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b/target/Config.in new file mode 100644 index 0000000..baae8d6 --- /dev/null +++ b/target/Config.in @@ -0,0 +1,198 @@ +source "tmp/.config-target.in" + +# Kernel/Hardware features + +config HAS_SPE_FPU + depends on powerpc + select HAS_FPU + bool + +config HAS_FPU + bool + +config AUDIO_SUPPORT + bool + +config GPIO_SUPPORT + bool + +config PCI_SUPPORT + select AUDIO_SUPPORT + bool + +config PCIE_SUPPORT + bool + +config PCMCIA_SUPPORT + bool + +config USB_SUPPORT + select AUDIO_SUPPORT + bool + +config USB_GADGET_SUPPORT + bool + +config RTC_SUPPORT + bool + +config BIG_ENDIAN + bool + +config USES_DEVICETREE + bool + +config USES_INITRAMFS + bool + +config USES_SQUASHFS + bool + +config USES_JFFS2 + bool + +config USES_JFFS2_NAND + bool + +config USES_EXT4 + bool + +config USES_TARGZ + bool + +config USES_CPIOGZ + bool + +config USES_UBIFS + bool + select NAND_SUPPORT + +config PROFILE_KCONFIG + bool + +config LOW_MEMORY_FOOTPRINT + bool + +config NOMMU + bool + +config HAS_MIPS16 + depends on (mips || mipsel || mips64 || mips64el) + bool + +config RFKILL_SUPPORT + bool + +config NAND_SUPPORT + bool + +config ARCH_64BIT + bool + +# Architecture selection + +config aarch64 + select ARCH_64BIT + bool + +config aarch64_be + select ARCH_64BIT + select BIG_ENDIAN + bool + +config arm + bool + +config armeb + select BIG_ENDIAN + bool + +config arm_v4 + bool + +config arm_v5 + bool + +config arm_v6 + bool + +config arm_v7 + bool + +config i386 + bool + +config i686 + bool + +config m68k + bool + +config mips + select BIG_ENDIAN + bool + +config mipsel + bool + +config mips64 + select BIG_ENDIAN + select ARCH_64BIT + bool + +config mips64el + select ARCH_64BIT + bool + +config powerpc + select BIG_ENDIAN + bool + +config powerpc64 + select BIG_ENDIAN + select ARCH_64BIT + bool + +config sh3 + bool + +config sh3eb + select BIG_ENDIAN + bool + +config sh4 + bool + +config sh4eb + select BIG_ENDIAN + bool + +config sparc + select BIG_ENDIAN + bool + +config x86_64 + select ARCH_64BIT + bool + +config ARCH + string + default "aarch64" if aarch64 + default "aarch64_be" if aarch64_be + default "arm" if arm + default "armeb" if armeb + default "i386" if i386 + default "i686" if i686 + default "m68k" if m68k + default "mips" if mips + default "mipsel" if mipsel + default "mips64" if mips64 + default "mips64el" if mips64el + default "powerpc" if powerpc + default "sh3" if sh3 + default "sh3eb" if sh3eb + default "sh4" if sh4 + default "sh4eb" if sh4eb + default "sparc" if sparc + default "x86_64" if x86_64 + diff --git a/target/Makefile b/target/Makefile new file mode 100644 index 0000000..cb68454 --- /dev/null +++ b/target/Makefile @@ -0,0 +1,21 @@ +# +# Copyright (C) 2007 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +curdir:=target + +$(curdir)/builddirs:=linux sdk imagebuilder toolchain +$(curdir)/builddirs-default:=linux +$(curdir)/builddirs-install:=linux $(if $(CONFIG_SDK),sdk) $(if $(CONFIG_IB),imagebuilder) $(if $(CONFIG_MAKE_TOOLCHAIN),toolchain) + +$(curdir)/imagebuilder/install:=$(curdir)/linux/install + +$(eval $(call stampfile,$(curdir),target,prereq,.config)) +$(eval $(call stampfile,$(curdir),target,compile,$(TMP_DIR)/.build)) +$(eval $(call stampfile,$(curdir),target,install,$(TMP_DIR)/.build)) + +$($(curdir)/stamp-install): $($(curdir)/stamp-compile) + +$(eval $(call subdir,$(curdir))) diff --git a/target/imagebuilder/Config.in b/target/imagebuilder/Config.in new file mode 100644 index 0000000..1bc4533 --- /dev/null +++ b/target/imagebuilder/Config.in @@ -0,0 +1,17 @@ +config IB + bool "Build the OpenWrt Image Builder" + depends on !PROFILE_KCONFIG + depends on !EXTERNAL_TOOLCHAIN + help + This is essentially a stripped-down version of the buildroot + with precompiled packages, kernel image and image building tools. + You can use it to generate custom images without compiling anything + +config IB_STANDALONE + bool "Include package repositories" + default y + depends on IB + help + Disabling this option will cause the ImageBuilder to embed only + toolchain and kmod packages while all other ipk archives will be + fetched from online repositories. diff --git a/target/imagebuilder/Makefile b/target/imagebuilder/Makefile new file mode 100644 index 0000000..7f48ed8 --- /dev/null +++ b/target/imagebuilder/Makefile @@ -0,0 +1,87 @@ +# +# Copyright (C) 2006-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/host.mk +include $(INCLUDE_DIR)/version.mk +include $(INCLUDE_DIR)/feeds.mk + +override MAKEFLAGS= + +IB_NAME:=OpenWrt-ImageBuilder-$(if $(CONFIG_VERSION_FILENAMES),$(VERSION_NUMBER)-)$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET)).$(HOST_OS)-$(HOST_ARCH) +PKG_BUILD_DIR:=$(BUILD_DIR)/$(IB_NAME) +IB_KDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(KERNEL_BUILD_DIR)) +IB_LDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(LINUX_DIR)) +IB_DTSDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(LINUX_DIR))/arch/$(ARCH)/boot/dts/ + +all: compile + +$(BIN_DIR)/$(IB_NAME).tar.bz2: clean + rm -rf $(PKG_BUILD_DIR) + mkdir -p $(IB_KDIR) $(IB_LDIR) $(PKG_BUILD_DIR)/staging_dir/host/lib \ + $(PKG_BUILD_DIR)/target $(PKG_BUILD_DIR)/scripts $(IB_DTSDIR) + -cp $(TOPDIR)/.config $(PKG_BUILD_DIR)/.config + $(CP) \ + $(INCLUDE_DIR) $(SCRIPT_DIR) \ + $(TOPDIR)/rules.mk \ + ./files/Makefile \ + ./files/repositories.conf \ + $(TMP_DIR)/.targetinfo \ + $(TMP_DIR)/.packageinfo \ + $(PKG_BUILD_DIR)/ + +ifeq ($(CONFIG_IB_STANDALONE),) + echo '## Remote package repositories' >> $(PKG_BUILD_DIR)/repositories.conf + $(call FeedSourcesAppend,$(PKG_BUILD_DIR)/repositories.conf) +endif + + echo '' >> $(PKG_BUILD_DIR)/repositories.conf + echo '## This is the local package repository, do not remove!' >> $(PKG_BUILD_DIR)/repositories.conf + echo 'src imagebuilder file:packages' >> $(PKG_BUILD_DIR)/repositories.conf + + $(VERSION_SED) $(PKG_BUILD_DIR)/repositories.conf + +ifeq ($(CONFIG_IB_STANDALONE),) + (cd $(PACKAGE_DIR); $(FIND) -type f -name 'libc_*.ipk' -or -name 'kernel_*.ipk' -or -name 'kmod-*.ipk') | \ + while read path; do \ + mkdir -p "$(PKG_BUILD_DIR)/packages/$${path%/*}"; \ + cp "$(PACKAGE_DIR)/$$path" "$(PKG_BUILD_DIR)/packages/$$path"; \ + done +else + $(CP) $(PACKAGE_DIR) $(PKG_BUILD_DIR)/packages +endif + + $(CP) $(TOPDIR)/target/linux $(PKG_BUILD_DIR)/target/ + if [ -d $(TOPDIR)/staging_dir/host/lib/grub ]; then \ + $(CP) $(TOPDIR)/staging_dir/host/lib/grub/ $(PKG_BUILD_DIR)/staging_dir/host/lib; \ + fi + rm -rf \ + $(PKG_BUILD_DIR)/target/linux/*/files{,-*} \ + $(PKG_BUILD_DIR)/target/linux/*/patches{,-*} + -cp $(KERNEL_BUILD_DIR)/* $(IB_KDIR)/ # don't copy subdirectories here + -cp $(LINUX_DIR)/.config $(IB_LDIR)/ + -$(SCRIPT_DIR)/bundle-libraries.sh $(IB_LDIR)/scripts/dtc \ + $(LINUX_DIR)/scripts/dtc/dtc + if [ -d $(LINUX_DIR)/arch/$(ARCH)/boot/dts ]; then \ + $(CP) $(LINUX_DIR)/arch/$(ARCH)/boot/dts/* $(IB_DTSDIR); \ + fi + $(SED) 's,^# REVISION:=.*,REVISION:=$(REVISION),g' $(PKG_BUILD_DIR)/include/version.mk + find $(PKG_BUILD_DIR) -name CVS -o -name .git -o -name .svn \ + | $(XARGS) rm -rf + find $(STAGING_DIR_HOST)/bin -maxdepth 1 -type f -perm -u=x \ + | $(XARGS) $(SCRIPT_DIR)/bundle-libraries.sh $(PKG_BUILD_DIR)/staging_dir/host/bin/ + STRIP=sstrip $(SCRIPT_DIR)/rstrip.sh $(PKG_BUILD_DIR)/staging_dir/host/bin/ + $(TAR) -cf - -C $(BUILD_DIR) $(IB_NAME) | bzip2 -c > $@ + +download: +prepare: +compile: $(BIN_DIR)/$(IB_NAME).tar.bz2 +install: compile + +clean: FORCE + rm -rf $(PKG_BUILD_DIR) $(BIN_DIR)/$(IB_NAME).tar.bz2 diff --git a/target/imagebuilder/files/Makefile b/target/imagebuilder/files/Makefile new file mode 100644 index 0000000..f612ea9 --- /dev/null +++ b/target/imagebuilder/files/Makefile @@ -0,0 +1,203 @@ +# Makefile for OpenWrt +# +# Copyright (C) 2007-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +TOPDIR:=${CURDIR} +LC_ALL:=C +LANG:=C +export TOPDIR LC_ALL LANG +export OPENWRT_VERBOSE=s +all: help + +include $(TOPDIR)/include/host.mk + +ifneq ($(OPENWRT_BUILD),1) + override OPENWRT_BUILD=1 + export OPENWRT_BUILD +endif + +include rules.mk +include $(INCLUDE_DIR)/debug.mk +include $(INCLUDE_DIR)/depends.mk + +include $(INCLUDE_DIR)/version.mk +export REVISION + +define Helptext +Available Commands: + help: This help text + info: Show a list of available target profiles + clean: Remove images and temporary build files + image: Build an image (see below for more information). + +Building images: + By default 'make image' will create an image with the default + target profile and package set. You can use the following parameters + to change that: + + make image PROFILE="" # override the default target profile + make image PACKAGES=" [ [ ...]]" # include extra packages + make image FILES="" # include extra files from + make image BIN_DIR="" # alternative output directory for the images + +endef +$(eval $(call shexport,Helptext)) + +help: FORCE + echo "$$$(call shvar,Helptext)" + + +# override variables from rules.mk +PACKAGE_DIR:=$(TOPDIR)/packages +LISTS_DIR:=$(subst $(space),/,$(patsubst %,..,$(subst /,$(space),$(TARGET_DIR))))$(DL_DIR) +OPKG:= \ + IPKG_NO_SCRIPT=1 \ + IPKG_TMP="$(TMP_DIR)/ipkgtmp" \ + IPKG_INSTROOT="$(TARGET_DIR)" \ + IPKG_CONF_DIR="$(TMP_DIR)" \ + IPKG_OFFLINE_ROOT="$(TARGET_DIR)" \ + $(STAGING_DIR_HOST)/bin/opkg \ + -f $(TOPDIR)/repositories.conf \ + --force-depends \ + --force-overwrite \ + --force-postinstall \ + --cache $(DL_DIR) \ + --lists-dir $(LISTS_DIR) \ + --offline-root $(TARGET_DIR) \ + --add-dest root:/ \ + --add-arch all:100 \ + --add-arch $(ARCH_PACKAGES):200 + +define Profile + $(eval $(call Profile/Default)) + $(eval $(call Profile/$(1))) + ifeq ($(USER_PROFILE),) + USER_PROFILE:=$(1) + endif + $(1)_NAME:=$(NAME) + $(1)_PACKAGES:=$(PACKAGES) + PROFILE_NAMES += $(1) + PROFILE_LIST += \ + echo '$(1):'; [ -z '$(NAME)' ] || echo ' $(NAME)'; echo ' Packages: $(PACKAGES)'; +endef + +include $(INCLUDE_DIR)/target.mk + +staging_dir/host/.prereq-build: include/prereq-build.mk + mkdir -p tmp + rm -f tmp/.host.mk + @$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f $(TOPDIR)/include/prereq-build.mk prereq 2>/dev/null || { \ + echo "Prerequisite check failed. Use FORCE=1 to override."; \ + false; \ + } + ifneq ($(realpath $(TOPDIR)/include/prepare.mk),) + @$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f $(TOPDIR)/include/prepare.mk prepare 2>/dev/null || { \ + echo "Preparation failed."; \ + false; \ + } + endif + touch $@ + +_call_info: FORCE + echo 'Current Target: "$(BOARD)$(if $(SUBTARGET), ($(BOARDNAME)))"' + echo 'Default Packages: $(DEFAULT_PACKAGES)' + echo 'Available Profiles:' + echo; $(PROFILE_LIST) + +BUILD_PACKAGES:=$(sort $(DEFAULT_PACKAGES) $(USER_PACKAGES) $($(USER_PROFILE)_PACKAGES) kernel) +# "-pkgname" in the package list means remove "pkgname" from the package list +BUILD_PACKAGES:=$(filter-out $(filter -%,$(BUILD_PACKAGES)) $(patsubst -%,%,$(filter -%,$(BUILD_PACKAGES))),$(BUILD_PACKAGES)) +PACKAGES:= + +_call_image: staging_dir/host/.prereq-build + echo 'Building images for $(BOARD)$(if $($(USER_PROFILE)_NAME), - $($(USER_PROFILE)_NAME))' + echo 'Packages: $(BUILD_PACKAGES)' + echo + rm -rf $(TARGET_DIR) + mkdir -p $(TARGET_DIR) $(BIN_DIR) $(TMP_DIR) $(DL_DIR) + if [ ! -f "$(PACKAGE_DIR)/Packages" ] || [ ! -f "$(PACKAGE_DIR)/Packages.gz" ] || [ "`find $(PACKAGE_DIR) -cnewer $(PACKAGE_DIR)/Packages.gz`" ]; then \ + echo "Package list missing or not up-to-date, generating it.";\ + $(MAKE) package_index; \ + else \ + mkdir -p $(TARGET_DIR)/tmp; \ + $(OPKG) update || true; \ + fi + $(MAKE) package_install +ifneq ($(USER_FILES),) + $(MAKE) copy_files +endif + $(MAKE) package_postinst + $(MAKE) build_image + +package_index: FORCE + @echo + @echo Building package index... + @mkdir -p $(TMP_DIR) $(TARGET_DIR)/tmp + (cd $(PACKAGE_DIR); $(SCRIPT_DIR)/ipkg-make-index.sh . > Packages && \ + gzip -9nc Packages > Packages.gz \ + ) >/dev/null 2>/dev/null + $(OPKG) update || true + +package_install: FORCE + @echo + @echo Installing packages... + $(OPKG) install $(firstword $(wildcard $(PACKAGE_DIR)/libc_*.ipk $(PACKAGE_DIR)/base/libc_*.ipk)) + $(OPKG) install $(firstword $(wildcard $(PACKAGE_DIR)/kernel_*.ipk $(PACKAGE_DIR)/base/kernel_*.ipk)) + $(OPKG) install $(BUILD_PACKAGES) + rm -f $(TARGET_DIR)/usr/lib/opkg/lists/* + +copy_files: FORCE + @echo + @echo Copying extra files + @$(call file_copy,$(USER_FILES)/*,$(TARGET_DIR)/) + +package_postinst: FORCE + @echo + @echo Cleaning up + @rm -f $(TARGET_DIR)/tmp/opkg.lock + @echo + @echo Activating init scripts + @mkdir -p $(TARGET_DIR)/etc/rc.d + @( \ + cd $(TARGET_DIR); \ + for script in ./usr/lib/opkg/info/*.postinst; do \ + IPKG_INSTROOT=$(TARGET_DIR) $$(which bash) $$script; \ + done || true \ + ) + rm -f $(TARGET_DIR)/usr/lib/opkg/info/*.postinst + $(if $(CONFIG_CLEAN_IPKG),rm -rf $(TARGET_DIR)/usr/lib/opkg) + +build_image: FORCE + @echo + @echo Building images... + $(NO_TRACE_MAKE) -C target/linux/$(BOARD)/image install TARGET_BUILD=1 IB=1 \ + $(if $(USER_PROFILE),PROFILE="$(USER_PROFILE)") + +clean: + rm -rf $(TMP_DIR) $(DL_DIR) $(TARGET_DIR) $(BIN_DIR) + + +info: + (unset PROFILE FILES PACKAGES MAKEFLAGS; $(MAKE) -s _call_info) + +image: +ifneq ($(PROFILE),) + ifeq ($(filter $(PROFILE),$(PROFILE_NAMES)),) + @echo 'Profile "$(PROFILE)" does not exist!' + @echo 'Use "make info" to get a list of available profile names.' + @exit 1 + endif +endif + (unset PROFILE FILES PACKAGES MAKEFLAGS; \ + $(MAKE) _call_image \ + $(if $(PROFILE),USER_PROFILE="$(PROFILE)") \ + $(if $(FILES),USER_FILES="$(FILES)") \ + $(if $(PACKAGES),USER_PACKAGES="$(PACKAGES)") \ + $(if $(BIN_DIR),BIN_DIR="$(BIN_DIR)")) + +.SILENT: help info image + diff --git a/target/imagebuilder/files/repositories.conf b/target/imagebuilder/files/repositories.conf new file mode 100644 index 0000000..8f1f27f --- /dev/null +++ b/target/imagebuilder/files/repositories.conf @@ -0,0 +1,4 @@ +## Place your custom repositories here, they must match the architecture and version. +# src/gz %n %U +# src custom file:///usr/src/openwrt/bin/%T/packages + diff --git a/target/linux/Makefile b/target/linux/Makefile new file mode 100644 index 0000000..f7bbdff --- /dev/null +++ b/target/linux/Makefile @@ -0,0 +1,13 @@ +# +# Copyright (C) 2006-2007 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/target.mk + +export TARGET_BUILD=1 + +prereq clean download prepare compile install menuconfig nconfig oldconfig update refresh: FORCE + @+$(NO_TRACE_MAKE) -C $(BOARD) $@ diff --git a/target/linux/adm5120/Makefile b/target/linux/adm5120/Makefile new file mode 100644 index 0000000..419c534 --- /dev/null +++ b/target/linux/adm5120/Makefile @@ -0,0 +1,24 @@ +# +# Copyright (C) 2007-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +BOARD:=adm5120 +BOARDNAME:=Infineon/ADMtek ADM5120 +FEATURES:=low_mem +SUBTARGETS:=router_le router_be rb1xx +INITRAMFS_EXTRA_FILES:= + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += admswconfig wpad-mini kmod-input-core \ + kmod-input-polldev kmod-input-gpio-keys-polled kmod-button-hotplug \ + kmod-leds-gpio kmod-ledtrig-adm5120-switch + +$(eval $(call BuildTarget)) diff --git a/target/linux/adm5120/base-files/etc/config/network b/target/linux/adm5120/base-files/etc/config/network new file mode 100644 index 0000000..87782f4 --- /dev/null +++ b/target/linux/adm5120/base-files/etc/config/network @@ -0,0 +1,39 @@ +#### VLAN configuration +config switch + option eth0 "0 1 2 3" + option eth1 "4" + + +#### Loopback configuration +config interface loopback + option ifname "lo" + option proto static + option ipaddr 127.0.0.1 + option netmask 255.0.0.0 + + +#### LAN configuration +config interface lan + option type bridge + option ifname "eth0" + option proto static + option ipaddr 192.168.1.1 + option netmask 255.255.255.0 + option ip6assign 60 + + +#### WAN configuration +config interface wan + option ifname "eth1" + option proto dhcp + + +#### WAN6 configuration +config interface wan6 + option ifname "eth1" + option proto dhcpv6 + + +#### Network global configuration +config globals globals + option ula_prefix auto diff --git a/target/linux/adm5120/base-files/etc/config/system b/target/linux/adm5120/base-files/etc/config/system new file mode 100644 index 0000000..ea54ca1 --- /dev/null +++ b/target/linux/adm5120/base-files/etc/config/system @@ -0,0 +1,40 @@ +config system + option hostname OpenWrt + option timezone UTC + +config timeserver ntp + list server 0.openwrt.pool.ntp.org + list server 1.openwrt.pool.ntp.org + list server 2.openwrt.pool.ntp.org + list server 3.openwrt.pool.ntp.org + +config led + option sysfs lan1 + option trigger port_state + option port_state link_act + +config led + option sysfs lan2 + option trigger port_state + option port_state link_act + +config led + option sysfs lan3 + option trigger port_state + option port_state link_act + +config led + option sysfs lan4 + option trigger port_state + option port_state link_act + +config led + option sysfs wan + option trigger port_state + option port_state link_act + +config led + option sysfs wlan + option trigger netdev + option dev wlan0 + diff --git a/target/linux/adm5120/base-files/etc/diag.sh b/target/linux/adm5120/base-files/etc/diag.sh new file mode 100644 index 0000000..08952bd --- /dev/null +++ b/target/linux/adm5120/base-files/etc/diag.sh @@ -0,0 +1,22 @@ +#!/bin/sh +# Copyright (C) 2007-2013 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/adm5120.sh + +set_state() { + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/adm5120/base-files/etc/inittab b/target/linux/adm5120/base-files/etc/inittab new file mode 100644 index 0000000..9f7c0ae --- /dev/null +++ b/target/linux/adm5120/base-files/etc/inittab @@ -0,0 +1,5 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +tts/0::askfirst:/bin/ash --login +ttyAM0::askfirst:/bin/ash --login +tty1::askfirst:/bin/ash --login diff --git a/target/linux/adm5120/base-files/lib/adm5120.sh b/target/linux/adm5120/base-files/lib/adm5120.sh new file mode 100755 index 0000000..496fc06 --- /dev/null +++ b/target/linux/adm5120/base-files/lib/adm5120.sh @@ -0,0 +1,53 @@ +#!/bin/sh +# +# Copyright (C) 2007 OpenWrt.org +# +# + +board_name="" +status_led="" +sys_mtd_part="" + +adm5120_detect() { + board_name=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /machine/ {print $2}' /proc/cpuinfo) + + case "$board_name" in + "Cellvision"*) + status_led="status" + sys_mtd_part="firmware" + ;; + "Compex"*) + status_led="diag" + case "$board_name" in + *-WRT) + sys_mtd_part="trx" + ;; + *) + sys_mtd_part="partition1" + ;; + esac + ;; + "Edimax"*) + status_led="power" + sys_mtd_part="firmware" + ;; + "Infineon"*) + sys_mtd_part="firmware" + ;; + "Mikrotik"*) + status_led="power" + ;; + "ZyXEL"*) + status_led="power" + sys_mtd_part="trx" + ;; + "EB-214A"*) + status_led="power" + sys_mtd_part="firmware" + ;; + *) + ;; + esac +} + +adm5120_detect diff --git a/target/linux/adm5120/base-files/lib/preinit/05_preinit_do_adm5120.sh b/target/linux/adm5120/base-files/lib/preinit/05_preinit_do_adm5120.sh new file mode 100644 index 0000000..4fca1e7 --- /dev/null +++ b/target/linux/adm5120/base-files/lib/preinit/05_preinit_do_adm5120.sh @@ -0,0 +1,7 @@ +#!/bin/sh + +do_adm5120() { + . /lib/adm5120.sh +} + +boot_hook_add preinit_main do_adm5120 diff --git a/target/linux/adm5120/base-files/lib/preinit/05_set_preinit_iface_adm5120 b/target/linux/adm5120/base-files/lib/preinit/05_set_preinit_iface_adm5120 new file mode 100644 index 0000000..ac2a7cb --- /dev/null +++ b/target/linux/adm5120/base-files/lib/preinit/05_set_preinit_iface_adm5120 @@ -0,0 +1,9 @@ +#!/bin/sh + +set_preinit_ifname() { + ifname=eth0 +} + +boot_hook_add preinit_main set_preinit_ifname + + diff --git a/target/linux/adm5120/base-files/lib/upgrade/platform.sh b/target/linux/adm5120/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..fab2b3d --- /dev/null +++ b/target/linux/adm5120/base-files/lib/upgrade/platform.sh @@ -0,0 +1,44 @@ +# +# Copyright (C) 2009-2010 OpenWrt.org +# + +. /lib/adm5120.sh + +PART_NAME="firmware" +RAMFS_COPY_DATA=/lib/adm5120.sh + +platform_check_image() { + local magic="$(get_magic_word "$1")" + + [ "$#" -gt 1 ] && return 1 + + case "$board_name" in + "ZyXEL"*|"Compex WP54 family") + # .trx files + [ "$magic" != "4844" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + *) + ;; + esac + + echo "Sysupgrade is not yet supported on $board_name." + return 1 +} + +platform_do_upgrade() { + PART_NAME="$sys_mtd_part" + default_do_upgrade "$ARGV" +} + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/adm5120/config-3.18 b/target/linux/adm5120/config-3.18 new file mode 100644 index 0000000..000424c --- /dev/null +++ b/target/linux/adm5120/config-3.18 @@ -0,0 +1,176 @@ +CONFIG_ADM5120=y +CONFIG_ADM5120_ENET=y +CONFIG_ADM5120_MACH_5GXI=y +CONFIG_ADM5120_MACH_BR_6104K=y +CONFIG_ADM5120_MACH_BR_6104KP=y +CONFIG_ADM5120_MACH_BR_61X4WG=y +CONFIG_ADM5120_MACH_CAS_771=y +CONFIG_ADM5120_MACH_EASY5120P_ATA=y +CONFIG_ADM5120_MACH_EASY5120_RT=y +CONFIG_ADM5120_MACH_EASY5120_WVOIP=y +CONFIG_ADM5120_MACH_EASY83000=y +CONFIG_ADM5120_MACH_EB_214A=y +CONFIG_ADM5120_MACH_NFS_101=y +CONFIG_ADM5120_MACH_NP27G=y +CONFIG_ADM5120_MACH_NP28G=y +CONFIG_ADM5120_MACH_PMUGW=y +# CONFIG_ADM5120_MACH_RB_11X is not set +# CONFIG_ADM5120_MACH_RB_133 is not set +# CONFIG_ADM5120_MACH_RB_133C is not set +# CONFIG_ADM5120_MACH_RB_150 is not set +# CONFIG_ADM5120_MACH_RB_153 is not set +# CONFIG_ADM5120_MACH_RB_192 is not set +CONFIG_ADM5120_MACH_WP54=y +CONFIG_ADM5120_OEM_CELLVISION=y +CONFIG_ADM5120_OEM_COMPEX=y +CONFIG_ADM5120_OEM_EDIMAX=y +CONFIG_ADM5120_OEM_GENERIC=y +CONFIG_ADM5120_OEM_INFINEON=y +# CONFIG_ADM5120_OEM_MIKROTIK is not set +CONFIG_ADM5120_OEM_MOTOROLA=y +CONFIG_ADM5120_OEM_OSBRIDGE=y +# CONFIG_ADM5120_OEM_ZYXEL is not set +CONFIG_ADM5120_SOC_BGA=y +CONFIG_ADM5120_WDT=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM_AMBA=y +CONFIG_BUILD_BIN2C=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyAM0,115200 rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IRQ_CPU=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_LEDS_TRIGGER_ADM5120_SWITCH is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MACHINE=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_ADM5120=y +CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC=y +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_MYLOADER_PARTS=y +CONFIG_MTD_TRXSPLIT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PCI=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2 +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SWAP is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/Kconfig b/target/linux/adm5120/files-3.18/arch/mips/adm5120/Kconfig new file mode 100644 index 0000000..be35a8f --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/Kconfig @@ -0,0 +1,197 @@ +if ADM5120 + +menu "ADM5120 Board selection" + +config ADM5120_MACH_CAS_771 + bool "Cellvision CAS-771/771W support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_CELLVISION + default y + +config ADM5120_MACH_NFS_101 + bool "Cellvision NFS-101U/101WU support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_CELLVISION + default y + +config ADM5120_MACH_NP27G + bool "Compex NP27G support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_COMPEX + default y + +config ADM5120_MACH_NP28G + bool "Compex NP28G support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_COMPEX + default y + +config ADM5120_MACH_WP54 + bool "Compex WP54 family support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_COMPEX + default y + +config ADM5120_MACH_EB_214A + bool "EB-214A support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_GENERIC + default y + +config ADM5120_MACH_BR_6104K + bool "Edimax BR-6104K support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_OEM_EDIMAX + default y + +config ADM5120_MACH_BR_6104KP + bool "Edimax BR-6104KP support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_OEM_EDIMAX + default y + +config ADM5120_MACH_BR_61X4WG + bool "Edimax BR-6104WG/6114WG support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_EDIMAX + default y + +config ADM5120_MACH_EASY5120_RT + bool "Infineon EASY 5120-RT Reference Board support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_INFINEON + default y + +config ADM5120_MACH_EASY5120_WVOIP + bool "Infineon EASY 5120-WVoIP Reference Board support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_INFINEON + default y + +config ADM5120_MACH_EASY5120P_ATA + bool "Infineon EASY 5120P-ATA Reference Board support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_OEM_INFINEON + default y + +config ADM5120_MACH_EASY83000 + bool "Infineon EASY 83000 Reference Board support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_OEM_INFINEON + default y + +config ADM5120_MACH_RB_11X + bool "MikroTik RouterBOARD 111/112 support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_MIKROTIK + default y + +config ADM5120_MACH_RB_133 + bool "MikroTik RouterBOARD 133 support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_MIKROTIK + default y + +config ADM5120_MACH_RB_133C + bool "MikroTik RouterBOARD 133C support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_MIKROTIK + default y + +config ADM5120_MACH_RB_150 + bool "MikroTik RouterBOARD 150 support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_OEM_MIKROTIK + default y + +config ADM5120_MACH_RB_153 + bool "MikroTik RouterBOARD 153 support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_MIKROTIK + default y + +config ADM5120_MACH_RB_192 + bool "MikroTik RouterBOARD 192 support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_MIKROTIK + default y + +config ADM5120_MACH_PMUGW + bool "Motorola Powerline MU Gateway" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_MOTOROLA + default y + +config ADM5120_MACH_5GXI + bool "OSBRiDGE 5GXi/5XLi support" + depends on CPU_LITTLE_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_OSBRIDGE + default y + +config ADM5120_MACH_P_334WT + bool "ZyXEL Prestige 334WT" + depends on CPU_BIG_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_ZYXEL + default y + +config ADM5120_MACH_P_335 + bool "ZyXEL Prestige 335/335WT" + depends on CPU_BIG_ENDIAN + select ADM5120_SOC_BGA + select ADM5120_OEM_ZYXEL + default y + +endmenu + +config ADM5120_SOC_BGA + select HW_HAS_PCI + def_bool n + +config ADM5120_OEM_CELLVISION + def_bool n + +config ADM5120_OEM_COMPEX + def_bool n + +config ADM5120_OEM_EDIMAX + def_bool n + +config ADM5120_OEM_GENERIC + def_bool n + +config ADM5120_OEM_INFINEON + def_bool n + +config ADM5120_OEM_MIKROTIK + def_bool n + +config ADM5120_OEM_MOTOROLA + def_bool n + +config ADM5120_OEM_OSBRIDGE + def_bool n + +config ADM5120_OEM_ZYXEL + def_bool n + +config ARM_AMBA + def_bool y + +endif diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/Platform b/target/linux/adm5120/files-3.18/arch/mips/adm5120/Platform new file mode 100644 index 0000000..0c9edf2 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/Platform @@ -0,0 +1,19 @@ +# +# Infineon/ADMtek ADM5120 +# + +platform-$(CONFIG_ADM5120) += adm5120/common/ + +platform-$(CONFIG_ADM5120_OEM_CELLVISION) += adm5120/cellvision/ +platform-$(CONFIG_ADM5120_OEM_COMPEX) += adm5120/compex/ +platform-$(CONFIG_ADM5120_OEM_EDIMAX) += adm5120/edimax/ +platform-$(CONFIG_ADM5120_OEM_GENERIC) += adm5120/generic/ +platform-$(CONFIG_ADM5120_OEM_INFINEON) += adm5120/infineon/ +platform-$(CONFIG_ADM5120_OEM_MIKROTIK) += adm5120/mikrotik/ +platform-$(CONFIG_ADM5120_OEM_MOTOROLA) += adm5120/motorola/ +platform-$(CONFIG_ADM5120_OEM_OSBRIDGE) += adm5120/osbridge/ +platform-$(CONFIG_ADM5120_OEM_ZYXEL) += adm5120/zyxel/ + +cflags-$(CONFIG_ADM5120) += -I$(srctree)/arch/mips/include/asm/mach-adm5120 +libs-$(CONFIG_ADM5120) += arch/mips/adm5120/prom/ +load-$(CONFIG_ADM5120) += 0xffffffff80001000 diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/Makefile new file mode 100644 index 0000000..a949fc9 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/Makefile @@ -0,0 +1,4 @@ +obj-y += cellvision.o + +obj-$(CONFIG_ADM5120_MACH_CAS_771) += cas-771.o +obj-$(CONFIG_ADM5120_MACH_NFS_101) += nfs-101.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cas-771.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cas-771.c new file mode 100644 index 0000000..5033e02 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cas-771.c @@ -0,0 +1,37 @@ +/* + * Cellvision/SparkLAN CAS-771/771W support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cellvision.h" + +static struct adm5120_pci_irq cas771_pci_irqs[] __initdata = { + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0), + PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1), + PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2) +}; + +static struct gpio_led cas771_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_PIN0, "cam_flash", NULL), + /* GPIO PIN3 is the reset */ + GPIO_LED_STD(ADM5120_GPIO_PIN6, "access", NULL), + GPIO_LED_STD(ADM5120_GPIO_P0L1, "status", NULL), + GPIO_LED_STD(ADM5120_GPIO_P0L2, "diag", NULL), +}; + +static void __init cas771_setup(void) +{ + cas7xx_setup(); + adm5120_add_device_gpio_leds(ARRAY_SIZE(cas771_gpio_leds), + cas771_gpio_leds); + adm5120_pci_set_irq_map(ARRAY_SIZE(cas771_pci_irqs), cas771_pci_irqs); +} + +MIPS_MACHINE(MACH_ADM5120_CAS771, "CAS-771", "Cellvision CAS-771/771W", + cas771_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cellvision.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cellvision.c new file mode 100644 index 0000000..a7cedf0 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cellvision.c @@ -0,0 +1,147 @@ +/* + * Cellvision/SparkLAN boards + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cellvision.h" + +#include + +#define CELLVISION_GPIO_FLASH_A20 ADM5120_GPIO_PIN5 +#define CELLVISION_GPIO_DEV_MASK (1 << CELLVISION_GPIO_FLASH_A20) + +#define CELLVISION_CONFIG_OFFSET 0x8000 +#define CELLVISION_CONFIG_SIZE 0x1000 + +static struct mtd_partition cas6xx_partitions[] = { + { + .name = "admboot", + .offset = 0, + .size = 32*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "config", + .offset = MTDPART_OFS_APPEND, + .size = 32*1024, + } , { + .name = "nvfs1", + .offset = MTDPART_OFS_APPEND, + .size = 64*1024, + } , { + .name = "nvfs2", + .offset = MTDPART_OFS_APPEND, + .size = 64*1024, + } , { + .name = "firmware", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct mtd_partition cas7xx_partitions[] = { + { + .name = "admboot", + .offset = 0, + .size = 32*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "config", + .offset = MTDPART_OFS_APPEND, + .size = 32*1024, + } , { + .name = "nvfs", + .offset = MTDPART_OFS_APPEND, + .size = 128*1024, + } , { + .name = "firmware", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static void switch_bank_gpio5(unsigned bank) +{ + switch (bank) { + case 0: + gpio_set_value(CELLVISION_GPIO_FLASH_A20, 0); + break; + case 1: + gpio_set_value(CELLVISION_GPIO_FLASH_A20, 1); + break; + } +} + +static void __init cellvision_flash_setup(void) +{ + /* setup flash A20 line */ + gpio_request(CELLVISION_GPIO_FLASH_A20, NULL); + gpio_direction_output(CELLVISION_GPIO_FLASH_A20, 0); + + adm5120_flash0_data.switch_bank = switch_bank_gpio5; + adm5120_add_device_flash(0); +} + +void __init cellvision_mac_setup(void) +{ + u8 mac_base[6]; + int err; + + err = admboot_get_mac_base(CELLVISION_CONFIG_OFFSET, + CELLVISION_CONFIG_SIZE, mac_base); + + if ((err) || !is_valid_ether_addr(mac_base)) + random_ether_addr(mac_base); + + adm5120_setup_eth_macs(mac_base); +} + +void __init cas6xx_flash_setup(void) +{ + adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas6xx_partitions); + adm5120_flash0_data.parts = cas6xx_partitions; + + cellvision_flash_setup(); +} + +void __init cas7xx_flash_setup(void) +{ + adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas7xx_partitions); + adm5120_flash0_data.parts = cas7xx_partitions; + + cellvision_flash_setup(); +} + +void __init cas6xx_setup(void) +{ + cas6xx_flash_setup(); + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + adm5120_add_device_switch(1, NULL); +} + +MIPS_MACHINE(MACH_ADM5120_CAS630, "CAS-630", "Cellvision CAS-630/630W", + cas6xx_setup); +MIPS_MACHINE(MACH_ADM5120_CAS670, "CAS-670", "Cellvision CAS-670/670W", + cas6xx_setup); + +void __init cas7xx_setup(void) +{ + cas7xx_flash_setup(); + cellvision_mac_setup(); + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + adm5120_add_device_switch(1, NULL); +} + +MIPS_MACHINE(MACH_ADM5120_CAS700, "CAS-700", "Cellvision CAS-700/700W", + cas7xx_setup); +MIPS_MACHINE(MACH_ADM5120_CAS790, "CAS-790", "Cellvision CAS-790", + cas7xx_setup); +MIPS_MACHINE(MACH_ADM5120_CAS861, "CAS-861", "Cellvision CAS-861/861W", + cas7xx_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cellvision.h b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cellvision.h new file mode 100644 index 0000000..2b55ebf --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/cellvision.h @@ -0,0 +1,28 @@ +/* + * Cellvision/SparkLAN boards + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +extern void cellvision_mac_setup(void) __init; + +extern void cas6xx_flash_setup(void) __init; +extern void cas7xx_flash_setup(void) __init; +extern void cas6xx_setup(void) __init; +extern void cas7xx_setup(void) __init; diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/nfs-101.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/nfs-101.c new file mode 100644 index 0000000..7d214c0 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/cellvision/nfs-101.c @@ -0,0 +1,47 @@ +/* + * Cellvision/SparkLAN NFS-101U/WU support + * + * Copyright (C) 2007-2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cellvision.h" + +static struct adm5120_pci_irq nfs101_pci_irqs[] __initdata = { + /* miniPCI slot */ + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0), + + /* ALi USB controller */ + PCIIRQ(3, 0, 2, ADM5120_IRQ_PCI2), + PCIIRQ(3, 3, 1, ADM5120_IRQ_PCI1), + + /* NEC USB controller */ + PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1), + PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI2), + PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2), +}; + +static u8 nfs101_vlans[6] __initdata = { + /* FIXME: not tested */ + 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static void __init nfs101_setup(void) +{ + cas6xx_flash_setup(); + cellvision_mac_setup(); + + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + adm5120_add_device_switch(1, nfs101_vlans); + + adm5120_pci_set_irq_map(ARRAY_SIZE(nfs101_pci_irqs), + nfs101_pci_irqs); +} + +MIPS_MACHINE(MACH_ADM5120_NFS101U, "NFS-101U", "Cellvision NFS-101U/101WU", + nfs101_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/Makefile new file mode 100644 index 0000000..8d302c5 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for the Infineon/ADMtek ADM5120 SoC specific parts of the kernel +# + +obj-y := adm5120.o setup.o prom.o irq.o memory.o clock.o \ + gpio.o platform.o + +obj-$(CONFIG_EARLY_PRINTK) += early-printk.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/adm5120.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/adm5120.c new file mode 100644 index 0000000..2838834 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/adm5120.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include + +#include +#include +#include + +unsigned int adm5120_product_code; +unsigned int adm5120_revision; +unsigned int adm5120_package; +unsigned int adm5120_nand_boot; +unsigned long adm5120_speed; + +/* + * CPU settings detection + */ +#define CODE_GET_PC(c) ((c) & CODE_PC_MASK) +#define CODE_GET_REV(c) (((c) >> CODE_REV_SHIFT) & CODE_REV_MASK) +#define CODE_GET_PK(c) (((c) >> CODE_PK_SHIFT) & CODE_PK_MASK) +#define CODE_GET_CLKS(c) (((c) >> CODE_CLKS_SHIFT) & CODE_CLKS_MASK) +#define CODE_GET_NAB(c) (((c) & CODE_NAB) != 0) + +void adm5120_ndelay(u32 ns) +{ + u32 t; + + SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT); + SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); + + t = (ns+640) / 640; + t &= TIMER_PERIOD_MASK; + SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE); + + /* wait until the timer expires */ + do { + t = SW_READ_REG(SWITCH_REG_TIMER_INT); + } while ((t & TIMER_INT_TOS) == 0); + + /* leave the timer disabled */ + SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT); + SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); +} + +void __init adm5120_soc_init(void) +{ + u32 code; + u32 clks; + + code = SW_READ_REG(SWITCH_REG_CODE); + + adm5120_product_code = CODE_GET_PC(code); + adm5120_revision = CODE_GET_REV(code); + adm5120_package = (CODE_GET_PK(code) == CODE_PK_BGA) ? + ADM5120_PACKAGE_BGA : ADM5120_PACKAGE_PQFP; + adm5120_nand_boot = CODE_GET_NAB(code); + + clks = CODE_GET_CLKS(code); + adm5120_speed = ADM5120_SPEED_175; + if (clks & 1) + adm5120_speed += 25000000; + if (clks & 2) + adm5120_speed += 50000000; +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/clock.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/clock.c new file mode 100644 index 0000000..52ae64c --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/clock.c @@ -0,0 +1,65 @@ +/* + * ADM5120 minimal CLK API implementation + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was based on the CLK API implementation in: + * arch/mips/tx4938/toshiba_rbtx4938/setup.c + * Copyright (C) 2000-2001 Toshiba Corporation + * 2003-2005 (c) MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +struct clk { + unsigned long rate; +}; + +static struct clk uart_clk = { + .rate = ADM5120_UART_CLOCK +}; + +struct clk *clk_get(struct device *dev, const char *id) +{ + const char *name = dev_name(dev); + + if (!strcmp(name, "apb:uart0") || !strcmp(name, "apb:uart1")) + return &uart_clk; + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/early-printk.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/early-printk.c new file mode 100644 index 0000000..d900712 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/early-printk.c @@ -0,0 +1,31 @@ +/* + * ADM5120 specific early printk support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include + +#include +#include +#include + +#define UART_READ(r) \ + __raw_readl((void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r))) +#define UART_WRITE(r, v) \ + __raw_writel((v), (void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r))) + +void __init prom_putchar(char ch) +{ + while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0) + ; + UART_WRITE(UART_REG_DATA, ch); + while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0) + ; +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/gpio.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/gpio.c new file mode 100644 index 0000000..461ea15 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/gpio.c @@ -0,0 +1,328 @@ +/* + * ADM5120 generic GPIO API support via GPIOLIB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define GPIO_REG(r) (void __iomem *)(KSEG1ADDR(ADM5120_SWITCH_BASE) + r) + +struct gpio1_desc { + void __iomem *reg; /* register address */ + u8 iv_shift; /* shift amount for input bit */ + u8 mode_shift; /* shift amount for mode bits */ +}; + +#define GPIO1_DESC(p, l) { \ + .reg = GPIO_REG(SWITCH_REG_PORT0_LED + ((p) * 4)), \ + .iv_shift = LED0_IV_SHIFT + (l), \ + .mode_shift = (l) * 4 \ + } + +static struct gpio1_desc gpio1_table[15] = { + GPIO1_DESC(0, 0), GPIO1_DESC(0, 1), GPIO1_DESC(0, 2), + GPIO1_DESC(1, 0), GPIO1_DESC(1, 1), GPIO1_DESC(1, 2), + GPIO1_DESC(2, 0), GPIO1_DESC(2, 1), GPIO1_DESC(2, 2), + GPIO1_DESC(3, 0), GPIO1_DESC(3, 1), GPIO1_DESC(3, 2), + GPIO1_DESC(4, 0), GPIO1_DESC(4, 1), GPIO1_DESC(4, 2) +}; + +static u32 gpio_conf2; + +int adm5120_gpio_to_irq(unsigned gpio) +{ + int ret; + + switch (gpio) { + case ADM5120_GPIO_PIN2: + ret = ADM5120_IRQ_GPIO2; + break; + case ADM5120_GPIO_PIN4: + ret = ADM5120_IRQ_GPIO4; + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} +EXPORT_SYMBOL(adm5120_gpio_to_irq); + +int adm5120_irq_to_gpio(unsigned irq) +{ + int ret; + + switch (irq) { + case ADM5120_IRQ_GPIO2: + ret = ADM5120_GPIO_PIN2; + break; + case ADM5120_IRQ_GPIO4: + ret = ADM5120_GPIO_PIN4; + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} +EXPORT_SYMBOL(adm5120_irq_to_gpio); + +/* + * Helpers for GPIO lines in GPIO_CONF0 register + */ +#define PIN_IM(p) ((1 << GPIO_CONF0_IM_SHIFT) << p) +#define PIN_IV(p) ((1 << GPIO_CONF0_IV_SHIFT) << p) +#define PIN_OE(p) ((1 << GPIO_CONF0_OE_SHIFT) << p) +#define PIN_OV(p) ((1 << GPIO_CONF0_OV_SHIFT) << p) + +int __adm5120_gpio0_get_value(unsigned offset) +{ + void __iomem **reg; + u32 t; + + reg = GPIO_REG(SWITCH_REG_GPIO_CONF0); + + t = __raw_readl(reg); + if ((t & PIN_IM(offset)) != 0) + t &= PIN_IV(offset); + else + t &= PIN_OV(offset); + + return (t) ? 1 : 0; +} +EXPORT_SYMBOL(__adm5120_gpio0_get_value); + +void __adm5120_gpio0_set_value(unsigned offset, int value) +{ + void __iomem **reg; + u32 t; + + reg = GPIO_REG(SWITCH_REG_GPIO_CONF0); + + t = __raw_readl(reg); + if (value == 0) + t &= ~(PIN_OV(offset)); + else + t |= PIN_OV(offset); + + __raw_writel(t, reg); +} +EXPORT_SYMBOL(__adm5120_gpio0_set_value); + +static int adm5120_gpio0_get_value(struct gpio_chip *chip, unsigned offset) +{ + return __adm5120_gpio0_get_value(offset); +} + +static void adm5120_gpio0_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + __adm5120_gpio0_set_value(offset, value); +} + +static int adm5120_gpio0_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + void __iomem **reg; + u32 t; + + reg = GPIO_REG(SWITCH_REG_GPIO_CONF0); + + t = __raw_readl(reg); + t &= ~(PIN_OE(offset)); + t |= PIN_IM(offset); + __raw_writel(t, reg); + + return 0; +} + +static int adm5120_gpio0_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + void __iomem **reg; + u32 t; + + reg = GPIO_REG(SWITCH_REG_GPIO_CONF0); + + t = __raw_readl(reg); + t &= ~(PIN_IM(offset) | PIN_OV(offset)); + t |= PIN_OE(offset); + + if (value) + t |= PIN_OV(offset); + + __raw_writel(t, reg); + + return 0; +} + +static struct gpio_chip adm5120_gpio0_chip = { + .label = "adm5120 gpio0", + .get = adm5120_gpio0_get_value, + .set = adm5120_gpio0_set_value, + .direction_input = adm5120_gpio0_direction_input, + .direction_output = adm5120_gpio0_direction_output, + .base = ADM5120_GPIO_PIN0, + .ngpio = ADM5120_GPIO_PIN7 - ADM5120_GPIO_PIN0 + 1, +}; + +int __adm5120_gpio1_get_value(unsigned offset) +{ + void __iomem **reg; + u32 t, m; + + reg = gpio1_table[offset].reg; + + t = __raw_readl(reg); + m = (t >> gpio1_table[offset].mode_shift) & LED_MODE_MASK; + if (m == LED_MODE_INPUT) + return (t >> gpio1_table[offset].iv_shift) & 1; + + if (m == LED_MODE_OUT_LOW) + return 0; + + return 1; +} +EXPORT_SYMBOL(__adm5120_gpio1_get_value); + +void __adm5120_gpio1_set_value(unsigned offset, int value) +{ + void __iomem **reg; + u32 t, s; + + reg = gpio1_table[offset].reg; + s = gpio1_table[offset].mode_shift; + + t = __raw_readl(reg); + t &= ~(LED_MODE_MASK << s); + + switch (value) { + case ADM5120_GPIO_LOW: + t |= (LED_MODE_OUT_LOW << s); + break; + case ADM5120_GPIO_FLASH: + case ADM5120_GPIO_LINK: + case ADM5120_GPIO_SPEED: + case ADM5120_GPIO_DUPLEX: + case ADM5120_GPIO_ACT: + case ADM5120_GPIO_COLL: + case ADM5120_GPIO_LINK_ACT: + case ADM5120_GPIO_DUPLEX_COLL: + case ADM5120_GPIO_10M_ACT: + case ADM5120_GPIO_100M_ACT: + t |= ((value & LED_MODE_MASK) << s); + break; + default: + t |= (LED_MODE_OUT_HIGH << s); + break; + } + + __raw_writel(t, reg); +} +EXPORT_SYMBOL(__adm5120_gpio1_set_value); + +static int adm5120_gpio1_get_value(struct gpio_chip *chip, unsigned offset) +{ + return __adm5120_gpio1_get_value(offset); +} + +static void adm5120_gpio1_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + __adm5120_gpio1_set_value(offset, value); +} + +static int adm5120_gpio1_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + void __iomem **reg; + u32 t; + + reg = gpio1_table[offset].reg; + t = __raw_readl(reg); + t &= ~(LED_MODE_MASK << gpio1_table[offset].mode_shift); + __raw_writel(t, reg); + + return 0; +} + +static int adm5120_gpio1_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + __adm5120_gpio1_set_value(offset, value); + return 0; +} + +static struct gpio_chip adm5120_gpio1_chip = { + .label = "adm5120 gpio1", + .get = adm5120_gpio1_get_value, + .set = adm5120_gpio1_set_value, + .direction_input = adm5120_gpio1_direction_input, + .direction_output = adm5120_gpio1_direction_output, + .base = ADM5120_GPIO_P0L0, + .ngpio = ADM5120_GPIO_P4L2 - ADM5120_GPIO_P0L0 + 1, +}; + +void __init adm5120_gpio_csx0_enable(void) +{ + gpio_conf2 |= GPIO_CONF2_CSX0; + SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2); + + gpio_request(ADM5120_GPIO_PIN1, "CSX0"); +} + +void __init adm5120_gpio_csx1_enable(void) +{ + gpio_conf2 |= GPIO_CONF2_CSX1; + SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2); + + gpio_request(ADM5120_GPIO_PIN3, "CSX1"); +} + +void __init adm5120_gpio_ew_enable(void) +{ + gpio_conf2 |= GPIO_CONF2_EW; + SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2); + + gpio_request(ADM5120_GPIO_PIN0, "EW"); +} + +void __init adm5120_gpio_init(void) +{ + int err; + + SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2); + + if (adm5120_package_pqfp()) + adm5120_gpio0_chip.ngpio = 4; + + err = gpiochip_add(&adm5120_gpio0_chip); + if (err) + panic("cannot add ADM5120 GPIO0 chip, error=%d", err); + + err = gpiochip_add(&adm5120_gpio1_chip); + if (err) + panic("cannot add ADM5120 GPIO1 chip, error=%d", err); + +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/irq.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/irq.c new file mode 100644 index 0000000..a26e651 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/irq.c @@ -0,0 +1,171 @@ +/* + * ADM5120 specific interrupt handlers + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +static void adm5120_intc_irq_unmask(struct irq_data *d); +static void adm5120_intc_irq_mask(struct irq_data *d); +static int adm5120_intc_irq_set_type(struct irq_data *d, unsigned int flow_type); + +static inline void intc_write_reg(unsigned int reg, u32 val) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE); + + __raw_writel(val, base + reg); +} + +static inline u32 intc_read_reg(unsigned int reg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE); + + return __raw_readl(base + reg); +} + +static struct irq_chip adm5120_intc_irq_chip = { + .name = "INTC", + .irq_unmask = adm5120_intc_irq_unmask, + .irq_mask = adm5120_intc_irq_mask, + .irq_mask_ack = adm5120_intc_irq_mask, + .irq_set_type = adm5120_intc_irq_set_type +}; + +static struct irqaction adm5120_intc_irq_action = { + .handler = no_action, + .name = "cascade [INTC]" +}; + +static void adm5120_intc_irq_unmask(struct irq_data *d) +{ + intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << (d->irq - ADM5120_INTC_IRQ_BASE)); +} + +static void adm5120_intc_irq_mask(struct irq_data *d) +{ + intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << (d->irq - ADM5120_INTC_IRQ_BASE)); +} + +static int adm5120_intc_irq_set_type(struct irq_data *d, unsigned int flow_type) +{ + unsigned int irq = d->irq; + unsigned int sense; + unsigned long mode; + int err = 0; + + sense = flow_type & (IRQ_TYPE_SENSE_MASK); + switch (sense) { + case IRQ_TYPE_NONE: + case IRQ_TYPE_LEVEL_HIGH: + break; + case IRQ_TYPE_LEVEL_LOW: + switch (irq) { + case ADM5120_IRQ_GPIO2: + case ADM5120_IRQ_GPIO4: + break; + default: + err = -EINVAL; + break; + } + break; + default: + err = -EINVAL; + break; + } + + if (err) + return err; + + switch (irq) { + case ADM5120_IRQ_GPIO2: + case ADM5120_IRQ_GPIO4: + mode = intc_read_reg(INTC_REG_INT_MODE); + if (sense == IRQ_TYPE_LEVEL_LOW) + mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE)); + else + mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE)); + + intc_write_reg(INTC_REG_INT_MODE, mode); + break; + } + + return 0; +} + +static void adm5120_intc_irq_dispatch(void) +{ + unsigned long status; + int irq; + + status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL; + if (status) { + irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1; + do_IRQ(irq); + } else + spurious_interrupt(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned long pending; + + pending = read_c0_status() & read_c0_cause() & ST0_IM; + + if (pending & STATUSF_IP7) + do_IRQ(ADM5120_IRQ_COUNTER); + else if (pending & STATUSF_IP2) + adm5120_intc_irq_dispatch(); + else + spurious_interrupt(); +} + +#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED) +static void __init adm5120_intc_irq_init(void) +{ + int i; + + /* disable all interrupts */ + intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL); + + /* setup all interrupts to generate IRQ instead of FIQ */ + intc_write_reg(INTC_REG_INT_MODE, 0); + + /* set active level for all external interrupts to HIGH */ + intc_write_reg(INTC_REG_INT_LEVEL, 0); + + /* disable usage of the TEST_SOURCE register */ + intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0); + + for (i = ADM5120_INTC_IRQ_BASE; + i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST; + i++) { + irq_set_chip_and_handler(i, &adm5120_intc_irq_chip, + handle_level_irq); + } + + setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + adm5120_intc_irq_init(); +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/memory.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/memory.c new file mode 100644 index 0000000..d07266f --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/memory.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#ifdef DEBUG +# define mem_dbg(f, a...) printk(KERN_INFO "mem_detect: " f, ## a) +#else +# define mem_dbg(f, a...) +#endif + +unsigned long adm5120_memsize; + +#define MEM_READL(a) __raw_readl((void __iomem *)(a)) +#define MEM_WRITEL(a, v) __raw_writel((v), (void __iomem *)(a)) + +static int __init mem_check_pattern(u8 *addr, unsigned long offs) +{ + u32 *p1 = (u32 *)addr; + u32 *p2 = (u32 *)(addr+offs); + u32 t, u, v; + + /* save original value */ + t = MEM_READL(p1); + + u = MEM_READL(p2); + if (t != u) + return 0; + + v = 0x55555555; + if (u == v) + v = 0xAAAAAAAA; + + mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1); + + MEM_WRITEL(p1, v); + adm5120_ndelay(1000); + u = MEM_READL(p2); + + mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u); + + /* restore original value */ + MEM_WRITEL(p1, t); + + return (v == u); +} + +static void __init adm5120_detect_memsize(void) +{ + u32 memctrl; + u32 size, maxsize; + u8 *p; + + memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL); + switch (memctrl & MEMCTRL_SDRS_MASK) { + case MEMCTRL_SDRS_4M: + maxsize = 4 << 20; + break; + case MEMCTRL_SDRS_8M: + maxsize = 8 << 20; + break; + case MEMCTRL_SDRS_16M: + maxsize = 16 << 20; + break; + default: + maxsize = 64 << 20; + break; + } + + mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20); + + /* detect size of the 1st SDRAM bank */ + p = (u8 *)KSEG1ADDR(0); + for (size = 2<<20; size <= (maxsize >> 1); size <<= 1) { + if (mem_check_pattern(p, size)) { + /* mirrored address */ + mem_dbg("mirrored data found at offset 0x%08X\n", size); + break; + } + } + + mem_dbg("chip size in 1st bank is %uMB\n", size >> 20); + adm5120_memsize = size; + + if (size != maxsize) + /* 2nd bank is not supported */ + goto out; + + if ((memctrl & MEMCTRL_SDR1_ENABLE) == 0) + /* 2nd bank is disabled */ + goto out; + + /* + * some bootloaders enable 2nd bank, even if the 2nd SDRAM chip + * are missing. + */ + mem_dbg("check presence of 2nd bank\n"); + + p = (u8 *)KSEG1ADDR(maxsize+size-4); + if (mem_check_pattern(p, 0)) + adm5120_memsize += size; + + if (maxsize != size) { + /* adjusting MECTRL register */ + memctrl &= ~(MEMCTRL_SDRS_MASK); + switch (size>>20) { + case 4: + memctrl |= MEMCTRL_SDRS_4M; + break; + case 8: + memctrl |= MEMCTRL_SDRS_8M; + break; + case 16: + memctrl |= MEMCTRL_SDRS_16M; + break; + default: + memctrl |= MEMCTRL_SDRS_64M; + break; + } + SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl); + } + +out: + mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 , + size>>20); +} + +void __init adm5120_mem_init(void) +{ + adm5120_detect_memsize(); + add_memory_region(0, adm5120_memsize, BOOT_MEM_RAM); +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/platform.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/platform.c new file mode 100644 index 0000000..bdbfbcb --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/platform.c @@ -0,0 +1,375 @@ +/* + * ADM5120 generic platform devices + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#if 1 +/* + * TODO:remove global adm5120_eth* variables when the switch driver will be + * converted into a real platform driver + */ +unsigned int adm5120_eth_num_ports = 6; +EXPORT_SYMBOL_GPL(adm5120_eth_num_ports); + +unsigned char adm5120_eth_macs[6][6] = { + {'\00', 'A', 'D', 'M', '\x51', '\x20' }, + {'\00', 'A', 'D', 'M', '\x51', '\x21' }, + {'\00', 'A', 'D', 'M', '\x51', '\x22' }, + {'\00', 'A', 'D', 'M', '\x51', '\x23' }, + {'\00', 'A', 'D', 'M', '\x51', '\x24' }, + {'\00', 'A', 'D', 'M', '\x51', '\x25' } +}; +EXPORT_SYMBOL_GPL(adm5120_eth_macs); + +unsigned char adm5120_eth_vlans[6] = { + 0x41, 0x42, 0x44, 0x48, 0x50, 0x60 +}; +EXPORT_SYMBOL_GPL(adm5120_eth_vlans); +#endif + +void __init adm5120_setup_eth_macs(u8 *mac_base) +{ + u32 t; + int i, j; + + t = ((u32) mac_base[3] << 16) | ((u32) mac_base[4] << 8) + | ((u32) mac_base[5]); + + for (i = 0; i < ARRAY_SIZE(adm5120_eth_macs); i++) { + for (j = 0; j < 3; j++) + adm5120_eth_macs[i][j] = mac_base[j]; + + adm5120_eth_macs[i][3] = (t >> 16) & 0xff; + adm5120_eth_macs[i][4] = (t >> 8) & 0xff; + adm5120_eth_macs[i][5] = t & 0xff; + + t++; + } +} + +/* + * Built-in ethernet switch + */ +struct resource adm5120_switch_resources[] = { + [0] = { + .start = ADM5120_SWITCH_BASE, + .end = ADM5120_SWITCH_BASE+ADM5120_SWITCH_SIZE-1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ADM5120_IRQ_SWITCH, + .end = ADM5120_IRQ_SWITCH, + .flags = IORESOURCE_IRQ, + }, +}; + +struct adm5120_switch_platform_data adm5120_switch_data; +struct platform_device adm5120_switch_device = { + .name = "adm5120-switch", + .id = -1, + .num_resources = ARRAY_SIZE(adm5120_switch_resources), + .resource = adm5120_switch_resources, + .dev.platform_data = &adm5120_switch_data, +}; + +void __init adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map) +{ + if (num_ports > 0) + adm5120_eth_num_ports = num_ports; + + if (vlan_map) + memcpy(adm5120_eth_vlans, vlan_map, sizeof(adm5120_eth_vlans)); + + platform_device_register(&adm5120_switch_device); +} + +/* + * USB Host Controller + */ +struct resource adm5120_hcd_resources[] = { + [0] = { + .start = ADM5120_USBC_BASE, + .end = ADM5120_USBC_BASE+ADM5120_USBC_SIZE-1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ADM5120_IRQ_USBC, + .end = ADM5120_IRQ_USBC, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 adm5120_hcd_dma_mask = DMA_BIT_MASK(24); +struct platform_device adm5120_hcd_device = { + .name = "adm5120-hcd", + .id = -1, + .num_resources = ARRAY_SIZE(adm5120_hcd_resources), + .resource = adm5120_hcd_resources, + .dev = { + .dma_mask = &adm5120_hcd_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(24), + } +}; + +void __init adm5120_add_device_usb(void) +{ + platform_device_register(&adm5120_hcd_device); +} + +/* + * NOR flash devices + */ +struct adm5120_flash_platform_data adm5120_flash0_data; +struct platform_device adm5120_flash0_device = { + .name = "adm5120-flash", + .id = 0, + .dev.platform_data = &adm5120_flash0_data, +}; + +struct adm5120_flash_platform_data adm5120_flash1_data; +struct platform_device adm5120_flash1_device = { + .name = "adm5120-flash", + .id = 1, + .dev.platform_data = &adm5120_flash1_data, +}; + +void __init adm5120_add_device_flash(unsigned id) +{ + struct platform_device *pdev; + + switch (id) { + case 0: + pdev = &adm5120_flash0_device; + break; + case 1: + pdev = &adm5120_flash1_device; + break; + default: + pdev = NULL; + break; + } + + if (pdev) + platform_device_register(pdev); +} + +/* + * built-in UARTs + */ +static void adm5120_uart_set_mctrl(struct amba_device *dev, void __iomem *base, + unsigned int mctrl) +{ +} + +struct amba_pl010_data adm5120_uart0_data = { + .set_mctrl = adm5120_uart_set_mctrl +}; + +struct amba_device adm5120_uart0_device = { + .dev = { + .init_name = "apb:uart0", + .platform_data = &adm5120_uart0_data, + }, + .res = { + .start = ADM5120_UART0_BASE, + .end = ADM5120_UART0_BASE + ADM5120_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = { ADM5120_IRQ_UART0, 0 }, + .periphid = 0x0041010, +}; + +struct amba_pl010_data adm5120_uart1_data = { + .set_mctrl = adm5120_uart_set_mctrl +}; + +struct amba_device adm5120_uart1_device = { + .dev = { + .init_name = "apb:uart1", + .platform_data = &adm5120_uart1_data, + }, + .res = { + .start = ADM5120_UART1_BASE, + .end = ADM5120_UART1_BASE + ADM5120_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = { ADM5120_IRQ_UART1, 0 }, + .periphid = 0x0041010, +}; + +void __init adm5120_add_device_uart(unsigned id) +{ + struct amba_device *dev; + + switch (id) { + case 0: + dev = &adm5120_uart0_device; + break; + case 1: + dev = &adm5120_uart1_device; + break; + default: + dev = NULL; + break; + } + + if (dev) + amba_device_register(dev, &iomem_resource); +} + +/* + * GPIO buttons + */ +void __init adm5120_register_gpio_buttons(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons) +{ + struct platform_device *pdev; + struct gpio_keys_platform_data pdata; + struct gpio_keys_button *p; + int err; + + p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + pdev = platform_device_alloc("gpio-keys-polled", id); + if (!pdev) + goto err_free_buttons; + + memset(&pdata, 0, sizeof(pdata)); + pdata.poll_interval = poll_interval; + pdata.nbuttons = nbuttons; + pdata.buttons = p; + + err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); + if (err) + goto err_put_pdev; + + err = platform_device_add(pdev); + if (err) + goto err_put_pdev; + + return; + +err_put_pdev: + platform_device_put(pdev); + +err_free_buttons: + kfree(p); +} + +/* + * GPIO LEDS + */ +struct gpio_led_platform_data adm5120_gpio_leds_data; +struct platform_device adm5120_gpio_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev.platform_data = &adm5120_gpio_leds_data, +}; + +void __init adm5120_add_device_gpio_leds(unsigned num_leds, + struct gpio_led *leds) +{ + struct gpio_led *p; + + p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); + if (!p) + return; + + memcpy(p, leds, num_leds * sizeof(*p)); + adm5120_gpio_leds_data.num_leds = num_leds; + adm5120_gpio_leds_data.leds = p; + + platform_device_register(&adm5120_gpio_leds_device); +} + +/* + * NAND flash + */ +struct resource adm5120_nand_resources[] = { + [0] = { + .start = ADM5120_NAND_BASE, + .end = ADM5120_NAND_BASE + ADM5120_NAND_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static int adm5120_nand_ready(struct mtd_info *mtd) +{ + return ((adm5120_nand_get_status() & ADM5120_NAND_STATUS_READY) != 0); +} + +static void adm5120_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + adm5120_nand_set_cle(ctrl & NAND_CLE); + adm5120_nand_set_ale(ctrl & NAND_ALE); + adm5120_nand_set_cen(ctrl & NAND_NCE); + } + + if (cmd != NAND_CMD_NONE) + NAND_WRITE_REG(NAND_REG_DATA, cmd); +} + +void __init adm5120_add_device_nand(struct platform_nand_data *pdata) +{ + struct platform_device *pdev; + int err; + + pdev = platform_device_alloc("gen_nand", -1); + if (!pdev) + goto err_out; + + err = platform_device_add_resources(pdev, adm5120_nand_resources, + ARRAY_SIZE(adm5120_nand_resources)); + if (err) + goto err_put; + + err = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (err) + goto err_put; + + pdata = pdev->dev.platform_data; + pdata->ctrl.dev_ready = adm5120_nand_ready; + pdata->ctrl.cmd_ctrl = adm5120_nand_cmd_ctrl; + + err = platform_device_add(pdev); + if (err) + goto err_put; + + return; + +err_put: + platform_device_put(pdev); +err_out: + return; +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/prom.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/prom.c new file mode 100644 index 0000000..5c52ea2 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/prom.c @@ -0,0 +1,264 @@ +/* + * ADM5120 specific prom routines + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include + +unsigned int adm5120_prom_type = ADM5120_PROM_GENERIC; + +struct board_desc { + unsigned long mach_type; + char *name; +}; + +#define DEFBOARD(n, mt) { .mach_type = (mt), .name = (n)} +static struct board_desc common_boards[] __initdata = { + /* Cellvision/SparkLAN boards */ + DEFBOARD("CAS-630", MACH_ADM5120_CAS630), + DEFBOARD("CAS-670", MACH_ADM5120_CAS670), + DEFBOARD("CAS-700", MACH_ADM5120_CAS700), + DEFBOARD("CAS-771", MACH_ADM5120_CAS771), + DEFBOARD("CAS-790", MACH_ADM5120_CAS790), + DEFBOARD("CAS-861", MACH_ADM5120_CAS861), + DEFBOARD("NFS-101U", MACH_ADM5120_NFS101U), + /* Compex boards */ + DEFBOARD("WP54G-WRT", MACH_ADM5120_WP54G_WRT), + /* Edimax boards */ + DEFBOARD("BR-6104K", MACH_ADM5120_BR6104K), + DEFBOARD("BR-6104KP", MACH_ADM5120_BR6104KP), + DEFBOARD("BR-6104WG", MACH_ADM5120_BR61X4WG), + DEFBOARD("BR-6114WG", MACH_ADM5120_BR61X4WG), + /* Infineon boards */ + DEFBOARD("EASY 5120P-ATA", MACH_ADM5120_EASY5120PATA), + DEFBOARD("EASY 5120-RT", MACH_ADM5120_EASY5120RT), + DEFBOARD("EASY 5120-WVoIP", MACH_ADM5120_EASY5120WVOIP), + DEFBOARD("EASY 83000", MACH_ADM5120_EASY83000), + /* Mikrotik RouterBOARDs */ + DEFBOARD("111", MACH_ADM5120_RB_11X), + DEFBOARD("112", MACH_ADM5120_RB_11X), + DEFBOARD("133", MACH_ADM5120_RB_133), + DEFBOARD("133C", MACH_ADM5120_RB_133C), + DEFBOARD("133C3", MACH_ADM5120_RB_133C), + DEFBOARD("150", MACH_ADM5120_RB_153), /* it's intentional */ + DEFBOARD("153", MACH_ADM5120_RB_153), + DEFBOARD("192", MACH_ADM5120_RB_192), + DEFBOARD("miniROUTER", MACH_ADM5120_RB_150), + /* OSBRiDGE boards */ + DEFBOARD("OSBRiDGE 5GXi", MACH_ADM5120_5GXI), + /* Motorola boards */ + DEFBOARD("Powerline MU Gateway", MACH_ADM5120_PMUGW), + /* Generic EB-214A */ + DEFBOARD("ADM5120", MACH_ADM5120_EB_214A), +}; + +static unsigned long __init find_machtype_byname(char *name) +{ + unsigned long ret; + int i; + + ret = MACH_ADM5120_GENERIC; + if (name == NULL) + goto out; + + if (*name == '\0') + goto out; + + for (i = 0; i < ARRAY_SIZE(common_boards); i++) { + if (strcmp(common_boards[i].name, name) == 0) { + ret = common_boards[i].mach_type; + break; + } + } + +out: + return ret; +} + +static unsigned long __init detect_machtype_routerboot(void) +{ + char *name; + + name = routerboot_get_boardname(); + return find_machtype_byname(name); +} + +static unsigned long __init detect_machtype_generic(void) +{ + char *name; + + name = generic_prom_getenv("board_name"); + return find_machtype_byname(name); +} + +unsigned long __init detect_machtype_cfe(void) +{ + char *name; + + name = cfe_getenv("BOARD_NAME"); + return find_machtype_byname(name); +} + +static struct { + unsigned long mach_type; + u16 vendor_id; + u16 board_id; +} zynos_boards[] __initdata = { +#define ZYNOS_BOARD(vi, bi, mt) \ + {.vendor_id = (vi), .board_id = (bi), .mach_type = (mt)} + +#define ZYXEL_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_ZYXEL, bi, mt) +#define DLINK_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_DLINK, bi, mt) +#define LUCENT_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_LUCENT, bi, mt) + ZYXEL_BOARD(ZYNOS_BOARD_HS100, MACH_ADM5120_HS100), + ZYXEL_BOARD(ZYNOS_BOARD_P334U, MACH_ADM5120_P334U), + ZYXEL_BOARD(ZYNOS_BOARD_P334W, MACH_ADM5120_P334W), + ZYXEL_BOARD(ZYNOS_BOARD_P334WH, MACH_ADM5120_P334WH), + ZYXEL_BOARD(ZYNOS_BOARD_P334WHD, MACH_ADM5120_P334WHD), + ZYXEL_BOARD(ZYNOS_BOARD_P334WT, MACH_ADM5120_P334WT), + ZYXEL_BOARD(ZYNOS_BOARD_P334WT_ALT, MACH_ADM5120_P334WT), + ZYXEL_BOARD(ZYNOS_BOARD_P335, MACH_ADM5120_P335), + ZYXEL_BOARD(ZYNOS_BOARD_P335PLUS, MACH_ADM5120_P335PLUS), + ZYXEL_BOARD(ZYNOS_BOARD_P335U, MACH_ADM5120_P335U) +}; + +static unsigned long __init detect_machtype_bootbase(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(zynos_boards); i++) { + if (zynos_boards[i].vendor_id == bootbase_info.vendor_id && + zynos_boards[i].board_id == bootbase_info.board_id) { + return zynos_boards[i].mach_type; + break; + } + } + + printk(KERN_WARNING "Unknown ZyXEL model (%u)\n", + bootbase_info.board_id); + return MACH_ADM5120_GENERIC; +} + +static struct { + unsigned long mach_type; + u16 vid; + u16 did; + u16 svid; + u16 sdid; +} mylo_boards[] __initdata = { +#define MYLO_BOARD(v, d, sv, sd, mt) \ + {.vid = (v), .did = (d), .svid = (sv), .sdid = (sd), .mach_type = (mt)} +#define COMPEX_BOARD(d, mt) \ + MYLO_BOARD(VENID_COMPEX, (d), VENID_COMPEX, (d), (mt)) + + COMPEX_BOARD(DEVID_COMPEX_NP27G, MACH_ADM5120_NP27G), + COMPEX_BOARD(DEVID_COMPEX_NP28G, MACH_ADM5120_NP28G), + COMPEX_BOARD(DEVID_COMPEX_NP28GHS, MACH_ADM5120_NP28GHS), + COMPEX_BOARD(DEVID_COMPEX_WP54G, MACH_ADM5120_WP54), + COMPEX_BOARD(DEVID_COMPEX_WP54Gv1C, MACH_ADM5120_WP54Gv1C), + COMPEX_BOARD(DEVID_COMPEX_WP54AG, MACH_ADM5120_WP54), + COMPEX_BOARD(DEVID_COMPEX_WPP54G, MACH_ADM5120_WP54), + COMPEX_BOARD(DEVID_COMPEX_WPP54AG, MACH_ADM5120_WP54), +}; + +static unsigned long __init detect_machtype_myloader(void) +{ + unsigned long ret; + int i; + + ret = MACH_ADM5120_GENERIC; + for (i = 0; i < ARRAY_SIZE(mylo_boards); i++) { + if (mylo_boards[i].vid == myloader_info.vid && + mylo_boards[i].did == myloader_info.did && + mylo_boards[i].svid == myloader_info.svid && + mylo_boards[i].sdid == myloader_info.sdid) { + ret = mylo_boards[i].mach_type; + break; + } + } + + return ret; +} + +static void __init prom_detect_machtype(void) +{ + if (bootbase_present()) { + adm5120_prom_type = ADM5120_PROM_BOOTBASE; + mips_machtype = detect_machtype_bootbase(); + return; + } + + if (cfe_present()) { + adm5120_prom_type = ADM5120_PROM_CFE; + mips_machtype = detect_machtype_cfe(); + return; + } + + if (myloader_present()) { + adm5120_prom_type = ADM5120_PROM_MYLOADER; + mips_machtype = detect_machtype_myloader(); + return; + } + + if (routerboot_present()) { + adm5120_prom_type = ADM5120_PROM_ROUTERBOOT; + mips_machtype = detect_machtype_routerboot(); + return; + } + + if (generic_prom_present()) { + adm5120_prom_type = ADM5120_PROM_GENERIC; + mips_machtype = detect_machtype_generic(); + return; + } + + mips_machtype = MACH_ADM5120_GENERIC; +} + +#ifdef CONFIG_IMAGE_CMDLINE_HACK +extern char __image_cmdline[]; + +static void __init prom_init_cmdline(void) +{ + char *cmd; + + /* init command line, register a default kernel command line */ + cmd = __image_cmdline; + if (strlen(cmd) > 0) + strlcpy(arcs_cmdline, cmd, sizeof(arcs_cmdline)); + +} +#else +static inline void prom_init_cmdline(void) {} +#endif /* CONFIG_IMAGE_CMDLINE_HACK */ + +void __init prom_init(void) +{ + prom_detect_machtype(); + prom_init_cmdline(); +} + +void __init prom_free_prom_memory(void) +{ + /* We do not have to prom memory to free */ +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/setup.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/setup.c new file mode 100644 index 0000000..c0410af --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/common/setup.c @@ -0,0 +1,129 @@ +/* + * ADM5120 specific setup + * + * Copyright (C) 2007-2009 Gabor Juhos + * + * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel + * done by Jeroen Vreeken + * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org) + * + * Jeroen's code was based on the Linux 2.4.xx source codes found in various + * tarballs released by Edimax for it's ADM5120 based devices + * Copyright (C) ADMtek Incorporated + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define ADM5120_SYS_TYPE_LEN 64 + +unsigned char adm5120_sys_type[ADM5120_SYS_TYPE_LEN]; +void (*adm5120_board_reset)(void); + +static char *prom_names[ADM5120_PROM_LAST+1] __initdata = { + [ADM5120_PROM_GENERIC] = "Generic", + [ADM5120_PROM_CFE] = "CFE", + [ADM5120_PROM_UBOOT] = "U-Boot", + [ADM5120_PROM_MYLOADER] = "MyLoader", + [ADM5120_PROM_ROUTERBOOT] = "RouterBOOT", + [ADM5120_PROM_BOOTBASE] = "Bootbase" +}; + +static void __init adm5120_report(void) +{ + printk(KERN_INFO "SoC : %s\n", adm5120_sys_type); + printk(KERN_INFO "Bootdev : %s flash\n", + adm5120_nand_boot ? "NAND" : "NOR"); + printk(KERN_INFO "Prom : %s\n", prom_names[adm5120_prom_type]); +} + +const char *get_system_type(void) +{ + return adm5120_sys_type; +} + +static void adm5120_restart(char *command) +{ + /* TODO: stop switch before reset */ + + if (adm5120_board_reset) + adm5120_board_reset(); + + SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1); +} + +static void adm5120_halt(void) +{ + local_irq_disable(); + + while (1) { + if (cpu_wait) + cpu_wait(); + } +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = adm5120_speed / 2; +} + +void __init plat_mem_setup(void) +{ + adm5120_soc_init(); + adm5120_mem_init(); + + sprintf(adm5120_sys_type, "ADM%04X%s rev %u, running at %lu.%03lu MHz", + adm5120_product_code, + adm5120_package_bga() ? "" : "P", + adm5120_revision, + (adm5120_speed / 1000000), (adm5120_speed / 1000) % 1000); + + adm5120_report(); + + _machine_restart = adm5120_restart; + _machine_halt = adm5120_halt; + pm_power_off = adm5120_halt; + + set_io_port_base(KSEG1); +} + +static int __init adm5120_board_setup(void) +{ + adm5120_gpio_init(); + + mips_machine_setup(); + + return 0; +} +arch_initcall(adm5120_board_setup); + +static void __init adm5120_generic_board_setup(void) +{ + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + + adm5120_add_device_flash(0); + adm5120_add_device_switch(6, NULL); +} + +MIPS_MACHINE(MACH_ADM5120_GENERIC, "Generic", "Generic ADM5120 board", + adm5120_generic_board_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/Makefile new file mode 100644 index 0000000..8c66c17 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/Makefile @@ -0,0 +1,5 @@ +obj-y += compex.o + +obj-$(CONFIG_ADM5120_MACH_NP27G) += np27g.o +obj-$(CONFIG_ADM5120_MACH_NP28G) += np28g.o +obj-$(CONFIG_ADM5120_MACH_WP54) += wp54.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/compex.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/compex.c new file mode 100644 index 0000000..814acfb --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/compex.c @@ -0,0 +1,60 @@ +/* + * Compex boards + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "compex.h" + +#include + +static void switch_bank_gpio5(unsigned bank) +{ + switch (bank) { + case 0: + gpio_set_value(ADM5120_GPIO_PIN5, 0); + break; + case 1: + gpio_set_value(ADM5120_GPIO_PIN5, 1); + break; + } +} + +void __init compex_mac_setup(void) +{ + if (myloader_present()) { + int i; + + for (i = 0; i < 6; i++) { + if (is_valid_ether_addr(myloader_info.macs[i])) + memcpy(adm5120_eth_macs[i], + myloader_info.macs[i], ETH_ALEN); + else + random_ether_addr(adm5120_eth_macs[i]); + } + } else { + u8 mac[ETH_ALEN]; + + random_ether_addr(mac); + adm5120_setup_eth_macs(mac); + } +} + +void __init compex_generic_setup(void) +{ + gpio_request(ADM5120_GPIO_PIN5, NULL); /* for flash A20 line */ + gpio_direction_output(ADM5120_GPIO_PIN5, 0); + + adm5120_flash0_data.switch_bank = switch_bank_gpio5; + adm5120_add_device_flash(0); + + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + + compex_mac_setup(); +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/compex.h b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/compex.h new file mode 100644 index 0000000..124e676 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/compex.h @@ -0,0 +1,23 @@ +/* + * Compex boards + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +extern void compex_generic_setup(void) __init; diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/np27g.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/np27g.c new file mode 100644 index 0000000..82da46d --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/np27g.c @@ -0,0 +1,28 @@ +/* + * Compex NP27G board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "compex.h" + +static u8 np27g_vlans[6] __initdata = { + /* FIXME: untested */ + 0x41, 0x42, 0x44, 0x48, 0x50, 0x00 +}; + +static void __init np27g_setup(void) +{ + compex_generic_setup(); + adm5120_add_device_switch(5, np27g_vlans); + adm5120_add_device_usb(); + + /* TODO: add PCI IRQ map */ +} + +MIPS_MACHINE(MACH_ADM5120_NP27G, "NP27G", "Compex NetPassage 27G", np27g_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/np28g.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/np28g.c new file mode 100644 index 0000000..a541439 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/np28g.c @@ -0,0 +1,63 @@ +/* + * Compex NP28G board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "compex.h" + +static struct adm5120_pci_irq np28g_pci_irqs[] __initdata = { + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0), + PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI0), + PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI1), + PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2) +}; + +static struct gpio_led np28g_gpio_leds[] __initdata = { + GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL), + GPIO_LED_INV(ADM5120_GPIO_PIN3, "power", NULL), + GPIO_LED_INV(ADM5120_GPIO_PIN6, "wan_cond", NULL), + GPIO_LED_INV(ADM5120_GPIO_PIN7, "wifi", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L2, "usb1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L2, "usb2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L2, "usb3", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L2, "usb4", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL), +}; + +static u8 np28g_vlans[6] __initdata = { + 0x50, 0x42, 0x44, 0x48, 0x00, 0x00 +}; + +static void np28g_reset(void) +{ + gpio_set_value(ADM5120_GPIO_PIN4, 0); +} + +static void __init np28g_setup(void) +{ + compex_generic_setup(); + + /* setup reset line */ + gpio_request(ADM5120_GPIO_PIN4, NULL); + gpio_direction_output(ADM5120_GPIO_PIN4, 1); + adm5120_board_reset = np28g_reset; + + adm5120_add_device_switch(4, np28g_vlans); + adm5120_add_device_usb(); + + adm5120_add_device_gpio_leds(ARRAY_SIZE(np28g_gpio_leds), + np28g_gpio_leds); + + adm5120_pci_set_irq_map(ARRAY_SIZE(np28g_pci_irqs), np28g_pci_irqs); +} + +MIPS_MACHINE(MACH_ADM5120_NP28G, "NP28G", "Compex NetPassage 28G", np28g_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/wp54.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/wp54.c new file mode 100644 index 0000000..8aa35c5 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/compex/wp54.c @@ -0,0 +1,95 @@ +/* + * Compex WP54 board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "compex.h" + +#define WP54_KEYS_POLL_INTERVAL 20 +#define WP54_KEYS_DEBOUNCE_INTERVAL (3 * WP54_KEYS_POLL_INTERVAL) + +static struct mtd_partition wp54g_wrt_partitions[] = { + { + .name = "cfe", + .offset = 0, + .size = 0x050000, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "trx", + .offset = MTDPART_OFS_APPEND, + .size = 0x3A0000, + } , { + .name = "nvram", + .offset = MTDPART_OFS_APPEND, + .size = 0x010000, + } +}; + +static struct adm5120_pci_irq wp54_pci_irqs[] __initdata = { + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0), +}; + +static struct gpio_keys_button wp54_gpio_buttons[] __initdata = { + { + .desc = "reset_button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WP54_KEYS_DEBOUNCE_INTERVAL, + .gpio = ADM5120_GPIO_PIN4, + } +}; + +static struct gpio_led wp54_gpio_leds[] __initdata = { + GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL), + GPIO_LED_INV(ADM5120_GPIO_PIN6, "wlan", NULL), + GPIO_LED_INV(ADM5120_GPIO_PIN7, "wan", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2", NULL), +}; + +static u8 wp54_vlans[6] __initdata = { + 0x41, 0x42, 0x00, 0x00, 0x00, 0x00 +}; + +static void wp54_reset(void) +{ + gpio_set_value(ADM5120_GPIO_PIN3, 0); +} + +static void __init wp54_setup(void) +{ + compex_generic_setup(); + + /* setup reset line */ + gpio_request(ADM5120_GPIO_PIN3, NULL); + gpio_direction_output(ADM5120_GPIO_PIN3, 1); + adm5120_board_reset = wp54_reset; + + adm5120_add_device_switch(2, wp54_vlans); + adm5120_register_gpio_buttons(-1, WP54_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wp54_gpio_buttons), + wp54_gpio_buttons); + adm5120_add_device_gpio_leds(ARRAY_SIZE(wp54_gpio_leds), + wp54_gpio_leds); + + adm5120_pci_set_irq_map(ARRAY_SIZE(wp54_pci_irqs), wp54_pci_irqs); +} + +MIPS_MACHINE(MACH_ADM5120_WP54, "WP54", "Compex WP54 family", wp54_setup); + +static void __init wp54_wrt_setup(void) +{ + adm5120_flash0_data.nr_parts = ARRAY_SIZE(wp54g_wrt_partitions); + adm5120_flash0_data.parts = wp54g_wrt_partitions; + + wp54_setup(); +} + +MIPS_MACHINE(MACH_ADM5120_WP54G_WRT, "WP54G-WRT", "Compex WP54G-WRT", + wp54_wrt_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/Makefile new file mode 100644 index 0000000..1286ed4 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/Makefile @@ -0,0 +1,5 @@ +obj-y := br-61xx.o + +obj-$(CONFIG_ADM5120_MACH_BR_6104K) += br-6104k.o +obj-$(CONFIG_ADM5120_MACH_BR_6104KP) += br-6104kp.o +obj-$(CONFIG_ADM5120_MACH_BR_61X4WG) += br-61x4wg.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-6104k.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-6104k.c new file mode 100644 index 0000000..8b2b445 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-6104k.c @@ -0,0 +1,36 @@ +/* + * Edimax BR-6104K board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "br-61xx.h" + +static struct gpio_led br6104k_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL), +}; + +static void __init br6104k_setup(void) +{ + br61xx_generic_setup(); + adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104k_gpio_leds), + br6104k_gpio_leds); +} + +MIPS_MACHINE(MACH_ADM5120_BR6104K, "BR-6104K", "Edimax BR-6104K", + br6104k_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-6104kp.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-6104kp.c new file mode 100644 index 0000000..034575d --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-6104kp.c @@ -0,0 +1,39 @@ +/* + * Edimax BR-6104KP board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "br-61xx.h" + +static struct gpio_led br6104kp_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL), + GPIO_LED_INV(ADM5120_GPIO_PIN3, "usb1", NULL), + GPIO_LED_INV(ADM5120_GPIO_PIN1, "usb2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL), +}; + +static void __init br6104kp_setup(void) +{ + br61xx_generic_setup(); + adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104kp_gpio_leds), + br6104kp_gpio_leds); + adm5120_add_device_usb(); +} + +MIPS_MACHINE(MACH_ADM5120_BR6104KP, "BR-6104KP", "Edimax BR-6104KP", + br6104kp_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61x4wg.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61x4wg.c new file mode 100644 index 0000000..5d57507 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61x4wg.c @@ -0,0 +1,43 @@ +/* + * Edimax BR-6104Wg/6114WG board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "br-61xx.h" + +static struct adm5120_pci_irq br61x4wg_pci_irqs[] __initdata = { + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0), +}; + +static struct gpio_led br61x4wg_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL), + GPIO_LED_STD(ADM5120_GPIO_PIN5, "wlan", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL), +}; + +static void __init br61x4wg_setup(void) +{ + br61xx_generic_setup(); + adm5120_add_device_gpio_leds(ARRAY_SIZE(br61x4wg_gpio_leds), + br61x4wg_gpio_leds); + adm5120_pci_set_irq_map(ARRAY_SIZE(br61x4wg_pci_irqs), + br61x4wg_pci_irqs); +} + +MIPS_MACHINE(MACH_ADM5120_BR61X4WG, "BR-6104WG", "Edimax BR-6104WG/6114WG", + br61x4wg_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61xx.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61xx.c new file mode 100644 index 0000000..62a1cee --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61xx.c @@ -0,0 +1,84 @@ +/* + * Edimax BR-61xx support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "br-61xx.h" + +#include + +#define BR61XX_CONFIG_OFFSET 0x8000 +#define BR61XX_CONFIG_SIZE 0x1000 + +#define BR61XX_KEYS_POLL_INTERVAL 20 +#define BR61XX_KEYS_DEBOUNCE_INTERVAL (3 * BR61XX_KEYS_POLL_INTERVAL) + +static struct mtd_partition br61xx_partitions[] = { + { + .name = "admboot", + .offset = 0, + .size = 32*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "config", + .offset = MTDPART_OFS_APPEND, + .size = 32*1024, + } , { + .name = "firmware", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct gpio_keys_button br61xx_gpio_buttons[] __initdata = { + { + .desc = "reset_button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = BR61XX_KEYS_DEBOUNCE_INTERVAL, + .gpio = ADM5120_GPIO_PIN2, + } +}; + +static u8 br61xx_vlans[6] __initdata = { + 0x41, 0x42, 0x44, 0x48, 0x50, 0x00 +}; + +static void __init br61xx_mac_setup(void) +{ + u8 mac_base[6]; + int err; + + err = admboot_get_mac_base(BR61XX_CONFIG_OFFSET, + BR61XX_CONFIG_SIZE, mac_base); + + if ((err) || !is_valid_ether_addr(mac_base)) + random_ether_addr(mac_base); + + adm5120_setup_eth_macs(mac_base); +} + +void __init br61xx_generic_setup(void) +{ + + adm5120_flash0_data.nr_parts = ARRAY_SIZE(br61xx_partitions); + adm5120_flash0_data.parts = br61xx_partitions; + adm5120_add_device_flash(0); + + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + + adm5120_add_device_switch(5, br61xx_vlans); + + adm5120_register_gpio_buttons(-1, BR61XX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(br61xx_gpio_buttons), + br61xx_gpio_buttons); + + br61xx_mac_setup(); +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61xx.h b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61xx.h new file mode 100644 index 0000000..c4a9ece --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/edimax/br-61xx.h @@ -0,0 +1,23 @@ +/* + * Edimax BR-61xx board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +extern void __init br61xx_generic_setup(void) __init; diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/generic/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/generic/Makefile new file mode 100644 index 0000000..0c032e3 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/generic/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ADM5120_MACH_EB_214A) += eb-214a.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/generic/eb-214a.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/generic/eb-214a.c new file mode 100644 index 0000000..cf491a1 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/generic/eb-214a.c @@ -0,0 +1,120 @@ +/* + * EB-214A board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * Copyright (C) 2010 Cezary Jackiewicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + + +#define EB214A_CONFIG_OFFSET 0x4000 + +#define EB214A_KEYS_POLL_INTERVAL 20 +#define EB214A_KEYS_DEBOUNCE_INTERVAL (3 * EB214A_KEYS_POLL_INTERVAL) + +static struct mtd_partition eb214a_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 32*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "config", + .offset = MTDPART_OFS_APPEND, + .size = 32*1024, + } , { + .name = "firmware", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct adm5120_pci_irq eb214a_pci_irqs[] __initdata = { + PCIIRQ(4, 0, 1, ADM5120_IRQ_PCI0), + PCIIRQ(4, 1, 2, ADM5120_IRQ_PCI0), + PCIIRQ(4, 2, 3, ADM5120_IRQ_PCI0), +}; + +static struct gpio_led eb214a_gpio_leds[] __initdata = { + GPIO_LED_INV(ADM5120_GPIO_PIN7, "power", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "usb1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L1, "usb2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L2, "usb3", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "usb4", NULL), +}; + +static struct gpio_keys_button eb214a_gpio_buttons[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EB214A_KEYS_DEBOUNCE_INTERVAL, + .gpio = ADM5120_GPIO_PIN1, + } +}; + +static u8 eb214a_vlans[6] __initdata = { + 0x41, 0x42, 0x44, 0x48, 0x50, 0x00 +}; + +static void __init eb214a_mac_setup(void) +{ + u8 mac_base[6]; + u8 *cfg; + int i; + + cfg = (u8 *) KSEG1ADDR(ADM5120_SRAM0_BASE + EB214A_CONFIG_OFFSET); + for (i = 0; i < 6; i++) + mac_base[i] = cfg[i]; + + if (!is_valid_ether_addr(mac_base)) + random_ether_addr(mac_base); + + adm5120_setup_eth_macs(mac_base); +} + +static void __init eb214a_setup(void) +{ + adm5120_flash0_data.nr_parts = ARRAY_SIZE(eb214a_partitions); + adm5120_flash0_data.parts = eb214a_partitions; + adm5120_add_device_flash(0); + + adm5120_add_device_uart(0); + /* adm5120_add_device_uart(1); */ + + adm5120_add_device_switch(5, eb214a_vlans); + + eb214a_mac_setup(); + + adm5120_register_gpio_buttons(-1, EB214A_KEYS_POLL_INTERVAL, + ARRAY_SIZE(eb214a_gpio_buttons), + eb214a_gpio_buttons); + + adm5120_add_device_gpio_leds(ARRAY_SIZE(eb214a_gpio_leds), + eb214a_gpio_leds); + + adm5120_pci_set_irq_map(ARRAY_SIZE(eb214a_pci_irqs), + eb214a_pci_irqs); + /* adm5120_add_device_usb(); */ +} + +MIPS_MACHINE(MACH_ADM5120_EB_214A, "EB-214A", "Generic EB-214A", eb214a_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/Makefile new file mode 100644 index 0000000..49453cb --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/Makefile @@ -0,0 +1,6 @@ +obj-y += infineon.o + +obj-$(CONFIG_ADM5120_MACH_EASY5120_RT) += easy5120-rt.o +obj-$(CONFIG_ADM5120_MACH_EASY5120_WVOIP) += easy5120-wvoip.o +obj-$(CONFIG_ADM5120_MACH_EASY5120P_ATA) += easy5120p-ata.o +obj-$(CONFIG_ADM5120_MACH_EASY83000) += easy83000.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120-rt.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120-rt.c new file mode 100644 index 0000000..31eaee7 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120-rt.c @@ -0,0 +1,48 @@ +/* + * Infineon EASY 5120-RT Reference Board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "infineon.h" + +static struct gpio_led easy5120_rt_gpio_leds[] __initdata = { + GPIO_LED_INV(ADM5120_GPIO_PIN6, "user", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan0_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan0_led2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_led2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_led2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL), +}; + +static struct adm5120_pci_irq easy5120_rt_pci_irqs[] __initdata = { + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0), +}; + +static u8 easy5120_rt_vlans[6] __initdata = { + 0x41, 0x42, 0x44, 0x48, 0x50, 0x00 +}; + +static void __init easy5120_rt_setup(void) +{ + easy_setup_bga(); + + adm5120_add_device_switch(5, easy5120_rt_vlans); + adm5120_add_device_usb(); + adm5120_add_device_gpio_leds(ARRAY_SIZE(easy5120_rt_gpio_leds), + easy5120_rt_gpio_leds); + adm5120_pci_set_irq_map(ARRAY_SIZE(easy5120_rt_pci_irqs), + easy5120_rt_pci_irqs); +} + +MIPS_MACHINE(MACH_ADM5120_EASY5120RT, "EASY5120-RT", + "Infineon EASY 5120-RT Reference Board", easy5120_rt_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120-wvoip.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120-wvoip.c new file mode 100644 index 0000000..0bf404c --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120-wvoip.c @@ -0,0 +1,24 @@ +/* + * Infineon EASY 5120-WVoIP Reference Board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "infineon.h" + +static void __init easy5120wvoip_setup(void) +{ + easy_setup_bga(); + adm5120_add_device_switch(6, NULL); + + /* TODO: add VINETIC2 device */ + /* TODO: setup PCI IRQ map */ +} + +MIPS_MACHINE(MACH_ADM5120_EASY5120WVOIP, "EASY5120WVoIP", + "Infineon EASY 5120-WVoIP Reference Board", easy5120wvoip_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120p-ata.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120p-ata.c new file mode 100644 index 0000000..fafe023 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy5120p-ata.c @@ -0,0 +1,22 @@ +/* + * Infineon EASY 5120P-ATA Reference Board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "infineon.h" + +static void __init easy5120pata_setup(void) +{ + easy_setup_pqfp(); + + adm5120_add_device_switch(6, NULL); +} + +MIPS_MACHINE(MACH_ADM5120_EASY5120PATA, "EASY5120P-ATA", + "Infineon EASY 5120P-ATA Reference Board", easy5120pata_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy83000.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy83000.c new file mode 100644 index 0000000..051b852 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/easy83000.c @@ -0,0 +1,23 @@ +/* + * Infineon EASY 83000 Reference Board support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "infineon.h" + +static void __init easy83000_setup(void) +{ + easy_setup_pqfp(); + adm5120_add_device_switch(6, NULL); + + /* TODO: add VINAX device */ +} + +MIPS_MACHINE(MACH_ADM5120_EASY83000, "EASY8300", + "Infineon EASY 83000 Reference Board", easy83000_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/infineon.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/infineon.c new file mode 100644 index 0000000..5c441da --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/infineon.c @@ -0,0 +1,108 @@ +/* + * Infineon Reference Boards + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "infineon.h" + +#include + +#define EASY_CONFIG_OFFSET 0x10000 +#define EASY_CONFIG_SIZE 0x1000 + +static struct mtd_partition easy_partitions[] = { + { + .name = "admboot", + .offset = 0, + .size = 64*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "boardcfg", + .offset = MTDPART_OFS_APPEND, + .size = 64*1024, + } , { + .name = "firmware", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static __init void easy_setup_mac(void) +{ + u8 mac_base[6]; + int err; + + err = admboot_get_mac_base(EASY_CONFIG_OFFSET, + EASY_CONFIG_SIZE, mac_base); + + if ((err) || !is_valid_ether_addr(mac_base)) + random_ether_addr(mac_base); + + adm5120_setup_eth_macs(mac_base); +} + +static void switch_bank_gpio3(unsigned bank) +{ + switch (bank) { + case 0: + gpio_set_value(ADM5120_GPIO_PIN3, 0); + break; + case 1: + gpio_set_value(ADM5120_GPIO_PIN3, 1); + break; + } +} + +void __init easy_setup_pqfp(void) +{ + /* setup flash A20 line */ + gpio_request(ADM5120_GPIO_PIN3, NULL); + gpio_direction_output(ADM5120_GPIO_PIN3, 0); + adm5120_flash0_data.switch_bank = switch_bank_gpio3; + + adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions); + adm5120_flash0_data.parts = easy_partitions; + + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + + adm5120_add_device_flash(0); + + easy_setup_mac(); +} + +static void switch_bank_gpio5(unsigned bank) +{ + switch (bank) { + case 0: + gpio_set_value(ADM5120_GPIO_PIN5, 0); + break; + case 1: + gpio_set_value(ADM5120_GPIO_PIN5, 1); + break; + } +} + +void __init easy_setup_bga(void) +{ + /* setup flash A20 line */ + gpio_request(ADM5120_GPIO_PIN5, NULL); + gpio_direction_output(ADM5120_GPIO_PIN5, 0); + adm5120_flash0_data.switch_bank = switch_bank_gpio5; + + adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions); + adm5120_flash0_data.parts = easy_partitions; + + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + + adm5120_add_device_flash(0); + + easy_setup_mac(); +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/infineon.h b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/infineon.h new file mode 100644 index 0000000..a5f28b4 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/infineon/infineon.h @@ -0,0 +1,25 @@ +/* + * Infineon Reference Boards + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +extern void easy_setup_pqfp(void) __init; +extern void easy_setup_bga(void) __init; diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/Makefile new file mode 100644 index 0000000..34ea0a3 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/Makefile @@ -0,0 +1,8 @@ +obj-y += rb-1xx.o + +obj-${CONFIG_ADM5120_MACH_RB_11X} += rb-11x.o +obj-${CONFIG_ADM5120_MACH_RB_133} += rb-133.o +obj-${CONFIG_ADM5120_MACH_RB_133C} += rb-133c.o +obj-${CONFIG_ADM5120_MACH_RB_150} += rb-150.o +obj-${CONFIG_ADM5120_MACH_RB_153} += rb-153.o +obj-${CONFIG_ADM5120_MACH_RB_192} += rb-192.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-11x.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-11x.c new file mode 100644 index 0000000..fd768d8 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-11x.c @@ -0,0 +1,35 @@ +/* + * Mikrotik RouterBOARD 111/112 support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "rb-1xx.h" + +static struct gpio_led rb11x_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_PIN3, "user", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan_lnkact", NULL), +}; + +static u8 rb11x_vlans[6] __initdata = { + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static void __init rb11x_setup(void) +{ + rb1xx_generic_setup(); + rb1xx_add_device_nand(); + + adm5120_add_device_switch(1, rb11x_vlans); + adm5120_add_device_gpio_leds(ARRAY_SIZE(rb11x_gpio_leds), + rb11x_gpio_leds); +} + +MIPS_MACHINE(MACH_ADM5120_RB_11X, "11x", "Mikrotik RouterBOARD 111/112", + rb11x_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-133.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-133.c new file mode 100644 index 0000000..23c5782 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-133.c @@ -0,0 +1,40 @@ +/* + * Mikrotik RouterBOARD 133 support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "rb-1xx.h" + +static struct gpio_led rb133_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL), + GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan2_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan3_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan3_lnkact", NULL), +}; + +static u8 rb133_vlans[6] __initdata = { + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static void __init rb133_setup(void) +{ + rb1xx_generic_setup(); + rb1xx_add_device_nand(); + + adm5120_add_device_switch(3, rb133_vlans); + adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133_gpio_leds), + rb133_gpio_leds); +} + +MIPS_MACHINE(MACH_ADM5120_RB_133, "133", "Mikrotik RouterBOARD 133", + rb133_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-133c.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-133c.c new file mode 100644 index 0000000..25bab70 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-133c.c @@ -0,0 +1,36 @@ +/* + * Mikrotik RouterBOARD 133C support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "rb-1xx.h" + +static struct gpio_led rb133c_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL), + GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL), +}; + +static u8 rb133c_vlans[6] __initdata = { + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static void __init rb133c_setup(void) +{ + rb1xx_generic_setup(); + rb1xx_add_device_nand(); + + adm5120_add_device_switch(1, rb133c_vlans); + adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133c_gpio_leds), + rb133c_gpio_leds); +} + +MIPS_MACHINE(MACH_ADM5120_RB_133C, "133C", "Mikrotik RouterBOARD 133C", + rb133c_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-150.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-150.c new file mode 100644 index 0000000..96a8c1b --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-150.c @@ -0,0 +1,131 @@ +/* + * Mikrotik RouterBOARD 150 support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "rb-1xx.h" + +#define RB150_NAND_BASE 0x1FC80000 +#define RB150_NAND_SIZE 1 + +#define RB150_GPIO_NAND_READY ADM5120_GPIO_PIN0 +#define RB150_GPIO_NAND_NCE ADM5120_GPIO_PIN1 +#define RB150_GPIO_NAND_CLE ADM5120_GPIO_P2L2 +#define RB150_GPIO_NAND_ALE ADM5120_GPIO_P3L2 +#define RB150_GPIO_RESET_BUTTON ADM5120_GPIO_PIN1 /* FIXME */ + +#define RB150_NAND_DELAY 100 + +#define RB150_NAND_WRITE(v) \ + writeb((v), (void __iomem *)KSEG1ADDR(RB150_NAND_BASE)) + +static struct resource rb150_nand_resources[] __initdata = { + [0] = { + .start = RB150_NAND_BASE, + .end = RB150_NAND_BASE + RB150_NAND_SIZE-1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct gpio_led rb150_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_P0L2, "user", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_led2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_led2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_led2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_led1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_led2", NULL), +}; + +static u8 rb150_vlans[6] __initdata = { + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static int rb150_nand_dev_ready(struct mtd_info *mtd) +{ + return gpio_get_value(RB150_GPIO_NAND_READY); +} + +static void rb150_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + gpio_set_value(RB150_GPIO_NAND_CLE, (ctrl & NAND_CLE) ? 1 : 0); + gpio_set_value(RB150_GPIO_NAND_ALE, (ctrl & NAND_ALE) ? 1 : 0); + gpio_set_value(RB150_GPIO_NAND_NCE, (ctrl & NAND_NCE) ? 0 : 1); + } + + udelay(RB150_NAND_DELAY); + + if (cmd != NAND_CMD_NONE) + RB150_NAND_WRITE(cmd); +} + +static void __init rb150_add_device_nand(void) +{ + struct platform_device *pdev; + int err; + + /* setup GPIO pins for NAND flash chip */ + gpio_request(RB150_GPIO_NAND_READY, "nand-ready"); + gpio_direction_input(RB150_GPIO_NAND_READY); + gpio_request(RB150_GPIO_NAND_NCE, "nand-nce"); + gpio_direction_output(RB150_GPIO_NAND_NCE, 1); + gpio_request(RB150_GPIO_NAND_CLE, "nand-cle"); + gpio_direction_output(RB150_GPIO_NAND_CLE, 0); + gpio_request(RB150_GPIO_NAND_ALE, "nand-ale"); + gpio_direction_output(RB150_GPIO_NAND_ALE, 0); + + pdev = platform_device_alloc("gen_nand", -1); + if (!pdev) + goto err_out; + + err = platform_device_add_resources(pdev, rb150_nand_resources, + ARRAY_SIZE(rb150_nand_resources)); + if (err) + goto err_put; + + + rb1xx_nand_data.ctrl.cmd_ctrl = rb150_nand_cmd_ctrl; + rb1xx_nand_data.ctrl.dev_ready = rb150_nand_dev_ready; + + err = platform_device_add_data(pdev, &rb1xx_nand_data, + sizeof(rb1xx_nand_data)); + if (err) + goto err_put; + + err = platform_device_add(pdev); + if (err) + goto err_put; + + return; + +err_put: + platform_device_put(pdev); +err_out: + return; +} + +static void __init rb150_setup(void) +{ + rb1xx_gpio_buttons[0].gpio = RB150_GPIO_RESET_BUTTON; + rb1xx_generic_setup(); + rb150_add_device_nand(); + + adm5120_add_device_gpio_leds(ARRAY_SIZE(rb150_gpio_leds), + rb150_gpio_leds); + adm5120_add_device_switch(5, rb150_vlans); +} + +MIPS_MACHINE(MACH_ADM5120_RB_150, "miniROUTER", "Mikrotik RouterBOARD 150", + rb150_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-153.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-153.c new file mode 100644 index 0000000..8456684 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-153.c @@ -0,0 +1,70 @@ +/* + * Mikrotik RouterBOARD 153 support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "rb-1xx.h" + +static struct resource rb153_cf_resources[] __initdata = { + { + .name = "cf_membase", + .start = ADM5120_EXTIO1_BASE, + .end = ADM5120_EXTIO1_BASE + ADM5120_EXTIO1_SIZE-1 , + .flags = IORESOURCE_MEM + }, { + .name = "cf_irq", + .start = ADM5120_IRQ_GPIO4, + .end = ADM5120_IRQ_GPIO4, + .flags = IORESOURCE_IRQ + } +}; + +static struct gpio_led rb153_gpio_leds[] __initdata = { + GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_speed", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_lnkact", NULL), +}; + +static u8 rb153_vlans[6] __initdata = { + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static void __init rb153_add_device_cf(void) +{ + /* enable CSX1:INTX1 on GPIO[3:4] for the CF slot */ + adm5120_gpio_csx1_enable(); + + /* enable the wait state pin GPIO[0] for external I/O control */ + adm5120_gpio_ew_enable(); + + platform_device_register_simple("pata-rb153-cf", -1, + rb153_cf_resources, ARRAY_SIZE(rb153_cf_resources)); +} + +static void __init rb153_setup(void) +{ + rb1xx_generic_setup(); + rb1xx_add_device_nand(); + rb153_add_device_cf(); + + adm5120_add_device_gpio_leds(ARRAY_SIZE(rb153_gpio_leds), + rb153_gpio_leds); + adm5120_add_device_switch(5, rb153_vlans); +} + +MIPS_MACHINE(MACH_ADM5120_RB_153, "150", "Mikrotik RouterBOARD 153", + rb153_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-192.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-192.c new file mode 100644 index 0000000..9049421 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-192.c @@ -0,0 +1,27 @@ +/* + * Mikrotik RouterBOARD 192 support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "rb-1xx.h" + +static u8 rb192_vlans[6] __initdata = { + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static void __init rb192_setup(void) +{ + rb1xx_generic_setup(); + rb1xx_add_device_nand(); + + adm5120_add_device_switch(6, rb192_vlans); +} + +MIPS_MACHINE(MACH_ADM5120_RB_192, "192", "Mikrotik RouterBOARD 192", + rb192_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-1xx.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-1xx.c new file mode 100644 index 0000000..8961115 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-1xx.c @@ -0,0 +1,149 @@ +/* + * Mikrotik RouterBOARD 1xx series support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * NAND initialization code was based on a driver for Linux 2.6.19+ which + * was derived from the driver for Linux 2.4.xx published by Mikrotik for + * their RouterBoard 1xx and 5xx series boards. + * Copyright (C) 2007 David Goodenough + * Copyright (C) 2007 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "rb-1xx.h" + +#define RB1XX_NAND_CHIP_DELAY 25 + +#define RB1XX_KEYS_POLL_INTERVAL 20 +#define RB1XX_KEYS_DEBOUNCE_INTERVAL (3 * RB1XX_KEYS_POLL_INTERVAL) + +static struct adm5120_pci_irq rb1xx_pci_irqs[] __initdata = { + PCIIRQ(1, 0, 1, ADM5120_IRQ_PCI0), + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI1), + PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI2) +}; + +static struct mtd_partition rb1xx_nor_parts[] = { + { + .name = "booter", + .offset = 0, + .size = 64*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "firmware", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct mtd_partition rb1xx_nand_parts[] = { + { + .name = "kernel", + .offset = 0, + .size = 4 * 1024 * 1024, + } , { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL + } +}; + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. So set the oobinfo + * when creating the partitions + */ +static struct nand_ecclayout rb1xx_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +/*--------------------------------------------------------------------------*/ + +static int rb1xx_nand_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) + chip->ecc.layout = &rb1xx_nand_ecclayout; + + return 0; +} + +struct platform_nand_data rb1xx_nand_data __initdata = { + .chip = { + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(rb1xx_nand_parts), + .partitions = rb1xx_nand_parts, + .chip_delay = RB1XX_NAND_CHIP_DELAY, + .chip_fixup = rb1xx_nand_fixup, + }, +}; + +struct gpio_keys_button rb1xx_gpio_buttons[] __initdata = { + { + .desc = "reset_button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RB1XX_KEYS_DEBOUNCE_INTERVAL, + .gpio = ADM5120_GPIO_PIN7, + } +}; + +static void __init rb1xx_mac_setup(void) +{ + if (rb_hs.mac_base != NULL && is_valid_ether_addr(rb_hs.mac_base)) { + adm5120_setup_eth_macs(rb_hs.mac_base); + } else { + u8 mac[ETH_ALEN]; + + random_ether_addr(mac); + adm5120_setup_eth_macs(mac); + } +} + +void __init rb1xx_add_device_flash(void) +{ + /* setup data for flash0 device */ + adm5120_flash0_data.nr_parts = ARRAY_SIZE(rb1xx_nor_parts); + adm5120_flash0_data.parts = rb1xx_nor_parts; + adm5120_flash0_data.window_size = 128*1024; + + adm5120_add_device_flash(0); +} + +void __init rb1xx_add_device_nand(void) +{ + /* enable NAND flash interface */ + adm5120_nand_enable(); + + /* initialize NAND chip */ + adm5120_nand_set_spn(1); + adm5120_nand_set_wpn(0); + + adm5120_add_device_nand(&rb1xx_nand_data); +} + +void __init rb1xx_generic_setup(void) +{ + if (adm5120_package_bga()) + adm5120_pci_set_irq_map(ARRAY_SIZE(rb1xx_pci_irqs), + rb1xx_pci_irqs); + + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + + adm5120_register_gpio_buttons(-1, RB1XX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rb1xx_gpio_buttons), + rb1xx_gpio_buttons); + + rb1xx_add_device_flash(); + rb1xx_mac_setup(); +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-1xx.h b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-1xx.h new file mode 100644 index 0000000..05e68bd --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/mikrotik/rb-1xx.h @@ -0,0 +1,33 @@ +/* + * Mikrotik RouterBOARD 1xx series support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include + +extern struct platform_nand_data rb1xx_nand_data __initdata; +extern struct gpio_keys_button rb1xx_gpio_buttons[] __initdata; + +extern void rb1xx_add_device_flash(void) __init; +extern void rb1xx_add_device_nand(void) __init; +extern void rb1xx_generic_setup(void) __init; diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/motorola/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/motorola/Makefile new file mode 100644 index 0000000..239d5a0 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/motorola/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ADM5120_MACH_PMUGW) += pmugw.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/motorola/pmugw.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/motorola/pmugw.c new file mode 100644 index 0000000..369892f --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/motorola/pmugw.c @@ -0,0 +1,96 @@ +/* + * Motorola Powerline MU Gateway board + * + * Copyright (C) 2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include + +#define PMUGW_CONFIG_OFFSET 0x10000 +#define PMUGW_CONFIG_SIZE 0x1000 + +static struct mtd_partition pmugw_partitions[] = { + { + .name = "admboot", + .offset = 0, + .size = 64*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "boardcfg", + .offset = MTDPART_OFS_APPEND, + .size = 64*1024, + } , { + .name = "firmware", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static u8 pmugw_vlans[6] __initdata = { + 0x41, 0x42, 0x44, 0x48, 0x50, 0x00 +}; + +static __init void pmugw_setup_mac(void) +{ + u8 mac_base[6]; + int err; + + err = admboot_get_mac_base(PMUGW_CONFIG_OFFSET, + PMUGW_CONFIG_SIZE, mac_base); + + if ((err) || !is_valid_ether_addr(mac_base)) + random_ether_addr(mac_base); + + adm5120_setup_eth_macs(mac_base); +} + +static void switch_bank_gpio5(unsigned bank) +{ + switch (bank) { + case 0: + gpio_set_value(ADM5120_GPIO_PIN5, 0); + break; + case 1: + gpio_set_value(ADM5120_GPIO_PIN5, 1); + break; + } +} + +void __init pmugw_setup(void) +{ + /* setup flash A20 line */ + gpio_request(ADM5120_GPIO_PIN5, NULL); + gpio_direction_output(ADM5120_GPIO_PIN5, 0); + adm5120_flash0_data.switch_bank = switch_bank_gpio5; + + adm5120_flash0_data.nr_parts = ARRAY_SIZE(pmugw_partitions); + adm5120_flash0_data.parts = pmugw_partitions; + + adm5120_add_device_uart(1); /* ttyAM0 */ + adm5120_add_device_uart(0); /* ttyAM1 */ + + adm5120_add_device_flash(0); + + pmugw_setup_mac(); + adm5120_add_device_switch(5, pmugw_vlans); +} + +MIPS_MACHINE(MACH_ADM5120_PMUGW, "PMUGW", "Motorola Powerline MU Gateway", + pmugw_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/osbridge/5gxi.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/osbridge/5gxi.c new file mode 100644 index 0000000..a5c2c36 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/osbridge/5gxi.c @@ -0,0 +1,71 @@ +/* + * OSBRiDGE 5GXi/5XLi board support + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +static struct mtd_partition osbridge_5gxi_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 64*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "boardcfg", + .offset = 64*1024, + .size = 64*1024, + } , { + .name = "firmware", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct gpio_led osbridge_5gxi_gpio_leds[] __initdata = { + GPIO_LED_INV(ADM5120_GPIO_PIN6, "5gxi:green:user", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "5gxi:yellow:lan", NULL), +}; + +static struct adm5120_pci_irq osbridge_5gxi_pci_irqs[] __initdata = { + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0), +}; + +static u8 osbridge_5gxi_vlans[6] __initdata = { + 0x41, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static void __init osbridge_5gxi_setup(void) +{ + adm5120_flash0_data.nr_parts = ARRAY_SIZE(osbridge_5gxi_partitions); + adm5120_flash0_data.parts = osbridge_5gxi_partitions; + + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + + adm5120_add_device_flash(0); + + adm5120_add_device_switch(1, osbridge_5gxi_vlans); + adm5120_add_device_gpio_leds(ARRAY_SIZE(osbridge_5gxi_gpio_leds), + osbridge_5gxi_gpio_leds); + adm5120_pci_set_irq_map(ARRAY_SIZE(osbridge_5gxi_pci_irqs), + osbridge_5gxi_pci_irqs); +} + +MIPS_MACHINE(MACH_ADM5120_5GXI, "5GXi", "OSBRiDGE 5GXi/5XLi board", + osbridge_5gxi_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/osbridge/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/osbridge/Makefile new file mode 100644 index 0000000..34946c5 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/osbridge/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ADM5120_MACH_5GXI) += 5gxi.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/Makefile new file mode 100644 index 0000000..650be40 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the ADMtek ADM5120 SoC specific parts of the kernel +# + +lib-y += admboot.o +lib-y += bootbase.o +lib-y += cfe.o +lib-y += generic.o +lib-y += myloader.o +lib-y += routerboot.o diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/admboot.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/admboot.c new file mode 100644 index 0000000..b655390 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/admboot.c @@ -0,0 +1,55 @@ +/* + * ADMBoot specific prom routines + * + * Copyright (C) 2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include "prom_read.h" + +#define ADMBOOT_MAGIC_MAC_BASE 0x636D676D /* 'mgmc' */ +#define ADMBOOT_MAGIC_MAC_BASE_BR6104XX 0x31305348 /* 'HS01' */ + +int __init admboot_get_mac_base(u32 offset, u32 len, u8 *mac) +{ + u8 *cfg; + int i; + + cfg = (u8 *) KSEG1ADDR(ADM5120_SRAM0_BASE + offset); + for (i = 0; i < len; i += 4) { + u32 magic; + + magic = prom_read_le32(cfg + i); + if (magic == ADMBOOT_MAGIC_MAC_BASE) { + int j; + + for (j = 0; j < 6; j++) + mac[j] = cfg[i + 4 + j]; + + return 0; + } + if (magic == ADMBOOT_MAGIC_MAC_BASE_BR6104XX) { + int j; + + for (j = 0; j < 6; j++) + mac[j] = cfg[i + 7 + j]; + + return 0; + } + } + + return -ENXIO; +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/bootbase.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/bootbase.c new file mode 100644 index 0000000..063281e --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/bootbase.c @@ -0,0 +1,119 @@ +/* + * ZyXEL's Bootbase specific prom routines + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include "prom_read.h" + +#define ZYNOS_INFO_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x3F90) +#define ZYNOS_HDBG_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x4000) +#define BOOTEXT_ADDR_MIN KSEG1ADDR(ADM5120_SRAM0_BASE) +#define BOOTEXT_ADDR_MAX (BOOTEXT_ADDR_MIN + (2*1024*1024)) + +static int bootbase_found; +static struct zynos_board_info *board_info; + +struct bootbase_info bootbase_info; + +static inline int bootbase_dbgarea_present(u8 *data) +{ + u32 t; + + t = prom_read_be32(data+5); + if (t != ZYNOS_MAGIC_DBGAREA1) + return 0; + + t = prom_read_be32(data+9); + if (t != ZYNOS_MAGIC_DBGAREA2) + return 0; + + return 1; +} + +static inline u32 bootbase_get_bootext_addr(void) +{ + return prom_read_be32(&board_info->bootext_addr); +} + +static inline void bootbase_get_mac(u8 *mac) +{ + int i; + + for (i = 0; i < 6; i++) + mac[i] = board_info->mac[i]; +} + +static inline u16 bootbase_get_vendor_id(void) +{ +#define CHECK_VENDOR(n) (strnicmp(board_info->vendor, (n), strlen(n)) == 0) + unsigned char vendor[ZYNOS_NAME_LEN]; + int i; + + for (i = 0; i < ZYNOS_NAME_LEN; i++) + vendor[i] = board_info->vendor[i]; + + if CHECK_VENDOR(ZYNOS_VENDOR_ZYXEL) + return ZYNOS_VENDOR_ID_ZYXEL; + + if CHECK_VENDOR(ZYNOS_VENDOR_DLINK) + return ZYNOS_VENDOR_ID_DLINK; + + if CHECK_VENDOR(ZYNOS_VENDOR_LUCENT) + return ZYNOS_VENDOR_ID_LUCENT; + + if CHECK_VENDOR(ZYNOS_VENDOR_NETGEAR) + return ZYNOS_VENDOR_ID_NETGEAR; + + return ZYNOS_VENDOR_ID_OTHER; +} + +static inline u16 bootbase_get_board_id(void) +{ + return prom_read_be16(&board_info->board_id); +} + +int __init bootbase_present(void) +{ + u32 t; + + if (bootbase_found) + goto out; + + /* check presence of the dbgarea */ + if (bootbase_dbgarea_present((u8 *)ZYNOS_HDBG_ADDR) == 0) + goto out; + + board_info = (struct zynos_board_info *)(ZYNOS_INFO_ADDR); + + /* check for a valid BootExt address */ + t = bootbase_get_bootext_addr(); + if ((t < BOOTEXT_ADDR_MIN) || (t > BOOTEXT_ADDR_MAX)) + goto out; + + bootbase_info.vendor_id = bootbase_get_vendor_id(); + bootbase_info.board_id = bootbase_get_board_id(); + bootbase_get_mac(bootbase_info.mac); + + bootbase_found = 1; + +out: + return bootbase_found; +} + diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/cfe.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/cfe.c new file mode 100644 index 0000000..5a343cd --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/cfe.c @@ -0,0 +1,69 @@ +/* + * Broadcom's CFE specific prom routines + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include + +#include +#include + +#include +#include "prom_read.h" + +/* + * CFE based boards + */ +#define CFE_EPTSEAL 0x43464531 /* CFE1 is the magic number to recognize CFE +from other bootloaders */ + +static int cfe_found; + +static u32 cfe_handle; +static u32 cfe_entry; +static u32 cfe_seal; + +int __init cfe_present(void) +{ + /* + * This method only works, when we are booted directly from the CFE. + */ + u32 a1 = (u32) fw_arg1; + + if (cfe_found) + return 1; + + cfe_handle = (u32) fw_arg0; + cfe_entry = (u32) fw_arg2; + cfe_seal = (u32) fw_arg3; + + /* Check for CFE by finding the CFE magic number */ + if (cfe_seal != CFE_EPTSEAL) + return 0; + + /* cfe_a1_val must be 0, because only one CPU present in the ADM5120 */ + if (a1 != 0) + return 0; + + /* The cfe_handle, and the cfe_entry must be kernel mode addresses */ + if ((cfe_handle < KSEG0) || (cfe_entry < KSEG0)) + return 0; + + cfe_found = 1; + return 1; +} + +char *cfe_getenv(char *envname) +{ + if (cfe_found == 0) + return NULL; + + return NULL; +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/generic.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/generic.c new file mode 100644 index 0000000..4d4caa8 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/generic.c @@ -0,0 +1,47 @@ +/* + * Generic PROM routines + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include + +#include + +#include + +static int *_prom_argc; +static char **_prom_argv; +static char **_prom_envp; + +char *generic_prom_getenv(char *envname) +{ + char **env; + char *ret; + + ret = NULL; + for (env = _prom_envp; *env != NULL; env++) { + if (strcmp(envname, *env++) == 0) { + ret = *env; + break; + } + } + + return ret; +} + +int generic_prom_present(void) +{ + _prom_argc = (int *)fw_arg0; + _prom_argv = (char **)fw_arg1; + _prom_envp = (char **)fw_arg2; + + return 1; +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/myloader.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/myloader.c new file mode 100644 index 0000000..5357db5 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/myloader.c @@ -0,0 +1,68 @@ +/* + * Compex's MyLoader specific prom routines + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include "prom_read.h" + +#define SYS_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F000) +#define BOARD_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F800) +#define PART_TABLE_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x10000) + +static int myloader_found; + +struct myloader_info myloader_info; + +int __init myloader_present(void) +{ + struct mylo_system_params *sysp; + struct mylo_board_params *boardp; + struct mylo_partition_table *parts; + int i; + + if (myloader_found) + goto out; + + sysp = (struct mylo_system_params *)(SYS_PARAMS_ADDR); + boardp = (struct mylo_board_params *)(BOARD_PARAMS_ADDR); + parts = (struct mylo_partition_table *)(PART_TABLE_ADDR); + + /* Check for some magic numbers */ + if ((le32_to_cpu(sysp->magic) != MYLO_MAGIC_SYS_PARAMS) || + (le32_to_cpu(boardp->magic) != MYLO_MAGIC_BOARD_PARAMS) || + (le32_to_cpu(parts->magic) != MYLO_MAGIC_PARTITIONS)) + goto out; + + myloader_info.vid = le32_to_cpu(sysp->vid); + myloader_info.did = le32_to_cpu(sysp->did); + myloader_info.svid = le32_to_cpu(sysp->svid); + myloader_info.sdid = le32_to_cpu(sysp->sdid); + + for (i = 0; i < MYLO_ETHADDR_COUNT; i++) { + int j; + for (j = 0; j < 6; j++) + myloader_info.macs[i][j] = boardp->addr[i].mac[j]; + } + + myloader_found = 1; + +out: + return myloader_found; +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/prom_read.h b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/prom_read.h new file mode 100644 index 0000000..1a6ea11 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/prom_read.h @@ -0,0 +1,50 @@ +/* + * Generic prom definitions + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ADM5120_PROM_H_ +#define _ADM5120_PROM_H_ + +/* + * Helper routines + */ +static inline u16 prom_read_le16(void *buf) +{ + u8 *p = buf; + + return ((u16)p[0] + ((u16)p[1] << 8)); +} + +static inline u32 prom_read_le32(void *buf) +{ + u8 *p = buf; + + return ((u32)p[0] + ((u32)p[1] << 8) + ((u32)p[2] << 16) + + ((u32)p[3] << 24)); +} + +static inline u16 prom_read_be16(void *buf) +{ + u8 *p = buf; + + return (((u16)p[0] << 8) + (u16)p[1]); +} + +static inline u32 prom_read_be32(void *buf) +{ + u8 *p = buf; + + return (((u32)p[0] << 24) + ((u32)p[1] << 16) + ((u32)p[2] << 8) + + ((u32)p[3])); +} + +#endif /* _ADM5120_PROM_H_ */ + + diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/routerboot.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/routerboot.c new file mode 100644 index 0000000..d9a06d9 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/prom/routerboot.c @@ -0,0 +1,121 @@ +/* + * Mikrotik's RouterBOOT specific prom routines + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "prom_read.h" + +struct rb_hard_settings rb_hs; +static int rb_found; + +static int __init routerboot_load_hs(u8 *buf, u16 buflen) +{ + u16 id, len; + + memset(&rb_hs, 0, sizeof(rb_hs)); + + if (buflen < 4) + return -1; + + if (prom_read_le32(buf) != RB_MAGIC_HARD) + return -1; + + /* skip magic value */ + buf += 4; + buflen -= 4; + + while (buflen > 2) { + id = prom_read_le16(buf); + buf += 2; + buflen -= 2; + if (id == RB_ID_TERMINATOR || buflen < 2) + break; + + len = prom_read_le16(buf); + buf += 2; + buflen -= 2; + + if (buflen < len) + break; + + switch (id) { + case RB_ID_BIOS_VERSION: + rb_hs.bios_ver = (char *)buf; + break; + case RB_ID_BOARD_NAME: + rb_hs.name = (char *)buf; + break; + case RB_ID_MEMORY_SIZE: + rb_hs.mem_size = prom_read_le32(buf); + break; + case RB_ID_MAC_ADDRESS_COUNT: + rb_hs.mac_count = prom_read_le32(buf); + break; + case RB_ID_MAC_ADDRESS_PACK: + if ((len / RB_MAC_SIZE) > 0) + rb_hs.mac_base = buf; + break; + } + + buf += len; + buflen -= len; + + } + + return 0; +} + +#define RB_BS_OFFS 0x14 +#define RB_OFFS_MAX (128*1024) + +int __init routerboot_present(void) +{ + struct rb_bios_settings *bs; + u8 *base; + u32 off, len; + + if (rb_found) + goto out; + + base = (u8 *)KSEG1ADDR(ADM5120_SRAM0_BASE); + bs = (struct rb_bios_settings *)(base + RB_BS_OFFS); + + off = prom_read_le32(&bs->hs_offs); + len = prom_read_le32(&bs->hs_size); + if (off > RB_OFFS_MAX) + goto out; + + if (routerboot_load_hs(base+off, len) != 0) + goto out; + + rb_found = 1; + +out: + return rb_found; +} + +char *routerboot_get_boardname(void) +{ + if (rb_found == 0) + return NULL; + + return rb_hs.name; +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/Makefile b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/Makefile new file mode 100644 index 0000000..e8325a1 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/Makefile @@ -0,0 +1,4 @@ +obj-y += p-33x.o + +obj-${CONFIG_ADM5120_MACH_P_334WT} += p-334wt.o +obj-${CONFIG_ADM5120_MACH_P_335} += p-335.o \ No newline at end of file diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-334wt.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-334wt.c new file mode 100644 index 0000000..6cc9aee --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-334wt.c @@ -0,0 +1,34 @@ +/* + * ZyXEL Prestige P-334WT support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "p-33x.h" + +static struct gpio_led p334wt_gpio_leds[] __initdata = { + GPIO_LED_INV(ADM5120_GPIO_PIN2, "power", NULL), + GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan1", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan3", NULL), + GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan4", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL), + GPIO_LED_INV(ADM5120_GPIO_P4L2, "wlan", NULL), + GPIO_LED_INV(ADM5120_GPIO_P2L2, "otist", NULL), + GPIO_LED_INV(ADM5120_GPIO_P1L2, "hidden", NULL), +}; + +static void __init p334wt_setup(void) +{ + p33x_generic_setup(); + adm5120_add_device_gpio_leds(ARRAY_SIZE(p334wt_gpio_leds), + p334wt_gpio_leds); +} + +MIPS_MACHINE(MACH_ADM5120_P334WT, "P-334WT", "ZyXEL Prestige 334WT", + p334wt_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-335.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-335.c new file mode 100644 index 0000000..6ac2b09 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-335.c @@ -0,0 +1,21 @@ +/* + * ZyXEL Prestige P-335/335WT support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "p-33x.h" + +static void __init p335_setup(void) +{ + p33x_generic_setup(); + adm5120_add_device_usb(); +} + +MIPS_MACHINE(MACH_ADM5120_P335, "P-335", "ZyXEL Prestige 335/335WT", + p335_setup); diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-33x.c b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-33x.c new file mode 100644 index 0000000..2626cf9 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-33x.c @@ -0,0 +1,85 @@ +/* + * ZyXEL Prestige P-33x boards support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "p-33x.h" + +#include + +#define P33X_GPIO_FLASH_A20 ADM5120_GPIO_PIN5 +static struct mtd_partition p33x_partitions[] = { + { + .name = "bootbase", + .offset = 0, + .size = 16*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "rom", + .offset = MTDPART_OFS_APPEND, + .size = 16*1024, + .mask_flags = MTD_WRITEABLE, + } , { + .name = "bootext1", + .offset = MTDPART_OFS_APPEND, + .size = 32*1024, + } , { + .name = "bootext2", + .offset = MTDPART_OFS_APPEND, + .size = 64*1024, + } , { + .name = "trx", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } , { + .name = "firmware", + .offset = 32*1024, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct adm5120_pci_irq p33x_pci_irqs[] __initdata = { + PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0), +}; + +static u8 p33x_vlans[6] __initdata = { + /* FIXME: untested */ + 0x50, 0x48, 0x44, 0x42, 0x41, 0x00 +}; + +static void switch_bank_gpio5(unsigned bank) +{ + switch (bank) { + case 0: + gpio_set_value(P33X_GPIO_FLASH_A20, 0); + break; + case 1: + gpio_set_value(P33X_GPIO_FLASH_A20, 1); + break; + } +} + +void __init p33x_generic_setup(void) +{ + /* setup data for flash0 device */ + gpio_request(P33X_GPIO_FLASH_A20, NULL); /* for flash A20 line */ + gpio_direction_output(P33X_GPIO_FLASH_A20, 0); + adm5120_flash0_data.switch_bank = switch_bank_gpio5; + adm5120_flash0_data.nr_parts = ARRAY_SIZE(p33x_partitions); + adm5120_flash0_data.parts = p33x_partitions; + adm5120_add_device_flash(0); + + adm5120_add_device_uart(0); + adm5120_add_device_uart(1); + + adm5120_setup_eth_macs(bootbase_info.mac); + adm5120_add_device_switch(6, p33x_vlans); + + adm5120_pci_set_irq_map(ARRAY_SIZE(p33x_pci_irqs), p33x_pci_irqs); +} diff --git a/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-33x.h b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-33x.h new file mode 100644 index 0000000..8a7340c --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/adm5120/zyxel/p-33x.h @@ -0,0 +1,22 @@ +/* + * ZyXEL Prestige P-33x boards support + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include + +#include +#include + +extern void p33x_generic_setup(void) __init; diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_defs.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_defs.h new file mode 100644 index 0000000..bf220ff --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_defs.h @@ -0,0 +1,53 @@ +/* + * ADM5120 SoC definitions + * + * This file defines some constants specific to the ADM5120 SoC + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _ASM_MIPS_MACH_ADM5120_DEFS_H +#define _ASM_MIPS_MACH_ADM5120_DEFS_H + +#define ADM5120_SDRAM0_BASE 0x00000000 +#define ADM5120_SDRAM1_BASE 0x01000000 +#define ADM5120_SRAM1_BASE 0x10000000 +#define ADM5120_EXTIO0_BASE 0x10C00000 +#define ADM5120_EXTIO0_SIZE 0x00200000 +#define ADM5120_EXTIO1_BASE 0x10E00000 +#define ADM5120_EXTIO1_SIZE 0x00200000 +#define ADM5120_MPMC_BASE 0x11000000 +#define ADM5120_MPMC_SIZE 0x00200000 +#define ADM5120_USBC_BASE 0x11200000 +#define ADM5120_USBC_SIZE 0x00200000 +#define ADM5120_PCIMEM_BASE 0x11400000 +#define ADM5120_PCIMEM_SIZE 0x00100000 +#define ADM5120_PCIIO_BASE 0x11500000 +#define ADM5120_PCIIO_SIZE 0x000FFFF0 +#define ADM5120_PCICFG_ADDR 0x115FFFF0 +#define ADM5120_PCICFG_DATA 0x115FFFF8 +#define ADM5120_PCICFG_SIZE 0x00000010 +#define ADM5120_SWITCH_BASE 0x12000000 +#define ADM5120_SWITCH_SIZE 0x00200000 +#define ADM5120_INTC_BASE 0x12200000 +#define ADM5120_INTC_SIZE 0x00200000 +#define ADM5120_UART0_BASE 0x12600000 +#define ADM5120_UART1_BASE 0x12800000 +#define ADM5120_UART_SIZE 0x00200000 +#define ADM5120_SRAM0_BASE 0x1FC00000 + +#define ADM5120_NAND_BASE ADM5120_SRAM1_BASE +#define ADM5120_NAND_SIZE 0xB + +#define ADM5120_CLK_175 175000000 +#define ADM5120_CLK_200 200000000 +#define ADM5120_CLK_225 225000000 +#define ADM5120_CLK_250 250000000 + +#define ADM5120_UART_CLOCK 62500000 + +#endif /* _ASM_MIPS_MACH_ADM5120_DEFS_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_info.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_info.h new file mode 100644 index 0000000..1d34d80 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_info.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2007-2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MACH_ADM5120_INFO_H +#define _MACH_ADM5120_INFO_H + +#include + +extern unsigned int adm5120_prom_type; +#define ADM5120_PROM_GENERIC 0 +#define ADM5120_PROM_CFE 1 +#define ADM5120_PROM_MYLOADER 2 +#define ADM5120_PROM_ROUTERBOOT 3 +#define ADM5120_PROM_BOOTBASE 4 +#define ADM5120_PROM_UBOOT 5 +#define ADM5120_PROM_LAST 5 + +extern unsigned int adm5120_product_code; +extern unsigned int adm5120_revision; +extern unsigned int adm5120_nand_boot; + +extern unsigned long adm5120_speed; +#define ADM5120_SPEED_175 175000000 +#define ADM5120_SPEED_200 200000000 +#define ADM5120_SPEED_225 225000000 +#define ADM5120_SPEED_250 250000000 + +extern unsigned int adm5120_package; +#define ADM5120_PACKAGE_PQFP 0 +#define ADM5120_PACKAGE_BGA 1 + +extern unsigned long adm5120_memsize; + +enum { + MACH_ADM5120_GENERIC = 0, /* Generic board */ + MACH_ADM5120_5GXI, /* OSBRiDGE 5GXi/5XLi */ + MACH_ADM5120_BR6104K, /* Edimax BR-6104K */ + MACH_ADM5120_BR6104KP, /* Edimax BR-6104KP */ + MACH_ADM5120_BR61X4WG, /* Edimax BR-6104Wg/BR-6114WG */ + MACH_ADM5120_CAS630, /* Cellvision CAS-630/630W */ + MACH_ADM5120_CAS670, /* Cellvision CAS-670/670W */ + MACH_ADM5120_CAS700, /* Cellvision CAS-700/700W */ + MACH_ADM5120_CAS771, /* Cellvision CAS-771/771W */ + MACH_ADM5120_CAS790, /* Cellvision CAS-790 */ + MACH_ADM5120_CAS861, /* Cellvision CAS-861/861W */ + MACH_ADM5120_EASY5120PATA, /* Infineon EASY 5120P-ATA */ + MACH_ADM5120_EASY5120RT, /* Infineon EASY 5120-RT */ + MACH_ADM5120_EASY5120WVOIP, /* Infineon EASY 5120-WVoIP */ + MACH_ADM5120_EASY83000, /* Infineon EASY-83000 */ + MACH_ADM5120_ES2108, /* ZyXEL Ethernet Switch 2108 */ + MACH_ADM5120_ES2108F, /* ZyXEL Ethernet Switch 2108-F */ + MACH_ADM5120_ES2108G, /* ZyXEL Ethernet Switch 2108-G */ + MACH_ADM5120_ES2108LC, /* ZyXEL Ethernet Switch 2108-LC */ + MACH_ADM5120_ES2108PWR, /* ZyXEL Ethernet Switch 2108-PWR */ + MACH_ADM5120_ES2024A, /* ZyXEL Ethernet Switch 2024A */ + MACH_ADM5120_ES2024PWR, /* ZyXEL Ethernet Switch 2024PWR */ + MACH_ADM5120_HS100, /* ZyXEL HomeSafe 100/100W */ + MACH_ADM5120_NFS101U, /* Cellvision NFS-101U/101WU */ + MACH_ADM5120_NFS202U, /* Cellvision NFS-202U/202WU */ + MACH_ADM5120_NP28G, /* Compex NP28G */ + MACH_ADM5120_NP28GHS, /* Compex NP28G HotSpot */ + MACH_ADM5120_NP27G, /* Compex NP27G */ + MACH_ADM5120_RB_11X, /* Mikrotik RouterBOARD 111/112 */ + MACH_ADM5120_RB_133, /* Mikrotik RouterBOARD 133 */ + MACH_ADM5120_RB_133C, /* Mikrotik RouterBOARD 133c */ + MACH_ADM5120_RB_150, /* Mikrotik RouterBOARD 150 */ + MACH_ADM5120_RB_153, /* Mikrotik RouterBOARD 153 */ + MACH_ADM5120_RB_192, /* Mikrotik RouterBOARD 192 */ + MACH_ADM5120_P334U, /* ZyXEL Prestige 334U */ + MACH_ADM5120_P334W, /* ZyXEL Prestige 334W */ + MACH_ADM5120_P334WH, /* ZyXEL Prestige 334WH */ + MACH_ADM5120_P334WHD, /* ZyXEL Prestige 334WHD */ + MACH_ADM5120_P334WT, /* ZyXEL Prestige 334WT */ + MACH_ADM5120_P335, /* ZyXEL Prestige 335/335WT */ + MACH_ADM5120_P335PLUS, /* ZyXEL Prestige 335Plus */ + MACH_ADM5120_P335U, /* ZyXEL Prestige 335U */ + MACH_ADM5120_PMUGW, /* Motorola Powerline MU Gateway */ + MACH_ADM5120_WP54, /* Compex WP54G/WP54AG/WPP54G/WPP54AG */ + MACH_ADM5120_WP54G_WRT, /* Compex WP54G-WRT */ + MACH_ADM5120_WP54Gv1C, /* Compex WP54G version 1C */ + MACH_ADM5120_EB_214A, /* Generic EB-214A */ +}; + +/* + * TODO:remove adm5120_eth* variables when the switch driver will be + * converted into a real platform driver + */ +extern unsigned int adm5120_eth_num_ports; +extern unsigned char adm5120_eth_macs[6][6]; +extern unsigned char adm5120_eth_vlans[6]; + +extern void adm5120_soc_init(void) __init; +extern void adm5120_mem_init(void) __init; +extern void adm5120_ndelay(u32 ns); + +extern void (*adm5120_board_reset)(void); + +extern void adm5120_gpio_init(void) __init; +extern void adm5120_gpio_csx0_enable(void) __init; +extern void adm5120_gpio_csx1_enable(void) __init; +extern void adm5120_gpio_ew_enable(void) __init; + +static inline int adm5120_package_pqfp(void) +{ + return (adm5120_package == ADM5120_PACKAGE_PQFP); +} + +static inline int adm5120_package_bga(void) +{ + return (adm5120_package == ADM5120_PACKAGE_BGA); +} + +static inline int adm5120_has_pci(void) +{ + return (adm5120_package == ADM5120_PACKAGE_BGA); +} + +static inline int adm5120_has_gmii(void) +{ + return (adm5120_package == ADM5120_PACKAGE_BGA); +} + +#endif /* _MACH_ADM5120_INFO_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_intc.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_intc.h new file mode 100644 index 0000000..70dd6bb --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_intc.h @@ -0,0 +1,63 @@ +/* + * ADM5120 interrupt controller definitions + * + * This header file defines the hardware registers of the ADM5120 SoC + * built-in interrupt controller. + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MACH_ADM5120_INTC_H +#define _MACH_ADM5120_INTC_H + +/* + * INTC register offsets + */ +#define INTC_REG_IRQ_STATUS 0x00 /* Interrupt status after masking */ +#define INTC_REG_IRQ_RAW_STATUS 0x04 /* Interrupt status before masking */ +#define INTC_REG_IRQ_ENABLE 0x08 /* Used to enable the interrupt sources */ +#define INTC_REG_IRQ_ENABLE_CLEAR 0x0C /* Used to disable the interrupt sources */ +#define INTC_REG_IRQ_DISABLE INTC_REG_IRQ_ENABLE_CLEAR +#define INTC_REG_INT_MODE 0x14 /* The interrupt mode of the sources */ +#define INTC_REG_FIQ_STATUS 0x18 /* FIQ status */ +#define INTC_REG_IRQ_TEST_SOURCE 0x1C +#define INTC_REG_IRQ_SOURCE_SELECT 0x20 +#define INTC_REG_INT_LEVEL 0x24 + +/* + * INTC IRQ numbers + */ +#define INTC_IRQ_TIMER 0 /* built in timer */ +#define INTC_IRQ_UART0 1 /* built-in UART0 */ +#define INTC_IRQ_UART1 2 /* built-in UART1 */ +#define INTC_IRQ_USBC 3 /* USB Host Controller */ +#define INTC_IRQ_GPIO2 4 /* GPIO line 2 */ +#define INTC_IRQ_GPIO4 5 /* GPIO line 4 */ +#define INTC_IRQ_PCI0 6 /* PCI slot 2 */ +#define INTC_IRQ_PCI1 7 /* PCI slot 3 */ +#define INTC_IRQ_PCI2 8 /* PCI slot 4 */ +#define INTC_IRQ_SWITCH 9 /* built-in ethernet switch */ +#define INTC_IRQ_LAST INTC_IRQ_SWITCH +#define INTC_IRQ_COUNT 10 + +/* + * INTC register bits + */ +#define INTC_INT_TIMER (1 << INTC_IRQ_TIMER) +#define INTC_INT_UART0 (1 << INTC_IRQ_UART0) +#define INTC_INT_UART1 (1 << INTC_IRQ_UART1) +#define INTC_INT_USBC (1 << INTC_IRQ_USBC) +#define INTC_INT_INTX0 (1 << INTC_IRQ_INTX0) +#define INTC_INT_INTX1 (1 << INTC_IRQ_INTX1) +#define INTC_INT_PCI0 (1 << INTC_IRQ_PCI0) +#define INTC_INT_PCI1 (1 << INTC_IRQ_PCI1) +#define INTC_INT_PCI2 (1 << INTC_IRQ_PCI2) +#define INTC_INT_SWITCH (1 << INTC_IRQ_SWITCH) +#define INTC_INT_ALL ((1 << INTC_IRQ_COUNT) - 1) + +#endif /* _MACH_ADM5120_INTC_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_mpmc.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_mpmc.h new file mode 100644 index 0000000..c4e9591 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_mpmc.h @@ -0,0 +1,92 @@ +/* + * ADM5120 MPMC (Multiport Memory Controller) register definitions + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MACH_ADM5120_MPMC_H +#define _MACH_ADM5120_MPMC_H + +#define MPMC_READ_REG(r) __raw_readl( \ + (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r) +#define MPMC_WRITE_REG(r, v) __raw_writel((v), \ + (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r) + +#define MPMC_REG_CTRL 0x0000 +#define MPMC_REG_STATUS 0x0004 +#define MPMC_REG_CONF 0x0008 +#define MPMC_REG_DC 0x0020 +#define MPMC_REG_DR 0x0024 +#define MPMC_REG_DRP 0x0030 + +#define MPMC_REG_DC0 0x0100 +#define MPMC_REG_DRC0 0x0104 +#define MPMC_REG_DC1 0x0120 +#define MPMC_REG_DRC1 0x0124 +#define MPMC_REG_DC2 0x0140 +#define MPMC_REG_DRC2 0x0144 +#define MPMC_REG_DC3 0x0160 +#define MPMC_REG_DRC3 0x0164 +#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */ +#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */ +#define MPMC_REG_SC2 0x0240 +#define MPMC_REG_WEN2 0x0244 +#define MPMC_REG_OEN2 0x0248 +#define MPMC_REG_RD2 0x024C +#define MPMC_REG_PG2 0x0250 +#define MPMC_REG_WR2 0x0254 +#define MPMC_REG_TN2 0x0258 +#define MPMC_REG_SC3 0x0260 + +/* Control register bits */ +#define MPMC_CTRL_AM (1 << 1) /* Address Mirror */ +#define MPMC_CTRL_LPM (1 << 2) /* Low Power Mode */ +#define MPMC_CTRL_DWB (1 << 3) /* Drain Write Buffers */ + +/* Status register bits */ +#define MPMC_STATUS_BUSY (1 << 0) /* Busy */ +#define MPMC_STATUS_WBS (1 << 1) /* Write Buffer Status */ +#define MPMC_STATUS_SRA (1 << 2) /* Self-Refresh Acknowledge*/ + +/* Dynamic Control register bits */ +#define MPMC_DC_CE (1 << 0) +#define MPMC_DC_DMC (1 << 1) +#define MPMC_DC_SRR (1 << 2) +#define MPMC_DC_SI_SHIFT 7 +#define MPMC_DC_SI_MASK (3 << 7) +#define MPMC_DC_SI_NORMAL (0 << 7) +#define MPMC_DC_SI_MODE (1 << 7) +#define MPMC_DC_SI_PALL (2 << 7) +#define MPMC_DC_SI_NOP (3 << 7) + +#define SRAM_REG_CONF 0x00 +#define SRAM_REG_WWE 0x04 +#define SRAM_REG_WOE 0x08 +#define SRAM_REG_WRD 0x0C +#define SRAM_REG_WPG 0x10 +#define SRAM_REG_WWR 0x14 +#define SRAM_REG_WTR 0x18 + +/* Dynamic Configuration register bits */ +#define DC_BE (1 << 19) /* buffer enable */ +#define DC_RW_SHIFT 28 /* shift for number of rows */ +#define DC_RW_MASK 0x03 +#define DC_NB_SHIFT 26 /* shift for number of banks */ +#define DC_NB_MASK 0x01 +#define DC_CW_SHIFT 22 /* shift for number of columns */ +#define DC_CW_MASK 0x07 +#define DC_DW_SHIFT 7 /* shift for device width */ +#define DC_DW_MASK 0x03 + +/* Static Configuration register bits */ +#define SC_MW_MASK 0x03 /* memory width mask */ +#define SC_MW_8 0x00 /* 8 bit memory width */ +#define SC_MW_16 0x01 /* 16 bit memory width */ +#define SC_MW_32 0x02 /* 32 bit memory width */ + +#endif /* _MACH_ADM5120_MPMC_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_nand.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_nand.h new file mode 100644 index 0000000..1e2f3bd --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_nand.h @@ -0,0 +1,89 @@ +/* + * ADM5120 NAND interface definitions + * + * This header file defines the hardware registers of the ADM5120 SoC + * built-in NAND interface. + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * NAND interface routines was based on a driver for Linux 2.6.19+ which + * was derived from the driver for Linux 2.4.xx published by Mikrotik for + * their RouterBoard 1xx and 5xx series boards. + * Copyright (C) 2007 David Goodenough + * Copyright (C) 2007 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MACH_ADM5120_NAND_H +#define _MACH_ADM5120_NAND_H + +#include +#include + +#include +#include + +/* NAND control registers */ +#define NAND_REG_DATA 0x0 /* data register */ +#define NAND_REG_SET_CEn 0x1 /* CE# low */ +#define NAND_REG_CLR_CEn 0x2 /* CE# high */ +#define NAND_REG_CLR_CLE 0x3 /* CLE low */ +#define NAND_REG_SET_CLE 0x4 /* CLE high */ +#define NAND_REG_CLR_ALE 0x5 /* ALE low */ +#define NAND_REG_SET_ALE 0x6 /* ALE high */ +#define NAND_REG_SET_SPn 0x7 /* SP# low (use spare area) */ +#define NAND_REG_CLR_SPn 0x8 /* SP# high (do not use spare area) */ +#define NAND_REG_SET_WPn 0x9 /* WP# low */ +#define NAND_REG_CLR_WPn 0xA /* WP# high */ +#define NAND_REG_STATUS 0xB /* Status register */ + +#define ADM5120_NAND_STATUS_READY 0x80 + +#define NAND_READ_REG(r) \ + readb((void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r)) +#define NAND_WRITE_REG(r, v) \ + writeb((v), (void __iomem *)KSEG1ADDR(ADM5120_NAND_BASE) + (r)) + +/*-------------------------------------------------------------------------*/ + +static inline void adm5120_nand_enable(void) +{ + SW_WRITE_REG(SWITCH_REG_BW_CNTL1, BW_CNTL1_NAND_ENABLE); + SW_WRITE_REG(SWITCH_REG_BOOT_DONE, 1); +} + +static inline void adm5120_nand_set_wpn(unsigned int set) +{ + NAND_WRITE_REG((set) ? NAND_REG_SET_WPn : NAND_REG_CLR_WPn, 1); +} + +static inline void adm5120_nand_set_spn(unsigned int set) +{ + NAND_WRITE_REG((set) ? NAND_REG_SET_SPn : NAND_REG_CLR_SPn, 1); +} + +static inline void adm5120_nand_set_cle(unsigned int set) +{ + NAND_WRITE_REG((set) ? NAND_REG_SET_CLE : NAND_REG_CLR_CLE, 1); +} + +static inline void adm5120_nand_set_ale(unsigned int set) +{ + NAND_WRITE_REG((set) ? NAND_REG_SET_ALE : NAND_REG_CLR_ALE, 1); +} + +static inline void adm5120_nand_set_cen(unsigned int set) +{ + NAND_WRITE_REG((set) ? NAND_REG_SET_CEn : NAND_REG_CLR_CEn, 1); +} + +static inline u8 adm5120_nand_get_status(void) +{ + return NAND_READ_REG(NAND_REG_STATUS); +} + +#endif /* _MACH_ADM5120_NAND_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_platform.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_platform.h new file mode 100644 index 0000000..ed73b53 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_platform.h @@ -0,0 +1,87 @@ +/* + * ADM5120 specific platform definitions + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ASM_MIPS_MACH_ADM5120_PLATFORM_H +#define _ASM_MIPS_MACH_ADM5120_PLATFORM_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct adm5120_flash_platform_data { + void (*set_vpp)(struct map_info *, int); + void (*switch_bank)(unsigned); + u32 window_size; + unsigned int nr_parts; + struct mtd_partition *parts; +}; + +struct adm5120_switch_platform_data { + /* TODO: not yet implemented */ +}; + +struct adm5120_pci_irq { + u8 slot; + u8 func; + u8 pin; + unsigned irq; +}; + +#define PCIIRQ(s, f, p, i) {.slot = (s), .func = (f), .pin = (p), .irq = (i)} + +#ifdef CONFIG_PCI +extern void adm5120_pci_set_irq_map(unsigned int nr_irqs, + struct adm5120_pci_irq *map) __init; +#else +static inline void adm5120_pci_set_irq_map(unsigned int nr_irqs, + struct adm5120_pci_irq *map) +{ +} +#endif + +extern void adm5120_setup_eth_macs(u8 *mac_base) __init; + +extern struct adm5120_flash_platform_data adm5120_flash0_data; +extern struct adm5120_flash_platform_data adm5120_flash1_data; + +extern void adm5120_add_device_flash(unsigned id) __init; +extern void adm5120_add_device_usb(void) __init; +extern void adm5120_add_device_uart(unsigned id) __init; +extern void adm5120_add_device_nand(struct platform_nand_data *pdata) __init; +extern void adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map) __init; +extern void adm5120_register_gpio_buttons(int id, + unsigned poll_interval, + unsigned nbuttons, + struct gpio_keys_button *buttons); + +#define GPIO_LED_DEF(g, n, t, a) { \ + .name = (n), \ + .default_trigger = (t), \ + .gpio = (g), \ + .active_low = (a) \ +} + +#define GPIO_LED_STD(g, n, t) GPIO_LED_DEF((g), (n), (t), 0) +#define GPIO_LED_INV(g, n, t) GPIO_LED_DEF((g), (n), (t), 1) + +extern void adm5120_add_device_gpio_leds(unsigned num_leds, + struct gpio_led *leds) __init; + +#endif /* _ASM_MIPS_MACH_ADM5120_PLATFORM_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_switch.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_switch.h new file mode 100644 index 0000000..91adc5b --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_switch.h @@ -0,0 +1,300 @@ +/* + * ADM5120 ethernet switch definitions + * + * This header file defines the hardware registers of the ADM5120 SoC + * built-in Ethernet switch. + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MACH_ADM5120_SWITCH_H +#define _MACH_ADM5120_SWITCH_H + +#ifndef BIT +# define BIT(at) (1 << (at)) +#endif +#define BITMASK(len) (BIT(len)-1) + +#define SW_READ_REG(r) __raw_readl( \ + (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r) +#define SW_WRITE_REG(r, v) __raw_writel((v), \ + (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE) + r) + +/* Switch register offsets */ +#define SWITCH_REG_CODE 0x0000 +#define SWITCH_REG_SOFT_RESET 0x0004 /* Soft Reset */ +#define SWITCH_REG_BOOT_DONE 0x0008 /* Boot Done */ +#define SWITCH_REG_SW_RESET 0x000C /* Switch Reset */ +#define SWITCH_REG_PHY_STATUS 0x0014 /* PHY Status */ +#define SWITCH_REG_MEMCTRL 0x001C /* Memory Control */ +#define SWITCH_REG_CPUP_CONF 0x0024 /* CPU Port Configuration */ +#define SWITCH_REG_PORT_CONF0 0x0028 /* Port Configuration 0 */ +#define SWITCH_REG_PORT_CONF1 0x002C /* Port Configuration 1 */ +#define SWITCH_REG_PORT_CONF2 0x0030 /* Port Configuration 2 */ +#define SWITCH_REG_VLAN_G1 0x0040 /* VLAN group 1 */ +#define SWITCH_REG_VLAN_G2 0x0044 /* VLAN group 2 */ +#define SWITCH_REG_SEND_TRIG 0x0048 /* Send Trigger */ +#define SWITCH_REG_MAC_WT0 0x0058 /* MAC Write Address 0 */ +#define SWITCH_REG_MAC_WT1 0x005C /* MAC Write Address 1 */ +#define SWITCH_REG_BW_CNTL0 0x0060 /* Bandwidth Control 0 */ +#define SWITCH_REG_BW_CNTL1 0x0064 /* Bandwidth Control 1 */ +#define SWITCH_REG_PHY_CNTL0 0x0068 /* PHY Control 0 */ +#define SWITCH_REG_PHY_CNTL1 0x006C /* PHY Control 1 */ +#define SWITCH_REG_PORT_TH 0x0078 /* Port Threshold */ +#define SWITCH_REG_PHY_CNTL2 0x007C /* PHY Control 2 */ +#define SWITCH_REG_PHY_CNTL3 0x0080 /* PHY Control 3 */ +#define SWITCH_REG_PRI_CNTL 0x0084 /* Priority Control */ +#define SWITCH_REG_PHY_CNTL4 0x00A0 /* PHY Control 4 */ +#define SWITCH_REG_EMPTY_CNT 0x00A4 /* Empty Count */ +#define SWITCH_REG_PORT_CNTLS 0x00A8 /* Port Control Select */ +#define SWITCH_REG_PORT_CNTL 0x00AC /* Port Control */ +#define SWITCH_REG_INT_STATUS 0x00B0 /* Interrupt Status */ +#define SWITCH_REG_INT_MASK 0x00B4 /* Interrupt Mask */ +#define SWITCH_REG_GPIO_CONF0 0x00B8 /* GPIO Configuration 0 */ +#define SWITCH_REG_GPIO_CONF2 0x00BC /* GPIO Configuration 1 */ +#define SWITCH_REG_WDOG0 0x00C0 /* Watchdog 0 */ +#define SWITCH_REG_WDOG1 0x00C4 /* Watchdog 1 */ + +#define SWITCH_REG_SHDA 0x00D0 /* Send High Descriptors Address */ +#define SWITCH_REG_SLDA 0x00D4 /* Send Low Descriptors Address */ +#define SWITCH_REG_RHDA 0x00D8 /* Receive High Descriptor Address */ +#define SWITCH_REG_RLDA 0x00DC /* Receive Low Descriptor Address */ +#define SWITCH_REG_SHWA 0x00E0 /* Send High Working Address */ +#define SWITCH_REG_SLWA 0x00E4 /* Send Low Working Address */ +#define SWITCH_REG_RHWA 0x00E8 /* Receive High Working Address */ +#define SWITCH_REG_RLWA 0x00EC /* Receive Low Working Address */ + +#define SWITCH_REG_TIMER_INT 0x00F0 /* Timer */ +#define SWITCH_REG_TIMER 0x00F4 /* Timer Interrupt */ + +#define SWITCH_REG_PORT0_LED 0x0100 +#define SWITCH_REG_PORT1_LED 0x0104 +#define SWITCH_REG_PORT2_LED 0x0108 +#define SWITCH_REG_PORT3_LED 0x010C +#define SWITCH_REG_PORT4_LED 0x0110 + +/* CODE register bits */ +#define CODE_PC_MASK BITMASK(16) /* Product Code */ +#define CODE_REV_SHIFT 16 +#define CODE_REV_MASK BITMASK(4) /* Product Revision */ +#define CODE_CLKS_SHIFT 20 +#define CODE_CLKS_MASK BITMASK(2) /* Clock Speed */ +#define CODE_CLKS_175 0 /* 175 MHz */ +#define CODE_CLKS_200 1 /* 200 MHz */ +#define CODE_CLKS_225 2 /* 225 MHz */ +#define CODE_CLKS_250 3 /* 250 MHz */ +#define CODE_NAB BIT(24) /* NAND boot */ +#define CODE_PK_MASK BITMASK(1) /* Package type */ +#define CODE_PK_SHIFT 29 +#define CODE_PK_BGA 0 /* BGA package */ +#define CODE_PK_PQFP 1 /* PQFP package */ + +/* MEMCTRL register bits */ +#define MEMCTRL_SDRS_MASK BITMASK(3) /* SDRAM bank size */ +#define MEMCTRL_SDRS_4M 0x01 +#define MEMCTRL_SDRS_8M 0x02 +#define MEMCTRL_SDRS_16M 0x03 +#define MEMCTRL_SDRS_64M 0x04 +#define MEMCTRL_SDRS_128M 0x05 +#define MEMCTRL_SDR1_ENABLE BIT(5) /* enable SDRAM bank 1 */ + +#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */ +#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */ +#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */ +#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */ +#define MEMCTRL_SRS_512K 0x01 /* 512KB*/ +#define MEMCTRL_SRS_1M 0x02 /* 1MB */ +#define MEMCTRL_SRS_2M 0x03 /* 2MB */ +#define MEMCTRL_SRS_4M 0x04 /* 4MB */ + +/* Port bits used in various registers */ +#define SWITCH_PORT_PHY0 BIT(0) +#define SWITCH_PORT_PHY1 BIT(1) +#define SWITCH_PORT_PHY2 BIT(2) +#define SWITCH_PORT_PHY3 BIT(3) +#define SWITCH_PORT_PHY4 BIT(4) +#define SWITCH_PORT_MII BIT(5) +#define SWITCH_PORT_CPU BIT(6) + +/* Port bit shorthands */ +#define SWITCH_PORTS_PHY 0x1F /* phy ports */ +#define SWITCH_PORTS_NOCPU 0x3F /* physical ports */ +#define SWITCH_PORTS_ALL 0x7F /* all ports */ + +/* CPUP_CONF register bits */ +#define CPUP_CONF_DCPUP BIT(0) /* Disable CPU port */ +#define CPUP_CONF_CRCP BIT(1) /* CRC padding from CPU */ +#define CPUP_CONF_BTM BIT(2) /* Bridge Testing Mode */ +#define CPUP_CONF_DUNP_SHIFT 9 /* Disable Unknown Packets for portX */ +#define CPUP_CONF_DMCP_SHIFT 16 /* Disable Mcast Packets form portX */ +#define CPUP_CONF_DBCP_SHIFT 24 /* Disable Bcast Packets form portX */ + +/* PORT_CONF0 register bits */ +#define PORT_CONF0_DP_SHIFT 0 /* Disable Port */ +#define PORT_CONF0_EMCP_SHIFT 8 /* Enable All MC Packets */ +#define PORT_CONF0_BP_SHIFT 16 /* Enable Back Pressure */ + +/* PORT_CONF1 register bits */ +#define PORT_CONF1_DISL_SHIFT 0 /* Disable Learning */ +#define PORT_CONF1_BS_SHIFT 6 /* Blocking State */ +#define PORT_CONF1_BM_SHIFT 12 /* Blocking Mode */ + +/* SEND_TRIG register bits */ +#define SEND_TRIG_STL BIT(0) /* Send Trigger Low */ +#define SEND_TRIG_STH BIT(1) /* Send Trigger High */ + +/* MAC_WT0 register bits */ +#define MAC_WT0_MAWC BIT(0) /* MAC address write command */ +#define MAC_WT0_MWD_SHIFT 1 +#define MAC_WT0_MWD BIT(1) /* MAC write done */ +#define MAC_WT0_WFB BIT(2) /* Write Filter Bit */ +#define MAC_WT0_WVN_SHIFT 3 /* Write Vlan Number shift */ +#define MAC_WT0_WVE BIT(6) /* Write VLAN enable */ +#define MAC_WT0_WPMN_SHIFT 7 +#define MAC_WT0_WAF_SHIFT 13 /* Write Age Field shift */ +#define MAC_WT0_WAF_EMPTY 0 +#define MAC_WT0_WAF_STATIC 7 /* age: static */ +#define MAC_WT0_MAC0_SHIFT 16 +#define MAC_WT0_MAC1_SHIFT 24 + +/* MAC_WT1 register bits */ +#define MAC_WT1_MAC2_SHIFT 0 +#define MAC_WT1_MAC3_SHIFT 8 +#define MAC_WT1_MAC4_SHIFT 16 +#define MAC_WT1_MAC5_SHIFT 24 + +/* BW_CNTL0/BW_CNTL1 register bits */ +#define BW_CNTL_DISABLE 0x00 +#define BW_CNTL_64K 0x01 +#define BW_CNTL_128K 0x02 +#define BW_CNTL_256K 0x03 +#define BW_CNTL_512K 0x04 +#define BW_CNTL_1M 0x05 +#define BW_CNTL_4M 0x06 +#define BW_CNTL_10M 0x07 + +#define P4TBC_SHIFT 0 +#define P4RBC_SHIFT 4 +#define P5TBC_SHIFT 8 +#define P5RBC_SHIFT 12 + +#define BW_CNTL1_NAND_ENABLE 0x100 + +/* PHY_CNTL0 register bits */ +#define PHY_CNTL0_PHYA_MASK BITMASK(5) +#define PHY_CNTL0_PHYR_MASK BITMASK(5) +#define PHY_CNTL0_PHYR_SHIFT 8 +#define PHY_CNTL0_WC BIT(13) /* Write Command */ +#define PHY_CNTL0_RC BIT(14) /* Read Command */ +#define PHY_CNTL0_WTD_MASK BIT(16) /* Read Command */ +#define PHY_CNTL0_WTD_SHIFT 16 + +/* PHY_CNTL1 register bits */ +#define PHY_CNTL1_WOD BIT(0) /* Write Operation Done */ +#define PHY_CNTL1_ROD BIT(1) /* Read Operation Done */ +#define PHY_CNTL1_RD_MASK BITMASK(16) +#define PHY_CNTL1_RD_SHIFT 16 + +/* PHY_CNTL2 register bits */ +#define PHY_CNTL2_ANE_SHIFT 0 /* Auto Negotiation Enable */ +#define PHY_CNTL2_SC_SHIFT 5 /* Speed Control */ +#define PHY_CNTL2_DC_SHIFT 10 /* Duplex Control */ +#define PHY_CNTL2_FNCV_SHIFT 15 /* Recommended FC Value */ +#define PHY_CNTL2_PHYR_SHIFT 20 /* PHY reset */ +#define PHY_CNTL2_AMDIX_SHIFT 25 /* Auto MDIX enable */ +/* PHY_CNTL2_RMAE is bad in datasheet */ +#define PHY_CNTL2_RMAE BIT(31) /* Recommended MCC Average enable */ + +/* PHY_CNTL3 register bits */ +#define PHY_CNTL3_RNT BIT(10) /* Recommend Normal Threshold */ + +/* PORT_TH register bits */ +#define PORT_TH_PPT_MASK BITMASK(8) /* Per Port Threshold */ +#define PORT_TH_CPUT_SHIFT 8 /* CPU Port Buffer Threshold */ +#define PORT_TH_CPUT_MASK BITMASK(8) +#define PORT_TH_CPUHT_SHIFT 16 /* CPU Hold Threshold */ +#define PORT_TH_CPUHT_MASK BITMASK(8) +#define PORT_TH_CPURT_SHIFT 24 /* CPU Release Threshold */ +#define PORT_TH_CPURT_MASK BITMASK(8) + +/* EMPTY_CNT register bits */ +#define EMPTY_CNT_EBGB_MASK BITMASK(9) /* Empty Blocks in the Global Buffer */ + +/* GPIO_CONF0 register bits */ +#define GPIO_CONF0_MASK BITMASK(8) +#define GPIO_CONF0_IM_SHIFT 0 +#define GPIO_CONF0_IV_SHIFT 8 +#define GPIO_CONF0_OE_SHIFT 16 +#define GPIO_CONF0_OV_SHIFT 24 +#define GPIO_CONF0_IM_MASK (0xFF << GPIO_CONF0_IM_SHIFT) +#define GPIO_CONF0_IV_MASK (0xFF << GPIO_CONF0_IV_SHIFT) +#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT) +#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT) + +/* GPIO_CONF2 register bits */ +#define GPIO_CONF2_CSX0 BIT(4) /* enable CSX0:INTX0 on GPIO 1:2 */ +#define GPIO_CONF2_CSX1 BIT(5) /* enable CSX1:INTX1 on GPIO 3:4 */ +#define GPIO_CONF2_EW BIT(6) /* enable wait state pin for CSX0/1 */ + +/* INT_STATUS/INT_MASK register bits */ +#define SWITCH_INT_SHD BIT(0) /* Send High Done */ +#define SWITCH_INT_SLD BIT(1) /* Send Low Done */ +#define SWITCH_INT_RHD BIT(2) /* Receive High Done */ +#define SWITCH_INT_RLD BIT(3) /* Receive Low Done */ +#define SWITCH_INT_HDF BIT(4) /* High Descriptor Full */ +#define SWITCH_INT_LDF BIT(5) /* Low Descriptor Full */ +#define SWITCH_INT_P0QF BIT(6) /* Port0 Queue Full */ +#define SWITCH_INT_P1QF BIT(7) /* Port1 Queue Full */ +#define SWITCH_INT_P2QF BIT(8) /* Port2 Queue Full */ +#define SWITCH_INT_P3QF BIT(9) /* Port3 Queue Full */ +#define SWITCH_INT_P4QF BIT(10) /* Port4 Queue Full */ +#define SWITCH_INT_P5QF BIT(11) /* Port5 Queue Full */ +#define SWITCH_INT_CPQF BIT(13) /* CPU Queue Full */ +#define SWITCH_INT_GQF BIT(14) /* Global Queue Full */ +#define SWITCH_INT_MD BIT(15) /* Must Drop */ +#define SWITCH_INT_BCS BIT(16) /* BC Storm */ +#define SWITCH_INT_PSC BIT(18) /* Port Status Change */ +#define SWITCH_INT_ID BIT(19) /* Intruder Detected */ +#define SWITCH_INT_W0TE BIT(20) /* Watchdog 0 Timer Expired */ +#define SWITCH_INT_W1TE BIT(21) /* Watchdog 1 Timer Expired */ +#define SWITCH_INT_RDE BIT(22) /* Receive Descriptor Error */ +#define SWITCH_INT_SDE BIT(23) /* Send Descriptor Error */ +#define SWITCH_INT_CPUH BIT(24) /* CPU Hold */ + +/* TIMER_INT register bits */ +#define TIMER_INT_TOS BIT(0) /* time-out status */ +#define TIMER_INT_TOM BIT(16) /* mask time-out interrupt */ + +/* TIMER register bits */ +#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */ +#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */ +#define TIMER_TE BIT(16) /* timer enable bit */ + +/* PORTx_LED register bits */ +#define LED_MODE_MASK BITMASK(4) +#define LED_MODE_INPUT 0 +#define LED_MODE_FLASH 1 +#define LED_MODE_OUT_HIGH 2 +#define LED_MODE_OUT_LOW 3 +#define LED_MODE_LINK 4 +#define LED_MODE_SPEED 5 +#define LED_MODE_DUPLEX 6 +#define LED_MODE_ACT 7 +#define LED_MODE_COLL 8 +#define LED_MODE_LINK_ACT 9 +#define LED_MODE_DUPLEX_COLL 10 +#define LED_MODE_10M_ACT 11 +#define LED_MODE_100M_ACT 12 +#define LED0_MODE_SHIFT 0 /* LED0 mode shift */ +#define LED1_MODE_SHIFT 4 /* LED1 mode shift */ +#define LED2_MODE_SHIFT 8 /* LED2 mode shift */ +#define LED0_IV_SHIFT 12 /* LED0 input value shift */ +#define LED1_IV_SHIFT 13 /* LED1 input value shift */ +#define LED2_IV_SHIFT 14 /* LED2 input value shift */ + +#endif /* _MACH_ADM5120_SWITCH_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_uart.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_uart.h new file mode 100644 index 0000000..81d3067 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/adm5120_uart.h @@ -0,0 +1,64 @@ +/* + * ADM5120 UART definitions + * + * This header file defines the hardware registers of the ADM5120 SoC + * built-in UARTs. + * + * Copyright (C) 2007 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MACH_ADM5120_UART_H +#define _MACH_ADM5120_UART_H + +#define UART_BAUDDIV(clk, baud) ((clk/(16 * (baud)))-1) + +#define UART_REG_DATA 0x00 +#define UART_REG_RSR 0x04 +#define UART_REG_ECR UART_REG_RSR +#define UART_REG_LCRH 0x08 +#define UART_REG_LCRM 0x0C +#define UART_REG_LCRL 0x10 +#define UART_REG_CTRL 0x14 +#define UART_REG_FLAG 0x18 + +/* Receive Status Register bits */ +#define UART_RSR_FE (1 << 0) +#define UART_RSR_PE (1 << 1) +#define UART_RSR_BE (1 << 2) +#define UART_RSR_OE (1 << 3) +#define UART_RSR_ERR (UART_RSR_FE | UART_RSR_PE | UART_RSR_BE) + +#define UART_ECR_ALL 0xFF + +/* Line Control High register bits */ +#define UART_LCRH_BRK (1 << 0) /* send break */ +#define UART_LCRH_PEN (1 << 1) /* parity enable */ +#define UART_LCRH_EPS (1 << 2) /* even parity select */ +#define UART_LCRH_STP1 (0 << 3) /* one stop bits select */ +#define UART_LCRH_STP2 (1 << 3) /* two stop bits select */ +#define UART_LCRH_FEN (1 << 4) /* FIFO enable */ + +#define UART_LCRH_WLEN5 (0 << 5) +#define UART_LCRH_WLEN6 (1 << 5) +#define UART_LCRH_WLEN7 (2 << 5) +#define UART_LCRH_WLEN8 (3 << 5) + +/* Control register bits */ +#define UART_CTRL_EN (1 << 0) + +/* Flag register bits */ +#define UART_FLAG_CTS (1 << 0) +#define UART_FLAG_DSR (1 << 1) +#define UART_FLAG_DCD (1 << 2) +#define UART_FLAG_BUSY (1 << 3) +#define UART_FLAG_RXFE (1 << 4) +#define UART_FLAG_TXFF (1 << 5) +#define UART_FLAG_RXFF (1 << 6) +#define UART_FLAG_TXFE (1 << 7) + +#endif /* _MACH_ADM5120_UART_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/asm/sizes.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/asm/sizes.h new file mode 100644 index 0000000..503843d --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/asm/sizes.h @@ -0,0 +1,56 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size definitions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_16 0x00000010 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif + +/* END */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/cpu-feature-overrides.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/cpu-feature-overrides.h new file mode 100644 index 0000000..c6310cc --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/cpu-feature-overrides.h @@ -0,0 +1,71 @@ +/* + * ADM5120 specific CPU feature overrides + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: include/asm-mips/cpu-features.h + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H + +/* + * The ADM5120 SOC has a built-in MIPS 4Kc core. + */ +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +/* #define cpu_has_vce ? */ +/* #define cpu_has_cache_cdex_p ? */ +/* #define cpu_has_cache_cdex_s ? */ +#define cpu_has_prefetch 1 +/* #define cpu_has_mcheck ? */ +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 + +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 + +/* #define cpu_has_vtag_icache ? */ +/* #define cpu_has_dc_aliases ? */ +/* #define cpu_has_ic_fills_f_dc ? */ +/* #define cpu_has_pindexed_dcache ? */ + +/* #define cpu_icache_snoops_remote_store ? */ + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 + +/* #define cpu_has_nofpuex ? */ +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 +#define cpu_has_64bit_gp_regs 0 +#define cpu_has_64bit_addresses 0 + +/* #define cpu_has_inclusive_pcaches ? */ + +#define cpu_dcache_line_size() 16 +#define cpu_icache_line_size() 16 + +#endif /* __ASM_MACH_ADM5120_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/gpio.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/gpio.h new file mode 100644 index 0000000..7ba7efc --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/gpio.h @@ -0,0 +1,115 @@ +/* + * ADM5120 GPIO wrappers for arch-neutral GPIO calls + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ASM_MIPS_MACH_ADM5120_GPIO_H +#define _ASM_MIPS_MACH_ADM5120_GPIO_H + +#define ARCH_NR_GPIOS 64 + +#include + +#include + +#define ADM5120_GPIO_PIN0 0 +#define ADM5120_GPIO_PIN1 1 +#define ADM5120_GPIO_PIN2 2 +#define ADM5120_GPIO_PIN3 3 +#define ADM5120_GPIO_PIN4 4 +#define ADM5120_GPIO_PIN5 5 +#define ADM5120_GPIO_PIN6 6 +#define ADM5120_GPIO_PIN7 7 +#define ADM5120_GPIO_P0L0 8 +#define ADM5120_GPIO_P0L1 9 +#define ADM5120_GPIO_P0L2 10 +#define ADM5120_GPIO_P1L0 11 +#define ADM5120_GPIO_P1L1 12 +#define ADM5120_GPIO_P1L2 13 +#define ADM5120_GPIO_P2L0 14 +#define ADM5120_GPIO_P2L1 15 +#define ADM5120_GPIO_P2L2 16 +#define ADM5120_GPIO_P3L0 17 +#define ADM5120_GPIO_P3L1 18 +#define ADM5120_GPIO_P3L2 19 +#define ADM5120_GPIO_P4L0 20 +#define ADM5120_GPIO_P4L1 21 +#define ADM5120_GPIO_P4L2 22 +#define ADM5120_GPIO_MAX 22 +#define ADM5120_GPIO_COUNT ADM5120_GPIO_MAX+1 + +#define ADM5120_GPIO_LOW 0 +#define ADM5120_GPIO_HIGH 1 + +#define ADM5120_GPIO_SWITCH 0x10 +#define ADM5120_GPIO_FLASH (ADM5120_GPIO_SWITCH | LED_MODE_FLASH) +#define ADM5120_GPIO_LINK (ADM5120_GPIO_SWITCH | LED_MODE_LINK) +#define ADM5120_GPIO_SPEED (ADM5120_GPIO_SWITCH | LED_MODE_SPEED) +#define ADM5120_GPIO_DUPLEX (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX) +#define ADM5120_GPIO_ACT (ADM5120_GPIO_SWITCH | LED_MODE_ACT) +#define ADM5120_GPIO_COLL (ADM5120_GPIO_SWITCH | LED_MODE_COLL) +#define ADM5120_GPIO_LINK_ACT (ADM5120_GPIO_SWITCH | LED_MODE_LINK_ACT) +#define ADM5120_GPIO_DUPLEX_COLL (ADM5120_GPIO_SWITCH | LED_MODE_DUPLEX_COLL) +#define ADM5120_GPIO_10M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_10M_ACT) +#define ADM5120_GPIO_100M_ACT (ADM5120_GPIO_SWITCH | LED_MODE_100M_ACT) + +extern int __adm5120_gpio0_get_value(unsigned gpio); +extern void __adm5120_gpio0_set_value(unsigned gpio, int value); +extern int __adm5120_gpio1_get_value(unsigned gpio); +extern void __adm5120_gpio1_set_value(unsigned gpio, int value); +extern int adm5120_gpio_to_irq(unsigned gpio); +extern int adm5120_irq_to_gpio(unsigned irq); + +static inline int gpio_get_value(unsigned gpio) +{ + int ret; + + switch (gpio) { + case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7: + ret = __adm5120_gpio0_get_value(gpio); + break; + case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2: + ret = __adm5120_gpio1_get_value(gpio - ADM5120_GPIO_P0L0); + break; + default: + ret = __gpio_get_value(gpio); + break; + } + + return ret; +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + switch (gpio) { + case ADM5120_GPIO_PIN0 ... ADM5120_GPIO_PIN7: + __adm5120_gpio0_set_value(gpio, value); + break; + case ADM5120_GPIO_P0L0 ... ADM5120_GPIO_P4L2: + __adm5120_gpio1_set_value(gpio - ADM5120_GPIO_P0L0, value); + break; + default: + __gpio_set_value(gpio, value); + break; + } +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return adm5120_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(unsigned irq) +{ + return adm5120_irq_to_gpio(irq); +} + +#define gpio_cansleep __gpio_cansleep + +#endif /* _ASM_MIPS_MACH_ADM5120_GPIO_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/irq.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/irq.h new file mode 100644 index 0000000..b0350c8 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/irq.h @@ -0,0 +1,43 @@ +/* + * ADM5120 specific IRQ numbers + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef _ASM_MIPS_MACH_ADM5120_IRQ_H +#define _ASM_MIPS_MACH_ADM5120_IRQ_H + +#define MIPS_CPU_IRQ_BASE 0 +#define NR_IRQS 24 + +#include_next + +#include + +#define NO_IRQ (-1) + +#define MIPS_CPU_IRQ_COUNT 8 +#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) + +#define ADM5120_INTC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_IRQ_COUNT) +#define ADM5120_INTC_IRQ(x) (ADM5120_INTC_IRQ_BASE + (x)) + +#define ADM5120_IRQ_INTC MIPS_CPU_IRQ(2) +#define ADM5120_IRQ_COUNTER MIPS_CPU_IRQ(7) + +#define ADM5120_IRQ_TIMER ADM5120_INTC_IRQ(INTC_IRQ_TIMER) +#define ADM5120_IRQ_UART0 ADM5120_INTC_IRQ(INTC_IRQ_UART0) +#define ADM5120_IRQ_UART1 ADM5120_INTC_IRQ(INTC_IRQ_UART1) +#define ADM5120_IRQ_USBC ADM5120_INTC_IRQ(INTC_IRQ_USBC) +#define ADM5120_IRQ_GPIO2 ADM5120_INTC_IRQ(INTC_IRQ_GPIO2) +#define ADM5120_IRQ_GPIO4 ADM5120_INTC_IRQ(INTC_IRQ_GPIO4) +#define ADM5120_IRQ_PCI0 ADM5120_INTC_IRQ(INTC_IRQ_PCI0) +#define ADM5120_IRQ_PCI1 ADM5120_INTC_IRQ(INTC_IRQ_PCI1) +#define ADM5120_IRQ_PCI2 ADM5120_INTC_IRQ(INTC_IRQ_PCI2) +#define ADM5120_IRQ_SWITCH ADM5120_INTC_IRQ(INTC_IRQ_SWITCH) + +#endif /* _ASM_MIPS_MACH_ADM5120_IRQ_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/admboot.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/admboot.h new file mode 100644 index 0000000..fa42bf7 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/admboot.h @@ -0,0 +1,17 @@ +/* + * ADMBoot specific definitions + * + * Copyright (C) 2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ADMBOOT_H +#define _ADMBOOT_H + +extern int admboot_get_mac_base(u32 offset, u32 len, u8 *mac) __init; + +#endif /* _ADMBOOT_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/cfe.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/cfe.h new file mode 100644 index 0000000..0cb3eee --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/cfe.h @@ -0,0 +1,18 @@ +/* + * Broadcom's CFE definitions + * + * Copyright (C) 2006-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _PROM_CFE_H_ +#define _PROM_CFE_H_ + +extern int cfe_present(void) __init; +extern char *cfe_getenv(char *); + +#endif /*_PROM_CFE_H_*/ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/generic.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/generic.h new file mode 100644 index 0000000..778df24 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/generic.h @@ -0,0 +1,18 @@ +/* + * Generic prom definitions + * + * Copyright (C) 2006-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _PROM_GENERIC_H_ +#define _PROM_GENERIC_H_ + +extern int generic_prom_present(void) __init; +extern char *generic_prom_getenv(char *); + +#endif /*_PROM_GENERIC_H_*/ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/myloader.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/myloader.h new file mode 100644 index 0000000..ea8db81 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/myloader.h @@ -0,0 +1,179 @@ +/* + * Compex's MyLoader specific definitions + * + * Copyright (C) 2006-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MYLOADER_H_ +#define _MYLOADER_H_ + +/* + * Firmware file format: + * + *
+ * [] + * ... + * [] + * + * [] + * ... + * [] + * + * + */ + +/* Myloader specific magic numbers */ +#define MYLO_MAGIC_FIRMWARE 0x4C594D00 +#define MYLO_MAGIC_20021103 0x20021103 +#define MYLO_MAGIC_20021107 0x20021107 + +#define MYLO_MAGIC_SYS_PARAMS MYLO_MAGIC_20021107 +#define MYLO_MAGIC_PARTITIONS MYLO_MAGIC_20021103 +#define MYLO_MAGIC_BOARD_PARAMS MYLO_MAGIC_20021103 + +/* + * Addresses of the data structures provided by MyLoader + */ +#define MYLO_MIPS_SYS_PARAMS 0x80000800 /* System Parameters */ +#define MYLO_MIPS_BOARD_PARAMS 0x80000A00 /* Board Parameters */ +#define MYLO_MIPS_PARTITIONS 0x80000C00 /* Partition Table */ +#define MYLO_MIPS_BOOT_PARAMS 0x80000E00 /* Boot Parameters */ + +/* Vendor ID's (seems to be same as the PCI vendor ID's) */ +#define VENID_COMPEX 0x11F6 + +/* Devices based on the ADM5120 */ +#define DEVID_COMPEX_NP27G 0x0078 +#define DEVID_COMPEX_NP28G 0x044C +#define DEVID_COMPEX_NP28GHS 0x044E +#define DEVID_COMPEX_WP54Gv1C 0x0514 +#define DEVID_COMPEX_WP54G 0x0515 +#define DEVID_COMPEX_WP54AG 0x0546 +#define DEVID_COMPEX_WPP54AG 0x0550 +#define DEVID_COMPEX_WPP54G 0x0555 + +/* Devices based on the IXP422 */ +#define DEVID_COMPEX_WP18 0x047E +#define DEVID_COMPEX_NP18A 0x0489 + +/* Other devices */ +#define DEVID_COMPEX_NP26G8M 0x03E8 +#define DEVID_COMPEX_NP26G16M 0x03E9 + +struct mylo_fw_header { + uint32_t magic; /* must be MYLO_MAGIC_FIRMWARE */ + uint32_t crc; /* CRC of the whole firmware */ + uint32_t res0; /* unknown/unused */ + uint32_t res1; /* unknown/unused */ + uint16_t vid; /* vendor ID */ + uint16_t did; /* device ID */ + uint16_t svid; /* sub vendor ID */ + uint16_t sdid; /* sub device ID */ + uint32_t rev; /* device revision */ + uint32_t fwhi; /* FIXME: firmware version high? */ + uint32_t fwlo; /* FIXME: firmware version low? */ + uint32_t flags; /* firmware flags */ +}; + +#define FW_FLAG_BOARD_PARAMS_WP 0x01 /* board parameters are write protected */ +#define FW_FLAG_BOOT_SECTOR_WE 0x02 /* enable of write boot sectors (below 64K) */ + +struct mylo_fw_blockdesc { + uint32_t type; /* block type */ + uint32_t addr; /* relative address to flash start */ + uint32_t dlen; /* size of block data in bytes */ + uint32_t blen; /* total size of block in bytes */ +}; + +#define FW_DESC_TYPE_UNUSED 0 +#define FW_DESC_TYPE_USED 1 + +struct mylo_partition { + uint16_t flags; /* partition flags */ + uint16_t type; /* type of the partition */ + uint32_t addr; /* relative address of the partition from the + flash start */ + uint32_t size; /* size of the partition in bytes */ + uint32_t param; /* if this is the active partition, the + MyLoader load code to this address */ +}; + +#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition, + * MyLoader loads firmware from here */ +#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */ +#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */ +#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM + * before decompression */ +#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */ + +#define PARTITION_TYPE_FREE 0 +#define PARTITION_TYPE_USED 1 + +#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the + partition table */ + +struct mylo_partition_table { + uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */ + uint32_t res0; /* unknown/unused */ + uint32_t res1; /* unknown/unused */ + uint32_t res2; /* unknown/unused */ + struct mylo_partition partitions[MYLO_MAX_PARTITIONS]; +}; + +struct mylo_partition_header { + uint32_t len; /* length of the partition data */ + uint32_t crc; /* CRC value of the partition data */ +}; + +struct mylo_system_params { + uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */ + uint32_t res0; + uint32_t res1; + uint32_t mylo_ver; + uint16_t vid; /* Vendor ID */ + uint16_t did; /* Device ID */ + uint16_t svid; /* Sub Vendor ID */ + uint16_t sdid; /* Sub Device ID */ + uint32_t rev; /* device revision */ + uint32_t fwhi; + uint32_t fwlo; + uint32_t tftp_addr; + uint32_t prog_start; + uint32_t flash_size; /* Size of boot FLASH in bytes */ + uint32_t dram_size; /* Size of onboard RAM in bytes */ +}; + + +struct mylo_eth_addr { + uint8_t mac[6]; + uint8_t csum[2]; +}; + +#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address + in the board parameters */ + +struct mylo_board_params { + uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */ + uint32_t res0; + uint32_t res1; + uint32_t res2; + struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT]; +}; + +struct myloader_info { + u32 vid; + u32 did; + u32 svid; + u32 sdid; + uint8_t macs[MYLO_ETHADDR_COUNT][6]; +}; + +extern struct myloader_info myloader_info; +extern int myloader_present(void) __init; + +#endif /* _MYLOADER_H_*/ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/routerboot.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/routerboot.h new file mode 100644 index 0000000..91ac05a --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/routerboot.h @@ -0,0 +1,36 @@ +/* + * Mikrotik's RouterBOOT definitions + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _PROM_ROUTERBOOT_H_ +#define _PROM_ROUTERBOOT_H_ + +struct rb_bios_settings { + u32 hs_offs; /* hard settings offset */ + u32 hs_size; /* hard settings size */ + u32 fw_offs; /* firmware offset */ + u32 ss_offs; /* soft settings offset */ + u32 ss_size; /* soft settings size */ +}; + +struct rb_hard_settings { + char *name; /* board name */ + char *bios_ver; /* BIOS version */ + u32 mem_size; /* memory size in bytes */ + u32 mac_count; /* number of mac addresses */ + u8 *mac_base; /* mac address base */ +}; + +extern int routerboot_present(void) __init; +extern char *routerboot_get_boardname(void); + +extern struct rb_hard_settings rb_hs; + +#endif /* _PROM_ROUTERBOOT_H_ */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/zynos.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/zynos.h new file mode 100644 index 0000000..d1e3e5b --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/prom/zynos.h @@ -0,0 +1,86 @@ +/* + * ZyNOS (ZyXEL's Networking OS) definitions + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ZYNOS_H +#define _ZYNOS_H + +#define ZYNOS_NAME_LEN 32 +#define ZYNOS_FEAT_BYTES 22 +#define ZYNOS_MAC_LEN 6 + +struct zynos_board_info { + unsigned char vendor[ZYNOS_NAME_LEN]; + unsigned char product[ZYNOS_NAME_LEN]; + u32 bootext_addr; + u32 res0; + u16 board_id; + u8 res1[6]; + u8 feat_other[ZYNOS_FEAT_BYTES]; + u8 feat_main; + u8 res2; + u8 mac[ZYNOS_MAC_LEN]; + u8 country; + u8 dbgflag; +} __attribute__ ((packed)); + +/* + * Vendor IDs + */ +#define ZYNOS_VENDOR_ID_ZYXEL 0 +#define ZYNOS_VENDOR_ID_NETGEAR 1 +#define ZYNOS_VENDOR_ID_DLINK 2 +#define ZYNOS_VENDOR_ID_OTHER 3 +#define ZYNOS_VENDOR_ID_LUCENT 4 + +/* + * Vendor names + */ +#define ZYNOS_VENDOR_DLINK "D-Link" +#define ZYNOS_VENDOR_LUCENT "LUCENT" +#define ZYNOS_VENDOR_NETGEAR "NetGear" +#define ZYNOS_VENDOR_ZYXEL "ZyXEL" + +/* + * Board IDs (big-endian) + */ +#define ZYNOS_BOARD_ES2108 0x00F2 /* Ethernet Switch 2108 */ +#define ZYNOS_BOARD_ES2108F 0x01AF /* Ethernet Switch 2108-F */ +#define ZYNOS_BOARD_ES2108G 0x00F3 /* Ethernet Switch 2108-G */ +#define ZYNOS_BOARD_ES2108LC 0x00FC /* Ethernet Switch 2108-LC */ +#define ZYNOS_BOARD_ES2108PWR 0x00F4 /* Ethernet Switch 2108PWR */ +#define ZYNOS_BOARD_HS100 0x9FF1 /* HomeSafe 100/100W */ +#define ZYNOS_BOARD_P334 0x9FF5 /* Prestige 334 */ +#define ZYNOS_BOARD_P334U 0x9FDD /* Prestige 334U */ +#define ZYNOS_BOARD_P334W 0x9FF3 /* Prestige 334W */ +#define ZYNOS_BOARD_P334WH 0x00E0 /* Prestige 334WH */ +#define ZYNOS_BOARD_P334WHD 0x00E1 /* Prestige 334WHD */ +#define ZYNOS_BOARD_P334WT 0x9FEF /* Prestige 334WT */ +#define ZYNOS_BOARD_P334WT_ALT 0x9F02 /* Prestige 334WT alternative*/ +#define ZYNOS_BOARD_P335 0x9FED /* Prestige 335/335WT */ +#define ZYNOS_BOARD_P335PLUS 0x0025 /* Prestige 335Plus */ +#define ZYNOS_BOARD_P335U 0x9FDC /* Prestige 335U */ + +/* + * Some magic numbers (big-endian) + */ +#define ZYNOS_MAGIC_DBGAREA1 0x48646267 /* "Hdbg" */ +#define ZYNOS_MAGIC_DBGAREA2 0x61726561 /* "area" */ + +struct bootbase_info { + u16 vendor_id; + u16 board_id; + u8 mac[6]; +}; + +extern struct bootbase_info bootbase_info; +extern int bootbase_present(void) __init; + +#endif /* _ZYNOS_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/war.h b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/war.h new file mode 100644 index 0000000..87c35f3 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/include/asm/mach-adm5120/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_ADM5120_WAR_H +#define __ASM_MIPS_MACH_ADM5120_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_ADM5120_WAR_H */ diff --git a/target/linux/adm5120/files-3.18/arch/mips/pci/pci-adm5120.c b/target/linux/adm5120/files-3.18/arch/mips/pci/pci-adm5120.c new file mode 100644 index 0000000..f8d3598 --- /dev/null +++ b/target/linux/adm5120/files-3.18/arch/mips/pci/pci-adm5120.c @@ -0,0 +1,277 @@ +/* + * ADM5120 PCI Host Controller driver + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel + * done by Jeroen Vreeken + * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org) + * + * Jeroen's code was based on the Linux 2.4.xx source codes found in various + * tarballs released by Edimax for it's ADM5120 based devices + * Copyright (C) ADMtek Incorporated + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#undef DEBUG + +#ifdef DEBUG +#define DBG(f, a...) printk(KERN_DEBUG f, ## a) +#else +#define DBG(f, a...) do {} while (0) +#endif + +#define PCI_ENABLE 0x80000000 + +/* -------------------------------------------------------------------------*/ + +static unsigned int adm5120_pci_nr_irqs __initdata; +static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata; + +static DEFINE_SPINLOCK(pci_lock); + +/* -------------------------------------------------------------------------*/ + +static inline void write_cfgaddr(u32 addr) +{ + __raw_writel((addr | PCI_ENABLE), + (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR))); +} + +static inline void write_cfgdata(u32 data) +{ + __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA)); +} + +static inline u32 read_cfgdata(void) +{ + return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA)); +} + +static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where) +{ + return ((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \ + (where & 0xFC); +} + +/* -------------------------------------------------------------------------*/ + +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *val) +{ + unsigned long flags; + u32 data; + + spin_lock_irqsave(&pci_lock, flags); + + write_cfgaddr(mkaddr(bus, devfn, where)); + data = read_cfgdata(); + + DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X", + bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), + where, size, data); + + switch (size) { + case 1: + if (where & 1) + data >>= 8; + if (where & 2) + data >>= 16; + data &= 0xFF; + break; + case 2: + if (where & 2) + data >>= 16; + data &= 0xFFFF; + break; + } + + *val = data; + DBG(", 0x%08X returned\n", data); + + spin_unlock_irqrestore(&pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + unsigned long flags; + u32 data; + int s; + + spin_lock_irqsave(&pci_lock, flags); + + write_cfgaddr(mkaddr(bus, devfn, where)); + data = read_cfgdata(); + + DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X", + bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), + where, size, data); + + switch (size) { + case 1: + s = ((where & 3) << 3); + data &= ~(0xFF << s); + data |= ((val & 0xFF) << s); + break; + case 2: + s = ((where & 2) << 4); + data &= ~(0xFFFF << s); + data |= ((val & 0xFFFF) << s); + break; + case 4: + data = val; + break; + } + + write_cfgdata(data); + DBG(", 0x%08X written\n", data); + + spin_unlock_irqrestore(&pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops adm5120_pci_ops = { + .read = pci_config_read, + .write = pci_config_write, +}; + +/* -------------------------------------------------------------------------*/ + +static void adm5120_pci_fixup(struct pci_dev *dev) +{ + if (dev->devfn != 0) + return; + + /* setup COMMAND register */ + pci_write_config_word(dev, PCI_COMMAND, + (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* setup CACHE_LINE_SIZE register */ + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4); + + /* setup BARS */ + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); +} + +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120, + adm5120_pci_fixup); + +/* -------------------------------------------------------------------------*/ + +void __init adm5120_pci_set_irq_map(unsigned int nr_irqs, + struct adm5120_pci_irq *map) +{ + adm5120_pci_nr_irqs = nr_irqs; + adm5120_pci_irq_map = map; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq = -1; + int i; + + if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) { + printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n"); + goto out; + } + + if (slot < 1 || slot > 4) { + printk(KERN_ALERT "PCI: slot number %u is not supported\n", + slot); + goto out; + } + + for (i = 0; i < adm5120_pci_nr_irqs; i++) { + if ((adm5120_pci_irq_map[i].slot == slot) + && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn)) + && (adm5120_pci_irq_map[i].pin == pin)) { + irq = adm5120_pci_irq_map[i].irq; + break; + } + } + + if (irq < 0) { + printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n", + pci_name((struct pci_dev *)dev), pin); + } else { + printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n", + pci_name((struct pci_dev *)dev), pin, irq); + } + +out: + return irq; +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +/* -------------------------------------------------------------------------*/ + +static struct resource pci_io_resource = { + .name = "ADM5120 PCI I/O", + .start = ADM5120_PCIIO_BASE, + .end = ADM5120_PCICFG_ADDR-1, + .flags = IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + .name = "ADM5120 PCI MEM", + .start = ADM5120_PCIMEM_BASE, + .end = ADM5120_PCIIO_BASE-1, + .flags = IORESOURCE_MEM +}; + +static struct pci_controller adm5120_controller = { + .pci_ops = &adm5120_pci_ops, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, +}; + +static int __init adm5120_pci_setup(void) +{ + if (adm5120_package_pqfp()) { + printk(KERN_INFO "PCI: not available on ADM5120P\n"); + return -1; + } + + /* Avoid ISA compat ranges. */ + PCIBIOS_MIN_IO = 0x00000000; + PCIBIOS_MIN_MEM = 0x00000000; + + /* Set I/O resource limits. */ + ioport_resource.end = 0x1fffffff; + iomem_resource.end = 0xffffffff; + + register_pci_controller(&adm5120_controller); + return 0; +} + +arch_initcall(adm5120_pci_setup); diff --git a/target/linux/adm5120/files-3.18/drivers/ata/pata_rb153_cf.c b/target/linux/adm5120/files-3.18/drivers/ata/pata_rb153_cf.c new file mode 100644 index 0000000..92a4d13 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/ata/pata_rb153_cf.c @@ -0,0 +1,267 @@ +/* + * A low-level PATA driver to handle a Compact Flash connected on the + * Mikrotik's RouterBoard 153 board. + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was based on: drivers/ata/pata_ixp4xx_cf.c + * Copyright (C) 2006-07 Tower Technologies + * Author: Alessandro Zummo + * + * Also was based on the driver for Linux 2.4.xx published by Mikrotik for + * their RouterBoard 1xx and 5xx series devices. The original Mikrotik code + * seems not to have a license. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_NAME "pata-rb153-cf" +#define DRV_VERSION "0.5.0" +#define DRV_DESC "PATA driver for RouterBOARD 153 Compact Flash" + +#define RB153_CF_MAXPORTS 1 +#define RB153_CF_IO_DELAY 100 + +#define RB153_CF_REG_CMD 0x0800 +#define RB153_CF_REG_CTRL 0x080E +#define RB153_CF_REG_DATA 0x0C00 + +struct rb153_cf_info { + void __iomem *iobase; + unsigned int gpio_line; + int frozen; + unsigned int irq; +}; + +static inline void rb153_pata_finish_io(struct ata_port *ap) +{ + struct rb153_cf_info *info = ap->host->private_data; + + /* FIXME: Keep previous delay. If this is merely a fence then + * ata_sff_sync might be sufficient. */ + ata_sff_dma_pause(ap); + ndelay(RB153_CF_IO_DELAY); + + irq_set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH); +} + +static void rb153_pata_exec_command(struct ata_port *ap, + const struct ata_taskfile *tf) +{ + writeb(tf->command, ap->ioaddr.command_addr); + rb153_pata_finish_io(ap); +} + +static unsigned int rb153_pata_data_xfer(struct ata_device *adev, + unsigned char *buf, + unsigned int buflen, + int write_data) +{ + void __iomem *ioaddr = adev->link->ap->ioaddr.data_addr; + unsigned int t; + + t = buflen; + if (write_data) { + for (; t > 0; t--, buf++) + writeb(*buf, ioaddr); + } else { + for (; t > 0; t--, buf++) + *buf = readb(ioaddr); + } + + rb153_pata_finish_io(adev->link->ap); + return buflen; +} + +static void rb153_pata_freeze(struct ata_port *ap) +{ + struct rb153_cf_info *info = ap->host->private_data; + + info->frozen = 1; +} + +static void rb153_pata_thaw(struct ata_port *ap) +{ + struct rb153_cf_info *info = ap->host->private_data; + + info->frozen = 0; +} + +static irqreturn_t rb153_pata_irq_handler(int irq, void *dev_instance) +{ + struct ata_host *ah = dev_instance; + struct rb153_cf_info *info = ah->private_data; + + if (gpio_get_value(info->gpio_line)) { + irq_set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW); + if (!info->frozen) + ata_sff_interrupt(irq, dev_instance); + } else { + irq_set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH); + } + + return IRQ_HANDLED; +} + +static struct ata_port_operations rb153_pata_port_ops = { + .inherits = &ata_sff_port_ops, + .sff_exec_command = rb153_pata_exec_command, + .sff_data_xfer = rb153_pata_data_xfer, + .freeze = rb153_pata_freeze, + .thaw = rb153_pata_thaw, +}; + +static struct scsi_host_template rb153_pata_sht = { + ATA_PIO_SHT(DRV_NAME), +}; + +static void rb153_pata_setup_port(struct ata_host *ah) +{ + struct rb153_cf_info *info = ah->private_data; + struct ata_port *ap; + + ap = ah->ports[0]; + + ap->ops = &rb153_pata_port_ops; + ap->pio_mask = 0x1f; /* PIO4 */ + + ap->ioaddr.cmd_addr = info->iobase + RB153_CF_REG_CMD; + ap->ioaddr.ctl_addr = info->iobase + RB153_CF_REG_CTRL; + ap->ioaddr.altstatus_addr = info->iobase + RB153_CF_REG_CTRL; + + ata_sff_std_ports(&ap->ioaddr); + + ap->ioaddr.data_addr = info->iobase + RB153_CF_REG_DATA; +} + +static int rb153_pata_driver_probe(struct platform_device *pdev) +{ + unsigned int irq; + int gpio; + struct resource *res; + struct ata_host *ah; + struct rb153_cf_info *info; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no IOMEM resource found\n"); + return -EINVAL; + } + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) { + dev_err(&pdev->dev, "no IRQ resource found\n"); + return -ENOENT; + } + + gpio = irq_to_gpio(irq); + if (gpio < 0) { + dev_err(&pdev->dev, "no GPIO found for irq%d\n", irq); + return -ENOENT; + } + + ret = gpio_request(gpio, DRV_NAME); + if (ret) { + dev_err(&pdev->dev, "GPIO request failed\n"); + return ret; + } + + ah = ata_host_alloc(&pdev->dev, RB153_CF_MAXPORTS); + if (!ah) + return -ENOMEM; + + platform_set_drvdata(pdev, ah); + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + ah->private_data = info; + info->gpio_line = gpio; + info->irq = irq; + + info->iobase = devm_ioremap_nocache(&pdev->dev, res->start, + res->end - res->start + 1); + if (!info->iobase) + return -ENOMEM; + + ret = gpio_direction_input(gpio); + if (ret) { + dev_err(&pdev->dev, "unable to set GPIO direction, err=%d\n", + ret); + goto err_free_gpio; + } + + rb153_pata_setup_port(ah); + + ret = ata_host_activate(ah, irq, rb153_pata_irq_handler, + IRQF_TRIGGER_LOW, &rb153_pata_sht); + if (ret) + goto err_free_gpio; + + return 0; + +err_free_gpio: + gpio_free(gpio); + + return ret; +} + +static int rb153_pata_driver_remove(struct platform_device *pdev) +{ + struct ata_host *ah = platform_get_drvdata(pdev); + struct rb153_cf_info *info = ah->private_data; + + ata_host_detach(ah); + gpio_free(info->gpio_line); + + return 0; +} + +static struct platform_driver rb153_pata_platform_driver = { + .probe = rb153_pata_driver_probe, + .remove = rb153_pata_driver_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +/* ------------------------------------------------------------------------ */ + +#define DRV_INFO DRV_DESC " version " DRV_VERSION + +static int __init rb153_pata_module_init(void) +{ + printk(KERN_INFO DRV_INFO "\n"); + + return platform_driver_register(&rb153_pata_platform_driver); +} + +static void __exit rb153_pata_module_exit(void) +{ + platform_driver_unregister(&rb153_pata_platform_driver); +} + +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_LICENSE("GPL v2"); + +module_init(rb153_pata_module_init); +module_exit(rb153_pata_module_exit); diff --git a/target/linux/adm5120/files-3.18/drivers/leds/ledtrig-adm5120-switch.c b/target/linux/adm5120/files-3.18/drivers/leds/ledtrig-adm5120-switch.c new file mode 100644 index 0000000..23a54a0 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/leds/ledtrig-adm5120-switch.c @@ -0,0 +1,149 @@ +/* + * LED ADM5120 Switch Port State Trigger + * + * Copyright (C) 2007 Bernhard Held + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was based on: drivers/leds/ledtrig-timer.c + * Copyright 2005-2006 Openedhand Ltd. + * Author: Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include + +#include "leds.h" + +#define DRV_NAME "port_state" +#define DRV_DESC "LED ADM5120 Switch Port State Trigger" + +struct port_state { + char *name; + unsigned int value; +}; + +#define PORT_STATE(n, v) {.name = (n), .value = (v)} + +static struct port_state port_states[] = { + PORT_STATE("off", LED_OFF), + PORT_STATE("on", LED_FULL), + PORT_STATE("flash", ADM5120_GPIO_FLASH), + PORT_STATE("link", ADM5120_GPIO_LINK), + PORT_STATE("speed", ADM5120_GPIO_SPEED), + PORT_STATE("duplex", ADM5120_GPIO_DUPLEX), + PORT_STATE("act", ADM5120_GPIO_ACT), + PORT_STATE("coll", ADM5120_GPIO_COLL), + PORT_STATE("link_act", ADM5120_GPIO_LINK_ACT), + PORT_STATE("duplex_coll", ADM5120_GPIO_DUPLEX_COLL), + PORT_STATE("10M_act", ADM5120_GPIO_10M_ACT), + PORT_STATE("100M_act", ADM5120_GPIO_100M_ACT), +}; + +static ssize_t led_port_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct port_state *state = led_cdev->trigger_data; + int len = 0; + int i; + + *buf = '\0'; + for (i = 0; i < ARRAY_SIZE(port_states); i++) { + if (&port_states[i] == state) + len += sprintf(buf+len, "[%s] ", port_states[i].name); + else + len += sprintf(buf+len, "%s ", port_states[i].name); + } + len += sprintf(buf+len, "\n"); + + return len; +} + +static ssize_t led_port_state_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + size_t len; + int i; + + for (i = 0; i < ARRAY_SIZE(port_states); i++) { + len = strlen(port_states[i].name); + if (strncmp(port_states[i].name, buf, len) != 0) + continue; + + if (buf[len] != '\0' && buf[len] != '\n') + continue; + + led_cdev->trigger_data = &port_states[i]; + led_set_brightness(led_cdev, port_states[i].value); + return size; + } + + return -EINVAL; +} + +static DEVICE_ATTR(port_state, 0644, led_port_state_show, + led_port_state_store); + +static void adm5120_switch_trig_activate(struct led_classdev *led_cdev) +{ + struct port_state *state = port_states; + int rc; + + led_cdev->trigger_data = state; + + rc = device_create_file(led_cdev->dev, &dev_attr_port_state); + if (rc) + goto err; + + led_set_brightness(led_cdev, state->value); + + return; +err: + led_cdev->trigger_data = NULL; +} + +static void adm5120_switch_trig_deactivate(struct led_classdev *led_cdev) +{ + struct port_state *state = led_cdev->trigger_data; + + if (!state) + return; + + device_remove_file(led_cdev->dev, &dev_attr_port_state); + +} + +static struct led_trigger adm5120_switch_led_trigger = { + .name = DRV_NAME, + .activate = adm5120_switch_trig_activate, + .deactivate = adm5120_switch_trig_deactivate, +}; + +static int __init adm5120_switch_trig_init(void) +{ + led_trigger_register(&adm5120_switch_led_trigger); + return 0; +} + +static void __exit adm5120_switch_trig_exit(void) +{ + led_trigger_unregister(&adm5120_switch_led_trigger); +} + +module_init(adm5120_switch_trig_init); +module_exit(adm5120_switch_trig_exit); + +MODULE_AUTHOR("Bernhard Held , " + "Gabor Juhos "); +MODULE_DESCRIPTION(DRV_DESC); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/adm5120/files-3.18/drivers/mtd/maps/adm5120-flash.c b/target/linux/adm5120/files-3.18/drivers/mtd/maps/adm5120-flash.c new file mode 100644 index 0000000..f6a86f4 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/mtd/maps/adm5120-flash.c @@ -0,0 +1,482 @@ +/* + * Platform driver for NOR flash devices on ADM5120 based boards + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: drivers/mtd/map/physmap.c + * Copyright (C) 2003 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#define DRV_NAME "adm5120-flash" +#define DRV_DESC "ADM5120 flash MAP driver" +#define MAX_PARSED_PARTS 8 + +#ifdef ADM5120_FLASH_DEBUG +#define MAP_DBG(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a) +#else +#define MAP_DBG(m, f, a...) do {} while (0) +#endif +#define MAP_ERR(m, f, a...) printk(KERN_ERR "%s: " f, (m->name) , ## a) +#define MAP_INFO(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a) + +struct adm5120_map_info { + struct map_info map; + void (*switch_bank)(unsigned); + unsigned long window_size; +}; + +struct adm5120_flash_info { + struct mtd_info *mtd; + struct resource *res; + struct platform_device *dev; + struct adm5120_map_info amap; +}; + +struct flash_desc { + u32 phys; + u32 srs_shift; +}; + +/* + * Globals + */ +static DEFINE_SPINLOCK(adm5120_flash_spin); +#define FLASH_LOCK() spin_lock(&adm5120_flash_spin) +#define FLASH_UNLOCK() spin_unlock(&adm5120_flash_spin) + +static u32 flash_bankwidths[4] = { 1, 2, 4, 0 }; + +static u32 flash_sizes[8] = { + 0, 512*1024, 1024*1024, 2*1024*1024, + 4*1024*1024, 0, 0, 0 +}; + +static struct flash_desc flash_descs[2] = { + { + .phys = ADM5120_SRAM0_BASE, + .srs_shift = MEMCTRL_SRS0_SHIFT, + }, { + .phys = ADM5120_SRAM1_BASE, + .srs_shift = MEMCTRL_SRS1_SHIFT, + } +}; + +static const char const *probe_types[] = { + "cfi_probe", + "jedec_probe", + "map_rom", + NULL +}; + +static const char const *parse_types[] = { + "cmdlinepart", +#ifdef CONFIG_MTD_REDBOOT_PARTS + "RedBoot", +#endif +#ifdef CONFIG_MTD_MYLOADER_PARTS + "MyLoader", +#endif + NULL, +}; + +#define BANK_SIZE (2<<20) +#define BANK_SIZE_MAX (4<<20) +#define BANK_OFFS_MASK (BANK_SIZE-1) +#define BANK_START_MASK (~BANK_OFFS_MASK) + +static inline struct adm5120_map_info *map_to_amap(struct map_info *map) +{ + return (struct adm5120_map_info *)map; +} + +static void adm5120_flash_switchbank(struct map_info *map, + unsigned long ofs) +{ + struct adm5120_map_info *amap = map_to_amap(map); + unsigned bank; + + if (amap->switch_bank == NULL) + return; + + bank = (ofs & BANK_START_MASK) >> 21; + if (bank > 1) + BUG(); + + MAP_DBG(map, "switching to bank %u, ofs=%lX\n", bank, ofs); + amap->switch_bank(bank); +} + +static map_word adm5120_flash_read(struct map_info *map, unsigned long ofs) +{ + struct adm5120_map_info *amap = map_to_amap(map); + map_word ret; + + MAP_DBG(map, "reading from ofs %lX\n", ofs); + + if (ofs >= amap->window_size) + return map_word_ff(map); + + FLASH_LOCK(); + adm5120_flash_switchbank(map, ofs); + ret = inline_map_read(map, (ofs & (amap->window_size-1))); + FLASH_UNLOCK(); + + return ret; +} + +static void adm5120_flash_write(struct map_info *map, const map_word datum, + unsigned long ofs) +{ + struct adm5120_map_info *amap = map_to_amap(map); + + MAP_DBG(map, "writing to ofs %lX\n", ofs); + + if (ofs > amap->window_size) + return; + + FLASH_LOCK(); + adm5120_flash_switchbank(map, ofs); + inline_map_write(map, datum, (ofs & (amap->window_size-1))); + FLASH_UNLOCK(); +} + +static void adm5120_flash_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + struct adm5120_map_info *amap = map_to_amap(map); + char *p; + ssize_t t; + + MAP_DBG(map, "copy_from, to=%lX, from=%lX, len=%lX\n", + (unsigned long)to, from, (unsigned long)len); + + if (from > amap->window_size) + return; + + p = (char *)to; + while (len > 0) { + t = len; + if ((from < BANK_SIZE) && ((from+len) > BANK_SIZE)) + t = BANK_SIZE-from; + + FLASH_LOCK(); + MAP_DBG(map, "copying %lu byte(s) from %lX to %lX\n", + (unsigned long)t, (from & (amap->window_size-1)), + (unsigned long)p); + adm5120_flash_switchbank(map, from); + inline_map_copy_from(map, p, (from & (amap->window_size-1)), t); + FLASH_UNLOCK(); + p += t; + from += t; + len -= t; + } +} + +static int adm5120_flash_initres(struct adm5120_flash_info *info) +{ + struct map_info *map = &info->amap.map; + int err = 0; + + info->res = request_mem_region(map->phys, info->amap.window_size, + map->name); + if (info->res == NULL) { + MAP_ERR(map, "could not reserve memory region\n"); + err = -ENOMEM; + goto out; + } + + map->virt = ioremap_nocache(map->phys, info->amap.window_size); + if (map->virt == NULL) { + MAP_ERR(map, "failed to ioremap flash region\n"); + err = -ENOMEM; + goto out; + } + +out: + return err; +} + +static int adm5120_flash_initinfo(struct adm5120_flash_info *info, + struct platform_device *dev) +{ + struct map_info *map = &info->amap.map; + struct adm5120_flash_platform_data *pdata = dev->dev.platform_data; + struct flash_desc *fdesc; + u32 t = 0; + + map->name = dev_name(&dev->dev); + + if (dev->id > 1) { + MAP_ERR(map, "invalid flash id\n"); + goto err_out; + } + + fdesc = &flash_descs[dev->id]; + + if (pdata) + info->amap.window_size = pdata->window_size; + + if (info->amap.window_size == 0) { + /* get memory window size */ + t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift; + t &= MEMCTRL_SRS_MASK; + info->amap.window_size = flash_sizes[t]; + } + + if (info->amap.window_size == 0) { + MAP_ERR(map, "unable to determine window size\n"); + goto err_out; + } + + /* get flash bus width */ + switch (dev->id) { + case 0: + t = MPMC_READ_REG(SC1) & SC_MW_MASK; + break; + case 1: + t = MPMC_READ_REG(SC0) & SC_MW_MASK; + break; + } + map->bankwidth = flash_bankwidths[t]; + if (map->bankwidth == 0) { + MAP_ERR(map, "invalid bus width detected\n"); + goto err_out; + } + + map->phys = fdesc->phys; + map->size = BANK_SIZE_MAX; + + simple_map_init(map); + map->read = adm5120_flash_read; + map->write = adm5120_flash_write; + map->copy_from = adm5120_flash_copy_from; + + if (pdata) { + map->set_vpp = pdata->set_vpp; + info->amap.switch_bank = pdata->switch_bank; + } + + info->dev = dev; + + MAP_INFO(map, "probing at 0x%lX, size:%ldKiB, width:%d bits\n", + (unsigned long)map->phys, + (unsigned long)info->amap.window_size >> 10, + map->bankwidth*8); + + return 0; + +err_out: + return -ENODEV; +} + +static void adm5120_flash_initbanks(struct adm5120_flash_info *info) +{ + struct map_info *map = &info->amap.map; + + if (info->mtd->size <= BANK_SIZE) + /* no bank switching needed */ + return; + + if (info->amap.switch_bank) { + info->amap.window_size = info->mtd->size; + return; + } + + MAP_ERR(map, "reduce visibility from %ldKiB to %ldKiB\n", + (unsigned long)map->size >> 10, + (unsigned long)info->mtd->size >> 10); + + info->mtd->size = info->amap.window_size; +} + +static int adm5120_flash_remove(struct platform_device *dev) +{ + struct adm5120_flash_info *info; + + info = platform_get_drvdata(dev); + if (info == NULL) + return 0; + + platform_set_drvdata(dev, NULL); + + if (info->mtd != NULL) { + mtd_device_unregister(info->mtd); + map_destroy(info->mtd); + } + + if (info->amap.map.virt != NULL) + iounmap(info->amap.map.virt); + + if (info->res != NULL) { + release_resource(info->res); + kfree(info->res); + } + + return 0; +} + +static int adm5120_flash_probe(struct platform_device *dev) +{ + struct adm5120_flash_platform_data *pdata; + struct adm5120_flash_info *info; + struct map_info *map; + const char **probe_type; + int err; + + pdata = dev->dev.platform_data; + if (!pdata) { + dev_err(&dev->dev, "no platform data\n"); + return -EINVAL; + } + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (info == NULL) { + err = -ENOMEM; + goto err_out; + } + + platform_set_drvdata(dev, info); + + err = adm5120_flash_initinfo(info, dev); + if (err) + goto err_out; + + err = adm5120_flash_initres(info); + if (err) + goto err_out; + + map = &info->amap.map; + for (probe_type = probe_types; info->mtd == NULL && *probe_type != NULL; + probe_type++) + info->mtd = do_map_probe(*probe_type, map); + + if (info->mtd == NULL) { + MAP_ERR(map, "map_probe failed\n"); + err = -ENXIO; + goto err_out; + } + + adm5120_flash_initbanks(info); + + if (info->mtd->size < info->amap.window_size) { + /* readjust resources */ + iounmap(map->virt); + release_resource(info->res); + kfree(info->res); + + info->amap.window_size = info->mtd->size; + map->size = info->mtd->size; + MAP_INFO(map, "reducing map size to %ldKiB\n", + (unsigned long)map->size >> 10); + err = adm5120_flash_initres(info); + if (err) + goto err_out; + } + + MAP_INFO(map, "found at 0x%lX, size:%ldKiB, width:%d bits\n", + (unsigned long)map->phys, (unsigned long)info->mtd->size >> 10, + map->bankwidth*8); + + info->mtd->owner = THIS_MODULE; + + err = mtd_device_parse_register(info->mtd, parse_types, 0, + pdata->parts, pdata->nr_parts); + if (err) + goto err_out; + + return 0; + +err_out: + adm5120_flash_remove(dev); + return err; +} + +#ifdef CONFIG_PM +static int adm5120_flash_suspend(struct platform_device *dev, + pm_message_t state) +{ + struct adm5120_flash_info *info = platform_get_drvdata(dev); + int ret = 0; + + if (info) + ret = info->mtd->suspend(info->mtd); + + return ret; +} + +static int adm5120_flash_resume(struct platform_device *dev) +{ + struct adm5120_flash_info *info = platform_get_drvdata(dev); + + if (info) + info->mtd->resume(info->mtd); + + return 0; +} + +static void adm5120_flash_shutdown(struct platform_device *dev) +{ + struct adm5120_flash_info *info = platform_get_drvdata(dev); + + if (info && info->mtd->suspend(info->mtd) == 0) + info->mtd->resume(info->mtd); +} +#endif + +static struct platform_driver adm5120_flash_driver = { + .probe = adm5120_flash_probe, + .remove = adm5120_flash_remove, +#ifdef CONFIG_PM + .suspend = adm5120_flash_suspend, + .resume = adm5120_flash_resume, + .shutdown = adm5120_flash_shutdown, +#endif + .driver = { + .name = DRV_NAME, + }, +}; + +static int __init adm5120_flash_init(void) +{ + int err; + + err = platform_driver_register(&adm5120_flash_driver); + + return err; +} + +static void __exit adm5120_flash_exit(void) +{ + platform_driver_unregister(&adm5120_flash_driver); +} + +module_init(adm5120_flash_init); +module_exit(adm5120_flash_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION(DRV_DESC); diff --git a/target/linux/adm5120/files-3.18/drivers/mtd/trxsplit.c b/target/linux/adm5120/files-3.18/drivers/mtd/trxsplit.c new file mode 100644 index 0000000..76cbdc7 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/mtd/trxsplit.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define PFX "trxsplit: " + +#define TRX_MAGIC 0x30524448 /* "HDR0" */ +#define TRX_VERSION 1 +#define TRX_MAX_LEN 0x3A0000 +#define TRX_NO_HEADER 0x1 /* do not write TRX header */ +#define TRX_GZ_FILES 0x2 /* contains individual gzip files */ +#define TRX_MAX_OFFSET 3 +#define TRX_MIN_KERNEL_SIZE (256 * 1024) + +struct trx_header { + u32 magic; /* "HDR0" */ + u32 len; /* Length of file including header */ + u32 crc32; /* 32-bit CRC from flag_version to end of file */ + u32 flag_version; /* 0:15 flags, 16:31 version */ + u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions */ +}; + +#define TRX_ALIGN 0x1000 + +static int trx_nr_parts; +static unsigned long trx_offset; +static struct mtd_info *trx_mtd; +static struct mtd_partition trx_parts[TRX_MAX_OFFSET]; +static struct trx_header trx_hdr; + +static int trxsplit_refresh_partitions(struct mtd_info *mtd); + +static int trxsplit_checktrx(struct mtd_info *mtd, unsigned long offset) +{ + size_t retlen; + int err; + + err = mtd_read(mtd, offset, sizeof(trx_hdr), &retlen, (void *)&trx_hdr); + if (err) { + printk(KERN_ALERT PFX "unable to read from '%s'\n", mtd->name); + goto err_out; + } + + if (retlen != sizeof(trx_hdr)) { + printk(KERN_ALERT PFX "reading failed on '%s'\n", mtd->name); + goto err_out; + } + + trx_hdr.magic = le32_to_cpu(trx_hdr.magic); + trx_hdr.len = le32_to_cpu(trx_hdr.len); + trx_hdr.crc32 = le32_to_cpu(trx_hdr.crc32); + trx_hdr.flag_version = le32_to_cpu(trx_hdr.flag_version); + trx_hdr.offsets[0] = le32_to_cpu(trx_hdr.offsets[0]); + trx_hdr.offsets[1] = le32_to_cpu(trx_hdr.offsets[1]); + trx_hdr.offsets[2] = le32_to_cpu(trx_hdr.offsets[2]); + + /* sanity checks */ + if (trx_hdr.magic != TRX_MAGIC) + goto err_out; + + if (trx_hdr.len > mtd->size - offset) + goto err_out; + + /* TODO: add crc32 checking too? */ + + return 0; + +err_out: + return -1; +} + +static void trxsplit_findtrx(struct mtd_info *mtd) +{ + unsigned long offset; + int err; + + printk(KERN_INFO PFX "searching TRX header in '%s'\n", mtd->name); + + err = 0; + for (offset = 0; offset < mtd->size; offset += TRX_ALIGN) { + err = trxsplit_checktrx(mtd, offset); + if (err == 0) + break; + } + + if (err) + return; + + printk(KERN_INFO PFX "TRX header found at 0x%lX\n", offset); + + trx_mtd = mtd; + trx_offset = offset; +} + +static void trxsplit_create_partitions(struct mtd_info *mtd) +{ + struct mtd_partition *part = trx_parts; + int err; + int i; + + for (i = 0; i < TRX_MAX_OFFSET; i++) { + part = &trx_parts[i]; + if (trx_hdr.offsets[i] == 0) + continue; + part->offset = trx_offset + trx_hdr.offsets[i]; + trx_nr_parts++; + } + + for (i = 0; i < trx_nr_parts-1; i++) + trx_parts[i].size = trx_parts[i+1].offset - trx_parts[i].offset; + + trx_parts[i].size = mtd->size - trx_parts[i].offset; + + i = 0; + part = &trx_parts[i]; + if (part->size < TRX_MIN_KERNEL_SIZE) { + part->name = "loader"; + i++; + } + + part = &trx_parts[i]; + part->name = "kernel"; + i++; + + part = &trx_parts[i]; + part->name = "rootfs"; + + err = mtd_device_register(mtd, trx_parts, trx_nr_parts); + if (err) { + printk(KERN_ALERT PFX "adding TRX partitions failed\n"); + return; + } + + mtd->refresh_device = trxsplit_refresh_partitions; +} + +static int trxsplit_refresh_partitions(struct mtd_info *mtd) +{ + printk(KERN_INFO PFX "refreshing TRX partitions in '%s' (%d,%d)\n", + mtd->name, MTD_BLOCK_MAJOR, mtd->index); + + /* remove old partitions */ + mtd_device_unregister(mtd); + + trxsplit_findtrx(mtd); + if (!trx_mtd) + goto err; + + trxsplit_create_partitions(trx_mtd); + return 1; + +err: + return 0; +} + +static void __init trxsplit_add_mtd(struct mtd_info *mtd) +{ + if (mtd->type != MTD_NORFLASH) { + printk(KERN_INFO PFX "'%s' is not a NOR flash, skipped\n", + mtd->name); + return; + } + + if (!trx_mtd) + trxsplit_findtrx(mtd); +} + +static void __init trxsplit_remove_mtd(struct mtd_info *mtd) +{ + /* nothing to do */ +} + +static struct mtd_notifier trxsplit_notifier __initdata = { + .add = trxsplit_add_mtd, + .remove = trxsplit_remove_mtd, +}; + +static void __init trxsplit_scan(void) +{ + register_mtd_user(&trxsplit_notifier); + unregister_mtd_user(&trxsplit_notifier); +} + +static int __init trxsplit_init(void) +{ + trxsplit_scan(); + + if (trx_mtd) { + printk(KERN_INFO PFX "creating TRX partitions in '%s' " + "(%d,%d)\n", trx_mtd->name, MTD_BLOCK_MAJOR, + trx_mtd->index); + trxsplit_create_partitions(trx_mtd); + } + + return 0; +} + +late_initcall(trxsplit_init); diff --git a/target/linux/adm5120/files-3.18/drivers/net/adm5120sw.c b/target/linux/adm5120/files-3.18/drivers/net/adm5120sw.c new file mode 100644 index 0000000..7fbabb0 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/net/adm5120sw.c @@ -0,0 +1,1219 @@ +/* + * ADM5120 built-in ethernet switch driver + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This code was based on a driver for Linux 2.6.xx by Jeroen Vreeken. + * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005 + * NAPI extension for the Jeroen's driver + * Copyright Thomas Langer (Thomas.Langer@infineon.com), 2007 + * Copyright Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007 + * Inspiration for the Jeroen's driver came from the ADMtek 2.4 driver. + * Copyright ADMtek Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include "adm5120sw.h" +#include + +#define DRV_NAME "adm5120-switch" +#define DRV_DESC "ADM5120 built-in ethernet switch driver" +#define DRV_VERSION "0.1.1" + +#define CONFIG_ADM5120_SWITCH_NAPI 1 +#undef CONFIG_ADM5120_SWITCH_DEBUG + +/* ------------------------------------------------------------------------ */ + +#ifdef CONFIG_ADM5120_SWITCH_DEBUG +#define SW_DBG(f, a...) printk(KERN_DEBUG "%s: " f, DRV_NAME , ## a) +#else +#define SW_DBG(f, a...) do {} while (0) +#endif +#define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a) +#define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a) + +#define SWITCH_NUM_PORTS 6 +#define ETH_CSUM_LEN 4 + +#define RX_MAX_PKTLEN 1550 +#define RX_RING_SIZE 64 + +#define TX_RING_SIZE 32 +#define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */ +#define TX_TIMEOUT (HZ * 400) + +#define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *)) +#define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *)) +#define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *)) +#define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *)) + +#define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32) +#define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD) + +#define SWITCH_INTS_HIGH (SWITCH_INT_SHD | SWITCH_INT_RHD | SWITCH_INT_HDF) +#define SWITCH_INTS_LOW (SWITCH_INT_SLD | SWITCH_INT_RLD | SWITCH_INT_LDF) +#define SWITCH_INTS_ERR (SWITCH_INT_RDE | SWITCH_INT_SDE | SWITCH_INT_CPUH) +#define SWITCH_INTS_Q (SWITCH_INT_P0QF | SWITCH_INT_P1QF | SWITCH_INT_P2QF | \ + SWITCH_INT_P3QF | SWITCH_INT_P4QF | SWITCH_INT_P5QF | \ + SWITCH_INT_CPQF | SWITCH_INT_GQF) + +#define SWITCH_INTS_ALL (SWITCH_INTS_HIGH | SWITCH_INTS_LOW | \ + SWITCH_INTS_ERR | SWITCH_INTS_Q | \ + SWITCH_INT_MD | SWITCH_INT_PSC) + +#define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC) +#define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF | SWITCH_INT_SLD) + +/* ------------------------------------------------------------------------ */ + +struct adm5120_if_priv { + struct net_device *dev; + + unsigned int vlan_no; + unsigned int port_mask; + +#ifdef CONFIG_ADM5120_SWITCH_NAPI + struct napi_struct napi; +#endif +}; + +struct dma_desc { + __u32 buf1; +#define DESC_OWN (1UL << 31) /* Owned by the switch */ +#define DESC_EOR (1UL << 28) /* End of Ring */ +#define DESC_ADDR_MASK 0x1FFFFFF +#define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK) + __u32 buf2; +#define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */ + __u32 buflen; + __u32 misc; +/* definitions for tx/rx descriptors */ +#define DESC_PKTLEN_SHIFT 16 +#define DESC_PKTLEN_MASK 0x7FF +/* tx descriptor specific part */ +#define DESC_CSUM (1UL << 31) /* Append checksum */ +#define DESC_DSTPORT_SHIFT 8 +#define DESC_DSTPORT_MASK 0x3F +#define DESC_VLAN_MASK 0x3F +/* rx descriptor specific part */ +#define DESC_SRCPORT_SHIFT 12 +#define DESC_SRCPORT_MASK 0x7 +#define DESC_DA_MASK 0x3 +#define DESC_DA_SHIFT 4 +#define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */ +#define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */ +#define DESC_TYPE_MASK 0x3 /* mask for Packet type */ +#define DESC_TYPE_IP 0x0 /* IP packet */ +#define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */ +} __attribute__ ((aligned(16))); + +/* ------------------------------------------------------------------------ */ + +static int adm5120_nrdevs; + +static struct net_device *adm5120_devs[SWITCH_NUM_PORTS]; +/* Lookup table port -> device */ +static struct net_device *adm5120_port[SWITCH_NUM_PORTS]; + +static struct dma_desc *txl_descs; +static struct dma_desc *rxl_descs; + +static dma_addr_t txl_descs_dma; +static dma_addr_t rxl_descs_dma; + +static struct sk_buff **txl_skbuff; +static struct sk_buff **rxl_skbuff; + +static unsigned int cur_rxl, dirty_rxl; /* producer/consumer ring indices */ +static unsigned int cur_txl, dirty_txl; + +static unsigned int sw_used; + +static DEFINE_SPINLOCK(tx_lock); + +/* ------------------------------------------------------------------------ */ + +static inline u32 sw_read_reg(u32 reg) +{ + return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg); +} + +static inline void sw_write_reg(u32 reg, u32 val) +{ + __raw_writel(val, (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg); +} + +static inline void sw_int_mask(u32 mask) +{ + u32 t; + + t = sw_read_reg(SWITCH_REG_INT_MASK); + t |= mask; + sw_write_reg(SWITCH_REG_INT_MASK, t); +} + +static inline void sw_int_unmask(u32 mask) +{ + u32 t; + + t = sw_read_reg(SWITCH_REG_INT_MASK); + t &= ~mask; + sw_write_reg(SWITCH_REG_INT_MASK, t); +} + +static inline void sw_int_ack(u32 mask) +{ + sw_write_reg(SWITCH_REG_INT_STATUS, mask); +} + +static inline u32 sw_int_status(void) +{ + u32 t; + + t = sw_read_reg(SWITCH_REG_INT_STATUS); + t &= ~sw_read_reg(SWITCH_REG_INT_MASK); + return t; +} + +static inline u32 desc_get_srcport(struct dma_desc *desc) +{ + return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK; +} + +static inline u32 desc_get_pktlen(struct dma_desc *desc) +{ + return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK; +} + +static inline int desc_ipcsum_fail(struct dma_desc *desc) +{ + return ((desc->misc & DESC_IPCSUM_FAIL) != 0); +} + +/* ------------------------------------------------------------------------ */ + +#ifdef CONFIG_ADM5120_SWITCH_DEBUG +static void sw_dump_desc(char *label, struct dma_desc *desc, int tx) +{ + u32 t; + + SW_DBG("%s %s desc/%p\n", label, tx ? "tx" : "rx", desc); + + t = desc->buf1; + SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t, + t & DESC_ADDR_MASK, + desc->buflen, + (t & DESC_OWN) ? "SWITCH" : "CPU", + (t & DESC_EOR) ? " RE" : ""); + + t = desc->buf2; + SW_DBG(" buf2 %08X addr=%08X%s\n", desc->buf2, + t & DESC_ADDR_MASK, + (t & DESC_BUF2_EN) ? " EN" : ""); + + t = desc->misc; + if (tx) + SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t, + (t & DESC_CSUM) ? " CSUM" : "", + (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK, + (t >> DESC_DSTPORT_SHIFT) & DESC_DSTPORT_MASK, + t & DESC_VLAN_MASK); + else + SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n", + t, + (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK, + (t >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK, + (t >> DESC_DA_SHIFT) & DESC_DA_MASK, + (t & DESC_IPCSUM_FAIL) ? " IPCF" : "", + (t & DESC_VLAN_TAG) ? " VLAN" : "", + (t & DESC_TYPE_MASK)); +} + +static void sw_dump_intr_mask(char *label, u32 mask) +{ + SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", + label, mask, + (mask & SWITCH_INT_SHD) ? " SHD" : "", + (mask & SWITCH_INT_SLD) ? " SLD" : "", + (mask & SWITCH_INT_RHD) ? " RHD" : "", + (mask & SWITCH_INT_RLD) ? " RLD" : "", + (mask & SWITCH_INT_HDF) ? " HDF" : "", + (mask & SWITCH_INT_LDF) ? " LDF" : "", + (mask & SWITCH_INT_P0QF) ? " P0QF" : "", + (mask & SWITCH_INT_P1QF) ? " P1QF" : "", + (mask & SWITCH_INT_P2QF) ? " P2QF" : "", + (mask & SWITCH_INT_P3QF) ? " P3QF" : "", + (mask & SWITCH_INT_P4QF) ? " P4QF" : "", + (mask & SWITCH_INT_CPQF) ? " CPQF" : "", + (mask & SWITCH_INT_GQF) ? " GQF" : "", + (mask & SWITCH_INT_MD) ? " MD" : "", + (mask & SWITCH_INT_BCS) ? " BCS" : "", + (mask & SWITCH_INT_PSC) ? " PSC" : "", + (mask & SWITCH_INT_ID) ? " ID" : "", + (mask & SWITCH_INT_W0TE) ? " W0TE" : "", + (mask & SWITCH_INT_W1TE) ? " W1TE" : "", + (mask & SWITCH_INT_RDE) ? " RDE" : "", + (mask & SWITCH_INT_SDE) ? " SDE" : "", + (mask & SWITCH_INT_CPUH) ? " CPUH" : ""); +} + +static void sw_dump_regs(void) +{ + u32 t; + + t = sw_read_reg(SWITCH_REG_PHY_STATUS); + SW_DBG("phy_status: %08X\n", t); + + t = sw_read_reg(SWITCH_REG_CPUP_CONF); + SW_DBG("cpup_conf: %08X%s%s%s\n", t, + (t & CPUP_CONF_DCPUP) ? " DCPUP" : "", + (t & CPUP_CONF_CRCP) ? " CRCP" : "", + (t & CPUP_CONF_BTM) ? " BTM" : ""); + + t = sw_read_reg(SWITCH_REG_PORT_CONF0); + SW_DBG("port_conf0: %08X\n", t); + t = sw_read_reg(SWITCH_REG_PORT_CONF1); + SW_DBG("port_conf1: %08X\n", t); + t = sw_read_reg(SWITCH_REG_PORT_CONF2); + SW_DBG("port_conf2: %08X\n", t); + + t = sw_read_reg(SWITCH_REG_VLAN_G1); + SW_DBG("vlan g1: %08X\n", t); + t = sw_read_reg(SWITCH_REG_VLAN_G2); + SW_DBG("vlan g2: %08X\n", t); + + t = sw_read_reg(SWITCH_REG_BW_CNTL0); + SW_DBG("bw_cntl0: %08X\n", t); + t = sw_read_reg(SWITCH_REG_BW_CNTL1); + SW_DBG("bw_cntl1: %08X\n", t); + + t = sw_read_reg(SWITCH_REG_PHY_CNTL0); + SW_DBG("phy_cntl0: %08X\n", t); + t = sw_read_reg(SWITCH_REG_PHY_CNTL1); + SW_DBG("phy_cntl1: %08X\n", t); + t = sw_read_reg(SWITCH_REG_PHY_CNTL2); + SW_DBG("phy_cntl2: %08X\n", t); + t = sw_read_reg(SWITCH_REG_PHY_CNTL3); + SW_DBG("phy_cntl3: %08X\n", t); + t = sw_read_reg(SWITCH_REG_PHY_CNTL4); + SW_DBG("phy_cntl4: %08X\n", t); + + t = sw_read_reg(SWITCH_REG_INT_STATUS); + sw_dump_intr_mask("int_status: ", t); + + t = sw_read_reg(SWITCH_REG_INT_MASK); + sw_dump_intr_mask("int_mask: ", t); + + t = sw_read_reg(SWITCH_REG_SHDA); + SW_DBG("shda: %08X\n", t); + t = sw_read_reg(SWITCH_REG_SLDA); + SW_DBG("slda: %08X\n", t); + t = sw_read_reg(SWITCH_REG_RHDA); + SW_DBG("rhda: %08X\n", t); + t = sw_read_reg(SWITCH_REG_RLDA); + SW_DBG("rlda: %08X\n", t); +} +#else +static inline void sw_dump_desc(char *label, struct dma_desc *desc, int tx) {} +static void sw_dump_intr_mask(char *label, u32 mask) {} +static inline void sw_dump_regs(void) {} +#endif /* CONFIG_ADM5120_SWITCH_DEBUG */ + +/* ------------------------------------------------------------------------ */ + +static inline void adm5120_rx_dma_update(struct dma_desc *desc, + struct sk_buff *skb, int end) +{ + desc->misc = 0; + desc->buf2 = 0; + desc->buflen = RX_MAX_PKTLEN; + desc->buf1 = DESC_ADDR(skb->data) | + DESC_OWN | (end ? DESC_EOR : 0); +} + +static void adm5120_switch_rx_refill(void) +{ + unsigned int entry; + + for (; cur_rxl - dirty_rxl > 0; dirty_rxl++) { + struct dma_desc *desc; + struct sk_buff *skb; + + entry = dirty_rxl % RX_RING_SIZE; + desc = &rxl_descs[entry]; + + skb = rxl_skbuff[entry]; + if (skb == NULL) { + skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC); + if (skb) { + skb_reserve(skb, SKB_RESERVE_LEN); + rxl_skbuff[entry] = skb; + } else { + SW_ERR("no memory for skb\n"); + desc->buflen = 0; + desc->buf2 = 0; + desc->misc = 0; + desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN; + break; + } + } + + desc->buf2 = 0; + desc->buflen = RX_MAX_PKTLEN; + desc->misc = 0; + desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN | + DESC_ADDR(skb->data); + } +} + +static int adm5120_switch_rx(int limit) +{ + unsigned int done = 0; + + SW_DBG("rx start, limit=%d, cur_rxl=%u, dirty_rxl=%u\n", + limit, cur_rxl, dirty_rxl); + + while (done < limit) { + int entry = cur_rxl % RX_RING_SIZE; + struct dma_desc *desc = &rxl_descs[entry]; + struct net_device *rdev; + unsigned int port; + + if (desc->buf1 & DESC_OWN) + break; + + if (dirty_rxl + RX_RING_SIZE == cur_rxl) + break; + + port = desc_get_srcport(desc); + rdev = adm5120_port[port]; + + SW_DBG("rx descriptor %u, desc=%p, skb=%p\n", entry, desc, + rxl_skbuff[entry]); + + if ((rdev) && netif_running(rdev)) { + struct sk_buff *skb = rxl_skbuff[entry]; + int pktlen; + + pktlen = desc_get_pktlen(desc); + pktlen -= ETH_CSUM_LEN; + + if ((pktlen == 0) || desc_ipcsum_fail(desc)) { + rdev->stats.rx_errors++; + if (pktlen == 0) + rdev->stats.rx_length_errors++; + if (desc_ipcsum_fail(desc)) + rdev->stats.rx_crc_errors++; + SW_DBG("rx error, recycling skb %u\n", entry); + } else { + skb_put(skb, pktlen); + + skb->dev = rdev; + skb->protocol = eth_type_trans(skb, rdev); + skb->ip_summed = CHECKSUM_UNNECESSARY; + + dma_cache_wback_inv((unsigned long)skb->data, + skb->len); + +#ifdef CONFIG_ADM5120_SWITCH_NAPI + netif_receive_skb(skb); +#else + netif_rx(skb); +#endif + + rdev->last_rx = jiffies; + rdev->stats.rx_packets++; + rdev->stats.rx_bytes += pktlen; + + rxl_skbuff[entry] = NULL; + done++; + } + } else { + SW_DBG("no rx device, recycling skb %u\n", entry); + } + + cur_rxl++; + if (cur_rxl - dirty_rxl > RX_RING_SIZE / 4) + adm5120_switch_rx_refill(); + } + + adm5120_switch_rx_refill(); + + SW_DBG("rx finished, cur_rxl=%u, dirty_rxl=%u, processed %d\n", + cur_rxl, dirty_rxl, done); + + return done; +} + +static void adm5120_switch_tx(void) +{ + unsigned int entry; + + spin_lock(&tx_lock); + entry = dirty_txl % TX_RING_SIZE; + while (dirty_txl != cur_txl) { + struct dma_desc *desc = &txl_descs[entry]; + struct sk_buff *skb = txl_skbuff[entry]; + + if (desc->buf1 & DESC_OWN) + break; + + if (netif_running(skb->dev)) { + skb->dev->stats.tx_bytes += skb->len; + skb->dev->stats.tx_packets++; + } + + dev_kfree_skb_irq(skb); + txl_skbuff[entry] = NULL; + entry = (++dirty_txl) % TX_RING_SIZE; + } + + if ((cur_txl - dirty_txl) < TX_QUEUE_LEN - 4) { + int i; + for (i = 0; i < SWITCH_NUM_PORTS; i++) { + if (!adm5120_devs[i]) + continue; + netif_wake_queue(adm5120_devs[i]); + } + } + spin_unlock(&tx_lock); +} + +#ifdef CONFIG_ADM5120_SWITCH_NAPI +static int adm5120_if_poll(struct napi_struct *napi, int limit) +{ + struct adm5120_if_priv *priv = container_of(napi, + struct adm5120_if_priv, napi); + struct net_device *dev __maybe_unused = priv->dev; + int done; + u32 status; + + sw_int_ack(SWITCH_INTS_POLL); + + SW_DBG("%s: processing TX ring\n", dev->name); + adm5120_switch_tx(); + + SW_DBG("%s: processing RX ring\n", dev->name); + done = adm5120_switch_rx(limit); + + status = sw_int_status() & SWITCH_INTS_POLL; + if ((done < limit) && (!status)) { + SW_DBG("disable polling mode for %s\n", dev->name); + napi_complete(napi); + sw_int_unmask(SWITCH_INTS_POLL); + return 0; + } + + SW_DBG("%s still in polling mode, done=%d, status=%x\n", + dev->name, done, status); + return 1; +} +#endif /* CONFIG_ADM5120_SWITCH_NAPI */ + + +static irqreturn_t adm5120_switch_irq(int irq, void *dev_id) +{ + u32 status; + + status = sw_int_status(); + status &= SWITCH_INTS_ALL; + if (!status) + return IRQ_NONE; + +#ifdef CONFIG_ADM5120_SWITCH_NAPI + sw_int_ack(status & ~SWITCH_INTS_POLL); + + if (status & SWITCH_INTS_POLL) { + struct net_device *dev = dev_id; + struct adm5120_if_priv *priv = netdev_priv(dev); + + sw_dump_intr_mask("poll ints", status); + SW_DBG("enable polling mode for %s\n", dev->name); + sw_int_mask(SWITCH_INTS_POLL); + napi_schedule(&priv->napi); + } +#else + sw_int_ack(status); + + if (status & (SWITCH_INT_RLD | SWITCH_INT_LDF)) + adm5120_switch_rx(RX_RING_SIZE); + + if (status & SWITCH_INT_SLD) + adm5120_switch_tx(); +#endif + + return IRQ_HANDLED; +} + +static void adm5120_set_bw(char *matrix) +{ + unsigned long val; + + /* Port 0 to 3 are set using the bandwidth control 0 register */ + val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24); + sw_write_reg(SWITCH_REG_BW_CNTL0, val); + + /* Port 4 and 5 are set using the bandwidth control 1 register */ + val = matrix[4]; + if (matrix[5] == 1) + sw_write_reg(SWITCH_REG_BW_CNTL1, val | 0x80000000); + else + sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000); + + SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0), + sw_read_reg(SWITCH_REG_BW_CNTL1)); +} + +static void adm5120_switch_tx_ring_reset(struct dma_desc *desc, + struct sk_buff **skbl, int num) +{ + memset(desc, 0, num * sizeof(*desc)); + desc[num-1].buf1 |= DESC_EOR; + memset(skbl, 0, sizeof(struct skb *) * num); + + cur_txl = 0; + dirty_txl = 0; +} + +static void adm5120_switch_rx_ring_reset(struct dma_desc *desc, + struct sk_buff **skbl, int num) +{ + int i; + + memset(desc, 0, num * sizeof(*desc)); + for (i = 0; i < num; i++) { + skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN); + if (!skbl[i]) { + i = num; + break; + } + skb_reserve(skbl[i], SKB_RESERVE_LEN); + adm5120_rx_dma_update(&desc[i], skbl[i], (num - 1 == i)); + } + + cur_rxl = 0; + dirty_rxl = 0; +} + +static int adm5120_switch_tx_ring_alloc(void) +{ + int err; + + txl_descs = dma_alloc_coherent(NULL, TX_DESCS_SIZE, &txl_descs_dma, + GFP_ATOMIC); + if (!txl_descs) { + err = -ENOMEM; + goto err; + } + + txl_skbuff = kzalloc(TX_SKBS_SIZE, GFP_KERNEL); + if (!txl_skbuff) { + err = -ENOMEM; + goto err; + } + + return 0; + +err: + return err; +} + +static void adm5120_switch_tx_ring_free(void) +{ + int i; + + if (txl_skbuff) { + for (i = 0; i < TX_RING_SIZE; i++) + if (txl_skbuff[i]) + kfree_skb(txl_skbuff[i]); + kfree(txl_skbuff); + } + + if (txl_descs) + dma_free_coherent(NULL, TX_DESCS_SIZE, txl_descs, + txl_descs_dma); +} + +static int adm5120_switch_rx_ring_alloc(void) +{ + int err; + int i; + + /* init RX ring */ + rxl_descs = dma_alloc_coherent(NULL, RX_DESCS_SIZE, &rxl_descs_dma, + GFP_ATOMIC); + if (!rxl_descs) { + err = -ENOMEM; + goto err; + } + + rxl_skbuff = kzalloc(RX_SKBS_SIZE, GFP_KERNEL); + if (!rxl_skbuff) { + err = -ENOMEM; + goto err; + } + + for (i = 0; i < RX_RING_SIZE; i++) { + struct sk_buff *skb; + skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC); + if (!skb) { + err = -ENOMEM; + goto err; + } + rxl_skbuff[i] = skb; + skb_reserve(skb, SKB_RESERVE_LEN); + } + + return 0; + +err: + return err; +} + +static void adm5120_switch_rx_ring_free(void) +{ + int i; + + if (rxl_skbuff) { + for (i = 0; i < RX_RING_SIZE; i++) + if (rxl_skbuff[i]) + kfree_skb(rxl_skbuff[i]); + kfree(rxl_skbuff); + } + + if (rxl_descs) + dma_free_coherent(NULL, RX_DESCS_SIZE, rxl_descs, + rxl_descs_dma); +} + +static void adm5120_write_mac(struct net_device *dev) +{ + struct adm5120_if_priv *priv = netdev_priv(dev); + unsigned char *mac = dev->dev_addr; + u32 t; + + t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) | + (mac[4] << MAC_WT1_MAC4_SHIFT) | (mac[5] << MAC_WT1_MAC5_SHIFT); + sw_write_reg(SWITCH_REG_MAC_WT1, t); + + t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) | + MAC_WT0_MAWC | MAC_WT0_WVE | (priv->vlan_no<<3); + + sw_write_reg(SWITCH_REG_MAC_WT0, t); + + while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD)) + ; +} + +static void adm5120_set_vlan(char *matrix) +{ + unsigned long val; + int vlan_port, port; + + val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24); + sw_write_reg(SWITCH_REG_VLAN_G1, val); + val = matrix[4] + (matrix[5]<<8); + sw_write_reg(SWITCH_REG_VLAN_G2, val); + + /* Now set/update the port vs. device lookup table */ + for (port = 0; port < SWITCH_NUM_PORTS; port++) { + for (vlan_port = 0; vlan_port < SWITCH_NUM_PORTS && !(matrix[vlan_port] & (0x00000001 << port)); vlan_port++) + ; + if (vlan_port < SWITCH_NUM_PORTS) + adm5120_port[port] = adm5120_devs[vlan_port]; + else + adm5120_port[port] = NULL; + } +} + +static void adm5120_switch_set_vlan_mac(unsigned int vlan, unsigned char *mac) +{ + u32 t; + + t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) + | (mac[4] << MAC_WT1_MAC4_SHIFT) + | (mac[5] << MAC_WT1_MAC5_SHIFT); + sw_write_reg(SWITCH_REG_MAC_WT1, t); + + t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) | + MAC_WT0_MAWC | MAC_WT0_WVE | (vlan << MAC_WT0_WVN_SHIFT) | + (MAC_WT0_WAF_STATIC << MAC_WT0_WAF_SHIFT); + sw_write_reg(SWITCH_REG_MAC_WT0, t); + + do { + t = sw_read_reg(SWITCH_REG_MAC_WT0); + } while ((t & MAC_WT0_MWD) == 0); +} + +static void adm5120_switch_set_vlan_ports(unsigned int vlan, u32 ports) +{ + unsigned int reg; + u32 t; + + if (vlan < 4) + reg = SWITCH_REG_VLAN_G1; + else { + vlan -= 4; + reg = SWITCH_REG_VLAN_G2; + } + + t = sw_read_reg(reg); + t &= ~(0xFF << (vlan*8)); + t |= (ports << (vlan*8)); + sw_write_reg(reg, t); +} + +/* ------------------------------------------------------------------------ */ + +#ifdef CONFIG_ADM5120_SWITCH_NAPI +static inline void adm5120_if_napi_enable(struct net_device *dev) +{ + struct adm5120_if_priv *priv = netdev_priv(dev); + napi_enable(&priv->napi); +} + +static inline void adm5120_if_napi_disable(struct net_device *dev) +{ + struct adm5120_if_priv *priv = netdev_priv(dev); + napi_disable(&priv->napi); +} +#else +static inline void adm5120_if_napi_enable(struct net_device *dev) {} +static inline void adm5120_if_napi_disable(struct net_device *dev) {} +#endif /* CONFIG_ADM5120_SWITCH_NAPI */ + +static int adm5120_if_open(struct net_device *dev) +{ + u32 t; + int err; + int i; + + adm5120_if_napi_enable(dev); + + err = request_irq(dev->irq, adm5120_switch_irq, IRQF_SHARED, + dev->name, dev); + if (err) { + SW_ERR("unable to get irq for %s\n", dev->name); + goto err; + } + + if (!sw_used++) + /* enable interrupts on first open */ + sw_int_unmask(SWITCH_INTS_USED); + + /* enable (additional) port */ + t = sw_read_reg(SWITCH_REG_PORT_CONF0); + for (i = 0; i < SWITCH_NUM_PORTS; i++) { + if (dev == adm5120_devs[i]) + t &= ~adm5120_eth_vlans[i]; + } + sw_write_reg(SWITCH_REG_PORT_CONF0, t); + + netif_start_queue(dev); + + return 0; + +err: + adm5120_if_napi_disable(dev); + return err; +} + +static int adm5120_if_stop(struct net_device *dev) +{ + u32 t; + int i; + + netif_stop_queue(dev); + adm5120_if_napi_disable(dev); + + /* disable port if not assigned to other devices */ + t = sw_read_reg(SWITCH_REG_PORT_CONF0); + t |= SWITCH_PORTS_NOCPU; + for (i = 0; i < SWITCH_NUM_PORTS; i++) { + if ((dev != adm5120_devs[i]) && netif_running(adm5120_devs[i])) + t &= ~adm5120_eth_vlans[i]; + } + sw_write_reg(SWITCH_REG_PORT_CONF0, t); + + if (!--sw_used) + sw_int_mask(SWITCH_INTS_USED); + + free_irq(dev->irq, dev); + + return 0; +} + +static int adm5120_if_hard_start_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct dma_desc *desc; + struct adm5120_if_priv *priv = netdev_priv(dev); + unsigned int entry; + unsigned long data; + int i; + + /* lock switch irq */ + spin_lock_irq(&tx_lock); + + /* calculate the next TX descriptor entry. */ + entry = cur_txl % TX_RING_SIZE; + + desc = &txl_descs[entry]; + if (desc->buf1 & DESC_OWN) { + /* We want to write a packet but the TX queue is still + * occupied by the DMA. We are faster than the DMA... */ + SW_DBG("%s unable to transmit, packet dopped\n", dev->name); + dev_kfree_skb(skb); + dev->stats.tx_dropped++; + return 0; + } + + txl_skbuff[entry] = skb; + data = (desc->buf1 & DESC_EOR); + data |= DESC_ADDR(skb->data); + + desc->misc = + ((skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len) << DESC_PKTLEN_SHIFT) | + (0x1 << priv->vlan_no); + + desc->buflen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + + desc->buf1 = data | DESC_OWN; + sw_write_reg(SWITCH_REG_SEND_TRIG, SEND_TRIG_STL); + + cur_txl++; + if (cur_txl == dirty_txl + TX_QUEUE_LEN) { + for (i = 0; i < SWITCH_NUM_PORTS; i++) { + if (!adm5120_devs[i]) + continue; + netif_stop_queue(adm5120_devs[i]); + } + } + + dev->trans_start = jiffies; + + spin_unlock_irq(&tx_lock); + + return 0; +} + +static void adm5120_if_tx_timeout(struct net_device *dev) +{ + SW_INFO("TX timeout on %s\n", dev->name); +} + +static void adm5120_if_set_rx_mode(struct net_device *dev) +{ + struct adm5120_if_priv *priv = netdev_priv(dev); + u32 ports; + u32 t; + + ports = adm5120_eth_vlans[priv->vlan_no] & SWITCH_PORTS_NOCPU; + + t = sw_read_reg(SWITCH_REG_CPUP_CONF); + if (dev->flags & IFF_PROMISC) + /* enable unknown packets */ + t &= ~(ports << CPUP_CONF_DUNP_SHIFT); + else + /* disable unknown packets */ + t |= (ports << CPUP_CONF_DUNP_SHIFT); + + if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI || + netdev_mc_count(dev)) + /* enable multicast packets */ + t &= ~(ports << CPUP_CONF_DMCP_SHIFT); + else + /* disable multicast packets */ + t |= (ports << CPUP_CONF_DMCP_SHIFT); + + /* If there is any port configured to be in promiscuous mode, then the */ + /* Bridge Test Mode has to be activated. This will result in */ + /* transporting also packets learned in another VLAN to be forwarded */ + /* to the CPU. */ + /* The difficult scenario is when we want to build a bridge on the CPU.*/ + /* Assume we have port0 and the CPU port in VLAN0 and port1 and the */ + /* CPU port in VLAN1. Now we build a bridge on the CPU between */ + /* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */ + /* Now assume a packet with ethernet source address 99 enters port 0 */ + /* It will be forwarded to the CPU because it is unknown. Then the */ + /* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */ + /* When now a packet with ethernet destination address 99 comes in at */ + /* port 1 in VLAN1, then the switch has learned that this address is */ + /* located at port 0 in VLAN0. Therefore the switch will drop */ + /* this packet. In order to avoid this and to send the packet still */ + /* to the CPU, the Bridge Test Mode has to be activated. */ + + /* Check if there is any vlan in promisc mode. */ + if (~t & (SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT)) + t |= CPUP_CONF_BTM; /* Enable Bridge Testing Mode */ + else + t &= ~CPUP_CONF_BTM; /* Disable Bridge Testing Mode */ + + sw_write_reg(SWITCH_REG_CPUP_CONF, t); + +} + +static int adm5120_if_set_mac_address(struct net_device *dev, void *p) +{ + int ret; + + ret = eth_mac_addr(dev, p); + if (ret) + return ret; + + adm5120_write_mac(dev); + return 0; +} + +static int adm5120_if_do_ioctl(struct net_device *dev, struct ifreq *rq, + int cmd) +{ + int err; + struct adm5120_sw_info info; + struct adm5120_if_priv *priv = netdev_priv(dev); + + switch (cmd) { + case SIOCGADMINFO: + info.magic = 0x5120; + info.ports = adm5120_nrdevs; + info.vlan = priv->vlan_no; + err = copy_to_user(rq->ifr_data, &info, sizeof(info)); + if (err) + return -EFAULT; + break; + case SIOCSMATRIX: + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + err = copy_from_user(adm5120_eth_vlans, rq->ifr_data, + sizeof(adm5120_eth_vlans)); + if (err) + return -EFAULT; + adm5120_set_vlan(adm5120_eth_vlans); + break; + case SIOCGMATRIX: + err = copy_to_user(rq->ifr_data, adm5120_eth_vlans, + sizeof(adm5120_eth_vlans)); + if (err) + return -EFAULT; + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +static const struct net_device_ops adm5120sw_netdev_ops = { + .ndo_open = adm5120_if_open, + .ndo_stop = adm5120_if_stop, + .ndo_start_xmit = adm5120_if_hard_start_xmit, + .ndo_set_rx_mode = adm5120_if_set_rx_mode, + .ndo_do_ioctl = adm5120_if_do_ioctl, + .ndo_tx_timeout = adm5120_if_tx_timeout, + .ndo_validate_addr = eth_validate_addr, + .ndo_change_mtu = eth_change_mtu, + .ndo_set_mac_address = adm5120_if_set_mac_address, +}; + +static struct net_device *adm5120_if_alloc(void) +{ + struct net_device *dev; + struct adm5120_if_priv *priv; + + dev = alloc_etherdev(sizeof(*priv)); + if (!dev) + return NULL; + + priv = netdev_priv(dev); + priv->dev = dev; + + dev->irq = ADM5120_IRQ_SWITCH; + dev->netdev_ops = &adm5120sw_netdev_ops; + dev->watchdog_timeo = TX_TIMEOUT; + +#ifdef CONFIG_ADM5120_SWITCH_NAPI + netif_napi_add(dev, &priv->napi, adm5120_if_poll, 64); +#endif + + return dev; +} + +/* ------------------------------------------------------------------------ */ + +static void adm5120_switch_cleanup(void) +{ + int i; + + /* disable interrupts */ + sw_int_mask(SWITCH_INTS_ALL); + + for (i = 0; i < SWITCH_NUM_PORTS; i++) { + struct net_device *dev = adm5120_devs[i]; + if (dev) { + unregister_netdev(dev); + free_netdev(dev); + } + } + + adm5120_switch_tx_ring_free(); + adm5120_switch_rx_ring_free(); +} + +static int adm5120_switch_probe(struct platform_device *pdev) +{ + u32 t; + int i, err; + + adm5120_nrdevs = adm5120_eth_num_ports; + + t = CPUP_CONF_DCPUP | CPUP_CONF_CRCP | + SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT | + SWITCH_PORTS_NOCPU << CPUP_CONF_DMCP_SHIFT ; + sw_write_reg(SWITCH_REG_CPUP_CONF, t); + + t = (SWITCH_PORTS_NOCPU << PORT_CONF0_EMCP_SHIFT) | + (SWITCH_PORTS_NOCPU << PORT_CONF0_BP_SHIFT) | + (SWITCH_PORTS_NOCPU); + sw_write_reg(SWITCH_REG_PORT_CONF0, t); + + /* setup ports to Autoneg/100M/Full duplex/Auto MDIX */ + t = SWITCH_PORTS_PHY | + (SWITCH_PORTS_PHY << PHY_CNTL2_SC_SHIFT) | + (SWITCH_PORTS_PHY << PHY_CNTL2_DC_SHIFT) | + (SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) | + (SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) | + PHY_CNTL2_RMAE; + sw_write_reg(SWITCH_REG_PHY_CNTL2, t); + + t = sw_read_reg(SWITCH_REG_PHY_CNTL3); + t |= PHY_CNTL3_RNT; + sw_write_reg(SWITCH_REG_PHY_CNTL3, t); + + /* Force all the packets from all ports are low priority */ + sw_write_reg(SWITCH_REG_PRI_CNTL, 0); + + sw_int_mask(SWITCH_INTS_ALL); + sw_int_ack(SWITCH_INTS_ALL); + + err = adm5120_switch_rx_ring_alloc(); + if (err) + goto err; + + err = adm5120_switch_tx_ring_alloc(); + if (err) + goto err; + + adm5120_switch_tx_ring_reset(txl_descs, txl_skbuff, TX_RING_SIZE); + adm5120_switch_rx_ring_reset(rxl_descs, rxl_skbuff, RX_RING_SIZE); + + sw_write_reg(SWITCH_REG_SHDA, 0); + sw_write_reg(SWITCH_REG_SLDA, KSEG1ADDR(txl_descs)); + sw_write_reg(SWITCH_REG_RHDA, 0); + sw_write_reg(SWITCH_REG_RLDA, KSEG1ADDR(rxl_descs)); + + for (i = 0; i < SWITCH_NUM_PORTS; i++) { + struct net_device *dev; + struct adm5120_if_priv *priv; + + dev = adm5120_if_alloc(); + if (!dev) { + err = -ENOMEM; + goto err; + } + + adm5120_devs[i] = dev; + priv = netdev_priv(dev); + + priv->vlan_no = i; + priv->port_mask = adm5120_eth_vlans[i]; + + memcpy(dev->dev_addr, adm5120_eth_macs[i], 6); + adm5120_write_mac(dev); + + err = register_netdev(dev); + if (err) { + SW_INFO("%s register failed, error=%d\n", + dev->name, err); + goto err; + } + } + + /* setup vlan/port mapping after devs are filled up */ + adm5120_set_vlan(adm5120_eth_vlans); + + /* enable CPU port */ + t = sw_read_reg(SWITCH_REG_CPUP_CONF); + t &= ~CPUP_CONF_DCPUP; + sw_write_reg(SWITCH_REG_CPUP_CONF, t); + + return 0; + +err: + adm5120_switch_cleanup(); + + SW_ERR("init failed\n"); + return err; +} + +static int adm5120_switch_remove(struct platform_device *pdev) +{ + adm5120_switch_cleanup(); + return 0; +} + +static struct platform_driver adm5120_switch_driver = { + .probe = adm5120_switch_probe, + .remove = adm5120_switch_remove, + .driver = { + .name = DRV_NAME, + }, +}; + +/* -------------------------------------------------------------------------- */ + +static int __init adm5120_switch_mod_init(void) +{ + int err; + + pr_info(DRV_DESC " version " DRV_VERSION "\n"); + err = platform_driver_register(&adm5120_switch_driver); + + return err; +} + +static void __exit adm5120_switch_mod_exit(void) +{ + platform_driver_unregister(&adm5120_switch_driver); +} + +module_init(adm5120_switch_mod_init); +module_exit(adm5120_switch_mod_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); diff --git a/target/linux/adm5120/files-3.18/drivers/net/adm5120sw.h b/target/linux/adm5120/files-3.18/drivers/net/adm5120sw.h new file mode 100644 index 0000000..fa9e503 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/net/adm5120sw.h @@ -0,0 +1,23 @@ +/* + * Defines for ADM5120 built in ethernet switch driver + * + * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005 + * + * Values come from ADM5120 datasheet and original ADMtek 2.4 driver, + * Copyright ADMtek Inc. + */ + +#ifndef _INCLUDE_ADM5120SW_H_ +#define _INCLUDE_ADM5120SW_H_ + +#define SIOCSMATRIX SIOCDEVPRIVATE +#define SIOCGMATRIX (SIOCDEVPRIVATE + 1) +#define SIOCGADMINFO (SIOCDEVPRIVATE + 2) + +struct adm5120_sw_info { + u16 magic; + u16 ports; + u16 vlan; +}; + +#endif /* _INCLUDE_ADM5120SW_H_ */ diff --git a/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-dbg.c b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-dbg.c new file mode 100644 index 0000000..2d5dc2a --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-dbg.c @@ -0,0 +1,836 @@ +/* + * ADM5120 HCD (Host Controller Driver) for USB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: drivers/usb/host/ohci-dbg.c + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +/*-------------------------------------------------------------------------*/ + +static inline char *ed_typestring(int ed_type) +{ + switch (ed_type) { + case PIPE_CONTROL: + return "ctrl"; + case PIPE_BULK: + return "bulk"; + case PIPE_INTERRUPT: + return "intr"; + case PIPE_ISOCHRONOUS: + return "isoc"; + } + return "(bad ed_type)"; +} + +static inline char *ed_statestring(int state) +{ + switch (state) { + case ED_IDLE: + return "IDLE"; + case ED_UNLINK: + return "UNLINK"; + case ED_OPER: + return "OPER"; + } + return "?STATE"; +} + +static inline char *pipestring(int pipe) +{ + return ed_typestring(usb_pipetype(pipe)); +} + +static inline char *td_pidstring(u32 info) +{ + switch (info & TD_DP) { + case TD_DP_SETUP: + return "SETUP"; + case TD_DP_IN: + return "IN"; + case TD_DP_OUT: + return "OUT"; + } + return "?PID"; +} + +static inline char *td_togglestring(u32 info) +{ + switch (info & TD_T) { + case TD_T_DATA0: + return "DATA0"; + case TD_T_DATA1: + return "DATA1"; + case TD_T_CARRY: + return "CARRY"; + } + return "?TOGGLE"; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header + */ +static void __attribute__((unused)) +urb_print(struct admhcd *ahcd, struct urb *urb, char *str, int small, int status) +{ + unsigned int pipe = urb->pipe; + + if (!urb->dev || !urb->dev->bus) { + admhc_dbg(ahcd, "%s URB: no dev", str); + return; + } + +#ifndef ADMHC_VERBOSE_DEBUG + if (status != 0) +#endif + admhc_dbg(ahcd, "URB-%s %p dev=%d ep=%d%s-%s flags=%x len=%d/%d " + "stat=%d\n", + str, + urb, + usb_pipedevice(pipe), + usb_pipeendpoint(pipe), + usb_pipeout(pipe) ? "out" : "in", + pipestring(pipe), + urb->transfer_flags, + urb->actual_length, + urb->transfer_buffer_length, + status); + +#ifdef ADMHC_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol(pipe)) { + admhc_dbg(ahcd, "setup(8):"); + for (i = 0; i < 8 ; i++) + printk(KERN_INFO" %02x", ((__u8 *)urb->setup_packet)[i]); + printk(KERN_INFO "\n"); + } + if (urb->transfer_buffer_length > 0 && urb->transfer_buffer) { + admhc_dbg(ahcd, "data(%d/%d):", + urb->actual_length, + urb->transfer_buffer_length); + len = usb_pipeout(pipe) ? + urb->transfer_buffer_length : urb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printk(KERN_INFO " %02x", ((__u8 *)urb->transfer_buffer)[i]); + printk(KERN_INFO "%s stat:%d\n", i < len ? "..." : "", status); + } + } +#endif /* ADMHC_VERBOSE_DEBUG */ +} + +#define admhc_dbg_sw(ahcd, next, size, format, arg...) \ + do { \ + if (next) { \ + unsigned s_len; \ + s_len = scnprintf(*next, *size, format, ## arg); \ + *size -= s_len; *next += s_len; \ + } else \ + admhc_dbg(ahcd, format, ## arg); \ + } while (0); + + +static void admhc_dump_intr_mask(struct admhcd *ahcd, char *label, u32 mask, + char **next, unsigned *size) +{ + admhc_dbg_sw(ahcd, next, size, "%s 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", + label, + mask, + (mask & ADMHC_INTR_INTA) ? " INTA" : "", + (mask & ADMHC_INTR_FATI) ? " FATI" : "", + (mask & ADMHC_INTR_SWI) ? " SWI" : "", + (mask & ADMHC_INTR_TDC) ? " TDC" : "", + (mask & ADMHC_INTR_FNO) ? " FNO" : "", + (mask & ADMHC_INTR_SO) ? " SO" : "", + (mask & ADMHC_INTR_INSM) ? " INSM" : "", + (mask & ADMHC_INTR_BABI) ? " BABI" : "", + (mask & ADMHC_INTR_7) ? " !7!" : "", + (mask & ADMHC_INTR_6) ? " !6!" : "", + (mask & ADMHC_INTR_RESI) ? " RESI" : "", + (mask & ADMHC_INTR_SOFI) ? " SOFI" : "" + ); +} + +static void maybe_print_eds(struct admhcd *ahcd, char *label, u32 value, + char **next, unsigned *size) +{ + if (value) + admhc_dbg_sw(ahcd, next, size, "%s %08x\n", label, value); +} + +static char *buss2string(int state) +{ + switch (state) { + case ADMHC_BUSS_RESET: + return "reset"; + case ADMHC_BUSS_RESUME: + return "resume"; + case ADMHC_BUSS_OPER: + return "operational"; + case ADMHC_BUSS_SUSPEND: + return "suspend"; + } + return "?state"; +} + +static void +admhc_dump_status(struct admhcd *ahcd, char **next, unsigned *size) +{ + struct admhcd_regs __iomem *regs = ahcd->regs; + u32 temp; + + temp = admhc_readl(ahcd, ®s->gencontrol); + admhc_dbg_sw(ahcd, next, size, + "gencontrol 0x%08x%s%s%s%s\n", + temp, + (temp & ADMHC_CTRL_UHFE) ? " UHFE" : "", + (temp & ADMHC_CTRL_SIR) ? " SIR" : "", + (temp & ADMHC_CTRL_DMAA) ? " DMAA" : "", + (temp & ADMHC_CTRL_SR) ? " SR" : "" + ); + + temp = admhc_readl(ahcd, ®s->host_control); + admhc_dbg_sw(ahcd, next, size, + "host_control 0x%08x BUSS=%s%s\n", + temp, + buss2string(temp & ADMHC_HC_BUSS), + (temp & ADMHC_HC_DMAE) ? " DMAE" : "" + ); + + admhc_dump_intr_mask(ahcd, "int_status", + admhc_readl(ahcd, ®s->int_status), + next, size); + admhc_dump_intr_mask(ahcd, "int_enable", + admhc_readl(ahcd, ®s->int_enable), + next, size); + + maybe_print_eds(ahcd, "hosthead", + admhc_readl(ahcd, ®s->hosthead), next, size); +} + +#define dbg_port_sw(hc, num, value, next, size) \ + admhc_dbg_sw(hc, next, size, \ + "portstatus [%d] " \ + "0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \ + num, temp, \ + (temp & ADMHC_PS_PRSC) ? " PRSC" : "", \ + (temp & ADMHC_PS_OCIC) ? " OCIC" : "", \ + (temp & ADMHC_PS_PSSC) ? " PSSC" : "", \ + (temp & ADMHC_PS_PESC) ? " PESC" : "", \ + (temp & ADMHC_PS_CSC) ? " CSC" : "", \ + \ + (temp & ADMHC_PS_LSDA) ? " LSDA" : "", \ + (temp & ADMHC_PS_PPS) ? " PPS" : "", \ + (temp & ADMHC_PS_PRS) ? " PRS" : "", \ + (temp & ADMHC_PS_POCI) ? " POCI" : "", \ + (temp & ADMHC_PS_PSS) ? " PSS" : "", \ + \ + (temp & ADMHC_PS_PES) ? " PES" : "", \ + (temp & ADMHC_PS_CCS) ? " CCS" : "" \ + ); + + +static void +admhc_dump_roothub( + struct admhcd *ahcd, + int verbose, + char **next, + unsigned *size) +{ + u32 temp, i; + + temp = admhc_read_rhdesc(ahcd); + if (temp == ~(u32)0) + return; + + if (verbose) { + admhc_dbg_sw(ahcd, next, size, + "rhdesc %08x%s%s%s%s%s%s PPCM=%02x%s%s%s%s NUMP=%d(%d)\n", + temp, + (temp & ADMHC_RH_CRWE) ? " CRWE" : "", + (temp & ADMHC_RH_OCIC) ? " OCIC" : "", + (temp & ADMHC_RH_LPSC) ? " LPSC" : "", + (temp & ADMHC_RH_LPSC) ? " DRWE" : "", + (temp & ADMHC_RH_LPSC) ? " OCI" : "", + (temp & ADMHC_RH_LPSC) ? " LPS" : "", + ((temp & ADMHC_RH_PPCM) >> 16), + (temp & ADMHC_RH_NOCP) ? " NOCP" : "", + (temp & ADMHC_RH_OCPM) ? " OCPM" : "", + (temp & ADMHC_RH_NPS) ? " NPS" : "", + (temp & ADMHC_RH_PSM) ? " PSM" : "", + (temp & ADMHC_RH_NUMP), ahcd->num_ports + ); + } + + for (i = 0; i < ahcd->num_ports; i++) { + temp = admhc_read_portstatus(ahcd, i); + dbg_port_sw(ahcd, i, temp, next, size); + } +} + +static void admhc_dump(struct admhcd *ahcd, int verbose) +{ + admhc_dbg(ahcd, "ADMHC ahcd state\n"); + + /* dumps some of the state we know about */ + admhc_dump_status(ahcd, NULL, NULL); + admhc_dbg(ahcd, "current frame #%04x\n", + admhc_frame_no(ahcd)); + + admhc_dump_roothub(ahcd, verbose, NULL, NULL); +} + +static const char data0[] = "DATA0"; +static const char data1[] = "DATA1"; + +static void admhc_dump_td(const struct admhcd *ahcd, const char *label, + const struct td *td) +{ + u32 tmp; + + admhc_dbg(ahcd, "%s td %p; urb %p index %d; hwNextTD %08x\n", + label, td, + td->urb, td->index, + hc32_to_cpup(ahcd, &td->hwNextTD)); + + tmp = hc32_to_cpup(ahcd, &td->hwINFO); + admhc_dbg(ahcd, " status %08x%s CC=%x EC=%d %s %s ISI=%x FN=%x\n", + tmp, + (tmp & TD_OWN) ? " OWN" : "", + TD_CC_GET(tmp), + TD_EC_GET(tmp), + td_togglestring(tmp), + td_pidstring(tmp), + TD_ISI_GET(tmp), + TD_FN_GET(tmp)); + + tmp = hc32_to_cpup(ahcd, &td->hwCBL); + admhc_dbg(ahcd, " dbp %08x; cbl %08x; LEN=%d%s\n", + hc32_to_cpup(ahcd, &td->hwDBP), + tmp, + TD_BL_GET(tmp), + (tmp & TD_IE) ? " IE" : ""); +} + +/* caller MUST own hcd spinlock if verbose is set! */ +static void __attribute__((unused)) +admhc_dump_ed(const struct admhcd *ahcd, const char *label, + const struct ed *ed, int verbose) +{ + u32 tmp = hc32_to_cpu(ahcd, ed->hwINFO); + + admhc_dbg(ahcd, "%s ed %p %s type %s; next ed %08x\n", + label, + ed, ed_statestring(ed->state), ed_typestring(ed->type), + hc32_to_cpup(ahcd, &ed->hwNextED)); + + admhc_dbg(ahcd, " info %08x MAX=%d%s%s%s%s EP=%d DEV=%d\n", tmp, + ED_MPS_GET(tmp), + (tmp & ED_ISO) ? " ISO" : "", + (tmp & ED_SKIP) ? " SKIP" : "", + (tmp & ED_SPEED_FULL) ? " FULL" : " LOW", + (tmp & ED_INT) ? " INT" : "", + ED_EN_GET(tmp), + ED_FA_GET(tmp)); + + tmp = hc32_to_cpup(ahcd, &ed->hwHeadP); + admhc_dbg(ahcd, " tds: head %08x tail %08x %s%s%s\n", + tmp & TD_MASK, + hc32_to_cpup(ahcd, &ed->hwTailP), + (tmp & ED_C) ? data1 : data0, + (tmp & ED_H) ? " HALT" : "", + verbose ? " td list follows" : " (not listing)"); + + if (verbose) { + struct list_head *tmp; + + /* use ed->td_list because HC concurrently modifies + * hwNextTD as it accumulates ed_donelist. + */ + list_for_each(tmp, &ed->td_list) { + struct td *td; + td = list_entry(tmp, struct td, td_list); + admhc_dump_td(ahcd, " ->", td); + } + } +} + +#else /* ifdef DEBUG */ + +static inline void urb_print(struct admhcd *ahcd, struct urb * urb, char * str, + int small, int status) {} +static inline void admhc_dump_ed(const struct admhcd *ahcd, const char *label, + const struct ed *ed, int verbose) {} +static inline void admhc_dump_td(const struct admhcd *ahcd, const char *label, + const struct td *td) {} +static inline void admhc_dump(struct admhcd *ahcd, int verbose) {} + +#undef ADMHC_VERBOSE_DEBUG + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------*/ + +#ifdef STUB_DEBUG_FILES + +static inline void create_debug_files(struct admhcd *bus) { } +static inline void remove_debug_files(struct admhcd *bus) { } + +#else + +static int debug_async_open(struct inode *, struct file *); +static int debug_periodic_open(struct inode *, struct file *); +static int debug_registers_open(struct inode *, struct file *); +static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*); +static int debug_close(struct inode *, struct file *); + +static const struct file_operations debug_async_fops = { + .owner = THIS_MODULE, + .open = debug_async_open, + .read = debug_output, + .release = debug_close, + .llseek = default_llseek, +}; +static const struct file_operations debug_periodic_fops = { + .owner = THIS_MODULE, + .open = debug_periodic_open, + .read = debug_output, + .release = debug_close, + .llseek = default_llseek, +}; +static const struct file_operations debug_registers_fops = { + .owner = THIS_MODULE, + .open = debug_registers_open, + .read = debug_output, + .release = debug_close, + .llseek = default_llseek, +}; + +static struct dentry *admhc_debug_root; + +struct debug_buffer { + ssize_t (*fill_func)(struct debug_buffer *); /* fill method */ + struct admhcd *ahcd; + struct mutex mutex; /* protect filling of buffer */ + size_t count; /* number of characters filled into buffer */ + char *page; +}; + +static ssize_t +show_list(struct admhcd *ahcd, char *buf, size_t count, struct ed *ed) +{ + unsigned temp; + unsigned size = count; + + if (!ed) + return 0; + + /* dump a snapshot of the bulk or control schedule */ + while (ed) { + u32 info = hc32_to_cpu(ahcd, ed->hwINFO); + u32 headp = hc32_to_cpu(ahcd, ed->hwHeadP); + u32 tailp = hc32_to_cpu(ahcd, ed->hwTailP); + struct list_head *entry; + struct td *td; + + temp = scnprintf(buf, size, + "ed/%p %s %s %cs dev%d ep%d %s%smax %d %08x%s%s %s" + " h:%08x t:%08x", + ed, + ed_statestring(ed->state), + ed_typestring(ed->type), + (info & ED_SPEED_FULL) ? 'f' : 'l', + info & ED_FA_MASK, + (info >> ED_EN_SHIFT) & ED_EN_MASK, + (info & ED_INT) ? "INT " : "", + (info & ED_ISO) ? "ISO " : "", + (info >> ED_MPS_SHIFT) & ED_MPS_MASK , + info, + (info & ED_SKIP) ? " S" : "", + (headp & ED_H) ? " H" : "", + (headp & ED_C) ? data1 : data0, + headp & ED_MASK, tailp); + size -= temp; + buf += temp; + + list_for_each(entry, &ed->td_list) { + u32 dbp, cbl; + + td = list_entry(entry, struct td, td_list); + info = hc32_to_cpup(ahcd, &td->hwINFO); + dbp = hc32_to_cpup(ahcd, &td->hwDBP); + cbl = hc32_to_cpup(ahcd, &td->hwCBL); + + temp = scnprintf(buf, size, + "\n\ttd/%p %s %d %s%scc=%x urb %p (%08x,%08x)", + td, + td_pidstring(info), + TD_BL_GET(cbl), + (info & TD_OWN) ? "" : "DONE ", + (cbl & TD_IE) ? "IE " : "", + TD_CC_GET(info), td->urb, info, cbl); + size -= temp; + buf += temp; + } + + temp = scnprintf(buf, size, "\n"); + size -= temp; + buf += temp; + + ed = ed->ed_next; + } + + return count - size; +} + +static ssize_t fill_async_buffer(struct debug_buffer *buf) +{ + struct admhcd *ahcd; + size_t temp; + unsigned long flags; + + ahcd = buf->ahcd; + + spin_lock_irqsave(&ahcd->lock, flags); + temp = show_list(ahcd, buf->page, PAGE_SIZE, ahcd->ed_head); + spin_unlock_irqrestore(&ahcd->lock, flags); + + return temp; +} + + +#define DBG_SCHED_LIMIT 64 + +static ssize_t fill_periodic_buffer(struct debug_buffer *buf) +{ + struct admhcd *ahcd; + struct ed **seen, *ed; + unsigned long flags; + unsigned temp, size, seen_count; + char *next; + unsigned i; + + seen = kmalloc(DBG_SCHED_LIMIT * sizeof(*seen), GFP_ATOMIC); + if (!seen) + return 0; + seen_count = 0; + + ahcd = buf->ahcd; + next = buf->page; + size = PAGE_SIZE; + + temp = scnprintf(next, size, "size = %d\n", NUM_INTS); + size -= temp; + next += temp; + + /* dump a snapshot of the periodic schedule (and load) */ + spin_lock_irqsave(&ahcd->lock, flags); + for (i = 0; i < NUM_INTS; i++) { + ed = ahcd->periodic[i]; + if (!ed) + continue; + + temp = scnprintf(next, size, "%2d [%3d]:", i, ahcd->load[i]); + size -= temp; + next += temp; + + do { + temp = scnprintf(next, size, " ed%d/%p", + ed->interval, ed); + size -= temp; + next += temp; + for (temp = 0; temp < seen_count; temp++) { + if (seen[temp] == ed) + break; + } + + /* show more info the first time around */ + if (temp == seen_count) { + u32 info = hc32_to_cpu(ahcd, ed->hwINFO); + struct list_head *entry; + unsigned qlen = 0; + + /* qlen measured here in TDs, not urbs */ + list_for_each(entry, &ed->td_list) + qlen++; + temp = scnprintf(next, size, + " (%cs dev%d ep%d%s qlen %u" + " max %d %08x%s%s)", + (info & ED_SPEED_FULL) ? 'f' : 'l', + ED_FA_GET(info), + ED_EN_GET(info), + (info & ED_ISO) ? "iso" : "int", + qlen, + ED_MPS_GET(info), + info, + (info & ED_SKIP) ? " K" : "", + (ed->hwHeadP & + cpu_to_hc32(ahcd, ED_H)) ? + " H" : ""); + size -= temp; + next += temp; + + if (seen_count < DBG_SCHED_LIMIT) + seen[seen_count++] = ed; + + ed = ed->ed_next; + + } else { + /* we've seen it and what's after */ + temp = 0; + ed = NULL; + } + + } while (ed); + + temp = scnprintf(next, size, "\n"); + size -= temp; + next += temp; + } + spin_unlock_irqrestore(&ahcd->lock, flags); + kfree(seen); + + return PAGE_SIZE - size; +} + + +#undef DBG_SCHED_LIMIT + +static ssize_t fill_registers_buffer(struct debug_buffer *buf) +{ + struct usb_hcd *hcd; + struct admhcd *ahcd; + struct admhcd_regs __iomem *regs; + unsigned long flags; + unsigned temp, size; + char *next; + u32 rdata; + + ahcd = buf->ahcd; + hcd = admhc_to_hcd(ahcd); + regs = ahcd->regs; + next = buf->page; + size = PAGE_SIZE; + + spin_lock_irqsave(&ahcd->lock, flags); + + /* dump driver info, then registers in spec order */ + + admhc_dbg_sw(ahcd, &next, &size, + "bus %s, device %s\n" + "%s\n" + "%s\n", + hcd->self.controller->bus->name, + dev_name(hcd->self.controller), + hcd->product_desc, + hcd_name); + + if (!HCD_HW_ACCESSIBLE(hcd)) { + size -= scnprintf(next, size, + "SUSPENDED (no register access)\n"); + goto done; + } + + admhc_dump_status(ahcd, &next, &size); + + /* other registers mostly affect frame timings */ + rdata = admhc_readl(ahcd, ®s->fminterval); + temp = scnprintf(next, size, + "fmintvl 0x%08x %sFSLDP=0x%04x FI=0x%04x\n", + rdata, (rdata & ADMHC_SFI_FIT) ? "FIT " : "", + (rdata >> ADMHC_SFI_FSLDP_SHIFT) & ADMHC_SFI_FSLDP_MASK, + rdata & ADMHC_SFI_FI_MASK); + size -= temp; + next += temp; + + rdata = admhc_readl(ahcd, ®s->fmnumber); + temp = scnprintf(next, size, "fmnumber 0x%08x %sFR=0x%04x FN=%04x\n", + rdata, (rdata & ADMHC_SFN_FRT) ? "FRT " : "", + (rdata >> ADMHC_SFN_FR_SHIFT) & ADMHC_SFN_FR_MASK, + rdata & ADMHC_SFN_FN_MASK); + size -= temp; + next += temp; + + /* TODO: use predefined bitmask */ + rdata = admhc_readl(ahcd, ®s->lsthresh); + temp = scnprintf(next, size, "lsthresh 0x%04x\n", + rdata & 0x3fff); + size -= temp; + next += temp; + + temp = scnprintf(next, size, "hub poll timer: %s\n", + admhcd_to_hcd(ahcd)->poll_rh ? "ON" : "OFF"); + size -= temp; + next += temp; + + /* roothub */ + admhc_dump_roothub(ahcd, 1, &next, &size); + +done: + spin_unlock_irqrestore(&ahcd->lock, flags); + return PAGE_SIZE - size; +} + + +static struct debug_buffer *alloc_buffer(struct admhcd *ahcd, + ssize_t (*fill_func)(struct debug_buffer *)) +{ + struct debug_buffer *buf; + + buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL); + + if (buf) { + buf->ahcd = ahcd; + buf->fill_func = fill_func; + mutex_init(&buf->mutex); + } + + return buf; +} + +static int fill_buffer(struct debug_buffer *buf) +{ + int ret = 0; + + if (!buf->page) + buf->page = (char *)get_zeroed_page(GFP_KERNEL); + + if (!buf->page) { + ret = -ENOMEM; + goto out; + } + + ret = buf->fill_func(buf); + + if (ret >= 0) { + buf->count = ret; + ret = 0; + } + +out: + return ret; +} + +static ssize_t debug_output(struct file *file, char __user *user_buf, + size_t len, loff_t *offset) +{ + struct debug_buffer *buf = file->private_data; + int ret = 0; + + mutex_lock(&buf->mutex); + if (buf->count == 0) { + ret = fill_buffer(buf); + if (ret != 0) { + mutex_unlock(&buf->mutex); + goto out; + } + } + mutex_unlock(&buf->mutex); + + ret = simple_read_from_buffer(user_buf, len, offset, + buf->page, buf->count); + +out: + return ret; +} + +static int debug_close(struct inode *inode, struct file *file) +{ + struct debug_buffer *buf = file->private_data; + + if (buf) { + if (buf->page) + free_page((unsigned long)buf->page); + kfree(buf); + } + + return 0; +} + +static int debug_async_open(struct inode *inode, struct file *file) +{ + file->private_data = alloc_buffer(inode->i_private, fill_async_buffer); + + return file->private_data ? 0 : -ENOMEM; +} + +static int debug_periodic_open(struct inode *inode, struct file *file) +{ + file->private_data = alloc_buffer(inode->i_private, + fill_periodic_buffer); + + return file->private_data ? 0 : -ENOMEM; +} + +static int debug_registers_open(struct inode *inode, struct file *file) +{ + file->private_data = alloc_buffer(inode->i_private, + fill_registers_buffer); + + return file->private_data ? 0 : -ENOMEM; +} + +static inline void create_debug_files(struct admhcd *ahcd) +{ + struct usb_bus *bus = &admhcd_to_hcd(ahcd)->self; + + ahcd->debug_dir = debugfs_create_dir(bus->bus_name, admhc_debug_root); + if (!ahcd->debug_dir) + goto dir_error; + + ahcd->debug_async = debugfs_create_file("async", S_IRUGO, + ahcd->debug_dir, ahcd, + &debug_async_fops); + if (!ahcd->debug_async) + goto async_error; + + ahcd->debug_periodic = debugfs_create_file("periodic", S_IRUGO, + ahcd->debug_dir, ahcd, + &debug_periodic_fops); + if (!ahcd->debug_periodic) + goto periodic_error; + + ahcd->debug_registers = debugfs_create_file("registers", S_IRUGO, + ahcd->debug_dir, ahcd, + &debug_registers_fops); + if (!ahcd->debug_registers) + goto registers_error; + + admhc_dbg(ahcd, "created debug files\n"); + return; + +registers_error: + debugfs_remove(ahcd->debug_periodic); +periodic_error: + debugfs_remove(ahcd->debug_async); +async_error: + debugfs_remove(ahcd->debug_dir); +dir_error: + ahcd->debug_periodic = NULL; + ahcd->debug_async = NULL; + ahcd->debug_dir = NULL; +} + +static inline void remove_debug_files(struct admhcd *ahcd) +{ + debugfs_remove(ahcd->debug_registers); + debugfs_remove(ahcd->debug_periodic); + debugfs_remove(ahcd->debug_async); + debugfs_remove(ahcd->debug_dir); +} + +#endif + +/*-------------------------------------------------------------------------*/ diff --git a/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-drv.c b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-drv.c new file mode 100644 index 0000000..798fd22 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-drv.c @@ -0,0 +1,228 @@ +/* + * ADM5120 HCD (Host Controller Driver) for USB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: drivers/usb/host/ohci-au1xxx.c + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * (C) Copyright 2002 Hewlett-Packard Company + * + * Written by Christopher Hoover + * Based on fragments of previous driver by Russell King et al. + * + * Modified for LH7A404 from ahcd-sa1111.c + * by Durgesh Pattamatta + * Modified for AMD Alchemy Au1xxx + * by Matt Porter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include + +#include +#include + +#ifdef DEBUG +#define HCD_DBG(f, a...) printk(KERN_DEBUG "%s: " f, hcd_name, ## a) +#else +#define HCD_DBG(f, a...) do {} while (0) +#endif +#define HCD_ERR(f, a...) printk(KERN_ERR "%s: " f, hcd_name, ## a) +#define HCD_INFO(f, a...) printk(KERN_INFO "%s: " f, hcd_name, ## a) + +/*-------------------------------------------------------------------------*/ + +static int admhc_adm5120_probe(const struct hc_driver *driver, + struct platform_device *dev) +{ + int retval; + struct usb_hcd *hcd; + int irq; + struct resource *regs; + + /* sanity checks */ + regs = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!regs) { + HCD_DBG("no IOMEM resource found\n"); + return -ENODEV; + } + + irq = platform_get_irq(dev, 0); + if (irq < 0) { + HCD_DBG("no IRQ resource found\n"); + return -ENODEV; + } + + hcd = usb_create_hcd(driver, &dev->dev, "ADM5120"); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = regs->start; + hcd->rsrc_len = regs->end - regs->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + HCD_DBG("request_mem_region failed\n"); + retval = -EBUSY; + goto err_dev; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + HCD_DBG("ioremap failed\n"); + retval = -ENOMEM; + goto err_mem; + } + + admhc_hcd_init(hcd_to_admhcd(hcd)); + + retval = usb_add_hcd(hcd, irq, 0); + if (retval) + goto err_io; + + return 0; + +err_io: + iounmap(hcd->regs); +err_mem: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err_dev: + usb_put_hcd(hcd); + return retval; +} + + +/* may be called without controller electrically present */ +/* may be called with controller, bus, and devices active */ + +static void admhc_adm5120_remove(struct usb_hcd *hcd, + struct platform_device *dev) +{ + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); +} + +static int admhc_adm5120_start(struct usb_hcd *hcd) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + int ret; + + ret = admhc_init(ahcd); + if (ret < 0) { + HCD_ERR("unable to init %s\n", hcd->self.bus_name); + goto err; + } + + ret = admhc_run(ahcd); + if (ret < 0) { + HCD_ERR("unable to run %s\n", hcd->self.bus_name); + goto err_stop; + } + + return 0; + +err_stop: + admhc_stop(hcd); +err: + return ret; +} + +static const struct hc_driver adm5120_hc_driver = { + .description = hcd_name, + .product_desc = "ADM5120 built-in USB 1.1 Host Controller", + .hcd_priv_size = sizeof(struct admhcd), + + /* + * generic hardware linkage + */ + .irq = admhc_irq, + .flags = HCD_USB11 | HCD_MEMORY, + + /* + * basic lifecycle operations + */ + .start = admhc_adm5120_start, + .stop = admhc_stop, + .shutdown = admhc_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = admhc_urb_enqueue, + .urb_dequeue = admhc_urb_dequeue, + .endpoint_disable = admhc_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = admhc_get_frame_number, + + /* + * root hub support + */ + .hub_status_data = admhc_hub_status_data, + .hub_control = admhc_hub_control, +#ifdef CONFIG_PM + .bus_suspend = admhc_bus_suspend, + .bus_resume = admhc_bus_resume, +#endif + .start_port_reset = admhc_start_port_reset, +}; + +static int usb_hcd_adm5120_probe(struct platform_device *pdev) +{ + int ret; + + ret = admhc_adm5120_probe(&adm5120_hc_driver, pdev); + + return ret; +} + +static int usb_hcd_adm5120_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + admhc_adm5120_remove(hcd, pdev); + + return 0; +} + +#ifdef CONFIG_PM +/* TODO */ +static int usb_hcd_adm5120_suspend(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + return 0; +} + +static int usb_hcd_adm5120_resume(struct platform_device *dev) +{ + struct usb_hcd *hcd = platform_get_drvdata(dev); + + return 0; +} +#else +#define usb_hcd_adm5120_suspend NULL +#define usb_hcd_adm5120_resume NULL +#endif /* CONFIG_PM */ + +static struct platform_driver usb_hcd_adm5120_driver = { + .probe = usb_hcd_adm5120_probe, + .remove = usb_hcd_adm5120_remove, + .shutdown = usb_hcd_platform_shutdown, + .suspend = usb_hcd_adm5120_suspend, + .resume = usb_hcd_adm5120_resume, + .driver = { + .name = "adm5120-hcd", + .owner = THIS_MODULE, + }, +}; + diff --git a/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-hcd.c b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-hcd.c new file mode 100644 index 0000000..f721ec1 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-hcd.c @@ -0,0 +1,843 @@ +/* + * ADM5120 HCD (Host Controller Driver) for USB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: drivers/usb/host/ohci-hcd.c + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2004 David Brownell + * + * [ Initialisation is based on Linus' ] + * [ uhci code and gregs ahcd fragments ] + * [ (C) Copyright 1999 Linus Torvalds ] + * [ (C) Copyright 1999 Gregory P. Smith] + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DRIVER_VERSION "0.27.0" +#define DRIVER_AUTHOR "Gabor Juhos " +#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver" + +/*-------------------------------------------------------------------------*/ + +#undef ADMHC_VERBOSE_DEBUG /* not always helpful */ + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR + +#define ADMHC_INTR_INIT \ + (ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \ + | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI) + +/*-------------------------------------------------------------------------*/ + +static const char hcd_name[] = "admhc-hcd"; + +#define STATECHANGE_DELAY msecs_to_jiffies(300) + +#include "adm5120.h" + +static void admhc_dump(struct admhcd *ahcd, int verbose); +static int admhc_init(struct admhcd *ahcd); +static void admhc_stop(struct usb_hcd *hcd); + +#include "adm5120-dbg.c" +#include "adm5120-mem.c" +#include "adm5120-pm.c" +#include "adm5120-hub.c" +#include "adm5120-q.c" + +/*-------------------------------------------------------------------------*/ + +/* + * queue up an urb for anything except the root hub + */ +static int admhc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, + gfp_t mem_flags) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + struct ed *ed; + struct urb_priv *urb_priv; + unsigned int pipe = urb->pipe; + int td_cnt = 0; + unsigned long flags; + int ret = 0; + +#ifdef ADMHC_VERBOSE_DEBUG + spin_lock_irqsave(&ahcd->lock, flags); + urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe), -EINPROGRESS); + spin_unlock_irqrestore(&ahcd->lock, flags); +#endif + + /* every endpoint has an ed, locate and maybe (re)initialize it */ + ed = ed_get(ahcd, urb->ep, urb->dev, pipe, urb->interval); + if (!ed) + return -ENOMEM; + + /* for the private part of the URB we need the number of TDs */ + switch (ed->type) { + case PIPE_CONTROL: + if (urb->transfer_buffer_length > TD_DATALEN_MAX) + /* td_submit_urb() doesn't yet handle these */ + return -EMSGSIZE; + + /* 1 TD for setup, 1 for ACK, plus ... */ + td_cnt = 2; + /* FALLTHROUGH */ + case PIPE_BULK: + /* one TD for every 4096 Bytes (can be up to 8K) */ + td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX; + /* ... and for any remaining bytes ... */ + if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0) + td_cnt++; + /* ... and maybe a zero length packet to wrap it up */ + if (td_cnt == 0) + td_cnt++; + else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 + && (urb->transfer_buffer_length + % usb_maxpacket(urb->dev, pipe, + usb_pipeout(pipe))) == 0) + td_cnt++; + break; + case PIPE_INTERRUPT: + /* + * for Interrupt IN/OUT transactions, each ED contains + * only 1 TD. + * TODO: check transfer_buffer_length? + */ + td_cnt = 1; + break; + case PIPE_ISOCHRONOUS: + /* number of packets from URB */ + td_cnt = urb->number_of_packets; + break; + } + + urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags); + if (!urb_priv) + return -ENOMEM; + + urb_priv->ed = ed; + + spin_lock_irqsave(&ahcd->lock, flags); + /* don't submit to a dead HC */ + if (!HCD_HW_ACCESSIBLE(hcd)) { + ret = -ENODEV; + goto fail; + } + if (!HC_IS_RUNNING(hcd->state)) { + ret = -ENODEV; + goto fail; + } + + ret = usb_hcd_link_urb_to_ep(hcd, urb); + if (ret) + goto fail; + + /* schedule the ed if needed */ + if (ed->state == ED_IDLE) { + ret = ed_schedule(ahcd, ed); + if (ret < 0) { + usb_hcd_unlink_urb_from_ep(hcd, urb); + goto fail; + } + if (ed->type == PIPE_ISOCHRONOUS) { + u16 frame = admhc_frame_no(ahcd); + + /* delay a few frames before the first TD */ + frame += max_t (u16, 8, ed->interval); + frame &= ~(ed->interval - 1); + frame |= ed->branch; + urb->start_frame = frame; + + /* yes, only URB_ISO_ASAP is supported, and + * urb->start_frame is never used as input. + */ + } + } else if (ed->type == PIPE_ISOCHRONOUS) + urb->start_frame = ed->last_iso + ed->interval; + + /* fill the TDs and link them to the ed; and + * enable that part of the schedule, if needed + * and update count of queued periodic urbs + */ + urb->hcpriv = urb_priv; + td_submit_urb(ahcd, urb); + +#ifdef ADMHC_VERBOSE_DEBUG + admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1); +#endif + +fail: + if (ret) + urb_priv_free(ahcd, urb_priv); + + spin_unlock_irqrestore(&ahcd->lock, flags); + return ret; +} + +/* + * decouple the URB from the HC queues (TDs, urb_priv); + * reporting is always done + * asynchronously, and we might be dealing with an urb that's + * partially transferred, or an ED with other urbs being unlinked. + */ +static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, + int status) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + unsigned long flags; + int ret; + + spin_lock_irqsave(&ahcd->lock, flags); + +#ifdef ADMHC_VERBOSE_DEBUG + urb_print(ahcd, urb, "DEQUEUE", 1, status); +#endif + ret = usb_hcd_check_unlink_urb(hcd, urb, status); + if (ret) { + /* Do nothing */ + ; + } else if (HC_IS_RUNNING(hcd->state)) { + struct urb_priv *urb_priv; + + /* Unless an IRQ completed the unlink while it was being + * handed to us, flag it for unlink and giveback, and force + * some upcoming INTR_SF to call finish_unlinks() + */ + urb_priv = urb->hcpriv; + if (urb_priv) { + if (urb_priv->ed->state == ED_OPER) + start_ed_unlink(ahcd, urb_priv->ed); + } + } else { + /* + * with HC dead, we won't respect hc queue pointers + * any more ... just clean up every urb's memory. + */ + if (urb->hcpriv) + finish_urb(ahcd, urb, status); + } + spin_unlock_irqrestore(&ahcd->lock, flags); + + return ret; +} + +/*-------------------------------------------------------------------------*/ + +/* frees config/altsetting state for endpoints, + * including ED memory, dummy TD, and bulk/intr data toggle + */ + +static void admhc_endpoint_disable(struct usb_hcd *hcd, + struct usb_host_endpoint *ep) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + unsigned long flags; + struct ed *ed = ep->hcpriv; + unsigned limit = 1000; + + /* ASSERT: any requests/urbs are being unlinked */ + /* ASSERT: nobody can be submitting urbs for this any more */ + + if (!ed) + return; + +#ifdef ADMHC_VERBOSE_DEBUG + spin_lock_irqsave(&ahcd->lock, flags); + admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1); + spin_unlock_irqrestore(&ahcd->lock, flags); +#endif + +rescan: + spin_lock_irqsave(&ahcd->lock, flags); + + if (!HC_IS_RUNNING(hcd->state)) { +sanitize: + ed->state = ED_IDLE; + finish_unlinks(ahcd, 0); + } + + switch (ed->state) { + case ED_UNLINK: /* wait for hw to finish? */ + /* major IRQ delivery trouble loses INTR_SOFI too... */ + if (limit-- == 0) { + admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n"); + goto sanitize; + } + spin_unlock_irqrestore(&ahcd->lock, flags); + schedule_timeout_uninterruptible(1); + goto rescan; + case ED_IDLE: /* fully unlinked */ + if (list_empty(&ed->td_list)) { + td_free(ahcd, ed->dummy); + ed_free(ahcd, ed); + break; + } + /* else FALL THROUGH */ + default: + /* caller was supposed to have unlinked any requests; + * that's not our job. can't recover; must leak ed. + */ + admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n", + ed, ep->desc.bEndpointAddress, ed->state, + list_empty(&ed->td_list) ? "" : " (has tds)"); + td_free(ahcd, ed->dummy); + break; + } + + ep->hcpriv = NULL; + + spin_unlock_irqrestore(&ahcd->lock, flags); +} + +static int admhc_get_frame_number(struct usb_hcd *hcd) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + + return admhc_frame_no(ahcd); +} + +static void admhc_usb_reset(struct admhcd *ahcd) +{ +#if 0 + ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control); + ahcd->hc_control &= OHCI_CTRL_RWC; + admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control); +#else + /* FIXME */ + ahcd->host_control = ADMHC_BUSS_RESET; + admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control); +#endif +} + +/* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and + * other cases where the next software may expect clean state from the + * "firmware". this is bus-neutral, unlike shutdown() methods. + */ +static void +admhc_shutdown(struct usb_hcd *hcd) +{ + struct admhcd *ahcd; + + ahcd = hcd_to_admhcd(hcd); + admhc_intr_disable(ahcd, ADMHC_INTR_MIE); + admhc_dma_disable(ahcd); + admhc_usb_reset(ahcd); + /* flush the writes */ + admhc_writel_flush(ahcd); +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +static void admhc_eds_cleanup(struct admhcd *ahcd) +{ + if (ahcd->ed_tails[PIPE_INTERRUPT]) { + ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]); + ahcd->ed_tails[PIPE_INTERRUPT] = NULL; + } + + if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) { + ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]); + ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL; + } + + if (ahcd->ed_tails[PIPE_CONTROL]) { + ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]); + ahcd->ed_tails[PIPE_CONTROL] = NULL; + } + + if (ahcd->ed_tails[PIPE_BULK]) { + ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]); + ahcd->ed_tails[PIPE_BULK] = NULL; + } + + ahcd->ed_head = NULL; +} + +#define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP) + +static int admhc_eds_init(struct admhcd *ahcd) +{ + struct ed *ed; + + ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO); + if (!ed) + goto err; + + ahcd->ed_tails[PIPE_INTERRUPT] = ed; + + ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO); + if (!ed) + goto err; + + ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed; + ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT]; + ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed; + ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma); + + ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO); + if (!ed) + goto err; + + ahcd->ed_tails[PIPE_CONTROL] = ed; + ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS]; + ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed; + ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma); + + ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO); + if (!ed) + goto err; + + ahcd->ed_tails[PIPE_BULK] = ed; + ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL]; + ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed; + ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma); + + ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT]; + +#ifdef ADMHC_VERBOSE_DEBUG + admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1); + admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1); + admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1); + admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1); +#endif + + return 0; + +err: + admhc_eds_cleanup(ahcd); + return -ENOMEM; +} + +/* init memory, and kick BIOS/SMM off */ + +static int admhc_init(struct admhcd *ahcd) +{ + struct usb_hcd *hcd = admhcd_to_hcd(ahcd); + int ret; + + admhc_disable(ahcd); + ahcd->regs = hcd->regs; + + /* Disable HC interrupts */ + admhc_intr_disable(ahcd, ADMHC_INTR_MIE); + + /* Read the number of ports unless overridden */ + if (ahcd->num_ports == 0) + ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP; + + ret = admhc_mem_init(ahcd); + if (ret) + goto err; + + /* init dummy endpoints */ + ret = admhc_eds_init(ahcd); + if (ret) + goto err; + + create_debug_files(ahcd); + + return 0; + +err: + admhc_stop(hcd); + return ret; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * resets USB and controller + * enable interrupts + */ +static int admhc_run(struct admhcd *ahcd) +{ + u32 val; + int first = ahcd->fminterval == 0; + struct usb_hcd *hcd = admhcd_to_hcd(ahcd); + + admhc_disable(ahcd); + + /* boot firmware should have set this up (5.1.1.3.1) */ + if (first) { + val = admhc_readl(ahcd, &ahcd->regs->fminterval); + ahcd->fminterval = val & ADMHC_SFI_FI_MASK; + if (ahcd->fminterval != FI) + admhc_dbg(ahcd, "fminterval delta %d\n", + ahcd->fminterval - FI); + ahcd->fminterval |= + (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT); + /* also: power/overcurrent flags in rhdesc */ + } + +#if 0 /* TODO: not applicable */ + /* Reset USB nearly "by the book". RemoteWakeupConnected has + * to be checked in case boot firmware (BIOS/SMM/...) has set up + * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). + * If the bus glue detected wakeup capability then it should + * already be enabled; if so we'll just enable it again. + */ + if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0) + device_set_wakeup_capable(hcd->self.controller, 1); +#endif + + switch (ahcd->host_control & ADMHC_HC_BUSS) { + case ADMHC_BUSS_OPER: + val = 0; + break; + case ADMHC_BUSS_SUSPEND: + /* FALLTHROUGH ? */ + case ADMHC_BUSS_RESUME: + ahcd->host_control = ADMHC_BUSS_RESUME; + val = 10 /* msec wait */; + break; + /* case ADMHC_BUSS_RESET: */ + default: + ahcd->host_control = ADMHC_BUSS_RESET; + val = 50 /* msec wait */; + break; + } + admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control); + + /* flush the writes */ + admhc_writel_flush(ahcd); + + msleep(val); + val = admhc_read_rhdesc(ahcd); + if (!(val & ADMHC_RH_NPS)) { + /* power down each port */ + for (val = 0; val < ahcd->num_ports; val++) + admhc_write_portstatus(ahcd, val, ADMHC_PS_CPP); + } + /* flush those writes */ + admhc_writel_flush(ahcd); + + /* 2msec timelimit here means no irqs/preempt */ + spin_lock_irq(&ahcd->lock); + + admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol); + val = 30; /* ... allow extra time */ + while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) { + if (--val == 0) { + spin_unlock_irq(&ahcd->lock); + admhc_err(ahcd, "USB HC reset timed out!\n"); + return -1; + } + udelay(1); + } + + /* enable HOST mode, before access any host specific register */ + admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol); + + /* Tell the controller where the descriptor list is */ + admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead); + + periodic_reinit(ahcd); + + /* use rhsc irqs after khubd is fully initialized */ + set_bit(HCD_FLAG_POLL_RH, &hcd->flags); + hcd->uses_new_polling = 1; + +#if 0 + /* wake on ConnectStatusChange, matching external hubs */ + admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status); +#else + /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */ +#endif + + /* Choose the interrupts we care about now, others later on demand */ + admhc_intr_ack(ahcd, ~0); + admhc_intr_enable(ahcd, ADMHC_INTR_INIT); + + admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc); + + /* flush those writes */ + admhc_writel_flush(ahcd); + + /* start controller operations */ + ahcd->host_control = ADMHC_BUSS_OPER; + admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control); + + val = 20; + while ((admhc_readl(ahcd, &ahcd->regs->host_control) + & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) { + if (--val == 0) { + spin_unlock_irq(&ahcd->lock); + admhc_err(ahcd, "unable to setup operational mode!\n"); + return -1; + } + mdelay(1); + } + + hcd->state = HC_STATE_RUNNING; + + ahcd->next_statechange = jiffies + STATECHANGE_DELAY; + +#if 0 + /* FIXME: enabling DMA is always failed here for an unknown reason */ + admhc_dma_enable(ahcd); + + val = 200; + while ((admhc_readl(ahcd, &ahcd->regs->host_control) + & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) { + if (--val == 0) { + spin_unlock_irq(&ahcd->lock); + admhc_err(ahcd, "unable to enable DMA!\n"); + admhc_dump(ahcd, 1); + return -1; + } + mdelay(1); + } + +#endif + + spin_unlock_irq(&ahcd->lock); + + mdelay(ADMHC_POTPGT); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static irqreturn_t admhc_irq(struct usb_hcd *hcd) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + struct admhcd_regs __iomem *regs = ahcd->regs; + u32 ints; + + ints = admhc_readl(ahcd, ®s->int_status); + if ((ints & ADMHC_INTR_INTA) == 0) { + /* no unmasked interrupt status is set */ + return IRQ_NONE; + } + + ints &= admhc_readl(ahcd, ®s->int_enable); + + if (ints & ADMHC_INTR_FATI) { + /* e.g. due to PCI Master/Target Abort */ + admhc_disable(ahcd); + admhc_err(ahcd, "Fatal Error, controller disabled\n"); + admhc_dump(ahcd, 1); + admhc_usb_reset(ahcd); + } + + if (ints & ADMHC_INTR_BABI) { + admhc_intr_disable(ahcd, ADMHC_INTR_BABI); + admhc_intr_ack(ahcd, ADMHC_INTR_BABI); + admhc_err(ahcd, "Babble Detected\n"); + } + + if (ints & ADMHC_INTR_INSM) { + admhc_vdbg(ahcd, "Root Hub Status Change\n"); + ahcd->next_statechange = jiffies + STATECHANGE_DELAY; + admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM); + + /* NOTE: Vendors didn't always make the same implementation + * choices for RHSC. Many followed the spec; RHSC triggers + * on an edge, like setting and maybe clearing a port status + * change bit. With others it's level-triggered, active + * until khubd clears all the port status change bits. We'll + * always disable it here and rely on polling until khubd + * re-enables it. + */ + admhc_intr_disable(ahcd, ADMHC_INTR_INSM); + usb_hcd_poll_rh_status(hcd); + } else if (ints & ADMHC_INTR_RESI) { + /* For connect and disconnect events, we expect the controller + * to turn on RHSC along with RD. But for remote wakeup events + * this might not happen. + */ + admhc_vdbg(ahcd, "Resume Detect\n"); + admhc_intr_ack(ahcd, ADMHC_INTR_RESI); + set_bit(HCD_FLAG_POLL_RH, &hcd->flags); + if (ahcd->autostop) { + spin_lock(&ahcd->lock); + admhc_rh_resume(ahcd); + spin_unlock(&ahcd->lock); + } else + usb_hcd_resume_root_hub(hcd); + } + + if (ints & ADMHC_INTR_TDC) { + admhc_vdbg(ahcd, "Transfer Descriptor Complete\n"); + admhc_intr_ack(ahcd, ADMHC_INTR_TDC); + if (HC_IS_RUNNING(hcd->state)) + admhc_intr_disable(ahcd, ADMHC_INTR_TDC); + spin_lock(&ahcd->lock); + admhc_td_complete(ahcd); + spin_unlock(&ahcd->lock); + if (HC_IS_RUNNING(hcd->state)) + admhc_intr_enable(ahcd, ADMHC_INTR_TDC); + } + + if (ints & ADMHC_INTR_SO) { + /* could track INTR_SO to reduce available PCI/... bandwidth */ + admhc_vdbg(ahcd, "Schedule Overrun\n"); + } + +#if 1 + spin_lock(&ahcd->lock); + if (ahcd->ed_rm_list) + finish_unlinks(ahcd, admhc_frame_no(ahcd)); + + if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list + && HC_IS_RUNNING(hcd->state)) + admhc_intr_disable(ahcd, ADMHC_INTR_SOFI); + spin_unlock(&ahcd->lock); +#else + if (ints & ADMHC_INTR_SOFI) { + admhc_vdbg(ahcd, "Start Of Frame\n"); + spin_lock(&ahcd->lock); + + /* handle any pending ED removes */ + finish_unlinks(ahcd, admhc_frameno(ahcd)); + + /* leaving INTR_SOFI enabled when there's still unlinking + * to be done in the (next frame). + */ + if ((ahcd->ed_rm_list == NULL) || + HC_IS_RUNNING(hcd->state) == 0) + /* + * disable INTR_SOFI if there are no unlinking to be + * done (in the next frame) + */ + admhc_intr_disable(ahcd, ADMHC_INTR_SOFI); + + spin_unlock(&ahcd->lock); + } +#endif + + if (HC_IS_RUNNING(hcd->state)) { + admhc_intr_ack(ahcd, ints); + admhc_intr_enable(ahcd, ADMHC_INTR_MIE); + admhc_writel_flush(ahcd); + } + + return IRQ_HANDLED; +} + +/*-------------------------------------------------------------------------*/ + +static void admhc_stop(struct usb_hcd *hcd) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + + admhc_dump(ahcd, 1); + + flush_scheduled_work(); + + admhc_usb_reset(ahcd); + admhc_intr_disable(ahcd, ADMHC_INTR_MIE); + + free_irq(hcd->irq, hcd); + hcd->irq = -1; + + remove_debug_files(ahcd); + admhc_eds_cleanup(ahcd); + admhc_mem_cleanup(ahcd); +} + +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_ADM5120 +#include "adm5120-drv.c" +#define PLATFORM_DRIVER usb_hcd_adm5120_driver +#endif + +#if !defined(PLATFORM_DRIVER) +#error "missing bus glue for admhc-hcd" +#endif + +#define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION + +static int __init admhc_hcd_mod_init(void) +{ + int ret = 0; + + if (usb_disabled()) + return -ENODEV; + + pr_info("%s: " DRIVER_INFO "\n", hcd_name); + pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name, + sizeof(struct ed), sizeof(struct td)); + set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); + +#ifdef DEBUG + admhc_debug_root = debugfs_create_dir("admhc", usb_debug_root); + if (!admhc_debug_root) { + ret = -ENOENT; + goto error_debug; + } +#endif + +#ifdef PLATFORM_DRIVER + ret = platform_driver_register(&PLATFORM_DRIVER); + if (ret < 0) + goto error_platform; +#endif + + return ret; + +#ifdef PLATFORM_DRIVER + platform_driver_unregister(&PLATFORM_DRIVER); +error_platform: +#endif + +#ifdef DEBUG + debugfs_remove(admhc_debug_root); + admhc_debug_root = NULL; +error_debug: +#endif + clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); + return ret; +} +module_init(admhc_hcd_mod_init); + +static void __exit admhc_hcd_mod_exit(void) +{ + platform_driver_unregister(&PLATFORM_DRIVER); +#ifdef DEBUG + debugfs_remove(admhc_debug_root); +#endif + clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); +} +module_exit(admhc_hcd_mod_exit); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_INFO); +MODULE_VERSION(DRIVER_VERSION); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-hub.c b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-hub.c new file mode 100644 index 0000000..8cabaf9 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-hub.c @@ -0,0 +1,430 @@ +/* + * ADM5120 HCD (Host Controller Driver) for USB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: drivers/usb/host/ohci-hub.c + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2004 David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +/*-------------------------------------------------------------------------*/ + +/* + * ADM5120 Root Hub ... the nonsharable stuff + */ + +#define dbg_port(hc, label, num, value) \ + admhc_dbg(hc, \ + "%s port%d " \ + "= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \ + label, num, value, \ + (value & ADMHC_PS_PRSC) ? " PRSC" : "", \ + (value & ADMHC_PS_OCIC) ? " OCIC" : "", \ + (value & ADMHC_PS_PSSC) ? " PSSC" : "", \ + (value & ADMHC_PS_PESC) ? " PESC" : "", \ + (value & ADMHC_PS_CSC) ? " CSC" : "", \ + \ + (value & ADMHC_PS_LSDA) ? " LSDA" : "", \ + (value & ADMHC_PS_PPS) ? " PPS" : "", \ + (value & ADMHC_PS_PRS) ? " PRS" : "", \ + (value & ADMHC_PS_POCI) ? " POCI" : "", \ + (value & ADMHC_PS_PSS) ? " PSS" : "", \ + \ + (value & ADMHC_PS_PES) ? " PES" : "", \ + (value & ADMHC_PS_CCS) ? " CCS" : "" \ + ); + +#define dbg_port_write(hc, label, num, value) \ + admhc_dbg(hc, \ + "%s port%d " \ + "= 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \ + label, num, value, \ + (value & ADMHC_PS_PRSC) ? " PRSC" : "", \ + (value & ADMHC_PS_OCIC) ? " OCIC" : "", \ + (value & ADMHC_PS_PSSC) ? " PSSC" : "", \ + (value & ADMHC_PS_PESC) ? " PESC" : "", \ + (value & ADMHC_PS_CSC) ? " CSC" : "", \ + \ + (value & ADMHC_PS_CPP) ? " CPP" : "", \ + (value & ADMHC_PS_SPP) ? " SPP" : "", \ + (value & ADMHC_PS_SPR) ? " SPR" : "", \ + (value & ADMHC_PS_CPS) ? " CPS" : "", \ + (value & ADMHC_PS_SPS) ? " SPS" : "", \ + \ + (value & ADMHC_PS_SPE) ? " SPE" : "", \ + (value & ADMHC_PS_CPE) ? " CPE" : "" \ + ); + +/*-------------------------------------------------------------------------*/ + +/* build "status change" packet (one or two bytes) from HC registers */ + +static int +admhc_hub_status_data(struct usb_hcd *hcd, char *buf) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + int i, changed = 0, length = 1; + int any_connected = 0; + unsigned long flags; + u32 status; + + spin_lock_irqsave(&ahcd->lock, flags); + if (!HCD_HW_ACCESSIBLE(hcd)) + goto done; + + /* init status */ + status = admhc_read_rhdesc(ahcd); + if (status & (ADMHC_RH_LPSC | ADMHC_RH_OCIC)) + buf[0] = changed = 1; + else + buf[0] = 0; + if (ahcd->num_ports > 7) { + buf[1] = 0; + length++; + } + + /* look at each port */ + for (i = 0; i < ahcd->num_ports; i++) { + status = admhc_read_portstatus(ahcd, i); + + /* can't autostop if ports are connected */ + any_connected |= (status & ADMHC_PS_CCS); + + if (status & (ADMHC_PS_CSC | ADMHC_PS_PESC | ADMHC_PS_PSSC + | ADMHC_PS_OCIC | ADMHC_PS_PRSC)) { + changed = 1; + if (i < 7) + buf[0] |= 1 << (i + 1); + else + buf[1] |= 1 << (i - 7); + } + } + + if (admhc_root_hub_state_changes(ahcd, changed, + any_connected)) + set_bit(HCD_FLAG_POLL_RH, &hcd->flags); + else + clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); + +done: + spin_unlock_irqrestore(&ahcd->lock, flags); + + return changed ? length : 0; +} + +/*-------------------------------------------------------------------------*/ + +static int admhc_get_hub_descriptor(struct admhcd *ahcd, char *buf) +{ + struct usb_hub_descriptor *desc = (struct usb_hub_descriptor *)buf; + u32 rh = admhc_read_rhdesc(ahcd); + u16 temp; + + desc->bDescriptorType = USB_DT_HUB; /* Hub-descriptor */ + desc->bPwrOn2PwrGood = ADMHC_POTPGT/2; /* use default value */ + desc->bHubContrCurrent = 0x00; /* 0mA */ + + desc->bNbrPorts = ahcd->num_ports; + temp = 1 + (ahcd->num_ports / 8); + desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; + + /* FIXME */ + temp = 0; + if (rh & ADMHC_RH_NPS) /* no power switching? */ + temp |= 0x0002; + if (rh & ADMHC_RH_PSM) /* per-port power switching? */ + temp |= 0x0001; + if (rh & ADMHC_RH_NOCP) /* no overcurrent reporting? */ + temp |= 0x0010; + else if (rh & ADMHC_RH_OCPM) /* per-port overcurrent reporting? */ + temp |= 0x0008; + desc->wHubCharacteristics = (__force __u16)cpu_to_hc16(ahcd, temp); + + /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ + desc->u.hs.DeviceRemovable[0] = 0; + desc->u.hs.DeviceRemovable[0] = ~0; + + return 0; +} + +static int admhc_get_hub_status(struct admhcd *ahcd, char *buf) +{ + struct usb_hub_status *hs = (struct usb_hub_status *)buf; + u32 t = admhc_read_rhdesc(ahcd); + u16 status, change; + + status = 0; + status |= (t & ADMHC_RH_LPS) ? HUB_STATUS_LOCAL_POWER : 0; + status |= (t & ADMHC_RH_OCI) ? HUB_STATUS_OVERCURRENT : 0; + + change = 0; + change |= (t & ADMHC_RH_LPSC) ? HUB_CHANGE_LOCAL_POWER : 0; + change |= (t & ADMHC_RH_OCIC) ? HUB_CHANGE_OVERCURRENT : 0; + + hs->wHubStatus = (__force __u16)cpu_to_hc16(ahcd, status); + hs->wHubChange = (__force __u16)cpu_to_hc16(ahcd, change); + + return 0; +} + +static int admhc_get_port_status(struct admhcd *ahcd, unsigned port, char *buf) +{ + struct usb_port_status *ps = (struct usb_port_status *)buf; + u32 t = admhc_read_portstatus(ahcd, port); + u16 status, change; + + status = 0; + status |= (t & ADMHC_PS_CCS) ? USB_PORT_STAT_CONNECTION : 0; + status |= (t & ADMHC_PS_PES) ? USB_PORT_STAT_ENABLE : 0; + status |= (t & ADMHC_PS_PSS) ? USB_PORT_STAT_SUSPEND : 0; + status |= (t & ADMHC_PS_POCI) ? USB_PORT_STAT_OVERCURRENT : 0; + status |= (t & ADMHC_PS_PRS) ? USB_PORT_STAT_RESET : 0; + status |= (t & ADMHC_PS_PPS) ? USB_PORT_STAT_POWER : 0; + status |= (t & ADMHC_PS_LSDA) ? USB_PORT_STAT_LOW_SPEED : 0; + + change = 0; + change |= (t & ADMHC_PS_CSC) ? USB_PORT_STAT_C_CONNECTION : 0; + change |= (t & ADMHC_PS_PESC) ? USB_PORT_STAT_C_ENABLE : 0; + change |= (t & ADMHC_PS_PSSC) ? USB_PORT_STAT_C_SUSPEND : 0; + change |= (t & ADMHC_PS_OCIC) ? USB_PORT_STAT_C_OVERCURRENT : 0; + change |= (t & ADMHC_PS_PRSC) ? USB_PORT_STAT_C_RESET : 0; + + ps->wPortStatus = (__force __u16)cpu_to_hc16(ahcd, status); + ps->wPortChange = (__force __u16)cpu_to_hc16(ahcd, change); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef CONFIG_USB_OTG + +static int admhc_start_port_reset(struct usb_hcd *hcd, unsigned port) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + u32 status; + + if (!port) + return -EINVAL; + port--; + + /* start port reset before HNP protocol times out */ + status = admhc_read_portstatus(ahcd, port); + if (!(status & ADMHC_PS_CCS)) + return -ENODEV; + + /* khubd will finish the reset later */ + admhc_write_portstatus(ahcd, port, ADMHC_PS_PRS); + return 0; +} + +static void start_hnp(struct admhcd *ahcd); + +#else + +#define admhc_start_port_reset NULL + +#endif + +/*-------------------------------------------------------------------------*/ + + +/* See usb 7.1.7.5: root hubs must issue at least 50 msec reset signaling, + * not necessarily continuous ... to guard against resume signaling. + * The short timeout is safe for non-root hubs, and is backward-compatible + * with earlier Linux hosts. + */ +#ifdef CONFIG_USB_SUSPEND +#define PORT_RESET_MSEC 50 +#else +#define PORT_RESET_MSEC 10 +#endif + +/* this timer value might be vendor-specific ... */ +#define PORT_RESET_HW_MSEC 10 + +/* wrap-aware logic morphed from */ +#define tick_before(t1, t2) ((s16)(((s16)(t1)) - ((s16)(t2))) < 0) + +/* called from some task, normally khubd */ +static inline int admhc_port_reset(struct admhcd *ahcd, unsigned port) +{ + u32 t; + + admhc_vdbg(ahcd, "reset port%d\n", port); + t = admhc_read_portstatus(ahcd, port); + if (!(t & ADMHC_PS_CCS)) + return -ENODEV; + + admhc_write_portstatus(ahcd, port, ADMHC_PS_SPR); + mdelay(10); + admhc_write_portstatus(ahcd, port, (ADMHC_PS_SPE | ADMHC_PS_CSC)); + mdelay(100); + + return 0; +} + +static inline int admhc_port_enable(struct admhcd *ahcd, unsigned port) +{ + u32 t; + + admhc_vdbg(ahcd, "enable port%d\n", port); + t = admhc_read_portstatus(ahcd, port); + if (!(t & ADMHC_PS_CCS)) + return -ENODEV; + + admhc_write_portstatus(ahcd, port, ADMHC_PS_SPE); + + return 0; +} + +static inline int admhc_port_disable(struct admhcd *ahcd, unsigned port) +{ + u32 t; + + admhc_vdbg(ahcd, "disable port%d\n", port); + t = admhc_read_portstatus(ahcd, port); + if (!(t & ADMHC_PS_CCS)) + return -ENODEV; + + admhc_write_portstatus(ahcd, port, ADMHC_PS_CPE); + + return 0; +} + +static inline int admhc_port_write(struct admhcd *ahcd, unsigned port, + u32 val) +{ +#ifdef ADMHC_VERBOSE_DEBUG + dbg_port_write(ahcd, "write", port, val); +#endif + admhc_write_portstatus(ahcd, port, val); + + return 0; +} + +static int admhc_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, + u16 wIndex, char *buf, u16 wLength) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + int ports = ahcd->num_ports; + int ret = 0; + + if (unlikely(!HCD_HW_ACCESSIBLE(hcd))) + return -ESHUTDOWN; + + switch (typeReq) { + case ClearHubFeature: + switch (wValue) { + case C_HUB_OVER_CURRENT: +#if 0 /* FIXME */ + admhc_writel(ahcd, ADMHC_RH_OCIC, + &ahcd->regs->roothub.status); +#endif + case C_HUB_LOCAL_POWER: + break; + default: + goto error; + } + break; + case ClearPortFeature: + if (!wIndex || wIndex > ports) + goto error; + wIndex--; + + switch (wValue) { + case USB_PORT_FEAT_ENABLE: + ret = admhc_port_disable(ahcd, wIndex); + break; + case USB_PORT_FEAT_SUSPEND: + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPS); + break; + case USB_PORT_FEAT_POWER: + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CPP); + break; + case USB_PORT_FEAT_C_CONNECTION: + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_CSC); + break; + case USB_PORT_FEAT_C_ENABLE: + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PESC); + break; + case USB_PORT_FEAT_C_SUSPEND: + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PSSC); + break; + case USB_PORT_FEAT_C_OVER_CURRENT: + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_OCIC); + break; + case USB_PORT_FEAT_C_RESET: + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_PRSC); + break; + default: + goto error; + } + break; + case GetHubDescriptor: + ret = admhc_get_hub_descriptor(ahcd, buf); + break; + case GetHubStatus: + ret = admhc_get_hub_status(ahcd, buf); + break; + case GetPortStatus: + if (!wIndex || wIndex > ports) + goto error; + wIndex--; + + ret = admhc_get_port_status(ahcd, wIndex, buf); + break; + case SetHubFeature: + switch (wValue) { + case C_HUB_OVER_CURRENT: + /* FIXME: this can be cleared, yes? */ + case C_HUB_LOCAL_POWER: + break; + default: + goto error; + } + break; + case SetPortFeature: + if (!wIndex || wIndex > ports) + goto error; + wIndex--; + + switch (wValue) { + case USB_PORT_FEAT_ENABLE: + ret = admhc_port_enable(ahcd, wIndex); + break; + case USB_PORT_FEAT_RESET: + ret = admhc_port_reset(ahcd, wIndex); + break; + case USB_PORT_FEAT_SUSPEND: +#ifdef CONFIG_USB_OTG + if (hcd->self.otg_port == (wIndex + 1) + && hcd->self.b_hnp_enable) + start_hnp(ahcd); + else +#endif + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPS); + break; + case USB_PORT_FEAT_POWER: + ret = admhc_port_write(ahcd, wIndex, ADMHC_PS_SPP); + break; + default: + goto error; + } + break; + + default: +error: + /* "protocol stall" on error */ + ret = -EPIPE; + } + + return ret; +} + diff --git a/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-mem.c b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-mem.c new file mode 100644 index 0000000..79fff70 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-mem.c @@ -0,0 +1,202 @@ +/* + * ADM5120 HCD (Host Controller Driver) for USB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: drivers/usb/host/ohci-mem.c + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +/*-------------------------------------------------------------------------*/ + +/* + * OHCI deals with three types of memory: + * - data used only by the HCD ... kmalloc is fine + * - async and periodic schedules, shared by HC and HCD ... these + * need to use dma_pool or dma_alloc_coherent + * - driver buffers, read/written by HC ... the hcd glue or the + * device driver provides us with dma addresses + * + * There's also "register" data, which is memory mapped. + * No memory seen by this driver (or any HCD) may be paged out. + */ + +/*-------------------------------------------------------------------------*/ + +static void admhc_hcd_init(struct admhcd *ahcd) +{ + ahcd->next_statechange = jiffies; + spin_lock_init(&ahcd->lock); + INIT_LIST_HEAD(&ahcd->pending); +} + +/*-------------------------------------------------------------------------*/ + +static int admhc_mem_init(struct admhcd *ahcd) +{ + ahcd->td_cache = dma_pool_create("admhc_td", + admhcd_to_hcd(ahcd)->self.controller, + sizeof(struct td), + TD_ALIGN, /* byte alignment */ + 0 /* no page-crossing issues */ + ); + if (!ahcd->td_cache) + goto err; + + ahcd->ed_cache = dma_pool_create("admhc_ed", + admhcd_to_hcd(ahcd)->self.controller, + sizeof(struct ed), + ED_ALIGN, /* byte alignment */ + 0 /* no page-crossing issues */ + ); + if (!ahcd->ed_cache) + goto err_td_cache; + + return 0; + +err_td_cache: + dma_pool_destroy(ahcd->td_cache); + ahcd->td_cache = NULL; +err: + return -ENOMEM; +} + +static void admhc_mem_cleanup(struct admhcd *ahcd) +{ + if (ahcd->td_cache) { + dma_pool_destroy(ahcd->td_cache); + ahcd->td_cache = NULL; + } + + if (ahcd->ed_cache) { + dma_pool_destroy(ahcd->ed_cache); + ahcd->ed_cache = NULL; + } +} + +/*-------------------------------------------------------------------------*/ + +/* ahcd "done list" processing needs this mapping */ +static inline struct td *dma_to_td(struct admhcd *ahcd, dma_addr_t td_dma) +{ + struct td *td; + + td_dma &= TD_MASK; + td = ahcd->td_hash[TD_HASH_FUNC(td_dma)]; + while (td && td->td_dma != td_dma) + td = td->td_hash; + + return td; +} + +/* TDs ... */ +static struct td *td_alloc(struct admhcd *ahcd, gfp_t mem_flags) +{ + dma_addr_t dma; + struct td *td; + + td = dma_pool_alloc(ahcd->td_cache, mem_flags, &dma); + if (!td) + return NULL; + + /* in case ahcd fetches it, make it look dead */ + memset(td, 0, sizeof *td); + td->hwNextTD = cpu_to_hc32(ahcd, dma); + td->td_dma = dma; + /* hashed in td_fill */ + + return td; +} + +static void td_free(struct admhcd *ahcd, struct td *td) +{ + struct td **prev = &ahcd->td_hash[TD_HASH_FUNC(td->td_dma)]; + + while (*prev && *prev != td) + prev = &(*prev)->td_hash; + if (*prev) + *prev = td->td_hash; +#if 0 + /* TODO: remove */ + else if ((td->hwINFO & cpu_to_hc32(ahcd, TD_DONE)) != 0) + admhc_dbg(ahcd, "no hash for td %p\n", td); +#else + else if ((td->flags & TD_FLAG_DONE) != 0) + admhc_dbg(ahcd, "no hash for td %p\n", td); +#endif + dma_pool_free(ahcd->td_cache, td, td->td_dma); +} + +/*-------------------------------------------------------------------------*/ + +/* EDs ... */ +static struct ed *ed_alloc(struct admhcd *ahcd, gfp_t mem_flags) +{ + dma_addr_t dma; + struct ed *ed; + + ed = dma_pool_alloc(ahcd->ed_cache, mem_flags, &dma); + if (!ed) + return NULL; + + memset(ed, 0, sizeof(*ed)); + ed->dma = dma; + + INIT_LIST_HEAD(&ed->td_list); + INIT_LIST_HEAD(&ed->urb_list); + + return ed; +} + +static void ed_free(struct admhcd *ahcd, struct ed *ed) +{ + dma_pool_free(ahcd->ed_cache, ed, ed->dma); +} + +/*-------------------------------------------------------------------------*/ + +/* URB priv ... */ +static void urb_priv_free(struct admhcd *ahcd, struct urb_priv *urb_priv) +{ + int i; + + for (i = 0; i < urb_priv->td_cnt; i++) + if (urb_priv->td[i]) + td_free(ahcd, urb_priv->td[i]); + + list_del(&urb_priv->pending); + kfree(urb_priv); +} + +static struct urb_priv *urb_priv_alloc(struct admhcd *ahcd, int num_tds, + gfp_t mem_flags) +{ + struct urb_priv *priv; + + /* allocate the private part of the URB */ + priv = kzalloc(sizeof(*priv) + sizeof(struct td) * num_tds, mem_flags); + if (!priv) + goto err; + + /* allocate the TDs (deferring hash chain updates) */ + for (priv->td_cnt = 0; priv->td_cnt < num_tds; priv->td_cnt++) { + priv->td[priv->td_cnt] = td_alloc(ahcd, mem_flags); + if (priv->td[priv->td_cnt] == NULL) + goto err_free; + } + + INIT_LIST_HEAD(&priv->pending); + + return priv; + +err_free: + urb_priv_free(ahcd, priv); +err: + return NULL; +} diff --git a/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-pm.c b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-pm.c new file mode 100644 index 0000000..7d7fc24 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-pm.c @@ -0,0 +1,449 @@ +/* + * ADM5120 HCD (Host Controller Driver) for USB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from fragments of the OHCI driver. + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2004 David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#define OHCI_SCHED_ENABLES \ + (OHCI_CTRL_CLE|OHCI_CTRL_BLE|OHCI_CTRL_PLE|OHCI_CTRL_IE) + +#ifdef CONFIG_PM +static int admhc_restart(struct admhcd *ahcd); + +static int admhc_rh_suspend(struct admhcd *ahcd, int autostop) +__releases(ahcd->lock) +__acquires(ahcd->lock) +{ + int status = 0; + + ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control); + switch (ahcd->hc_control & OHCI_CTRL_HCFS) { + case OHCI_USB_RESUME: + admhc_dbg(ahcd, "resume/suspend?\n"); + ahcd->hc_control &= ~OHCI_CTRL_HCFS; + ahcd->hc_control |= OHCI_USB_RESET; + admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control); + (void) admhc_readl(ahcd, &ahcd->regs->control); + /* FALL THROUGH */ + case OHCI_USB_RESET: + status = -EBUSY; + admhc_dbg(ahcd, "needs reinit!\n"); + goto done; + case OHCI_USB_SUSPEND: + if (!ahcd->autostop) { + admhc_dbg(ahcd, "already suspended\n"); + goto done; + } + } + admhc_dbg(ahcd, "%s root hub\n", + autostop ? "auto-stop" : "suspend"); + + /* First stop any processing */ + if (!autostop && (ahcd->hc_control & OHCI_SCHED_ENABLES)) { + ahcd->hc_control &= ~OHCI_SCHED_ENABLES; + admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control); + ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control); + admhc_writel(ahcd, OHCI_INTR_SF, &ahcd->regs->intrstatus); + + /* sched disables take effect on the next frame, + * then the last WDH could take 6+ msec + */ + admhc_dbg(ahcd, "stopping schedules ...\n"); + ahcd->autostop = 0; + spin_unlock_irq (&ahcd->lock); + msleep (8); + spin_lock_irq(&ahcd->lock); + } + dl_done_list (ahcd); + finish_unlinks (ahcd, admhc_frame_no(ahcd)); + + /* maybe resume can wake root hub */ + if (device_may_wakeup(&admhcd_to_hcd(ahcd)->self.root_hub->dev) || + autostop) + ahcd->hc_control |= OHCI_CTRL_RWE; + else { + admhc_writel(ahcd, OHCI_INTR_RHSC, &ahcd->regs->intrdisable); + ahcd->hc_control &= ~OHCI_CTRL_RWE; + } + + /* Suspend hub ... this is the "global (to this bus) suspend" mode, + * which doesn't imply ports will first be individually suspended. + */ + ahcd->hc_control &= ~OHCI_CTRL_HCFS; + ahcd->hc_control |= OHCI_USB_SUSPEND; + admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control); + (void) admhc_readl(ahcd, &ahcd->regs->control); + + /* no resumes until devices finish suspending */ + if (!autostop) { + ahcd->next_statechange = jiffies + msecs_to_jiffies (5); + ahcd->autostop = 0; + } + +done: + return status; +} + +static inline struct ed *find_head(struct ed *ed) +{ + /* for bulk and control lists */ + while (ed->ed_prev) + ed = ed->ed_prev; + return ed; +} + +/* caller has locked the root hub */ +static int admhc_rh_resume(struct admhcd *ahcd) +__releases(ahcd->lock) +__acquires(ahcd->lock) +{ + struct usb_hcd *hcd = admhcd_to_hcd (ahcd); + u32 temp, enables; + int status = -EINPROGRESS; + int autostopped = ahcd->autostop; + + ahcd->autostop = 0; + ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control); + + if (ahcd->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) { + /* this can happen after resuming a swsusp snapshot */ + if (hcd->state == HC_STATE_RESUMING) { + admhc_dbg(ahcd, "BIOS/SMM active, control %03x\n", + ahcd->hc_control); + status = -EBUSY; + /* this happens when pmcore resumes HC then root */ + } else { + admhc_dbg(ahcd, "duplicate resume\n"); + status = 0; + } + } else switch (ahcd->hc_control & OHCI_CTRL_HCFS) { + case OHCI_USB_SUSPEND: + ahcd->hc_control &= ~(OHCI_CTRL_HCFS|OHCI_SCHED_ENABLES); + ahcd->hc_control |= OHCI_USB_RESUME; + admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control); + (void) admhc_readl(ahcd, &ahcd->regs->control); + admhc_dbg(ahcd, "%s root hub\n", + autostopped ? "auto-start" : "resume"); + break; + case OHCI_USB_RESUME: + /* HCFS changes sometime after INTR_RD */ + admhc_dbg(ahcd, "%swakeup root hub\n", + autostopped ? "auto-" : ""); + break; + case OHCI_USB_OPER: + /* this can happen after resuming a swsusp snapshot */ + admhc_dbg(ahcd, "snapshot resume? reinit\n"); + status = -EBUSY; + break; + default: /* RESET, we lost power */ + admhc_dbg(ahcd, "lost power\n"); + status = -EBUSY; + } + if (status == -EBUSY) { + if (!autostopped) { + spin_unlock_irq (&ahcd->lock); + (void) ahcd_init (ahcd); + status = admhc_restart (ahcd); + spin_lock_irq(&ahcd->lock); + } + return status; + } + if (status != -EINPROGRESS) + return status; + if (autostopped) + goto skip_resume; + spin_unlock_irq (&ahcd->lock); + + /* Some controllers (lucent erratum) need extra-long delays */ + msleep (20 /* usb 11.5.1.10 */ + 12 /* 32 msec counter */ + 1); + + temp = admhc_readl(ahcd, &ahcd->regs->control); + temp &= OHCI_CTRL_HCFS; + if (temp != OHCI_USB_RESUME) { + admhc_err (ahcd, "controller won't resume\n"); + spin_lock_irq(&ahcd->lock); + return -EBUSY; + } + + /* disable old schedule state, reinit from scratch */ + admhc_writel(ahcd, 0, &ahcd->regs->ed_controlhead); + admhc_writel(ahcd, 0, &ahcd->regs->ed_controlcurrent); + admhc_writel(ahcd, 0, &ahcd->regs->ed_bulkhead); + admhc_writel(ahcd, 0, &ahcd->regs->ed_bulkcurrent); + admhc_writel(ahcd, 0, &ahcd->regs->ed_periodcurrent); + admhc_writel(ahcd, (u32) ahcd->hcca_dma, &ahcd->ahcd->regs->hcca); + + /* Sometimes PCI D3 suspend trashes frame timings ... */ + periodic_reinit(ahcd); + + /* the following code is executed with ahcd->lock held and + * irqs disabled if and only if autostopped is true + */ + +skip_resume: + /* interrupts might have been disabled */ + admhc_writel(ahcd, OHCI_INTR_INIT, &ahcd->regs->int_enable); + if (ahcd->ed_rm_list) + admhc_writel(ahcd, OHCI_INTR_SF, &ahcd->regs->int_enable); + + /* Then re-enable operations */ + admhc_writel(ahcd, OHCI_USB_OPER, &ahcd->regs->control); + (void) admhc_readl(ahcd, &ahcd->regs->control); + if (!autostopped) + msleep (3); + + temp = ahcd->hc_control; + temp &= OHCI_CTRL_RWC; + temp |= OHCI_CONTROL_INIT | OHCI_USB_OPER; + ahcd->hc_control = temp; + admhc_writel(ahcd, temp, &ahcd->regs->control); + (void) admhc_readl(ahcd, &ahcd->regs->control); + + /* TRSMRCY */ + if (!autostopped) { + msleep (10); + spin_lock_irq(&ahcd->lock); + } + /* now ahcd->lock is always held and irqs are always disabled */ + + /* keep it alive for more than ~5x suspend + resume costs */ + ahcd->next_statechange = jiffies + STATECHANGE_DELAY; + + /* maybe turn schedules back on */ + enables = 0; + temp = 0; + if (!ahcd->ed_rm_list) { + if (ahcd->ed_controltail) { + admhc_writel(ahcd, + find_head (ahcd->ed_controltail)->dma, + &ahcd->regs->ed_controlhead); + enables |= OHCI_CTRL_CLE; + temp |= OHCI_CLF; + } + if (ahcd->ed_bulktail) { + admhc_writel(ahcd, find_head (ahcd->ed_bulktail)->dma, + &ahcd->regs->ed_bulkhead); + enables |= OHCI_CTRL_BLE; + temp |= OHCI_BLF; + } + } + if (hcd->self.bandwidth_isoc_reqs || hcd->self.bandwidth_int_reqs) + enables |= OHCI_CTRL_PLE|OHCI_CTRL_IE; + if (enables) { + admhc_dbg(ahcd, "restarting schedules ... %08x\n", enables); + ahcd->hc_control |= enables; + admhc_writel(ahcd, ahcd->hc_control, &ahcd->ahcd->regs->control); + if (temp) + admhc_writel(ahcd, temp, &ahcd->regs->cmdstatus); + (void) admhc_readl(ahcd, &ahcd->regs->control); + } + + return 0; +} + +static int admhc_bus_suspend(struct usb_hcd *hcd) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + int rc; + + spin_lock_irq(&ahcd->lock); + + if (unlikely(!HCD_HW_ACCESSIBLE(hcd))) + rc = -ESHUTDOWN; + else + rc = admhc_rh_suspend(ahcd, 0); + spin_unlock_irq(&ahcd->lock); + return rc; +} + +static int admhc_bus_resume(struct usb_hcd *hcd) +{ + struct admhcd *ahcd = hcd_to_admhcd(hcd); + int rc; + + if (time_before(jiffies, ahcd->next_statechange)) + msleep(5); + + spin_lock_irq(&ahcd->lock); + + if (unlikely(!HCD_HW_ACCESSIBLE(hcd))) + rc = -ESHUTDOWN; + else + rc = admhc_rh_resume(ahcd); + spin_unlock_irq(&ahcd->lock); + + /* poll until we know a device is connected or we autostop */ + if (rc == 0) + usb_hcd_poll_rh_status(hcd); + return rc; +} + +/* Carry out polling-, autostop-, and autoresume-related state changes */ +static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed, + int any_connected) +{ + int poll_rh = 1; + + switch (ahcd->hc_control & OHCI_CTRL_HCFS) { + + case OHCI_USB_OPER: + /* keep on polling until we know a device is connected + * and RHSC is enabled */ + if (!ahcd->autostop) { + if (any_connected || + !device_may_wakeup(&admhcd_to_hcd(ahcd) + ->self.root_hub->dev)) { + if (admhc_readl(ahcd, &ahcd->regs->int_enable) & + OHCI_INTR_RHSC) + poll_rh = 0; + } else { + ahcd->autostop = 1; + ahcd->next_statechange = jiffies + HZ; + } + + /* if no devices have been attached for one second, autostop */ + } else { + if (changed || any_connected) { + ahcd->autostop = 0; + ahcd->next_statechange = jiffies + + STATECHANGE_DELAY; + } else if (time_after_eq(jiffies, + ahcd->next_statechange) + && !ahcd->ed_rm_list + && !(ahcd->hc_control & + OHCI_SCHED_ENABLES)) { + ahcd_rh_suspend(ahcd, 1); + } + } + break; + + /* if there is a port change, autostart or ask to be resumed */ + case OHCI_USB_SUSPEND: + case OHCI_USB_RESUME: + if (changed) { + if (ahcd->autostop) + admhc_rh_resume(ahcd); + else + usb_hcd_resume_root_hub(admhcd_to_hcd(ahcd)); + } else { + /* everything is idle, no need for polling */ + poll_rh = 0; + } + break; + } + return poll_rh; +} + +/*-------------------------------------------------------------------------*/ + +/* must not be called from interrupt context */ +static int admhc_restart(struct admhcd *ahcd) +{ + int temp; + int i; + struct urb_priv *priv; + + /* mark any devices gone, so they do nothing till khubd disconnects. + * recycle any "live" eds/tds (and urbs) right away. + * later, khubd disconnect processing will recycle the other state, + * (either as disconnect/reconnect, or maybe someday as a reset). + */ + spin_lock_irq(&ahcd->lock); + admhc_disable(ahcd); + usb_root_hub_lost_power(admhcd_to_hcd(ahcd)->self.root_hub); + if (!list_empty(&ahcd->pending)) + admhc_dbg(ahcd, "abort schedule...\n"); + list_for_each_entry(priv, &ahcd->pending, pending) { + struct urb *urb = priv->td[0]->urb; + struct ed *ed = priv->ed; + + switch (ed->state) { + case ED_OPER: + ed->state = ED_UNLINK; + ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE); + ed_deschedule (ahcd, ed); + + ed->ed_next = ahcd->ed_rm_list; + ed->ed_prev = NULL; + ahcd->ed_rm_list = ed; + /* FALLTHROUGH */ + case ED_UNLINK: + break; + default: + admhc_dbg(ahcd, "bogus ed %p state %d\n", + ed, ed->state); + } + + if (!urb->unlinked) + urb->unlinked = -ESHUTDOWN; + } + finish_unlinks(ahcd, 0); + spin_unlock_irq(&ahcd->lock); + + /* paranoia, in case that didn't work: */ + + /* empty the interrupt branches */ + for (i = 0; i < NUM_INTS; i++) ahcd->load[i] = 0; + for (i = 0; i < NUM_INTS; i++) ahcd->hcca->int_table[i] = 0; + + /* no EDs to remove */ + ahcd->ed_rm_list = NULL; + + /* empty control and bulk lists */ + ahcd->ed_controltail = NULL; + ahcd->ed_bulktail = NULL; + + if ((temp = admhc_run(ahcd)) < 0) { + admhc_err(ahcd, "can't restart, %d\n", temp); + return temp; + } else { + /* here we "know" root ports should always stay powered, + * and that if we try to turn them back on the root hub + * will respond to CSC processing. + */ + i = ahcd->num_ports; + while (i--) + admhc_writel(ahcd, RH_PS_PSS, + &ahcd->regs->portstatus[i]); + admhc_dbg(ahcd, "restart complete\n"); + } + return 0; +} + +#else /* CONFIG_PM */ + +static inline int admhc_rh_resume(struct admhcd *ahcd) +{ + return 0; +} + +/* Carry out polling-related state changes. + * autostop isn't used when CONFIG_PM is turned off. + */ +static int admhc_root_hub_state_changes(struct admhcd *ahcd, int changed, + int any_connected) +{ + /* If INSM is enabled, don't poll */ + if (admhc_readl(ahcd, &ahcd->regs->int_enable) & ADMHC_INTR_INSM) + return 0; + + /* If no status changes are pending, enable status-change interrupts */ + if (!changed) { + admhc_intr_enable(ahcd, ADMHC_INTR_INSM); + return 0; + } + + return 1; +} + +#endif /* CONFIG_PM */ + diff --git a/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-q.c b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-q.c new file mode 100644 index 0000000..cd9c892 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120-q.c @@ -0,0 +1,964 @@ +/* + * ADM5120 HCD (Host Controller Driver) for USB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: drivers/usb/host/ohci-q.c + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include + +/*-------------------------------------------------------------------------*/ + +/* + * URB goes back to driver, and isn't reissued. + * It's completely gone from HC data structures. + * PRECONDITION: ahcd lock held, irqs blocked. + */ +static void +finish_urb(struct admhcd *ahcd, struct urb *urb, int status) +__releases(ahcd->lock) +__acquires(ahcd->lock) +{ + urb_priv_free(ahcd, urb->hcpriv); + + if (likely(status == -EINPROGRESS)) + status = 0; + + switch (usb_pipetype(urb->pipe)) { + case PIPE_ISOCHRONOUS: + admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--; + break; + case PIPE_INTERRUPT: + admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--; + break; + } + +#ifdef ADMHC_VERBOSE_DEBUG + urb_print(ahcd, urb, "RET", usb_pipeout(urb->pipe), status); +#endif + + /* urb->complete() can reenter this HCD */ + usb_hcd_unlink_urb_from_ep(admhcd_to_hcd(ahcd), urb); + spin_unlock(&ahcd->lock); + usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb, status); + spin_lock(&ahcd->lock); +} + + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +#if 0 /* FIXME */ +/* search for the right schedule branch to use for a periodic ed. + * does some load balancing; returns the branch, or negative errno. + */ +static int balance(struct admhcd *ahcd, int interval, int load) +{ + int i, branch = -ENOSPC; + + /* iso periods can be huge; iso tds specify frame numbers */ + if (interval > NUM_INTS) + interval = NUM_INTS; + + /* search for the least loaded schedule branch of that period + * that has enough bandwidth left unreserved. + */ + for (i = 0; i < interval ; i++) { + if (branch < 0 || ahcd->load[branch] > ahcd->load[i]) { + int j; + + /* usb 1.1 says 90% of one frame */ + for (j = i; j < NUM_INTS; j += interval) { + if ((ahcd->load[j] + load) > 900) + break; + } + if (j < NUM_INTS) + continue; + branch = i; + } + } + return branch; +} +#endif + +/*-------------------------------------------------------------------------*/ + +#if 0 /* FIXME */ +/* both iso and interrupt requests have periods; this routine puts them + * into the schedule tree in the apppropriate place. most iso devices use + * 1msec periods, but that's not required. + */ +static void periodic_link(struct admhcd *ahcd, struct ed *ed) +{ + unsigned i; + + admhc_vdbg(ahcd, "link %sed %p branch %d [%dus.], interval %d\n", + (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "", + ed, ed->branch, ed->load, ed->interval); + + for (i = ed->branch; i < NUM_INTS; i += ed->interval) { + struct ed **prev = &ahcd->periodic[i]; + __hc32 *prev_p = &ahcd->hcca->int_table[i]; + struct ed *here = *prev; + + /* sorting each branch by period (slow before fast) + * lets us share the faster parts of the tree. + * (plus maybe: put interrupt eds before iso) + */ + while (here && ed != here) { + if (ed->interval > here->interval) + break; + prev = &here->ed_next; + prev_p = &here->hwNextED; + here = *prev; + } + if (ed != here) { + ed->ed_next = here; + if (here) + ed->hwNextED = *prev_p; + wmb(); + *prev = ed; + *prev_p = cpu_to_hc32(ahcd, ed->dma); + wmb(); + } + ahcd->load[i] += ed->load; + } + admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval; +} +#endif + +/* link an ed into the HC chain */ + +static int ed_schedule(struct admhcd *ahcd, struct ed *ed) +{ + struct ed *old_tail; + + if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING) + return -EAGAIN; + + ed->state = ED_OPER; + + old_tail = ahcd->ed_tails[ed->type]; + + ed->ed_next = old_tail->ed_next; + if (ed->ed_next) { + ed->ed_next->ed_prev = ed; + ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma); + } + ed->ed_prev = old_tail; + + old_tail->ed_next = ed; + old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma); + + ahcd->ed_tails[ed->type] = ed; + + admhc_dma_enable(ahcd); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#if 0 /* FIXME */ +/* scan the periodic table to find and unlink this ED */ +static void periodic_unlink(struct admhcd *ahcd, struct ed *ed) +{ + int i; + + for (i = ed->branch; i < NUM_INTS; i += ed->interval) { + struct ed *temp; + struct ed **prev = &ahcd->periodic[i]; + __hc32 *prev_p = &ahcd->hcca->int_table[i]; + + while (*prev && (temp = *prev) != ed) { + prev_p = &temp->hwNextED; + prev = &temp->ed_next; + } + if (*prev) { + *prev_p = ed->hwNextED; + *prev = ed->ed_next; + } + ahcd->load[i] -= ed->load; + } + + admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval; + admhc_vdbg(ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n", + (ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "", + ed, ed->branch, ed->load, ed->interval); +} +#endif + +/* unlink an ed from the HC chain. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed + * (assuming it already started that, which needn't be true). + * + * ED_UNLINK is a transient state: the HC may still see this ED, but soon + * it won't. ED_SKIP means the HC will finish its current transaction, + * but won't start anything new. The TD queue may still grow; device + * drivers don't know about this HCD-internal state. + * + * When the HC can't see the ED, something changes ED_UNLINK to one of: + * + * - ED_OPER: when there's any request queued, the ED gets rescheduled + * immediately. HC should be working on them. + * + * - ED_IDLE: when there's no TD queue. there's no reason for the HC + * to care about this ED; safe to disable the endpoint. + * + * When finish_unlinks() runs later, after SOF interrupt, it will often + * complete one or more URB unlinks before making that state change. + */ +static void ed_deschedule(struct admhcd *ahcd, struct ed *ed) +{ + +#ifdef ADMHC_VERBOSE_DEBUG + admhc_dump_ed(ahcd, "ED-DESCHED", ed, 1); +#endif + + ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP); + wmb(); + ed->state = ED_UNLINK; + + /* remove this ED from the HC list */ + ed->ed_prev->hwNextED = ed->hwNextED; + + /* and remove it from our list also */ + ed->ed_prev->ed_next = ed->ed_next; + + if (ed->ed_next) + ed->ed_next->ed_prev = ed->ed_prev; + + if (ahcd->ed_tails[ed->type] == ed) + ahcd->ed_tails[ed->type] = ed->ed_prev; +} + +/*-------------------------------------------------------------------------*/ + +static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info) +{ + struct ed *ed; + struct td *td; + + ed = ed_alloc(ahcd, GFP_ATOMIC); + if (!ed) + goto err; + + /* dummy td; end of td list for this ed */ + td = td_alloc(ahcd, GFP_ATOMIC); + if (!td) + goto err_free_ed; + + switch (type) { + case PIPE_INTERRUPT: + info |= ED_INT; + break; + case PIPE_ISOCHRONOUS: + info |= ED_ISO; + break; + } + + ed->dummy = td; + ed->state = ED_IDLE; + ed->type = type; + + ed->hwINFO = cpu_to_hc32(ahcd, info); + ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma); + ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */ + + return ed; + +err_free_ed: + ed_free(ahcd, ed); +err: + return NULL; +} + +/* get and maybe (re)init an endpoint. init _should_ be done only as part + * of enumeration, usb_set_configuration() or usb_set_interface(). + */ +static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep, + struct usb_device *udev, unsigned int pipe, int interval) +{ + struct ed *ed; + unsigned long flags; + + spin_lock_irqsave(&ahcd->lock, flags); + + ed = ep->hcpriv; + if (!ed) { + u32 info; + + /* FIXME: usbcore changes dev->devnum before SET_ADDRESS + * succeeds ... otherwise we wouldn't need "pipe". + */ + info = usb_pipedevice(pipe); + info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT; + info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT; + if (udev->speed == USB_SPEED_FULL) + info |= ED_SPEED_FULL; + + ed = ed_create(ahcd, usb_pipetype(pipe), info); + if (ed) + ep->hcpriv = ed; + } + + spin_unlock_irqrestore(&ahcd->lock, flags); + + return ed; +} + +/*-------------------------------------------------------------------------*/ + +/* request unlinking of an endpoint from an operational HC. + * put the ep on the rm_list + * real work is done at the next start frame (SOFI) hardware interrupt + * caller guarantees HCD is running, so hardware access is safe, + * and that ed->state is ED_OPER + */ +static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed) +{ + +#ifdef ADMHC_VERBOSE_DEBUG + admhc_dump_ed(ahcd, "ED-UNLINK", ed, 1); +#endif + + ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE); + ed_deschedule(ahcd, ed); + + /* add this ED into the remove list */ + ed->ed_rm_next = ahcd->ed_rm_list; + ahcd->ed_rm_list = ed; + + /* enable SOF interrupt */ + admhc_intr_ack(ahcd, ADMHC_INTR_SOFI); + admhc_intr_enable(ahcd, ADMHC_INTR_SOFI); + /* flush those writes */ + admhc_writel_flush(ahcd); + + /* SOF interrupt might get delayed; record the frame counter value that + * indicates when the HC isn't looking at it, so concurrent unlinks + * behave. frame_no wraps every 2^16 msec, and changes right before + * SOF is triggered. + */ + ed->tick = admhc_frame_no(ahcd) + 1; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void +td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len, + struct urb *urb, int index) +{ + struct td *td, *td_pt; + struct urb_priv *urb_priv = urb->hcpriv; + int hash; + u32 cbl = 0; + +#if 1 + if (index == (urb_priv->td_cnt - 1) && + ((urb->transfer_flags & URB_NO_INTERRUPT) == 0)) + cbl |= TD_IE; +#else + if (index == (urb_priv->td_cnt - 1)) + cbl |= TD_IE; +#endif + + /* use this td as the next dummy */ + td_pt = urb_priv->td[index]; + + /* fill the old dummy TD */ + td = urb_priv->td[index] = urb_priv->ed->dummy; + urb_priv->ed->dummy = td_pt; + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->urb = urb; + td->data_dma = data; + if (!len) + data = 0; + + if (data) + cbl |= (len & TD_BL_MASK); + + info |= TD_OWN; + + /* setup hardware specific fields */ + td->hwINFO = cpu_to_hc32(ahcd, info); + td->hwDBP = cpu_to_hc32(ahcd, data); + td->hwCBL = cpu_to_hc32(ahcd, cbl); + td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma); + + /* append to queue */ + list_add_tail(&td->td_list, &td->ed->td_list); + + /* hash it for later reverse mapping */ + hash = TD_HASH_FUNC(td->td_dma); + td->td_hash = ahcd->td_hash[hash]; + ahcd->td_hash[hash] = td; + + /* HC might read the TD (or cachelines) right away ... */ + wmb(); + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* Prepare all TDs of a transfer, and queue them onto the ED. + * Caller guarantees HC is active. + * Usually the ED is already on the schedule, so TDs might be + * processed as soon as they're queued. + */ +static void td_submit_urb(struct admhcd *ahcd, struct urb *urb) +{ + struct urb_priv *urb_priv = urb->hcpriv; + dma_addr_t data; + int data_len = urb->transfer_buffer_length; + int cnt = 0; + u32 info = 0; + int is_out = usb_pipeout(urb->pipe); + u32 toggle = 0; + + /* OHCI handles the bulk/interrupt data toggles itself. We just + * use the device toggle bits for resetting, and rely on the fact + * that resetting toggle is meaningless if the endpoint is active. + */ + + if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) { + toggle = TD_T_CARRY; + } else { + toggle = TD_T_DATA0; + usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe), + is_out, 1); + } + + urb_priv->td_idx = 0; + list_add(&urb_priv->pending, &ahcd->pending); + + if (data_len) + data = urb->transfer_dma; + else + data = 0; + + /* NOTE: TD_CC is set so we can tell which TDs the HC processed by + * using TD_CC_GET, as well as by seeing them on the done list. + * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.) + */ + switch (urb_priv->ed->type) { + case PIPE_INTERRUPT: + info = is_out + ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT + : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN; + + /* setup service interval and starting frame number */ + info |= (urb->start_frame & TD_FN_MASK); + info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT; + + td_fill(ahcd, info, data, data_len, urb, cnt); + cnt++; + + admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++; + break; + + case PIPE_BULK: + info = is_out + ? TD_SCC_NOTACCESSED | TD_DP_OUT + : TD_SCC_NOTACCESSED | TD_DP_IN; + + /* TDs _could_ transfer up to 8K each */ + while (data_len > TD_DATALEN_MAX) { + td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), + data, TD_DATALEN_MAX, urb, cnt); + data += TD_DATALEN_MAX; + data_len -= TD_DATALEN_MAX; + cnt++; + } + + td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data, + data_len, urb, cnt); + cnt++; + + if ((urb->transfer_flags & URB_ZERO_PACKET) + && (cnt < urb_priv->td_cnt)) { + td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), + 0, 0, urb, cnt); + cnt++; + } + break; + + /* control manages DATA0/DATA1 toggle per-request; SETUP resets it, + * any DATA phase works normally, and the STATUS ack is special. + */ + case PIPE_CONTROL: + /* fill a TD for the setup */ + info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0; + td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++); + + if (data_len > 0) { + /* fill a TD for the data */ + info = TD_SCC_NOTACCESSED | TD_T_DATA1; + info |= is_out ? TD_DP_OUT : TD_DP_IN; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill(ahcd, info, data, data_len, urb, cnt++); + } + + /* fill a TD for the ACK */ + info = (is_out || data_len == 0) + ? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1 + : TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1; + td_fill(ahcd, info, data, 0, urb, cnt++); + + break; + + /* ISO has no retransmit, so no toggle; + * Each TD could handle multiple consecutive frames (interval 1); + * we could often reduce the number of TDs here. + */ + case PIPE_ISOCHRONOUS: + info = is_out + ? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT + : TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN; + + for (cnt = 0; cnt < urb->number_of_packets; cnt++) { + int frame = urb->start_frame; + + frame += cnt * urb->interval; + frame &= TD_FN_MASK; + td_fill(ahcd, info | frame, + data + urb->iso_frame_desc[cnt].offset, + urb->iso_frame_desc[cnt].length, urb, cnt); + } + admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++; + break; + } + + if (urb_priv->td_cnt != cnt) + admhc_err(ahcd, "bad number of tds created for urb %p\n", urb); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + +/* calculate transfer length/status and update the urb */ +static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td) +{ + struct urb_priv *urb_priv = urb->hcpriv; + u32 info; + u32 bl; + u32 tdDBP; + int type = usb_pipetype(urb->pipe); + int cc; + int status = -EINPROGRESS; + + info = hc32_to_cpup(ahcd, &td->hwINFO); + tdDBP = hc32_to_cpup(ahcd, &td->hwDBP); + bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL)); + cc = TD_CC_GET(info); + + /* ISO ... drivers see per-TD length/status */ + if (type == PIPE_ISOCHRONOUS) { + /* TODO */ + int dlen = 0; + + /* NOTE: assumes FC in tdINFO == 0, and that + * only the first of 0..MAXPSW psws is used. + */ + if (info & TD_CC) /* hc didn't touch? */ + return status; + + if (usb_pipeout(urb->pipe)) + dlen = urb->iso_frame_desc[td->index].length; + else { + /* short reads are always OK for ISO */ + if (cc == TD_CC_DATAUNDERRUN) + cc = TD_CC_NOERROR; + dlen = tdDBP - td->data_dma + bl; + } + + urb->actual_length += dlen; + urb->iso_frame_desc[td->index].actual_length = dlen; + urb->iso_frame_desc[td->index].status = cc_to_error[cc]; + + if (cc != TD_CC_NOERROR) + admhc_vdbg(ahcd, + "urb %p iso td %p (%d) len %d cc %d\n", + urb, td, 1 + td->index, dlen, cc); + + /* BULK, INT, CONTROL ... drivers see aggregate length/status, + * except that "setup" bytes aren't counted and "short" transfers + * might not be reported as errors. + */ + } else { + /* update packet status if needed (short is normally ok) */ + if (cc == TD_CC_DATAUNDERRUN + && !(urb->transfer_flags & URB_SHORT_NOT_OK)) + cc = TD_CC_NOERROR; + + if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0) + status = cc_to_error[cc]; + + + /* count all non-empty packets except control SETUP packet */ + if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0) + urb->actual_length += tdDBP - td->data_dma + bl; + + if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0) + admhc_vdbg(ahcd, + "urb %p td %p (%d) cc %d, len=%d/%d\n", + urb, td, td->index, cc, + urb->actual_length, + urb->transfer_buffer_length); + } + + list_del(&td->td_list); + urb_priv->td_idx++; + + return status; +} + +/*-------------------------------------------------------------------------*/ + +static void ed_halted(struct admhcd *ahcd, struct td *td, int cc) +{ + struct urb *urb = td->urb; + struct urb_priv *urb_priv = urb->hcpriv; + struct ed *ed = td->ed; + struct list_head *tmp = td->td_list.next; + __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C); + + admhc_dump_ed(ahcd, "ed halted", td->ed, 1); + /* clear ed halt; this is the td that caused it, but keep it inactive + * until its urb->complete() has a chance to clean up. + */ + ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP); + wmb(); + ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H); + + /* Get rid of all later tds from this urb. We don't have + * to be careful: no errors and nothing was transferred. + * Also patch the ed so it looks as if those tds completed normally. + */ + while (tmp != &ed->td_list) { + struct td *next; + + next = list_entry(tmp, struct td, td_list); + tmp = next->td_list.next; + + if (next->urb != urb) + break; + + /* NOTE: if multi-td control DATA segments get supported, + * this urb had one of them, this td wasn't the last td + * in that segment (TD_R clear), this ed halted because + * of a short read, _and_ URB_SHORT_NOT_OK is clear ... + * then we need to leave the control STATUS packet queued + * and clear ED_SKIP. + */ + list_del(&next->td_list); + urb_priv->td_cnt++; + ed->hwHeadP = next->hwNextTD | toggle; + } + + /* help for troubleshooting: report anything that + * looks odd ... that doesn't include protocol stalls + * (or maybe some other things) + */ + switch (cc) { + case TD_CC_DATAUNDERRUN: + if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0) + break; + /* fallthrough */ + case TD_CC_STALL: + if (usb_pipecontrol(urb->pipe)) + break; + /* fallthrough */ + default: + admhc_dbg(ahcd, + "urb %p path %s ep%d%s %08x cc %d --> status %d\n", + urb, urb->dev->devpath, + usb_pipeendpoint (urb->pipe), + usb_pipein(urb->pipe) ? "in" : "out", + hc32_to_cpu(ahcd, td->hwINFO), + cc, cc_to_error[cc]); + } +} + +/*-------------------------------------------------------------------------*/ + +/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */ +static void +finish_unlinks(struct admhcd *ahcd, u16 tick) +{ + struct ed *ed, **last; + +rescan_all: + for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) { + struct list_head *entry, *tmp; + int completed, modified; + __hc32 *prev; + + /* only take off EDs that the HC isn't using, accounting for + * frame counter wraps and EDs with partially retired TDs + */ + if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) { + if (tick_before(tick, ed->tick)) { +skip_ed: + last = &ed->ed_rm_next; + continue; + } +#if 0 + if (!list_empty(&ed->td_list)) { + struct td *td; + u32 head; + + td = list_entry(ed->td_list.next, struct td, + td_list); + head = hc32_to_cpu(ahcd, ed->hwHeadP) & + TD_MASK; + + /* INTR_WDH may need to clean up first */ + if (td->td_dma != head) + goto skip_ed; + } +#endif + } + + /* reentrancy: if we drop the schedule lock, someone might + * have modified this list. normally it's just prepending + * entries (which we'd ignore), but paranoia won't hurt. + */ + *last = ed->ed_rm_next; + ed->ed_rm_next = NULL; + modified = 0; + + /* unlink urbs as requested, but rescan the list after + * we call a completion since it might have unlinked + * another (earlier) urb + * + * When we get here, the HC doesn't see this ed. But it + * must not be rescheduled until all completed URBs have + * been given back to the driver. + */ +rescan_this: + completed = 0; + prev = &ed->hwHeadP; + list_for_each_safe(entry, tmp, &ed->td_list) { + struct td *td; + struct urb *urb; + struct urb_priv *urb_priv; + __hc32 savebits; + u32 tdINFO; + int status; + + td = list_entry(entry, struct td, td_list); + urb = td->urb; + urb_priv = td->urb->hcpriv; + + if (!urb->unlinked) { + prev = &td->hwNextTD; + continue; + } + + if ((urb_priv) == NULL) + continue; + + /* patch pointer hc uses */ + savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK); + *prev = td->hwNextTD | savebits; + /* If this was unlinked, the TD may not have been + * retired ... so manually save dhe data toggle. + * The controller ignores the value we save for + * control and ISO endpoints. + */ + tdINFO = hc32_to_cpup(ahcd, &td->hwINFO); + if ((tdINFO & TD_T) == TD_T_DATA0) + ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_C); + else if ((tdINFO & TD_T) == TD_T_DATA1) + ed->hwHeadP |= cpu_to_hc32(ahcd, ED_C); + + /* HC may have partly processed this TD */ +#ifdef ADMHC_VERBOSE_DEBUG + urb_print(ahcd, urb, "PARTIAL", 0); +#endif + status = td_done(ahcd, urb, td); + + /* if URB is done, clean up */ + if (urb_priv->td_idx == urb_priv->td_cnt) { + modified = completed = 1; + finish_urb(ahcd, urb, status); + } + } + if (completed && !list_empty(&ed->td_list)) + goto rescan_this; + + /* ED's now officially unlinked, hc doesn't see */ + ed->state = ED_IDLE; + ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H); + ed->hwNextED = 0; + wmb(); + ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP | ED_DEQUEUE); + + /* but if there's work queued, reschedule */ + if (!list_empty(&ed->td_list)) { + if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state)) + ed_schedule(ahcd, ed); + } + + if (modified) + goto rescan_all; + } +} + +/*-------------------------------------------------------------------------*/ +/* + * Process normal completions (error or success) and clean the schedules. + * + * This is the main path for handing urbs back to drivers. The only other + * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list, + * instead of scanning the (re-reversed) donelist as this does. + */ + +static void ed_unhalt(struct admhcd *ahcd, struct ed *ed, struct urb *urb) +{ + struct list_head *entry, *tmp; + __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C); + +#ifdef ADMHC_VERBOSE_DEBUG + admhc_dump_ed(ahcd, "UNHALT", ed, 0); +#endif + /* clear ed halt; this is the td that caused it, but keep it inactive + * until its urb->complete() has a chance to clean up. + */ + ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP); + wmb(); + ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H); + + list_for_each_safe(entry, tmp, &ed->td_list) { + struct td *td = list_entry(entry, struct td, td_list); + __hc32 info; + + if (td->urb != urb) + break; + + info = td->hwINFO; + info &= ~cpu_to_hc32(ahcd, TD_CC | TD_OWN); + td->hwINFO = info; + + ed->hwHeadP = td->hwNextTD | toggle; + wmb(); + } + +} + +static void ed_intr_refill(struct admhcd *ahcd, struct ed *ed) +{ + __hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C); + + ed->hwHeadP = ed->hwTailP | toggle; +} + + +static inline int is_ed_halted(struct admhcd *ahcd, struct ed *ed) +{ + return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) == ED_H); +} + +static inline int is_td_halted(struct admhcd *ahcd, struct ed *ed, + struct td *td) +{ + return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & TD_MASK) == + (hc32_to_cpup(ahcd, &td->hwNextTD) & TD_MASK)); +} + +static void ed_update(struct admhcd *ahcd, struct ed *ed) +{ + struct list_head *entry, *tmp; + +#ifdef ADMHC_VERBOSE_DEBUG + admhc_dump_ed(ahcd, "UPDATE", ed, 1); +#endif + + list_for_each_safe(entry, tmp, &ed->td_list) { + struct td *td = list_entry(entry, struct td, td_list); + struct urb *urb = td->urb; + struct urb_priv *urb_priv = urb->hcpriv; + int status; + + if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN) + break; + + /* update URB's length and status from TD */ + status = td_done(ahcd, urb, td); + if (is_ed_halted(ahcd, ed) && is_td_halted(ahcd, ed, td)) + ed_unhalt(ahcd, ed, urb); + + if (ed->type == PIPE_INTERRUPT) + ed_intr_refill(ahcd, ed); + + /* If all this urb's TDs are done, call complete() */ + if (urb_priv->td_idx == urb_priv->td_cnt) + finish_urb(ahcd, urb, status); + + /* clean schedule: unlink EDs that are no longer busy */ + if (list_empty(&ed->td_list)) { + if (ed->state == ED_OPER) + start_ed_unlink(ahcd, ed); + + /* ... reenabling halted EDs only after fault cleanup */ + } else if ((ed->hwINFO & cpu_to_hc32(ahcd, + ED_SKIP | ED_DEQUEUE)) + == cpu_to_hc32(ahcd, ED_SKIP)) { + td = list_entry(ed->td_list.next, struct td, td_list); +#if 0 + if (!(td->hwINFO & cpu_to_hc32(ahcd, TD_DONE))) { + ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP); + /* ... hc may need waking-up */ + switch (ed->type) { + case PIPE_CONTROL: + admhc_writel(ahcd, OHCI_CLF, + &ahcd->regs->cmdstatus); + break; + case PIPE_BULK: + admhc_writel(ahcd, OHCI_BLF, + &ahcd->regs->cmdstatus); + break; + } + } +#else + if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN))) + ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP); +#endif + } + + } +} + +/* there are some tds completed; called in_irq(), with HCD locked */ +static void admhc_td_complete(struct admhcd *ahcd) +{ + struct ed *ed; + + for (ed = ahcd->ed_head; ed; ed = ed->ed_next) { + if (ed->state != ED_OPER) + continue; + + ed_update(ahcd, ed); + } +} diff --git a/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120.h b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120.h new file mode 100644 index 0000000..e47aac8 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/usb/host/adm5120.h @@ -0,0 +1,755 @@ +/* + * ADM5120 HCD (Host Controller Driver) for USB + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This file was derived from: drivers/usb/host/ohci.h + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +/* + * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to + * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the + * host controller implementation. + */ +typedef __u32 __bitwise __hc32; +typedef __u16 __bitwise __hc16; + +/* + * OHCI Endpoint Descriptor (ED) ... holds TD queue + * See OHCI spec, section 4.2 + * + * This is a "Queue Head" for those transfers, which is why + * both EHCI and UHCI call similar structures a "QH". + */ + +#define TD_DATALEN_MAX 4096 + +#define ED_ALIGN 16 +#define ED_MASK ((u32)~(ED_ALIGN-1)) /* strip hw status in low addr bits */ + +struct ed { + /* first fields are hardware-specified */ + __hc32 hwINFO; /* endpoint config bitmap */ + /* info bits defined by hcd */ +#define ED_DEQUEUE (1 << 27) + /* info bits defined by the hardware */ +#define ED_MPS_SHIFT 16 +#define ED_MPS_MASK ((1 << 11)-1) +#define ED_MPS_GET(x) (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK) +#define ED_ISO (1 << 15) /* isochronous endpoint */ +#define ED_SKIP (1 << 14) +#define ED_SPEED_FULL (1 << 13) /* fullspeed device */ +#define ED_INT (1 << 11) /* interrupt endpoint */ +#define ED_EN_SHIFT 7 /* endpoint shift */ +#define ED_EN_MASK ((1 << 4)-1) /* endpoint mask */ +#define ED_EN_GET(x) (((x) >> ED_EN_SHIFT) & ED_EN_MASK) +#define ED_FA_MASK ((1 << 7)-1) /* function address mask */ +#define ED_FA_GET(x) ((x) & ED_FA_MASK) + __hc32 hwTailP; /* tail of TD list */ + __hc32 hwHeadP; /* head of TD list (hc r/w) */ +#define ED_C (0x02) /* toggle carry */ +#define ED_H (0x01) /* halted */ + __hc32 hwNextED; /* next ED in list */ + + /* rest are purely for the driver's use */ + dma_addr_t dma; /* addr of ED */ + struct td *dummy; /* next TD to activate */ + + struct list_head urb_list; /* list of our URBs */ + + /* host's view of schedule */ + struct ed *ed_next; /* on schedule list */ + struct ed *ed_prev; /* for non-interrupt EDs */ + struct ed *ed_rm_next; /* on rm list */ + struct list_head td_list; /* "shadow list" of our TDs */ + + /* create --> IDLE --> OPER --> ... --> IDLE --> destroy + * usually: OPER --> UNLINK --> (IDLE | OPER) --> ... + */ + u8 state; /* ED_{IDLE,UNLINK,OPER} */ +#define ED_IDLE 0x00 /* NOT linked to HC */ +#define ED_UNLINK 0x01 /* being unlinked from hc */ +#define ED_OPER 0x02 /* IS linked to hc */ + + u8 type; /* PIPE_{BULK,...} */ + + /* periodic scheduling params (for intr and iso) */ + u8 branch; + u16 interval; + u16 load; + u16 last_iso; /* iso only */ + + /* HC may see EDs on rm_list until next frame (frame_no == tick) */ + u16 tick; +} __attribute__ ((aligned(ED_ALIGN))); + +/* + * OHCI Transfer Descriptor (TD) ... one per transfer segment + * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt) + * and 4.3.2 (iso) + */ + +#define TD_ALIGN 32 +#define TD_MASK ((u32)~(TD_ALIGN-1)) /* strip hw status in low addr bits */ + +struct td { + /* first fields are hardware-specified */ + __hc32 hwINFO; /* transfer info bitmask */ + + /* hwINFO bits */ +#define TD_OWN (1 << 31) /* owner of the descriptor */ +#define TD_CC_SHIFT 27 /* condition code */ +#define TD_CC_MASK 0xf +#define TD_CC (TD_CC_MASK << TD_CC_SHIFT) +#define TD_CC_GET(x) (((x) >> TD_CC_SHIFT) & TD_CC_MASK) + +#define TD_EC_SHIFT 25 /* error count */ +#define TD_EC_MASK 0x3 +#define TD_EC (TD_EC_MASK << TD_EC_SHIFT) +#define TD_EC_GET(x) ((x >> TD_EC_SHIFT) & TD_EC_MASK) +#define TD_T_SHIFT 23 /* data toggle state */ +#define TD_T_MASK 0x3 +#define TD_T (TD_T_MASK << TD_T_SHIFT) +#define TD_T_DATA0 (0x2 << TD_T_SHIFT) /* DATA0 */ +#define TD_T_DATA1 (0x3 << TD_T_SHIFT) /* DATA1 */ +#define TD_T_CARRY (0x0 << TD_T_SHIFT) /* uses ED_C */ +#define TD_T_GET(x) (((x) >> TD_T_SHIFT) & TD_T_MASK) +#define TD_DP_SHIFT 21 /* direction/pid */ +#define TD_DP_MASK 0x3 +#define TD_DP (TD_DP_MASK << TD_DP_SHIFT) +#define TD_DP_GET (((x) >> TD_DP_SHIFT) & TD_DP_MASK) +#define TD_DP_SETUP (0x0 << TD_DP_SHIFT) /* SETUP pid */ +#define TD_DP_OUT (0x1 << TD_DP_SHIFT) /* OUT pid */ +#define TD_DP_IN (0x2 << TD_DP_SHIFT) /* IN pid */ +#define TD_ISI_SHIFT 8 /* Interrupt Service Interval */ +#define TD_ISI_MASK 0x3f +#define TD_ISI_GET(x) (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK) +#define TD_FN_MASK 0x3f /* frame number */ +#define TD_FN_GET(x) ((x) & TD_FN_MASK) + + __hc32 hwDBP; /* Data Buffer Pointer (or 0) */ + __hc32 hwCBL; /* Controller/Buffer Length */ + + /* hwCBL bits */ +#define TD_BL_MASK 0xffff /* buffer length */ +#define TD_BL_GET(x) ((x) & TD_BL_MASK) +#define TD_IE (1 << 16) /* interrupt enable */ + __hc32 hwNextTD; /* Next TD Pointer */ + + /* rest are purely for the driver's use */ + __u8 index; + struct ed *ed; + struct td *td_hash; /* dma-->td hashtable */ + struct td *next_dl_td; + struct urb *urb; + + dma_addr_t td_dma; /* addr of this TD */ + dma_addr_t data_dma; /* addr of data it points to */ + + struct list_head td_list; /* "shadow list", TDs on same ED */ + + u32 flags; +#define TD_FLAG_DONE (1 << 17) /* retired to done list */ +#define TD_FLAG_ISO (1 << 16) /* copy of ED_ISO */ +} __attribute__ ((aligned(TD_ALIGN))); /* c/b/i need 16; only iso needs 32 */ + +/* + * Hardware transfer status codes -- CC from td->hwINFO + */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_CC_DEVNOTRESP 0x05 +#define TD_CC_PIDCHECKFAIL 0x06 +#define TD_CC_UNEXPECTEDPID 0x07 +#define TD_CC_DATAOVERRUN 0x08 +#define TD_CC_DATAUNDERRUN 0x09 + /* 0x0A, 0x0B reserved for hardware */ +#define TD_CC_BUFFEROVERRUN 0x0C +#define TD_CC_BUFFERUNDERRUN 0x0D + /* 0x0E, 0x0F reserved for HCD */ +#define TD_CC_HCD0 0x0E +#define TD_CC_NOTACCESSED 0x0F + +/* + * preshifted status codes + */ +#define TD_SCC_NOTACCESSED (TD_CC_NOTACCESSED << TD_CC_SHIFT) + + +/* map OHCI TD status codes (CC) to errno values */ +static const int cc_to_error[16] = { + /* No Error */ 0, + /* CRC Error */ -EILSEQ, + /* Bit Stuff */ -EPROTO, + /* Data Togg */ -EILSEQ, + /* Stall */ -EPIPE, + /* DevNotResp */ -ETIME, + /* PIDCheck */ -EPROTO, + /* UnExpPID */ -EPROTO, + /* DataOver */ -EOVERFLOW, + /* DataUnder */ -EREMOTEIO, + /* (for hw) */ -EIO, + /* (for hw) */ -EIO, + /* BufferOver */ -ECOMM, + /* BuffUnder */ -ENOSR, + /* (for HCD) */ -EALREADY, + /* (for HCD) */ -EALREADY +}; + +#define NUM_INTS 32 + +/* + * This is the structure of the OHCI controller's memory mapped I/O region. + * You must use readl() and writel() (in ) to access these fields!! + * Layout is in section 7 (and appendix B) of the spec. + */ +struct admhcd_regs { + __hc32 gencontrol; /* General Control */ + __hc32 int_status; /* Interrupt Status */ + __hc32 int_enable; /* Interrupt Enable */ + __hc32 reserved00; + __hc32 host_control; /* Host General Control */ + __hc32 reserved01; + __hc32 fminterval; /* Frame Interval */ + __hc32 fmnumber; /* Frame Number */ + __hc32 reserved02; + __hc32 reserved03; + __hc32 reserved04; + __hc32 reserved05; + __hc32 reserved06; + __hc32 reserved07; + __hc32 reserved08; + __hc32 reserved09; + __hc32 reserved10; + __hc32 reserved11; + __hc32 reserved12; + __hc32 reserved13; + __hc32 reserved14; + __hc32 reserved15; + __hc32 reserved16; + __hc32 reserved17; + __hc32 reserved18; + __hc32 reserved19; + __hc32 reserved20; + __hc32 reserved21; + __hc32 lsthresh; /* Low Speed Threshold */ + __hc32 rhdesc; /* Root Hub Descriptor */ +#define MAX_ROOT_PORTS 2 + __hc32 portstatus[MAX_ROOT_PORTS]; /* Port Status */ + __hc32 hosthead; /* Host Descriptor Head */ +} __attribute__ ((aligned(32))); + +/* + * General Control register bits + */ +#define ADMHC_CTRL_UHFE (1 << 0) /* USB Host Function Enable */ +#define ADMHC_CTRL_SIR (1 << 1) /* Software Interrupt request */ +#define ADMHC_CTRL_DMAA (1 << 2) /* DMA Arbitration Control */ +#define ADMHC_CTRL_SR (1 << 3) /* Software Reset */ + +/* + * Host General Control register bits + */ +#define ADMHC_HC_BUSS 0x3 /* USB bus state */ +#define ADMHC_BUSS_RESET 0x0 +#define ADMHC_BUSS_RESUME 0x1 +#define ADMHC_BUSS_OPER 0x2 +#define ADMHC_BUSS_SUSPEND 0x3 +#define ADMHC_HC_DMAE (1 << 2) /* DMA enable */ + +/* + * Interrupt Status/Enable register bits + */ +#define ADMHC_INTR_SOFI (1 << 4) /* start of frame */ +#define ADMHC_INTR_RESI (1 << 5) /* resume detected */ +#define ADMHC_INTR_6 (1 << 6) /* unknown */ +#define ADMHC_INTR_7 (1 << 7) /* unknown */ +#define ADMHC_INTR_BABI (1 << 8) /* babble detected */ +#define ADMHC_INTR_INSM (1 << 9) /* root hub status change */ +#define ADMHC_INTR_SO (1 << 10) /* scheduling overrun */ +#define ADMHC_INTR_FNO (1 << 11) /* frame number overflow */ +#define ADMHC_INTR_TDC (1 << 20) /* transfer descriptor completed */ +#define ADMHC_INTR_SWI (1 << 29) /* software interrupt */ +#define ADMHC_INTR_FATI (1 << 30) /* fatal error */ +#define ADMHC_INTR_INTA (1 << 31) /* interrupt active */ + +#define ADMHC_INTR_MIE (1 << 31) /* master interrupt enable */ + +/* + * SOF Frame Interval register bits + */ +#define ADMHC_SFI_FI_MASK ((1 << 14)-1) /* Frame Interval value */ +#define ADMHC_SFI_FSLDP_SHIFT 16 +#define ADMHC_SFI_FSLDP_MASK ((1 << 15)-1) +#define ADMHC_SFI_FIT (1 << 31) /* Frame Interval Toggle */ + +/* + * SOF Frame Number register bits + */ +#define ADMHC_SFN_FN_MASK ((1 << 16)-1) /* Frame Number Mask */ +#define ADMHC_SFN_FR_SHIFT 16 /* Frame Remaining Shift */ +#define ADMHC_SFN_FR_MASK ((1 << 14)-1) /* Frame Remaining Mask */ +#define ADMHC_SFN_FRT (1 << 31) /* Frame Remaining Toggle */ + +/* + * Root Hub Descriptor register bits + */ +#define ADMHC_RH_NUMP 0xff /* number of ports */ +#define ADMHC_RH_PSM (1 << 8) /* power switching mode */ +#define ADMHC_RH_NPS (1 << 9) /* no power switching */ +#define ADMHC_RH_OCPM (1 << 10) /* over current protection mode */ +#define ADMHC_RH_NOCP (1 << 11) /* no over current protection */ +#define ADMHC_RH_PPCM (0xff << 16) /* port power control */ + +#define ADMHC_RH_LPS (1 << 24) /* local power switch */ +#define ADMHC_RH_OCI (1 << 25) /* over current indicator */ + +/* status change bits */ +#define ADMHC_RH_LPSC (1 << 26) /* local power switch change */ +#define ADMHC_RH_OCIC (1 << 27) /* over current indicator change */ + +#define ADMHC_RH_DRWE (1 << 28) /* device remote wakeup enable */ +#define ADMHC_RH_CRWE (1 << 29) /* clear remote wakeup enable */ + +#define ADMHC_RH_CGP (1 << 24) /* clear global power */ +#define ADMHC_RH_SGP (1 << 26) /* set global power */ + +/* + * Port Status register bits + */ +#define ADMHC_PS_CCS (1 << 0) /* current connect status */ +#define ADMHC_PS_PES (1 << 1) /* port enable status */ +#define ADMHC_PS_PSS (1 << 2) /* port suspend status */ +#define ADMHC_PS_POCI (1 << 3) /* port over current indicator */ +#define ADMHC_PS_PRS (1 << 4) /* port reset status */ +#define ADMHC_PS_PPS (1 << 8) /* port power status */ +#define ADMHC_PS_LSDA (1 << 9) /* low speed device attached */ + +/* status change bits */ +#define ADMHC_PS_CSC (1 << 16) /* connect status change */ +#define ADMHC_PS_PESC (1 << 17) /* port enable status change */ +#define ADMHC_PS_PSSC (1 << 18) /* port suspend status change */ +#define ADMHC_PS_OCIC (1 << 19) /* over current indicator change */ +#define ADMHC_PS_PRSC (1 << 20) /* port reset status change */ + +/* port feature bits */ +#define ADMHC_PS_CPE (1 << 0) /* clear port enable */ +#define ADMHC_PS_SPE (1 << 1) /* set port enable */ +#define ADMHC_PS_SPS (1 << 2) /* set port suspend */ +#define ADMHC_PS_CPS (1 << 3) /* clear suspend status */ +#define ADMHC_PS_SPR (1 << 4) /* set port reset */ +#define ADMHC_PS_SPP (1 << 8) /* set port power */ +#define ADMHC_PS_CPP (1 << 9) /* clear port power */ + +/* + * the POTPGT value is not defined in the ADMHC, so define a dummy value + */ +#define ADMHC_POTPGT 2 /* in ms */ + +/* hcd-private per-urb state */ +struct urb_priv { + struct ed *ed; + struct list_head pending; /* URBs on the same ED */ + + u32 td_cnt; /* # tds in this request */ + u32 td_idx; /* index of the current td */ + struct td *td[0]; /* all TDs in this request */ +}; + +#define TD_HASH_SIZE 64 /* power'o'two */ +/* sizeof (struct td) ~= 64 == 2^6 ... */ +#define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE) + +/* + * This is the full ADMHCD controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + +struct admhcd { + spinlock_t lock; + + /* + * I/O memory used to communicate with the HC (dma-consistent) + */ + struct admhcd_regs __iomem *regs; + + /* + * hcd adds to schedule for a live hc any time, but removals finish + * only at the start of the next frame. + */ + + struct ed *ed_head; + struct ed *ed_tails[4]; + + struct ed *ed_rm_list; /* to be removed */ + + struct ed *periodic[NUM_INTS]; /* shadow int_table */ + +#if 0 /* TODO: remove? */ + /* + * OTG controllers and transceivers need software interaction; + * other external transceivers should be software-transparent + */ + struct otg_transceiver *transceiver; + void (*start_hnp)(struct admhcd *ahcd); +#endif + + /* + * memory management for queue data structures + */ + struct dma_pool *td_cache; + struct dma_pool *ed_cache; + struct td *td_hash[TD_HASH_SIZE]; + struct list_head pending; + + /* + * driver state + */ + int num_ports; + int load[NUM_INTS]; + u32 host_control; /* copy of the host_control reg */ + unsigned long next_statechange; /* suspend/resume */ + u32 fminterval; /* saved register */ + unsigned autostop:1; /* rh auto stopping/stopped */ + + unsigned long flags; /* for HC bugs */ +#define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */ +#define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */ +#define OHCI_QUIRK_INITRESET 0x04 /* SiS, OPTi, ... */ +#define OHCI_QUIRK_BE_DESC 0x08 /* BE descriptors */ +#define OHCI_QUIRK_BE_MMIO 0x10 /* BE registers */ +#define OHCI_QUIRK_ZFMICRO 0x20 /* Compaq ZFMicro chipset*/ + /* there are also chip quirks/bugs in init logic */ + +#ifdef DEBUG + struct dentry *debug_dir; + struct dentry *debug_async; + struct dentry *debug_periodic; + struct dentry *debug_registers; +#endif +}; + +/* convert between an hcd pointer and the corresponding ahcd_hcd */ +static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd) +{ + return (struct admhcd *)(hcd->hcd_priv); +} +static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd) +{ + return container_of((void *)ahcd, struct usb_hcd, hcd_priv); +} + +/*-------------------------------------------------------------------------*/ + +#ifndef DEBUG +#define STUB_DEBUG_FILES +#endif /* DEBUG */ + +#ifdef DEBUG +# define admhc_dbg(ahcd, fmt, args...) \ + printk(KERN_DEBUG "adm5120-hcd: " fmt, ## args) +#else +# define admhc_dbg(ahcd, fmt, args...) do { } while (0) +#endif + +#define admhc_err(ahcd, fmt, args...) \ + printk(KERN_ERR "adm5120-hcd: " fmt, ## args) +#define admhc_info(ahcd, fmt, args...) \ + printk(KERN_INFO "adm5120-hcd: " fmt, ## args) +#define admhc_warn(ahcd, fmt, args...) \ + printk(KERN_WARNING "adm5120-hcd: " fmt, ## args) + +#ifdef ADMHC_VERBOSE_DEBUG +# define admhc_vdbg admhc_dbg +#else +# define admhc_vdbg(ahcd, fmt, args...) do { } while (0) +#endif + +/*-------------------------------------------------------------------------*/ + +/* + * While most USB host controllers implement their registers and + * in-memory communication descriptors in little-endian format, + * a minority (notably the IBM STB04XXX and the Motorola MPC5200 + * processors) implement them in big endian format. + * + * In addition some more exotic implementations like the Toshiba + * Spider (aka SCC) cell southbridge are "mixed" endian, that is, + * they have a different endianness for registers vs. in-memory + * descriptors. + * + * This attempts to support either format at compile time without a + * runtime penalty, or both formats with the additional overhead + * of checking a flag bit. + * + * That leads to some tricky Kconfig rules howevber. There are + * different defaults based on some arch/ppc platforms, though + * the basic rules are: + * + * Controller type Kconfig options needed + * --------------- ---------------------- + * little endian CONFIG_USB_ADMHC_LITTLE_ENDIAN + * + * fully big endian CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_ + * CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO + * + * mixed endian CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_ + * CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC} + * + * (If you have a mixed endian controller, you -must- also define + * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building + * both your mixed endian and a fully big endian controller support in + * the same kernel image). + */ + +#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC +#ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN +#define big_endian_desc(ahcd) (ahcd->flags & OHCI_QUIRK_BE_DESC) +#else +#define big_endian_desc(ahcd) 1 /* only big endian */ +#endif +#else +#define big_endian_desc(ahcd) 0 /* only little endian */ +#endif + +#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO +#ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN +#define big_endian_mmio(ahcd) (ahcd->flags & OHCI_QUIRK_BE_MMIO) +#else +#define big_endian_mmio(ahcd) 1 /* only big endian */ +#endif +#else +#define big_endian_mmio(ahcd) 0 /* only little endian */ +#endif + +/* + * Big-endian read/write functions are arch-specific. + * Other arches can be added if/when they're needed. + * + */ +static inline unsigned int admhc_readl(const struct admhcd *ahcd, + __hc32 __iomem *regs) +{ +#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO + return big_endian_mmio(ahcd) ? + readl_be(regs) : + readl(regs); +#else + return readl(regs); +#endif +} + +static inline void admhc_writel(const struct admhcd *ahcd, + const unsigned int val, __hc32 __iomem *regs) +{ +#ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO + big_endian_mmio(ahcd) ? + writel_be(val, regs) : + writel(val, regs); +#else + writel(val, regs); +#endif +} + +static inline void admhc_writel_flush(const struct admhcd *ahcd) +{ +#if 0 + /* TODO: remove? */ + (void) admhc_readl(ahcd, &ahcd->regs->gencontrol); +#endif +} + + +/*-------------------------------------------------------------------------*/ + +/* cpu to ahcd */ +static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x) +{ + return big_endian_desc(ahcd) ? + (__force __hc16)cpu_to_be16(x) : + (__force __hc16)cpu_to_le16(x); +} + +static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x) +{ + return big_endian_desc(ahcd) ? + cpu_to_be16p(x) : + cpu_to_le16p(x); +} + +static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x) +{ + return big_endian_desc(ahcd) ? + (__force __hc32)cpu_to_be32(x) : + (__force __hc32)cpu_to_le32(x); +} + +static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x) +{ + return big_endian_desc(ahcd) ? + cpu_to_be32p(x) : + cpu_to_le32p(x); +} + +/* ahcd to cpu */ +static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x) +{ + return big_endian_desc(ahcd) ? + be16_to_cpu((__force __be16)x) : + le16_to_cpu((__force __le16)x); +} + +static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x) +{ + return big_endian_desc(ahcd) ? + be16_to_cpup((__force __be16 *)x) : + le16_to_cpup((__force __le16 *)x); +} + +static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x) +{ + return big_endian_desc(ahcd) ? + be32_to_cpu((__force __be32)x) : + le32_to_cpu((__force __le32)x); +} + +static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x) +{ + return big_endian_desc(ahcd) ? + be32_to_cpup((__force __be32 *)x) : + le32_to_cpup((__force __le32 *)x); +} + +/*-------------------------------------------------------------------------*/ + +static inline u16 admhc_frame_no(const struct admhcd *ahcd) +{ + u32 t; + + t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK; + return (u16)t; +} + +static inline u16 admhc_frame_remain(const struct admhcd *ahcd) +{ + u32 t; + + t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT; + t &= ADMHC_SFN_FR_MASK; + return (u16)t; +} + +/*-------------------------------------------------------------------------*/ + +static inline void admhc_disable(struct admhcd *ahcd) +{ + admhcd_to_hcd(ahcd)->state = HC_STATE_HALT; +} + +#define FI 0x2edf /* 12000 bits per frame (-1) */ +#define FSLDP(fi) (0x7fff & ((6 * ((fi) - 1200)) / 7)) +#define FIT ADMHC_SFI_FIT +#define LSTHRESH 0x628 /* lowspeed bit threshold */ + +static inline void periodic_reinit(struct admhcd *ahcd) +{ +#if 0 + u32 fi = ahcd->fminterval & ADMHC_SFI_FI_MASK; + u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT; + + /* TODO: adjust FSLargestDataPacket value too? */ + admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval, + &ahcd->regs->fminterval); +#else + u32 fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT; + + /* TODO: adjust FSLargestDataPacket value too? */ + admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval, + &ahcd->regs->fminterval); +#endif +} + +static inline u32 admhc_read_rhdesc(struct admhcd *ahcd) +{ + return admhc_readl(ahcd, &ahcd->regs->rhdesc); +} + +static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port) +{ + return admhc_readl(ahcd, &ahcd->regs->portstatus[port]); +} + +static inline void admhc_write_portstatus(struct admhcd *ahcd, int port, + u32 value) +{ + admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]); +} + +static inline void roothub_write_status(struct admhcd *ahcd, u32 value) +{ + /* FIXME: read-only bits must be masked out */ + admhc_writel(ahcd, value, &ahcd->regs->rhdesc); +} + +static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints) +{ + u32 t; + + t = admhc_readl(ahcd, &ahcd->regs->int_enable); + t &= ~(ints); + admhc_writel(ahcd, t, &ahcd->regs->int_enable); + /* TODO: flush writes ?*/ +} + +static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints) +{ + u32 t; + + t = admhc_readl(ahcd, &ahcd->regs->int_enable); + t |= ints; + admhc_writel(ahcd, t, &ahcd->regs->int_enable); + /* TODO: flush writes ?*/ +} + +static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints) +{ + admhc_writel(ahcd, ints, &ahcd->regs->int_status); +} + +static inline void admhc_dma_enable(struct admhcd *ahcd) +{ + u32 t; + + t = admhc_readl(ahcd, &ahcd->regs->host_control); + if (t & ADMHC_HC_DMAE) + return; + + t |= ADMHC_HC_DMAE; + admhc_writel(ahcd, t, &ahcd->regs->host_control); + admhc_vdbg(ahcd, "DMA enabled\n"); +} + +static inline void admhc_dma_disable(struct admhcd *ahcd) +{ + u32 t; + + t = admhc_readl(ahcd, &ahcd->regs->host_control); + if (!(t & ADMHC_HC_DMAE)) + return; + + t &= ~ADMHC_HC_DMAE; + admhc_writel(ahcd, t, &ahcd->regs->host_control); + admhc_vdbg(ahcd, "DMA disabled\n"); +} diff --git a/target/linux/adm5120/files-3.18/drivers/watchdog/adm5120_wdt.c b/target/linux/adm5120/files-3.18/drivers/watchdog/adm5120_wdt.c new file mode 100644 index 0000000..d5d63b2 --- /dev/null +++ b/target/linux/adm5120/files-3.18/drivers/watchdog/adm5120_wdt.c @@ -0,0 +1,202 @@ +/* + * ADM5120_WDT 0.01: Infineon ADM5120 SoC watchdog driver + * Copyright (c) Ondrej Zajicek , 2007 + * + * based on + * + * RC32434_WDT 0.01: IDT Interprise 79RC32434 watchdog driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define DEFAULT_TIMEOUT 15 /* (secs) Default is 15 seconds */ +#define MAX_TIMEOUT 327 +/* Max is 327 seconds, counter is 15-bit integer, step is 10 ms */ + +#define NAME "adm5120_wdt" +#define VERSION "0.1" + +static int expect_close; +static int access; +static unsigned int timeout = DEFAULT_TIMEOUT; + +static int nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_LICENSE("GPL"); + + +static inline void wdt_set_timeout(void) +{ + u32 val = (1 << 31) | (((timeout * 100) & 0x7FFF) << 16); + SW_WRITE_REG(SWITCH_REG_WDOG0, val); +} + +/* + It looks like WDOG0-register-write don't modify counter, + but WDOG0-register-read resets counter. +*/ + +static inline void wdt_reset_counter(void) +{ + SW_READ_REG(SWITCH_REG_WDOG0); +} + +static inline void wdt_disable(void) +{ + SW_WRITE_REG(SWITCH_REG_WDOG0, 0x7FFF0000); +} + + + +static int wdt_open(struct inode *inode, struct file *file) +{ + /* Allow only one person to hold it open */ + if (access) + return -EBUSY; + + if (nowayout) + __module_get(THIS_MODULE); + + /* Activate timer */ + wdt_reset_counter(); + wdt_set_timeout(); + printk(KERN_INFO NAME ": enabling watchdog timer\n"); + access = 1; + return 0; +} + +static int wdt_release(struct inode *inode, struct file *file) +{ + /* + * Shut off the timer. + * Lock it in if it's a module and we set nowayout + */ + if (expect_close && (nowayout == 0)) { + wdt_disable(); + printk(KERN_INFO NAME ": disabling watchdog timer\n"); + module_put(THIS_MODULE); + } else + printk(KERN_CRIT NAME ": device closed unexpectedly. WDT will not stop!\n"); + + access = 0; + return 0; +} + +static ssize_t wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) +{ + /* Refresh the timer. */ + if (len) { + if (!nowayout) { + size_t i; + + /* In case it was set long ago */ + expect_close = 0; + + for (i = 0; i != len; i++) { + char c; + if (get_user(c, data + i)) + return -EFAULT; + if (c == 'V') + expect_close = 1; + } + } + wdt_reset_counter(); + return len; + } + return 0; +} + +static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int new_timeout; + static struct watchdog_info ident = { + .options = WDIOF_SETTIMEOUT | + WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE, + .firmware_version = 0, + .identity = "ADM5120_WDT Watchdog", + }; + switch (cmd) { + default: + return -ENOTTY; + case WDIOC_GETSUPPORT: + if (copy_to_user((struct watchdog_info *)arg, &ident, sizeof(ident))) + return -EFAULT; + return 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, (int *)arg); + case WDIOC_KEEPALIVE: + wdt_reset_counter(); + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, (int *)arg)) + return -EFAULT; + if (new_timeout < 1) + return -EINVAL; + if (new_timeout > MAX_TIMEOUT) + return -EINVAL; + timeout = new_timeout; + wdt_set_timeout(); + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(timeout, (int *)arg); + } +} + +static const struct file_operations wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = wdt_write, + .unlocked_ioctl = wdt_ioctl, + .open = wdt_open, + .release = wdt_release, +}; + +static struct miscdevice wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &wdt_fops, +}; + +static char banner[] __initdata = KERN_INFO NAME ": Watchdog Timer version " VERSION "\n"; + +static int __init watchdog_init(void) +{ + int ret; + + ret = misc_register(&wdt_miscdev); + + if (ret) + return ret; + + wdt_disable(); + printk(banner); + + return 0; +} + +static void __exit watchdog_exit(void) +{ + misc_deregister(&wdt_miscdev); +} + +module_init(watchdog_init); +module_exit(watchdog_exit); diff --git a/target/linux/adm5120/image/Makefile b/target/linux/adm5120/image/Makefile new file mode 100644 index 0000000..4ca4d48 --- /dev/null +++ b/target/linux/adm5120/image/Makefile @@ -0,0 +1,112 @@ +# +# Copyright (C) 2006-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +LOADER_MAKE := $(NO_TRACE_MAKE) -C lzma-loader KDIR=$(KDIR) +JFFS2BLOCK := $(KDIR)/jffs2.block +JFFS2MARK := $(KDIR)/jffs2.mark + +define imgname +$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(patsubst jffs2-%,jffs2,$(1)) +endef + +VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux +fs_squash:=squashfs-only +fs_all:=all +fs_4k:=4k +fs_64k:=64k +fs_128k:=128k + +define Build/Clean + $(LOADER_MAKE) clean +endef + +define Image/Prepare + cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma + rm -f $(JFFS2BLOCK) + touch $(JFFS2BLOCK) + $(call prepare_generic_squashfs,$(JFFS2BLOCK)) + rm -f $(JFFS2MARK) + touch $(JFFS2MARK) + $(call add_jffs2_mark,$(JFFS2MARK)) +endef + +define Image/Build/Loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) LOADER_DATA="" \ + LZMA_TEXT_START=$(3) LZMA_STARTUP_ORG=$(4) \ + CONFIG_PASS_KARGS=$(5) CONFIG_BOARD=$(6) \ + compile loader.$(2) +endef + +define Image/Build/LZMAKernel + $(LOADER_MAKE) TARGET_DIR=$(BIN_DIR) \ + LOADER=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-ramfs.$(2) \ + LOADER_DATA=$(KDIR)/vmlinux.lzma \ + LZMA_TEXT_START=$(3) LZMA_STARTUP_ORG=$(4) \ + CONFIG_PASS_KARGS=$(5) CONFIG_BOARD=$(6) \ + compile loader.$(2) +endef + +define Image/Build/LZMAKernel/Generic + $(call Image/Build/LZMAKernel,$(1),$(2),0x80500000,0) +endef + +define Image/Build/LZMAKernel/Admboot + $(call Image/Build/LZMAKernel,$(1),$(2),0x80500000,0x6D8,y,$(1)) +endef + +define Image/Build/LZMAKernel/Cellvision + $(call Image/Build/LZMAKernel,$(1),$(3),0x80500000,0x6D8,y,$(2)) +endef + +define Image/Build/LZMAKernel/KArgs + $(call Image/Build/LZMAKernel,$(1),$(2),0x80500000,0,y,$(1)) +endef + +define trxalign/jffs2-128k +-a 0x20000 -f $(KDIR)/root.jffs2-128k +endef + +define trxalign/jffs2-64k +-a 0x10000 -f $(KDIR)/root.jffs2-64k +endef + +define trxalign/squashfs +-a 1024 -f $(KDIR)/root.squashfs -a 0x10000 -A $(JFFS2BLOCK) +endef + +define Image/Build/TRX + $(STAGING_DIR_HOST)/bin/trx -o $(1) -f $(3) -f $(KDIR)/vmlinux.lzma \ + $(call trxalign/$(2)) +endef + +define Image/Build/TRXNoloader + $(STAGING_DIR_HOST)/bin/trx -o $(1) -f $(KDIR)/vmlinux.lzma \ + $(call trxalign/$(2)) +endef + +include $(SUBTARGET).mk + +define Image/Build + $(call Image/Build/Profile/$(PROFILE),$(1)) +endef + +define Image/Build/Initramfs + $(call Image/Build/Profile/$(PROFILE),Initramfs) +endef + +define Image/BuildKernel + cp $(KDIR)/vmlinux.elf $(VMLINUX).elf + cp $(KDIR)/vmlinux $(VMLINUX).bin +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + cp $(KDIR)/vmlinux-initramfs.elf $(VMLINUX)-initramfs.elf + cp $(KDIR)/vmlinux $(VMLINUX)-initramfs.bin +endif +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/adm5120/image/lzma-loader/Makefile b/target/linux/adm5120/image/lzma-loader/Makefile new file mode 100644 index 0000000..36dfd09 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/Makefile @@ -0,0 +1,62 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +LOADER := loader.bin +LOADER_NAME := $(basename $(notdir $(LOADER))) +LOADER_DATA := +TARGET_DIR := + +ifeq ($(TARGET_DIR),) +TARGET_DIR := $(KDIR) +endif + +LOADER_BIN := $(TARGET_DIR)/$(LOADER_NAME).bin +LOADER_GZ := $(TARGET_DIR)/$(LOADER_NAME).gz +LOADER_ELF := $(TARGET_DIR)/$(LOADER_NAME).elf + +LZMA_STARTUP_ORG:= 0 +LZMA_TEXT_START := 0x80300000 + +PKG_NAME := lzma-loader +PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME) + +.PHONY : loader-compile loader.bin loader.elf loader.gz + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +loader-compile: $(PKG_BUILD_DIR)/.prepared + $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \ + LZMA_STARTUP_ORG=$(LZMA_STARTUP_ORG) \ + LZMA_TEXT_START=$(LZMA_TEXT_START) \ + LOADER_DATA=$(LOADER_DATA) \ + CONFIG_BOARD=$(CONFIG_BOARD) \ + CONFIG_PASS_KARGS=$(CONFIG_PASS_KARGS) \ + clean all + +loader.gz: $(PKG_BUILD_DIR)/loader.bin + gzip -nc9 $< > $(LOADER_GZ) + +loader.elf: $(PKG_BUILD_DIR)/loader.elf + $(CP) $< $(LOADER_ELF) + +loader.bin: $(PKG_BUILD_DIR)/loader.bin + $(CP) $< $(LOADER_BIN) + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: loader-compile + +install: + +clean: + rm -rf $(PKG_BUILD_DIR) + diff --git a/target/linux/adm5120/image/lzma-loader/src/LzmaDecode.c b/target/linux/adm5120/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 0000000..cb83453 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,584 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \ + BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + return LZMA_RESULT_DATA_ERROR; + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/adm5120/image/lzma-loader/src/LzmaDecode.h b/target/linux/adm5120/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 0000000..2870eeb --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,113 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +#include "LzmaTypes.h" + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb UInt16 +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/target/linux/adm5120/image/lzma-loader/src/LzmaTypes.h b/target/linux/adm5120/image/lzma-loader/src/LzmaTypes.h new file mode 100644 index 0000000..9c27290 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/LzmaTypes.h @@ -0,0 +1,45 @@ +/* +LzmaTypes.h + +Types for LZMA Decoder + +This file written and distributed to public domain by Igor Pavlov. +This file is part of LZMA SDK 4.40 (2006-05-01) +*/ + +#ifndef __LZMATYPES_H +#define __LZMATYPES_H + +#ifndef _7ZIP_BYTE_DEFINED +#define _7ZIP_BYTE_DEFINED +typedef unsigned char Byte; +#endif + +#ifndef _7ZIP_UINT16_DEFINED +#define _7ZIP_UINT16_DEFINED +typedef unsigned short UInt16; +#endif + +#ifndef _7ZIP_UINT32_DEFINED +#define _7ZIP_UINT32_DEFINED +#ifdef _LZMA_UINT32_IS_ULONG +typedef unsigned long UInt32; +#else +typedef unsigned int UInt32; +#endif +#endif + +/* #define _LZMA_NO_SYSTEM_SIZE_T */ +/* You can use it, if you don't want */ + +#ifndef _7ZIP_SIZET_DEFINED +#define _7ZIP_SIZET_DEFINED +#ifdef _LZMA_NO_SYSTEM_SIZE_T +typedef UInt32 SizeT; +#else +#include +typedef size_t SizeT; +#endif +#endif + +#endif diff --git a/target/linux/adm5120/image/lzma-loader/src/Makefile b/target/linux/adm5120/image/lzma-loader/src/Makefile new file mode 100644 index 0000000..f23d040 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/Makefile @@ -0,0 +1,99 @@ +# +# Makefile for Broadcom BCM947XX boards +# +# Copyright 2001-2003, Broadcom Corporation +# All Rights Reserved. +# +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. +# +# Copyright 2004 Manuel Novoa III +# Modified to support bzip'd kernels. +# Of course, it would be better to integrate bunzip capability into CFE. +# +# Copyright 2005 Oleg I. Vdovikin +# Cleaned up, modified for lzma support, removed from kernel +# +# Copyright 2007 Gabor Juhos +# Modified to support user defined entry point address. +# Added support for make targets with different names +# + +LOADADDR := 0x80001000 +LZMA_TEXT_START := 0x80500000 +LZMA_STARTUP_ORG:= 0 +LOADER_DATA := +CONFIG_PASS_KARGS := +CONFIG_BOARD := + +CC := $(CROSS_COMPILE)gcc +LD := $(CROSS_COMPILE)ld +OBJCOPY := $(CROSS_COMPILE)objcopy +OBJDUMP := $(CROSS_COMPILE)objdump + +BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug -S + +CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic \ + -ffunction-sections -pipe -mlong-calls -fno-common -ffreestanding \ + -fhonour-copts \ + -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap +CFLAGS += -DLOADADDR=$(LOADADDR) -D_LZMA_PROB32 + +ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ -DLZMA_STARTUP_ORG=$(LZMA_STARTUP_ORG) + +LDFLAGS = -static --gc-sections -no-warn-mismatch +LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START) + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +OBJECTS := head.o decompress.o board.o printf.o LzmaDecode.o + +ifneq ($(strip $(LOADER_DATA)),) +OBJECTS += data.o +CFLAGS += -DLZMA_WRAPPER=1 +else +CFLAGS += -D_LZMA_IN_CB +endif + +ifneq ($(strip $(CONFIG_PASS_KARGS)),) +CFLAGS += -DCONFIG_PASS_KARGS +endif + +BOARD_DEF := $(strip $(CONFIG_BOARD)) +BOARD_DEF := $(shell echo $(BOARD_DEF) | tr a-z A-Z | tr -d -) +ifneq ($(BOARD_DEF),) +CFLAGS += -DCONFIG_BOARD_$(BOARD_DEF) +endif + +all: loader.bin + +# Don't build dependencies, this may die if $(CC) isn't gcc +dep: + +install: + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $< + +%.o : %.S + $(CC) $(ASFLAGS) -c -o $@ $< + +data.o: $(LOADER_DATA) + $(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $< + +loader.bin: loader.elf + $(OBJCOPY) $(BIN_FLAGS) $< $@ + +loader.elf: $(OBJECTS) + $(LD) $(LDFLAGS) -o $@ $(OBJECTS) + +mrproper: clean + +clean: + rm -f *.elf *.bin *.o + + + diff --git a/target/linux/adm5120/image/lzma-loader/src/README b/target/linux/adm5120/image/lzma-loader/src/README new file mode 100644 index 0000000..16649e9 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/README @@ -0,0 +1,55 @@ +/* + * LZMA compressed kernel decompressor for bcm947xx boards + * + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +The code is intended to decompress kernel, being compressed using lzma utility +build using 7zip LZMA SDK. This utility is located in the LZMA_Alone directory + +decompressor code expects that your .trx file consist of three partitions: + +1) decompressor itself (this is gziped code which pmon/cfe will extract and run +on boot-up instead of real kernel) +2) LZMA compressed kernel (both streamed and regular modes are supported now) +3) Root filesystem + +Please be sure to apply the following patch for use this new trx layout (it will +allow using both new and old trx files for root filesystem lookup code) + +--- linuz/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:24:27.503322896 +0300 ++++ linux/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:29:05.237100944 +0300 +@@ -221,7 +221,9 @@ + /* Try looking at TRX header for rootfs offset */ + if (le32_to_cpu(trx->magic) == TRX_MAGIC) { + bcm947xx_parts[1].offset = off; +- if (le32_to_cpu(trx->offsets[1]) > off) ++ if (le32_to_cpu(trx->offsets[2]) > off) ++ off = le32_to_cpu(trx->offsets[2]); ++ else if (le32_to_cpu(trx->offsets[1]) > off) + off = le32_to_cpu(trx->offsets[1]); + continue; + } + + +Revision history: + 0.02 Initial release + 0.03 Added Mineharu Takahara patch to pass actual + output size to decoder (stream mode compressed input is not + a requirement anymore) + 0.04 Reordered functions using lds script diff --git a/target/linux/adm5120/image/lzma-loader/src/board.c b/target/linux/adm5120/image/lzma-loader/src/board.c new file mode 100644 index 0000000..5ebdbc3 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/board.c @@ -0,0 +1,185 @@ +/* + * ADM5120 specific board support for LZMA decompressor + * + * Copyright (C) 2007-2008 OpenWrt.org + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "config.h" +#include + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +/* + * INTC definitions + */ +#define INTC_BASE 0xB2200000 + +/* INTC registers */ +#define INTC_REG_IRQ_DISABLE 0x0C + +/* + * UART definitions + */ +#define UART0_BASE 0xB2600000 +#define UART1_BASE 0xB2800000 +/* UART registers */ +#define UART_REG_DATA 0x00 /* Data register */ +#define UART_REG_ECR 0x04 /* Error Clear register */ +#define UART_REG_LCRH 0x08 /* Line Control High register */ +#define UART_REG_LCRM 0x0C /* Line Control Middle register */ +#define UART_REG_LCRL 0x10 /* Line Control Low register */ +#define UART_REG_CTRL 0x14 /* Control register */ +#define UART_REG_FLAG 0x18 /* Flag register */ + +/* Control register bits */ +#define UART_CTRL_EN ( 1 << 0 ) /* UART enable */ + +/* Line Control High register bits */ +#define UART_LCRH_FEN ( 1 << 4 ) /* FIFO enable */ + +/* Flag register bits */ +#define UART_FLAG_CTS ( 1 << 0 ) +#define UART_FLAG_DSR ( 1 << 1 ) +#define UART_FLAG_DCD ( 1 << 2 ) +#define UART_FLAG_BUSY ( 1 << 3 ) +#define UART_FLAG_RXFE ( 1 << 4 ) /* RX FIFO empty */ +#define UART_FLAG_TXFF ( 1 << 5 ) /* TX FIFO full */ +#define UART_FLAG_RXFF ( 1 << 6 ) /* RX FIFO full */ +#define UART_FLAG_TXFE ( 1 << 7 ) /* TX FIFO empty */ + +/* + * SWITCH definitions + */ +#define SWITCH_BASE 0xB2000000 + +#define SWITCH_REG_CPUP_CONF 0x0024 +#define SWITCH_REG_PORT_CONF0 0x0028 + +#define SWITCH_REG_GPIO_CONF0 0x00B8 +#define SWITCH_REG_GPIO_CONF2 0x00BC + +#define SWITCH_REG_PORT0_LED 0x0100 +#define SWITCH_REG_PORT1_LED 0x0104 +#define SWITCH_REG_PORT2_LED 0x0108 +#define SWITCH_REG_PORT3_LED 0x010C +#define SWITCH_REG_PORT4_LED 0x0110 + +#define SWITCH_PORTS_HW 0x3F /* Hardware Ports */ + +/* CPUP_CONF register bits */ +#define CPUP_CONF_DCPUP ( 1 << 0 ) /* Disable CPU port */ + +/* PORT_CONF0 register bits */ +#define PORT_CONF0_DP_SHIFT 0 /* disable port shift*/ + + +/* + * UART routines + */ + +#if defined(CONFIG_USE_UART0) +# define UART_READ(r) READREG(UART0_BASE+(r)) +# define UART_WRITE(r,v) WRITEREG(UART0_BASE+(r),(v)) +#else +# define UART_READ(r) READREG(UART1_BASE+(r)) +# define UART_WRITE(r,v) WRITEREG(UART1_BASE+(r),(v)) +#endif + +static void uart_init(void) +{ +#if 0 + unsigned int t; + + /* disable uart */ + UART_WRITE(UART_REG_CTRL, 0); + + /* keep current baud rate */ + t = UART_READ(UART_REG_LCRM); + UART_WRITE(UART_REG_LCRM, t); + t = UART_READ(UART_REG_LCRL); + UART_WRITE(UART_REG_LCRL, t); + + /* keep data, stop, and parity bits, but disable FIFO */ + t = UART_READ(UART_REG_LCRH); + t &= ~(UART_LCRH_FEN); + UART_WRITE(UART_REG_LCRH, t ); + + /* clear error bits */ + UART_WRITE(UART_REG_ECR, 0xFF); + + /* enable uart, and disable interrupts */ + UART_WRITE(UART_REG_CTRL, UART_CTRL_EN); +#endif +} + +/* + * INTC routines + */ + +#define INTC_READ(r) READREG(INTC_BASE+(r)) +#define INTC_WRITE(r,v) WRITEREG(INTC_BASE+(r),v) + +static void intc_init(void) +{ + INTC_WRITE(INTC_REG_IRQ_DISABLE, 0xFFFFFFFF); +} + +/* + * SWITCH routines + */ + +#define SWITCH_READ(r) READREG(SWITCH_BASE+(r)) +#define SWITCH_WRITE(r,v) WRITEREG(SWITCH_BASE+(r),v) + +static void switch_init(void) +{ + /* disable PHYS ports */ + SWITCH_WRITE(SWITCH_REG_PORT_CONF0, + (SWITCH_PORTS_HW << PORT_CONF0_DP_SHIFT)); + + /* disable CPU port */ + SWITCH_WRITE(SWITCH_REG_CPUP_CONF, CPUP_CONF_DCPUP); + + /* disable GPIO lines */ + SWITCH_WRITE(SWITCH_REG_GPIO_CONF0, 0); + SWITCH_WRITE(SWITCH_REG_GPIO_CONF2, 0); + + /* disable LED lines */ + SWITCH_WRITE(SWITCH_REG_PORT0_LED, 0); + SWITCH_WRITE(SWITCH_REG_PORT1_LED, 0); + SWITCH_WRITE(SWITCH_REG_PORT2_LED, 0); + SWITCH_WRITE(SWITCH_REG_PORT3_LED, 0); + SWITCH_WRITE(SWITCH_REG_PORT4_LED, 0); +} + +void board_putc(int ch) +{ + while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0); + + UART_WRITE(UART_REG_DATA, ch); + + while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0); +} + +void board_init(void) +{ + intc_init(); + switch_init(); + uart_init(); +} diff --git a/target/linux/adm5120/image/lzma-loader/src/config.h b/target/linux/adm5120/image/lzma-loader/src/config.h new file mode 100644 index 0000000..e5511d1 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/config.h @@ -0,0 +1,143 @@ +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#define FLASH_2M (2<<20) +#define FLASH_4M (4<<20) + +/* + * Cellvision/SparkLAN boards + */ + +#if defined(CONFIG_BOARD_CAS630) +# define CONFIG_BOARD_NAME "CAS-630" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_CAS670) +# define CONFIG_BOARD_NAME "CAS-670" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_CAS700) +# define CONFIG_BOARD_NAME "CAS-700" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_CAS790) +# define CONFIG_BOARD_NAME "CAS-790" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_CAS771) +# define CONFIG_BOARD_NAME "CAS-771" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_CAS861) +# define CONFIG_BOARD_NAME "CAS-861" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_NFS101U) +# define CONFIG_BOARD_NAME "NFS-101U" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_NFS202U) +# define CONFIG_BOARD_NAME "NFS-202U" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +/* + * Compex boards + */ +#if defined(CONFIG_BOARD_WP54GWRT) +# define CONFIG_BOARD_NAME "WP54G-WRT" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +/* + * Edimax boards + */ +#if defined(CONFIG_BOARD_BR6104K) +# define CONFIG_BOARD_NAME "BR-6104K" +# define CONFIG_FLASH_SIZE FLASH_2M +#endif + +#if defined(CONFIG_BOARD_BR6104KP) +# define CONFIG_BOARD_NAME "BR-6104KP" +# define CONFIG_FLASH_SIZE FLASH_2M +#endif + +#if defined(CONFIG_BOARD_BR6104WG) +# define CONFIG_BOARD_NAME "BR-6104WG" +# define CONFIG_FLASH_SIZE FLASH_2M +#endif + +/* + * Infineon boards + */ +#if defined(CONFIG_BOARD_EASY5120PATA) +# define CONFIG_BOARD_NAME "EASY 5120P-ATA" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_EASY5120RT) +# define CONFIG_BOARD_NAME "EASY 5120-RT" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_EASY5120WVOIP) +# define CONFIG_BOARD_NAME "EASY 5120-WVOIP" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_EASY83000) +# define CONFIG_BOARD_NAME "EASY 83000" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +/* + * Motorola boards + */ +#if defined(CONFIG_BOARD_POWERLINEMUGW) +# define CONFIG_BOARD_NAME "Powerline MU Gateway" +# define CONFIG_USE_UART1 1 +#endif + +/* + * OSBRiDGE boards + */ +#if defined(CONFIG_BOARD_5GXI) +# define CONFIG_BOARD_NAME "OSBRiDGE 5GXi" +#endif + +/* + * ZyXEL boards + */ +#if defined(CONFIG_BOARD_P334WT) +# define CONFIG_BOARD_NAME "P-334WT" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +#if defined(CONFIG_BOARD_P335) +# define CONFIG_BOARD_NAME "P-335" +# define CONFIG_FLASH_SIZE FLASH_4M +#endif + +/* + * Default values + */ +#ifndef CONFIG_BOARD_NAME +# define CONFIG_BOARD_NAME "ADM5120" +#endif + +#ifndef CONFIG_FLASH_SIZE +# define CONFIG_FLASH_SIZE FLASH_2M +#endif + +#if !defined(CONFIG_USE_UART0) && !defined(CONFIG_USE_UART1) +# define CONFIG_USE_UART0 +#endif + +#endif /* _CONFIG_H_ */ diff --git a/target/linux/adm5120/image/lzma-loader/src/decompress.c b/target/linux/adm5120/image/lzma-loader/src/decompress.c new file mode 100644 index 0000000..cd4b8fa --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/decompress.c @@ -0,0 +1,353 @@ +/* + * + * LZMA compressed kernel decompressor for ADM5120 boards + * + * Copyright (C) 2005 by Oleg I. Vdovikin + * Copyright (C) 2007-2008 OpenWrt.org + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * Please note, this was code based on the bunzip2 decompressor code + * by Manuel Novoa III (mjn3@codepoet.org), although the only thing left + * is an idea and part of original vendor code + * + * + * 12-Mar-2005 Mineharu Takahara + * pass actual output size to decoder (stream mode + * compressed input is not a requirement anymore) + * + * 24-Apr-2005 Oleg I. Vdovikin + * reordered functions using lds script, removed forward decl + * + * 24-Mar-2007 Gabor Juhos + * pass original values of the a0,a1,a2,a3 registers to the kernel + * + * 19-May-2007 Gabor Juhos + * endiannes related cleanups + * add support for decompressing an embedded kernel + * + */ + +#include + +#include "config.h" +#include "printf.h" +#include "LzmaDecode.h" + +#define ADM5120_FLASH_START 0x1fc00000 /* Flash start */ +#define ADM5120_FLASH_END 0x1fe00000 /* Flash end */ + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) + +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 + +#define cache_unroll(base,op) \ + __asm__ __volatile__( \ + ".set noreorder;\n" \ + ".set mips3;\n" \ + "cache %1, (%0);\n" \ + ".set mips0;\n" \ + ".set reorder\n" \ + : \ + : "r" (base), \ + "i" (op)); + +#ifdef LZMA_DEBUG +# define DBG(f, a...) printf(f, ## a) +#else +# define DBG(f, a...) do {} while (0) +#endif + +static __inline__ void blast_icache(unsigned long size, unsigned long lsize) +{ + unsigned long start = KSEG0; + unsigned long end = (start + size); + + while(start < end) { + cache_unroll(start,Index_Invalidate_I); + start += lsize; + } +} + +static __inline__ void blast_dcache(unsigned long size, unsigned long lsize) +{ + unsigned long start = KSEG0; + unsigned long end = (start + size); + + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_D); + start += lsize; + } +} + +#define TRX_MAGIC 0x30524448 /* "HDR0" */ +#define TRX_ALIGN 0x1000 + +struct trx_header { + unsigned int magic; /* "HDR0" */ + unsigned int len; /* Length of file including header */ + unsigned int crc32; /* 32-bit CRC from flag_version to end of file */ + unsigned int flag_version; /* 0:15 flags, 16:31 version */ + unsigned int offsets[3]; /* Offsets of partitions from start of header */ +}; + +struct env_var { + char *name; + char *value; +}; + +/* beyound the image end, size not known in advance */ +extern unsigned char workspace[]; +extern void board_init(void); + +static CLzmaDecoderState lzma_state; + +typedef void (*kernel_entry)(unsigned long reg_a0, unsigned long reg_a1, + unsigned long reg_a2, unsigned long reg_a3); + +static int decompress_data(CLzmaDecoderState *vs, unsigned char *outStream, + UInt32 outSize); + +#ifdef CONFIG_PASS_KARGS +#define ENVV(n,v) {.name = (n), .value = (v)} +struct env_var env_vars[] = { + ENVV("board_name", CONFIG_BOARD_NAME), + ENVV(NULL, NULL) +}; +#endif + +static void halt(void) +{ + printf("\nSystem halted!\n"); + for(;;); +} + +#if (LZMA_WRAPPER) +extern unsigned char _lzma_data_start[]; +extern unsigned char _lzma_data_end[]; + +unsigned char *data; +unsigned long datalen; + +static __inline__ unsigned char get_byte(void) +{ + datalen--; + return *data++; +} + +static void decompress_init(void) +{ + data = _lzma_data_start; + datalen = _lzma_data_end - _lzma_data_start; +} + +static int decompress_data(CLzmaDecoderState *vs, unsigned char *outStream, + SizeT outSize) +{ + SizeT ip, op; + + return LzmaDecode(vs, data, datalen, &ip, outStream, outSize, &op); +} +#endif /* LZMA_WRAPPER */ + +#if !(LZMA_WRAPPER) + +#define FLASH_BANK_SIZE (2<<20) + +static unsigned char *flash_base = (unsigned char *) KSEG1ADDR(ADM5120_FLASH_START); +static unsigned long flash_ofs = 0; +static unsigned long flash_max = 0; +static unsigned long flash_ofs_mask = (FLASH_BANK_SIZE-1); + +static __inline__ unsigned char get_byte(void) +{ + return *(flash_base+flash_ofs++); +} + +static int lzma_read_byte(void *object, const unsigned char **buffer, + SizeT *bufferSize) +{ + unsigned long len; + + if (flash_ofs >= flash_max) + return LZMA_RESULT_DATA_ERROR; + + len = flash_max-flash_ofs; + +#if (CONFIG_FLASH_SIZE > FLASH_BANK_SIZE) + if (flash_ofs < FLASH_BANK_SIZE) { + /* switch to bank 0 */ + DBG("lzma_read_byte: switch to bank 0\n"); + + if (len > FLASH_BANK_SIZE-flash_ofs) + len = FLASH_BANK_SIZE-flash_ofs; + } else { + /* switch to bank 1 */ + DBG("lzma_read_byte: switch to bank 1\n"); + } +#endif + DBG("lzma_read_byte: ofs=%08X, len=%08X\n", flash_ofs, len); + + *buffer = flash_base+(flash_ofs & flash_ofs_mask); + *bufferSize = len; + flash_ofs += len; + + return LZMA_RESULT_OK; +} + +static ILzmaInCallback lzma_callback = { + .Read = lzma_read_byte, +}; + +static __inline__ unsigned int read_le32(void *buf) +{ + unsigned char *p = buf; + + return ((unsigned int)p[0] + ((unsigned int)p[1] << 8) + + ((unsigned int)p[2] << 16) +((unsigned int)p[3] << 24)); +} + +static void decompress_init(void) +{ + struct trx_header *hdr = NULL; + unsigned long kofs,klen; + + printf("Looking for TRX header... "); + /* look for trx header, 32-bit data access */ + for (flash_ofs = 0; flash_ofs < FLASH_BANK_SIZE; flash_ofs += TRX_ALIGN) { + if (read_le32(&flash_base[flash_ofs]) == TRX_MAGIC) { + hdr = (struct trx_header *)&flash_base[flash_ofs]; + break; + } + } + + if (hdr == NULL) { + printf("not found!\n"); + /* no compressed kernel found, halting */ + halt(); + } + + /* compressed kernel is in the partition 0 or 1 */ + kofs = read_le32(&hdr->offsets[1]); + if (kofs == 0 || kofs > 65536) { + klen = kofs-read_le32(&hdr->offsets[0]); + kofs = read_le32(&hdr->offsets[0]); + } else { + klen = read_le32(&hdr->offsets[2]); + if (klen > kofs) + klen -= kofs; + else + klen = read_le32(&hdr->len)-kofs; + } + + printf("found at %08X, kernel:%08X len:%08X\n", flash_ofs, + kofs, klen); + + flash_ofs += kofs; + flash_max = flash_ofs+klen; +} + +static int decompress_data(CLzmaDecoderState *vs, unsigned char *outStream, + SizeT outSize) +{ + SizeT op; + +#if 0 + vs->Buffer = data; + vs->BufferLim = datalen; +#endif + + return LzmaDecode(vs, &lzma_callback, outStream, outSize, &op); +} +#endif /* !(LZMA_WRAPPER) */ + +/* should be the first function */ +void decompress_entry(unsigned long reg_a0, unsigned long reg_a1, + unsigned long reg_a2, unsigned long reg_a3, + unsigned long icache_size, unsigned long icache_lsize, + unsigned long dcache_size, unsigned long dcache_lsize) +{ + unsigned char props[LZMA_PROPERTIES_SIZE]; + unsigned int i; /* temp value */ + SizeT osize; /* uncompressed size */ + int res; + + board_init(); + + printf("\n\nLZMA loader for " CONFIG_BOARD_NAME + ", Copyright (C) 2007-2008 OpenWrt.org\n\n"); + + decompress_init(); + + /* lzma args */ + for (i = 0; i < LZMA_PROPERTIES_SIZE; i++) + props[i] = get_byte(); + + /* skip rest of the LZMA coder property */ + /* read the lower half of uncompressed size in the header */ + osize = ((SizeT)get_byte()) + + ((SizeT)get_byte() << 8) + + ((SizeT)get_byte() << 16) + + ((SizeT)get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + for (i = 0; i < 4; i++) + get_byte(); + + res = LzmaDecodeProperties(&lzma_state.Properties, props, + LZMA_PROPERTIES_SIZE); + if (res != LZMA_RESULT_OK) { + printf("Incorrect LZMA stream properties!\n"); + halt(); + } + + printf("decompressing kernel... "); + + lzma_state.Probs = (CProb *)workspace; + res = decompress_data(&lzma_state, (unsigned char *)LOADADDR, osize); + + if (res != LZMA_RESULT_OK) { + printf("failed, "); + switch (res) { + case LZMA_RESULT_DATA_ERROR: + printf("data error!\n"); + break; + default: + printf("unknown error %d!\n", res); + } + halt(); + } else + printf("done!\n"); + + blast_dcache(dcache_size, dcache_lsize); + blast_icache(icache_size, icache_lsize); + + printf("launching kernel...\n\n"); + +#ifdef CONFIG_PASS_KARGS + reg_a0 = 0; + reg_a1 = 0; + reg_a2 = (unsigned long)env_vars; + reg_a3 = 0; +#endif + /* Jump to load address */ + ((kernel_entry) LOADADDR)(reg_a0, reg_a1, reg_a2, reg_a3); +} diff --git a/target/linux/adm5120/image/lzma-loader/src/head.S b/target/linux/adm5120/image/lzma-loader/src/head.S new file mode 100644 index 0000000..ee8b320 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/head.S @@ -0,0 +1,209 @@ +/* Copyright 2007 Gabor Juhos */ +/* keep original values of the a0,a1,a2,a3 registers */ +/* modifed to support user defined entry point address */ +/* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su) */ +/* cache manipulation adapted from Broadcom code */ +/* idea taken from original bunzip2 decompressor code */ +/* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org) */ +/* Licensed under the linux kernel's version of the GPL.*/ + +#include +#include + +#define KSEG0 0x80000000 + +#define C0_STATUS $12 +#define C0_CAUSE $13 +#define C0_CONFIG $16 +#define C0_WATCHLO $18 +#define C0_WATCHHI $19 +#define C0_TAGLO $28 +#define C0_TAGHI $29 + +#define CONF1_DA_SHIFT 7 /* D$ associativity */ +#define CONF1_DA_MASK 0x00000380 +#define CONF1_DA_BASE 1 +#define CONF1_DL_SHIFT 10 /* D$ line size */ +#define CONF1_DL_MASK 0x00001c00 +#define CONF1_DL_BASE 2 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */ +#define CONF1_DS_MASK 0x0000e000 +#define CONF1_DS_BASE 64 +#define CONF1_IA_SHIFT 16 /* I$ associativity */ +#define CONF1_IA_MASK 0x00070000 +#define CONF1_IA_BASE 1 +#define CONF1_IL_SHIFT 19 /* I$ line size */ +#define CONF1_IL_MASK 0x00380000 +#define CONF1_IL_BASE 2 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */ +#define CONF1_IS_MASK 0x01c00000 +#define CONF1_IS_BASE 64 + +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 + + .text + +#if (LZMA_STARTUP_ORG) + .set noreorder + + b startup + nop + + .org LZMA_STARTUP_ORG +#endif + +LEAF(startup) + .set noreorder + .set mips32 + + mtc0 zero, C0_WATCHLO # clear watch registers + mtc0 zero, C0_WATCHHI + + mtc0 zero, C0_CAUSE # clear before writing status register + + mfc0 t0, C0_STATUS # get status register + li t1, ~(0xFF01) + and t0, t1 # mask interrupts + mtc0 t0, C0_STATUS # set up status register + + move t1, ra # save return address + la t0, __reloc_label # get linked address of label + bal __reloc_label # branch and link to label to + nop # get actual address +__reloc_label: + subu t0, ra, t0 # get reloc_delta + move ra, t1 # restore return address + + beqz t0, __reloc_end # if delta is 0 we are in the right place + nop + + /* Copy our code to the right place */ + la t1, _code_start # get linked address of _code_start + la t2, _code_end # get linked address of _code_end + addu t0, t0, t1 # calculate actual address of _code_start + +__reloc_copy: + lw t3, 0(t0) + sw t3, 0(t1) + add t1, 4 + blt t1, t2, __reloc_copy + add t0, 4 + +__reloc_end: + + /* At this point we need to invalidate dcache and */ + /* icache before jumping to new code */ + +1: /* Get cache sizes */ + .set mips32 + mfc0 s0,C0_CONFIG,1 + .set mips0 + + li s1,CONF1_DL_MASK + and s1,s0 + beq s1,zero,nodc + nop + + srl s1,CONF1_DL_SHIFT + li t0,CONF1_DL_BASE + sll s1,t0,s1 /* s1 has D$ cache line size */ + + li s2,CONF1_DA_MASK + and s2,s0 + srl s2,CONF1_DA_SHIFT + addiu s2,CONF1_DA_BASE /* s2 now has D$ associativity */ + + li t0,CONF1_DS_MASK + and t0,s0 + srl t0,CONF1_DS_SHIFT + li s3,CONF1_DS_BASE + sll s3,s3,t0 /* s3 has D$ sets per way */ + + multu s2,s3 /* sets/way * associativity */ + mflo t0 /* total cache lines */ + + multu s1,t0 /* D$ linesize * lines */ + mflo s2 /* s2 is now D$ size in bytes */ + + /* Initilize the D$: */ + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + li t0,KSEG0 /* Just an address for the first $ line */ + addu t1,t0,s2 /* + size of cache == end */ + + .set mips3 +1: cache Index_Writeback_Inv_D,0(t0) + .set mips0 + bne t0,t1,1b + addu t0,s1 + +nodc: + /* Now we get to do it all again for the I$ */ + + move s3,zero /* just in case there is no icache */ + move s4,zero + + li t0,CONF1_IL_MASK + and t0,s0 + beq t0,zero,noic + nop + + srl t0,CONF1_IL_SHIFT + li s3,CONF1_IL_BASE + sll s3,t0 /* s3 has I$ cache line size */ + + li t0,CONF1_IA_MASK + and t0,s0 + srl t0,CONF1_IA_SHIFT + addiu s4,t0,CONF1_IA_BASE /* s4 now has I$ associativity */ + + li t0,CONF1_IS_MASK + and t0,s0 + srl t0,CONF1_IS_SHIFT + li s5,CONF1_IS_BASE + sll s5,t0 /* s5 has I$ sets per way */ + + multu s4,s5 /* sets/way * associativity */ + mflo t0 /* s4 is now total cache lines */ + + multu s3,t0 /* I$ linesize * lines */ + mflo s4 /* s4 is cache size in bytes */ + + /* Initilize the I$: */ + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + li t0,KSEG0 /* Just an address for the first $ line */ + addu t1,t0,s4 /* + size of cache == end */ + + .set mips3 +1: cache Index_Invalidate_I,0(t0) + .set mips0 + bne t0,t1,1b + addu t0,s3 + +noic: + /* Setup new "C" stack */ + la sp, _stack + + addiu sp, -32 /* reserve stack for parameters */ +#if 0 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw a3, 12(sp) +#endif + sw s3, 16(sp) /* icache line size */ + sw s4, 20(sp) /* icache size */ + sw s1, 24(sp) /* dcache line size */ + sw s2, 28(sp) /* dcache size */ + + /* jump to the decompressor routine */ + la t0, decompress_entry + jr t0 + nop + + .set reorder +END(startup) diff --git a/target/linux/adm5120/image/lzma-loader/src/loader.lds b/target/linux/adm5120/image/lzma-loader/src/loader.lds new file mode 100644 index 0000000..bae70fb --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/loader.lds @@ -0,0 +1,29 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + _code_start = .; + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + . = ALIGN(16); + *(.data.lzma) + } + + .data : { + *(.data) + *(.data.*) + } + _code_end = .; + + .bss : { + *(.bss) + *(.bss.*) + } + + . = ALIGN(16); + . = . + 8192; + _stack = .; + + workspace = .; +} diff --git a/target/linux/adm5120/image/lzma-loader/src/lzma-data.lds b/target/linux/adm5120/image/lzma-loader/src/lzma-data.lds new file mode 100644 index 0000000..abf756b --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/lzma-data.lds @@ -0,0 +1,8 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .data.lzma : { + _lzma_data_start = .; + *(.data) + _lzma_data_end = .; + } +} diff --git a/target/linux/adm5120/image/lzma-loader/src/printf.c b/target/linux/adm5120/image/lzma-loader/src/printf.c new file mode 100644 index 0000000..7bb5a86 --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/printf.c @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "printf.h" + +extern void board_putc(int ch); + +/* this is the maximum width for a variable */ +#define LP_MAX_BUF 256 + +/* macros */ +#define IsDigit(x) ( ((x) >= '0') && ((x) <= '9') ) +#define Ctod(x) ( (x) - '0') + +/* forward declaration */ +static int PrintChar(char *, char, int, int); +static int PrintString(char *, char *, int, int); +static int PrintNum(char *, unsigned long, int, int, int, int, char, int); + +/* private variable */ +static const char theFatalMsg[] = "fatal error in lp_Print!"; + +/* -*- + * A low level printf() function. + */ +static void +lp_Print(void (*output)(void *, char *, int), + void * arg, + char *fmt, + va_list ap) +{ + +#define OUTPUT(arg, s, l) \ + { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \ + (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \ + } else { \ + (*output)(arg, s, l); \ + } \ + } + + char buf[LP_MAX_BUF]; + + char c; + char *s; + long int num; + + int longFlag; + int negFlag; + int width; + int prec; + int ladjust; + char padc; + + int length; + + for(;;) { + { + /* scan for the next '%' */ + char *fmtStart = fmt; + while ( (*fmt != '\0') && (*fmt != '%')) { + fmt ++; + } + + /* flush the string found so far */ + OUTPUT(arg, fmtStart, fmt-fmtStart); + + /* are we hitting the end? */ + if (*fmt == '\0') break; + } + + /* we found a '%' */ + fmt ++; + + /* check for long */ + if (*fmt == 'l') { + longFlag = 1; + fmt ++; + } else { + longFlag = 0; + } + + /* check for other prefixes */ + width = 0; + prec = -1; + ladjust = 0; + padc = ' '; + + if (*fmt == '-') { + ladjust = 1; + fmt ++; + } + + if (*fmt == '0') { + padc = '0'; + fmt++; + } + + if (IsDigit(*fmt)) { + while (IsDigit(*fmt)) { + width = 10 * width + Ctod(*fmt++); + } + } + + if (*fmt == '.') { + fmt ++; + if (IsDigit(*fmt)) { + prec = 0; + while (IsDigit(*fmt)) { + prec = prec*10 + Ctod(*fmt++); + } + } + } + + + /* check format flag */ + negFlag = 0; + switch (*fmt) { + case 'b': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'd': + case 'D': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + if (num < 0) { + num = - num; + negFlag = 1; + } + length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'o': + case 'O': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'u': + case 'U': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'x': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'X': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1); + OUTPUT(arg, buf, length); + break; + + case 'c': + c = (char)va_arg(ap, int); + length = PrintChar(buf, c, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case 's': + s = (char*)va_arg(ap, char *); + length = PrintString(buf, s, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case '\0': + fmt --; + break; + + default: + /* output this char as it is */ + OUTPUT(arg, fmt, 1); + } /* switch (*fmt) */ + + fmt ++; + } /* for(;;) */ + + /* special termination call */ + OUTPUT(arg, "\0", 1); +} + + +/* --------------- local help functions --------------------- */ +static int +PrintChar(char * buf, char c, int length, int ladjust) +{ + int i; + + if (length < 1) length = 1; + if (ladjust) { + *buf = c; + for (i=1; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-1; i++) buf[i] = ' '; + buf[length - 1] = c; + } + return length; +} + +static int +PrintString(char * buf, char* s, int length, int ladjust) +{ + int i; + int len=0; + char* s1 = s; + while (*s1++) len++; + if (length < len) length = len; + + if (ladjust) { + for (i=0; i< len; i++) buf[i] = s[i]; + for (i=len; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-len; i++) buf[i] = ' '; + for (i=length-len; i < length; i++) buf[i] = s[i-length+len]; + } + return length; +} + +static int +PrintNum(char * buf, unsigned long u, int base, int negFlag, + int length, int ladjust, char padc, int upcase) +{ + /* algorithm : + * 1. prints the number from left to right in reverse form. + * 2. fill the remaining spaces with padc if length is longer than + * the actual length + * TRICKY : if left adjusted, no "0" padding. + * if negtive, insert "0" padding between "0" and number. + * 3. if (!ladjust) we reverse the whole string including paddings + * 4. otherwise we only reverse the actual string representing the num. + */ + + int actualLength =0; + char *p = buf; + int i; + + do { + int tmp = u %base; + if (tmp <= 9) { + *p++ = '0' + tmp; + } else if (upcase) { + *p++ = 'A' + tmp - 10; + } else { + *p++ = 'a' + tmp - 10; + } + u /= base; + } while (u != 0); + + if (negFlag) { + *p++ = '-'; + } + + /* figure out actual length and adjust the maximum length */ + actualLength = p - buf; + if (length < actualLength) length = actualLength; + + /* add padding */ + if (ladjust) { + padc = ' '; + } + if (negFlag && !ladjust && (padc == '0')) { + for (i = actualLength-1; i< length-1; i++) buf[i] = padc; + buf[length -1] = '-'; + } else { + for (i = actualLength; i< length; i++) buf[i] = padc; + } + + + /* prepare to reverse the string */ + { + int begin = 0; + int end; + if (ladjust) { + end = actualLength - 1; + } else { + end = length -1; + } + + while (end > begin) { + char tmp = buf[begin]; + buf[begin] = buf[end]; + buf[end] = tmp; + begin ++; + end --; + } + } + + /* adjust the string pointer */ + return length; +} + +static void printf_output(void *arg, char *s, int l) +{ + int i; + + // special termination call + if ((l==1) && (s[0] == '\0')) return; + + for (i=0; i< l; i++) { + board_putc(s[i]); + if (s[i] == '\n') board_putc('\r'); + } +} + +void printf(char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + lp_Print(printf_output, 0, fmt, ap); + va_end(ap); +} diff --git a/target/linux/adm5120/image/lzma-loader/src/printf.h b/target/linux/adm5120/image/lzma-loader/src/printf.h new file mode 100644 index 0000000..9b1c1df --- /dev/null +++ b/target/linux/adm5120/image/lzma-loader/src/printf.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _printf_h_ +#define _printf_h_ + +#include +void printf(char *fmt, ...); + +#endif /* _printf_h_ */ diff --git a/target/linux/adm5120/image/rb1xx.mk b/target/linux/adm5120/image/rb1xx.mk new file mode 100644 index 0000000..3552958 --- /dev/null +++ b/target/linux/adm5120/image/rb1xx.mk @@ -0,0 +1,24 @@ +# +# Copyright (C) 2007,2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + + +define Image/cmdline/yaffs2 + root=/dev/mtdblock3 rootfstype=yaffs2 +endef + +define Image/BuildKernel/RouterBoard + $(CP) $(KDIR)/vmlinux-initramfs.elf $(call imgname,kernel-initramfs,rb1xx) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(call imgname,kernel-initramfs,rb1xx) \ + '$(strip $(call Image/cmdline/yaffs2))' +endef + +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y) + define Image/BuildKernel + $(call Image/BuildKernel/RouterBoard) + endef +endif + diff --git a/target/linux/adm5120/image/router_be.mk b/target/linux/adm5120/image/router_be.mk new file mode 100644 index 0000000..5a16672 --- /dev/null +++ b/target/linux/adm5120/image/router_be.mk @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007,2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Image/Build/ZyXEL + $(call Image/Build/Loader,$(2),bin,0x80500000,0,y,$(2)) + $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1)) + $(STAGING_DIR_HOST)/bin/mkzynfw -B $(2) \ + -b $(KDIR)/loader-$(2).bin \ + -r $(call imgname,$(1),$(2)).trx:0x10000 \ + -o $(call imgname,$(1),$(2))-webui.bin +endef + +define Image/Build/Template/ZyXEL + $(call Image/Build/ZyXEL,$(1),$(2)) +endef + +define Image/Build/Template/ZyXEL/squashfs + $(call Image/Build/Template/ZyXEL,squashfs,$(1)) +endef + +define Image/Build/Template/ZyXEL/jffs2 + $(call Image/Build/Template/ZyXEL,jffs2,$(1)) +endef + +define Image/Build/Template/ZyXEL/Initramfs + $(call Image/Build/LZMAKernel/KArgs,$(1),bin) +endef + +# +# Profiles +# +define Image/Build/Profile/P334WT + $(call Image/Build/Template/ZyXEL/$(1),p-334wt) +endef + +define Image/Build/Profile/P335WT + $(call Image/Build/Template/ZyXEL/$(1),p-335wt) +endef + +define Image/Build/Profile/Generic + $(call Image/Build/Profile/P334WT,$(1)) + $(call Image/Build/Profile/P335WT,$(1)) +endef + diff --git a/target/linux/adm5120/image/router_le.mk b/target/linux/adm5120/image/router_le.mk new file mode 100644 index 0000000..1e3d7f7 --- /dev/null +++ b/target/linux/adm5120/image/router_le.mk @@ -0,0 +1,401 @@ +# +# Copyright (C) 2007-2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define trxedimax/jffs2-128k +-a 0x20000 -f $(KDIR)/root.jffs2-128k +endef + +define trxedimax/jffs2-64k +-a 0x10000 -f $(KDIR)/root.jffs2-64k +endef + +define trxedimax/squashfs +-a 1024 -f $(KDIR)/root.squashfs +endef + +define Image/Build/TRXEdimax + $(STAGING_DIR_HOST)/bin/trx -o $(1) -f $(KDIR)/vmlinux.lzma \ + $(call trxedimax/$(2)) +endef + +define Image/Build/Compex + $(call Image/Build/Loader,$(2),gz,0x80500000,0,y,$(2)) + $(call Image/Build/TRX,$(call imgname,$(1),$(2)).trx,$(1),$(KDIR)/loader-$(2).gz) +endef + +define Image/Build/Edimax + $(call Image/Build/Loader,$(2),gz,0x80500000,0x6D8,y,$(2)) + $(call Image/Build/TRXEdimax,$(call imgname,$(1),$(2)).trx,$(1)) + $(STAGING_DIR_HOST)/bin/mkcsysimg -B $(2) -d -w \ + -r $(KDIR)/loader-$(2).gz::0x1000 \ + -x $(call imgname,$(1),$(2)).trx:0x10000 \ + -x $(JFFS2MARK):0x10000 \ + $(call imgname,$(1),$(2))-webui.bin + $(STAGING_DIR_HOST)/bin/mkcsysimg -B $(2) -d \ + -r $(KDIR)/loader-$(2).gz::0x1000 \ + -x $(call imgname,$(1),$(2)).trx:0x10000 \ + -x $(JFFS2MARK):0x10000 \ + $(call imgname,$(1),$(2))-xmodem.bin + rm -f $(call imgname,$(1),$(2)).trx +endef + +define Image/Build/Osbridge + $(call Image/Build/Loader,$(2),gz,0x80500000,0x6D8,y,$(2)) + $(call Image/Build/TRXEdimax,$(call imgname,$(1),$(2)).trx,$(1)) + $(STAGING_DIR_HOST)/bin/mkcsysimg -B $(2) -d \ + -r $(KDIR)/loader-$(2).gz::0x1000 \ + -x $(call imgname,$(1),$(2)).trx:0x10000 \ + -x $(JFFS2MARK):0x10000 \ + $(call imgname,$(1),$(2))-firmware.bin + $(STAGING_DIR_HOST)/bin/osbridge-crc \ + -i $(call imgname,$(1),$(2))-firmware.bin \ + -o $(call imgname,$(1),$(2))-temp.bin + $(STAGING_DIR_HOST)/bin/pc1crypt \ + -i $(call imgname,$(1),$(2))-temp.bin \ + -o $(call imgname,$(1),$(2))-webui.bin + rm -f $(call imgname,$(1),$(2))-temp.bin + rm -f $(call imgname,$(1),$(2)).trx +endef + +define Image/Build/Infineon + $(call Image/Build/Loader,$(2),gz,0x80500000,0x6D8,y,$(2)) + $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1)) + dd if=$(KDIR)/loader-$(2).gz of=$(call imgname,$(1),$(2)).img bs=64k conv=sync + cat $(call imgname,$(1),$(2)).trx >> $(call imgname,$(1),$(2)).img +endef + +define Image/Build/Cellvision + $(call Image/Build/Loader,$(2),bin,0x80500000,0x6D8,y,$(3)) + mkdir -p $(BIN_DIR)/tmp + cp $(KDIR)/loader-$(2).bin $(BIN_DIR)/tmp/vmlinux.bin + gzip -9n $(BIN_DIR)/tmp/vmlinux.bin + dd if=$(BIN_DIR)/tmp/vmlinux.bin.gz of=$(call imgname,$(1),$(2))-xmodem.bin bs=64k conv=sync + rm -rf $(BIN_DIR)/tmp + $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1)) + cat $(call imgname,$(1),$(2)).trx >> $(call imgname,$(1),$(2))-xmodem.bin + $(STAGING_DIR_HOST)/bin/mkcasfw -B $(2) -d \ + -K $(call imgname,$(1),$(2))-xmodem.bin \ + $(call imgname,$(1),$(2))-webui.bin +endef + +define Image/Build/Cellvision2 + # only for CAS-700/771/790/861 + $(call Image/Build/Loader,$(2),gz,0x80500000,0x6D8,y,$(3)) + $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1)) + dd if=$(KDIR)/loader-$(2).gz of=$(call imgname,$(1),$(2)).bin bs=64k conv=sync + cat $(call imgname,$(1),$(2)).trx >> $(call imgname,$(1),$(2)).bin + echo -ne '\x14\x07\x24\x06$(2)' | dd bs=14 count=1 conv=sync >> $(call imgname,$(1),$(2)).bin + echo -ne 'OpenWrt\x00\x00\x00' >> $(call imgname,$(1),$(2)).bin +endef + +define Image/Build/MyLoader + $(call Image/Build/Loader,$(2),gz,0x80500000,0) + $(call Image/Build/TRXNoloader,$(call imgname,$(1),$(2)).trx,$(1)) + $(STAGING_DIR_HOST)/bin/mkmylofw -B $(2) \ + -p0x20000:0x10000:ahp:0x80001000 \ + -p0x30000:0 \ + -b0x20000:0x10000:h:$(KDIR)/loader-$(2).gz \ + -b0x30000:0::$(call imgname,$(1),$(2)).trx \ + $(call imgname,$(1),$(2)).bin +endef + +# +# Cellvision CAS-630/630W, CAS-670/670W, NFS-101U/101WU, NFS-202U/202WU +# +define Image/Build/Template/Cellvision + $(call Image/Build/Cellvision,$(1),$(2),$(3)) +endef + +define Image/Build/Template/Cellvision/squashfs + $(call Image/Build/Template/Cellvision,squashfs,$(1),$(2)) +endef + +define Image/Build/Template/Cellvision/jffs2-64k + $(call Image/Build/Template/Cellvision,jffs2-64k,$(1),$(2)) +endef + +# +# Cellvision CAS-700/700W, CAS-771/771W, CAS-790, CAS-861/861W +# +define Image/Build/Template/Cellvision2 + $(call Image/Build/Cellvision2,$(1),$(2),$(3)) +endef + +define Image/Build/Template/Cellvision2/squashfs + $(call Image/Build/Template/Cellvision2,squashfs,$(1),$(2)) +endef + +define Image/Build/Template/Cellvision2/jffs2-64k + $(call Image/Build/Template/Cellvision2,jffs2-64k,$(1),$(2)) +endef + +define Image/Build/Template/Cellvision2/Initramfs + $(call Image/Build/LZMAKernel/Cellvision,$(1),$(2),gz) +endef + +# +# Compex NP27G, NP28G, WP54G, WP54AG, WPP54G, WPP54AG +# +define Image/Build/Template/Compex + $(call Image/Build/MyLoader,$(1),$(2)) +endef + +define Image/Build/Template/Compex/squashfs + $(call Image/Build/Template/Compex,squashfs,$(1)) +endef + +define Image/Build/Template/Compex/jffs2-64k + $(call Image/Build/Template/Compex,jffs2-64k,$(1)) +endef + +define Image/Build/Template/Compex/Initramfs + $(call Image/Build/LZMAKernel/Generic,$(1),bin) +endef + +# +# Compex WP54G-WRT +# +define Image/Build/Template/WP54GWRT + $(call Image/Build/Compex,$(1),wp54g-wrt) +endef + +define Image/Build/Template/WP54GWRT/squashfs + $(call Image/Build/Template/WP54GWRT,squashfs) +endef + +define Image/Build/Template/WP54GWRT/jffs2-64k + $(call Image/Build/Template/WP54GWRT,jffs2-64k) +endef + +define Image/Build/Template/WP54GWRT/Initramfs + $(call Image/Build/LZMAKernel/KArgs,wp54g-wrt,bin) +endef + +# +# Edimax BR-6104K, BR-6104KP, BR-6104Wg, BR-6114WG +# +define Image/Build/Template/Edimax + $(call Image/Build/Edimax,$(1),$(2)) +endef + +define Image/Build/Template/Edimax/squashfs + $(call Image/Build/Template/Edimax,squashfs,$(1)) +endef + +define Image/Build/Template/Edimax/Initramfs + $(call Image/Build/LZMAKernel/Admboot,$(1),gz) +endef + +# +# Infineon EASY 5120, EASY 83000 +# +define Image/Build/Template/Infineon + $(call Image/Build/Infineon,$(1),$(2)) +endef + +define Image/Build/Template/Infineon/squashfs + $(call Image/Build/Template/Infineon,squashfs,$(1)) +endef + +define Image/Build/Template/Infineon/jffs2-64k + $(call Image/Build/Template/Infineon,jffs2-64k,$(1)) +endef + +define Image/Build/Template/Infineon/Initramfs + $(call Image/Build/LZMAKernel/Admboot,$(1),gz) +endef + +# +# Generic EB-214A +# +define Image/Build/Template/Edimax/Initramfs + $(call Image/Build/LZMAKernel/Admboot,eb-214a,bin) +endef + + +# +# Mikrotik RouterBOARD 1xx +# +define Image/Build/Template/Mikrotik/Initramfs + $(CP) $(KDIR)/vmlinux.elf $(call imgname,netboot,rb1xx) +endef + +# +# OSBRiDGE 5GXi/5XLi +# +define Image/Build/Template/Osbridge + $(call Image/Build/Osbridge,$(1),$(2)) +endef + +define Image/Build/Template/Osbridge/squashfs + $(call Image/Build/Template/Osbridge,squashfs,$(1)) +endef + +define Image/Build/Template/Osbridge/Initramfs + $(call Image/Build/LZMAKernel/Admboot,$(1),gz) +endef + +# +# Profiles +# +define Image/Build/Profile/CAS630 + $(call Image/Build/Template/Cellvision/$(1),cas-630,cas-630) +endef + +define Image/Build/Profile/CAS630W + $(call Image/Build/Template/Cellvision/$(1),cas-630w,cas-630) +endef + +define Image/Build/Profile/CAS670 + $(call Image/Build/Template/Cellvision/$(1),cas-670,cas-670) +endef + +define Image/Build/Profile/CAS670W + $(call Image/Build/Template/Cellvision/$(1),cas-670w,cas-670) +endef + +define Image/Build/Profile/NFS101U + $(call Image/Build/Template/Cellvision/$(1),nfs-101u,nfs-101u) + $(call Image/Build/Template/Cellvision/$(1),dn-7013,nfs-101u) + $(call Image/Build/Template/Cellvision/$(1),dns-120,nfs-101u) + $(call Image/Build/Template/Cellvision/$(1),mu-5000fs,nfs-101u) + $(call Image/Build/Template/Cellvision/$(1),tn-u100,nfs-101u) + $(call Image/Build/Template/Cellvision/$(1),cg-nsadp,nfs-101u) +endef + +define Image/Build/Profile/NFS101WU + $(call Image/Build/Template/Cellvision/$(1),nfs-101wu,nfs-101u) + $(call Image/Build/Template/Cellvision/$(1),dns-g120,nfs-101u) +endef + +define Image/Build/Profile/CAS700 + $(call Image/Build/Template/Cellvision2/$(1),cas-700,cas-700) +endef + +define Image/Build/Profile/CAS700W + $(call Image/Build/Template/Cellvision2/$(1),cas-700w,cas-700) +endef + +define Image/Build/Profile/CAS771 + $(call Image/Build/Template/Cellvision2/$(1),cas-771,cas-771) +endef + +define Image/Build/Profile/CAS771W + $(call Image/Build/Template/Cellvision2/$(1),cas-771w,cas-771) +endef + +define Image/Build/Profile/CAS790 + $(call Image/Build/Template/Cellvision2/$(1),cas-790,cas-790) +endef + +define Image/Build/Profile/CAS861 + $(call Image/Build/Template/Cellvision2/$(1),cas-861,cas-861) +endef + +define Image/Build/Profile/CAS861W + $(call Image/Build/Template/Cellvision2/$(1),cas-861w,cas-861) +endef + +define Image/Build/Profile/NP27G + $(call Image/Build/Template/Compex/$(1),np27g) +endef + +define Image/Build/Profile/NP28G + $(call Image/Build/Template/Compex/$(1),np28g) +endef + +define Image/Build/Profile/WP54 + $(call Image/Build/Template/Compex/$(1),wp54g) + $(call Image/Build/Template/Compex/$(1),wp54ag) + $(call Image/Build/Template/Compex/$(1),wpp54g) + $(call Image/Build/Template/Compex/$(1),wpp54ag) + $(call Image/Build/Template/WP54GWRT/$(1)) +endef + +define Image/Build/Profile/BR6104K + $(call Image/Build/Template/Edimax/$(1),br-6104k) +endef + +define Image/Build/Profile/BR6104KP + $(call Image/Build/Template/Edimax/$(1),br-6104kp) +endef + +define Image/Build/Profile/BR6104WG + $(call Image/Build/Template/Edimax/$(1),br-6104wg) +endef + +define Image/Build/Profile/BR6114WG + $(call Image/Build/Template/Edimax/$(1),br-6114wg) +endef + +define Image/Build/Profile/EASY83000 + $(call Image/Build/Template/Infineon/$(1),easy-83000) +endef + +define Image/Build/Profile/EASY5120RT + $(call Image/Build/Template/Infineon/$(1),easy-5120-rt) +endef + +define Image/Build/Profile/EASY5120PATA + $(call Image/Build/Template/Infineon/$(1),easy-5120p-ata) +endef + +define Image/Build/Profile/PMUGW + $(call Image/Build/Template/Infineon/$(1),powerline-mugw) +endef + +define Image/Build/Profile/5GXI + $(call Image/Build/Template/Osbridge/$(1),5gxi) +endef + +define Image/Build/Profile/RouterBoard + $(call Image/Build/Template/Mikrotik/$(1)) +endef + +ifeq ($(CONFIG_BROKEN),y) + define Image/Build/Experimental + # Cellvison + $(call Image/Build/Profile/CAS630,$(1)) + $(call Image/Build/Profile/CAS630W,$(1)) + $(call Image/Build/Profile/CAS670,$(1)) + $(call Image/Build/Profile/CAS670W,$(1)) + $(call Image/Build/Profile/CAS700,$(1)) + $(call Image/Build/Profile/CAS700W,$(1)) + $(call Image/Build/Profile/CAS771,$(1)) + $(call Image/Build/Profile/CAS771W,$(1)) + $(call Image/Build/Profile/CAS861,$(1)) + $(call Image/Build/Profile/CAS861W,$(1)) + # Motorola + $(call Image/Build/Profile/PMUGW,$(1)) + # OSBRiDGE + $(call Image/Build/Profile/5GXI,$(1)) + endef +endif + +define Image/Build/Profile/Generic + # Cellvision + $(call Image/Build/Profile/NFS101U,$(1)) + $(call Image/Build/Profile/NFS101WU,$(1)) + # Compex + $(call Image/Build/Profile/WP54,$(1)) + $(call Image/Build/Profile/NP27G,$(1)) + $(call Image/Build/Profile/NP28G,$(1)) + # Edimax + $(call Image/Build/Profile/BR6104K,$(1)) + $(call Image/Build/Profile/BR6104KP,$(1)) + $(call Image/Build/Profile/BR6104WG,$(1)) + $(call Image/Build/Profile/BR6114WG,$(1)) + $(call Image/Build/Profile/EB214A,$(1)) + # Infineon + $(call Image/Build/Profile/EASY83000,$(1)) + $(call Image/Build/Profile/EASY5120RT,$(1)) + $(call Image/Build/Profile/EASY5120PATA,$(1)) + # Mikrotik + $(call Image/Build/Profile/RB1xx/$(1)) + + $(call Image/Build/Experimental,$(1)) +endef diff --git a/target/linux/adm5120/modules.mk b/target/linux/adm5120/modules.mk new file mode 100644 index 0000000..3ad4540 --- /dev/null +++ b/target/linux/adm5120/modules.mk @@ -0,0 +1,56 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/ledtrig-adm5120-switch + SUBMENU:=$(OTHER_MENU) + TITLE:=LED ADM5120 Switch Port Status Trigger + DEPENDS:=@TARGET_adm5120 + KCONFIG:=CONFIG_LEDS_TRIGGER_ADM5120_SWITCH + FILES:=$(LINUX_DIR)/drivers/leds/ledtrig-adm5120-switch.ko + AUTOLOAD:=$(call AutoLoad,50,ledtrig-adm5120-switch) +endef + +define KernelPackage/ledtrig-adm5120-switch/description + Kernel module to allow LEDs to be controlled by the port states + of the ADM5120 built-in ethernet switch. +endef + +$(eval $(call KernelPackage,ledtrig-adm5120-switch)) + + +define KernelPackage/pata-rb153-cf + SUBMENU:=$(BLOCK_MENU) + TITLE:=RouterBOARD 153 CF Slot support + DEPENDS:=@TARGET_adm5120_rb1xx + KCONFIG:=CONFIG_PATA_RB153_CF + FILES:=$(LINUX_DIR)/drivers/ata/pata_rb153_cf.ko + AUTOLOAD:=$(call AutoLoad,30,pata_rb153_cf,1) + $(call AddDepends/ata) +endef + +define KernelPackage/pata-rb153-cf/description + Kernel support for the RouterBoard 153 CF slot. +endef + +$(eval $(call KernelPackage,pata-rb153-cf,1)) + + +define KernelPackage/usb-adm5120 + SUBMENU:=$(USB_MENU) + TITLE:=Support for the ADM5120 HCD controller + DEPENDS:=@TARGET_adm5120 + KCONFIG:=CONFIG_USB_ADM5120_HCD + FILES:=$(LINUX_DIR)/drivers/usb/host/adm5120-hcd.ko + AUTOLOAD:=$(call AutoLoad,50,adm5120-hcd,1) + $(call AddDepends/usb) +endef + +define KernelPackage/usb-adm5120/description + Kernel support for the ADM5120 HCD USB controller +endef + +$(eval $(call KernelPackage,usb-adm5120)) diff --git a/target/linux/adm5120/patches-3.18/001-adm5120.patch b/target/linux/adm5120/patches-3.18/001-adm5120.patch new file mode 100644 index 0000000..3e0e3ff --- /dev/null +++ b/target/linux/adm5120/patches-3.18/001-adm5120.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -60,6 +60,24 @@ choice + prompt "System type" + default SGI_IP22 + ++config ADM5120 ++ bool "Infineon/ADMtek ADM5120 SoC based machines" ++ select BOOT_RAW ++ select NO_EXCEPT_FILL ++ select CEVT_R4K ++ select CSRC_R4K ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_HAS_EARLY_PRINTK ++ select DMA_NONCOHERENT ++ select IRQ_CPU ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select ARCH_REQUIRE_GPIOLIB ++ select SWAP_IO_SPACE if CPU_BIG_ENDIAN ++ select MIPS_MACHINE ++ select HAVE_CLK ++ + config MIPS_ALCHEMY + bool "Alchemy processor based machines" + select 64BIT_PHYS_ADDR +@@ -834,6 +852,7 @@ config MIPS_PARAVIRT + + endchoice + ++source "arch/mips/adm5120/Kconfig" + source "arch/mips/alchemy/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm47xx/Kconfig" +--- a/arch/mips/Kbuild.platforms ++++ b/arch/mips/Kbuild.platforms +@@ -1,5 +1,6 @@ + # All platforms listed in alphabetic order + ++platforms += adm5120 + platforms += alchemy + platforms += ar7 + platforms += ath79 diff --git a/target/linux/adm5120/patches-3.18/002-adm5120_flash.patch b/target/linux/adm5120/patches-3.18/002-adm5120_flash.patch new file mode 100644 index 0000000..8936af1 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/002-adm5120_flash.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/maps/Kconfig ++++ b/drivers/mtd/maps/Kconfig +@@ -399,4 +399,8 @@ config MTD_LATCH_ADDR + + If compiled as a module, it will be called latch-addr-flash. + ++config MTD_ADM5120 ++ tristate "Map driver for ADM5120 based boards" ++ depends on ADM5120 ++ + endmenu +--- a/drivers/mtd/maps/Makefile ++++ b/drivers/mtd/maps/Makefile +@@ -30,6 +30,7 @@ obj-$(CONFIG_MTD_SUN_UFLASH) += sun_ufla + obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o + obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o + obj-$(CONFIG_MTD_PCI) += pci.o ++obj-$(CONFIG_MTD_ADM5120) += adm5120-flash.o + obj-$(CONFIG_MTD_IMPA7) += impa7.o + obj-$(CONFIG_MTD_UCLINUX) += uclinux.o + obj-$(CONFIG_MTD_NETtel) += nettel.o diff --git a/target/linux/adm5120/patches-3.18/003-adm5120_switch.patch b/target/linux/adm5120/patches-3.18/003-adm5120_switch.patch new file mode 100644 index 0000000..416488c --- /dev/null +++ b/target/linux/adm5120/patches-3.18/003-adm5120_switch.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -263,6 +263,10 @@ source "drivers/net/dsa/Kconfig" + + source "drivers/net/ethernet/Kconfig" + ++config ADM5120_ENET ++ tristate "ADM5120 Ethernet switch support" ++ depends on ADM5120 ++ + source "drivers/net/fddi/Kconfig" + + source "drivers/net/hippi/Kconfig" +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -34,6 +34,7 @@ obj-$(CONFIG_CAN) += can/ + obj-$(CONFIG_ETRAX_ETHERNET) += cris/ + obj-$(CONFIG_NET_DSA) += dsa/ + obj-$(CONFIG_ETHERNET) += ethernet/ ++obj-$(CONFIG_ADM5120_ENET) += adm5120sw.o + obj-$(CONFIG_FDDI) += fddi/ + obj-$(CONFIG_HIPPI) += hippi/ + obj-$(CONFIG_HAMRADIO) += hamradio/ diff --git a/target/linux/adm5120/patches-3.18/005-adm5120_usb.patch b/target/linux/adm5120/patches-3.18/005-adm5120_usb.patch new file mode 100644 index 0000000..139e223 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/005-adm5120_usb.patch @@ -0,0 +1,33 @@ +--- a/drivers/usb/Makefile ++++ b/drivers/usb/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_USB_DWC2) += dwc2/ + obj-$(CONFIG_USB_MON) += mon/ + + obj-$(CONFIG_PCI) += host/ ++obj-$(CONFIG_USB_ADM5120_HCD) += host/ + obj-$(CONFIG_USB_EHCI_HCD) += host/ + obj-$(CONFIG_USB_ISP116X_HCD) += host/ + obj-$(CONFIG_USB_OHCI_HCD) += host/ +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -3,6 +3,10 @@ + # + comment "USB Host Controller Drivers" + ++config USB_ADM5120_HCD ++ tristate "ADM5120 HCD support (EXPERIMENTAL)" ++ depends on USB && ADM5120 && EXPERIMENTAL ++ + config USB_C67X00_HCD + tristate "Cypress C67x00 HCD support" + help +--- a/drivers/usb/host/Makefile ++++ b/drivers/usb/host/Makefile +@@ -31,6 +31,7 @@ obj-$(CONFIG_PCI) += pci-quirks.o + obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o + obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o + ++obj-$(CONFIG_USB_ADM5120_HCD) += adm5120-hcd.o + obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o + obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o + obj-$(CONFIG_USB_EHCI_HCD_PLATFORM) += ehci-platform.o diff --git a/target/linux/adm5120/patches-3.18/007-adm5120_pci.patch b/target/linux/adm5120/patches-3.18/007-adm5120_pci.patch new file mode 100644 index 0000000..a5a0abf --- /dev/null +++ b/target/linux/adm5120/patches-3.18/007-adm5120_pci.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o + obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o + obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o ++obj-$(CONFIG_ADM5120) += pci-adm5120.o + obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o + obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o + obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -1820,6 +1820,9 @@ + + #define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */ + ++#define PCI_VENDOR_ID_ADMTEK 0x1317 ++#define PCI_DEVICE_ID_ADMTEK_ADM5120 0x5120 ++ + #define PCI_VENDOR_ID_SIIG 0x131f + #define PCI_SUBVENDOR_ID_SIIG 0x131f + #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 diff --git a/target/linux/adm5120/patches-3.18/009-adm5120_leds_switch_trigger.patch b/target/linux/adm5120/patches-3.18/009-adm5120_leds_switch_trigger.patch new file mode 100644 index 0000000..627afc1 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/009-adm5120_leds_switch_trigger.patch @@ -0,0 +1,22 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -508,4 +508,12 @@ config LEDS_VERSATILE + comment "LED Triggers" + source "drivers/leds/trigger/Kconfig" + ++config LEDS_TRIGGER_ADM5120_SWITCH ++ tristate "LED ADM5120 Switch Port Status Trigger" ++ depends on LEDS_TRIGGERS && ADM5120 ++ help ++ This allows LEDs to be controlled by the port states of ++ the ADM5120 built-in Ethernet Switch ++ If unsure, say N. ++ + endif # NEW_LEDS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -65,3 +65,4 @@ obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o + obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o + obj-$(CONFIG_LEDS_TRIGGER_USBDEV) += ledtrig-usbdev.o ++obj-$(CONFIG_LEDS_TRIGGER_ADM5120_SWITCH) += ledtrig-adm5120-switch.o diff --git a/target/linux/adm5120/patches-3.18/050-revert_rootfs_splits.patch b/target/linux/adm5120/patches-3.18/050-revert_rootfs_splits.patch new file mode 100644 index 0000000..6062259 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/050-revert_rootfs_splits.patch @@ -0,0 +1,354 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -30,11 +30,9 @@ + #include + #include + #include +-#include + #include + + #include "mtdcore.h" +-#include "mtdsplit/mtdsplit.h" + + #define MTD_ERASE_PARTIAL 0x8000 /* partition only covers parts of an erase block */ + +@@ -50,14 +48,13 @@ struct mtd_part { + struct list_head list; + }; + +-static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part); +- + /* + * Given a pointer to the MTD object in the mtd_part structure, we can retrieve + * the pointer to that structure with this macro. + */ + #define PART(x) ((struct mtd_part *)(x)) + ++ + /* + * MTD methods which simply translate the effective address and pass through + * to the _real_ device. +@@ -521,12 +518,14 @@ static struct mtd_part *allocate_partiti + if (slave->offset == MTDPART_OFS_APPEND) + slave->offset = cur_offset; + if (slave->offset == MTDPART_OFS_NXTBLK) { +- /* Round up to next erasesize */ +- slave->offset = mtd_roundup_to_eb(cur_offset, master); +- if (slave->offset != cur_offset) ++ slave->offset = cur_offset; ++ if (mtd_mod_by_eb(cur_offset, master) != 0) { ++ /* Round up to next erasesize */ ++ slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize; + printk(KERN_NOTICE "Moving partition %d: " + "0x%012llx -> 0x%012llx\n", partno, + (unsigned long long)cur_offset, (unsigned long long)slave->offset); ++ } + } + if (slave->offset == MTDPART_OFS_RETAIN) { + slave->offset = cur_offset; +@@ -627,10 +626,8 @@ out_register: + return slave; + } + +- +-static int +-__mtd_add_partition(struct mtd_info *master, const char *name, +- long long offset, long long length, bool dup_check) ++int mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length) + { + struct mtd_partition part; + struct mtd_part *p, *new; +@@ -662,24 +659,21 @@ __mtd_add_partition(struct mtd_info *mas + end = offset + length; + + mutex_lock(&mtd_partitions_mutex); +- if (dup_check) { +- list_for_each_entry(p, &mtd_partitions, list) +- if (p->master == master) { +- if ((start >= p->offset) && +- (start < (p->offset + p->mtd.size))) +- goto err_inv; +- +- if ((end >= p->offset) && +- (end < (p->offset + p->mtd.size))) +- goto err_inv; +- } +- } ++ list_for_each_entry(p, &mtd_partitions, list) ++ if (p->master == master) { ++ if ((start >= p->offset) && ++ (start < (p->offset + p->mtd.size))) ++ goto err_inv; ++ ++ if ((end >= p->offset) && ++ (end < (p->offset + p->mtd.size))) ++ goto err_inv; ++ } + + list_add(&new->list, &mtd_partitions); + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&new->mtd); +- mtd_partition_split(master, new); + + return ret; + err_inv: +@@ -689,12 +683,6 @@ err_inv: + } + EXPORT_SYMBOL_GPL(mtd_add_partition); + +-int mtd_add_partition(struct mtd_info *master, const char *name, +- long long offset, long long length) +-{ +- return __mtd_add_partition(master, name, offset, length, true); +-} +- + int mtd_del_partition(struct mtd_info *master, int partno) + { + struct mtd_part *slave, *next; +@@ -718,166 +706,6 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + +-static int +-run_parsers_by_type(struct mtd_part *slave, enum mtd_parser_type type) +-{ +- struct mtd_partition *parts; +- int nr_parts; +- int i; +- +- nr_parts = parse_mtd_partitions_by_type(&slave->mtd, type, &parts, +- NULL); +- if (nr_parts <= 0) +- return nr_parts; +- +- if (WARN_ON(!parts)) +- return 0; +- +- for (i = 0; i < nr_parts; i++) { +- /* adjust partition offsets */ +- parts[i].offset += slave->offset; +- +- __mtd_add_partition(slave->master, +- parts[i].name, +- parts[i].offset, +- parts[i].size, +- false); +- } +- +- kfree(parts); +- +- return nr_parts; +-} +- +-static inline unsigned long +-mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len) +-{ +- unsigned long mask = mtd->erasesize - 1; +- +- len += offset & mask; +- len = (len + mask) & ~mask; +- len -= offset & mask; +- return len; +-} +- +-static int split_squashfs(struct mtd_info *master, int offset, int *split_offset) +-{ +- size_t squashfs_len; +- int len, ret; +- +- ret = mtd_get_squashfs_len(master, offset, &squashfs_len); +- if (ret) +- return ret; +- +- len = mtd_pad_erasesize(master, offset, squashfs_len); +- *split_offset = offset + len; +- +- return 0; +-} +- +-static void split_rootfs_data(struct mtd_info *master, struct mtd_part *part) +-{ +- unsigned int split_offset = 0; +- unsigned int split_size; +- int ret; +- +- ret = split_squashfs(master, part->offset, &split_offset); +- if (ret) +- return; +- +- if (split_offset <= 0) +- return; +- +- if (config_enabled(CONFIG_MTD_SPLIT_SQUASHFS_ROOT)) +- pr_err("Dedicated partitioner didn't create \"rootfs_data\" partition, please fill a bug report!\n"); +- else +- pr_warn("Support for built-in \"rootfs_data\" splitter will be removed, please use CONFIG_MTD_SPLIT_SQUASHFS_ROOT\n"); +- +- split_size = part->mtd.size - (split_offset - part->offset); +- printk(KERN_INFO "mtd: partition \"%s\" created automatically, ofs=0x%x, len=0x%x\n", +- ROOTFS_SPLIT_NAME, split_offset, split_size); +- +- __mtd_add_partition(master, ROOTFS_SPLIT_NAME, split_offset, +- split_size, false); +-} +- +-#define UBOOT_MAGIC 0x27051956 +- +-static void split_uimage(struct mtd_info *master, struct mtd_part *part) +-{ +- struct { +- __be32 magic; +- __be32 pad[2]; +- __be32 size; +- } hdr; +- size_t len; +- +- if (mtd_read(master, part->offset, sizeof(hdr), &len, (void *) &hdr)) +- return; +- +- if (len != sizeof(hdr) || hdr.magic != cpu_to_be32(UBOOT_MAGIC)) +- return; +- +- len = be32_to_cpu(hdr.size) + 0x40; +- len = mtd_pad_erasesize(master, part->offset, len); +- if (len + master->erasesize > part->mtd.size) +- return; +- +- if (config_enabled(CONFIG_MTD_SPLIT_UIMAGE_FW)) +- pr_err("Dedicated partitioner didn't split firmware partition, please fill a bug report!\n"); +- else +- pr_warn("Support for built-in firmware splitter will be removed, please use CONFIG_MTD_SPLIT_UIMAGE_FW\n"); +- +- __mtd_add_partition(master, "rootfs", part->offset + len, +- part->mtd.size - len, false); +-} +- +-#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME +-#define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME +-#else +-#define SPLIT_FIRMWARE_NAME "unused" +-#endif +- +-static void split_firmware(struct mtd_info *master, struct mtd_part *part) +-{ +- int ret; +- +- ret = run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); +- if (ret > 0) +- return; +- +- if (config_enabled(CONFIG_MTD_UIMAGE_SPLIT)) +- split_uimage(master, part); +-} +- +-void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, +- int offset, int size) +-{ +-} +- +-static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part) +-{ +- static int rootfs_found = 0; +- +- if (rootfs_found) +- return; +- +- if (!strcmp(part->mtd.name, "rootfs")) { +- int num = run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); +- +- if (num <= 0 && config_enabled(CONFIG_MTD_ROOTFS_SPLIT)) +- split_rootfs_data(master, part); +- +- rootfs_found = 1; +- } +- +- if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && +- config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) +- split_firmware(master, part); +- +- arch_split_mtd_part(master, part->mtd.name, part->offset, +- part->mtd.size); +-} + /* + * This function, given a master MTD object and a partition table, creates + * and registers slave MTD objects which are bound to the master according to +@@ -907,7 +735,6 @@ int add_mtd_partitions(struct mtd_info * + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&slave->mtd); +- mtd_partition_split(master, slave); + + cur_offset = slave->offset + slave->mtd.size; + } +@@ -937,30 +764,6 @@ static struct mtd_part_parser *get_parti + + #define put_partition_parser(p) do { module_put((p)->owner); } while (0) + +-static struct mtd_part_parser * +-get_partition_parser_by_type(enum mtd_parser_type type, +- struct mtd_part_parser *start) +-{ +- struct mtd_part_parser *p, *ret = NULL; +- +- spin_lock(&part_parser_lock); +- +- p = list_prepare_entry(start, &part_parsers, list); +- if (start) +- put_partition_parser(start); +- +- list_for_each_entry_continue(p, &part_parsers, list) { +- if (p->type == type && try_module_get(p->owner)) { +- ret = p; +- break; +- } +- } +- +- spin_unlock(&part_parser_lock); +- +- return ret; +-} +- + void register_mtd_parser(struct mtd_part_parser *p) + { + spin_lock(&part_parser_lock); +@@ -1076,38 +879,6 @@ int parse_mtd_partitions(struct mtd_info + return ret; + } + +-int parse_mtd_partitions_by_type(struct mtd_info *master, +- enum mtd_parser_type type, +- struct mtd_partition **pparts, +- struct mtd_part_parser_data *data) +-{ +- struct mtd_part_parser *prev = NULL; +- int ret = 0; +- +- while (1) { +- struct mtd_part_parser *parser; +- +- parser = get_partition_parser_by_type(type, prev); +- if (!parser) +- break; +- +- ret = (*parser->parse_fn)(master, pparts, data); +- +- if (ret > 0) { +- put_partition_parser(parser); +- printk(KERN_NOTICE +- "%d %s partitions found on MTD device %s\n", +- ret, parser->name, master->name); +- break; +- } +- +- prev = parser; +- } +- +- return ret; +-} +-EXPORT_SYMBOL_GPL(parse_mtd_partitions_by_type); +- + int mtd_is_partition(const struct mtd_info *mtd) + { + struct mtd_part *part; diff --git a/target/linux/adm5120/patches-3.18/100-rootfs_split.patch b/target/linux/adm5120/patches-3.18/100-rootfs_split.patch new file mode 100644 index 0000000..dfc0e83 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/100-rootfs_split.patch @@ -0,0 +1,316 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -52,6 +52,14 @@ config MTD_TESTS + WARNING: some of the tests will ERASE entire MTD device which they + test. Do not use these tests unless you really know what you do. + ++config MTD_ROOTFS_ROOT_DEV ++ bool "Automatically set 'rootfs' partition to be root filesystem" ++ default y ++ ++config MTD_ROOTFS_SPLIT ++ bool "Automatically split 'rootfs' partition for squashfs" ++ default y ++ + config MTD_REDBOOT_PARTS + tristate "RedBoot partition table parsing" + ---help--- +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -30,6 +30,8 @@ + #include + #include + #include ++#include ++#include + #include + + #include "mtdcore.h" +@@ -53,7 +55,7 @@ struct mtd_part { + * the pointer to that structure with this macro. + */ + #define PART(x) ((struct mtd_part *)(x)) +- ++#define IS_PART(mtd) (mtd->_read == part_read) + + /* + * MTD methods which simply translate the effective address and pass through +@@ -706,6 +708,144 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++#ifdef CONFIG_MTD_ROOTFS_SPLIT ++#define ROOTFS_SPLIT_NAME "rootfs_data" ++#define ROOTFS_REMOVED_NAME "" ++ ++struct squashfs_super_block { ++ __le32 s_magic; ++ __le32 pad0[9]; ++ __le64 bytes_used; ++}; ++ ++ ++static int split_squashfs(struct mtd_info *master, int offset, int *split_offset) ++{ ++ struct squashfs_super_block sb; ++ int len, ret; ++ ++ ret = mtd_read(master, offset, sizeof(sb), &len, (void *) &sb); ++ if (ret || (len != sizeof(sb))) { ++ printk(KERN_ALERT "split_squashfs: error occured while reading " ++ "from \"%s\"\n", master->name); ++ return -EINVAL; ++ } ++ ++ if (SQUASHFS_MAGIC != le32_to_cpu(sb.s_magic) ) { ++ printk(KERN_ALERT "split_squashfs: no squashfs found in \"%s\"\n", ++ master->name); ++ *split_offset = 0; ++ return 0; ++ } ++ ++ if (le64_to_cpu((sb.bytes_used)) <= 0) { ++ printk(KERN_ALERT "split_squashfs: squashfs is empty in \"%s\"\n", ++ master->name); ++ *split_offset = 0; ++ return 0; ++ } ++ ++ len = (u32) le64_to_cpu(sb.bytes_used); ++ len += (offset & 0x000fffff); ++ len += (master->erasesize - 1); ++ len &= ~(master->erasesize - 1); ++ len -= (offset & 0x000fffff); ++ *split_offset = offset + len; ++ ++ return 0; ++} ++ ++static int split_rootfs_data(struct mtd_info *master, struct mtd_info *rpart, const struct mtd_partition *part) ++{ ++ struct mtd_partition dpart; ++ struct mtd_part *slave = NULL; ++ struct mtd_part *spart; ++ int ret, split_offset = 0; ++ ++ spart = PART(rpart); ++ ret = split_squashfs(master, spart->offset, &split_offset); ++ if (ret) ++ return ret; ++ ++ if (split_offset <= 0) ++ return 0; ++ ++ memcpy(&dpart, part, sizeof(dpart)); ++ dpart.name = ROOTFS_SPLIT_NAME; ++ ++ dpart.size = rpart->size - (split_offset - spart->offset); ++ dpart.offset = split_offset; ++ ++ printk(KERN_INFO "mtd: partition \"%s\" created automatically, ofs=%llX, len=%llX \n", ++ ROOTFS_SPLIT_NAME, dpart.offset, dpart.size); ++ ++ slave = allocate_partition(master, &dpart, 0, split_offset); ++ if (IS_ERR(slave)) ++ return PTR_ERR(slave); ++ mutex_lock(&mtd_partitions_mutex); ++ list_add(&slave->list, &mtd_partitions); ++ mutex_unlock(&mtd_partitions_mutex); ++ ++ add_mtd_device(&slave->mtd); ++ ++ rpart->split = &slave->mtd; ++ ++ return 0; ++} ++ ++static int refresh_rootfs_split(struct mtd_info *mtd) ++{ ++ struct mtd_partition tpart; ++ struct mtd_part *part; ++ char *name; ++ //int index = 0; ++ int offset, size; ++ int ret; ++ ++ part = PART(mtd); ++ ++ /* check for the new squashfs offset first */ ++ ret = split_squashfs(part->master, part->offset, &offset); ++ if (ret) ++ return ret; ++ ++ if ((offset > 0) && !mtd->split) { ++ printk(KERN_INFO "%s: creating new split partition for \"%s\"\n", __func__, mtd->name); ++ /* if we don't have a rootfs split partition, create a new one */ ++ tpart.name = (char *) mtd->name; ++ tpart.size = mtd->size; ++ tpart.offset = part->offset; ++ ++ return split_rootfs_data(part->master, &part->mtd, &tpart); ++ } else if ((offset > 0) && mtd->split) { ++ /* update the offsets of the existing partition */ ++ size = mtd->size + part->offset - offset; ++ ++ part = PART(mtd->split); ++ part->offset = offset; ++ part->mtd.size = size; ++ printk(KERN_INFO "%s: %s partition \"" ROOTFS_SPLIT_NAME "\", offset: 0x%06x (0x%06x)\n", ++ __func__, (!strcmp(part->mtd.name, ROOTFS_SPLIT_NAME) ? "updating" : "creating"), ++ (u32) part->offset, (u32) part->mtd.size); ++ name = kmalloc(sizeof(ROOTFS_SPLIT_NAME) + 1, GFP_KERNEL); ++ strcpy(name, ROOTFS_SPLIT_NAME); ++ part->mtd.name = name; ++ } else if ((offset <= 0) && mtd->split) { ++ printk(KERN_INFO "%s: removing partition \"%s\"\n", __func__, mtd->split->name); ++ ++ /* mark existing partition as removed */ ++ part = PART(mtd->split); ++ name = kmalloc(sizeof(ROOTFS_SPLIT_NAME) + 1, GFP_KERNEL); ++ strcpy(name, ROOTFS_REMOVED_NAME); ++ part->mtd.name = name; ++ part->offset = 0; ++ part->mtd.size = 0; ++ } ++ ++ return 0; ++} ++#endif /* CONFIG_MTD_ROOTFS_SPLIT */ ++ + /* + * This function, given a master MTD object and a partition table, creates + * and registers slave MTD objects which are bound to the master according to +@@ -722,6 +862,9 @@ int add_mtd_partitions(struct mtd_info * + struct mtd_part *slave; + uint64_t cur_offset = 0; + int i; ++#ifdef CONFIG_MTD_ROOTFS_SPLIT ++ int ret; ++#endif + + printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); + +@@ -736,12 +879,53 @@ int add_mtd_partitions(struct mtd_info * + + add_mtd_device(&slave->mtd); + ++ if (!strcmp(parts[i].name, "rootfs")) { ++#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV ++ if (ROOT_DEV == 0) { ++ printk(KERN_NOTICE "mtd: partition \"rootfs\" " ++ "set to be root filesystem\n"); ++ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, slave->mtd.index); ++ } ++#endif ++#ifdef CONFIG_MTD_ROOTFS_SPLIT ++ ret = split_rootfs_data(master, &slave->mtd, &parts[i]); ++ /* if (ret == 0) ++ * j++; */ ++#endif ++ } ++ + cur_offset = slave->offset + slave->mtd.size; + } + + return 0; + } + ++int mtd_device_refresh(struct mtd_info *mtd) ++{ ++ int ret = 0; ++ ++ if (IS_PART(mtd)) { ++ struct mtd_part *part; ++ struct mtd_info *master; ++ ++ part = PART(mtd); ++ master = part->master; ++ if (master->refresh_device) ++ ret = master->refresh_device(master); ++ } ++ ++ if (!ret && mtd->refresh_device) ++ ret = mtd->refresh_device(mtd); ++ ++#ifdef CONFIG_MTD_ROOTFS_SPLIT ++ if (!ret && IS_PART(mtd) && !strcmp(mtd->name, "rootfs")) ++ refresh_rootfs_split(mtd); ++#endif ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(mtd_device_refresh); ++ + static DEFINE_SPINLOCK(part_parser_lock); + static LIST_HEAD(part_parsers); + +--- a/drivers/mtd/mtdchar.c ++++ b/drivers/mtd/mtdchar.c +@@ -1008,6 +1008,12 @@ static int mtdchar_ioctl(struct file *fi + break; + } + ++ case MTDREFRESH: ++ { ++ ret = mtd_device_refresh(mtd); ++ break; ++ } ++ + default: + ret = -ENOTTY; + } +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -115,6 +115,7 @@ struct nand_ecclayout { + + struct module; /* only needed for owner field in mtd_info */ + ++struct mtd_info; + struct mtd_info { + u_char type; + uint32_t flags; +@@ -231,6 +232,9 @@ struct mtd_info { + int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs); + int (*_suspend) (struct mtd_info *mtd); + void (*_resume) (struct mtd_info *mtd); ++ int (*refresh_device)(struct mtd_info *mtd); ++ struct mtd_info *split; ++ + /* + * If the driver is something smart, like UBI, it may need to maintain + * its own reference counting. The below functions are only for driver. +@@ -397,6 +401,7 @@ extern int mtd_device_parse_register(str + int defnr_parts); + #define mtd_device_register(master, parts, nr_parts) \ + mtd_device_parse_register(master, NULL, NULL, parts, nr_parts) ++extern int mtd_device_refresh(struct mtd_info *master); + extern int mtd_device_unregister(struct mtd_info *master); + extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); + extern int __get_mtd_device(struct mtd_info *mtd); +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -37,12 +37,14 @@ + */ + struct mtd_info; + ++struct mtd_partition; + struct mtd_partition { + const char *name; /* identifier string */ + uint64_t size; /* partition size */ + uint64_t offset; /* offset within the master MTD space */ + uint32_t mask_flags; /* master MTD flags to mask out for this partition */ + struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only) */ ++ int (*refresh_partition)(struct mtd_info *); + }; + + #define MTDPART_OFS_RETAIN (-3) +--- a/include/uapi/mtd/mtd-abi.h ++++ b/include/uapi/mtd/mtd-abi.h +@@ -203,6 +203,7 @@ struct otp_info { + * without OOB, e.g., NOR flash. + */ + #define MEMWRITE _IOWR('M', 24, struct mtd_write_req) ++#define MTDREFRESH _IO('M', 50) + + /* + * Obsolete legacy interface. Keep it in order not to break userspace diff --git a/target/linux/adm5120/patches-3.18/101-cfi_fixup_macronix_bootloc.patch b/target/linux/adm5120/patches-3.18/101-cfi_fixup_macronix_bootloc.patch new file mode 100644 index 0000000..a0caa68 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/101-cfi_fixup_macronix_bootloc.patch @@ -0,0 +1,84 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -49,6 +49,12 @@ + #define SST49LF008A 0x005a + #define AT49BV6416 0x00d6 + ++/* Macronix */ ++#define MX29LV160B 0x2249 /* MX29LV160 Bottom-boot chip */ ++#define MX29LV160T 0x22C4 /* MX29LV160 Top-boot chip */ ++#define MX29LV320B 0x22A8 /* MX29LV320 Bottom-boot chip */ ++#define MX29LV320T 0x22A7 /* MX29LV320 Top-boot chip */ ++ + static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); + static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); + static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); +@@ -374,6 +380,41 @@ static struct cfi_fixup cfi_nopri_fixup_ + { 0, 0, NULL } + }; + ++#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC ++/* ++ * Some Macronix chips has no/bad bootblock information in the CFI table ++ */ ++static void fixup_macronix_bootloc(struct mtd_info *mtd) ++{ ++ struct map_info *map = mtd->priv; ++ struct cfi_private *cfi = map->fldrv_priv; ++ struct cfi_pri_amdstd *extp = cfi->cmdset_priv; ++ __u8 t; ++ ++ switch (cfi->id) { ++ /* TODO: put affected chip ids here */ ++ case MX29LV160B: ++ case MX29LV320B: ++ t = 2; /* Bottom boot */ ++ break; ++ case MX29LV160T: ++ case MX29LV320T: ++ t = 3; /* Top boot */ ++ break; ++ default: ++ return; ++ } ++ ++ if (extp->TopBottom == t) ++ /* boot location detected by the CFI layer is correct */ ++ return; ++ ++ extp->TopBottom = t; ++ printk("%s: Macronix chip detected, id:0x%04X, boot location forced " ++ "to %s\n", map->name, cfi->id, (t == 2) ? "bottom" : "top"); ++} ++#endif /* CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC */ ++ + static struct cfi_fixup cfi_fixup_table[] = { + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri }, + #ifdef AMD_BOOTLOC_BUG +@@ -416,6 +457,9 @@ static struct cfi_fixup fixup_table[] = + */ + { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip }, + { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock }, ++#ifdef CONFIG_MTD_CFI_FIXUP_MACRONIX_BOOTLOC ++ { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_macronix_bootloc }, ++#endif + { 0, 0, NULL } + }; + +--- a/drivers/mtd/chips/Kconfig ++++ b/drivers/mtd/chips/Kconfig +@@ -188,6 +188,14 @@ config MTD_CFI_AMDSTD + provides support for command set 0002, used on chips including + the AMD Am29LV320. + ++config MTD_CFI_FIXUP_MACRONIX_BOOTLOC ++ bool "Fix boot-block location for Macronix flash chips" ++ depends on MTD_CFI_AMDSTD ++ help ++ Some Macronix flash chips have no/wrong boot-block location in the ++ CFI table, and the driver may detect the type incorrectly. Select ++ this if your board has such chip. ++ + config MTD_CFI_STAA + tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)" + depends on MTD_GEN_PROBE diff --git a/target/linux/adm5120/patches-3.18/102-jedec_pmc_39lvxxx_chips.patch b/target/linux/adm5120/patches-3.18/102-jedec_pmc_39lvxxx_chips.patch new file mode 100644 index 0000000..00148fa --- /dev/null +++ b/target/linux/adm5120/patches-3.18/102-jedec_pmc_39lvxxx_chips.patch @@ -0,0 +1,68 @@ +--- a/drivers/mtd/chips/jedec_probe.c ++++ b/drivers/mtd/chips/jedec_probe.c +@@ -115,6 +115,10 @@ + #define UPD29F064115 0x221C + + /* PMC */ ++#define PM39LV512 0x001B ++#define PM39LV010 0x001C ++#define PM39LV020 0x003D ++#define PM39LV040 0x003E + #define PM49FL002 0x006D + #define PM49FL004 0x006E + #define PM49FL008 0x006A +@@ -1259,6 +1263,54 @@ static const struct amd_flash_info jedec + ERASEINFO(0x02000,2), + ERASEINFO(0x04000,1), + } ++ }, { ++ .mfr_id = CFI_MFR_PMC, ++ .dev_id = PM39LV512, ++ .name = "PMC Pm39LV512", ++ .devtypes = CFI_DEVICETYPE_X8, ++ .uaddr = MTD_UADDR_0x0555_0x02AA, ++ .dev_size = SIZE_64KiB, ++ .cmd_set = P_ID_AMD_STD, ++ .nr_regions = 1, ++ .regions = { ++ ERASEINFO(0x01000,16), ++ } ++ }, { ++ .mfr_id = CFI_MFR_PMC, ++ .dev_id = PM39LV010, ++ .name = "PMC Pm39LV010", ++ .devtypes = CFI_DEVICETYPE_X8, ++ .uaddr = MTD_UADDR_0x0555_0x02AA, ++ .dev_size = SIZE_128KiB, ++ .cmd_set = P_ID_AMD_STD, ++ .nr_regions = 1, ++ .regions = { ++ ERASEINFO(0x01000,32), ++ } ++ }, { ++ .mfr_id = CFI_MFR_PMC, ++ .dev_id = PM39LV020, ++ .name = "PMC Pm39LV020", ++ .devtypes = CFI_DEVICETYPE_X8, ++ .uaddr = MTD_UADDR_0x0555_0x02AA, ++ .dev_size = SIZE_256KiB, ++ .cmd_set = P_ID_AMD_STD, ++ .nr_regions = 1, ++ .regions = { ++ ERASEINFO(0x01000,64), ++ } ++ }, { ++ .mfr_id = CFI_MFR_PMC, ++ .dev_id = PM39LV040, ++ .name = "PMC Pm39LV040", ++ .devtypes = CFI_DEVICETYPE_X8, ++ .uaddr = MTD_UADDR_0x0555_0x02AA, ++ .dev_size = SIZE_512KiB, ++ .cmd_set = P_ID_AMD_STD, ++ .nr_regions = 1, ++ .regions = { ++ ERASEINFO(0x01000,128), ++ } + }, { + .mfr_id = CFI_MFR_PMC, + .dev_id = PM49FL002, diff --git a/target/linux/adm5120/patches-3.18/103-mtd_trxsplit.patch b/target/linux/adm5120/patches-3.18/103-mtd_trxsplit.patch new file mode 100644 index 0000000..6266776 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/103-mtd_trxsplit.patch @@ -0,0 +1,23 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -60,6 +60,10 @@ config MTD_ROOTFS_SPLIT + bool "Automatically split 'rootfs' partition for squashfs" + default y + ++config MTD_TRXSPLIT ++ bool "Automatically find and split TRX partitions" ++ default n ++ + config MTD_REDBOOT_PARTS + tristate "RedBoot partition table parsing" + ---help--- +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_TRXSPLIT) += trxsplit.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/adm5120/patches-3.18/120-rb153_cf_driver.patch b/target/linux/adm5120/patches-3.18/120-rb153_cf_driver.patch new file mode 100644 index 0000000..c5d4d3a --- /dev/null +++ b/target/linux/adm5120/patches-3.18/120-rb153_cf_driver.patch @@ -0,0 +1,28 @@ +--- a/drivers/ata/Makefile ++++ b/drivers/ata/Makefile +@@ -98,6 +98,7 @@ obj-$(CONFIG_PATA_PCMCIA) += pata_pcmcia + obj-$(CONFIG_PATA_PALMLD) += pata_palmld.o + obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o + obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o ++obj-$(CONFIG_PATA_RB153_CF) += pata_rb153_cf.o + obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o + obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o + obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -955,6 +955,15 @@ config PATA_QDI + help + Support for QDI 6500 and 6580 PATA controllers on VESA local bus. + ++config PATA_RB153_CF ++ tristate "RouterBOARD 153 Compact Flash support" ++ depends on ADM5120_MACH_RB_153 ++ help ++ This option enables support for a Compact Flash connected on ++ the RouterBOARD 153. ++ ++ If unsure, say N. ++ + config PATA_RB532 + tristate "RouterBoard 532 PATA CompactFlash support" + depends on MIKROTIK_RB532 diff --git a/target/linux/adm5120/patches-3.18/200-amba_pl010_hacks.patch b/target/linux/adm5120/patches-3.18/200-amba_pl010_hacks.patch new file mode 100644 index 0000000..8eee7a1 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/200-amba_pl010_hacks.patch @@ -0,0 +1,354 @@ +--- a/drivers/tty/serial/amba-pl010.c ++++ b/drivers/tty/serial/amba-pl010.c +@@ -48,11 +48,9 @@ + #include + #include + +-#define UART_NR 8 +- + #define SERIAL_AMBA_MAJOR 204 + #define SERIAL_AMBA_MINOR 16 +-#define SERIAL_AMBA_NR UART_NR ++#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS + + #define AMBA_ISR_PASS_LIMIT 256 + +@@ -78,9 +76,9 @@ static void pl010_stop_tx(struct uart_po + struct uart_amba_port *uap = (struct uart_amba_port *)port; + unsigned int cr; + +- cr = readb(uap->port.membase + UART010_CR); ++ cr = __raw_readl(uap->port.membase + UART010_CR); + cr &= ~UART010_CR_TIE; +- writel(cr, uap->port.membase + UART010_CR); ++ __raw_writel(cr, uap->port.membase + UART010_CR); + } + + static void pl010_start_tx(struct uart_port *port) +@@ -88,9 +86,9 @@ static void pl010_start_tx(struct uart_p + struct uart_amba_port *uap = (struct uart_amba_port *)port; + unsigned int cr; + +- cr = readb(uap->port.membase + UART010_CR); ++ cr = __raw_readl(uap->port.membase + UART010_CR); + cr |= UART010_CR_TIE; +- writel(cr, uap->port.membase + UART010_CR); ++ __raw_writel(cr, uap->port.membase + UART010_CR); + } + + static void pl010_stop_rx(struct uart_port *port) +@@ -98,9 +96,9 @@ static void pl010_stop_rx(struct uart_po + struct uart_amba_port *uap = (struct uart_amba_port *)port; + unsigned int cr; + +- cr = readb(uap->port.membase + UART010_CR); ++ cr = __raw_readl(uap->port.membase + UART010_CR); + cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); +- writel(cr, uap->port.membase + UART010_CR); ++ __raw_writel(cr, uap->port.membase + UART010_CR); + } + + static void pl010_enable_ms(struct uart_port *port) +@@ -108,18 +106,18 @@ static void pl010_enable_ms(struct uart_ + struct uart_amba_port *uap = (struct uart_amba_port *)port; + unsigned int cr; + +- cr = readb(uap->port.membase + UART010_CR); ++ cr = __raw_readl(uap->port.membase + UART010_CR); + cr |= UART010_CR_MSIE; +- writel(cr, uap->port.membase + UART010_CR); ++ __raw_writel(cr, uap->port.membase + UART010_CR); + } + + static void pl010_rx_chars(struct uart_amba_port *uap) + { + unsigned int status, ch, flag, rsr, max_count = 256; + +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + while (UART_RX_DATA(status) && max_count--) { +- ch = readb(uap->port.membase + UART01x_DR); ++ ch = __raw_readl(uap->port.membase + UART01x_DR); + flag = TTY_NORMAL; + + uap->port.icount.rx++; +@@ -128,9 +126,9 @@ static void pl010_rx_chars(struct uart_a + * Note that the error handling code is + * out of the main execution path + */ +- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; ++ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; + if (unlikely(rsr & UART01x_RSR_ANY)) { +- writel(0, uap->port.membase + UART01x_ECR); ++ __raw_writel(0, uap->port.membase + UART01x_ECR); + + if (rsr & UART01x_RSR_BE) { + rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); +@@ -160,7 +158,7 @@ static void pl010_rx_chars(struct uart_a + uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); + + ignore_char: +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + } + spin_unlock(&uap->port.lock); + tty_flip_buffer_push(&uap->port.state->port); +@@ -173,7 +171,7 @@ static void pl010_tx_chars(struct uart_a + int count; + + if (uap->port.x_char) { +- writel(uap->port.x_char, uap->port.membase + UART01x_DR); ++ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR); + uap->port.icount.tx++; + uap->port.x_char = 0; + return; +@@ -185,7 +183,7 @@ static void pl010_tx_chars(struct uart_a + + count = uap->port.fifosize >> 1; + do { +- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); ++ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + uap->port.icount.tx++; + if (uart_circ_empty(xmit)) +@@ -203,9 +201,9 @@ static void pl010_modem_status(struct ua + { + unsigned int status, delta; + +- writel(0, uap->port.membase + UART010_ICR); ++ __raw_writel(0, uap->port.membase + UART010_ICR); + +- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; ++ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; + + delta = status ^ uap->old_status; + uap->old_status = status; +@@ -233,7 +231,7 @@ static irqreturn_t pl010_int(int irq, vo + + spin_lock(&uap->port.lock); + +- status = readb(uap->port.membase + UART010_IIR); ++ status = __raw_readl(uap->port.membase + UART010_IIR); + if (status) { + do { + if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) +@@ -246,7 +244,7 @@ static irqreturn_t pl010_int(int irq, vo + if (pass_counter-- == 0) + break; + +- status = readb(uap->port.membase + UART010_IIR); ++ status = __raw_readl(uap->port.membase + UART010_IIR); + } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | + UART010_IIR_TIS)); + handled = 1; +@@ -260,7 +258,7 @@ static irqreturn_t pl010_int(int irq, vo + static unsigned int pl010_tx_empty(struct uart_port *port) + { + struct uart_amba_port *uap = (struct uart_amba_port *)port; +- unsigned int status = readb(uap->port.membase + UART01x_FR); ++ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR); + return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; + } + +@@ -270,7 +268,7 @@ static unsigned int pl010_get_mctrl(stru + unsigned int result = 0; + unsigned int status; + +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + if (status & UART01x_FR_DCD) + result |= TIOCM_CAR; + if (status & UART01x_FR_DSR) +@@ -296,12 +294,12 @@ static void pl010_break_ctl(struct uart_ + unsigned int lcr_h; + + spin_lock_irqsave(&uap->port.lock, flags); +- lcr_h = readb(uap->port.membase + UART010_LCRH); ++ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH); + if (break_state == -1) + lcr_h |= UART01x_LCRH_BRK; + else + lcr_h &= ~UART01x_LCRH_BRK; +- writel(lcr_h, uap->port.membase + UART010_LCRH); ++ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH); + spin_unlock_irqrestore(&uap->port.lock, flags); + } + +@@ -329,12 +327,12 @@ static int pl010_startup(struct uart_por + /* + * initialise the old status of the modem signals + */ +- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; ++ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; + + /* + * Finally, enable interrupts + */ +- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, ++ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, + uap->port.membase + UART010_CR); + + return 0; +@@ -357,10 +355,10 @@ static void pl010_shutdown(struct uart_p + /* + * disable all interrupts, disable the port + */ +- writel(0, uap->port.membase + UART010_CR); ++ __raw_writel(0, uap->port.membase + UART010_CR); + + /* disable break condition and fifos */ +- writel(readb(uap->port.membase + UART010_LCRH) & ++ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) & + ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), + uap->port.membase + UART010_LCRH); + +@@ -382,7 +380,7 @@ pl010_set_termios(struct uart_port *port + /* + * Ask the core to calculate the divisor for us. + */ +- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); ++ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); + quot = uart_get_divisor(port, baud); + + switch (termios->c_cflag & CSIZE) { +@@ -445,25 +443,25 @@ pl010_set_termios(struct uart_port *port + uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; + + /* first, disable everything */ +- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; ++ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; + + if (UART_ENABLE_MS(port, termios->c_cflag)) + old_cr |= UART010_CR_MSIE; + +- writel(0, uap->port.membase + UART010_CR); ++ __raw_writel(0, uap->port.membase + UART010_CR); + + /* Set baud rate */ + quot -= 1; +- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); +- writel(quot & 0xff, uap->port.membase + UART010_LCRL); ++ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); ++ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL); + + /* + * ----------v----------v----------v----------v----- + * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L + * ----------^----------^----------^----------^----- + */ +- writel(lcr_h, uap->port.membase + UART010_LCRH); +- writel(old_cr, uap->port.membase + UART010_CR); ++ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH); ++ __raw_writel(old_cr, uap->port.membase + UART010_CR); + + spin_unlock_irqrestore(&uap->port.lock, flags); + } +@@ -545,7 +543,7 @@ static struct uart_ops amba_pl010_pops = + .verify_port = pl010_verify_port, + }; + +-static struct uart_amba_port *amba_ports[UART_NR]; ++static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR]; + + #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE + +@@ -555,10 +553,10 @@ static void pl010_console_putchar(struct + unsigned int status; + + do { +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + barrier(); + } while (!UART_TX_READY(status)); +- writel(ch, uap->port.membase + UART01x_DR); ++ __raw_writel(ch, uap->port.membase + UART01x_DR); + } + + static void +@@ -572,8 +570,8 @@ pl010_console_write(struct console *co, + /* + * First save the CR then disable the interrupts + */ +- old_cr = readb(uap->port.membase + UART010_CR); +- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); ++ old_cr = __raw_readl(uap->port.membase + UART010_CR); ++ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); + + uart_console_write(&uap->port, s, count, pl010_console_putchar); + +@@ -582,10 +580,10 @@ pl010_console_write(struct console *co, + * and restore the TCR + */ + do { +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + barrier(); + } while (status & UART01x_FR_BUSY); +- writel(old_cr, uap->port.membase + UART010_CR); ++ __raw_writel(old_cr, uap->port.membase + UART010_CR); + + clk_disable(uap->clk); + } +@@ -594,9 +592,9 @@ static void __init + pl010_console_get_options(struct uart_amba_port *uap, int *baud, + int *parity, int *bits) + { +- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { ++ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { + unsigned int lcr_h, quot; +- lcr_h = readb(uap->port.membase + UART010_LCRH); ++ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH); + + *parity = 'n'; + if (lcr_h & UART01x_LCRH_PEN) { +@@ -611,8 +609,8 @@ pl010_console_get_options(struct uart_am + else + *bits = 8; + +- quot = readb(uap->port.membase + UART010_LCRL) | +- readb(uap->port.membase + UART010_LCRM) << 8; ++ quot = __raw_readl(uap->port.membase + UART010_LCRL) | ++ __raw_readl(uap->port.membase + UART010_LCRM) << 8; + *baud = uap->port.uartclk / (16 * (quot + 1)); + } + } +@@ -631,7 +629,7 @@ static int __init pl010_console_setup(st + * if so, search for the first available port that does have + * console support. + */ +- if (co->index >= UART_NR) ++ if (co->index >= SERIAL_AMBA_NR) + co->index = 0; + uap = amba_ports[co->index]; + if (!uap) +@@ -673,7 +671,7 @@ static struct uart_driver amba_reg = { + .dev_name = "ttyAM", + .major = SERIAL_AMBA_MAJOR, + .minor = SERIAL_AMBA_MINOR, +- .nr = UART_NR, ++ .nr = SERIAL_AMBA_NR, + .cons = AMBA_CONSOLE, + }; + +--- a/drivers/tty/serial/Kconfig ++++ b/drivers/tty/serial/Kconfig +@@ -25,10 +25,18 @@ config SERIAL_AMBA_PL010 + help + This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have + an Integrator/AP or Integrator/PP2 platform, or if you have a +- Cirrus Logic EP93xx CPU, say Y or M here. ++ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here. + + If unsure, say N. + ++config SERIAL_AMBA_PL010_NUMPORTS ++ int "Maximum number of AMBA PL010 serial ports" ++ depends on SERIAL_AMBA_PL010 ++ default "8" ++ ---help--- ++ Set this to the number of serial ports you want the AMBA PL010 driver ++ to support. ++ + config SERIAL_AMBA_PL010_CONSOLE + bool "Support for console on AMBA serial port" + depends on SERIAL_AMBA_PL010=y diff --git a/target/linux/adm5120/patches-3.18/203-gpio_leds_brightness.patch b/target/linux/adm5120/patches-3.18/203-gpio_leds_brightness.patch new file mode 100644 index 0000000..5345022 --- /dev/null +++ b/target/linux/adm5120/patches-3.18/203-gpio_leds_brightness.patch @@ -0,0 +1,27 @@ +--- a/drivers/leds/leds-gpio.c ++++ b/drivers/leds/leds-gpio.c +@@ -55,13 +55,17 @@ static void gpio_led_set(struct led_clas + container_of(led_cdev, struct gpio_led_data, cdev); + int level; + +- if (value == LED_OFF) +- level = 0; +- else +- level = 1; +- +- if (led_dat->active_low) +- level = !level; ++ switch (value) { ++ case LED_OFF: ++ level = led_dat->active_low ? 1 : 0; ++ break; ++ case LED_FULL: ++ level = led_dat->active_low ? 0 : 1; ++ break; ++ default: ++ level = value; ++ break; ++ } + + /* Setting GPIOs with I2C/etc requires a task context, and we don't + * seem to have a reliable way to know if we're already in one; so diff --git a/target/linux/adm5120/patches-3.18/310-adm5120_wdt.patch b/target/linux/adm5120/patches-3.18/310-adm5120_wdt.patch new file mode 100644 index 0000000..4b6db8b --- /dev/null +++ b/target/linux/adm5120/patches-3.18/310-adm5120_wdt.patch @@ -0,0 +1,31 @@ +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1116,6 +1116,18 @@ config RC32434_WDT + To compile this driver as a module, choose M here: the + module will be called rc32434_wdt. + ++config ADM5120_WDT ++ tristate "Infineon ADM5120 SoC hardware watchdog" ++ depends on WATCHDOG && ADM5120 ++ help ++ This is a driver for hardware watchdog integrated in Infineon ++ ADM5120 SoC. This watchdog simply watches your kernel to make sure ++ it doesn't freeze, and if it does, it reboots your computer after a ++ certain amount of time. ++ ++ To compile this driver as a module, choose M here: the module will be ++ called adm5120_wdt. ++ + config INDYDOG + tristate "Indy/I2 Hardware Watchdog" + depends on SGI_HAS_INDYDOG +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -131,6 +131,7 @@ obj-$(CONFIG_ATH79_WDT) += ath79_wdt.o + obj-$(CONFIG_BCM47XX_WDT) += bcm47xx_wdt.o + obj-$(CONFIG_BCM63XX_WDT) += bcm63xx_wdt.o + obj-$(CONFIG_RC32434_WDT) += rc32434_wdt.o ++obj-$(CONFIG_ADM5120_WDT) += adm5120_wdt.o + obj-$(CONFIG_INDYDOG) += indydog.o + obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o + obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o diff --git a/target/linux/adm5120/rb1xx/base-files/sbin/wget2nand b/target/linux/adm5120/rb1xx/base-files/sbin/wget2nand new file mode 100755 index 0000000..f7e0a09 --- /dev/null +++ b/target/linux/adm5120/rb1xx/base-files/sbin/wget2nand @@ -0,0 +1,78 @@ +#!/bin/sh +# wget2nand +# This script can be used to download a TGZ file from your build system which +# contains the files to be installed on the NAND flash on your RB1xx card. +# The one parameter is the URL of the TGZ file to be downloaded. +# Licence GPL V2 +# Author david.goodenough@linkchoose.co.uk +# Based on cf2nand from RB532 support +. /lib/functions.sh + +[ -d /tmp/wget2nand-rootfs ] && { + echo "/tmp/wget2nand-rootfs already exists" + exit 1 +} + +[ -d /tmp/wget2nand-kernel ] && { + echo "/tmp/wget2nand-kernel already exists" + exit 1 +} + +# need to find the wget server from the command line +url=$1 +[ -z "$url" ] && { + echo "No URL specified for image TGZ" + echo "Usage : $0 URL" + exit 1 +} + +# first get an address for br-lan using udhcpc +killall udhcpc +/sbin/udhcpc -i br-lan + +mtd_kernel="$(find_mtd_part 'kernel')" +mtd_rootfs="$(find_mtd_part 'rootfs')" +[ -z "$mtd_kernel" -o -z "$mtd_rootfs" ] && { + echo "Cannot find NAND Flash partitions" + exit 1 +} + +echo "Erasing filesystem..." +mtd erase kernel 2>/dev/null >/dev/null +mtd erase rootfs 2>/dev/null >/dev/null + +echo "Mounting $mtd_rootfs as new root and $mtd_kernel as kernel partition" + +mkdir /tmp/wget2nand-rootfs +mkdir /tmp/wget2nand-kernel +mount -t yaffs2 "$mtd_rootfs" /tmp/wget2nand-rootfs +mount -t yaffs2 "$mtd_kernel" /tmp/wget2nand-kernel + +echo "Erasing existing files..." +rm -rf /tmp/wget2nand-rootfs/* + +echo "Copying filesystem..." +( wget -O - $url/openwrt-adm5120-rb1xx-rootfs.tar.gz) | ( cd /tmp/wget2nand-rootfs/; tar xvz ) +# RouterBOOT is looking for a kernel named "kernel" +wget -O /tmp/wget2nand-kernel/kernel $url/openwrt-adm5120-rb1xx-vmlinux.elf + +chmod +x /tmp/wget2nand-kernel/kernel + +# make sure everything is written before we unmount the partitions +echo "chmod ugo+x /" > /tmp/wget2nand-rootfs/etc/uci-defaults/set_root_permission +sync +ls /tmp/wget2nand-kernel/ +ls /tmp/wget2nand-rootfs/ +# use kexec if present +[ -x /usr/sbin/kexec ] && { + kexec -l /tmp/wget2nand-kernel/kernel --command-line="$(cat /proc/cmdline) rootfstype=yaffs2 root=$mtd_kernel" + kexec -e +} +# unmount the partitions and remove the directories into which they were mounted +umount /tmp/wget2nand-kernel +umount /tmp/wget2nand-rootfs +rmdir /tmp/wget2nand-kernel +rmdir /tmp/wget2nand-rootfs + +# all done +echo "Image written, you can now reboot. Remember to change the boot source to Boot from Nand" diff --git a/target/linux/adm5120/rb1xx/config-default b/target/linux/adm5120/rb1xx/config-default new file mode 100644 index 0000000..37db0b3 --- /dev/null +++ b/target/linux/adm5120/rb1xx/config-default @@ -0,0 +1,52 @@ +# CONFIG_ADM5120_MACH_5GXI is not set +# CONFIG_ADM5120_MACH_BR_6104K is not set +# CONFIG_ADM5120_MACH_BR_6104KP is not set +# CONFIG_ADM5120_MACH_BR_61X4WG is not set +# CONFIG_ADM5120_MACH_CAS_771 is not set +# CONFIG_ADM5120_MACH_EASY5120P_ATA is not set +# CONFIG_ADM5120_MACH_EASY5120_RT is not set +# CONFIG_ADM5120_MACH_EASY5120_WVOIP is not set +# CONFIG_ADM5120_MACH_EASY83000 is not set +# CONFIG_ADM5120_MACH_EB_214A is not set +# CONFIG_ADM5120_MACH_NFS_101 is not set +# CONFIG_ADM5120_MACH_NP27G is not set +# CONFIG_ADM5120_MACH_NP28G is not set +# CONFIG_ADM5120_MACH_PMUGW is not set +CONFIG_ADM5120_MACH_RB_11X=y +CONFIG_ADM5120_MACH_RB_133=y +CONFIG_ADM5120_MACH_RB_133C=y +CONFIG_ADM5120_MACH_RB_150=y +CONFIG_ADM5120_MACH_RB_153=y +CONFIG_ADM5120_MACH_RB_192=y +# CONFIG_ADM5120_MACH_WP54 is not set +# CONFIG_ADM5120_OEM_CELLVISION is not set +# CONFIG_ADM5120_OEM_COMPEX is not set +# CONFIG_ADM5120_OEM_EDIMAX is not set +# CONFIG_ADM5120_OEM_GENERIC is not set +# CONFIG_ADM5120_OEM_INFINEON is not set +CONFIG_ADM5120_OEM_MIKROTIK=y +# CONFIG_ADM5120_OEM_MOTOROLA is not set +# CONFIG_ADM5120_OEM_OSBRIDGE is not set +CONFIG_CMDLINE="console=ttyAM0,115200 rootfstype=yaffs2" +# CONFIG_JFFS2_FS is not set +# CONFIG_MTD_MYLOADER_PARTS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ROOTFS_SPLIT is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_TRXSPLIT is not set +# CONFIG_OVERLAYFS_FS is not set +# CONFIG_PATA_RB153_CF is not set +# CONFIG_SQUASHFS is not set +CONFIG_YAFFS_9BYTE_TAGS=y +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_BACKGROUND is not set +# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set +CONFIG_YAFFS_DISABLE_TAGS_ECC=y +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_XATTR=y +CONFIG_YAFFS_YAFFS1=y +CONFIG_YAFFS_YAFFS2=y diff --git a/target/linux/adm5120/rb1xx/profiles/RB1xx.mk b/target/linux/adm5120/rb1xx/profiles/RB1xx.mk new file mode 100644 index 0000000..b9da164 --- /dev/null +++ b/target/linux/adm5120/rb1xx/profiles/RB1xx.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2007 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RouterBoard + NAME:=Mikrotik RouterBoard 1xx family + PACKAGES:=kmod-ath5k kmod-pata-rb153-cf +endef + +define Profile/RouterBoard/Description + Package set compatible with the RouterBoard RB1xx devices. Contains RouterOS to OpenWrt\\\ + installation scripts. +endef + +$(eval $(call Profile,RouterBoard)) diff --git a/target/linux/adm5120/rb1xx/target.mk b/target/linux/adm5120/rb1xx/target.mk new file mode 100644 index 0000000..34d10a9 --- /dev/null +++ b/target/linux/adm5120/rb1xx/target.mk @@ -0,0 +1,9 @@ +ARCH:=mipsel +ARCH_PACKAGES:=adm5120_mipsel +SUBTARGET:=rb1xx +BOARDNAME:=MikroTik RB-1xx boards +FEATURES+=tgz + +define Target/Description + Build firmware images for Mikrotik RB-1xx series. +endef diff --git a/target/linux/adm5120/router_be/config-default b/target/linux/adm5120/router_be/config-default new file mode 100644 index 0000000..c3b9e36 --- /dev/null +++ b/target/linux/adm5120/router_be/config-default @@ -0,0 +1,13 @@ +CONFIG_ADM5120_MACH_P_334WT=y +CONFIG_ADM5120_MACH_P_335=y +# CONFIG_ADM5120_OEM_CELLVISION is not set +# CONFIG_ADM5120_OEM_COMPEX is not set +# CONFIG_ADM5120_OEM_EDIMAX is not set +# CONFIG_ADM5120_OEM_GENERIC is not set +# CONFIG_ADM5120_OEM_INFINEON is not set +# CONFIG_ADM5120_OEM_MOTOROLA is not set +# CONFIG_ADM5120_OEM_OSBRIDGE is not set +CONFIG_ADM5120_OEM_ZYXEL=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SWAP_IO_SPACE=y diff --git a/target/linux/adm5120/router_be/profiles/010-Generic.mk b/target/linux/adm5120/router_be/profiles/010-Generic.mk new file mode 100644 index 0000000..1d47731 --- /dev/null +++ b/target/linux/adm5120/router_be/profiles/010-Generic.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2007 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Generic + NAME:=Generic (default) + PACKAGES:= +endef + +define Profile/Generic/Description + Generic package set compatible with most boards. +endef +$(eval $(call Profile,Generic)) + diff --git a/target/linux/adm5120/router_be/profiles/200-ZyXEL.mk b/target/linux/adm5120/router_be/profiles/200-ZyXEL.mk new file mode 100644 index 0000000..19ac9f5 --- /dev/null +++ b/target/linux/adm5120/router_be/profiles/200-ZyXEL.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2007 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/P334WT + NAME:=ZyXEL Prestige 334WT + PACKAGES:=kmod-acx-mac80211 +endef + +define Profile/P334WT/Description + Package set optimized for the ZyXEL Prestige 334WT board. +endef + +define Profile/P335WT + NAME:=ZyXEL Prestige 335WT + PACKAGES:=kmod-acx-mac80211 kmod-usb-core kmod-usb-adm5120 +endef + +define Profile/P335WT/Description + Package set optimized for the ZyXEL Prestige 335WT board. +endef + +$(eval $(call Profile,P334WT)) +$(eval $(call Profile,P335WT)) diff --git a/target/linux/adm5120/router_be/target.mk b/target/linux/adm5120/router_be/target.mk new file mode 100644 index 0000000..9cbf00b --- /dev/null +++ b/target/linux/adm5120/router_be/target.mk @@ -0,0 +1,11 @@ +ARCH:=mips +ARCH_PACKAGES:=adm5120_mips +SUBTARGET:=router_be +BOARDNAME:=Big Endian +FEATURES+=squashfs + +define Target/Description + Build firmware images for Infineon/ADMTek ADM5120 based boards + running in big-endian mode (e.g : ZyXEL Prestige 335WT ...) +endef + diff --git a/target/linux/adm5120/router_le/config-3.8 b/target/linux/adm5120/router_le/config-3.8 new file mode 100644 index 0000000..e69de29 diff --git a/target/linux/adm5120/router_le/profiles/010-Generic.mk b/target/linux/adm5120/router_le/profiles/010-Generic.mk new file mode 100644 index 0000000..6c3e5f3 --- /dev/null +++ b/target/linux/adm5120/router_le/profiles/010-Generic.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2007 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Generic + NAME:=Generic (default) + PACKAGES:= +endef + +define Profile/Generic/Description + Generic package set compatible with most boards. +endef + +define Profile/EB-214A + NAME:=Generic EB-214A + PACKAGES:=-wpad-mini -admswconfig -kmod-usb-adm5120 -kmod-ledtrig-adm5120-switch -dnsmasq kmod-usb-uhci kmod-usb2 +endef + +define Profile/EB-214A/Description + Package set optimized for generic EB-214A boards. +endef + +$(eval $(call Profile,Generic)) +$(eval $(call Profile,EB-214A)) + diff --git a/target/linux/adm5120/router_le/profiles/Cellvision.mk b/target/linux/adm5120/router_le/profiles/Cellvision.mk new file mode 100644 index 0000000..4093b4f --- /dev/null +++ b/target/linux/adm5120/router_le/profiles/Cellvision.mk @@ -0,0 +1,146 @@ +# +# Copyright (C) 2007-2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CAS630 + NAME:=Cellvision CAS-630 IP camera (Experimental) + # TODO: add default packages + PACKAGES:=-wpad-mini +endef + +define Profile/CAS630/Description + Package set optimized for the Cellvision CAS-630 device. +endef + +define Profile/CAS630W + NAME:=Cellvision CAS-630W IP camera (Experimental) + # TODO: add default packages + PACKAGES:=-wpad-mini +endef + +define Profile/CAS630W/Description + Package set optimized for the Cellvision CAS-630W device. +endef + +define Profile/CAS670 + NAME:=Cellvision CAS-670 IP camera (Experimental) + # TODO: add default packages + PACKAGES:=-wpad-mini +endef + +define Profile/CAS670/Description + Package set optimized for the Cellvision CAS-670 device. +endef + +define Profile/CAS670W + NAME:=Cellvision CAS-670W IP camera (Experimental) + # TODO: add default packages + PACKAGES:=-wpad-mini +endef + +define Profile/CAS670W/Description + Package set optimized for the Cellvision CAS-670 device. +endef + +define Profile/CAS700 + NAME:=Cellvision CAS-700 IP camera (Experimental) + # TODO: add default packages + PACKAGES:=-wpad-mini +endef + +define Profile/CAS700/Description + Package set optimized for the Cellvision CAS-700 device. +endef + +define Profile/CAS700W + NAME:=Cellvision CAS-700W IP camera (Experimental) + # TODO: add default packages + PACKAGES:=-wpad-mini +endef + +define Profile/CAS700W/Description + Package set optimized for the Cellvision CAS-700W device. +endef + +define Profile/CAS771 + NAME:=Cellvision CAS-771 IP camera (Experimental) + PACKAGES:=-wpad-mini kmod-video-cpia2 kmod-usb-ohci kmod-usb2 kmod-usb-audio +endef + +define Profile/CAS771/Description + Package set optimized for the Cellvision CAS-771 device. +endef + +define Profile/CAS771W + NAME:=Cellvision CAS-771W IP camera (Experimental) + PACKAGES:=-wpad-mini kmod-video-cpia2 kmod-usb-ohci kmod-usb2 kmod-usb-audio kmod-rt2500-pci +endef + +define Profile/CAS771W/Description + Package set optimized for the Cellvision CAS-771W device. +endef + +define Profile/CAS790 + NAME:=Cellvision CAS-790 IP camera (Experimental) + # TODO: add default packages + PACKAGES:=-wpad-mini +endef + +define Profile/CAS790/Description + Package set optimized for the Cellvision CAS-790 device. +endef + +define Profile/CAS861 + NAME:=Cellvision CAS-861 IP camera (Experimental) + # TODO: add default packages + PACKAGES:=-wpad-mini +endef + +define Profile/CAS861/Description + Package set optimized for the Cellvision CAS-861 device. +endef + +define Profile/CAS861W + NAME:=Cellvision CAS-861W IP camera (Experimental) + PACKAGES:=kmod-rt2500-pci +endef + +define Profile/CAS861W/Description + Package set optimized for the Cellvision CAS-861W device. +endef + +define Profile/NFS101U + NAME:=Cellvision NFS-101U Network File Server (Experimental) + PACKAGES:=-wpad-mini kmod-usb-ohci kmod-usb2 +endef + +define Profile/NFS101U/Description + Package set optimized for the Cellvision NFS-101U device. +endef + +define Profile/NFS101WU + NAME:=Cellvision NFS-101WU Network File Server (Experimental) + PACKAGES:=-wpad-mini kmod-usb-ohci kmod-usb2 +endef + +define Profile/NFS101WU/Description + Package set optimized for the Cellvision NFS-101WU device. +endef + +$(eval $(call Profile,CAS630)) +$(eval $(call Profile,CAS630W)) +$(eval $(call Profile,CAS670)) +$(eval $(call Profile,CAS670W)) +$(eval $(call Profile,CAS700)) +$(eval $(call Profile,CAS700W)) +$(eval $(call Profile,CAS771)) +$(eval $(call Profile,CAS771W)) +$(eval $(call Profile,CAS790)) +$(eval $(call Profile,CAS861)) +$(eval $(call Profile,CAS861W)) +$(eval $(call Profile,NFS101U)) +$(eval $(call Profile,NFS101WU)) + diff --git a/target/linux/adm5120/router_le/profiles/Compex.mk b/target/linux/adm5120/router_le/profiles/Compex.mk new file mode 100644 index 0000000..79d1f3f --- /dev/null +++ b/target/linux/adm5120/router_le/profiles/Compex.mk @@ -0,0 +1,37 @@ +# +# Copyright (C) 2007 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/NP27G + NAME:=Compex NP27G + PACKAGES:=kmod-ath5k kmod-usb-core kmod-usb-adm5120 +endef + +define Profile/NP27G/Description + Package set optimized for the Compex NP27G. +endef + +define Profile/NP28G + NAME:=Compex NP28G + PACKAGES:=kmod-ath5k kmod-usb-core kmod-usb-uhci kmod-usb2 +endef + +define Profile/NP28G/Description + Package set optimized for the Compex NP28G. +endef + +define Profile/WP54 + NAME:=Compex WP54 family + PACKAGES:=kmod-ath5k +endef + +define Profile/WP54/Description + Package set optimized for the Compex WP54 family. +endef + +$(eval $(call Profile,NP27G)) +$(eval $(call Profile,NP28G)) +$(eval $(call Profile,WP54)) diff --git a/target/linux/adm5120/router_le/profiles/Edimax.mk b/target/linux/adm5120/router_le/profiles/Edimax.mk new file mode 100644 index 0000000..55c2958 --- /dev/null +++ b/target/linux/adm5120/router_le/profiles/Edimax.mk @@ -0,0 +1,47 @@ +# +# Copyright (C) 2007,2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/BR6104K + NAME:=Edimax BR-6104K (Unofficial) + PACKAGES:=-wpad-mini +endef + +define Profile/BR6104K/Description + Package set optimized for the Edimax BR-6104K +endef + +define Profile/BR6104KP + NAME:=Edimax BR-6104KP (Unofficial) + PACKAGES:=-wpad-mini kmod-usb-core kmod-usb-adm5120 +endef + +define Profile/BR6104KP/Description + Package set optimized for the Edimax BR-6104KP +endef + +define Profile/BR6104WG + NAME:=Edimax BR-6104Wg (Unofficial, No WiFi) + PACKAGES:=-wpad-mini +endef + +define Profile/BR6104WG/Description + Package set optimized for the Edimax BR-6104Wg +endef + +define Profile/BR6114WG + NAME:=Edimax BR-6114WG (Unofficial, No WiFi) + PACKAGES:=-wpad-mini +endef + +define Profile/BR6114WG/Description + Package set optimized for the Edimax BR-6114WG +endef + +$(eval $(call Profile,BR6104K)) +$(eval $(call Profile,BR6104KP)) +$(eval $(call Profile,BR6104WG)) +$(eval $(call Profile,BR6114WG)) diff --git a/target/linux/adm5120/router_le/profiles/Infineon.mk b/target/linux/adm5120/router_le/profiles/Infineon.mk new file mode 100644 index 0000000..d650406 --- /dev/null +++ b/target/linux/adm5120/router_le/profiles/Infineon.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/EASY5120RT + NAME:=Infineon EASY 5120-RT Reference Board + PACKAGES:=kmod-usb-core kmod-usb-adm5120 +endef + +define Profile/EASY5120RT/Description + Package set optimized for the Infineon EASY 5120-RT Reference Board +endef + +$(eval $(call Profile,EASY5120RT)) + +define Profile/EASY5120PATA + NAME:=Infineon EASY 5120P-ATA Reference Board +endef + +define Profile/EASY5120RT/Description + Package set optimized for the Infineon EASY 5120P-ATA Reference Board +endef + +$(eval $(call Profile,EASY5120PATA)) diff --git a/target/linux/adm5120/router_le/profiles/Motorola.mk b/target/linux/adm5120/router_le/profiles/Motorola.mk new file mode 100644 index 0000000..e640b81 --- /dev/null +++ b/target/linux/adm5120/router_le/profiles/Motorola.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/PMUGW + NAME:=Motorola Powerline MU Gateway (EXPERIMENTAL) +endef + +define Profile/PMUGW/Description + Package set optimized for the Motorola Powerline MU Gateway board +endef + +$(eval $(call Profile,PMUGW)) diff --git a/target/linux/adm5120/router_le/profiles/Osbridge.mk b/target/linux/adm5120/router_le/profiles/Osbridge.mk new file mode 100644 index 0000000..459d524 --- /dev/null +++ b/target/linux/adm5120/router_le/profiles/Osbridge.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2007-2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/5GXI + NAME:=Osbridge 5GXi/5XLi (Unofficial) +endef + +define Profile/5GXI/Description + Package set optimized for the OSBRiDGE 5GXi/5XLi boards. +endef + +$(eval $(call Profile,5GXI)) diff --git a/target/linux/adm5120/router_le/target.mk b/target/linux/adm5120/router_le/target.mk new file mode 100644 index 0000000..6847d00 --- /dev/null +++ b/target/linux/adm5120/router_le/target.mk @@ -0,0 +1,11 @@ +ARCH:=mipsel +ARCH_PACKAGES:=adm5120_mipsel +SUBTARGET:=router_le +BOARDNAME:=Little Endian +FEATURES+=squashfs tgz + +define Target/Description + Build firmware images for Infineon/ADMtek ADM5120 based boards + running in little-endian mode (e.g: RouterBoard RB1xx, Compex WP54x ...) +endef + diff --git a/target/linux/adm8668/Makefile b/target/linux/adm8668/Makefile new file mode 100644 index 0000000..9695838 --- /dev/null +++ b/target/linux/adm8668/Makefile @@ -0,0 +1,24 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mipsel +BOARD:=adm8668 +BOARDNAME:=Infineon WildPass ADM8668 +FEATURES:=squashfs usb pci +MAINTAINER:=Florian Fainelli + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +define Target/Description + Build firmware images for Infineon WildPass (ADM8668) based routers + (e.g. T-Mobile branded Linksys WRTU54G-TM) +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/adm8668/base-files.mk b/target/linux/adm8668/base-files.mk new file mode 100644 index 0000000..a096236 --- /dev/null +++ b/target/linux/adm8668/base-files.mk @@ -0,0 +1,3 @@ +#define Package/base-files/install-target +# rm -f $(1)/etc/config/network +#endef diff --git a/target/linux/adm8668/base-files/etc/config/network b/target/linux/adm8668/base-files/etc/config/network new file mode 100644 index 0000000..5967cdd --- /dev/null +++ b/target/linux/adm8668/base-files/etc/config/network @@ -0,0 +1,24 @@ +config interface loopback + option ifname lo + option proto static + option ipaddr 127.0.0.1 + option netmask 255.0.0.0 + +config interface lan + option ifname eth0 + option type bridge + option proto static + option ipaddr 192.168.1.1 + option netmask 255.255.255.0 + option ip6assign 60 + +config interface wan + option ifname eth1 + option proto dhcp + +config interface wan6 + option ifname eth1 + option proto dhcpv6 + +config globals globals + option ula_prefix auto diff --git a/target/linux/adm8668/base-files/etc/diag.sh b/target/linux/adm8668/base-files/etc/diag.sh new file mode 100644 index 0000000..edcc753 --- /dev/null +++ b/target/linux/adm8668/base-files/etc/diag.sh @@ -0,0 +1,21 @@ +#!/bin/sh +# Copyright (C) 2010 OpenWrt.org + +set_led() { + local state="$1" + [ -f "/proc/adm8668/sesled" ] && echo "$state" > "/proc/adm8668/sesled" +} + +set_state() { + case "$1" in + preinit) + set_led 1 + ;; + failsafe) + set_led 2 + ;; + done) + set_led 0 + ;; + esac +} diff --git a/target/linux/adm8668/base-files/lib/preinit/03_init_hotplug_failsafe_adm8668 b/target/linux/adm8668/base-files/lib/preinit/03_init_hotplug_failsafe_adm8668 new file mode 100644 index 0000000..b0f4a4e --- /dev/null +++ b/target/linux/adm8668/base-files/lib/preinit/03_init_hotplug_failsafe_adm8668 @@ -0,0 +1,9 @@ +#!/bin/sh + +init_hotplug_failsafe() { + echo '/sbin/hotplug.failsafe' > /proc/sys/kernel/hotplug +} + +boot_hook_add preinit_main init_hotplug_failsafe + + diff --git a/target/linux/adm8668/base-files/lib/preinit/05_set_preinit_face_adm8668 b/target/linux/adm8668/base-files/lib/preinit/05_set_preinit_face_adm8668 new file mode 100644 index 0000000..ac2a7cb --- /dev/null +++ b/target/linux/adm8668/base-files/lib/preinit/05_set_preinit_face_adm8668 @@ -0,0 +1,9 @@ +#!/bin/sh + +set_preinit_ifname() { + ifname=eth0 +} + +boot_hook_add preinit_main set_preinit_ifname + + diff --git a/target/linux/adm8668/base-files/lib/upgrade/platform.sh b/target/linux/adm8668/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..98e47ad --- /dev/null +++ b/target/linux/adm8668/base-files/lib/upgrade/platform.sh @@ -0,0 +1,15 @@ +PART_NAME=linux +platform_check_image() { + [ "$#" -gt 1 ] && return 1 + + case "$(get_magic_word "$1")" in + # u-boot + 2705) return 0;; + *) + echo "Invalid image type. Please use only u-boot files" + return 1 + ;; + esac +} + +# use default for platform_do_upgrade() diff --git a/target/linux/adm8668/base-files/sbin/hotplug.failsafe b/target/linux/adm8668/base-files/sbin/hotplug.failsafe new file mode 100644 index 0000000..0544339 --- /dev/null +++ b/target/linux/adm8668/base-files/sbin/hotplug.failsafe @@ -0,0 +1,4 @@ +#!/bin/sh +case "$1" in + button) kill -USR1 1;; +esac diff --git a/target/linux/adm8668/config-3.18 b/target/linux/adm8668/config-3.18 new file mode 100644 index 0000000..0c24c17 --- /dev/null +++ b/target/linux/adm8668/config-3.18 @@ -0,0 +1,104 @@ +CONFIG_ADM8668=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_AMBA=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_CEVT_R4K=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CMDLINE="console=ttyS0 earlyprintk" +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE_OVERRIDE=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +CONFIG_CSRC_R4K_LIB=y +# CONFIG_DE2104X is not set +# CONFIG_DE4X5 is not set +CONFIG_DECOMPRESS_LZMA=y +# CONFIG_DM9102 is not set +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_WORK=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_CPU=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_MIPS=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_MT_DISABLED=y +CONFIG_MTD_ADM8668_NOR=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_TULIP=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +CONFIG_SERIAL_AMBA_PL010_NUMPORTS=2 +CONFIG_SERIAL_AMBA_PL010_PORTNAME="ttyS" +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SWAP_IO_SPACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_TULIP=y +CONFIG_TULIP_NAPI=y +# CONFIG_TULIP_NAPI_HW_MITIGATION is not set +# CONFIG_TULIP_PCI is not set +CONFIG_TULIP_PLATFORM=y +# CONFIG_ULI526X is not set +CONFIG_USB_ARCH_HAS_XHCI=y +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_SSB is not set +CONFIG_USB_SUPPORT=y +# CONFIG_WINBOND_840 is not set +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/Kconfig b/target/linux/adm8668/files-3.18/arch/mips/adm8668/Kconfig new file mode 100644 index 0000000..2e7281f --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/Kconfig @@ -0,0 +1,2 @@ +config ARM_AMBA + def_bool y diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/Makefile b/target/linux/adm8668/files-3.18/arch/mips/adm8668/Makefile new file mode 100644 index 0000000..515c3a4 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/Makefile @@ -0,0 +1,6 @@ +# +# something witty --neutronscott +# + +obj-y := irq.o prom.o platform.o gpio.o \ + setup.o clock.o time.o early_printk.o \ diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/Platform b/target/linux/adm8668/files-3.18/arch/mips/adm8668/Platform new file mode 100644 index 0000000..c70cd27 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/Platform @@ -0,0 +1,6 @@ +# +# Infineon ADM8668 WildPass +# +platform-$(CONFIG_ADM8668) += adm8668/ +cflags-$(CONFIG_ADM8668) += -I$(srctree)/arch/mips/include/asm/mach-adm8668 +load-$(CONFIG_ADM8668) += 0xffffffff80002000 diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/clock.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/clock.c new file mode 100644 index 0000000..1e010fc --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/clock.c @@ -0,0 +1,76 @@ +/* + * ADM8668 minimal clock support + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under the terms of the GPLv2 + */ + +#include +#include +#include +#include +#include + +#include + +struct clk { + unsigned long rate; +}; + +static struct clk uart_clk = { + .rate = 62500000, +}; + +static struct clk sys_clk; + +struct clk *clk_get(struct device *dev, const char *id) +{ + const char *lookup = id; + + if (dev) + lookup = dev_name(dev); + + if (!strcmp(lookup, "apb:uart0")) + return &uart_clk; + if (!strcmp(lookup, "sys")) + return &sys_clk; + + return ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(clk_get); + +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + +void __init adm8668_init_clocks(void) +{ + u32 adj; + + /* adjustable clock selection + * CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc... + */ + adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf; + sys_clk.rate = 175000000 + (adj * 5000000); + + pr_info("ADM8668 CPU clock: %lu MHz\n", sys_clk.rate / 1000000); +} diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/early_printk.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/early_printk.c new file mode 100644 index 0000000..03dd72a --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/early_printk.c @@ -0,0 +1,16 @@ +#include +#include +#include + +#define UART_READ(r) \ + __raw_readl((void __iomem *)(KSEG1ADDR(ADM8668_UART0_BASE) + (r))) + +#define UART_WRITE(v, r) \ + __raw_writel((v), (void __iomem *)(KSEG1ADDR(ADM8668_UART0_BASE) + (r))) + +void prom_putchar(char c) +{ + UART_WRITE(c, UART01x_DR); + while ((UART_READ(UART01x_FR) & UART01x_FR_TXFF) != 0) + ; +} diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/gpio.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/gpio.c new file mode 100644 index 0000000..fb39f7f --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/gpio.c @@ -0,0 +1,123 @@ +/* + * Infineon/ADMTek ADM8668 WildPass GPIO support + * + * Copyright (C) 2012 Florian Fainelli + * + * Licensed under the terms of GPLv2. + * + */ +#include +#include +#include + +#include + +#define GPIO_MASK 0x3f + +#define GPIO_IN_OFS 0 +#define GPIO_OUT_OFS 6 +#define GPIO_OE_OFS 12 + +struct adm8668_gpio_chip { + void __iomem *base; + struct gpio_chip chip; +}; + +static int adm8668_gpio_dir_out(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct adm8668_gpio_chip *c = + container_of(chip, struct adm8668_gpio_chip, chip); + u32 mask; + + /* clear input, set output enable and output value */ + mask = __raw_readl(c->base); + mask &= ~(1 << offset); + mask |= (1 << (offset + GPIO_OE_OFS)); + if (value) + mask |= (1 << (offset + GPIO_OUT_OFS)); + else + mask &= ~(1 << (offset + GPIO_OUT_OFS)); + __raw_writel(mask, c->base); + + return 0; +} + +static int adm8668_gpio_dir_in(struct gpio_chip *chip, + unsigned offset) +{ + struct adm8668_gpio_chip *c = + container_of(chip, struct adm8668_gpio_chip, chip); + u32 mask; + + mask = __raw_readl(c->base); + mask &= ~(((1 << (offset + GPIO_OE_OFS)) | (1 << (offset + GPIO_OUT_OFS)))); + mask |= (1 << offset); + __raw_writel(mask, c->base); + + return 0; +} + +static void adm8668_gpio_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct adm8668_gpio_chip *c = + container_of(chip, struct adm8668_gpio_chip, chip); + u32 mask; + + mask = __raw_readl(c->base); + if (value) + mask |= (1 << (offset + GPIO_OUT_OFS)); + else + mask &= ~(1 << (offset + GPIO_OUT_OFS)); + __raw_writel(mask, c->base); +} + +static int adm8668_gpio_get(struct gpio_chip *chip, + unsigned offset) +{ + struct adm8668_gpio_chip *c = + container_of(chip, struct adm8668_gpio_chip, chip); + u32 value; + + value = __raw_readl(c->base) & GPIO_MASK; + + return value & (1 << offset); +} + +static struct adm8668_gpio_chip adm8668_gpio_cpu = { + .base = (void __iomem *)KSEG1ADDR(ADM8668_CONFIG_BASE + CRGPIO_REG), + .chip = { + .label = "adm8668-cpu-gpio", + .direction_output = adm8668_gpio_dir_out, + .direction_input = adm8668_gpio_dir_in, + .set = adm8668_gpio_set, + .get = adm8668_gpio_get, + .ngpio = 6, + }, +}; + +static struct adm8668_gpio_chip adm8668_gpio_wlan = { + .base = (void __iomem *)KSEG1ADDR(ADM8668_WLAN_BASE + GPIO_REG), + .chip = { + .label = "adm8668-wlan-gpio", + .direction_output = adm8668_gpio_dir_out, + .direction_input = adm8668_gpio_dir_in, + .set = adm8668_gpio_set, + .get = adm8668_gpio_get, + .ngpio = 6, + .base = 6, + }, +}; + +static int __init adm8668_gpio_init(void) +{ + int ret; + + ret = gpiochip_add(&adm8668_gpio_cpu.chip); + if (ret) + return ret; + + return gpiochip_add(&adm8668_gpio_wlan.chip); +} +arch_initcall(adm8668_gpio_init); diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/irq.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/irq.c new file mode 100644 index 0000000..9d3b2b9 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/irq.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2010 Scott Nicholas + * Copyright (C) 2012 Florian Fainelli + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* interrupt controller */ +#define IRQ_STATUS_REG 0x00 /* Read */ +#define IRQ_ENABLE_REG 0x08 /* Read/Write */ +#define IRQ_DISABLE_REG 0x0C /* Write */ + +#define IRQ_MASK 0xffff + +static inline void intc_write_reg(u32 val, unsigned int reg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(ADM8668_INTC_BASE); + + __raw_writel(val, base + reg); +} + +static inline u32 intc_read_reg(unsigned int reg) +{ + void __iomem *base = (void __iomem *)KSEG1ADDR(ADM8668_INTC_BASE); + + return __raw_readl(base + reg); +} + +static void adm8668_irq_cascade(void) +{ + int irq; + u32 intsrc; + + intsrc = intc_read_reg(IRQ_STATUS_REG) & IRQ_MASK; + if (intsrc) { + irq = fls(intsrc) - 1; + do_IRQ(irq); + } else + spurious_interrupt(); +} + +/* + * System irq dispatch + */ +void plat_irq_dispatch(void) +{ + unsigned int pending; + + pending = read_c0_cause() & read_c0_status() & ST0_IM; + + /* timer interrupt, that we renumbered */ + if (pending & STATUSF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & STATUSF_IP2) + adm8668_irq_cascade(); + else + spurious_interrupt(); +} + +/* + * enable 8668 irq + */ +static void enable_adm8668_irq(struct irq_data *d) +{ + intc_write_reg((1 << d->irq), IRQ_ENABLE_REG); +} + + +static void ack_adm8668_irq(struct irq_data *d) +{ + intc_write_reg((1 << d->irq), IRQ_DISABLE_REG); +} + +/* + * system irq type + */ + +static struct irq_chip adm8668_irq_type = { + .name = "adm8668", + .irq_ack = ack_adm8668_irq, + .irq_mask = ack_adm8668_irq, + .irq_unmask = enable_adm8668_irq +}; + +/* + * irq init + */ +static void __init init_adm8668_irqs(void) +{ + int i; + + /* disable all interrupts for the moment */ + intc_write_reg(IRQ_MASK, IRQ_DISABLE_REG); + + for (i = 0; i <= ADM8668_IRQ_MAX; i++) + irq_set_chip_and_handler(i, &adm8668_irq_type, + handle_level_irq); + + /* hw0 is where our interrupts are uh.. interrupted at. */ + set_c0_status(IE_IRQ0); +} + +/* + * system init + */ +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + init_adm8668_irqs(); +} diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/platform.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/platform.c new file mode 100644 index 0000000..9e40691 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/platform.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2010 Scott Nicholas + * Copyright (C) 2012 Florian Fainelli + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define ADM8868_UBOOT_ENV 0x20000 +#define ADM8868_UBOOT_WAN_MAC 0x5ac +#define ADM8868_UBOOT_LAN_MAC 0x404 + +static void adm8668_uart_set_mctrl(struct amba_device *dev, + void __iomem *base, + unsigned int mcrtl) +{ +} + +static struct amba_pl010_data adm8668_uart0_data = { + .set_mctrl = adm8668_uart_set_mctrl, +}; + +static struct amba_device adm8668_uart0_device = { + .dev = { + .init_name = "apb:uart0", + .platform_data = &adm8668_uart0_data, + }, + .res = { + .start = ADM8668_UART0_BASE, + .end = ADM8668_UART0_BASE + 0xF, + .flags = IORESOURCE_MEM, + }, + .irq = { + ADM8668_UART0_IRQ, + -1 + }, + .periphid = 0x0041010, +}; + +static struct resource eth0_resources[] = { + { + .start = ADM8668_LAN_BASE, + .end = ADM8668_LAN_BASE + 256, + .flags = IORESOURCE_MEM, + }, + { + .start = ADM8668_LAN_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct tulip_platform_data eth0_pdata = { + .chip_id = ADM8668, +}; + +static struct platform_device adm8668_eth0_device = { + .name = "tulip", + .id = 0, + .resource = eth0_resources, + .num_resources = ARRAY_SIZE(eth0_resources), + .dev.platform_data = ð0_pdata, +}; + +static struct resource eth1_resources[] = { + { + .start = ADM8668_WAN_BASE, + .end = ADM8668_WAN_BASE + 256, + .flags = IORESOURCE_MEM, + }, + { + .start = ADM8668_WAN_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct tulip_platform_data eth1_pdata = { + .chip_id = ADM8668, +}; + +static struct platform_device adm8668_eth1_device = { + .name = "tulip", + .id = 1, + .resource = eth1_resources, + .num_resources = ARRAY_SIZE(eth1_resources), + .dev.platform_data = ð1_pdata, +}; + +static struct resource usb_resources[] = { + { + .start = ADM8668_USB_BASE, + .end = ADM8668_USB_BASE + 0x1FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .start = ADM8668_USB_IRQ, + .end = ADM8668_USB_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct usb_ehci_pdata usb_pdata = { + .caps_offset = 0x100, + .has_tt = 1, +}; + +static struct platform_device adm8668_usb_device = { + .name = "ehci-platform", + .id = -1, + .resource = usb_resources, + .num_resources = ARRAY_SIZE(usb_resources), + .dev.platform_data = &usb_pdata, +}; + +static struct platform_device *adm8668_devs[] = { + &adm8668_eth0_device, + &adm8668_eth1_device, + &adm8668_usb_device, +}; + +static void adm8668_fetch_mac(int unit) +{ + u8 *mac; + u32 offset; + struct tulip_platform_data *pdata; + + switch (unit) { + case -1: + case 0: + offset = ADM8868_UBOOT_LAN_MAC; + pdata = ð0_pdata; + break; + case 1: + offset = ADM8868_UBOOT_WAN_MAC; + pdata = ð1_pdata; + break; + default: + pr_err("unsupported ethernet unit: %d\n", unit); + return; + } + + mac = (u8 *)(KSEG1ADDR(ADM8668_SMEM1_BASE) + ADM8868_UBOOT_ENV + offset); + + memcpy(pdata->mac, mac, sizeof(pdata->mac)); +} + +static void adm8668_ehci_workaround(void) +{ + u32 chipid; + + chipid = ADM8668_CONFIG_REG(ADM8668_CR0); + ADM8668_CONFIG_REG(ADM8668_CR66) = 0x0C1600D9; + + if (chipid == 0x86880001) + return; + + ADM8668_CONFIG_REG(ADM8668_CR66) &= ~(3 << 20); + ADM8668_CONFIG_REG(ADM8668_CR66) |= (1 << 20); + pr_info("ADM8668: applied USB workaround\n"); +} + + +int __init adm8668_devs_register(void) +{ + int ret; + + ret = amba_device_register(&adm8668_uart0_device, &iomem_resource); + if (ret) + panic("failed to register AMBA UART"); + + adm8668_fetch_mac(0); + adm8668_fetch_mac(1); + adm8668_ehci_workaround(); + + return platform_add_devices(adm8668_devs, ARRAY_SIZE(adm8668_devs)); +} +arch_initcall(adm8668_devs_register); diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/prom.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/prom.c new file mode 100644 index 0000000..24b77f8 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/prom.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2010 Scott Nicholas + * + * based on work of rb532 prom.c + * Copyright (C) 2003, Peter Sadik + * Copyright (C) 2005-2006, P.Christeas + * Copyright (C) 2007, Gabor Juhos + * Felix Fietkau + * Florian Fainelli + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "u-boot.h" + +register volatile struct global_data *gd asm ("k0"); + +void __init prom_free_prom_memory(void) +{ + /* No prom memory to free */ +} + +static inline int match_tag(char *arg, const char *tag) +{ + return strncmp(arg, tag, strlen(tag)) == 0; +} + +static inline unsigned long tag2ul(char *arg, const char *tag) +{ + char *num; + + num = arg + strlen(tag); + return simple_strtoul(num, 0, 10); +} + +void __init prom_setup_cmdline(void) +{ + char *cp; + int prom_argc; + char **prom_argv; + int i; + + prom_argc = fw_arg0; + prom_argv = (char **)KSEG0ADDR(fw_arg1); + + cp = &(arcs_cmdline[0]); + for (i = 1; i < prom_argc; i++) { + prom_argv[i] = (char *)KSEG0ADDR(prom_argv[i]); + + /* default bootargs has "console=/dev/ttyS0" yet console won't + * show up at all if you include the '/dev/' nowadays ... */ + if (match_tag(prom_argv[i], "console=/dev/")) { + char *ptr = prom_argv[i] + strlen("console=/dev/"); + + strcpy(cp, "console="); + cp += strlen("console="); + strcpy(cp, ptr); + cp += strlen(ptr); + *cp++ = ' '; + continue; + } + strcpy(cp, prom_argv[i]); + cp += strlen(prom_argv[i]); + *cp++ = ' '; + } + if (prom_argc > 1) + --cp; /* trailing space */ + + *cp = '\0'; +} + +void __init prom_init(void) +{ + bd_t *bd = gd->bd; + int memsize; + + memsize = bd->bi_memsize; + printk("Board info:\n"); + printk(" RAM size: %d MB\n", (int)memsize/(1024*1024)); + printk(" NOR start: %#lx\n", bd->bi_flashstart); + printk(" NOR size: %#lx\n", bd->bi_flashsize); + + prom_setup_cmdline(); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/setup.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/setup.c new file mode 100644 index 0000000..b33c483 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/setup.c @@ -0,0 +1,36 @@ +#include +#include + +#include +#include + +static void adm8668_restart(char *cmd) +{ + int i; + + /* the real deal */ + for (i = 0; i < 1000; i++) + ; + ADM8668_CONFIG_REG(ADM8668_CR1) = 1; +} + +void __init plat_mem_setup(void) +{ + _machine_restart = adm8668_restart; +} + +const char *get_system_type(void) +{ + unsigned long chipid = ADM8668_CONFIG_REG(ADM8668_CR0); + int product, revision; + static char ret[32]; + + product = chipid >> 16; + revision = chipid & 0xffff; + + /* i getting fancy :\ */ + snprintf(ret, sizeof(ret), "ADM%xr%x", product, revision); + + return ret; +} + diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/time.c b/target/linux/adm8668/files-3.18/arch/mips/adm8668/time.c new file mode 100644 index 0000000..87bdd66 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/time.c @@ -0,0 +1,20 @@ +#include +#include +#include + +#include +#include + +void __init plat_time_init(void) +{ + struct clk *sys_clk; + + adm8668_init_clocks(); + + sys_clk = clk_get(NULL, "sys"); + if (IS_ERR(sys_clk)) + panic("unable to get system clock\n"); + + mips_hpt_frequency = clk_get_rate(sys_clk) / 2; +} + diff --git a/target/linux/adm8668/files-3.18/arch/mips/adm8668/u-boot.h b/target/linux/adm8668/files-3.18/arch/mips/adm8668/u-boot.h new file mode 100644 index 0000000..d9d2268 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/adm8668/u-boot.h @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ +} bd_t; + +struct global_data { + bd_t *bd; /* board data... */ + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + void **jt; /* jump table */ +}; + +#endif /* _U_BOOT_H_ */ diff --git a/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/adm8668.h b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/adm8668.h new file mode 100644 index 0000000..8a16863 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/adm8668.h @@ -0,0 +1,69 @@ +/************************************************************************ + * + * Copyright (c) 2005 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + ************************************************************************/ + +#ifndef __ADM8668_H__ +#define __ADM8668_H__ + +/*======================= Physical Memory Map ============================*/ +#define ADM8668_SDRAM_BASE 0 +#define ADM8668_SMEM1_BASE 0x10000000 +#define ADM8668_MPMC_BASE 0x11000000 +#define ADM8668_USB_BASE 0x11200000 +#define ADM8668_CONFIG_BASE 0x11400000 +#define ADM8668_WAN_BASE 0x11600000 +#define ADM8668_WLAN_BASE 0x11800000 +#define ADM8668_LAN_BASE 0x11A00000 +#define ADM8668_INTC_BASE 0x1E000000 +#define ADM8668_TMR_BASE 0x1E200000 +#define ADM8668_UART0_BASE 0x1E400000 +#define ADM8668_SMEM0_BASE 0x1FC00000 +#define ADM8668_NAND_BASE 0x1FFFFF00 + +#define ADM8668_PCICFG_BASE 0x12200000 +#define ADM8668_PCIDAT_BASE 0x12400000 + +/* interrupt levels */ +#define ADM8668_SWI_IRQ 1 +#define ADM8668_COMMS_RX_IRQ 2 +#define ADM8668_COMMS_TX_IRQ 3 +#define ADM8668_TIMER0_IRQ 4 +#define ADM8668_TIMER1_IRQ 5 +#define ADM8668_UART0_IRQ 6 +#define ADM8668_LAN_IRQ 7 +#define ADM8668_WAN_IRQ 8 +#define ADM8668_WLAN_IRQ 9 +#define ADM8668_GPIO_IRQ 10 +#define ADM8668_IDE_IRQ 11 +#define ADM8668_PCI2_IRQ 12 +#define ADM8668_PCI1_IRQ 13 +#define ADM8668_PCI0_IRQ 14 +#define ADM8668_USB_IRQ 15 +#define ADM8668_IRQ_MAX ADM8668_USB_IRQ + +/* register access macros */ +#define ADM8668_CONFIG_REG(_reg) \ + (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_CONFIG_BASE + (_reg))))) + +/* lan registers */ +#define NETCSR6 0x30 +#define NETCSR7 0x38 +#define NETCSR37 0xF8 + +/* known/used CPU configuration registers */ +#define ADM8668_CR0 0x00 +#define ADM8668_CR1 0x04 +#define ADM8668_CR3 0x0C +#define ADM8668_CR66 0x108 + +/** For GPIO control **/ +#define GPIO_REG 0x5C /* on WLAN */ +#define CRGPIO_REG 0x20 /* on CPU */ + +void adm8668_init_clocks(void); + +#endif /* __ADM8668_H__ */ diff --git a/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/asm/sizes.h b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/asm/sizes.h new file mode 100644 index 0000000..503843d --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/asm/sizes.h @@ -0,0 +1,56 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* DO NOT EDIT!! - this file automatically generated + * from .s file by awk -f s2h.awk + */ +/* Size definitions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_16 0x00000010 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif + +/* END */ diff --git a/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/gpio.h b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/gpio.h new file mode 100644 index 0000000..b0473fc --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/gpio.h @@ -0,0 +1,13 @@ +#ifndef __ADM8668_GPIO_H__ +#define __ADM8668_GPIO_H__ + +#define gpio_to_irq(gpio) -1 + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value + +#define gpio_cansleep __gpio_cansleep + +#include + +#endif diff --git a/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/irq.h b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/irq.h new file mode 100644 index 0000000..ea859f0 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/irq.h @@ -0,0 +1,14 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_ADM8668_IRQ_H +#define __ASM_MACH_ADM8668_IRQ_H + +#define NR_IRQS 32 +#define MIPS_CPU_IRQ_BASE 16 + +#endif /* __ASM_MACH_ADM8668_IRQ_H */ diff --git a/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/war.h b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/war.h new file mode 100644 index 0000000..7180043 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/include/asm/mach-adm8668/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_ADM8668_WAR_H +#define __ASM_MIPS_MACH_ADM8668_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_ADM8668_WAR_H */ diff --git a/target/linux/adm8668/files-3.18/arch/mips/pci/pci-adm8668.c b/target/linux/adm8668/files-3.18/arch/mips/pci/pci-adm8668.c new file mode 100644 index 0000000..5cfa546 --- /dev/null +++ b/target/linux/adm8668/files-3.18/arch/mips/pci/pci-adm8668.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2010 Scott Nicholas + * Copyright (C) 2012 Florian Fainelli + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Note that this controller is identical to the ADM5120 one + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +static DEFINE_SPINLOCK(pci_lock); + +#define PCI_ENABLE 0x80000000 +#define ADMPCI_IO_BASE 0x12600000 +#define ADMPCI_IO_SIZE 0x1fffff +#define ADMPCI_MEM_BASE 0x16000000 +#define ADMPCI_MEM_SIZE 0x7ffffff + +static inline void write_cfgaddr(u32 addr) +{ + __raw_writel((addr | PCI_ENABLE), + (void __iomem *)KSEG1ADDR(ADM8668_PCICFG_BASE)); +} + +static inline void write_cfgdata(u32 data) +{ + __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM8668_PCIDAT_BASE)); +} + +static inline u32 read_cfgdata(void) +{ + return __raw_readl((void __iomem *)KSEG1ADDR(ADM8668_PCIDAT_BASE)); +} + +static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where) +{ + return ((bus->number & 0xff) << 16) | ((devfn & 0xff) << 8) | + (where & 0xfc); +} + +static int pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + unsigned long flags; + u32 data; + + spin_lock_irqsave(&pci_lock, flags); + write_cfgaddr(mkaddr(bus, devfn, where)); + data = read_cfgdata(); + + switch (size) { + case 1: + if (where & 1) + data >>= 8; + if (where & 2) + data >>= 16; + data &= 0xff; + break; + case 2: + if (where & 2) + data >>= 16; + data &= 0xffff; + break; + } + + *val = data; + + spin_unlock_irqrestore(&pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +static int pci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + unsigned long flags; + u32 data; + int s; + + spin_lock_irqsave(&pci_lock, flags); + + write_cfgaddr(mkaddr(bus, devfn, where)); + data = read_cfgdata(); + + switch (size) { + case 1: + s = ((where & 3) << 3); + data &= ~(0xff << s); + data |= ((val & 0xff) << s); + break; + case 2: + s = ((where & 2) << 4); + data &= ~(0xffff << s); + data |= ((val & 0xffff) << s); + break; + case 4: + data = val; + break; + } + + write_cfgdata(data); + + spin_unlock_irqrestore(&pci_lock, flags); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops adm8668_pci_ops = { + .read = pci_read_config, + .write = pci_write_config +}; + + +struct resource pciioport_resource = { + .name = "adm8668_pci", + .start = ADMPCI_IO_BASE, + .end = ADMPCI_IO_BASE + ADMPCI_IO_SIZE, + .flags = IORESOURCE_IO +}; + +struct resource pciiomem_resource = { + .name = "adm8668_pci", + .start = ADMPCI_MEM_BASE, + .end = ADMPCI_MEM_BASE + ADMPCI_MEM_SIZE, + .flags = IORESOURCE_MEM +}; + +struct pci_controller adm8668_pci_controller = { + .pci_ops = &adm8668_pci_ops, + .io_resource = &pciioport_resource, + .mem_resource = &pciiomem_resource, +}; + +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + switch (slot) { + case 1: + return 14; + case 2: + return 13; + case 3: + return 12; + default: + return dev->irq; + } +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static void adm8668_pci_fixup(struct pci_dev *dev) +{ + if (dev->devfn != 0) + return; + + pr_info("PCI: fixing up ADM8668 controller\n"); + + /* setup COMMAND register */ + pci_write_config_word(dev, PCI_COMMAND, + (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); + + /* setup CACHE_LINE_SIZE register */ + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4); + + /* setup BARS */ + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); +} +DECLARE_PCI_FIXUP_HEADER(0x1317, 0x8688, adm8668_pci_fixup); + +static int __init adm8668_pci_init(void) +{ + void __iomem *io_map_base; + + ioport_resource.start = ADMPCI_IO_BASE; + ioport_resource.end = ADMPCI_IO_BASE + ADMPCI_IO_SIZE; + + io_map_base = ioremap(ADMPCI_IO_BASE, ADMPCI_IO_SIZE); + if (!io_map_base) + printk("io_map_base didn't work.\n"); + + adm8668_pci_controller.io_map_base = (unsigned long)io_map_base; + register_pci_controller(&adm8668_pci_controller); + + return 0; +} +arch_initcall(adm8668_pci_init); diff --git a/target/linux/adm8668/files-3.18/drivers/mtd/maps/adm8668.c b/target/linux/adm8668/files-3.18/drivers/mtd/maps/adm8668.c new file mode 100644 index 0000000..8737159 --- /dev/null +++ b/target/linux/adm8668/files-3.18/drivers/mtd/maps/adm8668.c @@ -0,0 +1,334 @@ +/* + * Copyright (C) 2010 Scott Nicholas + * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2005 Waldemar Brodkorb + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org) + * + * original functions for finding root filesystem from Mike Baker + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Copyright 2004, Broadcom Corporation + * All Rights Reserved. + * + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. + * + * Flash mapping for adm8668 boards + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WINDOW_ADDR 0x10000000 +#define WINDOW_SIZE 0x800000 +#define BANKWIDTH 2 + +/* first a little bit about the headers i need.. */ + +/* just interested in part of the full struct */ +struct squashfs_super_block { + __le32 s_magic; + __le32 pad0[9]; /* it's not really padding */ + __le64 bytes_used; +}; + +#define IH_MAGIC 0x56190527 /* Image Magic Number */ +struct uboot_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + char ih_name[32]; /* image name */ +}; + +/************************************************/ + +static struct mtd_info *adm8668_mtd; + +struct map_info adm8668_map = { + name: "adm8668-nor", + size: WINDOW_SIZE, + phys: WINDOW_ADDR, + bankwidth: BANKWIDTH, +}; + +/* + * Copied from mtdblock.c + * + * Cache stuff... + * + * Since typical flash erasable sectors are much larger than what Linux's + * buffer cache can handle, we must implement read-modify-write on flash + * sectors for each block write requests. To avoid over-erasing flash sectors + * and to speed things up, we locally cache a whole flash sector while it is + * being written to until a different sector is required. + */ + +static void erase_callback(struct erase_info *done) +{ + wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv; + wake_up(wait_q); +} + +static int erase_write (struct mtd_info *mtd, unsigned long pos, + int len, const char *buf) +{ + struct erase_info erase; + DECLARE_WAITQUEUE(wait, current); + wait_queue_head_t wait_q; + size_t retlen; + int ret; + + /* + * First, let's erase the flash block. + */ + + init_waitqueue_head(&wait_q); + erase.mtd = mtd; + erase.callback = erase_callback; + erase.addr = pos; + erase.len = len; + erase.priv = (u_long)&wait_q; + + set_current_state(TASK_INTERRUPTIBLE); + add_wait_queue(&wait_q, &wait); + + ret = mtd->_erase(mtd, &erase); + if (ret) { + set_current_state(TASK_RUNNING); + remove_wait_queue(&wait_q, &wait); + printk (KERN_WARNING "erase of region [0x%lx, 0x%x] " + "on \"%s\" failed\n", + pos, len, mtd->name); + return ret; + } + + schedule(); /* Wait for erase to finish. */ + remove_wait_queue(&wait_q, &wait); + + /* + * Next, write data to flash. + */ + + ret = mtd->_write (mtd, pos, len, &retlen, buf); + if (ret) + return ret; + if (retlen != len) + return -EIO; + return 0; +} + +/* decent defaults in case... shrug */ +static struct mtd_partition adm8668_parts[] = { + { name: "linux", offset: 0x40000, size: WINDOW_SIZE-0x40000, }, + { name: "rootfs", offset: 0xe0000, size: 0x140000, }, + { name: "uboot_env", offset: 0x20000, size: 0x20000, }, + { name: NULL, }, +}; + +/* in case i wanna change stuff later, and to clarify the math section... */ +#define PART_LINUX 0 +#define PART_ROOTFS 1 +#define NR_PARTS 3 + +static int __init +init_mtd_partitions(struct mtd_info *mtd, size_t size) +{ + struct uboot_header uhdr; + int off, blocksize; + size_t len, linux_len; + struct squashfs_super_block shdr; + + blocksize = mtd->erasesize; + if (blocksize < 0x10000) + blocksize = 0x10000; + + /* now find squashfs */ + memset(&shdr, 0xe5, sizeof(shdr)); + for (off = adm8668_parts[PART_LINUX].offset; off < size; off += blocksize) { + /* + * Read into buffer + */ + if (mtd->_read(mtd, off, sizeof(shdr), &len, (char *)&shdr) || + len != sizeof(shdr)) + continue; + + if (shdr.s_magic == SQUASHFS_MAGIC) { + uint32_t fs_size = (uint32_t)shdr.bytes_used; + + printk(KERN_INFO "%s: Filesystem type: squashfs, size=%dkB\n", + mtd->name, fs_size>>10); + + /* Update rootfs based on the superblock info, and + * stretch to end of MTD. rootfs_split will split it */ + adm8668_parts[PART_ROOTFS].offset = off; + adm8668_parts[PART_ROOTFS].size = mtd->size - + adm8668_parts[PART_ROOTFS].offset; + + /* kernel ends where rootfs starts + * but we'll keep it full-length for upgrades */ + linux_len = adm8668_parts[PART_LINUX+1].offset - + adm8668_parts[PART_LINUX].offset; +#if 1 + adm8668_parts[PART_LINUX].size = mtd->size - + adm8668_parts[PART_LINUX].offset; +#else + adm8668_parts[PART_LINUX].size = linux_len; +#endif + goto found; + } + } + + printk(KERN_NOTICE + "%s: Couldn't find root filesystem\n", + mtd->name); + return NR_PARTS; + + found: + if (mtd->_read(mtd, adm8668_parts[PART_LINUX].offset, sizeof(uhdr), &len, (char *)&uhdr) || + len != sizeof(uhdr)) + return NR_PARTS; + + /* that's odd. how'd ya boot it then */ + if (uhdr.ih_magic != IH_MAGIC) + return NR_PARTS; + + if (be32_to_cpu(uhdr.ih_size) != (linux_len - sizeof(uhdr))) { + unsigned char *block, *data; + unsigned int offset; + + offset = adm8668_parts[PART_LINUX].offset + + sizeof(struct uboot_header); + data = (unsigned char *)(WINDOW_ADDR | 0xA0000000 | offset); + + printk(KERN_NOTICE "Updating U-boot image:\n"); + printk(KERN_NOTICE " old: [size: %8d crc32: 0x%08x]\n", + be32_to_cpu(uhdr.ih_size), be32_to_cpu(uhdr.ih_dcrc)); + + /* Update the data length & crc32 */ + uhdr.ih_size = cpu_to_be32(linux_len - sizeof(uhdr)); + uhdr.ih_dcrc = crc32_le(~0, data, linux_len - sizeof(uhdr)) ^ (~0); + uhdr.ih_dcrc = cpu_to_be32(uhdr.ih_dcrc); + + printk(KERN_NOTICE " new: [size: %8d crc32: 0x%08x]\n", + be32_to_cpu(uhdr.ih_size), be32_to_cpu(uhdr.ih_dcrc)); + + /* update header's crc... */ + uhdr.ih_hcrc = 0; + uhdr.ih_hcrc = crc32_le(~0, (unsigned char *)&uhdr, + sizeof(uhdr)) ^ (~0); + uhdr.ih_hcrc = cpu_to_be32(uhdr.ih_hcrc); + + /* read first eraseblock from the image */ + block = kmalloc(mtd->erasesize, GFP_KERNEL); + if (mtd->_read(mtd, adm8668_parts[PART_LINUX].offset, mtd->erasesize, &len, block) || len != mtd->erasesize) { + printk("Error copying first eraseblock\n"); + return 0; + } + + /* Write updated header to the flash */ + memcpy(block, &uhdr, sizeof(uhdr)); + if (mtd->_unlock) + mtd->_unlock(mtd, off, mtd->erasesize); + erase_write(mtd, adm8668_parts[PART_LINUX].offset, mtd->erasesize, block); + if (mtd->_sync) + mtd->_sync(mtd); + kfree(block); + printk(KERN_NOTICE "Done\n"); + } + + return NR_PARTS; +} + +int __init init_adm8668_map(void) +{ + int nr_parts, ret; + + adm8668_map.virt = ioremap(WINDOW_ADDR, WINDOW_SIZE); + + if (!adm8668_map.virt) { + printk(KERN_ERR "Failed to ioremap\n"); + return -EIO; + } + + simple_map_init(&adm8668_map); + if (!(adm8668_mtd = do_map_probe("cfi_probe", &adm8668_map))) { + printk(KERN_ERR "cfi_probe failed\n"); + iounmap((void *)adm8668_map.virt); + return -ENXIO; + } + + adm8668_mtd->owner = THIS_MODULE; + + nr_parts = init_mtd_partitions(adm8668_mtd, adm8668_mtd->size); + ret = mtd_device_register(adm8668_mtd, adm8668_parts, nr_parts); + if (ret) { + printk(KERN_ERR "Flash: mtd_device_register failed\n"); + goto fail; + } + + return 0; + + fail: + if (adm8668_mtd) + map_destroy(adm8668_mtd); + if (adm8668_map.virt) + iounmap((void *) adm8668_map.virt); + adm8668_map.virt = 0; + return ret; +} + +void __exit cleanup_adm8668_map(void) +{ + mtd_device_unregister(adm8668_mtd); + map_destroy(adm8668_mtd); + iounmap((void *) adm8668_map.virt); + adm8668_map.virt = 0; +} + +module_init(init_adm8668_map); +module_exit(cleanup_adm8668_map); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Scott Nicholas "); +MODULE_DESCRIPTION("MTD map driver for ADM8668 NOR Flash"); diff --git a/target/linux/adm8668/image/Makefile b/target/linux/adm8668/image/Makefile new file mode 100644 index 0000000..597b8f7 --- /dev/null +++ b/target/linux/adm8668/image/Makefile @@ -0,0 +1,60 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux +UIMAGE:=$(IMG_PREFIX)-uImage + +define kernel_entry +-a 0x80002000 -e 0x80002000 +endef + + +define CompressGzip + gzip -9n -c $(1) > $(2) +endef + +define MkImage + mkimage -A mips -O linux -T kernel $(call kernel_entry) -C $(1) $(2) \ + -n "ADM8668 Linux Kernel(2.4.31)" \ + -d $(3) $(4) +endef + +define Build/Clean + $(MAKE) -C lzma-loader clean +endef + +define Image/Prepare + cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma + $(MAKE) -C lzma-loader \ + KDIR="$(KDIR)" \ + clean compile + rm -f $(KDIR)/fs_mark + touch $(KDIR)/fs_mark + $(call prepare_generic_squashfs,$(KDIR)/fs_mark) +endef + +define Image/Build + ./my-mkimage $(KDIR)/loader.bin $(KDIR)/root.squashfs \ + $(KDIR)/fs_mark $(BIN_DIR)/$(IMG_PREFIX)-$(1).bin +endef + +define Image/BuildKernel + cp $(KDIR)/vmlinux.elf $(VMLINUX).elf + cp $(KDIR)/vmlinux $(VMLINUX).bin + $(call CompressGzip,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.gz) + $(call MkImage,gzip,,$(KDIR)/vmlinux.bin.gz,$(BIN_DIR)/$(UIMAGE)-gzip.bin) +ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y) + cp $(KDIR)/vmlinux-initramfs.elf $(VMLINUX)-initramfs.elf + cp $(KDIR)/vmlinux $(VMLINUX)-initramfs.bin + $(call CompressGzip,$(KDIR)/vmlinux-initramfs,$(KDIR)/vmlinux-initramfs.bin.gz) + $(call MkImage,gzip,,$(KDIR)/vmlinux-initramfs.bin.gz,$(BIN_DIR)/$(UIMAGE)-initramfs-gzip.bin) +endif +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/adm8668/image/lzma-loader/Makefile b/target/linux/adm8668/image/lzma-loader/Makefile new file mode 100644 index 0000000..f6bc7ce --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME := loader +PKG_VERSION := 0.05 + +PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)-$(PKG_VERSION)$(LOADER_TYPE) + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +$(PKG_BUILD_DIR)/lzma.elf: $(PKG_BUILD_DIR)/.prepared $(PKG_BUILD_DIR)/vmlinux.lzma + PATH="$(TARGET_PATH)" $(MAKE) -C $(PKG_BUILD_DIR) \ + CC="$(TARGET_CC)" CROSS_COMPILE="$(TARGET_CROSS)" + +$(PKG_BUILD_DIR)/vmlinux.lzma: $(KDIR)/vmlinux.lzma + $(CP) $< $@ + +$(KDIR)/loader$(LOADER_TYPE).elf: $(PKG_BUILD_DIR)/lzma.elf + $(CP) $< $@ + +$(KDIR)/loader$(LOADER_TYPE).bin: $(PKG_BUILD_DIR)/lzma.bin + $(CP) $< $@ + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: $(KDIR)/loader$(LOADER_TYPE).elf $(KDIR)/loader$(LOADER_TYPE).bin +install: + +clean: + rm -rf $(PKG_BUILD_DIR) + rm -f $(KDIR)/loader.elf + rm -f $(KDIR)/loader.bin diff --git a/target/linux/adm8668/image/lzma-loader/src/LzmaDecode.c b/target/linux/adm8668/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 0000000..8c863ef --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,590 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.22 Copyright (c) 1999-2005 Igor Pavlov (2005-06-10) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#ifndef Byte +#define Byte unsigned char +#endif + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \ + BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +#if 0 +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} +#endif + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + return LZMA_RESULT_DATA_ERROR; + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/adm8668/image/lzma-loader/src/LzmaDecode.h b/target/linux/adm8668/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 0000000..abc02d7 --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,131 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.21 Copyright (c) 1999-2005 Igor Pavlov (2005-06-08) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +/* #define _LZMA_SYSTEM_SIZE_T */ +/* Use system's size_t. You can use it to enable 64-bit sizes supporting*/ + +#ifndef UInt32 +#ifdef _LZMA_UINT32_IS_ULONG +#define UInt32 unsigned long +#else +#define UInt32 unsigned int +#endif +#endif + +#ifndef SizeT +#ifdef _LZMA_SYSTEM_SIZE_T +#include +#define SizeT size_t +#else +#define SizeT UInt32 +#endif +#endif + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb unsigned short +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/target/linux/adm8668/image/lzma-loader/src/Makefile b/target/linux/adm8668/image/lzma-loader/src/Makefile new file mode 100644 index 0000000..998e390 --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/Makefile @@ -0,0 +1,47 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +RAMSTART = 0x80000000 +RAMSIZE = 0x00800000 # 8MB +LOADADDR = 0x80400000 # RAM start + 4M +KERNEL_ENTRY = 0x80002000 + +CROSS_COMPILE = mipsel-openwrt-linux- + +OBJCOPY:= $(CROSS_COMPILE)objcopy -O binary -R .reginfo -R .note -R .comment -R .mdebug -S +CFLAGS := -I./include -fno-builtin -Os -G 0 -ffunction-sections -mno-abicalls -fno-pic -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap -Wall -DRAMSTART=${RAMSTART} -DRAMSIZE=${RAMSIZE} -DKERNEL_ENTRY=${KERNEL_ENTRY} + +.c.o: + $(CC) $(CFLAGS) -c $< -o $*.o + +CC = $(CROSS_COMPILE)gcc +LD = $(CROSS_COMPILE)ld +OBJDUMP = $(CROSS_COMPILE)objdump + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +# Drop some uninteresting sections in the kernel. +# This is only relevant for ELF kernels but doesn't hurt a.out +drop-sections = .reginfo .mdebug .comment +strip-flags = $(addprefix --remove-section=,$(drop-sections)) + +all : lzma.elf lzma.bin + +lzma.lds: lzma.lds.in + sed -e 's,@LOADADDR@,$(LOADADDR),g' $< >$@ + +kernel.o: vmlinux.lzma lzma.lds + $(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $< + +lzma.bin: lzma.elf + $(OBJCOPY) $< $@ + +lzma.elf: decompress.o stubs.o LzmaDecode.o kernel.o lzma.lds + $(LD) -T lzma.lds -o $@ $^ +#-s ^ + +clean: + rm -f *.o lzma.elf lzma.bin *.tmp *.lds diff --git a/target/linux/adm8668/image/lzma-loader/src/decompress.c b/target/linux/adm8668/image/lzma-loader/src/decompress.c new file mode 100644 index 0000000..f328058 --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/decompress.c @@ -0,0 +1,118 @@ +/* + * LZMA compressed kernel decompressor for bcm947xx boards + * + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * Please note, this was code based on the bunzip2 decompressor code + * by Manuel Novoa III (mjn3@codepoet.org), although the only thing left + * is an idea and part of original vendor code + * + * + * 12-Mar-2005 Mineharu Takahara + * pass actual output size to decoder (stream mode + * compressed input is not a requirement anymore) + * + * 24-Apr-2005 Oleg I. Vdovikin + * reordered functions using lds script, removed forward decl + * + * ??-Nov-2005 Mike Baker + * reorder the script as an lzma wrapper; do not depend on flash access + */ + +#include "LzmaDecode.h" +#include + +#define KSEG0ADDR(addr) (0x80000000|addr) + +register volatile gd_t *gd asm ("k0"); +unsigned char *data; + +static __inline__ unsigned char get_byte() +{ + unsigned char *buffer; + + buffer = data; + data++; + + return *buffer; +} + +/* This puts lzma workspace 128k below RAM end. + * That should be enough for both lzma and stack + */ +static char *buffer = (char *)(RAMSTART + RAMSIZE - 0x00020000); +extern char _binary_vmlinux_lzma_start[]; +extern char _binary_vmlinux_lzma_end[]; +extern char lzma_start[]; +extern char lzma_end[]; + +/* should be the first function */ +void entry(unsigned int arg0, unsigned int arg1, + unsigned int arg2, unsigned int arg3) +{ + unsigned int i; /* temp value */ + unsigned int isize; /* compressed size */ + unsigned int osize; /* uncompressed size */ + int argc = arg0; + char **argv = (char **)arg1; + char **envp = (char **)arg2; + + CLzmaDecoderState vs; + + data = (unsigned char *)_binary_vmlinux_lzma_start; + isize = _binary_vmlinux_lzma_end - _binary_vmlinux_lzma_start + 1; + + puts("\nLZMA kernel loader\n"); + + printf("lzma data @ %#x - %#x\n", _binary_vmlinux_lzma_start, _binary_vmlinux_lzma_end); + printf("load addr @ %#x\n\n", KERNEL_ENTRY); + printf("jump table @ %#x\n", gd->jt[3]); + + /* lzma args */ + i = get_byte(); + vs.Properties.lc = i % 9, i = i / 9; + vs.Properties.lp = i % 5, vs.Properties.pb = i / 5; + + vs.Probs = (CProb *)buffer; + + /* skip rest of the LZMA coder property */ + data += 4; + + /* read the lower half of uncompressed size in the header */ + osize = ((unsigned int)get_byte()) + + ((unsigned int)get_byte() << 8) + + ((unsigned int)get_byte() << 16) + + ((unsigned int)get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + data += 4; + + /* decompress kernel */ + puts("\nDecompressing kernel..."); + if ((i = LzmaDecode(&vs, + (unsigned char*)data, isize, &isize, + (unsigned char*)KERNEL_ENTRY, osize, &osize)) == LZMA_RESULT_OK) + { + puts("success!\n"); + + /* Jump to load address */ +// ((void (*)(int a0, int a1, int a2, int a3))KERNEL_ENTRY)(0,0,0,0); + ((void (*)(int a0, int a1, int a2, int a3))KERNEL_ENTRY)(arg0, arg1, arg2, arg3); + } + puts("failure!\n"); +} diff --git a/target/linux/adm8668/image/lzma-loader/src/include/_exports.h b/target/linux/adm8668/image/lzma-loader/src/include/_exports.h new file mode 100644 index 0000000..61dcaaf --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/include/_exports.h @@ -0,0 +1,18 @@ +EXPORT_FUNC(get_version) +EXPORT_FUNC(getc) +EXPORT_FUNC(tstc) +EXPORT_FUNC(putc) +EXPORT_FUNC(puts) +EXPORT_FUNC(printf) +EXPORT_FUNC(install_hdlr) +EXPORT_FUNC(free_hdlr) +EXPORT_FUNC(malloc) +EXPORT_FUNC(free) +EXPORT_FUNC(udelay) +EXPORT_FUNC(get_timer) +EXPORT_FUNC(vprintf) +EXPORT_FUNC(do_reset) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +EXPORT_FUNC(i2c_write) +EXPORT_FUNC(i2c_read) +#endif /* CFG_CMD_I2C */ diff --git a/target/linux/adm8668/image/lzma-loader/src/include/asm/global_data.h b/target/linux/adm8668/image/lzma-loader/src/include/asm/global_data.h new file mode 100644 index 0000000..a024194 --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/include/asm/global_data.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2002-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H + +#include + +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long have_console; /* serial_init() was called */ + unsigned long ram_size; /* RAM size */ + unsigned long reloc_off; /* Relocation Offset */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + void **jt; /* jump table */ +} gd_t; + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ + +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") + +#endif /* __ASM_GBL_DATA_H */ diff --git a/target/linux/adm8668/image/lzma-loader/src/include/asm/u-boot.h b/target/linux/adm8668/image/lzma-loader/src/include/asm/u-boot.h new file mode 100644 index 0000000..0de0b4d --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/include/asm/u-boot.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ 1 + +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ +} bd_t; +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + +#endif /* _U_BOOT_H_ */ diff --git a/target/linux/adm8668/image/lzma-loader/src/include/common.h b/target/linux/adm8668/image/lzma-loader/src/include/common.h new file mode 100644 index 0000000..5d957af --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/include/common.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __COMMON_H_ +#define __COMMON_H_ 1 + +#undef _LINUX_CONFIG_H +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +typedef unsigned char uchar; +typedef volatile unsigned long vu_long; +typedef volatile unsigned short vu_short; +typedef volatile unsigned char vu_char; + +#include +#include +#include +#include +#include +#include + +typedef void (interrupt_handler_t)(void *); + +#include /* boot information for Linux kernel */ +#include /* global data used for startup functions */ + + +#endif /* __COMMON_H_ */ diff --git a/target/linux/adm8668/image/lzma-loader/src/include/exports.h b/target/linux/adm8668/image/lzma-loader/src/include/exports.h new file mode 100644 index 0000000..4cdc36e --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/include/exports.h @@ -0,0 +1,38 @@ +#ifndef __EXPORTS_H__ +#define __EXPORTS_H__ +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) +#ifndef __ASSEMBLY__ + +#include + +/* These are declarations of exported functions available in C code */ +unsigned long get_version(void); +int getc(void); +int tstc(void); +void putc(const char); +void puts(const char*); +void printf(const char* fmt, ...); +void install_hdlr(int, interrupt_handler_t*, void*); +void free_hdlr(int); +void *malloc(size_t); +void free(void*); +void udelay(unsigned long); +unsigned long get_timer(unsigned long); +void vprintf(const char *, va_list); +void do_reset (void); + +void app_startup(char **); + +#endif /* ifndef __ASSEMBLY__ */ + +enum { +#define EXPORT_FUNC(x) XF_ ## x , +#include <_exports.h> +#undef EXPORT_FUNC + + XF_MAX +}; + +#define XF_VERSION 2 + +#endif /* __EXPORTS_H__ */ diff --git a/target/linux/adm8668/image/lzma-loader/src/include/image.h b/target/linux/adm8668/image/lzma-loader/src/include/image.h new file mode 100644 index 0000000..69c73b7 --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/include/image.h @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMAGE_H__ +#define __IMAGE_H__ + +/* + * Operating System Codes + */ +#define IH_OS_INVALID 0 /* Invalid OS */ +#define IH_OS_OPENBSD 1 /* OpenBSD */ +#define IH_OS_NETBSD 2 /* NetBSD */ +#define IH_OS_FREEBSD 3 /* FreeBSD */ +#define IH_OS_4_4BSD 4 /* 4.4BSD */ +#define IH_OS_LINUX 5 /* Linux */ +#define IH_OS_SVR4 6 /* SVR4 */ +#define IH_OS_ESIX 7 /* Esix */ +#define IH_OS_SOLARIS 8 /* Solaris */ +#define IH_OS_IRIX 9 /* Irix */ +#define IH_OS_SCO 10 /* SCO */ +#define IH_OS_DELL 11 /* Dell */ +#define IH_OS_NCR 12 /* NCR */ +#define IH_OS_LYNXOS 13 /* LynxOS */ +#define IH_OS_VXWORKS 14 /* VxWorks */ +#define IH_OS_PSOS 15 /* pSOS */ +#define IH_OS_QNX 16 /* QNX */ +#define IH_OS_U_BOOT 17 /* Firmware */ +#define IH_OS_RTEMS 18 /* RTEMS */ +#define IH_OS_ARTOS 19 /* ARTOS */ +#define IH_OS_UNITY 20 /* Unity OS */ + +/* + * CPU Architecture Codes (supported by Linux) + */ +#define IH_CPU_INVALID 0 /* Invalid CPU */ +#define IH_CPU_ALPHA 1 /* Alpha */ +#define IH_CPU_ARM 2 /* ARM */ +#define IH_CPU_I386 3 /* Intel x86 */ +#define IH_CPU_IA64 4 /* IA64 */ +#define IH_CPU_MIPS 5 /* MIPS */ +#define IH_CPU_MIPS64 6 /* MIPS 64 Bit */ +#define IH_CPU_PPC 7 /* PowerPC */ +#define IH_CPU_S390 8 /* IBM S390 */ +#define IH_CPU_SH 9 /* SuperH */ +#define IH_CPU_SPARC 10 /* Sparc */ +#define IH_CPU_SPARC64 11 /* Sparc 64 Bit */ +#define IH_CPU_M68K 12 /* M68K */ +#define IH_CPU_NIOS 13 /* Nios-32 */ +#define IH_CPU_MICROBLAZE 14 /* MicroBlaze */ +#define IH_CPU_NIOS2 15 /* Nios-II */ + +/* + * Image Types + * + * "Standalone Programs" are directly runnable in the environment + * provided by U-Boot; it is expected that (if they behave + * well) you can continue to work in U-Boot after return from + * the Standalone Program. + * "OS Kernel Images" are usually images of some Embedded OS which + * will take over control completely. Usually these programs + * will install their own set of exception handlers, device + * drivers, set up the MMU, etc. - this means, that you cannot + * expect to re-enter U-Boot except by resetting the CPU. + * "RAMDisk Images" are more or less just data blocks, and their + * parameters (address, size) are passed to an OS kernel that is + * being started. + * "Multi-File Images" contain several images, typically an OS + * (Linux) kernel image and one or more data images like + * RAMDisks. This construct is useful for instance when you want + * to boot over the network using BOOTP etc., where the boot + * server provides just a single image file, but you want to get + * for instance an OS kernel and a RAMDisk image. + * + * "Multi-File Images" start with a list of image sizes, each + * image size (in bytes) specified by an "uint32_t" in network + * byte order. This list is terminated by an "(uint32_t)0". + * Immediately after the terminating 0 follow the images, one by + * one, all aligned on "uint32_t" boundaries (size rounded up to + * a multiple of 4 bytes - except for the last file). + * + * "Firmware Images" are binary images containing firmware (like + * U-Boot or FPGA images) which usually will be programmed to + * flash memory. + * + * "Script files" are command sequences that will be executed by + * U-Boot's command interpreter; this feature is especially + * useful when you configure U-Boot to use a real shell (hush) + * as command interpreter (=> Shell Scripts). + */ + +#define IH_TYPE_INVALID 0 /* Invalid Image */ +#define IH_TYPE_STANDALONE 1 /* Standalone Program */ +#define IH_TYPE_KERNEL 2 /* OS Kernel Image */ +#define IH_TYPE_RAMDISK 3 /* RAMDisk Image */ +#define IH_TYPE_MULTI 4 /* Multi-File Image */ +#define IH_TYPE_FIRMWARE 5 /* Firmware Image */ +#define IH_TYPE_SCRIPT 6 /* Script file */ +#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ + +/* + * Compression Types + */ +#define IH_COMP_NONE 0 /* No Compression Used */ +#define IH_COMP_GZIP 1 /* gzip Compression Used */ +#define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ + +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ + +#define IH_NAMEMAGIC 0x86680001 /* Name Magic Number */ +#define IH_SIZEMAX 5800000 /* Max image size */ +/* + * all data in network byte order (aka natural aka bigendian) + */ + +typedef struct image_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ +#ifdef NEW_IMAGE_HEADER + uint32_t ih_namemagic; /* image name CRC */ + uint8_t ih_name[IH_NMLEN-4]; /* image name */ +#else + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +#endif +} image_header_t; + + +#endif /* __IMAGE_H__ */ diff --git a/target/linux/adm8668/image/lzma-loader/src/lzma.lds.in b/target/linux/adm8668/image/lzma-loader/src/lzma.lds.in new file mode 100644 index 0000000..d6c60ca --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/lzma.lds.in @@ -0,0 +1,24 @@ +OUTPUT_ARCH(mips) +ENTRY(entry) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = @LOADADDR@; + .text : + { + _ftext = . ; + *(.text.entry) + *(.text) + lzma_start = .; + kernel.o + lzma_end = .; + *(.rodata) + } =0 + + .reginfo : { *(.reginfo) } + + .bss : + { + *(.bss) + } +} diff --git a/target/linux/adm8668/image/lzma-loader/src/stubs.c b/target/linux/adm8668/image/lzma-loader/src/stubs.c new file mode 100644 index 0000000..468e5a1 --- /dev/null +++ b/target/linux/adm8668/image/lzma-loader/src/stubs.c @@ -0,0 +1,52 @@ +#include + +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) +#endif /* GCC_VERSION */ + +/* + * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call- + * clobbered register that is also used to set gp ($26). Note that the + * jr instruction also executes the instruction immediately following + * it; however, GCC/mips generates an additional `nop' after each asm + * statement + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" lw $25, %0($26)\n" \ +" lw $25, %1($25)\n" \ +" jr $25\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "t9"); + +/* This function is necessary to prevent the compiler from + * generating prologue/epilogue, preparing stack frame etc. + * The stub functions are special, they do not use the stack + * frame passed to them, but pass it intact to the actual + * implementation. On the other hand, asm() statements with + * arguments can be used only inside the functions (gcc limitation) + */ +#if GCC_VERSION < 3004 +static +#endif /* GCC_VERSION */ +void __attribute__((unused)) dummy(void) +{ +#include <_exports.h> +} + +#if 0 +extern unsigned long __bss_start, _end; + +void app_startup(char **argv) +{ + unsigned long * cp = &__bss_start; + + /* Zero out BSS */ + while (cp < &_end) { + *cp++ = 0; + } +} +#endif + +#undef EXPORT_FUNC diff --git a/target/linux/adm8668/image/my-mkimage b/target/linux/adm8668/image/my-mkimage new file mode 100755 index 0000000..7ed6666 --- /dev/null +++ b/target/linux/adm8668/image/my-mkimage @@ -0,0 +1,32 @@ +#!/bin/sh +# my-mkimage +# This will pad given files to 64k boundaries to make a single u-boot image. +# we have to be fancy because u-boot mkimage is going to add 64 byte header, ... +# and i only know basic arithmetic.. ;) +# +# Copyright (C) 2010 Scott Nicholas +[ $# -lt 2 ] && { + echo usage: $0 loader.bin [rootfs.squashfs [fs_mark [...]]] output.bin +} + +OLDSIZE=$(stat -c%s $1) +NEWSIZE=$(((OLDSIZE / 65536 + 1) * 65536 - 64)) + +dd if=$1 of=vmlinuz.tmp bs=$NEWSIZE conv=sync >/dev/null 2>&1 +shift +appends=$(($# - 1)) +echo +while [ $appends -gt 0 ]; do + dd if=$1 of=temp bs=64k conv=sync >/dev/null 2>&1 + printf "### '%s' starts at 0x%x\n" "`basename $1`" "$((NEWSIZE+64))" + cat temp >>vmlinuz.tmp + shift + appends=$((appends-1)) + NEWSIZE=$(stat -c%s vmlinuz.tmp) +done +echo +../../../../staging_dir/host/bin/mkimage -A mips -O linux -T kernel \ +-C none -a 0x80400000 -e 0x80400000 -n "ADM8668 Linux Kernel(2.4.31)" \ +-d vmlinuz.tmp $1 + +rm temp vmlinuz.tmp diff --git a/target/linux/adm8668/patches-3.18/001-adm8668_arch.patch b/target/linux/adm8668/patches-3.18/001-adm8668_arch.patch new file mode 100644 index 0000000..80e9ed1 --- /dev/null +++ b/target/linux/adm8668/patches-3.18/001-adm8668_arch.patch @@ -0,0 +1,48 @@ +--- a/arch/mips/Kbuild.platforms ++++ b/arch/mips/Kbuild.platforms +@@ -30,6 +30,7 @@ platforms += sibyte + platforms += sni + platforms += txx9 + platforms += vr41xx ++platforms += adm8668 + + # include the platform specific files + include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms)) +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -136,6 +136,27 @@ config BCM47XX + help + Support for BCM47XX based boards + ++config ADM8668 ++ bool "WildPass ADM8668" ++ select SYS_HAS_CPU_MIPS32_R1 ++ select BOOT_RAW ++ select NO_EXCEPT_FILL ++ select IRQ_CPU ++ select CEVT_R4K ++ select CSRC_R4K ++ select HW_HAS_PCI ++ select PCI ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select DMA_NONCOHERENT ++ select SWAP_IO_SPACE ++ select SYS_HAS_EARLY_PRINTK ++ select ARCH_REQUIRE_GPIOLIB ++ select HAVE_CLK ++ help ++ ADM8668 board support by neutronscott ++ Scott Nicholas ++ + config BCM63XX + bool "Broadcom BCM63XX based boards" + select BOOT_RAW +@@ -834,6 +855,7 @@ config MIPS_PARAVIRT + + endchoice + ++source "arch/mips/adm8668/Kconfig" + source "arch/mips/alchemy/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm47xx/Kconfig" diff --git a/target/linux/adm8668/patches-3.18/002-adm8668_pci.patch b/target/linux/adm8668/patches-3.18/002-adm8668_pci.patch new file mode 100644 index 0000000..70ee00d --- /dev/null +++ b/target/linux/adm8668/patches-3.18/002-adm8668_pci.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -58,6 +58,7 @@ obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32 + obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o + obj-$(CONFIG_CPU_XLR) += pci-xlr.o + obj-$(CONFIG_CPU_XLP) += pci-xlp.o ++obj-$(CONFIG_ADM8668) += pci-adm8668.o + + ifdef CONFIG_PCI_MSI + obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -1820,6 +1820,9 @@ + + #define PCI_VENDOR_ID_CB 0x1307 /* Measurement Computing */ + ++#define PCI_VENDOR_ADMTEK 0x1317 ++#define PCI_DEVICE_ID_ADM8668 0x8688 ++ + #define PCI_VENDOR_ID_SIIG 0x131f + #define PCI_SUBVENDOR_ID_SIIG 0x131f + #define PCI_DEVICE_ID_SIIG_1S_10x_550 0x1000 diff --git a/target/linux/adm8668/patches-3.18/003-adm8668_nor_map.patch b/target/linux/adm8668/patches-3.18/003-adm8668_nor_map.patch new file mode 100644 index 0000000..f7883cd --- /dev/null +++ b/target/linux/adm8668/patches-3.18/003-adm8668_nor_map.patch @@ -0,0 +1,22 @@ +--- a/drivers/mtd/maps/Kconfig ++++ b/drivers/mtd/maps/Kconfig +@@ -97,6 +97,12 @@ config MSP_FLASH_MAP_LIMIT + default "0x02000000" + depends on MSP_FLASH_MAP_LIMIT_32M + ++config MTD_ADM8668_NOR ++ tristate "ADM8668 NOR mapping" ++ depends on ADM8668 && MTD_CFI ++ help ++ mapping driver for ADM8668 NOR ++ + config MTD_SUN_UFLASH + tristate "Sun Microsystems userflash support" + depends on SPARC && MTD_CFI && PCI +--- a/drivers/mtd/maps/Makefile ++++ b/drivers/mtd/maps/Makefile +@@ -43,3 +43,4 @@ obj-$(CONFIG_MTD_VMU) += vmu-flash.o + obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o + obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o + obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o ++obj-$(CONFIG_MTD_ADM8668_NOR) += adm8668.o diff --git a/target/linux/adm8668/patches-3.18/004-tulip_pci_split.patch b/target/linux/adm8668/patches-3.18/004-tulip_pci_split.patch new file mode 100644 index 0000000..e57bdb7 --- /dev/null +++ b/target/linux/adm8668/patches-3.18/004-tulip_pci_split.patch @@ -0,0 +1,452 @@ +--- a/drivers/net/ethernet/dec/tulip/tulip_core.c ++++ b/drivers/net/ethernet/dec/tulip/tulip_core.c +@@ -207,6 +207,7 @@ struct tulip_chip_table tulip_tbl[] = { + }; + + ++#ifdef CONFIG_TULIP_PCI + static const struct pci_device_id tulip_pci_tbl[] = { + { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 }, + { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 }, +@@ -250,7 +251,7 @@ static const struct pci_device_id tulip_ + { } /* terminate list */ + }; + MODULE_DEVICE_TABLE(pci, tulip_pci_tbl); +- ++#endif + + /* A full-duplex map for media types. */ + const char tulip_media_cap[32] = +@@ -268,11 +269,14 @@ static void tulip_down(struct net_device + static struct net_device_stats *tulip_get_stats(struct net_device *dev); + static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); + static void set_rx_mode(struct net_device *dev); ++#ifdef CONFIG_TULIP_PCI + static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts); ++#endif + #ifdef CONFIG_NET_POLL_CONTROLLER + static void poll_tulip(struct net_device *dev); + #endif + ++#ifdef CONFIG_TULIP_PCI + static void tulip_set_power_state (struct tulip_private *tp, + int sleep, int snooze) + { +@@ -289,7 +293,7 @@ static void tulip_set_power_state (struc + } + + } +- ++#endif + + static void tulip_up(struct net_device *dev) + { +@@ -303,6 +307,7 @@ static void tulip_up(struct net_device * + napi_enable(&tp->napi); + #endif + ++#ifdef CONFIG_TULIP_PCI + /* Wake the chip from sleep/snooze mode. */ + tulip_set_power_state (tp, 0, 0); + +@@ -310,6 +315,7 @@ static void tulip_up(struct net_device * + pci_enable_wake(tp->pdev, PCI_D3hot, 0); + pci_enable_wake(tp->pdev, PCI_D3cold, 0); + tulip_set_wolopts(tp->pdev, 0); ++#endif + + /* On some chip revs we must set the MII/SYM port before the reset!? */ + if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii)) +@@ -317,18 +323,22 @@ static void tulip_up(struct net_device * + + /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ + iowrite32(0x00000001, ioaddr + CSR0); ++#ifdef CONFIG_TULIP_PCI + pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */ ++#endif + udelay(100); + + /* Deassert reset. + Wait the specified 50 PCI cycles after a reset by initializing + Tx and Rx queues and the address filter list. */ + iowrite32(tp->csr0, ioaddr + CSR0); ++#ifdef CONFIG_TULIP_PCI + pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */ ++#endif + udelay(100); + + if (tulip_debug > 1) +- netdev_dbg(dev, "tulip_up(), irq==%d\n", tp->pdev->irq); ++ netdev_dbg(dev, "tulip_up(), irq==%d\n", tp->irq); + + iowrite32(tp->rx_ring_dma, ioaddr + CSR3); + iowrite32(tp->tx_ring_dma, ioaddr + CSR4); +@@ -362,9 +372,11 @@ static void tulip_up(struct net_device * + *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1]; + *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2]; + ++#ifdef CONFIG_TULIP_PCI + mapping = pci_map_single(tp->pdev, tp->setup_frame, + sizeof(tp->setup_frame), + PCI_DMA_TODEVICE); ++#endif + tp->tx_buffers[tp->cur_tx].skb = NULL; + tp->tx_buffers[tp->cur_tx].mapping = mapping; + +@@ -520,7 +532,7 @@ tulip_open(struct net_device *dev) + + tulip_init_ring (dev); + +- retval = request_irq(tp->pdev->irq, tulip_interrupt, IRQF_SHARED, ++ retval = request_irq(tp->irq, tulip_interrupt, IRQF_SHARED, + dev->name, dev); + if (retval) + goto free_ring; +@@ -644,8 +656,10 @@ static void tulip_init_ring(struct net_d + tp->rx_buffers[i].skb = skb; + if (skb == NULL) + break; ++#ifdef CONFIG_TULIP_PCI + mapping = pci_map_single(tp->pdev, skb->data, + PKT_BUF_SZ, PCI_DMA_FROMDEVICE); ++#endif + tp->rx_buffers[i].mapping = mapping; + tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */ + tp->rx_ring[i].buffer1 = cpu_to_le32(mapping); +@@ -678,8 +692,10 @@ tulip_start_xmit(struct sk_buff *skb, st + entry = tp->cur_tx % TX_RING_SIZE; + + tp->tx_buffers[entry].skb = skb; ++#ifdef CONFIG_TULIP_PCI + mapping = pci_map_single(tp->pdev, skb->data, + skb->len, PCI_DMA_TODEVICE); ++#endif + tp->tx_buffers[entry].mapping = mapping; + tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping); + +@@ -730,16 +746,19 @@ static void tulip_clean_tx_ring(struct t + if (tp->tx_buffers[entry].skb == NULL) { + /* test because dummy frames not mapped */ + if (tp->tx_buffers[entry].mapping) ++#ifdef CONFIG_TULIP_PCI + pci_unmap_single(tp->pdev, + tp->tx_buffers[entry].mapping, + sizeof(tp->setup_frame), + PCI_DMA_TODEVICE); ++#endif + continue; + } +- ++#ifdef CONFIG_TULIP_PCI + pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping, + tp->tx_buffers[entry].skb->len, + PCI_DMA_TODEVICE); ++#endif + + /* Free the original skb. */ + dev_kfree_skb_irq(tp->tx_buffers[entry].skb); +@@ -790,7 +809,9 @@ static void tulip_down (struct net_devic + dev->if_port = tp->saved_if_port; + + /* Leave the driver in snooze, not sleep, mode. */ ++#ifdef CONFIG_TULIP_PCI + tulip_set_power_state (tp, 0, 1); ++#endif + } + + static void tulip_free_ring (struct net_device *dev) +@@ -811,8 +832,10 @@ static void tulip_free_ring (struct net_ + /* An invalid address. */ + tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0); + if (skb) { ++#ifdef CONFIG_TULIP_PCI + pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ, + PCI_DMA_FROMDEVICE); ++#endif + dev_kfree_skb (skb); + } + } +@@ -821,8 +844,10 @@ static void tulip_free_ring (struct net_ + struct sk_buff *skb = tp->tx_buffers[i].skb; + + if (skb != NULL) { ++#ifdef CONFIG_TULIP_PCI + pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping, + skb->len, PCI_DMA_TODEVICE); ++#endif + dev_kfree_skb (skb); + } + tp->tx_buffers[i].skb = NULL; +@@ -843,7 +868,7 @@ static int tulip_close (struct net_devic + netdev_dbg(dev, "Shutting down ethercard, status was %02x\n", + ioread32 (ioaddr + CSR5)); + +- free_irq (tp->pdev->irq, dev); ++ free_irq (tp->irq, dev); + + tulip_free_ring (dev); + +@@ -874,7 +899,9 @@ static void tulip_get_drvinfo(struct net + struct tulip_private *np = netdev_priv(dev); + strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); + strlcpy(info->version, DRV_VERSION, sizeof(info->version)); ++#ifdef CONFIG_TULIP_PCI + strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info)); ++#endif + } + + +@@ -887,7 +914,9 @@ static int tulip_ethtool_set_wol(struct + return -EOPNOTSUPP; + + tp->wolinfo.wolopts = wolinfo->wolopts; +- device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts); ++#ifdef CONFIG_TULIP_PCI ++ device_set_wakeup_enable(tp->kdev, tp->wolinfo.wolopts); ++#endif + return 0; + } + +@@ -1165,9 +1194,11 @@ static void set_rx_mode(struct net_devic + + tp->tx_buffers[entry].skb = NULL; + tp->tx_buffers[entry].mapping = ++#ifdef CONFIG_TULIP_PCI + pci_map_single(tp->pdev, tp->setup_frame, + sizeof(tp->setup_frame), + PCI_DMA_TODEVICE); ++#endif + /* Put the setup frame on the Tx list. */ + if (entry == TX_RING_SIZE-1) + tx_flags |= DESC_RING_WRAP; /* Wrap ring. */ +@@ -1264,19 +1295,22 @@ out: + netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n", + cache, csr0); + } +-#endif + + /* + * Chips that have the MRM/reserved bit quirk and the burst quirk. That + * is the DM910X and the on chip ULi devices + */ ++#endif + ++#ifdef CONFIG_TULIP_PCI + static int tulip_uli_dm_quirk(struct pci_dev *pdev) + { + if (pdev->vendor == 0x1282 && pdev->device == 0x9102) + return 1; + return 0; + } ++#endif ++ + + static const struct net_device_ops tulip_netdev_ops = { + .ndo_open = tulip_open, +@@ -1294,6 +1328,7 @@ static const struct net_device_ops tulip + #endif + }; + ++#ifdef CONFIG_TULIP_PCI + const struct pci_device_id early_486_chipsets[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) }, + { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) }, +@@ -1471,6 +1506,8 @@ static int tulip_init_one(struct pci_dev + } + } + tp->pdev = pdev; ++ tp->kdev = &pdev->dev; ++ tp->irq = irq; + tp->base_addr = ioaddr; + tp->revision = pdev->revision; + tp->csr0 = csr0; +@@ -1801,6 +1838,7 @@ err_out_free_netdev: + } + + ++#ifdef CONFIG_TULIP_PCI + /* set the registers according to the given wolopts */ + static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts) + { +@@ -1829,6 +1867,7 @@ static void tulip_set_wolopts (struct pc + iowrite32(tmp, ioaddr + CSR13); + } + } ++#endif + + #ifdef CONFIG_PM + +@@ -1943,6 +1982,7 @@ static void tulip_remove_one(struct pci_ + + /* pci_power_off (pdev, -1); */ + } ++#endif /* CONFIG_TULIP_PCI */ + + #ifdef CONFIG_NET_POLL_CONTROLLER + /* +@@ -1964,7 +2004,8 @@ static void poll_tulip (struct net_devic + } + #endif + +-static struct pci_driver tulip_driver = { ++#ifdef CONFIG_TULIP_PCI ++static struct pci_driver tulip_pci_driver = { + .name = DRV_NAME, + .id_table = tulip_pci_tbl, + .probe = tulip_init_one, +@@ -1974,10 +2015,12 @@ static struct pci_driver tulip_driver = + .resume = tulip_resume, + #endif /* CONFIG_PM */ + }; ++#endif + + + static int __init tulip_init (void) + { ++ int ret = 0; + #ifdef MODULE + pr_info("%s", version); + #endif +@@ -1987,13 +2030,18 @@ static int __init tulip_init (void) + tulip_max_interrupt_work = max_interrupt_work; + + /* probe for and init boards */ +- return pci_register_driver(&tulip_driver); ++#ifdef CONFIG_TULIP_PCI ++ ret = pci_register_driver(&tulip_pci_driver); ++#endif ++ return ret; + } + + + static void __exit tulip_cleanup (void) + { +- pci_unregister_driver (&tulip_driver); ++#ifdef CONFIG_TULIP_PCI ++ pci_unregister_driver (&tulip_pci_driver); ++#endif + } + + +--- a/drivers/net/ethernet/dec/tulip/interrupt.c ++++ b/drivers/net/ethernet/dec/tulip/interrupt.c +@@ -73,10 +73,11 @@ int tulip_refill_rx(struct net_device *d + netdev_alloc_skb(dev, PKT_BUF_SZ); + if (skb == NULL) + break; +- ++#ifdef CONFIG_TULIP_PCI + mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ, + PCI_DMA_FROMDEVICE); +- if (dma_mapping_error(&tp->pdev->dev, mapping)) { ++#endif ++ if (dma_mapping_error(tp->kdev, mapping)) { + dev_kfree_skb(skb); + tp->rx_buffers[entry].skb = NULL; + break; +@@ -210,9 +211,11 @@ int tulip_poll(struct napi_struct *napi, + if (pkt_len < tulip_rx_copybreak && + (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) { + skb_reserve(skb, 2); /* 16 byte align the IP header */ ++#ifdef CONFIG_TULIP_PCI + pci_dma_sync_single_for_cpu(tp->pdev, + tp->rx_buffers[entry].mapping, + pkt_len, PCI_DMA_FROMDEVICE); ++#endif + #if ! defined(__alpha__) + skb_copy_to_linear_data(skb, tp->rx_buffers[entry].skb->data, + pkt_len); +@@ -222,9 +225,11 @@ int tulip_poll(struct napi_struct *napi, + tp->rx_buffers[entry].skb->data, + pkt_len); + #endif ++#ifdef CONFIG_TULIP_PCI + pci_dma_sync_single_for_device(tp->pdev, + tp->rx_buffers[entry].mapping, + pkt_len, PCI_DMA_FROMDEVICE); ++#endif + } else { /* Pass up the skb already on the Rx ring. */ + char *temp = skb_put(skb = tp->rx_buffers[entry].skb, + pkt_len); +@@ -239,9 +244,10 @@ int tulip_poll(struct napi_struct *napi, + skb->head, temp); + } + #endif +- ++#ifdef CONFIG_TULIP_PCI + pci_unmap_single(tp->pdev, tp->rx_buffers[entry].mapping, + PKT_BUF_SZ, PCI_DMA_FROMDEVICE); ++#endif + + tp->rx_buffers[entry].skb = NULL; + tp->rx_buffers[entry].mapping = 0; +@@ -597,10 +603,12 @@ irqreturn_t tulip_interrupt(int irq, voi + if (tp->tx_buffers[entry].skb == NULL) { + /* test because dummy frames not mapped */ + if (tp->tx_buffers[entry].mapping) ++#ifdef CONFIG_TULIP_PCI + pci_unmap_single(tp->pdev, + tp->tx_buffers[entry].mapping, + sizeof(tp->setup_frame), + PCI_DMA_TODEVICE); ++#endif + continue; + } + +@@ -628,10 +636,11 @@ irqreturn_t tulip_interrupt(int irq, voi + dev->stats.collisions += (status >> 3) & 15; + dev->stats.tx_packets++; + } +- ++#ifdef CONFIG_TULIP_PCI + pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping, + tp->tx_buffers[entry].skb->len, + PCI_DMA_TODEVICE); ++#endif + + /* Free the original skb. */ + dev_kfree_skb_irq(tp->tx_buffers[entry].skb); +--- a/drivers/net/ethernet/dec/tulip/Kconfig ++++ b/drivers/net/ethernet/dec/tulip/Kconfig +@@ -40,8 +40,12 @@ config DE2104X_DSL + Default is 0, and range is 0 to 31. + + config TULIP ++ tristate ++ ++config TULIP_PCI + tristate "DECchip Tulip (dc2114x) PCI support" + depends on PCI ++ select TULIP + select CRC32 + ---help--- + This driver is developed for the SMC EtherPower series Ethernet +@@ -58,7 +62,7 @@ config TULIP + + config TULIP_MWI + bool "New bus configuration" +- depends on TULIP ++ depends on TULIP_PCI + ---help--- + This configures your Tulip card specifically for the card and + system cache line size type you are using. +@@ -69,7 +73,7 @@ config TULIP_MWI + + config TULIP_MMIO + bool "Use PCI shared mem for NIC registers" +- depends on TULIP ++ depends on TULIP_PCI + ---help--- + Use PCI shared memory for the NIC registers, rather than going through + the Tulip's PIO (programmed I/O ports). Faster, but could produce +--- a/drivers/net/ethernet/dec/tulip/tulip.h ++++ b/drivers/net/ethernet/dec/tulip/tulip.h +@@ -447,6 +447,8 @@ struct tulip_private { + int cur_index; /* Current media index. */ + int saved_if_port; + struct pci_dev *pdev; ++ struct device *kdev; ++ int irq; + int ttimer; + int susp_rx; + unsigned long nir; diff --git a/target/linux/adm8668/patches-3.18/005-tulip_platform.patch b/target/linux/adm8668/patches-3.18/005-tulip_platform.patch new file mode 100644 index 0000000..bddc572 --- /dev/null +++ b/target/linux/adm8668/patches-3.18/005-tulip_platform.patch @@ -0,0 +1,490 @@ +--- a/drivers/net/ethernet/dec/tulip/Kconfig ++++ b/drivers/net/ethernet/dec/tulip/Kconfig +@@ -60,6 +60,14 @@ config TULIP_PCI + To compile this driver as a module, choose M here. The module will + be called tulip. + ++config TULIP_PLATFORM ++ tristate "DECchip Tulip (dc2114x) Platform support" ++ depends on HAS_IOMEM ++ select TULIP ++ select CRC32 ++ ---help--- ++ This driver is for the platform variant. ++ + config TULIP_MWI + bool "New bus configuration" + depends on TULIP_PCI +--- a/drivers/net/ethernet/dec/tulip/tulip_core.c ++++ b/drivers/net/ethernet/dec/tulip/tulip_core.c +@@ -27,6 +27,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -204,6 +206,9 @@ struct tulip_chip_table tulip_tbl[] = { + { "Conexant LANfinity", 256, 0x0001ebef, + HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task }, + ++ { "Infineon ADM8668", 256, 0x0001a451, ++ MC_HASH_ONLY | COMET_MAC_ADDR, tulip_timer, tulip_media_task, }, ++ + }; + + +@@ -377,6 +382,11 @@ static void tulip_up(struct net_device * + sizeof(tp->setup_frame), + PCI_DMA_TODEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ mapping = dma_map_single(&tp->pldev->dev, tp->setup_frame, ++ sizeof(tp->setup_frame), ++ DMA_TO_DEVICE); ++#endif + tp->tx_buffers[tp->cur_tx].skb = NULL; + tp->tx_buffers[tp->cur_tx].mapping = mapping; + +@@ -396,6 +406,7 @@ static void tulip_up(struct net_device * + i = 0; + if (tp->mtable == NULL) + goto media_picked; ++ + if (dev->if_port) { + int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 : + (dev->if_port == 12 ? 0 : dev->if_port); +@@ -489,6 +500,10 @@ media_picked: + iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88); + dev->if_port = tp->mii_cnt ? 11 : 0; + tp->csr6 = 0x00040000; ++ } else if (tp->chip_id == ADM8668) { ++ /* Enable automatic Tx underrun recovery. */ ++ iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88); ++ tp->csr6 = 0x00040000; + } else if (tp->chip_id == AX88140) { + tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100; + } else +@@ -660,6 +675,10 @@ static void tulip_init_ring(struct net_d + mapping = pci_map_single(tp->pdev, skb->data, + PKT_BUF_SZ, PCI_DMA_FROMDEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ mapping = dma_map_single(&tp->pldev->dev, skb->data, ++ PKT_BUF_SZ, DMA_FROM_DEVICE); ++#endif + tp->rx_buffers[i].mapping = mapping; + tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */ + tp->rx_ring[i].buffer1 = cpu_to_le32(mapping); +@@ -696,6 +715,11 @@ tulip_start_xmit(struct sk_buff *skb, st + mapping = pci_map_single(tp->pdev, skb->data, + skb->len, PCI_DMA_TODEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ mapping = dma_map_single(&tp->pldev->dev, skb->data, ++ skb->len, ++ DMA_TO_DEVICE); ++#endif + tp->tx_buffers[entry].mapping = mapping; + tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping); + +@@ -752,6 +776,13 @@ static void tulip_clean_tx_ring(struct t + sizeof(tp->setup_frame), + PCI_DMA_TODEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ dma_unmap_single(&tp->pldev->dev, ++ tp->tx_buffers[entry].mapping, ++ sizeof(tp->setup_frame), ++ DMA_TO_DEVICE); ++#endif ++ + continue; + } + #ifdef CONFIG_TULIP_PCI +@@ -759,6 +790,11 @@ static void tulip_clean_tx_ring(struct t + tp->tx_buffers[entry].skb->len, + PCI_DMA_TODEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ dma_unmap_single(&tp->pldev->dev, tp->tx_buffers[entry].mapping, ++ tp->tx_buffers[entry].skb->len, ++ DMA_TO_DEVICE); ++#endif + + /* Free the original skb. */ + dev_kfree_skb_irq(tp->tx_buffers[entry].skb); +@@ -836,6 +872,10 @@ static void tulip_free_ring (struct net_ + pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ, + PCI_DMA_FROMDEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ dma_unmap_single(&tp->pldev->dev, mapping, PKT_BUF_SZ, ++ DMA_FROM_DEVICE); ++#endif + dev_kfree_skb (skb); + } + } +@@ -848,6 +888,10 @@ static void tulip_free_ring (struct net_ + pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping, + skb->len, PCI_DMA_TODEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ dma_unmap_single(&tp->pldev->dev, tp->tx_buffers[i].mapping, ++ skb->len, DMA_TO_DEVICE); ++#endif + dev_kfree_skb (skb); + } + tp->tx_buffers[i].skb = NULL; +@@ -902,6 +946,9 @@ static void tulip_get_drvinfo(struct net + #ifdef CONFIG_TULIP_PCI + strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info)); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); ++#endif + } + + +@@ -917,6 +964,9 @@ static int tulip_ethtool_set_wol(struct + #ifdef CONFIG_TULIP_PCI + device_set_wakeup_enable(tp->kdev, tp->wolinfo.wolopts); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ device_set_wakeup_enable(&tp->pldev->dev, tp->wolinfo.wolopts); ++#endif + return 0; + } + +@@ -1192,13 +1242,20 @@ static void set_rx_mode(struct net_devic + + } + ++#ifdef CONFIG_TULIP_PCI + tp->tx_buffers[entry].skb = NULL; + tp->tx_buffers[entry].mapping = +-#ifdef CONFIG_TULIP_PCI + pci_map_single(tp->pdev, tp->setup_frame, + sizeof(tp->setup_frame), + PCI_DMA_TODEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ tp->tx_buffers[entry].skb = NULL; ++ tp->tx_buffers[entry].mapping = ++ dma_map_single(&tp->pldev->dev, tp->setup_frame, ++ sizeof(tp->setup_frame), ++ DMA_TO_DEVICE); ++#endif + /* Put the setup frame on the Tx list. */ + if (entry == TX_RING_SIZE-1) + tx_flags |= DESC_RING_WRAP; /* Wrap ring. */ +@@ -1218,6 +1275,9 @@ static void set_rx_mode(struct net_devic + spin_unlock_irqrestore(&tp->lock, flags); + } + ++ if (tp->chip_id == ADM8668) ++ csr6 |= (1 << 9); /* force 100Mbps full duplex */ ++ + iowrite32(csr6, ioaddr + CSR6); + } + +@@ -1984,6 +2044,126 @@ static void tulip_remove_one(struct pci_ + } + #endif /* CONFIG_TULIP_PCI */ + ++#ifdef CONFIG_TULIP_PLATFORM ++static int tulip_probe(struct platform_device *pdev) ++{ ++ struct tulip_private *tp; ++ struct tulip_platform_data *pdata; ++ struct net_device *dev; ++ struct resource *res; ++ void __iomem *ioaddr; ++ int irq; ++ ++ if (pdev->id < 0 || pdev->id >= MAX_UNITS) ++ return -EINVAL; ++ ++ if (!(res = platform_get_resource(pdev, IORESOURCE_IRQ, 0))) ++ return -ENODEV; ++ irq = res->start; ++ if (!(res = platform_get_resource(pdev, IORESOURCE_MEM, 0))) ++ return -ENODEV; ++ if (!(ioaddr = ioremap(res->start, res->end - res->start))) ++ return -ENODEV; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -ENODEV; ++ ++ if (!(dev = alloc_etherdev(sizeof (*tp)))) ++ return -ENOMEM; ++ ++ /* setup net dev */ ++ dev->base_addr = (unsigned long)res->start; ++ dev->irq = irq; ++ SET_NETDEV_DEV(dev, &pdev->dev); ++ ++ /* tulip private struct */ ++ tp = netdev_priv(dev); ++ tp->dev = dev; ++ tp->base_addr = ioaddr; ++ tp->csr0 = 0; ++ tp->pldev = pdev; ++ tp->kdev = &pdev->dev; ++ tp->irq = irq; ++ tp->rx_ring = dma_alloc_coherent(&pdev->dev, ++ sizeof(struct tulip_rx_desc) * RX_RING_SIZE + ++ sizeof(struct tulip_tx_desc) * TX_RING_SIZE, ++ &tp->rx_ring_dma, GFP_KERNEL); ++ if (!tp->rx_ring) ++ return -ENODEV; ++ tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE); ++ tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE; ++ ++ tp->chip_id = pdata->chip_id; ++ tp->flags = tulip_tbl[tp->chip_id].flags; ++ ++ spin_lock_init(&tp->lock); ++ spin_lock_init(&tp->mii_lock); ++ ++ init_timer(&tp->timer); ++ tp->timer.data = (unsigned long)dev; ++ tp->timer.function = tulip_tbl[tp->chip_id].media_timer; ++ ++ INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task); ++ ++ /* Stop the chip's Tx and Rx processes. */ ++ tulip_stop_rxtx(tp); ++ ++ /* Clear the missed-packet counter. */ ++ ioread32(ioaddr + CSR8); ++ ++ if (!is_valid_ether_addr(pdata->mac)) { ++ dev_info(&pdev->dev, "generating random ethernet MAC\n"); ++ random_ether_addr(dev->dev_addr); ++ } else ++ memcpy(dev->dev_addr, pdata->mac, ETH_ALEN); ++ ++ /* The Tulip-specific entries in the device structure. */ ++ dev->netdev_ops = &tulip_netdev_ops; ++ dev->watchdog_timeo = TX_TIMEOUT; ++ netif_napi_add(dev, &tp->napi, tulip_poll, 16); ++ dev->ethtool_ops = &ops; ++ ++ if (register_netdev(dev)) ++ goto err_out_free_ring; ++ ++ dev_info(&dev->dev, ++ "tulip_platform (%s) at MMIO %#lx %pM, IRQ %d\n", ++ tulip_tbl[tp->chip_id].chip_name, ++ (unsigned long)dev->base_addr, dev->dev_addr, irq); ++ ++ platform_set_drvdata(pdev, dev); ++ return 0; ++ ++err_out_free_ring: ++ dma_free_coherent(&pdev->dev, ++ sizeof (struct tulip_rx_desc) * RX_RING_SIZE + ++ sizeof (struct tulip_tx_desc) * TX_RING_SIZE, ++ tp->rx_ring, tp->rx_ring_dma); ++ return -ENODEV; ++} ++ ++static int tulip_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata (pdev); ++ struct tulip_private *tp; ++ ++ if (!dev) ++ return -ENODEV; ++ ++ tp = netdev_priv(dev); ++ unregister_netdev(dev); ++ dma_free_coherent(&pdev->dev, ++ sizeof (struct tulip_rx_desc) * RX_RING_SIZE + ++ sizeof (struct tulip_tx_desc) * TX_RING_SIZE, ++ tp->rx_ring, tp->rx_ring_dma); ++ iounmap(tp->base_addr); ++ free_netdev(dev); ++ platform_set_drvdata(pdev, NULL); ++ return 0; ++} ++#endif ++ + #ifdef CONFIG_NET_POLL_CONTROLLER + /* + * Polling 'interrupt' - used by things like netconsole to send skbs +@@ -2017,6 +2197,17 @@ static struct pci_driver tulip_pci_drive + }; + #endif + ++#ifdef CONFIG_TULIP_PLATFORM ++static struct platform_driver tulip_platform_driver = { ++ .probe = tulip_probe, ++ .remove = tulip_remove, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = DRV_NAME, ++ }, ++}; ++#endif ++ + + static int __init tulip_init (void) + { +@@ -2033,6 +2224,9 @@ static int __init tulip_init (void) + #ifdef CONFIG_TULIP_PCI + ret = pci_register_driver(&tulip_pci_driver); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ ret = platform_driver_register(&tulip_platform_driver); ++#endif + return ret; + } + +@@ -2042,6 +2236,9 @@ static void __exit tulip_cleanup (void) + #ifdef CONFIG_TULIP_PCI + pci_unregister_driver (&tulip_pci_driver); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ platform_driver_unregister (&tulip_platform_driver); ++#endif + } + + +--- a/drivers/net/ethernet/dec/tulip/tulip.h ++++ b/drivers/net/ethernet/dec/tulip/tulip.h +@@ -21,6 +21,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -69,28 +71,6 @@ enum tbl_flag { + }; + + +-/* chip types. careful! order is VERY IMPORTANT here, as these +- * are used throughout the driver as indices into arrays */ +-/* Note 21142 == 21143. */ +-enum chips { +- DC21040 = 0, +- DC21041 = 1, +- DC21140 = 2, +- DC21142 = 3, DC21143 = 3, +- LC82C168, +- MX98713, +- MX98715, +- MX98725, +- AX88140, +- PNIC2, +- COMET, +- COMPEX9881, +- I21145, +- DM910X, +- CONEXANT, +-}; +- +- + enum MediaIs { + MediaIsFD = 1, + MediaAlwaysFD = 2, +@@ -446,7 +426,12 @@ struct tulip_private { + struct mediatable *mtable; + int cur_index; /* Current media index. */ + int saved_if_port; ++#ifdef CONFIG_TULIP_PCI + struct pci_dev *pdev; ++#endif ++#ifdef CONFIG_TULIP_PLATFORM ++ struct platform_device *pldev; ++#endif + struct device *kdev; + int irq; + int ttimer; +--- a/drivers/net/ethernet/dec/tulip/interrupt.c ++++ b/drivers/net/ethernet/dec/tulip/interrupt.c +@@ -77,6 +77,10 @@ int tulip_refill_rx(struct net_device *d + mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ, + PCI_DMA_FROMDEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ mapping = dma_map_single(&tp->pldev->dev, skb->data, PKT_BUF_SZ, ++ DMA_FROM_DEVICE); ++#endif + if (dma_mapping_error(tp->kdev, mapping)) { + dev_kfree_skb(skb); + tp->rx_buffers[entry].skb = NULL; +@@ -204,8 +208,7 @@ int tulip_poll(struct napi_struct *napi, + dev->stats.rx_fifo_errors++; + } + } else { +- struct sk_buff *skb; +- ++ struct sk_buff *skb; + /* Check if the packet is long enough to accept without copying + to a minimally-sized skbuff. */ + if (pkt_len < tulip_rx_copybreak && +@@ -248,6 +251,10 @@ int tulip_poll(struct napi_struct *napi, + pci_unmap_single(tp->pdev, tp->rx_buffers[entry].mapping, + PKT_BUF_SZ, PCI_DMA_FROMDEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ dma_unmap_single(&tp->pldev->dev, tp->rx_buffers[entry].mapping, ++ PKT_BUF_SZ, DMA_FROM_DEVICE); ++#endif + + tp->rx_buffers[entry].skb = NULL; + tp->rx_buffers[entry].mapping = 0; +@@ -641,6 +648,11 @@ irqreturn_t tulip_interrupt(int irq, voi + tp->tx_buffers[entry].skb->len, + PCI_DMA_TODEVICE); + #endif ++#ifdef CONFIG_TULIP_PLATFORM ++ dma_unmap_single(&tp->pldev->dev, tp->tx_buffers[entry].mapping, ++ tp->tx_buffers[entry].skb->len, ++ DMA_TO_DEVICE); ++#endif + + /* Free the original skb. */ + dev_kfree_skb_irq(tp->tx_buffers[entry].skb); +--- /dev/null ++++ b/include/linux/platform_data/tulip.h +@@ -0,0 +1,31 @@ ++#ifndef _LINUX_TULIP_PDATA_H ++#define _LINUX_TULIP_PDATA_H ++ ++/* chip types. careful! order is VERY IMPORTANT here, as these ++ * are used throughout the driver as indices into arrays */ ++/* Note 21142 == 21143. */ ++enum chips { ++ DC21040 = 0, ++ DC21041 = 1, ++ DC21140 = 2, ++ DC21142 = 3, DC21143 = 3, ++ LC82C168, ++ MX98713, ++ MX98715, ++ MX98725, ++ AX88140, ++ PNIC2, ++ COMET, ++ COMPEX9881, ++ I21145, ++ DM910X, ++ CONEXANT, ++ ADM8668, ++}; ++ ++struct tulip_platform_data { ++ u8 mac[6]; ++ enum chips chip_id; ++}; ++ ++#endif diff --git a/target/linux/adm8668/patches-3.18/200-amba_pl010_hacks.patch b/target/linux/adm8668/patches-3.18/200-amba_pl010_hacks.patch new file mode 100644 index 0000000..66f4f25 --- /dev/null +++ b/target/linux/adm8668/patches-3.18/200-amba_pl010_hacks.patch @@ -0,0 +1,377 @@ +--- a/drivers/tty/serial/amba-pl010.c ++++ b/drivers/tty/serial/amba-pl010.c +@@ -48,11 +48,10 @@ + #include + #include + +-#define UART_NR 8 +- + #define SERIAL_AMBA_MAJOR 204 + #define SERIAL_AMBA_MINOR 16 +-#define SERIAL_AMBA_NR UART_NR ++#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS ++#define SERIAL_AMBA_NAME CONFIG_SERIAL_AMBA_PL010_PORTNAME + + #define AMBA_ISR_PASS_LIMIT 256 + +@@ -78,9 +77,9 @@ static void pl010_stop_tx(struct uart_po + struct uart_amba_port *uap = (struct uart_amba_port *)port; + unsigned int cr; + +- cr = readb(uap->port.membase + UART010_CR); ++ cr = __raw_readl(uap->port.membase + UART010_CR); + cr &= ~UART010_CR_TIE; +- writel(cr, uap->port.membase + UART010_CR); ++ __raw_writel(cr, uap->port.membase + UART010_CR); + } + + static void pl010_start_tx(struct uart_port *port) +@@ -88,9 +87,9 @@ static void pl010_start_tx(struct uart_p + struct uart_amba_port *uap = (struct uart_amba_port *)port; + unsigned int cr; + +- cr = readb(uap->port.membase + UART010_CR); ++ cr = __raw_readl(uap->port.membase + UART010_CR); + cr |= UART010_CR_TIE; +- writel(cr, uap->port.membase + UART010_CR); ++ __raw_writel(cr, uap->port.membase + UART010_CR); + } + + static void pl010_stop_rx(struct uart_port *port) +@@ -98,9 +97,9 @@ static void pl010_stop_rx(struct uart_po + struct uart_amba_port *uap = (struct uart_amba_port *)port; + unsigned int cr; + +- cr = readb(uap->port.membase + UART010_CR); ++ cr = __raw_readl(uap->port.membase + UART010_CR); + cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); +- writel(cr, uap->port.membase + UART010_CR); ++ __raw_writel(cr, uap->port.membase + UART010_CR); + } + + static void pl010_enable_ms(struct uart_port *port) +@@ -108,18 +107,18 @@ static void pl010_enable_ms(struct uart_ + struct uart_amba_port *uap = (struct uart_amba_port *)port; + unsigned int cr; + +- cr = readb(uap->port.membase + UART010_CR); ++ cr = __raw_readl(uap->port.membase + UART010_CR); + cr |= UART010_CR_MSIE; +- writel(cr, uap->port.membase + UART010_CR); ++ __raw_writel(cr, uap->port.membase + UART010_CR); + } + + static void pl010_rx_chars(struct uart_amba_port *uap) + { + unsigned int status, ch, flag, rsr, max_count = 256; + +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + while (UART_RX_DATA(status) && max_count--) { +- ch = readb(uap->port.membase + UART01x_DR); ++ ch = __raw_readl(uap->port.membase + UART01x_DR); + flag = TTY_NORMAL; + + uap->port.icount.rx++; +@@ -128,9 +127,9 @@ static void pl010_rx_chars(struct uart_a + * Note that the error handling code is + * out of the main execution path + */ +- rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; ++ rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; + if (unlikely(rsr & UART01x_RSR_ANY)) { +- writel(0, uap->port.membase + UART01x_ECR); ++ __raw_writel(0, uap->port.membase + UART01x_ECR); + + if (rsr & UART01x_RSR_BE) { + rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); +@@ -160,7 +159,7 @@ static void pl010_rx_chars(struct uart_a + uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); + + ignore_char: +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + } + spin_unlock(&uap->port.lock); + tty_flip_buffer_push(&uap->port.state->port); +@@ -173,7 +172,7 @@ static void pl010_tx_chars(struct uart_a + int count; + + if (uap->port.x_char) { +- writel(uap->port.x_char, uap->port.membase + UART01x_DR); ++ __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR); + uap->port.icount.tx++; + uap->port.x_char = 0; + return; +@@ -185,7 +184,7 @@ static void pl010_tx_chars(struct uart_a + + count = uap->port.fifosize >> 1; + do { +- writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); ++ __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + uap->port.icount.tx++; + if (uart_circ_empty(xmit)) +@@ -203,9 +202,9 @@ static void pl010_modem_status(struct ua + { + unsigned int status, delta; + +- writel(0, uap->port.membase + UART010_ICR); ++ __raw_writel(0, uap->port.membase + UART010_ICR); + +- status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; ++ status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; + + delta = status ^ uap->old_status; + uap->old_status = status; +@@ -233,7 +232,7 @@ static irqreturn_t pl010_int(int irq, vo + + spin_lock(&uap->port.lock); + +- status = readb(uap->port.membase + UART010_IIR); ++ status = __raw_readl(uap->port.membase + UART010_IIR); + if (status) { + do { + if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) +@@ -246,7 +245,7 @@ static irqreturn_t pl010_int(int irq, vo + if (pass_counter-- == 0) + break; + +- status = readb(uap->port.membase + UART010_IIR); ++ status = __raw_readl(uap->port.membase + UART010_IIR); + } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | + UART010_IIR_TIS)); + handled = 1; +@@ -260,7 +259,7 @@ static irqreturn_t pl010_int(int irq, vo + static unsigned int pl010_tx_empty(struct uart_port *port) + { + struct uart_amba_port *uap = (struct uart_amba_port *)port; +- unsigned int status = readb(uap->port.membase + UART01x_FR); ++ unsigned int status = __raw_readl(uap->port.membase + UART01x_FR); + return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; + } + +@@ -270,7 +269,7 @@ static unsigned int pl010_get_mctrl(stru + unsigned int result = 0; + unsigned int status; + +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + if (status & UART01x_FR_DCD) + result |= TIOCM_CAR; + if (status & UART01x_FR_DSR) +@@ -296,12 +295,12 @@ static void pl010_break_ctl(struct uart_ + unsigned int lcr_h; + + spin_lock_irqsave(&uap->port.lock, flags); +- lcr_h = readb(uap->port.membase + UART010_LCRH); ++ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH); + if (break_state == -1) + lcr_h |= UART01x_LCRH_BRK; + else + lcr_h &= ~UART01x_LCRH_BRK; +- writel(lcr_h, uap->port.membase + UART010_LCRH); ++ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH); + spin_unlock_irqrestore(&uap->port.lock, flags); + } + +@@ -329,12 +328,12 @@ static int pl010_startup(struct uart_por + /* + * initialise the old status of the modem signals + */ +- uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; ++ uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; + + /* + * Finally, enable interrupts + */ +- writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, ++ __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, + uap->port.membase + UART010_CR); + + return 0; +@@ -357,10 +356,10 @@ static void pl010_shutdown(struct uart_p + /* + * disable all interrupts, disable the port + */ +- writel(0, uap->port.membase + UART010_CR); ++ __raw_writel(0, uap->port.membase + UART010_CR); + + /* disable break condition and fifos */ +- writel(readb(uap->port.membase + UART010_LCRH) & ++ __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) & + ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), + uap->port.membase + UART010_LCRH); + +@@ -382,7 +381,7 @@ pl010_set_termios(struct uart_port *port + /* + * Ask the core to calculate the divisor for us. + */ +- baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); ++ baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); + quot = uart_get_divisor(port, baud); + + switch (termios->c_cflag & CSIZE) { +@@ -445,25 +444,25 @@ pl010_set_termios(struct uart_port *port + uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; + + /* first, disable everything */ +- old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; ++ old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; + + if (UART_ENABLE_MS(port, termios->c_cflag)) + old_cr |= UART010_CR_MSIE; + +- writel(0, uap->port.membase + UART010_CR); ++ __raw_writel(0, uap->port.membase + UART010_CR); + + /* Set baud rate */ + quot -= 1; +- writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); +- writel(quot & 0xff, uap->port.membase + UART010_LCRL); ++ __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); ++ __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL); + + /* + * ----------v----------v----------v----------v----- + * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L + * ----------^----------^----------^----------^----- + */ +- writel(lcr_h, uap->port.membase + UART010_LCRH); +- writel(old_cr, uap->port.membase + UART010_CR); ++ __raw_writel(lcr_h, uap->port.membase + UART010_LCRH); ++ __raw_writel(old_cr, uap->port.membase + UART010_CR); + + spin_unlock_irqrestore(&uap->port.lock, flags); + } +@@ -545,7 +544,7 @@ static struct uart_ops amba_pl010_pops = + .verify_port = pl010_verify_port, + }; + +-static struct uart_amba_port *amba_ports[UART_NR]; ++static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR]; + + #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE + +@@ -555,10 +554,10 @@ static void pl010_console_putchar(struct + unsigned int status; + + do { +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + barrier(); + } while (!UART_TX_READY(status)); +- writel(ch, uap->port.membase + UART01x_DR); ++ __raw_writel(ch, uap->port.membase + UART01x_DR); + } + + static void +@@ -572,8 +571,8 @@ pl010_console_write(struct console *co, + /* + * First save the CR then disable the interrupts + */ +- old_cr = readb(uap->port.membase + UART010_CR); +- writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); ++ old_cr = __raw_readl(uap->port.membase + UART010_CR); ++ __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); + + uart_console_write(&uap->port, s, count, pl010_console_putchar); + +@@ -582,10 +581,10 @@ pl010_console_write(struct console *co, + * and restore the TCR + */ + do { +- status = readb(uap->port.membase + UART01x_FR); ++ status = __raw_readl(uap->port.membase + UART01x_FR); + barrier(); + } while (status & UART01x_FR_BUSY); +- writel(old_cr, uap->port.membase + UART010_CR); ++ __raw_writel(old_cr, uap->port.membase + UART010_CR); + + clk_disable(uap->clk); + } +@@ -594,9 +593,9 @@ static void __init + pl010_console_get_options(struct uart_amba_port *uap, int *baud, + int *parity, int *bits) + { +- if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { ++ if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { + unsigned int lcr_h, quot; +- lcr_h = readb(uap->port.membase + UART010_LCRH); ++ lcr_h = __raw_readl(uap->port.membase + UART010_LCRH); + + *parity = 'n'; + if (lcr_h & UART01x_LCRH_PEN) { +@@ -611,8 +610,8 @@ pl010_console_get_options(struct uart_am + else + *bits = 8; + +- quot = readb(uap->port.membase + UART010_LCRL) | +- readb(uap->port.membase + UART010_LCRM) << 8; ++ quot = __raw_readl(uap->port.membase + UART010_LCRL) | ++ __raw_readl(uap->port.membase + UART010_LCRM) << 8; + *baud = uap->port.uartclk / (16 * (quot + 1)); + } + } +@@ -631,7 +630,7 @@ static int __init pl010_console_setup(st + * if so, search for the first available port that does have + * console support. + */ +- if (co->index >= UART_NR) ++ if (co->index >= SERIAL_AMBA_NR) + co->index = 0; + uap = amba_ports[co->index]; + if (!uap) +@@ -653,7 +652,7 @@ static int __init pl010_console_setup(st + + static struct uart_driver amba_reg; + static struct console amba_console = { +- .name = "ttyAM", ++ .name = SERIAL_AMBA_NAME, + .write = pl010_console_write, + .device = uart_console_device, + .setup = pl010_console_setup, +@@ -669,11 +668,11 @@ static struct console amba_console = { + + static struct uart_driver amba_reg = { + .owner = THIS_MODULE, +- .driver_name = "ttyAM", +- .dev_name = "ttyAM", ++ .driver_name = SERIAL_AMBA_NAME, ++ .dev_name = SERIAL_AMBA_NAME, + .major = SERIAL_AMBA_MAJOR, + .minor = SERIAL_AMBA_MINOR, +- .nr = UART_NR, ++ .nr = SERIAL_AMBA_NR, + .cons = AMBA_CONSOLE, + }; + +--- a/drivers/tty/serial/Kconfig ++++ b/drivers/tty/serial/Kconfig +@@ -25,10 +25,25 @@ config SERIAL_AMBA_PL010 + help + This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have + an Integrator/AP or Integrator/PP2 platform, or if you have a +- Cirrus Logic EP93xx CPU, say Y or M here. ++ Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here. + + If unsure, say N. + ++config SERIAL_AMBA_PL010_NUMPORTS ++ int "Maximum number of AMBA PL010 serial ports" ++ depends on SERIAL_AMBA_PL010 ++ default "8" ++ ---help--- ++ Set this to the number of serial ports you want the AMBA PL010 driver ++ to support. ++ ++config SERIAL_AMBA_PL010_PORTNAME ++ string "Name of the AMBA PL010 serial ports" ++ depends on SERIAL_AMBA_PL010 ++ default "ttyAM" ++ ---help--- ++ ::: To be written ::: ++ + config SERIAL_AMBA_PL010_CONSOLE + bool "Support for console on AMBA serial port" + depends on SERIAL_AMBA_PL010=y diff --git a/target/linux/adm8668/patches-3.18/201-amba_bus_hacks.patch b/target/linux/adm8668/patches-3.18/201-amba_bus_hacks.patch new file mode 100644 index 0000000..c79721a --- /dev/null +++ b/target/linux/adm8668/patches-3.18/201-amba_bus_hacks.patch @@ -0,0 +1,13 @@ +--- a/drivers/amba/bus.c ++++ b/drivers/amba/bus.c +@@ -21,6 +21,10 @@ + + #include + ++#ifndef NO_IRQ ++#define NO_IRQ (-1) ++#endif ++ + #define to_amba_driver(d) container_of(d, struct amba_driver, drv) + + static const struct amba_id * diff --git a/target/linux/adm8668/profiles/100-WRTU54G-TM.mk b/target/linux/adm8668/profiles/100-WRTU54G-TM.mk new file mode 100644 index 0000000..3ff0307 --- /dev/null +++ b/target/linux/adm8668/profiles/100-WRTU54G-TM.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WRTU54G-TM + NAME:=Linksys WRTU54G T-Mobile (Default) + PACKAGES:=kmod-rt61-pci kmod-usb2 wpad-mini +endef + +define Profile/WRTU54G-TM/Description + Package set compatible with the Linksys WRTU54G T-Mobile +endef +$(eval $(call Profile,WRTU54G-TM)) + diff --git a/target/linux/ar7/Makefile b/target/linux/ar7/Makefile new file mode 100644 index 0000000..1832e7b --- /dev/null +++ b/target/linux/ar7/Makefile @@ -0,0 +1,26 @@ +# +# Copyright (C) 2006-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mipsel +BOARD:=ar7 +BOARDNAME:=TI AR7 +FEATURES:=squashfs atm low_mem +MAINTAINER:=Florian Fainelli +SUBTARGETS:=generic ac49x + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES+= swconfig + +define Target/Description + Build firmware images for TI AR7 based routers. +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/ar7/ac49x/config-default b/target/linux/ar7/ac49x/config-default new file mode 100644 index 0000000..d56df86 --- /dev/null +++ b/target/linux/ar7/ac49x/config-default @@ -0,0 +1,4 @@ +CONFIG_AR7_AC49X=y +CONFIG_AR7_TYPE_AC49X=y +# CONFIG_AR7_TYPE_TI is not set +CONFIG_MTD_AC49X_PARTS=y diff --git a/target/linux/ar7/ac49x/profiles/210-None.mk b/target/linux/ar7/ac49x/profiles/210-None.mk new file mode 100644 index 0000000..2fcfacd --- /dev/null +++ b/target/linux/ar7/ac49x/profiles/210-None.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/None + NAME:=No WiFi + PACKAGES:= +endef + +define Profile/None/Description + Package set without WiFi support +endef +$(eval $(call Profile,None)) + diff --git a/target/linux/ar7/ac49x/target.mk b/target/linux/ar7/ac49x/target.mk new file mode 100644 index 0000000..47f3ab2 --- /dev/null +++ b/target/linux/ar7/ac49x/target.mk @@ -0,0 +1,10 @@ +# +# Copyright (C) 2012 OpenWrt.org +# + +SUBTARGET:=ac49x +BOARDNAME:=AudioCodes AC49x + +define Target/Description + Build firmware images for AudioCodes AC49x based routers. +endef diff --git a/target/linux/ar7/base-files.mk b/target/linux/ar7/base-files.mk new file mode 100644 index 0000000..f21a604 --- /dev/null +++ b/target/linux/ar7/base-files.mk @@ -0,0 +1,11 @@ +define Build/Compile + $(call Build/Compile/Default) + $(TARGET_CC) -o $(PKG_BUILD_DIR)/adam2patcher $(PLATFORM_DIR)/src/adam2patcher.c +endef + +define Package/base-files/install-target + mkdir -p $(1)/sbin + $(CP) $(PKG_BUILD_DIR)/adam2patcher $(1)/sbin +endef + + diff --git a/target/linux/ar7/base-files/etc/config/network b/target/linux/ar7/base-files/etc/config/network new file mode 100644 index 0000000..968d955 --- /dev/null +++ b/target/linux/ar7/base-files/etc/config/network @@ -0,0 +1,50 @@ +# Copyright (C) 2006 OpenWrt.org + +config interface loopback + option ifname lo + option proto static + option ipaddr 127.0.0.1 + option netmask 255.0.0.0 + +config interface lan + option type bridge + option ifname "eth0 eth1 eth0.1 eth0.2" + option proto static + option ipaddr 192.168.1.1 + option netmask 255.255.255.0 + option nat 1 + option ip6assign 60 + +config interface wan6 + option ifname @wan + option proto dhcpv6 + +config globals globals + option ula_prefix auto + +## Example for ATM bridging. +## Useful for PPPoE or IP over ATM. Will create 'nas${unit}' +# +# config atm-bridge +# option unit 0 +# option encaps llc +# option vpi 8 +# option vci 35 +# option payload bridged # some ISPs need this set to 'routed' + + +# config interface wan +## PPPoE: +# option ifname nas0 +# option proto pppoe + +## PPPoA: +# option ifname atm0 +# option proto pppoa +# option encaps llc +# option vpi 8 +# option vci 35 + +## Both: +# option username "my_username" +# option password "my_password" diff --git a/target/linux/ar7/base-files/etc/diag.sh b/target/linux/ar7/base-files/etc/diag.sh new file mode 100644 index 0000000..f6548e8 --- /dev/null +++ b/target/linux/ar7/base-files/etc/diag.sh @@ -0,0 +1,45 @@ +#!/bin/sh +# Copyright (C) 2007-2013 OpenWrt.org + +# This setup gives us 4.5 distinguishable states: +# +# (1-LED) Solid OFF: Bootloader running, or kernel hung (timer task stalled) +# (1-LED) Solid ON: Kernel hung (timer task stalled) +# (2-LED) Solid RED: Bootloader running, or kernel hung (timer task stalled) +# (2-LED) Solid YELLOW: Kernel hung (timer task stalled) +# 5Hz blink: preinit +# 10Hz blink: failsafe +# (1-LED) Heartbeat: normal operation +# (2-LED) Solid GREEN: normal operation + +. /lib/functions/leds.sh + +get_status_led() { + [ -d "/sys/class/leds/status" ] && status_led="status" + [ -d "/sys/class/leds/power:green" ] && status_led="power:green" +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_set_timer 100 100 + ;; + failsafe) + status_led_set_timer 50 50 + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + [ "$status_led" = "status" ] && { + status_led_set_heartbeat + } + [ "$status_led" = "power:green" ] && { + status_led_set_on + led_off "power:red" + } + ;; + esac +} diff --git a/target/linux/ar7/base-files/etc/init.d/adam2 b/target/linux/ar7/base-files/etc/init.d/adam2 new file mode 100755 index 0000000..6b78627 --- /dev/null +++ b/target/linux/ar7/base-files/etc/init.d/adam2 @@ -0,0 +1,13 @@ +#!/bin/sh /etc/rc.common +# ADAM2 patcher for Netgear DG834 and compatible +# Copyright (C) 2006 OpenWrt.org + +START=00 +start() { + MD5="$(md5sum /dev/mtdblock0 | awk '{print $1}')" + [ "$MD5" = "0530bfdf00ec155f4182afd70da028c1" ] && { + mtd unlock adam2 + /sbin/adam2patcher /dev/mtdblock0 + } + rm -f /etc/rc.d/S${START}adam2 /etc/init.d/adam2 /sbin/adam2patcher >&- 2>&- +} diff --git a/target/linux/ar7/base-files/etc/uci-defaults/02_network b/target/linux/ar7/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..2d35c56 --- /dev/null +++ b/target/linux/ar7/base-files/etc/uci-defaults/02_network @@ -0,0 +1,30 @@ +#!/bin/sh +if [ -e "/sys/bus/mdio_bus/drivers/IC+ IP175A/1:00" -o \ + -e "/sys/bus/mdio_bus/drivers/IC+ IP17xx/1:00" ] && \ + [ -x /sbin/swconfig ]; +then + uci batch < + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRVNAME "ar7_gpio" +#define LONGNAME "TI AR7 GPIOs Driver" + +MODULE_AUTHOR("Nicolas Thill "); +MODULE_DESCRIPTION(LONGNAME); +MODULE_LICENSE("GPL"); + +static int ar7_gpio_major; + +static ssize_t ar7_gpio_write(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + int pin = iminor(file->f_path.dentry->d_inode); + size_t i; + + for (i = 0; i < len; ++i) { + char c; + if (get_user(c, buf + i)) + return -EFAULT; + switch (c) { + case '0': + gpio_set_value(pin, 0); + break; + case '1': + gpio_set_value(pin, 1); + break; + case 'd': + case 'D': + ar7_gpio_disable(pin); + break; + case 'e': + case 'E': + ar7_gpio_enable(pin); + break; + case 'i': + case 'I': + case '<': + gpio_direction_input(pin); + break; + case 'o': + case 'O': + case '>': + gpio_direction_output(pin, 0); + break; + default: + return -EINVAL; + } + } + + return len; +} + +static ssize_t ar7_gpio_read(struct file *file, char __user *buf, + size_t len, loff_t *ppos) +{ + int pin = iminor(file->f_path.dentry->d_inode); + int value; + + value = gpio_get_value(pin); + if (put_user(value ? '1' : '0', buf)) + return -EFAULT; + + return 1; +} + +static int ar7_gpio_open(struct inode *inode, struct file *file) +{ + int m = iminor(inode); + + if (m >= (ar7_is_titan() ? TITAN_GPIO_MAX : AR7_GPIO_MAX)) + return -EINVAL; + + return nonseekable_open(inode, file); +} + +static int ar7_gpio_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations ar7_gpio_fops = { + .owner = THIS_MODULE, + .write = ar7_gpio_write, + .read = ar7_gpio_read, + .open = ar7_gpio_open, + .release = ar7_gpio_release, + .llseek = no_llseek, +}; + +static struct platform_device *ar7_gpio_device; + +static int __init ar7_gpio_char_init(void) +{ + int rc; + + ar7_gpio_device = platform_device_alloc(DRVNAME, -1); + if (!ar7_gpio_device) + return -ENOMEM; + + rc = platform_device_add(ar7_gpio_device); + if (rc < 0) + goto out_put; + + rc = register_chrdev(ar7_gpio_major, DRVNAME, &ar7_gpio_fops); + if (rc < 0) + goto out_put; + + ar7_gpio_major = rc; + + rc = 0; + + goto out; + +out_put: + platform_device_put(ar7_gpio_device); +out: + return rc; +} + +static void __exit ar7_gpio_char_exit(void) +{ + unregister_chrdev(ar7_gpio_major, DRVNAME); + platform_device_unregister(ar7_gpio_device); +} + +module_init(ar7_gpio_char_init); +module_exit(ar7_gpio_char_exit); diff --git a/target/linux/ar7/files/drivers/mtd/ac49xpart.c b/target/linux/ar7/files/drivers/mtd/ac49xpart.c new file mode 100644 index 0000000..7ac4a81 --- /dev/null +++ b/target/linux/ar7/files/drivers/mtd/ac49xpart.c @@ -0,0 +1,221 @@ +/* + * AudioCodes AC49x PSPBoot-based flash partition table + * Copyright 2012 Daniel Golle + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#define AC49X_MAXENVPARTS 8 + +#define AC49X_PARTTYPE_LOADER 0 +#define AC49X_PARTTYPE_BOOTENV 1 +#define AC49X_PARTTYPE_LINUX 2 +#define AC49X_PARTTYPE_ROOTFS 3 +#define AC49X_PARTTYPE_UNKNOWN 4 +#define AC49X_NUM_PARTTYPES 5 + +#define AC49X_FLASH_ADDRMASK 0x00FFFFFF + +#define AC49X_LOADER_MAGIC 0x40809000 +#define AC49X_LINUX_MAGIC 0x464c457f /* ELF */ +#define AC49X_BOOTENV_MAGIC 0x4578614d /* MaxE */ + +#define ROOTFS_MIN_OFFSET 0xC0000 + +int parse_partvar(const unsigned char *partvar, struct mtd_partition *part) +{ + unsigned int partstart, partend; + unsigned int pnum; + + pnum = sscanf(partvar, "0x%x,0x%x", &partstart, &partend); + if (pnum != 2) + return 1; + + part->offset = partstart & AC49X_FLASH_ADDRMASK; + part->size = partend - partstart; + + return 0; +} + +int detect_parttype(struct mtd_info *master, struct mtd_partition part) +{ + unsigned int magic; + size_t len; + + if (part.size < 4) + return -1; + + mtd_read(master, part.offset, sizeof(magic), &len, + (uint8_t *)&magic); + + if (len != sizeof(magic)) + return -1; + + switch (magic) { + case AC49X_LOADER_MAGIC: + return AC49X_PARTTYPE_LOADER; + case AC49X_LINUX_MAGIC: + return AC49X_PARTTYPE_LINUX; + case SQUASHFS_MAGIC: + case CRAMFS_MAGIC: + case CRAMFS_MAGIC_WEND: + return AC49X_PARTTYPE_ROOTFS; + case AC49X_BOOTENV_MAGIC: + return AC49X_PARTTYPE_BOOTENV; + default: + switch (magic & 0xFF) { + case JFFS2_SUPER_MAGIC: + return AC49X_PARTTYPE_ROOTFS; + } + switch (magic >> 8) { + case JFFS2_SUPER_MAGIC: + return AC49X_PARTTYPE_ROOTFS; + } + return AC49X_PARTTYPE_UNKNOWN; + } +} + +const char *partnames[] = { + "loader", + "config", + "linux", + "rootfs", + "data" +}; + +void gen_partname(unsigned int type, + unsigned int *typenumeration, + struct mtd_partition *part) +{ + char *s = kzalloc(sizeof(char) * 8, GFP_KERNEL); + + (typenumeration[type])++; + if (typenumeration[type] == 1) + sprintf(s, "%s", partnames[type]); + else + sprintf(s, "%s%d", partnames[type], typenumeration[type]); + + part->name = s; +} + +static int create_mtd_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + unsigned int envpartnum = 0, linuxpartnum = 0; + unsigned int typenumeration[5] = { 0, 0, 0, 0, 0 }; + unsigned char evn[5]; + const unsigned char *partvar = NULL; + + struct mtd_partition *ac49x_parts; + + ac49x_parts = kzalloc(sizeof(*ac49x_parts) * AC49X_MAXENVPARTS, + GFP_KERNEL); + + if (!ac49x_parts) + return -ENOMEM; + + linuxpartnum = 0; + for (envpartnum = 0; envpartnum < AC49X_MAXENVPARTS; envpartnum++) { + struct mtd_partition parsepart; + unsigned int offset, size, type; + int err; + sprintf(evn, "mtd%d", envpartnum); + partvar = prom_getenv(evn); + if (!partvar) + continue; + err = parse_partvar(partvar, &parsepart); + if (err) + continue; + offset = parsepart.offset; + size = parsepart.size; + type = detect_parttype(master, parsepart); + gen_partname(type, typenumeration, &parsepart); + /* protect loader */ + if (type == AC49X_PARTTYPE_LOADER) + parsepart.mask_flags = MTD_WRITEABLE; + else + parsepart.mask_flags = 0; + + memcpy(&(ac49x_parts[linuxpartnum]), &parsepart, + sizeof(struct mtd_partition)); + + /* scan for contained rootfs */ + if (type == AC49X_PARTTYPE_LINUX) { + parsepart.offset += ROOTFS_MIN_OFFSET & + ~(master->erasesize - 1); + parsepart.size -= ROOTFS_MIN_OFFSET & + ~(master->erasesize - 1); + do { + unsigned int size, offset; + size = parsepart.size; + offset = parsepart.offset; + + type = detect_parttype(master, parsepart); + if (type == AC49X_PARTTYPE_ROOTFS) { + gen_partname(type, typenumeration, + &parsepart); + printk(KERN_INFO + "%s %s: 0x%08x@0x%08x\n", + "detected sub-partition", + parsepart.name, + (unsigned int)parsepart.size, + (unsigned int)parsepart.offset); + linuxpartnum++; + memcpy(&(ac49x_parts[linuxpartnum]), + &parsepart, + sizeof(struct mtd_partition)); + break; + } + parsepart.offset += master->erasesize; + parsepart.size -= master->erasesize; + } while (parsepart.size >= master->erasesize); + } + linuxpartnum++; + } + + *pparts = ac49x_parts; + return linuxpartnum; +} + +static struct mtd_part_parser ac49x_parser = { + .owner = THIS_MODULE, + .parse_fn = create_mtd_partitions, + .name = "ac49xpart", +}; + +static int __init ac49x_parser_init(void) +{ + register_mtd_parser(&ac49x_parser); + return 0; +} + +module_init(ac49x_parser_init); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Daniel Golle "); +MODULE_DESCRIPTION("MTD partitioning for AudioCodes AC49x"); diff --git a/target/linux/ar7/files/drivers/mtd/titanpart.c b/target/linux/ar7/files/drivers/mtd/titanpart.c new file mode 100644 index 0000000..a6403f6 --- /dev/null +++ b/target/linux/ar7/files/drivers/mtd/titanpart.c @@ -0,0 +1,234 @@ +#include +#include + +#include +#include +#include +#include +#include + +#define IMAGE_A_SIZE 0X3c0000 +#define WRTP_PARTS 14 +#define NSP_IMG_MAGIC_NUMBER le32_to_cpu(0x4D544443) +#define NSP_IMG_SECTION_TYPE_KERNEL (0x01) +#define NSP_IMG_SECTION_TYPE_FILESYSTEM_ROOT (0x02) +#define NSP_IMG_SECTION_TYPE_FILESYSTEM (0x03) +#define MAX_NUM_PARTITIONS 14 + +static int part_count=0; +static struct mtd_partition titan_parts[WRTP_PARTS]; + + +struct nsp_img_hdr_head +{ + unsigned int magic; /* Magic number to identify this image header */ + unsigned int boot_offset; /* Offset from start of header to kernel code. */ + unsigned int flags; /* Image flags. */ + unsigned int hdr_version; /* Version of this header. */ + unsigned int hdr_size; /* The complete size of all portions of the header */ + unsigned int prod_id; /* This product id */ + unsigned int rel_id; /* Which release this is */ + unsigned int version; /* name-MMM.nnn.ooo-rxx => 0xMMnnooxx. See comment + below */ + unsigned int image_size; /* Image size (including header) */ + unsigned int info_offset; /* Offset from start of header to info block */ + unsigned int sect_info_offset; /* Offset from start of header to section desc */ + unsigned int chksum_offset; /* Offset from start of header to chksum block */ + unsigned int pad1; +}; + +struct nsp_img_hdr_section_info +{ + unsigned int num_sects; /* Number of section (and section desc blocks) in this image */ + unsigned int sect_size; /* Size of a SINGLE section_desc block */ + unsigned int sections_offset; /* Offset to from start of header to the start of the section blocks */ +}; + +/* There will be one of more of the following stuctures in the image header. Each + section will have one of these blocks. */ +struct nsp_img_hdr_sections +{ + unsigned int offset; /* Offset of section from start of NSP_IMG_HDR_HEAD */ + unsigned int total_size; /* Size of section (including pad size.) */ + unsigned int raw_size; /* Size of section only */ + unsigned int flags; /* Section flags */ + unsigned int chksum; /* Section checksum */ + unsigned int type; /* Section type. What kind of info does this section describe */ + char name[16]; /* Reference name for this section. */ +}; + + + + + +static int titan_parse_env_address(char *env_name, unsigned int *flash_base, + unsigned int *flash_end) +{ + char image_name[30]; + char *env_ptr; + char *base_ptr; + char *end_ptr; + char * string_ptr; + /* Get the image variable */ + env_ptr = prom_getenv(env_name); + if(!env_ptr){ + printk("titan: invalid env name, %s.\n", env_name); + return -1; /* Error, no image variable */ + } + strncpy(image_name, env_ptr, 30); + image_name[29]=0; + string_ptr = image_name; + /* Extract the start and stop addresses of the partition */ + base_ptr = strsep(&string_ptr, ","); + end_ptr = strsep(&string_ptr, ","); + if ((base_ptr == NULL) || (end_ptr == NULL)) { + printk("titan: Couldn't tokenize %s start,end.\n", image_name); + return -1; + } + + *flash_base = (unsigned int) simple_strtol(base_ptr, NULL, 0); + *flash_end = (unsigned int) simple_strtol(end_ptr, NULL, 0); + if((!*flash_base) || (!*flash_end)) { + printk("titan: Unable to convert :%s: :%s: into start,end values.\n", + env_name, image_name); + return -1; + } + *flash_base &= 0x0fffffff; + *flash_end &= 0x0fffffff; + return 0; +} + + + +static int titan_get_single_image(char *bootcfg_name, unsigned int *flash_base, + unsigned int *flash_end) +{ + char *env_ptr; + char *base_ptr; + char *end_ptr; + char image_name[30]; + char * string_ptr; + + if(!bootcfg_name || !flash_base || !flash_end) + return -1; + + env_ptr = prom_getenv(bootcfg_name); + if(!env_ptr){ + printk("titan: %s variable not found.\n", bootcfg_name); + return -1; /* Error, no bootcfg variable */ + } + + string_ptr = image_name; + /* Save off the image name */ + strncpy(image_name, env_ptr, 30); + image_name[29]=0; + + end_ptr=strsep(&string_ptr, "\""); + base_ptr=strsep(&string_ptr, "\""); /* Loose the last " */ + if(!end_ptr || !base_ptr){ + printk("titan: invalid bootcfg format, %s.\n", image_name); + return -1; /* Error, invalid bootcfg variable */ + } + + /* Now, parse the addresses */ + return titan_parse_env_address(base_ptr, flash_base, flash_end); +} + + + +static void titan_add_partition(char * env_name, unsigned int flash_base, unsigned int flash_end) +{ + titan_parts[part_count].name = env_name; + titan_parts[part_count].offset = flash_base; + titan_parts[part_count].size = flash_end-flash_base; + titan_parts[part_count].mask_flags = (strcmp(env_name, "bootloader")==0|| + strcmp(env_name, "boot_env")==0 || + strcmp(env_name, "full_image")==0 )?MTD_WRITEABLE:0; + part_count++; + +} +int create_titan_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + unsigned long origin) +{ + struct nsp_img_hdr_head hdr; + struct nsp_img_hdr_section_info sect_info; + struct nsp_img_hdr_sections section; + unsigned int flash_base, flash_end; + unsigned int start, end; + char *name; + int i; + int total_sects=0; + size_t len; + + /* Get the bootcfg env variable first */ + if(titan_get_single_image("BOOTCFG", &flash_base, &flash_end)) { + /* Error, fallback */ + return -1; + } + + /* Get access to the header, and do some validation checks */ + //hdr=(struct nsp_img_hdr_head*)flash_base; + mtd_read(master, flash_base, sizeof(struct nsp_img_hdr_head), &len, (uint8_t *)&hdr); + if(hdr.magic != NSP_IMG_MAGIC_NUMBER) + return -1; /* Not a single image */ + + mtd_read(master, flash_base + hdr.sect_info_offset, sizeof(struct nsp_img_hdr_section_info), &len, (uint8_t *)§_info); + + /* Look for the root fs, and add it first. This way we KNOW where the rootfs is */ + for(i=0; i< sect_info.num_sects && isize); + total_sects++; + + if (!titan_parse_env_address("BOOTLOADER", &start, &end)){ + titan_add_partition("bootloader", start, end); + total_sects++; + } + if (!titan_parse_env_address("boot_env", &start, &end)){ + titan_add_partition("boot_env", start, end); + total_sects++; + } + *pparts = titan_parts; + return total_sects; +} diff --git a/target/linux/ar7/generic/config-default b/target/linux/ar7/generic/config-default new file mode 100644 index 0000000..10d46e9 --- /dev/null +++ b/target/linux/ar7/generic/config-default @@ -0,0 +1,5 @@ +CONFIG_AR7_TI=y +# CONFIG_AR7_TYPE_AC49X is not set +CONFIG_AR7_TYPE_TI=y +# CONFIG_MTD_AC49X_PARTS is not set +CONFIG_MTD_AR7_PARTS=y diff --git a/target/linux/ar7/generic/profiles/100-Annex-A.mk b/target/linux/ar7/generic/profiles/100-Annex-A.mk new file mode 100644 index 0000000..d8e549e --- /dev/null +++ b/target/linux/ar7/generic/profiles/100-Annex-A.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Annex-A + NAME:=Annex-A DSL firmware (default) + PACKAGES:=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl \ + kmod-sangam-atm-annex-a +endef + +define Profile/Annex-A/Description + Package set compatible with Annex-A DSL lines (most countries). +endef +$(eval $(call Profile,Annex-A)) + diff --git a/target/linux/ar7/generic/profiles/110-Annex-B.mk b/target/linux/ar7/generic/profiles/110-Annex-B.mk new file mode 100644 index 0000000..55de1fc --- /dev/null +++ b/target/linux/ar7/generic/profiles/110-Annex-B.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Annex-B + NAME:=Annex-B DSL firmware + PACKAGES:=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl \ + kmod-sangam-atm-annex-b +endef + +define Profile/Annex-B/Description + Package set compatible with Annex-B DSL lines (Germany). +endef +$(eval $(call Profile,Annex-B)) + diff --git a/target/linux/ar7/generic/profiles/200-Texas.mk b/target/linux/ar7/generic/profiles/200-Texas.mk new file mode 100644 index 0000000..7d868bd --- /dev/null +++ b/target/linux/ar7/generic/profiles/200-Texas.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2006-2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Texas + NAME:=Texas Instruments WiFi (mac80211) + PACKAGES:=kmod-acx-mac80211 +endef + +define Profile/Texas/Description + Package set compatible with hardware using Texas Instruments WiFi cards + using the mac80211 driver. +endef +$(eval $(call Profile,Texas)) + diff --git a/target/linux/ar7/generic/profiles/210-None.mk b/target/linux/ar7/generic/profiles/210-None.mk new file mode 100644 index 0000000..2fcfacd --- /dev/null +++ b/target/linux/ar7/generic/profiles/210-None.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/None + NAME:=No WiFi + PACKAGES:= +endef + +define Profile/None/Description + Package set without WiFi support +endef +$(eval $(call Profile,None)) + diff --git a/target/linux/ar7/generic/target.mk b/target/linux/ar7/generic/target.mk new file mode 100644 index 0000000..8b5350e --- /dev/null +++ b/target/linux/ar7/generic/target.mk @@ -0,0 +1,12 @@ +# +# Copyright (C) 2012 OpenWrt.org +# + +SUBTARGET:=generic +BOARDNAME:=Texas Instruments AR7 boards + +DEFAULT_PACKAGES+= kmod-mac80211 kmod-acx-mac80211 wpad-mini + +define Target/Description + Build firmware images for TI AR7 based routers. +endef diff --git a/target/linux/ar7/image/Makefile b/target/linux/ar7/image/Makefile new file mode 100644 index 0000000..d20de27 --- /dev/null +++ b/target/linux/ar7/image/Makefile @@ -0,0 +1,137 @@ +# +# Copyright (C) 2006-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +DROP_SECTIONS:=.reginfo .mdebug .comment .note .pdr .options .MIPS.options +OBJCOPY_SREC:=$(TARGET_CROSS)objcopy -S -O srec $(addprefix --remove-section=,$(DROP_SECTIONS)) + +LOADADDR:=0x94600000 +KERNEL_ENTRY:=0x94100000 +RAMSTART:=0x94000000 +RAMSIZE:=0x00100000 + +EVA_LOADADDR := 0x94100000 + +LOADER_MAKEOPTS= \ + KDIR=$(KDIR) \ + LOADADDR=$(LOADADDR) \ + KERNEL_ENTRY=$(KERNEL_ENTRY) \ + RAMSTART=$(RAMSTART) \ + RAMSIZE=$(RAMSIZE) + +CFLAGS := -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic \ + -pipe -mlong-calls -fno-common \ + -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap \ + -DLOADADDR=$(LOADADDR) + +define Build/Clean + $(MAKE) -C $(GENERIC_PLATFORM_DIR)/image/lzma-loader $(LOADER_MAKEOPTS) clean +endef + +define Image/Prepare + cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma + $(STAGING_DIR_HOST)/bin/lzma2eva $(EVA_LOADADDR) 0x$${shell $(TARGET_CROSS)nm $(KDIR)/vmlinux | grep -w kernel_entry | cut -d' ' -f1} $(KDIR)/vmlinux.lzma $(KDIR)/loader.eva + + $(MAKE) -C $(GENERIC_PLATFORM_DIR)/image/lzma-loader \ + $(LOADER_MAKEOPTS) \ + clean compile + $(OBJCOPY_SREC) $(KDIR)/loader.elf $(KDIR)/loader.srec + $(OBJCOPY_SREC) $(KDIR)/vmlinux.elf $(KDIR)/vmlinux.srec + srec2bin $(KDIR)/loader.srec $(KDIR)/loader.bin + srec2bin $(KDIR)/vmlinux.srec $(KDIR)/vmlinux.bin +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(OBJCOPY_SREC) $(KDIR)/vmlinux-initramfs.elf \ + $(KDIR)/vmlinux-initramfs.srec + srec2bin $(KDIR)/vmlinux-initramfs.srec $(KDIR)/vmlinux-initramfs.bin +endif +endef + +define align/jffs2-64k +bs=65536 conv=sync +endef + +define align/jffs2-128k +bs=131072 conv=sync +endef + +define align/squashfs +endef + +define Image/Build/CyberTAN + (dd if=/dev/zero bs=16 count=1; cat $(BIN_DIR)/$(IMG_PREFIX)-$(1).bin) | \ + $(STAGING_DIR_HOST)/bin/addpattern -p $(3) -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(4)-code.bin +endef + +define Image/Build/Titan + $(STAGING_DIR_HOST)/bin/mktitanimg -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(4)-code.bin -i $(KDIR)/loader.bin $(KDIR)/root.$(1) -a 0x10000 0x10000 -h 2 -p 0x4C575943 -s 0x0b010000 + $(STAGING_DIR_HOST)/bin/mktitanimg -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-na-$(4)-code.bin -i $(KDIR)/loader.bin $(KDIR)/root.$(1) -a 0x10000 0x10000 -h 2 -p 0x4D575943 -s 0x0b010000 +endef + +define Image/Build/AudioCodes + ( dd if=$(KDIR)/vmlinux.elf bs=64k conv=sync ; dd if=$(KDIR)/root.$(1) ) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).bin +endef + +#define Image/Build/sErCoMm +# cat sercomm/adam2.bin "$(BIN_DIR)/$(IMG_PREFIX)-$(1).bin" > "$(KDIR)/dgfw.tmp" +# dd if=sercomm/$(2) of="$(KDIR)/dgfw.tmp" bs=$$$$((0x3e0000 - 80)) seek=1 conv=notrunc +# $(STAGING_DIR_HOST)/bin/dgfirmware -f -w "$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(3).img" "$(KDIR)/dgfw.tmp" +# rm -f "$(KDIR)/dgfw.tmp" +#endef + +define Image/Build/EVA + dd if=$(KDIR)/loader.eva $(call align/$(1)) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(KERNEL)-$(1).bin + cat $(KDIR)/root.$(1) >> $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(KERNEL)-$(1).bin + $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(KERNEL)-$(1).bin) +endef + +define Image/Build/Initramfs + $(CP) $(KDIR)/vmlinux-initramfs.bin $(BIN_DIR)/$(IMG_PREFIX)-initramfs.bin +endef + +ifeq ($(CONFIG_AR7_TI),y) +define Image/Build + dd if=$(KDIR)/loader.bin $(call align/$(1)) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).bin + cat $(KDIR)/root.$(1) >> $(BIN_DIR)/$(IMG_PREFIX)-$(1).bin + $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1).bin) + $(call Image/Build/CyberTAN,$(1),AG1B,AG1B,$(1)) + $(call Image/Build/CyberTAN,$(1),AG1A,AG1A,$(1)) + $(call Image/Build/CyberTAN,$(1),WA21,WA21,$(1)) + $(call Image/Build/CyberTAN,$(1),WA22,WA22,$(1)) + $(call Image/Build/CyberTAN,$(1),WAG2,WAG2,$(1)) + $(call Image/Build/CyberTAN,$(1),AG310,AV2A -b -r 1.0,$(1)) + $(call Image/Build/CyberTAN,$(1),AG241v2,AG3A -b -r 2.0,$(1)) + $(call Image/Build/CyberTAN,$(1),AG241v2b,AG3B -b -r 2.0,$(1)) + $(call Image/Build/CyberTAN,$(1),AG241v1,AG3A -b,$(1)) + $(call Image/Build/CyberTAN,$(1),WAG54GP2v1,ATWL -b,$(1)) + $(call Image/Build/CyberTAN,$(1),WAG54GP2v2,CTWL -b,$(1)) + $(call Image/Build/CyberTAN,$(1),WA31,WA31 -b,$(1)) + $(call Image/Build/CyberTAN,$(1),WA32,WA32 -b,$(1)) + $(call Image/Build/CyberTAN,$(1),WA7A,WA7A -b,$(1)) + $(call Image/Build/CyberTAN,$(1),WA7B,WA7B -b,$(1)) +# $(call Image/Build/sErCoMm,$(1),dg834,$(1)) +# $(call Image/Build/sErCoMm,$(1),jdr454wb,$(1)) + $(call Image/Build/EVA,$(1),EVA) + $(call Image/Build/Titan,$(1),Titan,Titan,$(1)) +ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y) + $(call Image/Build/Initramfs) +endif +endef +endif + +ifeq ($(CONFIG_AR7_AC49X),y) +define Image/Build +# $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1).bin) + $(call Image/Build/AudioCodes,$(1),mp202,$(1)) +ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y) + $(call Image/Build/Initramfs) +endif +endef +endif + +$(eval $(call BuildImage)) diff --git a/target/linux/ar7/patches-3.18/001-mips-ar7-fix-serial.patch b/target/linux/ar7/patches-3.18/001-mips-ar7-fix-serial.patch new file mode 100644 index 0000000..6896352 --- /dev/null +++ b/target/linux/ar7/patches-3.18/001-mips-ar7-fix-serial.patch @@ -0,0 +1,23 @@ +From 443ab715a40881d6c9ba11b027ba154bac904cb0 Mon Sep 17 00:00:00 2001 +From: Oswald Buddenhagen +Date: Sat, 10 May 2014 23:19:08 +0200 +Subject: [PATCH] MIPS/AR7: ensure that serial ports are properly set up + +without UPF_FIXED_TYPE, the data from the PORT_AR7 uart_config entry is +never copied, resulting in a dead port. + +Signed-off-by: Oswald Buddenhagen +--- + arch/mips/ar7/platform.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -581,6 +581,7 @@ static int __init ar7_register_uarts(voi + uart_port.type = PORT_AR7; + uart_port.uartclk = clk_get_rate(bus_clk) / 2; + uart_port.iotype = UPIO_MEM32; ++ uart_port.flags = UPF_FIXED_TYPE; + uart_port.regshift = 2; + + uart_port.line = 0; diff --git a/target/linux/ar7/patches-3.18/100-fix-highmem-offset.patch b/target/linux/ar7/patches-3.18/100-fix-highmem-offset.patch new file mode 100644 index 0000000..f1a7549 --- /dev/null +++ b/target/linux/ar7/patches-3.18/100-fix-highmem-offset.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/include/asm/mach-ar7/spaces.h ++++ b/arch/mips/include/asm/mach-ar7/spaces.h +@@ -20,6 +20,8 @@ + #define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */ + #define IO_BASE UNCAC_BASE + ++#define HIGHMEM_START _AC(0x20000000, UL) ++ + #include + + #endif /* __ASM_AR7_SPACES_H */ diff --git a/target/linux/ar7/patches-3.18/110-flash.patch b/target/linux/ar7/patches-3.18/110-flash.patch new file mode 100644 index 0000000..e4aeffd --- /dev/null +++ b/target/linux/ar7/patches-3.18/110-flash.patch @@ -0,0 +1,22 @@ +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -12,7 +12,7 @@ obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o + obj-$(CONFIG_MTD_AFS_PARTS) += afs.o +-obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o ++obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o titanpart.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -199,7 +199,7 @@ static struct resource physmap_flash_res + .name = "mem", + .flags = IORESOURCE_MEM, + .start = 0x10000000, +- .end = 0x107fffff, ++ .end = 0x11ffffff, + }; + + static const char *ar7_probe_types[] = { "ar7part", NULL }; diff --git a/target/linux/ar7/patches-3.18/120-gpio_chrdev.patch b/target/linux/ar7/patches-3.18/120-gpio_chrdev.patch new file mode 100644 index 0000000..beb0052 --- /dev/null +++ b/target/linux/ar7/patches-3.18/120-gpio_chrdev.patch @@ -0,0 +1,28 @@ +--- a/drivers/char/Kconfig ++++ b/drivers/char/Kconfig +@@ -452,6 +452,15 @@ config MWAVE + To compile this driver as a module, choose M here: the + module will be called mwave. + ++config AR7_GPIO ++ tristate "TI AR7 GPIO Support" ++ depends on AR7 ++ help ++ Give userspace access to the GPIO pins on the Texas Instruments AR7 ++ processors. ++ ++ If compiled as a module, it will be called ar7_gpio. ++ + config SCx200_GPIO + tristate "NatSemi SCx200 GPIO Support" + depends on SCx200 +--- a/drivers/char/Makefile ++++ b/drivers/char/Makefile +@@ -42,6 +42,7 @@ obj-$(CONFIG_HW_RANDOM) += hw_random/ + obj-$(CONFIG_PPDEV) += ppdev.o + obj-$(CONFIG_NWBUTTON) += nwbutton.o + obj-$(CONFIG_NWFLASH) += nwflash.o ++obj-$(CONFIG_AR7_GPIO) += ar7_gpio.o + obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o + obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o + obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o diff --git a/target/linux/ar7/patches-3.18/160-vlynq_try_remote_first.patch b/target/linux/ar7/patches-3.18/160-vlynq_try_remote_first.patch new file mode 100644 index 0000000..1d1310d --- /dev/null +++ b/target/linux/ar7/patches-3.18/160-vlynq_try_remote_first.patch @@ -0,0 +1,300 @@ +--- a/drivers/vlynq/vlynq.c ++++ b/drivers/vlynq/vlynq.c +@@ -119,20 +119,40 @@ static int vlynq_linked(struct vlynq_dev + return 0; + } + ++static volatile int vlynq_delay_value_new = 0; ++ ++static void vlynq_delay_wait(u32 count) ++{ ++ /* Code adopted from original vlynq driver */ ++ int i = 0; ++ volatile int *ptr = &vlynq_delay_value_new; ++ *ptr = 0; ++ ++ /* We are assuming that the each cycle takes about ++ * 23 assembly instructions. */ ++ for(i = 0; i < (count + 23)/23; i++) ++ *ptr = *ptr + 1; ++} ++ + static void vlynq_reset(struct vlynq_device *dev) + { ++ u32 rtm = readl(&dev->local->revision); ++ ++ rtm = rtm < 0x00010205 || readl(&dev->local->status) & 0x800 == 0 ? ++ 0 : 0x600000; ++ + writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET, + &dev->local->control); + + /* Wait for the devices to finish resetting */ +- msleep(5); ++ vlynq_delay_wait(0xffffff); + + /* Remove reset bit */ +- writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET, ++ writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET | rtm, + &dev->local->control); + + /* Give some time for the devices to settle */ +- msleep(5); ++ vlynq_delay_wait(0xffffff); + } + + static void vlynq_irq_unmask(struct irq_data *d) +@@ -379,6 +399,61 @@ void vlynq_unregister_driver(struct vlyn + } + EXPORT_SYMBOL(vlynq_unregister_driver); + ++enum vlynq_clk_src { ++ vlynq_clk_external, ++ vlynq_clk_local, ++ vlynq_clk_remote, ++ vlynq_clk_invalid, ++}; ++ ++static int __vlynq_set_clocks(struct vlynq_device *dev, ++ enum vlynq_clk_src clk_dir, ++ int lclk_div, int rclk_div) ++{ ++ u32 reg; ++ ++ if (clk_dir == vlynq_clk_invalid) { ++ printk(KERN_ERR "%s: attempt to set invalid clocking\n", ++ dev_name(&dev->dev)); ++ return -EINVAL; ++ } ++ ++ reg = readl(&dev->local->control); ++ if (readl(&dev->local->revision) < 0x00010205) { ++ if (clk_dir & vlynq_clk_local) ++ reg |= VLYNQ_CTRL_CLOCK_INT; ++ else ++ reg &= ~VLYNQ_CTRL_CLOCK_INT; ++ } ++ reg &= ~VLYNQ_CTRL_CLOCK_MASK; ++ reg |= VLYNQ_CTRL_CLOCK_DIV(lclk_div); ++ writel(reg, &dev->local->control); ++ ++ if (!vlynq_linked(dev)) ++ return -ENODEV; ++ ++ printk(KERN_INFO "%s: local VLYNQ protocol rev. is 0x%08x\n", ++ dev_name(&dev->dev), readl(&dev->local->revision)); ++ printk(KERN_INFO "%s: remote VLYNQ protocol rev. is 0x%08x\n", ++ dev_name(&dev->dev), readl(&dev->remote->revision)); ++ ++ reg = readl(&dev->remote->control); ++ if (readl(&dev->remote->revision) < 0x00010205) { ++ if (clk_dir & vlynq_clk_remote) ++ reg |= VLYNQ_CTRL_CLOCK_INT; ++ else ++ reg &= ~VLYNQ_CTRL_CLOCK_INT; ++ } ++ reg &= ~VLYNQ_CTRL_CLOCK_MASK; ++ reg |= VLYNQ_CTRL_CLOCK_DIV(rclk_div); ++ writel(reg, &dev->remote->control); ++ ++ if (!vlynq_linked(dev)) ++ return -ENODEV; ++ ++ return 0; ++} ++ + /* + * A VLYNQ remote device can clock the VLYNQ bus master + * using a dedicated clock line. In that case, both the +@@ -392,29 +467,16 @@ static int __vlynq_try_remote(struct vly + int i; + + vlynq_reset(dev); +- for (i = dev->dev_id ? vlynq_rdiv2 : vlynq_rdiv8; dev->dev_id ? +- i <= vlynq_rdiv8 : i >= vlynq_rdiv2; +- dev->dev_id ? i++ : i--) { ++ for (i = 0; i <= 7; i++) { + + if (!vlynq_linked(dev)) + break; + +- writel((readl(&dev->remote->control) & +- ~VLYNQ_CTRL_CLOCK_MASK) | +- VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1), +- &dev->remote->control); +- writel((readl(&dev->local->control) +- & ~(VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_MASK)) | +- VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1), +- &dev->local->control); +- +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG +- "%s: using remote clock divisor %d\n", +- dev_name(&dev->dev), i - vlynq_rdiv1 + 1); +- dev->divisor = i; ++ if (!__vlynq_set_clocks(dev, vlynq_clk_remote, i, i)) { ++ printk(KERN_INFO ++ "%s: using remote clock divisor %d\n", ++ dev_name(&dev->dev), i + 1); ++ dev->divisor = i + vlynq_rdiv1; + return 0; + } else { + vlynq_reset(dev); +@@ -433,25 +495,17 @@ static int __vlynq_try_remote(struct vly + */ + static int __vlynq_try_local(struct vlynq_device *dev) + { +- int i; ++ int i, dir = !dev->dev_id; + + vlynq_reset(dev); + +- for (i = dev->dev_id ? vlynq_ldiv2 : vlynq_ldiv8; dev->dev_id ? +- i <= vlynq_ldiv8 : i >= vlynq_ldiv2; +- dev->dev_id ? i++ : i--) { +- +- writel((readl(&dev->local->control) & +- ~VLYNQ_CTRL_CLOCK_MASK) | +- VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_DIV(i - vlynq_ldiv1), +- &dev->local->control); +- +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG +- "%s: using local clock divisor %d\n", +- dev_name(&dev->dev), i - vlynq_ldiv1 + 1); +- dev->divisor = i; ++ for (i = dir ? 7 : 0; dir ? i >= 0 : i <= 7; dir ? i-- : i++) { ++ ++ if (!__vlynq_set_clocks(dev, vlynq_clk_local, i, 0)) { ++ printk(KERN_INFO ++ "%s: using local clock divisor %d\n", ++ dev_name(&dev->dev), i + 1); ++ dev->divisor = i + vlynq_ldiv1; + return 0; + } else { + vlynq_reset(dev); +@@ -473,18 +527,10 @@ static int __vlynq_try_external(struct v + if (!vlynq_linked(dev)) + return -ENODEV; + +- writel((readl(&dev->remote->control) & +- ~VLYNQ_CTRL_CLOCK_INT), +- &dev->remote->control); +- +- writel((readl(&dev->local->control) & +- ~VLYNQ_CTRL_CLOCK_INT), +- &dev->local->control); +- +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG "%s: using external clock\n", +- dev_name(&dev->dev)); +- dev->divisor = vlynq_div_external; ++ if (!__vlynq_set_clocks(dev, vlynq_clk_external, 0, 0)) { ++ printk(KERN_INFO "%s: using external clock\n", ++ dev_name(&dev->dev)); ++ dev->divisor = vlynq_div_external; + return 0; + } + +@@ -501,24 +547,16 @@ static int __vlynq_enable_device(struct + return result; + + switch (dev->divisor) { +- case vlynq_div_external: + case vlynq_div_auto: + /* When the device is brought from reset it should have clock + * generation negotiated by hardware. + * Check which device is generating clocks and perform setup + * accordingly */ +- if (vlynq_linked(dev) && readl(&dev->remote->control) & +- VLYNQ_CTRL_CLOCK_INT) { +- if (!__vlynq_try_remote(dev) || +- !__vlynq_try_local(dev) || +- !__vlynq_try_external(dev)) +- return 0; +- } else { +- if (!__vlynq_try_external(dev) || +- !__vlynq_try_local(dev) || +- !__vlynq_try_remote(dev)) +- return 0; +- } ++ if (!__vlynq_try_remote(dev) || !__vlynq_try_local(dev)) ++ return 0; ++ case vlynq_div_external: ++ if (!__vlynq_try_external(dev)) ++ return 0; + break; + case vlynq_ldiv1: + case vlynq_ldiv2: +@@ -528,15 +566,12 @@ static int __vlynq_enable_device(struct + case vlynq_ldiv6: + case vlynq_ldiv7: + case vlynq_ldiv8: +- writel(VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_DIV(dev->divisor - +- vlynq_ldiv1), &dev->local->control); +- writel(0, &dev->remote->control); +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG +- "%s: using local clock divisor %d\n", +- dev_name(&dev->dev), +- dev->divisor - vlynq_ldiv1 + 1); ++ if (!__vlynq_set_clocks(dev, vlynq_clk_local, dev->divisor - ++ vlynq_ldiv1, 0)) { ++ printk(KERN_INFO ++ "%s: using local clock divisor %d\n", ++ dev_name(&dev->dev), ++ dev->divisor - vlynq_ldiv1 + 1); + return 0; + } + break; +@@ -548,20 +583,17 @@ static int __vlynq_enable_device(struct + case vlynq_rdiv6: + case vlynq_rdiv7: + case vlynq_rdiv8: +- writel(0, &dev->local->control); +- writel(VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_DIV(dev->divisor - +- vlynq_rdiv1), &dev->remote->control); +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG +- "%s: using remote clock divisor %d\n", +- dev_name(&dev->dev), +- dev->divisor - vlynq_rdiv1 + 1); ++ if (!__vlynq_set_clocks(dev, vlynq_clk_remote, 0, ++ dev->divisor - vlynq_rdiv1)) { ++ printk(KERN_INFO ++ "%s: using remote clock divisor %d\n", ++ dev_name(&dev->dev), ++ dev->divisor - vlynq_rdiv1 + 1); + return 0; + } + break; + } +- ++ vlynq_reset(dev); + ops->off(dev); + return -ENODEV; + } +@@ -732,14 +764,14 @@ static int vlynq_probe(struct platform_d + platform_set_drvdata(pdev, dev); + + printk(KERN_INFO "%s: regs 0x%p, irq %d, mem 0x%p\n", +- dev_name(&dev->dev), (void *)dev->regs_start, dev->irq, +- (void *)dev->mem_start); ++ dev_name(&dev->dev), (void *)dev->regs_start, ++ dev->irq, (void *)dev->mem_start); + + dev->dev_id = 0; + dev->divisor = vlynq_div_auto; +- result = __vlynq_enable_device(dev); +- if (result == 0) { ++ if (!__vlynq_enable_device(dev)) { + dev->dev_id = readl(&dev->remote->chip); ++ vlynq_reset(dev); + ((struct plat_vlynq_ops *)(dev->dev.platform_data))->off(dev); + } + if (dev->dev_id) diff --git a/target/linux/ar7/patches-3.18/200-free-mem-below-kernel-offset.patch b/target/linux/ar7/patches-3.18/200-free-mem-below-kernel-offset.patch new file mode 100644 index 0000000..4011942 --- /dev/null +++ b/target/linux/ar7/patches-3.18/200-free-mem-below-kernel-offset.patch @@ -0,0 +1,15 @@ +--- a/arch/mips/ar7/memory.c ++++ b/arch/mips/ar7/memory.c +@@ -66,5 +66,11 @@ void __init prom_meminit(void) + + void __init prom_free_prom_memory(void) + { +- /* Nothing to free */ ++ /* adapted from arch/mips/txx9/generic/setup.c */ ++ unsigned long saddr = PHYS_OFFSET + PAGE_SIZE; ++ unsigned long eaddr = __pa_symbol(&_text); ++ ++ /* free memory between prom-record and kernel _text base */ ++ if (saddr < eaddr) ++ free_init_pages("prom memory", saddr, eaddr); + } diff --git a/target/linux/ar7/patches-3.18/300-add-ac49x-platform.patch b/target/linux/ar7/patches-3.18/300-add-ac49x-platform.patch new file mode 100644 index 0000000..ccdc84d --- /dev/null +++ b/target/linux/ar7/patches-3.18/300-add-ac49x-platform.patch @@ -0,0 +1,85 @@ +--- a/arch/mips/ar7/Platform ++++ b/arch/mips/ar7/Platform +@@ -3,4 +3,9 @@ + # + platform-$(CONFIG_AR7) += ar7/ + cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7 +-load-$(CONFIG_AR7) += 0xffffffff94100000 ++load-$(CONFIG_AR7_TI) += 0xffffffff94100000 ++ ++# ++# AudioCodes AC49x ++# ++load-$(CONFIG_AR7_AC49X) += 0xffffffff945ca000 +--- a/arch/mips/ar7/setup.c ++++ b/arch/mips/ar7/setup.c +@@ -69,6 +69,10 @@ const char *get_system_type(void) + return "TI AR7 (TNETV1056)"; + case TITAN_CHIP_1060: + return "TI AR7 (TNETV1060)"; ++ case TITAN_CHIP_AC495: ++ return "AudioCodes AC495"; ++ case TITAN_CHIP_AC496: ++ return "AudioCodes AC496"; + } + default: + return "TI AR7 (unknown)"; +--- a/arch/mips/include/asm/mach-ar7/ar7.h ++++ b/arch/mips/include/asm/mach-ar7/ar7.h +@@ -92,6 +92,8 @@ + #define TITAN_CHIP_1055 0x0e + #define TITAN_CHIP_1056 0x0d + #define TITAN_CHIP_1060 0x07 ++#define TITAN_CHIP_AC495 0x00 ++#define TITAN_CHIP_AC496 0x02 + + /* Interrupts */ + #define AR7_IRQ_UART0 15 +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -94,7 +94,7 @@ config AR7 + select HAVE_CLK + help + Support for the Texas Instruments AR7 System-on-a-Chip +- family: TNETD7100, 7200 and 7300. ++ family: TI TNETD7100, 7200, 7300 and AudioCodes AC49x. + + config ATH79 + bool "Atheros AR71XX/AR724X/AR913X based boards" +@@ -835,6 +835,7 @@ config MIPS_PARAVIRT + endchoice + + source "arch/mips/alchemy/Kconfig" ++source "arch/mips/ar7/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm47xx/Kconfig" + source "arch/mips/bcm63xx/Kconfig" +--- /dev/null ++++ b/arch/mips/ar7/Kconfig +@@ -0,0 +1,26 @@ ++if AR7 ++ ++config AR7_TI ++ bool ++ ++config AR7_AC49X ++ bool ++ ++choice ++ prompt "AR7 SoC family selection" ++ default AR7_TYPE_TI ++ depends on AR7 ++ help ++ Select AR7 MIPS SoC implementation. ++ ++ config AR7_TYPE_TI ++ bool "Texas Instruments AR7" ++ select AR7_TI ++ ++ config AR7_TYPE_AC49X ++ bool "AudioCodes AC49X" ++ select AR7_AC49X ++ ++endchoice ++ ++endif diff --git a/target/linux/ar7/patches-3.18/310-ac49x-prom-support.patch b/target/linux/ar7/patches-3.18/310-ac49x-prom-support.patch new file mode 100644 index 0000000..dddf221 --- /dev/null +++ b/target/linux/ar7/patches-3.18/310-ac49x-prom-support.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/ar7/prom.c ++++ b/arch/mips/ar7/prom.c +@@ -70,6 +70,7 @@ struct psbl_rec { + }; + + static const char psp_env_version[] __initconst = "TIENV0.8"; ++static const char psp_env_version_ac49x[] __initconst = "MaxENV0.2"; + + struct psp_env_chunk { + u8 num; +@@ -186,7 +187,8 @@ static void __init ar7_init_env(struct e + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300)); + void *psp_env = (void *)KSEG1ADDR(psbl->env_base); + +- if (strcmp(psp_env, psp_env_version) == 0) { ++ if (strcmp(psp_env, psp_env_version) == 0 || ++ strcmp(psp_env, psp_env_version_ac49x) == 0) { + parse_psp_env(psp_env); + } else { + for (i = 0; i < MAX_ENTRY; i++, env++) diff --git a/target/linux/ar7/patches-3.18/320-ac49x-mtd-partitions.patch b/target/linux/ar7/patches-3.18/320-ac49x-mtd-partitions.patch new file mode 100644 index 0000000..53ac072 --- /dev/null +++ b/target/linux/ar7/patches-3.18/320-ac49x-mtd-partitions.patch @@ -0,0 +1,35 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -164,6 +164,11 @@ config MTD_OF_PARTS + the partition map from the children of the flash node, + as described in Documentation/devicetree/booting-without-of.txt. + ++config MTD_AC49X_PARTS ++ tristate "AudioCodes AC49X partitioning support" ++ ---help--- ++ AudioCodes AC49X partitioning support ++ + config MTD_AR7_PARTS + tristate "TI AR7 partitioning support" + ---help--- +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_MTD_SPLIT) += mtdsplit/ + obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o ++obj-$(CONFIG_MTD_AC49X_PARTS) += ac49xpart.o + obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o titanpart.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -202,7 +202,7 @@ static struct resource physmap_flash_res + .end = 0x11ffffff, + }; + +-static const char *ar7_probe_types[] = { "ar7part", NULL }; ++static const char *ar7_probe_types[] = { "ac49xpart", "ar7part", NULL }; + + static struct physmap_flash_data physmap_flash_data = { + .width = 2, diff --git a/target/linux/ar7/patches-3.18/500-serial_kludge.patch b/target/linux/ar7/patches-3.18/500-serial_kludge.patch new file mode 100644 index 0000000..08bd6a6 --- /dev/null +++ b/target/linux/ar7/patches-3.18/500-serial_kludge.patch @@ -0,0 +1,28 @@ +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -329,6 +329,13 @@ static const struct serial8250_config ua + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, + .flags = UART_CAP_FIFO | UART_CAP_AFE, + }, ++ [PORT_AR7] = { ++ .name = "TI-AR7", ++ .fifo_size = 16, ++ .tx_loadsz = 16, ++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, ++ .flags = UART_CAP_FIFO | UART_CAP_AFE, ++ }, + }; + + /* Uart divisor latch read */ +@@ -3174,7 +3181,11 @@ static void serial8250_console_putchar(s + { + struct uart_8250_port *up = up_to_u8250p(port); + ++#ifdef CONFIG_AR7 ++ wait_for_xmitr(up, BOTH_EMPTY); ++#else + wait_for_xmitr(up, UART_LSR_THRE); ++#endif + serial_port_out(port, UART_TX, ch); + } + diff --git a/target/linux/ar7/patches-3.18/920-ar7part.patch b/target/linux/ar7/patches-3.18/920-ar7part.patch new file mode 100644 index 0000000..9948858 --- /dev/null +++ b/target/linux/ar7/patches-3.18/920-ar7part.patch @@ -0,0 +1,118 @@ +--- a/drivers/mtd/ar7part.c ++++ b/drivers/mtd/ar7part.c +@@ -30,11 +30,14 @@ + + #include + ++#include ++ + #define AR7_PARTS 4 + #define ROOT_OFFSET 0xe0000 + + #define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42) + #define LOADER_MAGIC2 le32_to_cpu(0xfeed1281) ++#define LOADER_MAGIC3 le32_to_cpu(0x434d4d4c) + + struct ar7_bin_rec { + unsigned int checksum; +@@ -42,12 +45,16 @@ struct ar7_bin_rec { + unsigned int address; + }; + ++int create_titan_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data); ++ + static int create_mtd_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) + { + struct ar7_bin_rec header; +- unsigned int offset; ++ unsigned int offset, mtd_start, mtd_end; + size_t len; + unsigned int pre_size = master->erasesize, post_size = 0; + unsigned int root_offset = ROOT_OFFSET; +@@ -55,6 +62,16 @@ static int create_mtd_partitions(struct + int retries = 10; + struct mtd_partition *ar7_parts; + ++ const char *prom_str = prom_getenv("ProductID"); ++ char mtd_name[] = "mtd1"; ++ if(prom_str && ++ (strcmp(prom_str, "CYWL")==0 || ++ strcmp(prom_str, "CYWM")==0 || ++ strcmp(prom_str, "CYLM")==0 || ++ strcmp(prom_str, "CYLL")==0)){ ++ return create_titan_partitions(master, pparts, data); ++ } ++ + ar7_parts = kzalloc(sizeof(*ar7_parts) * AR7_PARTS, GFP_KERNEL); + if (!ar7_parts) + return -ENOMEM; +@@ -83,34 +100,39 @@ static int create_mtd_partitions(struct + + pre_size = offset; + +- if (!ar7_parts[1].offset) { +- ar7_parts[1].offset = master->size - master->erasesize; +- post_size = master->erasesize; +- } +- + switch (header.checksum) { +- case LOADER_MAGIC1: +- while (header.length) { +- offset += sizeof(header) + header.length; +- mtd_read(master, offset, sizeof(header), &len, +- (uint8_t *)&header); +- } +- root_offset = offset + sizeof(header) + 4; +- break; + case LOADER_MAGIC2: ++ for (retries = 0; retries <= 9; retries++) { ++ mtd_name[3] = '0' + retries; ++ prom_str = prom_getenv(mtd_name); ++ if (prom_str == NULL) ++ continue; ++ sscanf(prom_str, "%i,%i", &mtd_start, &mtd_end); ++ if (pre_size == (mtd_start & 0x1ffffff)) { ++ ar7_parts[1].offset = mtd_end &= 0x1ffffff; ++ ar7_parts[1].size = post_size = master->size - mtd_end; ++ break; ++ } ++ } ++ case LOADER_MAGIC1: ++ root_offset = (header.checksum == LOADER_MAGIC1) ? 4 : 0; + while (header.length) { + offset += sizeof(header) + header.length; + mtd_read(master, offset, sizeof(header), &len, + (uint8_t *)&header); + } +- root_offset = offset + sizeof(header) + 4 + 0xff; +- root_offset &= ~(uint32_t)0xff; ++ root_offset += offset + sizeof(header); + break; + default: + printk(KERN_WARNING "Unknown magic: %08x\n", header.checksum); + break; + } + ++ if (!ar7_parts[1].offset) { ++ post_size = master->erasesize; ++ ar7_parts[1].offset = master->size - post_size; ++ } ++ + mtd_read(master, root_offset, sizeof(header), &len, (u8 *)&header); + if (header.checksum != SQUASHFS_MAGIC) { + root_offset += master->erasesize - 1; +--- a/drivers/mtd/titanpart.c ++++ b/drivers/mtd/titanpart.c +@@ -149,7 +149,7 @@ static void titan_add_partition(char * e + } + int create_titan_partitions(struct mtd_info *master, + struct mtd_partition **pparts, +- unsigned long origin) ++ struct mtd_part_parser_data *data) + { + struct nsp_img_hdr_head hdr; + struct nsp_img_hdr_section_info sect_info; diff --git a/target/linux/ar7/patches-3.18/925-actiontec_leds.patch b/target/linux/ar7/patches-3.18/925-actiontec_leds.patch new file mode 100644 index 0000000..41af2cb --- /dev/null +++ b/target/linux/ar7/patches-3.18/925-actiontec_leds.patch @@ -0,0 +1,95 @@ +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -465,31 +465,22 @@ static struct gpio_led fb_fon_leds[] = { + }, + }; + +-static struct gpio_led gt701_leds[] = { ++static struct gpio_led actiontec_leds[] = { + { + .name = "inet:green", + .gpio = 13, +- .active_low = 1, +- }, +- { +- .name = "usb", +- .gpio = 12, +- .active_low = 1, + }, + { + .name = "inet:red", + .gpio = 9, +- .active_low = 1, + }, + { +- .name = "power:red", ++ .name = "power:green", + .gpio = 7, +- .active_low = 1, + }, + { +- .name = "power:green", ++ .name = "power:red", + .gpio = 8, +- .active_low = 1, + .default_trigger = "default-on", + }, + { +@@ -497,6 +488,44 @@ static struct gpio_led gt701_leds[] = { + .gpio = 10, + .active_low = 1, + }, ++ { ++ .name = "wifi", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ { ++ .name = "wifi:red", ++ .gpio = 3, ++ }, ++ { ++ .name = "standby", ++ .gpio = 4, ++ }, ++ { ++ .name = "wps", ++ .gpio = 16, ++ .active_low = 1, ++ }, ++ { ++ .name = "usb", ++ .gpio = 12, ++ .active_low = 1, ++ }, ++ { ++ .name = "voip", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ { ++ .name = "line1", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "line2", ++ .gpio = 25, ++ .active_low = 1, ++ }, + }; + + static struct gpio_led_platform_data ar7_led_data; +@@ -540,9 +569,9 @@ static void __init detect_leds(void) + } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) { + ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); + ar7_led_data.leds = titan_leds; +- } else if (strstr(prid, "GT701")) { +- ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds); +- ar7_led_data.leds = gt701_leds; ++ } else if (strstr(prid, "GT7") || strstr(prid, "PK5000")) { ++ ar7_led_data.num_leds = ARRAY_SIZE(actiontec_leds); ++ ar7_led_data.leds = actiontec_leds; + } + } + diff --git a/target/linux/ar7/patches-3.18/950-cpmac_titan.patch b/target/linux/ar7/patches-3.18/950-cpmac_titan.patch new file mode 100644 index 0000000..f1d432c --- /dev/null +++ b/target/linux/ar7/patches-3.18/950-cpmac_titan.patch @@ -0,0 +1,52 @@ +--- a/drivers/net/ethernet/ti/cpmac.c ++++ b/drivers/net/ethernet/ti/cpmac.c +@@ -1146,6 +1146,8 @@ static int cpmac_probe(struct platform_d + goto out; + } + ++ ar7_device_reset(pdata->reset_bit); ++ + dev->irq = platform_get_irq_byname(pdev, "irq"); + + dev->netdev_ops = &cpmac_netdev_ops; +@@ -1227,7 +1229,7 @@ int cpmac_init(void) + cpmac_mii->reset = cpmac_mdio_reset; + cpmac_mii->irq = mii_irqs; + +- cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256); ++ cpmac_mii->priv = ioremap(ar7_is_titan() ? TITAN_REGS_MDIO : AR7_REGS_MDIO, 256); + + if (!cpmac_mii->priv) { + pr_err("Can't ioremap mdio registers\n"); +@@ -1238,10 +1240,16 @@ int cpmac_init(void) + #warning FIXME: unhardcode gpio&reset bits + ar7_gpio_disable(26); + ar7_gpio_disable(27); +- ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); +- ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); ++ ++ if (!ar7_is_titan()) { ++ ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); ++ ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); ++ } + ar7_device_reset(AR7_RESET_BIT_EPHY); + ++ if (ar7_is_titan()) ++ ar7_device_reset(TITAN_RESET_BIT_EPHY1); ++ + cpmac_mii->reset(cpmac_mii); + + for (i = 0; i < 300; i++) { +@@ -1258,7 +1266,11 @@ int cpmac_init(void) + mask = 0; + } + +- cpmac_mii->phy_mask = ~(mask | 0x80000000); ++ if (ar7_is_titan()) ++ cpmac_mii->phy_mask = ~(mask | 0x80000000 | 0x40000000); ++ else ++ cpmac_mii->phy_mask = ~(mask | 0x80000000); ++ + snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1"); + + res = mdiobus_register(cpmac_mii); diff --git a/target/linux/ar7/patches-4.1/001-mips-ar7-fix-serial.patch b/target/linux/ar7/patches-4.1/001-mips-ar7-fix-serial.patch new file mode 100644 index 0000000..1aded92 --- /dev/null +++ b/target/linux/ar7/patches-4.1/001-mips-ar7-fix-serial.patch @@ -0,0 +1,23 @@ +From 443ab715a40881d6c9ba11b027ba154bac904cb0 Mon Sep 17 00:00:00 2001 +From: Oswald Buddenhagen +Date: Sat, 10 May 2014 23:19:08 +0200 +Subject: [PATCH] MIPS/AR7: ensure that serial ports are properly set up + +without UPF_FIXED_TYPE, the data from the PORT_AR7 uart_config entry is +never copied, resulting in a dead port. + +Signed-off-by: Oswald Buddenhagen +--- + arch/mips/ar7/platform.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -577,6 +577,7 @@ static int __init ar7_register_uarts(voi + uart_port.type = PORT_AR7; + uart_port.uartclk = clk_get_rate(bus_clk) / 2; + uart_port.iotype = UPIO_MEM32; ++ uart_port.flags = UPF_FIXED_TYPE; + uart_port.regshift = 2; + + uart_port.line = 0; diff --git a/target/linux/ar7/patches-4.1/100-fix-highmem-offset.patch b/target/linux/ar7/patches-4.1/100-fix-highmem-offset.patch new file mode 100644 index 0000000..f1a7549 --- /dev/null +++ b/target/linux/ar7/patches-4.1/100-fix-highmem-offset.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/include/asm/mach-ar7/spaces.h ++++ b/arch/mips/include/asm/mach-ar7/spaces.h +@@ -20,6 +20,8 @@ + #define UNCAC_BASE _AC(0xb4000000, UL) /* 0xa0000000 + PHYS_OFFSET */ + #define IO_BASE UNCAC_BASE + ++#define HIGHMEM_START _AC(0x20000000, UL) ++ + #include + + #endif /* __ASM_AR7_SPACES_H */ diff --git a/target/linux/ar7/patches-4.1/110-flash.patch b/target/linux/ar7/patches-4.1/110-flash.patch new file mode 100644 index 0000000..e4aeffd --- /dev/null +++ b/target/linux/ar7/patches-4.1/110-flash.patch @@ -0,0 +1,22 @@ +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -12,7 +12,7 @@ obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o + obj-$(CONFIG_MTD_AFS_PARTS) += afs.o +-obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o ++obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o titanpart.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -199,7 +199,7 @@ static struct resource physmap_flash_res + .name = "mem", + .flags = IORESOURCE_MEM, + .start = 0x10000000, +- .end = 0x107fffff, ++ .end = 0x11ffffff, + }; + + static const char *ar7_probe_types[] = { "ar7part", NULL }; diff --git a/target/linux/ar7/patches-4.1/120-gpio_chrdev.patch b/target/linux/ar7/patches-4.1/120-gpio_chrdev.patch new file mode 100644 index 0000000..1468ca3 --- /dev/null +++ b/target/linux/ar7/patches-4.1/120-gpio_chrdev.patch @@ -0,0 +1,28 @@ +--- a/drivers/char/Kconfig ++++ b/drivers/char/Kconfig +@@ -461,6 +461,15 @@ config MWAVE + To compile this driver as a module, choose M here: the + module will be called mwave. + ++config AR7_GPIO ++ tristate "TI AR7 GPIO Support" ++ depends on AR7 ++ help ++ Give userspace access to the GPIO pins on the Texas Instruments AR7 ++ processors. ++ ++ If compiled as a module, it will be called ar7_gpio. ++ + config SCx200_GPIO + tristate "NatSemi SCx200 GPIO Support" + depends on SCx200 +--- a/drivers/char/Makefile ++++ b/drivers/char/Makefile +@@ -42,6 +42,7 @@ obj-$(CONFIG_HW_RANDOM) += hw_random/ + obj-$(CONFIG_PPDEV) += ppdev.o + obj-$(CONFIG_NWBUTTON) += nwbutton.o + obj-$(CONFIG_NWFLASH) += nwflash.o ++obj-$(CONFIG_AR7_GPIO) += ar7_gpio.o + obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o + obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o + obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o diff --git a/target/linux/ar7/patches-4.1/160-vlynq_try_remote_first.patch b/target/linux/ar7/patches-4.1/160-vlynq_try_remote_first.patch new file mode 100644 index 0000000..1d1310d --- /dev/null +++ b/target/linux/ar7/patches-4.1/160-vlynq_try_remote_first.patch @@ -0,0 +1,300 @@ +--- a/drivers/vlynq/vlynq.c ++++ b/drivers/vlynq/vlynq.c +@@ -119,20 +119,40 @@ static int vlynq_linked(struct vlynq_dev + return 0; + } + ++static volatile int vlynq_delay_value_new = 0; ++ ++static void vlynq_delay_wait(u32 count) ++{ ++ /* Code adopted from original vlynq driver */ ++ int i = 0; ++ volatile int *ptr = &vlynq_delay_value_new; ++ *ptr = 0; ++ ++ /* We are assuming that the each cycle takes about ++ * 23 assembly instructions. */ ++ for(i = 0; i < (count + 23)/23; i++) ++ *ptr = *ptr + 1; ++} ++ + static void vlynq_reset(struct vlynq_device *dev) + { ++ u32 rtm = readl(&dev->local->revision); ++ ++ rtm = rtm < 0x00010205 || readl(&dev->local->status) & 0x800 == 0 ? ++ 0 : 0x600000; ++ + writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET, + &dev->local->control); + + /* Wait for the devices to finish resetting */ +- msleep(5); ++ vlynq_delay_wait(0xffffff); + + /* Remove reset bit */ +- writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET, ++ writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET | rtm, + &dev->local->control); + + /* Give some time for the devices to settle */ +- msleep(5); ++ vlynq_delay_wait(0xffffff); + } + + static void vlynq_irq_unmask(struct irq_data *d) +@@ -379,6 +399,61 @@ void vlynq_unregister_driver(struct vlyn + } + EXPORT_SYMBOL(vlynq_unregister_driver); + ++enum vlynq_clk_src { ++ vlynq_clk_external, ++ vlynq_clk_local, ++ vlynq_clk_remote, ++ vlynq_clk_invalid, ++}; ++ ++static int __vlynq_set_clocks(struct vlynq_device *dev, ++ enum vlynq_clk_src clk_dir, ++ int lclk_div, int rclk_div) ++{ ++ u32 reg; ++ ++ if (clk_dir == vlynq_clk_invalid) { ++ printk(KERN_ERR "%s: attempt to set invalid clocking\n", ++ dev_name(&dev->dev)); ++ return -EINVAL; ++ } ++ ++ reg = readl(&dev->local->control); ++ if (readl(&dev->local->revision) < 0x00010205) { ++ if (clk_dir & vlynq_clk_local) ++ reg |= VLYNQ_CTRL_CLOCK_INT; ++ else ++ reg &= ~VLYNQ_CTRL_CLOCK_INT; ++ } ++ reg &= ~VLYNQ_CTRL_CLOCK_MASK; ++ reg |= VLYNQ_CTRL_CLOCK_DIV(lclk_div); ++ writel(reg, &dev->local->control); ++ ++ if (!vlynq_linked(dev)) ++ return -ENODEV; ++ ++ printk(KERN_INFO "%s: local VLYNQ protocol rev. is 0x%08x\n", ++ dev_name(&dev->dev), readl(&dev->local->revision)); ++ printk(KERN_INFO "%s: remote VLYNQ protocol rev. is 0x%08x\n", ++ dev_name(&dev->dev), readl(&dev->remote->revision)); ++ ++ reg = readl(&dev->remote->control); ++ if (readl(&dev->remote->revision) < 0x00010205) { ++ if (clk_dir & vlynq_clk_remote) ++ reg |= VLYNQ_CTRL_CLOCK_INT; ++ else ++ reg &= ~VLYNQ_CTRL_CLOCK_INT; ++ } ++ reg &= ~VLYNQ_CTRL_CLOCK_MASK; ++ reg |= VLYNQ_CTRL_CLOCK_DIV(rclk_div); ++ writel(reg, &dev->remote->control); ++ ++ if (!vlynq_linked(dev)) ++ return -ENODEV; ++ ++ return 0; ++} ++ + /* + * A VLYNQ remote device can clock the VLYNQ bus master + * using a dedicated clock line. In that case, both the +@@ -392,29 +467,16 @@ static int __vlynq_try_remote(struct vly + int i; + + vlynq_reset(dev); +- for (i = dev->dev_id ? vlynq_rdiv2 : vlynq_rdiv8; dev->dev_id ? +- i <= vlynq_rdiv8 : i >= vlynq_rdiv2; +- dev->dev_id ? i++ : i--) { ++ for (i = 0; i <= 7; i++) { + + if (!vlynq_linked(dev)) + break; + +- writel((readl(&dev->remote->control) & +- ~VLYNQ_CTRL_CLOCK_MASK) | +- VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1), +- &dev->remote->control); +- writel((readl(&dev->local->control) +- & ~(VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_MASK)) | +- VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1), +- &dev->local->control); +- +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG +- "%s: using remote clock divisor %d\n", +- dev_name(&dev->dev), i - vlynq_rdiv1 + 1); +- dev->divisor = i; ++ if (!__vlynq_set_clocks(dev, vlynq_clk_remote, i, i)) { ++ printk(KERN_INFO ++ "%s: using remote clock divisor %d\n", ++ dev_name(&dev->dev), i + 1); ++ dev->divisor = i + vlynq_rdiv1; + return 0; + } else { + vlynq_reset(dev); +@@ -433,25 +495,17 @@ static int __vlynq_try_remote(struct vly + */ + static int __vlynq_try_local(struct vlynq_device *dev) + { +- int i; ++ int i, dir = !dev->dev_id; + + vlynq_reset(dev); + +- for (i = dev->dev_id ? vlynq_ldiv2 : vlynq_ldiv8; dev->dev_id ? +- i <= vlynq_ldiv8 : i >= vlynq_ldiv2; +- dev->dev_id ? i++ : i--) { +- +- writel((readl(&dev->local->control) & +- ~VLYNQ_CTRL_CLOCK_MASK) | +- VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_DIV(i - vlynq_ldiv1), +- &dev->local->control); +- +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG +- "%s: using local clock divisor %d\n", +- dev_name(&dev->dev), i - vlynq_ldiv1 + 1); +- dev->divisor = i; ++ for (i = dir ? 7 : 0; dir ? i >= 0 : i <= 7; dir ? i-- : i++) { ++ ++ if (!__vlynq_set_clocks(dev, vlynq_clk_local, i, 0)) { ++ printk(KERN_INFO ++ "%s: using local clock divisor %d\n", ++ dev_name(&dev->dev), i + 1); ++ dev->divisor = i + vlynq_ldiv1; + return 0; + } else { + vlynq_reset(dev); +@@ -473,18 +527,10 @@ static int __vlynq_try_external(struct v + if (!vlynq_linked(dev)) + return -ENODEV; + +- writel((readl(&dev->remote->control) & +- ~VLYNQ_CTRL_CLOCK_INT), +- &dev->remote->control); +- +- writel((readl(&dev->local->control) & +- ~VLYNQ_CTRL_CLOCK_INT), +- &dev->local->control); +- +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG "%s: using external clock\n", +- dev_name(&dev->dev)); +- dev->divisor = vlynq_div_external; ++ if (!__vlynq_set_clocks(dev, vlynq_clk_external, 0, 0)) { ++ printk(KERN_INFO "%s: using external clock\n", ++ dev_name(&dev->dev)); ++ dev->divisor = vlynq_div_external; + return 0; + } + +@@ -501,24 +547,16 @@ static int __vlynq_enable_device(struct + return result; + + switch (dev->divisor) { +- case vlynq_div_external: + case vlynq_div_auto: + /* When the device is brought from reset it should have clock + * generation negotiated by hardware. + * Check which device is generating clocks and perform setup + * accordingly */ +- if (vlynq_linked(dev) && readl(&dev->remote->control) & +- VLYNQ_CTRL_CLOCK_INT) { +- if (!__vlynq_try_remote(dev) || +- !__vlynq_try_local(dev) || +- !__vlynq_try_external(dev)) +- return 0; +- } else { +- if (!__vlynq_try_external(dev) || +- !__vlynq_try_local(dev) || +- !__vlynq_try_remote(dev)) +- return 0; +- } ++ if (!__vlynq_try_remote(dev) || !__vlynq_try_local(dev)) ++ return 0; ++ case vlynq_div_external: ++ if (!__vlynq_try_external(dev)) ++ return 0; + break; + case vlynq_ldiv1: + case vlynq_ldiv2: +@@ -528,15 +566,12 @@ static int __vlynq_enable_device(struct + case vlynq_ldiv6: + case vlynq_ldiv7: + case vlynq_ldiv8: +- writel(VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_DIV(dev->divisor - +- vlynq_ldiv1), &dev->local->control); +- writel(0, &dev->remote->control); +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG +- "%s: using local clock divisor %d\n", +- dev_name(&dev->dev), +- dev->divisor - vlynq_ldiv1 + 1); ++ if (!__vlynq_set_clocks(dev, vlynq_clk_local, dev->divisor - ++ vlynq_ldiv1, 0)) { ++ printk(KERN_INFO ++ "%s: using local clock divisor %d\n", ++ dev_name(&dev->dev), ++ dev->divisor - vlynq_ldiv1 + 1); + return 0; + } + break; +@@ -548,20 +583,17 @@ static int __vlynq_enable_device(struct + case vlynq_rdiv6: + case vlynq_rdiv7: + case vlynq_rdiv8: +- writel(0, &dev->local->control); +- writel(VLYNQ_CTRL_CLOCK_INT | +- VLYNQ_CTRL_CLOCK_DIV(dev->divisor - +- vlynq_rdiv1), &dev->remote->control); +- if (vlynq_linked(dev)) { +- printk(KERN_DEBUG +- "%s: using remote clock divisor %d\n", +- dev_name(&dev->dev), +- dev->divisor - vlynq_rdiv1 + 1); ++ if (!__vlynq_set_clocks(dev, vlynq_clk_remote, 0, ++ dev->divisor - vlynq_rdiv1)) { ++ printk(KERN_INFO ++ "%s: using remote clock divisor %d\n", ++ dev_name(&dev->dev), ++ dev->divisor - vlynq_rdiv1 + 1); + return 0; + } + break; + } +- ++ vlynq_reset(dev); + ops->off(dev); + return -ENODEV; + } +@@ -732,14 +764,14 @@ static int vlynq_probe(struct platform_d + platform_set_drvdata(pdev, dev); + + printk(KERN_INFO "%s: regs 0x%p, irq %d, mem 0x%p\n", +- dev_name(&dev->dev), (void *)dev->regs_start, dev->irq, +- (void *)dev->mem_start); ++ dev_name(&dev->dev), (void *)dev->regs_start, ++ dev->irq, (void *)dev->mem_start); + + dev->dev_id = 0; + dev->divisor = vlynq_div_auto; +- result = __vlynq_enable_device(dev); +- if (result == 0) { ++ if (!__vlynq_enable_device(dev)) { + dev->dev_id = readl(&dev->remote->chip); ++ vlynq_reset(dev); + ((struct plat_vlynq_ops *)(dev->dev.platform_data))->off(dev); + } + if (dev->dev_id) diff --git a/target/linux/ar7/patches-4.1/200-free-mem-below-kernel-offset.patch b/target/linux/ar7/patches-4.1/200-free-mem-below-kernel-offset.patch new file mode 100644 index 0000000..4011942 --- /dev/null +++ b/target/linux/ar7/patches-4.1/200-free-mem-below-kernel-offset.patch @@ -0,0 +1,15 @@ +--- a/arch/mips/ar7/memory.c ++++ b/arch/mips/ar7/memory.c +@@ -66,5 +66,11 @@ void __init prom_meminit(void) + + void __init prom_free_prom_memory(void) + { +- /* Nothing to free */ ++ /* adapted from arch/mips/txx9/generic/setup.c */ ++ unsigned long saddr = PHYS_OFFSET + PAGE_SIZE; ++ unsigned long eaddr = __pa_symbol(&_text); ++ ++ /* free memory between prom-record and kernel _text base */ ++ if (saddr < eaddr) ++ free_init_pages("prom memory", saddr, eaddr); + } diff --git a/target/linux/ar7/patches-4.1/300-add-ac49x-platform.patch b/target/linux/ar7/patches-4.1/300-add-ac49x-platform.patch new file mode 100644 index 0000000..2e5528e --- /dev/null +++ b/target/linux/ar7/patches-4.1/300-add-ac49x-platform.patch @@ -0,0 +1,85 @@ +--- a/arch/mips/ar7/Platform ++++ b/arch/mips/ar7/Platform +@@ -3,4 +3,9 @@ + # + platform-$(CONFIG_AR7) += ar7/ + cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7 +-load-$(CONFIG_AR7) += 0xffffffff94100000 ++load-$(CONFIG_AR7_TI) += 0xffffffff94100000 ++ ++# ++# AudioCodes AC49x ++# ++load-$(CONFIG_AR7_AC49X) += 0xffffffff945ca000 +--- a/arch/mips/ar7/setup.c ++++ b/arch/mips/ar7/setup.c +@@ -69,6 +69,10 @@ const char *get_system_type(void) + return "TI AR7 (TNETV1056)"; + case TITAN_CHIP_1060: + return "TI AR7 (TNETV1060)"; ++ case TITAN_CHIP_AC495: ++ return "AudioCodes AC495"; ++ case TITAN_CHIP_AC496: ++ return "AudioCodes AC496"; + } + default: + return "TI AR7 (unknown)"; +--- a/arch/mips/include/asm/mach-ar7/ar7.h ++++ b/arch/mips/include/asm/mach-ar7/ar7.h +@@ -92,6 +92,8 @@ + #define TITAN_CHIP_1055 0x0e + #define TITAN_CHIP_1056 0x0d + #define TITAN_CHIP_1060 0x07 ++#define TITAN_CHIP_AC495 0x00 ++#define TITAN_CHIP_AC496 0x02 + + /* Interrupts */ + #define AR7_IRQ_UART0 15 +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -99,7 +99,7 @@ config AR7 + select HAVE_CLK + help + Support for the Texas Instruments AR7 System-on-a-Chip +- family: TNETD7100, 7200 and 7300. ++ family: TI TNETD7100, 7200, 7300 and AudioCodes AC49x. + + config ATH25 + bool "Atheros AR231x/AR531x SoC support" +@@ -925,6 +925,7 @@ config MIPS_PARAVIRT + endchoice + + source "arch/mips/alchemy/Kconfig" ++source "arch/mips/ar7/Kconfig" + source "arch/mips/ath25/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm47xx/Kconfig" +--- /dev/null ++++ b/arch/mips/ar7/Kconfig +@@ -0,0 +1,26 @@ ++if AR7 ++ ++config AR7_TI ++ bool ++ ++config AR7_AC49X ++ bool ++ ++choice ++ prompt "AR7 SoC family selection" ++ default AR7_TYPE_TI ++ depends on AR7 ++ help ++ Select AR7 MIPS SoC implementation. ++ ++ config AR7_TYPE_TI ++ bool "Texas Instruments AR7" ++ select AR7_TI ++ ++ config AR7_TYPE_AC49X ++ bool "AudioCodes AC49X" ++ select AR7_AC49X ++ ++endchoice ++ ++endif diff --git a/target/linux/ar7/patches-4.1/310-ac49x-prom-support.patch b/target/linux/ar7/patches-4.1/310-ac49x-prom-support.patch new file mode 100644 index 0000000..dddf221 --- /dev/null +++ b/target/linux/ar7/patches-4.1/310-ac49x-prom-support.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/ar7/prom.c ++++ b/arch/mips/ar7/prom.c +@@ -70,6 +70,7 @@ struct psbl_rec { + }; + + static const char psp_env_version[] __initconst = "TIENV0.8"; ++static const char psp_env_version_ac49x[] __initconst = "MaxENV0.2"; + + struct psp_env_chunk { + u8 num; +@@ -186,7 +187,8 @@ static void __init ar7_init_env(struct e + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300)); + void *psp_env = (void *)KSEG1ADDR(psbl->env_base); + +- if (strcmp(psp_env, psp_env_version) == 0) { ++ if (strcmp(psp_env, psp_env_version) == 0 || ++ strcmp(psp_env, psp_env_version_ac49x) == 0) { + parse_psp_env(psp_env); + } else { + for (i = 0; i < MAX_ENTRY; i++, env++) diff --git a/target/linux/ar7/patches-4.1/320-ac49x-mtd-partitions.patch b/target/linux/ar7/patches-4.1/320-ac49x-mtd-partitions.patch new file mode 100644 index 0000000..2330493 --- /dev/null +++ b/target/linux/ar7/patches-4.1/320-ac49x-mtd-partitions.patch @@ -0,0 +1,35 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -159,6 +159,11 @@ config MTD_OF_PARTS + the partition map from the children of the flash node, + as described in Documentation/devicetree/bindings/mtd/partition.txt. + ++config MTD_AC49X_PARTS ++ tristate "AudioCodes AC49X partitioning support" ++ ---help--- ++ AudioCodes AC49X partitioning support ++ + config MTD_AR7_PARTS + tristate "TI AR7 partitioning support" + ---help--- +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -11,6 +11,7 @@ obj-$(CONFIG_MTD_SPLIT) += mtdsplit/ + obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o ++obj-$(CONFIG_MTD_AC49X_PARTS) += ac49xpart.o + obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o titanpart.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -202,7 +202,7 @@ static struct resource physmap_flash_res + .end = 0x11ffffff, + }; + +-static const char *ar7_probe_types[] = { "ar7part", NULL }; ++static const char *ar7_probe_types[] = { "ac49xpart", "ar7part", NULL }; + + static struct physmap_flash_data physmap_flash_data = { + .width = 2, diff --git a/target/linux/ar7/patches-4.1/500-serial_kludge.patch b/target/linux/ar7/patches-4.1/500-serial_kludge.patch new file mode 100644 index 0000000..2321449 --- /dev/null +++ b/target/linux/ar7/patches-4.1/500-serial_kludge.patch @@ -0,0 +1,28 @@ +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -347,6 +347,13 @@ configured less than Maximum supported f + .rxtrig_bytes = {1, 4, 8, 14}, + .flags = UART_CAP_FIFO, + }, ++ [PORT_AR7] = { ++ .name = "TI-AR7", ++ .fifo_size = 16, ++ .tx_loadsz = 16, ++ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, ++ .flags = UART_CAP_FIFO | UART_CAP_AFE, ++ }, + }; + + /* Uart divisor latch read */ +@@ -3348,7 +3355,11 @@ static void serial8250_console_putchar(s + { + struct uart_8250_port *up = up_to_u8250p(port); + ++#ifdef CONFIG_AR7 ++ wait_for_xmitr(up, BOTH_EMPTY); ++#else + wait_for_xmitr(up, UART_LSR_THRE); ++#endif + serial_port_out(port, UART_TX, ch); + } + diff --git a/target/linux/ar7/patches-4.1/920-ar7part.patch b/target/linux/ar7/patches-4.1/920-ar7part.patch new file mode 100644 index 0000000..9948858 --- /dev/null +++ b/target/linux/ar7/patches-4.1/920-ar7part.patch @@ -0,0 +1,118 @@ +--- a/drivers/mtd/ar7part.c ++++ b/drivers/mtd/ar7part.c +@@ -30,11 +30,14 @@ + + #include + ++#include ++ + #define AR7_PARTS 4 + #define ROOT_OFFSET 0xe0000 + + #define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42) + #define LOADER_MAGIC2 le32_to_cpu(0xfeed1281) ++#define LOADER_MAGIC3 le32_to_cpu(0x434d4d4c) + + struct ar7_bin_rec { + unsigned int checksum; +@@ -42,12 +45,16 @@ struct ar7_bin_rec { + unsigned int address; + }; + ++int create_titan_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data); ++ + static int create_mtd_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) + { + struct ar7_bin_rec header; +- unsigned int offset; ++ unsigned int offset, mtd_start, mtd_end; + size_t len; + unsigned int pre_size = master->erasesize, post_size = 0; + unsigned int root_offset = ROOT_OFFSET; +@@ -55,6 +62,16 @@ static int create_mtd_partitions(struct + int retries = 10; + struct mtd_partition *ar7_parts; + ++ const char *prom_str = prom_getenv("ProductID"); ++ char mtd_name[] = "mtd1"; ++ if(prom_str && ++ (strcmp(prom_str, "CYWL")==0 || ++ strcmp(prom_str, "CYWM")==0 || ++ strcmp(prom_str, "CYLM")==0 || ++ strcmp(prom_str, "CYLL")==0)){ ++ return create_titan_partitions(master, pparts, data); ++ } ++ + ar7_parts = kzalloc(sizeof(*ar7_parts) * AR7_PARTS, GFP_KERNEL); + if (!ar7_parts) + return -ENOMEM; +@@ -83,34 +100,39 @@ static int create_mtd_partitions(struct + + pre_size = offset; + +- if (!ar7_parts[1].offset) { +- ar7_parts[1].offset = master->size - master->erasesize; +- post_size = master->erasesize; +- } +- + switch (header.checksum) { +- case LOADER_MAGIC1: +- while (header.length) { +- offset += sizeof(header) + header.length; +- mtd_read(master, offset, sizeof(header), &len, +- (uint8_t *)&header); +- } +- root_offset = offset + sizeof(header) + 4; +- break; + case LOADER_MAGIC2: ++ for (retries = 0; retries <= 9; retries++) { ++ mtd_name[3] = '0' + retries; ++ prom_str = prom_getenv(mtd_name); ++ if (prom_str == NULL) ++ continue; ++ sscanf(prom_str, "%i,%i", &mtd_start, &mtd_end); ++ if (pre_size == (mtd_start & 0x1ffffff)) { ++ ar7_parts[1].offset = mtd_end &= 0x1ffffff; ++ ar7_parts[1].size = post_size = master->size - mtd_end; ++ break; ++ } ++ } ++ case LOADER_MAGIC1: ++ root_offset = (header.checksum == LOADER_MAGIC1) ? 4 : 0; + while (header.length) { + offset += sizeof(header) + header.length; + mtd_read(master, offset, sizeof(header), &len, + (uint8_t *)&header); + } +- root_offset = offset + sizeof(header) + 4 + 0xff; +- root_offset &= ~(uint32_t)0xff; ++ root_offset += offset + sizeof(header); + break; + default: + printk(KERN_WARNING "Unknown magic: %08x\n", header.checksum); + break; + } + ++ if (!ar7_parts[1].offset) { ++ post_size = master->erasesize; ++ ar7_parts[1].offset = master->size - post_size; ++ } ++ + mtd_read(master, root_offset, sizeof(header), &len, (u8 *)&header); + if (header.checksum != SQUASHFS_MAGIC) { + root_offset += master->erasesize - 1; +--- a/drivers/mtd/titanpart.c ++++ b/drivers/mtd/titanpart.c +@@ -149,7 +149,7 @@ static void titan_add_partition(char * e + } + int create_titan_partitions(struct mtd_info *master, + struct mtd_partition **pparts, +- unsigned long origin) ++ struct mtd_part_parser_data *data) + { + struct nsp_img_hdr_head hdr; + struct nsp_img_hdr_section_info sect_info; diff --git a/target/linux/ar7/patches-4.1/925-actiontec_leds.patch b/target/linux/ar7/patches-4.1/925-actiontec_leds.patch new file mode 100644 index 0000000..1346a21 --- /dev/null +++ b/target/linux/ar7/patches-4.1/925-actiontec_leds.patch @@ -0,0 +1,95 @@ +--- a/arch/mips/ar7/platform.c ++++ b/arch/mips/ar7/platform.c +@@ -461,31 +461,22 @@ static struct gpio_led fb_fon_leds[] = { + }, + }; + +-static struct gpio_led gt701_leds[] = { ++static struct gpio_led actiontec_leds[] = { + { + .name = "inet:green", + .gpio = 13, +- .active_low = 1, +- }, +- { +- .name = "usb", +- .gpio = 12, +- .active_low = 1, + }, + { + .name = "inet:red", + .gpio = 9, +- .active_low = 1, + }, + { +- .name = "power:red", ++ .name = "power:green", + .gpio = 7, +- .active_low = 1, + }, + { +- .name = "power:green", ++ .name = "power:red", + .gpio = 8, +- .active_low = 1, + .default_trigger = "default-on", + }, + { +@@ -493,6 +484,44 @@ static struct gpio_led gt701_leds[] = { + .gpio = 10, + .active_low = 1, + }, ++ { ++ .name = "wifi", ++ .gpio = 6, ++ .active_low = 1, ++ }, ++ { ++ .name = "wifi:red", ++ .gpio = 3, ++ }, ++ { ++ .name = "standby", ++ .gpio = 4, ++ }, ++ { ++ .name = "wps", ++ .gpio = 16, ++ .active_low = 1, ++ }, ++ { ++ .name = "usb", ++ .gpio = 12, ++ .active_low = 1, ++ }, ++ { ++ .name = "voip", ++ .gpio = 15, ++ .active_low = 1, ++ }, ++ { ++ .name = "line1", ++ .gpio = 23, ++ .active_low = 1, ++ }, ++ { ++ .name = "line2", ++ .gpio = 25, ++ .active_low = 1, ++ }, + }; + + static struct gpio_led_platform_data ar7_led_data; +@@ -536,9 +565,9 @@ static void __init detect_leds(void) + } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) { + ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); + ar7_led_data.leds = titan_leds; +- } else if (strstr(prid, "GT701")) { +- ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds); +- ar7_led_data.leds = gt701_leds; ++ } else if (strstr(prid, "GT7") || strstr(prid, "PK5000")) { ++ ar7_led_data.num_leds = ARRAY_SIZE(actiontec_leds); ++ ar7_led_data.leds = actiontec_leds; + } + } + diff --git a/target/linux/ar7/patches-4.1/950-cpmac_titan.patch b/target/linux/ar7/patches-4.1/950-cpmac_titan.patch new file mode 100644 index 0000000..f1d432c --- /dev/null +++ b/target/linux/ar7/patches-4.1/950-cpmac_titan.patch @@ -0,0 +1,52 @@ +--- a/drivers/net/ethernet/ti/cpmac.c ++++ b/drivers/net/ethernet/ti/cpmac.c +@@ -1146,6 +1146,8 @@ static int cpmac_probe(struct platform_d + goto out; + } + ++ ar7_device_reset(pdata->reset_bit); ++ + dev->irq = platform_get_irq_byname(pdev, "irq"); + + dev->netdev_ops = &cpmac_netdev_ops; +@@ -1227,7 +1229,7 @@ int cpmac_init(void) + cpmac_mii->reset = cpmac_mdio_reset; + cpmac_mii->irq = mii_irqs; + +- cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256); ++ cpmac_mii->priv = ioremap(ar7_is_titan() ? TITAN_REGS_MDIO : AR7_REGS_MDIO, 256); + + if (!cpmac_mii->priv) { + pr_err("Can't ioremap mdio registers\n"); +@@ -1238,10 +1240,16 @@ int cpmac_init(void) + #warning FIXME: unhardcode gpio&reset bits + ar7_gpio_disable(26); + ar7_gpio_disable(27); +- ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); +- ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); ++ ++ if (!ar7_is_titan()) { ++ ar7_device_reset(AR7_RESET_BIT_CPMAC_LO); ++ ar7_device_reset(AR7_RESET_BIT_CPMAC_HI); ++ } + ar7_device_reset(AR7_RESET_BIT_EPHY); + ++ if (ar7_is_titan()) ++ ar7_device_reset(TITAN_RESET_BIT_EPHY1); ++ + cpmac_mii->reset(cpmac_mii); + + for (i = 0; i < 300; i++) { +@@ -1258,7 +1266,11 @@ int cpmac_init(void) + mask = 0; + } + +- cpmac_mii->phy_mask = ~(mask | 0x80000000); ++ if (ar7_is_titan()) ++ cpmac_mii->phy_mask = ~(mask | 0x80000000 | 0x40000000); ++ else ++ cpmac_mii->phy_mask = ~(mask | 0x80000000); ++ + snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1"); + + res = mdiobus_register(cpmac_mii); diff --git a/target/linux/ar7/src/adam2patcher.c b/target/linux/ar7/src/adam2patcher.c new file mode 100644 index 0000000..25a7807 --- /dev/null +++ b/target/linux/ar7/src/adam2patcher.c @@ -0,0 +1,59 @@ +/* + * patcher.c - ADAM2 patcher for Netgear DG834 (and compatible) + * + * Copyright (C) 2006 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +int main(int argc, char **argv) +{ + int fd; + char *ptr; + uint32_t *i; + + if (argc != 2) { + fprintf(stderr, "Usage: %s \n", argv[0]); + exit(1); + } + + if (((fd = open(argv[1], O_RDWR)) < 0) + || ((ptr = mmap(0, 128 * 1024, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0)) == (void *) (-1))) { + fprintf(stderr, "Can't open file\n"); + exit(1); + } + + i = (uint32_t *) &ptr[0x3944]; + if (*i == 0x0c000944) { + fprintf(stderr, "Unpatched ADAM2 detected. Patching... "); + *i = 0x00000000; + msync(i, sizeof(*i), MS_SYNC|MS_INVALIDATE); + fprintf(stderr, "done!\n"); + } else if (*i == 0x00000000) { + fprintf(stderr, "Patched ADAM2 detected.\n"); + } else { + fprintf(stderr, "Unknown ADAM2 detected. Can't patch!\n"); + } + + close(fd); +} diff --git a/target/linux/ar71xx/Makefile b/target/linux/ar71xx/Makefile new file mode 100644 index 0000000..24d7d5c --- /dev/null +++ b/target/linux/ar71xx/Makefile @@ -0,0 +1,24 @@ +# +# Copyright (C) 2008-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips +BOARD:=ar71xx +BOARDNAME:=Atheros AR7xxx/AR9xxx +FEATURES:=mips16 +CPU_TYPE=34kc +SUBTARGETS:=generic nand mikrotik + +KERNEL_PATCHVER:=4.1 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += \ + kmod-gpio-button-hotplug swconfig \ + kmod-ath9k wpad-mini uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/target/linux/ar71xx/base-files.mk b/target/linux/ar71xx/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/ar71xx/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/ar71xx/base-files/etc/diag.sh b/target/linux/ar71xx/base-files/etc/diag.sh new file mode 100644 index 0000000..1375f38 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/diag.sh @@ -0,0 +1,397 @@ +#!/bin/sh +# Copyright (C) 2009-2013 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/ar71xx.sh + +get_status_led() { + case $(ar71xx_board_name) in + alfa-nx) + status_led="alfa:green:led_8" + ;; + all0305) + status_led="eap7660d:green:ds4" + ;; + antminer-s1) + status_led="antminer-s1:green:system" + ;; + antminer-s3) + status_led="antminer-s3:green:system" + ;; + ap132) + status_led="ap132:green:status" + ;; + ap136-010|\ + ap136-020) + status_led="ap136:green:status" + ;; + ap147-010) + status_led="ap147:green:status" + ;; + ap135-020) + status_led="ap135:green:status" + ;; + ap81) + status_led="ap81:green:status" + ;; + ap83) + status_led="ap83:green:power" + ;; + ap96) + status_led="ap96:green:led2" + ;; + aw-nr580) + status_led="aw-nr580:green:ready" + ;; + bsb) + status_led="bsb:red:sys" + ;; + bullet-m | rocket-m | rocket-m-xw | nano-m | nanostation-m | nanostation-m-xw | loco-m-xw) + status_led="ubnt:green:link4" + ;; + rocket-m-ti) + status_led="ubnt:green:link6" + ;; + bxu2000n-2-a1) + status_led="bhu:green:status" + ;; + cap4200ag) + status_led="senao:green:pwr" + ;; + cf-e316n-v2) + status_led="$(ar71xx_board_name):blue:wan" + ;; + cpe510) + status_led="tp-link:green:link4" + ;; + db120) + status_led="db120:green:status" + ;; + dgl-5500-a1 |\ + dhp-1565-a1|\ + dir-505-a1 |\ + dir-600-a1 |\ + dir-615-e1 |\ + dir-615-i1 |\ + dir-615-e4) + status_led="d-link:green:power" + ;; + dir-615-c1) + status_led="d-link:green:status" + ;; + dir-825-b1) + status_led="d-link:orange:power" + ;; + dir-825-c1 |\ + dir-835-a1) + status_led="d-link:amber:power" + ;; + dlan-pro-500-wp) + status_led="devolo:green:wlan-2g" + ;; + dlan-pro-1200-ac) + status_led="devolo:status:wlan" + ;; + dragino2) + status_led="dragino2:red:system" + ;; + eap300v2) + status_led="engenius:blue:power" + ;; + eap7660d) + status_led="eap7660d:green:ds4" + ;; + el-mini | \ + el-m150) + status_led="easylink:green:system" + ;; + ew-dorin | ew-dorin-router) + status_led="dorin:green:status" + ;; + f9k1115v2) + status_led="belkin:blue:status" + ;; + gl-inet) + status_led="gl-connect:green:lan" + ;; + epg5000) + status_led="epg5000:amber:power" + ;; + esr1750) + status_led="esr1750:amber:power" + ;; + esr900) + status_led="engenius:amber:power" + ;; + hiwifi-hc6361) + status_led="hiwifi:blue:system" + ;; + hornet-ub | \ + hornet-ub-x2) + status_led="alfa:blue:wps" + ;; + ja76pf | \ + ja76pf2) + status_led="jjplus:green:led1" + ;; + ls-sr71) + status_led="ubnt:green:d22" + ;; + mc-mac1200r) + status_led="mercury:green:system" + ;; + mr12) + status_led="mr12:green:power" + ;; + mr16) + status_led="mr16:green:power" + ;; + mr600) + status_led="mr600:orange:power" + ;; + mr600v2) + status_led="mr600:blue:power" + ;; + mr1750) + status_led="mr1750:blue:power" + ;; + mr900 | \ + mr900v2) + status_led="mr900:blue:power" + ;; + mynet-n600 | \ + mynet-n750) + status_led="wd:blue:power" + ;; + mynet-rext) + status_led="wd:blue:power" + ;; + mzk-w04nu | \ + mzk-w300nh) + status_led="planex:green:status" + ;; + nbg460n_550n_550nh) + status_led="nbg460n:green:power" + ;; + nbg6716) + status_led="zyxel:white:power" + ;; + om2p | \ + om2pv2 | \ + om2p-hs | \ + om2p-hsv2 | \ + om2p-lc) + status_led="om2p:blue:power" + ;; + om5p | \ + om5p-an) + status_led="om5p:blue:power" + ;; + onion-omega) + status_led="onion:amber:system" + ;; + pb44) + status_led="pb44:amber:jump1" + ;; + rb-2011l|\ + rb-2011uas|\ + rb-2011uas-2hnd) + status_led="rb:green:usr" + ;; + rb-411 | rb-411u | rb-433 | rb-433u | rb-450 | rb-450g | rb-493) + status_led="rb4xx:yellow:user" + ;; + rb-750) + status_led="rb750:green:act" + ;; + rb-911g-2hpnd|\ + rb-911g-5hpacd|\ + rb-911g-5hpnd|\ + rb-912uag-2hpnd|\ + rb-912uag-5hpnd) + status_led="rb:green:user" + ;; + rb-951ui-2hnd) + status_led="rb:green:act" + ;; + rb-sxt2n|\ + rb-sxt5n) + status_led="rb:green:power" + ;; + routerstation | routerstation-pro) + status_led="ubnt:green:rf" + ;; + rw2458n) + status_led="rw2458n:green:d3" + ;; + smart-300) + status_led="nc-link:green:system" + ;; + minibox-v1) + status_led="minibox-v1:green:system" + ;; + oolite) + status_led="oolite:red:system" + ;; + qihoo-c301) + status_led="qihoo:green:status" + ;; + tew-632brp) + status_led="tew-632brp:green:status" + ;; + tew-673gru) + status_led="trendnet:blue:wps" + ;; + tew-712br|\ + tew-732br) + status_led="trendnet:green:power" + ;; + tl-mr3020) + status_led="tp-link:green:wps" + ;; + tl-wa750re) + status_led="tp-link:orange:re" + ;; + tl-wa850re) + status_led="tp-link:blue:re" + ;; + tl-wa860re) + status_led="tp-link:green:power" + ;; + tl-mr3220 | \ + tl-mr3220-v2 | \ + tl-mr3420 | \ + tl-mr3420-v2 | \ + tl-wa701nd-v2 | \ + tl-wa801nd-v2 | \ + tl-wa901nd | \ + tl-wa901nd-v2 | \ + tl-wa901nd-v3 | \ + tl-wdr3320-v2 | \ + tl-wdr3500 | \ + tl-wr1041n-v2 | \ + tl-wr1043nd | \ + tl-wr1043nd-v2 | \ + tl-wr741nd | \ + tl-wr741nd-v4 | \ + tl-wr841n-v1 | \ + tl-wr841n-v7 | \ + tl-wr841n-v8 | \ + tl-wa830re-v2 | \ + tl-wr842n-v2 | \ + tl-wr941nd | \ + tl-wr941nd-v5) + status_led="tp-link:green:system" + ;; + archer-c5 | \ + archer-c7 | \ + tl-wdr4900-v2 | \ + tl-mr10u | \ + tl-mr12u | \ + tl-mr13u | \ + tl-wdr4300 | \ + tl-wr703n | \ + tl-wr710n | \ + tl-wr720n-v3) + status_led="tp-link:blue:system" + ;; + tl-wr841n-v9) + status_led="tp-link:green:qss" + ;; + tl-wr2543n) + status_led="tp-link:green:wps" + ;; + tl-wdr6500-v2) + status_led="tp-link:white:system" + ;; + tube2h) + status_led="alfa:green:signal4" + ;; + unifi) + status_led="ubnt:green:dome" + ;; + uap-pro) + status_led="ubnt:white:dome" + ;; + unifi-outdoor-plus) + status_led="ubnt:white:front" + ;; + airgateway | \ + airgatewaypro) + status_led="ubnt:white:status" + ;; + whr-g301n | \ + whr-hp-g300n | \ + whr-hp-gn | \ + wzr-hp-g300nh) + status_led="buffalo:green:router" + ;; + wlae-ag300n) + status_led="buffalo:green:status" + ;; + wzr-hp-ag300h | \ + wzr-hp-g300nh2) + status_led="buffalo:red:diag" + ;; + r6100 | \ + wndap360 | \ + wndr3700 | \ + wndr3700v4 | \ + wndr4300 | \ + wnr2000 | \ + wnr2200 |\ + wnr612-v2 |\ + wnr1000-v2) + status_led="netgear:green:power" + ;; + wp543) + status_led="wp543:green:diag" + ;; + wpj344) + status_led="wpj344:green:status" + ;; + wpj531) + status_led="wpj531:green:sig3" + ;; + wpj558) + status_led="wpj558:green:sig3" + ;; + wrt400n) + status_led="wrt400n:blue:wps" + ;; + wrt160nl) + status_led="wrt160nl:blue:wps" + ;; + zcn-1523h-2 | zcn-1523h-5) + status_led="zcn-1523h:amber:init" + ;; + wlr8100) + status_led="sitecom:amber:status" + ;; + esac +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + case $(ar71xx_board_name) in + qihoo-c301) + local n=$(fw_printenv activeregion | cut -d = -f 2) + fw_setenv "image${n}trynum" 0 + ;; + esac + ;; + esac +} diff --git a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom new file mode 100644 index 0000000..b5f0588 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -0,0 +1,65 @@ +#!/bin/sh + +ath9k_eeprom_die() { + echo "ath9k eeprom: " "$*" + exit 1 +} + +ath9k_eeprom_extract() { + local part=$1 + local offset=$2 + local count=$3 + local mtd + + mtd=$(find_mtd_chardev $part) + [ -n "$mtd" ] || \ + ath9k_eeprom_die "no mtd device found for partition $part" + + dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ + ath9k_eeprom_die "failed to extract from $mtd" +} + +ath9k_patch_firmware_mac() { + local mac=$1 + + [ -z "$mac" ] && return + + macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=2 count=6 +} + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/ar71xx.sh +. /lib/functions.sh +. /lib/functions/system.sh + +board=$(ar71xx_board_name) + +case "$FIRMWARE" in +"soc_wmac.eeprom") + case $board in + r6100 | \ + wndr3700v4 | \ + wndr4300) + ath9k_eeprom_extract "caldata" 4096 2048 + ath9k_patch_firmware_mac $(mtd_get_mac_binary caldata 0) + ;; + *) + ath9k_eeprom_die "board $board is not supported yet" + ;; + esac + ;; + +"pci_wmac0.eeprom") + case $board in + wndr3700v4 | \ + wndr4300) + ath9k_eeprom_extract "caldata" 20480 2048 + ath9k_patch_firmware_mac $(mtd_get_mac_binary caldata 12) + ;; + *) + ath9k_eeprom_die "board $board is not supported yet" + ;; + esac + ;; +esac diff --git a/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata new file mode 100644 index 0000000..f53c853 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -0,0 +1,98 @@ +#!/bin/sh + +ath10kcal_die() { + echo "ath10cal: " "$*" + exit 1 +} + +ath10kcal_from_file() { + local source=$1 + local offset=$2 + local count=$3 + + dd if=$source of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ + ath10kcal_die "failed to extract calibration data from $source" +} + +ath10kcal_extract() { + local part=$1 + local offset=$2 + local count=$3 + local mtd + + mtd=$(find_mtd_chardev $part) + [ -n "$mtd" ] || \ + ath10kcal_die "no mtd device found for partition $part" + + dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count 2>/dev/null || \ + ath10kcal_die "failed to extract calibration data from $mtd" +} + +ath10kcal_patch_mac() { + local mac=$1 + + [ -z "$mac" ] && return + + macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=6 count=6 +} + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/ar71xx.sh +. /lib/functions.sh +. /lib/functions/system.sh + +board=$(ar71xx_board_name) + +case "$FIRMWARE" in +"ath10k/cal-pci-0000:00:00.0.bin") + case $board in + dlan-pro-1200-ac) + ath10kcal_extract "art" 20480 2116 + ;; + mc-mac1200r) + ath10kcal_extract "art" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -1) + ;; + tl-wdr6500-v2) + ath10kcal_extract "art" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -2) + ;; + r6100) + ath10kcal_extract "caldata" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) +2) + ;; + qihoo-c301) + ath10kcal_extract "radiocfg" 20480 2116 + ath10kcal_patch_mac $(mtd_get_mac_ascii devdata wlan5mac) + ;; + esr1750 | \ + epg5000) + ath10kcal_extract "caldata" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +1) + ;; + mr1750) + ath10kcal_extract "ART" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16) + ;; + esac + ;; +"ath10k/cal-pci-0000:01:00.0.bin") + case $board in + archer-c5 | \ + archer-c7) + ath10kcal_extract "art" 20480 2116 + ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth1/address) -2) + ;; + nbg6716) + ath10kcal_extract "RFdata" 20480 2116 + ;; + rb-911g-5hpacd) + ath10kcal_from_file "/sys/firmware/routerboot/ext_wlan_data" 20480 2116 + ;; + esac + ;; +*) + exit 1 + ;; +esac diff --git a/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix b/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix new file mode 100644 index 0000000..1024150 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/hotplug.d/net/10-ar922x-led-fix @@ -0,0 +1,51 @@ +#!/bin/sh + +# For AR9220 and AR9223, GPIO JTAG must explicit be disabled +# before LEDs start working. Do this when wifi device is +# detected. + +# +# $DEVPATH is not valid for some boards (including WZR-HP-AG300H). +# Manipulate the $DEVPATH to reach the corresponding phyN. +# + +devdir=`dirname $DEVPATH` +devdir=`dirname $devdir` +phydir=/sys$devdir/ieee80211 +phyname=`cat $phydir/phy*/name` + +if [ -z $phyname -o $ACTION != "add" ]; then exit 0; fi + +# +# ar922x_disable_gpio_jtag(): +# +# Emulate +# REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); +# for AR9220 and AR9223. +# + +ar922x_disable_gpio_jtag() +{ + local regidx=0x4054 + + [ -f /sys/kernel/debug/ieee80211/$1/ath9k/regidx ] && { + echo $regidx > /sys/kernel/debug/ieee80211/$1/ath9k/regidx + regval=`cat /sys/kernel/debug/ieee80211/$1/ath9k/regval` + regval=$((regval | 0x20000)) + echo regval $regval + echo $regval > /sys/kernel/debug/ieee80211/$1/ath9k/regval + } +} + +if [ $phyname -a $ACTION = "add" ]; then + + . /lib/ar71xx.sh + + case $(ar71xx_board_name) in + wzr-hp-ag300h) + ar922x_disable_gpio_jtag $phyname + ;; + esac; +fi + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/inittab b/target/linux/ar71xx/base-files/etc/inittab new file mode 100644 index 0000000..7817185 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/inittab @@ -0,0 +1,3 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +::askconsole:/bin/ash --login diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/01_gpio-switches b/target/linux/ar71xx/base-files/etc/uci-defaults/01_gpio-switches new file mode 100644 index 0000000..b41f275 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/01_gpio-switches @@ -0,0 +1,25 @@ +#!/bin/sh +# +# Copyright (C) 2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +nanostation-m) + ucidef_set_gpio_switch "poe_passthrough" "PoE Passthrough" "8" + ;; +nanostation-m-xw) + ucidef_set_gpio_switch "poe_passthrough" "PoE Passthrough" "2" + ;; +cpe510) + ucidef_set_gpio_switch "poe_passthrough" "PoE Passthrough" "20" + ;; +esac + +ucidef_commit_gpio_switches + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..abed456 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,635 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +airgateway | \ +airgatewaypro) + ucidef_set_led_wlan "wlan" "WLAN" "ubnt:blue:wlan" "phy0tpt" + ;; +alfa-nx) + ucidef_set_led_netdev "wan" "WAN" "alfa:green:led_2" "eth0" + ucidef_set_led_netdev "lan" "LAN" "alfa:green:led_3" "eth1" + ;; + +all0258n) + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "all0258n:red:rssilow" "wlan0" "1" "40" "0" "6" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "all0258n:yellow:rssimedium" "wlan0" "30" "80" "-29" "5" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "all0258n:green:rssihigh" "wlan0" "70" "100" "-69" "8" + ;; + +all0315n) + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "all0315n:red:rssilow" "wlan0" "1" "40" "0" "6" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "all0315n:yellow:rssimedium" "wlan0" "30" "80" "-29" "5" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "all0315n:green:rssihigh" "wlan0" "70" "100" "-69" "8" + ;; + +antminer-s1) + ucidef_set_led_default "sys" "SYS" "antminer-s1:green:sys" "0" + ucidef_set_led_wlan "wlan" "WLAN" "antminer-s1:green:wlan" "phy0tpt" + ;; + +antminer-s3) + ucidef_set_led_wlan "wlan" "WLAN" "antminer-s3:green:wlan" "phy0tpt" + ucidef_set_led_default "sys" "SYS" "antminer-s3:green:sys" "0" + ucidef_set_led_default "lan" "LAN" "antminer-s3:yellow:lan" "0" + ;; + +ap113) + ucidef_set_led_usbdev "usb" "USB" "ap113:green:usb" "1-1" + ;; + +ap147-010) + ucidef_set_led_netdev "wan" "WAN" "ap147:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "ap147:green:lan1" "switch0" "0x10" + ucidef_set_led_switch "lan2" "LAN2" "ap147:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "ap147:green:lan3" "switch0" "0x04" + ucidef_set_led_switch "lan4" "LAN4" "ap147:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "ap147:green:wlan-2g" "phy0tpt" + ;; + +bsb) + ucidef_set_led_default "sys" "SYS" "bsb:red:sys" "1" + ;; + +bullet-m | \ +nanostation-m | \ +rocket-m | \ +rocket-m-xw | \ +nanostation-m-xw | \ +loco-m-xw) + ucidef_set_led_rssi "rssilow" "RSSILOW" "ubnt:red:link1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "ubnt:orange:link2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "ubnt:green:link3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "ubnt:green:link4" "wlan0" "76" "100" "-75" "13" + ;; + +rocket-m-ti) + ucidef_set_led_rssi "rssiverylow" "RSSIVERYLOW" "ubnt:green:link1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssilow" "RSSILOW" "ubnt:green:link2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "ubnt:green:link3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "ubnt:green:link4" "wlan0" "76" "100" "-75" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "ubnt:green:link5" "wlan0" "76" "100" "-75" "13" + ucidef_set_led_rssi "rssiveryhigh" "RSSIVERYHIGH" "ubnt:green:link4" "wlan0" "76" "100" "-75" "13" + ;; + +bxu2000n-2-a1) + ucidef_set_led_wlan "wlan" "WLAN" "bhu:green:wlan" "phy0tpt" + ;; + +cap4200ag) + ucidef_set_led_default "lan_green" "LAN_GREEN" "senao:green:lan" "1" + ucidef_set_led_wlan "wlan_amber" "WLAN_AMBER" "senao:amber:wlan" "phy0tpt" + ucidef_set_led_wlan "wlan_green" "WLAN_GREEN" "senao:green:wlan" "phy1tpt" + ;; + +carambola2) + ucidef_set_led_netdev "lan" "LAN" "carambola2:orange:eth0" "eth0" + ucidef_set_led_netdev "wan" "WAN" "carambola2:orange:eth1" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "carambola2:green:wlan" "phy0tpt" + ;; + +cf-e316n-v2) + ucidef_set_led_netdev "lan" "LAN" "$board:blue:lan" "eth0" + ucidef_set_led_netdev "wan" "WAN" "$board:blue:wan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "$board:blue:wlan" "phy0tpt" + ;; + +cpe510) + ucidef_set_led_switch "lan0" "LAN0" "tp-link:green:lan0" "switch0" "0x20" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:green:link1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:green:link2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:green:link3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:green:link4" "wlan0" "76" "100" "-75" "13" + ;; + +db120) + ucidef_set_led_usbdev "usb" "USB" "db120:green:usb" "1-1" + ;; + +dragino2) + ucidef_set_led_wlan "wlan" "WLAN" "dragino2:red:wlan" "phy0tpt" + ucidef_set_led_netdev "lan" "LAN" "dragino2:red:lan" "eth0" + ucidef_set_led_netdev "wan" "WAN" "dragino2:red:wan" "eth1" + ;; + +eap300v2) + ucidef_set_led_netdev "lan" "LAN" "engenius:blue:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "engenius:blue:wlan" "phy0tpt" + ;; + +f9k1115v2) + ucidef_set_led_usbdev "usb2" "USB2" "belkin:green:usb2" "1-1" + ;; + +rb-750) + ucidef_set_led_default "act" "act" "rb750:green:act" "1" + ucidef_set_led_netdev "port1" "port1" "rb750:green:port1" "eth1" + ucidef_set_led_switch "port2" "port2" "rb750:green:port2" "switch0" "0x10" + ucidef_set_led_switch "port3" "port3" "rb750:green:port3" "switch0" "0x08" + ucidef_set_led_switch "port4" "port4" "rb750:green:port4" "switch0" "0x04" + ucidef_set_led_switch "port5" "port5" "rb750:green:port5" "switch0" "0x02" + ;; + +rb-2011l|\ +rb-2011uas|\ +rb-2011uias|\ +rb-2011uas-2hnd|\ +rb-2011uias-2hnd) + ucidef_set_led_switch "eth6" "ETH6" "rb:green:eth6" "switch1" "0x20" + ucidef_set_led_switch "eth7" "ETH7" "rb:green:eth7" "switch1" "0x10" + ucidef_set_led_switch "eth8" "ETH8" "rb:green:eth8" "switch1" "0x08" + ucidef_set_led_switch "eth9" "ETH9" "rb:green:eth9" "switch1" "0x04" + ucidef_set_led_switch "eth10" "ETH10" "rb:green:eth10" "switch1" "0x02" + ;; + +dhp-1565-a1) + ucidef_set_led_switch "wan" "WAN" "d-link:green:planet" "switch0" "0x20" + ;; + +dir-505-a1) + ucidef_set_led_netdev "lan" "LAN" "d-link:green:power" "eth1" + ;; + +dir-600-a1|\ +dir-615-e1|\ +dir-615-e4) + ucidef_set_led_netdev "wan" "WAN" "d-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "d-link:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "d-link:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "d-link:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "d-link:green:lan4" "switch0" "0x10" + ;; + +dir-615-c1) + ucidef_set_led_netdev "wan" "WAN" "d-link:green:wan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "d-link:green:wlan" "phy0tpt" + ;; + +dir-825-b1) + ucidef_set_led_usbdev "usb" "USB" "d-link:blue:usb" "1-1" + ;; + +dir-615-i1) + ucidef_set_led_default "power" "POWER" "d-link:green:power" "1" + ucidef_set_led_default "diag" "DIAG" "d-link:amber:power" "0" + ucidef_set_led_default "wps" "WPS" "d-link:blue:wps" "0" + ucidef_set_led_netdev "wan" "WAN" "d-link:green:wan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "d-link:green:wlan" "phy0tpt" + ;; + +dir-825-c1) + ucidef_set_led_usbdev "usb" "USB" "d-link:blue:usb" "1-1" + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "d-link:blue:wlan2g" "phy0tpt" + ;; + +dlan-pro-500-wp) + ucidef_set_led_default "power" "System Power" "devolo:green:status" "1" + ucidef_set_led_netdev "lan" "Ethernet Activity" "devolo:green:eth" "br-lan" + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "devolo:green:wlan-2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "devolo:blue:wlan-5g" "none" + ;; + +dlan-pro-1200-ac) + ucidef_set_led_wlan "wlan" "WLAN" "devolo:status:wlan" "phy0radio" + ucidef_set_led_trigger_gpio "plcw" "dLAN" "devolo:status:dlan" "17" "0" + ucidef_set_led_trigger_gpio "plcr" "dLAN" "devolo:error:dlan" "16" "0" + ;; + +gl-inet) + ucidef_set_led_netdev "lan" "LAN" "gl-connect:green:lan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "gl-connect:red:wlan" "phy0tpt" + ;; + +esr900) + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "engenius:blue:wlan-2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "engenius:blue:wlan-5g" "phy1tpt" + ;; + +esr1750) + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "esr1750:blue:wlan-2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "esr1750:blue:wlan-5g" "phy0tpt" + ;; + +epg5000) + ucidef_set_led_wlan "wlan2g" "WLAN 2.4 GHz" "epg5000:blue:wlan-2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN 5 GHz" "epg5000:blue:wlan-5g" "phy0tpt" + ;; + +hiwifi-hc6361) + ucidef_set_led_netdev "inet" "INET" "hiwifi:blue:internet" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "hiwifi:blue:wlan-2p4" "phy0tpt" + ;; + +hornet-ub | \ +hornet-ub-x2) + ucidef_set_led_netdev "lan" "LAN" "alfa:blue:lan" "eth0" + ucidef_set_led_netdev "wan" "WAN" "alfa:blue:wan" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "alfa:blue:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "alfa:blue:usb" "1-1" + ;; + +mc-mac1200r) + ucidef_set_led_wlan "wlan2g" "WLAN2G" "mercury:green:wlan2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "mercury:green:wlan5g" "phy0tpt" + ;; + +mr12) + ucidef_set_led_netdev "wan" "WAN" "mr12:green:wan" "eth0" + ucidef_set_led_wlan "wlan1" "WLAN1" "mr12:green:wifi1" "phy0assoc" + ucidef_set_led_wlan "wlan2" "WLAN2" "mr12:green:wifi2" "phy0assoc" + ucidef_set_led_wlan "wlan3" "WLAN3" "mr12:green:wifi3" "phy0assoc" + ucidef_set_led_wlan "wlan4" "WLAN4" "mr12:green:wifi4" "phy0tpt" + ;; + +mr16) + ucidef_set_led_netdev "wan" "WAN" "mr16:green:wan" "eth0" + ucidef_set_led_wlan "wlan1" "WLAN1" "mr16:green:wifi1" "phy0assoc" + ucidef_set_led_wlan "wlan2" "WLAN2" "mr16:green:wifi2" "phy0assoc" + ucidef_set_led_wlan "wlan3" "WLAN3" "mr16:green:wifi3" "phy0assoc" + ucidef_set_led_wlan "wlan4" "WLAN4" "mr16:green:wifi4" "phy0tpt" + ;; + +mr600) + ucidef_set_led_wlan "wlan58" "WLAN58" "mr600:green:wlan58" "phy0tpt" + ;; + +mr1750) + ucidef_set_led_netdev "lan" "LAN" "mr1750:blue:wan" "eth0" + ucidef_set_led_wlan "wlan58" "WLAN58" "mr1750:blue:wlan58" "phy0tpt" + ucidef_set_led_wlan "wlan24" "WLAN24" "mr1750:blue:wlan24" "phy1tpt" + ;; + +mr900 | \ +mr900v2) + ucidef_set_led_netdev "lan" "LAN" "mr900:blue:wan" "eth0" + ucidef_set_led_wlan "wlan24" "WLAN24" "mr900:blue:wlan24" "phy0tpt" + ucidef_set_led_wlan "wlan58" "WLAN58" "mr900:blue:wlan58" "phy1tpt" + ;; + +mynet-n600) + ucidef_set_led_netdev "wan" "WAN" "wd:blue:internet" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "wd:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "wd:green:lan2" "switch0" "0x10" + ucidef_set_led_switch "lan3" "LAN3" "wd:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "wd:green:lan4" "switch0" "0x04" + ;; + +mynet-rext) + ucidef_set_led_netdev "lan" "LAN" "wd:blue:ethernet" "eth0" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "wd:blue:quality1" "wlan0" "1" "40" "0" "6" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "wd:blue:quality2" "wlan0" "30" "80" "-29" "5" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "wd:blue:quality3" "wlan0" "70" "100" "-69" "8" + ucidef_set_led_wlan "wlan" "WLAN" "wd:blue:wireless" "phy0tpt" + ;; + +mzk-w04u) + ucidef_set_led_usbdev "usb" "USB" "planex:green:usb" "1-1" + ;; + +mzk-w300nh) + ucidef_set_led_wlan "wlan" "WLAN" "planex:green:wlan" "phy0tpt" + ;; + +nbg460n_550n_550nh) + ucidef_set_led_wlan "wlan" "WLAN" "nbg460n:green:wlan" "phy0tpt" + ;; + +nbg6716) + ucidef_set_led_netdev "wan" "WAN" "zyxel:white:internet" "eth1" + ucidef_set_led_wlan "wlan" "WLAN" "zyxel:white:wifi2g" "phy1tpt" + ucidef_set_led_wlan "wlan5" "WLAN5" "zyxel:white:wifi5g" "phy0tpt" + ucidef_set_led_usbdev "usb1" "USB1" "zyxel:white:usb1" "2-1" + ucidef_set_led_usbdev "usb2" "USB2" "zyxel:white:usb2" "1-1" + ;; + +om2p | \ +om2pv2 | \ +om2p-hs | \ +om2p-hsv2 | \ +om2p-lc) + ucidef_set_led_netdev "port1" "port1" "om2p:blue:wan" "eth0" + ucidef_set_led_netdev "port2" "port2" "om2p:blue:lan" "eth1" + ;; + +om5p | \ +om5p-an) + ucidef_set_led_netdev "port1" "port1" "om5p:blue:wan" "eth0" + ucidef_set_led_netdev "port2" "port2" "om5p:blue:lan" "eth1" + ;; + +qihoo-c301) + ucidef_set_led_wlan "wlan2g" "WLAN2G" "qihoo:red:status" "phy1tpt" + ;; + +smart-300) + ucidef_set_led_netdev "wan" "WAN" "nc-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "nc-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "nc-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "nc-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "nc-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "nc-link:green:wlan" "phy0tpt" + ;; + +tew-712br) + ucidef_set_led_netdev "wan" "WAN" "trendnet:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "trendnet:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "trendnet:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "trendnet:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "trendnet:green:lan4" "switch0" "0x10" + ucidef_set_led_wlan "wlan" "WLAN" "trendnet:green:wlan" "phy0tpt" + ;; + +tew-732br) + ucidef_set_led_netdev "wan" "WAN" "trendnet:green:wan" "eth1" + ;; + +tl-mr11u | \ +tl-mr3020 | \ +tl-mr3040 | \ +tl-mr3040-v2) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ;; + +tl-mr3220 | \ +tl-mr3420 ) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-mr3220-v2) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-mr3420-v2) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-wa7210n-v2) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:green:signal1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:green:signal2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:green:signal3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:green:signal4" "wlan0" "76" "100" "-75" "13" + ;; + +tl-wa750re) + ucidef_set_led_netdev "lan" "LAN" "tp-link:orange:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:orange:wlan" "phy0tpt" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:orange:signal1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:orange:signal2" "wlan0" "20" "100" "-19" "13" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "tp-link:orange:signal3" "wlan0" "40" "100" "-39" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:orange:signal4" "wlan0" "60" "100" "-59" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:orange:signal5" "wlan0" "80" "100" "-79" "13" + ;; + +tl-wa850re) + ucidef_set_led_netdev "lan" "LAN" "tp-link:blue:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:blue:wlan" "phy0tpt" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "rssilow" "RSSILOW" "tp-link:blue:signal1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "tp-link:blue:signal2" "wlan0" "20" "100" "-19" "13" + ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "tp-link:blue:signal3" "wlan0" "40" "100" "-39" "13" + ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "tp-link:blue:signal4" "wlan0" "60" "100" "-59" "13" + ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "tp-link:blue:signal5" "wlan0" "80" "100" "-79" "13" + ;; + +tl-wa701nd-v2) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wa860re) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wa901nd) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ;; + +tl-wa901nd-v2) + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wdr3320-v2) + ucidef_set_led_wlan "wlan5g" "WLAN5G" "tp-link:green:wlan5g" "phy0tpt" + ;; + +tl-wdr3500) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:usb" "1-1" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:green:wlan2g" "phy0tpt" + ;; + +tl-wdr4300) + ucidef_set_led_usbdev "usb1" "USB1" "tp-link:green:usb1" "1-1.1" + ucidef_set_led_usbdev "usb2" "USB2" "tp-link:green:usb2" "1-1.2" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:blue:wlan2g" "phy0tpt" + ;; + +tl-wdr4900-v2) + ucidef_set_led_usbdev "usb1" "USB1" "tp-link:green:usb1" "1-1" + ucidef_set_led_usbdev "usb2" "USB2" "tp-link:green:usb2" "2-1" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:blue:wlan2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "tp-link:blue:wlan5g" "phy1tpt" + ;; + +tl-wdr6500-v2) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x10" + ;; + +archer-c5|\ +archer-c7) + ucidef_set_led_usbdev "usb1" "USB1" "tp-link:green:usb1" "1-1" + ucidef_set_led_usbdev "usb2" "USB2" "tp-link:green:usb2" "2-1" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "tp-link:blue:wlan2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "tp-link:blue:wlan5g" "phy0tpt" + ;; + +tl-wr741nd) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x10" + ;; + +tl-wr741nd-v4) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr841n-v8 | \ +tl-wr941nd-v5) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wa830re-v2) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr841n-v9) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x04" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr842n-v2) + ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth0" + ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x04" + ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08" + ucidef_set_led_switch "lan3" "LAN3" "tp-link:green:lan3" "switch0" "0x10" + ucidef_set_led_switch "lan4" "LAN4" "tp-link:green:lan4" "switch0" "0x02" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:3g" "1-1" + ;; + +tl-wa801nd-v2 | \ +tl-wa901nd-v3) + ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr941nd | \ +tl-wr1041n-v2) + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr1043nd | \ +tl-wr1043nd-v2) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:usb" "1-1" + ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt" + ;; + +tl-wr2543n) + ucidef_set_led_usbdev "usb" "USB" "tp-link:green:usb" "1-1" + ;; + +tube2h) + ucidef_set_led_netdev "lan" "LAN" "alfa:blue:lan" "eth0" + ucidef_set_rssimon "wlan0" "40000" "1" + ucidef_set_led_rssi "signal1" "SIGNAL1" "alfa:red:signal1" "wlan0" "1" "100" "0" "13" + ucidef_set_led_rssi "signal2" "SIGNAL2" "alfa:orange:signal2" "wlan0" "26" "100" "-25" "13" + ucidef_set_led_rssi "signal3" "SIGNAL3" "alfa:green:signal3" "wlan0" "51" "100" "-50" "13" + ucidef_set_led_rssi "signal4" "SIGNAL4" "alfa:green:signal4" "wlan0" "76" "100" "-75" "13" + ;; + +wrt160nl) + ucidef_set_led_wlan "wlan" "WLAN" "wrt160nl:blue:wlan" "phy0tpt" + ;; + +wndap360) + ucidef_set_led_power "power" "POWER GREEN" "netgear:green:power" "1" + ;; + +wndr3700) + ucidef_set_led_default "wan" "WAN LED (green)" "netgear:green:wan" "0" + ucidef_set_led_usbdev "usb" "USB" "netgear:green:usb" "1-1" + ;; + +r6100) + ucidef_set_led_netdev "wan" "WAN (green)" "netgear:green:wan" "eth0" + ucidef_set_led_usbdev "usb" "USB" "netgear:blue:usb" "1-1" + ucidef_set_led_wlan "wlan" "WLAN" "netgear:blue:wlan" "phy1tpt" + ;; + +wndr3700v4 | \ +wndr4300) + ucidef_set_led_netdev "wan" "WAN (green)" "netgear:green:wan" "eth0.2" + ucidef_set_led_usbdev "usb" "USB" "netgear:green:usb" "1-1" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "netgear:green:wlan2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "netgear:blue:wlan5g" "phy1tpt" + ;; + +whr-g301n |\ +whr-hp-g300n |\ +whr-hp-gn) + ucidef_set_led_netdev "wan" "WAN" "buffalo:green:wan" "eth1" + ucidef_set_led_switch "lan1" "LAN1" "buffalo:green:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "buffalo:green:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "buffalo:green:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "buffalo:green:lan4" "switch0" "0x10" + ;; + +wlae-ag300n) + ucidef_set_led_netdev "wireless" "WIRELESS" "buffalo:green:wireless" "wlan0" + ;; + +wnr2000-v4) + ucidef_set_led_netdev "wan" "WAN" "netgear:green:wan" "eth0" + ucidef_set_led_netdev "wlan" "WLAN" "netgear:blue:wlan" "wlan0" + ucidef_set_led_switch "lan1" "LAN1" "netgear:amber:lan1" "switch0" "0x02" + ucidef_set_led_switch "lan2" "LAN2" "netgear:amber:lan2" "switch0" "0x04" + ucidef_set_led_switch "lan3" "LAN3" "netgear:amber:lan3" "switch0" "0x08" + ucidef_set_led_switch "lan4" "LAN4" "netgear:amber:lan4" "switch0" "0x10" + ucidef_set_led_usbdev "usb" "USB" "netgear:amber:status" "1-1" + ;; + +wzr-hp-ag300h) + ucidef_set_led_default "diag" "DIAG" "buffalo:red:diag" "0" + ucidef_set_led_netdev "router" "ROUTER" "buffalo:green:router" "eth1" + ucidef_set_led_usbdev "usb" "USB" "buffalo:green:usb" "1-1" + ;; + +wzr-hp-g300nh) + ucidef_set_led_wlan "wlan" "Wireless" "buffalo:green:wireless" "phy0tpt" + ucidef_set_led_netdev "router" "Router" "buffalo:green:router" "eth1" + ucidef_set_led_usbdev "usb" "USB" "buffalo:blue:usb" "1-1" + ;; + +zcn-1523h-2) + ucidef_set_led_netdev "lan1" "lan1" "zcn-1523h:green:lan1" "eth0" + ;; + +zcn-1523h-5) + ucidef_set_led_netdev "lan1" "lan1" "zcn-1523h:green:lan1" "eth0" + ucidef_set_led_netdev "lan2" "lan2" "zcn-1523h:green:lan2" "eth1" + ;; +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..f6ac891 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network @@ -0,0 +1,529 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/ar71xx.sh + +ucidef_set_interface_loopback + +board=$(ar71xx_board_name) + +case "$board" in +all0315n |\ +all0258n |\ +ja76pf2|\ +rocket-m-ti |\ +ubnt-unifi-outdoor) + ucidef_set_interface_lan "eth0 eth1" + ;; + +ap132 |\ +wlr8100) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +esr1750 |\ +epg5000) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + ;; + +ap136-010) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "5 6" + ;; + +ap147-010) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "5 6" + ;; + +ap136-020 |\ +ap135-020 |\ +tl-wr1043nd-v2 |\ +wzr-450hp2) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "5 6" + ;; + +archer-c5 |\ +archer-c7 |\ +tl-wdr4900-v2) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "1 6" + ;; + +bsb) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 3" + ucidef_set_interface_wlan + ;; + +cpe510) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 5" + ucidef_add_switch_vlan "switch0" "2" "0t 4" + ;; + +airgatewaypro) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + ;; + +db120 |\ +rb-2011l | \ +rb-2011uas |\ +rb-2011uias |\ +rb-2011uas-2hnd|\ +rb-2011uias-2hnd) + ucidef_set_interfaces_lan_wan "eth0.1 eth1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ucidef_add_switch "switch1" "1" "1" + ucidef_add_switch_vlan "switch1" "1" "0 1 2 3 4 5" + + case "$board" in + rb-2011uas* | rb-2011uias | rb-2011uias-2hnd) + ucidef_set_interface_raw "sfp" "eth0.3" + ucidef_add_switch_vlan "switch0" "3" "0t 6" + ;; + esac + ;; + +dir-825-b1|\ +tew-673gru) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + ;; + +f9k1115v2) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "2 3 4 5 6" + ucidef_add_switch_vlan "switch0" "2" "0 1" + ;; + +nbg460n_550n_550nh) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "0" "0 1 2 3 5" + ;; + +nbg6716) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "5 6" + ;; + +ap143 |\ +rb-433 |\ +rb-433u) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 5" + ;; + +rb-435g) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2" + ;; + +rb-450) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5" + ;; + +rb-450g |\ +routerstation-pro) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ;; + +ap136 |\ +rb-750gl |\ +rb-751g |\ +rb-951g-2hnd |\ +wzr-hp-g450h) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +rb-951ui-2hnd) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; + +rb-493g) + ucidef_set_interfaces_lan_wan "eth0 eth1.1" "eth1.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ucidef_add_switch "switch1" "1" "1" + ucidef_add_switch_vlan "switch1" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch1" "2" "0t 5" + ;; + +wzr-hp-g300nh2 |\ +pb92 |\ +ap113) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 2" + ;; + +el-m150) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 3" + ;; + +tl-wdr4300|\ +tl-wr1041n-v2) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +tl-wr1043nd) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 3 4 5t" + ucidef_add_switch_vlan "switch0" "2" "0 5t" + ;; + +tl-wr2543n) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 3 4 9t" + ucidef_add_switch_vlan "switch0" "2" "0 9t" + ;; + +tl-wr841n-v1|\ +tl-wr941nd) + ucidef_set_interface_raw "eth" "eth0" + ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan" + ;; + +dir-615-i1 |\ +r6100 |\ +smart-300 |\ +tl-mr3420-v2 |\ +tl-wr841n-v8 |\ +tl-wr842n-v2 |\ +tl-wr941nd-v5 |\ +tl-wdr6500-v2 |\ +wnr2000-v3 |\ +wnr2000-v4 |\ +wnr2200 |\ +wnr612-v2 |\ +wnr1000-v2) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ;; + +uap-pro) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1" + ucidef_add_switch_vlan "switch0" "2" "0t 2" + ;; + +nanostation-m-xw) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +wrt160nl) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4 5" + ;; + +wzr-hp-g300nh) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + ;; + +dgl-5500-a1 |\ +dir-825-c1) + local mac + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + mac=$(mtd_get_mac_ascii nvram "wan_mac") + [ -n "$mac" ] && ucidef_set_interface_macaddr "wan" "$mac" + ;; + +mynet-n750) + local mac + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + mac=$(mtd_get_mac_ascii devdata "wanmac") + [ -n "$mac" ] && ucidef_set_interface_macaddr "wan" "$mac" + ;; + +onion-omega) + ucidef_set_interface_lan "wlan0" + ;; + +dhp-1565-a1 |\ +dir-835-a1 |\ +wndr3700v4 | \ +wndr4300) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + mac_lan=$(mtd_get_mac_binary caldata 0) + [ -n "$mac_lan" ] && ucidef_set_interface_macaddr "lan" "$mac_lan" + mac_wan=$(mtd_get_mac_binary caldata 6) + [ -n "$mac_wan" ] && ucidef_set_interface_macaddr "wan" "$mac_wan" + ;; + +esr900) + local mac + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0t 5" + mac=$(mtd_get_mac_ascii u-boot-env "wanaddr") + [ -n "$mac" ] && ucidef_set_interface_macaddr "wan" "$mac" + ;; + +dlan-pro-500-wp) + ucidef_set_interface_lan "eth0 eth1" + ;; + +dlan-pro-1200-ac) + ucidef_set_interface_lan "eth0" + ucidef_add_switch "switch0" "1" "0" + ucidef_add_switch_vlan "switch0" "0" "0 2 3 4" + ;; + +all0305 |\ +antminer-s1 |\ +antminer-s3 |\ +aw-nr580 |\ +bullet-m |\ +cap4200ag |\ +eap300v2 |\ +eap7660d |\ +el-mini |\ +loco-m-xw |\ +mr1750 |\ +mr600 |\ +mr600v2 |\ +mr900 |\ +mr900v2 |\ +rb-411 |\ +rb-911g-2hpnd |\ +rb-911g-5hpacd |\ +rb-911g-5hpnd |\ +rb-912uag-2hpnd |\ +rb-912uag-5hpnd |\ +rb-sxt2n |\ +rb-sxt5n |\ +rocket-m-xw |\ +tl-mr10u |\ +tl-mr11u |\ +tl-mr12u |\ +tl-mr13u |\ +tl-mr3020 |\ +tl-mr3040 |\ +tl-mr3040-v2 |\ +tl-wa701nd-v2 |\ +tl-wa7210n-v2 |\ +tl-wa750re |\ +tl-wa850re |\ +tl-wa830re-v2 |\ +tl-wa801nd-v2 |\ +tl-wa901nd |\ +tl-wa901nd-v2 |\ +tl-wa901nd-v3 |\ +tl-wr703n |\ +tube2h |\ +wndap360 |\ +mynet-rext |\ +wp543) + ucidef_set_interface_lan "eth0" + ;; + +dir-505-a1) + ucidef_set_interface_lan "eth1" + ;; + +alfa-ap96 |\ +alfa-nx |\ +ap83 |\ +gl-inet |\ +jwap003 |\ +pb42 |\ +pb44 |\ +routerstation|\ +tl-wr710n |\ +tl-wr720n-v3|\ +wpe72) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; + +wpj344) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 3" + ucidef_add_switch_vlan "switch0" "2" "0t 2" + ;; + +wpj531) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; + +wpj558) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "5 6t" + ucidef_add_switch_vlan "switch0" "2" "1 6t" + ;; + +ap121 |\ +ap121-mini |\ +ap96 |\ +airrouter |\ +dir-600-a1 |\ +dir-615-c1 |\ +dir-615-e1 |\ +dir-615-e4 |\ +hiwifi-hc6361 |\ +ja76pf |\ +mc-mac1200r|\ +minibox-v1 |\ +mynet-n600 |\ +oolite |\ +qihoo-c301 |\ +rb-750 |\ +rb-751 |\ +tew-632brp |\ +tew-712br |\ +tl-mr3220 |\ +tl-mr3220-v2 |\ +tl-mr3420 |\ +tl-wdr3320-v2 |\ +tl-wdr3500 |\ +tl-wr741nd |\ +tl-wr741nd-v4 |\ +tl-wr841n-v7 |\ +tl-wr841n-v9 |\ +whr-g301n |\ +whr-hp-g300n |\ +whr-hp-gn |\ +wzr-hp-ag300h) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 4" + ;; + +wzr-hp-g450h) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; + +ew-dorin) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 1 2" + ucidef_add_switch_vlan "switch0" "2" "0t 3" + ;; + +ew-dorin-router) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 2 3" + ;; + +wndr3700) + ucidef_set_interfaces_lan_wan "eth0.1" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + # Blinkrate: 0=43ms; 1=84ms; 2=120ms; 3=170ms; 4=340ms; 5=670ms + uci set network.@switch[-1].blinkrate='2' + + ucidef_add_switch_port "switch0" "1" + # Port 1 controls the GREEN configuration of LEDs for + # the switch and the section does not correspond to a real + # switch port. + # + # 0=LED off; 1=Collision/FDX; 2=Link/activity; 3=1000 Mb/s; + # 4=100 Mb/s; 5=10 Mb/s; 6=1000 Mb/s+activity; 7=100 Mb/s+activity; + # 8=10 Mb/s+activity; 9=10/100 Mb/s+activity; 10: Fiber; + # 11: Fault; 12: Link/activity(tx); 13: Link/activity(rx); + # 14: Link (master); 15: separate register + uci set network.@switch_port[-1].led='6' + + ucidef_add_switch_port "switch0" "2" + # Port 2 controls the ORANGE configuration of LEDs for + # the switch and the section does not correspond to a real + # switch port. + # + # See the key above for switch port 1 for the meaning of the + # 'led' setting below. + uci set network.@switch_port[-1].led='9' + + ucidef_add_switch_port "switch0" "5" + # Port 5 controls the configuration of the WAN LED and the + # section does not correspond to a real switch port. + # + # To toggle the use of green or orange LEDs for the WAN port, + # see the LED setting for wndr3700:green:wan in /etc/config/system. + # + # See the key above for switch port 1 for the meaning of the + # 'led' setting below. + uci set network.@switch_port[-1].led='2' + ;; + +*) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-switchX-migration b/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-switchX-migration new file mode 100644 index 0000000..aa0e1b4 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-switchX-migration @@ -0,0 +1,110 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +SWITCH_NAME_CHANGED= + +do_change_switch_name() { + local config="$1" + local option=$2 + local oldname=$3 + local newname=$4 + local val + + config_get val "$config" $option + [ "$val" != "$oldname" ] && return 0 + + uci_set network "$config" $option $newname + SWITCH_NAME_CHANGED=1 + + return 0 +} + +migrate_switch_name() { + local oldname=$1 + local newname=$2 + + . /lib/functions.sh + + config_load network + + logger -t migrate-switchX "Updating switch names in network configuration" + + config_foreach do_change_switch_name switch name $oldname $newname + config_foreach do_change_switch_name switch_vlan device $oldname $newname + + [ "$SWITCH_NAME_CHANGED" = "1" ] && { + logger -t migrate-switchX "Switch names updated, saving network configuration" + uci commit network + } +} + +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +dir-825-c1|\ +wzr-hp-g300nh2|\ +pb92|\ +ap113|\ +tl-wdr4300|\ +tl-wr1041n-v2|\ +wrt160nl|\ +ap121|\ +ap121-mini|\ +ap96|\ +airrouter|\ +dir-600-a1|\ +dir-615-c1|\ +dir-615-e1|\ +dir-615-e4|\ +ja76pf|\ +mr-12|\ +mr-16|\ +rb-750|\ +rb-751|\ +tew-632brp|\ +tew-712br|\ +tl-mr3220|\ +tl-mr3220-v2 |\ +tl-mr3420|\ +tl-wr741nd|\ +tl-wr741nd-v4|\ +tl-wr841n-v7|\ +whr-g301n|\ +whr-hp-g300n|\ +whr-hp-gn|\ +wzr-hp-ag300h|\ +wzr-hp-g450h|\ +ew-dorin|\ +ew-dorin-router) + migrate_switch_name "eth0" "switch0" + ;; + +el-m150|\ +rb-450) + migrate_switch_name "eth1" "switch0" + ;; + +db120 |\ +rb-2011l | \ +rb-2011uas-2hnd) + migrate_switch_name "eth0" "switch0" + migrate_switch_name "eth1" "switch1" + ;; + +dir-825-b1|\ +tew-673gru|\ +nbg460n_550n_550nh) + migrate_switch_name "rtl8366s" "switch0" + ;; + +tl-wr1043nd) + migrate_switch_name "rtl8366rb" "switch0" + ;; + +esac + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-vlan-migration b/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-vlan-migration new file mode 100644 index 0000000..bea9493 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/03_network-vlan-migration @@ -0,0 +1,13 @@ +#!/bin/sh +# +# Copyright (C) 2010 OpenWrt.org +# + +local dev="$(uci -q get network.@switch_vlan[0].device)" +local vlan="$(uci -q get network.@switch_vlan[0].vlan)" + +if [ "$dev" = "rtl8366s" ] && [ "$vlan" = 0 ]; then + logger -t vlan-migration "VLAN 0 is invalid for RTL8366s, changing to 1" + uci set network.@switch_vlan[0].vlan=1 + uci commit network +fi diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/04_led_migration b/target/linux/ar71xx/base-files/etc/uci-defaults/04_led_migration new file mode 100644 index 0000000..d578f59 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/04_led_migration @@ -0,0 +1,90 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +LED_OPTIONS_CHANGED=0 + +. /lib/functions.sh + +do_led_update_sysfs() +{ + local cfg=$1; shift + local tuples="$@" + local sysfs + local name + + config_get sysfs $cfg sysfs + config_get name $cfg name + + [ -z "$sysfs" ] && return + + for tuple in $tuples; do + local old=${tuple%=*} + local new=${tuple#*=} + local new_sysfs + + new_sysfs=$(echo ${sysfs} | sed "s/${old}/${new}/") + + [ "$new_sysfs" = "$sysfs" ] && continue + + uci set system.${cfg}.sysfs="${new_sysfs}" + LED_OPTIONS_CHANGED=1 + + logger -t led-migration "sysfs option of LED \"${name}\" updated to ${new_sysfs}" + done; +} + +migrate_leds() +{ + config_load system + config_foreach do_led_update_sysfs led "$@" +} + +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +case "$board" in +dhp-1565-a1|\ +dir-825-c1|\ +dir-835-a1) + migrate_leds ":orange:=:amber:" ":wifi_bgn=:wlan2g" + ;; + +wndap360) + migrate_leds "wndap360:=netgear:" + ;; + +wndr3700) + migrate_leds "wndr3700:=netgear:" + ;; + +wndr3700v4 | \ +wndr4300) + migrate_leds ":orange:=:amber:" + ;; + +wnr2000) + migrate_leds "wnr2000:=netgear:" + ;; + +wnr2200) + migrate_leds "wnr2200:=netgear:" + ;; + +wnr612-v2) + migrate_leds "wnr612v2:=netgear:" + ;; + +wnr1000-v2) + migrate_leds "wnr1000v2:=netgear:" + ;; + +*) + ;; +esac + +[ "$LED_OPTIONS_CHANGED" = "1" ] && uci commit system + +exit 0 diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-seama-header b/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-seama-header new file mode 100644 index 0000000..000b773 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-seama-header @@ -0,0 +1,21 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +. /lib/ar71xx.sh + +fix_seama_header() { + local part=$1 + + mtd fixseama $part +} + +board=$(ar71xx_board_name) + +case "$board" in +mynet-n600 | \ +mynet-n750) + fix_seama_header kernel + ;; +esac diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-trx-header b/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-trx-header new file mode 100644 index 0000000..1bfd525 --- /dev/null +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/09_fix-trx-header @@ -0,0 +1,19 @@ +#!/bin/sh +# +# Copyright (C) 2010 OpenWrt.org +# + +. /lib/ar71xx.sh + +board=$(ar71xx_board_name) + +fixtrx() { + mtd -o 32 fixtrx firmware +} + +case "$board" in +mynet-rext |\ +wrt160nl) + fixtrx + ;; +esac diff --git a/target/linux/ar71xx/base-files/lib/ar71xx.sh b/target/linux/ar71xx/base-files/lib/ar71xx.sh new file mode 100755 index 0000000..5f02e4e --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh @@ -0,0 +1,1002 @@ +#!/bin/sh +# +# Copyright (C) 2009-2011 OpenWrt.org +# + +AR71XX_BOARD_NAME= +AR71XX_MODEL= + +ar71xx_get_mtd_offset_size_format() { + local mtd="$1" + local offset="$2" + local size="$3" + local format="$4" + local dev + + dev=$(find_mtd_part $mtd) + [ -z "$dev" ] && return + + dd if=$dev bs=1 skip=$offset count=$size 2>/dev/null | hexdump -v -e "1/1 \"$format\"" +} + +ar71xx_get_mtd_part_magic() { + local mtd="$1" + ar71xx_get_mtd_offset_size_format "$mtd" 0 4 %02x +} + +wndr3700_board_detect() { + local machine="$1" + local magic + local name + + name="wndr3700" + + magic="$(ar71xx_get_mtd_part_magic firmware)" + case $magic in + "33373030") + machine="NETGEAR WNDR3700" + ;; + "33373031") + # Use awk to remove everything after the first zero byte + model="$(ar71xx_get_mtd_offset_size_format art 41 32 %c | LC_CTYPE=C awk -v 'FS=[^[:print:]]' '{print $1; exit}')" + case $model in + $'\xff'*) + if [ "${model:24:1}" = 'N' ]; then + machine="NETGEAR WNDRMAC" + else + machine="NETGEAR WNDR3700v2" + fi + ;; + '29763654+16+64'*) + machine="NETGEAR ${model:14}" + ;; + '29763654+16+128'*) + machine="NETGEAR ${model:15}" + ;; + *) + # Unknown ID + machine="NETGEAR $model" + esac + esac + + AR71XX_BOARD_NAME="$name" + AR71XX_MODEL="$machine" +} + +cybertan_get_hw_magic() { + local part + + part=$(find_mtd_part firmware) + [ -z "$part" ] && return 1 + + dd bs=8 count=1 skip=0 if=$part 2>/dev/null | hexdump -v -n 8 -e '1/1 "%02x"' +} + +tplink_get_hwid() { + local part + + part=$(find_mtd_part firmware) + [ -z "$part" ] && return 1 + + dd if=$part bs=4 count=1 skip=16 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_get_mid() { + local part + + part=$(find_mtd_part firmware) + [ -z "$part" ] && return 1 + + dd if=$part bs=4 count=1 skip=17 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_board_detect() { + local model="$1" + local hwid + local hwver + + hwid=$(tplink_get_hwid) + mid=$(tplink_get_mid) + hwver=${hwid:6:2} + hwver="v${hwver#0}" + + case "$hwid" in + "015000"*) + model="EasyLink EL-M150" + ;; + "015300"*) + model="EasyLink EL-MINI" + ;; + "044401"*) + model="ANTMINER-S1" + ;; + "044403"*) + model="ANTMINER-S3" + ;; + "120000"*) + model="MERCURY MAC1200R" + ;; + "3C0001"*) + model="OOLITE" + ;; + "3C0002"*) + model="MINIBOX_V1" + ;; + "070300"*) + model="TP-Link TL-WR703N" + ;; + "071000"*) + model="TP-Link TL-WR710N" + ;; + "072001"*) + model="TP-Link TL-WR720N" + ;; + "070100"*) + model="TP-Link TL-WA701N/ND" + ;; + "073000"*) + model="TP-Link TL-WA730RE" + ;; + "074000"*) + model="TP-Link TL-WR740N/ND" + ;; + "074100"*) + model="TP-Link TL-WR741N/ND" + ;; + "074300"*) + model="TP-Link TL-WR743N/ND" + ;; + "075000"*) + model="TP-Link TL-WA750RE" + ;; + "721000"*) + model="TP-Link TL-WA7210N" + ;; + "751000"*) + model="TP-Link TL-WA7510N" + ;; + "080100"*) + model="TP-Link TL-WA801N/ND" + ;; + "083000"*) + model="TP-Link TL-WA830RE" + + if [ "$hwver" = 'v10' ]; then + hwver='v1' + fi + ;; + "084100"*) + model="TP-Link TL-WR841N/ND" + ;; + "084200"*) + model="TP-Link TL-WR842N/ND" + ;; + "084300"*) + model="TP-Link TL-WR843N/ND" + ;; + "085000"*) + model="TP-Link TL-WA850RE" + ;; + "086000"*) + model="TP-Link TL-WA860RE" + ;; + "090100"*) + model="TP-Link TL-WA901N/ND" + ;; + "094100"*) + if [ "$hwid" = "09410002" -a "$mid" = "00420001" ]; then + model="Rosewill RNX-N360RT" + hwver="" + else + model="TP-Link TL-WR941N/ND" + fi + ;; + "104100"*) + model="TP-Link TL-WR1041N/ND" + ;; + "104300"*) + model="TP-Link TL-WR1043N/ND" + ;; + "254300"*) + model="TP-Link TL-WR2543N/ND" + ;; + "001001"*) + model="TP-Link TL-MR10U" + ;; + "001101"*) + model="TP-Link TL-MR11U" + ;; + "001201"*) + model="TP-Link TL-MR12U" + ;; + "001301"*) + model="TP-Link TL-MR13U" + ;; + "302000"*) + model="TP-Link TL-MR3020" + ;; + "304000"*) + model="TP-Link TL-MR3040" + ;; + "322000"*) + model="TP-Link TL-MR3220" + ;; + "342000"*) + model="TP-Link TL-MR3420" + ;; + "332000"*) + model="TP-Link TL-WDR3320" + ;; + "350000"*) + model="TP-Link TL-WDR3500" + ;; + "360000"*) + model="TP-Link TL-WDR3600" + ;; + "430000"*) + model="TP-Link TL-WDR4300" + ;; + "430080"*) + iw reg set IL + model="TP-Link TL-WDR4300 (IL)" + ;; + "431000"*) + model="TP-Link TL-WDR4310" + ;; + "49000002") + model="TP-Link TL-WDR4900" + ;; + "65000002") + model="TP-Link TL-WDR6500" + ;; + "453000"*) + model="MERCURY MW4530R" + ;; + "934100"*) + model="NC-LINK SMART-300" + ;; + "c50000"*) + model="TP-Link Archer C5" + ;; + "750000"*|\ + "c70000"*) + model="TP-Link Archer C7" + ;; + *) + hwver="" + ;; + esac + + AR71XX_MODEL="$model $hwver" +} + +tplink_pharos_get_model_string() { + local part + part=$(find_mtd_part 'product-info') + [ -z "$part" ] && return 1 + + # The returned string will end with \r\n, but we don't remove it here + # to simplify matching against it in the sysupgrade image check + dd if=$part bs=1 skip=4360 2>/dev/null | head -n 1 +} + +tplink_pharos_board_detect() { + local model_string="$(tplink_pharos_get_model_string | tr -d '\r')" + local oIFS="$IFS"; IFS=":"; set -- $model_string; IFS="$oIFS" + local model + + case "$1" in + 'CPE210(TP-LINK|UN|N300-2)') + model='TP-Link CPE210' + ;; + 'CPE220(TP-LINK|UN|N300-2)') + model='TP-Link CPE220' + ;; + 'CPE510(TP-LINK|UN|N300-5)') + model='TP-Link CPE510' + ;; + 'CPE520(TP-LINK|UN|N300-5)') + model='TP-Link CPE520' + ;; + esac + + [ -n "$model" ] && AR71XX_MODEL="$model v$2" +} + +gl_inet_board_detect() { + local size="$(mtd_get_part_size 'firmware')" + + case "$size" in + 8192000) + AR71XX_MODEL='GL-iNet 6408A v1' + ;; + 16580608) + AR71XX_MODEL='GL-iNet 6416A v1' + ;; + esac +} + +ar71xx_board_detect() { + local machine + local name + + machine=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /machine/ {print $2}' /proc/cpuinfo) + + case "$machine" in + *"Oolite V1.0") + name="oolite" + ;; + *"AC1750DB") + name="f9k1115v2" + ;; + *"AirGateway") + name="airgateway" + ;; + *"AirGateway Pro") + name="airgatewaypro" + ;; + *"AirRouter") + name="airrouter" + ;; + *"ALFA Network AP96") + name="alfa-ap96" + ;; + *"ALFA Network N2/N5") + name="alfa-nx" + ;; + *ALL0258N) + name="all0258n" + ;; + *ALL0305) + name="all0305" + ;; + *ALL0315N) + name="all0315n" + ;; + *Antminer-S1) + name="antminer-s1" + ;; + *Antminer-S3) + name="antminer-s3" + ;; + *AP113) + name="ap113" + ;; + *AP121) + name="ap121" + ;; + *AP121-MINI) + name="ap121-mini" + ;; + *"AP132 reference board") + name="ap132" + ;; + *"AP136-010 reference board") + name="ap136-010" + ;; + *"AP136-020 reference board") + name="ap136-020" + ;; + *"AP135-020 reference board") + name="ap135-020" + ;; + *"AP143 reference board") + name="ap143" + ;; + *"AP147-010 reference board") + name="ap147-010" + ;; + *"AP152 reference board") + name="ap152" + ;; + *AP81) + name="ap81" + ;; + *AP83) + name="ap83" + ;; + *"Archer C5") + name="archer-c5" + ;; + *"Archer C7") + name="archer-c7" + ;; + *"Atheros AP96") + name="ap96" + ;; + *AW-NR580) + name="aw-nr580" + ;; + *CAP4200AG) + name="cap4200ag" + ;; + *"COMFAST CF-E316N v2") + name="cf-e316n-v2" + ;; + *"CPE210/220/510/520") + name="cpe510" + tplink_pharos_board_detect + ;; + *"DB120 reference board") + name="db120" + ;; + *"DGL-5500 rev. A1") + name="dgl-5500-a1" + ;; + *"DHP-1565 rev. A1") + name="dhp-1565-a1" + ;; + *"DIR-505 rev. A1") + name="dir-505-a1" + ;; + *"DIR-600 rev. A1") + name="dir-600-a1" + ;; + *"DIR-615 rev. E1") + name="dir-615-e1" + ;; + *"DIR-615 rev. E4") + name="dir-615-e4" + ;; + *"DIR-615 rev. I1") + name="dir-615-i1" + ;; + *"DIR-825 rev. B1") + name="dir-825-b1" + ;; + *"DIR-825 rev. C1") + name="dir-825-c1" + ;; + *"DIR-835 rev. A1") + name="dir-835-a1" + ;; + *"dLAN pro 500 Wireless+") + name="dlan-pro-500-wp" + ;; + *"dLAN pro 1200+ WiFi ac") + name="dlan-pro-1200-ac" + ;; + *"Dragino v2") + name="dragino2" + ;; + *"EAP300 v2") + name="eap300v2" + ;; + *EAP7660D) + name="eap7660d" + ;; + *EL-M150) + name="el-m150" + ;; + *EL-MINI) + name="el-mini" + ;; + *"GL-CONNECT INET v1") + name="gl-inet" + gl_inet_board_detect + ;; + *"EnGenius EPG5000") + name="epg5000" + ;; + *"EnGenius ESR1750") + name="esr1750" + ;; + *"EnGenius ESR900") + name="esr900" + ;; + *JA76PF) + name="ja76pf" + ;; + *JA76PF2) + name="ja76pf2" + ;; + *"Bullet M") + name="bullet-m" + ;; + *"Loco M XW") + name="loco-m-xw" + ;; + *"Nanostation M") + name="nanostation-m" + ;; + *"Nanostation M XW") + name="nanostation-m-xw" + ;; + *JWAP003) + name="jwap003" + ;; + *"Hornet-UB") + local size + size=$(awk '/firmware/ { print $2 }' /proc/mtd) + + if [ "x$size" = "x00790000" ]; then + name="hornet-ub" + fi + + if [ "x$size" = "x00f90000" ]; then + name="hornet-ub-x2" + fi + ;; + *LS-SR71) + name="ls-sr71" + ;; + *"MAC1200R") + name="mc-mac1200r" + ;; + *"MiniBox V1.0") + name="minibox-v1" + ;; + *MR12) + name="mr12" + ;; + *MR16) + name="mr16" + ;; + *MR600v2) + name="mr600v2" + ;; + *MR1750) + name="mr1750" + ;; + *MR600) + name="mr600" + ;; + *MR900) + name="mr900" + ;; + *MR900v2) + name="mr900v2" + ;; + *"My Net N600") + name="mynet-n600" + ;; + *"My Net N750") + name="mynet-n750" + ;; + *"WD My Net Wi-Fi Range Extender") + name="mynet-rext" + ;; + *MZK-W04NU) + name="mzk-w04nu" + ;; + *MZK-W300NH) + name="mzk-w300nh" + ;; + *"NBG460N/550N/550NH") + name="nbg460n_550n_550nh" + ;; + *"Zyxel NBG6716") + name="nbg6716" + ;; + *OM2P) + name="om2p" + ;; + *OM2Pv2) + name="om2pv2" + ;; + *"OM2P HS") + name="om2p-hs" + ;; + *"OM2P HSv2") + name="om2p-hsv2" + ;; + *"OM2P LC") + name="om2p-lc" + ;; + *OM5P) + name="om5p" + ;; + *"OM5P AN") + name="om5p-an" + ;; + *"Onion Omega") + name="onion-omega" + ;; + *PB42) + name="pb42" + ;; + *"PB44 reference board") + name="pb44" + ;; + *PB92) + name="pb92" + ;; + *"Qihoo 360 C301") + name="qihoo-c301" + ;; + *"RouterBOARD 411/A/AH") + name="rb-411" + ;; + *"RouterBOARD 411U") + name="rb-411u" + ;; + *"RouterBOARD 433/AH") + name="rb-433" + ;; + *"RouterBOARD 433UAH") + name="rb-433u" + ;; + *"RouterBOARD 435G") + name="rb-435g" + ;; + *"RouterBOARD 450") + name="rb-450" + ;; + *"RouterBOARD 450G") + name="rb-450g" + ;; + *"RouterBOARD 493/AH") + name="rb-493" + ;; + *"RouterBOARD 493G") + name="rb-493g" + ;; + *"RouterBOARD 750") + name="rb-750" + ;; + *"RouterBOARD 750GL") + name="rb-750gl" + ;; + *"RouterBOARD 751") + name="rb-751" + ;; + *"RouterBOARD 751G") + name="rb-751g" + ;; + *"RouterBOARD 911G-2HPnD") + name="rb-911g-2hpnd" + ;; + *"RouterBOARD 911G-5HPnD") + name="rb-911g-5hpnd" + ;; + *"RouterBOARD 911G-5HPacD") + name="rb-911g-5hpacd" + ;; + *"RouterBOARD 912UAG-2HPnD") + name="rb-912uag-2hpnd" + ;; + *"RouterBOARD 912UAG-5HPnD") + name="rb-912uag-5hpnd" + ;; + *"RouterBOARD 951G-2HnD") + name="rb-951g-2hnd" + ;; + *"RouterBOARD 951Ui-2HnD") + name="rb-951ui-2hnd" + ;; + *"RouterBOARD 2011L") + name="rb-2011l" + ;; + *"RouterBOARD 2011UAS") + name="rb-2011uas" + ;; + *"RouterBOARD 2011UiAS") + name="rb-2011uias" + ;; + *"RouterBOARD 2011UAS-2HnD") + name="rb-2011uas-2hnd" + ;; + *"RouterBOARD 2011UiAS-2HnD") + name="rb-2011uias-2hnd" + ;; + *"RouterBOARD SXT Lite2") + name="rb-sxt2n" + ;; + *"RouterBOARD SXT Lite5") + name="rb-sxt5n" + ;; + *"Rocket M") + name="rocket-m" + ;; + *"Rocket M TI") + name="rocket-m-ti" + ;; + *"Rocket M XW") + name="rocket-m-xw" + ;; + *RouterStation) + name="routerstation" + ;; + *"RouterStation Pro") + name="routerstation-pro" + ;; + *RW2458N) + name="rw2458n" + ;; + *"SMART-300") + name="smart-300" + ;; + "Smart Electronics Black Swift board"*) + name="bsb" + ;; + *TEW-632BRP) + name="tew-632brp" + ;; + *TEW-673GRU) + name="tew-673gru" + ;; + *TEW-712BR) + name="tew-712br" + ;; + *TEW-732BR) + name="tew-732br" + ;; + *"TL-WR1041N v2") + name="tl-wr1041n-v2" + ;; + *TL-WR1043ND) + name="tl-wr1043nd" + ;; + *"TL-WR1043ND v2") + name="tl-wr1043nd-v2" + ;; + *TL-WR2543N*) + name="tl-wr2543n" + ;; + *"DIR-615 rev. C1") + name="dir-615-c1" + ;; + *TL-MR3020) + name="tl-mr3020" + ;; + *TL-MR3040) + name="tl-mr3040" + ;; + *"TL-MR3040 v2") + name="tl-mr3040-v2" + ;; + *TL-MR3220) + name="tl-mr3220" + ;; + *"TL-MR3220 v2") + name="tl-mr3220-v2" + ;; + *TL-MR3420) + name="tl-mr3420" + ;; + *"TL-MR3420 v2") + name="tl-mr3420-v2" + ;; + *"TL-WA701ND v2") + name="tl-wa701nd-v2" + ;; + *"TL-WA7210N v2") + name="tl-wa7210n-v2" + ;; + *TL-WA750RE) + name="tl-wa750re" + ;; + *"TL-WA7510N v1") + name="tl-wa7510n" + ;; + *TL-WA850RE) + name="tl-wa850re" + ;; + *TL-WA860RE) + name="tl-wa860re" + ;; + *"TL-WA830RE v2") + name="tl-wa830re-v2" + ;; + *"TL-WA801ND v2") + name="tl-wa801nd-v2" + ;; + *TL-WA901ND) + name="tl-wa901nd" + ;; + *"TL-WA901ND v2") + name="tl-wa901nd-v2" + ;; + *"TL-WA901ND v3") + name="tl-wa901nd-v3" + ;; + *"TL-WDR3320 v2") + name="tl-wdr3320-v2" + ;; + *"TL-WDR3500") + name="tl-wdr3500" + ;; + *"TL-WDR3600/4300/4310") + name="tl-wdr4300" + ;; + *"TL-WDR4900 v2") + name="tl-wdr4900-v2" + ;; + *"TL-WDR6500 v2") + name="tl-wdr6500-v2" + ;; + *TL-WR741ND) + name="tl-wr741nd" + ;; + *"TL-WR741ND v4") + name="tl-wr741nd-v4" + ;; + *"TL-WR841N v1") + name="tl-wr841n-v1" + ;; + *"TL-WR841N/ND v7") + name="tl-wr841n-v7" + ;; + *"TL-WR841N/ND v8") + name="tl-wr841n-v8" + ;; + *"TL-WR841N/ND v9") + name="tl-wr841n-v9" + ;; + *"TL-WR842N/ND v2") + name="tl-wr842n-v2" + ;; + *TL-WR941ND) + name="tl-wr941nd" + ;; + *"TL-WR941N/ND v5") + name="tl-wr941nd-v5" + ;; + *"TL-WR703N v1") + name="tl-wr703n" + ;; + *"TL-WR710N v1") + name="tl-wr710n" + ;; + *"TL-WR720N"*) + name="tl-wr720n-v3" + ;; + *"TL-MR10U") + name="tl-mr10u" + ;; + *"TL-MR11U") + name="tl-mr11u" + ;; + *"TL-MR12U") + name="tl-mr12u" + ;; + *"TL-MR13U v1") + name="tl-mr13u" + ;; + *"Tube2H") + name="tube2h" + ;; + *UniFi) + name="unifi" + ;; + *"UniFi AP Pro") + name="uap-pro" + ;; + "WeIO"*) + name="weio" + ;; + *WHR-G301N) + name="whr-g301n" + ;; + *WHR-HP-GN) + name="whr-hp-gn" + ;; + *WLAE-AG300N) + name="wlae-ag300n" + ;; + *"UniFiAP Outdoor") + name="unifi-outdoor" + ;; + *"UniFiAP Outdoor+") + name="unifi-outdoor-plus" + ;; + *WP543) + name="wp543" + ;; + *WPE72) + name="wpe72" + ;; + *WPJ344) + name="wpj344" + ;; + *WPJ531) + name="wpj531" + ;; + *WPJ558) + name="wpj558" + ;; + *WNDAP360) + name="wndap360" + ;; + *"WNDR3700/WNDR3800/WNDRMAC") + wndr3700_board_detect "$machine" + ;; + *"R6100") + name="r6100" + ;; + *"WNDR3700v4") + name="wndr3700v4" + ;; + *"WNDR4300") + name="wndr4300" + ;; + *"WNR2000 V4") + name="wnr2000-v4" + ;; + *"WNR2000 V3") + name="wnr2000-v3" + ;; + *WNR2000) + name="wnr2000" + ;; + *WNR2200) + name="wnr2200" + ;; + *"WNR612 V2") + name="wnr612-v2" + ;; + *"WNR1000 V2") + name="wnr1000-v2" + ;; + *WRT160NL) + name="wrt160nl" + ;; + *WRT400N) + name="wrt400n" + ;; + *"WZR-450HP2") + name="wzr-450hp2" + ;; + *"WZR-HP-AG300H/WZR-600DHP") + name="wzr-hp-ag300h" + ;; + *WZR-HP-G300NH) + name="wzr-hp-g300nh" + ;; + *WZR-HP-G450H) + name="wzr-hp-g450h" + ;; + *WZR-HP-G300NH2) + name="wzr-hp-g300nh2" + ;; + *WHR-HP-G300N) + name="whr-hp-g300n" + ;; + *ZCN-1523H-2) + name="zcn-1523h-2" + ;; + *ZCN-1523H-5) + name="zcn-1523h-5" + ;; + *EmbWir-Dorin) + name="ew-dorin" + ;; + *EmbWir-Dorin-Router) + name="ew-dorin-router" + ;; + "8devices Carambola2"*) + name="carambola2" + ;; + *"Sitecom WLR-8100") + name="wlr8100" + ;; + *"BHU BXU2000n-2 rev. A1") + name="bxu2000n-2-a1" + ;; + *"HiWiFi HC6361") + name="hiwifi-hc6361" + ;; + esac + + [ -z "$AR71XX_MODEL" ] && [ "${machine:0:8}" = 'TP-LINK ' ] && \ + tplink_board_detect "$machine" + + [ -z "$name" ] && name="unknown" + + [ -z "$AR71XX_BOARD_NAME" ] && AR71XX_BOARD_NAME="$name" + [ -z "$AR71XX_MODEL" ] && AR71XX_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$AR71XX_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$AR71XX_MODEL" > /tmp/sysinfo/model +} + +ar71xx_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh b/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh new file mode 100644 index 0000000..ff5407a --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/03_preinit_do_ar71xx.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_ar71xx() { + . /lib/ar71xx.sh + + ar71xx_board_detect +} + +boot_hook_add preinit_main do_ar71xx diff --git a/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx b/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx new file mode 100644 index 0000000..92b3765 --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/05_set_iface_mac_ar71xx @@ -0,0 +1,48 @@ +# +# Copyright (C) 2009 OpenWrt.org +# + +. /lib/ar71xx.sh + +fetch_mac_from_mtd() { + local mtd_part=$1 + local lan_env=$2 + local wan_env=$3 + local mtd mac + + mtd=$(grep $mtd_part /proc/mtd | cut -d: -f1) + [ -z $mtd ] && return + + mac=$(grep $lan_env /dev/$mtd | cut -d= -f2) + [ ! -z $mac ] && ifconfig eth0 hw ether $mac 2>/dev/null + + mac=$(grep $wan_env /dev/$mtd | cut -d= -f2) + [ ! -z $mac ] && ifconfig eth1 hw ether $mac 2>/dev/null +} + +preinit_set_mac_address() { + case $(ar71xx_board_name) in + dir-615-c1) + fetch_mac_from_mtd config lan_mac wan_mac + echo 1 > /sys/class/leds/dir-615-c1:green:wancpu/brightness + ;; + dir-615-i1) + fetch_mac_from_mtd nvram sys_lan_mac sys_wan_mac + ;; + r6100) + mac_lan=$(mtd_get_mac_binary caldata 0) + [ -n "$mac_lan" ] && ifconfig eth1 hw ether "$mac_lan" + mac_wan=$(mtd_get_mac_binary caldata 6) + [ -n "$mac_wan" ] && ifconfig eth0 hw ether "$mac_wan" + ;; + tew-632brp) + fetch_mac_from_mtd config lan_mac wan_mac + ;; + wrt160nl) + fetch_mac_from_mtd nvram lan_hwaddr wan_hwaddr + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address + diff --git a/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx b/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx new file mode 100644 index 0000000..d214e9b --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/05_set_preinit_iface_ar71xx @@ -0,0 +1,55 @@ +#!/bin/sh + +# +# Copyright (C) 2009 OpenWrt.org +# + +. /lib/ar71xx.sh + +set_preinit_iface() { + case $(ar71xx_board_name) in + alfa-ap96 |\ + alfa-nx |\ + ap135-020 |\ + ap136-020 |\ + ap147-010 |\ + ap83 |\ + archer-c5 |\ + archer-c7 |\ + dir-505-a1 |\ + gl-inet |\ + jwap003 |\ + pb42 |\ + pb44 |\ + rb-433 |\ + rb-433u |\ + rb-435g |\ + rb-450 |\ + rb-450g |\ + routerstation |\ + routerstation-pro |\ + smart-300 |\ + tl-mr3420-v2 |\ + tl-wdr4900-v2 |\ + tl-wr1043nd-v2 |\ + tl-wr710n |\ + tl-wr720n-v3 |\ + tl-wr841n-v8 |\ + tl-wr842n-v2 |\ + wnr2000-v3 |\ + wnr2200 |\ + wnr612-v2 |\ + wnr1000-v2 |\ + wpe72) + ifname=eth1 + ;; + *) + ifname=eth0 + ;; + esac +} + +boot_hook_add preinit_main set_preinit_iface + + + diff --git a/target/linux/ar71xx/base-files/lib/preinit/82_patch_ath10k b/target/linux/ar71xx/base-files/lib/preinit/82_patch_ath10k new file mode 100644 index 0000000..4da611a --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/preinit/82_patch_ath10k @@ -0,0 +1,51 @@ +#!/bin/sh + +. /lib/functions/system.sh +. /lib/ar71xx.sh + + +do_patch_ath10k_firmware() { + local firmware_file="/lib/firmware/ath10k/QCA988X/hw2.0/firmware-5.bin" + + # bail out if firmware does not exist + [ -f "$firmware_file" ] || { + return + } + + local firmware_md5_orig="36768dc68572b3f2660211e20e89f558" + local firmware_md5_current="$(md5sum $firmware_file)" + local firmware_md5_current="${firmware_md5_current%% *}" + + # verify md5sum before patching + [ "$firmware_md5_orig" != "$firmware_md5_current" ] || { + return + } + + # some boards have bogus mac in otp, patch the default mac in the firmware + case $(ar71xx_board_name) in + dgl-5500-a1) + local mac + mac=$(mtd_get_mac_ascii nvram wlan1_mac) + + cp $firmware_file /tmp/ath10k-firmware.bin + macaddr_2bin $mac | dd of=/tmp/ath10k-firmware.bin \ + conv=notrunc bs=1 seek=276 count=6 + + ;; + esac + [ -f /tmp/ath10k-firmware.bin ] || { + return + } + cp /tmp/ath10k-firmware.bin $firmware_file + rm /tmp/ath10k-firmware.bin +} + +check_patch_ath10k_firmware() { + case $(ar71xx_board_name) in + dgl-5500-a1) + do_patch_ath10k_firmware + ;; + esac +} + +boot_hook_add preinit_main check_patch_ath10k_firmware diff --git a/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh b/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh new file mode 100644 index 0000000..98b368d --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/allnet.sh @@ -0,0 +1,162 @@ +# The U-Boot loader of the some Allnet devices requires image sizes and +# checksums to be provided in the U-Boot environment. +# In case the check fails during boot, a failsafe-system is started to provide +# a minimal web-interface for flashing a new firmware. + +# make sure we got uboot-envtools and fw_env.config copied over to the ramfs +# create /var/lock for the lock "fw_setenv.lock" of fw_setenv +platform_add_ramfs_ubootenv() { + [ -e /usr/sbin/fw_printenv ] && install_bin /usr/sbin/fw_printenv /usr/sbin/fw_setenv + [ -e /etc/fw_env.config ] && install_file /etc/fw_env.config + mkdir -p $RAM_ROOT/var/lock +} +append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv + +# determine size of the main firmware partition +platform_get_firmware_size() { + local dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + firmware) + printf "%d" "0x$size" + break + ;; + esac + done < /proc/mtd +} + +# get the first 4 bytes (magic) of a given file starting at offset in hex format +get_magic_long_at() { + dd if="$1" skip=$(( $CI_BLKSZ / 4 * $2 )) bs=4 count=1 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +get_filesize() { + wc -c "$1" | while read image_size _n ; do echo $image_size ; break; done +} + +# scan through the update image pages until matching a magic +platform_get_offset() { + offsetcount=0 + magiclong="x" + if [ -n "$3" ]; then + offsetcount=$3 + fi + while magiclong=$( get_magic_long_at "$1" "$offsetcount" ) && [ -n "$magiclong" ]; do + case "$magiclong" in + "2705"*) + # U-Boot image magic + if [ "$2" = "uImage" ]; then + echo $offsetcount + return + fi + ;; + "68737173"|"73717368") + # SquashFS + if [ "$2" = "rootfs" ]; then + echo $offsetcount + return + fi + ;; + "deadc0de"|"19852003") + # JFFS2 empty page + if [ "$2" = "rootfs-data" ]; then + echo $offsetcount + return + fi + ;; + esac + offsetcount=$(( $offsetcount + 1 )) + done +} + +platform_check_image_allnet() { + local fw_printenv=/usr/sbin/fw_printenv + [ ! -n "$fw_printenv" -o ! -x "$fw_printenv" ] && { + echo "Please install uboot-envtools!" + return 1 + } + + [ ! -r "/etc/fw_env.config" ] && { + echo "/etc/fw_env.config is missing" + return 1 + } + + local image_size=$( get_filesize "$1" ) + local firmware_size=$( platform_get_firmware_size ) + [ $image_size -ge $firmware_size ] && + { + echo "upgrade image is too big (${image_size}b > ${firmware_size}b)" + } + + local vmlinux_blockoffset=$( platform_get_offset "$1" uImage ) + [ -z $vmlinux_blockoffset ] && { + echo "vmlinux-uImage not found" + return 1 + } + + local rootfs_blockoffset=$( platform_get_offset "$1" rootfs "$vmlinux_blockoffset" ) + [ -z $rootfs_blockoffset ] && { + echo "missing rootfs" + return 1 + } + + local data_blockoffset=$( platform_get_offset "$1" rootfs-data "$rootfs_blockoffset" ) + [ -z $data_blockoffset ] && { + echo "rootfs doesn't have JFFS2 end marker" + return 1 + } + + return 0 +} + +platform_do_upgrade_allnet() { + local firmware_base_addr=$( printf "%d" "$1" ) + local vmlinux_blockoffset=$( platform_get_offset "$2" uImage ) + if [ ! -n "$vmlinux_blockoffset" ]; then + echo "can't determine uImage offset" + return 1 + fi + local rootfs_blockoffset=$( platform_get_offset "$2" rootfs $(( $vmlinux_blockoffset + 1 )) ) + local vmlinux_offset=$(( $vmlinux_blockoffset * $CI_BLKSZ )) + local vmlinux_addr=$(( $firmware_base_addr + $vmlinux_offset )) + local vmlinux_hexaddr=0x$( printf "%08x" "$vmlinux_addr" ) + if [ ! -n "$rootfs_blockoffset" ]; then + echo "can't determine rootfs offset" + return 1 + fi + local rootfs_offset=$(( $rootfs_blockoffset * $CI_BLKSZ )) + local rootfs_addr=$(( $firmware_base_addr + $rootfs_offset )) + local rootfs_hexaddr=0x$( printf "%08x" "$rootfs_addr" ) + local vmlinux_blockcount=$(( $rootfs_blockoffset - $vmlinux_blockoffset )) + local vmlinux_size=$(( $rootfs_offset - $vmlinux_offset )) + local vmlinux_hexsize=0x$( printf "%08x" "$vmlinux_size" ) + local data_blockoffset=$( platform_get_offset "$2" rootfs-data $(( $rootfs_blockoffset + 1 )) ) + if [ ! -n "$data_blockoffset" ]; then + echo "can't determine rootfs size" + return 1 + fi + local data_offset=$(( $data_blockoffset * $CI_BLKSZ )) + local rootfs_blockcount=$(( $data_blockoffset - $rootfs_blockoffset )) + local rootfs_size=$(( $data_offset - $rootfs_offset )) + local rootfs_hexsize=0x$( printf "%08x" "$rootfs_size" ) + + local rootfs_md5=$( dd if="$2" bs=$CI_BLKSZ skip=$rootfs_blockoffset count=$rootfs_blockcount 2>/dev/null | md5sum -); rootfs_md5="${rootfs_md5%% *}" + local vmlinux_md5=$( dd if="$2" bs=$CI_BLKSZ skip=$vmlinux_blockoffset count=$vmlinux_blockcount 2>/dev/null | md5sum -); vmlinux_md5="${vmlinux_md5%% *}" + # this needs a recent version of uboot-envtools! + cat >/tmp/fw_env_upgrade </dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +dir825b_is_caldata_valid() { + local mtddev=$1 + local magic + + magic=$(get_magic_at $mtddev 4096) + [ "$magic" != "a55a" ] && return 0 + + magic=$(get_magic_at $mtddev 20480) + [ "$magic" != "a55a" ] && return 0 + + return 1 +} + +dir825b_copy_caldata() { + local cal_src=$1 + local cal_dst=$2 + local mtd_src + local mtd_dst + local md5_src + local md5_dst + + mtd_src=$(find_mtd_part $cal_src) + [ -z "$mtd_src" ] && { + echo "no $cal_src partition found" + return 1 + } + + mtd_dst=$(find_mtd_part $cal_dst) + [ -z "$mtd_dst" ] && { + echo "no $cal_dst partition found" + return 1 + } + + dir825b_is_caldata_valid "$mtd_src" && { + echo "no valid calibration data found in $cal_src" + return 1 + } + + dir825b_is_caldata_valid "$mtd_dst" && { + echo "Copying calibration data from $cal_src to $cal_dst..." + dd if="$mtd_src" 2>/dev/null | mtd -q -q write - "$cal_dst" + } + + md5_src=$(md5sum "$mtd_src") && md5_src="${md5_src%% *}" + md5_dst=$(md5sum "$mtd_dst") && md5_dst="${md5_dst%% *}" + + [ "$md5_src" != "$md5_dst" ] && { + echo "calibration data mismatch $cal_src:$md5_src $cal_dst:$md5_dst" + return 1 + } + + return 0 +} + +dir825b_do_upgrade_combined() { + local fw_part=$1 + local fw_file=$2 + local fw_mtd=$(find_mtd_part $fw_part) + local fw_length=0x$(dd if="$fw_file" bs=2 skip=1 count=4 2>/dev/null) + local fw_blocks=$(($fw_length / 65536)) + + if [ -n "$fw_mtd" ] && [ ${fw_blocks:-0} -gt 0 ]; then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + sync + dd if="$fw_file" bs=64k skip=1 count=$fw_blocks 2>/dev/null | \ + mtd $append write - "$fw_part" + fi +} + +dir825b_check_image() { + local magic="$(get_magic_long "$1")" + local fw_mtd=$(find_mtd_part "firmware_orig") + + case "$magic" in + "27051956") + ;; + "43493030") + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=64k skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + local fw_len=$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local fw_part_len=$(mtd_get_part_size "firmware") + + if [ -z "$fw_mtd" ]; then + ask_bool 0 "Do you have a backup of the caldata partition?" || { + echo "Warning, please make sure that you have a backup of the caldata partition." + echo "Once you have that, use 'sysupgrade -i' for upgrading to the 'fat' firmware." + return 1 + } + fi + + if [ -z "$md5_img" -o -z "$md5_chk" ]; then + echo "Unable to get image checksums. Maybe you are using a streamed image?" + return 1 + fi + + if [ "$md5_img" != "$md5_chk" ]; then + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + + fw_len=$((0x$fw_len)) + fw_part_len=${fw_part_len:-0} + + if [ $fw_part_len -lt $fw_len ]; then + echo "The upgrade image is too big (size:$fw_len available:$fw_part_len)" + return 1 + fi + ;; + *) + echo "Unsupported image format." + return 1 + ;; + esac + + return 0 +} + +platform_do_upgrade_dir825b() { + local magic="$(get_magic_long "$1")" + local fw_mtd=$(find_mtd_part "firmware_orig") + + case "$magic" in + "27051956") + if [ -n "$fw_mtd" ]; then + # restore calibration data before downgrading to + # the normal image + dir825b_copy_caldata "caldata" "caldata_orig" || { + echo "unable to restore calibration data" + exit 1 + } + PART_NAME="firmware_orig" + else + PART_NAME="firmware" + fi + default_do_upgrade "$ARGV" + ;; + "43493030") + if [ -z "$fw_mtd" ]; then + # backup calibration data before upgrading to the + # fat image + dir825b_copy_caldata "caldata" "caldata_copy" || { + echo "unable to backup calibration data" + exit 1 + } + fi + dir825b_do_upgrade_combined "firmware" "$ARGV" + ;; + esac +} diff --git a/target/linux/ar71xx/base-files/lib/upgrade/openmesh.sh b/target/linux/ar71xx/base-files/lib/upgrade/openmesh.sh new file mode 100644 index 0000000..9ca0f5b --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/openmesh.sh @@ -0,0 +1,218 @@ +# The U-Boot loader of the OpenMesh devices requires image sizes and +# checksums to be provided in the U-Boot environment. +# The OpenMesh devices come with 2 main partitions - while one is active +# sysupgrade will flash the other. The boot order is changed to boot the +# newly flashed partition. If the new partition can't be booted due to +# upgrade failures the previously used partition is loaded. + +trim() +{ + echo $1 +} + +cfg_value_get() +{ + local cfg=$1 cfg_opt + local section=$2 our_section=0 + local param=$3 our_param= + + for cfg_opt in $cfg + do + [ "$cfg_opt" = "[$section]" ] && our_section=1 && continue + [ "$our_section" = "1" ] || continue + + our_param=$(echo ${cfg_opt%%=*}) + [ "$param" = "$our_param" ] && echo ${cfg_opt##*=} && break + done +} + +# make sure we got uboot-envtools and fw_env.config copied over to the ramfs +# create /var/lock for the lock "fw_setenv.lock" of fw_setenv +platform_add_ramfs_ubootenv() +{ + [ -e /usr/sbin/fw_printenv ] && install_bin /usr/sbin/fw_printenv /usr/sbin/fw_setenv + [ -e /etc/fw_env.config ] && install_file /etc/fw_env.config + mkdir -p $RAM_ROOT/var/lock +} +append sysupgrade_pre_upgrade platform_add_ramfs_ubootenv + +platform_check_image_openmesh() +{ + local img_magic=$1 + local img_path=$2 + local fw_printenv=/usr/sbin/fw_printenv + local img_board_target= img_num_files= i=0 + local cfg_name= kernel_name= rootfs_name= + + case "$img_magic" in + # Combined Extended Image v1 + 43453031) + img_board_target=$(trim $(dd if="$img_path" bs=4 skip=1 count=8 2>/dev/null)) + img_num_files=$(trim $(dd if="$img_path" bs=2 skip=18 count=1 2>/dev/null)) + ;; + *) + echo "Invalid image ($img_magic). Use combined extended images on this platform" + return 1 + ;; + esac + + case "$img_board_target" in + OM2P) + [ "$board" = "om2p" ] && break + [ "$board" = "om2pv2" ] && break + [ "$board" = "om2p-lc" ] && break + [ "$board" = "om2p-hs" ] && break + [ "$board" = "om2p-hsv2" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + OM5P) + [ "$board" = "om5p" ] && break + [ "$board" = "om5p-an" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + MR1750) + [ "$board" = "mr1750" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + MR600) + [ "$board" = "mr600" ] && break + [ "$board" = "mr600v2" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + MR900) + [ "$board" = "mr900" ] && break + [ "$board" = "mr900v2" ] && break + echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform" + return 1 + ;; + *) + echo "Invalid board target ($img_board_target). Use the correct image for this platform" + return 1 + ;; + esac + + [ $img_num_files -ne 3 ] && { + echo "Invalid number of embedded images ($img_num_files). Use the correct image for this platform" + return 1 + } + + cfg_name=$(trim $(dd if="$img_path" bs=2 skip=19 count=16 2>/dev/null)) + + [ "$cfg_name" != "fwupgrade.cfg" ] && { + echo "Invalid embedded config file ($cfg_name). Use the correct image for this platform" + return 1 + } + + kernel_name=$(trim $(dd if="$img_path" bs=2 skip=55 count=16 2>/dev/null)) + + [ "$kernel_name" != "kernel" ] && { + echo "Invalid embedded kernel file ($kernel_name). Use the correct image for this platform" + return 1 + } + + rootfs_name=$(trim $(dd if="$img_path" bs=2 skip=91 count=16 2>/dev/null)) + + [ "$rootfs_name" != "rootfs" ] && { + echo "Invalid embedded kernel file ($rootfs_name). Use the correct image for this platform" + return 1 + } + + [ ! -x "$fw_printenv" ] && { + echo "Please install uboot-envtools!" + return 1 + } + + [ ! -r "/etc/fw_env.config" ] && { + echo "/etc/fw_env.config is missing" + return 1 + } + + return 0 +} + +platform_do_upgrade_openmesh() +{ + local img_path=$1 img_board_target= + local kernel_start_addr= kernel_start_addr1= kernel_start_addr2= + local kernel_size= kernel_md5= + local rootfs_size= rootfs_checksize= rootfs_md5= + local kernel_bsize= total_size= + local data_offset=$((64 * 1024)) block_size= offset= + local uboot_env_upgrade="/tmp/fw_env_upgrade" + local cfg_size= kernel_size= rootfs_size= + local append="" + + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + cfg_size=$(dd if="$img_path" bs=2 skip=35 count=4 2>/dev/null) + kernel_size=$(dd if="$img_path" bs=2 skip=71 count=4 2>/dev/null) + rootfs_size=$(dd if="$img_path" bs=2 skip=107 count=4 2>/dev/null) + + img_board_target=$(trim $(dd if="$img_path" bs=4 skip=1 count=8 2>/dev/null)) + cfg_content=$(dd if="$img_path" bs=1 skip=$data_offset count=$(echo $((0x$cfg_size))) 2>/dev/null) + + case $img_board_target in + OM2P) + block_size=$((256 * 1024)) + total_size=7340032 + kernel_start_addr1=0x9f1c0000 + kernel_start_addr2=0x9f8c0000 + ;; + OM5P|MR600|MR900|MR1750) + block_size=$((64 * 1024)) + total_size=7995392 + kernel_start_addr1=0x9f0b0000 + kernel_start_addr2=0x9f850000 + ;; + esac + + kernel_md5=$(cfg_value_get "$cfg_content" "vmlinux" "md5sum") + rootfs_md5=$(cfg_value_get "$cfg_content" "rootfs" "md5sum") + rootfs_checksize=$(cfg_value_get "$cfg_content" "rootfs" "checksize") + + if [ "$((0x$kernel_size % $block_size))" = "0" ] + then + kernel_bsize=$(echo $((0x$kernel_size))) + else + kernel_bsize=$((0x$kernel_size + ($block_size - (0x$kernel_size % $block_size)))) + fi + + mtd -q erase inactive + + offset=$(echo $(($data_offset + 0x$cfg_size + 0x$kernel_size))) + dd if="$img_path" bs=1 skip=$offset count=$(echo $((0x$rootfs_size))) 2>&- | mtd -n -p $kernel_bsize $append write - "inactive" + + offset=$(echo $(($data_offset + 0x$cfg_size))) + dd if="$img_path" bs=1 skip=$offset count=$(echo $((0x$kernel_size))) 2>&- | mtd -n write - "inactive" + + rm $uboot_env_upgrade 2>&- + + if [ "$(grep 'mtd3:.*inactive' /proc/mtd)" ] + then + printf "kernel_size_1 %u\n" $(($kernel_bsize / 1024)) >> $uboot_env_upgrade + printf "rootfs_size_1 %u\n" $((($total_size - $kernel_bsize) / 1024)) >> $uboot_env_upgrade + printf "bootseq 1,2\n" >> $uboot_env_upgrade + kernel_start_addr=$kernel_start_addr1 + else + printf "kernel_size_2 %u\n" $(($kernel_bsize / 1024)) >> $uboot_env_upgrade + printf "rootfs_size_2 %u\n" $((($total_size - $kernel_bsize) / 1024)) >> $uboot_env_upgrade + printf "bootseq 2,1\n" >> $uboot_env_upgrade + kernel_start_addr=$kernel_start_addr2 + fi + + printf "vmlinux_start_addr %s\n" $kernel_start_addr >> $uboot_env_upgrade + printf "vmlinux_size 0x%s\n" $kernel_size >> $uboot_env_upgrade + printf "vmlinux_checksum %s\n" $kernel_md5 >> $uboot_env_upgrade + printf "rootfs_start_addr 0x%x\n" $(($kernel_start_addr + $kernel_bsize)) >> $uboot_env_upgrade + printf "rootfs_size %s\n" $rootfs_checksize >> $uboot_env_upgrade + printf "rootfs_checksum %s\n" $rootfs_md5 >> $uboot_env_upgrade + + fw_setenv -s $uboot_env_upgrade || { + echo "failed to update U-Boot environment" + return 1 + } +} diff --git a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000..a464fee --- /dev/null +++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,559 @@ +# +# Copyright (C) 2011 OpenWrt.org +# + +. /lib/functions/system.sh +. /lib/ar71xx.sh + +PART_NAME=firmware +RAMFS_COPY_DATA=/lib/ar71xx.sh + +CI_BLKSZ=65536 +CI_LDADR=0x80060000 + +platform_find_partitions() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + vmlinux.bin.l7|vmlinux|kernel|linux|linux.bin|rootfs|filesystem) + if [ -z "$first" ]; then + first="$name" + else + echo "$erasesize:$first:$name" + break + fi + ;; + esac + done < /proc/mtd +} + +platform_find_kernelpart() { + local part + for part in "${1%:*}" "${1#*:}"; do + case "$part" in + vmlinux.bin.l7|vmlinux|kernel|linux|linux.bin) + echo "$part" + break + ;; + esac + done +} + +platform_do_upgrade_combined() { + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}" + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local kern_blocks=$(($kern_length / $CI_BLKSZ)) + local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ)) + + if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \ + [ ${kern_blocks:-0} -gt 0 ] && \ + [ ${root_blocks:-0} -gt 0 ] && \ + [ ${erase_size:-0} -gt 0 ]; + then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + ( dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \ + dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \ + mtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions + fi +} + +tplink_get_image_hwid() { + get_image "$@" | dd bs=4 count=1 skip=16 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_get_image_boot_size() { + get_image "$@" | dd bs=4 count=1 skip=37 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_pharos_check_image() { + local magic_long="$(get_magic_long "$1")" + [ "$magic_long" != "7f454c46" ] && { + echo "Invalid image magic '$magic_long'" + return 1 + } + + local model_string="$(tplink_pharos_get_model_string)" + local line + + # Here $1 is given to dd directly instead of get_image as otherwise the skip + # will take almost a second (as dd can't seek then) + # + # This will fail if the image isn't local, but that's fine: as the + # read loop won't be executed at all, it will return true, so the image + # is accepted (loading the first 1.5M of a remote image for this check seems + # a bit extreme) + dd if="$1" bs=1 skip=1511432 count=1024 2>/dev/null | while read line; do + [ "$line" == "$model_string" ] && break + done || { + echo "Unsupported image (model not in support-list)" + return 1 + } + + return 0 +} + +seama_get_type_magic() { + get_image "$@" | dd bs=1 count=4 skip=53 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +cybertan_get_image_magic() { + get_image "$@" | dd bs=8 count=1 skip=0 2>/dev/null | hexdump -v -n 8 -e '1/1 "%02x"' +} + +cybertan_check_image() { + local magic="$(cybertan_get_image_magic "$1")" + local fw_magic="$(cybertan_get_hw_magic)" + + [ "$fw_magic" != "$magic" ] && { + echo "Invalid image, ID mismatch, got:$magic, but need:$fw_magic" + return 1 + } + + return 0 +} + +platform_do_upgrade_compex() { + local fw_file=$1 + local fw_part=$PART_NAME + local fw_mtd=$(find_mtd_part $fw_part) + local fw_length=0x$(dd if="$fw_file" bs=2 skip=1 count=4 2>/dev/null) + local fw_blocks=$(($fw_length / 65536)) + + if [ -n "$fw_mtd" ] && [ ${fw_blocks:-0} -gt 0 ]; then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + sync + dd if="$fw_file" bs=64k skip=1 count=$fw_blocks 2>/dev/null | \ + mtd $append write - "$fw_part" + fi +} + +alfa_check_image() { + local magic_long="$(get_magic_long "$1")" + local fw_part_size=$(mtd_get_part_size firmware) + + case "$magic_long" in + "27051956") + [ "$fw_part_size" != "16318464" ] && { + echo "Invalid image magic \"$magic_long\" for $fw_part_size bytes" + return 1 + } + ;; + + "68737173") + [ "$fw_part_size" != "7929856" ] && { + echo "Invalid image magic \"$magic_long\" for $fw_part_size bytes" + return 1 + } + ;; + esac + + return 0 +} + +platform_check_image() { + local board=$(ar71xx_board_name) + local magic="$(get_magic_word "$1")" + local magic_long="$(get_magic_long "$1")" + + [ "$#" -gt 1 ] && return 1 + + case "$board" in + all0315n | \ + all0258n | \ + cap4200ag) + platform_check_image_allnet "$1" && return 0 + return 1 + ;; + alfa-ap96 | \ + alfa-nx | \ + ap113 | \ + ap121 | \ + ap121-mini | \ + ap136-010 | \ + ap136-020 | \ + ap135-020 | \ + ap147-010 | \ + ap96 | \ + bxu2000n-2-a1 | \ + db120 | \ + f9k1115v2 |\ + hornet-ub | \ + mr12 | \ + mr16 | \ + wpj558 | \ + zcn-1523h-2 | \ + zcn-1523h-5) + [ "$magic_long" != "68737173" -a "$magic_long" != "19852003" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + ap81 | \ + ap83 | \ + ap132 | \ + cf-e316n-v2 | \ + dgl-5500-a1 |\ + dhp-1565-a1 |\ + dir-505-a1 | \ + dir-600-a1 | \ + dir-615-c1 | \ + dir-615-e1 | \ + dir-615-e4 | \ + dir-615-i1 | \ + dir-825-c1 | \ + dir-835-a1 | \ + dlan-pro-500-wp | \ + dlan-pro-1200-ac | \ + dragino2 | \ + epg5000 | \ + esr1750 | \ + esr900 | \ + ew-dorin | \ + ew-dorin-router | \ + hiwifi-hc6361 | \ + hornet-ub-x2 | \ + mzk-w04nu | \ + mzk-w300nh | \ + tew-632brp | \ + tew-712br | \ + tew-732br | \ + wrt400n | \ + airgateway | \ + airgatewaypro | \ + airrouter | \ + bullet-m | \ + loco-m-xw | \ + nanostation-m | \ + rocket-m | \ + rocket-m-xw | \ + rocket-m-ti | \ + nanostation-m-xw | \ + rw2458n | \ + wpj531 | \ + wndap360 | \ + wpj344 | \ + wzr-hp-g300nh2 | \ + wzr-hp-g300nh | \ + wzr-hp-g450h | \ + wzr-hp-ag300h | \ + wzr-450hp2 | \ + whr-g301n | \ + whr-hp-g300n | \ + whr-hp-gn | \ + wlae-ag300n | \ + nbg460n_550n_550nh | \ + unifi | \ + unifi-outdoor | \ + carambola2 | \ + weio ) + [ "$magic" != "2705" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + + cpe510) + tplink_pharos_check_image "$1" && return 0 + return 1 + ;; + + bsb | \ + dir-825-b1 | \ + tew-673gru) + dir825b_check_image "$1" && return 0 + ;; + + mynet-rext|\ + wrt160nl) + cybertan_check_image "$1" && return 0 + return 1 + ;; + + qihoo-c301 | \ + mynet-n600 | \ + mynet-n750) + [ "$magic_long" != "5ea3a417" ] && { + echo "Invalid image, bad magic: $magic_long" + return 1 + } + + local typemagic=$(seama_get_type_magic "$1") + [ "$typemagic" != "6669726d" ] && { + echo "Invalid image, bad type: $typemagic" + return 1 + } + + return 0; + ;; + mr1750 | \ + mr600 | \ + mr600v2 | \ + mr900 | \ + mr900v2 | \ + om2p | \ + om2pv2 | \ + om2p-hs | \ + om2p-hsv2 | \ + om2p-lc | \ + om5p | \ + om5p-an) + platform_check_image_openmesh "$magic_long" "$1" && return 0 + return 1 + ;; + + antminer-s1 | \ + antminer-s3 | \ + archer-c5 | \ + archer-c7 | \ + el-m150 | \ + el-mini | \ + gl-inet | \ + mc-mac1200r | \ + minibox-v1 |\ + onion-omega | \ + oolite | \ + smart-300 | \ + tl-mr10u | \ + tl-mr11u | \ + tl-mr12u | \ + tl-mr13u | \ + tl-mr3020 | \ + tl-mr3040 | \ + tl-mr3040-v2 | \ + tl-mr3220 | \ + tl-mr3220-v2 | \ + tl-mr3420 | \ + tl-mr3420-v2 | \ + tl-wa701nd-v2 | \ + tl-wa7210n-v2 | \ + tl-wa7510n | \ + tl-wa750re | \ + tl-wa850re | \ + tl-wa860re | \ + tl-wa801nd-v2 | \ + tl-wa901nd | \ + tl-wa901nd-v2 | \ + tl-wa901nd-v3 | \ + tl-wdr3320-v2 | \ + tl-wdr3500 | \ + tl-wdr4300 | \ + tl-wdr4900-v2 | \ + tl-wdr6500-v2 | \ + tl-wr703n | \ + tl-wr710n | \ + tl-wr720n-v3 | \ + tl-wr741nd | \ + tl-wr741nd-v4 | \ + tl-wr841n-v1 | \ + tl-wa830re-v2 | \ + tl-wr841n-v7 | \ + tl-wr841n-v8 | \ + tl-wr841n-v9 | \ + tl-wr842n-v2 | \ + tl-wr941nd | \ + tl-wr941nd-v5 | \ + tl-wr1041n-v2 | \ + tl-wr1043nd | \ + tl-wr1043nd-v2 | \ + tl-wr2543n) + local magic_ver="0100" + + case "$board" in + tl-wdr6500-v2) + magic_ver="0200" + ;; + esac + + [ "$magic" != "$magic_ver" ] && { + echo "Invalid image type." + return 1 + } + + local hwid + local imageid + + hwid=$(tplink_get_hwid) + imageid=$(tplink_get_image_hwid "$1") + + [ "$hwid" != "$imageid" ] && { + echo "Invalid image, hardware ID mismatch, hw:$hwid image:$imageid." + return 1 + } + + local boot_size + + boot_size=$(tplink_get_image_boot_size "$1") + [ "$boot_size" != "00000000" ] && { + echo "Invalid image, it contains a bootloader." + return 1 + } + + return 0 + ;; + + tube2h) + alfa_check_image "$1" && return 0 + return 1 + ;; + + unifi-outdoor-plus | \ + uap-pro) + [ "$magic_long" != "19852003" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + wndr3700 | \ + wnr2000-v3 | \ + wnr612-v2 | \ + wnr1000-v2) + local hw_magic + + hw_magic="$(ar71xx_get_mtd_part_magic firmware)" + [ "$magic_long" != "$hw_magic" ] && { + echo "Invalid image, hardware ID mismatch, hw:$hw_magic image:$magic_long." + return 1 + } + return 0 + ;; + nbg6716 | \ + r6100 | \ + wndr3700v4 | \ + wndr4300 ) + nand_do_platform_check $board $1 + return $?; + ;; + routerstation | \ + routerstation-pro | \ + ls-sr71 | \ + pb42 | \ + pb44 | \ + all0305 | \ + eap300v2 | \ + eap7660d | \ + ja76pf | \ + ja76pf2 | \ + jwap003 | \ + wp543 | \ + wpe72) + [ "$magic" != "4349" ] && { + echo "Invalid image. Use *-sysupgrade.bin files on this board" + return 1 + } + + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + + if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then + return 0 + else + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + return 0 + ;; + wnr2000-v4) + [ "$magic_long" != "32303034" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; + + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_pre_upgrade() { + local board=$(ar71xx_board_name) + + case "$board" in + nbg6716 | \ + r6100 | \ + wndr3700v4 | \ + wndr4300 ) + nand_do_upgrade "$1" + ;; + esac +} + +platform_do_upgrade() { + local board=$(ar71xx_board_name) + + case "$board" in + routerstation | \ + routerstation-pro | \ + ls-sr71 | \ + all0305 | \ + eap7660d | \ + pb42 | \ + pb44 | \ + ja76pf | \ + ja76pf2 | \ + jwap003) + platform_do_upgrade_combined "$ARGV" + ;; + wp543|\ + wpe72) + platform_do_upgrade_compex "$ARGV" + ;; + all0258n ) + platform_do_upgrade_allnet "0x9f050000" "$ARGV" + ;; + all0315n ) + platform_do_upgrade_allnet "0x9f080000" "$ARGV" + ;; + eap300v2 |\ + cap4200ag) + platform_do_upgrade_allnet "0xbf0a0000" "$ARGV" + ;; + dir-825-b1 |\ + tew-673gru) + platform_do_upgrade_dir825b "$ARGV" + ;; + mr1750 | \ + mr600 | \ + mr600v2 | \ + mr900 | \ + mr900v2 | \ + om2p | \ + om2pv2 | \ + om2p-hs | \ + om2p-hsv2 | \ + om2p-lc | \ + om5p | \ + om5p-an) + platform_do_upgrade_openmesh "$ARGV" + ;; + unifi-outdoor-plus | \ + uap-pro) + MTD_CONFIG_ARGS="-s 0x180000" + default_do_upgrade "$ARGV" + ;; + *) + default_do_upgrade "$ARGV" + ;; + esac +} + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/ar71xx/base-files/sbin/wget2nand b/target/linux/ar71xx/base-files/sbin/wget2nand new file mode 100755 index 0000000..8175a9e --- /dev/null +++ b/target/linux/ar71xx/base-files/sbin/wget2nand @@ -0,0 +1,85 @@ +#!/bin/sh +# wget2nand +# This script can be used to download a TGZ file from your build system which +# contains the files to be installed on the NAND flash on your RB1xx card. +# The one parameter is the URL of the TGZ file to be downloaded. +# Licence GPL V2 +# Author david.goodenough@linkchoose.co.uk +# Based on cf2nand from RB532 support +. /lib/functions.sh + +wget2nand_dir=/tmp/wget2nand +mnt_kernel=$wget2nand_dir/mnt_kernel +mnt_rootfs=$wget2nand_dir/mnt_rootfs +src_rootfs=$wget2nand_dir/rootfs.tgz +src_kernel=$wget2nand_dir/kernel + +[ -d "$wget2nand_dir" ] && { + echo "$wget2nand_dir already exists" + exit 1 +} + +# need to find the wget server from the command line +url=$1 +[ -z "$url" ] && { + echo "No URL specified for image TGZ" + echo "Usage : $0 URL" + exit 1 +} + +url_kernel=$url/openwrt-ar71xx-mikrotik-vmlinux-lzma.elf +url_rootfs=$url/openwrt-ar71xx-mikrotik-rootfs.tar.gz + +mtd_kernel="$(find_mtd_part 'kernel')" +mtd_rootfs="$(find_mtd_part 'rootfs')" +[ -z "$mtd_kernel" -o -z "$mtd_rootfs" ] && { + echo "Cannot find NAND Flash partitions" + exit 1 +} + +mkdir "$wget2nand_dir" +wget $url_kernel -O "$src_kernel" || { + echo "Unable to download $url_kernel" + exit 1 +} + +wget $url_rootfs -O "$src_rootfs" || { + echo "Unable to download $url_rootfs" + exit 1 +} + +echo "Erasing filesystem..." +mtd erase kernel 2>/dev/null >/dev/null +mtd erase rootfs 2>/dev/null >/dev/null + +echo "Mounting $mtd_rootfs as new root and $mtd_kernel as kernel partition" + +mkdir "$mnt_kernel" +mkdir "$mnt_rootfs" +mount -t yaffs2 "$mtd_kernel" "$mnt_kernel" +mount -t yaffs2 "$mtd_rootfs" "$mnt_rootfs" + +echo "Copying kernel..." +cp $src_kernel $mnt_kernel/kernel || { + echo "Error occured while copying the kernel" + exit 1 +} +chmod +x $mnt_kernel/kernel + +echo "Preparing filesystem..." +( cd "$mnt_rootfs"; tar xvz -f "$src_rootfs" ) + +# make sure everything is written before we unmount the partitions +echo "chmod ugo+x /" > $mnt_rootfs/etc/uci-defaults/set_root_permission +sync +ls $mnt_kernel >/dev/null +ls $mnt_rootfs >/dev/null + +echo "Cleaning up..." +# unmount the partitions and remove the directories into which they were mounted +umount $mnt_kernel +umount $mnt_rootfs +rm -rf $wget2nand_dir + +# all done +echo "Image written, you can now reboot. Remember to change the boot source to Boot from Nand" diff --git a/target/linux/ar71xx/config-4.1 b/target/linux/ar71xx/config-4.1 new file mode 100644 index 0000000..6d31f67 --- /dev/null +++ b/target/linux/ar71xx/config-4.1 @@ -0,0 +1,355 @@ +CONFIG_AG71XX=y +CONFIG_AG71XX_AR8216_SUPPORT=y +# CONFIG_AG71XX_DEBUG is not set +# CONFIG_AG71XX_DEBUG_FS is not set +CONFIG_AR8216_PHY=y +CONFIG_AR8216_PHY_LEDS=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_AT803X_PHY=y +CONFIG_ATH79=y +CONFIG_ATH79_DEV_AP9X_PCI=y +CONFIG_ATH79_DEV_DSA=y +CONFIG_ATH79_DEV_ETH=y +CONFIG_ATH79_DEV_GPIO_BUTTONS=y +CONFIG_ATH79_DEV_LEDS_GPIO=y +CONFIG_ATH79_DEV_M25P80=y +CONFIG_ATH79_DEV_NFC=y +CONFIG_ATH79_DEV_SPI=y +CONFIG_ATH79_DEV_USB=y +CONFIG_ATH79_DEV_WMAC=y +CONFIG_ATH79_MACH_ALFA_AP96=y +CONFIG_ATH79_MACH_ALFA_NX=y +CONFIG_ATH79_MACH_ALL0258N=y +CONFIG_ATH79_MACH_ALL0315N=y +CONFIG_ATH79_MACH_ANTMINER_S1=y +CONFIG_ATH79_MACH_ANTMINER_S3=y +CONFIG_ATH79_MACH_AP113=y +CONFIG_ATH79_MACH_AP121=y +CONFIG_ATH79_MACH_AP132=y +CONFIG_ATH79_MACH_AP136=y +CONFIG_ATH79_MACH_AP143=y +CONFIG_ATH79_MACH_AP147=y +CONFIG_ATH79_MACH_AP152=y +CONFIG_ATH79_MACH_AP81=y +CONFIG_ATH79_MACH_AP83=y +CONFIG_ATH79_MACH_AP96=y +CONFIG_ATH79_MACH_ARCHER_C7=y +CONFIG_ATH79_MACH_AW_NR580=y +CONFIG_ATH79_MACH_BHU_BXU2000N2_A=y +CONFIG_ATH79_MACH_BSB=y +CONFIG_ATH79_MACH_CAP4200AG=y +CONFIG_ATH79_MACH_CARAMBOLA2=y +CONFIG_ATH79_MACH_CF_E316N_V2=y +CONFIG_ATH79_MACH_CPE510=y +CONFIG_ATH79_MACH_DB120=y +CONFIG_ATH79_MACH_DGL_5500_A1=y +CONFIG_ATH79_MACH_DHP_1565_A1=y +CONFIG_ATH79_MACH_DIR_505_A1=y +CONFIG_ATH79_MACH_DIR_600_A1=y +CONFIG_ATH79_MACH_DIR_615_C1=y +CONFIG_ATH79_MACH_DIR_615_I1=y +CONFIG_ATH79_MACH_DIR_825_B1=y +CONFIG_ATH79_MACH_DIR_825_C1=y +CONFIG_ATH79_MACH_DLAN_PRO_1200_AC=y +CONFIG_ATH79_MACH_DLAN_PRO_500_WP=y +CONFIG_ATH79_MACH_DRAGINO2=y +CONFIG_ATH79_MACH_EAP300V2=y +CONFIG_ATH79_MACH_EAP7660D=y +CONFIG_ATH79_MACH_EL_M150=y +CONFIG_ATH79_MACH_EL_MINI=y +CONFIG_ATH79_MACH_EPG5000=y +CONFIG_ATH79_MACH_ESR1750=y +CONFIG_ATH79_MACH_ESR900=y +CONFIG_ATH79_MACH_EW_DORIN=y +CONFIG_ATH79_MACH_F9K1115V2=y +CONFIG_ATH79_MACH_GL_INET=y +CONFIG_ATH79_MACH_GS_MINIBOX_V1=y +CONFIG_ATH79_MACH_GS_OOLITE=y +CONFIG_ATH79_MACH_HIWIFI_HC6361=y +CONFIG_ATH79_MACH_HORNET_UB=y +CONFIG_ATH79_MACH_JA76PF=y +CONFIG_ATH79_MACH_JWAP003=y +CONFIG_ATH79_MACH_MC_MAC1200R=y +CONFIG_ATH79_MACH_MR12=y +CONFIG_ATH79_MACH_MR16=y +CONFIG_ATH79_MACH_MR1750=y +CONFIG_ATH79_MACH_MR600=y +CONFIG_ATH79_MACH_MR900=y +CONFIG_ATH79_MACH_MYNET_N600=y +CONFIG_ATH79_MACH_MYNET_N750=y +CONFIG_ATH79_MACH_MYNET_REXT=y +CONFIG_ATH79_MACH_MZK_W04NU=y +CONFIG_ATH79_MACH_MZK_W300NH=y +CONFIG_ATH79_MACH_NBG460N=y +CONFIG_ATH79_MACH_NBG6716=y +CONFIG_ATH79_MACH_OM2P=y +CONFIG_ATH79_MACH_OM5P=y +CONFIG_ATH79_MACH_ONION_OMEGA=y +CONFIG_ATH79_MACH_PB42=y +CONFIG_ATH79_MACH_PB44=y +CONFIG_ATH79_MACH_PB92=y +CONFIG_ATH79_MACH_QIHOO_C301=y +CONFIG_ATH79_MACH_R6100=y +# CONFIG_ATH79_MACH_RB2011 is not set +# CONFIG_ATH79_MACH_RB4XX is not set +# CONFIG_ATH79_MACH_RB750 is not set +# CONFIG_ATH79_MACH_RB91X is not set +# CONFIG_ATH79_MACH_RB922 is not set +# CONFIG_ATH79_MACH_RB95X is not set +# CONFIG_ATH79_MACH_RBSXTLITE is not set +CONFIG_ATH79_MACH_RW2458N=y +CONFIG_ATH79_MACH_SMART_300=y +CONFIG_ATH79_MACH_TEW_632BRP=y +CONFIG_ATH79_MACH_TEW_673GRU=y +CONFIG_ATH79_MACH_TEW_712BR=y +CONFIG_ATH79_MACH_TEW_732BR=y +CONFIG_ATH79_MACH_TL_MR11U=y +CONFIG_ATH79_MACH_TL_MR13U=y +CONFIG_ATH79_MACH_TL_MR3020=y +CONFIG_ATH79_MACH_TL_MR3X20=y +CONFIG_ATH79_MACH_TL_WA701ND_V2=y +CONFIG_ATH79_MACH_TL_WA7210N_V2=y +CONFIG_ATH79_MACH_TL_WA830RE_V2=y +CONFIG_ATH79_MACH_TL_WA901ND=y +CONFIG_ATH79_MACH_TL_WA901ND_V2=y +CONFIG_ATH79_MACH_TL_WAX50RE=y +CONFIG_ATH79_MACH_TL_WDR3320_V2=y +CONFIG_ATH79_MACH_TL_WDR3500=y +CONFIG_ATH79_MACH_TL_WDR4300=y +CONFIG_ATH79_MACH_TL_WDR6500_V2=y +CONFIG_ATH79_MACH_TL_WR1041N_V2=y +CONFIG_ATH79_MACH_TL_WR1043ND=y +CONFIG_ATH79_MACH_TL_WR1043ND_V2=y +CONFIG_ATH79_MACH_TL_WR2543N=y +CONFIG_ATH79_MACH_TL_WR703N=y +CONFIG_ATH79_MACH_TL_WR720N_V3=y +CONFIG_ATH79_MACH_TL_WR741ND=y +CONFIG_ATH79_MACH_TL_WR741ND_V4=y +CONFIG_ATH79_MACH_TL_WR841N_V1=y +CONFIG_ATH79_MACH_TL_WR841N_V8=y +CONFIG_ATH79_MACH_TL_WR841N_V9=y +CONFIG_ATH79_MACH_TL_WR941ND=y +CONFIG_ATH79_MACH_TUBE2H=y +CONFIG_ATH79_MACH_UBNT=y +CONFIG_ATH79_MACH_UBNT_XM=y +CONFIG_ATH79_MACH_WEIO=y +CONFIG_ATH79_MACH_WHR_HP_G300N=y +CONFIG_ATH79_MACH_WLAE_AG300N=y +CONFIG_ATH79_MACH_WLR8100=y +CONFIG_ATH79_MACH_WNDAP360=y +CONFIG_ATH79_MACH_WNDR3700=y +CONFIG_ATH79_MACH_WNDR4300=y +CONFIG_ATH79_MACH_WNR2000=y +CONFIG_ATH79_MACH_WNR2000_V3=y +CONFIG_ATH79_MACH_WNR2000_V4=y +CONFIG_ATH79_MACH_WNR2200=y +CONFIG_ATH79_MACH_WP543=y +CONFIG_ATH79_MACH_WPE72=y +CONFIG_ATH79_MACH_WPJ344=y +CONFIG_ATH79_MACH_WPJ531=y +CONFIG_ATH79_MACH_WPJ558=y +CONFIG_ATH79_MACH_WRT160NL=y +CONFIG_ATH79_MACH_WRT400N=y +CONFIG_ATH79_MACH_WZR_450HP2=y +CONFIG_ATH79_MACH_WZR_HP_AG300H=y +CONFIG_ATH79_MACH_WZR_HP_G300NH=y +CONFIG_ATH79_MACH_WZR_HP_G300NH2=y +CONFIG_ATH79_MACH_WZR_HP_G450H=y +CONFIG_ATH79_MACH_ZCN_1523H=y +CONFIG_ATH79_NVRAM=y +CONFIG_ATH79_PCI_ATH9K_FIXUP=y +# CONFIG_ATH79_ROUTERBOOT is not set +CONFIG_ATH79_WDT=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_DEVRES=y +# CONFIG_GPIO_LATCH is not set +CONFIG_GPIO_NXP_74HC153=y +CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_HAS_PCI=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_GPIO=y +CONFIG_IMAGE_CMDLINE_HACK=y +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_SOURCE="../../root" +CONFIG_IP17XX_PHY=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_WNDR3700_USB is not set +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MICREL_PHY=y +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +CONFIG_MIPS_MACHINE=y +CONFIG_MIPS_SPRAM=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_CFI_I2 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CYBERTAN_PARTS=y +CONFIG_MTD_M25P80=y +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +CONFIG_MTD_MYLOADER_PARTS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2 +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_LZMA_FW=y +CONFIG_MTD_SPLIT_SEAMA_FW=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_TPLINK_PARTS=y +CONFIG_MYLOADER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MV88E6060=y +CONFIG_NET_DSA_MV88E6063=y +CONFIG_NET_DSA_TAG_TRAILER=y +CONFIG_NET_SWITCHDEV=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_AR724X=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366S_PHY=y +CONFIG_RTL8366_SMI=y +CONFIG_RTL8367_PHY=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SERIAL_AR933X=y +CONFIG_SERIAL_AR933X_CONSOLE=y +CONFIG_SERIAL_AR933X_NR_UARTS=2 +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SOC_AR71XX=y +CONFIG_SOC_AR724X=y +CONFIG_SOC_AR913X=y +CONFIG_SOC_AR933X=y +CONFIG_SOC_AR934X=y +CONFIG_SOC_QCA953X=y +CONFIG_SOC_QCA955X=y +# CONFIG_SOC_QCA956X is not set +CONFIG_SPI=y +CONFIG_SPI_AP83=y +CONFIG_SPI_ATH79=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_VSC7385 is not set +CONFIG_SRCU=y +CONFIG_SWCONFIG=y +CONFIG_SWCONFIG_LEDS=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c new file mode 100644 index 0000000..d382453 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.c @@ -0,0 +1,159 @@ +/* + * Atheros AP9X reference board PCI initialization + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "pci-ath9k-fixup.h" +#include "pci.h" + +static struct ath9k_platform_data ap9x_wmac0_data = { + .led_pin = -1, +}; +static struct ath9k_platform_data ap9x_wmac1_data = { + .led_pin = -1, +}; +static char ap9x_wmac0_mac[6]; +static char ap9x_wmac1_mac[6]; + +__init void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.led_pin = pin; + break; + case 1: + ap9x_wmac1_data.led_pin = pin; + break; + } +} + +__init struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac) +{ + switch (wmac) { + case 0: + return &ap9x_wmac0_data; + + case 1: + return &ap9x_wmac1_data; + } + + return NULL; +} + +__init void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.gpio_mask = mask; + ap9x_wmac0_data.gpio_val = val; + break; + case 1: + ap9x_wmac1_data.gpio_mask = mask; + ap9x_wmac1_data.gpio_val = val; + break; + } +} + +__init void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds, + int num_leds) +{ + switch (wmac) { + case 0: + ap9x_wmac0_data.leds = leds; + ap9x_wmac0_data.num_leds = num_leds; + break; + case 1: + ap9x_wmac1_data.leds = leds; + ap9x_wmac1_data.num_leds = num_leds; + break; + } +} + +static int ap91_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 0: + dev->dev.platform_data = &ap9x_wmac0_data; + break; + } + + return 0; +} + +__init void ap91_pci_init(u8 *cal_data, u8 *mac_addr) +{ + if (cal_data) + memcpy(ap9x_wmac0_data.eeprom_data, cal_data, + sizeof(ap9x_wmac0_data.eeprom_data)); + + if (mac_addr) { + memcpy(ap9x_wmac0_mac, mac_addr, sizeof(ap9x_wmac0_mac)); + ap9x_wmac0_data.macaddr = ap9x_wmac0_mac; + } + + ath79_pci_set_plat_dev_init(ap91_pci_plat_dev_init); + ath79_register_pci(); + + pci_enable_ath9k_fixup(0, ap9x_wmac0_data.eeprom_data); +} + +__init void ap91_pci_init_simple(void) +{ + ap91_pci_init(NULL, NULL); + ap9x_wmac0_data.eeprom_name = "pci_wmac0.eeprom"; +} + +static int ap94_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 17: + dev->dev.platform_data = &ap9x_wmac0_data; + break; + + case 18: + dev->dev.platform_data = &ap9x_wmac1_data; + break; + } + + return 0; +} + +__init void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ + if (cal_data0) + memcpy(ap9x_wmac0_data.eeprom_data, cal_data0, + sizeof(ap9x_wmac0_data.eeprom_data)); + + if (cal_data1) + memcpy(ap9x_wmac1_data.eeprom_data, cal_data1, + sizeof(ap9x_wmac1_data.eeprom_data)); + + if (mac_addr0) { + memcpy(ap9x_wmac0_mac, mac_addr0, sizeof(ap9x_wmac0_mac)); + ap9x_wmac0_data.macaddr = ap9x_wmac0_mac; + } + + if (mac_addr1) { + memcpy(ap9x_wmac1_mac, mac_addr1, sizeof(ap9x_wmac1_mac)); + ap9x_wmac1_data.macaddr = ap9x_wmac1_mac; + } + + ath79_pci_set_plat_dev_init(ap94_pci_plat_dev_init); + ath79_register_pci(); + + pci_enable_ath9k_fixup(17, ap9x_wmac0_data.eeprom_data); + pci_enable_ath9k_fixup(18, ap9x_wmac1_data.eeprom_data); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h new file mode 100644 index 0000000..ad288cb --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-ap9x-pci.h @@ -0,0 +1,48 @@ +/* + * Atheros AP9X reference board PCI initialization + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_AP9X_PCI_H +#define _ATH79_DEV_AP9X_PCI_H + +struct gpio_led; +struct ath9k_platform_data; + +#if defined(CONFIG_ATH79_DEV_AP9X_PCI) +void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin); +void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val); +void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds, + int num_leds); +struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac); + +void ap91_pci_init(u8 *cal_data, u8 *mac_addr); +void ap91_pci_init_simple(void); +void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1); + +#else +static inline void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) {} +static inline void ap9x_pci_setup_wmac_gpio(unsigned wmac, + u32 mask, u32 val) {} +static inline void ap9x_pci_setup_wmac_leds(unsigned wmac, + struct gpio_led *leds, + int num_leds) {} +static inline struct ath9k_platform_data *ap9x_pci_get_wmac_data(unsigned wmac) +{ + return NULL; +} + +static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) {} +static inline void ap91_pci_init_simple(void) {} +static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) {} +#endif + +#endif /* _ATH79_DEV_AP9X_PCI_H */ + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c new file mode 100644 index 0000000..a9bb334 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.c @@ -0,0 +1,41 @@ +/* + * Atheros AR71xx DSA switch device support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-dsa.h" + +static struct platform_device ar71xx_dsa_switch_device = { + .name = "dsa", + .id = 0, +}; + +void __init ath79_register_dsa(struct device *netdev, + struct device *miidev, + struct dsa_platform_data *d) +{ + int i; + + d->netdev = netdev; + for (i = 0; i < d->nr_chips; i++) +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) + d->chip[i].mii_bus = miidev; +#else + d->chip[i].host_dev = miidev; +#endif + + ar71xx_dsa_switch_device.dev.platform_data = d; + platform_device_register(&ar71xx_dsa_switch_device); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h new file mode 100644 index 0000000..3730202 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-dsa.h @@ -0,0 +1,21 @@ +/* + * Atheros AR71xx DSA switch device support + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_DSA_H +#define _ATH79_DEV_DSA_H + +#include + +void ath79_register_dsa(struct device *netdev, + struct device *miidev, + struct dsa_platform_data *d); + +#endif /* _ATH79_DEV_DSA_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c new file mode 100644 index 0000000..31d2438 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -0,0 +1,1254 @@ +/* + * Atheros AR71xx SoC platform devices + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" + +unsigned char ath79_mac_base[ETH_ALEN] __initdata; + +static struct resource ath79_mdio0_resources[] = { + { + .name = "mdio_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE0_BASE, + .end = AR71XX_GE0_BASE + 0x200 - 1, + } +}; + +struct ag71xx_mdio_platform_data ath79_mdio0_data; + +struct platform_device ath79_mdio0_device = { + .name = "ag71xx-mdio", + .id = 0, + .resource = ath79_mdio0_resources, + .num_resources = ARRAY_SIZE(ath79_mdio0_resources), + .dev = { + .platform_data = &ath79_mdio0_data, + }, +}; + +static struct resource ath79_mdio1_resources[] = { + { + .name = "mdio_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE1_BASE, + .end = AR71XX_GE1_BASE + 0x200 - 1, + } +}; + +struct ag71xx_mdio_platform_data ath79_mdio1_data; + +struct platform_device ath79_mdio1_device = { + .name = "ag71xx-mdio", + .id = 1, + .resource = ath79_mdio1_resources, + .num_resources = ARRAY_SIZE(ath79_mdio1_resources), + .dev = { + .platform_data = &ath79_mdio1_data, + }, +}; + +static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) +{ + void __iomem *base; + u32 t; + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + + t = __raw_readl(base + cfg_reg); + t &= ~(3 << shift); + t |= (2 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + __raw_writel(pll_val, base + pll_reg); + + t |= (3 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + t &= ~(3 << shift); + __raw_writel(t, base + cfg_reg); + udelay(100); + + printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", + (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); + + iounmap(base); +} + +static void __init ath79_mii_ctrl_set_if(unsigned int reg, + unsigned int mii_if) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE); + + t = __raw_readl(base + reg); + t &= ~(AR71XX_MII_CTRL_IF_MASK); + t |= (mii_if & AR71XX_MII_CTRL_IF_MASK); + __raw_writel(t, base + reg); + + iounmap(base); +} + +static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed) +{ + void __iomem *base; + unsigned int mii_speed; + u32 t; + + switch (speed) { + case SPEED_10: + mii_speed = AR71XX_MII_CTRL_SPEED_10; + break; + case SPEED_100: + mii_speed = AR71XX_MII_CTRL_SPEED_100; + break; + case SPEED_1000: + mii_speed = AR71XX_MII_CTRL_SPEED_1000; + break; + default: + BUG(); + } + + base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE); + + t = __raw_readl(base + reg); + t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT); + t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT; + __raw_writel(t, base + reg); + + iounmap(base); +} + +static unsigned long ar934x_get_mdio_ref_clock(void) +{ + void __iomem *base; + unsigned long ret; + u32 t; + + base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + + ret = 0; + t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) { + ret = 100 * 1000 * 1000; + } else { + struct clk *clk; + + clk = clk_get(NULL, "ref"); + if (!IS_ERR(clk)) + ret = clk_get_rate(clk); + } + + iounmap(base); + + return ret; +} + +void __init ath79_register_mdio(unsigned int id, u32 phy_mask) +{ + struct platform_device *mdio_dev; + struct ag71xx_mdio_platform_data *mdio_data; + unsigned int max_id; + + if (ath79_soc == ATH79_SOC_AR9341 || + ath79_soc == ATH79_SOC_AR9342 || + ath79_soc == ATH79_SOC_AR9344 || + ath79_soc == ATH79_SOC_QCA9556 || + ath79_soc == ATH79_SOC_QCA9558) + max_id = 1; + else + max_id = 0; + + if (id > max_id) { + printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id); + return; + } + + switch (ath79_soc) { + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + mdio_dev = &ath79_mdio1_device; + mdio_data = &ath79_mdio1_data; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + if (id == 0) { + mdio_dev = &ath79_mdio0_device; + mdio_data = &ath79_mdio0_data; + } else { + mdio_dev = &ath79_mdio1_device; + mdio_data = &ath79_mdio1_data; + } + break; + + case ATH79_SOC_AR7242: + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, + AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000, + AR71XX_ETH0_PLL_SHIFT); + /* fall through */ + default: + mdio_dev = &ath79_mdio0_device; + mdio_data = &ath79_mdio0_data; + break; + } + + mdio_data->phy_mask = phy_mask; + + switch (ath79_soc) { + case ATH79_SOC_AR7240: + mdio_data->is_ar7240 = 1; + /* fall through */ + case ATH79_SOC_AR7241: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_AR9330: + mdio_data->is_ar9330 = 1; + /* fall through */ + case ATH79_SOC_AR9331: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + if (id == 1) { + mdio_data->builtin_switch = 1; + mdio_data->ref_clock = ar934x_get_mdio_ref_clock(); + mdio_data->mdio_clock = 6250000; + } + mdio_data->is_ar934x = 1; + break; + + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + mdio_data->builtin_switch = 1; + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + mdio_data->is_ar934x = 1; + break; + + default: + break; + } + + platform_device_register(mdio_dev); +} + +struct ath79_eth_pll_data ath79_eth0_pll_data; +struct ath79_eth_pll_data ath79_eth1_pll_data; + +static u32 ath79_get_eth_pll(unsigned int mac, int speed) +{ + struct ath79_eth_pll_data *pll_data; + u32 pll_val; + + switch (mac) { + case 0: + pll_data = &ath79_eth0_pll_data; + break; + case 1: + pll_data = &ath79_eth1_pll_data; + break; + default: + BUG(); + } + + switch (speed) { + case SPEED_10: + pll_val = pll_data->pll_10; + break; + case SPEED_100: + pll_val = pll_data->pll_100; + break; + case SPEED_1000: + pll_val = pll_data->pll_1000; + break; + default: + BUG(); + } + + return pll_val; +} + +static void ath79_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, + val, AR71XX_ETH0_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed); +} + +static void ath79_set_speed_ge1(int speed) +{ + u32 val = ath79_get_eth_pll(1, speed); + + ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, + val, AR71XX_ETH1_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed); +} + +static void ar7242_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + void __iomem *base; + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK); + iounmap(base); +} + +static void ar91xx_set_speed_ge0(int speed) +{ + u32 val = ath79_get_eth_pll(0, speed); + + ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK, + val, AR913X_ETH0_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed); +} + +static void ar91xx_set_speed_ge1(int speed) +{ + u32 val = ath79_get_eth_pll(1, speed); + + ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK, + val, AR913X_ETH1_PLL_SHIFT); + ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed); +} + +static void ar934x_set_speed_ge0(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(0, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG); + iounmap(base); +} + +static void qca955x_set_speed_xmii(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(0, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG); + iounmap(base); +} + +static void qca955x_set_speed_sgmii(int speed) +{ + void __iomem *base; + u32 val = ath79_get_eth_pll(1, speed); + + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG); + iounmap(base); +} + +static void ath79_set_speed_dummy(int speed) +{ +} + +static void ath79_ddr_no_flush(void) +{ +} + +static void ath79_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0); +} + +static void ath79_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1); +} + +static void ar724x_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0); +} + +static void ar724x_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1); +} + +static void ar91xx_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0); +} + +static void ar91xx_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1); +} + +static void ar933x_ddr_flush_ge0(void) +{ + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0); +} + +static void ar933x_ddr_flush_ge1(void) +{ + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1); +} + +static struct resource ath79_eth0_resources[] = { + { + .name = "mac_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE0_BASE, + .end = AR71XX_GE0_BASE + 0x200 - 1, + }, { + .name = "mac_irq", + .flags = IORESOURCE_IRQ, + .start = ATH79_CPU_IRQ(4), + .end = ATH79_CPU_IRQ(4), + }, +}; + +struct ag71xx_platform_data ath79_eth0_data = { + .reset_bit = AR71XX_RESET_GE0_MAC, +}; + +struct platform_device ath79_eth0_device = { + .name = "ag71xx", + .id = 0, + .resource = ath79_eth0_resources, + .num_resources = ARRAY_SIZE(ath79_eth0_resources), + .dev = { + .platform_data = &ath79_eth0_data, + }, +}; + +static struct resource ath79_eth1_resources[] = { + { + .name = "mac_base", + .flags = IORESOURCE_MEM, + .start = AR71XX_GE1_BASE, + .end = AR71XX_GE1_BASE + 0x200 - 1, + }, { + .name = "mac_irq", + .flags = IORESOURCE_IRQ, + .start = ATH79_CPU_IRQ(5), + .end = ATH79_CPU_IRQ(5), + }, +}; + +struct ag71xx_platform_data ath79_eth1_data = { + .reset_bit = AR71XX_RESET_GE1_MAC, +}; + +struct platform_device ath79_eth1_device = { + .name = "ag71xx", + .id = 1, + .resource = ath79_eth1_resources, + .num_resources = ARRAY_SIZE(ath79_eth1_resources), + .dev = { + .platform_data = &ath79_eth1_data, + }, +}; + +struct ag71xx_switch_platform_data ath79_switch_data; + +#define AR71XX_PLL_VAL_1000 0x00110000 +#define AR71XX_PLL_VAL_100 0x00001099 +#define AR71XX_PLL_VAL_10 0x00991099 + +#define AR724X_PLL_VAL_1000 0x00110000 +#define AR724X_PLL_VAL_100 0x00001099 +#define AR724X_PLL_VAL_10 0x00991099 + +#define AR7242_PLL_VAL_1000 0x16000000 +#define AR7242_PLL_VAL_100 0x00000101 +#define AR7242_PLL_VAL_10 0x00001616 + +#define AR913X_PLL_VAL_1000 0x1a000000 +#define AR913X_PLL_VAL_100 0x13000a44 +#define AR913X_PLL_VAL_10 0x00441099 + +#define AR933X_PLL_VAL_1000 0x00110000 +#define AR933X_PLL_VAL_100 0x00001099 +#define AR933X_PLL_VAL_10 0x00991099 + +#define AR934X_PLL_VAL_1000 0x16000000 +#define AR934X_PLL_VAL_100 0x00000101 +#define AR934X_PLL_VAL_10 0x00001616 + +static void __init ath79_init_eth_pll_data(unsigned int id) +{ + struct ath79_eth_pll_data *pll_data; + u32 pll_10, pll_100, pll_1000; + + switch (id) { + case 0: + pll_data = &ath79_eth0_pll_data; + break; + case 1: + pll_data = &ath79_eth1_pll_data; + break; + default: + BUG(); + } + + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + pll_10 = AR71XX_PLL_VAL_10; + pll_100 = AR71XX_PLL_VAL_100; + pll_1000 = AR71XX_PLL_VAL_1000; + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + pll_10 = AR724X_PLL_VAL_10; + pll_100 = AR724X_PLL_VAL_100; + pll_1000 = AR724X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR7242: + pll_10 = AR7242_PLL_VAL_10; + pll_100 = AR7242_PLL_VAL_100; + pll_1000 = AR7242_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + pll_10 = AR913X_PLL_VAL_10; + pll_100 = AR913X_PLL_VAL_100; + pll_1000 = AR913X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + pll_10 = AR933X_PLL_VAL_10; + pll_100 = AR933X_PLL_VAL_100; + pll_1000 = AR933X_PLL_VAL_1000; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + pll_10 = AR934X_PLL_VAL_10; + pll_100 = AR934X_PLL_VAL_100; + pll_1000 = AR934X_PLL_VAL_1000; + break; + + default: + BUG(); + } + + if (!pll_data->pll_10) + pll_data->pll_10 = pll_10; + + if (!pll_data->pll_100) + pll_data->pll_100 = pll_100; + + if (!pll_data->pll_1000) + pll_data->pll_1000 = pll_1000; +} + +static int __init ath79_setup_phy_if_mode(unsigned int id, + struct ag71xx_platform_data *pdata) +{ + unsigned int mii_if; + + switch (id) { + case 0: + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + mii_if = AR71XX_MII0_CTRL_IF_MII; + break; + case PHY_INTERFACE_MODE_GMII: + mii_if = AR71XX_MII0_CTRL_IF_GMII; + break; + case PHY_INTERFACE_MODE_RGMII: + mii_if = AR71XX_MII0_CTRL_IF_RGMII; + break; + case PHY_INTERFACE_MODE_RMII: + mii_if = AR71XX_MII0_CTRL_IF_RMII; + break; + default: + return -EINVAL; + } + ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if); + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_TP9343: + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; + break; + + case ATH79_SOC_AR7242: + /* FIXME */ + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RMII: + break; + default: + return -EINVAL; + } + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: + break; + default: + return -EINVAL; + } + break; + + case ATH79_SOC_QCA9561: + if (!pdata->phy_if_mode) + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; + break; + + default: + BUG(); + } + break; + case 1: + switch (ath79_soc) { + case ATH79_SOC_AR7130: + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + case ATH79_SOC_AR9130: + case ATH79_SOC_AR9132: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_RMII: + mii_if = AR71XX_MII1_CTRL_IF_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + mii_if = AR71XX_MII1_CTRL_IF_RGMII; + break; + default: + return -EINVAL; + } + ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if); + break; + + case ATH79_SOC_AR7240: + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; + break; + + case ATH79_SOC_AR7242: + /* FIXME */ + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + break; + default: + return -EINVAL; + } + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: + break; + default: + return -EINVAL; + } + break; + + default: + BUG(); + } + break; + } + + return 0; +} + +void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE); + + t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG); + t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP); + if (mac) + t |= AR933X_ETH_CFG_SW_PHY_SWAP; + if (mdio) + t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP; + __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +void __init ath79_setup_ar934x_eth_cfg(u32 mask) +{ + void __iomem *base; + u32 t; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_MII_GMAC0 | + AR934X_ETH_CFG_GMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + t |= mask; + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + /* flush write */ + __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, + unsigned int rxdv) +{ + void __iomem *base; + u32 t; + + rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK; + rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK; + + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE); + + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT | + AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT); + + t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT | + rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT); + + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG); + /* flush write */ + __raw_readl(base + AR934X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +void __init ath79_setup_qca955x_eth_cfg(u32 mask) +{ + void __iomem *base; + u32 t; + + base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); + + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); + + t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); + + t |= mask; + + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); + + iounmap(base); +} + +static int ath79_eth_instance __initdata; +void __init ath79_register_eth(unsigned int id) +{ + struct platform_device *pdev; + struct ag71xx_platform_data *pdata; + int err; + + if (id > 1) { + printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); + return; + } + + ath79_init_eth_pll_data(id); + + if (id == 0) + pdev = &ath79_eth0_device; + else + pdev = &ath79_eth1_device; + + pdata = pdev->dev.platform_data; + + pdata->max_frame_len = 1540; + pdata->desc_pktlen_mask = 0xfff; + + err = ath79_setup_phy_if_mode(id, pdata); + if (err) { + printk(KERN_ERR + "ar71xx: invalid PHY interface mode for GE%u\n", id); + return; + } + + switch (ath79_soc) { + case ATH79_SOC_AR7130: + if (id == 0) { + pdata->ddr_flush = ath79_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_ge0; + } else { + pdata->ddr_flush = ath79_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_ge1; + } + break; + + case ATH79_SOC_AR7141: + case ATH79_SOC_AR7161: + if (id == 0) { + pdata->ddr_flush = ath79_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_ge0; + } else { + pdata->ddr_flush = ath79_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_ge1; + } + pdata->has_gbit = 1; + break; + + case ATH79_SOC_AR7242: + if (id == 0) { + pdata->reset_bit |= AR724X_RESET_GE0_MDIO | + AR71XX_RESET_GE0_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge0; + pdata->set_speed = ar7242_set_speed_ge0; + } else { + pdata->reset_bit |= AR724X_RESET_GE1_MDIO | + AR71XX_RESET_GE1_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + } + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR7241: + if (id == 0) + pdata->reset_bit |= AR724X_RESET_GE0_MDIO; + else + pdata->reset_bit |= AR724X_RESET_GE1_MDIO; + /* fall through */ + case ATH79_SOC_AR7240: + if (id == 0) { + pdata->reset_bit |= AR71XX_RESET_GE0_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit |= AR71XX_RESET_GE1_PHY; + pdata->ddr_flush = ar724x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + if (ath79_soc == ATH79_SOC_AR7240) + pdata->is_ar7240 = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR9130: + if (id == 0) { + pdata->ddr_flush = ar91xx_ddr_flush_ge0; + pdata->set_speed = ar91xx_set_speed_ge0; + } else { + pdata->ddr_flush = ar91xx_ddr_flush_ge1; + pdata->set_speed = ar91xx_set_speed_ge1; + } + pdata->is_ar91xx = 1; + break; + + case ATH79_SOC_AR9132: + if (id == 0) { + pdata->ddr_flush = ar91xx_ddr_flush_ge0; + pdata->set_speed = ar91xx_set_speed_ge0; + } else { + pdata->ddr_flush = ar91xx_ddr_flush_ge1; + pdata->set_speed = ar91xx_set_speed_ge1; + } + pdata->is_ar91xx = 1; + pdata->has_gbit = 1; + break; + + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + if (id == 0) { + pdata->reset_bit = AR933X_RESET_GE0_MAC | + AR933X_RESET_GE0_MDIO; + pdata->ddr_flush = ar933x_ddr_flush_ge0; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit = AR933X_RESET_GE1_MAC | + AR933X_RESET_GE1_MDIO; + pdata->ddr_flush = ar933x_ddr_flush_ge1; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->has_gbit = 1; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: + if (id == 0) { + pdata->reset_bit = AR934X_RESET_GE0_MAC | + AR934X_RESET_GE0_MDIO; + pdata->set_speed = ar934x_set_speed_ge0; + } else { + pdata->reset_bit = AR934X_RESET_GE1_MAC | + AR934X_RESET_GE1_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->switch_data = &ath79_switch_data; + + /* reset the built-in switch */ + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH); + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + pdata->max_frame_len = SZ_16K - 1; + pdata->desc_pktlen_mask = SZ_16K - 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + if (id == 0) { + pdata->reset_bit = AR933X_RESET_GE0_MAC | + AR933X_RESET_GE0_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + if (!pdata->phy_mask) + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit = AR933X_RESET_GE1_MAC | + AR933X_RESET_GE1_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + if (id == 0) { + pdata->reset_bit = QCA955X_RESET_GE0_MAC | + QCA955X_RESET_GE0_MDIO; + pdata->set_speed = qca955x_set_speed_xmii; + } else { + pdata->reset_bit = QCA955X_RESET_GE1_MAC | + QCA955X_RESET_GE1_MDIO; + pdata->set_speed = qca955x_set_speed_sgmii; + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + /* + * Limit the maximum frame length to 4095 bytes. + * Although the documentation says that the hardware + * limit is 16383 bytes but that does not work in + * practice. It seems that the hardware only updates + * the lowest 12 bits of the packet length field + * in the RX descriptor. + */ + pdata->max_frame_len = SZ_4K - 1; + pdata->desc_pktlen_mask = SZ_16K - 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + + default: + BUG(); + } + + switch (pdata->phy_if_mode) { + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_SGMII: + if (!pdata->has_gbit) { + printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", + id); + return; + } + /* fallthrough */ + default: + break; + } + + if (!is_valid_ether_addr(pdata->mac_addr)) { + random_ether_addr(pdata->mac_addr); + printk(KERN_DEBUG + "ar71xx: using random MAC address for eth%d\n", + ath79_eth_instance); + } + + if (pdata->mii_bus_dev == NULL) { + switch (ath79_soc) { + case ATH79_SOC_AR9341: + case ATH79_SOC_AR9342: + case ATH79_SOC_AR9344: + if (id == 0) + pdata->mii_bus_dev = &ath79_mdio0_device.dev; + else + pdata->mii_bus_dev = &ath79_mdio1_device.dev; + break; + + case ATH79_SOC_AR7241: + case ATH79_SOC_AR9330: + case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: + case ATH79_SOC_QCA9561: + case ATH79_SOC_TP9343: + pdata->mii_bus_dev = &ath79_mdio1_device.dev; + break; + + case ATH79_SOC_QCA9556: + case ATH79_SOC_QCA9558: + /* don't assign any MDIO device by default */ + break; + + default: + pdata->mii_bus_dev = &ath79_mdio0_device.dev; + break; + } + } + + /* Reset the device */ + ath79_device_reset_set(pdata->reset_bit); + msleep(100); + + ath79_device_reset_clear(pdata->reset_bit); + msleep(100); + + platform_device_register(pdev); + ath79_eth_instance++; +} + +void __init ath79_set_mac_base(unsigned char *mac) +{ + memcpy(ath79_mac_base, mac, ETH_ALEN); +} + +void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac) +{ + int t; + + t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + + if (t != ETH_ALEN) + t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + + if (t != ETH_ALEN || !is_valid_ether_addr(mac)) { + memset(mac, 0, ETH_ALEN); + printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n", + mac_str); + } +} + +static void __init ath79_set_mac_base_ascii(char *str) +{ + u8 mac[ETH_ALEN]; + + ath79_parse_ascii_mac(str, mac); + ath79_set_mac_base(mac); +} + +static int __init ath79_ethaddr_setup(char *str) +{ + ath79_set_mac_base_ascii(str); + return 1; +} +__setup("ethaddr=", ath79_ethaddr_setup); + +static int __init ath79_kmac_setup(char *str) +{ + ath79_set_mac_base_ascii(str); + return 1; +} +__setup("kmac=", ath79_kmac_setup); + +void __init ath79_init_mac(unsigned char *dst, const unsigned char *src, + int offset) +{ + int t; + + if (!dst) + return; + + if (!src || !is_valid_ether_addr(src)) { + memset(dst, '\0', ETH_ALEN); + return; + } + + t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]); + t += offset; + + dst[0] = src[0]; + dst[1] = src[1]; + dst[2] = src[2]; + dst[3] = (t >> 16) & 0xff; + dst[4] = (t >> 8) & 0xff; + dst[5] = t & 0xff; +} + +void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src) +{ + int i; + + if (!dst) + return; + + if (!src || !is_valid_ether_addr(src)) { + memset(dst, '\0', ETH_ALEN); + return; + } + + for (i = 0; i < ETH_ALEN; i++) + dst[i] = src[i]; + dst[0] |= 0x02; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h new file mode 100644 index 0000000..5a226e4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h @@ -0,0 +1,53 @@ +/* + * Atheros AR71xx SoC device definitions + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_ETH_H +#define _ATH79_DEV_ETH_H + +#include + +struct platform_device; + +extern unsigned char ath79_mac_base[] __initdata; +void ath79_parse_ascii_mac(char *mac_str, u8 *mac); +void ath79_init_mac(unsigned char *dst, const unsigned char *src, + int offset); +void ath79_init_local_mac(unsigned char *dst, const unsigned char *src); + +struct ath79_eth_pll_data { + u32 pll_10; + u32 pll_100; + u32 pll_1000; +}; + +extern struct ath79_eth_pll_data ath79_eth0_pll_data; +extern struct ath79_eth_pll_data ath79_eth1_pll_data; + +extern struct ag71xx_platform_data ath79_eth0_data; +extern struct ag71xx_platform_data ath79_eth1_data; +extern struct platform_device ath79_eth0_device; +extern struct platform_device ath79_eth1_device; +void ath79_register_eth(unsigned int id); + +extern struct ag71xx_switch_platform_data ath79_switch_data; + +extern struct ag71xx_mdio_platform_data ath79_mdio0_data; +extern struct ag71xx_mdio_platform_data ath79_mdio1_data; +extern struct platform_device ath79_mdio0_device; +extern struct platform_device ath79_mdio1_device; +void ath79_register_mdio(unsigned int id, u32 phy_mask); + +void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio); +void ath79_setup_ar934x_eth_cfg(u32 mask); +void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv); +void ath79_setup_qca955x_eth_cfg(u32 mask); + +#endif /* _ATH79_DEV_ETH_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c new file mode 100644 index 0000000..9323b31 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include "dev-spi.h" +#include "dev-m25p80.h" + +static struct ath79_spi_controller_data ath79_spi0_cdata = +{ + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 0, +}; + +static struct ath79_spi_controller_data ath79_spi1_cdata = +{ + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 1, +}; + +static struct spi_board_info ath79_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ath79_spi0_cdata, + }, + { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ath79_spi1_cdata, + } +}; + +static struct ath79_spi_platform_data ath79_spi_data; + +void __init ath79_register_m25p80(struct flash_platform_data *pdata) +{ + ath79_spi_data.bus_num = 0; + ath79_spi_data.num_chipselect = 1; + ath79_spi0_cdata.is_flash = true; + ath79_spi_info[0].platform_data = pdata; + ath79_register_spi(&ath79_spi_data, ath79_spi_info, 1); +} + +static struct flash_platform_data *multi_pdata; + +static struct mtd_info *concat_devs[2] = { NULL, NULL }; +static struct work_struct mtd_concat_work; + +static void mtd_concat_add_work(struct work_struct *work) +{ + struct mtd_info *mtd; + + mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash"); + + mtd_device_register(mtd, multi_pdata->parts, multi_pdata->nr_parts); +} + +static void mtd_concat_add(struct mtd_info *mtd) +{ + static bool registered = false; + + if (registered) + return; + + if (!strcmp(mtd->name, "spi0.0")) + concat_devs[0] = mtd; + else if (!strcmp(mtd->name, "spi0.1")) + concat_devs[1] = mtd; + else + return; + + if (!concat_devs[0] || !concat_devs[1]) + return; + + registered = true; + INIT_WORK(&mtd_concat_work, mtd_concat_add_work); + schedule_work(&mtd_concat_work); +} + +static void mtd_concat_remove(struct mtd_info *mtd) +{ +} + +static void add_mtd_concat_notifier(void) +{ + static struct mtd_notifier not = { + .add = mtd_concat_add, + .remove = mtd_concat_remove, + }; + + register_mtd_user(¬); +} + + +void __init ath79_register_m25p80_multi(struct flash_platform_data *pdata) +{ + multi_pdata = pdata; + add_mtd_concat_notifier(); + ath79_spi_data.bus_num = 0; + ath79_spi_data.num_chipselect = 2; + ath79_spi0_cdata.is_flash = true; + ath79_register_spi(&ath79_spi_data, ath79_spi_info, 2); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h new file mode 100644 index 0000000..637b41a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-m25p80.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_M25P80_H +#define _ATH79_DEV_M25P80_H + +#include + +void ath79_register_m25p80(struct flash_platform_data *pdata) __init; +void ath79_register_m25p80_multi(struct flash_platform_data *pdata) __init; + +#endif /* _ATH79_DEV_M25P80_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c new file mode 100644 index 0000000..9b5256e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.c @@ -0,0 +1,141 @@ +/* + * Atheros AR934X SoCs built-in NAND flash controller support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "dev-nfc.h" + +static struct resource ath79_nfc_resources[2]; +static u64 ar934x_nfc_dmamask = DMA_BIT_MASK(32); +static struct ar934x_nfc_platform_data ath79_nfc_data; + +static struct platform_device ath79_nfc_device = { + .name = AR934X_NFC_DRIVER_NAME, + .id = -1, + .resource = ath79_nfc_resources, + .num_resources = ARRAY_SIZE(ath79_nfc_resources), + .dev = { + .dma_mask = &ar934x_nfc_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &ath79_nfc_data, + }, +}; + +static void __init ath79_nfc_init_resource(struct resource res[2], + unsigned long base, + unsigned long size, + int irq) +{ + memset(res, 0, sizeof(struct resource) * 2); + + res[0].flags = IORESOURCE_MEM; + res[0].start = base; + res[0].end = base + size - 1; + + res[1].flags = IORESOURCE_IRQ; + res[1].start = irq; + res[1].end = irq; +} + +static void ar934x_nfc_hw_reset(bool active) +{ + if (active) { + ath79_device_reset_set(AR934X_RESET_NANDF); + udelay(100); + + ath79_device_reset_set(AR934X_RESET_ETH_SWITCH_ANALOG); + udelay(250); + } else { + ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH_ANALOG); + udelay(250); + + ath79_device_reset_clear(AR934X_RESET_NANDF); + udelay(100); + } +} + +static void ar934x_nfc_setup(void) +{ + ath79_nfc_data.hw_reset = ar934x_nfc_hw_reset; + + ath79_nfc_init_resource(ath79_nfc_resources, + AR934X_NFC_BASE, AR934X_NFC_SIZE, + ATH79_MISC_IRQ(21)); + + platform_device_register(&ath79_nfc_device); +} + +static void qca955x_nfc_hw_reset(bool active) +{ + if (active) { + ath79_device_reset_set(QCA955X_RESET_NANDF); + udelay(250); + } else { + ath79_device_reset_clear(QCA955X_RESET_NANDF); + udelay(100); + } +} + +static void qca955x_nfc_setup(void) +{ + ath79_nfc_data.hw_reset = qca955x_nfc_hw_reset; + + ath79_nfc_init_resource(ath79_nfc_resources, + QCA955X_NFC_BASE, QCA955X_NFC_SIZE, + ATH79_MISC_IRQ(21)); + + platform_device_register(&ath79_nfc_device); +} + +void __init ath79_nfc_set_select_chip(void (*f)(int chip_no)) +{ + ath79_nfc_data.select_chip = f; +} + +void __init ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)) +{ + ath79_nfc_data.scan_fixup = f; +} + +void __init ath79_nfc_set_swap_dma(bool enable) +{ + ath79_nfc_data.swap_dma = enable; +} + +void __init ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode) +{ + ath79_nfc_data.ecc_mode = mode; +} + +void __init ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts) +{ + ath79_nfc_data.parts = parts; + ath79_nfc_data.nr_parts = nr_parts; +} + +void __init ath79_register_nfc(void) +{ + if (soc_is_ar934x()) + ar934x_nfc_setup(); + else if (soc_is_qca955x()) + qca955x_nfc_setup(); + else + BUG(); +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h new file mode 100644 index 0000000..3a1c88f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-nfc.h @@ -0,0 +1,34 @@ +/* + * Atheros AR934X SoCs built-in NAND Flash Controller support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_DEV_NFC_H +#define _ATH79_DEV_NFC_H + +struct mtd_partition; +enum ar934x_nfc_ecc_mode; + +#ifdef CONFIG_ATH79_DEV_NFC +void ath79_nfc_set_parts(struct mtd_partition *parts, int nr_parts); +void ath79_nfc_set_select_chip(void (*f)(int chip_no)); +void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)); +void ath79_nfc_set_swap_dma(bool enable); +void ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode); +void ath79_register_nfc(void); +#else +static inline void ath79_nfc_set_parts(struct mtd_partition *parts, + int nr_parts) {} +static inline void ath79_nfc_set_select_chip(void (*f)(int chip_no)) {} +static inline void ath79_nfc_set_scan_fixup(int (*f)(struct mtd_info *mtd)) {} +static inline void ath79_nfc_set_swap_dma(bool enable) {} +static inline void ath79_nfc_set_ecc_mode(enum ar934x_nfc_ecc_mode mode) {} +static inline void ath79_register_nfc(void) {} +#endif + +#endif /* _ATH79_DEV_NFC_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c new file mode 100644 index 0000000..f7cd6ae --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-ap96.c @@ -0,0 +1,151 @@ +/* + * ALFA Network AP96 board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define ALFA_AP96_GPIO_PCIE_RESET 2 +#define ALFA_AP96_GPIO_SIM_DETECT 3 +#define ALFA_AP96_GPIO_MICROSD_CD 4 +#define ALFA_AP96_GPIO_PCIE_W_DISABLE 5 + +#define ALFA_AP96_GPIO_BUTTON_RESET 11 + +#define ALFA_AP96_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALFA_AP96_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_AP96_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button alfa_ap96_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALFA_AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALFA_AP96_GPIO_BUTTON_RESET, + .active_low = 1, + } +}; + +static struct mmc_spi_platform_data alfa_ap96_mmc_data = { + .flags = MMC_SPI_USE_CD_GPIO, + .cd_gpio = ALFA_AP96_GPIO_MICROSD_CD, + .cd_debounce = 1, + .caps = MMC_CAP_NEEDS_POLL, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct ath79_spi_controller_data ap96_spi0_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 0, + .is_flash = true, +}; + +static struct ath79_spi_controller_data ap96_spi1_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 1, +}; + +static struct ath79_spi_controller_data ap96_spi2_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 2, +}; + +static struct spi_board_info alfa_ap96_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .controller_data = &ap96_spi0_cdata + }, { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "mmc_spi", + .platform_data = &alfa_ap96_mmc_data, + .controller_data = &ap96_spi1_cdata + }, { + .bus_num = 0, + .chip_select = 2, + .max_speed_hz = 6250000, + .modalias = "rtc-pcf2123", + .controller_data = &ap96_spi2_cdata + }, +}; + +static struct ath79_spi_platform_data alfa_ap96_spi_data = { + .bus_num = 0, + .num_chipselect = 3, +}; + +static void __init alfa_ap96_gpio_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD"); + gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD); + gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset"); + gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1); + gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable"); + gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1); +} + +#define ALFA_AP96_WAN_PHYMASK BIT(4) +#define ALFA_AP96_LAN_PHYMASK BIT(5) +#define ALFA_AP96_MDIO_PHYMASK (ALFA_AP96_LAN_PHYMASK | ALFA_AP96_WAN_PHYMASK) + +static void __init alfa_ap96_init(void) +{ + alfa_ap96_gpio_setup(); + + ath79_register_mdio(0, ~ALFA_AP96_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK; + ath79_eth1_pll_data.pll_1000 = 0x110000; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK; + ath79_eth1_pll_data.pll_1000 = 0x110000; + + ath79_register_eth(1); + + ath79_register_pci(); + ath79_register_spi(&alfa_ap96_spi_data, alfa_ap96_spi_info, + ARRAY_SIZE(alfa_ap96_spi_info)); + + ath79_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL, + ARRAY_SIZE(alfa_ap96_gpio_keys), + alfa_ap96_gpio_keys); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_ALFA_AP96, "ALFA-AP96", "ALFA Network AP96", + alfa_ap96_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c new file mode 100644 index 0000000..a515f4f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-alfa-nx.c @@ -0,0 +1,113 @@ +/* + * ALFA Network N2/N5 board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define ALFA_NX_GPIO_LED_2 17 +#define ALFA_NX_GPIO_LED_3 16 +#define ALFA_NX_GPIO_LED_5 12 +#define ALFA_NX_GPIO_LED_6 8 +#define ALFA_NX_GPIO_LED_7 6 +#define ALFA_NX_GPIO_LED_8 7 + +#define ALFA_NX_GPIO_BTN_RESET 11 + +#define ALFA_NX_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALFA_NX_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_NX_KEYS_POLL_INTERVAL) + +#define ALFA_NX_MAC0_OFFSET 0 +#define ALFA_NX_MAC1_OFFSET 6 +#define ALFA_NX_CALDATA_OFFSET 0x1000 + +static struct gpio_keys_button alfa_nx_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALFA_NX_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALFA_NX_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct gpio_led alfa_nx_leds_gpio[] __initdata = { + { + .name = "alfa:green:led_2", + .gpio = ALFA_NX_GPIO_LED_2, + .active_low = 1, + }, { + .name = "alfa:green:led_3", + .gpio = ALFA_NX_GPIO_LED_3, + .active_low = 1, + }, { + .name = "alfa:red:led_5", + .gpio = ALFA_NX_GPIO_LED_5, + .active_low = 1, + }, { + .name = "alfa:amber:led_6", + .gpio = ALFA_NX_GPIO_LED_6, + .active_low = 1, + }, { + .name = "alfa:green:led_7", + .gpio = ALFA_NX_GPIO_LED_7, + .active_low = 1, + }, { + .name = "alfa:green:led_8", + .gpio = ALFA_NX_GPIO_LED_8, + .active_low = 1, + } +}; + +static void __init alfa_nx_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(0, ARRAY_SIZE(alfa_nx_leds_gpio), + alfa_nx_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALFA_NX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(alfa_nx_gpio_keys), + alfa_nx_gpio_keys); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + ALFA_NX_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, + art + ALFA_NX_MAC1_OFFSET, 0); + + /* WAN port */ + ath79_register_eth(0); + /* LAN port */ + ath79_register_eth(1); + + ap91_pci_init(art + ALFA_NX_CALDATA_OFFSET, NULL); +} + +MIPS_MACHINE(ATH79_MACH_ALFA_NX, "ALFA-NX", "ALFA Network N2/N5", + alfa_nx_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c new file mode 100644 index 0000000..2495bcb --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0258n.c @@ -0,0 +1,88 @@ +/* + * Allnet ALL0258N support + * + * Copyright (C) 2011 Daniel Golle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +/* found via /sys/gpio/... try and error */ +#define ALL0258N_GPIO_BTN_RESET 1 +#define ALL0258N_GPIO_LED_RSSIHIGH 13 +#define ALL0258N_GPIO_LED_RSSIMEDIUM 15 +#define ALL0258N_GPIO_LED_RSSILOW 14 + +/* defaults taken from others machs */ +#define ALL0258N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALL0258N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0258N_KEYS_POLL_INTERVAL) + +/* showed up in the original firmware's bootlog */ +#define ALL0258N_SEC_PHYMASK BIT(3) + +static struct gpio_led all0258n_leds_gpio[] __initdata = { + { + .name = "all0258n:green:rssihigh", + .gpio = ALL0258N_GPIO_LED_RSSIHIGH, + .active_low = 1, + }, { + .name = "all0258n:yellow:rssimedium", + .gpio = ALL0258N_GPIO_LED_RSSIMEDIUM, + .active_low = 1, + }, { + .name = "all0258n:red:rssilow", + .gpio = ALL0258N_GPIO_LED_RSSILOW, + .active_low = 1, + } +}; + +static struct gpio_keys_button all0258n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALL0258N_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALL0258N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init all0258n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f7f0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1f7f1000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(all0258n_leds_gpio), + all0258n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALL0258N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(all0258n_gpio_keys), + all0258n_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + ath79_eth1_data.phy_mask = ALL0258N_SEC_PHYMASK; + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ALL0258N, "ALL0258N", "Allnet ALL0258N", + all0258n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c new file mode 100644 index 0000000..387ee7f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-all0315n.c @@ -0,0 +1,85 @@ +/* + * Allnet ALL0315N support + * + * Copyright (C) 2012 Daniel Golle + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" +#include "pci.h" + +#define ALL0315N_GPIO_BTN_RESET 0 +#define ALL0315N_GPIO_LED_RSSIHIGH 14 +#define ALL0315N_GPIO_LED_RSSIMEDIUM 15 +#define ALL0315N_GPIO_LED_RSSILOW 16 + +#define ALL0315N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ALL0315N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0315N_KEYS_POLL_INTERVAL) + +static struct gpio_led all0315n_leds_gpio[] __initdata = { + { + .name = "all0315n:green:rssihigh", + .gpio = ALL0315N_GPIO_LED_RSSIHIGH, + .active_low = 1, + }, { + .name = "all0315n:yellow:rssimedium", + .gpio = ALL0315N_GPIO_LED_RSSIMEDIUM, + .active_low = 1, + }, { + .name = "all0315n:red:rssilow", + .gpio = ALL0315N_GPIO_LED_RSSILOW, + .active_low = 1, + } +}; + +static struct gpio_keys_button all0315n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ALL0315N_KEYS_DEBOUNCE_INTERVAL, + .gpio = ALL0315N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init all0315n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffc0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1ffc1000); + + ath79_register_m25p80(NULL); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(all0315n_leds_gpio), + all0315n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ALL0315N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(all0315n_gpio_keys), + all0315n_gpio_keys); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap91_pci_init(ee, NULL); +} + +MIPS_MACHINE(ATH79_MACH_ALL0315N, "ALL0315N", "Allnet ALL0315N", + all0315n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s1.c new file mode 100644 index 0000000..0a81227 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s1.c @@ -0,0 +1,98 @@ +/* + * Bitmain Antminer S1 board support + * + * Copyright (C) 2015 L. D. Pinney + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "dev-usb.h" + +#define ANTMINER_S1_GPIO_BTN_RESET 11 + +#define ANTMINER_S1_GPIO_LED_SYSTEM 23 +#define ANTMINER_S1_GPIO_LED_WLAN 0 +#define ANTMINER_S1_GPIO_USB_POWER 26 + +#define ANTMINER_S1_KEYSPOLL_INTERVAL 20 /* msecs */ +#define ANTMINER_S1_KEYSDEBOUNCE_INTERVAL (3 * ANTMINER_S1_KEYSPOLL_INTERVAL) + +static const char *ANTMINER_S1_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data ANTMINER_S1_flash_data = { + .part_probes = ANTMINER_S1_part_probes, +}; + +static struct gpio_led ANTMINER_S1_leds_gpio[] __initdata = { + { + .name = "antminer-s1:green:system", + .gpio = ANTMINER_S1_GPIO_LED_SYSTEM, + .active_low = 0, + },{ + .name = "antminer-s1:green:wlan", + .gpio = ANTMINER_S1_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ANTMINER_S1_GPIO_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ANTMINER_S1_KEYSDEBOUNCE_INTERVAL, + .gpio = ANTMINER_S1_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static void __init antminer_s1_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S1_leds_gpio), + ANTMINER_S1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ANTMINER_S1_KEYSPOLL_INTERVAL, + ARRAY_SIZE(ANTMINER_S1_GPIO_keys), + ANTMINER_S1_GPIO_keys); + + gpio_request_one(ANTMINER_S1_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_m25p80(&ANTMINER_S1_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ANTMINER_S1, "ANTMINER-S1", + "Antminer-S1", antminer_s1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s3.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s3.c new file mode 100644 index 0000000..b77a6cc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-antminer-s3.c @@ -0,0 +1,103 @@ +/* + * Bitmain Antminer S3 board support + * + * Copyright (C) 2015 L. D. Pinney + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "dev-usb.h" + +#define ANTMINER_S3_GPIO_LED_WLAN 0 +#define ANTMINER_S3_GPIO_LED_SYSTEM 17 +#define ANTMINER_S3_GPIO_LED_LAN 22 +#define ANTMINER_S3_GPIO_USB_POWER 26 + +#define ANTMINER_S3_GPIO_BTN_RESET 11 + +#define ANTMINER_S3_KEYSPOLL_INTERVAL 88 /* msecs */ +#define ANTMINER_S3_KEYSDEBOUNCE_INTERVAL (3 * ANTMINER_S3_KEYSPOLL_INTERVAL) + +static const char *ANTMINER_S3_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data ANTMINER_S3_flash_data = { + .part_probes = ANTMINER_S3_part_probes, +}; + +static struct gpio_led ANTMINER_S3_leds_gpio[] __initdata = { + { + .name = "antminer-s3:green:wlan", + .gpio = ANTMINER_S3_GPIO_LED_WLAN, + .active_low = 0, + },{ + .name = "antminer-s3:green:system", + .gpio = ANTMINER_S3_GPIO_LED_SYSTEM, + .active_low = 0, + },{ + .name = "antminer-s3:yellow:lan", + .gpio = ANTMINER_S3_GPIO_LED_LAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ANTMINER_S3_GPIO_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ANTMINER_S3_KEYSDEBOUNCE_INTERVAL, + .gpio = ANTMINER_S3_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static void __init antminer_s3_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ANTMINER_S3_leds_gpio), + ANTMINER_S3_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ANTMINER_S3_KEYSPOLL_INTERVAL, + ARRAY_SIZE(ANTMINER_S3_GPIO_keys), + ANTMINER_S3_GPIO_keys); + + gpio_request_one(ANTMINER_S3_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_m25p80(&ANTMINER_S3_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ANTMINER_S3, "ANTMINER-S3", + "Antminer-S3", antminer_s3_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c new file mode 100644 index 0000000..9b38faa --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap113.c @@ -0,0 +1,84 @@ +/* + * Atheros AP113 board support + * + * Copyright (C) 2011 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "pci.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define AP113_GPIO_LED_USB 0 +#define AP113_GPIO_LED_STATUS 1 +#define AP113_GPIO_LED_ST 11 + +#define AP113_GPIO_BTN_JUMPSTART 12 + +#define AP113_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP113_KEYS_DEBOUNCE_INTERVAL (3 * AP113_KEYS_POLL_INTERVAL) + +static struct gpio_led ap113_leds_gpio[] __initdata = { + { + .name = "ap113:green:usb", + .gpio = AP113_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "ap113:green:status", + .gpio = AP113_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "ap113:green:st", + .gpio = AP113_GPIO_LED_ST, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap113_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP113_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP113_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, +}; + +static void __init ap113_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + ath79_register_gpio_keys_polled(-1, AP113_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap113_gpio_keys), + ap113_gpio_keys); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap113_leds_gpio), + ap113_leds_gpio); + + ath79_register_pci(); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_AP113, "AP113", "Atheros AP113", + ap113_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c new file mode 100644 index 0000000..86fd8bd --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap132.c @@ -0,0 +1,189 @@ +/* + * Atheros AP132 reference board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012 Gabor Juhos + * Copyright (c) 2013 Embedded Wireless GmbH + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define AP132_GPIO_LED_USB 4 +#define AP132_GPIO_LED_WLAN_5G 12 +#define AP132_GPIO_LED_WLAN_2G 13 +#define AP132_GPIO_LED_STATUS_RED 14 +#define AP132_GPIO_LED_WPS_RED 15 + +#define AP132_GPIO_BTN_WPS 16 + +#define AP132_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP132_KEYS_DEBOUNCE_INTERVAL (3 * AP132_KEYS_POLL_INTERVAL) + +#define AP132_MAC0_OFFSET 0 +#define AP132_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led ap132_leds_gpio[] __initdata = { + { + .name = "ap132:red:status", + .gpio = AP132_GPIO_LED_STATUS_RED, + .active_low = 1, + }, + { + .name = "ap132:red:wps", + .gpio = AP132_GPIO_LED_WPS_RED, + .active_low = 1, + }, + { + .name = "ap132:red:wlan-2g", + .gpio = AP132_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "ap132:red:usb", + .gpio = AP132_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap132_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP132_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP132_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg ap132_ar8327_pad0_cfg; + +static struct ar8327_platform_data ap132_ar8327_data = { + .pad0_cfg = &ap132_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info ap132_mdio1_info[] = { + { + .bus_id = "ag71xx-mdio.1", + .phy_addr = 0, + .platform_data = &ap132_ar8327_data, + }, +}; + +static void __init ap132_mdio_setup(void) +{ + void __iomem *base; + u32 t; + +#define GPIO_IN_ENABLE3_ADDRESS 0x0050 +#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000 +#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16 +#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK) +#define GPIO_OUT_FUNCTION4_ADDRESS 0x003c +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK) +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) + + base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + + t = __raw_readl(base + GPIO_IN_ENABLE3_ADDRESS); + t &= ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK; + t |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19); + __raw_writel(t, base + GPIO_IN_ENABLE3_ADDRESS); + + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 19), base + AR71XX_GPIO_REG_OE); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 17), base + AR71XX_GPIO_REG_OE); + + + t = __raw_readl(base + GPIO_OUT_FUNCTION4_ADDRESS); + t &= ~(GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK); + t |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21); + __raw_writel(t, base + GPIO_OUT_FUNCTION4_ADDRESS); + + iounmap(base); + +} + +static void __init ap132_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap132_leds_gpio), + ap132_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP132_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap132_gpio_keys), + ap132_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + AP132_WMAC_CALDATA_OFFSET, NULL); + + /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ + ap132_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; + ap132_ar8327_pad0_cfg.sgmii_delay_en = true; + + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ap132_mdio_setup(); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth1_data.mac_addr, art + AP132_MAC0_OFFSET, 0); + + mdiobus_register_board_info(ap132_mdio1_info, + ARRAY_SIZE(ap132_mdio1_info)); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_data.phy_mask = BIT(0); + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_AP132, "AP132", + "Atheros AP132 reference board", + ap132_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap143.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap143.c new file mode 100644 index 0000000..098420b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap143.c @@ -0,0 +1,142 @@ +/* + * Atheros AP143 reference board support + * + * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved. + * Copyright (c) 2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define AP143_GPIO_LED_WLAN 12 +#define AP143_GPIO_LED_WPS 13 +#define AP143_GPIO_LED_STATUS 13 + +#define AP143_GPIO_LED_WAN 4 +#define AP143_GPIO_LED_LAN1 16 +#define AP143_GPIO_LED_LAN2 15 +#define AP143_GPIO_LED_LAN3 14 +#define AP143_GPIO_LED_LAN4 11 + +#define AP143_GPIO_BTN_WPS 17 + +#define AP143_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP143_KEYS_DEBOUNCE_INTERVAL (3 * AP143_KEYS_POLL_INTERVAL) + +#define AP143_MAC0_OFFSET 0 +#define AP143_MAC1_OFFSET 6 +#define AP143_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led ap143_leds_gpio[] __initdata = { + { + .name = "ap143:green:status", + .gpio = AP143_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "ap143:green:wlan", + .gpio = AP143_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap143_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP143_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP143_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static void __init ap143_gpio_led_setup(void) +{ + ath79_gpio_direction_select(AP143_GPIO_LED_WAN, true); + ath79_gpio_direction_select(AP143_GPIO_LED_LAN1, true); + ath79_gpio_direction_select(AP143_GPIO_LED_LAN2, true); + ath79_gpio_direction_select(AP143_GPIO_LED_LAN3, true); + ath79_gpio_direction_select(AP143_GPIO_LED_LAN4, true); + + ath79_gpio_output_select(AP143_GPIO_LED_WAN, + QCA953X_GPIO_OUT_MUX_LED_LINK5); + ath79_gpio_output_select(AP143_GPIO_LED_LAN1, + QCA953X_GPIO_OUT_MUX_LED_LINK1); + ath79_gpio_output_select(AP143_GPIO_LED_LAN2, + QCA953X_GPIO_OUT_MUX_LED_LINK2); + ath79_gpio_output_select(AP143_GPIO_LED_LAN3, + QCA953X_GPIO_OUT_MUX_LED_LINK3); + ath79_gpio_output_select(AP143_GPIO_LED_LAN4, + QCA953X_GPIO_OUT_MUX_LED_LINK4); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap143_leds_gpio), + ap143_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP143_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap143_gpio_keys), + ap143_gpio_keys); +} + +static void __init ap143_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ap143_gpio_led_setup(); + + ath79_register_usb(); + + ath79_wmac_set_led_pin(AP143_GPIO_LED_WLAN); + ath79_register_wmac(art + AP143_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_mdio(0, 0x0); + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP143_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + AP143_MAC1_OFFSET, 0); + + /* WAN port */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(4); + ath79_register_eth(0); + + /* LAN ports */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_switch_data.phy4_mii_en = 1; + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_AP143, "AP143", "Qualcomm Atheros AP143 reference board", + ap143_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap147.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap147.c new file mode 100644 index 0000000..7b45da4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap147.c @@ -0,0 +1,125 @@ +/* + * Atheros AP147 reference board support + * + * Copyright (C) 2014 Matthias Schiffer + * Copyright (C) 2015 Sven Eckelmann + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define AP147_GPIO_LED_WAN 4 +#define AP147_GPIO_LED_LAN1 16 +#define AP147_GPIO_LED_LAN2 15 +#define AP147_GPIO_LED_LAN3 14 +#define AP147_GPIO_LED_LAN4 11 +#define AP147_GPIO_LED_STATUS 13 +#define AP147_GPIO_LED_WLAN_2G 12 + +#define AP147_GPIO_BTN_WPS 17 + +#define AP147_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP147_KEYS_DEBOUNCE_INTERVAL (3 * AP147_KEYS_POLL_INTERVAL) + +#define AP147_MAC0_OFFSET 0x1000 + +static struct gpio_led ap147_leds_gpio[] __initdata = { + { + .name = "ap147:green:status", + .gpio = AP147_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "ap147:green:wlan-2g", + .gpio = AP147_GPIO_LED_WLAN_2G, + .active_low = 1, + }, { + .name = "ap147:green:lan1", + .gpio = AP147_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "ap147:green:lan2", + .gpio = AP147_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "ap147:green:lan3", + .gpio = AP147_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "ap147:green:lan4", + .gpio = AP147_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "ap147:green:wan", + .gpio = AP147_GPIO_LED_WAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button ap147_gpio_keys[] __initdata = { + { + .desc = "wps button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP147_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP147_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init ap147_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap147_leds_gpio), + ap147_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP147_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap147_gpio_keys), + ap147_gpio_keys); + + ath79_register_usb(); + + ath79_register_pci(); + + ath79_register_wmac(art + AP147_MAC0_OFFSET, NULL); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_mdio(0, 0x0); + + /* LAN */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_init_mac(ath79_eth1_data.mac_addr, art, 0); + ath79_register_eth(1); + + /* WAN */ + ath79_switch_data.phy4_mii_en = 1; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.phy_mask = BIT(4); + ath79_init_mac(ath79_eth0_data.mac_addr, art, 1); + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_AP147_010, "AP147-010", "Atheros AP147-010 reference board", ap147_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c new file mode 100644 index 0000000..a1eb06b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap152.c @@ -0,0 +1,141 @@ + +/* + * Qualcomm Atheros AP152 reference board support + * + * Copyright (c) 2015 Qualcomm Atheros + * Copyright (c) 2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include "common.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" + +#define AP152_GPIO_LED_USB0 7 +#define AP152_GPIO_LED_USB1 8 + +#define AP152_GPIO_BTN_RESET 2 +#define AP152_GPIO_BTN_WPS 1 +#define AP152_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP152_KEYS_DEBOUNCE_INTERVAL (3 * AP152_KEYS_POLL_INTERVAL) + +#define AP152_MAC0_OFFSET 0 +#define AP152_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led ap152_leds_gpio[] __initdata = { + { + .name = "ap152:green:usb0", + .gpio = AP152_GPIO_LED_USB0, + .active_low = 1, + }, + { + .name = "ap152:green:usb1", + .gpio = AP152_GPIO_LED_USB1, + .active_low = 1, + }, +}; + +static struct gpio_keys_button ap152_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP152_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP152_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP152_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg ap152_ar8337_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +static struct ar8327_platform_data ap152_ar8337_data = { + .pad0_cfg = &ap152_ar8337_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info ap152_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &ap152_ar8337_data, + }, +}; + +static void __init ap152_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap152_leds_gpio), + ap152_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP152_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap152_gpio_keys), + ap152_gpio_keys); + + ath79_register_usb(); + + platform_device_register(&ath79_mdio0_device); + + mdiobus_register_board_info(ap152_mdio0_info, + ARRAY_SIZE(ap152_mdio0_info)); + + ath79_register_wmac(art + AP152_WMAC_CALDATA_OFFSET, NULL); + ath79_register_pci(); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + AP152_MAC0_OFFSET, 0); + + /* GMAC0 is connected to an AR8337 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_AP152, "AP152", "Qualcomm Atheros AP152 reference board", + ap152_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c new file mode 100644 index 0000000..8519a9d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap83.c @@ -0,0 +1,275 @@ +/* + * Atheros AP83 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define AP83_GPIO_LED_WLAN 6 +#define AP83_GPIO_LED_POWER 14 +#define AP83_GPIO_LED_JUMPSTART 15 +#define AP83_GPIO_BTN_JUMPSTART 12 +#define AP83_GPIO_BTN_RESET 21 + +#define AP83_050_GPIO_VSC7385_CS 1 +#define AP83_050_GPIO_VSC7385_MISO 3 +#define AP83_050_GPIO_VSC7385_MOSI 16 +#define AP83_050_GPIO_VSC7385_SCK 17 + +#define AP83_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL) + +static struct mtd_partition ap83_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x040000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x060000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x1a0000, + .size = 0x650000, + }, { + .name = "art", + .offset = 0x7f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x060000, + .size = 0x790000, + } +}; + +static struct physmap_flash_data ap83_flash_data = { + .width = 2, + .parts = ap83_flash_partitions, + .nr_parts = ARRAY_SIZE(ap83_flash_partitions), +}; + +static struct resource ap83_flash_resources[] = { + [0] = { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ap83_flash_device = { + .name = "ar91xx-flash", + .id = -1, + .resource = ap83_flash_resources, + .num_resources = ARRAY_SIZE(ap83_flash_resources), + .dev = { + .platform_data = &ap83_flash_data, + } +}; + +static struct gpio_led ap83_leds_gpio[] __initdata = { + { + .name = "ap83:green:jumpstart", + .gpio = AP83_GPIO_LED_JUMPSTART, + .active_low = 0, + }, { + .name = "ap83:green:power", + .gpio = AP83_GPIO_LED_POWER, + .active_low = 0, + }, { + .name = "ap83:green:wlan", + .gpio = AP83_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button ap83_gpio_keys[] __initdata = { + { + .desc = "soft_reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP83_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "jumpstart", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP83_GPIO_BTN_JUMPSTART, + .active_low = 1, + } +}; + +static struct resource ap83_040_spi_resources[] = { + [0] = { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ap83_040_spi_device = { + .name = "ap83-spi", + .id = 0, + .resource = ap83_040_spi_resources, + .num_resources = ARRAY_SIZE(ap83_040_spi_resources), +}; + +static struct spi_gpio_platform_data ap83_050_spi_data = { + .miso = AP83_050_GPIO_VSC7385_MISO, + .mosi = AP83_050_GPIO_VSC7385_MOSI, + .sck = AP83_050_GPIO_VSC7385_SCK, + .num_chipselect = 1, +}; + +static struct platform_device ap83_050_spi_device = { + .name = "spi_gpio", + .id = 0, + .dev = { + .platform_data = &ap83_050_spi_data, + } +}; + +static void ap83_vsc7385_reset(void) +{ + ath79_device_reset_set(AR71XX_RESET_GE1_PHY); + udelay(10); + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); + mdelay(50); +} + +static struct vsc7385_platform_data ap83_vsc7385_data = { + .reset = ap83_vsc7385_reset, + .ucode_name = "vsc7385_ucode_ap83.bin", + .mac_cfg = { + .tx_ipg = 6, + .bit2 = 0, + .clk_sel = 3, + }, +}; + +static struct spi_board_info ap83_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "spi-vsc7385", + .platform_data = &ap83_vsc7385_data, + .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, + } +}; + +static void __init ap83_generic_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0xfffffffe); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = 0x1; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_eth1_pll_data.pll_1000 = 0x1f000000; + + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), + ap83_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AP83_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap83_gpio_keys), + ap83_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(eeprom, NULL); + + platform_device_register(&ap83_flash_device); + + spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); +} + +static void ap83_040_flash_lock(struct platform_device *pdev) +{ + ath79_flash_acquire(); +} + +static void ap83_040_flash_unlock(struct platform_device *pdev) +{ + ath79_flash_release(); +} + +static void __init ap83_040_setup(void) +{ + ap83_flash_data.lock = ap83_040_flash_lock; + ap83_flash_data.unlock = ap83_040_flash_unlock; + ap83_generic_setup(); + platform_device_register(&ap83_040_spi_device); +} + +static void __init ap83_050_setup(void) +{ + ap83_generic_setup(); + platform_device_register(&ap83_050_spi_device); +} + +static void __init ap83_setup(void) +{ + u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); + unsigned int board_version; + + board_version = (unsigned int)(board_id[0] - '0'); + board_version += ((unsigned int)(board_id[1] - '0')) * 10; + + switch (board_version) { + case 40: + ap83_040_setup(); + break; + case 50: + ap83_050_setup(); + break; + default: + printk(KERN_WARNING "AP83-%03u board is not yet supported\n", + board_version); + } +} + +MIPS_MACHINE(ATH79_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c new file mode 100644 index 0000000..35120d3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ap96.c @@ -0,0 +1,142 @@ +/* + * Atheros AP96 board support + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define AP96_GPIO_LED_12_GREEN 0 +#define AP96_GPIO_LED_3_GREEN 1 +#define AP96_GPIO_LED_2_GREEN 2 +#define AP96_GPIO_LED_WPS_GREEN 4 +#define AP96_GPIO_LED_5_GREEN 5 +#define AP96_GPIO_LED_4_ORANGE 6 + +/* Reset button - next to the power connector */ +#define AP96_GPIO_BTN_RESET 3 +/* WPS button - next to a led on right */ +#define AP96_GPIO_BTN_WPS 8 + +#define AP96_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL) + +#define AP96_WMAC0_MAC_OFFSET 0x120c +#define AP96_WMAC1_MAC_OFFSET 0x520c +#define AP96_CALDATA0_OFFSET 0x1000 +#define AP96_CALDATA1_OFFSET 0x5000 + +/* + * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12 + * below (from left to right on the board). Led 1 seems to be on whenever the + * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange; + * others are green. + * + * In addition, there is one led next to a button on the right side for WPS. + */ +static struct gpio_led ap96_leds_gpio[] __initdata = { + { + .name = "ap96:green:led2", + .gpio = AP96_GPIO_LED_2_GREEN, + .active_low = 1, + }, { + .name = "ap96:green:led3", + .gpio = AP96_GPIO_LED_3_GREEN, + .active_low = 1, + }, { + .name = "ap96:orange:led4", + .gpio = AP96_GPIO_LED_4_ORANGE, + .active_low = 1, + }, { + .name = "ap96:green:led5", + .gpio = AP96_GPIO_LED_5_GREEN, + .active_low = 1, + }, { + .name = "ap96:green:led12", + .gpio = AP96_GPIO_LED_12_GREEN, + .active_low = 1, + }, { /* next to a button on right */ + .name = "ap96:green:wps", + .gpio = AP96_GPIO_LED_WPS_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button ap96_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP96_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, + .gpio = AP96_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +#define AP96_WAN_PHYMASK 0x10 +#define AP96_LAN_PHYMASK 0x0f + +static void __init ap96_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = AP96_LAN_PHYMASK; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + + ath79_init_mac(ath79_eth1_data.mac_addr, art, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = AP96_WAN_PHYMASK; + + ath79_eth1_pll_data.pll_1000 = 0x1f000000; + + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio), + ap96_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap96_gpio_keys), + ap96_gpio_keys); + + ap94_pci_init(art + AP96_CALDATA0_OFFSET, + art + AP96_WMAC0_MAC_OFFSET, + art + AP96_CALDATA1_OFFSET, + art + AP96_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_AP96, "AP96", "Atheros AP96", ap96_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c new file mode 100644 index 0000000..fc12513 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c @@ -0,0 +1,266 @@ +/* + * TP-LINK Archer C5/C7/TL-WDR4900 v2 board support + * + * Copyright (c) 2013 Gabor Juhos + * Copyright (c) 2014 æ–½åº·æˆ + * Copyright (c) 2014 Imre Kaloz + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define ARCHER_C7_GPIO_LED_WLAN2G 12 +#define ARCHER_C7_GPIO_LED_SYSTEM 14 +#define ARCHER_C7_GPIO_LED_QSS 15 +#define ARCHER_C7_GPIO_LED_WLAN5G 17 +#define ARCHER_C7_GPIO_LED_USB1 18 +#define ARCHER_C7_GPIO_LED_USB2 19 + +#define ARCHER_C7_GPIO_BTN_RFKILL 13 +#define ARCHER_C7_GPIO_BTN_RESET 16 + +#define ARCHER_C7_GPIO_USB1_POWER 22 +#define ARCHER_C7_GPIO_USB2_POWER 21 + +#define ARCHER_C7_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL) + +#define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000 +#define ARCHER_C7_PCIE_CALDATA_OFFSET 0x5000 + +static const char *archer_c7_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data archer_c7_flash_data = { + .part_probes = archer_c7_part_probes, +}; + +static struct gpio_led archer_c7_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:qss", + .gpio = ARCHER_C7_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:blue:system", + .gpio = ARCHER_C7_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:blue:wlan2g", + .gpio = ARCHER_C7_GPIO_LED_WLAN2G, + .active_low = 1, + }, + { + .name = "tp-link:blue:wlan5g", + .gpio = ARCHER_C7_GPIO_LED_WLAN5G, + .active_low = 1, + }, + { + .name = "tp-link:green:usb1", + .gpio = ARCHER_C7_GPIO_LED_USB1, + .active_low = 1, + }, + { + .name = "tp-link:green:usb2", + .gpio = ARCHER_C7_GPIO_LED_USB2, + .active_low = 1, + }, +}; + +static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, + .gpio = ARCHER_C7_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, + .gpio = ARCHER_C7_GPIO_BTN_RFKILL, + }, +}; + +static const struct ar8327_led_info archer_c7_leds_ar8327[] __initconst = { + AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"), + AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"), + AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"), + AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"), + AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"), +}; + +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ +static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ +static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg archer_c7_ar8327_led_cfg = { + .led_ctrl0 = 0xc737c737, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static struct ar8327_platform_data archer_c7_ar8327_data = { + .pad0_cfg = &archer_c7_ar8327_pad0_cfg, + .pad6_cfg = &archer_c7_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &archer_c7_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(archer_c7_leds_ar8327), + .leds = archer_c7_leds_ar8327, +}; + +static struct mdio_board_info archer_c7_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &archer_c7_ar8327_data, + }, +}; + +static void __init common_setup(bool pcie_slot) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&archer_c7_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio), + archer_c7_leds_gpio); + ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, + ARRAY_SIZE(archer_c7_gpio_keys), + archer_c7_gpio_keys); + + ath79_init_mac(tmpmac, mac, -1); + ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac); + + if (pcie_slot) { + ath79_register_pci(); + } else { + ath79_init_mac(tmpmac, mac, -1); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac); + } + + mdiobus_register_board_info(archer_c7_mdio0_info, + ARRAY_SIZE(archer_c7_mdio0_info)); + ath79_register_mdio(0, 0x0); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x56000000; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + gpio_request_one(ARCHER_C7_GPIO_USB1_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB1 power"); + gpio_request_one(ARCHER_C7_GPIO_USB2_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB2 power"); + ath79_register_usb(); +} + +static void __init archer_c5_setup(void) +{ + common_setup(true); +} + +MIPS_MACHINE(ATH79_MACH_ARCHER_C5, "ARCHER-C5", "TP-LINK Archer C5", + archer_c5_setup); + +static void __init archer_c7_setup(void) +{ + common_setup(true); +} + +MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7", + archer_c7_setup); + +static void __init tl_wdr4900_v2_setup(void) +{ + common_setup(false); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2", + tl_wdr4900_v2_setup) + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c new file mode 100644 index 0000000..281129b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-aw-nr580.c @@ -0,0 +1,107 @@ +/* + * AzureWave AW-NR580 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" +#include "pci.h" + +#define AW_NR580_GPIO_LED_READY_RED 0 +#define AW_NR580_GPIO_LED_WLAN 1 +#define AW_NR580_GPIO_LED_READY_GREEN 2 +#define AW_NR580_GPIO_LED_WPS_GREEN 4 +#define AW_NR580_GPIO_LED_WPS_AMBER 5 + +#define AW_NR580_GPIO_BTN_WPS 3 +#define AW_NR580_GPIO_BTN_RESET 11 + +#define AW_NR580_KEYS_POLL_INTERVAL 20 /* msecs */ +#define AW_NR580_KEYS_DEBOUNCE_INTERVAL (3 * AW_NR580_KEYS_POLL_INTERVAL) + +static struct gpio_led aw_nr580_leds_gpio[] __initdata = { + { + .name = "aw-nr580:red:ready", + .gpio = AW_NR580_GPIO_LED_READY_RED, + .active_low = 0, + }, { + .name = "aw-nr580:green:ready", + .gpio = AW_NR580_GPIO_LED_READY_GREEN, + .active_low = 0, + }, { + .name = "aw-nr580:green:wps", + .gpio = AW_NR580_GPIO_LED_WPS_GREEN, + .active_low = 0, + }, { + .name = "aw-nr580:amber:wps", + .gpio = AW_NR580_GPIO_LED_WPS_AMBER, + .active_low = 0, + }, { + .name = "aw-nr580:green:wlan", + .gpio = AW_NR580_GPIO_LED_WLAN, + .active_low = 0, + } +}; + +static struct gpio_keys_button aw_nr580_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, + .gpio = AW_NR580_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, + .gpio = AW_NR580_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static const char *aw_nr580_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data aw_nr580_flash_data = { + .part_probes = aw_nr580_part_probes, +}; + +static void __init aw_nr580_setup(void) +{ + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + + ath79_register_pci(); + + ath79_register_m25p80(&aw_nr580_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), + aw_nr580_leds_gpio); + + ath79_register_gpio_keys_polled(-1, AW_NR580_KEYS_POLL_INTERVAL, + ARRAY_SIZE(aw_nr580_gpio_keys), + aw_nr580_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", + aw_nr580_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-bhu-bxu2000n2-a.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-bhu-bxu2000n2-a.c new file mode 100644 index 0000000..8d7c611 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-bhu-bxu2000n2-a.c @@ -0,0 +1,120 @@ +/* + * BHU BXU2000n-2 A1 board support + * + * Copyright (C) 2013 Terry Yang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define BHU_BXU2000N2_A1_GPIO_LED_WLAN 13 +#define BHU_BXU2000N2_A1_GPIO_LED_WAN 19 +#define BHU_BXU2000N2_A1_GPIO_LED_LAN 21 +#define BHU_BXU2000N2_A1_GPIO_LED_SYSTEM 14 + +#define BHU_BXU2000N2_A1_GPIO_BTN_RESET 17 + +#define BHU_BXU2000N2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define BHU_BXU2000N2_KEYS_DEBOUNCE_INTERVAL \ + (3 * BHU_BXU2000N2_KEYS_POLL_INTERVAL) + +static const char *bhu_bxu2000n2_part_probes[] = { + "cmdlinepart", + NULL, +}; + +static struct flash_platform_data bhu_bxu2000n2_flash_data = { + .part_probes = bhu_bxu2000n2_part_probes, +}; + +static struct gpio_led bhu_bxu2000n2_a1_leds_gpio[] __initdata = { + { + .name = "bhu:green:status", + .gpio = BHU_BXU2000N2_A1_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "bhu:green:lan", + .gpio = BHU_BXU2000N2_A1_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "bhu:green:wan", + .gpio = BHU_BXU2000N2_A1_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "bhu:green:wlan", + .gpio = BHU_BXU2000N2_A1_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button bhu_bxu2000n2_a1_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = BHU_BXU2000N2_KEYS_DEBOUNCE_INTERVAL, + .gpio = BHU_BXU2000N2_A1_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init bhu_ap123_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&bhu_bxu2000n2_flash_data); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch. Only use PHY3 */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.phy_mask = BIT(3); + ath79_register_eth(1); + + ath79_register_wmac(ee, ee+2); +} + +static void __init bhu_bxu2000n2_a1_setup(void) +{ + bhu_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(bhu_bxu2000n2_a1_leds_gpio), + bhu_bxu2000n2_a1_leds_gpio); + + ath79_register_gpio_keys_polled(1, BHU_BXU2000N2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(bhu_bxu2000n2_a1_gpio_keys), + bhu_bxu2000n2_a1_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_BHU_BXU2000N2_A1, "BXU2000n-2-A1", + "BHU BXU2000n-2 rev. A1", + bhu_bxu2000n2_a1_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-bsb.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-bsb.c new file mode 100644 index 0000000..9f9be02 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-bsb.c @@ -0,0 +1,83 @@ +/* + * Smart Electronics Black Swift board support + * + * Copyright (C) 2014 Dmitriy Zherebkov dzh@black-swift.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define BSB_GPIO_LED_SYS 27 + +#define BSB_GPIO_BTN_RESET 11 + +#define BSB_KEYS_POLL_INTERVAL 20 /* msecs */ +#define BSB_KEYS_DEBOUNCE_INTERVAL (3 * BSB_KEYS_POLL_INTERVAL) + +#define BSB_MAC_OFFSET 0x0000 +#define BSB_CALDATA_OFFSET 0x1000 + +static struct gpio_led bsb_leds_gpio[] __initdata = { + { + .name = "bsb:red:sys", + .gpio = BSB_GPIO_LED_SYS, + .active_low = 1, + } +}; + +static struct gpio_keys_button bsb_gpio_keys[] __initdata = { + { + .desc = "reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = BSB_KEYS_DEBOUNCE_INTERVAL, + .gpio = BSB_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init bsb_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false,false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(bsb_leds_gpio), + bsb_leds_gpio); + ath79_register_gpio_keys_polled(-1, BSB_KEYS_POLL_INTERVAL, + ARRAY_SIZE(bsb_gpio_keys), + bsb_gpio_keys); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + BSB_MAC_OFFSET, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, art + BSB_MAC_OFFSET, 2); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(art + BSB_CALDATA_OFFSET, + art + BSB_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_BSB, "BSB", "Smart Electronics Black Swift board", + bsb_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cap4200ag.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cap4200ag.c new file mode 100644 index 0000000..18944c4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cap4200ag.c @@ -0,0 +1,131 @@ +/* + * Senao CAP4200AG board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define CAP4200AG_GPIO_LED_PWR_GREEN 12 +#define CAP4200AG_GPIO_LED_PWR_AMBER 13 +#define CAP4200AG_GPIO_LED_LAN_GREEN 14 +#define CAP4200AG_GPIO_LED_LAN_AMBER 15 +#define CAP4200AG_GPIO_LED_WLAN_GREEN 18 +#define CAP4200AG_GPIO_LED_WLAN_AMBER 19 + +#define CAP4200AG_GPIO_BTN_RESET 17 + +#define CAP4200AG_KEYS_POLL_INTERVAL 20 /* msecs */ +#define CAP4200AG_KEYS_DEBOUNCE_INTERVAL (3 * CAP4200AG_KEYS_POLL_INTERVAL) + +#define CAP4200AG_MAC_OFFSET 0 +#define CAP4200AG_WMAC_CALDATA_OFFSET 0x1000 +#define CAP4200AG_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led cap4200ag_leds_gpio[] __initdata = { + { + .name = "senao:green:pwr", + .gpio = CAP4200AG_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, + { + .name = "senao:amber:pwr", + .gpio = CAP4200AG_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, + { + .name = "senao:green:lan", + .gpio = CAP4200AG_GPIO_LED_LAN_GREEN, + .active_low = 1, + }, + { + .name = "senao:amber:lan", + .gpio = CAP4200AG_GPIO_LED_LAN_AMBER, + .active_low = 1, + }, + { + .name = "senao:green:wlan", + .gpio = CAP4200AG_GPIO_LED_WLAN_GREEN, + .active_low = 1, + }, + { + .name = "senao:amber:wlan", + .gpio = CAP4200AG_GPIO_LED_WLAN_AMBER, + .active_low = 1, + }, +}; + +static struct gpio_keys_button cap4200ag_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = CAP4200AG_KEYS_DEBOUNCE_INTERVAL, + .gpio = CAP4200AG_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init cap4200ag_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_GREEN, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_AMBER, + AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(cap4200ag_leds_gpio), + cap4200ag_leds_gpio); + ath79_register_gpio_keys_polled(-1, CAP4200AG_KEYS_POLL_INTERVAL, + ARRAY_SIZE(cap4200ag_gpio_keys), + cap4200ag_gpio_keys); + + ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -1); + ath79_wmac_disable_2ghz(); + ath79_register_wmac(art + CAP4200AG_WMAC_CALDATA_OFFSET, mac); + + ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -2); + ap91_pci_init(art + CAP4200AG_PCIE_CALDATA_OFFSET, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + CAP4200AG_MAC_OFFSET, -2); + + /* GMAC0 is connected to an external PHY */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_CAP4200AG, "CAP4200AG", "Senao CAP4200AG", + cap4200ag_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-carambola2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-carambola2.c new file mode 100644 index 0000000..babe101 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-carambola2.c @@ -0,0 +1,105 @@ +/* + * 8devices Carambola2 board support + * + * Copyright (C) 2013 Darius Augulis + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define CARAMBOLA2_GPIO_LED_WLAN 0 +#define CARAMBOLA2_GPIO_LED_ETH0 14 +#define CARAMBOLA2_GPIO_LED_ETH1 13 + +#define CARAMBOLA2_GPIO_BTN_JUMPSTART 11 + +#define CARAMBOLA2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define CARAMBOLA2_KEYS_DEBOUNCE_INTERVAL (3 * CARAMBOLA2_KEYS_POLL_INTERVAL) + +#define CARAMBOLA2_MAC0_OFFSET 0x0000 +#define CARAMBOLA2_MAC1_OFFSET 0x0006 +#define CARAMBOLA2_CALDATA_OFFSET 0x1000 +#define CARAMBOLA2_WMAC_MAC_OFFSET 0x1002 + +static struct gpio_led carambola2_leds_gpio[] __initdata = { + { + .name = "carambola2:green:wlan", + .gpio = CARAMBOLA2_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "carambola2:orange:eth0", + .gpio = CARAMBOLA2_GPIO_LED_ETH0, + .active_low = 0, + }, { + .name = "carambola2:orange:eth1", + .gpio = CARAMBOLA2_GPIO_LED_ETH1, + .active_low = 0, + } +}; + +static struct gpio_keys_button carambola2_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = CARAMBOLA2_KEYS_DEBOUNCE_INTERVAL, + .gpio = CARAMBOLA2_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, +}; + +static void __init carambola2_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_wmac(art + CARAMBOLA2_CALDATA_OFFSET, + art + CARAMBOLA2_WMAC_MAC_OFFSET); + + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + CARAMBOLA2_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + CARAMBOLA2_MAC1_OFFSET, 0); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); +} + +static void __init carambola2_setup(void) +{ + carambola2_common_setup(); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(carambola2_leds_gpio), + carambola2_leds_gpio); + ath79_register_gpio_keys_polled(-1, CARAMBOLA2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(carambola2_gpio_keys), + carambola2_gpio_keys); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_CARAMBOLA2, "CARAMBOLA2", "8devices Carambola2 board", + carambola2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cf-e316n-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cf-e316n-v2.c new file mode 100644 index 0000000..cf3d33a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cf-e316n-v2.c @@ -0,0 +1,132 @@ +/* + * COMFAST CF-E316N v2 + * by Shenzhen Four Seas Global Link Network Technology Co., Ltd + * + * aka CF-E316V2, CF-E316N-V2 and CF-E316Nv2.0 (no FCC ID) + * + * Copyright (C) 2015 Paul Fertser + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "dev-usb.h" +#include "machtypes.h" + +static struct gpio_led cf_e316n_v2_leds_gpio[] __initdata = { + { + .name = "cf-e316n-v2:blue:diag", + .gpio = 0, + .active_low = 0, + }, { + .name = "cf-e316n-v2:red:diag", + .gpio = 2, + .active_low = 0, + }, { + .name = "cf-e316n-v2:green:diag", + .gpio = 3, + .active_low = 0, + }, { + .name = "cf-e316n-v2:blue:wlan", + .gpio = 12, + .active_low = 1, + }, { + .name = "cf-e316n-v2:blue:wan", + .gpio = 17, + .active_low = 1, + }, { + .name = "cf-e316n-v2:blue:lan", + .gpio = 19, + .active_low = 1, + }, +}; + +static struct gpio_keys_button cf_e316n_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = 60, + .gpio = 20, + .active_low = 1, + }, +}; + +/* There's a Pericon Technology PT7A7514 connected to GPIO 16 */ +#define EXT_WATCHDOG_GPIO 16 +static struct timer_list gpio_wdt_timer; + +static void gpio_wdt_toggle(unsigned long period) +{ + static int state; + state = !state; + gpio_set_value(EXT_WATCHDOG_GPIO, state); + mod_timer(&gpio_wdt_timer, jiffies + period); +} + +static void __init cf_e316n_v2_setup(void) +{ + u8 *maclan = (u8 *) KSEG1ADDR(0x1f010000); + u8 *macwlan = (u8 *) KSEG1ADDR(0x1f011002); + u8 *ee = (u8 *) KSEG1ADDR(0x1f011000); + u8 tmpmac[ETH_ALEN]; + + gpio_request(EXT_WATCHDOG_GPIO, "PT7A7514 watchdog"); + gpio_direction_output(EXT_WATCHDOG_GPIO, 0); + setup_timer(&gpio_wdt_timer, gpio_wdt_toggle, msecs_to_jiffies(500)); + gpio_wdt_toggle(msecs_to_jiffies(1)); + + ath79_register_m25p80(NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + ath79_register_mdio(1, 0x0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_init_mac(ath79_eth0_data.mac_addr, maclan, 0); + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_init_mac(ath79_eth1_data.mac_addr, maclan, 2); + ath79_register_eth(1); + + /* Enable 2x Skyworks SE2576L WLAN power amplifiers */ + gpio_request(13, "RF Amp 1"); + gpio_direction_output(13, 1); + gpio_request(14, "RF Amp 2"); + gpio_direction_output(14, 1); + ath79_init_mac(tmpmac, macwlan, 0); + ath79_register_wmac(ee, tmpmac); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e316n_v2_leds_gpio), + cf_e316n_v2_leds_gpio); + + ath79_register_gpio_keys_polled(1, 20, + ARRAY_SIZE(cf_e316n_v2_gpio_keys), + cf_e316n_v2_gpio_keys); + + /* J1 is a High-Speed USB port, pin 1 is Vcc */ + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_CF_E316N_V2, "CF-E316N-V2", "COMFAST CF-E316N v2", + cf_e316n_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c new file mode 100644 index 0000000..8bf5c0f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-cpe510.c @@ -0,0 +1,107 @@ +/* + * TP-LINK CPE210/220/510/520 board support + * + * Copyright (C) 2014 Matthias Schiffer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + + +#define CPE510_GPIO_LED_LAN0 11 +#define CPE510_GPIO_LED_LAN1 12 +#define CPE510_GPIO_LED_L1 13 +#define CPE510_GPIO_LED_L2 14 +#define CPE510_GPIO_LED_L3 15 +#define CPE510_GPIO_LED_L4 16 + +#define CPE510_GPIO_BTN_RESET 4 + +#define CPE510_KEYS_POLL_INTERVAL 20 /* msecs */ +#define CPE510_KEYS_DEBOUNCE_INTERVAL (3 * CPE510_KEYS_POLL_INTERVAL) + + +static struct gpio_led cpe510_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan0", + .gpio = CPE510_GPIO_LED_LAN0, + .active_low = 1, + }, { + .name = "tp-link:green:lan1", + .gpio = CPE510_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:link1", + .gpio = CPE510_GPIO_LED_L1, + .active_low = 1, + }, { + .name = "tp-link:green:link2", + .gpio = CPE510_GPIO_LED_L2, + .active_low = 1, + }, { + .name = "tp-link:green:link3", + .gpio = CPE510_GPIO_LED_L3, + .active_low = 1, + }, { + .name = "tp-link:green:link4", + .gpio = CPE510_GPIO_LED_L4, + .active_low = 1, + }, +}; + +static struct gpio_keys_button cpe510_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = CPE510_KEYS_DEBOUNCE_INTERVAL, + .gpio = CPE510_GPIO_BTN_RESET, + .active_low = 1, + } +}; + + +static void __init cpe510_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f830008); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(cpe510_leds_gpio), + cpe510_leds_gpio); + + ath79_register_gpio_keys_polled(1, CPE510_KEYS_POLL_INTERVAL, + ARRAY_SIZE(cpe510_gpio_keys), + cpe510_gpio_keys); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_CPE510, "CPE510", "TP-LINK CPE210/220/510/520", + cpe510_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dgl-5500-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dgl-5500-a1.c new file mode 100644 index 0000000..91b554e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dgl-5500-a1.c @@ -0,0 +1,150 @@ +/* + * D-Link DGL-5500 board support + * + * Copyright (C) 2014 Gabor Juhos + * Copyright (C) 2014 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DGL_5500_A1_GPIO_LED_POWER_ORANGE 14 +#define DGL_5500_A1_GPIO_LED_POWER_GREEN 19 +#define DGL_5500_A1_GPIO_LED_PLANET_GREEN 22 +#define DGL_5500_A1_GPIO_LED_PLANET_ORANGE 23 + +#define DGL_5500_A1_GPIO_BTN_WPS 16 +#define DGL_5500_A1_GPIO_BTN_RESET 17 + +#define DGL_5500_A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL \ + (3 * DGL_5500_A1_KEYS_POLL_INTERVAL) + +#define DGL_5500_A1_WMAC_CALDATA_OFFSET 0x1000 + +#define DGL_5500_A1_LAN_MAC_OFFSET 0x04 +#define DGL_5500_A1_WAN_MAC_OFFSET 0x16 + +static struct gpio_led dgl_5500_a1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DGL_5500_A1_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, + { + .name = "d-link:orange:power", + .gpio = DGL_5500_A1_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, + { + .name = "d-link:green:planet", + .gpio = DGL_5500_A1_GPIO_LED_PLANET_GREEN, + .active_low = 1, + }, + { + .name = "d-link:orange:planet", + .gpio = DGL_5500_A1_GPIO_LED_PLANET_ORANGE, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dgl_5500_a1_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DGL_5500_A1_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DGL_5500_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DGL_5500_A1_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg dgl_5500_a1_ar8327_pad0_cfg = { + /* Use the SGMII interface for the GMAC0 of the AR8327 switch */ + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +static struct ar8327_platform_data dgl_5500_a1_ar8327_data = { + .pad0_cfg = &dgl_5500_a1_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info dgl_5500_a1_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dgl_5500_a1_ar8327_data, + }, +}; + +static void __init dgl_5500_a1_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 lan_mac[ETH_ALEN]; + + ath79_parse_ascii_mac(mac + DGL_5500_A1_LAN_MAC_OFFSET, lan_mac); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dgl_5500_a1_leds_gpio), + dgl_5500_a1_leds_gpio); + ath79_register_gpio_keys_polled(-1, DGL_5500_A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dgl_5500_a1_gpio_keys), + dgl_5500_a1_gpio_keys); + + ath79_register_wmac(art + DGL_5500_A1_WMAC_CALDATA_OFFSET, lan_mac); + + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(dgl_5500_a1_mdio0_info, + ARRAY_SIZE(dgl_5500_a1_mdio0_info)); + + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + + /* GMAC1 is connected to an AR8327N switch via the SMGII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.phy_mask = BIT(0); + ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_register_eth(1); + + ath79_register_usb(); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_DGL_5500_A1, "DGL-5500-A1", "D-Link DGL-5500 rev. A1", + dgl_5500_a1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c new file mode 100644 index 0000000..ae47764 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dhp-1565-a1.c @@ -0,0 +1,170 @@ +/* + * D-Link DHP-1565 rev. A1 board support + * + * Copyright (C) 2014 Jacek Kikiewicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DHP1565A1_GPIO_LED_BLUE_USB 11 +#define DHP1565A1_GPIO_LED_AMBER_POWER 14 +#define DHP1565A1_GPIO_LED_BLUE_POWER 22 +#define DHP1565A1_GPIO_LED_BLUE_WPS 15 +#define DHP1565A1_GPIO_LED_AMBER_PLANET 19 +#define DHP1565A1_GPIO_LED_BLUE_PLANET 18 +#define DHP1565A1_GPIO_LED_WLAN_2G 13 + +#define DHP1565A1_GPIO_WAN_LED_ENABLE 20 + +#define DHP1565A1_GPIO_BTN_RESET 17 +#define DHP1565A1_GPIO_BTN_WPS 16 + +#define DHP1565A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DHP1565A1_KEYS_DEBOUNCE_INTERVAL (3 * DHP1565A1_KEYS_POLL_INTERVAL) + +#define DHP1565A1_MAC0_OFFSET 0xFFA0 +#define DHP1565A1_MAC1_OFFSET 0xFFB4 +#define DHP1565A1_WMAC0_OFFSET 0x5 +#define DHP1565A1_WMAC_CALDATA_OFFSET 0x1000 +#define DHP1565A1_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dhp1565a1_leds_gpio[] __initdata = { + { + .name = "d-link:amber:power", + .gpio = DHP1565A1_GPIO_LED_AMBER_POWER, + .active_low = 1, + }, + { + .name = "d-link:green:power", + .gpio = DHP1565A1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, + { + .name = "d-link:amber:planet", + .gpio = DHP1565A1_GPIO_LED_AMBER_PLANET, + .active_low = 1, + }, + { + .name = "d-link:green:planet", + .gpio = DHP1565A1_GPIO_LED_BLUE_PLANET, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dhp1565a1_gpio_keys[] __initdata = { + { + .desc = "Soft reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DHP1565A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DHP1565A1_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DHP1565A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DHP1565A1_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg dhp1565a1_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data dhp1565a1_ar8327_data = { + .pad0_cfg = &dhp1565a1_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info dhp1565a1_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dhp1565a1_ar8327_data, + }, +}; + +static void __init dhp1565a1_generic_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 mac0[ETH_ALEN], mac1[ETH_ALEN]; + u8 wmac0[ETH_ALEN]; + + ath79_parse_ascii_mac(mac + DHP1565A1_MAC0_OFFSET, mac0); + ath79_parse_ascii_mac(mac + DHP1565A1_MAC1_OFFSET, mac1); + + ath79_register_m25p80(NULL); + + ath79_register_gpio_keys_polled(-1, DHP1565A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dhp1565a1_gpio_keys), + dhp1565a1_gpio_keys); + + ath79_init_mac(wmac0, mac0, 0); + ath79_register_wmac(art + DHP1565A1_WMAC_CALDATA_OFFSET, wmac0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(dhp1565a1_mdio0_info, + ARRAY_SIZE(dhp1565a1_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 1); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_register_usb(); +} + +static void __init dhp1565a1_setup(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(dhp1565a1_leds_gpio), + dhp1565a1_leds_gpio); + + dhp1565a1_generic_setup(); +} + +MIPS_MACHINE(ATH79_MACH_DHP_1565_A1, "DHP-1565-A1", + "D-Link DHP-1565 rev. A1", + dhp1565a1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-505-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-505-a1.c new file mode 100644 index 0000000..1367b64 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-505-a1.c @@ -0,0 +1,116 @@ +/* + * DLink DIR-505 A1 board support + * + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define DIR_505A1_GPIO_BTN_WPS 11 /* verify */ +#define DIR_505A1_GPIO_BTN_RESET 12 /* verify */ + +#define DIR_505A1_GPIO_LED_RED 26 /* unused, fyi */ +#define DIR_505A1_GPIO_LED_GREEN 27 + +#define DIR_505A1_GPIO_WAN_LED_ENABLE 1 + +#define DIR_505A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_505A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_505A1_KEYS_POLL_INTERVAL) + +#define DIR_505A1_ART_ADDRESS 0x1f010000 +#define DIR_505A1_CALDATA_OFFSET 0x1000 + +#define DIR_505A1_MAC_PART_ADDRESS 0x1f020000 +#define DIR_505A1_LAN_MAC_OFFSET 0x04 +#define DIR_505A1_WAN_MAC_OFFSET 0x16 + +static struct gpio_led dir_505_a1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DIR_505A1_GPIO_LED_GREEN, + .active_low = 1, + }, { + .name = "d-link:red:status", + .gpio = DIR_505A1_GPIO_LED_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dir_505_a1_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_505A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_505A1_GPIO_BTN_RESET, + .active_low = 0, + }, { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_505A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_505A1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init dir_505_a1_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(DIR_505A1_ART_ADDRESS); + u8 *mac = (u8 *) KSEG1ADDR(DIR_505A1_MAC_PART_ADDRESS); + u8 lan_mac[ETH_ALEN]; + u8 wan_mac[ETH_ALEN]; + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + gpio_request_one(DIR_505A1_GPIO_WAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW, "WAN LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_505_a1_leds_gpio), + dir_505_a1_leds_gpio); + + ath79_register_gpio_keys_polled(1, DIR_505A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_505_a1_gpio_keys), + dir_505_a1_gpio_keys); + + ath79_register_m25p80(NULL); + + ath79_register_usb(); + + ath79_parse_ascii_mac(mac + DIR_505A1_LAN_MAC_OFFSET, lan_mac); + ath79_parse_ascii_mac(mac + DIR_505A1_WAN_MAC_OFFSET, wan_mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(art + DIR_505A1_CALDATA_OFFSET, lan_mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_505_A1, "DIR-505-A1", + "D-Link DIR-505 rev. A1", dir_505_a1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c new file mode 100644 index 0000000..321fdce --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-600-a1.c @@ -0,0 +1,159 @@ +/* + * D-Link DIR-600 rev. A1 board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * Copyright (C) 2012 Vadim Girlin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "nvram.h" + +#define DIR_600_A1_GPIO_LED_WPS 0 +#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 +#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 +#define DIR_600_A1_GPIO_LED_LAN1 13 +#define DIR_600_A1_GPIO_LED_LAN2 14 +#define DIR_600_A1_GPIO_LED_LAN3 15 +#define DIR_600_A1_GPIO_LED_LAN4 16 +#define DIR_600_A1_GPIO_LED_WAN_AMBER 7 +#define DIR_600_A1_GPIO_LED_WAN_GREEN 17 + +#define DIR_600_A1_GPIO_BTN_RESET 8 +#define DIR_600_A1_GPIO_BTN_WPS 12 + +#define DIR_600_A1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL) + +#define DIR_600_A1_NVRAM_ADDR 0x1f030000 +#define DIR_600_A1_NVRAM_SIZE 0x10000 + +static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, + }, { + .name = "d-link:amber:power", + .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, + }, { + .name = "d-link:amber:wan", + .gpio = DIR_600_A1_GPIO_LED_WAN_AMBER, + }, { + .name = "d-link:green:wan", + .gpio = DIR_600_A1_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:green:lan1", + .gpio = DIR_600_A1_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "d-link:green:lan2", + .gpio = DIR_600_A1_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "d-link:green:lan3", + .gpio = DIR_600_A1_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "d-link:green:lan4", + .gpio = DIR_600_A1_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_600_A1_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_600_A1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_600_A1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init dir_600_a1_setup(void) +{ + const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac_buff[6]; + u8 *mac = NULL; + + if (ath79_nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, + "lan_mac=", mac_buff) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1); + mac = mac_buff; + } + + ath79_register_m25p80(NULL); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), + dir_600_a1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_600_a1_gpio_keys), + dir_600_a1_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", + dir_600_a1_setup); + +static void __init dir_615_e1_setup(void) +{ + dir_600_a1_setup(); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_E1, "DIR-615-E1", "D-Link DIR-615 rev. E1", + dir_615_e1_setup); + +static void __init dir_615_e4_setup(void) +{ + dir_600_a1_setup(); + ap9x_pci_setup_wmac_led_pin(0, 1); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_E4, "DIR-615-E4", "D-Link DIR-615 rev. E4", + dir_615_e4_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c new file mode 100644 index 0000000..e55a43f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-c1.c @@ -0,0 +1,135 @@ +/* + * D-Link DIR-615 rev C1 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ +#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ +#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ +#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ +#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ +#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ +#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ + +/* buttons may need refinement */ + +#define DIR_615C1_GPIO_BTN_WPS 12 +#define DIR_615C1_GPIO_BTN_RESET 21 + +#define DIR_615C1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_615C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615C1_KEYS_POLL_INTERVAL) + +#define DIR_615C1_CONFIG_ADDR 0x1f020000 +#define DIR_615C1_CONFIG_SIZE 0x10000 + +#define DIR_615C1_WLAN_MAC_ADDR 0x1f3fffb4 + +static struct gpio_led dir_615c1_leds_gpio[] __initdata = { + { + .name = "d-link:orange:status", + .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, { + .name = "d-link:green:wan", + .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, + .active_low = 1, + }, { + .name = "d-link:green:wancpu", + .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, + .active_low = 1, + }, { + .name = "d-link:green:wlan", + .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, + .active_low = 1, + }, { + .name = "d-link:green:status", + .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, + .active_low = 1, + }, { + .name = "d-link:orange:wan", + .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, + .active_low = 1, + } + +}; + +static struct gpio_keys_button dir_615c1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615C1_GPIO_BTN_RESET, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615C1_GPIO_BTN_WPS, + } +}; + +#define DIR_615C1_LAN_PHYMASK BIT(0) +#define DIR_615C1_WAN_PHYMASK BIT(4) +#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ + DIR_615C1_WAN_PHYMASK)) + +static void __init dir_615c1_setup(void) +{ + const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[ETH_ALEN], wlan_mac[ETH_ALEN]; + + if (ath79_nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, + "lan_mac=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + } + + ath79_parse_ascii_mac((char *) KSEG1ADDR(DIR_615C1_WLAN_MAC_ADDR), wlan_mac); + + ath79_register_mdio(0, DIR_615C1_MDIO_MASK); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), + dir_615c1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR_615C1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_615c1_gpio_keys), + dir_615c1_gpio_keys); + + ath79_register_wmac(eeprom, wlan_mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", + dir_615c1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-i1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-i1.c new file mode 100644 index 0000000..64fe438 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-615-i1.c @@ -0,0 +1,133 @@ +/* + * D-Link DIR-615 rev. I1 board support + * Copyright (C) 2013-2015 Jaehoon You + * + * based on the DIR-600 rev. A1 board support code + * Copyright (C) 2010-2012 Gabor Juhos + * Copyright (C) 2012 Vadim Girlin + * + * based on the TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 board support code + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DIR_615_I1_GPIO_LED_WPS 15 +#define DIR_615_I1_GPIO_LED_POWER_AMBER 14 +#define DIR_615_I1_GPIO_LED_POWER_GREEN 4 +#define DIR_615_I1_GPIO_LED_WAN_AMBER 22 +#define DIR_615_I1_GPIO_LED_WAN_GREEN 12 +#define DIR_615_I1_GPIO_LED_WLAN_GREEN 13 + +#define DIR_615_I1_GPIO_BTN_WPS 16 +#define DIR_615_I1_GPIO_BTN_RESET 17 + +#define DIR_615_I1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR_615_I1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615_I1_KEYS_POLL_INTERVAL) + +#define DIR_615_I1_LAN_PHYMASK BIT(0) +#define DIR_615_I1_WAN_PHYMASK BIT(4) +#define DIR_615_I1_WLAN_MAC_ADDR 0x1fffffb4 + +static struct gpio_led dir_615_i1_leds_gpio[] __initdata = { + { + .name = "d-link:green:power", + .gpio = DIR_615_I1_GPIO_LED_POWER_GREEN, + }, { + .name = "d-link:amber:power", + .gpio = DIR_615_I1_GPIO_LED_POWER_AMBER, + }, { + .name = "d-link:amber:wan", + .gpio = DIR_615_I1_GPIO_LED_WAN_AMBER, + }, { + .name = "d-link:green:wan", + .gpio = DIR_615_I1_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:green:wlan", + .gpio = DIR_615_I1_GPIO_LED_WLAN_GREEN, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR_615_I1_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir_615_i1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR_615_I1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615_I1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR_615_I1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR_615_I1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init dir_615_i1_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[ETH_ALEN]; + + ath79_register_mdio(0, 0x0); + ath79_register_mdio(1, ~(DIR_615_I1_WAN_PHYMASK)); + + ath79_parse_ascii_mac((char *) KSEG1ADDR(DIR_615_I1_WLAN_MAC_ADDR), mac); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = DIR_615_I1_WAN_PHYMASK; + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_mask = DIR_615_I1_LAN_PHYMASK; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615_i1_leds_gpio), + dir_615_i1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR_615_I1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir_615_i1_gpio_keys), + dir_615_i1_gpio_keys); + + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_DIR_615_I1, "DIR-615-I1", "D-Link DIR-615 rev. I1", + dir_615_i1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c new file mode 100644 index 0000000..9b82990 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-b1.c @@ -0,0 +1,191 @@ +/* + * D-Link DIR-825 rev. B1 board support + * + * Copyright (C) 2009-2011 Lukas Kuna, Evkanet, s.r.o. + * + * based on mach-wndr3700.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define DIR825B1_GPIO_LED_BLUE_USB 0 +#define DIR825B1_GPIO_LED_ORANGE_POWER 1 +#define DIR825B1_GPIO_LED_BLUE_POWER 2 +#define DIR825B1_GPIO_LED_BLUE_WPS 4 +#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 +#define DIR825B1_GPIO_LED_BLUE_PLANET 11 + +#define DIR825B1_GPIO_BTN_RESET 3 +#define DIR825B1_GPIO_BTN_WPS 8 + +#define DIR825B1_GPIO_RTL8366_SDA 5 +#define DIR825B1_GPIO_RTL8366_SCK 7 + +#define DIR825B1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR825B1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825B1_KEYS_POLL_INTERVAL) + +#define DIR825B1_CAL0_OFFSET 0x1000 +#define DIR825B1_CAL1_OFFSET 0x5000 +#define DIR825B1_MAC0_OFFSET 0xffa0 +#define DIR825B1_MAC1_OFFSET 0xffb4 + +#define DIR825B1_CAL_LOCATION_0 0x1f660000 +#define DIR825B1_CAL_LOCATION_1 0x1f7f0000 + +static struct gpio_led dir825b1_leds_gpio[] __initdata = { + { + .name = "d-link:blue:usb", + .gpio = DIR825B1_GPIO_LED_BLUE_USB, + .active_low = 1, + }, { + .name = "d-link:orange:power", + .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, + .active_low = 1, + }, { + .name = "d-link:blue:power", + .gpio = DIR825B1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, { + .name = "d-link:blue:wps", + .gpio = DIR825B1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, { + .name = "d-link:orange:planet", + .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, + .active_low = 1, + }, { + .name = "d-link:blue:planet", + .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, + .active_low = 1, + } +}; + +static struct gpio_keys_button dir825b1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825B1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825B1_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = { + { .reg = 0x06, .val = 0x0108 }, +}; + +static struct rtl8366_platform_data dir825b1_rtl8366s_data = { + .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, + .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, + .num_initvals = ARRAY_SIZE(dir825b1_rtl8366s_initvals), + .initvals = dir825b1_rtl8366s_initvals, +}; + +static struct platform_device dir825b1_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &dir825b1_rtl8366s_data, + } +}; + +static bool __init dir825b1_is_caldata_valid(u8 *p) +{ + u16 *magic0, *magic1; + + magic0 = (u16 *)(p + DIR825B1_CAL0_OFFSET); + magic1 = (u16 *)(p + DIR825B1_CAL1_OFFSET); + + return (*magic0 == 0xa55a && *magic1 == 0xa55a); +} + +static void __init dir825b1_wlan_init(void) +{ + u8 *caldata; + u8 mac0[ETH_ALEN], mac1[ETH_ALEN]; + u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN]; + + caldata = (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0); + if (!dir825b1_is_caldata_valid(caldata)) { + caldata = (u8 *)KSEG1ADDR(DIR825B1_CAL_LOCATION_1); + if (!dir825b1_is_caldata_valid(caldata)) { + pr_err("no calibration data found\n"); + return; + } + } + + ath79_parse_ascii_mac(caldata + DIR825B1_MAC0_OFFSET, mac0); + ath79_parse_ascii_mac(caldata + DIR825B1_MAC1_OFFSET, mac1); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 0); + ath79_init_mac(wmac0, mac0, 0); + ath79_init_mac(wmac1, mac1, 1); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap94_pci_init(caldata + DIR825B1_CAL0_OFFSET, wmac0, + caldata + DIR825B1_CAL1_OFFSET, wmac1); +} + +static void __init dir825b1_setup(void) +{ + dir825b1_wlan_init(); + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x11110000; + + ath79_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + ath79_eth1_pll_data.pll_1000 = 0x11110000; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), + dir825b1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir825b1_gpio_keys), + dir825b1_gpio_keys); + + ath79_register_usb(); + + platform_device_register(&dir825b1_rtl8366s_device); +} + +MIPS_MACHINE(ATH79_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", + dir825b1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c new file mode 100644 index 0000000..9c4c1a8 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dir-825-c1.c @@ -0,0 +1,241 @@ +/* + * D-Link DIR-825 rev. C1 board support + * + * Copyright (C) 2013 Alexander Stadler + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DIR825C1_GPIO_LED_BLUE_USB 11 +#define DIR825C1_GPIO_LED_AMBER_POWER 14 +#define DIR825C1_GPIO_LED_BLUE_POWER 22 +#define DIR825C1_GPIO_LED_BLUE_WPS 15 +#define DIR825C1_GPIO_LED_AMBER_PLANET 19 +#define DIR825C1_GPIO_LED_BLUE_PLANET 18 +#define DIR825C1_GPIO_LED_WLAN_2G 13 + +#define DIR825C1_GPIO_WAN_LED_ENABLE 20 + +#define DIR825C1_GPIO_BTN_RESET 17 +#define DIR825C1_GPIO_BTN_WPS 16 + +#define DIR825C1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DIR825C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825C1_KEYS_POLL_INTERVAL) + +#define DIR825C1_MAC0_OFFSET 0x4 +#define DIR825C1_MAC1_OFFSET 0x18 +#define DIR825C1_WMAC_CALDATA_OFFSET 0x1000 +#define DIR825C1_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dir825c1_leds_gpio[] __initdata = { + { + .name = "d-link:blue:usb", + .gpio = DIR825C1_GPIO_LED_BLUE_USB, + .active_low = 1, + }, + { + .name = "d-link:amber:power", + .gpio = DIR825C1_GPIO_LED_AMBER_POWER, + .active_low = 1, + }, + { + .name = "d-link:blue:power", + .gpio = DIR825C1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, + { + .name = "d-link:blue:wps", + .gpio = DIR825C1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, + { + .name = "d-link:amber:planet", + .gpio = DIR825C1_GPIO_LED_AMBER_PLANET, + .active_low = 1, + }, + { + .name = "d-link:blue:wlan2g", + .gpio = DIR825C1_GPIO_LED_WLAN_2G, + .active_low = 1, + }, +}; + +static struct gpio_led dir835a1_leds_gpio[] __initdata = { + { + .name = "d-link:amber:power", + .gpio = DIR825C1_GPIO_LED_AMBER_POWER, + .active_low = 1, + }, + { + .name = "d-link:green:power", + .gpio = DIR825C1_GPIO_LED_BLUE_POWER, + .active_low = 1, + }, + { + .name = "d-link:blue:wps", + .gpio = DIR825C1_GPIO_LED_BLUE_WPS, + .active_low = 1, + }, + { + .name = "d-link:amber:planet", + .gpio = DIR825C1_GPIO_LED_AMBER_PLANET, + .active_low = 1, + }, + { + .name = "d-link:green:planet", + .gpio = DIR825C1_GPIO_LED_BLUE_PLANET, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dir825c1_gpio_keys[] __initdata = { + { + .desc = "Soft reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825C1_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DIR825C1_KEYS_DEBOUNCE_INTERVAL, + .gpio = DIR825C1_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg dir825c1_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg dir825c1_ar8327_led_cfg = { + .led_ctrl0 = 0x00000000, + .led_ctrl1 = 0xc737c737, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x00c30c00, + .open_drain = true, +}; + +static struct ar8327_platform_data dir825c1_ar8327_data = { + .pad0_cfg = &dir825c1_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &dir825c1_ar8327_led_cfg, +}; + +static struct mdio_board_info dir825c1_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dir825c1_ar8327_data, + }, +}; + +static void __init dir825c1_generic_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 mac0[ETH_ALEN], mac1[ETH_ALEN]; + u8 wmac0[ETH_ALEN], wmac1[ETH_ALEN]; + + ath79_parse_ascii_mac(mac + DIR825C1_MAC0_OFFSET, mac0); + ath79_parse_ascii_mac(mac + DIR825C1_MAC1_OFFSET, mac1); + + ath79_register_m25p80(NULL); + + ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dir825c1_gpio_keys), + dir825c1_gpio_keys); + + ath79_init_mac(wmac0, mac0, 0); + ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, wmac0); + + ath79_init_mac(wmac1, mac1, 1); + ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, wmac1); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(dir825c1_mdio0_info, + ARRAY_SIZE(dir825c1_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_register_usb(); +} + +static void __init dir825c1_setup(void) +{ + ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, + AR934X_GPIO_OUT_GPIO); + + gpio_request_one(DIR825C1_GPIO_WAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW, "WAN LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio), + dir825c1_leds_gpio); + + ap9x_pci_setup_wmac_led_pin(0, 0); + + dir825c1_generic_setup(); +} + +static void __init dir835a1_setup(void) +{ + dir825c1_ar8327_data.led_cfg = NULL; + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dir835a1_leds_gpio), + dir835a1_leds_gpio); + + dir825c1_generic_setup(); +} + +MIPS_MACHINE(ATH79_MACH_DIR_825_C1, "DIR-825-C1", + "D-Link DIR-825 rev. C1", + dir825c1_setup); + +MIPS_MACHINE(ATH79_MACH_DIR_835_A1, "DIR-835-A1", + "D-Link DIR-835 rev. A1", + dir835a1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-1200-ac.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-1200-ac.c new file mode 100644 index 0000000..03b9f19 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-1200-ac.c @@ -0,0 +1,189 @@ +/* + * devolo dLAN pro 500 Wireless+ support + * + * Copyright (c) 2013-2015 devolo AG + * Copyright (c) 2011-2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DLAN_PRO_1200_AC_GPIO_DLAN_POWER_ENABLE 13 +#define DLAN_PRO_1200_AC_GPIO_WLAN_POWER_ENABLE 21 +#define DLAN_PRO_1200_AC_GPIO_LED_WLAN 12 +#define DLAN_PRO_1200_AC_GPIO_LED_DLAN 14 +#define DLAN_PRO_1200_AC_GPIO_LED_DLAN_ERR 15 + +#define DLAN_PRO_1200_AC_GPIO_BTN_WLAN 20 +#define DLAN_PRO_1200_AC_GPIO_BTN_DLAN 22 +#define DLAN_PRO_1200_AC_GPIO_BTN_RESET 4 +#define DLAN_PRO_1200_AC_GPIO_DLAN_IND 17 +#define DLAN_PRO_1200_AC_GPIO_DLAN_ERR_IND 16 + +#define DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL (3 * DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL) + +#define DLAN_PRO_1200_AC_ART_ADDRESS 0x1fff0000 +#define DLAN_PRO_1200_AC_CALDATA_OFFSET 0x1000 +#define DLAN_PRO_1200_AC_WIFIMAC_OFFSET 0x1002 +#define DLAN_PRO_1200_AC_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dlan_pro_1200_ac_leds_gpio[] __initdata = { + { + .name = "devolo:status:wlan", + .gpio = DLAN_PRO_1200_AC_GPIO_LED_WLAN, + .active_low = 1, + }, + { + .name = "devolo:status:dlan", + .gpio = DLAN_PRO_1200_AC_GPIO_LED_DLAN, + .active_low = 1, + }, + { + .name = "devolo:error:dlan", + .gpio = DLAN_PRO_1200_AC_GPIO_LED_DLAN_ERR, + .active_low = 0, + } +}; + +static struct gpio_keys_button dlan_pro_1200_ac_gpio_keys[] __initdata = { + { + .desc = "dLAN button", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_DLAN, + .active_low = 1, + }, + { + .desc = "WLAN button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_WLAN, + .active_low = 0, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DLAN_PRO_1200_AC_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_1200_AC_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg dlan_pro_1200_ac_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = false, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_pad_cfg dlan_pro_1200_ac_ar8327_pad5_cfg = { + .mode = 0, + .txclk_delay_en = 0, + .rxclk_delay_en = 0, + .txclk_delay_sel = 0, + .rxclk_delay_sel = 0, +}; + +static struct ar8327_platform_data dlan_pro_1200_ac_ar8327_data = { + .pad0_cfg = &dlan_pro_1200_ac_ar8327_pad0_cfg, + .pad5_cfg = &dlan_pro_1200_ac_ar8327_pad5_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info dlan_pro_1200_ac_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dlan_pro_1200_ac_ar8327_data, + }, +}; + +static void __init dlan_pro_1200_ac_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(DLAN_PRO_1200_AC_ART_ADDRESS); + u8 *cal = art + DLAN_PRO_1200_AC_CALDATA_OFFSET; + u8 *wifi_mac = art + DLAN_PRO_1200_AC_WIFIMAC_OFFSET; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dlan_pro_1200_ac_leds_gpio), + dlan_pro_1200_ac_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DLAN_PRO_1200_AC_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dlan_pro_1200_ac_gpio_keys), + dlan_pro_1200_ac_gpio_keys); + + /* dLAN power must be enabled from user-space as soon as the boot-from-host daemon is running */ + gpio_request_one(DLAN_PRO_1200_AC_GPIO_DLAN_POWER_ENABLE, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, + "dLAN power"); + + /* WLAN power is turned on initially to allow the PCI bus scan to succeed */ + gpio_request_one(DLAN_PRO_1200_AC_GPIO_WLAN_POWER_ENABLE, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "WLAN power"); + + ath79_register_wmac(cal, wifi_mac); + ap91_pci_init(art + DLAN_PRO_1200_AC_PCIE_CALDATA_OFFSET, NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, wifi_mac, 2); + + mdiobus_register_board_info(dlan_pro_1200_ac_mdio0_info, + ARRAY_SIZE(dlan_pro_1200_ac_mdio0_info)); + + /* GMAC0 is connected to an AR8337 */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x02000000; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_DLAN_PRO_1200_AC, "dLAN-pro-1200-ac", "devolo dLAN pro 1200+ WiFi ac", + dlan_pro_1200_ac_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c new file mode 100644 index 0000000..ae6f443 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dlan-pro-500-wp.c @@ -0,0 +1,203 @@ +/* + * devolo dLAN pro 500 Wireless+ support + * + * Copyright (c) 2013-2015 devolo AG + * Copyright (c) 2011-2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DLAN_PRO_500_WP_GPIO_DLAN_POWER_ENABLE 13 +#define DLAN_PRO_500_WP_GPIO_DLAN_LED_ENABLE 17 +#define DLAN_PRO_500_WP_GPIO_LED_WLAN_5G 11 +#define DLAN_PRO_500_WP_GPIO_LED_WLAN_2G 12 +#define DLAN_PRO_500_WP_GPIO_LED_STATUS 16 +#define DLAN_PRO_500_WP_GPIO_LED_ETH 14 + +#define DLAN_PRO_500_WP_GPIO_BTN_WPS 20 +#define DLAN_PRO_500_WP_GPIO_BTN_WLAN 22 +#define DLAN_PRO_500_WP_GPIO_BTN_DLAN 21 +#define DLAN_PRO_500_WP_GPIO_BTN_RESET 4 + +#define DLAN_PRO_500_WP_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL (3 * DLAN_PRO_500_WP_KEYS_POLL_INTERVAL) + +#define DLAN_PRO_500_WP_ART_ADDRESS 0x1fff0000 +#define DLAN_PRO_500_WP_CALDATA_OFFSET 0x1000 +#define DLAN_PRO_500_WP_MAC_ADDRESS_OFFSET 0x1002 +#define DLAN_PRO_500_WP_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led dlan_pro_500_wp_leds_gpio[] __initdata = { + { + .name = "devolo:green:status", + .gpio = DLAN_PRO_500_WP_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "devolo:green:eth", + .gpio = DLAN_PRO_500_WP_GPIO_LED_ETH, + .active_low = 1, + }, + { + .name = "devolo:blue:wlan-5g", + .gpio = DLAN_PRO_500_WP_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "devolo:green:wlan-2g", + .gpio = DLAN_PRO_500_WP_GPIO_LED_WLAN_2G, + .active_low = 1, + } +}; + +static struct gpio_keys_button dlan_pro_500_wp_gpio_keys[] __initdata = { + { + .desc = "dLAN button", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_500_WP_GPIO_BTN_DLAN, + .active_low = 0, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_500_WP_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "WLAN button", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_500_WP_GPIO_BTN_WLAN, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DLAN_PRO_500_WP_KEYS_DEBOUNCE_INTERVAL, + .gpio = DLAN_PRO_500_WP_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg dlan_pro_500_wp_ar8327_pad0_cfg = { + .mode = AR8327_PAD_PHY_RGMII, + .txclk_delay_en = false, + .rxclk_delay_en = false, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL0, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_led_cfg dlan_pro_500_wp_ar8327_led_cfg = { + .led_ctrl0 = 0x00000000, + .led_ctrl1 = 0xc737c737, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x00c30c00, + .open_drain = true, +}; + +static struct ar8327_platform_data dlan_pro_500_wp_ar8327_data = { + .pad0_cfg = &dlan_pro_500_wp_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 0, + .rxpause = 0, + }, + .led_cfg = &dlan_pro_500_wp_ar8327_led_cfg, +}; + +static struct mdio_board_info dlan_pro_500_wp_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &dlan_pro_500_wp_ar8327_data, + }, +}; + +static void __init dlan_pro_500_wp_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(DLAN_PRO_500_WP_ART_ADDRESS); + u8 *cal = art + DLAN_PRO_500_WP_CALDATA_OFFSET; + u8 *wifi_mac = art + DLAN_PRO_500_WP_MAC_ADDRESS_OFFSET; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dlan_pro_500_wp_leds_gpio), + dlan_pro_500_wp_leds_gpio); + + ath79_register_gpio_keys_polled(-1, DLAN_PRO_500_WP_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dlan_pro_500_wp_gpio_keys), + dlan_pro_500_wp_gpio_keys); + + gpio_request_one(DLAN_PRO_500_WP_GPIO_DLAN_POWER_ENABLE, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, + "PLC power"); + gpio_request_one(DLAN_PRO_500_WP_GPIO_DLAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, + "PLC LEDs"); + + ath79_register_wmac(cal, wifi_mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(dlan_pro_500_wp_mdio0_info, + ARRAY_SIZE(dlan_pro_500_wp_mdio0_info)); + + /* GMAC0 is connected to a AR7400 PLC in PHY mode */ + ath79_init_mac(ath79_eth0_data.mac_addr, wifi_mac, 2); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_pll_data.pll_1000 = 0x0e000000; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, wifi_mac, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_DLAN_PRO_500_WP, "dLAN-pro-500-wp", "devolo dLAN pro 500 Wireless+", + dlan_pro_500_wp_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-dragino2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-dragino2.c new file mode 100644 index 0000000..95bd6f4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dragino2.c @@ -0,0 +1,136 @@ +/* + * DRAGINO V2 board support, based on Atheros AP121 board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2012 Elektra Wagenrad + * Copyright (C) 2014 Vittorio Gambaletta + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DRAGINO2_GPIO_LED_WLAN 0 +#define DRAGINO2_GPIO_LED_LAN 13 +#define DRAGINO2_GPIO_LED_WAN 17 + +/* + * The following GPIO is named "SYS" on newer revisions of the the board. + * It was previously used to indicate USB activity, even though it was + * named "Router". + */ + +#define DRAGINO2_GPIO_LED_SYS 28 +#define DRAGINO2_GPIO_BTN_JUMPSTART 11 +#define DRAGINO2_GPIO_BTN_RESET 12 + +#define DRAGINO2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DRAGINO2_KEYS_DEBOUNCE_INTERVAL (3 * DRAGINO2_KEYS_POLL_INTERVAL) + +#define DRAGINO2_MAC0_OFFSET 0x0000 +#define DRAGINO2_MAC1_OFFSET 0x0006 +#define DRAGINO2_CALDATA_OFFSET 0x1000 +#define DRAGINO2_WMAC_MAC_OFFSET 0x1002 + +static struct gpio_led dragino2_leds_gpio[] __initdata = { + { + .name = "dragino2:red:wlan", + .gpio = DRAGINO2_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "dragino2:red:wan", + .gpio = DRAGINO2_GPIO_LED_WAN, + .active_low = 1, + }, + { + .name = "dragino2:red:lan", + .gpio = DRAGINO2_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "dragino2:red:system", + .gpio = DRAGINO2_GPIO_LED_SYS, + .active_low = 0, + }, +}; + +static struct gpio_keys_button dragino2_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DRAGINO2_KEYS_DEBOUNCE_INTERVAL, + .gpio = DRAGINO2_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, + { + .desc = "reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DRAGINO2_KEYS_DEBOUNCE_INTERVAL, + .gpio = DRAGINO2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init dragino2_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_wmac(art + DRAGINO2_CALDATA_OFFSET, + art + DRAGINO2_WMAC_MAC_OFFSET); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + DRAGINO2_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + DRAGINO2_MAC1_OFFSET, 0); + + ath79_register_mdio(0, 0x0); + + /* Enable GPIO13, GPIO14, GPIO15, GPIO16 and GPIO17 */ + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + /* LAN port */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + /* Enable GPIO26 and GPIO27 */ + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, + ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP) | + AR933X_BOOTSTRAP_MDIO_GPIO_EN); +} + +static void __init dragino2_setup(void) +{ + dragino2_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dragino2_leds_gpio), + dragino2_leds_gpio); + ath79_register_gpio_keys_polled(-1, DRAGINO2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dragino2_gpio_keys), + dragino2_gpio_keys); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_DRAGINO2, "DRAGINO2", "Dragino Dragino v2", + dragino2_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-eap300v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap300v2.c new file mode 100644 index 0000000..ba577e2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap300v2.c @@ -0,0 +1,101 @@ +/* + * EnGenius EAP300 v2 board support + * + * Copyright (C) 2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define EAP300V2_GPIO_LED_POWER 0 +#define EAP300V2_GPIO_LED_LAN 16 +#define EAP300V2_GPIO_LED_WLAN 17 + +#define EAP300V2_GPIO_BTN_RESET 1 + +#define EAP300V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EAP300V2_KEYS_DEBOUNCE_INTERVAL (3 * EAP300V2_KEYS_POLL_INTERVAL) + +static struct gpio_led eap300v2_leds_gpio[] __initdata = { + { + .name = "engenius:blue:power", + .gpio = EAP300V2_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "engenius:blue:lan", + .gpio = EAP300V2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "engenius:blue:wlan", + .gpio = EAP300V2_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button eap300v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EAP300V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = EAP300V2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +#define EAP300V2_ART_MAC_OFFSET 2 + +#define EAP300V2_LAN_PHYMASK BIT(0) + +static void __init eap300v2_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff1000); + + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); + + ath79_gpio_output_select(EAP300V2_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(EAP300V2_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(EAP300V2_GPIO_LED_WLAN, AR934X_GPIO_OUT_GPIO); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(eap300v2_leds_gpio), + eap300v2_leds_gpio); + ath79_register_gpio_keys_polled(-1, EAP300V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(eap300v2_gpio_keys), + eap300v2_gpio_keys); + + ath79_register_m25p80(NULL); + ath79_register_wmac(art, NULL); + ath79_register_mdio(1, 0x0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + EAP300V2_ART_MAC_OFFSET, 0); + + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = EAP300V2_LAN_PHYMASK; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = EAP300V2_LAN_PHYMASK; + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_EAP300V2, "EAP300V2", "EnGenius EAP300 v2", + eap300v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c new file mode 100644 index 0000000..787e627 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-eap7660d.c @@ -0,0 +1,181 @@ +/* + * Senao EAP7660D board support + * + * Copyright (C) 2010 Daniel Golle + * Copyright (C) 2008 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" + +#define EAP7660D_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EAP7660D_KEYS_DEBOUNCE_INTERVAL (3 * EAP7660D_KEYS_POLL_INTERVAL) + +#define EAP7660D_GPIO_DS4 7 +#define EAP7660D_GPIO_DS5 2 +#define EAP7660D_GPIO_DS7 0 +#define EAP7660D_GPIO_DS8 4 +#define EAP7660D_GPIO_SW1 3 +#define EAP7660D_GPIO_SW3 8 +#define EAP7660D_PHYMASK BIT(20) +#define EAP7660D_BOARDCONFIG 0x1F7F0000 +#define EAP7660D_GBIC_MAC_OFFSET 0x1000 +#define EAP7660D_WMAC0_MAC_OFFSET 0x1010 +#define EAP7660D_WMAC1_MAC_OFFSET 0x1016 +#define EAP7660D_WMAC0_CALDATA_OFFSET 0x2000 +#define EAP7660D_WMAC1_CALDATA_OFFSET 0x3000 + +#ifdef CONFIG_PCI +static struct ath5k_platform_data eap7660d_wmac0_data; +static struct ath5k_platform_data eap7660d_wmac1_data; +static char eap7660d_wmac0_mac[6]; +static char eap7660d_wmac1_mac[6]; +static u16 eap7660d_wmac0_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; +static u16 eap7660d_wmac1_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; + +static int eap7660d_pci_plat_dev_init(struct pci_dev *dev) +{ + switch (PCI_SLOT(dev->devfn)) { + case 17: + dev->dev.platform_data = &eap7660d_wmac0_data; + break; + + case 18: + dev->dev.platform_data = &eap7660d_wmac1_data; + break; + } + + return 0; +} + +void __init eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ + if (cal_data0 && *cal_data0 == 0xa55a) { + memcpy(eap7660d_wmac0_eeprom, cal_data0, + ATH5K_PLAT_EEP_MAX_WORDS); + eap7660d_wmac0_data.eeprom_data = eap7660d_wmac0_eeprom; + } + + if (cal_data1 && *cal_data1 == 0xa55a) { + memcpy(eap7660d_wmac1_eeprom, cal_data1, + ATH5K_PLAT_EEP_MAX_WORDS); + eap7660d_wmac1_data.eeprom_data = eap7660d_wmac1_eeprom; + } + + if (mac_addr0) { + memcpy(eap7660d_wmac0_mac, mac_addr0, + sizeof(eap7660d_wmac0_mac)); + eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac; + } + + if (mac_addr1) { + memcpy(eap7660d_wmac1_mac, mac_addr1, + sizeof(eap7660d_wmac1_mac)); + eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac; + } + + ath79_pci_set_plat_dev_init(eap7660d_pci_plat_dev_init); + ath79_register_pci(); +} +#else +static inline void eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, + u8 *cal_data1, u8 *mac_addr1) +{ +} +#endif /* CONFIG_PCI */ + +static struct gpio_led eap7660d_leds_gpio[] __initdata = { + { + .name = "eap7660d:green:ds8", + .gpio = EAP7660D_GPIO_DS8, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds5", + .gpio = EAP7660D_GPIO_DS5, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds7", + .gpio = EAP7660D_GPIO_DS7, + .active_low = 0, + }, + { + .name = "eap7660d:green:ds4", + .gpio = EAP7660D_GPIO_DS4, + .active_low = 0, + } +}; + +static struct gpio_keys_button eap7660d_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, + .gpio = EAP7660D_GPIO_SW1, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, + .gpio = EAP7660D_GPIO_SW3, + .active_low = 1, + } +}; + +static const char *eap7660d_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data eap7660d_flash_data = { + .part_probes = eap7660d_part_probes, +}; + +static void __init eap7660d_setup(void) +{ + u8 *boardconfig = (u8 *) KSEG1ADDR(EAP7660D_BOARDCONFIG); + + ath79_register_mdio(0, ~EAP7660D_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, + boardconfig + EAP7660D_GBIC_MAC_OFFSET, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = EAP7660D_PHYMASK; + ath79_register_eth(0); + ath79_register_m25p80(&eap7660d_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(eap7660d_leds_gpio), + eap7660d_leds_gpio); + ath79_register_gpio_keys_polled(-1, EAP7660D_KEYS_POLL_INTERVAL, + ARRAY_SIZE(eap7660d_gpio_keys), + eap7660d_gpio_keys); + eap7660d_pci_init(boardconfig + EAP7660D_WMAC0_CALDATA_OFFSET, + boardconfig + EAP7660D_WMAC0_MAC_OFFSET, + boardconfig + EAP7660D_WMAC1_CALDATA_OFFSET, + boardconfig + EAP7660D_WMAC1_MAC_OFFSET); +}; + +MIPS_MACHINE(ATH79_MACH_EAP7660D, "EAP7660D", "Senao EAP7660D", + eap7660d_setup); + +MIPS_MACHINE(ATH79_MACH_ALL0305, "ALL0305", "Allnet ALL0305", + eap7660d_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-el-m150.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-el-m150.c new file mode 100644 index 0000000..b95d6c2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-el-m150.c @@ -0,0 +1,112 @@ +/* + * Easy-Link EL-M150 board support + * + * Copyright (C) 2012 huangfc + * Copyright (C) 2012 HYS <550663898@qq.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "dev-usb.h" + +#define EL_M150_GPIO_BTN6 6 +#define EL_M150_GPIO_BTN7 7 +#define EL_M150_GPIO_BTN_RESET 11 + +#define EL_M150_GPIO_LED_SYSTEM 27 +#define EL_M150_GPIO_USB_POWER 8 + +#define EL_M150_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EL_M150_KEYS_DEBOUNCE_INTERVAL (3 * EL_M150_KEYS_POLL_INTERVAL) + +static const char *EL_M150_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data EL_M150_flash_data = { + .part_probes = EL_M150_part_probes, +}; + +static struct gpio_led EL_M150_leds_gpio[] __initdata = { + { + .name = "easylink:green:system", + .gpio = EL_M150_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button EL_M150_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL, + .gpio = EL_M150_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "BTN_6", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL, + .gpio = EL_M150_GPIO_BTN6, + .active_low = 1, + }, + { + .desc = "BTN_7", + .type = EV_KEY, + .code = BTN_7, + .debounce_interval = EL_M150_KEYS_DEBOUNCE_INTERVAL, + .gpio = EL_M150_GPIO_BTN7, + .active_low = 1, + }, +}; + +static void __init el_m150_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(EL_M150_leds_gpio), + EL_M150_leds_gpio); + + ath79_register_gpio_keys_polled(-1, EL_M150_KEYS_POLL_INTERVAL, + ARRAY_SIZE(EL_M150_gpio_keys), + EL_M150_gpio_keys); + + gpio_request_one(EL_M150_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_m25p80(&EL_M150_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_EL_M150, "EL-M150", + "EasyLink EL-M150", el_m150_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-el-mini.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-el-mini.c new file mode 100644 index 0000000..9879b18 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-el-mini.c @@ -0,0 +1,86 @@ +/* + * Easy-Link EL-MINI board support + * + * Copyright (C) 2012 huangfc + * Copyright (C) 2011 hys <550663898@qq.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MINI_GPIO_LED_SYSTEM 27 +#define MINI_GPIO_BTN_RESET 11 + +#define MINI_GPIO_USB_POWER 8 + +#define MINI_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MINI_KEYS_DEBOUNCE_INTERVAL (3 * MINI_KEYS_POLL_INTERVAL) + +static const char *mini_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data mini_flash_data = { + .part_probes = mini_part_probes, +}; + +static struct gpio_led mini_leds_gpio[] __initdata = { + { + .name = "easylink:green:system", + .gpio = MINI_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mini_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MINI_KEYS_DEBOUNCE_INTERVAL, + .gpio = MINI_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init el_mini_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&mini_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(mini_leds_gpio), + mini_leds_gpio); + ath79_register_gpio_keys_polled(-1, MINI_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mini_gpio_keys), + mini_gpio_keys); + + gpio_request_one(MINI_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_EL_MINI, "EL-MINI", "EasyLink EL-MINI", + el_mini_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c new file mode 100644 index 0000000..b049f5d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c @@ -0,0 +1,178 @@ +/* + * EnGenius EPG5000 board support + * + * Copyright (c) 2014 Jon Suphammer + * Copyright (c) 2015 Christian Beier + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define EPG5000_GPIO_LED_WLAN_5G 23 +#define EPG5000_GPIO_LED_WLAN_2G 13 +#define EPG5000_GPIO_LED_POWER_AMBER 2 +#define EPG5000_GPIO_LED_WPS_AMBER 22 +#define EPG5000_GPIO_LED_WPS_BLUE 19 + +#define EPG5000_GPIO_BTN_WPS 16 +#define EPG5000_GPIO_BTN_RESET 17 + +#define EPG5000_KEYS_POLL_INTERVAL 20 /* msecs */ +#define EPG5000_KEYS_DEBOUNCE_INTERVAL (3 * EPG5000_KEYS_POLL_INTERVAL) + +#define EPG5000_CALDATA_ADDR 0x1fff0000 +#define EPG5000_WMAC_CALDATA_OFFSET 0x1000 +#define EPG5000_PCIE_CALDATA_OFFSET 0x5000 + +#define EPG5000_NVRAM_ADDR 0x1f030000 +#define EPG5000_NVRAM_SIZE 0x10000 + +static struct gpio_led epg5000_leds_gpio[] __initdata = { + { + .name = "epg5000:amber:power", + .gpio = EPG5000_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, + { + .name = "epg5000:blue:wps", + .gpio = EPG5000_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, + { + .name = "epg5000:amber:wps", + .gpio = EPG5000_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "epg5000:blue:wlan-2g", + .gpio = EPG5000_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "epg5000:blue:wlan-5g", + .gpio = EPG5000_GPIO_LED_WLAN_5G, + .active_low = 1, + } +}; + +static struct gpio_keys_button epg5000_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = EPG5000_KEYS_DEBOUNCE_INTERVAL, + .gpio = EPG5000_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = EPG5000_KEYS_DEBOUNCE_INTERVAL, + .gpio = EPG5000_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg epg5000_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .mac06_exchange_en = true, +}; + +static struct ar8327_platform_data epg5000_ar8327_data = { + .pad0_cfg = &epg5000_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info epg5000_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &epg5000_ar8327_data, + }, +}; + +static int epg5000_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(EPG5000_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, EPG5000_NVRAM_SIZE, + name, mac); + if (err) { + pr_err("no MAC address found for %s\n", name); + return false; + } + + return true; +} + +static void __init epg5000_setup(void) +{ + u8 *caldata = (u8 *) KSEG1ADDR(EPG5000_CALDATA_ADDR); + u8 mac1[ETH_ALEN]; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(epg5000_leds_gpio), + epg5000_leds_gpio); + ath79_register_gpio_keys_polled(-1, EPG5000_KEYS_POLL_INTERVAL, + ARRAY_SIZE(epg5000_gpio_keys), + epg5000_gpio_keys); + + ath79_register_usb(); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(epg5000_mdio0_info, + ARRAY_SIZE(epg5000_mdio0_info)); + + /* GMAC0 is connected to an QCA8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + if (epg5000_get_mac("ethaddr=", mac1)) + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_register_eth(0); + + ath79_register_wmac(caldata + EPG5000_WMAC_CALDATA_OFFSET, mac1); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_EPG5000, "EPG5000", + "EnGenius EPG5000", + epg5000_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c new file mode 100644 index 0000000..d2bc177 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c @@ -0,0 +1,177 @@ +/* + * EnGenius ESR1750 board support + * + * Copyright (c) 2014 Jon Suphammer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define ESR1750_GPIO_LED_WLAN_5G 23 +#define ESR1750_GPIO_LED_WLAN_2G 13 +#define ESR1750_GPIO_LED_POWER_AMBER 2 +#define ESR1750_GPIO_LED_WPS_AMBER 22 +#define ESR1750_GPIO_LED_WPS_BLUE 19 + +#define ESR1750_GPIO_BTN_WPS 16 +#define ESR1750_GPIO_BTN_RESET 17 + +#define ESR1750_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ESR1750_KEYS_DEBOUNCE_INTERVAL (3 * ESR1750_KEYS_POLL_INTERVAL) + +#define ESR1750_CALDATA_ADDR 0x1fff0000 +#define ESR1750_WMAC_CALDATA_OFFSET 0x1000 +#define ESR1750_PCIE_CALDATA_OFFSET 0x5000 + +#define ESR1750_NVRAM_ADDR 0x1f030000 +#define ESR1750_NVRAM_SIZE 0x10000 + +static struct gpio_led esr1750_leds_gpio[] __initdata = { + { + .name = "esr1750:amber:power", + .gpio = ESR1750_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, + { + .name = "esr1750:blue:wps", + .gpio = ESR1750_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, + { + .name = "esr1750:amber:wps", + .gpio = ESR1750_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "esr1750:blue:wlan-2g", + .gpio = ESR1750_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "esr1750:blue:wlan-5g", + .gpio = ESR1750_GPIO_LED_WLAN_5G, + .active_low = 1, + } +}; + +static struct gpio_keys_button esr1750_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ESR1750_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR1750_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ESR1750_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR1750_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg esr1750_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .mac06_exchange_en = true, +}; + +static struct ar8327_platform_data esr1750_ar8327_data = { + .pad0_cfg = &esr1750_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info esr1750_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &esr1750_ar8327_data, + }, +}; + +static int esr1750_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(ESR1750_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, ESR1750_NVRAM_SIZE, + name, mac); + if (err) { + pr_err("no MAC address found for %s\n", name); + return false; + } + + return true; +} + +static void __init esr1750_setup(void) +{ + u8 *caldata = (u8 *) KSEG1ADDR(ESR1750_CALDATA_ADDR); + u8 mac1[ETH_ALEN]; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(esr1750_leds_gpio), + esr1750_leds_gpio); + ath79_register_gpio_keys_polled(-1, ESR1750_KEYS_POLL_INTERVAL, + ARRAY_SIZE(esr1750_gpio_keys), + esr1750_gpio_keys); + + ath79_register_usb(); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(esr1750_mdio0_info, + ARRAY_SIZE(esr1750_mdio0_info)); + + /* GMAC0 is connected to an QCA8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + if (esr1750_get_mac("ethaddr=", mac1)) + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_register_eth(0); + + ath79_register_wmac(caldata + ESR1750_WMAC_CALDATA_OFFSET, mac1); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_ESR1750, "ESR1750", + "EnGenius ESR1750", + esr1750_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c new file mode 100644 index 0000000..aa2e7f7 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c @@ -0,0 +1,200 @@ +/* + * EnGenius ESR900 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "esr900: " fmt + +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define ESR900_GPIO_LED_POWER 2 +#define ESR900_GPIO_LED_WLAN_2G 13 +#define ESR900_GPIO_LED_WPS_BLUE 19 +#define ESR900_GPIO_LED_WPS_AMBER 22 +#define ESR900_GPIO_LED_WLAN_5G 23 + +#define ESR900_GPIO_BTN_WPS 16 +#define ESR900_GPIO_BTN_RESET 17 + +#define ESR900_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ESR900_KEYS_DEBOUNCE_INTERVAL (3 * ESR900_KEYS_POLL_INTERVAL) + +#define ESR900_CALDATA_ADDR 0x1fff0000 +#define ESR900_WMAC_CALDATA_OFFSET 0x1000 +#define ESR900_PCIE_CALDATA_OFFSET 0x5000 + +#define ESR900_CONFIG_ADDR 0x1f030000 +#define ESR900_CONFIG_SIZE 0x10000 + +#define ESR900_LAN_PHYMASK BIT(0) +#define ESR900_WAN_PHYMASK BIT(5) +#define ESR900_MDIO_MASK (~(ESR900_LAN_PHYMASK | ESR900_WAN_PHYMASK)) + +static struct gpio_led esr900_leds_gpio[] __initdata = { + { + .name = "engenius:amber:power", + .gpio = ESR900_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "engenius:blue:wlan-2g", + .gpio = ESR900_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "engenius:blue:wps", + .gpio = ESR900_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, + { + .name = "engenius:amber:wps", + .gpio = ESR900_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "engenius:blue:wlan-5g", + .gpio = ESR900_GPIO_LED_WLAN_5G, + .active_low = 1, + } +}; + +static struct gpio_keys_button esr900_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR900_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL, + .gpio = ESR900_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg esr900_ar8327_pad0_cfg = { + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */ + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_pad_cfg esr900_ar8327_pad6_cfg = { + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */ + .mode = AR8327_PAD_MAC_SGMII, + .rxclk_delay_en = true, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_platform_data esr900_ar8327_data = { + .pad0_cfg = &esr900_ar8327_pad0_cfg, + .pad6_cfg = &esr900_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info esr900_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &esr900_ar8327_data, + }, +}; + +static void __init esr900_setup(void) +{ + const char *config = (char *) KSEG1ADDR(ESR900_CONFIG_ADDR); + u8 *art = (u8 *) KSEG1ADDR(ESR900_CALDATA_ADDR); + u8 lan_mac[ETH_ALEN]; + u8 wlan0_mac[ETH_ALEN]; + u8 wlan1_mac[ETH_ALEN]; + + if (ath79_nvram_parse_mac_addr(config, ESR900_CONFIG_SIZE, + "ethaddr=", lan_mac) == 0) { + ath79_init_local_mac(ath79_eth0_data.mac_addr, lan_mac); + ath79_init_mac(wlan0_mac, lan_mac, 0); + ath79_init_mac(wlan1_mac, lan_mac, 1); + } else { + pr_err("could not find ethaddr in u-boot environment\n"); + } + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(esr900_leds_gpio), + esr900_leds_gpio); + ath79_register_gpio_keys_polled(-1, ESR900_KEYS_POLL_INTERVAL, + ARRAY_SIZE(esr900_gpio_keys), + esr900_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(esr900_mdio0_info, + ARRAY_SIZE(esr900_mdio0_info)); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = ESR900_LAN_PHYMASK; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_eth1_pll_data.pll_1000 = 0x03000101; + ath79_register_eth(1); + + ap91_pci_init(art + ESR900_PCIE_CALDATA_OFFSET, wlan1_mac); +} + +MIPS_MACHINE(ATH79_MACH_ESR900, "ESR900", "EnGenius ESR900", esr900_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c new file mode 100644 index 0000000..e686b5f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ew-dorin.c @@ -0,0 +1,150 @@ +/* + * EW Dorin board support + * (based on Atheros Ref. Design AP121) + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2012-2015 Embedded Wireless GmbH www.80211.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define DORIN_KEYS_POLL_INTERVAL 20 /* msecs */ +#define DORIN_KEYS_DEBOUNCE_INTERVAL (3 * DORIN_KEYS_POLL_INTERVAL) + +#define DORIN_CALDATA_OFFSET 0x1000 +#define DORIN_WMAC_MAC_OFFSET 0x1002 + +#define DORIN_GPIO_LED_21 21 +#define DORIN_GPIO_LED_22 22 +#define DORIN_GPIO_LED_STATUS 23 + +#define DORIN_GPIO_BTN_JUMPSTART 11 +#define DORIN_GPIO_BTN_RESET 6 + +static struct gpio_led dorin_leds_gpio[] __initdata = { + { + .name = "dorin:green:led21", + .gpio = DORIN_GPIO_LED_21, + .active_low = 1, + }, + { + .name = "dorin:green:led22", + .gpio = DORIN_GPIO_LED_22, + .active_low = 1, + }, + { + .name = "dorin:green:status", + .gpio = DORIN_GPIO_LED_STATUS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button dorin_gpio_keys[] __initdata = { + { + .desc = "jumpstart button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = DORIN_KEYS_DEBOUNCE_INTERVAL, + .gpio = DORIN_GPIO_BTN_JUMPSTART, + .active_low = 1, + }, + { + .desc = "reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = DORIN_KEYS_DEBOUNCE_INTERVAL, + .gpio = DORIN_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init ew_dorin_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + static u8 mac[6]; + + ath79_register_m25p80(NULL); + + ath79_register_usb(); + + if (ar93xx_wmac_read_mac_address(mac)) { + ath79_register_wmac(NULL, NULL); + } else { + ath79_register_wmac(art + DORIN_CALDATA_OFFSET, + art + DORIN_WMAC_MAC_OFFSET); + memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac)); + } + + mac[3] |= 0x40; + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio), + dorin_leds_gpio); + ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dorin_gpio_keys), + dorin_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_EW_DORIN, "EW-DORIN", "EmbWir-Dorin", + ew_dorin_setup); + + +static void __init ew_dorin_router_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + static u8 mac[6]; + + ath79_register_m25p80(NULL); + + ath79_register_usb(); + + if (ar93xx_wmac_read_mac_address(mac)) { + ath79_register_wmac(NULL, NULL); + } else { + ath79_register_wmac(art + DORIN_CALDATA_OFFSET, + art + DORIN_WMAC_MAC_OFFSET); + memcpy(mac, art + DORIN_WMAC_MAC_OFFSET, sizeof(mac)); + } + + mac[3] |= 0x40; + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + mac[3] &= 0x3F; + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(dorin_leds_gpio), + dorin_leds_gpio); + ath79_register_gpio_keys_polled(-1, DORIN_KEYS_POLL_INTERVAL, + ARRAY_SIZE(dorin_gpio_keys), + dorin_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_EW_DORIN_ROUTER, "EW-DORIN-ROUTER", + "EmbWir-Dorin-Router", ew_dorin_router_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c new file mode 100644 index 0000000..9e86e9a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c @@ -0,0 +1,190 @@ +/* + * Belkin AC1750DB (F9K1115V2) board support + * + * Copyright (C) 2014 Gabor Juhos + * Copyright (C) 2014 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define F9K1115V2_GPIO_LED_USB2 4 +#define F9K1115V2_GPIO_LED_WPS_AMBER 14 +#define F9K1115V2_GPIO_LED_STATUS_AMBER 15 +#define F9K1115V2_GPIO_LED_WPS_BLUE 19 +#define F9K1115V2_GPIO_LED_STATUS_BLUE 20 + +#define F9K1115V2_GPIO_BTN_WPS 16 +#define F9K1115V2_GPIO_BTN_RESET 17 + +#define F9K1115V2_GPIO_USB2_POWER 21 + +#define F9K1115V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define F9K1115V2_KEYS_DEBOUNCE_INTERVAL (3 * F9K1115V2_KEYS_POLL_INTERVAL) + +#define F9K1115V2_WAN_MAC_OFFSET 0 +#define F9K1115V2_LAN_MAC_OFFSET 6 +#define F9K1115V2_WMAC_CALDATA_OFFSET 0x1000 +#define F9K1115V2_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led f9k1115v2_leds_gpio[] __initdata = { + { + .name = "belkin:amber:status", + .gpio = F9K1115V2_GPIO_LED_STATUS_AMBER, + .active_low = 1, + }, + { + .name = "belkin:blue:status", + .gpio = F9K1115V2_GPIO_LED_STATUS_BLUE, + .active_low = 1, + }, + { + .name = "belkin:blue:wps", + .gpio = F9K1115V2_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, + { + .name = "belkin:amber:wps", + .gpio = F9K1115V2_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "belkin:green:usb2", + .gpio = F9K1115V2_GPIO_LED_USB2, + .active_low = 1, + }, +}; + +static struct gpio_keys_button f9k1115v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = F9K1115V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = F9K1115V2_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = F9K1115V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = F9K1115V2_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg f9k1115v2_ar8327_pad0_cfg = { + /* Use the RGMII interface for the GMAC0 of the AR8337 switch */ + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + .mac06_exchange_en = true, +}; + +static struct ar8327_pad_cfg f9k1115v2_ar8327_pad6_cfg = { + /* Use the SGMII interface for the GMAC6 of the AR8337 switch */ + .mode = AR8327_PAD_MAC_SGMII, + .rxclk_delay_en = true, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_platform_data f9k1115v2_ar8327_data = { + .pad0_cfg = &f9k1115v2_ar8327_pad0_cfg, + .pad6_cfg = &f9k1115v2_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info f9k1115v2_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &f9k1115v2_ar8327_data, + }, +}; + +static void __init f9k1115v2_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(f9k1115v2_leds_gpio), + f9k1115v2_leds_gpio); + ath79_register_gpio_keys_polled(-1, F9K1115V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(f9k1115v2_gpio_keys), + f9k1115v2_gpio_keys); + + ath79_register_wmac(art + F9K1115V2_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(f9k1115v2_mdio0_info, + ARRAY_SIZE(f9k1115v2_mdio0_info)); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + F9K1115V2_WAN_MAC_OFFSET, 0); + + ath79_init_mac(ath79_eth1_data.mac_addr, + art + F9K1115V2_LAN_MAC_OFFSET, 0); + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); + + ath79_register_pci(); + + ath79_register_usb(); + gpio_request_one(F9K1115V2_GPIO_USB2_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB2 power"); +} + +MIPS_MACHINE(ATH79_MACH_F9K1115V2, "F9K1115V2", "Belkin AC1750DB", + f9k1115v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-gl-inet.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-gl-inet.c new file mode 100644 index 0000000..0713f14 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-gl-inet.c @@ -0,0 +1,104 @@ +/* + * GL-CONNECT iNet board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2013 alzhao + * Copyright (C) 2014 Michel Stempin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define GL_INET_GPIO_LED_WLAN 0 +#define GL_INET_GPIO_LED_LAN 13 +#define GL_INET_GPIO_BTN_RESET 11 + +#define GL_INET_KEYS_POLL_INTERVAL 20 /* msecs */ +#define GL_INET_KEYS_DEBOUNCE_INTERVAL (3 * GL_INET_KEYS_POLL_INTERVAL) + +static const char * gl_inet_part_probes[] = { + "tp-link", /* dont change, this will use tplink parser */ + NULL , +}; + +static struct flash_platform_data gl_inet_flash_data = { + .part_probes = gl_inet_part_probes, +}; + +static struct gpio_led gl_inet_leds_gpio[] __initdata = { + { + .name = "gl-connect:red:wlan", + .gpio = GL_INET_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "gl-connect:green:lan", + .gpio = GL_INET_GPIO_LED_LAN, + .active_low = 0, + .default_state = 1, + }, +}; + +static struct gpio_keys_button gl_inet_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = GL_INET_KEYS_DEBOUNCE_INTERVAL, + .gpio = GL_INET_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init gl_inet_setup(void) +{ + /* get the mac address which is stored in the 1st 64k uboot MTD */ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + + /* get the art address, which is the last 64K. By using + 0x1fff1000, it doesn't matter it is 4M, 8M or 16M flash */ + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + /* register flash. MTD will use tp-link parser to parser MTD */ + ath79_register_m25p80(&gl_inet_flash_data); + + /* register gpio LEDs and keys */ + ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_inet_leds_gpio), + gl_inet_leds_gpio); + ath79_register_gpio_keys_polled(-1, GL_INET_KEYS_POLL_INTERVAL, + ARRAY_SIZE(gl_inet_gpio_keys), + gl_inet_gpio_keys); + + /* enable usb */ + ath79_register_usb(); + + /* register eth0 as WAN, eth1 as LAN */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + /* register wireless mac with cal data */ + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_GL_INET, "GL-INET", "GL-CONNECT INET v1", + gl_inet_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-minibox-v1.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-minibox-v1.c new file mode 100644 index 0000000..47eeb65 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-minibox-v1.c @@ -0,0 +1,85 @@ +/* + * Gainstrong MiniBox V1.0 board support + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define GS_MINIBOX_V1_GPIO_BTN_RESET 11 + +#define GS_MINIBOX_V1_GPIO_LED_SYSTEM 1 + +#define GS_MINIBOX_V1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define GS_MINIBOX_V1_KEYS_DEBOUNCE_INTERVAL (3 * GS_MINIBOX_V1_KEYS_POLL_INTERVAL) + +static const char *gs_minibox_v1_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data gs_minibox_v1_flash_data = { + .part_probes = gs_minibox_v1_part_probes, +}; + +static struct gpio_led gs_minibox_v1_leds_gpio[] __initdata = { + { + .name = "minibox-v1:green:system", + .gpio = GS_MINIBOX_V1_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button gs_minibox_v1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = GS_MINIBOX_V1_KEYS_DEBOUNCE_INTERVAL, + .gpio = GS_MINIBOX_V1_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static void __init gs_minibox_v1_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(gs_minibox_v1_leds_gpio), + gs_minibox_v1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, GS_MINIBOX_V1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(gs_minibox_v1_gpio_keys), + gs_minibox_v1_gpio_keys); + + ath79_register_usb(); + + ath79_register_m25p80(&gs_minibox_v1_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_GS_MINIBOX_V1, "MINIBOX-V1", + "MiniBox V1.0", gs_minibox_v1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-oolite.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-oolite.c new file mode 100644 index 0000000..c6cb61c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-gs-oolite.c @@ -0,0 +1,103 @@ +/* + * Oolite board support + * + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "dev-usb.h" + +#define GS_OOLITE_GPIO_BTN6 6 +#define GS_OOLITE_GPIO_BTN7 7 +#define GS_OOLITE_GPIO_BTN_RESET 11 + +#define GS_OOLITE_GPIO_LED_SYSTEM 27 + +#define GS_OOLITE_KEYS_POLL_INTERVAL 20 /* msecs */ +#define GS_OOLITE_KEYS_DEBOUNCE_INTERVAL (3 * GS_OOLITE_KEYS_POLL_INTERVAL) + +static const char *gs_oolite_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data gs_oolite_flash_data = { + .part_probes = gs_oolite_part_probes, +}; + +static struct gpio_led gs_oolite_leds_gpio[] __initdata = { + { + .name = "oolite:red:system", + .gpio = GS_OOLITE_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button gs_oolite_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL, + .gpio = GS_OOLITE_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "BTN_6", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL, + .gpio = GS_OOLITE_GPIO_BTN6, + .active_low = 0, + }, + { + .desc = "BTN_7", + .type = EV_KEY, + .code = BTN_7, + .debounce_interval = GS_OOLITE_KEYS_DEBOUNCE_INTERVAL, + .gpio = GS_OOLITE_GPIO_BTN7, + .active_low = 0, + }, +}; + +static void __init gs_oolite_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(gs_oolite_leds_gpio), + gs_oolite_leds_gpio); + + ath79_register_gpio_keys_polled(-1, GS_OOLITE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(gs_oolite_gpio_keys), + gs_oolite_gpio_keys); + + ath79_register_usb(); + + ath79_register_m25p80(&gs_oolite_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_GS_OOLITE, "GS-OOLITE", + "Oolite V1.0", gs_oolite_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-hiwifi-hc6361.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-hiwifi-hc6361.c new file mode 100644 index 0000000..6600595 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-hiwifi-hc6361.c @@ -0,0 +1,115 @@ +/* + * HiWiFi HC6361 board support + * + * Copyright (C) 2012-2013 eric + * Copyright (C) 2014 Yousong Zhou + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define HIWIFI_HC6361_GPIO_LED_WLAN_2P4 0 /* 2.4G WLAN LED */ +#define HIWIFI_HC6361_GPIO_LED_SYSTEM 1 /* System LED */ +#define HIWIFI_HC6361_GPIO_LED_INTERNET 27 /* Internet LED */ + +#define HIWIFI_HC6361_GPIO_USBPOWER 20 /* USB power control */ +#define HIWIFI_HC6361_GPIO_BTN_RST 11 /* Reset button */ + +#define HIWIFI_HC6361_KEYS_POLL_INTERVAL 20 /* msecs */ +#define HIWIFI_HC6361_KEYS_DEBOUNCE_INTERVAL \ + (3 * HIWIFI_HC6361_KEYS_POLL_INTERVAL) + +static struct gpio_led hiwifi_leds_gpio[] __initdata = { + { + .name = "hiwifi:blue:wlan-2p4", + .gpio = HIWIFI_HC6361_GPIO_LED_WLAN_2P4, + .active_low = 1, + }, { + .name = "hiwifi:blue:system", + .gpio = HIWIFI_HC6361_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "hiwifi:blue:internet", + .gpio = HIWIFI_HC6361_GPIO_LED_INTERNET, + .active_low = 1, + } +}; + +static struct gpio_keys_button hiwifi_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = HIWIFI_HC6361_KEYS_DEBOUNCE_INTERVAL, + .gpio = HIWIFI_HC6361_GPIO_BTN_RST, + .active_low = 1, + } +}; + +static void __init get_mac_from_bdinfo(u8 *mac, void *bdinfo) +{ + if (sscanf(bdinfo, "fac_mac = %2hhx:%2hhx:%2hhx:%2hhx:%2hhx:%2hhx", + &mac[0], &mac[1], &mac[2], &mac[3], + &mac[4], &mac[5]) == 6) { + return; + } + + printk(KERN_WARNING "Parsing MAC address failed.\n"); + memcpy(mac, "\x00\xba\xbe\x00\x00\x00", 6); +} + +static void __init hiwifi_hc6361_setup(void) +{ + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(NULL); + ath79_gpio_function_enable( + AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(hiwifi_leds_gpio), + hiwifi_leds_gpio); + ath79_register_gpio_keys_polled(-1, HIWIFI_HC6361_KEYS_POLL_INTERVAL, + ARRAY_SIZE(hiwifi_gpio_keys), + hiwifi_gpio_keys); + gpio_request_one(HIWIFI_HC6361_GPIO_USBPOWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + get_mac_from_bdinfo(mac, (void *) KSEG1ADDR(0x1f010180)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_HIWIFI_HC6361, "HiWiFi-HC6361", + "HiWiFi HC6361", hiwifi_hc6361_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c new file mode 100644 index 0000000..1d21424 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-hornet-ub.c @@ -0,0 +1,142 @@ +/* + * ALFA NETWORK Hornet-UB board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define HORNET_UB_GPIO_LED_WLAN 0 +#define HORNET_UB_GPIO_LED_USB 1 +#define HORNET_UB_GPIO_LED_LAN 13 +#define HORNET_UB_GPIO_LED_WAN 17 +#define HORNET_UB_GPIO_LED_WPS 27 +#define HORNET_UB_GPIO_EXT_LNA 28 + +#define HORNET_UB_GPIO_BTN_RESET 12 +#define HORNET_UB_GPIO_BTN_WPS 11 + +#define HORNET_UB_GPIO_USB_POWER 26 + +#define HORNET_UB_KEYS_POLL_INTERVAL 20 /* msecs */ +#define HORNET_UB_KEYS_DEBOUNCE_INTERVAL (3 * HORNET_UB_KEYS_POLL_INTERVAL) + +#define HORNET_UB_MAC0_OFFSET 0x0000 +#define HORNET_UB_MAC1_OFFSET 0x0006 +#define HORNET_UB_CALDATA_OFFSET 0x1000 + +static struct gpio_led hornet_ub_leds_gpio[] __initdata = { + { + .name = "alfa:blue:lan", + .gpio = HORNET_UB_GPIO_LED_LAN, + .active_low = 0, + }, + { + .name = "alfa:blue:usb", + .gpio = HORNET_UB_GPIO_LED_USB, + .active_low = 0, + }, + { + .name = "alfa:blue:wan", + .gpio = HORNET_UB_GPIO_LED_WAN, + .active_low = 1, + }, + { + .name = "alfa:blue:wlan", + .gpio = HORNET_UB_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "alfa:blue:wps", + .gpio = HORNET_UB_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button hornet_ub_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL, + .gpio = HORNET_UB_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL, + .gpio = HORNET_UB_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init hornet_ub_gpio_setup(void) +{ + u32 t; + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + gpio_request_one(HORNET_UB_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + gpio_request_one(HORNET_UB_GPIO_EXT_LNA, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "external LNA0"); + +} + +static void __init hornet_ub_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + hornet_ub_gpio_setup(); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(hornet_ub_leds_gpio), + hornet_ub_leds_gpio); + ath79_register_gpio_keys_polled(-1, HORNET_UB_KEYS_POLL_INTERVAL, + ARRAY_SIZE(hornet_ub_gpio_keys), + hornet_ub_gpio_keys); + + ath79_init_mac(ath79_eth1_data.mac_addr, + art + HORNET_UB_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth0_data.mac_addr, + art + HORNET_UB_MAC1_OFFSET, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(art + HORNET_UB_CALDATA_OFFSET, NULL); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_HORNET_UB, "HORNET-UB", "ALFA NETWORK Hornet-UB", + hornet_ub_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c new file mode 100644 index 0000000..d1fe0f8 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ja76pf.c @@ -0,0 +1,190 @@ +/* + * jjPlus JA76PF board support + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define JA76PF_KEYS_POLL_INTERVAL 20 /* msecs */ +#define JA76PF_KEYS_DEBOUNCE_INTERVAL (3 * JA76PF_KEYS_POLL_INTERVAL) + +#define JA76PF_GPIO_I2C_SCL 0 +#define JA76PF_GPIO_I2C_SDA 1 +#define JA76PF_GPIO_LED_1 5 +#define JA76PF_GPIO_LED_2 4 +#define JA76PF_GPIO_LED_3 3 +#define JA76PF_GPIO_BTN_RESET 11 + +static struct gpio_led ja76pf_leds_gpio[] __initdata = { + { + .name = "jjplus:green:led1", + .gpio = JA76PF_GPIO_LED_1, + .active_low = 1, + }, { + .name = "jjplus:green:led2", + .gpio = JA76PF_GPIO_LED_2, + .active_low = 1, + }, { + .name = "jjplus:green:led3", + .gpio = JA76PF_GPIO_LED_3, + .active_low = 1, + } +}; + +static struct gpio_keys_button ja76pf_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data ja76pf_i2c_gpio_data = { + .sda_pin = JA76PF_GPIO_I2C_SDA, + .scl_pin = JA76PF_GPIO_I2C_SCL, +}; + +static struct platform_device ja76pf_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &ja76pf_i2c_gpio_data, + } +}; + +static const char *ja76pf_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data ja76pf_flash_data = { + .part_probes = ja76pf_part_probes, +}; + +#define JA76PF_WAN_PHYMASK (1 << 4) +#define JA76PF_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 < 3)) +#define JA76PF_MDIO_PHYMASK (JA76PF_LAN_PHYMASK | JA76PF_WAN_PHYMASK) + +static void __init ja76pf_init(void) +{ + ath79_register_m25p80(&ja76pf_flash_data); + + ath79_register_mdio(0, ~JA76PF_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = JA76PF_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = JA76PF_WAN_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + platform_device_register(&ja76pf_i2c_gpio_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio), + ja76pf_leds_gpio); + + ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ja76pf_gpio_keys), + ja76pf_gpio_keys); + + ath79_register_usb(); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JA76PF, "JA76PF", "jjPlus JA76PF", ja76pf_init); + +#define JA76PF2_GPIO_LED_D2 5 +#define JA76PF2_GPIO_LED_D3 4 +#define JA76PF2_GPIO_LED_D4 3 +#define JA76PF2_GPIO_BTN_RESET 7 +#define JA76PF2_GPIO_BTN_WPS 8 + +static struct gpio_led ja76pf2_leds_gpio[] __initdata = { + { + .name = "jjplus:green:led1", + .gpio = JA76PF2_GPIO_LED_D2, + .active_low = 1, + }, { + .name = "jjplus:green:led2", + .gpio = JA76PF2_GPIO_LED_D3, + .active_low = 0, + }, { + .name = "jjplus:green:led3", + .gpio = JA76PF2_GPIO_LED_D4, + .active_low = 0, + } +}; + +static struct gpio_keys_button ja76pf2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF2_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, + .gpio = JA76PF2_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +#define JA76PF2_LAN_PHYMASK BIT(0) +#define JA76PF2_WAN_PHYMASK BIT(4) +#define JA76PF2_MDIO_PHYMASK (JA76PF2_LAN_PHYMASK | JA76PF2_WAN_PHYMASK) + +static void __init ja76pf2_init(void) +{ + ath79_register_m25p80(&ja76pf_flash_data); + + ath79_register_mdio(0, ~JA76PF2_MDIO_PHYMASK); + + /* MAC0 is connected to the CPU port of the AR8316 switch */ + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + /* MAC1 is connected to the PHY4 of the AR8316 switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf2_leds_gpio), + ja76pf2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ja76pf2_gpio_keys), + ja76pf2_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JA76PF2, "JA76PF2", "jjPlus JA76PF2", ja76pf2_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c new file mode 100644 index 0000000..a3c93cc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-jwap003.c @@ -0,0 +1,95 @@ +/* + * jjPlus JWAP003 board support + * + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define JWAP003_KEYS_POLL_INTERVAL 20 /* msecs */ +#define JWAP003_KEYS_DEBOUNCE_INTERVAL (3 * JWAP003_KEYS_POLL_INTERVAL) + +#define JWAP003_GPIO_WPS 11 +#define JWAP003_GPIO_I2C_SCL 0 +#define JWAP003_GPIO_I2C_SDA 1 + +static struct gpio_keys_button jwap003_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = JWAP003_KEYS_DEBOUNCE_INTERVAL, + .gpio = JWAP003_GPIO_WPS, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data jwap003_i2c_gpio_data = { + .sda_pin = JWAP003_GPIO_I2C_SDA, + .scl_pin = JWAP003_GPIO_I2C_SCL, +}; + +static struct platform_device jwap003_i2c_gpio_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &jwap003_i2c_gpio_data, + } +}; + +static const char *jwap003_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data jwap003_flash_data = { + .part_probes = jwap003_part_probes, +}; + +#define JWAP003_WAN_PHYMASK BIT(0) +#define JWAP003_LAN_PHYMASK BIT(4) + +static void __init jwap003_init(void) +{ + ath79_register_m25p80(&jwap003_flash_data); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = JWAP003_WAN_PHYMASK; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = JWAP003_LAN_PHYMASK; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + platform_device_register(&jwap003_i2c_gpio_device); + + ath79_register_usb(); + + ath79_register_gpio_keys_polled(-1, JWAP003_KEYS_POLL_INTERVAL, + ARRAY_SIZE(jwap003_gpio_keys), + jwap003_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_JWAP003, "JWAP003", "jjPlus JWAP003", jwap003_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mc-mac1200r.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mc-mac1200r.c new file mode 100644 index 0000000..70051cf --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mc-mac1200r.c @@ -0,0 +1,155 @@ +/* + * MERCURY MAC1200R board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2013 Gui Iribarren + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MAC1200R_GPIO_LED_WLAN2G 13 +#define MAC1200R_GPIO_LED_WLAN5G 17 +#define MAC1200R_GPIO_LED_SYSTEM 14 +#define MAC1200R_GPIO_LED_WPS 11 +#define MAC1200R_GPIO_LED_WAN 12 +#define MAC1200R_GPIO_LED_LAN1 15 +#define MAC1200R_GPIO_LED_LAN2 21 +#define MAC1200R_GPIO_LED_LAN3 22 +#define MAC1200R_GPIO_LED_LAN4 20 + +#define MAC1200R_GPIO_BTN_WPS 16 + +#define MAC1200R_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MAC1200R_KEYS_DEBOUNCE_INTERVAL (3 * MAC1200R_KEYS_POLL_INTERVAL) + +#define MAC1200R_MAC0_OFFSET 0 +#define MAC1200R_MAC1_OFFSET 6 +#define MAC1200R_WMAC_CALDATA_OFFSET 0x1000 +#define MAC1200R_PCIE_CALDATA_OFFSET 0x5000 + +static const char *mac1200r_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data mac1200r_flash_data = { + .part_probes = mac1200r_part_probes, +}; + +static struct gpio_led mac1200r_leds_gpio[] __initdata = { + { + .name = "mercury:green:wps", + .gpio = MAC1200R_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "mercury:green:system", + .gpio = MAC1200R_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "mercury:green:wlan2g", + .gpio = MAC1200R_GPIO_LED_WLAN2G, + .active_low = 1, + }, + { + .name = "mercury:green:wlan5g", + .gpio = MAC1200R_GPIO_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mac1200r_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MAC1200R_KEYS_DEBOUNCE_INTERVAL, + .gpio = MAC1200R_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + + +static void __init mac1200r_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&mac1200r_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mac1200r_leds_gpio), + mac1200r_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MAC1200R_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mac1200r_gpio_keys), + mac1200r_gpio_keys); + + ath79_init_mac(tmpmac, mac, 0); + ath79_wmac_disable_5ghz(); + ath79_register_wmac(art + MAC1200R_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, 1); + ap91_pci_init(art + MAC1200R_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN1, + AR934X_GPIO_OUT_LED_LINK3); + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN2, + AR934X_GPIO_OUT_LED_LINK2); + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN3, + AR934X_GPIO_OUT_LED_LINK1); + ath79_gpio_output_select(MAC1200R_GPIO_LED_LAN4, + AR934X_GPIO_OUT_LED_LINK0); + ath79_gpio_output_select(MAC1200R_GPIO_LED_WAN, + AR934X_GPIO_OUT_LED_LINK4); +} + +MIPS_MACHINE(ATH79_MACH_MC_MAC1200R, "MC-MAC1200R", + "MERCURY MAC1200R", + mac1200r_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr12.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr12.c new file mode 100644 index 0000000..12c9a1c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr12.c @@ -0,0 +1,115 @@ +/* + * Cisco Meraki MR12 board support + * + * Copyright (C) 2014-2015 Chris Blake + * + * Based on Atheros AP96 board support configuration + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define MR12_GPIO_LED_W4_GREEN 14 +#define MR12_GPIO_LED_W3_GREEN 13 +#define MR12_GPIO_LED_W2_GREEN 12 +#define MR12_GPIO_LED_W1_GREEN 11 + +#define MR12_GPIO_LED_WAN 15 + +#define MR12_GPIO_LED_POWER_ORANGE 16 +#define MR12_GPIO_LED_POWER_GREEN 17 + +#define MR12_GPIO_BTN_RESET 8 +#define MR12_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR12_KEYS_DEBOUNCE_INTERVAL (3 * MR12_KEYS_POLL_INTERVAL) + +#define MR12_WAN_PHYMASK BIT(4) + +#define MR12_WMAC0_MAC_OFFSET 0x120c +#define MR12_CALDATA0_OFFSET 0x1000 + +static struct gpio_led MR12_leds_gpio[] __initdata = { + { + .name = "mr12:green:wan", + .gpio = MR12_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "mr12:orange:power", + .gpio = MR12_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "mr12:green:power", + .gpio = MR12_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "mr12:green:wifi4", + .gpio = MR12_GPIO_LED_W4_GREEN, + .active_low = 1, + }, { + .name = "mr12:green:wifi3", + .gpio = MR12_GPIO_LED_W3_GREEN, + .active_low = 1, + }, { + .name = "mr12:green:wifi2", + .gpio = MR12_GPIO_LED_W2_GREEN, + .active_low = 1, + }, { + .name = "mr12:green:wifi1", + .gpio = MR12_GPIO_LED_W1_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button MR12_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR12_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR12_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init MR12_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0xbfff0000); + + ath79_register_mdio(0,0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = MR12_WAN_PHYMASK; + ath79_register_eth(0); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(MR12_leds_gpio), + MR12_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR12_KEYS_POLL_INTERVAL, + ARRAY_SIZE(MR12_gpio_keys), + MR12_gpio_keys); + + ap91_pci_init(mac + MR12_CALDATA0_OFFSET, + mac + MR12_WMAC0_MAC_OFFSET); + +} + +MIPS_MACHINE(ATH79_MACH_MR12, "MR12", "Meraki MR12", MR12_setup); \ No newline at end of file diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr16.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr16.c new file mode 100644 index 0000000..9f08e3d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr16.c @@ -0,0 +1,118 @@ +/* + * Cisco Meraki MR16 board support + * + * Copyright (C) 2015 Chris Blake + * + * Based on Atheros AP96 board support configuration + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define MR16_GPIO_LED_W4_GREEN 3 +#define MR16_GPIO_LED_W3_GREEN 2 +#define MR16_GPIO_LED_W2_GREEN 1 +#define MR16_GPIO_LED_W1_GREEN 0 + +#define MR16_GPIO_LED_WAN 4 + +#define MR16_GPIO_LED_POWER_ORANGE 5 +#define MR16_GPIO_LED_POWER_GREEN 6 + +#define MR16_GPIO_BTN_RESET 7 +#define MR16_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR16_KEYS_DEBOUNCE_INTERVAL (3 * MR16_KEYS_POLL_INTERVAL) + +#define MR16_WAN_PHYMASK BIT(0) + +#define MR16_WMAC0_MAC_OFFSET 0x120c +#define MR16_WMAC1_MAC_OFFSET 0x520c +#define MR16_CALDATA0_OFFSET 0x1000 +#define MR16_CALDATA1_OFFSET 0x5000 + +static struct gpio_led MR16_leds_gpio[] __initdata = { + { + .name = "mr16:green:wan", + .gpio = MR16_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "mr16:orange:power", + .gpio = MR16_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "mr16:green:power", + .gpio = MR16_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "mr16:green:wifi4", + .gpio = MR16_GPIO_LED_W4_GREEN, + .active_low = 1, + }, { + .name = "mr16:green:wifi3", + .gpio = MR16_GPIO_LED_W3_GREEN, + .active_low = 1, + }, { + .name = "mr16:green:wifi2", + .gpio = MR16_GPIO_LED_W2_GREEN, + .active_low = 1, + }, { + .name = "mr16:green:wifi1", + .gpio = MR16_GPIO_LED_W1_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button MR16_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR16_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR16_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init MR16_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0xbfff0000); + + ath79_register_mdio(0,0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = MR16_WAN_PHYMASK; + ath79_register_eth(0); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(MR16_leds_gpio), + MR16_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR16_KEYS_POLL_INTERVAL, + ARRAY_SIZE(MR16_gpio_keys), + MR16_gpio_keys); + + ap94_pci_init(mac + MR16_CALDATA0_OFFSET, + mac + MR16_WMAC0_MAC_OFFSET, + mac + MR16_CALDATA1_OFFSET, + mac + MR16_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_MR16, "MR16", "Meraki MR16", MR16_setup); \ No newline at end of file diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c new file mode 100644 index 0000000..8ace02f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c @@ -0,0 +1,129 @@ +/* + * MR1750 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Marek Lindner + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define MR1750_GPIO_LED_LAN 12 +#define MR1750_GPIO_LED_WLAN_2G 13 +#define MR1750_GPIO_LED_STATUS_GREEN 19 +#define MR1750_GPIO_LED_STATUS_RED 21 +#define MR1750_GPIO_LED_POWER 22 +#define MR1750_GPIO_LED_WLAN_5G 23 + +#define MR1750_GPIO_BTN_RESET 17 + +#define MR1750_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR1750_KEYS_DEBOUNCE_INTERVAL (3 * MR1750_KEYS_POLL_INTERVAL) + +#define MR1750_MAC0_OFFSET 0 +#define MR1750_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led mr1750_leds_gpio[] __initdata = { + { + .name = "mr1750:blue:power", + .gpio = MR1750_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr1750:blue:wan", + .gpio = MR1750_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "mr1750:blue:wlan24", + .gpio = MR1750_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "mr1750:blue:wlan58", + .gpio = MR1750_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "mr1750:green:status", + .gpio = MR1750_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { + .name = "mr1750:red:status", + .gpio = MR1750_GPIO_LED_STATUS_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mr1750_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR1750_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR1750_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init mr1750_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + ath79_eth0_pll_data.pll_1000 = 0xbe000101; + ath79_eth0_pll_data.pll_100 = 0x80000101; + ath79_eth0_pll_data.pll_10 = 0x80001313; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mr1750_leds_gpio), + mr1750_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR1750_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mr1750_gpio_keys), + mr1750_gpio_keys); + + ath79_init_mac(mac, art + MR1750_MAC0_OFFSET, 1); + ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac); + ath79_register_pci(); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(5); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_MR1750, "MR1750", "OpenMesh MR1750", mr1750_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr600.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr600.c new file mode 100644 index 0000000..701330c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr600.c @@ -0,0 +1,177 @@ +/* + * OpenMesh OM2P board support + * + * Copyright (C) 2012 Marek Lindner + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MR600_GPIO_LED_WLAN58 12 +#define MR600_GPIO_LED_WPS 13 +#define MR600_GPIO_LED_POWER 14 + +#define MR600V2_GPIO_LED_WLAN58_RED 12 +#define MR600V2_GPIO_LED_WPS 13 +#define MR600V2_GPIO_LED_POWER 14 +#define MR600V2_GPIO_LED_WLAN24_GREEN 18 +#define MR600V2_GPIO_LED_WLAN24_YELLOW 19 +#define MR600V2_GPIO_LED_WLAN24_RED 20 +#define MR600V2_GPIO_LED_WLAN58_GREEN 21 +#define MR600V2_GPIO_LED_WLAN58_YELLOW 22 + +#define MR600_GPIO_BTN_RESET 17 + +#define MR600_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR600_KEYS_DEBOUNCE_INTERVAL (3 * MR600_KEYS_POLL_INTERVAL) + +#define MR600_MAC_OFFSET 0 +#define MR600_WMAC_CALDATA_OFFSET 0x1000 +#define MR600_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led mr600_leds_gpio[] __initdata = { + { + .name = "mr600:orange:power", + .gpio = MR600_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr600:blue:wps", + .gpio = MR600_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "mr600:green:wlan58", + .gpio = MR600_GPIO_LED_WLAN58, + .active_low = 1, + }, +}; + +static struct gpio_led mr600v2_leds_gpio[] __initdata = { + { + .name = "mr600:blue:power", + .gpio = MR600V2_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr600:blue:wps", + .gpio = MR600V2_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "mr600:red:wlan24", + .gpio = MR600V2_GPIO_LED_WLAN24_RED, + .active_low = 1, + }, + { + .name = "mr600:yellow:wlan24", + .gpio = MR600V2_GPIO_LED_WLAN24_YELLOW, + .active_low = 1, + }, + { + .name = "mr600:green:wlan24", + .gpio = MR600V2_GPIO_LED_WLAN24_GREEN, + .active_low = 1, + }, + { + .name = "mr600:red:wlan58", + .gpio = MR600V2_GPIO_LED_WLAN58_RED, + .active_low = 1, + }, + { + .name = "mr600:yellow:wlan58", + .gpio = MR600V2_GPIO_LED_WLAN58_YELLOW, + .active_low = 1, + }, + { + .name = "mr600:green:wlan58", + .gpio = MR600V2_GPIO_LED_WLAN58_GREEN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mr600_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR600_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR600_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init mr600_base_setup(unsigned num_leds, struct gpio_led *leds) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, num_leds, leds); + ath79_register_gpio_keys_polled(-1, MR600_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mr600_gpio_keys), + mr600_gpio_keys); + + ath79_init_mac(mac, art + MR600_MAC_OFFSET, 1); + ath79_register_wmac(art + MR600_WMAC_CALDATA_OFFSET, mac); + + ath79_init_mac(mac, art + MR600_MAC_OFFSET, 8); + ap91_pci_init(art + MR600_PCIE_CALDATA_OFFSET, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR600_MAC_OFFSET, 0); + + /* GMAC0 is connected to an external PHY */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +static void __init mr600_setup(void) +{ + mr600_base_setup(ARRAY_SIZE(mr600_leds_gpio), mr600_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 0); +} + +MIPS_MACHINE(ATH79_MACH_MR600, "MR600", "OpenMesh MR600", mr600_setup); + +static void __init mr600v2_setup(void) +{ + mr600_base_setup(ARRAY_SIZE(mr600v2_leds_gpio), mr600v2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_MR600V2, "MR600v2", "OpenMesh MR600v2", mr600v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c new file mode 100644 index 0000000..9c3164d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c @@ -0,0 +1,140 @@ +/* + * MR900 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Marek Lindner + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define MR900_GPIO_LED_LAN 12 +#define MR900_GPIO_LED_WLAN_2G 13 +#define MR900_GPIO_LED_STATUS_GREEN 19 +#define MR900_GPIO_LED_STATUS_RED 21 +#define MR900_GPIO_LED_POWER 22 +#define MR900_GPIO_LED_WLAN_5G 23 + +#define MR900_GPIO_BTN_RESET 17 + +#define MR900_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MR900_KEYS_DEBOUNCE_INTERVAL (3 * MR900_KEYS_POLL_INTERVAL) + +#define MR900_MAC0_OFFSET 0 +#define MR900_WMAC_CALDATA_OFFSET 0x1000 +#define MR900_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led mr900_leds_gpio[] __initdata = { + { + .name = "mr900:blue:power", + .gpio = MR900_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "mr900:blue:wan", + .gpio = MR900_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "mr900:blue:wlan24", + .gpio = MR900_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "mr900:blue:wlan58", + .gpio = MR900_GPIO_LED_WLAN_5G, + .active_low = 1, + }, + { + .name = "mr900:green:status", + .gpio = MR900_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { + .name = "mr900:red:status", + .gpio = MR900_GPIO_LED_STATUS_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mr900_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MR900_KEYS_DEBOUNCE_INTERVAL, + .gpio = MR900_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init mr900_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6], pcie_mac[6]; + struct ath9k_platform_data *pdata; + + ath79_eth0_pll_data.pll_1000 = 0xbe000101; + ath79_eth0_pll_data.pll_100 = 0x80000101; + ath79_eth0_pll_data.pll_10 = 0x80001313; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mr900_leds_gpio), + mr900_leds_gpio); + ath79_register_gpio_keys_polled(-1, MR900_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mr900_gpio_keys), + mr900_gpio_keys); + + ath79_init_mac(mac, art + MR900_MAC0_OFFSET, 1); + ath79_register_wmac(art + MR900_WMAC_CALDATA_OFFSET, mac); + ath79_init_mac(pcie_mac, art + MR900_MAC0_OFFSET, 16); + ap91_pci_init(art + MR900_PCIE_CALDATA_OFFSET, pcie_mac); + pdata = ap9x_pci_get_wmac_data(0); + if (!pdata) { + pr_err("mr900: unable to get address of wlan data\n"); + return; + } + pdata->use_eeprom = true; + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(5); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_MR900, "MR900", "OpenMesh MR900", mr900_setup); +MIPS_MACHINE(ATH79_MACH_MR900v2, "MR900v2", "OpenMesh MR900v2", mr900_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n600.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n600.c new file mode 100644 index 0000000..a87413d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n600.c @@ -0,0 +1,202 @@ +/* + * WD My Net N600 board support + * + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define MYNET_N600_GPIO_LED_WIFI 0 +#define MYNET_N600_GPIO_LED_POWER 11 +#define MYNET_N600_GPIO_LED_INTERNET 12 +#define MYNET_N600_GPIO_LED_WPS 13 + +#define MYNET_N600_GPIO_LED_LAN1 4 +#define MYNET_N600_GPIO_LED_LAN2 3 +#define MYNET_N600_GPIO_LED_LAN3 2 +#define MYNET_N600_GPIO_LED_LAN4 1 + +#define MYNET_N600_GPIO_BTN_RESET 16 +#define MYNET_N600_GPIO_BTN_WPS 17 + +#define MYNET_N600_GPIO_EXTERNAL_LNA0 14 +#define MYNET_N600_GPIO_EXTERNAL_LNA1 15 + +#define MYNET_N600_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MYNET_N600_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_N600_KEYS_POLL_INTERVAL) + +#define MYNET_N600_MAC0_OFFSET 0 +#define MYNET_N600_MAC1_OFFSET 6 +#define MYNET_N600_WMAC_CALDATA_OFFSET 0x1000 +#define MYNET_N600_PCIE_CALDATA_OFFSET 0x5000 + +#define MYNET_N600_NVRAM_ADDR 0x1f058010 +#define MYNET_N600_NVRAM_SIZE 0x7ff0 + +static struct gpio_led mynet_n600_leds_gpio[] __initdata = { + { + .name = "wd:blue:power", + .gpio = MYNET_N600_GPIO_LED_POWER, + .active_low = 0, + }, + { + .name = "wd:blue:wps", + .gpio = MYNET_N600_GPIO_LED_WPS, + .active_low = 0, + }, + { + .name = "wd:blue:wireless", + .gpio = MYNET_N600_GPIO_LED_WIFI, + .active_low = 0, + }, + { + .name = "wd:blue:internet", + .gpio = MYNET_N600_GPIO_LED_INTERNET, + .active_low = 0, + }, + { + .name = "wd:green:lan1", + .gpio = MYNET_N600_GPIO_LED_LAN1, + .active_low = 1, + }, + { + .name = "wd:green:lan2", + .gpio = MYNET_N600_GPIO_LED_LAN2, + .active_low = 1, + }, + { + .name = "wd:green:lan3", + .gpio = MYNET_N600_GPIO_LED_LAN3, + .active_low = 1, + }, + { + .name = "wd:green:lan4", + .gpio = MYNET_N600_GPIO_LED_LAN4, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mynet_n600_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MYNET_N600_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_N600_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MYNET_N600_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_N600_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static void mynet_n600_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_N600_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, MYNET_N600_NVRAM_SIZE, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +#define MYNET_N600_WAN_PHY_MASK BIT(0) + +static void __init mynet_n600_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(NULL); + + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN1, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN2, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN3, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN4, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_N600_GPIO_LED_INTERNET, + AR934X_GPIO_OUT_GPIO); + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n600_leds_gpio), + mynet_n600_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MYNET_N600_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mynet_n600_gpio_keys), + mynet_n600_gpio_keys); + + /* + * Control signal for external LNAs 0 and 1 + * Taken from GPL bootloader source: + * board/ar7240/db12x/alpha_gpio.c + */ + ath79_wmac_set_ext_lna_gpio(0, MYNET_N600_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, MYNET_N600_GPIO_EXTERNAL_LNA1); + + mynet_n600_get_mac("wlan24mac=", tmpmac); + ath79_register_wmac(art + MYNET_N600_WMAC_CALDATA_OFFSET, tmpmac); + + mynet_n600_get_mac("wlan5mac=", tmpmac); + ap91_pci_init(art + MYNET_N600_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + mynet_n600_get_mac("lanmac=", ath79_eth1_data.mac_addr); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + mynet_n600_get_mac("wanmac=", ath79_eth0_data.mac_addr); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = MYNET_N600_WAN_PHY_MASK; + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = MYNET_N600_WAN_PHY_MASK; + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_MYNET_N600, "MYNET-N600", "WD My Net N600", + mynet_n600_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n750.c new file mode 100644 index 0000000..9d69dc5 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-n750.c @@ -0,0 +1,226 @@ +/* + * WD My Net N750 board support + * + * Copyright (C) 2013 Felix Kaechele + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + + +/* + * Taken from GPL bootloader source: + * board/ar7240/db12x/alpha_gpio.c + */ +#define MYNET_N750_GPIO_LED_WIFI 11 +#define MYNET_N750_GPIO_LED_INTERNET 12 +#define MYNET_N750_GPIO_LED_WPS 13 +#define MYNET_N750_GPIO_LED_POWER 14 + +#define MYNET_N750_GPIO_BTN_RESET 17 +#define MYNET_N750_GPIO_BTN_WPS 19 + +#define MYNET_N750_GPIO_EXTERNAL_LNA0 15 +#define MYNET_N750_GPIO_EXTERNAL_LNA1 18 + +#define MYNET_N750_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MYNET_N750_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_N750_KEYS_POLL_INTERVAL) + +#define MYNET_N750_WMAC_CALDATA_OFFSET 0x1000 +#define MYNET_N750_PCIE_CALDATA_OFFSET 0x5000 + +#define MYNET_N750_NVRAM_ADDR 0x1f058010 +#define MYNET_N750_NVRAM_SIZE 0x7ff0 + +static struct gpio_led mynet_n750_leds_gpio[] __initdata = { + { + .name = "wd:blue:power", + .gpio = MYNET_N750_GPIO_LED_POWER, + .active_low = 0, + }, + { + .name = "wd:blue:wps", + .gpio = MYNET_N750_GPIO_LED_WPS, + .active_low = 0, + }, + { + .name = "wd:blue:wireless", + .gpio = MYNET_N750_GPIO_LED_WIFI, + .active_low = 0, + }, + { + .name = "wd:blue:internet", + .gpio = MYNET_N750_GPIO_LED_INTERNET, + .active_low = 0, + }, +}; + +static struct gpio_keys_button mynet_n750_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MYNET_N750_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_N750_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MYNET_N750_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_N750_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info mynet_n750_leds_ar8327[] __initconst = { + AR8327_LED_INFO(PHY0_0, HW, "wd:green:lan1"), + AR8327_LED_INFO(PHY1_0, HW, "wd:green:lan2"), + AR8327_LED_INFO(PHY2_0, HW, "wd:green:lan3"), + AR8327_LED_INFO(PHY3_0, HW, "wd:green:lan4"), + AR8327_LED_INFO(PHY4_0, HW, "wd:green:wan"), + AR8327_LED_INFO(PHY0_1, HW, "wd:yellow:lan1"), + AR8327_LED_INFO(PHY1_1, HW, "wd:yellow:lan2"), + AR8327_LED_INFO(PHY2_1, HW, "wd:yellow:lan3"), + AR8327_LED_INFO(PHY3_1, HW, "wd:yellow:lan4"), + AR8327_LED_INFO(PHY4_1, HW, "wd:yellow:wan"), +}; + +static struct ar8327_pad_cfg mynet_n750_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg mynet_n750_ar8327_led_cfg = { + .led_ctrl0 = 0xcc35cc35, + .led_ctrl1 = 0xca35ca35, + .led_ctrl2 = 0xc935c935, + .led_ctrl3 = 0x03ffff00, + .open_drain = false, +}; + +static struct ar8327_platform_data mynet_n750_ar8327_data = { + .pad0_cfg = &mynet_n750_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &mynet_n750_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(mynet_n750_leds_ar8327), + .leds = mynet_n750_leds_ar8327, +}; + +static struct mdio_board_info mynet_n750_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &mynet_n750_ar8327_data, + }, +}; + +static void mynet_n750_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_N750_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, MYNET_N750_NVRAM_SIZE, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +/* + * The bootloader on this board powers down all PHYs on the switch + * before booting the kernel. We bring all PHYs back up so that they are + * discoverable by the mdio bus scan and the switch is detected + * correctly. + */ +static void mynet_n750_mdio_fixup(struct mii_bus *bus) +{ + int i; + + for (i = 0; i < 5; i++) + bus->write(bus, i, MII_BMCR, + (BMCR_RESET | BMCR_ANENABLE | BMCR_SPEED1000)); + + mdelay(1000); +} + +static void __init mynet_n750_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n750_leds_gpio), + mynet_n750_leds_gpio); + ath79_register_gpio_keys_polled(-1, MYNET_N750_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mynet_n750_gpio_keys), + mynet_n750_gpio_keys); + /* + * Control signal for external LNAs 0 and 1 + * Taken from GPL bootloader source: + * board/ar7240/db12x/alpha_gpio.c + */ + ath79_wmac_set_ext_lna_gpio(0, MYNET_N750_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, MYNET_N750_GPIO_EXTERNAL_LNA1); + + mynet_n750_get_mac("wlan24mac=", tmpmac); + ath79_register_wmac(art + MYNET_N750_WMAC_CALDATA_OFFSET, tmpmac); + + mynet_n750_get_mac("wlan5mac=", tmpmac); + ap91_pci_init(art + MYNET_N750_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(mynet_n750_mdio0_info, + ARRAY_SIZE(mynet_n750_mdio0_info)); + + ath79_mdio0_data.reset = mynet_n750_mdio_fixup; + ath79_register_mdio(0, 0x0); + + mynet_n750_get_mac("lanmac=", ath79_eth0_data.mac_addr); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_MYNET_N750, "MYNET-N750", "WD My Net N750", + mynet_n750_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c new file mode 100644 index 0000000..3d48ca8 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c @@ -0,0 +1,208 @@ +/* + * WD My Net WI-FI Range Extender (Codename:Starfish db12x) board support + * + * Copyright (C) 2013 Christian Lamparter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define MYNET_REXT_GPIO_LED_POWER 11 +#define MYNET_REXT_GPIO_LED_ETHERNET 12 +#define MYNET_REXT_GPIO_LED_WIFI 19 + +#define MYNET_REXT_GPIO_LED_RF_QTY1 20 +#define MYNET_REXT_GPIO_LED_RF_QTY2 21 +#define MYNET_REXT_GPIO_LED_RF_QTY3 22 + +#define MYNET_REXT_GPIO_BTN_RESET 13 +#define MYNET_REXT_GPIO_BTN_WPS 15 +#define MYNET_REXT_GPIO_SW_RF 14 + +#define MYNET_REXT_GPIO_PHY_SWRST 16 /* disables Ethernet PHY */ +#define MYNET_REXT_GPIO_PHY_INT 17 +#define MYNET_REXT_GPIO_18 18 + +#define MYNET_REXT_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MYNET_REXT_KEYS_DEBOUNCE_INTERVAL (3 * MYNET_REXT_KEYS_POLL_INTERVAL) + +#define MYNET_REXT_WMAC_CALDATA_OFFSET 0x1000 + +#define MYNET_REXT_NVRAM_ADDR 0x1f7e0010 +#define MYNET_REXT_NVRAM_SIZE 0xfff0 + +#define MYNET_REXT_ART_ADDR 0x1f7f0000 + +static const char *mynet_rext_part_probes[] = { + "cybertan", + NULL, +}; + +static struct flash_platform_data mynet_rext_flash_data = { + .type = "s25fl064k", + .part_probes = mynet_rext_part_probes, +}; + +static struct gpio_led mynet_rext_leds_gpio[] __initdata = { + { + .name = "wd:blue:power", + .gpio = MYNET_REXT_GPIO_LED_POWER, + .active_low = 0, + }, + { + .name = "wd:blue:wireless", + .gpio = MYNET_REXT_GPIO_LED_WIFI, + .active_low = 1, + }, + { + .name = "wd:blue:ethernet", + .gpio = MYNET_REXT_GPIO_LED_ETHERNET, + .active_low = 1, + }, + { + .name = "wd:blue:quality1", + .gpio = MYNET_REXT_GPIO_LED_RF_QTY1, + .active_low = 1, + }, + { + .name = "wd:blue:quality2", + .gpio = MYNET_REXT_GPIO_LED_RF_QTY2, + .active_low = 1, + }, + { + .name = "wd:blue:quality3", + .gpio = MYNET_REXT_GPIO_LED_RF_QTY3, + .active_low = 1, + }, +}; + +static struct gpio_keys_button mynet_rext_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_REXT_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_REXT_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RF Band switch", + .type = EV_SW, + .code = BTN_1, + .debounce_interval = MYNET_REXT_KEYS_DEBOUNCE_INTERVAL, + .gpio = MYNET_REXT_GPIO_SW_RF, + }, +}; + +static struct at803x_platform_data mynet_rext_at803x_data = { + .disable_smarteee = 0, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 0, + .fixup_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info mynet_rext_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 4, + .platform_data = &mynet_rext_at803x_data, + }, +}; + +static void mynet_rext_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(MYNET_REXT_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, MYNET_REXT_NVRAM_SIZE, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +static void __init mynet_rext_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(MYNET_REXT_ART_ADDR); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&mynet_rext_flash_data); + + /* GPIO configuration from drivers/char/GPIO8.c */ + + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_POWER, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_WIFI, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY1, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY2, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY3, + AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(MYNET_REXT_GPIO_LED_ETHERNET, + AR934X_GPIO_OUT_GPIO); + ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_rext_leds_gpio), + mynet_rext_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MYNET_REXT_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mynet_rext_gpio_keys), + mynet_rext_gpio_keys); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_RXD_DELAY | + AR934X_ETH_CFG_RDV_DELAY); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(mynet_rext_mdio0_info, + ARRAY_SIZE(mynet_rext_mdio0_info)); + + /* LAN */ + mynet_rext_get_mac("et0macaddr=", ath79_eth0_data.mac_addr); + + /* GMAC0 is connected to an external PHY on Port 4 */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_pll_data.pll_10 = 0x00001313; /* athrs_mac.c */ + ath79_eth0_pll_data.pll_1000 = 0x0e000000; /* athrs_mac.c */ + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_register_eth(0); + + /* WLAN */ + mynet_rext_get_mac("wl0_hwaddr=", tmpmac); + ap91_pci_init(art + MYNET_REXT_WMAC_CALDATA_OFFSET, tmpmac); +} + +MIPS_MACHINE(ATH79_MACH_MYNET_REXT, "MYNET-REXT", + "WD My Net Wi-Fi Range Extender", mynet_rext_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c new file mode 100644 index 0000000..c2460ce --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w04nu.c @@ -0,0 +1,124 @@ +/* + * Planex MZK-W04NU board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MZK_W04NU_GPIO_LED_USB 0 +#define MZK_W04NU_GPIO_LED_STATUS 1 +#define MZK_W04NU_GPIO_LED_WPS 3 +#define MZK_W04NU_GPIO_LED_WLAN 6 +#define MZK_W04NU_GPIO_LED_AP 15 +#define MZK_W04NU_GPIO_LED_ROUTER 16 + +#define MZK_W04NU_GPIO_BTN_APROUTER 5 +#define MZK_W04NU_GPIO_BTN_WPS 12 +#define MZK_W04NU_GPIO_BTN_RESET 21 + +#define MZK_W04NU_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MZK_W04NU_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W04NU_KEYS_POLL_INTERVAL) + +static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { + { + .name = "planex:green:status", + .gpio = MZK_W04NU_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "planex:blue:wps", + .gpio = MZK_W04NU_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "planex:green:wlan", + .gpio = MZK_W04NU_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "planex:green:usb", + .gpio = MZK_W04NU_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "planex:green:ap", + .gpio = MZK_W04NU_GPIO_LED_AP, + .active_low = 1, + }, { + .name = "planex:green:router", + .gpio = MZK_W04NU_GPIO_LED_ROUTER, + .active_low = 1, + } +}; + +static struct gpio_keys_button mzk_w04nu_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "aprouter", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W04NU_GPIO_BTN_APROUTER, + .active_low = 0, + } +}; + +#define MZK_W04NU_WAN_PHYMASK BIT(4) +#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) + +static void __init mzk_w04nu_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, MZK_W04NU_MDIO_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), + mzk_w04nu_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MZK_W04NU_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mzk_w04nu_gpio_keys), + mzk_w04nu_gpio_keys); + ath79_register_usb(); + + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", + mzk_w04nu_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c new file mode 100644 index 0000000..8c40365 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mzk-w300nh.c @@ -0,0 +1,115 @@ +/* + * Planex MZK-W300NH board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define MZK_W300NH_GPIO_LED_STATUS 1 +#define MZK_W300NH_GPIO_LED_WPS 3 +#define MZK_W300NH_GPIO_LED_WLAN 6 +#define MZK_W300NH_GPIO_LED_AP_GREEN 15 +#define MZK_W300NH_GPIO_LED_AP_AMBER 16 + +#define MZK_W300NH_GPIO_BTN_APROUTER 5 +#define MZK_W300NH_GPIO_BTN_WPS 12 +#define MZK_W300NH_GPIO_BTN_RESET 21 + +#define MZK_W300NH_KEYS_POLL_INTERVAL 20 /* msecs */ +#define MZK_W300NH_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W300NH_KEYS_POLL_INTERVAL) + +static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { + { + .name = "planex:green:status", + .gpio = MZK_W300NH_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "planex:blue:wps", + .gpio = MZK_W300NH_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "planex:green:wlan", + .gpio = MZK_W300NH_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "planex:green:aprouter", + .gpio = MZK_W300NH_GPIO_LED_AP_GREEN, + }, { + .name = "planex:amber:aprouter", + .gpio = MZK_W300NH_GPIO_LED_AP_AMBER, + } +}; + +static struct gpio_keys_button mzk_w300nh_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "aprouter", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = MZK_W300NH_GPIO_BTN_APROUTER, + .active_low = 0, + } +}; + +#define MZK_W300NH_WAN_PHYMASK BIT(4) +#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) + +static void __init mzk_w300nh_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, MZK_W300NH_MDIO_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), + mzk_w300nh_leds_gpio); + + ath79_register_gpio_keys_polled(-1, MZK_W300NH_KEYS_POLL_INTERVAL, + ARRAY_SIZE(mzk_w300nh_gpio_keys), + mzk_w300nh_gpio_keys); + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", + mzk_w300nh_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c new file mode 100644 index 0000000..ca00777 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg460n.c @@ -0,0 +1,220 @@ +/* + * Zyxel NBG 460N/550N/550NH board support + * + * Copyright (C) 2010 Michael Kurz + * + * based on mach-tl-wr1043nd.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +/* LEDs */ +#define NBG460N_GPIO_LED_WPS 3 +#define NBG460N_GPIO_LED_WAN 6 +#define NBG460N_GPIO_LED_POWER 14 +#define NBG460N_GPIO_LED_WLAN 15 + +/* Buttons */ +#define NBG460N_GPIO_BTN_WPS 12 +#define NBG460N_GPIO_BTN_RESET 21 + +#define NBG460N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define NBG460N_KEYS_DEBOUNCE_INTERVAL (3 * NBG460N_KEYS_POLL_INTERVAL) + +/* RTC chip PCF8563 I2C interface */ +#define NBG460N_GPIO_PCF8563_SDA 8 +#define NBG460N_GPIO_PCF8563_SCK 7 + +/* Switch configuration I2C interface */ +#define NBG460N_GPIO_RTL8366_SDA 16 +#define NBG460N_GPIO_RTL8366_SCK 18 + +static struct mtd_partition nbg460n_partitions[] = { + { + .name = "Bootbase", + .offset = 0, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "U-Boot Config", + .offset = 0x010000, + .size = 0x030000, + }, { + .name = "U-Boot", + .offset = 0x040000, + .size = 0x030000, + }, { + .name = "linux", + .offset = 0x070000, + .size = 0x0e0000, + }, { + .name = "rootfs", + .offset = 0x150000, + .size = 0x2a0000, + }, { + .name = "CalibData", + .offset = 0x3f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x070000, + .size = 0x380000, + } +}; + +static struct flash_platform_data nbg460n_flash_data = { + .parts = nbg460n_partitions, + .nr_parts = ARRAY_SIZE(nbg460n_partitions), +}; + +static struct gpio_led nbg460n_leds_gpio[] __initdata = { + { + .name = "nbg460n:green:power", + .gpio = NBG460N_GPIO_LED_POWER, + .active_low = 0, + .default_trigger = "default-on", + }, { + .name = "nbg460n:green:wps", + .gpio = NBG460N_GPIO_LED_WPS, + .active_low = 0, + }, { + .name = "nbg460n:green:wlan", + .gpio = NBG460N_GPIO_LED_WLAN, + .active_low = 0, + }, { + /* Not really for controlling the LED, + when set low the LED blinks uncontrollable */ + .name = "nbg460n:green:wan", + .gpio = NBG460N_GPIO_LED_WAN, + .active_low = 0, + } +}; + +static struct gpio_keys_button nbg460n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG460N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG460N_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { + .sda_pin = NBG460N_GPIO_PCF8563_SDA, + .scl_pin = NBG460N_GPIO_PCF8563_SCK, + .udelay = 10, +}; + +static struct platform_device nbg460n_i2c_device = { + .name = "i2c-gpio", + .id = -1, + .num_resources = 0, + .resource = NULL, + .dev = { + .platform_data = &nbg460n_i2c_device_platdata, + }, +}; + +static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("pcf8563", 0x51), + }, +}; + +static void nbg460n_i2c_init(void) +{ + /* The gpio interface */ + platform_device_register(&nbg460n_i2c_device); + /* I2C devices */ + i2c_register_board_info(0, nbg460n_i2c_devs, + ARRAY_SIZE(nbg460n_i2c_devs)); +} + + +static struct rtl8366_platform_data nbg460n_rtl8366s_data = { + .gpio_sda = NBG460N_GPIO_RTL8366_SDA, + .gpio_sck = NBG460N_GPIO_RTL8366_SCK, +}; + +static struct platform_device nbg460n_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &nbg460n_rtl8366s_data, + } +}; + +static void __init nbg460n_setup(void) +{ + /* end of bootloader sector contains mac address */ + u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); + /* last sector contains wlan calib data */ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + /* LAN Port */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + /* WAN Port */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + ath79_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + /* register the switch phy */ + platform_device_register(&nbg460n_rtl8366s_device); + + /* register flash */ + ath79_register_m25p80(&nbg460n_flash_data); + + ath79_register_wmac(eeprom, mac); + + /* register RTC chip */ + nbg460n_i2c_init(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), + nbg460n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, NBG460N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(nbg460n_gpio_keys), + nbg460n_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", + nbg460n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c new file mode 100644 index 0000000..69a73cc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c @@ -0,0 +1,276 @@ +/* + * ZyXEL NBG6716 board support + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Gabor Juhos + * Copyright (c) 2013 Andre Valentin + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-nfc.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define NBG6716_GPIO_LED_INTERNET 18 +#define NBG6716_GPIO_LED_POWER 15 +#define NBG6716_GPIO_LED_USB1 4 +#define NBG6716_GPIO_LED_USB2 13 +#define NBG6716_GPIO_LED_WIFI2G 19 +#define NBG6716_GPIO_LED_WIFI5G 17 +#define NBG6716_GPIO_LED_WPS 21 + +#define NBG6716_GPIO_BTN_RESET 23 +#define NBG6716_GPIO_BTN_RFKILL 1 +#define NBG6716_GPIO_BTN_USB1 0 +#define NBG6716_GPIO_BTN_USB2 14 +#define NBG6716_GPIO_BTN_WPS 22 + +#define NBG6716_GPIO_USB_POWER 16 + +#define NBG6716_KEYS_POLL_INTERVAL 20 /* msecs */ +#define NBG6716_KEYS_DEBOUNCE_INTERVAL (3 * NBG6716_KEYS_POLL_INTERVAL) + +#define NBG6716_MAC0_OFFSET 0 +#define NBG6716_MAC1_OFFSET 6 +#define NBG6716_WMAC_CALDATA_OFFSET 0x1000 +#define NBG6716_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led nbg6716_leds_gpio[] __initdata = { + { + .name = "zyxel:white:internet", + .gpio = NBG6716_GPIO_LED_INTERNET, + .active_low = 1, + }, + { + .name = "zyxel:white:power", + .gpio = NBG6716_GPIO_LED_POWER, + .active_low = 1, + }, + { + .name = "zyxel:white:usb1", + .gpio = NBG6716_GPIO_LED_USB1, + .active_low = 1, + }, + { + .name = "zyxel:white:usb2", + .gpio = NBG6716_GPIO_LED_USB2, + .active_low = 1, + }, + { + .name = "zyxel:white:wifi2g", + .gpio = NBG6716_GPIO_LED_WIFI2G, + .active_low = 1, + }, + { + .name = "zyxel:white:wifi5g", + .gpio = NBG6716_GPIO_LED_WIFI5G, + .active_low = 1, + }, + { + .name = "zyxel:white:wps", + .gpio = NBG6716_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button nbg6716_gpio_keys[] __initdata = { + { + .desc = "RESET button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_RFKILL, + .active_low = 0, + }, + { + .desc = "USB1 eject button", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_USB1, + .active_low = 1, + }, + { + .desc = "USB2 eject button", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_USB2, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = NBG6716_KEYS_DEBOUNCE_INTERVAL, + .gpio = NBG6716_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg nbg6716_ar8327_pad0_cfg; +static struct ar8327_pad_cfg nbg6716_ar8327_pad6_cfg; +static struct ar8327_led_cfg nbg6716_ar8327_led_cfg; + +static struct ar8327_platform_data nbg6716_ar8327_data = { + .pad0_cfg = &nbg6716_ar8327_pad0_cfg, + .pad6_cfg = &nbg6716_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &nbg6716_ar8327_led_cfg +}; + +static struct mdio_board_info nbg6716_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &nbg6716_ar8327_data, + }, +}; + +static void nbg6716_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(0x1f040000); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, 0x10000, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +static void __init nbg6716_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1f050000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(nbg6716_leds_gpio), + nbg6716_leds_gpio); + ath79_register_gpio_keys_polled(-1, NBG6716_KEYS_POLL_INTERVAL, + ARRAY_SIZE(nbg6716_gpio_keys), + nbg6716_gpio_keys); + + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); + ath79_register_nfc(); + + gpio_request_one(NBG6716_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_register_usb(); + + nbg6716_get_mac("ethaddr=", tmpmac); + + ath79_register_pci(); + + ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, tmpmac, 2); + ath79_init_mac(ath79_eth1_data.mac_addr, tmpmac, 3); + + mdiobus_register_board_info(nbg6716_mdio0_info, + ARRAY_SIZE(nbg6716_mdio0_info)); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); +} + +static void __init nbg6716_010_setup(void) +{ + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */ + nbg6716_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; + nbg6716_ar8327_pad0_cfg.txclk_delay_en = true; + nbg6716_ar8327_pad0_cfg.rxclk_delay_en = true; + nbg6716_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + nbg6716_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; + nbg6716_ar8327_pad0_cfg.mac06_exchange_en = true; + + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */ + nbg6716_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; + nbg6716_ar8327_pad6_cfg.rxclk_delay_en = true; + nbg6716_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + nbg6716_ar8327_led_cfg.open_drain = 0; + nbg6716_ar8327_led_cfg.led_ctrl0 = 0xffb7ffb7; + nbg6716_ar8327_led_cfg.led_ctrl1 = 0xffb7ffb7; + nbg6716_ar8327_led_cfg.led_ctrl2 = 0xffb7ffb7; + nbg6716_ar8327_led_cfg.led_ctrl3 = 0x03ffff00; + + nbg6716_common_setup(); +} + +MIPS_MACHINE(ATH79_MACH_NBG6716, "NBG6716", + "Zyxel NBG6716", + nbg6716_010_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c new file mode 100644 index 0000000..6b0bdc3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c @@ -0,0 +1,225 @@ +/* + * OpenMesh OM2P support + * + * Copyright (C) 2011 Marek Lindner + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define OM2P_GPIO_LED_POWER 0 +#define OM2P_GPIO_LED_GREEN 13 +#define OM2P_GPIO_LED_RED 14 +#define OM2P_GPIO_LED_YELLOW 15 +#define OM2P_GPIO_LED_LAN 16 +#define OM2P_GPIO_LED_WAN 17 +#define OM2P_GPIO_BTN_RESET 1 + +#define OM2P_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OM2P_KEYS_DEBOUNCE_INTERVAL (3 * OM2P_KEYS_POLL_INTERVAL) + +#define OM2P_WAN_PHYMASK BIT(4) + +#define OM2P_LC_GPIO_LED_POWER 1 +#define OM2P_LC_GPIO_LED_GREEN 15 +#define OM2P_LC_GPIO_LED_RED 16 +#define OM2P_LC_GPIO_LED_YELLOW 0 +#define OM2P_LC_GPIO_LED_LAN 13 +#define OM2P_LC_GPIO_LED_WAN 17 +#define OM2P_LC_GPIO_BTN_RESET 12 + +static struct flash_platform_data om2p_flash_data = { + .type = "s25sl12800", + .name = "ar7240-nor0", +}; + +static struct gpio_led om2p_leds_gpio[] __initdata = { + { + .name = "om2p:blue:power", + .gpio = OM2P_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "om2p:red:wifi", + .gpio = OM2P_GPIO_LED_RED, + .active_low = 1, + }, { + .name = "om2p:yellow:wifi", + .gpio = OM2P_GPIO_LED_YELLOW, + .active_low = 1, + }, { + .name = "om2p:green:wifi", + .gpio = OM2P_GPIO_LED_GREEN, + .active_low = 1, + }, { + .name = "om2p:blue:lan", + .gpio = OM2P_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "om2p:blue:wan", + .gpio = OM2P_GPIO_LED_WAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button om2p_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OM2P_KEYS_DEBOUNCE_INTERVAL, + .gpio = OM2P_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init om2p_setup(void) +{ + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000); + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN); + u8 *ee = (u8 *)KSEG1ADDR(0x1ffc1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(&om2p_flash_data); + + ath79_register_mdio(0, ~OM2P_WAN_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ap91_pci_init(ee, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio), + om2p_leds_gpio); + + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om2p_gpio_keys), + om2p_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_OM2P, "OM2P", "OpenMesh OM2P", om2p_setup); + + +static struct flash_platform_data om2p_lc_flash_data = { + .type = "s25sl12800", +}; + +static void __init om2p_lc_setup(void) +{ + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000); + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN); + u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000); + u32 t; + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + ath79_register_m25p80(&om2p_lc_flash_data); + + om2p_leds_gpio[0].gpio = OM2P_LC_GPIO_LED_POWER; + om2p_leds_gpio[1].gpio = OM2P_LC_GPIO_LED_RED; + om2p_leds_gpio[2].gpio = OM2P_LC_GPIO_LED_YELLOW; + om2p_leds_gpio[3].gpio = OM2P_LC_GPIO_LED_GREEN; + om2p_leds_gpio[4].gpio = OM2P_LC_GPIO_LED_LAN; + om2p_leds_gpio[5].gpio = OM2P_LC_GPIO_LED_WAN; + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio), + om2p_leds_gpio); + + om2p_gpio_keys[0].gpio = OM2P_LC_GPIO_BTN_RESET; + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om2p_gpio_keys), + om2p_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + ath79_register_mdio(0, 0x0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(art, NULL); +} + +MIPS_MACHINE(ATH79_MACH_OM2P_LC, "OM2P-LC", "OpenMesh OM2P LC", om2p_lc_setup); +MIPS_MACHINE(ATH79_MACH_OM2Pv2, "OM2Pv2", "OpenMesh OM2Pv2", om2p_lc_setup); + +static void __init om2p_hs_setup(void) +{ + u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000); + u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN); + u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000); + + /* make lan / wan leds software controllable */ + ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO); + + /* enable reset button */ + ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO); + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); + + om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN; + om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN; + + ath79_register_m25p80(&om2p_lc_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio), + om2p_leds_gpio); + ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om2p_gpio_keys), + om2p_gpio_keys); + + ath79_register_wmac(art, NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup); +MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c new file mode 100644 index 0000000..49acd3b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5p.c @@ -0,0 +1,218 @@ +/* + * OpenMesh OM5P support + * + * Copyright (C) 2013 Marek Lindner + * Copyright (C) 2014 Sven Eckelmann + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define OM5P_GPIO_LED_POWER 13 +#define OM5P_GPIO_LED_GREEN 16 +#define OM5P_GPIO_LED_RED 19 +#define OM5P_GPIO_LED_YELLOW 17 +#define OM5P_GPIO_LED_LAN 14 +#define OM5P_GPIO_LED_WAN 15 +#define OM5P_GPIO_BTN_RESET 4 +#define OM5P_GPIO_I2C_SCL 20 +#define OM5P_GPIO_I2C_SDA 21 + +#define OM5P_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OM5P_KEYS_DEBOUNCE_INTERVAL (3 * OM5P_KEYS_POLL_INTERVAL) + +#define OM5P_WMAC_CALDATA_OFFSET 0x1000 +#define OM5P_PCI_CALDATA_OFFSET 0x5000 + +static struct gpio_led om5p_leds_gpio[] __initdata = { + { + .name = "om5p:blue:power", + .gpio = OM5P_GPIO_LED_POWER, + .active_low = 1, + }, { + .name = "om5p:red:wifi", + .gpio = OM5P_GPIO_LED_RED, + .active_low = 1, + }, { + .name = "om5p:yellow:wifi", + .gpio = OM5P_GPIO_LED_YELLOW, + .active_low = 1, + }, { + .name = "om5p:green:wifi", + .gpio = OM5P_GPIO_LED_GREEN, + .active_low = 1, + }, { + .name = "om5p:blue:lan", + .gpio = OM5P_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "om5p:blue:wan", + .gpio = OM5P_GPIO_LED_WAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button om5p_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OM5P_KEYS_DEBOUNCE_INTERVAL, + .gpio = OM5P_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct flash_platform_data om5p_flash_data = { + .type = "mx25l12805d", +}; + +static void __init om5p_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + /* make lan / wan leds software controllable */ + ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&om5p_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio), + om5p_leds_gpio); + ath79_register_gpio_keys_polled(-1, OM5P_KEYS_POLL_INTERVAL, + ARRAY_SIZE(om5p_gpio_keys), + om5p_gpio_keys); + + ath79_init_mac(mac, art, 2); + ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art, 1); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_OM5P, "OM5P", "OpenMesh OM5P", om5p_setup); + +static struct i2c_gpio_platform_data om5pan_i2c_device_platdata = { + .sda_pin = OM5P_GPIO_I2C_SDA, + .scl_pin = OM5P_GPIO_I2C_SCL, + .udelay = 10, + .sda_is_open_drain = 1, + .scl_is_open_drain = 1, +}; + +static struct platform_device om5pan_i2c_device = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &om5pan_i2c_device_platdata, + }, +}; + +static struct i2c_board_info om5pan_i2c_devs[] __initdata = { + { + I2C_BOARD_INFO("tmp423", 0x4c), + }, +}; + +static struct at803x_platform_data om5p_an_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info om5p_an_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 7, + .platform_data = &om5p_an_at803x_data, + }, +}; + +static void __init om5p_an_setup(void) +{ + u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); + u8 mac[6]; + + /* temperature sensor */ + platform_device_register(&om5pan_i2c_device); + i2c_register_board_info(0, om5pan_i2c_devs, + ARRAY_SIZE(om5pan_i2c_devs)); + + /* make lan / wan leds software controllable */ + ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO); + ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&om5p_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio), + om5p_leds_gpio); + + ath79_init_mac(mac, art, 0x02); + ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + ath79_setup_ar934x_eth_rx_delay(2, 2); + ath79_register_mdio(0, 0x0); + ath79_register_mdio(1, 0x0); + + mdiobus_register_board_info(om5p_an_mdio0_info, + ARRAY_SIZE(om5p_an_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); + ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); + + /* GMAC0 is connected to the PHY7 */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_data.phy_mask = BIT(7); + ath79_eth0_pll_data.pll_1000 = 0x02000000; + ath79_eth0_pll_data.pll_100 = 0x00000101; + ath79_eth0_pll_data.pll_10 = 0x00001313; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(1); + + ath79_init_mac(mac, art, 0x10); + ap91_pci_init(art + OM5P_PCI_CALDATA_OFFSET, mac); +} + +MIPS_MACHINE(ATH79_MACH_OM5P_AN, "OM5P-AN", "OpenMesh OM5P AN", om5p_an_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-onion-omega.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-onion-omega.c new file mode 100644 index 0000000..c739840 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-onion-omega.c @@ -0,0 +1,84 @@ +/* + * Onion Omega board support + * + * Copyright (C) 2015 Boken Lin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define OMEGA_GPIO_LED_SYSTEM 27 +#define OMEGA_GPIO_BTN_RESET 11 + +#define OMEGA_GPIO_USB_POWER 8 + +#define OMEGA_KEYS_POLL_INTERVAL 20 /* msecs */ +#define OMEGA_KEYS_DEBOUNCE_INTERVAL (3 * OMEGA_KEYS_POLL_INTERVAL) + +static const char *omega_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data omega_flash_data = { + .part_probes = omega_part_probes, +}; + +static struct gpio_led omega_leds_gpio[] __initdata = { + { + .name = "onion:amber:system", + .gpio = OMEGA_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button omega_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = OMEGA_KEYS_DEBOUNCE_INTERVAL, + .gpio = OMEGA_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init onion_omega_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&omega_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(omega_leds_gpio), + omega_leds_gpio); + ath79_register_gpio_keys_polled(-1, OMEGA_KEYS_POLL_INTERVAL, + ARRAY_SIZE(omega_gpio_keys), + omega_gpio_keys); + + gpio_request_one(OMEGA_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_ONION_OMEGA, "ONION-OMEGA", "Onion Omega", onion_omega_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c new file mode 100644 index 0000000..3a350e9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb42.c @@ -0,0 +1,83 @@ +/* + * Atheros PB42 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define PB42_KEYS_POLL_INTERVAL 20 /* msecs */ +#define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL) + +#define PB42_GPIO_BTN_SW4 8 +#define PB42_GPIO_BTN_SW5 3 + +static struct gpio_keys_button pb42_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB42_GPIO_BTN_SW4, + .active_low = 1, + }, { + .desc = "sw5", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB42_GPIO_BTN_SW5, + .active_low = 1, + } +}; + +static const char *pb42_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data pb42_flash_data = { + .part_probes = pb42_part_probes, +}; + +#define PB42_WAN_PHYMASK BIT(20) +#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) +#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) + +static void __init pb42_init(void) +{ + ath79_register_m25p80(&pb42_flash_data); + + ath79_register_mdio(0, ~PB42_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = PB42_WAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pb42_gpio_keys), + pb42_gpio_keys); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_PB42, "PB42", "Atheros PB42", pb42_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c new file mode 100644 index 0000000..76715a5 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-pb92.c @@ -0,0 +1,70 @@ +/* + * Atheros PB92 board support + * + * Copyright (C) 2010 Felix Fietkau + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define PB92_KEYS_POLL_INTERVAL 20 /* msecs */ +#define PB92_KEYS_DEBOUNCE_INTERVAL (3 * PB92_KEYS_POLL_INTERVAL) + +#define PB92_GPIO_BTN_SW4 8 +#define PB92_GPIO_BTN_SW5 3 + +static struct gpio_keys_button pb92_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB92_GPIO_BTN_SW4, + .active_low = 1, + }, { + .desc = "sw5", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, + .gpio = PB92_GPIO_BTN_SW5, + .active_low = 1, + } +}; + +static void __init pb92_init(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + ath79_register_gpio_keys_polled(-1, PB92_KEYS_POLL_INTERVAL, + ARRAY_SIZE(pb92_gpio_keys), + pb92_gpio_keys); + + ath79_register_usb(); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_PB92, "PB92", "Atheros PB92", pb92_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-qihoo-c301.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-qihoo-c301.c new file mode 100644 index 0000000..a682f35 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-qihoo-c301.c @@ -0,0 +1,166 @@ +/* + * Qihoo 360 C301 board support + * + * Copyright (C) 2013 Gabor Juhos + * Copyright (C) 2014 Weijie Gao + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define QIHOO_C301_GPIO_LED_STATUS_GREEN 0 +#define QIHOO_C301_GPIO_LED_STATUS_RED 11 + +#define QIHOO_C301_GPIO_LED_WAN 1 +#define QIHOO_C301_GPIO_LED_LAN1 2 +#define QIHOO_C301_GPIO_LED_LAN2 3 +#define QIHOO_C301_GPIO_ETH_LEN_EN 18 + +#define QIHOO_C301_GPIO_BTN_RESET 16 + +#define QIHOO_C301_GPIO_USB_POWER 19 + +#define QIHOO_C301_GPIO_SPI_CS1 12 + +#define QIHOO_C301_GPIO_EXTERNAL_LNA0 14 +#define QIHOO_C301_GPIO_EXTERNAL_LNA1 15 + +#define QIHOO_C301_KEYS_POLL_INTERVAL 20 /* msecs */ +#define QIHOO_C301_KEYS_DEBOUNCE_INTERVAL \ + (3 * QIHOO_C301_KEYS_POLL_INTERVAL) + +#define QIHOO_C301_WMAC_CALDATA_OFFSET 0x1000 + +#define QIHOO_C301_NVRAM_ADDR 0x1f058010 +#define QIHOO_C301_NVRAM_SIZE 0x7ff0 + +static struct gpio_led qihoo_c301_leds_gpio[] __initdata = { + { + .name = "qihoo:green:status", + .gpio = QIHOO_C301_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { + .name = "qihoo:red:status", + .gpio = QIHOO_C301_GPIO_LED_STATUS_RED, + .active_low = 1, + }, +}; + +static struct gpio_keys_button qihoo_c301_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = QIHOO_C301_KEYS_DEBOUNCE_INTERVAL, + .gpio = QIHOO_C301_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct flash_platform_data flash __initdata = {NULL, NULL, 0}; + +static void qihoo_c301_get_mac(const char *name, char *mac) +{ + u8 *nvram = (u8 *) KSEG1ADDR(QIHOO_C301_NVRAM_ADDR); + int err; + + err = ath79_nvram_parse_mac_addr(nvram, QIHOO_C301_NVRAM_SIZE, + name, mac); + if (err) + pr_err("no MAC address found for %s\n", name); +} + +static void __init qihoo_c301_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80_multi(&flash); + + ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); + + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_WAN, + AR934X_GPIO_OUT_LED_LINK4); + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN1, + AR934X_GPIO_OUT_LED_LINK1); + ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN2, + AR934X_GPIO_OUT_LED_LINK2); + + ath79_gpio_output_select(QIHOO_C301_GPIO_SPI_CS1, + AR934X_GPIO_OUT_SPI_CS1); + + gpio_request_one(QIHOO_C301_GPIO_ETH_LEN_EN, + GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, + "Ethernet LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(qihoo_c301_leds_gpio), + qihoo_c301_leds_gpio); + + ath79_register_gpio_keys_polled(-1, QIHOO_C301_KEYS_POLL_INTERVAL, + ARRAY_SIZE(qihoo_c301_gpio_keys), + qihoo_c301_gpio_keys); + + ath79_wmac_set_ext_lna_gpio(0, QIHOO_C301_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, QIHOO_C301_GPIO_EXTERNAL_LNA1); + + qihoo_c301_get_mac("wlan24mac=", tmpmac); + ath79_register_wmac(art + QIHOO_C301_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_register_pci(); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE | + AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + qihoo_c301_get_mac("lanmac=", ath79_eth1_data.mac_addr); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + qihoo_c301_get_mac("wanmac=", ath79_eth0_data.mac_addr); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + gpio_request_one(QIHOO_C301_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_QIHOO_C301, "QIHOO-C301", "Qihoo 360 C301", + qihoo_c301_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-r6100.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-r6100.c new file mode 100644 index 0000000..c1f0e2c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-r6100.c @@ -0,0 +1,146 @@ +/* + * NETGEAR R6100 board support + * + * Copyright (C) 2014 Gabor Juhos + * Copyright (C) 2014 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define R6100_GPIO_LED_WLAN 0 +#define R6100_GPIO_LED_USB 11 +#define R6100_GPIO_LED_WAN_GREEN 13 +#define R6100_GPIO_LED_POWER_AMBER 14 +#define R6100_GPIO_LED_WAN_AMBER 15 +#define R6100_GPIO_LED_POWER_GREEN 17 + +#define R6100_GPIO_BTN_WIRELESS 1 +#define R6100_GPIO_BTN_WPS 3 +#define R6100_GPIO_BTN_RESET 12 + +#define R6100_GPIO_USB_POWER 16 + +#define R6100_KEYS_POLL_INTERVAL 20 /* msecs */ +#define R6100_KEYS_DEBOUNCE_INTERVAL (3 * R6100_KEYS_POLL_INTERVAL) + +static struct gpio_led r6100_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = R6100_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:power", + .gpio = R6100_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wan", + .gpio = R6100_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:wan", + .gpio = R6100_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, + { + .name = "netgear:blue:usb", + .gpio = R6100_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "netgear:blue:wlan", + .gpio = R6100_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button r6100_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL, + .gpio = R6100_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL, + .gpio = R6100_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = R6100_KEYS_DEBOUNCE_INTERVAL, + .gpio = R6100_GPIO_BTN_WIRELESS, + .active_low = 0, + }, +}; + +static void __init r6100_setup(void) +{ + ath79_register_leds_gpio(-1, ARRAY_SIZE(r6100_leds_gpio), + r6100_leds_gpio); + ath79_register_gpio_keys_polled(-1, R6100_KEYS_POLL_INTERVAL, + ARRAY_SIZE(r6100_gpio_keys), + r6100_gpio_keys); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + gpio_request_one(R6100_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); + ath79_register_nfc(); + + ath79_register_usb(); + + ath79_register_wmac_simple(); + + ap91_pci_init_simple(); +} + +MIPS_MACHINE(ATH79_MACH_R6100, "R6100", "NETGEAR R6100", + r6100_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c new file mode 100644 index 0000000..afd5608 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb2011.c @@ -0,0 +1,338 @@ +/* + * MikroTik RouterBOARD 2011 support + * + * Copyright (C) 2012 Stijn Tintel + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb2011: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "routerboot.h" + +#define RB2011_GPIO_NAND_NCE 14 +#define RB2011_GPIO_SFP_LOS 21 + +#define RB_ROUTERBOOT_OFFSET 0x0000 +#define RB_ROUTERBOOT_MIN_SIZE 0xb000 +#define RB_HARD_CFG_SIZE 0x1000 +#define RB_BIOS_OFFSET 0xd000 +#define RB_BIOS_SIZE 0x1000 +#define RB_SOFT_CFG_OFFSET 0xf000 +#define RB_SOFT_CFG_SIZE 0x1000 + +#define RB_ART_SIZE 0x10000 + +#define RB2011_FLAG_SFP BIT(0) +#define RB2011_FLAG_USB BIT(1) +#define RB2011_FLAG_WLAN BIT(2) + +static struct mtd_partition rb2011_spi_partitions[] = { + { + .name = "routerboot", + .offset = RB_ROUTERBOOT_OFFSET, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .size = RB_HARD_CFG_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = RB_BIOS_OFFSET, + .size = RB_BIOS_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .size = RB_SOFT_CFG_SIZE, + } +}; + +static void __init rb2011_init_partitions(const struct rb_info *info) +{ + rb2011_spi_partitions[0].size = info->hard_cfg_offs; + rb2011_spi_partitions[1].offset = info->hard_cfg_offs; + rb2011_spi_partitions[3].offset = info->soft_cfg_offs; +} + +static struct mtd_partition rb2011_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data rb2011_spi_flash_data = { + .parts = rb2011_spi_partitions, + .nr_parts = ARRAY_SIZE(rb2011_spi_partitions), +}; + +static struct ar8327_pad_cfg rb2011_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL3, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, +}; + +static struct ar8327_pad_cfg rb2011_ar8327_pad6_cfg; +static struct ar8327_sgmii_cfg rb2011_ar8327_sgmii_cfg; + +static struct ar8327_led_cfg rb2011_ar8327_led_cfg = { + .led_ctrl0 = 0xc731c731, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static const struct ar8327_led_info rb2011_ar8327_leds[] __initconst = { + AR8327_LED_INFO(PHY0_0, HW, "rb:green:eth1"), + AR8327_LED_INFO(PHY1_0, HW, "rb:green:eth2"), + AR8327_LED_INFO(PHY2_0, HW, "rb:green:eth3"), + AR8327_LED_INFO(PHY3_0, HW, "rb:green:eth4"), + AR8327_LED_INFO(PHY4_0, HW, "rb:green:eth5"), + AR8327_LED_INFO(PHY0_1, SW, "rb:green:eth6"), + AR8327_LED_INFO(PHY1_1, SW, "rb:green:eth7"), + AR8327_LED_INFO(PHY2_1, SW, "rb:green:eth8"), + AR8327_LED_INFO(PHY3_1, SW, "rb:green:eth9"), + AR8327_LED_INFO(PHY4_1, SW, "rb:green:eth10"), + AR8327_LED_INFO(PHY4_2, SW, "rb:green:usr"), +}; + +static struct ar8327_platform_data rb2011_ar8327_data = { + .pad0_cfg = &rb2011_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &rb2011_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(rb2011_ar8327_leds), + .leds = rb2011_ar8327_leds, +}; + +static struct mdio_board_info rb2011_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb2011_ar8327_data, + }, +}; + +static void __init rb2011_wlan_init(void) +{ + char *art_buf; + u8 wlan_mac[ETH_ALEN]; + + art_buf = rb_get_wlan_data(); + if (art_buf == NULL) + return; + + ath79_init_mac(wlan_mac, ath79_mac_base, 11); + ath79_register_wmac(art_buf + 0x1000, wlan_mac); + + kfree(art_buf); +} + +static void rb2011_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(RB2011_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(RB2011_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rb2011_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rb2011_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rb2011_nand_ecclayout; + } + + return 0; +} + +static void __init rb2011_nand_init(void) +{ + gpio_request_one(RB2011_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); + + ath79_nfc_set_scan_fixup(rb2011_nand_scan_fixup); + ath79_nfc_set_parts(rb2011_nand_partitions, + ARRAY_SIZE(rb2011_nand_partitions)); + ath79_nfc_set_select_chip(rb2011_nand_select_chip); + ath79_nfc_set_swap_dma(true); + ath79_register_nfc(); +} + +static int rb2011_get_port_link(unsigned port) +{ + if (port != 6) + return -EINVAL; + + /* The Loss of signal line is active low */ + return !gpio_get_value(RB2011_GPIO_SFP_LOS); +} + +static void __init rb2011_sfp_init(void) +{ + gpio_request_one(RB2011_GPIO_SFP_LOS, GPIOF_IN, "SFP LOS"); + + rb2011_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; + + rb2011_ar8327_data.pad6_cfg = &rb2011_ar8327_pad6_cfg; + + rb2011_ar8327_sgmii_cfg.sgmii_ctrl = 0xc70167d0; + rb2011_ar8327_sgmii_cfg.serdes_aen = true; + + rb2011_ar8327_data.sgmii_cfg = &rb2011_ar8327_sgmii_cfg; + + rb2011_ar8327_data.port6_cfg.force_link = 1; + rb2011_ar8327_data.port6_cfg.speed = AR8327_PORT_SPEED_1000; + rb2011_ar8327_data.port6_cfg.duplex = 1; + + rb2011_ar8327_data.get_port_link = rb2011_get_port_link; +} + +static int __init rb2011_setup(u32 flags) +{ + const struct rb_info *info; + char buf[64]; + + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); + if (!info) + return -ENODEV; + + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", + (info->board_name) ? info->board_name : ""); + mips_set_machine_name(buf); + + rb2011_init_partitions(info); + + ath79_register_m25p80(&rb2011_spi_flash_data); + rb2011_nand_init(); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb2011_mdio0_info, + ARRAY_SIZE(rb2011_mdio0_info)); + + /* GMAC0 is connected to an ar8327 switch */ + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 5); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); + + if (flags & RB2011_FLAG_SFP) + rb2011_sfp_init(); + + if (flags & RB2011_FLAG_WLAN) + rb2011_wlan_init(); + + if (flags & RB2011_FLAG_USB) + ath79_register_usb(); + + return 0; +} + +static void __init rb2011l_setup(void) +{ + rb2011_setup(0); +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011L, "2011L", rb2011l_setup); + +static void __init rb2011us_setup(void) +{ + rb2011_setup(RB2011_FLAG_SFP | RB2011_FLAG_USB); +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011US, "2011US", rb2011us_setup); + +static void __init rb2011r5_setup(void) +{ + rb2011_setup(RB2011_FLAG_SFP | RB2011_FLAG_USB | RB2011_FLAG_WLAN); +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011R5, "2011r5", rb2011r5_setup); + +static void __init rb2011g_setup(void) +{ + rb2011_setup(RB2011_FLAG_SFP | + RB2011_FLAG_USB | + RB2011_FLAG_WLAN); +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_2011G, "2011G", rb2011g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c new file mode 100644 index 0000000..1a61b45 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb4xx.c @@ -0,0 +1,465 @@ +/* + * MikroTik RouterBOARD 4xx series support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define RB4XX_GPIO_USER_LED 4 +#define RB4XX_GPIO_RESET_SWITCH 7 + +#define RB4XX_GPIO_CPLD_BASE 32 +#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1) +#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2) +#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3) +#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4) +#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5) + +#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */ +#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL) + +static struct gpio_led rb4xx_leds_gpio[] __initdata = { + { + .name = "rb4xx:yellow:user", + .gpio = RB4XX_GPIO_USER_LED, + .active_low = 0, + }, { + .name = "rb4xx:green:led1", + .gpio = RB4XX_GPIO_CPLD_LED1, + .active_low = 1, + }, { + .name = "rb4xx:green:led2", + .gpio = RB4XX_GPIO_CPLD_LED2, + .active_low = 1, + }, { + .name = "rb4xx:green:led3", + .gpio = RB4XX_GPIO_CPLD_LED3, + .active_low = 1, + }, { + .name = "rb4xx:green:led4", + .gpio = RB4XX_GPIO_CPLD_LED4, + .active_low = 1, + }, { + .name = "rb4xx:green:led5", + .gpio = RB4XX_GPIO_CPLD_LED5, + .active_low = 0, + }, +}; + +static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = { + { + .desc = "reset_switch", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL, + .gpio = RB4XX_GPIO_RESET_SWITCH, + .active_low = 1, + } +}; + +static struct platform_device rb4xx_nand_device = { + .name = "rb4xx-nand", + .id = -1, +}; + +static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = { + { + .slot = 17, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 18, + .pin = 1, + .irq = ATH79_PCI_IRQ(0), + }, { + .slot = 18, + .pin = 2, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 19, + .pin = 1, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 19, + .pin = 2, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 20, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 20, + .pin = 2, + .irq = ATH79_PCI_IRQ(0), + }, { + .slot = 21, + .pin = 1, + .irq = ATH79_PCI_IRQ(0), + }, { + .slot = 22, + .pin = 1, + .irq = ATH79_PCI_IRQ(1), + }, { + .slot = 22, + .pin = 2, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 23, + .pin = 1, + .irq = ATH79_PCI_IRQ(2), + }, { + .slot = 23, + .pin = 2, + .irq = ATH79_PCI_IRQ(0), + } +}; + +static struct mtd_partition rb4xx_partitions[] = { + { + .name = "routerboot", + .offset = 0, + .size = 0x0b000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .offset = 0x0b000, + .size = 0x01000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = 0x0d000, + .size = 0x02000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .offset = 0x0f000, + .size = 0x01000, + } +}; + +static struct flash_platform_data rb4xx_flash_data = { + .type = "pm25lv512", + .parts = rb4xx_partitions, + .nr_parts = ARRAY_SIZE(rb4xx_partitions), +}; + +static struct rb4xx_cpld_platform_data rb4xx_cpld_data = { + .gpio_base = RB4XX_GPIO_CPLD_BASE, +}; + +static struct mmc_spi_platform_data rb4xx_mmc_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, +}; + +static struct spi_board_info rb4xx_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .platform_data = &rb4xx_flash_data, + }, { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 25000000, + .modalias = "spi-rb4xx-cpld", + .platform_data = &rb4xx_cpld_data, + } +}; + +static struct spi_board_info rb4xx_microsd_info[] = { + { + .bus_num = 0, + .chip_select = 2, + .max_speed_hz = 25000000, + .modalias = "mmc_spi", + .platform_data = &rb4xx_mmc_data, + } +}; + + +static struct resource rb4xx_spi_resources[] = { + { + .start = AR71XX_SPI_BASE, + .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device rb4xx_spi_device = { + .name = "rb4xx-spi", + .id = -1, + .resource = rb4xx_spi_resources, + .num_resources = ARRAY_SIZE(rb4xx_spi_resources), +}; + +static void __init rb4xx_generic_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), + rb4xx_leds_gpio); + + ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rb4xx_gpio_keys), + rb4xx_gpio_keys); + + spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); + platform_device_register(&rb4xx_spi_device); + platform_device_register(&rb4xx_nand_device); +} + +static void __init rb411_setup(void) +{ + rb4xx_generic_setup(); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + ath79_register_mdio(0, 0xfffffffc); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x00000003; + + ath79_register_eth(0); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", + rb411_setup); + +static void __init rb411u_setup(void) +{ + rb411_setup(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", + rb411u_setup); + +#define RB433_LAN_PHYMASK BIT(0) +#define RB433_WAN_PHYMASK BIT(4) +#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK) + +static void __init rb433_setup(void) +{ + rb4xx_generic_setup(); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + ath79_register_mdio(0, ~RB433_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK; + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", + rb433_setup); + +static void __init rb433u_setup(void) +{ + rb433_setup(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", + rb433u_setup); + +static void __init rb435g_setup(void) +{ + rb4xx_generic_setup(); + + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + ath79_register_mdio(0, ~RB433_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK; + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_435G, "435G", "MikroTik RouterBOARD 435G", + rb435g_setup); + +#define RB450_LAN_PHYMASK BIT(0) +#define RB450_WAN_PHYMASK BIT(4) +#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK) + +static void __init rb450_generic_setup(int gige) +{ + rb4xx_generic_setup(); + ath79_register_mdio(0, ~RB450_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1); + ath79_eth0_data.phy_if_mode = (gige) ? + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = (gige) ? + PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK; + + ath79_register_eth(1); + ath79_register_eth(0); +} + +static void __init rb450_setup(void) +{ + rb450_generic_setup(0); +} + +MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450", + rb450_setup); + +static void __init rb450g_setup(void) +{ + rb450_generic_setup(1); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); +} + +MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", + rb450g_setup); + +static void __init rb493_setup(void) +{ + rb4xx_generic_setup(); + + ath79_register_mdio(0, 0x3fffff00); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x00000001; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", + rb493_setup); + +#define RB493G_GPIO_MDIO_MDC 7 +#define RB493G_GPIO_MDIO_DATA 8 + +#define RB493G_MDIO_PHYMASK BIT(0) + +static struct mdio_gpio_platform_data rb493g_mdio_data = { + .mdc = RB493G_GPIO_MDIO_MDC, + .mdio = RB493G_GPIO_MDIO_DATA, + + .phy_mask = ~RB493G_MDIO_PHYMASK, +}; + +static struct platform_device rb493g_mdio_device = { + .name = "mdio-gpio", + .id = -1, + .dev = { + .platform_data = &rb493g_mdio_data, + }, +}; + +static void __init rb493g_setup(void) +{ + ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | + AR71XX_GPIO_FUNC_SPI_CS2_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), + rb4xx_leds_gpio); + + spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); + spi_register_board_info(rb4xx_microsd_info, + ARRAY_SIZE(rb4xx_microsd_info)); + + platform_device_register(&rb4xx_spi_device); + platform_device_register(&rb4xx_nand_device); + + ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev; + ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + platform_device_register(&rb493g_mdio_device); + + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_usb(); + + ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G", + rb493g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c new file mode 100644 index 0000000..5656d3c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb750.c @@ -0,0 +1,346 @@ +/* + * MikroTik RouterBOARD 750/750GL support + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-usb.h" +#include "dev-eth.h" +#include "machtypes.h" +#include "routerboot.h" + +static struct rb750_led_data rb750_leds[] = { + { + .name = "rb750:green:act", + .mask = RB750_LED_ACT, + .active_low = 1, + }, { + .name = "rb750:green:port1", + .mask = RB750_LED_PORT5, + .active_low = 1, + }, { + .name = "rb750:green:port2", + .mask = RB750_LED_PORT4, + .active_low = 1, + }, { + .name = "rb750:green:port3", + .mask = RB750_LED_PORT3, + .active_low = 1, + }, { + .name = "rb750:green:port4", + .mask = RB750_LED_PORT2, + .active_low = 1, + }, { + .name = "rb750:green:port5", + .mask = RB750_LED_PORT1, + .active_low = 1, + } +}; + +static struct rb750_led_data rb750gr3_leds[] = { + { + .name = "rb750:green:act", + .mask = RB7XX_LED_ACT, + .active_low = 1, + }, +}; + +static struct rb750_led_platform_data rb750_leds_data; +static struct platform_device rb750_leds_device = { + .name = "leds-rb750", + .dev = { + .platform_data = &rb750_leds_data, + } +}; + +static struct rb7xx_nand_platform_data rb750_nand_data; +static struct platform_device rb750_nand_device = { + .name = "rb750-nand", + .id = -1, + .dev = { + .platform_data = &rb750_nand_data, + } +}; + +static void rb750_latch_change(u32 mask_clr, u32 mask_set) +{ + static DEFINE_SPINLOCK(lock); + static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; + static u32 latch_oe; + static u32 latch_clr; + unsigned long flags; + u32 t; + + spin_lock_irqsave(&lock, flags); + + if ((mask_clr & BIT(31)) != 0 && + (latch_set & RB750_LVC573_LE) == 0) { + goto unlock; + } + + latch_set = (latch_set | mask_set) & ~mask_clr; + latch_clr = (latch_clr | mask_clr) & ~mask_set; + + if (latch_oe == 0) + latch_oe = __raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_OE); + + if (likely(latch_set & RB750_LVC573_LE)) { + void __iomem *base = ath79_gpio_base; + + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= mask_clr | latch_oe | mask_set; + + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + __raw_writel(latch_clr, base + AR71XX_GPIO_REG_CLEAR); + __raw_writel(latch_set, base + AR71XX_GPIO_REG_SET); + } else if (mask_clr & RB750_LVC573_LE) { + void __iomem *base = ath79_gpio_base; + + latch_oe = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(RB750_LVC573_LE, base + AR71XX_GPIO_REG_CLEAR); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); + } + +unlock: + spin_unlock_irqrestore(&lock, flags); +} + +static void rb750_nand_enable_pins(void) +{ + rb750_latch_change(RB750_LVC573_LE, 0); + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_SPI_EN); +} + +static void rb750_nand_disable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, + AR724X_GPIO_FUNC_JTAG_DISABLE); + rb750_latch_change(0, RB750_LVC573_LE); +} + +static void __init rb750_setup(void) +{ + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + rb750_leds_data.num_leds = ARRAY_SIZE(rb750_leds); + rb750_leds_data.leds = rb750_leds; + rb750_leds_data.latch_change = rb750_latch_change; + platform_device_register(&rb750_leds_device); + + rb750_nand_data.nce_line = RB750_NAND_NCE; + rb750_nand_data.enable_pins = rb750_nand_enable_pins; + rb750_nand_data.disable_pins = rb750_nand_disable_pins; + rb750_nand_data.latch_change = rb750_latch_change; + platform_device_register(&rb750_nand_device); +} + +MIPS_MACHINE(ATH79_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", + rb750_setup); + +static struct ar8327_pad_cfg rb750gr3_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data rb750gr3_ar8327_data = { + .pad0_cfg = &rb750gr3_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info rb750g3_mdio_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb750gr3_ar8327_data, + }, +}; + +static void rb750gr3_nand_enable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, + AR724X_GPIO_FUNC_SPI_EN | + AR724X_GPIO_FUNC_SPI_CS_EN2); +} + +static void rb750gr3_nand_disable_pins(void) +{ + ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN | + AR724X_GPIO_FUNC_SPI_CS_EN2, + AR724X_GPIO_FUNC_JTAG_DISABLE); +} + +static void rb750gr3_latch_change(u32 mask_clr, u32 mask_set) +{ + static DEFINE_SPINLOCK(lock); + static u32 latch_set = RB7XX_LED_ACT; + static u32 latch_clr; + void __iomem *base = ath79_gpio_base; + unsigned long flags; + u32 t; + + spin_lock_irqsave(&lock, flags); + + latch_set = (latch_set | mask_set) & ~mask_clr; + latch_clr = (latch_clr | mask_clr) & ~mask_set; + + mask_set = latch_set & (RB7XX_USB_POWERON | RB7XX_MONITOR); + mask_clr = latch_clr & (RB7XX_USB_POWERON | RB7XX_MONITOR); + + if ((latch_set ^ RB7XX_LED_ACT) & RB7XX_LED_ACT) { + /* enable output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= RB7XX_LED_ACT; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + + mask_clr |= RB7XX_LED_ACT; + } else { + /* disable output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t &= ~RB7XX_LED_ACT; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + } + + __raw_writel(mask_set, base + AR71XX_GPIO_REG_SET); + __raw_writel(mask_clr, base + AR71XX_GPIO_REG_CLEAR); + + spin_unlock_irqrestore(&lock, flags); +} + +static void __init rb750gr3_setup(void) +{ + ath79_register_mdio(0, 0x0); + mdiobus_register_board_info(rb750g3_mdio_info, + ARRAY_SIZE(rb750g3_mdio_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_pll_data.pll_1000 = 0x62000000; + + ath79_register_eth(0); + + rb750_leds_data.num_leds = ARRAY_SIZE(rb750gr3_leds); + rb750_leds_data.leds = rb750gr3_leds; + rb750_leds_data.latch_change = rb750gr3_latch_change; + platform_device_register(&rb750_leds_device); + + rb750_nand_data.nce_line = RB7XX_NAND_NCE; + rb750_nand_data.enable_pins = rb750gr3_nand_enable_pins; + rb750_nand_data.disable_pins = rb750gr3_nand_disable_pins; + rb750_nand_data.latch_change = rb750gr3_latch_change; + platform_device_register(&rb750_nand_device); +} + +MIPS_MACHINE(ATH79_MACH_RB_750G_R3, "750Gr3", "MikroTik RouterBOARD 750GL", + rb750gr3_setup); + +#define RB751_HARDCONFIG 0x1f00b000 +#define RB751_HARDCONFIG_SIZE 0x1000 + +static void __init rb751_wlan_setup(void) +{ + u8 *hardconfig = (u8 *) KSEG1ADDR(RB751_HARDCONFIG); + struct ath9k_platform_data *wmac_data; + u16 tag_len; + u8 *tag; + u16 mac_len; + u8 *mac; + int err; + + wmac_data = ap9x_pci_get_wmac_data(0); + if (!wmac_data) { + pr_err("rb75x: unable to get address of wlan data\n"); + return; + } + + ap9x_pci_setup_wmac_led_pin(0, 9); + + err = routerboot_find_tag(hardconfig, RB751_HARDCONFIG_SIZE, + RB_ID_WLAN_DATA, &tag, &tag_len); + if (err) { + pr_err("rb75x: no calibration data found\n"); + return; + } + + err = rle_decode(tag, tag_len, (unsigned char *) wmac_data->eeprom_data, + sizeof(wmac_data->eeprom_data), NULL, NULL); + if (err) { + pr_err("rb75x: unable to decode wlan eeprom data\n"); + return; + } + + err = routerboot_find_tag(hardconfig, RB751_HARDCONFIG_SIZE, + RB_ID_MAC_ADDRESS_PACK, &mac, &mac_len); + if (err) { + pr_err("rb75x: no mac address found\n"); + return; + } + + ap91_pci_init(NULL, mac); +} + +static void __init rb751_setup(void) +{ + rb750_setup(); + ath79_register_usb(); + rb751_wlan_setup(); +} + +MIPS_MACHINE(ATH79_MACH_RB_751, "751", "MikroTik RouterBOARD 751", + rb751_setup); + +static void __init rb751g_setup(void) +{ + rb750gr3_setup(); + ath79_register_usb(); + rb751_wlan_setup(); +} + +MIPS_MACHINE(ATH79_MACH_RB_751G, "751g", "MikroTik RouterBOARD 751G", + rb751g_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb91x.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb91x.c new file mode 100644 index 0000000..9ef5c44 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb91x.c @@ -0,0 +1,349 @@ +/* + * MikroTik RouterBOARD 91X support + * + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb91x: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" +#include "routerboot.h" + +#define RB_ROUTERBOOT_OFFSET 0x0000 +#define RB_ROUTERBOOT_MIN_SIZE 0xb000 +#define RB_HARD_CFG_SIZE 0x1000 +#define RB_BIOS_OFFSET 0xd000 +#define RB_BIOS_SIZE 0x1000 +#define RB_SOFT_CFG_OFFSET 0xf000 +#define RB_SOFT_CFG_SIZE 0x1000 + +#define RB91X_FLAG_USB BIT(0) +#define RB91X_FLAG_PCIE BIT(1) + +#define RB91X_LATCH_GPIO_BASE AR934X_GPIO_COUNT +#define RB91X_LATCH_GPIO(_x) (RB91X_LATCH_GPIO_BASE + (_x)) + +#define RB91X_SSR_GPIO_BASE (RB91X_LATCH_GPIO_BASE + AR934X_GPIO_COUNT) +#define RB91X_SSR_GPIO(_x) (RB91X_SSR_GPIO_BASE + (_x)) + +#define RB91X_SSR_BIT_LED1 0 +#define RB91X_SSR_BIT_LED2 1 +#define RB91X_SSR_BIT_LED3 2 +#define RB91X_SSR_BIT_LED4 3 +#define RB91X_SSR_BIT_LED5 4 +#define RB91X_SSR_BIT_5 5 +#define RB91X_SSR_BIT_USB_POWER 6 +#define RB91X_SSR_BIT_PCIE_POWER 7 + +#define RB91X_GPIO_SSR_STROBE RB91X_LATCH_GPIO(0) +#define RB91X_GPIO_LED_POWER RB91X_LATCH_GPIO(1) +#define RB91X_GPIO_LED_USER RB91X_LATCH_GPIO(2) +#define RB91X_GPIO_NAND_READ RB91X_LATCH_GPIO(3) +#define RB91X_GPIO_NAND_RDY RB91X_LATCH_GPIO(4) +#define RB91X_GPIO_NLE RB91X_LATCH_GPIO(11) +#define RB91X_GPIO_NAND_NRW RB91X_LATCH_GPIO(12) +#define RB91X_GPIO_NAND_NCE RB91X_LATCH_GPIO(13) +#define RB91X_GPIO_NAND_CLE RB91X_LATCH_GPIO(14) +#define RB91X_GPIO_NAND_ALE RB91X_LATCH_GPIO(15) + +#define RB91X_GPIO_LED_1 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED1) +#define RB91X_GPIO_LED_2 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED2) +#define RB91X_GPIO_LED_3 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED3) +#define RB91X_GPIO_LED_4 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED4) +#define RB91X_GPIO_LED_5 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED5) +#define RB91X_GPIO_USB_POWER RB91X_SSR_GPIO(RB91X_SSR_BIT_USB_POWER) +#define RB91X_GPIO_PCIE_POWER RB91X_SSR_GPIO(RB91X_SSR_BIT_PCIE_POWER) + +struct rb_board_info { + const char *name; + u32 flags; +}; + +static struct mtd_partition rb711gr100_spi_partitions[] = { + { + .name = "routerboot", + .offset = RB_ROUTERBOOT_OFFSET, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .size = RB_HARD_CFG_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = RB_BIOS_OFFSET, + .size = RB_BIOS_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .size = RB_SOFT_CFG_SIZE, + } +}; + +static struct flash_platform_data rb711gr100_spi_flash_data = { + .parts = rb711gr100_spi_partitions, + .nr_parts = ARRAY_SIZE(rb711gr100_spi_partitions), +}; + +static int rb711gr100_gpio_latch_gpios[AR934X_GPIO_COUNT] __initdata = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 +}; + +static struct gpio_latch_platform_data rb711gr100_gpio_latch_data __initdata = { + .base = RB91X_LATCH_GPIO_BASE, + .num_gpios = ARRAY_SIZE(rb711gr100_gpio_latch_gpios), + .gpios = rb711gr100_gpio_latch_gpios, + .le_gpio_index = 11, + .le_active_low = true, +}; + +static struct rb91x_nand_platform_data rb711gr100_nand_data __initdata = { + .gpio_nce = RB91X_GPIO_NAND_NCE, + .gpio_ale = RB91X_GPIO_NAND_ALE, + .gpio_cle = RB91X_GPIO_NAND_CLE, + .gpio_rdy = RB91X_GPIO_NAND_RDY, + .gpio_read = RB91X_GPIO_NAND_READ, + .gpio_nrw = RB91X_GPIO_NAND_NRW, + .gpio_nle = RB91X_GPIO_NLE, +}; + +static u8 rb711gr100_ssr_initdata[] __initdata = { + BIT(RB91X_SSR_BIT_PCIE_POWER) | + BIT(RB91X_SSR_BIT_USB_POWER) | + BIT(RB91X_SSR_BIT_5) +}; + +static struct gen_74x164_chip_platform_data rb711gr100_ssr_data = { + .base = RB91X_SSR_GPIO_BASE, + .num_registers = ARRAY_SIZE(rb711gr100_ssr_initdata), + .init_data = rb711gr100_ssr_initdata, +}; + +static struct ath79_spi_controller_data rb711gr100_spi0_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, + .cs_line = 0, + .is_flash = true, +}; + +static struct ath79_spi_controller_data rb711gr100_spi1_cdata = { + .cs_type = ATH79_SPI_CS_TYPE_GPIO, + .cs_line = RB91X_GPIO_SSR_STROBE, +}; + +static struct spi_board_info rb711gr100_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p80", + .platform_data = &rb711gr100_spi_flash_data, + .controller_data = &rb711gr100_spi0_cdata + }, { + .bus_num = 0, + .chip_select = 1, + .max_speed_hz = 10000000, + .modalias = "74x164", + .platform_data = &rb711gr100_ssr_data, + .controller_data = &rb711gr100_spi1_cdata + } +}; + +static struct ath79_spi_platform_data rb711gr100_spi_data __initdata = { + .bus_num = 0, + .num_chipselect = 2, +}; + +static struct gpio_led rb711gr100_leds[] __initdata = { + { + .name = "rb:green:led1", + .gpio = RB91X_GPIO_LED_1, + .active_low = 0, + }, + { + .name = "rb:green:led2", + .gpio = RB91X_GPIO_LED_2, + .active_low = 0, + }, + { + .name = "rb:green:led3", + .gpio = RB91X_GPIO_LED_3, + .active_low = 0, + }, + { + .name = "rb:green:led4", + .gpio = RB91X_GPIO_LED_4, + .active_low = 0, + }, + { + .name = "rb:green:led5", + .gpio = RB91X_GPIO_LED_5, + .active_low = 0, + }, + { + .name = "rb:green:user", + .gpio = RB91X_GPIO_LED_USER, + .active_low = 0, + }, + { + .name = "rb:green:power", + .gpio = RB91X_GPIO_LED_POWER, + .active_low = 0, + }, +}; + +static struct at803x_platform_data rb91x_at803x_data = { + .disable_smarteee = 1, + .enable_rgmii_rx_delay = 1, + .enable_rgmii_tx_delay = 1, +}; + +static struct mdio_board_info rb91x_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb91x_at803x_data, + }, +}; + +static void __init rb711gr100_init_partitions(const struct rb_info *info) +{ + rb711gr100_spi_partitions[0].size = info->hard_cfg_offs; + rb711gr100_spi_partitions[1].offset = info->hard_cfg_offs; + + rb711gr100_spi_partitions[3].offset = info->soft_cfg_offs; +} + +void __init rb711gr100_wlan_init(void) +{ + char *caldata; + u8 wlan_mac[ETH_ALEN]; + + caldata = rb_get_wlan_data(); + if (caldata == NULL) + return; + + ath79_init_mac(wlan_mac, ath79_mac_base, 1); + ath79_register_wmac(caldata + 0x1000, wlan_mac); + + kfree(caldata); +} + +#define RB_BOARD_INFO(_name, _flags) \ + { \ + .name = (_name), \ + .flags = (_flags), \ + } + +static const struct rb_board_info rb711gr100_boards[] __initconst = { + RB_BOARD_INFO("911G-2HPnD", 0), + RB_BOARD_INFO("911G-5HPnD", 0), + RB_BOARD_INFO("912UAG-2HPnD", RB91X_FLAG_USB | RB91X_FLAG_PCIE), + RB_BOARD_INFO("912UAG-5HPnD", RB91X_FLAG_USB | RB91X_FLAG_PCIE), +}; + +static u32 rb711gr100_get_flags(const struct rb_info *info) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(rb711gr100_boards); i++) { + const struct rb_board_info *bi; + + bi = &rb711gr100_boards[i]; + if (strcmp(info->board_name, bi->name) == 0) + return bi->flags; + } + + return 0; +} + +static void __init rb711gr100_setup(void) +{ + const struct rb_info *info; + char buf[64]; + u32 flags; + + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); + if (!info) + return; + + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", + (info->board_name) ? info->board_name : ""); + mips_set_machine_name(buf); + + rb711gr100_init_partitions(info); + ath79_register_spi(&rb711gr100_spi_data, rb711gr100_spi_info, + ARRAY_SIZE(rb711gr100_spi_info)); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_RXD_DELAY | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb91x_mdio0_info, + ARRAY_SIZE(rb91x_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_pll_data.pll_1000 = 0x02000000; + + ath79_register_eth(0); + + rb711gr100_wlan_init(); + + platform_device_register_data(NULL, "rb91x-nand", -1, + &rb711gr100_nand_data, + sizeof(rb711gr100_nand_data)); + + platform_device_register_data(NULL, "gpio-latch", -1, + &rb711gr100_gpio_latch_data, + sizeof(rb711gr100_gpio_latch_data)); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb711gr100_leds), + rb711gr100_leds); + + flags = rb711gr100_get_flags(info); + + if (flags & RB91X_FLAG_USB) + ath79_register_usb(); + + if (flags & RB91X_FLAG_PCIE) + ath79_register_pci(); + +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_711GR100, "711Gr100", rb711gr100_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c new file mode 100644 index 0000000..c88c522 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c @@ -0,0 +1,236 @@ +/* + * MikroTik RouterBOARD 91X support + * + * Copyright (C) 2015 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "common.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-spi.h" +#include "machtypes.h" +#include "pci.h" +#include "routerboot.h" + +#define RB922_GPIO_LED_USR 12 +#define RB922_GPIO_USB_POWER 13 +#define RB922_GPIO_FAN_CTRL 14 +#define RB922_GPIO_BTN_RESET 20 +#define RB922_GPIO_NAND_NCE 23 + +#define RB922_PHY_ADDR 4 + +#define RB922_KEYS_POLL_INTERVAL 20 /* msecs */ +#define RB922_KEYS_DEBOUNCE_INTERVAL (3 * RB922_KEYS_POLL_INTERVAL) + +#define RB_ROUTERBOOT_OFFSET 0x0000 +#define RB_ROUTERBOOT_MIN_SIZE 0xb000 +#define RB_HARD_CFG_SIZE 0x1000 +#define RB_BIOS_OFFSET 0xd000 +#define RB_BIOS_SIZE 0x1000 +#define RB_SOFT_CFG_OFFSET 0xf000 +#define RB_SOFT_CFG_SIZE 0x1000 + +static struct mtd_partition rb922gs_spi_partitions[] = { + { + .name = "routerboot", + .offset = RB_ROUTERBOOT_OFFSET, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "hard_config", + .size = RB_HARD_CFG_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "bios", + .offset = RB_BIOS_OFFSET, + .size = RB_BIOS_SIZE, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "soft_config", + .size = RB_SOFT_CFG_SIZE, + } +}; + +static struct flash_platform_data rb922gs_spi_flash_data = { + .parts = rb922gs_spi_partitions, + .nr_parts = ARRAY_SIZE(rb922gs_spi_partitions), +}; + +static struct gpio_led rb922gs_leds[] __initdata = { + { + .name = "rb:green:user", + .gpio = RB922_GPIO_LED_USR, + .active_low = 1, + }, +}; + +static struct gpio_keys_button rb922gs_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RB922_KEYS_DEBOUNCE_INTERVAL, + .gpio = RB922_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct at803x_platform_data rb922gs_at803x_data = { + .disable_smarteee = 1, +}; + +static struct mdio_board_info rb922gs_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = RB922_PHY_ADDR, + .platform_data = &rb922gs_at803x_data, + }, +}; + +static void __init rb922gs_init_partitions(const struct rb_info *info) +{ + rb922gs_spi_partitions[0].size = info->hard_cfg_offs; + rb922gs_spi_partitions[1].offset = info->hard_cfg_offs; + rb922gs_spi_partitions[3].offset = info->soft_cfg_offs; +} + +static void rb922gs_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(RB922_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(RB922_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rb922gs_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rb922gs_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rb922gs_nand_ecclayout; + } + + return 0; +} + +static struct mtd_partition rb922gs_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static void __init rb922gs_nand_init(void) +{ + gpio_request_one(RB922_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); + + ath79_nfc_set_scan_fixup(rb922gs_nand_scan_fixup); + ath79_nfc_set_parts(rb922gs_nand_partitions, + ARRAY_SIZE(rb922gs_nand_partitions)); + ath79_nfc_set_select_chip(rb922gs_nand_select_chip); + ath79_nfc_set_swap_dma(true); + ath79_register_nfc(); +} + +static void __init rb922gs_setup(void) +{ + const struct rb_info *info; + char buf[64]; + + info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); + if (!info) + return; + + scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", + (info->board_name) ? info->board_name : ""); + mips_set_machine_name(buf); + + rb922gs_init_partitions(info); + ath79_register_m25p80(&rb922gs_spi_flash_data); + + rb922gs_nand_init(); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb922gs_mdio0_info, + ARRAY_SIZE(rb922gs_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(RB922_PHY_ADDR); + ath79_eth0_pll_data.pll_10 = 0x81001313; + ath79_eth0_pll_data.pll_100 = 0x81000101; + ath79_eth0_pll_data.pll_1000 = 0x8f000000; + + ath79_register_eth(0); + + ath79_register_pci(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb922gs_leds), rb922gs_leds); + ath79_register_gpio_keys_polled(-1, RB922_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rb922gs_gpio_keys), + rb922gs_gpio_keys); + + /* NOTE: + * This only supports the RB911G-5HPacD board for now. For other boards + * more devices must be registered based on the hardware options which + * can be found in the hardware configuration of RouterBOOT. + */ +} + +MIPS_MACHINE_NONAME(ATH79_MACH_RB_922GS, "922gs", rb922gs_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c new file mode 100644 index 0000000..c2261ab --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rb95x.c @@ -0,0 +1,258 @@ +/* + * MikroTik RouterBOARD 95X support + * + * Copyright (C) 2012 Stijn Tintel + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2013 Kamil Trzcinski + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb95x: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "routerboot.h" +#include "dev-leds-gpio.h" + +#define RB95X_GPIO_NAND_NCE 14 + +static struct mtd_partition rb95x_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct gpio_led rb951ui_leds_gpio[] __initdata = { + { + .name = "rb:green:wlan", + .gpio = 11, + .active_low = 1, + }, { + .name = "rb:green:act", + .gpio = 3, + .active_low = 1, + }, { + .name = "rb:green:port1", + .gpio = 13, + .active_low = 1, + }, { + .name = "rb:green:port2", + .gpio = 12, + .active_low = 1, + }, { + .name = "rb:green:port3", + .gpio = 4, + .active_low = 1, + }, { + .name = "rb:green:port4", + .gpio = 21, + .active_low = 1, + }, { + .name = "rb:green:port5", + .gpio = 16, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg rb95x_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data rb95x_ar8327_data = { + .pad0_cfg = &rb95x_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info rb95x_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &rb95x_ar8327_data, + }, +}; + +void __init rb95x_wlan_init(void) +{ + char *art_buf; + u8 wlan_mac[ETH_ALEN]; + + art_buf = rb_get_wlan_data(); + if (art_buf == NULL) + return; + + ath79_init_mac(wlan_mac, ath79_mac_base, 11); + ath79_register_wmac(art_buf + 0x1000, wlan_mac); + + kfree(art_buf); +} + +static void rb95x_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(RB95X_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(RB95X_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rb95x_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rb95x_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rb95x_nand_ecclayout; + } + + return 0; +} + +void __init rb95x_nand_init(void) +{ + gpio_request_one(RB95X_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); + + ath79_nfc_set_scan_fixup(rb95x_nand_scan_fixup); + ath79_nfc_set_parts(rb95x_nand_partitions, + ARRAY_SIZE(rb95x_nand_partitions)); + ath79_nfc_set_select_chip(rb95x_nand_select_chip); + ath79_nfc_set_swap_dma(true); + ath79_register_nfc(); +} + +static int __init rb95x_setup(void) +{ + const struct rb_info *info; + + info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x10000); + if (!info) + return -EINVAL; + + rb95x_nand_init(); + + return 0; +} + +static void __init rb951g_setup(void) +{ + if (rb95x_setup()) + return; + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(0, 0x0); + + mdiobus_register_board_info(rb95x_mdio0_info, + ARRAY_SIZE(rb95x_mdio0_info)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + rb95x_wlan_init(); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_RB_951G, "951G", "MikroTik RouterBOARD 951G-2HnD", + rb951g_setup); + +static void __init rb951ui_setup(void) +{ + if (rb95x_setup()) + return; + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + gpio_request_one(20, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "POE power"); + + rb95x_wlan_init(); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rb951ui_leds_gpio), + rb951ui_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_RB_951U, "951HnD", "MikroTik RouterBOARD 951Ui-2HnD", + rb951ui_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbsxtlite.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbsxtlite.c new file mode 100644 index 0000000..94e0b44 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbsxtlite.c @@ -0,0 +1,238 @@ +/* + * MikroTik RouterBOARD SXT Lite support + * + * Copyright (C) 2012 Stijn Tintel + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2013 Vyacheslav Adamanov + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "sxtlite: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-nfc.h" +#include "dev-wmac.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "routerboot.h" +#include + +#define SXTLITE_GPIO_NAND_NCE 14 +#define SXTLITE_GPIO_LED_USER 3 +#define SXTLITE_GPIO_LED_1 13 +#define SXTLITE_GPIO_LED_2 12 +#define SXTLITE_GPIO_LED_3 4 +#define SXTLITE_GPIO_LED_4 21 +#define SXTLITE_GPIO_LED_5 18 +#define SXTLITE_GPIO_LED_POWER 11 + +#define SXTLITE_GPIO_BUZZER 19 + +#define SXTLITE_GPIO_BTN_RESET 15 + +#define SXTLITE_KEYS_POLL_INTERVAL 20 +#define SXTLITE_KEYS_DEBOUNCE_INTERVAL (3 * SXTLITE_KEYS_POLL_INTERVAL) + +static struct mtd_partition rbsxtlite_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct gpio_led rbsxtlite_leds_gpio[] __initdata = { + { + .name = "rb:green:user", + .gpio = SXTLITE_GPIO_LED_USER, + .active_low = 1, + }, + { + .name = "rb:green:led1", + .gpio = SXTLITE_GPIO_LED_1, + .active_low = 1, + }, + { + .name = "rb:green:led2", + .gpio = SXTLITE_GPIO_LED_2, + .active_low = 1, + }, + { + .name = "rb:green:led3", + .gpio = SXTLITE_GPIO_LED_3, + .active_low = 1, + }, + { + .name = "rb:green:led4", + .gpio = SXTLITE_GPIO_LED_4, + .active_low = 1, + }, + { + .name = "rb:green:led5", + .gpio = SXTLITE_GPIO_LED_5, + .active_low = 1, + }, + { + .name = "rb:green:power", + .gpio = SXTLITE_GPIO_LED_POWER, + }, +}; + +static struct gpio_keys_button rbsxtlite_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = SXTLITE_KEYS_DEBOUNCE_INTERVAL, + .gpio = SXTLITE_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static int __init rbsxtlite_rbinfo_init(void) +{ + const struct rb_info *info; + + info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x10000); + if (!info) + return -EINVAL; + return 0; + +} + +void __init rbsxtlite_wlan_init(void) +{ + char *art_buf; + u8 wlan_mac[ETH_ALEN]; + + art_buf = rb_get_wlan_data(); + if (art_buf == NULL) + return; + + ath79_init_mac(wlan_mac, ath79_mac_base, 1); + ath79_register_wmac(art_buf + 0x1000, wlan_mac); + + kfree(art_buf); +} + +static void rbsxtlite_nand_select_chip(int chip_no) +{ + switch (chip_no) { + case 0: + gpio_set_value(SXTLITE_GPIO_NAND_NCE, 0); + break; + default: + gpio_set_value(SXTLITE_GPIO_NAND_NCE, 1); + break; + } + ndelay(500); +} + +static struct nand_ecclayout rbsxtlite_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static int rbsxtlite_nand_scan_fixup(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + + if (mtd->writesize == 512) { + /* + * Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot + * will not be able to find the kernel that we load. + */ + chip->ecc.layout = &rbsxtlite_nand_ecclayout; + } + + return 0; +} + +void __init rbsxtlite_gpio_init(void) +{ + gpio_request_one(SXTLITE_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE"); +} + +void __init rbsxtlite_nand_init(void) +{ + ath79_nfc_set_scan_fixup(rbsxtlite_nand_scan_fixup); + ath79_nfc_set_parts(rbsxtlite_nand_partitions, + ARRAY_SIZE(rbsxtlite_nand_partitions)); + ath79_nfc_set_select_chip(rbsxtlite_nand_select_chip); + ath79_nfc_set_swap_dma(true); + ath79_register_nfc(); +} + + +static void __init rbsxtlite_setup(void) +{ + if(rbsxtlite_rbinfo_init()) + return; + rbsxtlite_nand_init(); + rbsxtlite_wlan_init(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rbsxtlite_leds_gpio), + rbsxtlite_leds_gpio); + ath79_register_gpio_keys_polled(-1, SXTLITE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rbsxtlite_gpio_keys), + rbsxtlite_gpio_keys); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* GMAC0 is left unused */ + + /* GMAC1 is connected to MAC0 on the internal switch */ + /* The ethernet port connects to PHY P0, which connects to MAC1 + on the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + +} + + +MIPS_MACHINE(ATH79_MACH_RB_SXTLITE2ND, "sxt2n", "Mikrotik RouterBOARD SXT Lite2", + rbsxtlite_setup); + +MIPS_MACHINE(ATH79_MACH_RB_SXTLITE5ND, "sxt5n", "Mikrotik RouterBOARD SXT Lite5", + rbsxtlite_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c new file mode 100644 index 0000000..bb7c247 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rw2458n.c @@ -0,0 +1,91 @@ +/* + * Redwave RW2458N support + * + * Copyright (C) 2011-2013 Cezary Jackiewicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define RW2458N_GPIO_LED_D3 1 +#define RW2458N_GPIO_LED_D4 0 +#define RW2458N_GPIO_LED_D5 11 +#define RW2458N_GPIO_LED_D6 7 +#define RW2458N_GPIO_BTN_RESET 12 + +#define RW2458N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define RW2458N_KEYS_DEBOUNCE_INTERVAL (3 * RW2458N_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button rw2458n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = RW2458N_KEYS_DEBOUNCE_INTERVAL, + .gpio = RW2458N_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +#define RW2458N_WAN_PHYMASK BIT(4) + +static struct gpio_led rw2458n_leds_gpio[] __initdata = { + { + .name = "rw2458n:green:d3", + .gpio = RW2458N_GPIO_LED_D3, + .active_low = 1, + }, { + .name = "rw2458n:green:d4", + .gpio = RW2458N_GPIO_LED_D4, + .active_low = 1, + }, { + .name = "rw2458n:green:d5", + .gpio = RW2458N_GPIO_LED_D5, + .active_low = 1, + }, { + .name = "rw2458n:green:d6", + .gpio = RW2458N_GPIO_LED_D6, + .active_low = 1, + } +}; + +static void __init rw2458n_setup(void) +{ + u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + + ath79_register_m25p80(NULL); + + ath79_register_mdio(0, ~RW2458N_WAN_PHYMASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(rw2458n_leds_gpio), + rw2458n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, RW2458N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(rw2458n_gpio_keys), + rw2458n_gpio_keys); + ath79_register_usb(); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_RW2458N, "RW2458N", "Redwave RW2458N", + rw2458n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-smart-300.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-smart-300.c new file mode 100644 index 0000000..2520e96 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-smart-300.c @@ -0,0 +1,135 @@ +/* + * NC-LINK SMART-300 board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2014 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define SMART_300_GPIO_LED_WLAN 13 +#define SMART_300_GPIO_LED_WAN 18 +#define SMART_300_GPIO_LED_LAN4 19 +#define SMART_300_GPIO_LED_LAN3 12 +#define SMART_300_GPIO_LED_LAN2 21 +#define SMART_300_GPIO_LED_LAN1 20 +#define SMART_300_GPIO_LED_SYSTEM 15 +#define SMART_300_GPIO_LED_POWER 14 + +#define SMART_300_GPIO_BTN_RESET 17 +#define SMART_300_GPIO_SW_RFKILL 16 + +#define SMART_300_KEYS_POLL_INTERVAL 20 /* msecs */ +#define SMART_300_KEYS_DEBOUNCE_INTERVAL (3 * SMART_300_KEYS_POLL_INTERVAL) + +#define SMART_300_GPIO_MASK 0x007fffff + +static const char *smart_300_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data smart_300_flash_data = { + .part_probes = smart_300_part_probes, +}; + +static struct gpio_led smart_300_leds_gpio[] __initdata = { + { + .name = "nc-link:green:lan1", + .gpio = SMART_300_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "nc-link:green:lan2", + .gpio = SMART_300_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "nc-link:green:lan3", + .gpio = SMART_300_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "nc-link:green:lan4", + .gpio = SMART_300_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "nc-link:green:system", + .gpio = SMART_300_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "nc-link:green:wan", + .gpio = SMART_300_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "nc-link:green:wlan", + .gpio = SMART_300_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button smart_300_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = SMART_300_KEYS_DEBOUNCE_INTERVAL, + .gpio = SMART_300_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static void __init smart_300_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(smart_300_leds_gpio), + smart_300_leds_gpio); + + ath79_register_gpio_keys_polled(1, SMART_300_KEYS_POLL_INTERVAL, + ARRAY_SIZE(smart_300_gpio_keys), + smart_300_gpio_keys); + + ath79_register_m25p80(&smart_300_flash_data); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); + + gpio_request(SMART_300_GPIO_LED_POWER, "power"); + gpio_direction_output(SMART_300_GPIO_LED_POWER, GPIOF_OUT_INIT_LOW); +} + +MIPS_MACHINE(ATH79_MACH_SMART_300, "SMART-300", "NC-LINK SMART-300", + smart_300_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c new file mode 100644 index 0000000..855664e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-632brp.c @@ -0,0 +1,111 @@ +/* + * TrendNET TEW-632BRP board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "nvram.h" + +#define TEW_632BRP_GPIO_LED_STATUS 1 +#define TEW_632BRP_GPIO_LED_WPS 3 +#define TEW_632BRP_GPIO_LED_WLAN 6 +#define TEW_632BRP_GPIO_BTN_WPS 12 +#define TEW_632BRP_GPIO_BTN_RESET 21 + +#define TEW_632BRP_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW_632BRP_KEYS_DEBOUNCE_INTERVAL (3 * TEW_632BRP_KEYS_POLL_INTERVAL) + +#define TEW_632BRP_CONFIG_ADDR 0x1f020000 +#define TEW_632BRP_CONFIG_SIZE 0x10000 + +static struct gpio_led tew_632brp_leds_gpio[] __initdata = { + { + .name = "tew-632brp:green:status", + .gpio = TEW_632BRP_GPIO_LED_STATUS, + .active_low = 1, + }, { + .name = "tew-632brp:blue:wps", + .gpio = TEW_632BRP_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "tew-632brp:green:wlan", + .gpio = TEW_632BRP_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tew_632brp_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_632BRP_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_632BRP_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +#define TEW_632BRP_LAN_PHYMASK BIT(0) +#define TEW_632BRP_WAN_PHYMASK BIT(4) +#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ + TEW_632BRP_WAN_PHYMASK)) + +static void __init tew_632brp_setup(void) +{ + const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + u8 *wlan_mac = NULL; + + if (ath79_nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, + "lan_mac=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + wlan_mac = mac; + } + + ath79_register_mdio(0, TEW_632BRP_MDIO_MASK); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), + tew_632brp_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TEW_632BRP_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_632brp_gpio_keys), + tew_632brp_gpio_keys); + + ath79_register_wmac(eeprom, wlan_mac); +} + +MIPS_MACHINE(ATH79_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", + tew_632brp_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c new file mode 100644 index 0000000..80a5443 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-673gru.c @@ -0,0 +1,198 @@ +/* + * TRENDnet TEW-673GRU board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TEW673GRU_GPIO_LCD_SCK 0 +#define TEW673GRU_GPIO_LCD_MOSI 1 +#define TEW673GRU_GPIO_LCD_MISO 2 +#define TEW673GRU_GPIO_LCD_CS 6 + +#define TEW673GRU_GPIO_LED_WPS 9 + +#define TEW673GRU_GPIO_BTN_RESET 3 +#define TEW673GRU_GPIO_BTN_WPS 8 + +#define TEW673GRU_GPIO_RTL8366_SDA 5 +#define TEW673GRU_GPIO_RTL8366_SCK 7 + +#define TEW673GRU_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW673GRU_KEYS_DEBOUNCE_INTERVAL (3 * TEW673GRU_KEYS_POLL_INTERVAL) + +#define TEW673GRU_CAL0_OFFSET 0x1000 +#define TEW673GRU_CAL1_OFFSET 0x5000 +#define TEW673GRU_MAC0_OFFSET 0xffa0 +#define TEW673GRU_MAC1_OFFSET 0xffb4 + +#define TEW673GRU_CAL_LOCATION_0 0x1f660000 +#define TEW673GRU_CAL_LOCATION_1 0x1f7f0000 + +static struct gpio_led tew673gru_leds_gpio[] __initdata = { + { + .name = "trendnet:blue:wps", + .gpio = TEW673GRU_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_keys_button tew673gru_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW673GRU_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW673GRU_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW673GRU_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW673GRU_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8366_initval tew673gru_rtl8366s_initvals[] = { + { .reg = 0x06, .val = 0x0108 }, +}; + +static struct rtl8366_platform_data tew673gru_rtl8366s_data = { + .gpio_sda = TEW673GRU_GPIO_RTL8366_SDA, + .gpio_sck = TEW673GRU_GPIO_RTL8366_SCK, + .num_initvals = ARRAY_SIZE(tew673gru_rtl8366s_initvals), + .initvals = tew673gru_rtl8366s_initvals, +}; + +static struct platform_device tew673gru_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tew673gru_rtl8366s_data, + } +}; + +static struct spi_board_info tew673gru_spi_info[] = { + { + .bus_num = 1, + .chip_select = 0, + .max_speed_hz = 400000, + .modalias = "spidev", + .mode = SPI_MODE_2, + .controller_data = (void *) TEW673GRU_GPIO_LCD_CS, + }, +}; + +static struct spi_gpio_platform_data tew673gru_spi_data = { + .sck = TEW673GRU_GPIO_LCD_SCK, + .miso = TEW673GRU_GPIO_LCD_MISO, + .mosi = TEW673GRU_GPIO_LCD_MOSI, + .num_chipselect = 1, +}; + +static struct platform_device tew673gru_spi_device = { + .name = "spi_gpio", + .id = 1, + .dev = { + .platform_data = &tew673gru_spi_data, + }, +}; + +static bool __init tew673gru_is_caldata_valid(u8 *p) +{ + u16 *magic0, *magic1; + + magic0 = (u16 *)(p + TEW673GRU_CAL0_OFFSET); + magic1 = (u16 *)(p + TEW673GRU_CAL1_OFFSET); + + return (*magic0 == 0xa55a && *magic1 == 0xa55a); +} + +static void __init tew673gru_wlan_init(void) +{ + u8 mac1[ETH_ALEN], mac2[ETH_ALEN]; + u8 *caldata; + + caldata = (u8 *) KSEG1ADDR(TEW673GRU_CAL_LOCATION_0); + if (!tew673gru_is_caldata_valid(caldata)) { + caldata = (u8 *)KSEG1ADDR(TEW673GRU_CAL_LOCATION_1); + if (!tew673gru_is_caldata_valid(caldata)) { + pr_err("no calibration data found\n"); + return; + } + } + + ath79_parse_ascii_mac(caldata + TEW673GRU_MAC0_OFFSET, mac1); + ath79_parse_ascii_mac(caldata + TEW673GRU_MAC1_OFFSET, mac2); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap94_pci_init(caldata + TEW673GRU_CAL0_OFFSET, mac1, + caldata + TEW673GRU_CAL1_OFFSET, mac2); +} + +static void __init tew673gru_setup(void) +{ + tew673gru_wlan_init(); + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x11110000; + + ath79_eth1_data.mii_bus_dev = &tew673gru_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + ath79_eth1_pll_data.pll_1000 = 0x11110000; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew673gru_leds_gpio), + tew673gru_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TEW673GRU_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew673gru_gpio_keys), + tew673gru_gpio_keys); + + ath79_register_usb(); + + platform_device_register(&tew673gru_rtl8366s_device); + + spi_register_board_info(tew673gru_spi_info, + ARRAY_SIZE(tew673gru_spi_info)); + platform_device_register(&tew673gru_spi_device); +} + +MIPS_MACHINE(ATH79_MACH_TEW_673GRU, "TEW-673GRU", "TRENDnet TEW-673GRU", + tew673gru_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c new file mode 100644 index 0000000..304b994 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-712br.c @@ -0,0 +1,153 @@ +/* + * TRENDnet TEW-712BR board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TEW_712BR_GPIO_BTN_WPS 11 +#define TEW_712BR_GPIO_BTN_RESET 12 + +#define TEW_712BR_GPIO_LED_LAN1 13 +#define TEW_712BR_GPIO_LED_LAN2 14 +#define TEW_712BR_GPIO_LED_LAN3 15 +#define TEW_712BR_GPIO_LED_LAN4 16 +#define TEW_712BR_GPIO_LED_POWER_GREEN 20 +#define TEW_712BR_GPIO_LED_POWER_ORANGE 27 +#define TEW_712BR_GPIO_LED_WAN_GREEN 17 +#define TEW_712BR_GPIO_LED_WAN_ORANGE 23 +#define TEW_712BR_GPIO_LED_WLAN 0 +#define TEW_712BR_GPIO_LED_WPS 26 + +#define TEW_712BR_GPIO_WAN_LED_ENABLE 1 + +#define TEW_712BR_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW_712BR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_712BR_KEYS_POLL_INTERVAL) + +#define TEW_712BR_ART_ADDRESS 0x1f010000 +#define TEW_712BR_CALDATA_OFFSET 0x1000 + +#define TEW_712BR_MAC_PART_ADDRESS 0x1f020000 +#define TEW_712BR_LAN_MAC_OFFSET 0x04 +#define TEW_712BR_WAN_MAC_OFFSET 0x16 + +static struct gpio_led tew_712br_leds_gpio[] __initdata = { + { + .name = "trendnet:green:lan1", + .gpio = TEW_712BR_GPIO_LED_LAN1, + .active_low = 0, + }, { + .name = "trendnet:green:lan2", + .gpio = TEW_712BR_GPIO_LED_LAN2, + .active_low = 0, + }, { + .name = "trendnet:green:lan3", + .gpio = TEW_712BR_GPIO_LED_LAN3, + .active_low = 0, + }, { + .name = "trendnet:green:lan4", + .gpio = TEW_712BR_GPIO_LED_LAN4, + .active_low = 0, + }, { + .name = "trendnet:blue:wps", + .gpio = TEW_712BR_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "trendnet:green:power", + .gpio = TEW_712BR_GPIO_LED_POWER_GREEN, + .active_low = 0, + }, { + .name = "trendnet:orange:power", + .gpio = TEW_712BR_GPIO_LED_POWER_ORANGE, + .active_low = 0, + }, { + .name = "trendnet:green:wan", + .gpio = TEW_712BR_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "trendnet:orange:wan", + .gpio = TEW_712BR_GPIO_LED_WAN_ORANGE, + .active_low = 0, + }, { + .name = "trendnet:green:wlan", + .gpio = TEW_712BR_GPIO_LED_WLAN, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tew_712br_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_712BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_712BR_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_712BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_712BR_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init tew_712br_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(TEW_712BR_ART_ADDRESS); + u8 *mac = (u8 *) KSEG1ADDR(TEW_712BR_MAC_PART_ADDRESS); + u8 lan_mac[ETH_ALEN]; + u8 wan_mac[ETH_ALEN]; + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + gpio_request_one(TEW_712BR_GPIO_WAN_LED_ENABLE, + GPIOF_OUT_INIT_LOW, "WAN LED enable"); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_712br_leds_gpio), + tew_712br_leds_gpio); + + ath79_register_gpio_keys_polled(1, TEW_712BR_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_712br_gpio_keys), + tew_712br_gpio_keys); + + ath79_register_m25p80(NULL); + + ath79_parse_ascii_mac(mac + TEW_712BR_LAN_MAC_OFFSET, lan_mac); + ath79_parse_ascii_mac(mac + TEW_712BR_WAN_MAC_OFFSET, wan_mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(art + TEW_712BR_CALDATA_OFFSET, wan_mac); +} + +MIPS_MACHINE(ATH79_MACH_TEW_712BR, "TEW-712BR", + "TRENDnet TEW-712BR", tew_712br_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-732br.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-732br.c new file mode 100644 index 0000000..1f26f6f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tew-732br.c @@ -0,0 +1,127 @@ +/* + * TRENDnet TEW-732BR board support + * + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TEW_732BR_GPIO_BTN_WPS 16 +#define TEW_732BR_GPIO_BTN_RESET 17 + +#define TEW_732BR_GPIO_LED_POWER_GREEN 4 +#define TEW_732BR_GPIO_LED_POWER_AMBER 14 +#define TEW_732BR_GPIO_LED_PLANET_GREEN 12 +#define TEW_732BR_GPIO_LED_PLANET_AMBER 22 + +#define TEW_732BR_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TEW_732BR_KEYS_DEBOUNCE_INTERVAL (3 * TEW_732BR_KEYS_POLL_INTERVAL) + +#define TEW_732BR_ART_ADDRESS 0x1fff0000 +#define TEW_732BR_CALDATA_OFFSET 0x1000 +#define TEW_732BR_LAN_MAC_OFFSET 0xffa0 +#define TEW_732BR_WAN_MAC_OFFSET 0xffb4 + +static struct gpio_led tew_732br_leds_gpio[] __initdata = { + { + .name = "trendnet:green:power", + .gpio = TEW_732BR_GPIO_LED_POWER_GREEN, + .active_low = 0, + }, + { + .name = "trendnet:amber:power", + .gpio = TEW_732BR_GPIO_LED_POWER_AMBER, + .active_low = 0, + }, + { + .name = "trendnet:green:wan", + .gpio = TEW_732BR_GPIO_LED_PLANET_GREEN, + .active_low = 1, + }, + { + .name = "trendnet:amber:wan", + .gpio = TEW_732BR_GPIO_LED_PLANET_AMBER, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tew_732br_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TEW_732BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_732BR_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TEW_732BR_KEYS_DEBOUNCE_INTERVAL, + .gpio = TEW_732BR_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static void __init tew_732br_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(TEW_732BR_ART_ADDRESS); + u8 lan_mac[ETH_ALEN]; + u8 wan_mac[ETH_ALEN]; + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_732br_leds_gpio), + tew_732br_leds_gpio); + + ath79_register_gpio_keys_polled(1, TEW_732BR_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tew_732br_gpio_keys), + tew_732br_gpio_keys); + + ath79_register_m25p80(NULL); + + ath79_parse_ascii_mac(art + TEW_732BR_LAN_MAC_OFFSET, lan_mac); + ath79_parse_ascii_mac(art + TEW_732BR_WAN_MAC_OFFSET, wan_mac); + + ath79_register_wmac(art + TEW_732BR_CALDATA_OFFSET, lan_mac); + + ath79_register_mdio(1, 0x0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + /* LAN: GMAC1 is connected to the internal switch */ + ath79_init_mac(ath79_eth1_data.mac_addr, lan_mac, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN: GMAC0 is connected to the PHY4 of the internal switch */ + ath79_init_mac(ath79_eth0_data.mac_addr, wan_mac, 0); + + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_TEW_732BR, "TEW-732BR", "TRENDnet TEW-732BR", + tew_732br_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c new file mode 100644 index 0000000..74ccf63 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr11u.c @@ -0,0 +1,183 @@ +/* + * TP-LINK TL-MR11U/TL-MR3040 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_MR11U_GPIO_LED_3G 27 +#define TL_MR11U_GPIO_LED_WLAN 26 +#define TL_MR11U_GPIO_LED_LAN 17 + +#define TL_MR11U_GPIO_BTN_WPS 20 +#define TL_MR11U_GPIO_BTN_RESET 11 + +#define TL_MR11U_GPIO_USB_POWER 8 +#define TL_MR3040_GPIO_USB_POWER 18 + +#define TL_MR3040_V2_GPIO_BTN_SW1 19 +#define TL_MR3040_V2_GPIO_BTN_SW2 20 + +#define TL_MR11U_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR11U_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR11U_KEYS_POLL_INTERVAL) + +static const char *tl_mr11u_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr11u_flash_data = { + .part_probes = tl_mr11u_part_probes, +}; + +static struct gpio_led tl_mr11u_leds_gpio[] __initdata = { + { + .name = "tp-link:green:3g", + .gpio = TL_MR11U_GPIO_LED_3G, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan", + .gpio = TL_MR11U_GPIO_LED_WLAN, + .active_low = 1, + }, + { + .name = "tp-link:green:lan", + .gpio = TL_MR11U_GPIO_LED_LAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_mr11u_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR11U_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR11U_GPIO_BTN_WPS, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_mr3040_v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR11U_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "sw1", + .type = EV_SW, + .code = BTN_0, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3040_V2_GPIO_BTN_SW1, + .active_low = 0, + }, + { + .desc = "sw2", + .type = EV_SW, + .code = BTN_1, + .debounce_interval = TL_MR11U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3040_V2_GPIO_BTN_SW2, + .active_low = 0, + } +}; + +static void __init common_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* Disable hardware control LAN1 and LAN2 LEDs, enabling GPIO14 and GPIO15 */ + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_mr11u_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr11u_leds_gpio), + tl_mr11u_leds_gpio); + + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_mr11u_setup(void) +{ + common_setup(); + + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr11u_gpio_keys), + tl_mr11u_gpio_keys); + gpio_request_one(TL_MR11U_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR11U, "TL-MR11U", "TP-LINK TL-MR11U", + tl_mr11u_setup); + +static void __init tl_mr3040_setup(void) +{ + common_setup(); + + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL, + 1, tl_mr11u_gpio_keys); + gpio_request_one(TL_MR3040_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3040, "TL-MR3040", "TP-LINK TL-MR3040", + tl_mr3040_setup); + +static void __init tl_mr3040_v2_setup(void) +{ + common_setup(); + + ath79_register_gpio_keys_polled(-1, TL_MR11U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3040_v2_gpio_keys), + tl_mr3040_v2_gpio_keys); + gpio_request_one(TL_MR3040_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3040_V2, "TL-MR3040-v2", "TP-LINK TL-MR3040 v2", + tl_mr3040_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr13u.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr13u.c new file mode 100644 index 0000000..84b6937 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr13u.c @@ -0,0 +1,107 @@ +/* + * TP-LINK TL-MR13U board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_MR13U_GPIO_LED_SYSTEM 27 + +#define TL_MR13U_GPIO_BTN_RESET 11 +#define TL_MR13U_GPIO_BTN_SW1 6 +#define TL_MR13U_GPIO_BTN_SW2 7 + +#define TL_MR13U_GPIO_USB_POWER 18 + +#define TL_MR13U_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR13U_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR13U_KEYS_POLL_INTERVAL) + +static const char *tl_mr13u_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr13u_flash_data = { + .part_probes = tl_mr13u_part_probes, +}; + +static struct gpio_led tl_mr13u_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:system", + .gpio = TL_MR13U_GPIO_LED_SYSTEM, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_mr13u_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR13U_GPIO_BTN_RESET, + .active_low = 0, + }, + { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR13U_GPIO_BTN_SW1, + .active_low = 0, + }, + { + .desc = "sw2", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_MR13U_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR13U_GPIO_BTN_SW2, + .active_low = 0, + }, +}; + +static void __init tl_mr13u_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_mr13u_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr13u_leds_gpio), + tl_mr13u_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_MR13U_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr13u_gpio_keys), + tl_mr13u_gpio_keys); + + gpio_request_one(TL_MR13U_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR13U, "TL-MR13U", "TP-LINK TL-MR13U v1", + tl_mr13u_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c new file mode 100644 index 0000000..0a9dfbc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3020.c @@ -0,0 +1,126 @@ +/* + * TP-LINK TL-MR3020 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_MR3020_GPIO_LED_3G 27 +#define TL_MR3020_GPIO_LED_WLAN 0 +#define TL_MR3020_GPIO_LED_LAN 17 +#define TL_MR3020_GPIO_LED_WPS 26 + +#define TL_MR3020_GPIO_BTN_WPS 11 +#define TL_MR3020_GPIO_BTN_SW1 18 +#define TL_MR3020_GPIO_BTN_SW2 20 + +#define TL_MR3020_GPIO_USB_POWER 8 + +#define TL_MR3020_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR3020_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3020_KEYS_POLL_INTERVAL) + +static const char *tl_mr3020_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr3020_flash_data = { + .part_probes = tl_mr3020_part_probes, +}; + +static struct gpio_led tl_mr3020_leds_gpio[] __initdata = { + { + .name = "tp-link:green:3g", + .gpio = TL_MR3020_GPIO_LED_3G, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan", + .gpio = TL_MR3020_GPIO_LED_WLAN, + .active_low = 0, + }, + { + .name = "tp-link:green:lan", + .gpio = TL_MR3020_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "tp-link:green:wps", + .gpio = TL_MR3020_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_mr3020_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_WPS, + .active_low = 0, + }, + { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_SW1, + .active_low = 0, + }, + { + .desc = "sw2", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3020_GPIO_BTN_SW2, + .active_low = 0, + } +}; + +static void __init tl_mr3020_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_mr3020_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3020_leds_gpio), + tl_mr3020_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_MR3020_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3020_gpio_keys), + tl_mr3020_gpio_keys); + + gpio_request_one(TL_MR3020_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3020, "TL-MR3020", "TP-LINK TL-MR3020", + tl_mr3020_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c new file mode 100644 index 0000000..5924ac5 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-mr3x20.c @@ -0,0 +1,147 @@ +/* + * TP-LINK TL-MR3220/3420 board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TL_MR3X20_GPIO_LED_QSS 0 +#define TL_MR3X20_GPIO_LED_SYSTEM 1 +#define TL_MR3X20_GPIO_LED_3G 8 + +#define TL_MR3X20_GPIO_BTN_RESET 11 +#define TL_MR3X20_GPIO_BTN_QSS 12 + +#define TL_MR3X20_GPIO_USB_POWER 6 + +#define TL_MR3X20_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_MR3X20_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3X20_KEYS_POLL_INTERVAL) + +static const char *tl_mr3x20_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_mr3x20_flash_data = { + .part_probes = tl_mr3x20_part_probes, +}; + +static struct gpio_led tl_mr3x20_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_MR3X20_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_MR3X20_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:3g", + .gpio = TL_MR3X20_GPIO_LED_3G, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_mr3x20_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3X20_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3X20_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_ap99_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_mr3x20_flash_data); + + ath79_register_gpio_keys_polled(-1, TL_MR3X20_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3x20_gpio_keys), + tl_mr3x20_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + /* WAN port */ + ath79_register_eth(0); + + ap91_pci_init(ee, mac); +} + +static void __init tl_mr3x20_usb_setup(void) +{ + /* enable power for the USB port */ + gpio_request_one(TL_MR3X20_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); +} + +static void __init tl_mr3220_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio), + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 1); + tl_mr3x20_usb_setup(); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3220, "TL-MR3220", "TP-LINK TL-MR3220", + tl_mr3220_setup); + +static void __init tl_mr3420_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio), + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 0); + tl_mr3x20_usb_setup(); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3420, "TL-MR3420", "TP-LINK TL-MR3420", + tl_mr3420_setup); + +static void __init tl_wr841n_v7_setup(void) +{ + tl_ap99_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio) - 1, + tl_mr3x20_leds_gpio); + ap9x_pci_setup_wmac_led_pin(0, 0); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V7, "TL-WR841N-v7", + "TP-LINK TL-WR841N/ND v7", tl_wr841n_v7_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa701nd-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa701nd-v2.c new file mode 100644 index 0000000..aab92b3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa701nd-v2.c @@ -0,0 +1,116 @@ +/* + * TP-LINK TL-WA701ND v2 board support + * + * Copyright (C) 2015 Luigi Tarenga + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WA701NDV2_GPIO_LED_WLAN 0 +#define TL_WA701NDV2_GPIO_LED_QSS 1 +#define TL_WA701NDV2_GPIO_LED_LAN 17 +#define TL_WA701NDV2_GPIO_LED_SYSTEM 27 + +#define TL_WA701NDV2_GPIO_BTN_RESET 11 +#define TL_WA701NDV2_GPIO_BTN_QSS 26 + +#define TL_WA701NDV2_GPIO_USB_POWER 8 + +#define TL_WA701NDV2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA701NDV2_KEYS_POLL_INTERVAL) + +static const char *tl_wa701ndv2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa701ndv2_flash_data = { + .part_probes = tl_wa701ndv2_part_probes, +}; + +static struct gpio_led tl_wa701ndv2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:wlan", + .gpio = TL_WA701NDV2_GPIO_LED_WLAN, + .active_low = 0, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WA701NDV2_GPIO_LED_QSS, + .active_low = 0, + }, { + .name = "tp-link:green:lan", + .gpio = TL_WA701NDV2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA701NDV2_GPIO_LED_SYSTEM, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wa701ndv2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA701NDV2_GPIO_BTN_RESET, + .active_low = 0, + } , { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WA701NDV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA701NDV2_GPIO_BTN_QSS, + .active_low = 0, + } + +}; + +static void __init tl_wa701ndv2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa701ndv2_leds_gpio), + tl_wa701ndv2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WA701NDV2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa701ndv2_gpio_keys), + tl_wa701ndv2_gpio_keys); + + gpio_request_one(TL_WA701NDV2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_m25p80(&tl_wa701ndv2_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + /* ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); */ + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA701ND_V2, "TL-WA701ND-v2", + "TP-LINK TL-WA701ND v2", tl_wa701ndv2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa7210n-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa7210n-v2.c new file mode 100644 index 0000000..276353a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa7210n-v2.c @@ -0,0 +1,125 @@ +/* + * TP-LINK TL-WA7210N v2.1 board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2014 Nicolas Braud-Santoni + * Copyright (C) 2014 Alexander List + * Copyright (C) 2015 Hendrik Frenzel + * + * rebased on TL-WA7510Nv1 support, + * Copyright (C) 2012 Stefan Helmert + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include "dev-dsa.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#include "common.h" + +#define TL_WA7210N_V2_GPIO_BTN_RESET 11 +#define TL_WA7210N_V2_KEYS_POLL_INT 20 +#define TL_WA7210N_V2_KEYS_DEBOUNCE_INT (3 * TL_WA7210N_V2_KEYS_POLL_INT) + +#define TL_WA7210N_V2_GPIO_LED_LAN 17 +#define TL_WA7210N_V2_GPIO_LED_SIG1 0 +#define TL_WA7210N_V2_GPIO_LED_SIG2 1 +#define TL_WA7210N_V2_GPIO_LED_SIG3 27 +#define TL_WA7210N_V2_GPIO_LED_SIG4 26 + +#define TL_WA7210N_V2_GPIO_LNA_EN 28 + +static const char *tl_wa7210n_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct gpio_keys_button tl_wa7210n_v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA7210N_V2_KEYS_DEBOUNCE_INT, + .gpio = TL_WA7210N_V2_GPIO_BTN_RESET, + .active_low = 0, + }, +}; + +static struct gpio_led tl_wa7210n_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA7210N_V2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:signal1", + .gpio = TL_WA7210N_V2_GPIO_LED_SIG1, + .active_low = 0, + }, { + .name = "tp-link:green:signal2", + .gpio = TL_WA7210N_V2_GPIO_LED_SIG2, + .active_low = 0, + }, { + .name = "tp-link:green:signal3", + .gpio = TL_WA7210N_V2_GPIO_LED_SIG3, + .active_low = 1, + }, { + .name = "tp-link:green:signal4", + .gpio = TL_WA7210N_V2_GPIO_LED_SIG4, + .active_low = 1, + }, +}; + +static struct flash_platform_data tl_wa7210n_v2_flash_data = { + .part_probes = tl_wa7210n_v2_part_probes, +}; + +static void __init tl_wa7210n_v2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_gpio_keys_polled(-1, TL_WA7210N_V2_KEYS_POLL_INT, + ARRAY_SIZE(tl_wa7210n_v2_gpio_keys), + tl_wa7210n_v2_gpio_keys); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa7210n_v2_leds_gpio), + tl_wa7210n_v2_leds_gpio); + + ath79_gpio_function_enable(TL_WA7210N_V2_GPIO_LNA_EN); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_mdio(0, 0x0); + + ath79_register_wmac(ee, mac); + + ath79_register_m25p80(&tl_wa7210n_v2_flash_data); + + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA7210N_V2, "TL-WA7210N-v2", "TP-LINK TL-WA7210N v2", + tl_wa7210n_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa830re-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa830re-v2.c new file mode 100644 index 0000000..1c74fed --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa830re-v2.c @@ -0,0 +1,132 @@ +/* + * TP-LINK TL-WA830RE v2 board support + * + * Copyright (C) 2014 Fredrik Jonson + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WA830REV2_GPIO_LED_WLAN 13 +#define TL_WA830REV2_GPIO_LED_QSS 15 +#define TL_WA830REV2_GPIO_LED_LAN 18 +#define TL_WA830REV2_GPIO_LED_SYSTEM 14 + +#define TL_WA830REV2_GPIO_BTN_RESET 17 +#define TL_WA830REV2_GPIO_SW_RFKILL 16 /* WPS for MR3420 v2 */ + +#define TL_WA830REV2_GPIO_USB_POWER 4 + +#define TL_WA830REV2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA830REV2_KEYS_POLL_INTERVAL) + +static const char *tl_wa830re_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa830re_v2_flash_data = { + .part_probes = tl_wa830re_v2_part_probes, +}; + +static struct gpio_led tl_wa830re_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:qss", + .gpio = TL_WA830REV2_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA830REV2_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:lan", + .gpio = TL_WA830REV2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WA830REV2_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wa830re_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA830REV2_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = TL_WA830REV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA830REV2_GPIO_SW_RFKILL, + .active_low = 0, + } +}; + +static void __init tl_ap123_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + /* config gpio4 as normal gpio function */ + ath79_gpio_output_select(TL_WA830REV2_GPIO_USB_POWER, + AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&tl_wa830re_v2_flash_data); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_wa830re_v2_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa830re_v2_leds_gpio) - 1, + tl_wa830re_v2_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WA830REV2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa830re_v2_gpio_keys), + tl_wa830re_v2_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA830RE_V2, "TL-WA830RE-v2", "TP-LINK TL-WA830RE v2", + tl_wa830re_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c new file mode 100644 index 0000000..b4fb2a9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd-v2.c @@ -0,0 +1,104 @@ +/* + * TP-LINK TL-WA901N/ND v2 board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Pieter Hollants + * Copyright (C) 2011 Jonathan Bennett + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WA901ND_V2_GPIO_LED_QSS 4 +#define TL_WA901ND_V2_GPIO_LED_SYSTEM 2 +#define TL_WA901ND_V2_GPIO_LED_WLAN 9 + +#define TL_WA901ND_V2_GPIO_BTN_RESET 3 +#define TL_WA901ND_V2_GPIO_BTN_QSS 7 + +#define TL_WA901ND_V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL \ + (3 * TL_WA901ND_V2_KEYS_POLL_INTERVAL) + +static const char *tl_wa901nd_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa901nd_v2_flash_data = { + .part_probes = tl_wa901nd_v2_part_probes, +}; + +static struct gpio_led tl_wa901nd_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WA901ND_V2_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WA901ND_V2_GPIO_LED_QSS, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WA901ND_V2_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wa901nd_v2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_V2_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_V2_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_wa901nd_v2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x00001000; + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC | + AR71XX_RESET_GE0_PHY; + ath79_register_eth(0); + + ath79_register_m25p80(&tl_wa901nd_v2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_v2_leds_gpio), + tl_wa901nd_v2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WA901ND_V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa901nd_v2_gpio_keys), + tl_wa901nd_v2_gpio_keys); + + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA901ND_V2, "TL-WA901ND-v2", + "TP-LINK TL-WA901ND v2", tl_wa901nd_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c new file mode 100644 index 0000000..957b92c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wa901nd.c @@ -0,0 +1,127 @@ +/* + * TP-LINK TL-WA901N/ND v1, TL-WA7510N v1 board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Pieter Hollants + * Copyright (C) 2012 Stefan Helmert + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" + +#define TL_WA901ND_GPIO_LED_QSS 0 +#define TL_WA901ND_GPIO_LED_SYSTEM 1 +#define TL_WA901ND_GPIO_LED_LAN 13 + +#define TL_WA901ND_GPIO_BTN_RESET 11 +#define TL_WA901ND_GPIO_BTN_QSS 12 + +#define TL_WA901ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WA901ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA901ND_KEYS_POLL_INTERVAL) + +static const char *tl_wa901nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wa901nd_flash_data = { + .part_probes = tl_wa901nd_part_probes, +}; + +static struct gpio_led tl_wa901nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA901ND_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA901ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WA901ND_GPIO_LED_QSS, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wa901nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA901ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init common_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + + /* + * ath79_eth0 would be the WAN port, but is not connected. + * ath79_eth1 connects to the internal switch chip, however + * we have a single LAN port only. + */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + + ath79_register_m25p80(&tl_wa901nd_flash_data); +} + +static void __init tl_wa901nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_leds_gpio), + tl_wa901nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WA901ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa901nd_gpio_keys), + tl_wa901nd_gpio_keys); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA901ND, "TL-WA901ND", "TP-LINK TL-WA901ND", + tl_wa901nd_setup); + +static void __init tl_wa7510n_v1_setup(void) +{ + common_setup(); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA7510N_V1, "TL-WA7510N", "TP-LINK TL-WA7510N v1", + tl_wa7510n_v1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wax50re.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wax50re.c new file mode 100644 index 0000000..965b1cd --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wax50re.c @@ -0,0 +1,313 @@ +/* + * TP-LINK TL-WA750RE v1/TL-WA801ND v2/TL-WA850RE v1/TL-WA901ND v3 + * board support + * + * Copyright (C) 2013 Martijn Zilverschoon + * Copyright (C) 2013 Jiri Pirko + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WAX50RE_GPIO_LED_LAN 20 +#define TL_WAX50RE_GPIO_LED_WLAN 13 +#define TL_WAX50RE_GPIO_LED_RE 15 +#define TL_WAX50RE_GPIO_LED_SIGNAL1 0 +#define TL_WAX50RE_GPIO_LED_SIGNAL2 1 +#define TL_WAX50RE_GPIO_LED_SIGNAL3 2 +#define TL_WAX50RE_GPIO_LED_SIGNAL4 3 +#define TL_WAX50RE_GPIO_LED_SIGNAL5 4 + +#define TL_WA860RE_GPIO_LED_WLAN_ORANGE 0 +#define TL_WA860RE_GPIO_LED_WLAN_GREEN 2 +#define TL_WA860RE_GPIO_LED_POWER_ORANGE 12 +#define TL_WA860RE_GPIO_LED_POWER_GREEN 14 +#define TL_WA860RE_GPIO_LED_LAN 20 + +#define TL_WA801ND_V2_GPIO_LED_LAN 18 +#define TL_WA801ND_V2_GPIO_LED_SYSTEM 14 + +#define TL_WAX50RE_GPIO_BTN_RESET 17 +#define TL_WAX50RE_GPIO_BTN_WPS 16 + +#define TL_WA860RE_GPIO_BTN_RESET 17 +#define TL_WA860RE_GPIO_BTN_WPS 16 +#define TL_WA860RE_GPIO_BTN_ONOFF 11 + +#define TL_WAX50RE_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL (3 * TL_WAX50RE_KEYS_POLL_INTERVAL) + +static const char *tl_wax50re_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wax50re_flash_data = { + .part_probes = tl_wax50re_part_probes, +}; + +static struct gpio_led tl_wa750re_leds_gpio[] __initdata = { + { + .name = "tp-link:orange:lan", + .gpio = TL_WAX50RE_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:orange:wlan", + .gpio = TL_WAX50RE_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "tp-link:orange:re", + .gpio = TL_WAX50RE_GPIO_LED_RE, + .active_low = 1, + }, { + .name = "tp-link:orange:signal1", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL1, + .active_low = 1, + }, { + .name = "tp-link:orange:signal2", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL2, + .active_low = 1, + }, { + .name = "tp-link:orange:signal3", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL3, + .active_low = 1, + }, { + .name = "tp-link:orange:signal4", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL4, + .active_low = 1, + }, { + .name = "tp-link:orange:signal5", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL5, + .active_low = 1, + }, +}; + +static struct gpio_led tl_wa850re_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:lan", + .gpio = TL_WAX50RE_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:blue:wlan", + .gpio = TL_WAX50RE_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "tp-link:blue:re", + .gpio = TL_WAX50RE_GPIO_LED_RE, + .active_low = 1, + }, { + .name = "tp-link:blue:signal1", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL1, + .active_low = 1, + }, { + .name = "tp-link:blue:signal2", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL2, + .active_low = 1, + }, { + .name = "tp-link:blue:signal3", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL3, + .active_low = 1, + }, { + .name = "tp-link:blue:signal4", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL4, + .active_low = 1, + }, { + .name = "tp-link:blue:signal5", + .gpio = TL_WAX50RE_GPIO_LED_SIGNAL5, + .active_low = 1, + }, +}; + +static struct gpio_led tl_wa860re_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA860RE_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:power", + .gpio = TL_WA860RE_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "tp-link:orange:power", + .gpio = TL_WA860RE_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WA860RE_GPIO_LED_WLAN_GREEN, + .active_low = 1, + }, { + .name = "tp-link:orange:wlan", + .gpio = TL_WA860RE_GPIO_LED_WLAN_ORANGE, + .active_low = 1, + }, +}; + + +static struct gpio_keys_button tl_wax50re_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WAX50RE_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WAX50RE_GPIO_BTN_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wa860re_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA860RE_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA860RE_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "ONOFF", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_WAX50RE_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WA860RE_GPIO_BTN_ONOFF, + .active_low = 1, + }, +}; + +static struct gpio_led tl_wa801nd_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan", + .gpio = TL_WA801ND_V2_GPIO_LED_LAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WAX50RE_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WAX50RE_GPIO_LED_RE, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WA801ND_V2_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static void __init tl_ap123_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wax50re_flash_data); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_wa750re_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa750re_leds_gpio), + tl_wa750re_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wax50re_gpio_keys), + tl_wax50re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA750RE, "TL-WA750RE", "TP-LINK TL-WA750RE", + tl_wa750re_setup); + +static void __init tl_wa801nd_v2_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa801nd_v2_leds_gpio), + tl_wa801nd_v2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wax50re_gpio_keys), + tl_wax50re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA801ND_V2, "TL-WA801ND-v2", "TP-LINK TL-WA801ND v2", + tl_wa801nd_v2_setup); + +static void __init tl_wa850re_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa850re_leds_gpio), + tl_wa850re_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wax50re_gpio_keys), + tl_wax50re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA850RE, "TL-WA850RE", "TP-LINK TL-WA850RE", + tl_wa850re_setup); + +static void __init tl_wa860re_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa860re_leds_gpio), + tl_wa860re_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wa860re_gpio_keys), + tl_wa860re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA860RE, "TL-WA860RE", "TP-LINK TL-WA860RE", + tl_wa860re_setup); + +static void __init tl_wa901nd_v3_setup(void) +{ + tl_ap123_setup(); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa801nd_v2_leds_gpio), + tl_wa801nd_v2_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WAX50RE_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wax50re_gpio_keys) - 1, + tl_wax50re_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WA901ND_V3, "TL-WA901ND-v3", "TP-LINK TL-WA901ND v3", + tl_wa901nd_v3_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3320-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3320-v2.c new file mode 100644 index 0000000..3e452f2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3320-v2.c @@ -0,0 +1,146 @@ +/* + * TP-LINK TL-WDR3320 v2 board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2015 Weijie Gao + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WDR3320_GPIO_LED_WLAN5G 12 +#define WDR3320_GPIO_LED_SYSTEM 14 +#define WDR3320_GPIO_LED_QSS 15 +#define WDR3320_GPIO_LED_WAN 4 +#define WDR3320_GPIO_LED_LAN1 18 +#define WDR3320_GPIO_LED_LAN2 20 +#define WDR3320_GPIO_LED_LAN3 21 +#define WDR3320_GPIO_LED_LAN4 22 + +#define WDR3320_GPIO_BTN_RESET 16 + +#define WDR3320_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WDR3320_KEYS_DEBOUNCE_INTERVAL (3 * WDR3320_KEYS_POLL_INTERVAL) + +#define WDR3320_WMAC_CALDATA_OFFSET 0x1000 +#define WDR3320_PCIE_CALDATA_OFFSET 0x5000 + +static const char *wdr3320_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wdr3320_flash_data = { + .part_probes = wdr3320_part_probes, +}; + +static struct gpio_led wdr3320_leds_gpio[] __initdata = { + { + .name = "tp-link:green:qss", + .gpio = WDR3320_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:green:system", + .gpio = WDR3320_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan5g", + .gpio = WDR3320_GPIO_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wdr3320_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WDR3320_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR3320_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init wdr3320_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&wdr3320_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr3320_leds_gpio), + wdr3320_leds_gpio); + ath79_register_gpio_keys_polled(-1, WDR3320_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wdr3320_gpio_keys), + wdr3320_gpio_keys); + + ath79_init_mac(tmpmac, mac, 0); + ath79_register_wmac(art + WDR3320_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, -1); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + WDR3320_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + ath79_register_usb(); + + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN1, + AR934X_GPIO_OUT_LED_LINK0); + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN2, + AR934X_GPIO_OUT_LED_LINK1); + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN3, + AR934X_GPIO_OUT_LED_LINK2); + ath79_gpio_output_select(WDR3320_GPIO_LED_LAN4, + AR934X_GPIO_OUT_LED_LINK3); + ath79_gpio_output_select(WDR3320_GPIO_LED_WAN, + AR934X_GPIO_OUT_LED_LINK4); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR3320_V2, "TL-WDR3320-v2", + "TP-LINK TL-WDR3320 v2", + wdr3320_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3500.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3500.c new file mode 100644 index 0000000..452c20b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr3500.c @@ -0,0 +1,169 @@ +/* + * TP-LINK TL-WDR3500 board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2013 Gui Iribarren + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WDR3500_GPIO_LED_USB 11 +#define WDR3500_GPIO_LED_WLAN2G 13 +#define WDR3500_GPIO_LED_SYSTEM 14 +#define WDR3500_GPIO_LED_QSS 15 +#define WDR3500_GPIO_LED_WAN 18 +#define WDR3500_GPIO_LED_LAN1 19 +#define WDR3500_GPIO_LED_LAN2 20 +#define WDR3500_GPIO_LED_LAN3 21 +#define WDR3500_GPIO_LED_LAN4 22 + +#define WDR3500_GPIO_BTN_WPS 16 +#define WDR3500_GPIO_BTN_RFKILL 17 + +#define WDR3500_GPIO_USB_POWER 12 + +#define WDR3500_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WDR3500_KEYS_DEBOUNCE_INTERVAL (3 * WDR3500_KEYS_POLL_INTERVAL) + +#define WDR3500_MAC0_OFFSET 0 +#define WDR3500_MAC1_OFFSET 6 +#define WDR3500_WMAC_CALDATA_OFFSET 0x1000 +#define WDR3500_PCIE_CALDATA_OFFSET 0x5000 + +static const char *wdr3500_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wdr3500_flash_data = { + .part_probes = wdr3500_part_probes, +}; + +static struct gpio_led wdr3500_leds_gpio[] __initdata = { + { + .name = "tp-link:green:qss", + .gpio = WDR3500_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:green:system", + .gpio = WDR3500_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:usb", + .gpio = WDR3500_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan2g", + .gpio = WDR3500_GPIO_LED_WLAN2G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wdr3500_gpio_keys[] __initdata = { + { + .desc = "QSS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WDR3500_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR3500_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = WDR3500_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR3500_GPIO_BTN_RFKILL, + }, +}; + + +static void __init wdr3500_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&wdr3500_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr3500_leds_gpio), + wdr3500_leds_gpio); + ath79_register_gpio_keys_polled(-1, WDR3500_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wdr3500_gpio_keys), + wdr3500_gpio_keys); + + ath79_init_mac(tmpmac, mac, 0); + ath79_register_wmac(art + WDR3500_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, 1); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + WDR3500_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + + /* LAN */ + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + + ath79_register_eth(1); + + /* WAN */ + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2); + + /* GMAC0 is connected to the PHY4 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + + ath79_register_eth(0); + + gpio_request_one(WDR3500_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN1, + AR934X_GPIO_OUT_LED_LINK3); + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN2, + AR934X_GPIO_OUT_LED_LINK2); + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN3, + AR934X_GPIO_OUT_LED_LINK1); + ath79_gpio_output_select(WDR3500_GPIO_LED_LAN4, + AR934X_GPIO_OUT_LED_LINK0); + ath79_gpio_output_select(WDR3500_GPIO_LED_WAN, + AR934X_GPIO_OUT_LED_LINK4); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR3500, "TL-WDR3500", + "TP-LINK TL-WDR3500", + wdr3500_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c new file mode 100644 index 0000000..3afc714 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr4300.c @@ -0,0 +1,206 @@ +/* + * TP-LINK TL-WDR4300 board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WDR4300_GPIO_LED_USB1 11 +#define WDR4300_GPIO_LED_USB2 12 +#define WDR4300_GPIO_LED_WLAN2G 13 +#define WDR4300_GPIO_LED_SYSTEM 14 +#define WDR4300_GPIO_LED_QSS 15 + +#define WDR4300_GPIO_BTN_WPS 16 +#define WDR4300_GPIO_BTN_RFKILL 17 + +#define WDR4300_GPIO_EXTERNAL_LNA0 18 +#define WDR4300_GPIO_EXTERNAL_LNA1 19 + +#define WDR4300_GPIO_USB1_POWER 22 +#define WDR4300_GPIO_USB2_POWER 21 + +#define WDR4300_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WDR4300_KEYS_DEBOUNCE_INTERVAL (3 * WDR4300_KEYS_POLL_INTERVAL) + +#define WDR4300_MAC0_OFFSET 0 +#define WDR4300_MAC1_OFFSET 6 +#define WDR4300_WMAC_CALDATA_OFFSET 0x1000 +#define WDR4300_PCIE_CALDATA_OFFSET 0x5000 + +static const char *wdr4300_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wdr4300_flash_data = { + .part_probes = wdr4300_part_probes, +}; + +static struct gpio_led wdr4300_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:qss", + .gpio = WDR4300_GPIO_LED_QSS, + .active_low = 1, + }, + { + .name = "tp-link:blue:system", + .gpio = WDR4300_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:usb1", + .gpio = WDR4300_GPIO_LED_USB1, + .active_low = 1, + }, + { + .name = "tp-link:green:usb2", + .gpio = WDR4300_GPIO_LED_USB2, + .active_low = 1, + }, + { + .name = "tp-link:blue:wlan2g", + .gpio = WDR4300_GPIO_LED_WLAN2G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wdr4300_gpio_keys[] __initdata = { + { + .desc = "QSS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR4300_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = WDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WDR4300_GPIO_BTN_RFKILL, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info wdr4300_leds_ar8327[] __initconst = { + AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"), + AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"), + AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"), + AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"), + AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"), +}; + +static struct ar8327_pad_cfg wdr4300_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wdr4300_ar8327_led_cfg = { + .led_ctrl0 = 0xc737c737, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static struct ar8327_platform_data wdr4300_ar8327_data = { + .pad0_cfg = &wdr4300_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wdr4300_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(wdr4300_leds_ar8327), + .leds = wdr4300_leds_ar8327, +}; + +static struct mdio_board_info wdr4300_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wdr4300_ar8327_data, + }, +}; + +static void __init wdr4300_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&wdr4300_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio), + wdr4300_leds_gpio); + ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wdr4300_gpio_keys), + wdr4300_gpio_keys); + + ath79_wmac_set_ext_lna_gpio(0, WDR4300_GPIO_EXTERNAL_LNA0); + ath79_wmac_set_ext_lna_gpio(1, WDR4300_GPIO_EXTERNAL_LNA1); + + ath79_init_mac(tmpmac, mac, -1); + ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_init_mac(tmpmac, mac, 0); + ap9x_pci_setup_wmac_led_pin(0, 0); + ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(wdr4300_mdio0_info, + ARRAY_SIZE(wdr4300_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + gpio_request_one(WDR4300_GPIO_USB1_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB1 power"); + gpio_request_one(WDR4300_GPIO_USB2_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB2 power"); + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR4300, "TL-WDR4300", + "TP-LINK TL-WDR3600/4300/4310", + wdr4300_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr6500-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr6500-v2.c new file mode 100644 index 0000000..c2e75c2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wdr6500-v2.c @@ -0,0 +1,141 @@ +/* + * TP-LINK TL-WDR6500 v2 + * + * Copyright (C) 2015 Weijie Gao + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" +#include "pci.h" + +#define TL_WDR6500_V2_GPIO_LED_SYS 21 +#define TL_WDR6500_V2_GPIO_LED_WAN 18 +#define TL_WDR6500_V2_GPIO_LED_LAN1 17 +#define TL_WDR6500_V2_GPIO_LED_LAN2 16 +#define TL_WDR6500_V2_GPIO_LED_LAN3 15 +#define TL_WDR6500_V2_GPIO_LED_LAN4 14 + +#define TL_WDR6500_V2_GPIO_BTN_RESET 1 + +#define TL_WDR6500_V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WDR6500_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WDR6500_V2_KEYS_POLL_INTERVAL) + +#define TL_WDR6500_V2_WMAC_CALDATA_OFFSET 0x1000 +#define TL_WDR6500_V2_PCIE_CALDATA_OFFSET 0x5000 + +static const char *tl_wdr6500_v2_part_probes[] = { + "tp-link-64k", + NULL, +}; + +static struct flash_platform_data tl_wdr6500_v2_flash_data = { + .part_probes = tl_wdr6500_v2_part_probes, +}; + +static struct gpio_led tl_wdr6500_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WDR6500_V2_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WDR6500_V2_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WDR6500_V2_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WDR6500_V2_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WDR6500_V2_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:white:system", + .gpio = TL_WDR6500_V2_GPIO_LED_SYS, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_wdr6500_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WDR6500_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WDR6500_V2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + + +static void __init tl_ap151_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f00fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff0000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&tl_wdr6500_v2_flash_data); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_mdio(0, 0x0); + + /* WAN */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_register_eth(0); + + /* LAN */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_data.speed = SPEED_1000; + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + ath79_init_mac(tmpmac, mac, -1); + ath79_register_wmac(ee + TL_WDR6500_V2_WMAC_CALDATA_OFFSET, tmpmac); + + ath79_register_pci(); + + ath79_register_usb(); +} + +static void __init tl_wdr6500_v2_setup(void) +{ + tl_ap151_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wdr6500_v2_leds_gpio), + tl_wdr6500_v2_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WDR6500_V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wdr6500_v2_gpio_keys), + tl_wdr6500_v2_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WDR6500_V2, "TL-WDR6500-v2", "TP-LINK TL-WDR6500 v2", + tl_wdr6500_v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c new file mode 100644 index 0000000..fa8c474 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1041n-v2.c @@ -0,0 +1,138 @@ +/* + * TP-LINK TL-WR1041 v2 board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * Copyright (C) 2011-2012 Anan Huang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR1041NV2_GPIO_BTN_RESET 14 +#define TL_WR1041NV2_GPIO_LED_WPS 13 +#define TL_WR1041NV2_GPIO_LED_WLAN 11 + +#define TL_WR1041NV2_GPIO_LED_SYSTEM 12 + +#define TL_WR1041NV2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR1041NV2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1041NV2_KEYS_POLL_INTERVAL) + +#define TL_WR1041NV2_PCIE_CALDATA_OFFSET 0x5000 + +static const char *tl_wr1041nv2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr1041nv2_flash_data = { + .part_probes = tl_wr1041nv2_part_probes, +}; + +static struct gpio_led tl_wr1041nv2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR1041NV2_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wps", + .gpio = TL_WR1041NV2_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR1041NV2_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr1041nv2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR1041NV2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1041NV2_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data db120_ar8327_data = { + .pad0_cfg = &db120_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + } +}; + +static struct mdio_board_info db120_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &db120_ar8327_data, + }, +}; + +static void __init tl_wr1041nv2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr1041nv2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1041nv2_leds_gpio), + tl_wr1041nv2_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR1041NV2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr1041nv2_gpio_keys), + tl_wr1041nv2_gpio_keys); + ath79_register_wmac(ee, mac); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + + mdiobus_register_board_info(db120_mdio0_info, + ARRAY_SIZE(db120_mdio0_info)); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR1041N_V2, "TL-WR1041N-v2", + "TP-LINK TL-WR1041N v2", tl_wr1041nv2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c new file mode 100644 index 0000000..abdbde0 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c @@ -0,0 +1,215 @@ +/* + * TP-LINK TL-WR1043ND v2 board support + * + * Copyright (c) 2013 Gabor Juhos + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR1043_V2_GPIO_LED_WLAN 12 +#define TL_WR1043_V2_GPIO_LED_USB 15 +#define TL_WR1043_V2_GPIO_LED_WPS 18 +#define TL_WR1043_V2_GPIO_LED_SYSTEM 19 + +#define TL_WR1043_V2_GPIO_BTN_RESET 16 +#define TL_WR1043_V2_GPIO_BTN_RFKILL 17 + +#define TL_WR1043_V2_GPIO_USB_POWER 21 + +#define TL_WR1043_V2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043_V2_KEYS_POLL_INTERVAL) + +#define TL_WR1043_V2_WMAC_CALDATA_OFFSET 0x1000 + +static const char *wr1043nd_v2_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data wr1043nd_v2_flash_data = { + .part_probes = wr1043nd_v2_part_probes, +}; + +static struct gpio_led tl_wr1043_v2_leds_gpio[] __initdata = { + { + .name = "tp-link:green:wps", + .gpio = TL_WR1043_V2_GPIO_LED_WPS, + .active_low = 1, + }, + { + .name = "tp-link:green:system", + .gpio = TL_WR1043_V2_GPIO_LED_SYSTEM, + .active_low = 1, + }, + { + .name = "tp-link:green:wlan", + .gpio = TL_WR1043_V2_GPIO_LED_WLAN, + .active_low = 1, + }, + { + .name = "tp-link:green:usb", + .gpio = TL_WR1043_V2_GPIO_LED_USB, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr1043_v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043_V2_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043_V2_GPIO_BTN_RFKILL, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info tl_wr1043_leds_ar8327[] = { + AR8327_LED_INFO(PHY0_0, HW, "tp-link:green:lan4"), + AR8327_LED_INFO(PHY1_0, HW, "tp-link:green:lan3"), + AR8327_LED_INFO(PHY2_0, HW, "tp-link:green:lan2"), + AR8327_LED_INFO(PHY3_0, HW, "tp-link:green:lan1"), + AR8327_LED_INFO(PHY4_0, HW, "tp-link:green:wan"), +}; + +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ +static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ +static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wr1043nd_v2_ar8327_led_cfg = { + .led_ctrl0 = 0xcc35cc35, + .led_ctrl1 = 0xca35ca35, + .led_ctrl2 = 0xc935c935, + .led_ctrl3 = 0x03ffff00, + .open_drain = true, +}; + +static struct ar8327_platform_data wr1043nd_v2_ar8327_data = { + .pad0_cfg = &wr1043nd_v2_ar8327_pad0_cfg, + .pad6_cfg = &wr1043nd_v2_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wr1043nd_v2_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(tl_wr1043_leds_ar8327), + .leds = tl_wr1043_leds_ar8327, +}; + +static struct mdio_board_info wr1043nd_v2_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wr1043nd_v2_ar8327_data, + }, +}; + +static void __init tl_wr1043nd_v2_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(&wr1043nd_v2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio), + tl_wr1043_v2_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr1043_v2_gpio_keys), + tl_wr1043_v2_gpio_keys); + + ath79_register_wmac(art + TL_WR1043_V2_WMAC_CALDATA_OFFSET, mac); + + mdiobus_register_board_info(wr1043nd_v2_mdio0_info, + ARRAY_SIZE(wr1043nd_v2_mdio0_info)); + ath79_register_mdio(0, 0x0); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x56000000; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + ath79_register_usb(); + + gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR1043ND_V2, "TL-WR1043ND-v2", + "TP-LINK TL-WR1043ND v2", tl_wr1043nd_v2_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c new file mode 100644 index 0000000..61aeb52 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd.c @@ -0,0 +1,141 @@ +/* + * TP-LINK TL-WR1043N/ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR1043ND_GPIO_LED_USB 1 +#define TL_WR1043ND_GPIO_LED_SYSTEM 2 +#define TL_WR1043ND_GPIO_LED_QSS 5 +#define TL_WR1043ND_GPIO_LED_WLAN 9 + +#define TL_WR1043ND_GPIO_BTN_RESET 3 +#define TL_WR1043ND_GPIO_BTN_QSS 7 + +#define TL_WR1043ND_GPIO_RTL8366_SDA 18 +#define TL_WR1043ND_GPIO_RTL8366_SCK 19 + +#define TL_WR1043ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr1043nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr1043nd_flash_data = { + .part_probes = tl_wr1043nd_part_probes, +}; + +static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:usb", + .gpio = TL_WR1043ND_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR1043ND_GPIO_LED_QSS, + .active_low = 0, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR1043ND_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr1043nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR1043ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void tl_wr1043nd_rtl8366rb_hw_reset(bool active) +{ + if (active) + ath79_device_reset_set(AR71XX_RESET_GE0_PHY); + else + ath79_device_reset_clear(AR71XX_RESET_GE0_PHY); +} + +static struct rtl8366_platform_data tl_wr1043nd_rtl8366rb_data = { + .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, + .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, + .hw_reset = tl_wr1043nd_rtl8366rb_hw_reset, +}; + +static struct platform_device tl_wr1043nd_rtl8366rb_device = { + .name = RTL8366RB_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tl_wr1043nd_rtl8366rb_data, + } +}; + +static void __init tl_wr1043nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + tl_wr1043nd_rtl8366rb_hw_reset(true); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x1a000000; + + ath79_register_eth(0); + + ath79_register_usb(); + + ath79_register_m25p80(&tl_wr1043nd_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), + tl_wr1043nd_leds_gpio); + + platform_device_register(&tl_wr1043nd_rtl8366rb_device); + + ath79_register_gpio_keys_polled(-1, TL_WR1043ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr1043nd_gpio_keys), + tl_wr1043nd_gpio_keys); + + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", + tl_wr1043nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c new file mode 100644 index 0000000..8f6db5e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr2543n.c @@ -0,0 +1,156 @@ +/* + * TP-LINK TL-WR2543N/ND board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define TL_WR2543N_GPIO_LED_WPS 0 +#define TL_WR2543N_GPIO_LED_USB 8 + +/* The WLAN LEDs use GPIOs on the discrete AR9380 wmac */ +#define TL_WR2543N_GPIO_WMAC_LED_WLAN2G 0 +#define TL_WR2543N_GPIO_WMAC_LED_WLAN5G 1 + +#define TL_WR2543N_GPIO_BTN_RESET 11 +#define TL_WR2543N_GPIO_BTN_WPS 12 + +#define TL_WR2543N_GPIO_RTL8367_SDA 1 +#define TL_WR2543N_GPIO_RTL8367_SCK 6 + +#define TL_WR2543N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR2543N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR2543N_KEYS_POLL_INTERVAL) + +static const char *tl_wr2543n_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr2543n_flash_data = { + .part_probes = tl_wr2543n_part_probes, +}; + +static struct gpio_led tl_wr2543n_leds_gpio[] __initdata = { + { + .name = "tp-link:green:usb", + .gpio = TL_WR2543N_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "tp-link:green:wps", + .gpio = TL_WR2543N_GPIO_LED_WPS, + .active_low = 1, + } +}; + +static struct gpio_led tl_wr2543n_wmac_leds_gpio[] = { + { + .name = "tp-link:green:wlan5g", + .gpio = TL_WR2543N_GPIO_WMAC_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr2543n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR2543N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR2543N_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static struct rtl8367_extif_config tl_wr2543n_rtl8367_extif0_cfg = { + .mode = RTL8367_EXTIF_MODE_RGMII, + .txdelay = 1, + .rxdelay = 0, + .ability = { + .force_mode = 1, + .txpause = 1, + .rxpause = 1, + .link = 1, + .duplex = 1, + .speed = RTL8367_PORT_SPEED_1000, + }, +}; + +static struct rtl8367_platform_data tl_wr2543n_rtl8367_data = { + .gpio_sda = TL_WR2543N_GPIO_RTL8367_SDA, + .gpio_sck = TL_WR2543N_GPIO_RTL8367_SCK, + .extif0_cfg = &tl_wr2543n_rtl8367_extif0_cfg, +}; + +static struct platform_device tl_wr2543n_rtl8367_device = { + .name = RTL8367_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &tl_wr2543n_rtl8367_data, + } +}; + +static void __init tl_wr2543n_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr2543n_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr2543n_leds_gpio), + tl_wr2543n_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR2543N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr2543n_gpio_keys), + tl_wr2543n_gpio_keys); + ath79_register_usb(); + + /* + * The ath9k driver uses this pin for its default led device, which is + * named ath9k-phy0, and reflects activity on either the 2 GHz or 5 GHz + * bands. This pin is connected to the WR2543's 2GHz WLAN LED. + */ + ap9x_pci_setup_wmac_led_pin(0, TL_WR2543N_GPIO_WMAC_LED_WLAN2G); + + /* + * We also have the driver set up an led device for the WR2543's + * separate 5 GHz WLAN LED in case the user wants it. + */ + ap9x_pci_setup_wmac_leds(0, tl_wr2543n_wmac_leds_gpio, + ARRAY_SIZE(tl_wr2543n_wmac_leds_gpio)); + ap91_pci_init(eeprom, mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_eth0_data.mii_bus_dev = &tl_wr2543n_rtl8367_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_pll_data.pll_1000 = 0x1a000000; + + ath79_register_eth(0); + + platform_device_register(&tl_wr2543n_rtl8367_device); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR2543N, "TL-WR2543N", "TP-LINK TL-WR2543N/ND", + tl_wr2543n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c new file mode 100644 index 0000000..1d8d01c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr703n.c @@ -0,0 +1,118 @@ +/* + * TP-LINK TL-WR703N/TL-MR10U board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR703N_GPIO_LED_SYSTEM 27 +#define TL_WR703N_GPIO_BTN_RESET 11 + +#define TL_WR703N_GPIO_USB_POWER 8 + +#define TL_MR10U_GPIO_USB_POWER 18 + +#define TL_WR703N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR703N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR703N_KEYS_POLL_INTERVAL) + +static const char *tl_wr703n_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr703n_flash_data = { + .part_probes = tl_wr703n_part_probes, +}; + +static struct gpio_led tl_wr703n_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:system", + .gpio = TL_WR703N_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr703n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR703N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR703N_GPIO_BTN_RESET, + .active_low = 0, + } +}; + +static void __init common_setup(unsigned usb_power_gpio, bool sec_ethernet) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_wr703n_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr703n_leds_gpio), + tl_wr703n_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR703N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr703n_gpio_keys), + tl_wr703n_gpio_keys); + + gpio_request_one(usb_power_gpio, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + + if (sec_ethernet) + { + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + ath79_register_eth(1); + } + + ath79_register_wmac(ee, mac); +} + +static void __init tl_mr10u_setup(void) +{ + common_setup(TL_MR10U_GPIO_USB_POWER, false); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR10U, "TL-MR10U", "TP-LINK TL-MR10U", + tl_mr10u_setup); + +static void __init tl_wr703n_setup(void) +{ + common_setup(TL_WR703N_GPIO_USB_POWER, false); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR703N, "TL-WR703N", "TP-LINK TL-WR703N v1", + tl_wr703n_setup); + +static void __init tl_wr710n_setup(void) +{ + common_setup(TL_WR703N_GPIO_USB_POWER, true); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR710N, "TL-WR710N", "TP-LINK TL-WR710N v1", + tl_wr710n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr720n-v3.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr720n-v3.c new file mode 100644 index 0000000..2bb3b44 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr720n-v3.c @@ -0,0 +1,108 @@ +/* + * TP-LINK TL-WR720N board support + * + * Copyright (C) 2011 dongyuqi <729650915@qq.com> + * Copyright (C) 2011-2012 Gabor Juhos + * Copyright (C) 2013 yousong + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR720N_GPIO_LED_SYSTEM 27 +#define TL_WR720N_GPIO_BTN_RESET 11 +#define TL_WR720N_GPIO_BTN_SW1 18 +#define TL_WR720N_GPIO_BTN_SW2 20 + +#define TL_WR720N_GPIO_USB_POWER 8 + +#define TL_WR720N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR720N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR720N_KEYS_POLL_INTERVAL) + +static const char *tl_wr720n_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr720n_flash_data = { + .part_probes = tl_wr720n_part_probes, +}; + +static struct gpio_led tl_wr720n_leds_gpio[] __initdata = { + { + .name = "tp-link:blue:system", + .gpio = TL_WR720N_GPIO_LED_SYSTEM, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr720n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR720N_GPIO_BTN_RESET, + .active_low = 0, + }, { + .desc = "sw1", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR720N_GPIO_BTN_SW1, + .active_low = 0, + }, { + .desc = "sw2", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = TL_WR720N_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR720N_GPIO_BTN_SW2, + .active_low = 0, + } +}; + +static void __init tl_wr720n_v3_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* disable PHY_SWAP and PHY_ADDR_SWAP bits */ + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_m25p80(&tl_wr720n_flash_data); + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr720n_leds_gpio), + tl_wr720n_leds_gpio); + ath79_register_gpio_keys_polled(-1, TL_WR720N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr720n_gpio_keys), + tl_wr720n_gpio_keys); + + gpio_request_one(TL_WR720N_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR720N_V3, "TL-WR720N-v3", "TP-LINK TL-WR720N v3/v4", + tl_wr720n_v3_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c new file mode 100644 index 0000000..851b762 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd-v4.c @@ -0,0 +1,187 @@ +/* + * TP-LINK TL-WR741ND v4/TL-MR3220 v2 board support + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR741NDV4_GPIO_BTN_RESET 11 +#define TL_WR741NDV4_GPIO_BTN_WPS 26 + +#define TL_WR741NDV4_GPIO_LED_WLAN 0 +#define TL_WR741NDV4_GPIO_LED_QSS 1 +#define TL_WR741NDV4_GPIO_LED_WAN 13 +#define TL_WR741NDV4_GPIO_LED_LAN1 14 +#define TL_WR741NDV4_GPIO_LED_LAN2 15 +#define TL_WR741NDV4_GPIO_LED_LAN3 16 +#define TL_WR741NDV4_GPIO_LED_LAN4 17 +#define TL_WR741NDV4_GPIO_LED_SYSTEM 27 + +#define TL_MR3220V2_GPIO_BTN_WPS 11 +#define TL_MR3220V2_GPIO_BTN_WIFI 24 + +#define TL_MR3220V2_GPIO_LED_3G 26 +#define TL_MR3220V2_GPIO_USB_POWER 8 + +#define TL_WR741NDV4_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741NDV4_KEYS_POLL_INTERVAL) + +static const char *tl_wr741ndv4_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr741ndv4_flash_data = { + .part_probes = tl_wr741ndv4_part_probes, +}; + +static struct gpio_led tl_wr741ndv4_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR741NDV4_GPIO_LED_LAN1, + .active_low = 0, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR741NDV4_GPIO_LED_LAN2, + .active_low = 0, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR741NDV4_GPIO_LED_LAN3, + .active_low = 0, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR741NDV4_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR741NDV4_GPIO_LED_QSS, + .active_low = 0, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR741NDV4_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR741NDV4_GPIO_LED_WAN, + .active_low = 0, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR741NDV4_GPIO_LED_WLAN, + .active_low = 0, + }, { + /* the 3G LED is only present on the MR3220 v2 */ + .name = "tp-link:green:3g", + .gpio = TL_MR3220V2_GPIO_LED_3G, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tl_wr741ndv4_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741NDV4_GPIO_BTN_RESET, + .active_low = 0, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741NDV4_GPIO_BTN_WPS, + .active_low = 0, + } +}; + +static struct gpio_keys_button tl_mr3220v2_gpio_keys[] __initdata = { + { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3220V2_GPIO_BTN_WPS, + .active_low = 0, + }, { + .desc = "WIFI button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_MR3220V2_GPIO_BTN_WIFI, + .active_low = 0, + } +}; + +static void __init tl_ap121_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_setup_ar933x_phy4_switch(true, true); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(&tl_wr741ndv4_flash_data); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + ath79_register_eth(1); + ath79_register_eth(0); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_wr741ndv4_setup(void) +{ + tl_ap121_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741ndv4_leds_gpio) - 1, + tl_wr741ndv4_leds_gpio); + ath79_register_gpio_keys_polled(1, TL_WR741NDV4_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr741ndv4_gpio_keys), + tl_wr741ndv4_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR741ND_V4, "TL-WR741ND-v4", + "TP-LINK TL-WR741ND v4", tl_wr741ndv4_setup); + +static void __init tl_mr3220v2_setup(void) +{ + tl_ap121_setup(); + + gpio_request_one(TL_MR3220V2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741ndv4_leds_gpio), + tl_wr741ndv4_leds_gpio); + ath79_register_gpio_keys_polled(1, TL_WR741NDV4_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3220v2_gpio_keys), + tl_mr3220v2_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3220_V2, "TL-MR3220-v2", + "TP-LINK TL-MR3220 v2", tl_mr3220v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c new file mode 100644 index 0000000..5931654 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr741nd.c @@ -0,0 +1,130 @@ +/* + * TP-LINK TL-WR741ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define TL_WR741ND_GPIO_LED_QSS 0 +#define TL_WR741ND_GPIO_LED_SYSTEM 1 +#define TL_WR741ND_GPIO_LED_LAN1 13 +#define TL_WR741ND_GPIO_LED_LAN2 14 +#define TL_WR741ND_GPIO_LED_LAN3 15 +#define TL_WR741ND_GPIO_LED_LAN4 16 +#define TL_WR741ND_GPIO_LED_WAN 17 + +#define TL_WR741ND_GPIO_BTN_RESET 11 +#define TL_WR741ND_GPIO_BTN_QSS 12 + +#define TL_WR741ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR741ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr741nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr741nd_flash_data = { + .part_probes = tl_wr741nd_part_probes, +}; + +static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR741ND_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR741ND_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR741ND_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR741ND_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR741ND_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR741ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR741ND_GPIO_LED_WAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr741nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR741ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static void __init tl_wr741nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_m25p80(&tl_wr741nd_flash_data); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), + tl_wr741nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR741ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr741nd_gpio_keys), + tl_wr741nd_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + + /* WAN port */ + ath79_register_eth(0); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap91_pci_init(ee, mac); +} +MIPS_MACHINE(ATH79_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", + tl_wr741nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c new file mode 100644 index 0000000..73cfdd9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c @@ -0,0 +1,286 @@ +/* + * TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 board support + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR841NV8_GPIO_LED_WLAN 13 +#define TL_WR841NV8_GPIO_LED_QSS 15 +#define TL_WR841NV8_GPIO_LED_WAN 18 +#define TL_WR841NV8_GPIO_LED_LAN1 19 +#define TL_WR841NV8_GPIO_LED_LAN2 20 +#define TL_WR841NV8_GPIO_LED_LAN3 21 +#define TL_WR841NV8_GPIO_LED_LAN4 12 +#define TL_WR841NV8_GPIO_LED_SYSTEM 14 + +#define TL_WR841NV8_GPIO_BTN_RESET 17 +#define TL_WR841NV8_GPIO_SW_RFKILL 16 /* WPS for MR3420 v2 */ + +#define TL_MR3420V2_GPIO_LED_3G 11 +#define TL_MR3420V2_GPIO_USB_POWER 4 + +#define TL_WR941NDV5_GPIO_LED_WLAN 13 +#define TL_WR941NDV5_GPIO_LED_QSS 15 +#define TL_WR941NDV5_GPIO_LED_WAN 18 +#define TL_WR941NDV5_GPIO_LED_LAN1 19 +#define TL_WR941NDV5_GPIO_LED_LAN2 20 +#define TL_WR941NDV5_GPIO_LED_LAN3 2 +#define TL_WR941NDV5_GPIO_LED_LAN4 3 +#define TL_WR941NDV5_GPIO_LED_SYSTEM 14 + +#define TL_WR841NV8_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV8_KEYS_POLL_INTERVAL) + +static const char *tl_wr841n_v8_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr841n_v8_flash_data = { + .part_probes = tl_wr841n_v8_part_probes, +}; + +static struct gpio_led tl_wr841n_v8_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR841NV8_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR841NV8_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR841NV8_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR841NV8_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841NV8_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR841NV8_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR841NV8_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR841NV8_GPIO_LED_WLAN, + .active_low = 1, + }, { + /* the 3G LED is only present on the MR3420 v2 */ + .name = "tp-link:green:3g", + .gpio = TL_MR3420V2_GPIO_LED_3G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr841n_v8_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "RFKILL switch", + .type = EV_SW, + .code = KEY_RFKILL, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_SW_RFKILL, + .active_low = 0, + } +}; + +static struct gpio_keys_button tl_mr3420v2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WPS", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR841NV8_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV8_GPIO_SW_RFKILL, + .active_low = 0, + } +}; + +static struct gpio_led tl_wr941nd_v5_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR941NDV5_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR941NDV5_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR941NDV5_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR941NDV5_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR941NDV5_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:system", + .gpio = TL_WR941NDV5_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR941NDV5_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR941NDV5_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static void __init tl_ap123_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + /* config gpio4 as normal gpio function */ + ath79_gpio_output_select(TL_MR3420V2_GPIO_USB_POWER, + AR934X_GPIO_OUT_GPIO); + + ath79_register_m25p80(&tl_wr841n_v8_flash_data); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); + + ath79_register_mdio(1, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, mac); +} + +static void __init tl_wr841n_v8_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio) - 1, + tl_wr841n_v8_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v8_gpio_keys), + tl_wr841n_v8_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V8, "TL-WR841N-v8", "TP-LINK TL-WR841N/ND v8", + tl_wr841n_v8_setup); + + +static void __init tl_wr842n_v2_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio), + tl_wr841n_v8_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v8_gpio_keys), + tl_wr841n_v8_gpio_keys); + + gpio_request_one(TL_MR3420V2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR842N_V2, "TL-WR842N-v2", "TP-LINK TL-WR842N/ND v2", + tl_wr842n_v2_setup); + +static void __init tl_mr3420v2_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio), + tl_wr841n_v8_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_mr3420v2_gpio_keys), + tl_mr3420v2_gpio_keys); + + /* enable power for the USB port */ + gpio_request_one(TL_MR3420V2_GPIO_USB_POWER, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_TL_MR3420_V2, "TL-MR3420-v2", "TP-LINK TL-MR3420 v2", + tl_mr3420v2_setup); + + +static void __init tl_wr941nd_v5_setup(void) +{ + tl_ap123_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_v5_leds_gpio), + tl_wr941nd_v5_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v8_gpio_keys), + tl_wr841n_v8_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR941ND_V5, "TL-WR941ND-v5", "TP-LINK TL-WR941N/ND v5", + tl_wr941nd_v5_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c new file mode 100644 index 0000000..3e5c2a2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c @@ -0,0 +1,144 @@ +/* + * TP-LINK TL-WR841N/ND v9 + * + * Copyright (C) 2014 Matthias Schiffer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR841NV9_GPIO_LED_WLAN 13 +#define TL_WR841NV9_GPIO_LED_QSS 3 +#define TL_WR841NV9_GPIO_LED_WAN 4 +#define TL_WR841NV9_GPIO_LED_LAN1 16 +#define TL_WR841NV9_GPIO_LED_LAN2 15 +#define TL_WR841NV9_GPIO_LED_LAN3 14 +#define TL_WR841NV9_GPIO_LED_LAN4 11 + +#define TL_WR841NV9_GPIO_BTN_RESET 12 +#define TL_WR841NV9_GPIO_BTN_WIFI 17 + +#define TL_WR841NV9_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR841NV9_KEYS_POLL_INTERVAL) + +static const char *tl_wr841n_v9_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr841n_v9_flash_data = { + .part_probes = tl_wr841n_v9_part_probes, +}; + +static struct gpio_led tl_wr841n_v9_leds_gpio[] __initdata = { + { + .name = "tp-link:green:lan1", + .gpio = TL_WR841NV9_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "tp-link:green:lan2", + .gpio = TL_WR841NV9_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "tp-link:green:lan3", + .gpio = TL_WR841NV9_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "tp-link:green:lan4", + .gpio = TL_WR841NV9_GPIO_LED_LAN4, + .active_low = 1, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841NV9_GPIO_LED_QSS, + .active_low = 1, + }, { + .name = "tp-link:green:wan", + .gpio = TL_WR841NV9_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR841NV9_GPIO_LED_WLAN, + .active_low = 1, + }, +}; + +static struct gpio_keys_button tl_wr841n_v9_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV9_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "WIFI button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = TL_WR841NV9_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841NV9_GPIO_BTN_WIFI, + .active_low = 1, + } +}; + + +static void __init tl_ap143_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 tmpmac[ETH_ALEN]; + + ath79_register_m25p80(&tl_wr841n_v9_flash_data); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_mdio(0, 0x0); + + /* LAN */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); + ath79_register_eth(1); + + /* WAN */ + ath79_switch_data.phy4_mii_en = 1; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.phy_mask = BIT(4); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_register_eth(0); + + ath79_init_mac(tmpmac, mac, 0); + ath79_register_wmac(ee, tmpmac); +} + +static void __init tl_wr841n_v9_setup(void) +{ + tl_ap143_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v9_leds_gpio), + tl_wr841n_v9_leds_gpio); + + ath79_register_gpio_keys_polled(1, TL_WR841NV9_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v9_gpio_keys), + tl_wr841n_v9_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V9, "TL-WR841N-v9", "TP-LINK TL-WR841N/ND v9", + tl_wr841n_v9_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c new file mode 100644 index 0000000..11f853f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n.c @@ -0,0 +1,140 @@ +/* + * TP-LINK TL-WR841N/ND v1 board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-dsa.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" +#include "pci.h" + +#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 +#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 +#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 + +#define TL_WR841ND_V1_GPIO_BTN_RESET 3 +#define TL_WR841ND_V1_GPIO_BTN_QSS 7 + +#define TL_WR841ND_V1_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL \ + (3 * TL_WR841ND_V1_KEYS_POLL_INTERVAL) + +static struct mtd_partition tl_wr841n_v1_partitions[] = { + { + .name = "redboot", + .offset = 0, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = 0x020000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x160000, + .size = 0x280000, + }, { + .name = "config", + .offset = 0x3e0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x020000, + .size = 0x3c0000, + } +}; + +static struct flash_platform_data tl_wr841n_v1_flash_data = { + .parts = tl_wr841n_v1_partitions, + .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), +}; + +static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:red:qss", + .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, + } +}; + +static struct gpio_keys_button tl_wr841n_v1_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { + .port_names[0] = "wan", + .port_names[1] = "lan1", + .port_names[2] = "lan2", + .port_names[3] = "lan3", + .port_names[4] = "lan4", + .port_names[5] = "cpu", +}; + +static struct dsa_platform_data tl_wr841n_v1_dsa_data = { + .nr_chips = 1, + .chip = &tl_wr841n_v1_dsa_chip, +}; + +static void __init tl_wr841n_v1_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev, + &tl_wr841n_v1_dsa_data); + + ath79_register_m25p80(&tl_wr841n_v1_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), + tl_wr841n_v1_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR841ND_V1_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr841n_v1_gpio_keys), + tl_wr841n_v1_gpio_keys); + ath79_register_pci(); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", + tl_wr841n_v1_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c new file mode 100644 index 0000000..1ddeec7 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr941nd.c @@ -0,0 +1,121 @@ +/* + * TP-LINK TL-WR941ND board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include + +#include "dev-dsa.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TL_WR941ND_GPIO_LED_SYSTEM 2 +#define TL_WR941ND_GPIO_LED_QSS_RED 4 +#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 +#define TL_WR941ND_GPIO_LED_WLAN 9 + +#define TL_WR941ND_GPIO_BTN_RESET 3 +#define TL_WR941ND_GPIO_BTN_QSS 7 + +#define TL_WR941ND_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TL_WR941ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR941ND_KEYS_POLL_INTERVAL) + +static const char *tl_wr941nd_part_probes[] = { + "tp-link", + NULL, +}; + +static struct flash_platform_data tl_wr941nd_flash_data = { + .part_probes = tl_wr941nd_part_probes, +}; + +static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { + { + .name = "tp-link:green:system", + .gpio = TL_WR941ND_GPIO_LED_SYSTEM, + .active_low = 1, + }, { + .name = "tp-link:red:qss", + .gpio = TL_WR941ND_GPIO_LED_QSS_RED, + }, { + .name = "tp-link:green:qss", + .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, + }, { + .name = "tp-link:green:wlan", + .gpio = TL_WR941ND_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button tl_wr941nd_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR941ND_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "qss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, + .gpio = TL_WR941ND_GPIO_BTN_QSS, + .active_low = 1, + } +}; + +static struct dsa_chip_data tl_wr941nd_dsa_chip = { + .port_names[0] = "wan", + .port_names[1] = "lan1", + .port_names[2] = "lan2", + .port_names[3] = "lan3", + .port_names[4] = "lan4", + .port_names[5] = "cpu", +}; + +static struct dsa_platform_data tl_wr941nd_dsa_data = { + .nr_chips = 1, + .chip = &tl_wr941nd_dsa_chip, +}; + +static void __init tl_wr941nd_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev, + &tl_wr941nd_dsa_data); + + ath79_register_m25p80(&tl_wr941nd_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), + tl_wr941nd_leds_gpio); + + ath79_register_gpio_keys_polled(-1, TL_WR941ND_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tl_wr941nd_gpio_keys), + tl_wr941nd_gpio_keys); + ath79_register_wmac(eeprom, mac); +} + +MIPS_MACHINE(ATH79_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", + tl_wr941nd_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tube2h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tube2h.c new file mode 100644 index 0000000..19b32e2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tube2h.c @@ -0,0 +1,118 @@ +/* + * ALFA NETWORK Tube2H board support + * + * Copyright (C) 2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define TUBE2H_GPIO_LED_SIGNAL4 0 +#define TUBE2H_GPIO_LED_SIGNAL3 1 +#define TUBE2H_GPIO_LED_SIGNAL2 13 +#define TUBE2H_GPIO_LED_LAN 17 +#define TUBE2H_GPIO_LED_SIGNAL1 27 +#define TUBE2H_GPIO_EXT_LNA 28 + +#define TUBE2H_GPIO_BTN_RESET 12 + +#define TUBE2H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define TUBE2H_KEYS_DEBOUNCE_INTERVAL (3 * TUBE2H_KEYS_POLL_INTERVAL) + +#define TUBE2H_ART_ADDRESS 0x1f7f0000 +#define TUBE2H_LAN_MAC_OFFSET 0x06 +#define TUBE2H_CALDATA_OFFSET 0x1000 + +static struct gpio_led tube2h_leds_gpio[] __initdata = { + { + .name = "alfa:blue:lan", + .gpio = TUBE2H_GPIO_LED_LAN, + .active_low = 1, + }, + { + .name = "alfa:red:signal1", + .gpio = TUBE2H_GPIO_LED_SIGNAL1, + .active_low = 1, + }, + { + .name = "alfa:orange:signal2", + .gpio = TUBE2H_GPIO_LED_SIGNAL2, + .active_low = 0, + }, + { + .name = "alfa:green:signal3", + .gpio = TUBE2H_GPIO_LED_SIGNAL3, + .active_low = 0, + }, + { + .name = "alfa:green:signal4", + .gpio = TUBE2H_GPIO_LED_SIGNAL4, + .active_low = 0, + }, +}; + +static struct gpio_keys_button tube2h_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = TUBE2H_KEYS_DEBOUNCE_INTERVAL, + .gpio = TUBE2H_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init tube2h_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(TUBE2H_ART_ADDRESS); + u32 t; + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_JTAG_DISABLE | + AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + /* Ensure that GPIO26 and GPIO27 are controllable by software */ + t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); + t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; + ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); + + gpio_request_one(TUBE2H_GPIO_EXT_LNA, + GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "external LNA0"); + + ath79_register_wmac(art + TUBE2H_CALDATA_OFFSET, NULL); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(tube2h_leds_gpio), + tube2h_leds_gpio); + ath79_register_gpio_keys_polled(-1, TUBE2H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(tube2h_gpio_keys), + tube2h_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, + art + TUBE2H_LAN_MAC_OFFSET, 0); + ath79_register_mdio(0, 0x0); + ath79_register_eth(0); +} + +MIPS_MACHINE(ATH79_MACH_TUBE2H, "TUBE2H", "ALFA NETWORK Tube2H", + tube2h_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c new file mode 100644 index 0000000..e49ac23 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-ubnt.c @@ -0,0 +1,205 @@ +/* + * Ubiquiti RouterStation support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008 Ubiquiti + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define UBNT_RS_GPIO_LED_RF 2 +#define UBNT_RS_GPIO_SW4 8 + +#define UBNT_LS_SR71_GPIO_LED_D25 0 +#define UBNT_LS_SR71_GPIO_LED_D26 1 +#define UBNT_LS_SR71_GPIO_LED_D24 2 +#define UBNT_LS_SR71_GPIO_LED_D23 4 +#define UBNT_LS_SR71_GPIO_LED_D22 5 +#define UBNT_LS_SR71_GPIO_LED_D27 6 +#define UBNT_LS_SR71_GPIO_LED_D28 7 + +#define UBNT_KEYS_POLL_INTERVAL 20 /* msecs */ +#define UBNT_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_KEYS_POLL_INTERVAL) + +static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { + { + .name = "ubnt:green:rf", + .gpio = UBNT_RS_GPIO_LED_RF, + .active_low = 0, + } +}; + +static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { + { + .name = "ubnt:green:d22", + .gpio = UBNT_LS_SR71_GPIO_LED_D22, + .active_low = 0, + }, { + .name = "ubnt:green:d23", + .gpio = UBNT_LS_SR71_GPIO_LED_D23, + .active_low = 0, + }, { + .name = "ubnt:green:d24", + .gpio = UBNT_LS_SR71_GPIO_LED_D24, + .active_low = 0, + }, { + .name = "ubnt:red:d25", + .gpio = UBNT_LS_SR71_GPIO_LED_D25, + .active_low = 0, + }, { + .name = "ubnt:red:d26", + .gpio = UBNT_LS_SR71_GPIO_LED_D26, + .active_low = 0, + }, { + .name = "ubnt:green:d27", + .gpio = UBNT_LS_SR71_GPIO_LED_D27, + .active_low = 0, + }, { + .name = "ubnt:green:d28", + .gpio = UBNT_LS_SR71_GPIO_LED_D28, + .active_low = 0, + } +}; + +static struct gpio_keys_button ubnt_gpio_keys[] __initdata = { + { + .desc = "sw4", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL, + .gpio = UBNT_RS_GPIO_SW4, + .active_low = 1, + } +}; + +static const char *ubnt_part_probes[] = { + "RedBoot", + NULL, +}; + +static struct flash_platform_data ubnt_flash_data = { + .part_probes = ubnt_part_probes, +}; + +static void __init ubnt_generic_setup(void) +{ + ath79_register_m25p80(&ubnt_flash_data); + + ath79_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ubnt_gpio_keys), + ubnt_gpio_keys); + ath79_register_pci(); +} + +#define UBNT_RS_WAN_PHYMASK BIT(20) +#define UBNT_RS_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) + +static void __init ubnt_rs_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; + + /* + * There is Secondary MAC address duplicate problem with some + * UBNT HW batches. Do not increase Secondary MAC address by 1 + * but do workaround with 'Locally Administrated' bit. + */ + ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.speed = SPEED_100; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), + ubnt_rs_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", + ubnt_rs_setup); + +#define UBNT_RSPRO_WAN_PHYMASK BIT(4) +#define UBNT_RSPRO_LAN_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +static void __init ubnt_rspro_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~(UBNT_RSPRO_WAN_PHYMASK | + UBNT_RSPRO_LAN_PHYMASK)); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; + + /* + * There is Secondary MAC address duplicate problem with some + * UBNT HW batches. Do not increase Secondary MAC address by 1 + * but do workaround with 'Locally Administrated' bit. + */ + ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), + ubnt_rs_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", + ubnt_rspro_setup); + +static void __init ubnt_lsx_setup(void) +{ + ubnt_generic_setup(); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); + +#define UBNT_LSSR71_PHY_MASK BIT(1) + +static void __init ubnt_lssr71_setup(void) +{ + ubnt_generic_setup(); + + ath79_register_mdio(0, ~UBNT_LSSR71_PHY_MASK); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; + + ath79_register_eth(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), + ubnt_ls_sr71_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", + ubnt_lssr71_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-weio.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-weio.c new file mode 100644 index 0000000..3973ada --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-weio.c @@ -0,0 +1,140 @@ +/** + * WEIO Web Of Things Platform + * + * Copyright (C) 2013 Drasko DRASKOVIC and Uros PETREVSKI + * + * ## ## ######## #### ####### + * ## ## ## ## ## ## ## + * ## ## ## ## ## ## ## + * ## ## ## ###### ## ## ## + * ## ## ## ## ## ## ## + * ## ## ## ## ## ## ## + * ### ### ######## #### ####### + * + * Web Of Things Platform + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Authors : + * Drasko DRASKOVIC + * Uros PETREVSKI + */ + +#include +#include +#include +#include +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WEIO_GPIO_LED_STA 1 +#define WEIO_GPIO_LED_AP 16 + +#define WEIO_GPIO_BTN_AP 20 +#define WEIO_GPIO_BTN_RESET 23 + +#define WEIO_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WEIO_KEYS_DEBOUNCE_INTERVAL (3 * WEIO_KEYS_POLL_INTERVAL) + +#define WEIO_MAC0_OFFSET 0x0000 +#define WEIO_MAC1_OFFSET 0x0006 +#define WEIO_CALDATA_OFFSET 0x1000 +#define WEIO_WMAC_MAC_OFFSET 0x1002 + +static struct gpio_led weio_leds_gpio[] __initdata = { + { + .name = "weio:green:sta", + .gpio = WEIO_GPIO_LED_STA, + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "weio:green:ap", + .gpio = WEIO_GPIO_LED_AP, + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_ON, + } +}; + +static struct gpio_keys_button weio_gpio_keys[] __initdata = { + { + .desc = "ap button", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = WEIO_KEYS_DEBOUNCE_INTERVAL, + .gpio = WEIO_GPIO_BTN_AP, + .active_low = 1, + }, + { + .desc = "soft-reset button", + .type = EV_KEY, + .code = BTN_1, + .debounce_interval = WEIO_KEYS_DEBOUNCE_INTERVAL, + .gpio = WEIO_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct i2c_gpio_platform_data weio_i2c_gpio_data = { + .sda_pin = 18, + .scl_pin = 19, +}; + +static struct platform_device weio_i2c_gpio = { + .name = "i2c-gpio", + .id = 0, + .dev = { + .platform_data = &weio_i2c_gpio_data, + }, +}; + +static void __init weio_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_wmac(art + WEIO_CALDATA_OFFSET, art + WEIO_WMAC_MAC_OFFSET); +} + +static void __init weio_setup(void) +{ + weio_common_setup(); + + ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + platform_device_register(&weio_i2c_gpio); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(weio_leds_gpio), + weio_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WEIO_KEYS_POLL_INTERVAL, + ARRAY_SIZE(weio_gpio_keys), + weio_gpio_keys); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_WEIO, "WEIO", "WeIO board", weio_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c new file mode 100644 index 0000000..48f49ad --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-whr-hp-g300n.c @@ -0,0 +1,155 @@ +/* + * Buffalo WHR-HP-G300N board support + * + * based on ... + * + * TP-LINK TL-WR741ND board support + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WHRHPG300N_GPIO_LED_SECURITY 0 +#define WHRHPG300N_GPIO_LED_DIAG 1 +#define WHRHPG300N_GPIO_LED_ROUTER 6 + +#define WHRHPG300N_GPIO_BTN_ROUTER_ON 7 +#define WHRHPG300N_GPIO_BTN_ROUTER_AUTO 8 +#define WHRHPG300N_GPIO_BTN_RESET 11 +#define WHRHPG300N_GPIO_BTN_AOSS 12 +#define WHRHPG300N_GPIO_LED_LAN1 13 +#define WHRHPG300N_GPIO_LED_LAN2 14 +#define WHRHPG300N_GPIO_LED_LAN3 15 +#define WHRHPG300N_GPIO_LED_LAN4 16 +#define WHRHPG300N_GPIO_LED_WAN 17 + +#define WHRHPG300N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WHRHPG300N_KEYS_DEBOUNCE_INTERVAL (3 * WHRHPG300N_KEYS_POLL_INTERVAL) + +#define WHRHPG300N_MAC_OFFSET 0x20c + +static struct gpio_led whrhpg300n_leds_gpio[] __initdata = { + { + .name = "buffalo:orange:security", + .gpio = WHRHPG300N_GPIO_LED_SECURITY, + .active_low = 1, + }, { + .name = "buffalo:red:diag", + .gpio = WHRHPG300N_GPIO_LED_DIAG, + .active_low = 1, + }, { + .name = "buffalo:green:router", + .gpio = WHRHPG300N_GPIO_LED_ROUTER, + .active_low = 1, + }, { + .name = "buffalo:green:wan", + .gpio = WHRHPG300N_GPIO_LED_WAN, + .active_low = 1, + }, { + .name = "buffalo:green:lan1", + .gpio = WHRHPG300N_GPIO_LED_LAN1, + .active_low = 1, + }, { + .name = "buffalo:green:lan2", + .gpio = WHRHPG300N_GPIO_LED_LAN2, + .active_low = 1, + }, { + .name = "buffalo:green:lan3", + .gpio = WHRHPG300N_GPIO_LED_LAN3, + .active_low = 1, + }, { + .name = "buffalo:green:lan4", + .gpio = WHRHPG300N_GPIO_LED_LAN4, + .active_low = 1, + } +}; + +static struct gpio_keys_button whrhpg300n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = WHRHPG300N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "aoss/wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .gpio = WHRHPG300N_GPIO_BTN_AOSS, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_2, + .gpio = WHRHPG300N_GPIO_BTN_ROUTER_ON, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + }, { + .desc = "router_auto", + .type = EV_KEY, + .code = BTN_3, + .gpio = WHRHPG300N_GPIO_BTN_ROUTER_AUTO, + .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL, + .active_low = 1, + } +}; + +static void __init whrhpg300n_setup(void) +{ + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac = (u8 *) KSEG1ADDR(ee + WHRHPG300N_MAC_OFFSET); + + ath79_register_m25p80(NULL); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(whrhpg300n_leds_gpio), + whrhpg300n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WHRHPG300N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(whrhpg300n_gpio_keys), + whrhpg300n_gpio_keys); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN ports */ + ath79_register_eth(1); + /* WAN port */ + ath79_register_eth(0); + + ap9x_pci_setup_wmac_led_pin(0, 1); + + ap91_pci_init(ee, mac); +} + +MIPS_MACHINE(ATH79_MACH_WHR_HP_G300N, "WHR-HP-G300N", "Buffalo WHR-HP-G300N", + whrhpg300n_setup); + +MIPS_MACHINE(ATH79_MACH_WHR_G301N, "WHR-G301N", "Buffalo WHR-G301N", + whrhpg300n_setup); + +MIPS_MACHINE(ATH79_MACH_WHR_HP_GN, "WHR-HP-GN", "Buffalo WHR-HP-GN", + whrhpg300n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c new file mode 100644 index 0000000..11006fd --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlae-ag300n.c @@ -0,0 +1,114 @@ +/* + * Buffalo WLAE-AG300N board support + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WLAEAG300N_MAC_OFFSET 0x20c +#define WLAEAG300N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WLAEAG300N_KEYS_DEBOUNCE_INTERVAL (3 * WLAEAG300N_KEYS_POLL_INTERVAL) + + +static struct gpio_led wlaeag300n_leds_gpio[] __initdata = { + /* + * Note: Writing 1 into GPIO 13 will power down the device. + */ + { + .name = "buffalo:green:wireless", + .gpio = 14, + .active_low = 1, + }, { + .name = "buffalo:red:wireless", + .gpio = 15, + .active_low = 1, + }, { + .name = "buffalo:green:status", + .gpio = 16, + .active_low = 1, + }, { + .name = "buffalo:red:status", + .gpio = 17, + .active_low = 1, + } +}; + + +static struct gpio_keys_button wlaeag300n_gpio_keys[] __initdata = { + { + .desc = "function", + .type = EV_KEY, + .code = KEY_MODE, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 0, + .active_low = 1, + }, { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "power", + .type = EV_KEY, + .code = KEY_POWER, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WLAEAG300N_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 1, + } +}; + +static void __init wlaeag300n_setup(void) +{ + u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac1 = eeprom1 + WLAEAG300N_MAC_OFFSET; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 1); + + ath79_register_mdio(0, ~(BIT(0) | BIT(4))); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wlaeag300n_leds_gpio), + wlaeag300n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WLAEAG300N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wlaeag300n_gpio_keys), + wlaeag300n_gpio_keys); + + ath79_register_m25p80(NULL); + + ap91_pci_init(eeprom1, mac1); +} + +MIPS_MACHINE(ATH79_MACH_WLAE_AG300N, "WLAE-AG300N", + "Buffalo WLAE-AG300N", wlaeag300n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c new file mode 100644 index 0000000..6a90c6e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c @@ -0,0 +1,206 @@ +/* + * Sitecom X8 AC1750 WLR-8100 board support + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WLR8100_GPIO_LED_USB 4 +#define WLR8100_GPIO_LED_WLAN_5G 12 +#define WLR8100_GPIO_LED_WLAN_2G 13 +#define WLR8100_GPIO_LED_STATUS_RED 14 +#define WLR8100_GPIO_LED_WPS_RED 15 +#define WLR8100_GPIO_LED_STATUS_AMBER 19 +#define WLR8100_GPIO_LED_WPS_GREEN 20 + +#define WLR8100_GPIO_BTN_WPS 16 +#define WLR8100_GPIO_BTN_RFKILL 21 + +#define WLR8100_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WLR8100_KEYS_DEBOUNCE_INTERVAL (3 * WLR8100_KEYS_POLL_INTERVAL) + +#define WLR8100_MAC0_OFFSET 0 +#define WLR8100_MAC1_OFFSET 6 +#define WLR8100_WMAC_CALDATA_OFFSET 0x1000 +#define WLR8100_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led wlr8100_leds_gpio[] __initdata = { + { + .name = "wlr8100:amber:status", + .gpio = WLR8100_GPIO_LED_STATUS_AMBER, + .active_low = 1, + }, + { + .name = "wlr8100:red:status", + .gpio = WLR8100_GPIO_LED_STATUS_RED, + .active_low = 1, + }, + { + .name = "wlr8100:green:wps", + .gpio = WLR8100_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, + { + .name = "wlr8100:red:wps", + .gpio = WLR8100_GPIO_LED_WPS_RED, + .active_low = 1, + }, + { + .name = "wlr8100:red:wlan-2g", + .gpio = WLR8100_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { + .name = "wlr8100:red:usb", + .gpio = WLR8100_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button wlr8100_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL, + .gpio = WLR8100_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL, + .gpio = WLR8100_GPIO_BTN_RFKILL, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg wlr8100_ar8327_pad0_cfg; +static struct ar8327_pad_cfg wlr8100_ar8327_pad6_cfg; + +static struct ar8327_platform_data wlr8100_ar8327_data = { + .pad0_cfg = &wlr8100_ar8327_pad0_cfg, + .pad6_cfg = &wlr8100_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info wlr8100_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wlr8100_ar8327_data, + }, +}; + +static void __init wlr8100_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wlr8100_leds_gpio), + wlr8100_leds_gpio); + ath79_register_gpio_keys_polled(-1, WLR8100_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wlr8100_gpio_keys), + wlr8100_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + WLR8100_MAC0_OFFSET, 0); + + mdiobus_register_board_info(wlr8100_mdio0_info, + ARRAY_SIZE(wlr8100_mdio0_info)); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + + ath79_register_eth(0); + + /* GMAC1 is connected tot eh SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(1); +} + +static void __init wlr8100_010_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */ + wlr8100_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; + wlr8100_ar8327_pad0_cfg.txclk_delay_en = true; + wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true; + wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; + wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; + wlr8100_ar8327_pad0_cfg.mac06_exchange_en = true; + + /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */ + wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; + wlr8100_ar8327_pad6_cfg.rxclk_delay_en = true; + wlr8100_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; + + ath79_eth0_pll_data.pll_1000 = 0xa6000000; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + wlr8100_common_setup(); + ap91_pci_init(art + WLR8100_PCIE_CALDATA_OFFSET, NULL); +} + +MIPS_MACHINE(ATH79_MACH_WLR8100, "WLR8100", + "Sitecom WLR-8100", + wlr8100_010_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wndap360.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndap360.c new file mode 100644 index 0000000..e70d88b --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndap360.c @@ -0,0 +1,105 @@ +/* + * Netgear WNDAP360 board support (proper leds / button support missing) + * + * Based on AP96 + * Copyright (C) 2013 Jacek Kikiewicz + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2010 Atheros Communications + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WNDAP360_GPIO_LED_POWER_ORANGE 0 +#define WNDAP360_GPIO_LED_POWER_GREEN 2 + +/* Reset button - next to the power connector */ +#define WNDAP360_GPIO_BTN_RESET 8 + +#define WNDAP360_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNDAP360_KEYS_DEBOUNCE_INTERVAL (3 * WNDAP360_KEYS_POLL_INTERVAL) + +#define WNDAP360_WMAC0_MAC_OFFSET 0x120c +#define WNDAP360_WMAC1_MAC_OFFSET 0x520c +#define WNDAP360_CALDATA0_OFFSET 0x1000 +#define WNDAP360_CALDATA1_OFFSET 0x5000 + +/* + * WNDAP360 this still uses leds definitions from AP96 + * + */ +static struct gpio_led wndap360_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNDAP360_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "netgear:orange:power", + .gpio = WNDAP360_GPIO_LED_POWER_ORANGE, + .active_low = 1, + } +}; + +static struct gpio_keys_button wndap360_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNDAP360_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDAP360_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +#define WNDAP360_LAN_PHYMASK 0x0f + +static void __init wndap360_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, ~(WNDAP360_LAN_PHYMASK)); + + /* Reusing wifi MAC with offset of 1 as eth0 MAC */ + ath79_init_mac(ath79_eth0_data.mac_addr, + art + WNDAP360_WMAC0_MAC_OFFSET, 1); + ath79_eth0_pll_data.pll_1000 = 0x11110000; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = WNDAP360_LAN_PHYMASK; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndap360_leds_gpio), + wndap360_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNDAP360_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wndap360_gpio_keys), + wndap360_gpio_keys); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap94_pci_init(art + WNDAP360_CALDATA0_OFFSET, + art + WNDAP360_WMAC0_MAC_OFFSET, + art + WNDAP360_CALDATA1_OFFSET, + art + WNDAP360_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_WNDAP360, "WNDAP360", "Netgear WNDAP360", wndap360_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c new file mode 100644 index 0000000..1315bab --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr3700.c @@ -0,0 +1,172 @@ +/* + * Netgear WNDR3700 board support + * + * Copyright (C) 2009 Marco Porsch + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WNDR3700_GPIO_LED_WPS_ORANGE 0 +#define WNDR3700_GPIO_LED_POWER_ORANGE 1 +#define WNDR3700_GPIO_LED_POWER_GREEN 2 +#define WNDR3700_GPIO_LED_WPS_GREEN 4 +#define WNDR3700_GPIO_LED_WAN_GREEN 6 + +#define WNDR3700_GPIO_BTN_WPS 3 +#define WNDR3700_GPIO_BTN_RESET 8 +#define WNDR3700_GPIO_BTN_WIFI 11 + +#define WNDR3700_GPIO_RTL8366_SDA 5 +#define WNDR3700_GPIO_RTL8366_SCK 7 + +#define WNDR3700_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNDR3700_KEYS_DEBOUNCE_INTERVAL (3 * WNDR3700_KEYS_POLL_INTERVAL) + +#define WNDR3700_ETH0_MAC_OFFSET 0 +#define WNDR3700_ETH1_MAC_OFFSET 0x6 + +#define WNDR3700_WMAC0_MAC_OFFSET 0 +#define WNDR3700_WMAC1_MAC_OFFSET 0xc +#define WNDR3700_CALDATA0_OFFSET 0x1000 +#define WNDR3700_CALDATA1_OFFSET 0x5000 + +static struct gpio_led wndr3700_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNDR3700_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, { + .name = "netgear:orange:power", + .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, + .active_low = 1, + }, { + .name = "netgear:green:wps", + .gpio = WNDR3700_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, { + .name = "netgear:orange:wps", + .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, + .active_low = 1, + }, { + .name = "netgear:green:wan", + .gpio = WNDR3700_GPIO_LED_WAN_GREEN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wndr3700_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_WPS, + .active_low = 1, + }, { + .desc = "wifi", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR3700_GPIO_BTN_WIFI, + .active_low = 1, + } +}; + +static struct rtl8366_platform_data wndr3700_rtl8366s_data = { + .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, + .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, +}; + +static struct platform_device wndr3700_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wndr3700_rtl8366s_data, + } +}; + +static void __init wndr3700_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + /* + * The eth0 and wmac0 interfaces share the same MAC address which + * can lead to problems if operated unbridged. Set the locally + * administered bit on the eth0 MAC to make it unique. + */ + ath79_init_local_mac(ath79_eth0_data.mac_addr, + art + WNDR3700_ETH0_MAC_OFFSET); + ath79_eth0_pll_data.pll_1000 = 0x11110000; + ath79_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, + art + WNDR3700_ETH1_MAC_OFFSET, 0); + ath79_eth1_pll_data.pll_1000 = 0x11110000; + ath79_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), + wndr3700_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNDR3700_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wndr3700_gpio_keys), + wndr3700_gpio_keys); + + platform_device_register(&wndr3700_rtl8366s_device); + platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); + + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_led_pin(1, 5); + + /* 2.4 GHz uses the first fixed antenna group (1, 0, 1, 0) */ + ap9x_pci_setup_wmac_gpio(0, (0xf << 6), (0xa << 6)); + + /* 5 GHz uses the second fixed antenna group (0, 1, 1, 0) */ + ap9x_pci_setup_wmac_gpio(1, (0xf << 6), (0x6 << 6)); + + ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, + art + WNDR3700_WMAC0_MAC_OFFSET, + art + WNDR3700_CALDATA1_OFFSET, + art + WNDR3700_WMAC1_MAC_OFFSET); +} + +MIPS_MACHINE(ATH79_MACH_WNDR3700, "WNDR3700", + "NETGEAR WNDR3700/WNDR3800/WNDRMAC", + wndr3700_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr4300.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr4300.c new file mode 100644 index 0000000..2884c6c --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wndr4300.c @@ -0,0 +1,210 @@ +/* + * NETGEAR WNDR3700v4/WNDR4300 board support + * + * Copyright (C) 2012 Gabor Juhos + * Copyright (C) 2014 Ralph Perlich + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-nfc.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +/* AR9344 GPIOs */ +#define WNDR4300_GPIO_LED_POWER_GREEN 0 +#define WNDR4300_GPIO_LED_POWER_AMBER 2 +#define WNDR4300_GPIO_LED_USB 13 +#define WNDR4300_GPIO_LED_WAN_GREEN 1 +#define WNDR4300_GPIO_LED_WAN_AMBER 3 +#define WNDR4300_GPIO_LED_WLAN2G 11 +#define WNDR4300_GPIO_LED_WLAN5G 14 +#define WNDR4300_GPIO_LED_WPS_GREEN 16 +#define WNDR4300_GPIO_LED_WPS_AMBER 17 + +#define WNDR4300_GPIO_BTN_RESET 21 +#define WNDR4300_GPIO_BTN_WIRELESS 15 +#define WNDR4300_GPIO_BTN_WPS 12 + +/* AR9580 GPIOs */ +#define WNDR4300_GPIO_USB_5V 0 + +#define WNDR4300_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNDR4300_KEYS_DEBOUNCE_INTERVAL (3 * WNDR4300_KEYS_POLL_INTERVAL) + +static struct gpio_led wndr4300_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNDR4300_GPIO_LED_POWER_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:power", + .gpio = WNDR4300_GPIO_LED_POWER_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wan", + .gpio = WNDR4300_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:wan", + .gpio = WNDR4300_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:usb", + .gpio = WNDR4300_GPIO_LED_USB, + .active_low = 1, + }, + { + .name = "netgear:green:wps", + .gpio = WNDR4300_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:wps", + .gpio = WNDR4300_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wlan2g", + .gpio = WNDR4300_GPIO_LED_WLAN2G, + .active_low = 1, + }, + { + .name = "netgear:blue:wlan5g", + .gpio = WNDR4300_GPIO_LED_WLAN5G, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wndr4300_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR4300_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR4300_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Wireless button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = WNDR4300_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNDR4300_GPIO_BTN_WIRELESS, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg wndr4300_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wndr4300_ar8327_led_cfg = { + .led_ctrl0 = 0xc737c737, + .led_ctrl1 = 0x00000000, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x0030c300, + .open_drain = false, +}; + +static struct ar8327_platform_data wndr4300_ar8327_data = { + .pad0_cfg = &wndr4300_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wndr4300_ar8327_led_cfg, +}; + +static struct mdio_board_info wndr4300_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wndr4300_ar8327_data, + }, +}; + +static void __init wndr4300_setup(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(wndr4300_leds_gpio); i++) + ath79_gpio_output_select(wndr4300_leds_gpio[i].gpio, + AR934X_GPIO_OUT_GPIO); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr4300_leds_gpio), + wndr4300_leds_gpio); + ath79_register_gpio_keys_polled(-1, WNDR4300_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wndr4300_gpio_keys), + wndr4300_gpio_keys); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); + + mdiobus_register_board_info(wndr4300_mdio0_info, + ARRAY_SIZE(wndr4300_mdio0_info)); + + ath79_register_mdio(0, 0x0); + + /* GMAC0 is connected to an AR8327N switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + ath79_register_eth(0); + + ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); + ath79_register_nfc(); + ath79_register_usb(); + + ath79_register_wmac_simple(); + + /* enable power for the USB port */ + ap9x_pci_setup_wmac_gpio(0, BIT(WNDR4300_GPIO_USB_5V), + BIT(WNDR4300_GPIO_USB_5V)); + + ap91_pci_init_simple(); +} + +MIPS_MACHINE(ATH79_MACH_WNDR3700_V4, "WNDR3700_V4", "NETGEAR WNDR3700v4", + wndr4300_setup); +MIPS_MACHINE(ATH79_MACH_WNDR4300, "WNDR4300", "NETGEAR WNDR4300", + wndr4300_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v3.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v3.c new file mode 100644 index 0000000..2e14782 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v3.c @@ -0,0 +1,140 @@ +/* + * NETGEAR WNR2000v3/WNR612v2/WNR1000v2 board support + * + * Copytight (C) 2013 Mathieu Olivari + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008-2009 Andy Boyett + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WNR2000V3_GPIO_LED_WAN_GREEN 0 +#define WNR2000V3_GPIO_LED_LAN1_AMBER 1 +#define WNR2000V3_GPIO_LED_LAN4_AMBER 12 +#define WNR2000V3_GPIO_LED_PWR_GREEN 14 +#define WNR2000V3_GPIO_BTN_WPS 11 + +#define WNR612V2_GPIO_LED_PWR_GREEN 11 + +#define WNR1000V2_GPIO_LED_PWR_AMBER 1 +#define WNR1000V2_GPIO_LED_PWR_GREEN 11 + +#define WNR2000V3_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2000V3_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000V3_KEYS_POLL_INTERVAL) + +#define WNR2000V3_MAC0_OFFSET 0 +#define WNR2000V3_MAC1_OFFSET 6 +#define WNR2000V3_PCIE_CALDATA_OFFSET 0x1000 + +static struct gpio_led wnr2000v3_leds_gpio[] __initdata = { + { + .name = "wnr2000v3:green:power", + .gpio = WNR2000V3_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, { + .name = "wnr2000v3:green:wan", + .gpio = WNR2000V3_GPIO_LED_WAN_GREEN, + .active_low = 1, + } +}; + +static struct gpio_led wnr612v2_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNR612V2_GPIO_LED_PWR_GREEN, + .active_low = 1, + } +}; + +static struct gpio_led wnr1000v2_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNR1000V2_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, { + .name = "netgear:amber:power", + .gpio = WNR1000V2_GPIO_LED_PWR_AMBER, + .active_low = 1, + } +}; + +static struct gpio_keys_button wnr2000v3_gpio_keys[] __initdata = { + { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNR2000V3_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000V3_GPIO_BTN_WPS, + } +}; + +static void __init wnr_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V3_MAC0_OFFSET, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V3_MAC1_OFFSET, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + ap91_pci_init(art + WNR2000V3_PCIE_CALDATA_OFFSET, NULL); +} + +static void __init wnr2000v3_setup(void) +{ + wnr_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000v3_leds_gpio), + wnr2000v3_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNR2000V3_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wnr2000v3_gpio_keys), + wnr2000v3_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WNR2000_V3, "WNR2000V3", "NETGEAR WNR2000 V3", wnr2000v3_setup); + +static void __init wnr612v2_setup(void) +{ + wnr_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr612v2_leds_gpio), + wnr612v2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_WNR612_V2, "WNR612V2", "NETGEAR WNR612 V2", wnr612v2_setup); + +static void __init wnr1000v2_setup(void) +{ + wnr_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr1000v2_leds_gpio), + wnr1000v2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_WNR1000_V2, "WNR1000V2", "NETGEAR WNR1000 V2", wnr1000v2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v4.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v4.c new file mode 100644 index 0000000..c5159a3 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v4.c @@ -0,0 +1,214 @@ +/* + * NETGEAR WNR2000v4 board support + * + * Copyright (C) 2015 Michael Bazzinotti + * Copyright (C) 2014 Michaël Burtin + * Copyright (C) 2013 Mathieu Olivari + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008-2009 Andy Boyett + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +/* AR9341 GPIOs */ +#define WNR2000V4_GPIO_LED_PWR_GREEN 0 +#define WNR2000V4_GPIO_LED_PWR_AMBER 1 +#define WNR2000V4_GPIO_LED_WPS 2 +#define WNR2000V4_GPIO_LED_WLAN 12 +#define WNR2000V4_GPIO_LED_LAN1_GREEN 13 +#define WNR2000V4_GPIO_LED_LAN2_GREEN 14 +#define WNR2000V4_GPIO_LED_LAN3_GREEN 15 +#define WNR2000V4_GPIO_LED_LAN4_GREEN 16 +#define WNR2000V4_GPIO_LED_LAN1_AMBER 18 +#define WNR2000V4_GPIO_LED_LAN2_AMBER 19 +#define WNR2000V4_GPIO_LED_LAN3_AMBER 20 +#define WNR2000V4_GPIO_LED_LAN4_AMBER 21 +#define WNR2000V4_GPIO_LED_WAN_GREEN 17 +#define WNR2000V4_GPIO_LED_WAN_AMBER 22 +/* Buttons */ +#define WNR2000V4_GPIO_BTN_WPS 3 +#define WNR2000V4_GPIO_BTN_RESET 4 +#define WNR2000V4_GPIO_BTN_WLAN 11 +#define WNR2000V4_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2000V4_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000V4_KEYS_POLL_INTERVAL) + + +/* ART offsets */ +#define WNR2000V4_MAC0_OFFSET 0 /* WAN/WLAN0 MAC */ +#define WNR2000V4_MAC1_OFFSET 6 /* Eth-switch0 MAC */ + +static struct gpio_led wnr2000v4_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNR2000V4_GPIO_LED_PWR_GREEN, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "netgear:amber:status", + .gpio = WNR2000V4_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wan", + .gpio = WNR2000V4_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:wan", + .gpio = WNR2000V4_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, + { + .name = "netgear:blue:wlan", + .gpio = WNR2000V4_GPIO_LED_WLAN, + .active_low = 1, + }, + /* LAN LEDS */ + { + .name = "netgear:green:lan1", + .gpio = WNR2000V4_GPIO_LED_LAN1_GREEN, + .active_low = 1, + }, + { + .name = "netgear:green:lan2", + .gpio = WNR2000V4_GPIO_LED_LAN2_GREEN, + .active_low = 1, + }, + { + .name = "netgear:green:lan3", + .gpio = WNR2000V4_GPIO_LED_LAN3_GREEN, + .active_low = 1, + }, + { + .name = "netgear:green:lan4", + .gpio = WNR2000V4_GPIO_LED_LAN4_GREEN, + .active_low = 1, + }, + { + .name = "netgear:amber:lan1", + .gpio = WNR2000V4_GPIO_LED_LAN1_AMBER, + .active_low = 1, + }, + { + .name = "netgear:amber:lan2", + .gpio = WNR2000V4_GPIO_LED_LAN2_AMBER, + .active_low = 1, + }, + { + .name = "netgear:amber:lan3", + .gpio = WNR2000V4_GPIO_LED_LAN3_AMBER, + .active_low = 1, + }, + { + .name = "netgear:amber:lan4", + .gpio = WNR2000V4_GPIO_LED_LAN4_AMBER, + .active_low = 1, + }, + { + .name = "netgear:green:wps", + .gpio = WNR2000V4_GPIO_LED_WPS, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wnr2000v4_gpio_keys[] __initdata = { + { + .desc = "WPS button", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000V4_GPIO_BTN_WPS, + .active_low = 1, + }, + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000V4_GPIO_BTN_RESET, + .active_low = 1, + }, + { + .desc = "WLAN button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = WNR2000V4_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000V4_GPIO_BTN_WLAN, + .active_low = 1, + }, +}; + +static void __init wnr_common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(1, 0x0); + + ath79_register_usb(); + + ath79_register_m25p80(NULL); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); + + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0); + + /* GMAC0 is connected to the PHY0 of the internal switch, GE0 */ + ath79_switch_data.phy4_mii_en = 1; + ath79_switch_data.phy_poll_mask = BIT(4); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = BIT(4); + ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; + ath79_register_eth(0); + + /* GMAC1 is connected to the internal switch, GE1 */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_register_eth(1); + + ath79_register_wmac(ee, art); +} + +static void __init wnr2000v4_setup(void) +{ + int i; + + wnr_common_setup(); + + /* Ensure no LED has an internal MUX signal, otherwise + control of LED could be lost... This is especially important + for most green LEDS (Eth,WAN).. who arrive in this function with + MUX signals set. */ + for (i = 0; i < ARRAY_SIZE(wnr2000v4_leds_gpio); i++) + ath79_gpio_output_select(wnr2000v4_leds_gpio[i].gpio, + AR934X_GPIO_OUT_GPIO); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000v4_leds_gpio), + wnr2000v4_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNR2000V4_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wnr2000v4_gpio_keys), + wnr2000v4_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WNR2000_V4, "WNR2000V4", "NETGEAR WNR2000 V4", wnr2000v4_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c new file mode 100644 index 0000000..b4da7ec --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000.c @@ -0,0 +1,145 @@ +/* + * NETGEAR WNR2000 board support + * + * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2008-2009 Andy Boyett + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WNR2000_GPIO_LED_PWR_GREEN 14 +#define WNR2000_GPIO_LED_PWR_AMBER 7 +#define WNR2000_GPIO_LED_WPS 4 +#define WNR2000_GPIO_LED_WLAN 6 +#define WNR2000_GPIO_BTN_RESET 21 +#define WNR2000_GPIO_BTN_WPS 8 + +#define WNR2000_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2000_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000_KEYS_POLL_INTERVAL) + +static struct mtd_partition wnr2000_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x040000, + .size = 0x010000, + }, { + .name = "rootfs", + .offset = 0x050000, + .size = 0x240000, + }, { + .name = "user-config", + .offset = 0x290000, + .size = 0x010000, + }, { + .name = "uImage", + .offset = 0x2a0000, + .size = 0x120000, + }, { + .name = "language_table", + .offset = 0x3c0000, + .size = 0x020000, + }, { + .name = "rootfs_checksum", + .offset = 0x3e0000, + .size = 0x010000, + }, { + .name = "art", + .offset = 0x3f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct flash_platform_data wnr2000_flash_data = { + .parts = wnr2000_partitions, + .nr_parts = ARRAY_SIZE(wnr2000_partitions), +}; + +static struct gpio_led wnr2000_leds_gpio[] __initdata = { + { + .name = "netgear:green:power", + .gpio = WNR2000_GPIO_LED_PWR_GREEN, + .active_low = 1, + }, { + .name = "netgear:amber:power", + .gpio = WNR2000_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, { + .name = "netgear:green:wps", + .gpio = WNR2000_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "netgear:blue:wlan", + .gpio = WNR2000_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wnr2000_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000_GPIO_BTN_RESET, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, + .gpio = WNR2000_GPIO_BTN_WPS, + } +}; + +static void __init wnr2000_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.has_ar8216 = 1; + + ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wnr2000_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), + wnr2000_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WNR2000_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wnr2000_gpio_keys), + wnr2000_gpio_keys); + + ath79_register_wmac(eeprom, NULL); +} + +MIPS_MACHINE(ATH79_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2200.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2200.c new file mode 100644 index 0000000..a1de26a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2200.c @@ -0,0 +1,137 @@ +/* + * NETGEAR WNR2200 board support + * + * Copyright (C) 2013 Aidan Kissane + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WNR2200_GPIO_LED_LAN2_AMBER 0 +#define WNR2200_GPIO_LED_LAN4_AMBER 1 +#define WNR2200_GPIO_LED_WPS 5 +#define WNR2200_GPIO_LED_WAN_GREEN 7 +#define WNR2200_GPIO_LED_USB 8 +#define WNR2200_GPIO_LED_LAN3_AMBER 11 +#define WNR2200_GPIO_LED_WAN_AMBER 12 +#define WNR2200_GPIO_LED_LAN1_GREEN 13 +#define WNR2200_GPIO_LED_LAN2_GREEN 14 +#define WNR2200_GPIO_LED_LAN3_GREEN 15 +#define WNR2200_GPIO_LED_LAN4_GREEN 16 +#define WNR2200_GPIO_LED_PWR_AMBER 21 +#define WNR2200_GPIO_LED_PWR_GREEN 22 +#define WNR2200_GPIO_USB_5V 4 +#define WNR2200_GPIO_USB_POWER 24 + +#define WNR2200_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WNR2200_KEYS_DEBOUNCE_INTERVAL (3 * WNR2200_KEYS_POLL_INTERVAL) + +#define WNR2200_MAC0_OFFSET 0 +#define WNR2200_MAC1_OFFSET 6 +#define WNR2200_PCIE_CALDATA_OFFSET 0x1000 + +static struct gpio_led wnr2200_leds_gpio[] __initdata = { + { + .name = "netgear:amber:lan2", + .gpio = WNR2200_GPIO_LED_LAN2_AMBER, + .active_low = 1, + }, { + .name = "netgear:amber:lan4", + .gpio = WNR2200_GPIO_LED_LAN4_AMBER, + .active_low = 1, + }, { + .name = "netgear:green:wps", + .gpio = WNR2200_GPIO_LED_WPS, + .active_low = 1, + }, { + .name = "netgear:green:wan", + .gpio = WNR2200_GPIO_LED_WAN_GREEN, + .active_low = 1, + }, { + .name = "netgear:green:usb", + .gpio = WNR2200_GPIO_LED_USB, + .active_low = 1, + }, { + .name = "netgear:amber:lan3", + .gpio = WNR2200_GPIO_LED_LAN3_AMBER, + .active_low = 1, + }, { + .name = "netgear:amber:wan", + .gpio = WNR2200_GPIO_LED_WAN_AMBER, + .active_low = 1, + }, { + .name = "netgear:green:lan1", + .gpio = WNR2200_GPIO_LED_LAN1_GREEN, + .active_low = 1, + }, { + .name = "netgear:green:lan2", + .gpio = WNR2200_GPIO_LED_LAN2_GREEN, + .active_low = 1, + }, { + .name = "netgear:green:lan3", + .gpio = WNR2200_GPIO_LED_LAN3_GREEN, + .active_low = 1, + }, { + .name = "netgear:green:lan4", + .gpio = WNR2200_GPIO_LED_LAN4_GREEN, + .active_low = 1, + }, { + .name = "netgear:amber:power", + .gpio = WNR2200_GPIO_LED_PWR_AMBER, + .active_low = 1, + }, { + .name = "netgear:green:power", + .gpio = WNR2200_GPIO_LED_PWR_GREEN, + .active_low = 1, + } +}; + +static void __init wnr2200_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2200_MAC0_OFFSET, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2200_MAC1_OFFSET, 0); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(NULL); + ap91_pci_init(art + WNR2200_PCIE_CALDATA_OFFSET, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2200_leds_gpio), + wnr2200_leds_gpio); + + /* enable power for the USB port */ + ap9x_pci_setup_wmac_gpio(0, + BIT(WNR2200_GPIO_USB_5V), + BIT(WNR2200_GPIO_USB_5V)); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_WNR2200, "WNR2200", "NETGEAR WNR2200", wnr2200_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c new file mode 100644 index 0000000..dc4aee0 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wp543.c @@ -0,0 +1,109 @@ +/* + * Compex WP543/WPJ543 board support + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define WP543_GPIO_SW6 2 +#define WP543_GPIO_LED_1 3 +#define WP543_GPIO_LED_2 4 +#define WP543_GPIO_LED_WLAN 5 +#define WP543_GPIO_LED_CONN 6 +#define WP543_GPIO_LED_DIAG 7 +#define WP543_GPIO_SW4 8 + +#define WP543_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WP543_KEYS_DEBOUNCE_INTERVAL (3 * WP543_KEYS_POLL_INTERVAL) + +static struct gpio_led wp543_leds_gpio[] __initdata = { + { + .name = "wp543:green:led1", + .gpio = WP543_GPIO_LED_1, + .active_low = 1, + }, { + .name = "wp543:green:led2", + .gpio = WP543_GPIO_LED_2, + .active_low = 1, + }, { + .name = "wp543:green:wlan", + .gpio = WP543_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "wp543:green:conn", + .gpio = WP543_GPIO_LED_CONN, + .active_low = 1, + }, { + .name = "wp543:green:diag", + .gpio = WP543_GPIO_LED_DIAG, + .active_low = 1, + } +}; + +static struct gpio_keys_button wp543_gpio_keys[] __initdata = { + { + .desc = "sw6", + .type = EV_KEY, + .code = BTN_0, + .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, + .gpio = WP543_GPIO_SW6, + .active_low = 1, + }, { + .desc = "sw4", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, + .gpio = WP543_GPIO_SW4, + .active_low = 1, + } +}; + +static const char *wp543_part_probes[] = { + "MyLoader", + NULL, +}; + +static struct flash_platform_data wp543_flash_data = { + .part_probes = wp543_part_probes, +}; + +static void __init wp543_setup(void) +{ + ath79_register_m25p80(&wp543_flash_data); + + ath79_register_mdio(0, 0xfffffff0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.phy_mask = 0x0f; + ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC | + AR71XX_RESET_GE0_PHY; + ath79_register_eth(0); + + ath79_register_usb(); + ath79_register_pci(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), + wp543_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WP543_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wp543_gpio_keys), + wp543_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WP543, "WP543", "Compex WP543", wp543_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c new file mode 100644 index 0000000..9452484 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpe72.c @@ -0,0 +1,97 @@ +/* + * Compex WPE72 board support + * + * Copyright (C) 2012 Johnathan Boyce + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" +#include "pci.h" + +#define WPE72_GPIO_RESET 12 +#define WPE72_GPIO_LED_DIAG 13 +#define WPE72_GPIO_LED_1 14 +#define WPE72_GPIO_LED_2 15 +#define WPE72_GPIO_LED_3 16 +#define WPE72_GPIO_LED_4 17 + +#define WPE72_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPE72_KEYS_DEBOUNCE_INTERVAL (3 * WPE72_KEYS_POLL_INTERVAL) + +static struct gpio_led wpe72_leds_gpio[] __initdata = { + { + .name = "wpe72:green:led1", + .gpio = WPE72_GPIO_LED_1, + .active_low = 1, + }, { + .name = "wpe72:green:led2", + .gpio = WPE72_GPIO_LED_2, + .active_low = 1, + }, { + .name = "wpe72:green:led3", + .gpio = WPE72_GPIO_LED_3, + .active_low = 1, + }, { + .name = "wpe72:green:led4", + .gpio = WPE72_GPIO_LED_4, + .active_low = 1, + }, { + .name = "wpe72:green:diag", + .gpio = WPE72_GPIO_LED_DIAG, + .active_low = 1, + } +}; + +static struct gpio_keys_button wpe72_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPE72_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPE72_GPIO_RESET, + .active_low = 1, + } +}; + +static const char *wpe72_part_probes[] = { + "MyLoader", + NULL, +}; + +static struct flash_platform_data wpe72_flash_data = { + .part_probes = wpe72_part_probes, +}; + +static void __init wpe72_setup(void) +{ + ath79_register_m25p80(&wpe72_flash_data); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + ath79_register_pci(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpe72_leds_gpio), + wpe72_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WPE72_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpe72_gpio_keys), + wpe72_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WPE72, "WPE72", "Compex WPE72", wpe72_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c new file mode 100644 index 0000000..3ca94dc --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj344.c @@ -0,0 +1,175 @@ +/* + * Compex WPJ344 board support + * + * Copyright (c) 2011 Qualcomm Atheros + * Copyright (c) 2011-2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-usb.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WPJ344_GPIO_LED_SIG1 15 +#define WPJ344_GPIO_LED_SIG2 20 +#define WPJ344_GPIO_LED_SIG3 21 +#define WPJ344_GPIO_LED_SIG4 22 +#define WPJ344_GPIO_LED_STATUS 14 + +#define WPJ344_GPIO_BTN_RESET 12 + +#define WPJ344_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPJ344_KEYS_DEBOUNCE_INTERVAL (3 * WPJ344_KEYS_POLL_INTERVAL) + +#define WPJ344_MAC0_OFFSET 0 +#define WPJ344_MAC1_OFFSET 6 +#define WPJ344_WMAC_CALDATA_OFFSET 0x1000 +#define WPJ344_PCIE_CALDATA_OFFSET 0x5000 + +static struct gpio_led wpj344_leds_gpio[] __initdata = { + { + .name = "wpj344:green:status", + .gpio = WPJ344_GPIO_LED_STATUS, + .active_low = 1, + }, + { + .name = "wpj344:red:sig1", + .gpio = WPJ344_GPIO_LED_SIG1, + .active_low = 1, + }, + { + .name = "wpj344:yellow:sig2", + .gpio = WPJ344_GPIO_LED_SIG2, + .active_low = 1, + }, + { + .name = "wpj344:green:sig3", + .gpio = WPJ344_GPIO_LED_SIG3, + .active_low = 1, + }, + { + .name = "wpj344:green:sig4", + .gpio = WPJ344_GPIO_LED_SIG4, + .active_low = 1, + } +}; + +static struct gpio_keys_button wpj344_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPJ344_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPJ344_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg wpj344_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wpj344_ar8327_led_cfg = { + .led_ctrl0 = 0x00000000, + .led_ctrl1 = 0xc737c737, + .led_ctrl2 = 0x00000000, + .led_ctrl3 = 0x00c30c00, + .open_drain = true, +}; + +static struct ar8327_platform_data wpj344_ar8327_data = { + .pad0_cfg = &wpj344_ar8327_pad0_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wpj344_ar8327_led_cfg, +}; + +static struct mdio_board_info wpj344_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wpj344_ar8327_data, + }, +}; + +static void __init wpj344_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj344_leds_gpio), + wpj344_leds_gpio); + ath79_register_gpio_keys_polled(-1, WPJ344_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpj344_gpio_keys), + wpj344_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + WPJ344_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_pci(); + + mdiobus_register_board_info(wpj344_mdio0_info, + ARRAY_SIZE(wpj344_mdio0_info)); + + ath79_register_mdio(1, 0x0); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ344_MAC0_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ344_MAC1_OFFSET, 0); + + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | + AR934X_ETH_CFG_SW_ONLY_MODE); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x06000000; + + /* GMAC1 is connected to the internal switch */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + + ath79_register_eth(0); + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_WPJ344, "WPJ344", "Compex WPJ344", wpj344_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c new file mode 100644 index 0000000..8a238da --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj531.c @@ -0,0 +1,143 @@ +/* + * Compex WPJ531 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include + +#include + +#include "pci.h" +#include "common.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WPJ531_GPIO_LED_SIG1 14 +#define WPJ531_GPIO_LED_SIG2 15 +#define WPJ531_GPIO_LED_SIG3 22 +#define WPJ531_GPIO_LED_SIG4 23 +#define WPJ531_GPIO_BUZZER 4 + +#define WPJ531_GPIO_BTN_RESET 17 + +#define WPJ531_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPJ531_KEYS_DEBOUNCE_INTERVAL (3 * WPJ531_KEYS_POLL_INTERVAL) + +#define WPJ531_MAC0_OFFSET 0x10 +#define WPJ531_MAC1_OFFSET 0x18 +#define WPJ531_WMAC_CALDATA_OFFSET 0x1000 +#define WPJ531_PCIE_CALDATA_OFFSET 0x5000 + +#define WPJ531_ART_SIZE 0x8000 + +static struct gpio_led wpj531_leds_gpio[] __initdata = { + { + .name = "wpj531:red:sig1", + .gpio = WPJ531_GPIO_LED_SIG1, + .active_low = 1, + }, + { + .name = "wpj531:yellow:sig2", + .gpio = WPJ531_GPIO_LED_SIG2, + .active_low = 1, + }, + { + .name = "wpj531:green:sig3", + .gpio = WPJ531_GPIO_LED_SIG3, + .active_low = 1, + }, + { + .name = "wpj531:green:sig4", + .gpio = WPJ531_GPIO_LED_SIG4, + .active_low = 1, + }, + { + .name = "wpj531:buzzer", + .gpio = WPJ531_GPIO_BUZZER, + .active_low = 0, + } +}; + +static struct gpio_keys_button wpj531_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPJ531_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPJ531_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static void __init common_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000); + + ath79_register_m25p80(NULL); + + ath79_setup_ar933x_phy4_switch(false, false); + + ath79_register_mdio(0, 0x0); + + /* LAN */ + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.phy_mask = BIT(4); + ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ531_MAC0_OFFSET, 0); + ath79_register_eth(0); + + /* WAN */ + ath79_switch_data.phy4_mii_en = 1; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_switch_data.phy_poll_mask |= BIT(4); + ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ531_MAC1_OFFSET, 0); + ath79_register_eth(1); + + ath79_register_wmac(art + WPJ531_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_pci(); + ath79_register_usb(); +} + +static void __init wpj531_setup(void) +{ + common_setup(); + + ath79_register_leds_gpio(-1, + ARRAY_SIZE(wpj531_leds_gpio), + wpj531_leds_gpio); + + ath79_register_gpio_keys_polled(-1, + WPJ531_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpj531_gpio_keys), + wpj531_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WPJ531, "WPJ531", "Compex WPJ531", wpj531_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c new file mode 100644 index 0000000..c7b120d --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c @@ -0,0 +1,177 @@ +/* + * Compex WPJ558 board support + * + * Copyright (c) 2012 Qualcomm Atheros + * Copyright (c) 2012-2013 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "pci.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-eth.h" +#include "dev-usb.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WPJ558_GPIO_LED_SIG1 14 +#define WPJ558_GPIO_LED_SIG2 15 +#define WPJ558_GPIO_LED_SIG3 22 +#define WPJ558_GPIO_LED_SIG4 23 +#define WPJ558_GPIO_BUZZER 4 + +#define WPJ558_GPIO_BTN_RESET 17 + +#define WPJ558_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WPJ558_KEYS_DEBOUNCE_INTERVAL (3 * WPJ558_KEYS_POLL_INTERVAL) + +#define WPJ558_MAC_OFFSET 0x1002 +#define WPJ558_WMAC_CALDATA_OFFSET 0x1000 + +static struct gpio_led wpj558_leds_gpio[] __initdata = { + { + .name = "wpj558:red:sig1", + .gpio = WPJ558_GPIO_LED_SIG1, + .active_low = 1, + }, + { + .name = "wpj558:yellow:sig2", + .gpio = WPJ558_GPIO_LED_SIG2, + .active_low = 1, + }, + { + .name = "wpj558:green:sig3", + .gpio = WPJ558_GPIO_LED_SIG3, + .active_low = 1, + }, + { + .name = "wpj558:green:sig4", + .gpio = WPJ558_GPIO_LED_SIG4, + .active_low = 1, + }, + { + .name = "wpj558:buzzer", + .gpio = WPJ558_GPIO_BUZZER, + .active_low = 0, + } +}; + +static struct gpio_keys_button wpj558_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WPJ558_KEYS_DEBOUNCE_INTERVAL, + .gpio = WPJ558_GPIO_BTN_RESET, + .active_low = 1, + }, +}; + +static struct ar8327_pad_cfg wpj558_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +static struct ar8327_pad_cfg wpj558_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_platform_data wpj558_ar8327_data = { + .pad0_cfg = &wpj558_ar8327_pad0_cfg, + .pad6_cfg = &wpj558_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, +}; + +static struct mdio_board_info wpj558_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wpj558_ar8327_data, + }, +}; + +static void __init wpj558_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + + ath79_register_m25p80(NULL); + ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj558_leds_gpio), + wpj558_leds_gpio); + ath79_register_gpio_keys_polled(-1, WPJ558_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wpj558_gpio_keys), + wpj558_gpio_keys); + + ath79_register_usb(); + + ath79_register_wmac(art + WPJ558_WMAC_CALDATA_OFFSET, NULL); + + ath79_register_pci(); + + mdiobus_register_board_info(wpj558_mdio0_info, + ARRAY_SIZE(wpj558_mdio0_info)); + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + /* GMAC0 is connected to an AR8327 switch */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x56000000; + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_register_eth(0); + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_WPJ558, "WPJ558", "Compex WPJ558", wpj558_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c new file mode 100644 index 0000000..ede3c21 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt160nl.c @@ -0,0 +1,126 @@ +/* + * Linksys WRT160NL board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "nvram.h" +#include "machtypes.h" + +#define WRT160NL_GPIO_LED_POWER 14 +#define WRT160NL_GPIO_LED_WPS_AMBER 9 +#define WRT160NL_GPIO_LED_WPS_BLUE 8 +#define WRT160NL_GPIO_LED_WLAN 6 + +#define WRT160NL_GPIO_BTN_WPS 7 +#define WRT160NL_GPIO_BTN_RESET 21 + +#define WRT160NL_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WRT160NL_KEYS_DEBOUNCE_INTERVAL (3 * WRT160NL_KEYS_POLL_INTERVAL) + +#define WRT160NL_NVRAM_ADDR 0x1f7e0000 +#define WRT160NL_NVRAM_SIZE 0x10000 + +static const char *wrt160nl_part_probes[] = { + "cybertan", + NULL, +}; + +static struct flash_platform_data wrt160nl_flash_data = { + .part_probes = wrt160nl_part_probes, +}; + +static struct gpio_led wrt160nl_leds_gpio[] __initdata = { + { + .name = "wrt160nl:blue:power", + .gpio = WRT160NL_GPIO_LED_POWER, + .active_low = 1, + .default_trigger = "default-on", + }, { + .name = "wrt160nl:amber:wps", + .gpio = WRT160NL_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, { + .name = "wrt160nl:blue:wps", + .gpio = WRT160NL_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, { + .name = "wrt160nl:blue:wlan", + .gpio = WRT160NL_GPIO_LED_WLAN, + .active_low = 1, + } +}; + +static struct gpio_keys_button wrt160nl_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, + .gpio = WRT160NL_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wps", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, + .gpio = WRT160NL_GPIO_BTN_WPS, + .active_low = 1, + } +}; + +static void __init wrt160nl_setup(void) +{ + const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 mac[6]; + + if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, + "lan_hwaddr=", mac) == 0) { + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + } + + ath79_register_mdio(0, 0x0); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.phy_mask = 0x01; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wrt160nl_flash_data); + + ath79_register_usb(); + + if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, + "wl0_hwaddr=", mac) == 0) + ath79_register_wmac(eeprom, mac); + else + ath79_register_wmac(eeprom, NULL); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), + wrt160nl_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WRT160NL_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wrt160nl_gpio_keys), + wrt160nl_gpio_keys); +} + +MIPS_MACHINE(ATH79_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", + wrt160nl_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c new file mode 100644 index 0000000..6c4c1cb --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c @@ -0,0 +1,161 @@ +/* + * Linksys WRT400N board support + * + * Copyright (C) 2009-2012 Gabor Juhos + * Copyright (C) 2009 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "machtypes.h" + +#define WRT400N_GPIO_LED_POWER 1 +#define WRT400N_GPIO_LED_WPS_BLUE 4 +#define WRT400N_GPIO_LED_WPS_AMBER 5 +#define WRT400N_GPIO_LED_WLAN 6 + +#define WRT400N_GPIO_BTN_RESET 8 +#define WRT400N_GPIO_BTN_WLSEC 3 + +#define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL) + +#define WRT400N_MAC_ADDR_OFFSET 0x120c +#define WRT400N_CALDATA0_OFFSET 0x1000 +#define WRT400N_CALDATA1_OFFSET 0x5000 + +static struct mtd_partition wrt400n_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = 0x030000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "env", + .offset = 0x030000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "linux", + .offset = 0x040000, + .size = 0x140000, + }, { + .name = "rootfs", + .offset = 0x180000, + .size = 0x630000, + }, { + .name = "nvram", + .offset = 0x7b0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "factory", + .offset = 0x7c0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "language", + .offset = 0x7d0000, + .size = 0x020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "caldata", + .offset = 0x7f0000, + .size = 0x010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x040000, + .size = 0x770000, + } +}; + +static struct flash_platform_data wrt400n_flash_data = { + .parts = wrt400n_partitions, + .nr_parts = ARRAY_SIZE(wrt400n_partitions), +}; + +static struct gpio_led wrt400n_leds_gpio[] __initdata = { + { + .name = "wrt400n:blue:wps", + .gpio = WRT400N_GPIO_LED_WPS_BLUE, + .active_low = 1, + }, { + .name = "wrt400n:amber:wps", + .gpio = WRT400N_GPIO_LED_WPS_AMBER, + .active_low = 1, + }, { + .name = "wrt400n:blue:wlan", + .gpio = WRT400N_GPIO_LED_WLAN, + .active_low = 1, + }, { + .name = "wrt400n:blue:power", + .gpio = WRT400N_GPIO_LED_POWER, + .active_low = 0, + .default_trigger = "default-on", + } +}; + +static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, + .gpio = WRT400N_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "wlsec", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, + .gpio = WRT400N_GPIO_BTN_WLSEC, + .active_low = 1, + } +}; + +static void __init wrt400n_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac = art + WRT400N_MAC_ADDR_OFFSET; + + ath79_register_mdio(0, 0x0); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth0_data.speed = SPEED_100; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2); + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_m25p80(&wrt400n_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), + wrt400n_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wrt400n_gpio_keys), + wrt400n_gpio_keys); + + ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, + art + WRT400N_CALDATA1_OFFSET, NULL); +} + +MIPS_MACHINE(ATH79_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c new file mode 100644 index 0000000..428876f --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c @@ -0,0 +1,221 @@ +/* + * Buffalo WZR-450HP2 board support + * + * Copyright (c) 2013 Gabor Juhos + * + * Based on the Qualcomm Atheros AP135/AP136 reference board support code + * Copyright (c) 2012 Qualcomm Atheros + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-spi.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WZR_450HP2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZR_450HP2_KEYS_DEBOUNCE_INTERVAL (3 * WZR_450HP2_KEYS_POLL_INTERVAL) + +#define WZR_450HP2_WMAC_CALDATA_OFFSET 0x1000 + +static struct mtd_partition wzrhpg450h_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + }, { + .name = "ART", + .offset = 0x0ff0000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0050000, + .size = 0x0f90000, + }, { + .name = "user_property", + .offset = 0x0fe0000, + .size = 0x0010000, + } +}; + +static struct flash_platform_data wzr_450hp2_flash_data = { + .parts = wzrhpg450h_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions), +}; + +static struct gpio_led wzr_450hp2_leds_gpio[] __initdata = { + { + .name = "buffalo:green:wps", + .gpio = 3, + .active_low = 1, + }, + { + .name = "buffalo:green:system", + .gpio = 20, + .active_low = 1, + }, + { + .name = "buffalo:green:wlan", + .gpio = 18, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wzr_450hp2_gpio_keys[] __initdata = { + { + .desc = "Reset button", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZR_450HP2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 17, + .active_low = 1, + }, + { + .desc = "RFKILL button", + .type = EV_KEY, + .code = KEY_RFKILL, + .debounce_interval = WZR_450HP2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 21, + .active_low = 1, + }, +}; + +static const struct ar8327_led_info wzr_450hp2_leds_ar8327[] = { + AR8327_LED_INFO(PHY0_0, HW, "buffalo:green:lan1"), + AR8327_LED_INFO(PHY1_0, HW, "buffalo:green:lan2"), + AR8327_LED_INFO(PHY2_0, HW, "buffalo:green:lan3"), + AR8327_LED_INFO(PHY3_0, HW, "buffalo:green:lan4"), + AR8327_LED_INFO(PHY4_0, HW, "buffalo:green:wan"), +}; + +/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ +static struct ar8327_pad_cfg wzr_450hp2_ar8327_pad0_cfg = { + .mode = AR8327_PAD_MAC_SGMII, + .sgmii_delay_en = true, +}; + +/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ +static struct ar8327_pad_cfg wzr_450hp2_ar8327_pad6_cfg = { + .mode = AR8327_PAD_MAC_RGMII, + .txclk_delay_en = true, + .rxclk_delay_en = true, + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, +}; + +static struct ar8327_led_cfg wzr_450hp2_ar8327_led_cfg = { + .led_ctrl0 = 0xcc35cc35, + .led_ctrl1 = 0xca35ca35, + .led_ctrl2 = 0xc935c935, + .led_ctrl3 = 0x03ffff00, + .open_drain = true, +}; + +static struct ar8327_platform_data wzr_450hp2_ar8327_data = { + .pad0_cfg = &wzr_450hp2_ar8327_pad0_cfg, + .pad6_cfg = &wzr_450hp2_ar8327_pad6_cfg, + .port0_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .port6_cfg = { + .force_link = 1, + .speed = AR8327_PORT_SPEED_1000, + .duplex = 1, + .txpause = 1, + .rxpause = 1, + }, + .led_cfg = &wzr_450hp2_ar8327_led_cfg, + .num_leds = ARRAY_SIZE(wzr_450hp2_leds_ar8327), + .leds = wzr_450hp2_leds_ar8327, +}; + +static struct mdio_board_info wzr_450hp2_mdio0_info[] = { + { + .bus_id = "ag71xx-mdio.0", + .phy_addr = 0, + .platform_data = &wzr_450hp2_ar8327_data, + }, +}; + +static void __init wzr_450hp2_setup(void) +{ + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + u8 *mac_wan = art; + u8 *mac_lan = mac_wan + ETH_ALEN; + + ath79_register_m25p80(&wzr_450hp2_flash_data); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzr_450hp2_leds_gpio), + wzr_450hp2_leds_gpio); + ath79_register_gpio_keys_polled(-1, WZR_450HP2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzr_450hp2_gpio_keys), + wzr_450hp2_gpio_keys); + + ath79_register_wmac(art + WZR_450HP2_WMAC_CALDATA_OFFSET, mac_lan); + + mdiobus_register_board_info(wzr_450hp2_mdio0_info, + ARRAY_SIZE(wzr_450hp2_mdio0_info)); + ath79_register_mdio(0, 0x0); + + ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + + /* GMAC0 is connected to the RMGII interface */ + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.phy_mask = BIT(0); + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; + ath79_eth0_pll_data.pll_1000 = 0x56000000; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac_wan, 0); + ath79_register_eth(0); + + /* GMAC1 is connected to the SGMII interface */ + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; + ath79_eth1_data.speed = SPEED_1000; + ath79_eth1_data.duplex = DUPLEX_FULL; + ath79_eth1_pll_data.pll_1000 = 0x03000101; + + ath79_init_mac(ath79_eth1_data.mac_addr, mac_lan, 0); + ath79_register_eth(1); + + ath79_register_usb(); +} + +MIPS_MACHINE(ATH79_MACH_WZR_450HP2, "WZR-450HP2", + "Buffalo WZR-450HP2", wzr_450hp2_setup); + diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c new file mode 100644 index 0000000..edd48f2 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-ag300h.c @@ -0,0 +1,205 @@ +/* + * Buffalo WZR-HP-AG300H board support + * + * Copyright (C) 2011 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPAG300H_MAC_OFFSET 0x20c +#define WZRHPAG300H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPAG300H_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpag300h_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f90000, + }, { + .name = "user_property", + .offset = 0x1ff0000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct flash_platform_data wzrhpag300h_flash_data = { + .parts = wzrhpag300h_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpag300h_flash_partitions), +}; + +static struct gpio_led wzrhpag300h_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 1, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpag300h_wmac0_leds_gpio[] = { + { + .name = "buffalo:amber:band2g", + .gpio = 1, + .active_low = 1, + }, + { + .name = "buffalo:green:usb", + .gpio = 3, + .active_low = 1, + }, + { + .name = "buffalo:green:band2g", + .gpio = 5, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpag300h_wmac1_leds_gpio[] = { + { + .name = "buffalo:green:band5g", + .gpio = 1, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 3, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine", + .gpio = 4, + .active_low = 1, + }, + { + .name = "buffalo:amber:band5g", + .gpio = 5, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wzrhpag300h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 3, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 5, + .active_low = 1, + }, { + .desc = "router_auto", + .type = EV_SW, + .code = BTN_6, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 6, + .active_low = 1, + }, { + .desc = "router_off", + .type = EV_SW, + .code = BTN_5, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 1, + }, { + .desc = "movie_engine", + .type = EV_SW, + .code = BTN_7, + .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 1, + } +}; + +static void __init wzrhpag300h_setup(void) +{ + u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000); + u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000); + u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET; + u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 1); + + ath79_register_mdio(0, ~(BIT(0) | BIT(4))); + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = BIT(4); + + ath79_register_eth(0); + ath79_register_eth(1); + + gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio), + wzrhpag300h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpag300h_gpio_keys), + wzrhpag300h_gpio_keys); + + ath79_register_m25p80_multi(&wzrhpag300h_flash_data); + + ap94_pci_init(eeprom1, mac1, eeprom2, mac2); + + ap9x_pci_setup_wmac_led_pin(0, 1); + ap9x_pci_setup_wmac_led_pin(1, 5); + + ap9x_pci_setup_wmac_leds(0, wzrhpag300h_wmac0_leds_gpio, + ARRAY_SIZE(wzrhpag300h_wmac0_leds_gpio)); + ap9x_pci_setup_wmac_leds(1, wzrhpag300h_wmac1_leds_gpio, + ARRAY_SIZE(wzrhpag300h_wmac1_leds_gpio)); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_AG300H, "WZR-HP-AG300H", + "Buffalo WZR-HP-AG300H/WZR-600DHP", wzrhpag300h_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c new file mode 100644 index 0000000..0a3eba9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh.c @@ -0,0 +1,279 @@ +/* + * Buffalo WZR-HP-G300NH board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "dev-wmac.h" +#include "machtypes.h" + +#define WZRHPG300NH_GPIO_LED_USB 0 +#define WZRHPG300NH_GPIO_LED_DIAG 1 +#define WZRHPG300NH_GPIO_LED_WIRELESS 6 +#define WZRHPG300NH_GPIO_LED_SECURITY 17 +#define WZRHPG300NH_GPIO_LED_ROUTER 18 + +#define WZRHPG300NH_GPIO_RTL8366_SDA 19 +#define WZRHPG300NH_GPIO_RTL8366_SCK 20 + +#define WZRHPG300NH_GPIO_74HC153_S0 9 +#define WZRHPG300NH_GPIO_74HC153_S1 11 +#define WZRHPG300NH_GPIO_74HC153_1Y 12 +#define WZRHPG300NH_GPIO_74HC153_2Y 14 + +#define WZRHPG300NH_GPIO_EXP_BASE 32 +#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) +#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) +#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) +#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) +#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) +#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) +#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) + +#define WZRHPG300NH_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH_KEYS_POLL_INTERVAL) + +#define WZRHPG300NH_MAC_OFFSET 0x20c + +static struct mtd_partition wzrhpg300nh_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f60000, + }, { + .name = "user_property", + .offset = 0x1fc0000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x1fe0000, + .size = 0x0020000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct physmap_flash_data wzrhpg300nh_flash_data = { + .width = 2, + .parts = wzrhpg300nh_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), +}; + +#define WZRHPG300NH_FLASH_BASE 0x1e000000 +#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) + +static struct resource wzrhpg300nh_flash_resources[] = { + [0] = { + .start = WZRHPG300NH_FLASH_BASE, + .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device wzrhpg300nh_flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = wzrhpg300nh_flash_resources, + .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), + .dev = { + .platform_data = &wzrhpg300nh_flash_data, + } +}; + +static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { + { + .name = "buffalo:orange:security", + .gpio = WZRHPG300NH_GPIO_LED_SECURITY, + .active_low = 1, + }, { + .name = "buffalo:green:wireless", + .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, + .active_low = 1, + }, { + .name = "buffalo:green:router", + .gpio = WZRHPG300NH_GPIO_LED_ROUTER, + .active_low = 1, + }, { + .name = "buffalo:red:diag", + .gpio = WZRHPG300NH_GPIO_LED_DIAG, + .active_low = 1, + }, { + .name = "buffalo:blue:usb", + .gpio = WZRHPG300NH_GPIO_LED_USB, + .active_low = 1, + } +}; + +static struct gpio_keys_button wzrhpg300nh_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_RESET, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_AOSS, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_USB, + .active_low = 1, + }, { + .desc = "qos_on", + .type = EV_KEY, + .code = BTN_3, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, + .active_low = 0, + }, { + .desc = "qos_off", + .type = EV_KEY, + .code = BTN_4, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, + .active_low = 0, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, + .active_low = 0, + }, { + .desc = "router_auto", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, + .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, + .active_low = 0, + } +}; + +static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { + .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, + .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, + .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, + .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, + .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, +}; + +static struct platform_device wzrhpg300nh_74hc153_device = { + .name = NXP_74HC153_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_74hc153_data, + } +}; + +static struct rtl8366_platform_data wzrhpg300nh_rtl8366_data = { + .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, + .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, +}; + +static struct platform_device wzrhpg300nh_rtl8366s_device = { + .name = RTL8366S_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_rtl8366_data, + } +}; + +static struct platform_device wzrhpg300nh_rtl8366rb_device = { + .name = RTL8366RB_DRIVER_NAME, + .id = -1, + .dev = { + .platform_data = &wzrhpg300nh_rtl8366_data, + } +}; + +static void __init wzrhpg300nh_setup(void) +{ + u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + u8 *mac = eeprom + WZRHPG300NH_MAC_OFFSET; + bool hasrtl8366rb = false; + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + if (rtl8366_smi_detect(&wzrhpg300nh_rtl8366_data) == RTL8366_TYPE_RB) + hasrtl8366rb = true; + + if (hasrtl8366rb) { + ath79_eth0_pll_data.pll_1000 = 0x1f000000; + ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; + ath79_eth1_pll_data.pll_1000 = 0x100; + ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; + } else { + ath79_eth0_pll_data.pll_1000 = 0x1e000100; + ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; + ath79_eth1_pll_data.pll_1000 = 0x1e000100; + ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; + } + + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth1_data.phy_mask = 0x10; + + ath79_register_eth(0); + ath79_register_eth(1); + + ath79_register_usb(); + ath79_register_wmac(eeprom, NULL); + + platform_device_register(&wzrhpg300nh_74hc153_device); + platform_device_register(&wzrhpg300nh_flash_device); + + if (hasrtl8366rb) + platform_device_register(&wzrhpg300nh_rtl8366rb_device); + else + platform_device_register(&wzrhpg300nh_rtl8366s_device); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), + wzrhpg300nh_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPG300NH_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg300nh_gpio_keys), + wzrhpg300nh_gpio_keys); + +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", + "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c new file mode 100644 index 0000000..733d996 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g300nh2.c @@ -0,0 +1,170 @@ +/* + * Buffalo WZR-HP-G300NH2 board support + * + * Copyright (C) 2011 Felix Fietkau + * Copyright (C) 2011 Mark Deneen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include "dev-ap9x-pci.h" +#include "dev-eth.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-m25p80.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPG300NH2_MAC_OFFSET 0x20c +#define WZRHPG300NH2_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH2_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpg300nh2_flash_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "art", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f90000, + }, { + .name = "user_property", + .offset = 0x1ff0000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct flash_platform_data wzrhpg300nh2_flash_data = { + .parts = wzrhpg300nh2_flash_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg300nh2_flash_partitions), +}; + +static struct gpio_led wzrhpg300nh2_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 16, + .active_low = 1, + }, +}; + +static struct gpio_led wzrhpg300nh2_wmac_leds_gpio[] = { + { + .name = "buffalo:blue:usb", + .gpio = 4, + .active_low = 1, + }, + { + .name = "buffalo:orange:security", + .gpio = 6, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 7, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine_on", + .gpio = 8, + .active_low = 1, + }, + { + .name = "buffalo:blue:movie_engine_off", + .gpio = 9, + .active_low = 1, + }, +}; + +/* The AOSS button is wmac gpio 12 */ +static struct gpio_keys_button wzrhpg300nh2_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 1, + }, { + .desc = "qos", + .type = EV_KEY, + .code = BTN_3, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 11, + .active_low = 0, + }, { + .desc = "router_on", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 0, + }, +}; + +static void __init wzrhpg300nh2_setup(void) +{ + + u8 *eeprom = (u8 *) KSEG1ADDR(0x1f051000); + u8 *mac0 = eeprom + WZRHPG300NH2_MAC_OFFSET; + /* There is an eth1 but it is not connected to the switch */ + + ath79_register_m25p80_multi(&wzrhpg300nh2_flash_data); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + ath79_register_mdio(0, ~(BIT(0))); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_eth(0); + + /* gpio13 is usb power. Turn it on. */ + gpio_request_one(13, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh2_leds_gpio), + wzrhpg300nh2_leds_gpio); + ath79_register_gpio_keys_polled(-1, WZRHPG300NH2_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg300nh2_gpio_keys), + wzrhpg300nh2_gpio_keys); + ap9x_pci_setup_wmac_led_pin(0, 5); + ap9x_pci_setup_wmac_leds(0, wzrhpg300nh2_wmac_leds_gpio, + ARRAY_SIZE(wzrhpg300nh2_wmac_leds_gpio)); + + ap91_pci_init(eeprom, mac0); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH2, "WZR-HP-G300NH2", + "Buffalo WZR-HP-G300NH2", wzrhpg300nh2_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c new file mode 100644 index 0000000..a559d73 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-hp-g450h.c @@ -0,0 +1,165 @@ +/* + * Buffalo WZR-HP-G450G board support + * + * Copyright (C) 2011 Felix Fietkau + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include + +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "dev-usb.h" +#include "machtypes.h" + +#define WZRHPG450H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define WZRHPG450H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG450H_KEYS_POLL_INTERVAL) + +static struct mtd_partition wzrhpg450h_partitions[] = { + { + .name = "u-boot", + .offset = 0, + .size = 0x0040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "u-boot-env", + .offset = 0x0040000, + .size = 0x0010000, + }, { + .name = "ART", + .offset = 0x0050000, + .size = 0x0010000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "firmware", + .offset = 0x0060000, + .size = 0x1f80000, + }, { + .name = "user_property", + .offset = 0x1fe0000, + .size = 0x0020000, + } +}; + +static struct flash_platform_data wzrhpg450h_flash_data = { + .parts = wzrhpg450h_partitions, + .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions), +}; + +static struct gpio_led wzrhpg450h_leds_gpio[] __initdata = { + { + .name = "buffalo:red:diag", + .gpio = 14, + .active_low = 1, + }, + { + .name = "buffalo:orange:security", + .gpio = 13, + .active_low = 1, + }, +}; + + +static struct gpio_led wzrhpg450h_wmac_leds_gpio[] = { + { + .name = "buffalo:blue:movie_engine", + .gpio = 13, + .active_low = 1, + }, + { + .name = "buffalo:green:router", + .gpio = 14, + .active_low = 1, + }, +}; + +static struct gpio_keys_button wzrhpg450h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 6, + .active_low = 1, + }, { + .desc = "usb", + .type = EV_KEY, + .code = BTN_2, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 1, + .active_low = 1, + }, { + .desc = "aoss", + .type = EV_KEY, + .code = KEY_WPS_BUTTON, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 8, + .active_low = 1, + }, { + .desc = "movie_engine", + .type = EV_KEY, + .code = BTN_6, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 7, + .active_low = 0, + }, { + .desc = "router_off", + .type = EV_KEY, + .code = BTN_5, + .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL, + .gpio = 12, + .active_low = 0, + } +}; + + +static void __init wzrhpg450h_init(void) +{ + u8 *ee = (u8 *) KSEG1ADDR(0x1f051000); + u8 *mac = (u8 *) ee + 2; + + ath79_register_m25p80_multi(&wzrhpg450h_flash_data); + + ath79_register_mdio(0, ~BIT(0)); + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; + ath79_eth0_data.speed = SPEED_1000; + ath79_eth0_data.duplex = DUPLEX_FULL; + ath79_eth0_data.phy_mask = BIT(0); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg450h_leds_gpio), + wzrhpg450h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, WZRHPG450H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(wzrhpg450h_gpio_keys), + wzrhpg450h_gpio_keys); + + ath79_register_eth(0); + + gpio_request_one(16, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, + "USB power"); + ath79_register_usb(); + + ap91_pci_init(ee, NULL); + ap9x_pci_get_wmac_data(0)->tx_gain_buffalo = true; + ap9x_pci_get_wmac_data(1)->tx_gain_buffalo = true; + ap9x_pci_setup_wmac_led_pin(0, 15); + ap9x_pci_setup_wmac_leds(0, wzrhpg450h_wmac_leds_gpio, + ARRAY_SIZE(wzrhpg450h_wmac_leds_gpio)); +} + +MIPS_MACHINE(ATH79_MACH_WZR_HP_G450H, "WZR-HP-G450H", "Buffalo WZR-HP-G450H", + wzrhpg450h_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c new file mode 100644 index 0000000..bc79ab9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-zcn-1523h.c @@ -0,0 +1,154 @@ +/* + * Zcomax ZCN-1523H-2-8/5-16 board support + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "common.h" +#include "dev-eth.h" +#include "dev-m25p80.h" +#include "dev-ap9x-pci.h" +#include "dev-gpio-buttons.h" +#include "dev-leds-gpio.h" +#include "machtypes.h" + +#define ZCN_1523H_GPIO_BTN_RESET 0 +#define ZCN_1523H_GPIO_LED_INIT 11 +#define ZCN_1523H_GPIO_LED_LAN1 17 + +#define ZCN_1523H_2_GPIO_LED_WEAK 13 +#define ZCN_1523H_2_GPIO_LED_MEDIUM 14 +#define ZCN_1523H_2_GPIO_LED_STRONG 15 + +#define ZCN_1523H_5_GPIO_LAN2_POWER 1 +#define ZCN_1523H_5_GPIO_LED_LAN2 13 +#define ZCN_1523H_5_GPIO_LED_WEAK 14 +#define ZCN_1523H_5_GPIO_LED_MEDIUM 15 +#define ZCN_1523H_5_GPIO_LED_STRONG 16 + +#define ZCN_1523H_KEYS_POLL_INTERVAL 20 /* msecs */ +#define ZCN_1523H_KEYS_DEBOUNCE_INTERVAL (3 * ZCN_1523H_KEYS_POLL_INTERVAL) + +static struct gpio_keys_button zcn_1523h_gpio_keys[] __initdata = { + { + .desc = "reset", + .type = EV_KEY, + .code = KEY_RESTART, + .debounce_interval = ZCN_1523H_KEYS_DEBOUNCE_INTERVAL, + .gpio = ZCN_1523H_GPIO_BTN_RESET, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:amber:init", + .gpio = ZCN_1523H_GPIO_LED_INIT, + .active_low = 1, + }, { + .name = "zcn-1523h:green:lan1", + .gpio = ZCN_1523H_GPIO_LED_LAN1, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_2_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:red:weak", + .gpio = ZCN_1523H_2_GPIO_LED_WEAK, + .active_low = 1, + }, { + .name = "zcn-1523h:amber:medium", + .gpio = ZCN_1523H_2_GPIO_LED_MEDIUM, + .active_low = 1, + }, { + .name = "zcn-1523h:green:strong", + .gpio = ZCN_1523H_2_GPIO_LED_STRONG, + .active_low = 1, + } +}; + +static struct gpio_led zcn_1523h_5_leds_gpio[] __initdata = { + { + .name = "zcn-1523h:red:weak", + .gpio = ZCN_1523H_5_GPIO_LED_WEAK, + .active_low = 1, + }, { + .name = "zcn-1523h:amber:medium", + .gpio = ZCN_1523H_5_GPIO_LED_MEDIUM, + .active_low = 1, + }, { + .name = "zcn-1523h:green:strong", + .gpio = ZCN_1523H_5_GPIO_LED_STRONG, + .active_low = 1, + }, { + .name = "zcn-1523h:green:lan2", + .gpio = ZCN_1523H_5_GPIO_LED_LAN2, + .active_low = 1, + } +}; + +static void __init zcn_1523h_generic_setup(void) +{ + u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0004); + u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + + ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | + AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + + ath79_register_m25p80(NULL); + + ath79_register_leds_gpio(0, ARRAY_SIZE(zcn_1523h_leds_gpio), + zcn_1523h_leds_gpio); + + ath79_register_gpio_keys_polled(-1, ZCN_1523H_KEYS_POLL_INTERVAL, + ARRAY_SIZE(zcn_1523h_gpio_keys), + zcn_1523h_gpio_keys); + + ap91_pci_init(ee, mac); + + ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); + ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1); + + ath79_register_mdio(0, 0x0); + + /* LAN1 port */ + ath79_register_eth(0); +} + +static void __init zcn_1523h_2_setup(void) +{ + zcn_1523h_generic_setup(); + ap9x_pci_setup_wmac_gpio(0, BIT(9), 0); + + ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_2_leds_gpio), + zcn_1523h_2_leds_gpio); +} + +MIPS_MACHINE(ATH79_MACH_ZCN_1523H_2, "ZCN-1523H-2", "Zcomax ZCN-1523H-2", + zcn_1523h_2_setup); + +static void __init zcn_1523h_5_setup(void) +{ + zcn_1523h_generic_setup(); + ap9x_pci_setup_wmac_gpio(0, BIT(8), 0); + + ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_5_leds_gpio), + zcn_1523h_5_leds_gpio); + + /* LAN2 port */ + ath79_register_eth(1); +} + +MIPS_MACHINE(ATH79_MACH_ZCN_1523H_5, "ZCN-1523H-5", "Zcomax ZCN-1523H-5", + zcn_1523h_5_setup); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/nvram.c b/target/linux/ar71xx/files/arch/mips/ath79/nvram.c new file mode 100644 index 0000000..e55af5a --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/nvram.c @@ -0,0 +1,80 @@ +/* + * Atheros AR71xx minimal nvram support + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "nvram.h" + +char *ath79_nvram_find_var(const char *name, const char *buf, unsigned buf_len) +{ + unsigned len = strlen(name); + char *cur, *last; + + if (buf_len == 0 || len == 0) + return NULL; + + if (buf_len < len) + return NULL; + + if (len == 1) + return memchr(buf, (int) *name, buf_len); + + last = (char *) buf + buf_len - len; + for (cur = (char *) buf; cur <= last; cur++) + if (cur[0] == name[0] && memcmp(cur, name, len) == 0) + return cur + len; + + return NULL; +} + +int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, + const char *name, char *mac) +{ + char *buf; + char *mac_str; + int ret; + int t; + + buf = vmalloc(nvram_len); + if (!buf) + return -ENOMEM; + + memcpy(buf, nvram, nvram_len); + buf[nvram_len - 1] = '\0'; + + mac_str = ath79_nvram_find_var(name, buf, nvram_len); + if (!mac_str) { + ret = -EINVAL; + goto free; + } + + if (strlen(mac_str) == 19 && mac_str[0] == '"' && mac_str[18] == '"') { + mac_str[18] = 0; + mac_str++; + } + + t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + + if (t != 6) { + ret = -EINVAL; + goto free; + } + + ret = 0; + +free: + vfree(buf); + return ret; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/nvram.h b/target/linux/ar71xx/files/arch/mips/ath79/nvram.h new file mode 100644 index 0000000..75151d4 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/nvram.h @@ -0,0 +1,19 @@ +/* + * Atheros AR71xx minimal nvram support + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_NVRAM_H +#define _ATH79_NVRAM_H + +char *ath79_nvram_find_var(const char *name, const char *buf, + unsigned buf_len); +int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, + const char *name, char *mac); + +#endif /* _ATH79_NVRAM_H */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c new file mode 100644 index 0000000..2202351 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.c @@ -0,0 +1,126 @@ +/* + * Atheros AP94 reference board PCI initialization + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include +#include + +struct ath9k_fixup { + u16 *cal_data; + unsigned slot; +}; + +static int ath9k_num_fixups; +static struct ath9k_fixup ath9k_fixups[2]; + +static void ath9k_pci_fixup(struct pci_dev *dev) +{ + void __iomem *mem; + u16 *cal_data = NULL; + u16 cmd; + u32 bar0; + u32 val; + unsigned i; + + for (i = 0; i < ath9k_num_fixups; i++) { + if (ath9k_fixups[i].cal_data == NULL) + continue; + + if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) + continue; + + cal_data = ath9k_fixups[i].cal_data; + break; + } + + if (cal_data == NULL) + return; + + if (*cal_data != 0xa55a) { + pr_err("pci %s: invalid calibration data\n", pci_name(dev)); + return; + } + + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); + + mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); + if (!mem) { + pr_err("pci %s: ioremap error\n", pci_name(dev)); + return; + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + + switch (ath79_soc) { + case ATH79_SOC_AR7161: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, + AR71XX_PCI_MEM_BASE); + break; + case ATH79_SOC_AR7240: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); + break; + + case ATH79_SOC_AR7241: + case ATH79_SOC_AR7242: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff); + break; + case ATH79_SOC_AR9344: + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff); + break; + + default: + BUG(); + } + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, cmd); + + /* set pointer to first reg address */ + cal_data += 3; + while (*cal_data != 0xffff) { + u32 reg; + reg = *cal_data++; + val = *cal_data++; + val |= (*cal_data++) << 16; + + __raw_writel(val, mem + reg); + udelay(100); + } + + pci_read_config_dword(dev, PCI_VENDOR_ID, &val); + dev->vendor = val & 0xffff; + dev->device = (val >> 16) & 0xffff; + + pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); + dev->revision = val & 0xff; + dev->class = val >> 8; /* upper 3 bytes */ + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config_word(dev, PCI_COMMAND, cmd); + + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); + + iounmap(mem); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + +void __init pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) +{ + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; + ath9k_fixups[ath9k_num_fixups].cal_data = cal_data; + ath9k_num_fixups++; +} diff --git a/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h new file mode 100644 index 0000000..5794941 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/pci-ath9k-fixup.h @@ -0,0 +1,6 @@ +#ifndef _PCI_ATH9K_FIXUP +#define _PCI_ATH9K_FIXUP + +void pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) __init; + +#endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c new file mode 100644 index 0000000..76776e1 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.c @@ -0,0 +1,358 @@ +/* + * RouterBoot helper routines + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define pr_fmt(fmt) "rb: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include "routerboot.h" + +#define RB_BLOCK_SIZE 0x1000 +#define RB_ART_SIZE 0x10000 +#define RB_MAGIC_ERD 0x00455244 /* extended radio data */ + +static struct rb_info rb_info; + +static u32 get_u32(void *buf) +{ + u8 *p = buf; + + return ((u32) p[3] + ((u32) p[2] << 8) + ((u32) p[1] << 16) + + ((u32) p[0] << 24)); +} + +static u16 get_u16(void *buf) +{ + u8 *p = buf; + + return (u16) p[1] + ((u16) p[0] << 8); +} + +__init int +routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard) +{ + u32 magic_ref = hard ? RB_MAGIC_HARD : RB_MAGIC_SOFT; + u32 magic; + u32 cur = *offset; + + while (cur < buflen) { + magic = get_u32(buf + cur); + if (magic == magic_ref) { + *offset = cur; + return 0; + } + + cur += 0x1000; + } + + return -ENOENT; +} + +__init int +routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len) +{ + uint32_t magic; + bool align = false; + int ret; + + if (buflen < 4) + return -EINVAL; + + magic = get_u32(buf); + switch (magic) { + case RB_MAGIC_ERD: + align = true; + /* fall trough */ + case RB_MAGIC_HARD: + /* skip magic value */ + buf += 4; + buflen -= 4; + break; + + case RB_MAGIC_SOFT: + if (buflen < 8) + return -EINVAL; + + /* skip magic and CRC value */ + buf += 8; + buflen -= 8; + + break; + + default: + return -EINVAL; + } + + ret = -ENOENT; + while (buflen > 2) { + u16 id; + u16 len; + + len = get_u16(buf); + buf += 2; + buflen -= 2; + + if (buflen < 2) + break; + + id = get_u16(buf); + buf += 2; + buflen -= 2; + + if (id == RB_ID_TERMINATOR) + break; + + if (buflen < len) + break; + + if (id == tag_id) { + if (tag_len) + *tag_len = len; + if (tag_data) + *tag_data = buf; + ret = 0; + break; + } + + if (align) + len = (len + 3) / 4; + + buf += len; + buflen -= len; + } + + return ret; +} + +static inline int +rb_find_hard_cfg_tag(u16 tag_id, u8 **tag_data, u16 *tag_len) +{ + if (!rb_info.hard_cfg_data || + !rb_info.hard_cfg_size) + return -ENOENT; + + return routerboot_find_tag(rb_info.hard_cfg_data, + rb_info.hard_cfg_size, + tag_id, tag_data, tag_len); +} + +__init const char * +rb_get_board_name(void) +{ + u16 tag_len; + u8 *tag; + int err; + + err = rb_find_hard_cfg_tag(RB_ID_BOARD_NAME, &tag, &tag_len); + if (err) + return NULL; + + return tag; +} + +__init u32 +rb_get_hw_options(void) +{ + u16 tag_len; + u8 *tag; + int err; + + err = rb_find_hard_cfg_tag(RB_ID_HW_OPTIONS, &tag, &tag_len); + if (err) + return 0; + + return get_u32(tag); +} + +static void * __init +__rb_get_wlan_data(u16 id) +{ + u16 tag_len; + u8 *tag; + void *buf; + int err; + u32 magic; + size_t src_done; + size_t dst_done; + + err = rb_find_hard_cfg_tag(RB_ID_WLAN_DATA, &tag, &tag_len); + if (err) { + pr_err("no calibration data found\n"); + goto err; + } + + buf = kmalloc(RB_ART_SIZE, GFP_KERNEL); + if (buf == NULL) { + pr_err("no memory for calibration data\n"); + goto err; + } + + magic = get_u32(tag); + if (magic == RB_MAGIC_ERD) { + u8 *erd_data; + u16 erd_len; + + if (id == 0) + goto err_free; + + err = routerboot_find_tag(tag, tag_len, id, + &erd_data, &erd_len); + if (err) { + pr_err("no ERD data found for id %u\n", id); + goto err_free; + } + + dst_done = RB_ART_SIZE; + err = lzo1x_decompress_safe(erd_data, erd_len, buf, &dst_done); + if (err) { + pr_err("unable to decompress calibration data %d\n", + err); + goto err_free; + } + } else { + if (id != 0) + goto err_free; + + err = rle_decode((char *) tag, tag_len, buf, RB_ART_SIZE, + &src_done, &dst_done); + if (err) { + pr_err("unable to decode calibration data\n"); + goto err_free; + } + } + + return buf; + +err_free: + kfree(buf); +err: + return NULL; +} + +__init void * +rb_get_wlan_data(void) +{ + return __rb_get_wlan_data(0); +} + +__init void * +rb_get_ext_wlan_data(u16 id) +{ + return __rb_get_wlan_data(id); +} + +__init const struct rb_info * +rb_init_info(void *data, unsigned int size) +{ + unsigned int offset; + + if (size == 0 || (size % RB_BLOCK_SIZE) != 0) + return NULL; + + for (offset = 0; offset < size; offset += RB_BLOCK_SIZE) { + u32 magic; + + magic = get_u32(data + offset); + switch (magic) { + case RB_MAGIC_HARD: + rb_info.hard_cfg_offs = offset; + break; + + case RB_MAGIC_SOFT: + rb_info.soft_cfg_offs = offset; + break; + } + } + + if (!rb_info.hard_cfg_offs) { + pr_err("could not find a valid RouterBOOT hard config\n"); + return NULL; + } + + if (!rb_info.soft_cfg_offs) { + pr_err("could not find a valid RouterBOOT soft config\n"); + return NULL; + } + + rb_info.hard_cfg_size = RB_BLOCK_SIZE; + rb_info.hard_cfg_data = kmemdup(data + rb_info.hard_cfg_offs, + RB_BLOCK_SIZE, GFP_KERNEL); + if (!rb_info.hard_cfg_data) + return NULL; + + rb_info.board_name = rb_get_board_name(); + rb_info.hw_options = rb_get_hw_options(); + + return &rb_info; +} + +static char *rb_ext_wlan_data; + +static ssize_t +rb_ext_wlan_data_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, char *buf, + loff_t off, size_t count) +{ + if (off + count > attr->size) + return -EFBIG; + + memcpy(buf, &rb_ext_wlan_data[off], count); + + return count; +} + +static const struct bin_attribute rb_ext_wlan_data_attr = { + .attr = { + .name = "ext_wlan_data", + .mode = S_IRUSR | S_IWUSR, + }, + .read = rb_ext_wlan_data_read, + .size = RB_ART_SIZE, +}; + +static int __init rb_sysfs_init(void) +{ + struct kobject *rb_kobj; + int ret; + + rb_ext_wlan_data = rb_get_ext_wlan_data(1); + if (rb_ext_wlan_data == NULL) + return -ENOENT; + + rb_kobj = kobject_create_and_add("routerboot", firmware_kobj); + if (rb_kobj == NULL) { + ret = -ENOMEM; + pr_err("unable to create sysfs entry\n"); + goto err_free_wlan_data; + } + + ret = sysfs_create_bin_file(rb_kobj, &rb_ext_wlan_data_attr); + if (ret) { + pr_err("unable to create sysfs file, %d\n", ret); + goto err_put_kobj; + } + + return 0; + +err_put_kobj: + kobject_put(rb_kobj); +err_free_wlan_data: + kfree(rb_ext_wlan_data); + return ret; +} + +late_initcall(rb_sysfs_init); diff --git a/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h new file mode 100644 index 0000000..c1d7fb9 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/ath79/routerboot.h @@ -0,0 +1,63 @@ +/* + * RouterBoot definitions + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _ATH79_ROUTERBOOT_H_ +#define _ATH79_ROUTERBOOT_H_ + +struct rb_info { + unsigned int hard_cfg_offs; + unsigned int hard_cfg_size; + void *hard_cfg_data; + unsigned int soft_cfg_offs; + + const char *board_name; + u32 hw_options; +}; + +#ifdef CONFIG_ATH79_ROUTERBOOT +const struct rb_info *rb_init_info(void *data, unsigned int size); +void *rb_get_wlan_data(void); +void *rb_get_ext_wlan_data(u16 id); + +int routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len); +int routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard); +#else +static inline const struct rb_info * +rb_init_info(void *data, unsigned int size) +{ + return NULL; +} + +static inline void *rb_get_wlan_data(void) +{ + return NULL; +} + +static inline void *rb_get_wlan_data(u16 id) +{ + return NULL; +} + +static inline int +routerboot_find_tag(u8 *buf, unsigned int buflen, u16 tag_id, + u8 **tag_data, u16 *tag_len) +{ + return -ENOENT; +} + +static inline int +routerboot_find_magic(u8 *buf, unsigned int buflen, u32 *offset, bool hard) +{ + return -ENOENT; +} +#endif + +#endif /* _ATH79_ROUTERBOOT_H_ */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h b/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h new file mode 100644 index 0000000..8a99d56 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/fw/myloader/myloader.h @@ -0,0 +1,34 @@ +/* + * Compex's MyLoader specific definitions + * + * Copyright (C) 2006-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ASM_MIPS_FW_MYLOADER_H +#define _ASM_MIPS_FW_MYLOADER_H + +#include + +struct myloader_info { + uint32_t vid; + uint32_t did; + uint32_t svid; + uint32_t sdid; + uint8_t macs[MYLO_ETHADDR_COUNT][6]; +}; + +#ifdef CONFIG_MYLOADER +extern struct myloader_info *myloader_get_info(void) __init; +#else +static inline struct myloader_info *myloader_get_info(void) +{ + return NULL; +} +#endif /* CONFIG_MYLOADER */ + +#endif /* _ASM_MIPS_FW_MYLOADER_H */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h new file mode 100644 index 0000000..d46dc4e --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h @@ -0,0 +1,65 @@ +/* + * Atheros AR71xx SoC specific platform data definitions + * + * Copyright (C) 2008-2012 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ATH79_PLATFORM_H +#define __ASM_MACH_ATH79_PLATFORM_H + +#include +#include +#include +#include + +struct ag71xx_switch_platform_data { + u8 phy4_mii_en:1; + u8 phy_poll_mask; +}; + +struct ag71xx_platform_data { + phy_interface_t phy_if_mode; + u32 phy_mask; + int speed; + int duplex; + u32 reset_bit; + u8 mac_addr[ETH_ALEN]; + struct device *mii_bus_dev; + + u8 has_gbit:1; + u8 is_ar91xx:1; + u8 is_ar7240:1; + u8 is_ar724x:1; + u8 has_ar8216:1; + + struct ag71xx_switch_platform_data *switch_data; + + void (*ddr_flush)(void); + void (*set_speed)(int speed); + + u32 fifo_cfg1; + u32 fifo_cfg2; + u32 fifo_cfg3; + + unsigned int max_frame_len; + unsigned int desc_pktlen_mask; +}; + +struct ag71xx_mdio_platform_data { + u32 phy_mask; + u8 builtin_switch:1; + u8 is_ar7240:1; + u8 is_ar9330:1; + u8 is_ar934x:1; + unsigned long mdio_clock; + unsigned long ref_clock; + + void (*reset)(struct mii_bus *bus); +}; + +#endif /* __ASM_MACH_ATH79_PLATFORM_H */ diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h new file mode 100644 index 0000000..50d5a20 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/mach-rb750.h @@ -0,0 +1,84 @@ +/* + * MikroTik RouterBOARD 750 definitions + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ +#ifndef _MACH_RB750_H +#define _MACH_RB750_H + +#include + +#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ +#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ +#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ +#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ +#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ +#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ +#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ +#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ +#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ +#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ +#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ +#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ +#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ +#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ +#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ + +#define RB750_GPIO_BTN_RESET 1 +#define RB750_GPIO_SPI_CS0 2 +#define RB750_GPIO_LED_ACT 12 +#define RB750_GPIO_LED_PORT1 13 +#define RB750_GPIO_LED_PORT2 14 +#define RB750_GPIO_LED_PORT3 15 +#define RB750_GPIO_LED_PORT4 16 +#define RB750_GPIO_LED_PORT5 17 + +#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) +#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) +#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) +#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) +#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) +#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) +#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) + +#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) + +#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ + RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) + +#define RB7XX_GPIO_NAND_NCE 0 +#define RB7XX_GPIO_MON 9 +#define RB7XX_GPIO_LED_ACT 11 +#define RB7XX_GPIO_USB_POWERON 13 + +#define RB7XX_NAND_NCE BIT(RB7XX_GPIO_NAND_NCE) +#define RB7XX_LED_ACT BIT(RB7XX_GPIO_LED_ACT) +#define RB7XX_MONITOR BIT(RB7XX_GPIO_MON) +#define RB7XX_USB_POWERON BIT(RB7XX_GPIO_USB_POWERON) + +struct rb750_led_data { + char *name; + char *default_trigger; + u32 mask; + int active_low; +}; + +struct rb750_led_platform_data { + int num_leds; + struct rb750_led_data *leds; + void (*latch_change)(u32 clear, u32 set); +}; + +struct rb7xx_nand_platform_data { + u32 nce_line; + + void (*enable_pins)(void); + void (*disable_pins)(void); + void (*latch_change)(u32, u32); +}; + +#endif /* _MACH_RB750_H */ \ No newline at end of file diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h new file mode 100644 index 0000000..5b17e94 --- /dev/null +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/rb4xx_cpld.h @@ -0,0 +1,48 @@ +/* + * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#define CPLD_GPIO_nLED1 0 +#define CPLD_GPIO_nLED2 1 +#define CPLD_GPIO_nLED3 2 +#define CPLD_GPIO_nLED4 3 +#define CPLD_GPIO_FAN 4 +#define CPLD_GPIO_ALE 5 +#define CPLD_GPIO_CLE 6 +#define CPLD_GPIO_nCE 7 +#define CPLD_GPIO_nLED5 8 + +#define CPLD_NUM_GPIOS 9 + +#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1) +#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2) +#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3) +#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4) +#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN) +#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE) +#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE) +#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE) +#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5) + +struct rb4xx_cpld_platform_data { + unsigned gpio_base; +}; + +extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value); +extern int rb4xx_cpld_read(unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_read_from(unsigned addr, + unsigned char *rx_buf, + const unsigned char *verify_buf, + unsigned cnt); +extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count); diff --git a/target/linux/ar71xx/files/drivers/gpio/gpio-latch.c b/target/linux/ar71xx/files/drivers/gpio/gpio-latch.c new file mode 100644 index 0000000..d911f6a --- /dev/null +++ b/target/linux/ar71xx/files/drivers/gpio/gpio-latch.c @@ -0,0 +1,220 @@ +/* + * GPIO latch driver + * + * Copyright (C) 2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct gpio_latch_chip { + struct gpio_chip gc; + + struct mutex mutex; + struct mutex latch_mutex; + bool latch_enabled; + int le_gpio; + bool le_active_low; + int *gpios; +}; + +static inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc) +{ + return container_of(gc, struct gpio_latch_chip, gc); +} + +static void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable) +{ + mutex_lock(&glc->mutex); + + if (enable) + glc->latch_enabled = true; + + if (glc->latch_enabled) + mutex_lock(&glc->latch_mutex); +} + +static void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable) +{ + if (glc->latch_enabled) + mutex_unlock(&glc->latch_mutex); + + if (disable) + glc->latch_enabled = true; + + mutex_unlock(&glc->mutex); +} + +static int +gpio_latch_get(struct gpio_chip *gc, unsigned offset) +{ + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc); + int ret; + + gpio_latch_lock(glc, false); + ret = gpio_get_value(glc->gpios[offset]); + gpio_latch_unlock(glc, false); + + return ret; +} + +static void +gpio_latch_set(struct gpio_chip *gc, unsigned offset, int value) +{ + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc); + bool enable_latch = false; + bool disable_latch = false; + int gpio; + + gpio = glc->gpios[offset]; + + if (gpio == glc->le_gpio) { + enable_latch = value ^ glc->le_active_low; + disable_latch = !enable_latch; + } + + gpio_latch_lock(glc, enable_latch); + gpio_set_value(gpio, value); + gpio_latch_unlock(glc, disable_latch); +} + +static int +gpio_latch_direction_input(struct gpio_chip *gc, unsigned offset) +{ + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc); + int ret; + + gpio_latch_lock(glc, false); + ret = gpio_direction_input(glc->gpios[offset]); + gpio_latch_unlock(glc, false); + + return ret; +} + +static int +gpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value) +{ + struct gpio_latch_chip *glc = to_gpio_latch_chip(gc); + bool enable_latch = false; + bool disable_latch = false; + int gpio; + int ret; + + gpio = glc->gpios[offset]; + + if (gpio == glc->le_gpio) { + enable_latch = value ^ glc->le_active_low; + disable_latch = !enable_latch; + } + + gpio_latch_lock(glc, enable_latch); + ret = gpio_direction_output(gpio, value); + gpio_latch_unlock(glc, disable_latch); + + return ret; +} + +static int gpio_latch_probe(struct platform_device *pdev) +{ + struct gpio_latch_chip *glc; + struct gpio_latch_platform_data *pdata; + struct gpio_chip *gc; + int size; + int ret; + int i; + + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) + return -EINVAL; + + if (pdata->le_gpio_index >= pdata->num_gpios || + !pdata->num_gpios || + !pdata->gpios) + return -EINVAL; + + for (i = 0; i < pdata->num_gpios; i++) { + int gpio = pdata->gpios[i]; + + ret = devm_gpio_request(&pdev->dev, gpio, + GPIO_LATCH_DRIVER_NAME); + if (ret) + return ret; + } + + glc = devm_kzalloc(&pdev->dev, sizeof(*glc), GFP_KERNEL); + if (!glc) + return -ENOMEM; + + mutex_init(&glc->mutex); + mutex_init(&glc->latch_mutex); + + size = pdata->num_gpios * sizeof(glc->gpios[0]); + glc->gpios = devm_kzalloc(&pdev->dev, size , GFP_KERNEL); + if (!glc->gpios) + return -ENOMEM; + + memcpy(glc->gpios, pdata->gpios, size); + + glc->le_gpio = glc->gpios[pdata->le_gpio_index]; + glc->le_active_low = pdata->le_active_low; + + gc = &glc->gc; + + gc->label = GPIO_LATCH_DRIVER_NAME; + gc->base = pdata->base; + gc->can_sleep = true; + gc->ngpio = pdata->num_gpios; + gc->get = gpio_latch_get; + gc->set = gpio_latch_set; + gc->direction_input = gpio_latch_direction_input, + gc->direction_output = gpio_latch_direction_output; + + platform_set_drvdata(pdev, glc); + + ret = gpiochip_add(&glc->gc); + if (ret) + return ret; + + return 0; +} + +static int gpio_latch_remove(struct platform_device *pdev) +{ + struct gpio_latch_chip *glc = platform_get_drvdata(pdev); + + gpiochip_remove(&glc->gc); + return 0; +} + + +static struct platform_driver gpio_latch_driver = { + .probe = gpio_latch_probe, + .remove = gpio_latch_remove, + .driver = { + .name = GPIO_LATCH_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init gpio_latch_init(void) +{ + return platform_driver_register(&gpio_latch_driver); +} + +postcore_initcall(gpio_latch_init); + +MODULE_DESCRIPTION("GPIO latch driver"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" GPIO_LATCH_DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c b/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c new file mode 100644 index 0000000..8c01efe --- /dev/null +++ b/target/linux/ar71xx/files/drivers/gpio/gpio-nxp-74hc153.c @@ -0,0 +1,251 @@ +/* + * NXP 74HC153 - Dual 4-input multiplexer GPIO driver + * + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define NXP_74HC153_NUM_GPIOS 8 +#define NXP_74HC153_S0_MASK 0x1 +#define NXP_74HC153_S1_MASK 0x2 +#define NXP_74HC153_BANK_MASK 0x4 + +struct nxp_74hc153_chip { + struct device *parent; + struct gpio_chip gpio_chip; + struct mutex lock; +}; + +static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) +{ + return container_of(gc, struct nxp_74hc153_chip, gpio_chip); +} + +static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) +{ + return 0; +} + +static int nxp_74hc153_direction_output(struct gpio_chip *gc, + unsigned offset, int val) +{ + return -EINVAL; +} + +static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) +{ + struct nxp_74hc153_chip *nxp; + struct nxp_74hc153_platform_data *pdata; + unsigned s0; + unsigned s1; + unsigned pin; + int ret; + + nxp = gpio_to_nxp(gc); + pdata = nxp->parent->platform_data; + + s0 = !!(offset & NXP_74HC153_S0_MASK); + s1 = !!(offset & NXP_74HC153_S1_MASK); + pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y + : pdata->gpio_pin_1y; + + mutex_lock(&nxp->lock); + gpio_set_value(pdata->gpio_pin_s0, s0); + gpio_set_value(pdata->gpio_pin_s1, s1); + ret = gpio_get_value(pin); + mutex_unlock(&nxp->lock); + + return ret; +} + +static void nxp_74hc153_set_value(struct gpio_chip *gc, + unsigned offset, int val) +{ + /* not supported */ +} + +static int nxp_74hc153_probe(struct platform_device *pdev) +{ + struct nxp_74hc153_platform_data *pdata; + struct nxp_74hc153_chip *nxp; + struct gpio_chip *gc; + int err; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) { + dev_dbg(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); + if (nxp == NULL) { + dev_err(&pdev->dev, "no memory for private data\n"); + return -ENOMEM; + } + + err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_s0, err); + goto err_free_nxp; + } + + err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_s1, err); + goto err_free_s0; + } + + err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_1y, err); + goto err_free_s1; + } + + err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); + if (err) { + dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", + pdata->gpio_pin_2y, err); + goto err_free_1y; + } + + err = gpio_direction_output(pdata->gpio_pin_s0, 0); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_s0, err); + goto err_free_2y; + } + + err = gpio_direction_output(pdata->gpio_pin_s1, 0); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_s1, err); + goto err_free_2y; + } + + err = gpio_direction_input(pdata->gpio_pin_1y); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_1y, err); + goto err_free_2y; + } + + err = gpio_direction_input(pdata->gpio_pin_2y); + if (err) { + dev_err(&pdev->dev, + "unable to set direction of gpio %u, err=%d\n", + pdata->gpio_pin_2y, err); + goto err_free_2y; + } + + nxp->parent = &pdev->dev; + mutex_init(&nxp->lock); + + gc = &nxp->gpio_chip; + + gc->direction_input = nxp_74hc153_direction_input; + gc->direction_output = nxp_74hc153_direction_output; + gc->get = nxp_74hc153_get_value; + gc->set = nxp_74hc153_set_value; + gc->can_sleep = 1; + + gc->base = pdata->gpio_base; + gc->ngpio = NXP_74HC153_NUM_GPIOS; + gc->label = dev_name(nxp->parent); + gc->dev = nxp->parent; + gc->owner = THIS_MODULE; + + err = gpiochip_add(&nxp->gpio_chip); + if (err) { + dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); + goto err_free_2y; + } + + platform_set_drvdata(pdev, nxp); + return 0; + +err_free_2y: + gpio_free(pdata->gpio_pin_2y); +err_free_1y: + gpio_free(pdata->gpio_pin_1y); +err_free_s1: + gpio_free(pdata->gpio_pin_s1); +err_free_s0: + gpio_free(pdata->gpio_pin_s0); +err_free_nxp: + kfree(nxp); + return err; +} + +static int nxp_74hc153_remove(struct platform_device *pdev) +{ + struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); + struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; + + if (nxp) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) + int err; + + err = gpiochip_remove(&nxp->gpio_chip); + if (err) { + dev_err(&pdev->dev, + "unable to remove gpio chip, err=%d\n", + err); + return err; + } +#else + gpiochip_remove(&nxp->gpio_chip); +#endif + gpio_free(pdata->gpio_pin_2y); + gpio_free(pdata->gpio_pin_1y); + gpio_free(pdata->gpio_pin_s1); + gpio_free(pdata->gpio_pin_s0); + + kfree(nxp); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver nxp_74hc153_driver = { + .probe = nxp_74hc153_probe, + .remove = nxp_74hc153_remove, + .driver = { + .name = NXP_74HC153_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init nxp_74hc153_init(void) +{ + return platform_driver_register(&nxp_74hc153_driver); +} +subsys_initcall(nxp_74hc153_init); + +static void __exit nxp_74hc153_exit(void) +{ + platform_driver_unregister(&nxp_74hc153_driver); +} +module_exit(nxp_74hc153_exit); + +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/leds/leds-rb750.c b/target/linux/ar71xx/files/drivers/leds/leds-rb750.c new file mode 100644 index 0000000..79e98b4 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/leds/leds-rb750.c @@ -0,0 +1,144 @@ +/* + * LED driver for the RouterBOARD 750 + * + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_NAME "leds-rb750" + +struct rb750_led_dev { + struct led_classdev cdev; + u32 mask; + int active_low; + void (*latch_change)(u32 clear, u32 set); +}; + +struct rb750_led_drvdata { + struct rb750_led_dev *led_devs; + int num_leds; +}; + +static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) +{ + return (struct rb750_led_dev *)container_of(led_cdev, + struct rb750_led_dev, cdev); +} + +static void rb750_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct rb750_led_dev *rbled = to_rbled(led_cdev); + int level; + + level = (value == LED_OFF) ? 0 : 1; + level ^= rbled->active_low; + + if (level) + rbled->latch_change(0, rbled->mask); + else + rbled->latch_change(rbled->mask, 0); +} + +static int rb750_led_probe(struct platform_device *pdev) +{ + struct rb750_led_platform_data *pdata; + struct rb750_led_drvdata *drvdata; + int ret = 0; + int i; + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + + sizeof(struct rb750_led_dev) * pdata->num_leds, + GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->num_leds = pdata->num_leds; + drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; + + for (i = 0; i < drvdata->num_leds; i++) { + struct rb750_led_dev *rbled = &drvdata->led_devs[i]; + struct rb750_led_data *led_data = &pdata->leds[i]; + + rbled->cdev.name = led_data->name; + rbled->cdev.default_trigger = led_data->default_trigger; + rbled->cdev.brightness_set = rb750_led_brightness_set; + rbled->cdev.brightness = LED_OFF; + + rbled->mask = led_data->mask; + rbled->active_low = !!led_data->active_low; + rbled->latch_change = pdata->latch_change; + + ret = led_classdev_register(&pdev->dev, &rbled->cdev); + if (ret) + goto err; + } + + platform_set_drvdata(pdev, drvdata); + return 0; + +err: + for (i = i - 1; i >= 0; i--) + led_classdev_unregister(&drvdata->led_devs[i].cdev); + + kfree(drvdata); + return ret; +} + +static int rb750_led_remove(struct platform_device *pdev) +{ + struct rb750_led_drvdata *drvdata; + int i; + + drvdata = platform_get_drvdata(pdev); + for (i = 0; i < drvdata->num_leds; i++) + led_classdev_unregister(&drvdata->led_devs[i].cdev); + + kfree(drvdata); + return 0; +} + +static struct platform_driver rb750_led_driver = { + .probe = rb750_led_probe, + .remove = rb750_led_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS("platform:leds-rb750"); + +static int __init rb750_led_init(void) +{ + return platform_driver_register(&rb750_led_driver); +} + +static void __exit rb750_led_exit(void) +{ + platform_driver_unregister(&rb750_led_driver); +} + +module_init(rb750_led_init); +module_exit(rb750_led_exit); + +MODULE_DESCRIPTION(DRV_NAME); +MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c b/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c new file mode 100644 index 0000000..6425b05 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/leds/leds-wndr3700-usb.c @@ -0,0 +1,76 @@ +/* + * USB LED driver for the NETGEAR WNDR3700 + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +#define DRIVER_NAME "wndr3700-led-usb" + +static void wndr3700_usb_led_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + if (brightness) + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); + else + ath79_device_reset_set(AR71XX_RESET_GE1_PHY); +} + +static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) +{ + return ath79_device_reset_get(AR71XX_RESET_GE1_PHY) ? LED_OFF : LED_FULL; +} + +static struct led_classdev wndr3700_usb_led = { + .name = "netgear:green:usb", + .brightness_set = wndr3700_usb_led_set, + .brightness_get = wndr3700_usb_led_get, +}; + +static int wndr3700_usb_led_probe(struct platform_device *pdev) +{ + return led_classdev_register(&pdev->dev, &wndr3700_usb_led); +} + +static int wndr3700_usb_led_remove(struct platform_device *pdev) +{ + led_classdev_unregister(&wndr3700_usb_led); + return 0; +} + +static struct platform_driver wndr3700_usb_led_driver = { + .probe = wndr3700_usb_led_probe, + .remove = wndr3700_usb_led_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init wndr3700_usb_led_init(void) +{ + return platform_driver_register(&wndr3700_usb_led_driver); +} + +static void __exit wndr3700_usb_led_exit(void) +{ + platform_driver_unregister(&wndr3700_usb_led_driver); +} + +module_init(wndr3700_usb_led_init); +module_exit(wndr3700_usb_led_exit); + +MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/mtd/cybertan_part.c b/target/linux/ar71xx/files/drivers/mtd/cybertan_part.c new file mode 100644 index 0000000..7c6dad8 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/cybertan_part.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2009 Christian Daniel + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * TRX flash partition table. + * Based on ar7 map by Felix Fietkau + * + */ + +#include +#include +#include +#include + +#include +#include + +struct cybertan_header { + char magic[4]; + u8 res1[4]; + char fw_date[3]; + char fw_ver[3]; + char id[4]; + char hw_ver; + char unused; + u8 flags[2]; + u8 res2[10]; +}; + +#define TRX_PARTS 6 +#define TRX_MAGIC 0x30524448 +#define TRX_MAX_OFFSET 3 + +struct trx_header { + uint32_t magic; /* "HDR0" */ + uint32_t len; /* Length of file including header */ + uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ + uint32_t flag_version; /* 0:15 flags, 16:31 version */ + uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ +}; + +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ + +struct uimage_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data» Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +}; + +struct firmware_header { + struct cybertan_header cybertan; + struct trx_header trx; + struct uimage_header uimage; +} __packed; + +#define UBOOT_LEN 0x40000 +#define ART_LEN 0x10000 +#define NVRAM_LEN 0x10000 + +static int cybertan_parse_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct firmware_header *header; + struct trx_header *theader; + struct uimage_header *uheader; + struct mtd_partition *trx_parts; + size_t retlen; + unsigned int kernel_len; + unsigned int uboot_len; + unsigned int nvram_len; + unsigned int art_len; + int ret; + + uboot_len = max_t(unsigned int, master->erasesize, UBOOT_LEN); + nvram_len = max_t(unsigned int, master->erasesize, NVRAM_LEN); + art_len = max_t(unsigned int, master->erasesize, ART_LEN); + + trx_parts = kzalloc(TRX_PARTS * sizeof(struct mtd_partition), + GFP_KERNEL); + if (!trx_parts) { + ret = -ENOMEM; + goto out; + } + + header = vmalloc(sizeof(*header)); + if (!header) { + return -ENOMEM; + goto free_parts; + } + + ret = mtd_read(master, uboot_len, sizeof(*header), + &retlen, (void *) header); + if (ret) + goto free_hdr; + + if (retlen != sizeof(*header)) { + ret = -EIO; + goto free_hdr; + } + + theader = &header->trx; + if (le32_to_cpu(theader->magic) != TRX_MAGIC) { + printk(KERN_NOTICE "%s: no TRX header found\n", master->name); + goto free_hdr; + } + + uheader = &header->uimage; + if (uheader->ih_magic != IH_MAGIC) { + printk(KERN_NOTICE "%s: no uImage found\n", master->name); + goto free_hdr; + } + + kernel_len = le32_to_cpu(theader->offsets[1]) + + sizeof(struct cybertan_header); + + trx_parts[0].name = "u-boot"; + trx_parts[0].offset = 0; + trx_parts[0].size = uboot_len; + trx_parts[0].mask_flags = MTD_WRITEABLE; + + trx_parts[1].name = "kernel"; + trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; + trx_parts[1].size = kernel_len; + trx_parts[1].mask_flags = 0; + + trx_parts[2].name = "rootfs"; + trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; + trx_parts[2].size = master->size - uboot_len - nvram_len - art_len - + trx_parts[1].size; + trx_parts[2].mask_flags = 0; + + trx_parts[3].name = "nvram"; + trx_parts[3].offset = master->size - nvram_len - art_len; + trx_parts[3].size = nvram_len; + trx_parts[3].mask_flags = MTD_WRITEABLE; + + trx_parts[4].name = "art"; + trx_parts[4].offset = master->size - art_len; + trx_parts[4].size = art_len; + trx_parts[4].mask_flags = MTD_WRITEABLE; + + trx_parts[5].name = "firmware"; + trx_parts[5].offset = uboot_len; + trx_parts[5].size = master->size - uboot_len - nvram_len - art_len; + trx_parts[5].mask_flags = 0; + + vfree(header); + + *pparts = trx_parts; + return TRX_PARTS; + +free_hdr: + vfree(header); +free_parts: + kfree(trx_parts); +out: + return ret; +} + +static struct mtd_part_parser cybertan_parser = { + .owner = THIS_MODULE, + .parse_fn = cybertan_parse_partitions, + .name = "cybertan", +}; + +static int __init cybertan_parser_init(void) +{ + register_mtd_parser(&cybertan_parser); + + return 0; +} + +module_init(cybertan_parser_init); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Christian Daniel "); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c b/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c new file mode 100644 index 0000000..90ba03a --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/ar934x_nfc.c @@ -0,0 +1,1508 @@ +/* + * Driver for the built-in NAND controller of the Atheros AR934x SoCs + * + * Copyright (C) 2011-2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define AR934X_NFC_REG_CMD 0x00 +#define AR934X_NFC_REG_CTRL 0x04 +#define AR934X_NFC_REG_STATUS 0x08 +#define AR934X_NFC_REG_INT_MASK 0x0c +#define AR934X_NFC_REG_INT_STATUS 0x10 +#define AR934X_NFC_REG_ECC_CTRL 0x14 +#define AR934X_NFC_REG_ECC_OFFSET 0x18 +#define AR934X_NFC_REG_ADDR0_0 0x1c +#define AR934X_NFC_REG_ADDR0_1 0x24 +#define AR934X_NFC_REG_ADDR1_0 0x20 +#define AR934X_NFC_REG_ADDR1_1 0x28 +#define AR934X_NFC_REG_SPARE_SIZE 0x30 +#define AR934X_NFC_REG_PROTECT 0x38 +#define AR934X_NFC_REG_LOOKUP_EN 0x40 +#define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4) +#define AR934X_NFC_REG_DMA_ADDR 0x64 +#define AR934X_NFC_REG_DMA_COUNT 0x68 +#define AR934X_NFC_REG_DMA_CTRL 0x6c +#define AR934X_NFC_REG_MEM_CTRL 0x80 +#define AR934X_NFC_REG_DATA_SIZE 0x84 +#define AR934X_NFC_REG_READ_STATUS 0x88 +#define AR934X_NFC_REG_TIME_SEQ 0x8c +#define AR934X_NFC_REG_TIMINGS_ASYN 0x90 +#define AR934X_NFC_REG_TIMINGS_SYN 0x94 +#define AR934X_NFC_REG_FIFO_DATA 0x98 +#define AR934X_NFC_REG_TIME_MODE 0x9c +#define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0 +#define AR934X_NFC_REG_FIFO_INIT 0xb0 +#define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4 + +#define AR934X_NFC_CMD_CMD_SEQ_S 0 +#define AR934X_NFC_CMD_CMD_SEQ_M 0x3f +#define AR934X_NFC_CMD_SEQ_1C 0x00 +#define AR934X_NFC_CMD_SEQ_ERASE 0x0e +#define AR934X_NFC_CMD_SEQ_12 0x0c +#define AR934X_NFC_CMD_SEQ_1C1AXR 0x21 +#define AR934X_NFC_CMD_SEQ_S 0x24 +#define AR934X_NFC_CMD_SEQ_1C3AXR 0x27 +#define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a +#define AR934X_NFC_CMD_SEQ_18 0x32 +#define AR934X_NFC_CMD_INPUT_SEL_SIU 0 +#define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6) +#define AR934X_NFC_CMD_ADDR_SEL_0 0 +#define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7) +#define AR934X_NFC_CMD_CMD0_S 8 +#define AR934X_NFC_CMD_CMD0_M 0xff +#define AR934X_NFC_CMD_CMD1_S 16 +#define AR934X_NFC_CMD_CMD1_M 0xff +#define AR934X_NFC_CMD_CMD2_S 24 +#define AR934X_NFC_CMD_CMD2_M 0xff + +#define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7 +#define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0 +#define AR934X_NFC_CTRL_SPARE_EN BIT(3) +#define AR934X_NFC_CTRL_INT_EN BIT(4) +#define AR934X_NFC_CTRL_ECC_EN BIT(5) +#define AR934X_NFC_CTRL_BLOCK_SIZE_S 6 +#define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3 +#define AR934X_NFC_CTRL_BLOCK_SIZE_32 0 +#define AR934X_NFC_CTRL_BLOCK_SIZE_64 1 +#define AR934X_NFC_CTRL_BLOCK_SIZE_128 2 +#define AR934X_NFC_CTRL_BLOCK_SIZE_256 3 +#define AR934X_NFC_CTRL_PAGE_SIZE_S 8 +#define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7 +#define AR934X_NFC_CTRL_PAGE_SIZE_256 0 +#define AR934X_NFC_CTRL_PAGE_SIZE_512 1 +#define AR934X_NFC_CTRL_PAGE_SIZE_1024 2 +#define AR934X_NFC_CTRL_PAGE_SIZE_2048 3 +#define AR934X_NFC_CTRL_PAGE_SIZE_4096 4 +#define AR934X_NFC_CTRL_PAGE_SIZE_8192 5 +#define AR934X_NFC_CTRL_PAGE_SIZE_16384 6 +#define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11) +#define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0 +#define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12) +#define AR934X_NFC_CTRL_LOOKUP_EN BIT(13) +#define AR934X_NFC_CTRL_PROT_EN BIT(14) +#define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0 +#define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15) +#define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16) +#define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17) +#define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7 +#define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18 +#define AR934X_NFC_CTRL_SMALL_PAGE BIT(21) + +#define AR934X_NFC_DMA_CTRL_DMA_START BIT(7) +#define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0 +#define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6) +#define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5) +#define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4 +#define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5 +#define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1) +#define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0) + +#define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x)) +#define AR934X_NFC_INT_CMD_END BIT(1) + +#define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8 +#define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f +#define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6 +#define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7 +#define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2) +#define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1) +#define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0) + +#define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff + +/* default timing values */ +#define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff +#define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22 +#define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf + +#define AR934X_NFC_ID_BUF_SIZE 8 +#define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */ +#define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */ +#define AR934X_NFC_DONE_TIMEOUT 1000 +#define AR934X_NFC_DMA_RETRIES 20 + +#define AR934X_NFC_USE_IRQ true +#define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0) + +#define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043 + +#undef AR934X_NFC_DEBUG_DATA +#undef AR934X_NFC_DEBUG + +struct ar934x_nfc; + +static inline __attribute__ ((format (printf, 2, 3))) +void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...) +{ +} + +#ifdef AR934X_NFC_DEBUG +#define nfc_dbg(_nfc, fmt, ...) \ + dev_info((_nfc)->parent, fmt, ##__VA_ARGS__) +#else +#define nfc_dbg(_nfc, fmt, ...) \ + _nfc_dbg((_nfc), fmt, ##__VA_ARGS__) +#endif /* AR934X_NFC_DEBUG */ + +#ifdef AR934X_NFC_DEBUG_DATA +static void +nfc_debug_data(const char *label, void *data, int len) +{ + print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1, + data, len, 0); +} +#else +static inline void +nfc_debug_data(const char *label, void *data, int len) {} +#endif /* AR934X_NFC_DEBUG_DATA */ + +struct ar934x_nfc { + struct mtd_info mtd; + struct nand_chip nand_chip; + struct device *parent; + void __iomem *base; + void (*select_chip)(int chip_no); + bool swap_dma; + int irq; + wait_queue_head_t irq_waitq; + + bool spurious_irq_expected; + u32 irq_status; + + u32 ctrl_reg; + u32 ecc_ctrl_reg; + u32 ecc_offset_reg; + u32 ecc_thres; + u32 ecc_oob_pos; + + bool small_page; + unsigned int addr_count0; + unsigned int addr_count1; + + u8 *buf; + dma_addr_t buf_dma; + unsigned int buf_size; + int buf_index; + + bool read_id; + + int erase1_page_addr; + + int rndout_page_addr; + int rndout_read_cmd; + + int seqin_page_addr; + int seqin_column; + int seqin_read_cmd; +}; + +static void ar934x_nfc_restart(struct ar934x_nfc *nfc); + +static inline bool +is_all_ff(u8 *buf, int len) +{ + while (len--) + if (buf[len] != 0xff) + return false; + + return true; +} + +static inline void +ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val) +{ + __raw_writel(val, nfc->base + reg); +} + +static inline u32 +ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg) +{ + return __raw_readl(nfc->base + reg); +} + +static inline struct ar934x_nfc_platform_data * +ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc) +{ + return nfc->parent->platform_data; +} + +static inline struct +ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd) +{ + return container_of(mtd, struct ar934x_nfc, mtd); +} + +static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc) +{ + return AR934X_NFC_USE_IRQ; +} + +static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg) +{ + wmb(); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD); +} + +static bool +__ar934x_nfc_dev_ready(struct ar934x_nfc *nfc) +{ + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS); + return (status & 0xff) == 0xff; +} + +static inline bool +__ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc) +{ + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL); + return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0; +} + +static int +ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc) +{ + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT); + do { + if (__ar934x_nfc_dev_ready(nfc)) + return 0; + } while time_before(jiffies, timeout); + + nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n", + ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS), + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS)); + return -ETIMEDOUT; +} + +static int +ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc) +{ + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT); + do { + if (__ar934x_nfc_is_dma_ready(nfc)) + return 0; + } while time_before(jiffies, timeout); + + nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n", + ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL)); + return -ETIMEDOUT; +} + +static int +ar934x_nfc_wait_irq(struct ar934x_nfc *nfc) +{ + long timeout; + int ret; + + timeout = wait_event_timeout(nfc->irq_waitq, + (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0, + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT)); + + ret = 0; + if (!timeout) { + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + nfc_dbg(nfc, + "timeout waiting for interrupt, status:%08x\n", + nfc->irq_status); + ret = -ETIMEDOUT; + } + + nfc->irq_status = 0; + return ret; +} + +static int +ar934x_nfc_wait_done(struct ar934x_nfc *nfc) +{ + int ret; + + if (ar934x_nfc_use_irq(nfc)) + ret = ar934x_nfc_wait_irq(nfc); + else + ret = ar934x_nfc_wait_dev_ready(nfc); + + if (ret) + return ret; + + return ar934x_nfc_wait_dma_ready(nfc); +} + +static int +ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size) +{ + nfc->buf = dma_alloc_coherent(nfc->parent, size, + &nfc->buf_dma, GFP_KERNEL); + if (nfc->buf == NULL) { + dev_err(nfc->parent, "no memory for DMA buffer\n"); + return -ENOMEM; + } + + nfc->buf_size = size; + nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size); + + return 0; +} + +static void +ar934x_nfc_free_buf(struct ar934x_nfc *nfc) +{ + dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma); +} + +static void +ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr, + u32 *addr0, u32 *addr1) +{ + u32 a0, a1; + + a0 = 0; + a1 = 0; + + if (column == -1) { + /* ERASE1 */ + a0 = (page_addr & 0xffff) << 16; + a1 = (page_addr >> 16) & 0xf; + } else if (page_addr != -1) { + /* SEQIN, READ0, etc.. */ + + /* TODO: handle 16bit bus width */ + if (nfc->small_page) { + a0 = column & 0xff; + a0 |= (page_addr & 0xff) << 8; + a0 |= ((page_addr >> 8) & 0xff) << 16; + a0 |= ((page_addr >> 16) & 0xff) << 24; + } else { + a0 = column & 0x0FFF; + a0 |= (page_addr & 0xffff) << 16; + + if (nfc->addr_count0 > 4) + a1 = (page_addr >> 16) & 0xf; + } + } + + *addr0 = a0; + *addr1 = a1; +} + +static void +ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command) +{ + u32 cmd_reg; + + cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 | + AR934X_NFC_CMD_SEQ_1C; + cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); +} + +static int +ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr, + int len, u32 cmd_reg, u32 ctrl_reg, bool write) +{ + u32 addr0, addr1; + u32 dma_ctrl; + int dir; + int err; + int retries = 0; + + WARN_ON(len & 3); + + if (WARN_ON(len > nfc->buf_size)) + dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size); + + if (write) { + dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE; + dir = DMA_TO_DEVICE; + } else { + dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ; + dir = DMA_FROM_DEVICE; + } + + ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1); + + dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START | + (AR934X_NFC_DMA_CTRL_DMA_BURST_3 << + AR934X_NFC_DMA_CTRL_DMA_BURST_S); + + cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0; + ctrl_reg |= AR934X_NFC_CTRL_INT_EN; + + nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n", + (write) ? "write" : "read", + addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg); + +retry: + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg); + + if (ar934x_nfc_use_irq(nfc)) { + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK); + } + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + err = ar934x_nfc_wait_done(nfc); + if (err) { + dev_dbg(nfc->parent, "%s operation stuck at page %d\n", + (write) ? "write" : "read", page_addr); + + ar934x_nfc_restart(nfc); + if (retries++ < AR934X_NFC_DMA_RETRIES) + goto retry; + + dev_err(nfc->parent, "%s operation failed on page %d\n", + (write) ? "write" : "read", page_addr); + } + + return err; +} + +static int +ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command) +{ + u32 cmd_reg; + int err; + + nfc_dbg(nfc, "readid, cmd:%02x\n", command); + + cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR; + cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + err = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE, + cmd_reg, nfc->ctrl_reg, false); + + nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE); + + return err; +} + +static int +ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr, int len) +{ + u32 cmd_reg; + int err; + + nfc_dbg(nfc, "read, column=%d page=%d len=%d\n", + column, page_addr, len); + + cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S; + + if (nfc->small_page) { + cmd_reg |= AR934X_NFC_CMD_SEQ_18; + } else { + cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR; + } + + err = ar934x_nfc_do_rw_command(nfc, column, page_addr, len, + cmd_reg, nfc->ctrl_reg, false); + + nfc_debug_data("[data] ", nfc->buf, len); + + return err; +} + +static void +ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr) +{ + u32 addr0, addr1; + u32 ctrl_reg; + u32 cmd_reg; + + ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1); + + ctrl_reg = nfc->ctrl_reg; + if (nfc->small_page) { + /* override number of address cycles for the erase command */ + ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M << + AR934X_NFC_CTRL_ADDR_CYCLE0_S); + ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M << + AR934X_NFC_CTRL_ADDR_CYCLE1_S); + ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE); + ctrl_reg |= (nfc->addr_count0 + 1) << + AR934X_NFC_CTRL_ADDR_CYCLE0_S; + } + + cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= command << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE; + + nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n", + page_addr, addr0, addr1, cmd_reg, ctrl_reg); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); +} + +static int +ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column, + int page_addr, int len) +{ + u32 cmd_reg; + + nfc_dbg(nfc, "write, column=%d page=%d len=%d\n", + column, page_addr, len); + + nfc_debug_data("[data] ", nfc->buf, len); + + cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= command << AR934X_NFC_CMD_CMD1_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_12; + + return ar934x_nfc_do_rw_command(nfc, column, page_addr, len, + cmd_reg, nfc->ctrl_reg, true); +} + +static void +ar934x_nfc_read_status(struct ar934x_nfc *nfc) +{ + u32 cmd_reg; + u32 status; + + cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S; + cmd_reg |= AR934X_NFC_CMD_SEQ_S; + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_write_cmd_reg(nfc, cmd_reg); + ar934x_nfc_wait_dev_ready(nfc); + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS); + + nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n", + cmd_reg, (status & 0xff)); + + if (nfc->swap_dma) + nfc->buf[0 ^ 3] = status; + else + nfc->buf[0] = status; +} + +static void +ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column, + int page_addr) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + struct nand_chip *nand = mtd->priv; + + nfc->read_id = false; + if (command != NAND_CMD_PAGEPROG) + nfc->buf_index = 0; + + switch (command) { + case NAND_CMD_RESET: + ar934x_nfc_send_cmd(nfc, command); + break; + + case NAND_CMD_READID: + nfc->read_id = true; + ar934x_nfc_send_readid(nfc, command); + break; + + case NAND_CMD_READ0: + case NAND_CMD_READ1: + if (nfc->small_page) { + ar934x_nfc_send_read(nfc, command, column, page_addr, + mtd->writesize + mtd->oobsize); + } else { + ar934x_nfc_send_read(nfc, command, 0, page_addr, + mtd->writesize + mtd->oobsize); + nfc->buf_index = column; + nfc->rndout_page_addr = page_addr; + nfc->rndout_read_cmd = command; + } + break; + + case NAND_CMD_READOOB: + if (nfc->small_page) + ar934x_nfc_send_read(nfc, NAND_CMD_READOOB, + column, page_addr, + mtd->oobsize); + else + ar934x_nfc_send_read(nfc, NAND_CMD_READ0, + mtd->writesize, page_addr, + mtd->oobsize); + break; + + case NAND_CMD_RNDOUT: + if (WARN_ON(nfc->small_page)) + break; + + /* emulate subpage read */ + ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0, + nfc->rndout_page_addr, + mtd->writesize + mtd->oobsize); + nfc->buf_index = column; + break; + + case NAND_CMD_ERASE1: + nfc->erase1_page_addr = page_addr; + break; + + case NAND_CMD_ERASE2: + ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr); + break; + + case NAND_CMD_STATUS: + ar934x_nfc_read_status(nfc); + break; + + case NAND_CMD_SEQIN: + if (nfc->small_page) { + /* output read command */ + if (column >= mtd->writesize) { + column -= mtd->writesize; + nfc->seqin_read_cmd = NAND_CMD_READOOB; + } else if (column < 256) { + nfc->seqin_read_cmd = NAND_CMD_READ0; + } else { + column -= 256; + nfc->seqin_read_cmd = NAND_CMD_READ1; + } + } else { + nfc->seqin_read_cmd = NAND_CMD_READ0; + } + nfc->seqin_column = column; + nfc->seqin_page_addr = page_addr; + break; + + case NAND_CMD_PAGEPROG: + if (nand->ecc.mode == NAND_ECC_HW) { + /* the data is already written */ + break; + } + + if (nfc->small_page) + ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd); + + ar934x_nfc_send_write(nfc, command, nfc->seqin_column, + nfc->seqin_page_addr, + nfc->buf_index); + break; + + default: + dev_err(nfc->parent, + "unsupported command: %x, column:%d page_addr=%d\n", + command, column, page_addr); + break; + } +} + +static int +ar934x_nfc_dev_ready(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + return __ar934x_nfc_dev_ready(nfc); +} + +static void +ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + if (nfc->select_chip) + nfc->select_chip(chip_no); +} + +static u8 +ar934x_nfc_read_byte(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + u8 data; + + WARN_ON(nfc->buf_index >= nfc->buf_size); + + if (nfc->swap_dma || nfc->read_id) + data = nfc->buf[nfc->buf_index ^ 3]; + else + data = nfc->buf[nfc->buf_index]; + + nfc->buf_index++; + + return data; +} + +static void +ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int i; + + WARN_ON(nfc->buf_index + len > nfc->buf_size); + + if (nfc->swap_dma) { + for (i = 0; i < len; i++) { + nfc->buf[nfc->buf_index ^ 3] = buf[i]; + nfc->buf_index++; + } + } else { + for (i = 0; i < len; i++) { + nfc->buf[nfc->buf_index] = buf[i]; + nfc->buf_index++; + } + } +} + +static void +ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int buf_index; + int i; + + WARN_ON(nfc->buf_index + len > nfc->buf_size); + + buf_index = nfc->buf_index; + + if (nfc->swap_dma || nfc->read_id) { + for (i = 0; i < len; i++) { + buf[i] = nfc->buf[buf_index ^ 3]; + buf_index++; + } + } else { + for (i = 0; i < len; i++) { + buf[i] = nfc->buf[buf_index]; + buf_index++; + } + } + + nfc->buf_index = buf_index; +} + +static inline void +ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc) +{ + nfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN; + nfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN; +} + +static inline void +ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc) +{ + nfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN; + nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN; +} + +static int +ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int err; + + nfc_dbg(nfc, "read_oob: page:%d\n", page); + + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page, + mtd->oobsize); + if (err) + return err; + + memcpy(chip->oob_poi, nfc->buf, mtd->oobsize); + + return 0; +} + +static int +ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + + nfc_dbg(nfc, "write_oob: page:%d\n", page); + + memcpy(nfc->buf, chip->oob_poi, mtd->oobsize); + + return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize, + page, mtd->oobsize); +} + +static int +ar934x_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int len; + int err; + + nfc_dbg(nfc, "read_page_raw: page:%d oob:%d\n", page, oob_required); + + len = mtd->writesize; + if (oob_required) + len += mtd->oobsize; + + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len); + if (err) + return err; + + memcpy(buf, nfc->buf, mtd->writesize); + + if (oob_required) + memcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize); + + return 0; +} + +static int +ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, + u8 *buf, int oob_required, int page) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + u32 ecc_ctrl; + int max_bitflips = 0; + bool ecc_failed; + bool ecc_corrected; + int err; + + nfc_dbg(nfc, "read_page: page:%d oob:%d\n", page, oob_required); + + ar934x_nfc_enable_hwecc(nfc); + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, + mtd->writesize); + ar934x_nfc_disable_hwecc(nfc); + + if (err) + return err; + + /* TODO: optimize to avoid memcpy */ + memcpy(buf, nfc->buf, mtd->writesize); + + /* read the ECC status */ + ecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL); + ecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT; + ecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT; + + if (oob_required || ecc_failed) { + err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, + page, mtd->oobsize); + if (err) + return err; + + if (oob_required) + memcpy(chip->oob_poi, nfc->buf, mtd->oobsize); + } + + if (ecc_failed) { + /* + * The hardware ECC engine reports uncorrectable errors + * on empty pages. Check the ECC bytes and the data. If + * both contains 0xff bytes only, dont report a failure. + * + * TODO: prebuild a buffer with 0xff bytes and use memcmp + * for better performance? + */ + if (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) || + !is_all_ff(buf, mtd->writesize)) + mtd->ecc_stats.failed++; + } else if (ecc_corrected) { + /* + * The hardware does not report the exact count of the + * corrected bitflips, use assumptions based on the + * threshold. + */ + if (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) { + /* + * The number of corrected bitflips exceeds the + * threshold. Assume the maximum. + */ + max_bitflips = chip->ecc.strength * chip->ecc.steps; + } else { + max_bitflips = nfc->ecc_thres * chip->ecc.steps; + } + + mtd->ecc_stats.corrected += max_bitflips; + } + + return max_bitflips; +} + +static int +ar934x_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int page; + int len; + + page = nfc->seqin_page_addr; + + nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required); + + memcpy(nfc->buf, buf, mtd->writesize); + len = mtd->writesize; + + if (oob_required) { + memcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize); + len += mtd->oobsize; + } + + return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len); +} + +static int +ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + int page; + int err; + + page = nfc->seqin_page_addr; + + nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required); + + /* write OOB first */ + if (oob_required && + !is_all_ff(chip->oob_poi, mtd->oobsize)) { + err = ar934x_nfc_write_oob(mtd, chip, page); + if (err) + return err; + } + + /* TODO: optimize to avoid memcopy */ + memcpy(nfc->buf, buf, mtd->writesize); + + ar934x_nfc_enable_hwecc(nfc); + err = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, + mtd->writesize); + ar934x_nfc_disable_hwecc(nfc); + + return err; +} + +static void +ar934x_nfc_hw_init(struct ar934x_nfc *nfc) +{ + struct ar934x_nfc_platform_data *pdata; + + pdata = ar934x_nfc_get_platform_data(nfc); + if (pdata->hw_reset) { + pdata->hw_reset(true); + pdata->hw_reset(false); + } + + /* + * setup timings + * TODO: make it configurable via platform data + */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ, + AR934X_NFC_TIME_SEQ_DEFAULT); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN, + AR934X_NFC_TIMINGS_ASYN_DEFAULT); + ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN, + AR934X_NFC_TIMINGS_SYN_DEFAULT); + + /* disable WP on all chips, and select chip 0 */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0); + + /* initialize Control register */ + nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN; + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + if (nfc->small_page) { + /* Setup generic sequence register for small page reads. */ + ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL, + AR934X_NFC_GENSEQ_SMALL_PAGE_READ); + } +} + +static void +ar934x_nfc_restart(struct ar934x_nfc *nfc) +{ + u32 ctrl_reg; + + if (nfc->select_chip) + nfc->select_chip(-1); + + ctrl_reg = nfc->ctrl_reg; + ar934x_nfc_hw_init(nfc); + nfc->ctrl_reg = ctrl_reg; + + if (nfc->select_chip) + nfc->select_chip(0); + + ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET); +} + +static irqreturn_t +ar934x_nfc_irq_handler(int irq, void *data) +{ + struct ar934x_nfc *nfc = data; + u32 status; + + status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0); + /* flush write */ + ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS); + + status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK); + if (status) { + nfc_dbg(nfc, "got IRQ, status:%08x\n", status); + + nfc->irq_status = status; + nfc->spurious_irq_expected = true; + wake_up(&nfc->irq_waitq); + } else { + if (nfc->spurious_irq_expected) { + nfc->spurious_irq_expected = false; + } else { + dev_warn(nfc->parent, "spurious interrupt\n"); + } + } + + return IRQ_HANDLED; +} + +static int +ar934x_nfc_init_tail(struct mtd_info *mtd) +{ + struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd); + struct nand_chip *chip = &nfc->nand_chip; + u32 ctrl; + u32 t; + int err; + + switch (mtd->oobsize) { + case 16: + case 64: + case 128: + ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize); + break; + + default: + dev_err(nfc->parent, "unsupported OOB size: %d bytes\n", + mtd->oobsize); + return -ENXIO; + } + + ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN; + + switch (mtd->erasesize / mtd->writesize) { + case 32: + t = AR934X_NFC_CTRL_BLOCK_SIZE_32; + break; + + case 64: + t = AR934X_NFC_CTRL_BLOCK_SIZE_64; + break; + + case 128: + t = AR934X_NFC_CTRL_BLOCK_SIZE_128; + break; + + case 256: + t = AR934X_NFC_CTRL_BLOCK_SIZE_256; + break; + + default: + dev_err(nfc->parent, "unsupported block size: %u\n", + mtd->erasesize / mtd->writesize); + return -ENXIO; + } + + ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S; + + switch (mtd->writesize) { + case 256: + nfc->small_page = 1; + t = AR934X_NFC_CTRL_PAGE_SIZE_256; + break; + + case 512: + nfc->small_page = 1; + t = AR934X_NFC_CTRL_PAGE_SIZE_512; + break; + + case 1024: + t = AR934X_NFC_CTRL_PAGE_SIZE_1024; + break; + + case 2048: + t = AR934X_NFC_CTRL_PAGE_SIZE_2048; + break; + + case 4096: + t = AR934X_NFC_CTRL_PAGE_SIZE_4096; + break; + + case 8192: + t = AR934X_NFC_CTRL_PAGE_SIZE_8192; + break; + + case 16384: + t = AR934X_NFC_CTRL_PAGE_SIZE_16384; + break; + + default: + dev_err(nfc->parent, "unsupported write size: %d bytes\n", + mtd->writesize); + return -ENXIO; + } + + ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S; + + if (nfc->small_page) { + ctrl |= AR934X_NFC_CTRL_SMALL_PAGE; + + if (chip->chipsize > (32 << 20)) { + nfc->addr_count0 = 4; + nfc->addr_count1 = 3; + } else if (chip->chipsize > (2 << 16)) { + nfc->addr_count0 = 3; + nfc->addr_count1 = 2; + } else { + nfc->addr_count0 = 2; + nfc->addr_count1 = 1; + } + } else { + if (chip->chipsize > (128 << 20)) { + nfc->addr_count0 = 5; + nfc->addr_count1 = 3; + } else if (chip->chipsize > (8 << 16)) { + nfc->addr_count0 = 4; + nfc->addr_count1 = 2; + } else { + nfc->addr_count0 = 3; + nfc->addr_count1 = 1; + } + } + + ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S; + ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S; + + nfc->ctrl_reg = ctrl; + ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg); + + ar934x_nfc_free_buf(nfc); + err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize); + + return err; +} + +static struct nand_ecclayout ar934x_nfc_oob_64_hwecc = { + .eccbytes = 28, + .eccpos = { + 20, 21, 22, 23, 24, 25, 26, + 27, 28, 29, 30, 31, 32, 33, + 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, 47, + }, + .oobfree = { + { + .offset = 4, + .length = 16, + }, + { + .offset = 48, + .length = 16, + }, + }, +}; + +static int +ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc) +{ + struct nand_chip *nand = &nfc->nand_chip; + u32 ecc_cap; + u32 ecc_thres; + + if (!config_enabled(CONFIG_MTD_NAND_AR934X_HW_ECC)) { + dev_err(nfc->parent, "hardware ECC support is disabled\n"); + return -EINVAL; + } + + switch (nfc->mtd.writesize) { + case 2048: + /* + * Writing a subpage separately is not supported, because + * the controller only does ECC on full-page accesses. + */ + nand->options = NAND_NO_SUBPAGE_WRITE; + + nand->ecc.size = 512; + nand->ecc.bytes = 7; + nand->ecc.strength = 4; + nand->ecc.layout = &ar934x_nfc_oob_64_hwecc; + break; + + default: + dev_err(nfc->parent, + "hardware ECC is not available for %d byte pages\n", + nfc->mtd.writesize); + return -EINVAL; + } + + BUG_ON(!nand->ecc.layout); + + switch (nand->ecc.strength) { + case 4: + ecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4; + ecc_thres = 4; + break; + + default: + dev_err(nfc->parent, "unsupported ECC strength %u\n", + nand->ecc.strength); + return -EINVAL; + } + + nfc->ecc_thres = ecc_thres; + nfc->ecc_oob_pos = nand->ecc.layout->eccpos[0]; + + nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S; + nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S; + + nfc->ecc_offset_reg = nfc->mtd.writesize + nfc->ecc_oob_pos; + + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.read_page = ar934x_nfc_read_page; + nand->ecc.read_page_raw = ar934x_nfc_read_page_raw; + nand->ecc.write_page = ar934x_nfc_write_page; + nand->ecc.write_page_raw = ar934x_nfc_write_page_raw; + nand->ecc.read_oob = ar934x_nfc_read_oob; + nand->ecc.write_oob = ar934x_nfc_write_oob; + + return 0; +} + +static int +ar934x_nfc_probe(struct platform_device *pdev) +{ + static const char *part_probes[] = { "cmdlinepart", NULL, }; + struct ar934x_nfc_platform_data *pdata; + struct ar934x_nfc *nfc; + struct resource *res; + struct mtd_info *mtd; + struct nand_chip *nand; + struct mtd_part_parser_data ppdata; + int ret; + + pdata = pdev->dev.platform_data; + if (pdata == NULL) { + dev_err(&pdev->dev, "no platform data defined\n"); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get I/O memory\n"); + return -EINVAL; + } + + nfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL); + if (!nfc) { + dev_err(&pdev->dev, "failed to allocate driver data\n"); + return -ENOMEM; + } + + nfc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(nfc->base)) { + dev_err(&pdev->dev, "failed to remap I/O memory\n"); + return PTR_ERR(nfc->base); + } + + nfc->irq = platform_get_irq(pdev, 0); + if (nfc->irq < 0) { + dev_err(&pdev->dev, "no IRQ resource specified\n"); + return -EINVAL; + } + + init_waitqueue_head(&nfc->irq_waitq); + ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, 0, + dev_name(&pdev->dev), nfc); + if (ret) { + dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret); + return ret; + } + + nfc->parent = &pdev->dev; + nfc->select_chip = pdata->select_chip; + nfc->swap_dma = pdata->swap_dma; + + nand = &nfc->nand_chip; + mtd = &nfc->mtd; + + mtd->priv = nand; + mtd->owner = THIS_MODULE; + if (pdata->name) + mtd->name = pdata->name; + else + mtd->name = dev_name(&pdev->dev); + + nand->chip_delay = 25; + + nand->dev_ready = ar934x_nfc_dev_ready; + nand->cmdfunc = ar934x_nfc_cmdfunc; + nand->read_byte = ar934x_nfc_read_byte; + nand->write_buf = ar934x_nfc_write_buf; + nand->read_buf = ar934x_nfc_read_buf; + nand->select_chip = ar934x_nfc_select_chip; + + ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE); + if (ret) + goto err_free_irq; + + platform_set_drvdata(pdev, nfc); + + ar934x_nfc_hw_init(nfc); + + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) { + dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret); + goto err_free_buf; + } + + ret = ar934x_nfc_init_tail(mtd); + if (ret) { + dev_err(&pdev->dev, "init tail failed, err:%d\n", ret); + goto err_free_buf; + } + + if (pdata->scan_fixup) { + ret = pdata->scan_fixup(mtd); + if (ret) + goto err_free_buf; + } + + switch (pdata->ecc_mode) { + case AR934X_NFC_ECC_SOFT: + nand->ecc.mode = NAND_ECC_SOFT; + break; + + case AR934X_NFC_ECC_SOFT_BCH: + nand->ecc.mode = NAND_ECC_SOFT_BCH; + break; + + case AR934X_NFC_ECC_HW: + ret = ar934x_nfc_setup_hwecc(nfc); + if (ret) + goto err_free_buf; + + break; + + default: + dev_err(nfc->parent, "unknown ECC mode %d\n", pdata->ecc_mode); + return -EINVAL; + } + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret); + goto err_free_buf; + } + + memset(&ppdata, '\0', sizeof(ppdata)); + ret = mtd_device_parse_register(mtd, part_probes, &ppdata, + pdata->parts, pdata->nr_parts); + if (ret) { + dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret); + goto err_free_buf; + } + + return 0; + +err_free_buf: + ar934x_nfc_free_buf(nfc); +err_free_irq: + free_irq(nfc->irq, nfc); + return ret; +} + +static int +ar934x_nfc_remove(struct platform_device *pdev) +{ + struct ar934x_nfc *nfc; + + nfc = platform_get_drvdata(pdev); + if (nfc) { + nand_release(&nfc->mtd); + ar934x_nfc_free_buf(nfc); + free_irq(nfc->irq, nfc); + } + + return 0; +} + +static struct platform_driver ar934x_nfc_driver = { + .probe = ar934x_nfc_probe, + .remove = ar934x_nfc_remove, + .driver = { + .name = AR934X_NFC_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(ar934x_nfc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver"); +MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c new file mode 100644 index 0000000..5b9841b --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c @@ -0,0 +1,305 @@ +/* + * NAND flash driver for the MikroTik RouterBoard 4xx series + * + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * This file was based on the driver for Linux 2.6.22 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_NAME "rb4xx-nand" +#define DRV_VERSION "0.2.0" +#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" + +#define RB4XX_NAND_GPIO_READY 5 +#define RB4XX_NAND_GPIO_ALE 37 +#define RB4XX_NAND_GPIO_CLE 38 +#define RB4XX_NAND_GPIO_NCE 39 + +struct rb4xx_nand_info { + struct nand_chip chip; + struct mtd_info mtd; +}; + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. + */ +static struct nand_ecclayout rb4xx_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static struct mtd_partition rb4xx_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static int rb4xx_nand_dev_ready(struct mtd_info *mtd) +{ + return gpio_get_value_cansleep(RB4XX_NAND_GPIO_READY); +} + +static void rb4xx_nand_write_cmd(unsigned char cmd) +{ + unsigned char data = cmd; + int err; + + err = rb4xx_cpld_write(&data, 1); + if (err) + pr_err("rb4xx_nand: write cmd failed, err=%d\n", err); +} + +static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + gpio_set_value_cansleep(RB4XX_NAND_GPIO_CLE, + (ctrl & NAND_CLE) ? 1 : 0); + gpio_set_value_cansleep(RB4XX_NAND_GPIO_ALE, + (ctrl & NAND_ALE) ? 1 : 0); + gpio_set_value_cansleep(RB4XX_NAND_GPIO_NCE, + (ctrl & NAND_NCE) ? 0 : 1); + } + + if (cmd != NAND_CMD_NONE) + rb4xx_nand_write_cmd(cmd); +} + +static unsigned char rb4xx_nand_read_byte(struct mtd_info *mtd) +{ + unsigned char data = 0; + int err; + + err = rb4xx_cpld_read(&data, NULL, 1); + if (err) { + pr_err("rb4xx_nand: read data failed, err=%d\n", err); + data = 0xff; + } + + return data; +} + +static void rb4xx_nand_write_buf(struct mtd_info *mtd, const unsigned char *buf, + int len) +{ + int err; + + err = rb4xx_cpld_write(buf, len); + if (err) + pr_err("rb4xx_nand: write buf failed, err=%d\n", err); +} + +static void rb4xx_nand_read_buf(struct mtd_info *mtd, unsigned char *buf, + int len) +{ + int err; + + err = rb4xx_cpld_read(buf, NULL, len); + if (err) + pr_err("rb4xx_nand: read buf failed, err=%d\n", err); +} + +static int rb4xx_nand_probe(struct platform_device *pdev) +{ + struct rb4xx_nand_info *info; + int ret; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + + ret = gpio_request(RB4XX_NAND_GPIO_READY, "NAND RDY"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_READY); + goto err; + } + + ret = gpio_direction_input(RB4XX_NAND_GPIO_READY); + if (ret) { + dev_err(&pdev->dev, "unable to set input mode on gpio %d\n", + RB4XX_NAND_GPIO_READY); + goto err_free_gpio_ready; + } + + ret = gpio_request(RB4XX_NAND_GPIO_ALE, "NAND ALE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_ready; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_ALE, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_ale; + } + + ret = gpio_request(RB4XX_NAND_GPIO_CLE, "NAND CLE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_CLE); + goto err_free_gpio_ale; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_CLE, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_CLE); + goto err_free_gpio_cle; + } + + ret = gpio_request(RB4XX_NAND_GPIO_NCE, "NAND NCE"); + if (ret) { + dev_err(&pdev->dev, "unable to request gpio %d\n", + RB4XX_NAND_GPIO_NCE); + goto err_free_gpio_cle; + } + + ret = gpio_direction_output(RB4XX_NAND_GPIO_NCE, 1); + if (ret) { + dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", + RB4XX_NAND_GPIO_ALE); + goto err_free_gpio_nce; + } + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + dev_err(&pdev->dev, "rb4xx-nand: no memory for private data\n"); + ret = -ENOMEM; + goto err_free_gpio_nce; + } + + info->chip.priv = &info; + info->mtd.priv = &info->chip; + info->mtd.owner = THIS_MODULE; + + info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; + info->chip.dev_ready = rb4xx_nand_dev_ready; + info->chip.read_byte = rb4xx_nand_read_byte; + info->chip.write_buf = rb4xx_nand_write_buf; + info->chip.read_buf = rb4xx_nand_read_buf; + + info->chip.chip_delay = 25; + info->chip.ecc.mode = NAND_ECC_SOFT; + + platform_set_drvdata(pdev, info); + + ret = nand_scan_ident(&info->mtd, 1, NULL); + if (ret) { + ret = -ENXIO; + goto err_free_info; + } + + if (info->mtd.writesize == 512) + info->chip.ecc.layout = &rb4xx_nand_ecclayout; + + ret = nand_scan_tail(&info->mtd); + if (ret) { + return -ENXIO; + goto err_set_drvdata; + } + + mtd_device_register(&info->mtd, rb4xx_nand_partitions, + ARRAY_SIZE(rb4xx_nand_partitions)); + if (ret) + goto err_release_nand; + + return 0; + +err_release_nand: + nand_release(&info->mtd); +err_set_drvdata: + platform_set_drvdata(pdev, NULL); +err_free_info: + kfree(info); +err_free_gpio_nce: + gpio_free(RB4XX_NAND_GPIO_NCE); +err_free_gpio_cle: + gpio_free(RB4XX_NAND_GPIO_CLE); +err_free_gpio_ale: + gpio_free(RB4XX_NAND_GPIO_ALE); +err_free_gpio_ready: + gpio_free(RB4XX_NAND_GPIO_READY); +err: + return ret; +} + +static int rb4xx_nand_remove(struct platform_device *pdev) +{ + struct rb4xx_nand_info *info = platform_get_drvdata(pdev); + + nand_release(&info->mtd); + platform_set_drvdata(pdev, NULL); + kfree(info); + gpio_free(RB4XX_NAND_GPIO_NCE); + gpio_free(RB4XX_NAND_GPIO_CLE); + gpio_free(RB4XX_NAND_GPIO_ALE); + gpio_free(RB4XX_NAND_GPIO_READY); + + return 0; +} + +static struct platform_driver rb4xx_nand_driver = { + .probe = rb4xx_nand_probe, + .remove = rb4xx_nand_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb4xx_nand_init(void) +{ + return platform_driver_register(&rb4xx_nand_driver); +} + +static void __exit rb4xx_nand_exit(void) +{ + platform_driver_unregister(&rb4xx_nand_driver); +} + +module_init(rb4xx_nand_init); +module_exit(rb4xx_nand_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_AUTHOR("Imre Kaloz "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c new file mode 100644 index 0000000..a20409b --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c @@ -0,0 +1,354 @@ +/* + * NAND flash driver for the MikroTik RouterBOARD 750 + * + * Copyright (C) 2010-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define DRV_NAME "rb750-nand" +#define DRV_VERSION "0.1.0" +#define DRV_DESC "NAND flash driver for the RouterBOARD 750" + +#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) +#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) +#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) +#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) +#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) +#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) + +#define RB750_NAND_DATA_SHIFT 1 +#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) +#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) +#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ + RB750_NAND_NRE | RB750_NAND_NWE) + +struct rb750_nand_info { + struct nand_chip chip; + struct mtd_info mtd; + struct rb7xx_nand_platform_data *pdata; +}; + +static inline struct rb750_nand_info *mtd_to_rbinfo(struct mtd_info *mtd) +{ + return container_of(mtd, struct rb750_nand_info, mtd); +} + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. + */ +static struct nand_ecclayout rb750_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static struct mtd_partition rb750_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static void rb750_nand_write(const u8 *buf, unsigned len) +{ + void __iomem *base = ath79_gpio_base; + u32 out; + u32 t; + unsigned i; + + /* set data lines to output mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE); + + out = __raw_readl(base + AR71XX_GPIO_REG_OUT); + out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); + for (i = 0; i != len; i++) { + u32 data; + + data = buf[i]; + data <<= RB750_NAND_DATA_SHIFT; + data |= out; + __raw_writel(data, base + AR71XX_GPIO_REG_OUT); + + __raw_writel(data | RB750_NAND_NWE, base + AR71XX_GPIO_REG_OUT); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + } + + /* set data lines to input mode */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OE); +} + +static void rb750_nand_read(u8 *read_buf, unsigned len) +{ + void __iomem *base = ath79_gpio_base; + unsigned i; + + for (i = 0; i < len; i++) { + u8 data; + + /* activate RE line */ + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_CLEAR); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); + + /* read input lines */ + data = __raw_readl(base + AR71XX_GPIO_REG_IN) >> + RB750_NAND_DATA_SHIFT; + + /* deactivate RE line */ + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_SET); + + read_buf[i] = data; + } +} + +static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct rb750_nand_info *rbinfo = mtd_to_rbinfo(mtd); + void __iomem *base = ath79_gpio_base; + u32 t; + + if (chip >= 0) { + rbinfo->pdata->enable_pins(); + + /* set input mode for data lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~RB750_NAND_INPUT_BITS, + base + AR71XX_GPIO_REG_OE); + + /* deactivate RE and WE lines */ + __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, + base + AR71XX_GPIO_REG_SET); + /* flush write */ + (void) __raw_readl(base + AR71XX_GPIO_REG_SET); + + /* activate CE line */ + __raw_writel(rbinfo->pdata->nce_line, + base + AR71XX_GPIO_REG_CLEAR); + } else { + /* deactivate CE line */ + __raw_writel(rbinfo->pdata->nce_line, + base + AR71XX_GPIO_REG_SET); + /* flush write */ + (void) __raw_readl(base + AR71XX_GPIO_REG_SET); + + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY, + base + AR71XX_GPIO_REG_OE); + + rbinfo->pdata->disable_pins(); + } +} + +static int rb750_nand_dev_ready(struct mtd_info *mtd) +{ + void __iomem *base = ath79_gpio_base; + + return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB750_NAND_RDY); +} + +static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + void __iomem *base = ath79_gpio_base; + u32 t; + + t = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); + t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; + t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; + + __raw_writel(t, base + AR71XX_GPIO_REG_OUT); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + } + + if (cmd != NAND_CMD_NONE) { + u8 t = cmd; + rb750_nand_write(&t, 1); + } +} + +static u8 rb750_nand_read_byte(struct mtd_info *mtd) +{ + u8 data = 0; + rb750_nand_read(&data, 1); + return data; +} + +static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + rb750_nand_read(buf, len); +} + +static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + rb750_nand_write(buf, len); +} + +static void __init rb750_nand_gpio_init(struct rb750_nand_info *info) +{ + void __iomem *base = ath79_gpio_base; + u32 out; + u32 t; + + out = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* setup output levels */ + __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, + base + AR71XX_GPIO_REG_SET); + + __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, + base + AR71XX_GPIO_REG_CLEAR); + + /* setup input lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~(RB750_NAND_INPUT_BITS), base + AR71XX_GPIO_REG_OE); + + /* setup output lines */ + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + t |= RB750_NAND_OUTPUT_BITS; + t |= info->pdata->nce_line; + __raw_writel(t, base + AR71XX_GPIO_REG_OE); + + info->pdata->latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); +} + +static int rb750_nand_probe(struct platform_device *pdev) +{ + struct rb750_nand_info *info; + struct rb7xx_nand_platform_data *pdata; + int ret; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->chip.priv = &info; + info->mtd.priv = &info->chip; + info->mtd.owner = THIS_MODULE; + + info->chip.select_chip = rb750_nand_select_chip; + info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; + info->chip.dev_ready = rb750_nand_dev_ready; + info->chip.read_byte = rb750_nand_read_byte; + info->chip.write_buf = rb750_nand_write_buf; + info->chip.read_buf = rb750_nand_read_buf; + + info->chip.chip_delay = 25; + info->chip.ecc.mode = NAND_ECC_SOFT; + + info->pdata = pdata; + + platform_set_drvdata(pdev, info); + + rb750_nand_gpio_init(info); + + ret = nand_scan_ident(&info->mtd, 1, NULL); + if (ret) { + ret = -ENXIO; + goto err_free_info; + } + + if (info->mtd.writesize == 512) + info->chip.ecc.layout = &rb750_nand_ecclayout; + + ret = nand_scan_tail(&info->mtd); + if (ret) { + return -ENXIO; + goto err_set_drvdata; + } + + ret = mtd_device_register(&info->mtd, rb750_nand_partitions, + ARRAY_SIZE(rb750_nand_partitions)); + if (ret) + goto err_release_nand; + + return 0; + +err_release_nand: + nand_release(&info->mtd); +err_set_drvdata: + platform_set_drvdata(pdev, NULL); +err_free_info: + kfree(info); + return ret; +} + +static int rb750_nand_remove(struct platform_device *pdev) +{ + struct rb750_nand_info *info = platform_get_drvdata(pdev); + + nand_release(&info->mtd); + platform_set_drvdata(pdev, NULL); + kfree(info); + + return 0; +} + +static struct platform_driver rb750_nand_driver = { + .probe = rb750_nand_probe, + .remove = rb750_nand_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb750_nand_init(void) +{ + return platform_driver_register(&rb750_nand_driver); +} + +static void __exit rb750_nand_exit(void) +{ + platform_driver_unregister(&rb750_nand_driver); +} + +module_init(rb750_nand_init); +module_exit(rb750_nand_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c new file mode 100644 index 0000000..f0aa3c3 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c @@ -0,0 +1,377 @@ +/* + * NAND flash driver for the MikroTik RouterBOARD 91x series + * + * Copyright (C) 2013-2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_DESC "NAND flash driver for the RouterBOARD 91x series" + +#define RB91X_NAND_NRWE BIT(12) + +#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\ + BIT(13) | BIT(14) | BIT(15)) + +#define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY) +#define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE) + +#define RB91X_NAND_LOW_DATA_MASK 0x1f +#define RB91X_NAND_HIGH_DATA_MASK 0xe0 +#define RB91X_NAND_HIGH_DATA_SHIFT 8 + +struct rb91x_nand_info { + struct nand_chip chip; + struct mtd_info mtd; + struct device *dev; + + int gpio_nce; + int gpio_ale; + int gpio_cle; + int gpio_rdy; + int gpio_read; + int gpio_nrw; + int gpio_nle; +}; + +static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd) +{ + return container_of(mtd, struct rb91x_nand_info, mtd); +} + +/* + * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader + * will not be able to find the kernel that we load. + */ +static struct nand_ecclayout rb91x_nand_ecclayout = { + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15 }, + .oobavail = 9, + .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } +}; + +static struct mtd_partition rb91x_nand_partitions[] = { + { + .name = "booter", + .offset = 0, + .size = (256 * 1024), + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = (256 * 1024), + .size = (4 * 1024 * 1024) - (256 * 1024), + }, { + .name = "rootfs", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + }, +}; + +static void rb91x_nand_write(struct rb91x_nand_info *rbni, + const u8 *buf, + unsigned len) +{ + void __iomem *base = ath79_gpio_base; + u32 oe_reg; + u32 out_reg; + u32 out; + unsigned i; + + /* enable the latch */ + gpio_set_value_cansleep(rbni->gpio_nle, 0); + + oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); + out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* set data lines to output mode */ + __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE), + base + AR71XX_GPIO_REG_OE); + + out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE); + for (i = 0; i != len; i++) { + u32 data; + + data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) << + RB91X_NAND_HIGH_DATA_SHIFT; + data |= buf[i] & RB91X_NAND_LOW_DATA_MASK; + data |= out; + __raw_writel(data, base + AR71XX_GPIO_REG_OUT); + + /* deactivate WE line */ + data |= RB91X_NAND_NRWE; + __raw_writel(data, base + AR71XX_GPIO_REG_OUT); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + } + + /* restore registers */ + __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT); + __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* disable the latch */ + gpio_set_value_cansleep(rbni->gpio_nle, 1); +} + +static void rb91x_nand_read(struct rb91x_nand_info *rbni, + u8 *read_buf, + unsigned len) +{ + void __iomem *base = ath79_gpio_base; + u32 oe_reg; + u32 out_reg; + unsigned i; + + /* enable read mode */ + gpio_set_value_cansleep(rbni->gpio_read, 1); + + /* enable latch */ + gpio_set_value_cansleep(rbni->gpio_nle, 0); + + /* save registers */ + oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); + out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* set data lines to input mode */ + __raw_writel(oe_reg | RB91X_NAND_DATA_BITS, + base + AR71XX_GPIO_REG_OE); + + for (i = 0; i < len; i++) { + u32 in; + u8 data; + + /* activate RE line */ + __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); + + /* read input lines */ + in = __raw_readl(base + AR71XX_GPIO_REG_IN); + + /* deactivate RE line */ + __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET); + + data = (in & RB91X_NAND_LOW_DATA_MASK); + data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) & + RB91X_NAND_HIGH_DATA_MASK; + + read_buf[i] = data; + } + + /* restore registers */ + __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT); + __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); + /* flush write */ + __raw_readl(base + AR71XX_GPIO_REG_OUT); + + /* disable latch */ + gpio_set_value_cansleep(rbni->gpio_nle, 1); + + /* disable read mode */ + gpio_set_value_cansleep(rbni->gpio_read, 0); +} + +static int rb91x_nand_dev_ready(struct mtd_info *mtd) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + + return gpio_get_value_cansleep(rbni->gpio_rdy); +} + +static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + + if (ctrl & NAND_CTRL_CHANGE) { + gpio_set_value_cansleep(rbni->gpio_cle, + (ctrl & NAND_CLE) ? 1 : 0); + gpio_set_value_cansleep(rbni->gpio_ale, + (ctrl & NAND_ALE) ? 1 : 0); + gpio_set_value_cansleep(rbni->gpio_nce, + (ctrl & NAND_NCE) ? 0 : 1); + } + + if (cmd != NAND_CMD_NONE) { + u8 t = cmd; + + rb91x_nand_write(rbni, &t, 1); + } +} + +static u8 rb91x_nand_read_byte(struct mtd_info *mtd) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + u8 data = 0xff; + + rb91x_nand_read(rbni, &data, 1); + + return data; +} + +static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + + rb91x_nand_read(rbni, buf, len); +} + +static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); + + rb91x_nand_write(rbni, buf, len); +} + +static int rb91x_nand_gpio_init(struct rb91x_nand_info *info) +{ + int ret; + + /* + * Ensure that the LATCH is disabled before initializing + * control lines. + */ + ret = devm_gpio_request_one(info->dev, info->gpio_nle, + GPIOF_OUT_INIT_HIGH, "LATCH enable"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_nce, + GPIOF_OUT_INIT_HIGH, "NAND nCE"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_nrw, + GPIOF_OUT_INIT_HIGH, "NAND nRW"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_cle, + GPIOF_OUT_INIT_LOW, "NAND CLE"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_ale, + GPIOF_OUT_INIT_LOW, "NAND ALE"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_read, + GPIOF_OUT_INIT_LOW, "NAND READ"); + if (ret) + return ret; + + ret = devm_gpio_request_one(info->dev, info->gpio_rdy, + GPIOF_IN, "NAND RDY"); + return ret; +} + +static int rb91x_nand_probe(struct platform_device *pdev) +{ + struct rb91x_nand_info *rbni; + struct rb91x_nand_platform_data *pdata; + int ret; + + pr_info(DRV_DESC "\n"); + + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) + return -EINVAL; + + rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL); + if (!rbni) + return -ENOMEM; + + rbni->dev = &pdev->dev; + rbni->gpio_nce = pdata->gpio_nce; + rbni->gpio_ale = pdata->gpio_ale; + rbni->gpio_cle = pdata->gpio_cle; + rbni->gpio_read = pdata->gpio_read; + rbni->gpio_nrw = pdata->gpio_nrw; + rbni->gpio_rdy = pdata->gpio_rdy; + rbni->gpio_nle = pdata->gpio_nle; + + rbni->chip.priv = &rbni; + rbni->mtd.priv = &rbni->chip; + rbni->mtd.owner = THIS_MODULE; + + rbni->chip.cmd_ctrl = rb91x_nand_cmd_ctrl; + rbni->chip.dev_ready = rb91x_nand_dev_ready; + rbni->chip.read_byte = rb91x_nand_read_byte; + rbni->chip.write_buf = rb91x_nand_write_buf; + rbni->chip.read_buf = rb91x_nand_read_buf; + + rbni->chip.chip_delay = 25; + rbni->chip.ecc.mode = NAND_ECC_SOFT; + + platform_set_drvdata(pdev, rbni); + + ret = rb91x_nand_gpio_init(rbni); + if (ret) + return ret; + + ret = nand_scan_ident(&rbni->mtd, 1, NULL); + if (ret) + return ret; + + if (rbni->mtd.writesize == 512) + rbni->chip.ecc.layout = &rb91x_nand_ecclayout; + + ret = nand_scan_tail(&rbni->mtd); + if (ret) + return ret; + + ret = mtd_device_register(&rbni->mtd, rb91x_nand_partitions, + ARRAY_SIZE(rb91x_nand_partitions)); + if (ret) + goto err_release_nand; + + return 0; + +err_release_nand: + nand_release(&rbni->mtd); + return ret; +} + +static int rb91x_nand_remove(struct platform_device *pdev) +{ + struct rb91x_nand_info *info = platform_get_drvdata(pdev); + + nand_release(&info->mtd); + + return 0; +} + +static struct platform_driver rb91x_nand_driver = { + .probe = rb91x_nand_probe, + .remove = rb91x_nand_remove, + .driver = { + .name = RB91X_NAND_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(rb91x_nand_driver); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c b/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c new file mode 100644 index 0000000..ac1efa1 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/mtd/tplinkpart.c @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define TPLINK_NUM_PARTS 5 +#define TPLINK_HEADER_V1 0x01000000 +#define TPLINK_HEADER_V2 0x02000000 +#define MD5SUM_LEN 16 + +#define TPLINK_ART_LEN 0x10000 +#define TPLINK_KERNEL_OFFS 0x20000 +#define TPLINK_64K_KERNEL_OFFS 0x10000 + +struct tplink_fw_header { + uint32_t version; /* header version */ + char vendor_name[24]; + char fw_version[36]; + uint32_t hw_id; /* hardware id */ + uint32_t hw_rev; /* hardware revision */ + uint32_t unk1; + uint8_t md5sum1[MD5SUM_LEN]; + uint32_t unk2; + uint8_t md5sum2[MD5SUM_LEN]; + uint32_t unk3; + uint32_t kernel_la; /* kernel load address */ + uint32_t kernel_ep; /* kernel entry point */ + uint32_t fw_length; /* total length of the firmware */ + uint32_t kernel_ofs; /* kernel data offset */ + uint32_t kernel_len; /* kernel data length */ + uint32_t rootfs_ofs; /* rootfs data offset */ + uint32_t rootfs_len; /* rootfs data length */ + uint32_t boot_ofs; /* bootloader data offset */ + uint32_t boot_len; /* bootloader data length */ + uint8_t pad[360]; +} __attribute__ ((packed)); + +static struct tplink_fw_header * +tplink_read_header(struct mtd_info *mtd, size_t offset) +{ + struct tplink_fw_header *header; + size_t header_len; + size_t retlen; + int ret; + u32 t; + + header = vmalloc(sizeof(*header)); + if (!header) + goto err; + + header_len = sizeof(struct tplink_fw_header); + ret = mtd_read(mtd, offset, header_len, &retlen, + (unsigned char *) header); + if (ret) + goto err_free_header; + + if (retlen != header_len) + goto err_free_header; + + /* sanity checks */ + t = be32_to_cpu(header->version); + if ((t != TPLINK_HEADER_V1) && (t != TPLINK_HEADER_V2)) + goto err_free_header; + + t = be32_to_cpu(header->kernel_ofs); + if (t != header_len) + goto err_free_header; + + return header; + +err_free_header: + vfree(header); +err: + return NULL; +} + +static int tplink_check_rootfs_magic(struct mtd_info *mtd, size_t offset) +{ + u32 magic; + size_t retlen; + int ret; + + ret = mtd_read(mtd, offset, sizeof(magic), &retlen, + (unsigned char *) &magic); + if (ret) + return ret; + + if (retlen != sizeof(magic)) + return -EIO; + + if (le32_to_cpu(magic) != SQUASHFS_MAGIC && + magic != 0x19852003) + return -EINVAL; + + return 0; +} + +static int tplink_parse_partitions_offset(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data, + size_t offset) +{ + struct mtd_partition *parts; + struct tplink_fw_header *header; + int nr_parts; + size_t art_offset; + size_t rootfs_offset; + size_t squashfs_offset; + int ret; + + nr_parts = TPLINK_NUM_PARTS; + parts = kzalloc(nr_parts * sizeof(struct mtd_partition), GFP_KERNEL); + if (!parts) { + ret = -ENOMEM; + goto err; + } + + header = tplink_read_header(master, offset); + if (!header) { + pr_notice("%s: no TP-Link header found\n", master->name); + ret = -ENODEV; + goto err_free_parts; + } + + squashfs_offset = offset + sizeof(struct tplink_fw_header) + + be32_to_cpu(header->kernel_len); + + ret = tplink_check_rootfs_magic(master, squashfs_offset); + if (ret == 0) + rootfs_offset = squashfs_offset; + else + rootfs_offset = offset + be32_to_cpu(header->rootfs_ofs); + + art_offset = master->size - TPLINK_ART_LEN; + + parts[0].name = "u-boot"; + parts[0].offset = 0; + parts[0].size = offset; + parts[0].mask_flags = MTD_WRITEABLE; + + parts[1].name = "kernel"; + parts[1].offset = offset; + parts[1].size = rootfs_offset - offset; + + parts[2].name = "rootfs"; + parts[2].offset = rootfs_offset; + parts[2].size = art_offset - rootfs_offset; + + parts[3].name = "art"; + parts[3].offset = art_offset; + parts[3].size = TPLINK_ART_LEN; + parts[3].mask_flags = MTD_WRITEABLE; + + parts[4].name = "firmware"; + parts[4].offset = offset; + parts[4].size = art_offset - offset; + + vfree(header); + + *pparts = parts; + return nr_parts; + +err_free_parts: + kfree(parts); +err: + *pparts = NULL; + return ret; +} + +static int tplink_parse_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + return tplink_parse_partitions_offset(master, pparts, data, + TPLINK_KERNEL_OFFS); +} + +static int tplink_parse_64k_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + return tplink_parse_partitions_offset(master, pparts, data, + TPLINK_64K_KERNEL_OFFS); +} + +static struct mtd_part_parser tplink_parser = { + .owner = THIS_MODULE, + .parse_fn = tplink_parse_partitions, + .name = "tp-link", +}; + +static struct mtd_part_parser tplink_64k_parser = { + .owner = THIS_MODULE, + .parse_fn = tplink_parse_64k_partitions, + .name = "tp-link-64k", +}; + +static int __init tplink_parser_init(void) +{ + register_mtd_parser(&tplink_parser); + register_mtd_parser(&tplink_64k_parser); + + return 0; +} + +module_init(tplink_parser_init); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gabor Juhos "); diff --git a/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c b/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c new file mode 100644 index 0000000..b9e9af3 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/dsa/mv88e6063.c @@ -0,0 +1,311 @@ +/* + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips + * Copyright (c) 2009 Gabor Juhos + * + * This driver was base on: net/dsa/mv88e6060.c + * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips + * Copyright (c) 2008-2009 Marvell Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include + +#define REG_BASE 0x10 +#define REG_PHY(p) (REG_BASE + (p)) +#define REG_PORT(p) (REG_BASE + 8 + (p)) +#define REG_GLOBAL (REG_BASE + 0x0f) +#define NUM_PORTS 7 + +static int reg_read(struct dsa_switch *ds, int addr, int reg) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) + return mdiobus_read(ds->master_mii_bus, addr, reg); +#else + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); + return mdiobus_read(bus, addr, reg); +#endif +} + +#define REG_READ(addr, reg) \ + ({ \ + int __ret; \ + \ + __ret = reg_read(ds, addr, reg); \ + if (__ret < 0) \ + return __ret; \ + __ret; \ + }) + + +static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) + return mdiobus_write(ds->master_mii_bus, addr, reg, val); +#else + struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); + return mdiobus_write(bus, addr, reg, val); +#endif +} + +#define REG_WRITE(addr, reg, val) \ + ({ \ + int __ret; \ + \ + __ret = reg_write(ds, addr, reg, val); \ + if (__ret < 0) \ + return __ret; \ + }) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) +static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) +{ +#else +static char *mv88e6063_probe(struct device *host_dev, int sw_addr) +{ + struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); +#endif + int ret; + + ret = mdiobus_read(bus, REG_PORT(0), 0x03); + if (ret >= 0) { + ret &= 0xfff0; + if (ret == 0x1530) + return "Marvell 88E6063"; + } + + return NULL; +} + +static int mv88e6063_switch_reset(struct dsa_switch *ds) +{ + int i; + int ret; + + /* + * Set all ports to the disabled state. + */ + for (i = 0; i < NUM_PORTS; i++) { + ret = REG_READ(REG_PORT(i), 0x04); + REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); + } + + /* + * Wait for transmit queues to drain. + */ + msleep(2); + + /* + * Reset the switch. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); + + /* + * Wait up to one second for reset to complete. + */ + for (i = 0; i < 1000; i++) { + ret = REG_READ(REG_GLOBAL, 0x00); + if ((ret & 0x8000) == 0x0000) + break; + + msleep(1); + } + if (i == 1000) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e6063_setup_global(struct dsa_switch *ds) +{ + /* + * Disable discarding of frames with excessive collisions, + * set the maximum frame size to 1536 bytes, and mask all + * interrupt sources. + */ + REG_WRITE(REG_GLOBAL, 0x04, 0x0800); + + /* + * Enable automatic address learning, set the address + * database size to 1024 entries, and set the default aging + * time to 5 minutes. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); + + return 0; +} + +static int mv88e6063_setup_port(struct dsa_switch *ds, int p) +{ + int addr = REG_PORT(p); + + /* + * Do not force flow control, disable Ingress and Egress + * Header tagging, disable VLAN tunneling, and set the port + * state to Forwarding. Additionally, if this is the CPU + * port, enable Ingress and Egress Trailer tagging mode. + */ + REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); + + /* + * Port based VLAN map: give each port its own address + * database, allow the CPU port to talk to each of the 'real' + * ports, and allow each of the 'real' ports to only talk to + * the CPU port. + */ + REG_WRITE(addr, 0x06, + ((p & 0xf) << 12) | + (dsa_is_cpu_port(ds, p) ? + ds->phys_port_mask : + (1 << ds->dst->cpu_port))); + + /* + * Port Association Vector: when learning source addresses + * of packets, add the address to the address database using + * a port bitmap that has only the bit for this port set and + * the other bits clear. + */ + REG_WRITE(addr, 0x0b, 1 << p); + + return 0; +} + +static int mv88e6063_setup(struct dsa_switch *ds) +{ + int i; + int ret; + + ret = mv88e6063_switch_reset(ds); + if (ret < 0) + return ret; + + /* @@@ initialise atu */ + + ret = mv88e6063_setup_global(ds); + if (ret < 0) + return ret; + + for (i = 0; i < NUM_PORTS; i++) { + ret = mv88e6063_setup_port(ds, i); + if (ret < 0) + return ret; + } + + return 0; +} + +static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) +{ + REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); + REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); + REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); + + return 0; +} + +static int mv88e6063_port_to_phy_addr(int port) +{ + if (port >= 0 && port <= NUM_PORTS) + return REG_PHY(port); + return -1; +} + +static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_read(ds, addr, regnum); +} + +static int +mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_write(ds, addr, regnum, val); +} + +static void mv88e6063_poll_link(struct dsa_switch *ds) +{ + int i; + + for (i = 0; i < DSA_MAX_PORTS; i++) { + struct net_device *dev; + int uninitialized_var(port_status); + int link; + int speed; + int duplex; + int fc; + + dev = ds->ports[i]; + if (dev == NULL) + continue; + + link = 0; + if (dev->flags & IFF_UP) { + port_status = reg_read(ds, REG_PORT(i), 0x00); + if (port_status < 0) + continue; + + link = !!(port_status & 0x1000); + } + + if (!link) { + if (netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link down\n", dev->name); + netif_carrier_off(dev); + } + continue; + } + + speed = (port_status & 0x0100) ? 100 : 10; + duplex = (port_status & 0x0200) ? 1 : 0; + fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; + + if (!netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " + "flow control %sabled\n", dev->name, + speed, duplex ? "full" : "half", + fc ? "en" : "dis"); + netif_carrier_on(dev); + } + } +} + +static struct dsa_switch_driver mv88e6063_switch_driver = { + .tag_protocol = htons(ETH_P_TRAILER), + .probe = mv88e6063_probe, + .setup = mv88e6063_setup, + .set_addr = mv88e6063_set_addr, + .phy_read = mv88e6063_phy_read, + .phy_write = mv88e6063_phy_write, + .poll_link = mv88e6063_poll_link, +}; + +static int __init mv88e6063_init(void) +{ + register_switch_driver(&mv88e6063_switch_driver); + return 0; +} +module_init(mv88e6063_init); + +static void __exit mv88e6063_cleanup(void) +{ + unregister_switch_driver(&mv88e6063_switch_driver); +} +module_exit(mv88e6063_cleanup); diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig new file mode 100644 index 0000000..42d544f --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Kconfig @@ -0,0 +1,33 @@ +config AG71XX + tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support" + depends on ATH79 + select PHYLIB + help + If you wish to compile a kernel for AR7XXX/91XXX and enable + ethernet support, then you should always answer Y to this. + +if AG71XX + +config AG71XX_DEBUG + bool "Atheros AR71xx built-in ethernet driver debugging" + default n + help + Atheros AR71xx built-in ethernet driver debugging messages. + +config AG71XX_DEBUG_FS + bool "Atheros AR71xx built-in ethernet driver debugfs support" + depends on DEBUG_FS + default n + help + Say Y, if you need access to various statistics provided by + the ag71xx driver. + +config AG71XX_AR8216_SUPPORT + bool "special support for the Atheros AR8216 switch" + default n + default y if ATH79_MACH_WNR2000 || ATH79_MACH_MZK_W04NU + help + Say 'y' here if you want to enable special support for the + Atheros AR8216 switch found on some boards. + +endif diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile new file mode 100644 index 0000000..b3ec408 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the Atheros AR71xx built-in ethernet macs +# + +ag71xx-y += ag71xx_main.o +ag71xx-y += ag71xx_ethtool.o +ag71xx-y += ag71xx_phy.o +ag71xx-y += ag71xx_mdio.o +ag71xx-y += ag71xx_ar7240.o + +ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o +ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o + +obj-$(CONFIG_AG71XX) += ag71xx.o + diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h new file mode 100644 index 0000000..b18c20b --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h @@ -0,0 +1,485 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __AG71XX_H +#define __AG71XX_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define AG71XX_DRV_NAME "ag71xx" +#define AG71XX_DRV_VERSION "0.5.35" + +#define AG71XX_NAPI_WEIGHT 64 +#define AG71XX_OOM_REFILL (1 + HZ/10) + +#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) +#define AG71XX_INT_TX (AG71XX_INT_TX_PS) +#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) + +#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) +#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) + +#define AG71XX_TX_MTU_LEN 1540 + +#define AG71XX_TX_RING_SPLIT 512 +#define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \ + AG71XX_TX_RING_SPLIT) +#define AG71XX_TX_RING_SIZE_DEFAULT 48 +#define AG71XX_RX_RING_SIZE_DEFAULT 128 + +#define AG71XX_TX_RING_SIZE_MAX 48 +#define AG71XX_RX_RING_SIZE_MAX 128 + +#ifdef CONFIG_AG71XX_DEBUG +#define DBG(fmt, args...) pr_debug(fmt, ## args) +#else +#define DBG(fmt, args...) do {} while (0) +#endif + +#define ag71xx_assert(_cond) \ +do { \ + if (_cond) \ + break; \ + printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ + BUG(); \ +} while (0) + +struct ag71xx_desc { + u32 data; + u32 ctrl; +#define DESC_EMPTY BIT(31) +#define DESC_MORE BIT(24) +#define DESC_PKTLEN_M 0xfff + u32 next; + u32 pad; +} __attribute__((aligned(4))); + +struct ag71xx_buf { + union { + struct sk_buff *skb; + void *rx_buf; + }; + union { + dma_addr_t dma_addr; + unsigned long timestamp; + }; + unsigned int len; +}; + +struct ag71xx_ring { + struct ag71xx_buf *buf; + u8 *descs_cpu; + dma_addr_t descs_dma; + u16 desc_split; + u16 desc_size; + unsigned int curr; + unsigned int dirty; + unsigned int size; +}; + +struct ag71xx_mdio { + struct mii_bus *mii_bus; + int mii_irq[PHY_MAX_ADDR]; + void __iomem *mdio_base; + struct ag71xx_mdio_platform_data *pdata; +}; + +struct ag71xx_int_stats { + unsigned long rx_pr; + unsigned long rx_be; + unsigned long rx_of; + unsigned long tx_ps; + unsigned long tx_be; + unsigned long tx_ur; + unsigned long total; +}; + +struct ag71xx_napi_stats { + unsigned long napi_calls; + unsigned long rx_count; + unsigned long rx_packets; + unsigned long rx_packets_max; + unsigned long tx_count; + unsigned long tx_packets; + unsigned long tx_packets_max; + + unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; + unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; +}; + +struct ag71xx_debug { + struct dentry *debugfs_dir; + + struct ag71xx_int_stats int_stats; + struct ag71xx_napi_stats napi_stats; +}; + +struct ag71xx { + void __iomem *mac_base; + + spinlock_t lock; + struct platform_device *pdev; + struct net_device *dev; + struct napi_struct napi; + u32 msg_enable; + + struct ag71xx_desc *stop_desc; + dma_addr_t stop_desc_dma; + + struct ag71xx_ring rx_ring; + struct ag71xx_ring tx_ring; + + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + void *phy_priv; + + unsigned int link; + unsigned int speed; + int duplex; + + unsigned int max_frame_len; + unsigned int desc_pktlen_mask; + unsigned int rx_buf_size; + + struct work_struct restart_work; + struct delayed_work link_work; + struct timer_list oom_timer; + +#ifdef CONFIG_AG71XX_DEBUG_FS + struct ag71xx_debug debug; +#endif +}; + +extern struct ethtool_ops ag71xx_ethtool_ops; +void ag71xx_link_adjust(struct ag71xx *ag); + +int ag71xx_mdio_driver_init(void) __init; +void ag71xx_mdio_driver_exit(void); + +int ag71xx_phy_connect(struct ag71xx *ag); +void ag71xx_phy_disconnect(struct ag71xx *ag); +void ag71xx_phy_start(struct ag71xx *ag); +void ag71xx_phy_stop(struct ag71xx *ag); + +static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) +{ + return ag->pdev->dev.platform_data; +} + +static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) +{ + return (desc->ctrl & DESC_EMPTY) != 0; +} + +static inline struct ag71xx_desc * +ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) +{ + return (struct ag71xx_desc *) &ring->descs_cpu[idx * ring->desc_size]; +} + +/* Register offsets */ +#define AG71XX_REG_MAC_CFG1 0x0000 +#define AG71XX_REG_MAC_CFG2 0x0004 +#define AG71XX_REG_MAC_IPG 0x0008 +#define AG71XX_REG_MAC_HDX 0x000c +#define AG71XX_REG_MAC_MFL 0x0010 +#define AG71XX_REG_MII_CFG 0x0020 +#define AG71XX_REG_MII_CMD 0x0024 +#define AG71XX_REG_MII_ADDR 0x0028 +#define AG71XX_REG_MII_CTRL 0x002c +#define AG71XX_REG_MII_STATUS 0x0030 +#define AG71XX_REG_MII_IND 0x0034 +#define AG71XX_REG_MAC_IFCTL 0x0038 +#define AG71XX_REG_MAC_ADDR1 0x0040 +#define AG71XX_REG_MAC_ADDR2 0x0044 +#define AG71XX_REG_FIFO_CFG0 0x0048 +#define AG71XX_REG_FIFO_CFG1 0x004c +#define AG71XX_REG_FIFO_CFG2 0x0050 +#define AG71XX_REG_FIFO_CFG3 0x0054 +#define AG71XX_REG_FIFO_CFG4 0x0058 +#define AG71XX_REG_FIFO_CFG5 0x005c +#define AG71XX_REG_FIFO_RAM0 0x0060 +#define AG71XX_REG_FIFO_RAM1 0x0064 +#define AG71XX_REG_FIFO_RAM2 0x0068 +#define AG71XX_REG_FIFO_RAM3 0x006c +#define AG71XX_REG_FIFO_RAM4 0x0070 +#define AG71XX_REG_FIFO_RAM5 0x0074 +#define AG71XX_REG_FIFO_RAM6 0x0078 +#define AG71XX_REG_FIFO_RAM7 0x007c + +#define AG71XX_REG_TX_CTRL 0x0180 +#define AG71XX_REG_TX_DESC 0x0184 +#define AG71XX_REG_TX_STATUS 0x0188 +#define AG71XX_REG_RX_CTRL 0x018c +#define AG71XX_REG_RX_DESC 0x0190 +#define AG71XX_REG_RX_STATUS 0x0194 +#define AG71XX_REG_INT_ENABLE 0x0198 +#define AG71XX_REG_INT_STATUS 0x019c + +#define AG71XX_REG_FIFO_DEPTH 0x01a8 +#define AG71XX_REG_RX_SM 0x01b0 +#define AG71XX_REG_TX_SM 0x01b4 + +#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ +#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ +#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ +#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ +#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ +#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ +#define MAC_CFG1_LB BIT(8) /* Loopback mode */ +#define MAC_CFG1_SR BIT(31) /* Soft Reset */ + +#define MAC_CFG2_FDX BIT(0) +#define MAC_CFG2_CRC_EN BIT(1) +#define MAC_CFG2_PAD_CRC_EN BIT(2) +#define MAC_CFG2_LEN_CHECK BIT(4) +#define MAC_CFG2_HUGE_FRAME_EN BIT(5) +#define MAC_CFG2_IF_1000 BIT(9) +#define MAC_CFG2_IF_10_100 BIT(8) + +#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ +#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ +#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ +#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ +#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ +#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ + | FIFO_CFG0_TXS | FIFO_CFG0_TXF) + +#define FIFO_CFG0_ENABLE_SHIFT 8 + +#define FIFO_CFG4_DE BIT(0) /* Drop Event */ +#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ +#define FIFO_CFG4_FC BIT(2) /* False Carrier */ +#define FIFO_CFG4_CE BIT(3) /* Code Error */ +#define FIFO_CFG4_CR BIT(4) /* CRC error */ +#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ +#define FIFO_CFG4_LO BIT(6) /* Length out of range */ +#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ +#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ +#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ +#define FIFO_CFG4_DR BIT(10) /* Dribble */ +#define FIFO_CFG4_LE BIT(11) /* Long Event */ +#define FIFO_CFG4_CF BIT(12) /* Control Frame */ +#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ +#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ +#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ +#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ +#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ + +#define FIFO_CFG5_DE BIT(0) /* Drop Event */ +#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ +#define FIFO_CFG5_FC BIT(2) /* False Carrier */ +#define FIFO_CFG5_CE BIT(3) /* Code Error */ +#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ +#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ +#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ +#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ +#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ +#define FIFO_CFG5_DR BIT(9) /* Dribble */ +#define FIFO_CFG5_CF BIT(10) /* Control Frame */ +#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ +#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ +#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ +#define FIFO_CFG5_LE BIT(14) /* Long Event */ +#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ +#define FIFO_CFG5_16 BIT(16) /* unknown */ +#define FIFO_CFG5_17 BIT(17) /* unknown */ +#define FIFO_CFG5_SF BIT(18) /* Short Frame */ +#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ + +#define AG71XX_INT_TX_PS BIT(0) +#define AG71XX_INT_TX_UR BIT(1) +#define AG71XX_INT_TX_BE BIT(3) +#define AG71XX_INT_RX_PR BIT(4) +#define AG71XX_INT_RX_OF BIT(6) +#define AG71XX_INT_RX_BE BIT(7) + +#define MAC_IFCTL_SPEED BIT(16) + +#define MII_CFG_CLK_DIV_4 0 +#define MII_CFG_CLK_DIV_6 2 +#define MII_CFG_CLK_DIV_8 3 +#define MII_CFG_CLK_DIV_10 4 +#define MII_CFG_CLK_DIV_14 5 +#define MII_CFG_CLK_DIV_20 6 +#define MII_CFG_CLK_DIV_28 7 +#define MII_CFG_CLK_DIV_34 8 +#define MII_CFG_CLK_DIV_42 9 +#define MII_CFG_CLK_DIV_50 10 +#define MII_CFG_CLK_DIV_58 11 +#define MII_CFG_CLK_DIV_66 12 +#define MII_CFG_CLK_DIV_74 13 +#define MII_CFG_CLK_DIV_82 14 +#define MII_CFG_CLK_DIV_98 15 +#define MII_CFG_RESET BIT(31) + +#define MII_CMD_WRITE 0x0 +#define MII_CMD_READ 0x1 +#define MII_ADDR_SHIFT 8 +#define MII_IND_BUSY BIT(0) +#define MII_IND_INVALID BIT(2) + +#define TX_CTRL_TXE BIT(0) /* Tx Enable */ + +#define TX_STATUS_PS BIT(0) /* Packet Sent */ +#define TX_STATUS_UR BIT(1) /* Tx Underrun */ +#define TX_STATUS_BE BIT(3) /* Bus Error */ + +#define RX_CTRL_RXE BIT(0) /* Rx Enable */ + +#define RX_STATUS_PR BIT(0) /* Packet Received */ +#define RX_STATUS_OF BIT(2) /* Rx Overflow */ +#define RX_STATUS_BE BIT(3) /* Bus Error */ + +static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) +{ + switch (reg) { + case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: + case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM: + case AG71XX_REG_MII_CFG: + break; + + default: + BUG(); + } +} + +static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) +{ + ag71xx_check_reg_offset(ag, reg); + + __raw_writel(value, ag->mac_base + reg); + /* flush write */ + (void) __raw_readl(ag->mac_base + reg); +} + +static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) +{ + ag71xx_check_reg_offset(ag, reg); + + return __raw_readl(ag->mac_base + reg); +} + +static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) +{ + void __iomem *r; + + ag71xx_check_reg_offset(ag, reg); + + r = ag->mac_base + reg; + __raw_writel(__raw_readl(r) | mask, r); + /* flush write */ + (void)__raw_readl(r); +} + +static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) +{ + void __iomem *r; + + ag71xx_check_reg_offset(ag, reg); + + r = ag->mac_base + reg; + __raw_writel(__raw_readl(r) & ~mask, r); + /* flush write */ + (void) __raw_readl(r); +} + +static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) +{ + ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); +} + +static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) +{ + ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); +} + +#ifdef CONFIG_AG71XX_AR8216_SUPPORT +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, + int pktlen); +static inline int ag71xx_has_ar8216(struct ag71xx *ag) +{ + return ag71xx_get_pdata(ag)->has_ar8216; +} +#else +static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, + struct sk_buff *skb) +{ +} + +static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, + struct sk_buff *skb, + int pktlen) +{ + return 0; +} +static inline int ag71xx_has_ar8216(struct ag71xx *ag) +{ + return 0; +} +#endif + +#ifdef CONFIG_AG71XX_DEBUG_FS +int ag71xx_debugfs_root_init(void); +void ag71xx_debugfs_root_exit(void); +int ag71xx_debugfs_init(struct ag71xx *ag); +void ag71xx_debugfs_exit(struct ag71xx *ag); +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); +#else +static inline int ag71xx_debugfs_root_init(void) { return 0; } +static inline void ag71xx_debugfs_root_exit(void) {} +static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } +static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} +static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, + u32 status) {} +static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, + int rx, int tx) {} +#endif /* CONFIG_AG71XX_DEBUG_FS */ + +void ag71xx_ar7240_start(struct ag71xx *ag); +void ag71xx_ar7240_stop(struct ag71xx *ag); +int ag71xx_ar7240_init(struct ag71xx *ag); +void ag71xx_ar7240_cleanup(struct ag71xx *ag); + +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg); +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val); + +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr); +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr, u16 reg_val); + +#endif /* _AG71XX_H */ diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c new file mode 100644 index 0000000..8dfff3b --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar7240.c @@ -0,0 +1,1229 @@ +/* + * Driver for the built-in ethernet switch of the Atheros AR7240 SoC + * Copyright (c) 2010 Gabor Juhos + * Copyright (c) 2010 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ag71xx.h" + +#define BITM(_count) (BIT(_count) - 1) +#define BITS(_shift, _count) (BITM(_count) << _shift) + +#define AR7240_REG_MASK_CTRL 0x00 +#define AR7240_MASK_CTRL_REVISION_M BITM(8) +#define AR7240_MASK_CTRL_VERSION_M BITM(8) +#define AR7240_MASK_CTRL_VERSION_S 8 +#define AR7240_MASK_CTRL_VERSION_AR7240 0x01 +#define AR7240_MASK_CTRL_VERSION_AR934X 0x02 +#define AR7240_MASK_CTRL_SOFT_RESET BIT(31) + +#define AR7240_REG_MAC_ADDR0 0x20 +#define AR7240_REG_MAC_ADDR1 0x24 + +#define AR7240_REG_FLOOD_MASK 0x2c +#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26) + +#define AR7240_REG_GLOBAL_CTRL 0x30 +#define AR7240_GLOBAL_CTRL_MTU_M BITM(11) +#define AR9340_GLOBAL_CTRL_MTU_M BITM(14) + +#define AR7240_REG_VTU 0x0040 +#define AR7240_VTU_OP BITM(3) +#define AR7240_VTU_OP_NOOP 0x0 +#define AR7240_VTU_OP_FLUSH 0x1 +#define AR7240_VTU_OP_LOAD 0x2 +#define AR7240_VTU_OP_PURGE 0x3 +#define AR7240_VTU_OP_REMOVE_PORT 0x4 +#define AR7240_VTU_ACTIVE BIT(3) +#define AR7240_VTU_FULL BIT(4) +#define AR7240_VTU_PORT BITS(8, 4) +#define AR7240_VTU_PORT_S 8 +#define AR7240_VTU_VID BITS(16, 12) +#define AR7240_VTU_VID_S 16 +#define AR7240_VTU_PRIO BITS(28, 3) +#define AR7240_VTU_PRIO_S 28 +#define AR7240_VTU_PRIO_EN BIT(31) + +#define AR7240_REG_VTU_DATA 0x0044 +#define AR7240_VTUDATA_MEMBER BITS(0, 10) +#define AR7240_VTUDATA_VALID BIT(11) + +#define AR7240_REG_ATU 0x50 +#define AR7240_ATU_FLUSH_ALL 0x1 + +#define AR7240_REG_AT_CTRL 0x5c +#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15) +#define AR7240_AT_CTRL_AGE_EN BIT(17) +#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18) +#define AR7240_AT_CTRL_RESERVED BIT(19) +#define AR7240_AT_CTRL_ARP_EN BIT(20) + +#define AR7240_REG_TAG_PRIORITY 0x70 + +#define AR7240_REG_SERVICE_TAG 0x74 +#define AR7240_SERVICE_TAG_M BITM(16) + +#define AR7240_REG_CPU_PORT 0x78 +#define AR7240_MIRROR_PORT_S 4 +#define AR7240_CPU_PORT_EN BIT(8) + +#define AR7240_REG_MIB_FUNCTION0 0x80 +#define AR7240_MIB_TIMER_M BITM(16) +#define AR7240_MIB_AT_HALF_EN BIT(16) +#define AR7240_MIB_BUSY BIT(17) +#define AR7240_MIB_FUNC_S 24 +#define AR7240_MIB_FUNC_M BITM(3) +#define AR7240_MIB_FUNC_NO_OP 0x0 +#define AR7240_MIB_FUNC_FLUSH 0x1 +#define AR7240_MIB_FUNC_CAPTURE 0x3 + +#define AR7240_REG_MDIO_CTRL 0x98 +#define AR7240_MDIO_CTRL_DATA_M BITM(16) +#define AR7240_MDIO_CTRL_REG_ADDR_S 16 +#define AR7240_MDIO_CTRL_PHY_ADDR_S 21 +#define AR7240_MDIO_CTRL_CMD_WRITE 0 +#define AR7240_MDIO_CTRL_CMD_READ BIT(27) +#define AR7240_MDIO_CTRL_MASTER_EN BIT(30) +#define AR7240_MDIO_CTRL_BUSY BIT(31) + +#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) + +#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00) +#define AR7240_PORT_STATUS_SPEED_S 0 +#define AR7240_PORT_STATUS_SPEED_M BITM(2) +#define AR7240_PORT_STATUS_SPEED_10 0 +#define AR7240_PORT_STATUS_SPEED_100 1 +#define AR7240_PORT_STATUS_SPEED_1000 2 +#define AR7240_PORT_STATUS_TXMAC BIT(2) +#define AR7240_PORT_STATUS_RXMAC BIT(3) +#define AR7240_PORT_STATUS_TXFLOW BIT(4) +#define AR7240_PORT_STATUS_RXFLOW BIT(5) +#define AR7240_PORT_STATUS_DUPLEX BIT(6) +#define AR7240_PORT_STATUS_LINK_UP BIT(8) +#define AR7240_PORT_STATUS_LINK_AUTO BIT(9) +#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10) + +#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04) +#define AR7240_PORT_CTRL_STATE_M BITM(3) +#define AR7240_PORT_CTRL_STATE_DISABLED 0 +#define AR7240_PORT_CTRL_STATE_BLOCK 1 +#define AR7240_PORT_CTRL_STATE_LISTEN 2 +#define AR7240_PORT_CTRL_STATE_LEARN 3 +#define AR7240_PORT_CTRL_STATE_FORWARD 4 +#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7) +#define AR7240_PORT_CTRL_VLAN_MODE_S 8 +#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0 +#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1 +#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2 +#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3 +#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10) +#define AR7240_PORT_CTRL_HEADER BIT(11) +#define AR7240_PORT_CTRL_MAC_LOOP BIT(12) +#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13) +#define AR7240_PORT_CTRL_LEARN BIT(14) +#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15) +#define AR7240_PORT_CTRL_MIRROR_TX BIT(16) +#define AR7240_PORT_CTRL_MIRROR_RX BIT(17) + +#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08) + +#define AR7240_PORT_VLAN_DEFAULT_ID_S 0 +#define AR7240_PORT_VLAN_DEST_PORTS_S 16 +#define AR7240_PORT_VLAN_MODE_S 30 +#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0 +#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1 +#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2 +#define AR7240_PORT_VLAN_MODE_SECURE 3 + + +#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100) + +#define AR7240_STATS_RXBROAD 0x00 +#define AR7240_STATS_RXPAUSE 0x04 +#define AR7240_STATS_RXMULTI 0x08 +#define AR7240_STATS_RXFCSERR 0x0c +#define AR7240_STATS_RXALIGNERR 0x10 +#define AR7240_STATS_RXRUNT 0x14 +#define AR7240_STATS_RXFRAGMENT 0x18 +#define AR7240_STATS_RX64BYTE 0x1c +#define AR7240_STATS_RX128BYTE 0x20 +#define AR7240_STATS_RX256BYTE 0x24 +#define AR7240_STATS_RX512BYTE 0x28 +#define AR7240_STATS_RX1024BYTE 0x2c +#define AR7240_STATS_RX1518BYTE 0x30 +#define AR7240_STATS_RXMAXBYTE 0x34 +#define AR7240_STATS_RXTOOLONG 0x38 +#define AR7240_STATS_RXGOODBYTE 0x3c +#define AR7240_STATS_RXBADBYTE 0x44 +#define AR7240_STATS_RXOVERFLOW 0x4c +#define AR7240_STATS_FILTERED 0x50 +#define AR7240_STATS_TXBROAD 0x54 +#define AR7240_STATS_TXPAUSE 0x58 +#define AR7240_STATS_TXMULTI 0x5c +#define AR7240_STATS_TXUNDERRUN 0x60 +#define AR7240_STATS_TX64BYTE 0x64 +#define AR7240_STATS_TX128BYTE 0x68 +#define AR7240_STATS_TX256BYTE 0x6c +#define AR7240_STATS_TX512BYTE 0x70 +#define AR7240_STATS_TX1024BYTE 0x74 +#define AR7240_STATS_TX1518BYTE 0x78 +#define AR7240_STATS_TXMAXBYTE 0x7c +#define AR7240_STATS_TXOVERSIZE 0x80 +#define AR7240_STATS_TXBYTE 0x84 +#define AR7240_STATS_TXCOLLISION 0x8c +#define AR7240_STATS_TXABORTCOL 0x90 +#define AR7240_STATS_TXMULTICOL 0x94 +#define AR7240_STATS_TXSINGLECOL 0x98 +#define AR7240_STATS_TXEXCDEFER 0x9c +#define AR7240_STATS_TXDEFER 0xa0 +#define AR7240_STATS_TXLATECOL 0xa4 + +#define AR7240_PORT_CPU 0 +#define AR7240_NUM_PORTS 6 +#define AR7240_NUM_PHYS 5 + +#define AR7240_PHY_ID1 0x004d +#define AR7240_PHY_ID2 0xd041 + +#define AR934X_PHY_ID1 0x004d +#define AR934X_PHY_ID2 0xd042 + +#define AR7240_MAX_VLANS 16 + +#define AR934X_REG_OPER_MODE0 0x04 +#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6) +#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10) + +#define AR934X_REG_OPER_MODE1 0x08 +#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28) + +#define AR934X_REG_FLOOD_MASK 0x2c +#define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p)) +#define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p)) + +#define AR934X_REG_QM_CTRL 0x3c +#define AR934X_QM_CTRL_ARP_EN BIT(15) + +#define AR934X_REG_AT_CTRL 0x5c +#define AR934X_AT_CTRL_AGE_TIME BITS(0, 15) +#define AR934X_AT_CTRL_AGE_EN BIT(17) +#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18) + +#define AR934X_MIB_ENABLE BIT(30) + +#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) + +#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) +#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0 +#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12) +#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13) +#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14) +#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15) +#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16 +#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28) +#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29 + +#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c) +#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16 +#define AR934X_PORT_VLAN2_8021Q_MODE_S 30 +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0 +#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1 +#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2 +#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3 + +#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev) + +struct ar7240sw_port_stat { + unsigned long rx_broadcast; + unsigned long rx_pause; + unsigned long rx_multicast; + unsigned long rx_fcs_error; + unsigned long rx_align_error; + unsigned long rx_runt; + unsigned long rx_fragments; + unsigned long rx_64byte; + unsigned long rx_128byte; + unsigned long rx_256byte; + unsigned long rx_512byte; + unsigned long rx_1024byte; + unsigned long rx_1518byte; + unsigned long rx_maxbyte; + unsigned long rx_toolong; + unsigned long rx_good_byte; + unsigned long rx_bad_byte; + unsigned long rx_overflow; + unsigned long filtered; + + unsigned long tx_broadcast; + unsigned long tx_pause; + unsigned long tx_multicast; + unsigned long tx_underrun; + unsigned long tx_64byte; + unsigned long tx_128byte; + unsigned long tx_256byte; + unsigned long tx_512byte; + unsigned long tx_1024byte; + unsigned long tx_1518byte; + unsigned long tx_maxbyte; + unsigned long tx_oversize; + unsigned long tx_byte; + unsigned long tx_collision; + unsigned long tx_abortcol; + unsigned long tx_multicol; + unsigned long tx_singlecol; + unsigned long tx_excdefer; + unsigned long tx_defer; + unsigned long tx_xlatecol; +}; + +struct ar7240sw { + struct mii_bus *mii_bus; + struct ag71xx_switch_platform_data *swdata; + struct switch_dev swdev; + int num_ports; + u8 ver; + bool vlan; + u16 vlan_id[AR7240_MAX_VLANS]; + u8 vlan_table[AR7240_MAX_VLANS]; + u8 vlan_tagged; + u16 pvid[AR7240_NUM_PORTS]; + char buf[80]; + + rwlock_t stats_lock; + struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS]; +}; + +struct ar7240sw_hw_stat { + char string[ETH_GSTRING_LEN]; + int sizeof_stat; + int reg; +}; + +static DEFINE_MUTEX(reg_mutex); + +static inline int sw_is_ar7240(struct ar7240sw *as) +{ + return as->ver == AR7240_MASK_CTRL_VERSION_AR7240; +} + +static inline int sw_is_ar934x(struct ar7240sw *as) +{ + return as->ver == AR7240_MASK_CTRL_VERSION_AR934X; +} + +static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port) +{ + return BIT(port); +} + +static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as) +{ + return BIT(as->swdev.ports) - 1; +} + +static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port) +{ + return ar7240sw_port_mask_all(as) & ~BIT(port); +} + +static inline u16 mk_phy_addr(u32 reg) +{ + return 0x17 & ((reg >> 4) | 0x10); +} + +static inline u16 mk_phy_reg(u32 reg) +{ + return (reg << 1) & 0x1e; +} + +static inline u16 mk_high_addr(u32 reg) +{ + return (reg >> 7) & 0x1ff; +} + +static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg) +{ + unsigned long flags; + u16 phy_addr; + u16 phy_reg; + u32 hi, lo; + + reg = (reg & 0xfffffffc) >> 2; + phy_addr = mk_phy_addr(reg); + phy_reg = mk_phy_reg(reg); + + local_irq_save(flags); + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); + lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg); + hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1); + local_irq_restore(flags); + + return (hi << 16) | lo; +} + +static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val) +{ + unsigned long flags; + u16 phy_addr; + u16 phy_reg; + + reg = (reg & 0xfffffffc) >> 2; + phy_addr = mk_phy_addr(reg); + phy_reg = mk_phy_reg(reg); + + local_irq_save(flags); + ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16)); + ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff)); + local_irq_restore(flags); +} + +static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr) +{ + u32 ret; + + mutex_lock(®_mutex); + ret = __ar7240sw_reg_read(mii, reg_addr); + mutex_unlock(®_mutex); + + return ret; +} + +static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val) +{ + mutex_lock(®_mutex); + __ar7240sw_reg_write(mii, reg_addr, reg_val); + mutex_unlock(®_mutex); +} + +static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val) +{ + u32 t; + + mutex_lock(®_mutex); + t = __ar7240sw_reg_read(mii, reg); + t &= ~mask; + t |= val; + __ar7240sw_reg_write(mii, reg, t); + mutex_unlock(®_mutex); + + return t; +} + +static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val) +{ + u32 t; + + mutex_lock(®_mutex); + t = __ar7240sw_reg_read(mii, reg); + t |= val; + __ar7240sw_reg_write(mii, reg, t); + mutex_unlock(®_mutex); +} + +static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, + unsigned timeout) +{ + int i; + + for (i = 0; i < timeout; i++) { + u32 t; + + t = __ar7240sw_reg_read(mii, reg); + if ((t & mask) == val) + return 0; + + usleep_range(1000, 2000); + } + + return -ETIMEDOUT; +} + +static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, + unsigned timeout) +{ + int ret; + + mutex_lock(®_mutex); + ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout); + mutex_unlock(®_mutex); + return ret; +} + +u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr) +{ + u32 t, val = 0xffff; + int err; + + if (phy_addr >= AR7240_NUM_PHYS) + return 0xffff; + + mutex_lock(®_mutex); + t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | + (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | + AR7240_MDIO_CTRL_MASTER_EN | + AR7240_MDIO_CTRL_BUSY | + AR7240_MDIO_CTRL_CMD_READ; + + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); + err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, + AR7240_MDIO_CTRL_BUSY, 0, 5); + if (!err) + val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL); + mutex_unlock(®_mutex); + + return val & AR7240_MDIO_CTRL_DATA_M; +} + +int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, + unsigned reg_addr, u16 reg_val) +{ + u32 t; + int ret; + + if (phy_addr >= AR7240_NUM_PHYS) + return -EINVAL; + + mutex_lock(®_mutex); + t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | + (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | + AR7240_MDIO_CTRL_MASTER_EN | + AR7240_MDIO_CTRL_BUSY | + AR7240_MDIO_CTRL_CMD_WRITE | + reg_val; + + __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); + ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, + AR7240_MDIO_CTRL_BUSY, 0, 5); + mutex_unlock(®_mutex); + + return ret; +} + +static int ar7240sw_capture_stats(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + int port; + int ret; + + write_lock(&as->stats_lock); + + /* Capture the hardware statistics for all ports */ + ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0, + (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S), + (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); + + /* Wait for the capturing to complete. */ + ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0, + AR7240_MIB_BUSY, 0, 10); + + if (ret) + goto unlock; + + for (port = 0; port < AR7240_NUM_PORTS; port++) { + unsigned int base; + struct ar7240sw_port_stat *stats; + + base = AR7240_REG_STATS_BASE(port); + stats = &as->port_stats[port]; + +#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r) + + stats->rx_good_byte += READ_STAT(RXGOODBYTE); + stats->tx_byte += READ_STAT(TXBYTE); + +#undef READ_STAT + } + + ret = 0; + +unlock: + write_unlock(&as->stats_lock); + return ret; +} + +static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port) +{ + ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port), + AR7240_PORT_CTRL_STATE_DISABLED); +} + +static void ar7240sw_setup(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + + /* Enable CPU port, and disable mirror port */ + ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT, + AR7240_CPU_PORT_EN | + (15 << AR7240_MIRROR_PORT_S)); + + /* Setup TAG priority mapping */ + ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50); + + if (sw_is_ar934x(as)) { + /* Enable aging, MAC replacing */ + ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL, + 0x2b /* 5 min age time */ | + AR934X_AT_CTRL_AGE_EN | + AR934X_AT_CTRL_LEARN_CHANGE); + /* Enable ARP frame acknowledge */ + ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL, + AR934X_QM_CTRL_ARP_EN); + /* Enable Broadcast/Multicast frames transmitted to the CPU */ + ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK, + AR934X_FLOOD_MASK_BC_DP(0) | + AR934X_FLOOD_MASK_MC_DP(0)); + + /* setup MTU */ + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, + AR9340_GLOBAL_CTRL_MTU_M, + AR9340_GLOBAL_CTRL_MTU_M); + + /* Enable MIB counters */ + ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0, + AR934X_MIB_ENABLE); + + } else { + /* Enable ARP frame acknowledge, aging, MAC replacing */ + ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL, + AR7240_AT_CTRL_RESERVED | + 0x2b /* 5 min age time */ | + AR7240_AT_CTRL_AGE_EN | + AR7240_AT_CTRL_ARP_EN | + AR7240_AT_CTRL_LEARN_CHANGE); + /* Enable Broadcast frames transmitted to the CPU */ + ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK, + AR7240_FLOOD_MASK_BROAD_TO_CPU); + + /* setup MTU */ + ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, + AR7240_GLOBAL_CTRL_MTU_M, + AR7240_GLOBAL_CTRL_MTU_M); + } + + /* setup Service TAG */ + ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0); +} + +/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */ +static int +ar7240sw_phy_poll_reset(struct mii_bus *bus) +{ + const unsigned int sleep_msecs = 20; + int ret, elapsed, i; + + for (elapsed = sleep_msecs; elapsed <= 600; + elapsed += sleep_msecs) { + msleep(sleep_msecs); + for (i = 0; i < AR7240_NUM_PHYS; i++) { + ret = ar7240sw_phy_read(bus, i, MII_BMCR); + if (ret < 0) + return ret; + if (ret & BMCR_RESET) + break; + if (i == AR7240_NUM_PHYS - 1) { + usleep_range(1000, 2000); + return 0; + } + } + } + return -ETIMEDOUT; +} + +static int ar7240sw_reset(struct ar7240sw *as) +{ + struct mii_bus *mii = as->mii_bus; + int ret; + int i; + + /* Set all ports to disabled state. */ + for (i = 0; i < AR7240_NUM_PORTS; i++) + ar7240sw_disable_port(as, i); + + /* Wait for transmit queues to drain. */ + usleep_range(2000, 3000); + + /* Reset the switch. */ + ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL, + AR7240_MASK_CTRL_SOFT_RESET); + + ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL, + AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); + + /* setup PHYs */ + for (i = 0; i < AR7240_NUM_PHYS; i++) { + ar7240sw_phy_write(mii, i, MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + ar7240sw_phy_write(mii, i, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); + } + ret = ar7240sw_phy_poll_reset(mii); + if (ret) + return ret; + + ar7240sw_setup(as); + return ret; +} + +static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask) +{ + struct mii_bus *mii = as->mii_bus; + u32 ctrl; + u32 vid, mode; + + ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN | + AR7240_PORT_CTRL_SINGLE_VLAN; + + if (port == AR7240_PORT_CPU) { + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), + AR7240_PORT_STATUS_SPEED_1000 | + AR7240_PORT_STATUS_TXFLOW | + AR7240_PORT_STATUS_RXFLOW | + AR7240_PORT_STATUS_TXMAC | + AR7240_PORT_STATUS_RXMAC | + AR7240_PORT_STATUS_DUPLEX); + } else { + ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), + AR7240_PORT_STATUS_LINK_AUTO); + } + + /* Set the default VID for this port */ + if (as->vlan) { + vid = as->vlan_id[as->pvid[port]]; + mode = AR7240_PORT_VLAN_MODE_SECURE; + } else { + vid = port; + mode = AR7240_PORT_VLAN_MODE_PORT_ONLY; + } + + if (as->vlan) { + if (as->vlan_tagged & BIT(port)) + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD << + AR7240_PORT_CTRL_VLAN_MODE_S; + else + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP << + AR7240_PORT_CTRL_VLAN_MODE_S; + } else { + ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP << + AR7240_PORT_CTRL_VLAN_MODE_S; + } + + if (!portmask) { + if (port == AR7240_PORT_CPU) + portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU); + else + portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU); + } + + /* allow the port to talk to all other ports, but exclude its + * own ID to prevent frames from being reflected back to the + * port that they came from */ + portmask &= ar7240sw_port_mask_but(as, port); + + ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl); + if (sw_is_ar934x(as)) { + u32 vlan1, vlan2; + + vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S); + vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) | + (mode << AR934X_PORT_VLAN2_8021Q_MODE_S); + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1); + ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2); + } else { + u32 vlan; + + vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) | + (portmask << AR7240_PORT_VLAN_DEST_PORTS_S); + + ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan); + } +} + +static int ar7240_set_addr(struct ar7240sw *as, u8 *addr) +{ + struct mii_bus *mii = as->mii_bus; + u32 t; + + t = (addr[4] << 8) | addr[5]; + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t); + + t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; + ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t); + + return 0; +} + +static int +ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + as->vlan_id[val->port_vlan] = val->value.i; + return 0; +} + +static int +ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + val->value.i = as->vlan_id[val->port_vlan]; + return 0; +} + +static int +ar7240_set_pvid(struct switch_dev *dev, int port, int vlan) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + + /* make sure no invalid PVIDs get set */ + + if (vlan >= dev->vlans) + return -EINVAL; + + as->pvid[port] = vlan; + return 0; +} + +static int +ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + *vlan = as->pvid[port]; + return 0; +} + +static int +ar7240_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 ports = as->vlan_table[val->port_vlan]; + int i; + + val->len = 0; + for (i = 0; i < as->swdev.ports; i++) { + struct switch_port *p; + + if (!(ports & (1 << i))) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if (as->vlan_tagged & (1 << i)) + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); + else + p->flags = 0; + } + return 0; +} + +static int +ar7240_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 *vt = &as->vlan_table[val->port_vlan]; + int i, j; + + *vt = 0; + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) + as->vlan_tagged |= (1 << p->id); + else { + as->vlan_tagged &= ~(1 << p->id); + as->pvid[p->id] = val->port_vlan; + + /* make sure that an untagged port does not + * appear in other vlans */ + for (j = 0; j < AR7240_MAX_VLANS; j++) { + if (j == val->port_vlan) + continue; + as->vlan_table[j] &= ~(1 << p->id); + } + } + + *vt |= 1 << p->id; + } + return 0; +} + +static int +ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + as->vlan = !!val->value.i; + return 0; +} + +static int +ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + val->value.i = as->vlan; + return 0; +} + +static void +ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val) +{ + struct mii_bus *mii = as->mii_bus; + + if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5)) + return; + + if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) { + val &= AR7240_VTUDATA_MEMBER; + val |= AR7240_VTUDATA_VALID; + ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val); + } + op |= AR7240_VTU_ACTIVE; + ar7240sw_reg_write(mii, AR7240_REG_VTU, op); +} + +static int +ar7240_hw_apply(struct switch_dev *dev) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + u8 portmask[AR7240_NUM_PORTS]; + int i, j; + + /* flush all vlan translation unit entries */ + ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0); + + memset(portmask, 0, sizeof(portmask)); + if (as->vlan) { + /* calculate the port destination masks and load vlans + * into the vlan translation unit */ + for (j = 0; j < AR7240_MAX_VLANS; j++) { + u8 vp = as->vlan_table[j]; + + if (!vp) + continue; + + for (i = 0; i < as->swdev.ports; i++) { + u8 mask = (1 << i); + if (vp & mask) + portmask[i] |= vp & ~mask; + } + + ar7240_vtu_op(as, + AR7240_VTU_OP_LOAD | + (as->vlan_id[j] << AR7240_VTU_VID_S), + as->vlan_table[j]); + } + } else { + /* vlan disabled: + * isolate all ports, but connect them to the cpu port */ + for (i = 0; i < as->swdev.ports; i++) { + if (i == AR7240_PORT_CPU) + continue; + + portmask[i] = 1 << AR7240_PORT_CPU; + portmask[AR7240_PORT_CPU] |= (1 << i); + } + } + + /* update the port destination mask registers and tag settings */ + for (i = 0; i < as->swdev.ports; i++) + ar7240sw_setup_port(as, i, portmask[i]); + + return 0; +} + +static int +ar7240_reset_switch(struct switch_dev *dev) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + ar7240sw_reset(as); + return 0; +} + +static int +ar7240_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + struct mii_bus *mii = as->mii_bus; + u32 status; + + if (port > AR7240_NUM_PORTS) + return -EINVAL; + + status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port)); + link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO); + if (link->aneg) { + link->link = !!(status & AR7240_PORT_STATUS_LINK_UP); + if (!link->link) + return 0; + } else { + link->link = true; + } + + link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX); + link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW); + link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW); + switch (status & AR7240_PORT_STATUS_SPEED_M) { + case AR7240_PORT_STATUS_SPEED_10: + link->speed = SWITCH_PORT_SPEED_10; + break; + case AR7240_PORT_STATUS_SPEED_100: + link->speed = SWITCH_PORT_SPEED_100; + break; + case AR7240_PORT_STATUS_SPEED_1000: + link->speed = SWITCH_PORT_SPEED_1000; + break; + } + + return 0; +} + +static int +ar7240_get_port_stats(struct switch_dev *dev, int port, + struct switch_port_stats *stats) +{ + struct ar7240sw *as = sw_to_ar7240(dev); + + if (port > AR7240_NUM_PORTS) + return -EINVAL; + + ar7240sw_capture_stats(as); + + read_lock(&as->stats_lock); + stats->rx_bytes = as->port_stats[port].rx_good_byte; + stats->tx_bytes = as->port_stats[port].tx_byte; + read_unlock(&as->stats_lock); + + return 0; +} + +static struct switch_attr ar7240_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = ar7240_set_vlan, + .get = ar7240_get_vlan, + .max = 1 + }, +}; + +static struct switch_attr ar7240_port[] = { +}; + +static struct switch_attr ar7240_vlan[] = { + { + .type = SWITCH_TYPE_INT, + .name = "vid", + .description = "VLAN ID", + .set = ar7240_set_vid, + .get = ar7240_get_vid, + .max = 4094, + }, +}; + +static const struct switch_dev_ops ar7240_ops = { + .attr_global = { + .attr = ar7240_globals, + .n_attr = ARRAY_SIZE(ar7240_globals), + }, + .attr_port = { + .attr = ar7240_port, + .n_attr = ARRAY_SIZE(ar7240_port), + }, + .attr_vlan = { + .attr = ar7240_vlan, + .n_attr = ARRAY_SIZE(ar7240_vlan), + }, + .get_port_pvid = ar7240_get_pvid, + .set_port_pvid = ar7240_set_pvid, + .get_vlan_ports = ar7240_get_ports, + .set_vlan_ports = ar7240_set_ports, + .apply_config = ar7240_hw_apply, + .reset_switch = ar7240_reset_switch, + .get_port_link = ar7240_get_port_link, + .get_port_stats = ar7240_get_port_stats, +}; + +static struct ar7240sw *ar7240_probe(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct mii_bus *mii = ag->mii_bus; + struct ar7240sw *as; + struct switch_dev *swdev; + u32 ctrl; + u16 phy_id1; + u16 phy_id2; + int i; + + phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1); + phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2); + if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) && + (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) { + pr_err("%s: unknown phy id '%04x:%04x'\n", + dev_name(&mii->dev), phy_id1, phy_id2); + return NULL; + } + + as = kzalloc(sizeof(*as), GFP_KERNEL); + if (!as) + return NULL; + + as->mii_bus = mii; + as->swdata = pdata->switch_data; + + swdev = &as->swdev; + + ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL); + as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & + AR7240_MASK_CTRL_VERSION_M; + + if (sw_is_ar7240(as)) { + swdev->name = "AR7240/AR9330 built-in switch"; + swdev->ports = AR7240_NUM_PORTS - 1; + } else if (sw_is_ar934x(as)) { + swdev->name = "AR934X built-in switch"; + + if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0, + AR934X_OPER_MODE0_MAC_GMII_EN); + } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0, + AR934X_OPER_MODE0_PHY_MII_EN); + } else { + pr_err("%s: invalid PHY interface mode\n", + dev_name(&mii->dev)); + goto err_free; + } + + if (as->swdata->phy4_mii_en) { + ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1, + AR934X_REG_OPER_MODE1_PHY4_MII_EN); + swdev->ports = AR7240_NUM_PORTS - 1; + } else { + swdev->ports = AR7240_NUM_PORTS; + } + } else { + pr_err("%s: unsupported chip, ctrl=%08x\n", + dev_name(&mii->dev), ctrl); + goto err_free; + } + + swdev->cpu_port = AR7240_PORT_CPU; + swdev->vlans = AR7240_MAX_VLANS; + swdev->ops = &ar7240_ops; + + if (register_switch(&as->swdev, ag->dev) < 0) + goto err_free; + + pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name); + + /* initialize defaults */ + for (i = 0; i < AR7240_MAX_VLANS; i++) + as->vlan_id[i] = i; + + as->vlan_table[0] = ar7240sw_port_mask_all(as); + + return as; + +err_free: + kfree(as); + return NULL; +} + +static void link_function(struct work_struct *work) { + struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work); + struct ar7240sw *as = ag->phy_priv; + unsigned long flags; + u8 mask; + int i; + int status = 0; + + mask = ~as->swdata->phy_poll_mask; + for (i = 0; i < AR7240_NUM_PHYS; i++) { + int link; + + if (!(mask & BIT(i))) + continue; + + link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR); + if (link & BMSR_LSTATUS) { + status = 1; + break; + } + } + + spin_lock_irqsave(&ag->lock, flags); + if (status != ag->link) { + ag->link = status; + ag71xx_link_adjust(ag); + } + spin_unlock_irqrestore(&ag->lock, flags); + + schedule_delayed_work(&ag->link_work, HZ / 2); +} + +void ag71xx_ar7240_start(struct ag71xx *ag) +{ + struct ar7240sw *as = ag->phy_priv; + + ar7240sw_reset(as); + + ag->speed = SPEED_1000; + ag->duplex = 1; + + ar7240_set_addr(as, ag->dev->dev_addr); + ar7240_hw_apply(&as->swdev); + + schedule_delayed_work(&ag->link_work, HZ / 10); +} + +void ag71xx_ar7240_stop(struct ag71xx *ag) +{ + cancel_delayed_work_sync(&ag->link_work); +} + +int ag71xx_ar7240_init(struct ag71xx *ag) +{ + struct ar7240sw *as; + + as = ar7240_probe(ag); + if (!as) + return -ENODEV; + + ag->phy_priv = as; + ar7240sw_reset(as); + + rwlock_init(&as->stats_lock); + INIT_DELAYED_WORK(&ag->link_work, link_function); + + return 0; +} + +void ag71xx_ar7240_cleanup(struct ag71xx *ag) +{ + struct ar7240sw *as = ag->phy_priv; + + if (!as) + return; + + unregister_switch(&as->swdev); + kfree(as); + ag->phy_priv = NULL; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c new file mode 100644 index 0000000..7ec43b7 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ar8216.c @@ -0,0 +1,44 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * Special support for the Atheros ar8216 switch chip + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AR8216_PACKET_TYPE_MASK 0xf +#define AR8216_PACKET_TYPE_NORMAL 0 + +#define AR8216_HEADER_LEN 2 + +void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) +{ + skb_push(skb, AR8216_HEADER_LEN); + skb->data[0] = 0x10; + skb->data[1] = 0x80; +} + +int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, + int pktlen) +{ + u8 type; + + type = skb->data[1] & AR8216_PACKET_TYPE_MASK; + switch (type) { + case AR8216_PACKET_TYPE_NORMAL: + break; + + default: + return -EINVAL; + } + + skb_pull(skb, AR8216_HEADER_LEN); + return 0; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c new file mode 100644 index 0000000..c480121 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c @@ -0,0 +1,285 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include + +#include "ag71xx.h" + +static struct dentry *ag71xx_debugfs_root; + +static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) +{ + if (status) + ag->debug.int_stats.total++; + if (status & AG71XX_INT_TX_PS) + ag->debug.int_stats.tx_ps++; + if (status & AG71XX_INT_TX_UR) + ag->debug.int_stats.tx_ur++; + if (status & AG71XX_INT_TX_BE) + ag->debug.int_stats.tx_be++; + if (status & AG71XX_INT_RX_PR) + ag->debug.int_stats.rx_pr++; + if (status & AG71XX_INT_RX_OF) + ag->debug.int_stats.rx_of++; + if (status & AG71XX_INT_RX_BE) + ag->debug.int_stats.rx_be++; +} + +static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ +#define PR_INT_STAT(_label, _field) \ + len += snprintf(buf + len, sizeof(buf) - len, \ + "%20s: %10lu\n", _label, ag->debug.int_stats._field); + + struct ag71xx *ag = file->private_data; + char buf[256]; + unsigned int len = 0; + + PR_INT_STAT("TX Packet Sent", tx_ps); + PR_INT_STAT("TX Underrun", tx_ur); + PR_INT_STAT("TX Bus Error", tx_be); + PR_INT_STAT("RX Packet Received", rx_pr); + PR_INT_STAT("RX Overflow", rx_of); + PR_INT_STAT("RX Bus Error", rx_be); + len += snprintf(buf + len, sizeof(buf) - len, "\n"); + PR_INT_STAT("Total", total); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +#undef PR_INT_STAT +} + +static const struct file_operations ag71xx_fops_int_stats = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_int_stats, + .owner = THIS_MODULE +}; + +void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) +{ + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; + + if (rx) { + stats->rx_count++; + stats->rx_packets += rx; + if (rx <= AG71XX_NAPI_WEIGHT) + stats->rx[rx]++; + if (rx > stats->rx_packets_max) + stats->rx_packets_max = rx; + } + + if (tx) { + stats->tx_count++; + stats->tx_packets += tx; + if (tx <= AG71XX_NAPI_WEIGHT) + stats->tx[tx]++; + if (tx > stats->tx_packets_max) + stats->tx_packets_max = tx; + } +} + +static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; + char *buf; + unsigned int buflen; + unsigned int len = 0; + unsigned long rx_avg = 0; + unsigned long tx_avg = 0; + int ret; + int i; + + buflen = 2048; + buf = kmalloc(buflen, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + if (stats->rx_count) + rx_avg = stats->rx_packets / stats->rx_count; + + if (stats->tx_count) + tx_avg = stats->tx_packets / stats->tx_count; + + len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n", + "len", "rx", "tx"); + + for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) + len += snprintf(buf + len, buflen - len, + "%3d: %10lu %10lu\n", + i, stats->rx[i], stats->tx[i]); + + len += snprintf(buf + len, buflen - len, "\n"); + + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "sum", stats->rx_count, stats->tx_count); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "avg", rx_avg, tx_avg); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "max", stats->rx_packets_max, stats->tx_packets_max); + len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", + "pkt", stats->rx_packets, stats->tx_packets); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return ret; +} + +static const struct file_operations ag71xx_fops_napi_stats = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_napi_stats, + .owner = THIS_MODULE +}; + +#define DESC_PRINT_LEN 64 + +static ssize_t read_file_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos, + struct ag71xx *ag, + struct ag71xx_ring *ring, + unsigned desc_reg) +{ + char *buf; + unsigned int buflen; + unsigned int len = 0; + unsigned long flags; + ssize_t ret; + int curr; + int dirty; + u32 desc_hw; + int i; + + buflen = (ring->size * DESC_PRINT_LEN); + buf = kmalloc(buflen, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + len += snprintf(buf + len, buflen - len, + "Idx ... %-8s %-8s %-8s %-8s . %-10s\n", + "desc", "next", "data", "ctrl", "timestamp"); + + spin_lock_irqsave(&ag->lock, flags); + + curr = (ring->curr % ring->size); + dirty = (ring->dirty % ring->size); + desc_hw = ag71xx_rr(ag, desc_reg); + for (i = 0; i < ring->size; i++) { + struct ag71xx_buf *ab = &ring->buf[i]; + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size; + + len += snprintf(buf + len, buflen - len, + "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n", + i, + (i == curr) ? 'C' : ' ', + (i == dirty) ? 'D' : ' ', + (desc_hw == desc_dma) ? 'H' : ' ', + desc_dma, + desc->next, + desc->data, + desc->ctrl, + (desc->ctrl & DESC_EMPTY) ? 'E' : '*', + ab->timestamp); + } + + spin_unlock_irqrestore(&ag->lock, flags); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return ret; +} + +static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + + return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring, + AG71XX_REG_TX_DESC); +} + +static const struct file_operations ag71xx_fops_tx_ring = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_tx_ring, + .owner = THIS_MODULE +}; + +static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ag71xx *ag = file->private_data; + + return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring, + AG71XX_REG_RX_DESC); +} + +static const struct file_operations ag71xx_fops_rx_ring = { + .open = ag71xx_debugfs_generic_open, + .read = read_file_rx_ring, + .owner = THIS_MODULE +}; + +void ag71xx_debugfs_exit(struct ag71xx *ag) +{ + debugfs_remove_recursive(ag->debug.debugfs_dir); +} + +int ag71xx_debugfs_init(struct ag71xx *ag) +{ + struct device *dev = &ag->pdev->dev; + + ag->debug.debugfs_dir = debugfs_create_dir(dev_name(dev), + ag71xx_debugfs_root); + if (!ag->debug.debugfs_dir) { + dev_err(dev, "unable to create debugfs directory\n"); + return -ENOENT; + } + + debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_int_stats); + debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_napi_stats); + debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_tx_ring); + debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir, + ag, &ag71xx_fops_rx_ring); + + return 0; +} + +int ag71xx_debugfs_root_init(void) +{ + if (ag71xx_debugfs_root) + return -EBUSY; + + ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); + if (!ag71xx_debugfs_root) + return -ENOENT; + + return 0; +} + +void ag71xx_debugfs_root_exit(void) +{ + debugfs_remove(ag71xx_debugfs_root); + ag71xx_debugfs_root = NULL; +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c new file mode 100644 index 0000000..cad9f2f --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c @@ -0,0 +1,130 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +static int ag71xx_ethtool_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_gset(phydev, cmd); +} + +static int ag71xx_ethtool_set_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + + if (!phydev) + return -ENODEV; + + return phy_ethtool_sset(phydev, cmd); +} + +static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + struct ag71xx *ag = netdev_priv(dev); + + strcpy(info->driver, ag->pdev->dev.driver->name); + strcpy(info->version, AG71XX_DRV_VERSION); + strcpy(info->bus_info, dev_name(&ag->pdev->dev)); +} + +static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + + return ag->msg_enable; +} + +static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) +{ + struct ag71xx *ag = netdev_priv(dev); + + ag->msg_enable = msg_level; +} + +static void ag71xx_ethtool_get_ringparam(struct net_device *dev, + struct ethtool_ringparam *er) +{ + struct ag71xx *ag = netdev_priv(dev); + + er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX; + er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX; + er->rx_mini_max_pending = 0; + er->rx_jumbo_max_pending = 0; + + er->tx_pending = ag->tx_ring.size; + er->rx_pending = ag->rx_ring.size; + er->rx_mini_pending = 0; + er->rx_jumbo_pending = 0; + + if (ag->tx_ring.desc_split) + er->tx_pending /= AG71XX_TX_RING_DS_PER_PKT; +} + +static int ag71xx_ethtool_set_ringparam(struct net_device *dev, + struct ethtool_ringparam *er) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned tx_size; + unsigned rx_size; + int err; + + if (er->rx_mini_pending != 0|| + er->rx_jumbo_pending != 0 || + er->rx_pending == 0 || + er->tx_pending == 0) + return -EINVAL; + + tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ? + er->tx_pending : AG71XX_TX_RING_SIZE_MAX; + + rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ? + er->rx_pending : AG71XX_RX_RING_SIZE_MAX; + + if (netif_running(dev)) { + err = dev->netdev_ops->ndo_stop(dev); + if (err) + return err; + } + + if (ag->tx_ring.desc_split) + tx_size *= AG71XX_TX_RING_DS_PER_PKT; + + ag->tx_ring.size = tx_size; + ag->rx_ring.size = rx_size; + + if (netif_running(dev)) + err = dev->netdev_ops->ndo_open(dev); + + return err; +} + +struct ethtool_ops ag71xx_ethtool_ops = { + .set_settings = ag71xx_ethtool_set_settings, + .get_settings = ag71xx_ethtool_get_settings, + .get_drvinfo = ag71xx_ethtool_get_drvinfo, + .get_msglevel = ag71xx_ethtool_get_msglevel, + .set_msglevel = ag71xx_ethtool_set_msglevel, + .get_ringparam = ag71xx_ethtool_get_ringparam, + .set_ringparam = ag71xx_ethtool_set_ringparam, + .get_link = ethtool_op_get_link, +}; diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c new file mode 100644 index 0000000..c7671d9 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c @@ -0,0 +1,1406 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AG71XX_DEFAULT_MSG_ENABLE \ + (NETIF_MSG_DRV \ + | NETIF_MSG_PROBE \ + | NETIF_MSG_LINK \ + | NETIF_MSG_TIMER \ + | NETIF_MSG_IFDOWN \ + | NETIF_MSG_IFUP \ + | NETIF_MSG_RX_ERR \ + | NETIF_MSG_TX_ERR) + +static int ag71xx_msg_level = -1; + +module_param_named(msg_level, ag71xx_msg_level, int, 0); +MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); + +#define ETH_SWITCH_HEADER_LEN 2 + +static inline unsigned int ag71xx_max_frame_len(unsigned int mtu) +{ + return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN; +} + +static void ag71xx_dump_dma_regs(struct ag71xx *ag) +{ + DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_TX_CTRL), + ag71xx_rr(ag, AG71XX_REG_TX_DESC), + ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); + + DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_RX_CTRL), + ag71xx_rr(ag, AG71XX_REG_RX_DESC), + ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); +} + +static void ag71xx_dump_regs(struct ag71xx *ag) +{ + DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), + ag71xx_rr(ag, AG71XX_REG_MAC_IPG), + ag71xx_rr(ag, AG71XX_REG_MAC_HDX), + ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); + DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), + ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); + DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); + DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); +} + +static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) +{ + DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", + ag->dev->name, label, intr, + (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", + (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", + (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", + (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", + (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", + (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); +} + +static void ag71xx_ring_free(struct ag71xx_ring *ring) +{ + kfree(ring->buf); + + if (ring->descs_cpu) + dma_free_coherent(NULL, ring->size * ring->desc_size, + ring->descs_cpu, ring->descs_dma); +} + +static int ag71xx_ring_alloc(struct ag71xx_ring *ring) +{ + int err; + + ring->desc_size = sizeof(struct ag71xx_desc); + if (ring->desc_size % cache_line_size()) { + DBG("ag71xx: ring %p, desc size %u rounded to %u\n", + ring, ring->desc_size, + roundup(ring->desc_size, cache_line_size())); + ring->desc_size = roundup(ring->desc_size, cache_line_size()); + } + + ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size, + &ring->descs_dma, GFP_ATOMIC); + if (!ring->descs_cpu) { + err = -ENOMEM; + goto err; + } + + + ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL); + if (!ring->buf) { + err = -ENOMEM; + goto err; + } + + return 0; + +err: + return err; +} + +static void ag71xx_ring_tx_clean(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + struct net_device *dev = ag->dev; + u32 bytes_compl = 0, pkts_compl = 0; + + while (ring->curr != ring->dirty) { + struct ag71xx_desc *desc; + u32 i = ring->dirty % ring->size; + + desc = ag71xx_ring_desc(ring, i); + if (!ag71xx_desc_empty(desc)) { + desc->ctrl = 0; + dev->stats.tx_errors++; + } + + if (ring->buf[i].skb) { + bytes_compl += ring->buf[i].len; + pkts_compl++; + dev_kfree_skb_any(ring->buf[i].skb); + } + ring->buf[i].skb = NULL; + ring->dirty++; + } + + /* flush descriptors */ + wmb(); + + netdev_completed_queue(dev, pkts_compl, bytes_compl); +} + +static void ag71xx_ring_tx_init(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + int i; + + for (i = 0; i < ring->size; i++) { + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + + desc->next = (u32) (ring->descs_dma + + ring->desc_size * ((i + 1) % ring->size)); + + desc->ctrl = DESC_EMPTY; + ring->buf[i].skb = NULL; + } + + /* flush descriptors */ + wmb(); + + ring->curr = 0; + ring->dirty = 0; + netdev_reset_queue(ag->dev); +} + +static void ag71xx_ring_rx_clean(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + int i; + + if (!ring->buf) + return; + + for (i = 0; i < ring->size; i++) + if (ring->buf[i].rx_buf) { + dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, + ag->rx_buf_size, DMA_FROM_DEVICE); + kfree(ring->buf[i].rx_buf); + } +} + +static int ag71xx_buffer_offset(struct ag71xx *ag) +{ + int offset = NET_SKB_PAD; + + /* + * On AR71xx/AR91xx packets must be 4-byte aligned. + * + * When using builtin AR8216 support, hardware adds a 2-byte header, + * so we don't need any extra alignment in that case. + */ + if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag)) + return offset; + + return offset + NET_IP_ALIGN; +} + +static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, + int offset) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); + void *data; + + data = kmalloc(ag->rx_buf_size + + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), + GFP_ATOMIC); + if (!data) + return false; + + buf->rx_buf = data; + buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size, + DMA_FROM_DEVICE); + desc->data = (u32) buf->dma_addr + offset; + return true; +} + +static int ag71xx_ring_rx_init(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + unsigned int i; + int ret; + int offset = ag71xx_buffer_offset(ag); + + ret = 0; + for (i = 0; i < ring->size; i++) { + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + + desc->next = (u32) (ring->descs_dma + + ring->desc_size * ((i + 1) % ring->size)); + + DBG("ag71xx: RX desc at %p, next is %08x\n", + desc, desc->next); + } + + for (i = 0; i < ring->size; i++) { + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + + if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) { + ret = -ENOMEM; + break; + } + + desc->ctrl = DESC_EMPTY; + } + + /* flush descriptors */ + wmb(); + + ring->curr = 0; + ring->dirty = 0; + + return ret; +} + +static int ag71xx_ring_rx_refill(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->rx_ring; + unsigned int count; + int offset = ag71xx_buffer_offset(ag); + + count = 0; + for (; ring->curr - ring->dirty > 0; ring->dirty++) { + struct ag71xx_desc *desc; + unsigned int i; + + i = ring->dirty % ring->size; + desc = ag71xx_ring_desc(ring, i); + + if (!ring->buf[i].rx_buf && + !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) + break; + + desc->ctrl = DESC_EMPTY; + count++; + } + + /* flush descriptors */ + wmb(); + + DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); + + return count; +} + +static int ag71xx_rings_init(struct ag71xx *ag) +{ + int ret; + + ret = ag71xx_ring_alloc(&ag->tx_ring); + if (ret) + return ret; + + ag71xx_ring_tx_init(ag); + + ret = ag71xx_ring_alloc(&ag->rx_ring); + if (ret) + return ret; + + ret = ag71xx_ring_rx_init(ag); + return ret; +} + +static void ag71xx_rings_cleanup(struct ag71xx *ag) +{ + ag71xx_ring_rx_clean(ag); + ag71xx_ring_free(&ag->rx_ring); + + ag71xx_ring_tx_clean(ag); + netdev_reset_queue(ag->dev); + ag71xx_ring_free(&ag->tx_ring); +} + +static unsigned char *ag71xx_speed_str(struct ag71xx *ag) +{ + switch (ag->speed) { + case SPEED_1000: + return "1000"; + case SPEED_100: + return "100"; + case SPEED_10: + return "10"; + } + + return "?"; +} + +static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) +{ + u32 t; + + t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) + | (((u32) mac[3]) << 8) | ((u32) mac[2]); + + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); + + t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); + ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); +} + +static void ag71xx_dma_reset(struct ag71xx *ag) +{ + u32 val; + int i; + + ag71xx_dump_dma_regs(ag); + + /* stop RX and TX */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); + + /* + * give the hardware some time to really stop all rx/tx activity + * clearing the descriptors too early causes random memory corruption + */ + mdelay(1); + + /* clear descriptor addresses */ + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); + + /* clear pending RX/TX interrupts */ + for (i = 0; i < 256; i++) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); + } + + /* clear pending errors */ + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); + + val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); + if (val) + pr_alert("%s: unable to clear DMA Rx status: %08x\n", + ag->dev->name, val); + + val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); + + /* mask out reserved bits */ + val &= ~0xff000000; + + if (val) + pr_alert("%s: unable to clear DMA Tx status: %08x\n", + ag->dev->name, val); + + ag71xx_dump_dma_regs(ag); +} + +#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ + MAC_CFG1_SRX | MAC_CFG1_STX) + +#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) + +#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ + FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ + FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ + FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ + FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ + FIFO_CFG4_VT) + +#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ + FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ + FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ + FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ + FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ + FIFO_CFG5_17 | FIFO_CFG5_SF) + +static void ag71xx_hw_stop(struct ag71xx *ag) +{ + /* disable all interrupts and stop the rx/tx engine */ + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); +} + +static void ag71xx_hw_setup(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + /* setup MAC configuration registers */ + ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); + + ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, + MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); + + /* setup max frame length to zero */ + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0); + + /* setup FIFO configuration registers */ + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); + if (pdata->is_ar724x) { + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); + } else { + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); + } + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); +} + +static void ag71xx_hw_init(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + u32 reset_mask = pdata->reset_bit; + + ag71xx_hw_stop(ag); + + if (pdata->is_ar724x) { + u32 reset_phy = reset_mask; + + reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY; + reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY); + + ath79_device_reset_set(reset_phy); + msleep(50); + ath79_device_reset_clear(reset_phy); + msleep(200); + } + + ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); + udelay(20); + + ath79_device_reset_set(reset_mask); + msleep(100); + ath79_device_reset_clear(reset_mask); + msleep(200); + + ag71xx_hw_setup(ag); + + ag71xx_dma_reset(ag); +} + +static void ag71xx_fast_reset(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct net_device *dev = ag->dev; + u32 reset_mask = pdata->reset_bit; + u32 rx_ds, tx_ds; + u32 mii_reg; + + reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC; + + mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); + rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); + tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC); + + ath79_device_reset_set(reset_mask); + udelay(10); + ath79_device_reset_clear(reset_mask); + udelay(10); + + ag71xx_dma_reset(ag); + ag71xx_hw_setup(ag); + + /* setup max frame length */ + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, + ag71xx_max_frame_len(ag->dev->mtu)); + + ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); + ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds); + ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); + + ag71xx_hw_set_macaddr(ag, dev->dev_addr); +} + +static void ag71xx_hw_start(struct ag71xx *ag) +{ + /* start RX engine */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); + + /* enable interrupts */ + ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); +} + +void ag71xx_link_adjust(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + u32 cfg2; + u32 ifctl; + u32 fifo5; + u32 fifo3; + + if (!ag->link) { + ag71xx_hw_stop(ag); + netif_carrier_off(ag->dev); + if (netif_msg_link(ag)) + pr_info("%s: link down\n", ag->dev->name); + return; + } + + if (pdata->is_ar724x) + ag71xx_fast_reset(ag); + + cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); + cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); + cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; + + ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); + ifctl &= ~(MAC_IFCTL_SPEED); + + fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); + fifo5 &= ~FIFO_CFG5_BM; + + switch (ag->speed) { + case SPEED_1000: + cfg2 |= MAC_CFG2_IF_1000; + fifo5 |= FIFO_CFG5_BM; + break; + case SPEED_100: + cfg2 |= MAC_CFG2_IF_10_100; + ifctl |= MAC_IFCTL_SPEED; + break; + case SPEED_10: + cfg2 |= MAC_CFG2_IF_10_100; + break; + default: + BUG(); + return; + } + + if (pdata->is_ar91xx) + fifo3 = 0x00780fff; + else if (pdata->is_ar724x) + fifo3 = pdata->fifo_cfg3; + else + fifo3 = 0x008001ff; + + if (ag->tx_ring.desc_split) { + fifo3 &= 0xffff; + fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; + } + + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3); + + if (pdata->set_speed) + pdata->set_speed(ag->speed); + + ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); + ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); + ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); + ag71xx_hw_start(ag); + + netif_carrier_on(ag->dev); + if (netif_msg_link(ag)) + pr_info("%s: link up (%sMbps/%s duplex)\n", + ag->dev->name, + ag71xx_speed_str(ag), + (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); + + DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); + + DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), + ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); + + DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n", + ag->dev->name, + ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), + ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL)); +} + +static int ag71xx_open(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned int max_frame_len; + int ret; + + max_frame_len = ag71xx_max_frame_len(dev->mtu); + ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN; + + /* setup max frame length */ + ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len); + + ret = ag71xx_rings_init(ag); + if (ret) + goto err; + + napi_enable(&ag->napi); + + netif_carrier_off(dev); + ag71xx_phy_start(ag); + + ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); + ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); + + ag71xx_hw_set_macaddr(ag, dev->dev_addr); + + netif_start_queue(dev); + + return 0; + +err: + ag71xx_rings_cleanup(ag); + return ret; +} + +static int ag71xx_stop(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned long flags; + + netif_carrier_off(dev); + ag71xx_phy_stop(ag); + + spin_lock_irqsave(&ag->lock, flags); + + netif_stop_queue(dev); + + ag71xx_hw_stop(ag); + ag71xx_dma_reset(ag); + + napi_disable(&ag->napi); + del_timer_sync(&ag->oom_timer); + + spin_unlock_irqrestore(&ag->lock, flags); + + ag71xx_rings_cleanup(ag); + + return 0; +} + +static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) +{ + int i; + struct ag71xx_desc *desc; + int ndesc = 0; + int split = ring->desc_split; + + if (!split) + split = len; + + while (len > 0) { + unsigned int cur_len = len; + + i = (ring->curr + ndesc) % ring->size; + desc = ag71xx_ring_desc(ring, i); + + if (!ag71xx_desc_empty(desc)) + return -1; + + if (cur_len > split) { + cur_len = split; + + /* + * TX will hang if DMA transfers <= 4 bytes, + * make sure next segment is more than 4 bytes long. + */ + if (len <= split + 4) + cur_len -= 4; + } + + desc->data = addr; + addr += cur_len; + len -= cur_len; + + if (len > 0) + cur_len |= DESC_MORE; + + /* prevent early tx attempt of this descriptor */ + if (!ndesc) + cur_len |= DESC_EMPTY; + + desc->ctrl = cur_len; + ndesc++; + } + + return ndesc; +} + +static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + struct ag71xx_ring *ring = &ag->tx_ring; + struct ag71xx_desc *desc; + dma_addr_t dma_addr; + int i, n, ring_min; + + if (ag71xx_has_ar8216(ag)) + ag71xx_add_ar8216_header(ag, skb); + + if (skb->len <= 4) { + DBG("%s: packet len is too small\n", ag->dev->name); + goto err_drop; + } + + dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + + i = ring->curr % ring->size; + desc = ag71xx_ring_desc(ring, i); + + /* setup descriptor fields */ + n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask); + if (n < 0) + goto err_drop_unmap; + + i = (ring->curr + n - 1) % ring->size; + ring->buf[i].len = skb->len; + ring->buf[i].skb = skb; + ring->buf[i].timestamp = jiffies; + + netdev_sent_queue(dev, skb->len); + + desc->ctrl &= ~DESC_EMPTY; + ring->curr += n; + + /* flush descriptor */ + wmb(); + + ring_min = 2; + if (ring->desc_split) + ring_min *= AG71XX_TX_RING_DS_PER_PKT; + + if (ring->curr - ring->dirty >= ring->size - ring_min) { + DBG("%s: tx queue full\n", dev->name); + netif_stop_queue(dev); + } + + DBG("%s: packet injected into TX queue\n", ag->dev->name); + + /* enable TX engine */ + ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); + + return NETDEV_TX_OK; + +err_drop_unmap: + dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE); + +err_drop: + dev->stats.tx_dropped++; + + dev_kfree_skb(skb); + return NETDEV_TX_OK; +} + +static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + struct ag71xx *ag = netdev_priv(dev); + int ret; + + switch (cmd) { + case SIOCETHTOOL: + if (ag->phy_dev == NULL) + break; + + spin_lock_irq(&ag->lock); + ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); + spin_unlock_irq(&ag->lock); + return ret; + + case SIOCSIFHWADDR: + if (copy_from_user + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) + return -EFAULT; + return 0; + + case SIOCGIFHWADDR: + if (copy_to_user + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) + return -EFAULT; + return 0; + + case SIOCGMIIPHY: + case SIOCGMIIREG: + case SIOCSMIIREG: + if (ag->phy_dev == NULL) + break; + + return phy_mii_ioctl(ag->phy_dev, ifr, cmd); + + default: + break; + } + + return -EOPNOTSUPP; +} + +static void ag71xx_oom_timer_handler(unsigned long data) +{ + struct net_device *dev = (struct net_device *) data; + struct ag71xx *ag = netdev_priv(dev); + + napi_schedule(&ag->napi); +} + +static void ag71xx_tx_timeout(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + + if (netif_msg_tx_err(ag)) + pr_info("%s: tx timeout\n", ag->dev->name); + + schedule_work(&ag->restart_work); +} + +static void ag71xx_restart_work_func(struct work_struct *work) +{ + struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); + + if (ag71xx_get_pdata(ag)->is_ar724x) { + ag->link = 0; + ag71xx_link_adjust(ag); + return; + } + + ag71xx_stop(ag->dev); + ag71xx_open(ag->dev); +} + +static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp) +{ + u32 rx_sm, tx_sm, rx_fd; + + if (likely(time_before(jiffies, timestamp + HZ/10))) + return false; + + if (!netif_carrier_ok(ag->dev)) + return false; + + rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); + if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) + return true; + + tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); + rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); + if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && + ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) + return true; + + return false; +} + +static int ag71xx_tx_packets(struct ag71xx *ag) +{ + struct ag71xx_ring *ring = &ag->tx_ring; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + int sent = 0; + int bytes_compl = 0; + int n = 0; + + DBG("%s: processing TX ring\n", ag->dev->name); + + while (ring->dirty + n != ring->curr) { + unsigned int i = (ring->dirty + n) % ring->size; + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + struct sk_buff *skb = ring->buf[i].skb; + + if (!ag71xx_desc_empty(desc)) { + if (pdata->is_ar7240 && + ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) + schedule_work(&ag->restart_work); + break; + } + + n++; + if (!skb) + continue; + + dev_kfree_skb_any(skb); + ring->buf[i].skb = NULL; + + bytes_compl += ring->buf[i].len; + + sent++; + ring->dirty += n; + + while (n > 0) { + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); + n--; + } + } + + DBG("%s: %d packets sent out\n", ag->dev->name, sent); + + ag->dev->stats.tx_bytes += bytes_compl; + ag->dev->stats.tx_packets += sent; + + if (!sent) + return 0; + + netdev_completed_queue(ag->dev, sent, bytes_compl); + if ((ring->curr - ring->dirty) < (ring->size * 3) / 4) + netif_wake_queue(ag->dev); + + return sent; +} + +static int ag71xx_rx_packets(struct ag71xx *ag, int limit) +{ + struct net_device *dev = ag->dev; + struct ag71xx_ring *ring = &ag->rx_ring; + int offset = ag71xx_buffer_offset(ag); + unsigned int pktlen_mask = ag->desc_pktlen_mask; + int done = 0; + + DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", + dev->name, limit, ring->curr, ring->dirty); + + while (done < limit) { + unsigned int i = ring->curr % ring->size; + struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); + struct sk_buff *skb; + int pktlen; + int err = 0; + + if (ag71xx_desc_empty(desc)) + break; + + if ((ring->dirty + ring->size) == ring->curr) { + ag71xx_assert(0); + break; + } + + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); + + pktlen = desc->ctrl & pktlen_mask; + pktlen -= ETH_FCS_LEN; + + dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, + ag->rx_buf_size, DMA_FROM_DEVICE); + + dev->stats.rx_packets++; + dev->stats.rx_bytes += pktlen; + + skb = build_skb(ring->buf[i].rx_buf, 0); + if (!skb) { + kfree(ring->buf[i].rx_buf); + goto next; + } + + skb_reserve(skb, offset); + skb_put(skb, pktlen); + + if (ag71xx_has_ar8216(ag)) + err = ag71xx_remove_ar8216_header(ag, skb, pktlen); + + if (err) { + dev->stats.rx_dropped++; + kfree_skb(skb); + } else { + skb->dev = dev; + skb->ip_summed = CHECKSUM_NONE; + skb->protocol = eth_type_trans(skb, dev); + netif_receive_skb(skb); + } + +next: + ring->buf[i].rx_buf = NULL; + done++; + + ring->curr++; + } + + ag71xx_ring_rx_refill(ag); + + DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", + dev->name, ring->curr, ring->dirty, done); + + return done; +} + +static int ag71xx_poll(struct napi_struct *napi, int limit) +{ + struct ag71xx *ag = container_of(napi, struct ag71xx, napi); + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct net_device *dev = ag->dev; + struct ag71xx_ring *rx_ring; + unsigned long flags; + u32 status; + int tx_done; + int rx_done; + + pdata->ddr_flush(); + tx_done = ag71xx_tx_packets(ag); + + DBG("%s: processing RX ring\n", dev->name); + rx_done = ag71xx_rx_packets(ag, limit); + + ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); + + rx_ring = &ag->rx_ring; + if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL) + goto oom; + + status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); + if (unlikely(status & RX_STATUS_OF)) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); + dev->stats.rx_fifo_errors++; + + /* restart RX */ + ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); + } + + if (rx_done < limit) { + if (status & RX_STATUS_PR) + goto more; + + status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); + if (status & TX_STATUS_PS) + goto more; + + DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", + dev->name, rx_done, tx_done, limit); + + napi_complete(napi); + + /* enable interrupts */ + spin_lock_irqsave(&ag->lock, flags); + ag71xx_int_enable(ag, AG71XX_INT_POLL); + spin_unlock_irqrestore(&ag->lock, flags); + return rx_done; + } + +more: + DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", + dev->name, rx_done, tx_done, limit); + return limit; + +oom: + if (netif_msg_rx_err(ag)) + pr_info("%s: out of memory\n", dev->name); + + mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); + napi_complete(napi); + return 0; +} + +static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct ag71xx *ag = netdev_priv(dev); + u32 status; + + status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); + ag71xx_dump_intr(ag, "raw", status); + + if (unlikely(!status)) + return IRQ_NONE; + + if (unlikely(status & AG71XX_INT_ERR)) { + if (status & AG71XX_INT_TX_BE) { + ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); + dev_err(&dev->dev, "TX BUS error\n"); + } + if (status & AG71XX_INT_RX_BE) { + ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); + dev_err(&dev->dev, "RX BUS error\n"); + } + } + + if (likely(status & AG71XX_INT_POLL)) { + ag71xx_int_disable(ag, AG71XX_INT_POLL); + DBG("%s: enable polling mode\n", dev->name); + napi_schedule(&ag->napi); + } + + ag71xx_debugfs_update_int_stats(ag, status); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +/* + * Polling 'interrupt' - used by things like netconsole to send skbs + * without having to re-enable interrupts. It's not called while + * the interrupt routine is executing. + */ +static void ag71xx_netpoll(struct net_device *dev) +{ + disable_irq(dev->irq); + ag71xx_interrupt(dev->irq, dev); + enable_irq(dev->irq); +} +#endif + +static int ag71xx_change_mtu(struct net_device *dev, int new_mtu) +{ + struct ag71xx *ag = netdev_priv(dev); + unsigned int max_frame_len; + + max_frame_len = ag71xx_max_frame_len(new_mtu); + if (new_mtu < 68 || max_frame_len > ag->max_frame_len) + return -EINVAL; + + if (netif_running(dev)) + return -EBUSY; + + dev->mtu = new_mtu; + return 0; +} + +static const struct net_device_ops ag71xx_netdev_ops = { + .ndo_open = ag71xx_open, + .ndo_stop = ag71xx_stop, + .ndo_start_xmit = ag71xx_hard_start_xmit, + .ndo_do_ioctl = ag71xx_do_ioctl, + .ndo_tx_timeout = ag71xx_tx_timeout, + .ndo_change_mtu = ag71xx_change_mtu, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = ag71xx_netpoll, +#endif +}; + +static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode) +{ + switch (mode) { + case PHY_INTERFACE_MODE_MII: + return "MII"; + case PHY_INTERFACE_MODE_GMII: + return "GMII"; + case PHY_INTERFACE_MODE_RMII: + return "RMII"; + case PHY_INTERFACE_MODE_RGMII: + return "RGMII"; + case PHY_INTERFACE_MODE_SGMII: + return "SGMII"; + default: + break; + } + + return "unknown"; +} + + +static int ag71xx_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct resource *res; + struct ag71xx *ag; + struct ag71xx_platform_data *pdata; + int err; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "no platform data specified\n"); + err = -ENXIO; + goto err_out; + } + + if (pdata->mii_bus_dev == NULL && pdata->phy_mask) { + dev_err(&pdev->dev, "no MII bus device specified\n"); + err = -EINVAL; + goto err_out; + } + + dev = alloc_etherdev(sizeof(*ag)); + if (!dev) { + dev_err(&pdev->dev, "alloc_etherdev failed\n"); + err = -ENOMEM; + goto err_out; + } + + if (!pdata->max_frame_len || !pdata->desc_pktlen_mask) + return -EINVAL; + + SET_NETDEV_DEV(dev, &pdev->dev); + + ag = netdev_priv(dev); + ag->pdev = pdev; + ag->dev = dev; + ag->msg_enable = netif_msg_init(ag71xx_msg_level, + AG71XX_DEFAULT_MSG_ENABLE); + spin_lock_init(&ag->lock); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); + if (!res) { + dev_err(&pdev->dev, "no mac_base resource found\n"); + err = -ENXIO; + goto err_out; + } + + ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!ag->mac_base) { + dev_err(&pdev->dev, "unable to ioremap mac_base\n"); + err = -ENOMEM; + goto err_free_dev; + } + + dev->irq = platform_get_irq(pdev, 0); + err = request_irq(dev->irq, ag71xx_interrupt, + 0x0, + dev->name, dev); + if (err) { + dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); + goto err_unmap_base; + } + + dev->base_addr = (unsigned long)ag->mac_base; + dev->netdev_ops = &ag71xx_netdev_ops; + dev->ethtool_ops = &ag71xx_ethtool_ops; + + INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); + + init_timer(&ag->oom_timer); + ag->oom_timer.data = (unsigned long) dev; + ag->oom_timer.function = ag71xx_oom_timer_handler; + + ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT; + ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT; + + ag->max_frame_len = pdata->max_frame_len; + ag->desc_pktlen_mask = pdata->desc_pktlen_mask; + + if (!pdata->is_ar724x && !pdata->is_ar91xx) { + ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; + ag->tx_ring.size *= AG71XX_TX_RING_DS_PER_PKT; + } + + ag->stop_desc = dma_alloc_coherent(NULL, + sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL); + + if (!ag->stop_desc) + goto err_free_irq; + + ag->stop_desc->data = 0; + ag->stop_desc->ctrl = 0; + ag->stop_desc->next = (u32) ag->stop_desc_dma; + + memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); + + netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); + + ag71xx_dump_regs(ag); + + ag71xx_hw_init(ag); + + ag71xx_dump_regs(ag); + + err = ag71xx_phy_connect(ag); + if (err) + goto err_free_desc; + + err = ag71xx_debugfs_init(ag); + if (err) + goto err_phy_disconnect; + + platform_set_drvdata(pdev, dev); + + err = register_netdev(dev); + if (err) { + dev_err(&pdev->dev, "unable to register net device\n"); + goto err_debugfs_exit; + } + + pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n", + dev->name, dev->base_addr, dev->irq, + ag71xx_get_phy_if_mode_name(pdata->phy_if_mode)); + + return 0; + +err_debugfs_exit: + ag71xx_debugfs_exit(ag); +err_phy_disconnect: + ag71xx_phy_disconnect(ag); +err_free_desc: + dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc, + ag->stop_desc_dma); +err_free_irq: + free_irq(dev->irq, dev); +err_unmap_base: + iounmap(ag->mac_base); +err_free_dev: + kfree(dev); +err_out: + platform_set_drvdata(pdev, NULL); + return err; +} + +static int ag71xx_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (dev) { + struct ag71xx *ag = netdev_priv(dev); + + ag71xx_debugfs_exit(ag); + ag71xx_phy_disconnect(ag); + unregister_netdev(dev); + free_irq(dev->irq, dev); + iounmap(ag->mac_base); + kfree(dev); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver ag71xx_driver = { + .probe = ag71xx_probe, + .remove = ag71xx_remove, + .driver = { + .name = AG71XX_DRV_NAME, + } +}; + +static int __init ag71xx_module_init(void) +{ + int ret; + + ret = ag71xx_debugfs_root_init(); + if (ret) + goto err_out; + + ret = ag71xx_mdio_driver_init(); + if (ret) + goto err_debugfs_exit; + + ret = platform_driver_register(&ag71xx_driver); + if (ret) + goto err_mdio_exit; + + return 0; + +err_mdio_exit: + ag71xx_mdio_driver_exit(); +err_debugfs_exit: + ag71xx_debugfs_root_exit(); +err_out: + return ret; +} + +static void __exit ag71xx_module_exit(void) +{ + platform_driver_unregister(&ag71xx_driver); + ag71xx_mdio_driver_exit(); + ag71xx_debugfs_root_exit(); +} + +module_init(ag71xx_module_init); +module_exit(ag71xx_module_exit); + +MODULE_VERSION(AG71XX_DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_AUTHOR("Imre Kaloz "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" AG71XX_DRV_NAME); diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c new file mode 100644 index 0000000..71ae825 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c @@ -0,0 +1,318 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +#define AG71XX_MDIO_RETRY 1000 +#define AG71XX_MDIO_DELAY 5 + +static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, + u32 value) +{ + void __iomem *r; + + r = am->mdio_base + reg; + __raw_writel(value, r); + + /* flush write */ + (void) __raw_readl(r); +} + +static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) +{ + return __raw_readl(am->mdio_base + reg); +} + +static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) +{ + DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", + am->mii_bus->name, + ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), + ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), + ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); + DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", + am->mii_bus->name, + ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), + ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), + ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); +} + +static int ag71xx_mdio_wait_busy(struct ag71xx_mdio *am) +{ + int i; + + for (i = 0; i < AG71XX_MDIO_RETRY; i++) { + u32 busy; + + udelay(AG71XX_MDIO_DELAY); + + busy = ag71xx_mdio_rr(am, AG71XX_REG_MII_IND); + if (!busy) + return 0; + + udelay(AG71XX_MDIO_DELAY); + } + + pr_err("%s: MDIO operation timed out\n", am->mii_bus->name); + + return -ETIMEDOUT; +} + +int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) +{ + int err; + int ret; + + err = ag71xx_mdio_wait_busy(am); + if (err) + return 0xffff; + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); + + err = ag71xx_mdio_wait_busy(am); + if (err) + return 0xffff; + + ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; + ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); + + DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); + + return ret; +} + +void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val) +{ + DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); + + ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, + ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); + ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); + + ag71xx_mdio_wait_busy(am); +} + +static const u32 ar71xx_mdio_div_table[] = { + 4, 4, 6, 8, 10, 14, 20, 28, +}; + +static const u32 ar7240_mdio_div_table[] = { + 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96, +}; + +static const u32 ar933x_mdio_div_table[] = { + 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98, +}; + +static int ag71xx_mdio_get_divider(struct ag71xx_mdio *am, u32 *div) +{ + unsigned long ref_clock, mdio_clock; + const u32 *table; + int ndivs; + int i; + + ref_clock = am->pdata->ref_clock; + mdio_clock = am->pdata->mdio_clock; + + if (!ref_clock || !mdio_clock) + return -EINVAL; + + if (am->pdata->is_ar9330 || am->pdata->is_ar934x) { + table = ar933x_mdio_div_table; + ndivs = ARRAY_SIZE(ar933x_mdio_div_table); + } else if (am->pdata->is_ar7240) { + table = ar7240_mdio_div_table; + ndivs = ARRAY_SIZE(ar7240_mdio_div_table); + } else { + table = ar71xx_mdio_div_table; + ndivs = ARRAY_SIZE(ar71xx_mdio_div_table); + } + + for (i = 0; i < ndivs; i++) { + unsigned long t; + + t = ref_clock / table[i]; + if (t <= mdio_clock) { + *div = i; + return 0; + } + } + + dev_err(&am->mii_bus->dev, "no divider found for %lu/%lu\n", + ref_clock, mdio_clock); + return -ENOENT; +} + +static int ag71xx_mdio_reset(struct mii_bus *bus) +{ + struct ag71xx_mdio *am = bus->priv; + u32 t; + int err; + + err = ag71xx_mdio_get_divider(am, &t); + if (err) { + /* fallback */ + if (am->pdata->is_ar7240) + t = MII_CFG_CLK_DIV_6; + else if (am->pdata->builtin_switch && !am->pdata->is_ar934x) + t = MII_CFG_CLK_DIV_10; + else if (!am->pdata->builtin_switch && am->pdata->is_ar934x) + t = MII_CFG_CLK_DIV_58; + else + t = MII_CFG_CLK_DIV_28; + } + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); + udelay(100); + + ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); + udelay(100); + + if (am->pdata->reset) + am->pdata->reset(bus); + + return 0; +} + +static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) +{ + struct ag71xx_mdio *am = bus->priv; + + if (am->pdata->builtin_switch) + return ar7240sw_phy_read(bus, addr, reg); + else + return ag71xx_mdio_mii_read(am, addr, reg); +} + +static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) +{ + struct ag71xx_mdio *am = bus->priv; + + if (am->pdata->builtin_switch) + ar7240sw_phy_write(bus, addr, reg, val); + else + ag71xx_mdio_mii_write(am, addr, reg, val); + return 0; +} + +static int ag71xx_mdio_probe(struct platform_device *pdev) +{ + struct ag71xx_mdio_platform_data *pdata; + struct ag71xx_mdio *am; + struct resource *res; + int i; + int err; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + am = kzalloc(sizeof(*am), GFP_KERNEL); + if (!am) { + err = -ENOMEM; + goto err_out; + } + + am->pdata = pdata; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no iomem resource found\n"); + err = -ENXIO; + goto err_out; + } + + am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!am->mdio_base) { + dev_err(&pdev->dev, "unable to ioremap registers\n"); + err = -ENOMEM; + goto err_free_mdio; + } + + am->mii_bus = mdiobus_alloc(); + if (am->mii_bus == NULL) { + err = -ENOMEM; + goto err_iounmap; + } + + am->mii_bus->name = "ag71xx_mdio"; + am->mii_bus->read = ag71xx_mdio_read; + am->mii_bus->write = ag71xx_mdio_write; + am->mii_bus->reset = ag71xx_mdio_reset; + am->mii_bus->irq = am->mii_irq; + am->mii_bus->priv = am; + am->mii_bus->parent = &pdev->dev; + snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); + am->mii_bus->phy_mask = pdata->phy_mask; + + for (i = 0; i < PHY_MAX_ADDR; i++) + am->mii_irq[i] = PHY_POLL; + + ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); + + err = mdiobus_register(am->mii_bus); + if (err) + goto err_free_bus; + + ag71xx_mdio_dump_regs(am); + + platform_set_drvdata(pdev, am); + return 0; + +err_free_bus: + mdiobus_free(am->mii_bus); +err_iounmap: + iounmap(am->mdio_base); +err_free_mdio: + kfree(am); +err_out: + return err; +} + +static int ag71xx_mdio_remove(struct platform_device *pdev) +{ + struct ag71xx_mdio *am = platform_get_drvdata(pdev); + + if (am) { + mdiobus_unregister(am->mii_bus); + mdiobus_free(am->mii_bus); + iounmap(am->mdio_base); + kfree(am); + platform_set_drvdata(pdev, NULL); + } + + return 0; +} + +static struct platform_driver ag71xx_mdio_driver = { + .probe = ag71xx_mdio_probe, + .remove = ag71xx_mdio_remove, + .driver = { + .name = "ag71xx-mdio", + } +}; + +int __init ag71xx_mdio_driver_init(void) +{ + return platform_driver_register(&ag71xx_mdio_driver); +} + +void ag71xx_mdio_driver_exit(void) +{ + platform_driver_unregister(&ag71xx_mdio_driver); +} diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c new file mode 100644 index 0000000..9de77e9 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c @@ -0,0 +1,235 @@ +/* + * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ag71xx.h" + +static void ag71xx_phy_link_adjust(struct net_device *dev) +{ + struct ag71xx *ag = netdev_priv(dev); + struct phy_device *phydev = ag->phy_dev; + unsigned long flags; + int status_change = 0; + + spin_lock_irqsave(&ag->lock, flags); + + if (phydev->link) { + if (ag->duplex != phydev->duplex + || ag->speed != phydev->speed) { + status_change = 1; + } + } + + if (phydev->link != ag->link) + status_change = 1; + + ag->link = phydev->link; + ag->duplex = phydev->duplex; + ag->speed = phydev->speed; + + if (status_change) + ag71xx_link_adjust(ag); + + spin_unlock_irqrestore(&ag->lock, flags); +} + +void ag71xx_phy_start(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (ag->phy_dev) { + phy_start(ag->phy_dev); + } else if (pdata->mii_bus_dev && pdata->switch_data) { + ag71xx_ar7240_start(ag); + } else { + ag->link = 1; + ag71xx_link_adjust(ag); + } +} + +void ag71xx_phy_stop(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + unsigned long flags; + + if (ag->phy_dev) + phy_stop(ag->phy_dev); + else if (pdata->mii_bus_dev && pdata->switch_data) + ag71xx_ar7240_stop(ag); + + spin_lock_irqsave(&ag->lock, flags); + if (ag->link) { + ag->link = 0; + ag71xx_link_adjust(ag); + } + spin_unlock_irqrestore(&ag->lock, flags); +} + +static int ag71xx_phy_connect_fixed(struct ag71xx *ag) +{ + struct device *dev = &ag->pdev->dev; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + int ret = 0; + + /* use fixed settings */ + switch (pdata->speed) { + case SPEED_10: + case SPEED_100: + case SPEED_1000: + break; + default: + dev_err(dev, "invalid speed specified\n"); + ret = -EINVAL; + break; + } + + dev_dbg(dev, "using fixed link parameters\n"); + + ag->duplex = pdata->duplex; + ag->speed = pdata->speed; + + return ret; +} + +static int ag71xx_phy_connect_multi(struct ag71xx *ag) +{ + struct device *dev = &ag->pdev->dev; + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + struct phy_device *phydev = NULL; + int phy_addr; + int ret = 0; + + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (!(pdata->phy_mask & (1 << phy_addr))) + continue; + + if (ag->mii_bus->phy_map[phy_addr] == NULL) + continue; + + DBG("%s: PHY found at %s, uid=%08x\n", + dev_name(dev), + dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), + ag->mii_bus->phy_map[phy_addr]->phy_id); + + if (phydev == NULL) + phydev = ag->mii_bus->phy_map[phy_addr]; + } + + if (!phydev) { + dev_err(dev, "no PHY found with phy_mask=%08x\n", + pdata->phy_mask); + return -ENODEV; + } + + ag->phy_dev = phy_connect(ag->dev, dev_name(&phydev->dev), + &ag71xx_phy_link_adjust, + pdata->phy_if_mode); + + if (IS_ERR(ag->phy_dev)) { + dev_err(dev, "could not connect to PHY at %s\n", + dev_name(&phydev->dev)); + return PTR_ERR(ag->phy_dev); + } + + /* mask with MAC supported features */ + if (pdata->has_gbit) + phydev->supported &= PHY_GBIT_FEATURES; + else + phydev->supported &= PHY_BASIC_FEATURES; + + phydev->advertising = phydev->supported; + + dev_info(dev, "connected to PHY at %s [uid=%08x, driver=%s]\n", + dev_name(&phydev->dev), phydev->phy_id, phydev->drv->name); + + ag->link = 0; + ag->speed = 0; + ag->duplex = -1; + + return ret; +} + +static int dev_is_class(struct device *dev, void *class) +{ + if (dev->class != NULL && !strcmp(dev->class->name, class)) + return 1; + + return 0; +} + +static struct device *dev_find_class(struct device *parent, char *class) +{ + if (dev_is_class(parent, class)) { + get_device(parent); + return parent; + } + + return device_find_child(parent, class, dev_is_class); +} + +static struct mii_bus *dev_to_mii_bus(struct device *dev) +{ + struct device *d; + + d = dev_find_class(dev, "mdio_bus"); + if (d != NULL) { + struct mii_bus *bus; + + bus = to_mii_bus(d); + put_device(d); + + return bus; + } + + return NULL; +} + +int ag71xx_phy_connect(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (pdata->mii_bus_dev == NULL || + pdata->mii_bus_dev->bus == NULL ) + return ag71xx_phy_connect_fixed(ag); + + ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); + if (ag->mii_bus == NULL) { + dev_err(&ag->pdev->dev, "unable to find MII bus on device '%s'\n", + dev_name(pdata->mii_bus_dev)); + return -ENODEV; + } + + /* Reset the mdio bus explicitly */ + if (ag->mii_bus->reset) { + mutex_lock(&ag->mii_bus->mdio_lock); + ag->mii_bus->reset(ag->mii_bus); + mutex_unlock(&ag->mii_bus->mdio_lock); + } + + if (pdata->switch_data) + return ag71xx_ar7240_init(ag); + + if (pdata->phy_mask) + return ag71xx_phy_connect_multi(ag); + + return ag71xx_phy_connect_fixed(ag); +} + +void ag71xx_phy_disconnect(struct ag71xx *ag) +{ + struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + + if (pdata->switch_data) + ag71xx_ar7240_cleanup(ag); + else if (ag->phy_dev) + phy_disconnect(ag->phy_dev); +} diff --git a/target/linux/ar71xx/files/drivers/spi/spi-ap83.c b/target/linux/ar71xx/files/drivers/spi/spi-ap83.c new file mode 100644 index 0000000..33843a6 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-ap83.c @@ -0,0 +1,283 @@ +/* + * Atheros AP83 board specific SPI Controller driver + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_DESC "Atheros AP83 board SPI Controller driver" +#define DRV_VERSION "0.1.0" +#define DRV_NAME "ap83-spi" + +#define AP83_SPI_CLK_HIGH (1 << 23) +#define AP83_SPI_CLK_LOW 0 +#define AP83_SPI_MOSI_HIGH (1 << 22) +#define AP83_SPI_MOSI_LOW 0 + +#define AP83_SPI_GPIO_CS 1 +#define AP83_SPI_GPIO_MISO 3 + +struct ap83_spi { + struct spi_bitbang bitbang; + void __iomem *base; + u32 addr; + + struct platform_device *pdev; +}; + +static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) +{ + return __raw_readl(sp->base + reg); +} + +static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) +{ + return spi_master_get_devdata(spi->master); +} + +static inline void setsck(struct spi_device *spi, int val) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + if (val) + sp->addr |= AP83_SPI_CLK_HIGH; + else + sp->addr &= ~AP83_SPI_CLK_HIGH; + + dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", + sp->addr, (val) ? "HIGH" : "LOW"); + + ap83_spi_rr(sp, sp->addr); +} + +static inline void setmosi(struct spi_device *spi, int val) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + if (val) + sp->addr |= AP83_SPI_MOSI_HIGH; + else + sp->addr &= ~AP83_SPI_MOSI_HIGH; + + dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", + sp->addr, (val) ? "HIGH" : "LOW"); + + ap83_spi_rr(sp, sp->addr); +} + +static inline u32 getmiso(struct spi_device *spi) +{ + u32 ret; + + ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; + dev_dbg(&spi->dev, "get MISO: %d\n", ret); + + return ret; +} + +static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) +{ + ndelay(nsecs); +} + +static void ap83_spi_chipselect(struct spi_device *spi, int on) +{ + struct ap83_spi *sp = spidev_to_sp(spi); + + dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); + + if (on) { + ath79_flash_acquire(); + + sp->addr = 0; + ap83_spi_rr(sp, sp->addr); + + gpio_set_value(AP83_SPI_GPIO_CS, 0); + } else { + gpio_set_value(AP83_SPI_GPIO_CS, 1); + ath79_flash_release(); + } +} + +#define spidelay(nsecs) \ + do { \ + /* Steal the spi_device pointer from our caller. \ + * The bitbang-API should probably get fixed here... */ \ + do_spidelay(spi, nsecs); \ + } while (0) + +#define EXPAND_BITBANG_TXRX +#include +#include "spi-bitbang-txrx.h" + +static u32 ap83_spi_txrx_mode0(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode1(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode2(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); +} + +static u32 ap83_spi_txrx_mode3(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits) +{ + dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); + return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); +} + +static int ap83_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct ap83_spi *sp; + struct ap83_spi_platform_data *pdata; + struct resource *r; + int ret; + + ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); + if (ret) { + dev_err(&pdev->dev, "gpio request failed for MISO\n"); + return ret; + } + + ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); + if (ret) { + dev_err(&pdev->dev, "gpio request failed for CS\n"); + goto err_free_miso; + } + + ret = gpio_direction_input(AP83_SPI_GPIO_MISO); + if (ret) { + dev_err(&pdev->dev, "unable to set direction of MISO\n"); + goto err_free_cs; + } + + ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); + if (ret) { + dev_err(&pdev->dev, "unable to set direction of CS\n"); + goto err_free_cs; + } + + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); + return -ENOMEM; + } + + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + + pdata = pdev->dev.platform_data; + + sp->bitbang.master = spi_master_get(master); + sp->bitbang.chipselect = ap83_spi_chipselect; + sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; + sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; + sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; + sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; + + sp->bitbang.master->bus_num = pdev->id; + sp->bitbang.master->num_chipselect = 1; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + ret = -ENOENT; + goto err_spi_put; + } + + sp->base = ioremap_nocache(r->start, r->end - r->start + 1); + if (!sp->base) { + ret = -ENXIO; + goto err_spi_put; + } + + ret = spi_bitbang_start(&sp->bitbang); + if (!ret) + goto err_unmap; + + dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); + + return 0; + +err_unmap: + iounmap(sp->base); +err_spi_put: + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + +err_free_cs: + gpio_free(AP83_SPI_GPIO_CS); +err_free_miso: + gpio_free(AP83_SPI_GPIO_MISO); + return ret; +} + +static int ap83_spi_remove(struct platform_device *pdev) +{ + struct ap83_spi *sp = platform_get_drvdata(pdev); + + spi_bitbang_stop(&sp->bitbang); + iounmap(sp->base); + platform_set_drvdata(pdev, NULL); + spi_master_put(sp->bitbang.master); + + return 0; +} + +static struct platform_driver ap83_spi_drv = { + .probe = ap83_spi_probe, + .remove = ap83_spi_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init ap83_spi_init(void) +{ + return platform_driver_register(&ap83_spi_drv); +} +module_init(ap83_spi_init); + +static void __exit ap83_spi_exit(void) +{ + platform_driver_unregister(&ap83_spi_drv); +} +module_exit(ap83_spi_exit); + +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c new file mode 100644 index 0000000..a8d5282 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx-cpld.c @@ -0,0 +1,441 @@ +/* + * SPI driver for the CPLD chip on the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_NAME "spi-rb4xx-cpld" +#define DRV_DESC "RB4xx CPLD driver" +#define DRV_VERSION "0.1.0" + +#define CPLD_CMD_WRITE_NAND 0x08 /* send cmd, n x send data, send indle */ +#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ +#define CPLD_CMD_READ_NAND 0x0a /* send cmd, send idle, n x read data */ +#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ +#define CPLD_CMD_LED5_ON 0x0c /* send cmd */ +#define CPLD_CMD_LED5_OFF 0x0d /* send cmd */ + +struct rb4xx_cpld { + struct spi_device *spi; + struct mutex lock; + struct gpio_chip chip; + unsigned int config; +}; + +static struct rb4xx_cpld *rb4xx_cpld; + +static inline struct rb4xx_cpld *gpio_to_cpld(struct gpio_chip *chip) +{ + return container_of(chip, struct rb4xx_cpld, chip); +} + +static int rb4xx_cpld_write_cmd(struct rb4xx_cpld *cpld, unsigned char cmd) +{ + struct spi_transfer t[1]; + struct spi_message m; + unsigned char tx_buf[1]; + int err; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = tx_buf; + t[0].len = sizeof(tx_buf); + spi_message_add_tail(&t[0], &m); + + tx_buf[0] = cmd; + + err = spi_sync(cpld->spi, &m); + return err; +} + +static int rb4xx_cpld_write_cfg(struct rb4xx_cpld *cpld, unsigned char config) +{ + struct spi_transfer t[1]; + struct spi_message m; + unsigned char cmd[2]; + int err; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_WRITE_CFG; + cmd[1] = config; + + err = spi_sync(cpld->spi, &m); + return err; +} + +static int __rb4xx_cpld_change_cfg(struct rb4xx_cpld *cpld, unsigned mask, + unsigned value) +{ + unsigned int config; + int err; + + config = cpld->config & ~mask; + config |= value; + + if ((cpld->config ^ config) & 0xff) { + err = rb4xx_cpld_write_cfg(cpld, config); + if (err) + return err; + } + + if ((cpld->config ^ config) & CPLD_CFG_nLED5) { + err = rb4xx_cpld_write_cmd(cpld, (value) ? CPLD_CMD_LED5_ON : + CPLD_CMD_LED5_OFF); + if (err) + return err; + } + + cpld->config = config; + return 0; +} + +int rb4xx_cpld_change_cfg(unsigned mask, unsigned value) +{ + int ret; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + mutex_lock(&rb4xx_cpld->lock); + ret = __rb4xx_cpld_change_cfg(rb4xx_cpld, mask, value); + mutex_unlock(&rb4xx_cpld->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_change_cfg); + +int rb4xx_cpld_read_from(unsigned addr, unsigned char *rx_buf, + const unsigned char *verify_buf, unsigned count) +{ + const unsigned char cmd[5] = { + CPLD_CMD_READ_FAST, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + addr & 0xff, + 0 + }; + struct spi_transfer t[2] = { + { + .tx_buf = &cmd, + .len = 5, + }, + { + .tx_buf = verify_buf, + .rx_buf = rx_buf, + .len = count, + .verify = (verify_buf != NULL), + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + m.fast_read = 1; + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + return spi_sync(rb4xx_cpld->spi, &m); +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_read_from); + +#if 0 +int rb4xx_cpld_read(unsigned char *buf, unsigned char *verify_buf, + unsigned count) +{ + struct spi_transfer t[2]; + struct spi_message m; + unsigned char cmd[2]; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + memset(&t, 0, sizeof(t)); + + /* send command */ + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_READ_NAND; + cmd[1] = 0; + + /* read data */ + t[1].rx_buf = buf; + t[1].len = count; + spi_message_add_tail(&t[1], &m); + + return spi_sync(rb4xx_cpld->spi, &m); +} +#else +int rb4xx_cpld_read(unsigned char *rx_buf, const unsigned char *verify_buf, + unsigned count) +{ + static const unsigned char cmd[2] = { CPLD_CMD_READ_NAND, 0 }; + struct spi_transfer t[2] = { + { + .tx_buf = &cmd, + .len = 2, + }, { + .tx_buf = verify_buf, + .rx_buf = rx_buf, + .len = count, + .verify = (verify_buf != NULL), + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + return spi_sync(rb4xx_cpld->spi, &m); +} +#endif +EXPORT_SYMBOL_GPL(rb4xx_cpld_read); + +int rb4xx_cpld_write(const unsigned char *buf, unsigned count) +{ +#if 0 + struct spi_transfer t[3]; + struct spi_message m; + unsigned char cmd[1]; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + memset(&t, 0, sizeof(t)); + spi_message_init(&m); + + /* send command */ + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + cmd[0] = CPLD_CMD_WRITE_NAND; + + /* write data */ + t[1].tx_buf = buf; + t[1].len = count; + spi_message_add_tail(&t[1], &m); + + /* send idle */ + t[2].len = 1; + spi_message_add_tail(&t[2], &m); + + return spi_sync(rb4xx_cpld->spi, &m); +#else + static const unsigned char cmd = CPLD_CMD_WRITE_NAND; + struct spi_transfer t[3] = { + { + .tx_buf = &cmd, + .len = 1, + }, { + .tx_buf = buf, + .len = count, + .fast_write = 1, + }, { + .len = 1, + .fast_write = 1, + }, + }; + struct spi_message m; + + if (rb4xx_cpld == NULL) + return -ENODEV; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + spi_message_add_tail(&t[2], &m); + return spi_sync(rb4xx_cpld->spi, &m); +#endif +} +EXPORT_SYMBOL_GPL(rb4xx_cpld_write); + +static int rb4xx_cpld_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + int ret; + + mutex_lock(&cpld->lock); + ret = (cpld->config >> offset) & 1; + mutex_unlock(&cpld->lock); + + return ret; +} + +static void rb4xx_cpld_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + + mutex_lock(&cpld->lock); + __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); + mutex_unlock(&cpld->lock); +} + +static int rb4xx_cpld_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + return -EOPNOTSUPP; +} + +static int rb4xx_cpld_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, + int value) +{ + struct rb4xx_cpld *cpld = gpio_to_cpld(chip); + int ret; + + mutex_lock(&cpld->lock); + ret = __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); + mutex_unlock(&cpld->lock); + + return ret; +} + +static int rb4xx_cpld_gpio_init(struct rb4xx_cpld *cpld, unsigned int base) +{ + int err; + + /* init config */ + cpld->config = CPLD_CFG_nLED1 | CPLD_CFG_nLED2 | CPLD_CFG_nLED3 | + CPLD_CFG_nLED4 | CPLD_CFG_nCE; + rb4xx_cpld_write_cfg(cpld, cpld->config); + + /* setup GPIO chip */ + cpld->chip.label = DRV_NAME; + + cpld->chip.get = rb4xx_cpld_gpio_get; + cpld->chip.set = rb4xx_cpld_gpio_set; + cpld->chip.direction_input = rb4xx_cpld_gpio_direction_input; + cpld->chip.direction_output = rb4xx_cpld_gpio_direction_output; + + cpld->chip.base = base; + cpld->chip.ngpio = CPLD_NUM_GPIOS; + cpld->chip.can_sleep = 1; + cpld->chip.dev = &cpld->spi->dev; + cpld->chip.owner = THIS_MODULE; + + err = gpiochip_add(&cpld->chip); + if (err) + dev_err(&cpld->spi->dev, "adding GPIO chip failed, err=%d\n", + err); + + return err; +} + +static int rb4xx_cpld_probe(struct spi_device *spi) +{ + struct rb4xx_cpld *cpld; + struct rb4xx_cpld_platform_data *pdata; + int err; + + pdata = spi->dev.platform_data; + if (!pdata) { + dev_dbg(&spi->dev, "no platform data\n"); + return -EINVAL; + } + + cpld = kzalloc(sizeof(*cpld), GFP_KERNEL); + if (!cpld) { + dev_err(&spi->dev, "no memory for private data\n"); + return -ENOMEM; + } + + mutex_init(&cpld->lock); + cpld->spi = spi_dev_get(spi); + dev_set_drvdata(&spi->dev, cpld); + + spi->mode = SPI_MODE_0; + spi->bits_per_word = 8; + err = spi_setup(spi); + if (err) { + dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); + goto err_drvdata; + } + + err = rb4xx_cpld_gpio_init(cpld, pdata->gpio_base); + if (err) + goto err_drvdata; + + rb4xx_cpld = cpld; + + return 0; + +err_drvdata: + dev_set_drvdata(&spi->dev, NULL); + kfree(cpld); + + return err; +} + +static int rb4xx_cpld_remove(struct spi_device *spi) +{ + struct rb4xx_cpld *cpld; + + rb4xx_cpld = NULL; + cpld = dev_get_drvdata(&spi->dev); + dev_set_drvdata(&spi->dev, NULL); + kfree(cpld); + + return 0; +} + +static struct spi_driver rb4xx_cpld_driver = { + .driver = { + .name = DRV_NAME, + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = rb4xx_cpld_probe, + .remove = rb4xx_cpld_remove, +}; + +static int __init rb4xx_cpld_init(void) +{ + return spi_register_driver(&rb4xx_cpld_driver); +} +module_init(rb4xx_cpld_init); + +static void __exit rb4xx_cpld_exit(void) +{ + spi_unregister_driver(&rb4xx_cpld_driver); +} +module_exit(rb4xx_cpld_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c new file mode 100644 index 0000000..56260ff --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-rb4xx.c @@ -0,0 +1,507 @@ +/* + * SPI controller driver for the Mikrotik RB4xx boards + * + * Copyright (C) 2010 Gabor Juhos + * + * This file was based on the patches for Linux 2.6.27.39 published by + * MikroTik for their RouterBoard 4xx series devices. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_NAME "rb4xx-spi" +#define DRV_DESC "Mikrotik RB4xx SPI controller driver" +#define DRV_VERSION "0.1.0" + +#define SPI_CTRL_FASTEST 0x40 +#define SPI_FLASH_HZ 33333334 +#define SPI_CPLD_HZ 33333334 + +#define CPLD_CMD_READ_FAST 0x0b + +#undef RB4XX_SPI_DEBUG + +struct rb4xx_spi { + void __iomem *base; + struct spi_master *master; + + unsigned spi_ctrl_flash; + unsigned spi_ctrl_fread; + + struct clk *ahb_clk; + unsigned long ahb_freq; + + spinlock_t lock; + struct list_head queue; + int busy:1; + int cs_wait; +}; + +static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1; + +#ifdef RB4XX_SPI_DEBUG +static inline void do_spi_delay(void) +{ + ndelay(20000); +} +#else +static inline void do_spi_delay(void) { } +#endif + +static inline void do_spi_init(struct spi_device *spi) +{ + unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1; + + if (!(spi->mode & SPI_CS_HIGH)) + cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 : + AR71XX_SPI_IOC_CS0; + + spi_clk_low = cs; +} + +static inline void do_spi_finish(void __iomem *base) +{ + do_spi_delay(); + __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1, + base + AR71XX_SPI_REG_IOC); +} + +static inline void do_spi_clk(void __iomem *base, int bit) +{ + unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0); + + do_spi_delay(); + __raw_writel(bval, base + AR71XX_SPI_REG_IOC); + do_spi_delay(); + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC); +} + +static void do_spi_byte(void __iomem *base, unsigned char byte) +{ + do_spi_clk(base, byte >> 7); + do_spi_clk(base, byte >> 6); + do_spi_clk(base, byte >> 5); + do_spi_clk(base, byte >> 4); + do_spi_clk(base, byte >> 3); + do_spi_clk(base, byte >> 2); + do_spi_clk(base, byte >> 1); + do_spi_clk(base, byte); + + pr_debug("spi_byte sent 0x%02x got 0x%02x\n", + (unsigned)byte, + (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS)); +} + +static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1, + unsigned bit2) +{ + unsigned bval = (spi_clk_low | + ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) | + ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0)); + do_spi_delay(); + __raw_writel(bval, base + AR71XX_SPI_REG_IOC); + do_spi_delay(); + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC); +} + +static void do_spi_byte_fast(void __iomem *base, unsigned char byte) +{ + do_spi_clk_fast(base, byte >> 7, byte >> 6); + do_spi_clk_fast(base, byte >> 5, byte >> 4); + do_spi_clk_fast(base, byte >> 3, byte >> 2); + do_spi_clk_fast(base, byte >> 1, byte >> 0); + + pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n", + (unsigned)byte, + (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS)); +} + +static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t) +{ + const unsigned char *rxv_ptr = NULL; + const unsigned char *tx_ptr = t->tx_buf; + unsigned char *rx_ptr = t->rx_buf; + unsigned i; + + pr_debug("spi_txrx len %u tx %u rx %u\n", + t->len, + (t->tx_buf ? 1 : 0), + (t->rx_buf ? 1 : 0)); + + if (t->verify) { + rxv_ptr = tx_ptr; + tx_ptr = NULL; + } + + for (i = 0; i < t->len; ++i) { + unsigned char sdata = tx_ptr ? tx_ptr[i] : 0; + + if (t->fast_write) + do_spi_byte_fast(base, sdata); + else + do_spi_byte(base, sdata); + + if (rx_ptr) { + rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff; + } else if (rxv_ptr) { + unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS); + if (rxv_ptr[i] != c) + return i; + } + } + + return i; +} + +static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi, + struct spi_message *m) +{ + struct spi_transfer *t; + const unsigned char *tx_ptr; + unsigned addr; + void __iomem *base = rbspi->base; + + /* check for exactly two transfers */ + if (list_empty(&m->transfers) || + list_is_last(m->transfers.next, &m->transfers) || + !list_is_last(m->transfers.next->next, &m->transfers)) { + return -1; + } + + /* first transfer contains command and address */ + t = list_entry(m->transfers.next, + struct spi_transfer, transfer_list); + + if (t->len != 5 || t->tx_buf == NULL) + return -1; + + tx_ptr = t->tx_buf; + if (tx_ptr[0] != CPLD_CMD_READ_FAST) + return -1; + + addr = tx_ptr[1]; + addr = tx_ptr[2] | (addr << 8); + addr = tx_ptr[3] | (addr << 8); + addr += (unsigned) base; + + m->actual_length += t->len; + + /* second transfer contains data itself */ + t = list_entry(m->transfers.next->next, + struct spi_transfer, transfer_list); + + if (t->tx_buf && !t->verify) + return -1; + + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + + if (t->rx_buf) { + memcpy(t->rx_buf, (const void *)addr, t->len); + } else if (t->tx_buf) { + unsigned char buf[t->len]; + memcpy(buf, (const void *)addr, t->len); + if (memcmp(t->tx_buf, buf, t->len) != 0) + m->status = -EMSGSIZE; + } + m->actual_length += t->len; + + if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) { + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + } + + return 0; +} + +static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m) +{ + struct spi_transfer *t = NULL; + void __iomem *base = rbspi->base; + + m->status = 0; + if (list_empty(&m->transfers)) + return -1; + + if (m->fast_read) + if (rb4xx_spi_read_fast(rbspi, m) == 0) + return -1; + + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); + __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL); + do_spi_init(m->spi); + + list_for_each_entry(t, &m->transfers, transfer_list) { + int len; + + len = rb4xx_spi_txrx(base, t); + if (len != t->len) { + m->status = -EMSGSIZE; + break; + } + m->actual_length += len; + + if (t->cs_change) { + if (list_is_last(&t->transfer_list, &m->transfers)) { + /* wait for continuation */ + return m->spi->chip_select; + } + do_spi_finish(base); + ndelay(100); + } + } + + do_spi_finish(base); + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL); + __raw_writel(0, base + AR71XX_SPI_REG_FS); + return -1; +} + +static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi, + unsigned long *flags) +{ + int cs = rbspi->cs_wait; + + rbspi->busy = 1; + while (!list_empty(&rbspi->queue)) { + struct spi_message *m; + + list_for_each_entry(m, &rbspi->queue, queue) + if (cs < 0 || cs == m->spi->chip_select) + break; + + if (&m->queue == &rbspi->queue) + break; + + list_del_init(&m->queue); + spin_unlock_irqrestore(&rbspi->lock, *flags); + + cs = rb4xx_spi_msg(rbspi, m); + m->complete(m->context); + + spin_lock_irqsave(&rbspi->lock, *flags); + } + + rbspi->cs_wait = cs; + rbspi->busy = 0; + + if (cs >= 0) { + /* TODO: add timer to unlock cs after 1s inactivity */ + } +} + +static int rb4xx_spi_transfer(struct spi_device *spi, + struct spi_message *m) +{ + struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); + unsigned long flags; + + m->actual_length = 0; + m->status = -EINPROGRESS; + + spin_lock_irqsave(&rbspi->lock, flags); + list_add_tail(&m->queue, &rbspi->queue); + if (rbspi->busy || + (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) { + /* job will be done later */ + spin_unlock_irqrestore(&rbspi->lock, flags); + return 0; + } + + /* process job in current context */ + rb4xx_spi_process_queue_locked(rbspi, &flags); + spin_unlock_irqrestore(&rbspi->lock, flags); + + return 0; +} + +static int rb4xx_spi_setup(struct spi_device *spi) +{ + struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); + unsigned long flags; + + if (spi->mode & ~(SPI_CS_HIGH)) { + dev_err(&spi->dev, "mode %x not supported\n", + (unsigned) spi->mode); + return -EINVAL; + } + + if (spi->bits_per_word != 8 && spi->bits_per_word != 0) { + dev_err(&spi->dev, "bits_per_word %u not supported\n", + (unsigned) spi->bits_per_word); + return -EINVAL; + } + + spin_lock_irqsave(&rbspi->lock, flags); + if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) { + rbspi->cs_wait = -1; + rb4xx_spi_process_queue_locked(rbspi, &flags); + } + spin_unlock_irqrestore(&rbspi->lock, flags); + + return 0; +} + +static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max, + const char *name) +{ + unsigned div; + + div = (rbspi->ahb_freq - 1) / (2 * hz_max); + + /* + * CPU has a bug at (div == 0) - first bit read is random + */ + if (div == 0) + ++div; + + if (name) { + unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000; + unsigned div_real = 2 * (div + 1); + pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n", + name, + ahb_khz / div_real, + ahb_khz, div_real); + } + + return SPI_CTRL_FASTEST + div; +} + +static int rb4xx_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct rb4xx_spi *rbspi; + struct resource *r; + int err = 0; + + master = spi_alloc_master(&pdev->dev, sizeof(*rbspi)); + if (master == NULL) { + dev_err(&pdev->dev, "no memory for spi_master\n"); + err = -ENOMEM; + goto err_out; + } + + master->bus_num = 0; + master->num_chipselect = 3; + master->setup = rb4xx_spi_setup; + master->transfer = rb4xx_spi_transfer; + + rbspi = spi_master_get_devdata(master); + + rbspi->ahb_clk = clk_get(&pdev->dev, "ahb"); + if (IS_ERR(rbspi->ahb_clk)) { + err = PTR_ERR(rbspi->ahb_clk); + goto err_put_master; + } + + err = clk_enable(rbspi->ahb_clk); + if (err) + goto err_clk_put; + + rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk); + if (!rbspi->ahb_freq) { + err = -EINVAL; + goto err_clk_disable; + } + + platform_set_drvdata(pdev, rbspi); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + err = -ENOENT; + goto err_clk_disable; + } + + rbspi->base = ioremap(r->start, r->end - r->start + 1); + if (!rbspi->base) { + err = -ENXIO; + goto err_clk_disable; + } + + rbspi->master = master; + rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH"); + rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD"); + rbspi->cs_wait = -1; + + spin_lock_init(&rbspi->lock); + INIT_LIST_HEAD(&rbspi->queue); + + err = spi_register_master(master); + if (err) { + dev_err(&pdev->dev, "failed to register SPI master\n"); + goto err_iounmap; + } + + return 0; + +err_iounmap: + iounmap(rbspi->base); +err_clk_disable: + clk_disable(rbspi->ahb_clk); +err_clk_put: + clk_put(rbspi->ahb_clk); +err_put_master: + platform_set_drvdata(pdev, NULL); + spi_master_put(master); +err_out: + return err; +} + +static int rb4xx_spi_remove(struct platform_device *pdev) +{ + struct rb4xx_spi *rbspi = platform_get_drvdata(pdev); + + iounmap(rbspi->base); + clk_disable(rbspi->ahb_clk); + clk_put(rbspi->ahb_clk); + platform_set_drvdata(pdev, NULL); + spi_master_put(rbspi->master); + + return 0; +} + +static struct platform_driver rb4xx_spi_drv = { + .probe = rb4xx_spi_probe, + .remove = rb4xx_spi_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb4xx_spi_init(void) +{ + return platform_driver_register(&rb4xx_spi_drv); +} +subsys_initcall(rb4xx_spi_init); + +static void __exit rb4xx_spi_exit(void) +{ + platform_driver_unregister(&rb4xx_spi_drv); +} + +module_exit(rb4xx_spi_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c b/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c new file mode 100644 index 0000000..b712e71 --- /dev/null +++ b/target/linux/ar71xx/files/drivers/spi/spi-vsc7385.c @@ -0,0 +1,621 @@ +/* + * SPI driver for the Vitesse VSC7385 ethernet switch + * + * Copyright (C) 2009 Gabor Juhos + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "spi-vsc7385" +#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" +#define DRV_VERSION "0.1.0" + +#define VSC73XX_BLOCK_MAC 0x1 +#define VSC73XX_BLOCK_2 0x2 +#define VSC73XX_BLOCK_MII 0x3 +#define VSC73XX_BLOCK_4 0x4 +#define VSC73XX_BLOCK_5 0x5 +#define VSC73XX_BLOCK_SYSTEM 0x7 + +#define VSC73XX_SUBBLOCK_PORT_0 0 +#define VSC73XX_SUBBLOCK_PORT_1 1 +#define VSC73XX_SUBBLOCK_PORT_2 2 +#define VSC73XX_SUBBLOCK_PORT_3 3 +#define VSC73XX_SUBBLOCK_PORT_4 4 +#define VSC73XX_SUBBLOCK_PORT_MAC 6 + +/* MAC Block registers */ +#define VSC73XX_MAC_CFG 0x0 +#define VSC73XX_ADVPORTM 0x19 +#define VSC73XX_RXOCT 0x50 +#define VSC73XX_TXOCT 0x51 +#define VSC73XX_C_RX0 0x52 +#define VSC73XX_C_RX1 0x53 +#define VSC73XX_C_RX2 0x54 +#define VSC73XX_C_TX0 0x55 +#define VSC73XX_C_TX1 0x56 +#define VSC73XX_C_TX2 0x57 +#define VSC73XX_C_CFG 0x58 + +/* MAC_CFG register bits */ +#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) +#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) +#define VSC73XX_MAC_CFG_TX_EN (1 << 28) +#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) +#define VSC73XX_MAC_CFG_FDX (1 << 18) +#define VSC73XX_MAC_CFG_GIGE (1 << 17) +#define VSC73XX_MAC_CFG_RX_EN (1 << 16) +#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) +#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) +#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) +#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) +#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) +#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) +#define VSC73XX_MAC_CFG_BIT2 (1 << 2) +#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) + +/* ADVPORTM register bits */ +#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) +#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) +#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) +#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) +#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) +#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) +#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) +#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) + +/* MII Block registers */ +#define VSC73XX_MII_STAT 0x0 +#define VSC73XX_MII_CMD 0x1 +#define VSC73XX_MII_DATA 0x2 + +/* System Block registers */ +#define VSC73XX_ICPU_SIPAD 0x01 +#define VSC73XX_ICPU_CLOCK_DELAY 0x05 +#define VSC73XX_ICPU_CTRL 0x10 +#define VSC73XX_ICPU_ADDR 0x11 +#define VSC73XX_ICPU_SRAM 0x12 +#define VSC73XX_ICPU_MBOX_VAL 0x15 +#define VSC73XX_ICPU_MBOX_SET 0x16 +#define VSC73XX_ICPU_MBOX_CLR 0x17 +#define VSC73XX_ICPU_CHIPID 0x18 +#define VSC73XX_ICPU_GPIO 0x34 + +#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) +#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) +#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) +#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) +#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) +#define VSC73XX_ICPU_CTRL_SRST (1 << 0) + +#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 +#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff +#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 +#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf +#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 +#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 + +#define VSC73XX_CMD_MODE_READ 0 +#define VSC73XX_CMD_MODE_WRITE 1 +#define VSC73XX_CMD_MODE_SHIFT 4 +#define VSC73XX_CMD_BLOCK_SHIFT 5 +#define VSC73XX_CMD_BLOCK_MASK 0x7 +#define VSC73XX_CMD_SUBBLOCK_MASK 0xf + +#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) +#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) + +#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ + VSC73XX_ICPU_CTRL_BOOT_EN | \ + VSC73XX_ICPU_CTRL_EXT_ACC_EN) + +#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ + VSC73XX_ICPU_CTRL_BOOT_EN | \ + VSC73XX_ICPU_CTRL_CLK_EN | \ + VSC73XX_ICPU_CTRL_SRST) + +#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ + VSC73XX_ADVPORTM_EXC_COL_CONT | \ + VSC73XX_ADVPORTM_EXT_PORT | \ + VSC73XX_ADVPORTM_INV_GTX | \ + VSC73XX_ADVPORTM_ENA_GTX | \ + VSC73XX_ADVPORTM_DDR_MODE | \ + VSC73XX_ADVPORTM_IO_LOOPBACK | \ + VSC73XX_ADVPORTM_HOST_LOOPBACK) + +#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ + VSC73XX_ADVPORTM_ENA_GTX | \ + VSC73XX_ADVPORTM_DDR_MODE) + +#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ + VSC73XX_MAC_CFG_MAC_RX_RST | \ + VSC73XX_MAC_CFG_MAC_TX_RST) + +#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ + VSC73XX_MAC_CFG_FDX | \ + VSC73XX_MAC_CFG_GIGE | \ + VSC73XX_MAC_CFG_RX_EN) + +#define VSC73XX_RESET_DELAY 100 + +struct vsc7385 { + struct spi_device *spi; + struct mutex lock; + struct vsc7385_platform_data *pdata; +}; + +static int vsc7385_is_addr_valid(u8 block, u8 subblock) +{ + switch (block) { + case VSC73XX_BLOCK_MAC: + switch (subblock) { + case 0 ... 4: + case 6: + return 1; + } + break; + + case VSC73XX_BLOCK_2: + case VSC73XX_BLOCK_SYSTEM: + switch (subblock) { + case 0: + return 1; + } + break; + + case VSC73XX_BLOCK_MII: + case VSC73XX_BLOCK_4: + case VSC73XX_BLOCK_5: + switch (subblock) { + case 0 ... 1: + return 1; + } + break; + } + + return 0; +} + +static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) +{ + u8 ret; + + ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; + ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; + ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; + + return ret; +} + +static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, + u32 *value) +{ + u8 cmd[4]; + u8 buf[4]; + struct spi_transfer t[2]; + struct spi_message m; + int err; + + if (!vsc7385_is_addr_valid(block, subblock)) + return -EINVAL; + + spi_message_init(&m); + + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + t[1].rx_buf = buf; + t[1].len = sizeof(buf); + spi_message_add_tail(&t[1], &m); + + cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); + cmd[1] = reg; + cmd[2] = 0; + cmd[3] = 0; + + mutex_lock(&vsc->lock); + err = spi_sync(vsc->spi, &m); + mutex_unlock(&vsc->lock); + + if (err) + return err; + + *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | + (((u32) buf[2]) << 8) | ((u32) buf[3]); + + return 0; +} + + +static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, + u32 value) +{ + u8 cmd[2]; + u8 buf[4]; + struct spi_transfer t[2]; + struct spi_message m; + int err; + + if (!vsc7385_is_addr_valid(block, subblock)) + return -EINVAL; + + spi_message_init(&m); + + memset(&t, 0, sizeof(t)); + + t[0].tx_buf = cmd; + t[0].len = sizeof(cmd); + spi_message_add_tail(&t[0], &m); + + t[1].tx_buf = buf; + t[1].len = sizeof(buf); + spi_message_add_tail(&t[1], &m); + + cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); + cmd[1] = reg; + + buf[0] = (value >> 24) & 0xff; + buf[1] = (value >> 16) & 0xff; + buf[2] = (value >> 8) & 0xff; + buf[3] = value & 0xff; + + mutex_lock(&vsc->lock); + err = spi_sync(vsc->spi, &m); + mutex_unlock(&vsc->lock); + + return err; +} + +static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, + u8 subblock, u8 reg, u32 value, + u32 read_mask, u32 read_val) +{ + struct spi_device *spi = vsc->spi; + u32 t; + int err; + + err = vsc7385_write(vsc, block, subblock, reg, value); + if (err) + return err; + + err = vsc7385_read(vsc, block, subblock, reg, &t); + if (err) + return err; + + if ((t & read_mask) != read_val) { + dev_err(&spi->dev, "register write error\n"); + return -EIO; + } + + return 0; +} + +static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, val); +} + +static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) +{ + return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, val); +} + +static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, + VSC73XX_ICPU_CTRL_STOP); +} + +static inline int vsc7385_icpu_start(struct vsc7385 *vsc) +{ + return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, + VSC73XX_ICPU_CTRL_START); +} + +static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) +{ + int rc; + + rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, + 0x0000); + if (rc) + dev_err(&vsc->spi->dev, + "could not reset microcode, err=%d\n", rc); + + return rc; +} + +static int vsc7385_upload_ucode(struct vsc7385 *vsc) +{ + struct spi_device *spi = vsc->spi; + const struct firmware *firmware; + char *ucode_name; + unsigned char *dp; + unsigned int curVal; + int i; + int diffs; + int rc; + + ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name + : "vsc7385_ucode.bin"; + rc = request_firmware(&firmware, ucode_name, &spi->dev); + if (rc) { + dev_err(&spi->dev, "request_firmware failed, err=%d\n", + rc); + return rc; + } + + rc = vsc7385_icpu_stop(vsc); + if (rc) + goto out; + + rc = vsc7385_icpu_reset(vsc); + if (rc) + goto out; + + dev_info(&spi->dev, "uploading microcode...\n"); + + dp = (unsigned char *) firmware->data; + for (i = 0; i < firmware->size; i++) { + rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_SRAM, *dp++); + if (rc) { + dev_err(&spi->dev, "could not load microcode, err=%d\n", + rc); + goto out; + } + } + + rc = vsc7385_icpu_reset(vsc); + if (rc) + goto out; + + dev_info(&spi->dev, "verifying microcode...\n"); + + dp = (unsigned char *) firmware->data; + diffs = 0; + for (i = 0; i < firmware->size; i++) { + rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_SRAM, &curVal); + if (rc) { + dev_err(&spi->dev, "could not read microcode %d\n", + rc); + goto out; + } + + if (curVal > 0xff) { + dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", + i, *dp, curVal); + rc = -EIO; + goto out; + } + + if ((curVal & 0xff) != *dp) { + diffs++; + dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", + i, *dp, curVal); + + if (diffs > 4) + break; + } + dp++; + } + + if (diffs) { + dev_err(&spi->dev, "microcode verification failed\n"); + rc = -EIO; + goto out; + } + + dev_info(&spi->dev, "microcode uploaded\n"); + + rc = vsc7385_icpu_start(vsc); + +out: + release_firmware(firmware); + return rc; +} + +static int vsc7385_setup(struct vsc7385 *vsc) +{ + struct vsc7385_platform_data *pdata = vsc->pdata; + u32 t; + int err; + + err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CLOCK_DELAY, + VSC7385_CLOCK_DELAY, + VSC7385_CLOCK_DELAY_MASK, + VSC7385_CLOCK_DELAY); + if (err) + goto err; + + err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, + VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, + VSC7385_ADVPORTM_INIT, + VSC7385_ADVPORTM_MASK, + VSC7385_ADVPORTM_INIT); + if (err) + goto err; + + err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, + VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); + if (err) + goto err; + + t = VSC73XX_MAC_CFG_INIT; + t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); + t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); + if (pdata->mac_cfg.bit2) + t |= VSC73XX_MAC_CFG_BIT2; + + err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, + VSC73XX_MAC_CFG, t); + if (err) + goto err; + + return 0; + +err: + return err; +} + +static int vsc7385_detect(struct vsc7385 *vsc) +{ + struct spi_device *spi = vsc->spi; + u32 t; + u32 id; + u32 rev; + int err; + + err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_MBOX_VAL, &t); + if (err) { + dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); + return err; + } + + if (t == 0xffffffff) { + dev_dbg(&spi->dev, "assert chip reset\n"); + if (vsc->pdata->reset) + vsc->pdata->reset(); + + } + + err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, + VSC73XX_ICPU_CHIPID, &t); + if (err) { + dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); + return err; + } + + id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; + switch (id) { + case VSC73XX_ICPU_CHIPID_ID_7385: + case VSC73XX_ICPU_CHIPID_ID_7395: + break; + default: + dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); + return -ENODEV; + } + + rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & + VSC73XX_ICPU_CHIPID_REV_MASK; + dev_info(&spi->dev, "VSC%04X (rev. %d) switch found\n", id, rev); + + return 0; +} + +static int vsc7385_probe(struct spi_device *spi) +{ + struct vsc7385 *vsc; + struct vsc7385_platform_data *pdata; + int err; + + printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); + + pdata = spi->dev.platform_data; + if (!pdata) { + dev_err(&spi->dev, "no platform data specified\n"); + return -ENODEV; + } + + vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); + if (!vsc) { + dev_err(&spi->dev, "no memory for private data\n"); + return -ENOMEM; + } + + mutex_init(&vsc->lock); + vsc->pdata = pdata; + vsc->spi = spi_dev_get(spi); + dev_set_drvdata(&spi->dev, vsc); + + spi->mode = SPI_MODE_0; + spi->bits_per_word = 8; + err = spi_setup(spi); + if (err) { + dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); + goto err_drvdata; + } + + err = vsc7385_detect(vsc); + if (err) { + dev_err(&spi->dev, "no chip found, err=%d\n", err); + goto err_drvdata; + } + + err = vsc7385_upload_ucode(vsc); + if (err) + goto err_drvdata; + + err = vsc7385_setup(vsc); + if (err) + goto err_drvdata; + + return 0; + +err_drvdata: + dev_set_drvdata(&spi->dev, NULL); + kfree(vsc); + return err; +} + +static int vsc7385_remove(struct spi_device *spi) +{ + struct vsc7385_data *vsc; + + vsc = dev_get_drvdata(&spi->dev); + dev_set_drvdata(&spi->dev, NULL); + kfree(vsc); + + return 0; +} + +static struct spi_driver vsc7385_driver = { + .driver = { + .name = DRV_NAME, + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = vsc7385_probe, + .remove = vsc7385_remove, +}; + +static int __init vsc7385_init(void) +{ + return spi_register_driver(&vsc7385_driver); +} +module_init(vsc7385_init); + +static void __exit vsc7385_exit(void) +{ + spi_unregister_driver(&vsc7385_driver); +} +module_exit(vsc7385_exit); + +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); + diff --git a/target/linux/ar71xx/files/include/linux/nxp_74hc153.h b/target/linux/ar71xx/files/include/linux/nxp_74hc153.h new file mode 100644 index 0000000..20b8845 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/nxp_74hc153.h @@ -0,0 +1,24 @@ +/* + * NXP 74HC153 - Dual 4-input multiplexer defines + * + * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _NXP_74HC153_H +#define _NXP_74HC153_H + +#define NXP_74HC153_DRIVER_NAME "nxp-74hc153" + +struct nxp_74hc153_platform_data { + unsigned gpio_base; + unsigned gpio_pin_s0; + unsigned gpio_pin_s1; + unsigned gpio_pin_1y; + unsigned gpio_pin_2y; +}; + +#endif /* _NXP_74HC153_H */ diff --git a/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h b/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h new file mode 100644 index 0000000..371aaee --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/platform/ar934x_nfc.h @@ -0,0 +1,39 @@ +/* + * Platform data definition for the built-in NAND controller of the + * Atheros AR934x SoCs + * + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _AR934X_NFC_PLATFORM_H +#define _AR934X_NFC_PLATFORM_H + +#define AR934X_NFC_DRIVER_NAME "ar934x-nfc" + +struct mtd_info; +struct mtd_partition; + +enum ar934x_nfc_ecc_mode { + AR934X_NFC_ECC_SOFT = 0, + AR934X_NFC_ECC_HW, + AR934X_NFC_ECC_SOFT_BCH, +}; + +struct ar934x_nfc_platform_data { + const char *name; + struct mtd_partition *parts; + int nr_parts; + + bool swap_dma; + enum ar934x_nfc_ecc_mode ecc_mode; + + void (*hw_reset)(bool active); + void (*select_chip)(int chip_no); + int (*scan_fixup)(struct mtd_info *mtd); +}; + +#endif /* _AR934X_NFC_PLATFORM_H */ diff --git a/target/linux/ar71xx/files/include/linux/platform_data/gpio-latch.h b/target/linux/ar71xx/files/include/linux/platform_data/gpio-latch.h new file mode 100644 index 0000000..0450e67 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/platform_data/gpio-latch.h @@ -0,0 +1,14 @@ +#ifndef _GPIO_LATCH_H_ +#define _GPIO_LATCH_H_ + +#define GPIO_LATCH_DRIVER_NAME "gpio-latch" + +struct gpio_latch_platform_data { + int base; + int num_gpios; + int *gpios; + int le_gpio_index; + bool le_active_low; +}; + +#endif /* _GPIO_LATCH_H_ */ diff --git a/target/linux/ar71xx/files/include/linux/platform_data/rb91x_nand.h b/target/linux/ar71xx/files/include/linux/platform_data/rb91x_nand.h new file mode 100644 index 0000000..5f17fb8 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/platform_data/rb91x_nand.h @@ -0,0 +1,16 @@ +#ifndef _RB91X_NAND_H_ +#define _RB91X_NAND_H_ + +#define RB91X_NAND_DRIVER_NAME "rb91x-nand" + +struct rb91x_nand_platform_data { + int gpio_nce; /* chip enable, active low */ + int gpio_ale; /* address latch enable */ + int gpio_cle; /* command latch enable */ + int gpio_rdy; + int gpio_read; + int gpio_nrw; /* read/write enable, active low */ + int gpio_nle; /* latch enable, active low */ +}; + +#endif /* _RB91X_NAND_H_ */ \ No newline at end of file diff --git a/target/linux/ar71xx/files/include/linux/spi/vsc7385.h b/target/linux/ar71xx/files/include/linux/spi/vsc7385.h new file mode 100644 index 0000000..1072ad7 --- /dev/null +++ b/target/linux/ar71xx/files/include/linux/spi/vsc7385.h @@ -0,0 +1,19 @@ +/* + * Platform data definition for the Vitesse VSC7385 ethernet switch driver + * + * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +struct vsc7385_platform_data { + void (*reset)(void); + char *ucode_name; + struct { + u32 tx_ipg:5; + u32 bit2:1; + u32 clk_sel:3; + } mac_cfg; +}; diff --git a/target/linux/ar71xx/files/net/dsa/mv88e6063.c b/target/linux/ar71xx/files/net/dsa/mv88e6063.c new file mode 100644 index 0000000..5638a9f --- /dev/null +++ b/target/linux/ar71xx/files/net/dsa/mv88e6063.c @@ -0,0 +1,294 @@ +/* + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips + * Copyright (c) 2009 Gabor Juhos + * + * This driver was base on: net/dsa/mv88e6060.c + * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips + * Copyright (c) 2008-2009 Marvell Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include "dsa_priv.h" + +#define REG_BASE 0x10 +#define REG_PHY(p) (REG_BASE + (p)) +#define REG_PORT(p) (REG_BASE + 8 + (p)) +#define REG_GLOBAL (REG_BASE + 0x0f) +#define NUM_PORTS 7 + +static int reg_read(struct dsa_switch *ds, int addr, int reg) +{ + return mdiobus_read(ds->master_mii_bus, addr, reg); +} + +#define REG_READ(addr, reg) \ + ({ \ + int __ret; \ + \ + __ret = reg_read(ds, addr, reg); \ + if (__ret < 0) \ + return __ret; \ + __ret; \ + }) + + +static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) +{ + return mdiobus_write(ds->master_mii_bus, addr, reg, val); +} + +#define REG_WRITE(addr, reg, val) \ + ({ \ + int __ret; \ + \ + __ret = reg_write(ds, addr, reg, val); \ + if (__ret < 0) \ + return __ret; \ + }) + +static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) +{ + int ret; + + ret = mdiobus_read(bus, REG_PORT(0), 0x03); + if (ret >= 0) { + ret &= 0xfff0; + if (ret == 0x1530) + return "Marvell 88E6063"; + } + + return NULL; +} + +static int mv88e6063_switch_reset(struct dsa_switch *ds) +{ + int i; + int ret; + + /* + * Set all ports to the disabled state. + */ + for (i = 0; i < NUM_PORTS; i++) { + ret = REG_READ(REG_PORT(i), 0x04); + REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); + } + + /* + * Wait for transmit queues to drain. + */ + msleep(2); + + /* + * Reset the switch. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); + + /* + * Wait up to one second for reset to complete. + */ + for (i = 0; i < 1000; i++) { + ret = REG_READ(REG_GLOBAL, 0x00); + if ((ret & 0x8000) == 0x0000) + break; + + msleep(1); + } + if (i == 1000) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e6063_setup_global(struct dsa_switch *ds) +{ + /* + * Disable discarding of frames with excessive collisions, + * set the maximum frame size to 1536 bytes, and mask all + * interrupt sources. + */ + REG_WRITE(REG_GLOBAL, 0x04, 0x0800); + + /* + * Enable automatic address learning, set the address + * database size to 1024 entries, and set the default aging + * time to 5 minutes. + */ + REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); + + return 0; +} + +static int mv88e6063_setup_port(struct dsa_switch *ds, int p) +{ + int addr = REG_PORT(p); + + /* + * Do not force flow control, disable Ingress and Egress + * Header tagging, disable VLAN tunneling, and set the port + * state to Forwarding. Additionally, if this is the CPU + * port, enable Ingress and Egress Trailer tagging mode. + */ + REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); + + /* + * Port based VLAN map: give each port its own address + * database, allow the CPU port to talk to each of the 'real' + * ports, and allow each of the 'real' ports to only talk to + * the CPU port. + */ + REG_WRITE(addr, 0x06, + ((p & 0xf) << 12) | + (dsa_is_cpu_port(ds, p) ? + ds->phys_port_mask : + (1 << ds->dst->cpu_port))); + + /* + * Port Association Vector: when learning source addresses + * of packets, add the address to the address database using + * a port bitmap that has only the bit for this port set and + * the other bits clear. + */ + REG_WRITE(addr, 0x0b, 1 << p); + + return 0; +} + +static int mv88e6063_setup(struct dsa_switch *ds) +{ + int i; + int ret; + + ret = mv88e6063_switch_reset(ds); + if (ret < 0) + return ret; + + /* @@@ initialise atu */ + + ret = mv88e6063_setup_global(ds); + if (ret < 0) + return ret; + + for (i = 0; i < NUM_PORTS; i++) { + ret = mv88e6063_setup_port(ds, i); + if (ret < 0) + return ret; + } + + return 0; +} + +static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) +{ + REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); + REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); + REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); + + return 0; +} + +static int mv88e6063_port_to_phy_addr(int port) +{ + if (port >= 0 && port <= NUM_PORTS) + return REG_PHY(port); + return -1; +} + +static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_read(ds, addr, regnum); +} + +static int +mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) +{ + int addr; + + addr = mv88e6063_port_to_phy_addr(port); + if (addr == -1) + return 0xffff; + + return reg_write(ds, addr, regnum, val); +} + +static void mv88e6063_poll_link(struct dsa_switch *ds) +{ + int i; + + for (i = 0; i < DSA_MAX_PORTS; i++) { + struct net_device *dev; + int uninitialized_var(port_status); + int link; + int speed; + int duplex; + int fc; + + dev = ds->ports[i]; + if (dev == NULL) + continue; + + link = 0; + if (dev->flags & IFF_UP) { + port_status = reg_read(ds, REG_PORT(i), 0x00); + if (port_status < 0) + continue; + + link = !!(port_status & 0x1000); + } + + if (!link) { + if (netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link down\n", dev->name); + netif_carrier_off(dev); + } + continue; + } + + speed = (port_status & 0x0100) ? 100 : 10; + duplex = (port_status & 0x0200) ? 1 : 0; + fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; + + if (!netif_carrier_ok(dev)) { + printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " + "flow control %sabled\n", dev->name, + speed, duplex ? "full" : "half", + fc ? "en" : "dis"); + netif_carrier_on(dev); + } + } +} + +static struct dsa_switch_driver mv88e6063_switch_driver = { + .tag_protocol = htons(ETH_P_TRAILER), + .probe = mv88e6063_probe, + .setup = mv88e6063_setup, + .set_addr = mv88e6063_set_addr, + .phy_read = mv88e6063_phy_read, + .phy_write = mv88e6063_phy_write, + .poll_link = mv88e6063_poll_link, +}; + +static int __init mv88e6063_init(void) +{ + register_switch_driver(&mv88e6063_switch_driver); + return 0; +} +module_init(mv88e6063_init); + +static void __exit mv88e6063_cleanup(void) +{ + unregister_switch_driver(&mv88e6063_switch_driver); +} +module_exit(mv88e6063_cleanup); diff --git a/target/linux/ar71xx/generic/config-default b/target/linux/ar71xx/generic/config-default new file mode 100644 index 0000000..4516968 --- /dev/null +++ b/target/linux/ar71xx/generic/config-default @@ -0,0 +1 @@ +CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd" diff --git a/target/linux/ar71xx/generic/profiles/00-default.mk b/target/linux/ar71xx/generic/profiles/00-default.mk new file mode 100644 index 0000000..36c4aa6 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/00-default.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (all drivers) + PACKAGES:= \ + kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/ar71xx/generic/profiles/01-minimal.mk b/target/linux/ar71xx/generic/profiles/01-minimal.mk new file mode 100644 index 0000000..dfaa3b0 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/01-minimal.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Minimal + NAME:=Minimal Profile (no drivers) + PACKAGES:=-kmod-ath9k -wpad-mini +endef + +define Profile/Minimal/Description + Minimal package set compatible with most boards. +endef +$(eval $(call Profile,Minimal)) diff --git a/target/linux/ar71xx/generic/profiles/02-ath5k.mk b/target/linux/ar71xx/generic/profiles/02-ath5k.mk new file mode 100644 index 0000000..7820349 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/02-ath5k.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ath5k + NAME:=Atheros 802.11abg WiFi (ath5k) + PACKAGES:=kmod-ath5k -kmod-ath9k +endef + +define Profile/ath5k/Description + Package set compatible with hardware using Atheros 802.11abg cards. +endef +$(eval $(call Profile,ath5k)) diff --git a/target/linux/ar71xx/generic/profiles/8devices.mk b/target/linux/ar71xx/generic/profiles/8devices.mk new file mode 100644 index 0000000..209403a --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/8devices.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CARAMBOLA2 + NAME:=Carambola2 board from 8Devices + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/CARAMBOLA2/Description + Package set optimized for the 8devices Carambola2 board. +endef + +$(eval $(call Profile,CARAMBOLA2)) diff --git a/target/linux/ar71xx/generic/profiles/alfa.mk b/target/linux/ar71xx/generic/profiles/alfa.mk new file mode 100644 index 0000000..6e259dc --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/alfa.mk @@ -0,0 +1,66 @@ +# +# Copyright (C) 2011-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ALFAAP96 + NAME:=ALFA Network AP96 board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-rtc-pcf2123 +endef + +define Profile/ALFAAP96/Description + Package set optimized for the ALFA Network AP96 board. +endef + +$(eval $(call Profile,ALFAAP96)) + + +define Profile/HORNETUB + NAME:=ALFA Network Hornet-UB board (8MB flash, 32MB ram) + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/HORNETUB/Description + Package set optimized for the ALFA Network Hornet-UB board with 8MB + flash and 32MB ram. +endef + +$(eval $(call Profile,HORNETUB)) + + +define Profile/HORNETUBx2 + NAME:=ALFA Network Hornet-UB-x2 board (16MB flash, 64MB ram) + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/HORNETUBx2/Description + Package set optimized for the ALFA Network Hornet-UB board with 16MB + flash and 64MB ram. +endef + +$(eval $(call Profile,HORNETUBx2)) + + +define Profile/ALFANX + NAME:=ALFA Network N2/N5 board + PACKAGES:= +endef + +define Profile/ALFANX/Description + Package set optimized for the ALFA Network N2/N5 boards. +endef + +$(eval $(call Profile,ALFANX)) + +define Profile/TUBE2H + NAME:=ALFA Network Tube2H board + PACKAGES:= +endef + +define Profile/TUBE2H/Description + Package set optimized for the ALFA Network Tube2H board. +endef + +$(eval $(call Profile,TUBE2H)) diff --git a/target/linux/ar71xx/generic/profiles/allnet.mk b/target/linux/ar71xx/generic/profiles/allnet.mk new file mode 100644 index 0000000..07ca964 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/allnet.mk @@ -0,0 +1,39 @@ +# +# Copyright (C) 20012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ALL0305 + NAME:=Allnet ALL0305 + PACKAGES:=fconfig kmod-ath5k -kmod-ath9k +endef + +define Profile/ALL0305/Description + Package set optimized for the Allnet ALL0305. +endef + +$(eval $(call Profile,ALL0305)) + +define Profile/ALL0258N + NAME:=Allnet ALL0258N + PACKAGES:=uboot-envtools rssileds +endef + +define Profile/ALL0258N/Description + Package set optimized for the Allnet ALL0258N. +endef + +$(eval $(call Profile,ALL0258N)) + +define Profile/ALL0315N + NAME:=Allnet ALL0315N + PACKAGES:=uboot-envtools rssileds +endef + +define Profile/ALL0315N/Description + Package set optimized for the Allnet ALL0315N. +endef + +$(eval $(call Profile,ALL0315N)) diff --git a/target/linux/ar71xx/generic/profiles/antminer.mk b/target/linux/ar71xx/generic/profiles/antminer.mk new file mode 100644 index 0000000..d59a089 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/antminer.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ANTMINERS1 + NAME:=Antminer-S1 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-crypto-manager kmod-i2c-gpio-custom kmod-usb-hid +endef + + +define Profile/ANTMINERS1/Description + Package set optimized for the Bitmain Antminer S1. +endef +$(eval $(call Profile,ANTMINERS1)) + +define Profile/ANTMINERS3 + NAME:=Antminer-S3 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-crypto-manager kmod-i2c-gpio-custom kmod-usb-hid +endef + + +define Profile/ANTMINERS3/Description + Package set optimized for the Bitmain Antminer S3. +endef +$(eval $(call Profile,ANTMINERS3)) diff --git a/target/linux/ar71xx/generic/profiles/atheros.mk b/target/linux/ar71xx/generic/profiles/atheros.mk new file mode 100644 index 0000000..3a312a4 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/atheros.mk @@ -0,0 +1,184 @@ +# +# Copyright (C) 2009-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/AP113 + NAME:=Atheros AP113 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP113/description + Package set optimized for the Atheros AP113 reference board. +endef + +$(eval $(call Profile,AP113)) + +define Profile/AP121 + NAME:=Atheros AP121 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP121/Description + Package set optimized for the Atheros AP121 reference board. +endef + +$(eval $(call Profile,AP121)) + +define Profile/AP121MINI + NAME:=Atheros AP121-MINI reference board + PACKAGES:= +endef + +define Profile/AP121MINI/Description + Package set optimized for the Atheros AP121-MINI reference board. +endef + +$(eval $(call Profile,AP121MINI)) + +define Profile/AP132 + NAME:=Atheros AP132 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP132/Description + Package set optimized for the Atheros AP132 reference board. +endef + +$(eval $(call Profile,AP132)) + +define Profile/AP135 + NAME:=Atheros AP135 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP135/Description + Package set optimized for the Atheros AP135 reference board. +endef + +$(eval $(call Profile,AP135)) + +define Profile/AP136 + NAME:=Atheros AP136 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP136/Description + Package set optimized for the Atheros AP136 reference board. +endef + +$(eval $(call Profile,AP136)) + +define Profile/AP143 + NAME:=Qualcomm Atheros AP143 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP143/Description + Package set optimized for the Qualcomm Atheros AP143 reference board. +endef + +$(eval $(call Profile,AP143)) + +define Profile/AP147 + NAME:=Qualcomm Atheros AP147 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP147/Description + Package set optimized for the Atheros AP147 reference board. +endef + +$(eval $(call Profile,AP147)) + +define Profile/AP152 + NAME:=Qualcomm Atheros AP152 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/AP152/Description + Package set optimized for the Qualcomm Atheros AP152 reference board. +endef + +$(eval $(call Profile,AP152)) + +define Profile/AP81 + NAME:=Atheros AP81 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP81/Description + Package set optimized for the Atheros AP81 reference board. +endef + +$(eval $(call Profile,AP81)) + +define Profile/AP83 + NAME:=Atheros AP83 reference board + PACKAGES:=kmod-usb-core kmod-usb2 \ + vsc7385-ucode-ap83 vsc7395-ucode-ap83 +endef + +define Profile/AP83/Description + Package set optimized for the Atheros AP83 reference board. +endef + +$(eval $(call Profile,AP83)) + +define Profile/AP96 + NAME:=Atheros AP96 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/AP96/Description + Package set optimized for the Atheros AP96 reference board. +endef + +$(eval $(call Profile,AP96)) + +define Profile/DB120 + NAME:=Atheros DB120 reference board + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage +endef + +define Profile/DB120/Description + Package set optimized for the Atheros DB120 reference board. +endef + +$(eval $(call Profile,DB120)) + +define Profile/PB42 + NAME:=Atheros PB42 reference board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/PB42/Description + Package set optimized for the Atheros PB42 reference board. +endef + +$(eval $(call Profile,PB42)) + +define Profile/PB44 + NAME:=Atheros PB44 reference board + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 \ + vsc7385-ucode-pb44 vsc7395-ucode-pb44 +endef + +define Profile/PB44/Description + Package set optimized for the Atheros PB44 reference board. +endef + +$(eval $(call Profile,PB44)) + +define Profile/PB92 + NAME:=Atheros PB92 reference board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/PB92/Description + Package set optimized for the Atheros PB92 reference board. +endef + +$(eval $(call Profile,PB92)) diff --git a/target/linux/ar71xx/generic/profiles/atlantis.mk b/target/linux/ar71xx/generic/profiles/atlantis.mk new file mode 100644 index 0000000..073d8d1 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/atlantis.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/A02RBW300N + NAME:=Atlantis-Land A02-RB-W300N + PACKAGES:= +endef + +define Profile/A02RBW300N/Description + Package set optimized for the Atlantis-Land A02-RB-W300N. +endef + +$(eval $(call Profile,A02RBW300N)) diff --git a/target/linux/ar71xx/generic/profiles/belkin.mk b/target/linux/ar71xx/generic/profiles/belkin.mk new file mode 100644 index 0000000..c8f6bde --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/belkin.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/F9K1115V2 + NAME:=Belkin AC1750DB (F9K1115V2) + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb3 kmod-ledtrig-usbdev \ + kmod-ath10k +endef + +define Profile/F9K1115V2/Description + Package set optimized for the Belkin AC1750DB (F9K1115V2) board. +endef + +$(eval $(call Profile,F9K1115V2)) diff --git a/target/linux/ar71xx/generic/profiles/bhu.mk b/target/linux/ar71xx/generic/profiles/bhu.mk new file mode 100644 index 0000000..f21b3c3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/bhu.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 BHU Networks. +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/BXU2000N2 + NAME:=BHU BXU2000n-2 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-usb-storage +endef + +define Profile/BXU2000N2/Description + Package set optimized for the BHU BXU2000n-2. +endef + +$(eval $(call Profile,BXU2000N2)) diff --git a/target/linux/ar71xx/generic/profiles/buffalo.mk b/target/linux/ar71xx/generic/profiles/buffalo.mk new file mode 100644 index 0000000..900f6a8 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/buffalo.mk @@ -0,0 +1,118 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WZRHPG300NH + NAME:=Buffalo WZR-HP-G300NH + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG300NH/Description + Package set optimized for the Buffalo WZR-HP-G300NH and WZR-HP-G301NH +endef + +$(eval $(call Profile,WZRHPG300NH)) + +define Profile/WZRHPG300NH2 + NAME:=Buffalo WZR-HP-G300NH2 + PACKAGES:=kmod-ath9k wpad-mini kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG300NH/Description + Package set optimized for the Buffalo WZR-HP-G300NH2 +endef + +$(eval $(call Profile,WZRHPG300NH2)) + +define Profile/WZRHPAG300H + NAME:=Buffalo WZR-HP-AG300H + PACKAGES:=kmod-usb-ohci kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPAG300H/Description + Package set optimized for the Buffalo WZR-HP-AG300H +endef + +$(eval $(call Profile,WZRHPAG300H)) + +define Profile/WZRHPG450H + NAME:=Buffalo WZR-HP-G450H + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZRHPG450H/Description + Package set optimized for the Buffalo WZR-HP-G450H +endef + +$(eval $(call Profile,WZRHPG450H)) + +define Profile/WZR450HP2 + NAME:=Buffalo WZR-450HP2 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZR450HP2/Description + Package set optimized for the Buffalo WZR-450HP2 +endef + +$(eval $(call Profile,WZR450HP2)) + +define Profile/WZR600DHP + NAME:=Buffalo WZR-600DHP + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WZR600DHP/Description + Package set optimized for the Buffalo WZR-600DHP +endef + +$(eval $(call Profile,WZR600DHP)) + +define Profile/WHRG301N + NAME:=Buffalo WHR-G301N + PACKAGES:= +endef + +define Profile/WHRG301N/Description + Package set optimized for the Buffalo WHR-G301N. +endef + +$(eval $(call Profile,WHRG301N)) + + +define Profile/WHRHPG300N + NAME:=Buffalo WHR-HP-G300N + PACKAGES:= +endef + +define Profile/WHRHPG300N/Description + Package set optimized for the Buffalo WHR-HP-G300N +endef + +$(eval $(call Profile,WHRHPG300N)) + + +define Profile/WHRHPGN + NAME:=Buffalo WHR-HP-GN + PACKAGES:= +endef + +define Profile/WHRHPGN/Description + Package set optimized for the Buffalo WHR-HP-GN. +endef + +$(eval $(call Profile,WHRHPGN)) + +define Profile/WLAEAG300N + NAME:=Buffalo WLAE-AG300N + PACKAGES:=kmod-ledtrig-netdev +endef + +define Profile/WLAEAG300N/Description + Package set optimized for the Buffalo WLAE-AG300N +endef + +$(eval $(call Profile,WLAEAG300N)) diff --git a/target/linux/ar71xx/generic/profiles/comfast.mk b/target/linux/ar71xx/generic/profiles/comfast.mk new file mode 100644 index 0000000..5d447e5 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/comfast.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CF-E316N-V2 + NAME:=COMFAST CF-E316N v2 + PACKAGES:= +endef + +define Profile/CF-E316N-V2/Description + Package set optimised for the COMFAST CF-E316N v2 + by Shenzhen Four Seas Global Link Network Technology Co., Ltd + aka CF-E316V2, CF-E316N-V2 and CF-E316Nv2.0 (no FCC ID) +endef + +$(eval $(call Profile,CF-E316N-V2)) diff --git a/target/linux/ar71xx/generic/profiles/compex.mk b/target/linux/ar71xx/generic/profiles/compex.mk new file mode 100644 index 0000000..2f6e0b2 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/compex.mk @@ -0,0 +1,58 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WP543 + NAME:=Compex WP543/WPJ543 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/WP543/Description + Package set optimized for the Compex WP543/WPJ543 boards. +endef + +$(eval $(call Profile,WP543)) + +define Profile/WPE72 + NAME:=Compex WPE72/WPE72NX + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/WPE72/Description + Package set optimized for the Compex WPE72 boards including Compex WPE72NX Indoor Access Point. +endef + +$(eval $(call Profile,WPE72)) + +define Profile/WPJ344 + NAME:=Compex WPJ344 +endef + +define Profile/WPJ344/Description + Package set optimized for the Compex WPJ344 board. +endef + +$(eval $(call Profile,WPJ344)) + +define Profile/WPJ531 + NAME:=Compex WPJ531 +endef + +define Profile/WPJ531/Description + Package set optimized for the Compex WPJ531 board. +endef + +$(eval $(call Profile,WPJ531)) + +define Profile/WPJ558 + NAME:=Compex WPJ558 +endef + +define Profile/WPJ558/Description + Package set optimized for the Compex WPJ558 board. +endef + +$(eval $(call Profile,WPJ558)) diff --git a/target/linux/ar71xx/generic/profiles/d-link.mk b/target/linux/ar71xx/generic/profiles/d-link.mk new file mode 100644 index 0000000..f782a41 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/d-link.mk @@ -0,0 +1,150 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DHP1565A1 + NAME:=D-Link DHP-1565 rev. A1 + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/DHP1565A1/Description + Package set optimized for the D-Link DHP-1565 rev. A1. +endef + +$(eval $(call Profile,DHP1565A1)) + +define Profile/DIR505A1 + NAME:=D-Link DIR-505 rev. A1 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DIR505A1/Description + Package set optimized for the D-Link DIR-505 rev. A1. +endef + +$(eval $(call Profile,DIR505A1)) + +define Profile/DIR600A1 + NAME:=D-Link DIR-600 rev. A1 + PACKAGES:= +endef + +define Profile/DIR600A1/Description + Package set optimized for the D-Link DIR-600 rev. A1. +endef + +$(eval $(call Profile,DIR600A1)) + +define Profile/DIR601A1 + NAME:=D-Link DIR-601 rev. A1 + PACKAGES:= +endef + +define Profile/DIR601A1/Description + Package set optimized for the D-Link DIR-601 rev. A1. +endef + +$(eval $(call Profile,DIR601A1)) + +define Profile/DIR601B1 + NAME:=D-Link DIR-601 rev. B1 + PACKAGES:= +endef + +define Profile/DIR601B1/Description + Package set optimized for the D-Link DIR-601 rev. B1. +endef + +$(eval $(call Profile,DIR601B1)) + +define Profile/DIR615C1 + NAME:=D-Link DIR-615 rev. C1 + PACKAGES:= +endef + +define Profile/DIR615C1/Description + Package set optimized for the D-Link DIR-615 rev. C1. +endef + +$(eval $(call Profile,DIR615C1)) + +define Profile/DIR615E1 + NAME:=D-Link DIR-615 rev. E1 + PACKAGES:= +endef + +define Profile/DIR615E1/Description + Package set optimized for the D-Link DIR-615 rev. E1. +endef + +$(eval $(call Profile,DIR615E1)) + +define Profile/DIR615E4 + NAME:=D-Link DIR-615 rev. E4 + PACKAGES:= +endef + +define Profile/DIR615E4/Description + Package set optimized for the D-Link DIR-615 rev. E4. +endef + +$(eval $(call Profile,DIR615E4)) + +define Profile/DIR615IX + NAME:=D-Link DIR-615 rev. I1 + PACKAGES:= +endef + +define Profile/DIR615IX/Description + Package set optimized for the D-Link DIR-615 rev. I1. +endef + +$(eval $(call Profile,DIR615IX)) + +define Profile/DIR825B1 + NAME:=D-Link DIR-825 rev. B1 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DIR825B1/Description + Package set optimized for the D-Link DIR-825 rev. B1. +endef + +$(eval $(call Profile,DIR825B1)) + +define Profile/DIR825C1 + NAME:=D-Link DIR-825 rev. C1 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DIR825C1/Description + Package set optimized for the D-Link DIR-825 rev. C1. +endef + +$(eval $(call Profile,DIR825C1)) + +define Profile/DIR835A1 + NAME:=D-Link DIR-835 rev. A1 + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/DIR835A1/Description + Package set optimized for the D-Link DIR-835 rev. A1. +endef + +$(eval $(call Profile,DIR835A1)) + + +define Profile/DGL5500A1 + NAME:=D-Link DGL-5500 rev. A1 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ath10k +endef + +define Profile/DIR5500A1/Description + Package set optimized for the D-Link DGL-5500 rev. A1. +endef + +$(eval $(call Profile,DGL5500A1)) diff --git a/target/linux/ar71xx/generic/profiles/devolo-dlan.mk b/target/linux/ar71xx/generic/profiles/devolo-dlan.mk new file mode 100644 index 0000000..741f5d5 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/devolo-dlan.mk @@ -0,0 +1,33 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/dLAN_pro_500_wp + NAME:=devolo dLAN pro 500 Wireless+ + PACKAGES:=open-plc-utils open-plc-utils-chkpib open-plc-utils-getpib open-plc-utils-modpib \ + open-plc-utils-setpib open-plc-utils-hpavkey open-plc-utils-amphost \ + open-plc-utils-plctool open-plc-utils-pibdump open-plc-utils-plcstat \ + ebtables hostapd-utils wifitoggle wpad +endef + +define Profile/dLAN_pro_500_wp/Description + Package set optimized for the devolo dLAN pro 500 Wireless+. +endef +$(eval $(call Profile,dLAN_pro_500_wp)) + +define Profile/dLAN_pro_1200_ac + NAME:=devolo dLAN pro 1200+ WiFi ac + PACKAGES:=open-plc-utils open-plc-utils-chkpib open-plc-utils-getpib open-plc-utils-modpib \ + open-plc-utils-setpib open-plc-utils-hpavkey open-plc-utils-plchost \ + open-plc-utils-plctool open-plc-utils-pibdump open-plc-utils-plcstat \ + ebtables hostapd-utils wifitoggle wpad ip-full kmod-ath10k kmod-leds-gpio \ + kmod-ledtrig-gpio +endef + +define Profile/dLAN_pro_1200_ac/Description + Package set optimized for the devolo dLAN pro 1200+ WiFi ac. +endef +$(eval $(call Profile,dLAN_pro_1200_ac)) diff --git a/target/linux/ar71xx/generic/profiles/dragino.mk b/target/linux/ar71xx/generic/profiles/dragino.mk new file mode 100644 index 0000000..ff222c1 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/dragino.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DRAGINO2 + NAME:=DRAGINO2 + PACKAGES:=kmod-ath9k kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DRAGINO2/Description + Package set optimized for the DRAGINO v2. +endef + +$(eval $(call Profile,DRAGINO2)) diff --git a/target/linux/ar71xx/generic/profiles/easylink.mk b/target/linux/ar71xx/generic/profiles/easylink.mk new file mode 100644 index 0000000..8d327b7 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/easylink.mk @@ -0,0 +1,29 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ELM150 + NAME:=EasyLink EL-M150 + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/ELM150/Description + Package set optimized for the EasyLink EL-M150. +endef +$(eval $(call Profile,ELM150)) + + +define Profile/ELMINI + NAME:=EasyLink EL-MINI + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/ELMINI/Description + Package set optimized for the EasyLink EL-MINI. +endef +$(eval $(call Profile,ELMINI)) diff --git a/target/linux/ar71xx/generic/profiles/engenius.mk b/target/linux/ar71xx/generic/profiles/engenius.mk new file mode 100644 index 0000000..7ea93e3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/engenius.mk @@ -0,0 +1,53 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/EAP300V2 + NAME:=EnGenius EAP300V2 + PACKAGES:= +endef + +define Profile/EAP300V2/Description + Package set optimized for the EnGenius EAP300V2. +endef + +$(eval $(call Profile,EAP300V2)) + + +define Profile/ESR900 + NAME:=EnGenius ESR900 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/ESR900/Description + Package set optimized for the EnGenius ESR900 +endef + +$(eval $(call Profile,ESR900)) + + +define Profile/ESR1750 + NAME:=EnGenius ESR1750 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage kmod-ath10k wpad-mini +endef + +define Profile/ESR1750/Description + Package set optimized for the EnGenius ESR1750 +endef + +$(eval $(call Profile,ESR1750)) + + +define Profile/EPG5000 + NAME:=EnGenius EPG5000 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage kmod-ath10k wpad-mini +endef + +define Profile/EPG5000/Description + Package set optimized for the EnGenius EPG5000 +endef + +$(eval $(call Profile,EPG5000)) diff --git a/target/linux/ar71xx/generic/profiles/ew.mk b/target/linux/ar71xx/generic/profiles/ew.mk new file mode 100644 index 0000000..b4e15e3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/ew.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/EWDORIN + NAME:=Embedded Wireless Dorin Platform + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev kmod-usb-storage \ + kmod-fs-vfat kmod-fs-msdos kmod-fs-ntfs kmod-fs-ext4 \ + kmod-nls-cp437 kmod-nls-cp850 kmod-nls-cp852 kmod-nls-iso8859-1 kmod-nls-utf8 +endef + +define Profile/EWDORIN/Description + Package set optimized for the Dorin Platform. +endef + +$(eval $(call Profile,EWDORIN)) + diff --git a/target/linux/ar71xx/generic/profiles/gl-connect.mk b/target/linux/ar71xx/generic/profiles/gl-connect.mk new file mode 100644 index 0000000..e9377db --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/gl-connect.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/GLINET + NAME:=GL.iNet + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/GLINET/Description + Package set optimized for the GL-Connect GL.iNet v1. +endef + +$(eval $(call Profile,GLINET)) diff --git a/target/linux/ar71xx/generic/profiles/gs-minibox-v1.mk b/target/linux/ar71xx/generic/profiles/gs-minibox-v1.mk new file mode 100644 index 0000000..1484114 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/gs-minibox-v1.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MINIBOXV1 + NAME:=Gainstrong MiniBox V1.0 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + + +define Profile/MINIBOXV1/Description + Package set optimized for the Gainstrong MiniBox V1.0 +endef +$(eval $(call Profile,MINIBOXV1)) diff --git a/target/linux/ar71xx/generic/profiles/hiwifi.mk b/target/linux/ar71xx/generic/profiles/hiwifi.mk new file mode 100644 index 0000000..5bd2476 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/hiwifi.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2012-2013 Hiwifi Wireless +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/HIWIFI_HC6361 + NAME:=HiWiFi HC6361 + PACKAGES:= kmod-usb-core kmod-usb2 kmod-usb-storage \ + kmod-crypto-deflate kmod-fs-ext4 kmod-ledtrig-gpio \ + kmod-nls-iso8859-1 e2fsprogs +endef + +define Profile/HIWIFI_HC6361/description + Package set optimized for the HiWiFi HC6361. +endef +$(eval $(call Profile,HIWIFI_HC6361)) diff --git a/target/linux/ar71xx/generic/profiles/jjplus.mk b/target/linux/ar71xx/generic/profiles/jjplus.mk new file mode 100644 index 0000000..3f97dbf --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/jjplus.mk @@ -0,0 +1,39 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/JA76PF + NAME:=jjPlus JA76PF + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-hwmon-core kmod-i2c-core kmod-hwmon-lm75 +endef + +define Profile/JA76PF/Description + Package set optimized for the jjPlus JA76PF board. +endef + +$(eval $(call Profile,JA76PF)) + +define Profile/JA76PF2 + NAME:=jjPlus JA76PF2 + PACKAGES:= +endef + +define Profile/JA76PF2/Description + Package set optimized for the jjPlus JA76PF2 board. +endef + +$(eval $(call Profile,JA76PF2)) + +define Profile/JWAP003 + NAME:=jjPlus JWAP0003 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/JWAP003/Description + Package set optimized for the jjPlus JWAP003 board. +endef + +$(eval $(call Profile,JWAP003)) diff --git a/target/linux/ar71xx/generic/profiles/linksys.mk b/target/linux/ar71xx/generic/profiles/linksys.mk new file mode 100644 index 0000000..bedf3a3 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/linksys.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WRT160NL + NAME:=Linksys WRT160NL + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/WRT160NL/Description + Package set optimized for the Linksys WRT160NL. +endef + +define Profile/WRT400N + NAME:=Linksys WRT400N + PACKAGES:= +endef + +define Profile/WRT400N/Description + Package set optimized for the Linksys WRT400N. +endef + +$(eval $(call Profile,WRT160NL)) +$(eval $(call Profile,WRT400N)) diff --git a/target/linux/ar71xx/generic/profiles/meraki.mk b/target/linux/ar71xx/generic/profiles/meraki.mk new file mode 100644 index 0000000..0d5cda0 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/meraki.mk @@ -0,0 +1,27 @@ +# +# Copyright (C) 2014-2015 Chris Blake (chrisrblake93@gmail.com) +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MR12 + NAME:=Meraki MR12 + PACKAGES:=kmod-spi-gpio kmod-ath9k +endef + +define Profile/MR12/description + Package set optimized for the Cisco Meraki MR12 Access Point. +endef + +define Profile/MR16 + NAME:=Meraki MR16 + PACKAGES:=kmod-spi-gpio kmod-ath9k +endef + +define Profile/MR16/description + Package set optimized for the Cisco Meraki MR16 Access Point. +endef + +$(eval $(call Profile,MR12)) +$(eval $(call Profile,MR16)) \ No newline at end of file diff --git a/target/linux/ar71xx/generic/profiles/mercury.mk b/target/linux/ar71xx/generic/profiles/mercury.mk new file mode 100644 index 0000000..e66d70d --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/mercury.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + + +define Profile/MAC1200R + NAME:=MERCURY MAC1200R + PACKAGES:=kmod-ath10k +endef + +define Profile/MAC1200R/Description + Package set optimized for the MERCURY MAC1200R. +endef +$(eval $(call Profile,MAC1200R)) diff --git a/target/linux/ar71xx/generic/profiles/nclink.mk b/target/linux/ar71xx/generic/profiles/nclink.mk new file mode 100644 index 0000000..04eb9ec --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/nclink.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/SMART-300 + NAME:=NC-LINK SMART-300 +endef + +define Profile/SMART-300/Description + Package set optimized for the NC-LINK SMART-300. +endef +$(eval $(call Profile,SMART-300)) diff --git a/target/linux/ar71xx/generic/profiles/netgear.mk b/target/linux/ar71xx/generic/profiles/netgear.mk new file mode 100644 index 0000000..16b1087 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/netgear.mk @@ -0,0 +1,84 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WNDAP360 + NAME:=NETGEAR WNDAP360 + PACKAGES:= +endef + +define Profile/WNDAP360/Description + Package set optimized for the NETGEAR WNDAP360 +endef + +$(eval $(call Profile,WNDAP360)) + +define Profile/WNDR3700 + NAME:=NETGEAR WNDR3700/WNDR3800/WNDRMAC + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev kmod-leds-wndr3700-usb +endef + +define Profile/WNDR3700/Description + Package set optimized for the NETGEAR WNDR3700/WNDR3800/WNDRMAC +endef + +$(eval $(call Profile,WNDR3700)) + + +define Profile/WNR2000V3 + NAME:=NETGEAR WNR2000V3 +endef + +define Profile/WNR2000V3/Description + Package set optimized for the NETGEAR WNR2000V3 +endef + +$(eval $(call Profile,WNR2000V3)) + + +define Profile/WNR2000V4 + NAME:=NETGEAR WNR2000V4 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WNR2000V4/Description + Package set optimized for the NETGEAR WNR2000V4 +endef + +$(eval $(call Profile,WNR2000V4)) + + +define Profile/WNR612V2 + NAME:=NETGEAR WNR612V2 / On Networks N150 +endef + +define Profile/WNR612V2/Description + Package set optimized for the NETGEAR WNR612V2 / On Networks N150 +endef + +$(eval $(call Profile,WNR612V2)) + + +define Profile/WNR1000V2 + NAME:=NETGEAR WNR1000V2 +endef + +define Profile/WNR1000V2/Description + Package set optimized for the NETGEAR WNR1000V2 +endef + +$(eval $(call Profile,WNR1000V2)) + + +define Profile/WNR2200 + NAME:=NETGEAR WNR2200 +endef + +define Profile/WNR2200/Description + Package set optimized for the NETGEAR WNR2200 +endef + +$(eval $(call Profile,WNR2200)) diff --git a/target/linux/ar71xx/generic/profiles/onion.mk b/target/linux/ar71xx/generic/profiles/onion.mk new file mode 100644 index 0000000..dd5874e --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/onion.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OMEGA + NAME:=Onion Omega + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb-storage kmod-i2c-core kmod-i2c-gpio-custom kmod-spi-bitbang kmod-spi-dev kmod-spi-gpio kmod-spi-gpio-custom kmod-usb-serial +endef + +define Profile/OMEGA/Description + Package set optimized for the Onion Omega development platform. +endef +$(eval $(call Profile,OMEGA)) diff --git a/target/linux/ar71xx/generic/profiles/oolite.mk b/target/linux/ar71xx/generic/profiles/oolite.mk new file mode 100644 index 0000000..448f08d --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/oolite.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OOLITE + NAME:=OOLITE + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + + +define Profile/OOLITE/Description + Package set optimized for the OOLITE. +endef +$(eval $(call Profile,OOLITE)) + diff --git a/target/linux/ar71xx/generic/profiles/openmesh.mk b/target/linux/ar71xx/generic/profiles/openmesh.mk new file mode 100644 index 0000000..1c51e93 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/openmesh.mk @@ -0,0 +1,73 @@ +# +# Copyright (C) 2011-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OM2P + NAME:=OpenMesh OM2P/OM2Pv2/OM2P-HS/OM2P-HSv2/OM2P-LC + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/OM2P/Description + Package set optimized for the OpenMesh OM2P/OM2Pv2/OM2P-HS/OM2P-HSv2/OM2P-LC. +endef + +$(eval $(call Profile,OM2P)) + +define Profile/OM5P + NAME:=OpenMesh OM5P/OM5P-AN + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/OM5P/Description + Package set optimized for the OpenMesh OM5P/OM5P-AN. +endef + +$(eval $(call Profile,OM5P)) + +define Profile/MR600 + NAME:=OpenMesh MR600 + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/MR600/Description + Package set optimized for the OpenMesh MR600. +endef + +$(eval $(call Profile,MR600)) + +define Profile/MR900 + NAME:=OpenMesh MR900/MR900v2 + PACKAGES:=kmod-ath9k om-watchdog +endef + +define Profile/MR900/Description + Package set optimized for the OpenMesh MR900/MR900v2. +endef + +$(eval $(call Profile,MR900)) + +define Profile/MR1750 + NAME:=OpenMesh MR1750 + PACKAGES:=kmod-ath9k kmod-ath10k +endef + +define Profile/MR1750/Description + Package set optimized for the OpenMesh MR1750. +endef + +$(eval $(call Profile,MR1750)) + +define Profile/OPENMESH + NAME:=OpenMesh products + PACKAGES:=kmod-ath9k kmod-ath10k om-watchdog +endef + +define Profile/OPENMESH/Description + Build images for all OpenMesh products. +endef + +$(eval $(call Profile,OPENMESH)) + diff --git a/target/linux/ar71xx/generic/profiles/pcs.mk b/target/linux/ar71xx/generic/profiles/pcs.mk new file mode 100644 index 0000000..1399ef4 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/pcs.mk @@ -0,0 +1,29 @@ +# +# Copyright (C) 2009 OpenWrt.org +# Copyright (C) 2012 PowerCloud Systems +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/UBDEV01 + NAME:=PowerCloud Systems ubdev01 model + PACKAGES:= +endef + +define Profile/UBDEV01/Description + Package set optimized for the PowerCloud Systems ubdev01 board. +endef + +$(eval $(call Profile,UBDEV01)) + +define Profile/DLRTDEV01 + NAME:=PowerCloud Systems dlrtdev01 model + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/DLRTDEV01/Description + Package set optimized for the PowerCloud Systems dlrtdev01 board. +endef + +$(eval $(call Profile,DLRTDEV01)) diff --git a/target/linux/ar71xx/generic/profiles/planex.mk b/target/linux/ar71xx/generic/profiles/planex.mk new file mode 100644 index 0000000..3d192ba --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/planex.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MZKW04NU + NAME:=Planex MZK-W04NU + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/MZKW04NU/Description + Package set optimized for the Planex MZK-W04NU. +endef + +$(eval $(call Profile,MZKW04NU)) + +define Profile/MZKW300NH + NAME:=Planex MZK-W300NH + PACKAGES:= +endef + +define Profile/MZKW300NH/Description + Package set optimized for the Planex MZK-W300NH. +endef + +$(eval $(call Profile,MZKW300NH)) diff --git a/target/linux/ar71xx/generic/profiles/qihoo.mk b/target/linux/ar71xx/generic/profiles/qihoo.mk new file mode 100644 index 0000000..0ec778a --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/qihoo.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/QIHOO360 + NAME:=Qihoo 360 C301 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev kmod-ath10k +endef + +define Profile/QIHOO360/Description + Package set optimized for the Qihoo 360 C301 device. +endef +$(eval $(call Profile,QIHOO360)) diff --git a/target/linux/ar71xx/generic/profiles/redwave.mk b/target/linux/ar71xx/generic/profiles/redwave.mk new file mode 100644 index 0000000..069dd8f --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/redwave.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RW2458N + NAME:=Redwave RW2458N + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-ath9k wpad-mini +endef + +define Profile/RW2458N/Description + Package set optimized for the Redwave RW2458N board. +endef + +$(eval $(call Profile,RW2458N)) diff --git a/target/linux/ar71xx/generic/profiles/rosewill.mk b/target/linux/ar71xx/generic/profiles/rosewill.mk new file mode 100644 index 0000000..00c1d7d --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/rosewill.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RNXN360RT + NAME:=Rosewill RNX-N360RT + PACKAGES:= +endef + +define Profile/RNXN360RT/Description + Package set optimized for the Rosewill RNX-N360RT. +endef +$(eval $(call Profile,RNXN360RT)) diff --git a/target/linux/ar71xx/generic/profiles/senao.mk b/target/linux/ar71xx/generic/profiles/senao.mk new file mode 100644 index 0000000..20a79e9 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/senao.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CAP4200AG + NAME:=Senao CAP4200AG + PACKAGES:=kmod-ath9k +endef + +define Profile/CAP4200AG/Description + Package set optimized for the Senao CAP4200AG. +endef + +$(eval $(call Profile,CAP4200AG)) diff --git a/target/linux/ar71xx/generic/profiles/sitecom.mk b/target/linux/ar71xx/generic/profiles/sitecom.mk new file mode 100644 index 0000000..3dd8e43 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/sitecom.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +define Profile/WLR8100 + NAME:=Sitecom WLR-8100 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev kmod-usb3 +endef + +define Profile/WLR8100/Description + Package set optimized for the Sitecom WLR-8100 +endef + +$(eval $(call Profile,WLR8100)) diff --git a/target/linux/ar71xx/generic/profiles/smartelectronics.mk b/target/linux/ar71xx/generic/profiles/smartelectronics.mk new file mode 100644 index 0000000..6d3dc8c --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/smartelectronics.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/BSB + NAME:=Smart Electronics Black Swift board + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/BSB/Description + Package set optimized for the Smart Electronics Black Swift board. +endef + +$(eval $(call Profile,BSB)) diff --git a/target/linux/ar71xx/generic/profiles/tp-link.mk b/target/linux/ar71xx/generic/profiles/tp-link.mk new file mode 100644 index 0000000..2875290 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/tp-link.mk @@ -0,0 +1,409 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ARCHERC7 + NAME:=TP-LINK Archer C5/C7 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev kmod-ath10k +endef + +define Profile/ARCHERC7/Description + Package set optimized for the TP-LINK Archer C5/C7. +endef +$(eval $(call Profile,ARCHERC7)) + + +define Profile/CPE510 + NAME:=TP-LINK CPE210/220/510/520 + PACKAGES:=rssileds +endef + +define Profile/CPE510/Description + Package set optimized for the TP-LINK CPE210/220/510/520. +endef +$(eval $(call Profile,CPE510)) + + +define Profile/TLMR10U + NAME:=TP-LINK TL-MR10U + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/TLMR10U/Description + Package set optimized for the TP-LINK TL-MR10U. +endef +$(eval $(call Profile,TLMR10U)) + + +define Profile/TLMR11U + NAME:=TP-LINK TL-MR11U + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR11U/Description + Package set optimized for the TP-LINK TL-MR11U. +endef +$(eval $(call Profile,TLMR11U)) + +define Profile/TLMR12U + NAME:=TP-LINK TL-MR12U + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR12U/Description + Package set optimized for the TP-LINK TL-MR12U. +endef + +$(eval $(call Profile,TLMR12U)) + +define Profile/TLMR13U + NAME:=TP-LINK TL-MR13U + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR13U/Description + Package set optimized for the TP-LINK TL-MR13U. +endef +$(eval $(call Profile,TLMR13U)) + + +define Profile/TLMR3020 + NAME:=TP-LINK TL-MR3020 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3020/Description + Package set optimized for the TP-LINK TL-MR3020. +endef +$(eval $(call Profile,TLMR3020)) + + +define Profile/TLMR3040 + NAME:=TP-LINK TL-MR3040 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3040/Description + Package set optimized for the TP-LINK TL-MR3040. +endef +$(eval $(call Profile,TLMR3040)) + + +define Profile/TLMR3220 + NAME:=TP-LINK TL-MR3220 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3220/Description + Package set optimized for the TP-LINK TL-MR3220. +endef +$(eval $(call Profile,TLMR3220)) + + +define Profile/TLMR3420 + NAME:=TP-LINK TL-MR3420 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLMR3420/Description + Package set optimized for the TP-LINK TL-MR3420. +endef +$(eval $(call Profile,TLMR3420)) + + +define Profile/TLWR703 + NAME:=TP-LINK TL-WR703N + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/TLWR703/Description + Package set optimized for the TP-LINK TL-WR703N. +endef +$(eval $(call Profile,TLWR703)) + + +define Profile/TLWR710 + NAME:=TP-LINK TL-WR710N + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/TLWR710/Description + Package set optimized for the TP-LINK TL-WR710N. +endef +$(eval $(call Profile,TLWR710)) + + +define Profile/TLWR720 + NAME:=TP-LINK TL-WR720N + PACKAGES:=kmod-usb-core kmod-usb2 +endef + + +define Profile/TLWR720/Description + Package set optimized for the TP-LINK TL-WR720N. +endef +$(eval $(call Profile,TLWR720)) + + +define Profile/TLWA701 + NAME:=TP-LINK TL-WA701N/ND + PACKAGES:= +endef + +define Profile/TLWA701/Description + Package set optimized for the TP-LINK TL-WA701N/ND. +endef +$(eval $(call Profile,TLWA701)) + +define Profile/TLWA7210 + NAME:=TP-LINK TL-WA7210N + PACKAGES:=rssileds kmod-ledtrig-netdev +endef + +define Profile/TLWA7210/Description + Package set optimized for the TP-LINK TL-WA7210N. +endef +$(eval $(call Profile,TLWA7210)) + +define Profile/TLWA730RE + NAME:=TP-LINK TL-WA730RE + PACKAGES:= +endef + +define Profile/TLWA730RE/Description + Package set optimized for the TP-LINK TL-WA730RE. +endef +$(eval $(call Profile,TLWA730RE)) + +define Profile/TLWA750 + NAME:=TP-LINK TL-WA750RE + PACKAGES:=rssileds +endef + +define Profile/TLWA750/Description + Package set optimized for the TP-LINK TL-WA750RE. +endef +$(eval $(call Profile,TLWA750)) + + +define Profile/TLWA7510 + NAME:=TP-LINK TL-WA7510N + PACKAGES:= +endef + +define Profile/TLWA7510/Description + Package set optimized for the TP-LINK TL-WA7510N. +endef +$(eval $(call Profile,TLWA7510)) + +define Profile/TLWA801 + NAME:=TP-LINK TL-WA801N/ND + PACKAGES:= +endef + +define Profile/TLWA801/Description + Package set optimized for the TP-LINK TL-WA801N/ND. +endef +$(eval $(call Profile,TLWA801)) + +define Profile/TLWA830 + NAME:=TP-LINK TL-WA830RE + PACKAGES:= +endef + +define Profile/TLWA830/Description + Package set optimized for the TP-LINK TL-WA830RE. +endef +$(eval $(call Profile,TLWA830)) + + +define Profile/TLWA850 + NAME:=TP-LINK TL-WA850RE + PACKAGES:=rssileds +endef + +define Profile/TLWA850/Description + Package set optimized for the TP-LINK TL-WA850RE. +endef +$(eval $(call Profile,TLWA850)) + + +define Profile/TLWA860 + NAME:=TP-LINK TL-WA860RE + PACKAGES:= +endef + +define Profile/TLWA860/Description + Package set optimized for the TP-LINK TL-WA860RE. +endef +$(eval $(call Profile,TLWA860)) + + +define Profile/TLWA901 + NAME:=TP-LINK TL-WA901N/ND + PACKAGES:= +endef + +define Profile/TLWA901/Description + Package set optimized for the TP-LINK TL-WA901N/ND. +endef +$(eval $(call Profile,TLWA901)) + + +define Profile/TLWDR4300 + NAME:=TP-LINK TL-WDR3500/3600/4300/4310/MW4350R + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWDR4300/Description + Package set optimized for the TP-LINK TL-WDR3500/3600/4300/4310/MW4350R. +endef +$(eval $(call Profile,TLWDR4300)) + + +define Profile/TLWDR3320V2 + NAME:=TP-LINK TL-WDR3320v2 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWDR3320V2/Description + Package set optimized for the TP-LINK TL-WDR3320v2. +endef +$(eval $(call Profile,TLWDR3320V2)) + + +define Profile/TLWDR4900V2 + NAME:=TP-LINK TL-WDR4900v2 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWDR4900V2/Description + Package set optimized for the TP-LINK TL-WDR4900v2. +endef +$(eval $(call Profile,TLWDR4900V2)) + + +define Profile/TLWDR6500V2 + NAME:=TP-LINK TL-WDR6500v2 + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev kmod-ath10k +endef + +define Profile/TLWDR6500V2/Description + Package set optimized for the TP-LINK TL-WDR6500v2. +endef +$(eval $(call Profile,TLWDR6500V2)) + + +define Profile/TLWR740 + NAME:=TP-LINK TL-WR740N/ND + PACKAGES:= +endef + +define Profile/TLWR740/Description + Package set optimized for the TP-LINK TL-WR740N/ND. +endef +$(eval $(call Profile,TLWR740)) + + +define Profile/TLWR741 + NAME:=TP-LINK TL-WR741N/ND + PACKAGES:= +endef + +define Profile/TLWR741/Description + Package set optimized for the TP-LINK TL-WR741N/ND. +endef +$(eval $(call Profile,TLWR741)) + + +define Profile/TLWR743 + NAME:=TP-LINK TL-WR743N/ND + PACKAGES:= +endef + +define Profile/TLWR743/Description + Package set optimized for the TP-LINK TL-WR743N/ND. +endef +$(eval $(call Profile,TLWR743)) + + +define Profile/TLWR841 + NAME:=TP-LINK TL-WR841N/ND + PACKAGES:= +endef + +define Profile/TLWR841/Description + Package set optimized for the TP-LINK TL-WR841N/ND. +endef +$(eval $(call Profile,TLWR841)) + + +define Profile/TLWR842 + NAME:=TP-LINK TL-WR842N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR842/Description + Package set optimized for the TP-LINK TL-WR842N/ND. +endef +$(eval $(call Profile,TLWR842)) + + +define Profile/TLWR843 + NAME:=TP-LINK TL-WR843N/ND + PACKAGES:= +endef + +define Profile/TLWR843/Description + Package set optimized for the TP-LINK TL-WR843N/ND. +endef +$(eval $(call Profile,TLWR843)) + + +define Profile/TLWR941 + NAME:=TP-LINK TL-WR941N/ND + PACKAGES:= +endef + +define Profile/TLWR941/Description + Package set optimized for the TP-LINK TL-WR941N/ND. +endef +$(eval $(call Profile,TLWR941)) + + +define Profile/TLWR1041 + NAME:=TP-LINK TL-WR1041N + PACKAGES:= +endef + +define Profile/TLWR1041/Description + Package set optimized for the TP-LINK TL-WR1041N/ND. +endef +$(eval $(call Profile,TLWR1041)) + + +define Profile/TLWR1043 + NAME:=TP-LINK TL-WR1043N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR1043/Description + Package set optimized for the TP-LINK TL-WR1043N/ND. +endef +$(eval $(call Profile,TLWR1043)) + + +define Profile/TLWR2543 + NAME:=TP-LINK TL-WR2543N/ND + PACKAGES:=kmod-usb-core kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/TLWR2543/Description + Package set optimized for the TP-LINK TL-WR2543N/ND. +endef +$(eval $(call Profile,TLWR2543)) diff --git a/target/linux/ar71xx/generic/profiles/trendnet.mk b/target/linux/ar71xx/generic/profiles/trendnet.mk new file mode 100644 index 0000000..42d05b6 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/trendnet.mk @@ -0,0 +1,62 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/TEW632BRP + NAME:=TRENDNet TEW-632BRP + PACKAGES:= +endef + +define Profile/TEW632BRP/Description + Package set optimized for the TRENDNet TEW-632BRP. +endef + +$(eval $(call Profile,TEW632BRP)) + +define Profile/TEW652BRP + NAME:=TRENDNet TEW-652BRP + PACKAGES:= +endef + +define Profile/TEW652BRP/Description + Package set optimized for the TRENDNet TEW-652BRP. +endef + +$(eval $(call Profile,TEW652BRP)) + +define Profile/TEW673GRU + NAME:=TRENDNet TEW-673GRU + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/TEW673GRU/Description + Package set optimized for the TRENDNet TEW-673GRU. +endef + +$(eval $(call Profile,TEW673GRU)) + +define Profile/TEW712BR + NAME:=TRENDNet TEW-712BR + PACKAGES:= +endef + +define Profile/TEW712BR/Description + Package set optimized for the TRENDNet TEW-712BR. +endef + +$(eval $(call Profile,TEW712BR)) + + +define Profile/TEW732BR + NAME:=TRENDNet TEW-732BR + PACKAGES:= +endef + +define Profile/TEW732BR/Description + Package set optimized for the TRENDNet TEW-732BR. +endef + +$(eval $(call Profile,TEW732BR)) diff --git a/target/linux/ar71xx/generic/profiles/ubnt.mk b/target/linux/ar71xx/generic/profiles/ubnt.mk new file mode 100644 index 0000000..d8e24d0 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/ubnt.mk @@ -0,0 +1,73 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/UBNTRS + NAME:=Ubiquiti RouterStation + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNTRS/Description + Package set optimized for the Ubiquiti RouterStation. +endef + +$(eval $(call Profile,UBNTRS)) + +define Profile/UBNTRSPRO + NAME:=Ubiquiti RouterStation Pro + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNTRSPRO/Description + Package set optimized for the Ubiquiti RouterStation Pro. +endef + +$(eval $(call Profile,UBNTRSPRO)) + +define Profile/UBNTUNIFI + NAME:=Ubiquiti UniFi AP + PACKAGES:= +endef + +define Profile/UBNTUNIFI/Description + Package set optimized for the Ubiquiti UniFi AP. +endef + +$(eval $(call Profile,UBNTUNIFI)) + +define Profile/UBNTUNIFIOUTDOOR + NAME:=Ubiquiti UniFiAP Outdoor + PACKAGES:= +endef + +define Profile/UBNTUNIFIOUTDOOR/Description + Package set optimized for the Ubiquiti UniFiAP Outdoor. +endef + +$(eval $(call Profile,UBNTUNIFIOUTDOOR)) + +define Profile/UAPPRO + NAME:=Ubiquiti UniFi AP Pro + PACKAGES:= +endef + +define Profile/UAPPRO/Description + Package set optimized for the Ubiquiti UniFi AP Pro. +endef + +$(eval $(call Profile,UAPPRO)) + + +define Profile/UBNT + NAME:=Ubiquiti Products + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 +endef + +define Profile/UBNT/Description + Build images for all Ubiquiti products (including LS-SR71, RouterStation and RouterStation Pro) +endef + +$(eval $(call Profile,UBNT)) diff --git a/target/linux/ar71xx/generic/profiles/wd.mk b/target/linux/ar71xx/generic/profiles/wd.mk new file mode 100644 index 0000000..b8cb99b --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/wd.mk @@ -0,0 +1,36 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MYNETN600 + NAME:=WD My Net N600 + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/MYNETN600/Description + Package set optimized for the WD My Net N600 device. +endef +$(eval $(call Profile,MYNETN600)) + +define Profile/MYNETN750 + NAME:=WD My Net N750 + PACKAGES:=kmod-usb-core kmod-usb2 +endef +define Profile/MYNETN750/Description + Package set optimized for the WD My Net N750 device. +endef + +$(eval $(call Profile,MYNETN750)) + +define Profile/MYNETREXT + NAME:=WD My Net Wi-Fi Range Extender + PACKAGES:=rssileds +endef + +define Profile/MYNETREXT/Description + Package set optimized for the WD My Net Wi-Fi Range Extender device. +endef +$(eval $(call Profile,MYNETREXT)) diff --git a/target/linux/ar71xx/generic/profiles/weio.mk b/target/linux/ar71xx/generic/profiles/weio.mk new file mode 100644 index 0000000..227cec9 --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/weio.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WEIO + NAME:=WeIO + PACKAGES:=kmod-usb-core kmod-usb2 +endef + +define Profile/WEIO/Description + Package set optimized for the WeIO board. +endef + +$(eval $(call Profile,WEIO)) diff --git a/target/linux/ar71xx/generic/profiles/zcomax.mk b/target/linux/ar71xx/generic/profiles/zcomax.mk new file mode 100644 index 0000000..b9ab77e --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/zcomax.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/ZCN1523H28 + NAME:=Zcomax ZCN-1523H-2-8 + PACKAGES:= +endef + +define Profile/ZCN1523H28/Description + Package set optimized for the Zcomax ZCN-1523H-2-8 board. +endef + +$(eval $(call Profile,ZCN1523H28)) + +define Profile/ZCN1523H516 + NAME:=Zcomax ZCN-1523H-5-16 + PACKAGES:= +endef + +define Profile/ZCN1523H516/Description + Package set optimized for the Zcomax ZCN-1523H-5-16 board. +endef + +$(eval $(call Profile,ZCN1523H516)) diff --git a/target/linux/ar71xx/generic/profiles/zyxel.mk b/target/linux/ar71xx/generic/profiles/zyxel.mk new file mode 100644 index 0000000..66258bd --- /dev/null +++ b/target/linux/ar71xx/generic/profiles/zyxel.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/NBG_460N_550N_550NH + NAME:=Zyxel NBG 460N/550N/550NH + PACKAGES:=kmod-rtc-pcf8563 +endef + +define Profile/NBG_460N_550N_550NH/Description + Package set optimized for the Zyxel NBG 460N/550N/550NH Routers. +endef + +$(eval $(call Profile,NBG_460N_550N_550NH)) diff --git a/target/linux/ar71xx/generic/target.mk b/target/linux/ar71xx/generic/target.mk new file mode 100644 index 0000000..64eb205 --- /dev/null +++ b/target/linux/ar71xx/generic/target.mk @@ -0,0 +1,8 @@ +BOARDNAME:=Generic +FEATURES += squashfs + +define Target/Description + Build firmware images for generic Atheros AR71xx/AR913x/AR934x based boards. +endef + + diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile new file mode 100644 index 0000000..7bf2f27 --- /dev/null +++ b/target/linux/ar71xx/image/Makefile @@ -0,0 +1,2397 @@ +# +# Copyright (C) 2008-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +JFFS2_BLOCKSIZE = 64k 128k 256k + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +IMAGE_PROFILE:=$(if $(PROFILE),$(PROFILE),Default) + +KERNEL_LOADADDR = 0x80060000 + +DEVICE_VARS += NETGEAR_KERNEL_MAGIC NETGEAR_BOARD_ID NETGEAR_HW_ID CMDLINE CONSOLE IMAGE_SIZE BOARDNAME LOADER_FLASH_OFFS + +define Build/netgear-squashfs + rm -rf $@.fs $@.squashfs + mkdir -p $@.fs/image + cp $@ $@.fs/image/uImage + $(STAGING_DIR_HOST)/bin/mksquashfs-lzma \ + $@.fs $@.squashfs \ + -noappend -root-owned -be -b 65536 + dd if=/dev/zero bs=1k count=1 >> $@.squashfs + mkimage \ + -A mips -O linux -T filesystem -C none \ + -M $(NETGEAR_KERNEL_MAGIC) \ + -a 0xbf070000 -e 0xbf070000 \ + -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $@.squashfs $@ + rm -rf $@.squashfs $@.fs +endef + +define Build/netgear-uImage + $(call Build/uImage,$(1) -M $(NETGEAR_KERNEL_MAGIC)) +endef + +# combine kernel and rootfs into one image +# mktplinkfw +# is "sysupgrade" or "factory" +# +# -a align the rootfs start on an bytes boundary +# -j add jffs2 end-of-filesystem markers +# -s strip padding from end of the image +# -X reserve bytes in the firmware image (hexval prefixed with 0x) +define Build/mktplinkfw + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -F $(TPLINK_FLASHLAYOUT) -N OpenWrt -V $(REVISION) $2 \ + -m $(TPLINK_HEADER_VERSION) \ + -k $(word 1,$^) \ + -r $@ \ + -o $@.new \ + -j -X 0x40000 \ + -a $(call rootfs_align,$(FILESYSTEM)) \ + $(if $(findstring sysupgrade,$1),-s) && mv $@.new $@ || rm -f $@ +endef + +# mktplinkfw-initramfs +# +# -c combined image +define Build/mktplinkfw-initramfs + $(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -F $(TPLINK_FLASHLAYOUT) -N OpenWrt -V $(REVISION) $2 \ + -m $(TPLINK_HEADER_VERSION) \ + -k $@ \ + -o $@.new \ + -s -S \ + -c + @mv $@.new $@ +endef + +define Build/loader-common + rm -rf $@.src + $(MAKE) -C lzma-loader \ + PKG_BUILD_DIR="$@.src" \ + TARGET_DIR="$(dir $@)" LOADER_NAME="$(notdir $@)" \ + KERNEL_CMDLINE="$(CMDLINE)" BOARD="$(BOARDNAME)" \ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + $(1) compile loader.gz + mv "$@.gz" "$@" + rm -rf $@.src +endef + +define Build/loader-okli-compile + $(call Build/loader-common,FLASH_OFFS=$(LOADER_FLASH_OFFS) FLASH_MAX=0) +endef + +define Build/loader-kernel + $(call Build/loader-common,LOADER_DATA="$@") +endef + +define Build/loader-okli + dd if=$(KDIR)/loader-$(1).gz bs=7680 conv=sync of="$@.new" + cat "$@" >> "$@.new" + mv "$@.new" "$@" +endef + +define Build/copy-file + cat "$(1)" > "$@" +endef + +DEVICE_VARS += TPLINK_HWID TPLINK_HWREV TPLINK_FLASHLAYOUT TPLINK_HEADER_VERSION + +# UBNT_BOARD e.g. one of (XS2, XS5, RS, XM) +# UBNT_TYPE e.g. one of (BZ, XM, XW) +# UBNT_CHIP e.g. one of (ar7240, ar933x, ar934x) + +# mkubntimage is using the kernel image direct +# routerboard creates partitions out of the ubnt header +define Build/mkubntimage + $(STAGING_DIR_HOST)/bin/mkfwimage \ + -B $(UBNT_BOARD) -v $(UBNT_TYPE).$(UBNT_CHIP).v6.0.0-OpenWrt-$(REVISION) \ + -k $(word 1,$^) \ + -r $@ \ + -o $@ +endef + +# all UBNT XM device expect the kernel image to have 1024k while flash, when +# booting the image, the size doesn't matter. +define Build/mkubntimage-split + dd if=$@ of=$@.old1 bs=1024k count=1 + dd if=$@ of=$@.old2 bs=1024k skip=1 + $(STAGING_DIR_HOST)/bin/mkfwimage \ + -B $(UBNT_BOARD) -v $(UBNT_TYPE).$(UBNT_CHIP).v6.0.0-OpenWrt-$(REVISION) \ + -k $@.old1 \ + -r $@.old2 \ + -o $@ + rm $@.old1 $@.old2 +endef + +define Build/mkubntimage2 + $(STAGING_DIR_HOST)/bin/mkfwimage2 -f 0x9f000000 \ + -v $(UBNT_TYPE).$(UBNT_CHIP).v6.0.0-OpenWrt-$(REVISION) \ + -p jffs2:0x50000:0xf60000:0:0:$@ \ + -o $@.new + @mv $@.new $@ +endef + +DEVICE_VARS += UBNT_BOARD UBNT_CHIP UBNT_TYPE + +define Build/mkubntkernelimage + rm -rf $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image && \ + mkdir -p $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image && \ + cp $@ $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image/kernel0 && \ + $(STAGING_DIR_HOST)/bin/mkfs.jffs2 \ + --pad --big-endian --squash-uids -v -e 64KiB \ + -o $@.new \ + -d $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image \ + 2>&1 && \ + $(STAGING_DIR_HOST)/bin/padjffs2 $@.new -J 64 + -rm -rf $(KDIR_TMP)/ubnt-$(KERNEL_IMAGE)/image + @mv $@.new $@ +endef + +define Device/Default + BOARDNAME := + DEVICE_PROFILE = $$(BOARDNAME) + PROFILES = Default Minimal $$(DEVICE_PROFILE) + MTDPARTS := + IMAGES := sysupgrade.bin + BLOCKSIZE := 64k + FILESYSTEMS = $(filter-out jffs2-%,$(TARGET_FILESYSTEMS)) jffs2-$$(BLOCKSIZE) + CONSOLE = ttyS0,115200 + CMDLINE = $$(if $$(BOARDNAME),board=$$(BOARDNAME)) $$(if $$(MTDPARTS),mtdparts=$$(MTDPARTS)) $$(if $$(CONSOLE),console=$$(CONSOLE)) + KERNEL := kernel-bin | patch-cmdline | lzma | uImage lzma + COMPILE := + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin = append-kernel $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) +endef + +define Device/bsb + BOARDNAME = BSB + IMAGE_SIZE = 16000k + CONSOLE = ttyATH0,115200 + MTDPARTS = spi0.0:128k(u-boot)ro,64k(u-boot-env)ro,16128k(firmware),64k(art)ro +endef +TARGET_DEVICES += bsb + +define Device/carambola2 + BOARDNAME = CARAMBOLA2 + IMAGE_SIZE = 16000k + CONSOLE = ttyATH0,115200 + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,16000k(firmware),64k(art)ro +endef +TARGET_DEVICES += carambola2 + +define Device/cf-e316n-v2 + BOARDNAME = CF-E316N-V2 + IMAGE_SIZE = 16192k + CONSOLE = ttyS0,115200 + MTDPARTS = spi0.0:64k(u-boot)ro,64k(art)ro,16192k(firmware),64k(nvram)ro +endef +TARGET_DEVICES += cf-e316n-v2 + +define Device/weio + BOARDNAME = WEIO + IMAGE_SIZE = 16000k + CONSOLE = ttyATH0,115200 + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,16000k(firmware),64k(art)ro +endef +TARGET_DEVICES += weio + +define Device/wndr3700 + BOARDNAME = WNDR3700 + NETGEAR_KERNEL_MAGIC = 0x33373030 + NETGEAR_BOARD_ID = WNDR3700 + IMAGE_SIZE = 7680k + MTDPARTS = spi0.0:320k(u-boot)ro,128k(u-boot-env)ro,7680k(firmware),64k(art)ro + IMAGES := sysupgrade.bin factory.img factory-NA.img + KERNEL := kernel-bin | patch-cmdline | lzma -d20 | netgear-uImage lzma + IMAGE/default = append-kernel $$$$(BLOCKSIZE) | netgear-squashfs | append-rootfs | pad-rootfs + IMAGE/sysupgrade.bin = $$(IMAGE/default) | check-size $$$$(IMAGE_SIZE) + IMAGE/factory.img = $$(IMAGE/default) | netgear-dni | check-size $$$$(IMAGE_SIZE) + IMAGE/factory-NA.img = $$(IMAGE/default) | netgear-dni NA | check-size $$$$(IMAGE_SIZE) +endef + +define Device/wndr3700v2 +$(Device/wndr3700) + NETGEAR_BOARD_ID = WNDR3700v2 + NETGEAR_KERNEL_MAGIC = 0x33373031 + NETGEAR_HW_ID = 29763654+16+64 + IMAGE_SIZE = 15872k + MTDPARTS = spi0.0:320k(u-boot)ro,128k(u-boot-env)ro,15872k(firmware),64k(art)ro + IMAGES := sysupgrade.bin factory.img +endef + +define Device/wndr3800 +$(Device/wndr3700v2) + NETGEAR_BOARD_ID = WNDR3800 + NETGEAR_HW_ID = 29763654+16+128 +endef + +define Device/wndr3800ch +$(Device/wndr3800) + NETGEAR_BOARD_ID = WNDR3800CH +endef + +define Device/wndrmac +$(Device/wndr3700v2) + NETGEAR_BOARD_ID = WNDRMAC +endef + +define Device/wndrmacv2 +$(Device/wndr3800) + NETGEAR_BOARD_ID = WNDRMACv2 +endef + +TARGET_DEVICES += wndr3700 wndr3700v2 wndr3800 wndr3800ch wndrmac wndrmacv2 + +define Device/tplink + TPLINK_HWREV := 0x1 + TPLINK_HEADER_VERSION := 1 + KERNEL := kernel-bin | patch-cmdline | lzma + KERNEL_INITRAMFS := kernel-bin | patch-cmdline | lzma | mktplinkfw-initramfs + IMAGES := sysupgrade.bin factory.bin + IMAGE/sysupgrade.bin := append-rootfs | mktplinkfw sysupgrade + IMAGE/factory.bin := append-rootfs | mktplinkfw factory +endef + +define Device/tplink-nolzma +$(Device/tplink) + LOADER_FLASH_OFFS := 0x22000 + COMPILE := loader-$(1).gz + COMPILE/loader-$(1).gz := loader-okli-compile + KERNEL := copy-file $(KDIR)/vmlinux.bin.lzma | uImage lzma -M 0x4f4b4c49 | loader-okli $(1) + KERNEL_INITRAMFS := copy-file $(KDIR)/vmlinux-initramfs.bin.lzma | loader-kernel | mktplinkfw-initramfs +endef + +define Device/tplink-4m +$(Device/tplink-nolzma) + TPLINK_FLASHLAYOUT := 4M + IMAGE_SIZE := 3904k +endef + +define Device/tplink-8m +$(Device/tplink-nolzma) + TPLINK_FLASHLAYOUT := 8M + IMAGE_SIZE := 7936k +endef + +define Device/tplink-4mlzma +$(Device/tplink) + TPLINK_FLASHLAYOUT := 4Mlzma + IMAGE_SIZE := 3904k +endef + +define Device/tplink-8mlzma +$(Device/tplink) + TPLINK_FLASHLAYOUT := 8Mlzma + IMAGE_SIZE := 7936k +endef + +define Device/tplink-16mlzma +$(Device/tplink) + TPLINK_FLASHLAYOUT := 16Mlzma + IMAGE_SIZE := 15872k +endef + +define Device/tl-wdr4300-v1 +$(Device/tplink-8mlzma) + BOARDNAME = TL-WDR4300 + DEVICE_PROFILE = TLWDR4300 + TPLINK_HWID := 0x43000001 +endef + +define Device/tl-wdr3500-v1 +$(Device/tl-wdr4300-v1) + BOARDNAME = TL-WDR3500 + TPLINK_HWID := 0x35000001 +endef + +define Device/tl-wdr3600-v1 +$(Device/tl-wdr4300-v1) + TPLINK_HWID := 0x36000001 +endef + +define Device/tl-wdr4300-v1-il +$(Device/tl-wdr4300-v1) + TPLINK_HWID := 0x43008001 +endef + +define Device/tl-wdr4310-v1 +$(Device/tl-wdr4300-v1) + TPLINK_HWID := 0x43100001 +endef + +define Device/mw4530r-v1 +$(Device/tl-wdr4300-v1) + TPLINK_HWID := 0x45300001 +endef +TARGET_DEVICES += tl-wdr3500-v1 tl-wdr3600-v1 tl-wdr4300-v1 tl-wdr4300-v1-il tl-wdr4310-v1 mw4530r-v1 + +define Device/tl-wdr6500-v2 +$(Device/tplink-8mlzma) + KERNEL := kernel-bin | patch-cmdline | lzma | uImage lzma + KERNEL_INITRAMFS := kernel-bin | patch-cmdline | lzma | uImage lzma | mktplinkfw-initramfs + BOARDNAME = TL-WDR6500-v2 + DEVICE_PROFILE = TLWDR6500V2 + TPLINK_HWID := 0x65000002 + TPLINK_HEADER_VERSION := 2 +endef +TARGET_DEVICES += tl-wdr6500-v2 + +define Device/tl-wdr3320-v2 +$(Device/tplink-4mlzma) + BOARDNAME = TL-WDR3320-v2 + DEVICE_PROFILE = TLWDR3320V2 + TPLINK_HWID := 0x33200002 + TPLINK_HEADER_VERSION := 2 +endef +TARGET_DEVICES += tl-wdr3320-v2 + +define Device/archer-c5-v1 + $(Device/tplink-16mlzma) + BOARDNAME := ARCHER-C5 + DEVICE_PROFILE := ARCHERC7 + TPLINK_HWID := 0xc5000001 +endef + +define Device/archer-c7-v1 + $(Device/tplink-8mlzma) + BOARDNAME := ARCHER-C7 + DEVICE_PROFILE := ARCHERC7 + TPLINK_HWID := 0x75000001 +endef + +define Device/archer-c7-v2 + $(Device/tplink-16mlzma) + BOARDNAME := ARCHER-C7 + DEVICE_PROFILE := ARCHERC7 + TPLINK_HWID := 0xc7000002 +endef + +define Device/tl-wdr7500-v3 + $(Device/tplink-8mlzma) + BOARDNAME := ARCHER-C7 + DEVICE_PROFILE := ARCHERC7 + TPLINK_HWID := 0x75000003 +endef +TARGET_DEVICES += archer-c5-v1 archer-c7-v1 archer-c7-v2 tl-wdr7500-v3 + +define Device/antminer-s1 + $(Device/tplink-8mlzma) + BOARDNAME := ANTMINER-S1 + DEVICE_PROFILE := ANTMINERS1 + TPLINK_HWID := 0x04440101 + CONSOLE := ttyATH0,115200 +endef + +define Device/antminer-s3 + $(Device/tplink-8mlzma) + BOARDNAME := ANTMINER-S3 + DEVICE_PROFILE := ANTMINERS3 + TPLINK_HWID := 0x04440301 + CONSOLE := ttyATH0,115200 +endef + +define Device/el-m150 + $(Device/tplink-8mlzma) + BOARDNAME := EL-M150 + DEVICE_PROFILE := ELM150 + TPLINK_HWID := 0x01500101 + CONSOLE := ttyATH0,115200 +endef + +define Device/el-mini + $(Device/tplink-8mlzma) + BOARDNAME := EL-MINI + DEVICE_PROFILE := ELMINI + TPLINK_HWID := 0x01530001 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += antminer-s1 antminer-s3 el-m150 el-mini + +define Device/gl-inet-6408A-v1 + $(Device/tplink-8mlzma) + BOARDNAME := GL-INET + DEVICE_PROFILE := GLINET + TPLINK_HWID := 0x08000001 + CONSOLE := ttyATH0,115200 +endef + +define Device/gl-inet-6416A-v1 + $(Device/tplink-16mlzma) + BOARDNAME := GL-INET + DEVICE_PROFILE := GLINET + TPLINK_HWID := 0x08000001 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += gl-inet-6408A-v1 gl-inet-6416A-v1 + +define Device/rnx-n360rt + $(Device/tplink-4m) + BOARDNAME := TL-WR941ND + DEVICE_PROFILE := RNXN360RT + TPLINK_HWID := 0x09410002 + TPLINK_HWREV := 0x00420001 +endef +TARGET_DEVICES += rnx-n360rt + +define Device/mc-mac1200r + $(Device/tplink-8mlzma) + BOARDNAME := MC-MAC1200R + DEVICE_PROFILE := MAC1200R + TPLINK_HWID := 0x12000001 +endef +TARGET_DEVICES += mc-mac1200r + +define Device/minibox-v1 + $(Device/tplink-16mlzma) + BOARDNAME := MINIBOX-V1 + DEVICE_PROFILE := MINIBOXV1 + TPLINK_HWID := 0x3C000201 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += minibox-v1 + +define Device/onion-omega + $(Device/tplink-16mlzma) + BOARDNAME := ONION-OMEGA + DEVICE_PROFILE := OMEGA + TPLINK_HWID := 0x04700001 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += onion-omega + +define Device/tl-mr10u-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR10U + DEVICE_PROFILE := TLMR10U + TPLINK_HWID := 0x00100101 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr11u-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR11U + DEVICE_PROFILE := TLMR11U + TPLINK_HWID := 0x00110101 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr11u-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR11U + DEVICE_PROFILE := TLMR11U + TPLINK_HWID := 0x00110102 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr12u-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR13U + DEVICE_PROFILE := TLMR12U + TPLINK_HWID := 0x00120101 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr13u-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR13U + DEVICE_PROFILE := TLMR13U + TPLINK_HWID := 0x00130101 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += tl-mr10u-v1 tl-mr11u-v1 tl-mr11u-v2 tl-mr12u-v1 tl-mr13u-v1 + +define Device/tl-mr3020-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3020 + DEVICE_PROFILE := TLMR3020 + TPLINK_HWID := 0x30200001 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr3040-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3040 + DEVICE_PROFILE := TLMR3040 + TPLINK_HWID := 0x30400001 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr3040-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3040-v2 + DEVICE_PROFILE := TLMR3040 + TPLINK_HWID := 0x30400002 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr3220-v1 + $(Device/tplink-4m) + BOARDNAME := TL-MR3220 + DEVICE_PROFILE := TLMR3220 + TPLINK_HWID := 0x32200001 +endef + +define Device/tl-mr3220-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3220-v2 + DEVICE_PROFILE := TLMR3220 + TPLINK_HWID := 0x32200002 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-mr3420-v1 + $(Device/tplink-4m) + BOARDNAME := TL-MR3420 + DEVICE_PROFILE := TLMR3420 + TPLINK_HWID := 0x34200001 +endef + +define Device/tl-mr3420-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-MR3420-v2 + DEVICE_PROFILE := TLMR3420 + TPLINK_HWID := 0x34200002 +endef +TARGET_DEVICES += tl-mr3020-v1 tl-mr3040-v1 tl-mr3040-v2 tl-mr3220-v1 tl-mr3220-v2 tl-mr3420-v1 tl-mr3420-v2 + +define Device/tl-wr703n-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR703N + DEVICE_PROFILE := TLWR703 + TPLINK_HWID := 0x07030101 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr710n-v1 + $(Device/tplink-8mlzma) + BOARDNAME := TL-WR710N + DEVICE_PROFILE := TLWR710 + TPLINK_HWID := 0x07100001 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr710n-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR710N + DEVICE_PROFILE := TLWR710 + TPLINK_HWID := 0x07100002 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr720n-v3 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR720N-v3 + DEVICE_PROFILE := TLWR720 + TPLINK_HWID := 0x07200103 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr720n-v4 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR720N-v3 + DEVICE_PROFILE := TLWR720 + TPLINK_HWID := 0x07200104 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += tl-wr703n-v1 tl-wr710n-v1 tl-wr710n-v2 tl-wr720n-v3 tl-wr720n-v4 + +define Device/tl-wr740n-v1 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR740 + TPLINK_HWID := 0x07400001 +endef + +define Device/tl-wr740n-v3 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR740 + TPLINK_HWID := 0x07400003 +endef + +define Device/tl-wr740n-v4 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR740 + TPLINK_HWID := 0x07400004 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr740n-v5 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR740 + TPLINK_HWID := 0x07400005 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr741nd-v1 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR741 + TPLINK_HWID := 0x07410001 +endef + +define Device/tl-wr741nd-v2 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR741 + TPLINK_HWID := 0x07410001 +endef + +define Device/tl-wr741nd-v4 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR741 + TPLINK_HWID := 0x07410004 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr741nd-v5 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR741 + TPLINK_HWID := 0x07400005 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wr743nd-v1 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR743 + TPLINK_HWID := 0x07430001 +endef + +define Device/tl-wr743nd-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR741ND-v4 + DEVICE_PROFILE := TLWR743 + TPLINK_HWID := 0x07430002 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += tl-wr740n-v1 tl-wr740n-v3 tl-wr740n-v4 tl-wr740n-v5 tl-wr741nd-v1 tl-wr741nd-v2 tl-wr741nd-v4 tl-wr741nd-v5 tl-wr743nd-v1 tl-wr743nd-v2 + +define Device/tl-wr841nd-v1.5 + $(Device/tplink-4m) + BOARDNAME := TL-WR841N-v1.5 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410002 + TPLINK_HWREV := 2 +endef + +define Device/tl-wr841nd-v3 + $(Device/tplink-4m) + BOARDNAME := TL-WR941ND + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410003 + TPLINK_HWREV := 3 +endef + +define Device/tl-wr841nd-v5 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410005 +endef + +define Device/tl-wr841nd-v7 + $(Device/tplink-4m) + BOARDNAME := TL-WR841N-v7 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410007 +endef + +define Device/tl-wr841n-v8 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v8 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410008 +endef + +define Device/tl-wr841n-v9 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v9 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410009 +endef + +define Device/tl-wr841n-v10 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v9 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08410010 +endef + +define Device/tl-wr842n-v1 + $(Device/tplink-8m) + BOARDNAME := TL-MR3420 + DEVICE_PROFILE := TLWR842 + TPLINK_HWID := 0x08420001 +endef + +define Device/tl-wr842n-v2 + $(Device/tplink-8mlzma) + BOARDNAME := TL-WR842N-v2 + DEVICE_PROFILE := TLWR842 + TPLINK_HWID := 0x8420002 +endef + +define Device/tl-wr843nd-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v8 + DEVICE_PROFILE := TLWR843 + TPLINK_HWID := 0x08430001 +endef + +define Device/tl-wr847n-v8 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR841N-v8 + DEVICE_PROFILE := TLWR841 + TPLINK_HWID := 0x08470008 +endef +TARGET_DEVICES += tl-wr841nd-v1.5 tl-wr841nd-v3 tl-wr841nd-v5 tl-wr841nd-v7 tl-wr841n-v8 tl-wr841n-v9 tl-wr841n-v10 tl-wr842n-v1 tl-wr842n-v2 tl-wr843nd-v1 tl-wr847n-v8 + +define Device/tl-wr941nd-v2 + $(Device/tplink-4m) + BOARDNAME := TL-WR941ND + DEVICE_PROFILE := TLWR941 + TPLINK_HWID := 0x09410002 + TPLINK_HWREV := 2 +endef + +define Device/tl-wr941nd-v3 + $(Device/tplink-4m) + BOARDNAME := TL-WR941ND + DEVICE_PROFILE := TLWR941 + TPLINK_HWID := 0x09410002 + TPLINK_HWREV := 2 +endef + +define Device/tl-wr941nd-v4 + $(Device/tplink-4m) + BOARDNAME := TL-WR741ND + DEVICE_PROFILE := TLWR941 + TPLINK_HWID := 0x09410004 +endef + +define Device/tl-wr941nd-v5 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR941ND-v5 + DEVICE_PROFILE := TLWR941 + TPLINK_HWID := 0x09410005 +endef + +# Chinese version (unlike European) is similar to the TL-WDR3500 +define Device/tl-wr941nd-v6-cn + $(Device/tplink-4mlzma) + BOARDNAME := TL-WDR3500 + DEVICE_PROFILE := TLWR941 + TPLINK_HWID := 0x09410006 +endef +TARGET_DEVICES += tl-wr941nd-v2 tl-wr941nd-v3 tl-wr941nd-v4 tl-wr941nd-v5 tl-wr941nd-v6-cn + +define Device/tl-wr1041n-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WR1041N-v2 + DEVICE_PROFILE := TLWR1041 + TPLINK_HWID := 0x10410002 +endef +TARGET_DEVICES += tl-wr1041n-v2 + +define Device/tl-wr1043nd-v1 + $(Device/tplink-8m) + BOARDNAME := TL-WR1043ND + DEVICE_PROFILE := TLWR1043 + TPLINK_HWID := 0x10430001 +endef + +define Device/tl-wr1043nd-v2 + $(Device/tplink-8mlzma) + BOARDNAME := TL-WR1043ND-v2 + DEVICE_PROFILE := TLWR1043 + TPLINK_HWID := 0x10430002 +endef +TARGET_DEVICES += tl-wr1043nd-v1 tl-wr1043nd-v2 + +define Device/tl-wr2543-v1 + $(Device/tplink-8mlzma) + BOARDNAME := TL-WR2543N + DEVICE_PROFILE := TLWR2543 + TPLINK_HWID := 0x25430001 + IMAGE/sysupgrade.bin := append-rootfs | mktplinkfw sysupgrade "-v 3.13.99" + IMAGE/factory.bin := append-rootfs | mktplinkfw factory "-v 3.13.99" +endef +TARGET_DEVICES += tl-wr2543-v1 + +define Device/tl-wdr4900-v2 + $(Device/tplink-8mlzma) + BOARDNAME := TL-WDR4900-v2 + DEVICE_PROFILE := TLWDR4900V2 + TPLINK_HWID := 0x49000002 +endef +TARGET_DEVICES += tl-wdr4900-v2 + +define Device/tl-wa701n-v1 + $(Device/tplink-4m) + BOARDNAME := TL-WA901ND + DEVICE_PROFILE := TLWA701 + TPLINK_HWID := 0x07010001 +endef + +define Device/tl-wa701nd-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA701ND-v2 + DEVICE_PROFILE := TLWA701 + TPLINK_HWID := 0x07010002 + CONSOLE := ttyATH0,115200 +endef + +define Device/tl-wa730rev1 + $(Device/tplink-4m) + BOARDNAME := TL-WA901ND + DEVICE_PROFILE := TLWA730RE + TPLINK_HWID := 0x07300001 +endef + +define Device/tl-wa750re-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA750RE + DEVICE_PROFILE := TLWA750 + TPLINK_HWID := 0x07500001 +endef + +define Device/tl-wa7510n + $(Device/tplink-4m) + BOARDNAME := TL-WA7510N + DEVICE_PROFILE := TLWA7510 + TPLINK_HWID := 0x75100001 +endef +TARGET_DEVICES += tl-wa701n-v1 tl-wa701nd-v2 tl-wa730rev1 tl-wa750re-v1 tl-wa7510n + +define Device/tl-wa801nd-v1 + $(Device/tplink-4m) + BOARDNAME := TL-WA901ND + DEVICE_PROFILE := TLWA801 + TPLINK_HWID := 0x08010001 +endef + +define Device/tl-wa801nd-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA801ND-v2 + DEVICE_PROFILE := TLWA801 + TPLINK_HWID := 0x08010002 +endef + +define Device/tl-wa830re-v1 + $(Device/tplink-4m) + BOARDNAME := TL-WA901ND + DEVICE_PROFILE := TLWA830 + TPLINK_HWID := 0x08300010 +endef + +define Device/tl-wa830re-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA830RE-v2 + DEVICE_PROFILE := TLWA830 + TPLINK_HWID := 0x08300002 +endef + +define Device/tl-wa850re-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA850RE + DEVICE_PROFILE := TLWA850 + TPLINK_HWID := 0x08500001 +endef + +define Device/tl-wa860re-v1 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA860RE + DEVICE_PROFILE := TLWA860 + TPLINK_HWID := 0x08600001 +endef +TARGET_DEVICES += tl-wa801nd-v1 tl-wa801nd-v2 tl-wa830re-v1 tl-wa830re-v2 tl-wa850re-v1 tl-wa860re-v1 + +define Device/tl-wa901nd-v1 + $(Device/tplink-4m) + BOARDNAME := TL-WA901ND + DEVICE_PROFILE := TLWA901 + TPLINK_HWID := 0x09010001 +endef + +define Device/tl-wa901nd-v2 + $(Device/tplink-4m) + BOARDNAME := TL-WA901ND-v2 + DEVICE_PROFILE := TLWA901 + TPLINK_HWID := 0x09010002 +endef + +define Device/tl-wa901nd-v3 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA901ND-v3 + DEVICE_PROFILE := TLWA901 + TPLINK_HWID := 0x09010003 +endef +TARGET_DEVICES += tl-wa901nd-v1 tl-wa901nd-v2 tl-wa901nd-v3 + +define Device/tl-wa7210n-v2 + $(Device/tplink-4mlzma) + BOARDNAME := TL-WA7210N-v2 + DEVICE_PROFILE := TLWA7210 + TPLINK_HWID := 0x72100002 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += tl-wa7210n-v2 + +define Device/smart-300 + $(Device/tplink-8mlzma) + BOARDNAME := SMART-300 + DEVICE_PROFILE := SMART-300 + TPLINK_HWID := 0x93410001 +endef +TARGET_DEVICES += smart-300 + +define Device/oolite + $(Device/tplink-16mlzma) + BOARDNAME := GS-OOLITE + DEVICE_PROFILE := OOLITE + TPLINK_HWID := 0x3C000101 + CONSOLE := ttyATH0,115200 +endef +TARGET_DEVICES += oolite + +# UBNT_BOARD e.g. one of (XS2, XS5, RS, XM) +# UBNT_TYPE e.g. one of (BZ, XM, XW) +# UBNT_CHIP e.g. one of (ar7240, ar933x, ar934x) +define Device/ubnt-xm + DEVICE_PROFILE := UBNT + IMAGE_SIZE := 7552k + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7552k(firmware),256k(cfg)ro,64k(EEPROM)ro + UBNT_TYPE := XM + UBNT_BOARD := XM + UBNT_CHIP := ar7240 + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin = $$(IMAGE/sysupgrade.bin) | mkubntimage-split + IMAGE/sysupgrade.bin = append-kernel $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) +endef + +define Device/ubnt-xw + DEVICE_PROFILE := UBNT + IMAGE_SIZE := 7552k + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7552k(firmware),256k(cfg)ro,64k(EEPROM)ro + UBNT_TYPE := XW + UBNT_BOARD := XM + UBNT_CHIP := ar934x + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin = $$(IMAGE/sysupgrade.bin) | mkubntimage-split + IMAGE/sysupgrade.bin = append-kernel $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) +endef + +define Device/ubnt-bz + DEVICE_PROFILE := UBNT + IMAGE_SIZE := 7552k + MTDPARTS = spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7552k(firmware),256k(cfg)ro,64k(EEPROM)ro + UBNT_TYPE := BZ + UBNT_BOARD := XM + UBNT_CHIP := ar934x + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin = $$(IMAGE/sysupgrade.bin) | mkubntimage-split + IMAGE/sysupgrade.bin = append-kernel $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) +endef + +define Device/rw2458n + $(Device/ubnt-xm) + BOARDNAME := RW2458N +endef + +define Device/ubnt-airrouter + $(Device/ubnt-xm) + BOARDNAME := UBNT-AR +endef + +define Device/ubnt-bullet-m + $(Device/ubnt-xm) + BOARDNAME := UBNT-BM +endef + +define Device/ubnt-rocket-m + $(Device/ubnt-xm) + BOARDNAME := UBNT-RM +endef + +define Device/ubnt-nano-m + $(Device/ubnt-xm) + BOARDNAME := UBNT-NM +endef +TARGET_DEVICES += rw2458n ubnt-airrouter ubnt-bullet-m ubnt-rocket-m ubnt-nano-m + +define Device/ubnt-unifi + $(Device/ubnt-bz) + BOARDNAME := UBNT-UF + DEVICE_PROFILE := UBNT UBNTUNIFI +endef + +define Device/ubnt-unifi-outdoor + $(Device/ubnt-bz) + BOARDNAME := UBNT-U20 + DEVICE_PROFILE := UBNT UBNTUNIFIOUTDOOR +endef +TARGET_DEVICES += ubnt-unifi ubnt-unifi-outdoor + +define Device/ubnt-nano-m-xw + $(Device/ubnt-xw) + BOARDNAME := UBNT-NM-XW +endef + +define Device/ubnt-loco-m-xw + $(Device/ubnt-xw) + BOARDNAME := UBNT-LOCO-XW +endef + +define Device/ubnt-rocket-m-xw + $(Device/ubnt-xw) + BOARDNAME := UBNT-RM-XW +endef + +define Device/ubnt-rocket-m-ti + $(Device/ubnt-xw) + BOARDNAME := UBNT-RM-TI + UBNT_TYPE := TI + UBNT_BOARD := XM +endef +TARGET_DEVICES += ubnt-nano-m-xw ubnt-loco-m-xw ubnt-rocket-m-xw ubnt-rocket-m-ti + +define Device/ubnt-air-gateway + $(Device/ubnt-xm) + BOARDNAME := UBNT-AGW + UBNT_BOARD := XM + UBNT_TYPE := AirGW + UBNT_CHIP := ar933x + CONSOLE = ttyATH0,115200 +endef +TARGET_DEVICES += ubnt-air-gateway + +define Device/ubnt-air-gateway-pro + $(Device/ubnt-xm) + BOARDNAME := UBNT-AGWP + UBNT_TYPE := AirGWP + UBNT_CHIP := ar934x + CONSOLE = ttyS0,115200 +endef +TARGET_DEVICES += ubnt-air-gateway-pro + +define Device/ubdev01 + $(Device/ubnt-xm) + MTDPARTS := spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7488k(firmware),64k(certs),256k(cfg)ro,64k(EEPROM)ro + BOARDNAME := UBNT-UF + UBNT_BOARD := XM + UBNT_TYPE := XM + UBNT_CHIP := ar7240 +endef + +TARGET_DEVICES += ubdev01 + +define Device/ubnt-routerstation + IMAGE_SIZE := 16128k + IMAGES := sysupgrade.bin factory.bin + IMAGE/factory.bin = append-rootfs | pad-rootfs | mkubntimage + IMAGE/sysupgrade.bin = append-rootfs | pad-rootfs | combined-image | check-size $$$$(IMAGE_SIZE) + KERNEL := kernel-bin | patch-cmdline | lzma | pad-to $$(BLOCKSIZE) +endef + +define Device/ubnt-rs +$(Device/ubnt-routerstation) + BOARDNAME := UBNT-RS + DEVICE_PROFILE := Madwifi UBNT UBNTRS + UBNT_BOARD := RS + UBNT_TYPE := RSx + UBNT_CHIP := ar7100 +endef + +define Device/ubnt-rspro +$(Device/ubnt-routerstation) + BOARDNAME := UBNT-RSPRO + DEVICE_PROFILE := Madwifi UBNT UBNTRSPRO + UBNT_BOARD := RSPRO + UBNT_TYPE := RSPRO + UBNT_CHIP := ar7100pro +endef + +define Device/ubnt-ls-sr71 +$(Device/ubnt-routerstation) + BOARDNAME := UBNT-LS-SR71 + DEVICE_PROFILE := Madwifi UBNT + UBNT_BOARD := LS-SR71 + UBNT_TYPE := LS-SR71 + UBNT_CHIP := ar7100 +endef + +TARGET_DEVICES += ubnt-rs ubnt-rspro ubnt-ls-sr71 + +define Device/ubnt-uap-pro + IMAGE_SIZE := 15744k + MTDPARTS := spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1536k(kernel),14208k(rootfs),256k(cfg)ro,64k(EEPROM)ro,15744k@0x50000(firmware) + UBNT_TYPE := BZ + UBNT_CHIP := ar934x + BOARDNAME := UAP-PRO + DEVICE_PROFILE := UBNT UAPPRO + KERNEL := kernel-bin | patch-cmdline | lzma | uImage lzma | mkubntkernelimage + IMAGES := sysupgrade.bin factory.bin + IMAGE/sysupgrade.bin = append-kernel 1536k | append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) + IMAGE/factory.bin = $$(IMAGE/sysupgrade.bin) | mkubntimage2 +endef + +define Device/ubnt-unifi-outdoor-plus +$(Device/ubnt-uap-pro) + UBNT_CHIP := ar7240 + BOARDNAME := UBNT-UOP + DEVICE_PROFILE := UBNT +endef + +TARGET_DEVICES += ubnt-uap-pro ubnt-unifi-outdoor-plus + +rootfs_type=$(patsubst jffs2-%,jffs2,$(patsubst squashfs-%,squashfs,$(1))) + +# $(1): rootfs type. +# $(2): board name. +define imgname +$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(call rootfs_type,$(1)) +endef + +define rootfs_align +$(patsubst %-256k,0x40000,$(patsubst %-128k,0x20000,$(patsubst %-64k,0x10000,$(patsubst squashfs%,0x4,$(patsubst root.%,%,$(1)))))) +endef + +define sysupname +$(call imgname,$(1),$(2))-sysupgrade.bin +endef + +define factoryname +$(call imgname,$(1),$(2))-factory.bin +endef + +COMMA:=, + +define mkcmdline +$(if $(1),board=$(1) )$(if $(2),console=$(2)$(COMMA)$(3)) +endef + +define mtdpartsize +$(shell sz=`echo '$(2)' | sed -ne 's/.*[:$(COMMA)]\([0-9]*\)k[@]*[0-9a-zx]*($(1)).*/\1/p'`; [ -n "$$sz" ] && echo $$(($$sz * 1024))) +endef + +SINGLE_PROFILES:= + +# $(1) : name of image build method to be used, e.g., AthLzma. +# $(2) : name of the build template to be used, e.g. 64k, 64kraw, 128k, etc. +# $(3) : name of the profile to be defined. +# $(4) : board name. +# $(5)~$(7) : arguments for $(mkcmdline) +# board=$(1) console=$(2),$(3) +# $(8)~$(14): extra arguments. +define SingleProfile + # $(1): action name, e.g. loader, buildkernel, squashfs, etc. + define Image/Build/Profile/$(3) + $$(call Image/Build/Template/$(2)/$$(1),$(1),$(4),$$(call mkcmdline,$(5),$(6),$(7)),$(8),$(9),$(10),$(11),$(12),$(13),$(14)) + endef + SINGLE_PROFILES += $(3) +endef + +# $(1), name of the MultiProfile to be added. +# $(2), name of Profiles to be included in the MultiProfile. +define MultiProfile + define Image/Build/Profile/$(1) + $(foreach p,$(2), + $$(call Image/Build/Profile/$p,$$(1)) + ) + endef +endef + +LOADER_MAKE := $(NO_TRACE_MAKE) -C lzma-loader KDIR=$(KDIR) + +VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux +UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage + +# $(1): input file. +# $(2): output file. +# $(3): extra arguments for lzma. +define CompressLzma + $(STAGING_DIR_HOST)/bin/lzma e $(1) -lc1 -lp2 -pb2 $(3) $(2) +endef + +define PatchKernel + cp $(KDIR)/vmlinux$(3) $(KDIR_TMP)/vmlinux$(3)-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR_TMP)/vmlinux$(3)-$(1) "$(strip $(2))" +endef + +define PatchKernel/initramfs + $(call PatchKernel,$(1),$(2),-initramfs) + cp $(KDIR_TMP)/vmlinux-initramfs-$(1) $(call imgname,initramfs,$(1)).bin +endef + +# $(1): board name. +# $(2): kernel command line. +# $(3): extra argumetns for lzma. +# $(4): name suffix, e.g. "-initramfs". +define PatchKernelLzma + cp $(KDIR)/vmlinux$(4) $(KDIR_TMP)/vmlinux$(4)-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR_TMP)/vmlinux$(4)-$(1) "$(strip $(2))" + $(call CompressLzma,$(KDIR_TMP)/vmlinux$(4)-$(1),$(KDIR_TMP)/vmlinux$(4)-$(1).bin.lzma,$(3)) +endef + +define PatchKernelGzip + cp $(KDIR)/vmlinux$(3) $(KDIR_TMP)/vmlinux$(3)-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR_TMP)/vmlinux$(3)-$(1) "$(strip $(2))" + gzip -9n -c $(KDIR_TMP)/vmlinux$(3)-$(1) > $(KDIR_TMP)/vmlinux$(3)-$(1).bin.gz +endef + +ifneq ($(SUBTARGET),mikrotik) +# $(1): compression method of the data. +# $(2): extra arguments. +# $(3): input data file. +# $(4): output file. +define MkuImage + mkimage -A mips -O linux -T kernel -a 0x80060000 -C $(1) $(2) \ + -e 0x80060000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(3) $(4) +endef + +# $(1): board name. +# $(2): kernel command line. +# $(3): extra arguments for lzma. +# $(4): name suffix, e.g. "-initramfs". +# $(5): extra arguments for mkimage. +define MkuImageLzma + $(call PatchKernelLzma,$(1),$(2),$(3),$(4)) + $(call MkuImage,lzma,$(5),$(KDIR_TMP)/vmlinux$(4)-$(1).bin.lzma,$(KDIR_TMP)/vmlinux$(4)-$(1).uImage) +endef + +define MkuImageLzma/initramfs + $(call PatchKernelLzma,$(1),$(2),$(3),-initramfs) + $(call MkuImage,lzma,$(4),$(KDIR_TMP)/vmlinux-initramfs-$(1).bin.lzma,$(call imgname,initramfs,$(1))-uImage.bin) +endef + +define MkuImageGzip + $(call PatchKernelGzip,$(1),$(2)) + $(call MkuImage,gzip,,$(KDIR_TMP)/vmlinux-$(1).bin.gz,$(KDIR_TMP)/vmlinux-$(1).uImage) +endef + +define MkuImageGzip/initramfs + $(call PatchKernelGzip,$(1),$(2),-initramfs) + $(call MkuImage,gzip,,$(KDIR_TMP)/vmlinux-initramfs-$(1).bin.gz,$(call imgname,initramfs,$(1))-uImage.bin) +endef + +define MkuImageOKLI + $(call MkuImage,lzma,-M 0x4f4b4c49,$(KDIR)/vmlinux.bin.lzma,$(KDIR_TMP)/vmlinux-$(1).okli) +endef +endif + +# $(1): name of the 1st file. +# $(2): size limit of the 1st file if it is greater than 262144, or +# the erase size of the flash if it is greater than zero and less +# than 262144 +# $(3): name of the 2nd file. +# $(4): size limit of the 2nd file if $(2) is greater than 262144, otherwise +# it is the size limit of the output file +# $(5): name of the output file. +# $(6): padding size. +define CatFiles + if [ $(2) -eq 0 ]; then \ + filename="$(3)"; fstype=$$$${filename##*\.}; \ + case "$$$${fstype}" in \ + "jffs2-64k") bs=65536;; \ + "jffs2-128k") bs=131072;; \ + "jffs2-256k") bs=262144;; \ + *) bs=`stat -c%s $(1)`;; \ + esac; \ + ( dd if=$(1) bs=$$$${bs} conv=sync; cat $(3) ) > $(5); \ + if [ -n "$(6)" ]; then \ + case "$$$${fstype}" in \ + squashfs*) \ + padjffs2 $(5) $(6); \ + ;; \ + esac; \ + fi; \ + if [ `stat -c%s $(5)` -gt $(4) ]; then \ + echo "Warning: $(5) is too big (> $(4) bytes)" >&2; \ + rm -f $(5); \ + fi; \ + else if [ $(2) -gt 262144 ]; then \ + if [ `stat -c%s "$(1)"` -gt $(2) ]; then \ + echo "Warning: $(1) is too big (> $(2) bytes)" >&2; \ + else if [ `stat -c%s $(3)` -gt $(4) ]; then \ + echo "Warning: $(3) is too big (> $(4) bytes)" >&2; \ + else \ + ( dd if=$(1) bs=$(2) conv=sync; dd if=$(3) ) > $(5); \ + fi; fi; \ + else \ + ( dd if=$(1) bs=$(2) conv=sync; dd if=$(3) ) > $(5); \ + if [ `stat -c%s $(5)` -gt $(4) ]; then \ + echo "Warning: $(5) is too big (> $(4) bytes)" >&2; \ + rm -f $(5); \ + fi; \ + fi; fi +endef + +# $(1): rootfs type. +# $(2): board name. +# $(3): kernel image size limit. +# $(4): rootfs image size limit. +# $(5): padding argument for padjffs2. +Sysupgrade/KR=$(call CatFiles,$(2),$(3),$(KDIR)/root.$(1),$(4),$(call sysupname,$(1),$(5))) +Sysupgrade/KRuImage=$(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).uImage,$(3),$(KDIR)/root.$(1),$(4),$(call sysupname,$(1),$(2)),$(5)) +Sysupgrade/RKuImage=$(call CatFiles,$(KDIR)/root.$(1),$(4),$(KDIR_TMP)/vmlinux-$(2).uImage,$(3),$(call sysupname,$(1),$(2))) + +# $(1): ubinize ini file +# $(2): working directory +# $(3): output file +# $(4): physical erase block size +# $(5): minimum I/O unit size +# $(6): custom options +define ubinize + $(CP) $(1) $(2) + ( cd $(2); $(STAGING_DIR_HOST)/bin/ubinize -o $(3) -p $(4) -m $(5) $(6) $(1)) +endef + +# +# Embed lzma-compressed kernel inside lzma-loader. +# +# $(1), suffix of output filename, e.g. generic, lowercase board name, etc. +# $(2), suffix of target file to build, e.g. bin, gz, elf +# $(3), kernel command line to pass from lzma-loader to kernel +# $(4), unused here +# $(5), suffix of kernel filename, e.g. -initramfs, or empty +define Image/BuildLoader + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) KERNEL_CMDLINE="$(3)"\ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + LOADER_DATA="$(KDIR)/vmlinux$(5).bin.lzma" BOARD="$(1)" \ + compile loader.$(2) + -$(CP) $(KDIR)/loader-$(1).$(2) $(KDIR)/loader-$(1)$(5).$(2) +endef + +# +# Embed patched lzma-compressed kernel inside lzma-loader. +# +# Specifying the command line via the lzma-loader doesn't work with some +# models (like the TP-LINK CPE series), so this version first patches the +# command line in the image and then builds the loader around it. +# +# $(1), suffix of output filename, e.g. generic, lowercase board name, etc. +# $(2), suffix of target file to build, e.g. bin, gz, elf +# $(3), kernel command line to pass from lzma-loader to kernel +# $(4), unused here +# $(5), suffix of kernel filename, e.g. -initramfs, or empty +define Image/BuildLoaderPatched + $(call PatchKernelLzma,$(1),$(3)) + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) \ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + LOADER_DATA="$(KDIR_TMP)/vmlinux-$(1)$(5).bin.lzma" BOARD="$(1)" \ + compile loader.$(2) + -$(CP) $(KDIR)/loader-$(1).$(2) $(KDIR)/loader-$(1)$(5).$(2) +endef + +# +# Build lzma-loader alone which will search for lzma-compressed kernel identified by +# uImage header with magic "OKLI" at boot time. +# +# $(4), offset into the flash space to start searching uImage magic "OKLI". +# $(5), size of search range starting at $(4). With 0 as the value, uImage +# header is expected to be at precisely $(4) +define Image/BuildLoaderAlone + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader-$(1).$(2) KERNEL_CMDLINE="$(3)" \ + LZMA_TEXT_START=0x80a00000 LOADADDR=0x80060000 \ + BOARD="$(1)" FLASH_OFFS=$(4) FLASH_MAX=$(5) \ + compile loader.$(2) +endef + +define Build/Clean + $(LOADER_MAKE) clean +endef + + +alfa_ap96_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env)ro,13312k(rootfs),2048k(kernel),512k(caldata)ro,15360k@0x80000(firmware) +alfa_mtdlayout_8M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6144k(rootfs),1600k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) +alfa_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,15936k(firmware),64k(nvram),64k(art)ro +all0258n_mtdlayout=mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),6272k(firmware),1536k(failsafe),64k(art) +all0315n_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env),13568k(firmware),2048k(failsafe),256k(art)ro +ap81_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,5120k(rootfs),2688k(kernel),64k(art)ro,7808k@0x50000(firmware) +ap83_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,128k(u-boot-env)ro,4096k(rootfs),3648k(kernel),64k(art)ro,7744k@0x60000(firmware) +ap96_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,6144k(rootfs),1728k(kernel),64k(art)ro,7872k@0x40000(firmware) +ap113_mtd_layout=mtdparts=spi0.0:64k(u-boot),3008k(rootfs),896k(uImage),64k(NVRAM),64k(ART),3904k@0x10000(firmware) +ap121_mtdlayout_2M=mtdparts=spi0.0:64k(u-boot)ro,1216k(rootfs),704k(kernel),64k(art)ro,1920k@0x10000(firmware) +ap121_mtdlayout_4M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,2448k(rootfs),1200k(kernel),64k(nvram),64k(art)ro,3648k@0x50000(firmware) +ap121_mtdlayout_8M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6144k(rootfs),1600k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) +ap132_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),6400k(rootfs),64k(art),7808k@0x50000(firmware) +ap135_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1472k(kernel),64k(art)ro,16000k@0x50000(firmware) +ap136_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(mib0),64k(art)ro,7744k@0x50000(firmware) +ap143_mtdlayout_8M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1472k(kernel),64k(art)ro,7744k@0x50000(firmware) +ap143_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1472k(kernel),64k(art)ro,16000k@0x50000(firmware) +ap147_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1472k(kernel),64k(art),16000k@0x50000(firmware) +ap152_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,14528k(rootfs),1472k(kernel),64k(art)ro,16000k@0x50000(firmware) +bxu2000n2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),8448k(rootfs),6016k(user),64k(cfg),64k(oem),64k(art)ro +cameo_ap81_mtdlayout=mtdparts=spi0.0:128k(u-boot)ro,64k(config)ro,3840k(firmware),64k(art)ro +cameo_ap91_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(nvram)ro,3712k(firmware),64k(mac)ro,64k(art)ro +cameo_ap99_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(nvram)ro,3520k(firmware),64k(mac)ro,192k(lp)ro,64k(art)ro +cameo_ap121_mtdlayout=mtdparts=spi0.0:64k(u-boot)ro,64k(art)ro,64k(mac)ro,64k(nvram)ro,192k(language)ro,3648k(firmware) +cameo_ap121_mtdlayout_8M=mtdparts=spi0.0:64k(u-boot)ro,64k(art)ro,64k(mac)ro,64k(nvram)ro,256k(language)ro,7680k@0x80000(firmware) +cameo_ap123_mtdlayout_4M=mtdparts=spi0.0:64k(u-boot)ro,64k(nvram)ro,3712k(firmware),192k(lang)ro,64k(art)ro +cameo_db120_mtdlayout=mtdparts=spi0.0:64k(uboot)ro,64k(nvram)ro,15936k(firmware),192k(lang)ro,64k(mac)ro,64k(art)ro +cameo_db120_mtdlayout_8M=mtdparts=spi0.0:64k(uboot)ro,64k(nvram)ro,7872k(firmware),128k(lang)ro,64k(art)ro +cap4200ag_mtdlayout=mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),320k(custom)ro,1536k(kernel),12096k(rootfs),2048k(failsafe),64k(art),13632k@0xa0000(firmware) +cpe510_mtdlayout=mtdparts=spi0.0:128k(u-boot)ro,64k(pation-table)ro,64k(product-info)ro,1536k(kernel),6144k(rootfs),192k(config)ro,64k(ART)ro,7680k@0x40000(firmware) +eap300v2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),320k(custom),13632k(firmware),2048k(failsafe),64k(art)ro +db120_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware) +dgl_5500_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(nvram)ro,15296k(firmware),192k(lang)ro,512k(my-dlink)ro,64k(mac)ro,64k(art)ro +dlan_pro_500_wp_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,64k(Config1)ro,64k(Config2)ro,7680k@0x70000(firmware),64k(art)ro +dlan_pro_1200_ac_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,64k(Config1)ro,64k(Config2)ro,15872k@0x70000(firmware),64k(art)ro +cameo_ap94_mtdlayout=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,6208k(firmware),64k(caldata)ro,1600k(unknown)ro,64k@0x7f0000(caldata_copy) +cameo_ap94_mtdlayout_fat=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,7808k(firmware),64k(caldata)ro,64k@0x660000(caldata_orig),6208k@0x50000(firmware_orig) +esr900_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware) +esr1750_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware) +epg5000_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),13248k(rootfs),1024k(manufacture)ro,64k(backup)ro,320k(storage)ro,64k(caldata)ro,14656k@0x40000(firmware) +ew-dorin_mtdlayout_4M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),3712k(firmware),64k(art) +ew-dorin_mtdlayout_16M=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),16000k(firmware),64k(art)ro +f9k1115v2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),14464k(rootfs),1408k(kernel),64k(nvram)ro,64k(envram)ro,64k(art)ro,15872k@0x50000(firmware) +dlrtdev_mtdlayout=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,6208k(firmware),64k(caldata)ro,640k(certs),960k(unknown)ro,64k@0x7f0000(caldata_copy) +dlrtdev_mtdlayout_fat=mtdparts=spi0.0:256k(uboot)ro,64k(config)ro,7168k(firmware),640k(certs),64k(caldata)ro,64k@0x660000(caldata_orig),6208k@0x50000(firmware_orig) +dragino2_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,16000k(firmware),64k(config)ro,64k(art)ro +hiwifi_hc6361_mtdlayout=mtdparts=spi0.0:64k(u-boot)ro,64k(bdinfo)ro,1280k(kernel),14848k(rootfs),64k(backup)ro,64k(art)ro,16128k@0x20000(firmware) +mr12_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env)ro,13440k(rootfs),2304k(kernel),128k(art)ro,15744k@0x80000(firmware) +mr16_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,256k(u-boot-env)ro,13440k(rootfs),2304k(kernel),128k(art)ro,15744k@0x80000(firmware) +pb92_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,2752k(rootfs),896k(kernel),64k(nvram),64k(art)ro,3648k@0x50000(firmware) +planex_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7744k(firmware),128k(art)ro +ubntxm_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7552k(firmware),256k(cfg)ro,64k(EEPROM)ro +uap_pro_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1536k(kernel),14208k(rootfs),256k(cfg)ro,64k(EEPROM)ro,15744k@0x50000(firmware) +ubdev_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7488k(firmware),64k(certs),256k(cfg)ro,64k(EEPROM)ro +whrhpg300n_mtdlayout=mtdparts=spi0.0:248k(u-boot)ro,8k(u-boot-env)ro,3712k(firmware),64k(art)ro +wlr8100_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),14080k(rootfs),192k(unknown)ro,64k(art)ro,384k(unknown2)ro,15488k@0x40000(firmware) +wpj344_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro +wpj531_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro +wpj558_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro +wndap360_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1728k(kernel),6016k(rootfs),64k(nvram)ro,64k(art)ro,7744k@0x50000(firmware) +wnr2200_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7808k(firmware),64k(art)ro +wnr2000v3_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,3712k(firmware),64k(art)ro +wnr2000v4_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,3776k(firmware),64k(art)ro +r6100_mtdlayout=mtdparts=ar934x-nfc:128k(u-boot)ro,256k(caldata),256k(caldata-backup),512k(config),512k(pot),2048k(kernel),122240k(ubi),25600k@0x1a0000(firmware),2048k(language),3072k(traffic_meter) +wndr4300_mtdlayout=mtdparts=ar934x-nfc:256k(u-boot)ro,256k(u-boot-env)ro,256k(caldata),512k(pot),2048k(language),512k(config),3072k(traffic_meter),2048k(kernel),23552k(ubi),25600k@0x6c0000(firmware),256k(caldata_backup),-(reserved) +zcn1523h_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6208k(rootfs),1472k(kernel),64k(configure)ro,64k(mfg)ro,64k(art)ro,7680k@0x50000(firmware) +mynet_n600_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,64k(devdata)ro,64k(devconf)ro,15872k(firmware),64k(radiocfg)ro +mynet_rext_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,7808k(firmware),64k(nvram)ro,64k(ART)ro +zyx_nbg6716_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(env)ro,64k(RFdata)ro,-(nbu);ar934x-nfc:2048k(zyxel_rfsd),2048k(romd),1024k(header),2048k(kernel),-(ubi) +qihoo_c301_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env),64k(devdata),64k(devconf),15744k(firmware),64k(warm_start),64k(action_image_config),64k(radiocfg)ro;spi0.1:15360k(upgrade2),1024k(privatedata) + + +define Image/BuildKernel + cp $(KDIR)/vmlinux.elf $(VMLINUX).elf + cp $(KDIR)/vmlinux $(VMLINUX).bin + dd if=$(KDIR)/vmlinux.bin.lzma of=$(VMLINUX).lzma bs=65536 conv=sync + dd if=$(KDIR)/vmlinux.bin.gz of=$(VMLINUX).gz bs=65536 conv=sync + $(call MkuImage,gzip,,$(KDIR)/vmlinux.bin.gz,$(UIMAGE)-gzip.bin) + $(call MkuImage,lzma,,$(KDIR)/vmlinux.bin.lzma,$(UIMAGE)-lzma.bin) + cp $(KDIR)/loader-generic.elf $(VMLINUX)-lzma.elf + -mkdir -p $(KDIR_TMP) + $(call Image/Build/Profile/$(IMAGE_PROFILE),buildkernel) +endef + +define Image/BuildKernel/Initramfs + cp $(KDIR)/vmlinux-initramfs.elf $(VMLINUX)-initramfs.elf + cp $(KDIR)/vmlinux-initramfs $(VMLINUX)-initramfs.bin + dd if=$(KDIR)/vmlinux-initramfs.bin.lzma of=$(VMLINUX)-initramfs.lzma bs=65536 conv=sync + dd if=$(KDIR)/vmlinux-initramfs.bin.gz of=$(VMLINUX)-initramfs.gz bs=65536 conv=sync + $(call MkuImage,gzip,,$(KDIR)/vmlinux-initramfs.bin.gz,$(UIMAGE)-initramfs-gzip.bin) + $(call MkuImage,lzma,,$(KDIR)/vmlinux-initramfs.bin.lzma,$(UIMAGE)-initramfs-lzma.bin) + cp $(KDIR)/loader-generic-initramfs.elf $(VMLINUX)-initramfs-lzma.elf + $(call Image/Build/Initramfs) +endef + +Image/Build/WRT400N/buildkernel=$(call MkuImageLzma,$(2),$(3)) + +define Image/Build/WRT400N + $(call Sysupgrade/KRuImage,$(1),$(2),1310720,6488064) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + wrt400n $(KDIR_TMP)/vmlinux-$(2).uImage $(KDIR)/root.$(1) $(call factoryname,$(1),$(2)); \ + fi +endef + + +define Image/Build/CameoAP94/buildkernel + $(call MkuImageLzma,$(2),$(3) $(4)) + $(call MkuImageLzma,$(2)-fat,$(3) $(5)) +endef + +define Image/Build/CameoAP94 + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval fwsize_fat=$(call mtdpartsize,firmware,$(5))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + dd if=$(call sysupname,$(1),$(2)); \ + echo -n "$(6)"; \ + ) > $(call imgname,$(1),$(2))-backup-loader.bin; \ + if [ `stat -c%s $(call sysupname,$(1),$(2))` -gt 4194304 ]; then \ + echo "Warning: $(call sysupname,$(1),$(2)) is too big" >&2; \ + else \ + ( \ + dd if=$(call sysupname,$(1),$(2)) bs=4096k conv=sync; \ + echo -n "$(7)"; \ + ) > $(call factoryname,$(1),$(2)); \ + fi; \ + fi + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2)-fat.uImage,0,$(KDIR)/root.$(1),$$$$(($(fwsize_fat)-4*64*1024)),$(KDIR_TMP)/$(2)-fat.bin,64) + if [ -e "$(KDIR_TMP)/$(2)-fat.bin" ]; then \ + echo -n "" > $(KDIR_TMP)/$(2)-fat.dummy; \ + sh $(TOPDIR)/scripts/combined-image.sh \ + "$(KDIR_TMP)/$(2)-fat.bin" \ + "$(KDIR_TMP)/$(2)-fat.dummy" \ + $(call sysupname,$(1),$(2)-fat); \ + fi +endef + +define Image/Build/WZRHP + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(3)-4*$(4)*1024)),$(4)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + echo -n -e "# Airstation Public Fmt1\x00\x00\x00\x00\x00\x00\x00\x00"; \ + dd if=$(call sysupname,$(1),$(2)); \ + ) > $(call imgname,$(1),$(2))-tftp.bin; \ + buffalo-enc -p $(5) -v 1.99 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(KDIR_TMP)/$(2).enc; \ + buffalo-tag -b $(5) -p $(5) -a ath -v 1.99 -m 1.01 -l mlang8 \ + -w 3 -c 0x80041000 -d 0x801e8000 -f 1 -r M_ \ + -i $(KDIR_TMP)/$(2).enc \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + +Image/Build/WZRHP64K/buildkernel=$(call MkuImageLzma,$(2),$(3)) +Image/Build/WZRHP64K/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) +Image/Build/WZRHP64K=$(call Image/Build/WZRHP,$(1),$(2),33095680,64,$(4)) + +Image/Build/WZRHP128K/buildkernel=$(call MkuImageLzma,$(2),$(3)) +Image/Build/WZRHP128K/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) +Image/Build/WZRHP128K=$(call Image/Build/WZRHP,$(1),$(2),33030144,128,$(4)) + + +Image/Build/WHRHPG300N/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/WHRHPG300N/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/WHRHPG300N + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + ( \ + echo -n -e "# Airstation Public Fmt1\x00\x00\x00\x00\x00\x00\x00\x00"; \ + dd if=$(call sysupname,$(1),$(2)); \ + ) > $(call imgname,$(1),$(2))-tftp.bin; \ + buffalo-enc -p $(5) -v 1.99 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(KDIR_TMP)/$(2).enc; \ + buffalo-tag -b $(5) -p $(5) -a ath -v 1.99 -m 1.01 -l mlang8 \ + -w 3 -c 0x80041000 -d 0x801e8000 -f 1 -r M_ \ + -i $(KDIR_TMP)/$(2).enc \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + + +define Image/Build/Cameo + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + factory_size=$$$$(($(fwsize) - $(6))); \ + ( \ + dd if=$(call sysupname,$(1),$(2)) bs=$$$${factory_size} conv=sync; \ + echo -n $(5); \ + ) > $(call factoryname,$(1),$(2)); \ + fi +endef + +Image/Build/CameoAP81/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap81_mtdlayout)) +Image/Build/CameoAP81=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_ap81_mtdlayout),$(4),65536) +Image/Build/CameoAP81/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap81_mtdlayout)) + +Image/Build/CameoAP91/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap91_mtdlayout)) +Image/Build/CameoAP91=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_ap91_mtdlayout),$(4),65536) +Image/Build/CameoAP91/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap91_mtdlayout)) + +Image/Build/CameoAP99/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap99_mtdlayout)) +Image/Build/CameoAP99=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_ap99_mtdlayout),$(4),65536) +Image/Build/CameoAP99/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap99_mtdlayout)) + +Image/Build/CameoAP123_4M/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap123_mtdlayout_4M)) +Image/Build/CameoAP123_4M=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_ap123_mtdlayout_4M),$(4),26) +Image/Build/CameoAP123_4M/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap123_mtdlayout_4M)) + +Image/Build/CameoAP135/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/CameoAP135=$(call Image/Build/Cameo,$(1),$(2),$(3),$(4),$(5),26) +Image/Build/CameoAP135/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +Image/Build/CameoDB120/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_db120_mtdlayout)) +Image/Build/CameoDB120=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_db120_mtdlayout),$(4),26) +Image/Build/CameoDB120/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_db120_mtdlayout)) + +Image/Build/CameoDB120_8M/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_db120_mtdlayout_8M)) +Image/Build/CameoDB120_8M=$(call Image/Build/Cameo,$(1),$(2),$(3),$(cameo_db120_mtdlayout_8M),$(4),26) +Image/Build/CameoDB120_8M/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_db120_mtdlayout_8M)) + +define Image/Build/CameoHornet + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + for r in $(7); do \ + [ -n "$$$$r" ] && dashr="-$$$$r" || dashr=; \ + [ -z "$$$$r" ] && r="DEF"; \ + mkcameofw -M HORNET -R "$$$$r" -S $(5) -V $(6) -c \ + -K $(8) -I $(fwsize) \ + -k "$(call sysupname,$(1),$(2))" \ + -o $(call imgname,$(1),$(2))-factory$$$$dashr.bin; \ + true; \ + done; \ + fi +endef + +Image/Build/CameoAP121/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap121_mtdlayout)) +Image/Build/CameoAP121=$(call Image/Build/CameoHornet,$(1),$(2),$(3),$(cameo_ap121_mtdlayout),$(4),$(5),$(6),0xe0000) +Image/Build/CameoAP121/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap121_mtdlayout)) + +Image/Build/CameoAP121_8M/buildkernel=$(call MkuImageLzma,$(2),$(3) $(cameo_ap121_mtdlayout_8M)) +Image/Build/CameoAP121_8M=$(call Image/Build/CameoHornet,$(1),$(2),$(3),$(cameo_ap121_mtdlayout_8M),$(4),$(5),$(6),0x100000) +Image/Build/CameoAP121_8M/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(cameo_ap121_mtdlayout_8M)) + +define Image/Build/dLAN + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval rootsize=$(call mtdpartsize,rootfs,$(4))) + $(eval kernsize=$(call mtdpartsize,kernel,$(4))) + $(call Sysupgrade/$(5),$(1),$(2),$(if $(6),$(6),$(kernsize)),$(if $(rootsize),$(rootsize),$(fwsize))) + if [ -e "$(call factoryname,$(1),$(2))" ]; then \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync; \ + fi +endef + +Image/Build/dLANLzma/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/dLANLzma=$(call Image/Build/dLAN,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +Image/Build/dLANLzma/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/Ath + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval rootsize=$(call mtdpartsize,rootfs,$(4))) + $(eval kernsize=$(call mtdpartsize,kernel,$(4))) + $(call Sysupgrade/$(5),$(1),$(2),$(if $(6),$(6),$(kernsize)),$(if $(rootsize),$(rootsize),$(fwsize))) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync; \ + fi +endef + +Image/Build/AthGzip/buildkernel=$(call MkuImageGzip,$(2),$(3) $(4)) +Image/Build/AthGzip=$(call Image/Build/Ath,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +Image/Build/AthGzip/initramfs=$(call MkuImageGzip/initramfs,$(2),$(3) $(4)) + +Image/Build/AthLzma/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/AthLzma=$(call Image/Build/Ath,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +Image/Build/AthLzma/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + + +Image/Build/Belkin/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/Belkin/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/Belkin + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval kernsize=$(call mtdpartsize,kernel,$(4))) + $(eval rootsize=$(call mtdpartsize,rootfs,$(4))) + $(call Sysupgrade/RKuImage,$(1),$(2),$(kernsize),$(rootsize)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + edimax_fw_header -m $(5) -v "OpenWrt$(REVISION)" \ + -n "uImage" \ + -i $(KDIR_TMP)/vmlinux-$(2).uImage \ + -o $(KDIR_TMP)/$(2)-uImage; \ + edimax_fw_header -m $(5) -v "OpenWrt$(REVISION)" \ + -n "rootfs" \ + -i $(KDIR)/root.$(1) \ + -o $(KDIR_TMP)/$(2)-rootfs; \ + ( \ + dd if=$(KDIR_TMP)/$(2)-rootfs; \ + dd if=$(KDIR_TMP)/$(2)-uImage; \ + ) > "$(call factoryname,$(1),$(2))"; \ + fi +endef + +define Image/Build/EnGenius + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(eval rootsize=$(call mtdpartsize,rootfs,$(4))) + $(eval kernsize=$(call mtdpartsize,kernel,$(4))) + $(call Sysupgrade/$(5),$(1),$(2),$(if $(6),$(6),$(kernsize)),$(if $(rootsize),$(rootsize),$(fwsize))) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync; \ + mksenaofw -e $(call sysupname,$(1),$(2)) \ + -o $(call imgname,$(1),$(2))-factory.dlf \ + -r 0x101 -p $(7) -t 2; \ + fi +endef + +Image/Build/EnGenius/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/EnGenius/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + + +define MkuImageHiWiFi + # Field ih_name needs to start with "tw150v1" + mkimage -A mips -O linux -T kernel -a 0x80060000 -C $(1) $(2) \ + -e 0x80060000 -n 'tw150v1 MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(3) $(4) +endef + +define MkuImageLzmaHiWiFi + $(call PatchKernelLzma,$(1),$(2),$(3),$(4)) + $(call MkuImageHiWiFi,lzma,$(5),$(KDIR_TMP)/vmlinux$(4)-$(1).bin.lzma,$(KDIR_TMP)/vmlinux$(4)-$(1).uImage) +endef + +Image/Build/HiWiFi/buildkernel=$(call MkuImageLzmaHiWiFi,$(2),$(3) $(4)) +Image/Build/HiWiFi=$(call Image/Build/Ath,$(1),$(2),$(3),$(4),$(5),$(6),$(7)) +Image/Build/HiWiFi/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +Image/Build/PB4X/buildkernel=$(call PatchKernelLzma,$(2),$(3)) + +define Image/Build/PB4X + dd if=$(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + of=$(call imgname,kernel,$(2)).bin bs=64k conv=sync + dd if=$(KDIR)/root.$(1) \ + of=$(call imgname,$(1),$(2)-rootfs).bin bs=128k conv=sync + -sh $(TOPDIR)/scripts/combined-image.sh \ + "$(call imgname,kernel,$(2)).bin" \ + "$(call imgname,$(1),$(2)-rootfs).bin" \ + $(call sysupname,$(1),$(2)) +endef + + +Image/Build/MyLoader/buildkernel=$(call PatchKernelLzma,$(2),$(3)) +Image/Build/MyLoader/initramfs=$(call PatchKernel/initramfs,$(2),$(3)) + +define Image/Build/MyLoader + $(eval fwsize=$(shell echo $$(($(4)-0x30000-4*64*1024)))) + $(eval fwimage=$(KDIR_TMP)/$(2)-$(5)-firmware.bin) + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).bin.lzma,65536,$(KDIR)/root.$(1),$(fwsize),$(fwimage)) + if [ -e "$(fwimage)" ]; then \ + $(STAGING_DIR_HOST)/bin/mkmylofw -B $(2) -s $(4) -v \ + -p0x00030000:0:al:0x80060000:firmware:$(fwimage) \ + $(call imgname,$(1),$(2))-$(5)-factory.img; \ + echo -n "" > $(KDIR_TMP)/empty.bin; \ + sh $(TOPDIR)/scripts/combined-image.sh \ + $(fwimage) $(KDIR_TMP)/empty.bin \ + $(call imgname,$(1),$(2))-$(5)-sysupgrade.bin; \ + fi +endef + +Image/Build/Planex/initramfs=$(call MkuImageGzip/initramfs,$(2),$(3) $(planex_mtdlayout)) +Image/Build/Planex/loader=$(call Image/BuildLoaderAlone,$(1),gz,$(2) $(planex_mtdlayout),0x52000,0) + +define Image/Build/Planex/buildkernel + [ -e "$(KDIR)/loader-$(2).gz" ] + $(call MkuImageOKLI,$(2)) + ( \ + dd if=$(KDIR)/loader-$(2).gz bs=8128 count=1 conv=sync; \ + dd if=$(KDIR_TMP)/vmlinux-$(2).okli; \ + ) > $(KDIR_TMP)/kernel-$(2).bin + $(call MkuImage,gzip,,$(KDIR_TMP)/kernel-$(2).bin,$(KDIR_TMP)/vmlinux-$(2).uImage) +endef + +define Image/Build/Planex + $(eval fwsize=$(call mtdpartsize,firmware,$(planex_mtdlayout))) + $(call Sysupgrade/KRuImage,$(1),$(2),0,$$$$(($(fwsize)-4*64*1024)),64) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + $(STAGING_DIR_HOST)/bin/mkplanexfw \ + -B $(2) \ + -v 2.00.00 \ + -i $(call sysupname,$(1),$(2)) \ + -o $(call factoryname,$(1),$(2)); \ + fi +endef + + +Image/Build/ALFA/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/ALFA/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/ALFA + $(call Sysupgrade/RKuImage,$(1),$(2),$(5),$(6)) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + rm -rf $(KDIR)/$(1); \ + mkdir -p $(KDIR)/$(1); \ + cd $(KDIR)/$(1); \ + cp $(KDIR_TMP)/vmlinux-$(2).uImage $(KDIR)/$(1)/$(7); \ + cp $(KDIR)/root.$(1) $(KDIR)/$(1)/$(8); \ + $(TAR) zcf $(call factoryname,$(1),$(2)) -C $(KDIR)/$(1) $(7) $(8); \ + ( \ + echo WRM7222C | dd bs=32 count=1 conv=sync; \ + echo -ne '\xfe'; \ + ) >> $(call factoryname,$(1),$(2)); \ + fi +endef + + +Image/Build/Seama/loader=$(call Image/BuildLoader,$(1),bin,$(2) $(3),0x80060000) + +define Image/Build/Seama + [ -e "$(KDIR)/loader-$(2).bin" ] + $(call CompressLzma,$(KDIR)/loader-$(2).bin,$(KDIR_TMP)/loader-$(2).bin.lzma) + -rm -f $(KDIR_TMP)/image-$(2).tmp + $(call CatFiles,$(KDIR_TMP)/loader-$(2).bin.lzma,$$$$(($(6) - 64)),$(KDIR)/root.$(1),$(7),$(KDIR_TMP)/image-$(2).tmp) + [ -e "$(KDIR_TMP)/image-$(2).tmp" ] && { \ + head -c -4 "$(KDIR_TMP)/image-$(2).tmp" > "$(KDIR_TMP)/image-$(2).no-jffs2mark.tmp"; \ + $(STAGING_DIR_HOST)/bin/seama \ + -i $(KDIR_TMP)/image-$(2).no-jffs2mark.tmp \ + -m "dev=/dev/mtdblock/1" -m "type=firmware"; \ + $(STAGING_DIR_HOST)/bin/seama \ + -s $(call imgname,$(1),$(2))-factory.bin \ + -m "signature=$(5)" \ + -i $(KDIR_TMP)/image-$(2).no-jffs2mark.tmp.seama; \ + tail -c 4 "$(KDIR_TMP)/image-$(2).tmp" >> $(call imgname,$(1),$(2))-factory.bin; \ + } + cat $(KDIR_TMP)/loader-$(2).bin.lzma > $(KDIR_TMP)/image-$(2)-sysupgrade.tmp + $(STAGING_DIR_HOST)/bin/seama \ + -i $(KDIR_TMP)/image-$(2)-sysupgrade.tmp \ + -m "dev=/dev/mtdblock/1" -m "type=firmware" + $(call CatFiles,$(KDIR_TMP)/image-$(2)-sysupgrade.tmp.seama,$(6),$(KDIR)/root.$(1),$(7),$(call sysupname,$(1),$(2))) +endef + +define Image/Build/Seama/initramfs + $(call PatchKernelLzma,$(2),$(3) $(4),,-initramfs) + $(STAGING_DIR_HOST)/bin/seama \ + -i $(KDIR_TMP)/vmlinux-initramfs-$(2).bin.lzma \ + -m "dev=/dev/mtdblock/1" -m "type=firmware" + cat $(KDIR_TMP)/vmlinux-initramfs-$(2).bin.lzma.seama > $(call imgname,initramfs,$(2))-seama.bin +endef + +Image/Build/Senao/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/Senao/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/Senao + mkdir -p $(KDIR_TMP)/$(2)/ + touch $(KDIR_TMP)/$(2)/FWINFO-OpenWrt-$(REVISION)-$(2) + -$(CP) ./$(2)/* $(KDIR_TMP)/$(2)/ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage \ + of=$(KDIR_TMP)/$(2)/openwrt-senao-$(2)-uImage-lzma.bin bs=64k conv=sync + dd if=$(KDIR)/root.$(1) \ + of=$(KDIR_TMP)/$(2)/openwrt-senao-$(2)-root.$(1) bs=64k conv=sync + ( \ + cd $(KDIR_TMP)/$(2)/; \ + $(TAR) -cz -f $(call factoryname,$(1),$(2)) * \ + ) + -rm -rf $(KDIR_TMP)/$(2)/ + -sh $(TOPDIR)/scripts/combined-image.sh \ + $(KDIR_TMP)/vmlinux-$(2).uImage \ + $(KDIR)/root.$(1) \ + $(call sysupname,$(1),$(2)) +endef + +Image/Build/TPLINK-SAFELOADER/loader = $(call Image/BuildLoaderPatched,$(1),elf,$(2) $(3)) + +define Image/Build/TPLINK-SAFELOADER + [ -e "$(KDIR)/loader-$(2).elf" ] + + -$(STAGING_DIR_HOST)/bin/tplink-safeloader \ + -B $(5) \ + -k $(KDIR)/loader-$(2).elf \ + -r $(KDIR)/root.$(1) \ + -V $(REVISION) \ + -j \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/tplink-safeloader \ + -B $(5) \ + -k $(KDIR)/loader-$(2).elf \ + -r $(KDIR)/root.$(1) \ + -V $(REVISION) \ + -j -S \ + -o $(call sysupname,$(1),$(2)) +endef + + +define Image/Build/CyberTAN + echo -n '' > $(KDIR_TMP)/empty.bin + $(STAGING_DIR_HOST)/bin/trx -o $(KDIR)/image.tmp \ + -f $(KDIR_TMP)/vmlinux-$(2).uImage -F $(KDIR_TMP)/empty.bin \ + -x 32 -a 0x10000 -x -32 -f $(KDIR)/root.$(1) + -$(STAGING_DIR_HOST)/bin/addpattern -B $(2) -v v$(5) \ + -i $(KDIR)/image.tmp \ + -o $(call sysupname,$(1),$(2)) + $(STAGING_DIR_HOST)/bin/trx -o $(KDIR)/image.tmp -f $(KDIR_TMP)/vmlinux-$(2).uImage \ + -x 32 -a 0x10000 -x -32 -f $(KDIR)/root.$(1) + -$(STAGING_DIR_HOST)/bin/addpattern -B $(2) -v v$(5) -g \ + -i $(KDIR)/image.tmp \ + -o $(call factoryname,$(1),$(2)) + rm $(KDIR)/image.tmp +endef + +Image/Build/CyberTANGZIP/loader=$(call Image/BuildLoader,$(1),gz,$(2),0x80060000) +Image/Build/CyberTANGZIP/buildkernel=$(call MkuImage,gzip,,$(KDIR)/loader-$(2).gz,$(KDIR_TMP)/vmlinux-$(2).uImage) +Image/Build/CyberTANGZIP=$(call Image/Build/CyberTAN,$(1),$(2),$(3),$(4),$(5)) + +Image/Build/CyberTANLZMA/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/CyberTANLZMA=$(call Image/Build/CyberTAN,$(1),$(2),$(3),$(4),$(5)) + + +Image/Build/Netgear/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4),,-M $(5)) + +define Image/Build/Netgear/buildkernel + $(call MkuImageLzma,$(2),$(3) $(4),-d20,,-M $(5)) + -rm -rf $(KDIR_TMP)/$(2) + mkdir -p $(KDIR_TMP)/$(2)/image + cat $(KDIR_TMP)/vmlinux-$(2).uImage > $(KDIR_TMP)/$(2)/image/uImage + $(STAGING_DIR_HOST)/bin/mksquashfs-lzma \ + $(KDIR_TMP)/$(2) $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs.tmp1 \ + -noappend -root-owned -be -b 65536 + ( \ + cat $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs.tmp1; \ + dd if=/dev/zero bs=1k count=1 \ + ) > $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs.tmp2 + mkimage -A mips -O linux -T filesystem -C none -M $(5) \ + -a 0xbf070000 -e 0xbf070000 \ + -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs.tmp2 \ + $(KDIR_TMP)/vmlinux-$(2).uImage.squashfs +endef + +define Image/Build/Netgear + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).uImage.squashfs,0,$(KDIR)/root.$(1),$(fwsize),$(call sysupname,$(1),$(2)),64) + if [ -e $(call sysupname,$(1),$(2)) ]; then \ + for r in $(7) ; do \ + [ -n "$$$$r" ] && dashr="-$$$$r" || dashr= ; \ + $(STAGING_DIR_HOST)/bin/mkdniimg \ + -B $(6) -v OpenWrt.$(REVISION) -r "$$$$r" $(8) \ + -i $(call sysupname,$(1),$(2)) \ + -o $(call imgname,$(1),$(2))-factory$$$$dashr.img; \ + done; \ + fi +endef + + +Image/Build/NetgearLzma/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4),,-M $(5)) +Image/Build/NetgearLzma/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4),-d20,,-M $(5)) + +define Image/Build/NetgearLzma + $(eval fwsize=$(call mtdpartsize,firmware,$(4))) + $(call CatFiles,$(KDIR_TMP)/vmlinux-$(2).uImage,0,$(KDIR)/root.$(1),$(fwsize),$(call sysupname,$(1),$(2)),64) +endef + + +Image/Build/NetgearNAND/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4),,-M $(5)) + +# $(1): (empty) +# $(2): Board name (small caps) +# $(3): Kernel board specific cmdline +# $(4): Kernel mtdparts definition +# $(5): U-Boot magic +define Image/Build/NetgearNAND/buildkernel + $(eval kernelsize=$(call mtdpartsize,kernel,$(4))) + $(call PatchKernelLzma,$(2),$(3) $(4),-d20) + dd if=$(KDIR_TMP)/vmlinux-$(2).bin.lzma \ + of=$(KDIR_TMP)/vmlinux-$(2).bin.tmp \ + bs=$$$$(($(kernelsize)-131072-2*64-1)) \ + count=1 conv=sync + $(call MkuImage,lzma,-M $(5),$(KDIR_TMP)/vmlinux-$(2).bin.tmp,$(KDIR_TMP)/vmlinux-$(2).uImage) + echo -ne '\xff' >> $(KDIR_TMP)/vmlinux-$(2).uImage + # create a fake rootfs image + dd if=/dev/zero of=$(KDIR_TMP)/fakeroot-$(2) bs=131072 count=1 + mkimage -A mips -O linux -T filesystem -C none \ + -a 0xbf070000 -e 0xbf070000 \ + -n 'MIPS OpenWrt fakeroot' \ + -d $(KDIR_TMP)/fakeroot-$(2) \ + -M $(5) \ + $(KDIR_TMP)/fakeroot-$(2).uImage + # append the fake rootfs image to the kernel, it will reside in the last + # erase block of the kernel partition + cat $(KDIR_TMP)/fakeroot-$(2).uImage >> $(KDIR_TMP)/vmlinux-$(2).uImage +endef + + +# $(1): rootfs image suffix +# $(2): Board name (small caps) +# $(3): Kernel board specific cmdline +# $(4): Kernel mtdparts definition +# $(5): U-Boot magic +# $(6): Board name (upper caps) +# $(7): firmware region code (not used yet) +# $(8): DNI Hardware version +# $(9): suffix of the configuration file for ubinize +define Image/Build/NetgearNAND + $(eval firmwaresize=$(call mtdpartsize,firmware,$(4))) + $(eval kernelsize=$(call mtdpartsize,kernel,$(4))) + $(eval imageraw=$(KDIR_TMP)/$(2)-raw.img) + $(CP) $(KDIR)/root.squashfs-raw $(KDIR_TMP)/root.squashfs + echo -ne '\xde\xad\xc0\xde' > $(KDIR_TMP)/jffs2.eof + $(call ubinize,ubinize-$(9).ini,$(KDIR_TMP),$(KDIR_TMP)/$(2)-root.ubi,128KiB,2048,-E 5) + ( \ + dd if=$(KDIR_TMP)/vmlinux-$(2).uImage; \ + dd if=$(KDIR_TMP)/$(2)-root.ubi \ + ) > $(imageraw) + $(STAGING_DIR_HOST)/bin/mkdniimg \ + -B $(6) -v OpenWrt.$(REVISION) -r "$$$$r" $(8) \ + -i $(imageraw) \ + -o $(call imgname,ubi,$(2))-factory.img + + $(call Image/Build/SysupgradeNAND,$(2),squashfs,$(KDIR_TMP)/vmlinux-$(2).uImage) +endef + + +ifdef CONFIG_PACKAGE_uboot-ar71xx-nbg460n_550n_550nh + Image/Build/ZyXEL/buildkernel=$(call MkuImageLzma,$(2),$(3)) + + define Image/Build/ZyXEL + $(call Sysupgrade/KRuImage,$(1),$(2),917504,2752512) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + if [ ! -f $(BIN_DIR)/$(IMG_PREFIX)-$(2)-u-boot.bin ]; then \ + echo "Warning: $(IMG_PREFIX)-$(2)-u-boot.bin not found" >&2; \ + else \ + $(STAGING_DIR_HOST)/bin/mkzynfw \ + -B $(4) \ + -b $(BIN_DIR)/$(IMG_PREFIX)-$(2)-u-boot.bin \ + -r $(call sysupname,$(1),$(2)):0x10000 \ + -o $(call factoryname,$(1),$(2)); \ + fi; fi + endef +endif + + +define Image/Build/ZyXELNAND/buildkernel + $(eval kernelsize=$(call mtdpartsize,kernel,$(5))) + $(call MkuImageLzma,$(2),$(3) $(5) $(6)) + mkdir -p $(KDIR_TMP)/$(2)/image/boot + cp $(KDIR_TMP)/vmlinux-$(2).uImage $(KDIR_TMP)/$(2)/image/boot/vmlinux.lzma.uImage + $(STAGING_DIR_HOST)/bin/mkfs.jffs2 \ + --pad=$(kernelsize) --big-endian --squash-uids -v -e 128KiB \ + -o $(KDIR_TMP)/$(2)-kernel.jffs2 \ + -d $(KDIR_TMP)/$(2)/image \ + 2>&1 1>/dev/null | awk '/^.+$$$$/' + -rm -rf $(KDIR_TMP)/$(2) +endef + +define Image/Build/ZyXELNAND + if [ "$(1)" != "squashfs" ]; then \ + echo Only squashfs is supported; \ + return 0; \ + fi + $(eval firmwaresize=$(call mtdpartsize,firmware,$(4))) + $(eval kernelsize=$(call mtdpartsize,kernel,$(4))) + $(eval imageraw=$(KDIR_TMP)/$(2)-raw.img) + $(CP) $(KDIR)/root.$(1) $(KDIR_TMP)/ubi_root.img + $(call ubinize,ubinize-$(2).ini,$(KDIR_TMP),$(KDIR_TMP)/$(2)-root.ubi,128KiB,2048,-E 5) + ( \ + dd if=$(KDIR_TMP)/$(2)-kernel.jffs2; \ + dd if=$(KDIR_TMP)/$(2)-root.ubi \ + ) > $(imageraw) + dd if=$(imageraw) of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory.bin \ + bs=128k conv=sync + $(call Image/Build/SysupgradeNAND,$(2),squashfs,$(KDIR_TMP)/$(2)-kernel.jffs2) +endef + + +Image/Build/OpenMesh/buildkernel=$(call MkuImageLzma,$(2)) + +define Image/Build/OpenMesh + -sh $(TOPDIR)/scripts/om-fwupgradecfg-gen.sh \ + "$(4)" \ + "$(BUILD_DIR)/fwupgrade.cfg-$(4)" \ + "$(KDIR_TMP)/vmlinux-$(2).uImage" \ + "$(KDIR)/root.$(1)" + -sh $(TOPDIR)/scripts/combined-ext-image.sh \ + "$(4)" "$(call factoryname,$(1),$(2))" \ + "$(BUILD_DIR)/fwupgrade.cfg-$(4)" "fwupgrade.cfg" \ + "$(KDIR_TMP)/vmlinux-$(2).uImage" "kernel" \ + "$(KDIR)/root.$(1)" "rootfs" +endef + + +Image/Build/Zcomax/buildkernel=$(call MkuImageLzma,$(2),$(3) $(4)) +Image/Build/Zcomax/initramfs=$(call MkuImageLzma/initramfs,$(2),$(3) $(4)) + +define Image/Build/Zcomax + $(call Sysupgrade/RKuImage,$(1),$(2),1507328,6356992) + if [ -e "$(call sysupname,$(1),$(2))" ]; then \ + $(STAGING_DIR_HOST)/bin/mkzcfw \ + -B $(2) \ + -k $(KDIR_TMP)/vmlinux-$(2).uImage \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(call imgname,$(1),$(2))-factory.img; \ + fi +endef + + +# $(1): template name to be defined, etc. squashfs-only, 64k, 64kraw, etc. +# $(2): jffs2 blocksize. +define Jffs2Template + define Image/Build/Template/$(1)/jffs2-$(2) + $$(call Image/Build/$$(1),jffs2-$(2),$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef +endef + +# $(1): template name to be defined. +# $(2): squashfs suffix to be used. +# $(3): jffs2 suffix to be used. +define BuildTemplate + # $(1) : name of build method. + # $(2) : board name. + # $(3) : kernel command line. + # $(4)~$(8): extra arguments. + define Image/Build/Template/$(1)/initramfs + $$(call Image/Build/$$(1)/initramfs,initramfs,$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef + define Image/Build/Template/$(1)/loader + $$(call Image/Build/$$(1)/loader,$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef + define Image/Build/Template/$(1)/buildkernel + $$(call Image/Build/$$(1)/buildkernel,,$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef + define Image/Build/Template/$(1)/squashfs + $$(call Image/Build/$$(1),squashfs$(2),$$(2),$$(3),$$(4),$$(5),$$(6),$$(7),$$(8),$$(9),$$(10)) + endef + $(if $(3),$(foreach bs,$(3),$(eval $(call Jffs2Template,$(1),$(bs))))) +endef + +$(eval $(call BuildTemplate,squashfs-only)) +$(eval $(call BuildTemplate,64k,-64k,64k)) +$(eval $(call BuildTemplate,64kraw,-raw,64k)) +$(eval $(call BuildTemplate,64kraw-nojffs,-raw)) +$(eval $(call BuildTemplate,128k,,128k)) +$(eval $(call BuildTemplate,128kraw,-raw,128k)) +$(eval $(call BuildTemplate,256k,,256k)) +$(eval $(call BuildTemplate,all,,64k 128k 256k)) + +ifeq ($(SUBTARGET),generic) +$(eval $(call SingleProfile,ALFA,64k,ALFANX,alfa-nx,ALFA-NX,ttyS0,115200,$$(alfa_mtdlayout_8M),1638400,6291456,vmlinux.gz.uImage,pb9x-2.6.31-jffs2)) +$(eval $(call SingleProfile,ALFA,64k,HORNETUB,hornet-ub,HORNET-UB,ttyATH0,115200,$$(alfa_mtdlayout_8M),1638400,6291456,kernel_image,rootfs_image)) +$(eval $(call SingleProfile,ALFA,64k,TUBE2H8M,tube2h-8M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_8M),1638400,6291456,kernel.image,rootfs.image)) + +$(eval $(call SingleProfile,AthGzip,64k,AP81,ap81,AP81,ttyS0,115200,$$(ap81_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthGzip,64k,AP83,ap83,AP83,ttyS0,115200,$$(ap83_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthGzip,64k,AP96,ap96,AP96,ttyS0,115200,$$(ap96_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthGzip,64k,WNDAP360,wndap360,WNDAP360,ttyS0,9600,$$(wndap360_mtdlayout),KRuImage)) + +$(eval $(call SingleProfile,AthLzma,64k,ALFAAP96,alfa-ap96,ALFA-AP96,ttyS0,115200,$$(alfa_ap96_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,ALL0258N,all0258n,ALL0258N,ttyS0,115200,$$(all0258n_mtdlayout),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,256k,ALL0315N,all0315n,ALL0315N,ttyS0,115200,$$(all0315n_mtdlayout),KRuImage,262144)) +$(eval $(call SingleProfile,AthLzma,64k,AP113,ap113,AP113,ttyS0,115200,$$(ap113_mtd_layout),RK)) +$(eval $(call SingleProfile,AthLzma,64k,AP121_2M,ap121-2M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_2M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP121_4M,ap121-4M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_4M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP121_8M,ap121-8M,AP121,ttyATH0,115200,$$(ap121_mtdlayout_8M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP121MINI,ap121-mini,AP121-MINI,ttyATH0,115200,$$(ap121_mtdlayout_4M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP132,ap132,AP132,ttyS0,115200,$$(ap132_mtdlayout),KRuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP135,ap135-020,AP135-020,ttyS0,115200,$$(ap135_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP136_010,ap136-010,AP136-010,ttyS0,115200,$$(ap136_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP136_020,ap136-020,AP136-020,ttyS0,115200,$$(ap136_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP143_8M,ap143-8M,AP143,ttyS0,115200,$$(ap143_mtdlayout_8M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP143_16M,ap143-16M,AP143,ttyS0,115200,$$(ap143_mtdlayout_16M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP147_010,ap147-010,AP147-010,ttyS0,115200,$$(ap147_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,AP152_16M,ap152-16M,AP152,ttyS0,115200,$$(ap152_mtdlayout_16M),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,BXU2000N2,bxu2000n-2-a1,BXU2000n-2-A1,ttyS0,115200,$$(bxu2000n2_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,CAP4200AG,cap4200ag,CAP4200AG,ttyS0,115200,$$(cap4200ag_mtdlayout),KRuImage)) +$(eval $(call SingleProfile,AthLzma,64k,DB120,db120,DB120,ttyS0,115200,$$(db120_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,DRAGINO2,dragino2,DRAGINO2,ttyATH0,115200,$$(dragino2_mtdlayout),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,EWDORINAP,ew-dorin,EW-DORIN,ttyATH0,115200,$$(ew-dorin_mtdlayout_4M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,EWDORINRT,ew-dorin-router,EW-DORIN-ROUTER,ttyATH0,115200,$$(ew-dorin_mtdlayout_4M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,EWDORIN16M,ew-dorin-16M,EW-DORIN,ttyATH0,115200,$$(ew-dorin_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,HORNETUBx2,hornet-ub-x2,HORNET-UB,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,MR12,mr12,MR12,ttyS0,115200,$$(mr12_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,MR16,mr16,MR16,ttyS0,115200,$$(mr16_mtdlayout),RKuImage)) +$(eval $(call SingleProfile,AthLzma,64k,PB92,pb92,PB92,ttyS0,115200,$$(pb92_mtdlayout),KRuImage)) +$(eval $(call SingleProfile,AthLzma,64k,TUBE2H16M,tube2h-16M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,WLR8100,wlr8100,WLR8100,ttyS0,115200,$$(wlr8100_mtdlayout),KRuImage)) +$(eval $(call SingleProfile,AthLzma,64k,WPJ344_16M,wpj344-16M,WPJ344,ttyS0,115200,$$(wpj344_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,WPJ531_16M,wpj531-16M,WPJ531,ttyS0,115200,$$(wpj531_mtdlayout_16M),KRuImage,65536)) +$(eval $(call SingleProfile,AthLzma,64k,WPJ558_16M,wpj558-16M,WPJ558,ttyS0,115200,$$(wpj558_mtdlayout_16M),KRuImage,65536)) + +$(eval $(call SingleProfile,Belkin,64k,F9K1115V2,f9k1115v2,F9K1115V2,ttyS0,115200,$$(f9k1115v2_mtdlayout),BR-6679BAC)) + +$(eval $(call SingleProfile,CameoAP91,64kraw,DIR600A1,dir-600-a1,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-00")) +$(eval $(call SingleProfile,CameoAP91,64kraw,DIR601A1,dir-601-a1,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-02")) +$(eval $(call SingleProfile,CameoAP91,64kraw,FR54RTR,fr-54rtr,DIR-600-A1,ttyS0,115200,"AP91-AR7240-RT-090223-01")) + +$(eval $(call SingleProfile,CameoAP99,64kraw,DIR615E1,dir-615-e1,DIR-615-E1,ttyS0,115200,"AP93-AR7240-RT-081028-00")) +$(eval $(call SingleProfile,CameoAP99,64kraw,DIR615E4,dir-615-e4,DIR-615-E4,ttyS0,115200,"AP99-AR7240-RT-091105-05")) + +$(eval $(call SingleProfile,CameoAP123_4M,64kraw,DIR615I1,dir-615-i1,DIR-615-I1,ttyS0,115200,"00DB120AR9341-RT-1012I1-00")) +$(eval $(call SingleProfile,CameoAP123_4M,64kraw,DIR615I3,dir-615-i3,DIR-615-I1,ttyS0,115200,"00DB120AR9341-RT-101214-00")) + +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,A02RBW300N,a02-rb-w300n,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-03")) +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,DIR615C1,dir-615-c1,DIR-615-C1,ttyS0,115200,"AP81-AR9130-RT-070614-02")) +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,TEW632BRP,tew-632brp,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-00")) +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,TEW652BRP_FW,tew-652brp,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-080609-05")) +$(eval $(call SingleProfile,CameoAP81,64kraw-nojffs,TEW652BRP_RECOVERY,tew-652brp-recovery,TEW-632BRP,ttyS0,115200,"AP81-AR9130-RT-070614-02")) + +$(eval $(call SingleProfile,CameoAP121,64kraw-nojffs,TEW712BR,tew-712br,TEW-712BR,ttyATH0,115200,"HORNET-RT-TEW712BR-3",1.99,"")) +$(eval $(call SingleProfile,CameoAP121,64kraw-nojffs,DIR601B1,dir-601-b1,TEW-712BR,ttyATH0,115200,"HORNET-RT-DIR601B1-3",2.99.99,"" "NA")) +$(eval $(call SingleProfile,CameoAP121_8M,64kraw-nojffs,DIR505A1,dir-505-a1,DIR-505-A1,ttyATH0,115200,"HORNET-PACKET-DIR505A1-3",1.99.99,"")) + +$(eval $(call SingleProfile,CameoAP135,64kraw,DGL5500A1,dgl-5500-a1,DGL-5500-A1,ttyS0,115200,$$(dgl_5500_mtdlayout),"00AP135AR9558-RT-130508-00")) + +$(eval $(call SingleProfile,CameoDB120,64kraw,DHP1565A1,dhp-1565-a1,DHP-1565-A1,ttyS0,115200,"00DB120AR9344-RT-101214-00")) +$(eval $(call SingleProfile,CameoDB120,64kraw,DIR825C1,dir-825-c1,DIR-825-C1,ttyS0,115200,"00DB120AR9344-RT-101214-00")) +$(eval $(call SingleProfile,CameoDB120,64kraw,DIR835A1,dir-835-a1,DIR-835-A1,ttyS0,115200,"00DB120AR9344-RT-101214-00")) + +$(eval $(call SingleProfile,CameoDB120_8M,64kraw,TEW732BR,tew-732br,TEW-732BR,ttyS0,115200,"00DB120AR9341-RT-120906-NA")) + +$(eval $(call SingleProfile,CyberTANGZIP,64k,WRT160NL,wrt160nl,WRT160NL,ttyS0,115200,,1.00.01)) + +$(eval $(call SingleProfile,CyberTANLZMA,64k,MYNETREXT,mynet-rext,MYNET-REXT,ttyS0,115200,$$(mynet_rext_mtdlayout) root=31:2,1.00.01)) + +$(eval $(call SingleProfile,CameoAP94,64kraw,DIR825B1,dir-825-b1,DIR-825-B1,ttyS0,115200,$$(cameo_ap94_mtdlayout),$$(cameo_ap94_mtdlayout_fat),01AP94-AR7161-RT-080619-00,00AP94-AR7161-RT-080619-00)) +$(eval $(call SingleProfile,CameoAP94,64kraw,TEW673GRU,tew-673gru,TEW-673GRU,ttyS0,115200,$$(cameo_ap94_mtdlayout),$$(cameo_ap94_mtdlayout_fat),01AP94-AR7161-RT-080619-01,00AP94-AR7161-RT-080619-01)) +$(eval $(call SingleProfile,CameoAP94,64kraw,DLRTDEV01,dlrtdev01,DIR-825-B1,ttyS0,115200,$$(dlrtdev_mtdlayout),$$(dlrtdev_mtdlayout_fat),01AP94-AR7161-RT-080619-00,00AP94-AR7161-RT-080619-00)) + +$(eval $(call SingleProfile,dLANLzma,64k,dLAN_pro_500_wp,dlan-pro-500-wp,dLAN-pro-500-wp,ttyS0,115200,$$(dlan_pro_500_wp_mtdlayout) mem=128M,KRuImage,64k)) +$(eval $(call SingleProfile,dLANLzma,64k,dLAN_pro_1200_ac,dlan-pro-1200-ac,dLAN-pro-1200-ac,ttyS0,115200,$$(dlan_pro_1200_ac_mtdlayout) mem=128M,KRuImage,64k)) + +$(eval $(call SingleProfile,EnGenius,64k,ESR900,esr900,ESR900,ttyS0,115200,$$(esr900_mtdlayout),KRuImage,,0x4e)) +$(eval $(call SingleProfile,EnGenius,64k,ESR1750,esr1750,ESR1750,ttyS0,115200,$$(esr1750_mtdlayout),KRuImage,,0x61)) +$(eval $(call SingleProfile,EnGenius,64k,EPG5000,epg5000,EPG5000,ttyS0,115200,$$(epg5000_mtdlayout),KRuImage,,0x71)) + +$(eval $(call SingleProfile,HiWiFi,64k,HIWIFI_HC6361,hiwifi-hc6361,HiWiFi-HC6361,ttyATH0,115200,$$(hiwifi_hc6361_mtdlayout),KRuImage)) + +$(eval $(call SingleProfile,MyLoader,64k,WP543_2M,wp543,,ttyS0,115200,0x200000,2M)) +$(eval $(call SingleProfile,MyLoader,64k,WP543_4M,wp543,,ttyS0,115200,0x400000,4M)) +$(eval $(call SingleProfile,MyLoader,64k,WP543_8M,wp543,,ttyS0,115200,0x800000,8M)) +$(eval $(call SingleProfile,MyLoader,64k,WP543_16M,wp543,,ttyS0,115200,0x1000000,16M)) +$(eval $(call SingleProfile,MyLoader,64k,WPE72_4M,wpe72,,ttyS0,115200,0x400000,4M)) +$(eval $(call SingleProfile,MyLoader,64k,WPE72_8M,wpe72,,ttyS0,115200,0x800000,8M)) +$(eval $(call SingleProfile,MyLoader,64k,WPE72_16M,wpe72,,ttyS0,115200,0x1000000,16M)) + +$(eval $(call SingleProfile,Netgear,64kraw,WNR2000V3,wnr2000v3,WNR2000V3,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x32303033,WNR2000V3,"" NA,-H 29763551+04+32)) +$(eval $(call SingleProfile,NetgearLzma,64kraw,WNR2000V4,wnr2000v4,WNR2000V4,ttyS0,115200,$$(wnr2000v4_mtdlayout),0x32303034,WNR2000V4,"" NA,)) +$(eval $(call SingleProfile,Netgear,64kraw,WNR2200,wnr2200,WNR2200,ttyS0,115200,$$(wnr2200_mtdlayout),0x32323030,WNR2200,"" NA,)) +$(eval $(call SingleProfile,Netgear,64kraw,REALWNR612V2,wnr612v2,WNR612V2,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x32303631,WNR612V2,"",)) +$(eval $(call SingleProfile,Netgear,64kraw,N150R,n150r,WNR612V2,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x32303631,N150R,"",)) +$(eval $(call SingleProfile,Netgear,64kraw,REALWNR1000V2,wnr1000v2,WNR1000V2,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x31303031,WNR1000V2,"",)) +$(eval $(call SingleProfile,Netgear,64kraw,WNR1000V2_VC,wnr1000v2-vc,WNR1000V2,ttyS0,115200,$$(wnr2000v3_mtdlayout),0x31303030,WNR1000V2-VC,"",)) + +$(eval $(call SingleProfile,OpenMesh,squashfs-only,OM2P,om2p,,,,OM2P)) +$(eval $(call SingleProfile,OpenMesh,squashfs-only,OM5P,om5p,,,,OM5P)) +$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR600,mr600,,,,MR600)) +$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR900,mr900,,,,MR900)) +$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR1750,mr1750,,,,MR1750)) + +$(eval $(call SingleProfile,PB4X,128k,ALL0305,all0305,ALL0305,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,128k,EAP7660D,eap7660d,EAP7660D,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,JA76PF,ja76pf,JA76PF,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,JA76PF2,ja76pf2,JA76PF2,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,JWAP003,jwap003,JWAP003,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,PB42,pb42,PB42,ttyS0,115200)) +$(eval $(call SingleProfile,PB4X,64k,PB44,pb44,PB44,ttyS0,115200)) + +$(eval $(call SingleProfile,Planex,64kraw,MZKW04NU,mzk-w04nu,MZK-W04NU,ttyS0,115200)) +$(eval $(call SingleProfile,Planex,64kraw,MZKW300NH,mzk-w300nh,MZK-W300NH,ttyS0,115200)) + +$(eval $(call SingleProfile,Seama,64k,MYNETN600,mynet-n600,MYNET-N600,ttyS0,115200,$$(mynet_n600_mtdlayout),wrgnd16_wd_db600,65536,16187392)) +$(eval $(call SingleProfile,Seama,64k,MYNETN750,mynet-n750,MYNET-N750,ttyS0,115200,$$(mynet_n600_mtdlayout),wrgnd13_wd_av,65536,16187392)) + +$(eval $(call SingleProfile,Seama,64k,QIHOO360,qihoo-c301,QIHOO-C301,ttyS0,115200,$$(qihoo_c301_mtdlayout),wrgac26_qihoo360_360rg,65536,16121856)) + +$(eval $(call SingleProfile,Senao,squashfs-only,EAP300V2,eap300v2,EAP300V2,ttyS0,115200,$$(eap300v2_mtdlayout))) + +$(eval $(call SingleProfile,TPLINK-SAFELOADER,64kraw,CPE510,cpe210-220-510-520,CPE510,ttyS0,115200,$$(cpe510_mtdlayout),CPE510)) + +$(eval $(call SingleProfile,WHRHPG300N,64kraw,WHRG301N,whr-g301n,WHR-G301N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-G301N)) +$(eval $(call SingleProfile,WHRHPG300N,64kraw,WHRHPG300N,whr-hp-g300n,WHR-HP-G300N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-HP-G300N)) +$(eval $(call SingleProfile,WHRHPG300N,64kraw,WHRHPGN,whr-hp-gn,WHR-HP-GN,ttyS0,115200,$$(whrhpg300n_mtdlayout),WHR-HP-GN)) +$(eval $(call SingleProfile,WHRHPG300N,64kraw,WLAEAG300N,wlae-ag300n,WLAE-AG300N,ttyS0,115200,$$(whrhpg300n_mtdlayout),WLAE-AG300N)) + +$(eval $(call SingleProfile,WRT400N,64k,WRT400N,wrt400n,WRT400N,ttyS0,115200)) + +$(eval $(call SingleProfile,WZRHP128K,128kraw,WZRHPG300NH,wzr-hp-g300nh,WZR-HP-G300NH,ttyS0,115200,WZR-HP-G300NH)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZRHPG300NH2,wzr-hp-g300nh2,WZR-HP-G300NH2,ttyS0,115200,WZR-HP-G300NH2)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZRHPAG300H,wzr-hp-ag300h,WZR-HP-AG300H,ttyS0,115200,WZR-HP-AG300H)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZRHPG450H,wzr-hp-g450h,WZR-HP-G450H,ttyS0,115200,WZR-HP-AG450H)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZR600DHP,wzr-600dhp,WZR-HP-AG300H,ttyS0,115200,WZR-600DHP)) +$(eval $(call SingleProfile,WZRHP64K,64kraw,WZR450HP2,wzr-450hp2,WZR-450HP2,ttyS0,115200,WZR-450HP2)) + +$(eval $(call SingleProfile,Zcomax,64k,ZCN1523H28,zcn-1523h-2-8,ZCN-1523H-2,ttyS0,115200,$$(zcn1523h_mtdlayout))) +$(eval $(call SingleProfile,Zcomax,64k,ZCN1523H516,zcn-1523h-5-16,ZCN-1523H-5,ttyS0,115200,$$(zcn1523h_mtdlayout))) + +$(eval $(call SingleProfile,ZyXEL,64k,NBG_460N_550N_550NH,nbg460n_550n_550nh,NBG460N,ttyS0,115200,NBG-460N)) + +$(eval $(call MultiProfile,AP121,AP121_2M AP121_4M AP121_8M)) +$(eval $(call MultiProfile,AP136,AP136_010 AP136_020)) +$(eval $(call MultiProfile,AP143,AP143_8M AP143_16M)) +$(eval $(call MultiProfile,AP147,AP147_010)) +$(eval $(call MultiProfile,AP152,AP152_16M)) +$(eval $(call MultiProfile,DIR615IX,DIR615I1 DIR615I3)) +$(eval $(call MultiProfile,EWDORIN, EWDORINAP EWDORINRT EWDORIN16M)) +$(eval $(call MultiProfile,OPENMESH,OM2P OM5P MR600 MR900 MR1750)) +$(eval $(call MultiProfile,TEW652BRP,TEW652BRP_FW TEW652BRP_RECOVERY)) +$(eval $(call MultiProfile,TUBE2H,TUBE2H8M TUBE2H16M)) +$(eval $(call MultiProfile,WNR612V2,REALWNR612V2 N150R)) +$(eval $(call MultiProfile,WNR1000V2,REALWNR1000V2 WNR1000V2_VC)) +$(eval $(call MultiProfile,WP543,WP543_2M WP543_4M WP543_8M WP543_16M)) +$(eval $(call MultiProfile,WPE72,WPE72_4M WPE72_8M WPE72_16M)) +$(eval $(call MultiProfile,WPJ344,WPJ344_16M)) +$(eval $(call MultiProfile,WPJ531,WPJ531_16M)) +$(eval $(call MultiProfile,WPJ558,WPJ558_16M)) + +$(eval $(call MultiProfile,Minimal,$(SINGLE_PROFILES))) +$(eval $(call MultiProfile,Madwifi,EAP7660D WP543)) +endif # ifeq ($(SUBTARGET),generic) + +ifeq ($(SUBTARGET),nand) +$(eval $(call SingleProfile,NetgearNAND,64k,WNDR3700V4,wndr3700v4,WNDR3700_V4,ttyS0,115200,$$(wndr4300_mtdlayout),0x33373033,WNDR3700v4,"",-H 29763948+128+128,wndr4300)) +$(eval $(call SingleProfile,NetgearNAND,64k,WNDR4300V1,wndr4300,WNDR4300,ttyS0,115200,$$(wndr4300_mtdlayout),0x33373033,WNDR4300,"",-H 29763948+0+128+128+2x2+3x3,wndr4300)) +$(eval $(call SingleProfile,NetgearNAND,64k,R6100,r6100,R6100,ttyS0,115200,$$(r6100_mtdlayout),0x36303030,R6100,"",-H 29764434+0+128+128+2x2+2x2,wndr4300)) + +$(eval $(call SingleProfile,ZyXELNAND,128k,NBG6716,nbg6716,NBG6716,ttyS0,115200,NBG6716,$$(zyx_nbg6716_mtdlayout),mem=256M)) + +$(eval $(call MultiProfile,WNDR4300,WNDR3700V4 WNDR4300V1)) +endif # ifeq ($(SUBTARGET),nand) + + +$(eval $(call MultiProfile,Default,$(SINGLE_PROFILES))) + +define Image/Build/squashfs + cp $(KDIR)/root.squashfs $(KDIR)/root.squashfs-raw + cp $(KDIR)/root.squashfs $(KDIR)/root.squashfs-64k + $(STAGING_DIR_HOST)/bin/padjffs2 $(KDIR)/root.squashfs-64k 64 + cp $(KDIR)/root.squashfs-64k $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs-64k + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +define Image/Build/jffs2 + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +define Image/Build/Initramfs + $(call Image/Build/Profile/$(IMAGE_PROFILE),initramfs) +endef + +define Image/Prepare + gzip -9n -c $(KDIR)/vmlinux > $(KDIR)/vmlinux.bin.gz + $(call CompressLzma,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.lzma) +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + gzip -9n -c $(KDIR)/vmlinux-initramfs > $(KDIR)/vmlinux-initramfs.bin.gz + $(call CompressLzma,$(KDIR)/vmlinux-initramfs,$(KDIR)/vmlinux-initramfs.bin.lzma) + $(call Image/BuildLoader,generic,elf,,,-initramfs) +endif + $(call Image/BuildLoader,generic,elf) + $(call Image/Build/Profile/$(if $(CONFIG_IB),Default,$(IMAGE_PROFILE)),loader) +endef + +# $(1): filesystem type. +define Image/Build + $(call Image/Build/$(call rootfs_type,$(1)),$(1)) + $(call Image/Build/Profile/$(IMAGE_PROFILE),$(1)) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/ar71xx/image/lzma-loader/Makefile b/target/linux/ar71xx/image/lzma-loader/Makefile new file mode 100644 index 0000000..2e0b911 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/Makefile @@ -0,0 +1,64 @@ +# +# Copyright (C) 2011 OpenWrt.org +# Copyright (C) 2011 Gabor Juhos +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +LZMA_TEXT_START := 0x80a00000 +LOADER := loader.bin +LOADER_NAME := $(basename $(notdir $(LOADER))) +LOADER_DATA := +TARGET_DIR := +FLASH_OFFS := +FLASH_MAX := +BOARD := + +ifeq ($(TARGET_DIR),) +TARGET_DIR := $(KDIR) +endif + +LOADER_BIN := $(TARGET_DIR)/$(LOADER_NAME).bin +LOADER_GZ := $(TARGET_DIR)/$(LOADER_NAME).gz +LOADER_ELF := $(TARGET_DIR)/$(LOADER_NAME).elf + +PKG_NAME := lzma-loader +PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME) + +.PHONY : loader-compile loader.bin loader.elf loader.gz + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +loader-compile: $(PKG_BUILD_DIR)/.prepared + $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \ + LZMA_TEXT_START=$(LZMA_TEXT_START) \ + LOADER_DATA=$(LOADER_DATA) \ + FLASH_OFFS=$(FLASH_OFFS) \ + FLASH_MAX=$(FLASH_MAX) \ + BOARD="$(BOARD)" \ + clean all + +loader.gz: $(PKG_BUILD_DIR)/loader.bin + gzip -nc9 $< > $(LOADER_GZ) + +loader.elf: $(PKG_BUILD_DIR)/loader.elf + $(CP) $< $(LOADER_ELF) + +loader.bin: $(PKG_BUILD_DIR)/loader.bin + $(CP) $< $(LOADER_BIN) + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: loader-compile + +install: + +clean: + rm -rf $(PKG_BUILD_DIR) + diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 0000000..cb83453 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,584 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \ + BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + return LZMA_RESULT_DATA_ERROR; + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 0000000..2870eeb --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,113 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +#include "LzmaTypes.h" + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb UInt16 +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h b/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h new file mode 100644 index 0000000..9c27290 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/LzmaTypes.h @@ -0,0 +1,45 @@ +/* +LzmaTypes.h + +Types for LZMA Decoder + +This file written and distributed to public domain by Igor Pavlov. +This file is part of LZMA SDK 4.40 (2006-05-01) +*/ + +#ifndef __LZMATYPES_H +#define __LZMATYPES_H + +#ifndef _7ZIP_BYTE_DEFINED +#define _7ZIP_BYTE_DEFINED +typedef unsigned char Byte; +#endif + +#ifndef _7ZIP_UINT16_DEFINED +#define _7ZIP_UINT16_DEFINED +typedef unsigned short UInt16; +#endif + +#ifndef _7ZIP_UINT32_DEFINED +#define _7ZIP_UINT32_DEFINED +#ifdef _LZMA_UINT32_IS_ULONG +typedef unsigned long UInt32; +#else +typedef unsigned int UInt32; +#endif +#endif + +/* #define _LZMA_NO_SYSTEM_SIZE_T */ +/* You can use it, if you don't want */ + +#ifndef _7ZIP_SIZET_DEFINED +#define _7ZIP_SIZET_DEFINED +#ifdef _LZMA_NO_SYSTEM_SIZE_T +typedef UInt32 SizeT; +#else +#include +typedef size_t SizeT; +#endif +#endif + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/Makefile b/target/linux/ar71xx/image/lzma-loader/src/Makefile new file mode 100644 index 0000000..5f10bdb --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/Makefile @@ -0,0 +1,106 @@ +# +# Makefile for the LZMA compressed kernel loader for +# Atheros AR7XXX/AR9XXX based boards +# +# Copyright (C) 2011 Gabor Juhos +# +# Some parts of this file was based on the OpenWrt specific lzma-loader +# for the BCM47xx and ADM5120 based boards: +# Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) +# Copyright (C) 2005 Mineharu Takahara +# Copyright (C) 2005 by Oleg I. Vdovikin +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. +# + +LOADADDR := +LZMA_TEXT_START := 0x80a00000 +LOADER_DATA := +BOARD := +FLASH_OFFS := +FLASH_MAX := + +CC := $(CROSS_COMPILE)gcc +LD := $(CROSS_COMPILE)ld +OBJCOPY := $(CROSS_COMPILE)objcopy +OBJDUMP := $(CROSS_COMPILE)objdump + +BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug \ + -R .MIPS.abiflags -S + +CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \ + -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \ + -fno-common -ffreestanding -fhonour-copts \ + -mabi=32 -march=mips32r2 \ + -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap +CFLAGS += -D_LZMA_PROB32 + +ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +LDFLAGS = -static --gc-sections -no-warn-mismatch +LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START) + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +OBJECTS := head.o loader.o cache.o board.o printf.o LzmaDecode.o + +ifneq ($(strip $(LOADER_DATA)),) +OBJECTS += data.o +CFLAGS += -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR) +endif + +ifneq ($(strip $(KERNEL_CMDLINE)),) +CFLAGS += -DCONFIG_KERNEL_CMDLINE='"$(KERNEL_CMDLINE)"' +endif + +ifneq ($(strip $(FLASH_OFFS)),) +CFLAGS += -DCONFIG_FLASH_OFFS=$(FLASH_OFFS) +endif + +ifneq ($(strip $(FLASH_MAX)),) +CFLAGS += -DCONFIG_FLASH_MAX=$(FLASH_MAX) +endif + +BOARD_DEF := $(shell echo $(strip $(BOARD)) | tr a-z A-Z | tr - _) +ifneq ($(BOARD_DEF),) +CFLAGS += -DCONFIG_BOARD_$(BOARD_DEF) +endif + +all: loader.elf + +# Don't build dependencies, this may die if $(CC) isn't gcc +dep: + +install: + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $< + +%.o : %.S + $(CC) $(ASFLAGS) -c -o $@ $< + +data.o: $(LOADER_DATA) + $(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $< + +loader: $(OBJECTS) + $(LD) $(LDFLAGS) -o $@ $(OBJECTS) + +loader.bin: loader + $(OBJCOPY) $(BIN_FLAGS) $< $@ + +loader2.o: loader.bin + $(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $< + +loader.elf: loader2.o + $(LD) -e startup -T loader2.lds -Ttext $(LOADADDR) -o $@ $< + +mrproper: clean + +clean: + rm -f loader *.elf *.bin *.o + + + diff --git a/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h b/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h new file mode 100644 index 0000000..19a4785 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h @@ -0,0 +1,725 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#define BIT(_x) (1UL << (_x)) + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 + +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 +#define AR9300_OTP_STATUS_TYPE 0x7 +#define AR9300_OTP_STATUS_VALID 0x4 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 +#define AR9300_OTP_STATUS_SM_BUSY 0x1 +#define AR9300_OTP_READ_DATA 0x15f1c + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9558 0x1130 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define AR944X_REV_ID_REVISION_MASK 0xf + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define AR71XX_GPIO_COUNT 16 +#define AR724X_GPIO_COUNT 18 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA955X_GPIO_COUNT 24 + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) +#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) +#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) + +#define AR934X_GPIO_OUT_GPIO 0x00 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6) + +#endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/board.c b/target/linux/ar71xx/image/lzma-loader/src/board.c new file mode 100644 index 0000000..2f4dd6b --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/board.c @@ -0,0 +1,56 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include "config.h" +#include "ar71xx_regs.h" + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +#define KSEG1ADDR(_x) (((_x) & 0x1fffffff) | 0xa0000000) + +#define UART_BASE 0xb8020000 + +#define UART_TX 0 +#define UART_LSR 5 + +#define UART_LSR_THRE 0x20 + +#define UART_READ(r) READREG(UART_BASE + 4 * (r)) +#define UART_WRITE(r,v) WRITEREG(UART_BASE + 4 * (r), (v)) + +void board_putc(int ch) +{ + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(UART_TX, ch); + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); +} + +#ifdef CONFIG_BOARD_TL_WR1043ND_V1 +static void tlwr1043nd_init(void) +{ + unsigned int reg = KSEG1ADDR(AR71XX_RESET_BASE); + unsigned int t; + + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); + t |= AR71XX_RESET_GE0_PHY; + WRITEREG(reg + AR913X_RESET_REG_RESET_MODULE, t); + /* flush write */ + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); +} +#else +static inline void tlwr1043nd_init(void) {} +#endif + +void board_init(void) +{ + tlwr1043nd_init(); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/cache.c b/target/linux/ar71xx/image/lzma-loader/src/cache.c new file mode 100644 index 0000000..28cc848 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cache.c @@ -0,0 +1,43 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * The cache manipulation routine has been taken from the U-Boot project. + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cache.h" +#include "cacheops.h" +#include "config.h" + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/cache.h b/target/linux/ar71xx/image/lzma-loader/src/cache.h new file mode 100644 index 0000000..506a235 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cache.h @@ -0,0 +1,17 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __CACHE_H +#define __CACHE_H + +void flush_cache(unsigned long start_addr, unsigned long size); + +#endif /* __CACHE_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/cacheops.h b/target/linux/ar71xx/image/lzma-loader/src/cacheops.h new file mode 100644 index 0000000..70bcad7 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cacheops.h @@ -0,0 +1,85 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 + +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +#endif /* __ASM_CACHEOPS_H */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/config.h b/target/linux/ar71xx/image/lzma-loader/src/config.h new file mode 100644 index 0000000..287392b --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/config.h @@ -0,0 +1,31 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#define CONFIG_ICACHE_SIZE (32 * 1024) +#define CONFIG_DCACHE_SIZE (64 * 1024) +#define CONFIG_CACHELINE_SIZE 32 + +#ifndef CONFIG_FLASH_OFFS +#define CONFIG_FLASH_OFFS 0 +#endif + +#ifndef CONFIG_FLASH_MAX +#define CONFIG_FLASH_MAX 0 +#endif + +#ifndef CONFIG_FLASH_STEP +#define CONFIG_FLASH_STEP 0x1000 +#endif + +#endif /* _CONFIG_H_ */ diff --git a/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h b/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h new file mode 100644 index 0000000..c1188ad --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/cp0regdef.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * + * Copyright (C) 2001, Monta Vista Software + * Author: jsun@mvista.com or jsun@junsun.net + */ +#ifndef _cp0regdef_h_ +#define _cp0regdef_h_ + +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 + +#endif diff --git a/target/linux/ar71xx/image/lzma-loader/src/head.S b/target/linux/ar71xx/image/lzma-loader/src/head.S new file mode 100644 index 0000000..543996a --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/head.S @@ -0,0 +1,118 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "cp0regdef.h" +#include "cacheops.h" +#include "config.h" + +#define KSEG0 0x80000000 + + .macro ehb + sll zero, 3 + .endm + + .text + +LEAF(startup) + .set noreorder + .set mips32 + + mtc0 zero, CP0_WATCHLO # clear watch registers + mtc0 zero, CP0_WATCHHI + mtc0 zero, CP0_CAUSE # clear before writing status register + + mfc0 t0, CP0_STATUS + li t1, 0x1000001f + or t0, t1 + xori t0, 0x1f + mtc0 t0, CP0_STATUS + ehb + + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + ehb + + la t0, __reloc_label # get linked address of label + bal __reloc_label # branch and link to label to + nop # get actual address +__reloc_label: + subu t0, ra, t0 # get reloc_delta + + beqz t0, __reloc_done # if delta is 0 we are in the right place + nop + + /* Copy our code to the right place */ + la t1, _code_start # get linked address of _code_start + la t2, _code_end # get linked address of _code_end + addu t0, t0, t1 # calculate actual address of _code_start + +__reloc_copy: + lw t3, 0(t0) + sw t3, 0(t1) + add t1, 4 + blt t1, t2, __reloc_copy + add t0, 4 + + /* flush cache */ + la t0, _code_start + la t1, _code_end + + li t2, ~(CONFIG_CACHELINE_SIZE - 1) + and t0, t2 + and t1, t2 + li t2, CONFIG_CACHELINE_SIZE + + b __flush_check + nop + +__flush_line: + cache Hit_Writeback_Inv_D, 0(t0) + cache Hit_Invalidate_I, 0(t0) + add t0, t2 + +__flush_check: + bne t0, t1, __flush_line + nop + + sync + +__reloc_done: + + /* clear bss */ + la t0, _bss_start + la t1, _bss_end + b __bss_check + nop + +__bss_fill: + sw zero, 0(t0) + addi t0, 4 + +__bss_check: + bne t0, t1, __bss_fill + nop + + /* Setup new "C" stack */ + la sp, _stack + + /* jump to the decompressor routine */ + la t0, loader_main + jr t0 + nop + + .set reorder +END(startup) diff --git a/target/linux/ar71xx/image/lzma-loader/src/loader.c b/target/linux/ar71xx/image/lzma-loader/src/loader.c new file mode 100644 index 0000000..cc73eb1 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/loader.c @@ -0,0 +1,264 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 Mineharu Takahara + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * The image_header structure has been taken from the U-Boot project. + * (C) Copyright 2008 Semihalf + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "config.h" +#include "cache.h" +#include "printf.h" +#include "LzmaDecode.h" + +#define AR71XX_FLASH_START 0x1f000000 +#define AR71XX_FLASH_END 0x1fe00000 + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) + +#undef LZMA_DEBUG + +#ifdef LZMA_DEBUG +# define DBG(f, a...) printf(f, ## a) +#else +# define DBG(f, a...) do {} while (0) +#endif + +#define IH_MAGIC_OKLI 0x4f4b4c49 /* 'OKLI' */ + +#define IH_NMLEN 32 /* Image Name Length */ + +typedef struct image_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +} image_header_t; + +/* beyond the image end, size not known in advance */ +extern unsigned char workspace[]; +extern void board_init(void); + +static CLzmaDecoderState lzma_state; +static unsigned char *lzma_data; +static unsigned long lzma_datasize; +static unsigned long lzma_outsize; +static unsigned long kernel_la; + +#ifdef CONFIG_KERNEL_CMDLINE +#define kernel_argc 2 +static const char kernel_cmdline[] = CONFIG_KERNEL_CMDLINE; +static const char *kernel_argv[] = { + NULL, + kernel_cmdline, + NULL, +}; +#endif /* CONFIG_KERNEL_CMDLINE */ + +static void halt(void) +{ + printf("\nSystem halted!\n"); + for(;;); +} + +static __inline__ unsigned long get_be32(void *buf) +{ + unsigned char *p = buf; + + return (((unsigned long) p[0] << 24) + + ((unsigned long) p[1] << 16) + + ((unsigned long) p[2] << 8) + + (unsigned long) p[3]); +} + +static __inline__ unsigned char lzma_get_byte(void) +{ + unsigned char c; + + lzma_datasize--; + c = *lzma_data++; + + return c; +} + +static int lzma_init_props(void) +{ + unsigned char props[LZMA_PROPERTIES_SIZE]; + int res; + int i; + + /* read lzma properties */ + for (i = 0; i < LZMA_PROPERTIES_SIZE; i++) + props[i] = lzma_get_byte(); + + /* read the lower half of uncompressed size in the header */ + lzma_outsize = ((SizeT) lzma_get_byte()) + + ((SizeT) lzma_get_byte() << 8) + + ((SizeT) lzma_get_byte() << 16) + + ((SizeT) lzma_get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + for (i = 0; i < 4; i++) + lzma_get_byte(); + + res = LzmaDecodeProperties(&lzma_state.Properties, props, + LZMA_PROPERTIES_SIZE); + return res; +} + +static int lzma_decompress(unsigned char *outStream) +{ + SizeT ip, op; + int ret; + + lzma_state.Probs = (CProb *) workspace; + + ret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream, + lzma_outsize, &op); + + if (ret != LZMA_RESULT_OK) { + int i; + + DBG("LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\n", + ret, lzma_data + ip, lzma_outsize, ip, op); + + for (i = 0; i < 16; i++) + DBG("%02x ", lzma_data[ip + i]); + + DBG("\n"); + } + + return ret; +} + +#if (LZMA_WRAPPER) +static void lzma_init_data(void) +{ + extern unsigned char _lzma_data_start[]; + extern unsigned char _lzma_data_end[]; + + kernel_la = LOADADDR; + lzma_data = _lzma_data_start; + lzma_datasize = _lzma_data_end - _lzma_data_start; +} +#else +static void lzma_init_data(void) +{ + struct image_header *hdr = NULL; + unsigned char *flash_base; + unsigned long flash_ofs; + unsigned long kernel_ofs; + unsigned long kernel_size; + + flash_base = (unsigned char *) KSEG1ADDR(AR71XX_FLASH_START); + + printf("Looking for OpenWrt image... "); + + for (flash_ofs = CONFIG_FLASH_OFFS; + flash_ofs <= (CONFIG_FLASH_OFFS + CONFIG_FLASH_MAX); + flash_ofs += CONFIG_FLASH_STEP) { + unsigned long magic; + unsigned char *p; + + p = flash_base + flash_ofs; + magic = get_be32(p); + if (magic == IH_MAGIC_OKLI) { + hdr = (struct image_header *) p; + break; + } + } + + if (hdr == NULL) { + printf("not found!\n"); + halt(); + } + + printf("found at 0x%08x\n", flash_base + flash_ofs); + + kernel_ofs = sizeof(struct image_header); + kernel_size = get_be32(&hdr->ih_size); + kernel_la = get_be32(&hdr->ih_load); + + lzma_data = flash_base + flash_ofs + kernel_ofs; + lzma_datasize = kernel_size; +} +#endif /* (LZMA_WRAPPER) */ + +void loader_main(unsigned long reg_a0, unsigned long reg_a1, + unsigned long reg_a2, unsigned long reg_a3) +{ + void (*kernel_entry) (unsigned long, unsigned long, unsigned long, + unsigned long); + int res; + + board_init(); + + printf("\n\nOpenWrt kernel loader for AR7XXX/AR9XXX\n"); + printf("Copyright (C) 2011 Gabor Juhos \n"); + + lzma_init_data(); + + res = lzma_init_props(); + if (res != LZMA_RESULT_OK) { + printf("Incorrect LZMA stream properties!\n"); + halt(); + } + + printf("Decompressing kernel... "); + + res = lzma_decompress((unsigned char *) kernel_la); + if (res != LZMA_RESULT_OK) { + printf("failed, "); + switch (res) { + case LZMA_RESULT_DATA_ERROR: + printf("data error!\n"); + break; + default: + printf("unknown error %d!\n", res); + } + halt(); + } else { + printf("done!\n"); + } + + flush_cache(kernel_la, lzma_outsize); + + printf("Starting kernel at %08x...\n\n", kernel_la); + +#ifdef CONFIG_KERNEL_CMDLINE + reg_a0 = kernel_argc; + reg_a1 = (unsigned long) kernel_argv; + reg_a2 = 0; + reg_a3 = 0; +#endif + + kernel_entry = (void *) kernel_la; + kernel_entry(reg_a0, reg_a1, reg_a2, reg_a3); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/loader.lds b/target/linux/ar71xx/image/lzma-loader/src/loader.lds new file mode 100644 index 0000000..80cc7ca --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/loader.lds @@ -0,0 +1,35 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + _code_start = .; + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.data.lzma) + } + + . = ALIGN(32); + .data : { + *(.data) + *(.data.*) + . = . + 524288; /* workaround for buggy bootloaders */ + } + + . = ALIGN(32); + _code_end = .; + + _bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + } + + . = ALIGN(32); + _bss_end = .; + + . = . + 8192; + _stack = .; + + workspace = .; +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/loader2.lds b/target/linux/ar71xx/image/lzma-loader/src/loader2.lds new file mode 100644 index 0000000..db0bb46 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/loader2.lds @@ -0,0 +1,10 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + startup = .; + *(.text) + *(.text.*) + *(.data) + *(.data.*) + } +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds b/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds new file mode 100644 index 0000000..abf756b --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/lzma-data.lds @@ -0,0 +1,8 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .data.lzma : { + _lzma_data_start = .; + *(.data) + _lzma_data_end = .; + } +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/printf.c b/target/linux/ar71xx/image/lzma-loader/src/printf.c new file mode 100644 index 0000000..7bb5a86 --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/printf.c @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "printf.h" + +extern void board_putc(int ch); + +/* this is the maximum width for a variable */ +#define LP_MAX_BUF 256 + +/* macros */ +#define IsDigit(x) ( ((x) >= '0') && ((x) <= '9') ) +#define Ctod(x) ( (x) - '0') + +/* forward declaration */ +static int PrintChar(char *, char, int, int); +static int PrintString(char *, char *, int, int); +static int PrintNum(char *, unsigned long, int, int, int, int, char, int); + +/* private variable */ +static const char theFatalMsg[] = "fatal error in lp_Print!"; + +/* -*- + * A low level printf() function. + */ +static void +lp_Print(void (*output)(void *, char *, int), + void * arg, + char *fmt, + va_list ap) +{ + +#define OUTPUT(arg, s, l) \ + { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \ + (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \ + } else { \ + (*output)(arg, s, l); \ + } \ + } + + char buf[LP_MAX_BUF]; + + char c; + char *s; + long int num; + + int longFlag; + int negFlag; + int width; + int prec; + int ladjust; + char padc; + + int length; + + for(;;) { + { + /* scan for the next '%' */ + char *fmtStart = fmt; + while ( (*fmt != '\0') && (*fmt != '%')) { + fmt ++; + } + + /* flush the string found so far */ + OUTPUT(arg, fmtStart, fmt-fmtStart); + + /* are we hitting the end? */ + if (*fmt == '\0') break; + } + + /* we found a '%' */ + fmt ++; + + /* check for long */ + if (*fmt == 'l') { + longFlag = 1; + fmt ++; + } else { + longFlag = 0; + } + + /* check for other prefixes */ + width = 0; + prec = -1; + ladjust = 0; + padc = ' '; + + if (*fmt == '-') { + ladjust = 1; + fmt ++; + } + + if (*fmt == '0') { + padc = '0'; + fmt++; + } + + if (IsDigit(*fmt)) { + while (IsDigit(*fmt)) { + width = 10 * width + Ctod(*fmt++); + } + } + + if (*fmt == '.') { + fmt ++; + if (IsDigit(*fmt)) { + prec = 0; + while (IsDigit(*fmt)) { + prec = prec*10 + Ctod(*fmt++); + } + } + } + + + /* check format flag */ + negFlag = 0; + switch (*fmt) { + case 'b': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'd': + case 'D': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + if (num < 0) { + num = - num; + negFlag = 1; + } + length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'o': + case 'O': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'u': + case 'U': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'x': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'X': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1); + OUTPUT(arg, buf, length); + break; + + case 'c': + c = (char)va_arg(ap, int); + length = PrintChar(buf, c, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case 's': + s = (char*)va_arg(ap, char *); + length = PrintString(buf, s, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case '\0': + fmt --; + break; + + default: + /* output this char as it is */ + OUTPUT(arg, fmt, 1); + } /* switch (*fmt) */ + + fmt ++; + } /* for(;;) */ + + /* special termination call */ + OUTPUT(arg, "\0", 1); +} + + +/* --------------- local help functions --------------------- */ +static int +PrintChar(char * buf, char c, int length, int ladjust) +{ + int i; + + if (length < 1) length = 1; + if (ladjust) { + *buf = c; + for (i=1; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-1; i++) buf[i] = ' '; + buf[length - 1] = c; + } + return length; +} + +static int +PrintString(char * buf, char* s, int length, int ladjust) +{ + int i; + int len=0; + char* s1 = s; + while (*s1++) len++; + if (length < len) length = len; + + if (ladjust) { + for (i=0; i< len; i++) buf[i] = s[i]; + for (i=len; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-len; i++) buf[i] = ' '; + for (i=length-len; i < length; i++) buf[i] = s[i-length+len]; + } + return length; +} + +static int +PrintNum(char * buf, unsigned long u, int base, int negFlag, + int length, int ladjust, char padc, int upcase) +{ + /* algorithm : + * 1. prints the number from left to right in reverse form. + * 2. fill the remaining spaces with padc if length is longer than + * the actual length + * TRICKY : if left adjusted, no "0" padding. + * if negtive, insert "0" padding between "0" and number. + * 3. if (!ladjust) we reverse the whole string including paddings + * 4. otherwise we only reverse the actual string representing the num. + */ + + int actualLength =0; + char *p = buf; + int i; + + do { + int tmp = u %base; + if (tmp <= 9) { + *p++ = '0' + tmp; + } else if (upcase) { + *p++ = 'A' + tmp - 10; + } else { + *p++ = 'a' + tmp - 10; + } + u /= base; + } while (u != 0); + + if (negFlag) { + *p++ = '-'; + } + + /* figure out actual length and adjust the maximum length */ + actualLength = p - buf; + if (length < actualLength) length = actualLength; + + /* add padding */ + if (ladjust) { + padc = ' '; + } + if (negFlag && !ladjust && (padc == '0')) { + for (i = actualLength-1; i< length-1; i++) buf[i] = padc; + buf[length -1] = '-'; + } else { + for (i = actualLength; i< length; i++) buf[i] = padc; + } + + + /* prepare to reverse the string */ + { + int begin = 0; + int end; + if (ladjust) { + end = actualLength - 1; + } else { + end = length -1; + } + + while (end > begin) { + char tmp = buf[begin]; + buf[begin] = buf[end]; + buf[end] = tmp; + begin ++; + end --; + } + } + + /* adjust the string pointer */ + return length; +} + +static void printf_output(void *arg, char *s, int l) +{ + int i; + + // special termination call + if ((l==1) && (s[0] == '\0')) return; + + for (i=0; i< l; i++) { + board_putc(s[i]); + if (s[i] == '\n') board_putc('\r'); + } +} + +void printf(char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + lp_Print(printf_output, 0, fmt, ap); + va_end(ap); +} diff --git a/target/linux/ar71xx/image/lzma-loader/src/printf.h b/target/linux/ar71xx/image/lzma-loader/src/printf.h new file mode 100644 index 0000000..9b1c1df --- /dev/null +++ b/target/linux/ar71xx/image/lzma-loader/src/printf.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _printf_h_ +#define _printf_h_ + +#include +void printf(char *fmt, ...); + +#endif /* _printf_h_ */ diff --git a/target/linux/ar71xx/image/ubinize-nbg6716.ini b/target/linux/ar71xx/image/ubinize-nbg6716.ini new file mode 100644 index 0000000..814b0fb --- /dev/null +++ b/target/linux/ar71xx/image/ubinize-nbg6716.ini @@ -0,0 +1,24 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=ubi_root.img +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs + +[rootfs_data] +# Volume mode (other option is static) +mode=ubi +# Volume ID in UBI image +vol_id=1 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs_data +# Autoresize volume at first mount +vol_size=1MiB +vol_flags=autoresize diff --git a/target/linux/ar71xx/image/ubinize-wndr4300.ini b/target/linux/ar71xx/image/ubinize-wndr4300.ini new file mode 100644 index 0000000..5bff906 --- /dev/null +++ b/target/linux/ar71xx/image/ubinize-wndr4300.ini @@ -0,0 +1,26 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.squashfs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs +# Autoresize volume at first mount +# vol_flags=autoresize + +[rootfs_data] +# Volume mode (other option is static) +mode=ubi +# Volume ID in UBI image +vol_id=1 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs_data +# Autoresize volume at first mount +vol_flags=autoresize +vol_size=1MiB diff --git a/target/linux/ar71xx/mikrotik/config-default b/target/linux/ar71xx/mikrotik/config-default new file mode 100644 index 0000000..de91e4b --- /dev/null +++ b/target/linux/ar71xx/mikrotik/config-default @@ -0,0 +1,169 @@ +# CONFIG_ATH79_DEV_DSA is not set +# CONFIG_ATH79_MACH_ALFA_AP96 is not set +# CONFIG_ATH79_MACH_ALFA_NX is not set +# CONFIG_ATH79_MACH_ALL0258N is not set +# CONFIG_ATH79_MACH_ALL0315N is not set +# CONFIG_ATH79_MACH_ANTMINER_S1 is not set +# CONFIG_ATH79_MACH_AP113 is not set +# CONFIG_ATH79_MACH_AP121 is not set +# CONFIG_ATH79_MACH_AP132 is not set +# CONFIG_ATH79_MACH_AP136 is not set +# CONFIG_ATH79_MACH_AP147 is not set +# CONFIG_ATH79_MACH_AP81 is not set +# CONFIG_ATH79_MACH_AP83 is not set +# CONFIG_ATH79_MACH_AP96 is not set +# CONFIG_ATH79_MACH_ARCHER_C7 is not set +# CONFIG_ATH79_MACH_AW_NR580 is not set +# CONFIG_ATH79_MACH_BHU_BXU2000N2_A is not set +# CONFIG_ATH79_MACH_CAP4200AG is not set +# CONFIG_ATH79_MACH_CARAMBOLA2 is not set +# CONFIG_ATH79_MACH_CPE510 is not set +# CONFIG_ATH79_MACH_DB120 is not set +# CONFIG_ATH79_MACH_DGL_5500_A1 is not set +# CONFIG_ATH79_MACH_DHP_1565_A1 is not set +# CONFIG_ATH79_MACH_DIR_505_A1 is not set +# CONFIG_ATH79_MACH_DIR_600_A1 is not set +# CONFIG_ATH79_MACH_DIR_615_C1 is not set +# CONFIG_ATH79_MACH_DIR_825_B1 is not set +# CONFIG_ATH79_MACH_DIR_825_C1 is not set +# CONFIG_ATH79_MACH_DRAGINO2 is not set +# CONFIG_ATH79_MACH_EAP300V2 is not set +# CONFIG_ATH79_MACH_EAP7660D is not set +# CONFIG_ATH79_MACH_EL_M150 is not set +# CONFIG_ATH79_MACH_EL_MINI is not set +# CONFIG_ATH79_MACH_EPG5000 is not set +# CONFIG_ATH79_MACH_ESR1750 is not set +# CONFIG_ATH79_MACH_ESR900 is not set +# CONFIG_ATH79_MACH_EW_DORIN is not set +# CONFIG_ATH79_MACH_F9K1115V2 is not set +# CONFIG_ATH79_MACH_GL_INET is not set +# CONFIG_ATH79_MACH_GS_OOLITE is not set +# CONFIG_ATH79_MACH_HIWIFI_HC6361 is not set +# CONFIG_ATH79_MACH_HORNET_UB is not set +# CONFIG_ATH79_MACH_JA76PF is not set +# CONFIG_ATH79_MACH_JWAP003 is not set +# CONFIG_ATH79_MACH_MC_MAC1200R is not set +# CONFIG_ATH79_MACH_MR12 is not set +# CONFIG_ATH79_MACH_MR16 is not set +# CONFIG_ATH79_MACH_MR600 is not set +# CONFIG_ATH79_MACH_MR900 is not set +# CONFIG_ATH79_MACH_MYNET_N600 is not set +# CONFIG_ATH79_MACH_MYNET_N750 is not set +# CONFIG_ATH79_MACH_MYNET_REXT is not set +# CONFIG_ATH79_MACH_MZK_W04NU is not set +# CONFIG_ATH79_MACH_MZK_W300NH is not set +# CONFIG_ATH79_MACH_NBG460N is not set +# CONFIG_ATH79_MACH_NBG6716 is not set +# CONFIG_ATH79_MACH_OM2P is not set +# CONFIG_ATH79_MACH_OM5P is not set +# CONFIG_ATH79_MACH_PB42 is not set +# CONFIG_ATH79_MACH_PB44 is not set +# CONFIG_ATH79_MACH_PB92 is not set +# CONFIG_ATH79_MACH_QIHOO_C301 is not set +# CONFIG_ATH79_MACH_R6100 is not set +CONFIG_ATH79_MACH_RB2011=y +CONFIG_ATH79_MACH_RB4XX=y +CONFIG_ATH79_MACH_RB750=y +CONFIG_ATH79_MACH_RB91X=y +CONFIG_ATH79_MACH_RB922=y +CONFIG_ATH79_MACH_RB95X=y +CONFIG_ATH79_MACH_RBSXTLITE=y +# CONFIG_ATH79_MACH_RW2458N is not set +# CONFIG_ATH79_MACH_SMART_300 is not set +# CONFIG_ATH79_MACH_TEW_632BRP is not set +# CONFIG_ATH79_MACH_TEW_673GRU is not set +# CONFIG_ATH79_MACH_TEW_712BR is not set +# CONFIG_ATH79_MACH_TEW_732BR is not set +# CONFIG_ATH79_MACH_TL_MR11U is not set +# CONFIG_ATH79_MACH_TL_MR13U is not set +# CONFIG_ATH79_MACH_TL_MR3020 is not set +# CONFIG_ATH79_MACH_TL_MR3X20 is not set +# CONFIG_ATH79_MACH_TL_WA701ND_V2 is not set +# CONFIG_ATH79_MACH_TL_WA7210N_V2 is not set +# CONFIG_ATH79_MACH_TL_WA830RE_V2 is not set +# CONFIG_ATH79_MACH_TL_WA901ND is not set +# CONFIG_ATH79_MACH_TL_WA901ND_V2 is not set +# CONFIG_ATH79_MACH_TL_WAX50RE is not set +# CONFIG_ATH79_MACH_TL_WDR3500 is not set +# CONFIG_ATH79_MACH_TL_WDR4300 is not set +# CONFIG_ATH79_MACH_TL_WR1041N_V2 is not set +# CONFIG_ATH79_MACH_TL_WR1043ND is not set +# CONFIG_ATH79_MACH_TL_WR1043ND_V2 is not set +# CONFIG_ATH79_MACH_TL_WR2543N is not set +# CONFIG_ATH79_MACH_TL_WR703N is not set +# CONFIG_ATH79_MACH_TL_WR720N_V3 is not set +# CONFIG_ATH79_MACH_TL_WR741ND is not set +# CONFIG_ATH79_MACH_TL_WR741ND_V4 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V1 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V8 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V9 is not set +# CONFIG_ATH79_MACH_TL_WR941ND is not set +# CONFIG_ATH79_MACH_TUBE2H is not set +# CONFIG_ATH79_MACH_UBNT is not set +# CONFIG_ATH79_MACH_UBNT_XM is not set +# CONFIG_ATH79_MACH_WHR_HP_G300N is not set +# CONFIG_ATH79_MACH_WLAE_AG300N is not set +# CONFIG_ATH79_MACH_WLR8100 is not set +# CONFIG_ATH79_MACH_WNDAP360 is not set +# CONFIG_ATH79_MACH_WNDR3700 is not set +# CONFIG_ATH79_MACH_WNDR4300 is not set +# CONFIG_ATH79_MACH_WNR2000 is not set +# CONFIG_ATH79_MACH_WNR2000_V3 is not set +# CONFIG_ATH79_MACH_WNR2000_V4 is not set +# CONFIG_ATH79_MACH_WNR2200 is not set +# CONFIG_ATH79_MACH_WP543 is not set +# CONFIG_ATH79_MACH_WPE72 is not set +# CONFIG_ATH79_MACH_WPJ344 is not set +# CONFIG_ATH79_MACH_WPJ531 is not set +# CONFIG_ATH79_MACH_WPJ558 is not set +# CONFIG_ATH79_MACH_WRT160NL is not set +# CONFIG_ATH79_MACH_WRT400N is not set +# CONFIG_ATH79_MACH_WZR_450HP2 is not set +# CONFIG_ATH79_MACH_WZR_HP_AG300H is not set +# CONFIG_ATH79_MACH_WZR_HP_G300NH is not set +# CONFIG_ATH79_MACH_WZR_HP_G300NH2 is not set +# CONFIG_ATH79_MACH_WZR_HP_G450H is not set +# CONFIG_ATH79_MACH_ZCN_1523H is not set +# CONFIG_ATH79_NVRAM is not set +CONFIG_ATH79_ROUTERBOOT=y +CONFIG_CMDLINE="rootfstype=yaffs noinitrd" +CONFIG_GPIO_74X164=y +CONFIG_GPIO_LATCH=y +# CONFIG_JFFS2_FS is not set +CONFIG_LEDS_RB750=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MYLOADER_PARTS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_AR934X=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_RB4XX=y +CONFIG_MTD_NAND_RB750=y +CONFIG_MTD_NAND_RB91X=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_TPLINK_PARTS is not set +# CONFIG_OVERLAY_FS is not set +CONFIG_RLE_DECOMPRESS=y +# CONFIG_SOC_AR913X is not set +# CONFIG_SOC_AR933X is not set +# CONFIG_SOC_QCA953X is not set +CONFIG_SPI_RB4XX=y +CONFIG_SPI_RB4XX_CPLD=y +# CONFIG_SQUASHFS is not set +CONFIG_YAFFS_9BYTE_TAGS=y +CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_BACKGROUND is not set +# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +CONFIG_YAFFS_FS=y +CONFIG_YAFFS_XATTR=y +CONFIG_YAFFS_YAFFS1=y +CONFIG_YAFFS_YAFFS2=y diff --git a/target/linux/ar71xx/mikrotik/profiles/01-minimal.mk b/target/linux/ar71xx/mikrotik/profiles/01-minimal.mk new file mode 100644 index 0000000..3651c88 --- /dev/null +++ b/target/linux/ar71xx/mikrotik/profiles/01-minimal.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DefaultNoWifi + NAME:=Default Profile (no WiFi) + PACKAGES:= +endef + +define Profile/DefaultNoWifi/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,DefaultNoWifi)) diff --git a/target/linux/ar71xx/mikrotik/profiles/02-ath5k.mk b/target/linux/ar71xx/mikrotik/profiles/02-ath5k.mk new file mode 100644 index 0000000..a291ff6 --- /dev/null +++ b/target/linux/ar71xx/mikrotik/profiles/02-ath5k.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Ath5k + NAME:=Atheros WiFi (ath5k) + PACKAGES:=kmod-ath5k -kmod-ath9k +endef + +define Profile/Ath5k/Description + Package set compatible with hardware using Atheros WiFi cards. +endef +$(eval $(call Profile,Ath5k)) diff --git a/target/linux/ar71xx/mikrotik/target.mk b/target/linux/ar71xx/mikrotik/target.mk new file mode 100644 index 0000000..a2a41ed --- /dev/null +++ b/target/linux/ar71xx/mikrotik/target.mk @@ -0,0 +1,9 @@ +BOARDNAME:=Mikrotik devices with NAND flash +FEATURES += targz + +define Target/Description + Build firmware images for Atheros AR71xx/AR913x based Mikrotik boards. + e.g. MikroTik RB-4xx or RB-750 +endef + + diff --git a/target/linux/ar71xx/modules.mk b/target/linux/ar71xx/modules.mk new file mode 100644 index 0000000..a6a13d2 --- /dev/null +++ b/target/linux/ar71xx/modules.mk @@ -0,0 +1,53 @@ +# +# Copyright (C) 2006-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/leds-rb750 + SUBMENU:=$(LEDS_MENU) + TITLE:=RouterBOARD 750 LED support + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_LEDS_RB750 + FILES:=$(LINUX_DIR)/drivers/leds/leds-rb750.ko + AUTOLOAD:=$(call AutoLoad,60,leds-rb750) +endef + +define KernelPackage/leds-rb750/description + Kernel module for the LEDs on the MikroTik RouterBOARD 750. +endef + +$(eval $(call KernelPackage,leds-rb750)) + + +define KernelPackage/leds-wndr3700-usb + SUBMENU:=$(LEDS_MENU) + TITLE:=WNDR3700 USB LED support + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_LEDS_WNDR3700_USB + FILES:=$(LINUX_DIR)/drivers/leds/leds-wndr3700-usb.ko + AUTOLOAD:=$(call AutoLoad,60,leds-wndr3700-usb) +endef + +define KernelPackage/leds-wndr3700-usb/description + Kernel module for the USB LED on the NETGEAR WNDR3700 board. +endef + +$(eval $(call KernelPackage,leds-wndr3700-usb)) + + +define KernelPackage/spi-vsc7385 + SUBMENU:=$(SPI_MENU) + TITLE:=Vitesse VSC7385 ethernet switch driver + DEPENDS:=@TARGET_ar71xx + KCONFIG:=CONFIG_SPI_VSC7385 + FILES:=$(LINUX_DIR)/drivers/spi/spi-vsc7385.ko + AUTOLOAD:=$(call AutoLoad,93,spi-vsc7385) +endef + +define KernelPackage/spi-vsc7385/description + This package contains the SPI driver for the Vitesse VSC7385 ethernet switch. +endef + +$(eval $(call KernelPackage,spi-vsc7385)) diff --git a/target/linux/ar71xx/nand/config-default b/target/linux/ar71xx/nand/config-default new file mode 100644 index 0000000..50b6dbe --- /dev/null +++ b/target/linux/ar71xx/nand/config-default @@ -0,0 +1,112 @@ +# CONFIG_ATH79_DEV_DSA is not set +# CONFIG_ATH79_MACH_ALFA_AP96 is not set +# CONFIG_ATH79_MACH_ALFA_NX is not set +# CONFIG_ATH79_MACH_ALL0258N is not set +# CONFIG_ATH79_MACH_ALL0315N is not set +# CONFIG_ATH79_MACH_AP113 is not set +# CONFIG_ATH79_MACH_AP121 is not set +# CONFIG_ATH79_MACH_AP132 is not set +# CONFIG_ATH79_MACH_AP136 is not set +# CONFIG_ATH79_MACH_AP147 is not set +# CONFIG_ATH79_MACH_AP81 is not set +# CONFIG_ATH79_MACH_AP83 is not set +# CONFIG_ATH79_MACH_AP96 is not set +# CONFIG_ATH79_MACH_ARCHER_C7 is not set +# CONFIG_ATH79_MACH_AW_NR580 is not set +# CONFIG_ATH79_MACH_CAP4200AG is not set +# CONFIG_ATH79_MACH_CARAMBOLA2 is not set +# CONFIG_ATH79_MACH_DB120 is not set +# CONFIG_ATH79_MACH_DIR_505_A1 is not set +# CONFIG_ATH79_MACH_DIR_600_A1 is not set +# CONFIG_ATH79_MACH_DIR_615_C1 is not set +# CONFIG_ATH79_MACH_DIR_825_B1 is not set +# CONFIG_ATH79_MACH_DIR_825_C1 is not set +# CONFIG_ATH79_MACH_EAP7660D is not set +# CONFIG_ATH79_MACH_EW_DORIN is not set +# CONFIG_ATH79_MACH_HORNET_UB is not set +# CONFIG_ATH79_MACH_JA76PF is not set +# CONFIG_ATH79_MACH_JWAP003 is not set +# CONFIG_ATH79_MACH_MR600 is not set +# CONFIG_ATH79_MACH_MYNET_N600 is not set +# CONFIG_ATH79_MACH_MZK_W04NU is not set +# CONFIG_ATH79_MACH_MZK_W300NH is not set +# CONFIG_ATH79_MACH_NBG460N is not set +# CONFIG_ATH79_MACH_OM2P is not set +# CONFIG_ATH79_MACH_PB42 is not set +# CONFIG_ATH79_MACH_PB44 is not set +# CONFIG_ATH79_MACH_PB92 is not set +# CONFIG_ATH79_MACH_RW2458N is not set +# CONFIG_ATH79_MACH_TEW_632BRP is not set +# CONFIG_ATH79_MACH_TEW_673GRU is not set +# CONFIG_ATH79_MACH_TEW_712BR is not set +# CONFIG_ATH79_MACH_TEW_732BR is not set +# CONFIG_ATH79_MACH_TL_MR11U is not set +# CONFIG_ATH79_MACH_TL_MR13U is not set +# CONFIG_ATH79_MACH_TL_MR3020 is not set +# CONFIG_ATH79_MACH_TL_MR3X20 is not set +# CONFIG_ATH79_MACH_TL_WA901ND is not set +# CONFIG_ATH79_MACH_TL_WA901ND_V2 is not set +# CONFIG_ATH79_MACH_TL_WDR3500 is not set +# CONFIG_ATH79_MACH_TL_WDR4300 is not set +# CONFIG_ATH79_MACH_TL_WR1041N_V2 is not set +# CONFIG_ATH79_MACH_TL_WR1043ND is not set +# CONFIG_ATH79_MACH_TL_WR2543N is not set +# CONFIG_ATH79_MACH_TL_WR703N is not set +# CONFIG_ATH79_MACH_TL_WR720N_V3 is not set +# CONFIG_ATH79_MACH_TL_WR741ND is not set +# CONFIG_ATH79_MACH_TL_WR741ND_V4 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V1 is not set +# CONFIG_ATH79_MACH_TL_WR841N_V8 is not set +# CONFIG_ATH79_MACH_TL_WR941ND is not set +# CONFIG_ATH79_MACH_UBNT is not set +# CONFIG_ATH79_MACH_UBNT_XM is not set +# CONFIG_ATH79_MACH_WHR_HP_G300N is not set +# CONFIG_ATH79_MACH_WLAE_AG300N is not set +# CONFIG_ATH79_MACH_WNDAP360 is not set +# CONFIG_ATH79_MACH_WNDR3700 is not set +# CONFIG_ATH79_MACH_WNR2000 is not set +# CONFIG_ATH79_MACH_WNR2000_V3 is not set +# CONFIG_ATH79_MACH_WNR2200 is not set +# CONFIG_ATH79_MACH_WP543 is not set +# CONFIG_ATH79_MACH_WPE72 is not set +# CONFIG_ATH79_MACH_WRT160NL is not set +# CONFIG_ATH79_MACH_WRT400N is not set +# CONFIG_ATH79_MACH_WZR_HP_AG300H is not set +# CONFIG_ATH79_MACH_WZR_HP_G300NH is not set +# CONFIG_ATH79_MACH_WZR_HP_G300NH2 is not set +# CONFIG_ATH79_MACH_WZR_HP_G450H is not set +# CONFIG_ATH79_MACH_ZCN_1523H is not set +# CONFIG_ATH79_NVRAM is not set +CONFIG_CMDLINE="rootfstype=squashfs noinitrd" +# CONFIG_IP17XX_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MYLOADER_PARTS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_AR934X=y +CONFIG_MTD_NAND_AR934X_HW_ECC=y +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_SPLIT_SEAMA_FW is not set +# CONFIG_MTD_TPLINK_PARTS is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +# CONFIG_RTL8306_PHY is not set +# CONFIG_RTL8366_SMI is not set +# CONFIG_SOC_AR71XX is not set +# CONFIG_SOC_AR724X is not set +# CONFIG_SOC_AR913X is not set +CONFIG_SPI_ATH79=y +# CONFIG_SPI_BITBANG is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set diff --git a/target/linux/ar71xx/nand/profiles/netgear.mk b/target/linux/ar71xx/nand/profiles/netgear.mk new file mode 100644 index 0000000..738aaba --- /dev/null +++ b/target/linux/ar71xx/nand/profiles/netgear.mk @@ -0,0 +1,29 @@ +# +# Copyright (C) 2009-2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/R6100 + NAME:=NETGEAR R6100 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/R6100/Description + Package set optimized for the NETGEAR R6100 +endef + +$(eval $(call Profile,R6100)) + + +define Profile/WNDR4300 + NAME:=NETGEAR WNDR3700v4/WNDR4300 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev +endef + +define Profile/WNDR4300/Description + Package set optimized for the NETGEAR WNDR3700v4/WNDR4300 +endef + +$(eval $(call Profile,WNDR4300)) diff --git a/target/linux/ar71xx/nand/profiles/zyxel.mk b/target/linux/ar71xx/nand/profiles/zyxel.mk new file mode 100644 index 0000000..ec813e5 --- /dev/null +++ b/target/linux/ar71xx/nand/profiles/zyxel.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/NBG6716 + NAME:=Zyxel NBG 6716 + PACKAGES:=kmod-rtc-pcf8563 kmod-ath10k +endef + +define Profile/NBG6716/Description + Package set optimized for the Zyxel NBG 6716 Routers. +endef + +$(eval $(call Profile,NBG6716)) + diff --git a/target/linux/ar71xx/nand/target.mk b/target/linux/ar71xx/nand/target.mk new file mode 100644 index 0000000..7532ec6 --- /dev/null +++ b/target/linux/ar71xx/nand/target.mk @@ -0,0 +1,7 @@ +BOARDNAME := Generic devices with NAND flash +FEATURES += squashfs nand rtc + +define Target/Description + Build firmware images for Atheros AR71xx/AR913x based boards with + NAND flash, e.g. Netgear WNDR4300. +endef diff --git a/target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch b/target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch new file mode 100644 index 0000000..79c7ab0 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/100-MIPS-ath79-Avoid-using-unitialized-reg-variable.patch @@ -0,0 +1,42 @@ +From 8b7a76e72fc819753878cd5684e243f33f847c79 Mon Sep 17 00:00:00 2001 +From: Markos Chandras +Date: Wed, 21 Aug 2013 11:47:22 +0100 +Subject: [PATCH] MIPS: ath79: Avoid using unitialized 'reg' variable + +Fixes the following build error: +arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used +uninitialized in this function [-Werror=maybe-uninitialized] +arch/mips/ath79/common.c:62:6: note: 'reg' was declared here +In file included from arch/mips/ath79/common.c:20:0: +arch/mips/ath79/common.c: In function 'ath79_device_reset_clear': +arch/mips/include/asm/mach-ath79/ath79.h:139:20: +error: 'reg' may be used uninitialized in this function +[-Werror=maybe-uninitialized] +arch/mips/ath79/common.c:90:6: note: 'reg' was declared here + +Signed-off-by: Markos Chandras +Acked-by: Gabor Juhos +--- + arch/mips/ath79/common.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -75,7 +75,7 @@ void ath79_device_reset_set(u32 mask) + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else +- BUG(); ++ panic("Reset register not defined for this SOC"); + + spin_lock_irqsave(&ath79_device_reset_lock, flags); + t = ath79_reset_rr(reg); +@@ -103,7 +103,7 @@ void ath79_device_reset_clear(u32 mask) + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else +- BUG(); ++ panic("Reset register not defined for this SOC"); + + spin_lock_irqsave(&ath79_device_reset_lock, flags); + t = ath79_reset_rr(reg); diff --git a/target/linux/ar71xx/patches-4.1/110-export-missing-clk-functions.patch b/target/linux/ar71xx/patches-4.1/110-export-missing-clk-functions.patch new file mode 100644 index 0000000..b30087c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/110-export-missing-clk-functions.patch @@ -0,0 +1,28 @@ +This exports some clock functions used by some modules. +This fixes this linking problem: + +ERROR: "clk_set_rate" [drivers/usb/phy/phy-generic.ko] undefined! +ERROR: "clk_round_rate" [drivers/media/v4l2-core/videodev.ko] undefined! +ERROR: "clk_set_rate" [drivers/media/v4l2-core/videodev.ko] undefined! + +In the upstream kernel it is fixed here: +https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=411520af8ec9456886359b42628e583ac58e7e44 + +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -488,3 +488,15 @@ unsigned long clk_get_rate(struct clk *c + return clk->rate; + } + EXPORT_SYMBOL(clk_get_rate); ++ ++int clk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(clk_set_rate); ++ ++long clk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(clk_round_rate); diff --git a/target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch b/target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch new file mode 100644 index 0000000..e0821a7 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/200-MIPS-ath79-fix-ar933x-wmac-reset.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -62,10 +62,27 @@ static void __init ar913x_wmac_setup(voi + + static int ar933x_wmac_reset(void) + { ++ int retries = 20; ++ + ath79_device_reset_set(AR933X_RESET_WMAC); + ath79_device_reset_clear(AR933X_RESET_WMAC); + +- return 0; ++ while (1) { ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); ++ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0) ++ return 0; ++ ++ if (retries-- == 0) ++ break; ++ ++ udelay(10000); ++ retries++; ++ } ++ ++ pr_err("ar933x: WMAC reset timed out"); ++ return -ETIMEDOUT; + } + + static int ar933x_r1_get_wmac_revision(void) diff --git a/target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch b/target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch new file mode 100644 index 0000000..9b704a3 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/201-ar913x_wmac_external_reset.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -44,7 +44,7 @@ static struct platform_device ath79_wmac + }, + }; + +-static void __init ar913x_wmac_setup(void) ++static int ar913x_wmac_reset(void) + { + /* reset the WMAC */ + ath79_device_reset_set(AR913X_RESET_AMBA2WMAC); +@@ -53,10 +53,19 @@ static void __init ar913x_wmac_setup(voi + ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC); + mdelay(10); + ++ return 0; ++} ++ ++static void __init ar913x_wmac_setup(void) ++{ ++ ar913x_wmac_reset(); ++ + ath79_wmac_resources[0].start = AR913X_WMAC_BASE; + ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; + ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2); + ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2); ++ ++ ath79_wmac_data.external_reset = ar913x_wmac_reset; + } + + diff --git a/target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch b/target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch new file mode 100644 index 0000000..c91ecdf --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/202-MIPS-ath79-ar934x-wmac-revision.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -140,6 +140,8 @@ static void ar934x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = false; + else + ath79_wmac_data.is_clk_25mhz = true; ++ ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; + } + + static void qca955x_wmac_setup(void) diff --git a/target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch b/target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch new file mode 100644 index 0000000..713a191 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/203-MIPS-ath79-fix-restart.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -40,6 +40,7 @@ static char ath79_sys_type[ATH79_SYS_TYP + + static void ath79_restart(char *command) + { ++ local_irq_disable(); + ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); + for (;;) + if (cpu_wait) +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -132,6 +132,7 @@ static inline u32 ath79_pll_rr(unsigned + static inline void ath79_reset_wr(unsigned reg, u32 val) + { + __raw_writel(val, ath79_reset_base + reg); ++ (void) __raw_readl(ath79_reset_base + reg); /* flush */ + } + + static inline u32 ath79_reset_rr(unsigned reg) diff --git a/target/linux/ar71xx/patches-4.1/206-spi-ath79-make-chipselect-logic-more-flexible.patch b/target/linux/ar71xx/patches-4.1/206-spi-ath79-make-chipselect-logic-more-flexible.patch new file mode 100644 index 0000000..76c067a --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/206-spi-ath79-make-chipselect-logic-more-flexible.patch @@ -0,0 +1,191 @@ +From 7008284716403237f6bc7d7590b3ed073555bd56 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 11 Jan 2012 22:25:11 +0100 +Subject: [PATCH 34/34] spi/ath79: make chipselect logic more flexible + +Signed-off-by: Gabor Juhos +--- + arch/mips/ath79/mach-pb44.c | 6 ++ + .../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++- + drivers/spi/spi-ath79.c | 67 +++++++++++++------- + 8 files changed, 88 insertions(+), 23 deletions(-) + +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio + } + }; + ++static struct ath79_spi_controller_data pb44_spi0_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL, ++ .cs_line = 0, ++}; ++ + static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .controller_data = &pb44_spi0_data, + }, + }; + +--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h ++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h +@@ -16,8 +16,14 @@ struct ath79_spi_platform_data { + unsigned num_chipselect; + }; + ++enum ath79_spi_cs_type { ++ ATH79_SPI_CS_TYPE_INTERNAL, ++ ATH79_SPI_CS_TYPE_GPIO, ++}; ++ + struct ath79_spi_controller_data { +- unsigned gpio; ++ enum ath79_spi_cs_type cs_type; ++ unsigned cs_line; + }; + + #endif /* _ATH79_SPI_PLATFORM_H */ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -33,6 +33,8 @@ + #define ATH79_SPI_RRW_DELAY_FACTOR 12000 + #define MHZ (1000 * 1000) + ++#define ATH79_SPI_CS_LINE_MAX 2 ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; +@@ -67,6 +69,7 @@ static void ath79_spi_chipselect(struct + { + struct ath79_spi *sp = ath79_spidev_to_sp(spi); + int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; ++ struct ath79_spi_controller_data *cdata = spi->controller_data; + + if (is_active) { + /* set initial clock polarity */ +@@ -78,20 +81,24 @@ static void ath79_spi_chipselect(struct + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); + } + +- if (spi->chip_select) { +- struct ath79_spi_controller_data *cdata = spi->controller_data; +- +- /* SPI is normally active-low */ +- gpio_set_value(cdata->gpio, cs_high); +- } else { ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: + if (cs_high) +- sp->ioc_base |= AR71XX_SPI_IOC_CS0; ++ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line); + else +- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; ++ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line); + + ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); +- } ++ break; + ++ case ATH79_SPI_CS_TYPE_GPIO: ++ /* SPI is normally active-low */ ++ if (gpio_cansleep(cdata->cs_line)) ++ gpio_set_value_cansleep(cdata->cs_line, cs_high); ++ else ++ gpio_set_value(cdata->cs_line, cs_high); ++ break; ++ } + } + + static void ath79_spi_enable(struct ath79_spi *sp) +@@ -118,24 +125,30 @@ static void ath79_spi_disable(struct ath + static int ath79_spi_setup_cs(struct spi_device *spi) + { + struct ath79_spi_controller_data *cdata; ++ unsigned long flags; + int status; + + cdata = spi->controller_data; +- if (spi->chip_select && !cdata) ++ if (!cdata) + return -EINVAL; + + status = 0; +- if (spi->chip_select) { +- unsigned long flags; ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: ++ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX) ++ status = -EINVAL; ++ break; + ++ case ATH79_SPI_CS_TYPE_GPIO: + flags = GPIOF_DIR_OUT; + if (spi->mode & SPI_CS_HIGH) + flags |= GPIOF_INIT_LOW; + else + flags |= GPIOF_INIT_HIGH; + +- status = gpio_request_one(cdata->gpio, flags, ++ status = gpio_request_one(cdata->cs_line, flags, + dev_name(&spi->dev)); ++ break; + } + + return status; +@@ -143,9 +156,19 @@ static int ath79_spi_setup_cs(struct spi + + static void ath79_spi_cleanup_cs(struct spi_device *spi) + { +- if (spi->chip_select) { +- struct ath79_spi_controller_data *cdata = spi->controller_data; +- gpio_free(cdata->gpio); ++ struct ath79_spi_controller_data *cdata; ++ ++ cdata = spi->controller_data; ++ if (!cdata) ++ return; ++ ++ switch (cdata->cs_type) { ++ case ATH79_SPI_CS_TYPE_INTERNAL: ++ /* nothing to do */ ++ break; ++ case ATH79_SPI_CS_TYPE_GPIO: ++ gpio_free(cdata->cs_line); ++ break; + } + } + +@@ -210,6 +233,10 @@ static int ath79_spi_probe(struct platfo + unsigned long rate; + int ret; + ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -EINVAL; ++ + master = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (master == NULL) { + dev_err(&pdev->dev, "failed to allocate spi master\n"); +@@ -219,15 +246,11 @@ static int ath79_spi_probe(struct platfo + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + +- pdata = dev_get_platdata(&pdev->dev); +- + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; +- if (pdata) { +- master->bus_num = pdata->bus_num; +- master->num_chipselect = pdata->num_chipselect; +- } ++ master->bus_num = pdata->bus_num; ++ master->num_chipselect = pdata->num_chipselect; + + sp->bitbang.master = master; + sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ar71xx/patches-4.1/220-add_cpu_feature_overrides.patch b/target/linux/ar71xx/patches-4.1/220-add_cpu_feature_overrides.patch new file mode 100644 index 0000000..d925f92 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/220-add_cpu_feature_overrides.patch @@ -0,0 +1,28 @@ +--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h ++++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h +@@ -36,6 +36,7 @@ + #define cpu_has_mdmx 0 + #define cpu_has_mips3d 0 + #define cpu_has_smartmips 0 ++#define cpu_has_rixi 0 + + #define cpu_has_mips32r1 1 + #define cpu_has_mips32r2 1 +@@ -43,6 +44,7 @@ + #define cpu_has_mips64r2 0 + + #define cpu_has_mipsmt 0 ++#define cpu_has_userlocal 0 + + #define cpu_has_64bits 0 + #define cpu_has_64bit_zero_reg 0 +@@ -51,5 +53,9 @@ + + #define cpu_dcache_line_size() 32 + #define cpu_icache_line_size() 32 ++#define cpu_has_vtag_icache 0 ++#define cpu_has_dc_aliases 1 ++#define cpu_has_ic_fills_f_dc 0 ++#define cpu_has_pindexed_dcache 0 + + #endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */ diff --git a/target/linux/ar71xx/patches-4.1/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch b/target/linux/ar71xx/patches-4.1/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch new file mode 100644 index 0000000..0bc64b7 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/300-MIPS-add-MIPS_MACHINE_NONAME-macro.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/include/asm/mips_machine.h ++++ b/arch/mips/include/asm/mips_machine.h +@@ -36,6 +36,18 @@ static struct mips_machine machine_##_ty + .mach_setup = _setup, \ + }; + ++#define MIPS_MACHINE_NONAME(_type, _id, _setup) \ ++static const char machine_id_##_type[] __initconst \ ++ __aligned(1) = _id; \ ++static struct mips_machine machine_##_type \ ++ __used __section(.mips.machines.init) = \ ++{ \ ++ .mach_type = _type, \ ++ .mach_id = machine_id_##_type, \ ++ .mach_name = NULL, \ ++ .mach_setup = _setup, \ ++}; ++ + extern long __mips_machines_start; + extern long __mips_machines_end; + diff --git a/target/linux/ar71xx/patches-4.1/310-lib-add-rle-decompression.patch b/target/linux/ar71xx/patches-4.1/310-lib-add-rle-decompression.patch new file mode 100644 index 0000000..d23edf8 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/310-lib-add-rle-decompression.patch @@ -0,0 +1,124 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -241,6 +241,9 @@ config LZMA_COMPRESS + config LZMA_DECOMPRESS + tristate + ++config RLE_DECOMPRESS ++ tristate ++ + # + # These all provide a common interface (hence the apparent duplication with + # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -101,6 +101,7 @@ obj-$(CONFIG_XZ_DEC) += xz/ + obj-$(CONFIG_RAID6_PQ) += raid6/ + obj-$(CONFIG_LZMA_COMPRESS) += lzma/ + obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ ++obj-$(CONFIG_RLE_DECOMPRESS) += rle.o + + lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o + lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o +--- /dev/null ++++ b/include/linux/rle.h +@@ -0,0 +1,18 @@ ++#ifndef _RLE_H_ ++#define _RLE_H_ ++ ++#ifdef CONFIG_RLE_DECOMPRESS ++int rle_decode(const unsigned char *src, size_t srclen, ++ unsigned char *dst, size_t dstlen, ++ size_t *src_done, size_t *dst_done); ++#else ++static inline int ++rle_decode(const unsigned char *src, size_t srclen, ++ unsigned char *dst, size_t dstlen, ++ size_t *src_done, size_t *dst_done) ++{ ++ return -ENOTSUPP; ++} ++#endif /* CONFIG_RLE_DECOMPRESS */ ++ ++#endif /* _RLE_H_ */ +--- /dev/null ++++ b/lib/rle.c +@@ -0,0 +1,78 @@ ++/* ++ * RLE decoding routine ++ * ++ * Copyright (C) 2012 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++int rle_decode(const unsigned char *src, size_t srclen, ++ unsigned char *dst, size_t dstlen, ++ size_t *src_done, size_t *dst_done) ++{ ++ size_t srcpos, dstpos; ++ int ret; ++ ++ srcpos = 0; ++ dstpos = 0; ++ ret = -EINVAL; ++ ++ /* sanity checks */ ++ if (!src || !srclen || !dst || !dstlen) ++ goto out; ++ ++ while (1) { ++ char count; ++ ++ if (srcpos >= srclen) ++ break; ++ ++ count = (char) src[srcpos++]; ++ if (count == 0) { ++ ret = 0; ++ break; ++ } ++ ++ if (count > 0) { ++ unsigned char c; ++ ++ if (srcpos >= srclen) ++ break; ++ ++ c = src[srcpos++]; ++ ++ while (count--) { ++ if (dstpos >= dstlen) ++ break; ++ ++ dst[dstpos++] = c; ++ } ++ } else { ++ count *= -1; ++ ++ while (count--) { ++ if (srcpos >= srclen) ++ break; ++ if (dstpos >= dstlen) ++ break; ++ dst[dstpos++] = src[srcpos++]; ++ } ++ } ++ } ++ ++out: ++ if (src_done) ++ *src_done = srcpos; ++ if (dst_done) ++ *dst_done = dstpos; ++ ++ return ret; ++} ++ ++EXPORT_SYMBOL_GPL(rle_decode); diff --git a/target/linux/ar71xx/patches-4.1/401-mtd-physmap-add-lock-unlock.patch b/target/linux/ar71xx/patches-4.1/401-mtd-physmap-add-lock-unlock.patch new file mode 100644 index 0000000..db7b3ca --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/401-mtd-physmap-add-lock-unlock.patch @@ -0,0 +1,94 @@ +--- a/drivers/mtd/maps/physmap.c ++++ b/drivers/mtd/maps/physmap.c +@@ -31,6 +31,66 @@ struct physmap_flash_info { + int vpp_refcnt; + }; + ++static struct platform_device *physmap_map2pdev(struct map_info *map) ++{ ++ return (struct platform_device *) map->map_priv_1; ++} ++ ++static void physmap_lock(struct map_info *map) ++{ ++ struct platform_device *pdev; ++ struct physmap_flash_data *physmap_data; ++ ++ pdev = physmap_map2pdev(map); ++ physmap_data = pdev->dev.platform_data; ++ physmap_data->lock(pdev); ++} ++ ++static void physmap_unlock(struct map_info *map) ++{ ++ struct platform_device *pdev; ++ struct physmap_flash_data *physmap_data; ++ ++ pdev = physmap_map2pdev(map); ++ physmap_data = pdev->dev.platform_data; ++ physmap_data->unlock(pdev); ++} ++ ++static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs) ++{ ++ map_word ret; ++ ++ physmap_lock(map); ++ ret = inline_map_read(map, ofs); ++ physmap_unlock(map); ++ ++ return ret; ++} ++ ++static void physmap_flash_write_lock(struct map_info *map, map_word d, ++ unsigned long ofs) ++{ ++ physmap_lock(map); ++ inline_map_write(map, d, ofs); ++ physmap_unlock(map); ++} ++ ++static void physmap_flash_copy_from_lock(struct map_info *map, void *to, ++ unsigned long from, ssize_t len) ++{ ++ physmap_lock(map); ++ inline_map_copy_from(map, to, from, len); ++ physmap_unlock(map); ++} ++ ++static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to, ++ const void *from, ssize_t len) ++{ ++ physmap_lock(map); ++ inline_map_copy_to(map, to, from, len); ++ physmap_unlock(map); ++} ++ + static int physmap_flash_remove(struct platform_device *dev) + { + struct physmap_flash_info *info; +@@ -153,6 +213,13 @@ static int physmap_flash_probe(struct pl + + simple_map_init(&info->map[i]); + ++ if (physmap_data->lock && physmap_data->unlock) { ++ info->map[i].read = physmap_flash_read_lock; ++ info->map[i].write = physmap_flash_write_lock; ++ info->map[i].copy_from = physmap_flash_copy_from_lock; ++ info->map[i].copy_to = physmap_flash_copy_to_lock; ++ } ++ + probe_type = rom_probe_types; + if (physmap_data->probe_type == NULL) { + for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++) +--- a/include/linux/mtd/physmap.h ++++ b/include/linux/mtd/physmap.h +@@ -25,6 +25,8 @@ struct physmap_flash_data { + unsigned int width; + int (*init)(struct platform_device *); + void (*exit)(struct platform_device *); ++ void (*lock)(struct platform_device *); ++ void (*unlock)(struct platform_device *); + void (*set_vpp)(struct platform_device *, int); + unsigned int nr_parts; + unsigned int pfow_base; diff --git a/target/linux/ar71xx/patches-4.1/402-mtd-SST39VF6401B-support.patch b/target/linux/ar71xx/patches-4.1/402-mtd-SST39VF6401B-support.patch new file mode 100644 index 0000000..0d483ab --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/402-mtd-SST39VF6401B-support.patch @@ -0,0 +1,29 @@ +--- a/drivers/mtd/chips/jedec_probe.c ++++ b/drivers/mtd/chips/jedec_probe.c +@@ -148,6 +148,7 @@ + #define SST39LF160 0x2782 + #define SST39VF1601 0x234b + #define SST39VF3201 0x235b ++#define SST39VF6401B 0x236d + #define SST39WF1601 0x274b + #define SST39WF1602 0x274a + #define SST39LF512 0x00D4 +@@ -1569,6 +1570,18 @@ static const struct amd_flash_info jedec + ERASEINFO(0x10000,64), + } + }, { ++ .mfr_id = CFI_MFR_SST, ++ .dev_id = SST39VF6401B, ++ .name = "SST 39VF6401B", ++ .devtypes = CFI_DEVICETYPE_X16, ++ .uaddr = MTD_UADDR_0xAAAA_0x5555, ++ .dev_size = SIZE_8MiB, ++ .cmd_set = P_ID_AMD_STD, ++ .nr_regions = 1, ++ .regions = { ++ ERASEINFO(0x10000,128) ++ } ++ }, { + .mfr_id = CFI_MFR_ST, + .dev_id = M29F800AB, + .name = "ST M29F800AB", diff --git a/target/linux/ar71xx/patches-4.1/403-mtd_fix_cfi_cmdset_0002_status_check.patch b/target/linux/ar71xx/patches-4.1/403-mtd_fix_cfi_cmdset_0002_status_check.patch new file mode 100644 index 0000000..1ccce4e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/403-mtd_fix_cfi_cmdset_0002_status_check.patch @@ -0,0 +1,69 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1632,8 +1632,8 @@ static int __xipram do_write_oneword(str + break; + } + +- if (chip_ready(map, adr)) +- break; ++ if (chip_good(map, adr, datum)) ++ goto enable_xip; + + /* Latency issues. Drop the lock, wait a while and retry */ + UDELAY(map, chip, adr, 1); +@@ -1649,6 +1649,8 @@ static int __xipram do_write_oneword(str + + ret = -EIO; + } ++ ++ enable_xip: + xip_enable(map, chip, adr); + op_done: + if (mode == FL_OTP_WRITE) +@@ -2227,7 +2229,6 @@ static int cfi_amdstd_panic_write(struct + return 0; + } + +- + /* + * Handle devices with one erase region, that only implement + * the chip erase command. +@@ -2291,8 +2292,8 @@ static int __xipram do_erase_chip(struct + chip->erase_suspended = 0; + } + +- if (chip_ready(map, adr)) +- break; ++ if (chip_good(map, adr, map_word_ff(map))) ++ goto op_done; + + if (time_after(jiffies, timeo)) { + printk(KERN_WARNING "MTD %s(): software timeout\n", +@@ -2312,6 +2313,7 @@ static int __xipram do_erase_chip(struct + ret = -EIO; + } + ++ op_done: + chip->state = FL_READY; + xip_enable(map, chip, adr); + DISABLE_VPP(map); +@@ -2380,9 +2382,9 @@ static int __xipram do_erase_oneblock(st + chip->erase_suspended = 0; + } + +- if (chip_ready(map, adr)) { ++ if (chip_good(map, adr, map_word_ff(map))) { + xip_enable(map, chip, adr); +- break; ++ goto op_done; + } + + if (time_after(jiffies, timeo)) { +@@ -2404,6 +2406,7 @@ static int __xipram do_erase_oneblock(st + ret = -EIO; + } + ++ op_done: + chip->state = FL_READY; + DISABLE_VPP(map); + put_chip(map, chip, adr); diff --git a/target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch b/target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch new file mode 100644 index 0000000..8809256 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch @@ -0,0 +1,25 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -179,6 +179,12 @@ config MTD_BCM47XX_PARTS + This provides partitions parser for devices based on BCM47xx + boards. + ++config MTD_CYBERTAN_PARTS ++ tristate "Cybertan partitioning support" ++ depends on ATH79 ++ ---help--- ++ Cybertan partitioning support ++ + config MTD_MYLOADER_PARTS + tristate "MyLoader partition parsing" + depends on ADM5120 || ATH25 || ATH79 +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/ar71xx/patches-4.1/405-mtd-tp-link-partition-parser.patch b/target/linux/ar71xx/patches-4.1/405-mtd-tp-link-partition-parser.patch new file mode 100644 index 0000000..04c9cee --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/405-mtd-tp-link-partition-parser.patch @@ -0,0 +1,25 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -201,6 +201,12 @@ config MTD_MYLOADER_PARTS + You will still need the parsing functions to be called by the driver + for your particular device. It won't happen automatically. + ++config MTD_TPLINK_PARTS ++ tristate "TP-Link AR7XXX/AR9XXX partitioning support" ++ depends on ATH79 ++ ---help--- ++ TBD. ++ + comment "User Modules And Translation Layers" + + # +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o + obj-$(CONFIG_MTD_CYBERTAN_PARTS) += cybertan_part.o + + # 'Users' - code which presents functionality to userspace. diff --git a/target/linux/ar71xx/patches-4.1/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-4.1/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch new file mode 100644 index 0000000..bdfa887 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch @@ -0,0 +1,23 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -234,7 +234,9 @@ static int m25p_probe(struct spi_device + + ppdata.of_node = spi->dev.of_node; + +- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, ++ return mtd_device_parse_register(&flash->mtd, ++ data ? data->part_probes : NULL, ++ &ppdata, + data ? data->parts : NULL, + data ? data->nr_parts : 0); + } +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -24,6 +24,7 @@ struct flash_platform_data { + unsigned int nr_parts; + + char *type; ++ const char **part_probes; + + /* we'll likely add more ... use JEDEC IDs, etc */ + }; diff --git a/target/linux/ar71xx/patches-4.1/408-mtd-redboot_partition_scan.patch b/target/linux/ar71xx/patches-4.1/408-mtd-redboot_partition_scan.patch new file mode 100644 index 0000000..cd41e7c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/408-mtd-redboot_partition_scan.patch @@ -0,0 +1,44 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -76,12 +76,18 @@ static int parse_redboot_partitions(stru + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; + while (mtd_block_isbad(master, offset)) { + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; +@@ -94,10 +100,6 @@ static int parse_redboot_partitions(stru + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; + + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); +@@ -170,6 +172,11 @@ static int parse_redboot_partitions(stru + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block :) */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; diff --git a/target/linux/ar71xx/patches-4.1/409-mtd-rb4xx_nand_driver.patch b/target/linux/ar71xx/patches-4.1/409-mtd-rb4xx_nand_driver.patch new file mode 100644 index 0000000..408086f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/409-mtd-rb4xx_nand_driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -530,4 +530,8 @@ config MTD_NAND_HISI504 + help + Enables support for NAND controller on Hisilicon SoC Hip04. + ++config MTD_NAND_RB4XX ++ tristate "NAND flash driver for RouterBoard 4xx series" ++ depends on MTD_NAND && ATH79_MACH_RB4XX ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27 + obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o ++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o + obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.1/410-mtd-rb750-nand-driver.patch b/target/linux/ar71xx/patches-4.1/410-mtd-rb750-nand-driver.patch new file mode 100644 index 0000000..666f7d2 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/410-mtd-rb750-nand-driver.patch @@ -0,0 +1,21 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -534,4 +534,8 @@ config MTD_NAND_RB4XX + tristate "NAND flash driver for RouterBoard 4xx series" + depends on MTD_NAND && ATH79_MACH_RB4XX + ++config MTD_NAND_RB750 ++ tristate "NAND flash driver for the RouterBoard 750" ++ depends on MTD_NAND && ATH79_MACH_RB750 ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o + obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o ++obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o + obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.1/411-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/ar71xx/patches-4.1/411-mtd-cfi_cmdset_0002-force-word-write.patch new file mode 100644 index 0000000..39c5478 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/411-mtd-cfi_cmdset_0002-force-word-write.patch @@ -0,0 +1,61 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -40,7 +40,7 @@ + #include + + #define AMD_BOOTLOC_BUG +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + #define MAX_WORD_RETRIES 3 + +@@ -51,7 +51,9 @@ + + static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); + static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#if !FORCE_WORD_WRITE + static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); ++#endif + static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); + static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); + static void cfi_amdstd_sync (struct mtd_info *); +@@ -202,6 +204,7 @@ static void fixup_amd_bootblock(struct m + } + #endif + ++#if !FORCE_WORD_WRITE + static void fixup_use_write_buffers(struct mtd_info *mtd) + { + struct map_info *map = mtd->priv; +@@ -211,6 +214,7 @@ static void fixup_use_write_buffers(stru + mtd->_write = cfi_amdstd_write_buffers; + } + } ++#endif /* !FORCE_WORD_WRITE */ + + /* Atmel chips don't use the same PRI format as AMD chips */ + static void fixup_convert_atmel_pri(struct mtd_info *mtd) +@@ -1791,6 +1795,7 @@ static int cfi_amdstd_write_words(struct + /* + * FIXME: interleaved mode not tested, and probably not supported! + */ ++#if !FORCE_WORD_WRITE + static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, + unsigned long adr, const u_char *buf, + int len) +@@ -1919,7 +1924,6 @@ static int __xipram do_write_buffer(stru + return ret; + } + +- + static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) + { +@@ -1994,6 +1998,7 @@ static int cfi_amdstd_write_buffers(stru + + return 0; + } ++#endif /* !FORCE_WORD_WRITE */ + + /* + * Wait for the flash chip to become ready to write data diff --git a/target/linux/ar71xx/patches-4.1/412-mtd-m25p80-zero-partition-parser-data.patch b/target/linux/ar71xx/patches-4.1/412-mtd-m25p80-zero-partition-parser-data.patch new file mode 100644 index 0000000..7cade53 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/412-mtd-m25p80-zero-partition-parser-data.patch @@ -0,0 +1,10 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -232,6 +232,7 @@ static int m25p_probe(struct spi_device + if (ret) + return ret; + ++ memset(&ppdata, '\0', sizeof(ppdata)); + ppdata.of_node = spi->dev.of_node; + + return mtd_device_parse_register(&flash->mtd, diff --git a/target/linux/ar71xx/patches-4.1/413-mtd-ar934x-nand-driver.patch b/target/linux/ar71xx/patches-4.1/413-mtd-ar934x-nand-driver.patch new file mode 100644 index 0000000..44fdba4 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/413-mtd-ar934x-nand-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -538,4 +538,12 @@ config MTD_NAND_RB750 + tristate "NAND flash driver for the RouterBoard 750" + depends on MTD_NAND && ATH79_MACH_RB750 + ++config MTD_NAND_AR934X ++ tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs" ++ depends on (SOC_AR934X || SOC_QCA955X) ++ ++config MTD_NAND_AR934X_HW_ECC ++ bool "Hardware ECC support for the AR934X NAND Controller (EXPERIMENTAL)" ++ depends on MTD_NAND_AR934X ++ + endif # MTD_NAND +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams- + obj-$(CONFIG_MTD_NAND_DENALI) += denali.o + obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o + obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o ++obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nfc.o + obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o + obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o + obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o diff --git a/target/linux/ar71xx/patches-4.1/414-mtd-rb91x-nand-driver.patch b/target/linux/ar71xx/patches-4.1/414-mtd-rb91x-nand-driver.patch new file mode 100644 index 0000000..bad95c1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/414-mtd-rb91x-nand-driver.patch @@ -0,0 +1,23 @@ +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -538,6 +538,10 @@ config MTD_NAND_RB750 + tristate "NAND flash driver for the RouterBoard 750" + depends on MTD_NAND && ATH79_MACH_RB750 + ++config MTD_NAND_RB91X ++ tristate "NAND flash driver for the RouterBOARD 91x series" ++ depends on MTD_NAND && ATH79_MACH_RB91X ++ + config MTD_NAND_AR934X + tristate "NAND flash driver for the Qualcomm Atheros AR934x/QCA955x SoCs" + depends on (SOC_AR934X || SOC_QCA955X) +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -35,6 +35,7 @@ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nan + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o + obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o + obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o ++obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o + obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/target/linux/ar71xx/patches-4.1/420-net-ar71xx_mac_driver.patch b/target/linux/ar71xx/patches-4.1/420-net-ar71xx_mac_driver.patch new file mode 100644 index 0000000..5da869a --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/420-net-ar71xx_mac_driver.patch @@ -0,0 +1,28 @@ +--- a/drivers/net/ethernet/atheros/Kconfig ++++ b/drivers/net/ethernet/atheros/Kconfig +@@ -5,7 +5,7 @@ + config NET_VENDOR_ATHEROS + bool "Atheros devices" + default y +- depends on PCI ++ depends on (PCI || ATH79) + ---help--- + If you have a network (Ethernet) card belonging to this class, say Y + and read the Ethernet-HOWTO, available from +@@ -80,4 +80,6 @@ config ALX + To compile this driver as a module, choose M here. The module + will be called alx. + ++source drivers/net/ethernet/atheros/ag71xx/Kconfig ++ + endif # NET_VENDOR_ATHEROS +--- a/drivers/net/ethernet/atheros/Makefile ++++ b/drivers/net/ethernet/atheros/Makefile +@@ -2,6 +2,7 @@ + # Makefile for the Atheros network device drivers. + # + ++obj-$(CONFIG_AG71XX) += ag71xx/ + obj-$(CONFIG_ATL1) += atlx/ + obj-$(CONFIG_ATL2) += atlx/ + obj-$(CONFIG_ATL1E) += atl1e/ diff --git a/target/linux/ar71xx/patches-4.1/422-dsa-trailer-tag-validation-fix.patch b/target/linux/ar71xx/patches-4.1/422-dsa-trailer-tag-validation-fix.patch new file mode 100644 index 0000000..eeeeaf5 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/422-dsa-trailer-tag-validation-fix.patch @@ -0,0 +1,11 @@ +--- a/net/dsa/tag_trailer.c ++++ b/net/dsa/tag_trailer.c +@@ -84,7 +84,7 @@ static int trailer_rcv(struct sk_buff *s + + trailer = skb_tail_pointer(skb) - 4; + if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 || +- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00) ++ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00) + goto out_drop; + + source_port = trailer[1] & 7; diff --git a/target/linux/ar71xx/patches-4.1/423-dsa-add-88e6063-driver.patch b/target/linux/ar71xx/patches-4.1/423-dsa-add-88e6063-driver.patch new file mode 100644 index 0000000..1348cd9 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/423-dsa-add-88e6063-driver.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -13,6 +13,13 @@ config NET_DSA_MV88E6060 + This enables support for the Marvell 88E6060 ethernet switch + chip. + ++config NET_DSA_MV88E6063 ++ bool "Marvell 88E6063 ethernet switch chip support" ++ select NET_DSA_TAG_TRAILER ++ ---help--- ++ This enables support for the Marvell 88E6063 ethernet switch ++ chip ++ + config NET_DSA_MV88E6XXX_NEED_PPU + bool + default n +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -1,4 +1,5 @@ + obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o ++obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o + obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx_drv.o + mv88e6xxx_drv-y += mv88e6xxx.o + ifdef CONFIG_NET_DSA_MV88E6123_61_65 diff --git a/target/linux/ar71xx/patches-4.1/425-net-phy-at803x-allow-to-configure-via-pdata.patch b/target/linux/ar71xx/patches-4.1/425-net-phy-at803x-allow-to-configure-via-pdata.patch new file mode 100644 index 0000000..53abcc3 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/425-net-phy-at803x-allow-to-configure-via-pdata.patch @@ -0,0 +1,180 @@ +--- a/drivers/net/phy/at803x.c ++++ b/drivers/net/phy/at803x.c +@@ -12,12 +12,14 @@ + */ + + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + + #define AT803X_INTR_ENABLE 0x12 + #define AT803X_INTR_STATUS 0x13 +@@ -34,8 +36,16 @@ + #define AT803X_INER 0x0012 + #define AT803X_INER_INIT 0xec00 + #define AT803X_INSR 0x0013 ++ ++#define AT803X_PCS_SMART_EEE_CTRL3 0x805D ++#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_MASK 0x3 ++#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT 12 ++#define AT803X_SMART_EEE_CTRL3_LPI_EN BIT(8) ++ + #define AT803X_DEBUG_ADDR 0x1D + #define AT803X_DEBUG_DATA 0x1E ++#define AT803X_DBG0_REG 0x00 ++#define AT803X_DEBUG_RGMII_RX_CLK_DLY BIT(8) + #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05 + #define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8) + +@@ -50,6 +60,7 @@ MODULE_LICENSE("GPL"); + struct at803x_priv { + bool phy_reset:1; + struct gpio_desc *gpiod_reset; ++ int prev_speed; + }; + + struct at803x_context { +@@ -61,6 +72,43 @@ struct at803x_context { + u16 led_control; + }; + ++static u16 ++at803x_dbg_reg_rmw(struct phy_device *phydev, u16 reg, u16 clear, u16 set) ++{ ++ struct mii_bus *bus = phydev->bus; ++ int val; ++ ++ mutex_lock(&bus->mdio_lock); ++ ++ bus->write(bus, phydev->addr, AT803X_DEBUG_ADDR, reg); ++ val = bus->read(bus, phydev->addr, AT803X_DEBUG_DATA); ++ if (val < 0) { ++ val = 0xffff; ++ goto out; ++ } ++ ++ val &= ~clear; ++ val |= set; ++ bus->write(bus, phydev->addr, AT803X_DEBUG_DATA, val); ++ ++out: ++ mutex_unlock(&bus->mdio_lock); ++ return val; ++} ++ ++static inline void ++at803x_dbg_reg_set(struct phy_device *phydev, u16 reg, u16 set) ++{ ++ at803x_dbg_reg_rmw(phydev, reg, 0, set); ++} ++ ++static inline void ++at803x_dbg_reg_clr(struct phy_device *phydev, u16 reg, u16 clear) ++{ ++ at803x_dbg_reg_rmw(phydev, reg, clear, 0); ++} ++ ++ + /* save relevant PHY registers to private copy */ + static void at803x_context_save(struct phy_device *phydev, + struct at803x_context *context) +@@ -209,8 +257,16 @@ static int at803x_probe(struct phy_devic + return 0; + } + ++static void at803x_disable_smarteee(struct phy_device *phydev) ++{ ++ phy_write_mmd(phydev, MDIO_MMD_PCS, AT803X_PCS_SMART_EEE_CTRL3, ++ 1 << AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT); ++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); ++} ++ + static int at803x_config_init(struct phy_device *phydev) + { ++ struct at803x_platform_data *pdata; + int ret; + + ret = genphy_config_init(phydev); +@@ -228,6 +284,26 @@ static int at803x_config_init(struct phy + return ret; + } + ++ pdata = dev_get_platdata(&phydev->dev); ++ if (pdata) { ++ if (pdata->disable_smarteee) ++ at803x_disable_smarteee(phydev); ++ ++ if (pdata->enable_rgmii_rx_delay) ++ at803x_dbg_reg_set(phydev, AT803X_DBG0_REG, ++ AT803X_DEBUG_RGMII_RX_CLK_DLY); ++ else ++ at803x_dbg_reg_clr(phydev, AT803X_DBG0_REG, ++ AT803X_DEBUG_RGMII_RX_CLK_DLY); ++ ++ if (pdata->enable_rgmii_tx_delay) ++ at803x_dbg_reg_set(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL, ++ AT803X_DEBUG_RGMII_TX_CLK_DLY); ++ else ++ at803x_dbg_reg_clr(phydev, AT803X_DEBUG_SYSTEM_MODE_CTRL, ++ AT803X_DEBUG_RGMII_TX_CLK_DLY); ++ } ++ + return 0; + } + +@@ -259,6 +335,8 @@ static int at803x_config_intr(struct phy + static void at803x_link_change_notify(struct phy_device *phydev) + { + struct at803x_priv *priv = phydev->priv; ++ struct at803x_platform_data *pdata; ++ pdata = dev_get_platdata(&phydev->dev); + + /* + * Conduct a hardware reset for AT8030 every time a link loss is +@@ -289,6 +367,26 @@ static void at803x_link_change_notify(st + priv->phy_reset = false; + } + } ++ if (pdata && pdata->fixup_rgmii_tx_delay && ++ phydev->speed != priv->prev_speed) { ++ switch (phydev->speed) { ++ case SPEED_10: ++ case SPEED_100: ++ at803x_dbg_reg_set(phydev, ++ AT803X_DEBUG_SYSTEM_MODE_CTRL, ++ AT803X_DEBUG_RGMII_TX_CLK_DLY); ++ break; ++ case SPEED_1000: ++ at803x_dbg_reg_clr(phydev, ++ AT803X_DEBUG_SYSTEM_MODE_CTRL, ++ AT803X_DEBUG_RGMII_TX_CLK_DLY); ++ break; ++ default: ++ break; ++ } ++ ++ priv->prev_speed = phydev->speed; ++ } + } + + static struct phy_driver at803x_driver[] = { +--- /dev/null ++++ b/include/linux/platform_data/phy-at803x.h +@@ -0,0 +1,11 @@ ++#ifndef _PHY_AT803X_PDATA_H ++#define _PHY_AT803X_PDATA_H ++ ++struct at803x_platform_data { ++ int disable_smarteee:1; ++ int enable_rgmii_tx_delay:1; ++ int enable_rgmii_rx_delay:1; ++ int fixup_rgmii_tx_delay:1; ++}; ++ ++#endif /* _PHY_AT803X_PDATA_H */ diff --git a/target/linux/ar71xx/patches-4.1/430-drivers-link-spi-before-mtd.patch b/target/linux/ar71xx/patches-4.1/430-drivers-link-spi-before-mtd.patch new file mode 100644 index 0000000..02c7064 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/430-drivers-link-spi-before-mtd.patch @@ -0,0 +1,12 @@ +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -71,8 +71,8 @@ obj-$(CONFIG_IDE) += ide/ + obj-$(CONFIG_SCSI) += scsi/ + obj-$(CONFIG_ATA) += ata/ + obj-$(CONFIG_TARGET_CORE) += target/ +-obj-$(CONFIG_MTD) += mtd/ + obj-$(CONFIG_SPI) += spi/ ++obj-$(CONFIG_MTD) += mtd/ + obj-$(CONFIG_SPMI) += spmi/ + obj-y += hsi/ + obj-y += net/ diff --git a/target/linux/ar71xx/patches-4.1/431-spi-add-various-flags.patch b/target/linux/ar71xx/patches-4.1/431-spi-add-various-flags.patch new file mode 100644 index 0000000..8b25c93 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/431-spi-add-various-flags.patch @@ -0,0 +1,19 @@ +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -618,6 +618,8 @@ struct spi_transfer { + unsigned cs_change:1; + unsigned tx_nbits:3; + unsigned rx_nbits:3; ++ unsigned verify:1; ++ unsigned fast_write:1; + #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */ + #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */ + #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */ +@@ -663,6 +665,7 @@ struct spi_message { + struct spi_device *spi; + + unsigned is_dma_mapped:1; ++ unsigned fast_read:1; + + /* REVISIT: we might want a flag affecting the behavior of the + * last transfer ... allowing things like "read 16 bit length L" diff --git a/target/linux/ar71xx/patches-4.1/432-spi-rb4xx-spi-driver.patch b/target/linux/ar71xx/patches-4.1/432-spi-rb4xx-spi-driver.patch new file mode 100644 index 0000000..2870e19 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/432-spi-rb4xx-spi-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -457,6 +457,12 @@ config SPI_QUP + This driver can also be built as a module. If so, the module + will be called spi_qup. + ++config SPI_RB4XX ++ tristate "Mikrotik RB4XX SPI master" ++ depends on SPI_MASTER && ATH79_MACH_RB4XX ++ help ++ SPI controller driver for the Mikrotik RB4xx series boards. ++ + config SPI_S3C24XX + tristate "Samsung S3C24XX series SPI" + depends on ARCH_S3C24XX +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -65,6 +65,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_ + spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o + obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o + obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o ++obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o + obj-$(CONFIG_SPI_QUP) += spi-qup.o + obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o + obj-$(CONFIG_SPI_RSPI) += spi-rspi.o diff --git a/target/linux/ar71xx/patches-4.1/433-spi-rb4xx-cpld-driver.patch b/target/linux/ar71xx/patches-4.1/433-spi-rb4xx-cpld-driver.patch new file mode 100644 index 0000000..ccce5b1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/433-spi-rb4xx-cpld-driver.patch @@ -0,0 +1,26 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -676,6 +676,13 @@ config SPI_TLE62X0 + sysfs interface, with each line presented as a kind of GPIO + exposing both switch control and diagnostic feedback. + ++config SPI_RB4XX_CPLD ++ tristate "MikroTik RB4XX CPLD driver" ++ depends on ATH79_MACH_RB4XX ++ help ++ SPI driver for the Xilinx CPLD chip present on the ++ MikroTik RB4xx boards. ++ + # + # Add new SPI protocol masters in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -66,6 +66,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_ + obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o + obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o + obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o ++obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o + obj-$(CONFIG_SPI_QUP) += spi-qup.o + obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o + obj-$(CONFIG_SPI_RSPI) += spi-rspi.o diff --git a/target/linux/ar71xx/patches-4.1/434-spi-ap83_spi_controller.patch b/target/linux/ar71xx/patches-4.1/434-spi-ap83_spi_controller.patch new file mode 100644 index 0000000..a67e808 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/434-spi-ap83_spi_controller.patch @@ -0,0 +1,27 @@ +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o + # SPI master controller drivers (bus) + obj-$(CONFIG_SPI_ALTERA) += spi-altera.o + obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o ++obj-$(CONFIG_SPI_AP83) += spi-ap83.o + obj-$(CONFIG_SPI_ATH79) += spi-ath79.o + obj-$(CONFIG_SPI_AU1550) += spi-au1550.o + obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -59,6 +59,14 @@ config SPI_ALTERA + help + This is the driver for the Altera SPI Controller. + ++config SPI_AP83 ++ tristate "Atheros AP83 specific SPI Controller" ++ depends on SPI_MASTER && ATH79_MACH_AP83 ++ select SPI_BITBANG ++ help ++ This is a specific SPI controller driver for the Atheros AP83 ++ reference board. ++ + config SPI_ATH79 + tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver" + depends on ATH79 && GPIOLIB diff --git a/target/linux/ar71xx/patches-4.1/435-spi-vsc7385_driver.patch b/target/linux/ar71xx/patches-4.1/435-spi-vsc7385_driver.patch new file mode 100644 index 0000000..f860dfe --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/435-spi-vsc7385_driver.patch @@ -0,0 +1,24 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -691,6 +691,11 @@ config SPI_RB4XX_CPLD + SPI driver for the Xilinx CPLD chip present on the + MikroTik RB4xx boards. + ++config SPI_VSC7385 ++ tristate "Vitesse VSC7385 ethernet switch driver" ++ help ++ SPI driver for the Vitesse VSC7385 ethernet switch. ++ + # + # Add new SPI protocol masters in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -90,6 +90,7 @@ obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi- + obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o + obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o + obj-$(CONFIG_SPI_TXX9) += spi-txx9.o ++obj-$(CONFIG_SPI_VSC7385) += spi-vsc7385.o + obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o + obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o diff --git a/target/linux/ar71xx/patches-4.1/440-leds-wndr3700-usb-led-driver.patch b/target/linux/ar71xx/patches-4.1/440-leds-wndr3700-usb-led-driver.patch new file mode 100644 index 0000000..77ed60e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/440-leds-wndr3700-usb-led-driver.patch @@ -0,0 +1,26 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -534,6 +534,13 @@ config LEDS_PM8941_WLED + This option enables support for the 'White' LED block + on Qualcomm PM8941 PMICs. + ++config LEDS_WNDR3700_USB ++ tristate "NETGEAR WNDR3700 USB LED driver" ++ depends on LEDS_CLASS && ATH79_MACH_WNDR3700 ++ help ++ This option enables support for the USB LED found on the ++ NETGEAR WNDR3700 board. ++ + comment "LED Triggers" + source "drivers/leds/trigger/Kconfig" + +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -43,6 +43,7 @@ obj-$(CONFIG_LEDS_DA9052) += leds-da905 + obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o + obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o + obj-$(CONFIG_LEDS_PWM) += leds-pwm.o ++obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o + obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o + obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o + obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o diff --git a/target/linux/ar71xx/patches-4.1/441-leds-rb750-led-driver.patch b/target/linux/ar71xx/patches-4.1/441-leds-rb750-led-driver.patch new file mode 100644 index 0000000..55ea26b --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/441-leds-rb750-led-driver.patch @@ -0,0 +1,23 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -541,6 +541,10 @@ config LEDS_WNDR3700_USB + This option enables support for the USB LED found on the + NETGEAR WNDR3700 board. + ++config LEDS_RB750 ++ tristate "LED driver for the Mikrotik RouterBOARD 750" ++ depends on LEDS_CLASS && ATH79_MACH_RB750 ++ + comment "LED Triggers" + source "drivers/leds/trigger/Kconfig" + +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -50,6 +50,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt359 + obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o + obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o + obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o ++obj-$(CONFIG_LEDS_RB750) += leds-rb750.o + obj-$(CONFIG_LEDS_NS2) += leds-ns2.o + obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o + obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o diff --git a/target/linux/ar71xx/patches-4.1/450-gpio-nxp-74hc153-gpio-chip-driver.patch b/target/linux/ar71xx/patches-4.1/450-gpio-nxp-74hc153-gpio-chip-driver.patch new file mode 100644 index 0000000..30b1c65 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/450-gpio-nxp-74hc153-gpio-chip-driver.patch @@ -0,0 +1,25 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -988,4 +988,12 @@ config GPIO_VIPERBOARD + + endmenu + ++comment "Other GPIO expanders" ++ ++config GPIO_NXP_74HC153 ++ tristate "NXP 74HC153 Dual 4-input multiplexer" ++ help ++ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This ++ provides a GPIO interface supporting input mode only. ++ + endif +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -64,6 +64,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2 + obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o + obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o + obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o ++obj-$(CONFIG_GPIO_NXP_74HC153) += gpio-nxp-74hc153.o + obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o + obj-$(CONFIG_GPIO_OMAP) += gpio-omap.o + obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o diff --git a/target/linux/ar71xx/patches-4.1/451-gpio-74x164-improve-platform-device-support.patch b/target/linux/ar71xx/patches-4.1/451-gpio-74x164-improve-platform-device-support.patch new file mode 100644 index 0000000..95e5b5a --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/451-gpio-74x164-improve-platform-device-support.patch @@ -0,0 +1,111 @@ +--- a/drivers/gpio/gpio-74x164.c ++++ b/drivers/gpio/gpio-74x164.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -107,8 +108,18 @@ static int gen_74x164_direction_output(s + static int gen_74x164_probe(struct spi_device *spi) + { + struct gen_74x164_chip *chip; ++ struct gen_74x164_chip_platform_data *pdata; ++ struct device_node *np; + int ret; + ++ pdata = spi->dev.platform_data; ++ np = spi->dev.of_node; ++ ++ if (!np && !pdata) { ++ dev_err(&spi->dev, "No configuration data available.\n"); ++ return -EINVAL; ++ } ++ + /* + * bits_per_word cannot be configured in platform data + */ +@@ -130,18 +141,28 @@ static int gen_74x164_probe(struct spi_d + chip->gpio_chip.set = gen_74x164_set_value; + chip->gpio_chip.base = -1; + +- if (of_property_read_u32(spi->dev.of_node, "registers-number", +- &chip->registers)) { +- dev_err(&spi->dev, +- "Missing registers-number property in the DT.\n"); +- return -EINVAL; ++ if (np) { ++ if (of_property_read_u32(spi->dev.of_node, "registers-number", &chip->registers)) { ++ dev_err(&spi->dev, "Missing registers-number property in the DT.\n"); ++ ret = -EINVAL; ++ goto exit_destroy; ++ } ++ } else if (pdata) { ++ chip->gpio_chip.base = pdata->base; ++ chip->registers = pdata->num_registers; + } + ++ if (!chip->registers) ++ chip->registers = 1; ++ + chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; + chip->buffer = devm_kzalloc(&spi->dev, chip->registers, GFP_KERNEL); + if (!chip->buffer) + return -ENOMEM; + ++ if (pdata && pdata->init_data) ++ memcpy(chip->buffer, pdata->init_data, chip->registers); ++ + chip->gpio_chip.can_sleep = true; + chip->gpio_chip.dev = &spi->dev; + chip->gpio_chip.owner = THIS_MODULE; +@@ -174,17 +195,19 @@ static int gen_74x164_remove(struct spi_ + return 0; + } + ++#ifdef CONFIG_OF + static const struct of_device_id gen_74x164_dt_ids[] = { + { .compatible = "fairchild,74hc595" }, + {}, + }; + MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids); ++#endif /* CONFIG_OF */ + + static struct spi_driver gen_74x164_driver = { + .driver = { + .name = "74x164", + .owner = THIS_MODULE, +- .of_match_table = gen_74x164_dt_ids, ++ .of_match_table = of_match_ptr(gen_74x164_dt_ids), + }, + .probe = gen_74x164_probe, + .remove = gen_74x164_remove, +--- /dev/null ++++ b/include/linux/spi/74x164.h +@@ -0,0 +1,13 @@ ++#ifndef LINUX_SPI_74X164_H ++#define LINUX_SPI_74X164_H ++ ++struct gen_74x164_chip_platform_data { ++ /* number assigned to the first GPIO */ ++ unsigned base; ++ /* number of chained registers */ ++ unsigned num_registers; ++ /* address of a buffer containing initial data */ ++ u8 *init_data; ++}; ++ ++#endif +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -941,7 +941,7 @@ menu "SPI GPIO expanders" + + config GPIO_74X164 + tristate "74x164 serial-in/parallel-out 8-bits shift register" +- depends on SPI_MASTER && OF ++ depends on SPI_MASTER + help + Driver for 74x164 compatible serial-in/parallel-out 8-outputs + shift registers. This driver can be used to provide access diff --git a/target/linux/ar71xx/patches-4.1/452-gpio-add-gpio-latch-driver.patch b/target/linux/ar71xx/patches-4.1/452-gpio-add-gpio-latch-driver.patch new file mode 100644 index 0000000..080a718 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/452-gpio-add-gpio-latch-driver.patch @@ -0,0 +1,22 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -996,4 +996,9 @@ config GPIO_NXP_74HC153 + Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This + provides a GPIO interface supporting input mode only. + ++config GPIO_LATCH ++ tristate "GPIO latch driver" ++ help ++ Say yes here to enable a GPIO latch driver. ++ + endif +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -42,6 +42,7 @@ obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz + obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o + obj-$(CONFIG_ARCH_KS8695) += gpio-ks8695.o + obj-$(CONFIG_GPIO_INTEL_MID) += gpio-intel-mid.o ++obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o + obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o + obj-$(CONFIG_GPIO_LP3943) += gpio-lp3943.o + obj-$(CONFIG_ARCH_LPC32XX) += gpio-lpc32xx.o diff --git a/target/linux/ar71xx/patches-4.1/460-spi-bitbang-export-spi_bitbang_bufs.patch b/target/linux/ar71xx/patches-4.1/460-spi-bitbang-export-spi_bitbang_bufs.patch new file mode 100644 index 0000000..4f0de01 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/460-spi-bitbang-export-spi_bitbang_bufs.patch @@ -0,0 +1,28 @@ +--- a/drivers/spi/spi-bitbang.c ++++ b/drivers/spi/spi-bitbang.c +@@ -230,13 +230,14 @@ void spi_bitbang_cleanup(struct spi_devi + } + EXPORT_SYMBOL_GPL(spi_bitbang_cleanup); + +-static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) ++int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) + { + struct spi_bitbang_cs *cs = spi->controller_state; + unsigned nsecs = cs->nsecs; + + return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t); + } ++EXPORT_SYMBOL_GPL(spi_bitbang_bufs); + + /*----------------------------------------------------------------------*/ + +--- a/include/linux/spi/spi_bitbang.h ++++ b/include/linux/spi/spi_bitbang.h +@@ -39,6 +39,7 @@ extern int spi_bitbang_setup(struct spi_ + extern void spi_bitbang_cleanup(struct spi_device *spi); + extern int spi_bitbang_setup_transfer(struct spi_device *spi, + struct spi_transfer *t); ++extern int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t); + + /* start or stop queue processing */ + extern int spi_bitbang_start(struct spi_bitbang *spi); diff --git a/target/linux/ar71xx/patches-4.1/461-spi-add-type-field-to-spi_transfer.patch b/target/linux/ar71xx/patches-4.1/461-spi-add-type-field-to-spi_transfer.patch new file mode 100644 index 0000000..ce1b69c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/461-spi-add-type-field-to-spi_transfer.patch @@ -0,0 +1,23 @@ +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -506,6 +506,12 @@ extern struct spi_master *spi_busnum_to_ + + /*---------------------------------------------------------------------------*/ + ++enum spi_transfer_type { ++ SPI_TRANSFER_GENERIC = 0, ++ SPI_TRANSFER_FLASH_READ_CMD, ++ SPI_TRANSFER_FLASH_READ_DATA, ++}; ++ + /* + * I/O INTERFACE between SPI controller and protocol drivers + * +@@ -626,6 +632,7 @@ struct spi_transfer { + u8 bits_per_word; + u16 delay_usecs; + u32 speed_hz; ++ enum spi_transfer_type type; + + struct list_head transfer_list; + }; diff --git a/target/linux/ar71xx/patches-4.1/462-mtd-m25p80-set-spi-transfer-type.patch b/target/linux/ar71xx/patches-4.1/462-mtd-m25p80-set-spi-transfer-type.patch new file mode 100644 index 0000000..b011c28 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/462-mtd-m25p80-set-spi-transfer-type.patch @@ -0,0 +1,15 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -139,10 +139,12 @@ static int m25p80_read(struct spi_nor *n + flash->command[0] = nor->read_opcode; + m25p_addr2cmd(nor, from, flash->command); + ++ t[0].type = SPI_TRANSFER_FLASH_READ_CMD; + t[0].tx_buf = flash->command; + t[0].len = m25p_cmdsz(nor) + dummy; + spi_message_add_tail(&t[0], &m); + ++ t[1].type = SPI_TRANSFER_FLASH_READ_DATA; + t[1].rx_buf = buf; + t[1].rx_nbits = m25p80_rx_nbits(nor); + t[1].len = len; diff --git a/target/linux/ar71xx/patches-4.1/463-spi-ath79-add-fast-flash-read.patch b/target/linux/ar71xx/patches-4.1/463-spi-ath79-add-fast-flash-read.patch new file mode 100644 index 0000000..0e0e28f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/463-spi-ath79-add-fast-flash-read.patch @@ -0,0 +1,185 @@ +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -35,6 +35,11 @@ + + #define ATH79_SPI_CS_LINE_MAX 2 + ++enum ath79_spi_state { ++ ATH79_SPI_STATE_WAIT_CMD = 0, ++ ATH79_SPI_STATE_WAIT_READ, ++}; ++ + struct ath79_spi { + struct spi_bitbang bitbang; + u32 ioc_base; +@@ -42,6 +47,11 @@ struct ath79_spi { + void __iomem *base; + struct clk *clk; + unsigned rrw_delay; ++ ++ enum ath79_spi_state state; ++ u32 clk_div; ++ unsigned long read_addr; ++ unsigned long ahb_rate; + }; + + static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) +@@ -109,9 +119,6 @@ static void ath79_spi_enable(struct ath7 + /* save CTRL register */ + sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); + sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); +- +- /* TODO: setup speed? */ +- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); + } + + static void ath79_spi_disable(struct ath79_spi *sp) +@@ -224,6 +231,110 @@ static u32 ath79_spi_txrx_mode0(struct s + return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); + } + ++static int ath79_spi_do_read_flash_data(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ ++ /* disable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); ++ ++ memcpy_fromio(t->rx_buf, sp->base + sp->read_addr, t->len); ++ ++ /* enable GPIO mode */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); ++ ++ /* restore IOC register */ ++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); ++ ++ return t->len; ++} ++ ++static int ath79_spi_do_read_flash_cmd(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ int len; ++ const u8 *p; ++ ++ sp->read_addr = 0; ++ ++ len = t->len - 1; ++ p = t->tx_buf; ++ ++ while (len--) { ++ p++; ++ sp->read_addr <<= 8; ++ sp->read_addr |= *p; ++ } ++ ++ return t->len; ++} ++ ++static bool ath79_spi_is_read_cmd(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ return t->type == SPI_TRANSFER_FLASH_READ_CMD; ++} ++ ++static bool ath79_spi_is_data_read(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ return t->type == SPI_TRANSFER_FLASH_READ_DATA; ++} ++ ++static int ath79_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ int ret; ++ ++ switch (sp->state) { ++ case ATH79_SPI_STATE_WAIT_CMD: ++ if (ath79_spi_is_read_cmd(spi, t)) { ++ ret = ath79_spi_do_read_flash_cmd(spi, t); ++ sp->state = ATH79_SPI_STATE_WAIT_READ; ++ } else { ++ ret = spi_bitbang_bufs(spi, t); ++ } ++ break; ++ ++ case ATH79_SPI_STATE_WAIT_READ: ++ if (ath79_spi_is_data_read(spi, t)) { ++ ret = ath79_spi_do_read_flash_data(spi, t); ++ } else { ++ dev_warn(&spi->dev, "flash data read expected\n"); ++ ret = -EIO; ++ } ++ sp->state = ATH79_SPI_STATE_WAIT_CMD; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ return ret; ++} ++ ++static int ath79_spi_setup_transfer(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ath79_spi *sp = ath79_spidev_to_sp(spi); ++ struct ath79_spi_controller_data *cdata; ++ int ret; ++ ++ ret = spi_bitbang_setup_transfer(spi, t); ++ if (ret) ++ return ret; ++ ++ cdata = spi->controller_data; ++ if (cdata->is_flash) ++ sp->bitbang.txrx_bufs = ath79_spi_txrx_bufs; ++ else ++ sp->bitbang.txrx_bufs = spi_bitbang_bufs; ++ ++ return ret; ++} ++ + static int ath79_spi_probe(struct platform_device *pdev) + { + struct spi_master *master; +@@ -246,6 +357,8 @@ static int ath79_spi_probe(struct platfo + sp = spi_master_get_devdata(master); + platform_set_drvdata(pdev, sp); + ++ sp->state = ATH79_SPI_STATE_WAIT_CMD; ++ + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); + master->setup = ath79_spi_setup; + master->cleanup = ath79_spi_cleanup; +@@ -255,7 +368,7 @@ static int ath79_spi_probe(struct platfo + sp->bitbang.master = master; + sp->bitbang.chipselect = ath79_spi_chipselect; + sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; +- sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; ++ sp->bitbang.setup_transfer = ath79_spi_setup_transfer; + sp->bitbang.flags = SPI_CS_HIGH; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); +@@ -280,7 +393,8 @@ static int ath79_spi_probe(struct platfo + if (ret) + goto err_put_master; + +- rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); ++ sp->ahb_rate = clk_get_rate(sp->clk); ++ rate = DIV_ROUND_UP(sp->ahb_rate, MHZ); + if (!rate) { + ret = -EINVAL; + goto err_clk_disable; +--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h ++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h +@@ -24,6 +24,7 @@ enum ath79_spi_cs_type { + struct ath79_spi_controller_data { + enum ath79_spi_cs_type cs_type; + unsigned cs_line; ++ bool is_flash; + }; + + #endif /* _ATH79_SPI_PLATFORM_H */ diff --git a/target/linux/ar71xx/patches-4.1/464-spi-ath79-fix-fast-flash-read.patch b/target/linux/ar71xx/patches-4.1/464-spi-ath79-fix-fast-flash-read.patch new file mode 100644 index 0000000..65eb875 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/464-spi-ath79-fix-fast-flash-read.patch @@ -0,0 +1,35 @@ +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -139,6 +139,9 @@ static int m25p80_read(struct spi_nor *n + flash->command[0] = nor->read_opcode; + m25p_addr2cmd(nor, from, flash->command); + ++ if (dummy == 1) ++ t[0].dummy = true; ++ + t[0].type = SPI_TRANSFER_FLASH_READ_CMD; + t[0].tx_buf = flash->command; + t[0].len = m25p_cmdsz(nor) + dummy; +--- a/drivers/spi/spi-ath79.c ++++ b/drivers/spi/spi-ath79.c +@@ -260,6 +260,10 @@ static int ath79_spi_do_read_flash_cmd(s + sp->read_addr = 0; + + len = t->len - 1; ++ ++ if (t->dummy) ++ len -= 1; ++ + p = t->tx_buf; + + while (len--) { +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -633,6 +633,7 @@ struct spi_transfer { + u16 delay_usecs; + u32 speed_hz; + enum spi_transfer_type type; ++ bool dummy; + + struct list_head transfer_list; + }; diff --git a/target/linux/ar71xx/patches-4.1/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ar71xx/patches-4.1/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch new file mode 100644 index 0000000..520c652 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch @@ -0,0 +1,111 @@ +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath79/mangle-port.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2012 Gabor Juhos ++ * ++ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H ++#define __ASM_MACH_ATH79_MANGLE_PORT_H ++ ++#ifdef CONFIG_PCI ++extern unsigned long (ath79_pci_swizzle_b)(unsigned long port); ++extern unsigned long (ath79_pci_swizzle_w)(unsigned long port); ++#else ++#define ath79_pci_swizzle_b(port) (port) ++#define ath79_pci_swizzle_w(port) (port) ++#endif ++ ++#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port) ++#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port) ++#define __swizzle_addr_l(port) (port) ++#define __swizzle_addr_q(port) (port) ++ ++# define ioswabb(a, x) (x) ++# define __mem_ioswabb(a, x) (x) ++# define ioswabw(a, x) (x) ++# define __mem_ioswabw(a, x) cpu_to_le16(x) ++# define ioswabl(a, x) (x) ++# define __mem_ioswabl(a, x) cpu_to_le32(x) ++# define ioswabq(a, x) (x) ++# define __mem_ioswabq(a, x) cpu_to_le64(x) ++ ++#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -13,6 +13,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -25,6 +26,9 @@ static int (*ath79_pci_plat_dev_init)(st + static const struct ath79_pci_irq *ath79_pci_irq_map __initdata; + static unsigned ath79_pci_nr_irqs __initdata; + ++static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port); ++static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port); ++ + static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = { + { + .slot = 17, +@@ -212,12 +216,50 @@ ath79_register_pci_ar724x(int id, + return pdev; + } + ++static inline bool ar71xx_is_pci_addr(unsigned long port) ++{ ++ unsigned long phys = CPHYSADDR(port); ++ ++ return (phys >= AR71XX_PCI_MEM_BASE && ++ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE); ++} ++ ++static unsigned long ar71xx_pci_swizzle_b(unsigned long port) ++{ ++ return ar71xx_is_pci_addr(port) ? port ^ 3 : port; ++} ++ ++static unsigned long ar71xx_pci_swizzle_w(unsigned long port) ++{ ++ return ar71xx_is_pci_addr(port) ? port ^ 2 : port; ++} ++ ++unsigned long ath79_pci_swizzle_b(unsigned long port) ++{ ++ if (__ath79_pci_swizzle_b) ++ return __ath79_pci_swizzle_b(port); ++ ++ return port; ++} ++EXPORT_SYMBOL(ath79_pci_swizzle_b); ++ ++unsigned long ath79_pci_swizzle_w(unsigned long port) ++{ ++ if (__ath79_pci_swizzle_w) ++ return __ath79_pci_swizzle_w(port); ++ ++ return port; ++} ++EXPORT_SYMBOL(ath79_pci_swizzle_w); ++ + int __init ath79_register_pci(void) + { + struct platform_device *pdev = NULL; + + if (soc_is_ar71xx()) { + pdev = ath79_register_pci_ar71xx(); ++ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b; ++ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w; + } else if (soc_is_ar724x()) { + pdev = ath79_register_pci_ar724x(-1, + AR724X_PCI_CFG_BASE, diff --git a/target/linux/ar71xx/patches-4.1/490-usb-ehci-add-quirks-for-qca-socs.patch b/target/linux/ar71xx/patches-4.1/490-usb-ehci-add-quirks-for-qca-socs.patch new file mode 100644 index 0000000..162510b --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/490-usb-ehci-add-quirks-for-qca-socs.patch @@ -0,0 +1,103 @@ +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -252,6 +252,37 @@ static int ehci_reset (struct ehci_hcd * + command |= CMD_RESET; + dbg_cmd (ehci, "reset", command); + ehci_writel(ehci, command, &ehci->regs->command); ++ ++ if (ehci->qca_force_host_mode) { ++ u32 usbmode; ++ ++ udelay(1000); ++ ++ usbmode = ehci_readl(ehci, &ehci->regs->usbmode); ++ usbmode |= USBMODE_CM_HC | (1 << 4); ++ ehci_writel(ehci, usbmode, &ehci->regs->usbmode); ++ ++ ehci_dbg(ehci, "forced host mode, usbmode: %08x\n", ++ ehci_readl(ehci, &ehci->regs->usbmode)); ++ } ++ ++ if (ehci->qca_force_16bit_ptw) { ++ u32 port_status; ++ ++ udelay(1000); ++ ++ /* enable 16-bit UTMI interface */ ++ port_status = ehci_readl(ehci, &ehci->regs->port_status[0]); ++ port_status |= BIT(28); ++ ehci_writel(ehci, port_status, &ehci->regs->port_status[0]); ++ ++ ehci_dbg(ehci, "16-bit UTMI interface enabled, status: %08x\n", ++ ehci_readl(ehci, &ehci->regs->port_status[0])); ++ } ++ ++ if (ehci->reset_notifier) ++ ehci->reset_notifier(ehci_to_hcd(ehci)); ++ + ehci->rh_state = EHCI_RH_HALTED; + ehci->next_statechange = jiffies; + retval = ehci_handshake(ehci, &ehci->regs->command, +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -227,6 +227,10 @@ struct ehci_hcd { /* one per controlle + unsigned need_oc_pp_cycle:1; /* MPC834X port power */ + unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ + unsigned ignore_oc:1; ++ unsigned qca_force_host_mode:1; ++ unsigned qca_force_16bit_ptw:1; /* force 16 bit UTMI */ ++ ++ void (*reset_notifier)(struct usb_hcd *hcd); + + /* required for usb32 quirk */ + #define OHCI_CTRL_HCFS (3 << 6) +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -50,6 +50,8 @@ struct usb_ehci_pdata { + unsigned reset_on_resume:1; + unsigned dma_mask_64:1; + unsigned ignore_oc:1; ++ unsigned qca_force_host_mode:1; ++ unsigned qca_force_16bit_ptw:1; + + /* Turn on all power and clocks */ + int (*power_on)(struct platform_device *pdev); +@@ -59,6 +61,7 @@ struct usb_ehci_pdata { + * turn off everything else */ + void (*power_suspend)(struct platform_device *pdev); + int (*pre_setup)(struct usb_hcd *hcd); ++ void (*reset_notifier)(struct platform_device *pdev); + }; + + #endif /* __USB_CORE_EHCI_PDRIVER_H */ +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -49,6 +49,14 @@ struct ehci_platform_priv { + + static const char hcd_name[] = "ehci-platform"; + ++static void ehci_platform_reset_notifier(struct usb_hcd *hcd) ++{ ++ struct platform_device *pdev = to_platform_device(hcd->self.controller); ++ struct usb_ehci_pdata *pdata = pdev->dev.platform_data; ++ ++ pdata->reset_notifier(pdev); ++} ++ + static int ehci_platform_reset(struct usb_hcd *hcd) + { + struct platform_device *pdev = to_platform_device(hcd->self.controller); +@@ -266,6 +274,13 @@ static int ehci_platform_probe(struct pl + ehci->big_endian_mmio = 1; + if (pdata->ignore_oc) + ehci->ignore_oc = 1; ++ if (pdata->qca_force_host_mode) ++ ehci->qca_force_host_mode = 1; ++ if (pdata->qca_force_16bit_ptw) ++ ehci->qca_force_16bit_ptw = 1; ++ ++ if (pdata->reset_notifier) ++ ehci->reset_notifier = ehci_platform_reset_notifier; + + #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO + if (ehci->big_endian_mmio) { diff --git a/target/linux/ar71xx/patches-4.1/500-MIPS-fw-myloader.patch b/target/linux/ar71xx/patches-4.1/500-MIPS-fw-myloader.patch new file mode 100644 index 0000000..1aa6097 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/500-MIPS-fw-myloader.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -225,6 +225,7 @@ endif + # + libs-$(CONFIG_FW_ARC) += arch/mips/fw/arc/ + libs-$(CONFIG_FW_CFE) += arch/mips/fw/cfe/ ++libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ + libs-$(CONFIG_FW_SNIPROM) += arch/mips/fw/sni/ + libs-y += arch/mips/fw/lib/ + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1067,6 +1067,9 @@ config MIPS_MSC + config MIPS_NILE4 + bool + ++config MYLOADER ++ bool ++ + config SYNC_R4K + bool + diff --git a/target/linux/ar71xx/patches-4.1/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch b/target/linux/ar71xx/patches-4.1/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch new file mode 100644 index 0000000..fdf353c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/501-MIPS-ath79-add-mac-argument-to-ath79_register_wmac.patch @@ -0,0 +1,81 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -22,6 +23,7 @@ + #include + #include "dev-wmac.h" + ++static u8 ath79_wmac_mac[ETH_ALEN]; + static struct ath9k_platform_data ath79_wmac_data; + + static struct resource ath79_wmac_resources[] = { +@@ -162,7 +164,7 @@ static void qca955x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + +-void __init ath79_register_wmac(u8 *cal_data) ++void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) + ar913x_wmac_setup(); +@@ -179,5 +181,10 @@ void __init ath79_register_wmac(u8 *cal_ + memcpy(ath79_wmac_data.eeprom_data, cal_data, + sizeof(ath79_wmac_data.eeprom_data)); + ++ if (mac_addr) { ++ memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac)); ++ ath79_wmac_data.macaddr = ath79_wmac_mac; ++ } ++ + platform_device_register(&ath79_wmac_device); + } +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -12,6 +12,6 @@ + #ifndef _ATH79_DEV_WMAC_H + #define _ATH79_DEV_WMAC_H + +-void ath79_register_wmac(u8 *cal_data); ++void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); + + #endif /* _ATH79_DEV_WMAC_H */ +--- a/arch/mips/ath79/mach-ap81.c ++++ b/arch/mips/ath79/mach-ap81.c +@@ -92,7 +92,7 @@ static void __init ap81_setup(void) + ap81_gpio_keys); + ath79_register_spi(&ap81_spi_data, ap81_spi_info, + ARRAY_SIZE(ap81_spi_info)); +- ath79_register_wmac(cal_data); ++ ath79_register_wmac(cal_data, NULL); + ath79_register_usb(); + } + +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -128,7 +128,7 @@ static void __init db120_setup(void) + ath79_register_spi(&db120_spi_data, db120_spi_info, + ARRAY_SIZE(db120_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET); ++ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); + db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); + } + +--- a/arch/mips/ath79/mach-ap121.c ++++ b/arch/mips/ath79/mach-ap121.c +@@ -85,7 +85,7 @@ static void __init ap121_setup(void) + ath79_register_spi(&ap121_spi_data, ap121_spi_info, + ARRAY_SIZE(ap121_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(cal_data); ++ ath79_register_wmac(cal_data, NULL); + } + + MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", diff --git a/target/linux/ar71xx/patches-4.1/502-MIPS-ath79-export-ath79_gpio_base.patch b/target/linux/ar71xx/patches-4.1/502-MIPS-ath79-export-ath79_gpio_base.patch new file mode 100644 index 0000000..73eb8e1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/502-MIPS-ath79-export-ath79_gpio_base.patch @@ -0,0 +1,23 @@ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -25,7 +25,9 @@ + #include + #include "common.h" + +-static void __iomem *ath79_gpio_base; ++void __iomem *ath79_gpio_base; ++EXPORT_SYMBOL_GPL(ath79_gpio_base); ++ + static unsigned long ath79_gpio_count; + static DEFINE_SPINLOCK(ath79_gpio_lock); + +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -116,6 +116,7 @@ static inline int soc_is_qca955x(void) + } + + extern void __iomem *ath79_ddr_base; ++extern void __iomem *ath79_gpio_base; + extern void __iomem *ath79_pll_base; + extern void __iomem *ath79_reset_base; + diff --git a/target/linux/ar71xx/patches-4.1/503-MIPS-ath79-add-flash-acquire-release.patch b/target/linux/ar71xx/patches-4.1/503-MIPS-ath79-add-flash-acquire-release.patch new file mode 100644 index 0000000..108f659 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/503-MIPS-ath79-add-flash-acquire-release.patch @@ -0,0 +1,37 @@ +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -22,6 +22,7 @@ + #include "common.h" + + static DEFINE_SPINLOCK(ath79_device_reset_lock); ++static DEFINE_MUTEX(ath79_flash_mutex); + + u32 ath79_cpu_freq; + EXPORT_SYMBOL_GPL(ath79_cpu_freq); +@@ -111,3 +112,16 @@ void ath79_device_reset_clear(u32 mask) + spin_unlock_irqrestore(&ath79_device_reset_lock, flags); + } + EXPORT_SYMBOL_GPL(ath79_device_reset_clear); ++ ++void ath79_flash_acquire(void) ++{ ++ mutex_lock(&ath79_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ath79_flash_acquire); ++ ++void ath79_flash_release(void) ++{ ++ mutex_unlock(&ath79_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ath79_flash_release); ++ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -144,4 +144,7 @@ static inline u32 ath79_reset_rr(unsigne + void ath79_device_reset_set(u32 mask); + void ath79_device_reset_clear(u32 mask); + ++void ath79_flash_acquire(void); ++void ath79_flash_release(void); ++ + #endif /* __ASM_MACH_ATH79_H */ diff --git a/target/linux/ar71xx/patches-4.1/504-MIPS-ath79-add-ath79_device_reset_get.patch b/target/linux/ar71xx/patches-4.1/504-MIPS-ath79-add-ath79_device_reset_get.patch new file mode 100644 index 0000000..8748aa3 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/504-MIPS-ath79-add-ath79_device_reset_get.patch @@ -0,0 +1,45 @@ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -143,6 +143,7 @@ static inline u32 ath79_reset_rr(unsigne + + void ath79_device_reset_set(u32 mask); + void ath79_device_reset_clear(u32 mask); ++u32 ath79_device_reset_get(u32 mask); + + void ath79_flash_acquire(void); + void ath79_flash_release(void); +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -113,6 +113,32 @@ void ath79_device_reset_clear(u32 mask) + } + EXPORT_SYMBOL_GPL(ath79_device_reset_clear); + ++u32 ath79_device_reset_get(u32 mask) ++{ ++ unsigned long flags; ++ u32 reg; ++ u32 ret; ++ ++ if (soc_is_ar71xx()) ++ reg = AR71XX_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar724x()) ++ reg = AR724X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar913x()) ++ reg = AR913X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar933x()) ++ reg = AR933X_RESET_REG_RESET_MODULE; ++ else if (soc_is_ar934x()) ++ reg = AR934X_RESET_REG_RESET_MODULE; ++ else ++ BUG(); ++ ++ spin_lock_irqsave(&ath79_device_reset_lock, flags); ++ ret = ath79_reset_rr(reg); ++ spin_unlock_irqrestore(&ath79_device_reset_lock, flags); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(ath79_device_reset_get); ++ + void ath79_flash_acquire(void) + { + mutex_lock(&ath79_flash_mutex); diff --git a/target/linux/ar71xx/patches-4.1/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-4.1/505-MIPS-ath79-add-ath79_gpio_function_select.patch new file mode 100644 index 0000000..4c4c891 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/505-MIPS-ath79-add-ath79_gpio_function_select.patch @@ -0,0 +1,47 @@ +--- a/arch/mips/ath79/common.h ++++ b/arch/mips/ath79/common.h +@@ -27,6 +27,7 @@ void ath79_ddr_wb_flush(unsigned int reg + void ath79_gpio_function_enable(u32 mask); + void ath79_gpio_function_disable(u32 mask); + void ath79_gpio_function_setup(u32 set, u32 clear); ++void ath79_gpio_output_select(unsigned gpio, u8 val); + void ath79_gpio_init(void); + + #endif /* __ATH79_COMMON_H */ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -180,6 +180,34 @@ void ath79_gpio_function_disable(u32 mas + ath79_gpio_function_setup(0, mask); + } + ++void __init ath79_gpio_output_select(unsigned gpio, u8 val) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ unsigned int reg; ++ u32 t, s; ++ ++ BUG_ON(!soc_is_ar934x()); ++ ++ if (gpio >= AR934X_GPIO_COUNT) ++ return; ++ ++ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); ++ s = 8 * (gpio % 4); ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ t = __raw_readl(base + reg); ++ t &= ~(0xff << s); ++ t |= val << s; ++ __raw_writel(t, base + reg); ++ ++ /* flush write */ ++ (void) __raw_readl(base + reg); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++} ++ + void __init ath79_gpio_init(void) + { + int err; diff --git a/target/linux/ar71xx/patches-4.1/506-MIPS-ath79-prom-parse-redboot-args.patch b/target/linux/ar71xx/patches-4.1/506-MIPS-ath79-prom-parse-redboot-args.patch new file mode 100644 index 0000000..46beeff --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/506-MIPS-ath79-prom-parse-redboot-args.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -22,10 +22,39 @@ + + #include "common.h" + ++static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata; ++ ++static void __init ath79_prom_append_cmdline(const char *name, ++ const char *value) ++{ ++ snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf), ++ " %s=%s", name, value); ++ strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); ++} ++ + void __init prom_init(void) + { ++ const char *env; ++ + fw_init_cmdline(); + ++ env = fw_getenv("ethaddr"); ++ if (env) ++ ath79_prom_append_cmdline("ethaddr", env); ++ ++ env = fw_getenv("board"); ++ if (env) { ++ /* Workaround for buggy bootloaders */ ++ if (strcmp(env, "RouterStation") == 0 || ++ strcmp(env, "Ubiquiti AR71xx-based board") == 0) ++ env = "UBNT-RS"; ++ ++ if (strcmp(env, "RouterStation PRO") == 0) ++ env = "UBNT-RSPRO"; ++ ++ ath79_prom_append_cmdline("board", env); ++ } ++ + #ifdef CONFIG_BLK_DEV_INITRD + /* Read the initrd address from the firmware environment */ + initrd_start = fw_getenvl("initrd_start"); diff --git a/target/linux/ar71xx/patches-4.1/507-MIPS-ath79-prom-add-myloader-support.patch b/target/linux/ar71xx/patches-4.1/507-MIPS-ath79-prom-add-myloader-support.patch new file mode 100644 index 0000000..17a9733 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/507-MIPS-ath79-prom-add-myloader-support.patch @@ -0,0 +1,55 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include "common.h" + +@@ -32,10 +33,44 @@ static void __init ath79_prom_append_cmd + strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); + } + ++static int __init ath79_prom_init_myloader(void) ++{ ++ struct myloader_info *mylo; ++ char mac_buf[32]; ++ unsigned char *mac; ++ ++ mylo = myloader_get_info(); ++ if (!mylo) ++ return 0; ++ ++ switch (mylo->did) { ++ case DEVID_COMPEX_WP543: ++ ath79_prom_append_cmdline("board", "WP543"); ++ break; ++ case DEVID_COMPEX_WPE72: ++ ath79_prom_append_cmdline("board", "WPE72"); ++ break; ++ default: ++ pr_warn("prom: unknown device id: %x\n", mylo->did); ++ return 0; ++ } ++ ++ mac = mylo->macs[0]; ++ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x", ++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); ++ ++ ath79_prom_append_cmdline("ethaddr", mac_buf); ++ ++ return 1; ++} ++ + void __init prom_init(void) + { + const char *env; + ++ if (ath79_prom_init_myloader()) ++ return; ++ + fw_init_cmdline(); + + env = fw_getenv("ethaddr"); diff --git a/target/linux/ar71xx/patches-4.1/508-MIPS-ath79-prom-image-command-line-hack.patch b/target/linux/ar71xx/patches-4.1/508-MIPS-ath79-prom-image-command-line-hack.patch new file mode 100644 index 0000000..cfa5e72 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/508-MIPS-ath79-prom-image-command-line-hack.patch @@ -0,0 +1,73 @@ +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -33,6 +33,41 @@ static void __init ath79_prom_append_cmd + strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline)); + } + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++extern char __image_cmdline[]; ++ ++static int __init ath79_use_image_cmdline(void) ++{ ++ char *p = __image_cmdline; ++ int replace = 0; ++ ++ if (*p == '-') { ++ replace = 1; ++ p++; ++ } ++ ++ if (*p == '\0') ++ return 0; ++ ++ if (replace) { ++ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } else { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } ++ ++ /* Validate and setup environment pointer */ ++ if (fw_arg2 < CKSEG0) ++ _fw_envp = NULL; ++ else ++ _fw_envp = (int *)fw_arg2; ++ ++ return 1; ++} ++#else ++static inline int ath79_use_image_cmdline(void) { return 0; } ++#endif ++ + static int __init ath79_prom_init_myloader(void) + { + struct myloader_info *mylo; +@@ -61,6 +96,8 @@ static int __init ath79_prom_init_myload + + ath79_prom_append_cmdline("ethaddr", mac_buf); + ++ ath79_use_image_cmdline(); ++ + return 1; + } + +@@ -71,7 +108,8 @@ void __init prom_init(void) + if (ath79_prom_init_myloader()) + return; + +- fw_init_cmdline(); ++ if (!ath79_use_image_cmdline()) ++ fw_init_cmdline(); + + env = fw_getenv("ethaddr"); + if (env) +--- a/arch/mips/fw/lib/cmdline.c ++++ b/arch/mips/fw/lib/cmdline.c +@@ -35,6 +35,7 @@ void __init fw_init_cmdline(void) + else + _fw_envp = (int *)fw_arg2; + ++ arcs_cmdline[0] = '\0'; + for (i = 1; i < fw_argc; i++) { + strlcat(arcs_cmdline, fw_argv(i), COMMAND_LINE_SIZE); + if (i < (fw_argc - 1)) diff --git a/target/linux/ar71xx/patches-4.1/509-MIPS-ath79-process-board-kernel-option.patch b/target/linux/ar71xx/patches-4.1/509-MIPS-ath79-process-board-kernel-option.patch new file mode 100644 index 0000000..2366c40 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/509-MIPS-ath79-process-board-kernel-option.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -236,6 +236,8 @@ void __init plat_time_init(void) + mips_hpt_frequency = cpu_clk_rate / 2; + } + ++__setup("board=", mips_machtype_setup); ++ + static int __init ath79_setup(void) + { + ath79_gpio_init(); diff --git a/target/linux/ar71xx/patches-4.1/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch b/target/linux/ar71xx/patches-4.1/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch new file mode 100644 index 0000000..2d2235e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/510-MIPS-ath79-init-gpio-pin-of-wmac-device.patch @@ -0,0 +1,14 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -24,7 +24,10 @@ + #include "dev-wmac.h" + + static u8 ath79_wmac_mac[ETH_ALEN]; +-static struct ath9k_platform_data ath79_wmac_data; ++ ++static struct ath9k_platform_data ath79_wmac_data = { ++ .led_pin = -1, ++}; + + static struct resource ath79_wmac_resources[] = { + { diff --git a/target/linux/ar71xx/patches-4.1/520-MIPS-ath79-enable-UART-function.patch b/target/linux/ar71xx/patches-4.1/520-MIPS-ath79-enable-UART-function.patch new file mode 100644 index 0000000..019e558 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/520-MIPS-ath79-enable-UART-function.patch @@ -0,0 +1,18 @@ +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -80,6 +80,15 @@ void __init ath79_register_uart(void) + + uart_clk_rate = ath79_get_sys_clk_rate("uart"); + ++ if (soc_is_ar71xx()) ++ ath79_gpio_function_enable(AR71XX_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar724x()) ++ ath79_gpio_function_enable(AR724X_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar913x()) ++ ath79_gpio_function_enable(AR913X_GPIO_FUNC_UART_EN); ++ else if (soc_is_ar933x()) ++ ath79_gpio_function_enable(AR933X_GPIO_FUNC_UART_EN); ++ + if (soc_is_ar71xx() || + soc_is_ar724x() || + soc_is_ar913x() || diff --git a/target/linux/ar71xx/patches-4.1/521-MIPS-ath79-enable-UART-for-early_serial.patch b/target/linux/ar71xx/patches-4.1/521-MIPS-ath79-enable-UART-for-early_serial.patch new file mode 100644 index 0000000..3d6ddfe --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/521-MIPS-ath79-enable-UART-for-early_serial.patch @@ -0,0 +1,61 @@ +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -56,6 +56,46 @@ static void prom_putchar_dummy(unsigned + /* nothing to do */ + } + ++static void prom_enable_uart(u32 id) ++{ ++ void __iomem *gpio_base; ++ u32 uart_en; ++ u32 t; ++ ++ switch (id) { ++ case REV_ID_MAJOR_AR71XX: ++ uart_en = AR71XX_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR7240: ++ case REV_ID_MAJOR_AR7241: ++ case REV_ID_MAJOR_AR7242: ++ uart_en = AR724X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR913X: ++ uart_en = AR913X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR9330: ++ case REV_ID_MAJOR_AR9331: ++ uart_en = AR933X_GPIO_FUNC_UART_EN; ++ break; ++ ++ case REV_ID_MAJOR_AR9341: ++ case REV_ID_MAJOR_AR9342: ++ case REV_ID_MAJOR_AR9344: ++ /* TODO */ ++ default: ++ return; ++ } ++ ++ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE)); ++ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC); ++ t |= uart_en; ++ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC); ++} ++ + static void prom_putchar_init(void) + { + void __iomem *base; +@@ -86,8 +126,10 @@ static void prom_putchar_init(void) + + default: + _prom_putchar = prom_putchar_dummy; +- break; ++ return; + } ++ ++ prom_enable_uart(id); + } + + void prom_putchar(unsigned char ch) diff --git a/target/linux/ar71xx/patches-4.1/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch b/target/linux/ar71xx/patches-4.1/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch new file mode 100644 index 0000000..a29c7be --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/522-MIPS-ath79-add-ath79_wmac_register_simple-helper.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -191,3 +191,9 @@ void __init ath79_register_wmac(u8 *cal_ + + platform_device_register(&ath79_wmac_device); + } ++ ++void __init ath79_register_wmac_simple(void) ++{ ++ ath79_register_wmac(NULL, NULL); ++ ath79_wmac_data.eeprom_name = "soc_wmac.eeprom"; ++} +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -13,5 +13,6 @@ + #define _ATH79_DEV_WMAC_H + + void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); ++void ath79_register_wmac_simple(void); + + #endif /* _ATH79_DEV_WMAC_H */ diff --git a/target/linux/ar71xx/patches-4.1/523-MIPS-ath79-OTP-support.patch b/target/linux/ar71xx/patches-4.1/523-MIPS-ath79-OTP-support.patch new file mode 100644 index 0000000..e030d7c --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/523-MIPS-ath79-OTP-support.patch @@ -0,0 +1,166 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -167,6 +167,137 @@ static void qca955x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + ++static bool __init ++ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data) ++{ ++ int timeout = 1000; ++ u32 val; ++ ++ __raw_readl(base + AR9300_OTP_BASE + (4 * addr)); ++ while (timeout--) { ++ val = __raw_readl(base + AR9300_OTP_STATUS); ++ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID) ++ break; ++ ++ udelay(10); ++ } ++ ++ if (!timeout) ++ return false; ++ ++ *data = __raw_readl(base + AR9300_OTP_READ_DATA); ++ return true; ++} ++ ++static bool __init ++ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len) ++{ ++ u32 data; ++ int i; ++ ++ for (i = 0; i < len; i++) { ++ int offset = 8 * ((addr - i) % 4); ++ ++ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data)) ++ return false; ++ ++ dest[i] = (data >> offset) & 0xff; ++ } ++ ++ return true; ++} ++ ++static bool __init ++ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest, ++ int dest_start, int dest_len) ++{ ++ int dest_bytes = 0; ++ int offset = 0; ++ int end = addr - len; ++ u8 hdr[2]; ++ ++ while (addr > end) { ++ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2)) ++ return false; ++ ++ addr -= 2; ++ offset += hdr[0]; ++ ++ if (offset <= dest_start + dest_len && ++ offset + len >= dest_start) { ++ int data_offset = 0; ++ int dest_offset = 0; ++ int copy_len; ++ ++ if (offset < dest_start) ++ data_offset = dest_start - offset; ++ else ++ dest_offset = offset - dest_start; ++ ++ copy_len = len - data_offset; ++ if (copy_len > dest_len - dest_offset) ++ copy_len = dest_len - dest_offset; ++ ++ ar93xx_wmac_otp_read(base, addr - data_offset, ++ dest + dest_offset, ++ copy_len); ++ ++ dest_bytes += copy_len; ++ } ++ addr -= hdr[1]; ++ } ++ return !!dest_bytes; ++} ++ ++bool __init ar93xx_wmac_read_mac_address(u8 *dest) ++{ ++ void __iomem *base; ++ bool ret = false; ++ int addr = 0x1ff; ++ unsigned int len; ++ u32 hdr_u32; ++ u8 *hdr = (u8 *) &hdr_u32; ++ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 }; ++ int mac_start = 2, mac_end = 8; ++ ++ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x()); ++ base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE); ++ while (addr > sizeof(hdr)) { ++ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr))) ++ break; ++ ++ if (hdr_u32 == 0 || hdr_u32 == ~0) ++ break; ++ ++ len = (hdr[1] << 4) | (hdr[2] >> 4); ++ addr -= 4; ++ ++ switch (hdr[0] >> 5) { ++ case 0: ++ if (len < mac_end) ++ break; ++ ++ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6); ++ ret = true; ++ break; ++ case 3: ++ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac, ++ mac_start, 6); ++ break; ++ default: ++ break; ++ } ++ ++ addr -= len + 2; ++ } ++ ++ iounmap(base); ++ if (ret) ++ memcpy(dest, mac, 6); ++ ++ return ret; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -14,5 +14,6 @@ + + void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); + void ath79_register_wmac_simple(void); ++bool ar93xx_wmac_read_mac_address(u8 *dest); + + #endif /* _ATH79_DEV_WMAC_H */ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -112,6 +112,14 @@ + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x1000 + ++#define AR9300_OTP_BASE 0x14000 ++#define AR9300_OTP_STATUS 0x15f18 ++#define AR9300_OTP_STATUS_TYPE 0x7 ++#define AR9300_OTP_STATUS_VALID 0x4 ++#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 ++#define AR9300_OTP_STATUS_SM_BUSY 0x1 ++#define AR9300_OTP_READ_DATA 0x15f1c ++ + /* + * DDR_CTRL block + */ diff --git a/target/linux/ar71xx/patches-4.1/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch b/target/linux/ar71xx/patches-4.1/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch new file mode 100644 index 0000000..31f885f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -298,6 +298,16 @@ bool __init ar93xx_wmac_read_mac_address + return ret; + } + ++void __init ath79_wmac_disable_2ghz(void) ++{ ++ ath79_wmac_data.disable_2ghz = true; ++} ++ ++void __init ath79_wmac_disable_5ghz(void) ++{ ++ ath79_wmac_data.disable_5ghz = true; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -14,6 +14,9 @@ + + void ath79_register_wmac(u8 *cal_data, u8 *mac_addr); + void ath79_register_wmac_simple(void); ++void ath79_wmac_disable_2ghz(void); ++void ath79_wmac_disable_5ghz(void); ++ + bool ar93xx_wmac_read_mac_address(u8 *dest); + + #endif /* _ATH79_DEV_WMAC_H */ diff --git a/target/linux/ar71xx/patches-4.1/525-MIPS-ath79-enable-qca-usb-quirks.patch b/target/linux/ar71xx/patches-4.1/525-MIPS-ath79-enable-qca-usb-quirks.patch new file mode 100644 index 0000000..0e33674 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/525-MIPS-ath79-enable-qca-usb-quirks.patch @@ -0,0 +1,101 @@ +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -37,6 +37,8 @@ static struct usb_ehci_pdata ath79_ehci_ + static struct usb_ehci_pdata ath79_ehci_pdata_v2 = { + .caps_offset = 0x100, + .has_tt = 1, ++ .qca_force_host_mode = 1, ++ .qca_force_16bit_ptw = 1, + }; + + static void __init ath79_usb_register(const char *name, int id, +@@ -159,6 +161,9 @@ static void __init ar913x_usb_setup(void + ath79_device_reset_clear(AR913X_RESET_USB_PHY); + mdelay(10); + ++ ath79_ehci_pdata_v2.qca_force_host_mode = 0; ++ ath79_ehci_pdata_v2.qca_force_16bit_ptw = 0; ++ + ath79_usb_register("ehci-platform", -1, + AR913X_EHCI_BASE, AR913X_EHCI_SIZE, + ATH79_CPU_IRQ(3), +@@ -182,14 +187,34 @@ static void __init ar933x_usb_setup(void + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + +-static void __init ar934x_usb_setup(void) ++static void enable_tx_tx_idp_violation_fix(unsigned base) + { +- u32 bootstrap; ++ void __iomem *phy_reg; ++ u32 t; ++ ++ phy_reg = ioremap(base, 4); ++ if (!phy_reg) ++ return; ++ ++ t = ioread32(phy_reg); ++ t &= ~0xff; ++ t |= 0x58; ++ iowrite32(t, phy_reg); ++ ++ iounmap(phy_reg); ++} + +- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); +- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE) ++static void ar934x_usb_reset_notifier(struct platform_device *pdev) ++{ ++ if (pdev->id != -1) + return; + ++ enable_tx_tx_idp_violation_fix(0x18116c94); ++ dev_info(&pdev->dev, "TX-TX IDP fix enabled\n"); ++} ++ ++static void __init ar934x_usb_setup(void) ++{ + ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE); + udelay(1000); + +@@ -202,14 +227,40 @@ static void __init ar934x_usb_setup(void + ath79_device_reset_clear(AR934X_RESET_USB_HOST); + udelay(1000); + ++ if (ath79_soc_rev >= 3) ++ ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier; ++ + ath79_usb_register("ehci-platform", -1, + AR934X_EHCI_BASE, AR934X_EHCI_SIZE, + ATH79_CPU_IRQ(3), + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + ++static void qca955x_usb_reset_notifier(struct platform_device *pdev) ++{ ++ u32 base; ++ ++ switch (pdev->id) { ++ case 0: ++ base = 0x18116c94; ++ break; ++ ++ case 1: ++ base = 0x18116e54; ++ break; ++ ++ default: ++ return; ++ } ++ ++ enable_tx_tx_idp_violation_fix(base); ++ dev_info(&pdev->dev, "TX-TX IDP fix enabled\n"); ++} ++ + static void __init qca955x_usb_setup(void) + { ++ ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier; ++ + ath79_usb_register("ehci-platform", 0, + QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE, + ATH79_IP3_IRQ(0), diff --git a/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch new file mode 100644 index 0000000..8bf7658 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch @@ -0,0 +1,363 @@ +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -20,6 +20,10 @@ + #include + + #define AR71XX_APB_BASE 0x18000000 ++#define AR71XX_GE0_BASE 0x19000000 ++#define AR71XX_GE0_SIZE 0x10000 ++#define AR71XX_GE1_BASE 0x1a000000 ++#define AR71XX_GE1_SIZE 0x10000 + #define AR71XX_EHCI_BASE 0x1b000000 + #define AR71XX_EHCI_SIZE 0x1000 + #define AR71XX_OHCI_BASE 0x1c000000 +@@ -39,6 +43,8 @@ + #define AR71XX_PLL_SIZE 0x100 + #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) + #define AR71XX_RESET_SIZE 0x100 ++#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR71XX_MII_SIZE 0x100 + + #define AR71XX_PCI_MEM_BASE 0x10000000 + #define AR71XX_PCI_MEM_SIZE 0x07000000 +@@ -81,15 +87,21 @@ + + #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) + #define AR933X_UART_SIZE 0x14 ++#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR933X_GMAC_SIZE 0x04 + #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define AR933X_WMAC_SIZE 0x20000 + #define AR933X_EHCI_BASE 0x1b000000 + #define AR933X_EHCI_SIZE 0x1000 + ++#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR934X_GMAC_SIZE 0x14 + #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define AR934X_WMAC_SIZE 0x20000 + #define AR934X_EHCI_BASE 0x1b000000 + #define AR934X_EHCI_SIZE 0x200 ++#define AR934X_NFC_BASE 0x1b000200 ++#define AR934X_NFC_SIZE 0xb8 + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + +@@ -106,11 +118,15 @@ + #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) + #define QCA955X_PCI_CTRL_SIZE 0x100 + ++#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA955X_GMAC_SIZE 0x40 + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 + #define QCA955X_EHCI0_BASE 0x1b000000 + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x1000 ++#define QCA955X_NFC_BASE 0x1b800200 ++#define QCA955X_NFC_SIZE 0xb8 + + #define AR9300_OTP_BASE 0x14000 + #define AR9300_OTP_STATUS 0x15f18 +@@ -174,6 +190,9 @@ + #define AR71XX_AHB_DIV_SHIFT 20 + #define AR71XX_AHB_DIV_MASK 0x7 + ++#define AR71XX_ETH0_PLL_SHIFT 17 ++#define AR71XX_ETH1_PLL_SHIFT 19 ++ + #define AR724X_PLL_REG_CPU_CONFIG 0x00 + #define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +@@ -186,6 +205,8 @@ + #define AR724X_DDR_DIV_SHIFT 22 + #define AR724X_DDR_DIV_MASK 0x3 + ++#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c ++ + #define AR913X_PLL_REG_CPU_CONFIG 0x00 + #define AR913X_PLL_REG_ETH_CONFIG 0x04 + #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +@@ -198,6 +219,9 @@ + #define AR913X_AHB_DIV_SHIFT 19 + #define AR913X_AHB_DIV_MASK 0x1 + ++#define AR913X_ETH0_PLL_SHIFT 20 ++#define AR913X_ETH1_PLL_SHIFT 22 ++ + #define AR933X_PLL_CPU_CONFIG_REG 0x00 + #define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +@@ -219,6 +243,8 @@ + #define AR934X_PLL_CPU_CONFIG_REG 0x00 + #define AR934X_PLL_DDR_CONFIG_REG 0x04 + #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 ++#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + + #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 + #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +@@ -251,9 +277,13 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) ++ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 ++#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 ++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + + #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 + #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +@@ -378,16 +408,83 @@ + #define AR913X_RESET_USB_HOST BIT(5) + #define AR913X_RESET_USB_PHY BIT(4) + ++#define AR933X_RESET_GE1_MDIO BIT(23) ++#define AR933X_RESET_GE0_MDIO BIT(22) ++#define AR933X_RESET_GE1_MAC BIT(13) + #define AR933X_RESET_WMAC BIT(11) ++#define AR933X_RESET_GE0_MAC BIT(9) + #define AR933X_RESET_USB_HOST BIT(5) + #define AR933X_RESET_USB_PHY BIT(4) + #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + ++#define AR934X_RESET_HOST BIT(31) ++#define AR934X_RESET_SLIC BIT(30) ++#define AR934X_RESET_HDMA BIT(29) ++#define AR934X_RESET_EXTERNAL BIT(28) ++#define AR934X_RESET_RTC BIT(27) ++#define AR934X_RESET_PCIE_EP_INT BIT(26) ++#define AR934X_RESET_CHKSUM_ACC BIT(25) ++#define AR934X_RESET_FULL_CHIP BIT(24) ++#define AR934X_RESET_GE1_MDIO BIT(23) ++#define AR934X_RESET_GE0_MDIO BIT(22) ++#define AR934X_RESET_CPU_NMI BIT(21) ++#define AR934X_RESET_CPU_COLD BIT(20) ++#define AR934X_RESET_HOST_RESET_INT BIT(19) ++#define AR934X_RESET_PCIE_EP BIT(18) ++#define AR934X_RESET_UART1 BIT(17) ++#define AR934X_RESET_DDR BIT(16) ++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define AR934X_RESET_NANDF BIT(14) ++#define AR934X_RESET_GE1_MAC BIT(13) ++#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) + #define AR934X_RESET_USB_PHY_ANALOG BIT(11) ++#define AR934X_RESET_HOST_DMA_INT BIT(10) ++#define AR934X_RESET_GE0_MAC BIT(9) ++#define AR934X_RESET_ETH_SWITCH BIT(8) ++#define AR934X_RESET_PCIE_PHY BIT(7) ++#define AR934X_RESET_PCIE BIT(6) + #define AR934X_RESET_USB_HOST BIT(5) + #define AR934X_RESET_USB_PHY BIT(4) + #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) ++#define AR934X_RESET_LUT BIT(2) ++#define AR934X_RESET_MBOX BIT(1) ++#define AR934X_RESET_I2S BIT(0) ++ ++#define QCA955X_RESET_HOST BIT(31) ++#define QCA955X_RESET_SLIC BIT(30) ++#define QCA955X_RESET_HDMA BIT(29) ++#define QCA955X_RESET_EXTERNAL BIT(28) ++#define QCA955X_RESET_RTC BIT(27) ++#define QCA955X_RESET_PCIE_EP_INT BIT(26) ++#define QCA955X_RESET_CHKSUM_ACC BIT(25) ++#define QCA955X_RESET_FULL_CHIP BIT(24) ++#define QCA955X_RESET_GE1_MDIO BIT(23) ++#define QCA955X_RESET_GE0_MDIO BIT(22) ++#define QCA955X_RESET_CPU_NMI BIT(21) ++#define QCA955X_RESET_CPU_COLD BIT(20) ++#define QCA955X_RESET_HOST_RESET_INT BIT(19) ++#define QCA955X_RESET_PCIE_EP BIT(18) ++#define QCA955X_RESET_UART1 BIT(17) ++#define QCA955X_RESET_DDR BIT(16) ++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define QCA955X_RESET_NANDF BIT(14) ++#define QCA955X_RESET_GE1_MAC BIT(13) ++#define QCA955X_RESET_SGMII_ANALOG BIT(12) ++#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) ++#define QCA955X_RESET_HOST_DMA_INT BIT(10) ++#define QCA955X_RESET_GE0_MAC BIT(9) ++#define QCA955X_RESET_SGMII BIT(8) ++#define QCA955X_RESET_PCIE_PHY BIT(7) ++#define QCA955X_RESET_PCIE BIT(6) ++#define QCA955X_RESET_USB_HOST BIT(5) ++#define QCA955X_RESET_USB_PHY BIT(4) ++#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) ++#define QCA955X_RESET_LUT BIT(2) ++#define QCA955X_RESET_MBOX BIT(1) ++#define QCA955X_RESET_I2S BIT(0) + ++#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) ++#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + + #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +@@ -529,6 +626,12 @@ + #define AR71XX_GPIO_REG_INT_ENABLE 0x24 + #define AR71XX_GPIO_REG_FUNC 0x28 + ++#define AR934X_GPIO_REG_OUT_FUNC0 0x2c ++#define AR934X_GPIO_REG_OUT_FUNC1 0x30 ++#define AR934X_GPIO_REG_OUT_FUNC2 0x34 ++#define AR934X_GPIO_REG_OUT_FUNC3 0x38 ++#define AR934X_GPIO_REG_OUT_FUNC4 0x3c ++#define AR934X_GPIO_REG_OUT_FUNC5 0x40 + #define AR934X_GPIO_REG_FUNC 0x6c + + #define AR71XX_GPIO_COUNT 16 +@@ -560,4 +663,153 @@ + #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 + #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + ++#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) ++#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) ++#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) ++#define AR71XX_GPIO_FUNC_UART_EN BIT(8) ++#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) ++#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) ++ ++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) ++#define AR724X_GPIO_FUNC_SPI_EN BIT(18) ++#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) ++#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) ++#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) ++#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) ++#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) ++#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) ++#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) ++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) ++#define AR724X_GPIO_FUNC_UART_EN BIT(1) ++#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) ++ ++#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) ++#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) ++#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) ++#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) ++#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) ++#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) ++#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) ++#define AR913X_GPIO_FUNC_UART_EN BIT(8) ++#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) ++ ++#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) ++#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) ++#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) ++#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) ++#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) ++#define AR933X_GPIO_FUNC_SPI_EN BIT(18) ++#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) ++#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) ++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) ++#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) ++#define AR933X_GPIO_FUNC_UART_EN BIT(1) ++#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) ++ ++#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) ++#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) ++#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) ++#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) ++#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) ++#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) ++#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) ++#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) ++#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) ++ ++#define AR934X_GPIO_OUT_GPIO 0 ++#define AR934X_GPIO_OUT_SPI_CS1 7 ++#define AR934X_GPIO_OUT_LED_LINK0 41 ++#define AR934X_GPIO_OUT_LED_LINK1 42 ++#define AR934X_GPIO_OUT_LED_LINK2 43 ++#define AR934X_GPIO_OUT_LED_LINK3 44 ++#define AR934X_GPIO_OUT_LED_LINK4 45 ++#define AR934X_GPIO_OUT_EXT_LNA0 46 ++#define AR934X_GPIO_OUT_EXT_LNA1 47 ++ ++/* ++ * MII_CTRL block ++ */ ++#define AR71XX_MII_REG_MII0_CTRL 0x00 ++#define AR71XX_MII_REG_MII1_CTRL 0x04 ++ ++#define AR71XX_MII_CTRL_IF_MASK 3 ++#define AR71XX_MII_CTRL_SPEED_SHIFT 4 ++#define AR71XX_MII_CTRL_SPEED_MASK 3 ++#define AR71XX_MII_CTRL_SPEED_10 0 ++#define AR71XX_MII_CTRL_SPEED_100 1 ++#define AR71XX_MII_CTRL_SPEED_1000 2 ++ ++#define AR71XX_MII0_CTRL_IF_GMII 0 ++#define AR71XX_MII0_CTRL_IF_MII 1 ++#define AR71XX_MII0_CTRL_IF_RGMII 2 ++#define AR71XX_MII0_CTRL_IF_RMII 3 ++ ++#define AR71XX_MII1_CTRL_IF_RGMII 0 ++#define AR71XX_MII1_CTRL_IF_RMII 1 ++ ++/* ++ * AR933X GMAC interface ++ */ ++#define AR933X_GMAC_REG_ETH_CFG 0x00 ++ ++#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) ++#define AR933X_ETH_CFG_MII_GE0 BIT(1) ++#define AR933X_ETH_CFG_GMII_GE0 BIT(2) ++#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) ++#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) ++#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) ++#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) ++#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) ++#define AR933X_ETH_CFG_RMII_GE0 BIT(9) ++#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 ++#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) ++ ++/* ++ * AR934X GMAC Interface ++ */ ++#define AR934X_GMAC_REG_ETH_CFG 0x00 ++ ++#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) ++#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) ++#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) ++#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) ++#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) ++#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) ++#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) ++#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) ++#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) ++#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) ++#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) ++#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) ++#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) ++#define AR934X_ETH_CFG_RXD_DELAY BIT(14) ++#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 ++#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 ++#define AR934X_ETH_CFG_RDV_DELAY BIT(16) ++#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 ++#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 ++ ++/* ++ * QCA955X GMAC Interface ++ */ ++ ++#define QCA955X_GMAC_REG_ETH_CFG 0x00 ++ ++#define QCA955X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) ++ + #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.1/602-MIPS-ath79-add-openwrt-stuff.patch b/target/linux/ar71xx/patches-4.1/602-MIPS-ath79-add-openwrt-stuff.patch new file mode 100644 index 0000000..a772d9b --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/602-MIPS-ath79-add-openwrt-stuff.patch @@ -0,0 +1,76 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -98,6 +98,20 @@ config SOC_QCA955X + select PCI_AR724X if PCI + def_bool n + ++config ATH79_DEV_M25P80 ++ select ATH79_DEV_SPI ++ def_bool n ++ ++config ATH79_DEV_AP9X_PCI ++ select ATH79_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config ATH79_DEV_DSA ++ def_bool n ++ ++config ATH79_DEV_ETH ++ def_bool n ++ + config PCI_AR724X + def_bool n + +@@ -107,6 +121,10 @@ config ATH79_DEV_GPIO_BUTTONS + config ATH79_DEV_LEDS_GPIO + def_bool n + ++config ATH79_DEV_NFC ++ depends on (SOC_AR934X || SOC_QCA955X) ++ def_bool n ++ + config ATH79_DEV_SPI + def_bool n + +@@ -117,4 +135,13 @@ config ATH79_DEV_WMAC + depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) + def_bool n + ++config ATH79_NVRAM ++ def_bool n ++ ++config ATH79_PCI_ATH9K_FIXUP ++ def_bool n ++ ++config ATH79_ROUTERBOOT ++ def_bool n ++ + endif +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -17,13 +17,25 @@ obj-$(CONFIG_PCI) += pci.o + # Devices + # + obj-y += dev-common.o ++obj-$(CONFIG_ATH79_DEV_AP9X_PCI) += dev-ap9x-pci.o ++obj-$(CONFIG_ATH79_DEV_DSA) += dev-dsa.o ++obj-$(CONFIG_ATH79_DEV_ETH) += dev-eth.o + obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o + obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o ++obj-$(CONFIG_ATH79_DEV_M25P80) += dev-m25p80.o ++obj-$(CONFIG_ATH79_DEV_NFC) += dev-nfc.o + obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o + obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o + obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o + + # ++# Miscellaneous objects ++# ++obj-$(CONFIG_ATH79_NVRAM) += nvram.o ++obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o ++obj-$(CONFIG_ATH79_ROUTERBOOT) += routerboot.o ++ ++# + # Machines + # + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o diff --git a/target/linux/ar71xx/patches-4.1/603-MIPS-ath79-ap121-fixes.patch b/target/linux/ar71xx/patches-4.1/603-MIPS-ath79-ap121-fixes.patch new file mode 100644 index 0000000..706e5af --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/603-MIPS-ath79-ap121-fixes.patch @@ -0,0 +1,159 @@ +--- a/arch/mips/ath79/mach-ap121.c ++++ b/arch/mips/ath79/mach-ap121.c +@@ -1,19 +1,21 @@ + /* + * Atheros AP121 board support + * +- * Copyright (C) 2011 Gabor Juhos ++ * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +-#include "machtypes.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" ++#include "dev-m25p80.h" + #include "dev-spi.h" + #include "dev-usb.h" + #include "dev-wmac.h" ++#include "machtypes.h" + + #define AP121_GPIO_LED_WLAN 0 + #define AP121_GPIO_LED_USB 1 +@@ -24,7 +26,14 @@ + #define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ + #define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) + +-#define AP121_CAL_DATA_ADDR 0x1fff1000 ++#define AP121_MAC0_OFFSET 0x0000 ++#define AP121_MAC1_OFFSET 0x0006 ++#define AP121_CALDATA_OFFSET 0x1000 ++#define AP121_WMAC_MAC_OFFSET 0x1002 ++ ++#define AP121_MINI_GPIO_LED_WLAN 0 ++#define AP121_MINI_GPIO_BTN_JUMPSTART 12 ++#define AP121_MINI_GPIO_BTN_RESET 11 + + static struct gpio_led ap121_leds_gpio[] __initdata = { + { +@@ -58,35 +67,78 @@ static struct gpio_keys_button ap121_gpi + } + }; + +-static struct spi_board_info ap121_spi_info[] = { ++static struct gpio_led ap121_mini_leds_gpio[] __initdata = { + { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l1606e", +- } ++ .name = "ap121:green:wlan", ++ .gpio = AP121_MINI_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, + }; + +-static struct ath79_spi_platform_data ap121_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, ++static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = { ++ { ++ .desc = "jumpstart button", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART, ++ .active_low = 1, ++ }, ++ { ++ .desc = "reset button", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = AP121_MINI_GPIO_BTN_RESET, ++ .active_low = 1, ++ } + }; + ++static void __init ap121_common_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_wmac(art + AP121_CALDATA_OFFSET, ++ art + AP121_WMAC_MAC_OFFSET); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ /* LAN ports */ ++ ath79_register_eth(1); ++ ++ /* WAN port */ ++ ath79_register_eth(0); ++} ++ + static void __init ap121_setup(void) + { +- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR); ++ ap121_common_setup(); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), + ap121_leds_gpio); + ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap121_gpio_keys), + ap121_gpio_keys); +- +- ath79_register_spi(&ap121_spi_data, ap121_spi_info, +- ARRAY_SIZE(ap121_spi_info)); + ath79_register_usb(); +- ath79_register_wmac(cal_data, NULL); + } + + MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board", + ap121_setup); ++ ++static void __init ap121_mini_setup(void) ++{ ++ ap121_common_setup(); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio), ++ ap121_mini_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap121_mini_gpio_keys), ++ ap121_mini_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI", ++ ap121_mini_setup); +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi + config ATH79_MACH_AP121 + bool "Atheros AP121 reference board" + select SOC_AR933X ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -17,6 +17,7 @@ + enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ ++ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ diff --git a/target/linux/ar71xx/patches-4.1/604-MIPS-ath79-ap81-fixes.patch b/target/linux/ar71xx/patches-4.1/604-MIPS-ath79-ap81-fixes.patch new file mode 100644 index 0000000..3112eab --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/604-MIPS-ath79-ap81-fixes.patch @@ -0,0 +1,84 @@ +--- a/arch/mips/ath79/mach-ap81.c ++++ b/arch/mips/ath79/mach-ap81.c +@@ -9,12 +9,16 @@ + * by the Free Software Foundation. + */ + +-#include "machtypes.h" +-#include "dev-wmac.h" ++#include ++#include ++ ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" + #include "dev-usb.h" ++#include "dev-wmac.h" ++#include "machtypes.h" + + #define AP81_GPIO_LED_STATUS 1 + #define AP81_GPIO_LED_AOSS 3 +@@ -67,20 +71,6 @@ static struct gpio_keys_button ap81_gpio + } + }; + +-static struct spi_board_info ap81_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "m25p64", +- } +-}; +- +-static struct ath79_spi_platform_data ap81_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, +-}; +- + static void __init ap81_setup(void) + { + u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR); +@@ -90,10 +80,24 @@ static void __init ap81_setup(void) + ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, + ARRAY_SIZE(ap81_gpio_keys), + ap81_gpio_keys); +- ath79_register_spi(&ap81_spi_data, ap81_spi_info, +- ARRAY_SIZE(ap81_spi_info)); ++ ath79_register_m25p80(NULL); + ath79_register_wmac(cal_data, NULL); + ath79_register_usb(); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0); ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ath79_eth0_data.speed = SPEED_100; ++ ath79_eth0_data.duplex = DUPLEX_FULL; ++ ath79_eth0_data.has_ar8216 = 1; ++ ++ ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ath79_eth1_data.phy_mask = 0x10; ++ ++ ath79_register_eth(0); ++ ath79_register_eth(1); + } + + MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -30,9 +30,10 @@ config ATH79_MACH_AP136 + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help diff --git a/target/linux/ar71xx/patches-4.1/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-4.1/605-MIPS-ath79-db120-fixes.patch new file mode 100644 index 0000000..080165a --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/605-MIPS-ath79-db120-fixes.patch @@ -0,0 +1,204 @@ +--- a/arch/mips/ath79/mach-db120.c ++++ b/arch/mips/ath79/mach-db120.c +@@ -2,7 +2,7 @@ + * Atheros DB120 reference board support + * + * Copyright (c) 2011 Qualcomm Atheros +- * Copyright (c) 2011 Gabor Juhos ++ * Copyright (c) 2011-2012 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above +@@ -19,16 +19,26 @@ + */ + + #include ++#include ++#include + #include ++#include + +-#include "machtypes.h" ++#include ++ ++#include "common.h" ++#include "dev-ap9x-pci.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" ++#include "dev-m25p80.h" ++#include "dev-nfc.h" + #include "dev-spi.h" + #include "dev-usb.h" + #include "dev-wmac.h" +-#include "pci.h" ++#include "machtypes.h" + ++#define DB120_GPIO_LED_USB 11 + #define DB120_GPIO_LED_WLAN_5G 12 + #define DB120_GPIO_LED_WLAN_2G 13 + #define DB120_GPIO_LED_STATUS 14 +@@ -39,8 +49,10 @@ + #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ + #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) + +-#define DB120_WMAC_CALDATA_OFFSET 0x1000 +-#define DB120_PCIE_CALDATA_OFFSET 0x5000 ++#define DB120_MAC0_OFFSET 0 ++#define DB120_MAC1_OFFSET 6 ++#define DB120_WMAC_CALDATA_OFFSET 0x1000 ++#define DB120_PCIE_CALDATA_OFFSET 0x5000 + + static struct gpio_led db120_leds_gpio[] __initdata = { + { +@@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[] + .gpio = DB120_GPIO_LED_WLAN_2G, + .active_low = 1, + }, ++ { ++ .name = "db120:green:usb", ++ .gpio = DB120_GPIO_LED_USB, ++ .active_low = 1, ++ } + }; + + static struct gpio_keys_button db120_gpio_keys[] __initdata = { +@@ -76,60 +93,85 @@ static struct gpio_keys_button db120_gpi + }, + }; + +-static struct spi_board_info db120_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "s25sl064a", +- } ++static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { ++ .mode = AR8327_PAD_MAC_RGMII, ++ .txclk_delay_en = true, ++ .rxclk_delay_en = true, ++ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, ++ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + }; + +-static struct ath79_spi_platform_data db120_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, ++static struct ar8327_led_cfg db120_ar8327_led_cfg = { ++ .led_ctrl0 = 0x00000000, ++ .led_ctrl1 = 0xc737c737, ++ .led_ctrl2 = 0x00000000, ++ .led_ctrl3 = 0x00c30c00, ++ .open_drain = true, + }; + +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data db120_ath9k_data; +- +-static int db120_pci_plat_dev_init(struct pci_dev *dev) +-{ +- switch (PCI_SLOT(dev->devfn)) { +- case 0: +- dev->dev.platform_data = &db120_ath9k_data; +- break; +- } +- +- return 0; +-} +- +-static void __init db120_pci_init(u8 *eeprom) +-{ +- memcpy(db120_ath9k_data.eeprom_data, eeprom, +- sizeof(db120_ath9k_data.eeprom_data)); ++static struct ar8327_platform_data db120_ar8327_data = { ++ .pad0_cfg = &db120_ar8327_pad0_cfg, ++ .port0_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++ .led_cfg = &db120_ar8327_led_cfg, ++}; + +- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); +- ath79_register_pci(); +-} +-#else +-static inline void db120_pci_init(u8 *eeprom) {} +-#endif /* CONFIG_PCI */ ++static struct mdio_board_info db120_mdio0_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &db120_ar8327_data, ++ }, ++}; + + static void __init db120_setup(void) + { + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + ++ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO); ++ ath79_register_m25p80(NULL); ++ + ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), + db120_leds_gpio); + ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, + ARRAY_SIZE(db120_gpio_keys), + db120_gpio_keys); +- ath79_register_spi(&db120_spi_data, db120_spi_info, +- ARRAY_SIZE(db120_spi_info)); + ath79_register_usb(); + ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL); +- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET); ++ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL); ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | ++ AR934X_ETH_CFG_SW_ONLY_MODE); ++ ++ ath79_register_mdio(1, 0x0); ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0); ++ ++ mdiobus_register_board_info(db120_mdio0_info, ++ ARRAY_SIZE(db120_mdio0_info)); ++ ++ /* GMAC0 is connected to an AR8327 switch */ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = BIT(0); ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ath79_eth0_pll_data.pll_1000 = 0x06000000; ++ ath79_register_eth(0); ++ ++ /* GMAC1 is connected to the internal switch */ ++ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ++ ath79_register_eth(1); ++ ++ ath79_register_nfc(); + } + + MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -43,9 +43,12 @@ config ATH79_MACH_AP81 + config ATH79_MACH_DB120 + bool "Atheros DB120 reference board" + select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help diff --git a/target/linux/ar71xx/patches-4.1/606-MIPS-ath79-pb44-fixes.patch b/target/linux/ar71xx/patches-4.1/606-MIPS-ath79-pb44-fixes.patch new file mode 100644 index 0000000..f9ec775 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/606-MIPS-ath79-pb44-fixes.patch @@ -0,0 +1,153 @@ +--- a/arch/mips/ath79/mach-pb44.c ++++ b/arch/mips/ath79/mach-pb44.c +@@ -8,23 +8,48 @@ + * by the Free Software Foundation. + */ + ++#include + #include + #include + #include + #include + #include ++#include ++#include ++#include + +-#include "machtypes.h" ++#include ++#include ++ ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-spi.h" + #include "dev-usb.h" ++#include "machtypes.h" + #include "pci.h" + + #define PB44_GPIO_I2C_SCL 0 + #define PB44_GPIO_I2C_SDA 1 + ++#define PB44_PCF8757_VSC7395_CS 0 ++#define PB44_PCF8757_STEREO_CS 1 ++#define PB44_PCF8757_SLIC_CS0 2 ++#define PB44_PCF8757_SLIC_TEST 3 ++#define PB44_PCF8757_SLIC_INT0 4 ++#define PB44_PCF8757_SLIC_INT1 5 ++#define PB44_PCF8757_SW_RESET 6 ++#define PB44_PCF8757_SW_JUMP 8 ++#define PB44_PCF8757_LED_JUMP1 9 ++#define PB44_PCF8757_LED_JUMP2 10 ++#define PB44_PCF8757_TP24 11 ++#define PB44_PCF8757_TP25 12 ++#define PB44_PCF8757_TP26 13 ++#define PB44_PCF8757_TP27 14 ++#define PB44_PCF8757_TP28 15 ++ + #define PB44_GPIO_EXP_BASE 16 ++#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) + #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6) + #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8) + #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9) +@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data + .cs_line = 0, + }; + ++static struct ath79_spi_controller_data pb44_spi1_data = { ++ .cs_type = ATH79_SPI_CS_TYPE_GPIO, ++ .cs_line = PB44_GPIO_VSC7395_CS, ++}; ++ ++static void pb44_vsc7395_reset(void) ++{ ++ ath79_device_reset_set(AR71XX_RESET_GE1_PHY); ++ udelay(10); ++ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY); ++ mdelay(50); ++} ++ ++static struct vsc7385_platform_data pb44_vsc7395_data = { ++ .reset = pb44_vsc7395_reset, ++ .ucode_name = "vsc7395_ucode_pb44.bin", ++ .mac_cfg = { ++ .tx_ipg = 6, ++ .bit2 = 1, ++ .clk_sel = 0, ++ }, ++}; ++ ++static const char *pb44_part_probes[] = { ++ "RedBoot", ++ NULL, ++}; ++ ++static struct flash_platform_data pb44_flash_data = { ++ .part_probes = pb44_part_probes, ++}; ++ + static struct spi_board_info pb44_spi_info[] = { + { + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 25000000, + .modalias = "m25p64", ++ .platform_data = &pb44_flash_data, + .controller_data = &pb44_spi0_data, + }, ++ { ++ .bus_num = 0, ++ .chip_select = 1, ++ .max_speed_hz = 25000000, ++ .modalias = "spi-vsc7385", ++ .platform_data = &pb44_vsc7395_data, ++ .controller_data = &pb44_spi1_data, ++ } + }; + + static struct ath79_spi_platform_data pb44_spi_data = { + .bus_num = 0, +- .num_chipselect = 1, ++ .num_chipselect = 2, + }; + ++#define PB44_WAN_PHYMASK BIT(0) ++#define PB44_LAN_PHYMASK 0 ++#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) ++ + static void __init pb44_init(void) + { + i2c_register_board_info(0, pb44_i2c_board_info, +@@ -122,6 +192,22 @@ static void __init pb44_init(void) + ARRAY_SIZE(pb44_spi_info)); + ath79_register_usb(); + ath79_register_pci(); ++ ++ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK; ++ ++ ath79_register_eth(0); ++ ++ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ath79_eth1_pll_data.pll_1000 = 0x110000; ++ ++ ath79_register_eth(1); + } + + MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -58,6 +58,7 @@ config ATH79_MACH_DB120 + config ATH79_MACH_PB44 + bool "Atheros PB44 reference board" + select SOC_AR71XX ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_SPI diff --git a/target/linux/ar71xx/patches-4.1/607-MIPS-ath79-ubnt-xm-fixes.patch b/target/linux/ar71xx/patches-4.1/607-MIPS-ath79-ubnt-xm-fixes.patch new file mode 100644 index 0000000..50be509 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/607-MIPS-ath79-ubnt-xm-fixes.patch @@ -0,0 +1,103 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -70,9 +70,10 @@ config ATH79_MACH_PB44 + config ATH79_MACH_UBNT_XM + bool "Ubiquiti Networks XM (rev 1.0) board" + select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + help + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -16,10 +16,11 @@ + + #include + +-#include "machtypes.h" ++#include "dev-ap9x-pci.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" ++#include "machtypes.h" + #include "pci.h" + + #define UBNT_XM_GPIO_LED_L1 0 +@@ -32,7 +33,7 @@ + #define UBNT_XM_KEYS_POLL_INTERVAL 20 + #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL) + +-#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000) ++#define UBNT_XM_EEPROM_ADDR 0x1fff1000 + + static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { + { +@@ -65,48 +66,10 @@ static struct gpio_keys_button ubnt_xm_g + } + }; + +-static struct spi_board_info ubnt_xm_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l6405d", +- } +-}; +- +-static struct ath79_spi_platform_data ubnt_xm_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, +-}; +- +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data ubnt_xm_eeprom_data; +- +-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev) +-{ +- switch (PCI_SLOT(dev->devfn)) { +- case 0: +- dev->dev.platform_data = &ubnt_xm_eeprom_data; +- break; +- } +- +- return 0; +-} +- +-static void __init ubnt_xm_pci_init(void) +-{ +- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR, +- sizeof(ubnt_xm_eeprom_data.eeprom_data)); +- +- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init); +- ath79_register_pci(); +-} +-#else +-static inline void ubnt_xm_pci_init(void) {} +-#endif /* CONFIG_PCI */ +- + static void __init ubnt_xm_init(void) + { ++ u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR); ++ + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), + ubnt_xm_leds_gpio); + +@@ -114,10 +77,8 @@ static void __init ubnt_xm_init(void) + ARRAY_SIZE(ubnt_xm_gpio_keys), + ubnt_xm_gpio_keys); + +- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info, +- ARRAY_SIZE(ubnt_xm_spi_info)); +- +- ubnt_xm_pci_init(); ++ ath79_register_m25p80(NULL); ++ ap91_pci_init(eeprom, NULL); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, diff --git a/target/linux/ar71xx/patches-4.1/608-MIPS-ath79-ubnt-xm-add-more-boards.patch b/target/linux/ar71xx/patches-4.1/608-MIPS-ath79-ubnt-xm-add-more-boards.patch new file mode 100644 index 0000000..24b0f27 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/608-MIPS-ath79-ubnt-xm-add-more-boards.patch @@ -0,0 +1,659 @@ +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -12,16 +12,26 @@ + + #include + #include ++#include + #include ++#include ++#include + ++#include + #include ++#include + ++#include ++ ++#include "common.h" + #include "dev-ap9x-pci.h" ++#include "dev-eth.h" + #include "dev-gpio-buttons.h" + #include "dev-leds-gpio.h" + #include "dev-m25p80.h" ++#include "dev-usb.h" ++#include "dev-wmac.h" + #include "machtypes.h" +-#include "pci.h" + + #define UBNT_XM_GPIO_LED_L1 0 + #define UBNT_XM_GPIO_LED_L2 1 +@@ -37,19 +47,19 @@ + + static struct gpio_led ubnt_xm_leds_gpio[] __initdata = { + { +- .name = "ubnt-xm:red:link1", ++ .name = "ubnt:red:link1", + .gpio = UBNT_XM_GPIO_LED_L1, + .active_low = 0, + }, { +- .name = "ubnt-xm:orange:link2", ++ .name = "ubnt:orange:link2", + .gpio = UBNT_XM_GPIO_LED_L2, + .active_low = 0, + }, { +- .name = "ubnt-xm:green:link3", ++ .name = "ubnt:green:link3", + .gpio = UBNT_XM_GPIO_LED_L3, + .active_low = 0, + }, { +- .name = "ubnt-xm:green:link4", ++ .name = "ubnt:green:link4", + .gpio = UBNT_XM_GPIO_LED_L4, + .active_low = 0, + }, +@@ -66,9 +76,13 @@ static struct gpio_keys_button ubnt_xm_g + } + }; + ++#define UBNT_M_WAN_PHYMASK BIT(4) ++ + static void __init ubnt_xm_init(void) + { + u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR); ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); + + ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio), + ubnt_xm_leds_gpio); +@@ -79,9 +93,552 @@ static void __init ubnt_xm_init(void) + + ath79_register_m25p80(NULL); + ap91_pci_init(eeprom, NULL); ++ ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); ++ ath79_register_eth(0); + } + + MIPS_MACHINE(ATH79_MACH_UBNT_XM, + "UBNT-XM", + "Ubiquiti Networks XM (rev 1.0) board", + ubnt_xm_init); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", ++ ubnt_xm_init); ++ ++static void __init ubnt_rocket_m_setup(void) ++{ ++ ubnt_xm_init(); ++ ath79_register_usb(); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", ++ ubnt_rocket_m_setup); ++ ++static void __init ubnt_nano_m_setup(void) ++{ ++ ubnt_xm_init(); ++ ath79_register_eth(1); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", ++ ubnt_nano_m_setup); ++ ++static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:globe", ++ .gpio = 0, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:power", ++ .gpio = 11, ++ .active_low = 1, ++ .default_state = LEDS_GPIO_DEFSTATE_ON, ++ } ++}; ++ ++static void __init ubnt_airrouter_setup(void) ++{ ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1); ++ ++ ath79_register_eth(1); ++ ath79_register_eth(0); ++ ath79_register_usb(); ++ ++ ap91_pci_init(ee, NULL); ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio), ++ ubnt_airrouter_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter", ++ ubnt_airrouter_setup); ++ ++static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:orange:dome", ++ .gpio = 1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:dome", ++ .gpio = 0, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_led ubnt_unifi_outdoor_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:orange:front", ++ .gpio = 1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:front", ++ .gpio = 0, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_led ubnt_unifi_outdoor_plus_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:white:front", ++ .gpio = 1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:blue:front", ++ .gpio = 0, ++ .active_low = 0, ++ } ++}; ++ ++ ++static void __init ubnt_unifi_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); ++ ath79_register_eth(0); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio), ++ ubnt_unifi_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi", ++ ubnt_unifi_setup); ++ ++ ++#define UBNT_UNIFIOD_PRI_PHYMASK BIT(4) ++#define UBNT_UNIFIOD_2ND_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) ++ ++static void __init ubnt_unifi_outdoor_setup(void) ++{ ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK | ++ UBNT_UNIFIOD_2ND_PHYMASK)); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); ++ ath79_register_eth(0); ++ ath79_register_eth(1); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_leds_gpio), ++ ubnt_unifi_outdoor_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR, "UBNT-U20", ++ "Ubiquiti UniFiAP Outdoor", ++ ubnt_unifi_outdoor_setup); ++ ++ ++static void __init ubnt_unifi_outdoor_plus_setup(void) ++{ ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_mdio(0, ~(UBNT_UNIFIOD_PRI_PHYMASK | ++ UBNT_UNIFIOD_2ND_PHYMASK)); ++ ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0); ++ ath79_register_eth(0); ++ ath79_register_eth(1); ++ ++ ap91_pci_init(ee, NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_outdoor_plus_leds_gpio), ++ ubnt_unifi_outdoor_plus_leds_gpio); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, "UBNT-UOP", ++ "Ubiquiti UniFiAP Outdoor+", ++ ubnt_unifi_outdoor_plus_setup); ++ ++ ++static struct gpio_led ubnt_uap_pro_gpio_leds[] __initdata = { ++ { ++ .name = "ubnt:white:dome", ++ .gpio = 12, ++ }, { ++ .name = "ubnt:blue:dome", ++ .gpio = 13, ++ } ++}; ++ ++static struct gpio_keys_button uap_pro_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 17, ++ .active_low = 1, ++ } ++}; ++ ++static struct ar8327_pad_cfg uap_pro_ar8327_pad0_cfg = { ++ .mode = AR8327_PAD_MAC_RGMII, ++ .txclk_delay_en = true, ++ .rxclk_delay_en = true, ++ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, ++ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, ++}; ++ ++static struct ar8327_platform_data uap_pro_ar8327_data = { ++ .pad0_cfg = &uap_pro_ar8327_pad0_cfg, ++ .port0_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++}; ++ ++static struct mdio_board_info uap_pro_mdio0_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &uap_pro_ar8327_data, ++ }, ++}; ++ ++#define UAP_PRO_MAC0_OFFSET 0x0000 ++#define UAP_PRO_MAC1_OFFSET 0x0006 ++#define UAP_PRO_WMAC_CALDATA_OFFSET 0x1000 ++#define UAP_PRO_PCI_CALDATA_OFFSET 0x5000 ++ ++static void __init ubnt_uap_pro_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_uap_pro_gpio_leds), ++ ubnt_uap_pro_gpio_leds); ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(uap_pro_gpio_keys), ++ uap_pro_gpio_keys); ++ ++ ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ++ ++ ath79_register_mdio(0, 0x0); ++ mdiobus_register_board_info(uap_pro_mdio0_info, ++ ARRAY_SIZE(uap_pro_mdio0_info)); ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ++ ath79_init_mac(ath79_eth0_data.mac_addr, ++ eeprom + UAP_PRO_MAC0_OFFSET, 0); ++ ++ /* GMAC0 is connected to an AR8327 switch */ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = BIT(0); ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ath79_eth0_pll_data.pll_1000 = 0x06000000; ++ ath79_register_eth(0); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_UAP_PRO, "UAP-PRO", "Ubiquiti UniFi AP Pro", ++ ubnt_uap_pro_setup); ++ ++#define UBNT_XW_GPIO_LED_L1 11 ++#define UBNT_XW_GPIO_LED_L2 16 ++#define UBNT_XW_GPIO_LED_L3 13 ++#define UBNT_XW_GPIO_LED_L4 14 ++ ++static struct gpio_led ubnt_xw_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:red:link1", ++ .gpio = UBNT_XW_GPIO_LED_L1, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:orange:link2", ++ .gpio = UBNT_XW_GPIO_LED_L2, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link3", ++ .gpio = UBNT_XW_GPIO_LED_L3, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link4", ++ .gpio = UBNT_XW_GPIO_LED_L4, ++ .active_low = 1, ++ }, ++}; ++ ++#define UBNT_ROCKET_TI_GPIO_LED_L1 16 ++#define UBNT_ROCKET_TI_GPIO_LED_L2 17 ++#define UBNT_ROCKET_TI_GPIO_LED_L3 18 ++#define UBNT_ROCKET_TI_GPIO_LED_L4 19 ++#define UBNT_ROCKET_TI_GPIO_LED_L5 20 ++#define UBNT_ROCKET_TI_GPIO_LED_L6 21 ++static struct gpio_led ubnt_rocket_ti_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:link1", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L1, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link2", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L2, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link3", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L3, ++ .active_low = 1, ++ }, { ++ .name = "ubnt:green:link4", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L4, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:link5", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L5, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:link6", ++ .gpio = UBNT_ROCKET_TI_GPIO_LED_L6, ++ .active_low = 0, ++ }, ++}; ++ ++static void __init ubnt_xw_init(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio), ++ ubnt_xw_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++ ++ ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ++ ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0_SLAVE); ++ ath79_init_mac(ath79_eth0_data.mac_addr, ++ eeprom + UAP_PRO_MAC0_OFFSET, 0); ++ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++} ++ ++static void __init ubnt_nano_m_xw_setup(void) ++{ ++ ubnt_xw_init(); ++ ++ /* GMAC0 is connected to an AR8326 switch */ ++ ath79_register_mdio(0, ~(BIT(0) | BIT(1) | BIT(5))); ++ ath79_eth0_data.phy_mask = (BIT(0) | BIT(1) | BIT(5)); ++ ath79_eth0_data.speed = SPEED_100; ++ ath79_eth0_data.duplex = DUPLEX_FULL; ++ ath79_register_eth(0); ++} ++ ++static void __init ubnt_loco_m_xw_setup(void) ++{ ++ ubnt_xw_init(); ++ ++ ath79_register_mdio(0, ~BIT(1)); ++ ath79_eth0_data.phy_mask = BIT(1); ++ ath79_register_eth(0); ++} ++ ++static void __init ubnt_rocket_m_xw_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xw_leds_gpio), ++ ubnt_xw_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++ ++ ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ++ ath79_init_mac(ath79_eth0_data.mac_addr, ++ eeprom + UAP_PRO_MAC0_OFFSET, 0); ++ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ++ ath79_register_mdio(0, ~BIT(4)); ++ ath79_eth0_data.phy_mask = BIT(4); ++ ath79_eth0_pll_data.pll_1000 = 0x06000000; ++ ath79_register_eth(0); ++} ++ ++static struct at803x_platform_data ubnt_rocket_m_ti_at803_data = { ++ .disable_smarteee = 1, ++ .enable_rgmii_rx_delay = 1, ++ .enable_rgmii_tx_delay = 1, ++}; ++static struct mdio_board_info ubnt_rocket_m_ti_mdio_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 4, ++ .platform_data = &ubnt_rocket_m_ti_at803_data, ++ }, ++}; ++ ++static void __init ubnt_rocket_m_ti_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rocket_ti_leds_gpio), ++ ubnt_rocket_ti_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_xm_gpio_keys), ++ ubnt_xm_gpio_keys); ++ ++ ap91_pci_init(eeprom + 0x1000, NULL); ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); ++ ath79_setup_ar934x_eth_rx_delay(3, 3); ++ ath79_init_mac(ath79_eth0_data.mac_addr, ++ eeprom + UAP_PRO_MAC0_OFFSET, 0); ++ ath79_init_mac(ath79_eth1_data.mac_addr, ++ eeprom + UAP_PRO_MAC1_OFFSET, 0); ++ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ++ ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; ++ ++ mdiobus_register_board_info(ubnt_rocket_m_ti_mdio_info, ++ ARRAY_SIZE(ubnt_rocket_m_ti_mdio_info)); ++ ath79_register_mdio(0, 0x0); ++ ++ ++ ath79_eth0_data.phy_mask = BIT(4); ++ /* read out from vendor */ ++ ath79_eth0_pll_data.pll_1000 = 0x2000000; ++ ath79_eth0_pll_data.pll_10 = 0x1313; ++ ath79_register_eth(0); ++ ++ ath79_register_mdio(1, 0x0); ++ ath79_eth1_data.phy_mask = BIT(3); ++ ath79_register_eth(1); ++} ++ ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M_XW, "UBNT-NM-XW", "Ubiquiti Nanostation M XW", ++ ubnt_nano_m_xw_setup); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_LOCO_M_XW, "UBNT-LOCO-XW", "Ubiquiti Loco M XW", ++ ubnt_loco_m_xw_setup); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_XW, "UBNT-RM-XW", "Ubiquiti Rocket M XW", ++ ubnt_rocket_m_xw_setup); ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M_TI, "UBNT-RM-TI", "Ubiquiti Rocket M TI", ++ ubnt_rocket_m_ti_setup); ++ ++static struct gpio_led ubnt_airgateway_gpio_leds[] __initdata = { ++ { ++ .name = "ubnt:blue:wlan", ++ .gpio = 0, ++ }, { ++ .name = "ubnt:white:status", ++ .gpio = 1, ++ }, ++}; ++ ++static struct gpio_keys_button airgateway_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 12, ++ .active_low = 1, ++ } ++}; ++ ++static void __init ubnt_airgateway_setup(void) ++{ ++ u32 t; ++ u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ ++ ++ ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN | ++ AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN | ++ AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN | ++ AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN | ++ AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN); ++ ++ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); ++ t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN; ++ ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_gpio_leds), ++ ubnt_airgateway_gpio_leds); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(airgateway_gpio_keys), ++ airgateway_gpio_keys); ++ ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0); ++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0); ++ ++ ath79_register_mdio(0, 0x0); ++ ++ ath79_register_eth(1); ++ ath79_register_eth(0); ++ ++ ath79_register_wmac(ee, NULL); ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_AIRGW, "UBNT-AGW", "Ubiquiti AirGateway", ++ ubnt_airgateway_setup); ++ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -68,12 +68,16 @@ config ATH79_MACH_PB44 + Atheros PB44 reference board. + + config ATH79_MACH_UBNT_XM +- bool "Ubiquiti Networks XM (rev 1.0) board" ++ bool "Ubiquiti Networks XM/UniFi boards" + select SOC_AR724X ++ select SOC_AR934X + select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC + help + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -22,6 +22,15 @@ enum ath79_mach_type { + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ ++ ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */ ++ ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ ++ ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ ++ ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ ++ ATH79_MACH_UBNT_ROCKET_M_XW, /* Ubiquiti Rocket M XW*/ ++ ATH79_MACH_UBNT_ROCKET_M_TI, /* Ubiquiti Rocket M TI*/ ++ ATH79_MACH_UBNT_UAP_PRO, /* Ubiquiti UniFi AP Pro */ ++ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */ ++ ATH79_MACH_UBNT_UNIFI_OUTDOOR, /* Ubiquiti UnifiAP Outdoor */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ + }; + diff --git a/target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch new file mode 100644 index 0000000..bf64fc6 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch @@ -0,0 +1,312 @@ +--- a/arch/mips/ath79/mach-ap136.c ++++ b/arch/mips/ath79/mach-ap136.c +@@ -18,23 +18,29 @@ + * + */ + +-#include +-#include ++#include ++#include + +-#include "machtypes.h" ++#include ++ ++#include "common.h" ++#include "pci.h" ++#include "dev-ap9x-pci.h" + #include "dev-gpio-buttons.h" ++#include "dev-eth.h" + #include "dev-leds-gpio.h" +-#include "dev-spi.h" ++#include "dev-m25p80.h" ++#include "dev-nfc.h" + #include "dev-usb.h" + #include "dev-wmac.h" +-#include "pci.h" ++#include "machtypes.h" + +-#define AP136_GPIO_LED_STATUS_RED 14 +-#define AP136_GPIO_LED_STATUS_GREEN 19 + #define AP136_GPIO_LED_USB 4 +-#define AP136_GPIO_LED_WLAN_2G 13 + #define AP136_GPIO_LED_WLAN_5G 12 ++#define AP136_GPIO_LED_WLAN_2G 13 ++#define AP136_GPIO_LED_STATUS_RED 14 + #define AP136_GPIO_LED_WPS_RED 15 ++#define AP136_GPIO_LED_STATUS_GREEN 19 + #define AP136_GPIO_LED_WPS_GREEN 20 + + #define AP136_GPIO_BTN_WPS 16 +@@ -43,37 +49,39 @@ + #define AP136_KEYS_POLL_INTERVAL 20 /* msecs */ + #define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL) + +-#define AP136_WMAC_CALDATA_OFFSET 0x1000 +-#define AP136_PCIE_CALDATA_OFFSET 0x5000 ++#define AP136_MAC0_OFFSET 0 ++#define AP136_MAC1_OFFSET 6 ++#define AP136_WMAC_CALDATA_OFFSET 0x1000 ++#define AP136_PCIE_CALDATA_OFFSET 0x5000 + + static struct gpio_led ap136_leds_gpio[] __initdata = { + { +- .name = "qca:green:status", ++ .name = "ap136:green:status", + .gpio = AP136_GPIO_LED_STATUS_GREEN, + .active_low = 1, + }, + { +- .name = "qca:red:status", ++ .name = "ap136:red:status", + .gpio = AP136_GPIO_LED_STATUS_RED, + .active_low = 1, + }, + { +- .name = "qca:green:wps", ++ .name = "ap136:green:wps", + .gpio = AP136_GPIO_LED_WPS_GREEN, + .active_low = 1, + }, + { +- .name = "qca:red:wps", ++ .name = "ap136:red:wps", + .gpio = AP136_GPIO_LED_WPS_RED, + .active_low = 1, + }, + { +- .name = "qca:red:wlan-2g", ++ .name = "ap136:red:wlan-2g", + .gpio = AP136_GPIO_LED_WLAN_2G, + .active_low = 1, + }, + { +- .name = "qca:red:usb", ++ .name = "ap136:red:usb", + .gpio = AP136_GPIO_LED_USB, + .active_low = 1, + } +@@ -98,59 +106,151 @@ static struct gpio_keys_button ap136_gpi + }, + }; + +-static struct spi_board_info ap136_spi_info[] = { +- { +- .bus_num = 0, +- .chip_select = 0, +- .max_speed_hz = 25000000, +- .modalias = "mx25l6405d", +- } ++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg; ++static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg; ++ ++static struct ar8327_platform_data ap136_ar8327_data = { ++ .pad0_cfg = &ap136_ar8327_pad0_cfg, ++ .pad6_cfg = &ap136_ar8327_pad6_cfg, ++ .port0_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++ .port6_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, + }; + +-static struct ath79_spi_platform_data ap136_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, ++static struct mdio_board_info ap136_mdio0_info[] = { ++ { ++ .bus_id = "ag71xx-mdio.0", ++ .phy_addr = 0, ++ .platform_data = &ap136_ar8327_data, ++ }, + }; + +-#ifdef CONFIG_PCI +-static struct ath9k_platform_data ap136_ath9k_data; ++static void __init ap136_common_setup(void) ++{ ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), ++ ap136_leds_gpio); ++ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(ap136_gpio_keys), ++ ap136_gpio_keys); ++ ++ ath79_register_usb(); ++ ath79_register_nfc(); ++ ++ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL); ++ ++ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); + +-static int ap136_pci_plat_dev_init(struct pci_dev *dev) ++ ath79_register_mdio(0, 0x0); ++ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0); ++ ++ mdiobus_register_board_info(ap136_mdio0_info, ++ ARRAY_SIZE(ap136_mdio0_info)); ++ ++ /* GMAC0 is connected to the RMGII interface */ ++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ath79_eth0_data.phy_mask = BIT(0); ++ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; ++ ++ ath79_register_eth(0); ++ ++ /* GMAC1 is connected tot eh SGMII interface */ ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; ++ ath79_eth1_data.speed = SPEED_1000; ++ ath79_eth1_data.duplex = DUPLEX_FULL; ++ ++ ath79_register_eth(1); ++} ++ ++static void __init ap136_010_setup(void) + { +- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0) +- dev->dev.platform_data = &ap136_ath9k_data; ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + +- return 0; ++ /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */ ++ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII; ++ ap136_ar8327_pad0_cfg.txclk_delay_en = true; ++ ap136_ar8327_pad0_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; ++ ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; ++ ++ /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */ ++ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII; ++ ap136_ar8327_pad6_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0; ++ ++ ath79_eth0_pll_data.pll_1000 = 0xa6000000; ++ ath79_eth1_pll_data.pll_1000 = 0x03000101; ++ ++ ap136_common_setup(); ++ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); + } + +-static void __init ap136_pci_init(u8 *eeprom) ++MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", ++ "Atheros AP136-010 reference board", ++ ap136_010_setup); ++ ++static void __init ap136_020_common_setup(void) + { +- memcpy(ap136_ath9k_data.eeprom_data, eeprom, +- sizeof(ap136_ath9k_data.eeprom_data)); ++ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ ++ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; ++ ap136_ar8327_pad0_cfg.sgmii_delay_en = true; ++ ++ /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */ ++ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII; ++ ap136_ar8327_pad6_cfg.txclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.rxclk_delay_en = true; ++ ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1; ++ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2; + +- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init); +- ath79_register_pci(); ++ ath79_eth0_pll_data.pll_1000 = 0x56000000; ++ ath79_eth1_pll_data.pll_1000 = 0x03000101; ++ ++ ap136_common_setup(); + } +-#else +-static inline void ap136_pci_init(u8 *eeprom) {} +-#endif /* CONFIG_PCI */ + +-static void __init ap136_setup(void) ++static void __init ap136_020_setup(void) + { + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + +- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio), +- ap136_leds_gpio); +- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL, +- ARRAY_SIZE(ap136_gpio_keys), +- ap136_gpio_keys); +- ath79_register_spi(&ap136_spi_data, ap136_spi_info, +- ARRAY_SIZE(ap136_spi_info)); +- ath79_register_usb(); +- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET); +- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET); ++ ap136_020_common_setup(); ++ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL); + } + +-MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010", +- "Atheros AP136-010 reference board", +- ap136_setup); ++MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020", ++ "Atheros AP136-020 reference board", ++ ap136_020_setup); ++ ++/* ++ * AP135-020 is similar to AP136-020, any future AP135 specific init ++ * code can be added here. ++ */ ++static void __init ap135_020_setup(void) ++{ ++ ap136_leds_gpio[0].name = "ap135:green:status"; ++ ap136_leds_gpio[1].name = "ap135:red:status"; ++ ap136_leds_gpio[2].name = "ap135:green:wps"; ++ ap136_leds_gpio[3].name = "ap135:red:wps"; ++ ap136_leds_gpio[4].name = "ap135:red:wlan-2g"; ++ ap136_leds_gpio[5].name = "ap135:red:usb"; ++ ++ ap136_020_common_setup(); ++ ath79_register_pci(); ++} ++ ++MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020", ++ "Atheros AP135-020 reference board", ++ ap135_020_setup); +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -18,7 +18,9 @@ enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, + ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ ++ ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ ++ ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -16,16 +16,17 @@ config ATH79_MACH_AP121 + Atheros AP121 reference board. + + config ATH79_MACH_AP136 +- bool "Atheros AP136 reference board" ++ bool "Atheros AP136/AP135 reference board" + select SOC_QCA955X + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC + select ATH79_DEV_SPI + select ATH79_DEV_USB + select ATH79_DEV_WMAC + help + Say 'Y' here if you want your kernel to support the +- Atheros AP136 reference board. ++ Atheros AP136 or AP135 reference boards. + + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" diff --git a/target/linux/ar71xx/patches-4.1/610-MIPS-ath79-UBNT-add-airGateway-pro-support.patch b/target/linux/ar71xx/patches-4.1/610-MIPS-ath79-UBNT-add-airGateway-pro-support.patch new file mode 100644 index 0000000..27cc1e5 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/610-MIPS-ath79-UBNT-add-airGateway-pro-support.patch @@ -0,0 +1,62 @@ +--- a/arch/mips/ath79/mach-ubnt-xm.c ++++ b/arch/mips/ath79/mach-ubnt-xm.c +@@ -642,3 +642,59 @@ static void __init ubnt_airgateway_setup + MIPS_MACHINE(ATH79_MACH_UBNT_AIRGW, "UBNT-AGW", "Ubiquiti AirGateway", + ubnt_airgateway_setup); + ++static struct gpio_led ubnt_airgateway_pro_gpio_leds[] __initdata = { ++ { ++ .name = "ubnt:blue:wlan", ++ .gpio = 13, ++ }, { ++ .name = "ubnt:white:status", ++ .gpio = 17, ++ }, ++}; ++ ++ ++static struct gpio_keys_button airgateway_pro_gpio_keys[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL, ++ .gpio = 12, ++ .active_low = 1, ++ } ++}; ++ ++static void __init ubnt_airgateway_pro_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *mac0 = (u8 *) KSEG1ADDR(0x1fff0000); ++ ++ ath79_register_m25p80(NULL); ++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airgateway_pro_gpio_leds), ++ ubnt_airgateway_pro_gpio_leds); ++ ++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL, ++ ARRAY_SIZE(airgateway_pro_gpio_keys), ++ airgateway_pro_gpio_keys); ++ ++ ath79_register_wmac(eeprom + UAP_PRO_WMAC_CALDATA_OFFSET, NULL); ++ ap91_pci_init(eeprom + UAP_PRO_PCI_CALDATA_OFFSET, NULL); ++ ++ ++ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); ++ ++ ath79_register_mdio(1, 0x0); ++ ++ /* GMAC0 is left unused in this configuration */ ++ ++ /* GMAC1 is connected to MAC0 on the internal switch */ ++ /* The PoE/WAN port connects to port 5 on the internal switch */ ++ /* The LAN port connects to port 4 on the internal switch */ ++ ath79_init_mac(ath79_eth1_data.mac_addr, mac0, 0); ++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; ++ ath79_register_eth(1); ++ ++} ++ ++MIPS_MACHINE(ATH79_MACH_UBNT_AIRGWP, "UBNT-AGWP", "Ubiquiti AirGateway Pro", ++ ubnt_airgateway_pro_setup); diff --git a/target/linux/ar71xx/patches-4.1/611-MIPS-ath79-wdt-timeout.patch b/target/linux/ar71xx/patches-4.1/611-MIPS-ath79-wdt-timeout.patch new file mode 100644 index 0000000..7a70ac3 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/611-MIPS-ath79-wdt-timeout.patch @@ -0,0 +1,25 @@ +MIPS: ath79: fix maximum timeout + +If the userland tries to set a timeout higher than the max_timeout, then we should fallback to max_timeout. + +Signed-off-by: John Crispin + +--- a/drivers/watchdog/ath79_wdt.c ++++ b/drivers/watchdog/ath79_wdt.c +@@ -114,10 +114,14 @@ static inline void ath79_wdt_disable(voi + + static int ath79_wdt_set_timeout(int val) + { +- if (val < 1 || val > max_timeout) ++ if (val < 1) + return -EINVAL; + +- timeout = val; ++ if (val > max_timeout) ++ timeout = max_timeout; ++ else ++ timeout = val; ++ + ath79_wdt_keepalive(); + + return 0; diff --git a/target/linux/ar71xx/patches-4.1/612-MIPS-ath79-set-buffalo-txgain.patch b/target/linux/ar71xx/patches-4.1/612-MIPS-ath79-set-buffalo-txgain.patch new file mode 100644 index 0000000..4e3ac70 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/612-MIPS-ath79-set-buffalo-txgain.patch @@ -0,0 +1,24 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -308,6 +308,11 @@ void __init ath79_wmac_disable_5ghz(void + ath79_wmac_data.disable_5ghz = true; + } + ++void __init ath79_wmac_set_tx_gain_buffalo(void) ++{ ++ ath79_wmac_data.tx_gain_buffalo = true; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -16,6 +16,7 @@ void ath79_register_wmac(u8 *cal_data, u + void ath79_register_wmac_simple(void); + void ath79_wmac_disable_2ghz(void); + void ath79_wmac_disable_5ghz(void); ++void ath79_wmac_set_tx_gain_buffalo(void); + + bool ar93xx_wmac_read_mac_address(u8 *dest); + diff --git a/target/linux/ar71xx/patches-4.1/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch b/target/linux/ar71xx/patches-4.1/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch new file mode 100644 index 0000000..a832bf8 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/613-MIPS-ath79-add-ath79_wmac_setup_ext_lna_gpio-helper.patch @@ -0,0 +1,76 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -18,9 +18,11 @@ + #include + #include + #include ++#include + + #include + #include ++#include "common.h" + #include "dev-wmac.h" + + static u8 ath79_wmac_mac[ETH_ALEN]; +@@ -313,6 +315,51 @@ void __init ath79_wmac_set_tx_gain_buffa + ath79_wmac_data.tx_gain_buffalo = true; + } + ++static int ath79_request_ext_lna_gpio(unsigned chain, int gpio) ++{ ++ char buf[32]; ++ char *label; ++ int err; ++ ++ scnprintf(buf, sizeof(buf), "external LNA%u", chain); ++ label = kstrdup(buf, GFP_KERNEL); ++ ++ err = gpio_request_one(gpio, GPIOF_DIR_OUT | GPIOF_INIT_LOW, label); ++ if (err) { ++ pr_err("unable to request GPIO%d for external LNA%u\n", ++ gpio, chain); ++ kfree(label); ++ } ++ ++ return err; ++} ++ ++static void ar934x_set_ext_lna_gpio(unsigned chain, int gpio) ++{ ++ unsigned int sel; ++ int err; ++ ++ if (WARN_ON(chain > 1)) ++ return; ++ ++ err = ath79_request_ext_lna_gpio(chain, gpio); ++ if (err) ++ return; ++ ++ if (chain == 0) ++ sel = AR934X_GPIO_OUT_EXT_LNA0; ++ else ++ sel = AR934X_GPIO_OUT_EXT_LNA1; ++ ++ ath79_gpio_output_select(gpio, sel); ++} ++ ++void __init ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio) ++{ ++ if (soc_is_ar934x()) ++ ar934x_set_ext_lna_gpio(chain, gpio); ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -17,6 +17,7 @@ void ath79_register_wmac_simple(void); + void ath79_wmac_disable_2ghz(void); + void ath79_wmac_disable_5ghz(void); + void ath79_wmac_set_tx_gain_buffalo(void); ++void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio); + + bool ar93xx_wmac_read_mac_address(u8 *dest); + diff --git a/target/linux/ar71xx/patches-4.1/615-MIPS-ath79-ap83-remove-mtd-partitions.patch b/target/linux/ar71xx/patches-4.1/615-MIPS-ath79-ap83-remove-mtd-partitions.patch new file mode 100644 index 0000000..60872ae --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/615-MIPS-ath79-ap83-remove-mtd-partitions.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/ath79/mach-ap83.c ++++ b/arch/mips/ath79/mach-ap83.c +@@ -42,41 +42,8 @@ + #define AP83_KEYS_POLL_INTERVAL 20 /* msecs */ + #define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL) + +-static struct mtd_partition ap83_flash_partitions[] = { +- { +- .name = "u-boot", +- .offset = 0, +- .size = 0x040000, +- .mask_flags = MTD_WRITEABLE, +- }, { +- .name = "u-boot-env", +- .offset = 0x040000, +- .size = 0x020000, +- .mask_flags = MTD_WRITEABLE, +- }, { +- .name = "kernel", +- .offset = 0x060000, +- .size = 0x140000, +- }, { +- .name = "rootfs", +- .offset = 0x1a0000, +- .size = 0x650000, +- }, { +- .name = "art", +- .offset = 0x7f0000, +- .size = 0x010000, +- .mask_flags = MTD_WRITEABLE, +- }, { +- .name = "firmware", +- .offset = 0x060000, +- .size = 0x790000, +- } +-}; +- + static struct physmap_flash_data ap83_flash_data = { + .width = 2, +- .parts = ap83_flash_partitions, +- .nr_parts = ARRAY_SIZE(ap83_flash_partitions), + }; + + static struct resource ap83_flash_resources[] = { diff --git a/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch new file mode 100644 index 0000000..d739ccd --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -0,0 +1,730 @@ +From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001 +Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net> +From: Matthias Schiffer +Date: Sat, 29 Mar 2014 20:26:08 +0100 +Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC + +Note that the clock calculation looks very similar to the QCA955x, but the +meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. +--- + arch/mips/ath79/Kconfig | 6 +- + arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++ + arch/mips/ath79/common.c | 4 ++ + arch/mips/ath79/dev-common.c | 1 + + arch/mips/ath79/dev-wmac.c | 20 +++++++ + arch/mips/ath79/early_printk.c | 1 + + arch/mips/ath79/gpio.c | 4 +- + arch/mips/ath79/irq.c | 4 ++ + arch/mips/ath79/setup.c | 8 ++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++ + arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++ + 11 files changed, 182 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -105,6 +105,10 @@ config SOC_AR934X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA953X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config SOC_QCA955X + select HW_HAS_PCI + select PCI_AR724X if PCI +@@ -144,7 +148,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X) + def_bool n + + config ATH79_NVRAM +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo + iounmap(dpll_base); + } + ++static void __init qca953x_clocks_init(void) ++{ ++ unsigned long ref_rate; ++ unsigned long cpu_rate; ++ unsigned long ddr_rate; ++ unsigned long ahb_rate; ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40) ++ ref_rate = 40 * 1000 * 1000; ++ else ++ ref_rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_NINT_MASK; ++ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK; ++ ++ cpu_pll = nint * ref_rate / ref_div; ++ cpu_pll += frac * (ref_rate >> 6) / ref_div; ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_NINT_MASK; ++ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK; ++ ++ ddr_pll = nint * ref_rate / ref_div; ++ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS) ++ cpu_rate = ref_rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) ++ cpu_rate = cpu_pll / (postdiv + 1); ++ else ++ cpu_rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS) ++ ddr_rate = ref_rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) ++ ddr_rate = ddr_pll / (postdiv + 1); ++ else ++ ddr_rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) ++ ahb_rate = ref_rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ahb_rate = ddr_pll / (postdiv + 1); ++ else ++ ahb_rate = cpu_pll / (postdiv + 1); ++ ++ ath79_add_sys_clkdev("ref", ref_rate); ++ ath79_add_sys_clkdev("cpu", cpu_rate); ++ ath79_add_sys_clkdev("ddr", ddr_rate); ++ ath79_add_sys_clkdev("ahb", ahb_rate); ++ ++ clk_add_alias("wdt", NULL, "ref", NULL); ++ clk_add_alias("uart", NULL, "ref", NULL); ++} ++ + static void __init qca955x_clocks_init(void) + { + unsigned long ref_rate; +@@ -447,6 +532,8 @@ void __init ath79_clocks_init(void) + ar933x_clocks_init(); + else if (soc_is_ar934x()) + ar934x_clocks_init(); ++ else if (soc_is_qca953x()) ++ qca953x_clocks_init(); + else if (soc_is_qca955x()) + qca955x_clocks_init(); + else +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca953x()) ++ reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else +@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask) + reg = AR933X_RESET_REG_RESET_MODULE; + else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca953x()) ++ reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; + else +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -93,6 +93,7 @@ void __init ath79_register_uart(void) + soc_is_ar724x() || + soc_is_ar913x() || + soc_is_ar934x() || ++ soc_is_qca953x() || + soc_is_qca955x()) { + ath79_uart_data[0].uartclk = uart_clk_rate; + platform_device_register(&ath79_uart_device); +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + ++static void __init qca953x_usb_setup(void) ++{ ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); ++ ++ ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE); ++ udelay(1000); ++ ++ ath79_device_reset_clear(QCA953X_RESET_USB_PHY); ++ udelay(1000); ++ ++ ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG); ++ udelay(1000); ++ ++ ath79_device_reset_clear(QCA953X_RESET_USB_HOST); ++ udelay(1000); ++ ++ ath79_usb_register("ehci-platform", -1, ++ QCA953X_EHCI_BASE, QCA953X_EHCI_SIZE, ++ ATH79_CPU_IRQ(3), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); ++} ++ + static void qca955x_usb_reset_notifier(struct platform_device *pdev) + { + u32 base; +@@ -286,6 +310,8 @@ void __init ath79_register_usb(void) + ar933x_usb_setup(); + else if (soc_is_ar934x()) + ar934x_usb_setup(); ++ else if (soc_is_qca953x()) ++ qca953x_usb_setup(); + else if (soc_is_qca955x()) + qca955x_usb_setup(); + else +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void) + return -ETIMEDOUT; + } + +-static int ar933x_r1_get_wmac_revision(void) ++static int ar93xx_get_soc_revision(void) + { + return ath79_soc_rev; + } +@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi + ath79_wmac_data.is_clk_25mhz = true; + + if (ath79_soc_rev == 1) +- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; + + ath79_wmac_data.external_reset = ar933x_wmac_reset; + } +@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void) + ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; + } + ++static void qca953x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "qca953x_wmac"; ++ ++ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE; ++ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); ++ ++ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); ++ if (t & QCA953X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++ ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision; ++} ++ + static void qca955x_wmac_setup(void) + { + u32 t; +@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_ + ar933x_wmac_setup(); + else if (soc_is_ar934x()) + ar934x_wmac_setup(); ++ else if (soc_is_qca953x()) ++ qca953x_wmac_setup(); + else if (soc_is_qca955x()) + qca955x_wmac_setup(); + else +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -114,6 +114,8 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_AR9341: + case REV_ID_MAJOR_AR9342: + case REV_ID_MAJOR_AR9344: ++ case REV_ID_MAJOR_QCA9533: ++ case REV_ID_MAJOR_QCA9533_V2: + case REV_ID_MAJOR_QCA9556: + case REV_ID_MAJOR_QCA9558: + _prom_putchar = prom_putchar_ar71xx; +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func + soc_is_ar913x() || + soc_is_ar933x()) + reg = AR71XX_GPIO_REG_FUNC; +- else if (soc_is_ar934x()) ++ else if (soc_is_ar934x() || soc_is_qca953x()) + reg = AR934X_GPIO_REG_FUNC; + else + BUG(); +@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns + unsigned int reg; + u32 t, s; + +- BUG_ON(!soc_is_ar934x()); ++ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x()); + + if (gpio >= AR934X_GPIO_COUNT) + return; +@@ -224,6 +224,8 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = AR933X_GPIO_COUNT; + else if (soc_is_ar934x()) + ath79_gpio_count = AR934X_GPIO_COUNT; ++ else if (soc_is_qca953x()) ++ ath79_gpio_count = QCA953X_GPIO_COUNT; + else if (soc_is_qca955x()) + ath79_gpio_count = QCA955X_GPIO_COUNT; + else +@@ -231,7 +233,7 @@ void __init ath79_gpio_init(void) + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; +- if (soc_is_ar934x() || soc_is_qca955x()) { ++ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v + else if (soc_is_ar724x() || + soc_is_ar933x() || + soc_is_ar934x() || ++ soc_is_qca953x() || + soc_is_qca955x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else +@@ -153,6 +154,38 @@ static void ar934x_ip2_irq_init(void) + irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); + } + ++static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS); ++ ++ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) { ++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE); ++ generic_handle_irq(ATH79_IP2_IRQ(0)); ++ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) { ++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC); ++ generic_handle_irq(ATH79_IP2_IRQ(1)); ++ } else { ++ spurious_interrupt(); ++ } ++ ++ enable_irq(irq); ++} ++ ++static void qca953x_irq_init(void) ++{ ++ int i; ++ ++ for (i = ATH79_IP2_IRQ_BASE; ++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); ++} ++ + static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) + { + u32 status; +@@ -335,6 +368,12 @@ static void ar934x_ip3_handler(void) + do_IRQ(ATH79_CPU_IRQ(3)); + } + ++static void qca953x_ip3_handler(void) ++{ ++ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB); ++ do_IRQ(ATH79_CPU_IRQ(3)); ++} ++ + void __init arch_init_irq(void) + { + if (soc_is_ar71xx()) { +@@ -352,6 +391,9 @@ void __init arch_init_irq(void) + } else if (soc_is_ar934x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ar934x_ip3_handler; ++ } else if (soc_is_qca953x()) { ++ ath79_ip2_handler = ath79_default_ip2_handler; ++ ath79_ip3_handler = qca953x_ip3_handler; + } else if (soc_is_qca955x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ath79_default_ip3_handler; +@@ -364,6 +406,8 @@ void __init arch_init_irq(void) + + if (soc_is_ar934x()) + ar934x_ip2_irq_init(); ++ else if (soc_is_qca953x()) ++ qca953x_irq_init(); + else if (soc_is_qca955x()) + qca955x_irq_init(); + } +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type + u32 major; + u32 minor; + u32 rev = 0; ++ u32 ver = 1; + + id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); + major = id & REV_ID_MAJOR_MASK; +@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_QCA9533_V2: ++ ver = 2; ++ ath79_soc_rev = 2; ++ /* drop through */ ++ ++ case REV_ID_MAJOR_QCA9533: ++ ath79_soc = ATH79_SOC_QCA9533; ++ chip = "9533"; ++ rev = id & QCA953X_REV_ID_REVISION_MASK; ++ break; ++ + case REV_ID_MAJOR_QCA9556: + ath79_soc = ATH79_SOC_QCA9556; + chip = "9556"; +@@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type + panic("ath79: unknown SoC, id:0x%08x", id); + } + +- ath79_soc_rev = rev; ++ if (ver == 1) ++ ath79_soc_rev = rev; + +- if (soc_is_qca955x()) +- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", +- chip, rev); ++ if (soc_is_qca953x() || soc_is_qca955x()) ++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", ++ chip, ver, rev); + else + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + pr_info("SoC: %s\n", ath79_sys_type); +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -105,6 +105,21 @@ + #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) + #define AR934X_SRIF_SIZE 0x1000 + ++#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA953X_GMAC_SIZE 0x14 ++#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define QCA953X_WMAC_SIZE 0x20000 ++#define QCA953X_EHCI_BASE 0x1b000000 ++#define QCA953X_EHCI_SIZE 0x200 ++#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) ++#define QCA953X_SRIF_SIZE 0x1000 ++ ++#define QCA953X_PCI_CFG_BASE0 0x14000000 ++#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) ++#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) ++#define QCA953X_PCI_MEM_BASE0 0x10000000 ++#define QCA953X_PCI_MEM_SIZE 0x02000000 ++ + #define QCA955X_PCI_MEM_BASE0 0x10000000 + #define QCA955X_PCI_MEM_BASE1 0x12000000 + #define QCA955X_PCI_MEM_SIZE 0x02000000 +@@ -173,6 +188,12 @@ + #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 + #define AR934X_DDR_REG_FLUSH_WMAC 0xac + ++#define QCA953X_DDR_REG_FLUSH_GE0 0x9c ++#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 ++#define QCA953X_DDR_REG_FLUSH_USB 0xa4 ++#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 ++#define QCA953X_DDR_REG_FLUSH_WMAC 0xac ++ + /* + * PLL block + */ +@@ -279,6 +300,44 @@ + + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + ++#define QCA953X_PLL_CPU_CONFIG_REG 0x00 ++#define QCA953X_PLL_DDR_CONFIG_REG 0x04 ++#define QCA953X_PLL_CLK_CTRL_REG 0x08 ++#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 ++#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c ++#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 ++ ++#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 ++#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f ++#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 ++#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f ++#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 ++#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff ++#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 ++#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f ++#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) ++#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) ++#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 +@@ -355,6 +414,10 @@ + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + ++#define QCA953X_RESET_REG_RESET_MODULE 0x1c ++#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 ++#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac ++ + #define QCA955X_RESET_REG_RESET_MODULE 0x1c + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 + #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac +@@ -450,6 +513,27 @@ + #define AR934X_RESET_MBOX BIT(1) + #define AR934X_RESET_I2S BIT(0) + ++#define QCA953X_RESET_USB_EXT_PWR BIT(29) ++#define QCA953X_RESET_EXTERNAL BIT(28) ++#define QCA953X_RESET_RTC BIT(27) ++#define QCA953X_RESET_FULL_CHIP BIT(24) ++#define QCA953X_RESET_GE1_MDIO BIT(23) ++#define QCA953X_RESET_GE0_MDIO BIT(22) ++#define QCA953X_RESET_CPU_NMI BIT(21) ++#define QCA953X_RESET_CPU_COLD BIT(20) ++#define QCA953X_RESET_DDR BIT(16) ++#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define QCA953X_RESET_GE1_MAC BIT(13) ++#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) ++#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) ++#define QCA953X_RESET_GE0_MAC BIT(9) ++#define QCA953X_RESET_ETH_SWITCH BIT(8) ++#define QCA953X_RESET_PCIE_PHY BIT(7) ++#define QCA953X_RESET_PCIE BIT(6) ++#define QCA953X_RESET_USB_HOST BIT(5) ++#define QCA953X_RESET_USB_PHY BIT(4) ++#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) ++ + #define QCA955X_RESET_HOST BIT(31) + #define QCA955X_RESET_SLIC BIT(30) + #define QCA955X_RESET_HDMA BIT(29) +@@ -503,6 +587,13 @@ + #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) + #define AR934X_BOOTSTRAP_DDR1 BIT(0) + ++#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) ++#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) ++#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) ++#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) ++#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) ++#define QCA953X_BOOTSTRAP_DDR1 BIT(0) ++ + #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +@@ -523,6 +614,24 @@ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + ++#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) ++#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) ++#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) ++#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) ++#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) ++#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ ++ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ ++ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) ++ ++#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \ ++ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \ ++ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ ++ QCA953X_PCIE_WMAC_INT_PCIE_RC3) ++ + #define QCA955X_EXT_INT_WMAC_MISC BIT(0) + #define QCA955X_EXT_INT_WMAC_TX BIT(1) + #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +@@ -565,6 +674,8 @@ + #define REV_ID_MAJOR_AR9341 0x0120 + #define REV_ID_MAJOR_AR9342 0x1120 + #define REV_ID_MAJOR_AR9344 0x2120 ++#define REV_ID_MAJOR_QCA9533 0x0140 ++#define REV_ID_MAJOR_QCA9533_V2 0x0160 + #define REV_ID_MAJOR_QCA9556 0x0130 + #define REV_ID_MAJOR_QCA9558 0x1130 + +@@ -587,6 +698,8 @@ + + #define AR934X_REV_ID_REVISION_MASK 0xf + ++#define QCA953X_REV_ID_REVISION_MASK 0xf ++ + #define QCA955X_REV_ID_REVISION_MASK 0xf + + /* +@@ -634,12 +747,32 @@ + #define AR934X_GPIO_REG_OUT_FUNC5 0x40 + #define AR934X_GPIO_REG_FUNC 0x6c + ++#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c ++#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 ++#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 ++#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 ++#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c ++#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 ++#define QCA953X_GPIO_REG_FUNC 0x6c ++ ++#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 ++#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 ++#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 ++#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 ++#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 ++#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 ++ + #define AR71XX_GPIO_COUNT 16 + #define AR7240_GPIO_COUNT 18 + #define AR7241_GPIO_COUNT 20 + #define AR913X_GPIO_COUNT 22 + #define AR933X_GPIO_COUNT 30 + #define AR934X_GPIO_COUNT 23 ++#define QCA953X_GPIO_COUNT 18 + #define QCA955X_GPIO_COUNT 24 + + /* +@@ -663,6 +796,24 @@ + #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 + #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 + ++#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 ++#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 ++#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 ++ ++#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 ++#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 ++#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 ++ ++#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 ++#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f ++#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 ++#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff ++#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff ++ ++#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) ++#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 ++#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 ++ + #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) + #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) + #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +@@ -804,6 +955,16 @@ + #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 + + /* ++ * QCA953X GMAC Interface ++ */ ++#define QCA953X_GMAC_REG_ETH_CFG 0x00 ++ ++#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) ++#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) ++#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) ++#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) ++ ++/* + * QCA955X GMAC Interface + */ + +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -32,6 +32,7 @@ enum ath79_soc_type { + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, ++ ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, + }; +@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void) + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); + } + ++static inline int soc_is_qca9533(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9533; ++} ++ ++static inline int soc_is_qca953x(void) ++{ ++ return soc_is_qca9533(); ++} ++ + static inline int soc_is_qca9556(void) + { + return ath79_soc == ATH79_SOC_QCA9556; diff --git a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch new file mode 100644 index 0000000..ca92d0e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch @@ -0,0 +1,701 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -114,6 +114,12 @@ config SOC_QCA955X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA956X ++ select USB_ARCH_HAS_EHCI ++ select HW_HAS_PCI ++ select PCI_AR724X if PCI ++ def_bool n ++ + config ATH79_DEV_M25P80 + select ATH79_DEV_SPI + def_bool n +@@ -148,7 +154,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X) + def_bool n + + config ATH79_NVRAM +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v + clk_add_alias("uart", NULL, "ref", NULL); + } + ++static void __init qca956x_clocks_init(void) ++{ ++ unsigned long ref_rate; ++ unsigned long cpu_rate; ++ unsigned long ddr_rate; ++ unsigned long ahb_rate; ++ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40) ++ ref_rate = 40 * 1000 * 1000; ++ else ++ ref_rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK; ++ ++ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG); ++ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG1_NINT_MASK; ++ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK; ++ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) & ++ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK; ++ ++ cpu_pll = nint * ref_rate / ref_div; ++ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); ++ cpu_pll += (hfrac >> 13) * ref_rate / ref_div; ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK; ++ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG); ++ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG1_NINT_MASK; ++ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK; ++ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) & ++ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK; ++ ++ ddr_pll = nint * ref_rate / ref_div; ++ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); ++ ddr_pll += (hfrac >> 13) * ref_rate / ref_div; ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS) ++ cpu_rate = ref_rate; ++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL) ++ cpu_rate = ddr_pll / (postdiv + 1); ++ else ++ cpu_rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS) ++ ddr_rate = ref_rate; ++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL) ++ ddr_rate = cpu_pll / (postdiv + 1); ++ else ++ ddr_rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS) ++ ahb_rate = ref_rate; ++ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ahb_rate = ddr_pll / (postdiv + 1); ++ else ++ ahb_rate = cpu_pll / (postdiv + 1); ++ ++ ath79_add_sys_clkdev("ref", ref_rate); ++ ath79_add_sys_clkdev("cpu", cpu_rate); ++ ath79_add_sys_clkdev("ddr", ddr_rate); ++ ath79_add_sys_clkdev("ahb", ahb_rate); ++ ++ clk_add_alias("wdt", NULL, "ref", NULL); ++ clk_add_alias("uart", NULL, "ref", NULL); ++} ++ + void __init ath79_clocks_init(void) + { + if (soc_is_ar71xx()) +@@ -536,6 +630,8 @@ void __init ath79_clocks_init(void) + qca953x_clocks_init(); + else if (soc_is_qca955x()) + qca955x_clocks_init(); ++ else if (soc_is_qca956x()) ++ qca956x_clocks_init(); + else + BUG(); + } +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -77,6 +77,8 @@ void ath79_device_reset_set(u32 mask) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca956x()) ++ reg = QCA956X_RESET_REG_RESET_MODULE; + else + panic("Reset register not defined for this SOC"); + +@@ -107,6 +109,8 @@ void ath79_device_reset_clear(u32 mask) + reg = QCA953X_RESET_REG_RESET_MODULE; + else if (soc_is_qca955x()) + reg = QCA955X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca956x()) ++ reg = QCA956X_RESET_REG_RESET_MODULE; + else + panic("Reset register not defined for this SOC"); + +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -94,7 +94,8 @@ void __init ath79_register_uart(void) + soc_is_ar913x() || + soc_is_ar934x() || + soc_is_qca953x() || +- soc_is_qca955x()) { ++ soc_is_qca955x() || ++ soc_is_qca956x()) { + ath79_uart_data[0].uartclk = uart_clk_rate; + platform_device_register(&ath79_uart_device); + } else if (soc_is_ar933x()) { +--- a/arch/mips/ath79/dev-usb.c ++++ b/arch/mips/ath79/dev-usb.c +@@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi + &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); + } + ++static void __init qca956x_usb_setup(void) ++{ ++ ath79_usb_register("ehci-platform", 0, ++ QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE, ++ ATH79_IP3_IRQ(0), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); ++ ++ ath79_usb_register("ehci-platform", 1, ++ QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE, ++ ATH79_IP3_IRQ(1), ++ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2)); ++} ++ + void __init ath79_register_usb(void) + { + if (soc_is_ar71xx()) +@@ -314,6 +327,8 @@ void __init ath79_register_usb(void) + qca953x_usb_setup(); + else if (soc_is_qca955x()) + qca955x_usb_setup(); ++ else if (soc_is_qca9561()) ++ qca956x_usb_setup(); + else + BUG(); + } +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + ++static void qca956x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "qca956x_wmac"; ++ ++ ath79_wmac_resources[0].start = QCA956X_WMAC_BASE; ++ ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); ++ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1); ++ ++ t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP); ++ if (t & QCA956X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++} ++ + static bool __init + ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data) + { +@@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_ + qca953x_wmac_setup(); + else if (soc_is_qca955x()) + qca955x_wmac_setup(); ++ else if (soc_is_qca956x()) ++ qca956x_wmac_setup(); + else + BUG(); + +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -118,6 +118,8 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_QCA9533_V2: + case REV_ID_MAJOR_QCA9556: + case REV_ID_MAJOR_QCA9558: ++ case REV_ID_MAJOR_TP9343: ++ case REV_ID_MAJOR_QCA9561: + _prom_putchar = prom_putchar_ar71xx; + break; + +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func + soc_is_ar913x() || + soc_is_ar933x()) + reg = AR71XX_GPIO_REG_FUNC; +- else if (soc_is_ar934x() || soc_is_qca953x()) ++ else if (soc_is_ar934x() || ++ soc_is_qca953x() || soc_is_qca956x()) + reg = AR934X_GPIO_REG_FUNC; + else + BUG(); +@@ -228,12 +229,15 @@ void __init ath79_gpio_init(void) + ath79_gpio_count = QCA953X_GPIO_COUNT; + else if (soc_is_qca955x()) + ath79_gpio_count = QCA955X_GPIO_COUNT; ++ else if (soc_is_qca956x()) ++ ath79_gpio_count = QCA956X_GPIO_COUNT; + else + BUG(); + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; +- if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) { ++ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() || ++ soc_is_qca956x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v + soc_is_ar933x() || + soc_is_ar934x() || + soc_is_qca953x() || +- soc_is_qca955x()) ++ soc_is_qca955x() || ++ soc_is_qca956x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else + BUG(); +@@ -268,6 +269,97 @@ static void qca955x_irq_init(void) + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); + } + ++static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); ++ status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL; ++ ++ if (status == 0) { ++ spurious_interrupt(); ++ goto enable; ++ } ++ ++ if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP2_IRQ(0)); ++ } ++ ++ if (status & QCA956X_EXT_INT_WMAC_ALL) { ++ /* TODO: flsuh DDR? */ ++ generic_handle_irq(ATH79_IP2_IRQ(1)); ++ } ++ ++enable: ++ enable_irq(irq); ++} ++ ++static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc) ++{ ++ u32 status; ++ ++ disable_irq_nosync(irq); ++ ++ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS); ++ status &= QCA956X_EXT_INT_PCIE_RC2_ALL | ++ QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2; ++ ++ if (status == 0) { ++ spurious_interrupt(); ++ goto enable; ++ } ++ ++ if (status & QCA956X_EXT_INT_USB1) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(0)); ++ } ++ ++ if (status & QCA956X_EXT_INT_USB2) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(1)); ++ } ++ ++ if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) { ++ /* TODO: flush DDR? */ ++ generic_handle_irq(ATH79_IP3_IRQ(2)); ++ } ++ ++enable: ++ enable_irq(irq); ++} ++ ++static void qca956x_enable_timer_cb(void) { ++ u32 misc; ++ ++ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); ++ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK; ++ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); ++} ++ ++static void qca956x_irq_init(void) ++{ ++ int i; ++ ++ for (i = ATH79_IP2_IRQ_BASE; ++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); ++ ++ for (i = ATH79_IP3_IRQ_BASE; ++ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) ++ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ ++ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); ++ ++ /* QCA956x timer init workaround has to be applied right before setting ++ * up the clock. Else, there will be no jiffies */ ++ late_time_init = &qca956x_enable_timer_cb; ++} ++ + asmlinkage void plat_irq_dispatch(void) + { + unsigned long pending; +@@ -397,6 +489,9 @@ void __init arch_init_irq(void) + } else if (soc_is_qca955x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ath79_default_ip3_handler; ++ } else if (soc_is_qca956x()) { ++ ath79_ip2_handler = ath79_default_ip2_handler; ++ ath79_ip3_handler = ath79_default_ip3_handler; + } else { + BUG(); + } +@@ -410,4 +505,6 @@ void __init arch_init_irq(void) + qca953x_irq_init(); + else if (soc_is_qca955x()) + qca955x_irq_init(); ++ else if (soc_is_qca956x()) ++ qca956x_irq_init(); + } +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955 + }, + }; + ++static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = { ++ { ++ .bus = 0, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ }, ++ { ++ .bus = 1, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(1), ++ }, ++}; ++ + int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) + { + int irq = -1; +@@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct + } else if (soc_is_qca955x()) { + ath79_pci_irq_map = qca955x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); ++ } else if (soc_is_qca9561()) { ++ ath79_pci_irq_map = qca956x_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map); + } else { + pr_crit("pci %s: invalid irq map\n", + pci_name((struct pci_dev *) dev)); +@@ -303,6 +321,15 @@ int __init ath79_register_pci(void) + QCA955X_PCI_MEM_SIZE, + 1, + ATH79_IP3_IRQ(2)); ++ } else if (soc_is_qca9561()) { ++ pdev = ath79_register_pci_ar724x(0, ++ QCA956X_PCI_CFG_BASE1, ++ QCA956X_PCI_CTRL_BASE1, ++ QCA956X_PCI_CRP_BASE1, ++ QCA956X_PCI_MEM_BASE1, ++ QCA956X_PCI_MEM_SIZE, ++ 1, ++ ATH79_IP3_IRQ(2)); + } else { + /* No PCI support */ + return -ENODEV; +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type + rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_TP9343: ++ ath79_soc = ATH79_SOC_TP9343; ++ chip = "9343"; ++ rev = id & QCA956X_REV_ID_REVISION_MASK; ++ break; ++ ++ case REV_ID_MAJOR_QCA9561: ++ ath79_soc = ATH79_SOC_QCA9561; ++ chip = "9561"; ++ rev = id & QCA956X_REV_ID_REVISION_MASK; ++ break; ++ + default: + panic("ath79: unknown SoC, id:0x%08x", id); + } +@@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type + if (ver == 1) + ath79_soc_rev = rev; + +- if (soc_is_qca953x() || soc_is_qca955x()) ++ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561()) + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", + chip, ver, rev); ++ else if (soc_is_tp9343()) ++ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", ++ chip, rev); + else + sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); + pr_info("SoC: %s\n", ath79_sys_type); +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -143,6 +143,23 @@ + #define QCA955X_NFC_BASE 0x1b800200 + #define QCA955X_NFC_SIZE 0xb8 + ++#define QCA956X_PCI_MEM_BASE1 0x12000000 ++#define QCA956X_PCI_MEM_SIZE 0x02000000 ++#define QCA956X_PCI_CFG_BASE1 0x16000000 ++#define QCA956X_PCI_CFG_SIZE 0x1000 ++#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) ++#define QCA956X_PCI_CRP_SIZE 0x1000 ++#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) ++#define QCA956X_PCI_CTRL_SIZE 0x100 ++ ++#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define QCA956X_WMAC_SIZE 0x20000 ++#define QCA956X_EHCI0_BASE 0x1b000000 ++#define QCA956X_EHCI1_BASE 0x1b400000 ++#define QCA956X_EHCI_SIZE 0x200 ++#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA956X_GMAC_SIZE 0x64 ++ + #define AR9300_OTP_BASE 0x14000 + #define AR9300_OTP_STATUS 0x15f18 + #define AR9300_OTP_STATUS_TYPE 0x7 +@@ -375,6 +392,49 @@ + #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) + #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + ++#define QCA956X_PLL_CPU_CONFIG_REG 0x00 ++#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 ++#define QCA956X_PLL_DDR_CONFIG_REG 0x08 ++#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c ++#define QCA956X_PLL_CLK_CTRL_REG 0x10 ++ ++#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff ++#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 ++#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff ++ ++#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff ++#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 ++#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff ++ ++#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) ++#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) ++#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + /* + * USB_CONFIG block + */ +@@ -422,6 +482,11 @@ + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 + #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + ++#define QCA956X_RESET_REG_RESET_MODULE 0x1c ++#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 ++#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac ++ ++#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) + #define MISC_INT_ETHSW BIT(12) + #define MISC_INT_TIMER4 BIT(10) + #define MISC_INT_TIMER3 BIT(9) +@@ -596,6 +661,8 @@ + + #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + ++#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) ++ + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) + #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) + #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +@@ -663,6 +730,37 @@ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + ++#define QCA956X_EXT_INT_WMAC_MISC BIT(0) ++#define QCA956X_EXT_INT_WMAC_TX BIT(1) ++#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) ++#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) ++#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) ++#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) ++#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) ++#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) ++#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) ++#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) ++#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) ++#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) ++#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) ++#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) ++#define QCA956X_EXT_INT_USB1 BIT(24) ++#define QCA956X_EXT_INT_USB2 BIT(28) ++ ++#define QCA956X_EXT_INT_WMAC_ALL \ ++ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ ++ QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP) ++ ++#define QCA956X_EXT_INT_PCIE_RC1_ALL \ ++ (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \ ++ QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \ ++ QCA956X_EXT_INT_PCIE_RC1_INT3) ++ ++#define QCA956X_EXT_INT_PCIE_RC2_ALL \ ++ (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \ ++ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ ++ QCA956X_EXT_INT_PCIE_RC2_INT3) ++ + #define REV_ID_MAJOR_MASK 0xfff0 + #define REV_ID_MAJOR_AR71XX 0x00a0 + #define REV_ID_MAJOR_AR913X 0x00b0 +@@ -678,6 +776,8 @@ + #define REV_ID_MAJOR_QCA9533_V2 0x0160 + #define REV_ID_MAJOR_QCA9556 0x0130 + #define REV_ID_MAJOR_QCA9558 0x1130 ++#define REV_ID_MAJOR_TP9343 0x0150 ++#define REV_ID_MAJOR_QCA9561 0x1150 + + #define AR71XX_REV_ID_MINOR_MASK 0x3 + #define AR71XX_REV_ID_MINOR_AR7130 0x0 +@@ -702,6 +802,8 @@ + + #define QCA955X_REV_ID_REVISION_MASK 0xf + ++#define QCA956X_REV_ID_REVISION_MASK 0xf ++ + /* + * SPI block + */ +@@ -766,6 +868,19 @@ + #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 + #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + ++#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c ++#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 ++#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 ++#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 ++#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c ++#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 ++#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 ++#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 ++#define QCA956X_GPIO_REG_FUNC 0x6c ++ ++#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 ++#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 ++ + #define AR71XX_GPIO_COUNT 16 + #define AR7240_GPIO_COUNT 18 + #define AR7241_GPIO_COUNT 20 +@@ -774,6 +889,7 @@ + #define AR934X_GPIO_COUNT 23 + #define QCA953X_GPIO_COUNT 18 + #define QCA955X_GPIO_COUNT 24 ++#define QCA956X_GPIO_COUNT 23 + + /* + * SRIF block +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -35,6 +35,8 @@ enum ath79_soc_type { + ATH79_SOC_QCA9533, + ATH79_SOC_QCA9556, + ATH79_SOC_QCA9558, ++ ATH79_SOC_TP9343, ++ ATH79_SOC_QCA9561, + }; + + extern enum ath79_soc_type ath79_soc; +@@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void) + return soc_is_qca9556() || soc_is_qca9558(); + } + ++static inline int soc_is_tp9343(void) ++{ ++ return ath79_soc == ATH79_SOC_TP9343; ++} ++ ++static inline int soc_is_qca9561(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9561; ++} ++ ++static inline int soc_is_qca956x(void) ++{ ++ return soc_is_tp9343() || soc_is_qca9561(); ++} ++ + extern void __iomem *ath79_ddr_base; + extern void __iomem *ath79_gpio_base; + extern void __iomem *ath79_pll_base; diff --git a/target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch new file mode 100644 index 0000000..8c0cc95 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/630-MIPS-ath79-fix-chained-irq-disable.patch @@ -0,0 +1,100 @@ +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -26,6 +26,8 @@ + + static void (*ath79_ip2_handler)(void); + static void (*ath79_ip3_handler)(void); ++static struct irq_chip ip2_chip; ++static struct irq_chip ip3_chip; + + static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) + { +@@ -149,8 +151,7 @@ static void ar934x_ip2_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); + } +@@ -182,7 +183,7 @@ static void qca953x_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); + } +@@ -256,15 +257,13 @@ static void qca955x_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); + + for (i = ATH79_IP3_IRQ_BASE; + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, +- handle_level_irq); ++ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); + } +@@ -345,13 +344,13 @@ static void qca956x_irq_init(void) + + for (i = ATH79_IP2_IRQ_BASE; + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); + + for (i = ATH79_IP3_IRQ_BASE; + i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) +- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); ++ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); + + irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); + +@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void) + do_IRQ(ATH79_CPU_IRQ(3)); + } + ++static void ath79_ip2_disable(struct irq_data *data) ++{ ++ disable_irq(ATH79_CPU_IRQ(2)); ++} ++ ++static void ath79_ip2_enable(struct irq_data *data) ++{ ++ enable_irq(ATH79_CPU_IRQ(2)); ++} ++ ++static void ath79_ip3_disable(struct irq_data *data) ++{ ++ disable_irq(ATH79_CPU_IRQ(3)); ++} ++ ++static void ath79_ip3_enable(struct irq_data *data) ++{ ++ enable_irq(ATH79_CPU_IRQ(3)); ++} ++ + void __init arch_init_irq(void) + { ++ ip2_chip = dummy_irq_chip; ++ ip3_chip = dummy_irq_chip; ++ ip2_chip.irq_disable = ath79_ip2_disable; ++ ip2_chip.irq_enable = ath79_ip2_enable; ++ ip3_chip.irq_disable = ath79_ip3_disable; ++ ip3_chip.irq_enable = ath79_ip3_enable; ++ + if (soc_is_ar71xx()) { + ath79_ip2_handler = ar71xx_ip2_handler; + ath79_ip3_handler = ar71xx_ip3_handler; diff --git a/target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch b/target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch new file mode 100644 index 0000000..03b32b1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/631-MIPS-ath79-wmac-enable-set-led-pin.patch @@ -0,0 +1,24 @@ +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -398,6 +398,11 @@ void __init ath79_wmac_set_ext_lna_gpio( + ar934x_set_ext_lna_gpio(chain, gpio); + } + ++void __init ath79_wmac_set_led_pin(int gpio) ++{ ++ ath79_wmac_data.led_pin = gpio; ++} ++ + void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr) + { + if (soc_is_ar913x()) +--- a/arch/mips/ath79/dev-wmac.h ++++ b/arch/mips/ath79/dev-wmac.h +@@ -18,6 +18,7 @@ void ath79_wmac_disable_2ghz(void); + void ath79_wmac_disable_5ghz(void); + void ath79_wmac_set_tx_gain_buffalo(void); + void ath79_wmac_set_ext_lna_gpio(unsigned chain, int gpio); ++void ath79_wmac_set_led_pin(int gpio); + + bool ar93xx_wmac_read_mac_address(u8 *dest); + diff --git a/target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch b/target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch new file mode 100644 index 0000000..c628f1d --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/632-MIPS-ath79-gpio-enable-set-direction.patch @@ -0,0 +1,43 @@ +--- a/arch/mips/ath79/common.h ++++ b/arch/mips/ath79/common.h +@@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask + void ath79_gpio_function_disable(u32 mask); + void ath79_gpio_function_setup(u32 set, u32 clear); + void ath79_gpio_output_select(unsigned gpio, u8 val); ++int ath79_gpio_direction_select(unsigned gpio, bool oe); + void ath79_gpio_init(void); + + #endif /* __ATH79_COMMON_H */ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -130,6 +130,30 @@ static int ar934x_gpio_direction_output( + return 0; + } + ++int ath79_gpio_direction_select(unsigned gpio, bool oe) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ bool ieq_1 = (soc_is_ar934x() || ++ soc_is_qca953x()); ++ ++ if (gpio >= ath79_gpio_count) ++ return -1; ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ if ((ieq_1 && oe) || (!ieq_1 && !oe)) ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio), ++ base + AR71XX_GPIO_REG_OE); ++ else ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio), ++ base + AR71XX_GPIO_REG_OE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ ++ return 0; ++} ++ + static struct gpio_chip ath79_gpio_chip = { + .label = "ath79", + .get = ath79_gpio_get_value, diff --git a/target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch b/target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch new file mode 100644 index 0000000..e8183e7 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/633-MIPS-ath79-add-gpio-irq-support.patch @@ -0,0 +1,224 @@ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -20,9 +20,14 @@ + #include + #include + #include ++#include ++#include ++ ++#include + + #include + #include ++#include + #include "common.h" + + void __iomem *ath79_gpio_base; +@@ -31,6 +36,13 @@ EXPORT_SYMBOL_GPL(ath79_gpio_base); + static unsigned long ath79_gpio_count; + static DEFINE_SPINLOCK(ath79_gpio_lock); + ++/* ++ * gpio_both_edge is a bitmask of which gpio pins need to have ++ * the detect priority flipped from the interrupt handler to ++ * emulate IRQ_TYPE_EDGE_BOTH. ++ */ ++static unsigned long gpio_both_edge = 0; ++ + static void __ath79_gpio_set_value(unsigned gpio, int value) + { + void __iomem *base = ath79_gpio_base; +@@ -233,6 +245,132 @@ void __init ath79_gpio_output_select(uns + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } + ++static int ath79_gpio_irq_type(struct irq_data *d, unsigned type) ++{ ++ int offset = d->irq - ATH79_GPIO_IRQ_BASE; ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ unsigned long int_type; ++ unsigned long int_polarity; ++ unsigned long bit = (1 << offset); ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ int_type = __raw_readl(base + AR71XX_GPIO_REG_INT_TYPE); ++ int_polarity = __raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY); ++ ++ gpio_both_edge &= ~bit; ++ ++ switch (type) { ++ case IRQ_TYPE_EDGE_RISING: ++ int_type &= ~bit; ++ int_polarity |= bit; ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ int_type &= ~bit; ++ int_polarity &= ~bit; ++ break; ++ ++ case IRQ_TYPE_LEVEL_HIGH: ++ int_type |= bit; ++ int_polarity |= bit; ++ break; ++ ++ case IRQ_TYPE_LEVEL_LOW: ++ int_type |= bit; ++ int_polarity &= ~bit; ++ break; ++ ++ case IRQ_TYPE_EDGE_BOTH: ++ int_type |= bit; ++ /* set polarity based on current value */ ++ if (gpio_get_value(offset)) { ++ int_polarity &= ~bit; ++ } else { ++ int_polarity |= bit; ++ } ++ /* flip this gpio in the interrupt handler */ ++ gpio_both_edge |= bit; ++ break; ++ ++ default: ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ return -EINVAL; ++ } ++ ++ __raw_writel(int_type, base + AR71XX_GPIO_REG_INT_TYPE); ++ __raw_writel(int_polarity, base + AR71XX_GPIO_REG_INT_POLARITY); ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_MODE) | (1 << offset), ++ base + AR71XX_GPIO_REG_INT_MODE); ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset), ++ base + AR71XX_GPIO_REG_INT_ENABLE); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++ return 0; ++} ++ ++static void ath79_gpio_irq_enable(struct irq_data *d) ++{ ++ int offset = d->irq - ATH79_GPIO_IRQ_BASE; ++ void __iomem *base = ath79_gpio_base; ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) | (1 << offset), ++ base + AR71XX_GPIO_REG_INT_ENABLE); ++} ++ ++static void ath79_gpio_irq_disable(struct irq_data *d) ++{ ++ int offset = d->irq - ATH79_GPIO_IRQ_BASE; ++ void __iomem *base = ath79_gpio_base; ++ ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset), ++ base + AR71XX_GPIO_REG_INT_ENABLE); ++} ++ ++static struct irq_chip ath79_gpio_irqchip = { ++ .name = "GPIO", ++ .irq_enable = ath79_gpio_irq_enable, ++ .irq_disable = ath79_gpio_irq_disable, ++ .irq_set_type = ath79_gpio_irq_type, ++}; ++ ++static irqreturn_t ath79_gpio_irq(int irq, void *dev) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long stat = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING); ++ int bit_num; ++ ++ for_each_set_bit(bit_num, &stat, sizeof(stat) * BITS_PER_BYTE) { ++ unsigned long bit = BIT(bit_num); ++ ++ if (bit & gpio_both_edge) { ++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY) ^ bit, ++ base + AR71XX_GPIO_REG_INT_POLARITY); ++ } ++ ++ generic_handle_irq(ATH79_GPIO_IRQ(bit_num)); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init ath79_gpio_irq_init(struct gpio_chip *chip) ++{ ++ int irq; ++ int irq_base = ATH79_GPIO_IRQ_BASE; ++ ++ for (irq = irq_base; irq < irq_base + chip->ngpio; irq++) { ++ irq_set_chip_data(irq, chip); ++ irq_set_chip_and_handler(irq, &ath79_gpio_irqchip, handle_simple_irq); ++ irq_set_noprobe(irq); ++ } ++ ++ return 0; ++} ++ + void __init ath79_gpio_init(void) + { + int err; +@@ -269,6 +407,10 @@ void __init ath79_gpio_init(void) + err = gpiochip_add(&ath79_gpio_chip); + if (err) + panic("cannot add AR71xx GPIO chip, error=%d", err); ++ ++ ath79_gpio_irq_init(&ath79_gpio_chip); ++ ++ request_irq(ATH79_MISC_IRQ(2), ath79_gpio_irq, 0, "ath79-gpio", NULL); + } + + int gpio_get_value(unsigned gpio) +@@ -291,14 +433,22 @@ EXPORT_SYMBOL(gpio_set_value); + + int gpio_to_irq(unsigned gpio) + { +- /* FIXME */ +- return -EINVAL; ++ if (gpio > ath79_gpio_count) { ++ return -EINVAL; ++ } ++ ++ return ATH79_GPIO_IRQ_BASE + gpio; + } + EXPORT_SYMBOL(gpio_to_irq); + + int irq_to_gpio(unsigned irq) + { +- /* FIXME */ +- return -EINVAL; ++ unsigned gpio = irq - ATH79_GPIO_IRQ_BASE; ++ ++ if (gpio > ath79_gpio_count) { ++ return -EINVAL; ++ } ++ ++ return gpio; + } + EXPORT_SYMBOL(irq_to_gpio); +--- a/arch/mips/include/asm/mach-ath79/irq.h ++++ b/arch/mips/include/asm/mach-ath79/irq.h +@@ -10,7 +10,7 @@ + #define __ASM_MACH_ATH79_IRQ_H + + #define MIPS_CPU_IRQ_BASE 0 +-#define NR_IRQS 51 ++#define NR_IRQS 83 + + #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x)) + +@@ -30,6 +30,10 @@ + #define ATH79_IP3_IRQ_COUNT 3 + #define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x)) + ++#define ATH79_GPIO_IRQ_BASE (ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT) ++#define ATH79_GPIO_IRQ_COUNT 32 ++#define ATH79_GPIO_IRQ(_x) (ATH79_GPIO_IRQ_BASE + (_x)) ++ + #include_next + + #endif /* __ASM_MACH_ATH79_IRQ_H */ diff --git a/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch new file mode 100644 index 0000000..4583346 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -25,7 +25,7 @@ + #include "common.h" + + #define AR71XX_BASE_FREQ 40000000 +-#define AR724X_BASE_FREQ 5000000 ++#define AR724X_BASE_FREQ 40000000 + #define AR913X_BASE_FREQ 5000000 + + struct clk { +@@ -99,8 +99,8 @@ static void __init ar724x_clocks_init(vo + div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); + freq = div * ref_rate; + +- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); +- freq *= div; ++ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; ++ freq /= div; + + cpu_rate = freq; + diff --git a/target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch b/target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch new file mode 100644 index 0000000..17cabe1 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/700-MIPS-ath79-openwrt-machines.patch @@ -0,0 +1,1737 @@ +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -16,24 +16,210 @@ + + enum ath79_mach_type { + ATH79_MACH_GENERIC = 0, ++ ATH79_MACH_ALFA_AP96, /* ALFA Network AP96 board */ ++ ATH79_MACH_ALFA_NX, /* ALFA Network N2/N5 board */ ++ ATH79_MACH_ALL0258N, /* Allnet ALL0258N */ ++ ATH79_MACH_ALL0305, /* Allnet ALL0305 */ ++ ATH79_MACH_ALL0315N, /* Allnet ALL0315N */ ++ ATH79_MACH_ANTMINER_S1, /* Antminer S1 */ ++ ATH79_MACH_ANTMINER_S3, /* Antminer S3 */ ++ ATH79_MACH_AP113, /* Atheros AP113 reference board */ + ATH79_MACH_AP121, /* Atheros AP121 reference board */ + ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */ ++ ATH79_MACH_AP132, /* Atheros AP132 reference board */ + ATH79_MACH_AP135_020, /* Atheros AP135-020 reference board */ + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ ++ ATH79_MACH_AP143, /* Atheros AP143 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ ++ ATH79_MACH_AP83, /* Atheros AP83 */ ++ ATH79_MACH_AP96, /* Atheros AP96 */ ++ ATH79_MACH_ARCHER_C5, /* TP-LINK Archer C5 board */ ++ ATH79_MACH_ARCHER_C7, /* TP-LINK Archer C7 board */ ++ ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */ ++ ATH79_MACH_BHU_BXU2000N2_A1, /* BHU BXU2000n-2 A1 */ ++ ATH79_MACH_CAP4200AG, /* Senao CAP4200AG */ ++ ATH79_MACH_CARAMBOLA2, /* 8devices Carambola2 */ ++ ATH79_MACH_CF_E316N_V2, /* COMFAST CF-E316N v2 */ ++ ATH79_MACH_CPE510, /* TP-LINK CPE510 */ + ATH79_MACH_DB120, /* Atheros DB120 reference board */ + ATH79_MACH_PB44, /* Atheros PB44 reference board */ ++ ATH79_MACH_DGL_5500_A1, /* D-link DGL-5500 rev. A1 */ ++ ATH79_MACH_DHP_1565_A1, /* D-Link DHP-1565 rev. A1 */ ++ ATH79_MACH_DIR_505_A1, /* D-Link DIR-505 rev. A1 */ ++ ATH79_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ ++ ATH79_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ ++ ATH79_MACH_DIR_615_E1, /* D-Link DIR-615 rev. E1 */ ++ ATH79_MACH_DIR_615_E4, /* D-Link DIR-615 rev. E4 */ ++ ATH79_MACH_DIR_615_I1, /* D-Link DIR-615 rev. I1 */ ++ ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ ++ ATH79_MACH_DIR_825_C1, /* D-Link DIR-825 rev. C1 */ ++ ATH79_MACH_DIR_835_A1, /* D-Link DIR-835 rev. A1 */ ++ ATH79_MACH_DLAN_PRO_500_WP, /* devolo dLAN pro 500 Wireless+ */ ++ ATH79_MACH_DLAN_PRO_1200_AC, /* devolo dLAN pro 1200+ WiFi ac*/ ++ ATH79_MACH_DRAGINO2, /* Dragino Version 2 */ ++ ATH79_MACH_ESR900, /* EnGenius ESR900 */ ++ ATH79_MACH_EW_DORIN, /* embedded wireless Dorin Platform */ ++ ATH79_MACH_EW_DORIN_ROUTER, /* embedded wireless Dorin Router Platform */ ++ ATH79_MACH_EAP300V2, /* EnGenius EAP300 v2 */ ++ ATH79_MACH_EAP7660D, /* Senao EAP7660D */ ++ ATH79_MACH_EL_M150, /* EasyLink EL-M150 */ ++ ATH79_MACH_EL_MINI, /* EasyLink EL-MINI */ ++ ATH79_MACH_ESR1750, /* EnGenius ESR1750 */ ++ ATH79_MACH_EPG5000, /* EnGenius EPG5000 */ ++ ATH79_MACH_F9K1115V2, /* Belkin AC1750DB */ ++ ATH79_MACH_GL_INET, /* GL-CONNECT GL-INET */ ++ ATH79_MACH_GS_OOLITE, /* GS OOLITE V1.0 */ ++ ATH79_MACH_HIWIFI_HC6361, /* HiWiFi HC6361 */ ++ ATH79_MACH_JA76PF, /* jjPlus JA76PF */ ++ ATH79_MACH_JA76PF2, /* jjPlus JA76PF2 */ ++ ATH79_MACH_JWAP003, /* jjPlus JWAP003 */ ++ ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */ ++ ATH79_MACH_MR12, /* Cisco Meraki MR12 */ ++ ATH79_MACH_MR16, /* Cisco Meraki MR16 */ ++ ATH79_MACH_MR600V2, /* OpenMesh MR600v2 */ ++ ATH79_MACH_MR600, /* OpenMesh MR600 */ ++ ATH79_MACH_MR900, /* OpenMesh MR900 */ ++ ATH79_MACH_MR900v2, /* OpenMesh MR900v2 */ ++ ATH79_MACH_MYNET_N600, /* WD My Net N600 */ ++ ATH79_MACH_MYNET_N750, /* WD My Net N750 */ ++ ATH79_MACH_MYNET_REXT, /* WD My Net Wi-Fi Range Extender */ ++ ATH79_MACH_MZK_W04NU, /* Planex MZK-W04NU */ ++ ATH79_MACH_MZK_W300NH, /* Planex MZK-W300NH */ ++ ATH79_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ ++ ATH79_MACH_NBG6716, /* Zyxel NBG6716 */ ++ ATH79_MACH_OM2P_HSv2, /* OpenMesh OM2P-HSv2 */ ++ ATH79_MACH_OM2P_HS, /* OpenMesh OM2P-HS */ ++ ATH79_MACH_OM2P_LC, /* OpenMesh OM2P-LC */ ++ ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */ ++ ATH79_MACH_OM2P, /* OpenMesh OM2P */ ++ ATH79_MACH_OM5P_AN, /* OpenMesh OM5P-AN */ ++ ATH79_MACH_OM5P, /* OpenMesh OM5P */ ++ ATH79_MACH_ONION_OMEGA, /* ONION OMEGA */ ++ ATH79_MACH_PB42, /* Atheros PB42 */ ++ ATH79_MACH_PB92, /* Atheros PB92 */ ++ ATH79_MACH_QIHOO_C301, /* Qihoo 360 C301 */ ++ ATH79_MACH_R6100, /* NETGEAR R6100 */ ++ ATH79_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ ++ ATH79_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ ++ ATH79_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ ++ ATH79_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ ++ ATH79_MACH_RB_435G, /* MikroTik RouterBOARD 435G */ ++ ATH79_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ ++ ATH79_MACH_RB_450, /* MikroTik RouterBOARD 450 */ ++ ATH79_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ ++ ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */ ++ ATH79_MACH_RB_711GR100, /* Mikrotik RouterBOARD 911/912 boards */ ++ ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */ ++ ATH79_MACH_RB_750G_R3, /* MikroTik RouterBOARD 750GL */ ++ ATH79_MACH_RB_751, /* MikroTik RouterBOARD 751 */ ++ ATH79_MACH_RB_751G, /* Mikrotik RouterBOARD 751G */ ++ ATH79_MACH_RB_922GS, /* Mikrotik RouterBOARD 911/922GS boards */ ++ ATH79_MACH_RB_951G, /* Mikrotik RouterBOARD 951G */ ++ ATH79_MACH_RB_951U, /* Mikrotik RouterBOARD 951Ui-2HnD */ ++ ATH79_MACH_RB_2011G, /* Mikrotik RouterBOARD 2011UAS-2HnD */ ++ ATH79_MACH_RB_2011L, /* Mikrotik RouterBOARD 2011L */ ++ ATH79_MACH_RB_2011US, /* Mikrotik RouterBOARD 2011UAS */ ++ ATH79_MACH_RB_2011R5, /* Mikrotik RouterBOARD 2011UiAS(-2Hnd) */ ++ ATH79_MACH_RB_SXTLITE2ND, /* Mikrotik RouterBOARD SXT Lite 2nD */ ++ ATH79_MACH_RB_SXTLITE5ND, /* Mikrotik RouterBOARD SXT Lite 5nD */ ++ ATH79_MACH_RW2458N, /* Redwave RW2458N */ ++ ATH79_MACH_SMART_300, /* NC-LINK SMART-300 */ ++ ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ ++ ATH79_MACH_TEW_673GRU, /* TRENDnet TEW-673GRU */ ++ ATH79_MACH_TEW_712BR, /* TRENDnet TEW-712BR */ ++ ATH79_MACH_TEW_732BR, /* TRENDnet TEW-732BR */ ++ ATH79_MACH_MC_MAC1200R, /* MERCURY MAC1200R*/ ++ ATH79_MACH_TL_MR10U, /* TP-LINK TL-MR10U */ ++ ATH79_MACH_TL_MR11U, /* TP-LINK TL-MR11U */ ++ ATH79_MACH_TL_MR13U, /* TP-LINK TL-MR13U */ ++ ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */ ++ ATH79_MACH_TL_MR3040, /* TP-LINK TL-MR3040 */ ++ ATH79_MACH_TL_MR3040_V2, /* TP-LINK TL-MR3040 v2 */ ++ ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */ ++ ATH79_MACH_TL_MR3220_V2, /* TP-LINK TL-MR3220 v2 */ ++ ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */ ++ ATH79_MACH_TL_MR3420_V2, /* TP-LINK TL-MR3420 v2 */ ++ ATH79_MACH_TL_WA701ND_V2, /* TP-LINK TL-WA701ND v2 */ ++ ATH79_MACH_TL_WA750RE, /* TP-LINK TL-WA750RE */ ++ ATH79_MACH_TL_WA7210N_V2, /* TP-LINK TL-WA7210N v2 */ ++ ATH79_MACH_TL_WA7510N_V1, /* TP-LINK TL-WA7510N v1*/ ++ ATH79_MACH_TL_WA850RE, /* TP-LINK TL-WA850RE */ ++ ATH79_MACH_TL_WA860RE, /* TP-LINK TL-WA860RE */ ++ ATH79_MACH_TL_WA801ND_V2, /* TP-LINK TL-WA801ND v2 */ ++ ATH79_MACH_TL_WA830RE_V2, /* TP-LINK TL-WA830RE v2 */ ++ ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */ ++ ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */ ++ ATH79_MACH_TL_WA901ND_V3, /* TP-LINK TL-WA901ND v3 */ ++ ATH79_MACH_TL_WDR3500, /* TP-LINK TL-WDR3500 */ ++ ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */ ++ ATH79_MACH_TL_WDR4900_V2, /* TP-LINK TL-WDR4900 v2 */ ++ ATH79_MACH_TL_WR1041N_V2, /* TP-LINK TL-WR1041N v2 */ ++ ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1043ND */ ++ ATH79_MACH_TL_WR1043ND_V2, /* TP-LINK TL-WR1043ND v2 */ ++ ATH79_MACH_TL_WR2543N, /* TP-LINK TL-WR2543N/ND */ ++ ATH79_MACH_TL_WR703N, /* TP-LINK TL-WR703N */ ++ ATH79_MACH_TL_WR710N, /* TP-LINK TL-WR710N */ ++ ATH79_MACH_TL_WR720N_V3, /* TP-LINK TL-WR720N v3/v4 */ ++ ATH79_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ ++ ATH79_MACH_TL_WR741ND_V4, /* TP-LINK TL-WR741ND v4*/ ++ ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ ++ ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */ ++ ATH79_MACH_TL_WR841N_V8, /* TP-LINK TL-WR841N/ND v8 */ ++ ATH79_MACH_TL_WR841N_V9, /* TP-LINK TL-WR841N/ND v9 */ ++ ATH79_MACH_TL_WR842N_V2, /* TP-LINK TL-WR842N/ND v2 */ ++ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ ++ ATH79_MACH_TL_WR941ND_V5, /* TP-LINK TL-WR941ND v5 */ ++ ATH79_MACH_TUBE2H, /* Alfa Network Tube2H */ ++ ATH79_MACH_UBNT_AIRGW, /* Ubiquiti AirGateway */ ++ ATH79_MACH_UBNT_AIRGWP, /* Ubiquiti AirGateway Pro */ + ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */ + ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ ++ ATH79_MACH_UBNT_LOCO_M_XW, /* Ubiquiti Loco M XW */ ++ ATH79_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ ++ ATH79_MACH_UBNT_LSX, /* Ubiquiti LSX */ + ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ ++ ATH79_MACH_UBNT_NANO_M_XW, /* Ubiquiti NanoStation M XW */ + ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ + ATH79_MACH_UBNT_ROCKET_M_XW, /* Ubiquiti Rocket M XW*/ + ATH79_MACH_UBNT_ROCKET_M_TI, /* Ubiquiti Rocket M TI*/ ++ ATH79_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ ++ ATH79_MACH_UBNT_RS, /* Ubiquiti RouterStation */ + ATH79_MACH_UBNT_UAP_PRO, /* Ubiquiti UniFi AP Pro */ + ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */ + ATH79_MACH_UBNT_UNIFI_OUTDOOR, /* Ubiquiti UnifiAP Outdoor */ ++ ATH79_MACH_UBNT_UNIFI_OUTDOOR_PLUS, /* Ubiquiti UnifiAP Outdoor+ */ + ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */ ++ ATH79_MACH_WEIO, /* WeIO board */ ++ ATH79_MACH_WHR_G301N, /* Buffalo WHR-G301N */ ++ ATH79_MACH_WHR_HP_G300N, /* Buffalo WHR-HP-G300N */ ++ ATH79_MACH_WHR_HP_GN, /* Buffalo WHR-HP-GN */ ++ ATH79_MACH_WLAE_AG300N, /* Buffalo WLAE-AG300N */ ++ ATH79_MACH_WLR8100, /* SITECOM WLR-8100 */ ++ ATH79_MACH_WNDAP360, /* NETGEAR WNDAP360 */ ++ ATH79_MACH_WNDR3700, /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */ ++ ATH79_MACH_WNDR3700_V4, /* NETGEAR WNDR3700v4 */ ++ ATH79_MACH_WNDR4300, /* NETGEAR WNDR4300 */ ++ ATH79_MACH_WNR2000, /* NETGEAR WNR2000 */ ++ ATH79_MACH_WNR2000_V3, /* NETGEAR WNR2000 v3 */ ++ ATH79_MACH_WNR2000_V4, /* NETGEAR WNR2000 v4 */ ++ ATH79_MACH_WNR2200, /* NETGEAR WNR2200 */ ++ ATH79_MACH_WNR612_V2, /* NETGEAR WNR612 v2 */ ++ ATH79_MACH_WNR1000_V2, /* NETGEAR WNR1000 v2 */ ++ ATH79_MACH_WP543, /* Compex WP543 */ ++ ATH79_MACH_WPE72, /* Compex WPE72 */ ++ ATH79_MACH_WPJ344, /* Compex WPJ344 */ ++ ATH79_MACH_WPJ531, /* Compex WPJ531 */ ++ ATH79_MACH_WPJ558, /* Compex WPJ558 */ ++ ATH79_MACH_WRT160NL, /* Linksys WRT160NL */ ++ ATH79_MACH_WRT400N, /* Linksys WRT400N */ ++ ATH79_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */ ++ ATH79_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ ++ ATH79_MACH_WZR_HP_G300NH2, /* Buffalo WZR-HP-G300NH2 */ ++ ATH79_MACH_WZR_HP_G450H, /* Buffalo WZR-HP-G450H */ ++ ATH79_MACH_WZR_450HP2, /* Buffalo WZR-450HP2 */ ++ ATH79_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */ ++ ATH79_MACH_ZCN_1523H_5, /* Zcomax ZCN-1523H-5-xx */ + }; + + #endif /* _ATH79_MACHTYPE_H */ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -2,6 +2,90 @@ if ATH79 + + menu "Atheros AR71XX/AR724X/AR913X machine selection" + ++config ATH79_MACH_ALFA_AP96 ++ bool "ALFA Network AP96 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_HORNET_UB ++ bool "ALFA Network Hornet-UB board support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ALFA_NX ++ bool "ALFA Network N2/N5 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TUBE2H ++ bool "ALFA Network Tube2H board support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ALL0258N ++ bool "Allnet ALL0258N support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_ALL0315N ++ bool "Allnet ALL0315N support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_ANTMINER_S1 ++ bool "Bitmain Antminer S1 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ANTMINER_S3 ++ bool "Bitmain Antminer S3 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_AP113 ++ bool "Atheros AP113 board support" ++ select SOC_AR724X ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_PB9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_ETH ++ + config ATH79_MACH_AP121 + bool "Atheros AP121 reference board" + select SOC_AR933X +@@ -11,62 +95,1107 @@ config ATH79_MACH_AP121 + select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC +- help +- Say 'Y' here if you want your kernel to support the +- Atheros AP121 reference board. ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP121 reference board. ++ ++config ATH79_MACH_AP132 ++ bool "Atheros AP132 reference board" ++ select SOC_QCA955X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP132 reference boards. ++ ++config ATH79_MACH_AP136 ++ bool "Atheros AP136/AP135 reference board" ++ select SOC_QCA955X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP136 or AP135 reference boards. ++ ++config ATH79_MACH_AP143 ++ bool "Atheros AP143 reference board" ++ select SOC_QCA953X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_ETH ++ select ATH79_DEV_M25P80 ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP143 reference board. ++ ++config ATH79_MACH_AP81 ++ bool "Atheros AP81 reference board" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros AP81 reference board. ++ ++config ATH79_MACH_AP83 ++ bool "Atheros AP83 board support" ++ select SOC_AR913X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_AP96 ++ bool "Atheros AP96 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DB120 ++ bool "Atheros DB120 reference board" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros DB120 reference board. ++ ++config ATH79_MACH_PB42 ++ bool "Atheros PB42 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_PB44 ++ bool "Atheros PB44 reference board" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_USB ++ help ++ Say 'Y' here if you want your kernel to support the ++ Atheros PB44 reference board. ++ ++config ATH79_MACH_PB92 ++ bool "Atheros PB92 board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_PB9X_PCI if PCI ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_AW_NR580 ++ bool "AzureWave AW-NR580 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_F9K1115V2 ++ bool "Belkin AC1750DB board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EPG5000 ++ bool "EnGenius EPG5000 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_ESR1750 ++ bool "EnGenius ESR1750 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WHR_HP_G300N ++ bool "Buffalo WHR-HP-G300N board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WLAE_AG300N ++ bool "Buffalo WLAE-AG300N board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WLR8100 ++ bool "Sitecom WLR-8100 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WZR_HP_AG300H ++ bool "Buffalo WZR-HP-AG300H board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WZR_HP_G300NH ++ bool "Buffalo WZR-HP-G300NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select RTL8366_SMI ++ ++config ATH79_MACH_WZR_HP_G300NH2 ++ bool "Buffalo WZR-HP-G300NH2 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WZR_HP_G450H ++ bool "Buffalo WZR-HP-G450H board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WZR_450HP2 ++ bool "Buffalo WZR-450HP2 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WP543 ++ bool "Compex WP543/WPJ543 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select MYLOADER ++ ++config ATH79_MACH_WPE72 ++ bool "Compex WPE72/WPE72NX board support" ++ select SOC_AR724X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select MYLOADER ++ ++config ATH79_MACH_WPJ344 ++ bool "Compex WPJ344 board support" ++ select SOC_AS934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WPJ531 ++ bool "Compex WPJ531 board support" ++ select SOC_QCA953X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WPJ558 ++ bool "Compex WPJ558 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_DGL_5500_A1 ++ bool "D-Link DGL-5500 A1 support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DHP_1565_A1 ++ bool "D-Link DHP-1565 rev. A1 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_DIR_505_A1 ++ bool "D-Link DIR-505-A1 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_600_A1 ++ bool "D-Link DIR-600 A1/DIR-615 E1/DIR-615 E4 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_615_C1 ++ bool "D-Link DIR-615 rev. C1 support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_615_I1 ++ bool "D-Link DIR-615 rev. I1 support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_DIR_825_B1 ++ bool "D-Link DIR-825 rev. B1 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DIR_825_C1 ++ bool "D-Link DIR-825 rev. C1/DIR-835 rev. A1 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_DLAN_PRO_500_WP ++ bool "devolo dLAN pro 500 Wireless+ support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DLAN_PRO_1200_AC ++ bool "devolo dLAN pro 1200+ WiFi ac support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_DRAGINO2 ++ bool "DRAGINO V2 support" ++ select SOC_AR933X ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_ETH ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_ESR900 ++ bool "EnGenius ESR900 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EW_DORIN ++ bool "embedded wireless Dorin Platform support" ++ select SOC_AR933X ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_ETH ++ help ++ Say 'Y' here if you want your kernel to support the ++ Dorin Platform from www.80211.de . ++ ++config ATH79_MACH_EL_M150 ++ bool "EasyLink EL-M150 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EL_MINI ++ bool "EasyLink EL-MINI support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_GL_INET ++ bool "GL-INET support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EAP300V2 ++ bool "EnGenius EAP300 v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_GS_OOLITE ++ bool "GS Oolite V1 support" ++ select SOC_AR933X ++ select ARH79_DEV_ETH ++ select ARH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_HIWIFI_HC6361 ++ bool "HiWiFi HC6361 board support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_JA76PF ++ bool "jjPlus JA76PF board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_JWAP003 ++ bool "jjPlus JWAP003 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WRT160NL ++ bool "Linksys WRT160NL board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_WRT400N ++ bool "Linksys WRT400N board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_R6100 ++ bool "NETGEAR R6100 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MC_MAC1200R ++ bool "MERCURY MAC1200R board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_RB4XX ++ bool "MikroTik RouterBOARD 4xx series support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_RB750 ++ bool "MikroTik RouterBOARD 750 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_RB91X ++ bool "MikroTik RouterBOARD 91X support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_SPI ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_RB922 ++ bool "MikroTik RouterBOARD 922 support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ select RLE_DECOMPRESS ++ ++config ATH79_MACH_RB95X ++ bool "MikroTik RouterBOARD 95X support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_NFC ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_RB2011 ++ bool "MikroTik RouterBOARD 2011 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_RBSXTLITE ++ bool "MikroTik RouterBOARD SXT Lite" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_NFC ++ select ATH79_DEV_WMAC ++ select ATH79_ROUTERBOOT ++ ++config ATH79_MACH_SMART_300 ++ bool "NC-LINK SMART-300 board support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WNDAP360 ++ bool "NETGEAR WNDAP360 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_WNDR3700 ++ bool "NETGEAR WNDR3700 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WNDR4300 ++ bool "NETGEAR WNDR3700v4/WNDR4300 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WNR2000 ++ bool "NETGEAR WNR2000 board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_WNR2000_V3 ++ bool "NETGEAR WNR2000 V3/WNR612 v2/WNR1000 v2 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++ config ATH79_MACH_WNR2200 ++ bool "NETGEAR WNR2200 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_WNR2000_V4 ++ bool "NETGEAR WNR2000 V4" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_OM2P ++ bool "OpenMesh OM2P board support" ++ select SOC_AR724X ++ select SOC_AR933X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_OM5P ++ bool "OpenMesh OM5P board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_ONION_OMEGA ++ bool "ONION OMEGA support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MR12 ++ bool "Meraki MR12 board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MR16 ++ bool "Meraki MR16 board support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MR600 ++ bool "OpenMesh MR600 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MZK_W04NU ++ bool "Planex MZK-W04NU board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MZK_W300NH ++ bool "Planex MZK-W300NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_RW2458N ++ bool "Redwave RW2458N board support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_CAP4200AG ++ bool "Senao CAP4200AG support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MR900 ++ bool "OpenMesh MR900 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_EAP7660D ++ bool "Senao EAP7660D support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_ARCHER_C7 ++ bool "TP-LINK Archer C5/C7/TL-WDR4900 v2 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_CPE510 ++ bool "TP-LINK CPE510 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR11U ++ bool "TP-LINK TL-MR11U/TL-MR3040 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR13U ++ bool "TP-LINK TL-MR13U support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR3020 ++ bool "TP-LINK TL-MR3020 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_MR3X20 ++ bool "TP-LINK TL-MR3220/3420 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_TL_WAX50RE ++ bool "TP-LINK TL-WA750/850RE support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WA701ND_V2 ++ bool "TP-LINK TL-WA701ND v2 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC + +-config ATH79_MACH_AP136 +- bool "Atheros AP136/AP135 reference board" +- select SOC_QCA955X ++config ATH79_MACH_TL_WA7210N_V2 ++ bool "TP-LINK TL-WA7210N v2 support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WA830RE_V2 ++ bool "TP-LINK TL-WA830RE v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_NFC +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC +- help +- Say 'Y' here if you want your kernel to support the +- Atheros AP136 or AP135 reference boards. + +-config ATH79_MACH_AP81 +- bool "Atheros AP81 reference board" ++config ATH79_MACH_TL_WA901ND ++ bool "TP-LINK TL-WA901ND/TL-WA7510N support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WA901ND_V2 ++ bool "TP-LINK TL-WA901ND v2 support" + select SOC_AR913X + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WDR3500 ++ bool "TP-LINK TL-WDR3500 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB + select ATH79_DEV_WMAC +- help +- Say 'Y' here if you want your kernel to support the +- Atheros AP81 reference board. + +-config ATH79_MACH_DB120 +- bool "Atheros DB120 reference board" ++config ATH79_MACH_TL_WDR4300 ++ bool "TP-LINK TL-WDR3600/4300/4310 board support" + select SOC_AR934X + select ATH79_DEV_AP9X_PCI if PCI + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 +- select ATH79_DEV_NFC + select ATH79_DEV_USB + select ATH79_DEV_WMAC +- help +- Say 'Y' here if you want your kernel to support the +- Atheros DB120 reference board. + +-config ATH79_MACH_PB44 +- bool "Atheros PB44 reference board" ++config ATH79_MACH_TL_WR703N ++ bool "TP-LINK TL-WR703N/TL-WR710N/TL-MR10U support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR720N_V3 ++ bool "TP-LINK TL-WR720N v3/v4 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR741ND ++ bool "TP-LINK TL-WR741ND support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WR741ND_V4 ++ bool "TP-LINK TL-WR741ND v4/TL-MR3220 v2 support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR841N_V1 ++ bool "TP-LINK TL-WR841N v1 support" + select SOC_AR71XX ++ select ATH79_DEV_DSA + select ATH79_DEV_ETH + select ATH79_DEV_GPIO_BUTTONS + select ATH79_DEV_LEDS_GPIO +- select ATH79_DEV_SPI ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_TL_WR841N_V8 ++ bool "TP-LINK TL-WR841N/ND v8/TL-MR3420 v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR841N_V9 ++ bool "TP-LINK TL-WR841N/ND v9 support" ++ select SOC_QCA953X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR941ND ++ bool "TP-LINK TL-WR941ND support" ++ select SOC_AR913X ++ select ATH79_DEV_DSA ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR1041N_V2 ++ bool "TP-LINK TL-WR1041N v2 support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR1043ND ++ bool "TP-LINK TL-WR1043ND support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR1043ND_V2 ++ bool "TP-LINK TL-WR1043ND v2 support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_TL_WR2543N ++ bool "TP-LINK TL-WR2543N/ND support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ ++config ATH79_MACH_TEW_632BRP ++ bool "TRENDnet TEW-632BRP support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_TEW_673GRU ++ bool "TRENDnet TEW-673GRU support" ++ select SOC_AR71XX ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_NVRAM ++ ++config ATH79_MACH_TEW_712BR ++ bool "TRENDnet TEW-712BR support" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_TEW_732BR ++ bool "TRENDnet TEW-732BR support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_UBNT ++ bool "Ubiquiti AR71xx based boards support" ++ select SOC_AR71XX ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 + select ATH79_DEV_USB +- help +- Say 'Y' here if you want your kernel to support the +- Atheros PB44 reference board. + + config ATH79_MACH_UBNT_XM + bool "Ubiquiti Networks XM/UniFi boards" +@@ -83,6 +1212,116 @@ config ATH79_MACH_UBNT_XM + Say 'Y' here if you want your kernel to support the + Ubiquiti Networks XM (rev 1.0) board. + ++config ATH79_MACH_WEIO ++ bool "WeIO board" ++ select SOC_AR933X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_MYNET_N600 ++ bool "WD My Net N600 board support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_MYNET_N750 ++ bool "WD My Net N750 board support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_MYNET_REXT ++ bool "WD My Net Wi-Fi Range Extender board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_NVRAM ++ ++config ATH79_MACH_ZCN_1523H ++ bool "Zcomax ZCN-1523H support" ++ select SOC_AR724X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ ++config ATH79_MACH_NBG460N ++ bool "Zyxel NBG460N/550N/550NH board support" ++ select SOC_AR913X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_NBG6716 ++ bool "Zyxel NBG6716 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_NFC ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_CARAMBOLA2 ++ bool "8devices Carambola2 board" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_CF_E316N_V2 ++ bool "COMFAST CF-E316N v2 board" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_BHU_BXU2000N2_A ++ bool "BHU BXU2000n-2 rev. A support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ ++config ATH79_MACH_QIHOO_C301 ++ bool "Qihoo 360 C301 board support" ++ select SOC_AR934X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_USB ++ select ATH79_NVRAM ++ + endmenu + + config SOC_AR71XX +@@ -134,7 +1373,10 @@ config ATH79_DEV_DSA + config ATH79_DEV_ETH + def_bool n + +-config PCI_AR724X ++config ATH79_DEV_DSA ++ def_bool n ++ ++config ATH79_DEV_ETH + def_bool n + + config ATH79_DEV_GPIO_BUTTONS +@@ -164,6 +1406,11 @@ config ATH79_PCI_ATH9K_FIXUP + def_bool n + + config ATH79_ROUTERBOOT ++ select RLE_DECOMPRESS ++ select LZO_DECOMPRESS ++ def_bool n ++ ++config PCI_AR724X + def_bool n + + endif +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -38,9 +38,135 @@ obj-$(CONFIG_ATH79_ROUTERBOOT) += route + # + # Machines + # ++obj-$(CONFIG_ATH79_MACH_ALFA_AP96) += mach-alfa-ap96.o ++obj-$(CONFIG_ATH79_MACH_ALFA_NX) += mach-alfa-nx.o ++obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o ++obj-$(CONFIG_ATH79_MACH_ALL0315N) += mach-all0315n.o ++obj-$(CONFIG_ATH79_MACH_ANTMINER_S1)+= mach-antminer-s1.o ++obj-$(CONFIG_ATH79_MACH_ANTMINER_S3)+= mach-antminer-s3.o ++obj-$(CONFIG_ATH79_MACH_AP113) += mach-ap113.o + obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o ++obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o + obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o ++obj-$(CONFIG_ATH79_MACH_AP143) += mach-ap143.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o ++obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o ++obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o ++obj-$(CONFIG_ATH79_MACH_ARCHER_C7) += mach-archer-c7.o ++obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o ++obj-$(CONFIG_ATH79_MACH_BHU_BXU2000N2_A)+= mach-bhu-bxu2000n2-a.o ++obj-$(CONFIG_ATH79_MACH_CAP4200AG) += mach-cap4200ag.o ++obj-$(CONFIG_ATH79_MACH_CF_E316N_V2) += mach-cf-e316n-v2.o ++obj-$(CONFIG_ATH79_MACH_CPE510) += mach-cpe510.o + obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o ++obj-$(CONFIG_ATH79_MACH_DLAN_PRO_500_WP) += mach-dlan-pro-500-wp.o ++obj-$(CONFIG_ATH79_MACH_DLAN_PRO_1200_AC) += mach-dlan-pro-1200-ac.o ++obj-$(CONFIG_ATH79_MACH_DGL_5500_A1) += mach-dgl-5500-a1.o ++obj-$(CONFIG_ATH79_MACH_DHP_1565_A1) += mach-dhp-1565-a1.o ++obj-$(CONFIG_ATH79_MACH_DIR_505_A1) += mach-dir-505-a1.o ++obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o ++obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o ++obj-$(CONFIG_ATH79_MACH_DIR_615_I1) += mach-dir-615-i1.o ++obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o ++obj-$(CONFIG_ATH79_MACH_DIR_825_C1) += mach-dir-825-c1.o ++obj-$(CONFIG_ATH79_MACH_DRAGINO2) += mach-dragino2.o ++obj-$(CONFIG_ATH79_MACH_ESR900) += mach-esr900.o ++obj-$(CONFIG_ATH79_MACH_EW_DORIN) += mach-ew-dorin.o ++obj-$(CONFIG_ATH79_MACH_EAP300V2) += mach-eap300v2.o ++obj-$(CONFIG_ATH79_MACH_EAP7660D) += mach-eap7660d.o ++obj-$(CONFIG_ATH79_MACH_EL_M150) += mach-el-m150.o ++obj-$(CONFIG_ATH79_MACH_EL_MINI) += mach-el-mini.o ++obj-$(CONFIG_ATH79_MACH_EPG5000) += mach-epg5000.o ++obj-$(CONFIG_ATH79_MACH_ESR1750) += mach-esr1750.o ++obj-$(CONFIG_ATH79_MACH_F9K1115V2) += mach-f9k1115v2.o ++obj-$(CONFIG_ATH79_MACH_GL_INET) += mach-gl-inet.o ++obj-$(CONFIG_ATH79_MACH_GS_OOLITE) += mach-gs-oolite.o ++obj-$(CONFIG_ATH79_MACH_HIWIFI_HC6361) += mach-hiwifi-hc6361.o ++obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o ++obj-$(CONFIG_ATH79_MACH_JWAP003) += mach-jwap003.o ++obj-$(CONFIG_ATH79_MACH_HORNET_UB) += mach-hornet-ub.o ++obj-$(CONFIG_ATH79_MACH_MC_MAC1200R) += mach-mc-mac1200r.o ++obj-$(CONFIG_ATH79_MACH_MR12) += mach-mr12.o ++obj-$(CONFIG_ATH79_MACH_MR16) += mach-mr16.o ++obj-$(CONFIG_ATH79_MACH_MR600) += mach-mr600.o ++obj-$(CONFIG_ATH79_MACH_MR900) += mach-mr900.o ++obj-$(CONFIG_ATH79_MACH_MYNET_N600) += mach-mynet-n600.o ++obj-$(CONFIG_ATH79_MACH_MYNET_N750) += mach-mynet-n750.o ++obj-$(CONFIG_ATH79_MACH_MYNET_REXT) += mach-mynet-rext.o ++obj-$(CONFIG_ATH79_MACH_MZK_W04NU) += mach-mzk-w04nu.o ++obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += mach-mzk-w300nh.o ++obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o ++obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o ++obj-$(CONFIG_ATH79_MACH_OM5P) += mach-om5p.o ++obj-$(CONFIG_ATH79_MACH_ONION_OMEGA) += mach-onion-omega.o ++obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o + obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o ++obj-$(CONFIG_ATH79_MACH_PB92) += mach-pb92.o ++obj-$(CONFIG_ATH79_MACH_QIHOO_C301) += mach-qihoo-c301.o ++obj-$(CONFIG_ATH79_MACH_R6100) += mach-r6100.o ++obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-rb4xx.o ++obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o ++obj-$(CONFIG_ATH79_MACH_RB91X) += mach-rb91x.o ++obj-$(CONFIG_ATH79_MACH_RB922) += mach-rb922.o ++obj-$(CONFIG_ATH79_MACH_RB95X) += mach-rb95x.o ++obj-$(CONFIG_ATH79_MACH_RB2011) += mach-rb2011.o ++obj-$(CONFIG_ATH79_MACH_RBSXTLITE) += mach-rbsxtlite.o ++obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o ++obj-$(CONFIG_ATH79_MACH_SMART_300) += mach-smart-300.o ++obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o ++obj-$(CONFIG_ATH79_MACH_TEW_673GRU) += mach-tew-673gru.o ++obj-$(CONFIG_ATH79_MACH_TEW_712BR) += mach-tew-712br.o ++obj-$(CONFIG_ATH79_MACH_TEW_732BR) += mach-tew-732br.o ++obj-$(CONFIG_ATH79_MACH_TL_MR11U) += mach-tl-mr11u.o ++obj-$(CONFIG_ATH79_MACH_TL_MR13U) += mach-tl-mr13u.o ++obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o ++obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o ++obj-$(CONFIG_ATH79_MACH_TL_WAX50RE) += mach-tl-wax50re.o ++obj-$(CONFIG_ATH79_MACH_TL_WA701ND_V2) += mach-tl-wa701nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WA7210N_V2) += mach-tl-wa7210n-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WA830RE_V2) += mach-tl-wa830re-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR3500) += mach-tl-wdr3500.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o ++obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o ++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V8) += mach-tl-wr841n-v8.o ++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V9) += mach-tl-wr841n-v9.o ++obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR1041N_V2) += mach-tl-wr1041n-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o ++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND_V2) += mach-tl-wr1043nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WR2543N) += mach-tl-wr2543n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR703N) += mach-tl-wr703n.o ++obj-$(CONFIG_ATH79_MACH_TL_WR720N_V3) += mach-tl-wr720n-v3.o ++obj-$(CONFIG_ATH79_MACH_TUBE2H) += mach-tube2h.o ++obj-$(CONFIG_ATH79_MACH_UBNT) += mach-ubnt.o + obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o ++obj-$(CONFIG_ATH79_MACH_WEIO) += mach-weio.o ++obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o ++obj-$(CONFIG_ATH79_MACH_WLAE_AG300N) += mach-wlae-ag300n.o ++obj-$(CONFIG_ATH79_MACH_WLR8100) += mach-wlr8100.o ++obj-$(CONFIG_ATH79_MACH_WNDAP360) += mach-wndap360.o ++obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o ++obj-$(CONFIG_ATH79_MACH_WNDR4300) += mach-wndr4300.o ++obj-$(CONFIG_ATH79_MACH_WNR2000) += mach-wnr2000.o ++obj-$(CONFIG_ATH79_MACH_WNR2000_V3) += mach-wnr2000-v3.o ++obj-$(CONFIG_ATH79_MACH_WNR2000_V4) += mach-wnr2000-v4.o ++obj-$(CONFIG_ATH79_MACH_WNR2200) += mach-wnr2200.o ++obj-$(CONFIG_ATH79_MACH_WP543) += mach-wp543.o ++obj-$(CONFIG_ATH79_MACH_WPE72) += mach-wpe72.o ++obj-$(CONFIG_ATH79_MACH_WPJ344) += mach-wpj344.o ++obj-$(CONFIG_ATH79_MACH_WPJ531) += mach-wpj531.o ++obj-$(CONFIG_ATH79_MACH_WPJ558) += mach-wpj558.o ++obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o ++obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o ++obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o ++obj-$(CONFIG_ATH79_MACH_WZR_450HP2) += mach-wzr-450hp2.o ++obj-$(CONFIG_ATH79_MACH_ZCN_1523H) += mach-zcn-1523h.o ++obj-$(CONFIG_ATH79_MACH_CARAMBOLA2) += mach-carambola2.o ++obj-$(CONFIG_ATH79_MACH_NBG6716) += mach-nbg6716.o +--- a/arch/mips/ath79/prom.c ++++ b/arch/mips/ath79/prom.c +@@ -130,6 +130,13 @@ void __init prom_init(void) + initrd_end = initrd_start + fw_getenvl("initrd_size"); + } + #endif ++ ++ if (strstr(arcs_cmdline, "board=750Gr3") || ++ strstr(arcs_cmdline, "board=951G") || ++ strstr(arcs_cmdline, "board=2011L") || ++ strstr(arcs_cmdline, "board=711Gr100") || ++ strstr(arcs_cmdline, "board=922gs")) ++ ath79_prom_append_cmdline("console", "ttyS0,115200"); + } + + void __init prom_free_prom_memory(void) diff --git a/target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch b/target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch new file mode 100644 index 0000000..23425dc --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch @@ -0,0 +1,60 @@ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -221,15 +221,27 @@ void __init ath79_gpio_output_select(uns + { + void __iomem *base = ath79_gpio_base; + unsigned long flags; +- unsigned int reg; ++ unsigned int reg, reg_base; ++ unsigned long gpio_count; + u32 t, s; + +- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x()); ++ if (soc_is_ar934x()) { ++ gpio_count = AR934X_GPIO_COUNT; ++ reg_base = AR934X_GPIO_REG_OUT_FUNC0; ++ } else if (soc_is_qca953x()) { ++ gpio_count = QCA953X_GPIO_COUNT; ++ reg_base = QCA953X_GPIO_REG_OUT_FUNC0; ++ } else if (soc_is_qca955x()) { ++ gpio_count = QCA955X_GPIO_COUNT; ++ reg_base = QCA955X_GPIO_REG_OUT_FUNC0; ++ } else { ++ BUG(); ++ } + +- if (gpio >= AR934X_GPIO_COUNT) ++ if (gpio >= gpio_count) + return; + +- reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); ++ reg = reg_base + 4 * (gpio / 4); + s = 8 * (gpio % 4); + + spin_lock_irqsave(&ath79_gpio_lock, flags); +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -868,6 +868,14 @@ + #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 + #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + ++#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c ++#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 ++#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 ++#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 ++#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c ++#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 ++#define QCA955X_GPIO_REG_FUNC 0x6c ++ + #define QCA956X_GPIO_REG_OUT_FUNC0 0x2c + #define QCA956X_GPIO_REG_OUT_FUNC1 0x30 + #define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +@@ -1007,6 +1015,8 @@ + #define AR934X_GPIO_OUT_EXT_LNA0 46 + #define AR934X_GPIO_OUT_EXT_LNA1 47 + ++#define QCA955X_GPIO_OUT_GPIO 0 ++ + /* + * MII_CTRL block + */ diff --git a/target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch new file mode 100644 index 0000000..a57351e --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/740-MIPS-ath79-add-PCI-for-QCA953x-SoC.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/ath79/pci.c ++++ b/arch/mips/ath79/pci.c +@@ -53,6 +53,15 @@ static const struct ath79_pci_irq ar724x + } + }; + ++static const struct ath79_pci_irq qca953x_pci_irq_map[] __initconst = { ++ { ++ .bus = 0, ++ .slot = 0, ++ .pin = 1, ++ .irq = ATH79_PCI_IRQ(0), ++ }, ++}; ++ + static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = { + { + .bus = 0, +@@ -98,6 +107,9 @@ int __init pcibios_map_irq(const struct + soc_is_ar9344()) { + ath79_pci_irq_map = ar724x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); ++ } else if (soc_is_qca953x()) { ++ ath79_pci_irq_map = qca953x_pci_irq_map; ++ ath79_pci_nr_irqs = ARRAY_SIZE(qca953x_pci_irq_map); + } else if (soc_is_qca955x()) { + ath79_pci_irq_map = qca955x_pci_irq_map; + ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map); +@@ -303,6 +315,15 @@ int __init ath79_register_pci(void) + AR724X_PCI_MEM_SIZE, + 0, + ATH79_IP2_IRQ(0)); ++ } else if (soc_is_qca9533()) { ++ pdev = ath79_register_pci_ar724x(0, ++ QCA953X_PCI_CFG_BASE0, ++ QCA953X_PCI_CTRL_BASE0, ++ QCA953X_PCI_CRP_BASE0, ++ QCA953X_PCI_MEM_BASE0, ++ QCA953X_PCI_MEM_SIZE, ++ 0, ++ ATH79_IP2_IRQ(0)); + } else if (soc_is_qca9558()) { + pdev = ath79_register_pci_ar724x(0, + QCA955X_PCI_CFG_BASE0, diff --git a/target/linux/ar71xx/patches-4.1/799-MIPS-ath79-add-minibox-v1-support.patch b/target/linux/ar71xx/patches-4.1/799-MIPS-ath79-add-minibox-v1-support.patch new file mode 100644 index 0000000..55a0248 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/799-MIPS-ath79-add-minibox-v1-support.patch @@ -0,0 +1,39 @@ +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -69,6 +69,7 @@ enum ath79_mach_type { + ATH79_MACH_EPG5000, /* EnGenius EPG5000 */ + ATH79_MACH_F9K1115V2, /* Belkin AC1750DB */ + ATH79_MACH_GL_INET, /* GL-CONNECT GL-INET */ ++ ATH79_MACH_GS_MINIBOX_V1, /* Gainstrong MiniBox V1.0 */ + ATH79_MACH_GS_OOLITE, /* GS OOLITE V1.0 */ + ATH79_MACH_HIWIFI_HC6361, /* HiWiFi HC6361 */ + ATH79_MACH_JA76PF, /* jjPlus JA76PF */ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -556,6 +556,16 @@ config ATH79_MACH_EAP300V2 + select ATH79_DEV_M25P80 + select ATH79_DEV_WMAC + ++config ATH79_MACH_GS_MINIBOX_V1 ++ bool "Gainstrong MiniBox V1.0 support" ++ select SOC_AR933X ++ select ARH79_DEV_ETH ++ select ARH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_GS_OOLITE + bool "GS Oolite V1 support" + select SOC_AR933X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -80,6 +80,7 @@ obj-$(CONFIG_ATH79_MACH_EPG5000) += mach + obj-$(CONFIG_ATH79_MACH_ESR1750) += mach-esr1750.o + obj-$(CONFIG_ATH79_MACH_F9K1115V2) += mach-f9k1115v2.o + obj-$(CONFIG_ATH79_MACH_GL_INET) += mach-gl-inet.o ++obj-$(CONFIG_ATH79_MACH_GS_MINIBOX_V1) += mach-gs-minibox-v1.o + obj-$(CONFIG_ATH79_MACH_GS_OOLITE) += mach-gs-oolite.o + obj-$(CONFIG_ATH79_MACH_HIWIFI_HC6361) += mach-hiwifi-hc6361.o + obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o diff --git a/target/linux/ar71xx/patches-4.1/813-MIPS-ath79-add-ap147-support.patch b/target/linux/ar71xx/patches-4.1/813-MIPS-ath79-add-ap147-support.patch new file mode 100644 index 0000000..ed0d984 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/813-MIPS-ath79-add-ap147-support.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -138,6 +138,19 @@ config ATH79_MACH_AP143 + Say 'Y' here if you want your kernel to support the + Atheros AP143 reference board. + ++config ATH79_MACH_AP147 ++ bool "Atheros AP147 reference board" ++ select SOC_QCA953X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_AP9X_PCI if PCI ++ help ++ Say 'Y' here if you want your kernel to support the ++ QCA AP147 reference boards. ++ + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -49,6 +49,7 @@ obj-$(CONFIG_ATH79_MACH_AP121) += mach- + obj-$(CONFIG_ATH79_MACH_AP132) += mach-ap132.o + obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o + obj-$(CONFIG_ATH79_MACH_AP143) += mach-ap143.o ++obj-$(CONFIG_ATH79_MACH_AP147) += mach-ap147.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o + obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o + obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -31,6 +31,7 @@ enum ath79_mach_type { + ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */ + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ + ATH79_MACH_AP143, /* Atheros AP143 reference board */ ++ ATH79_MACH_AP147_010, /* Atheros AP147-010 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_AP83, /* Atheros AP83 */ + ATH79_MACH_AP96, /* Atheros AP96 */ diff --git a/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-blackswift.patch b/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-blackswift.patch new file mode 100644 index 0000000..cfa0a6b --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-blackswift.patch @@ -0,0 +1,39 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -914,6 +914,16 @@ config ATH79_MACH_EAP7660D + select ATH79_DEV_LEDS_GPIO + select ATH79_DEV_M25P80 + ++config ATH79_MACH_BSB ++ bool "Smart Electronics Black Swift board" ++ select SOC_AR933X ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_ARCHER_C7 + bool "TP-LINK Archer C5/C7/TL-WDR4900 v2 board support" + select SOC_QCA955X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -56,6 +56,7 @@ obj-$(CONFIG_ATH79_MACH_AP96) += mach-a + obj-$(CONFIG_ATH79_MACH_ARCHER_C7) += mach-archer-c7.o + obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o + obj-$(CONFIG_ATH79_MACH_BHU_BXU2000N2_A)+= mach-bhu-bxu2000n2-a.o ++obj-$(CONFIG_ATH79_MACH_BSB) += mach-bsb.o + obj-$(CONFIG_ATH79_MACH_CAP4200AG) += mach-cap4200ag.o + obj-$(CONFIG_ATH79_MACH_CF_E316N_V2) += mach-cf-e316n-v2.o + obj-$(CONFIG_ATH79_MACH_CPE510) += mach-cpe510.o +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -39,6 +39,7 @@ enum ath79_mach_type { + ATH79_MACH_ARCHER_C7, /* TP-LINK Archer C7 board */ + ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */ + ATH79_MACH_BHU_BXU2000N2_A1, /* BHU BXU2000n-2 A1 */ ++ ATH79_MACH_BSB, /* Smart Electronics Black Swift board */ + ATH79_MACH_CAP4200AG, /* Senao CAP4200AG */ + ATH79_MACH_CARAMBOLA2, /* 8devices Carambola2 */ + ATH79_MACH_CF_E316N_V2, /* COMFAST CF-E316N v2 */ diff --git a/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-tplink-tl-wdr6500-v2-support.patch b/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-tplink-tl-wdr6500-v2-support.patch new file mode 100644 index 0000000..675489f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/814-MIPS-ath79-add-tplink-tl-wdr6500-v2-support.patch @@ -0,0 +1,40 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -1063,6 +1063,17 @@ config ATH79_MACH_TL_WDR4300 + select ATH79_DEV_USB + select ATH79_DEV_WMAC + ++config ATH79_MACH_TL_WDR6500_V2 ++ bool "TP-LINK TL-WDR6500 v2 board support" ++ select SOC_QCA956X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_TL_WR703N + bool "TP-LINK TL-WR703N/TL-WR710N/TL-MR10U support" + select SOC_AR933X +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -156,6 +156,7 @@ enum ath79_mach_type { + ATH79_MACH_TL_WA901ND_V3, /* TP-LINK TL-WA901ND v3 */ + ATH79_MACH_TL_WDR3500, /* TP-LINK TL-WDR3500 */ + ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */ ++ ATH79_MACH_TL_WDR6500_V2, /* TP-LINK TL-WDR6500 v2 */ + ATH79_MACH_TL_WDR4900_V2, /* TP-LINK TL-WDR4900 v2 */ + ATH79_MACH_TL_WR1041N_V2, /* TP-LINK TL-WR1041N v2 */ + ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1043ND */ +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -132,6 +132,7 @@ obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += m + obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WDR3500) += mach-tl-wdr3500.o + obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR6500_V2) += mach-tl-wdr6500-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o + obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o + obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o diff --git a/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-ap152-support.patch b/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-ap152-support.patch new file mode 100644 index 0000000..b134914 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-ap152-support.patch @@ -0,0 +1,43 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -151,6 +151,20 @@ config ATH79_MACH_AP147 + Say 'Y' here if you want your kernel to support the + QCA AP147 reference boards. + ++config ATH79_MACH_AP152 ++ bool "Atheros AP152 reference board" ++ select SOC_QCA956X ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ select ATH79_DEV_AP9X_PCI if PCI ++ help ++ Say 'Y' here if you want your kernel to support the ++ QCA AP152 reference boards. ++ ++ + config ATH79_MACH_AP81 + bool "Atheros AP81 reference board" + select SOC_AR913X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -50,6 +50,7 @@ obj-$(CONFIG_ATH79_MACH_AP132) += mach- + obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o + obj-$(CONFIG_ATH79_MACH_AP143) += mach-ap143.o + obj-$(CONFIG_ATH79_MACH_AP147) += mach-ap147.o ++obj-$(CONFIG_ATH79_MACH_AP152) += mach-ap152.o + obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o + obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o + obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -32,6 +32,7 @@ enum ath79_mach_type { + ATH79_MACH_AP136_020, /* Atheros AP136-020 reference board */ + ATH79_MACH_AP143, /* Atheros AP143 reference board */ + ATH79_MACH_AP147_010, /* Atheros AP147-010 reference board */ ++ ATH79_MACH_AP152, /* Atheros AP152 reference board */ + ATH79_MACH_AP81, /* Atheros AP81 reference board */ + ATH79_MACH_AP83, /* Atheros AP83 */ + ATH79_MACH_AP96, /* Atheros AP96 */ diff --git a/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-mr1750-support.patch b/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-mr1750-support.patch new file mode 100644 index 0000000..6f28086 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/815-MIPS-ath79-add-mr1750-support.patch @@ -0,0 +1,39 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -910,6 +910,16 @@ config ATH79_MACH_CAP4200AG + select ATH79_DEV_M25P80 + select ATH79_DEV_WMAC + ++config ATH79_MACH_MR1750 ++ bool "OpenMesh MR1750 board support" ++ select SOC_QCA955X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_MR900 + bool "OpenMesh MR900 board support" + select SOC_QCA955X +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -92,6 +92,7 @@ obj-$(CONFIG_ATH79_MACH_HORNET_UB) += ma + obj-$(CONFIG_ATH79_MACH_MC_MAC1200R) += mach-mc-mac1200r.o + obj-$(CONFIG_ATH79_MACH_MR12) += mach-mr12.o + obj-$(CONFIG_ATH79_MACH_MR16) += mach-mr16.o ++obj-$(CONFIG_ATH79_MACH_MR1750) += mach-mr1750.o + obj-$(CONFIG_ATH79_MACH_MR600) += mach-mr600.o + obj-$(CONFIG_ATH79_MACH_MR900) += mach-mr900.o + obj-$(CONFIG_ATH79_MACH_MYNET_N600) += mach-mynet-n600.o +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -81,6 +81,7 @@ enum ath79_mach_type { + ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */ + ATH79_MACH_MR12, /* Cisco Meraki MR12 */ + ATH79_MACH_MR16, /* Cisco Meraki MR16 */ ++ ATH79_MACH_MR1750, /* OpenMesh MR1750 */ + ATH79_MACH_MR600V2, /* OpenMesh MR600v2 */ + ATH79_MACH_MR600, /* OpenMesh MR600 */ + ATH79_MACH_MR900, /* OpenMesh MR900 */ diff --git a/target/linux/ar71xx/patches-4.1/816-MIPS-ath79-add-tl-wdr3320-v2-support.patch b/target/linux/ar71xx/patches-4.1/816-MIPS-ath79-add-tl-wdr3320-v2-support.patch new file mode 100644 index 0000000..aa78d59 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/816-MIPS-ath79-add-tl-wdr3320-v2-support.patch @@ -0,0 +1,40 @@ +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -1065,6 +1065,17 @@ config ATH79_MACH_TL_WA901ND_V2 + select ATH79_DEV_M25P80 + select ATH79_DEV_WMAC + ++config ATH79_MACH_TL_WDR3320_V2 ++ bool "TP-LINK TL-WDR3320 v2 board support" ++ select SOC_AR934X ++ select ATH79_DEV_AP9X_PCI if PCI ++ select ATH79_DEV_ETH ++ select ATH79_DEV_GPIO_BUTTONS ++ select ATH79_DEV_LEDS_GPIO ++ select ATH79_DEV_M25P80 ++ select ATH79_DEV_USB ++ select ATH79_DEV_WMAC ++ + config ATH79_MACH_TL_WDR3500 + bool "TP-LINK TL-WDR3500 board support" + select SOC_AR934X +--- a/arch/mips/ath79/machtypes.h ++++ b/arch/mips/ath79/machtypes.h +@@ -156,6 +156,7 @@ enum ath79_mach_type { + ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */ + ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */ + ATH79_MACH_TL_WA901ND_V3, /* TP-LINK TL-WA901ND v3 */ ++ ATH79_MACH_TL_WDR3320_V2, /* TP-LINK TL-WDR3320 v2 */ + ATH79_MACH_TL_WDR3500, /* TP-LINK TL-WDR3500 */ + ATH79_MACH_TL_WDR4300, /* TP-LINK TL-WDR4300 */ + ATH79_MACH_TL_WDR6500_V2, /* TP-LINK TL-WDR6500 v2 */ +--- a/arch/mips/ath79/Makefile ++++ b/arch/mips/ath79/Makefile +@@ -132,6 +132,7 @@ obj-$(CONFIG_ATH79_MACH_TL_WA7210N_V2) + + obj-$(CONFIG_ATH79_MACH_TL_WA830RE_V2) += mach-tl-wa830re-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o + obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o ++obj-$(CONFIG_ATH79_MACH_TL_WDR3320_V2) += mach-tl-wdr3320-v2.o + obj-$(CONFIG_ATH79_MACH_TL_WDR3500) += mach-tl-wdr3500.o + obj-$(CONFIG_ATH79_MACH_TL_WDR4300) += mach-tl-wdr4300.o + obj-$(CONFIG_ATH79_MACH_TL_WDR6500_V2) += mach-tl-wdr6500-v2.o diff --git a/target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch b/target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch new file mode 100644 index 0000000..39584aa --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/900-mdio_bitbang_ignore_ta_value.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/phy/mdio-bitbang.c ++++ b/drivers/net/phy/mdio-bitbang.c +@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b + + ctrl->ops->set_mdio_dir(ctrl, 0); + +- /* check the turnaround bit: the PHY should be driving it to zero */ +- if (mdiobb_get_bit(ctrl) != 0) { +- /* PHY didn't drive TA low -- flush any bits it +- * may be trying to send. +- */ +- for (i = 0; i < 32; i++) +- mdiobb_get_bit(ctrl); +- +- return 0xffff; +- } ++ mdiobb_get_bit(ctrl); + + ret = mdiobb_get_num(ctrl, 16); + mdiobb_get_bit(ctrl); diff --git a/target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch b/target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch new file mode 100644 index 0000000..68f86e0 --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch @@ -0,0 +1,61 @@ +From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 16 Jun 2015 13:15:08 +0200 +Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command + +It seems some phys have some maximum timings for accessing the MDIO line, +resulting in bit errors under cpu stress. Prevent this from happening by +disabling interrupts when sending commands. + +Signed-off-by: Jonas Gorski +--- + drivers/net/phy/mdio-bitbang.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/phy/mdio-bitbang.c ++++ b/drivers/net/phy/mdio-bitbang.c +@@ -17,6 +17,7 @@ + * kind, whether express or implied. + */ + ++#include + #include + #include + #include +@@ -156,7 +157,9 @@ static int mdiobb_read(struct mii_bus *b + { + struct mdiobb_ctrl *ctrl = bus->priv; + int ret, i; ++ long flags; + ++ local_irq_save(flags); + if (reg & MII_ADDR_C45) { + reg = mdiobb_cmd_addr(ctrl, phy, reg); + mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); +@@ -169,13 +172,17 @@ static int mdiobb_read(struct mii_bus *b + + ret = mdiobb_get_num(ctrl, 16); + mdiobb_get_bit(ctrl); ++ local_irq_restore(flags); ++ + return ret; + } + + static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) + { + struct mdiobb_ctrl *ctrl = bus->priv; ++ long flags; + ++ local_irq_save(flags); + if (reg & MII_ADDR_C45) { + reg = mdiobb_cmd_addr(ctrl, phy, reg); + mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); +@@ -190,6 +197,8 @@ static int mdiobb_write(struct mii_bus * + + ctrl->ops->set_mdio_dir(ctrl, 0); + mdiobb_get_bit(ctrl); ++ local_irq_restore(flags); ++ + return 0; + } + diff --git a/target/linux/ar71xx/patches-4.1/910-unaligned_access_hacks.patch b/target/linux/ar71xx/patches-4.1/910-unaligned_access_hacks.patch new file mode 100644 index 0000000..d98695f --- /dev/null +++ b/target/linux/ar71xx/patches-4.1/910-unaligned_access_hacks.patch @@ -0,0 +1,893 @@ +--- a/arch/mips/include/asm/checksum.h ++++ b/arch/mips/include/asm/checksum.h +@@ -134,26 +134,30 @@ static inline __sum16 ip_fast_csum(const + const unsigned int *stop = word + ihl; + unsigned int csum; + int carry; ++ unsigned int w; + +- csum = word[0]; +- csum += word[1]; +- carry = (csum < word[1]); ++ csum = net_hdr_word(word++); ++ ++ w = net_hdr_word(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- csum += word[2]; +- carry = (csum < word[2]); ++ w = net_hdr_word(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- csum += word[3]; +- carry = (csum < word[3]); ++ w = net_hdr_word(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; + +- word += 4; + do { +- csum += *word; +- carry = (csum < *word); ++ w = net_hdr_word(word++); ++ csum += w; ++ carry = (csum < w); + csum += carry; +- word++; + } while (word != stop); + + return csum_fold(csum); +@@ -212,73 +216,6 @@ static inline __sum16 ip_compute_csum(co + return csum_fold(csum_partial(buff, len, 0)); + } + +-#define _HAVE_ARCH_IPV6_CSUM +-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, +- const struct in6_addr *daddr, +- __u32 len, unsigned short proto, +- __wsum sum) +-{ +- __wsum tmp; +- +- __asm__( +- " .set push # csum_ipv6_magic\n" +- " .set noreorder \n" +- " .set noat \n" +- " addu %0, %5 # proto (long in network byte order)\n" +- " sltu $1, %0, %5 \n" +- " addu %0, $1 \n" +- +- " addu %0, %6 # csum\n" +- " sltu $1, %0, %6 \n" +- " lw %1, 0(%2) # four words source address\n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 4(%2) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 8(%2) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 12(%2) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 0(%3) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 4(%3) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 8(%3) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " lw %1, 12(%3) \n" +- " addu %0, $1 \n" +- " addu %0, %1 \n" +- " sltu $1, %0, %1 \n" +- +- " addu %0, $1 # Add final carry\n" +- " .set pop" +- : "=&r" (sum), "=&r" (tmp) +- : "r" (saddr), "r" (daddr), +- "0" (htonl(len)), "r" (htonl(proto)), "r" (sum)); +- +- return csum_fold(sum); +-} +- + #include + #endif /* CONFIG_GENERIC_CSUM */ + +--- a/include/uapi/linux/ip.h ++++ b/include/uapi/linux/ip.h +@@ -102,7 +102,7 @@ struct iphdr { + __be32 saddr; + __be32 daddr; + /*The options start here. */ +-}; ++} __attribute__((packed, aligned(2))); + + + struct ip_auth_hdr { +--- a/include/uapi/linux/ipv6.h ++++ b/include/uapi/linux/ipv6.h +@@ -129,7 +129,7 @@ struct ipv6hdr { + + struct in6_addr saddr; + struct in6_addr daddr; +-}; ++} __attribute__((packed, aligned(2))); + + + /* index values for the variables in ipv6_devconf */ +--- a/include/uapi/linux/tcp.h ++++ b/include/uapi/linux/tcp.h +@@ -54,7 +54,7 @@ struct tcphdr { + __be16 window; + __sum16 check; + __be16 urg_ptr; +-}; ++} __attribute__((packed, aligned(2))); + + /* + * The union cast uses a gcc extension to avoid aliasing problems +@@ -64,7 +64,7 @@ struct tcphdr { + union tcp_word_hdr { + struct tcphdr hdr; + __be32 words[5]; +-}; ++} __attribute__((packed, aligned(2))); + + #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) + +--- a/include/uapi/linux/udp.h ++++ b/include/uapi/linux/udp.h +@@ -24,7 +24,7 @@ struct udphdr { + __be16 dest; + __be16 len; + __sum16 check; +-}; ++} __attribute__((packed, aligned(2))); + + /* UDP socket options */ + #define UDP_CORK 1 /* Never send partially complete segments */ +--- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c ++++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c +@@ -41,8 +41,8 @@ static bool ipv4_pkt_to_tuple(const stru + if (ap == NULL) + return false; + +- tuple->src.u3.ip = ap[0]; +- tuple->dst.u3.ip = ap[1]; ++ tuple->src.u3.ip = net_hdr_word(ap++); ++ tuple->dst.u3.ip = net_hdr_word(ap); + + return true; + } +--- a/include/uapi/linux/icmp.h ++++ b/include/uapi/linux/icmp.h +@@ -80,7 +80,7 @@ struct icmphdr { + __be16 mtu; + } frag; + } un; +-}; ++} __attribute__((packed, aligned(2))); + + + /* +--- a/include/uapi/linux/in6.h ++++ b/include/uapi/linux/in6.h +@@ -42,7 +42,7 @@ struct in6_addr { + #define s6_addr16 in6_u.u6_addr16 + #define s6_addr32 in6_u.u6_addr32 + #endif +-}; ++} __attribute__((packed, aligned(2))); + #endif /* __UAPI_DEF_IN6_ADDR */ + + #if __UAPI_DEF_SOCKADDR_IN6 +--- a/net/ipv6/tcp_ipv6.c ++++ b/net/ipv6/tcp_ipv6.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -772,10 +773,10 @@ static void tcp_v6_send_response(struct + topt = (__be32 *)(t1 + 1); + + if (tsecr) { +- *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | +- (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP); +- *topt++ = htonl(tsval); +- *topt++ = htonl(tsecr); ++ put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | ++ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++); ++ put_unaligned_be32(tsval, topt++); ++ put_unaligned_be32(tsecr, topt++); + } + + #ifdef CONFIG_TCP_MD5SIG +--- a/include/linux/ipv6.h ++++ b/include/linux/ipv6.h +@@ -5,6 +5,7 @@ + + #define ipv6_optlen(p) (((p)->hdrlen+1) << 3) + #define ipv6_authlen(p) (((p)->hdrlen+2) << 2) ++ + /* + * This structure contains configuration options per IPv6 link. + */ +--- a/net/ipv6/datagram.c ++++ b/net/ipv6/datagram.c +@@ -424,7 +424,7 @@ int ipv6_recv_error(struct sock *sk, str + ipv6_iface_scope_id(&sin->sin6_addr, + IP6CB(skb)->iif); + } else { +- ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset), ++ ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset), + &sin->sin6_addr); + sin->sin6_scope_id = 0; + } +@@ -761,12 +761,12 @@ int ip6_datagram_send_ctl(struct net *ne + } + + if (fl6->flowlabel&IPV6_FLOWINFO_MASK) { +- if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) { ++ if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) { + err = -EINVAL; + goto exit_f; + } + } +- fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg); ++ fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg)); + break; + + case IPV6_2292HOPOPTS: +--- a/net/ipv6/ip6_gre.c ++++ b/net/ipv6/ip6_gre.c +@@ -394,7 +394,7 @@ static void ip6gre_err(struct sk_buff *s + + t = ip6gre_tunnel_lookup(skb->dev, &ipv6h->daddr, &ipv6h->saddr, + flags & GRE_KEY ? +- *(((__be32 *)p) + (grehlen / 4) - 1) : 0, ++ net_hdr_word(((__be32 *)p) + (grehlen / 4) - 1) : 0, + p[1]); + if (!t) + return; +@@ -476,11 +476,11 @@ static int ip6gre_rcv(struct sk_buff *sk + offset += 4; + } + if (flags&GRE_KEY) { +- key = *(__be32 *)(h + offset); ++ key = net_hdr_word(h + offset); + offset += 4; + } + if (flags&GRE_SEQ) { +- seqno = ntohl(*(__be32 *)(h + offset)); ++ seqno = ntohl(net_hdr_word(h + offset)); + offset += 4; + } + } +@@ -745,7 +745,7 @@ static netdev_tx_t ip6gre_xmit2(struct s + + if (tunnel->parms.o_flags&GRE_SEQ) { + ++tunnel->o_seqno; +- *ptr = htonl(tunnel->o_seqno); ++ net_hdr_word(ptr) = htonl(tunnel->o_seqno); + ptr--; + } + if (tunnel->parms.o_flags&GRE_KEY) { +@@ -841,7 +841,7 @@ static inline int ip6gre_xmit_ipv6(struc + + dsfield = ipv6_get_dsfield(ipv6h); + if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS) +- fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK); ++ fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK; + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL) + fl6.flowlabel |= ip6_flowlabel(ipv6h); + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK) +--- a/net/ipv6/ip6_tunnel.c ++++ b/net/ipv6/ip6_tunnel.c +@@ -1340,7 +1340,7 @@ ip6ip6_tnl_xmit(struct sk_buff *skb, str + + dsfield = ipv6_get_dsfield(ipv6h); + if (t->parms.flags & IP6_TNL_F_USE_ORIG_TCLASS) +- fl6.flowlabel |= (*(__be32 *) ipv6h & IPV6_TCLASS_MASK); ++ fl6.flowlabel |= net_hdr_word(ipv6h) & IPV6_TCLASS_MASK; + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FLOWLABEL) + fl6.flowlabel |= ip6_flowlabel(ipv6h); + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK) +--- a/net/ipv6/exthdrs.c ++++ b/net/ipv6/exthdrs.c +@@ -573,7 +573,7 @@ static bool ipv6_hop_jumbo(struct sk_buf + goto drop; + } + +- pkt_len = ntohl(*(__be32 *)(nh + optoff + 2)); ++ pkt_len = ntohl(net_hdr_word(nh + optoff + 2)); + if (pkt_len <= IPV6_MAXPLEN) { + IP6_INC_STATS_BH(net, ipv6_skb_idev(skb), + IPSTATS_MIB_INHDRERRORS); +--- a/include/linux/types.h ++++ b/include/linux/types.h +@@ -215,5 +215,11 @@ struct callback_head { + /* clocksource cycle base type */ + typedef u64 cycle_t; + ++struct net_hdr_word { ++ u32 words[1]; ++} __attribute__((packed, aligned(2))); ++ ++#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0]) ++ + #endif /* __ASSEMBLY__ */ + #endif /* _LINUX_TYPES_H */ +--- a/net/ipv4/af_inet.c ++++ b/net/ipv4/af_inet.c +@@ -1323,8 +1323,8 @@ static struct sk_buff **inet_gro_receive + if (unlikely(ip_fast_csum((u8 *)iph, 5))) + goto out_unlock; + +- id = ntohl(*(__be32 *)&iph->id); +- flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF)); ++ id = ntohl(net_hdr_word(&iph->id)); ++ flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF)); + id >>= 16; + + for (p = *head; p; p = p->next) { +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -453,7 +453,7 @@ static struct neighbour *ipv4_neigh_look + else if (skb) + pkey = &ip_hdr(skb)->daddr; + +- n = __ipv4_neigh_lookup(dev, *(__force u32 *)pkey); ++ n = __ipv4_neigh_lookup(dev, net_hdr_word(pkey)); + if (n) + return n; + return neigh_create(&arp_tbl, pkey, dev); +--- a/net/ipv4/tcp_output.c ++++ b/net/ipv4/tcp_output.c +@@ -452,48 +452,53 @@ static void tcp_options_write(__be32 *pt + u16 options = opts->options; /* mungable copy */ + + if (unlikely(OPTION_MD5 & options)) { +- *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | +- (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | ++ (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); + /* overload cookie hash location */ + opts->hash_location = (__u8 *)ptr; + ptr += 4; + } + + if (unlikely(opts->mss)) { +- *ptr++ = htonl((TCPOPT_MSS << 24) | +- (TCPOLEN_MSS << 16) | +- opts->mss); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) | ++ opts->mss); + } + + if (likely(OPTION_TS & options)) { + if (unlikely(OPTION_SACK_ADVERTISE & options)) { +- *ptr++ = htonl((TCPOPT_SACK_PERM << 24) | +- (TCPOLEN_SACK_PERM << 16) | +- (TCPOPT_TIMESTAMP << 8) | +- TCPOLEN_TIMESTAMP); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_SACK_PERM << 24) | ++ (TCPOLEN_SACK_PERM << 16) | ++ (TCPOPT_TIMESTAMP << 8) | ++ TCPOLEN_TIMESTAMP); + options &= ~OPTION_SACK_ADVERTISE; + } else { +- *ptr++ = htonl((TCPOPT_NOP << 24) | +- (TCPOPT_NOP << 16) | +- (TCPOPT_TIMESTAMP << 8) | +- TCPOLEN_TIMESTAMP); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_NOP << 16) | ++ (TCPOPT_TIMESTAMP << 8) | ++ TCPOLEN_TIMESTAMP); + } +- *ptr++ = htonl(opts->tsval); +- *ptr++ = htonl(opts->tsecr); ++ net_hdr_word(ptr++) = htonl(opts->tsval); ++ net_hdr_word(ptr++) = htonl(opts->tsecr); + } + + if (unlikely(OPTION_SACK_ADVERTISE & options)) { +- *ptr++ = htonl((TCPOPT_NOP << 24) | +- (TCPOPT_NOP << 16) | +- (TCPOPT_SACK_PERM << 8) | +- TCPOLEN_SACK_PERM); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_NOP << 16) | ++ (TCPOPT_SACK_PERM << 8) | ++ TCPOLEN_SACK_PERM); + } + + if (unlikely(OPTION_WSCALE & options)) { +- *ptr++ = htonl((TCPOPT_NOP << 24) | +- (TCPOPT_WINDOW << 16) | +- (TCPOLEN_WINDOW << 8) | +- opts->ws); ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_WINDOW << 16) | ++ (TCPOLEN_WINDOW << 8) | ++ opts->ws); + } + + if (unlikely(opts->num_sack_blocks)) { +@@ -501,16 +506,17 @@ static void tcp_options_write(__be32 *pt + tp->duplicate_sack : tp->selective_acks; + int this_sack; + +- *ptr++ = htonl((TCPOPT_NOP << 24) | +- (TCPOPT_NOP << 16) | +- (TCPOPT_SACK << 8) | +- (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * ++ net_hdr_word(ptr++) = ++ htonl((TCPOPT_NOP << 24) | ++ (TCPOPT_NOP << 16) | ++ (TCPOPT_SACK << 8) | ++ (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * + TCPOLEN_SACK_PERBLOCK))); + + for (this_sack = 0; this_sack < opts->num_sack_blocks; + ++this_sack) { +- *ptr++ = htonl(sp[this_sack].start_seq); +- *ptr++ = htonl(sp[this_sack].end_seq); ++ net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq); ++ net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq); + } + + tp->rx_opt.dsack = 0; +@@ -523,13 +529,14 @@ static void tcp_options_write(__be32 *pt + + if (foc->exp) { + len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len; +- *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) | ++ net_hdr_word(ptr) = ++ htonl((TCPOPT_EXP << 24) | (len << 16) | + TCPOPT_FASTOPEN_MAGIC); + p += TCPOLEN_EXP_FASTOPEN_BASE; + } else { + len = TCPOLEN_FASTOPEN_BASE + foc->len; +- *p++ = TCPOPT_FASTOPEN; +- *p++ = len; ++ net_hdr_word(p++) = TCPOPT_FASTOPEN; ++ net_hdr_word(p++) = len; + } + + memcpy(p, foc->val, foc->len); +--- a/net/ipv4/igmp.c ++++ b/net/ipv4/igmp.c +@@ -496,7 +496,7 @@ static struct sk_buff *add_grec(struct s + if (!skb) + return NULL; + psrc = (__be32 *)skb_put(skb, sizeof(__be32)); +- *psrc = psf->sf_inaddr; ++ net_hdr_word(psrc) = psf->sf_inaddr; + scount++; stotal++; + if ((type == IGMPV3_ALLOW_NEW_SOURCES || + type == IGMPV3_BLOCK_OLD_SOURCES) && psf->sf_crcount) { +--- a/include/uapi/linux/igmp.h ++++ b/include/uapi/linux/igmp.h +@@ -32,7 +32,7 @@ struct igmphdr { + __u8 code; /* For newer IGMP */ + __sum16 csum; + __be32 group; +-}; ++} __attribute__((packed, aligned(2))); + + /* V3 group record types [grec_type] */ + #define IGMPV3_MODE_IS_INCLUDE 1 +@@ -48,7 +48,7 @@ struct igmpv3_grec { + __be16 grec_nsrcs; + __be32 grec_mca; + __be32 grec_src[0]; +-}; ++} __attribute__((packed, aligned(2))); + + struct igmpv3_report { + __u8 type; +@@ -57,7 +57,7 @@ struct igmpv3_report { + __be16 resv2; + __be16 ngrec; + struct igmpv3_grec grec[0]; +-}; ++} __attribute__((packed, aligned(2))); + + struct igmpv3_query { + __u8 type; +@@ -78,7 +78,7 @@ struct igmpv3_query { + __u8 qqic; + __be16 nsrcs; + __be32 srcs[0]; +-}; ++} __attribute__((packed, aligned(2))); + + #define IGMP_HOST_MEMBERSHIP_QUERY 0x11 /* From RFC1112 */ + #define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */ +--- a/net/core/flow_dissector.c ++++ b/net/core/flow_dissector.c +@@ -53,7 +53,7 @@ __be32 __skb_flow_get_ports(const struct + ports = __skb_header_pointer(skb, thoff + poff, + sizeof(_ports), data, hlen, &_ports); + if (ports) +- return *ports; ++ return (__be32)net_hdr_word(ports); + } + + return 0; +--- a/include/uapi/linux/icmpv6.h ++++ b/include/uapi/linux/icmpv6.h +@@ -76,7 +76,7 @@ struct icmp6hdr { + #define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other + #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime + #define icmp6_router_pref icmp6_dataun.u_nd_ra.router_pref +-}; ++} __attribute__((packed, aligned(2))); + + + #define ICMPV6_ROUTER_PREF_LOW 0x3 +--- a/include/net/ndisc.h ++++ b/include/net/ndisc.h +@@ -76,7 +76,7 @@ struct ra_msg { + struct icmp6hdr icmph; + __be32 reachable_time; + __be32 retrans_timer; +-}; ++} __attribute__((packed, aligned(2))); + + struct rd_msg { + struct icmp6hdr icmph; +@@ -148,10 +148,10 @@ static inline u32 ndisc_hashfn(const voi + { + const u32 *p32 = pkey; + +- return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) + +- (p32[1] * hash_rnd[1]) + +- (p32[2] * hash_rnd[2]) + +- (p32[3] * hash_rnd[3])); ++ return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) + ++ (net_hdr_word(&p32[1]) * hash_rnd[1]) + ++ (net_hdr_word(&p32[2]) * hash_rnd[2]) + ++ (net_hdr_word(&p32[3]) * hash_rnd[3])); + } + + static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey) +--- a/net/sched/cls_u32.c ++++ b/net/sched/cls_u32.c +@@ -151,7 +151,7 @@ next_knode: + data = skb_header_pointer(skb, toff, 4, &hdata); + if (!data) + goto out; +- if ((*data ^ key->val) & key->mask) { ++ if ((net_hdr_word(data) ^ key->val) & key->mask) { + n = rcu_dereference_bh(n->next); + goto next_knode; + } +@@ -204,8 +204,8 @@ check_terminal: + &hdata); + if (!data) + goto out; +- sel = ht->divisor & u32_hash_fold(*data, &n->sel, +- n->fshift); ++ sel = ht->divisor & u32_hash_fold(net_hdr_word(data), ++ &n->sel, n->fshift); + } + if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT))) + goto next_ht; +--- a/net/ipv6/ip6_offload.c ++++ b/net/ipv6/ip6_offload.c +@@ -221,7 +221,7 @@ static struct sk_buff **ipv6_gro_receive + continue; + + iph2 = (struct ipv6hdr *)(p->data + off); +- first_word = *(__be32 *)iph ^ *(__be32 *)iph2; ++ first_word = net_hdr_word(iph) ^ net_hdr_word(iph2); + + /* All fields must match except length and Traffic Class. + * XXX skbs on the gro_list have all been parsed and pulled +--- a/include/net/addrconf.h ++++ b/include/net/addrconf.h +@@ -43,7 +43,7 @@ struct prefix_info { + __be32 reserved2; + + struct in6_addr prefix; +-}; ++} __attribute__((packed, aligned(2))); + + + #include +--- a/include/net/inet_ecn.h ++++ b/include/net/inet_ecn.h +@@ -115,13 +115,13 @@ static inline int IP6_ECN_set_ce(struct + { + if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph))) + return 0; +- *(__be32*)iph |= htonl(INET_ECN_CE << 20); ++ net_hdr_word(iph) |= htonl(INET_ECN_CE << 20); + return 1; + } + + static inline void IP6_ECN_clear(struct ipv6hdr *iph) + { +- *(__be32*)iph &= ~htonl(INET_ECN_MASK << 20); ++ net_hdr_word(iph) &= ~htonl(INET_ECN_MASK << 20); + } + + static inline void ipv6_copy_dscp(unsigned int dscp, struct ipv6hdr *inner) +--- a/include/net/ipv6.h ++++ b/include/net/ipv6.h +@@ -107,7 +107,7 @@ struct frag_hdr { + __u8 reserved; + __be16 frag_off; + __be32 identification; +-}; ++} __attribute__((packed, aligned(2))); + + #define IP6_MF 0x0001 + #define IP6_OFFSET 0xFFF8 +@@ -396,8 +396,8 @@ static inline void __ipv6_addr_set_half( + } + #endif + #endif +- addr[0] = wh; +- addr[1] = wl; ++ net_hdr_word(&addr[0]) = wh; ++ net_hdr_word(&addr[1]) = wl; + } + + static inline void ipv6_addr_set(struct in6_addr *addr, +@@ -456,6 +456,8 @@ static inline bool ipv6_prefix_equal(con + const __be32 *a1 = addr1->s6_addr32; + const __be32 *a2 = addr2->s6_addr32; + unsigned int pdw, pbi; ++ /* Used for last <32-bit fraction of prefix */ ++ u32 pbia1, pbia2; + + /* check complete u32 in prefix */ + pdw = prefixlen >> 5; +@@ -464,7 +466,9 @@ static inline bool ipv6_prefix_equal(con + + /* check incomplete u32 in prefix */ + pbi = prefixlen & 0x1f; +- if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi)))) ++ pbia1 = net_hdr_word(&a1[pdw]); ++ pbia2 = net_hdr_word(&a2[pdw]); ++ if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi)))) + return false; + + return true; +@@ -607,13 +611,13 @@ static inline void ipv6_addr_set_v4mappe + */ + static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen) + { +- const __be32 *a1 = token1, *a2 = token2; ++ const struct in6_addr *a1 = token1, *a2 = token2; + int i; + + addrlen >>= 2; + + for (i = 0; i < addrlen; i++) { +- __be32 xb = a1[i] ^ a2[i]; ++ __be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i]; + if (xb) + return i * 32 + 31 - __fls(ntohl(xb)); + } +@@ -739,17 +743,18 @@ static inline __be32 ip6_make_flowlabel( + static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass, + __be32 flowlabel) + { +- *(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel; ++ net_hdr_word((__be32 *)hdr) = ++ htonl(0x60000000 | (tclass << 20)) | flowlabel; + } + + static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr) + { +- return *(__be32 *)hdr & IPV6_FLOWINFO_MASK; ++ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK; + } + + static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr) + { +- return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK; ++ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK; + } + + static inline u8 ip6_tclass(__be32 flowinfo) +--- a/include/net/secure_seq.h ++++ b/include/net/secure_seq.h +@@ -2,6 +2,7 @@ + #define _NET_SECURE_SEQ + + #include ++#include + + u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); + u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, +--- a/include/uapi/linux/in.h ++++ b/include/uapi/linux/in.h +@@ -81,7 +81,7 @@ enum { + /* Internet address. */ + struct in_addr { + __be32 s_addr; +-}; ++} __attribute__((packed, aligned(2))); + #endif + + #define IP_TOS 1 +--- a/net/core/secure_seq.c ++++ b/net/core/secure_seq.c +@@ -46,11 +46,12 @@ __u32 secure_tcpv6_sequence_number(const + u32 secret[MD5_MESSAGE_BYTES / 4]; + u32 hash[MD5_DIGEST_WORDS]; + u32 i; ++ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; + + net_secret_init(); + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) +- secret[i] = net_secret[i] + (__force u32)daddr[i]; ++ secret[i] = net_secret[i] + (__force u32)daddr6->s6_addr32[i]; + secret[4] = net_secret[4] + + (((__force u16)sport << 16) + (__force u16)dport); + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) +@@ -68,11 +69,12 @@ u32 secure_ipv6_port_ephemeral(const __b + u32 secret[MD5_MESSAGE_BYTES / 4]; + u32 hash[MD5_DIGEST_WORDS]; + u32 i; ++ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; + + net_secret_init(); + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) +- secret[i] = net_secret[i] + (__force u32) daddr[i]; ++ secret[i] = net_secret[i] + (__force u32) daddr6->s6_addr32[i]; + secret[4] = net_secret[4] + (__force u32)dport; + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) + secret[i] = net_secret[i]; +@@ -150,11 +152,12 @@ u64 secure_dccpv6_sequence_number(__be32 + u32 hash[MD5_DIGEST_WORDS]; + u64 seq; + u32 i; ++ const struct in6_addr *daddr6 = (struct in6_addr *) daddr; + + net_secret_init(); + memcpy(hash, saddr, 16); + for (i = 0; i < 4; i++) +- secret[i] = net_secret[i] + daddr[i]; ++ secret[i] = net_secret[i] + daddr6->s6_addr32[i]; + secret[4] = net_secret[4] + + (((__force u16)sport << 16) + (__force u16)dport); + for (i = 5; i < MD5_MESSAGE_BYTES / 4; i++) +--- a/net/ipv6/ip6_fib.c ++++ b/net/ipv6/ip6_fib.c +@@ -137,7 +137,7 @@ static __be32 addr_bit_set(const void *t + * See include/asm-generic/bitops/le.h. + */ + return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) & +- addr[fn_bit >> 5]; ++ net_hdr_word(&addr[fn_bit >> 5]); + } + + static struct fib6_node *node_alloc(void) +--- a/net/netfilter/nf_conntrack_proto_tcp.c ++++ b/net/netfilter/nf_conntrack_proto_tcp.c +@@ -456,7 +456,7 @@ static void tcp_sack(const struct sk_buf + + /* Fast path for timestamp-only option */ + if (length == TCPOLEN_TSTAMP_ALIGNED +- && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24) ++ && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24) + | (TCPOPT_NOP << 16) + | (TCPOPT_TIMESTAMP << 8) + | TCPOLEN_TIMESTAMP)) +--- a/net/xfrm/xfrm_input.c ++++ b/net/xfrm/xfrm_input.c +@@ -154,8 +154,8 @@ int xfrm_parse_spi(struct sk_buff *skb, + if (!pskb_may_pull(skb, hlen)) + return -EINVAL; + +- *spi = *(__be32 *)(skb_transport_header(skb) + offset); +- *seq = *(__be32 *)(skb_transport_header(skb) + offset_seq); ++ *spi = net_hdr_word(skb_transport_header(skb) + offset); ++ *seq = net_hdr_word(skb_transport_header(skb) + offset_seq); + return 0; + } + +--- a/net/ipv4/tcp_input.c ++++ b/net/ipv4/tcp_input.c +@@ -3760,14 +3760,16 @@ static bool tcp_parse_aligned_timestamp( + { + const __be32 *ptr = (const __be32 *)(th + 1); + +- if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) +- | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { ++ if (net_hdr_word(ptr) == ++ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | ++ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { + tp->rx_opt.saw_tstamp = 1; + ++ptr; +- tp->rx_opt.rcv_tsval = ntohl(*ptr); ++ tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr); + ++ptr; +- if (*ptr) +- tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset; ++ if (net_hdr_word(ptr)) ++ tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) - ++ tp->tsoffset; + else + tp->rx_opt.rcv_tsecr = 0; + return true; +--- a/include/uapi/linux/if_pppox.h ++++ b/include/uapi/linux/if_pppox.h +@@ -47,6 +47,7 @@ struct pppoe_addr { + */ + struct pptp_addr { + __u16 call_id; ++ __u16 pad; + struct in_addr sin_addr; + }; + +--- a/net/ipv6/netfilter/nf_log_ipv6.c ++++ b/net/ipv6/netfilter/nf_log_ipv6.c +@@ -66,9 +66,9 @@ static void dump_ipv6_packet(struct nf_l + /* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */ + nf_log_buf_add(m, "LEN=%Zu TC=%u HOPLIMIT=%u FLOWLBL=%u ", + ntohs(ih->payload_len) + sizeof(struct ipv6hdr), +- (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20, ++ (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20, + ih->hop_limit, +- (ntohl(*(__be32 *)ih) & 0x000fffff)); ++ (ntohl(net_hdr_word(ih)) & 0x000fffff)); + + fragment = 0; + ptr = ip6hoff + sizeof(struct ipv6hdr); +--- a/include/net/neighbour.h ++++ b/include/net/neighbour.h +@@ -262,8 +262,10 @@ static inline bool neigh_key_eq128(const + const u32 *n32 = (const u32 *)n->primary_key; + const u32 *p32 = pkey; + +- return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) | +- (n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0; ++ return ((n32[0] ^ net_hdr_word(&p32[0])) | ++ (n32[1] ^ net_hdr_word(&p32[1])) | ++ (n32[2] ^ net_hdr_word(&p32[2])) | ++ (n32[3] ^ net_hdr_word(&p32[3]))) == 0; + } + + static inline struct neighbour *___neigh_lookup_noref( diff --git a/target/linux/arm64/Makefile b/target/linux/arm64/Makefile new file mode 100644 index 0000000..25ece9a --- /dev/null +++ b/target/linux/arm64/Makefile @@ -0,0 +1,28 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=aarch64 +BOARD:=arm64 +BOARDNAME:=ARMv8 multiplatform +FEATURES:=fpu ramdisk +CFLAGS:=-Os -pipe -fno-caller-saves +MAINTAINER:=Florian Fainelli + +KERNEL_PATCHVER:=4.1 + +DEVICE_TYPE:=developerboard + +include $(INCLUDE_DIR)/target.mk + +define Target/Description + Build multi-platform images for the ARMv8 instruction set architecture +endef + +KERNELNAME:=Image dtbs + +$(eval $(call BuildTarget)) diff --git a/target/linux/arm64/README b/target/linux/arm64/README new file mode 100644 index 0000000..0328ca1 --- /dev/null +++ b/target/linux/arm64/README @@ -0,0 +1,13 @@ +This multi-platform ARMv8 target can be used either with ARM Ltd.'s Foundation_V8 +fast-model doing the following: + +Foundation_v8 --image bin/arm64-eglibc/openwrt-arm64-vexpress-foundation.axf + +or you can also use QEMU: + +qemu-system-aarch64 -machine virt -cpu cortex-a57 -machine type=virt -nographic \ + -smp 1 -m 2048 \ + -kernel bin/arm64-eglibc/openwrt-arm64-qemu-virt-initramfs.Image \ + --append "console=ttyAMA0" + +and enjoy the system booting. diff --git a/target/linux/arm64/base-files/etc/inittab b/target/linux/arm64/base-files/etc/inittab new file mode 100644 index 0000000..d9d571e --- /dev/null +++ b/target/linux/arm64/base-files/etc/inittab @@ -0,0 +1,5 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +tts/0::askfirst:/bin/ash --login +ttyAMA0::askfirst:/bin/ash --login +tty1::askfirst:/bin/ash --login diff --git a/target/linux/arm64/config-default b/target/linux/arm64/config-default new file mode 100644 index 0000000..adb75c7 --- /dev/null +++ b/target/linux/arm64/config-default @@ -0,0 +1,318 @@ +CONFIG_64BIT=y +CONFIG_ACPI=y +# CONFIG_ACPI_CONTAINER is not set +# CONFIG_ACPI_CUSTOM_DSDT is not set +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_DOCK is not set +# CONFIG_ACPI_EC_DEBUGFS is not set +CONFIG_ACPI_GENERIC_GSI=y +# CONFIG_ACPI_PCI_SLOT is not set +# CONFIG_ACPI_PROCFS_POWER is not set +CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +# CONFIG_ARCH_EXYNOS7 is not set +# CONFIG_ARCH_FSL_LS2085A is not set +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SEATTLE is not set +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +# CONFIG_ARCH_SPRD is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARCH_THUNDER is not set +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZYNQMP is not set +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_64K_PAGES is not set +# CONFIG_ARM64_CRYPTO is not set +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_845719=y +# CONFIG_ARM64_PTDUMP is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V3=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ATOMIC64_SELFTEST=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AVERAGE=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLOCK_COMPAT=y +CONFIG_BOUNCE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BUILD_BIN2C=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLK_SP810=y +CONFIG_CLK_VEXPRESS_OSC=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyAMA0" +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_VERSATILE=y +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMPAT=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_COMPAT_OLD_SIGACTION=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_RMAP=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CUSE=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_DEFAULT_NOOP=y +CONFIG_DEVTMPFS=y +CONFIG_DTC=y +# CONFIG_EFI is not set +CONFIG_EXT4_FS=y +CONFIG_FAT_FS=y +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_SM750 is not set +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +# CONFIG_FSL_MC_BUS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_MBCACHE=y +CONFIG_FUSE_FS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_ACPI=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_GPIO_XGENE is not set +CONFIG_GRACE_PERIOD=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_RCU_GUP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HPET is not set +# CONFIG_HUGETLBFS is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_WORK=y +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_KVM_COMPAT=y +CONFIG_LIBFDT=y +CONFIG_LOCKD=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_VEXPRESS_SYSREG=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_MMC=y +CONFIG_MMC_ARMMMCI=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NFS_FS=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_BUS_ADDR_T_64BIT=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_LABEL=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_XGENE is not set +# CONFIG_PMIC_OPREGION is not set +CONFIG_PNP=y +CONFIG_PNPACPI=y +CONFIG_PNP_DEBUG_MESSAGES=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_VEXPRESS=y +# CONFIG_POWER_RESET_XGENE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PROFILING=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RFS_ACCEL=y +CONFIG_ROOT_NFS=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCSI=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_PROC_FS is not set +CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SMC91X=y +CONFIG_SMP=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SRCU=y +CONFIG_STOP_MACHINE=y +CONFIG_SUNRPC=y +# CONFIG_SWAP is not set +CONFIG_SWIOTLB=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_UID16=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_VEXPRESS_SYSCFG=y +CONFIG_VFAT_FS=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_BLK=y +# CONFIG_VIRTIO_CONSOLE is not set +CONFIG_VIRTIO_MMIO=y +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_NET=y +CONFIG_XPS=y diff --git a/target/linux/arm64/image/Makefile b/target/linux/arm64/image/Makefile new file mode 100644 index 0000000..cc04b18 --- /dev/null +++ b/target/linux/arm64/image/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Image/Prepare + -rm -rf $(KDIR)/linux-system.axf + cp $(LINUX_DIR)/arch/$(LINUX_KARCH)/boot/Image $(KDIR)/Image + $(MAKE) -C boot-wrapper clean + $(MAKE) -C boot-wrapper compile +endef + +define Build/Clean + $(MAKE) -C boot-wrapper clean +endef + +define Image/Build/QemuVirt + $(CP) $(KDIR)/Image $(BIN_DIR)/$(IMG_PREFIX)-qemu-virt.Image +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(CP) $(KDIR)/Image-initramfs $(BIN_DIR)/$(IMG_PREFIX)-qemu-virt-initramfs.Image +endif +endef + +define Image/Build/VexpressFoundation + $(CP) $(KDIR)/linux-system.axf $(BIN_DIR)/$(IMG_PREFIX)-vexpress-foundation.axf +endef + +define Image/BuildKernel + $(call Image/Build/QemuVirt) + $(call Image/Build/VexpressFoundation) +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +endef + +define Image/Build + $(call Image/Build/$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/arm64/image/boot-wrapper/Makefile b/target/linux/arm64/image/boot-wrapper/Makefile new file mode 100644 index 0000000..fa39708 --- /dev/null +++ b/target/linux/arm64/image/boot-wrapper/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=aarch64-boot-wrapper +PKG_VERSION:=2013-01-10 +PKG_RELEASE:=$(PKG_SOURCE_VERSION) + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/boot-wrapper-aarch64.git +PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION) +PKG_SOURCE_VERSION:=c51dde817b5ed5b8f741b67ac51bd67bd87b4a2a +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.gz +PKG_MAINTAINER:=Florian Fainelli + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk +include $(INCLUDE_DIR)/image.mk + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) \ + KERNEL="../Image" \ + DTC="$(LINUX_DIR)/scripts/dtc/dtc" \ + FDT_SRC="$(LINUX_DIR)/arch/$(LINUX_KARCH)/boot/dts/arm/foundation-v8.dts" \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + BOOTARGS="console=ttyAMA0 earlyprintk" +endef + +define Build/InstallDev + $(CP) $(PKG_BUILD_DIR)/linux-system.axf $(KDIR)/linux-system.axf +endef + +$(eval $(call Build/DefaultTargets)) diff --git a/target/linux/at91/Makefile b/target/linux/at91/Makefile new file mode 100644 index 0000000..e1c771a --- /dev/null +++ b/target/linux/at91/Makefile @@ -0,0 +1,22 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=at91 +MAINTAINER:=Claudio Mignanti +BOARDNAME:=Atmel AT91 +FEATURES:=squashfs targz ext2 usb usbgadget ubifs +SUBTARGETS:=legacy sama5d3 + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += kmod-usb-ohci kmod-at91-udc kmod-usb-eth-gadget + +$(eval $(call BuildTarget)) diff --git a/target/linux/at91/base-files.mk b/target/linux/at91/base-files.mk new file mode 100644 index 0000000..d6682bd --- /dev/null +++ b/target/linux/at91/base-files.mk @@ -0,0 +1,5 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef + + diff --git a/target/linux/at91/base-files/etc/config/firewall b/target/linux/at91/base-files/etc/config/firewall new file mode 100644 index 0000000..f9c860e --- /dev/null +++ b/target/linux/at91/base-files/etc/config/firewall @@ -0,0 +1,6 @@ +config defaults + option syn_flood 1 + option input ACCEPT + option output ACCEPT + option forward REJECT + diff --git a/target/linux/at91/base-files/etc/config/network b/target/linux/at91/base-files/etc/config/network new file mode 100644 index 0000000..a99b60d --- /dev/null +++ b/target/linux/at91/base-files/etc/config/network @@ -0,0 +1,20 @@ +config interface loopback + option ifname lo + option proto static + option ipaddr 127.0.0.1 + option netmask 255.0.0.0 + +config interface lan + option ifname eth0 + option type none + option proto static + option ipaddr 192.168.1.1 + option netmask 255.255.255.0 + +config interface debug + option ifname usb0 + option type none + option proto static + option ipaddr 172.18.0.18 + option netmask 255.255.255.0 + diff --git a/target/linux/at91/base-files/etc/uci-defaults/02_network b/target/linux/at91/base-files/etc/uci-defaults/02_network new file mode 100755 index 0000000..5df138c --- /dev/null +++ b/target/linux/at91/base-files/etc/uci-defaults/02_network @@ -0,0 +1,29 @@ +#!/bin/sh +# +# Copyright (C) 2014 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/at91.sh + +ucidef_set_interface_loopback + +case "$(at91_board_name)" in + +sama5d3_xplained) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; + +*) + ucidef_set_interface_lan "eth0" + ;; + +esac + +uci commit network + +exit 0 diff --git a/target/linux/at91/base-files/lib/at91.sh b/target/linux/at91/base-files/lib/at91.sh new file mode 100755 index 0000000..e395646 --- /dev/null +++ b/target/linux/at91/base-files/lib/at91.sh @@ -0,0 +1,90 @@ +#!/bin/sh +# +# Copyright (C) 2014 OpenWrt.org +# + +AT91_BOARD_NAME= +AT91_MODEL= + +at91_board_detect() { + local machine + local name + + machine=$(cat /proc/device-tree/model) + + case "$machine" in + *"Atmel at91sam9263ek") + name="at91sam9263ek" + ;; + *"Atmel AT91SAM9G15-EK") + name="at91sam9g15ek" + ;; + *"Atmel at91sam9g20ek") + name="at91sam9g20ek" + ;; + *"Atmel at91sam9g20ek 2 mmc") + name="at91sam9g20ek_2mmc" + ;; + *"Atmel AT91SAM9G25-EK") + name="at91sam9g25ek" + ;; + *"Atmel AT91SAM9G35-EK") + name="at91sam9g35ek" + ;; + *"Atmel AT91SAM9M10G45-EK") + name="at91sam9m10g45ek" + ;; + *"Atmel AT91SAM9X25-EK") + name="at91sam9x25ek" + ;; + *"Atmel AT91SAM9X35-EK") + name="at91sam9x35ek" + ;; + *"SAMA5D3 Xplained") + name="sama5d3_xplained" + ;; + *"CalAmp LMU5000") + name="lmu5000" + ;; + *"Calao TNY A9260") + name="tny_a9260" + ;; + *"Calao TNY A9263") + name="tny_a9263" + ;; + *"Calao TNY A9G20") + name="tny_a9g20" + ;; + *"Calao USB A9260") + name="usb_a9260" + ;; + *"Calao USB A9263") + name="usb_a9263" + ;; + *"Calao USB A9G20") + name="usb_a9g20" + ;; + *"Ethernut 5") + name="ethernut5" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$AT91_BOARD_NAME" ] && AT91_BOARD_NAME="$name" + [ -z "$AT91_MODEL" ] && AT91_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$AT91_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$AT91_MODEL" > /tmp/sysinfo/model +} + +at91_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -n "$name" ] || name="unknown" + + echo "$name" +} diff --git a/target/linux/at91/base-files/lib/preinit/03_preinit_do_at91.sh b/target/linux/at91/base-files/lib/preinit/03_preinit_do_at91.sh new file mode 100644 index 0000000..5c98101 --- /dev/null +++ b/target/linux/at91/base-files/lib/preinit/03_preinit_do_at91.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_at91() { + . /lib/at91.sh + + at91_board_detect +} + +boot_hook_add preinit_main do_at91 diff --git a/target/linux/at91/config-default b/target/linux/at91/config-default new file mode 100644 index 0000000..8faced7 --- /dev/null +++ b/target/linux/at91/config-default @@ -0,0 +1,230 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_AT91=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_NR_BANKS=8 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_AT91SAM9X_WATCHDOG=y +CONFIG_AT91_PMC_UNIT=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_AT91_SAM9G45_RESET=y +CONFIG_AT91_SAM9_ALT_RESET=y +CONFIG_AT91_SAM9_TIME=y +CONFIG_AT91_TIMER_HZ=100 +CONFIG_ATAGS=y +# CONFIG_ATMEL_TCLIB is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CONFIGFS_FS=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_LZO=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +CONFIG_DTC=y +CONFIG_EXT4_FS=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_MBCACHE=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_AT91_DBGU0=y +CONFIG_HAVE_AT91_DBGU1=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FB_ATMEL=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HZ_PERIODIC=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_JBD2=y +CONFIG_JFFS2_ZLIB=y +CONFIG_KTIME_SCALAR=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_M25PXX_PREFER_SMALL_SECTOR_ERASE=y +CONFIG_M25PXX_USE_FAST_READ=y +CONFIG_MACB=y +CONFIG_MACH_AT91SAM9_DT=y +CONFIG_MDIO_BOARDINFO=y +# CONFIG_MII is not set +CONFIG_MICREL_PHY=y +CONFIG_MMC=y +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_OF_PARTS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_SM_COMMON is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_MACH_GPIO_H=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NLS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DEVICE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCONF=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINMUX=y +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AT91_POWEROFF=y +CONFIG_POWER_RESET_AT91_RESET=y +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +# CONFIG_PREEMPT_RCU is not set +CONFIG_PROC_DEVICETREE=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_AT91RM9200 is not set +# CONFIG_RTC_DRV_AT91SAM9 is not set +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_ATMEL=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_STAGING is not set +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +# CONFIG_UBIFS_FS_XZ is not set +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UIDGID_CONVERTED=y +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +# CONFIG_USB_ARCH_HAS_XHCI is not set +# CONFIG_USB_ATMEL_USBA is not set +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_WLAN is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/at91/files/arch/arm/boot/dts/at91-q5xr5.dts b/target/linux/at91/files/arch/arm/boot/dts/at91-q5xr5.dts new file mode 100644 index 0000000..2aa04ca --- /dev/null +++ b/target/linux/at91/files/arch/arm/boot/dts/at91-q5xr5.dts @@ -0,0 +1,193 @@ +/* + * q5xr5.dts - Device Tree file for Exegin Q5xR5 board + * + * Copyright (C) 2014 Owen Kirby + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9g20.dtsi" + +/ { + model = "Exegin Q5x (rev5)"; + compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2"; + }; + + memory { + reg = <0x20000000 0x0>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <18432000>; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + pinctrl@fffff400 { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = <2 1 0x2 0x0>; /* PC1 periph B */ + }; + pinctrl_spi0_npcs0: spi0_npcs0 { + atmel,pins = <0 3 0x1 0x0>; /* PA3 periph A */ + }; + pinctrl_spi0_npcs1: spi0_npcs1 { + atmel,pins = <2 11 0x2 0x0>; /* PC11 periph B */ + }; + pinctrl_spi1_npcs0: spi1_npcs0 { + atmel,pins = <1 3 0x1 0x0>; /* PB3 periph A */ + }; + pinctrl_spi1_npcs1: spi1_npcs1 { + atmel,pins = <2 5 0x2 0x0>; /* PC5 periph B */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <0 0 0x1 0x0 /* PA0 periph A SPI0_MISO pin */ + 0 1 0x1 0x0 /* PA1 periph A SPI0_MOSI pin */ + 0 2 0x1 0x0>; /* PA2 periph A SPI0_SPCK pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + <1 0 0x1 0x0 /* PB0 periph A SPI1_MISO pin */ + 1 1 0x1 0x0 /* PB1 periph A SPI1_MOSI pin */ + 1 2 0x1 0x0>; /* PB2 periph A SPI1_SPCK pin */ + }; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "mii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + spi0: spi@fffc8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffc8000 0x200>; + interrupts = <12 4 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + status = "okay"; + cs-gpios = <&pioA 3 0>, <&pioC 11 1>, <0>, <0>; + + m25p80@0 { + compatible = "sst,sst25vf040b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + at91boot@0 { + label = "at91boot"; + reg = <0x0 0x4000>; + }; + uenv@4000 { + label = "uboot-env"; + reg = <0x4000 0x4000>; + }; + uboot@8000 { + label = "uboot"; + reg = <0x8000 0x3E000>; + }; + }; + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <1>; + }; + }; + spi1: spi@fffcc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xfffcc000 0x200>; + interrupts = <13 4 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&pioB 3 0>, <&pioC 5 1>, <0>, <0>; + status = "okay"; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <0>; + }; + spidev@1 { + compatible = "spidev"; + spi-max-frequency = <2000000>; + reg = <1>; + }; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + flash@10000000 { + compatible = "cfi-flash"; + bank-width = <2>; + reg = <0x10000000 0x00800000>; + #address-cells = <1>; + #size-cells = <1>; + + kernel@0 { + label = "kernel"; + reg = <0x0 0x200000>; + }; + rootfs@200000 { + label = "rootfs"; + reg = <0x200000 0x600000>; + }; + }; +}; diff --git a/target/linux/at91/files/arch/arm/boot/dts/lmu5000.dts b/target/linux/at91/files/arch/arm/boot/dts/lmu5000.dts new file mode 100644 index 0000000..921d44b --- /dev/null +++ b/target/linux/at91/files/arch/arm/boot/dts/lmu5000.dts @@ -0,0 +1,125 @@ +/* + * lmu5000.dst - Device Tree file for CalAmp LMU5000 board + * + * Copyright (C) 2013 Adam Porter + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9g20.dtsi" + +/ { + model = "CalAmp LMU5000"; + compatible = "calamp,lmu5000", "atmel,at91sam9g20", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 rootfstype=jffs2"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + pinctrl@fffff400 { + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + <2 1 0x2 0x0>; /* PC1 periph B */ + }; + + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart2: serial@fffb8000 { + status = "okay"; + }; + + uart0: serial@fffd4000 { + status = "okay"; + }; + + uart1: serial@fffd8000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "mii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 0>; + status = "okay"; + }; + + ssc0: ssc@fffbc000 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + kernel@0 { + label = "kernel"; + reg = <0x0 0x400000>; + }; + + rootfs@400000 { + label = "rootfs"; + reg = <0x400000 0x3C00000>; + }; + + user1@4000000 { + label = "user1"; + reg = <0x4000000 0x2000000>; + }; + + user2@6000000 { + label = "user2"; + reg = <0x6000000 0x2000000>; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; +}; diff --git a/target/linux/at91/files/drivers/mtd/at91part.c b/target/linux/at91/files/drivers/mtd/at91part.c new file mode 100644 index 0000000..31f3bbd --- /dev/null +++ b/target/linux/at91/files/drivers/mtd/at91part.c @@ -0,0 +1,122 @@ +/* + * + * Copyright (C) 2007 OpenWrt.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Atmel AT91 flash partition table. (Modified by Hamish Guthrie). + * Based on ar7 map by Felix Fietkau. + * + */ + +#include +#include + +#include +#include +#include +#include + +static struct mtd_partition at91_parts[6]; + +static int create_mtd_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + unsigned long origin) +{ + unsigned int offset, len; + unsigned int pre_size = 0x42000, root_max = 0x362400; + unsigned char buf[512]; + struct squashfs_super_block *sb = (struct squashfs_super_block *) buf; + + printk("Parsing AT91 partition map...\n"); + + at91_parts[0].name = "loaders"; + at91_parts[0].offset = 0; + at91_parts[0].size = 0x21000; + at91_parts[0].mask_flags = MTD_WRITEABLE; + + at91_parts[1].name = "ubparams"; + at91_parts[1].offset = 0x21000; + at91_parts[1].size = 0x8400; + at91_parts[1].mask_flags = 0; + + at91_parts[2].name = "kernel"; + at91_parts[2].offset = pre_size; + at91_parts[2].size = 0; + at91_parts[2].mask_flags = 0; + + at91_parts[3].name = "rootfs"; + at91_parts[3].offset = 0; + at91_parts[3].size = 0; + at91_parts[3].mask_flags = 0; + + for(offset = pre_size; offset < root_max; offset += master->erasesize) { + + memset(&buf, 0xe5, sizeof(buf)); + + if (master->read(master, offset, sizeof(buf), &len, buf) || len != sizeof(buf)) + break; + + if (*((__u32 *) buf) == SQUASHFS_MAGIC) { + printk(KERN_INFO "%s: Filesystem type: squashfs, size=0x%x\n", + master->name, (u32) sb->bytes_used); + + at91_parts[3].size = sb->bytes_used; + at91_parts[3].offset = offset; + len = at91_parts[3].offset + at91_parts[3].size; + len = ((len / (master->erasesize * 8)) + 1) * master->erasesize * 8; + at91_parts[3].size = len - at91_parts[3].offset; + at91_parts[2].size = offset - at91_parts[2].offset; + break; + } + } + + if (at91_parts[3].size == 0) { + printk(KERN_NOTICE "%s: Couldn't find root filesystem\n", master->name); + return -1; + } + + at91_parts[4].name = "rootfs_data"; + at91_parts[4].offset = root_max; + at91_parts[4].size = master->size - root_max; + at91_parts[4].mask_flags = 0; + + at91_parts[5].name = "complete"; + at91_parts[5].offset = 0; + at91_parts[5].size = master->size; + at91_parts[5].mask_flags = 0; + + *pparts = at91_parts; + return 6; +} + +static struct mtd_part_parser at91_parser = { + .owner = THIS_MODULE, + .parse_fn = create_mtd_partitions, + .name = "at91part", +}; + +static int __init at91_parser_init(void) +{ + register_mtd_parser(&at91_parser); + + return 0; +} + +module_init(at91_parser_init); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Felix Fietkau, Eugene Konev, Hamish Guthrie"); +MODULE_DESCRIPTION("MTD partitioning for Atmel at91"); diff --git a/target/linux/at91/image/Config.in b/target/linux/at91/image/Config.in new file mode 100644 index 0000000..54a501d --- /dev/null +++ b/target/linux/at91/image/Config.in @@ -0,0 +1,37 @@ +config AT91_DFBOOT + bool "Build dataflashboot loader" + depends on TARGET_at91 + default n + +config AT91_UBOOT + bool "Build U-Boot bootloader" + depends on TARGET_at91 + default n + +config UBOOT_TARGET + string "U-Boot target board" + depends on AT91_UBOOT + default "netusg20" + help + For all supported boards there are ready-to-use default + configurations available; just type "". + +config UBOOT_IPADDR + string "IP Address for U-Boot" + depends on AT91_UBOOT + default "192.168.0.178" + help + IP address of device to be used in U-Boot + +config UBOOT_SERVERIP + string "IP Address of TFTP server" + depends on AT91_UBOOT + default "192.168.0.232" + help + IP address of TFTP server for U-Boot + +config FLEXIBITY_ROOT + bool "Build Flexibity RootFS (with embedded kernel)" + depends on TARGET_at91_flexibity + default n + diff --git a/target/linux/at91/image/Makefile b/target/linux/at91/image/Makefile new file mode 100644 index 0000000..4e472f2 --- /dev/null +++ b/target/linux/at91/image/Makefile @@ -0,0 +1,105 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +UBIFS_OPTS = -F -m 2048 -e 126KiB -c 2048 -U +UBI_OPTS = -m 2048 -p 128KiB -s 512 + +AT91SAMA5D3XPLAINED_UBIFS_OPTS = -m 2048 -e 124KiB -c 2048 +AT91SAMA5D3XPLAINED_UBI_OPTS = -m 2048 -p 128KiB -s 2048 + +define Build/Clean + $(MAKE) -C u-boot clean +endef + +define Build/Compile + if [ $(CONFIG_AT91_UBOOT) ]; then \ + $(MAKE) -C u-boot compile; \ + fi +endef + +define Image/Prepare + cp $(LINUX_DIR)/arch/arm/boot/Image $(KDIR)/Image + cp $(LINUX_DIR)/arch/arm/boot/zImage $(KDIR)/zImage +endef + +define MkuImageDtb + cat $(KDIR)/zImage $(DTS_DIR)/$(2).dtb > $(KDIR)/zImage-$(1) + mkimage -A arm -T kernel -C none -a 0x20008000 -e 0x20008000 \ + -n "OpenWrt ARM $(LINUX_VERSION)" \ + -d $(KDIR)/zImage-$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage +endef + +define MkOftree + cp -u $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage + cp $(DTS_DIR)/$(2).dtb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-oftree.dtb +endef + +# Atmel +Image/Build/Kernel/AT91SAM9263EK=$(call MkuImageDtb,9263ek,at91sam9263ek) +Image/Build/Kernel/AT91SAM9G15EK=$(call MkuImageDtb,9g15ek,at91sam9g15ek) +Image/Build/Kernel/AT91SAM9G20EK=$(call MkOftree,9g20ek,at91sam9g20ek) +Image/Build/Kernel/AT91SAM9G20EK-2MMC=$(call MkOftree,9g20ek_2mmc,at91sam9g20ek_2mmc) +Image/Build/Kernel/AT91SAM9G25EK=$(call MkuImageDtb,9g25ek,at91sam9g25ek) +Image/Build/Kernel/AT91SAM9G35EK=$(call MkuImageDtb,9g35ek,at91sam9g35ek) +Image/Build/Kernel/AT91SAM9M10G45EK=$(call MkuImageDtb,9m10g45ek,at91sam9m10g45ek) +Image/Build/Kernel/AT91SAM9X25EK=$(call MkuImageDtb,9x25ek,at91sam9x25ek) +Image/Build/Kernel/AT91SAM9X35EK=$(call MkuImageDtb,9x35ek,at91sam9x35ek) +Image/Build/Kernel/AT91SAMA5D3XPLAINED=$(call MkuImageDtb,sama5,at91-sama5d3_xplained) +# CalAmp +Image/Build/Kernel/LMU5000=$(call MkuImageDtb,lmu5000,lmu5000) +# Calao +Image/Build/Kernel/TNYA9260=$(call MkuImageDtb,tny_a9260,tny_a9260) +Image/Build/Kernel/TNYA9263=$(call MkuImageDtb,tny_a9263,tny_a9263) +Image/Build/Kernel/TNYA9G20=$(call MkuImageDtb,tny_a9g20,tny_a9g20) +Image/Build/Kernel/USBA9260=$(call MkuImageDtb,usb_a9260,usb_a9260) +Image/Build/Kernel/USBA9263=$(call MkuImageDtb,usb_a9263,usb_a9263) +Image/Build/Kernel/USBA9G20=$(call MkuImageDtb,usb_a9g20,usb_a9g20) +# Ethernut +Image/Build/Kernel/ETHERNUT5=$(call MkuImageDtb,ethernut5,ethernut5) +# Exegin +Image/Build/Kernel/Q5XR5=$(call MkOftree,q5xr5,at91-q5xr5) + + +define Image/Build/Kernel/Default + $(call Image/Build/Kernel/AT91SAM9263EK) + $(call Image/Build/Kernel/AT91SAM9G15EK) + $(call Image/Build/Kernel/AT91SAM9G20EK) + $(call Image/Build/Kernel/AT91SAM9G20EK-2MMC) + $(call Image/Build/Kernel/AT91SAM9G25EK) + $(call Image/Build/Kernel/AT91SAM9G35EK) + $(call Image/Build/Kernel/AT91SAM9M10G45EK) + $(call Image/Build/Kernel/AT91SAM9X25EK) + $(call Image/Build/Kernel/AT91SAM9X35EK) + $(call Image/Build/Kernel/AT91SAMA5D3XPLAINED) + $(call Image/Build/Kernel/LMU5000) + $(call Image/Build/Kernel/TNYA9260) + $(call Image/Build/Kernel/TNYA9263) + $(call Image/Build/Kernel/TNYA9G20) + $(call Image/Build/Kernel/USBA9260) + $(call Image/Build/Kernel/USBA9263) + $(call Image/Build/Kernel/USBA9G20) + $(call Image/Build/Kernel/ETHERNUT5) + $(call Image/Build/Kernel/Q5XR5) +endef + +define Image/BuildKernel + mkimage -A arm -T kernel -C none -a 0x20008000 -e 0x20008000 -n linux-2.6 \ + -d $(KDIR)/Image $(BIN_DIR)/$(IMG_PREFIX)-uImage + if [ $(CONFIG_FLEXIBITY_ROOT) ]; then \ + $(INSTALL_BIN) $(BIN_DIR)/$(IMG_PREFIX)-uImage $(TARGET_DIR)/uImage ; \ + fi + $(call Image/Build/Kernel/$(PROFILE)) +endef + +define Image/Build + $(call Image/Build/$(1)) + cp $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/at91/image/dfboot/Makefile b/target/linux/at91/image/dfboot/Makefile new file mode 100644 index 0000000..91a603d --- /dev/null +++ b/target/linux/at91/image/dfboot/Makefile @@ -0,0 +1,35 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=dfboot +PKG_VERSION:=0.1 +PKG_RELEASE:=1 + +PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME) + +include $(INCLUDE_DIR)/package.mk + +define Build/Prepare + mkdir -p $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ +endef + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) \ + $(TARGET_CONFIGURE_OPTS) \ + CFLAGS="$(TARGET_CFLAGS)" \ + LDFLAGS="$(LIBGCC_S)" +endef + +define Build/InstallDev + dd if=$(PKG_BUILD_DIR)/binary/dfboot.bin of=$(PKG_BUILD_DIR)/binary/dfboot.block bs=32k count=1 conv=sync +endef + +$(eval $(call Build/DefaultTargets)) diff --git a/target/linux/at91/image/dfboot/src/Makefile b/target/linux/at91/image/dfboot/src/Makefile new file mode 100644 index 0000000..ff92e0d --- /dev/null +++ b/target/linux/at91/image/dfboot/src/Makefile @@ -0,0 +1,94 @@ +# Makefile for DataFlashBoot.bin +# Must use toolchain with H/W FLoating Point + +BASENAME=dfboot +BINNAME=$(BASENAME).bin +OUTNAME=$(BASENAME).out +LSSNAME=$(BASENAME).lss +MAPNAME=$(BASENAME).map + +BASENAME2=dfbptest +BINNAME2=$(BASENAME2).bin +OUTNAME2=$(BASENAME2).out +LSSNAME2=$(BASENAME2).lss +MAPNAME2=$(BASENAME2).map + +INCPATH=include + +CFLAGS_LOCAL=-Os -Wall -I$(INCPATH) +BUILD=$(CC) $(CFLAGS) $(CFLAGS_LOCAL) + +LDFLAGS+=-T elf32-littlearm.lds -Ttext 0 +LINK=$(LD) $(LDFLAGS) + +OBJS=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\ + objs/div0.o objs/init.o objs/main.o objs/asm_isr.o objs/asm_mci_isr.o\ + objs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o + +OBJS2=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\ + objs/div0.o objs/init.o objs/ptmain.o objs/asm_isr.o objs/asm_mci_isr.o\ + objs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o + +I=config.h com.h dataflash.h embedded_services.h main.h stdio.h include/AT91RM9200.h include/lib_AT91RM9200.h + +all:clean $(BASENAME) $(BASENAME2) + +$(BASENAME): $(OBJS) + $(LINK) -n -o $(OUTNAME) $(OBJS) + $(OBJCOPY) $(OUTNAME) -O binary $(BINNAME) + $(OBJDUMP) -h -s $(OUTNAME) > $(LSSNAME) + $(NM) -n $(OUTNAME) | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)' > $(MAPNAME) + cp $(BINNAME) binary + +$(BASENAME2): $(OBJS2) + $(LINK) -n -o $(OUTNAME2) $(OBJS2) + $(OBJCOPY) $(OUTNAME2) -O binary $(BINNAME2) + $(OBJDUMP) -h -s $(OUTNAME2) > $(LSSNAME2) + $(NM) -n $(OUTNAME2) | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)' > $(MAPNAME2) + cp $(BINNAME2) binary + +# C objects here +objs/at45.o: at45.c $(I) + $(BUILD) -c -o objs/at45.o at45.c +objs/com.o: com.c $(I) + $(BUILD) -c -o objs/com.o com.c +objs/dataflash.o: dataflash.c $(I) + $(BUILD) -c -o objs/dataflash.o dataflash.c +objs/mci_device.o: mci_device.c $(I) + $(BUILD) -c -o objs/mci_device.o mci_device.c +objs/div0.o: div0.c $(I) + $(BUILD) -c -o objs/div0.o div0.c +objs/init.o: init.c $(I) + $(BUILD) -c -o objs/init.o init.c +objs/main.o: main.c $(I) + $(BUILD) -c -o objs/main.o main.c +objs/ptmain.o: main.c $(I) + $(BUILD) -c -D PRODTEST -o objs/ptmain.o main.c + +# ASM objects here +objs/asm_isr.o: asm_isr.S + $(BUILD) -c -o objs/asm_isr.o asm_isr.S +objs/asm_mci_isr.o: asm_mci_isr.S + $(BUILD) -c -o objs/asm_mci_isr.o asm_mci_isr.S +objs/cstartup_ram.o: cstartup_ram.S + $(BUILD) -c -o objs/cstartup_ram.o cstartup_ram.S +objs/jump.o: jump.S + $(BUILD) -c -o objs/jump.o jump.S +objs/_udivsi3.o: _udivsi3.S + $(BUILD) -c -o objs/_udivsi3.o _udivsi3.S +objs/_umodsi3.o: _umodsi3.S + $(BUILD) -c -o objs/_umodsi3.o _umodsi3.S + +install: $(BINNAME) $(BINNAME2) + cp $(BINNAME) binary + cp $(BINNAME2) binary + +clean: + rm -f *~ + rm -f objs/* + rm -f *.out + rm -f *.bin + rm -f *.lss + rm -f *.map + rm -f .unpacked + mkdir -p objs diff --git a/target/linux/at91/image/dfboot/src/_udivsi3.S b/target/linux/at91/image/dfboot/src/_udivsi3.S new file mode 100644 index 0000000..2cdcd48 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/_udivsi3.S @@ -0,0 +1,77 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +dividend .req r0 +divisor .req r1 +result .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __udivsi3 + .type __udivsi3 ,function + .align 0 + __udivsi3 : + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + mov result, #0 + cmp dividend, divisor + bcc Lgot_result +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions, and note which bits + @ are done in the result. On the final pass, this may subtract + @ too much from the dividend, but the result will be ok, since the + @ "bit" will have been shifted out at the bottom. + cmp dividend, divisor + subcs dividend, dividend, divisor + orrcs result, result, curbit + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs result, result, curbit, lsr #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs result, result, curbit, lsr #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs result, result, curbit, lsr #3 + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 +Lgot_result: + mov r0, result + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __udivsi3 , . - __udivsi3 +/* # 235 "libgcc1.S" */ +/* # 320 "libgcc1.S" */ +/* # 421 "libgcc1.S" */ +/* # 433 "libgcc1.S" */ +/* # 456 "libgcc1.S" */ +/* # 500 "libgcc1.S" */ +/* # 580 "libgcc1.S" */ diff --git a/target/linux/at91/image/dfboot/src/_umodsi3.S b/target/linux/at91/image/dfboot/src/_umodsi3.S new file mode 100644 index 0000000..e4aebe8 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/_umodsi3.S @@ -0,0 +1,88 @@ +/* # 1 "libgcc1.S" */ +@ libgcc1 routines for ARM cpu. +@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) +/* # 145 "libgcc1.S" */ +dividend .req r0 +divisor .req r1 +overdone .req r2 +curbit .req r3 +/* ip .req r12 */ +/* sp .req r13 */ +/* lr .req r14 */ +/* pc .req r15 */ + .text + .globl __umodsi3 + .type __umodsi3 ,function + .align 0 + __umodsi3 : + cmp divisor, #0 + beq Ldiv0 + mov curbit, #1 + cmp dividend, divisor + movcc pc, lr +Loop1: + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. + cmp divisor, #0x10000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #4 + movcc curbit, curbit, lsl #4 + bcc Loop1 +Lbignum: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. + cmp divisor, #0x80000000 + cmpcc divisor, dividend + movcc divisor, divisor, lsl #1 + movcc curbit, curbit, lsl #1 + bcc Lbignum +Loop3: + @ Test for possible subtractions. On the final pass, this may + @ subtract too much from the dividend, so keep track of which + @ subtractions are done, we can fix them up afterwards... + mov overdone, #0 + cmp dividend, divisor + subcs dividend, dividend, divisor + cmp dividend, divisor, lsr #1 + subcs dividend, dividend, divisor, lsr #1 + orrcs overdone, overdone, curbit, ror #1 + cmp dividend, divisor, lsr #2 + subcs dividend, dividend, divisor, lsr #2 + orrcs overdone, overdone, curbit, ror #2 + cmp dividend, divisor, lsr #3 + subcs dividend, dividend, divisor, lsr #3 + orrcs overdone, overdone, curbit, ror #3 + mov ip, curbit + cmp dividend, #0 @ Early termination? + movnes curbit, curbit, lsr #4 @ No, any more bits to do? + movne divisor, divisor, lsr #4 + bne Loop3 + @ Any subtractions that we should not have done will be recorded in + @ the top three bits of "overdone". Exactly which were not needed + @ are governed by the position of the bit, stored in ip. + @ If we terminated early, because dividend became zero, + @ then none of the below will match, since the bit in ip will not be + @ in the bottom nibble. + ands overdone, overdone, #0xe0000000 + moveq pc, lr @ No fixups needed + tst overdone, ip, ror #3 + addne dividend, dividend, divisor, lsr #3 + tst overdone, ip, ror #2 + addne dividend, dividend, divisor, lsr #2 + tst overdone, ip, ror #1 + addne dividend, dividend, divisor, lsr #1 + mov pc, lr +Ldiv0: + str lr, [sp, #-4]! + bl __div0 (PLT) + mov r0, #0 @ about as wrong as it could be + ldmia sp!, {pc} + .size __umodsi3 , . - __umodsi3 +/* # 320 "libgcc1.S" */ +/* # 421 "libgcc1.S" */ +/* # 433 "libgcc1.S" */ +/* # 456 "libgcc1.S" */ +/* # 500 "libgcc1.S" */ +/* # 580 "libgcc1.S" */ diff --git a/target/linux/at91/image/dfboot/src/asm_isr.S b/target/linux/at91/image/dfboot/src/asm_isr.S new file mode 100644 index 0000000..8d1d52e --- /dev/null +++ b/target/linux/at91/image/dfboot/src/asm_isr.S @@ -0,0 +1,75 @@ +#include "AT91RM9200_inc.h" + +#define ARM_MODE_USER 0x10 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_ABORT 0x17 +#define ARM_MODE_UNDEF 0x1B +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 +#define T_BIT 0x20 + + +/* ----------------------------------------------------------------------------- + AT91F_ASM_SPI_Handler + --------------------- + Handler called by the AIC + + Save context + Call C handler + Restore context + ----------------------------------------------------------------------------- */ + +.global AT91F_ST_ASM_HANDLER + +AT91F_ST_ASM_HANDLER: +/* Adjust and save LR_irq in IRQ stack */ + sub r14, r14, #4 + stmfd sp!, {r14} + +/* Write in the IVR to support Protect Mode + No effect in Normal Mode + De-assert the NIRQ and clear the source in Protect Mode */ + ldr r14, =AT91C_BASE_AIC + str r14, [r14, #AIC_IVR] + +/* Save SPSR and r0 in IRQ stack */ + mrs r14, SPSR + stmfd sp!, {r0, r14} + +/* Enable Interrupt and Switch in SYS Mode */ + mrs r0, CPSR + bic r0, r0, #I_BIT + orr r0, r0, #ARM_MODE_SYS + msr CPSR_c, r0 + +/* Save scratch/used registers and LR in User Stack */ + stmfd sp!, { r1-r3, r12, r14} + + ldr r1, =AT91F_ST_HANDLER + mov r14, pc + bx r1 + +/* Restore scratch/used registers and LR from User Stack */ + ldmia sp!, { r1-r3, r12, r14} + +/* Disable Interrupt and switch back in IRQ mode */ + mrs r0, CPSR + bic r0, r0, #ARM_MODE_SYS + orr r0, r0, #I_BIT | ARM_MODE_IRQ + msr CPSR_c, r0 + +/* Mark the End of Interrupt on the AIC */ + ldr r0, =AT91C_BASE_AIC + str r0, [r0, #AIC_EOICR] + +/* Restore SPSR_irq and r0 from IRQ stack */ + ldmia sp!, {r0, r14} + msr SPSR_cxsf, r14 + +/* Restore adjusted LR_irq from IRQ stack directly in the PC */ + ldmia sp!, {pc}^ + diff --git a/target/linux/at91/image/dfboot/src/asm_mci_isr.S b/target/linux/at91/image/dfboot/src/asm_mci_isr.S new file mode 100644 index 0000000..0f66fc0 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/asm_mci_isr.S @@ -0,0 +1,75 @@ +#include + +#define ARM_MODE_USER 0x10 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_ABORT 0x17 +#define ARM_MODE_UNDEF 0x1B +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 +#define T_BIT 0x20 + + +/* ----------------------------------------------------------------------------- + AT91F_ASM_MCI_Handler + --------------------- + Handler called by the AIC + + Save context + Call C handler + Restore context + ----------------------------------------------------------------------------- */ + +.global AT91F_ASM_MCI_Handler + +AT91F_ASM_MCI_Handler: +/* Adjust and save LR_irq in IRQ stack */ + sub r14, r14, #4 + stmfd sp!, {r14} + +/* Write in the IVR to support Protect Mode + No effect in Normal Mode + De-assert the NIRQ and clear the source in Protect Mode */ + ldr r14, =AT91C_BASE_AIC + str r14, [r14, #AIC_IVR] + +/* Save SPSR and r0 in IRQ stack */ + mrs r14, SPSR + stmfd sp!, {r0, r14} + +/* Enable Interrupt and Switch in SYS Mode */ + mrs r0, CPSR + bic r0, r0, #I_BIT + orr r0, r0, #ARM_MODE_SYS + msr CPSR_c, r0 + +/* Save scratch/used registers and LR in User Stack */ + stmfd sp!, { r1-r3, r12, r14} + + ldr r1, =AT91F_MCI_Handler + mov r14, pc + bx r1 + +/* Restore scratch/used registers and LR from User Stack */ + ldmia sp!, { r1-r3, r12, r14} + +/* Disable Interrupt and switch back in IRQ mode */ + mrs r0, CPSR + bic r0, r0, #ARM_MODE_SYS + orr r0, r0, #I_BIT | ARM_MODE_IRQ + msr CPSR_c, r0 + +/* Mark the End of Interrupt on the AIC */ + ldr r0, =AT91C_BASE_AIC + str r0, [r0, #AIC_EOICR] + +/* Restore SPSR_irq and r0 from IRQ stack */ + ldmia sp!, {r0, r14} + msr SPSR_cxsf, r14 + +/* Restore adjusted LR_irq from IRQ stack directly in the PC */ + ldmia sp!, {pc}^ + diff --git a/target/linux/at91/image/dfboot/src/at45.c b/target/linux/at91/image/dfboot/src/at45.c new file mode 100644 index 0000000..8830d7e --- /dev/null +++ b/target/linux/at91/image/dfboot/src/at45.c @@ -0,0 +1,595 @@ +/*---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + *---------------------------------------------------------------------------- + * The software is delivered "AS IS" without warranty or condition of any + * kind, either express, implied or statutory. This includes without + * limitation any warranty or condition with respect to merchantability or + * fitness for any particular purpose, or against the infringements of + * intellectual property rights of others. + *---------------------------------------------------------------------------- + * File Name : at45c.h + * Object : + * + * 1.0 10/12/03 HIi : Creation. + * 1.01 03/05/04 HIi : Bug Fix in AT91F_DataFlashWaitReady() Function. + *---------------------------------------------------------------------------- + */ +#include "config.h" +#include "stdio.h" +#include "AT91RM9200.h" +#include "lib_AT91RM9200.h" +#include "dataflash.h" +#include "main.h" + + +/*----------------------------------------------------------------------------*/ +/* \fn AT91F_SpiInit */ +/* \brief SPI Low level Init */ +/*----------------------------------------------------------------------------*/ +void AT91F_SpiInit(void) { + /* Configure PIOs */ + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | + AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | + AT91C_PA2_SPCK; + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | + AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | + AT91C_PA2_SPCK; + /* Enable CLock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; + + /* Reset the SPI */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; + + /* Configure SPI in Master Mode with No CS selected !!! */ + AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; + + /* Configure CS0 and CS3 */ + *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | + (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | + ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); +} + + +/*----------------------------------------------------------------------------*/ +/* \fn AT91F_SpiEnable */ +/* \brief Enable SPI chip select */ +/*----------------------------------------------------------------------------*/ +static void AT91F_SpiEnable(int cs) { + switch(cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH << 16) & AT91C_SPI_PCS); + break; + case 3: /* Configure SPI CS3 for Serial DataFlash Card */ + /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ + AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; + /* Configure PCS */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + } + + /* SPI_Enable */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; +} + +/*----------------------------------------------------------------------------*/ +/* \fn AT91F_SpiWrite */ +/* \brief Set the PDC registers for a transfert */ +/*----------------------------------------------------------------------------*/ +static unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) +{ + unsigned int timeout; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + /* Initialize the Transmit and Receive Pointer */ + AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; + AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; + + /* Intialize the Transmit and Receive Counters */ + AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; + AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; + + if ( pDesc->tx_data_size != 0 ) { + /* Initialize the Next Transmit and Next Receive Pointer */ + AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; + AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; + + /* Intialize the Next Transmit and Next Receive Counters */ + AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; + AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; + } + + /* ARM simple, non interrupt dependent timer */ + timeout = 0; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; + while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF)); + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + if (timeout >= AT91C_DATAFLASH_TIMEOUT){ + return AT91C_DATAFLASH_ERROR; + } + + return AT91C_DATAFLASH_OK; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashSendCommand */ +/* \brief Generic function to send a command to the dataflash */ +/*----------------------------------------------------------------------*/ +static AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress) +{ + unsigned int adr; + + /* process the address to obtain page address and byte address */ + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) + << pDataFlash->pDevice->page_offset) + + (DataflashAddress % (pDataFlash->pDevice->pages_size)); + + /* fill the command buffer */ + pDataFlash->pDataFlashDesc->command[0] = OpCode; + if (pDataFlash->pDevice->pages_number >= 16384) + { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); + } + else + { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + } + pDataFlash->pDataFlashDesc->command[5] = 0; + pDataFlash->pDataFlashDesc->command[6] = 0; + pDataFlash->pDataFlashDesc->command[7] = 0; + + /* Initialize the SpiData structure for the spi write fuction */ + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; + + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashGetStatus */ +/* \brief Read the status register of the dataflash */ +/*----------------------------------------------------------------------*/ +static AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +{ + AT91S_DataFlashStatus status; + + /* first send the read status command (D7H) */ + pDesc->command[0] = DB_STATUS; + pDesc->command[1] = 0; + + pDesc->DataFlash_state = GET_STATUS; + pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ + pDesc->tx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_size = 2 ; + pDesc->tx_cmd_size = 2 ; + status = AT91F_SpiWrite (pDesc); + + pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); + return status; +} + +/*----------------------------------------------------------------------------- + * Function Name : AT91F_DataFlashWaitReady + * Object : wait for dataflash ready (bit7 of the status register == 1) + * Input Parameters : DataFlash Service and timeout + * Return value : DataFlash status "ready or not" + *----------------------------------------------------------------------------- + */ +static AT91S_DataFlashStatus AT91F_DataFlashWaitReady( + AT91PS_DataflashDesc pDataFlashDesc, + unsigned int timeout) +{ + pDataFlashDesc->DataFlash_state = IDLE; + do { + AT91F_DataFlashGetStatus(pDataFlashDesc); + timeout--; + } + while(((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0)); + + if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) + return AT91C_DATAFLASH_ERROR; + + return AT91C_DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashContinuousRead */ +/* Object : Continuous stream Read */ +/* Input Parameters : DataFlash Service */ +/* : = dataflash address */ +/* : <*dataBuffer> = data buffer pointer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +static AT91S_DataFlashStatus AT91F_DataFlashContinuousRead( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ) +{ + AT91S_DataFlashStatus status; + /* Test the size to read in the device */ + if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return AT91C_DATAFLASH_MEMORY_OVERFLOW; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; + + status = AT91F_DataFlashSendCommand(pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + /* Send the command to the dataflash */ + return(status); +} + + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_MainMemoryToBufferTransfer */ +/* Object : Read a page in the SRAM Buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +static AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfer( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + return AT91C_DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize, + page*pDataFlash->pDevice->pages_size)); +} + + + +/*----------------------------------------------------------------------------- */ +/* Function Name : AT91F_DataFlashWriteBuffer */ +/* Object : Write data to the internal sram buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : = command to write buffer1 or buffer2 */ +/* : <*dataBuffer> = data buffer to write */ +/* : = address in the internal buffer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +static AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) + return AT91C_DATAFLASH_BAD_COMMAND; + + /* buffer address must be lower than page size */ + if (bufferAddress > pDataFlash->pDevice->pages_size) + return AT91C_DATAFLASH_BAD_ADDRESS; + + /* Send first Write Command */ + pDataFlash->pDataFlashDesc->command[0] = BufferCommand; + pDataFlash->pDataFlashDesc->command[1] = 0; + if (pDataFlash->pDevice->pages_number >= 16384) + { + pDataFlash->pDataFlashDesc->command[2] = 0; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + cmdsize = 5; + } + else + { + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + cmdsize = 4; + } + + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PageErase */ +/* Object : Read a page in the SRAM Buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +static AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_ERASE, cmdsize, + page*pDataFlash->pDevice->pages_size)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_WriteBufferToMain */ +/* Object : Write buffer to the main memory */ +/* Input Parameters : DataFlash Service */ +/* : = command to send to buf1 or buf2 */ +/* : = main memory address */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +static AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ) +{ + int cmdsize; + /* Test if the buffer command is correct */ + if ((BufferCommand != DB_BUF1_PAGE_PGM) && + (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && + (BufferCommand != DB_BUF2_PAGE_PGM) && + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) + return AT91C_DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + /* Send the command to the dataflash */ + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PartialPageWrite */ +/* Object : Erase partially a page */ +/* Input Parameters : = page number */ +/* : = adr to begin the fading */ +/* : = Number of bytes to erase */ +/*------------------------------------------------------------------------------*/ +static AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size) +{ + unsigned int page; + unsigned int AdrInPage; + + page = dest / (pDataFlash->pDevice->pages_size); + AdrInPage = dest % (pDataFlash->pDevice->pages_size); + + /* Read the contents of the page in the Sram Buffer */ + AT91F_MainMemoryToBufferTransfer(pDataFlash, DB_PAGE_2_BUF1_TRF, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + + /*Update the SRAM buffer */ + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + + /* Erase page if a 128 Mbits device */ + if (pDataFlash->pDevice->pages_number >= 16384) + { + AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + } + + /* Rewrite the modified Sram Buffer in the main memory */ + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, + (page*pDataFlash->pDevice->pages_size))); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashWrite */ +/* Object : */ +/* Input Parameters : <*src> = Source buffer */ +/* : = dataflash adress */ +/* : = data buffer size */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ) +{ + unsigned int length; + unsigned int page; + unsigned int status; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return AT91C_DATAFLASH_MEMORY_OVERFLOW; + + /* If destination does not fit a page start address */ + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { + length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); + + if (size < length) + length = size; + + if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) + return AT91C_DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + + /* Update size, source and destination pointers */ + size -= length; + dest += length; + src += length; + } + + while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) + { + /* program dataflash page */ + page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); + + status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, + 0, pDataFlash->pDevice->pages_size); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + + status = AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + if (!status) + return AT91C_DATAFLASH_ERROR; + + status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); + if(!status) + return AT91C_DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + + /* Update size, source and destination pointers */ + size -= pDataFlash->pDevice->pages_size ; + dest += pDataFlash->pDevice->pages_size ; + src += pDataFlash->pDevice->pages_size ; + } + + /* If still some bytes to read */ + if ( size > 0 ) { + /* program dataflash page */ + if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) + return AT91C_DATAFLASH_ERROR; + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + } + return AT91C_DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashRead */ +/* Object : Read a block in dataflash */ +/* Input Parameters : */ +/* Return value : */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer) +{ + unsigned long SizeToRead; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT) != AT91C_DATAFLASH_OK) + return -1; + + while (size) + { + SizeToRead = (size < 0x8000)? size:0x8000; + + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT) + != AT91C_DATAFLASH_OK) + return -1; + + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (unsigned char *)buffer, + SizeToRead) != AT91C_DATAFLASH_OK) + return -1; + + size -= SizeToRead; + addr += SizeToRead; + buffer += SizeToRead; + } + + return AT91C_DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataflashProbe */ +/* Object : */ +/* Input Parameters : */ +/* Return value : Dataflash status register */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) +{ + AT91F_SpiEnable(cs); + AT91F_DataFlashGetStatus(pDesc); + return ((pDesc->command[1] == 0xFF)? 0: (pDesc->command[1] & 0x3C)); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashErase */ +/* Object : */ +/* Input Parameters : <*pDataFlash> = Device info */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash) +{ + unsigned int page; + unsigned int status; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + for(page=0; page < pDataFlash->pDevice->pages_number; page++) + { + /* Erase dataflash page */ + if ((page & 0x00FF) == 0) + printf("\rERA %d/%d", page, pDataFlash->pDevice->pages_number); + status = AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT); + if (!status) + return AT91C_DATAFLASH_ERROR; + } + + return AT91C_DATAFLASH_OK; +} + diff --git a/target/linux/at91/image/dfboot/src/com.c b/target/linux/at91/image/dfboot/src/com.c new file mode 100644 index 0000000..aacfb55 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/com.c @@ -0,0 +1,368 @@ +/*---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + *---------------------------------------------------------------------------- + * The software is delivered "AS IS" without warranty or condition of any + * kind, either express, implied or statutory. This includes without + * limitation any warranty or condition with respect to merchantability or + * fitness for any particular purpose, or against the infringements of + * intellectual property rights of others. + *---------------------------------------------------------------------------- + * File Name : com.c + * Object : + * Creation : HIi 03/27/2003 + * + *---------------------------------------------------------------------------- + */ +#include "AT91RM9200.h" +#include "lib_AT91RM9200.h" +#include "config.h" +#include "com.h" +#include "stdio.h" + +static char erase_seq[] = "\b \b"; /* erase sequence */ + +#define MAX_UARTS 1 + +//unsigned int usa[2] = {(unsigned int)AT91C_BASE_DBGU, (unsigned int)AT91C_ALTERNATE_USART}; +unsigned int usa[1] = {(unsigned int)AT91C_BASE_DBGU}; +unsigned int us; +int port_detected; + +void at91_init_uarts(void) +{ + int i; + + port_detected = 0; + AT91F_DBGU_CfgPIO(); + AT91F_US0_CfgPIO(); + AT91F_US0_CfgPMC(); + + for(i=0; i 16) + return 0; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + + if(type & SIGN && num < 0) + { + sign = '-'; + num = -num; + size--; + } + + i = 0; + if(num == 0) + tmp[i++] = digits[0]; + else while(num != 0) + tmp[i++] = digits[do_div(num, base)]; + + if(i > precision) + precision = i; + size -= precision; + + if(!(type&(ZEROPAD+LEFT))) + while(size-->0) + putc(' '); + + if(sign) + putc(sign); + + if (!(type & LEFT)) + while (size-- > 0) + putc(c); + + while (i < precision--) + putc('0'); + + while (i-- > 0) + putc(tmp[i]); + + while (size-- > 0) + putc(' ');; + + return 1; +} + +int hvfprintf(const char *fmt, va_list va) +{ + char *s; + + do { + if(*fmt == '%') { + bool done = false; + + int type = 0; + int precision = 0; + + do { + fmt++; + switch(*fmt) { + case '0' : + if(!precision) + type |= ZEROPAD; + case '1' : + case '2' : + case '3' : + case '4' : + case '5' : + case '6' : + case '7' : + case '8' : + case '9' : + precision = precision * 10 + (*fmt - '0'); + break; + case '.' : + break; + case 's' : + s = va_arg(va, char *); + if(!s) + puts(""); + else + puts(s); + done = true; + break; + case 'c' : + putc(va_arg(va, int)); + done = true; + break; + case 'd' : + number(va_arg(va, int), 10, 0, precision, type); + done = true; + break; + case 'x' : + case 'X' : + number(va_arg(va, int), 16, 0, precision, type); + done = true; + break; + case '%' : + putc(*fmt); + done = true; + default: + putc('%'); + putc(*fmt); + done = true; + break; + } + } while(!done); + } else if(*fmt == '\\') { + fmt++; + if(*fmt == 'r') { + putc('\r'); + } else if(*fmt == 'n') { + putc('\n'); + } + } else { + putc(*fmt); + } + fmt++; + } while(*fmt != 0); + + return 0; +} + +int printf(const char *fmt, ...) +{ + va_list ap; + int i; + + va_start(ap, fmt); + i = hvfprintf(fmt, ap); + va_end(ap); + + return i; +} diff --git a/target/linux/at91/image/dfboot/src/com.h b/target/linux/at91/image/dfboot/src/com.h new file mode 100644 index 0000000..7af09e4 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/com.h @@ -0,0 +1,28 @@ +/*---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + *---------------------------------------------------------------------------- + * The software is delivered "AS IS" without warranty or condition of any + * kind, either express, implied or statutory. This includes without + * limitation any warranty or condition with respect to merchantability or + * fitness for any particular purpose, or against the infringements of + * intellectual property rights of others. + *---------------------------------------------------------------------------- + * File Name : com.h + * Object : + * + * 1.0 27/03/03 HIi : Creation + *---------------------------------------------------------------------------- + */ +#ifndef com_h +#define com_h + +#define AT91C_CB_SIZE 20 /* size of the console buffer */ + +/* Escape sequences */ +#define ESC \033 + +extern int AT91F_ReadLine (const char *const prompt, char *console_buffer); +extern void AT91F_WaitKeyPressed(void); + +#endif + diff --git a/target/linux/at91/image/dfboot/src/config.h b/target/linux/at91/image/dfboot/src/config.h new file mode 100644 index 0000000..3be8d49 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/config.h @@ -0,0 +1,17 @@ + +#ifndef _CONFIG_H +#define _CONFIG_H + +//#define PAGESZ_1056 1 +#undef PAGESZ_1056 +#define SPI_LOW_SPEED 1 +#define AT91C_DELAY_TO_BOOT 1500 + +#define CRC_RETRIES 0x100 + +#define AT91C_MASTER_CLOCK 59904000 +#define AT91C_BAUD_RATE 115200 + +#define AT91C_ALTERNATE_USART AT91C_BASE_US0 + +#endif diff --git a/target/linux/at91/image/dfboot/src/cstartup_ram.S b/target/linux/at91/image/dfboot/src/cstartup_ram.S new file mode 100644 index 0000000..2239000 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/cstartup_ram.S @@ -0,0 +1,144 @@ +#include "AT91RM9200_inc.h" + +/*--------------------------- +ARM Core Mode and Status Bits +---------------------------*/ +.section start + .text + +#define ARM_MODE_USER 0x10 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_ABORT 0x17 +#define ARM_MODE_UNDEF 0x1B +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 +#define T_BIT 0x20 + +/*---------------------------------------------------------------------------- + Area Definition +---------------- + Must be defined as function to put first in the code as it must be mapped + at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap. +_---------------------------------------------------------------------------*/ + + .align 4 + .globl _start +_start: + +/*---------------------------------------------------------------------------- + Exception vectors ( before Remap ) +------------------------------------ + These vectors are read at address 0. + They absolutely requires to be in relative addresssing mode in order to + guarantee a valid jump. For the moment, all are just looping (what may be + dangerous in a final system). If an exception occurs before remap, this + would result in an infinite loop. +----------------------------------------------------------------------------*/ + b reset /* reset */ + b undefvec /* Undefined Instruction */ + b swivec /* Software Interrupt */ + b pabtvec /* Prefetch Abort */ + b dabtvec /* Data Abort */ + b rsvdvec /* reserved */ + b aicvec /* IRQ : read the AIC */ + b fiqvec /* FIQ */ + +undefvec: +swivec: +pabtvec: +dabtvec: +rsvdvec: +aicvec: +fiqvec: + b undefvec + +reset: + +#define MEMEND 0x00004000 + +/* ---------------------------- + Setup the stack for each mode +---------------------------- */ + +#define IRQ_STACK_SIZE 0x10 +#define FIQ_STACK_SIZE 0x04 +#define ABT_STACK_SIZE 0x04 +#define UND_STACK_SIZE 0x04 +#define SVC_STACK_SIZE 0x10 +#define USER_STACK_SIZE 0x400 + + ldr r0,= MEMEND + +/*- Set up Supervisor Mode and set Supervisor Mode Stack*/ + msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT + mov r13, r0 /* Init stack Undef*/ + sub r0, r0, #SVC_STACK_SIZE + +/*- Set up Interrupt Mode and set IRQ Mode Stack*/ + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + mov r13, r0 /* Init stack IRQ*/ + sub r0, r0, #IRQ_STACK_SIZE + +/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/ + msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT + mov r13, r0 /* Init stack FIQ*/ + sub r0, r0, #FIQ_STACK_SIZE + +/*- Set up Abort Mode and set Abort Mode Stack*/ + msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT + mov r13, r0 /* Init stack Abort*/ + sub r0, r0, #ABT_STACK_SIZE + +/*- Set up Undefined Instruction Mode and set Undef Mode Stack*/ + msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT + mov r13, r0 /* Init stack Undef*/ + sub r0, r0, #UND_STACK_SIZE + +/*- Set up user Mode and set System Mode Stack*/ + msr CPSR_c, #ARM_MODE_SYS | I_BIT | F_BIT + bic r0, r0, #3 /* Insure word alignement */ + mov sp, r0 /* Init stack System */ + + + ldr r0, = AT91F_LowLevelInit + mov lr, pc + bx r0 + +/*---------------------------------------- + Read/modify/write CP15 control register +----------------------------------------*/ + mrc p15, 0, r0, c1, c0,0 /* read cp15 control registre (cp15 r1) in r0 */ + ldr r3,= 0xC0000080 /* Reset bit :Little Endian end fast bus mode */ + ldr r4,= 0xC0001000 /* Set bit :Asynchronous clock mode, Not Fast Bus, I-Cache enable */ + bic r0, r0, r3 + orr r0, r0, r4 + mcr p15, 0, r0, c1, c0,0 /* write r0 in cp15 control registre (cp15 r1) */ + +/* Enable interrupts */ + msr CPSR_c, #ARM_MODE_SYS | F_BIT + +/*------------------------------------------------------------------------------ +- Branch on C code Main function (with interworking) +---------------------------------------------------- +- Branch must be performed by an interworking call as either an ARM or Thumb +- _start function must be supported. This makes the code not position- +- independent. A Branch with link would generate errors +----------------------------------------------------------------------------*/ + +/*- Branch to _start by interworking*/ + ldr r4, = main + mov lr, pc + bx r4 + +/*----------------------------------------------------------------------------- +- Loop for ever +--------------- +- End of application. Normally, never occur. +- Could jump on Software Reset ( B 0x0 ). +------------------------------------------------------------------------------*/ +End: + b End diff --git a/target/linux/at91/image/dfboot/src/dataflash.c b/target/linux/at91/image/dfboot/src/dataflash.c new file mode 100644 index 0000000..5e54460 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/dataflash.c @@ -0,0 +1,208 @@ +/*---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + *---------------------------------------------------------------------------- + * The software is delivered "AS IS" without warranty or condition of any + * kind, either express, implied or statutory. This includes without + * limitation any warranty or condition with respect to merchantability or + * fitness for any particular purpose, or against the infringements of + * intellectual property rights of others. + *---------------------------------------------------------------------------- + * File Name : dataflash.c + * Object : High level functions for the dataflash + * Creation : HIi 10/10/2003 + *---------------------------------------------------------------------------- + */ +#include "config.h" +#include "stdio.h" +#include "dataflash.h" + + +AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +static AT91S_DataFlash DataFlashInst; + +int cs[][CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} +}; + +int AT91F_DataflashInit(void) +{ + int i; + int dfcode; + int Nb_device = 0; + + AT91F_SpiInit(); + + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + dataflash_info[i].id = 0; + dataflash_info[i].Device.pages_number = 0; + dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); + + switch (dfcode) { + case AT45DB161: + dataflash_info[i].Device.pages_number = 4096; + dataflash_info[i].Device.pages_size = 528; + dataflash_info[i].Device.page_offset = 10; + dataflash_info[i].Device.byte_mask = 0x300; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + Nb_device++; + break; + + case AT45DB321: + dataflash_info[i].Device.pages_number = 8192; + dataflash_info[i].Device.pages_size = 528; + dataflash_info[i].Device.page_offset = 10; + dataflash_info[i].Device.byte_mask = 0x300; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + Nb_device++; + break; + + case AT45DB642: + dataflash_info[i].Device.pages_number = 8192; + dataflash_info[i].Device.pages_size = 1056; + dataflash_info[i].Device.page_offset = 11; + dataflash_info[i].Device.byte_mask = 0x700; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + Nb_device++; + break; + case AT45DB128: + dataflash_info[i].Device.pages_number = 16384; + dataflash_info[i].Device.pages_size = 1056; + dataflash_info[i].Device.page_offset = 11; + dataflash_info[i].Device.byte_mask = 0x700; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + Nb_device++; + break; + default: + break; + } + } + return (Nb_device); +} + + +void AT91F_DataflashPrintInfo(void) +{ + int i; + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + if (dataflash_info[i].id != 0) { + printf ("DF:AT45DB"); + switch (dataflash_info[i].id) { + case AT45DB161: + printf ("161"); + break; + + case AT45DB321: + printf ("321"); + break; + + case AT45DB642: + printf ("642"); + break; + case AT45DB128: + printf ("128"); + break; + } + + printf ("\n# PG: %6d\n" + "PG SZ: %6d\n" + "SZ=%8d bytes\n" + "ADDR: %08X\n", + (unsigned int) dataflash_info[i].Device.pages_number, + (unsigned int) dataflash_info[i].Device.pages_size, + (unsigned int) dataflash_info[i].Device.pages_number * + dataflash_info[i].Device.pages_size, + (unsigned int) dataflash_info[i].logical_address); + } + } +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataflashSelect */ +/* Object : Select the correct device */ +/*------------------------------------------------------------------------------*/ +static AT91PS_DataFlash AT91F_DataflashSelect(AT91PS_DataFlash pFlash, + unsigned int *addr) +{ + char addr_valid = 0; + int i; + + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) + if ((*addr & 0xFF000000) == dataflash_info[i].logical_address) { + addr_valid = 1; + break; + } + if (!addr_valid) { + pFlash = (AT91PS_DataFlash) 0; + return pFlash; + } + pFlash->pDataFlashDesc = &(dataflash_info[i].Desc); + pFlash->pDevice = &(dataflash_info[i].Device); + *addr -= dataflash_info[i].logical_address; + return (pFlash); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : read_dataflash */ +/* Object : dataflash memory read */ +/*------------------------------------------------------------------------------*/ +int read_dataflash(unsigned long addr, unsigned long size, char *result) +{ + unsigned int AddrToRead = addr; + AT91PS_DataFlash pFlash = &DataFlashInst; + + pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead); + if (pFlash == 0) + return -1; + + return (AT91F_DataFlashRead(pFlash, AddrToRead, size, result)); +} + + +/*-----------------------------------------------------------------------------*/ +/* Function Name : write_dataflash */ +/* Object : write a block in dataflash */ +/*-----------------------------------------------------------------------------*/ +int write_dataflash(unsigned long addr_dest, unsigned int addr_src, + unsigned int size) +{ + unsigned int AddrToWrite = addr_dest; + AT91PS_DataFlash pFlash = &DataFlashInst; + + pFlash = AT91F_DataflashSelect(pFlash, &AddrToWrite); + if (AddrToWrite == -1) + return -1; + + return AT91F_DataFlashWrite(pFlash, (unsigned char *) addr_src, AddrToWrite, size); +} + +/*-----------------------------------------------------------------------------*/ +/* Function Name : erase_dataflash */ +/* Object : Erase entire dataflash */ +/*-----------------------------------------------------------------------------*/ +int erase_dataflash(unsigned long addr_dest) +{ + unsigned int AddrToWrite = addr_dest; + AT91PS_DataFlash pFlash = &DataFlashInst; + + pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite); + if (AddrToWrite == -1) + return -1; + + return AT91F_DataFlashErase(pFlash); +} + diff --git a/target/linux/at91/image/dfboot/src/dataflash.h b/target/linux/at91/image/dfboot/src/dataflash.h new file mode 100644 index 0000000..8fab63f --- /dev/null +++ b/target/linux/at91/image/dfboot/src/dataflash.h @@ -0,0 +1,181 @@ +//*--------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*--------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*--------------------------------------------------------------------------- +//* File Name : AT91_SpiDataFlash.h +//* Object : Data Flash Atmel Description File +//* Translator : +//* +//* 1.0 03/04/01 HI : Creation +//* +//*--------------------------------------------------------------------------- + +#ifndef _DataFlash_h +#define _DataFlash_h + +/* Max value = 15Mhz to be compliant with the Continuous array read function */ +#ifdef SPI_LOW_SPEED +#define AT91C_SPI_CLK 14976000/4 +#else +#define AT91C_SPI_CLK 14976000 +#endif + +/* AC characteristics */ +/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */ + +#define DATAFLASH_TCSS (0xf << 16) /* 250ns 15/60000000 */ +#define DATAFLASH_TCHS (0x1 << 24) /* 250ns 32*1/60000000 */ + + +#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ +#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ + +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 + +typedef struct { + unsigned long base; /* logical base address for a bank */ + unsigned long size; /* total bank size */ + unsigned long page_count; + unsigned long page_size; + unsigned long id; /* device id */ +} dataflash_info_t; + +typedef unsigned int AT91S_DataFlashStatus; + +/*----------------------------------------------------------------------*/ +/* DataFlash Structures */ +/*----------------------------------------------------------------------*/ + +/*---------------------------------------------*/ +/* DataFlash Descriptor Structure Definition */ +/*---------------------------------------------*/ +typedef struct _AT91S_DataflashDesc { + unsigned char *tx_cmd_pt; + unsigned int tx_cmd_size; + unsigned char *rx_cmd_pt; + unsigned int rx_cmd_size; + unsigned char *tx_data_pt; + unsigned int tx_data_size; + unsigned char *rx_data_pt; + unsigned int rx_data_size; + volatile unsigned char DataFlash_state; + unsigned char command[8]; +} AT91S_DataflashDesc, *AT91PS_DataflashDesc; + +/*---------------------------------------------*/ +/* DataFlash device definition structure */ +/*---------------------------------------------*/ +typedef struct _AT91S_Dataflash { + int pages_number; /* dataflash page number */ + int pages_size; /* dataflash page size */ + int page_offset; /* page offset in command */ + int byte_mask; /* byte mask in command */ + int cs; +} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures; + + +/*---------------------------------------------*/ +/* DataFlash Structure Definition */ +/*---------------------------------------------*/ +typedef struct _AT91S_DataFlash { + AT91PS_DataflashDesc pDataFlashDesc; /* dataflash descriptor */ + AT91PS_DataflashFeatures pDevice; /* Pointer on a dataflash features array */ +} AT91S_DataFlash, *AT91PS_DataFlash; + + +typedef struct _AT91S_DATAFLASH_INFO { + + AT91S_DataflashDesc Desc; + AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */ + unsigned long logical_address; + unsigned int id; /* device id */ +} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO; + + +/*-------------------------------------------------------------------------------------------------*/ + +#define AT45DB161 0x2c +#define AT45DB321 0x34 +#define AT45DB642 0x3c +#define AT45DB128 0x10 + +#define AT91C_DATAFLASH_TIMEOUT 20000 /* For AT91F_DataFlashWaitReady */ + +/* DataFlash return value */ +#define AT91C_DATAFLASH_BUSY 0x00 +#define AT91C_DATAFLASH_OK 0x01 +#define AT91C_DATAFLASH_ERROR 0x02 +#define AT91C_DATAFLASH_MEMORY_OVERFLOW 0x03 +#define AT91C_DATAFLASH_BAD_COMMAND 0x04 +#define AT91C_DATAFLASH_BAD_ADDRESS 0x05 + + +/* Driver State */ +#define IDLE 0x0 +#define BUSY 0x1 +#define ERROR 0x2 + +/* DataFlash Driver State */ +#define GET_STATUS 0x0F + +/*-------------------------------------------------------------------------------------------------*/ +/* Command Definition */ +/*-------------------------------------------------------------------------------------------------*/ + +/* READ COMMANDS */ +#define DB_CONTINUOUS_ARRAY_READ 0xE8 /* Continuous array read */ +#define DB_BURST_ARRAY_READ 0xE8 /* Burst array read */ +#define DB_PAGE_READ 0xD2 /* Main memory page read */ +#define DB_BUF1_READ 0xD4 /* Buffer 1 read */ +#define DB_BUF2_READ 0xD6 /* Buffer 2 read */ +#define DB_STATUS 0xD7 /* Status Register */ + +/* PROGRAM and ERASE COMMANDS */ +#define DB_BUF1_WRITE 0x84 /* Buffer 1 write */ +#define DB_BUF2_WRITE 0x87 /* Buffer 2 write */ +#define DB_BUF1_PAGE_ERASE_PGM 0x83 /* Buffer 1 to main memory page program with built-In erase */ +#define DB_BUF1_PAGE_ERASE_FASTPGM 0x93 /* Buffer 1 to main memory page program with built-In erase, Fast program */ +#define DB_BUF2_PAGE_ERASE_PGM 0x86 /* Buffer 2 to main memory page program with built-In erase */ +#define DB_BUF2_PAGE_ERASE_FASTPGM 0x96 /* Buffer 1 to main memory page program with built-In erase, Fast program */ +#define DB_BUF1_PAGE_PGM 0x88 /* Buffer 1 to main memory page program without built-In erase */ +#define DB_BUF1_PAGE_FASTPGM 0x98 /* Buffer 1 to main memory page program without built-In erase, Fast program */ +#define DB_BUF2_PAGE_PGM 0x89 /* Buffer 2 to main memory page program without built-In erase */ +#define DB_BUF2_PAGE_FASTPGM 0x99 /* Buffer 1 to main memory page program without built-In erase, Fast program */ +#define DB_PAGE_ERASE 0x81 /* Page Erase */ +#define DB_BLOCK_ERASE 0x50 /* Block Erase */ +#define DB_PAGE_PGM_BUF1 0x82 /* Main memory page through buffer 1 */ +#define DB_PAGE_FASTPGM_BUF1 0x92 /* Main memory page through buffer 1, Fast program */ +#define DB_PAGE_PGM_BUF2 0x85 /* Main memory page through buffer 2 */ +#define DB_PAGE_FastPGM_BUF2 0x95 /* Main memory page through buffer 2, Fast program */ + +/* ADDITIONAL COMMANDS */ +#define DB_PAGE_2_BUF1_TRF 0x53 /* Main memory page to buffer 1 transfert */ +#define DB_PAGE_2_BUF2_TRF 0x55 /* Main memory page to buffer 2 transfert */ +#define DB_PAGE_2_BUF1_CMP 0x60 /* Main memory page to buffer 1 compare */ +#define DB_PAGE_2_BUF2_CMP 0x61 /* Main memory page to buffer 2 compare */ +#define DB_AUTO_PAGE_PGM_BUF1 0x58 /* Auto page rewrite throught buffer 1 */ +#define DB_AUTO_PAGE_PGM_BUF2 0x59 /* Auto page rewrite throught buffer 2 */ + +/*-------------------------------------------------------------------------------------------------*/ + +extern AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; + +extern void AT91F_SpiInit(void); +extern int AT91F_DataflashProbe(int i, AT91PS_DataflashDesc pDesc); +extern int AT91F_DataFlashRead(AT91PS_DataFlash, unsigned long , unsigned long, char *); +extern AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash ,unsigned char *, int, int); +extern AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash); +extern int AT91F_DataflashInit(void); +extern void AT91F_DataflashPrintInfo(void); +extern int read_dataflash(unsigned long addr, unsigned long size, char *result); +extern int write_dataflash(unsigned long addr_dest, unsigned int addr_src, unsigned int size); +extern int erase_dataflash(unsigned long addr_dest); + +#endif diff --git a/target/linux/at91/image/dfboot/src/div0.c b/target/linux/at91/image/dfboot/src/div0.c new file mode 100644 index 0000000..d6fd90e --- /dev/null +++ b/target/linux/at91/image/dfboot/src/div0.c @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Replacement (=dummy) for GNU/Linux division-by zero handler */ +void __div0 (void) +{ + while(-1); +} diff --git a/target/linux/at91/image/dfboot/src/elf32-littlearm.lds b/target/linux/at91/image/dfboot/src/elf32-littlearm.lds new file mode 100644 index 0000000..4d4efb6 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/elf32-littlearm.lds @@ -0,0 +1,19 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : { *(.text) } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .bss : { *(.bss) } +} \ No newline at end of file diff --git a/target/linux/at91/image/dfboot/src/embedded_services.h b/target/linux/at91/image/dfboot/src/embedded_services.h new file mode 100644 index 0000000..956b9ed --- /dev/null +++ b/target/linux/at91/image/dfboot/src/embedded_services.h @@ -0,0 +1,500 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : embedded_sevices.h +//* Object : Header File with all the embedded software services definitions +//* +//* 1.0 24 Jan 2003 FB : Creation +//*---------------------------------------------------------------------------- +#ifndef embedded_sevices_h +#define embedded_sevices_h + +#include "AT91RM9200.h" + +#define AT91C_BASE_ROM (char *)0x00100000 + +/* Return values */ +#define AT91C_BUFFER_SUCCESS 0 +#define AT91C_BUFFER_ERROR_SHIFT 16 +#define AT91C_BUFFER_ERROR (0x0F << AT91C_BUFFER_ERROR_SHIFT) + +#define AT91C_BUFFER_OVERFLOW (0x01 << AT91C_BUFFER_ERROR_SHIFT) +#define AT91C_BUFFER_UNDERRUN (0x02 << AT91C_BUFFER_ERROR_SHIFT) + +typedef unsigned int AT91S_BufferStatus; + +struct _AT91S_Pipe; + +// This structure is a virtual object of a buffer +typedef struct _AT91S_Buffer +{ + struct _AT91S_Pipe *pPipe; + void *pChild; + + // Functions invoked by the pipe + AT91S_BufferStatus (*SetRdBuffer) (struct _AT91S_Buffer *pSBuffer, char *pBuffer, unsigned int Size); + AT91S_BufferStatus (*SetWrBuffer) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer, unsigned int Size); + AT91S_BufferStatus (*RstRdBuffer) (struct _AT91S_Buffer *pSBuffer); + AT91S_BufferStatus (*RstWrBuffer) (struct _AT91S_Buffer *pSBuffer); + char (*MsgWritten) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer); + char (*MsgRead) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer); + // Functions invoked by the peripheral + AT91S_BufferStatus (*GetWrBuffer) (struct _AT91S_Buffer *pSBuffer, char const **pData, unsigned int *pSize); + AT91S_BufferStatus (*GetRdBuffer) (struct _AT91S_Buffer *pSBuffer, char **pData, unsigned int *pSize); + AT91S_BufferStatus (*EmptyWrBuffer) (struct _AT91S_Buffer *pSBuffer, unsigned int size); + AT91S_BufferStatus (*FillRdBuffer) (struct _AT91S_Buffer *pSBuffer, unsigned int size); + char (*IsWrEmpty) (struct _AT91S_Buffer *pSBuffer); + char (*IsRdFull) (struct _AT91S_Buffer *pSBuffer); +} AT91S_Buffer, *AT91PS_Buffer; + +// =========================================================================================== +// SimpleBuffer definition +// +// This structure is pointed by pRealBuffer field in the SBuffer +// It contains usefull information for a real implementation of +// a SBuffer object. +// The application just create an instance of SSBUffer and SBuffer, +// call OpenSimpleBuffer, and continue using SBuffer instance + +typedef struct _AT91S_SBuffer +{ + AT91S_Buffer parent; + char *pRdBuffer; + char const *pWrBuffer; + unsigned int szRdBuffer; + unsigned int szWrBuffer; + unsigned int stRdBuffer; + unsigned int stWrBuffer; +} AT91S_SBuffer, *AT91PS_SBuffer; + +typedef AT91PS_Buffer (*AT91PF_OpenSBuffer) (AT91PS_SBuffer); + +// This function is called by the application +extern AT91PS_Buffer AT91F_OpenSBuffer(AT91PS_SBuffer pBuffer); + +// Functions invoked by the pipe +extern AT91S_BufferStatus AT91F_SbSetRdBuffer (AT91PS_Buffer pBuffer, char *pData, unsigned int Size); +extern AT91S_BufferStatus AT91F_SbSetWrBuffer (AT91PS_Buffer pBuffer, char const *pData, unsigned int Size); +extern AT91S_BufferStatus AT91F_SbRstRdBuffer (AT91PS_Buffer pBuffer); +extern AT91S_BufferStatus AT91F_SbRstWrBuffer (AT91PS_Buffer pBuffer); +extern char AT91F_SbMsgWritten (AT91PS_Buffer pBuffer, char const *pMsg); +extern char AT91F_SbMsgRead (AT91PS_Buffer pBuffer, char const *pMsg); +// Functions invoked by the peripheral +extern AT91S_BufferStatus AT91F_SbGetWrBuffer (AT91PS_Buffer pBuffer, char const **pData, unsigned int *pSize); +extern AT91S_BufferStatus AT91F_SbGetRdBuffer (AT91PS_Buffer pBuffer, char **pData, unsigned int *pSize); +extern AT91S_BufferStatus AT91F_SbEmptyWrBuffer(AT91PS_Buffer pBuffer, unsigned int size); +extern AT91S_BufferStatus AT91F_SbFillRdBuffer (AT91PS_Buffer pBuffer, unsigned int size); +extern char AT91F_SbIsWrEmpty (AT91PS_Buffer pBuffer); +extern char AT91F_SbIsRdFull (AT91PS_Buffer pBuffer); + +#ifdef DBG_DRV_BUFFER +extern char const *AT91F_SbGetError(AT91S_BufferStatus errorNumber); +#endif + + +#define AT91C_OPEN_CTRLTEMPO_SUCCESS 0 +#define AT91C_ERROR_OPEN_CTRLTEMPO 1 +#define AT91C_START_OK 2 +#define AT91C_STOP_OK 3 +#define AT91C_TIMEOUT_REACHED 4 + +typedef enum _AT91E_SvcTempo { + AT91E_SVCTEMPO_DIS, + AT91E_SVCTEMPO_EN +} AT91E_SvcTempo; + +typedef unsigned int AT91S_TempoStatus; + +// AT91S_SvcTempo +typedef struct _AT91S_SvcTempo +{ + + // Methods: + AT91S_TempoStatus (*Start) ( + struct _AT91S_SvcTempo *pSvc, + unsigned int timeout, + unsigned int reload, + void (*callback) (AT91S_TempoStatus, void *), + void *pData); + AT91S_TempoStatus (*Stop) (struct _AT91S_SvcTempo *pSvc); + + struct _AT91S_SvcTempo *pPreviousTempo; + struct _AT91S_SvcTempo *pNextTempo; + + // Data + unsigned int TickTempo; //* timeout value + unsigned int ReloadTempo;//* Reload value for periodic execution + void (*TempoCallback)(AT91S_TempoStatus, void *); + void *pPrivateData; + AT91E_SvcTempo flag; +} AT91S_SvcTempo, *AT91PS_SvcTempo; + + +// AT91S_CtrlTempo +typedef struct _AT91S_CtlTempo +{ + // Members: + + // Start and stop for Timer hardware + AT91S_TempoStatus (*CtlTempoStart) (void *pTimer); + AT91S_TempoStatus (*CtlTempoStop) (void *pTimer); + + // Start and stop for Tempo service + AT91S_TempoStatus (*SvcTempoStart) ( + struct _AT91S_SvcTempo *pSvc, + unsigned int timeout, + unsigned int reload, + void (*callback) (AT91S_TempoStatus, void *), + void *pData); + AT91S_TempoStatus (*SvcTempoStop) (struct _AT91S_SvcTempo *pSvc); + AT91S_TempoStatus (*CtlTempoSetTime)(struct _AT91S_CtlTempo *pCtrl, unsigned int NewTime); + AT91S_TempoStatus (*CtlTempoGetTime)(struct _AT91S_CtlTempo *pCtrl); + AT91S_TempoStatus (*CtlTempoIsStart)(struct _AT91S_CtlTempo *pCtrl); + AT91S_TempoStatus (*CtlTempoCreate) ( + struct _AT91S_CtlTempo *pCtrl, + struct _AT91S_SvcTempo *pTempo); + AT91S_TempoStatus (*CtlTempoRemove) ( + struct _AT91S_CtlTempo *pCtrl, + struct _AT91S_SvcTempo *pTempo); + AT91S_TempoStatus (*CtlTempoTick) (struct _AT91S_CtlTempo *pCtrl); + + // Data: + + void *pPrivateData; // Pointer to devived class + void const *pTimer; // hardware + AT91PS_SvcTempo pFirstTempo; + AT91PS_SvcTempo pNewTempo; +} AT91S_CtlTempo, *AT91PS_CtlTempo; +typedef AT91S_TempoStatus (*AT91PF_OpenCtlTempo) ( AT91PS_CtlTempo, void const *); + +// This function is called by the application. +extern AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtrlTempo, void const *pTempoTimer ); + +extern AT91S_TempoStatus AT91F_STStart (void *); +extern AT91S_TempoStatus AT91F_STStop (void *); +extern AT91S_TempoStatus AT91F_STSetTime (AT91PS_CtlTempo, unsigned int); +extern AT91S_TempoStatus AT91F_STGetTime (AT91PS_CtlTempo); +extern AT91S_TempoStatus AT91F_STIsStart (AT91PS_CtlTempo); +extern AT91S_TempoStatus AT91F_CtlTempoCreate (AT91PS_CtlTempo, AT91PS_SvcTempo); +extern AT91S_TempoStatus AT91F_CtlTempoRemove (AT91PS_CtlTempo, AT91PS_SvcTempo); +extern AT91S_TempoStatus AT91F_CtlTempoTick (AT91PS_CtlTempo); +extern AT91S_TempoStatus AT91F_SvcTempoStart ( + AT91PS_SvcTempo pSvc, + unsigned int timeout, + unsigned int reload, + void (*callback) (AT91S_TempoStatus, void *), + void *pData); +extern AT91S_TempoStatus AT91F_SvcTempoStop (AT91PS_SvcTempo); + + +// Following types are defined in another header files +struct _AT91S_Buffer; + +// Constants: +#define AT91C_COMMSVC_SUCCESS 0 +#define AT91C_COMMSVC_ERROR_SHIFT 8 +#define AT91C_COMMSVC_ERROR (0x0f << AT91C_COMMSVC_ERROR_SHIFT) + +typedef unsigned int AT91S_SvcCommStatus; + +// AT91S_Service definition +// This structure is an abstraction of a communication peripheral +typedef struct _AT91S_Service +{ + // Methods: + AT91S_SvcCommStatus (*Reset) (struct _AT91S_Service *pService); + AT91S_SvcCommStatus (*StartTx)(struct _AT91S_Service *pService); + AT91S_SvcCommStatus (*StartRx)(struct _AT91S_Service *pService); + AT91S_SvcCommStatus (*StopTx) (struct _AT91S_Service *pService); + AT91S_SvcCommStatus (*StopRx) (struct _AT91S_Service *pService); + char (*TxReady)(struct _AT91S_Service *pService); + char (*RxReady)(struct _AT91S_Service *pService); + // Data: + struct _AT91S_Buffer *pBuffer; // Link to a buffer object + void *pChild; +} AT91S_SvcComm, *AT91PS_SvcComm; + +// Constants: +#define AT91C_XMODEM_SOH 0x01 /* Start of Heading for 128 bytes */ +#define AT91C_XMODEM_STX 0x02 /* Start of heading for 1024 bytes */ +#define AT91C_XMODEM_EOT 0x04 /* End of transmission */ +#define AT91C_XMODEM_ACK 0x06 /* Acknowledge */ +#define AT91C_XMODEM_NAK 0x15 /* Negative Acknowledge */ +#define AT91C_XMODEM_CRCCHR 'C' + +#define AT91C_XMODEM_PACKET_SIZE 2 // packet + packetCRC +#define AT91C_XMODEM_CRC_SIZE 2 // crcLSB + crcMSB +#define AT91C_XMODEM_DATA_SIZE_SOH 128 // data 128 corresponding to SOH header +#define AT91C_XMODEM_DATA_SIZE_STX 1024 // data 1024 corresponding to STX header + +//* Following structure is used by SPipe to refer to the USB device peripheral endpoint +typedef struct _AT91PS_SvcXmodem { + + // Public Methods: + AT91S_SvcCommStatus (*Handler) (struct _AT91PS_SvcXmodem *, unsigned int); + AT91S_SvcCommStatus (*StartTx) (struct _AT91PS_SvcXmodem *, unsigned int); + AT91S_SvcCommStatus (*StopTx) (struct _AT91PS_SvcXmodem *, unsigned int); + + // Private Methods: + AT91S_SvcCommStatus (*ReadHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr); + AT91S_SvcCommStatus (*WriteHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr); + unsigned short (*GetCrc) (char *ptr, unsigned int count); + char (*CheckHeader) (unsigned char currentPacket, char *packet); + char (*CheckData) (struct _AT91PS_SvcXmodem *); + + AT91S_SvcComm parent; // Base class + AT91PS_USART pUsart; + + AT91S_SvcTempo tempo; // Link to a AT91S_Tempo object + + char *pData; + unsigned int dataSize; // = XMODEM_DATA_STX or XMODEM_DATA_SOH + char packetDesc[AT91C_XMODEM_PACKET_SIZE]; + unsigned char packetId; // Current packet + char packetStatus; + char isPacketDesc; + char eot; // end of transmition +} AT91S_SvcXmodem, *AT91PS_SvcXmodem; + +typedef AT91PS_SvcComm (*AT91PF_OpenSvcXmodem) ( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo); + +// This function is called by the application. +extern AT91PS_SvcComm AT91F_OpenSvcXmodem( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo); + +extern unsigned short AT91F_SvcXmodemGetCrc (char *ptr, unsigned int count); +extern char AT91F_SvcXmodemCheckHeader(unsigned char currentPacket, char *packet); +extern char AT91F_SvcXmodemCheckData (AT91PS_SvcXmodem pSvcXmodem); +extern AT91S_SvcCommStatus AT91F_SvcXmodemReadHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr); +extern AT91S_SvcCommStatus AT91F_SvcXmodemWriteHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr); +extern AT91S_SvcCommStatus AT91F_SvcXmodemStartTx(AT91PS_SvcComm pSvcComm); +extern AT91S_SvcCommStatus AT91F_SvcXmodemStopTx(AT91PS_SvcComm pSvcComm); +extern AT91S_SvcCommStatus AT91F_SvcXmodemStartRx(AT91PS_SvcComm pSvcComm); +extern AT91S_SvcCommStatus AT91F_SvcXmodemStopRx(AT91PS_SvcComm pSvcComm); +extern char AT91F_SvcXmodemTxReady(AT91PS_SvcComm pService); +extern char AT91F_SvcXmodemRxReady(AT91PS_SvcComm pSvcComm); + + +// Constants: +#define AT91C_PIPE_SUCCESS 0 +#define AT91C_PIPE_ERROR_SHIFT 8 +#define AT91C_PIPE_ERROR (0x0F << AT91C_PIPE_ERROR_SHIFT) + +#define AT91C_PIPE_OPEN_FAILED (1 << AT91C_PIPE_ERROR_SHIFT) +#define AT91C_PIPE_WRITE_FAILED (2 << AT91C_PIPE_ERROR_SHIFT) +#define AT91C_PIPE_WRITE_ABORTED (3 << AT91C_PIPE_ERROR_SHIFT) +#define AT91C_PIPE_READ_FAILED (4 << AT91C_PIPE_ERROR_SHIFT) +#define AT91C_PIPE_READ_ABORTED (5 << AT91C_PIPE_ERROR_SHIFT) +#define AT91C_PIPE_ABORT_FAILED (6 << AT91C_PIPE_ERROR_SHIFT) +#define AT91C_PIPE_RESET_FAILED (7 << AT91C_PIPE_ERROR_SHIFT) + +/* _AT91S_Pipe stucture */ +typedef unsigned int AT91S_PipeStatus; + +typedef struct _AT91S_Pipe +{ + // A pipe is linked with a peripheral and a buffer + AT91PS_SvcComm pSvcComm; + AT91PS_Buffer pBuffer; + + // Callback functions with their arguments + void (*WriteCallback) (AT91S_PipeStatus, void *); + void (*ReadCallback) (AT91S_PipeStatus, void *); + void *pPrivateReadData; + void *pPrivateWriteData; + + // Pipe methods + AT91S_PipeStatus (*Write) ( + struct _AT91S_Pipe *pPipe, + char const * pData, + unsigned int size, + void (*callback) (AT91S_PipeStatus, void *), + void *privateData); + AT91S_PipeStatus (*Read) ( + struct _AT91S_Pipe *pPipe, + char *pData, + unsigned int size, + void (*callback) (AT91S_PipeStatus, void *), + void *privateData); + AT91S_PipeStatus (*AbortWrite) ( + struct _AT91S_Pipe *pPipe); + AT91S_PipeStatus (*AbortRead) ( + struct _AT91S_Pipe *pPipe); + AT91S_PipeStatus (*Reset) ( + struct _AT91S_Pipe *pPipe); + char (*IsWritten) ( + struct _AT91S_Pipe *pPipe, + char const *pVoid); + char (*IsReceived) ( + struct _AT91S_Pipe *pPipe, + char const *pVoid); +} AT91S_Pipe, *AT91PS_Pipe; + +// types used in AT91S_Pipe +typedef AT91PS_Pipe (*AT91PF_OpenPipe) (AT91PS_Pipe, AT91PS_SvcComm, AT91PS_Buffer); +typedef void (*AT91PF_PipeWriteCallBack) (AT91S_PipeStatus, void *); +typedef void (*AT91PF_PipeReadCallBack) (AT91S_PipeStatus, void *); +typedef AT91S_PipeStatus (*AT91PF_PipeWrite) (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *), void *); +typedef AT91S_PipeStatus (*AT91PF_PipeRead) (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *), void *); +typedef AT91S_PipeStatus (*AT91PF_PipeAbortWrite) (AT91PS_Pipe); +typedef AT91S_PipeStatus (*AT91PF_PipeAbortRead) (AT91PS_Pipe); +typedef AT91S_PipeStatus (*AT91PF_PipeReset) (AT91PS_Pipe); +typedef char (*AT91PF_PipeIsWritten) (AT91PS_Pipe, char const *); +typedef char (*AT91PF_PipeIsReceived) (AT91PS_Pipe, char const *); + +// This function is called by the application +extern AT91PS_Pipe AT91F_OpenPipe( + AT91PS_Pipe pPipe, + AT91PS_SvcComm pSvcComm, + AT91PS_Buffer pBuffer); + +// Following functions are called through AT91S_Pipe pointers + +extern AT91S_PipeStatus AT91F_PipeWrite( + AT91PS_Pipe pPipe, + char const *pVoid, + unsigned int size, + AT91PF_PipeWriteCallBack callback, + void *privateData); +extern AT91S_PipeStatus AT91F_PipeRead( + AT91PS_Pipe pPipe, + char *pVoid, + unsigned int Size, + AT91PF_PipeReadCallBack callback, + void *privateData); +extern AT91S_PipeStatus AT91F_PipeAbortWrite(AT91PS_Pipe pPipe); +extern AT91S_PipeStatus AT91F_PipeAbortRead(AT91PS_Pipe pPipe); +extern AT91S_PipeStatus AT91F_PipeReset(AT91PS_Pipe pPipe); +extern char AT91F_PipeMsgWritten(AT91PS_Pipe pPipe, char const *pVoid); +extern char AT91F_PipeMsgReceived(AT91PS_Pipe pPipe, char const *pVoid); + +#ifdef DBG_DRV_PIPE +// This function parse the error number and return a string +// describing the error message +extern char const *AT91F_PipeGetError(AT91S_PipeStatus msgId); +#endif + +extern const unsigned char bit_rev[256]; + +extern void CalculateCrc32(const unsigned char *,unsigned int, unsigned int *); +extern void CalculateCrc16(const unsigned char *, unsigned int , unsigned short *); +extern void CalculateCrcHdlc(const unsigned char *, unsigned int, unsigned short *); +extern void CalculateCrc16ccitt(const unsigned char *, unsigned int , unsigned short *); + +typedef const unsigned char* AT91PS_SVC_CRC_BIT_REV ; + +typedef void (*AT91PF_SVC_CRC32) (const unsigned char *, unsigned int, unsigned int *); +typedef void (*AT91PF_SVC_CRC16) (const unsigned char *, unsigned int, unsigned short *); +typedef void (*AT91PF_SVC_CRCHDLC) (const unsigned char *, unsigned int, unsigned short *); +typedef void (*AT91PF_SVC_CRCCCITT)(const unsigned char *, unsigned int , unsigned short *); + + +typedef short (*AT91PF_Sinus) (int angle); +typedef const short * AT91PS_SINE_TAB; + +extern short AT91F_Sinus(int angle); +extern const short AT91C_SINUS180_TAB[256]; + + +typedef void (TypeAICHandler) (void) ; + + +// ROM BOOT Structure Element Definition (liv v2) +typedef struct _AT91S_MEMCDesc +{ + AT91PS_MC memc_base ; /* Peripheral base */ + unsigned char periph_id ; /* MC Peripheral Identifier */ +} AT91S_MEMCDesc, *AT91PS_MEMCDesc ; + +typedef struct _AT91S_Pio2Desc +{ + AT91PS_PIO pio_base ; /* Base Address */ + unsigned char periph_id ; /* Peripheral Identifier */ + unsigned char pio_number ; /* Total Pin Number */ +} AT91S_Pio2Desc, *AT91PS_Pio2Desc ; + +typedef struct _AT91S_SPIDesc +{ + AT91PS_SPI spi_base ; + const AT91PS_PIO pio_base ; + unsigned char periph_id ; + unsigned char pin_spck ; + unsigned char pin_miso ; + unsigned char pin_mosi ; + unsigned char pin_npcs[4] ; +} AT91S_SPIDesc, *AT91PS_SPIDesc ; + +typedef struct _AT91S_USART2Desc +{ + AT91PS_USART usart_base ; /* Peripheral base */ + const AT91PS_PIO pio_base ; /* IO controller descriptor */ + unsigned int pin_rxd ; /* RXD pin number in the PIO */ + unsigned int pin_txd ; /* TXD pin number in the PIO */ + unsigned int pin_sck ; /* SCK pin number in the PIO */ + unsigned int pin_rts ; /* RTS pin number in the PIO */ + unsigned int pin_cts ; /* CTS pin number in the PIO */ + unsigned int pin_dtr ; /* DTR pin number in the PIO */ + unsigned int pin_ri ; /* RI pin number in the PIO */ + unsigned int pin_dsr ; /* DSR pin number in the PIO */ + unsigned int pin_dcd ; /* DCD pin number in the PIO */ + unsigned int periph_id ; /* USART Peripheral Identifier */ +} AT91S_USART2Desc, *AT91PS_USART2Desc ; + +typedef struct _AT91S_TWIDesc +{ + AT91PS_TWI TWI_base ; + const AT91PS_PIO pio_base ; + unsigned int pin_sck ; + unsigned int pin_sda ; + unsigned int periph_id; +}AT91S_TWIDesc, *AT91PS_TWIDesc; + +typedef struct _AT91S_STDesc +{ + AT91PS_ST st_base ; /* Peripheral base address */ + TypeAICHandler *AsmSTHandler ; /* Assembly interrupt handler */ + unsigned char PeriphId ; /* Peripheral Identifier */ +} AT91S_STDesc, *AT91PS_STDesc; + +typedef struct _AT91S_RomBoot { + const unsigned int version; + // Peripheral descriptors + const AT91S_MEMCDesc MEMC_DESC; + const AT91S_STDesc SYSTIMER_DESC; + const AT91S_Pio2Desc PIOA_DESC; + const AT91S_Pio2Desc PIOB_DESC; + const AT91S_USART2Desc DBGU_DESC; + const AT91S_USART2Desc USART0_DESC; + const AT91S_USART2Desc USART1_DESC; + const AT91S_USART2Desc USART2_DESC; + const AT91S_USART2Desc USART3_DESC; + const AT91S_TWIDesc TWI_DESC; + const AT91S_SPIDesc SPI_DESC; + + // Objects entry + const AT91PF_OpenPipe OpenPipe; + const AT91PF_OpenSBuffer OpenSBuffer; + const unsigned int reserved1; + const AT91PF_OpenSvcXmodem OpenSvcXmodem; + const AT91PF_OpenCtlTempo OpenCtlTempo; + const unsigned int reserved2; + const unsigned int reserved3; + const unsigned int reserved4; + const AT91PF_SVC_CRC16 CRC16; + const AT91PF_SVC_CRCCCITT CRCCCITT; + const AT91PF_SVC_CRCHDLC CRCHDLC; + const AT91PF_SVC_CRC32 CRC32; + const AT91PS_SVC_CRC_BIT_REV Bit_Reverse_Array; + const AT91PS_SINE_TAB SineTab; + const AT91PF_Sinus Sine; +} AT91S_RomBoot, *AT91PS_RomBoot; + +#define AT91C_ROM_BOOT_ADDRESS ((const AT91S_RomBoot *) ( *((unsigned int *) (AT91C_BASE_ROM + 0x20))) ) + +#endif + diff --git a/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h b/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h new file mode 100644 index 0000000..43d5835 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h @@ -0,0 +1,379 @@ +//*--------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*--------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*--------------------------------------------------------------------------- +//* File Name : AT91C_MCI_Device.h +//* Object : Data Flash Atmel Description File +//* Translator : +//* +//* 1.0 26/11/02 FB : Creation +//*--------------------------------------------------------------------------- + +#ifndef AT91C_MCI_Device_h +#define AT91C_MCI_Device_h + +#include "AT91RM9200.h" +#include "lib_AT91RM9200.h" + +typedef unsigned int AT91S_MCIDeviceStatus; + +///////////////////////////////////////////////////////////////////////////////////////////////////// + +#define AT91C_CARD_REMOVED 0 +#define AT91C_MMC_CARD_INSERTED 1 +#define AT91C_SD_CARD_INSERTED 2 + +#define AT91C_NO_ARGUMENT 0x0 + +#define AT91C_FIRST_RCA 0xCAFE +#define AT91C_MAX_MCI_CARDS 10 + +#define AT91C_BUS_WIDTH_1BIT 0x00 +#define AT91C_BUS_WIDTH_4BITS 0x02 + +/* Driver State */ +#define AT91C_MCI_IDLE 0x0 +#define AT91C_MCI_TIMEOUT_ERROR 0x1 +#define AT91C_MCI_RX_SINGLE_BLOCK 0x2 +#define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3 +#define AT91C_MCI_RX_STREAM 0x4 +#define AT91C_MCI_TX_SINGLE_BLOCK 0x5 +#define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6 +#define AT91C_MCI_TX_STREAM 0x7 + +/* TimeOut */ +#define AT91C_TIMEOUT_CMDRDY 30 + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// MMC & SDCard Structures +///////////////////////////////////////////////////////////////////////////////////////////////////// + +/*-----------------------------------------------*/ +/* SDCard Device Descriptor Structure Definition */ +/*-----------------------------------------------*/ +typedef struct _AT91S_MciDeviceDesc +{ + volatile unsigned char state; + unsigned char SDCard_bus_width; + +} AT91S_MciDeviceDesc, *AT91PS_MciDeviceDesc; + +/*---------------------------------------------*/ +/* MMC & SDCard Structure Device Features */ +/*---------------------------------------------*/ +typedef struct _AT91S_MciDeviceFeatures +{ + unsigned char Card_Inserted; // (0=AT91C_CARD_REMOVED) (1=AT91C_MMC_CARD_INSERTED) (2=AT91C_SD_CARD_INSERTED) + unsigned int Relative_Card_Address; // RCA + unsigned int Max_Read_DataBlock_Length; // 2^(READ_BL_LEN) in CSD + unsigned int Max_Write_DataBlock_Length; // 2^(WRITE_BL_LEN) in CSD + unsigned char Read_Partial; // READ_BL_PARTIAL + unsigned char Write_Partial; // WRITE_BL_PARTIAL + unsigned char Erase_Block_Enable; // ERASE_BLK_EN + unsigned char Read_Block_Misalignment; // READ_BLK_MISALIGN + unsigned char Write_Block_Misalignment; // WRITE_BLK_MISALIGN + unsigned char Sector_Size; // SECTOR_SIZE + unsigned int Memory_Capacity; // Size in bits of the device + +} AT91S_MciDeviceFeatures, *AT91PS_MciDeviceFeatures ; + +/*---------------------------------------------*/ +/* MCI Device Structure Definition */ +/*---------------------------------------------*/ +typedef struct _AT91S_MciDevice +{ + AT91PS_MciDeviceDesc pMCI_DeviceDesc; // MCI device descriptor + AT91PS_MciDeviceFeatures pMCI_DeviceFeatures;// Pointer on a MCI device features array +}AT91S_MciDevice, *AT91PS_MciDevice; + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// MCI_CMD Register Value +///////////////////////////////////////////////////////////////////////////////////////////////////// +#define AT91C_POWER_ON_INIT (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_INIT | AT91C_MCI_OPDCMD) + +///////////////////////////////////////////////////////////////// +// Class 0 & 1 commands: Basic commands and Read Stream commands +///////////////////////////////////////////////////////////////// + +#define AT91C_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE ) +#define AT91C_MMC_GO_IDLE_STATE_CMD (0 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_OPDCMD) +#define AT91C_MMC_SEND_OP_COND_CMD (1 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD) +#define AT91C_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 ) +#define AT91C_MMC_ALL_SEND_CID_CMD (2 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_OPDCMD) +#define AT91C_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) +#define AT91C_MMC_SET_RELATIVE_ADDR_CMD (3 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT | AT91C_MCI_OPDCMD) + +#define AT91C_SET_DSR_CMD (4 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_NO | AT91C_MCI_MAXLAT ) // no tested + +#define AT91C_SEL_DESEL_CARD_CMD (7 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) +#define AT91C_SEND_CSD_CMD (9 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT ) +#define AT91C_SEND_CID_CMD (10 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_136 | AT91C_MCI_MAXLAT ) +#define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD (11 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) + +#define AT91C_STOP_TRANSMISSION_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) +#define AT91C_STOP_TRANSMISSION_SYNC_CMD (12 | AT91C_MCI_TRCMD_STOP | AT91C_MCI_SPCMD_SYNC | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) +#define AT91C_SEND_STATUS_CMD (13 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) +#define AT91C_GO_INACTIVE_STATE_CMD (15 | AT91C_MCI_RSPTYP_NO ) + +//*------------------------------------------------ +//* Class 2 commands: Block oriented Read commands +//*------------------------------------------------ + +#define AT91C_SET_BLOCKLEN_CMD (16 | AT91C_MCI_TRCMD_NO | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT ) +#define AT91C_READ_SINGLE_BLOCK_CMD (17 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_BLOCK | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT) +#define AT91C_READ_MULTIPLE_BLOCK_CMD (18 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | AT91C_MCI_TRTYP_MULTIPLE | AT91C_MCI_TRDIR | AT91C_MCI_MAXLAT) + +//*-------------------------------------------- +//* Class 3 commands: Sequential write commands +//*-------------------------------------------- + +#define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 & ~(AT91C_MCI_TRDIR) | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT ) // MMC + +//*------------------------------------------------ +//* Class 4 commands: Block oriented write commands +//*------------------------------------------------ + +#define AT91C_WRITE_BLOCK_CMD (24 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_BLOCK & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) +#define AT91C_WRITE_MULTIPLE_BLOCK_CMD (25 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_START | (AT91C_MCI_TRTYP_MULTIPLE & ~(AT91C_MCI_TRDIR)) | AT91C_MCI_MAXLAT) +#define AT91C_PROGRAM_CSD_CMD (27 | AT91C_MCI_RSPTYP_48 ) + + +//*---------------------------------------- +//* Class 6 commands: Group Write protect +//*---------------------------------------- + +#define AT91C_SET_WRITE_PROT_CMD (28 | AT91C_MCI_RSPTYP_48 ) +#define AT91C_CLR_WRITE_PROT_CMD (29 | AT91C_MCI_RSPTYP_48 ) +#define AT91C_SEND_WRITE_PROT_CMD (30 | AT91C_MCI_RSPTYP_48 ) + + +//*---------------------------------------- +//* Class 5 commands: Erase commands +//*---------------------------------------- + +#define AT91C_TAG_SECTOR_START_CMD (32 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) +#define AT91C_TAG_SECTOR_END_CMD (33 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) +#define AT91C_MMC_UNTAG_SECTOR_CMD (34 | AT91C_MCI_RSPTYP_48 ) +#define AT91C_MMC_TAG_ERASE_GROUP_START_CMD (35 | AT91C_MCI_RSPTYP_48 ) +#define AT91C_MMC_TAG_ERASE_GROUP_END_CMD (36 | AT91C_MCI_RSPTYP_48 ) +#define AT91C_MMC_UNTAG_ERASE_GROUP_CMD (37 | AT91C_MCI_RSPTYP_48 ) +#define AT91C_ERASE_CMD (38 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT ) + +//*---------------------------------------- +//* Class 7 commands: Lock commands +//*---------------------------------------- + +#define AT91C_LOCK_UNLOCK (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested + +//*----------------------------------------------- +// Class 8 commands: Application specific commands +//*----------------------------------------------- + +#define AT91C_APP_CMD (55 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) +#define AT91C_GEN_CMD (56 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) // no tested + +#define AT91C_SDCARD_SET_BUS_WIDTH_CMD (6 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) +#define AT91C_SDCARD_STATUS_CMD (13 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) +#define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) +#define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) +#define AT91C_SDCARD_APP_OP_COND_CMD (41 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO ) +#define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD (42 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) +#define AT91C_SDCARD_SEND_SCR_CMD (51 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) + +#define AT91C_SDCARD_APP_ALL_CMD (AT91C_SDCARD_SET_BUS_WIDTH_CMD +\ + AT91C_SDCARD_STATUS_CMD +\ + AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\ + AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\ + AT91C_SDCARD_APP_OP_COND_CMD +\ + AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\ + AT91C_SDCARD_SEND_SCR_CMD) + +//*---------------------------------------- +//* Class 9 commands: IO Mode commands +//*---------------------------------------- + +#define AT91C_MMC_FAST_IO_CMD (39 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT) +#define AT91C_MMC_GO_IRQ_STATE_CMD (40 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT) + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// Functions returnals +///////////////////////////////////////////////////////////////////////////////////////////////////// +#define AT91C_CMD_SEND_OK 0 // Command ok +#define AT91C_CMD_SEND_ERROR -1 // Command failed +#define AT91C_INIT_OK 2 // Init Successfull +#define AT91C_INIT_ERROR 3 // Init Failed +#define AT91C_READ_OK 4 // Read Successfull +#define AT91C_READ_ERROR 5 // Read Failed +#define AT91C_WRITE_OK 6 // Write Successfull +#define AT91C_WRITE_ERROR 7 // Write Failed +#define AT91C_ERASE_OK 8 // Erase Successfull +#define AT91C_ERASE_ERROR 9 // Erase Failed +#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull +#define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// MCI_SR Errors +///////////////////////////////////////////////////////////////////////////////////////////////////// +#define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE |\ + AT91C_MCI_OVRE |\ + AT91C_MCI_DTOE |\ + AT91C_MCI_DCRCE |\ + AT91C_MCI_RTOE |\ + AT91C_MCI_RENDE |\ + AT91C_MCI_RCRCE |\ + AT91C_MCI_RDIRE |\ + AT91C_MCI_RINDE) + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// OCR Register +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define AT91C_VDD_16_17 (1 << 4) +#define AT91C_VDD_17_18 (1 << 5) +#define AT91C_VDD_18_19 (1 << 6) +#define AT91C_VDD_19_20 (1 << 7) +#define AT91C_VDD_20_21 (1 << 8) +#define AT91C_VDD_21_22 (1 << 9) +#define AT91C_VDD_22_23 (1 << 10) +#define AT91C_VDD_23_24 (1 << 11) +#define AT91C_VDD_24_25 (1 << 12) +#define AT91C_VDD_25_26 (1 << 13) +#define AT91C_VDD_26_27 (1 << 14) +#define AT91C_VDD_27_28 (1 << 15) +#define AT91C_VDD_28_29 (1 << 16) +#define AT91C_VDD_29_30 (1 << 17) +#define AT91C_VDD_30_31 (1 << 18) +#define AT91C_VDD_31_32 (1 << 19) +#define AT91C_VDD_32_33 (1 << 20) +#define AT91C_VDD_33_34 (1 << 21) +#define AT91C_VDD_34_35 (1 << 22) +#define AT91C_VDD_35_36 (1 << 23) +#define AT91C_CARD_POWER_UP_BUSY (1 << 31) + +#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 +\ + AT91C_VDD_28_29 +\ + AT91C_VDD_29_30 +\ + AT91C_VDD_30_31 +\ + AT91C_VDD_31_32 +\ + AT91C_VDD_32_33) + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1) +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus +#define AT91C_SR_IDLE (0 << 9) +#define AT91C_SR_READY (1 << 9) +#define AT91C_SR_IDENT (2 << 9) +#define AT91C_SR_STBY (3 << 9) +#define AT91C_SR_TRAN (4 << 9) +#define AT91C_SR_DATA (5 << 9) +#define AT91C_SR_RCV (6 << 9) +#define AT91C_SR_PRG (7 << 9) +#define AT91C_SR_DIS (8 << 9) + +#define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN) + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// MMC CSD register header File +// AT91C_CSD_xxx_S for shift value +// AT91C_CSD_xxx_M for mask value +///////////////////////////////////////////////////////////////////////////////////////////////////// + +// First Response INT <=> CSD[3] : bits 0 to 31 +#define AT91C_CSD_BIT0_S 0 // [0:0] +#define AT91C_CSD_BIT0_M 0x01 +#define AT91C_CSD_CRC_S 1 // [7:1] +#define AT91C_CSD_CRC_M 0x7F +#define AT91C_CSD_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility +#define AT91C_CSD_MMC_ECC_M 0x03 +#define AT91C_CSD_FILE_FMT_S 10 // [11:10] +#define AT91C_CSD_FILE_FMT_M 0x03 +#define AT91C_CSD_TMP_WP_S 12 // [12:12] +#define AT91C_CSD_TMP_WP_M 0x01 +#define AT91C_CSD_PERM_WP_S 13 // [13:13] +#define AT91C_CSD_PERM_WP_M 0x01 +#define AT91C_CSD_COPY_S 14 // [14:14] +#define AT91C_CSD_COPY_M 0x01 +#define AT91C_CSD_FILE_FMT_GRP_S 15 // [15:15] +#define AT91C_CSD_FILE_FMT_GRP_M 0x01 +// reserved 16 // [20:16] +// reserved 0x1F +#define AT91C_CSD_WBLOCK_P_S 21 // [21:21] +#define AT91C_CSD_WBLOCK_P_M 0x01 +#define AT91C_CSD_WBLEN_S 22 // [25:22] +#define AT91C_CSD_WBLEN_M 0x0F +#define AT91C_CSD_R2W_F_S 26 // [28:26] +#define AT91C_CSD_R2W_F_M 0x07 +#define AT91C_CSD_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility +#define AT91C_CSD_MMC_DEF_ECC_M 0x03 +#define AT91C_CSD_WP_GRP_EN_S 31 // [31:31] +#define AT91C_CSD_WP_GRP_EN_M 0x01 + +// Seconde Response INT <=> CSD[2] : bits 32 to 63 +#define AT91C_CSD_v21_WP_GRP_SIZE_S 0 // [38:32] +#define AT91C_CSD_v21_WP_GRP_SIZE_M 0x7F +#define AT91C_CSD_v21_SECT_SIZE_S 7 // [45:39] +#define AT91C_CSD_v21_SECT_SIZE_M 0x7F +#define AT91C_CSD_v21_ER_BLEN_EN_S 14 // [46:46] +#define AT91C_CSD_v21_ER_BLEN_EN_M 0x01 + +#define AT91C_CSD_v22_WP_GRP_SIZE_S 0 // [36:32] +#define AT91C_CSD_v22_WP_GRP_SIZE_M 0x1F +#define AT91C_CSD_v22_ER_GRP_SIZE_S 5 // [41:37] +#define AT91C_CSD_v22_ER_GRP_SIZE_M 0x1F +#define AT91C_CSD_v22_SECT_SIZE_S 10 // [46:42] +#define AT91C_CSD_v22_SECT_SIZE_M 0x1F + +#define AT91C_CSD_C_SIZE_M_S 15 // [49:47] +#define AT91C_CSD_C_SIZE_M_M 0x07 +#define AT91C_CSD_VDD_WMAX_S 18 // [52:50] +#define AT91C_CSD_VDD_WMAX_M 0x07 +#define AT91C_CSD_VDD_WMIN_S 21 // [55:53] +#define AT91C_CSD_VDD_WMIN_M 0x07 +#define AT91C_CSD_RCUR_MAX_S 24 // [58:56] +#define AT91C_CSD_RCUR_MAX_M 0x07 +#define AT91C_CSD_RCUR_MIN_S 27 // [61:59] +#define AT91C_CSD_RCUR_MIN_M 0x07 +#define AT91C_CSD_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE +#define AT91C_CSD_CSIZE_L_M 0x03 + +// Third Response INT <=> CSD[1] : bits 64 to 95 +#define AT91C_CSD_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE +#define AT91C_CSD_CSIZE_H_M 0x03FF +// reserved 10 // [75:74] +// reserved 0x03 +#define AT91C_CSD_DSR_I_S 12 // [76:76] +#define AT91C_CSD_DSR_I_M 0x01 +#define AT91C_CSD_RD_B_MIS_S 13 // [77:77] +#define AT91C_CSD_RD_B_MIS_M 0x01 +#define AT91C_CSD_WR_B_MIS_S 14 // [78:78] +#define AT91C_CSD_WR_B_MIS_M 0x01 +#define AT91C_CSD_RD_B_PAR_S 15 // [79:79] +#define AT91C_CSD_RD_B_PAR_M 0x01 +#define AT91C_CSD_RD_B_LEN_S 16 // [83:80] +#define AT91C_CSD_RD_B_LEN_M 0x0F +#define AT91C_CSD_CCC_S 20 // [95:84] +#define AT91C_CSD_CCC_M 0x0FFF + +// Fourth Response INT <=> CSD[0] : bits 96 to 127 +#define AT91C_CSD_TRANS_SPEED_S 0 // [103:96] +#define AT91C_CSD_TRANS_SPEED_M 0xFF +#define AT91C_CSD_NSAC_S 8 // [111:104] +#define AT91C_CSD_NSAC_M 0xFF +#define AT91C_CSD_TAAC_S 16 // [119:112] +#define AT91C_CSD_TAAC_M 0xFF +// reserved 24 // [121:120] +// reserved 0x03 +#define AT91C_CSD_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility +#define AT91C_CSD_MMC_SPEC_VERS_M 0x0F +#define AT91C_CSD_STRUCT_S 30 // [127:126] +#define AT91C_CSD_STRUCT_M 0x03 + +///////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif + diff --git a/target/linux/at91/image/dfboot/src/include/AT91RM9200.h b/target/linux/at91/image/dfboot/src/include/AT91RM9200.h new file mode 100644 index 0000000..0cd153b --- /dev/null +++ b/target/linux/at91/image/dfboot/src/include/AT91RM9200.h @@ -0,0 +1,2745 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91RM9200.h +// Object : AT91RM9200 definitions +// Generated : AT91 SW Application Group 11/19/2003 (17:20:50) +// +// CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// +// CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// +// CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// +// CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// +// CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// +// CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// +// CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// +// CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// +// CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// +// CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// +// CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// +// CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// +// CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// +// CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// +// CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// +// ---------------------------------------------------------------------------- + +#ifndef AT91RM9200_H +#define AT91RM9200_H + +typedef volatile unsigned int AT91_REG;// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_C1R; // Chip ID1 Register + AT91_REG DBGU_C2R; // Chip ID2 Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[85]; // + AT91_REG PIOC_PER; // PIO Enable Register + AT91_REG PIOC_PDR; // PIO Disable Register + AT91_REG PIOC_PSR; // PIO Status Register + AT91_REG Reserved20[1]; // + AT91_REG PIOC_OER; // Output Enable Register + AT91_REG PIOC_ODR; // Output Disable Registerr + AT91_REG PIOC_OSR; // Output Status Register + AT91_REG Reserved21[1]; // + AT91_REG PIOC_IFER; // Input Filter Enable Register + AT91_REG PIOC_IFDR; // Input Filter Disable Register + AT91_REG PIOC_IFSR; // Input Filter Status Register + AT91_REG Reserved22[1]; // + AT91_REG PIOC_SODR; // Set Output Data Register + AT91_REG PIOC_CODR; // Clear Output Data Register + AT91_REG PIOC_ODSR; // Output Data Status Register + AT91_REG PIOC_PDSR; // Pin Data Status Register + AT91_REG PIOC_IER; // Interrupt Enable Register + AT91_REG PIOC_IDR; // Interrupt Disable Register + AT91_REG PIOC_IMR; // Interrupt Mask Register + AT91_REG PIOC_ISR; // Interrupt Status Register + AT91_REG PIOC_MDER; // Multi-driver Enable Register + AT91_REG PIOC_MDDR; // Multi-driver Disable Register + AT91_REG PIOC_MDSR; // Multi-driver Status Register + AT91_REG Reserved23[1]; // + AT91_REG PIOC_PPUDR; // Pull-up Disable Register + AT91_REG PIOC_PPUER; // Pull-up Enable Register + AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved24[1]; // + AT91_REG PIOC_ASR; // Select A Register + AT91_REG PIOC_BSR; // Select B Register + AT91_REG PIOC_ABSR; // AB Select Status Register + AT91_REG Reserved25[9]; // + AT91_REG PIOC_OWER; // Output Write Enable Register + AT91_REG PIOC_OWDR; // Output Write Disable Register + AT91_REG PIOC_OWSR; // Output Write Status Register + AT91_REG Reserved26[85]; // + AT91_REG PIOD_PER; // PIO Enable Register + AT91_REG PIOD_PDR; // PIO Disable Register + AT91_REG PIOD_PSR; // PIO Status Register + AT91_REG Reserved27[1]; // + AT91_REG PIOD_OER; // Output Enable Register + AT91_REG PIOD_ODR; // Output Disable Registerr + AT91_REG PIOD_OSR; // Output Status Register + AT91_REG Reserved28[1]; // + AT91_REG PIOD_IFER; // Input Filter Enable Register + AT91_REG PIOD_IFDR; // Input Filter Disable Register + AT91_REG PIOD_IFSR; // Input Filter Status Register + AT91_REG Reserved29[1]; // + AT91_REG PIOD_SODR; // Set Output Data Register + AT91_REG PIOD_CODR; // Clear Output Data Register + AT91_REG PIOD_ODSR; // Output Data Status Register + AT91_REG PIOD_PDSR; // Pin Data Status Register + AT91_REG PIOD_IER; // Interrupt Enable Register + AT91_REG PIOD_IDR; // Interrupt Disable Register + AT91_REG PIOD_IMR; // Interrupt Mask Register + AT91_REG PIOD_ISR; // Interrupt Status Register + AT91_REG PIOD_MDER; // Multi-driver Enable Register + AT91_REG PIOD_MDDR; // Multi-driver Disable Register + AT91_REG PIOD_MDSR; // Multi-driver Status Register + AT91_REG Reserved30[1]; // + AT91_REG PIOD_PPUDR; // Pull-up Disable Register + AT91_REG PIOD_PPUER; // Pull-up Enable Register + AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved31[1]; // + AT91_REG PIOD_ASR; // Select A Register + AT91_REG PIOD_BSR; // Select B Register + AT91_REG PIOD_ABSR; // AB Select Status Register + AT91_REG Reserved32[9]; // + AT91_REG PIOD_OWER; // Output Write Enable Register + AT91_REG PIOD_OWDR; // Output Write Disable Register + AT91_REG PIOD_OWSR; // Output Write Status Register + AT91_REG Reserved33[85]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved34[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved35[1]; // + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG CKGR_PLLAR; // PLL A Register + AT91_REG CKGR_PLLBR; // PLL B Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved36[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved37[36]; // + AT91_REG ST_CR; // Control Register + AT91_REG ST_PIMR; // Period Interval Mode Register + AT91_REG ST_WDMR; // Watchdog Mode Register + AT91_REG ST_RTMR; // Real-time Mode Register + AT91_REG ST_SR; // Status Register + AT91_REG ST_IER; // Interrupt Enable Register + AT91_REG ST_IDR; // Interrupt Disable Register + AT91_REG ST_IMR; // Interrupt Mask Register + AT91_REG ST_RTAR; // Real-time Alarm Register + AT91_REG ST_CRTR; // Current Real-time Register + AT91_REG Reserved38[54]; // + AT91_REG RTC_CR; // Control Register + AT91_REG RTC_MR; // Mode Register + AT91_REG RTC_TIMR; // Time Register + AT91_REG RTC_CALR; // Calendar Register + AT91_REG RTC_TIMALR; // Time Alarm Register + AT91_REG RTC_CALALR; // Calendar Alarm Register + AT91_REG RTC_SR; // Status Register + AT91_REG RTC_SCCR; // Status Clear Command Register + AT91_REG RTC_IER; // Interrupt Enable Register + AT91_REG RTC_IDR; // Interrupt Disable Register + AT91_REG RTC_IMR; // Interrupt Mask Register + AT91_REG RTC_VER; // Valid Entry Register + AT91_REG Reserved39[52]; // + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved40[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved41[2]; // + AT91_REG EBI_CSA; // Chip Select Assignment Register + AT91_REG EBI_CFGR; // Configuration Register + AT91_REG Reserved42[2]; // + AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register + AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register + AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register + AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register + AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register + AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG Reserved43[3]; // + AT91_REG EBI_BFC_MR; // BFC Mode Register +} AT91S_SYS, *AT91PS_SYS; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register +} AT91S_MC, *AT91PS_MC; + +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU ((unsigned int) 0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT ((unsigned int) 0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE ((unsigned int) 0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB ((unsigned int) 0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB ((unsigned int) 0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB ((unsigned int) 0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB ((unsigned int) 0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB ((unsigned int) 0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB ((unsigned int) 0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB ((unsigned int) 0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB ((unsigned int) 0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB ((unsigned int) 0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB ((unsigned int) 0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB ((unsigned int) 0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB ((unsigned int) 0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB ((unsigned int) 0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB ((unsigned int) 0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB ((unsigned int) 0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB ((unsigned int) 0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB ((unsigned int) 0x1 << 0) // (MC) Protection Unit enable Bit + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface +// ***************************************************************************** +typedef struct _AT91S_RTC { + AT91_REG RTC_CR; // Control Register + AT91_REG RTC_MR; // Mode Register + AT91_REG RTC_TIMR; // Time Register + AT91_REG RTC_CALR; // Calendar Register + AT91_REG RTC_TIMALR; // Time Alarm Register + AT91_REG RTC_CALALR; // Calendar Alarm Register + AT91_REG RTC_SR; // Status Register + AT91_REG RTC_SCCR; // Status Clear Command Register + AT91_REG RTC_IER; // Interrupt Enable Register + AT91_REG RTC_IDR; // Interrupt Disable Register + AT91_REG RTC_IMR; // Interrupt Mask Register + AT91_REG RTC_VER; // Valid Entry Register +} AT91S_RTC, *AT91PS_RTC; + +// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- +#define AT91C_RTC_UPDTIM ((unsigned int) 0x1 << 0) // (RTC) Update Request Time Register +#define AT91C_RTC_UPDCAL ((unsigned int) 0x1 << 1) // (RTC) Update Request Calendar Register +#define AT91C_RTC_TIMEVSEL ((unsigned int) 0x3 << 8) // (RTC) Time Event Selection +#define AT91C_RTC_TIMEVSEL_MINUTE ((unsigned int) 0x0 << 8) // (RTC) Minute change. +#define AT91C_RTC_TIMEVSEL_HOUR ((unsigned int) 0x1 << 8) // (RTC) Hour change. +#define AT91C_RTC_TIMEVSEL_DAY24 ((unsigned int) 0x2 << 8) // (RTC) Every day at midnight. +#define AT91C_RTC_TIMEVSEL_DAY12 ((unsigned int) 0x3 << 8) // (RTC) Every day at noon. +#define AT91C_RTC_CALEVSEL ((unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection +#define AT91C_RTC_CALEVSEL_WEEK ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). +#define AT91C_RTC_CALEVSEL_MONTH ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). +#define AT91C_RTC_CALEVSEL_YEAR ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). +// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- +#define AT91C_RTC_HRMOD ((unsigned int) 0x1 << 0) // (RTC) 12-24 hour Mode +// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- +#define AT91C_RTC_SEC ((unsigned int) 0x7F << 0) // (RTC) Current Second +#define AT91C_RTC_MIN ((unsigned int) 0x7F << 8) // (RTC) Current Minute +#define AT91C_RTC_HOUR ((unsigned int) 0x1F << 16) // (RTC) Current Hour +#define AT91C_RTC_AMPM ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator +// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- +#define AT91C_RTC_CENT ((unsigned int) 0x3F << 0) // (RTC) Current Century +#define AT91C_RTC_YEAR ((unsigned int) 0xFF << 8) // (RTC) Current Year +#define AT91C_RTC_MONTH ((unsigned int) 0x1F << 16) // (RTC) Current Month +#define AT91C_RTC_DAY ((unsigned int) 0x7 << 21) // (RTC) Current Day +#define AT91C_RTC_DATE ((unsigned int) 0x3F << 24) // (RTC) Current Date +// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- +#define AT91C_RTC_SECEN ((unsigned int) 0x1 << 7) // (RTC) Second Alarm Enable +#define AT91C_RTC_MINEN ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm +#define AT91C_RTC_HOUREN ((unsigned int) 0x1 << 23) // (RTC) Current Hour +// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- +#define AT91C_RTC_MONTHEN ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable +#define AT91C_RTC_DATEEN ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable +// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- +#define AT91C_RTC_ACKUPD ((unsigned int) 0x1 << 0) // (RTC) Acknowledge for Update +#define AT91C_RTC_ALARM ((unsigned int) 0x1 << 1) // (RTC) Alarm Flag +#define AT91C_RTC_SECEV ((unsigned int) 0x1 << 2) // (RTC) Second Event +#define AT91C_RTC_TIMEV ((unsigned int) 0x1 << 3) // (RTC) Time Event +#define AT91C_RTC_CALEV ((unsigned int) 0x1 << 4) // (RTC) Calendar event +// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- +// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- +// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- +// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- +// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- +#define AT91C_RTC_NVTIM ((unsigned int) 0x1 << 0) // (RTC) Non valid Time +#define AT91C_RTC_NVCAL ((unsigned int) 0x1 << 1) // (RTC) Non valid Calendar +#define AT91C_RTC_NVTIMALR ((unsigned int) 0x1 << 2) // (RTC) Non valid time Alarm +#define AT91C_RTC_NVCALALR ((unsigned int) 0x1 << 3) // (RTC) Nonvalid Calendar Alarm + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Timer Interface +// ***************************************************************************** +typedef struct _AT91S_ST { + AT91_REG ST_CR; // Control Register + AT91_REG ST_PIMR; // Period Interval Mode Register + AT91_REG ST_WDMR; // Watchdog Mode Register + AT91_REG ST_RTMR; // Real-time Mode Register + AT91_REG ST_SR; // Status Register + AT91_REG ST_IER; // Interrupt Enable Register + AT91_REG ST_IDR; // Interrupt Disable Register + AT91_REG ST_IMR; // Interrupt Mask Register + AT91_REG ST_RTAR; // Real-time Alarm Register + AT91_REG ST_CRTR; // Current Real-time Register +} AT91S_ST, *AT91PS_ST; + +// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- +#define AT91C_ST_WDRST ((unsigned int) 0x1 << 0) // (ST) Watchdog Timer Restart +// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- +#define AT91C_ST_PIV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart +// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- +#define AT91C_ST_WDV ((unsigned int) 0xFFFF << 0) // (ST) Watchdog Timer Restart +#define AT91C_ST_RSTEN ((unsigned int) 0x1 << 16) // (ST) Reset Enable +#define AT91C_ST_EXTEN ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable +// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- +#define AT91C_ST_RTPRES ((unsigned int) 0xFFFF << 0) // (ST) Real-time Timer Prescaler Value +// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- +#define AT91C_ST_PITS ((unsigned int) 0x1 << 0) // (ST) Period Interval Timer Interrupt +#define AT91C_ST_WDOVF ((unsigned int) 0x1 << 1) // (ST) Watchdog Overflow +#define AT91C_ST_RTTINC ((unsigned int) 0x1 << 2) // (ST) Real-time Timer Increment +#define AT91C_ST_ALMS ((unsigned int) 0x1 << 3) // (ST) Alarm Status +// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- +// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- +// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- +// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- +#define AT91C_ST_ALMV ((unsigned int) 0xFFFFF << 0) // (ST) Alarm Value Value +// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- +#define AT91C_ST_CRTV ((unsigned int) 0xFFFFF << 0) // (ST) Current Real-time Value + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[5]; // + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved2[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) // (PMC) USB Device Port Clock +#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend +#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) // (PMC) USB Host Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected +#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division +#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same +#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock +#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is three times faster than the master clock +#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) // (PMC) The processor clock is four times faster than the master clock +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG CKGR_PLLAR; // PLL A Register + AT91_REG CKGR_PLLBR; // PLL B Register +} AT91S_CKGR, *AT91PS_CKGR; + +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) // (CKGR) Oscillator Test +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- +#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL A Counter +#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range +#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier +#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source +// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL B Counter +#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range +#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier +#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports +#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) // (CKGR) PLL Use + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pad Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_C1R; // Chip ID1 Register + AT91_REG DBGU_C2R; // Chip ID2 Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; + +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; + +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; + +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG SSC_RC0R; // Receive Compare 0 Register + AT91_REG SSC_RC1R; // Receive Compare 1 Register + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG US_XXR; // XON_XOFF Register + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved1[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; + +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register +} AT91S_TWI, *AT91PS_TWI; + +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN ((unsigned int) 0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS ((unsigned int) 0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD ((unsigned int) 0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC ((unsigned int) 0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC ((unsigned int) 0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST ((unsigned int) 0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Multimedia Card Interface +// ***************************************************************************** +typedef struct _AT91S_MCI { + AT91_REG MCI_CR; // MCI Control Register + AT91_REG MCI_MR; // MCI Mode Register + AT91_REG MCI_DTOR; // MCI Data Timeout Register + AT91_REG MCI_SDCR; // MCI SD Card Register + AT91_REG MCI_ARGR; // MCI Argument Register + AT91_REG MCI_CMDR; // MCI Command Register + AT91_REG Reserved0[2]; // + AT91_REG MCI_RSPR[4]; // MCI Response Register + AT91_REG MCI_RDR; // MCI Receive Data Register + AT91_REG MCI_TDR; // MCI Transmit Data Register + AT91_REG Reserved1[2]; // + AT91_REG MCI_SR; // MCI Status Register + AT91_REG MCI_IER; // MCI Interrupt Enable Register + AT91_REG MCI_IDR; // MCI Interrupt Disable Register + AT91_REG MCI_IMR; // MCI Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG MCI_RPR; // Receive Pointer Register + AT91_REG MCI_RCR; // Receive Counter Register + AT91_REG MCI_TPR; // Transmit Pointer Register + AT91_REG MCI_TCR; // Transmit Counter Register + AT91_REG MCI_RNPR; // Receive Next Pointer Register + AT91_REG MCI_RNCR; // Receive Next Counter Register + AT91_REG MCI_TNPR; // Transmit Next Pointer Register + AT91_REG MCI_TNCR; // Transmit Next Counter Register + AT91_REG MCI_PTCR; // PDC Transfer Control Register + AT91_REG MCI_PTSR; // PDC Transfer Status Register +} AT91S_MCI, *AT91PS_MCI; + +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +#define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable +#define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable +#define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable +#define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +#define AT91C_MCI_CLKDIV ((unsigned int) 0x1 << 0) // (MCI) Clock Divider +#define AT91C_MCI_PWSDIV ((unsigned int) 0x1 << 8) // (MCI) Power Saving Divider +#define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value +#define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode +#define AT91C_MCI_BLKLEN ((unsigned int) 0x1 << 18) // (MCI) Data Block Length +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +#define AT91C_MCI_DTOCYC ((unsigned int) 0x1 << 0) // (MCI) Data Timeout Cycle Number +#define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier +#define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1 +#define AT91C_MCI_DTOMUL_16 ((unsigned int) 0x1 << 4) // (MCI) DTOCYC x 16 +#define AT91C_MCI_DTOMUL_128 ((unsigned int) 0x2 << 4) // (MCI) DTOCYC x 128 +#define AT91C_MCI_DTOMUL_256 ((unsigned int) 0x3 << 4) // (MCI) DTOCYC x 256 +#define AT91C_MCI_DTOMUL_1024 ((unsigned int) 0x4 << 4) // (MCI) DTOCYC x 1024 +#define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096 +#define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536 +#define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576 +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +#define AT91C_MCI_SCDSEL ((unsigned int) 0x1 << 0) // (MCI) SD Card Selector +#define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +#define AT91C_MCI_CMDNB ((unsigned int) 0x1F << 0) // (MCI) Command Number +#define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type +#define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response +#define AT91C_MCI_RSPTYP_48 ((unsigned int) 0x1 << 6) // (MCI) 48-bit response +#define AT91C_MCI_RSPTYP_136 ((unsigned int) 0x2 << 6) // (MCI) 136-bit response +#define AT91C_MCI_SPCMD ((unsigned int) 0x7 << 8) // (MCI) Special CMD +#define AT91C_MCI_SPCMD_NONE ((unsigned int) 0x0 << 8) // (MCI) Not a special CMD +#define AT91C_MCI_SPCMD_INIT ((unsigned int) 0x1 << 8) // (MCI) Initialization CMD +#define AT91C_MCI_SPCMD_SYNC ((unsigned int) 0x2 << 8) // (MCI) Synchronized CMD +#define AT91C_MCI_SPCMD_IT_CMD ((unsigned int) 0x4 << 8) // (MCI) Interrupt command +#define AT91C_MCI_SPCMD_IT_REP ((unsigned int) 0x5 << 8) // (MCI) Interrupt response +#define AT91C_MCI_OPDCMD ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command +#define AT91C_MCI_MAXLAT ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond +#define AT91C_MCI_TRCMD ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD +#define AT91C_MCI_TRCMD_NO ((unsigned int) 0x0 << 16) // (MCI) No transfer +#define AT91C_MCI_TRCMD_START ((unsigned int) 0x1 << 16) // (MCI) Start transfer +#define AT91C_MCI_TRCMD_STOP ((unsigned int) 0x2 << 16) // (MCI) Stop transfer +#define AT91C_MCI_TRDIR ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction +#define AT91C_MCI_TRTYP ((unsigned int) 0x3 << 19) // (MCI) Transfer Type +#define AT91C_MCI_TRTYP_BLOCK ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type +#define AT91C_MCI_TRTYP_MULTIPLE ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type +#define AT91C_MCI_TRTYP_STREAM ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +#define AT91C_MCI_CMDRDY ((unsigned int) 0x1 << 0) // (MCI) Command Ready flag +#define AT91C_MCI_RXRDY ((unsigned int) 0x1 << 1) // (MCI) RX Ready flag +#define AT91C_MCI_TXRDY ((unsigned int) 0x1 << 2) // (MCI) TX Ready flag +#define AT91C_MCI_BLKE ((unsigned int) 0x1 << 3) // (MCI) Data Block Transfer Ended flag +#define AT91C_MCI_DTIP ((unsigned int) 0x1 << 4) // (MCI) Data Transfer in Progress flag +#define AT91C_MCI_NOTBUSY ((unsigned int) 0x1 << 5) // (MCI) Data Line Not Busy flag +#define AT91C_MCI_ENDRX ((unsigned int) 0x1 << 6) // (MCI) End of RX Buffer flag +#define AT91C_MCI_ENDTX ((unsigned int) 0x1 << 7) // (MCI) End of TX Buffer flag +#define AT91C_MCI_RXBUFF ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag +#define AT91C_MCI_TXBUFE ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag +#define AT91C_MCI_RINDE ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag +#define AT91C_MCI_RDIRE ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag +#define AT91C_MCI_RCRCE ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag +#define AT91C_MCI_RENDE ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag +#define AT91C_MCI_RTOE ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag +#define AT91C_MCI_DCRCE ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag +#define AT91C_MCI_DTOE ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag +#define AT91C_MCI_OVRE ((unsigned int) 0x1 << 30) // (MCI) Overrun flag +#define AT91C_MCI_UNRE ((unsigned int) 0x1 << 31) // (MCI) Underrun flag +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register +} AT91S_UDP, *AT91PS_UDP; + +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 ((unsigned int) 0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 ((unsigned int) 0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 ((unsigned int) 0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 ((unsigned int) 0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Host Interface +// ***************************************************************************** +typedef struct _AT91S_UHP { + AT91_REG UHP_HcRevision; // Revision + AT91_REG UHP_HcControl; // Operating modes for the Host Controller + AT91_REG UHP_HcCommandStatus; // Command & status Register + AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register + AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register + AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register + AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area + AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor + AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list + AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register + AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list + AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list + AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor + AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs + AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame + AT91_REG UHP_HcFmNumber; // Frame number + AT91_REG UHP_HcPeriodicStart; // Periodic Start + AT91_REG UHP_HcLSThreshold; // LS Threshold + AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A + AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B + AT91_REG UHP_HcRhStatus; // Root Hub Status register + AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register +} AT91S_UHP, *AT91PS_UHP; + + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC +// ***************************************************************************** +typedef struct _AT91S_EMAC { + AT91_REG EMAC_CTL; // Network Control Register + AT91_REG EMAC_CFG; // Network Configuration Register + AT91_REG EMAC_SR; // Network Status Register + AT91_REG EMAC_TAR; // Transmit Address Register + AT91_REG EMAC_TCR; // Transmit Control Register + AT91_REG EMAC_TSR; // Transmit Status Register + AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer + AT91_REG Reserved0[1]; // + AT91_REG EMAC_RSR; // Receive Status Register + AT91_REG EMAC_ISR; // Interrupt Status Register + AT91_REG EMAC_IER; // Interrupt Enable Register + AT91_REG EMAC_IDR; // Interrupt Disable Register + AT91_REG EMAC_IMR; // Interrupt Mask Register + AT91_REG EMAC_MAN; // PHY Maintenance Register + AT91_REG Reserved1[2]; // + AT91_REG EMAC_FRA; // Frames Transmitted OK Register + AT91_REG EMAC_SCOL; // Single Collision Frame Register + AT91_REG EMAC_MCOL; // Multiple Collision Frame Register + AT91_REG EMAC_OK; // Frames Received OK Register + AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register + AT91_REG EMAC_ALE; // Alignment Error Register + AT91_REG EMAC_DTE; // Deferred Transmission Frame Register + AT91_REG EMAC_LCOL; // Late Collision Register + AT91_REG EMAC_ECOL; // Excessive Collision Register + AT91_REG EMAC_CSE; // Carrier Sense Error Register + AT91_REG EMAC_TUE; // Transmit Underrun Error Register + AT91_REG EMAC_CDE; // Code Error Register + AT91_REG EMAC_ELR; // Excessive Length Error Register + AT91_REG EMAC_RJB; // Receive Jabber Register + AT91_REG EMAC_USF; // Undersize Frame Register + AT91_REG EMAC_SQEE; // SQE Test Error Register + AT91_REG EMAC_DRFC; // Discarded RX Frame Register + AT91_REG Reserved2[3]; // + AT91_REG EMAC_HSH; // Hash Address High[63:32] + AT91_REG EMAC_HSL; // Hash Address Low[31:0] + AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes + AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes + AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes + AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes + AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes + AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes + AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes + AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr +} AT91S_EMAC, *AT91PS_EMAC; + +// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. +// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) // (EMAC) Bit rate. +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash enable +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) // (EMAC) +// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) +// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- +#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) // (EMAC) +#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) // (EMAC) +#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) // (EMAC) +#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) // (EMAC) +#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) // (EMAC) +#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) // (EMAC) +#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) // (EMAC) +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) +#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) // (EMAC) +#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +typedef struct _AT91S_EBI { + AT91_REG EBI_CSA; // Chip Select Assignment Register + AT91_REG EBI_CFGR; // Configuration Register +} AT91S_EBI, *AT91PS_EBI; + +// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- +#define AT91C_EBI_CS0A ((unsigned int) 0x1 << 0) // (EBI) Chip Select 0 Assignment +#define AT91C_EBI_CS0A_SMC ((unsigned int) 0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS0A_BFC ((unsigned int) 0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. +#define AT91C_EBI_CS1A ((unsigned int) 0x1 << 1) // (EBI) Chip Select 1 Assignment +#define AT91C_EBI_CS1A_SMC ((unsigned int) 0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS1A_SDRAMC ((unsigned int) 0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_EBI_CS3A ((unsigned int) 0x1 << 3) // (EBI) Chip Select 3 Assignment +#define AT91C_EBI_CS3A_SMC ((unsigned int) 0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. +#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_EBI_CS4A ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 Assignment +#define AT91C_EBI_CS4A_SMC ((unsigned int) 0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. +#define AT91C_EBI_CS4A_SMC_CompactFlash ((unsigned int) 0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. +// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- +#define AT91C_EBI_DBPUC ((unsigned int) 0x1 << 0) // (EBI) Data Bus Pull-Up Configuration +#define AT91C_EBI_EBSEN ((unsigned int) 0x1 << 1) // (EBI) Bus Sharing Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface +// ***************************************************************************** +typedef struct _AT91S_SMC2 { + AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register +} AT91S_SMC2, *AT91PS_SMC2; + +// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- +#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) // (SMC2) Number of Wait States +#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) // (SMC2) Wait State Enable +#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) // (SMC2) Data Float Time +#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) // (SMC2) Byte Access Type +#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) // (SMC2) Data Bus Width +#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) // (SMC2) 16-bit. +#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) // (SMC2) 8-bit. +#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) // (SMC2) Data Read Protocol +#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) // (SMC2) Address to Chip Select Setup +#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. +#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. +#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. +#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. +#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) // (SMC2) Read and Write Signal Setup Time +#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) // (SMC2) Read and Write Signal Hold Time + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR SDRAM Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SDRC { + AT91_REG SDRC_MR; // SDRAM Controller Mode Register + AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register + AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register +} AT91S_SDRC, *AT91PS_SDRC; + +// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- +#define AT91C_SDRC_MODE ((unsigned int) 0xF << 0) // (SDRC) Mode +#define AT91C_SDRC_MODE_NORMAL_CMD ((unsigned int) 0x0) // (SDRC) Normal Mode +#define AT91C_SDRC_MODE_NOP_CMD ((unsigned int) 0x1) // (SDRC) NOP Command +#define AT91C_SDRC_MODE_PRCGALL_CMD ((unsigned int) 0x2) // (SDRC) All Banks Precharge Command +#define AT91C_SDRC_MODE_LMR_CMD ((unsigned int) 0x3) // (SDRC) Load Mode Register Command +#define AT91C_SDRC_MODE_RFSH_CMD ((unsigned int) 0x4) // (SDRC) Refresh Command +#define AT91C_SDRC_DBW ((unsigned int) 0x1 << 4) // (SDRC) Data Bus Width +#define AT91C_SDRC_DBW_32_BITS ((unsigned int) 0x0 << 4) // (SDRC) 32 Bits datas bus +#define AT91C_SDRC_DBW_16_BITS ((unsigned int) 0x1 << 4) // (SDRC) 16 Bits datas bus +// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- +#define AT91C_SDRC_COUNT ((unsigned int) 0xFFF << 0) // (SDRC) Refresh Counter +// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- +#define AT91C_SDRC_NC ((unsigned int) 0x3 << 0) // (SDRC) Number of Column Bits +#define AT91C_SDRC_NC_8 ((unsigned int) 0x0) // (SDRC) 8 Bits +#define AT91C_SDRC_NC_9 ((unsigned int) 0x1) // (SDRC) 9 Bits +#define AT91C_SDRC_NC_10 ((unsigned int) 0x2) // (SDRC) 10 Bits +#define AT91C_SDRC_NC_11 ((unsigned int) 0x3) // (SDRC) 11 Bits +#define AT91C_SDRC_NR ((unsigned int) 0x3 << 2) // (SDRC) Number of Row Bits +#define AT91C_SDRC_NR_11 ((unsigned int) 0x0 << 2) // (SDRC) 11 Bits +#define AT91C_SDRC_NR_12 ((unsigned int) 0x1 << 2) // (SDRC) 12 Bits +#define AT91C_SDRC_NR_13 ((unsigned int) 0x2 << 2) // (SDRC) 13 Bits +#define AT91C_SDRC_NB ((unsigned int) 0x1 << 4) // (SDRC) Number of Banks +#define AT91C_SDRC_NB_2_BANKS ((unsigned int) 0x0 << 4) // (SDRC) 2 banks +#define AT91C_SDRC_NB_4_BANKS ((unsigned int) 0x1 << 4) // (SDRC) 4 banks +#define AT91C_SDRC_CAS ((unsigned int) 0x3 << 5) // (SDRC) CAS Latency +#define AT91C_SDRC_CAS_2 ((unsigned int) 0x2 << 5) // (SDRC) 2 cycles +#define AT91C_SDRC_TWR ((unsigned int) 0xF << 7) // (SDRC) Number of Write Recovery Time Cycles +#define AT91C_SDRC_TRC ((unsigned int) 0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles +#define AT91C_SDRC_TRP ((unsigned int) 0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles +#define AT91C_SDRC_TRCD ((unsigned int) 0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles +#define AT91C_SDRC_TRAS ((unsigned int) 0xF << 23) // (SDRC) Number of RAS Active Time Cycles +#define AT91C_SDRC_TXSR ((unsigned int) 0xF << 27) // (SDRC) Number of Command Recovery Time Cycles +// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- +#define AT91C_SDRC_SRCB ((unsigned int) 0x1 << 0) // (SDRC) Self-refresh Command Bit +// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- +#define AT91C_SDRC_LPCB ((unsigned int) 0x1 << 0) // (SDRC) Low-power Command Bit +// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +#define AT91C_SDRC_RES ((unsigned int) 0x1 << 0) // (SDRC) Refresh Error Status +// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface +// ***************************************************************************** +typedef struct _AT91S_BFC { + AT91_REG BFC_MR; // BFC Mode Register +} AT91S_BFC, *AT91PS_BFC; + +// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- +#define AT91C_BFC_BFCOM ((unsigned int) 0x3 << 0) // (BFC) Burst Flash Controller Operating Mode +#define AT91C_BFC_BFCOM_DISABLED ((unsigned int) 0x0) // (BFC) NPCS0 is driven by the SMC or remains high. +#define AT91C_BFC_BFCOM_ASYNC ((unsigned int) 0x1) // (BFC) Asynchronous +#define AT91C_BFC_BFCOM_BURST_READ ((unsigned int) 0x2) // (BFC) Burst Read +#define AT91C_BFC_BFCC ((unsigned int) 0x3 << 2) // (BFC) Burst Flash Controller Operating Mode +#define AT91C_BFC_BFCC_MCK ((unsigned int) 0x1 << 2) // (BFC) Master Clock. +#define AT91C_BFC_BFCC_MCK_DIV_2 ((unsigned int) 0x2 << 2) // (BFC) Master Clock divided by 2. +#define AT91C_BFC_BFCC_MCK_DIV_4 ((unsigned int) 0x3 << 2) // (BFC) Master Clock divided by 4. +#define AT91C_BFC_AVL ((unsigned int) 0xF << 4) // (BFC) Address Valid Latency +#define AT91C_BFC_PAGES ((unsigned int) 0x7 << 8) // (BFC) Page Size +#define AT91C_BFC_PAGES_NO_PAGE ((unsigned int) 0x0 << 8) // (BFC) No page handling. +#define AT91C_BFC_PAGES_16 ((unsigned int) 0x1 << 8) // (BFC) 16 bytes page size. +#define AT91C_BFC_PAGES_32 ((unsigned int) 0x2 << 8) // (BFC) 32 bytes page size. +#define AT91C_BFC_PAGES_64 ((unsigned int) 0x3 << 8) // (BFC) 64 bytes page size. +#define AT91C_BFC_PAGES_128 ((unsigned int) 0x4 << 8) // (BFC) 128 bytes page size. +#define AT91C_BFC_PAGES_256 ((unsigned int) 0x5 << 8) // (BFC) 256 bytes page size. +#define AT91C_BFC_PAGES_512 ((unsigned int) 0x6 << 8) // (BFC) 512 bytes page size. +#define AT91C_BFC_PAGES_1024 ((unsigned int) 0x7 << 8) // (BFC) 1024 bytes page size. +#define AT91C_BFC_OEL ((unsigned int) 0x3 << 12) // (BFC) Output Enable Latency +#define AT91C_BFC_BAAEN ((unsigned int) 0x1 << 16) // (BFC) Burst Address Advance Enable +#define AT91C_BFC_BFOEH ((unsigned int) 0x1 << 17) // (BFC) Burst Flash Output Enable Handling +#define AT91C_BFC_MUXEN ((unsigned int) 0x1 << 18) // (BFC) Multiplexed Bus Enable +#define AT91C_BFC_RDYEN ((unsigned int) 0x1 << 19) // (BFC) Ready Enable Mode + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91RM9200 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register +#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for RTC peripheral ========== +#define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register +#define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register +#define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register +#define AT91C_RTC_TIMALR ((AT91_REG *) 0xFFFFFE10) // (RTC) Time Alarm Register +#define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFFFE08) // (RTC) Time Register +#define AT91C_RTC_CR ((AT91_REG *) 0xFFFFFE00) // (RTC) Control Register +#define AT91C_RTC_VER ((AT91_REG *) 0xFFFFFE2C) // (RTC) Valid Entry Register +#define AT91C_RTC_IDR ((AT91_REG *) 0xFFFFFE24) // (RTC) Interrupt Disable Register +#define AT91C_RTC_SCCR ((AT91_REG *) 0xFFFFFE1C) // (RTC) Status Clear Command Register +#define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register +#define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register +#define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register +// ========== Register definition for ST peripheral ========== +#define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register +#define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register +#define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register +#define AT91C_ST_RTMR ((AT91_REG *) 0xFFFFFD0C) // (ST) Real-time Mode Register +#define AT91C_ST_PIMR ((AT91_REG *) 0xFFFFFD04) // (ST) Period Interval Mode Register +#define AT91C_ST_RTAR ((AT91_REG *) 0xFFFFFD20) // (ST) Real-time Alarm Register +#define AT91C_ST_IDR ((AT91_REG *) 0xFFFFFD18) // (ST) Interrupt Disable Register +#define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register +#define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register +#define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register +#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register +#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PIOD peripheral ========== +#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register +#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register +#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register +#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) // (PIOD) Multi-driver Enable Register +#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) // (PIOD) Interrupt Mask Register +#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) // (PIOD) Interrupt Enable Register +#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) // (PIOD) Output Data Status Register +#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) // (PIOD) Set Output Data Register +#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) // (PIOD) PIO Enable Register +#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) // (PIOD) Output Write Disable Register +#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) // (PIOD) Pull-up Enable Register +#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) // (PIOD) Multi-driver Disable Register +#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) // (PIOD) Interrupt Status Register +#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) // (PIOD) Interrupt Disable Register +#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) // (PIOD) PIO Disable Register +#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) // (PIOD) Output Disable Registerr +#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) // (PIOD) Output Write Status Register +#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) // (PIOD) AB Select Status Register +#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) // (PIOD) Select A Register +#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) // (PIOD) Pad Pull-up Status Register +#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) // (PIOD) Pull-up Disable Register +#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) // (PIOD) Multi-driver Status Register +#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) // (PIOD) PIO Status Register +#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) // (PIOD) Output Enable Register +#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) // (PIOD) Output Status Register +#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) // (PIOD) Input Filter Enable Register +#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) // (PIOD) Select B Register +#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) // (PIOD) Input Filter Disable Register +#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) // (PIOD) Input Filter Status Register +// ========== Register definition for PIOC peripheral ========== +#define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register +#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr +#define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register +#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register +#define AT91C_PIOC_IFSR ((AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register +#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register +#define AT91C_PIOC_ODSR ((AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register +#define AT91C_PIOC_IER ((AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register +#define AT91C_PIOC_IMR ((AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register +#define AT91C_PIOC_OWDR ((AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register +#define AT91C_PIOC_MDDR ((AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register +#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register +#define AT91C_PIOC_IDR ((AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register +#define AT91C_PIOC_ISR ((AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register +#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register +#define AT91C_PIOC_OWSR ((AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register +#define AT91C_PIOC_OWER ((AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register +#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register +#define AT91C_PIOC_PPUSR ((AT91_REG *) 0xFFFFF868) // (PIOC) Pad Pull-up Status Register +#define AT91C_PIOC_PPUDR ((AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register +#define AT91C_PIOC_MDSR ((AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register +#define AT91C_PIOC_MDER ((AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register +#define AT91C_PIOC_IFER ((AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register +#define AT91C_PIOC_OSR ((AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register +#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register +#define AT91C_PIOC_PSR ((AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register +#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register +#define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register +#define AT91C_PIOC_PPUER ((AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pad Pull-up Status Register +#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_SSC2 peripheral ========== +#define AT91C_SSC2_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register +#define AT91C_SSC2_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register +#define AT91C_SSC2_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register +#define AT91C_SSC2_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register +#define AT91C_SSC2_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_SSC2) Receive Pointer Register +#define AT91C_SSC2_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register +#define AT91C_SSC2_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register +#define AT91C_SSC2_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register +#define AT91C_SSC2_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_SSC2) Transmit Counter Register +#define AT91C_SSC2_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_SSC2) Receive Counter Register +// ========== Register definition for SSC2 peripheral ========== +#define AT91C_SSC2_IMR ((AT91_REG *) 0xFFFD804C) // (SSC2) Interrupt Mask Register +#define AT91C_SSC2_IER ((AT91_REG *) 0xFFFD8044) // (SSC2) Interrupt Enable Register +#define AT91C_SSC2_RC1R ((AT91_REG *) 0xFFFD803C) // (SSC2) Receive Compare 1 Register +#define AT91C_SSC2_TSHR ((AT91_REG *) 0xFFFD8034) // (SSC2) Transmit Sync Holding Register +#define AT91C_SSC2_CMR ((AT91_REG *) 0xFFFD8004) // (SSC2) Clock Mode Register +#define AT91C_SSC2_IDR ((AT91_REG *) 0xFFFD8048) // (SSC2) Interrupt Disable Register +#define AT91C_SSC2_TCMR ((AT91_REG *) 0xFFFD8018) // (SSC2) Transmit Clock Mode Register +#define AT91C_SSC2_RCMR ((AT91_REG *) 0xFFFD8010) // (SSC2) Receive Clock ModeRegister +#define AT91C_SSC2_CR ((AT91_REG *) 0xFFFD8000) // (SSC2) Control Register +#define AT91C_SSC2_RFMR ((AT91_REG *) 0xFFFD8014) // (SSC2) Receive Frame Mode Register +#define AT91C_SSC2_TFMR ((AT91_REG *) 0xFFFD801C) // (SSC2) Transmit Frame Mode Register +#define AT91C_SSC2_THR ((AT91_REG *) 0xFFFD8024) // (SSC2) Transmit Holding Register +#define AT91C_SSC2_SR ((AT91_REG *) 0xFFFD8040) // (SSC2) Status Register +#define AT91C_SSC2_RC0R ((AT91_REG *) 0xFFFD8038) // (SSC2) Receive Compare 0 Register +#define AT91C_SSC2_RSHR ((AT91_REG *) 0xFFFD8030) // (SSC2) Receive Sync Holding Register +#define AT91C_SSC2_RHR ((AT91_REG *) 0xFFFD8020) // (SSC2) Receive Holding Register +// ========== Register definition for PDC_SSC1 peripheral ========== +#define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register +#define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register +#define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register +#define AT91C_SSC1_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register +#define AT91C_SSC1_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register +#define AT91C_SSC1_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register +#define AT91C_SSC1_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register +#define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register +#define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register +#define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register +// ========== Register definition for SSC1 peripheral ========== +#define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register +#define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register +#define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register +#define AT91C_SSC1_SR ((AT91_REG *) 0xFFFD4040) // (SSC1) Status Register +#define AT91C_SSC1_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC1) Receive Compare 0 Register +#define AT91C_SSC1_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register +#define AT91C_SSC1_RHR ((AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register +#define AT91C_SSC1_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register +#define AT91C_SSC1_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister +#define AT91C_SSC1_CR ((AT91_REG *) 0xFFFD4000) // (SSC1) Control Register +#define AT91C_SSC1_IMR ((AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register +#define AT91C_SSC1_IER ((AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register +#define AT91C_SSC1_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC1) Receive Compare 1 Register +#define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register +#define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register +#define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register +// ========== Register definition for PDC_SSC0 peripheral ========== +#define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register +#define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register +#define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register +#define AT91C_SSC0_TPR ((AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register +#define AT91C_SSC0_RPR ((AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register +#define AT91C_SSC0_PTSR ((AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register +#define AT91C_SSC0_TNCR ((AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register +#define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register +#define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register +#define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register +// ========== Register definition for SSC0 peripheral ========== +#define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register +#define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register +#define AT91C_SSC0_RC1R ((AT91_REG *) 0xFFFD003C) // (SSC0) Receive Compare 1 Register +#define AT91C_SSC0_TSHR ((AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register +#define AT91C_SSC0_THR ((AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register +#define AT91C_SSC0_TFMR ((AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register +#define AT91C_SSC0_RFMR ((AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register +#define AT91C_SSC0_CMR ((AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register +#define AT91C_SSC0_IDR ((AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register +#define AT91C_SSC0_SR ((AT91_REG *) 0xFFFD0040) // (SSC0) Status Register +#define AT91C_SSC0_RC0R ((AT91_REG *) 0xFFFD0038) // (SSC0) Receive Compare 0 Register +#define AT91C_SSC0_RSHR ((AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register +#define AT91C_SSC0_RHR ((AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register +#define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register +#define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister +#define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register +// ========== Register definition for PDC_US3 peripheral ========== +#define AT91C_US3_PTSR ((AT91_REG *) 0xFFFCC124) // (PDC_US3) PDC Transfer Status Register +#define AT91C_US3_TNCR ((AT91_REG *) 0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register +#define AT91C_US3_RNCR ((AT91_REG *) 0xFFFCC114) // (PDC_US3) Receive Next Counter Register +#define AT91C_US3_TCR ((AT91_REG *) 0xFFFCC10C) // (PDC_US3) Transmit Counter Register +#define AT91C_US3_RCR ((AT91_REG *) 0xFFFCC104) // (PDC_US3) Receive Counter Register +#define AT91C_US3_PTCR ((AT91_REG *) 0xFFFCC120) // (PDC_US3) PDC Transfer Control Register +#define AT91C_US3_TNPR ((AT91_REG *) 0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register +#define AT91C_US3_RNPR ((AT91_REG *) 0xFFFCC110) // (PDC_US3) Receive Next Pointer Register +#define AT91C_US3_TPR ((AT91_REG *) 0xFFFCC108) // (PDC_US3) Transmit Pointer Register +#define AT91C_US3_RPR ((AT91_REG *) 0xFFFCC100) // (PDC_US3) Receive Pointer Register +// ========== Register definition for US3 peripheral ========== +#define AT91C_US3_IF ((AT91_REG *) 0xFFFCC04C) // (US3) IRDA_FILTER Register +#define AT91C_US3_NER ((AT91_REG *) 0xFFFCC044) // (US3) Nb Errors Register +#define AT91C_US3_RTOR ((AT91_REG *) 0xFFFCC024) // (US3) Receiver Time-out Register +#define AT91C_US3_THR ((AT91_REG *) 0xFFFCC01C) // (US3) Transmitter Holding Register +#define AT91C_US3_CSR ((AT91_REG *) 0xFFFCC014) // (US3) Channel Status Register +#define AT91C_US3_IDR ((AT91_REG *) 0xFFFCC00C) // (US3) Interrupt Disable Register +#define AT91C_US3_MR ((AT91_REG *) 0xFFFCC004) // (US3) Mode Register +#define AT91C_US3_XXR ((AT91_REG *) 0xFFFCC048) // (US3) XON_XOFF Register +#define AT91C_US3_FIDI ((AT91_REG *) 0xFFFCC040) // (US3) FI_DI_Ratio Register +#define AT91C_US3_TTGR ((AT91_REG *) 0xFFFCC028) // (US3) Transmitter Time-guard Register +#define AT91C_US3_BRGR ((AT91_REG *) 0xFFFCC020) // (US3) Baud Rate Generator Register +#define AT91C_US3_RHR ((AT91_REG *) 0xFFFCC018) // (US3) Receiver Holding Register +#define AT91C_US3_IMR ((AT91_REG *) 0xFFFCC010) // (US3) Interrupt Mask Register +#define AT91C_US3_IER ((AT91_REG *) 0xFFFCC008) // (US3) Interrupt Enable Register +#define AT91C_US3_CR ((AT91_REG *) 0xFFFCC000) // (US3) Control Register +// ========== Register definition for PDC_US2 peripheral ========== +#define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register +#define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register +#define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register +#define AT91C_US2_TCR ((AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register +#define AT91C_US2_PTCR ((AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register +#define AT91C_US2_RCR ((AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register +#define AT91C_US2_TNPR ((AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register +#define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register +#define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register +#define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register +// ========== Register definition for US2 peripheral ========== +#define AT91C_US2_XXR ((AT91_REG *) 0xFFFC8048) // (US2) XON_XOFF Register +#define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register +#define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register +#define AT91C_US2_BRGR ((AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register +#define AT91C_US2_RHR ((AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register +#define AT91C_US2_IMR ((AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register +#define AT91C_US2_IER ((AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register +#define AT91C_US2_CR ((AT91_REG *) 0xFFFC8000) // (US2) Control Register +#define AT91C_US2_IF ((AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register +#define AT91C_US2_NER ((AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register +#define AT91C_US2_RTOR ((AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register +#define AT91C_US2_THR ((AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register +#define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register +#define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register +#define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for PDC_MCI peripheral ========== +#define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register +#define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register +#define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register +#define AT91C_MCI_TPR ((AT91_REG *) 0xFFFB4108) // (PDC_MCI) Transmit Pointer Register +#define AT91C_MCI_RPR ((AT91_REG *) 0xFFFB4100) // (PDC_MCI) Receive Pointer Register +#define AT91C_MCI_PTSR ((AT91_REG *) 0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register +#define AT91C_MCI_TNCR ((AT91_REG *) 0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register +#define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFB4114) // (PDC_MCI) Receive Next Counter Register +#define AT91C_MCI_TCR ((AT91_REG *) 0xFFFB410C) // (PDC_MCI) Transmit Counter Register +#define AT91C_MCI_RCR ((AT91_REG *) 0xFFFB4104) // (PDC_MCI) Receive Counter Register +// ========== Register definition for MCI peripheral ========== +#define AT91C_MCI_IDR ((AT91_REG *) 0xFFFB4048) // (MCI) MCI Interrupt Disable Register +#define AT91C_MCI_SR ((AT91_REG *) 0xFFFB4040) // (MCI) MCI Status Register +#define AT91C_MCI_RDR ((AT91_REG *) 0xFFFB4030) // (MCI) MCI Receive Data Register +#define AT91C_MCI_RSPR ((AT91_REG *) 0xFFFB4020) // (MCI) MCI Response Register +#define AT91C_MCI_ARGR ((AT91_REG *) 0xFFFB4010) // (MCI) MCI Argument Register +#define AT91C_MCI_DTOR ((AT91_REG *) 0xFFFB4008) // (MCI) MCI Data Timeout Register +#define AT91C_MCI_CR ((AT91_REG *) 0xFFFB4000) // (MCI) MCI Control Register +#define AT91C_MCI_IMR ((AT91_REG *) 0xFFFB404C) // (MCI) MCI Interrupt Mask Register +#define AT91C_MCI_IER ((AT91_REG *) 0xFFFB4044) // (MCI) MCI Interrupt Enable Register +#define AT91C_MCI_TDR ((AT91_REG *) 0xFFFB4034) // (MCI) MCI Transmit Data Register +#define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFB4014) // (MCI) MCI Command Register +#define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFB400C) // (MCI) MCI SD Card Register +#define AT91C_MCI_MR ((AT91_REG *) 0xFFFB4004) // (MCI) MCI Mode Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +// ========== Register definition for TC5 peripheral ========== +#define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register +#define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register +#define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register +#define AT91C_TC5_RB ((AT91_REG *) 0xFFFA4098) // (TC5) Register B +#define AT91C_TC5_CV ((AT91_REG *) 0xFFFA4090) // (TC5) Counter Value +#define AT91C_TC5_CCR ((AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register +#define AT91C_TC5_IMR ((AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register +#define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register +#define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C +#define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A +// ========== Register definition for TC4 peripheral ========== +#define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register +#define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register +#define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C +#define AT91C_TC4_RA ((AT91_REG *) 0xFFFA4054) // (TC4) Register A +#define AT91C_TC4_CMR ((AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register +#define AT91C_TC4_IDR ((AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register +#define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register +#define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B +#define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value +#define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register +// ========== Register definition for TC3 peripheral ========== +#define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register +#define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value +#define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register +#define AT91C_TC3_IER ((AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register +#define AT91C_TC3_CMR ((AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register +#define AT91C_TC3_RA ((AT91_REG *) 0xFFFA4014) // (TC3) Register A +#define AT91C_TC3_RC ((AT91_REG *) 0xFFFA401C) // (TC3) Register C +#define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register +#define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B +#define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register +// ========== Register definition for TCB1 peripheral ========== +#define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA4140) // (TCB1) TC Block Control Register +#define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA4144) // (TCB1) TC Block Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register +#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register +#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register +#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB0 peripheral ========== +#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register +#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register +// ========== Register definition for UHP peripheral ========== +#define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 0x00300048) // (UHP) Root Hub characteristics A +#define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 0x00300054) // (UHP) Root Hub Port Status Register +#define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 0x0030004C) // (UHP) Root Hub characteristics B +#define AT91C_UHP_HcControl ((AT91_REG *) 0x00300004) // (UHP) Operating modes for the Host Controller +#define AT91C_UHP_HcInterruptStatus ((AT91_REG *) 0x0030000C) // (UHP) Interrupt Status Register +#define AT91C_UHP_HcRhStatus ((AT91_REG *) 0x00300050) // (UHP) Root Hub Status register +#define AT91C_UHP_HcRevision ((AT91_REG *) 0x00300000) // (UHP) Revision +#define AT91C_UHP_HcCommandStatus ((AT91_REG *) 0x00300008) // (UHP) Command & status Register +#define AT91C_UHP_HcInterruptEnable ((AT91_REG *) 0x00300010) // (UHP) Interrupt Enable Register +#define AT91C_UHP_HcHCCA ((AT91_REG *) 0x00300018) // (UHP) Pointer to the Host Controller Communication Area +#define AT91C_UHP_HcControlHeadED ((AT91_REG *) 0x00300020) // (UHP) First Endpoint Descriptor of the Control list +#define AT91C_UHP_HcInterruptDisable ((AT91_REG *) 0x00300014) // (UHP) Interrupt Disable Register +#define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) 0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor +#define AT91C_UHP_HcControlCurrentED ((AT91_REG *) 0x00300024) // (UHP) Endpoint Control and Status Register +#define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) 0x0030002C) // (UHP) Current endpoint of the Bulk list +#define AT91C_UHP_HcFmInterval ((AT91_REG *) 0x00300034) // (UHP) Bit time between 2 consecutive SOFs +#define AT91C_UHP_HcBulkHeadED ((AT91_REG *) 0x00300028) // (UHP) First endpoint register of the Bulk list +#define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) 0x00300030) // (UHP) Last completed transfer descriptor +#define AT91C_UHP_HcFmRemaining ((AT91_REG *) 0x00300038) // (UHP) Bit time remaining in the current Frame +#define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 0x00300040) // (UHP) Periodic Start +#define AT91C_UHP_HcLSThreshold ((AT91_REG *) 0x00300044) // (UHP) LS Threshold +#define AT91C_UHP_HcFmNumber ((AT91_REG *) 0x0030003C) // (UHP) Frame number +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) // (EMAC) Hash Address High[63:32] +#define AT91C_EMAC_MCOL ((AT91_REG *) 0xFFFBC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFBC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes +#define AT91C_EMAC_HSL ((AT91_REG *) 0xFFFBC094) // (EMAC) Hash Address Low[31:0] +#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFBC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_OK ((AT91_REG *) 0xFFFBC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_CFG ((AT91_REG *) 0xFFFBC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes +#define AT91C_EMAC_SEQE ((AT91_REG *) 0xFFFBC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFBC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_ELR ((AT91_REG *) 0xFFFBC070) // (EMAC) Excessive Length Error Register +#define AT91C_EMAC_SR ((AT91_REG *) 0xFFFBC008) // (EMAC) Network Status Register +#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFBC064) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_RJB ((AT91_REG *) 0xFFFBC074) // (EMAC) Receive Jabber Register +#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFBC078) // (EMAC) Undersize Frame Register +#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFBC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes +#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFBC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_FRA ((AT91_REG *) 0xFFFBC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes +#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes +#define AT91C_EMAC_SCOL ((AT91_REG *) 0xFFFBC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFBC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_TAR ((AT91_REG *) 0xFFFBC00C) // (EMAC) Transmit Address Register +#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes +#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes +#define AT91C_EMAC_TUE ((AT91_REG *) 0xFFFBC068) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_DTE ((AT91_REG *) 0xFFFBC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TCR ((AT91_REG *) 0xFFFBC010) // (EMAC) Transmit Control Register +#define AT91C_EMAC_CTL ((AT91_REG *) 0xFFFBC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr +#define AT91C_EMAC_CDE ((AT91_REG *) 0xFFFBC06C) // (EMAC) Code Error Register +#define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) // (EMAC) SQE Test Error Register +#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) // (EMAC) Discarded RX Frame Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_CFGR ((AT91_REG *) 0xFFFFFF64) // (EBI) Configuration Register +#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) // (EBI) Chip Select Assignment Register +// ========== Register definition for SMC2 peripheral ========== +#define AT91C_SMC2_CSR ((AT91_REG *) 0xFFFFFF70) // (SMC2) SMC2 Chip Select Register +// ========== Register definition for SDRC peripheral ========== +#define AT91C_SDRC_IMR ((AT91_REG *) 0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRC_IER ((AT91_REG *) 0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register +#define AT91C_SDRC_SRR ((AT91_REG *) 0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register +#define AT91C_SDRC_TR ((AT91_REG *) 0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register +#define AT91C_SDRC_ISR ((AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRC_IDR ((AT91_REG *) 0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register +#define AT91C_SDRC_LPR ((AT91_REG *) 0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register +#define AT91C_SDRC_CR ((AT91_REG *) 0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register +#define AT91C_SDRC_MR ((AT91_REG *) 0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register +// ========== Register definition for BFC peripheral ========== +#define AT91C_BFC_MR ((AT91_REG *) 0xFFFFFFC0) // (BFC) BFC Mode Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91RM9200 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) // SPI Master In Slave +#define AT91C_PA0_PCK3 ((unsigned int) AT91C_PIO_PA0) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) // SPI Master Out Slave +#define AT91C_PA1_PCK0 ((unsigned int) AT91C_PIO_PA1) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1 +#define AT91C_PA10_MCDB1 ((unsigned int) AT91C_PIO_PA10) // Multimedia Card B Data 1 +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PA11_MCDB2 ((unsigned int) AT91C_PIO_PA11) // Multimedia Card B Data 2 +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 +#define AT91C_PA12_MCDB3 ((unsigned int) AT91C_PIO_PA12) // Multimedia Card B Data 3 +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 +#define AT91C_PA13_TCLK0 ((unsigned int) AT91C_PIO_PA13) // Timer Counter 0 external clock input +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) // Ethernet MAC Receive Error +#define AT91C_PA14_TCLK1 ((unsigned int) AT91C_PIO_PA14) // Timer Counter 1 external clock input +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) // Ethernet MAC Management Data Clock +#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output +#define AT91C_PA16_IRQ6 ((unsigned int) AT91C_PIO_PA16) // AIC Interrupt input 6 +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TXD0 ((unsigned int) AT91C_PIO_PA17) // USART 0 Transmit Data +#define AT91C_PA17_TIOA0 ((unsigned int) AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RXD0 ((unsigned int) AT91C_PIO_PA18) // USART 0 Receive Data +#define AT91C_PA18_TIOB0 ((unsigned int) AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_SCK0 ((unsigned int) AT91C_PIO_PA19) // USART 0 Serial Clock +#define AT91C_PA19_TIOA1 ((unsigned int) AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) // SPI Serial Clock +#define AT91C_PA2_IRQ4 ((unsigned int) AT91C_PIO_PA2) // AIC Interrupt Input 4 +#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CTS0 ((unsigned int) AT91C_PIO_PA20) // USART 0 Clear To Send +#define AT91C_PA20_TIOB1 ((unsigned int) AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RTS0 ((unsigned int) AT91C_PIO_PA21) // Usart 0 Ready To Send +#define AT91C_PA21_TIOA2 ((unsigned int) AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) // USART 2 Receive Data +#define AT91C_PA22_TIOB2 ((unsigned int) AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) // USART 2 Transmit Data +#define AT91C_PA23_IRQ3 ((unsigned int) AT91C_PIO_PA23) // Interrupt input 3 +#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_SCK2 ((unsigned int) AT91C_PIO_PA24) // USART2 Serial Clock +#define AT91C_PA24_PCK1 ((unsigned int) AT91C_PIO_PA24) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_TWD ((unsigned int) AT91C_PIO_PA25) // TWI Two-wire Serial Data +#define AT91C_PA25_IRQ2 ((unsigned int) AT91C_PIO_PA25) // Interrupt input 2 +#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_TWCK ((unsigned int) AT91C_PIO_PA26) // TWI Two-wire Serial Clock +#define AT91C_PA26_IRQ1 ((unsigned int) AT91C_PIO_PA26) // Interrupt input 1 +#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_MCCK ((unsigned int) AT91C_PIO_PA27) // Multimedia Card Clock +#define AT91C_PA27_TCLK3 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 3 External Clock Input +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_MCCDA ((unsigned int) AT91C_PIO_PA28) // Multimedia Card A Command +#define AT91C_PA28_TCLK4 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 4 external Clock Input +#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_MCDA0 ((unsigned int) AT91C_PIO_PA29) // Multimedia Card A Data 0 +#define AT91C_PA29_TCLK5 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 5 external clock input +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 0 +#define AT91C_PA3_IRQ5 ((unsigned int) AT91C_PIO_PA3) // AIC Interrupt Input 5 +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) // DBGU Debug Receive Data +#define AT91C_PA30_CTS2 ((unsigned int) AT91C_PIO_PA30) // Usart 2 Clear To Send +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) // DBGU Debug Transmit Data +#define AT91C_PA31_RTS2 ((unsigned int) AT91C_PIO_PA31) // USART 2 Ready To Send +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) // SPI Peripheral Chip Select 1 +#define AT91C_PA4_PCK1 ((unsigned int) AT91C_PIO_PA4) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 2 +#define AT91C_PA5_TXD3 ((unsigned int) AT91C_PIO_PA5) // USART 3 Transmit Data +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) // SPI Peripheral Chip Select 3 +#define AT91C_PA6_RXD3 ((unsigned int) AT91C_PIO_PA6) // USART 3 Receive Data +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PA7_PCK2 ((unsigned int) AT91C_PIO_PA7) // PMC Programmable Clock 2 +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) // Ethernet MAC Transmit Enable +#define AT91C_PA8_MCCDB ((unsigned int) AT91C_PIO_PA8) // Multimedia Card B Command +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0 +#define AT91C_PA9_MCDB0 ((unsigned int) AT91C_PIO_PA9) // Multimedia Card B Data 0 +#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_TF0 ((unsigned int) AT91C_PIO_PB0) // SSC Transmit Frame Sync 0 +#define AT91C_PB0_TIOB3 ((unsigned int) AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_TK0 ((unsigned int) AT91C_PIO_PB1) // SSC Transmit Clock 0 +#define AT91C_PB1_CTS3 ((unsigned int) AT91C_PIO_PB1) // USART 3 Clear To Send +#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_RK1 ((unsigned int) AT91C_PIO_PB10) // SSC Receive Clock 1 +#define AT91C_PB10_TIOA5 ((unsigned int) AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_RF1 ((unsigned int) AT91C_PIO_PB11) // SSC Receive Frame Sync 1 +#define AT91C_PB11_TIOB5 ((unsigned int) AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) // SSC Transmit Frame Sync 2 +#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) // SSC Transmit Clock 2 +#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) // SSC Transmit Data 2 +#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) // SSC Receive Data 2 +#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data 2 +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) // SSC Receive Clock 2 +#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Receive Data 3 +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) // SSC Receive Frame Sync 2 +#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) // USART 1 Ring Indicator +#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Collision Detected +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) // USART 1 Data Terminal ready +#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) // Ethernet MAC Receive Clock +#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_TD0 ((unsigned int) AT91C_PIO_PB2) // SSC Transmit data +#define AT91C_PB2_SCK3 ((unsigned int) AT91C_PIO_PB2) // USART 3 Serial Clock +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_TXD1 ((unsigned int) AT91C_PIO_PB20) // USART 1 Transmit Data +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_RXD1 ((unsigned int) AT91C_PIO_PB21) // USART 1 Receive Data +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_SCK1 ((unsigned int) AT91C_PIO_PB22) // USART1 Serial Clock +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_CTS1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Clear To Send +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Set ready +#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_RTS1 ((unsigned int) AT91C_PIO_PB26) // Usart 0 Ready To Send +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_PCK0 ((unsigned int) AT91C_PIO_PB27) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_FIQ ((unsigned int) AT91C_PIO_PB28) // AIC Fast Interrupt Input +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_IRQ0 ((unsigned int) AT91C_PIO_PB29) // Interrupt input 0 +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_RD0 ((unsigned int) AT91C_PIO_PB3) // SSC Receive Data +#define AT91C_PB3_MCDA1 ((unsigned int) AT91C_PIO_PB3) // Multimedia Card A Data 1 +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_RK0 ((unsigned int) AT91C_PIO_PB4) // SSC Receive Clock +#define AT91C_PB4_MCDA2 ((unsigned int) AT91C_PIO_PB4) // Multimedia Card A Data 2 +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_RF0 ((unsigned int) AT91C_PIO_PB5) // SSC Receive Frame Sync 0 +#define AT91C_PB5_MCDA3 ((unsigned int) AT91C_PIO_PB5) // Multimedia Card A Data 3 +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_TF1 ((unsigned int) AT91C_PIO_PB6) // SSC Transmit Frame Sync 1 +#define AT91C_PB6_TIOA3 ((unsigned int) AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_TK1 ((unsigned int) AT91C_PIO_PB7) // SSC Transmit Clock 1 +#define AT91C_PB7_TIOB3 ((unsigned int) AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_TD1 ((unsigned int) AT91C_PIO_PB8) // SSC Transmit Data 1 +#define AT91C_PB8_TIOA4 ((unsigned int) AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_RD1 ((unsigned int) AT91C_PIO_PB9) // SSC Receive Data 1 +#define AT91C_PB9_TIOB4 ((unsigned int) AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) // Pin Controlled by PC0 +#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) // Burst Flash Clock +#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) // Pin Controlled by PC1 +#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) // Burst Flash Ready +#define AT91C_PIO_PC10 ((unsigned int) 1 << 10) // Pin Controlled by PC10 +#define AT91C_PC10_NCS4_CFCS ((unsigned int) AT91C_PIO_PC10) // Compact Flash Chip Select +#define AT91C_PIO_PC11 ((unsigned int) 1 << 11) // Pin Controlled by PC11 +#define AT91C_PC11_NCS5_CFCE1 ((unsigned int) AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1 +#define AT91C_PIO_PC12 ((unsigned int) 1 << 12) // Pin Controlled by PC12 +#define AT91C_PC12_NCS6_CFCE2 ((unsigned int) AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2 +#define AT91C_PIO_PC13 ((unsigned int) 1 << 13) // Pin Controlled by PC13 +#define AT91C_PC13_NCS7 ((unsigned int) AT91C_PIO_PC13) // Chip Select 7 +#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) // Pin Controlled by PC14 +#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) // Pin Controlled by PC15 +#define AT91C_PIO_PC16 ((unsigned int) 1 << 16) // Pin Controlled by PC16 +#define AT91C_PC16_D16 ((unsigned int) AT91C_PIO_PC16) // Data Bus [16] +#define AT91C_PIO_PC17 ((unsigned int) 1 << 17) // Pin Controlled by PC17 +#define AT91C_PC17_D17 ((unsigned int) AT91C_PIO_PC17) // Data Bus [17] +#define AT91C_PIO_PC18 ((unsigned int) 1 << 18) // Pin Controlled by PC18 +#define AT91C_PC18_D18 ((unsigned int) AT91C_PIO_PC18) // Data Bus [18] +#define AT91C_PIO_PC19 ((unsigned int) 1 << 19) // Pin Controlled by PC19 +#define AT91C_PC19_D19 ((unsigned int) AT91C_PIO_PC19) // Data Bus [19] +#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) // Pin Controlled by PC2 +#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) // Burst Flash Address Valid +#define AT91C_PIO_PC20 ((unsigned int) 1 << 20) // Pin Controlled by PC20 +#define AT91C_PC20_D20 ((unsigned int) AT91C_PIO_PC20) // Data Bus [20] +#define AT91C_PIO_PC21 ((unsigned int) 1 << 21) // Pin Controlled by PC21 +#define AT91C_PC21_D21 ((unsigned int) AT91C_PIO_PC21) // Data Bus [21] +#define AT91C_PIO_PC22 ((unsigned int) 1 << 22) // Pin Controlled by PC22 +#define AT91C_PC22_D22 ((unsigned int) AT91C_PIO_PC22) // Data Bus [22] +#define AT91C_PIO_PC23 ((unsigned int) 1 << 23) // Pin Controlled by PC23 +#define AT91C_PC23_D23 ((unsigned int) AT91C_PIO_PC23) // Data Bus [23] +#define AT91C_PIO_PC24 ((unsigned int) 1 << 24) // Pin Controlled by PC24 +#define AT91C_PC24_D24 ((unsigned int) AT91C_PIO_PC24) // Data Bus [24] +#define AT91C_PIO_PC25 ((unsigned int) 1 << 25) // Pin Controlled by PC25 +#define AT91C_PC25_D25 ((unsigned int) AT91C_PIO_PC25) // Data Bus [25] +#define AT91C_PIO_PC26 ((unsigned int) 1 << 26) // Pin Controlled by PC26 +#define AT91C_PC26_D26 ((unsigned int) AT91C_PIO_PC26) // Data Bus [26] +#define AT91C_PIO_PC27 ((unsigned int) 1 << 27) // Pin Controlled by PC27 +#define AT91C_PC27_D27 ((unsigned int) AT91C_PIO_PC27) // Data Bus [27] +#define AT91C_PIO_PC28 ((unsigned int) 1 << 28) // Pin Controlled by PC28 +#define AT91C_PC28_D28 ((unsigned int) AT91C_PIO_PC28) // Data Bus [28] +#define AT91C_PIO_PC29 ((unsigned int) 1 << 29) // Pin Controlled by PC29 +#define AT91C_PC29_D29 ((unsigned int) AT91C_PIO_PC29) // Data Bus [29] +#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) // Pin Controlled by PC3 +#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable +#define AT91C_PIO_PC30 ((unsigned int) 1 << 30) // Pin Controlled by PC30 +#define AT91C_PC30_D30 ((unsigned int) AT91C_PIO_PC30) // Data Bus [30] +#define AT91C_PIO_PC31 ((unsigned int) 1 << 31) // Pin Controlled by PC31 +#define AT91C_PC31_D31 ((unsigned int) AT91C_PIO_PC31) // Data Bus [31] +#define AT91C_PIO_PC4 ((unsigned int) 1 << 4) // Pin Controlled by PC4 +#define AT91C_PC4_BFOE ((unsigned int) AT91C_PIO_PC4) // Burst Flash Output Enable +#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) // Pin Controlled by PC5 +#define AT91C_PC5_BFWE ((unsigned int) AT91C_PIO_PC5) // Burst Flash Write Enable +#define AT91C_PIO_PC6 ((unsigned int) 1 << 6) // Pin Controlled by PC6 +#define AT91C_PC6_NWAIT ((unsigned int) AT91C_PIO_PC6) // NWAIT +#define AT91C_PIO_PC7 ((unsigned int) 1 << 7) // Pin Controlled by PC7 +#define AT91C_PC7_A23 ((unsigned int) AT91C_PIO_PC7) // Address Bus[23] +#define AT91C_PIO_PC8 ((unsigned int) 1 << 8) // Pin Controlled by PC8 +#define AT91C_PC8_A24 ((unsigned int) AT91C_PIO_PC8) // Address Bus[24] +#define AT91C_PIO_PC9 ((unsigned int) 1 << 9) // Pin Controlled by PC9 +#define AT91C_PC9_A25_CFRNW ((unsigned int) AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write +#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) // Pin Controlled by PD0 +#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) // Pin Controlled by PD1 +#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) // Pin Controlled by PD10 +#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) // PMC Programmable Clock Output 3 +#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 +#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) // Pin Controlled by PD11 +#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) // +#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 +#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) // Pin Controlled by PD12 +#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) // +#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) // ETM Trace Packet 0 +#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) // Pin Controlled by PD13 +#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) // +#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) // ETM Trace Packet 1 +#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) // Pin Controlled by PD14 +#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) // +#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) // ETM Trace Packet 2 +#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) // Pin Controlled by PD15 +#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) // SSC Transmit data +#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) // ETM Trace Packet 3 +#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) // Pin Controlled by PD16 +#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) // SSC Transmit Data 1 +#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) // ETM Trace Packet 4 +#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) // Pin Controlled by PD17 +#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) // SSC Transmit Data 2 +#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) // ETM Trace Packet 5 +#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) // Pin Controlled by PD18 +#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) // SPI Peripheral Chip Select 1 +#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) // ETM Trace Packet 6 +#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) // Pin Controlled by PD19 +#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) // SPI Peripheral Chip Select 2 +#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) // ETM Trace Packet 7 +#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) // Pin Controlled by PD2 +#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) // Pin Controlled by PD20 +#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) // SPI Peripheral Chip Select 3 +#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) // ETM Trace Packet 8 +#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) // Pin Controlled by PD21 +#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) // Usart 0 Ready To Send +#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) // ETM Trace Packet 9 +#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) // Pin Controlled by PD22 +#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) // Usart 0 Ready To Send +#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) // ETM Trace Packet 10 +#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) // Pin Controlled by PD23 +#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) // USART 2 Ready To Send +#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) // ETM Trace Packet 11 +#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) // Pin Controlled by PD24 +#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) // USART 3 Ready To Send +#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) // ETM Trace Packet 12 +#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) // Pin Controlled by PD25 +#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) // USART 1 Data Terminal ready +#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) // ETM Trace Packet 13 +#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) // Pin Controlled by PD26 +#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) // ETM Trace Packet 14 +#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) // Pin Controlled by PD27 +#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) // ETM Trace Packet 15 +#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) // Pin Controlled by PD3 +#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) // Pin Controlled by PD4 +#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) // Pin Controlled by PD5 +#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error +#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) // Pin Controlled by PD6 +#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) // DBGU Debug Transmit Data +#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) // Pin Controlled by PD7 +#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) // PMC Programmable Clock Output 0 +#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) // ETM Synchronization signal +#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) // Pin Controlled by PD8 +#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) // PMC Programmable Clock Output 1 +#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) // ETM Trace Clock signal +#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) // Pin Controlled by PD9 +#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) // PMC Programmable Clock 2 +#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) // ETM ARM9 pipeline status 0 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91RM9200 +// ***************************************************************************** +#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral +#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B +#define AT91C_ID_PIOC ((unsigned int) 4) // Parallel IO Controller C +#define AT91C_ID_PIOD ((unsigned int) 5) // Parallel IO Controller D +#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 +#define AT91C_ID_US2 ((unsigned int) 8) // USART 2 +#define AT91C_ID_US3 ((unsigned int) 9) // USART 3 +#define AT91C_ID_MCI ((unsigned int) 10) // Multimedia Card Interface +#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port +#define AT91C_ID_TWI ((unsigned int) 12) // Two-Wire Interface +#define AT91C_ID_SPI ((unsigned int) 13) // Serial Peripheral Interface +#define AT91C_ID_SSC0 ((unsigned int) 14) // Serial Synchronous Controller 0 +#define AT91C_ID_SSC1 ((unsigned int) 15) // Serial Synchronous Controller 1 +#define AT91C_ID_SSC2 ((unsigned int) 16) // Serial Synchronous Controller 2 +#define AT91C_ID_TC0 ((unsigned int) 17) // Timer Counter 0 +#define AT91C_ID_TC1 ((unsigned int) 18) // Timer Counter 1 +#define AT91C_ID_TC2 ((unsigned int) 19) // Timer Counter 2 +#define AT91C_ID_TC3 ((unsigned int) 20) // Timer Counter 3 +#define AT91C_ID_TC4 ((unsigned int) 21) // Timer Counter 4 +#define AT91C_ID_TC5 ((unsigned int) 22) // Timer Counter 5 +#define AT91C_ID_UHP ((unsigned int) 23) // USB Host port +#define AT91C_ID_EMAC ((unsigned int) 24) // Ethernet MAC +#define AT91C_ID_IRQ0 ((unsigned int) 25) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 ((unsigned int) 26) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_IRQ2 ((unsigned int) 27) // Advanced Interrupt Controller (IRQ2) +#define AT91C_ID_IRQ3 ((unsigned int) 28) // Advanced Interrupt Controller (IRQ3) +#define AT91C_ID_IRQ4 ((unsigned int) 29) // Advanced Interrupt Controller (IRQ4) +#define AT91C_ID_IRQ5 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ5) +#define AT91C_ID_IRQ6 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ6) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91RM9200 +// ***************************************************************************** +#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) // (RTC) Base Address +#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) // (ST) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) // (PIOD) Base Address +#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_SSC2 ((AT91PS_PDC) 0xFFFD8100) // (PDC_SSC2) Base Address +#define AT91C_BASE_SSC2 ((AT91PS_SSC) 0xFFFD8000) // (SSC2) Base Address +#define AT91C_BASE_PDC_SSC1 ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address +#define AT91C_BASE_SSC1 ((AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address +#define AT91C_BASE_PDC_SSC0 ((AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address +#define AT91C_BASE_SSC0 ((AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address +#define AT91C_BASE_PDC_US3 ((AT91PS_PDC) 0xFFFCC100) // (PDC_US3) Base Address +#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) // (US3) Base Address +#define AT91C_BASE_PDC_US2 ((AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address +#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) // (US2) Base Address +#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PDC_MCI ((AT91PS_PDC) 0xFFFB4100) // (PDC_MCI) Base Address +#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) // (MCI) Base Address +#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC5 ((AT91PS_TC) 0xFFFA4080) // (TC5) Base Address +#define AT91C_BASE_TC4 ((AT91PS_TC) 0xFFFA4040) // (TC4) Base Address +#define AT91C_BASE_TC3 ((AT91PS_TC) 0xFFFA4000) // (TC3) Base Address +#define AT91C_BASE_TCB1 ((AT91PS_TCB) 0xFFFA4080) // (TCB1) Base Address +#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address +#define AT91C_BASE_UHP ((AT91PS_UHP) 0x00300000) // (UHP) Base Address +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) // (EMAC) Base Address +#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFFFFF60) // (EBI) Base Address +#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) // (SMC2) Base Address +#define AT91C_BASE_SDRC ((AT91PS_SDRC) 0xFFFFFF90) // (SDRC) Base Address +#define AT91C_BASE_BFC ((AT91PS_BFC) 0xFFFFFFC0) // (BFC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91RM9200 +// ***************************************************************************** +#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IROM ((char *) 0x00100000) // Internal ROM base address +#define AT91C_IROM_SIZE ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte) + +#endif diff --git a/target/linux/at91/image/dfboot/src/include/AT91RM9200.inc b/target/linux/at91/image/dfboot/src/include/AT91RM9200.inc new file mode 100644 index 0000000..670e023 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/include/AT91RM9200.inc @@ -0,0 +1,2437 @@ +;- ---------------------------------------------------------------------------- +;- ATMEL Microcontroller Software Support - ROUSSET - +;- ---------------------------------------------------------------------------- +;- The software is delivered "AS IS" without warranty or condition of any +;- kind, either express, implied or statutory. This includes without +;- limitation any warranty or condition with respect to merchantability or +;- fitness for any particular purpose, or against the infringements of +;- intellectual property rights of others. +;- ---------------------------------------------------------------------------- +;- File Name : AT91RM9200.h +;- Object : AT91RM9200 definitions +;- Generated : AT91 SW Application Group 11/19/2003 (17:20:51) +;- +;- CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// +;- CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// +;- CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// +;- CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// +;- CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +;- CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// +;- CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// +;- CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// +;- CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +;- CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// +;- CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// +;- CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// +;- CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// +;- CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// +;- CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// +;- CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// +;- CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// +;- CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// +;- CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// +;- CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// +;- CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// +;- CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// +;- CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// +;- ---------------------------------------------------------------------------- + +;- Hardware register definition + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR System Peripherals +;- ***************************************************************************** + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Memory Controller Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_MC +MC_RCR # 4 ;- MC Remap Control Register +MC_ASR # 4 ;- MC Abort Status Register +MC_AASR # 4 ;- MC Abort Address Status Register + # 4 ;- Reserved +MC_PUIA # 64 ;- MC Protection Unit Area +MC_PUP # 4 ;- MC Protection Unit Peripherals +MC_PUER # 4 ;- MC Protection Unit Enable Register +;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit +;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status +AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status +AT91C_MC_MPU EQU (0x1:SHL:2) ;- (MC) Memory protection Unit Abort Status +AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status +AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte +AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word +AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word +AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status +AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read +AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write +AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch +AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source +AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source +AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source +AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source +;- -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +AT91C_MC_PROT EQU (0x3:SHL:0) ;- (MC) Protection +AT91C_MC_PROT_PNAUNA EQU (0x0) ;- (MC) Privilege: No Access, User: No Access +AT91C_MC_PROT_PRWUNA EQU (0x1) ;- (MC) Privilege: Read/Write, User: No Access +AT91C_MC_PROT_PRWURO EQU (0x2) ;- (MC) Privilege: Read/Write, User: Read Only +AT91C_MC_PROT_PRWURW EQU (0x3) ;- (MC) Privilege: Read/Write, User: Read/Write +AT91C_MC_SIZE EQU (0xF:SHL:4) ;- (MC) Internal Area Size +AT91C_MC_SIZE_1KB EQU (0x0:SHL:4) ;- (MC) Area size 1KByte +AT91C_MC_SIZE_2KB EQU (0x1:SHL:4) ;- (MC) Area size 2KByte +AT91C_MC_SIZE_4KB EQU (0x2:SHL:4) ;- (MC) Area size 4KByte +AT91C_MC_SIZE_8KB EQU (0x3:SHL:4) ;- (MC) Area size 8KByte +AT91C_MC_SIZE_16KB EQU (0x4:SHL:4) ;- (MC) Area size 16KByte +AT91C_MC_SIZE_32KB EQU (0x5:SHL:4) ;- (MC) Area size 32KByte +AT91C_MC_SIZE_64KB EQU (0x6:SHL:4) ;- (MC) Area size 64KByte +AT91C_MC_SIZE_128KB EQU (0x7:SHL:4) ;- (MC) Area size 128KByte +AT91C_MC_SIZE_256KB EQU (0x8:SHL:4) ;- (MC) Area size 256KByte +AT91C_MC_SIZE_512KB EQU (0x9:SHL:4) ;- (MC) Area size 512KByte +AT91C_MC_SIZE_1MB EQU (0xA:SHL:4) ;- (MC) Area size 1MByte +AT91C_MC_SIZE_2MB EQU (0xB:SHL:4) ;- (MC) Area size 2MByte +AT91C_MC_SIZE_4MB EQU (0xC:SHL:4) ;- (MC) Area size 4MByte +AT91C_MC_SIZE_8MB EQU (0xD:SHL:4) ;- (MC) Area size 8MByte +AT91C_MC_SIZE_16MB EQU (0xE:SHL:4) ;- (MC) Area size 16MByte +AT91C_MC_SIZE_64MB EQU (0xF:SHL:4) ;- (MC) Area size 64MByte +AT91C_MC_BA EQU (0x3FFFF:SHL:10) ;- (MC) Internal Area Base Address +;- -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +;- -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +AT91C_MC_PUEB EQU (0x1:SHL:0) ;- (MC) Protection Unit enable Bit + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_RTC +RTC_CR # 4 ;- Control Register +RTC_MR # 4 ;- Mode Register +RTC_TIMR # 4 ;- Time Register +RTC_CALR # 4 ;- Calendar Register +RTC_TIMALR # 4 ;- Time Alarm Register +RTC_CALALR # 4 ;- Calendar Alarm Register +RTC_SR # 4 ;- Status Register +RTC_SCCR # 4 ;- Status Clear Command Register +RTC_IER # 4 ;- Interrupt Enable Register +RTC_IDR # 4 ;- Interrupt Disable Register +RTC_IMR # 4 ;- Interrupt Mask Register +RTC_VER # 4 ;- Valid Entry Register +;- -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- +AT91C_RTC_UPDTIM EQU (0x1:SHL:0) ;- (RTC) Update Request Time Register +AT91C_RTC_UPDCAL EQU (0x1:SHL:1) ;- (RTC) Update Request Calendar Register +AT91C_RTC_TIMEVSEL EQU (0x3:SHL:8) ;- (RTC) Time Event Selection +AT91C_RTC_TIMEVSEL_MINUTE EQU (0x0:SHL:8) ;- (RTC) Minute change. +AT91C_RTC_TIMEVSEL_HOUR EQU (0x1:SHL:8) ;- (RTC) Hour change. +AT91C_RTC_TIMEVSEL_DAY24 EQU (0x2:SHL:8) ;- (RTC) Every day at midnight. +AT91C_RTC_TIMEVSEL_DAY12 EQU (0x3:SHL:8) ;- (RTC) Every day at noon. +AT91C_RTC_CALEVSEL EQU (0x3:SHL:16) ;- (RTC) Calendar Event Selection +AT91C_RTC_CALEVSEL_WEEK EQU (0x0:SHL:16) ;- (RTC) Week change (every Monday at time 00:00:00). +AT91C_RTC_CALEVSEL_MONTH EQU (0x1:SHL:16) ;- (RTC) Month change (every 01 of each month at time 00:00:00). +AT91C_RTC_CALEVSEL_YEAR EQU (0x2:SHL:16) ;- (RTC) Year change (every January 1 at time 00:00:00). +;- -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- +AT91C_RTC_HRMOD EQU (0x1:SHL:0) ;- (RTC) 12-24 hour Mode +;- -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- +AT91C_RTC_SEC EQU (0x7F:SHL:0) ;- (RTC) Current Second +AT91C_RTC_MIN EQU (0x7F:SHL:8) ;- (RTC) Current Minute +AT91C_RTC_HOUR EQU (0x1F:SHL:16) ;- (RTC) Current Hour +AT91C_RTC_AMPM EQU (0x1:SHL:22) ;- (RTC) Ante Meridiem, Post Meridiem Indicator +;- -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- +AT91C_RTC_CENT EQU (0x3F:SHL:0) ;- (RTC) Current Century +AT91C_RTC_YEAR EQU (0xFF:SHL:8) ;- (RTC) Current Year +AT91C_RTC_MONTH EQU (0x1F:SHL:16) ;- (RTC) Current Month +AT91C_RTC_DAY EQU (0x7:SHL:21) ;- (RTC) Current Day +AT91C_RTC_DATE EQU (0x3F:SHL:24) ;- (RTC) Current Date +;- -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- +AT91C_RTC_SECEN EQU (0x1:SHL:7) ;- (RTC) Second Alarm Enable +AT91C_RTC_MINEN EQU (0x1:SHL:15) ;- (RTC) Minute Alarm +AT91C_RTC_HOUREN EQU (0x1:SHL:23) ;- (RTC) Current Hour +;- -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- +AT91C_RTC_MONTHEN EQU (0x1:SHL:23) ;- (RTC) Month Alarm Enable +AT91C_RTC_DATEEN EQU (0x1:SHL:31) ;- (RTC) Date Alarm Enable +;- -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- +AT91C_RTC_ACKUPD EQU (0x1:SHL:0) ;- (RTC) Acknowledge for Update +AT91C_RTC_ALARM EQU (0x1:SHL:1) ;- (RTC) Alarm Flag +AT91C_RTC_SECEV EQU (0x1:SHL:2) ;- (RTC) Second Event +AT91C_RTC_TIMEV EQU (0x1:SHL:3) ;- (RTC) Time Event +AT91C_RTC_CALEV EQU (0x1:SHL:4) ;- (RTC) Calendar event +;- -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- +;- -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- +;- -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- +;- -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- +;- -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- +AT91C_RTC_NVTIM EQU (0x1:SHL:0) ;- (RTC) Non valid Time +AT91C_RTC_NVCAL EQU (0x1:SHL:1) ;- (RTC) Non valid Calendar +AT91C_RTC_NVTIMALR EQU (0x1:SHL:2) ;- (RTC) Non valid time Alarm +AT91C_RTC_NVCALALR EQU (0x1:SHL:3) ;- (RTC) Nonvalid Calendar Alarm + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR System Timer Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_ST +ST_CR # 4 ;- Control Register +ST_PIMR # 4 ;- Period Interval Mode Register +ST_WDMR # 4 ;- Watchdog Mode Register +ST_RTMR # 4 ;- Real-time Mode Register +ST_SR # 4 ;- Status Register +ST_IER # 4 ;- Interrupt Enable Register +ST_IDR # 4 ;- Interrupt Disable Register +ST_IMR # 4 ;- Interrupt Mask Register +ST_RTAR # 4 ;- Real-time Alarm Register +ST_CRTR # 4 ;- Current Real-time Register +;- -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- +AT91C_ST_WDRST EQU (0x1:SHL:0) ;- (ST) Watchdog Timer Restart +;- -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- +AT91C_ST_PIV EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart +;- -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- +AT91C_ST_WDV EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart +AT91C_ST_RSTEN EQU (0x1:SHL:16) ;- (ST) Reset Enable +AT91C_ST_EXTEN EQU (0x1:SHL:17) ;- (ST) External Signal Assertion Enable +;- -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- +AT91C_ST_RTPRES EQU (0xFFFF:SHL:0) ;- (ST) Real-time Timer Prescaler Value +;- -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- +AT91C_ST_PITS EQU (0x1:SHL:0) ;- (ST) Period Interval Timer Interrupt +AT91C_ST_WDOVF EQU (0x1:SHL:1) ;- (ST) Watchdog Overflow +AT91C_ST_RTTINC EQU (0x1:SHL:2) ;- (ST) Real-time Timer Increment +AT91C_ST_ALMS EQU (0x1:SHL:3) ;- (ST) Alarm Status +;- -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- +;- -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- +;- -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- +;- -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- +AT91C_ST_ALMV EQU (0xFFFFF:SHL:0) ;- (ST) Alarm Value Value +;- -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- +AT91C_ST_CRTV EQU (0xFFFFF:SHL:0) ;- (ST) Current Real-time Value + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Power Management Controler +;- ***************************************************************************** + ^ 0 ;- AT91S_PMC +PMC_SCER # 4 ;- System Clock Enable Register +PMC_SCDR # 4 ;- System Clock Disable Register +PMC_SCSR # 4 ;- System Clock Status Register + # 4 ;- Reserved +PMC_PCER # 4 ;- Peripheral Clock Enable Register +PMC_PCDR # 4 ;- Peripheral Clock Disable Register +PMC_PCSR # 4 ;- Peripheral Clock Status Register + # 20 ;- Reserved +PMC_MCKR # 4 ;- Master Clock Register + # 12 ;- Reserved +PMC_PCKR # 32 ;- Programmable Clock Register +PMC_IER # 4 ;- Interrupt Enable Register +PMC_IDR # 4 ;- Interrupt Disable Register +PMC_SR # 4 ;- Status Register +PMC_IMR # 4 ;- Interrupt Mask Register +;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor Clock +AT91C_PMC_UDP EQU (0x1:SHL:1) ;- (PMC) USB Device Port Clock +AT91C_PMC_MCKUDP EQU (0x1:SHL:2) ;- (PMC) USB Device Port Master Clock Automatic Disable on Suspend +AT91C_PMC_UHP EQU (0x1:SHL:4) ;- (PMC) USB Host Port Clock +AT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK3 EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK4 EQU (0x1:SHL:12) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK5 EQU (0x1:SHL:13) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK6 EQU (0x1:SHL:14) ;- (PMC) Programmable Clock Output +AT91C_PMC_PCK7 EQU (0x1:SHL:15) ;- (PMC) Programmable Clock Output +;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection +AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected +AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected +AT91C_PMC_CSS_PLLA_CLK EQU (0x2) ;- (PMC) Clock from PLL A is selected +AT91C_PMC_CSS_PLLB_CLK EQU (0x3) ;- (PMC) Clock from PLL B is selected +AT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler +AT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clock +AT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2 +AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4 +AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8 +AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16 +AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32 +AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64 +AT91C_PMC_MDIV EQU (0x3:SHL:8) ;- (PMC) Master Clock Division +AT91C_PMC_MDIV_1 EQU (0x0:SHL:8) ;- (PMC) The master clock and the processor clock are the same +AT91C_PMC_MDIV_2 EQU (0x1:SHL:8) ;- (PMC) The processor clock is twice as fast as the master clock +AT91C_PMC_MDIV_3 EQU (0x2:SHL:8) ;- (PMC) The processor clock is three times faster than the master clock +AT91C_PMC_MDIV_4 EQU (0x3:SHL:8) ;- (PMC) The processor clock is four times faster than the master clock +;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask +AT91C_PMC_LOCKA EQU (0x1:SHL:1) ;- (PMC) PLL A Status/Enable/Disable/Mask +AT91C_PMC_LOCKB EQU (0x1:SHL:2) ;- (PMC) PLL B Status/Enable/Disable/Mask +AT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK3RDY EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK4RDY EQU (0x1:SHL:12) ;- (PMC) PCK4_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK5RDY EQU (0x1:SHL:13) ;- (PMC) PCK5_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK6RDY EQU (0x1:SHL:14) ;- (PMC) PCK6_RDY Status/Enable/Disable/Mask +AT91C_PMC_PCK7RDY EQU (0x1:SHL:15) ;- (PMC) PCK7_RDY Status/Enable/Disable/Mask +;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Clock Generator Controler +;- ***************************************************************************** + ^ 0 ;- AT91S_CKGR +CKGR_MOR # 4 ;- Main Oscillator Register +CKGR_MCFR # 4 ;- Main Clock Frequency Register +CKGR_PLLAR # 4 ;- PLL A Register +CKGR_PLLBR # 4 ;- PLL B Register +;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable +AT91C_CKGR_OSCTEST EQU (0x1:SHL:1) ;- (CKGR) Oscillator Test +AT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time +;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency +AT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready +;- -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- +AT91C_CKGR_DIVA EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected +AT91C_CKGR_DIVA_0 EQU (0x0) ;- (CKGR) Divider output is 0 +AT91C_CKGR_DIVA_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed +AT91C_CKGR_PLLACOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL A Counter +AT91C_CKGR_OUTA EQU (0x3:SHL:14) ;- (CKGR) PLL A Output Frequency Range +AT91C_CKGR_OUTA_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet +AT91C_CKGR_OUTA_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet +AT91C_CKGR_OUTA_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet +AT91C_CKGR_OUTA_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet +AT91C_CKGR_MULA EQU (0x7FF:SHL:16) ;- (CKGR) PLL A Multiplier +AT91C_CKGR_SRCA EQU (0x1:SHL:29) ;- (CKGR) PLL A Source +;- -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- +AT91C_CKGR_DIVB EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected +AT91C_CKGR_DIVB_0 EQU (0x0) ;- (CKGR) Divider output is 0 +AT91C_CKGR_DIVB_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed +AT91C_CKGR_PLLBCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL B Counter +AT91C_CKGR_OUTB EQU (0x3:SHL:14) ;- (CKGR) PLL B Output Frequency Range +AT91C_CKGR_OUTB_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet +AT91C_CKGR_OUTB_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet +AT91C_CKGR_OUTB_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet +AT91C_CKGR_OUTB_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet +AT91C_CKGR_MULB EQU (0x7FF:SHL:16) ;- (CKGR) PLL B Multiplier +AT91C_CKGR_USB_96M EQU (0x1:SHL:28) ;- (CKGR) Divider for USB Ports +AT91C_CKGR_USB_PLL EQU (0x1:SHL:29) ;- (CKGR) PLL Use + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler +;- ***************************************************************************** + ^ 0 ;- AT91S_PIO +PIO_PER # 4 ;- PIO Enable Register +PIO_PDR # 4 ;- PIO Disable Register +PIO_PSR # 4 ;- PIO Status Register + # 4 ;- Reserved +PIO_OER # 4 ;- Output Enable Register +PIO_ODR # 4 ;- Output Disable Registerr +PIO_OSR # 4 ;- Output Status Register + # 4 ;- Reserved +PIO_IFER # 4 ;- Input Filter Enable Register +PIO_IFDR # 4 ;- Input Filter Disable Register +PIO_IFSR # 4 ;- Input Filter Status Register + # 4 ;- Reserved +PIO_SODR # 4 ;- Set Output Data Register +PIO_CODR # 4 ;- Clear Output Data Register +PIO_ODSR # 4 ;- Output Data Status Register +PIO_PDSR # 4 ;- Pin Data Status Register +PIO_IER # 4 ;- Interrupt Enable Register +PIO_IDR # 4 ;- Interrupt Disable Register +PIO_IMR # 4 ;- Interrupt Mask Register +PIO_ISR # 4 ;- Interrupt Status Register +PIO_MDER # 4 ;- Multi-driver Enable Register +PIO_MDDR # 4 ;- Multi-driver Disable Register +PIO_MDSR # 4 ;- Multi-driver Status Register + # 4 ;- Reserved +PIO_PPUDR # 4 ;- Pull-up Disable Register +PIO_PPUER # 4 ;- Pull-up Enable Register +PIO_PPUSR # 4 ;- Pad Pull-up Status Register + # 4 ;- Reserved +PIO_ASR # 4 ;- Select A Register +PIO_BSR # 4 ;- Select B Register +PIO_ABSR # 4 ;- AB Select Status Register + # 36 ;- Reserved +PIO_OWER # 4 ;- Output Write Enable Register +PIO_OWDR # 4 ;- Output Write Disable Register +PIO_OWSR # 4 ;- Output Write Status Register + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Debug Unit +;- ***************************************************************************** + ^ 0 ;- AT91S_DBGU +DBGU_CR # 4 ;- Control Register +DBGU_MR # 4 ;- Mode Register +DBGU_IER # 4 ;- Interrupt Enable Register +DBGU_IDR # 4 ;- Interrupt Disable Register +DBGU_IMR # 4 ;- Interrupt Mask Register +DBGU_CSR # 4 ;- Channel Status Register +DBGU_RHR # 4 ;- Receiver Holding Register +DBGU_THR # 4 ;- Transmitter Holding Register +DBGU_BRGR # 4 ;- Baud Rate Generator Register + # 28 ;- Reserved +DBGU_C1R # 4 ;- Chip ID1 Register +DBGU_C2R # 4 ;- Chip ID2 Register +DBGU_FNTR # 4 ;- Force NTRST Register + # 180 ;- Reserved +DBGU_RPR # 4 ;- Receive Pointer Register +DBGU_RCR # 4 ;- Receive Counter Register +DBGU_TPR # 4 ;- Transmit Pointer Register +DBGU_TCR # 4 ;- Transmit Counter Register +DBGU_RNPR # 4 ;- Receive Next Pointer Register +DBGU_RNCR # 4 ;- Receive Next Counter Register +DBGU_TNPR # 4 ;- Transmit Next Pointer Register +DBGU_TNCR # 4 ;- Transmit Next Counter Register +DBGU_PTCR # 4 ;- PDC Transfer Control Register +DBGU_PTSR # 4 ;- PDC Transfer Status Register +;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver +AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter +AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable +AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable +AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable +AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable +;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type +AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity +AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity +AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space) +AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark) +AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity +AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode +AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode +AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt +AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt +AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt +AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt +AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt +AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt +AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt +AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt +AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt +AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt +AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt +AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt +;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Peripheral Data Controller +;- ***************************************************************************** + ^ 0 ;- AT91S_PDC +PDC_RPR # 4 ;- Receive Pointer Register +PDC_RCR # 4 ;- Receive Counter Register +PDC_TPR # 4 ;- Transmit Pointer Register +PDC_TCR # 4 ;- Transmit Counter Register +PDC_RNPR # 4 ;- Receive Next Pointer Register +PDC_RNCR # 4 ;- Receive Next Counter Register +PDC_TNPR # 4 ;- Transmit Next Pointer Register +PDC_TNCR # 4 ;- Transmit Next Counter Register +PDC_PTCR # 4 ;- PDC Transfer Control Register +PDC_PTSR # 4 ;- PDC Transfer Status Register +;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable +AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable +AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable +AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable +;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +;- ***************************************************************************** + ^ 0 ;- AT91S_AIC +AIC_SMR # 128 ;- Source Mode Register +AIC_SVR # 128 ;- Source Vector Register +AIC_IVR # 4 ;- IRQ Vector Register +AIC_FVR # 4 ;- FIQ Vector Register +AIC_ISR # 4 ;- Interrupt Status Register +AIC_IPR # 4 ;- Interrupt Pending Register +AIC_IMR # 4 ;- Interrupt Mask Register +AIC_CISR # 4 ;- Core Interrupt Status Register + # 8 ;- Reserved +AIC_IECR # 4 ;- Interrupt Enable Command Register +AIC_IDCR # 4 ;- Interrupt Disable Command Register +AIC_ICCR # 4 ;- Interrupt Clear Command Register +AIC_ISCR # 4 ;- Interrupt Set Command Register +AIC_EOICR # 4 ;- End of Interrupt Command Register +AIC_SPU # 4 ;- Spurious Vector Register +AIC_DCR # 4 ;- Debug Control Register (Protect) + # 4 ;- Reserved +AIC_FFER # 4 ;- Fast Forcing Enable Register +AIC_FFDR # 4 ;- Fast Forcing Disable Register +AIC_FFSR # 4 ;- Fast Forcing Status Register +;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level +AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level +AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level +AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type +AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive +AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered +AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive +AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered +;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status +AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status +;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode +AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Serial Parallel Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_SPI +SPI_CR # 4 ;- Control Register +SPI_MR # 4 ;- Mode Register +SPI_RDR # 4 ;- Receive Data Register +SPI_TDR # 4 ;- Transmit Data Register +SPI_SR # 4 ;- Status Register +SPI_IER # 4 ;- Interrupt Enable Register +SPI_IDR # 4 ;- Interrupt Disable Register +SPI_IMR # 4 ;- Interrupt Mask Register + # 16 ;- Reserved +SPI_CSR # 16 ;- Chip Select Register + # 192 ;- Reserved +SPI_RPR # 4 ;- Receive Pointer Register +SPI_RCR # 4 ;- Receive Counter Register +SPI_TPR # 4 ;- Transmit Pointer Register +SPI_TCR # 4 ;- Transmit Counter Register +SPI_RNPR # 4 ;- Receive Next Pointer Register +SPI_RNCR # 4 ;- Receive Next Counter Register +SPI_TNPR # 4 ;- Transmit Next Pointer Register +SPI_TNCR # 4 ;- Transmit Next Counter Register +SPI_PTCR # 4 ;- PDC Transfer Control Register +SPI_PTSR # 4 ;- PDC Transfer Status Register +;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable +AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable +AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset +;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode +AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select +AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select +AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select +AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode +AT91C_SPI_DIV32 EQU (0x1:SHL:3) ;- (SPI) Clock Selection +AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection +AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection +AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select +AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects +;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data +AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status +;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data +AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status +;- -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full +AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty +AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error +AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status +AT91C_SPI_SPENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer +AT91C_SPI_SPENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer +AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt +AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt +AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status +;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity +AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase +AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer +AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer +AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer +AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer +AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer +AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer +AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer +AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer +AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer +AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer +AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate +AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud Rate +AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_SSC +SSC_CR # 4 ;- Control Register +SSC_CMR # 4 ;- Clock Mode Register + # 8 ;- Reserved +SSC_RCMR # 4 ;- Receive Clock ModeRegister +SSC_RFMR # 4 ;- Receive Frame Mode Register +SSC_TCMR # 4 ;- Transmit Clock Mode Register +SSC_TFMR # 4 ;- Transmit Frame Mode Register +SSC_RHR # 4 ;- Receive Holding Register +SSC_THR # 4 ;- Transmit Holding Register + # 8 ;- Reserved +SSC_RSHR # 4 ;- Receive Sync Holding Register +SSC_TSHR # 4 ;- Transmit Sync Holding Register +SSC_RC0R # 4 ;- Receive Compare 0 Register +SSC_RC1R # 4 ;- Receive Compare 1 Register +SSC_SR # 4 ;- Status Register +SSC_IER # 4 ;- Interrupt Enable Register +SSC_IDR # 4 ;- Interrupt Disable Register +SSC_IMR # 4 ;- Interrupt Mask Register + # 176 ;- Reserved +SSC_RPR # 4 ;- Receive Pointer Register +SSC_RCR # 4 ;- Receive Counter Register +SSC_TPR # 4 ;- Transmit Pointer Register +SSC_TCR # 4 ;- Transmit Counter Register +SSC_RNPR # 4 ;- Receive Next Pointer Register +SSC_RNCR # 4 ;- Receive Next Counter Register +SSC_TNPR # 4 ;- Transmit Next Pointer Register +SSC_TNCR # 4 ;- Transmit Next Counter Register +SSC_PTCR # 4 ;- PDC Transfer Control Register +SSC_PTSR # 4 ;- PDC Transfer Status Register +;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable +AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable +AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable +AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable +AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset +;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection +AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock +AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal +AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin +AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection +AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output +AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion +AT91C_SSC_CKG EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection +AT91C_SSC_CKG_NONE EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock +AT91C_SSC_CKG_LOW EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low +AT91C_SSC_CKG_HIGH EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High +AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection +AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start +AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input +AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input +AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input +AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input +AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input +AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input +AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0 +AT91C_SSC_STOP EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection +AT91C_SSC_STTOUT EQU (0x1:SHL:15) ;- (SSC) Receive/Transmit Start Output Selection +AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay +AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection +;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length +AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode +AT91C_SSC_MSBF EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First +AT91C_SSC_DATNB EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame +AT91C_SSC_FSLEN EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length +AT91C_SSC_FSOS EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection +AT91C_SSC_FSOS_NONE EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +AT91C_SSC_FSOS_NEGATIVE EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +AT91C_SSC_FSOS_POSITIVE EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +AT91C_SSC_FSOS_LOW EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +AT91C_SSC_FSOS_HIGH EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +AT91C_SSC_FSOS_TOGGLE EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +AT91C_SSC_FSEDGE EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection +;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +AT91C_SSC_DATDEF EQU (0x1:SHL:5) ;- (SSC) Data Default Value +AT91C_SSC_FSDEN EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable +;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +AT91C_SSC_TXRDY EQU (0x1:SHL:0) ;- (SSC) Transmit Ready +AT91C_SSC_TXEMPTY EQU (0x1:SHL:1) ;- (SSC) Transmit Empty +AT91C_SSC_ENDTX EQU (0x1:SHL:2) ;- (SSC) End Of Transmission +AT91C_SSC_TXBUFE EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty +AT91C_SSC_RXRDY EQU (0x1:SHL:4) ;- (SSC) Receive Ready +AT91C_SSC_OVRUN EQU (0x1:SHL:5) ;- (SSC) Receive Overrun +AT91C_SSC_ENDRX EQU (0x1:SHL:6) ;- (SSC) End of Reception +AT91C_SSC_RXBUFF EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full +AT91C_SSC_CP0 EQU (0x1:SHL:8) ;- (SSC) Compare 0 +AT91C_SSC_CP1 EQU (0x1:SHL:9) ;- (SSC) Compare 1 +AT91C_SSC_TXSYN EQU (0x1:SHL:10) ;- (SSC) Transmit Sync +AT91C_SSC_RXSYN EQU (0x1:SHL:11) ;- (SSC) Receive Sync +AT91C_SSC_TXENA EQU (0x1:SHL:16) ;- (SSC) Transmit Enable +AT91C_SSC_RXENA EQU (0x1:SHL:17) ;- (SSC) Receive Enable +;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Usart +;- ***************************************************************************** + ^ 0 ;- AT91S_USART +US_CR # 4 ;- Control Register +US_MR # 4 ;- Mode Register +US_IER # 4 ;- Interrupt Enable Register +US_IDR # 4 ;- Interrupt Disable Register +US_IMR # 4 ;- Interrupt Mask Register +US_CSR # 4 ;- Channel Status Register +US_RHR # 4 ;- Receiver Holding Register +US_THR # 4 ;- Transmitter Holding Register +US_BRGR # 4 ;- Baud Rate Generator Register +US_RTOR # 4 ;- Receiver Time-out Register +US_TTGR # 4 ;- Transmitter Time-guard Register + # 20 ;- Reserved +US_FIDI # 4 ;- FI_DI_Ratio Register +US_NER # 4 ;- Nb Errors Register +US_XXR # 4 ;- XON_XOFF Register +US_IF # 4 ;- IRDA_FILTER Register + # 176 ;- Reserved +US_RPR # 4 ;- Receive Pointer Register +US_RCR # 4 ;- Receive Counter Register +US_TPR # 4 ;- Transmit Pointer Register +US_TCR # 4 ;- Transmit Counter Register +US_RNPR # 4 ;- Receive Next Pointer Register +US_RNCR # 4 ;- Receive Next Counter Register +US_TNPR # 4 ;- Transmit Next Pointer Register +US_TNCR # 4 ;- Transmit Next Counter Register +US_PTCR # 4 ;- PDC Transfer Control Register +US_PTSR # 4 ;- PDC Transfer Status Register +;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (USART) Reset Status Bits +AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break +AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break +AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out +AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address +AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations +AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge +AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out +AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable +AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable +AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable +AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable +;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode +AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal +AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 +AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking +AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem +AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 +AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 +AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA +AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking +AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock +AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1 +AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM) +AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK) +AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock +AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits +AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits +AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits +AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits +AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select +AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits +AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit +AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits +AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order +AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length +AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select +AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode +AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge +AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK +AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions +AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter +;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break +AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out +AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached +AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge +AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag +AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag +AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag +AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag +;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input +AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input +AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input +AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Two-wire Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_TWI +TWI_CR # 4 ;- Control Register +TWI_MMR # 4 ;- Master Mode Register +TWI_SMR # 4 ;- Slave Mode Register +TWI_IADR # 4 ;- Internal Address Register +TWI_CWGR # 4 ;- Clock Waveform Generator Register + # 12 ;- Reserved +TWI_SR # 4 ;- Status Register +TWI_IER # 4 ;- Interrupt Enable Register +TWI_IDR # 4 ;- Interrupt Disable Register +TWI_IMR # 4 ;- Interrupt Mask Register +TWI_RHR # 4 ;- Receive Holding Register +TWI_THR # 4 ;- Transmit Holding Register +;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition +AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition +AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled +AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled +AT91C_TWI_SVEN EQU (0x1:SHL:4) ;- (TWI) TWI Slave Transfer Enabled +AT91C_TWI_SVDIS EQU (0x1:SHL:5) ;- (TWI) TWI Slave Transfer Disabled +AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset +;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size +AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address +AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address +AT91C_TWI_IADRSZ_2_BYTE EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address +AT91C_TWI_IADRSZ_3_BYTE EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address +AT91C_TWI_MREAD EQU (0x1:SHL:12) ;- (TWI) Master Read Direction +AT91C_TWI_DADR EQU (0x7F:SHL:16) ;- (TWI) Device Address +;- -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +AT91C_TWI_SADR EQU (0x7F:SHL:16) ;- (TWI) Slave Device Address +;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +AT91C_TWI_CLDIV EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider +AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider +AT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider +;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission Completed +AT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY +AT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY +AT91C_TWI_SVREAD EQU (0x1:SHL:3) ;- (TWI) Slave Read +AT91C_TWI_SVACC EQU (0x1:SHL:4) ;- (TWI) Slave Access +AT91C_TWI_GCACC EQU (0x1:SHL:5) ;- (TWI) General Call Access +AT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun Error +AT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun Error +AT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged +AT91C_TWI_ARBLST EQU (0x1:SHL:9) ;- (TWI) Arbitration Lost +;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Multimedia Card Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_MCI +MCI_CR # 4 ;- MCI Control Register +MCI_MR # 4 ;- MCI Mode Register +MCI_DTOR # 4 ;- MCI Data Timeout Register +MCI_SDCR # 4 ;- MCI SD Card Register +MCI_ARGR # 4 ;- MCI Argument Register +MCI_CMDR # 4 ;- MCI Command Register + # 8 ;- Reserved +MCI_RSPR # 16 ;- MCI Response Register +MCI_RDR # 4 ;- MCI Receive Data Register +MCI_TDR # 4 ;- MCI Transmit Data Register + # 8 ;- Reserved +MCI_SR # 4 ;- MCI Status Register +MCI_IER # 4 ;- MCI Interrupt Enable Register +MCI_IDR # 4 ;- MCI Interrupt Disable Register +MCI_IMR # 4 ;- MCI Interrupt Mask Register + # 176 ;- Reserved +MCI_RPR # 4 ;- Receive Pointer Register +MCI_RCR # 4 ;- Receive Counter Register +MCI_TPR # 4 ;- Transmit Pointer Register +MCI_TCR # 4 ;- Transmit Counter Register +MCI_RNPR # 4 ;- Receive Next Pointer Register +MCI_RNCR # 4 ;- Receive Next Counter Register +MCI_TNPR # 4 ;- Transmit Next Pointer Register +MCI_TNCR # 4 ;- Transmit Next Counter Register +MCI_PTCR # 4 ;- PDC Transfer Control Register +MCI_PTSR # 4 ;- PDC Transfer Status Register +;- -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +AT91C_MCI_MCIEN EQU (0x1:SHL:0) ;- (MCI) Multimedia Interface Enable +AT91C_MCI_MCIDIS EQU (0x1:SHL:1) ;- (MCI) Multimedia Interface Disable +AT91C_MCI_PWSEN EQU (0x1:SHL:2) ;- (MCI) Power Save Mode Enable +AT91C_MCI_PWSDIS EQU (0x1:SHL:3) ;- (MCI) Power Save Mode Disable +;- -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +AT91C_MCI_CLKDIV EQU (0x1:SHL:0) ;- (MCI) Clock Divider +AT91C_MCI_PWSDIV EQU (0x1:SHL:8) ;- (MCI) Power Saving Divider +AT91C_MCI_PDCPADV EQU (0x1:SHL:14) ;- (MCI) PDC Padding Value +AT91C_MCI_PDCMODE EQU (0x1:SHL:15) ;- (MCI) PDC Oriented Mode +AT91C_MCI_BLKLEN EQU (0x1:SHL:18) ;- (MCI) Data Block Length +;- -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +AT91C_MCI_DTOCYC EQU (0x1:SHL:0) ;- (MCI) Data Timeout Cycle Number +AT91C_MCI_DTOMUL EQU (0x7:SHL:4) ;- (MCI) Data Timeout Multiplier +AT91C_MCI_DTOMUL_1 EQU (0x0:SHL:4) ;- (MCI) DTOCYC x 1 +AT91C_MCI_DTOMUL_16 EQU (0x1:SHL:4) ;- (MCI) DTOCYC x 16 +AT91C_MCI_DTOMUL_128 EQU (0x2:SHL:4) ;- (MCI) DTOCYC x 128 +AT91C_MCI_DTOMUL_256 EQU (0x3:SHL:4) ;- (MCI) DTOCYC x 256 +AT91C_MCI_DTOMUL_1024 EQU (0x4:SHL:4) ;- (MCI) DTOCYC x 1024 +AT91C_MCI_DTOMUL_4096 EQU (0x5:SHL:4) ;- (MCI) DTOCYC x 4096 +AT91C_MCI_DTOMUL_65536 EQU (0x6:SHL:4) ;- (MCI) DTOCYC x 65536 +AT91C_MCI_DTOMUL_1048576 EQU (0x7:SHL:4) ;- (MCI) DTOCYC x 1048576 +;- -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +AT91C_MCI_SCDSEL EQU (0x1:SHL:0) ;- (MCI) SD Card Selector +AT91C_MCI_SCDBUS EQU (0x1:SHL:7) ;- (MCI) SD Card Bus Width +;- -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +AT91C_MCI_CMDNB EQU (0x1F:SHL:0) ;- (MCI) Command Number +AT91C_MCI_RSPTYP EQU (0x3:SHL:6) ;- (MCI) Response Type +AT91C_MCI_RSPTYP_NO EQU (0x0:SHL:6) ;- (MCI) No response +AT91C_MCI_RSPTYP_48 EQU (0x1:SHL:6) ;- (MCI) 48-bit response +AT91C_MCI_RSPTYP_136 EQU (0x2:SHL:6) ;- (MCI) 136-bit response +AT91C_MCI_SPCMD EQU (0x7:SHL:8) ;- (MCI) Special CMD +AT91C_MCI_SPCMD_NONE EQU (0x0:SHL:8) ;- (MCI) Not a special CMD +AT91C_MCI_SPCMD_INIT EQU (0x1:SHL:8) ;- (MCI) Initialization CMD +AT91C_MCI_SPCMD_SYNC EQU (0x2:SHL:8) ;- (MCI) Synchronized CMD +AT91C_MCI_SPCMD_IT_CMD EQU (0x4:SHL:8) ;- (MCI) Interrupt command +AT91C_MCI_SPCMD_IT_REP EQU (0x5:SHL:8) ;- (MCI) Interrupt response +AT91C_MCI_OPDCMD EQU (0x1:SHL:11) ;- (MCI) Open Drain Command +AT91C_MCI_MAXLAT EQU (0x1:SHL:12) ;- (MCI) Maximum Latency for Command to respond +AT91C_MCI_TRCMD EQU (0x3:SHL:16) ;- (MCI) Transfer CMD +AT91C_MCI_TRCMD_NO EQU (0x0:SHL:16) ;- (MCI) No transfer +AT91C_MCI_TRCMD_START EQU (0x1:SHL:16) ;- (MCI) Start transfer +AT91C_MCI_TRCMD_STOP EQU (0x2:SHL:16) ;- (MCI) Stop transfer +AT91C_MCI_TRDIR EQU (0x1:SHL:18) ;- (MCI) Transfer Direction +AT91C_MCI_TRTYP EQU (0x3:SHL:19) ;- (MCI) Transfer Type +AT91C_MCI_TRTYP_BLOCK EQU (0x0:SHL:19) ;- (MCI) Block Transfer type +AT91C_MCI_TRTYP_MULTIPLE EQU (0x1:SHL:19) ;- (MCI) Multiple Block transfer type +AT91C_MCI_TRTYP_STREAM EQU (0x2:SHL:19) ;- (MCI) Stream transfer type +;- -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +AT91C_MCI_CMDRDY EQU (0x1:SHL:0) ;- (MCI) Command Ready flag +AT91C_MCI_RXRDY EQU (0x1:SHL:1) ;- (MCI) RX Ready flag +AT91C_MCI_TXRDY EQU (0x1:SHL:2) ;- (MCI) TX Ready flag +AT91C_MCI_BLKE EQU (0x1:SHL:3) ;- (MCI) Data Block Transfer Ended flag +AT91C_MCI_DTIP EQU (0x1:SHL:4) ;- (MCI) Data Transfer in Progress flag +AT91C_MCI_NOTBUSY EQU (0x1:SHL:5) ;- (MCI) Data Line Not Busy flag +AT91C_MCI_ENDRX EQU (0x1:SHL:6) ;- (MCI) End of RX Buffer flag +AT91C_MCI_ENDTX EQU (0x1:SHL:7) ;- (MCI) End of TX Buffer flag +AT91C_MCI_RXBUFF EQU (0x1:SHL:14) ;- (MCI) RX Buffer Full flag +AT91C_MCI_TXBUFE EQU (0x1:SHL:15) ;- (MCI) TX Buffer Empty flag +AT91C_MCI_RINDE EQU (0x1:SHL:16) ;- (MCI) Response Index Error flag +AT91C_MCI_RDIRE EQU (0x1:SHL:17) ;- (MCI) Response Direction Error flag +AT91C_MCI_RCRCE EQU (0x1:SHL:18) ;- (MCI) Response CRC Error flag +AT91C_MCI_RENDE EQU (0x1:SHL:19) ;- (MCI) Response End Bit Error flag +AT91C_MCI_RTOE EQU (0x1:SHL:20) ;- (MCI) Response Time-out Error flag +AT91C_MCI_DCRCE EQU (0x1:SHL:21) ;- (MCI) data CRC Error flag +AT91C_MCI_DTOE EQU (0x1:SHL:22) ;- (MCI) Data timeout Error flag +AT91C_MCI_OVRE EQU (0x1:SHL:30) ;- (MCI) Overrun flag +AT91C_MCI_UNRE EQU (0x1:SHL:31) ;- (MCI) Underrun flag +;- -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +;- -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +;- -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR USB Device Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_UDP +UDP_NUM # 4 ;- Frame Number Register +UDP_GLBSTATE # 4 ;- Global State Register +UDP_FADDR # 4 ;- Function Address Register + # 4 ;- Reserved +UDP_IER # 4 ;- Interrupt Enable Register +UDP_IDR # 4 ;- Interrupt Disable Register +UDP_IMR # 4 ;- Interrupt Mask Register +UDP_ISR # 4 ;- Interrupt Status Register +UDP_ICR # 4 ;- Interrupt Clear Register + # 4 ;- Reserved +UDP_RSTEP # 4 ;- Reset Endpoint Register + # 4 ;- Reserved +UDP_CSR # 32 ;- Endpoint Control and Status Register +UDP_FDR # 32 ;- Endpoint FIFO Data Register +;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +AT91C_UDP_FRM_NUM EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats +AT91C_UDP_FRM_ERR EQU (0x1:SHL:16) ;- (UDP) Frame Error +AT91C_UDP_FRM_OK EQU (0x1:SHL:17) ;- (UDP) Frame OK +;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +AT91C_UDP_FADDEN EQU (0x1:SHL:0) ;- (UDP) Function Address Enable +AT91C_UDP_CONFG EQU (0x1:SHL:1) ;- (UDP) Configured +AT91C_UDP_RMWUPE EQU (0x1:SHL:2) ;- (UDP) Remote Wake Up Enable +AT91C_UDP_RSMINPR EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host +;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +AT91C_UDP_FADD EQU (0xFF:SHL:0) ;- (UDP) Function Address Value +AT91C_UDP_FEN EQU (0x1:SHL:8) ;- (UDP) Function Enable +;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +AT91C_UDP_EPINT0 EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT1 EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt +AT91C_UDP_EPINT2 EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt +AT91C_UDP_EPINT3 EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt +AT91C_UDP_EPINT4 EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt +AT91C_UDP_EPINT5 EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt +AT91C_UDP_EPINT6 EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 Interrupt +AT91C_UDP_EPINT7 EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 Interrupt +AT91C_UDP_RXSUSP EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt +AT91C_UDP_RXRSM EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt +AT91C_UDP_EXTRSM EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt +AT91C_UDP_SOFINT EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt +AT91C_UDP_WAKEUP EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt +;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +AT91C_UDP_ENDBUSRES EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt +;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +AT91C_UDP_EP0 EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0 +AT91C_UDP_EP1 EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1 +AT91C_UDP_EP2 EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2 +AT91C_UDP_EP3 EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3 +AT91C_UDP_EP4 EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4 +AT91C_UDP_EP5 EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5 +AT91C_UDP_EP6 EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6 +AT91C_UDP_EP7 EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7 +;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +AT91C_UDP_TXCOMP EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR +AT91C_UDP_RX_DATA_BK0 EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0 +AT91C_UDP_RXSETUP EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints) +AT91C_UDP_ISOERROR EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints) +AT91C_UDP_TXPKTRDY EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready +AT91C_UDP_FORCESTALL EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +AT91C_UDP_RX_DATA_BK1 EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +AT91C_UDP_DIR EQU (0x1:SHL:7) ;- (UDP) Transfer Direction +AT91C_UDP_EPTYPE EQU (0x7:SHL:8) ;- (UDP) Endpoint type +AT91C_UDP_EPTYPE_CTRL EQU (0x0:SHL:8) ;- (UDP) Control +AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT +AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT +AT91C_UDP_EPTYPE_INT_OUT EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT +AT91C_UDP_EPTYPE_ISO_IN EQU (0x5:SHL:8) ;- (UDP) Isochronous IN +AT91C_UDP_EPTYPE_BULK_IN EQU (0x6:SHL:8) ;- (UDP) Bulk IN +AT91C_UDP_EPTYPE_INT_IN EQU (0x7:SHL:8) ;- (UDP) Interrupt IN +AT91C_UDP_DTGLE EQU (0x1:SHL:11) ;- (UDP) Data Toggle +AT91C_UDP_EPEDS EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable +AT91C_UDP_RXBYTECNT EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_TC +TC_CCR # 4 ;- Channel Control Register +TC_CMR # 4 ;- Channel Mode Register + # 8 ;- Reserved +TC_CV # 4 ;- Counter Value +TC_RA # 4 ;- Register A +TC_RB # 4 ;- Register B +TC_RC # 4 ;- Register C +TC_SR # 4 ;- Status Register +TC_IER # 4 ;- Interrupt Enable Register +TC_IDR # 4 ;- Interrupt Disable Register +TC_IMR # 4 ;- Interrupt Mask Register +;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command +AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command +AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command +;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare +AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare +AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection +AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None +AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge +AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge +AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge +AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection +AT91C_TC_EEVT_NONE EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input +AT91C_TC_EEVT_RISING EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output +AT91C_TC_EEVT_FALLING EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output +AT91C_TC_EEVT_BOTH EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output +AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable +AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection +AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare +AT91C_TC_WAVESEL_UP_AUTO EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare +AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare +AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable +AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC) +AT91C_TC_ACPA EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA +AT91C_TC_ACPA_NONE EQU (0x0:SHL:16) ;- (TC) Effect: none +AT91C_TC_ACPA_SET EQU (0x1:SHL:16) ;- (TC) Effect: set +AT91C_TC_ACPA_CLEAR EQU (0x2:SHL:16) ;- (TC) Effect: clear +AT91C_TC_ACPA_TOGGLE EQU (0x3:SHL:16) ;- (TC) Effect: toggle +AT91C_TC_ACPC EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA +AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none +AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set +AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear +AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle +AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA +AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none +AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set +AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear +AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle +AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA +AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none +AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set +AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear +AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle +AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB +AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none +AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set +AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear +AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle +AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB +AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none +AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set +AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear +AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle +AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB +AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none +AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set +AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear +AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle +AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB +AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none +AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set +AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear +AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle +;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow +AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun +AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare +AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare +AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare +AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading +AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading +AT91C_TC_ETRCS EQU (0x1:SHL:7) ;- (TC) External Trigger +AT91C_TC_ETRGS EQU (0x1:SHL:16) ;- (TC) Clock Enabling +AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror +AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror +;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Timer Counter Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_TCB +TCB_TC0 # 48 ;- TC Channel 0 + # 16 ;- Reserved +TCB_TC1 # 48 ;- TC Channel 1 + # 16 ;- Reserved +TCB_TC2 # 48 ;- TC Channel 2 + # 16 ;- Reserved +TCB_BCR # 4 ;- TC Block Control Register +TCB_BMR # 4 ;- TC Block Mode Register +;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +AT91C_TCB_SYNC EQU (0x1:SHL:0) ;- (TCB) Synchro Command +;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +AT91C_TCB_TC0XC0S EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection +AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 +AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 +AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 +AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 +AT91C_TCB_TC1XC1S EQU (0x1:SHL:2) ;- (TCB) External Clock Signal 1 Selection +AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1 +AT91C_TCB_TC1XC1S_NONE EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1 +AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1 +AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1 +AT91C_TCB_TC2XC2S EQU (0x1:SHL:4) ;- (TCB) External Clock Signal 2 Selection +AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2 +AT91C_TCB_TC2XC2S_NONE EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2 +AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2 +AT91C_TCB_TC2XC2S_TIOA2 EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2 + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR USB Host Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_UHP +UHP_HcRevision # 4 ;- Revision +UHP_HcControl # 4 ;- Operating modes for the Host Controller +UHP_HcCommandStatus # 4 ;- Command & status Register +UHP_HcInterruptStatus # 4 ;- Interrupt Status Register +UHP_HcInterruptEnable # 4 ;- Interrupt Enable Register +UHP_HcInterruptDisable # 4 ;- Interrupt Disable Register +UHP_HcHCCA # 4 ;- Pointer to the Host Controller Communication Area +UHP_HcPeriodCurrentED # 4 ;- Current Isochronous or Interrupt Endpoint Descriptor +UHP_HcControlHeadED # 4 ;- First Endpoint Descriptor of the Control list +UHP_HcControlCurrentED # 4 ;- Endpoint Control and Status Register +UHP_HcBulkHeadED # 4 ;- First endpoint register of the Bulk list +UHP_HcBulkCurrentED # 4 ;- Current endpoint of the Bulk list +UHP_HcBulkDoneHead # 4 ;- Last completed transfer descriptor +UHP_HcFmInterval # 4 ;- Bit time between 2 consecutive SOFs +UHP_HcFmRemaining # 4 ;- Bit time remaining in the current Frame +UHP_HcFmNumber # 4 ;- Frame number +UHP_HcPeriodicStart # 4 ;- Periodic Start +UHP_HcLSThreshold # 4 ;- LS Threshold +UHP_HcRhDescriptorA # 4 ;- Root Hub characteristics A +UHP_HcRhDescriptorB # 4 ;- Root Hub characteristics B +UHP_HcRhStatus # 4 ;- Root Hub Status register +UHP_HcRhPortStatus # 8 ;- Root Hub Port Status Register + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Ethernet MAC +;- ***************************************************************************** + ^ 0 ;- AT91S_EMAC +EMAC_CTL # 4 ;- Network Control Register +EMAC_CFG # 4 ;- Network Configuration Register +EMAC_SR # 4 ;- Network Status Register +EMAC_TAR # 4 ;- Transmit Address Register +EMAC_TCR # 4 ;- Transmit Control Register +EMAC_TSR # 4 ;- Transmit Status Register +EMAC_RBQP # 4 ;- Receive Buffer Queue Pointer + # 4 ;- Reserved +EMAC_RSR # 4 ;- Receive Status Register +EMAC_ISR # 4 ;- Interrupt Status Register +EMAC_IER # 4 ;- Interrupt Enable Register +EMAC_IDR # 4 ;- Interrupt Disable Register +EMAC_IMR # 4 ;- Interrupt Mask Register +EMAC_MAN # 4 ;- PHY Maintenance Register + # 8 ;- Reserved +EMAC_FRA # 4 ;- Frames Transmitted OK Register +EMAC_SCOL # 4 ;- Single Collision Frame Register +EMAC_MCOL # 4 ;- Multiple Collision Frame Register +EMAC_OK # 4 ;- Frames Received OK Register +EMAC_SEQE # 4 ;- Frame Check Sequence Error Register +EMAC_ALE # 4 ;- Alignment Error Register +EMAC_DTE # 4 ;- Deferred Transmission Frame Register +EMAC_LCOL # 4 ;- Late Collision Register +EMAC_ECOL # 4 ;- Excessive Collision Register +EMAC_CSE # 4 ;- Carrier Sense Error Register +EMAC_TUE # 4 ;- Transmit Underrun Error Register +EMAC_CDE # 4 ;- Code Error Register +EMAC_ELR # 4 ;- Excessive Length Error Register +EMAC_RJB # 4 ;- Receive Jabber Register +EMAC_USF # 4 ;- Undersize Frame Register +EMAC_SQEE # 4 ;- SQE Test Error Register +EMAC_DRFC # 4 ;- Discarded RX Frame Register + # 12 ;- Reserved +EMAC_HSH # 4 ;- Hash Address High[63:32] +EMAC_HSL # 4 ;- Hash Address Low[31:0] +EMAC_SA1L # 4 ;- Specific Address 1 Low, First 4 bytes +EMAC_SA1H # 4 ;- Specific Address 1 High, Last 2 bytes +EMAC_SA2L # 4 ;- Specific Address 2 Low, First 4 bytes +EMAC_SA2H # 4 ;- Specific Address 2 High, Last 2 bytes +EMAC_SA3L # 4 ;- Specific Address 3 Low, First 4 bytes +EMAC_SA3H # 4 ;- Specific Address 3 High, Last 2 bytes +EMAC_SA4L # 4 ;- Specific Address 4 Low, First 4 bytes +EMAC_SA4H # 4 ;- Specific Address 4 High, Last 2 bytesr +;- -------- EMAC_CTL : (EMAC Offset: 0x0) -------- +AT91C_EMAC_LB EQU (0x1:SHL:0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. +AT91C_EMAC_LBL EQU (0x1:SHL:1) ;- (EMAC) Loopback local. +AT91C_EMAC_RE EQU (0x1:SHL:2) ;- (EMAC) Receive enable. +AT91C_EMAC_TE EQU (0x1:SHL:3) ;- (EMAC) Transmit enable. +AT91C_EMAC_MPE EQU (0x1:SHL:4) ;- (EMAC) Management port enable. +AT91C_EMAC_CSR EQU (0x1:SHL:5) ;- (EMAC) Clear statistics registers. +AT91C_EMAC_ISR EQU (0x1:SHL:6) ;- (EMAC) Increment statistics registers. +AT91C_EMAC_WES EQU (0x1:SHL:7) ;- (EMAC) Write enable for statistics registers. +AT91C_EMAC_BP EQU (0x1:SHL:8) ;- (EMAC) Back pressure. +;- -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- +AT91C_EMAC_SPD EQU (0x1:SHL:0) ;- (EMAC) Speed. +AT91C_EMAC_FD EQU (0x1:SHL:1) ;- (EMAC) Full duplex. +AT91C_EMAC_BR EQU (0x1:SHL:2) ;- (EMAC) Bit rate. +AT91C_EMAC_CAF EQU (0x1:SHL:4) ;- (EMAC) Copy all frames. +AT91C_EMAC_NBC EQU (0x1:SHL:5) ;- (EMAC) No broadcast. +AT91C_EMAC_MTI EQU (0x1:SHL:6) ;- (EMAC) Multicast hash enable +AT91C_EMAC_UNI EQU (0x1:SHL:7) ;- (EMAC) Unicast hash enable. +AT91C_EMAC_BIG EQU (0x1:SHL:8) ;- (EMAC) Receive 1522 bytes. +AT91C_EMAC_EAE EQU (0x1:SHL:9) ;- (EMAC) External address match enable. +AT91C_EMAC_CLK EQU (0x3:SHL:10) ;- (EMAC) +AT91C_EMAC_CLK_HCLK_8 EQU (0x0:SHL:10) ;- (EMAC) HCLK divided by 8 +AT91C_EMAC_CLK_HCLK_16 EQU (0x1:SHL:10) ;- (EMAC) HCLK divided by 16 +AT91C_EMAC_CLK_HCLK_32 EQU (0x2:SHL:10) ;- (EMAC) HCLK divided by 32 +AT91C_EMAC_CLK_HCLK_64 EQU (0x3:SHL:10) ;- (EMAC) HCLK divided by 64 +AT91C_EMAC_RTY EQU (0x1:SHL:12) ;- (EMAC) +AT91C_EMAC_RMII EQU (0x1:SHL:13) ;- (EMAC) +;- -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- +AT91C_EMAC_MDIO EQU (0x1:SHL:1) ;- (EMAC) +AT91C_EMAC_IDLE EQU (0x1:SHL:2) ;- (EMAC) +;- -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- +AT91C_EMAC_LEN EQU (0x7FF:SHL:0) ;- (EMAC) +AT91C_EMAC_NCRC EQU (0x1:SHL:15) ;- (EMAC) +;- -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- +AT91C_EMAC_OVR EQU (0x1:SHL:0) ;- (EMAC) +AT91C_EMAC_COL EQU (0x1:SHL:1) ;- (EMAC) +AT91C_EMAC_RLE EQU (0x1:SHL:2) ;- (EMAC) +AT91C_EMAC_TXIDLE EQU (0x1:SHL:3) ;- (EMAC) +AT91C_EMAC_BNQ EQU (0x1:SHL:4) ;- (EMAC) +AT91C_EMAC_COMP EQU (0x1:SHL:5) ;- (EMAC) +AT91C_EMAC_UND EQU (0x1:SHL:6) ;- (EMAC) +;- -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +AT91C_EMAC_BNA EQU (0x1:SHL:0) ;- (EMAC) +AT91C_EMAC_REC EQU (0x1:SHL:1) ;- (EMAC) +;- -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +AT91C_EMAC_DONE EQU (0x1:SHL:0) ;- (EMAC) +AT91C_EMAC_RCOM EQU (0x1:SHL:1) ;- (EMAC) +AT91C_EMAC_RBNA EQU (0x1:SHL:2) ;- (EMAC) +AT91C_EMAC_TOVR EQU (0x1:SHL:3) ;- (EMAC) +AT91C_EMAC_TUND EQU (0x1:SHL:4) ;- (EMAC) +AT91C_EMAC_RTRY EQU (0x1:SHL:5) ;- (EMAC) +AT91C_EMAC_TBRE EQU (0x1:SHL:6) ;- (EMAC) +AT91C_EMAC_TCOM EQU (0x1:SHL:7) ;- (EMAC) +AT91C_EMAC_TIDLE EQU (0x1:SHL:8) ;- (EMAC) +AT91C_EMAC_LINK EQU (0x1:SHL:9) ;- (EMAC) +AT91C_EMAC_ROVR EQU (0x1:SHL:10) ;- (EMAC) +AT91C_EMAC_HRESP EQU (0x1:SHL:11) ;- (EMAC) +;- -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +;- -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +;- -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +;- -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +AT91C_EMAC_DATA EQU (0xFFFF:SHL:0) ;- (EMAC) +AT91C_EMAC_CODE EQU (0x3:SHL:16) ;- (EMAC) +AT91C_EMAC_REGA EQU (0x1F:SHL:18) ;- (EMAC) +AT91C_EMAC_PHYA EQU (0x1F:SHL:23) ;- (EMAC) +AT91C_EMAC_RW EQU (0x3:SHL:28) ;- (EMAC) +AT91C_EMAC_HIGH EQU (0x1:SHL:30) ;- (EMAC) +AT91C_EMAC_LOW EQU (0x1:SHL:31) ;- (EMAC) + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR External Bus Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_EBI +EBI_CSA # 4 ;- Chip Select Assignment Register +EBI_CFGR # 4 ;- Configuration Register +;- -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- +AT91C_EBI_CS0A EQU (0x1:SHL:0) ;- (EBI) Chip Select 0 Assignment +AT91C_EBI_CS0A_SMC EQU (0x0) ;- (EBI) Chip Select 0 is assigned to the Static Memory Controller. +AT91C_EBI_CS0A_BFC EQU (0x1) ;- (EBI) Chip Select 0 is assigned to the Burst Flash Controller. +AT91C_EBI_CS1A EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 Assignment +AT91C_EBI_CS1A_SMC EQU (0x0:SHL:1) ;- (EBI) Chip Select 1 is assigned to the Static Memory Controller. +AT91C_EBI_CS1A_SDRAMC EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 is assigned to the SDRAM Controller. +AT91C_EBI_CS3A EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 Assignment +AT91C_EBI_CS3A_SMC EQU (0x0:SHL:3) ;- (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. +AT91C_EBI_CS3A_SMC_SmartMedia EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +AT91C_EBI_CS4A EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 Assignment +AT91C_EBI_CS4A_SMC EQU (0x0:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. +AT91C_EBI_CS4A_SMC_CompactFlash EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. +;- -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- +AT91C_EBI_DBPUC EQU (0x1:SHL:0) ;- (EBI) Data Bus Pull-Up Configuration +AT91C_EBI_EBSEN EQU (0x1:SHL:1) ;- (EBI) Bus Sharing Enable + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_SMC2 +SMC2_CSR # 32 ;- SMC2 Chip Select Register +;- -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- +AT91C_SMC2_NWS EQU (0x7F:SHL:0) ;- (SMC2) Number of Wait States +AT91C_SMC2_WSEN EQU (0x1:SHL:7) ;- (SMC2) Wait State Enable +AT91C_SMC2_TDF EQU (0xF:SHL:8) ;- (SMC2) Data Float Time +AT91C_SMC2_BAT EQU (0x1:SHL:12) ;- (SMC2) Byte Access Type +AT91C_SMC2_DBW EQU (0x1:SHL:13) ;- (SMC2) Data Bus Width +AT91C_SMC2_DBW_16 EQU (0x1:SHL:13) ;- (SMC2) 16-bit. +AT91C_SMC2_DBW_8 EQU (0x2:SHL:13) ;- (SMC2) 8-bit. +AT91C_SMC2_DRP EQU (0x1:SHL:15) ;- (SMC2) Data Read Protocol +AT91C_SMC2_ACSS EQU (0x3:SHL:16) ;- (SMC2) Address to Chip Select Setup +AT91C_SMC2_ACSS_STANDARD EQU (0x0:SHL:16) ;- (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. +AT91C_SMC2_ACSS_1_CYCLE EQU (0x1:SHL:16) ;- (SMC2) One cycle less at the beginning and the end of the access. +AT91C_SMC2_ACSS_2_CYCLES EQU (0x2:SHL:16) ;- (SMC2) Two cycles less at the beginning and the end of the access. +AT91C_SMC2_ACSS_3_CYCLES EQU (0x3:SHL:16) ;- (SMC2) Three cycles less at the beginning and the end of the access. +AT91C_SMC2_RWSETUP EQU (0x7:SHL:24) ;- (SMC2) Read and Write Signal Setup Time +AT91C_SMC2_RWHOLD EQU (0x7:SHL:29) ;- (SMC2) Read and Write Signal Hold Time + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR SDRAM Controller Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_SDRC +SDRC_MR # 4 ;- SDRAM Controller Mode Register +SDRC_TR # 4 ;- SDRAM Controller Refresh Timer Register +SDRC_CR # 4 ;- SDRAM Controller Configuration Register +SDRC_SRR # 4 ;- SDRAM Controller Self Refresh Register +SDRC_LPR # 4 ;- SDRAM Controller Low Power Register +SDRC_IER # 4 ;- SDRAM Controller Interrupt Enable Register +SDRC_IDR # 4 ;- SDRAM Controller Interrupt Disable Register +SDRC_IMR # 4 ;- SDRAM Controller Interrupt Mask Register +SDRC_ISR # 4 ;- SDRAM Controller Interrupt Mask Register +;- -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- +AT91C_SDRC_MODE EQU (0xF:SHL:0) ;- (SDRC) Mode +AT91C_SDRC_MODE_NORMAL_CMD EQU (0x0) ;- (SDRC) Normal Mode +AT91C_SDRC_MODE_NOP_CMD EQU (0x1) ;- (SDRC) NOP Command +AT91C_SDRC_MODE_PRCGALL_CMD EQU (0x2) ;- (SDRC) All Banks Precharge Command +AT91C_SDRC_MODE_LMR_CMD EQU (0x3) ;- (SDRC) Load Mode Register Command +AT91C_SDRC_MODE_RFSH_CMD EQU (0x4) ;- (SDRC) Refresh Command +AT91C_SDRC_DBW EQU (0x1:SHL:4) ;- (SDRC) Data Bus Width +AT91C_SDRC_DBW_32_BITS EQU (0x0:SHL:4) ;- (SDRC) 32 Bits datas bus +AT91C_SDRC_DBW_16_BITS EQU (0x1:SHL:4) ;- (SDRC) 16 Bits datas bus +;- -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- +AT91C_SDRC_COUNT EQU (0xFFF:SHL:0) ;- (SDRC) Refresh Counter +;- -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- +AT91C_SDRC_NC EQU (0x3:SHL:0) ;- (SDRC) Number of Column Bits +AT91C_SDRC_NC_8 EQU (0x0) ;- (SDRC) 8 Bits +AT91C_SDRC_NC_9 EQU (0x1) ;- (SDRC) 9 Bits +AT91C_SDRC_NC_10 EQU (0x2) ;- (SDRC) 10 Bits +AT91C_SDRC_NC_11 EQU (0x3) ;- (SDRC) 11 Bits +AT91C_SDRC_NR EQU (0x3:SHL:2) ;- (SDRC) Number of Row Bits +AT91C_SDRC_NR_11 EQU (0x0:SHL:2) ;- (SDRC) 11 Bits +AT91C_SDRC_NR_12 EQU (0x1:SHL:2) ;- (SDRC) 12 Bits +AT91C_SDRC_NR_13 EQU (0x2:SHL:2) ;- (SDRC) 13 Bits +AT91C_SDRC_NB EQU (0x1:SHL:4) ;- (SDRC) Number of Banks +AT91C_SDRC_NB_2_BANKS EQU (0x0:SHL:4) ;- (SDRC) 2 banks +AT91C_SDRC_NB_4_BANKS EQU (0x1:SHL:4) ;- (SDRC) 4 banks +AT91C_SDRC_CAS EQU (0x3:SHL:5) ;- (SDRC) CAS Latency +AT91C_SDRC_CAS_2 EQU (0x2:SHL:5) ;- (SDRC) 2 cycles +AT91C_SDRC_TWR EQU (0xF:SHL:7) ;- (SDRC) Number of Write Recovery Time Cycles +AT91C_SDRC_TRC EQU (0xF:SHL:11) ;- (SDRC) Number of RAS Cycle Time Cycles +AT91C_SDRC_TRP EQU (0xF:SHL:15) ;- (SDRC) Number of RAS Precharge Time Cycles +AT91C_SDRC_TRCD EQU (0xF:SHL:19) ;- (SDRC) Number of RAS to CAS Delay Cycles +AT91C_SDRC_TRAS EQU (0xF:SHL:23) ;- (SDRC) Number of RAS Active Time Cycles +AT91C_SDRC_TXSR EQU (0xF:SHL:27) ;- (SDRC) Number of Command Recovery Time Cycles +;- -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- +AT91C_SDRC_SRCB EQU (0x1:SHL:0) ;- (SDRC) Self-refresh Command Bit +;- -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- +AT91C_SDRC_LPCB EQU (0x1:SHL:0) ;- (SDRC) Low-power Command Bit +;- -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +AT91C_SDRC_RES EQU (0x1:SHL:0) ;- (SDRC) Refresh Error Status +;- -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +;- -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +;- -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- + +;- ***************************************************************************** +;- SOFTWARE API DEFINITION FOR Burst Flash Controller Interface +;- ***************************************************************************** + ^ 0 ;- AT91S_BFC +BFC_MR # 4 ;- BFC Mode Register +;- -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- +AT91C_BFC_BFCOM EQU (0x3:SHL:0) ;- (BFC) Burst Flash Controller Operating Mode +AT91C_BFC_BFCOM_DISABLED EQU (0x0) ;- (BFC) NPCS0 is driven by the SMC or remains high. +AT91C_BFC_BFCOM_ASYNC EQU (0x1) ;- (BFC) Asynchronous +AT91C_BFC_BFCOM_BURST_READ EQU (0x2) ;- (BFC) Burst Read +AT91C_BFC_BFCC EQU (0x3:SHL:2) ;- (BFC) Burst Flash Controller Operating Mode +AT91C_BFC_BFCC_MCK EQU (0x1:SHL:2) ;- (BFC) Master Clock. +AT91C_BFC_BFCC_MCK_DIV_2 EQU (0x2:SHL:2) ;- (BFC) Master Clock divided by 2. +AT91C_BFC_BFCC_MCK_DIV_4 EQU (0x3:SHL:2) ;- (BFC) Master Clock divided by 4. +AT91C_BFC_AVL EQU (0xF:SHL:4) ;- (BFC) Address Valid Latency +AT91C_BFC_PAGES EQU (0x7:SHL:8) ;- (BFC) Page Size +AT91C_BFC_PAGES_NO_PAGE EQU (0x0:SHL:8) ;- (BFC) No page handling. +AT91C_BFC_PAGES_16 EQU (0x1:SHL:8) ;- (BFC) 16 bytes page size. +AT91C_BFC_PAGES_32 EQU (0x2:SHL:8) ;- (BFC) 32 bytes page size. +AT91C_BFC_PAGES_64 EQU (0x3:SHL:8) ;- (BFC) 64 bytes page size. +AT91C_BFC_PAGES_128 EQU (0x4:SHL:8) ;- (BFC) 128 bytes page size. +AT91C_BFC_PAGES_256 EQU (0x5:SHL:8) ;- (BFC) 256 bytes page size. +AT91C_BFC_PAGES_512 EQU (0x6:SHL:8) ;- (BFC) 512 bytes page size. +AT91C_BFC_PAGES_1024 EQU (0x7:SHL:8) ;- (BFC) 1024 bytes page size. +AT91C_BFC_OEL EQU (0x3:SHL:12) ;- (BFC) Output Enable Latency +AT91C_BFC_BAAEN EQU (0x1:SHL:16) ;- (BFC) Burst Address Advance Enable +AT91C_BFC_BFOEH EQU (0x1:SHL:17) ;- (BFC) Burst Flash Output Enable Handling +AT91C_BFC_MUXEN EQU (0x1:SHL:18) ;- (BFC) Multiplexed Bus Enable +AT91C_BFC_RDYEN EQU (0x1:SHL:19) ;- (BFC) Ready Enable Mode + +;- ***************************************************************************** +;- REGISTER ADDRESS DEFINITION FOR AT91RM9200 +;- ***************************************************************************** +;- ========== Register definition for SYS peripheral ========== +;- ========== Register definition for MC peripheral ========== +AT91C_MC_PUER EQU (0xFFFFFF54) ;- (MC) MC Protection Unit Enable Register +AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register +AT91C_MC_PUP EQU (0xFFFFFF50) ;- (MC) MC Protection Unit Peripherals +AT91C_MC_PUIA EQU (0xFFFFFF10) ;- (MC) MC Protection Unit Area +AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register +AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register +;- ========== Register definition for RTC peripheral ========== +AT91C_RTC_IMR EQU (0xFFFFFE28) ;- (RTC) Interrupt Mask Register +AT91C_RTC_IER EQU (0xFFFFFE20) ;- (RTC) Interrupt Enable Register +AT91C_RTC_SR EQU (0xFFFFFE18) ;- (RTC) Status Register +AT91C_RTC_TIMALR EQU (0xFFFFFE10) ;- (RTC) Time Alarm Register +AT91C_RTC_TIMR EQU (0xFFFFFE08) ;- (RTC) Time Register +AT91C_RTC_CR EQU (0xFFFFFE00) ;- (RTC) Control Register +AT91C_RTC_VER EQU (0xFFFFFE2C) ;- (RTC) Valid Entry Register +AT91C_RTC_IDR EQU (0xFFFFFE24) ;- (RTC) Interrupt Disable Register +AT91C_RTC_SCCR EQU (0xFFFFFE1C) ;- (RTC) Status Clear Command Register +AT91C_RTC_CALALR EQU (0xFFFFFE14) ;- (RTC) Calendar Alarm Register +AT91C_RTC_CALR EQU (0xFFFFFE0C) ;- (RTC) Calendar Register +AT91C_RTC_MR EQU (0xFFFFFE04) ;- (RTC) Mode Register +;- ========== Register definition for ST peripheral ========== +AT91C_ST_CRTR EQU (0xFFFFFD24) ;- (ST) Current Real-time Register +AT91C_ST_IMR EQU (0xFFFFFD1C) ;- (ST) Interrupt Mask Register +AT91C_ST_IER EQU (0xFFFFFD14) ;- (ST) Interrupt Enable Register +AT91C_ST_RTMR EQU (0xFFFFFD0C) ;- (ST) Real-time Mode Register +AT91C_ST_PIMR EQU (0xFFFFFD04) ;- (ST) Period Interval Mode Register +AT91C_ST_RTAR EQU (0xFFFFFD20) ;- (ST) Real-time Alarm Register +AT91C_ST_IDR EQU (0xFFFFFD18) ;- (ST) Interrupt Disable Register +AT91C_ST_SR EQU (0xFFFFFD10) ;- (ST) Status Register +AT91C_ST_WDMR EQU (0xFFFFFD08) ;- (ST) Watchdog Mode Register +AT91C_ST_CR EQU (0xFFFFFD00) ;- (ST) Control Register +;- ========== Register definition for PMC peripheral ========== +AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register +AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register +AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register +AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register +AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register +AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register +AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register +AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register +AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register +AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register +AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register +AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register +;- ========== Register definition for CKGR peripheral ========== +AT91C_CKGR_PLLBR EQU (0xFFFFFC2C) ;- (CKGR) PLL B Register +AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register +AT91C_CKGR_PLLAR EQU (0xFFFFFC28) ;- (CKGR) PLL A Register +AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register +;- ========== Register definition for PIOD peripheral ========== +AT91C_PIOD_PDSR EQU (0xFFFFFA3C) ;- (PIOD) Pin Data Status Register +AT91C_PIOD_CODR EQU (0xFFFFFA34) ;- (PIOD) Clear Output Data Register +AT91C_PIOD_OWER EQU (0xFFFFFAA0) ;- (PIOD) Output Write Enable Register +AT91C_PIOD_MDER EQU (0xFFFFFA50) ;- (PIOD) Multi-driver Enable Register +AT91C_PIOD_IMR EQU (0xFFFFFA48) ;- (PIOD) Interrupt Mask Register +AT91C_PIOD_IER EQU (0xFFFFFA40) ;- (PIOD) Interrupt Enable Register +AT91C_PIOD_ODSR EQU (0xFFFFFA38) ;- (PIOD) Output Data Status Register +AT91C_PIOD_SODR EQU (0xFFFFFA30) ;- (PIOD) Set Output Data Register +AT91C_PIOD_PER EQU (0xFFFFFA00) ;- (PIOD) PIO Enable Register +AT91C_PIOD_OWDR EQU (0xFFFFFAA4) ;- (PIOD) Output Write Disable Register +AT91C_PIOD_PPUER EQU (0xFFFFFA64) ;- (PIOD) Pull-up Enable Register +AT91C_PIOD_MDDR EQU (0xFFFFFA54) ;- (PIOD) Multi-driver Disable Register +AT91C_PIOD_ISR EQU (0xFFFFFA4C) ;- (PIOD) Interrupt Status Register +AT91C_PIOD_IDR EQU (0xFFFFFA44) ;- (PIOD) Interrupt Disable Register +AT91C_PIOD_PDR EQU (0xFFFFFA04) ;- (PIOD) PIO Disable Register +AT91C_PIOD_ODR EQU (0xFFFFFA14) ;- (PIOD) Output Disable Registerr +AT91C_PIOD_OWSR EQU (0xFFFFFAA8) ;- (PIOD) Output Write Status Register +AT91C_PIOD_ABSR EQU (0xFFFFFA78) ;- (PIOD) AB Select Status Register +AT91C_PIOD_ASR EQU (0xFFFFFA70) ;- (PIOD) Select A Register +AT91C_PIOD_PPUSR EQU (0xFFFFFA68) ;- (PIOD) Pad Pull-up Status Register +AT91C_PIOD_PPUDR EQU (0xFFFFFA60) ;- (PIOD) Pull-up Disable Register +AT91C_PIOD_MDSR EQU (0xFFFFFA58) ;- (PIOD) Multi-driver Status Register +AT91C_PIOD_PSR EQU (0xFFFFFA08) ;- (PIOD) PIO Status Register +AT91C_PIOD_OER EQU (0xFFFFFA10) ;- (PIOD) Output Enable Register +AT91C_PIOD_OSR EQU (0xFFFFFA18) ;- (PIOD) Output Status Register +AT91C_PIOD_IFER EQU (0xFFFFFA20) ;- (PIOD) Input Filter Enable Register +AT91C_PIOD_BSR EQU (0xFFFFFA74) ;- (PIOD) Select B Register +AT91C_PIOD_IFDR EQU (0xFFFFFA24) ;- (PIOD) Input Filter Disable Register +AT91C_PIOD_IFSR EQU (0xFFFFFA28) ;- (PIOD) Input Filter Status Register +;- ========== Register definition for PIOC peripheral ========== +AT91C_PIOC_IFDR EQU (0xFFFFF824) ;- (PIOC) Input Filter Disable Register +AT91C_PIOC_ODR EQU (0xFFFFF814) ;- (PIOC) Output Disable Registerr +AT91C_PIOC_ABSR EQU (0xFFFFF878) ;- (PIOC) AB Select Status Register +AT91C_PIOC_SODR EQU (0xFFFFF830) ;- (PIOC) Set Output Data Register +AT91C_PIOC_IFSR EQU (0xFFFFF828) ;- (PIOC) Input Filter Status Register +AT91C_PIOC_CODR EQU (0xFFFFF834) ;- (PIOC) Clear Output Data Register +AT91C_PIOC_ODSR EQU (0xFFFFF838) ;- (PIOC) Output Data Status Register +AT91C_PIOC_IER EQU (0xFFFFF840) ;- (PIOC) Interrupt Enable Register +AT91C_PIOC_IMR EQU (0xFFFFF848) ;- (PIOC) Interrupt Mask Register +AT91C_PIOC_OWDR EQU (0xFFFFF8A4) ;- (PIOC) Output Write Disable Register +AT91C_PIOC_MDDR EQU (0xFFFFF854) ;- (PIOC) Multi-driver Disable Register +AT91C_PIOC_PDSR EQU (0xFFFFF83C) ;- (PIOC) Pin Data Status Register +AT91C_PIOC_IDR EQU (0xFFFFF844) ;- (PIOC) Interrupt Disable Register +AT91C_PIOC_ISR EQU (0xFFFFF84C) ;- (PIOC) Interrupt Status Register +AT91C_PIOC_PDR EQU (0xFFFFF804) ;- (PIOC) PIO Disable Register +AT91C_PIOC_OWSR EQU (0xFFFFF8A8) ;- (PIOC) Output Write Status Register +AT91C_PIOC_OWER EQU (0xFFFFF8A0) ;- (PIOC) Output Write Enable Register +AT91C_PIOC_ASR EQU (0xFFFFF870) ;- (PIOC) Select A Register +AT91C_PIOC_PPUSR EQU (0xFFFFF868) ;- (PIOC) Pad Pull-up Status Register +AT91C_PIOC_PPUDR EQU (0xFFFFF860) ;- (PIOC) Pull-up Disable Register +AT91C_PIOC_MDSR EQU (0xFFFFF858) ;- (PIOC) Multi-driver Status Register +AT91C_PIOC_MDER EQU (0xFFFFF850) ;- (PIOC) Multi-driver Enable Register +AT91C_PIOC_IFER EQU (0xFFFFF820) ;- (PIOC) Input Filter Enable Register +AT91C_PIOC_OSR EQU (0xFFFFF818) ;- (PIOC) Output Status Register +AT91C_PIOC_OER EQU (0xFFFFF810) ;- (PIOC) Output Enable Register +AT91C_PIOC_PSR EQU (0xFFFFF808) ;- (PIOC) PIO Status Register +AT91C_PIOC_PER EQU (0xFFFFF800) ;- (PIOC) PIO Enable Register +AT91C_PIOC_BSR EQU (0xFFFFF874) ;- (PIOC) Select B Register +AT91C_PIOC_PPUER EQU (0xFFFFF864) ;- (PIOC) Pull-up Enable Register +;- ========== Register definition for PIOB peripheral ========== +AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register +AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pad Pull-up Status Register +AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register +AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register +AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register +AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register +AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register +AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register +AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register +AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register +AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register +AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register +AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register +AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr +AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register +AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register +AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register +AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register +AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register +AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register +AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register +AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register +AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register +AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register +AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register +AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register +AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register +AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register +AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register +;- ========== Register definition for PIOA peripheral ========== +AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register +AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register +AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register +AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register +AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register +AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register +AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register +AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register +AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register +AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register +AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register +AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register +AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register +AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register +AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr +AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register +AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register +AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register +AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pad Pull-up Status Register +AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register +AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register +AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register +AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register +AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register +AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register +AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register +AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register +AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register +AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register +;- ========== Register definition for DBGU peripheral ========== +AT91C_DBGU_C2R EQU (0xFFFFF244) ;- (DBGU) Chip ID2 Register +AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register +AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register +AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register +AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register +AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register +AT91C_DBGU_C1R EQU (0xFFFFF240) ;- (DBGU) Chip ID1 Register +AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register +AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register +AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register +AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register +AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register +;- ========== Register definition for PDC_DBGU peripheral ========== +AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register +AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register +AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register +AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register +AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register +AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register +AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register +AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register +AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register +AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register +;- ========== Register definition for AIC peripheral ========== +AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register +AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register +AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register +AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register +AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register +AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) +AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register +AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register +AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register +AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register +AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register +AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register +AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register +AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register +AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register +AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register +AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register +AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register +;- ========== Register definition for PDC_SPI peripheral ========== +AT91C_SPI_PTCR EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register +AT91C_SPI_TNPR EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register +AT91C_SPI_RNPR EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register +AT91C_SPI_TPR EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register +AT91C_SPI_RPR EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register +AT91C_SPI_PTSR EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register +AT91C_SPI_TNCR EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register +AT91C_SPI_RNCR EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register +AT91C_SPI_TCR EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register +AT91C_SPI_RCR EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register +;- ========== Register definition for SPI peripheral ========== +AT91C_SPI_CSR EQU (0xFFFE0030) ;- (SPI) Chip Select Register +AT91C_SPI_IDR EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register +AT91C_SPI_SR EQU (0xFFFE0010) ;- (SPI) Status Register +AT91C_SPI_RDR EQU (0xFFFE0008) ;- (SPI) Receive Data Register +AT91C_SPI_CR EQU (0xFFFE0000) ;- (SPI) Control Register +AT91C_SPI_IMR EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register +AT91C_SPI_IER EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register +AT91C_SPI_TDR EQU (0xFFFE000C) ;- (SPI) Transmit Data Register +AT91C_SPI_MR EQU (0xFFFE0004) ;- (SPI) Mode Register +;- ========== Register definition for PDC_SSC2 peripheral ========== +AT91C_SSC2_PTCR EQU (0xFFFD8120) ;- (PDC_SSC2) PDC Transfer Control Register +AT91C_SSC2_TNPR EQU (0xFFFD8118) ;- (PDC_SSC2) Transmit Next Pointer Register +AT91C_SSC2_RNPR EQU (0xFFFD8110) ;- (PDC_SSC2) Receive Next Pointer Register +AT91C_SSC2_TPR EQU (0xFFFD8108) ;- (PDC_SSC2) Transmit Pointer Register +AT91C_SSC2_RPR EQU (0xFFFD8100) ;- (PDC_SSC2) Receive Pointer Register +AT91C_SSC2_PTSR EQU (0xFFFD8124) ;- (PDC_SSC2) PDC Transfer Status Register +AT91C_SSC2_TNCR EQU (0xFFFD811C) ;- (PDC_SSC2) Transmit Next Counter Register +AT91C_SSC2_RNCR EQU (0xFFFD8114) ;- (PDC_SSC2) Receive Next Counter Register +AT91C_SSC2_TCR EQU (0xFFFD810C) ;- (PDC_SSC2) Transmit Counter Register +AT91C_SSC2_RCR EQU (0xFFFD8104) ;- (PDC_SSC2) Receive Counter Register +;- ========== Register definition for SSC2 peripheral ========== +AT91C_SSC2_IMR EQU (0xFFFD804C) ;- (SSC2) Interrupt Mask Register +AT91C_SSC2_IER EQU (0xFFFD8044) ;- (SSC2) Interrupt Enable Register +AT91C_SSC2_RC1R EQU (0xFFFD803C) ;- (SSC2) Receive Compare 1 Register +AT91C_SSC2_TSHR EQU (0xFFFD8034) ;- (SSC2) Transmit Sync Holding Register +AT91C_SSC2_CMR EQU (0xFFFD8004) ;- (SSC2) Clock Mode Register +AT91C_SSC2_IDR EQU (0xFFFD8048) ;- (SSC2) Interrupt Disable Register +AT91C_SSC2_TCMR EQU (0xFFFD8018) ;- (SSC2) Transmit Clock Mode Register +AT91C_SSC2_RCMR EQU (0xFFFD8010) ;- (SSC2) Receive Clock ModeRegister +AT91C_SSC2_CR EQU (0xFFFD8000) ;- (SSC2) Control Register +AT91C_SSC2_RFMR EQU (0xFFFD8014) ;- (SSC2) Receive Frame Mode Register +AT91C_SSC2_TFMR EQU (0xFFFD801C) ;- (SSC2) Transmit Frame Mode Register +AT91C_SSC2_THR EQU (0xFFFD8024) ;- (SSC2) Transmit Holding Register +AT91C_SSC2_SR EQU (0xFFFD8040) ;- (SSC2) Status Register +AT91C_SSC2_RC0R EQU (0xFFFD8038) ;- (SSC2) Receive Compare 0 Register +AT91C_SSC2_RSHR EQU (0xFFFD8030) ;- (SSC2) Receive Sync Holding Register +AT91C_SSC2_RHR EQU (0xFFFD8020) ;- (SSC2) Receive Holding Register +;- ========== Register definition for PDC_SSC1 peripheral ========== +AT91C_SSC1_PTCR EQU (0xFFFD4120) ;- (PDC_SSC1) PDC Transfer Control Register +AT91C_SSC1_TNPR EQU (0xFFFD4118) ;- (PDC_SSC1) Transmit Next Pointer Register +AT91C_SSC1_RNPR EQU (0xFFFD4110) ;- (PDC_SSC1) Receive Next Pointer Register +AT91C_SSC1_TPR EQU (0xFFFD4108) ;- (PDC_SSC1) Transmit Pointer Register +AT91C_SSC1_RPR EQU (0xFFFD4100) ;- (PDC_SSC1) Receive Pointer Register +AT91C_SSC1_PTSR EQU (0xFFFD4124) ;- (PDC_SSC1) PDC Transfer Status Register +AT91C_SSC1_TNCR EQU (0xFFFD411C) ;- (PDC_SSC1) Transmit Next Counter Register +AT91C_SSC1_RNCR EQU (0xFFFD4114) ;- (PDC_SSC1) Receive Next Counter Register +AT91C_SSC1_TCR EQU (0xFFFD410C) ;- (PDC_SSC1) Transmit Counter Register +AT91C_SSC1_RCR EQU (0xFFFD4104) ;- (PDC_SSC1) Receive Counter Register +;- ========== Register definition for SSC1 peripheral ========== +AT91C_SSC1_RFMR EQU (0xFFFD4014) ;- (SSC1) Receive Frame Mode Register +AT91C_SSC1_CMR EQU (0xFFFD4004) ;- (SSC1) Clock Mode Register +AT91C_SSC1_IDR EQU (0xFFFD4048) ;- (SSC1) Interrupt Disable Register +AT91C_SSC1_SR EQU (0xFFFD4040) ;- (SSC1) Status Register +AT91C_SSC1_RC0R EQU (0xFFFD4038) ;- (SSC1) Receive Compare 0 Register +AT91C_SSC1_RSHR EQU (0xFFFD4030) ;- (SSC1) Receive Sync Holding Register +AT91C_SSC1_RHR EQU (0xFFFD4020) ;- (SSC1) Receive Holding Register +AT91C_SSC1_TCMR EQU (0xFFFD4018) ;- (SSC1) Transmit Clock Mode Register +AT91C_SSC1_RCMR EQU (0xFFFD4010) ;- (SSC1) Receive Clock ModeRegister +AT91C_SSC1_CR EQU (0xFFFD4000) ;- (SSC1) Control Register +AT91C_SSC1_IMR EQU (0xFFFD404C) ;- (SSC1) Interrupt Mask Register +AT91C_SSC1_IER EQU (0xFFFD4044) ;- (SSC1) Interrupt Enable Register +AT91C_SSC1_RC1R EQU (0xFFFD403C) ;- (SSC1) Receive Compare 1 Register +AT91C_SSC1_TSHR EQU (0xFFFD4034) ;- (SSC1) Transmit Sync Holding Register +AT91C_SSC1_THR EQU (0xFFFD4024) ;- (SSC1) Transmit Holding Register +AT91C_SSC1_TFMR EQU (0xFFFD401C) ;- (SSC1) Transmit Frame Mode Register +;- ========== Register definition for PDC_SSC0 peripheral ========== +AT91C_SSC0_PTCR EQU (0xFFFD0120) ;- (PDC_SSC0) PDC Transfer Control Register +AT91C_SSC0_TNPR EQU (0xFFFD0118) ;- (PDC_SSC0) Transmit Next Pointer Register +AT91C_SSC0_RNPR EQU (0xFFFD0110) ;- (PDC_SSC0) Receive Next Pointer Register +AT91C_SSC0_TPR EQU (0xFFFD0108) ;- (PDC_SSC0) Transmit Pointer Register +AT91C_SSC0_RPR EQU (0xFFFD0100) ;- (PDC_SSC0) Receive Pointer Register +AT91C_SSC0_PTSR EQU (0xFFFD0124) ;- (PDC_SSC0) PDC Transfer Status Register +AT91C_SSC0_TNCR EQU (0xFFFD011C) ;- (PDC_SSC0) Transmit Next Counter Register +AT91C_SSC0_RNCR EQU (0xFFFD0114) ;- (PDC_SSC0) Receive Next Counter Register +AT91C_SSC0_TCR EQU (0xFFFD010C) ;- (PDC_SSC0) Transmit Counter Register +AT91C_SSC0_RCR EQU (0xFFFD0104) ;- (PDC_SSC0) Receive Counter Register +;- ========== Register definition for SSC0 peripheral ========== +AT91C_SSC0_IMR EQU (0xFFFD004C) ;- (SSC0) Interrupt Mask Register +AT91C_SSC0_IER EQU (0xFFFD0044) ;- (SSC0) Interrupt Enable Register +AT91C_SSC0_RC1R EQU (0xFFFD003C) ;- (SSC0) Receive Compare 1 Register +AT91C_SSC0_TSHR EQU (0xFFFD0034) ;- (SSC0) Transmit Sync Holding Register +AT91C_SSC0_THR EQU (0xFFFD0024) ;- (SSC0) Transmit Holding Register +AT91C_SSC0_TFMR EQU (0xFFFD001C) ;- (SSC0) Transmit Frame Mode Register +AT91C_SSC0_RFMR EQU (0xFFFD0014) ;- (SSC0) Receive Frame Mode Register +AT91C_SSC0_CMR EQU (0xFFFD0004) ;- (SSC0) Clock Mode Register +AT91C_SSC0_IDR EQU (0xFFFD0048) ;- (SSC0) Interrupt Disable Register +AT91C_SSC0_SR EQU (0xFFFD0040) ;- (SSC0) Status Register +AT91C_SSC0_RC0R EQU (0xFFFD0038) ;- (SSC0) Receive Compare 0 Register +AT91C_SSC0_RSHR EQU (0xFFFD0030) ;- (SSC0) Receive Sync Holding Register +AT91C_SSC0_RHR EQU (0xFFFD0020) ;- (SSC0) Receive Holding Register +AT91C_SSC0_TCMR EQU (0xFFFD0018) ;- (SSC0) Transmit Clock Mode Register +AT91C_SSC0_RCMR EQU (0xFFFD0010) ;- (SSC0) Receive Clock ModeRegister +AT91C_SSC0_CR EQU (0xFFFD0000) ;- (SSC0) Control Register +;- ========== Register definition for PDC_US3 peripheral ========== +AT91C_US3_PTSR EQU (0xFFFCC124) ;- (PDC_US3) PDC Transfer Status Register +AT91C_US3_TNCR EQU (0xFFFCC11C) ;- (PDC_US3) Transmit Next Counter Register +AT91C_US3_RNCR EQU (0xFFFCC114) ;- (PDC_US3) Receive Next Counter Register +AT91C_US3_TCR EQU (0xFFFCC10C) ;- (PDC_US3) Transmit Counter Register +AT91C_US3_RCR EQU (0xFFFCC104) ;- (PDC_US3) Receive Counter Register +AT91C_US3_PTCR EQU (0xFFFCC120) ;- (PDC_US3) PDC Transfer Control Register +AT91C_US3_TNPR EQU (0xFFFCC118) ;- (PDC_US3) Transmit Next Pointer Register +AT91C_US3_RNPR EQU (0xFFFCC110) ;- (PDC_US3) Receive Next Pointer Register +AT91C_US3_TPR EQU (0xFFFCC108) ;- (PDC_US3) Transmit Pointer Register +AT91C_US3_RPR EQU (0xFFFCC100) ;- (PDC_US3) Receive Pointer Register +;- ========== Register definition for US3 peripheral ========== +AT91C_US3_IF EQU (0xFFFCC04C) ;- (US3) IRDA_FILTER Register +AT91C_US3_NER EQU (0xFFFCC044) ;- (US3) Nb Errors Register +AT91C_US3_RTOR EQU (0xFFFCC024) ;- (US3) Receiver Time-out Register +AT91C_US3_THR EQU (0xFFFCC01C) ;- (US3) Transmitter Holding Register +AT91C_US3_CSR EQU (0xFFFCC014) ;- (US3) Channel Status Register +AT91C_US3_IDR EQU (0xFFFCC00C) ;- (US3) Interrupt Disable Register +AT91C_US3_MR EQU (0xFFFCC004) ;- (US3) Mode Register +AT91C_US3_XXR EQU (0xFFFCC048) ;- (US3) XON_XOFF Register +AT91C_US3_FIDI EQU (0xFFFCC040) ;- (US3) FI_DI_Ratio Register +AT91C_US3_TTGR EQU (0xFFFCC028) ;- (US3) Transmitter Time-guard Register +AT91C_US3_BRGR EQU (0xFFFCC020) ;- (US3) Baud Rate Generator Register +AT91C_US3_RHR EQU (0xFFFCC018) ;- (US3) Receiver Holding Register +AT91C_US3_IMR EQU (0xFFFCC010) ;- (US3) Interrupt Mask Register +AT91C_US3_IER EQU (0xFFFCC008) ;- (US3) Interrupt Enable Register +AT91C_US3_CR EQU (0xFFFCC000) ;- (US3) Control Register +;- ========== Register definition for PDC_US2 peripheral ========== +AT91C_US2_PTSR EQU (0xFFFC8124) ;- (PDC_US2) PDC Transfer Status Register +AT91C_US2_TNCR EQU (0xFFFC811C) ;- (PDC_US2) Transmit Next Counter Register +AT91C_US2_RNCR EQU (0xFFFC8114) ;- (PDC_US2) Receive Next Counter Register +AT91C_US2_TCR EQU (0xFFFC810C) ;- (PDC_US2) Transmit Counter Register +AT91C_US2_PTCR EQU (0xFFFC8120) ;- (PDC_US2) PDC Transfer Control Register +AT91C_US2_RCR EQU (0xFFFC8104) ;- (PDC_US2) Receive Counter Register +AT91C_US2_TNPR EQU (0xFFFC8118) ;- (PDC_US2) Transmit Next Pointer Register +AT91C_US2_RPR EQU (0xFFFC8100) ;- (PDC_US2) Receive Pointer Register +AT91C_US2_TPR EQU (0xFFFC8108) ;- (PDC_US2) Transmit Pointer Register +AT91C_US2_RNPR EQU (0xFFFC8110) ;- (PDC_US2) Receive Next Pointer Register +;- ========== Register definition for US2 peripheral ========== +AT91C_US2_XXR EQU (0xFFFC8048) ;- (US2) XON_XOFF Register +AT91C_US2_FIDI EQU (0xFFFC8040) ;- (US2) FI_DI_Ratio Register +AT91C_US2_TTGR EQU (0xFFFC8028) ;- (US2) Transmitter Time-guard Register +AT91C_US2_BRGR EQU (0xFFFC8020) ;- (US2) Baud Rate Generator Register +AT91C_US2_RHR EQU (0xFFFC8018) ;- (US2) Receiver Holding Register +AT91C_US2_IMR EQU (0xFFFC8010) ;- (US2) Interrupt Mask Register +AT91C_US2_IER EQU (0xFFFC8008) ;- (US2) Interrupt Enable Register +AT91C_US2_CR EQU (0xFFFC8000) ;- (US2) Control Register +AT91C_US2_IF EQU (0xFFFC804C) ;- (US2) IRDA_FILTER Register +AT91C_US2_NER EQU (0xFFFC8044) ;- (US2) Nb Errors Register +AT91C_US2_RTOR EQU (0xFFFC8024) ;- (US2) Receiver Time-out Register +AT91C_US2_THR EQU (0xFFFC801C) ;- (US2) Transmitter Holding Register +AT91C_US2_CSR EQU (0xFFFC8014) ;- (US2) Channel Status Register +AT91C_US2_IDR EQU (0xFFFC800C) ;- (US2) Interrupt Disable Register +AT91C_US2_MR EQU (0xFFFC8004) ;- (US2) Mode Register +;- ========== Register definition for PDC_US1 peripheral ========== +AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register +AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register +AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register +AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register +AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register +AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register +AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register +AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register +AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register +AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register +;- ========== Register definition for US1 peripheral ========== +AT91C_US1_XXR EQU (0xFFFC4048) ;- (US1) XON_XOFF Register +AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register +AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register +AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register +AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register +AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register +AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register +AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register +AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register +AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register +AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register +AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register +AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register +AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register +AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register +;- ========== Register definition for PDC_US0 peripheral ========== +AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register +AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register +AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register +AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register +AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register +AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register +AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register +AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register +AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register +AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register +;- ========== Register definition for US0 peripheral ========== +AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register +AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register +AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register +AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register +AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register +AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register +AT91C_US0_XXR EQU (0xFFFC0048) ;- (US0) XON_XOFF Register +AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register +AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register +AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register +AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register +AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register +AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register +AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register +AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register +;- ========== Register definition for TWI peripheral ========== +AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register +AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register +AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register +AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register +AT91C_TWI_SMR EQU (0xFFFB8008) ;- (TWI) Slave Mode Register +AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register +AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register +AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register +AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register +AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register +AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register +;- ========== Register definition for PDC_MCI peripheral ========== +AT91C_MCI_PTCR EQU (0xFFFB4120) ;- (PDC_MCI) PDC Transfer Control Register +AT91C_MCI_TNPR EQU (0xFFFB4118) ;- (PDC_MCI) Transmit Next Pointer Register +AT91C_MCI_RNPR EQU (0xFFFB4110) ;- (PDC_MCI) Receive Next Pointer Register +AT91C_MCI_TPR EQU (0xFFFB4108) ;- (PDC_MCI) Transmit Pointer Register +AT91C_MCI_RPR EQU (0xFFFB4100) ;- (PDC_MCI) Receive Pointer Register +AT91C_MCI_PTSR EQU (0xFFFB4124) ;- (PDC_MCI) PDC Transfer Status Register +AT91C_MCI_TNCR EQU (0xFFFB411C) ;- (PDC_MCI) Transmit Next Counter Register +AT91C_MCI_RNCR EQU (0xFFFB4114) ;- (PDC_MCI) Receive Next Counter Register +AT91C_MCI_TCR EQU (0xFFFB410C) ;- (PDC_MCI) Transmit Counter Register +AT91C_MCI_RCR EQU (0xFFFB4104) ;- (PDC_MCI) Receive Counter Register +;- ========== Register definition for MCI peripheral ========== +AT91C_MCI_IDR EQU (0xFFFB4048) ;- (MCI) MCI Interrupt Disable Register +AT91C_MCI_SR EQU (0xFFFB4040) ;- (MCI) MCI Status Register +AT91C_MCI_RDR EQU (0xFFFB4030) ;- (MCI) MCI Receive Data Register +AT91C_MCI_RSPR EQU (0xFFFB4020) ;- (MCI) MCI Response Register +AT91C_MCI_ARGR EQU (0xFFFB4010) ;- (MCI) MCI Argument Register +AT91C_MCI_DTOR EQU (0xFFFB4008) ;- (MCI) MCI Data Timeout Register +AT91C_MCI_CR EQU (0xFFFB4000) ;- (MCI) MCI Control Register +AT91C_MCI_IMR EQU (0xFFFB404C) ;- (MCI) MCI Interrupt Mask Register +AT91C_MCI_IER EQU (0xFFFB4044) ;- (MCI) MCI Interrupt Enable Register +AT91C_MCI_TDR EQU (0xFFFB4034) ;- (MCI) MCI Transmit Data Register +AT91C_MCI_CMDR EQU (0xFFFB4014) ;- (MCI) MCI Command Register +AT91C_MCI_SDCR EQU (0xFFFB400C) ;- (MCI) MCI SD Card Register +AT91C_MCI_MR EQU (0xFFFB4004) ;- (MCI) MCI Mode Register +;- ========== Register definition for UDP peripheral ========== +AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register +AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register +AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register +AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register +AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register +AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register +AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register +AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register +AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register +AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register +AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register +;- ========== Register definition for TC5 peripheral ========== +AT91C_TC5_CMR EQU (0xFFFA4084) ;- (TC5) Channel Mode Register +AT91C_TC5_IDR EQU (0xFFFA40A8) ;- (TC5) Interrupt Disable Register +AT91C_TC5_SR EQU (0xFFFA40A0) ;- (TC5) Status Register +AT91C_TC5_RB EQU (0xFFFA4098) ;- (TC5) Register B +AT91C_TC5_CV EQU (0xFFFA4090) ;- (TC5) Counter Value +AT91C_TC5_CCR EQU (0xFFFA4080) ;- (TC5) Channel Control Register +AT91C_TC5_IMR EQU (0xFFFA40AC) ;- (TC5) Interrupt Mask Register +AT91C_TC5_IER EQU (0xFFFA40A4) ;- (TC5) Interrupt Enable Register +AT91C_TC5_RC EQU (0xFFFA409C) ;- (TC5) Register C +AT91C_TC5_RA EQU (0xFFFA4094) ;- (TC5) Register A +;- ========== Register definition for TC4 peripheral ========== +AT91C_TC4_IMR EQU (0xFFFA406C) ;- (TC4) Interrupt Mask Register +AT91C_TC4_IER EQU (0xFFFA4064) ;- (TC4) Interrupt Enable Register +AT91C_TC4_RC EQU (0xFFFA405C) ;- (TC4) Register C +AT91C_TC4_RA EQU (0xFFFA4054) ;- (TC4) Register A +AT91C_TC4_CMR EQU (0xFFFA4044) ;- (TC4) Channel Mode Register +AT91C_TC4_IDR EQU (0xFFFA4068) ;- (TC4) Interrupt Disable Register +AT91C_TC4_SR EQU (0xFFFA4060) ;- (TC4) Status Register +AT91C_TC4_RB EQU (0xFFFA4058) ;- (TC4) Register B +AT91C_TC4_CV EQU (0xFFFA4050) ;- (TC4) Counter Value +AT91C_TC4_CCR EQU (0xFFFA4040) ;- (TC4) Channel Control Register +;- ========== Register definition for TC3 peripheral ========== +AT91C_TC3_IMR EQU (0xFFFA402C) ;- (TC3) Interrupt Mask Register +AT91C_TC3_CV EQU (0xFFFA4010) ;- (TC3) Counter Value +AT91C_TC3_CCR EQU (0xFFFA4000) ;- (TC3) Channel Control Register +AT91C_TC3_IER EQU (0xFFFA4024) ;- (TC3) Interrupt Enable Register +AT91C_TC3_CMR EQU (0xFFFA4004) ;- (TC3) Channel Mode Register +AT91C_TC3_RA EQU (0xFFFA4014) ;- (TC3) Register A +AT91C_TC3_RC EQU (0xFFFA401C) ;- (TC3) Register C +AT91C_TC3_IDR EQU (0xFFFA4028) ;- (TC3) Interrupt Disable Register +AT91C_TC3_RB EQU (0xFFFA4018) ;- (TC3) Register B +AT91C_TC3_SR EQU (0xFFFA4020) ;- (TC3) Status Register +;- ========== Register definition for TCB1 peripheral ========== +AT91C_TCB1_BCR EQU (0xFFFA4140) ;- (TCB1) TC Block Control Register +AT91C_TCB1_BMR EQU (0xFFFA4144) ;- (TCB1) TC Block Mode Register +;- ========== Register definition for TC2 peripheral ========== +AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register +AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register +AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C +AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A +AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register +AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register +AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register +AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B +AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value +AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register +;- ========== Register definition for TC1 peripheral ========== +AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register +AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register +AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C +AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A +AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register +AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register +AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register +AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B +AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value +AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register +;- ========== Register definition for TC0 peripheral ========== +AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register +AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register +AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C +AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A +AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register +AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register +AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register +AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B +AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value +AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register +;- ========== Register definition for TCB0 peripheral ========== +AT91C_TCB0_BMR EQU (0xFFFA00C4) ;- (TCB0) TC Block Mode Register +AT91C_TCB0_BCR EQU (0xFFFA00C0) ;- (TCB0) TC Block Control Register +;- ========== Register definition for UHP peripheral ========== +AT91C_UHP_HcRhDescriptorA EQU (0x00300048) ;- (UHP) Root Hub characteristics A +AT91C_UHP_HcRhPortStatus EQU (0x00300054) ;- (UHP) Root Hub Port Status Register +AT91C_UHP_HcRhDescriptorB EQU (0x0030004C) ;- (UHP) Root Hub characteristics B +AT91C_UHP_HcControl EQU (0x00300004) ;- (UHP) Operating modes for the Host Controller +AT91C_UHP_HcInterruptStatus EQU (0x0030000C) ;- (UHP) Interrupt Status Register +AT91C_UHP_HcRhStatus EQU (0x00300050) ;- (UHP) Root Hub Status register +AT91C_UHP_HcRevision EQU (0x00300000) ;- (UHP) Revision +AT91C_UHP_HcCommandStatus EQU (0x00300008) ;- (UHP) Command & status Register +AT91C_UHP_HcInterruptEnable EQU (0x00300010) ;- (UHP) Interrupt Enable Register +AT91C_UHP_HcHCCA EQU (0x00300018) ;- (UHP) Pointer to the Host Controller Communication Area +AT91C_UHP_HcControlHeadED EQU (0x00300020) ;- (UHP) First Endpoint Descriptor of the Control list +AT91C_UHP_HcInterruptDisable EQU (0x00300014) ;- (UHP) Interrupt Disable Register +AT91C_UHP_HcPeriodCurrentED EQU (0x0030001C) ;- (UHP) Current Isochronous or Interrupt Endpoint Descriptor +AT91C_UHP_HcControlCurrentED EQU (0x00300024) ;- (UHP) Endpoint Control and Status Register +AT91C_UHP_HcBulkCurrentED EQU (0x0030002C) ;- (UHP) Current endpoint of the Bulk list +AT91C_UHP_HcFmInterval EQU (0x00300034) ;- (UHP) Bit time between 2 consecutive SOFs +AT91C_UHP_HcBulkHeadED EQU (0x00300028) ;- (UHP) First endpoint register of the Bulk list +AT91C_UHP_HcBulkDoneHead EQU (0x00300030) ;- (UHP) Last completed transfer descriptor +AT91C_UHP_HcFmRemaining EQU (0x00300038) ;- (UHP) Bit time remaining in the current Frame +AT91C_UHP_HcPeriodicStart EQU (0x00300040) ;- (UHP) Periodic Start +AT91C_UHP_HcLSThreshold EQU (0x00300044) ;- (UHP) LS Threshold +AT91C_UHP_HcFmNumber EQU (0x0030003C) ;- (UHP) Frame number +;- ========== Register definition for EMAC peripheral ========== +AT91C_EMAC_RSR EQU (0xFFFBC020) ;- (EMAC) Receive Status Register +AT91C_EMAC_MAN EQU (0xFFFBC034) ;- (EMAC) PHY Maintenance Register +AT91C_EMAC_HSH EQU (0xFFFBC090) ;- (EMAC) Hash Address High[63:32] +AT91C_EMAC_MCOL EQU (0xFFFBC048) ;- (EMAC) Multiple Collision Frame Register +AT91C_EMAC_IER EQU (0xFFFBC028) ;- (EMAC) Interrupt Enable Register +AT91C_EMAC_SA2H EQU (0xFFFBC0A4) ;- (EMAC) Specific Address 2 High, Last 2 bytes +AT91C_EMAC_HSL EQU (0xFFFBC094) ;- (EMAC) Hash Address Low[31:0] +AT91C_EMAC_LCOL EQU (0xFFFBC05C) ;- (EMAC) Late Collision Register +AT91C_EMAC_OK EQU (0xFFFBC04C) ;- (EMAC) Frames Received OK Register +AT91C_EMAC_CFG EQU (0xFFFBC004) ;- (EMAC) Network Configuration Register +AT91C_EMAC_SA3L EQU (0xFFFBC0A8) ;- (EMAC) Specific Address 3 Low, First 4 bytes +AT91C_EMAC_SEQE EQU (0xFFFBC050) ;- (EMAC) Frame Check Sequence Error Register +AT91C_EMAC_ECOL EQU (0xFFFBC060) ;- (EMAC) Excessive Collision Register +AT91C_EMAC_ELR EQU (0xFFFBC070) ;- (EMAC) Excessive Length Error Register +AT91C_EMAC_SR EQU (0xFFFBC008) ;- (EMAC) Network Status Register +AT91C_EMAC_RBQP EQU (0xFFFBC018) ;- (EMAC) Receive Buffer Queue Pointer +AT91C_EMAC_CSE EQU (0xFFFBC064) ;- (EMAC) Carrier Sense Error Register +AT91C_EMAC_RJB EQU (0xFFFBC074) ;- (EMAC) Receive Jabber Register +AT91C_EMAC_USF EQU (0xFFFBC078) ;- (EMAC) Undersize Frame Register +AT91C_EMAC_IDR EQU (0xFFFBC02C) ;- (EMAC) Interrupt Disable Register +AT91C_EMAC_SA1L EQU (0xFFFBC098) ;- (EMAC) Specific Address 1 Low, First 4 bytes +AT91C_EMAC_IMR EQU (0xFFFBC030) ;- (EMAC) Interrupt Mask Register +AT91C_EMAC_FRA EQU (0xFFFBC040) ;- (EMAC) Frames Transmitted OK Register +AT91C_EMAC_SA3H EQU (0xFFFBC0AC) ;- (EMAC) Specific Address 3 High, Last 2 bytes +AT91C_EMAC_SA1H EQU (0xFFFBC09C) ;- (EMAC) Specific Address 1 High, Last 2 bytes +AT91C_EMAC_SCOL EQU (0xFFFBC044) ;- (EMAC) Single Collision Frame Register +AT91C_EMAC_ALE EQU (0xFFFBC054) ;- (EMAC) Alignment Error Register +AT91C_EMAC_TAR EQU (0xFFFBC00C) ;- (EMAC) Transmit Address Register +AT91C_EMAC_SA4L EQU (0xFFFBC0B0) ;- (EMAC) Specific Address 4 Low, First 4 bytes +AT91C_EMAC_SA2L EQU (0xFFFBC0A0) ;- (EMAC) Specific Address 2 Low, First 4 bytes +AT91C_EMAC_TUE EQU (0xFFFBC068) ;- (EMAC) Transmit Underrun Error Register +AT91C_EMAC_DTE EQU (0xFFFBC058) ;- (EMAC) Deferred Transmission Frame Register +AT91C_EMAC_TCR EQU (0xFFFBC010) ;- (EMAC) Transmit Control Register +AT91C_EMAC_CTL EQU (0xFFFBC000) ;- (EMAC) Network Control Register +AT91C_EMAC_SA4H EQU (0xFFFBC0B4) ;- (EMAC) Specific Address 4 High, Last 2 bytesr +AT91C_EMAC_CDE EQU (0xFFFBC06C) ;- (EMAC) Code Error Register +AT91C_EMAC_SQEE EQU (0xFFFBC07C) ;- (EMAC) SQE Test Error Register +AT91C_EMAC_TSR EQU (0xFFFBC014) ;- (EMAC) Transmit Status Register +AT91C_EMAC_DRFC EQU (0xFFFBC080) ;- (EMAC) Discarded RX Frame Register +;- ========== Register definition for EBI peripheral ========== +AT91C_EBI_CFGR EQU (0xFFFFFF64) ;- (EBI) Configuration Register +AT91C_EBI_CSA EQU (0xFFFFFF60) ;- (EBI) Chip Select Assignment Register +;- ========== Register definition for SMC2 peripheral ========== +AT91C_SMC2_CSR EQU (0xFFFFFF70) ;- (SMC2) SMC2 Chip Select Register +;- ========== Register definition for SDRC peripheral ========== +AT91C_SDRC_IMR EQU (0xFFFFFFAC) ;- (SDRC) SDRAM Controller Interrupt Mask Register +AT91C_SDRC_IER EQU (0xFFFFFFA4) ;- (SDRC) SDRAM Controller Interrupt Enable Register +AT91C_SDRC_SRR EQU (0xFFFFFF9C) ;- (SDRC) SDRAM Controller Self Refresh Register +AT91C_SDRC_TR EQU (0xFFFFFF94) ;- (SDRC) SDRAM Controller Refresh Timer Register +AT91C_SDRC_ISR EQU (0xFFFFFFB0) ;- (SDRC) SDRAM Controller Interrupt Mask Register +AT91C_SDRC_IDR EQU (0xFFFFFFA8) ;- (SDRC) SDRAM Controller Interrupt Disable Register +AT91C_SDRC_LPR EQU (0xFFFFFFA0) ;- (SDRC) SDRAM Controller Low Power Register +AT91C_SDRC_CR EQU (0xFFFFFF98) ;- (SDRC) SDRAM Controller Configuration Register +AT91C_SDRC_MR EQU (0xFFFFFF90) ;- (SDRC) SDRAM Controller Mode Register +;- ========== Register definition for BFC peripheral ========== +AT91C_BFC_MR EQU (0xFFFFFFC0) ;- (BFC) BFC Mode Register + +;- ***************************************************************************** +;- PIO DEFINITIONS FOR AT91RM9200 +;- ***************************************************************************** +AT91C_PIO_PA0 EQU (1:SHL:0) ;- Pin Controlled by PA0 +AT91C_PA0_MISO EQU (AT91C_PIO_PA0) ;- SPI Master In Slave +AT91C_PA0_PCK3 EQU (AT91C_PIO_PA0) ;- PMC Programmable Clock Output 3 +AT91C_PIO_PA1 EQU (1:SHL:1) ;- Pin Controlled by PA1 +AT91C_PA1_MOSI EQU (AT91C_PIO_PA1) ;- SPI Master Out Slave +AT91C_PA1_PCK0 EQU (AT91C_PIO_PA1) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PA10 EQU (1:SHL:10) ;- Pin Controlled by PA10 +AT91C_PA10_ETX1 EQU (AT91C_PIO_PA10) ;- Ethernet MAC Transmit Data 1 +AT91C_PA10_MCDB1 EQU (AT91C_PIO_PA10) ;- Multimedia Card B Data 1 +AT91C_PIO_PA11 EQU (1:SHL:11) ;- Pin Controlled by PA11 +AT91C_PA11_ECRS_ECRSDV EQU (AT91C_PIO_PA11) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +AT91C_PA11_MCDB2 EQU (AT91C_PIO_PA11) ;- Multimedia Card B Data 2 +AT91C_PIO_PA12 EQU (1:SHL:12) ;- Pin Controlled by PA12 +AT91C_PA12_ERX0 EQU (AT91C_PIO_PA12) ;- Ethernet MAC Receive Data 0 +AT91C_PA12_MCDB3 EQU (AT91C_PIO_PA12) ;- Multimedia Card B Data 3 +AT91C_PIO_PA13 EQU (1:SHL:13) ;- Pin Controlled by PA13 +AT91C_PA13_ERX1 EQU (AT91C_PIO_PA13) ;- Ethernet MAC Receive Data 1 +AT91C_PA13_TCLK0 EQU (AT91C_PIO_PA13) ;- Timer Counter 0 external clock input +AT91C_PIO_PA14 EQU (1:SHL:14) ;- Pin Controlled by PA14 +AT91C_PA14_ERXER EQU (AT91C_PIO_PA14) ;- Ethernet MAC Receive Error +AT91C_PA14_TCLK1 EQU (AT91C_PIO_PA14) ;- Timer Counter 1 external clock input +AT91C_PIO_PA15 EQU (1:SHL:15) ;- Pin Controlled by PA15 +AT91C_PA15_EMDC EQU (AT91C_PIO_PA15) ;- Ethernet MAC Management Data Clock +AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input +AT91C_PIO_PA16 EQU (1:SHL:16) ;- Pin Controlled by PA16 +AT91C_PA16_EMDIO EQU (AT91C_PIO_PA16) ;- Ethernet MAC Management Data Input/Output +AT91C_PA16_IRQ6 EQU (AT91C_PIO_PA16) ;- AIC Interrupt input 6 +AT91C_PIO_PA17 EQU (1:SHL:17) ;- Pin Controlled by PA17 +AT91C_PA17_TXD0 EQU (AT91C_PIO_PA17) ;- USART 0 Transmit Data +AT91C_PA17_TIOA0 EQU (AT91C_PIO_PA17) ;- Timer Counter 0 Multipurpose Timer I/O Pin A +AT91C_PIO_PA18 EQU (1:SHL:18) ;- Pin Controlled by PA18 +AT91C_PA18_RXD0 EQU (AT91C_PIO_PA18) ;- USART 0 Receive Data +AT91C_PA18_TIOB0 EQU (AT91C_PIO_PA18) ;- Timer Counter 0 Multipurpose Timer I/O Pin B +AT91C_PIO_PA19 EQU (1:SHL:19) ;- Pin Controlled by PA19 +AT91C_PA19_SCK0 EQU (AT91C_PIO_PA19) ;- USART 0 Serial Clock +AT91C_PA19_TIOA1 EQU (AT91C_PIO_PA19) ;- Timer Counter 1 Multipurpose Timer I/O Pin A +AT91C_PIO_PA2 EQU (1:SHL:2) ;- Pin Controlled by PA2 +AT91C_PA2_SPCK EQU (AT91C_PIO_PA2) ;- SPI Serial Clock +AT91C_PA2_IRQ4 EQU (AT91C_PIO_PA2) ;- AIC Interrupt Input 4 +AT91C_PIO_PA20 EQU (1:SHL:20) ;- Pin Controlled by PA20 +AT91C_PA20_CTS0 EQU (AT91C_PIO_PA20) ;- USART 0 Clear To Send +AT91C_PA20_TIOB1 EQU (AT91C_PIO_PA20) ;- Timer Counter 1 Multipurpose Timer I/O Pin B +AT91C_PIO_PA21 EQU (1:SHL:21) ;- Pin Controlled by PA21 +AT91C_PA21_RTS0 EQU (AT91C_PIO_PA21) ;- Usart 0 Ready To Send +AT91C_PA21_TIOA2 EQU (AT91C_PIO_PA21) ;- Timer Counter 2 Multipurpose Timer I/O Pin A +AT91C_PIO_PA22 EQU (1:SHL:22) ;- Pin Controlled by PA22 +AT91C_PA22_RXD2 EQU (AT91C_PIO_PA22) ;- USART 2 Receive Data +AT91C_PA22_TIOB2 EQU (AT91C_PIO_PA22) ;- Timer Counter 2 Multipurpose Timer I/O Pin B +AT91C_PIO_PA23 EQU (1:SHL:23) ;- Pin Controlled by PA23 +AT91C_PA23_TXD2 EQU (AT91C_PIO_PA23) ;- USART 2 Transmit Data +AT91C_PA23_IRQ3 EQU (AT91C_PIO_PA23) ;- Interrupt input 3 +AT91C_PIO_PA24 EQU (1:SHL:24) ;- Pin Controlled by PA24 +AT91C_PA24_SCK2 EQU (AT91C_PIO_PA24) ;- USART2 Serial Clock +AT91C_PA24_PCK1 EQU (AT91C_PIO_PA24) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PA25 EQU (1:SHL:25) ;- Pin Controlled by PA25 +AT91C_PA25_TWD EQU (AT91C_PIO_PA25) ;- TWI Two-wire Serial Data +AT91C_PA25_IRQ2 EQU (AT91C_PIO_PA25) ;- Interrupt input 2 +AT91C_PIO_PA26 EQU (1:SHL:26) ;- Pin Controlled by PA26 +AT91C_PA26_TWCK EQU (AT91C_PIO_PA26) ;- TWI Two-wire Serial Clock +AT91C_PA26_IRQ1 EQU (AT91C_PIO_PA26) ;- Interrupt input 1 +AT91C_PIO_PA27 EQU (1:SHL:27) ;- Pin Controlled by PA27 +AT91C_PA27_MCCK EQU (AT91C_PIO_PA27) ;- Multimedia Card Clock +AT91C_PA27_TCLK3 EQU (AT91C_PIO_PA27) ;- Timer Counter 3 External Clock Input +AT91C_PIO_PA28 EQU (1:SHL:28) ;- Pin Controlled by PA28 +AT91C_PA28_MCCDA EQU (AT91C_PIO_PA28) ;- Multimedia Card A Command +AT91C_PA28_TCLK4 EQU (AT91C_PIO_PA28) ;- Timer Counter 4 external Clock Input +AT91C_PIO_PA29 EQU (1:SHL:29) ;- Pin Controlled by PA29 +AT91C_PA29_MCDA0 EQU (AT91C_PIO_PA29) ;- Multimedia Card A Data 0 +AT91C_PA29_TCLK5 EQU (AT91C_PIO_PA29) ;- Timer Counter 5 external clock input +AT91C_PIO_PA3 EQU (1:SHL:3) ;- Pin Controlled by PA3 +AT91C_PA3_NPCS0 EQU (AT91C_PIO_PA3) ;- SPI Peripheral Chip Select 0 +AT91C_PA3_IRQ5 EQU (AT91C_PIO_PA3) ;- AIC Interrupt Input 5 +AT91C_PIO_PA30 EQU (1:SHL:30) ;- Pin Controlled by PA30 +AT91C_PA30_DRXD EQU (AT91C_PIO_PA30) ;- DBGU Debug Receive Data +AT91C_PA30_CTS2 EQU (AT91C_PIO_PA30) ;- Usart 2 Clear To Send +AT91C_PIO_PA31 EQU (1:SHL:31) ;- Pin Controlled by PA31 +AT91C_PA31_DTXD EQU (AT91C_PIO_PA31) ;- DBGU Debug Transmit Data +AT91C_PA31_RTS2 EQU (AT91C_PIO_PA31) ;- USART 2 Ready To Send +AT91C_PIO_PA4 EQU (1:SHL:4) ;- Pin Controlled by PA4 +AT91C_PA4_NPCS1 EQU (AT91C_PIO_PA4) ;- SPI Peripheral Chip Select 1 +AT91C_PA4_PCK1 EQU (AT91C_PIO_PA4) ;- PMC Programmable Clock Output 1 +AT91C_PIO_PA5 EQU (1:SHL:5) ;- Pin Controlled by PA5 +AT91C_PA5_NPCS2 EQU (AT91C_PIO_PA5) ;- SPI Peripheral Chip Select 2 +AT91C_PA5_TXD3 EQU (AT91C_PIO_PA5) ;- USART 3 Transmit Data +AT91C_PIO_PA6 EQU (1:SHL:6) ;- Pin Controlled by PA6 +AT91C_PA6_NPCS3 EQU (AT91C_PIO_PA6) ;- SPI Peripheral Chip Select 3 +AT91C_PA6_RXD3 EQU (AT91C_PIO_PA6) ;- USART 3 Receive Data +AT91C_PIO_PA7 EQU (1:SHL:7) ;- Pin Controlled by PA7 +AT91C_PA7_ETXCK_EREFCK EQU (AT91C_PIO_PA7) ;- Ethernet MAC Transmit Clock/Reference Clock +AT91C_PA7_PCK2 EQU (AT91C_PIO_PA7) ;- PMC Programmable Clock 2 +AT91C_PIO_PA8 EQU (1:SHL:8) ;- Pin Controlled by PA8 +AT91C_PA8_ETXEN EQU (AT91C_PIO_PA8) ;- Ethernet MAC Transmit Enable +AT91C_PA8_MCCDB EQU (AT91C_PIO_PA8) ;- Multimedia Card B Command +AT91C_PIO_PA9 EQU (1:SHL:9) ;- Pin Controlled by PA9 +AT91C_PA9_ETX0 EQU (AT91C_PIO_PA9) ;- Ethernet MAC Transmit Data 0 +AT91C_PA9_MCDB0 EQU (AT91C_PIO_PA9) ;- Multimedia Card B Data 0 +AT91C_PIO_PB0 EQU (1:SHL:0) ;- Pin Controlled by PB0 +AT91C_PB0_TF0 EQU (AT91C_PIO_PB0) ;- SSC Transmit Frame Sync 0 +AT91C_PB0_TIOB3 EQU (AT91C_PIO_PB0) ;- Timer Counter 3 Multipurpose Timer I/O Pin B +AT91C_PIO_PB1 EQU (1:SHL:1) ;- Pin Controlled by PB1 +AT91C_PB1_TK0 EQU (AT91C_PIO_PB1) ;- SSC Transmit Clock 0 +AT91C_PB1_CTS3 EQU (AT91C_PIO_PB1) ;- USART 3 Clear To Send +AT91C_PIO_PB10 EQU (1:SHL:10) ;- Pin Controlled by PB10 +AT91C_PB10_RK1 EQU (AT91C_PIO_PB10) ;- SSC Receive Clock 1 +AT91C_PB10_TIOA5 EQU (AT91C_PIO_PB10) ;- Timer Counter 5 Multipurpose Timer I/O Pin A +AT91C_PIO_PB11 EQU (1:SHL:11) ;- Pin Controlled by PB11 +AT91C_PB11_RF1 EQU (AT91C_PIO_PB11) ;- SSC Receive Frame Sync 1 +AT91C_PB11_TIOB5 EQU (AT91C_PIO_PB11) ;- Timer Counter 5 Multipurpose Timer I/O Pin B +AT91C_PIO_PB12 EQU (1:SHL:12) ;- Pin Controlled by PB12 +AT91C_PB12_TF2 EQU (AT91C_PIO_PB12) ;- SSC Transmit Frame Sync 2 +AT91C_PB12_ETX2 EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmit Data 2 +AT91C_PIO_PB13 EQU (1:SHL:13) ;- Pin Controlled by PB13 +AT91C_PB13_TK2 EQU (AT91C_PIO_PB13) ;- SSC Transmit Clock 2 +AT91C_PB13_ETX3 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Transmit Data 3 +AT91C_PIO_PB14 EQU (1:SHL:14) ;- Pin Controlled by PB14 +AT91C_PB14_TD2 EQU (AT91C_PIO_PB14) ;- SSC Transmit Data 2 +AT91C_PB14_ETXER EQU (AT91C_PIO_PB14) ;- Ethernet MAC Transmikt Coding Error +AT91C_PIO_PB15 EQU (1:SHL:15) ;- Pin Controlled by PB15 +AT91C_PB15_RD2 EQU (AT91C_PIO_PB15) ;- SSC Receive Data 2 +AT91C_PB15_ERX2 EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data 2 +AT91C_PIO_PB16 EQU (1:SHL:16) ;- Pin Controlled by PB16 +AT91C_PB16_RK2 EQU (AT91C_PIO_PB16) ;- SSC Receive Clock 2 +AT91C_PB16_ERX3 EQU (AT91C_PIO_PB16) ;- Ethernet MAC Receive Data 3 +AT91C_PIO_PB17 EQU (1:SHL:17) ;- Pin Controlled by PB17 +AT91C_PB17_RF2 EQU (AT91C_PIO_PB17) ;- SSC Receive Frame Sync 2 +AT91C_PB17_ERXDV EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Data Valid +AT91C_PIO_PB18 EQU (1:SHL:18) ;- Pin Controlled by PB18 +AT91C_PB18_RI1 EQU (AT91C_PIO_PB18) ;- USART 1 Ring Indicator +AT91C_PB18_ECOL EQU (AT91C_PIO_PB18) ;- Ethernet MAC Collision Detected +AT91C_PIO_PB19 EQU (1:SHL:19) ;- Pin Controlled by PB19 +AT91C_PB19_DTR1 EQU (AT91C_PIO_PB19) ;- USART 1 Data Terminal ready +AT91C_PB19_ERXCK EQU (AT91C_PIO_PB19) ;- Ethernet MAC Receive Clock +AT91C_PIO_PB2 EQU (1:SHL:2) ;- Pin Controlled by PB2 +AT91C_PB2_TD0 EQU (AT91C_PIO_PB2) ;- SSC Transmit data +AT91C_PB2_SCK3 EQU (AT91C_PIO_PB2) ;- USART 3 Serial Clock +AT91C_PIO_PB20 EQU (1:SHL:20) ;- Pin Controlled by PB20 +AT91C_PB20_TXD1 EQU (AT91C_PIO_PB20) ;- USART 1 Transmit Data +AT91C_PIO_PB21 EQU (1:SHL:21) ;- Pin Controlled by PB21 +AT91C_PB21_RXD1 EQU (AT91C_PIO_PB21) ;- USART 1 Receive Data +AT91C_PIO_PB22 EQU (1:SHL:22) ;- Pin Controlled by PB22 +AT91C_PB22_SCK1 EQU (AT91C_PIO_PB22) ;- USART1 Serial Clock +AT91C_PIO_PB23 EQU (1:SHL:23) ;- Pin Controlled by PB23 +AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect +AT91C_PIO_PB24 EQU (1:SHL:24) ;- Pin Controlled by PB24 +AT91C_PB24_CTS1 EQU (AT91C_PIO_PB24) ;- USART 1 Clear To Send +AT91C_PIO_PB25 EQU (1:SHL:25) ;- Pin Controlled by PB25 +AT91C_PB25_DSR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Set ready +AT91C_PB25_EF100 EQU (AT91C_PIO_PB25) ;- Ethernet MAC Force 100 Mbits/sec +AT91C_PIO_PB26 EQU (1:SHL:26) ;- Pin Controlled by PB26 +AT91C_PB26_RTS1 EQU (AT91C_PIO_PB26) ;- Usart 0 Ready To Send +AT91C_PIO_PB27 EQU (1:SHL:27) ;- Pin Controlled by PB27 +AT91C_PB27_PCK0 EQU (AT91C_PIO_PB27) ;- PMC Programmable Clock Output 0 +AT91C_PIO_PB28 EQU (1:SHL:28) ;- Pin Controlled by PB28 +AT91C_PB28_FIQ EQU (AT91C_PIO_PB28) ;- AIC Fast Interrupt Input +AT91C_PIO_PB29 EQU (1:SHL:29) ;- Pin Controlled by PB29 +AT91C_PB29_IRQ0 EQU (AT91C_PIO_PB29) ;- Interrupt input 0 +AT91C_PIO_PB3 EQU (1:SHL:3) ;- Pin Controlled by PB3 +AT91C_PB3_RD0 EQU (AT91C_PIO_PB3) ;- SSC Receive Data +AT91C_PB3_MCDA1 EQU (AT91C_PIO_PB3) ;- Multimedia Card A Data 1 +AT91C_PIO_PB4 EQU (1:SHL:4) ;- Pin Controlled by PB4 +AT91C_PB4_RK0 EQU (AT91C_PIO_PB4) ;- SSC Receive Clock +AT91C_PB4_MCDA2 EQU (AT91C_PIO_PB4) ;- Multimedia Card A Data 2 +AT91C_PIO_PB5 EQU (1:SHL:5) ;- Pin Controlled by PB5 +AT91C_PB5_RF0 EQU (AT91C_PIO_PB5) ;- SSC Receive Frame Sync 0 +AT91C_PB5_MCDA3 EQU (AT91C_PIO_PB5) ;- Multimedia Card A Data 3 +AT91C_PIO_PB6 EQU (1:SHL:6) ;- Pin Controlled by PB6 +AT91C_PB6_TF1 EQU (AT91C_PIO_PB6) ;- SSC Transmit Frame Sync 1 +AT91C_PB6_TIOA3 EQU (AT91C_PIO_PB6) ;- Timer Counter 4 Multipurpose Timer I/O Pin A +AT91C_PIO_PB7 EQU (1:SHL:7) ;- Pin Controlled by PB7 +AT91C_PB7_TK1 EQU (AT91C_PIO_PB7) ;- SSC Transmit Clock 1 +AT91C_PB7_TIOB3 EQU (AT91C_PIO_PB7) ;- Timer Counter 3 Multipurpose Timer I/O Pin B +AT91C_PIO_PB8 EQU (1:SHL:8) ;- Pin Controlled by PB8 +AT91C_PB8_TD1 EQU (AT91C_PIO_PB8) ;- SSC Transmit Data 1 +AT91C_PB8_TIOA4 EQU (AT91C_PIO_PB8) ;- Timer Counter 4 Multipurpose Timer I/O Pin A +AT91C_PIO_PB9 EQU (1:SHL:9) ;- Pin Controlled by PB9 +AT91C_PB9_RD1 EQU (AT91C_PIO_PB9) ;- SSC Receive Data 1 +AT91C_PB9_TIOB4 EQU (AT91C_PIO_PB9) ;- Timer Counter 4 Multipurpose Timer I/O Pin B +AT91C_PIO_PC0 EQU (1:SHL:0) ;- Pin Controlled by PC0 +AT91C_PC0_BFCK EQU (AT91C_PIO_PC0) ;- Burst Flash Clock +AT91C_PIO_PC1 EQU (1:SHL:1) ;- Pin Controlled by PC1 +AT91C_PC1_BFRDY_SMOE EQU (AT91C_PIO_PC1) ;- Burst Flash Ready +AT91C_PIO_PC10 EQU (1:SHL:10) ;- Pin Controlled by PC10 +AT91C_PC10_NCS4_CFCS EQU (AT91C_PIO_PC10) ;- Compact Flash Chip Select +AT91C_PIO_PC11 EQU (1:SHL:11) ;- Pin Controlled by PC11 +AT91C_PC11_NCS5_CFCE1 EQU (AT91C_PIO_PC11) ;- Chip Select 5 / Compact Flash Chip Enable 1 +AT91C_PIO_PC12 EQU (1:SHL:12) ;- Pin Controlled by PC12 +AT91C_PC12_NCS6_CFCE2 EQU (AT91C_PIO_PC12) ;- Chip Select 6 / Compact Flash Chip Enable 2 +AT91C_PIO_PC13 EQU (1:SHL:13) ;- Pin Controlled by PC13 +AT91C_PC13_NCS7 EQU (AT91C_PIO_PC13) ;- Chip Select 7 +AT91C_PIO_PC14 EQU (1:SHL:14) ;- Pin Controlled by PC14 +AT91C_PIO_PC15 EQU (1:SHL:15) ;- Pin Controlled by PC15 +AT91C_PIO_PC16 EQU (1:SHL:16) ;- Pin Controlled by PC16 +AT91C_PC16_D16 EQU (AT91C_PIO_PC16) ;- Data Bus [16] +AT91C_PIO_PC17 EQU (1:SHL:17) ;- Pin Controlled by PC17 +AT91C_PC17_D17 EQU (AT91C_PIO_PC17) ;- Data Bus [17] +AT91C_PIO_PC18 EQU (1:SHL:18) ;- Pin Controlled by PC18 +AT91C_PC18_D18 EQU (AT91C_PIO_PC18) ;- Data Bus [18] +AT91C_PIO_PC19 EQU (1:SHL:19) ;- Pin Controlled by PC19 +AT91C_PC19_D19 EQU (AT91C_PIO_PC19) ;- Data Bus [19] +AT91C_PIO_PC2 EQU (1:SHL:2) ;- Pin Controlled by PC2 +AT91C_PC2_BFAVD EQU (AT91C_PIO_PC2) ;- Burst Flash Address Valid +AT91C_PIO_PC20 EQU (1:SHL:20) ;- Pin Controlled by PC20 +AT91C_PC20_D20 EQU (AT91C_PIO_PC20) ;- Data Bus [20] +AT91C_PIO_PC21 EQU (1:SHL:21) ;- Pin Controlled by PC21 +AT91C_PC21_D21 EQU (AT91C_PIO_PC21) ;- Data Bus [21] +AT91C_PIO_PC22 EQU (1:SHL:22) ;- Pin Controlled by PC22 +AT91C_PC22_D22 EQU (AT91C_PIO_PC22) ;- Data Bus [22] +AT91C_PIO_PC23 EQU (1:SHL:23) ;- Pin Controlled by PC23 +AT91C_PC23_D23 EQU (AT91C_PIO_PC23) ;- Data Bus [23] +AT91C_PIO_PC24 EQU (1:SHL:24) ;- Pin Controlled by PC24 +AT91C_PC24_D24 EQU (AT91C_PIO_PC24) ;- Data Bus [24] +AT91C_PIO_PC25 EQU (1:SHL:25) ;- Pin Controlled by PC25 +AT91C_PC25_D25 EQU (AT91C_PIO_PC25) ;- Data Bus [25] +AT91C_PIO_PC26 EQU (1:SHL:26) ;- Pin Controlled by PC26 +AT91C_PC26_D26 EQU (AT91C_PIO_PC26) ;- Data Bus [26] +AT91C_PIO_PC27 EQU (1:SHL:27) ;- Pin Controlled by PC27 +AT91C_PC27_D27 EQU (AT91C_PIO_PC27) ;- Data Bus [27] +AT91C_PIO_PC28 EQU (1:SHL:28) ;- Pin Controlled by PC28 +AT91C_PC28_D28 EQU (AT91C_PIO_PC28) ;- Data Bus [28] +AT91C_PIO_PC29 EQU (1:SHL:29) ;- Pin Controlled by PC29 +AT91C_PC29_D29 EQU (AT91C_PIO_PC29) ;- Data Bus [29] +AT91C_PIO_PC3 EQU (1:SHL:3) ;- Pin Controlled by PC3 +AT91C_PC3_BFBAA_SMWE EQU (AT91C_PIO_PC3) ;- Burst Flash Address Advance / SmartMedia Write Enable +AT91C_PIO_PC30 EQU (1:SHL:30) ;- Pin Controlled by PC30 +AT91C_PC30_D30 EQU (AT91C_PIO_PC30) ;- Data Bus [30] +AT91C_PIO_PC31 EQU (1:SHL:31) ;- Pin Controlled by PC31 +AT91C_PC31_D31 EQU (AT91C_PIO_PC31) ;- Data Bus [31] +AT91C_PIO_PC4 EQU (1:SHL:4) ;- Pin Controlled by PC4 +AT91C_PC4_BFOE EQU (AT91C_PIO_PC4) ;- Burst Flash Output Enable +AT91C_PIO_PC5 EQU (1:SHL:5) ;- Pin Controlled by PC5 +AT91C_PC5_BFWE EQU (AT91C_PIO_PC5) ;- Burst Flash Write Enable +AT91C_PIO_PC6 EQU (1:SHL:6) ;- Pin Controlled by PC6 +AT91C_PC6_NWAIT EQU (AT91C_PIO_PC6) ;- NWAIT +AT91C_PIO_PC7 EQU (1:SHL:7) ;- Pin Controlled by PC7 +AT91C_PC7_A23 EQU (AT91C_PIO_PC7) ;- Address Bus[23] +AT91C_PIO_PC8 EQU (1:SHL:8) ;- Pin Controlled by PC8 +AT91C_PC8_A24 EQU (AT91C_PIO_PC8) ;- Address Bus[24] +AT91C_PIO_PC9 EQU (1:SHL:9) ;- Pin Controlled by PC9 +AT91C_PC9_A25_CFRNW EQU (AT91C_PIO_PC9) ;- Address Bus[25] / Compact Flash Read Not Write +AT91C_PIO_PD0 EQU (1:SHL:0) ;- Pin Controlled by PD0 +AT91C_PD0_ETX0 EQU (AT91C_PIO_PD0) ;- Ethernet MAC Transmit Data 0 +AT91C_PIO_PD1 EQU (1:SHL:1) ;- Pin Controlled by PD1 +AT91C_PD1_ETX1 EQU (AT91C_PIO_PD1) ;- Ethernet MAC Transmit Data 1 +AT91C_PIO_PD10 EQU (1:SHL:10) ;- Pin Controlled by PD10 +AT91C_PD10_PCK3 EQU (AT91C_PIO_PD10) ;- PMC Programmable Clock Output 3 +AT91C_PD10_TPS1 EQU (AT91C_PIO_PD10) ;- ETM ARM9 pipeline status 1 +AT91C_PIO_PD11 EQU (1:SHL:11) ;- Pin Controlled by PD11 +AT91C_PD11_ EQU (AT91C_PIO_PD11) ;- +AT91C_PD11_TPS2 EQU (AT91C_PIO_PD11) ;- ETM ARM9 pipeline status 2 +AT91C_PIO_PD12 EQU (1:SHL:12) ;- Pin Controlled by PD12 +AT91C_PD12_ EQU (AT91C_PIO_PD12) ;- +AT91C_PD12_TPK0 EQU (AT91C_PIO_PD12) ;- ETM Trace Packet 0 +AT91C_PIO_PD13 EQU (1:SHL:13) ;- Pin Controlled by PD13 +AT91C_PD13_ EQU (AT91C_PIO_PD13) ;- +AT91C_PD13_TPK1 EQU (AT91C_PIO_PD13) ;- ETM Trace Packet 1 +AT91C_PIO_PD14 EQU (1:SHL:14) ;- Pin Controlled by PD14 +AT91C_PD14_ EQU (AT91C_PIO_PD14) ;- +AT91C_PD14_TPK2 EQU (AT91C_PIO_PD14) ;- ETM Trace Packet 2 +AT91C_PIO_PD15 EQU (1:SHL:15) ;- Pin Controlled by PD15 +AT91C_PD15_TD0 EQU (AT91C_PIO_PD15) ;- SSC Transmit data +AT91C_PD15_TPK3 EQU (AT91C_PIO_PD15) ;- ETM Trace Packet 3 +AT91C_PIO_PD16 EQU (1:SHL:16) ;- Pin Controlled by PD16 +AT91C_PD16_TD1 EQU (AT91C_PIO_PD16) ;- SSC Transmit Data 1 +AT91C_PD16_TPK4 EQU (AT91C_PIO_PD16) ;- ETM Trace Packet 4 +AT91C_PIO_PD17 EQU (1:SHL:17) ;- Pin Controlled by PD17 +AT91C_PD17_TD2 EQU (AT91C_PIO_PD17) ;- SSC Transmit Data 2 +AT91C_PD17_TPK5 EQU (AT91C_PIO_PD17) ;- ETM Trace Packet 5 +AT91C_PIO_PD18 EQU (1:SHL:18) ;- Pin Controlled by PD18 +AT91C_PD18_NPCS1 EQU (AT91C_PIO_PD18) ;- SPI Peripheral Chip Select 1 +AT91C_PD18_TPK6 EQU (AT91C_PIO_PD18) ;- ETM Trace Packet 6 +AT91C_PIO_PD19 EQU (1:SHL:19) ;- Pin Controlled by PD19 +AT91C_PD19_NPCS2 EQU (AT91C_PIO_PD19) ;- SPI Peripheral Chip Select 2 +AT91C_PD19_TPK7 EQU (AT91C_PIO_PD19) ;- ETM Trace Packet 7 +AT91C_PIO_PD2 EQU (1:SHL:2) ;- Pin Controlled by PD2 +AT91C_PD2_ETX2 EQU (AT91C_PIO_PD2) ;- Ethernet MAC Transmit Data 2 +AT91C_PIO_PD20 EQU (1:SHL:20) ;- Pin Controlled by PD20 +AT91C_PD20_NPCS3 EQU (AT91C_PIO_PD20) ;- SPI Peripheral Chip Select 3 +AT91C_PD20_TPK8 EQU (AT91C_PIO_PD20) ;- ETM Trace Packet 8 +AT91C_PIO_PD21 EQU (1:SHL:21) ;- Pin Controlled by PD21 +AT91C_PD21_RTS0 EQU (AT91C_PIO_PD21) ;- Usart 0 Ready To Send +AT91C_PD21_TPK9 EQU (AT91C_PIO_PD21) ;- ETM Trace Packet 9 +AT91C_PIO_PD22 EQU (1:SHL:22) ;- Pin Controlled by PD22 +AT91C_PD22_RTS1 EQU (AT91C_PIO_PD22) ;- Usart 0 Ready To Send +AT91C_PD22_TPK10 EQU (AT91C_PIO_PD22) ;- ETM Trace Packet 10 +AT91C_PIO_PD23 EQU (1:SHL:23) ;- Pin Controlled by PD23 +AT91C_PD23_RTS2 EQU (AT91C_PIO_PD23) ;- USART 2 Ready To Send +AT91C_PD23_TPK11 EQU (AT91C_PIO_PD23) ;- ETM Trace Packet 11 +AT91C_PIO_PD24 EQU (1:SHL:24) ;- Pin Controlled by PD24 +AT91C_PD24_RTS3 EQU (AT91C_PIO_PD24) ;- USART 3 Ready To Send +AT91C_PD24_TPK12 EQU (AT91C_PIO_PD24) ;- ETM Trace Packet 12 +AT91C_PIO_PD25 EQU (1:SHL:25) ;- Pin Controlled by PD25 +AT91C_PD25_DTR1 EQU (AT91C_PIO_PD25) ;- USART 1 Data Terminal ready +AT91C_PD25_TPK13 EQU (AT91C_PIO_PD25) ;- ETM Trace Packet 13 +AT91C_PIO_PD26 EQU (1:SHL:26) ;- Pin Controlled by PD26 +AT91C_PD26_TPK14 EQU (AT91C_PIO_PD26) ;- ETM Trace Packet 14 +AT91C_PIO_PD27 EQU (1:SHL:27) ;- Pin Controlled by PD27 +AT91C_PD27_TPK15 EQU (AT91C_PIO_PD27) ;- ETM Trace Packet 15 +AT91C_PIO_PD3 EQU (1:SHL:3) ;- Pin Controlled by PD3 +AT91C_PD3_ETX3 EQU (AT91C_PIO_PD3) ;- Ethernet MAC Transmit Data 3 +AT91C_PIO_PD4 EQU (1:SHL:4) ;- Pin Controlled by PD4 +AT91C_PD4_ETXEN EQU (AT91C_PIO_PD4) ;- Ethernet MAC Transmit Enable +AT91C_PIO_PD5 EQU (1:SHL:5) ;- Pin Controlled by PD5 +AT91C_PD5_ETXER EQU (AT91C_PIO_PD5) ;- Ethernet MAC Transmikt Coding Error +AT91C_PIO_PD6 EQU (1:SHL:6) ;- Pin Controlled by PD6 +AT91C_PD6_DTXD EQU (AT91C_PIO_PD6) ;- DBGU Debug Transmit Data +AT91C_PIO_PD7 EQU (1:SHL:7) ;- Pin Controlled by PD7 +AT91C_PD7_PCK0 EQU (AT91C_PIO_PD7) ;- PMC Programmable Clock Output 0 +AT91C_PD7_TSYNC EQU (AT91C_PIO_PD7) ;- ETM Synchronization signal +AT91C_PIO_PD8 EQU (1:SHL:8) ;- Pin Controlled by PD8 +AT91C_PD8_PCK1 EQU (AT91C_PIO_PD8) ;- PMC Programmable Clock Output 1 +AT91C_PD8_TCLK EQU (AT91C_PIO_PD8) ;- ETM Trace Clock signal +AT91C_PIO_PD9 EQU (1:SHL:9) ;- Pin Controlled by PD9 +AT91C_PD9_PCK2 EQU (AT91C_PIO_PD9) ;- PMC Programmable Clock 2 +AT91C_PD9_TPS0 EQU (AT91C_PIO_PD9) ;- ETM ARM9 pipeline status 0 + +;- ***************************************************************************** +;- PERIPHERAL ID DEFINITIONS FOR AT91RM9200 +;- ***************************************************************************** +AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) +AT91C_ID_SYS EQU ( 1) ;- System Peripheral +AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A +AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B +AT91C_ID_PIOC EQU ( 4) ;- Parallel IO Controller C +AT91C_ID_PIOD EQU ( 5) ;- Parallel IO Controller D +AT91C_ID_US0 EQU ( 6) ;- USART 0 +AT91C_ID_US1 EQU ( 7) ;- USART 1 +AT91C_ID_US2 EQU ( 8) ;- USART 2 +AT91C_ID_US3 EQU ( 9) ;- USART 3 +AT91C_ID_MCI EQU (10) ;- Multimedia Card Interface +AT91C_ID_UDP EQU (11) ;- USB Device Port +AT91C_ID_TWI EQU (12) ;- Two-Wire Interface +AT91C_ID_SPI EQU (13) ;- Serial Peripheral Interface +AT91C_ID_SSC0 EQU (14) ;- Serial Synchronous Controller 0 +AT91C_ID_SSC1 EQU (15) ;- Serial Synchronous Controller 1 +AT91C_ID_SSC2 EQU (16) ;- Serial Synchronous Controller 2 +AT91C_ID_TC0 EQU (17) ;- Timer Counter 0 +AT91C_ID_TC1 EQU (18) ;- Timer Counter 1 +AT91C_ID_TC2 EQU (19) ;- Timer Counter 2 +AT91C_ID_TC3 EQU (20) ;- Timer Counter 3 +AT91C_ID_TC4 EQU (21) ;- Timer Counter 4 +AT91C_ID_TC5 EQU (22) ;- Timer Counter 5 +AT91C_ID_UHP EQU (23) ;- USB Host port +AT91C_ID_EMAC EQU (24) ;- Ethernet MAC +AT91C_ID_IRQ0 EQU (25) ;- Advanced Interrupt Controller (IRQ0) +AT91C_ID_IRQ1 EQU (26) ;- Advanced Interrupt Controller (IRQ1) +AT91C_ID_IRQ2 EQU (27) ;- Advanced Interrupt Controller (IRQ2) +AT91C_ID_IRQ3 EQU (28) ;- Advanced Interrupt Controller (IRQ3) +AT91C_ID_IRQ4 EQU (29) ;- Advanced Interrupt Controller (IRQ4) +AT91C_ID_IRQ5 EQU (30) ;- Advanced Interrupt Controller (IRQ5) +AT91C_ID_IRQ6 EQU (31) ;- Advanced Interrupt Controller (IRQ6) + +;- ***************************************************************************** +;- BASE ADDRESS DEFINITIONS FOR AT91RM9200 +;- ***************************************************************************** +AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address +AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address +AT91C_BASE_RTC EQU (0xFFFFFE00) ;- (RTC) Base Address +AT91C_BASE_ST EQU (0xFFFFFD00) ;- (ST) Base Address +AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address +AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address +AT91C_BASE_PIOD EQU (0xFFFFFA00) ;- (PIOD) Base Address +AT91C_BASE_PIOC EQU (0xFFFFF800) ;- (PIOC) Base Address +AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address +AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address +AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address +AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address +AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address +AT91C_BASE_PDC_SPI EQU (0xFFFE0100) ;- (PDC_SPI) Base Address +AT91C_BASE_SPI EQU (0xFFFE0000) ;- (SPI) Base Address +AT91C_BASE_PDC_SSC2 EQU (0xFFFD8100) ;- (PDC_SSC2) Base Address +AT91C_BASE_SSC2 EQU (0xFFFD8000) ;- (SSC2) Base Address +AT91C_BASE_PDC_SSC1 EQU (0xFFFD4100) ;- (PDC_SSC1) Base Address +AT91C_BASE_SSC1 EQU (0xFFFD4000) ;- (SSC1) Base Address +AT91C_BASE_PDC_SSC0 EQU (0xFFFD0100) ;- (PDC_SSC0) Base Address +AT91C_BASE_SSC0 EQU (0xFFFD0000) ;- (SSC0) Base Address +AT91C_BASE_PDC_US3 EQU (0xFFFCC100) ;- (PDC_US3) Base Address +AT91C_BASE_US3 EQU (0xFFFCC000) ;- (US3) Base Address +AT91C_BASE_PDC_US2 EQU (0xFFFC8100) ;- (PDC_US2) Base Address +AT91C_BASE_US2 EQU (0xFFFC8000) ;- (US2) Base Address +AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address +AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address +AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address +AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address +AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address +AT91C_BASE_PDC_MCI EQU (0xFFFB4100) ;- (PDC_MCI) Base Address +AT91C_BASE_MCI EQU (0xFFFB4000) ;- (MCI) Base Address +AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address +AT91C_BASE_TC5 EQU (0xFFFA4080) ;- (TC5) Base Address +AT91C_BASE_TC4 EQU (0xFFFA4040) ;- (TC4) Base Address +AT91C_BASE_TC3 EQU (0xFFFA4000) ;- (TC3) Base Address +AT91C_BASE_TCB1 EQU (0xFFFA4080) ;- (TCB1) Base Address +AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address +AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address +AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address +AT91C_BASE_TCB0 EQU (0xFFFA0000) ;- (TCB0) Base Address +AT91C_BASE_UHP EQU (0x00300000) ;- (UHP) Base Address +AT91C_BASE_EMAC EQU (0xFFFBC000) ;- (EMAC) Base Address +AT91C_BASE_EBI EQU (0xFFFFFF60) ;- (EBI) Base Address +AT91C_BASE_SMC2 EQU (0xFFFFFF70) ;- (SMC2) Base Address +AT91C_BASE_SDRC EQU (0xFFFFFF90) ;- (SDRC) Base Address +AT91C_BASE_BFC EQU (0xFFFFFFC0) ;- (BFC) Base Address + +;- ***************************************************************************** +;- MEMORY MAPPING DEFINITIONS FOR AT91RM9200 +;- ***************************************************************************** +AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address +AT91C_ISRAM_SIZE EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbyte) +AT91C_IROM EQU (0x00100000) ;- Internal ROM base address +AT91C_IROM_SIZE EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte) + + + END diff --git a/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h b/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h new file mode 100644 index 0000000..dabab01 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h @@ -0,0 +1,2401 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91RM9200.h +// Object : AT91RM9200 definitions +// Generated : AT91 SW Application Group 11/19/2003 (17:20:51) +// +// CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// +// CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// +// CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// +// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// +// CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// +// CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// +// CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// +// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// +// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// +// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// +// CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// +// CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// +// CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// +// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// +// CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// +// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// +// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// +// CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// +// CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// +// CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// +// CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// +// CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// +// CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// +// ---------------------------------------------------------------------------- + +// Hardware register definition + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_MC structure *** +#define MC_RCR ( 0) // MC Remap Control Register +#define MC_ASR ( 4) // MC Abort Status Register +#define MC_AASR ( 8) // MC Abort Address Status Register +#define MC_PUIA (16) // MC Protection Unit Area +#define MC_PUP (80) // MC Protection Unit Peripherals +#define MC_PUER (84) // MC Protection Unit Enable Register +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface +// ***************************************************************************** +// *** Register offset in AT91S_RTC structure *** +#define RTC_CR ( 0) // Control Register +#define RTC_MR ( 4) // Mode Register +#define RTC_TIMR ( 8) // Time Register +#define RTC_CALR (12) // Calendar Register +#define RTC_TIMALR (16) // Time Alarm Register +#define RTC_CALALR (20) // Calendar Alarm Register +#define RTC_SR (24) // Status Register +#define RTC_SCCR (28) // Status Clear Command Register +#define RTC_IER (32) // Interrupt Enable Register +#define RTC_IDR (36) // Interrupt Disable Register +#define RTC_IMR (40) // Interrupt Mask Register +#define RTC_VER (44) // Valid Entry Register +// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- +#define AT91C_RTC_UPDTIM (0x1 << 0) // (RTC) Update Request Time Register +#define AT91C_RTC_UPDCAL (0x1 << 1) // (RTC) Update Request Calendar Register +#define AT91C_RTC_TIMEVSEL (0x3 << 8) // (RTC) Time Event Selection +#define AT91C_RTC_TIMEVSEL_MINUTE (0x0 << 8) // (RTC) Minute change. +#define AT91C_RTC_TIMEVSEL_HOUR (0x1 << 8) // (RTC) Hour change. +#define AT91C_RTC_TIMEVSEL_DAY24 (0x2 << 8) // (RTC) Every day at midnight. +#define AT91C_RTC_TIMEVSEL_DAY12 (0x3 << 8) // (RTC) Every day at noon. +#define AT91C_RTC_CALEVSEL (0x3 << 16) // (RTC) Calendar Event Selection +#define AT91C_RTC_CALEVSEL_WEEK (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). +#define AT91C_RTC_CALEVSEL_MONTH (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). +#define AT91C_RTC_CALEVSEL_YEAR (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). +// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- +#define AT91C_RTC_HRMOD (0x1 << 0) // (RTC) 12-24 hour Mode +// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- +#define AT91C_RTC_SEC (0x7F << 0) // (RTC) Current Second +#define AT91C_RTC_MIN (0x7F << 8) // (RTC) Current Minute +#define AT91C_RTC_HOUR (0x1F << 16) // (RTC) Current Hour +#define AT91C_RTC_AMPM (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator +// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- +#define AT91C_RTC_CENT (0x3F << 0) // (RTC) Current Century +#define AT91C_RTC_YEAR (0xFF << 8) // (RTC) Current Year +#define AT91C_RTC_MONTH (0x1F << 16) // (RTC) Current Month +#define AT91C_RTC_DAY (0x7 << 21) // (RTC) Current Day +#define AT91C_RTC_DATE (0x3F << 24) // (RTC) Current Date +// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- +#define AT91C_RTC_SECEN (0x1 << 7) // (RTC) Second Alarm Enable +#define AT91C_RTC_MINEN (0x1 << 15) // (RTC) Minute Alarm +#define AT91C_RTC_HOUREN (0x1 << 23) // (RTC) Current Hour +// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- +#define AT91C_RTC_MONTHEN (0x1 << 23) // (RTC) Month Alarm Enable +#define AT91C_RTC_DATEEN (0x1 << 31) // (RTC) Date Alarm Enable +// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- +#define AT91C_RTC_ACKUPD (0x1 << 0) // (RTC) Acknowledge for Update +#define AT91C_RTC_ALARM (0x1 << 1) // (RTC) Alarm Flag +#define AT91C_RTC_SECEV (0x1 << 2) // (RTC) Second Event +#define AT91C_RTC_TIMEV (0x1 << 3) // (RTC) Time Event +#define AT91C_RTC_CALEV (0x1 << 4) // (RTC) Calendar event +// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- +// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- +// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- +// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- +// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- +#define AT91C_RTC_NVTIM (0x1 << 0) // (RTC) Non valid Time +#define AT91C_RTC_NVCAL (0x1 << 1) // (RTC) Non valid Calendar +#define AT91C_RTC_NVTIMALR (0x1 << 2) // (RTC) Non valid time Alarm +#define AT91C_RTC_NVCALALR (0x1 << 3) // (RTC) Nonvalid Calendar Alarm + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Timer Interface +// ***************************************************************************** +// *** Register offset in AT91S_ST structure *** +#define ST_CR ( 0) // Control Register +#define ST_PIMR ( 4) // Period Interval Mode Register +#define ST_WDMR ( 8) // Watchdog Mode Register +#define ST_RTMR (12) // Real-time Mode Register +#define ST_SR (16) // Status Register +#define ST_IER (20) // Interrupt Enable Register +#define ST_IDR (24) // Interrupt Disable Register +#define ST_IMR (28) // Interrupt Mask Register +#define ST_RTAR (32) // Real-time Alarm Register +#define ST_CRTR (36) // Current Real-time Register +// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- +#define AT91C_ST_WDRST (0x1 << 0) // (ST) Watchdog Timer Restart +// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- +#define AT91C_ST_PIV (0xFFFF << 0) // (ST) Watchdog Timer Restart +// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- +#define AT91C_ST_WDV (0xFFFF << 0) // (ST) Watchdog Timer Restart +#define AT91C_ST_RSTEN (0x1 << 16) // (ST) Reset Enable +#define AT91C_ST_EXTEN (0x1 << 17) // (ST) External Signal Assertion Enable +// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- +#define AT91C_ST_RTPRES (0xFFFF << 0) // (ST) Real-time Timer Prescaler Value +// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- +#define AT91C_ST_PITS (0x1 << 0) // (ST) Period Interval Timer Interrupt +#define AT91C_ST_WDOVF (0x1 << 1) // (ST) Watchdog Overflow +#define AT91C_ST_RTTINC (0x1 << 2) // (ST) Real-time Timer Increment +#define AT91C_ST_ALMS (0x1 << 3) // (ST) Alarm Status +// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- +// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- +// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- +// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- +#define AT91C_ST_ALMV (0xFFFFF << 0) // (ST) Alarm Value Value +// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- +#define AT91C_ST_CRTV (0xFFFFF << 0) // (ST) Current Real-time Value + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +// *** Register offset in AT91S_PMC structure *** +#define PMC_SCER ( 0) // System Clock Enable Register +#define PMC_SCDR ( 4) // System Clock Disable Register +#define PMC_SCSR ( 8) // System Clock Status Register +#define PMC_PCER (16) // Peripheral Clock Enable Register +#define PMC_PCDR (20) // Peripheral Clock Disable Register +#define PMC_PCSR (24) // Peripheral Clock Status Register +#define PMC_MCKR (48) // Master Clock Register +#define PMC_PCKR (64) // Programmable Clock Register +#define PMC_IER (96) // Interrupt Enable Register +#define PMC_IDR (100) // Interrupt Disable Register +#define PMC_SR (104) // Status Register +#define PMC_IMR (108) // Interrupt Mask Register +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 1) // (PMC) USB Device Port Clock +#define AT91C_PMC_MCKUDP (0x1 << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend +#define AT91C_PMC_UHP (0x1 << 4) // (PMC) USB Host Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK4 (0x1 << 12) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK5 (0x1 << 13) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK6 (0x1 << 14) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK7 (0x1 << 15) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected +#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division +#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same +#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock +#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is three times faster than the master clock +#define AT91C_PMC_MDIV_4 (0x3 << 8) // (PMC) The processor clock is four times faster than the master clock +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK4RDY (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK5RDY (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK6RDY (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK7RDY (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +// *** Register offset in AT91S_CKGR structure *** +#define CKGR_MOR ( 0) // Main Oscillator Register +#define CKGR_MCFR ( 4) // Main Clock Frequency Register +#define CKGR_PLLAR ( 8) // PLL A Register +#define CKGR_PLLBR (12) // PLL B Register +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCTEST (0x1 << 1) // (CKGR) Oscillator Test +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- +#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter +#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range +#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet +#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier +#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) PLL A Source +// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter +#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range +#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet +#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier +#define AT91C_CKGR_USB_96M (0x1 << 28) // (CKGR) Divider for USB Ports +#define AT91C_CKGR_USB_PLL (0x1 << 29) // (CKGR) PLL Use + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +// *** Register offset in AT91S_PIO structure *** +#define PIO_PER ( 0) // PIO Enable Register +#define PIO_PDR ( 4) // PIO Disable Register +#define PIO_PSR ( 8) // PIO Status Register +#define PIO_OER (16) // Output Enable Register +#define PIO_ODR (20) // Output Disable Registerr +#define PIO_OSR (24) // Output Status Register +#define PIO_IFER (32) // Input Filter Enable Register +#define PIO_IFDR (36) // Input Filter Disable Register +#define PIO_IFSR (40) // Input Filter Status Register +#define PIO_SODR (48) // Set Output Data Register +#define PIO_CODR (52) // Clear Output Data Register +#define PIO_ODSR (56) // Output Data Status Register +#define PIO_PDSR (60) // Pin Data Status Register +#define PIO_IER (64) // Interrupt Enable Register +#define PIO_IDR (68) // Interrupt Disable Register +#define PIO_IMR (72) // Interrupt Mask Register +#define PIO_ISR (76) // Interrupt Status Register +#define PIO_MDER (80) // Multi-driver Enable Register +#define PIO_MDDR (84) // Multi-driver Disable Register +#define PIO_MDSR (88) // Multi-driver Status Register +#define PIO_PPUDR (96) // Pull-up Disable Register +#define PIO_PPUER (100) // Pull-up Enable Register +#define PIO_PPUSR (104) // Pad Pull-up Status Register +#define PIO_ASR (112) // Select A Register +#define PIO_BSR (116) // Select B Register +#define PIO_ABSR (120) // AB Select Status Register +#define PIO_OWER (160) // Output Write Enable Register +#define PIO_OWDR (164) // Output Write Disable Register +#define PIO_OWSR (168) // Output Write Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +// *** Register offset in AT91S_DBGU structure *** +#define DBGU_CR ( 0) // Control Register +#define DBGU_MR ( 4) // Mode Register +#define DBGU_IER ( 8) // Interrupt Enable Register +#define DBGU_IDR (12) // Interrupt Disable Register +#define DBGU_IMR (16) // Interrupt Mask Register +#define DBGU_CSR (20) // Channel Status Register +#define DBGU_RHR (24) // Receiver Holding Register +#define DBGU_THR (28) // Transmitter Holding Register +#define DBGU_BRGR (32) // Baud Rate Generator Register +#define DBGU_C1R (64) // Chip ID1 Register +#define DBGU_C2R (68) // Chip ID2 Register +#define DBGU_FNTR (72) // Force NTRST Register +#define DBGU_RPR (256) // Receive Pointer Register +#define DBGU_RCR (260) // Receive Counter Register +#define DBGU_TPR (264) // Transmit Pointer Register +#define DBGU_TCR (268) // Transmit Counter Register +#define DBGU_RNPR (272) // Receive Next Pointer Register +#define DBGU_RNCR (276) // Receive Next Counter Register +#define DBGU_TNPR (280) // Transmit Next Pointer Register +#define DBGU_TNCR (284) // Transmit Next Counter Register +#define DBGU_PTCR (288) // PDC Transfer Control Register +#define DBGU_PTSR (292) // PDC Transfer Status Register +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral Data Controller +// ***************************************************************************** +// *** Register offset in AT91S_PDC structure *** +#define PDC_RPR ( 0) // Receive Pointer Register +#define PDC_RCR ( 4) // Receive Counter Register +#define PDC_TPR ( 8) // Transmit Pointer Register +#define PDC_TCR (12) // Transmit Counter Register +#define PDC_RNPR (16) // Receive Next Pointer Register +#define PDC_RNCR (20) // Receive Next Counter Register +#define PDC_TNPR (24) // Transmit Next Pointer Register +#define PDC_TNCR (28) // Transmit Next Counter Register +#define PDC_PTCR (32) // PDC Transfer Control Register +#define PDC_PTSR (36) // PDC Transfer Status Register +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +// *** Register offset in AT91S_AIC structure *** +#define AIC_SMR ( 0) // Source Mode Register +#define AIC_SVR (128) // Source Vector Register +#define AIC_IVR (256) // IRQ Vector Register +#define AIC_FVR (260) // FIQ Vector Register +#define AIC_ISR (264) // Interrupt Status Register +#define AIC_IPR (268) // Interrupt Pending Register +#define AIC_IMR (272) // Interrupt Mask Register +#define AIC_CISR (276) // Core Interrupt Status Register +#define AIC_IECR (288) // Interrupt Enable Command Register +#define AIC_IDCR (292) // Interrupt Disable Command Register +#define AIC_ICCR (296) // Interrupt Clear Command Register +#define AIC_ISCR (300) // Interrupt Set Command Register +#define AIC_EOICR (304) // End of Interrupt Command Register +#define AIC_SPU (308) // Spurious Vector Register +#define AIC_DCR (312) // Debug Control Register (Protect) +#define AIC_FFER (320) // Fast Forcing Enable Register +#define AIC_FFDR (324) // Fast Forcing Disable Register +#define AIC_FFSR (328) // Fast Forcing Status Register +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive +#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +// *** Register offset in AT91S_SPI structure *** +#define SPI_CR ( 0) // Control Register +#define SPI_MR ( 4) // Mode Register +#define SPI_RDR ( 8) // Receive Data Register +#define SPI_TDR (12) // Transmit Data Register +#define SPI_SR (16) // Status Register +#define SPI_IER (20) // Interrupt Enable Register +#define SPI_IDR (24) // Interrupt Disable Register +#define SPI_IMR (28) // Interrupt Mask Register +#define SPI_CSR (48) // Chip Select Register +#define SPI_RPR (256) // Receive Pointer Register +#define SPI_RCR (260) // Receive Counter Register +#define SPI_TPR (264) // Transmit Pointer Register +#define SPI_TCR (268) // Transmit Counter Register +#define SPI_RNPR (272) // Receive Next Pointer Register +#define SPI_RNCR (276) // Receive Next Counter Register +#define SPI_TNPR (280) // Transmit Next Pointer Register +#define SPI_TNCR (284) // Transmit Next Counter Register +#define SPI_PTCR (288) // PDC Transfer Control Register +#define SPI_PTSR (292) // PDC Transfer Status Register +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_DIV32 (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_SPENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_SPENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SSC structure *** +#define SSC_CR ( 0) // Control Register +#define SSC_CMR ( 4) // Clock Mode Register +#define SSC_RCMR (16) // Receive Clock ModeRegister +#define SSC_RFMR (20) // Receive Frame Mode Register +#define SSC_TCMR (24) // Transmit Clock Mode Register +#define SSC_TFMR (28) // Transmit Frame Mode Register +#define SSC_RHR (32) // Receive Holding Register +#define SSC_THR (36) // Transmit Holding Register +#define SSC_RSHR (48) // Receive Sync Holding Register +#define SSC_TSHR (52) // Transmit Sync Holding Register +#define SSC_RC0R (56) // Receive Compare 0 Register +#define SSC_RC1R (60) // Receive Compare 1 Register +#define SSC_SR (64) // Status Register +#define SSC_IER (68) // Interrupt Enable Register +#define SSC_IDR (72) // Interrupt Disable Register +#define SSC_IMR (76) // Interrupt Mask Register +#define SSC_RPR (256) // Receive Pointer Register +#define SSC_RCR (260) // Receive Counter Register +#define SSC_TPR (264) // Transmit Pointer Register +#define SSC_TCR (268) // Transmit Counter Register +#define SSC_RNPR (272) // Receive Next Pointer Register +#define SSC_RNCR (276) // Receive Next Counter Register +#define SSC_TNPR (280) // Transmit Next Pointer Register +#define SSC_TNCR (284) // Transmit Next Counter Register +#define SSC_PTCR (288) // PDC Transfer Control Register +#define SSC_PTSR (292) // PDC Transfer Status Register +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +// *** Register offset in AT91S_USART structure *** +#define US_CR ( 0) // Control Register +#define US_MR ( 4) // Mode Register +#define US_IER ( 8) // Interrupt Enable Register +#define US_IDR (12) // Interrupt Disable Register +#define US_IMR (16) // Interrupt Mask Register +#define US_CSR (20) // Channel Status Register +#define US_RHR (24) // Receiver Holding Register +#define US_THR (28) // Transmitter Holding Register +#define US_BRGR (32) // Baud Rate Generator Register +#define US_RTOR (36) // Receiver Time-out Register +#define US_TTGR (40) // Transmitter Time-guard Register +#define US_FIDI (64) // FI_DI_Ratio Register +#define US_NER (68) // Nb Errors Register +#define US_XXR (72) // XON_XOFF Register +#define US_IF (76) // IRDA_FILTER Register +#define US_RPR (256) // Receive Pointer Register +#define US_RCR (260) // Receive Counter Register +#define US_TPR (264) // Transmit Pointer Register +#define US_TCR (268) // Transmit Counter Register +#define US_RNPR (272) // Receive Next Pointer Register +#define US_RNCR (276) // Receive Next Counter Register +#define US_TNPR (280) // Transmit Next Pointer Register +#define US_TNCR (284) // Transmit Next Counter Register +#define US_PTCR (288) // PDC Transfer Control Register +#define US_PTSR (292) // PDC Transfer Status Register +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +// *** Register offset in AT91S_TWI structure *** +#define TWI_CR ( 0) // Control Register +#define TWI_MMR ( 4) // Master Mode Register +#define TWI_SMR ( 8) // Slave Mode Register +#define TWI_IADR (12) // Internal Address Register +#define TWI_CWGR (16) // Clock Waveform Generator Register +#define TWI_SR (32) // Status Register +#define TWI_IER (36) // Interrupt Enable Register +#define TWI_IDR (40) // Interrupt Disable Register +#define TWI_IMR (44) // Interrupt Mask Register +#define TWI_RHR (48) // Receive Holding Register +#define TWI_THR (52) // Transmit Holding Register +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access +#define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error +#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error +#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Multimedia Card Interface +// ***************************************************************************** +// *** Register offset in AT91S_MCI structure *** +#define MCI_CR ( 0) // MCI Control Register +#define MCI_MR ( 4) // MCI Mode Register +#define MCI_DTOR ( 8) // MCI Data Timeout Register +#define MCI_SDCR (12) // MCI SD Card Register +#define MCI_ARGR (16) // MCI Argument Register +#define MCI_CMDR (20) // MCI Command Register +#define MCI_RSPR (32) // MCI Response Register +#define MCI_RDR (48) // MCI Receive Data Register +#define MCI_TDR (52) // MCI Transmit Data Register +#define MCI_SR (64) // MCI Status Register +#define MCI_IER (68) // MCI Interrupt Enable Register +#define MCI_IDR (72) // MCI Interrupt Disable Register +#define MCI_IMR (76) // MCI Interrupt Mask Register +#define MCI_RPR (256) // Receive Pointer Register +#define MCI_RCR (260) // Receive Counter Register +#define MCI_TPR (264) // Transmit Pointer Register +#define MCI_TCR (268) // Transmit Counter Register +#define MCI_RNPR (272) // Receive Next Pointer Register +#define MCI_RNCR (276) // Receive Next Counter Register +#define MCI_TNPR (280) // Transmit Next Pointer Register +#define MCI_TNCR (284) // Transmit Next Counter Register +#define MCI_PTCR (288) // PDC Transfer Control Register +#define MCI_PTSR (292) // PDC Transfer Status Register +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable +#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable +#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable +#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +#define AT91C_MCI_CLKDIV (0x1 << 0) // (MCI) Clock Divider +#define AT91C_MCI_PWSDIV (0x1 << 8) // (MCI) Power Saving Divider +#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value +#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode +#define AT91C_MCI_BLKLEN (0x1 << 18) // (MCI) Data Block Length +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +#define AT91C_MCI_DTOCYC (0x1 << 0) // (MCI) Data Timeout Cycle Number +#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier +#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 +#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16 +#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128 +#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256 +#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024 +#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 +#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 +#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +#define AT91C_MCI_SCDSEL (0x1 << 0) // (MCI) SD Card Selector +#define AT91C_MCI_SCDBUS (0x1 << 7) // (MCI) SD Card Bus Width +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +#define AT91C_MCI_CMDNB (0x1F << 0) // (MCI) Command Number +#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type +#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response +#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response +#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response +#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD +#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD +#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD +#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD +#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command +#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response +#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command +#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond +#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD +#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer +#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer +#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer +#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction +#define AT91C_MCI_TRTYP (0x3 << 19) // (MCI) Transfer Type +#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) Block Transfer type +#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) Multiple Block transfer type +#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) Stream transfer type +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag +#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag +#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag +#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag +#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag +#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag +#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag +#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag +#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag +#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag +#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag +#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag +#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag +#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag +#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag +#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag +#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag +#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag +#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +// *** Register offset in AT91S_UDP structure *** +#define UDP_NUM ( 0) // Frame Number Register +#define UDP_GLBSTATE ( 4) // Global State Register +#define UDP_FADDR ( 8) // Function Address Register +#define UDP_IER (16) // Interrupt Enable Register +#define UDP_IDR (20) // Interrupt Disable Register +#define UDP_IMR (24) // Interrupt Mask Register +#define UDP_ISR (28) // Interrupt Status Register +#define UDP_ICR (32) // Interrupt Clear Register +#define UDP_RSTEP (40) // Reset Endpoint Register +#define UDP_CSR (48) // Endpoint Control and Status Register +#define UDP_FDR (80) // Endpoint FIFO Data Register +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +// *** Register offset in AT91S_TC structure *** +#define TC_CCR ( 0) // Channel Control Register +#define TC_CMR ( 4) // Channel Mode Register +#define TC_CV (16) // Counter Value +#define TC_RA (20) // Register A +#define TC_RB (24) // Register B +#define TC_RC (28) // Register C +#define TC_SR (32) // Status Register +#define TC_IER (36) // Interrupt Enable Register +#define TC_IDR (40) // Interrupt Disable Register +#define TC_IMR (44) // Interrupt Mask Register +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// *** Register offset in AT91S_TCB structure *** +#define TCB_TC0 ( 0) // TC Channel 0 +#define TCB_TC1 (64) // TC Channel 1 +#define TCB_TC2 (128) // TC Channel 2 +#define TCB_BCR (192) // TC Block Control Register +#define TCB_BMR (196) // TC Block Mode Register +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Host Interface +// ***************************************************************************** +// *** Register offset in AT91S_UHP structure *** +#define UHP_HcRevision ( 0) // Revision +#define UHP_HcControl ( 4) // Operating modes for the Host Controller +#define UHP_HcCommandStatus ( 8) // Command & status Register +#define UHP_HcInterruptStatus (12) // Interrupt Status Register +#define UHP_HcInterruptEnable (16) // Interrupt Enable Register +#define UHP_HcInterruptDisable (20) // Interrupt Disable Register +#define UHP_HcHCCA (24) // Pointer to the Host Controller Communication Area +#define UHP_HcPeriodCurrentED (28) // Current Isochronous or Interrupt Endpoint Descriptor +#define UHP_HcControlHeadED (32) // First Endpoint Descriptor of the Control list +#define UHP_HcControlCurrentED (36) // Endpoint Control and Status Register +#define UHP_HcBulkHeadED (40) // First endpoint register of the Bulk list +#define UHP_HcBulkCurrentED (44) // Current endpoint of the Bulk list +#define UHP_HcBulkDoneHead (48) // Last completed transfer descriptor +#define UHP_HcFmInterval (52) // Bit time between 2 consecutive SOFs +#define UHP_HcFmRemaining (56) // Bit time remaining in the current Frame +#define UHP_HcFmNumber (60) // Frame number +#define UHP_HcPeriodicStart (64) // Periodic Start +#define UHP_HcLSThreshold (68) // LS Threshold +#define UHP_HcRhDescriptorA (72) // Root Hub characteristics A +#define UHP_HcRhDescriptorB (76) // Root Hub characteristics B +#define UHP_HcRhStatus (80) // Root Hub Status register +#define UHP_HcRhPortStatus (84) // Root Hub Port Status Register + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Ethernet MAC +// ***************************************************************************** +// *** Register offset in AT91S_EMAC structure *** +#define EMAC_CTL ( 0) // Network Control Register +#define EMAC_CFG ( 4) // Network Configuration Register +#define EMAC_SR ( 8) // Network Status Register +#define EMAC_TAR (12) // Transmit Address Register +#define EMAC_TCR (16) // Transmit Control Register +#define EMAC_TSR (20) // Transmit Status Register +#define EMAC_RBQP (24) // Receive Buffer Queue Pointer +#define EMAC_RSR (32) // Receive Status Register +#define EMAC_ISR (36) // Interrupt Status Register +#define EMAC_IER (40) // Interrupt Enable Register +#define EMAC_IDR (44) // Interrupt Disable Register +#define EMAC_IMR (48) // Interrupt Mask Register +#define EMAC_MAN (52) // PHY Maintenance Register +#define EMAC_FRA (64) // Frames Transmitted OK Register +#define EMAC_SCOL (68) // Single Collision Frame Register +#define EMAC_MCOL (72) // Multiple Collision Frame Register +#define EMAC_OK (76) // Frames Received OK Register +#define EMAC_SEQE (80) // Frame Check Sequence Error Register +#define EMAC_ALE (84) // Alignment Error Register +#define EMAC_DTE (88) // Deferred Transmission Frame Register +#define EMAC_LCOL (92) // Late Collision Register +#define EMAC_ECOL (96) // Excessive Collision Register +#define EMAC_CSE (100) // Carrier Sense Error Register +#define EMAC_TUE (104) // Transmit Underrun Error Register +#define EMAC_CDE (108) // Code Error Register +#define EMAC_ELR (112) // Excessive Length Error Register +#define EMAC_RJB (116) // Receive Jabber Register +#define EMAC_USF (120) // Undersize Frame Register +#define EMAC_SQEE (124) // SQE Test Error Register +#define EMAC_DRFC (128) // Discarded RX Frame Register +#define EMAC_HSH (144) // Hash Address High[63:32] +#define EMAC_HSL (148) // Hash Address Low[31:0] +#define EMAC_SA1L (152) // Specific Address 1 Low, First 4 bytes +#define EMAC_SA1H (156) // Specific Address 1 High, Last 2 bytes +#define EMAC_SA2L (160) // Specific Address 2 Low, First 4 bytes +#define EMAC_SA2H (164) // Specific Address 2 High, Last 2 bytes +#define EMAC_SA3L (168) // Specific Address 3 Low, First 4 bytes +#define EMAC_SA3H (172) // Specific Address 3 High, Last 2 bytes +#define EMAC_SA4L (176) // Specific Address 4 Low, First 4 bytes +#define EMAC_SA4H (180) // Specific Address 4 High, Last 2 bytesr +// -------- EMAC_CTL : (EMAC Offset: 0x0) -------- +#define AT91C_EMAC_LB (0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. +#define AT91C_EMAC_LBL (0x1 << 1) // (EMAC) Loopback local. +#define AT91C_EMAC_RE (0x1 << 2) // (EMAC) Receive enable. +#define AT91C_EMAC_TE (0x1 << 3) // (EMAC) Transmit enable. +#define AT91C_EMAC_MPE (0x1 << 4) // (EMAC) Management port enable. +#define AT91C_EMAC_CSR (0x1 << 5) // (EMAC) Clear statistics registers. +#define AT91C_EMAC_ISR (0x1 << 6) // (EMAC) Increment statistics registers. +#define AT91C_EMAC_WES (0x1 << 7) // (EMAC) Write enable for statistics registers. +#define AT91C_EMAC_BP (0x1 << 8) // (EMAC) Back pressure. +// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- +#define AT91C_EMAC_SPD (0x1 << 0) // (EMAC) Speed. +#define AT91C_EMAC_FD (0x1 << 1) // (EMAC) Full duplex. +#define AT91C_EMAC_BR (0x1 << 2) // (EMAC) Bit rate. +#define AT91C_EMAC_CAF (0x1 << 4) // (EMAC) Copy all frames. +#define AT91C_EMAC_NBC (0x1 << 5) // (EMAC) No broadcast. +#define AT91C_EMAC_MTI (0x1 << 6) // (EMAC) Multicast hash enable +#define AT91C_EMAC_UNI (0x1 << 7) // (EMAC) Unicast hash enable. +#define AT91C_EMAC_BIG (0x1 << 8) // (EMAC) Receive 1522 bytes. +#define AT91C_EMAC_EAE (0x1 << 9) // (EMAC) External address match enable. +#define AT91C_EMAC_CLK (0x3 << 10) // (EMAC) +#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) // (EMAC) HCLK divided by 8 +#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) // (EMAC) HCLK divided by 16 +#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) // (EMAC) HCLK divided by 32 +#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) // (EMAC) HCLK divided by 64 +#define AT91C_EMAC_RTY (0x1 << 12) // (EMAC) +#define AT91C_EMAC_RMII (0x1 << 13) // (EMAC) +// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- +#define AT91C_EMAC_MDIO (0x1 << 1) // (EMAC) +#define AT91C_EMAC_IDLE (0x1 << 2) // (EMAC) +// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- +#define AT91C_EMAC_LEN (0x7FF << 0) // (EMAC) +#define AT91C_EMAC_NCRC (0x1 << 15) // (EMAC) +// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- +#define AT91C_EMAC_OVR (0x1 << 0) // (EMAC) +#define AT91C_EMAC_COL (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RLE (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TXIDLE (0x1 << 3) // (EMAC) +#define AT91C_EMAC_BNQ (0x1 << 4) // (EMAC) +#define AT91C_EMAC_COMP (0x1 << 5) // (EMAC) +#define AT91C_EMAC_UND (0x1 << 6) // (EMAC) +// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- +#define AT91C_EMAC_BNA (0x1 << 0) // (EMAC) +#define AT91C_EMAC_REC (0x1 << 1) // (EMAC) +// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- +#define AT91C_EMAC_DONE (0x1 << 0) // (EMAC) +#define AT91C_EMAC_RCOM (0x1 << 1) // (EMAC) +#define AT91C_EMAC_RBNA (0x1 << 2) // (EMAC) +#define AT91C_EMAC_TOVR (0x1 << 3) // (EMAC) +#define AT91C_EMAC_TUND (0x1 << 4) // (EMAC) +#define AT91C_EMAC_RTRY (0x1 << 5) // (EMAC) +#define AT91C_EMAC_TBRE (0x1 << 6) // (EMAC) +#define AT91C_EMAC_TCOM (0x1 << 7) // (EMAC) +#define AT91C_EMAC_TIDLE (0x1 << 8) // (EMAC) +#define AT91C_EMAC_LINK (0x1 << 9) // (EMAC) +#define AT91C_EMAC_ROVR (0x1 << 10) // (EMAC) +#define AT91C_EMAC_HRESP (0x1 << 11) // (EMAC) +// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- +// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- +// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- +// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- +#define AT91C_EMAC_DATA (0xFFFF << 0) // (EMAC) +#define AT91C_EMAC_CODE (0x3 << 16) // (EMAC) +#define AT91C_EMAC_REGA (0x1F << 18) // (EMAC) +#define AT91C_EMAC_PHYA (0x1F << 23) // (EMAC) +#define AT91C_EMAC_RW (0x3 << 28) // (EMAC) +#define AT91C_EMAC_HIGH (0x1 << 30) // (EMAC) +#define AT91C_EMAC_LOW (0x1 << 31) // (EMAC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +// *** Register offset in AT91S_EBI structure *** +#define EBI_CSA ( 0) // Chip Select Assignment Register +#define EBI_CFGR ( 4) // Configuration Register +// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- +#define AT91C_EBI_CS0A (0x1 << 0) // (EBI) Chip Select 0 Assignment +#define AT91C_EBI_CS0A_SMC (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS0A_BFC (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller. +#define AT91C_EBI_CS1A (0x1 << 1) // (EBI) Chip Select 1 Assignment +#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_EBI_CS3A (0x1 << 3) // (EBI) Chip Select 3 Assignment +#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. +#define AT91C_EBI_CS3A_SMC_SmartMedia (0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_EBI_CS4A (0x1 << 4) // (EBI) Chip Select 4 Assignment +#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. +#define AT91C_EBI_CS4A_SMC_CompactFlash (0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. +// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- +#define AT91C_EBI_DBPUC (0x1 << 0) // (EBI) Data Bus Pull-Up Configuration +#define AT91C_EBI_EBSEN (0x1 << 1) // (EBI) Bus Sharing Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface +// ***************************************************************************** +// *** Register offset in AT91S_SMC2 structure *** +#define SMC2_CSR ( 0) // SMC2 Chip Select Register +// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- +#define AT91C_SMC2_NWS (0x7F << 0) // (SMC2) Number of Wait States +#define AT91C_SMC2_WSEN (0x1 << 7) // (SMC2) Wait State Enable +#define AT91C_SMC2_TDF (0xF << 8) // (SMC2) Data Float Time +#define AT91C_SMC2_BAT (0x1 << 12) // (SMC2) Byte Access Type +#define AT91C_SMC2_DBW (0x1 << 13) // (SMC2) Data Bus Width +#define AT91C_SMC2_DBW_16 (0x1 << 13) // (SMC2) 16-bit. +#define AT91C_SMC2_DBW_8 (0x2 << 13) // (SMC2) 8-bit. +#define AT91C_SMC2_DRP (0x1 << 15) // (SMC2) Data Read Protocol +#define AT91C_SMC2_ACSS (0x3 << 16) // (SMC2) Address to Chip Select Setup +#define AT91C_SMC2_ACSS_STANDARD (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. +#define AT91C_SMC2_ACSS_1_CYCLE (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. +#define AT91C_SMC2_ACSS_2_CYCLES (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. +#define AT91C_SMC2_ACSS_3_CYCLES (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. +#define AT91C_SMC2_RWSETUP (0x7 << 24) // (SMC2) Read and Write Signal Setup Time +#define AT91C_SMC2_RWHOLD (0x7 << 29) // (SMC2) Read and Write Signal Hold Time + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR SDRAM Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_SDRC structure *** +#define SDRC_MR ( 0) // SDRAM Controller Mode Register +#define SDRC_TR ( 4) // SDRAM Controller Refresh Timer Register +#define SDRC_CR ( 8) // SDRAM Controller Configuration Register +#define SDRC_SRR (12) // SDRAM Controller Self Refresh Register +#define SDRC_LPR (16) // SDRAM Controller Low Power Register +#define SDRC_IER (20) // SDRAM Controller Interrupt Enable Register +#define SDRC_IDR (24) // SDRAM Controller Interrupt Disable Register +#define SDRC_IMR (28) // SDRAM Controller Interrupt Mask Register +#define SDRC_ISR (32) // SDRAM Controller Interrupt Mask Register +// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- +#define AT91C_SDRC_MODE (0xF << 0) // (SDRC) Mode +#define AT91C_SDRC_MODE_NORMAL_CMD (0x0) // (SDRC) Normal Mode +#define AT91C_SDRC_MODE_NOP_CMD (0x1) // (SDRC) NOP Command +#define AT91C_SDRC_MODE_PRCGALL_CMD (0x2) // (SDRC) All Banks Precharge Command +#define AT91C_SDRC_MODE_LMR_CMD (0x3) // (SDRC) Load Mode Register Command +#define AT91C_SDRC_MODE_RFSH_CMD (0x4) // (SDRC) Refresh Command +#define AT91C_SDRC_DBW (0x1 << 4) // (SDRC) Data Bus Width +#define AT91C_SDRC_DBW_32_BITS (0x0 << 4) // (SDRC) 32 Bits datas bus +#define AT91C_SDRC_DBW_16_BITS (0x1 << 4) // (SDRC) 16 Bits datas bus +// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- +#define AT91C_SDRC_COUNT (0xFFF << 0) // (SDRC) Refresh Counter +// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- +#define AT91C_SDRC_NC (0x3 << 0) // (SDRC) Number of Column Bits +#define AT91C_SDRC_NC_8 (0x0) // (SDRC) 8 Bits +#define AT91C_SDRC_NC_9 (0x1) // (SDRC) 9 Bits +#define AT91C_SDRC_NC_10 (0x2) // (SDRC) 10 Bits +#define AT91C_SDRC_NC_11 (0x3) // (SDRC) 11 Bits +#define AT91C_SDRC_NR (0x3 << 2) // (SDRC) Number of Row Bits +#define AT91C_SDRC_NR_11 (0x0 << 2) // (SDRC) 11 Bits +#define AT91C_SDRC_NR_12 (0x1 << 2) // (SDRC) 12 Bits +#define AT91C_SDRC_NR_13 (0x2 << 2) // (SDRC) 13 Bits +#define AT91C_SDRC_NB (0x1 << 4) // (SDRC) Number of Banks +#define AT91C_SDRC_NB_2_BANKS (0x0 << 4) // (SDRC) 2 banks +#define AT91C_SDRC_NB_4_BANKS (0x1 << 4) // (SDRC) 4 banks +#define AT91C_SDRC_CAS (0x3 << 5) // (SDRC) CAS Latency +#define AT91C_SDRC_CAS_2 (0x2 << 5) // (SDRC) 2 cycles +#define AT91C_SDRC_TWR (0xF << 7) // (SDRC) Number of Write Recovery Time Cycles +#define AT91C_SDRC_TRC (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles +#define AT91C_SDRC_TRP (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles +#define AT91C_SDRC_TRCD (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles +#define AT91C_SDRC_TRAS (0xF << 23) // (SDRC) Number of RAS Active Time Cycles +#define AT91C_SDRC_TXSR (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles +// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- +#define AT91C_SDRC_SRCB (0x1 << 0) // (SDRC) Self-refresh Command Bit +// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- +#define AT91C_SDRC_LPCB (0x1 << 0) // (SDRC) Low-power Command Bit +// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +#define AT91C_SDRC_RES (0x1 << 0) // (SDRC) Refresh Error Status +// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface +// ***************************************************************************** +// *** Register offset in AT91S_BFC structure *** +#define BFC_MR ( 0) // BFC Mode Register +// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- +#define AT91C_BFC_BFCOM (0x3 << 0) // (BFC) Burst Flash Controller Operating Mode +#define AT91C_BFC_BFCOM_DISABLED (0x0) // (BFC) NPCS0 is driven by the SMC or remains high. +#define AT91C_BFC_BFCOM_ASYNC (0x1) // (BFC) Asynchronous +#define AT91C_BFC_BFCOM_BURST_READ (0x2) // (BFC) Burst Read +#define AT91C_BFC_BFCC (0x3 << 2) // (BFC) Burst Flash Controller Operating Mode +#define AT91C_BFC_BFCC_MCK (0x1 << 2) // (BFC) Master Clock. +#define AT91C_BFC_BFCC_MCK_DIV_2 (0x2 << 2) // (BFC) Master Clock divided by 2. +#define AT91C_BFC_BFCC_MCK_DIV_4 (0x3 << 2) // (BFC) Master Clock divided by 4. +#define AT91C_BFC_AVL (0xF << 4) // (BFC) Address Valid Latency +#define AT91C_BFC_PAGES (0x7 << 8) // (BFC) Page Size +#define AT91C_BFC_PAGES_NO_PAGE (0x0 << 8) // (BFC) No page handling. +#define AT91C_BFC_PAGES_16 (0x1 << 8) // (BFC) 16 bytes page size. +#define AT91C_BFC_PAGES_32 (0x2 << 8) // (BFC) 32 bytes page size. +#define AT91C_BFC_PAGES_64 (0x3 << 8) // (BFC) 64 bytes page size. +#define AT91C_BFC_PAGES_128 (0x4 << 8) // (BFC) 128 bytes page size. +#define AT91C_BFC_PAGES_256 (0x5 << 8) // (BFC) 256 bytes page size. +#define AT91C_BFC_PAGES_512 (0x6 << 8) // (BFC) 512 bytes page size. +#define AT91C_BFC_PAGES_1024 (0x7 << 8) // (BFC) 1024 bytes page size. +#define AT91C_BFC_OEL (0x3 << 12) // (BFC) Output Enable Latency +#define AT91C_BFC_BAAEN (0x1 << 16) // (BFC) Burst Address Advance Enable +#define AT91C_BFC_BFOEH (0x1 << 17) // (BFC) Burst Flash Output Enable Handling +#define AT91C_BFC_MUXEN (0x1 << 18) // (BFC) Multiplexed Bus Enable +#define AT91C_BFC_RDYEN (0x1 << 19) // (BFC) Ready Enable Mode + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91RM9200 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_PUER (0xFFFFFF54) // (MC) MC Protection Unit Enable Register +#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_PUP (0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_PUIA (0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register +// ========== Register definition for RTC peripheral ========== +#define AT91C_RTC_IMR (0xFFFFFE28) // (RTC) Interrupt Mask Register +#define AT91C_RTC_IER (0xFFFFFE20) // (RTC) Interrupt Enable Register +#define AT91C_RTC_SR (0xFFFFFE18) // (RTC) Status Register +#define AT91C_RTC_TIMALR (0xFFFFFE10) // (RTC) Time Alarm Register +#define AT91C_RTC_TIMR (0xFFFFFE08) // (RTC) Time Register +#define AT91C_RTC_CR (0xFFFFFE00) // (RTC) Control Register +#define AT91C_RTC_VER (0xFFFFFE2C) // (RTC) Valid Entry Register +#define AT91C_RTC_IDR (0xFFFFFE24) // (RTC) Interrupt Disable Register +#define AT91C_RTC_SCCR (0xFFFFFE1C) // (RTC) Status Clear Command Register +#define AT91C_RTC_CALALR (0xFFFFFE14) // (RTC) Calendar Alarm Register +#define AT91C_RTC_CALR (0xFFFFFE0C) // (RTC) Calendar Register +#define AT91C_RTC_MR (0xFFFFFE04) // (RTC) Mode Register +// ========== Register definition for ST peripheral ========== +#define AT91C_ST_CRTR (0xFFFFFD24) // (ST) Current Real-time Register +#define AT91C_ST_IMR (0xFFFFFD1C) // (ST) Interrupt Mask Register +#define AT91C_ST_IER (0xFFFFFD14) // (ST) Interrupt Enable Register +#define AT91C_ST_RTMR (0xFFFFFD0C) // (ST) Real-time Mode Register +#define AT91C_ST_PIMR (0xFFFFFD04) // (ST) Period Interval Mode Register +#define AT91C_ST_RTAR (0xFFFFFD20) // (ST) Real-time Alarm Register +#define AT91C_ST_IDR (0xFFFFFD18) // (ST) Interrupt Disable Register +#define AT91C_ST_SR (0xFFFFFD10) // (ST) Status Register +#define AT91C_ST_WDMR (0xFFFFFD08) // (ST) Watchdog Mode Register +#define AT91C_ST_CR (0xFFFFFD00) // (ST) Control Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register +#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_PLLBR (0xFFFFFC2C) // (CKGR) PLL B Register +#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register +#define AT91C_CKGR_PLLAR (0xFFFFFC28) // (CKGR) PLL A Register +#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register +// ========== Register definition for PIOD peripheral ========== +#define AT91C_PIOD_PDSR (0xFFFFFA3C) // (PIOD) Pin Data Status Register +#define AT91C_PIOD_CODR (0xFFFFFA34) // (PIOD) Clear Output Data Register +#define AT91C_PIOD_OWER (0xFFFFFAA0) // (PIOD) Output Write Enable Register +#define AT91C_PIOD_MDER (0xFFFFFA50) // (PIOD) Multi-driver Enable Register +#define AT91C_PIOD_IMR (0xFFFFFA48) // (PIOD) Interrupt Mask Register +#define AT91C_PIOD_IER (0xFFFFFA40) // (PIOD) Interrupt Enable Register +#define AT91C_PIOD_ODSR (0xFFFFFA38) // (PIOD) Output Data Status Register +#define AT91C_PIOD_SODR (0xFFFFFA30) // (PIOD) Set Output Data Register +#define AT91C_PIOD_PER (0xFFFFFA00) // (PIOD) PIO Enable Register +#define AT91C_PIOD_OWDR (0xFFFFFAA4) // (PIOD) Output Write Disable Register +#define AT91C_PIOD_PPUER (0xFFFFFA64) // (PIOD) Pull-up Enable Register +#define AT91C_PIOD_MDDR (0xFFFFFA54) // (PIOD) Multi-driver Disable Register +#define AT91C_PIOD_ISR (0xFFFFFA4C) // (PIOD) Interrupt Status Register +#define AT91C_PIOD_IDR (0xFFFFFA44) // (PIOD) Interrupt Disable Register +#define AT91C_PIOD_PDR (0xFFFFFA04) // (PIOD) PIO Disable Register +#define AT91C_PIOD_ODR (0xFFFFFA14) // (PIOD) Output Disable Registerr +#define AT91C_PIOD_OWSR (0xFFFFFAA8) // (PIOD) Output Write Status Register +#define AT91C_PIOD_ABSR (0xFFFFFA78) // (PIOD) AB Select Status Register +#define AT91C_PIOD_ASR (0xFFFFFA70) // (PIOD) Select A Register +#define AT91C_PIOD_PPUSR (0xFFFFFA68) // (PIOD) Pad Pull-up Status Register +#define AT91C_PIOD_PPUDR (0xFFFFFA60) // (PIOD) Pull-up Disable Register +#define AT91C_PIOD_MDSR (0xFFFFFA58) // (PIOD) Multi-driver Status Register +#define AT91C_PIOD_PSR (0xFFFFFA08) // (PIOD) PIO Status Register +#define AT91C_PIOD_OER (0xFFFFFA10) // (PIOD) Output Enable Register +#define AT91C_PIOD_OSR (0xFFFFFA18) // (PIOD) Output Status Register +#define AT91C_PIOD_IFER (0xFFFFFA20) // (PIOD) Input Filter Enable Register +#define AT91C_PIOD_BSR (0xFFFFFA74) // (PIOD) Select B Register +#define AT91C_PIOD_IFDR (0xFFFFFA24) // (PIOD) Input Filter Disable Register +#define AT91C_PIOD_IFSR (0xFFFFFA28) // (PIOD) Input Filter Status Register +// ========== Register definition for PIOC peripheral ========== +#define AT91C_PIOC_IFDR (0xFFFFF824) // (PIOC) Input Filter Disable Register +#define AT91C_PIOC_ODR (0xFFFFF814) // (PIOC) Output Disable Registerr +#define AT91C_PIOC_ABSR (0xFFFFF878) // (PIOC) AB Select Status Register +#define AT91C_PIOC_SODR (0xFFFFF830) // (PIOC) Set Output Data Register +#define AT91C_PIOC_IFSR (0xFFFFF828) // (PIOC) Input Filter Status Register +#define AT91C_PIOC_CODR (0xFFFFF834) // (PIOC) Clear Output Data Register +#define AT91C_PIOC_ODSR (0xFFFFF838) // (PIOC) Output Data Status Register +#define AT91C_PIOC_IER (0xFFFFF840) // (PIOC) Interrupt Enable Register +#define AT91C_PIOC_IMR (0xFFFFF848) // (PIOC) Interrupt Mask Register +#define AT91C_PIOC_OWDR (0xFFFFF8A4) // (PIOC) Output Write Disable Register +#define AT91C_PIOC_MDDR (0xFFFFF854) // (PIOC) Multi-driver Disable Register +#define AT91C_PIOC_PDSR (0xFFFFF83C) // (PIOC) Pin Data Status Register +#define AT91C_PIOC_IDR (0xFFFFF844) // (PIOC) Interrupt Disable Register +#define AT91C_PIOC_ISR (0xFFFFF84C) // (PIOC) Interrupt Status Register +#define AT91C_PIOC_PDR (0xFFFFF804) // (PIOC) PIO Disable Register +#define AT91C_PIOC_OWSR (0xFFFFF8A8) // (PIOC) Output Write Status Register +#define AT91C_PIOC_OWER (0xFFFFF8A0) // (PIOC) Output Write Enable Register +#define AT91C_PIOC_ASR (0xFFFFF870) // (PIOC) Select A Register +#define AT91C_PIOC_PPUSR (0xFFFFF868) // (PIOC) Pad Pull-up Status Register +#define AT91C_PIOC_PPUDR (0xFFFFF860) // (PIOC) Pull-up Disable Register +#define AT91C_PIOC_MDSR (0xFFFFF858) // (PIOC) Multi-driver Status Register +#define AT91C_PIOC_MDER (0xFFFFF850) // (PIOC) Multi-driver Enable Register +#define AT91C_PIOC_IFER (0xFFFFF820) // (PIOC) Input Filter Enable Register +#define AT91C_PIOC_OSR (0xFFFFF818) // (PIOC) Output Status Register +#define AT91C_PIOC_OER (0xFFFFF810) // (PIOC) Output Enable Register +#define AT91C_PIOC_PSR (0xFFFFF808) // (PIOC) PIO Status Register +#define AT91C_PIOC_PER (0xFFFFF800) // (PIOC) PIO Enable Register +#define AT91C_PIOC_BSR (0xFFFFF874) // (PIOC) Select B Register +#define AT91C_PIOC_PPUER (0xFFFFF864) // (PIOC) Pull-up Enable Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWSR (0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PPUSR (0xFFFFF668) // (PIOB) Pad Pull-up Status Register +#define AT91C_PIOB_PPUDR (0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_MDSR (0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_MDER (0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_IMR (0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_OSR (0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_OER (0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PSR (0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_PER (0xFFFFF600) // (PIOB) PIO Enable Register +#define AT91C_PIOB_BSR (0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_PPUER (0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_IFDR (0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_ODR (0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_ABSR (0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_ASR (0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_IFER (0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_IFSR (0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_SODR (0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ODSR (0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_CODR (0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_PDSR (0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_OWER (0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_IER (0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_OWDR (0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDDR (0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_ISR (0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_IDR (0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_PDR (0xFFFFF604) // (PIOB) PIO Disable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register +#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register +#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register +#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register +#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register +#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register +#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register +// ========== Register definition for PDC_SSC2 peripheral ========== +#define AT91C_SSC2_PTCR (0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register +#define AT91C_SSC2_TNPR (0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register +#define AT91C_SSC2_RNPR (0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register +#define AT91C_SSC2_TPR (0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register +#define AT91C_SSC2_RPR (0xFFFD8100) // (PDC_SSC2) Receive Pointer Register +#define AT91C_SSC2_PTSR (0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register +#define AT91C_SSC2_TNCR (0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register +#define AT91C_SSC2_RNCR (0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register +#define AT91C_SSC2_TCR (0xFFFD810C) // (PDC_SSC2) Transmit Counter Register +#define AT91C_SSC2_RCR (0xFFFD8104) // (PDC_SSC2) Receive Counter Register +// ========== Register definition for SSC2 peripheral ========== +#define AT91C_SSC2_IMR (0xFFFD804C) // (SSC2) Interrupt Mask Register +#define AT91C_SSC2_IER (0xFFFD8044) // (SSC2) Interrupt Enable Register +#define AT91C_SSC2_RC1R (0xFFFD803C) // (SSC2) Receive Compare 1 Register +#define AT91C_SSC2_TSHR (0xFFFD8034) // (SSC2) Transmit Sync Holding Register +#define AT91C_SSC2_CMR (0xFFFD8004) // (SSC2) Clock Mode Register +#define AT91C_SSC2_IDR (0xFFFD8048) // (SSC2) Interrupt Disable Register +#define AT91C_SSC2_TCMR (0xFFFD8018) // (SSC2) Transmit Clock Mode Register +#define AT91C_SSC2_RCMR (0xFFFD8010) // (SSC2) Receive Clock ModeRegister +#define AT91C_SSC2_CR (0xFFFD8000) // (SSC2) Control Register +#define AT91C_SSC2_RFMR (0xFFFD8014) // (SSC2) Receive Frame Mode Register +#define AT91C_SSC2_TFMR (0xFFFD801C) // (SSC2) Transmit Frame Mode Register +#define AT91C_SSC2_THR (0xFFFD8024) // (SSC2) Transmit Holding Register +#define AT91C_SSC2_SR (0xFFFD8040) // (SSC2) Status Register +#define AT91C_SSC2_RC0R (0xFFFD8038) // (SSC2) Receive Compare 0 Register +#define AT91C_SSC2_RSHR (0xFFFD8030) // (SSC2) Receive Sync Holding Register +#define AT91C_SSC2_RHR (0xFFFD8020) // (SSC2) Receive Holding Register +// ========== Register definition for PDC_SSC1 peripheral ========== +#define AT91C_SSC1_PTCR (0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register +#define AT91C_SSC1_TNPR (0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register +#define AT91C_SSC1_RNPR (0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register +#define AT91C_SSC1_TPR (0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register +#define AT91C_SSC1_RPR (0xFFFD4100) // (PDC_SSC1) Receive Pointer Register +#define AT91C_SSC1_PTSR (0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register +#define AT91C_SSC1_TNCR (0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register +#define AT91C_SSC1_RNCR (0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register +#define AT91C_SSC1_TCR (0xFFFD410C) // (PDC_SSC1) Transmit Counter Register +#define AT91C_SSC1_RCR (0xFFFD4104) // (PDC_SSC1) Receive Counter Register +// ========== Register definition for SSC1 peripheral ========== +#define AT91C_SSC1_RFMR (0xFFFD4014) // (SSC1) Receive Frame Mode Register +#define AT91C_SSC1_CMR (0xFFFD4004) // (SSC1) Clock Mode Register +#define AT91C_SSC1_IDR (0xFFFD4048) // (SSC1) Interrupt Disable Register +#define AT91C_SSC1_SR (0xFFFD4040) // (SSC1) Status Register +#define AT91C_SSC1_RC0R (0xFFFD4038) // (SSC1) Receive Compare 0 Register +#define AT91C_SSC1_RSHR (0xFFFD4030) // (SSC1) Receive Sync Holding Register +#define AT91C_SSC1_RHR (0xFFFD4020) // (SSC1) Receive Holding Register +#define AT91C_SSC1_TCMR (0xFFFD4018) // (SSC1) Transmit Clock Mode Register +#define AT91C_SSC1_RCMR (0xFFFD4010) // (SSC1) Receive Clock ModeRegister +#define AT91C_SSC1_CR (0xFFFD4000) // (SSC1) Control Register +#define AT91C_SSC1_IMR (0xFFFD404C) // (SSC1) Interrupt Mask Register +#define AT91C_SSC1_IER (0xFFFD4044) // (SSC1) Interrupt Enable Register +#define AT91C_SSC1_RC1R (0xFFFD403C) // (SSC1) Receive Compare 1 Register +#define AT91C_SSC1_TSHR (0xFFFD4034) // (SSC1) Transmit Sync Holding Register +#define AT91C_SSC1_THR (0xFFFD4024) // (SSC1) Transmit Holding Register +#define AT91C_SSC1_TFMR (0xFFFD401C) // (SSC1) Transmit Frame Mode Register +// ========== Register definition for PDC_SSC0 peripheral ========== +#define AT91C_SSC0_PTCR (0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register +#define AT91C_SSC0_TNPR (0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register +#define AT91C_SSC0_RNPR (0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register +#define AT91C_SSC0_TPR (0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register +#define AT91C_SSC0_RPR (0xFFFD0100) // (PDC_SSC0) Receive Pointer Register +#define AT91C_SSC0_PTSR (0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register +#define AT91C_SSC0_TNCR (0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register +#define AT91C_SSC0_RNCR (0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register +#define AT91C_SSC0_TCR (0xFFFD010C) // (PDC_SSC0) Transmit Counter Register +#define AT91C_SSC0_RCR (0xFFFD0104) // (PDC_SSC0) Receive Counter Register +// ========== Register definition for SSC0 peripheral ========== +#define AT91C_SSC0_IMR (0xFFFD004C) // (SSC0) Interrupt Mask Register +#define AT91C_SSC0_IER (0xFFFD0044) // (SSC0) Interrupt Enable Register +#define AT91C_SSC0_RC1R (0xFFFD003C) // (SSC0) Receive Compare 1 Register +#define AT91C_SSC0_TSHR (0xFFFD0034) // (SSC0) Transmit Sync Holding Register +#define AT91C_SSC0_THR (0xFFFD0024) // (SSC0) Transmit Holding Register +#define AT91C_SSC0_TFMR (0xFFFD001C) // (SSC0) Transmit Frame Mode Register +#define AT91C_SSC0_RFMR (0xFFFD0014) // (SSC0) Receive Frame Mode Register +#define AT91C_SSC0_CMR (0xFFFD0004) // (SSC0) Clock Mode Register +#define AT91C_SSC0_IDR (0xFFFD0048) // (SSC0) Interrupt Disable Register +#define AT91C_SSC0_SR (0xFFFD0040) // (SSC0) Status Register +#define AT91C_SSC0_RC0R (0xFFFD0038) // (SSC0) Receive Compare 0 Register +#define AT91C_SSC0_RSHR (0xFFFD0030) // (SSC0) Receive Sync Holding Register +#define AT91C_SSC0_RHR (0xFFFD0020) // (SSC0) Receive Holding Register +#define AT91C_SSC0_TCMR (0xFFFD0018) // (SSC0) Transmit Clock Mode Register +#define AT91C_SSC0_RCMR (0xFFFD0010) // (SSC0) Receive Clock ModeRegister +#define AT91C_SSC0_CR (0xFFFD0000) // (SSC0) Control Register +// ========== Register definition for PDC_US3 peripheral ========== +#define AT91C_US3_PTSR (0xFFFCC124) // (PDC_US3) PDC Transfer Status Register +#define AT91C_US3_TNCR (0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register +#define AT91C_US3_RNCR (0xFFFCC114) // (PDC_US3) Receive Next Counter Register +#define AT91C_US3_TCR (0xFFFCC10C) // (PDC_US3) Transmit Counter Register +#define AT91C_US3_RCR (0xFFFCC104) // (PDC_US3) Receive Counter Register +#define AT91C_US3_PTCR (0xFFFCC120) // (PDC_US3) PDC Transfer Control Register +#define AT91C_US3_TNPR (0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register +#define AT91C_US3_RNPR (0xFFFCC110) // (PDC_US3) Receive Next Pointer Register +#define AT91C_US3_TPR (0xFFFCC108) // (PDC_US3) Transmit Pointer Register +#define AT91C_US3_RPR (0xFFFCC100) // (PDC_US3) Receive Pointer Register +// ========== Register definition for US3 peripheral ========== +#define AT91C_US3_IF (0xFFFCC04C) // (US3) IRDA_FILTER Register +#define AT91C_US3_NER (0xFFFCC044) // (US3) Nb Errors Register +#define AT91C_US3_RTOR (0xFFFCC024) // (US3) Receiver Time-out Register +#define AT91C_US3_THR (0xFFFCC01C) // (US3) Transmitter Holding Register +#define AT91C_US3_CSR (0xFFFCC014) // (US3) Channel Status Register +#define AT91C_US3_IDR (0xFFFCC00C) // (US3) Interrupt Disable Register +#define AT91C_US3_MR (0xFFFCC004) // (US3) Mode Register +#define AT91C_US3_XXR (0xFFFCC048) // (US3) XON_XOFF Register +#define AT91C_US3_FIDI (0xFFFCC040) // (US3) FI_DI_Ratio Register +#define AT91C_US3_TTGR (0xFFFCC028) // (US3) Transmitter Time-guard Register +#define AT91C_US3_BRGR (0xFFFCC020) // (US3) Baud Rate Generator Register +#define AT91C_US3_RHR (0xFFFCC018) // (US3) Receiver Holding Register +#define AT91C_US3_IMR (0xFFFCC010) // (US3) Interrupt Mask Register +#define AT91C_US3_IER (0xFFFCC008) // (US3) Interrupt Enable Register +#define AT91C_US3_CR (0xFFFCC000) // (US3) Control Register +// ========== Register definition for PDC_US2 peripheral ========== +#define AT91C_US2_PTSR (0xFFFC8124) // (PDC_US2) PDC Transfer Status Register +#define AT91C_US2_TNCR (0xFFFC811C) // (PDC_US2) Transmit Next Counter Register +#define AT91C_US2_RNCR (0xFFFC8114) // (PDC_US2) Receive Next Counter Register +#define AT91C_US2_TCR (0xFFFC810C) // (PDC_US2) Transmit Counter Register +#define AT91C_US2_PTCR (0xFFFC8120) // (PDC_US2) PDC Transfer Control Register +#define AT91C_US2_RCR (0xFFFC8104) // (PDC_US2) Receive Counter Register +#define AT91C_US2_TNPR (0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register +#define AT91C_US2_RPR (0xFFFC8100) // (PDC_US2) Receive Pointer Register +#define AT91C_US2_TPR (0xFFFC8108) // (PDC_US2) Transmit Pointer Register +#define AT91C_US2_RNPR (0xFFFC8110) // (PDC_US2) Receive Next Pointer Register +// ========== Register definition for US2 peripheral ========== +#define AT91C_US2_XXR (0xFFFC8048) // (US2) XON_XOFF Register +#define AT91C_US2_FIDI (0xFFFC8040) // (US2) FI_DI_Ratio Register +#define AT91C_US2_TTGR (0xFFFC8028) // (US2) Transmitter Time-guard Register +#define AT91C_US2_BRGR (0xFFFC8020) // (US2) Baud Rate Generator Register +#define AT91C_US2_RHR (0xFFFC8018) // (US2) Receiver Holding Register +#define AT91C_US2_IMR (0xFFFC8010) // (US2) Interrupt Mask Register +#define AT91C_US2_IER (0xFFFC8008) // (US2) Interrupt Enable Register +#define AT91C_US2_CR (0xFFFC8000) // (US2) Control Register +#define AT91C_US2_IF (0xFFFC804C) // (US2) IRDA_FILTER Register +#define AT91C_US2_NER (0xFFFC8044) // (US2) Nb Errors Register +#define AT91C_US2_RTOR (0xFFFC8024) // (US2) Receiver Time-out Register +#define AT91C_US2_THR (0xFFFC801C) // (US2) Transmitter Holding Register +#define AT91C_US2_CSR (0xFFFC8014) // (US2) Channel Status Register +#define AT91C_US2_IDR (0xFFFC800C) // (US2) Interrupt Disable Register +#define AT91C_US2_MR (0xFFFC8004) // (US2) Mode Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register +#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register +#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register +#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register +#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register +#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register +#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register +#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register +// ========== Register definition for PDC_MCI peripheral ========== +#define AT91C_MCI_PTCR (0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register +#define AT91C_MCI_TNPR (0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register +#define AT91C_MCI_RNPR (0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register +#define AT91C_MCI_TPR (0xFFFB4108) // (PDC_MCI) Transmit Pointer Register +#define AT91C_MCI_RPR (0xFFFB4100) // (PDC_MCI) Receive Pointer Register +#define AT91C_MCI_PTSR (0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register +#define AT91C_MCI_TNCR (0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register +#define AT91C_MCI_RNCR (0xFFFB4114) // (PDC_MCI) Receive Next Counter Register +#define AT91C_MCI_TCR (0xFFFB410C) // (PDC_MCI) Transmit Counter Register +#define AT91C_MCI_RCR (0xFFFB4104) // (PDC_MCI) Receive Counter Register +// ========== Register definition for MCI peripheral ========== +#define AT91C_MCI_IDR (0xFFFB4048) // (MCI) MCI Interrupt Disable Register +#define AT91C_MCI_SR (0xFFFB4040) // (MCI) MCI Status Register +#define AT91C_MCI_RDR (0xFFFB4030) // (MCI) MCI Receive Data Register +#define AT91C_MCI_RSPR (0xFFFB4020) // (MCI) MCI Response Register +#define AT91C_MCI_ARGR (0xFFFB4010) // (MCI) MCI Argument Register +#define AT91C_MCI_DTOR (0xFFFB4008) // (MCI) MCI Data Timeout Register +#define AT91C_MCI_CR (0xFFFB4000) // (MCI) MCI Control Register +#define AT91C_MCI_IMR (0xFFFB404C) // (MCI) MCI Interrupt Mask Register +#define AT91C_MCI_IER (0xFFFB4044) // (MCI) MCI Interrupt Enable Register +#define AT91C_MCI_TDR (0xFFFB4034) // (MCI) MCI Transmit Data Register +#define AT91C_MCI_CMDR (0xFFFB4014) // (MCI) MCI Command Register +#define AT91C_MCI_SDCR (0xFFFB400C) // (MCI) MCI SD Card Register +#define AT91C_MCI_MR (0xFFFB4004) // (MCI) MCI Mode Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register +#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register +// ========== Register definition for TC5 peripheral ========== +#define AT91C_TC5_CMR (0xFFFA4084) // (TC5) Channel Mode Register +#define AT91C_TC5_IDR (0xFFFA40A8) // (TC5) Interrupt Disable Register +#define AT91C_TC5_SR (0xFFFA40A0) // (TC5) Status Register +#define AT91C_TC5_RB (0xFFFA4098) // (TC5) Register B +#define AT91C_TC5_CV (0xFFFA4090) // (TC5) Counter Value +#define AT91C_TC5_CCR (0xFFFA4080) // (TC5) Channel Control Register +#define AT91C_TC5_IMR (0xFFFA40AC) // (TC5) Interrupt Mask Register +#define AT91C_TC5_IER (0xFFFA40A4) // (TC5) Interrupt Enable Register +#define AT91C_TC5_RC (0xFFFA409C) // (TC5) Register C +#define AT91C_TC5_RA (0xFFFA4094) // (TC5) Register A +// ========== Register definition for TC4 peripheral ========== +#define AT91C_TC4_IMR (0xFFFA406C) // (TC4) Interrupt Mask Register +#define AT91C_TC4_IER (0xFFFA4064) // (TC4) Interrupt Enable Register +#define AT91C_TC4_RC (0xFFFA405C) // (TC4) Register C +#define AT91C_TC4_RA (0xFFFA4054) // (TC4) Register A +#define AT91C_TC4_CMR (0xFFFA4044) // (TC4) Channel Mode Register +#define AT91C_TC4_IDR (0xFFFA4068) // (TC4) Interrupt Disable Register +#define AT91C_TC4_SR (0xFFFA4060) // (TC4) Status Register +#define AT91C_TC4_RB (0xFFFA4058) // (TC4) Register B +#define AT91C_TC4_CV (0xFFFA4050) // (TC4) Counter Value +#define AT91C_TC4_CCR (0xFFFA4040) // (TC4) Channel Control Register +// ========== Register definition for TC3 peripheral ========== +#define AT91C_TC3_IMR (0xFFFA402C) // (TC3) Interrupt Mask Register +#define AT91C_TC3_CV (0xFFFA4010) // (TC3) Counter Value +#define AT91C_TC3_CCR (0xFFFA4000) // (TC3) Channel Control Register +#define AT91C_TC3_IER (0xFFFA4024) // (TC3) Interrupt Enable Register +#define AT91C_TC3_CMR (0xFFFA4004) // (TC3) Channel Mode Register +#define AT91C_TC3_RA (0xFFFA4014) // (TC3) Register A +#define AT91C_TC3_RC (0xFFFA401C) // (TC3) Register C +#define AT91C_TC3_IDR (0xFFFA4028) // (TC3) Interrupt Disable Register +#define AT91C_TC3_RB (0xFFFA4018) // (TC3) Register B +#define AT91C_TC3_SR (0xFFFA4020) // (TC3) Status Register +// ========== Register definition for TCB1 peripheral ========== +#define AT91C_TCB1_BCR (0xFFFA4140) // (TCB1) TC Block Control Register +#define AT91C_TCB1_BMR (0xFFFA4144) // (TCB1) TC Block Mode Register +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register +#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register +#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register +#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value +#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register +#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register +#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register +// ========== Register definition for TCB0 peripheral ========== +#define AT91C_TCB0_BMR (0xFFFA00C4) // (TCB0) TC Block Mode Register +#define AT91C_TCB0_BCR (0xFFFA00C0) // (TCB0) TC Block Control Register +// ========== Register definition for UHP peripheral ========== +#define AT91C_UHP_HcRhDescriptorA (0x00300048) // (UHP) Root Hub characteristics A +#define AT91C_UHP_HcRhPortStatus (0x00300054) // (UHP) Root Hub Port Status Register +#define AT91C_UHP_HcRhDescriptorB (0x0030004C) // (UHP) Root Hub characteristics B +#define AT91C_UHP_HcControl (0x00300004) // (UHP) Operating modes for the Host Controller +#define AT91C_UHP_HcInterruptStatus (0x0030000C) // (UHP) Interrupt Status Register +#define AT91C_UHP_HcRhStatus (0x00300050) // (UHP) Root Hub Status register +#define AT91C_UHP_HcRevision (0x00300000) // (UHP) Revision +#define AT91C_UHP_HcCommandStatus (0x00300008) // (UHP) Command & status Register +#define AT91C_UHP_HcInterruptEnable (0x00300010) // (UHP) Interrupt Enable Register +#define AT91C_UHP_HcHCCA (0x00300018) // (UHP) Pointer to the Host Controller Communication Area +#define AT91C_UHP_HcControlHeadED (0x00300020) // (UHP) First Endpoint Descriptor of the Control list +#define AT91C_UHP_HcInterruptDisable (0x00300014) // (UHP) Interrupt Disable Register +#define AT91C_UHP_HcPeriodCurrentED (0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor +#define AT91C_UHP_HcControlCurrentED (0x00300024) // (UHP) Endpoint Control and Status Register +#define AT91C_UHP_HcBulkCurrentED (0x0030002C) // (UHP) Current endpoint of the Bulk list +#define AT91C_UHP_HcFmInterval (0x00300034) // (UHP) Bit time between 2 consecutive SOFs +#define AT91C_UHP_HcBulkHeadED (0x00300028) // (UHP) First endpoint register of the Bulk list +#define AT91C_UHP_HcBulkDoneHead (0x00300030) // (UHP) Last completed transfer descriptor +#define AT91C_UHP_HcFmRemaining (0x00300038) // (UHP) Bit time remaining in the current Frame +#define AT91C_UHP_HcPeriodicStart (0x00300040) // (UHP) Periodic Start +#define AT91C_UHP_HcLSThreshold (0x00300044) // (UHP) LS Threshold +#define AT91C_UHP_HcFmNumber (0x0030003C) // (UHP) Frame number +// ========== Register definition for EMAC peripheral ========== +#define AT91C_EMAC_RSR (0xFFFBC020) // (EMAC) Receive Status Register +#define AT91C_EMAC_MAN (0xFFFBC034) // (EMAC) PHY Maintenance Register +#define AT91C_EMAC_HSH (0xFFFBC090) // (EMAC) Hash Address High[63:32] +#define AT91C_EMAC_MCOL (0xFFFBC048) // (EMAC) Multiple Collision Frame Register +#define AT91C_EMAC_IER (0xFFFBC028) // (EMAC) Interrupt Enable Register +#define AT91C_EMAC_SA2H (0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes +#define AT91C_EMAC_HSL (0xFFFBC094) // (EMAC) Hash Address Low[31:0] +#define AT91C_EMAC_LCOL (0xFFFBC05C) // (EMAC) Late Collision Register +#define AT91C_EMAC_OK (0xFFFBC04C) // (EMAC) Frames Received OK Register +#define AT91C_EMAC_CFG (0xFFFBC004) // (EMAC) Network Configuration Register +#define AT91C_EMAC_SA3L (0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes +#define AT91C_EMAC_SEQE (0xFFFBC050) // (EMAC) Frame Check Sequence Error Register +#define AT91C_EMAC_ECOL (0xFFFBC060) // (EMAC) Excessive Collision Register +#define AT91C_EMAC_ELR (0xFFFBC070) // (EMAC) Excessive Length Error Register +#define AT91C_EMAC_SR (0xFFFBC008) // (EMAC) Network Status Register +#define AT91C_EMAC_RBQP (0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer +#define AT91C_EMAC_CSE (0xFFFBC064) // (EMAC) Carrier Sense Error Register +#define AT91C_EMAC_RJB (0xFFFBC074) // (EMAC) Receive Jabber Register +#define AT91C_EMAC_USF (0xFFFBC078) // (EMAC) Undersize Frame Register +#define AT91C_EMAC_IDR (0xFFFBC02C) // (EMAC) Interrupt Disable Register +#define AT91C_EMAC_SA1L (0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes +#define AT91C_EMAC_IMR (0xFFFBC030) // (EMAC) Interrupt Mask Register +#define AT91C_EMAC_FRA (0xFFFBC040) // (EMAC) Frames Transmitted OK Register +#define AT91C_EMAC_SA3H (0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes +#define AT91C_EMAC_SA1H (0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes +#define AT91C_EMAC_SCOL (0xFFFBC044) // (EMAC) Single Collision Frame Register +#define AT91C_EMAC_ALE (0xFFFBC054) // (EMAC) Alignment Error Register +#define AT91C_EMAC_TAR (0xFFFBC00C) // (EMAC) Transmit Address Register +#define AT91C_EMAC_SA4L (0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes +#define AT91C_EMAC_SA2L (0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes +#define AT91C_EMAC_TUE (0xFFFBC068) // (EMAC) Transmit Underrun Error Register +#define AT91C_EMAC_DTE (0xFFFBC058) // (EMAC) Deferred Transmission Frame Register +#define AT91C_EMAC_TCR (0xFFFBC010) // (EMAC) Transmit Control Register +#define AT91C_EMAC_CTL (0xFFFBC000) // (EMAC) Network Control Register +#define AT91C_EMAC_SA4H (0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr +#define AT91C_EMAC_CDE (0xFFFBC06C) // (EMAC) Code Error Register +#define AT91C_EMAC_SQEE (0xFFFBC07C) // (EMAC) SQE Test Error Register +#define AT91C_EMAC_TSR (0xFFFBC014) // (EMAC) Transmit Status Register +#define AT91C_EMAC_DRFC (0xFFFBC080) // (EMAC) Discarded RX Frame Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_CFGR (0xFFFFFF64) // (EBI) Configuration Register +#define AT91C_EBI_CSA (0xFFFFFF60) // (EBI) Chip Select Assignment Register +// ========== Register definition for SMC2 peripheral ========== +#define AT91C_SMC2_CSR (0xFFFFFF70) // (SMC2) SMC2 Chip Select Register +// ========== Register definition for SDRC peripheral ========== +#define AT91C_SDRC_IMR (0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRC_IER (0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register +#define AT91C_SDRC_SRR (0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register +#define AT91C_SDRC_TR (0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register +#define AT91C_SDRC_ISR (0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRC_IDR (0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register +#define AT91C_SDRC_LPR (0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register +#define AT91C_SDRC_CR (0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register +#define AT91C_SDRC_MR (0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register +// ========== Register definition for BFC peripheral ========== +#define AT91C_BFC_MR (0xFFFFFFC0) // (BFC) BFC Mode Register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91RM9200 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_MISO (AT91C_PIO_PA0) // SPI Master In Slave +#define AT91C_PA0_PCK3 (AT91C_PIO_PA0) // PMC Programmable Clock Output 3 +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_MOSI (AT91C_PIO_PA1) // SPI Master Out Slave +#define AT91C_PA1_PCK0 (AT91C_PIO_PA1) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_ETX1 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 1 +#define AT91C_PA10_MCDB1 (AT91C_PIO_PA10) // Multimedia Card B Data 1 +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_ECRS_ECRSDV (AT91C_PIO_PA11) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid +#define AT91C_PA11_MCDB2 (AT91C_PIO_PA11) // Multimedia Card B Data 2 +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_ERX0 (AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 +#define AT91C_PA12_MCDB3 (AT91C_PIO_PA12) // Multimedia Card B Data 3 +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_ERX1 (AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 +#define AT91C_PA13_TCLK0 (AT91C_PIO_PA13) // Timer Counter 0 external clock input +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_ERXER (AT91C_PIO_PA14) // Ethernet MAC Receive Error +#define AT91C_PA14_TCLK1 (AT91C_PIO_PA14) // Timer Counter 1 external clock input +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_EMDC (AT91C_PIO_PA15) // Ethernet MAC Management Data Clock +#define AT91C_PA15_TCLK2 (AT91C_PIO_PA15) // Timer Counter 2 external clock input +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_EMDIO (AT91C_PIO_PA16) // Ethernet MAC Management Data Input/Output +#define AT91C_PA16_IRQ6 (AT91C_PIO_PA16) // AIC Interrupt input 6 +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TXD0 (AT91C_PIO_PA17) // USART 0 Transmit Data +#define AT91C_PA17_TIOA0 (AT91C_PIO_PA17) // Timer Counter 0 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RXD0 (AT91C_PIO_PA18) // USART 0 Receive Data +#define AT91C_PA18_TIOB0 (AT91C_PIO_PA18) // Timer Counter 0 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_SCK0 (AT91C_PIO_PA19) // USART 0 Serial Clock +#define AT91C_PA19_TIOA1 (AT91C_PIO_PA19) // Timer Counter 1 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SPCK (AT91C_PIO_PA2) // SPI Serial Clock +#define AT91C_PA2_IRQ4 (AT91C_PIO_PA2) // AIC Interrupt Input 4 +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_CTS0 (AT91C_PIO_PA20) // USART 0 Clear To Send +#define AT91C_PA20_TIOB1 (AT91C_PIO_PA20) // Timer Counter 1 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RTS0 (AT91C_PIO_PA21) // Usart 0 Ready To Send +#define AT91C_PA21_TIOA2 (AT91C_PIO_PA21) // Timer Counter 2 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_RXD2 (AT91C_PIO_PA22) // USART 2 Receive Data +#define AT91C_PA22_TIOB2 (AT91C_PIO_PA22) // Timer Counter 2 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_TXD2 (AT91C_PIO_PA23) // USART 2 Transmit Data +#define AT91C_PA23_IRQ3 (AT91C_PIO_PA23) // Interrupt input 3 +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_SCK2 (AT91C_PIO_PA24) // USART2 Serial Clock +#define AT91C_PA24_PCK1 (AT91C_PIO_PA24) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_TWD (AT91C_PIO_PA25) // TWI Two-wire Serial Data +#define AT91C_PA25_IRQ2 (AT91C_PIO_PA25) // Interrupt input 2 +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_TWCK (AT91C_PIO_PA26) // TWI Two-wire Serial Clock +#define AT91C_PA26_IRQ1 (AT91C_PIO_PA26) // Interrupt input 1 +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_MCCK (AT91C_PIO_PA27) // Multimedia Card Clock +#define AT91C_PA27_TCLK3 (AT91C_PIO_PA27) // Timer Counter 3 External Clock Input +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_MCCDA (AT91C_PIO_PA28) // Multimedia Card A Command +#define AT91C_PA28_TCLK4 (AT91C_PIO_PA28) // Timer Counter 4 external Clock Input +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_MCDA0 (AT91C_PIO_PA29) // Multimedia Card A Data 0 +#define AT91C_PA29_TCLK5 (AT91C_PIO_PA29) // Timer Counter 5 external clock input +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_NPCS0 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 0 +#define AT91C_PA3_IRQ5 (AT91C_PIO_PA3) // AIC Interrupt Input 5 +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_DRXD (AT91C_PIO_PA30) // DBGU Debug Receive Data +#define AT91C_PA30_CTS2 (AT91C_PIO_PA30) // Usart 2 Clear To Send +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_DTXD (AT91C_PIO_PA31) // DBGU Debug Transmit Data +#define AT91C_PA31_RTS2 (AT91C_PIO_PA31) // USART 2 Ready To Send +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_NPCS1 (AT91C_PIO_PA4) // SPI Peripheral Chip Select 1 +#define AT91C_PA4_PCK1 (AT91C_PIO_PA4) // PMC Programmable Clock Output 1 +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_NPCS2 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 2 +#define AT91C_PA5_TXD3 (AT91C_PIO_PA5) // USART 3 Transmit Data +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_NPCS3 (AT91C_PIO_PA6) // SPI Peripheral Chip Select 3 +#define AT91C_PA6_RXD3 (AT91C_PIO_PA6) // USART 3 Receive Data +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_ETXCK_EREFCK (AT91C_PIO_PA7) // Ethernet MAC Transmit Clock/Reference Clock +#define AT91C_PA7_PCK2 (AT91C_PIO_PA7) // PMC Programmable Clock 2 +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_ETXEN (AT91C_PIO_PA8) // Ethernet MAC Transmit Enable +#define AT91C_PA8_MCCDB (AT91C_PIO_PA8) // Multimedia Card B Command +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_ETX0 (AT91C_PIO_PA9) // Ethernet MAC Transmit Data 0 +#define AT91C_PA9_MCDB0 (AT91C_PIO_PA9) // Multimedia Card B Data 0 +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_TF0 (AT91C_PIO_PB0) // SSC Transmit Frame Sync 0 +#define AT91C_PB0_TIOB3 (AT91C_PIO_PB0) // Timer Counter 3 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_TK0 (AT91C_PIO_PB1) // SSC Transmit Clock 0 +#define AT91C_PB1_CTS3 (AT91C_PIO_PB1) // USART 3 Clear To Send +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_RK1 (AT91C_PIO_PB10) // SSC Receive Clock 1 +#define AT91C_PB10_TIOA5 (AT91C_PIO_PB10) // Timer Counter 5 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_RF1 (AT91C_PIO_PB11) // SSC Receive Frame Sync 1 +#define AT91C_PB11_TIOB5 (AT91C_PIO_PB11) // Timer Counter 5 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_TF2 (AT91C_PIO_PB12) // SSC Transmit Frame Sync 2 +#define AT91C_PB12_ETX2 (AT91C_PIO_PB12) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_TK2 (AT91C_PIO_PB13) // SSC Transmit Clock 2 +#define AT91C_PB13_ETX3 (AT91C_PIO_PB13) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_TD2 (AT91C_PIO_PB14) // SSC Transmit Data 2 +#define AT91C_PB14_ETXER (AT91C_PIO_PB14) // Ethernet MAC Transmikt Coding Error +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_RD2 (AT91C_PIO_PB15) // SSC Receive Data 2 +#define AT91C_PB15_ERX2 (AT91C_PIO_PB15) // Ethernet MAC Receive Data 2 +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_RK2 (AT91C_PIO_PB16) // SSC Receive Clock 2 +#define AT91C_PB16_ERX3 (AT91C_PIO_PB16) // Ethernet MAC Receive Data 3 +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_RF2 (AT91C_PIO_PB17) // SSC Receive Frame Sync 2 +#define AT91C_PB17_ERXDV (AT91C_PIO_PB17) // Ethernet MAC Receive Data Valid +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_RI1 (AT91C_PIO_PB18) // USART 1 Ring Indicator +#define AT91C_PB18_ECOL (AT91C_PIO_PB18) // Ethernet MAC Collision Detected +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_DTR1 (AT91C_PIO_PB19) // USART 1 Data Terminal ready +#define AT91C_PB19_ERXCK (AT91C_PIO_PB19) // Ethernet MAC Receive Clock +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_TD0 (AT91C_PIO_PB2) // SSC Transmit data +#define AT91C_PB2_SCK3 (AT91C_PIO_PB2) // USART 3 Serial Clock +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_TXD1 (AT91C_PIO_PB20) // USART 1 Transmit Data +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_RXD1 (AT91C_PIO_PB21) // USART 1 Receive Data +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_SCK1 (AT91C_PIO_PB22) // USART1 Serial Clock +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_CTS1 (AT91C_PIO_PB24) // USART 1 Clear To Send +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_DSR1 (AT91C_PIO_PB25) // USART 1 Data Set ready +#define AT91C_PB25_EF100 (AT91C_PIO_PB25) // Ethernet MAC Force 100 Mbits/sec +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_RTS1 (AT91C_PIO_PB26) // Usart 0 Ready To Send +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_PCK0 (AT91C_PIO_PB27) // PMC Programmable Clock Output 0 +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_FIQ (AT91C_PIO_PB28) // AIC Fast Interrupt Input +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_IRQ0 (AT91C_PIO_PB29) // Interrupt input 0 +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_RD0 (AT91C_PIO_PB3) // SSC Receive Data +#define AT91C_PB3_MCDA1 (AT91C_PIO_PB3) // Multimedia Card A Data 1 +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_RK0 (AT91C_PIO_PB4) // SSC Receive Clock +#define AT91C_PB4_MCDA2 (AT91C_PIO_PB4) // Multimedia Card A Data 2 +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_RF0 (AT91C_PIO_PB5) // SSC Receive Frame Sync 0 +#define AT91C_PB5_MCDA3 (AT91C_PIO_PB5) // Multimedia Card A Data 3 +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_TF1 (AT91C_PIO_PB6) // SSC Transmit Frame Sync 1 +#define AT91C_PB6_TIOA3 (AT91C_PIO_PB6) // Timer Counter 4 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_TK1 (AT91C_PIO_PB7) // SSC Transmit Clock 1 +#define AT91C_PB7_TIOB3 (AT91C_PIO_PB7) // Timer Counter 3 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_TD1 (AT91C_PIO_PB8) // SSC Transmit Data 1 +#define AT91C_PB8_TIOA4 (AT91C_PIO_PB8) // Timer Counter 4 Multipurpose Timer I/O Pin A +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_RD1 (AT91C_PIO_PB9) // SSC Receive Data 1 +#define AT91C_PB9_TIOB4 (AT91C_PIO_PB9) // Timer Counter 4 Multipurpose Timer I/O Pin B +#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 +#define AT91C_PC0_BFCK (AT91C_PIO_PC0) // Burst Flash Clock +#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 +#define AT91C_PC1_BFRDY_SMOE (AT91C_PIO_PC1) // Burst Flash Ready +#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 +#define AT91C_PC10_NCS4_CFCS (AT91C_PIO_PC10) // Compact Flash Chip Select +#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 +#define AT91C_PC11_NCS5_CFCE1 (AT91C_PIO_PC11) // Chip Select 5 / Compact Flash Chip Enable 1 +#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 +#define AT91C_PC12_NCS6_CFCE2 (AT91C_PIO_PC12) // Chip Select 6 / Compact Flash Chip Enable 2 +#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 +#define AT91C_PC13_NCS7 (AT91C_PIO_PC13) // Chip Select 7 +#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 +#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 +#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 +#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus [16] +#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 +#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus [17] +#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 +#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus [18] +#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 +#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus [19] +#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 +#define AT91C_PC2_BFAVD (AT91C_PIO_PC2) // Burst Flash Address Valid +#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 +#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus [20] +#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 +#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus [21] +#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 +#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus [22] +#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 +#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus [23] +#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24 +#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus [24] +#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25 +#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus [25] +#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26 +#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus [26] +#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27 +#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus [27] +#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28 +#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus [28] +#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29 +#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus [29] +#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 +#define AT91C_PC3_BFBAA_SMWE (AT91C_PIO_PC3) // Burst Flash Address Advance / SmartMedia Write Enable +#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30 +#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus [30] +#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31 +#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus [31] +#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 +#define AT91C_PC4_BFOE (AT91C_PIO_PC4) // Burst Flash Output Enable +#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 +#define AT91C_PC5_BFWE (AT91C_PIO_PC5) // Burst Flash Write Enable +#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 +#define AT91C_PC6_NWAIT (AT91C_PIO_PC6) // NWAIT +#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 +#define AT91C_PC7_A23 (AT91C_PIO_PC7) // Address Bus[23] +#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 +#define AT91C_PC8_A24 (AT91C_PIO_PC8) // Address Bus[24] +#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 +#define AT91C_PC9_A25_CFRNW (AT91C_PIO_PC9) // Address Bus[25] / Compact Flash Read Not Write +#define AT91C_PIO_PD0 (1 << 0) // Pin Controlled by PD0 +#define AT91C_PD0_ETX0 (AT91C_PIO_PD0) // Ethernet MAC Transmit Data 0 +#define AT91C_PIO_PD1 (1 << 1) // Pin Controlled by PD1 +#define AT91C_PD1_ETX1 (AT91C_PIO_PD1) // Ethernet MAC Transmit Data 1 +#define AT91C_PIO_PD10 (1 << 10) // Pin Controlled by PD10 +#define AT91C_PD10_PCK3 (AT91C_PIO_PD10) // PMC Programmable Clock Output 3 +#define AT91C_PD10_TPS1 (AT91C_PIO_PD10) // ETM ARM9 pipeline status 1 +#define AT91C_PIO_PD11 (1 << 11) // Pin Controlled by PD11 +#define AT91C_PD11_ (AT91C_PIO_PD11) // +#define AT91C_PD11_TPS2 (AT91C_PIO_PD11) // ETM ARM9 pipeline status 2 +#define AT91C_PIO_PD12 (1 << 12) // Pin Controlled by PD12 +#define AT91C_PD12_ (AT91C_PIO_PD12) // +#define AT91C_PD12_TPK0 (AT91C_PIO_PD12) // ETM Trace Packet 0 +#define AT91C_PIO_PD13 (1 << 13) // Pin Controlled by PD13 +#define AT91C_PD13_ (AT91C_PIO_PD13) // +#define AT91C_PD13_TPK1 (AT91C_PIO_PD13) // ETM Trace Packet 1 +#define AT91C_PIO_PD14 (1 << 14) // Pin Controlled by PD14 +#define AT91C_PD14_ (AT91C_PIO_PD14) // +#define AT91C_PD14_TPK2 (AT91C_PIO_PD14) // ETM Trace Packet 2 +#define AT91C_PIO_PD15 (1 << 15) // Pin Controlled by PD15 +#define AT91C_PD15_TD0 (AT91C_PIO_PD15) // SSC Transmit data +#define AT91C_PD15_TPK3 (AT91C_PIO_PD15) // ETM Trace Packet 3 +#define AT91C_PIO_PD16 (1 << 16) // Pin Controlled by PD16 +#define AT91C_PD16_TD1 (AT91C_PIO_PD16) // SSC Transmit Data 1 +#define AT91C_PD16_TPK4 (AT91C_PIO_PD16) // ETM Trace Packet 4 +#define AT91C_PIO_PD17 (1 << 17) // Pin Controlled by PD17 +#define AT91C_PD17_TD2 (AT91C_PIO_PD17) // SSC Transmit Data 2 +#define AT91C_PD17_TPK5 (AT91C_PIO_PD17) // ETM Trace Packet 5 +#define AT91C_PIO_PD18 (1 << 18) // Pin Controlled by PD18 +#define AT91C_PD18_NPCS1 (AT91C_PIO_PD18) // SPI Peripheral Chip Select 1 +#define AT91C_PD18_TPK6 (AT91C_PIO_PD18) // ETM Trace Packet 6 +#define AT91C_PIO_PD19 (1 << 19) // Pin Controlled by PD19 +#define AT91C_PD19_NPCS2 (AT91C_PIO_PD19) // SPI Peripheral Chip Select 2 +#define AT91C_PD19_TPK7 (AT91C_PIO_PD19) // ETM Trace Packet 7 +#define AT91C_PIO_PD2 (1 << 2) // Pin Controlled by PD2 +#define AT91C_PD2_ETX2 (AT91C_PIO_PD2) // Ethernet MAC Transmit Data 2 +#define AT91C_PIO_PD20 (1 << 20) // Pin Controlled by PD20 +#define AT91C_PD20_NPCS3 (AT91C_PIO_PD20) // SPI Peripheral Chip Select 3 +#define AT91C_PD20_TPK8 (AT91C_PIO_PD20) // ETM Trace Packet 8 +#define AT91C_PIO_PD21 (1 << 21) // Pin Controlled by PD21 +#define AT91C_PD21_RTS0 (AT91C_PIO_PD21) // Usart 0 Ready To Send +#define AT91C_PD21_TPK9 (AT91C_PIO_PD21) // ETM Trace Packet 9 +#define AT91C_PIO_PD22 (1 << 22) // Pin Controlled by PD22 +#define AT91C_PD22_RTS1 (AT91C_PIO_PD22) // Usart 0 Ready To Send +#define AT91C_PD22_TPK10 (AT91C_PIO_PD22) // ETM Trace Packet 10 +#define AT91C_PIO_PD23 (1 << 23) // Pin Controlled by PD23 +#define AT91C_PD23_RTS2 (AT91C_PIO_PD23) // USART 2 Ready To Send +#define AT91C_PD23_TPK11 (AT91C_PIO_PD23) // ETM Trace Packet 11 +#define AT91C_PIO_PD24 (1 << 24) // Pin Controlled by PD24 +#define AT91C_PD24_RTS3 (AT91C_PIO_PD24) // USART 3 Ready To Send +#define AT91C_PD24_TPK12 (AT91C_PIO_PD24) // ETM Trace Packet 12 +#define AT91C_PIO_PD25 (1 << 25) // Pin Controlled by PD25 +#define AT91C_PD25_DTR1 (AT91C_PIO_PD25) // USART 1 Data Terminal ready +#define AT91C_PD25_TPK13 (AT91C_PIO_PD25) // ETM Trace Packet 13 +#define AT91C_PIO_PD26 (1 << 26) // Pin Controlled by PD26 +#define AT91C_PD26_TPK14 (AT91C_PIO_PD26) // ETM Trace Packet 14 +#define AT91C_PIO_PD27 (1 << 27) // Pin Controlled by PD27 +#define AT91C_PD27_TPK15 (AT91C_PIO_PD27) // ETM Trace Packet 15 +#define AT91C_PIO_PD3 (1 << 3) // Pin Controlled by PD3 +#define AT91C_PD3_ETX3 (AT91C_PIO_PD3) // Ethernet MAC Transmit Data 3 +#define AT91C_PIO_PD4 (1 << 4) // Pin Controlled by PD4 +#define AT91C_PD4_ETXEN (AT91C_PIO_PD4) // Ethernet MAC Transmit Enable +#define AT91C_PIO_PD5 (1 << 5) // Pin Controlled by PD5 +#define AT91C_PD5_ETXER (AT91C_PIO_PD5) // Ethernet MAC Transmikt Coding Error +#define AT91C_PIO_PD6 (1 << 6) // Pin Controlled by PD6 +#define AT91C_PD6_DTXD (AT91C_PIO_PD6) // DBGU Debug Transmit Data +#define AT91C_PIO_PD7 (1 << 7) // Pin Controlled by PD7 +#define AT91C_PD7_PCK0 (AT91C_PIO_PD7) // PMC Programmable Clock Output 0 +#define AT91C_PD7_TSYNC (AT91C_PIO_PD7) // ETM Synchronization signal +#define AT91C_PIO_PD8 (1 << 8) // Pin Controlled by PD8 +#define AT91C_PD8_PCK1 (AT91C_PIO_PD8) // PMC Programmable Clock Output 1 +#define AT91C_PD8_TCLK (AT91C_PIO_PD8) // ETM Trace Clock signal +#define AT91C_PIO_PD9 (1 << 9) // Pin Controlled by PD9 +#define AT91C_PD9_PCK2 (AT91C_PIO_PD9) // PMC Programmable Clock 2 +#define AT91C_PD9_TPS0 (AT91C_PIO_PD9) // ETM ARM9 pipeline status 0 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91RM9200 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C +#define AT91C_ID_PIOD ( 5) // Parallel IO Controller D +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_US2 ( 8) // USART 2 +#define AT91C_ID_US3 ( 9) // USART 3 +#define AT91C_ID_MCI (10) // Multimedia Card Interface +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TWI (12) // Two-Wire Interface +#define AT91C_ID_SPI (13) // Serial Peripheral Interface +#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0 +#define AT91C_ID_SSC1 (15) // Serial Synchronous Controller 1 +#define AT91C_ID_SSC2 (16) // Serial Synchronous Controller 2 +#define AT91C_ID_TC0 (17) // Timer Counter 0 +#define AT91C_ID_TC1 (18) // Timer Counter 1 +#define AT91C_ID_TC2 (19) // Timer Counter 2 +#define AT91C_ID_TC3 (20) // Timer Counter 3 +#define AT91C_ID_TC4 (21) // Timer Counter 4 +#define AT91C_ID_TC5 (22) // Timer Counter 5 +#define AT91C_ID_UHP (23) // USB Host port +#define AT91C_ID_EMAC (24) // Ethernet MAC +#define AT91C_ID_IRQ0 (25) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (26) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_IRQ2 (27) // Advanced Interrupt Controller (IRQ2) +#define AT91C_ID_IRQ3 (28) // Advanced Interrupt Controller (IRQ3) +#define AT91C_ID_IRQ4 (29) // Advanced Interrupt Controller (IRQ4) +#define AT91C_ID_IRQ5 (30) // Advanced Interrupt Controller (IRQ5) +#define AT91C_ID_IRQ6 (31) // Advanced Interrupt Controller (IRQ6) + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91RM9200 +// ***************************************************************************** +#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_RTC (0xFFFFFE00) // (RTC) Base Address +#define AT91C_BASE_ST (0xFFFFFD00) // (ST) Base Address +#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PIOD (0xFFFFFA00) // (PIOD) Base Address +#define AT91C_BASE_PIOC (0xFFFFF800) // (PIOC) Base Address +#define AT91C_BASE_PIOB (0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_SSC2 (0xFFFD8100) // (PDC_SSC2) Base Address +#define AT91C_BASE_SSC2 (0xFFFD8000) // (SSC2) Base Address +#define AT91C_BASE_PDC_SSC1 (0xFFFD4100) // (PDC_SSC1) Base Address +#define AT91C_BASE_SSC1 (0xFFFD4000) // (SSC1) Base Address +#define AT91C_BASE_PDC_SSC0 (0xFFFD0100) // (PDC_SSC0) Base Address +#define AT91C_BASE_SSC0 (0xFFFD0000) // (SSC0) Base Address +#define AT91C_BASE_PDC_US3 (0xFFFCC100) // (PDC_US3) Base Address +#define AT91C_BASE_US3 (0xFFFCC000) // (US3) Base Address +#define AT91C_BASE_PDC_US2 (0xFFFC8100) // (PDC_US2) Base Address +#define AT91C_BASE_US2 (0xFFFC8000) // (US2) Base Address +#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PDC_MCI (0xFFFB4100) // (PDC_MCI) Base Address +#define AT91C_BASE_MCI (0xFFFB4000) // (MCI) Base Address +#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC5 (0xFFFA4080) // (TC5) Base Address +#define AT91C_BASE_TC4 (0xFFFA4040) // (TC4) Base Address +#define AT91C_BASE_TC3 (0xFFFA4000) // (TC3) Base Address +#define AT91C_BASE_TCB1 (0xFFFA4080) // (TCB1) Base Address +#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TCB0 (0xFFFA0000) // (TCB0) Base Address +#define AT91C_BASE_UHP (0x00300000) // (UHP) Base Address +#define AT91C_BASE_EMAC (0xFFFBC000) // (EMAC) Base Address +#define AT91C_BASE_EBI (0xFFFFFF60) // (EBI) Base Address +#define AT91C_BASE_SMC2 (0xFFFFFF70) // (SMC2) Base Address +#define AT91C_BASE_SDRC (0xFFFFFF90) // (SDRC) Base Address +#define AT91C_BASE_BFC (0xFFFFFFC0) // (BFC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91RM9200 +// ***************************************************************************** +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte) +#define AT91C_IROM (0x00100000) // Internal ROM base address +#define AT91C_IROM_SIZE (0x00020000) // Internal ROM size in byte (128 Kbyte) + + diff --git a/target/linux/at91/image/dfboot/src/include/led.h b/target/linux/at91/image/dfboot/src/include/led.h new file mode 100644 index 0000000..9bebd9c --- /dev/null +++ b/target/linux/at91/image/dfboot/src/include/led.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2006 + * Atmel Nordic AB + * Ulf Samuelsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + #ifndef __LED_H +#define __LED_H + +#ifndef __ASSEMBLY__ +extern void LED_init (void); +extern void LED_set(unsigned int led); +extern void red_LED_on(void); +extern void red_LED_off(void); +extern void green_LED_on(void); +extern void green_LED_off(void); +extern void yellow_LED_on(void); +extern void yellow_LED_off(void); +extern void LED_blink(unsigned int led); +#else + .extern LED_init + .extern LED_set + .extern LED_blink + .extern red_LED_on + .extern red_LED_off + .extern yellow_LED_on + .extern yellow_LED_off + .extern green_LED_on + .extern green_LED_off +#endif +#endif diff --git a/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h b/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h new file mode 100644 index 0000000..c322b32 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h @@ -0,0 +1,2978 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : lib_AT91RM9200.h +//* Object : AT91RM9200 inlined functions +//* Generated : AT91 SW Application Group 11/19/2003 (17:20:51) +//* +//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 02 12:29:40 2002// +//* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003// +//* CVS Reference : /lib_rtc_1245d.h/1.1/Fri Jan 31 12:19:12 2003// +//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// +//* CVS Reference : /lib_spi_AT91RMxxxx.h/1.2/Fri Jan 31 12:19:31 2003// +//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// +//* CVS Reference : /lib_pmc.h/1.3/Thu Nov 14 07:40:45 2002// +//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// +//* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003// +//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:53 2002// +//* CVS Reference : /lib_mci.h/1.2/Wed Nov 20 14:18:55 2002// +//* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:11 2002// +//* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003// +//* CVS Reference : /lib_st.h/1.4/Fri Jan 31 12:20:13 2003// +//*---------------------------------------------------------------------------- + +#ifndef lib_AT91RM9200_H +#define lib_AT91RM9200_H + +/* ***************************************************************************** + SOFTWARE API FOR PDC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextRx +//* \brief Set the next receive transfer descriptor +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_SetNextRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RNPR = (unsigned int) address; + pPDC->PDC_RNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetNextTx +//* \brief Set the next transmit transfer descriptor +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_SetNextTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TNPR = (unsigned int) address; + pPDC->PDC_TNCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetRx +//* \brief Set the receive transfer descriptor +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_SetRx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be received + unsigned int bytes) // \arg number of bytes to be received +{ + pPDC->PDC_RPR = (unsigned int) address; + pPDC->PDC_RCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SetTx +//* \brief Set the transmit transfer descriptor +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_SetTx ( + AT91PS_PDC pPDC, // \arg pointer to a PDC controller + char *address, // \arg address to the next bloc to be transmitted + unsigned int bytes) // \arg number of bytes to be transmitted +{ + pPDC->PDC_TPR = (unsigned int) address; + pPDC->PDC_TCR = bytes; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableTx +//* \brief Enable transmit +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_EnableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_EnableRx +//* \brief Enable receive +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_EnableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableTx +//* \brief Disable transmit +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_DisableTx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_DisableRx +//* \brief Disable receive +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_DisableRx ( + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsTxEmpty +//* \brief Test if the current transfer descriptor has been sent +//*---------------------------------------------------------------------------- +static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextTxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_TNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsRxEmpty +//* \brief Test if the current transfer descriptor has been filled +//*---------------------------------------------------------------------------- +static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_IsNextRxEmpty +//* \brief Test if the next transfer descriptor has been moved to the current td +//*---------------------------------------------------------------------------- +static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete + AT91PS_PDC pPDC ) // \arg pointer to a PDC controller +{ + return !(pPDC->PDC_RNCR); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Open +//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_Open ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + + //* Enable the RX and TX PDC transfer requests + AT91F_PDC_EnableRx(pPDC); + AT91F_PDC_EnableTx(pPDC); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_Close +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +static inline void AT91F_PDC_Close ( + AT91PS_PDC pPDC) // \arg pointer to a PDC controller +{ + //* Disable the RX and TX PDC transfer requests + AT91F_PDC_DisableRx(pPDC); + AT91F_PDC_DisableTx(pPDC); + + //* Reset all Counter register Next buffer first + AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); + AT91F_PDC_SetTx(pPDC, (char *) 0, 0); + AT91F_PDC_SetRx(pPDC, (char *) 0, 0); + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_SendFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PDC_SendFrame( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsTxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PDC_ReceiveFrame +//* \brief Close PDC: disable TX and RX reset transfer descriptors +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PDC_ReceiveFrame ( + AT91PS_PDC pPDC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + if (AT91F_PDC_IsRxEmpty(pPDC)) { + //* Buffer and next buffer can be initialized + AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); + AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); + return 2; + } + else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { + //* Only one buffer can be initialized + AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); + return 1; + } + else { + //* All buffer are in use... + return 0; + } +} +/* ***************************************************************************** + SOFTWARE API FOR DBGU + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptEnable +//* \brief Enable DBGU Interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_DBGU_InterruptEnable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be enabled +{ + pDbgu->DBGU_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_InterruptDisable +//* \brief Disable DBGU Interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_DBGU_InterruptDisable( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg dbgu interrupt to be disabled +{ + pDbgu->DBGU_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_GetInterruptMaskStatus +//* \brief Return DBGU Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status + AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller +{ + return pDbgu->DBGU_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_IsInterruptMasked +//* \brief Test if DBGU Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_DBGU_IsInterruptMasked( + AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR RTC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTC_InterruptEnable +//* \brief Enable RTC Interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_RTC_InterruptEnable( + AT91PS_RTC pRtc, // \arg pointer to a RTC controller + unsigned int flag) // \arg RTC interrupt to be enabled +{ + pRtc->RTC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTC_InterruptDisable +//* \brief Disable RTC Interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_RTC_InterruptDisable( + AT91PS_RTC pRtc, // \arg pointer to a RTC controller + unsigned int flag) // \arg RTC interrupt to be disabled +{ + pRtc->RTC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTC_GetInterruptMaskStatus +//* \brief Return RTC Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_RTC_GetInterruptMaskStatus( // \return RTC Interrupt Mask Status + AT91PS_RTC pRtc) // \arg pointer to a RTC controller +{ + return pRtc->RTC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTC_IsInterruptMasked +//* \brief Test if RTC Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_RTC_IsInterruptMasked( + AT91PS_RTC pRtc, // \arg pointer to a RTC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_RTC_GetInterruptMaskStatus(pRtc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SSC + ***************************************************************************** */ +//* Define the standard I2S mode configuration + +//* Configuration to set in the SSC Transmit Clock Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + AT91C_SSC_CKS_DIV +\ + AT91C_SSC_CKO_CONTINOUS +\ + AT91C_SSC_CKG_NONE +\ + AT91C_SSC_START_FALL_RF +\ + AT91C_SSC_STTOUT +\ + ((1<<16) & AT91C_SSC_STTDLY) +\ + ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) + + +//* Configuration to set in the SSC Transmit Frame Mode Register +//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits +//* nb_slot_by_frame : number of channels +#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ + (nb_bit_by_slot-1) +\ + AT91C_SSC_MSBF +\ + (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ + (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ + AT91C_SSC_FSOS_NEGATIVE) + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC_SetBaudrate ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg SSC baudrate +{ + unsigned int baud_value; + //* Define the baud rate divisor register + if (speed == 0) + baud_value = 0; + else + { + baud_value = (unsigned int) (mainClock * 10)/(2*speed); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + } + + pSSC->SSC_CMR = baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_Configure +//* \brief Configure SSC +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC_Configure ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int syst_clock, // \arg System Clock Frequency + unsigned int baud_rate, // \arg Expected Baud Rate Frequency + unsigned int clock_rx, // \arg Receiver Clock Parameters + unsigned int mode_rx, // \arg mode Register to be programmed + unsigned int clock_tx, // \arg Transmitter Clock Parameters + unsigned int mode_tx) // \arg mode Register to be programmed +{ + //* Disable interrupts + pSSC->SSC_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; + + //* Define the Clock Mode Register + AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); + + //* Write the Receive Clock Mode Register + pSSC->SSC_RCMR = clock_rx; + + //* Write the Transmit Clock Mode Register + pSSC->SSC_TCMR = clock_tx; + + //* Write the Receive Frame Mode Register + pSSC->SSC_RFMR = mode_rx; + + //* Write the Transmit Frame Mode Register + pSSC->SSC_TFMR = mode_tx; + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); + + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableRx +//* \brief Enable receiving datas +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC_EnableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable receiver + pSSC->SSC_CR = AT91C_SSC_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableRx +//* \brief Disable receiving datas +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC_DisableRx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable receiver + pSSC->SSC_CR = AT91C_SSC_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableTx +//* \brief Enable sending datas +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC_EnableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Enable transmitter + pSSC->SSC_CR = AT91C_SSC_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableTx +//* \brief Disable sending datas +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC_DisableTx ( + AT91PS_SSC pSSC) // \arg pointer to a SSC controller +{ + //* Disable transmitter + pSSC->SSC_CR = AT91C_SSC_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_EnableIt +//* \brief Enable SSC IT +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC_EnableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pSSC->SSC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_DisableIt +//* \brief Disable SSC IT +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC_DisableIt ( + AT91PS_SSC pSSC, // \arg pointer to a SSC controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pSSC->SSC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_SSC_ReceiveFrame ( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_SSC_SendFrame( + AT91PS_SSC pSSC, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSSC->SSC_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_GetInterruptMaskStatus +//* \brief Return SSC Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status + AT91PS_SSC pSsc) // \arg pointer to a SSC controller +{ + return pSsc->SSC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC_IsInterruptMasked +//* \brief Test if SSC Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_SSC_IsInterruptMasked( + AT91PS_SSC pSsc, // \arg pointer to a SSC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR SPI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Open +//* \brief Open a SPI Port +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_SPI_Open ( + const unsigned int null) // \arg +{ + /* NOT DEFINED AT THIS MOMENT */ + return ( 0 ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgCs +//* \brief Configure SPI chip select register +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_CfgCs ( + int cs, // SPI cs number (0 to 3) + int val) // chip select register +{ + //* Write to the CSR register + *(AT91C_SPI_CSR + cs) = val; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_EnableIt +//* \brief Enable SPI interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_EnableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be enabled +{ + //* Write to the IER register + pSPI->SPI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_DisableIt +//* \brief Disable SPI interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_DisableIt ( + AT91PS_SPI pSPI, // pointer to a SPI controller + unsigned int flag) // IT to be disabled +{ + //* Write to the IDR register + pSPI->SPI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Reset +//* \brief Reset the SPI controller +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_Reset ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SWRST; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Enable +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_Enable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Disable +//* \brief Disable the SPI controller +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_Disable ( + AT91PS_SPI pSPI // pointer to a SPI controller + ) +{ + //* Write to the CR register + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgMode +//* \brief Enable the SPI controller +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_CfgMode ( + AT91PS_SPI pSPI, // pointer to a SPI controller + int mode) // mode register +{ + //* Write to the MR register + pSPI->SPI_MR = mode; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPCS +//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_CfgPCS ( + AT91PS_SPI pSPI, // pointer to a SPI controller + char PCS_Device) // PCS of the Device +{ + //* Write to the MR register + pSPI->SPI_MR &= 0xFFF0FFFF; + pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_SPI_ReceiveFrame ( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_SPI_SendFrame( + AT91PS_SPI pSPI, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pSPI->SPI_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_Close +//* \brief Close SPI: disable IT disable transfert, close PDC +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_Close ( + AT91PS_SPI pSPI) // \arg pointer to a SPI controller +{ + //* Reset all the Chip Select register + pSPI->SPI_CSR[0] = 0 ; + pSPI->SPI_CSR[1] = 0 ; + pSPI->SPI_CSR[2] = 0 ; + pSPI->SPI_CSR[3] = 0 ; + + //* Reset the SPI mode + pSPI->SPI_MR = 0 ; + + //* Disable all interrupts + pSPI->SPI_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pSPI->SPI_CR = AT91C_SPI_SPIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_PutChar ( + AT91PS_SPI pSPI, + unsigned int character, + unsigned int cs_number ) +{ + unsigned int value_for_cs; + value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number + pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +static inline int AT91F_SPI_GetChar ( + const AT91PS_SPI pSPI) +{ + return((pSPI->SPI_RDR) & 0xFFFF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_GetInterruptMaskStatus +//* \brief Return SPI Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status + AT91PS_SPI pSpi) // \arg pointer to a SPI controller +{ + return pSpi->SPI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_IsInterruptMasked +//* \brief Test if SPI Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_SPI_IsInterruptMasked( + AT91PS_SPI pSpi, // \arg pointer to a SPI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptEnable +//* \brief Enable TC Interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_TC_InterruptEnable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be enabled +{ + pTc->TC_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_InterruptDisable +//* \brief Disable TC Interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_TC_InterruptDisable( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg TC interrupt to be disabled +{ + pTc->TC_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_GetInterruptMaskStatus +//* \brief Return TC Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status + AT91PS_TC pTc) // \arg pointer to a TC controller +{ + return pTc->TC_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC_IsInterruptMasked +//* \brief Test if TC Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_TC_IsInterruptMasked( + AT91PS_TC pTc, // \arg pointer to a TC controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR PMC + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_CKGR_GetMainClock +//* \brief Return Main clock in Hz +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_CKGR_GetMainClock ( + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetProcessorClock +//* \brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200) +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PMC_GetProcessorClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + unsigned int reg = pPMC->PMC_MCKR; + unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); + unsigned int pllDivider, pllMultiplier; + + switch (reg & AT91C_PMC_CSS) { + case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected + return slowClock / prescaler; + case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; + case AT91C_PMC_CSS_PLLA_CLK: // PLLA clock is selected + reg = pCKGR->CKGR_PLLAR; + pllDivider = (reg & AT91C_CKGR_DIVA); + pllMultiplier = ((reg & AT91C_CKGR_MULA) >> 16) + 1; + if (reg & AT91C_CKGR_SRCA) // Source is Main clock + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + else // Source is Slow clock + return slowClock / pllDivider * pllMultiplier / prescaler; + case AT91C_PMC_CSS_PLLB_CLK: // PLLB clock is selected + reg = pCKGR->CKGR_PLLBR; + pllDivider = (reg & AT91C_CKGR_DIVB); + pllMultiplier = ((reg & AT91C_CKGR_MULB) >> 16) + 1; + return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; + } + return 0; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_GetMasterClock +//* \brief Return master clock in Hz (just for AT91RM9200) +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PMC_GetMasterClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller + unsigned int slowClock) // \arg slowClock in Hz +{ + return AT91F_PMC_GetProcessorClock(pPMC, pCKGR, slowClock) / + (((pPMC->PMC_MCKR & AT91C_PMC_MDIV) >> 8)+1); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +static inline void AT91F_PMC_EnablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCER = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePeriphClock +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +static inline void AT91F_PMC_DisablePeriphClock ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int periphIds) // \arg IDs of peripherals to enable +{ + pPMC->PMC_PCDR = periphIds; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_EnablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +static inline void AT91F_PMC_EnablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck, // \arg Peripheral clock identifier 0 .. 7 + unsigned int ccs, // \arg clock selection: AT91C_PMC_CSS_SLOW_CLK, AT91C_PMC_CSS_MAIN_CLK, AT91C_PMC_CSS_PLLA_CLK, AT91C_PMC_CSS_PLLB_CLK + unsigned int pres) // \arg Programmable clock prescalar AT91C_PMC_PRES_CLK, AT91C_PMC_PRES_CLK_2, ..., AT91C_PMC_PRES_CLK_64 +{ + pPMC->PMC_PCKR[pck] = ccs | pres; + pPMC->PMC_SCER = (1 << pck) << 8; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_DisablePCK +//* \brief Enable peripheral clock +//*---------------------------------------------------------------------------- +static inline void AT91F_PMC_DisablePCK ( + AT91PS_PMC pPMC, // \arg pointer to PMC controller + unsigned int pck) // \arg Peripheral clock identifier 0 .. 7 +{ + pPMC->PMC_SCDR = (1 << pck) << 8; +} + +/* ***************************************************************************** + SOFTWARE API FOR PIO + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPeriph +//* \brief Enable pins to be drived by peripheral +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_CfgPeriph( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int periphAEnable, // \arg PERIPH A to enable + unsigned int periphBEnable) // \arg PERIPH B to enable + +{ + pPio->PIO_ASR = periphAEnable; + pPio->PIO_BSR = periphBEnable; + pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOutput +//* \brief Enable PIO in output mode +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_CfgOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pioEnable) // \arg PIO to be enabled +{ + pPio->PIO_PER = pioEnable; // Set in PIO mode + pPio->PIO_OER = pioEnable; // Configure in Output +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInput +//* \brief Enable PIO in input mode +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_CfgInput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputEnable) // \arg PIO to be enabled +{ + // Disable output + pPio->PIO_ODR = inputEnable; + pPio->PIO_PER = inputEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgOpendrain +//* \brief Configure PIO in open drain +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_CfgOpendrain( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int multiDrvEnable) // \arg pio to be configured in open drain +{ + // Configure the multi-drive option + pPio->PIO_MDDR = ~multiDrvEnable; + pPio->PIO_MDER = multiDrvEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgPullup +//* \brief Enable pullup on PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_CfgPullup( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int pullupEnable) // \arg enable pullup on PIO +{ + // Connect or not Pullup + pPio->PIO_PPUDR = ~pullupEnable; + pPio->PIO_PPUER = pullupEnable; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgDirectDrive +//* \brief Enable direct drive on PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_CfgDirectDrive( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int directDrive) // \arg PIO to be configured with direct drive + +{ + // Configure the Direct Drive + pPio->PIO_OWDR = ~directDrive; + pPio->PIO_OWER = directDrive; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_CfgInputFilter +//* \brief Enable input filter on input PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_CfgInputFilter( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int inputFilter) // \arg PIO to be configured with input filter + +{ + // Configure the Direct Drive + pPio->PIO_IFDR = ~inputFilter; + pPio->PIO_IFER = inputFilter; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInput +//* \brief Return PIO input value +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetInput( // \return PIO input + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputSet +//* \brief Test if PIO is input flag is active +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsInputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInput(pPio) & flag); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_SetOutput +//* \brief Set to 1 output PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_SetOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be set +{ + pPio->PIO_SODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ClearOutput +//* \brief Set to 0 output PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_ClearOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be cleared +{ + pPio->PIO_CODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_ForceOutput +//* \brief Force output when Direct drive option is enabled +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_ForceOutput( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg output to be forced +{ + pPio->PIO_ODSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Enable +//* \brief Enable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_Enable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_PER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Disable +//* \brief Disable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_Disable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_PDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetStatus +//* \brief Return PIO Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsSet +//* \brief Test if PIO is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputEnable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_OutputEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be enabled +{ + pPio->PIO_OER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputDisable +//* \brief Output Enable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_OutputDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output to be disabled +{ + pPio->PIO_ODR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputStatus +//* \brief Return PIO Output Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOuputSet +//* \brief Test if PIO Output is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsOutputSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterEnable +//* \brief Input Filter Enable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_InputFilterEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be enabled +{ + pPio->PIO_IFER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InputFilterDisable +//* \brief Input Filter Disable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_InputFilterDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio input filter to be disabled +{ + pPio->PIO_IFDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInputFilterStatus +//* \brief Return PIO Input Filter Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IFSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInputFilterSet +//* \brief Test if PIO Input filter is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsInputFilterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputDataStatus +//* \brief Return PIO Output Data Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ODSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptEnable +//* \brief Enable PIO Interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_InterruptEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be enabled +{ + pPio->PIO_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_InterruptDisable +//* \brief Disable PIO Interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_InterruptDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio interrupt to be disabled +{ + pPio->PIO_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptMaskStatus +//* \brief Return PIO Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetInterruptStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ISR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptMasked +//* \brief Test if PIO Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsInterruptMasked( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsInterruptSet +//* \brief Test if PIO Interrupt is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsInterruptSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetInterruptStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverEnable +//* \brief Multi Driver Enable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_MultiDriverEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be enabled +{ + pPio->PIO_MDER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_MultiDriverDisable +//* \brief Multi Driver Disable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_MultiDriverDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio to be disabled +{ + pPio->PIO_MDDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetMultiDriverStatus +//* \brief Return PIO Multi Driver Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_MDSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsMultiDriverSet +//* \brief Test if PIO MultiDriver is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsMultiDriverSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_A_RegisterSelection +//* \brief PIO A Register Selection +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_A_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio A register selection +{ + pPio->PIO_ASR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_B_RegisterSelection +//* \brief PIO B Register Selection +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_B_RegisterSelection( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio B register selection +{ + pPio->PIO_BSR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_Get_AB_RegisterStatus +//* \brief Return PIO Interrupt Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_ABSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsAB_RegisterSet +//* \brief Test if PIO AB Register is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsAB_RegisterSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteEnable +//* \brief Output Write Enable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_OutputWriteEnable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be enabled +{ + pPio->PIO_OWER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_OutputWriteDisable +//* \brief Output Write Disable PIO +//*---------------------------------------------------------------------------- +static inline void AT91F_PIO_OutputWriteDisable( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg pio output write to be disabled +{ + pPio->PIO_OWDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetOutputWriteStatus +//* \brief Return PIO Output Write Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_OWSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputWriteSet +//* \brief Test if PIO OutputWrite is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsOutputWriteSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_GetCfgPullup +//* \brief Return PIO Configuration Pullup +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup + AT91PS_PIO pPio) // \arg pointer to a PIO controller +{ + return pPio->PIO_PPUSR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsOutputDataStatusSet +//* \brief Test if PIO Output Data Status is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsOutputDataStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIO_IsCfgPullupStatusSet +//* \brief Test if PIO Configuration Pullup Status is Set +//*---------------------------------------------------------------------------- +static inline int AT91F_PIO_IsCfgPullupStatusSet( + AT91PS_PIO pPio, // \arg pointer to a PIO controller + unsigned int flag) // \arg flag to be tested +{ + return (~AT91F_PIO_GetCfgPullup(pPio) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR TWI + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_EnableIt +//* \brief Enable TWI IT +//*---------------------------------------------------------------------------- +static inline void AT91F_TWI_EnableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pTWI->TWI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_DisableIt +//* \brief Disable TWI IT +//*---------------------------------------------------------------------------- +static inline void AT91F_TWI_DisableIt ( + AT91PS_TWI pTWI, // \arg pointer to a TWI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pTWI->TWI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_Configure +//* \brief Configure TWI in master mode +//*---------------------------------------------------------------------------- +static inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller +{ + //* Disable interrupts + pTWI->TWI_IDR = (unsigned int) -1; + + //* Reset peripheral + pTWI->TWI_CR = AT91C_TWI_SWRST; + + //* Set Master mode + pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_GetInterruptMaskStatus +//* \brief Return TWI Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status + AT91PS_TWI pTwi) // \arg pointer to a TWI controller +{ + return pTwi->TWI_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_IsInterruptMasked +//* \brief Test if TWI Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_TWI_IsInterruptMasked( + AT91PS_TWI pTwi, // \arg pointer to a TWI controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR USART + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Calculate the baudrate +//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_EXT ) + +//* Standard Synchronous Mode : 8 bits , 1 stop , no parity +#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ + AT91C_US_USMODE_NORMAL + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//* SCK used Label +#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) + +//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity +#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ + AT91C_US_CLKS_CLOCK +\ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_EVEN + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CKLO +\ + AT91C_US_OVER) + +//* Standard IRDA mode +#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ + AT91C_US_NBSTOP_1_BIT + \ + AT91C_US_PAR_NONE + \ + AT91C_US_CHRL_8_BITS + \ + AT91C_US_CLKS_CLOCK ) + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Baudrate +//* \brief Caluculate baud_value according to the main clock and the baud rate +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_US_Baudrate ( + const unsigned int main_clock, // \arg peripheral clock + const unsigned int baud_rate) // \arg UART baudrate +{ + unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); + if ((baud_value % 10) >= 5) + baud_value = (baud_value / 10) + 1; + else + baud_value /= 10; + return baud_value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetBaudrate +//* \brief Set the baudrate according to the CPU clock +//*---------------------------------------------------------------------------- +static inline void AT91F_US_SetBaudrate ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int speed) // \arg UART baudrate +{ + //* Define the baud rate divisor register + pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetTimeguard +//* \brief Set USART timeguard +//*---------------------------------------------------------------------------- +static inline void AT91F_US_SetTimeguard ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int timeguard) // \arg timeguard value +{ + //* Write the Timeguard Register + pUSART->US_TTGR = timeguard ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableIt +//* \brief Enable USART IT +//*---------------------------------------------------------------------------- +static inline void AT91F_US_EnableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUSART->US_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableIt +//* \brief Disable USART IT +//*---------------------------------------------------------------------------- +static inline void AT91F_US_DisableIt ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IER register + pUSART->US_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Configure +//* \brief Configure USART +//*---------------------------------------------------------------------------- +static inline void AT91F_US_Configure ( + AT91PS_USART pUSART, // \arg pointer to a USART controller + unsigned int mainClock, // \arg peripheral clock + unsigned int mode , // \arg mode Register to be programmed + unsigned int baudRate , // \arg baudrate to be programmed + unsigned int timeguard ) // \arg timeguard to be programmed +{ + //* Disable interrupts + pUSART->US_IDR = (unsigned int) -1; + + //* Reset receiver and transmitter + pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; + + //* Define the baud rate divisor register + AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); + + //* Write the Timeguard Register + AT91F_US_SetTimeguard(pUSART, timeguard); + + //* Clear Transmit and Receive Counters + AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Define the USART mode + pUSART->US_MR = mode ; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableRx +//* \brief Enable receiving characters +//*---------------------------------------------------------------------------- +static inline void AT91F_US_EnableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_EnableTx +//* \brief Enable sending characters +//*---------------------------------------------------------------------------- +static inline void AT91F_US_EnableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetRx +//* \brief Reset Receiver and re-enable it +//*---------------------------------------------------------------------------- +static inline void AT91F_US_ResetRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset receiver + pUSART->US_CR = AT91C_US_RSTRX; + //* Re-Enable receiver + pUSART->US_CR = AT91C_US_RXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ResetTx +//* \brief Reset Transmitter and re-enable it +//*---------------------------------------------------------------------------- +static inline void AT91F_US_ResetTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset transmitter + pUSART->US_CR = AT91C_US_RSTTX; + //* Enable transmitter + pUSART->US_CR = AT91C_US_TXEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableRx +//* \brief Disable Receiver +//*---------------------------------------------------------------------------- +static inline void AT91F_US_DisableRx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable receiver + pUSART->US_CR = AT91C_US_RXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_DisableTx +//* \brief Disable Transmitter +//*---------------------------------------------------------------------------- +static inline void AT91F_US_DisableTx ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Disable transmitter + pUSART->US_CR = AT91C_US_TXDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Close +//* \brief Close USART: disable IT disable receiver and transmitter, close PDC +//*---------------------------------------------------------------------------- +static inline void AT91F_US_Close ( + AT91PS_USART pUSART) // \arg pointer to a USART controller +{ + //* Reset the baud rate divisor register + pUSART->US_BRGR = 0 ; + + //* Reset the USART mode + pUSART->US_MR = 0 ; + + //* Reset the Timeguard Register + pUSART->US_TTGR = 0; + + //* Disable all interrupts + pUSART->US_IDR = 0xFFFFFFFF ; + + //* Abort the Peripheral Data Transfers + AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); + + //* Disable receiver and transmitter and stop any activity immediately + pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_TxReady +//* \brief Return 1 if a character can be written in US_THR +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_US_TxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_TXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_RxReady +//* \brief Return 1 if a character can be read in US_RHR +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_US_RxReady ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & AT91C_US_RXRDY); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_Error +//* \brief Return the error flag +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_US_Error ( + AT91PS_USART pUSART ) // \arg pointer to a USART controller +{ + return (pUSART->US_CSR & + (AT91C_US_OVRE | // Overrun error + AT91C_US_FRAME | // Framing error + AT91C_US_PARE)); // Parity error +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_PutChar +//* \brief Send a character,does not check if ready to send +//*---------------------------------------------------------------------------- +static inline void AT91F_US_PutChar ( + AT91PS_USART pUSART, + int character ) +{ + pUSART->US_THR = (character & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_GetChar +//* \brief Receive a character,does not check if a character is available +//*---------------------------------------------------------------------------- +static inline int AT91F_US_GetChar ( + const AT91PS_USART pUSART) +{ + return((pUSART->US_RHR) & 0x1FF); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SendFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_US_SendFrame( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_SendFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_ReceiveFrame +//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_US_ReceiveFrame ( + AT91PS_USART pUSART, + char *pBuffer, + unsigned int szBuffer, + char *pNextBuffer, + unsigned int szNextBuffer ) +{ + return AT91F_PDC_ReceiveFrame( + (AT91PS_PDC) &(pUSART->US_RPR), + pBuffer, + szBuffer, + pNextBuffer, + szNextBuffer); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US_SetIrdaFilter +//* \brief Set the value of IrDa filter tregister +//*---------------------------------------------------------------------------- +static inline void AT91F_US_SetIrdaFilter ( + AT91PS_USART pUSART, + unsigned char value +) +{ + pUSART->US_IF = value; +} + +/* ***************************************************************************** + SOFTWARE API FOR MCI + ***************************************************************************** */ +//* Classic MCI Mode Register Configuration with PDC mode enabled and MCK = MCI Clock +#define AT91C_MCI_MR_PDCMODE (AT91C_MCI_CLKDIV |\ + AT91C_MCI_PWSDIV |\ + (AT91C_MCI_PWSDIV<<1) |\ + AT91C_MCI_PDCMODE) + +//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer +#define AT91C_MCI_DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL) + +//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A +#define AT91C_MCI_MMC_SLOTA (AT91C_MCI_SCDSEL & 0x0) + +//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B +#define AT91C_MCI_MMC_SLOTB (AT91C_MCI_SCDSEL) + +//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A +#define AT91C_MCI_SDCARD_4BITS_SLOTA ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS ) + +//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B +#define AT91C_MCI_SDCARD_4BITS_SLOTB (AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS) + + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_Configure +//* \brief Configure the MCI +//*---------------------------------------------------------------------------- +static inline void AT91F_MCI_Configure ( + AT91PS_MCI pMCI, // \arg pointer to a MCI controller + unsigned int DTOR_register, // \arg Data Timeout Register to be programmed + unsigned int MR_register, // \arg Mode Register to be programmed + unsigned int SDCR_register) // \arg SDCard Register to be programmed +{ + //* Reset the MCI + pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN; + + //* Disable all the interrupts + pMCI->MCI_IDR = 0xFFFFFFFF; + + //* Set the Data Timeout Register + pMCI->MCI_DTOR = DTOR_register; + + //* Set the Mode Register + pMCI->MCI_MR = MR_register; + + //* Set the SDCard Register + pMCI->MCI_SDCR = SDCR_register; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_EnableIt +//* \brief Enable MCI IT +//*---------------------------------------------------------------------------- +static inline void AT91F_MCI_EnableIt ( + AT91PS_MCI pMCI, // \arg pointer to a MCI controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pMCI->MCI_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_DisableIt +//* \brief Disable MCI IT +//*---------------------------------------------------------------------------- +static inline void AT91F_MCI_DisableIt ( + AT91PS_MCI pMCI, // \arg pointer to a MCI controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pMCI->MCI_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_Enable_Interface +//* \brief Enable the MCI Interface +//*---------------------------------------------------------------------------- +static inline void AT91F_MCI_Enable_Interface ( + AT91PS_MCI pMCI) // \arg pointer to a MCI controller +{ + //* Enable the MCI + pMCI->MCI_CR = AT91C_MCI_MCIEN; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_Disable_Interface +//* \brief Disable the MCI Interface +//*---------------------------------------------------------------------------- +static inline void AT91F_MCI_Disable_Interface ( + AT91PS_MCI pMCI) // \arg pointer to a MCI controller +{ + //* Disable the MCI + pMCI->MCI_CR = AT91C_MCI_MCIDIS; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_Cfg_ModeRegister +//* \brief Configure the MCI Mode Register +//*---------------------------------------------------------------------------- +static inline void AT91F_MCI_Cfg_ModeRegister ( + AT91PS_MCI pMCI, // \arg pointer to a MCI controller + unsigned int mode_register) // \arg value to set in the mode register +{ + //* Configure the MCI MR + pMCI->MCI_MR = mode_register; +} +/* ***************************************************************************** + SOFTWARE API FOR AIC + ***************************************************************************** */ +#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ConfigureIt +//* \brief Interrupt Handler Initialization +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_AIC_ConfigureIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id, // \arg interrupt number to initialize + unsigned int priority, // \arg priority to give to the interrupt + unsigned int src_type, // \arg activation and sense of activation + void (*newHandler) (void) ) // \arg address of the interrupt handler +{ + unsigned int oldHandler; + unsigned int mask ; + + oldHandler = pAic->AIC_SVR[irq_id]; + + mask = 0x1 << irq_id ; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Save the interrupt handler routine pointer and the interrupt priority + pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; + //* Store the Source Mode Register + pAic->AIC_SMR[irq_id] = src_type | priority ; + //* Clear the interrupt on the interrupt controller + pAic->AIC_ICCR = mask ; + + return oldHandler; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_EnableIt +//* \brief Enable corresponding IT number +//*---------------------------------------------------------------------------- +static inline void AT91F_AIC_EnableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + //* Enable the interrupt on the interrupt controller + pAic->AIC_IECR = 0x1 << irq_id ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_DisableIt +//* \brief Disable corresponding IT number +//*---------------------------------------------------------------------------- +static inline void AT91F_AIC_DisableIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id ) // \arg interrupt number to initialize +{ + unsigned int mask = 0x1 << irq_id; + //* Disable the interrupt on the interrupt controller + pAic->AIC_IDCR = mask ; + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = mask ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_ClearIt +//* \brief Clear corresponding IT number +//*---------------------------------------------------------------------------- +static inline void AT91F_AIC_ClearIt ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number to initialize +{ + //* Clear the interrupt on the Interrupt Controller ( if one is pending ) + pAic->AIC_ICCR = (0x1 << irq_id); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_AcknowledgeIt +//* \brief Acknowledge corresponding IT number +//*---------------------------------------------------------------------------- +static inline void AT91F_AIC_AcknowledgeIt ( + AT91PS_AIC pAic) // \arg pointer to the AIC registers +{ + pAic->AIC_EOICR = pAic->AIC_EOICR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_SetExceptionVector +//* \brief Configure vector handler +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_AIC_SetExceptionVector ( + unsigned int *pVector, // \arg pointer to the AIC registers + void (*Handler) () ) // \arg Interrupt Handler +{ + unsigned int oldVector = *pVector; + + if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) + *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; + else + *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; + + return oldVector; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Trig +//* \brief Trig an IT +//*---------------------------------------------------------------------------- +static inline void AT91F_AIC_Trig ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg interrupt number +{ + pAic->AIC_ISCR = (0x1 << irq_id) ; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsActive +//* \brief Test if an IT is active +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_AIC_IsActive ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_ISR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_IsPending +//* \brief Test if an IT is pending +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_AIC_IsPending ( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + unsigned int irq_id) // \arg Interrupt Number +{ + return (pAic->AIC_IPR & (0x1 << irq_id)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_Open +//* \brief Set exception vectors and AIC registers to default values +//*---------------------------------------------------------------------------- +static inline void AT91F_AIC_Open( + AT91PS_AIC pAic, // \arg pointer to the AIC registers + void (*IrqHandler) (), // \arg Default IRQ vector exception + void (*FiqHandler) (), // \arg Default FIQ vector exception + void (*DefaultHandler) (), // \arg Default Handler set in ISR + void (*SpuriousHandler) (), // \arg Default Spurious Handler + unsigned int protectMode) // \arg Debug Control Register +{ + int i; + + // Disable all interrupts and set IVR to the default handler + for (i = 0; i < 32; ++i) { + AT91F_AIC_DisableIt(pAic, i); + AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler); + } + + // Set the IRQ exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); + // Set the Fast Interrupt exception vector + AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); + + pAic->AIC_SPU = (unsigned int) SpuriousHandler; + pAic->AIC_DCR = protectMode; +} +/* ***************************************************************************** + SOFTWARE API FOR UDP + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableIt +//* \brief Enable UDP IT +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_EnableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be enabled +{ + //* Write to the IER register + pUDP->UDP_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableIt +//* \brief Disable UDP IT +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_DisableIt ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg IT to be disabled +{ + //* Write to the IDR register + pUDP->UDP_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetAddress +//* \brief Set UDP functional address +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_SetAddress ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char address) // \arg new UDP address +{ + pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EnableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_EnableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_DisableEp +//* \brief Enable Endpoint +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_DisableEp ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg endpoints to be enabled +{ + pUDP->UDP_GLBSTATE &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_SetState +//* \brief Set UDP Device state +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_SetState ( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg new UDP address +{ + pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); + pUDP->UDP_GLBSTATE |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetState +//* \brief return UDP Device state +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state + AT91PS_UDP pUDP) // \arg pointer to a UDP controller +{ + return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_ResetEp +//* \brief Reset UDP endpoint +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_ResetEp ( // \return the UDP device state + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned int flag) // \arg Endpoints to be reset +{ + pUDP->UDP_RSTEP = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStall +//* \brief Endpoint will STALL requests +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_EpStall( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpWrite +//* \brief Write value in the DPR +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_EpWrite( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned char value) // \arg value to be written in the DPR +{ + pUDP->UDP_FDR[endpoint] = value; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpRead +//* \brief Return value from the DPR +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_UDP_EpRead( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_FDR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpEndOfWr +//* \brief Notify the UDP that values in DPR are ready to be sent +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_EpEndOfWr( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpClear +//* \brief Clear flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_EpClear( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] &= ~(flag); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpSet +//* \brief Set flag in the endpoint CSR register +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_EpSet( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint, // \arg endpoint number + unsigned int flag) // \arg flag to be cleared +{ + pUDP->UDP_CSR[endpoint] |= flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_EpStatus +//* \brief Return the endpoint CSR register +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_UDP_EpStatus( + AT91PS_UDP pUDP, // \arg pointer to a UDP controller + unsigned char endpoint) // \arg endpoint number +{ + return pUDP->UDP_CSR[endpoint]; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_GetInterruptMaskStatus +//* \brief Return UDP Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status + AT91PS_UDP pUdp) // \arg pointer to a UDP controller +{ + return pUdp->UDP_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_IsInterruptMasked +//* \brief Test if UDP Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_UDP_IsInterruptMasked( + AT91PS_UDP pUdp, // \arg pointer to a UDP controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); +} + +/* ***************************************************************************** + SOFTWARE API FOR ST + ***************************************************************************** */ +//*---------------------------------------------------------------------------- +//* \fn AT91F_ST_SetPeriodInterval +//* \brief Set Periodic Interval Interrupt (period in ms) +//*---------------------------------------------------------------------------- +static inline void AT91F_ST_SetPeriodInterval( + AT91PS_ST pSt, + unsigned int period) +{ + volatile int status; + pSt->ST_IDR = AT91C_ST_PITS; /* Interrupt disable Register */ + + status = pSt->ST_SR; + pSt->ST_PIMR = period << 5; /* Period Interval Mode Register == timer interval = 1ms*/ +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ST_EnableIt +//* \brief Enable system timer interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_ST_EnableIt( + AT91PS_ST pSt, + unsigned int flag) +{ + pSt->ST_IER = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ST_DisableIt +//* \brief Disable system timer interrupt +//*---------------------------------------------------------------------------- +static inline void AT91F_ST_DisableIt( + AT91PS_ST pSt, + unsigned int flag) +{ + pSt->ST_IDR = flag; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ST_GetInterruptMaskStatus +//* \brief Return ST Interrupt Mask Status +//*---------------------------------------------------------------------------- +static inline unsigned int AT91F_ST_GetInterruptMaskStatus( // \return ST Interrupt Mask Status + AT91PS_ST pSt) // \arg pointer to a ST controller +{ + return pSt->ST_IMR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ST_IsInterruptMasked +//* \brief Test if ST Interrupt is Masked +//*---------------------------------------------------------------------------- +static inline int AT91F_ST_IsInterruptMasked( + AT91PS_ST pSt, // \arg pointer to a ST controller + unsigned int flag) // \arg flag to be tested +{ + return (AT91F_ST_GetInterruptMaskStatus(pSt) & flag); +} +//*---------------------------------------------------------------------------- +//* \fn AT91F_EBI_CfgPIO +//* \brief Configure PIO controllers to drive EBI signals +//*---------------------------------------------------------------------------- +static inline void AT91F_EBI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOC, // PIO controller base address + ((unsigned int) AT91C_PC8_A24 ) | + ((unsigned int) AT91C_PC7_A23 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPMC +//* \brief Enable Peripheral clock in PMC for DBGU +//*---------------------------------------------------------------------------- +static inline void AT91F_DBGU_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DBGU_CfgPIO +//* \brief Configure PIO controllers to drive DBGU signals +//*---------------------------------------------------------------------------- +static inline void AT91F_DBGU_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA31_DTXD ) | + ((unsigned int) AT91C_PA30_DRXD ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SYS_CfgPMC +//* \brief Enable Peripheral clock in PMC for SYS +//*---------------------------------------------------------------------------- +static inline void AT91F_SYS_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UHP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UHP +//*---------------------------------------------------------------------------- +static inline void AT91F_UHP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UHP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SDRC_CfgPIO +//* \brief Configure PIO controllers to drive SDRC signals +//*---------------------------------------------------------------------------- +static inline void AT91F_SDRC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOC, // PIO controller base address + ((unsigned int) AT91C_PC20_D20 ) | + ((unsigned int) AT91C_PC21_D21 ) | + ((unsigned int) AT91C_PC30_D30 ) | + ((unsigned int) AT91C_PC22_D22 ) | + ((unsigned int) AT91C_PC31_D31 ) | + ((unsigned int) AT91C_PC23_D23 ) | + ((unsigned int) AT91C_PC16_D16 ) | + ((unsigned int) AT91C_PC24_D24 ) | + ((unsigned int) AT91C_PC17_D17 ) | + ((unsigned int) AT91C_PC25_D25 ) | + ((unsigned int) AT91C_PC18_D18 ) | + ((unsigned int) AT91C_PC26_D26 ) | + ((unsigned int) AT91C_PC19_D19 ) | + ((unsigned int) AT91C_PC27_D27 ) | + ((unsigned int) AT91C_PC28_D28 ) | + ((unsigned int) AT91C_PC29_D29 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPMC +//* \brief Enable Peripheral clock in PMC for EMAC +//*---------------------------------------------------------------------------- +static inline void AT91F_EMAC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_EMAC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_EMAC_CfgPIO +//* \brief Configure PIO controllers to drive EMAC signals +//*---------------------------------------------------------------------------- +static inline void AT91F_EMAC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA14_ERXER ) | + ((unsigned int) AT91C_PA12_ERX0 ) | + ((unsigned int) AT91C_PA13_ERX1 ) | + ((unsigned int) AT91C_PA8_ETXEN ) | + ((unsigned int) AT91C_PA16_EMDIO ) | + ((unsigned int) AT91C_PA9_ETX0 ) | + ((unsigned int) AT91C_PA10_ETX1 ) | + ((unsigned int) AT91C_PA11_ECRS_ECRSDV) | + ((unsigned int) AT91C_PA15_EMDC ) | + ((unsigned int) AT91C_PA7_ETXCK_EREFCK), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_RTC_CfgPMC +//* \brief Enable Peripheral clock in PMC for RTC +//*---------------------------------------------------------------------------- +static inline void AT91F_RTC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC2 +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC2_CfgPIO +//* \brief Configure PIO controllers to drive SSC2 signals +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB12_TF2 ) | + ((unsigned int) AT91C_PB17_RF2 ) | + ((unsigned int) AT91C_PB13_TK2 ) | + ((unsigned int) AT91C_PB16_RK2 ) | + ((unsigned int) AT91C_PB14_TD2 ) | + ((unsigned int) AT91C_PB15_RD2 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC1 +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC1_CfgPIO +//* \brief Configure PIO controllers to drive SSC1 signals +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB11_RF1 ) | + ((unsigned int) AT91C_PB10_RK1 ) | + ((unsigned int) AT91C_PB8_TD1 ) | + ((unsigned int) AT91C_PB9_RD1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SSC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for SSC0 +//*---------------------------------------------------------------------------- +static inline void AT91F_SSC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SSC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPMC +//* \brief Enable Peripheral clock in PMC for SPI +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SPI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SPI_CfgPIO +//* \brief Configure PIO controllers to drive SPI signals +//*---------------------------------------------------------------------------- +static inline void AT91F_SPI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA3_NPCS0 ) | + ((unsigned int) AT91C_PA4_NPCS1 ) | + ((unsigned int) AT91C_PA1_MOSI ) | + ((unsigned int) AT91C_PA5_NPCS2 ) | + ((unsigned int) AT91C_PA6_NPCS3 ) | + ((unsigned int) AT91C_PA0_MISO ) | + ((unsigned int) AT91C_PA2_SPCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC5_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC5 +//*---------------------------------------------------------------------------- +static inline void AT91F_TC5_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC5)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC4_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC4 +//*---------------------------------------------------------------------------- +static inline void AT91F_TC4_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC4)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC3_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC3 +//*---------------------------------------------------------------------------- +static inline void AT91F_TC3_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC3)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC2_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC2 +//*---------------------------------------------------------------------------- +static inline void AT91F_TC2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC1_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC1 +//*---------------------------------------------------------------------------- +static inline void AT91F_TC1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TC0_CfgPMC +//* \brief Enable Peripheral clock in PMC for TC0 +//*---------------------------------------------------------------------------- +static inline void AT91F_TC0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TC0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_SMC2_CfgPIO +//* \brief Configure PIO controllers to drive SMC2 signals +//*---------------------------------------------------------------------------- +static inline void AT91F_SMC2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOC, // PIO controller base address + ((unsigned int) AT91C_PC10_NCS4_CFCS) | + ((unsigned int) AT91C_PC9_A25_CFRNW) | + ((unsigned int) AT91C_PC12_NCS6_CFCE2) | + ((unsigned int) AT91C_PC11_NCS5_CFCE1), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PMC +//*---------------------------------------------------------------------------- +static inline void AT91F_PMC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PMC_CfgPIO +//* \brief Configure PIO controllers to drive PMC signals +//*---------------------------------------------------------------------------- +static inline void AT91F_PMC_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PA24_PCK1 )); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB27_PCK0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOD_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOD +//*---------------------------------------------------------------------------- +static inline void AT91F_PIOD_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOD)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOC_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOC +//*---------------------------------------------------------------------------- +static inline void AT91F_PIOC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOC)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOB_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOB +//*---------------------------------------------------------------------------- +static inline void AT91F_PIOB_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOB)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_PIOA_CfgPMC +//* \brief Enable Peripheral clock in PMC for PIOA +//*---------------------------------------------------------------------------- +static inline void AT91F_PIOA_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_PIOA)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPMC +//* \brief Enable Peripheral clock in PMC for TWI +//*---------------------------------------------------------------------------- +static inline void AT91F_TWI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_TWI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_TWI_CfgPIO +//* \brief Configure PIO controllers to drive TWI signals +//*---------------------------------------------------------------------------- +static inline void AT91F_TWI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA25_TWD ) | + ((unsigned int) AT91C_PA26_TWCK ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US3_CfgPMC +//* \brief Enable Peripheral clock in PMC for US3 +//*---------------------------------------------------------------------------- +static inline void AT91F_US3_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US3)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US2_CfgPMC +//* \brief Enable Peripheral clock in PMC for US2 +//*---------------------------------------------------------------------------- +static inline void AT91F_US2_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US2)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US2_CfgPIO +//* \brief Configure PIO controllers to drive US2 signals +//*---------------------------------------------------------------------------- +static inline void AT91F_US2_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA23_TXD2 ) | + ((unsigned int) AT91C_PA22_RXD2 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPMC +//* \brief Enable Peripheral clock in PMC for US1 +//*---------------------------------------------------------------------------- +static inline void AT91F_US1_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US1)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US1_CfgPIO +//* \brief Configure PIO controllers to drive US1 signals +//*---------------------------------------------------------------------------- +static inline void AT91F_US1_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + ((unsigned int) AT91C_PB21_RXD1 ) | + ((unsigned int) AT91C_PB26_RTS1 ) | + ((unsigned int) AT91C_PB25_DSR1 ) | + ((unsigned int) AT91C_PB24_CTS1 ) | + ((unsigned int) AT91C_PB19_DTR1 ) | + ((unsigned int) AT91C_PB23_DCD1 ) | + ((unsigned int) AT91C_PB20_TXD1 ) | + ((unsigned int) AT91C_PB18_RI1 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPMC +//* \brief Enable Peripheral clock in PMC for US0 +//*---------------------------------------------------------------------------- +static inline void AT91F_US0_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_US0)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_US0_CfgPIO +//* \brief Configure PIO controllers to drive US0 signals +//*---------------------------------------------------------------------------- +static inline void AT91F_US0_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA17_TXD0 ) | + ((unsigned int) AT91C_PA21_RTS0 ) | + ((unsigned int) AT91C_PA19_SCK0 ) | + ((unsigned int) AT91C_PA20_CTS0 ), // Peripheral A + 0); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_CfgPMC +//* \brief Enable Peripheral clock in PMC for MCI +//*---------------------------------------------------------------------------- +static inline void AT91F_MCI_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_MCI)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_CfgPIO +//* \brief Configure PIO controllers to drive MCI signals +//*---------------------------------------------------------------------------- +static inline void AT91F_MCI_CfgPIO (void) +{ + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOA, // PIO controller base address + ((unsigned int) AT91C_PA28_MCCDA ) | + ((unsigned int) AT91C_PA29_MCDA0 ) | + ((unsigned int) AT91C_PA27_MCCK ), // Peripheral A + 0); // Peripheral B + // Configure PIO controllers to periph mode + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOB, // PIO controller base address + 0, // Peripheral A + ((unsigned int) AT91C_PB5_MCDA3 ) | + ((unsigned int) AT91C_PB3_MCDA1 ) | + ((unsigned int) AT91C_PB4_MCDA2 )); // Peripheral B +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_AIC_CfgPMC +//* \brief Enable Peripheral clock in PMC for AIC +//*---------------------------------------------------------------------------- +static inline void AT91F_AIC_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_IRQ4) | + ((unsigned int) 1 << AT91C_ID_FIQ) | + ((unsigned int) 1 << AT91C_ID_IRQ5) | + ((unsigned int) 1 << AT91C_ID_IRQ6) | + ((unsigned int) 1 << AT91C_ID_IRQ0) | + ((unsigned int) 1 << AT91C_ID_IRQ1) | + ((unsigned int) 1 << AT91C_ID_IRQ2) | + ((unsigned int) 1 << AT91C_ID_IRQ3)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UDP_CfgPMC +//* \brief Enable Peripheral clock in PMC for UDP +//*---------------------------------------------------------------------------- +static inline void AT91F_UDP_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_UDP)); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_ST_CfgPMC +//* \brief Enable Peripheral clock in PMC for ST +//*---------------------------------------------------------------------------- +static inline void AT91F_ST_CfgPMC (void) +{ + AT91F_PMC_EnablePeriphClock( + AT91C_BASE_PMC, // PIO controller base address + ((unsigned int) 1 << AT91C_ID_SYS)); +} + +#endif // lib_AT91RM9200_H diff --git a/target/linux/at91/image/dfboot/src/init.c b/target/linux/at91/image/dfboot/src/init.c new file mode 100644 index 0000000..4088973 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/init.c @@ -0,0 +1,165 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : init.c +//* Object : Low level initialisations written in C +//* Creation : HIi 10/10/2003 +//* +//*---------------------------------------------------------------------------- +#include "config.h" +#include "AT91RM9200.h" +#include "lib_AT91RM9200.h" +#include "stdio.h" + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DataAbort +//* \brief This function reports an Abort +//*---------------------------------------------------------------------------- +static void AT91F_SpuriousHandler() +{ + puts("ISI"); + while (1); +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_DataAbort +//* \brief This function reports an Abort +//*---------------------------------------------------------------------------- +static void AT91F_DataAbort() +{ + puts("IDA"); + while (1); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_FetchAbort +//* \brief This function reports an Abort +//*---------------------------------------------------------------------------- +static void AT91F_FetchAbort() +{ + puts("IFA"); + while (1); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_UndefHandler +//* \brief This function reports that no handler have been set for current IT +//*---------------------------------------------------------------------------- +static void AT91F_UndefHandler() +{ + puts("IUD"); + while (1); +} + + +//*-------------------------------------------------------------------------------------- +//* Function Name : AT91F_InitSdram +//* Object : Initialize the SDRAM +//* Input Parameters : +//* Output Parameters : +//*-------------------------------------------------------------------------------------- +static void AT91F_InitSdram() +{ + int *pRegister; + + //* Configure PIOC as peripheral (D16/D31) + + AT91F_PIO_CfgPeriph( + AT91C_BASE_PIOC, // PIO controller base address + 0xFFFF0030, + 0 + ); + + //*Init SDRAM + pRegister = (int *)0xFFFFFF98; + *pRegister = 0x2188c155; + pRegister = (int *)0xFFFFFF90; + *pRegister = 0x2; + pRegister = (int *)0x20000000; + *pRegister = 0; + pRegister = (int *)0xFFFFFF90; + *pRegister = 0x4; + pRegister = (int *)0x20000000; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + *pRegister = 0; + pRegister = (int *)0xFFFFFF90; + *pRegister = 0x3; + pRegister = (int *)0x20000080; + *pRegister = 0; + + pRegister = (int *)0xFFFFFF94; + *pRegister = 0x2e0; + pRegister = (int *)0x20000000; + *pRegister = 0; + + pRegister = (int *)0xFFFFFF90; + *pRegister = 0x00; + pRegister = (int *)0x20000000; + *pRegister = 0; +} + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_InitFlash +//* \brief This function performs low level HW initialization +//*---------------------------------------------------------------------------- +static void AT91F_InitMemories() +{ + int *pEbi = (int *)0xFFFFFF60; + + //* Setup MEMC to support all connected memories (CS0 = FLASH; CS1=SDRAM) + pEbi = (int *)0xFFFFFF60; + *pEbi = 0x00000002; + + //* CS0 cs for flash + pEbi = (int *)0xFFFFFF70; + *pEbi = 0x00003284; + + AT91F_InitSdram(); +} + + + +//*---------------------------------------------------------------------------- +//* \fn AT91F_LowLevelInit +//* \brief This function performs very low level HW initialization +//*---------------------------------------------------------------------------- +void AT91F_LowLevelInit(void) +{ + int i; + + // Init Interrupt Controller + AT91F_AIC_Open( + AT91C_BASE_AIC, // pointer to the AIC registers + AT91C_AIC_BRANCH_OPCODE, // IRQ exception vector + AT91F_UndefHandler, // FIQ exception vector + AT91F_UndefHandler, // AIC default handler + AT91F_SpuriousHandler, // AIC spurious handler + 0); // Protect mode + + // Perform 8 End Of Interrupt Command to make sýre AIC will not Lock out nIRQ + for(i=0; i<8; i++) + AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC); + + AT91F_AIC_SetExceptionVector((unsigned int *)0x0C, AT91F_FetchAbort); + AT91F_AIC_SetExceptionVector((unsigned int *)0x10, AT91F_DataAbort); + AT91F_AIC_SetExceptionVector((unsigned int *)0x4, AT91F_UndefHandler); + + //Initialize SDRAM and Flash + AT91F_InitMemories(); + +} + diff --git a/target/linux/at91/image/dfboot/src/jump.S b/target/linux/at91/image/dfboot/src/jump.S new file mode 100644 index 0000000..cc69311 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/jump.S @@ -0,0 +1,4 @@ +.global Jump + +Jump: mov pc, r0 + diff --git a/target/linux/at91/image/dfboot/src/led.c b/target/linux/at91/image/dfboot/src/led.c new file mode 100644 index 0000000..40d4911 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/led.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2006 + * Atmel Nordic AB + * Ulf Samuelsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define GREEN_LED AT91C_PIO_PB0 +#define YELLOW_LED AT91C_PIO_PB1 +#define RED_LED AT91C_PIO_PB2 + +void LED_set(unsigned int led) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + PIOB->PIO_SODR = (led ^ 0x7) & 0x7; // All 0's => Set PIO high => OFF + PIOB->PIO_CODR = led & 0x7; // All 1's => Set PIO low => ON +} + +void green_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; +// PIOB->PIO_CODR = GREEN_LED; + PIOB->PIO_CODR = (1 << 0); +} + +void yellow_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; +// PIOB->PIO_CODR = YELLOW_LED; + PIOB->PIO_CODR = (1 << 1); +} + +void red_LED_on(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; +// PIOB->PIO_CODR = RED_LED; + PIOB->PIO_CODR = (1 << 2); +} + +void green_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; +// PIOB->PIO_SODR = GREEN_LED; + PIOB->PIO_SODR = (1 << 0); +} + +void yellow_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; +// PIOB->PIO_SODR = YELLOW_LED; + PIOB->PIO_SODR = (1 << 1); +} + +void red_LED_off(void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; +// PIOB->PIO_SODR = RED_LED; + PIOB->PIO_SODR = (1 << 2); +} + +void LED_blink(unsigned int led) +{ + volatile int i,j; + for(i = 0; i < 5; i++) { + LED_set((1 << led)&0x7); + for(j= 0; j < 200000; j++); + LED_set(0); + for(j= 0; j < 200000; j++); + } +} + + +void LED_init (void) +{ + AT91PS_PIO PIOB = AT91C_BASE_PIOB; + AT91PS_PMC PMC = AT91C_BASE_PMC; + PMC->PMC_PCER = (1 << AT91C_ID_PIOB); // Enable PIOB clock + // Disable peripherals on LEDs + PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; + // Enable pins as outputs + PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; + // Turn all LEDs OFF + PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; +} diff --git a/target/linux/at91/image/dfboot/src/main.c b/target/linux/at91/image/dfboot/src/main.c new file mode 100644 index 0000000..c0705de --- /dev/null +++ b/target/linux/at91/image/dfboot/src/main.c @@ -0,0 +1,811 @@ +/*---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support - ROUSSET - + *---------------------------------------------------------------------------- + * The software is delivered "AS IS" without warranty or condition of any + * kind, either express, implied or statutory. This includes without + * limitation any warranty or condition with respect to merchantability or + * fitness for any particular purpose, or against the infringements of + * intellectual property rights of others. + *---------------------------------------------------------------------------- + * File Name : main.c + * Object : + * Creation : HIi 10/10/2003 + * Modif : HIi 15/06/2004 : add crc32 to verify the download + * from dataflash + * : HIi 21/09/2004 : Set first PLLA to 180Mhz and MCK to + * 60Mhz to speed up dataflash boot (15Mhz) + * : MLC 12/04/2005 : Modify SetPLL() to avoid errata + * : USA 30/12/2005 : Change to page Size 1056 + * Change startaddress to C0008400 + * Change SPI Speed to ~4 Mhz + * Add retry on CRC Error + *---------------------------------------------------------------------------- + */ +#include "config.h" +#include "stdio.h" +#include "AT91RM9200.h" +#include "lib_AT91RM9200.h" +#include "com.h" +#include "main.h" +#include "dataflash.h" +#include "AT91C_MCI_Device.h" + +#define DEBUGOUT +#define XMODEM +#define MEMDISP + +#ifdef PAGESZ_1056 +#define PAGESIZE 1056 +#else +#define PAGESIZE 1024 +#endif + +#define AT91C_SDRAM_START 0x20000000 +#define AT91C_BOOT_ADDR 0x21F00000 +#define AT91C_BOOT_SIZE 128*PAGESIZE +#ifdef PAGESZ_1056 +#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008400 +#else +#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008000 +#endif +#define AT91C_PLLA_VALUE 0x237A3E5A // crystal= 18.432MHz - fixes BRG error at 115kbps +//#define AT91C_PLLA_VALUE 0x2026BE04 // crystal= 18.432MHz +//#define AT91C_PLLA_VALUE 0x202CBE01 // crystal= 4MHz + + + +#define DISP_LINE_LEN 16 + +// Reason for boot failure +#define IMAGE_BAD_SIZE 0 +#define IMAGE_READ_FAILURE 1 +#define IMAGE_CRC_ERROR 2 +#define IMAGE_ERROR 3 +#define SUCCESS -1 + +/* prototypes*/ +extern void AT91F_ST_ASM_HANDLER(void); +extern void Jump(unsigned int addr); + +const char *menu_dataflash[] = { +#ifdef XMODEM + "1: P DFboot\n", + "2: P U-Boot\n", +#endif + "3: P SDCard\n", +#ifdef PAGESZ_1056 + "4: R UBOOT\n", +#else + "4: R UBOOT\n", +#endif +#ifdef XMODEM + "5: P DF [addr]\n", +#endif + "6: RD DF [addr]\n", + "7: E DF\n" +}; +#ifdef XMODEM +#define MAXMENU 7 +#else +#define MAXMENU 4 +#endif + +char message[20]; +#ifdef XMODEM +volatile char XmodemComplete = 0; +#endif +unsigned int StTick = 0; + +AT91S_RomBoot const *pAT91; +#ifdef XMODEM +AT91S_SBuffer sXmBuffer; +AT91S_SvcXmodem svcXmodem; +AT91S_Pipe xmodemPipe; +#endif +AT91S_CtlTempo ctlTempo; + + +//*-------------------------------------------------------------------------------------- +//* Function Name : GetTickCount() +//* Object : Return the number of systimer tick +//* Input Parameters : +//* Output Parameters : +//*-------------------------------------------------------------------------------------- +unsigned int GetTickCount(void) +{ + return StTick; +} + +#ifdef XMODEM +//*-------------------------------------------------------------------------------------- +//* Function Name : AT91_XmodemComplete() +//* Object : Perform the remap and jump to appli in RAM +//* Input Parameters : +//* Output Parameters : +//*-------------------------------------------------------------------------------------- +static void AT91_XmodemComplete(AT91S_PipeStatus status, void *pVoid) +{ + /* stop the Xmodem tempo */ + svcXmodem.tempo.Stop(&(svcXmodem.tempo)); + XmodemComplete = 1; +} + + +//*-------------------------------------------------------------------------------------- +//* Function Name : AT91F_XmodemProtocol(AT91S_PipeStatus status, void *pVoid) +//* Object : Xmodem dispatcher +//* Input Parameters : +//* Output Parameters : +//*-------------------------------------------------------------------------------------- +static void XmodemProtocol(AT91S_PipeStatus status, void *pVoid) +{ + AT91PS_SBuffer pSBuffer = (AT91PS_SBuffer) xmodemPipe.pBuffer->pChild; + AT91PS_USART pUsart = svcXmodem.pUsart; + + if (pSBuffer->szRdBuffer == 0) { + /* Start a tempo to wait the Xmodem protocol complete */ + svcXmodem.tempo.Start(&(svcXmodem.tempo), 10, 0, AT91_XmodemComplete, pUsart); + } +} +#endif + +//*-------------------------------------------------------------------------------------- +//* Function Name : irq1_c_handler() +//* Object : C Interrupt handler for Interrutp source 1 +//* Input Parameters : none +//* Output Parameters : none +//*-------------------------------------------------------------------------------------- +void AT91F_ST_HANDLER(void) +{ + volatile unsigned int csr = *AT91C_DBGU_CSR; +#ifdef XMODEM + unsigned int error; +#endif + + if (AT91C_BASE_ST->ST_SR & 0x01) { + StTick++; + ctlTempo.CtlTempoTick(&ctlTempo); + return; + } + +#ifdef XMODEM + error = AT91F_US_Error((AT91PS_USART)AT91C_BASE_DBGU); + if (csr & error) { + /* Stop previous Xmodem transmition*/ + *(AT91C_DBGU_CR) = AT91C_US_RSTSTA; + AT91F_US_DisableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_ENDRX); + AT91F_US_EnableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_RXRDY); + + } + + else if (csr & (AT91C_US_TXRDY | AT91C_US_ENDTX | AT91C_US_TXEMPTY | + AT91C_US_RXRDY | AT91C_US_ENDRX | AT91C_US_TIMEOUT | + AT91C_US_RXBUFF)) { + if ( !(svcXmodem.eot) ) + svcXmodem.Handler(&svcXmodem, csr); + } +#endif +} + + +//*----------------------------------------------------------------------------- +//* Function Name : AT91F_DisplayMenu() +//* Object : +//* Input Parameters : +//* Return value : +//*----------------------------------------------------------------------------- +static int AT91F_DisplayMenu(void) +{ + int i, mci_present = 0; + printf("\nDF LOADER %s %s %s\n",AT91C_VERSION,__DATE__,__TIME__); + AT91F_DataflashPrintInfo(); + mci_present = AT91F_MCI_Init(); + for(i = 0; i < MAXMENU; i++) { + puts(menu_dataflash[i]); + } + return mci_present; +} + + +//*----------------------------------------------------------------------------- +//* Function Name : AsciiToHex() +//* Object : ascii to hexa conversion +//* Input Parameters : +//* Return value : +//*----------------------------------------------------------------------------- +static unsigned int AsciiToHex(char *s, unsigned int *val) +{ + int n; + + *val=0; + + if(s[0] == '0' && ((s[1] == 'x') || (s[1] == 'X'))) + s+=2; + n = 0; + while((n < 8) && (s[n] !=0)) + { + *val <<= 4; + if ( (s[n] >= '0') && (s[n] <='9')) + *val += (s[n] - '0'); + else + if ((s[n] >= 'a') && (s[n] <='f')) + *val += (s[n] - 0x57); + else + if ((s[n] >= 'A') && (s[n] <='F')) + *val += (s[n] - 0x37); + else + return 0; + n++; + } + + return 1; +} + + +#ifdef MEMDISP +//*----------------------------------------------------------------------------- +//* Function Name : AT91F_MemoryDisplay() +//* Object : Display the content of the dataflash +//* Input Parameters : +//* Return value : +//*----------------------------------------------------------------------------- +static int AT91F_MemoryDisplay(unsigned int addr, unsigned int length) +{ + unsigned long i, nbytes, linebytes; + char *cp; +// unsigned int *uip; +// unsigned short *usp; + unsigned char *ucp; + char linebuf[DISP_LINE_LEN]; + +// nbytes = length * size; + nbytes = length; + do + { +// uip = (unsigned int *)linebuf; +// usp = (unsigned short *)linebuf; + ucp = (unsigned char *)linebuf; + + printf("%08x:", addr); + linebytes = (nbytes > DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; + if((addr & 0xF0000000) == 0x20000000) { + for(i = 0; i < linebytes; i ++) { + linebuf[i] = *(char *)(addr+i); + } + } else { + read_dataflash(addr, linebytes, linebuf); + } + for (i=0; i 0x7e)) + printf("."); + else + printf("%c", *cp); + cp++; + } + printf("\n"); + nbytes -= linebytes; + } while (nbytes > 0); + return 0; +} +#endif + +//*-------------------------------------------------------------------------------------- +//* Function Name : AT91F_SetPLL +//* Object : Set the PLLA to 180Mhz and Master clock to 60 Mhz +//* Input Parameters : +//* Output Parameters : +//*-------------------------------------------------------------------------------------- +static unsigned int AT91F_SetPLL(void) +{ + AT91_REG tmp; + AT91PS_PMC pPmc = AT91C_BASE_PMC; + AT91PS_CKGR pCkgr = AT91C_BASE_CKGR; + + pPmc->PMC_IDR = 0xFFFFFFFF; + + /* -Setup the PLL A */ + pCkgr->CKGR_PLLAR = AT91C_PLLA_VALUE; + + while (!(*AT91C_PMC_SR & AT91C_PMC_LOCKA)); + + /* - Switch Master Clock from PLLB to PLLA/3 */ + tmp = pPmc->PMC_MCKR; + /* See Atmel Errata #27 and #28 */ + if (tmp & 0x0000001C) { + tmp = (tmp & ~0x0000001C); + pPmc->PMC_MCKR = tmp; + while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)); + } + if (tmp != 0x00000202) { + pPmc->PMC_MCKR = 0x00000202; + if ((tmp & 0x00000003) != 0x00000002) + while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY)); + } + + return 1; +} + + +//*-------------------------------------------------------------------------------------- +//* Function Name : AT91F_ResetRegisters +//* Object : Restore the initial state to registers +//* Input Parameters : +//* Output Parameters : +//*-------------------------------------------------------------------------------------- +static unsigned int AT91F_ResetRegisters(void) +{ + volatile int i = 0; + + /* set the PIOs in input*/ + /* This disables the UART output, so dont execute for now*/ + +#ifndef DEBUGOUT + *AT91C_PIOA_ODR = 0xFFFFFFFF; /* Disables all the output pins */ + *AT91C_PIOA_PER = 0xFFFFFFFF; /* Enables the PIO to control all the pins */ +#endif + + AT91F_AIC_DisableIt (AT91C_BASE_AIC, AT91C_ID_SYS); + /* close all peripheral clocks */ + +#ifndef DEBUGOUT + AT91C_BASE_PMC->PMC_PCDR = 0xFFFFFFFC; +#endif + /* Disable core interrupts and set supervisor mode */ + __asm__ ("msr CPSR_c, #0xDF"); //* ARM_MODE_SYS(0x1F) | I_BIT(0x80) | F_BIT(0x40) + /* Clear all the interrupts */ + *AT91C_AIC_ICCR = 0xffffffff; + + /* read the AIC_IVR and AIC_FVR */ + i = *AT91C_AIC_IVR; + i = *AT91C_AIC_FVR; + + /* write the end of interrupt control register */ + *AT91C_AIC_EOICR = 0; + + return 1; +} + + +static int AT91F_LoadBoot(void) +{ +// volatile unsigned int crc1 = 0, crc2 = 0; + volatile unsigned int SizeToDownload = 0x21400; + volatile unsigned int AddressToDownload = AT91C_BOOT_ADDR; + +#if 0 + /* Read vector 6 to extract size to load */ + if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, 32, + (char *)AddressToDownload) != AT91C_DATAFLASH_OK) + { + printf("Bad Code Size\n"); + return IMAGE_BAD_SIZE; + } + /* calculate the size to download */ + SizeToDownload = *(int *)(AddressToDownload + AT91C_OFFSET_VECT6); +#endif + +// printf("\nLoad UBOOT from dataflash[%x] to SDRAM[%x]\n", +// AT91C_BOOT_DATAFLASH_ADDR, AT91C_BOOT_ADDR); + if (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, SizeToDownload + 8, + (char *)AddressToDownload) != AT91C_DATAFLASH_OK) + { + printf("F DF RD\n"); + return IMAGE_READ_FAILURE; + } +#if 0 + pAT91->CRC32((const unsigned char *)AT91C_BOOT_ADDR, + (unsigned int)SizeToDownload , (unsigned int *)&crc2); + crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) + + (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) + + (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) + + (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24); + + /* Restore the value of Vector 6 */ + *(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = + *(int *)(AddressToDownload + SizeToDownload + 4); + + if (crc1 != crc2) { + printf("DF CRC bad %x != %x\n",crc1,crc2); + return IMAGE_CRC_ERROR; + } +#endif + return SUCCESS; +} + +static int AT91F_StartBoot(void) +{ + int sts; + if((sts = AT91F_LoadBoot()) != SUCCESS) return sts; +// printf("\n"); +// printf("PLLA[180MHz], MCK[60Mhz] ==> Start UBOOT\n"); + if (AT91F_ResetRegisters()) + { + printf("Jump"); + Jump(AT91C_BOOT_ADDR); +// LED_blink(0); + } + return IMAGE_ERROR; +} + +#if 0 +static void AT91F_RepeatedStartBoot(void) +{ + int i; + for(i = 0; i < CRC_RETRIES; i++) { + if(AT91F_StartBoot() != IMAGE_CRC_ERROR){ +// LED_blink(1); + return; + } + } + return; +} +#endif + +#define TRUE 1 +#define FALSE 0 +#define TRX_MAGIC 0x30524448 /* "HDR0" */ +#define TRX_VERSION 1 + +struct trx_header { + unsigned int magic; + unsigned int len; + unsigned int crc32; + unsigned int flag_version; + unsigned int offsets[3]; +}; + +#define AT91C_MCI_TIMEOUT 1000000 + +extern AT91S_MciDevice MCI_Device; +extern void AT91F_MCIDeviceWaitReady(unsigned int); +extern int AT91F_MCI_ReadBlockSwab(AT91PS_MciDevice, int, unsigned int *, int); + +int Program_From_MCI(void) +{ + int i; + unsigned int Max_Read_DataBlock_Length; + int block = 0; + int buffer = AT91C_DOWNLOAD_BASE_ADDRESS; + int bufpos = AT91C_DOWNLOAD_BASE_ADDRESS; + int NbPage = 0; + struct trx_header *p; + + p = (struct trx_header *)bufpos; + + Max_Read_DataBlock_Length = MCI_Device.pMCI_DeviceFeatures->Max_Read_DataBlock_Length; + + AT91F_MCIDeviceWaitReady(AT91C_MCI_TIMEOUT); + + AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length); + + if (p->magic != TRX_MAGIC) { + printf("Inv IMG 0x%08x\n", p->magic); + return FALSE; + } + + printf("RDSD"); + AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC8 | AT91C_PIO_PC14; + for (i=0; i<(p->len/512); i++) { + AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length); + block++; + bufpos += Max_Read_DataBlock_Length; + } + + NbPage = 0; + i = dataflash_info[0].Device.pages_number; + while(i >>= 1) + NbPage++; + i = ((p->offsets[1] - p->offsets[0])/ 512) + 1 + (NbPage << 13) + (dataflash_info[0].Device.pages_size << 17); + *(int *)(buffer + p->offsets[0] + AT91C_OFFSET_VECT6) = i; + + printf(" WDFB"); + AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC14; + AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8; + write_dataflash(0xc0000000, buffer + p->offsets[0], p->offsets[1] - p->offsets[0]); + printf(" WUB"); + AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15; + AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8 | AT91C_PIO_PC14; + write_dataflash(0xc0008000, buffer + p->offsets[1], p->offsets[2] - p->offsets[1]); + printf(" WKRFS"); + AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC15; + AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC14; + write_dataflash(0xc0042000, buffer + p->offsets[2], p->len - p->offsets[2]); + AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC14; + AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC15; + return TRUE; +} + +//*---------------------------------------------------------------------------- +//* Function Name : main +//* Object : Main function +//* Input Parameters : none +//* Output Parameters : True +//*---------------------------------------------------------------------------- +int main(void) +{ +#ifdef XMODEM + AT91PS_Buffer pXmBuffer; + AT91PS_SvcComm pSvcXmodem; +#endif + AT91S_SvcTempo svcBootTempo; // Link to a AT91S_Tempo object + unsigned int ix; + volatile unsigned int AddressToDownload, SizeToDownload; + unsigned int DeviceAddress = 0; + char command = 0; +#ifdef XMODEM + volatile int i = 0; + unsigned int crc1 = 0, crc2 = 0; + volatile int device; + int NbPage; +#endif + volatile int Nb_Device = 0; + int mci_present = 0; + + pAT91 = AT91C_ROM_BOOT_ADDRESS; + + if (!AT91F_SetPLL()) + { + printf("F SetPLL"); + while(1); + } + + at91_init_uarts(); + + /* Tempo Initialisation */ + pAT91->OpenCtlTempo(&ctlTempo, (void *) &(pAT91->SYSTIMER_DESC)); + ctlTempo.CtlTempoStart((void *) &(pAT91->SYSTIMER_DESC)); + + // Attach the tempo to a tempo controler + ctlTempo.CtlTempoCreate(&ctlTempo, &svcBootTempo); +// LED_init(); +// LED_blink(2); + +#ifdef XMODEM + /* Xmodem Initialisation */ + pXmBuffer = pAT91->OpenSBuffer(&sXmBuffer); + pSvcXmodem = pAT91->OpenSvcXmodem(&svcXmodem, + (AT91PS_USART)AT91C_BASE_DBGU, &ctlTempo); + pAT91->OpenPipe(&xmodemPipe, pSvcXmodem, pXmBuffer); +#endif + + /* System Timer initialization */ + AT91F_AIC_ConfigureIt( + AT91C_BASE_AIC, // AIC base address + AT91C_ID_SYS, // System peripheral ID + AT91C_AIC_PRIOR_HIGHEST, // Max priority + AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, // Level sensitive + AT91F_ST_ASM_HANDLER + ); + /* Enable ST interrupt */ + AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS); + +#ifndef PRODTEST + /* Start tempo to start Boot in a delay of + * AT91C_DELAY_TO_BOOT sec if no key pressed */ + svcBootTempo.Start(&svcBootTempo, AT91C_DELAY_TO_BOOT, + 0, AT91F_StartBoot, NULL); +#endif + + while(1) + { + while(command == 0) + { + AddressToDownload = AT91C_DOWNLOAD_BASE_ADDRESS; + SizeToDownload = AT91C_DOWNLOAD_MAX_SIZE; + DeviceAddress = 0; + + /* try to detect Dataflash */ + if (!Nb_Device) + Nb_Device = AT91F_DataflashInit(); + + mci_present = AT91F_DisplayMenu(); + +#ifdef PRODTEST + if (mci_present) { + if (Program_From_MCI()) + AT91F_StartBoot(); + } +#endif + + message[0] = 0; + AT91F_ReadLine ("Enter: ", message); + +#ifndef PRODTEST + /* stop tempo ==> stop autoboot */ + svcBootTempo.Stop(&svcBootTempo); +#endif + + command = message[0]; + for(ix = 1; (message[ix] == ' ') && (ix < 12); ix++); // Skip some whitespace + + if(!AsciiToHex(&message[ix], &DeviceAddress) ) + DeviceAddress = 0; // Illegal DeviceAddress + + switch(command) + { +#ifdef XMODEM + case '1': + case '2': + case '5': + if(command == '1') { + DeviceAddress = 0xC0000000; +// printf("Download DataflashBoot.bin to [0x%x]\n", DeviceAddress); + } else if(command == '2') { + DeviceAddress = AT91C_BOOT_DATAFLASH_ADDR; +// printf("Download u-boot.bin to [0x%x]\n", DeviceAddress); + } else { +// printf("Download Dataflash to [0x%x]\n", DeviceAddress); + } + switch(DeviceAddress & 0xFF000000) + { + case CFG_DATAFLASH_LOGIC_ADDR_CS0: + if (dataflash_info[0].id == 0){ + printf("No DF"); + AT91F_WaitKeyPressed(); + command = 0; + } + + device = 0; + break; + + case CFG_DATAFLASH_LOGIC_ADDR_CS3: + if (dataflash_info[1].id == 0){ + printf("No DF"); + AT91F_WaitKeyPressed(); + command = 0; + } + device = 1; + break; + + default: + command = 0; + break; + } + break; +#endif + + case '3': + if (mci_present) + Program_From_MCI(); + command = 0; + break; + + case '4': + AT91F_StartBoot(); + command = 0; + break; + +#ifdef MEMDISP + case '6': + do + { + AT91F_MemoryDisplay(DeviceAddress, 256); + AT91F_ReadLine (NULL, message); + DeviceAddress += 0x100; + } + while(message[0] == '\0'); + command = 0; + break; +#endif + + case '7': + switch(DeviceAddress & 0xFF000000) + { + case CFG_DATAFLASH_LOGIC_ADDR_CS0: + break; + case CFG_DATAFLASH_LOGIC_ADDR_CS3: + break; + default: + command = 0; + break; + } + + if (command != 0) { + AT91F_ReadLine ("RDY ERA\nSure?", + message); + if(message[0] == 'Y' || message[0] == 'y') { + erase_dataflash(DeviceAddress & 0xFF000000); +// printf("Erase complete\n\n"); + } +// else +// printf("Erase aborted\n"); + } + command = 0; + + break; + + default: + command = 0; + break; + } + } +#ifdef XMODEM + for(i = 0; i <= AT91C_DOWNLOAD_MAX_SIZE; i++) + *(unsigned char *)(AddressToDownload + i) = 0; + + xmodemPipe.Read(&xmodemPipe, (char *)AddressToDownload, + SizeToDownload, XmodemProtocol, 0); + while(XmodemComplete !=1); + SizeToDownload = (unsigned int)((svcXmodem.pData) - + (unsigned int)AddressToDownload); + + /* Modification of vector 6 */ + if ((DeviceAddress == CFG_DATAFLASH_LOGIC_ADDR_CS0)) { + // Vector 6 must be compliant to the BootRom description (ref Datasheet) + NbPage = 0; + i = dataflash_info[device].Device.pages_number; + while(i >>= 1) + NbPage++; + i = (SizeToDownload / 512)+1 + (NbPage << 13) + + (dataflash_info[device].Device.pages_size << 17); //+4 to add crc32 + SizeToDownload = 512 * (i &0xFF); + } + else + { + /* Save the contents of vector 6 ==> will be restored + * at boot time (AT91F_StartBoot) */ + *(int *)(AddressToDownload + SizeToDownload + 4) = + *(int *)(AddressToDownload + AT91C_OFFSET_VECT6); + /* Modify Vector 6 to contain the size of the + * file to copy (Dataflash -> SDRAM)*/ + i = SizeToDownload; + } + + *(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = i; +// printf("\nModification of Arm Vector 6 :%x\n", i); + +// printf("\nWrite %d bytes in DataFlash [0x%x]\n",SizeToDownload, DeviceAddress); + crc1 = 0; + pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc1); + + /* Add the crc32 at the end of the code */ + *(char *)(AddressToDownload + SizeToDownload) = (char)(crc1 & 0x000000FF); + *(char *)(AddressToDownload + SizeToDownload + 1) = (char)((crc1 & 0x0000FF00) >> 8); + *(char *)(AddressToDownload + SizeToDownload + 2) = (char)((crc1 & 0x00FF0000) >> 16); + *(char *)(AddressToDownload + SizeToDownload + 3) = (char)((crc1 & 0xFF000000) >> 24); + + /* write dataflash */ + write_dataflash (DeviceAddress, AddressToDownload, (SizeToDownload + 8)); + + /* clear the buffer before read */ + for(i=0; i <= SizeToDownload; i++) + *(unsigned char *)(AddressToDownload + i) = 0; + + /* Read dataflash to check the validity of the data */ + read_dataflash (DeviceAddress, (SizeToDownload + 4), (char *)(AddressToDownload)); + + printf("VFY: "); + crc2 = 0; + + pAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc2); + crc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) + + (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) + + (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) + + (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24); + + if (crc1 != crc2) + printf("ERR"); + else + printf("OK"); + + command = 0; + XmodemComplete = 0; + AT91F_WaitKeyPressed(); +#endif + } +} + diff --git a/target/linux/at91/image/dfboot/src/main.h b/target/linux/at91/image/dfboot/src/main.h new file mode 100644 index 0000000..a8cd325 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/main.h @@ -0,0 +1,43 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : main.h +//* Object : +//* +//* 1.0 27/03/03 HIi : Creation +//* 1.01 03/05/04 HIi : AT9C_VERSION incremented to 1.01 +//* 1.02 15/06/04 HIi : AT9C_VERSION incremented to 1.02 ==> +//* Add crc32 to verify dataflash download +//* 1.03 18/04/05 MLC : AT91C_VERSION incremented to 1.03g +//* Repeat boot on CRC Failure +//* Change Page Size to 1056 +//* Reduce SPI speed to 4 Mbit +//* Change U-Boot boot address to a 1056 byte page boundary +//* 1.04 30/04/05 USA : AT91C_VERSION incremented to 1.04 +//* 1.05 07/08/06 USA : AT91C_VERSION incremented to 1.05 +//* Will only support loading Dataflashboot.bin and U-Boot +//*---------------------------------------------------------------------------- + +#ifndef main_h +#define main_h + +#include "embedded_services.h" + +#define AT91C_DOWNLOAD_BASE_ADDRESS 0x20000000 +#define AT91C_DOWNLOAD_MAX_SIZE 0x00040000 + +#define AT91C_OFFSET_VECT6 0x14 //* Offset for ARM vector 6 + +#define AT91C_VERSION "VER 1.05" + + +// Global variables and functions definition +extern unsigned int GetTickCount(void); +#endif + diff --git a/target/linux/at91/image/dfboot/src/mci_device.c b/target/linux/at91/image/dfboot/src/mci_device.c new file mode 100644 index 0000000..cce74a3 --- /dev/null +++ b/target/linux/at91/image/dfboot/src/mci_device.c @@ -0,0 +1,743 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : mci_device.c +//* Object : TEST DataFlash Functions +//* Creation : FB 26/11/2002 +//* +//*---------------------------------------------------------------------------- + +#include +#include "stdio.h" + +#define AT91C_MCI_TIMEOUT 1000000 /* For AT91F_MCIDeviceWaitReady */ +#define BUFFER_SIZE_MCI_DEVICE 512 +#define MASTER_CLOCK 60000000 +#define FALSE 0 +#define TRUE 1 + +//* External Functions +extern void AT91F_ASM_MCI_Handler(void); +//* Global Variables +AT91S_MciDeviceFeatures MCI_Device_Features; +AT91S_MciDeviceDesc MCI_Device_Desc; +AT91S_MciDevice MCI_Device; + +#undef ENABLE_WRITE +#undef MMC + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_SendCommand +//* \brief Generic function to send a command to the MMC or SDCard +//*---------------------------------------------------------------------------- +int AT91F_MCI_SendCommand ( + AT91PS_MciDevice pMCI_Device, + unsigned int Cmd, + unsigned int Arg) +{ + unsigned int error,status; + //unsigned int tick=0; + + // Send the command + AT91C_BASE_MCI->MCI_ARGR = Arg; + AT91C_BASE_MCI->MCI_CMDR = Cmd; + + // wait for CMDRDY Status flag to read the response + do + { + status = AT91C_BASE_MCI->MCI_SR; + //tick++; + } + while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) ); + + // Test error ==> if crc error and response R3 ==> don't check error + error = (AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR; + if(error != 0 ) + { + // if the command is SEND_OP_COND the CRC error flag is always present (cf : R3 response) + if ( (Cmd != AT91C_SDCARD_APP_OP_COND_CMD) && (Cmd != AT91C_MMC_SEND_OP_COND_CMD) ) + return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); + else + { + if (error != AT91C_MCI_RCRCE) + return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); + } + } + return AT91C_CMD_SEND_OK; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_SDCard_SendAppCommand +//* \brief Specific function to send a specific command to the SDCard +//*---------------------------------------------------------------------------- +int AT91F_MCI_SDCard_SendAppCommand ( + AT91PS_MciDevice pMCI_Device, + unsigned int Cmd_App, + unsigned int Arg ) +{ + unsigned int status; + //unsigned int tick=0; + + // Send the CMD55 for application specific command + AT91C_BASE_MCI->MCI_ARGR = (pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address << 16 ); + AT91C_BASE_MCI->MCI_CMDR = AT91C_APP_CMD; + + // wait for CMDRDY Status flag to read the response + do + { + status = AT91C_BASE_MCI->MCI_SR; + //tick++; + } + while( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) ); + + // if an error occurs + if (((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR) != 0 ) + return ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR); + + // check if it is a specific command and then send the command + if ( (Cmd_App && AT91C_SDCARD_APP_ALL_CMD) == 0) + return AT91C_CMD_SEND_ERROR; + + return( AT91F_MCI_SendCommand(pMCI_Device,Cmd_App,Arg) ); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_GetStatus +//* \brief Addressed card sends its status register +//*---------------------------------------------------------------------------- +int AT91F_MCI_GetStatus(AT91PS_MciDevice pMCI_Device,unsigned int relative_card_address) +{ + if (AT91F_MCI_SendCommand(pMCI_Device, + AT91C_SEND_STATUS_CMD, + relative_card_address <<16) == AT91C_CMD_SEND_OK) + return (AT91C_BASE_MCI->MCI_RSPR[0]); + + return AT91C_CMD_SEND_ERROR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_Device_Handler +//* \brief MCI C interrupt handler +//*---------------------------------------------------------------------------- +void AT91F_MCI_Device_Handler( + AT91PS_MciDevice pMCI_Device, + unsigned int status) +{ + // If End of Tx Buffer Empty interrupt occurred + if ( status & AT91C_MCI_TXBUFE ) + { + AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_TXBUFE; + AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTDIS; + + pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE; + } // End of if AT91C_MCI_TXBUFF + + // If End of Rx Buffer Full interrupt occurred + if ( status & AT91C_MCI_RXBUFF ) + { + AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_RXBUFF; + AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTDIS; + + pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE; + } // End of if AT91C_MCI_RXBUFF + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_Handler +//* \brief MCI Handler +//*---------------------------------------------------------------------------- +void AT91F_MCI_Handler(void) +{ + int status; + + status = ( AT91C_BASE_MCI->MCI_SR & AT91C_BASE_MCI->MCI_IMR ); + + AT91F_MCI_Device_Handler(&MCI_Device,status); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_ReadBlock +//* \brief Read an ENTIRE block or PARTIAL block +//*---------------------------------------------------------------------------- +int AT91F_MCI_ReadBlock( + AT91PS_MciDevice pMCI_Device, + int src, + unsigned int *dataBuffer, + int sizeToRead ) +{ + //////////////////////////////////////////////////////////////////////////////////////////// + if(pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE) + return AT91C_READ_ERROR; + + if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA) + return AT91C_READ_ERROR; + + if ( (src + sizeToRead) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity ) + return AT91C_READ_ERROR; + + // If source does not fit a begin of a block + if ( (src % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 ) + return AT91C_READ_ERROR; + + // Test if the MMC supports Partial Read Block + // ALWAYS SUPPORTED IN SD Memory Card + if( (sizeToRead < pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) + && (pMCI_Device->pMCI_DeviceFeatures->Read_Partial == 0x00) ) + return AT91C_READ_ERROR; + + if( sizeToRead > pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) + return AT91C_READ_ERROR; + //////////////////////////////////////////////////////////////////////////////////////////// + + // Init Mode Register + AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length << 16) | AT91C_MCI_PDCMODE); + + if (sizeToRead %4) + sizeToRead = (sizeToRead /4)+1; + else + sizeToRead = sizeToRead/4; + + AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); + AT91C_BASE_PDC_MCI->PDC_RPR = (unsigned int)dataBuffer; + AT91C_BASE_PDC_MCI->PDC_RCR = sizeToRead; + + // Send the Read single block command + if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_READ_SINGLE_BLOCK_CMD, src) != AT91C_CMD_SEND_OK ) + return AT91C_READ_ERROR; + + pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_RX_SINGLE_BLOCK; + + // Enable AT91C_MCI_RXBUFF Interrupt + AT91C_BASE_MCI->MCI_IER = AT91C_MCI_RXBUFF; + + // (PDC) Receiver Transfer Enable + AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTEN; + + return AT91C_READ_OK; +} + + +#ifdef ENABLE_WRITE +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_WriteBlock +//* \brief Write an ENTIRE block but not always PARTIAL block !!! +//*---------------------------------------------------------------------------- +int AT91F_MCI_WriteBlock( + AT91PS_MciDevice pMCI_Device, + int dest, + unsigned int *dataBuffer, + int sizeToWrite ) +{ + //////////////////////////////////////////////////////////////////////////////////////////// + if( pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE) + return AT91C_WRITE_ERROR; + + if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA) + return AT91C_WRITE_ERROR; + + if ( (dest + sizeToWrite) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity ) + return AT91C_WRITE_ERROR; + + // If source does not fit a begin of a block + if ( (dest % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 ) + return AT91C_WRITE_ERROR; + + // Test if the MMC supports Partial Write Block + if( (sizeToWrite < pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length) + && (pMCI_Device->pMCI_DeviceFeatures->Write_Partial == 0x00) ) + return AT91C_WRITE_ERROR; + + if( sizeToWrite > pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length ) + return AT91C_WRITE_ERROR; + //////////////////////////////////////////////////////////////////////////////////////////// + + // Init Mode Register + AT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length << 16) | AT91C_MCI_PDCMODE); + + if (sizeToWrite %4) + sizeToWrite = (sizeToWrite /4)+1; + else + sizeToWrite = sizeToWrite/4; + + // Init PDC for write sequence + AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); + AT91C_BASE_PDC_MCI->PDC_TPR = (unsigned int) dataBuffer; + AT91C_BASE_PDC_MCI->PDC_TCR = sizeToWrite; + + // Send the write single block command + if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_WRITE_BLOCK_CMD, dest) != AT91C_CMD_SEND_OK) + return AT91C_WRITE_ERROR; + + pMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_TX_SINGLE_BLOCK; + + // Enable AT91C_MCI_TXBUFE Interrupt + AT91C_BASE_MCI->MCI_IER = AT91C_MCI_TXBUFE; + + // Enables TX for PDC transfert requests + AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTEN; + + return AT91C_WRITE_OK; +} +#endif + +#ifdef MMC +//*------------------------------------------------------------------------------------------------------------ +//* \fn AT91F_MCI_MMC_SelectCard +//* \brief Toggles a card between the Stand_by and Transfer states or between Programming and Disconnect states +//*------------------------------------------------------------------------------------------------------------ +int AT91F_MCI_MMC_SelectCard(AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address) +{ + int status; + + //* Check if the MMC card chosen is already the selected one + status = AT91F_MCI_GetStatus(pMCI_Device,relative_card_address); + + if (status < 0) + return AT91C_CARD_SELECTED_ERROR; + + if ((status & AT91C_SR_CARD_SELECTED) == AT91C_SR_CARD_SELECTED) + return AT91C_CARD_SELECTED_OK; + + //* Search for the MMC Card to be selected, status = the Corresponding Device Number + status = 0; + while( (pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address != relative_card_address) + && (status < AT91C_MAX_MCI_CARDS) ) + status++; + + if (status > AT91C_MAX_MCI_CARDS) + return AT91C_CARD_SELECTED_ERROR; + + if (AT91F_MCI_SendCommand( pMCI_Device, + AT91C_SEL_DESEL_CARD_CMD, + pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address << 16) == AT91C_CMD_SEND_OK) + return AT91C_CARD_SELECTED_OK; + return AT91C_CARD_SELECTED_ERROR; +} +#endif + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_GetCSD +//* \brief Asks to the specified card to send its CSD +//*---------------------------------------------------------------------------- +int AT91F_MCI_GetCSD (AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address , unsigned int * response) +{ + + if(AT91F_MCI_SendCommand(pMCI_Device, + AT91C_SEND_CSD_CMD, + (relative_card_address << 16)) != AT91C_CMD_SEND_OK) + return AT91C_CMD_SEND_ERROR; + + response[0] = AT91C_BASE_MCI->MCI_RSPR[0]; + response[1] = AT91C_BASE_MCI->MCI_RSPR[1]; + response[2] = AT91C_BASE_MCI->MCI_RSPR[2]; + response[3] = AT91C_BASE_MCI->MCI_RSPR[3]; + + return AT91C_CMD_SEND_OK; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_SetBlocklength +//* \brief Select a block length for all following block commands (R/W) +//*---------------------------------------------------------------------------- +int AT91F_MCI_SetBlocklength(AT91PS_MciDevice pMCI_Device,unsigned int length) +{ + return( AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_BLOCKLEN_CMD, length) ); +} + +#ifdef MMC +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_MMC_GetAllOCR +//* \brief Asks to all cards to send their operations conditions +//*---------------------------------------------------------------------------- +int AT91F_MCI_MMC_GetAllOCR (AT91PS_MciDevice pMCI_Device) +{ + unsigned int response =0x0; + + while(1) + { + response = AT91F_MCI_SendCommand(pMCI_Device, + AT91C_MMC_SEND_OP_COND_CMD, + AT91C_MMC_HOST_VOLTAGE_RANGE); + if (response != AT91C_CMD_SEND_OK) + return AT91C_INIT_ERROR; + + response = AT91C_BASE_MCI->MCI_RSPR[0]; + + if ( (response & AT91C_CARD_POWER_UP_BUSY) == AT91C_CARD_POWER_UP_BUSY) + return(response); + } +} +#endif + +#ifdef MMC +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_MMC_GetAllCID +//* \brief Asks to the MMC on the chosen slot to send its CID +//*---------------------------------------------------------------------------- +int AT91F_MCI_MMC_GetAllCID (AT91PS_MciDevice pMCI_Device, unsigned int *response) +{ + int Nb_Cards_Found=-1; + + while(1) + { + if(AT91F_MCI_SendCommand(pMCI_Device, + AT91C_MMC_ALL_SEND_CID_CMD, + AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK) + return Nb_Cards_Found; + else + { + Nb_Cards_Found = 0; + //* Assignation of the relative address to the MMC CARD + pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Relative_Card_Address = Nb_Cards_Found + AT91C_FIRST_RCA; + //* Set the insert flag + pMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Card_Inserted = AT91C_MMC_CARD_INSERTED; + + if (AT91F_MCI_SendCommand(pMCI_Device, + AT91C_MMC_SET_RELATIVE_ADDR_CMD, + (Nb_Cards_Found + AT91C_FIRST_RCA) << 16) != AT91C_CMD_SEND_OK) + return AT91C_CMD_SEND_ERROR; + + //* If no error during assignation address ==> Increment Nb_cards_Found + Nb_Cards_Found++ ; + } + } +} +#endif +#ifdef MMC +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_MMC_Init +//* \brief Return the MMC initialisation status +//*---------------------------------------------------------------------------- +int AT91F_MCI_MMC_Init (AT91PS_MciDevice pMCI_Device) +{ + unsigned int tab_response[4]; + unsigned int mult,blocknr; + unsigned int i,Nb_Cards_Found=0; + + //* Resets all MMC Cards in Idle state + AT91F_MCI_SendCommand(pMCI_Device, AT91C_MMC_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT); + + if(AT91F_MCI_MMC_GetAllOCR(pMCI_Device) == AT91C_INIT_ERROR) + return AT91C_INIT_ERROR; + + Nb_Cards_Found = AT91F_MCI_MMC_GetAllCID(pMCI_Device,tab_response); + if (Nb_Cards_Found != AT91C_CMD_SEND_ERROR) + { + //* Set the Mode Register + AT91C_BASE_MCI->MCI_MR = AT91C_MCI_MR_PDCMODE; + + for(i = 0; i < Nb_Cards_Found; i++) + { + if (AT91F_MCI_GetCSD(pMCI_Device, + pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address, + tab_response) != AT91C_CMD_SEND_OK) + pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address = 0; + else + { + pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M ); + pMCI_Device->pMCI_DeviceFeatures[i].Max_Write_DataBlock_Length = 1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M ); + pMCI_Device->pMCI_DeviceFeatures[i].Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v22_SECT_SIZE_S) & AT91C_CSD_v22_SECT_SIZE_M ); + pMCI_Device->pMCI_DeviceFeatures[i].Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M; + pMCI_Device->pMCI_DeviceFeatures[i].Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M; + + // None in MMC specification version 2.2 + pMCI_Device->pMCI_DeviceFeatures[i].Erase_Block_Enable = 0; + + pMCI_Device->pMCI_DeviceFeatures[i].Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M; + pMCI_Device->pMCI_DeviceFeatures[i].Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M; + + //// Compute Memory Capacity + // compute MULT + mult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 ); + // compute MSB of C_SIZE + blocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2; + // compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR + blocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 ); + + pMCI_Device->pMCI_DeviceFeatures[i].Memory_Capacity = pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length * blocknr; + //// End of Compute Memory Capacity + + } // end of else + } // end of for + + return AT91C_INIT_OK; + } // end of if + + return AT91C_INIT_ERROR; +} +#endif + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_SDCard_GetOCR +//* \brief Asks to all cards to send their operations conditions +//*---------------------------------------------------------------------------- +int AT91F_MCI_SDCard_GetOCR (AT91PS_MciDevice pMCI_Device) +{ + unsigned int response =0x0; + + // The RCA to be used for CMD55 in Idle state shall be the card's default RCA=0x0000. + pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = 0x0; + + while( (response & AT91C_CARD_POWER_UP_BUSY) != AT91C_CARD_POWER_UP_BUSY ) + { + response = AT91F_MCI_SDCard_SendAppCommand(pMCI_Device, + AT91C_SDCARD_APP_OP_COND_CMD, + AT91C_MMC_HOST_VOLTAGE_RANGE); + if (response != AT91C_CMD_SEND_OK) + return AT91C_INIT_ERROR; + + response = AT91C_BASE_MCI->MCI_RSPR[0]; + } + + return(AT91C_BASE_MCI->MCI_RSPR[0]); +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_SDCard_GetCID +//* \brief Asks to the SDCard on the chosen slot to send its CID +//*---------------------------------------------------------------------------- +int AT91F_MCI_SDCard_GetCID (AT91PS_MciDevice pMCI_Device, unsigned int *response) +{ + if(AT91F_MCI_SendCommand(pMCI_Device, + AT91C_ALL_SEND_CID_CMD, + AT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK) + return AT91C_CMD_SEND_ERROR; + + response[0] = AT91C_BASE_MCI->MCI_RSPR[0]; + response[1] = AT91C_BASE_MCI->MCI_RSPR[1]; + response[2] = AT91C_BASE_MCI->MCI_RSPR[2]; + response[3] = AT91C_BASE_MCI->MCI_RSPR[3]; + + return AT91C_CMD_SEND_OK; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_SDCard_SetBusWidth +//* \brief Set bus width for SDCard +//*---------------------------------------------------------------------------- +int AT91F_MCI_SDCard_SetBusWidth(AT91PS_MciDevice pMCI_Device) +{ + volatile int ret_value; + char bus_width; + + do + { + ret_value =AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address); + } + while((ret_value > 0) && ((ret_value & AT91C_SR_READY_FOR_DATA) == 0)); + + // Select Card + AT91F_MCI_SendCommand(pMCI_Device, + AT91C_SEL_DESEL_CARD_CMD, + (pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address)<<16); + + // Set bus width for Sdcard + if(pMCI_Device->pMCI_DeviceDesc->SDCard_bus_width == AT91C_MCI_SCDBUS) + bus_width = AT91C_BUS_WIDTH_4BITS; + else bus_width = AT91C_BUS_WIDTH_1BIT; + + if (AT91F_MCI_SDCard_SendAppCommand(pMCI_Device,AT91C_SDCARD_SET_BUS_WIDTH_CMD,bus_width) != AT91C_CMD_SEND_OK) + return AT91C_CMD_SEND_ERROR; + + return AT91C_CMD_SEND_OK; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_SDCard_Init +//* \brief Return the SDCard initialisation status +//*---------------------------------------------------------------------------- +int AT91F_MCI_SDCard_Init (AT91PS_MciDevice pMCI_Device) +{ + unsigned int tab_response[4]; + unsigned int mult,blocknr; + + AT91F_MCI_SendCommand(pMCI_Device, AT91C_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT); + + if(AT91F_MCI_SDCard_GetOCR(pMCI_Device) == AT91C_INIT_ERROR) + return AT91C_INIT_ERROR; + + if (AT91F_MCI_SDCard_GetCID(pMCI_Device,tab_response) == AT91C_CMD_SEND_OK) + { + pMCI_Device->pMCI_DeviceFeatures->Card_Inserted = AT91C_SD_CARD_INSERTED; + + if (AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_RELATIVE_ADDR_CMD, 0) == AT91C_CMD_SEND_OK) + { + pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = (AT91C_BASE_MCI->MCI_RSPR[0] >> 16); + if (AT91F_MCI_GetCSD(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address,tab_response) == AT91C_CMD_SEND_OK) + { + pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M ); + pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length = 1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M ); + pMCI_Device->pMCI_DeviceFeatures->Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v21_SECT_SIZE_S) & AT91C_CSD_v21_SECT_SIZE_M ); + pMCI_Device->pMCI_DeviceFeatures->Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M; + pMCI_Device->pMCI_DeviceFeatures->Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M; + pMCI_Device->pMCI_DeviceFeatures->Erase_Block_Enable = (tab_response[3] >> AT91C_CSD_v21_ER_BLEN_EN_S) & AT91C_CSD_v21_ER_BLEN_EN_M; + pMCI_Device->pMCI_DeviceFeatures->Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M; + pMCI_Device->pMCI_DeviceFeatures->Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M; + + //// Compute Memory Capacity + // compute MULT + mult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 ); + // compute MSB of C_SIZE + blocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2; + // compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR + blocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 ); + + pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity = pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length * blocknr; + //// End of Compute Memory Capacity + printf("SD-Card: %d Bytes\n\r", pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity); + + if( AT91F_MCI_SDCard_SetBusWidth(pMCI_Device) == AT91C_CMD_SEND_OK ) + { + if (AT91F_MCI_SetBlocklength(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) == AT91C_CMD_SEND_OK) + return AT91C_INIT_OK; + } + } + } + } + return AT91C_INIT_ERROR; +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_CfgDevice +//* \brief This function is used to initialise MMC or SDCard Features +//*---------------------------------------------------------------------------- +void AT91F_CfgDevice(void) +{ + // Init Device Structure + + MCI_Device_Features.Relative_Card_Address = 0; + MCI_Device_Features.Card_Inserted = AT91C_CARD_REMOVED; + MCI_Device_Features.Max_Read_DataBlock_Length = 0; + MCI_Device_Features.Max_Write_DataBlock_Length = 0; + MCI_Device_Features.Read_Partial = 0; + MCI_Device_Features.Write_Partial = 0; + MCI_Device_Features.Erase_Block_Enable = 0; + MCI_Device_Features.Sector_Size = 0; + MCI_Device_Features.Memory_Capacity = 0; + + MCI_Device_Desc.state = AT91C_MCI_IDLE; + MCI_Device_Desc.SDCard_bus_width = AT91C_MCI_SCDBUS; + + // Init AT91S_DataFlash Global Structure, by default AT45DB choosen !!! + MCI_Device.pMCI_DeviceDesc = &MCI_Device_Desc; + MCI_Device.pMCI_DeviceFeatures = &MCI_Device_Features; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCI_Init +//* \brief Initialsise Card +//*---------------------------------------------------------------------------- +int AT91F_MCI_Init(void) +{ + +/////////////////////////////////////////////////////////////////////////////////////////// +// MCI Init : common to MMC and SDCard +/////////////////////////////////////////////////////////////////////////////////////////// + + // Set up PIO SDC_TYPE to switch on MMC/SDCard and not DataFlash Card + AT91F_PIO_CfgOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7); + AT91F_PIO_SetOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7); + + // Init MCI for MMC and SDCard interface + AT91F_MCI_CfgPIO(); + AT91F_MCI_CfgPMC(); + AT91F_PDC_Open(AT91C_BASE_PDC_MCI); + + // Disable all the interrupts + AT91C_BASE_MCI->MCI_IDR = 0xFFFFFFFF; + + // Init MCI Device Structures + AT91F_CfgDevice(); + + // Configure MCI interrupt + AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, + AT91C_ID_MCI, + AT91C_AIC_PRIOR_HIGHEST, + AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, + AT91F_ASM_MCI_Handler); + + // Enable MCI interrupt + AT91F_AIC_EnableIt(AT91C_BASE_AIC,AT91C_ID_MCI); + + // Enable Receiver + AT91F_US_EnableRx((AT91PS_USART) AT91C_BASE_DBGU); + + AT91F_MCI_Configure(AT91C_BASE_MCI, + AT91C_MCI_DTOR_1MEGA_CYCLES, + AT91C_MCI_MR_PDCMODE, // 15MHz for MCK = 60MHz (CLKDIV = 1) + AT91C_MCI_SDCARD_4BITS_SLOTA); + + if(AT91F_MCI_SDCard_Init(&MCI_Device) != AT91C_INIT_OK) + return FALSE; + else + return TRUE; + +} + +//*---------------------------------------------------------------------------- +//* \fn AT91F_MCIDeviceWaitReady +//* \brief Wait for MCI Device ready +//*---------------------------------------------------------------------------- +void AT91F_MCIDeviceWaitReady(unsigned int timeout) +{ + volatile int status; + + do + { + status = AT91C_BASE_MCI->MCI_SR; + timeout--; + } + while( !(status & AT91C_MCI_NOTBUSY) && (timeout>0) ); +} + +unsigned int swab32(unsigned int data) +{ + unsigned int res = 0; + + res = (data & 0x000000ff) << 24 | + (data & 0x0000ff00) << 8 | + (data & 0x00ff0000) >> 8 | + (data & 0xff000000) >> 24; + + return res; +} + +//*-------------------------------------------------------------------- +//* \fn AT91F_MCI_ReadBlockSwab +//* \brief Read Block and swap byte order +//*-------------------------------------------------------------------- +int AT91F_MCI_ReadBlockSwab( + AT91PS_MciDevice pMCI_Device, + int src, + unsigned int *databuffer, + int sizeToRead) +{ + int i; + unsigned char *buf = (unsigned char *)databuffer; + + //* Read Block 1 + for(i=0;i +#include + +#ifndef NULL +#define NULL ((void *)0) +#endif + +void at91_init_uarts(void); +int puts(const char *str); +int putc(int c); +int putchar(int c); +int getc(); + +int strlen(const char *str); + +int hvfprintf(const char *fmt, va_list ap); + +int printf(const char *fmt, ...); diff --git a/target/linux/at91/image/u-boot/Makefile b/target/linux/at91/image/u-boot/Makefile new file mode 100644 index 0000000..1d1b314 --- /dev/null +++ b/target/linux/at91/image/u-boot/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/kernel.mk + +PKG_NAME:=u-boot +PKG_VERSION:=2010.06 +PKG_RELEASE:=1 + +PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) +PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 +PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot +PKG_MD5SUM:= +PKG_CAT:=bzcat + +include $(INCLUDE_DIR)/package.mk + +UBOOT_CONFIG=$(call qstrip,$(CONFIG_UBOOT_TARGET)) +LAN_IP=$(call qstrip,$(CONFIG_UBOOT_IPADDR)) +LAN_SERVERIP=$(call qstrip,$(CONFIG_UBOOT_SERVERIP)) + +define Build/Compile + $(MAKE) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIG)_config + export CROSS_COMPILE=$(TARGET_CROSS); \ + export LAN_IP=$(LAN_IP); \ + export LAN_SERVERIP=$(LAN_SERVERIP); \ + $(MAKE) -C $(PKG_BUILD_DIR) + mkdir -p $(PKG_BUILD_DIR)/ubclient + $(CP) ./ubclient/* $(PKG_BUILD_DIR)/ubclient + export LAN_IP=$(LAN_IP); \ + export LAN_SERVERIP=$(LAN_SERVERIP); \ + #$(MAKE) -C $(PKG_BUILD_DIR)/ubclient \ + # $(TARGET_CONFIGURE_OPTS) \ + # CFLAGS="$(TARGET_CFLAGS) -Dtarget_$(BOARD)=1" +endef + +define Build/InstallDev + dd if=$(PKG_BUILD_DIR)/u-boot.bin of=$(PKG_BUILD_DIR)/u-boot.block bs=232k count=1 conv=sync +# $(INSTALL_DIR) $(STAGING_DIR)/ubclient/sbin +# $(INSTALL_BIN) $(PKG_BUILD_DIR)/ubclient/ubpar $(STAGING_DIR)/ubclient/sbin/ +# $(CP) $(PKG_BUILD_DIR)/ubclient/ubpar ../../base-files/sbin + mkdir -p $(BIN_DIR)/ + cp $(PKG_BUILD_DIR)/u-boot.bin $(BIN_DIR)/u-boot.$(PKG_VERSION).bin +endef + +$(eval $(call Build/DefaultTargets)) diff --git a/target/linux/at91/image/u-boot/patches/100-netusg20.patch b/target/linux/at91/image/u-boot/patches/100-netusg20.patch new file mode 100644 index 0000000..127372e --- /dev/null +++ b/target/linux/at91/image/u-boot/patches/100-netusg20.patch @@ -0,0 +1,574 @@ +Add support for the NetusG20 board by Acmesystems srl. +This board is based on AT91SAM9G20 SoC. + +Signed-off-by: Claudio Mignanti +--- + MAKEALL | 1 + + Makefile | 3 + + arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 5 + + board/acmesystems/netusg20/Makefile | 56 +++++++ + board/acmesystems/netusg20/config.mk | 1 + + board/acmesystems/netusg20/led.c | 40 +++++ + board/acmesystems/netusg20/netusg20.c | 152 +++++++++++++++++ + board/acmesystems/netusg20/partition.c | 39 +++++ + include/configs/netusg20.h | 181 +++++++++++++++++++++ + 9 files changed, 478 insertions(+), 0 deletions(-) + create mode 100644 board/acmesystems/netusg20/Makefile + create mode 100644 board/acmesystems/netusg20/config.mk + create mode 100644 board/acmesystems/netusg20/led.c + create mode 100644 board/acmesystems/netusg20/netusg20.c + create mode 100644 board/acmesystems/netusg20/partition.c + create mode 100644 include/configs/netusg20.h + +diff --git a/MAKEALL b/MAKEALL +index d6d5f5b..60e36e1 100755 +--- a/MAKEALL ++++ b/MAKEALL +@@ -684,6 +684,7 @@ LIST_at91=" \ + meesc \ + mp2usb \ + m501sk \ ++ netusg20 \ + otc570 \ + pm9261 \ + pm9263 \ +diff --git a/Makefile b/Makefile +index 87d5214..b73659f 100644 +--- a/Makefile ++++ b/Makefile +@@ -2867,6 +2867,9 @@ at91sam9g45ekes_config : unconfig + fi; + @$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91 + ++netusg20_config: unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm926ejs netusg20 acmesystems at91 ++ + otc570_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs otc570 esd at91 + +diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +index 77d49ab..87ec531 100644 +--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c ++++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +@@ -59,7 +59,12 @@ void at91_serial3_hw_init(void) + { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + ++#ifdef CONFIG_NETUSG20 ++ /* pull-up active on DRXD*/ ++ at91_set_a_periph(AT91_PIO_PORTB, 14, 1); ++#else + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */ ++#endif + at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ + writel(1 << AT91_ID_SYS, &pmc->pcer); + } +diff --git a/board/acmesystems/netusg20/Makefile b/board/acmesystems/netusg20/Makefile +new file mode 100644 +index 0000000..31589fd +--- /dev/null ++++ b/board/acmesystems/netusg20/Makefile +@@ -0,0 +1,56 @@ ++# ++# (C) Copyright 2003-2008 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# (C) Copyright 2008 ++# Stelian Pop ++# Lead Tech Design ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS-y += netusg20.o ++COBJS-y += led.o ++COBJS-y += partition.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS-y)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak $(obj).depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/acmesystems/netusg20/config.mk b/board/acmesystems/netusg20/config.mk +new file mode 100644 +index 0000000..ff2cfd1 +--- /dev/null ++++ b/board/acmesystems/netusg20/config.mk +@@ -0,0 +1 @@ ++TEXT_BASE = 0x23f00000 +diff --git a/board/acmesystems/netusg20/led.c b/board/acmesystems/netusg20/led.c +new file mode 100644 +index 0000000..1016b98 +--- /dev/null ++++ b/board/acmesystems/netusg20/led.c +@@ -0,0 +1,40 @@ ++/* ++ * (C) Copyright 2007-2008 ++ * Stelian Pop ++ * Lead Tech Design ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++void coloured_LED_init(void) ++{ ++ /* Enable clock */ ++ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); ++ ++ at91_set_gpio_output(CONFIG_RED_LED, 1); ++ ++ at91_set_gpio_value(CONFIG_RED_LED, 1); ++} +diff --git a/board/acmesystems/netusg20/netusg20.c b/board/acmesystems/netusg20/netusg20.c +new file mode 100644 +index 0000000..94b4d4c +--- /dev/null ++++ b/board/acmesystems/netusg20/netusg20.c +@@ -0,0 +1,152 @@ ++/* ++ * (C) Copyright 2007-2008 ++ * Stelian Pop ++ * Lead Tech Design ++ * ++ * (C) Copyright 2010 ++ * Claudio Mignanti ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) ++#include ++#endif ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++/* ------------------------------------------------------------------------- */ ++/* ++ * Miscelaneous platform dependent initialisations ++ */ ++ ++#ifdef CONFIG_MACB ++static void at91sam9260ek_macb_hw_init(void) ++{ ++ unsigned long rstc; ++ ++ /* Enable clock */ ++ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); ++ ++ /* ++ * Disable pull-up on: ++ * RXDV (PA17) => PHY normal mode (not Test mode) ++ * ERX0 (PA14) => PHY ADDR0 ++ * ERX1 (PA15) => PHY ADDR1 ++ * ERX2 (PA25) => PHY ADDR2 ++ * ERX3 (PA26) => PHY ADDR3 ++ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 ++ * ++ * PHY has internal pull-down ++ */ ++ writel(pin_to_mask(AT91_PIN_PA14) | ++ pin_to_mask(AT91_PIN_PA15) | ++ pin_to_mask(AT91_PIN_PA17) | ++ pin_to_mask(AT91_PIN_PA25) | ++ pin_to_mask(AT91_PIN_PA26) | ++ pin_to_mask(AT91_PIN_PA28), ++ pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); ++ ++ rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; ++ ++ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); ++ ++ /* Wait for end hardware reset */ ++ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); ++ ++ /* Restore NRST value */ ++ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | ++ (rstc) | ++ AT91_RSTC_URSTEN); ++ ++ /* Re-enable pull-up */ ++ writel(pin_to_mask(AT91_PIN_PA14) | ++ pin_to_mask(AT91_PIN_PA15) | ++ pin_to_mask(AT91_PIN_PA17) | ++ pin_to_mask(AT91_PIN_PA25) | ++ pin_to_mask(AT91_PIN_PA26) | ++ pin_to_mask(AT91_PIN_PA28), ++ pin_to_controller(AT91_PIN_PA0) + PIO_PUER); ++ ++ at91_macb_hw_init(); ++} ++#endif ++ ++int board_init(void) ++{ ++ /* Enable Ctrlc */ ++ console_init_f(); ++ ++ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK; ++ ++ /* adress of boot parameters */ ++ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; ++ ++ at91_serial_hw_init(); ++#ifdef CONFIG_HAS_DATAFLASH ++ at91_spi0_hw_init((1 << 0) | (1 << 1)); ++#endif ++#ifdef CONFIG_MACB ++ at91sam9260ek_macb_hw_init(); ++#endif ++ ++ return 0; ++} ++ ++int dram_init(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; ++ return 0; ++} ++ ++#ifdef CONFIG_RESET_PHY_R ++void reset_phy(void) ++{ ++#ifdef CONFIG_MACB ++ /* ++ * Initialize ethernet HW addr prior to starting Linux, ++ * needed for nfsroot ++ */ ++ eth_init(gd->bd); ++#endif ++} ++#endif ++ ++int board_eth_init(bd_t *bis) ++{ ++ int rc = 0; ++#ifdef CONFIG_MACB ++ rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); ++#endif ++ return rc; ++} ++ ++void show_boot_progress (int val){} +diff --git a/board/acmesystems/netusg20/partition.c b/board/acmesystems/netusg20/partition.c +new file mode 100644 +index 0000000..7d79e53 +--- /dev/null ++++ b/board/acmesystems/netusg20/partition.c +@@ -0,0 +1,39 @@ ++/* ++ * (C) Copyright 2008 ++ * Ulf Samuelsson ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++#include ++#include ++#include ++#include ++ ++AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; ++ ++struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { ++ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1} ++}; ++ ++/*define the area offsets*/ ++dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { ++ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, ++ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, ++ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, ++ {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, ++ {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, ++}; +diff --git a/include/configs/netusg20.h b/include/configs/netusg20.h +new file mode 100644 +index 0000000..99b4f12 +--- /dev/null ++++ b/include/configs/netusg20.h +@@ -0,0 +1,181 @@ ++/* ++ * (C) Copyright 2007-2008 ++ * Stelian Pop ++ * Lead Tech Design ++ * ++ * Configuation settings for the NetusG20 boards. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_AT91_LEGACY ++ ++/* ARM asynchronous clock */ ++#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ ++#define CONFIG_SYS_HZ 1000 ++ ++#define CONFIG_DISPLAY_CPUINFO ++ ++#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ ++#define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC*/ ++#define CONFIG_NETUSG20 1 ++ ++#define CONFIG_ARCH_CPU_INIT ++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ ++ ++#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ ++#define CONFIG_SETUP_MEMORY_TAGS 1 ++#define CONFIG_INITRD_TAG 1 ++ ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SKIP_RELOCATE_UBOOT ++ ++/* ++ * Hardware drivers ++ */ ++#define CONFIG_AT91_GPIO 1 ++#define CONFIG_ATMEL_USART 1 ++#undef CONFIG_USART0 ++#undef CONFIG_USART1 ++#undef CONFIG_USART2 ++#define CONFIG_USART3 1 /* USART 3 is DBGU */ ++ ++/* LED */ ++#define CONFIG_AT91_LED ++#define CONFIG_RED_LED AT91_PIN_PA9 /* this is the power led */ ++#define CONFIG_GREEN_LED AT91_PIN_PA6 /* this is the user led */ ++ ++#define CONFIG_BOOTDELAY 3 ++ ++/* ++ * BOOTP options ++ */ ++#define CONFIG_BOOTP_BOOTFILESIZE 1 ++#define CONFIG_BOOTP_BOOTPATH 1 ++#define CONFIG_BOOTP_GATEWAY 1 ++#define CONFIG_BOOTP_HOSTNAME 1 ++ ++/* ++ * Command line configuration. ++ */ ++#include ++#undef CONFIG_CMD_BDI ++#undef CONFIG_CMD_FPGA ++#undef CONFIG_CMD_IMI ++#undef CONFIG_CMD_IMLS ++#undef CONFIG_CMD_LOADS ++#undef CONFIG_CMD_SOURCE ++ ++#define CONFIG_CMD_PING 1 ++#define CONFIG_CMD_DHCP 1 ++#define CONFIG_CMD_USB 1 ++ ++/* SDRAM */ ++#define CONFIG_NR_DRAM_BANKS 1 ++#define PHYS_SDRAM 0x20000000 ++#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ ++ ++/* DataFlash */ ++#define CONFIG_ATMEL_DATAFLASH_SPI ++#define CONFIG_HAS_DATAFLASH 1 ++#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) ++#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 ++#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */ ++#define AT91_SPI_CLK 15000000 ++ ++#define DATAFLASH_TCSS (0x22 << 16) ++#define DATAFLASH_TCHS (0x1 << 24) ++ ++/* no NAND flash on this board*/ ++#define CONFIG_SYS_NO_FLASH ++ ++/* Ethernet */ ++#define CONFIG_MACB 1 ++#define CONFIG_RMII 1 ++#define CONFIG_NET_MULTI 1 ++#define CONFIG_NET_RETRY_COUNT 20 ++#define CONFIG_RESET_PHY_R 1 ++ ++/* MMC */ ++#define CONFIG_MMC ++#define CONFIG_CMD_MMC ++#define CONFIG_ATMEL_MCI ++#define CONFIG_CMD_AUTOSCRIPT ++#define CONFIG_CMD_IMI ++#define CONFIG_CMD_SOURCE ++ ++#define MMCI_BASE 0xFFFA8000 ++ ++/* USB */ ++#define CONFIG_USB_ATMEL ++#define CONFIG_USB_OHCI_NEW 1 ++#define CONFIG_DOS_PARTITION 1 ++#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 ++#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ ++#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" ++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 ++#define CONFIG_USB_STORAGE 1 ++ ++#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ ++ ++#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM ++#define CONFIG_SYS_MEMTEST_END 0x23e00000 ++ ++/* Filesystem */ ++#define CONFIG_CMD_FAT 1 ++#define CONFIG_CMD_EXT2 1 ++ ++/* bootstrap + u-boot + env + linux in dataflash on CS1 */ ++#define CONFIG_ENV_IS_IN_DATAFLASH 1 ++#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400) ++#define CONFIG_ENV_OFFSET 0x4200 ++#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET) ++#define CONFIG_ENV_SIZE 0x4200 ++#define CONFIG_BOOTCOMMAND "mmc init; sleep 1; " \ ++ "ext2load mmc 0 0x20000000 uImage; " \ ++ "source 0x20000000" ++#define CONFIG_BOOTARGS "mem=64M console=ttyS0,115200 " \ ++ "root=/dev/mmcblk0p1 rootwait" ++ ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } ++ ++#define CONFIG_SYS_PROMPT "U-Boot> " ++#define CONFIG_SYS_CBSIZE 256 ++#define CONFIG_SYS_MAXARGS 16 ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) ++#define CONFIG_SYS_LONGHELP 1 ++#define CONFIG_CMDLINE_EDITING 1 ++ ++/* ++ * Size of malloc() pool ++ */ ++#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) ++#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ ++ ++#define CONFIG_STACKSIZE (32*1024) /* regular stack */ ++ ++#ifdef CONFIG_USE_IRQ ++#error CONFIG_USE_IRQ not supported ++#endif ++ ++#endif +-- +1.7.0.4 + + diff --git a/target/linux/at91/image/u-boot/patches/200-clock.patch b/target/linux/at91/image/u-boot/patches/200-clock.patch new file mode 100644 index 0000000..fbfb641 --- /dev/null +++ b/target/linux/at91/image/u-boot/patches/200-clock.patch @@ -0,0 +1,24 @@ +The function get_mci_clk_rate is used inside atmel_mci driver +but never defined. Fix this typo. + +Signed-off-by: Claudio Mignanti +--- + drivers/mmc/atmel_mci.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/mmc/atmel_mci.c b/drivers/mmc/atmel_mci.c +index 3946ffe..628aac9 100644 +--- a/drivers/mmc/atmel_mci.c ++++ b/drivers/mmc/atmel_mci.c +@@ -67,7 +67,7 @@ static void mci_set_mode(unsigned long hz, unsigned long blklen) + unsigned long bus_hz; + unsigned long clkdiv; + +- bus_hz = get_mci_clk_rate(); ++ bus_hz = get_mck_clk_rate(); + clkdiv = (bus_hz / hz) / 2 - 1; + + pr_debug("mmc: setting clock %lu Hz, block size %lu\n", +-- +1.7.0.4 + diff --git a/target/linux/at91/image/u-boot/ubclient/Makefile b/target/linux/at91/image/u-boot/ubclient/Makefile new file mode 100644 index 0000000..f8ff67c --- /dev/null +++ b/target/linux/at91/image/u-boot/ubclient/Makefile @@ -0,0 +1,15 @@ +# + +all: ubpar + +crc32.c: + ln -s ../lib_generic/crc32.c ./ + +%.o: %.c + $(CC) -I ../include $(CFLAGS) $(EXTRA_FLAGS) -DLAN_IP=$(LAN_IP) -DLAN_SERVERIP=$(LAN_SERVERIP) -c -o $@ $^ + +ubpar: ubpar.o crc32.o + $(CC) -o $@ $^ + +clean: + rm -f *.o ubpar diff --git a/target/linux/at91/image/u-boot/ubclient/ubpar.c b/target/linux/at91/image/u-boot/ubclient/ubpar.c new file mode 100644 index 0000000..edc5b2c --- /dev/null +++ b/target/linux/at91/image/u-boot/ubclient/ubpar.c @@ -0,0 +1,135 @@ +/* + * ubparams.c + * + * Generate a u-boot parameter block with correct crc + * + * (C) 1007 Guthrie Consulting + * hamish@prodigi.ch + * + */ + +#include +#include +#include + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif +#define __ASM_STUB_PROCESSOR_H__ +#include +#undef __ASSEMBLY__ +#include + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); + +#if !defined(ENV_CRC) +#define ENV_CRC ~0 +#endif + +#ifdef LAN_IP + #warning LAN_IP +#else + #warning LAN_IP NOT DEFINED +#endif +#ifdef LAN_SERVERIP + #warning LAN_SERVERIP +#else + #warning LAN_SERVERIP NOT DEFINED +#endif + +static char *environment[] = { + "bootdelay=3\0" + "baudrate=115200\0" + "stdin=serial\0" + "stdout=serial\0" + "stderr=serial\0" + "fbargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" + "rdba=setenv bootargs root=/dev/ram rw initrd=0x21200000,6000000 ramdisk_size=20000 console=/dev/ttyS0,115200,mem=32M\0" + "rdram=run rdba; tftp 21000000 uImage; tftp 21200000 root.squashfs; bootm 21000000\0" + "flash=run fbargs; bootm 0xc0042000\0" + "bootargs=setenv bootargs root=/dev/mtdblock3 ro console=/dev/ttyS0,115200,mem=32M\0" + "bootcmd=bootm 0xc0042000\0" + "ipaddr=" MK_STR(LAN_IP) "\0" + "serverip=" MK_STR(LAN_SERVERIP) "\0" + "\0" + }; + +int main(int argc, char *argv[]) { + env_t *envptr; + char *src, *srcptr; + char *dataptr; + FILE *params; + int argfail = 1; + char newmac[30]; + char newser[30]; + int paramlen = 0; + int progmac = 0; + int progser = 0; + + if (argc < 3) { + printf ("Invalid arguments\n"); + return 1; + } + + switch (argc) { + case 5: + if (strcmp(argv[3], "--serial") == 0) { + argfail = 0; + sprintf(newser, "serial#=%s", argv[4]); + progser = 1; + } + case 3: + if (strcmp(argv[1], "--mac") == 0) { + argfail = 0; + sprintf(newmac, "ethaddr=%s", argv[2]); + progmac = 1; + } + else + argfail = 1; + } + + if (argfail) { + printf("Invalid arguments\n"); + return 1; + } + + + src = srcptr = *environment; + envptr = (env_t *)malloc(CFG_ENV_SIZE); + dataptr = (char *)envptr + ENV_HEADER_SIZE; + + while(*srcptr) { + //printf("%d, %s\n", strlen(srcptr), srcptr); + paramlen += strlen(srcptr) + 1; + srcptr += strlen(srcptr) + 1; + } + + printf("Make u-boot params\n"); + printf("Params size is %d\n", CFG_ENV_SIZE); + + memset(envptr, 0, CFG_ENV_SIZE); + memcpy(dataptr, src, paramlen); + dataptr += paramlen; + + if (progmac) { + memcpy(dataptr, newmac, strlen(newmac)); + dataptr += strlen(newmac) + 1; + } + + if (progser) { + memcpy(dataptr, newser, strlen(newser)); + dataptr += strlen(newser) + 1; + } + + envptr->crc = crc32(0, envptr->data, ENV_SIZE); + + params = fopen("/dev/mtd1", "w"); + fwrite(envptr, CFG_ENV_SIZE, 1, params); + fclose(params); + + free(envptr); + return 0; +} diff --git a/target/linux/at91/image/ubinize.cfg b/target/linux/at91/image/ubinize.cfg new file mode 100644 index 0000000..e4149ec --- /dev/null +++ b/target/linux/at91/image/ubinize.cfg @@ -0,0 +1,13 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.ubifs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs +# Autoresize volume at first mount +vol_flags=autoresize diff --git a/target/linux/at91/legacy/config-default b/target/linux/at91/legacy/config-default new file mode 100644 index 0000000..12beb46 --- /dev/null +++ b/target/linux/at91/legacy/config-default @@ -0,0 +1,33 @@ +# CONFIG_ARCH_AT91RM9200 is not set +# CONFIG_ARCH_AT91SAM9260 is not set +# CONFIG_ARCH_AT91SAM9261 is not set +# CONFIG_ARCH_AT91SAM9263 is not set +# CONFIG_ARCH_AT91SAM9G10 is not set +# CONFIG_ARCH_AT91SAM9G20 is not set +# CONFIG_ARCH_AT91SAM9G45 is not set +# CONFIG_ARCH_AT91SAM9RL is not set +CONFIG_ARCH_AT91_NONE=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_TLB_V4WBI=y +# CONFIG_SOC_AT91RM9200 is not set +CONFIG_SOC_AT91SAM9=y +CONFIG_SOC_AT91SAM9260=y +CONFIG_SOC_AT91SAM9261=y +CONFIG_SOC_AT91SAM9263=y +CONFIG_SOC_AT91SAM9G45=y +CONFIG_SOC_AT91SAM9N12=y +CONFIG_SOC_AT91SAM9RL=y +CONFIG_SOC_AT91SAM9X5=y +CONFIG_SOC_SAM_V4_V5=y +# CONFIG_SOC_SAM_V7 is not set diff --git a/target/linux/at91/legacy/profiles/00-default.mk b/target/linux/at91/legacy/profiles/00-default.mk new file mode 100644 index 0000000..3ff040d --- /dev/null +++ b/target/linux/at91/legacy/profiles/00-default.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef + +$(eval $(call Profile,Default)) diff --git a/target/linux/at91/legacy/profiles/atmel.mk b/target/linux/at91/legacy/profiles/atmel.mk new file mode 100644 index 0000000..4b14f93 --- /dev/null +++ b/target/linux/at91/legacy/profiles/atmel.mk @@ -0,0 +1,86 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/AT91SAM9263EK + NAME:=Atmel AT91SAM9263-EK +endef +define Profile/AT91SAM9263EK/Description + Atmel AT91SAM9263-EK eval board +endef +$(eval $(call Profile,AT91SAM9263EK)) + + +define Profile/AT91SAM9G15EK + NAME:=Atmel AT91SAM9G15-EK +endef +define Profile/AT91SAM9G15EK/Description + Atmel AT91SAM9G15-EK eval board +endef +$(eval $(call Profile,AT91SAM9G15EK)) + + +define Profile/AT91SAM9G20EK + NAME:=Atmel AT91SAM9G20-EK +endef +define Profile/AT91SAM9G20EK/Description + Atmel AT91SAM9G20-EK eval board +endef +$(eval $(call Profile,AT91SAM9G20EK)) + + +define Profile/AT91SAM9G20EK-2MMC + NAME:=Atmel AT91SAM9G20-EK 2MMC +endef +define Profile/AT91SAM9G20EK-2MMC/Description + Atmel AT91SAM9G20-EK eval board with 2 MMC +endef +$(eval $(call Profile,AT91SAM9G20EK-2MMC)) + + +define Profile/AT91SAM9G25EK + NAME:=Atmel AT91SAM9G25-EK +endef +define Profile/AT91SAM9G25EK/Description + Atmel AT91SAM9G25-EK eval board +endef +$(eval $(call Profile,AT91SAM9G25EK)) + + +define Profile/AT91SAM9G35EK + NAME:=Atmel AT91SAM9G35-EK +endef +define Profile/AT91SAM9G35EK/Description + Atmel AT91SAM9G35-EK eval board +endef +$(eval $(call Profile,AT91SAM9G35EK)) + + +define Profile/AT91SAM9M10G45EK + NAME:=Atmel AT91SAM9M10G45-EK +endef +define Profile/AT91SAM9M10G45EK/Description + Atmel AT91SAM9M10G45-EK eval board +endef +$(eval $(call Profile,AT91SAM9M10G45EK)) + + +define Profile/AT91SAM9X25EK + NAME:=Atmel AT91SAM9X25-EK +endef +define Profile/AT91SAM9X25EK/Description + Atmel AT91SAM9X25-EK eval board +endef +$(eval $(call Profile,AT91SAM9X25EK)) + + +define Profile/AT91SAM9X35EK + NAME:=Atmel AT91SAM9X35-EK +endef +define Profile/AT91SAM9X35EK/Description + Atmel AT91SAM9X35-EK eval board +endef +$(eval $(call Profile,AT91SAM9X35EK)) diff --git a/target/linux/at91/legacy/profiles/calamp.mk b/target/linux/at91/legacy/profiles/calamp.mk new file mode 100644 index 0000000..33f78e1 --- /dev/null +++ b/target/linux/at91/legacy/profiles/calamp.mk @@ -0,0 +1,23 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/LMU5000 + NAME:=CalAmp LMU5000 + PACKAGES:= \ + kmod-rtc-pcf2123 \ + kmod-usb-acm \ + kmod-usb-serial \ + kmod-usb-serial-option \ + kmod-usb-serial-sierrawireless \ + kmod-gpio-mcp23s08 +endef + +define Profile/LMU5000/Description + CalAmp LMU5000 +endef + +$(eval $(call Profile,LMU5000)) diff --git a/target/linux/at91/legacy/target.mk b/target/linux/at91/legacy/target.mk new file mode 100644 index 0000000..a3d99bb --- /dev/null +++ b/target/linux/at91/legacy/target.mk @@ -0,0 +1,7 @@ +BOARDNAME:=Legacy (ARMv5) +CPU_TYPE:=arm926ej-s + +define Target/Description + Build generic firmware for legacy Atmel AT91 platforms + using the ARMv5 instruction set. +endef diff --git a/target/linux/at91/modules.mk b/target/linux/at91/modules.mk new file mode 100644 index 0000000..6cfc3e4 --- /dev/null +++ b/target/linux/at91/modules.mk @@ -0,0 +1,86 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/mmc-at91 + SUBMENU:=$(OTHER_MENU) + TITLE:=MMC/SD Card Support on AT91 + DEPENDS:=@TARGET_at91 +kmod-mmc + KCONFIG:=CONFIG_MMC_AT91 + FILES:=$(LINUX_DIR)/drivers/mmc/host/at91_mci.ko + AUTOLOAD:=$(call AutoLoad,90,at91_mci,1) +endef + +define KernelPackage/mmc-at91/description + Kernel support for MMC/SD cards on the AT91 target +endef + +$(eval $(call KernelPackage,mmc-at91)) + +define KernelPackage/pwm-atmel + SUBMENU:=$(OTHER_MENU) + TITLE:=PWM on atmel SoC + DEPENDS:=@TARGET_at91 + KCONFIG:=CONFIG_ATMEL_PWM + FILES:=$(LINUX_DIR)/drivers/misc/atmel_pwm.ko + AUTOLOAD:=$(call AutoLoad,51,atmel_pwm) +endef + +define KernelPackage/pwm-atmel/description + Kernel module to use the PWM channel on ATMEL SoC +endef + +$(eval $(call KernelPackage,pwm-atmel)) + +define KernelPackage/at91-adc + SUBMENU:=$(OTHER_MENU) + TITLE:=ADC on atmel SoC + DEPENDS:=@TARGET_at91 +kmod-iio-core +kmod-input-core + KCONFIG:=CONFIG_AT91_ADC + FILES:=$(LINUX_DIR)/drivers/iio/adc/at91_adc.ko + AUTOLOAD:=$(call AutoLoad,40,at91_adc) +endef + +define KernelPackage/at91-adc/description + Kernel module to use the ADC channels of SoC +endef + +$(eval $(call KernelPackage,at91-adc)) + +define KernelPackage/at91-udc + SUBMENU:=$(USB_MENU) + TITLE:=USB Device Controller on atmel SoC + DEPENDS:=@TARGET_at91 +kmod-usb-gadget + KCONFIG:=CONFIG_USB_AT91 +ifneq ($(wildcard $(LINUX_DIR)/drivers/usb/gadget/udc/at91_udc.ko),) + FILES:=$(LINUX_DIR)/drivers/usb/gadget/udc/at91_udc.ko +else + FILES:=$(LINUX_DIR)/drivers/usb/gadget/at91_udc.ko +endif + AUTOLOAD:=$(call AutoLoad,51,at91_udc) +endef + +define KernelPackage/at91-adc/description + Kernel module to use the USB Device controller for Atmel AT91 +endef + +$(eval $(call KernelPackage,at91-udc)) + +I2C_AT91_MODULES:=\ + CONFIG_I2C_AT91:drivers/i2c/busses/i2c-at91 + +define KernelPackage/at91-i2c + $(call i2c_defaults,$(I2C_AT91_MODULES),55) + TITLE:=I2C (TWI) master driver for Atmel AT91 + DEPENDS:=@TARGET_at91 +kmod-i2c-core +endef + +define KernelPackage/at91-i2c/description + Kernel module to use the I2C (TWI) master driver for Atmel AT91 +endef + +$(eval $(call KernelPackage,at91-i2c)) + diff --git a/target/linux/at91/patches/100-ARM-at91-build-dtb-for-LMU5000.patch b/target/linux/at91/patches/100-ARM-at91-build-dtb-for-LMU5000.patch new file mode 100644 index 0000000..8852b6a --- /dev/null +++ b/target/linux/at91/patches/100-ARM-at91-build-dtb-for-LMU5000.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb + dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb + # sam9g45 + dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb ++dtb-$(CONFIG_ARCH_AT91) += lmu5000.dtb + dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb + # sam9n12 + dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb diff --git a/target/linux/at91/patches/101-ARM-at91-build-dtb-for-q5xr5.patch b/target/linux/at91/patches/101-ARM-at91-build-dtb-for-q5xr5.patch new file mode 100644 index 0000000..b5a9b68 --- /dev/null +++ b/target/linux/at91/patches/101-ARM-at91-build-dtb-for-q5xr5.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb + dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb + # sam9g20 + dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb ++dtb-$(CONFIG_ARCH_AT91) += at91-q5xr5.dtb + dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb + dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb + dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb diff --git a/target/linux/at91/patches/200-ARM-at91-udc-clockfix-backport.patch b/target/linux/at91/patches/200-ARM-at91-udc-clockfix-backport.patch new file mode 100644 index 0000000..32e1ac5 --- /dev/null +++ b/target/linux/at91/patches/200-ARM-at91-udc-clockfix-backport.patch @@ -0,0 +1,82 @@ +--- a/drivers/usb/gadget/udc/at91_udc.c ++++ b/drivers/usb/gadget/udc/at91_udc.c +@@ -870,8 +870,6 @@ static void clk_on(struct at91_udc *udc) + return; + udc->clocked = 1; + +- if (IS_ENABLED(CONFIG_COMMON_CLK)) +- clk_enable(udc->uclk); + clk_enable(udc->iclk); + clk_enable(udc->fclk); + } +@@ -884,8 +882,6 @@ static void clk_off(struct at91_udc *udc + udc->gadget.speed = USB_SPEED_UNKNOWN; + clk_disable(udc->fclk); + clk_disable(udc->iclk); +- if (IS_ENABLED(CONFIG_COMMON_CLK)) +- clk_disable(udc->uclk); + } + + /* +@@ -1766,27 +1762,18 @@ static int at91udc_probe(struct platform + udc_reinit(udc); + + /* get interface and function clocks */ +- udc->iclk = clk_get(dev, "udc_clk"); +- udc->fclk = clk_get(dev, "udpck"); +- if (IS_ENABLED(CONFIG_COMMON_CLK)) +- udc->uclk = clk_get(dev, "usb_clk"); +- if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk) || +- (IS_ENABLED(CONFIG_COMMON_CLK) && IS_ERR(udc->uclk))) { ++ udc->iclk = clk_get(dev, "pclk"); ++ udc->fclk = clk_get(dev, "hclk"); ++ if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk)) { + DBG("clocks missing\n"); + retval = -ENODEV; + goto fail1; + } + +- /* don't do anything until we have both gadget driver and VBUS */ +- if (IS_ENABLED(CONFIG_COMMON_CLK)) { +- clk_set_rate(udc->uclk, 48000000); +- retval = clk_prepare(udc->uclk); +- if (retval) +- goto fail1; +- } ++ clk_set_rate(udc->fclk, 48000000); + retval = clk_prepare(udc->fclk); + if (retval) +- goto fail1a; ++ goto fail1; + + retval = clk_prepare_enable(udc->iclk); + if (retval) +@@ -1860,12 +1847,7 @@ fail1c: + clk_unprepare(udc->iclk); + fail1b: + clk_unprepare(udc->fclk); +-fail1a: +- if (IS_ENABLED(CONFIG_COMMON_CLK)) +- clk_unprepare(udc->uclk); + fail1: +- if (IS_ENABLED(CONFIG_COMMON_CLK) && !IS_ERR(udc->uclk)) +- clk_put(udc->uclk); + if (!IS_ERR(udc->fclk)) + clk_put(udc->fclk); + if (!IS_ERR(udc->iclk)) +@@ -1911,15 +1893,11 @@ static int __exit at91udc_remove(struct + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, resource_size(res)); + +- if (IS_ENABLED(CONFIG_COMMON_CLK)) +- clk_unprepare(udc->uclk); + clk_unprepare(udc->fclk); + clk_unprepare(udc->iclk); + + clk_put(udc->iclk); + clk_put(udc->fclk); +- if (IS_ENABLED(CONFIG_COMMON_CLK)) +- clk_put(udc->uclk); + + return 0; + } diff --git a/target/linux/at91/patches/201-ARM-at91-usb-determine_rate-backport.patch b/target/linux/at91/patches/201-ARM-at91-usb-determine_rate-backport.patch new file mode 100644 index 0000000..d083628 --- /dev/null +++ b/target/linux/at91/patches/201-ARM-at91-usb-determine_rate-backport.patch @@ -0,0 +1,20 @@ +--- a/drivers/clk/at91/clk-usb.c ++++ b/drivers/clk/at91/clk-usb.c +@@ -59,7 +59,7 @@ static unsigned long at91sam9x5_clk_usb_ + static long at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *best_parent_rate, +- struct clk_hw **best_parent_hw) ++ struct clk **best_parent_clk) + { + struct clk *parent = NULL; + long best_rate = -EINVAL; +@@ -91,7 +91,7 @@ static long at91sam9x5_clk_usb_determine + best_rate = tmp_rate; + best_diff = tmp_diff; + *best_parent_rate = tmp_parent_rate; +- *best_parent_hw = __clk_get_hw(parent); ++ *best_parent_clk = parent; + } + + if (!best_diff || tmp_rate < rate) diff --git a/target/linux/at91/patches/805-free_some_portc_pins.patch b/target/linux/at91/patches/805-free_some_portc_pins.patch new file mode 100644 index 0000000..a9694d1 --- /dev/null +++ b/target/linux/at91/patches/805-free_some_portc_pins.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-at91/at91sam9260_devices.c ++++ b/arch/arm/mach-at91/at91sam9260_devices.c +@@ -507,7 +507,7 @@ static struct platform_device at91sam926 + .num_resources = ARRAY_SIZE(spi1_resources), + }; + +-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 }; ++static const unsigned spi1_standard_cs[2] = { AT91_PIN_PB3, AT91_PIN_PC5 }; + + void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) + { diff --git a/target/linux/at91/patches/901-AT91-flexibity-default-leds-to-heartbeat.patch b/target/linux/at91/patches/901-AT91-flexibity-default-leds-to-heartbeat.patch new file mode 100644 index 0000000..1da2e4d --- /dev/null +++ b/target/linux/at91/patches/901-AT91-flexibity-default-leds-to-heartbeat.patch @@ -0,0 +1,60 @@ +--- a/arch/arm/mach-at91/board-flexibity.c ++++ b/arch/arm/mach-at91/board-flexibity.c +@@ -90,49 +90,49 @@ static struct gpio_led flexibity_leds[] + .name = "usb1:green", + .gpio = AT91_PIN_PA12, + .active_low = 1, +- .default_trigger = "default-on", ++ .default_trigger = "heartbeat", + }, + { + .name = "usb1:red", + .gpio = AT91_PIN_PA13, + .active_low = 1, +- .default_trigger = "default-on", ++ .default_trigger = "heartbeat", + }, + { + .name = "usb2:green", + .gpio = AT91_PIN_PB26, + .active_low = 1, +- .default_trigger = "default-on", ++ .default_trigger = "heartbeat", + }, + { + .name = "usb2:red", + .gpio = AT91_PIN_PB27, + .active_low = 1, +- .default_trigger = "default-on", ++ .default_trigger = "heartbeat", + }, + { + .name = "usb3:green", + .gpio = AT91_PIN_PC8, + .active_low = 1, +- .default_trigger = "default-on", ++ .default_trigger = "heartbeat", + }, + { + .name = "usb3:red", + .gpio = AT91_PIN_PC6, + .active_low = 1, +- .default_trigger = "default-on", ++ .default_trigger = "heartbeat", + }, + { + .name = "usb4:green", + .gpio = AT91_PIN_PB4, + .active_low = 1, +- .default_trigger = "default-on", ++ .default_trigger = "heartbeat", + }, + { + .name = "usb4:red", + .gpio = AT91_PIN_PB5, + .active_low = 1, +- .default_trigger = "default-on", ++ .default_trigger = "heartbeat", + } + }; + diff --git a/target/linux/at91/sama5d3/config-default b/target/linux/at91/sama5d3/config-default new file mode 100644 index 0000000..62aef01 --- /dev/null +++ b/target/linux/at91/sama5d3/config-default @@ -0,0 +1,13 @@ +CONFIG_SOC_SAMA5=y +# CONFIG_SOC_SAM_V4_V5 is not set +CONFIG_SOC_SAM_V7=y +CONFIG_SOC_SAMA5D3=y +CONFIG_SOC_SAMA5D4=y +CONFIG_MACH_SAMA5_DT=y +# CONFIG_ARM_LPAE is not set +# CONFIG_ARM_THUMBEE is not set +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +# CONFIG_THUMB2_KERNEL is not set +# CONFIG_XEN is not set diff --git a/target/linux/at91/sama5d3/profiles/atmel.mk b/target/linux/at91/sama5d3/profiles/atmel.mk new file mode 100644 index 0000000..8a9b1ef --- /dev/null +++ b/target/linux/at91/sama5d3/profiles/atmel.mk @@ -0,0 +1,14 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/AT91SAMA5D3XPLAINED + NAME:=Atmel AT91SAMA5D3XPLAINED +endef +define Profile/AT91SAMA5D3XPLAINED/Description + Atmel AT91SAMA5D3EXPLAINED eval board +endef +$(eval $(call Profile,AT91SAMA5D3XPLAINED)) diff --git a/target/linux/at91/sama5d3/target.mk b/target/linux/at91/sama5d3/target.mk new file mode 100644 index 0000000..0319f4b --- /dev/null +++ b/target/linux/at91/sama5d3/target.mk @@ -0,0 +1,9 @@ +BOARDNAME:=SAMA5D3 (Cortex-A5) +CPU_TYPE:=cortex-a5 + +DEFAULT_PACKAGES += kmod-usb2 + +define Target/Description + Build generic firmware for SAMA5D3 AT91 platforms + using the ARMv7 instruction set. +endef diff --git a/target/linux/ath25/Makefile b/target/linux/ath25/Makefile new file mode 100644 index 0000000..ae867e9 --- /dev/null +++ b/target/linux/ath25/Makefile @@ -0,0 +1,25 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips +BOARD:=ath25 +BOARDNAME:=Atheros AR231x/AR5312 +FEATURES:=squashfs low_mem +MAINTAINER:=Sergey Ryazanov + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += wpad-mini kmod-ath5k swconfig kmod-gpio-button-hotplug + +define Target/Description + Build firmware images for Atheros SoC boards +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/ath25/base-files/etc/config/system b/target/linux/ath25/base-files/etc/config/system new file mode 100644 index 0000000..1d29ad8 --- /dev/null +++ b/target/linux/ath25/base-files/etc/config/system @@ -0,0 +1,23 @@ +config system + option hostname OpenWrt + option timezone UTC + +config timeserver ntp + list server 0.openwrt.pool.ntp.org + list server 1.openwrt.pool.ntp.org + list server 2.openwrt.pool.ntp.org + list server 3.openwrt.pool.ntp.org + +config button + option button reset + option action released + option handler "logger reboot" + option min 0 + option max 4 + +config button + option button reset + option action released + option handler "logger factory default" + option min 5 + option max 30 diff --git a/target/linux/ath25/base-files/etc/hotplug.d/button/00-button b/target/linux/ath25/base-files/etc/hotplug.d/button/00-button new file mode 100644 index 0000000..63cc217 --- /dev/null +++ b/target/linux/ath25/base-files/etc/hotplug.d/button/00-button @@ -0,0 +1,24 @@ +. /lib/functions.sh +do_button () { + local button + local action + local handler + local min + local max + + config_get button $1 button + config_get action $1 action + config_get handler $1 handler + config_get min $1 min + config_get max $1 max + + [ "$ACTION" = "$action" -a "$BUTTON" = "$button" -a -n "$handler" ] && { + [ -z "$min" -o -z "$max" ] && eval $handler + [ -n "$min" -a -n "$max" ] && { + [ $min -le $SEEN -a $max -ge $SEEN ] && eval $handler + } + } +} + +config_load system +config_foreach do_button button diff --git a/target/linux/ath25/base-files/etc/uci-defaults/01_leds b/target/linux/ath25/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..076a04b --- /dev/null +++ b/target/linux/ath25/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,11 @@ +#!/bin/sh +# Copyright 2012 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh + +ucidef_set_led_netdev "wlan" "wlan" "wlan" "wlan0" + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/ath25/base-files/etc/uci-defaults/02_network b/target/linux/ath25/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..7e91e6a --- /dev/null +++ b/target/linux/ath25/base-files/etc/uci-defaults/02_network @@ -0,0 +1,45 @@ +#!/bin/sh +if [ -e "/sys/bus/mdio_bus/drivers/IC+ IP175C/0:00" -o \ + -e "/sys/bus/mdio_bus/drivers/IC+ IP17xx/0:00" ] && \ + [ -x /sbin/swconfig ]; +then + uci batch </dev/null + ifconfig $pi_ifname down + elif [ -n "$pi_ifname" ]; then + ifconfig $pi_ifname 0.0.0.0 + fi +} diff --git a/target/linux/ath25/base-files/lib/upgrade/platform.sh b/target/linux/ath25/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..d44b8fa --- /dev/null +++ b/target/linux/ath25/base-files/lib/upgrade/platform.sh @@ -0,0 +1,76 @@ +CI_BLKSZ=65536 +CI_LDADR=0x80041000 + +platform_find_partitions() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + vmlinux.bin.l7|kernel|linux|rootfs) + if [ -z "$first" ]; then + first="$name" + else + echo "$erasesize:$first:$name" + break + fi + ;; + esac + done < /proc/mtd +} + +platform_find_kernelpart() { + local part + for part in "${1%:*}" "${1#*:}"; do + case "$part" in + vmlinux.bin.l7|kernel|linux) + echo "$part" + break + ;; + esac + done +} + +platform_check_image() { + [ "$#" -gt 1 ] && return 1 + + case "$(get_magic_word "$1")" in + # Combined Image + 4349) + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + + if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then + return 0 + else + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + ;; + *) + echo "Invalid image. Use combined .img files on this platform" + return 1 + ;; + esac +} + +platform_do_upgrade() { + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}" + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local kern_blocks=$(($kern_length / $CI_BLKSZ)) + local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ)) + + if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \ + [ ${kern_blocks:-0} -gt 0 ] && \ + [ ${root_blocks:-0} -gt ${kern_blocks:-0} ] && \ + [ ${erase_size:-0} -gt 0 ]; + then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + ( dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \ + dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \ + mtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions + fi +} diff --git a/target/linux/ath25/config-3.18 b/target/linux/ath25/config-3.18 new file mode 100644 index 0000000..8856041 --- /dev/null +++ b/target/linux/ath25/config-3.18 @@ -0,0 +1,136 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR2315_WDT=y +CONFIG_AR8216_PHY=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ATH25=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_AR2315=y +CONFIG_GPIO_AR5312=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IP17XX_PHY=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_GPIO=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_AR2315=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_MYLOADER_PARTS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3 +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MVSWITCH_PHY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_AR231X=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_AR2315=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=1 +CONFIG_SOC_AR2315=y +CONFIG_SOC_AR5312=y +# CONFIG_SWAP is not set +CONFIG_SWCONFIG=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ath25/image/Makefile b/target/linux/ath25/image/Makefile new file mode 100644 index 0000000..6bdb3c4 --- /dev/null +++ b/target/linux/ath25/image/Makefile @@ -0,0 +1,60 @@ +# +# Copyright (C) 2006-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Image/BuildKernel + cp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf + gzip -9n -c $(KDIR)/vmlinux > $(KDIR)/vmlinux.bin.gz + $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.bin.l7 + dd if=$(KDIR)/vmlinux.bin.l7 of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma bs=65536 conv=sync + dd if=$(KDIR)/vmlinux.bin.gz of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.gz bs=65536 conv=sync +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +endef + +define Image/Build + $(call Image/Build/$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync + + -$(STAGING_DIR_HOST)/bin/mkfwimage \ + -B XS2 -v XS2.ar2316.OpenWrt.$(REVISION) \ + -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt2-$(1).bin + + -$(STAGING_DIR_HOST)/bin/mkfwimage \ + -B XS5 -v XS5.ar2313.OpenWrt.$(REVISION) \ + -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt5-$(1).bin + + -$(STAGING_DIR_HOST)/bin/mkfwimage \ + -B XS2-8 -v XS2.ar2316.OpenWrt.$(REVISION) \ + -k $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma \ + -r $(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + -o $(BIN_DIR)/$(IMG_PREFIX)-ubnt2-pico2-$(1).bin + + -$(STAGING_DIR_HOST)/bin/mkmylofw -B np25g \ + -p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/vmlinux.bin.gz \ + -p0x150000:0x2a0000:::rootfs:$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + $(BIN_DIR)/$(IMG_PREFIX)-np25g-$(1).bin + + -$(STAGING_DIR_HOST)/bin/mkmylofw -B wpe53g \ + -p0x020000:0x130000:ah:0x80041000:linux:$(KDIR)/vmlinux.bin.gz \ + -p0x150000:0x2a0000:::rootfs:$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) \ + $(BIN_DIR)/$(IMG_PREFIX)-wpe53g-$(1).bin + + -sh $(TOPDIR)/scripts/combined-image.sh \ + "$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma" \ + "$(BIN_DIR)/$(IMG_PREFIX)-root.$(1)" \ + "$(BIN_DIR)/$(IMG_PREFIX)-combined.$(1).img" +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/ath25/patches-3.18/010-board.patch b/target/linux/ath25/patches-3.18/010-board.patch new file mode 100644 index 0000000..03332b6 --- /dev/null +++ b/target/linux/ath25/patches-3.18/010-board.patch @@ -0,0 +1,2189 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -96,6 +96,19 @@ config AR7 + Support for the Texas Instruments AR7 System-on-a-Chip + family: TNETD7100, 7200 and 7300. + ++config ATH25 ++ bool "Atheros AR231x/AR531x SoC support" ++ select CEVT_R4K ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select IRQ_CPU ++ select IRQ_DOMAIN ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ help ++ Support for Atheros AR231x and Atheros AR531x based boards ++ + config ATH79 + bool "Atheros AR71XX/AR724X/AR913X based boards" + select ARCH_REQUIRE_GPIOLIB +@@ -835,6 +848,7 @@ config MIPS_PARAVIRT + endchoice + + source "arch/mips/alchemy/Kconfig" ++source "arch/mips/ath25/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm47xx/Kconfig" + source "arch/mips/bcm63xx/Kconfig" +--- a/arch/mips/Kbuild.platforms ++++ b/arch/mips/Kbuild.platforms +@@ -2,6 +2,7 @@ + + platforms += alchemy + platforms += ar7 ++platforms += ath25 + platforms += ath79 + platforms += bcm47xx + platforms += bcm63xx +--- /dev/null ++++ b/arch/mips/ath25/Platform +@@ -0,0 +1,6 @@ ++# ++# Atheros AR531X/AR231X WiSoC ++# ++platform-$(CONFIG_ATH25) += ath25/ ++cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25 ++load-$(CONFIG_ATH25) += 0xffffffff80041000 +--- /dev/null ++++ b/arch/mips/ath25/Kconfig +@@ -0,0 +1,9 @@ ++config SOC_AR5312 ++ bool "Atheros AR5312/AR2312+ SoC support" ++ depends on ATH25 ++ default y ++ ++config SOC_AR2315 ++ bool "Atheros AR2315+ SoC support" ++ depends on ATH25 ++ default y +--- /dev/null ++++ b/arch/mips/ath25/Makefile +@@ -0,0 +1,13 @@ ++# ++# This file is subject to the terms and conditions of the GNU General Public ++# License. See the file "COPYING" in the main directory of this archive ++# for more details. ++# ++# Copyright (C) 2006 FON Technology, SL. ++# Copyright (C) 2006 Imre Kaloz ++# Copyright (C) 2006-2009 Felix Fietkau ++# ++ ++obj-y += board.o prom.o devices.o ++obj-$(CONFIG_SOC_AR5312) += ar5312.o ++obj-$(CONFIG_SOC_AR2315) += ar2315.o +--- /dev/null ++++ b/arch/mips/ath25/board.c +@@ -0,0 +1,234 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void (*ath25_irq_dispatch)(void); ++ ++static inline bool check_radio_magic(const void __iomem *addr) ++{ ++ addr += 0x7a; /* offset for flash magic */ ++ return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5); ++} ++ ++static inline bool check_notempty(const void __iomem *addr) ++{ ++ return __raw_readl(addr) != 0xffffffff; ++} ++ ++static inline bool check_board_data(const void __iomem *addr, bool broken) ++{ ++ /* config magic found */ ++ if (__raw_readl(addr) == ATH25_BD_MAGIC) ++ return true; ++ ++ if (!broken) ++ return false; ++ ++ /* broken board data detected, use radio data to find the ++ * offset, user will fix this */ ++ ++ if (check_radio_magic(addr + 0x1000)) ++ return true; ++ if (check_radio_magic(addr + 0xf8)) ++ return true; ++ ++ return false; ++} ++ ++static const void __iomem * __init find_board_config(const void __iomem *limit, ++ const bool broken) ++{ ++ const void __iomem *addr; ++ const void __iomem *begin = limit - 0x1000; ++ const void __iomem *end = limit - 0x30000; ++ ++ for (addr = begin; addr >= end; addr -= 0x1000) ++ if (check_board_data(addr, broken)) ++ return addr; ++ ++ return NULL; ++} ++ ++static const void __iomem * __init find_radio_config(const void __iomem *limit, ++ const void __iomem *bcfg) ++{ ++ const void __iomem *rcfg, *begin, *end; ++ ++ /* ++ * Now find the start of Radio Configuration data, using heuristics: ++ * Search forward from Board Configuration data by 0x1000 bytes ++ * at a time until we find non-0xffffffff. ++ */ ++ begin = bcfg + 0x1000; ++ end = limit; ++ for (rcfg = begin; rcfg < end; rcfg += 0x1000) ++ if (check_notempty(rcfg) && check_radio_magic(rcfg)) ++ return rcfg; ++ ++ /* AR2316 relocates radio config to new location */ ++ begin = bcfg + 0xf8; ++ end = limit - 0x1000 + 0xf8; ++ for (rcfg = begin; rcfg < end; rcfg += 0x1000) ++ if (check_notempty(rcfg) && check_radio_magic(rcfg)) ++ return rcfg; ++ ++ return NULL; ++} ++ ++/* ++ * NB: Search region size could be larger than the actual flash size, ++ * but this shouldn't be a problem here, because the flash ++ * will simply be mapped multiple times. ++ */ ++int __init ath25_find_config(phys_addr_t base, unsigned long size) ++{ ++ const void __iomem *flash_base, *flash_limit; ++ struct ath25_boarddata *config; ++ unsigned int rcfg_size; ++ int broken_boarddata = 0; ++ const void __iomem *bcfg, *rcfg; ++ u8 *board_data; ++ u8 *radio_data; ++ u8 *mac_addr; ++ u32 offset; ++ ++ flash_base = ioremap_nocache(base, size); ++ flash_limit = flash_base + size; ++ ++ ath25_board.config = NULL; ++ ath25_board.radio = NULL; ++ ++ /* Copy the board and radio data to RAM, because accessing the mapped ++ * memory of the flash directly after booting is not safe */ ++ ++ /* Try to find valid board and radio data */ ++ bcfg = find_board_config(flash_limit, false); ++ ++ /* If that fails, try to at least find valid radio data */ ++ if (!bcfg) { ++ bcfg = find_board_config(flash_limit, true); ++ broken_boarddata = 1; ++ } ++ ++ if (!bcfg) { ++ pr_warn("WARNING: No board configuration data found!\n"); ++ goto error; ++ } ++ ++ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); ++ ath25_board.config = (struct ath25_boarddata *)board_data; ++ memcpy_fromio(board_data, bcfg, 0x100); ++ if (broken_boarddata) { ++ pr_warn("WARNING: broken board data detected\n"); ++ config = ath25_board.config; ++ if (is_zero_ether_addr(config->enet0_mac)) { ++ pr_info("Fixing up empty mac addresses\n"); ++ config->reset_config_gpio = 0xffff; ++ config->sys_led_gpio = 0xffff; ++ random_ether_addr(config->wlan0_mac); ++ config->wlan0_mac[0] &= ~0x06; ++ random_ether_addr(config->enet0_mac); ++ random_ether_addr(config->enet1_mac); ++ } ++ } ++ ++ /* Radio config starts 0x100 bytes after board config, regardless ++ * of what the physical layout on the flash chip looks like */ ++ ++ rcfg = find_radio_config(flash_limit, bcfg); ++ if (!rcfg) { ++ pr_warn("WARNING: Could not find Radio Configuration data\n"); ++ goto error; ++ } ++ ++ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); ++ ath25_board.radio = radio_data; ++ offset = radio_data - board_data; ++ pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg, ++ offset); ++ rcfg_size = BOARD_CONFIG_BUFSZ - offset; ++ memcpy_fromio(radio_data, rcfg, rcfg_size); ++ ++ mac_addr = &radio_data[0x1d * 2]; ++ if (is_broadcast_ether_addr(mac_addr)) { ++ pr_info("Radio MAC is blank; using board-data\n"); ++ ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac); ++ } ++ ++ iounmap(flash_base); ++ ++ return 0; ++ ++error: ++ iounmap(flash_base); ++ return -ENODEV; ++} ++ ++static void ath25_halt(void) ++{ ++ local_irq_disable(); ++ unreachable(); ++} ++ ++void __init plat_mem_setup(void) ++{ ++ _machine_halt = ath25_halt; ++ pm_power_off = ath25_halt; ++ ++ if (is_ar5312()) ++ ar5312_plat_mem_setup(); ++ else ++ ar2315_plat_mem_setup(); ++ ++ /* Disable data watchpoints */ ++ write_c0_watchlo0(0); ++} ++ ++asmlinkage void plat_irq_dispatch(void) ++{ ++ ath25_irq_dispatch(); ++} ++ ++void __init plat_time_init(void) ++{ ++ if (is_ar5312()) ++ ar5312_plat_time_init(); ++ else ++ ar2315_plat_time_init(); ++} ++ ++unsigned int __cpuinit get_c0_compare_int(void) ++{ ++ return CP0_LEGACY_COMPARE_IRQ; ++} ++ ++void __init arch_init_irq(void) ++{ ++ clear_c0_status(ST0_IM); ++ mips_cpu_irq_init(); ++ ++ /* Initialize interrupt controllers */ ++ if (is_ar5312()) ++ ar5312_arch_init_irq(); ++ else ++ ar2315_arch_init_irq(); ++} +--- /dev/null ++++ b/arch/mips/ath25/prom.c +@@ -0,0 +1,26 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright MontaVista Software Inc ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Prom setup file for AR5312/AR231x SoCs ++ */ ++ ++#include ++#include ++ ++void __init prom_init(void) ++{ ++} ++ ++void __init prom_free_prom_memory(void) ++{ ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h +@@ -0,0 +1,73 @@ ++#ifndef __ASM_MACH_ATH25_PLATFORM_H ++#define __ASM_MACH_ATH25_PLATFORM_H ++ ++#include ++ ++/* ++ * This is board-specific data that is stored in a "fixed" location in flash. ++ * It is shared across operating systems, so it should not be changed lightly. ++ * The main reason we need it is in order to extract the ethernet MAC ++ * address(es). ++ */ ++struct ath25_boarddata { ++ u32 magic; /* board data is valid */ ++#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */ ++ u16 cksum; /* checksum (starting with BD_REV 2) */ ++ u16 rev; /* revision of this struct */ ++#define BD_REV 4 ++ char board_name[64]; /* Name of board */ ++ u16 major; /* Board major number */ ++ u16 minor; /* Board minor number */ ++ u32 flags; /* Board configuration */ ++#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ ++#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ ++#define BD_UART1 0x00000004 /* UART1 is stuffed */ ++#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ ++#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ ++#define BD_SYSLED 0x00000020 /* System LED stuffed */ ++#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ ++#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ ++#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ ++#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ ++#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */ ++#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ ++#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ ++#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ ++#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ ++#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ ++ u16 reset_config_gpio; /* Reset factory GPIO pin */ ++ u16 sys_led_gpio; /* System LED GPIO pin */ ++ ++ u32 cpu_freq; /* CPU core frequency in Hz */ ++ u32 sys_freq; /* System frequency in Hz */ ++ u32 cnt_freq; /* Calculated C0_COUNT frequency */ ++ ++ u8 wlan0_mac[ETH_ALEN]; ++ u8 enet0_mac[ETH_ALEN]; ++ u8 enet1_mac[ETH_ALEN]; ++ ++ u16 pci_id; /* Pseudo PCIID for common code */ ++ u16 mem_cap; /* cap bank1 in MB */ ++ ++ /* version 3 */ ++ u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */ ++}; ++ ++#define BOARD_CONFIG_BUFSZ 0x1000 ++ ++/* ++ * Platform device information for the Wireless MAC ++ */ ++struct ar231x_board_config { ++ u16 devid; ++ ++ /* board config data */ ++ struct ath25_boarddata *config; ++ ++ /* radio calibration data */ ++ const char *radio; ++}; ++ ++#endif /* __ASM_MACH_ATH25_PLATFORM_H */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h +@@ -0,0 +1,64 @@ ++/* ++ * Atheros AR231x/AR531x SoC specific CPU feature overrides ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H ++ ++/* ++ * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core. ++ */ ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++#define cpu_has_ejtag 1 ++ ++#if !defined(CONFIG_SOC_AR5312) ++# define cpu_has_llsc 1 ++#else ++/* ++ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the ++ * ll/sc instructions. ++ */ ++# define cpu_has_llsc 0 ++#endif ++ ++#define cpu_has_mips16 0 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 ++ ++#define cpu_has_mips32r1 1 ++ ++#if !defined(CONFIG_SOC_AR5312) ++# define cpu_has_mips32r2 1 ++#endif ++ ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++ ++#define cpu_has_dsp 0 ++#define cpu_has_mipsmt 0 ++ ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 ++ ++#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h +@@ -0,0 +1,82 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2006 Ralf Baechle ++ * Copyright (C) 2007 Felix Fietkau ++ * ++ */ ++#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H ++#define __ASM_MACH_ATH25_DMA_COHERENCE_H ++ ++#include ++ ++/* ++ * We need some arbitrary non-zero value to be programmed to the BAR1 register ++ * of PCI host controller to enable DMA. The same value should be used as the ++ * offset to calculate the physical address of DMA buffer for PCI devices. ++ */ ++#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000 ++ ++static inline dma_addr_t ath25_dev_offset(struct device *dev) ++{ ++#ifdef CONFIG_PCI ++ extern struct bus_type pci_bus_type; ++ ++ if (dev && dev->bus == &pci_bus_type) ++ return AR2315_PCI_HOST_SDRAM_BASEADDR; ++#endif ++ return 0; ++} ++ ++static inline dma_addr_t ++plat_map_dma_mem(struct device *dev, void *addr, size_t size) ++{ ++ return virt_to_phys(addr) + ath25_dev_offset(dev); ++} ++ ++static inline dma_addr_t ++plat_map_dma_mem_page(struct device *dev, struct page *page) ++{ ++ return page_to_phys(page) + ath25_dev_offset(dev); ++} ++ ++static inline unsigned long ++plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) ++{ ++ return dma_addr - ath25_dev_offset(dev); ++} ++ ++static inline void ++plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size, ++ enum dma_data_direction direction) ++{ ++} ++ ++static inline int plat_dma_supported(struct device *dev, u64 mask) ++{ ++ return 1; ++} ++ ++static inline void plat_extra_sync_for_device(struct device *dev) ++{ ++} ++ ++static inline int plat_dma_mapping_error(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return 0; ++} ++ ++static inline int plat_device_is_coherent(struct device *dev) ++{ ++#ifdef CONFIG_DMA_COHERENT ++ return 1; ++#endif ++#ifdef CONFIG_DMA_NONCOHERENT ++ return 0; ++#endif ++} ++ ++#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath25/gpio.h +@@ -0,0 +1,16 @@ ++#ifndef __ASM_MACH_ATH25_GPIO_H ++#define __ASM_MACH_ATH25_GPIO_H ++ ++#include ++ ++#define gpio_get_value __gpio_get_value ++#define gpio_set_value __gpio_set_value ++#define gpio_cansleep __gpio_cansleep ++#define gpio_to_irq __gpio_to_irq ++ ++static inline int irq_to_gpio(unsigned irq) ++{ ++ return -EINVAL; ++} ++ ++#endif /* __ASM_MACH_ATH25_GPIO_H */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-ath25/war.h +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Felix Fietkau ++ */ ++#ifndef __ASM_MACH_ATH25_WAR_H ++#define __ASM_MACH_ATH25_WAR_H ++ ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 ++ ++#endif /* __ASM_MACH_ATH25_WAR_H */ +--- /dev/null ++++ b/arch/mips/ath25/ar2315_regs.h +@@ -0,0 +1,410 @@ ++/* ++ * Register definitions for AR2315+ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2008 Felix Fietkau ++ */ ++ ++#ifndef __ASM_MACH_ATH25_AR2315_REGS_H ++#define __ASM_MACH_ATH25_AR2315_REGS_H ++ ++/* ++ * IRQs ++ */ ++#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ ++#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ ++#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ ++#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ ++#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */ ++ ++/* ++ * Miscellaneous interrupts, which share IP2. ++ */ ++#define AR2315_MISC_IRQ_UART0 0 ++#define AR2315_MISC_IRQ_I2C_RSVD 1 ++#define AR2315_MISC_IRQ_SPI 2 ++#define AR2315_MISC_IRQ_AHB 3 ++#define AR2315_MISC_IRQ_APB 4 ++#define AR2315_MISC_IRQ_TIMER 5 ++#define AR2315_MISC_IRQ_GPIO 6 ++#define AR2315_MISC_IRQ_WATCHDOG 7 ++#define AR2315_MISC_IRQ_IR_RSVD 8 ++#define AR2315_MISC_IRQ_COUNT 9 ++ ++/* ++ * Address map ++ */ ++#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */ ++#define AR2315_SPI_READ_SIZE 0x01000000 ++#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */ ++#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */ ++#define AR2315_PCI_SIZE 0x00001000 ++#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */ ++#define AR2315_SDRAMCTL_SIZE 0x00000020 ++#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */ ++#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */ ++#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */ ++#define AR2315_RST_SIZE 0x00000100 ++#define AR2315_UART0_BASE 0x11100000 /* UART MMR */ ++#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */ ++#define AR2315_SPI_MMR_SIZE 0x00000010 ++#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */ ++#define AR2315_PCI_EXT_SIZE 0x40000000 ++ ++/* ++ * Configuration registers ++ */ ++ ++/* Cold reset register */ ++#define AR2315_COLD_RESET 0x0000 ++ ++#define AR2315_RESET_COLD_AHB 0x00000001 ++#define AR2315_RESET_COLD_APB 0x00000002 ++#define AR2315_RESET_COLD_CPU 0x00000004 ++#define AR2315_RESET_COLD_CPUWARM 0x00000008 ++#define AR2315_RESET_SYSTEM (RESET_COLD_CPU |\ ++ RESET_COLD_APB |\ ++ RESET_COLD_AHB) /* full system */ ++#define AR2317_RESET_SYSTEM 0x00000010 ++ ++/* Reset register */ ++#define AR2315_RESET 0x0004 ++ ++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ ++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */ ++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ ++#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ ++#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */ ++#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ ++#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ ++#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */ ++#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ ++#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */ ++#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ ++#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */ ++ ++/* AHB master arbitration control */ ++#define AR2315_AHB_ARB_CTL 0x0008 ++ ++#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ ++#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ ++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ ++#define AR2315_ARB_LOCAL 0x00000008 /* Local bus */ ++#define AR2315_ARB_PCI 0x00000010 /* PCI bus */ ++#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ ++#define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */ ++ ++/* Config Register */ ++#define AR2315_ENDIAN_CTL 0x000c ++ ++#define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */ ++#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ ++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ ++#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ ++#define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */ ++#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ ++#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ ++#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ ++#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ ++#define AR2315_CONFIG_BIG 0x00000400 ++#define AR2315_CONFIG_PCIAHB 0x00000800 ++#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 ++#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ ++#define AR2315_CONFIG_CPU_DRAM 0x00010000 ++#define AR2315_CONFIG_CPU_PCI 0x00020000 ++#define AR2315_CONFIG_CPU_MMR 0x00040000 ++ ++/* NMI control */ ++#define AR2315_NMI_CTL 0x0010 ++ ++#define AR2315_NMI_EN 1 ++ ++/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */ ++#define AR2315_SREV 0x0014 ++ ++#define AR2315_REV_MAJ 0x000000f0 ++#define AR2315_REV_MAJ_S 4 ++#define AR2315_REV_MIN 0x0000000f ++#define AR2315_REV_MIN_S 0 ++#define AR2315_REV_CHIP (AR2315_REV_MAJ | AR2315_REV_MIN) ++ ++/* Interface Enable */ ++#define AR2315_IF_CTL 0x0018 ++ ++#define AR2315_IF_MASK 0x00000007 ++#define AR2315_IF_DISABLED 0 /* Disable all */ ++#define AR2315_IF_PCI 1 /* PCI */ ++#define AR2315_IF_TS_LOCAL 2 /* Local bus */ ++#define AR2315_IF_ALL 3 /* Emulation only */ ++#define AR2315_IF_LOCAL_HOST 0x00000008 ++#define AR2315_IF_PCI_HOST 0x00000010 ++#define AR2315_IF_PCI_INTR 0x00000020 ++#define AR2315_IF_PCI_CLK_MASK 0x00030000 ++#define AR2315_IF_PCI_CLK_INPUT 0 ++#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 ++#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 ++#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 ++#define AR2315_IF_PCI_CLK_SHIFT 16 ++ ++/* APB Interrupt control */ ++#define AR2315_ISR 0x0020 ++#define AR2315_IMR 0x0024 ++#define AR2315_GISR 0x0028 ++ ++#define AR2315_ISR_UART0 0x00000001 /* high speed UART */ ++#define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */ ++#define AR2315_ISR_SPI 0x00000004 /* SPI bus */ ++#define AR2315_ISR_AHB 0x00000008 /* AHB error */ ++#define AR2315_ISR_APB 0x00000010 /* APB error */ ++#define AR2315_ISR_TIMER 0x00000020 /* Timer */ ++#define AR2315_ISR_GPIO 0x00000040 /* GPIO */ ++#define AR2315_ISR_WD 0x00000080 /* Watchdog */ ++#define AR2315_ISR_IR_RSVD 0x00000100 /* IR */ ++ ++#define AR2315_GISR_MISC 0x00000001 /* Misc */ ++#define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */ ++#define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ ++#define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */ ++#define AR2315_GISR_WMACPOLL 0x00000010 ++#define AR2315_GISR_TIMER 0x00000020 ++#define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */ ++ ++/* Generic timer */ ++#define AR2315_TIMER 0x0030 ++#define AR2315_RELOAD 0x0034 ++ ++/* Watchdog timer */ ++#define AR2315_WDT_TIMER 0x0038 ++#define AR2315_WDT_CTRL 0x003c ++ ++#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */ ++#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */ ++#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */ ++ ++/* CPU Performance Counters */ ++#define AR2315_PERFCNT0 0x0048 ++#define AR2315_PERFCNT1 0x004c ++ ++#define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */ ++#define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */ ++#define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */ ++#define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */ ++#define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */ ++#define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */ ++#define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */ ++ ++#define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */ ++#define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */ ++#define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */ ++#define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */ ++#define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/ ++#define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/ ++#define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */ ++ ++/* AHB Error Reporting */ ++#define AR2315_AHB_ERR0 0x0050 /* error */ ++#define AR2315_AHB_ERR1 0x0054 /* haddr */ ++#define AR2315_AHB_ERR2 0x0058 /* hwdata */ ++#define AR2315_AHB_ERR3 0x005c /* hrdata */ ++#define AR2315_AHB_ERR4 0x0060 /* status */ ++ ++#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */ ++ /* write 1 to clear all bits in ERR0 */ ++#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ ++#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ ++ ++#define AR2315_PROCERR_HMAST 0x0000000f ++#define AR2315_PROCERR_HMAST_DFLT 0 ++#define AR2315_PROCERR_HMAST_WMAC 1 ++#define AR2315_PROCERR_HMAST_ENET 2 ++#define AR2315_PROCERR_HMAST_PCIENDPT 3 ++#define AR2315_PROCERR_HMAST_LOCAL 4 ++#define AR2315_PROCERR_HMAST_CPU 5 ++#define AR2315_PROCERR_HMAST_PCITGT 6 ++#define AR2315_PROCERR_HMAST_S 0 ++#define AR2315_PROCERR_HWRITE 0x00000010 ++#define AR2315_PROCERR_HSIZE 0x00000060 ++#define AR2315_PROCERR_HSIZE_S 5 ++#define AR2315_PROCERR_HTRANS 0x00000180 ++#define AR2315_PROCERR_HTRANS_S 7 ++#define AR2315_PROCERR_HBURST 0x00000e00 ++#define AR2315_PROCERR_HBURST_S 9 ++ ++/* Clock Control */ ++#define AR2315_PLLC_CTL 0x0064 ++#define AR2315_PLLV_CTL 0x0068 ++#define AR2315_CPUCLK 0x006c ++#define AR2315_AMBACLK 0x0070 ++#define AR2315_SYNCCLK 0x0074 ++#define AR2315_DSL_SLEEP_CTL 0x0080 ++#define AR2315_DSL_SLEEP_DUR 0x0084 ++ ++/* PLLc Control fields */ ++#define AR2315_PLLC_REF_DIV_M 0x00000003 ++#define AR2315_PLLC_REF_DIV_S 0 ++#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c ++#define AR2315_PLLC_FDBACK_DIV_S 2 ++#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080 ++#define AR2315_PLLC_ADD_FDBACK_DIV_S 7 ++#define AR2315_PLLC_CLKC_DIV_M 0x0001c000 ++#define AR2315_PLLC_CLKC_DIV_S 14 ++#define AR2315_PLLC_CLKM_DIV_M 0x00700000 ++#define AR2315_PLLC_CLKM_DIV_S 20 ++ ++/* CPU CLK Control fields */ ++#define AR2315_CPUCLK_CLK_SEL_M 0x00000003 ++#define AR2315_CPUCLK_CLK_SEL_S 0 ++#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c ++#define AR2315_CPUCLK_CLK_DIV_S 2 ++ ++/* AMBA CLK Control fields */ ++#define AR2315_AMBACLK_CLK_SEL_M 0x00000003 ++#define AR2315_AMBACLK_CLK_SEL_S 0 ++#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c ++#define AR2315_AMBACLK_CLK_DIV_S 2 ++ ++/* PCI Clock Control */ ++#define AR2315_PCICLK 0x00a4 ++ ++#define AR2315_PCICLK_INPUT_M 0x00000003 ++#define AR2315_PCICLK_INPUT_S 0 ++#define AR2315_PCICLK_PLLC_CLKM 0 ++#define AR2315_PCICLK_PLLC_CLKM1 1 ++#define AR2315_PCICLK_PLLC_CLKC 2 ++#define AR2315_PCICLK_REF_CLK 3 ++#define AR2315_PCICLK_DIV_M 0x0000000c ++#define AR2315_PCICLK_DIV_S 2 ++#define AR2315_PCICLK_IN_FREQ 0 ++#define AR2315_PCICLK_IN_FREQ_DIV_6 1 ++#define AR2315_PCICLK_IN_FREQ_DIV_8 2 ++#define AR2315_PCICLK_IN_FREQ_DIV_10 3 ++ ++/* Observation Control Register */ ++#define AR2315_OCR 0x00b0 ++ ++#define AR2315_OCR_GPIO0_IRIN 0x00000040 ++#define AR2315_OCR_GPIO1_IROUT 0x00000080 ++#define AR2315_OCR_GPIO3_RXCLR 0x00000200 ++ ++/* General Clock Control */ ++#define AR2315_MISCCLK 0x00b4 ++ ++#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001 ++#define AR2315_MISCCLK_PROCREFCLK 0x00000002 ++ ++/* ++ * SDRAM Controller ++ * - No read or write buffers are included. ++ */ ++#define AR2315_MEM_CFG 0x0000 ++#define AR2315_MEM_CTRL 0x000c ++#define AR2315_MEM_REF 0x0010 ++ ++#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000 ++#define AR2315_MEM_CFG_DATA_WIDTH_S 13 ++#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00 ++#define AR2315_MEM_CFG_COL_WIDTH_S 9 ++#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0 ++#define AR2315_MEM_CFG_ROW_WIDTH_S 5 ++#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018 ++#define AR2315_MEM_CFG_BANKADDR_BITS_S 3 ++ ++/* ++ * Local Bus Interface Registers ++ */ ++#define AR2315_LB_CONFIG 0x0000 ++ ++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ ++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ ++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ ++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ ++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ ++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ ++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ ++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ ++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ ++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ ++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ ++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ ++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ ++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ ++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ ++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ ++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ ++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ ++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ ++#define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */ ++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ ++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ ++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ ++ ++#define AR2315_LB_CLKSEL 0x0004 ++ ++#define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */ ++ ++#define AR2315_LB_1MS 0x0008 ++ ++#define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_LB_MISCCFG 0x000c ++ ++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ ++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ ++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ ++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ ++#define AR2315_LBM_TIMEOUT_M 0x00ffff80 ++#define AR2315_LBM_TIMEOUT_S 7 ++#define AR2315_LBM_PORTMUX 0x07000000 ++ ++#define AR2315_LB_RXTSOFF 0x0010 ++ ++#define AR2315_LB_TX_CHAIN_EN 0x0100 ++ ++#define AR2315_LB_TXEN_0 0x00000001 ++#define AR2315_LB_TXEN_1 0x00000002 ++#define AR2315_LB_TXEN_2 0x00000004 ++#define AR2315_LB_TXEN_3 0x00000008 ++ ++#define AR2315_LB_TX_CHAIN_DIS 0x0104 ++#define AR2315_LB_TX_DESC_PTR 0x0200 ++ ++#define AR2315_LB_RX_CHAIN_EN 0x0400 ++ ++#define AR2315_LB_RXEN 0x00000001 ++ ++#define AR2315_LB_RX_CHAIN_DIS 0x0404 ++#define AR2315_LB_RX_DESC_PTR 0x0408 ++ ++#define AR2315_LB_INT_STATUS 0x0500 ++ ++#define AR2315_LB_INT_TX_DESC 0x00000001 ++#define AR2315_LB_INT_TX_OK 0x00000002 ++#define AR2315_LB_INT_TX_ERR 0x00000004 ++#define AR2315_LB_INT_TX_EOF 0x00000008 ++#define AR2315_LB_INT_RX_DESC 0x00000010 ++#define AR2315_LB_INT_RX_OK 0x00000020 ++#define AR2315_LB_INT_RX_ERR 0x00000040 ++#define AR2315_LB_INT_RX_EOF 0x00000080 ++#define AR2315_LB_INT_TX_TRUNC 0x00000100 ++#define AR2315_LB_INT_TX_STARVE 0x00000200 ++#define AR2315_LB_INT_LB_TIMEOUT 0x00000400 ++#define AR2315_LB_INT_LB_ERR 0x00000800 ++#define AR2315_LB_INT_MBOX_WR 0x00001000 ++#define AR2315_LB_INT_MBOX_RD 0x00002000 ++ ++/* Bit definitions for INT MASK are the same as INT_STATUS */ ++#define AR2315_LB_INT_MASK 0x0504 ++ ++#define AR2315_LB_INT_EN 0x0508 ++#define AR2315_LB_MBOX 0x0600 ++ ++#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */ +--- /dev/null ++++ b/arch/mips/ath25/ar5312_regs.h +@@ -0,0 +1,224 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++#ifndef __ASM_MACH_ATH25_AR5312_REGS_H ++#define __ASM_MACH_ATH25_AR5312_REGS_H ++ ++/* ++ * IRQs ++ */ ++#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ ++#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ ++#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ ++#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ ++#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */ ++ ++/* ++ * Miscellaneous interrupts, which share IP6. ++ */ ++#define AR5312_MISC_IRQ_TIMER 0 ++#define AR5312_MISC_IRQ_AHB_PROC 1 ++#define AR5312_MISC_IRQ_AHB_DMA 2 ++#define AR5312_MISC_IRQ_GPIO 3 ++#define AR5312_MISC_IRQ_UART0 4 ++#define AR5312_MISC_IRQ_UART0_DMA 5 ++#define AR5312_MISC_IRQ_WATCHDOG 6 ++#define AR5312_MISC_IRQ_LOCAL 7 ++#define AR5312_MISC_IRQ_SPI 8 ++#define AR5312_MISC_IRQ_COUNT 9 ++ ++/* ++ * Address Map ++ * ++ * The AR5312 supports 2 enet MACS, even though many reference boards only ++ * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet ++ * PHY or PHY switch. The AR2312 supports 1 enet MAC. ++ */ ++#define AR5312_WLAN0_BASE 0x18000000 ++#define AR5312_ENET0_BASE 0x18100000 ++#define AR5312_ENET1_BASE 0x18200000 ++#define AR5312_SDRAMCTL_BASE 0x18300000 ++#define AR5312_SDRAMCTL_SIZE 0x00000010 ++#define AR5312_FLASHCTL_BASE 0x18400000 ++#define AR5312_FLASHCTL_SIZE 0x00000010 ++#define AR5312_WLAN1_BASE 0x18500000 ++#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */ ++#define AR5312_GPIO_BASE 0x1c002000 ++#define AR5312_GPIO_SIZE 0x00000010 ++#define AR5312_RST_BASE 0x1c003000 ++#define AR5312_RST_SIZE 0x00000100 ++#define AR5312_FLASH_BASE 0x1e000000 ++#define AR5312_FLASH_SIZE 0x00800000 ++ ++/* ++ * Need these defines to determine true number of ethernet MACs ++ */ ++#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ ++#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ ++#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ ++ ++/* Reset/Timer Block Address Map */ ++#define AR5312_TIMER 0x0000 /* countdown timer */ ++#define AR5312_RELOAD 0x0004 /* timer reload value */ ++#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */ ++#define AR5312_WDT_TIMER 0x000c /* watchdog timer */ ++#define AR5312_ISR 0x0010 /* Intr Status Reg */ ++#define AR5312_IMR 0x0014 /* Intr Mask Reg */ ++#define AR5312_RESET 0x0020 ++#define AR5312_CLOCKCTL1 0x0064 ++#define AR5312_SCRATCH 0x006c ++#define AR5312_PROCADDR 0x0070 ++#define AR5312_PROC1 0x0074 ++#define AR5312_DMAADDR 0x0078 ++#define AR5312_DMA1 0x007c ++#define AR5312_ENABLE 0x0080 /* interface enb */ ++#define AR5312_REV 0x0090 /* revision */ ++ ++/* AR5312_WDT_CTRL register bit field definitions */ ++#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */ ++#define AR5312_WDT_CTRL_NMI 0x00000001 ++#define AR5312_WDT_CTRL_RESET 0x00000002 ++ ++/* AR5312_ISR register bit field definitions */ ++#define AR5312_ISR_TIMER 0x00000001 ++#define AR5312_ISR_AHBPROC 0x00000002 ++#define AR5312_ISR_AHBDMA 0x00000004 ++#define AR5312_ISR_GPIO 0x00000008 ++#define AR5312_ISR_UART0 0x00000010 ++#define AR5312_ISR_UART0DMA 0x00000020 ++#define AR5312_ISR_WD 0x00000040 ++#define AR5312_ISR_LOCAL 0x00000080 ++ ++/* AR5312_RESET register bit field definitions */ ++#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */ ++#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */ ++#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */ ++#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ ++#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ ++#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */ ++#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */ ++#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */ ++#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ ++#define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */ ++#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ ++#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ ++#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */ ++#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the CPU */ ++#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */ ++#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */ ++#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ ++#define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */ ++ ++#define AR5312_RESET_WMAC0_BITS (AR5312_RESET_WLAN0 |\ ++ AR5312_RESET_WARM_WLAN0_MAC |\ ++ AR5312_RESET_WARM_WLAN0_BB) ++ ++#define AR5312_RESET_WMAC1_BITS (AR5312_RESET_WLAN1 |\ ++ AR5312_RESET_WARM_WLAN1_MAC |\ ++ AR5312_RESET_WARM_WLAN1_BB) ++ ++/* AR5312_CLOCKCTL1 register bit field definitions */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR5312 and AR2312 */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR2313 */ ++#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 ++#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 ++#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 ++#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 ++#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 ++ ++/* AR5312_ENABLE register bit field definitions */ ++#define AR5312_ENABLE_WLAN0 0x00000001 ++#define AR5312_ENABLE_ENET0 0x00000002 ++#define AR5312_ENABLE_ENET1 0x00000004 ++#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x00000008/* UART & WLAN1 PIO */ ++#define AR5312_ENABLE_WLAN1_DMA 0x00000010/* WLAN1 DMAs */ ++#define AR5312_ENABLE_WLAN1 (AR5312_ENABLE_UART_AND_WLAN1_PIO |\ ++ AR5312_ENABLE_WLAN1_DMA) ++ ++/* AR5312_REV register bit field definitions */ ++#define AR5312_REV_WMAC_MAJ 0x0000f000 ++#define AR5312_REV_WMAC_MAJ_S 12 ++#define AR5312_REV_WMAC_MIN 0x00000f00 ++#define AR5312_REV_WMAC_MIN_S 8 ++#define AR5312_REV_MAJ 0x000000f0 ++#define AR5312_REV_MAJ_S 4 ++#define AR5312_REV_MIN 0x0000000f ++#define AR5312_REV_MIN_S 0 ++#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN) ++ ++/* Major revision numbers, bits 7..4 of Revision ID register */ ++#define AR5312_REV_MAJ_AR5312 0x4 ++#define AR5312_REV_MAJ_AR2313 0x5 ++ ++/* Minor revision numbers, bits 3..0 of Revision ID register */ ++#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ ++#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ ++ ++/* ++ * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices ++ */ ++#define AR5312_FLASHCTL0 0x0000 ++#define AR5312_FLASHCTL1 0x0004 ++#define AR5312_FLASHCTL2 0x0008 ++ ++/* AR5312_FLASHCTL register bit field definitions */ ++#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */ ++#define AR5312_FLASHCTL_IDCY_S 0 ++#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ ++#define AR5312_FLASHCTL_WST1_S 5 ++#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ ++#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ ++#define AR5312_FLASHCTL_WST2_S 11 ++#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */ ++#define AR5312_FLASHCTL_AC_S 16 ++#define AR5312_FLASHCTL_AC_128K 0x00000000 ++#define AR5312_FLASHCTL_AC_256K 0x00010000 ++#define AR5312_FLASHCTL_AC_512K 0x00020000 ++#define AR5312_FLASHCTL_AC_1M 0x00030000 ++#define AR5312_FLASHCTL_AC_2M 0x00040000 ++#define AR5312_FLASHCTL_AC_4M 0x00050000 ++#define AR5312_FLASHCTL_AC_8M 0x00060000 ++#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ ++#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ ++#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */ ++#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */ ++#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */ ++#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */ ++#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */ ++#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */ ++#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */ ++#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */ ++#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */ ++#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */ ++#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */ ++ ++/* ++ * ARM SDRAM Controller -- just enough to determine memory size ++ */ ++#define AR5312_MEM_CFG1 0x0004 ++ ++#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */ ++#define AR5312_MEM_CFG1_AC0_S 8 ++#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */ ++#define AR5312_MEM_CFG1_AC1_S 12 ++ ++#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */ +--- /dev/null ++++ b/arch/mips/ath25/ar5312.c +@@ -0,0 +1,393 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * Copyright (C) 2012 Alexandros C. Couloumbis ++ */ ++ ++/* ++ * Platform devices for Atheros AR5312 SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "devices.h" ++#include "ar5312.h" ++#include "ar5312_regs.h" ++ ++static void __iomem *ar5312_rst_base; ++static struct irq_domain *ar5312_misc_irq_domain; ++ ++static inline u32 ar5312_rst_reg_read(u32 reg) ++{ ++ return __raw_readl(ar5312_rst_base + reg); ++} ++ ++static inline void ar5312_rst_reg_write(u32 reg, u32 val) ++{ ++ __raw_writel(val, ar5312_rst_base + reg); ++} ++ ++static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val) ++{ ++ u32 ret = ar5312_rst_reg_read(reg); ++ ++ ret &= ~mask; ++ ret |= val; ++ ar5312_rst_reg_write(reg, ret); ++} ++ ++static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id) ++{ ++ u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1); ++ u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */ ++ u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1); ++ u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */ ++ ++ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", ++ proc_addr, proc1, dma_addr, dma1); ++ ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction ar5312_ahb_err_interrupt = { ++ .handler = ar5312_ahb_err_handler, ++ .name = "ar5312-ahb-error", ++}; ++ ++static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc) ++{ ++ u32 pending = ar5312_rst_reg_read(AR5312_ISR) & ++ ar5312_rst_reg_read(AR5312_IMR); ++ unsigned nr, misc_irq = 0; ++ ++ if (pending) { ++ struct irq_domain *domain = irq_get_handler_data(irq); ++ ++ nr = __ffs(pending); ++ misc_irq = irq_find_mapping(domain, nr); ++ } ++ ++ if (misc_irq) { ++ generic_handle_irq(misc_irq); ++ if (nr == AR5312_MISC_IRQ_TIMER) ++ ar5312_rst_reg_read(AR5312_TIMER); ++ } else { ++ spurious_interrupt(); ++ } ++} ++ ++/* Enable the specified AR5312_MISC_IRQ interrupt */ ++static void ar5312_misc_irq_unmask(struct irq_data *d) ++{ ++ ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); ++} ++ ++/* Disable the specified AR5312_MISC_IRQ interrupt */ ++static void ar5312_misc_irq_mask(struct irq_data *d) ++{ ++ ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); ++ ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */ ++} ++ ++static struct irq_chip ar5312_misc_irq_chip = { ++ .name = "ar5312-misc", ++ .irq_unmask = ar5312_misc_irq_unmask, ++ .irq_mask = ar5312_misc_irq_mask, ++}; ++ ++static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq, ++ irq_hw_number_t hw) ++{ ++ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq); ++ return 0; ++} ++ ++static struct irq_domain_ops ar5312_misc_irq_domain_ops = { ++ .map = ar5312_misc_irq_map, ++}; ++ ++static void ar5312_irq_dispatch(void) ++{ ++ u32 pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP2) ++ do_IRQ(AR5312_IRQ_WLAN0); ++ else if (pending & CAUSEF_IP5) ++ do_IRQ(AR5312_IRQ_WLAN1); ++ else if (pending & CAUSEF_IP6) ++ do_IRQ(AR5312_IRQ_MISC); ++ else if (pending & CAUSEF_IP7) ++ do_IRQ(ATH25_IRQ_CPU_CLOCK); ++ else ++ spurious_interrupt(); ++} ++ ++void __init ar5312_arch_init_irq(void) ++{ ++ struct irq_domain *domain; ++ unsigned irq; ++ ++ ath25_irq_dispatch = ar5312_irq_dispatch; ++ ++ domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT, ++ &ar5312_misc_irq_domain_ops, NULL); ++ if (!domain) ++ panic("Failed to add IRQ domain"); ++ ++ irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC); ++ setup_irq(irq, &ar5312_ahb_err_interrupt); ++ ++ irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler); ++ irq_set_handler_data(AR5312_IRQ_MISC, domain); ++ ++ ar5312_misc_irq_domain = domain; ++} ++ ++static struct physmap_flash_data ar5312_flash_data = { ++ .width = 2, ++}; ++ ++static struct resource ar5312_flash_resource = { ++ .start = AR5312_FLASH_BASE, ++ .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device ar5312_physmap_flash = { ++ .name = "physmap-flash", ++ .id = 0, ++ .dev.platform_data = &ar5312_flash_data, ++ .resource = &ar5312_flash_resource, ++ .num_resources = 1, ++}; ++ ++static void __init ar5312_flash_init(void) ++{ ++ void __iomem *flashctl_base; ++ u32 ctl; ++ ++ flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE, ++ AR5312_FLASHCTL_SIZE); ++ ++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0); ++ ctl &= AR5312_FLASHCTL_MW; ++ ++ /* fixup flash width */ ++ switch (ctl) { ++ case AR5312_FLASHCTL_MW16: ++ ar5312_flash_data.width = 2; ++ break; ++ case AR5312_FLASHCTL_MW8: ++ default: ++ ar5312_flash_data.width = 1; ++ break; ++ } ++ ++ /* ++ * Configure flash bank 0. ++ * Assume 8M window size. Flash will be aliased if it's smaller ++ */ ++ ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE; ++ ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S; ++ ctl |= 0x07 << AR5312_FLASHCTL_WST1_S; ++ ctl |= 0x07 << AR5312_FLASHCTL_WST2_S; ++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0); ++ ++ /* Disable other flash banks */ ++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1); ++ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC); ++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1); ++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2); ++ ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC); ++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2); ++ ++ iounmap(flashctl_base); ++} ++ ++void __init ar5312_init_devices(void) ++{ ++ struct ath25_boarddata *config; ++ ++ ar5312_flash_init(); ++ ++ /* Locate board/radio config data */ ++ ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE); ++ config = ath25_board.config; ++ ++ /* AR2313 has CPU minor rev. 10 */ ++ if ((current_cpu_data.processor_id & 0xff) == 0x0a) ++ ath25_soc = ATH25_SOC_AR2313; ++ ++ /* AR2312 shares the same Silicon ID as AR5312 */ ++ else if (config->flags & BD_ISCASPER) ++ ath25_soc = ATH25_SOC_AR2312; ++ ++ /* Everything else is probably AR5312 or compatible */ ++ else ++ ath25_soc = ATH25_SOC_AR5312; ++ ++ platform_device_register(&ar5312_physmap_flash); ++ ++ switch (ath25_soc) { ++ case ATH25_SOC_AR5312: ++ if (!ath25_board.radio) ++ return; ++ ++ if (!(config->flags & BD_WLAN0)) ++ break; ++ ++ ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0); ++ break; ++ case ATH25_SOC_AR2312: ++ case ATH25_SOC_AR2313: ++ if (!ath25_board.radio) ++ return; ++ break; ++ default: ++ break; ++ } ++ ++ if (config->flags & BD_WLAN1) ++ ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1); ++} ++ ++static void ar5312_restart(char *command) ++{ ++ /* reset the system */ ++ local_irq_disable(); ++ while (1) ++ ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM); ++} ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 }; ++ ++static unsigned __init ar5312_cpu_frequency(void) ++{ ++ u32 scratch, devid, clock_ctl1; ++ u32 predivide_mask, multiplier_mask, doubler_mask; ++ unsigned predivide_shift, multiplier_shift; ++ unsigned predivide_select, predivisor, multiplier; ++ ++ /* Trust the bootrom's idea of cpu frequency. */ ++ scratch = ar5312_rst_reg_read(AR5312_SCRATCH); ++ if (scratch) ++ return scratch; ++ ++ devid = ar5312_rst_reg_read(AR5312_REV); ++ devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S; ++ if (devid == AR5312_REV_MAJ_AR2313) { ++ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; ++ } else { /* AR5312 and AR2312 */ ++ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; ++ } ++ ++ /* ++ * Clocking is derived from a fixed 40MHz input clock. ++ * ++ * cpu_freq = input_clock * MULT (where MULT is PLL multiplier) ++ * sys_freq = cpu_freq / 4 (used for APB clock, serial, ++ * flash, Timer, Watchdog Timer) ++ * ++ * cnt_freq = cpu_freq / 2 (use for CPU count/compare) ++ * ++ * So, for example, with a PLL multiplier of 5, we have ++ * ++ * cpu_freq = 200MHz ++ * sys_freq = 50MHz ++ * cnt_freq = 100MHz ++ * ++ * We compute the CPU frequency, based on PLL settings. ++ */ ++ ++ clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1); ++ predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift; ++ predivisor = clockctl1_predivide_table[predivide_select]; ++ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift; ++ ++ if (clock_ctl1 & doubler_mask) ++ multiplier <<= 1; ++ ++ return (40000000 / predivisor) * multiplier; ++} ++ ++static inline unsigned ar5312_sys_frequency(void) ++{ ++ return ar5312_cpu_frequency() / 4; ++} ++ ++void __init ar5312_plat_time_init(void) ++{ ++ mips_hpt_frequency = ar5312_cpu_frequency() / 2; ++} ++ ++void __init ar5312_plat_mem_setup(void) ++{ ++ void __iomem *sdram_base; ++ u32 memsize, memcfg, bank0_ac, bank1_ac; ++ u32 devid; ++ ++ /* Detect memory size */ ++ sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE, ++ AR5312_SDRAMCTL_SIZE); ++ memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1); ++ bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0); ++ bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1); ++ memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) + ++ (bank1_ac ? (1 << (bank1_ac + 1)) : 0); ++ memsize <<= 20; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ iounmap(sdram_base); ++ ++ ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE); ++ ++ devid = ar5312_rst_reg_read(AR5312_REV); ++ devid >>= AR5312_REV_WMAC_MIN_S; ++ devid &= AR5312_REV_CHIP; ++ ath25_board.devid = (u16)devid; ++ ++ /* Clear any lingering AHB errors */ ++ ar5312_rst_reg_read(AR5312_PROCADDR); ++ ar5312_rst_reg_read(AR5312_DMAADDR); ++ ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE); ++ ++ _machine_restart = ar5312_restart; ++} ++ ++void __init ar5312_arch_init(void) ++{ ++ unsigned irq = irq_create_mapping(ar5312_misc_irq_domain, ++ AR5312_MISC_IRQ_UART0); ++ ++ ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency()); ++} +--- /dev/null ++++ b/arch/mips/ath25/ar2315.c +@@ -0,0 +1,308 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ * Copyright (C) 2012 Alexandros C. Couloumbis ++ */ ++ ++/* ++ * Platform devices for Atheros AR2315 SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "devices.h" ++#include "ar2315.h" ++#include "ar2315_regs.h" ++ ++static void __iomem *ar2315_rst_base; ++static struct irq_domain *ar2315_misc_irq_domain; ++ ++static inline u32 ar2315_rst_reg_read(u32 reg) ++{ ++ return __raw_readl(ar2315_rst_base + reg); ++} ++ ++static inline void ar2315_rst_reg_write(u32 reg, u32 val) ++{ ++ __raw_writel(val, ar2315_rst_base + reg); ++} ++ ++static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val) ++{ ++ u32 ret = ar2315_rst_reg_read(reg); ++ ++ ret &= ~mask; ++ ret |= val; ++ ar2315_rst_reg_write(reg, ret); ++} ++ ++static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id) ++{ ++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET); ++ ar2315_rst_reg_read(AR2315_AHB_ERR1); ++ ++ pr_emerg("AHB fatal error\n"); ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction ar2315_ahb_err_interrupt = { ++ .handler = ar2315_ahb_err_handler, ++ .name = "ar2315-ahb-error", ++}; ++ ++static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc) ++{ ++ u32 pending = ar2315_rst_reg_read(AR2315_ISR) & ++ ar2315_rst_reg_read(AR2315_IMR); ++ unsigned nr, misc_irq = 0; ++ ++ if (pending) { ++ struct irq_domain *domain = irq_get_handler_data(irq); ++ ++ nr = __ffs(pending); ++ misc_irq = irq_find_mapping(domain, nr); ++ } ++ ++ if (misc_irq) { ++ if (nr == AR2315_MISC_IRQ_GPIO) ++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO); ++ else if (nr == AR2315_MISC_IRQ_WATCHDOG) ++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD); ++ generic_handle_irq(misc_irq); ++ } else { ++ spurious_interrupt(); ++ } ++} ++ ++static void ar2315_misc_irq_unmask(struct irq_data *d) ++{ ++ ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq)); ++} ++ ++static void ar2315_misc_irq_mask(struct irq_data *d) ++{ ++ ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0); ++} ++ ++static struct irq_chip ar2315_misc_irq_chip = { ++ .name = "ar2315-misc", ++ .irq_unmask = ar2315_misc_irq_unmask, ++ .irq_mask = ar2315_misc_irq_mask, ++}; ++ ++static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq, ++ irq_hw_number_t hw) ++{ ++ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq); ++ return 0; ++} ++ ++static struct irq_domain_ops ar2315_misc_irq_domain_ops = { ++ .map = ar2315_misc_irq_map, ++}; ++ ++/* ++ * Called when an interrupt is received, this function ++ * determines exactly which interrupt it was, and it ++ * invokes the appropriate handler. ++ * ++ * Implicitly, we also define interrupt priority by ++ * choosing which to dispatch first. ++ */ ++static void ar2315_irq_dispatch(void) ++{ ++ u32 pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP3) ++ do_IRQ(AR2315_IRQ_WLAN0); ++ else if (pending & CAUSEF_IP2) ++ do_IRQ(AR2315_IRQ_MISC); ++ else if (pending & CAUSEF_IP7) ++ do_IRQ(ATH25_IRQ_CPU_CLOCK); ++ else ++ spurious_interrupt(); ++} ++ ++void __init ar2315_arch_init_irq(void) ++{ ++ struct irq_domain *domain; ++ unsigned irq; ++ ++ ath25_irq_dispatch = ar2315_irq_dispatch; ++ ++ domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT, ++ &ar2315_misc_irq_domain_ops, NULL); ++ if (!domain) ++ panic("Failed to add IRQ domain"); ++ ++ irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB); ++ setup_irq(irq, &ar2315_ahb_err_interrupt); ++ ++ irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler); ++ irq_set_handler_data(AR2315_IRQ_MISC, domain); ++ ++ ar2315_misc_irq_domain = domain; ++} ++ ++void __init ar2315_init_devices(void) ++{ ++ /* Find board configuration */ ++ ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE); ++ ++ ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0); ++} ++ ++static void ar2315_restart(char *command) ++{ ++ void (*mips_reset_vec)(void) = (void *)0xbfc00000; ++ ++ local_irq_disable(); ++ ++ /* try reset the system via reset control */ ++ ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM); ++ ++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits ++ * a workaround. Give it some time to attempt a gpio based hardware ++ * reset (atheros reference design workaround) */ ++ ++ /* TODO: implement the GPIO reset workaround */ ++ ++ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic ++ * workaround. Attempt to jump to the mips reset location - ++ * the boot loader itself might be able to recover the system */ ++ mips_reset_vec(); ++} ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 }; ++static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 }; ++ ++static unsigned __init ar2315_sys_clk(u32 clock_ctl) ++{ ++ unsigned int pllc_ctrl, cpu_div; ++ unsigned int pllc_out, refdiv, fdiv, divby2; ++ unsigned int clk_div; ++ ++ pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL); ++ refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV); ++ refdiv = clockctl1_predivide_table[refdiv]; ++ fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV); ++ divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1; ++ pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv; ++ ++ /* clkm input selected */ ++ switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) { ++ case 0: ++ case 1: ++ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV); ++ clk_div = pllc_divide_table[clk_div]; ++ break; ++ case 2: ++ clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV); ++ clk_div = pllc_divide_table[clk_div]; ++ break; ++ default: ++ pllc_out = 40000000; ++ clk_div = 1; ++ break; ++ } ++ ++ cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV); ++ cpu_div = cpu_div * 2 ?: 1; ++ ++ return pllc_out / (clk_div * cpu_div); ++} ++ ++static inline unsigned ar2315_cpu_frequency(void) ++{ ++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK)); ++} ++ ++static inline unsigned ar2315_apb_frequency(void) ++{ ++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK)); ++} ++ ++void __init ar2315_plat_time_init(void) ++{ ++ mips_hpt_frequency = ar2315_cpu_frequency() / 2; ++} ++ ++void __init ar2315_plat_mem_setup(void) ++{ ++ void __iomem *sdram_base; ++ u32 memsize, memcfg; ++ u32 devid; ++ u32 config; ++ ++ /* Detect memory size */ ++ sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE, ++ AR2315_SDRAMCTL_SIZE); ++ memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG); ++ memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH); ++ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH); ++ memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH); ++ memsize <<= 3; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ iounmap(sdram_base); ++ ++ ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE); ++ ++ /* Detect the hardware based on the device ID */ ++ devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP; ++ switch (devid) { ++ case 0x91: /* Need to check */ ++ ath25_soc = ATH25_SOC_AR2318; ++ break; ++ case 0x90: ++ ath25_soc = ATH25_SOC_AR2317; ++ break; ++ case 0x87: ++ ath25_soc = ATH25_SOC_AR2316; ++ break; ++ case 0x86: ++ default: ++ ath25_soc = ATH25_SOC_AR2315; ++ break; ++ } ++ ath25_board.devid = devid; ++ ++ /* Clear any lingering AHB errors */ ++ config = read_c0_config(); ++ write_c0_config(config & ~0x3); ++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET); ++ ar2315_rst_reg_read(AR2315_AHB_ERR1); ++ ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE); ++ ++ _machine_restart = ar2315_restart; ++} ++ ++void __init ar2315_arch_init(void) ++{ ++ unsigned irq = irq_create_mapping(ar2315_misc_irq_domain, ++ AR2315_MISC_IRQ_UART0); ++ ++ ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency()); ++} +--- /dev/null ++++ b/arch/mips/ath25/ar2315.h +@@ -0,0 +1,22 @@ ++#ifndef __AR2315_H ++#define __AR2315_H ++ ++#ifdef CONFIG_SOC_AR2315 ++ ++void ar2315_arch_init_irq(void); ++void ar2315_init_devices(void); ++void ar2315_plat_time_init(void); ++void ar2315_plat_mem_setup(void); ++void ar2315_arch_init(void); ++ ++#else ++ ++static inline void ar2315_arch_init_irq(void) {} ++static inline void ar2315_init_devices(void) {} ++static inline void ar2315_plat_time_init(void) {} ++static inline void ar2315_plat_mem_setup(void) {} ++static inline void ar2315_arch_init(void) {} ++ ++#endif ++ ++#endif /* __AR2315_H */ +--- /dev/null ++++ b/arch/mips/ath25/ar5312.h +@@ -0,0 +1,22 @@ ++#ifndef __AR5312_H ++#define __AR5312_H ++ ++#ifdef CONFIG_SOC_AR5312 ++ ++void ar5312_arch_init_irq(void); ++void ar5312_init_devices(void); ++void ar5312_plat_time_init(void); ++void ar5312_plat_mem_setup(void); ++void ar5312_arch_init(void); ++ ++#else ++ ++static inline void ar5312_arch_init_irq(void) {} ++static inline void ar5312_init_devices(void) {} ++static inline void ar5312_plat_time_init(void) {} ++static inline void ar5312_plat_mem_setup(void) {} ++static inline void ar5312_arch_init(void) {} ++ ++#endif ++ ++#endif /* __AR5312_H */ +--- /dev/null ++++ b/arch/mips/ath25/devices.h +@@ -0,0 +1,43 @@ ++#ifndef __ATH25_DEVICES_H ++#define __ATH25_DEVICES_H ++ ++#include ++ ++#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S) ++ ++#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */ ++ ++enum ath25_soc_type { ++ /* handled by ar5312.c */ ++ ATH25_SOC_AR2312, ++ ATH25_SOC_AR2313, ++ ATH25_SOC_AR5312, ++ ++ /* handled by ar2315.c */ ++ ATH25_SOC_AR2315, ++ ATH25_SOC_AR2316, ++ ATH25_SOC_AR2317, ++ ATH25_SOC_AR2318, ++ ++ ATH25_SOC_UNKNOWN ++}; ++ ++extern enum ath25_soc_type ath25_soc; ++extern struct ar231x_board_config ath25_board; ++extern void (*ath25_irq_dispatch)(void); ++ ++int ath25_find_config(phys_addr_t offset, unsigned long size); ++void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk); ++int ath25_add_wmac(int nr, u32 base, int irq); ++ ++static inline bool is_ar2315(void) ++{ ++ return (current_cpu_data.cputype == CPU_4KEC); ++} ++ ++static inline bool is_ar5312(void) ++{ ++ return !is_ar2315(); ++} ++ ++#endif +--- /dev/null ++++ b/arch/mips/ath25/devices.c +@@ -0,0 +1,125 @@ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++struct ar231x_board_config ath25_board; ++enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN; ++ ++static struct resource ath25_wmac0_res[] = { ++ { ++ .name = "wmac0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ath25_wmac1_res[] = { ++ { ++ .name = "wmac1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device ath25_wmac[] = { ++ { ++ .id = 0, ++ .name = "ar231x-wmac", ++ .resource = ath25_wmac0_res, ++ .num_resources = ARRAY_SIZE(ath25_wmac0_res), ++ .dev.platform_data = &ath25_board, ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-wmac", ++ .resource = ath25_wmac1_res, ++ .num_resources = ARRAY_SIZE(ath25_wmac1_res), ++ .dev.platform_data = &ath25_board, ++ }, ++}; ++ ++static const char * const soc_type_strings[] = { ++ [ATH25_SOC_AR5312] = "Atheros AR5312", ++ [ATH25_SOC_AR2312] = "Atheros AR2312", ++ [ATH25_SOC_AR2313] = "Atheros AR2313", ++ [ATH25_SOC_AR2315] = "Atheros AR2315", ++ [ATH25_SOC_AR2316] = "Atheros AR2316", ++ [ATH25_SOC_AR2317] = "Atheros AR2317", ++ [ATH25_SOC_AR2318] = "Atheros AR2318", ++ [ATH25_SOC_UNKNOWN] = "Atheros (unknown)", ++}; ++ ++const char *get_system_type(void) ++{ ++ if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) || ++ !soc_type_strings[ath25_soc]) ++ return soc_type_strings[ATH25_SOC_UNKNOWN]; ++ return soc_type_strings[ath25_soc]; ++} ++ ++void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk) ++{ ++ struct uart_port s; ++ ++ memset(&s, 0, sizeof(s)); ++ ++ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP; ++ s.iotype = UPIO_MEM32; ++ s.irq = irq; ++ s.regshift = 2; ++ s.mapbase = mapbase; ++ s.uartclk = uartclk; ++ ++ early_serial_setup(&s); ++} ++ ++int __init ath25_add_wmac(int nr, u32 base, int irq) ++{ ++ struct resource *res; ++ ++ ath25_wmac[nr].dev.platform_data = &ath25_board; ++ res = &ath25_wmac[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x10000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ath25_wmac[nr]); ++} ++ ++static int __init ath25_register_devices(void) ++{ ++ if (is_ar5312()) ++ ar5312_init_devices(); ++ else ++ ar2315_init_devices(); ++ ++ return 0; ++} ++ ++device_initcall(ath25_register_devices); ++ ++static int __init ath25_arch_init(void) ++{ ++ if (is_ar5312()) ++ ar5312_arch_init(); ++ else ++ ar2315_arch_init(); ++ ++ return 0; ++} ++ ++arch_initcall(ath25_arch_init); diff --git a/target/linux/ath25/patches-3.18/020-early-printk-support.patch b/target/linux/ath25/patches-3.18/020-early-printk-support.patch new file mode 100644 index 0000000..bd937d3 --- /dev/null +++ b/target/linux/ath25/patches-3.18/020-early-printk-support.patch @@ -0,0 +1,68 @@ +--- /dev/null ++++ b/arch/mips/ath25/early_printk.c +@@ -0,0 +1,44 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ */ ++ ++#include ++#include ++#include ++ ++#include "devices.h" ++#include "ar2315_regs.h" ++#include "ar5312_regs.h" ++ ++static inline void prom_uart_wr(void __iomem *base, unsigned reg, ++ unsigned char ch) ++{ ++ __raw_writel(ch, base + 4 * reg); ++} ++ ++static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) ++{ ++ return __raw_readl(base + 4 * reg); ++} ++ ++void prom_putchar(unsigned char ch) ++{ ++ static void __iomem *base; ++ ++ if (unlikely(base == NULL)) { ++ if (is_ar2315()) ++ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE)); ++ else ++ base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); ++ } ++ ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) ++ ; ++ prom_uart_wr(base, UART_TX, ch); ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) ++ ; ++} +--- a/arch/mips/ath25/Makefile ++++ b/arch/mips/ath25/Makefile +@@ -9,5 +9,8 @@ + # + + obj-y += board.o prom.o devices.o ++ ++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++ + obj-$(CONFIG_SOC_AR5312) += ar5312.o + obj-$(CONFIG_SOC_AR2315) += ar2315.o +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -106,6 +106,7 @@ config ATH25 + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_HAS_EARLY_PRINTK + help + Support for Atheros AR231x and Atheros AR531x based boards + diff --git a/target/linux/ath25/patches-3.18/030-ar2315_pci.patch b/target/linux/ath25/patches-3.18/030-ar2315_pci.patch new file mode 100644 index 0000000..08b7463 --- /dev/null +++ b/target/linux/ath25/patches-3.18/030-ar2315_pci.patch @@ -0,0 +1,613 @@ +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o + obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o + obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o ++obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o + obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o + obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o + obj-$(CONFIG_MIPS_PCI_VIRTIO) += pci-virtio-guest.o +--- /dev/null ++++ b/arch/mips/pci/pci-ar2315.c +@@ -0,0 +1,511 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see . ++ */ ++ ++/** ++ * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA ++ * and interrupt. PCI interface supports MMIO access method, but does not ++ * seem to support I/O ports. ++ * ++ * Read/write operation in the region 0x80000000-0xBFFFFFFF causes ++ * a memory read/write command on the PCI bus. 30 LSBs of address on ++ * the bus are taken from memory read/write request and 2 MSBs are ++ * determined by PCI unit configuration. ++ * ++ * To work with the configuration space instead of memory is necessary set ++ * the CFG_SEL bit in the PCI_MISC_CONFIG register. ++ * ++ * Devices on the bus can perform DMA requests via chip BAR1. PCI host ++ * controller BARs are programmend as if an external device is programmed. ++ * Which means that during configuration, IDSEL pin of the chip should be ++ * asserted. ++ * ++ * We know (and support) only one board that uses the PCI interface - ++ * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the ++ * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line ++ * and IDSEL pin of AR2315 is connected to AD[16] line. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * PCI Bus Interface Registers ++ */ ++#define AR2315_PCI_1MS_REG 0x0008 ++ ++#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_PCI_MISC_CONFIG 0x000c ++ ++#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */ ++#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ ++#define AR2315_PCIMISC_RST_MODE 0x00000030 ++#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ ++#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ ++#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ ++#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ ++#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ ++#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache ++ * disable */ ++ ++#define AR2315_PCI_OUT_TSTAMP 0x0010 ++ ++#define AR2315_PCI_UNCACHE_CFG 0x0014 ++ ++#define AR2315_PCI_IN_EN 0x0100 ++ ++#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ ++#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ ++#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ ++#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ ++ ++#define AR2315_PCI_IN_DIS 0x0104 ++ ++#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ ++#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ ++#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ ++#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ ++ ++#define AR2315_PCI_IN_PTR 0x0200 ++ ++#define AR2315_PCI_OUT_EN 0x0400 ++ ++#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ ++ ++#define AR2315_PCI_OUT_DIS 0x0404 ++ ++#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ ++ ++#define AR2315_PCI_OUT_PTR 0x0408 ++ ++/* PCI interrupt status (write one to clear) */ ++#define AR2315_PCI_ISR 0x0500 ++ ++#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */ ++#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */ ++#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */ ++#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */ ++#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */ ++#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */ ++#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */ ++#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */ ++#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */ ++#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */ ++#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */ ++#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */ ++ ++/* PCI interrupt mask */ ++#define AR2315_PCI_IMR 0x0504 ++ ++/* Global PCI interrupt enable */ ++#define AR2315_PCI_IER 0x0508 ++ ++#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */ ++#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */ ++ ++#define AR2315_PCI_HOST_IN_EN 0x0800 ++#define AR2315_PCI_HOST_IN_DIS 0x0804 ++#define AR2315_PCI_HOST_IN_PTR 0x0810 ++#define AR2315_PCI_HOST_OUT_EN 0x0900 ++#define AR2315_PCI_HOST_OUT_DIS 0x0904 ++#define AR2315_PCI_HOST_OUT_PTR 0x0908 ++ ++/* ++ * PCI interrupts, which share IP5 ++ * Keep ordered according to AR2315_PCI_INT_XXX bits ++ */ ++#define AR2315_PCI_IRQ_EXT 25 ++#define AR2315_PCI_IRQ_ABORT 26 ++#define AR2315_PCI_IRQ_COUNT 27 ++ ++/* Arbitrary size of memory region to access the configuration space */ ++#define AR2315_PCI_CFG_SIZE 0x00100000 ++ ++#define AR2315_PCI_HOST_SLOT 3 ++#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS) ++ ++/* ??? access BAR */ ++#define AR2315_PCI_HOST_MBAR0 0x10000000 ++/* RAM access BAR */ ++#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR ++/* ??? access BAR */ ++#define AR2315_PCI_HOST_MBAR2 0x30000000 ++ ++struct ar2315_pci_ctrl { ++ void __iomem *cfg_mem; ++ void __iomem *mmr_mem; ++ unsigned irq; ++ unsigned irq_ext; ++ struct irq_domain *domain; ++ struct pci_controller pci_ctrl; ++ struct resource mem_res; ++ struct resource io_res; ++}; ++ ++static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus) ++{ ++ struct pci_controller *hose = bus->sysdata; ++ ++ return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl); ++} ++ ++static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg) ++{ ++ return __raw_readl(apc->mmr_mem + reg); ++} ++ ++static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg, ++ u32 val) ++{ ++ __raw_writel(val, apc->mmr_mem + reg); ++} ++ ++static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg, ++ u32 mask, u32 val) ++{ ++ u32 ret = ar2315_pci_reg_read(apc, reg); ++ ++ ret &= ~mask; ++ ret |= val; ++ ar2315_pci_reg_write(apc, reg, ret); ++} ++ ++static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn, ++ int where, int size, u32 *ptr, bool write) ++{ ++ int func = PCI_FUNC(devfn); ++ int dev = PCI_SLOT(devfn); ++ u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3); ++ u32 mask = 0xffffffff >> 8 * (4 - size); ++ u32 sh = (where & 3) * 8; ++ u32 value, isr; ++ ++ /* Prevent access past the remapped area */ ++ if (addr >= AR2315_PCI_CFG_SIZE || dev > 18) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ /* Clear pending errors */ ++ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT); ++ /* Select Configuration access */ ++ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0, ++ AR2315_PCIMISC_CFG_SEL); ++ ++ mb(); /* PCI must see space change before we begin */ ++ ++ value = __raw_readl(apc->cfg_mem + addr); ++ ++ isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR); ++ ++ if (isr & AR2315_PCI_INT_ABORT) ++ goto exit_err; ++ ++ if (write) { ++ value = (value & ~(mask << sh)) | *ptr << sh; ++ __raw_writel(value, apc->cfg_mem + addr); ++ isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR); ++ if (isr & AR2315_PCI_INT_ABORT) ++ goto exit_err; ++ } else { ++ *ptr = (value >> sh) & mask; ++ } ++ ++ goto exit; ++ ++exit_err: ++ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT); ++ if (!write) ++ *ptr = 0xffffffff; ++ ++exit: ++ /* Select Memory access */ ++ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, ++ 0); ++ ++ return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND : ++ PCIBIOS_SUCCESSFUL; ++} ++ ++static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc, ++ unsigned devfn, int where, u32 *val) ++{ ++ return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val, ++ false); ++} ++ ++static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc, ++ unsigned devfn, int where, u32 val) ++{ ++ return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val, ++ true); ++} ++ ++static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where, ++ int size, u32 *value) ++{ ++ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus); ++ ++ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ return ar2315_pci_cfg_access(apc, devfn, where, size, value, false); ++} ++ ++static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where, ++ int size, u32 value) ++{ ++ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus); ++ ++ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true); ++} ++ ++static struct pci_ops ar2315_pci_ops = { ++ .read = ar2315_pci_cfg_read, ++ .write = ar2315_pci_cfg_write, ++}; ++ ++static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc) ++{ ++ unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0); ++ int res; ++ u32 id; ++ ++ res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id); ++ if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID) ++ return -ENODEV; ++ ++ /* Program MBARs */ ++ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0, ++ AR2315_PCI_HOST_MBAR0); ++ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1, ++ AR2315_PCI_HOST_MBAR1); ++ ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2, ++ AR2315_PCI_HOST_MBAR2); ++ ++ /* Run */ ++ ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY | ++ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | ++ PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK); ++ ++ return 0; ++} ++ ++static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc) ++{ ++ struct ar2315_pci_ctrl *apc = irq_get_handler_data(irq); ++ u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) & ++ ar2315_pci_reg_read(apc, AR2315_PCI_IMR); ++ unsigned pci_irq = 0; ++ ++ if (pending) ++ pci_irq = irq_find_mapping(apc->domain, __ffs(pending)); ++ ++ if (pci_irq) ++ generic_handle_irq(pci_irq); ++ else ++ spurious_interrupt(); ++} ++ ++static void ar2315_pci_irq_mask(struct irq_data *d) ++{ ++ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d); ++ ++ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0); ++} ++ ++static void ar2315_pci_irq_mask_ack(struct irq_data *d) ++{ ++ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d); ++ u32 m = BIT(d->hwirq); ++ ++ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0); ++ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m); ++} ++ ++static void ar2315_pci_irq_unmask(struct irq_data *d) ++{ ++ struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d); ++ ++ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq)); ++} ++ ++static struct irq_chip ar2315_pci_irq_chip = { ++ .name = "AR2315-PCI", ++ .irq_mask = ar2315_pci_irq_mask, ++ .irq_mask_ack = ar2315_pci_irq_mask_ack, ++ .irq_unmask = ar2315_pci_irq_unmask, ++}; ++ ++static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq, ++ irq_hw_number_t hw) ++{ ++ irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq); ++ irq_set_chip_data(irq, d->host_data); ++ return 0; ++} ++ ++static struct irq_domain_ops ar2315_pci_irq_domain_ops = { ++ .map = ar2315_pci_irq_map, ++}; ++ ++static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc) ++{ ++ ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0); ++ ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT | ++ AR2315_PCI_INT_EXT), 0); ++ ++ apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT); ++ ++ irq_set_chained_handler(apc->irq, ar2315_pci_irq_handler); ++ irq_set_handler_data(apc->irq, apc); ++ ++ /* Clear any pending Abort or external Interrupts ++ * and enable interrupt processing */ ++ ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT | ++ AR2315_PCI_INT_EXT); ++ ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE); ++} ++ ++static int ar2315_pci_probe(struct platform_device *pdev) ++{ ++ struct ar2315_pci_ctrl *apc; ++ struct device *dev = &pdev->dev; ++ struct resource *res; ++ int irq, err; ++ ++ apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL); ++ if (!apc) ++ return -ENOMEM; ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return -EINVAL; ++ apc->irq = irq; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "ar2315-pci-ctrl"); ++ apc->mmr_mem = devm_ioremap_resource(dev, res); ++ if (IS_ERR(apc->mmr_mem)) ++ return PTR_ERR(apc->mmr_mem); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "ar2315-pci-ext"); ++ if (!res) ++ return -EINVAL; ++ ++ apc->mem_res.name = "AR2315 PCI mem space"; ++ apc->mem_res.parent = res; ++ apc->mem_res.start = res->start; ++ apc->mem_res.end = res->end; ++ apc->mem_res.flags = IORESOURCE_MEM; ++ ++ /* Remap PCI config space */ ++ apc->cfg_mem = devm_ioremap_nocache(dev, res->start, ++ AR2315_PCI_CFG_SIZE); ++ if (!apc->cfg_mem) { ++ dev_err(dev, "failed to remap PCI config space\n"); ++ return -ENOMEM; ++ } ++ ++ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ ++ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, ++ AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_LOW); ++ msleep(100); ++ ++ /* Bring the PCI out of reset */ ++ ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, ++ AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); ++ ++ ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG, ++ 0x1E | /* 1GB uncached */ ++ (1 << 5) | /* Enable uncached */ ++ (0x2 << 30) /* Base: 0x80000000 */); ++ ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG); ++ ++ msleep(500); ++ ++ err = ar2315_pci_host_setup(apc); ++ if (err) ++ return err; ++ ++ apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT, ++ &ar2315_pci_irq_domain_ops, apc); ++ if (!apc->domain) { ++ dev_err(dev, "failed to add IRQ domain\n"); ++ return -ENOMEM; ++ } ++ ++ ar2315_pci_irq_init(apc); ++ ++ /* PCI controller does not support I/O ports */ ++ apc->io_res.name = "AR2315 IO space"; ++ apc->io_res.start = 0; ++ apc->io_res.end = 0; ++ apc->io_res.flags = IORESOURCE_IO, ++ ++ apc->pci_ctrl.pci_ops = &ar2315_pci_ops; ++ apc->pci_ctrl.mem_resource = &apc->mem_res, ++ apc->pci_ctrl.io_resource = &apc->io_res, ++ ++ register_pci_controller(&apc->pci_ctrl); ++ ++ dev_info(dev, "register PCI controller\n"); ++ ++ return 0; ++} ++ ++static struct platform_driver ar2315_pci_driver = { ++ .probe = ar2315_pci_probe, ++ .driver = { ++ .name = "ar2315-pci", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ar2315_pci_init(void) ++{ ++ return platform_driver_register(&ar2315_pci_driver); ++} ++arch_initcall(ar2315_pci_init); ++ ++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus); ++ ++ return slot ? 0 : apc->irq_ext; ++} ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ return 0; ++} +--- a/arch/mips/ath25/Kconfig ++++ b/arch/mips/ath25/Kconfig +@@ -7,3 +7,10 @@ config SOC_AR2315 + bool "Atheros AR2315+ SoC support" + depends on ATH25 + default y ++ ++config PCI_AR2315 ++ bool "Atheros AR2315 PCI controller support" ++ depends on SOC_AR2315 ++ select HW_HAS_PCI ++ select PCI ++ default y +--- a/arch/mips/ath25/ar2315.c ++++ b/arch/mips/ath25/ar2315.c +@@ -134,6 +134,10 @@ static void ar2315_irq_dispatch(void) + + if (pending & CAUSEF_IP3) + do_IRQ(AR2315_IRQ_WLAN0); ++#ifdef CONFIG_PCI_AR2315 ++ else if (pending & CAUSEF_IP5) ++ do_IRQ(AR2315_IRQ_LCBUS_PCI); ++#endif + else if (pending & CAUSEF_IP2) + do_IRQ(AR2315_IRQ_MISC); + else if (pending & CAUSEF_IP7) +@@ -299,10 +303,62 @@ void __init ar2315_plat_mem_setup(void) + _machine_restart = ar2315_restart; + } + ++#ifdef CONFIG_PCI_AR2315 ++static struct resource ar2315_pci_res[] = { ++ { ++ .name = "ar2315-pci-ctrl", ++ .flags = IORESOURCE_MEM, ++ .start = AR2315_PCI_BASE, ++ .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1, ++ }, ++ { ++ .name = "ar2315-pci-ext", ++ .flags = IORESOURCE_MEM, ++ .start = AR2315_PCI_EXT_BASE, ++ .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1, ++ }, ++ { ++ .name = "ar2315-pci", ++ .flags = IORESOURCE_IRQ, ++ .start = AR2315_IRQ_LCBUS_PCI, ++ .end = AR2315_IRQ_LCBUS_PCI, ++ }, ++}; ++#endif ++ + void __init ar2315_arch_init(void) + { + unsigned irq = irq_create_mapping(ar2315_misc_irq_domain, + AR2315_MISC_IRQ_UART0); + + ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency()); ++ ++#ifdef CONFIG_PCI_AR2315 ++ if (ath25_soc == ATH25_SOC_AR2315) { ++ /* Reset PCI DMA logic */ ++ ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA); ++ msleep(20); ++ ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0); ++ msleep(20); ++ ++ /* Configure endians */ ++ ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB | ++ AR2315_CONFIG_PCIAHB_BRIDGE); ++ ++ /* Configure as PCI host with DMA */ ++ ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | ++ (AR2315_PCICLK_IN_FREQ_DIV_6 << ++ AR2315_PCICLK_DIV_S)); ++ ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); ++ ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | ++ AR2315_IF_MASK, AR2315_IF_PCI | ++ AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | ++ (AR2315_IF_PCI_CLK_OUTPUT_CLK << ++ AR2315_IF_PCI_CLK_SHIFT)); ++ ++ platform_device_register_simple("ar2315-pci", -1, ++ ar2315_pci_res, ++ ARRAY_SIZE(ar2315_pci_res)); ++ } ++#endif + } diff --git a/target/linux/ath25/patches-3.18/107-ar5312_gpio.patch b/target/linux/ath25/patches-3.18/107-ar5312_gpio.patch new file mode 100644 index 0000000..a6d0a88 --- /dev/null +++ b/target/linux/ath25/patches-3.18/107-ar5312_gpio.patch @@ -0,0 +1,212 @@ +--- a/arch/mips/ath25/Kconfig ++++ b/arch/mips/ath25/Kconfig +@@ -1,6 +1,7 @@ + config SOC_AR5312 + bool "Atheros AR5312/AR2312+ SoC support" + depends on ATH25 ++ select GPIO_AR5312 + default y + + config SOC_AR2315 +--- a/arch/mips/ath25/ar5312.c ++++ b/arch/mips/ath25/ar5312.c +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -180,6 +181,22 @@ static struct platform_device ar5312_phy + .num_resources = 1, + }; + ++static struct resource ar5312_gpio_res[] = { ++ { ++ .name = "ar5312-gpio", ++ .flags = IORESOURCE_MEM, ++ .start = AR5312_GPIO_BASE, ++ .end = AR5312_GPIO_BASE + AR5312_GPIO_SIZE - 1, ++ }, ++}; ++ ++static struct platform_device ar5312_gpio = { ++ .name = "ar5312-gpio", ++ .id = -1, ++ .resource = ar5312_gpio_res, ++ .num_resources = ARRAY_SIZE(ar5312_gpio_res), ++}; ++ + static void __init ar5312_flash_init(void) + { + void __iomem *flashctl_base; +@@ -247,6 +264,8 @@ void __init ar5312_init_devices(void) + + platform_device_register(&ar5312_physmap_flash); + ++ platform_device_register(&ar5312_gpio); ++ + switch (ath25_soc) { + case ATH25_SOC_AR5312: + if (!ath25_board.radio) +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -112,6 +112,13 @@ config GPIO_MAX730X + + comment "Memory mapped GPIO drivers:" + ++config GPIO_AR5312 ++ bool "AR5312 SoC GPIO support" ++ default y if SOC_AR5312 ++ depends on SOC_AR5312 ++ help ++ Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs. ++ + config GPIO_CLPS711X + tristate "CLPS711X GPIO support" + depends on ARCH_CLPS711X || COMPILE_TEST +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o + obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o + obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o + obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o ++obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o + obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o + obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o + obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o +--- /dev/null ++++ b/drivers/gpio/gpio-ar5312.c +@@ -0,0 +1,121 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * Copyright (C) 2012 Alexandros C. Couloumbis ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "ar5312-gpio" ++ ++#define AR5312_GPIO_DO 0x00 /* output register */ ++#define AR5312_GPIO_DI 0x04 /* intput register */ ++#define AR5312_GPIO_CR 0x08 /* control register */ ++ ++#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */ ++#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */ ++#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ ++#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ ++ ++#define AR5312_GPIO_NUM 8 ++ ++static void __iomem *ar5312_mem; ++ ++static inline u32 ar5312_gpio_reg_read(unsigned reg) ++{ ++ return __raw_readl(ar5312_mem + reg); ++} ++ ++static inline void ar5312_gpio_reg_write(unsigned reg, u32 val) ++{ ++ __raw_writel(val, ar5312_mem + reg); ++} ++ ++static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val) ++{ ++ ar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val); ++} ++ ++static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio) ++{ ++ return (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1; ++} ++ ++static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val) ++{ ++ u32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO); ++ ++ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio); ++ ar5312_gpio_reg_write(AR5312_GPIO_DO, reg); ++} ++ ++static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) ++{ ++ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio); ++ return 0; ++} ++ ++static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val) ++{ ++ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0); ++ ar5312_gpio_set_val(chip, gpio, val); ++ return 0; ++} ++ ++static struct gpio_chip ar5312_gpio_chip = { ++ .label = DRIVER_NAME, ++ .direction_input = ar5312_gpio_dir_in, ++ .direction_output = ar5312_gpio_dir_out, ++ .set = ar5312_gpio_set_val, ++ .get = ar5312_gpio_get_val, ++ .base = 0, ++ .ngpio = AR5312_GPIO_NUM, ++}; ++ ++static int ar5312_gpio_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct resource *res; ++ int ret; ++ ++ if (ar5312_mem) ++ return -EBUSY; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ar5312_mem = devm_ioremap_resource(dev, res); ++ if (IS_ERR(ar5312_mem)) ++ return PTR_ERR(ar5312_mem); ++ ++ ar5312_gpio_chip.dev = dev; ++ ret = gpiochip_add(&ar5312_gpio_chip); ++ if (ret) { ++ dev_err(dev, "failed to add gpiochip\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver ar5312_gpio_driver = { ++ .probe = ar5312_gpio_probe, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init ar5312_gpio_init(void) ++{ ++ return platform_driver_register(&ar5312_gpio_driver); ++} ++subsys_initcall(ar5312_gpio_init); +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -107,6 +107,7 @@ config ATH25 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_HAS_EARLY_PRINTK ++ select ARCH_REQUIRE_GPIOLIB + help + Support for Atheros AR231x and Atheros AR531x based boards + diff --git a/target/linux/ath25/patches-3.18/108-ar2315_gpio.patch b/target/linux/ath25/patches-3.18/108-ar2315_gpio.patch new file mode 100644 index 0000000..5d97853 --- /dev/null +++ b/target/linux/ath25/patches-3.18/108-ar2315_gpio.patch @@ -0,0 +1,363 @@ +--- a/arch/mips/ath25/Kconfig ++++ b/arch/mips/ath25/Kconfig +@@ -7,6 +7,7 @@ config SOC_AR5312 + config SOC_AR2315 + bool "Atheros AR2315+ SoC support" + depends on ATH25 ++ select GPIO_AR2315 + default y + + config PCI_AR2315 +--- a/arch/mips/ath25/ar2315.c ++++ b/arch/mips/ath25/ar2315.c +@@ -21,6 +21,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -167,11 +169,42 @@ void __init ar2315_arch_init_irq(void) + ar2315_misc_irq_domain = domain; + } + ++static struct resource ar2315_gpio_res[] = { ++ { ++ .name = "ar2315-gpio", ++ .flags = IORESOURCE_MEM, ++ .start = AR2315_RST_BASE + AR2315_GPIO, ++ .end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1, ++ }, ++ { ++ .name = "ar2315-gpio", ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .name = "ar2315-gpio-irq-base", ++ .flags = IORESOURCE_IRQ, ++ .start = AR231X_GPIO_IRQ_BASE, ++ .end = AR231X_GPIO_IRQ_BASE, ++ } ++}; ++ ++static struct platform_device ar2315_gpio = { ++ .id = -1, ++ .name = "ar2315-gpio", ++ .resource = ar2315_gpio_res, ++ .num_resources = ARRAY_SIZE(ar2315_gpio_res) ++}; ++ + void __init ar2315_init_devices(void) + { + /* Find board configuration */ + ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE); + ++ ar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain, ++ AR2315_MISC_IRQ_GPIO); ++ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; ++ platform_device_register(&ar2315_gpio); ++ + ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0); + } + +@@ -187,8 +220,8 @@ static void ar2315_restart(char *command + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits + * a workaround. Give it some time to attempt a gpio based hardware + * reset (atheros reference design workaround) */ +- +- /* TODO: implement the GPIO reset workaround */ ++ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset"); ++ mdelay(100); + + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic + * workaround. Attempt to jump to the mips reset location - +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -112,6 +112,13 @@ config GPIO_MAX730X + + comment "Memory mapped GPIO drivers:" + ++config GPIO_AR2315 ++ bool "AR2315 SoC GPIO support" ++ default y if SOC_AR2315 ++ depends on SOC_AR2315 ++ help ++ Say yes here to enable GPIO support for Atheros AR2315+ SoCs. ++ + config GPIO_AR5312 + bool "AR5312 SoC GPIO support" + default y if SOC_AR5312 +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -17,6 +17,7 @@ obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o + obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o + obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o + obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o ++obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o + obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o + obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o + obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o +--- /dev/null ++++ b/drivers/gpio/gpio-ar2315.c +@@ -0,0 +1,233 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ * Copyright (C) 2012 Alexandros C. Couloumbis ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "ar2315-gpio" ++ ++#define AR2315_GPIO_DI 0x0000 ++#define AR2315_GPIO_DO 0x0008 ++#define AR2315_GPIO_DIR 0x0010 ++#define AR2315_GPIO_INT 0x0018 ++ ++#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */ ++#define AR2315_GPIO_DIR_I(x) (0) /* input */ ++ ++#define AR2315_GPIO_INT_NUM_M 0x3F /* mask for GPIO num */ ++#define AR2315_GPIO_INT_TRIG(x) ((x) << 6) /* interrupt trigger */ ++#define AR2315_GPIO_INT_TRIG_M (0x3 << 6) /* mask for int trig */ ++ ++#define AR2315_GPIO_INT_TRIG_OFF 0 /* Triggerring off */ ++#define AR2315_GPIO_INT_TRIG_LOW 1 /* Low Level Triggered */ ++#define AR2315_GPIO_INT_TRIG_HIGH 2 /* High Level Triggered */ ++#define AR2315_GPIO_INT_TRIG_EDGE 3 /* Edge Triggered */ ++ ++#define AR2315_GPIO_NUM 22 ++ ++static u32 ar2315_gpio_intmask; ++static u32 ar2315_gpio_intval; ++static unsigned ar2315_gpio_irq_base; ++static void __iomem *ar2315_mem; ++ ++static inline u32 ar2315_gpio_reg_read(unsigned reg) ++{ ++ return __raw_readl(ar2315_mem + reg); ++} ++ ++static inline void ar2315_gpio_reg_write(unsigned reg, u32 val) ++{ ++ __raw_writel(val, ar2315_mem + reg); ++} ++ ++static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val) ++{ ++ ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val); ++} ++ ++static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc) ++{ ++ u32 pend; ++ int bit = -1; ++ ++ /* only do one gpio interrupt at a time */ ++ pend = ar2315_gpio_reg_read(AR2315_GPIO_DI); ++ pend ^= ar2315_gpio_intval; ++ pend &= ar2315_gpio_intmask; ++ ++ if (pend) { ++ bit = fls(pend) - 1; ++ pend &= ~(1 << bit); ++ ar2315_gpio_intval ^= (1 << bit); ++ } ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) != ++ AR2315_GPIO_DIR_I(bit)) ++ return; ++ ++ if (bit >= 0) ++ generic_handle_irq(ar2315_gpio_irq_base + bit); ++} ++ ++static void ar2315_gpio_int_setup(unsigned gpio, int trig) ++{ ++ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT); ++ ++ reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M); ++ reg |= gpio | AR2315_GPIO_INT_TRIG(trig); ++ ar2315_gpio_reg_write(AR2315_GPIO_INT, reg); ++} ++ ++static void ar2315_gpio_irq_unmask(struct irq_data *d) ++{ ++ unsigned gpio = d->irq - ar2315_gpio_irq_base; ++ u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR); ++ ++ /* Enable interrupt with edge detection */ ++ if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio)) ++ return; ++ ++ ar2315_gpio_intmask |= (1 << gpio); ++ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE); ++} ++ ++static void ar2315_gpio_irq_mask(struct irq_data *d) ++{ ++ unsigned gpio = d->irq - ar2315_gpio_irq_base; ++ ++ /* Disable interrupt */ ++ ar2315_gpio_intmask &= ~(1 << gpio); ++ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF); ++} ++ ++static struct irq_chip ar2315_gpio_irq_chip = { ++ .name = DRIVER_NAME, ++ .irq_unmask = ar2315_gpio_irq_unmask, ++ .irq_mask = ar2315_gpio_irq_mask, ++}; ++ ++static void ar2315_gpio_irq_init(unsigned irq) ++{ ++ unsigned i; ++ ++ ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI); ++ for (i = 0; i < AR2315_GPIO_NUM; i++) { ++ unsigned _irq = ar2315_gpio_irq_base + i; ++ ++ irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip, ++ handle_level_irq); ++ } ++ irq_set_chained_handler(irq, ar2315_gpio_irq_handler); ++} ++ ++static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio) ++{ ++ return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1; ++} ++ ++static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val) ++{ ++ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO); ++ ++ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio); ++ ar2315_gpio_reg_write(AR2315_GPIO_DO, reg); ++} ++ ++static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) ++{ ++ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0); ++ return 0; ++} ++ ++static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val) ++{ ++ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio); ++ ar2315_gpio_set_val(chip, gpio, val); ++ return 0; ++} ++ ++static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) ++{ ++ return ar2315_gpio_irq_base + gpio; ++} ++ ++static struct gpio_chip ar2315_gpio_chip = { ++ .label = DRIVER_NAME, ++ .direction_input = ar2315_gpio_dir_in, ++ .direction_output = ar2315_gpio_dir_out, ++ .set = ar2315_gpio_set_val, ++ .get = ar2315_gpio_get_val, ++ .to_irq = ar2315_gpio_to_irq, ++ .base = 0, ++ .ngpio = AR2315_GPIO_NUM, ++}; ++ ++static int ar2315_gpio_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct resource *res; ++ unsigned irq; ++ int ret; ++ ++ if (ar2315_mem) ++ return -EBUSY; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, ++ "ar2315-gpio-irq-base"); ++ if (!res) { ++ dev_err(dev, "not found GPIO IRQ base\n"); ++ return -ENXIO; ++ } ++ ar2315_gpio_irq_base = res->start; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME); ++ if (!res) { ++ dev_err(dev, "not found IRQ number\n"); ++ return -ENXIO; ++ } ++ irq = res->start; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME); ++ ar2315_mem = devm_ioremap_resource(dev, res); ++ if (IS_ERR(ar2315_mem)) ++ return PTR_ERR(ar2315_mem); ++ ++ ar2315_gpio_chip.dev = dev; ++ ret = gpiochip_add(&ar2315_gpio_chip); ++ if (ret) { ++ dev_err(dev, "failed to add gpiochip\n"); ++ return ret; ++ } ++ ++ ar2315_gpio_irq_init(irq); ++ ++ return 0; ++} ++ ++static struct platform_driver ar2315_gpio_driver = { ++ .probe = ar2315_gpio_probe, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init ar2315_gpio_init(void) ++{ ++ return platform_driver_register(&ar2315_gpio_driver); ++} ++subsys_initcall(ar2315_gpio_init); +--- a/arch/mips/ath25/devices.h ++++ b/arch/mips/ath25/devices.h +@@ -3,6 +3,11 @@ + + #include + ++#define AR231X_GPIO_IRQ_BASE 0x30 ++ ++/* GPIO number for AR2315/16 reset issue workaround */ ++#define AR2315_RESET_GPIO 5 ++ + #define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S) + + #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */ +--- a/arch/mips/ath25/ar2315_regs.h ++++ b/arch/mips/ath25/ar2315_regs.h +@@ -315,6 +315,9 @@ + #define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018 + #define AR2315_MEM_CFG_BANKADDR_BITS_S 3 + ++/* GPIO MMR base address */ ++#define AR2315_GPIO 0x0088 ++ + /* + * Local Bus Interface Registers + */ diff --git a/target/linux/ath25/patches-3.18/110-ar2313_ethernet.patch b/target/linux/ath25/patches-3.18/110-ar2313_ethernet.patch new file mode 100644 index 0000000..bef70dd --- /dev/null +++ b/target/linux/ath25/patches-3.18/110-ar2313_ethernet.patch @@ -0,0 +1,1828 @@ +--- a/drivers/net/ethernet/atheros/Makefile ++++ b/drivers/net/ethernet/atheros/Makefile +@@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/ + obj-$(CONFIG_ATL1E) += atl1e/ + obj-$(CONFIG_ATL1C) += atl1c/ + obj-$(CONFIG_ALX) += alx/ ++obj-$(CONFIG_NET_AR231X) += ar231x/ +--- a/drivers/net/ethernet/atheros/Kconfig ++++ b/drivers/net/ethernet/atheros/Kconfig +@@ -5,7 +5,7 @@ + config NET_VENDOR_ATHEROS + bool "Atheros devices" + default y +- depends on PCI ++ depends on (PCI || ATH25) + ---help--- + If you have a network (Ethernet) card belonging to this class, say Y + and read the Ethernet-HOWTO, available from +@@ -80,4 +80,10 @@ config ALX + To compile this driver as a module, choose M here. The module + will be called alx. + ++config NET_AR231X ++ tristate "Atheros AR231X built-in Ethernet support" ++ depends on ATH25 ++ help ++ Support for the AR231x/531x ethernet controller ++ + endif # NET_VENDOR_ATHEROS +--- /dev/null ++++ b/drivers/net/ethernet/atheros/ar231x/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_NET_AR231X) += ar231x.o +--- /dev/null ++++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c +@@ -0,0 +1,1206 @@ ++/* ++ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Additional credits: ++ * This code is taken from John Taylor's Sibyte driver and then ++ * modified for the AR2313. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define AR2313_MTU 1692 ++#define AR2313_PRIOS 1 ++#define AR2313_QUEUES (2*AR2313_PRIOS) ++#define AR2313_DESCR_ENTRIES 64 ++ ++#ifndef min ++#define min(a, b) (((a) < (b)) ? (a) : (b)) ++#endif ++ ++#ifndef SMP_CACHE_BYTES ++#define SMP_CACHE_BYTES L1_CACHE_BYTES ++#endif ++ ++#define AR2313_MBOX_SET_BIT 0x8 ++ ++#include "ar231x.h" ++ ++/** ++ * New interrupt handler strategy: ++ * ++ * An old interrupt handler worked using the traditional method of ++ * replacing an skbuff with a new one when a packet arrives. However ++ * the rx rings do not need to contain a static number of buffer ++ * descriptors, thus it makes sense to move the memory allocation out ++ * of the main interrupt handler and do it in a bottom half handler ++ * and only allocate new buffers when the number of buffers in the ++ * ring is below a certain threshold. In order to avoid starving the ++ * NIC under heavy load it is however necessary to force allocation ++ * when hitting a minimum threshold. The strategy for alloction is as ++ * follows: ++ * ++ * RX_LOW_BUF_THRES - allocate buffers in the bottom half ++ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate ++ * the buffers in the interrupt handler ++ * RX_RING_THRES - maximum number of buffers in the rx ring ++ * ++ * One advantagous side effect of this allocation approach is that the ++ * entire rx processing can be done without holding any spin lock ++ * since the rx rings and registers are totally independent of the tx ++ * ring and its registers. This of course includes the kmalloc's of ++ * new skb's. Thus start_xmit can run in parallel with rx processing ++ * and the memory allocation on SMP systems. ++ * ++ * Note that running the skb reallocation in a bottom half opens up ++ * another can of races which needs to be handled properly. In ++ * particular it can happen that the interrupt handler tries to run ++ * the reallocation while the bottom half is either running on another ++ * CPU or was interrupted on the same CPU. To get around this the ++ * driver uses bitops to prevent the reallocation routines from being ++ * reentered. ++ * ++ * TX handling can also be done without holding any spin lock, wheee ++ * this is fun! since tx_csm is only written to by the interrupt ++ * handler. ++ */ ++ ++/** ++ * Threshold values for RX buffer allocation - the low water marks for ++ * when to start refilling the rings are set to 75% of the ring ++ * sizes. It seems to make sense to refill the rings entirely from the ++ * intrrupt handler once it gets below the panic threshold, that way ++ * we don't risk that the refilling is moved to another CPU when the ++ * one running the interrupt handler just got the slab code hot in its ++ * cache. ++ */ ++#define RX_RING_SIZE AR2313_DESCR_ENTRIES ++#define RX_PANIC_THRES (RX_RING_SIZE/4) ++#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) ++#define CRC_LEN 4 ++#define RX_OFFSET 2 ++ ++#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) ++#define VLAN_HDR 4 ++#else ++#define VLAN_HDR 0 ++#endif ++ ++#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \ ++ RX_OFFSET) ++ ++#ifdef MODULE ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); ++MODULE_DESCRIPTION("AR231x Ethernet driver"); ++#endif ++ ++#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) ++ ++/* prototypes */ ++static void ar231x_halt(struct net_device *dev); ++static void rx_tasklet_func(unsigned long data); ++static void rx_tasklet_cleanup(struct net_device *dev); ++static void ar231x_multicast_list(struct net_device *dev); ++static void ar231x_tx_timeout(struct net_device *dev); ++ ++static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); ++static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, ++ u16 value); ++static int ar231x_mdiobus_reset(struct mii_bus *bus); ++static int ar231x_mdiobus_probe(struct net_device *dev); ++static void ar231x_adjust_link(struct net_device *dev); ++ ++#ifndef ERR ++#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) ++#endif ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void ++ar231x_netpoll(struct net_device *dev) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ar231x_interrupt(dev->irq, dev); ++ local_irq_restore(flags); ++} ++#endif ++ ++static const struct net_device_ops ar231x_ops = { ++ .ndo_open = ar231x_open, ++ .ndo_stop = ar231x_close, ++ .ndo_start_xmit = ar231x_start_xmit, ++ .ndo_set_rx_mode = ar231x_multicast_list, ++ .ndo_do_ioctl = ar231x_ioctl, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_tx_timeout = ar231x_tx_timeout, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = ar231x_netpoll, ++#endif ++}; ++ ++static int ar231x_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ struct ar231x_private *sp; ++ struct resource *res; ++ unsigned long ar_eth_base; ++ char buf[64]; ++ ++ dev = alloc_etherdev(sizeof(struct ar231x_private)); ++ ++ if (dev == NULL) { ++ printk(KERN_ERR ++ "ar231x: Unable to allocate net_device structure!\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, dev); ++ ++ sp = netdev_priv(dev); ++ sp->dev = dev; ++ sp->cfg = pdev->dev.platform_data; ++ ++ sprintf(buf, "eth%d_membase", pdev->id); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); ++ if (!res) ++ return -ENODEV; ++ ++ sp->link = 0; ++ ar_eth_base = res->start; ++ ++ sprintf(buf, "eth%d_irq", pdev->id); ++ dev->irq = platform_get_irq_byname(pdev, buf); ++ ++ spin_lock_init(&sp->lock); ++ ++ dev->features |= NETIF_F_HIGHDMA; ++ dev->netdev_ops = &ar231x_ops; ++ ++ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long)dev); ++ tasklet_disable(&sp->rx_tasklet); ++ ++ sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs)); ++ if (!sp->eth_regs) { ++ printk("Can't remap eth registers\n"); ++ return -ENXIO; ++ } ++ ++ /** ++ * When there's only one MAC, PHY regs are typically on ENET0, ++ * even though the MAC might be on ENET1. ++ * So remap PHY regs separately. ++ */ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii"); ++ if (!res) { ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "eth1_mii"); ++ if (!res) ++ return -ENODEV; ++ } ++ sp->phy_regs = ioremap_nocache(res->start, resource_size(res)); ++ if (!sp->phy_regs) { ++ printk("Can't remap phy registers\n"); ++ return -ENXIO; ++ } ++ ++ sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000, ++ sizeof(*sp->dma_regs)); ++ if (!sp->dma_regs) { ++ printk("Can't remap DMA registers\n"); ++ return -ENXIO; ++ } ++ dev->base_addr = ar_eth_base + 0x1000; ++ ++ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); ++ sp->name[sizeof(sp->name) - 1] = '\0'; ++ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); ++ ++ if (ar231x_init(dev)) { ++ /* ar231x_init() calls ar231x_init_cleanup() on error */ ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ if (register_netdev(dev)) { ++ printk("%s: register_netdev failed\n", __func__); ++ return -1; ++ } ++ ++ printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr, ++ dev->irq); ++ ++ sp->mii_bus = mdiobus_alloc(); ++ if (sp->mii_bus == NULL) ++ return -1; ++ ++ sp->mii_bus->priv = dev; ++ sp->mii_bus->read = ar231x_mdiobus_read; ++ sp->mii_bus->write = ar231x_mdiobus_write; ++ sp->mii_bus->reset = ar231x_mdiobus_reset; ++ sp->mii_bus->name = "ar231x_eth_mii"; ++ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); ++ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); ++ *sp->mii_bus->irq = PHY_POLL; ++ ++ mdiobus_register(sp->mii_bus); ++ ++ if (ar231x_mdiobus_probe(dev) != 0) { ++ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ /* start link poll timer */ ++ ar231x_setup_timer(dev); ++ ++ return 0; ++} ++ ++static void ar231x_multicast_list(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int filter; ++ ++ filter = sp->eth_regs->mac_control; ++ ++ if (dev->flags & IFF_PROMISC) ++ filter |= MAC_CONTROL_PR; ++ else ++ filter &= ~MAC_CONTROL_PR; ++ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) ++ filter |= MAC_CONTROL_PM; ++ else ++ filter &= ~MAC_CONTROL_PM; ++ ++ sp->eth_regs->mac_control = filter; ++} ++ ++static void rx_tasklet_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ /** ++ * Tasklet may be scheduled. Need to get it removed from the list ++ * since we're about to free the struct. ++ */ ++ ++ sp->unloading = 1; ++ tasklet_enable(&sp->rx_tasklet); ++ tasklet_kill(&sp->rx_tasklet); ++} ++ ++static int ar231x_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ mdiobus_unregister(sp->mii_bus); ++ mdiobus_free(sp->mii_bus); ++ kfree(dev); ++ return 0; ++} ++ ++/** ++ * Restart the AR2313 ethernet controller. ++ */ ++static int ar231x_restart(struct net_device *dev) ++{ ++ /* disable interrupts */ ++ disable_irq(dev->irq); ++ ++ /* stop mac */ ++ ar231x_halt(dev); ++ ++ /* initialize */ ++ ar231x_init(dev); ++ ++ /* enable interrupts */ ++ enable_irq(dev->irq); ++ ++ return 0; ++} ++ ++static struct platform_driver ar231x_driver = { ++ .driver.name = "ar231x-eth", ++ .probe = ar231x_probe, ++ .remove = ar231x_remove, ++}; ++ ++module_platform_driver(ar231x_driver); ++ ++static void ar231x_free_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ if (sp->rx_ring != NULL) { ++ kfree((void *)KSEG0ADDR(sp->rx_ring)); ++ sp->rx_ring = NULL; ++ sp->tx_ring = NULL; ++ } ++} ++ ++static int ar231x_allocate_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int size; ++ int j; ++ ar231x_descr_t *space; ++ ++ if (sp->rx_ring != NULL) { ++ printk("%s: already done.\n", __func__); ++ return 0; ++ } ++ ++ size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES); ++ space = kmalloc(size, GFP_KERNEL); ++ if (space == NULL) ++ return 1; ++ ++ /* invalidate caches */ ++ dma_cache_inv((unsigned int)space, size); ++ ++ /* now convert pointer to KSEG1 */ ++ space = (ar231x_descr_t *)KSEG1ADDR(space); ++ ++ memset((void *)space, 0, size); ++ ++ sp->rx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ sp->tx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ /* Initialize the transmit Descriptors */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ ar231x_descr_t *td = &sp->tx_ring[j]; ++ ++ td->status = 0; ++ td->devcs = DMA_TX1_CHAINED; ++ td->addr = 0; ++ td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]); ++ } ++ ++ return 0; ++} ++ ++/** ++ * Generic cleanup handling data allocated during init. Used when the ++ * module is unloaded or if an error occurs during initialization ++ */ ++static void ar231x_init_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb; ++ int j; ++ ++ ar231x_free_descriptors(dev); ++ ++ if (sp->eth_regs) ++ iounmap((void *)sp->eth_regs); ++ if (sp->dma_regs) ++ iounmap((void *)sp->dma_regs); ++ if (sp->phy_regs) ++ iounmap((void *)sp->phy_regs); ++ ++ if (sp->rx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->rx_skb[j]; ++ if (skb) { ++ sp->rx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->rx_skb); ++ sp->rx_skb = NULL; ++ } ++ ++ if (sp->tx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ sp->tx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->tx_skb); ++ sp->tx_skb = NULL; ++ } ++} ++ ++static int ar231x_setup_timer(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ init_timer(&sp->link_timer); ++ ++ sp->link_timer.function = ar231x_link_timer_fn; ++ sp->link_timer.data = (int)dev; ++ sp->link_timer.expires = jiffies + HZ; ++ ++ add_timer(&sp->link_timer); ++ return 0; ++} ++ ++static void ar231x_link_timer_fn(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ /** ++ * See if the link status changed. ++ * This was needed to make sure we set the PHY to the ++ * autonegotiated value of half or full duplex. ++ */ ++ ar231x_check_link(dev); ++ ++ /** ++ * Loop faster when we don't have link. ++ * This was needed to speed up the AP bootstrap time. ++ */ ++ if (sp->link == 0) ++ mod_timer(&sp->link_timer, jiffies + HZ / 2); ++ else ++ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); ++} ++ ++static void ar231x_check_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u16 phy_data; ++ ++ phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); ++ if (sp->phy_data != phy_data) { ++ if (phy_data & BMSR_LSTATUS) { ++ /** ++ * Link is present, ready link partner ability to ++ * deterine duplexity. ++ */ ++ int duplex = 0; ++ u16 reg; ++ ++ sp->link = 1; ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, ++ MII_BMCR); ++ if (reg & BMCR_ANENABLE) { ++ /* auto neg enabled */ ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, ++ MII_LPA); ++ duplex = reg & (LPA_100FULL | LPA_10FULL) ? ++ 1 : 0; ++ } else { ++ /* no auto neg, just read duplex config */ ++ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; ++ } ++ ++ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", ++ dev->name, (duplex) ? "full" : "half"); ++ ++ if (duplex) { ++ /* full duplex */ ++ sp->eth_regs->mac_control = ++ (sp->eth_regs->mac_control | ++ MAC_CONTROL_F) & ~MAC_CONTROL_DRO; ++ } else { ++ /* half duplex */ ++ sp->eth_regs->mac_control = ++ (sp->eth_regs->mac_control | ++ MAC_CONTROL_DRO) & ~MAC_CONTROL_F; ++ } ++ } else { ++ /* no link */ ++ sp->link = 0; ++ } ++ sp->phy_data = phy_data; ++ } ++} ++ ++static int ar231x_reset_reg(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ unsigned int flags; ++ ++ sp->cfg->reset_set(sp->cfg->reset_mac); ++ mdelay(10); ++ sp->cfg->reset_clear(sp->cfg->reset_mac); ++ mdelay(10); ++ sp->cfg->reset_set(sp->cfg->reset_phy); ++ mdelay(10); ++ sp->cfg->reset_clear(sp->cfg->reset_phy); ++ mdelay(10); ++ ++ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); ++ mdelay(10); ++ sp->dma_regs->bus_mode = ++ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); ++ ++ /* enable interrupts */ ++ sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS | ++ DMA_STATUS_RI | DMA_STATUS_TI | ++ DMA_STATUS_FBE; ++ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); ++ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); ++ sp->dma_regs->control = ++ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); ++ ++ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); ++ sp->eth_regs->vlan_tag = (0x8100); ++ ++ /* Enable Ethernet Interface */ ++ flags = (MAC_CONTROL_TE | /* transmit enable */ ++ MAC_CONTROL_PM | /* pass mcast */ ++ MAC_CONTROL_F | /* full duplex */ ++ MAC_CONTROL_HBD); /* heart beat disabled */ ++ ++ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ ++ flags |= MAC_CONTROL_PR; ++ } ++ sp->eth_regs->mac_control = flags; ++ ++ /* Set all Ethernet station address registers to their initial values */ ++ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF); ++ ++ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ return 0; ++} ++ ++static int ar231x_init(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ecode = 0; ++ ++ /* Allocate descriptors */ ++ if (ar231x_allocate_descriptors(dev)) { ++ printk("%s: %s: ar231x_allocate_descriptors failed\n", ++ dev->name, __func__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ ++ /* Get the memory for the skb rings */ ++ if (sp->rx_skb == NULL) { ++ sp->rx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->rx_skb)) { ++ printk("%s: %s: rx_skb kmalloc failed\n", ++ dev->name, __func__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ if (sp->tx_skb == NULL) { ++ sp->tx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->tx_skb)) { ++ printk("%s: %s: tx_skb kmalloc failed\n", ++ dev->name, __func__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ /** ++ * Set tx_csm before we start receiving interrupts, otherwise ++ * the interrupt handler might think it is supposed to process ++ * tx ints before we are up and running, which may cause a null ++ * pointer access in the int handler. ++ */ ++ sp->rx_skbprd = 0; ++ sp->cur_rx = 0; ++ sp->tx_prd = 0; ++ sp->tx_csm = 0; ++ ++ /* Zero the stats before starting the interface */ ++ memset(&dev->stats, 0, sizeof(dev->stats)); ++ ++ /** ++ * We load the ring here as there seem to be no way to tell the ++ * firmware to wipe the ring without re-initializing it. ++ */ ++ ar231x_load_rx_ring(dev, RX_RING_SIZE); ++ ++ /* Init hardware */ ++ ar231x_reset_reg(dev); ++ ++ /* Get the IRQ */ ++ ecode = request_irq(dev->irq, &ar231x_interrupt, IRQF_DISABLED, ++ dev->name, dev); ++ if (ecode) { ++ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", ++ dev->name, __func__, dev->irq); ++ goto init_error; ++ } ++ ++ tasklet_enable(&sp->rx_tasklet); ++ ++ return 0; ++ ++init_error: ++ ar231x_init_cleanup(dev); ++ return ecode; ++} ++ ++/** ++ * Load the rx ring. ++ * ++ * Loading rings is safe without holding the spin lock since this is ++ * done only before the device is enabled, thus no interrupts are ++ * generated and by the interrupt handler/tasklet handler. ++ */ ++static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ short i, idx; ++ ++ idx = sp->rx_skbprd; ++ ++ for (i = 0; i < nr_bufs; i++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *rd; ++ ++ if (sp->rx_skb[idx]) ++ break; ++ ++ skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE); ++ if (!skb) { ++ printk("\n\n\n\n %s: No memory in system\n\n\n\n", ++ __func__); ++ break; ++ } ++ ++ /* Make sure IP header starts on a fresh cache line */ ++ skb->dev = dev; ++ sp->rx_skb[idx] = skb; ++ ++ rd = (ar231x_descr_t *)&sp->rx_ring[idx]; ++ ++ /* initialize dma descriptor */ ++ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rd->addr = virt_to_phys(skb->data); ++ rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]); ++ rd->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ if (i) ++ sp->rx_skbprd = idx; ++} ++ ++#define AR2313_MAX_PKTS_PER_CALL 64 ++ ++static int ar231x_rx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb, *skb_new; ++ ar231x_descr_t *rxdesc; ++ unsigned int status; ++ u32 idx; ++ int pkts = 0; ++ int rval; ++ ++ idx = sp->cur_rx; ++ ++ /* process at most the entire ring and then wait for another int */ ++ while (1) { ++ rxdesc = &sp->rx_ring[idx]; ++ status = rxdesc->status; ++ ++ if (status & DMA_RX_OWN) { ++ /* SiByte owns descriptor or descr not yet filled in */ ++ rval = 0; ++ break; ++ } ++ ++ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { ++ rval = 1; ++ break; ++ } ++ ++ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { ++ dev->stats.rx_errors++; ++ dev->stats.rx_dropped++; ++ ++ /* add statistics counters */ ++ if (status & DMA_RX_ERR_CRC) ++ dev->stats.rx_crc_errors++; ++ if (status & DMA_RX_ERR_COL) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_LENGTH) ++ dev->stats.rx_length_errors++; ++ if (status & DMA_RX_ERR_RUNT) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_DESC) ++ dev->stats.rx_over_errors++; ++ ++ } else { ++ /* alloc new buffer. */ ++ skb_new = netdev_alloc_skb_ip_align(dev, ++ AR2313_BUFSIZE); ++ if (skb_new != NULL) { ++ skb = sp->rx_skb[idx]; ++ /* set skb */ ++ skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) & ++ 0x3fff) - CRC_LEN); ++ ++ dev->stats.rx_bytes += skb->len; ++ skb->protocol = eth_type_trans(skb, dev); ++ /* pass the packet to upper layers */ ++ netif_rx(skb); ++ ++ skb_new->dev = dev; ++ /* reset descriptor's curr_addr */ ++ rxdesc->addr = virt_to_phys(skb_new->data); ++ ++ dev->stats.rx_packets++; ++ sp->rx_skb[idx] = skb_new; ++ } else { ++ dev->stats.rx_dropped++; ++ } ++ } ++ ++ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rxdesc->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ sp->cur_rx = idx; ++ ++ return rval; ++} ++ ++static void ar231x_tx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u32 idx; ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ unsigned int status = 0; ++ ++ idx = sp->tx_csm; ++ ++ while (idx != sp->tx_prd) { ++ txdesc = &sp->tx_ring[idx]; ++ status = txdesc->status; ++ ++ if (status & DMA_TX_OWN) { ++ /* ar231x dma still owns descr */ ++ break; ++ } ++ /* done with this descriptor */ ++ dma_unmap_single(NULL, txdesc->addr, ++ txdesc->devcs & DMA_TX1_BSIZE_MASK, ++ DMA_TO_DEVICE); ++ txdesc->status = 0; ++ ++ if (status & DMA_TX_ERROR) { ++ dev->stats.tx_errors++; ++ dev->stats.tx_dropped++; ++ if (status & DMA_TX_ERR_UNDER) ++ dev->stats.tx_fifo_errors++; ++ if (status & DMA_TX_ERR_HB) ++ dev->stats.tx_heartbeat_errors++; ++ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) ++ dev->stats.tx_carrier_errors++; ++ if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL | ++ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) ++ dev->stats.tx_aborted_errors++; ++ } else { ++ /* transmit OK */ ++ dev->stats.tx_packets++; ++ } ++ ++ skb = sp->tx_skb[idx]; ++ sp->tx_skb[idx] = NULL; ++ idx = DSC_NEXT(idx); ++ dev->stats.tx_bytes += skb->len; ++ dev_kfree_skb_irq(skb); ++ } ++ ++ sp->tx_csm = idx; ++} ++ ++static void rx_tasklet_func(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ if (sp->unloading) ++ return; ++ ++ if (ar231x_rx_int(dev)) { ++ tasklet_hi_schedule(&sp->rx_tasklet); ++ } else { ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sp->lock, flags); ++ sp->dma_regs->intr_ena |= DMA_STATUS_RI; ++ spin_unlock_irqrestore(&sp->lock, flags); ++ } ++} ++ ++static void rx_schedule(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; ++ ++ tasklet_hi_schedule(&sp->rx_tasklet); ++} ++ ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int status, enabled; ++ ++ /* clear interrupt */ ++ /* Don't clear RI bit if currently disabled */ ++ status = sp->dma_regs->status; ++ enabled = sp->dma_regs->intr_ena; ++ sp->dma_regs->status = status & enabled; ++ ++ if (status & DMA_STATUS_NIS) { ++ /* normal status */ ++ /** ++ * Don't schedule rx processing if interrupt ++ * is already disabled. ++ */ ++ if (status & enabled & DMA_STATUS_RI) { ++ /* receive interrupt */ ++ rx_schedule(dev); ++ } ++ if (status & DMA_STATUS_TI) { ++ /* transmit interrupt */ ++ ar231x_tx_int(dev); ++ } ++ } ++ ++ /* abnormal status */ ++ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) ++ ar231x_restart(dev); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ar231x_open(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ ++ /* reset the hardware, in case the MAC address changed */ ++ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF); ++ ++ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ dev->mtu = 1500; ++ netif_start_queue(dev); ++ ++ sp->eth_regs->mac_control |= MAC_CONTROL_RE; ++ ++ return 0; ++} ++ ++static void ar231x_tx_timeout(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sp->lock, flags); ++ ar231x_restart(dev); ++ spin_unlock_irqrestore(&sp->lock, flags); ++} ++ ++static void ar231x_halt(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int j; ++ ++ tasklet_disable(&sp->rx_tasklet); ++ ++ /* kill the MAC */ ++ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ ++ MAC_CONTROL_TE); /* disable Transmits */ ++ /* stop dma */ ++ sp->dma_regs->control = 0; ++ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; ++ ++ /* place phy and MAC in reset */ ++ sp->cfg->reset_set(sp->cfg->reset_mac); ++ sp->cfg->reset_set(sp->cfg->reset_phy); ++ ++ /* free buffers on tx ring */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ ++ txdesc = &sp->tx_ring[j]; ++ txdesc->descr = 0; ++ ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ dev_kfree_skb(skb); ++ sp->tx_skb[j] = NULL; ++ } ++ } ++} ++ ++/** ++ * close should do nothing. Here's why. It's called when ++ * 'ifconfig bond0 down' is run. If it calls free_irq then ++ * the irq is gone forever ! When bond0 is made 'up' again, ++ * the ar231x_open () does not call request_irq (). Worse, ++ * the call to ar231x_halt() generates a WDOG reset due to ++ * the write to reset register and the box reboots. ++ * Commenting this out is good since it allows the ++ * system to resume when bond0 is made up again. ++ */ ++static int ar231x_close(struct net_device *dev) ++{ ++#if 0 ++ /* Disable interrupts */ ++ disable_irq(dev->irq); ++ ++ /** ++ * Without (or before) releasing irq and stopping hardware, this ++ * is an absolute non-sense, by the way. It will be reset instantly ++ * by the first irq. ++ */ ++ netif_stop_queue(dev); ++ ++ /* stop the MAC and DMA engines */ ++ ar231x_halt(dev); ++ ++ /* release the interrupt */ ++ free_irq(dev->irq, dev); ++ ++#endif ++ return 0; ++} ++ ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ar231x_descr_t *td; ++ u32 idx; ++ ++ idx = sp->tx_prd; ++ td = &sp->tx_ring[idx]; ++ ++ if (td->status & DMA_TX_OWN) { ++ /* free skbuf and lie to the caller that we sent it out */ ++ dev->stats.tx_dropped++; ++ dev_kfree_skb(skb); ++ ++ /* restart transmitter in case locked */ ++ sp->dma_regs->xmt_poll = 0; ++ return 0; ++ } ++ ++ /* Setup the transmit descriptor. */ ++ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | ++ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); ++ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++ td->status = DMA_TX_OWN; ++ ++ /* kick transmitter last */ ++ sp->dma_regs->xmt_poll = 0; ++ ++ sp->tx_skb[idx] = skb; ++ idx = DSC_NEXT(idx); ++ sp->tx_prd = idx; ++ ++ return 0; ++} ++ ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ switch (cmd) { ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ return phy_mii_ioctl(sp->phy_dev, ifr, cmd); ++ ++ default: ++ break; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++static void ar231x_adjust_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int mc; ++ ++ if (!sp->phy_dev->link) ++ return; ++ ++ if (sp->phy_dev->duplex != sp->oldduplex) { ++ mc = readl(&sp->eth_regs->mac_control); ++ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); ++ if (sp->phy_dev->duplex) ++ mc |= MAC_CONTROL_F; ++ else ++ mc |= MAC_CONTROL_DRO; ++ writel(mc, &sp->eth_regs->mac_control); ++ sp->oldduplex = sp->phy_dev->duplex; ++ } ++} ++ ++#define MII_ADDR(phy, reg) \ ++ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) ++ ++static int ++ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile MII *ethernet = sp->phy_regs; ++ ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); ++ while (ethernet->mii_addr & MII_ADDR_BUSY) ++ ; ++ return ethernet->mii_data >> MII_DATA_SHIFT; ++} ++ ++static int ++ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile MII *ethernet = sp->phy_regs; ++ ++ while (ethernet->mii_addr & MII_ADDR_BUSY) ++ ; ++ ethernet->mii_data = value << MII_DATA_SHIFT; ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_reset(struct mii_bus *bus) ++{ ++ struct net_device *const dev = bus->priv; ++ ++ ar231x_reset_reg(dev); ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_probe(struct net_device *dev) ++{ ++ struct ar231x_private *const sp = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ int phy_addr; ++ ++ /* find the first (lowest address) PHY on the current MAC's MII bus */ ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) ++ if (sp->mii_bus->phy_map[phy_addr]) { ++ phydev = sp->mii_bus->phy_map[phy_addr]; ++ sp->phy = phy_addr; ++ break; /* break out with first one found */ ++ } ++ ++ if (!phydev) { ++ printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name); ++ return -1; ++ } ++ ++ /* now we are supposed to have a proper phydev, to attach to... */ ++ BUG_ON(!phydev); ++ BUG_ON(phydev->attached_dev); ++ ++ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, ++ PHY_INTERFACE_MODE_MII); ++ ++ if (IS_ERR(phydev)) { ++ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); ++ return PTR_ERR(phydev); ++ } ++ ++ /* mask with MAC supported features */ ++ phydev->supported &= (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_Autoneg ++ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ ++ | SUPPORTED_MII ++ | SUPPORTED_TP); ++ ++ phydev->advertising = phydev->supported; ++ ++ sp->oldduplex = -1; ++ sp->phy_dev = phydev; ++ ++ printk(KERN_INFO "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", ++ dev->name, phydev->drv->name, dev_name(&phydev->dev)); ++ ++ return 0; ++} ++ +--- /dev/null ++++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h +@@ -0,0 +1,288 @@ ++/* ++ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef _AR2313_H_ ++#define _AR2313_H_ ++ ++#include ++#include ++#include ++#include ++ ++/* probe link timer - 5 secs */ ++#define LINK_TIMER (5*HZ) ++ ++#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) ++#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) ++#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) ++ ++#define AR2313_TX_TIMEOUT (HZ/4) ++ ++/* Rings */ ++#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) ++#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) ++ ++#define AR2313_MBGET 2 ++#define AR2313_MBSET 3 ++#define AR2313_PCI_RECONFIG 4 ++#define AR2313_PCI_DUMP 5 ++#define AR2313_TEST_PANIC 6 ++#define AR2313_TEST_NULLPTR 7 ++#define AR2313_READ_DATA 8 ++#define AR2313_WRITE_DATA 9 ++#define AR2313_GET_VERSION 10 ++#define AR2313_TEST_HANG 11 ++#define AR2313_SYNC 12 ++ ++#define DMA_RX_ERR_CRC BIT(1) ++#define DMA_RX_ERR_DRIB BIT(2) ++#define DMA_RX_ERR_MII BIT(3) ++#define DMA_RX_EV2 BIT(5) ++#define DMA_RX_ERR_COL BIT(6) ++#define DMA_RX_LONG BIT(7) ++#define DMA_RX_LS BIT(8) /* last descriptor */ ++#define DMA_RX_FS BIT(9) /* first descriptor */ ++#define DMA_RX_MF BIT(10) /* multicast frame */ ++#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ ++#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ ++#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ ++#define DMA_RX_ERROR BIT(15) /* error summary */ ++#define DMA_RX_LEN_MASK 0x3fff0000 ++#define DMA_RX_LEN_SHIFT 16 ++#define DMA_RX_FILT BIT(30) ++#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ ++ ++#define DMA_RX1_BSIZE_MASK 0x000007ff ++#define DMA_RX1_BSIZE_SHIFT 0 ++#define DMA_RX1_CHAINED BIT(24) ++#define DMA_RX1_RER BIT(25) ++ ++#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ ++#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ ++#define DMA_TX_COL_MASK 0x78 ++#define DMA_TX_COL_SHIFT 3 ++#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ ++#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ ++#define DMA_TX_ERR_LATE BIT(9) /* late collision */ ++#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ ++#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ ++#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ ++#define DMA_TX_ERROR BIT(15) /* frame aborted */ ++#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ ++ ++#define DMA_TX1_BSIZE_MASK 0x000007ff ++#define DMA_TX1_BSIZE_SHIFT 0 ++#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ ++#define DMA_TX1_TER BIT(25) /* transmit end of ring */ ++#define DMA_TX1_FS BIT(29) /* first segment */ ++#define DMA_TX1_LS BIT(30) /* last segment */ ++#define DMA_TX1_IC BIT(31) /* interrupt on completion */ ++ ++#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ ++ ++#define MAC_CONTROL_RE BIT(2) /* receive enable */ ++#define MAC_CONTROL_TE BIT(3) /* transmit enable */ ++#define MAC_CONTROL_DC BIT(5) /* Deferral check */ ++#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ ++#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ ++#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ ++#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ ++#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ ++#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ ++#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ ++#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ ++#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ ++#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */ ++#define MAC_CONTROL_PM BIT(19) /* pass multicast */ ++#define MAC_CONTROL_F BIT(20) /* full-duplex */ ++#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ ++#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ ++#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ ++#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */ ++ ++#define MII_ADDR_BUSY BIT(0) ++#define MII_ADDR_WRITE BIT(1) ++#define MII_ADDR_REG_SHIFT 6 ++#define MII_ADDR_PHY_SHIFT 11 ++#define MII_DATA_SHIFT 0 ++ ++#define FLOW_CONTROL_FCE BIT(1) ++ ++#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ ++#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ ++#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ ++#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ ++ ++#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ ++#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ ++#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ ++#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ ++#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ ++#define DMA_STATUS_RI BIT(6) /* receive interrupt */ ++#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ ++#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ ++#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ ++#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ ++#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ ++#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ ++#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ ++#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ ++#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ ++#define DMA_STATUS_EB_SHIFT 23 /* error bits */ ++ ++#define DMA_CONTROL_SR BIT(1) /* start receive */ ++#define DMA_CONTROL_ST BIT(13) /* start transmit */ ++#define DMA_CONTROL_SF BIT(21) /* store and forward */ ++ ++typedef struct { ++ volatile unsigned int status; /* OWN, Device control and status. */ ++ volatile unsigned int devcs; /* pkt Control bits + Length */ ++ volatile unsigned int addr; /* Current Address. */ ++ volatile unsigned int descr; /* Next descriptor in chain. */ ++} ar231x_descr_t; ++ ++/** ++ * New Combo structure for Both Eth0 AND eth1 ++ * ++ * Don't directly access MII related regs since phy chip could be actually ++ * connected to another ethernet block. ++ */ ++typedef struct { ++ volatile unsigned int mac_control; /* 0x00 */ ++ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ ++ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ ++ volatile unsigned int __mii_addr; /* 0x14 */ ++ volatile unsigned int __mii_data; /* 0x18 */ ++ volatile unsigned int flow_control; /* 0x1c */ ++ volatile unsigned int vlan_tag; /* 0x20 */ ++ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ ++ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ ++} ETHERNET_STRUCT; ++ ++typedef struct { ++ volatile unsigned int mii_addr; ++ volatile unsigned int mii_data; ++} MII; ++ ++/******************************************************************** ++ * Interrupt controller ++ ********************************************************************/ ++ ++typedef struct { ++ volatile unsigned int wdog_control; /* 0x08 */ ++ volatile unsigned int wdog_timer; /* 0x0c */ ++ volatile unsigned int misc_status; /* 0x10 */ ++ volatile unsigned int misc_mask; /* 0x14 */ ++ volatile unsigned int global_status; /* 0x18 */ ++ volatile unsigned int reserved; /* 0x1c */ ++ volatile unsigned int reset_control; /* 0x20 */ ++} INTERRUPT; ++ ++/******************************************************************** ++ * DMA controller ++ ********************************************************************/ ++typedef struct { ++ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ ++ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ ++ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ ++ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ ++ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ ++ volatile unsigned int status; /* 0x14 (CSR5) */ ++ volatile unsigned int control; /* 0x18 (CSR6) */ ++ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ ++ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ ++ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ ++ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ ++ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ ++} DMA; ++ ++/** ++ * Struct private for the Sibyte. ++ * ++ * Elements are grouped so variables used by the tx handling goes ++ * together, and will go into the same cache lines etc. in order to ++ * avoid cache line contention between the rx and tx handling on SMP. ++ * ++ * Frequently accessed variables are put at the beginning of the ++ * struct to help the compiler generate better/shorter code. ++ */ ++struct ar231x_private { ++ struct net_device *dev; ++ int version; ++ u32 mb[2]; ++ ++ volatile MII *phy_regs; ++ volatile ETHERNET_STRUCT *eth_regs; ++ volatile DMA *dma_regs; ++ struct ar231x_eth *cfg; ++ ++ spinlock_t lock; /* Serialise access to device */ ++ ++ /* RX and TX descriptors, must be adjacent */ ++ ar231x_descr_t *rx_ring; ++ ar231x_descr_t *tx_ring; ++ ++ struct sk_buff **rx_skb; ++ struct sk_buff **tx_skb; ++ ++ /* RX elements */ ++ u32 rx_skbprd; ++ u32 cur_rx; ++ ++ /* TX elements */ ++ u32 tx_prd; ++ u32 tx_csm; ++ ++ /* Misc elements */ ++ char name[48]; ++ struct { ++ u32 address; ++ u32 length; ++ char *mapping; ++ } desc; ++ ++ struct timer_list link_timer; ++ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ ++ unsigned short mac; ++ unsigned short link; /* 0 - link down, 1 - link up */ ++ u16 phy_data; ++ ++ struct tasklet_struct rx_tasklet; ++ int unloading; ++ ++ struct phy_device *phy_dev; ++ struct mii_bus *mii_bus; ++ int oldduplex; ++}; ++ ++/* Prototypes */ ++static int ar231x_init(struct net_device *dev); ++#ifdef TX_TIMEOUT ++static void ar231x_tx_timeout(struct net_device *dev); ++#endif ++static int ar231x_restart(struct net_device *dev); ++static void ar231x_load_rx_ring(struct net_device *dev, int bufs); ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id); ++static int ar231x_open(struct net_device *dev); ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); ++static int ar231x_close(struct net_device *dev); ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); ++static void ar231x_init_cleanup(struct net_device *dev); ++static int ar231x_setup_timer(struct net_device *dev); ++static void ar231x_link_timer_fn(unsigned long data); ++static void ar231x_check_link(struct net_device *dev); ++ ++#endif /* _AR2313_H_ */ +--- a/arch/mips/ath25/ar2315_regs.h ++++ b/arch/mips/ath25/ar2315_regs.h +@@ -57,6 +57,9 @@ + #define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */ + #define AR2315_PCI_EXT_SIZE 0x40000000 + ++/* MII registers offset inside Ethernet MMR region */ ++#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14) ++ + /* + * Configuration registers + */ +--- a/arch/mips/ath25/ar5312_regs.h ++++ b/arch/mips/ath25/ar5312_regs.h +@@ -64,6 +64,10 @@ + #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ + #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ + ++/* MII registers offset inside Ethernet MMR region */ ++#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14) ++#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14) ++ + /* Reset/Timer Block Address Map */ + #define AR5312_TIMER 0x0000 /* countdown timer */ + #define AR5312_RELOAD 0x0004 /* timer reload value */ +--- a/arch/mips/ath25/ar2315.c ++++ b/arch/mips/ath25/ar2315.c +@@ -136,6 +136,8 @@ static void ar2315_irq_dispatch(void) + + if (pending & CAUSEF_IP3) + do_IRQ(AR2315_IRQ_WLAN0); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR2315_IRQ_ENET0); + #ifdef CONFIG_PCI_AR2315 + else if (pending & CAUSEF_IP5) + do_IRQ(AR2315_IRQ_LCBUS_PCI); +@@ -169,6 +171,29 @@ void __init ar2315_arch_init_irq(void) + ar2315_misc_irq_domain = domain; + } + ++static void ar2315_device_reset_set(u32 mask) ++{ ++ u32 val; ++ ++ val = ar2315_rst_reg_read(AR2315_RESET); ++ ar2315_rst_reg_write(AR2315_RESET, val | mask); ++} ++ ++static void ar2315_device_reset_clear(u32 mask) ++{ ++ u32 val; ++ ++ val = ar2315_rst_reg_read(AR2315_RESET); ++ ar2315_rst_reg_write(AR2315_RESET, val & ~mask); ++} ++ ++static struct ar231x_eth ar2315_eth_data = { ++ .reset_set = ar2315_device_reset_set, ++ .reset_clear = ar2315_device_reset_clear, ++ .reset_mac = AR2315_RESET_ENET0, ++ .reset_phy = AR2315_RESET_EPHY0, ++}; ++ + static struct resource ar2315_gpio_res[] = { + { + .name = "ar2315-gpio", +@@ -205,6 +230,11 @@ void __init ar2315_init_devices(void) + ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; + platform_device_register(&ar2315_gpio); + ++ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac; ++ ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii", ++ AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0, ++ &ar2315_eth_data); ++ + ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0); + } + +--- a/arch/mips/ath25/ar5312.c ++++ b/arch/mips/ath25/ar5312.c +@@ -132,6 +132,10 @@ static void ar5312_irq_dispatch(void) + + if (pending & CAUSEF_IP2) + do_IRQ(AR5312_IRQ_WLAN0); ++ else if (pending & CAUSEF_IP3) ++ do_IRQ(AR5312_IRQ_ENET0); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR5312_IRQ_ENET1); + else if (pending & CAUSEF_IP5) + do_IRQ(AR5312_IRQ_WLAN1); + else if (pending & CAUSEF_IP6) +@@ -163,6 +167,36 @@ void __init ar5312_arch_init_irq(void) + ar5312_misc_irq_domain = domain; + } + ++static void ar5312_device_reset_set(u32 mask) ++{ ++ u32 val; ++ ++ val = ar5312_rst_reg_read(AR5312_RESET); ++ ar5312_rst_reg_write(AR5312_RESET, val | mask); ++} ++ ++static void ar5312_device_reset_clear(u32 mask) ++{ ++ u32 val; ++ ++ val = ar5312_rst_reg_read(AR5312_RESET); ++ ar5312_rst_reg_write(AR5312_RESET, val & ~mask); ++} ++ ++static struct ar231x_eth ar5312_eth0_data = { ++ .reset_set = ar5312_device_reset_set, ++ .reset_clear = ar5312_device_reset_clear, ++ .reset_mac = AR5312_RESET_ENET0, ++ .reset_phy = AR5312_RESET_EPHY0, ++}; ++ ++static struct ar231x_eth ar5312_eth1_data = { ++ .reset_set = ar5312_device_reset_set, ++ .reset_clear = ar5312_device_reset_clear, ++ .reset_mac = AR5312_RESET_ENET1, ++ .reset_phy = AR5312_RESET_EPHY1, ++}; ++ + static struct physmap_flash_data ar5312_flash_data = { + .width = 2, + }; +@@ -243,6 +277,7 @@ static void __init ar5312_flash_init(voi + void __init ar5312_init_devices(void) + { + struct ath25_boarddata *config; ++ u8 *c; + + ar5312_flash_init(); + +@@ -266,8 +301,30 @@ void __init ar5312_init_devices(void) + + platform_device_register(&ar5312_gpio); + ++ /* Fix up MAC addresses if necessary */ ++ if (is_broadcast_ether_addr(config->enet0_mac)) ++ ether_addr_copy(config->enet0_mac, config->enet1_mac); ++ ++ /* If ENET0 and ENET1 have the same mac address, ++ * increment the one from ENET1 */ ++ if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) { ++ c = config->enet1_mac + 5; ++ while ((c >= config->enet1_mac) && !(++(*c))) ++ c--; ++ } ++ + switch (ath25_soc) { + case ATH25_SOC_AR5312: ++ ar5312_eth0_data.macaddr = config->enet0_mac; ++ ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii", ++ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0, ++ &ar5312_eth0_data); ++ ++ ar5312_eth1_data.macaddr = config->enet1_mac; ++ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii", ++ AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1, ++ &ar5312_eth1_data); ++ + if (!ath25_board.radio) + return; + +@@ -276,8 +333,18 @@ void __init ar5312_init_devices(void) + + ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0); + break; ++ /* ++ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC ++ * of ENET1. Atheros calls it 'twisted' for a reason :) ++ */ + case ATH25_SOC_AR2312: + case ATH25_SOC_AR2313: ++ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; ++ ar5312_eth1_data.macaddr = config->enet0_mac; ++ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii", ++ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1, ++ &ar5312_eth1_data); ++ + if (!ath25_board.radio) + return; + break; +--- a/arch/mips/ath25/devices.h ++++ b/arch/mips/ath25/devices.h +@@ -32,6 +32,8 @@ extern struct ar231x_board_config ath25_ + extern void (*ath25_irq_dispatch)(void); + + int ath25_find_config(phys_addr_t offset, unsigned long size); ++int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base, ++ int irq, void *pdata); + void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk); + int ath25_add_wmac(int nr, u32 base, int irq); + +--- a/arch/mips/ath25/devices.c ++++ b/arch/mips/ath25/devices.c +@@ -12,6 +12,51 @@ + struct ar231x_board_config ath25_board; + enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN; + ++static struct resource ath25_eth0_res[] = { ++ { ++ .name = "eth0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth0_mii", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ath25_eth1_res[] = { ++ { ++ .name = "eth1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth1_mii", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device ath25_eth[] = { ++ { ++ .id = 0, ++ .name = "ar231x-eth", ++ .resource = ath25_eth0_res, ++ .num_resources = ARRAY_SIZE(ath25_eth0_res) ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-eth", ++ .resource = ath25_eth1_res, ++ .num_resources = ARRAY_SIZE(ath25_eth1_res) ++ } ++}; ++ + static struct resource ath25_wmac0_res[] = { + { + .name = "wmac0_membase", +@@ -70,6 +115,25 @@ const char *get_system_type(void) + return soc_type_strings[ath25_soc]; + } + ++int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name, ++ u32 mii_base, int irq, void *pdata) ++{ ++ struct resource *res; ++ ++ ath25_eth[nr].dev.platform_data = pdata; ++ res = &ath25_eth[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x2000 - 1; ++ res++; ++ res->name = mii_name; ++ res->start = mii_base; ++ res->end = mii_base + 8 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ath25_eth[nr]); ++} ++ + void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk) + { + struct uart_port s; +--- a/arch/mips/include/asm/mach-ath25/ath25_platform.h ++++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h +@@ -70,4 +70,15 @@ struct ar231x_board_config { + const char *radio; + }; + ++/* ++ * Platform device information for the Ethernet MAC ++ */ ++struct ar231x_eth { ++ void (*reset_set)(u32); ++ void (*reset_clear)(u32); ++ u32 reset_mac; ++ u32 reset_phy; ++ char *macaddr; ++}; ++ + #endif /* __ASM_MACH_ATH25_PLATFORM_H */ diff --git a/target/linux/ath25/patches-3.18/120-spiflash.patch b/target/linux/ath25/patches-3.18/120-spiflash.patch new file mode 100644 index 0000000..7d88ee2 --- /dev/null +++ b/target/linux/ath25/patches-3.18/120-spiflash.patch @@ -0,0 +1,634 @@ +--- a/drivers/mtd/devices/Kconfig ++++ b/drivers/mtd/devices/Kconfig +@@ -120,6 +120,10 @@ config MTD_BCM47XXSFLASH + registered by bcma as platform devices. This enables driver for + serial flash memories (only read-only mode is implemented). + ++config MTD_AR2315 ++ tristate "Atheros AR2315+ SPI Flash support" ++ depends on SOC_AR2315 ++ + config MTD_SLRAM + tristate "Uncached system RAM" + help +--- a/drivers/mtd/devices/Makefile ++++ b/drivers/mtd/devices/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataf + obj-$(CONFIG_MTD_M25P80) += m25p80.o + obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o + obj-$(CONFIG_MTD_SST25L) += sst25l.o ++obj-$(CONFIG_MTD_AR2315) += ar2315.o + obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o + obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o + +--- /dev/null ++++ b/drivers/mtd/devices/ar2315.c +@@ -0,0 +1,459 @@ ++ ++/* ++ * MTD driver for the SPI Flash Memory support on Atheros AR2315 ++ * ++ * Copyright (c) 2005-2006 Atheros Communications Inc. ++ * Copyright (C) 2006-2007 FON Technology, SL. ++ * Copyright (C) 2006-2007 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * Copyright (C) 2012 Alexandros C. Couloumbis ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ar2315_spiflash.h" ++ ++#define DRIVER_NAME "ar2315-spiflash" ++ ++#define busy_wait(_priv, _condition, _wait) do { \ ++ while (_condition) { \ ++ if (_wait > 1) \ ++ msleep(_wait); \ ++ else if ((_wait == 1) && need_resched()) \ ++ schedule(); \ ++ else \ ++ udelay(1); \ ++ } \ ++} while (0) ++ ++enum { ++ FLASH_NONE, ++ FLASH_1MB, ++ FLASH_2MB, ++ FLASH_4MB, ++ FLASH_8MB, ++ FLASH_16MB, ++}; ++ ++/* Flash configuration table */ ++struct flashconfig { ++ u32 byte_cnt; ++ u32 sector_cnt; ++ u32 sector_size; ++}; ++ ++static const struct flashconfig flashconfig_tbl[] = { ++ [FLASH_NONE] = { 0, 0, 0}, ++ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, ++ STM_1MB_SECTOR_SIZE}, ++ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, ++ STM_2MB_SECTOR_SIZE}, ++ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, ++ STM_4MB_SECTOR_SIZE}, ++ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, ++ STM_8MB_SECTOR_SIZE}, ++ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, ++ STM_16MB_SECTOR_SIZE} ++}; ++ ++/* Mapping of generic opcodes to STM serial flash opcodes */ ++enum { ++ SPI_WRITE_ENABLE, ++ SPI_WRITE_DISABLE, ++ SPI_RD_STATUS, ++ SPI_WR_STATUS, ++ SPI_RD_DATA, ++ SPI_FAST_RD_DATA, ++ SPI_PAGE_PROGRAM, ++ SPI_SECTOR_ERASE, ++ SPI_BULK_ERASE, ++ SPI_DEEP_PWRDOWN, ++ SPI_RD_SIG, ++}; ++ ++struct opcodes { ++ __u16 code; ++ __s8 tx_cnt; ++ __s8 rx_cnt; ++}; ++ ++static const struct opcodes stm_opcodes[] = { ++ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, ++ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, ++ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, ++ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, ++ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, ++ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, ++ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, ++ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, ++ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, ++ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, ++ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, ++}; ++ ++/* Driver private data structure */ ++struct spiflash_priv { ++ struct mtd_info mtd; ++ void __iomem *readaddr; /* memory mapped data for read */ ++ void __iomem *mmraddr; /* memory mapped register space */ ++ struct mutex lock; /* serialize registers access */ ++}; ++ ++#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) ++ ++enum { ++ FL_READY, ++ FL_READING, ++ FL_ERASING, ++ FL_WRITING ++}; ++ ++/*****************************************************************************/ ++ ++static u32 ++spiflash_read_reg(struct spiflash_priv *priv, int reg) ++{ ++ return ioread32(priv->mmraddr + reg); ++} ++ ++static void ++spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) ++{ ++ iowrite32(data, priv->mmraddr + reg); ++} ++ ++static u32 ++spiflash_wait_busy(struct spiflash_priv *priv) ++{ ++ u32 reg; ++ ++ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & ++ SPI_CTL_BUSY, 0); ++ return reg; ++} ++ ++static u32 ++spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr) ++{ ++ const struct opcodes *op; ++ u32 reg, mask; ++ ++ op = &stm_opcodes[opcode]; ++ reg = spiflash_wait_busy(priv); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, ++ ((u32)op->code) | (addr << 8)); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); ++ ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ spiflash_wait_busy(priv); ++ ++ if (!op->rx_cnt) ++ return 0; ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); ++ ++ switch (op->rx_cnt) { ++ case 1: ++ mask = 0x000000ff; ++ break; ++ case 2: ++ mask = 0x0000ffff; ++ break; ++ case 3: ++ mask = 0x00ffffff; ++ break; ++ default: ++ mask = 0xffffffff; ++ break; ++ } ++ reg &= mask; ++ ++ return reg; ++} ++ ++/* ++ * Probe SPI flash device ++ * Function returns 0 for failure. ++ * and flashconfig_tbl array index for success. ++ */ ++static int ++spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv) ++{ ++ u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); ++ int flash_size; ++ ++ switch (sig) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = FLASH_1MB; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = FLASH_2MB; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = FLASH_4MB; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = FLASH_8MB; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = FLASH_16MB; ++ break; ++ default: ++ dev_warn(&pdev->dev, "read of flash device signature failed!\n"); ++ return 0; ++ } ++ ++ return flash_size; ++} ++ ++static void ++spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) ++{ ++ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & ++ SPI_STATUS_WIP, timeout); ++} ++ ++static int ++spiflash_erase(struct mtd_info *mtd, struct erase_info *instr) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ const struct opcodes *op; ++ u32 temp, reg; ++ ++ if (instr->addr + instr->len > mtd->size) ++ return -EINVAL; ++ ++ mutex_lock(&priv->lock); ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ reg = spiflash_wait_busy(priv); ++ ++ op = &stm_opcodes[SPI_SECTOR_ERASE]; ++ temp = ((u32)instr->addr << 8) | (u32)(op->code); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= op->tx_cnt | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 20); ++ ++ mutex_unlock(&priv->lock); ++ ++ instr->state = MTD_ERASE_DONE; ++ mtd_erase_callback(instr); ++ ++ return 0; ++} ++ ++static int ++spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, ++ u_char *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ ++ if (!len) ++ return 0; ++ ++ if (from + len > mtd->size) ++ return -EINVAL; ++ ++ *retlen = len; ++ ++ mutex_lock(&priv->lock); ++ ++ memcpy_fromio(buf, priv->readaddr + from, len); ++ ++ mutex_unlock(&priv->lock); ++ ++ return 0; ++} ++ ++static int ++spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, ++ const u8 *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u32 opcode, bytes_left; ++ ++ *retlen = 0; ++ ++ if (!len) ++ return 0; ++ ++ if (to + len > mtd->size) ++ return -EINVAL; ++ ++ bytes_left = len; ++ ++ do { ++ u32 read_len, reg, page_offset, spi_data = 0; ++ ++ read_len = min(bytes_left, sizeof(u32)); ++ ++ /* 32-bit writes cannot span across a page boundary ++ * (256 bytes). This types of writes require two page ++ * program operations to handle it correctly. The STM part ++ * will write the overflow data to the beginning of the ++ * current page as opposed to the subsequent page. ++ */ ++ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; ++ ++ if (page_offset > STM_PAGE_SIZE) ++ read_len -= (page_offset - STM_PAGE_SIZE); ++ ++ mutex_lock(&priv->lock); ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ spi_data = 0; ++ switch (read_len) { ++ case 4: ++ spi_data |= buf[3] << 24; ++ /* fall through */ ++ case 3: ++ spi_data |= buf[2] << 16; ++ /* fall through */ ++ case 2: ++ spi_data |= buf[1] << 8; ++ /* fall through */ ++ case 1: ++ spi_data |= buf[0] & 0xff; ++ break; ++ default: ++ break; ++ } ++ ++ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); ++ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | ++ (to & 0x00ffffff) << 8; ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (read_len + 4) | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 1); ++ ++ mutex_unlock(&priv->lock); ++ ++ bytes_left -= read_len; ++ to += read_len; ++ buf += read_len; ++ ++ *retlen += read_len; ++ } while (bytes_left != 0); ++ ++ return 0; ++} ++ ++#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS ++static const char * const part_probe_types[] = { ++ "cmdlinepart", "RedBoot", "MyLoader", NULL ++}; ++#endif ++ ++static int ++spiflash_probe(struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv; ++ struct mtd_info *mtd; ++ struct resource *res; ++ int index; ++ int result = 0; ++ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ mutex_init(&priv->lock); ++ mtd = &priv->mtd; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ priv->mmraddr = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(priv->mmraddr)) { ++ dev_warn(&pdev->dev, "failed to map flash MMR\n"); ++ return PTR_ERR(priv->mmraddr); ++ } ++ ++ index = spiflash_probe_chip(pdev, priv); ++ if (!index) { ++ dev_warn(&pdev->dev, "found no flash device\n"); ++ return -ENODEV; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ priv->readaddr = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(priv->readaddr)) { ++ dev_warn(&pdev->dev, "failed to map flash read mem\n"); ++ return PTR_ERR(priv->readaddr); ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ mtd->name = "spiflash"; ++ mtd->type = MTD_NORFLASH; ++ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); ++ mtd->size = flashconfig_tbl[index].byte_cnt; ++ mtd->erasesize = flashconfig_tbl[index].sector_size; ++ mtd->writesize = 1; ++ mtd->numeraseregions = 0; ++ mtd->eraseregions = NULL; ++ mtd->_erase = spiflash_erase; ++ mtd->_read = spiflash_read; ++ mtd->_write = spiflash_write; ++ mtd->owner = THIS_MODULE; ++ ++ dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10); ++ ++#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS ++ /* parse redboot partitions */ ++ ++ result = mtd_device_parse_register(mtd, part_probe_types, ++ NULL, NULL, 0); ++#endif ++ ++ return result; ++} ++ ++static int ++spiflash_remove(struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv = platform_get_drvdata(pdev); ++ ++ mtd_device_unregister(&priv->mtd); ++ ++ return 0; ++} ++ ++static struct platform_driver spiflash_driver = { ++ .driver.name = DRIVER_NAME, ++ .probe = spiflash_probe, ++ .remove = spiflash_remove, ++}; ++ ++module_platform_driver(spiflash_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("OpenWrt.org"); ++MODULE_AUTHOR("Atheros Communications Inc"); ++MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC"); ++MODULE_ALIAS("platform:" DRIVER_NAME); ++ +--- /dev/null ++++ b/drivers/mtd/devices/ar2315_spiflash.h +@@ -0,0 +1,106 @@ ++/* ++ * Atheros AR2315 SPI Flash Memory support header file. ++ * ++ * Copyright (c) 2005, Atheros Communications Inc. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef __AR2315_SPIFLASH_H ++#define __AR2315_SPIFLASH_H ++ ++#define STM_PAGE_SIZE 256 ++ ++#define SFI_WRITE_BUFFER_SIZE 4 ++#define SFI_FLASH_ADDR_MASK 0x00ffffff ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_M25P80_BYTE_COUNT 1048576 ++#define STM_M25P80_SECTOR_COUNT 16 ++#define STM_M25P80_SECTOR_SIZE 0x10000 ++ ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_M25P16_BYTE_COUNT 2097152 ++#define STM_M25P16_SECTOR_COUNT 32 ++#define STM_M25P16_SECTOR_SIZE 0x10000 ++ ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_M25P32_BYTE_COUNT 4194304 ++#define STM_M25P32_SECTOR_COUNT 64 ++#define STM_M25P32_SECTOR_SIZE 0x10000 ++ ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_M25P64_BYTE_COUNT 8388608 ++#define STM_M25P64_SECTOR_COUNT 128 ++#define STM_M25P64_SECTOR_SIZE 0x10000 ++ ++#define STM_128MBIT_SIGNATURE 0x17 ++#define STM_M25P128_BYTE_COUNT 16777216 ++#define STM_M25P128_SECTOR_COUNT 256 ++#define STM_M25P128_SECTOR_SIZE 0x10000 ++ ++#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT ++#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT ++#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE ++#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT ++#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT ++#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE ++#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT ++#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT ++#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE ++#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT ++#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT ++#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE ++#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT ++#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT ++#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE ++ ++/* ++ * ST Microelectronics Opcodes for Serial Flash ++ */ ++ ++#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ ++#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ ++#define STM_OP_RD_STATUS 0x05 /* Read Status */ ++#define STM_OP_WR_STATUS 0x01 /* Write Status */ ++#define STM_OP_RD_DATA 0x03 /* Read Data */ ++#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ ++#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ ++#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ ++#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ ++#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ ++#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ ++ ++#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ ++#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ ++#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ ++#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ ++#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ ++#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++ ++#define SPI_FLASH_CTL 0x00 ++#define SPI_FLASH_OPCODE 0x04 ++#define SPI_FLASH_DATA 0x08 ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++#define SPI_STATUS_WIP STM_STATUS_WIP ++ ++#endif +--- a/arch/mips/ath25/ar2315.c ++++ b/arch/mips/ath25/ar2315.c +@@ -220,6 +220,28 @@ static struct platform_device ar2315_gpi + .num_resources = ARRAY_SIZE(ar2315_gpio_res) + }; + ++static struct resource ar2315_spiflash_res[] = { ++ { ++ .name = "spiflash_read", ++ .flags = IORESOURCE_MEM, ++ .start = AR2315_SPI_READ_BASE, ++ .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1, ++ }, ++ { ++ .name = "spiflash_mmr", ++ .flags = IORESOURCE_MEM, ++ .start = AR2315_SPI_MMR_BASE, ++ .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1, ++ }, ++}; ++ ++static struct platform_device ar2315_spiflash = { ++ .id = 0, ++ .name = "ar2315-spiflash", ++ .resource = ar2315_spiflash_res, ++ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) ++}; ++ + void __init ar2315_init_devices(void) + { + /* Find board configuration */ +@@ -230,6 +252,8 @@ void __init ar2315_init_devices(void) + ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; + platform_device_register(&ar2315_gpio); + ++ platform_device_register(&ar2315_spiflash); ++ + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac; + ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii", + AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0, diff --git a/target/linux/ath25/patches-3.18/130-watchdog.patch b/target/linux/ath25/patches-3.18/130-watchdog.patch new file mode 100644 index 0000000..255064a --- /dev/null +++ b/target/linux/ath25/patches-3.18/130-watchdog.patch @@ -0,0 +1,277 @@ +--- /dev/null ++++ b/drivers/watchdog/ar2315-wtd.c +@@ -0,0 +1,209 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see . ++ * ++ * Copyright (C) 2008 John Crispin ++ * Based on EP93xx and ifxmips wdt driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "ar2315-wdt" ++ ++#define CLOCK_RATE 40000000 ++#define HEARTBEAT(x) (x < 1 || x > 90 ? 20 : x) ++ ++#define WDT_REG_TIMER 0x00 ++#define WDT_REG_CTRL 0x04 ++ ++#define WDT_CTRL_ACT_NONE 0x00000000 /* No action */ ++#define WDT_CTRL_ACT_NMI 0x00000001 /* NMI on watchdog */ ++#define WDT_CTRL_ACT_RESET 0x00000002 /* reset on watchdog */ ++ ++static int wdt_timeout = 20; ++static int started; ++static int in_use; ++static void __iomem *wdt_base; ++ ++static inline void ar2315_wdt_wr(unsigned reg, u32 val) ++{ ++ iowrite32(val, wdt_base + reg); ++} ++ ++static void ++ar2315_wdt_enable(void) ++{ ++ ar2315_wdt_wr(WDT_REG_TIMER, wdt_timeout * CLOCK_RATE); ++} ++ ++static ssize_t ++ar2315_wdt_write(struct file *file, const char __user *data, size_t len, ++ loff_t *ppos) ++{ ++ if (len) ++ ar2315_wdt_enable(); ++ return len; ++} ++ ++static int ++ar2315_wdt_open(struct inode *inode, struct file *file) ++{ ++ if (in_use) ++ return -EBUSY; ++ ar2315_wdt_enable(); ++ in_use = 1; ++ started = 1; ++ return nonseekable_open(inode, file); ++} ++ ++static int ++ar2315_wdt_release(struct inode *inode, struct file *file) ++{ ++ in_use = 0; ++ return 0; ++} ++ ++static irqreturn_t ++ar2315_wdt_interrupt(int irq, void *dev) ++{ ++ struct platform_device *pdev = (struct platform_device *)dev; ++ ++ if (started) { ++ dev_crit(&pdev->dev, "watchdog expired, rebooting system\n"); ++ emergency_restart(); ++ } else { ++ ar2315_wdt_wr(WDT_REG_CTRL, 0); ++ ar2315_wdt_wr(WDT_REG_TIMER, 0); ++ } ++ return IRQ_HANDLED; ++} ++ ++static struct watchdog_info ident = { ++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, ++ .identity = "ar2315 Watchdog", ++}; ++ ++static long ++ar2315_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int new_wdt_timeout; ++ int ret = -ENOIOCTLCMD; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ ret = copy_to_user((void __user *)arg, &ident, sizeof(ident)) ? ++ -EFAULT : 0; ++ break; ++ case WDIOC_KEEPALIVE: ++ ar2315_wdt_enable(); ++ ret = 0; ++ break; ++ case WDIOC_SETTIMEOUT: ++ ret = get_user(new_wdt_timeout, (int __user *)arg); ++ if (ret) ++ break; ++ wdt_timeout = HEARTBEAT(new_wdt_timeout); ++ ar2315_wdt_enable(); ++ break; ++ case WDIOC_GETTIMEOUT: ++ ret = put_user(wdt_timeout, (int __user *)arg); ++ break; ++ } ++ return ret; ++} ++ ++static const struct file_operations ar2315_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = ar2315_wdt_write, ++ .unlocked_ioctl = ar2315_wdt_ioctl, ++ .open = ar2315_wdt_open, ++ .release = ar2315_wdt_release, ++}; ++ ++static struct miscdevice ar2315_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &ar2315_wdt_fops, ++}; ++ ++static int ++ar2315_wdt_probe(struct platform_device *dev) ++{ ++ struct resource *mem_res, *irq_res; ++ int ret = 0; ++ ++ if (wdt_base) ++ return -EBUSY; ++ ++ irq_res = platform_get_resource(dev, IORESOURCE_IRQ, 0); ++ if (!irq_res) { ++ dev_err(&dev->dev, "no IRQ resource\n"); ++ return -ENOENT; ++ } ++ ++ mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ wdt_base = devm_ioremap_resource(&dev->dev, mem_res); ++ if (IS_ERR(wdt_base)) ++ return PTR_ERR(wdt_base); ++ ++ ret = devm_request_irq(&dev->dev, irq_res->start, ar2315_wdt_interrupt, ++ IRQF_DISABLED, DRIVER_NAME, dev); ++ if (ret) { ++ dev_err(&dev->dev, "failed to register inetrrupt\n"); ++ goto out; ++ } ++ ++ ret = misc_register(&ar2315_wdt_miscdev); ++ if (ret) ++ dev_err(&dev->dev, "failed to register miscdev\n"); ++ ++out: ++ return ret; ++} ++ ++static int ++ar2315_wdt_remove(struct platform_device *dev) ++{ ++ misc_deregister(&ar2315_wdt_miscdev); ++ return 0; ++} ++ ++static struct platform_driver ar2315_wdt_driver = { ++ .probe = ar2315_wdt_probe, ++ .remove = ar2315_wdt_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(ar2315_wdt_driver); ++ ++MODULE_DESCRIPTION("Atheros AR2315 hardware watchdog driver"); ++MODULE_AUTHOR("John Crispin "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" DRIVER_NAME); +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1257,6 +1257,13 @@ config RALINK_WDT + help + Hardware driver for the Ralink SoC Watchdog Timer. + ++config AR2315_WDT ++ tristate "Atheros AR2315+ WiSoCs Watchdog Timer" ++ depends on ATH25 ++ help ++ Hardware driver for the built-in watchdog timer on the Atheros ++ AR2315/AR2316 WiSoCs. ++ + # PARISC Architecture + + # POWERPC Architecture +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -138,6 +138,7 @@ obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o ++obj-$(CONFIG_AR2315_WDT) += ar2315-wtd.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o + obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o + octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +--- a/arch/mips/ath25/ar2315.c ++++ b/arch/mips/ath25/ar2315.c +@@ -220,6 +220,24 @@ static struct platform_device ar2315_gpi + .num_resources = ARRAY_SIZE(ar2315_gpio_res) + }; + ++static struct resource ar2315_wdt_res[] = { ++ { ++ .flags = IORESOURCE_MEM, ++ .start = AR2315_RST_BASE + AR2315_WDT_TIMER, ++ .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1, ++ }, ++ { ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device ar2315_wdt = { ++ .id = 0, ++ .name = "ar2315-wdt", ++ .resource = ar2315_wdt_res, ++ .num_resources = ARRAY_SIZE(ar2315_wdt_res) ++}; ++ + static struct resource ar2315_spiflash_res[] = { + { + .name = "spiflash_read", +@@ -252,6 +270,11 @@ void __init ar2315_init_devices(void) + ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; + platform_device_register(&ar2315_gpio); + ++ ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain, ++ AR2315_MISC_IRQ_WATCHDOG); ++ ar2315_wdt_res[1].end = ar2315_wdt_res[1].start; ++ platform_device_register(&ar2315_wdt); ++ + platform_device_register(&ar2315_spiflash); + + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac; diff --git a/target/linux/ath25/patches-3.18/140-redboot_boardconfig.patch b/target/linux/ath25/patches-3.18/140-redboot_boardconfig.patch new file mode 100644 index 0000000..98dbf52 --- /dev/null +++ b/target/linux/ath25/patches-3.18/140-redboot_boardconfig.patch @@ -0,0 +1,60 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -30,6 +30,8 @@ + #include + #include + ++#define BOARD_CONFIG_PART "boardconfig" ++ + struct fis_image_desc { + unsigned char name[16]; // Null terminated name + uint32_t flash_base; // Address within FLASH of image +@@ -60,6 +62,7 @@ static int parse_redboot_partitions(stru + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) + { ++ unsigned long max_offset = 0; + int nrparts = 0; + struct fis_image_desc *buf; + struct mtd_partition *parts; +@@ -225,14 +228,15 @@ static int parse_redboot_partitions(stru + } + } + #endif +- parts = kzalloc(sizeof(*parts)*nrparts + nulllen + namelen, GFP_KERNEL); ++ parts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen + ++ sizeof(BOARD_CONFIG_PART), GFP_KERNEL); + + if (!parts) { + ret = -ENOMEM; + goto out; + } + +- nullname = (char *)&parts[nrparts]; ++ nullname = (char *)&parts[nrparts + 1]; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + if (nulllen > 0) { + strcpy(nullname, nullstring); +@@ -251,6 +255,8 @@ static int parse_redboot_partitions(stru + } + #endif + for ( ; iimg->size; + parts[i].offset = fl->img->flash_base; + parts[i].name = names; +@@ -284,6 +290,13 @@ static int parse_redboot_partitions(stru + fl = fl->next; + kfree(tmp_fl); + } ++ if (master->size - max_offset >= master->erasesize) { ++ parts[nrparts].size = master->size - max_offset; ++ parts[nrparts].offset = max_offset; ++ parts[nrparts].name = names; ++ strcpy(names, BOARD_CONFIG_PART); ++ nrparts++; ++ } + ret = nrparts; + *pparts = parts; + out: diff --git a/target/linux/ath25/patches-3.18/141-redboot_partition_scan.patch b/target/linux/ath25/patches-3.18/141-redboot_partition_scan.patch new file mode 100644 index 0000000..d1d281e --- /dev/null +++ b/target/linux/ath25/patches-3.18/141-redboot_partition_scan.patch @@ -0,0 +1,44 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -79,12 +79,18 @@ static int parse_redboot_partitions(stru + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; + while (mtd_block_isbad(master, offset)) { + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; +@@ -97,10 +103,6 @@ static int parse_redboot_partitions(stru + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; + + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); +@@ -173,6 +175,11 @@ static int parse_redboot_partitions(stru + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; diff --git a/target/linux/ath25/patches-3.18/142-redboot_various_erase_size_fix.patch b/target/linux/ath25/patches-3.18/142-redboot_various_erase_size_fix.patch new file mode 100644 index 0000000..e1b0a89 --- /dev/null +++ b/target/linux/ath25/patches-3.18/142-redboot_various_erase_size_fix.patch @@ -0,0 +1,72 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -58,6 +58,22 @@ static inline int redboot_checksum(struc + return 1; + } + ++static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) ++{ ++ struct mtd_erase_region_info *regions = mtd->eraseregions; ++ int i; ++ ++ for (i = 0; i < mtd->numeraseregions; i++) { ++ if (regions[i].offset + ++ regions[i].numblocks * regions[i].erasesize <= offset) ++ continue; ++ ++ return regions[i].erasesize; ++ } ++ ++ return mtd->erasesize; ++} ++ + static int parse_redboot_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -74,6 +90,7 @@ static int parse_redboot_partitions(stru + int namelen = 0; + int nulllen = 0; + int numslots; ++ int first_slot; + unsigned long offset; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; +@@ -186,7 +203,10 @@ static int parse_redboot_partitions(stru + goto out; + } + +- for (i = 0; i < numslots; i++) { ++ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / ++ sizeof(struct fis_image_desc); ++ ++ for (i = first_slot; i < first_slot + numslots; i++) { + struct fis_list *new_fl, **prev; + + if (buf[i].name[0] == 0xff) { +@@ -262,12 +282,13 @@ static int parse_redboot_partitions(stru + } + #endif + for ( ; iimg->size; + parts[i].offset = fl->img->flash_base; + parts[i].name = names; + ++ if (max_offset < parts[i].offset + parts[i].size) ++ max_offset = parts[i].offset + parts[i].size; ++ + strcpy(names, fl->img->name); + #ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY + if (!memcmp(names, "RedBoot", 8) || +@@ -297,7 +318,9 @@ static int parse_redboot_partitions(stru + fl = fl->next; + kfree(tmp_fl); + } +- if (master->size - max_offset >= master->erasesize) { ++ ++ if (master->size - max_offset >= ++ mtd_get_offset_erasesize(master, max_offset)) { + parts[nrparts].size = master->size - max_offset; + parts[nrparts].offset = max_offset; + parts[nrparts].name = names; diff --git a/target/linux/ath25/patches-3.18/210-reset_button.patch b/target/linux/ath25/patches-3.18/210-reset_button.patch new file mode 100644 index 0000000..34ef46b --- /dev/null +++ b/target/linux/ath25/patches-3.18/210-reset_button.patch @@ -0,0 +1,71 @@ +--- a/arch/mips/ath25/Makefile ++++ b/arch/mips/ath25/Makefile +@@ -8,7 +8,7 @@ + # Copyright (C) 2006-2009 Felix Fietkau + # + +-obj-y += board.o prom.o devices.o ++obj-y += board.o prom.o devices.o reset.o + + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +--- /dev/null ++++ b/arch/mips/ath25/reset.c +@@ -0,0 +1,57 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++static int __init ++ar231x_init_reset(void) ++{ ++ struct platform_device *pdev; ++ struct gpio_keys_platform_data pdata; ++ struct gpio_keys_button *p; ++ int err; ++ ++ if (ath25_board.config->reset_config_gpio == 0xffff) ++ return -ENODEV; ++ ++ p = kzalloc(sizeof(*p), GFP_KERNEL); ++ if (!p) ++ goto err; ++ ++ p->desc = "reset"; ++ p->type = EV_KEY; ++ p->code = KEY_RESTART; ++ p->debounce_interval = 60; ++ p->gpio = ath25_board.config->reset_config_gpio; ++ ++ memset(&pdata, 0, sizeof(pdata)); ++ pdata.poll_interval = 20; ++ pdata.buttons = p; ++ pdata.nbuttons = 1; ++ ++ pdev = platform_device_alloc("gpio-keys-polled", 0); ++ if (!pdev) ++ goto err_free; ++ ++ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); ++ if (err) ++ goto err_put_pdev; ++ ++ err = platform_device_add(pdev); ++ if (err) ++ goto err_put_pdev; ++ ++ return 0; ++ ++err_put_pdev: ++ platform_device_put(pdev); ++err_free: ++ kfree(p); ++err: ++ return -ENOMEM; ++} ++ ++module_init(ar231x_init_reset); diff --git a/target/linux/ath25/patches-3.18/220-enet_micrel_workaround.patch b/target/linux/ath25/patches-3.18/220-enet_micrel_workaround.patch new file mode 100644 index 0000000..398495a --- /dev/null +++ b/target/linux/ath25/patches-3.18/220-enet_micrel_workaround.patch @@ -0,0 +1,91 @@ +--- a/drivers/net/ethernet/atheros/ar231x/ar231x.c ++++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c +@@ -135,6 +135,7 @@ static int ar231x_mdiobus_write(struct m + static int ar231x_mdiobus_reset(struct mii_bus *bus); + static int ar231x_mdiobus_probe(struct net_device *dev); + static void ar231x_adjust_link(struct net_device *dev); ++static bool no_phy; + + #ifndef ERR + #define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) +@@ -167,6 +168,32 @@ static const struct net_device_ops ar231 + #endif + }; + ++static int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id) ++{ ++ int phy_reg; ++ ++ /** ++ * Grab the bits from PHYIR1, and put them ++ * in the upper half. ++ */ ++ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1); ++ ++ if (phy_reg < 0) ++ return -EIO; ++ ++ *phy_id = (phy_reg & 0xffff) << 16; ++ ++ /* Grab the bits from PHYIR2, and put them in the lower half */ ++ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2); ++ ++ if (phy_reg < 0) ++ return -EIO; ++ ++ *phy_id |= (phy_reg & 0xffff); ++ ++ return 0; ++} ++ + static int ar231x_probe(struct platform_device *pdev) + { + struct net_device *dev; +@@ -273,6 +300,24 @@ static int ar231x_probe(struct platform_ + + mdiobus_register(sp->mii_bus); + ++ /** ++ * Workaround for Micrel switch, which is only available on ++ * one PHY and cannot be configured through MDIO. ++ */ ++ if (!no_phy) { ++ u32 phy_id = 0; ++ ++ get_phy_id(sp->mii_bus, 1, &phy_id); ++ if (phy_id == 0x00221450) ++ no_phy = true; ++ } ++ if (no_phy) { ++ sp->link = 1; ++ netif_carrier_on(dev); ++ return 0; ++ } ++ no_phy = true; ++ + if (ar231x_mdiobus_probe(dev) != 0) { + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); + rx_tasklet_cleanup(dev); +@@ -329,8 +374,10 @@ static int ar231x_remove(struct platform + rx_tasklet_cleanup(dev); + ar231x_init_cleanup(dev); + unregister_netdev(dev); +- mdiobus_unregister(sp->mii_bus); +- mdiobus_free(sp->mii_bus); ++ if (sp->mii_bus) { ++ mdiobus_unregister(sp->mii_bus); ++ mdiobus_free(sp->mii_bus); ++ } + kfree(dev); + return 0; + } +@@ -1079,6 +1126,9 @@ static int ar231x_ioctl(struct net_devic + { + struct ar231x_private *sp = netdev_priv(dev); + ++ if (!sp->phy_dev) ++ return -ENODEV; ++ + switch (cmd) { + case SIOCGMIIPHY: + case SIOCGMIIREG: diff --git a/target/linux/ath25/patches-3.18/330-board_leds.patch b/target/linux/ath25/patches-3.18/330-board_leds.patch new file mode 100644 index 0000000..e357fc6 --- /dev/null +++ b/target/linux/ath25/patches-3.18/330-board_leds.patch @@ -0,0 +1,116 @@ +--- a/arch/mips/ath25/ar2315.c ++++ b/arch/mips/ath25/ar2315.c +@@ -23,6 +23,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -260,6 +261,50 @@ static struct platform_device ar2315_spi + .num_resources = ARRAY_SIZE(ar2315_spiflash_res) + }; + ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar2315_leds[6]; ++static struct gpio_led_platform_data ar2315_led_data = { ++ .leds = (void *)ar2315_leds, ++}; ++ ++static struct platform_device ar2315_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = (void *)&ar2315_led_data, ++ } ++}; ++ ++static void __init ar2315_init_gpio_leds(void) ++{ ++ static char led_names[6][6]; ++ int i, led = 0; ++ ++ ar2315_led_data.num_leds = 0; ++ for (i = 1; i < 8; i++) { ++ if ((i == AR2315_RESET_GPIO) || ++ (i == ath25_board.config->reset_config_gpio)) ++ continue; ++ ++ if (i == ath25_board.config->sys_led_gpio) ++ strcpy(led_names[led], "wlan"); ++ else ++ sprintf(led_names[led], "gpio%d", i); ++ ++ ar2315_leds[led].name = led_names[led]; ++ ar2315_leds[led].gpio = i; ++ ar2315_leds[led].active_low = 0; ++ led++; ++ } ++ ar2315_led_data.num_leds = led; ++ platform_device_register(&ar2315_gpio_leds); ++} ++#else ++static inline void ar2315_init_gpio_leds(void) ++{ ++} ++#endif ++ + void __init ar2315_init_devices(void) + { + /* Find board configuration */ +@@ -270,6 +315,8 @@ void __init ar2315_init_devices(void) + ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; + platform_device_register(&ar2315_gpio); + ++ ar2315_init_gpio_leds(); ++ + ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain, + AR2315_MISC_IRQ_WATCHDOG); + ar2315_wdt_res[1].end = ar2315_wdt_res[1].start; +--- a/arch/mips/ath25/ar5312.c ++++ b/arch/mips/ath25/ar5312.c +@@ -23,6 +23,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -231,6 +232,23 @@ static struct platform_device ar5312_gpi + .num_resources = ARRAY_SIZE(ar5312_gpio_res), + }; + ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar5312_leds[] = { ++ { .name = "wlan", .gpio = 0, .active_low = 1, }, ++}; ++ ++static const struct gpio_led_platform_data ar5312_led_data = { ++ .num_leds = ARRAY_SIZE(ar5312_leds), ++ .leds = (void *)ar5312_leds, ++}; ++ ++static struct platform_device ar5312_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = (void *)&ar5312_led_data, ++}; ++#endif ++ + static void __init ar5312_flash_init(void) + { + void __iomem *flashctl_base; +@@ -301,6 +319,11 @@ void __init ar5312_init_devices(void) + + platform_device_register(&ar5312_gpio); + ++#ifdef CONFIG_LEDS_GPIO ++ ar5312_leds[0].gpio = config->sys_led_gpio; ++ platform_device_register(&ar5312_gpio_leds); ++#endif ++ + /* Fix up MAC addresses if necessary */ + if (is_broadcast_ether_addr(config->enet0_mac)) + ether_addr_copy(config->enet0_mac, config->enet1_mac); diff --git a/target/linux/au1000/Makefile b/target/linux/au1000/Makefile new file mode 100644 index 0000000..7438e9b --- /dev/null +++ b/target/linux/au1000/Makefile @@ -0,0 +1,32 @@ +# +# Copyright (C) 2006-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mipsel +BOARD:=au1000 +BOARDNAME:=RMI/AMD AU1x00 +FEATURES:=squashfs usb pci +SUBTARGETS=au1500 au1550 +MAINTAINER:=Florian Fainelli + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += wpad-mini yamonenv + +define Target/Description + Build firmware for RMI/AMD Alchemy 1500,1550 boards + (e.g. 4G-Systems Mesh/Access Cube, DBAu1550 ...) +endef + +define Kernel/BuildImage + $(call Kernel/BuildImage/Default) + $(CP) $(LINUX_DIR)/arch/mips/boot/compressed/images/zImage.flash.srec $(LINUX_DIR)/zImage.flash.srec + $(CP) $(LINUX_DIR)/arch/mips/boot/compressed/images/zImage.srec $(LINUX_DIR)/zImage.srec +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/au1000/au1500/config-default b/target/linux/au1000/au1500/config-default new file mode 100644 index 0000000..0289d96 --- /dev/null +++ b/target/linux/au1000/au1500/config-default @@ -0,0 +1,5 @@ +CONFIG_DMA_NONCOHERENT=y +# CONFIG_MIPS_DB1550 is not set +CONFIG_MIPS_MTX1=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_WDT_MTX1=y diff --git a/target/linux/au1000/au1500/profiles/Atheros.mk b/target/linux/au1000/au1500/profiles/Atheros.mk new file mode 100644 index 0000000..75e8e10 --- /dev/null +++ b/target/linux/au1000/au1500/profiles/Atheros.mk @@ -0,0 +1,13 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Atheros + NAME:=Atheros WiFi (default) + PACKAGES:=kmod-ath5k +endef +$(eval $(call Profile,Atheros)) + diff --git a/target/linux/au1000/au1500/profiles/InternetBox.mk b/target/linux/au1000/au1500/profiles/InternetBox.mk new file mode 100644 index 0000000..a73f0ce --- /dev/null +++ b/target/linux/au1000/au1500/profiles/InternetBox.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2007-2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/InternetBox + NAME:=T-Mobile "InternetBox" + PACKAGES:=kmod-ath5k kmod-usb-core kmod-usb-ohci kmod-usb-serial kmod-usb-serial-option \ + comgt +endef + +define Profile/InternetBox/Description + Package set for the T-Mobile "InternetBox" (TMD SB1-S) +endef + +$(eval $(call Profile,InternetBox)) diff --git a/target/linux/au1000/au1500/profiles/MeshCube.mk b/target/linux/au1000/au1500/profiles/MeshCube.mk new file mode 100644 index 0000000..5f0c14f --- /dev/null +++ b/target/linux/au1000/au1500/profiles/MeshCube.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2007-2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/MeshCube + NAME:=MeshCube MTX-1 + PACKAGES:=kmod-ath5k kmod-hostap kmod-hostap-pci kmod-net-prism54 \ + kmod-usb-core kmod-usb-ohci kmod-usb-storage kmod-fs-ext4 kmod-fs-vfat +endef + +define Profile/MeshCube/Description + Package set for the 4G MeshCube (MTX-1) +endef + +$(eval $(call Profile,MeshCube)) diff --git a/target/linux/au1000/au1500/target.mk b/target/linux/au1000/au1500/target.mk new file mode 100644 index 0000000..240914f --- /dev/null +++ b/target/linux/au1000/au1500/target.mk @@ -0,0 +1,7 @@ +BOARDNAME:=Au1500 + +DEFAULT_PACKAGES+= wpad-mini + +define Target/Description + Build firmware images for Au1500 based boards +endef diff --git a/target/linux/au1000/au1550/config-default b/target/linux/au1000/au1550/config-default new file mode 100644 index 0000000..2c641b8 --- /dev/null +++ b/target/linux/au1000/au1550/config-default @@ -0,0 +1,4 @@ +CONFIG_DMA_COHERENT=y +CONFIG_MIPS_DB1550=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_MIPS_MTX1 is not set diff --git a/target/linux/au1000/au1550/profiles/DBAu1550.mk b/target/linux/au1000/au1550/profiles/DBAu1550.mk new file mode 100644 index 0000000..3535be6 --- /dev/null +++ b/target/linux/au1000/au1550/profiles/DBAu1550.mk @@ -0,0 +1,13 @@ +# +# Copyright (C) 2009-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DBAu1550 + NAME:=AMD DBAu1550 Development Kit + PACKAGES:=kmod-pcmcia-au1000 kmod-usb-ohci kmod-usb2-pci +endef + +$(eval $(call Profile,DBAu1550)) diff --git a/target/linux/au1000/au1550/target.mk b/target/linux/au1000/au1550/target.mk new file mode 100644 index 0000000..1429cb4 --- /dev/null +++ b/target/linux/au1000/au1550/target.mk @@ -0,0 +1,8 @@ +BOARDNAME:=Au1550 +FEATURES += pcmcia + +DEFAULT_PACKAGES+= wpad-mini + +define Target/Description + Build firmware images for Au1550 based boards +endef diff --git a/target/linux/au1000/base-files/etc/diag.sh b/target/linux/au1000/base-files/etc/diag.sh new file mode 100644 index 0000000..65e3011 --- /dev/null +++ b/target/linux/au1000/base-files/etc/diag.sh @@ -0,0 +1,21 @@ +#!/bin/sh +# Copyright (C) 2007-2013 OpenWrt.org + +. /lib/functions/leds.sh + +set_state() { + case "$1" in + preinit) + led_off "mtx1:green" + led_on "mtx1:red" + ;; + failsafe) + led_on "mtx1:green" + led_on "mtx1:red" + ;; + done) + led_on "mtx1:green" + led_off "mtx1:red" + ;; + esac +} diff --git a/target/linux/au1000/base-files/lib/upgrade/platform.sh b/target/linux/au1000/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..1a9d151 --- /dev/null +++ b/target/linux/au1000/base-files/lib/upgrade/platform.sh @@ -0,0 +1,36 @@ +KERNEL_IMG="openwrt-au1000-au1500-vmlinux.bin" +ROOTFS_IMG="openwrt-au1000-au1500-root.fs" + +platform_check_image() { + [ "$#" -gt 1 ] && return 1 + case "$(get_magic_word "$1")" in + 6f70) + ( get_image "$1" | tar -tf - $KERNEL_IMG >/dev/null && \ + get_image "$1" | tar -tf - $ROOTFS_IMG >/dev/null) || { + echo "Invalid image contents" + return 1 + } + return 0;; + *) + echo "Invalid image type" + return 1;; + esac +} + +platform_do_upgrade() { + sync + local conf="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && conf="-j $CONF_TAR" + get_image "$1" | tar -Oxvf - $KERNEL_IMG | mtd write - "kernel" + get_image "$1" | tar -Oxvf - $ROOTFS_IMG | mtd $conf write - "rootfs" +} + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/au1000/config-3.18 b/target/linux/au1000/config-3.18 new file mode 100644 index 0000000..cb2eee2 --- /dev/null +++ b/target/linux/au1000/config-3.18 @@ -0,0 +1,141 @@ +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ALCHEMY_GPIOINT_AU1000=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/mtdblock0 rootfstype=squashfs,jffs2" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CRC16=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_CPU=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KEXEC=y +CONFIG_LEDS_GPIO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +CONFIG_MIPS_ALCHEMY=y +CONFIG_MIPS_AU1X00_ENET=y +CONFIG_MIPS_DB1000=y +# CONFIG_MIPS_DB1XXX is not set +# CONFIG_MIPS_DB1235 is not set +# CONFIG_MIPS_GPR is not set +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +# CONFIG_MIPS_MTX1 is not set +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_XXS1500 is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MTD_CFI_INTELEXT is not set +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_STANDALONE is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/au1000/image/Makefile b/target/linux/au1000/image/Makefile new file mode 100644 index 0000000..744e5c6 --- /dev/null +++ b/target/linux/au1000/image/Makefile @@ -0,0 +1,74 @@ +# +# Copyright (C) 2006-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +JFFS2_BLOCKSIZE = 128k + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +LOADADDR = 0x81000000 # RAM start + 16M +KERNEL_ENTRY = 0x80100000 +RAMSIZE = 0x00100000 # 1MB + +FLASH_KERNEL := 0xBFD00000 +FLASH_FS := 0xBE000000 + +LOADER_MAKEOPTS= \ + KDIR=$(KDIR) \ + LOADADDR=$(LOADADDR) \ + KERNEL_ENTRY=$(KERNEL_ENTRY) \ + RAMSIZE=$(RAMSIZE) + +define Build/Clean + $(MAKE) -C $(GENERIC_PLATFORM_DIR)/image/lzma-loader $(LOADER_MAKEOPTS) clean +endef + +DROP_SECTIONS := .reginfo .mdebug .comment .note .pdr .options .MIPS.options +OBJCOPY_SREC := $(TARGET_CROSS)objcopy -S -O srec $(addprefix --remove-section=,$(DROP_SECTIONS)) +OBJCOPY_BIN := $(TARGET_CROSS)objcopy -S -O binary $(addprefix --remove-section=,$(DROP_SECTIONS)) + +define Image/Prepare + cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma + + # Build RAM image + $(MAKE) -C $(GENERIC_PLATFORM_DIR)/image/lzma-loader \ + $(LOADER_MAKEOPTS) \ + clean compile + $(OBJCOPY_SREC) $(KDIR)/loader.elf $(KDIR)/kernel.ram.srec + + # Build Flash image + $(MAKE) -C $(GENERIC_PLATFORM_DIR)/image/lzma-loader \ + $(LOADER_MAKEOPTS) \ + IMAGE_COPY=1 \ + LOADER_ENTRY=$(FLASH_KERNEL) \ + LOADER_TYPE=_flash \ + clean compile + $(OBJCOPY_SREC) $(KDIR)/loader_flash.elf $(KDIR)/kernel.flash.srec + $(OBJCOPY_BIN) $(KDIR)/loader_flash.elf $(KDIR)/kernel.flash.bin +endef + +define Image/Build/Initramfs + $(OBJCOPY_SREC) $(KDIR)/vmlinux-initramfs.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.srec +endef + +define Image/Build + $(SCRIPT_DIR)/srecimage.pl $(KDIR)/root.$(1) $(KDIR)/root.$(1).srec $(FLASH_FS) + grep -v S7 $(KDIR)/root.$(1).srec > $(BIN_DIR)/$(IMG_PREFIX)-$(1).srec + grep -v S0 $(KDIR)/kernel.flash.srec >> $(BIN_DIR)/$(IMG_PREFIX)-$(1).srec + $(INSTALL_BIN) $(KDIR)/kernel.flash.bin $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.bin + $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).fs + $(CP) $(KDIR)/kernel.flash.srec $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-flash.srec + $(CP) $(KDIR)/kernel.ram.srec $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-ram.srec + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(1).fs $(TMP_DIR)/$(IMG_PREFIX)-root.fs + tar -C $(BIN_DIR) -cvzf $(BIN_DIR)/$(IMG_PREFIX)-$(1)-sysupgrade.bin \ + $(IMG_PREFIX)-vmlinux.bin -C $(TMP_DIR) $(IMG_PREFIX)-root.fs +ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y) + $(call Image/Build/Initramfs) +endif +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/au1000/modules.mk b/target/linux/au1000/modules.mk new file mode 100644 index 0000000..6b11053 --- /dev/null +++ b/target/linux/au1000/modules.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2010-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/pcmcia-au1000 + SUBMENU:=$(PCMCIA_MENU) + TITLE:=RMI/AMD Au1000 PCMCIA support + DEPENDS:=@TARGET_au1000 +kmod-pcmcia-core +kmod-pcmcia-rsrc + FILES:=$(LINUX_DIR)/drivers/pcmcia/db1xxx_ss.ko + KCONFIG:=CONFIG_PCMCIA_ALCHEMY_DEVBOARD + AUTOLOAD:=$(call AutoLoad,41,db1xxx_ss) +endef + +$(eval $(call KernelPackage,pcmcia-au1000)) diff --git a/target/linux/au1000/patches/002-openwrt_rootfs.patch b/target/linux/au1000/patches/002-openwrt_rootfs.patch new file mode 100644 index 0000000..1de8236 --- /dev/null +++ b/target/linux/au1000/patches/002-openwrt_rootfs.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/alchemy/board-mtx1.c ++++ b/arch/mips/alchemy/board-mtx1.c +@@ -169,7 +169,7 @@ static struct platform_device mtx1_gpio_ + + static struct mtd_partition mtx1_mtd_partitions[] = { + { +- .name = "filesystem", ++ .name = "rootfs", + .size = 0x01C00000, + .offset = 0, + }, diff --git a/target/linux/au1000/patches/003-au1000_eth_ioctl.patch b/target/linux/au1000/patches/003-au1000_eth_ioctl.patch new file mode 100644 index 0000000..58927f5 --- /dev/null +++ b/target/linux/au1000/patches/003-au1000_eth_ioctl.patch @@ -0,0 +1,17 @@ +--- a/drivers/net/ethernet/amd/au1000_eth.c ++++ b/drivers/net/ethernet/amd/au1000_eth.c +@@ -1113,10 +1113,14 @@ static void au1000_multicast_list(struct + writel(reg, &aup->mac->control); + } + ++#define AU1000_KNOWN_PHY_IOCTLS (SIOCGMIIPHY & 0xfff0) + static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) + { + struct au1000_private *aup = netdev_priv(dev); + ++ if((cmd & AU1000_KNOWN_PHY_IOCTLS) != AU1000_KNOWN_PHY_IOCTLS) ++ return -EINVAL; ++ + if (!netif_running(dev)) + return -EINVAL; + diff --git a/target/linux/au1000/patches/004-watchdog_low_init.patch b/target/linux/au1000/patches/004-watchdog_low_init.patch new file mode 100644 index 0000000..0911040 --- /dev/null +++ b/target/linux/au1000/patches/004-watchdog_low_init.patch @@ -0,0 +1,12 @@ +--- a/arch/mips/alchemy/board-mtx1.c ++++ b/arch/mips/alchemy/board-mtx1.c +@@ -98,6 +98,9 @@ void __init board_setup(void) + alchemy_gpio_direction_output(211, 1); /* green on */ + alchemy_gpio_direction_output(212, 0); /* red off */ + ++ /* Set watchdog pin low */ ++ alchemy_gpio_direction_output(215, 0); ++ + pm_power_off = mtx1_power_off; + _machine_halt = mtx1_power_off; + _machine_restart = mtx1_reset; diff --git a/target/linux/au1000/patches/006-codec.patch b/target/linux/au1000/patches/006-codec.patch new file mode 100644 index 0000000..d80cf56 --- /dev/null +++ b/target/linux/au1000/patches/006-codec.patch @@ -0,0 +1,26 @@ +--- a/arch/mips/alchemy/devboards/db1300.c ++++ b/arch/mips/alchemy/devboards/db1300.c +@@ -712,6 +712,7 @@ static struct platform_device db1300_lcd + + /**********************************************************************/ + ++#ifdef CONFIG_TOUCHSCREEN_WM97XX + static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable) + { + if (enable) +@@ -744,6 +745,15 @@ static int db1300_wm97xx_probe(struct pl + return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops); + } + ++#else ++ ++static int db1300_wm97xx_probe(struct platform_device *pdev) ++{ ++ return -1; ++} ++ ++#endif ++ + static struct platform_driver db1300_wm97xx_driver = { + .driver.name = "wm97xx-touch", + .driver.owner = THIS_MODULE, diff --git a/target/linux/bcm53xx/Makefile b/target/linux/bcm53xx/Makefile new file mode 100644 index 0000000..68cfa63 --- /dev/null +++ b/target/linux/bcm53xx/Makefile @@ -0,0 +1,30 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=bcm53xx +BOARDNAME:=Broadcom BCM47xx/53xx (ARM) +FEATURES:=squashfs nand usb pci pcie gpio +MAINTAINER:=Hauke Mehrtens +CPU_TYPE:=cortex-a9 + +KERNEL_PATCHVER:=4.1 + +include $(INCLUDE_DIR)/target.mk + +define Target/Description + Build firmware images for Broadcom based BCM47xx/53xx routers with ARM CPU, *not* MIPS. +endef + +KERNELNAME:=zImage dtbs + +DEFAULT_PACKAGES += swconfig wpad-mini nvram otrx \ + kmod-gpio-button-hotplug \ + kmod-leds-gpio kmod-ledtrig-default-on kmod-ledtrig-timer + +$(eval $(call BuildTarget)) diff --git a/target/linux/bcm53xx/base-files.mk b/target/linux/bcm53xx/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/bcm53xx/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/bcm53xx/base-files/etc/board.d/02_network b/target/linux/bcm53xx/base-files/etc/board.d/02_network new file mode 100755 index 0000000..a164251 --- /dev/null +++ b/target/linux/bcm53xx/base-files/etc/board.d/02_network @@ -0,0 +1,70 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# + +. /lib/functions/uci-defaults-new.sh + +board_config_update + +board=$(cat /proc/device-tree/compatible | tr '\0' '\t' | cut -f 1) +case "$board" in +asus,rt-ac87u) + ifname=eth1 + ;; +netgear,r8000) + ifname=eth2 + ;; +*) + ifname=eth0 + ;; +esac + +# Workaround for devices using eth2 +case "$board" in +netgear,r8000) + ifname=eth0 + ;; +esac + +ucidef_set_interface_loopback +ucidef_set_interfaces_lan_wan "$ifname.1" "$ifname.2" +ucidef_add_switch "switch0" "1" "1" + +# Workaround for devices using CPU port 8 (connected to eth2) +case "$board" in +netgear,r8000) + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + ucidef_add_switch_vlan "switch0" "2" "4 5t" + board_config_flush + exit 0 + ;; +esac + +# NVRAM entries may contain unsorted ports, e.g. Netgear R6250 uses +# vlan1ports=3 2 1 0 5* +# vlan2ports=4 5u +# and early Netgear R8000 was using +# vlan1ports=3 2 1 0 5 7 8* +vlan1ports="$(echo $(nvram get vlan1ports | tr " " "\n" | sort))" +vlan2ports="$(echo $(nvram get vlan2ports | tr " " "\n" | sort))" +if echo "$vlan1ports" | egrep -q "^1 2 3 4 5" && \ + echo "$vlan2ports" | egrep -q "^0 5"; then + ucidef_add_switch_vlan "switch0" "1" "1 2 3 4 5t" + ucidef_add_switch_vlan "switch0" "2" "0 5t" +elif echo "$vlan1ports" | egrep -q "^1 2 3 5 7" && \ + echo "$vlan2ports" | egrep -q "^0 7"; then + ucidef_add_switch_vlan "switch0" "1" "1 2 3 5 7t" + ucidef_add_switch_vlan "switch0" "2" "0 7t" +elif echo "$vlan1ports" | egrep -q "^0 1 2 3 5 7 8" && \ + echo "$vlan2ports" | egrep -q "^4 8"; then + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5 7 8t" + ucidef_add_switch_vlan "switch0" "2" "4 8t" +else + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5t" + ucidef_add_switch_vlan "switch0" "2" "4 5t" +fi + +board_config_flush + +exit 0 diff --git a/target/linux/bcm53xx/base-files/etc/diag.sh b/target/linux/bcm53xx/base-files/etc/diag.sh new file mode 100644 index 0000000..0a8c5fb --- /dev/null +++ b/target/linux/bcm53xx/base-files/etc/diag.sh @@ -0,0 +1,43 @@ +#!/bin/sh +# Copyright (C) 2014 OpenWrt.org + +. /lib/functions/leds.sh + +get_status_led() { + local status_led_file + + # There may be more than one color of power LED, try to avoid amber/red + status_led_file=$(find /sys/class/leds/ -name "*:power" -a ! -name "*:amber:*" -a ! -name "*:red:*" | head -n1) + if [ -d "$status_led_file" ]; then + status_led=$(basename $status_led_file) + return + fi; + + # Now just pick any power LED + status_led_file=$(find /sys/class/leds/ -name "*:power:*" | head -n1) + if [ -d "$status_led_file" ]; then + status_led=$(basename $status_led_file) + return + fi; +} + +set_state() { + get_status_led + + [ -z "$status_led" ] && return + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/bcm53xx/base-files/etc/uci-defaults/09_fix_crc b/target/linux/bcm53xx/base-files/etc/uci-defaults/09_fix_crc new file mode 100644 index 0000000..346a532 --- /dev/null +++ b/target/linux/bcm53xx/base-files/etc/uci-defaults/09_fix_crc @@ -0,0 +1,7 @@ +#!/bin/sh +# +# Copyright (C) 2007 OpenWrt.org +# +# + +mtd fixtrx firmware diff --git a/target/linux/bcm53xx/base-files/lib/preinit/05_set_preinit_iface_bcm53xx b/target/linux/bcm53xx/base-files/lib/preinit/05_set_preinit_iface_bcm53xx new file mode 100644 index 0000000..0539b82 --- /dev/null +++ b/target/linux/bcm53xx/base-files/lib/preinit/05_set_preinit_iface_bcm53xx @@ -0,0 +1,7 @@ +#!/bin/sh + +set_preinit_iface() { + ifname=eth0 +} + +boot_hook_add preinit_main set_preinit_iface diff --git a/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh b/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..eff7aff --- /dev/null +++ b/target/linux/bcm53xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,210 @@ +PART_NAME=firmware + +# $(1): file to read magic from +# $(2): offset in bytes +get_magic_long_at() { + dd if="$1" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -e '1/1 "%02x"' +} + +platform_machine() { + cat /proc/device-tree/compatible | tr '\0' '\t' | cut -f 1 +} + +platform_flash_type() { + # On NAND devices "rootfs" is UBI volume, so won't be find in /proc/mtd + grep -q "\"rootfs\"" /proc/mtd && { + echo "serial" + return + } + + echo "nand" +} + +platform_expected_image() { + local machine=$(platform_machine) + + case "$machine" in + "netgear,r6250v1") echo "chk U12H245T00_NETGEAR"; return;; + "netgear,r6300v2") echo "chk U12H240T00_NETGEAR"; return;; + "netgear,r7000") echo "chk U12H270T00_NETGEAR"; return;; + "netgear,r8000") echo "chk U12H315T00_NETGEAR"; return;; + esac +} + +platform_identify() { + local magic + + magic=$(get_magic_long "$1") + case "$magic" in + "48445230") + echo "trx" + return + ;; + "2a23245e") + echo "chk" + return + ;; + esac + + magic=$(get_magic_long_at "$1" 14) + [ "$magic" = "55324e44" ] && { + echo "cybertan" + return + } + + echo "unknown" +} + +platform_check_image() { + [ "$#" -gt 1 ] && return 1 + + local file_type=$(platform_identify "$1") + local magic + local error=0 + + case "$file_type" in + "chk") + local header_len=$((0x$(get_magic_long_at "$1" 4))) + local board_id_len=$(($header_len - 40)) + local board_id=$(dd if="$1" skip=40 bs=1 count=$board_id_len 2>/dev/null | hexdump -v -e '1/1 "%c"') + local dev_board_id=$(platform_expected_image) + echo "Found CHK image with device board_id $board_id" + + [ -n "$dev_board_id" -a "chk $board_id" != "$dev_board_id" ] && { + echo "Firmware board_id doesn't match device board_id ($dev_board_id)" + error=1 + } + + if ! otrx check "$1" -o "$header_len"; then + echo "No valid TRX firmware in the CHK image" + error=1 + fi + ;; + "cybertan") + local pattern=$(dd if="$1" bs=1 count=4 2>/dev/null | hexdump -v -e '1/1 "%c"') + local dev_pattern=$(platform_expected_image) + echo "Found CyberTAN image with device pattern: $pattern" + + [ -n "$dev_pattern" -a "cybertan $pattern" != "$dev_pattern" ] && { + echo "Firmware pattern doesn't match device pattern ($dev_pattern)" + error=1 + } + + if ! otrx check "$1" -o 32; then + echo "No valid TRX firmware in the CyberTAN image" + error=1 + fi + ;; + "trx") + if ! otrx check "$1"; then + echo "Invalid (corrupted?) TRX firmware" + error=1 + fi + ;; + *) + echo "Invalid image type. Please use only .trx files" + error=1 + ;; + esac + + return $error +} + +platform_pre_upgrade() { + local file_type=$(platform_identify "$1") + local dir="/tmp/sysupgrade-bcm53xx" + local trx="$1" + local offset + + [ "$(platform_flash_type)" != "nand" ] && return + + # Find trx offset + case "$file_type" in + "chk") offset=$((0x$(get_magic_long_at "$1" 4)));; + "cybertan") offset=32;; + esac + + # Extract partitions from trx + rm -fR $dir + mkdir -p $dir + otrx extract "$trx" \ + ${offset:+-o $offset} \ + -1 $dir/kernel \ + -2 $dir/root + [ $? -ne 0 ] && { + echo "Failed to extract TRX partitions." + return + } + + # Firmwares without UBI image should be flashed "normally" + local root_type=$(identify $dir/root) + [ "$root_type" != "ubi" ] && { + echo "Provided firmware doesn't use UBI for rootfs." + return + } + + # Prepare TRX file with just a kernel that will replace current one + local linux_length=$(grep "\"linux\"" /proc/mtd | sed "s/mtd[0-9]*:[ \t]*\([^ \t]*\).*/\1/") + [ -z "$linux_length" ] && { + echo "Unable to find \"linux\" partition size" + exit 1 + } + linux_length=$((0x$linux_length)) + local kernel_length=$(wc -c $dir/kernel | cut -d ' ' -f 1) + [ $kernel_length -gt $linux_length ] && { + echo "New kernel doesn't fit \"linux\" partition." + return + } + rm -f /tmp/null.bin + rm -f /tmp/kernel.trx + touch /tmp/null.bin + otrx create /tmp/kernel.trx \ + -f $dir/kernel -b $(($linux_length + 28)) \ + -f /tmp/null.bin + [ $? -ne 0 ] && { + echo "Failed to create simple TRX with new kernel." + return + } + + # Prepare UBI image (drop unwanted extra blocks) + local ubi_length=0 + while [ "$(dd if=$dir/root skip=$ubi_length bs=1 count=4 2>/dev/null)" = "UBI#" ]; do + ubi_length=$(($ubi_length + 131072)) + done + dd if=$dir/root of=/tmp/root.ubi bs=131072 count=$((ubi_length / 131072)) 2>/dev/null + [ $? -ne 0 ] && { + echo "Failed to prepare new UBI image." + return + } + + # Flash + mtd write /tmp/kernel.trx firmware + nand_do_upgrade /tmp/root.ubi +} + +platform_trx_from_chk_cmd() { + local header_len=$((0x$(get_magic_long_at "$1" 4))) + + echo -n dd bs=$header_len skip=1 +} + +platform_trx_from_cybertan_cmd() { + echo -n dd bs=32 skip=1 +} + +platform_do_upgrade() { + local file_type=$(platform_identify "$1") + local trx="$1" + local cmd= + + [ "$(platform_flash_type)" == "nand" ] && { + echo "Writing whole image to NAND flash. All erase counters will be lost." + } + + case "$file_type" in + "chk") cmd=$(platform_trx_from_chk_cmd "$trx");; + "cybertan") cmd=$(platform_trx_from_cybertan_cmd "$trx");; + esac + + default_do_upgrade "$trx" "$cmd" +} diff --git a/target/linux/bcm53xx/config-4.1 b/target/linux/bcm53xx/config-4.1 new file mode 100644 index 0000000..e2d122b --- /dev/null +++ b/target/linux/bcm53xx/config-4.1 @@ -0,0 +1,305 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ARCH_ALPINE is not set +CONFIG_ARCH_BCM=y +# CONFIG_ARCH_BCM_21664 is not set +# CONFIG_ARCH_BCM_281XX is not set +CONFIG_ARCH_BCM_5301X=y +# CONFIG_ARCH_BCM_63XX is not set +# CONFIG_ARCH_BCM_CYGNUS is not set +CONFIG_ARCH_BCM_IPROC=y +# CONFIG_ARCH_BRCMSTB is not set +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_ERRATA_798181=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GLOBAL_TIMER=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_B53=y +# CONFIG_B53_MMAP_DRIVER is not set +# CONFIG_B53_PHY_DRIVER is not set +CONFIG_B53_SRAB_DRIVER=y +CONFIG_BCM47XX_NVRAM=y +CONFIG_BCM47XX_SPROM=y +CONFIG_BCM47XX_WDT=y +CONFIG_BCMA=y +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_DEBUG=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BGMAC=y +CONFIG_BOUNCE=y +CONFIG_CACHE_L2X0=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BCM_5301X=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=0 +CONFIG_DEBUG_UART_PHYS=0x18000300 +CONFIG_DEBUG_UART_VIRT=0xf1000300 +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_DEBUG_USER=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_FIXED_PHY=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_74X164=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_LIBFDT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_BCM47XX_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_BRCMNAND=y +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MTD_SPI_BCM53XXSPIFLASH=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NO_BOOTMEM=y +CONFIG_NR_CPUS=2 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCIE_IPROC=y +CONFIG_PCIE_IPROC_BCMA=y +# CONFIG_PCIE_IPROC_PLATFORM is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +# CONFIG_PL310_ERRATA_588369 is not set +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BCM53XX=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SRCU=y +CONFIG_STOP_MACHINE=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/bcm53xx/config-4.3 b/target/linux/bcm53xx/config-4.3 new file mode 100644 index 0000000..16705a1 --- /dev/null +++ b/target/linux/bcm53xx/config-4.3 @@ -0,0 +1,319 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BCM=y +# CONFIG_ARCH_BCM_21664 is not set +# CONFIG_ARCH_BCM_281XX is not set +CONFIG_ARCH_BCM_5301X=y +# CONFIG_ARCH_BCM_63XX is not set +# CONFIG_ARCH_BCM_CYGNUS is not set +CONFIG_ARCH_BCM_IPROC=y +# CONFIG_ARCH_BRCMSTB is not set +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_ERRATA_798181=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GLOBAL_TIMER=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_B53=y +# CONFIG_B53_MMAP_DRIVER is not set +# CONFIG_B53_PHY_DRIVER is not set +CONFIG_B53_SRAB_DRIVER=y +CONFIG_BCM47XX_NVRAM=y +CONFIG_BCM47XX_SPROM=y +CONFIG_BCM47XX_WDT=y +CONFIG_BCMA=y +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_DEBUG=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BGMAC=y +CONFIG_BOUNCE=y +CONFIG_CACHE_L2X0=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_IPROC=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BCM_5301X=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=0 +CONFIG_DEBUG_UART_PHYS=0x18000300 +CONFIG_DEBUG_UART_VIRT=0xf1000300 +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_DEBUG_USER=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_74X164=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_LIBFDT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_BCM47XX_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_BRCMNAND=y +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MTD_SPI_BCM53XXSPIFLASH=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NO_BOOTMEM=y +CONFIG_NR_CPUS=2 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCIE_IPROC=y +CONFIG_PCIE_IPROC_BCMA=y +# CONFIG_PCIE_IPROC_PLATFORM is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +# CONFIG_PL310_ERRATA_588369 is not set +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SG_SPLIT is not set +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BCM53XX=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SRCU=y +CONFIG_STOP_MACHINE=y +# CONFIG_SUNXI_SRAM is not set +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/Kconfig b/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/Kconfig new file mode 100644 index 0000000..6bed119 --- /dev/null +++ b/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/Kconfig @@ -0,0 +1,11 @@ +config BCM47XX_NVRAM + bool "Broadcom NVRAM driver" + depends on BCM47XX || ARCH_BCM_5301X + help + Broadcom home routers contain flash partition called "nvram" with all + important hardware configuration as well as some minor user setup. + NVRAM partition contains a text-like data representing name=value + pairs. + This driver provides an easy way to get value of requested parameter. + It simply reads content of NVRAM and parses it. It doesn't control any + hardware part itself. diff --git a/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/Makefile b/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/Makefile new file mode 100644 index 0000000..d0e6835 --- /dev/null +++ b/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o diff --git a/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/bcm47xx_nvram.c b/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/bcm47xx_nvram.c new file mode 100644 index 0000000..87add3f --- /dev/null +++ b/target/linux/bcm53xx/files-4.1/drivers/firmware/broadcom/bcm47xx_nvram.c @@ -0,0 +1,248 @@ +/* + * BCM947xx nvram variable access + * + * Copyright (C) 2005 Broadcom Corporation + * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2010-2012 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */ +#define NVRAM_SPACE 0x10000 +#define NVRAM_MAX_GPIO_ENTRIES 32 +#define NVRAM_MAX_GPIO_VALUE_LEN 30 + +#define FLASH_MIN 0x00020000 /* Minimum flash size */ + +struct nvram_header { + u32 magic; + u32 len; + u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */ + u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */ + u32 config_ncdl; /* ncdl values for memc */ +}; + +static char nvram_buf[NVRAM_SPACE]; +static size_t nvram_len; +static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000}; + +static u32 find_nvram_size(void __iomem *end) +{ + struct nvram_header __iomem *header; + int i; + + for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) { + header = (struct nvram_header *)(end - nvram_sizes[i]); + if (header->magic == NVRAM_MAGIC) + return nvram_sizes[i]; + } + + return 0; +} + +/* Probe for NVRAM header */ +static int nvram_find_and_copy(void __iomem *iobase, u32 lim) +{ + struct nvram_header __iomem *header; + int i; + u32 off; + u32 *src, *dst; + u32 size; + + if (nvram_len) { + pr_warn("nvram already initialized\n"); + return -EEXIST; + } + + /* TODO: when nvram is on nand flash check for bad blocks first. */ + off = FLASH_MIN; + while (off <= lim) { + /* Windowed flash access */ + size = find_nvram_size(iobase + off); + if (size) { + header = (struct nvram_header *)(iobase + off - size); + goto found; + } + off <<= 1; + } + + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */ + header = (struct nvram_header *)(iobase + 4096); + if (header->magic == NVRAM_MAGIC) { + size = NVRAM_SPACE; + goto found; + } + + header = (struct nvram_header *)(iobase + 1024); + if (header->magic == NVRAM_MAGIC) { + size = NVRAM_SPACE; + goto found; + } + + pr_err("no nvram found\n"); + return -ENXIO; + +found: + src = (u32 *)header; + dst = (u32 *)nvram_buf; + for (i = 0; i < sizeof(struct nvram_header); i += 4) + *dst++ = __raw_readl(src++); + header = (struct nvram_header *)nvram_buf; + nvram_len = header->len; + if (nvram_len > size) { + pr_err("The nvram size according to the header seems to be bigger than the partition on flash\n"); + nvram_len = size; + } + if (nvram_len >= NVRAM_SPACE) { + pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", + header->len, NVRAM_SPACE - 1); + nvram_len = NVRAM_SPACE - 1; + } + /* proceed reading data after header */ + for (; i < nvram_len; i += 4) + *dst++ = readl(src++); + nvram_buf[NVRAM_SPACE - 1] = '\0'; + + return 0; +} + +/* + * On bcm47xx we need access to the NVRAM very early, so we can't use mtd + * subsystem to access flash. We can't even use platform device / driver to + * store memory offset. + * To handle this we provide following symbol. It's supposed to be called as + * soon as we get info about flash device, before any NVRAM entry is needed. + */ +int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) +{ + void __iomem *iobase; + int err; + + iobase = ioremap_nocache(base, lim); + if (!iobase) + return -ENOMEM; + + err = nvram_find_and_copy(iobase, lim); + + iounmap(iobase); + + return err; +} + +static int nvram_init(void) +{ +#ifdef CONFIG_MTD + struct mtd_info *mtd; + struct nvram_header header; + size_t bytes_read; + int err; + + mtd = get_mtd_device_nm("nvram"); + if (IS_ERR(mtd)) + return -ENODEV; + + err = mtd_read(mtd, 0, sizeof(header), &bytes_read, (uint8_t *)&header); + if (!err && header.magic == NVRAM_MAGIC && + header.len > sizeof(header)) { + nvram_len = header.len; + if (nvram_len >= NVRAM_SPACE) { + pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", + header.len, NVRAM_SPACE); + nvram_len = NVRAM_SPACE - 1; + } + + err = mtd_read(mtd, 0, nvram_len, &nvram_len, + (u8 *)nvram_buf); + return err; + } +#endif + + return -ENXIO; +} + +int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len) +{ + char *var, *value, *end, *eq; + int err; + + if (!name) + return -EINVAL; + + if (!nvram_len) { + err = nvram_init(); + if (err) + return err; + } + + /* Look for name=value and return value */ + var = &nvram_buf[sizeof(struct nvram_header)]; + end = nvram_buf + sizeof(nvram_buf); + while (var < end && *var) { + eq = strchr(var, '='); + if (!eq) + break; + value = eq + 1; + if (eq - var == strlen(name) && + strncmp(var, name, eq - var) == 0) + return snprintf(val, val_len, "%s", value); + var = value + strlen(value) + 1; + } + return -ENOENT; +} +EXPORT_SYMBOL(bcm47xx_nvram_getenv); + +int bcm47xx_nvram_gpio_pin(const char *name) +{ + int i, err; + char nvram_var[] = "gpioXX"; + char buf[NVRAM_MAX_GPIO_VALUE_LEN]; + + /* TODO: Optimize it to don't call getenv so many times */ + for (i = 0; i < NVRAM_MAX_GPIO_ENTRIES; i++) { + err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i); + if (err <= 0) + continue; + err = bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf)); + if (err <= 0) + continue; + if (!strcmp(name, buf)) + return i; + } + return -ENOENT; +} +EXPORT_SYMBOL(bcm47xx_nvram_gpio_pin); + +char *bcm47xx_nvram_get_contents(size_t *nvram_size) +{ + int err; + char *nvram; + + if (!nvram_len) { + err = nvram_init(); + if (err) + return NULL; + } + + *nvram_size = nvram_len - sizeof(struct nvram_header); + nvram = vmalloc(*nvram_size); + if (!nvram) + return NULL; + memcpy(nvram, &nvram_buf[sizeof(struct nvram_header)], *nvram_size); + + return nvram; +} +EXPORT_SYMBOL(bcm47xx_nvram_get_contents); + +MODULE_LICENSE("GPLv2"); diff --git a/target/linux/bcm53xx/files-4.1/include/linux/bcm47xx_nvram.h b/target/linux/bcm53xx/files-4.1/include/linux/bcm47xx_nvram.h new file mode 100644 index 0000000..2793652 --- /dev/null +++ b/target/linux/bcm53xx/files-4.1/include/linux/bcm47xx_nvram.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __BCM47XX_NVRAM_H +#define __BCM47XX_NVRAM_H + +#include +#include +#include + +#ifdef CONFIG_BCM47XX_NVRAM +int bcm47xx_nvram_init_from_mem(u32 base, u32 lim); +int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len); +int bcm47xx_nvram_gpio_pin(const char *name); +char *bcm47xx_nvram_get_contents(size_t *val_len); +static inline void bcm47xx_nvram_release_contents(char *nvram) +{ + vfree(nvram); +}; +#else +static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) +{ + return -ENOTSUPP; +}; +static inline int bcm47xx_nvram_getenv(const char *name, char *val, + size_t val_len) +{ + return -ENOTSUPP; +}; +static inline int bcm47xx_nvram_gpio_pin(const char *name) +{ + return -ENOTSUPP; +}; + +static inline char *bcm47xx_nvram_get_contents(size_t *val_len) +{ + return NULL; +}; + +static inline void bcm47xx_nvram_release_contents(char *nvram) +{ +}; +#endif + +#endif /* __BCM47XX_NVRAM_H */ diff --git a/target/linux/bcm53xx/files/drivers/misc/bcm47xx-sprom.c b/target/linux/bcm53xx/files/drivers/misc/bcm47xx-sprom.c new file mode 100644 index 0000000..b695f0a --- /dev/null +++ b/target/linux/bcm53xx/files/drivers/misc/bcm47xx-sprom.c @@ -0,0 +1,691 @@ +/* + * Copyright (C) 2004 Florian Schirmer + * Copyright (C) 2006 Felix Fietkau + * Copyright (C) 2006 Michael Buesch + * Copyright (C) 2010 Waldemar Brodkorb + * Copyright (C) 2010-2012 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void create_key(const char *prefix, const char *postfix, + const char *name, char *buf, int len) +{ + if (prefix && postfix) + snprintf(buf, len, "%s%s%s", prefix, name, postfix); + else if (prefix) + snprintf(buf, len, "%s%s", prefix, name); + else if (postfix) + snprintf(buf, len, "%s%s", name, postfix); + else + snprintf(buf, len, "%s", name); +} + +static int get_nvram_var(const char *prefix, const char *postfix, + const char *name, char *buf, int len, bool fallback) +{ + char key[40]; + int err; + + create_key(prefix, postfix, name, key, sizeof(key)); + + err = bcm47xx_nvram_getenv(key, buf, len); + if (fallback && err == -ENOENT && prefix) { + create_key(NULL, postfix, name, key, sizeof(key)); + err = bcm47xx_nvram_getenv(key, buf, len); + } + return err; +} + +#define NVRAM_READ_VAL(type) \ +static void nvram_read_ ## type (const char *prefix, \ + const char *postfix, const char *name, \ + type *val, type allset, bool fallback) \ +{ \ + char buf[100]; \ + int err; \ + type var; \ + \ + err = get_nvram_var(prefix, postfix, name, buf, sizeof(buf), \ + fallback); \ + if (err < 0) \ + return; \ + err = kstrto ## type(strim(buf), 0, &var); \ + if (err) { \ + pr_warn("can not parse nvram name %s%s%s with value %s got %i\n", \ + prefix, name, postfix, buf, err); \ + return; \ + } \ + if (allset && var == allset) \ + return; \ + *val = var; \ +} + +NVRAM_READ_VAL(u8) +NVRAM_READ_VAL(s8) +NVRAM_READ_VAL(u16) +NVRAM_READ_VAL(u32) + +#undef NVRAM_READ_VAL + +static void nvram_read_u32_2(const char *prefix, const char *name, + u16 *val_lo, u16 *val_hi, bool fallback) +{ + char buf[100]; + int err; + u32 val; + + err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback); + if (err < 0) + return; + err = kstrtou32(strim(buf), 0, &val); + if (err) { + pr_warn("can not parse nvram name %s%s with value %s got %i\n", + prefix, name, buf, err); + return; + } + *val_lo = (val & 0x0000FFFFU); + *val_hi = (val & 0xFFFF0000U) >> 16; +} + +static void nvram_read_leddc(const char *prefix, const char *name, + u8 *leddc_on_time, u8 *leddc_off_time, + bool fallback) +{ + char buf[100]; + int err; + u32 val; + + err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback); + if (err < 0) + return; + err = kstrtou32(strim(buf), 0, &val); + if (err) { + pr_warn("can not parse nvram name %s%s with value %s got %i\n", + prefix, name, buf, err); + return; + } + + if (val == 0xffff || val == 0xffffffff) + return; + + *leddc_on_time = val & 0xff; + *leddc_off_time = (val >> 16) & 0xff; +} + +static void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6]) +{ + if (strchr(buf, ':')) + sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], + &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4], + &macaddr[5]); + else if (strchr(buf, '-')) + sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0], + &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4], + &macaddr[5]); + else + pr_warn("Can not parse mac address: %s\n", buf); +} + +static void nvram_read_macaddr(const char *prefix, const char *name, + u8 val[6], bool fallback) +{ + char buf[100]; + int err; + + err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback); + if (err < 0) + return; + + bcm47xx_nvram_parse_macaddr(buf, val); +} + +static void nvram_read_alpha2(const char *prefix, const char *name, + char val[2], bool fallback) +{ + char buf[10]; + int err; + + err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback); + if (err < 0) + return; + if (buf[0] == '0') + return; + if (strlen(buf) > 2) { + pr_warn("alpha2 is too long %s\n", buf); + return; + } + memcpy(val, buf, 2); +} + +/* This is one-function-only macro, it uses local "sprom" variable! */ +#define ENTRY(_revmask, _type, _prefix, _name, _val, _allset, _fallback) \ + if (_revmask & BIT(sprom->revision)) \ + nvram_read_ ## _type(_prefix, NULL, _name, &sprom->_val, \ + _allset, _fallback) +/* + * Special version of filling function that can be safely called for any SPROM + * revision. For every NVRAM to SPROM mapping it contains bitmask of revisions + * for which the mapping is valid. + * It obviously requires some hexadecimal/bitmasks knowledge, but allows + * writing cleaner code (easy revisions handling). + * Note that while SPROM revision 0 was never used, we still keep BIT(0) + * reserved for it, just to keep numbering sane. + */ +static void bcm47xx_sprom_fill_auto(struct ssb_sprom *sprom, + const char *prefix, bool fallback) +{ + const char *pre = prefix; + bool fb = fallback; + + /* Broadcom extracts it for rev 8+ but it was found on 2 and 4 too */ + ENTRY(0xfffffffe, u16, pre, "devid", dev_id, 0, fallback); + + ENTRY(0xfffffffe, u16, pre, "boardrev", board_rev, 0, true); + ENTRY(0xfffffffe, u32, pre, "boardflags", boardflags, 0, fb); + ENTRY(0xfffffff0, u32, pre, "boardflags2", boardflags2, 0, fb); + ENTRY(0xfffff800, u32, pre, "boardflags3", boardflags3, 0, fb); + ENTRY(0x00000002, u16, pre, "boardflags", boardflags_lo, 0, fb); + ENTRY(0xfffffffc, u16, pre, "boardtype", board_type, 0, true); + ENTRY(0xfffffffe, u16, pre, "boardnum", board_num, 0, fb); + ENTRY(0x00000002, u8, pre, "cc", country_code, 0, fb); + ENTRY(0xfffffff8, u8, pre, "regrev", regrev, 0, fb); + + ENTRY(0xfffffffe, u8, pre, "ledbh0", gpio0, 0xff, fb); + ENTRY(0xfffffffe, u8, pre, "ledbh1", gpio1, 0xff, fb); + ENTRY(0xfffffffe, u8, pre, "ledbh2", gpio2, 0xff, fb); + ENTRY(0xfffffffe, u8, pre, "ledbh3", gpio3, 0xff, fb); + + ENTRY(0x0000070e, u16, pre, "pa0b0", pa0b0, 0, fb); + ENTRY(0x0000070e, u16, pre, "pa0b1", pa0b1, 0, fb); + ENTRY(0x0000070e, u16, pre, "pa0b2", pa0b2, 0, fb); + ENTRY(0x0000070e, u8, pre, "pa0itssit", itssi_bg, 0, fb); + ENTRY(0x0000070e, u8, pre, "pa0maxpwr", maxpwr_bg, 0, fb); + + ENTRY(0x0000070c, u8, pre, "opo", opo, 0, fb); + ENTRY(0xfffffffe, u8, pre, "aa2g", ant_available_bg, 0, fb); + ENTRY(0xfffffffe, u8, pre, "aa5g", ant_available_a, 0, fb); + ENTRY(0x000007fe, s8, pre, "ag0", antenna_gain.a0, 0, fb); + ENTRY(0x000007fe, s8, pre, "ag1", antenna_gain.a1, 0, fb); + ENTRY(0x000007f0, s8, pre, "ag2", antenna_gain.a2, 0, fb); + ENTRY(0x000007f0, s8, pre, "ag3", antenna_gain.a3, 0, fb); + + ENTRY(0x0000070e, u16, pre, "pa1b0", pa1b0, 0, fb); + ENTRY(0x0000070e, u16, pre, "pa1b1", pa1b1, 0, fb); + ENTRY(0x0000070e, u16, pre, "pa1b2", pa1b2, 0, fb); + ENTRY(0x0000070c, u16, pre, "pa1lob0", pa1lob0, 0, fb); + ENTRY(0x0000070c, u16, pre, "pa1lob1", pa1lob1, 0, fb); + ENTRY(0x0000070c, u16, pre, "pa1lob2", pa1lob2, 0, fb); + ENTRY(0x0000070c, u16, pre, "pa1hib0", pa1hib0, 0, fb); + ENTRY(0x0000070c, u16, pre, "pa1hib1", pa1hib1, 0, fb); + ENTRY(0x0000070c, u16, pre, "pa1hib2", pa1hib2, 0, fb); + ENTRY(0x0000070e, u8, pre, "pa1itssit", itssi_a, 0, fb); + ENTRY(0x0000070e, u8, pre, "pa1maxpwr", maxpwr_a, 0, fb); + ENTRY(0x0000070c, u8, pre, "pa1lomaxpwr", maxpwr_al, 0, fb); + ENTRY(0x0000070c, u8, pre, "pa1himaxpwr", maxpwr_ah, 0, fb); + + ENTRY(0x00000708, u8, pre, "bxa2g", bxa2g, 0, fb); + ENTRY(0x00000708, u8, pre, "rssisav2g", rssisav2g, 0, fb); + ENTRY(0x00000708, u8, pre, "rssismc2g", rssismc2g, 0, fb); + ENTRY(0x00000708, u8, pre, "rssismf2g", rssismf2g, 0, fb); + ENTRY(0x00000708, u8, pre, "bxa5g", bxa5g, 0, fb); + ENTRY(0x00000708, u8, pre, "rssisav5g", rssisav5g, 0, fb); + ENTRY(0x00000708, u8, pre, "rssismc5g", rssismc5g, 0, fb); + ENTRY(0x00000708, u8, pre, "rssismf5g", rssismf5g, 0, fb); + ENTRY(0x00000708, u8, pre, "tri2g", tri2g, 0, fb); + ENTRY(0x00000708, u8, pre, "tri5g", tri5g, 0, fb); + ENTRY(0x00000708, u8, pre, "tri5gl", tri5gl, 0, fb); + ENTRY(0x00000708, u8, pre, "tri5gh", tri5gh, 0, fb); + ENTRY(0x00000708, s8, pre, "rxpo2g", rxpo2g, 0, fb); + ENTRY(0x00000708, s8, pre, "rxpo5g", rxpo5g, 0, fb); + ENTRY(0xfffffff0, u8, pre, "txchain", txchain, 0xf, fb); + ENTRY(0xfffffff0, u8, pre, "rxchain", rxchain, 0xf, fb); + ENTRY(0xfffffff0, u8, pre, "antswitch", antswitch, 0xff, fb); + ENTRY(0x00000700, u8, pre, "tssipos2g", fem.ghz2.tssipos, 0, fb); + ENTRY(0x00000700, u8, pre, "extpagain2g", fem.ghz2.extpa_gain, 0, fb); + ENTRY(0x00000700, u8, pre, "pdetrange2g", fem.ghz2.pdet_range, 0, fb); + ENTRY(0x00000700, u8, pre, "triso2g", fem.ghz2.tr_iso, 0, fb); + ENTRY(0x00000700, u8, pre, "antswctl2g", fem.ghz2.antswlut, 0, fb); + ENTRY(0x00000700, u8, pre, "tssipos5g", fem.ghz5.tssipos, 0, fb); + ENTRY(0x00000700, u8, pre, "extpagain5g", fem.ghz5.extpa_gain, 0, fb); + ENTRY(0x00000700, u8, pre, "pdetrange5g", fem.ghz5.pdet_range, 0, fb); + ENTRY(0x00000700, u8, pre, "triso5g", fem.ghz5.tr_iso, 0, fb); + ENTRY(0x00000700, u8, pre, "antswctl5g", fem.ghz5.antswlut, 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid2ga0", txpid2g[0], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid2ga1", txpid2g[1], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid2ga2", txpid2g[2], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid2ga3", txpid2g[3], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5ga0", txpid5g[0], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5ga1", txpid5g[1], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5ga2", txpid5g[2], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5ga3", txpid5g[3], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5gla0", txpid5gl[0], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5gla1", txpid5gl[1], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5gla2", txpid5gl[2], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5gla3", txpid5gl[3], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5gha0", txpid5gh[0], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5gha1", txpid5gh[1], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5gha2", txpid5gh[2], 0, fb); + ENTRY(0x000000f0, u8, pre, "txpid5gha3", txpid5gh[3], 0, fb); + + ENTRY(0xffffff00, u8, pre, "tempthresh", tempthresh, 0, fb); + ENTRY(0xffffff00, u8, pre, "tempoffset", tempoffset, 0, fb); + ENTRY(0xffffff00, u16, pre, "rawtempsense", rawtempsense, 0, fb); + ENTRY(0xffffff00, u8, pre, "measpower", measpower, 0, fb); + ENTRY(0xffffff00, u8, pre, "tempsense_slope", tempsense_slope, 0, fb); + ENTRY(0xffffff00, u8, pre, "tempcorrx", tempcorrx, 0, fb); + ENTRY(0xffffff00, u8, pre, "tempsense_option", tempsense_option, 0, fb); + ENTRY(0x00000700, u8, pre, "freqoffset_corr", freqoffset_corr, 0, fb); + ENTRY(0x00000700, u8, pre, "iqcal_swp_dis", iqcal_swp_dis, 0, fb); + ENTRY(0x00000700, u8, pre, "hw_iqcal_en", hw_iqcal_en, 0, fb); + ENTRY(0x00000700, u8, pre, "elna2g", elna2g, 0, fb); + ENTRY(0x00000700, u8, pre, "elna5g", elna5g, 0, fb); + ENTRY(0xffffff00, u8, pre, "phycal_tempdelta", phycal_tempdelta, 0, fb); + ENTRY(0xffffff00, u8, pre, "temps_period", temps_period, 0, fb); + ENTRY(0xffffff00, u8, pre, "temps_hysteresis", temps_hysteresis, 0, fb); + ENTRY(0xffffff00, u8, pre, "measpower1", measpower1, 0, fb); + ENTRY(0xffffff00, u8, pre, "measpower2", measpower2, 0, fb); + + ENTRY(0x000001f0, u16, pre, "cck2gpo", cck2gpo, 0, fb); + ENTRY(0x000001f0, u32, pre, "ofdm2gpo", ofdm2gpo, 0, fb); + ENTRY(0x000001f0, u32, pre, "ofdm5gpo", ofdm5gpo, 0, fb); + ENTRY(0x000001f0, u32, pre, "ofdm5glpo", ofdm5glpo, 0, fb); + ENTRY(0x000001f0, u32, pre, "ofdm5ghpo", ofdm5ghpo, 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs2gpo0", mcs2gpo[0], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs2gpo1", mcs2gpo[1], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs2gpo2", mcs2gpo[2], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs2gpo3", mcs2gpo[3], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs2gpo4", mcs2gpo[4], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs2gpo5", mcs2gpo[5], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs2gpo6", mcs2gpo[6], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs2gpo7", mcs2gpo[7], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5gpo0", mcs5gpo[0], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5gpo1", mcs5gpo[1], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5gpo2", mcs5gpo[2], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5gpo3", mcs5gpo[3], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5gpo4", mcs5gpo[4], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5gpo5", mcs5gpo[5], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5gpo6", mcs5gpo[6], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5gpo7", mcs5gpo[7], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5glpo0", mcs5glpo[0], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5glpo1", mcs5glpo[1], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5glpo2", mcs5glpo[2], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5glpo3", mcs5glpo[3], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5glpo4", mcs5glpo[4], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5glpo5", mcs5glpo[5], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5glpo6", mcs5glpo[6], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5glpo7", mcs5glpo[7], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5ghpo0", mcs5ghpo[0], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5ghpo1", mcs5ghpo[1], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5ghpo2", mcs5ghpo[2], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5ghpo3", mcs5ghpo[3], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5ghpo4", mcs5ghpo[4], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5ghpo5", mcs5ghpo[5], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5ghpo6", mcs5ghpo[6], 0, fb); + ENTRY(0x000001f0, u16, pre, "mcs5ghpo7", mcs5ghpo[7], 0, fb); + ENTRY(0x000001f0, u16, pre, "cddpo", cddpo, 0, fb); + ENTRY(0x000001f0, u16, pre, "stbcpo", stbcpo, 0, fb); + ENTRY(0x000001f0, u16, pre, "bw40po", bw40po, 0, fb); + ENTRY(0x000001f0, u16, pre, "bwduppo", bwduppo, 0, fb); + + ENTRY(0xfffffe00, u16, pre, "cckbw202gpo", cckbw202gpo, 0, fb); + ENTRY(0xfffffe00, u16, pre, "cckbw20ul2gpo", cckbw20ul2gpo, 0, fb); + ENTRY(0x00000600, u32, pre, "legofdmbw202gpo", legofdmbw202gpo, 0, fb); + ENTRY(0x00000600, u32, pre, "legofdmbw20ul2gpo", legofdmbw20ul2gpo, 0, fb); + ENTRY(0x00000600, u32, pre, "legofdmbw205glpo", legofdmbw205glpo, 0, fb); + ENTRY(0x00000600, u32, pre, "legofdmbw20ul5glpo", legofdmbw20ul5glpo, 0, fb); + ENTRY(0x00000600, u32, pre, "legofdmbw205gmpo", legofdmbw205gmpo, 0, fb); + ENTRY(0x00000600, u32, pre, "legofdmbw20ul5gmpo", legofdmbw20ul5gmpo, 0, fb); + ENTRY(0x00000600, u32, pre, "legofdmbw205ghpo", legofdmbw205ghpo, 0, fb); + ENTRY(0x00000600, u32, pre, "legofdmbw20ul5ghpo", legofdmbw20ul5ghpo, 0, fb); + ENTRY(0xfffffe00, u32, pre, "mcsbw202gpo", mcsbw202gpo, 0, fb); + ENTRY(0x00000600, u32, pre, "mcsbw20ul2gpo", mcsbw20ul2gpo, 0, fb); + ENTRY(0xfffffe00, u32, pre, "mcsbw402gpo", mcsbw402gpo, 0, fb); + ENTRY(0xfffffe00, u32, pre, "mcsbw205glpo", mcsbw205glpo, 0, fb); + ENTRY(0x00000600, u32, pre, "mcsbw20ul5glpo", mcsbw20ul5glpo, 0, fb); + ENTRY(0xfffffe00, u32, pre, "mcsbw405glpo", mcsbw405glpo, 0, fb); + ENTRY(0xfffffe00, u32, pre, "mcsbw205gmpo", mcsbw205gmpo, 0, fb); + ENTRY(0x00000600, u32, pre, "mcsbw20ul5gmpo", mcsbw20ul5gmpo, 0, fb); + ENTRY(0xfffffe00, u32, pre, "mcsbw405gmpo", mcsbw405gmpo, 0, fb); + ENTRY(0xfffffe00, u32, pre, "mcsbw205ghpo", mcsbw205ghpo, 0, fb); + ENTRY(0x00000600, u32, pre, "mcsbw20ul5ghpo", mcsbw20ul5ghpo, 0, fb); + ENTRY(0xfffffe00, u32, pre, "mcsbw405ghpo", mcsbw405ghpo, 0, fb); + ENTRY(0x00000600, u16, pre, "mcs32po", mcs32po, 0, fb); + ENTRY(0x00000600, u16, pre, "legofdm40duppo", legofdm40duppo, 0, fb); + ENTRY(0x00000700, u8, pre, "pcieingress_war", pcieingress_war, 0, fb); + + /* TODO: rev 11 support */ + ENTRY(0x00000700, u8, pre, "rxgainerr2ga0", rxgainerr2ga[0], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr2ga1", rxgainerr2ga[1], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr2ga2", rxgainerr2ga[2], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gla0", rxgainerr5gla[0], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gla1", rxgainerr5gla[1], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gla2", rxgainerr5gla[2], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gma0", rxgainerr5gma[0], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gma1", rxgainerr5gma[1], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gma2", rxgainerr5gma[2], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gha0", rxgainerr5gha[0], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gha1", rxgainerr5gha[1], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gha2", rxgainerr5gha[2], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gua0", rxgainerr5gua[0], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gua1", rxgainerr5gua[1], 0, fb); + ENTRY(0x00000700, u8, pre, "rxgainerr5gua2", rxgainerr5gua[2], 0, fb); + + ENTRY(0xfffffe00, u8, pre, "sar2g", sar2g, 0, fb); + ENTRY(0xfffffe00, u8, pre, "sar5g", sar5g, 0, fb); + + /* TODO: rev 11 support */ + ENTRY(0x00000700, u8, pre, "noiselvl2ga0", noiselvl2ga[0], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl2ga1", noiselvl2ga[1], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl2ga2", noiselvl2ga[2], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gla0", noiselvl5gla[0], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gla1", noiselvl5gla[1], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gla2", noiselvl5gla[2], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gma0", noiselvl5gma[0], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gma1", noiselvl5gma[1], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gma2", noiselvl5gma[2], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gha0", noiselvl5gha[0], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gha1", noiselvl5gha[1], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gha2", noiselvl5gha[2], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gua0", noiselvl5gua[0], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gua1", noiselvl5gua[1], 0, fb); + ENTRY(0x00000700, u8, pre, "noiselvl5gua2", noiselvl5gua[2], 0, fb); +} +#undef ENTRY /* It's specififc, uses local variable, don't use it (again). */ + +static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom, + const char *prefix, bool fallback) +{ + char postfix[2]; + int i; + + for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) { + struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i]; + snprintf(postfix, sizeof(postfix), "%i", i); + nvram_read_u8(prefix, postfix, "maxp2ga", + &pwr_info->maxpwr_2g, 0, fallback); + nvram_read_u8(prefix, postfix, "itt2ga", + &pwr_info->itssi_2g, 0, fallback); + nvram_read_u8(prefix, postfix, "itt5ga", + &pwr_info->itssi_5g, 0, fallback); + nvram_read_u16(prefix, postfix, "pa2gw0a", + &pwr_info->pa_2g[0], 0, fallback); + nvram_read_u16(prefix, postfix, "pa2gw1a", + &pwr_info->pa_2g[1], 0, fallback); + nvram_read_u16(prefix, postfix, "pa2gw2a", + &pwr_info->pa_2g[2], 0, fallback); + nvram_read_u8(prefix, postfix, "maxp5ga", + &pwr_info->maxpwr_5g, 0, fallback); + nvram_read_u8(prefix, postfix, "maxp5gha", + &pwr_info->maxpwr_5gh, 0, fallback); + nvram_read_u8(prefix, postfix, "maxp5gla", + &pwr_info->maxpwr_5gl, 0, fallback); + nvram_read_u16(prefix, postfix, "pa5gw0a", + &pwr_info->pa_5g[0], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5gw1a", + &pwr_info->pa_5g[1], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5gw2a", + &pwr_info->pa_5g[2], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5glw0a", + &pwr_info->pa_5gl[0], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5glw1a", + &pwr_info->pa_5gl[1], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5glw2a", + &pwr_info->pa_5gl[2], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5ghw0a", + &pwr_info->pa_5gh[0], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5ghw1a", + &pwr_info->pa_5gh[1], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5ghw2a", + &pwr_info->pa_5gh[2], 0, fallback); + } +} + +static void bcm47xx_fill_sprom_path_r45(struct ssb_sprom *sprom, + const char *prefix, bool fallback) +{ + char postfix[2]; + int i; + + for (i = 0; i < ARRAY_SIZE(sprom->core_pwr_info); i++) { + struct ssb_sprom_core_pwr_info *pwr_info = &sprom->core_pwr_info[i]; + snprintf(postfix, sizeof(postfix), "%i", i); + nvram_read_u16(prefix, postfix, "pa2gw3a", + &pwr_info->pa_2g[3], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5gw3a", + &pwr_info->pa_5g[3], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5glw3a", + &pwr_info->pa_5gl[3], 0, fallback); + nvram_read_u16(prefix, postfix, "pa5ghw3a", + &pwr_info->pa_5gh[3], 0, fallback); + } +} + +static bool bcm47xx_is_valid_mac(u8 *mac) +{ + return mac && !(mac[0] == 0x00 && mac[1] == 0x90 && mac[2] == 0x4c); +} + +static int bcm47xx_increase_mac_addr(u8 *mac, u8 num) +{ + u8 *oui = mac + ETH_ALEN/2 - 1; + u8 *p = mac + ETH_ALEN - 1; + + do { + (*p) += num; + if (*p > num) + break; + p--; + num = 1; + } while (p != oui); + + if (p == oui) { + pr_err("unable to fetch mac address\n"); + return -ENOENT; + } + return 0; +} + +static int mac_addr_used = 2; + +static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, + const char *prefix, bool fallback) +{ + bool fb = fallback; + + nvram_read_macaddr(prefix, "et0macaddr", sprom->et0mac, fallback); + nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0, + fallback); + nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0, + fallback); + + nvram_read_macaddr(prefix, "et1macaddr", sprom->et1mac, fallback); + nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0, + fallback); + nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0, + fallback); + + nvram_read_macaddr(prefix, "et2macaddr", sprom->et2mac, fb); + nvram_read_u8(prefix, NULL, "et2mdcport", &sprom->et2mdcport, 0, fb); + nvram_read_u8(prefix, NULL, "et2phyaddr", &sprom->et2phyaddr, 0, fb); + + nvram_read_macaddr(prefix, "macaddr", sprom->il0mac, fallback); + nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback); + + /* The address prefix 00:90:4C is used by Broadcom in their initial + configuration. When a mac address with the prefix 00:90:4C is used + all devices from the same series are sharing the same mac address. + To prevent mac address collisions we replace them with a mac address + based on the base address. */ + if (!bcm47xx_is_valid_mac(sprom->il0mac)) { + u8 mac[6]; + + nvram_read_macaddr(NULL, "et0macaddr", mac, false); + if (bcm47xx_is_valid_mac(mac)) { + int err = bcm47xx_increase_mac_addr(mac, mac_addr_used); + + if (!err) { + ether_addr_copy(sprom->il0mac, mac); + mac_addr_used++; + } + } + } +} + +static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix, + bool fallback) +{ + nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, + &sprom->boardflags_hi, fallback); + nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo, + &sprom->boardflags2_hi, fallback); +} + +void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix, + bool fallback) +{ + bcm47xx_fill_sprom_ethernet(sprom, prefix, fallback); + bcm47xx_fill_board_data(sprom, prefix, fallback); + + nvram_read_u8(prefix, NULL, "sromrev", &sprom->revision, 0, fallback); + + /* Entries requiring custom functions */ + nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback); + if (sprom->revision >= 3) + nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time, + &sprom->leddc_off_time, fallback); + + switch (sprom->revision) { + case 4: + case 5: + bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback); + bcm47xx_fill_sprom_path_r45(sprom, prefix, fallback); + break; + case 8: + case 9: + bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback); + break; + } + + bcm47xx_sprom_fill_auto(sprom, prefix, fallback); +} + +/* + * Having many NVRAM entries for PCI devices led to repeating prefixes like + * pci/1/1/ all the time and wasting flash space. So at some point Broadcom + * decided to introduce prefixes like 0: 1: 2: etc. + * If we find e.g. devpath0=pci/2/1 or devpath0=pci/2/1/ we should use 0: + * instead of pci/2/1/. + */ +static void bcm47xx_sprom_apply_prefix_alias(char *prefix, size_t prefix_size) +{ + size_t prefix_len = strlen(prefix); + size_t short_len = prefix_len - 1; + char nvram_var[10]; + char buf[20]; + int i; + + if (prefix_len <= 0 || prefix[prefix_len - 1] != '/') + return; + + for (i = 0; i < 3; i++) { + if (snprintf(nvram_var, sizeof(nvram_var), "devpath%d", i) <= 0) + continue; + if (bcm47xx_nvram_getenv(nvram_var, buf, sizeof(buf)) < 0) + continue; + if (!strcmp(buf, prefix) || + (short_len && strlen(buf) == short_len && !strncmp(buf, prefix, short_len))) { + snprintf(prefix, prefix_size, "%d:", i); + return; + } + } +} + +/* + * This function has to be called in a very precise moment. It has to be done: + * 1) After bcma registers flash cores, so we can read NVRAM. + * 2) Before any code needs SPROM content. + * + * This can be achieved only by using bcma callback. + */ +static int bcm47xx_sprom_init(struct bcma_bus *bus, struct ssb_sprom *out) +{ + char prefix[20]; + + switch (bus->hosttype) { + case BCMA_HOSTTYPE_PCI: + snprintf(prefix, sizeof(prefix), "pci/%u/%u/", + pci_domain_nr(bus->host_pci->bus) + 1, + bus->host_pci->bus->number); + bcm47xx_sprom_apply_prefix_alias(prefix, sizeof(prefix)); + bcm47xx_fill_sprom(out, prefix, false); + break; + case BCMA_HOSTTYPE_SOC: + bcm47xx_fill_sprom(out, NULL, false); + break; + default: + pr_err("Unable to fill SPROM for given hosttype.\n"); + return -EINVAL; + } + + return 0; +}; + +static int bcm47xx_sprom_probe(struct platform_device *pdev) +{ + return bcma_arch_register_fallback_sprom(&bcm47xx_sprom_init); +} + +static const struct of_device_id bcm47xx_sprom_of_match_table[] = { + { .compatible = "brcm,bcm47xx-sprom", }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm47xx_sprom_of_match_table); + +static struct platform_driver bcm47xx_sprom_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "bcm47xx-sprom", + .of_match_table = bcm47xx_sprom_of_match_table, + /* driver unloading/unbinding currently not supported */ + .suppress_bind_attrs = true, + }, + .probe = bcm47xx_sprom_probe, +}; +module_platform_driver(bcm47xx_sprom_driver); + +MODULE_AUTHOR("Hauke Mehrtens "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/bcm53xx/files/drivers/mtd/spi-nor/bcm53xxspiflash.c b/target/linux/bcm53xx/files/drivers/mtd/spi-nor/bcm53xxspiflash.c new file mode 100644 index 0000000..954b9c5 --- /dev/null +++ b/target/linux/bcm53xx/files/drivers/mtd/spi-nor/bcm53xxspiflash.c @@ -0,0 +1,231 @@ +#include +#include +#include +#include +#include +#include +#include + +static const char * const probes[] = { "ofpart", "bcm47xxpart", NULL }; + +struct bcm53xxsf { + struct spi_device *spi; + struct mtd_info mtd; + struct spi_nor nor; +}; + +/************************************************** + * spi-nor API + **************************************************/ + +static int bcm53xxspiflash_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, + int len) +{ + struct bcm53xxsf *b53sf = nor->priv; + + return spi_write_then_read(b53sf->spi, &opcode, 1, buf, len); +} + +static int bcm53xxspiflash_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, + int len, int write_enable) +{ + struct bcm53xxsf *b53sf = nor->priv; + u8 *cmd = kzalloc(len + 1, GFP_KERNEL); + int err; + + if (!cmd) + return -ENOMEM; + + cmd[0] = opcode; + memcpy(&cmd[1], buf, len); + err = spi_write(b53sf->spi, cmd, len + 1); + + kfree(cmd); + + return err; +} + +static int bcm53xxspiflash_read(struct spi_nor *nor, loff_t from, size_t len, + size_t *retlen, u_char *buf) +{ + struct bcm53xxsf *b53sf = nor->priv; + struct spi_message m; + struct spi_transfer t[2] = { { 0 }, { 0 } }; + unsigned char cmd[5]; + int cmd_len = 0; + int err; + + spi_message_init(&m); + + cmd[cmd_len++] = SPINOR_OP_READ; + if (b53sf->mtd.size > 0x1000000) + cmd[cmd_len++] = (from & 0xFF000000) >> 24; + cmd[cmd_len++] = (from & 0x00FF0000) >> 16; + cmd[cmd_len++] = (from & 0x0000FF00) >> 8; + cmd[cmd_len++] = (from & 0x000000FF) >> 0; + + t[0].tx_buf = cmd; + t[0].len = cmd_len; + spi_message_add_tail(&t[0], &m); + + t[1].rx_buf = buf; + t[1].len = len; + spi_message_add_tail(&t[1], &m); + + err = spi_sync(b53sf->spi, &m); + if (err) + return err; + + if (retlen && m.actual_length > cmd_len) + *retlen = m.actual_length - cmd_len; + + return 0; +} + +static void bcm53xxspiflash_write(struct spi_nor *nor, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + struct bcm53xxsf *b53sf = nor->priv; + struct spi_message m; + struct spi_transfer t = { 0 }; + u8 *cmd = kzalloc(len + 5, GFP_KERNEL); + int cmd_len = 0; + int err; + + if (!cmd) + return; + + spi_message_init(&m); + + cmd[cmd_len++] = nor->program_opcode; + if (b53sf->mtd.size > 0x1000000) + cmd[cmd_len++] = (to & 0xFF000000) >> 24; + cmd[cmd_len++] = (to & 0x00FF0000) >> 16; + cmd[cmd_len++] = (to & 0x0000FF00) >> 8; + cmd[cmd_len++] = (to & 0x000000FF) >> 0; + memcpy(&cmd[cmd_len], buf, len); + + t.tx_buf = cmd; + t.len = cmd_len + len; + spi_message_add_tail(&t, &m); + + err = spi_sync(b53sf->spi, &m); + if (err) + goto out; + + if (retlen && m.actual_length > cmd_len) + *retlen += m.actual_length - cmd_len; + +out: + kfree(cmd); +} + +static int bcm53xxspiflash_erase(struct spi_nor *nor, loff_t offs) +{ + struct bcm53xxsf *b53sf = nor->priv; + unsigned char cmd[5]; + int i; + + i = 0; + cmd[i++] = nor->erase_opcode; + if (b53sf->mtd.size > 0x1000000) + cmd[i++] = (offs & 0xFF000000) >> 24; + cmd[i++] = ((offs & 0x00FF0000) >> 16); + cmd[i++] = ((offs & 0x0000FF00) >> 8); + cmd[i++] = ((offs & 0x000000FF) >> 0); + + return spi_write(b53sf->spi, cmd, i); +} + +static const char *bcm53xxspiflash_chip_name(struct spi_nor *nor) +{ + struct bcm53xxsf *b53sf = nor->priv; + struct device *dev = &b53sf->spi->dev; + unsigned char cmd[4]; + unsigned char resp[2]; + int err; + + /* SST and Winbond/NexFlash specific command */ + cmd[0] = 0x90; /* Read Manufacturer / Device ID */ + cmd[1] = 0; + cmd[2] = 0; + cmd[3] = 0; + err = spi_write_then_read(b53sf->spi, cmd, 4, resp, 2); + if (err < 0) { + dev_err(dev, "error reading SPI flash id\n"); + return ERR_PTR(-EBUSY); + } + switch (resp[0]) { + case 0xef: /* Winbond/NexFlash */ + switch (resp[1]) { + case 0x17: + return "w25q128"; + } + dev_err(dev, "Unknown Winbond/NexFlash flash: %02X %02X\n", + resp[0], resp[1]); + return NULL; + } + + /* TODO: Try more ID commands */ + + return NULL; +} + +/************************************************** + * SPI driver + **************************************************/ + +static int bcm53xxspiflash_probe(struct spi_device *spi) +{ + struct mtd_part_parser_data parser_data = {}; + struct bcm53xxsf *b53sf; + struct spi_nor *nor; + int err; + + b53sf = devm_kzalloc(&spi->dev, sizeof(*b53sf), GFP_KERNEL); + if (!b53sf) + return -ENOMEM; + spi_set_drvdata(spi, b53sf); + + nor = &b53sf->nor; + b53sf->spi = spi; + b53sf->mtd.priv = &b53sf->nor; + + nor->mtd = &b53sf->mtd; + nor->dev = &spi->dev; + nor->read_reg = bcm53xxspiflash_read_reg; + nor->write_reg = bcm53xxspiflash_write_reg; + nor->read = bcm53xxspiflash_read; + nor->write = bcm53xxspiflash_write; + nor->erase = bcm53xxspiflash_erase; + nor->priv = b53sf; + + err = spi_nor_scan(&b53sf->nor, bcm53xxspiflash_chip_name(nor), + SPI_NOR_NORMAL); + if (err) + return err; + + parser_data.of_node = spi->master->dev.parent->of_node; + err = mtd_device_parse_register(&b53sf->mtd, probes, &parser_data, + NULL, 0); + if (err) + return err; + + return 0; +} + +static int bcm53xxspiflash_remove(struct spi_device *spi) +{ + return 0; +} + +static struct spi_driver bcm53xxspiflash_driver = { + .driver = { + .name = "bcm53xxspiflash", + .owner = THIS_MODULE, + }, + .probe = bcm53xxspiflash_probe, + .remove = bcm53xxspiflash_remove, +}; + +module_spi_driver(bcm53xxspiflash_driver); diff --git a/target/linux/bcm53xx/image/Makefile b/target/linux/bcm53xx/image/Makefile new file mode 100644 index 0000000..c9987dd --- /dev/null +++ b/target/linux/bcm53xx/image/Makefile @@ -0,0 +1,149 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Image/Prepare + $(CP) $(DTS_DIR)/*.dtb $(KDIR)/ + + rm -f $(KDIR)/fs_mark + echo -ne '\xde\xad\xc0\xde' > $(KDIR)/fs_mark + $(call prepare_generic_squashfs,$(KDIR)/fs_mark) + + # For UBI we want only one extra block + rm -f $(KDIR)/ubi_mark + echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark + + $(CP) ./ubinize.cfg $(KDIR) +endef + +define Build/append-dtb + cat $(KDIR)/$(DT).dtb >> $@ +endef + +define Build/lzma-d16 + $(STAGING_DIR_HOST)/bin/lzma e $@ -d16 $(1) $@.new + @mv $@.new $@ +endef + +define Build/mkfs/squashfs + ( cd $(KDIR); $(STAGING_DIR_HOST)/bin/ubinize -p 128KiB -m 2048 -o $(KDIR)/root-block-0x20000-min-0x800.ubi ubinize.cfg ) +endef + +define Build/trx-serial + $(STAGING_DIR_HOST)/bin/trx \ + -o $@ \ + -f $(word 1,$^) -a 1024 \ + -f $(KDIR)/root.squashfs -a 0x10000 -A $(KDIR)/fs_mark +endef + +define Build/trx-nand + # kernel: always use 4 MiB (-28 B or TRX header) to allow upgrades even + # if it grows up between releases + # root: UBI with one extra block containing UBI mark to trigger erasing + # rest of partition + $(STAGING_DIR_HOST)/bin/trx \ + -o $@ \ + -m 33554432 \ + -f $(word 1,$^) -a 0x20000 -b 0x400000 \ + -f $(KDIR)/root-block-0x20000-min-0x800.ubi \ + -A $(KDIR)/ubi_mark -a 0x20000 +endef + +define Build/asus-trx + $(STAGING_DIR_HOST)/bin/asustrx \ + -p $(PRODUCTID) -i $@ -o $@.new + mv $@.new $@ +endef + +DEVICE_VARS += DT PRODUCTID NETGEAR_BOARD_ID NETGEAR_REGION + +define Device/Default + # .dtb files are prefixed by SoC type, e.g. bcm4708- which is not included in device/image names + # extract the full dtb name based on the device info + DT := $(patsubst %.dtb,%,$(notdir $(wildcard $(if $(IB),$(KDIR),$(DTS_DIR))/*-$(1).dtb))) + KERNEL := kernel-bin | append-dtb | lzma-d16 + FILESYSTEMS := squashfs + KERNEL_NAME := zImage + IMAGE_NAME = $$(IMAGE_PREFIX)-$$(1).$$(2) + IMAGES := trx + IMAGE/trx := trx-nand +endef + +define Device/asus + IMAGES := trx + IMAGE/trx := trx-nand | asus-trx +endef + +define AsusDevice + define Device/asus-$(1) + $$(Device/asus) + PRODUCTID := $(2) + endef + TARGET_DEVICES += asus-$(1) +endef + +define Device/linksys + IMAGES := trx + IMAGE/trx := trx-nand +endef + +define LinksysDevice + define Device/linksys-$(1) + $$(Device/linksys) + endef + TARGET_DEVICES += linksys-$(1) +endef + +define Device/netgear + IMAGES := chk + IMAGE/chk := trx-nand | netgear-chk + NETGEAR_REGION := 1 +endef + +define NetgearDevice + define Device/netgear-$(1) + $$(Device/netgear) + NETGEAR_BOARD_ID := $(2) + endef + TARGET_DEVICES += netgear-$(1) +endef + +define Device/netgear-r6250 + $(Device/netgear) + NETGEAR_BOARD_ID := U12H245T00_NETGEAR +endef + +define Device/netgear-r6300-v2 + $(Device/netgear) + NETGEAR_BOARD_ID := U12H240T00_NETGEAR +endef + +define Device/netgear-r8000 + $(Device/netgear) + NETGEAR_BOARD_ID := U12H315T00_NETGEAR +endef + +define Device/smartrg-sr400ac + IMAGES := trx + IMAGE/trx := trx-serial +endef + +TARGET_DEVICES += \ + buffalo-wzr-1750dhp buffalo-wzr-600dhp2 buffalo-wzr-900dhp \ + buffalo-wxr-1900dhp \ + netgear-r6250 netgear-r6300-v2 netgear-r8000 \ + smartrg-sr400ac + +$(eval $(call AsusDevice,rt-ac56u,RT-AC56U)) +$(eval $(call AsusDevice,rt-ac68u,RT-AC68U)) +$(eval $(call AsusDevice,rt-ac87u,RT-AC87U)) +$(eval $(call AsusDevice,rt-n18u,RT-N18U)) +$(eval $(call LinksysDevice,ea6300-v1)) +$(eval $(call NetgearDevice,r7000,U12H270T00_NETGEAR)) + +$(eval $(call BuildImage)) diff --git a/target/linux/bcm53xx/image/ubinize.cfg b/target/linux/bcm53xx/image/ubinize.cfg new file mode 100644 index 0000000..a4f2f09 --- /dev/null +++ b/target/linux/bcm53xx/image/ubinize.cfg @@ -0,0 +1,24 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.squashfs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs + +[rootfs_data] +# Volume mode (other option is static) +mode=ubi +# Volume ID in UBI image +vol_id=1 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs_data +# Autoresize volume at first mount +vol_flags=autoresize +vol_size=1MiB diff --git a/target/linux/bcm53xx/patches-4.1/030-PCI-iproc-Allow-override-of-device-tree-IRQ-mapping-.patch b/target/linux/bcm53xx/patches-4.1/030-PCI-iproc-Allow-override-of-device-tree-IRQ-mapping-.patch new file mode 100644 index 0000000..9050f72 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/030-PCI-iproc-Allow-override-of-device-tree-IRQ-mapping-.patch @@ -0,0 +1,53 @@ +From c1e02ceaf5739d32f092ac07bf886a0281ec40b1 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Tue, 12 May 2015 23:23:00 +0200 +Subject: [PATCH 1/2] PCI: iproc: Allow override of device tree IRQ mapping + function + +The iProc core PCIe driver defaults to using of_irq_parse_and_map_pci() for +IRQ mapping. Add iproc_pcie.map_irq so bus interfaces that don't use +device tree can override this by supplying their own IRQ mapping function. + +[bhelgaas: changelog] +Posting: http://lkml.kernel.org/r/1431465781-10753-1-git-send-email-hauke@hauke-m.de +Signed-off-by: Hauke Mehrtens +Signed-off-by: Bjorn Helgaas +Reviewed-by: Ray Jui +--- + drivers/pci/host/pcie-iproc-platform.c | 2 ++ + drivers/pci/host/pcie-iproc.c | 2 +- + drivers/pci/host/pcie-iproc.h | 1 + + 3 files changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/pci/host/pcie-iproc-platform.c ++++ b/drivers/pci/host/pcie-iproc-platform.c +@@ -71,6 +71,8 @@ static int iproc_pcie_pltfm_probe(struct + + pcie->resources = &res; + ++ pcie->map_irq = of_irq_parse_and_map_pci; ++ + ret = iproc_pcie_setup(pcie); + if (ret) { + dev_err(pcie->dev, "PCIe controller setup failed\n"); +--- a/drivers/pci/host/pcie-iproc.c ++++ b/drivers/pci/host/pcie-iproc.c +@@ -229,7 +229,7 @@ int iproc_pcie_setup(struct iproc_pcie * + + pci_scan_child_bus(bus); + pci_assign_unassigned_bus_resources(bus); +- pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); ++ pci_fixup_irqs(pci_common_swizzle, pcie->map_irq); + pci_bus_add_devices(bus); + + return 0; +--- a/drivers/pci/host/pcie-iproc.h ++++ b/drivers/pci/host/pcie-iproc.h +@@ -34,6 +34,7 @@ struct iproc_pcie { + struct pci_bus *root_bus; + struct phy *phy; + int irqs[IPROC_PCIE_MAX_NUM_IRQS]; ++ int (*map_irq)(const struct pci_dev *, u8, u8); + }; + + int iproc_pcie_setup(struct iproc_pcie *pcie); diff --git a/target/linux/bcm53xx/patches-4.1/031-PCI-iproc-Add-BCMA-PCIe-driver.patch b/target/linux/bcm53xx/patches-4.1/031-PCI-iproc-Add-BCMA-PCIe-driver.patch new file mode 100644 index 0000000..a850baf --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/031-PCI-iproc-Add-BCMA-PCIe-driver.patch @@ -0,0 +1,177 @@ +From 4785ffbdc9b52e308e43b9e2dcc1dca44f056d76 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Tue, 12 May 2015 23:23:01 +0200 +Subject: [PATCH 2/2] PCI: iproc: Add BCMA PCIe driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This driver adds support for the PCIe 2.0 controller found on the BCMA bus. +This controller can be found on (mostly) all Broadcom BCM470X / BCM5301X +ARM SoCs. + +The driver found in the Broadcom SDK does some more stuff, like setting up +some DMA memory areas, chaining MPS and MRRS to 512 and also some PHY +changes like "improving" the PCIe jitter and doing some special +initialization for the 3rd PCIe port. + +This was tested on a bcm4708 board with 2 PCIe ports and wireless cards +connected to them. + +PCI_DOMAINS is needed by this driver, because normally there is more than +one PCIe controller and without PCI_DOMAINS only the first controller gets +registered. This controller gets 6 IRQs; the last one is trigged by all +IRQ events. + +[bhelgaas: fix "GPLv2" MODULE_LICENSE typo] +Signed-off-by: Hauke Mehrtens +Signed-off-by: Bjorn Helgaas +Acked-by: RafaÅ‚ MiÅ‚ecki +Acked-by: Ray Jui +--- + drivers/pci/host/Kconfig | 11 ++++ + drivers/pci/host/Makefile | 1 + + drivers/pci/host/pcie-iproc-bcma.c | 112 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 124 insertions(+) + create mode 100644 drivers/pci/host/pcie-iproc-bcma.c + +--- a/drivers/pci/host/Kconfig ++++ b/drivers/pci/host/Kconfig +@@ -125,4 +125,15 @@ config PCIE_IPROC_PLATFORM + Say Y here if you want to use the Broadcom iProc PCIe controller + through the generic platform bus interface + ++config PCIE_IPROC_BCMA ++ bool "Broadcom iProc PCIe BCMA bus driver" ++ depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST) ++ select PCIE_IPROC ++ select BCMA ++ select PCI_DOMAINS ++ default ARCH_BCM_5301X ++ help ++ Say Y here if you want to use the Broadcom iProc PCIe controller ++ through the BCMA bus interface ++ + endmenu +--- a/drivers/pci/host/Makefile ++++ b/drivers/pci/host/Makefile +@@ -15,3 +15,4 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-laye + obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o + obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o + obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o ++obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o +--- /dev/null ++++ b/drivers/pci/host/pcie-iproc-bcma.c +@@ -0,0 +1,112 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * Copyright (C) 2015 Hauke Mehrtens ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-iproc.h" ++ ++ ++/* NS: CLASS field is R/O, and set to wrong 0x200 value */ ++static void bcma_pcie2_fixup_class(struct pci_dev *dev) ++{ ++ dev->class = PCI_CLASS_BRIDGE_PCI << 8; ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8011, bcma_pcie2_fixup_class); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8012, bcma_pcie2_fixup_class); ++ ++static int iproc_pcie_bcma_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ struct pci_sys_data *sys = dev->sysdata; ++ struct iproc_pcie *pcie = sys->private_data; ++ struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); ++ ++ return bcma_core_irq(bdev, 5); ++} ++ ++static int iproc_pcie_bcma_probe(struct bcma_device *bdev) ++{ ++ struct iproc_pcie *pcie; ++ LIST_HEAD(res); ++ struct resource res_mem; ++ int ret; ++ ++ pcie = devm_kzalloc(&bdev->dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) ++ return -ENOMEM; ++ ++ pcie->dev = &bdev->dev; ++ bcma_set_drvdata(bdev, pcie); ++ ++ pcie->base = bdev->io_addr; ++ ++ res_mem.start = bdev->addr_s[0]; ++ res_mem.end = bdev->addr_s[0] + SZ_128M - 1; ++ res_mem.name = "PCIe MEM space"; ++ res_mem.flags = IORESOURCE_MEM; ++ pci_add_resource(&res, &res_mem); ++ ++ pcie->resources = &res; ++ ++ pcie->map_irq = iproc_pcie_bcma_map_irq; ++ ++ ret = iproc_pcie_setup(pcie); ++ if (ret) { ++ dev_err(pcie->dev, "PCIe controller setup failed\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void iproc_pcie_bcma_remove(struct bcma_device *bdev) ++{ ++ struct iproc_pcie *pcie = bcma_get_drvdata(bdev); ++ ++ iproc_pcie_remove(pcie); ++} ++ ++static const struct bcma_device_id iproc_pcie_bcma_table[] = { ++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_PCIEG2, BCMA_ANY_REV, BCMA_ANY_CLASS), ++ {}, ++}; ++MODULE_DEVICE_TABLE(bcma, iproc_pcie_bcma_table); ++ ++static struct bcma_driver iproc_pcie_bcma_driver = { ++ .name = KBUILD_MODNAME, ++ .id_table = iproc_pcie_bcma_table, ++ .probe = iproc_pcie_bcma_probe, ++ .remove = iproc_pcie_bcma_remove, ++}; ++ ++static int __init iproc_pcie_bcma_init(void) ++{ ++ return bcma_driver_register(&iproc_pcie_bcma_driver); ++} ++module_init(iproc_pcie_bcma_init); ++ ++static void __exit iproc_pcie_bcma_exit(void) ++{ ++ bcma_driver_unregister(&iproc_pcie_bcma_driver); ++} ++module_exit(iproc_pcie_bcma_exit); ++ ++MODULE_AUTHOR("Hauke Mehrtens"); ++MODULE_DESCRIPTION("Broadcom iProc PCIe BCMA driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/bcm53xx/patches-4.1/032-PCI-iproc-Directly-add-PCI-resources.patch b/target/linux/bcm53xx/patches-4.1/032-PCI-iproc-Directly-add-PCI-resources.patch new file mode 100644 index 0000000..09d8226 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/032-PCI-iproc-Directly-add-PCI-resources.patch @@ -0,0 +1,90 @@ +From 18c4342aa56d70176eea85021e6fe8f6f8f39c7b Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 24 May 2015 22:37:02 +0200 +Subject: [PATCH 1/2] PCI: iproc: Directly add PCI resources + +The struct iproc_pcie.resources member was pointing to a stack variable and +is invalid after the registration function returned. + +Remove this pointer and add a parameter to the function. + +Tested-by: Ray Jui +Signed-off-by: Hauke Mehrtens +Signed-off-by: Bjorn Helgaas +Reviewed-by: Ray Jui +--- + drivers/pci/host/pcie-iproc-bcma.c | 4 +--- + drivers/pci/host/pcie-iproc-platform.c | 4 +--- + drivers/pci/host/pcie-iproc.c | 4 ++-- + drivers/pci/host/pcie-iproc.h | 3 +-- + 4 files changed, 5 insertions(+), 10 deletions(-) + +--- a/drivers/pci/host/pcie-iproc-bcma.c ++++ b/drivers/pci/host/pcie-iproc-bcma.c +@@ -62,11 +62,9 @@ static int iproc_pcie_bcma_probe(struct + res_mem.flags = IORESOURCE_MEM; + pci_add_resource(&res, &res_mem); + +- pcie->resources = &res; +- + pcie->map_irq = iproc_pcie_bcma_map_irq; + +- ret = iproc_pcie_setup(pcie); ++ ret = iproc_pcie_setup(pcie, &res); + if (ret) { + dev_err(pcie->dev, "PCIe controller setup failed\n"); + return ret; +--- a/drivers/pci/host/pcie-iproc-platform.c ++++ b/drivers/pci/host/pcie-iproc-platform.c +@@ -69,11 +69,9 @@ static int iproc_pcie_pltfm_probe(struct + return ret; + } + +- pcie->resources = &res; +- + pcie->map_irq = of_irq_parse_and_map_pci; + +- ret = iproc_pcie_setup(pcie); ++ ret = iproc_pcie_setup(pcie, &res); + if (ret) { + dev_err(pcie->dev, "PCIe controller setup failed\n"); + return ret; +--- a/drivers/pci/host/pcie-iproc.c ++++ b/drivers/pci/host/pcie-iproc.c +@@ -183,7 +183,7 @@ static void iproc_pcie_enable(struct ipr + writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN); + } + +-int iproc_pcie_setup(struct iproc_pcie *pcie) ++int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res) + { + int ret; + struct pci_bus *bus; +@@ -211,7 +211,7 @@ int iproc_pcie_setup(struct iproc_pcie * + pcie->sysdata.private_data = pcie; + + bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, +- &pcie->sysdata, pcie->resources); ++ &pcie->sysdata, res); + if (!bus) { + dev_err(pcie->dev, "unable to create PCI root bus\n"); + ret = -ENOMEM; +--- a/drivers/pci/host/pcie-iproc.h ++++ b/drivers/pci/host/pcie-iproc.h +@@ -29,7 +29,6 @@ + struct iproc_pcie { + struct device *dev; + void __iomem *base; +- struct list_head *resources; + struct pci_sys_data sysdata; + struct pci_bus *root_bus; + struct phy *phy; +@@ -37,7 +36,7 @@ struct iproc_pcie { + int (*map_irq)(const struct pci_dev *, u8, u8); + }; + +-int iproc_pcie_setup(struct iproc_pcie *pcie); ++int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res); + int iproc_pcie_remove(struct iproc_pcie *pcie); + + #endif /* _PCIE_IPROC_H */ diff --git a/target/linux/bcm53xx/patches-4.1/033-PCI-iproc-Free-resource-list-after-registration.patch b/target/linux/bcm53xx/patches-4.1/033-PCI-iproc-Free-resource-list-after-registration.patch new file mode 100644 index 0000000..bbd3164 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/033-PCI-iproc-Free-resource-list-after-registration.patch @@ -0,0 +1,57 @@ +From ef07991a95de76b07594448c3521361831ec2cfe Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 24 May 2015 22:37:03 +0200 +Subject: [PATCH 2/2] PCI: iproc: Free resource list after registration + +The resource list is only used in the setup process and was never freed. +pci_add_resource() allocates a memory area to store the list item. + +Fix the memory leak. + +Tested-by: Ray Jui +Signed-off-by: Hauke Mehrtens +Signed-off-by: Bjorn Helgaas +Reviewed-by: Ray Jui +--- + drivers/pci/host/pcie-iproc-bcma.c | 8 ++++---- + drivers/pci/host/pcie-iproc-platform.c | 8 ++++---- + 2 files changed, 8 insertions(+), 8 deletions(-) + +--- a/drivers/pci/host/pcie-iproc-bcma.c ++++ b/drivers/pci/host/pcie-iproc-bcma.c +@@ -65,12 +65,12 @@ static int iproc_pcie_bcma_probe(struct + pcie->map_irq = iproc_pcie_bcma_map_irq; + + ret = iproc_pcie_setup(pcie, &res); +- if (ret) { ++ if (ret) + dev_err(pcie->dev, "PCIe controller setup failed\n"); +- return ret; +- } + +- return 0; ++ pci_free_resource_list(&res); ++ ++ return ret; + } + + static void iproc_pcie_bcma_remove(struct bcma_device *bdev) +--- a/drivers/pci/host/pcie-iproc-platform.c ++++ b/drivers/pci/host/pcie-iproc-platform.c +@@ -72,12 +72,12 @@ static int iproc_pcie_pltfm_probe(struct + pcie->map_irq = of_irq_parse_and_map_pci; + + ret = iproc_pcie_setup(pcie, &res); +- if (ret) { ++ if (ret) + dev_err(pcie->dev, "PCIe controller setup failed\n"); +- return ret; +- } + +- return 0; ++ pci_free_resource_list(&res); ++ ++ return ret; + } + + static int iproc_pcie_pltfm_remove(struct platform_device *pdev) diff --git a/target/linux/bcm53xx/patches-4.1/058-ARM-BCM5301X-Add-USB-LED-for-Buffalo-WZR-1750DHP.patch b/target/linux/bcm53xx/patches-4.1/058-ARM-BCM5301X-Add-USB-LED-for-Buffalo-WZR-1750DHP.patch new file mode 100644 index 0000000..290ea0a --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/058-ARM-BCM5301X-Add-USB-LED-for-Buffalo-WZR-1750DHP.patch @@ -0,0 +1,26 @@ +From 35ad0e50bd6683c6699586e3bd5045f0695586d9 Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Wed, 13 May 2015 09:10:51 +0200 +Subject: [PATCH] ARM: BCM5301X: Add USB LED for Buffalo WZR-1750DHP + +Signed-off-by: Felix Fietkau +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -47,6 +47,12 @@ + leds { + compatible = "gpio-leds"; + ++ usb { ++ label = "bcm53xx:blue:usb"; ++ gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ + power0 { + label = "bcm53xx:red:power"; + gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; diff --git a/target/linux/bcm53xx/patches-4.1/059-ARM-BCM5301X-Add-DT-for-Buffalo-WXR-1900DHP.patch b/target/linux/bcm53xx/patches-4.1/059-ARM-BCM5301X-Add-DT-for-Buffalo-WXR-1900DHP.patch new file mode 100644 index 0000000..e16d39b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/059-ARM-BCM5301X-Add-DT-for-Buffalo-WXR-1900DHP.patch @@ -0,0 +1,157 @@ +From 35eecd10ee57b9d4f31e12598296b235ed2b34ae Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Wed, 13 May 2015 09:10:52 +0200 +Subject: [PATCH] ARM: BCM5301X: Add DT for Buffalo WXR-1900DHP +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Felix Fietkau +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 127 ++++++++++++++++++++++ + 2 files changed, 128 insertions(+) + create mode 100644 arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm47081-asus-rt-n18u.dtb \ + bcm47081-buffalo-wzr-600dhp2.dtb \ + bcm47081-buffalo-wzr-900dhp.dtb \ ++ bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-netgear-r8000.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ + bcm963138dvt.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -0,0 +1,127 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Buffalo WXR-1900DHP ++ * ++ * Copyright (C) 2015 Felix Fietkau ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ compatible = "buffalo,wxr-1900dhp", "brcm,bcm4709", "brcm,bcm4708"; ++ model = "Buffalo WXR-1900DHP"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ usb { ++ label = "bcm53xx:green:usb"; ++ gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ power-amber { ++ label = "bcm53xx:amber:power"; ++ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ power-white { ++ label = "bcm53xx:white:power"; ++ gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ router-amber { ++ label = "bcm53xx:amber:router"; ++ gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ router-white { ++ label = "bcm53xx:white:router"; ++ gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wan-amber { ++ label = "bcm53xx:amber:wan"; ++ gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wan-white { ++ label = "bcm53xx:white:wan"; ++ gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wireless-amber { ++ label = "bcm53xx:amber:wireless"; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wireless-white { ++ label = "bcm53xx:white:wireless"; ++ gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ power { ++ label = "Power"; ++ linux,code = ; ++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ++ }; ++ ++ aoss { ++ label = "AOSS"; ++ linux,code = ; ++ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; ++ }; ++ ++ /* Commit mode set by switch? */ ++ mode { ++ label = "Mode"; ++ linux,code = ; ++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ++ }; ++ ++ /* Switch: AP mode */ ++ sw_ap { ++ label = "AP"; ++ linux,code = ; ++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; ++ }; ++ ++ eject { ++ label = "USB eject"; ++ linux,code = ; ++ gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/060-ARM-BCM5301X-Add-DT-for-SmartRG-SR400ac.patch b/target/linux/bcm53xx/patches-4.1/060-ARM-BCM5301X-Add-DT-for-SmartRG-SR400ac.patch new file mode 100644 index 0000000..dafae7b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/060-ARM-BCM5301X-Add-DT-for-SmartRG-SR400ac.patch @@ -0,0 +1,148 @@ +From 691917f20cae813d242f7123a4dc97e7d48e6ff1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 13 May 2015 09:10:53 +0200 +Subject: [PATCH] ARM: BCM5301X: Add DT for SmartRG SR400ac +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 119 ++++++++++++++++++++++++++ + 2 files changed, 120 insertions(+) + create mode 100644 arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-luxul-xwc-1000.dtb \ + bcm4708-netgear-r6250.dtb \ + bcm4708-netgear-r6300-v2.dtb \ ++ bcm4708-smartrg-sr400ac.dtb \ + bcm47081-asus-rt-n18u.dtb \ + bcm47081-buffalo-wzr-600dhp2.dtb \ + bcm47081-buffalo-wzr-900dhp.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -0,0 +1,119 @@ ++/* ++ * Broadcom BCM470X / BCM5301X arm platform code. ++ * DTS for SmartRG SR400ac ++ * ++ * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ compatible = "smartrg,sr400ac", "brcm,bcm4708"; ++ model = "SmartRG SR400ac"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ power-white { ++ label = "bcm53xx:white:power"; ++ gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ power-amber { ++ label = "bcm53xx:amber:power"; ++ gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb2 { ++ label = "bcm53xx:white:usb2"; ++ gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb3-white { ++ label = "bcm53xx:white:usb3"; ++ gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb3-green { ++ label = "bcm53xx:green:usb3"; ++ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wps { ++ label = "bcm53xx:white:wps"; ++ gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ status-red { ++ label = "bcm53xx:red:status"; ++ gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ status-green { ++ label = "bcm53xx:green:status"; ++ gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ status-blue { ++ label = "bcm53xx:blue:status"; ++ gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wan-white { ++ label = "bcm53xx:white:wan"; ++ gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wan-red { ++ label = "bcm53xx:red:wan"; ++ gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rfkill { ++ label = "WiFi"; ++ linux,code = ; ++ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/061-ARM-BCM5301X-Add-DT-for-Asus-RT-AC68U.patch b/target/linux/bcm53xx/patches-4.1/061-ARM-BCM5301X-Add-DT-for-Asus-RT-AC68U.patch new file mode 100644 index 0000000..02e644e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/061-ARM-BCM5301X-Add-DT-for-Asus-RT-AC68U.patch @@ -0,0 +1,112 @@ +From b5f350c790ae6aaf3dda5a825d7e3fdeed731164 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sat, 28 Mar 2015 15:01:38 +0100 +Subject: [PATCH] ARM: BCM5301X: Add DT for Asus RT-AC68U +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 83 +++++++++++++++++++++++++++++ + 2 files changed, 84 insertions(+) + create mode 100644 arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ + bcm2835-rpi-b.dtb \ + bcm2835-rpi-b-plus.dtb + dtb-$(CONFIG_ARCH_BCM_5301X) += \ ++ bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-luxul-xwc-1000.dtb \ + bcm4708-netgear-r6250.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -0,0 +1,83 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Asus RT-AC68U ++ * ++ * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ compatible = "asus,rt-ac68u", "brcm,bcm4708"; ++ model = "Asus RT-AC68U (BCM4708)"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ usb2 { ++ label = "bcm53xx:blue:usb2"; ++ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ power { ++ label = "bcm53xx:blue:power"; ++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ logo { ++ label = "bcm53xx:white:logo"; ++ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ usb3 { ++ label = "bcm53xx:blue:usb3"; ++ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ brightness { ++ label = "Backlight"; ++ linux,code = ; ++ gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ++ }; ++ ++ rfkill { ++ label = "WiFi"; ++ linux,code = ; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/062-ARM-BCM5301X-Add-DT-for-Asus-RT-AC56U.patch b/target/linux/bcm53xx/patches-4.1/062-ARM-BCM5301X-Add-DT-for-Asus-RT-AC56U.patch new file mode 100644 index 0000000..e72835b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/062-ARM-BCM5301X-Add-DT-for-Asus-RT-AC56U.patch @@ -0,0 +1,125 @@ +From 16dc3bac722252a10e396546f44135ae1b6a7ff3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 31 Mar 2015 17:29:18 +0200 +Subject: [PATCH] ARM: BCM5301X: Add DT for Asus RT-AC56U +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 96 +++++++++++++++++++++++++++++ + 2 files changed, 97 insertions(+) + create mode 100644 arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ + bcm2835-rpi-b.dtb \ + bcm2835-rpi-b-plus.dtb + dtb-$(CONFIG_ARCH_BCM_5301X) += \ ++ bcm4708-asus-rt-ac56u.dtb \ + bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-luxul-xwc-1000.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -0,0 +1,96 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Asus RT-AC56U ++ * ++ * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ compatible = "asus,rt-ac56u", "brcm,bcm4708"; ++ model = "Asus RT-AC56U (BCM4708)"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ usb3 { ++ label = "bcm53xx:blue:usb3"; ++ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wan { ++ label = "bcm53xx:blue:wan"; ++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ lan { ++ label = "bcm53xx:blue:lan"; ++ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ power { ++ label = "bcm53xx:blue:power"; ++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ all { ++ label = "bcm53xx:blue:all"; ++ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ 2ghz { ++ label = "bcm53xx:blue:2ghz"; ++ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ ++ usb2 { ++ label = "bcm53xx:blue:usb2"; ++ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rfkill { ++ label = "WiFi"; ++ linux,code = ; ++ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/063-ARM-BCM5301X-Ignore-another-BCM4709-specific-fault-c.patch b/target/linux/bcm53xx/patches-4.1/063-ARM-BCM5301X-Ignore-another-BCM4709-specific-fault-c.patch new file mode 100644 index 0000000..8716a0d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/063-ARM-BCM5301X-Ignore-another-BCM4709-specific-fault-c.patch @@ -0,0 +1,41 @@ +From 7eb68a2a0519a77b93184c695d4d293c92dc2286 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 11 Feb 2015 16:40:58 +0100 +Subject: [PATCH] ARM: BCM5301X: Ignore another (BCM4709 specific) fault code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Broadcom ARM devices seem to generate some fault once per boot. We +already have an ignoring handler for BCM4707/BCM4708, but BCM4709 +generates different code. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Florian Fainelli +--- + arch/arm/mach-bcm/bcm_5301x.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/arch/arm/mach-bcm/bcm_5301x.c ++++ b/arch/arm/mach-bcm/bcm_5301x.c +@@ -18,15 +18,16 @@ static bool first_fault = true; + static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) + { +- if (fsr == 0x1c06 && first_fault) { ++ if ((fsr == 0x1406 || fsr == 0x1c06) && first_fault) { + first_fault = false; + + /* +- * These faults with code 0x1c06 happens for no good reason, +- * possibly left over from the CFE boot loader. ++ * These faults with codes 0x1406 (BCM4709) or 0x1c06 happens ++ * for no good reason, possibly left over from the CFE boot ++ * loader. + */ + pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n", +- addr, fsr); ++ addr, fsr); + + /* Returning non-zero causes fault display and panic */ + return 0; diff --git a/target/linux/bcm53xx/patches-4.1/064-ARM-BCM5301X-add-NAND-flash-chip-description.patch b/target/linux/bcm53xx/patches-4.1/064-ARM-BCM5301X-add-NAND-flash-chip-description.patch new file mode 100644 index 0000000..aa99f37 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/064-ARM-BCM5301X-add-NAND-flash-chip-description.patch @@ -0,0 +1,210 @@ +From 9faa5960eef3204cae6637b530f5e23e53b5a9ef Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Fri, 29 May 2015 23:39:47 +0200 +Subject: [PATCH] ARM: BCM5301X: add NAND flash chip description + +This adds the NAND flash chip description for a standard chip found +connected to this SoC. This makes use of generic Broadcom NAND driver +with the iProc interface. + +Signed-off-by: Hauke Mehrtens +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 1 + + arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 1 + + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 1 + + arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 9 +++----- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 1 + + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 1 + + arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 1 + + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 1 + + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 1 + + arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 1 + + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 1 + + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 1 + + arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi | 24 ++++++++++++++++++++++ + arch/arm/boot/dts/bcm5301x.dtsi | 12 +++++++++++ + 14 files changed, 50 insertions(+), 6 deletions(-) + create mode 100644 arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi + +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "asus,rt-ac56u", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "asus,rt-ac68u", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "luxul,xwc-1000", "brcm,bcm4708"; +@@ -23,12 +24,8 @@ + reg = <0x00000000 0x08000000>; + }; + +- axi@18000000 { +- nand@28000 { +- reg = <0x00028000 0x1000>; +- #address-cells = <1>; +- #size-cells = <1>; +- ++ nand: nand@18028000 { ++ nandcs@0 { + partition@0 { + label = "ubi"; + reg = <0x00000000 0x08000000>; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "netgear,r6250v1", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "netgear,r6300v2", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "smartrg,sr400ac", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm47081.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm47081.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm47081.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "buffalo,wzr-900dhp", "brcm,bcm47081", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "buffalo,wxr-1900dhp", "brcm,bcm4709", "brcm,bcm4708"; +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "netgear,r8000", "brcm,bcm4709", "brcm,bcm4708"; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi +@@ -0,0 +1,24 @@ ++/* ++ * Broadcom BCM470X / BCM5301X Nand chip defaults. ++ * ++ * This should be included if the NAND controller is on chip select 0 ++ * and uses 8 bit ECC. ++ * ++ * Copyright (C) 2015 Hauke Mehrtens ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/ { ++ nand@18028000 { ++ nandcs@0 { ++ compatible = "brcm,nandcs"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ nand-ecc-strength = <8>; ++ nand-ecc-step-size = <512>; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -143,4 +143,16 @@ + #gpio-cells = <2>; + }; + }; ++ ++ nand: nand@18028000 { ++ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; ++ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; ++ reg-names = "nand", "iproc-idm", "iproc-ext"; ++ interrupts = ; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ brcm,nand-has-wp; ++ }; + }; diff --git a/target/linux/bcm53xx/patches-4.1/065-ARM-BCM5301X-add-IRQ-numbers-for-PCIe-controller.patch b/target/linux/bcm53xx/patches-4.1/065-ARM-BCM5301X-add-IRQ-numbers-for-PCIe-controller.patch new file mode 100644 index 0000000..1422115 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/065-ARM-BCM5301X-add-IRQ-numbers-for-PCIe-controller.patch @@ -0,0 +1,48 @@ +From 1f80de6863ca0e36cabc622e858168fe5beb1e92 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 24 May 2015 21:08:14 +0200 +Subject: [PATCH] ARM: BCM5301X: add IRQ numbers for PCIe controller + +The driver for the PCIe controller was just added, this adds the +missing definition of the IRQ numbers to device tree. The driver itself +will be automatically detected by bcma. + +Signed-off-by: Hauke Mehrtens +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/bcm5301x.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -108,6 +108,30 @@ + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + ++ /* PCIe Controller 0 */ ++ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* PCIe Controller 1 */ ++ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* PCIe Controller 2 */ ++ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, ++ + /* USB 2.0 Controller */ + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + diff --git a/target/linux/bcm53xx/patches-4.1/066-ARM-BCM5301X-Add-DT-for-Asus-RT-AC87U.patch b/target/linux/bcm53xx/patches-4.1/066-ARM-BCM5301X-Add-DT-for-Asus-RT-AC87U.patch new file mode 100644 index 0000000..5790c9a --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/066-ARM-BCM5301X-Add-DT-for-Asus-RT-AC87U.patch @@ -0,0 +1,95 @@ +From 26343bdacfcdbf6ee3303d6078a015b908f90193 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sat, 16 May 2015 16:55:39 +0200 +Subject: [PATCH] ARM: BCM5301X: Add DT for Asus RT-AC87U +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Ãlvaro Fernández Rojas +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 65 +++++++++++++++++++++++++++++ + 2 files changed, 66 insertions(+) + create mode 100644 arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm47081-asus-rt-n18u.dtb \ + bcm47081-buffalo-wzr-600dhp2.dtb \ + bcm47081-buffalo-wzr-900dhp.dtb \ ++ bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-netgear-r8000.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -0,0 +1,65 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Asus RT-AC87U ++ * ++ * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; ++ model = "Asus RT-AC87U"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ wps { ++ label = "bcm53xx:blue:wps"; ++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ power { ++ label = "bcm53xx:blue:power"; ++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ wan { ++ label = "bcm53xx:red:wan"; ++ gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch b/target/linux/bcm53xx/patches-4.1/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch new file mode 100644 index 0000000..ccb8e27 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch @@ -0,0 +1,32 @@ +From af8fe7176ec13de08b1bfb7ea2ae9cc147b2429a Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 12 Sep 2015 12:56:37 +0200 +Subject: [PATCH] ARM: BCM5301X: add NAND flash chip description for Asus + RT-AC87U + +The NAND flash chip description were not imported for the Asus RT-AC87U +dts file when this was done for all the other dts files, because these +patches were send in parallel. + +This adds a missing NAND flash chip description to this patch: +commit 9faa5960eef3204cae6637b530f5e23e53b5a9ef +Author: Hauke Mehrtens +Date: Fri May 29 23:39:47 2015 +0200 + +ARM: BCM5301X: add NAND flash chip description + +Signed-off-by: Hauke Mehrtens +--- + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; diff --git a/target/linux/bcm53xx/patches-4.1/070-ARM-l2c-restore-the-behaviour-documented-above-l2c_e.patch b/target/linux/bcm53xx/patches-4.1/070-ARM-l2c-restore-the-behaviour-documented-above-l2c_e.patch new file mode 100644 index 0000000..abee99d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/070-ARM-l2c-restore-the-behaviour-documented-above-l2c_e.patch @@ -0,0 +1,43 @@ +From d965b0fca7dcde3f82c982e0bf1631069fdeb8c9 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Fri, 15 May 2015 11:56:45 +0100 +Subject: [PATCH 70/74] ARM: l2c: restore the behaviour documented above + l2c_enable() + +l2c_enable() is documented that it must not be called if the cache has +already been enabled. Unfortunately, commit 6b49241ac252 ("ARM: 8259/1: +l2c: Refactor the driver to use commit-like interface") changed this +without updating the comment, for very little reason. Revert this +change and restore the expected behaviour. + +Signed-off-by: Russell King +--- + arch/arm/mm/cache-l2x0.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -129,10 +129,6 @@ static void l2c_enable(void __iomem *bas + { + unsigned long flags; + +- /* Do not touch the controller if already enabled. */ +- if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN) +- return; +- + l2x0_saved_regs.aux_ctrl = aux; + l2c_configure(base); + +@@ -163,7 +159,11 @@ static void l2c_save(void __iomem *base) + + static void l2c_resume(void) + { +- l2c_enable(l2x0_base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock); ++ void __iomem *base = l2x0_base; ++ ++ /* Do not touch the controller if already enabled. */ ++ if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) ++ l2c_enable(base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock); + } + + /* diff --git a/target/linux/bcm53xx/patches-4.1/071-ARM-l2c-write-auxiliary-control-register-first.patch b/target/linux/bcm53xx/patches-4.1/071-ARM-l2c-write-auxiliary-control-register-first.patch new file mode 100644 index 0000000..a9cca83 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/071-ARM-l2c-write-auxiliary-control-register-first.patch @@ -0,0 +1,30 @@ +From 7705dd256ce363f8b01429efb2f0dc4d1ee23c89 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Fri, 15 May 2015 11:07:14 +0100 +Subject: [PATCH 71/74] ARM: l2c: write auxiliary control register first + +Before calling the controller specific configuration function, write +the auxiliary control register first, so that bits shared with other +registers (such as the prefetch control register) are not overwritten +by the later write to the auxctrl register. + +Signed-off-by: Russell King +--- + arch/arm/mm/cache-l2x0.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -115,10 +115,10 @@ static void l2c_configure(void __iomem * + return; + } + ++ l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); ++ + if (l2x0_data->configure) + l2x0_data->configure(base); +- +- l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); + } + + /* diff --git a/target/linux/bcm53xx/patches-4.1/072-ARM-l2c-clean-up-l2c_configure.patch b/target/linux/bcm53xx/patches-4.1/072-ARM-l2c-clean-up-l2c_configure.patch new file mode 100644 index 0000000..72e9e76 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/072-ARM-l2c-clean-up-l2c_configure.patch @@ -0,0 +1,109 @@ +From 50beefde30224888d6d63224405ace4bdd4b32a0 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Fri, 15 May 2015 11:05:54 +0100 +Subject: [PATCH 72/74] ARM: l2c: clean up l2c_configure() + +l2c_configure() does not follow the pattern of other l2c_* functions. +Fix this so that it does to avoid future confusion. + +Signed-off-by: Russell King +--- + arch/arm/mm/cache-l2x0.c | 23 ++++++++++++++--------- + 1 file changed, 14 insertions(+), 9 deletions(-) + +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -110,15 +110,7 @@ static inline void l2c_unlock(void __iom + + static void l2c_configure(void __iomem *base) + { +- if (outer_cache.configure) { +- outer_cache.configure(&l2x0_saved_regs); +- return; +- } +- + l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); +- +- if (l2x0_data->configure) +- l2x0_data->configure(base); + } + + /* +@@ -130,7 +122,11 @@ static void l2c_enable(void __iomem *bas + unsigned long flags; + + l2x0_saved_regs.aux_ctrl = aux; +- l2c_configure(base); ++ ++ if (outer_cache.configure) ++ outer_cache.configure(&l2x0_saved_regs); ++ else ++ l2x0_data->configure(base); + + l2c_unlock(base, num_lock); + +@@ -252,6 +248,7 @@ static const struct l2c_init_data l2c210 + .num_lock = 1, + .enable = l2c_enable, + .save = l2c_save, ++ .configure = l2c_configure, + .outer_cache = { + .inv_range = l2c210_inv_range, + .clean_range = l2c210_clean_range, +@@ -409,6 +406,7 @@ static const struct l2c_init_data l2c220 + .num_lock = 1, + .enable = l2c220_enable, + .save = l2c_save, ++ .configure = l2c_configure, + .outer_cache = { + .inv_range = l2c220_inv_range, + .clean_range = l2c220_clean_range, +@@ -569,6 +567,8 @@ static void l2c310_configure(void __iome + { + unsigned revision; + ++ l2c_configure(base); ++ + /* restore pl310 setup */ + l2c_write_sec(l2x0_saved_regs.tag_latency, base, + L310_TAG_LATENCY_CTRL); +@@ -1066,6 +1066,7 @@ static const struct l2c_init_data of_l2c + .of_parse = l2x0_of_parse, + .enable = l2c_enable, + .save = l2c_save, ++ .configure = l2c_configure, + .outer_cache = { + .inv_range = l2c210_inv_range, + .clean_range = l2c210_clean_range, +@@ -1084,6 +1085,7 @@ static const struct l2c_init_data of_l2c + .of_parse = l2x0_of_parse, + .enable = l2c220_enable, + .save = l2c_save, ++ .configure = l2c_configure, + .outer_cache = { + .inv_range = l2c220_inv_range, + .clean_range = l2c220_clean_range, +@@ -1416,6 +1418,7 @@ static const struct l2c_init_data of_aur + .enable = l2c_enable, + .fixup = aurora_fixup, + .save = aurora_save, ++ .configure = l2c_configure, + .outer_cache = { + .inv_range = aurora_inv_range, + .clean_range = aurora_clean_range, +@@ -1435,6 +1438,7 @@ static const struct l2c_init_data of_aur + .enable = aurora_enable_no_outer, + .fixup = aurora_fixup, + .save = aurora_save, ++ .configure = l2c_configure, + .outer_cache = { + .resume = l2c_resume, + }, +@@ -1608,6 +1612,7 @@ static void __init tauros3_save(void __i + + static void tauros3_configure(void __iomem *base) + { ++ l2c_configure(base); + writel_relaxed(l2x0_saved_regs.aux2_ctrl, + base + TAUROS3_AUX2_CTRL); + writel_relaxed(l2x0_saved_regs.prefetch_ctrl, diff --git a/target/linux/bcm53xx/patches-4.1/073-ARM-l2c-only-unlock-caches-if-NS_LOCKDOWN-bit-is-set.patch b/target/linux/bcm53xx/patches-4.1/073-ARM-l2c-only-unlock-caches-if-NS_LOCKDOWN-bit-is-set.patch new file mode 100644 index 0000000..852dd02 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/073-ARM-l2c-only-unlock-caches-if-NS_LOCKDOWN-bit-is-set.patch @@ -0,0 +1,149 @@ +From e946a8cbe4a47a7c2615ffb0d45712e72c7d0f3a Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Fri, 15 May 2015 11:51:51 +0100 +Subject: [PATCH 73/74] ARM: l2c: only unlock caches if NS_LOCKDOWN bit is set + +Some L2C caches have a bit which allows non-secure software to control +the cache lockdown. Some platforms are unable to set this bit. To +avoid receiving an abort while trying to unlock the cache lines, check +the state of this bit before unlocking. We do this by providing a new +method in the l2c_init_data to perform the unlocking. + +Signed-off-by: Russell King +--- + arch/arm/mm/cache-l2x0.c | 26 +++++++++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -42,6 +42,7 @@ struct l2c_init_data { + void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); + void (*save)(void __iomem *); + void (*configure)(void __iomem *); ++ void (*unlock)(void __iomem *, unsigned); + struct outer_cache_fns outer_cache; + }; + +@@ -128,7 +129,7 @@ static void l2c_enable(void __iomem *bas + else + l2x0_data->configure(base); + +- l2c_unlock(base, num_lock); ++ l2x0_data->unlock(base, num_lock); + + local_irq_save(flags); + __l2c_op_way(base + L2X0_INV_WAY); +@@ -249,6 +250,7 @@ static const struct l2c_init_data l2c210 + .enable = l2c_enable, + .save = l2c_save, + .configure = l2c_configure, ++ .unlock = l2c_unlock, + .outer_cache = { + .inv_range = l2c210_inv_range, + .clean_range = l2c210_clean_range, +@@ -400,6 +402,12 @@ static void l2c220_enable(void __iomem * + l2c_enable(base, aux, num_lock); + } + ++static void l2c220_unlock(void __iomem *base, unsigned num_lock) ++{ ++ if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN) ++ l2c_unlock(base, num_lock); ++} ++ + static const struct l2c_init_data l2c220_data = { + .type = "L2C-220", + .way_size_0 = SZ_8K, +@@ -407,6 +415,7 @@ static const struct l2c_init_data l2c220 + .enable = l2c220_enable, + .save = l2c_save, + .configure = l2c_configure, ++ .unlock = l2c220_unlock, + .outer_cache = { + .inv_range = l2c220_inv_range, + .clean_range = l2c220_clean_range, +@@ -755,6 +764,12 @@ static void l2c310_resume(void) + set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1)); + } + ++static void l2c310_unlock(void __iomem *base, unsigned num_lock) ++{ ++ if (readl_relaxed(base + L2X0_AUX_CTRL) & L310_AUX_CTRL_NS_LOCKDOWN) ++ l2c_unlock(base, num_lock); ++} ++ + static const struct l2c_init_data l2c310_init_fns __initconst = { + .type = "L2C-310", + .way_size_0 = SZ_8K, +@@ -763,6 +778,7 @@ static const struct l2c_init_data l2c310 + .fixup = l2c310_fixup, + .save = l2c310_save, + .configure = l2c310_configure, ++ .unlock = l2c310_unlock, + .outer_cache = { + .inv_range = l2c210_inv_range, + .clean_range = l2c210_clean_range, +@@ -1067,6 +1083,7 @@ static const struct l2c_init_data of_l2c + .enable = l2c_enable, + .save = l2c_save, + .configure = l2c_configure, ++ .unlock = l2c_unlock, + .outer_cache = { + .inv_range = l2c210_inv_range, + .clean_range = l2c210_clean_range, +@@ -1086,6 +1103,7 @@ static const struct l2c_init_data of_l2c + .enable = l2c220_enable, + .save = l2c_save, + .configure = l2c_configure, ++ .unlock = l2c220_unlock, + .outer_cache = { + .inv_range = l2c220_inv_range, + .clean_range = l2c220_clean_range, +@@ -1213,6 +1231,7 @@ static const struct l2c_init_data of_l2c + .fixup = l2c310_fixup, + .save = l2c310_save, + .configure = l2c310_configure, ++ .unlock = l2c310_unlock, + .outer_cache = { + .inv_range = l2c210_inv_range, + .clean_range = l2c210_clean_range, +@@ -1242,6 +1261,7 @@ static const struct l2c_init_data of_l2c + .fixup = l2c310_fixup, + .save = l2c310_save, + .configure = l2c310_configure, ++ .unlock = l2c310_unlock, + .outer_cache = { + .inv_range = l2c210_inv_range, + .clean_range = l2c210_clean_range, +@@ -1419,6 +1439,7 @@ static const struct l2c_init_data of_aur + .fixup = aurora_fixup, + .save = aurora_save, + .configure = l2c_configure, ++ .unlock = l2c_unlock, + .outer_cache = { + .inv_range = aurora_inv_range, + .clean_range = aurora_clean_range, +@@ -1439,6 +1460,7 @@ static const struct l2c_init_data of_aur + .fixup = aurora_fixup, + .save = aurora_save, + .configure = l2c_configure, ++ .unlock = l2c_unlock, + .outer_cache = { + .resume = l2c_resume, + }, +@@ -1589,6 +1611,7 @@ static const struct l2c_init_data of_bcm + .enable = l2c310_enable, + .save = l2c310_save, + .configure = l2c310_configure, ++ .unlock = l2c310_unlock, + .outer_cache = { + .inv_range = bcm_inv_range, + .clean_range = bcm_clean_range, +@@ -1626,6 +1649,7 @@ static const struct l2c_init_data of_tau + .enable = l2c_enable, + .save = tauros3_save, + .configure = tauros3_configure, ++ .unlock = l2c_unlock, + /* Tauros3 broadcasts L1 cache operations to L2 */ + .outer_cache = { + .resume = l2c_resume, diff --git a/target/linux/bcm53xx/patches-4.1/074-ARM-l2c-avoid-passing-auxiliary-control-register-thr.patch b/target/linux/bcm53xx/patches-4.1/074-ARM-l2c-avoid-passing-auxiliary-control-register-thr.patch new file mode 100644 index 0000000..05e739f --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/074-ARM-l2c-avoid-passing-auxiliary-control-register-thr.patch @@ -0,0 +1,129 @@ +From 5b290ec2074c68b9f4f8f8789fa9b3e1782869e7 Mon Sep 17 00:00:00 2001 +From: Russell King +Date: Fri, 15 May 2015 12:03:29 +0100 +Subject: [PATCH 74/74] ARM: l2c: avoid passing auxiliary control register + through enable method + +Avoid passing the auxiliary control register value through the enable +method. In the resume path, we have to read the value stored in +l2x0_saved_regs.aux_ctrl, only to have it immediately written back by +l2c_enable(). We can avoid this if we have __l2c_init() save the value +directly to l2x0_saved_regs.aux_ctrl before calling the specific enable +method. + +Signed-off-by: Russell King +--- + arch/arm/mm/cache-l2x0.c | 32 +++++++++++++++++--------------- + 1 file changed, 17 insertions(+), 15 deletions(-) + +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -38,7 +38,7 @@ struct l2c_init_data { + unsigned way_size_0; + unsigned num_lock; + void (*of_parse)(const struct device_node *, u32 *, u32 *); +- void (*enable)(void __iomem *, u32, unsigned); ++ void (*enable)(void __iomem *, unsigned); + void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); + void (*save)(void __iomem *); + void (*configure)(void __iomem *); +@@ -118,12 +118,10 @@ static void l2c_configure(void __iomem * + * Enable the L2 cache controller. This function must only be + * called when the cache controller is known to be disabled. + */ +-static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) ++static void l2c_enable(void __iomem *base, unsigned num_lock) + { + unsigned long flags; + +- l2x0_saved_regs.aux_ctrl = aux; +- + if (outer_cache.configure) + outer_cache.configure(&l2x0_saved_regs); + else +@@ -160,7 +158,7 @@ static void l2c_resume(void) + + /* Do not touch the controller if already enabled. */ + if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) +- l2c_enable(base, l2x0_saved_regs.aux_ctrl, l2x0_data->num_lock); ++ l2c_enable(base, l2x0_data->num_lock); + } + + /* +@@ -390,16 +388,16 @@ static void l2c220_sync(void) + raw_spin_unlock_irqrestore(&l2x0_lock, flags); + } + +-static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) ++static void l2c220_enable(void __iomem *base, unsigned num_lock) + { + /* + * Always enable non-secure access to the lockdown registers - + * we write to them as part of the L2C enable sequence so they + * need to be accessible. + */ +- aux |= L220_AUX_CTRL_NS_LOCKDOWN; ++ l2x0_saved_regs.aux_ctrl |= L220_AUX_CTRL_NS_LOCKDOWN; + +- l2c_enable(base, aux, num_lock); ++ l2c_enable(base, num_lock); + } + + static void l2c220_unlock(void __iomem *base, unsigned num_lock) +@@ -612,10 +610,11 @@ static int l2c310_cpu_enable_flz(struct + return NOTIFY_OK; + } + +-static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) ++static void __init l2c310_enable(void __iomem *base, unsigned num_lock) + { + unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK; + bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9; ++ u32 aux = l2x0_saved_regs.aux_ctrl; + + if (rev >= L310_CACHE_ID_RTL_R2P0) { + if (cortex_a9) { +@@ -658,9 +657,9 @@ static void __init l2c310_enable(void __ + * we write to them as part of the L2C enable sequence so they + * need to be accessible. + */ +- aux |= L310_AUX_CTRL_NS_LOCKDOWN; ++ l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN; + +- l2c_enable(base, aux, num_lock); ++ l2c_enable(base, num_lock); + + /* Read back resulting AUX_CTRL value as it could have been altered. */ + aux = readl_relaxed(base + L2X0_AUX_CTRL); +@@ -872,8 +871,11 @@ static int __init __l2c_init(const struc + * Check if l2x0 controller is already enabled. If we are booting + * in non-secure mode accessing the below registers will fault. + */ +- if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) +- data->enable(l2x0_base, aux, data->num_lock); ++ if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { ++ l2x0_saved_regs.aux_ctrl = aux; ++ ++ data->enable(l2x0_base, data->num_lock); ++ } + + outer_cache = fns; + +@@ -1388,7 +1390,7 @@ static void aurora_save(void __iomem *ba + * For Aurora cache in no outer mode, enable via the CP15 coprocessor + * broadcasting of cache commands to L2. + */ +-static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, ++static void __init aurora_enable_no_outer(void __iomem *base, + unsigned num_lock) + { + u32 u; +@@ -1399,7 +1401,7 @@ static void __init aurora_enable_no_oute + + isb(); + +- l2c_enable(base, aux, num_lock); ++ l2c_enable(base, num_lock); + } + + static void __init aurora_fixup(void __iomem *base, u32 cache_id, diff --git a/target/linux/bcm53xx/patches-4.1/075-ARM-8391-1-l2c-add-options-to-overwrite-prefetching-.patch b/target/linux/bcm53xx/patches-4.1/075-ARM-8391-1-l2c-add-options-to-overwrite-prefetching-.patch new file mode 100644 index 0000000..857d2c4 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/075-ARM-8391-1-l2c-add-options-to-overwrite-prefetching-.patch @@ -0,0 +1,60 @@ +From ec3bd0e68a679a7af2c46af1ddc9af8b534a8b0e Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Wed, 10 Jun 2015 20:23:24 +0100 +Subject: [PATCH] ARM: 8391/1: l2c: add options to overwrite prefetching + behavior + +These options make it possible to overwrites the data and instruction +prefetching behavior of the arm pl310 cache controller. + +Signed-off-by: Hauke Mehrtens +Acked-by: Florian Fainelli +Signed-off-by: Russell King +--- + Documentation/devicetree/bindings/arm/l2cc.txt | 5 +++++ + arch/arm/mm/cache-l2x0.c | 20 ++++++++++++++++++++ + 2 files changed, 25 insertions(+) + +--- a/Documentation/devicetree/bindings/arm/l2cc.txt ++++ b/Documentation/devicetree/bindings/arm/l2cc.txt +@@ -67,6 +67,11 @@ Optional properties: + disable if zero. + - arm,prefetch-offset : Override prefetch offset value. Valid values are + 0-7, 15, 23, and 31. ++- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> ++ (forcibly enable), property absent (retain settings set by firmware) ++- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), ++ <1> (forcibly enable), property absent (retain settings set by ++ firmware) + + Example: + +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -1221,6 +1221,26 @@ static void __init l2c310_of_parse(const + pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n"); + } + ++ ret = of_property_read_u32(np, "prefetch-data", &val); ++ if (ret == 0) { ++ if (val) ++ prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH; ++ else ++ prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; ++ } else if (ret != -EINVAL) { ++ pr_err("L2C-310 OF prefetch-data property value is missing\n"); ++ } ++ ++ ret = of_property_read_u32(np, "prefetch-instr", &val); ++ if (ret == 0) { ++ if (val) ++ prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH; ++ else ++ prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; ++ } else if (ret != -EINVAL) { ++ pr_err("L2C-310 OF prefetch-instr property value is missing\n"); ++ } ++ + l2x0_saved_regs.prefetch_ctrl = prefetch; + } + diff --git a/target/linux/bcm53xx/patches-4.1/077-ARM-l2c-Add-support-for-the-arm-shared-override-prop.patch b/target/linux/bcm53xx/patches-4.1/077-ARM-l2c-Add-support-for-the-arm-shared-override-prop.patch new file mode 100644 index 0000000..cac4c0c --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/077-ARM-l2c-Add-support-for-the-arm-shared-override-prop.patch @@ -0,0 +1,81 @@ +From 1bc7c02e7f37ddfa09cb0db330ee8cd4034d6410 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Thu, 7 May 2015 11:27:11 +0200 +Subject: [PATCH 1/4] ARM: l2c: Add support for the "arm, shared-override" + property + +"CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2 +Shareable attribute" states: + + "The default behavior of the cache controller with respect to the + shareable attribute is to transform Normal Memory Non-cacheable + transactions into: + - cacheable no allocate for reads + - write through no write allocate for writes." + +Depending on the system architecture, this may cause memory corruption +in the presence of bus mastering devices (e.g. OHCI). To avoid such +corruption, the default behavior can be disabled by setting the Shared +Override bit in the Auxiliary Control register. + +Currently the Shared Override bit can be set only using C code: + - by calling l2x0_init() directly, which is deprecated, + - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask + fields, but using values differing from 0/~0 is also deprecated. + +Hence add support for an "arm,shared-override" device tree property for +the l2c device node. By specifying this property, affected systems can +indicate that non-cacheable transactions must not be transformed. +Then, it's up to the OS to decide. The current behavior is to set the +"shared attribute override enable" bit, as there may exist kernel linear +mappings and cacheable aliases for the DMA buffers, even if CMA is +enabled. + +See also commit 1a8e41cd672f894b ("ARM: 6395/1: VExpress: Set bit 22 in +the PL310 (cache controller) AuxCtlr register"): + + "Clearing bit 22 in the PL310 Auxiliary Control register (shared + attribute override enable) has the side effect of transforming + Normal Shared Non-cacheable reads into Cacheable no-allocate reads. + + Coherent DMA buffers in Linux always have a Cacheable alias via the + kernel linear mapping and the processor can speculatively load + cache lines into the PL310 controller. With bit 22 cleared, + Non-cacheable reads would unexpectedly hit such cache lines leading + to buffer corruption." + +Signed-off-by: Geert Uytterhoeven +--- + Documentation/devicetree/bindings/arm/l2cc.txt | 6 ++++++ + arch/arm/mm/cache-l2x0.c | 5 +++++ + 2 files changed, 11 insertions(+) + +--- a/Documentation/devicetree/bindings/arm/l2cc.txt ++++ b/Documentation/devicetree/bindings/arm/l2cc.txt +@@ -72,6 +72,12 @@ Optional properties: + - prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), + <1> (forcibly enable), property absent (retain settings set by + firmware) ++- arm,shared-override : The default behavior of the pl310 cache controller with ++ respect to the shareable attribute is to transform "normal memory ++ non-cacheable transactions" into "cacheable no allocate" (for reads) or ++ "write through no write allocate" (for writes). ++ On systems where this may cause DMA buffer corruption, this property must be ++ specified to indicate that such transforms are precluded. + + Example: + +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -1171,6 +1171,11 @@ static void __init l2c310_of_parse(const + } + } + ++ if (of_property_read_bool(np, "arm,shared-override")) { ++ *aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE; ++ *aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE; ++ } ++ + prefetch = l2x0_saved_regs.prefetch_ctrl; + + ret = of_property_read_u32(np, "arm,double-linefill", &val); diff --git a/target/linux/bcm53xx/patches-4.1/079-ARM-BCM5301X-activate-some-additional-options-in-pl3.patch b/target/linux/bcm53xx/patches-4.1/079-ARM-BCM5301X-activate-some-additional-options-in-pl3.patch new file mode 100644 index 0000000..bfe4304 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/079-ARM-BCM5301X-activate-some-additional-options-in-pl3.patch @@ -0,0 +1,29 @@ +From e8ec653c767f56346eb1fadbc07e0706d6dbd56f Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Thu, 14 May 2015 00:38:28 +0200 +Subject: [PATCH 3/3] ARM: BCM5301X: activate some additional options in pl310 + cache controller + +In the default Broadcom SDK the shared override is activated for this +cache controller, do the same in the upstream code. Data and +instruction prefetching is not activated by default for this cache +controller on the bcm53xx SoC, do it manually like it is done in the +vendor SDK. + +Signed-off-by: Hauke Mehrtens +--- + arch/arm/boot/dts/bcm5301x.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -78,6 +78,9 @@ + compatible = "arm,pl310-cache"; + reg = <0x2000 0x1000>; + cache-unified; ++ arm,shared-override; ++ prefetch-data = <1>; ++ prefetch-instr = <1>; + cache-level = <2>; + }; + }; diff --git a/target/linux/bcm53xx/patches-4.1/080-ARM-BCM5301X-Enable-UART0-on-tested-devices.patch b/target/linux/bcm53xx/patches-4.1/080-ARM-BCM5301X-Enable-UART0-on-tested-devices.patch new file mode 100644 index 0000000..ce69cca --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/080-ARM-BCM5301X-Enable-UART0-on-tested-devices.patch @@ -0,0 +1,83 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 29 Jun 2015 07:22:16 +0200 +Subject: [PATCH] ARM: BCM5301X: Enable UART0 on tested devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There are two possible UARTs so we have (both of) them disabled by +default. Override uart0 status on devices that were verified to use it. +In case of Netgear R6250 also drop an old (and invalid) overwrite. It +doesn't have uart1 connected. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Acked-by: Hauke Mehrtens +Signed-off-by: Florian Fainelli +--- +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -135,3 +135,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +@@ -55,3 +55,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -24,16 +24,6 @@ + reg = <0x00000000 0x08000000>; + }; + +- chipcommonA { +- uart0: serial@0300 { +- status = "okay"; +- }; +- +- uart1: serial@0400 { +- status = "okay"; +- }; +- }; +- + leds { + compatible = "gpio-leds"; + +@@ -92,3 +82,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -118,3 +118,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -122,3 +122,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/081-ARM-BCM5301X-Add-profiling-support.patch b/target/linux/bcm53xx/patches-4.1/081-ARM-BCM5301X-Add-profiling-support.patch new file mode 100644 index 0000000..afd73f5 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/081-ARM-BCM5301X-Add-profiling-support.patch @@ -0,0 +1,25 @@ +From: Felix Fietkau +Date: Wed, 29 Jul 2015 23:51:00 +0200 +Subject: [PATCH] ARM: BCM5301X: Add profiling support + +Signed-off-by: Felix Fietkau +Signed-off-by: Hauke Mehrtens +Signed-off-by: Florian Fainelli +Signed-off-by: Olof Johansson +--- +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -85,6 +85,13 @@ + }; + }; + ++ pmu { ++ compatible = "arm,cortex-a9-pmu"; ++ interrupts = ++ , ++ ; ++ }; ++ + clocks { + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/bcm53xx/patches-4.1/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch b/target/linux/bcm53xx/patches-4.1/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch new file mode 100644 index 0000000..02856d0 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch @@ -0,0 +1,128 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 26 Aug 2015 16:11:38 +0200 +Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7000 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -68,6 +68,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm47081-buffalo-wzr-900dhp.dtb \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ ++ bcm4709-netgear-r7000.dtb \ + bcm4709-netgear-r8000.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ + bcm963138dvt.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -0,0 +1,106 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Netgear R7000 ++ * ++ * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" ++ ++/ { ++ compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; ++ model = "Netgear R7000"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ power-white { ++ label = "bcm53xx:white:power"; ++ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ power-amber { ++ label = "bcm53xx:amber:power"; ++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 5ghz { ++ label = "bcm53xx:white:5ghz"; ++ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 2ghz { ++ label = "bcm53xx:white:2ghz"; ++ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wps { ++ label = "bcm53xx:white:wps"; ++ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wireless { ++ label = "bcm53xx:white:wireless"; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb3 { ++ label = "bcm53xx:white:usb3"; ++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb2 { ++ label = "bcm53xx:white:usb2"; ++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ rfkill { ++ label = "WiFi"; ++ linux,code = ; ++ gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch b/target/linux/bcm53xx/patches-4.1/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch new file mode 100644 index 0000000..1d2c250 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch @@ -0,0 +1,218 @@ +From a0aef7fbab0d8b5a0d445c74990e5233beda246e Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Wed, 21 Oct 2015 18:46:04 -0400 +Subject: [PATCH] ARM: dts: bcm5301x: Add BCM SVK DT files + +Add device tree files for Broadcom Northstar based SVKs. Since the +bcm5301x.dtsi already exists, all that is necessary is the dts files to +enable the UARTs. With these files, the SVKs are able to boot to shell. + +Signed-off-by: Jon Mason +--- + arch/arm/boot/dts/Makefile | 5 +++- + arch/arm/boot/dts/bcm94708.dts | 56 +++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm94709.dts | 56 +++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm953012k.dts | 63 ++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 179 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/bcm94708.dts + create mode 100644 arch/arm/boot/dts/bcm94709.dts + create mode 100644 arch/arm/boot/dts/bcm953012k.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -69,7 +69,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-netgear-r7000.dtb \ +- bcm4709-netgear-r8000.dtb ++ bcm4709-netgear-r8000.dtb \ ++ bcm94708.dtb \ ++ bcm94709.dtb \ ++ bcm953012k.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ + bcm963138dvt.dtb + dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm94708.dts +@@ -0,0 +1,56 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM94708)"; ++ compatible = "brcm,bcm94708", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm94709.dts +@@ -0,0 +1,56 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM94709)"; ++ compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm953012k.dts +@@ -0,0 +1,63 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM953012K)"; ++ compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x10000000>; ++ }; ++}; ++ ++&uart0 { ++ clock-frequency = <62499840>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ clock-frequency = <62499840>; ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/090-mtd-nand-add-common-DT-init-code.patch b/target/linux/bcm53xx/patches-4.1/090-mtd-nand-add-common-DT-init-code.patch new file mode 100644 index 0000000..cb2141a --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/090-mtd-nand-add-common-DT-init-code.patch @@ -0,0 +1,111 @@ +From 5844feeaa4154d1c46d3462c7a4653d22356d8b4 Mon Sep 17 00:00:00 2001 +From: Brian Norris +Date: Fri, 23 Jan 2015 00:22:27 -0800 +Subject: [PATCH 20/32] mtd: nand: add common DT init code + +These are already-documented common bindings for NAND chips. Let's +handle them in nand_base. + +If NAND controller drivers need to act on this data before bringing up +the NAND chip (e.g., fill out ECC callback functions, change HW modes, +etc.), then they can do so between calling nand_scan_ident() and +nand_scan_tail(). + +Signed-off-by: Brian Norris +--- + drivers/mtd/nand/nand_base.c | 41 +++++++++++++++++++++++++++++++++++++++++ + include/linux/mtd/nand.h | 5 +++++ + 2 files changed, 46 insertions(+) + +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -48,6 +48,7 @@ + #include + #include + #include ++#include + + /* Define default oob placement schemes for large and small page devices */ + static struct nand_ecclayout nand_oob_8 = { +@@ -3798,6 +3799,39 @@ ident_done: + return type; + } + ++static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ++ struct device_node *dn) ++{ ++ int ecc_mode, ecc_strength, ecc_step; ++ ++ if (of_get_nand_bus_width(dn) == 16) ++ chip->options |= NAND_BUSWIDTH_16; ++ ++ if (of_get_nand_on_flash_bbt(dn)) ++ chip->bbt_options |= NAND_BBT_USE_FLASH; ++ ++ ecc_mode = of_get_nand_ecc_mode(dn); ++ ecc_strength = of_get_nand_ecc_strength(dn); ++ ecc_step = of_get_nand_ecc_step_size(dn); ++ ++ if ((ecc_step >= 0 && !(ecc_strength >= 0)) || ++ (!(ecc_step >= 0) && ecc_strength >= 0)) { ++ pr_err("must set both strength and step size in DT\n"); ++ return -EINVAL; ++ } ++ ++ if (ecc_mode >= 0) ++ chip->ecc.mode = ecc_mode; ++ ++ if (ecc_strength >= 0) ++ chip->ecc.strength = ecc_strength; ++ ++ if (ecc_step > 0) ++ chip->ecc.size = ecc_step; ++ ++ return 0; ++} ++ + /** + * nand_scan_ident - [NAND Interface] Scan for the NAND device + * @mtd: MTD device structure +@@ -3815,6 +3849,13 @@ int nand_scan_ident(struct mtd_info *mtd + int i, nand_maf_id, nand_dev_id; + struct nand_chip *chip = mtd->priv; + struct nand_flash_dev *type; ++ int ret; ++ ++ if (chip->dn) { ++ ret = nand_dt_init(mtd, chip, chip->dn); ++ if (ret) ++ return ret; ++ } + + /* Set the default functions */ + nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -26,6 +26,8 @@ + + struct mtd_info; + struct nand_flash_dev; ++struct device_node; ++ + /* Scan and identify a NAND device */ + extern int nand_scan(struct mtd_info *mtd, int max_chips); + /* +@@ -542,6 +544,7 @@ struct nand_buffers { + * flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the + * flash device. ++ * @dn: [BOARDSPECIFIC] device node describing this instance + * @read_byte: [REPLACEABLE] read one byte from the chip + * @read_word: [REPLACEABLE] read one word from the chip + * @write_byte: [REPLACEABLE] write a single byte to the chip on the +@@ -644,6 +647,8 @@ struct nand_chip { + void __iomem *IO_ADDR_R; + void __iomem *IO_ADDR_W; + ++ struct device_node *dn; ++ + uint8_t (*read_byte)(struct mtd_info *mtd); + u16 (*read_word)(struct mtd_info *mtd); + void (*write_byte)(struct mtd_info *mtd, uint8_t byte); diff --git a/target/linux/bcm53xx/patches-4.1/092-Add-Broadcom-STB-NAND.patch b/target/linux/bcm53xx/patches-4.1/092-Add-Broadcom-STB-NAND.patch new file mode 100644 index 0000000..a6cf211 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/092-Add-Broadcom-STB-NAND.patch @@ -0,0 +1,2765 @@ +This contains the following commits: + +commit bcb83a19d3ac95fe3c0e79e942fb628120738853 +Author: Hauke Mehrtens +Date: Sun May 17 17:41:01 2015 +0200 + + mtd: brcmnand: do not make local variable static + + Remove static in front of ctrl. This variable should not be shared + between different instances of brcmnand_probe(), it should be local to + this function and stored on the stack. + + Signed-off-by: Hauke Mehrtens + Signed-off-by: Brian Norris + +commit 802041247a0abbeaf1dddb8a8d56f491762ae357 +Author: Hauke Mehrtens +Date: Sun May 17 17:41:00 2015 +0200 + + mtd: brcmnand: remove double new line from print + + The caller already adds a new line and in the other cases there is no + new line added. + + Signed-off-by: Hauke Mehrtens + Signed-off-by: Brian Norris + +commit f628ece6636c2f0354a52566cafdea6d2f963b3d +Author: Brian Norris +Date: Tue May 12 12:13:14 2015 -0700 + + mtd: brcmnand: add BCM63138 support + + Signed-off-by: Brian Norris + Reviewed-by: Florian Fainelli + Tested-by: Florian Fainelli + +commit ca22f040dd145fc4d8069ce174f6eb0bc3ebd19f +Author: Brian Norris +Date: Tue May 12 12:12:02 2015 -0700 + + mtd: brcmnand: add support for Broadcom's IPROC family + + Signed-off-by: Brian Norris + + +commit c26211d37f11d5913d9803fdede6d053f918ba7b +Author: Brian Norris +Date: Tue May 12 12:09:28 2015 -0700 + + mtd: brcmnand: add extra SoC support to library + + There are a few small hooks required for chips like BCM63138 and the + iProc family. Let's introduce those now. + + Signed-off-by: Brian Norris + Reviewed-by: Florian Fainelli + Tested-by: Florian Fainelli + +commit 303b4420ff1896b444017b5b0eb8252ce197797d +Author: Brian Norris +Date: Tue May 12 17:00:57 2015 -0700 + + mtd: brcmnand: add support for STB chips + + BCM7xxx chips are supported entirely by the library code, since they use + generic irqchip interfaces and don't need any extra SoC-specific + configuration. + + Signed-off-by: Brian Norris + +commit 27c5b17cd1b10564fa36f8f51e4b4b41436ecc32 +Author: Brian Norris +Date: Fri Mar 6 11:38:08 2015 -0800 + + mtd: nand: add NAND driver "library" for Broadcom STB NAND controller + + This core originated in Set-Top Box chips (BCM7xxx) but is used in a + variety of other Broadcom chips, including some BCM63xxx, BCM33xx, and + iProc/Cygnus. It's been used only on ARM and MIPS SoCs, so restrict it + to those architectures. + + There are multiple revisions of this core throughout the years, and + almost every version broke register compatibility in some small way, but + with some effort, this driver is able to support v4.0, v5.0, v6.x, v7.0, + and v7.1. It's been tested on v5.0, v6.0, v6.1, v7.0, and v7.1 recently, + so there hopefully are no more lurking inconsistencies. + + This patch adds just some library support, on which platform drivers can + be built. + + Signed-off-by: Brian Norris + Reviewed-by: Florian Fainelli + Tested-by: Florian Fainelli + +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -394,6 +394,14 @@ config MTD_NAND_GPMI_NAND + block, such as SD card. So pay attention to it when you enable + the GPMI. + ++config MTD_NAND_BRCMNAND ++ tristate "Broadcom STB NAND controller" ++ depends on ARM || MIPS ++ help ++ Enables the Broadcom NAND controller driver. The controller was ++ originally designed for Set-Top Box but is used on various BCM7xxx, ++ BCM3xxx, BCM63xxx, iProc/Cygnus and more. ++ + config MTD_NAND_BCM47XXNFLASH + tristate "Support for NAND flash on BCM4706 BCMA bus" + depends on BCMA_NFLASH +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -52,5 +52,6 @@ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nan + obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ + obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o + obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o ++obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ + + nand-objs := nand_base.o nand_bbt.o nand_timings.o +--- /dev/null ++++ b/drivers/mtd/nand/brcmnand/Makefile +@@ -0,0 +1,6 @@ ++# link order matters; don't link the more generic brcmstb_nand.o before the ++# more specific iproc_nand.o, for instance ++obj-$(CONFIG_MTD_NAND_BRCMNAND) += iproc_nand.o ++obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm63138_nand.o ++obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmstb_nand.o ++obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o +--- /dev/null ++++ b/drivers/mtd/nand/brcmnand/bcm63138_nand.c +@@ -0,0 +1,109 @@ ++/* ++ * Copyright © 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "brcmnand.h" ++ ++struct bcm63138_nand_soc { ++ struct brcmnand_soc soc; ++ void __iomem *base; ++}; ++ ++#define BCM63138_NAND_INT_STATUS 0x00 ++#define BCM63138_NAND_INT_EN 0x04 ++ ++enum { ++ BCM63138_CTLRDY = BIT(4), ++}; ++ ++static bool bcm63138_nand_intc_ack(struct brcmnand_soc *soc) ++{ ++ struct bcm63138_nand_soc *priv = ++ container_of(soc, struct bcm63138_nand_soc, soc); ++ void __iomem *mmio = priv->base + BCM63138_NAND_INT_STATUS; ++ u32 val = brcmnand_readl(mmio); ++ ++ if (val & BCM63138_CTLRDY) { ++ brcmnand_writel(val & ~BCM63138_CTLRDY, mmio); ++ return true; ++ } ++ ++ return false; ++} ++ ++static void bcm63138_nand_intc_set(struct brcmnand_soc *soc, bool en) ++{ ++ struct bcm63138_nand_soc *priv = ++ container_of(soc, struct bcm63138_nand_soc, soc); ++ void __iomem *mmio = priv->base + BCM63138_NAND_INT_EN; ++ u32 val = brcmnand_readl(mmio); ++ ++ if (en) ++ val |= BCM63138_CTLRDY; ++ else ++ val &= ~BCM63138_CTLRDY; ++ ++ brcmnand_writel(val, mmio); ++} ++ ++static int bcm63138_nand_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct bcm63138_nand_soc *priv; ++ struct brcmnand_soc *soc; ++ struct resource *res; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ soc = &priv->soc; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-int-base"); ++ priv->base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ soc->ctlrdy_ack = bcm63138_nand_intc_ack; ++ soc->ctlrdy_set_enabled = bcm63138_nand_intc_set; ++ ++ return brcmnand_probe(pdev, soc); ++} ++ ++static const struct of_device_id bcm63138_nand_of_match[] = { ++ { .compatible = "brcm,nand-bcm63138" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm63138_nand_of_match); ++ ++static struct platform_driver bcm63138_nand_driver = { ++ .probe = bcm63138_nand_probe, ++ .remove = brcmnand_remove, ++ .driver = { ++ .name = "bcm63138_nand", ++ .pm = &brcmnand_pm_ops, ++ .of_match_table = bcm63138_nand_of_match, ++ } ++}; ++module_platform_driver(bcm63138_nand_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Brian Norris"); ++MODULE_DESCRIPTION("NAND driver for BCM63138"); +--- /dev/null ++++ b/drivers/mtd/nand/brcmnand/brcmnand.c +@@ -0,0 +1,2246 @@ ++/* ++ * Copyright © 2010-2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "brcmnand.h" ++ ++/* ++ * This flag controls if WP stays on between erase/write commands to mitigate ++ * flash corruption due to power glitches. Values: ++ * 0: NAND_WP is not used or not available ++ * 1: NAND_WP is set by default, cleared for erase/write operations ++ * 2: NAND_WP is always cleared ++ */ ++static int wp_on = 1; ++module_param(wp_on, int, 0444); ++ ++/*********************************************************************** ++ * Definitions ++ ***********************************************************************/ ++ ++#define DRV_NAME "brcmnand" ++ ++#define CMD_NULL 0x00 ++#define CMD_PAGE_READ 0x01 ++#define CMD_SPARE_AREA_READ 0x02 ++#define CMD_STATUS_READ 0x03 ++#define CMD_PROGRAM_PAGE 0x04 ++#define CMD_PROGRAM_SPARE_AREA 0x05 ++#define CMD_COPY_BACK 0x06 ++#define CMD_DEVICE_ID_READ 0x07 ++#define CMD_BLOCK_ERASE 0x08 ++#define CMD_FLASH_RESET 0x09 ++#define CMD_BLOCKS_LOCK 0x0a ++#define CMD_BLOCKS_LOCK_DOWN 0x0b ++#define CMD_BLOCKS_UNLOCK 0x0c ++#define CMD_READ_BLOCKS_LOCK_STATUS 0x0d ++#define CMD_PARAMETER_READ 0x0e ++#define CMD_PARAMETER_CHANGE_COL 0x0f ++#define CMD_LOW_LEVEL_OP 0x10 ++ ++struct brcm_nand_dma_desc { ++ u32 next_desc; ++ u32 next_desc_ext; ++ u32 cmd_irq; ++ u32 dram_addr; ++ u32 dram_addr_ext; ++ u32 tfr_len; ++ u32 total_len; ++ u32 flash_addr; ++ u32 flash_addr_ext; ++ u32 cs; ++ u32 pad2[5]; ++ u32 status_valid; ++} __packed; ++ ++/* Bitfields for brcm_nand_dma_desc::status_valid */ ++#define FLASH_DMA_ECC_ERROR (1 << 8) ++#define FLASH_DMA_CORR_ERROR (1 << 9) ++ ++/* 512B flash cache in the NAND controller HW */ ++#define FC_SHIFT 9U ++#define FC_BYTES 512U ++#define FC_WORDS (FC_BYTES >> 2) ++ ++#define BRCMNAND_MIN_PAGESIZE 512 ++#define BRCMNAND_MIN_BLOCKSIZE (8 * 1024) ++#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) ++ ++/* Controller feature flags */ ++enum { ++ BRCMNAND_HAS_1K_SECTORS = BIT(0), ++ BRCMNAND_HAS_PREFETCH = BIT(1), ++ BRCMNAND_HAS_CACHE_MODE = BIT(2), ++ BRCMNAND_HAS_WP = BIT(3), ++}; ++ ++struct brcmnand_controller { ++ struct device *dev; ++ struct nand_hw_control controller; ++ void __iomem *nand_base; ++ void __iomem *nand_fc; /* flash cache */ ++ void __iomem *flash_dma_base; ++ unsigned int irq; ++ unsigned int dma_irq; ++ int nand_version; ++ ++ /* Some SoCs provide custom interrupt status register(s) */ ++ struct brcmnand_soc *soc; ++ ++ int cmd_pending; ++ bool dma_pending; ++ struct completion done; ++ struct completion dma_done; ++ ++ /* List of NAND hosts (one for each chip-select) */ ++ struct list_head host_list; ++ ++ struct brcm_nand_dma_desc *dma_desc; ++ dma_addr_t dma_pa; ++ ++ /* in-memory cache of the FLASH_CACHE, used only for some commands */ ++ u32 flash_cache[FC_WORDS]; ++ ++ /* Controller revision details */ ++ const u16 *reg_offsets; ++ unsigned int reg_spacing; /* between CS1, CS2, ... regs */ ++ const u8 *cs_offsets; /* within each chip-select */ ++ const u8 *cs0_offsets; /* within CS0, if different */ ++ unsigned int max_block_size; ++ const unsigned int *block_sizes; ++ unsigned int max_page_size; ++ const unsigned int *page_sizes; ++ unsigned int max_oob; ++ u32 features; ++ ++ /* for low-power standby/resume only */ ++ u32 nand_cs_nand_select; ++ u32 nand_cs_nand_xor; ++ u32 corr_stat_threshold; ++ u32 flash_dma_mode; ++}; ++ ++struct brcmnand_cfg { ++ u64 device_size; ++ unsigned int block_size; ++ unsigned int page_size; ++ unsigned int spare_area_size; ++ unsigned int device_width; ++ unsigned int col_adr_bytes; ++ unsigned int blk_adr_bytes; ++ unsigned int ful_adr_bytes; ++ unsigned int sector_size_1k; ++ unsigned int ecc_level; ++ /* use for low-power standby/resume only */ ++ u32 acc_control; ++ u32 config; ++ u32 config_ext; ++ u32 timing_1; ++ u32 timing_2; ++}; ++ ++struct brcmnand_host { ++ struct list_head node; ++ struct device_node *of_node; ++ ++ struct nand_chip chip; ++ struct mtd_info mtd; ++ struct platform_device *pdev; ++ int cs; ++ ++ unsigned int last_cmd; ++ unsigned int last_byte; ++ u64 last_addr; ++ struct brcmnand_cfg hwcfg; ++ struct brcmnand_controller *ctrl; ++}; ++ ++enum brcmnand_reg { ++ BRCMNAND_CMD_START = 0, ++ BRCMNAND_CMD_EXT_ADDRESS, ++ BRCMNAND_CMD_ADDRESS, ++ BRCMNAND_INTFC_STATUS, ++ BRCMNAND_CS_SELECT, ++ BRCMNAND_CS_XOR, ++ BRCMNAND_LL_OP, ++ BRCMNAND_CS0_BASE, ++ BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */ ++ BRCMNAND_CORR_THRESHOLD, ++ BRCMNAND_CORR_THRESHOLD_EXT, ++ BRCMNAND_UNCORR_COUNT, ++ BRCMNAND_CORR_COUNT, ++ BRCMNAND_CORR_EXT_ADDR, ++ BRCMNAND_CORR_ADDR, ++ BRCMNAND_UNCORR_EXT_ADDR, ++ BRCMNAND_UNCORR_ADDR, ++ BRCMNAND_SEMAPHORE, ++ BRCMNAND_ID, ++ BRCMNAND_ID_EXT, ++ BRCMNAND_LL_RDATA, ++ BRCMNAND_OOB_READ_BASE, ++ BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */ ++ BRCMNAND_OOB_WRITE_BASE, ++ BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */ ++ BRCMNAND_FC_BASE, ++}; ++ ++/* BRCMNAND v4.0 */ ++static const u16 brcmnand_regs_v40[] = { ++ [BRCMNAND_CMD_START] = 0x04, ++ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, ++ [BRCMNAND_CMD_ADDRESS] = 0x0c, ++ [BRCMNAND_INTFC_STATUS] = 0x6c, ++ [BRCMNAND_CS_SELECT] = 0x14, ++ [BRCMNAND_CS_XOR] = 0x18, ++ [BRCMNAND_LL_OP] = 0x178, ++ [BRCMNAND_CS0_BASE] = 0x40, ++ [BRCMNAND_CS1_BASE] = 0xd0, ++ [BRCMNAND_CORR_THRESHOLD] = 0x84, ++ [BRCMNAND_CORR_THRESHOLD_EXT] = 0, ++ [BRCMNAND_UNCORR_COUNT] = 0, ++ [BRCMNAND_CORR_COUNT] = 0, ++ [BRCMNAND_CORR_EXT_ADDR] = 0x70, ++ [BRCMNAND_CORR_ADDR] = 0x74, ++ [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, ++ [BRCMNAND_UNCORR_ADDR] = 0x7c, ++ [BRCMNAND_SEMAPHORE] = 0x58, ++ [BRCMNAND_ID] = 0x60, ++ [BRCMNAND_ID_EXT] = 0x64, ++ [BRCMNAND_LL_RDATA] = 0x17c, ++ [BRCMNAND_OOB_READ_BASE] = 0x20, ++ [BRCMNAND_OOB_READ_10_BASE] = 0x130, ++ [BRCMNAND_OOB_WRITE_BASE] = 0x30, ++ [BRCMNAND_OOB_WRITE_10_BASE] = 0, ++ [BRCMNAND_FC_BASE] = 0x200, ++}; ++ ++/* BRCMNAND v5.0 */ ++static const u16 brcmnand_regs_v50[] = { ++ [BRCMNAND_CMD_START] = 0x04, ++ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, ++ [BRCMNAND_CMD_ADDRESS] = 0x0c, ++ [BRCMNAND_INTFC_STATUS] = 0x6c, ++ [BRCMNAND_CS_SELECT] = 0x14, ++ [BRCMNAND_CS_XOR] = 0x18, ++ [BRCMNAND_LL_OP] = 0x178, ++ [BRCMNAND_CS0_BASE] = 0x40, ++ [BRCMNAND_CS1_BASE] = 0xd0, ++ [BRCMNAND_CORR_THRESHOLD] = 0x84, ++ [BRCMNAND_CORR_THRESHOLD_EXT] = 0, ++ [BRCMNAND_UNCORR_COUNT] = 0, ++ [BRCMNAND_CORR_COUNT] = 0, ++ [BRCMNAND_CORR_EXT_ADDR] = 0x70, ++ [BRCMNAND_CORR_ADDR] = 0x74, ++ [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, ++ [BRCMNAND_UNCORR_ADDR] = 0x7c, ++ [BRCMNAND_SEMAPHORE] = 0x58, ++ [BRCMNAND_ID] = 0x60, ++ [BRCMNAND_ID_EXT] = 0x64, ++ [BRCMNAND_LL_RDATA] = 0x17c, ++ [BRCMNAND_OOB_READ_BASE] = 0x20, ++ [BRCMNAND_OOB_READ_10_BASE] = 0x130, ++ [BRCMNAND_OOB_WRITE_BASE] = 0x30, ++ [BRCMNAND_OOB_WRITE_10_BASE] = 0x140, ++ [BRCMNAND_FC_BASE] = 0x200, ++}; ++ ++/* BRCMNAND v6.0 - v7.1 */ ++static const u16 brcmnand_regs_v60[] = { ++ [BRCMNAND_CMD_START] = 0x04, ++ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, ++ [BRCMNAND_CMD_ADDRESS] = 0x0c, ++ [BRCMNAND_INTFC_STATUS] = 0x14, ++ [BRCMNAND_CS_SELECT] = 0x18, ++ [BRCMNAND_CS_XOR] = 0x1c, ++ [BRCMNAND_LL_OP] = 0x20, ++ [BRCMNAND_CS0_BASE] = 0x50, ++ [BRCMNAND_CS1_BASE] = 0, ++ [BRCMNAND_CORR_THRESHOLD] = 0xc0, ++ [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4, ++ [BRCMNAND_UNCORR_COUNT] = 0xfc, ++ [BRCMNAND_CORR_COUNT] = 0x100, ++ [BRCMNAND_CORR_EXT_ADDR] = 0x10c, ++ [BRCMNAND_CORR_ADDR] = 0x110, ++ [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, ++ [BRCMNAND_UNCORR_ADDR] = 0x118, ++ [BRCMNAND_SEMAPHORE] = 0x150, ++ [BRCMNAND_ID] = 0x194, ++ [BRCMNAND_ID_EXT] = 0x198, ++ [BRCMNAND_LL_RDATA] = 0x19c, ++ [BRCMNAND_OOB_READ_BASE] = 0x200, ++ [BRCMNAND_OOB_READ_10_BASE] = 0, ++ [BRCMNAND_OOB_WRITE_BASE] = 0x280, ++ [BRCMNAND_OOB_WRITE_10_BASE] = 0, ++ [BRCMNAND_FC_BASE] = 0x400, ++}; ++ ++enum brcmnand_cs_reg { ++ BRCMNAND_CS_CFG_EXT = 0, ++ BRCMNAND_CS_CFG, ++ BRCMNAND_CS_ACC_CONTROL, ++ BRCMNAND_CS_TIMING1, ++ BRCMNAND_CS_TIMING2, ++}; ++ ++/* Per chip-select offsets for v7.1 */ ++static const u8 brcmnand_cs_offsets_v71[] = { ++ [BRCMNAND_CS_ACC_CONTROL] = 0x00, ++ [BRCMNAND_CS_CFG_EXT] = 0x04, ++ [BRCMNAND_CS_CFG] = 0x08, ++ [BRCMNAND_CS_TIMING1] = 0x0c, ++ [BRCMNAND_CS_TIMING2] = 0x10, ++}; ++ ++/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */ ++static const u8 brcmnand_cs_offsets[] = { ++ [BRCMNAND_CS_ACC_CONTROL] = 0x00, ++ [BRCMNAND_CS_CFG_EXT] = 0x04, ++ [BRCMNAND_CS_CFG] = 0x04, ++ [BRCMNAND_CS_TIMING1] = 0x08, ++ [BRCMNAND_CS_TIMING2] = 0x0c, ++}; ++ ++/* Per chip-select offset for <= v5.0 on CS0 only */ ++static const u8 brcmnand_cs_offsets_cs0[] = { ++ [BRCMNAND_CS_ACC_CONTROL] = 0x00, ++ [BRCMNAND_CS_CFG_EXT] = 0x08, ++ [BRCMNAND_CS_CFG] = 0x08, ++ [BRCMNAND_CS_TIMING1] = 0x10, ++ [BRCMNAND_CS_TIMING2] = 0x14, ++}; ++ ++/* BRCMNAND_INTFC_STATUS */ ++enum { ++ INTFC_FLASH_STATUS = GENMASK(7, 0), ++ ++ INTFC_ERASED = BIT(27), ++ INTFC_OOB_VALID = BIT(28), ++ INTFC_CACHE_VALID = BIT(29), ++ INTFC_FLASH_READY = BIT(30), ++ INTFC_CTLR_READY = BIT(31), ++}; ++ ++static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) ++{ ++ return brcmnand_readl(ctrl->nand_base + offs); ++} ++ ++static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, ++ u32 val) ++{ ++ brcmnand_writel(val, ctrl->nand_base + offs); ++} ++ ++static int brcmnand_revision_init(struct brcmnand_controller *ctrl) ++{ ++ static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 }; ++ static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 }; ++ static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 }; ++ ++ ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; ++ ++ /* Only support v4.0+? */ ++ if (ctrl->nand_version < 0x0400) { ++ dev_err(ctrl->dev, "version %#x not supported\n", ++ ctrl->nand_version); ++ return -ENODEV; ++ } ++ ++ /* Register offsets */ ++ if (ctrl->nand_version >= 0x0600) ++ ctrl->reg_offsets = brcmnand_regs_v60; ++ else if (ctrl->nand_version >= 0x0500) ++ ctrl->reg_offsets = brcmnand_regs_v50; ++ else if (ctrl->nand_version >= 0x0400) ++ ctrl->reg_offsets = brcmnand_regs_v40; ++ ++ /* Chip-select stride */ ++ if (ctrl->nand_version >= 0x0701) ++ ctrl->reg_spacing = 0x14; ++ else ++ ctrl->reg_spacing = 0x10; ++ ++ /* Per chip-select registers */ ++ if (ctrl->nand_version >= 0x0701) { ++ ctrl->cs_offsets = brcmnand_cs_offsets_v71; ++ } else { ++ ctrl->cs_offsets = brcmnand_cs_offsets; ++ ++ /* v5.0 and earlier has a different CS0 offset layout */ ++ if (ctrl->nand_version <= 0x0500) ++ ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; ++ } ++ ++ /* Page / block sizes */ ++ if (ctrl->nand_version >= 0x0701) { ++ /* >= v7.1 use nice power-of-2 values! */ ++ ctrl->max_page_size = 16 * 1024; ++ ctrl->max_block_size = 2 * 1024 * 1024; ++ } else { ++ ctrl->page_sizes = page_sizes; ++ if (ctrl->nand_version >= 0x0600) ++ ctrl->block_sizes = block_sizes_v6; ++ else ++ ctrl->block_sizes = block_sizes_v4; ++ ++ if (ctrl->nand_version < 0x0400) { ++ ctrl->max_page_size = 4096; ++ ctrl->max_block_size = 512 * 1024; ++ } ++ } ++ ++ /* Maximum spare area sector size (per 512B) */ ++ if (ctrl->nand_version >= 0x0600) ++ ctrl->max_oob = 64; ++ else if (ctrl->nand_version >= 0x0500) ++ ctrl->max_oob = 32; ++ else ++ ctrl->max_oob = 16; ++ ++ /* v6.0 and newer (except v6.1) have prefetch support */ ++ if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) ++ ctrl->features |= BRCMNAND_HAS_PREFETCH; ++ ++ /* ++ * v6.x has cache mode, but it's implemented differently. Ignore it for ++ * now. ++ */ ++ if (ctrl->nand_version >= 0x0700) ++ ctrl->features |= BRCMNAND_HAS_CACHE_MODE; ++ ++ if (ctrl->nand_version >= 0x0500) ++ ctrl->features |= BRCMNAND_HAS_1K_SECTORS; ++ ++ if (ctrl->nand_version >= 0x0700) ++ ctrl->features |= BRCMNAND_HAS_WP; ++ else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) ++ ctrl->features |= BRCMNAND_HAS_WP; ++ ++ return 0; ++} ++ ++static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, ++ enum brcmnand_reg reg) ++{ ++ u16 offs = ctrl->reg_offsets[reg]; ++ ++ if (offs) ++ return nand_readreg(ctrl, offs); ++ else ++ return 0; ++} ++ ++static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, ++ enum brcmnand_reg reg, u32 val) ++{ ++ u16 offs = ctrl->reg_offsets[reg]; ++ ++ if (offs) ++ nand_writereg(ctrl, offs, val); ++} ++ ++static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, ++ enum brcmnand_reg reg, u32 mask, unsigned ++ int shift, u32 val) ++{ ++ u32 tmp = brcmnand_read_reg(ctrl, reg); ++ ++ tmp &= ~mask; ++ tmp |= val << shift; ++ brcmnand_write_reg(ctrl, reg, tmp); ++} ++ ++static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) ++{ ++ return __raw_readl(ctrl->nand_fc + word * 4); ++} ++ ++static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, ++ int word, u32 val) ++{ ++ __raw_writel(val, ctrl->nand_fc + word * 4); ++} ++ ++static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, ++ enum brcmnand_cs_reg reg) ++{ ++ u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; ++ u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; ++ u8 cs_offs; ++ ++ if (cs == 0 && ctrl->cs0_offsets) ++ cs_offs = ctrl->cs0_offsets[reg]; ++ else ++ cs_offs = ctrl->cs_offsets[reg]; ++ ++ if (cs && offs_cs1) ++ return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; ++ ++ return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; ++} ++ ++static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) ++{ ++ if (ctrl->nand_version < 0x0600) ++ return 1; ++ return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); ++} ++ ++static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ unsigned int shift = 0, bits; ++ enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; ++ int cs = host->cs; ++ ++ if (ctrl->nand_version >= 0x0600) ++ bits = 6; ++ else if (ctrl->nand_version >= 0x0500) ++ bits = 5; ++ else ++ bits = 4; ++ ++ if (ctrl->nand_version >= 0x0600) { ++ if (cs >= 5) ++ reg = BRCMNAND_CORR_THRESHOLD_EXT; ++ shift = (cs % 5) * bits; ++ } ++ brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); ++} ++ ++static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) ++{ ++ if (ctrl->nand_version < 0x0700) ++ return 24; ++ return 0; ++} ++ ++/*********************************************************************** ++ * NAND ACC CONTROL bitfield ++ * ++ * Some bits have remained constant throughout hardware revision, while ++ * others have shifted around. ++ ***********************************************************************/ ++ ++/* Constant for all versions (where supported) */ ++enum { ++ /* See BRCMNAND_HAS_CACHE_MODE */ ++ ACC_CONTROL_CACHE_MODE = BIT(22), ++ ++ /* See BRCMNAND_HAS_PREFETCH */ ++ ACC_CONTROL_PREFETCH = BIT(23), ++ ++ ACC_CONTROL_PAGE_HIT = BIT(24), ++ ACC_CONTROL_WR_PREEMPT = BIT(25), ++ ACC_CONTROL_PARTIAL_PAGE = BIT(26), ++ ACC_CONTROL_RD_ERASED = BIT(27), ++ ACC_CONTROL_FAST_PGM_RDIN = BIT(28), ++ ACC_CONTROL_WR_ECC = BIT(30), ++ ACC_CONTROL_RD_ECC = BIT(31), ++}; ++ ++static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) ++{ ++ if (ctrl->nand_version >= 0x0600) ++ return GENMASK(6, 0); ++ else ++ return GENMASK(5, 0); ++} ++ ++#define NAND_ACC_CONTROL_ECC_SHIFT 16 ++ ++static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) ++{ ++ u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; ++ ++ return mask << NAND_ACC_CONTROL_ECC_SHIFT; ++} ++ ++static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); ++ u32 acc_control = nand_readreg(ctrl, offs); ++ u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC; ++ ++ if (en) { ++ acc_control |= ecc_flags; /* enable RD/WR ECC */ ++ acc_control |= host->hwcfg.ecc_level ++ << NAND_ACC_CONTROL_ECC_SHIFT; ++ } else { ++ acc_control &= ~ecc_flags; /* disable RD/WR ECC */ ++ acc_control &= ~brcmnand_ecc_level_mask(ctrl); ++ } ++ ++ nand_writereg(ctrl, offs, acc_control); ++} ++ ++static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) ++{ ++ if (ctrl->nand_version >= 0x0600) ++ return 7; ++ else if (ctrl->nand_version >= 0x0500) ++ return 6; ++ else ++ return -1; ++} ++ ++static int brcmnand_get_sector_size_1k(struct brcmnand_host *host) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ int shift = brcmnand_sector_1k_shift(ctrl); ++ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, ++ BRCMNAND_CS_ACC_CONTROL); ++ ++ if (shift < 0) ++ return 0; ++ ++ return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; ++} ++ ++static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ int shift = brcmnand_sector_1k_shift(ctrl); ++ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, ++ BRCMNAND_CS_ACC_CONTROL); ++ u32 tmp; ++ ++ if (shift < 0) ++ return; ++ ++ tmp = nand_readreg(ctrl, acc_control_offs); ++ tmp &= ~(1 << shift); ++ tmp |= (!!val) << shift; ++ nand_writereg(ctrl, acc_control_offs, tmp); ++} ++ ++/*********************************************************************** ++ * CS_NAND_SELECT ++ ***********************************************************************/ ++ ++enum { ++ CS_SELECT_NAND_WP = BIT(29), ++ CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), ++}; ++ ++static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) ++{ ++ u32 val = en ? CS_SELECT_NAND_WP : 0; ++ ++ brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); ++} ++ ++/*********************************************************************** ++ * Flash DMA ++ ***********************************************************************/ ++ ++enum flash_dma_reg { ++ FLASH_DMA_REVISION = 0x00, ++ FLASH_DMA_FIRST_DESC = 0x04, ++ FLASH_DMA_FIRST_DESC_EXT = 0x08, ++ FLASH_DMA_CTRL = 0x0c, ++ FLASH_DMA_MODE = 0x10, ++ FLASH_DMA_STATUS = 0x14, ++ FLASH_DMA_INTERRUPT_DESC = 0x18, ++ FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c, ++ FLASH_DMA_ERROR_STATUS = 0x20, ++ FLASH_DMA_CURRENT_DESC = 0x24, ++ FLASH_DMA_CURRENT_DESC_EXT = 0x28, ++}; ++ ++static inline bool has_flash_dma(struct brcmnand_controller *ctrl) ++{ ++ return ctrl->flash_dma_base; ++} ++ ++static inline bool flash_dma_buf_ok(const void *buf) ++{ ++ return buf && !is_vmalloc_addr(buf) && ++ likely(IS_ALIGNED((uintptr_t)buf, 4)); ++} ++ ++static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs, ++ u32 val) ++{ ++ brcmnand_writel(val, ctrl->flash_dma_base + offs); ++} ++ ++static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs) ++{ ++ return brcmnand_readl(ctrl->flash_dma_base + offs); ++} ++ ++/* Low-level operation types: command, address, write, or read */ ++enum brcmnand_llop_type { ++ LL_OP_CMD, ++ LL_OP_ADDR, ++ LL_OP_WR, ++ LL_OP_RD, ++}; ++ ++/*********************************************************************** ++ * Internal support functions ++ ***********************************************************************/ ++ ++static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg) ++{ ++ return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && ++ cfg->ecc_level == 15; ++} ++ ++/* ++ * Returns a nand_ecclayout strucutre for the given layout/configuration. ++ * Returns NULL on failure. ++ */ ++static struct nand_ecclayout *brcmnand_create_layout(int ecc_level, ++ struct brcmnand_host *host) ++{ ++ struct brcmnand_cfg *cfg = &host->hwcfg; ++ int i, j; ++ struct nand_ecclayout *layout; ++ int req; ++ int sectors; ++ int sas; ++ int idx1, idx2; ++ ++ layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL); ++ if (!layout) ++ return NULL; ++ ++ sectors = cfg->page_size / (512 << cfg->sector_size_1k); ++ sas = cfg->spare_area_size << cfg->sector_size_1k; ++ ++ /* Hamming */ ++ if (is_hamming_ecc(cfg)) { ++ for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) { ++ /* First sector of each page may have BBI */ ++ if (i == 0) { ++ layout->oobfree[idx2].offset = i * sas + 1; ++ /* Small-page NAND use byte 6 for BBI */ ++ if (cfg->page_size == 512) ++ layout->oobfree[idx2].offset--; ++ layout->oobfree[idx2].length = 5; ++ } else { ++ layout->oobfree[idx2].offset = i * sas; ++ layout->oobfree[idx2].length = 6; ++ } ++ idx2++; ++ layout->eccpos[idx1++] = i * sas + 6; ++ layout->eccpos[idx1++] = i * sas + 7; ++ layout->eccpos[idx1++] = i * sas + 8; ++ layout->oobfree[idx2].offset = i * sas + 9; ++ layout->oobfree[idx2].length = 7; ++ idx2++; ++ /* Leave zero-terminated entry for OOBFREE */ ++ if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE || ++ idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1) ++ break; ++ } ++ goto out; ++ } ++ ++ /* ++ * CONTROLLER_VERSION: ++ * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) ++ * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) ++ * But we will just be conservative. ++ */ ++ req = DIV_ROUND_UP(ecc_level * 14, 8); ++ if (req >= sas) { ++ dev_err(&host->pdev->dev, ++ "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", ++ req, sas); ++ return NULL; ++ } ++ ++ layout->eccbytes = req * sectors; ++ for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) { ++ for (j = sas - req; j < sas && idx1 < ++ MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++) ++ layout->eccpos[idx1] = i * sas + j; ++ ++ /* First sector of each page may have BBI */ ++ if (i == 0) { ++ if (cfg->page_size == 512 && (sas - req >= 6)) { ++ /* Small-page NAND use byte 6 for BBI */ ++ layout->oobfree[idx2].offset = 0; ++ layout->oobfree[idx2].length = 5; ++ idx2++; ++ if (sas - req > 6) { ++ layout->oobfree[idx2].offset = 6; ++ layout->oobfree[idx2].length = ++ sas - req - 6; ++ idx2++; ++ } ++ } else if (sas > req + 1) { ++ layout->oobfree[idx2].offset = i * sas + 1; ++ layout->oobfree[idx2].length = sas - req - 1; ++ idx2++; ++ } ++ } else if (sas > req) { ++ layout->oobfree[idx2].offset = i * sas; ++ layout->oobfree[idx2].length = sas - req; ++ idx2++; ++ } ++ /* Leave zero-terminated entry for OOBFREE */ ++ if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE || ++ idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1) ++ break; ++ } ++out: ++ /* Sum available OOB */ ++ for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++) ++ layout->oobavail += layout->oobfree[i].length; ++ return layout; ++} ++ ++static struct nand_ecclayout *brcmstb_choose_ecc_layout( ++ struct brcmnand_host *host) ++{ ++ struct nand_ecclayout *layout; ++ struct brcmnand_cfg *p = &host->hwcfg; ++ unsigned int ecc_level = p->ecc_level; ++ ++ if (p->sector_size_1k) ++ ecc_level <<= 1; ++ ++ layout = brcmnand_create_layout(ecc_level, host); ++ if (!layout) { ++ dev_err(&host->pdev->dev, ++ "no proper ecc_layout for this NAND cfg\n"); ++ return NULL; ++ } ++ ++ return layout; ++} ++ ++static void brcmnand_wp(struct mtd_info *mtd, int wp) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct brcmnand_host *host = chip->priv; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ ++ if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { ++ static int old_wp = -1; ++ ++ if (old_wp != wp) { ++ dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); ++ old_wp = wp; ++ } ++ brcmnand_set_wp(ctrl, wp); ++ } ++} ++ ++/* Helper functions for reading and writing OOB registers */ ++static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) ++{ ++ u16 offset0, offset10, reg_offs; ++ ++ offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; ++ offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; ++ ++ if (offs >= ctrl->max_oob) ++ return 0x77; ++ ++ if (offs >= 16 && offset10) ++ reg_offs = offset10 + ((offs - 0x10) & ~0x03); ++ else ++ reg_offs = offset0 + (offs & ~0x03); ++ ++ return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); ++} ++ ++static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, ++ u32 data) ++{ ++ u16 offset0, offset10, reg_offs; ++ ++ offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; ++ offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; ++ ++ if (offs >= ctrl->max_oob) ++ return; ++ ++ if (offs >= 16 && offset10) ++ reg_offs = offset10 + ((offs - 0x10) & ~0x03); ++ else ++ reg_offs = offset0 + (offs & ~0x03); ++ ++ nand_writereg(ctrl, reg_offs, data); ++} ++ ++/* ++ * read_oob_from_regs - read data from OOB registers ++ * @ctrl: NAND controller ++ * @i: sub-page sector index ++ * @oob: buffer to read to ++ * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) ++ * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal ++ */ ++static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, ++ int sas, int sector_1k) ++{ ++ int tbytes = sas << sector_1k; ++ int j; ++ ++ /* Adjust OOB values for 1K sector size */ ++ if (sector_1k && (i & 0x01)) ++ tbytes = max(0, tbytes - (int)ctrl->max_oob); ++ tbytes = min_t(int, tbytes, ctrl->max_oob); ++ ++ for (j = 0; j < tbytes; j++) ++ oob[j] = oob_reg_read(ctrl, j); ++ return tbytes; ++} ++ ++/* ++ * write_oob_to_regs - write data to OOB registers ++ * @i: sub-page sector index ++ * @oob: buffer to write from ++ * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) ++ * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal ++ */ ++static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, ++ const u8 *oob, int sas, int sector_1k) ++{ ++ int tbytes = sas << sector_1k; ++ int j; ++ ++ /* Adjust OOB values for 1K sector size */ ++ if (sector_1k && (i & 0x01)) ++ tbytes = max(0, tbytes - (int)ctrl->max_oob); ++ tbytes = min_t(int, tbytes, ctrl->max_oob); ++ ++ for (j = 0; j < tbytes; j += 4) ++ oob_reg_write(ctrl, j, ++ (oob[j + 0] << 24) | ++ (oob[j + 1] << 16) | ++ (oob[j + 2] << 8) | ++ (oob[j + 3] << 0)); ++ return tbytes; ++} ++ ++static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) ++{ ++ struct brcmnand_controller *ctrl = data; ++ ++ /* Discard all NAND_CTLRDY interrupts during DMA */ ++ if (ctrl->dma_pending) ++ return IRQ_HANDLED; ++ ++ complete(&ctrl->done); ++ return IRQ_HANDLED; ++} ++ ++/* Handle SoC-specific interrupt hardware */ ++static irqreturn_t brcmnand_irq(int irq, void *data) ++{ ++ struct brcmnand_controller *ctrl = data; ++ ++ if (ctrl->soc->ctlrdy_ack(ctrl->soc)) ++ return brcmnand_ctlrdy_irq(irq, data); ++ ++ return IRQ_NONE; ++} ++ ++static irqreturn_t brcmnand_dma_irq(int irq, void *data) ++{ ++ struct brcmnand_controller *ctrl = data; ++ ++ complete(&ctrl->dma_done); ++ ++ return IRQ_HANDLED; ++} ++ ++static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ u32 intfc; ++ ++ dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd, ++ brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS)); ++ BUG_ON(ctrl->cmd_pending != 0); ++ ctrl->cmd_pending = cmd; ++ ++ intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); ++ BUG_ON(!(intfc & INTFC_CTLR_READY)); ++ ++ mb(); /* flush previous writes */ ++ brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, ++ cmd << brcmnand_cmd_shift(ctrl)); ++} ++ ++/*********************************************************************** ++ * NAND MTD API: read/program/erase ++ ***********************************************************************/ ++ ++static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat, ++ unsigned int ctrl) ++{ ++ /* intentionally left blank */ ++} ++ ++static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct brcmnand_host *host = chip->priv; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ unsigned long timeo = msecs_to_jiffies(100); ++ ++ dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); ++ if (ctrl->cmd_pending && ++ wait_for_completion_timeout(&ctrl->done, timeo) <= 0) { ++ u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) ++ >> brcmnand_cmd_shift(ctrl); ++ ++ dev_err_ratelimited(ctrl->dev, ++ "timeout waiting for command %#02x\n", cmd); ++ dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", ++ brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); ++ } ++ ctrl->cmd_pending = 0; ++ return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & ++ INTFC_FLASH_STATUS; ++} ++ ++enum { ++ LLOP_RE = BIT(16), ++ LLOP_WE = BIT(17), ++ LLOP_ALE = BIT(18), ++ LLOP_CLE = BIT(19), ++ LLOP_RETURN_IDLE = BIT(31), ++ ++ LLOP_DATA_MASK = GENMASK(15, 0), ++}; ++ ++static int brcmnand_low_level_op(struct brcmnand_host *host, ++ enum brcmnand_llop_type type, u32 data, ++ bool last_op) ++{ ++ struct mtd_info *mtd = &host->mtd; ++ struct nand_chip *chip = &host->chip; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ u32 tmp; ++ ++ tmp = data & LLOP_DATA_MASK; ++ switch (type) { ++ case LL_OP_CMD: ++ tmp |= LLOP_WE | LLOP_CLE; ++ break; ++ case LL_OP_ADDR: ++ /* WE | ALE */ ++ tmp |= LLOP_WE | LLOP_ALE; ++ break; ++ case LL_OP_WR: ++ /* WE */ ++ tmp |= LLOP_WE; ++ break; ++ case LL_OP_RD: ++ /* RE */ ++ tmp |= LLOP_RE; ++ break; ++ } ++ if (last_op) ++ /* RETURN_IDLE */ ++ tmp |= LLOP_RETURN_IDLE; ++ ++ dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); ++ ++ brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); ++ (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); ++ ++ brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP); ++ return brcmnand_waitfunc(mtd, chip); ++} ++ ++static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, ++ int column, int page_addr) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct brcmnand_host *host = chip->priv; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ u64 addr = (u64)page_addr << chip->page_shift; ++ int native_cmd = 0; ++ ++ if (command == NAND_CMD_READID || command == NAND_CMD_PARAM || ++ command == NAND_CMD_RNDOUT) ++ addr = (u64)column; ++ /* Avoid propagating a negative, don't-care address */ ++ else if (page_addr < 0) ++ addr = 0; ++ ++ dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, ++ (unsigned long long)addr); ++ ++ host->last_cmd = command; ++ host->last_byte = 0; ++ host->last_addr = addr; ++ ++ switch (command) { ++ case NAND_CMD_RESET: ++ native_cmd = CMD_FLASH_RESET; ++ break; ++ case NAND_CMD_STATUS: ++ native_cmd = CMD_STATUS_READ; ++ break; ++ case NAND_CMD_READID: ++ native_cmd = CMD_DEVICE_ID_READ; ++ break; ++ case NAND_CMD_READOOB: ++ native_cmd = CMD_SPARE_AREA_READ; ++ break; ++ case NAND_CMD_ERASE1: ++ native_cmd = CMD_BLOCK_ERASE; ++ brcmnand_wp(mtd, 0); ++ break; ++ case NAND_CMD_PARAM: ++ native_cmd = CMD_PARAMETER_READ; ++ break; ++ case NAND_CMD_SET_FEATURES: ++ case NAND_CMD_GET_FEATURES: ++ brcmnand_low_level_op(host, LL_OP_CMD, command, false); ++ brcmnand_low_level_op(host, LL_OP_ADDR, column, false); ++ break; ++ case NAND_CMD_RNDOUT: ++ native_cmd = CMD_PARAMETER_CHANGE_COL; ++ addr &= ~((u64)(FC_BYTES - 1)); ++ /* ++ * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0 ++ * NB: hwcfg.sector_size_1k may not be initialized yet ++ */ ++ if (brcmnand_get_sector_size_1k(host)) { ++ host->hwcfg.sector_size_1k = ++ brcmnand_get_sector_size_1k(host); ++ brcmnand_set_sector_size_1k(host, 0); ++ } ++ break; ++ } ++ ++ if (!native_cmd) ++ return; ++ ++ brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, ++ (host->cs << 16) | ((addr >> 32) & 0xffff)); ++ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); ++ brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr)); ++ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); ++ ++ brcmnand_send_cmd(host, native_cmd); ++ brcmnand_waitfunc(mtd, chip); ++ ++ if (native_cmd == CMD_PARAMETER_READ || ++ native_cmd == CMD_PARAMETER_CHANGE_COL) { ++ int i; ++ ++ brcmnand_soc_data_bus_prepare(ctrl->soc); ++ ++ /* ++ * Must cache the FLASH_CACHE now, since changes in ++ * SECTOR_SIZE_1K may invalidate it ++ */ ++ for (i = 0; i < FC_WORDS; i++) ++ ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i); ++ ++ brcmnand_soc_data_bus_unprepare(ctrl->soc); ++ ++ /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */ ++ if (host->hwcfg.sector_size_1k) ++ brcmnand_set_sector_size_1k(host, ++ host->hwcfg.sector_size_1k); ++ } ++ ++ /* Re-enable protection is necessary only after erase */ ++ if (command == NAND_CMD_ERASE1) ++ brcmnand_wp(mtd, 1); ++} ++ ++static uint8_t brcmnand_read_byte(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct brcmnand_host *host = chip->priv; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ uint8_t ret = 0; ++ int addr, offs; ++ ++ switch (host->last_cmd) { ++ case NAND_CMD_READID: ++ if (host->last_byte < 4) ++ ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> ++ (24 - (host->last_byte << 3)); ++ else if (host->last_byte < 8) ++ ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> ++ (56 - (host->last_byte << 3)); ++ break; ++ ++ case NAND_CMD_READOOB: ++ ret = oob_reg_read(ctrl, host->last_byte); ++ break; ++ ++ case NAND_CMD_STATUS: ++ ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & ++ INTFC_FLASH_STATUS; ++ if (wp_on) /* hide WP status */ ++ ret |= NAND_STATUS_WP; ++ break; ++ ++ case NAND_CMD_PARAM: ++ case NAND_CMD_RNDOUT: ++ addr = host->last_addr + host->last_byte; ++ offs = addr & (FC_BYTES - 1); ++ ++ /* At FC_BYTES boundary, switch to next column */ ++ if (host->last_byte > 0 && offs == 0) ++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1); ++ ++ ret = ctrl->flash_cache[offs >> 2] >> ++ (24 - ((offs & 0x03) << 3)); ++ break; ++ case NAND_CMD_GET_FEATURES: ++ if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { ++ ret = 0; ++ } else { ++ bool last = host->last_byte == ++ ONFI_SUBFEATURE_PARAM_LEN - 1; ++ brcmnand_low_level_op(host, LL_OP_RD, 0, last); ++ ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; ++ } ++ } ++ ++ dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); ++ host->last_byte++; ++ ++ return ret; ++} ++ ++static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) ++{ ++ int i; ++ ++ for (i = 0; i < len; i++, buf++) ++ *buf = brcmnand_read_byte(mtd); ++} ++ ++static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf, ++ int len) ++{ ++ int i; ++ struct nand_chip *chip = mtd->priv; ++ struct brcmnand_host *host = chip->priv; ++ ++ switch (host->last_cmd) { ++ case NAND_CMD_SET_FEATURES: ++ for (i = 0; i < len; i++) ++ brcmnand_low_level_op(host, LL_OP_WR, buf[i], ++ (i + 1) == len); ++ break; ++ default: ++ BUG(); ++ break; ++ } ++} ++ ++/** ++ * Construct a FLASH_DMA descriptor as part of a linked list. You must know the ++ * following ahead of time: ++ * - Is this descriptor the beginning or end of a linked list? ++ * - What is the (DMA) address of the next descriptor in the linked list? ++ */ ++static int brcmnand_fill_dma_desc(struct brcmnand_host *host, ++ struct brcm_nand_dma_desc *desc, u64 addr, ++ dma_addr_t buf, u32 len, u8 dma_cmd, ++ bool begin, bool end, ++ dma_addr_t next_desc) ++{ ++ memset(desc, 0, sizeof(*desc)); ++ /* Descriptors are written in native byte order (wordwise) */ ++ desc->next_desc = lower_32_bits(next_desc); ++ desc->next_desc_ext = upper_32_bits(next_desc); ++ desc->cmd_irq = (dma_cmd << 24) | ++ (end ? (0x03 << 8) : 0) | /* IRQ | STOP */ ++ (!!begin) | ((!!end) << 1); /* head, tail */ ++#ifdef CONFIG_CPU_BIG_ENDIAN ++ desc->cmd_irq |= 0x01 << 12; ++#endif ++ desc->dram_addr = lower_32_bits(buf); ++ desc->dram_addr_ext = upper_32_bits(buf); ++ desc->tfr_len = len; ++ desc->total_len = len; ++ desc->flash_addr = lower_32_bits(addr); ++ desc->flash_addr_ext = upper_32_bits(addr); ++ desc->cs = host->cs; ++ desc->status_valid = 0x01; ++ return 0; ++} ++ ++/** ++ * Kick the FLASH_DMA engine, with a given DMA descriptor ++ */ ++static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ unsigned long timeo = msecs_to_jiffies(100); ++ ++ flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); ++ (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); ++ flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc)); ++ (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); ++ ++ /* Start FLASH_DMA engine */ ++ ctrl->dma_pending = true; ++ mb(); /* flush previous writes */ ++ flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ ++ ++ if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { ++ dev_err(ctrl->dev, ++ "timeout waiting for DMA; status %#x, error status %#x\n", ++ flash_dma_readl(ctrl, FLASH_DMA_STATUS), ++ flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); ++ } ++ ctrl->dma_pending = false; ++ flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ ++} ++ ++static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf, ++ u32 len, u8 dma_cmd) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ dma_addr_t buf_pa; ++ int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; ++ ++ buf_pa = dma_map_single(ctrl->dev, buf, len, dir); ++ if (dma_mapping_error(ctrl->dev, buf_pa)) { ++ dev_err(ctrl->dev, "unable to map buffer for DMA\n"); ++ return -ENOMEM; ++ } ++ ++ brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, ++ dma_cmd, true, true, 0); ++ ++ brcmnand_dma_run(host, ctrl->dma_pa); ++ ++ dma_unmap_single(ctrl->dev, buf_pa, len, dir); ++ ++ if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) ++ return -EBADMSG; ++ else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) ++ return -EUCLEAN; ++ ++ return 0; ++} ++ ++/* ++ * Assumes proper CS is already set ++ */ ++static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, ++ u64 addr, unsigned int trans, u32 *buf, ++ u8 *oob, u64 *err_addr) ++{ ++ struct brcmnand_host *host = chip->priv; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ int i, j, ret = 0; ++ ++ /* Clear error addresses */ ++ brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); ++ brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); ++ ++ brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, ++ (host->cs << 16) | ((addr >> 32) & 0xffff)); ++ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); ++ ++ for (i = 0; i < trans; i++, addr += FC_BYTES) { ++ brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, ++ lower_32_bits(addr)); ++ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); ++ /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ ++ brcmnand_send_cmd(host, CMD_PAGE_READ); ++ brcmnand_waitfunc(mtd, chip); ++ ++ if (likely(buf)) { ++ brcmnand_soc_data_bus_prepare(ctrl->soc); ++ ++ for (j = 0; j < FC_WORDS; j++, buf++) ++ *buf = brcmnand_read_fc(ctrl, j); ++ ++ brcmnand_soc_data_bus_unprepare(ctrl->soc); ++ } ++ ++ if (oob) ++ oob += read_oob_from_regs(ctrl, i, oob, ++ mtd->oobsize / trans, ++ host->hwcfg.sector_size_1k); ++ ++ if (!ret) { ++ *err_addr = brcmnand_read_reg(ctrl, ++ BRCMNAND_UNCORR_ADDR) | ++ ((u64)(brcmnand_read_reg(ctrl, ++ BRCMNAND_UNCORR_EXT_ADDR) ++ & 0xffff) << 32); ++ if (*err_addr) ++ ret = -EBADMSG; ++ } ++ ++ if (!ret) { ++ *err_addr = brcmnand_read_reg(ctrl, ++ BRCMNAND_CORR_ADDR) | ++ ((u64)(brcmnand_read_reg(ctrl, ++ BRCMNAND_CORR_EXT_ADDR) ++ & 0xffff) << 32); ++ if (*err_addr) ++ ret = -EUCLEAN; ++ } ++ } ++ ++ return ret; ++} ++ ++static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, ++ u64 addr, unsigned int trans, u32 *buf, u8 *oob) ++{ ++ struct brcmnand_host *host = chip->priv; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ u64 err_addr = 0; ++ int err; ++ ++ dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); ++ ++ brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0); ++ ++ if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { ++ err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES, ++ CMD_PAGE_READ); ++ if (err) { ++ if (mtd_is_bitflip_or_eccerr(err)) ++ err_addr = addr; ++ else ++ return -EIO; ++ } ++ } else { ++ if (oob) ++ memset(oob, 0x99, mtd->oobsize); ++ ++ err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, ++ oob, &err_addr); ++ } ++ ++ if (mtd_is_eccerr(err)) { ++ dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", ++ (unsigned long long)err_addr); ++ mtd->ecc_stats.failed++; ++ /* NAND layer expects zero on ECC errors */ ++ return 0; ++ } ++ ++ if (mtd_is_bitflip(err)) { ++ unsigned int corrected = brcmnand_count_corrected(ctrl); ++ ++ dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", ++ (unsigned long long)err_addr); ++ mtd->ecc_stats.corrected += corrected; ++ /* Always exceed the software-imposed threshold */ ++ return max(mtd->bitflip_threshold, corrected); ++ } ++ ++ return 0; ++} ++ ++static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf, int oob_required, int page) ++{ ++ struct brcmnand_host *host = chip->priv; ++ u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; ++ ++ return brcmnand_read(mtd, chip, host->last_addr, ++ mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); ++} ++ ++static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf, int oob_required, int page) ++{ ++ struct brcmnand_host *host = chip->priv; ++ u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; ++ int ret; ++ ++ brcmnand_set_ecc_enabled(host, 0); ++ ret = brcmnand_read(mtd, chip, host->last_addr, ++ mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); ++ brcmnand_set_ecc_enabled(host, 1); ++ return ret; ++} ++ ++static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, ++ mtd->writesize >> FC_SHIFT, ++ NULL, (u8 *)chip->oob_poi); ++} ++ ++static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ struct brcmnand_host *host = chip->priv; ++ ++ brcmnand_set_ecc_enabled(host, 0); ++ brcmnand_read(mtd, chip, (u64)page << chip->page_shift, ++ mtd->writesize >> FC_SHIFT, ++ NULL, (u8 *)chip->oob_poi); ++ brcmnand_set_ecc_enabled(host, 1); ++ return 0; ++} ++ ++static int brcmnand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, ++ uint32_t data_offs, uint32_t readlen, ++ uint8_t *bufpoi, int page) ++{ ++ struct brcmnand_host *host = chip->priv; ++ ++ return brcmnand_read(mtd, chip, host->last_addr + data_offs, ++ readlen >> FC_SHIFT, (u32 *)bufpoi, NULL); ++} ++ ++static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, ++ u64 addr, const u32 *buf, u8 *oob) ++{ ++ struct brcmnand_host *host = chip->priv; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; ++ int status, ret = 0; ++ ++ dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); ++ ++ if (unlikely((u32)buf & 0x03)) { ++ dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); ++ buf = (u32 *)((u32)buf & ~0x03); ++ } ++ ++ brcmnand_wp(mtd, 0); ++ ++ for (i = 0; i < ctrl->max_oob; i += 4) ++ oob_reg_write(ctrl, i, 0xffffffff); ++ ++ if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { ++ if (brcmnand_dma_trans(host, addr, (u32 *)buf, ++ mtd->writesize, CMD_PROGRAM_PAGE)) ++ ret = -EIO; ++ goto out; ++ } ++ ++ brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, ++ (host->cs << 16) | ((addr >> 32) & 0xffff)); ++ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); ++ ++ for (i = 0; i < trans; i++, addr += FC_BYTES) { ++ /* full address MUST be set before populating FC */ ++ brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, ++ lower_32_bits(addr)); ++ (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); ++ ++ if (buf) { ++ brcmnand_soc_data_bus_prepare(ctrl->soc); ++ ++ for (j = 0; j < FC_WORDS; j++, buf++) ++ brcmnand_write_fc(ctrl, j, *buf); ++ ++ brcmnand_soc_data_bus_unprepare(ctrl->soc); ++ } else if (oob) { ++ for (j = 0; j < FC_WORDS; j++) ++ brcmnand_write_fc(ctrl, j, 0xffffffff); ++ } ++ ++ if (oob) { ++ oob += write_oob_to_regs(ctrl, i, oob, ++ mtd->oobsize / trans, ++ host->hwcfg.sector_size_1k); ++ } ++ ++ /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */ ++ brcmnand_send_cmd(host, CMD_PROGRAM_PAGE); ++ status = brcmnand_waitfunc(mtd, chip); ++ ++ if (status & NAND_STATUS_FAIL) { ++ dev_info(ctrl->dev, "program failed at %llx\n", ++ (unsigned long long)addr); ++ ret = -EIO; ++ goto out; ++ } ++ } ++out: ++ brcmnand_wp(mtd, 1); ++ return ret; ++} ++ ++static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf, int oob_required) ++{ ++ struct brcmnand_host *host = chip->priv; ++ void *oob = oob_required ? chip->oob_poi : NULL; ++ ++ brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); ++ return 0; ++} ++ ++static int brcmnand_write_page_raw(struct mtd_info *mtd, ++ struct nand_chip *chip, const uint8_t *buf, ++ int oob_required) ++{ ++ struct brcmnand_host *host = chip->priv; ++ void *oob = oob_required ? chip->oob_poi : NULL; ++ ++ brcmnand_set_ecc_enabled(host, 0); ++ brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); ++ brcmnand_set_ecc_enabled(host, 1); ++ return 0; ++} ++ ++static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ return brcmnand_write(mtd, chip, (u64)page << chip->page_shift, ++ NULL, chip->oob_poi); ++} ++ ++static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ struct brcmnand_host *host = chip->priv; ++ int ret; ++ ++ brcmnand_set_ecc_enabled(host, 0); ++ ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, ++ (u8 *)chip->oob_poi); ++ brcmnand_set_ecc_enabled(host, 1); ++ ++ return ret; ++} ++ ++/*********************************************************************** ++ * Per-CS setup (1 NAND device) ++ ***********************************************************************/ ++ ++static int brcmnand_set_cfg(struct brcmnand_host *host, ++ struct brcmnand_cfg *cfg) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ struct nand_chip *chip = &host->chip; ++ u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); ++ u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, ++ BRCMNAND_CS_CFG_EXT); ++ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, ++ BRCMNAND_CS_ACC_CONTROL); ++ u8 block_size = 0, page_size = 0, device_size = 0; ++ u32 tmp; ++ ++ if (ctrl->block_sizes) { ++ int i, found; ++ ++ for (i = 0, found = 0; ctrl->block_sizes[i]; i++) ++ if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { ++ block_size = i; ++ found = 1; ++ } ++ if (!found) { ++ dev_warn(ctrl->dev, "invalid block size %u\n", ++ cfg->block_size); ++ return -EINVAL; ++ } ++ } else { ++ block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); ++ } ++ ++ if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && ++ cfg->block_size > ctrl->max_block_size)) { ++ dev_warn(ctrl->dev, "invalid block size %u\n", ++ cfg->block_size); ++ block_size = 0; ++ } ++ ++ if (ctrl->page_sizes) { ++ int i, found; ++ ++ for (i = 0, found = 0; ctrl->page_sizes[i]; i++) ++ if (ctrl->page_sizes[i] == cfg->page_size) { ++ page_size = i; ++ found = 1; ++ } ++ if (!found) { ++ dev_warn(ctrl->dev, "invalid page size %u\n", ++ cfg->page_size); ++ return -EINVAL; ++ } ++ } else { ++ page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); ++ } ++ ++ if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && ++ cfg->page_size > ctrl->max_page_size)) { ++ dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); ++ return -EINVAL; ++ } ++ ++ if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { ++ dev_warn(ctrl->dev, "invalid device size 0x%llx\n", ++ (unsigned long long)cfg->device_size); ++ return -EINVAL; ++ } ++ device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); ++ ++ tmp = (cfg->blk_adr_bytes << 8) | ++ (cfg->col_adr_bytes << 12) | ++ (cfg->ful_adr_bytes << 16) | ++ (!!(cfg->device_width == 16) << 23) | ++ (device_size << 24); ++ if (cfg_offs == cfg_ext_offs) { ++ tmp |= (page_size << 20) | (block_size << 28); ++ nand_writereg(ctrl, cfg_offs, tmp); ++ } else { ++ nand_writereg(ctrl, cfg_offs, tmp); ++ tmp = page_size | (block_size << 4); ++ nand_writereg(ctrl, cfg_ext_offs, tmp); ++ } ++ ++ tmp = nand_readreg(ctrl, acc_control_offs); ++ tmp &= ~brcmnand_ecc_level_mask(ctrl); ++ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; ++ tmp &= ~brcmnand_spare_area_mask(ctrl); ++ tmp |= cfg->spare_area_size; ++ nand_writereg(ctrl, acc_control_offs, tmp); ++ ++ brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); ++ ++ /* threshold = ceil(BCH-level * 0.75) */ ++ brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); ++ ++ return 0; ++} ++ ++static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg) ++{ ++ buf += sprintf(buf, ++ "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", ++ (unsigned long long)cfg->device_size >> 20, ++ cfg->block_size >> 10, ++ cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, ++ cfg->page_size >= 1024 ? "KiB" : "B", ++ cfg->spare_area_size, cfg->device_width); ++ ++ /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ ++ if (is_hamming_ecc(cfg)) ++ sprintf(buf, ", Hamming ECC"); ++ else if (cfg->sector_size_1k) ++ sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); ++ else ++ sprintf(buf, ", BCH-%u", cfg->ecc_level); ++} ++ ++/* ++ * Minimum number of bytes to address a page. Calculated as: ++ * roundup(log2(size / page-size) / 8) ++ * ++ * NB: the following does not "round up" for non-power-of-2 'size'; but this is ++ * OK because many other things will break if 'size' is irregular... ++ */ ++static inline int get_blk_adr_bytes(u64 size, u32 writesize) ++{ ++ return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; ++} ++ ++static int brcmnand_setup_dev(struct brcmnand_host *host) ++{ ++ struct mtd_info *mtd = &host->mtd; ++ struct nand_chip *chip = &host->chip; ++ struct brcmnand_controller *ctrl = host->ctrl; ++ struct brcmnand_cfg *cfg = &host->hwcfg; ++ char msg[128]; ++ u32 offs, tmp, oob_sector; ++ int ret; ++ ++ memset(cfg, 0, sizeof(*cfg)); ++ ++ ret = of_property_read_u32(chip->dn, "brcm,nand-oob-sector-size", ++ &oob_sector); ++ if (ret) { ++ /* Use detected size */ ++ cfg->spare_area_size = mtd->oobsize / ++ (mtd->writesize >> FC_SHIFT); ++ } else { ++ cfg->spare_area_size = oob_sector; ++ } ++ if (cfg->spare_area_size > ctrl->max_oob) ++ cfg->spare_area_size = ctrl->max_oob; ++ /* ++ * Set oobsize to be consistent with controller's spare_area_size, as ++ * the rest is inaccessible. ++ */ ++ mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); ++ ++ cfg->device_size = mtd->size; ++ cfg->block_size = mtd->erasesize; ++ cfg->page_size = mtd->writesize; ++ cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; ++ cfg->col_adr_bytes = 2; ++ cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); ++ ++ switch (chip->ecc.size) { ++ case 512: ++ if (chip->ecc.strength == 1) /* Hamming */ ++ cfg->ecc_level = 15; ++ else ++ cfg->ecc_level = chip->ecc.strength; ++ cfg->sector_size_1k = 0; ++ break; ++ case 1024: ++ if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { ++ dev_err(ctrl->dev, "1KB sectors not supported\n"); ++ return -EINVAL; ++ } ++ if (chip->ecc.strength & 0x1) { ++ dev_err(ctrl->dev, ++ "odd ECC not supported with 1KB sectors\n"); ++ return -EINVAL; ++ } ++ ++ cfg->ecc_level = chip->ecc.strength >> 1; ++ cfg->sector_size_1k = 1; ++ break; ++ default: ++ dev_err(ctrl->dev, "unsupported ECC size: %d\n", ++ chip->ecc.size); ++ return -EINVAL; ++ } ++ ++ cfg->ful_adr_bytes = cfg->blk_adr_bytes; ++ if (mtd->writesize > 512) ++ cfg->ful_adr_bytes += cfg->col_adr_bytes; ++ else ++ cfg->ful_adr_bytes += 1; ++ ++ ret = brcmnand_set_cfg(host, cfg); ++ if (ret) ++ return ret; ++ ++ brcmnand_set_ecc_enabled(host, 1); ++ ++ brcmnand_print_cfg(msg, cfg); ++ dev_info(ctrl->dev, "detected %s\n", msg); ++ ++ /* Configure ACC_CONTROL */ ++ offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); ++ tmp = nand_readreg(ctrl, offs); ++ tmp &= ~ACC_CONTROL_PARTIAL_PAGE; ++ tmp &= ~ACC_CONTROL_RD_ERASED; ++ tmp &= ~ACC_CONTROL_FAST_PGM_RDIN; ++ if (ctrl->features & BRCMNAND_HAS_PREFETCH) { ++ /* ++ * FIXME: Flash DMA + prefetch may see spurious erased-page ECC ++ * errors ++ */ ++ if (has_flash_dma(ctrl)) ++ tmp &= ~ACC_CONTROL_PREFETCH; ++ else ++ tmp |= ACC_CONTROL_PREFETCH; ++ } ++ nand_writereg(ctrl, offs, tmp); ++ ++ return 0; ++} ++ ++static int brcmnand_init_cs(struct brcmnand_host *host) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ struct device_node *dn = host->of_node; ++ struct platform_device *pdev = host->pdev; ++ struct mtd_info *mtd; ++ struct nand_chip *chip; ++ int ret = 0; ++ struct mtd_part_parser_data ppdata = { .of_node = dn }; ++ ++ ret = of_property_read_u32(dn, "reg", &host->cs); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get chip-select\n"); ++ return -ENXIO; ++ } ++ ++ mtd = &host->mtd; ++ chip = &host->chip; ++ ++ chip->dn = dn; ++ chip->priv = host; ++ mtd->priv = chip; ++ mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", ++ host->cs); ++ mtd->owner = THIS_MODULE; ++ mtd->dev.parent = &pdev->dev; ++ ++ chip->IO_ADDR_R = (void __iomem *)0xdeadbeef; ++ chip->IO_ADDR_W = (void __iomem *)0xdeadbeef; ++ ++ chip->cmd_ctrl = brcmnand_cmd_ctrl; ++ chip->cmdfunc = brcmnand_cmdfunc; ++ chip->waitfunc = brcmnand_waitfunc; ++ chip->read_byte = brcmnand_read_byte; ++ chip->read_buf = brcmnand_read_buf; ++ chip->write_buf = brcmnand_write_buf; ++ ++ chip->ecc.mode = NAND_ECC_HW; ++ chip->ecc.read_page = brcmnand_read_page; ++ chip->ecc.read_subpage = brcmnand_read_subpage; ++ chip->ecc.write_page = brcmnand_write_page; ++ chip->ecc.read_page_raw = brcmnand_read_page_raw; ++ chip->ecc.write_page_raw = brcmnand_write_page_raw; ++ chip->ecc.write_oob_raw = brcmnand_write_oob_raw; ++ chip->ecc.read_oob_raw = brcmnand_read_oob_raw; ++ chip->ecc.read_oob = brcmnand_read_oob; ++ chip->ecc.write_oob = brcmnand_write_oob; ++ ++ chip->controller = &ctrl->controller; ++ ++ if (nand_scan_ident(mtd, 1, NULL)) ++ return -ENXIO; ++ ++ chip->options |= NAND_NO_SUBPAGE_WRITE; ++ /* ++ * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA ++ * to/from, and have nand_base pass us a bounce buffer instead, as ++ * needed. ++ */ ++ chip->options |= NAND_USE_BOUNCE_BUFFER; ++ ++ if (of_get_nand_on_flash_bbt(dn)) ++ chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; ++ ++ if (brcmnand_setup_dev(host)) ++ return -ENXIO; ++ ++ chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; ++ /* only use our internal HW threshold */ ++ mtd->bitflip_threshold = 1; ++ ++ chip->ecc.layout = brcmstb_choose_ecc_layout(host); ++ if (!chip->ecc.layout) ++ return -ENXIO; ++ ++ if (nand_scan_tail(mtd)) ++ return -ENXIO; ++ ++ return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); ++} ++ ++static void brcmnand_save_restore_cs_config(struct brcmnand_host *host, ++ int restore) ++{ ++ struct brcmnand_controller *ctrl = host->ctrl; ++ u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); ++ u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, ++ BRCMNAND_CS_CFG_EXT); ++ u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, ++ BRCMNAND_CS_ACC_CONTROL); ++ u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); ++ u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); ++ ++ if (restore) { ++ nand_writereg(ctrl, cfg_offs, host->hwcfg.config); ++ if (cfg_offs != cfg_ext_offs) ++ nand_writereg(ctrl, cfg_ext_offs, ++ host->hwcfg.config_ext); ++ nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); ++ nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); ++ nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); ++ } else { ++ host->hwcfg.config = nand_readreg(ctrl, cfg_offs); ++ if (cfg_offs != cfg_ext_offs) ++ host->hwcfg.config_ext = ++ nand_readreg(ctrl, cfg_ext_offs); ++ host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); ++ host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); ++ host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); ++ } ++} ++ ++static int brcmnand_suspend(struct device *dev) ++{ ++ struct brcmnand_controller *ctrl = dev_get_drvdata(dev); ++ struct brcmnand_host *host; ++ ++ list_for_each_entry(host, &ctrl->host_list, node) ++ brcmnand_save_restore_cs_config(host, 0); ++ ++ ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); ++ ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); ++ ctrl->corr_stat_threshold = ++ brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); ++ ++ if (has_flash_dma(ctrl)) ++ ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); ++ ++ return 0; ++} ++ ++static int brcmnand_resume(struct device *dev) ++{ ++ struct brcmnand_controller *ctrl = dev_get_drvdata(dev); ++ struct brcmnand_host *host; ++ ++ if (has_flash_dma(ctrl)) { ++ flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); ++ flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); ++ } ++ ++ brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); ++ brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); ++ brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, ++ ctrl->corr_stat_threshold); ++ if (ctrl->soc) { ++ /* Clear/re-enable interrupt */ ++ ctrl->soc->ctlrdy_ack(ctrl->soc); ++ ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); ++ } ++ ++ list_for_each_entry(host, &ctrl->host_list, node) { ++ struct mtd_info *mtd = &host->mtd; ++ struct nand_chip *chip = mtd->priv; ++ ++ brcmnand_save_restore_cs_config(host, 1); ++ ++ /* Reset the chip, required by some chips after power-up */ ++ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); ++ } ++ ++ return 0; ++} ++ ++const struct dev_pm_ops brcmnand_pm_ops = { ++ .suspend = brcmnand_suspend, ++ .resume = brcmnand_resume, ++}; ++EXPORT_SYMBOL_GPL(brcmnand_pm_ops); ++ ++static const struct of_device_id brcmnand_of_match[] = { ++ { .compatible = "brcm,brcmnand-v4.0" }, ++ { .compatible = "brcm,brcmnand-v5.0" }, ++ { .compatible = "brcm,brcmnand-v6.0" }, ++ { .compatible = "brcm,brcmnand-v6.1" }, ++ { .compatible = "brcm,brcmnand-v7.0" }, ++ { .compatible = "brcm,brcmnand-v7.1" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, brcmnand_of_match); ++ ++/*********************************************************************** ++ * Platform driver setup (per controller) ++ ***********************************************************************/ ++ ++int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *dn = dev->of_node, *child; ++ struct brcmnand_controller *ctrl; ++ struct resource *res; ++ int ret; ++ ++ /* We only support device-tree instantiation */ ++ if (!dn) ++ return -ENODEV; ++ ++ if (!of_match_node(brcmnand_of_match, dn)) ++ return -ENODEV; ++ ++ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); ++ if (!ctrl) ++ return -ENOMEM; ++ ++ dev_set_drvdata(dev, ctrl); ++ ctrl->dev = dev; ++ ++ init_completion(&ctrl->done); ++ init_completion(&ctrl->dma_done); ++ spin_lock_init(&ctrl->controller.lock); ++ init_waitqueue_head(&ctrl->controller.wq); ++ INIT_LIST_HEAD(&ctrl->host_list); ++ ++ /* NAND register range */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ctrl->nand_base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(ctrl->nand_base)) ++ return PTR_ERR(ctrl->nand_base); ++ ++ /* Initialize NAND revision */ ++ ret = brcmnand_revision_init(ctrl); ++ if (ret) ++ return ret; ++ ++ /* ++ * Most chips have this cache at a fixed offset within 'nand' block. ++ * Some must specify this region separately. ++ */ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); ++ if (res) { ++ ctrl->nand_fc = devm_ioremap_resource(dev, res); ++ if (IS_ERR(ctrl->nand_fc)) ++ return PTR_ERR(ctrl->nand_fc); ++ } else { ++ ctrl->nand_fc = ctrl->nand_base + ++ ctrl->reg_offsets[BRCMNAND_FC_BASE]; ++ } ++ ++ /* FLASH_DMA */ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); ++ if (res) { ++ ctrl->flash_dma_base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(ctrl->flash_dma_base)) ++ return PTR_ERR(ctrl->flash_dma_base); ++ ++ flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */ ++ flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); ++ ++ /* Allocate descriptor(s) */ ++ ctrl->dma_desc = dmam_alloc_coherent(dev, ++ sizeof(*ctrl->dma_desc), ++ &ctrl->dma_pa, GFP_KERNEL); ++ if (!ctrl->dma_desc) ++ return -ENOMEM; ++ ++ ctrl->dma_irq = platform_get_irq(pdev, 1); ++ if ((int)ctrl->dma_irq < 0) { ++ dev_err(dev, "missing FLASH_DMA IRQ\n"); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(dev, ctrl->dma_irq, ++ brcmnand_dma_irq, 0, DRV_NAME, ++ ctrl); ++ if (ret < 0) { ++ dev_err(dev, "can't allocate IRQ %d: error %d\n", ++ ctrl->dma_irq, ret); ++ return ret; ++ } ++ ++ dev_info(dev, "enabling FLASH_DMA\n"); ++ } ++ ++ /* Disable automatic device ID config, direct addressing */ ++ brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, ++ CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0); ++ /* Disable XOR addressing */ ++ brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); ++ ++ if (ctrl->features & BRCMNAND_HAS_WP) { ++ /* Permanently disable write protection */ ++ if (wp_on == 2) ++ brcmnand_set_wp(ctrl, false); ++ } else { ++ wp_on = 0; ++ } ++ ++ /* IRQ */ ++ ctrl->irq = platform_get_irq(pdev, 0); ++ if ((int)ctrl->irq < 0) { ++ dev_err(dev, "no IRQ defined\n"); ++ return -ENODEV; ++ } ++ ++ /* ++ * Some SoCs integrate this controller (e.g., its interrupt bits) in ++ * interesting ways ++ */ ++ if (soc) { ++ ctrl->soc = soc; ++ ++ ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, ++ DRV_NAME, ctrl); ++ ++ /* Enable interrupt */ ++ ctrl->soc->ctlrdy_ack(ctrl->soc); ++ ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); ++ } else { ++ /* Use standard interrupt infrastructure */ ++ ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, ++ DRV_NAME, ctrl); ++ } ++ if (ret < 0) { ++ dev_err(dev, "can't allocate IRQ %d: error %d\n", ++ ctrl->irq, ret); ++ return ret; ++ } ++ ++ for_each_available_child_of_node(dn, child) { ++ if (of_device_is_compatible(child, "brcm,nandcs")) { ++ struct brcmnand_host *host; ++ ++ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); ++ if (!host) ++ return -ENOMEM; ++ host->pdev = pdev; ++ host->ctrl = ctrl; ++ host->of_node = child; ++ ++ ret = brcmnand_init_cs(host); ++ if (ret) ++ continue; /* Try all chip-selects */ ++ ++ list_add_tail(&host->node, &ctrl->host_list); ++ } ++ } ++ ++ /* No chip-selects could initialize properly */ ++ if (list_empty(&ctrl->host_list)) ++ return -ENODEV; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(brcmnand_probe); ++ ++int brcmnand_remove(struct platform_device *pdev) ++{ ++ struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); ++ struct brcmnand_host *host; ++ ++ list_for_each_entry(host, &ctrl->host_list, node) ++ nand_release(&host->mtd); ++ ++ dev_set_drvdata(&pdev->dev, NULL); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(brcmnand_remove); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Kevin Cernekee"); ++MODULE_AUTHOR("Brian Norris"); ++MODULE_DESCRIPTION("NAND driver for Broadcom chips"); ++MODULE_ALIAS("platform:brcmnand"); +--- /dev/null ++++ b/drivers/mtd/nand/brcmnand/brcmnand.h +@@ -0,0 +1,71 @@ ++/* ++ * Copyright © 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __BRCMNAND_H__ ++#define __BRCMNAND_H__ ++ ++#include ++#include ++ ++struct platform_device; ++struct dev_pm_ops; ++ ++struct brcmnand_soc { ++ bool (*ctlrdy_ack)(struct brcmnand_soc *soc); ++ void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en); ++ void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare); ++}; ++ ++static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc) ++{ ++ if (soc && soc->prepare_data_bus) ++ soc->prepare_data_bus(soc, true); ++} ++ ++static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc) ++{ ++ if (soc && soc->prepare_data_bus) ++ soc->prepare_data_bus(soc, false); ++} ++ ++static inline u32 brcmnand_readl(void __iomem *addr) ++{ ++ /* ++ * MIPS endianness is configured by boot strap, which also reverses all ++ * bus endianness (i.e., big-endian CPU + big endian bus ==> native ++ * endian I/O). ++ * ++ * Other architectures (e.g., ARM) either do not support big endian, or ++ * else leave I/O in little endian mode. ++ */ ++ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN)) ++ return __raw_readl(addr); ++ else ++ return readl_relaxed(addr); ++} ++ ++static inline void brcmnand_writel(u32 val, void __iomem *addr) ++{ ++ /* See brcmnand_readl() comments */ ++ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN)) ++ __raw_writel(val, addr); ++ else ++ writel_relaxed(val, addr); ++} ++ ++int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc); ++int brcmnand_remove(struct platform_device *pdev); ++ ++extern const struct dev_pm_ops brcmnand_pm_ops; ++ ++#endif /* __BRCMNAND_H__ */ +--- /dev/null ++++ b/drivers/mtd/nand/brcmnand/brcmstb_nand.c +@@ -0,0 +1,44 @@ ++/* ++ * Copyright © 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include "brcmnand.h" ++ ++static const struct of_device_id brcmstb_nand_of_match[] = { ++ { .compatible = "brcm,brcmnand" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, brcmstb_nand_of_match); ++ ++static int brcmstb_nand_probe(struct platform_device *pdev) ++{ ++ return brcmnand_probe(pdev, NULL); ++} ++ ++static struct platform_driver brcmstb_nand_driver = { ++ .probe = brcmstb_nand_probe, ++ .remove = brcmnand_remove, ++ .driver = { ++ .name = "brcmstb_nand", ++ .pm = &brcmnand_pm_ops, ++ .of_match_table = brcmstb_nand_of_match, ++ } ++}; ++module_platform_driver(brcmstb_nand_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Brian Norris"); ++MODULE_DESCRIPTION("NAND driver for Broadcom STB chips"); +--- /dev/null ++++ b/drivers/mtd/nand/brcmnand/iproc_nand.c +@@ -0,0 +1,150 @@ ++/* ++ * Copyright © 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "brcmnand.h" ++ ++struct iproc_nand_soc { ++ struct brcmnand_soc soc; ++ ++ void __iomem *idm_base; ++ void __iomem *ext_base; ++ spinlock_t idm_lock; ++}; ++ ++#define IPROC_NAND_CTLR_READY_OFFSET 0x10 ++#define IPROC_NAND_CTLR_READY BIT(0) ++ ++#define IPROC_NAND_IO_CTRL_OFFSET 0x00 ++#define IPROC_NAND_APB_LE_MODE BIT(24) ++#define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6) ++ ++static bool iproc_nand_intc_ack(struct brcmnand_soc *soc) ++{ ++ struct iproc_nand_soc *priv = ++ container_of(soc, struct iproc_nand_soc, soc); ++ void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET; ++ u32 val = brcmnand_readl(mmio); ++ ++ if (val & IPROC_NAND_CTLR_READY) { ++ brcmnand_writel(IPROC_NAND_CTLR_READY, mmio); ++ return true; ++ } ++ ++ return false; ++} ++ ++static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en) ++{ ++ struct iproc_nand_soc *priv = ++ container_of(soc, struct iproc_nand_soc, soc); ++ void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET; ++ u32 val; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->idm_lock, flags); ++ ++ val = brcmnand_readl(mmio); ++ ++ if (en) ++ val |= IPROC_NAND_INT_CTRL_READ_ENABLE; ++ else ++ val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE; ++ ++ brcmnand_writel(val, mmio); ++ ++ spin_unlock_irqrestore(&priv->idm_lock, flags); ++} ++ ++static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare) ++{ ++ struct iproc_nand_soc *priv = ++ container_of(soc, struct iproc_nand_soc, soc); ++ void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET; ++ u32 val; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->idm_lock, flags); ++ ++ val = brcmnand_readl(mmio); ++ ++ if (prepare) ++ val |= IPROC_NAND_APB_LE_MODE; ++ else ++ val &= ~IPROC_NAND_APB_LE_MODE; ++ ++ brcmnand_writel(val, mmio); ++ ++ spin_unlock_irqrestore(&priv->idm_lock, flags); ++} ++ ++static int iproc_nand_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct iproc_nand_soc *priv; ++ struct brcmnand_soc *soc; ++ struct resource *res; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ soc = &priv->soc; ++ ++ spin_lock_init(&priv->idm_lock); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iproc-idm"); ++ priv->idm_base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->idm_base)) ++ return PTR_ERR(priv->idm_base); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iproc-ext"); ++ priv->ext_base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->ext_base)) ++ return PTR_ERR(priv->ext_base); ++ ++ soc->ctlrdy_ack = iproc_nand_intc_ack; ++ soc->ctlrdy_set_enabled = iproc_nand_intc_set; ++ soc->prepare_data_bus = iproc_nand_apb_access; ++ ++ return brcmnand_probe(pdev, soc); ++} ++ ++static const struct of_device_id iproc_nand_of_match[] = { ++ { .compatible = "brcm,nand-iproc" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, iproc_nand_of_match); ++ ++static struct platform_driver iproc_nand_driver = { ++ .probe = iproc_nand_probe, ++ .remove = brcmnand_remove, ++ .driver = { ++ .name = "iproc_nand", ++ .pm = &brcmnand_pm_ops, ++ .of_match_table = iproc_nand_of_match, ++ } ++}; ++module_platform_driver(iproc_nand_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Brian Norris"); ++MODULE_AUTHOR("Ray Jui"); ++MODULE_DESCRIPTION("NAND driver for Broadcom IPROC-based SoCs"); diff --git a/target/linux/bcm53xx/patches-4.1/101-use-part-parser.patch b/target/linux/bcm53xx/patches-4.1/101-use-part-parser.patch new file mode 100644 index 0000000..8d48673 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/101-use-part-parser.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi ++++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi +@@ -19,6 +19,8 @@ + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; ++ ++ linux,part-probe = "ofpart", "bcm47xxpart"; + }; + }; + }; diff --git a/target/linux/bcm53xx/patches-4.1/110-firmware-backport-NVRAM-driver.patch b/target/linux/bcm53xx/patches-4.1/110-firmware-backport-NVRAM-driver.patch new file mode 100644 index 0000000..7486649 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/110-firmware-backport-NVRAM-driver.patch @@ -0,0 +1,49 @@ +From 0509f6dcc46d10ea4bb8c70494dc7ae11bcb3f01 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 10 Dec 2014 21:14:10 +0100 +Subject: [PATCH] firmware: backport NVRAM driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/Kconfig | 2 ++ + drivers/firmware/Kconfig | 1 + + drivers/firmware/Makefile | 1 + + drivers/net/ethernet/broadcom/b44.c | 2 +- + drivers/net/ethernet/broadcom/bgmac.c | 2 +- + drivers/ssb/driver_chipcommon_pmu.c | 2 +- + 6 files changed, 7 insertions(+), 3 deletions(-) + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -2106,6 +2106,8 @@ source "drivers/Kconfig" + + source "drivers/firmware/Kconfig" + ++source "drivers/firmware/Kconfig" ++ + source "fs/Kconfig" + + source "arch/arm/Kconfig.debug" +--- a/drivers/firmware/Kconfig ++++ b/drivers/firmware/Kconfig +@@ -136,6 +136,7 @@ config QCOM_SCM + bool + depends on ARM || ARM64 + ++source "drivers/firmware/broadcom/Kconfig" + source "drivers/firmware/google/Kconfig" + source "drivers/firmware/efi/Kconfig" + +--- a/drivers/firmware/Makefile ++++ b/drivers/firmware/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap. + obj-$(CONFIG_QCOM_SCM) += qcom_scm.o + CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) + ++obj-y += broadcom/ + obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ + obj-$(CONFIG_EFI) += efi/ + obj-$(CONFIG_UEFI_CPER) += efi/ diff --git a/target/linux/bcm53xx/patches-4.1/112-bcm53xx-sprom-add-sprom-driver.patch b/target/linux/bcm53xx/patches-4.1/112-bcm53xx-sprom-add-sprom-driver.patch new file mode 100644 index 0000000..b914fd9 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/112-bcm53xx-sprom-add-sprom-driver.patch @@ -0,0 +1,69 @@ +From 4e0ab3269a6d260a41a3673157753147f5f71341 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 4 May 2014 13:19:20 +0200 +Subject: [PATCH 03/17] bcm47xx-sprom: add Broadcom sprom parser driver + +This driver needs an nvram driver and fetches the sprom values from the +nvram and provides it to any other driver. The calibration data for the +wifi chip the mac address and some more board description data is +stores in the sprom. + +This is based on a copy of arch/mips/bcm47xx/sprom.c and my plan is to +make the bcm47xx MIPS SoCs also use this driver some time later. + +Signed-off-by: Hauke Mehrtens +--- + .../devicetree/bindings/misc/bcm47xx-sprom.txt | 16 + + drivers/misc/Kconfig | 11 + + drivers/misc/Makefile | 1 + + drivers/misc/bcm47xx-sprom.c | 690 +++++++++++++++++++++ + 4 files changed, 718 insertions(+) + create mode 100644 Documentation/devicetree/bindings/misc/bcm47xx-sprom.txt + create mode 100644 drivers/misc/bcm47xx-sprom.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/misc/bcm47xx-sprom.txt +@@ -0,0 +1,16 @@ ++Broadcom bcm47xx/bcm53xx sprom converter ++ ++This driver provbides an sprom based on a given nvram. ++ ++Required properties: ++ ++- compatible : brcm,bcm47xx-sprom ++ ++- nvram : reference to a nvram driver, e.g. bcm47xx-nvram ++ ++Example: ++ ++sprom0: sprom@0 { ++ compatible = "brcm,bcm47xx-sprom"; ++ nvram = <&nvram0>; ++}; +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -515,6 +515,17 @@ config VEXPRESS_SYSCFG + bus. System Configuration interface is one of the possible means + of generating transactions on this bus. + ++config BCM47XX_SPROM ++ tristate "BCM47XX sprom driver" ++ help ++ This driver parses the sprom from a given nvram which is found on ++ Broadcom bcm47xx and bcm53xx SoCs. ++ ++ The sprom contains board configuration data like the ++ calibration data fro the wifi chips, the mac addresses used ++ by the board and many other board configuration data. This ++ driver will provide the sprom to bcma. ++ + source "drivers/misc/c2port/Kconfig" + source "drivers/misc/eeprom/Kconfig" + source "drivers/misc/cb710/Kconfig" +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -56,3 +56,4 @@ obj-$(CONFIG_GENWQE) += genwqe/ + obj-$(CONFIG_ECHO) += echo/ + obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o + obj-$(CONFIG_CXL_BASE) += cxl/ ++obj-$(CONFIG_BCM47XX_SPROM) += bcm47xx-sprom.o diff --git a/target/linux/bcm53xx/patches-4.1/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch b/target/linux/bcm53xx/patches-4.1/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch new file mode 100644 index 0000000..5e3bd77 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch @@ -0,0 +1,635 @@ +From a0ad1511d5805b95ac4c454d7904c670a1696055 Mon Sep 17 00:00:00 2001 +From: Kapil Hali +Date: Wed, 14 Oct 2015 13:47:00 -0400 +Subject: [PATCH] ARM: BCM: Add SMP support for Broadcom NSP + +Add SMP support for Broadcom's Northstar Plus SoC, +cpu enable method and pen_release procedures. This +changes also consolidates iProc family's - BCM NSP +and BCM Kona, SMP handling in a common file. + +Northstar Plus SoC is based on ARM Cortex-A9 +revision r3p0 which requires configuration for ARM +Errata 764369 for SMP. This change adds the needed +configuration option. + +Signed-off-by: Kapil Hali +--- + arch/arm/mach-bcm/Makefile | 2 +- + arch/arm/mach-bcm/bcm_nsp.h | 19 +++ + arch/arm/mach-bcm/headsmp.S | 37 +++++ + arch/arm/mach-bcm/kona_smp.c | 202 --------------------------- + arch/arm/mach-bcm/platsmp.c | 326 +++++++++++++++++++++++++++++++++++++++++++ + 5 files changed, 383 insertions(+), 203 deletions(-) + create mode 100644 arch/arm/mach-bcm/bcm_nsp.h + create mode 100644 arch/arm/mach-bcm/headsmp.S + delete mode 100644 arch/arm/mach-bcm/kona_smp.c + create mode 100644 arch/arm/mach-bcm/platsmp.c + +--- a/arch/arm/mach-bcm/Makefile ++++ b/arch/arm/mach-bcm/Makefile +@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bc + obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o + + # BCM281XX and BCM21664 SMP support +-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o ++obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o + + # BCM281XX and BCM21664 L2 cache control + obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o +--- /dev/null ++++ b/arch/arm/mach-bcm/bcm_nsp.h +@@ -0,0 +1,19 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __BCM_NSP_H ++#define __BCM_NSP_H ++ ++extern void nsp_secondary_startup(void); ++ ++#endif /* __BCM_NSP_H */ +--- /dev/null ++++ b/arch/arm/mach-bcm/headsmp.S +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++ ++/* ++ * iProc specific entry point for secondary CPUs. This provides ++ * a "holding pen" into which all secondary cores are held until ++ * we are ready for them to initialise. ++ */ ++ENTRY(nsp_secondary_startup) ++ mrc p15, 0, r0, c0, c0, 5 ++ and r0, r0, #15 ++ adr r4, 1f ++ ldmia r4, {r5, r6} ++ sub r4, r4, r5 ++ add r6, r6, r4 ++pen: ldr r7, [r6] ++ cmp r7, r0 ++ bne pen ++ ++ b secondary_startup ++ ++1: .long . ++ .long pen_release ++ ++ENDPROC(nsp_secondary_startup) +--- a/arch/arm/mach-bcm/kona_smp.c ++++ /dev/null +@@ -1,202 +0,0 @@ +-/* +- * Copyright (C) 2014 Broadcom Corporation +- * Copyright 2014 Linaro Limited +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-/* Size of mapped Cortex A9 SCU address space */ +-#define CORTEX_A9_SCU_SIZE 0x58 +- +-#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ +-#define BOOT_ADDR_CPUID_MASK 0x3 +- +-/* Name of device node property defining secondary boot register location */ +-#define OF_SECONDARY_BOOT "secondary-boot-reg" +- +-/* I/O address of register used to coordinate secondary core startup */ +-static u32 secondary_boot; +- +-/* +- * Enable the Cortex A9 Snoop Control Unit +- * +- * By the time this is called we already know there are multiple +- * cores present. We assume we're running on a Cortex A9 processor, +- * so any trouble getting the base address register or getting the +- * SCU base is a problem. +- * +- * Return 0 if successful or an error code otherwise. +- */ +-static int __init scu_a9_enable(void) +-{ +- unsigned long config_base; +- void __iomem *scu_base; +- +- if (!scu_a9_has_base()) { +- pr_err("no configuration base address register!\n"); +- return -ENXIO; +- } +- +- /* Config base address register value is zero for uniprocessor */ +- config_base = scu_a9_get_base(); +- if (!config_base) { +- pr_err("hardware reports only one core\n"); +- return -ENOENT; +- } +- +- scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); +- if (!scu_base) { +- pr_err("failed to remap config base (%lu/%u) for SCU\n", +- config_base, CORTEX_A9_SCU_SIZE); +- return -ENOMEM; +- } +- +- scu_enable(scu_base); +- +- iounmap(scu_base); /* That's the last we'll need of this */ +- +- return 0; +-} +- +-static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) +-{ +- static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; +- struct device_node *node; +- int ret; +- +- BUG_ON(secondary_boot); /* We're called only once */ +- +- /* +- * This function is only called via smp_ops->smp_prepare_cpu(). +- * That only happens if a "/cpus" device tree node exists +- * and has an "enable-method" property that selects the SMP +- * operations defined herein. +- */ +- node = of_find_node_by_path("/cpus"); +- BUG_ON(!node); +- +- /* +- * Our secondary enable method requires a "secondary-boot-reg" +- * property to specify a register address used to request the +- * ROM code boot a secondary code. If we have any trouble +- * getting this we fall back to uniprocessor mode. +- */ +- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) { +- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n", +- node->name); +- ret = -ENOENT; /* Arrange to disable SMP */ +- goto out; +- } +- +- /* +- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is +- * returned, the SoC reported a uniprocessor configuration. +- * We bail on any other error. +- */ +- ret = scu_a9_enable(); +-out: +- of_node_put(node); +- if (ret) { +- /* Update the CPU present map to reflect uniprocessor mode */ +- BUG_ON(ret != -ENOENT); +- pr_warn("disabling SMP\n"); +- init_cpu_present(&only_cpu_0); +- } +-} +- +-/* +- * The ROM code has the secondary cores looping, waiting for an event. +- * When an event occurs each core examines the bottom two bits of the +- * secondary boot register. When a core finds those bits contain its +- * own core id, it performs initialization, including computing its boot +- * address by clearing the boot register value's bottom two bits. The +- * core signals that it is beginning its execution by writing its boot +- * address back to the secondary boot register, and finally jumps to +- * that address. +- * +- * So to start a core executing we need to: +- * - Encode the (hardware) CPU id with the bottom bits of the secondary +- * start address. +- * - Write that value into the secondary boot register. +- * - Generate an event to wake up the secondary CPU(s). +- * - Wait for the secondary boot register to be re-written, which +- * indicates the secondary core has started. +- */ +-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle) +-{ +- void __iomem *boot_reg; +- phys_addr_t boot_func; +- u64 start_clock; +- u32 cpu_id; +- u32 boot_val; +- bool timeout = false; +- +- cpu_id = cpu_logical_map(cpu); +- if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { +- pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); +- return -EINVAL; +- } +- +- if (!secondary_boot) { +- pr_err("required secondary boot register not specified\n"); +- return -EINVAL; +- } +- +- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32)); +- if (!boot_reg) { +- pr_err("unable to map boot register for cpu %u\n", cpu_id); +- return -ENOSYS; +- } +- +- /* +- * Secondary cores will start in secondary_startup(), +- * defined in "arch/arm/kernel/head.S" +- */ +- boot_func = virt_to_phys(secondary_startup); +- BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); +- BUG_ON(boot_func > (phys_addr_t)U32_MAX); +- +- /* The core to start is encoded in the low bits */ +- boot_val = (u32)boot_func | cpu_id; +- writel_relaxed(boot_val, boot_reg); +- +- sev(); +- +- /* The low bits will be cleared once the core has started */ +- start_clock = local_clock(); +- while (!timeout && readl_relaxed(boot_reg) == boot_val) +- timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; +- +- iounmap(boot_reg); +- +- if (!timeout) +- return 0; +- +- pr_err("timeout waiting for cpu %u to start\n", cpu_id); +- +- return -ENOSYS; +-} +- +-static struct smp_operations bcm_smp_ops __initdata = { +- .smp_prepare_cpus = bcm_smp_prepare_cpus, +- .smp_boot_secondary = bcm_boot_secondary, +-}; +-CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", +- &bcm_smp_ops); +--- /dev/null ++++ b/arch/arm/mach-bcm/platsmp.c +@@ -0,0 +1,326 @@ ++/* ++ * Copyright (C) 2014-2015 Broadcom Corporation ++ * Copyright 2014 Linaro Limited ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "bcm_nsp.h" ++ ++/* Size of mapped Cortex A9 SCU address space */ ++#define CORTEX_A9_SCU_SIZE 0x58 ++ ++#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ ++#define BOOT_ADDR_CPUID_MASK 0x3 ++ ++/* Name of device node property defining secondary boot register location */ ++#define OF_SECONDARY_BOOT "secondary-boot-reg" ++ ++/* I/O address of register used to coordinate secondary core startup */ ++static u32 secondary_boot; ++ ++static DEFINE_SPINLOCK(boot_lock); ++ ++/* ++ * Write pen_release in a way that is guaranteed to be visible to all ++ * observers, irrespective of whether they're taking part in coherency ++ * or not. This is necessary for the hotplug code to work reliably. ++ */ ++static void write_pen_release(int val) ++{ ++ pen_release = val; ++ /* ++ * Ensure write to pen_release is visible to the other cores, ++ * here - primary core ++ */ ++ smp_wmb(); ++ sync_cache_w(&pen_release); ++} ++ ++/* ++ * Enable the Cortex A9 Snoop Control Unit ++ * ++ * By the time this is called we already know there are multiple ++ * cores present. We assume we're running on a Cortex A9 processor, ++ * so any trouble getting the base address register or getting the ++ * SCU base is a problem. ++ * ++ * Return 0 if successful or an error code otherwise. ++ */ ++static int __init scu_a9_enable(void) ++{ ++ unsigned long config_base; ++ void __iomem *scu_base; ++ ++ if (!scu_a9_has_base()) { ++ pr_err("no configuration base address register!\n"); ++ return -ENXIO; ++ } ++ ++ /* Config base address register value is zero for uniprocessor */ ++ config_base = scu_a9_get_base(); ++ if (!config_base) { ++ pr_err("hardware reports only one core\n"); ++ return -ENOENT; ++ } ++ ++ scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); ++ if (!scu_base) { ++ pr_err("failed to remap config base (%lu/%u) for SCU\n", ++ config_base, CORTEX_A9_SCU_SIZE); ++ return -ENOMEM; ++ } ++ ++ scu_enable(scu_base); ++ ++ iounmap(scu_base); /* That's the last we'll need of this */ ++ ++ return 0; ++} ++ ++static int nsp_write_lut(void (*secondary_startup) (void)) ++{ ++ void __iomem *sku_rom_lut; ++ phys_addr_t secondary_startup_phy; ++ ++ if (!secondary_boot) { ++ pr_warn("required secondary boot register not specified\n"); ++ return -EINVAL; ++ } ++ ++ sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot, ++ sizeof(secondary_boot)); ++ if (!sku_rom_lut) { ++ pr_warn("unable to ioremap SKU-ROM LUT register\n"); ++ return -ENOMEM; ++ } ++ ++ secondary_startup_phy = virt_to_phys(secondary_startup); ++ BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX); ++ ++ writel_relaxed(secondary_startup_phy, sku_rom_lut); ++ /* ++ * Ensure the write is visible to the secondary core. ++ */ ++ smp_wmb(); ++ ++ iounmap(sku_rom_lut); ++ ++ return 0; ++} ++ ++static void nsp_secondary_init(unsigned int cpu) ++{ ++ /* ++ * Let the primary cpu know we are out of holding pen. ++ */ ++ write_pen_release(-1); ++ ++ /* ++ * Synchronise with the boot thread. ++ */ ++ spin_lock(&boot_lock); ++ spin_unlock(&boot_lock); ++} ++ ++static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; ++ struct device_node *node; ++ int ret; ++ ++ BUG_ON(secondary_boot); /* We're called only once */ ++ ++ /* ++ * This function is only called via smp_ops->smp_prepare_cpu(). ++ * That only happens if a "/cpus" device tree node exists ++ * and has an "enable-method" property that selects the SMP ++ * operations defined herein. ++ */ ++ node = of_find_node_by_path("/cpus"); ++ BUG_ON(!node); ++ ++ /* ++ * Our secondary enable method requires a "secondary-boot-reg" ++ * property to specify a register address used to request the ++ * ROM code boot a secondary core. If we have any trouble ++ * getting this we fall back to uniprocessor mode. ++ */ ++ if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) { ++ pr_warn("%s: missing/invalid " OF_SECONDARY_BOOT " property\n", ++ node->name); ++ ret = -ENOENT; /* Arrange to disable SMP */ ++ goto out; ++ } ++ ++ /* ++ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is ++ * returned, the SoC reported a uniprocessor configuration. ++ * We bail on any other error. ++ */ ++ ret = scu_a9_enable(); ++out: ++ of_node_put(node); ++ if (ret) { ++ /* Update the CPU present map to reflect uniprocessor mode */ ++ pr_warn("disabling SMP\n"); ++ init_cpu_present(&only_cpu_0); ++ } ++} ++ ++/* ++ * The ROM code has the secondary cores looping, waiting for an event. ++ * When an event occurs each core examines the bottom two bits of the ++ * secondary boot register. When a core finds those bits contain its ++ * own core id, it performs initialization, including computing its boot ++ * address by clearing the boot register value's bottom two bits. The ++ * core signals that it is beginning its execution by writing its boot ++ * address back to the secondary boot register, and finally jumps to ++ * that address. ++ * ++ * So to start a core executing we need to: ++ * - Encode the (hardware) CPU id with the bottom bits of the secondary ++ * start address. ++ * - Write that value into the secondary boot register. ++ * - Generate an event to wake up the secondary CPU(s). ++ * - Wait for the secondary boot register to be re-written, which ++ * indicates the secondary core has started. ++ */ ++static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ void __iomem *boot_reg; ++ phys_addr_t boot_func; ++ u64 start_clock; ++ u32 cpu_id; ++ u32 boot_val; ++ bool timeout = false; ++ ++ cpu_id = cpu_logical_map(cpu); ++ if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { ++ pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); ++ return -EINVAL; ++ } ++ ++ if (!secondary_boot) { ++ pr_err("required secondary boot register not specified\n"); ++ return -EINVAL; ++ } ++ ++ boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32)); ++ if (!boot_reg) { ++ pr_err("unable to map boot register for cpu %u\n", cpu_id); ++ return -ENOMEM; ++ } ++ ++ /* ++ * Secondary cores will start in secondary_startup(), ++ * defined in "arch/arm/kernel/head.S" ++ */ ++ boot_func = virt_to_phys(secondary_startup); ++ BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); ++ BUG_ON(boot_func > (phys_addr_t)U32_MAX); ++ ++ /* The core to start is encoded in the low bits */ ++ boot_val = (u32)boot_func | cpu_id; ++ writel_relaxed(boot_val, boot_reg); ++ ++ sev(); ++ ++ /* The low bits will be cleared once the core has started */ ++ start_clock = local_clock(); ++ while (!timeout && readl_relaxed(boot_reg) == boot_val) ++ timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; ++ ++ iounmap(boot_reg); ++ ++ if (!timeout) ++ return 0; ++ ++ pr_err("timeout waiting for cpu %u to start\n", cpu_id); ++ ++ return -ENXIO; ++} ++ ++static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ unsigned long timeout; ++ int ret; ++ ++ /* ++ * After wake up, secondary core branches to the startup ++ * address programmed at SKU ROM LUT location. ++ */ ++ ret = nsp_write_lut(nsp_secondary_startup); ++ if (ret) { ++ pr_err("unable to write startup addr to SKU ROM LUT\n"); ++ goto out; ++ } ++ ++ /* ++ * The secondary processor is waiting to be released from ++ * the holding pen - release it, then wait for it to flag ++ * that it has been released by resetting pen_release. ++ */ ++ spin_lock(&boot_lock); ++ ++ write_pen_release(cpu_logical_map(cpu)); ++ /* ++ * Send an Event to wake up the secondary core which is in ++ * WFE state. Updated pen_release should also be visible to ++ * the secondary core. ++ */ ++ dsb_sev(); ++ ++ timeout = jiffies + (1 * HZ); ++ while (time_before(jiffies, timeout)) { ++ /* Make sure loads on other CPU is visible */ ++ smp_rmb(); ++ if (pen_release == -1) ++ break; ++ ++ udelay(10); ++ } ++ ++ spin_unlock(&boot_lock); ++ ++ ret = pen_release != -1 ? -ENXIO : 0; ++ ++out: ++ return ret; ++} ++ ++static struct smp_operations bcm_smp_ops __initdata = { ++ .smp_prepare_cpus = bcm_smp_prepare_cpus, ++ .smp_boot_secondary = kona_boot_secondary, ++}; ++CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", ++ &bcm_smp_ops); ++ ++struct smp_operations nsp_smp_ops __initdata = { ++ .smp_prepare_cpus = bcm_smp_prepare_cpus, ++ .smp_secondary_init = nsp_secondary_init, ++ .smp_boot_secondary = nsp_boot_secondary, ++}; ++CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); diff --git a/target/linux/bcm53xx/patches-4.1/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch b/target/linux/bcm53xx/patches-4.1/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch new file mode 100644 index 0000000..4cd0473 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch @@ -0,0 +1,50 @@ +From ddbf0ad85be06948dd214c7beb7b315ef2749e65 Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 14:14:10 -0400 +Subject: [PATCH] ARM: BCM: Add SMP support for Broadcom 4708 + +ARM: BCM: Add SMP support for Broadcom 4708 + +Add SMP support for Broadcom's 4708 SoCs. + +Signed-off-by: Jon Mason +--- + arch/arm/boot/dts/bcm4708.dtsi | 2 ++ + arch/arm/mach-bcm/Kconfig | 2 ++ + arch/arm/mach-bcm/Makefile | 3 +++ + 3 files changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/bcm4708.dtsi ++++ b/arch/arm/boot/dts/bcm4708.dtsi +@@ -15,6 +15,8 @@ + cpus { + #address-cells = <1>; + #size-cells = <0>; ++ enable-method = "brcm,bcm-nsp-smp"; ++ secondary-boot-reg = <0xffff0400>; + + cpu@0 { + device_type = "cpu"; +--- a/arch/arm/mach-bcm/Kconfig ++++ b/arch/arm/mach-bcm/Kconfig +@@ -38,6 +38,8 @@ config ARCH_BCM_CYGNUS + config ARCH_BCM_5301X + bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 + select ARCH_BCM_IPROC ++ select ARM_ERRATA_764369 if SMP ++ select HAVE_SMP + help + Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. + +--- a/arch/arm/mach-bcm/Makefile ++++ b/arch/arm/mach-bcm/Makefile +@@ -36,6 +36,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2 + + # BCM5301X + obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o ++ifeq ($(CONFIG_ARCH_BCM_5301X),y) ++obj-$(CONFIG_SMP) += headsmp.o platsmp.o ++endif + + # BCM63XXx + obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o diff --git a/target/linux/bcm53xx/patches-4.1/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch b/target/linux/bcm53xx/patches-4.1/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch new file mode 100644 index 0000000..c117774 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch @@ -0,0 +1,57 @@ +From b58682598541262f967ecd6db04bacac38026d3c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 30 Oct 2015 15:29:52 +0100 +Subject: [PATCH] ARM: BCM5301X: Add missing Netgear R8000 LEDs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 30 +++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +index 446c586..b52927c 100644 +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -50,6 +50,36 @@ + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; ++ ++ wireless { ++ label = "bcm53xx:white:wireless"; ++ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wps { ++ label = "bcm53xx:white:wps"; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 5ghz-2 { ++ label = "bcm53xx:white:5ghz-2"; ++ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb3 { ++ label = "bcm53xx:white:usb3"; ++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb2 { ++ label = "bcm53xx:white:usb2"; ++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; + }; + + gpio-keys { +-- +1.8.4.5 + diff --git a/target/linux/bcm53xx/patches-4.1/180-USB-bcma-remove-chip-id-check.patch b/target/linux/bcm53xx/patches-4.1/180-USB-bcma-remove-chip-id-check.patch new file mode 100644 index 0000000..e5e3010 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/180-USB-bcma-remove-chip-id-check.patch @@ -0,0 +1,34 @@ +From baf3d128e5bdf9d322539609133a15b493b0c2ef Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Thu, 11 Jun 2015 22:57:35 +0200 +Subject: [PATCH] USB: bcma: remove chip id check + +I have never seen any bcma device with an USB host core which was not a +SoC, the bcma devices have an USB device core with a different core id. +Some SoC have IDs with 47XX and 53XX in decimal form which would be +rejected by this check. Instead of fixing this check just remove it. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 5 ----- + 1 file changed, 5 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -214,16 +214,11 @@ err_alloc: + static int bcma_hcd_probe(struct bcma_device *dev) + { + int err; +- u16 chipid_top; + u32 ohci_addr; + struct bcma_hcd_device *usb_dev; + struct bcma_chipinfo *chipinfo; + + chipinfo = &dev->bus->chipinfo; +- /* USBcores are only connected on embedded devices. */ +- chipid_top = (chipinfo->id & 0xFF00); +- if (chipid_top != 0x4700 && chipid_top != 0x5300) +- return -ENODEV; + + /* TODO: Probably need checks here; is the core connected? */ + diff --git a/target/linux/bcm53xx/patches-4.1/181-USB-bcma-replace-numbers-with-constants.patch b/target/linux/bcm53xx/patches-4.1/181-USB-bcma-replace-numbers-with-constants.patch new file mode 100644 index 0000000..5ae4e0d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/181-USB-bcma-replace-numbers-with-constants.patch @@ -0,0 +1,24 @@ +From f5bc834917a8b1b9487749bdfe8eda52a01967b4 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Thu, 11 Jun 2015 22:57:36 +0200 +Subject: [PATCH] USB: bcma: replace numbers with constants + +The constants for these numbers were added long time ago, use them. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -233,7 +233,8 @@ static int bcma_hcd_probe(struct bcma_de + + /* In AI chips EHCI is addrspace 0, OHCI is 1 */ + ohci_addr = dev->addr_s[0]; +- if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749) ++ if ((chipinfo->id == BCMA_CHIP_ID_BCM5357 || ++ chipinfo->id == BCMA_CHIP_ID_BCM4749) + && chipinfo->rev == 0) + ohci_addr = 0x18009000; + diff --git a/target/linux/bcm53xx/patches-4.1/182-USB-bcma-use-devm_kzalloc.patch b/target/linux/bcm53xx/patches-4.1/182-USB-bcma-use-devm_kzalloc.patch new file mode 100644 index 0000000..700d354 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/182-USB-bcma-use-devm_kzalloc.patch @@ -0,0 +1,47 @@ +From 93724affb195149df6f7630901d878f6e273fa02 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Thu, 11 Jun 2015 22:57:37 +0200 +Subject: [PATCH] USB: bcma: use devm_kzalloc + +Instead of manually handling the frees use devm. There was also a free +missing in the unregister call which is not needed with devm. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -225,7 +225,8 @@ static int bcma_hcd_probe(struct bcma_de + if (dma_set_mask_and_coherent(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + +- usb_dev = kzalloc(sizeof(struct bcma_hcd_device), GFP_KERNEL); ++ usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), ++ GFP_KERNEL); + if (!usb_dev) + return -ENOMEM; + +@@ -239,10 +240,8 @@ static int bcma_hcd_probe(struct bcma_de + ohci_addr = 0x18009000; + + usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr); +- if (IS_ERR(usb_dev->ohci_dev)) { +- err = PTR_ERR(usb_dev->ohci_dev); +- goto err_free_usb_dev; +- } ++ if (IS_ERR(usb_dev->ohci_dev)) ++ return PTR_ERR(usb_dev->ohci_dev); + + usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr); + if (IS_ERR(usb_dev->ehci_dev)) { +@@ -255,8 +254,6 @@ static int bcma_hcd_probe(struct bcma_de + + err_unregister_ohci_dev: + platform_device_unregister(usb_dev->ohci_dev); +-err_free_usb_dev: +- kfree(usb_dev); + return err; + } + diff --git a/target/linux/bcm53xx/patches-4.1/183-USB-bcma-fix-error-handling-in-bcma_hcd_create_pdev.patch b/target/linux/bcm53xx/patches-4.1/183-USB-bcma-fix-error-handling-in-bcma_hcd_create_pdev.patch new file mode 100644 index 0000000..91cd0fa --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/183-USB-bcma-fix-error-handling-in-bcma_hcd_create_pdev.patch @@ -0,0 +1,33 @@ +From 232996d1ba3002e7e80b18075e2838fc86f21412 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Thu, 11 Jun 2015 22:57:38 +0200 +Subject: [PATCH] USB: bcma: fix error handling in bcma_hcd_create_pdev() + +This patch makes bcma_hcd_create_pdev() not return NULL, but a prober +error code in case of an error. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -169,7 +169,7 @@ static struct platform_device *bcma_hcd_ + { + struct platform_device *hci_dev; + struct resource hci_res[2]; +- int ret = -ENOMEM; ++ int ret; + + memset(hci_res, 0, sizeof(hci_res)); + +@@ -183,7 +183,7 @@ static struct platform_device *bcma_hcd_ + hci_dev = platform_device_alloc(ohci ? "ohci-platform" : + "ehci-platform" , 0); + if (!hci_dev) +- return NULL; ++ return ERR_PTR(-ENOMEM); + + hci_dev->dev.parent = &dev->dev; + hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask; diff --git a/target/linux/bcm53xx/patches-4.1/184-USB-bcma-add-bcm53xx-support.patch b/target/linux/bcm53xx/patches-4.1/184-USB-bcma-add-bcm53xx-support.patch new file mode 100644 index 0000000..bca555c --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/184-USB-bcma-add-bcm53xx-support.patch @@ -0,0 +1,133 @@ +From b65851f41c22b8c69b8fe9ca7782d19ed2155efc Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Thu, 11 Jun 2015 22:57:39 +0200 +Subject: [PATCH] USB: bcma: add bcm53xx support + +The Broadcom ARM SoCs with this usb core need a different +initialization and they have a different core id. This patch adds +support for these USB 2.0 core. + +Signed-off-by: Felix Fietkau +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 81 +++++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 78 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -2,7 +2,8 @@ + * Broadcom specific Advanced Microcontroller Bus + * Broadcom USB-core driver (BCMA bus glue) + * +- * Copyright 2011-2012 Hauke Mehrtens ++ * Copyright 2011-2015 Hauke Mehrtens ++ * Copyright 2015 Felix Fietkau + * + * Based on ssb-ohci driver + * Copyright 2007 Michael Buesch +@@ -88,7 +89,7 @@ static void bcma_hcd_4716wa(struct bcma_ + } + + /* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */ +-static void bcma_hcd_init_chip(struct bcma_device *dev) ++static void bcma_hcd_init_chip_mips(struct bcma_device *dev) + { + u32 tmp; + +@@ -159,6 +160,70 @@ static void bcma_hcd_init_chip(struct bc + } + } + ++static void bcma_hcd_init_chip_arm_phy(struct bcma_device *dev) ++{ ++ struct bcma_device *arm_core; ++ void __iomem *dmu; ++ ++ arm_core = bcma_find_core(dev->bus, BCMA_CORE_ARMCA9); ++ if (!arm_core) { ++ dev_err(&dev->dev, "can not find ARM Cortex A9 ihost core\n"); ++ return; ++ } ++ ++ dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000); ++ if (!dmu) { ++ dev_err(&dev->dev, "can not map ARM Cortex A9 ihost core\n"); ++ return; ++ } ++ ++ /* Unlock DMU PLL settings */ ++ iowrite32(0x0000ea68, dmu + 0x180); ++ ++ /* Write USB 2.0 PLL control setting */ ++ iowrite32(0x00dd10c3, dmu + 0x164); ++ ++ /* Lock DMU PLL settings */ ++ iowrite32(0x00000000, dmu + 0x180); ++ ++ iounmap(dmu); ++} ++ ++static void bcma_hcd_init_chip_arm_hc(struct bcma_device *dev) ++{ ++ u32 val; ++ ++ /* ++ * Delay after PHY initialized to ensure HC is ready to be configured ++ */ ++ usleep_range(1000, 2000); ++ ++ /* Set packet buffer OUT threshold */ ++ val = bcma_read32(dev, 0x94); ++ val &= 0xffff; ++ val |= 0x80 << 16; ++ bcma_write32(dev, 0x94, val); ++ ++ /* Enable break memory transfer */ ++ val = bcma_read32(dev, 0x9c); ++ val |= 1; ++ bcma_write32(dev, 0x9c, val); ++} ++ ++static void bcma_hcd_init_chip_arm(struct bcma_device *dev) ++{ ++ bcma_core_enable(dev, 0); ++ ++ if (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4707 || ++ dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM53018) { ++ if (dev->bus->chipinfo.pkg == BCMA_PKG_ID_BCM4707 || ++ dev->bus->chipinfo.pkg == BCMA_PKG_ID_BCM4708) ++ bcma_hcd_init_chip_arm_phy(dev); ++ ++ bcma_hcd_init_chip_arm_hc(dev); ++ } ++} ++ + static const struct usb_ehci_pdata ehci_pdata = { + }; + +@@ -230,7 +295,16 @@ static int bcma_hcd_probe(struct bcma_de + if (!usb_dev) + return -ENOMEM; + +- bcma_hcd_init_chip(dev); ++ switch (dev->id.id) { ++ case BCMA_CORE_NS_USB20: ++ bcma_hcd_init_chip_arm(dev); ++ break; ++ case BCMA_CORE_USB20_HOST: ++ bcma_hcd_init_chip_mips(dev); ++ break; ++ default: ++ return -ENODEV; ++ } + + /* In AI chips EHCI is addrspace 0, OHCI is 1 */ + ohci_addr = dev->addr_s[0]; +@@ -299,6 +373,7 @@ static int bcma_hcd_resume(struct bcma_d + + static const struct bcma_device_id bcma_hcd_table[] = { + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), ++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS), + {}, + }; + MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); diff --git a/target/linux/bcm53xx/patches-4.1/185-USB-bcma-add-support-for-controlling-bus-power-throu.patch b/target/linux/bcm53xx/patches-4.1/185-USB-bcma-add-support-for-controlling-bus-power-throu.patch new file mode 100644 index 0000000..d9a8a1e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/185-USB-bcma-add-support-for-controlling-bus-power-throu.patch @@ -0,0 +1,82 @@ +From f3cf44a313b3687efd55ba091558e20a4d218c31 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Thu, 11 Jun 2015 22:57:40 +0200 +Subject: [PATCH] USB: bcma: add support for controlling bus power through GPIO + +On some boards a GPIO is needed to activate USB controller. Make it +possible to specify such a GPIO in device tree. + +Signed-off-by: Felix Fietkau +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -24,6 +24,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + +@@ -224,6 +226,23 @@ static void bcma_hcd_init_chip_arm(struc + } + } + ++static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val) ++{ ++ int gpio; ++ ++ gpio = of_get_named_gpio(dev->dev.of_node, "vcc-gpio", 0); ++ if (!gpio_is_valid(gpio)) ++ return; ++ ++ if (val) { ++ gpio_request(gpio, "bcma-hcd-gpio"); ++ gpio_set_value(gpio, 1); ++ } else { ++ gpio_set_value(gpio, 0); ++ gpio_free(gpio); ++ } ++} ++ + static const struct usb_ehci_pdata ehci_pdata = { + }; + +@@ -295,6 +314,8 @@ static int bcma_hcd_probe(struct bcma_de + if (!usb_dev) + return -ENOMEM; + ++ bcma_hci_platform_power_gpio(dev, true); ++ + switch (dev->id.id) { + case BCMA_CORE_NS_USB20: + bcma_hcd_init_chip_arm(dev); +@@ -347,6 +368,7 @@ static void bcma_hcd_remove(struct bcma_ + + static void bcma_hcd_shutdown(struct bcma_device *dev) + { ++ bcma_hci_platform_power_gpio(dev, false); + bcma_core_disable(dev, 0); + } + +@@ -354,6 +376,7 @@ static void bcma_hcd_shutdown(struct bcm + + static int bcma_hcd_suspend(struct bcma_device *dev) + { ++ bcma_hci_platform_power_gpio(dev, false); + bcma_core_disable(dev, 0); + + return 0; +@@ -361,6 +384,7 @@ static int bcma_hcd_suspend(struct bcma_ + + static int bcma_hcd_resume(struct bcma_device *dev) + { ++ bcma_hci_platform_power_gpio(dev, true); + bcma_core_enable(dev, 0); + + return 0; diff --git a/target/linux/bcm53xx/patches-4.1/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch b/target/linux/bcm53xx/patches-4.1/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch new file mode 100644 index 0000000..5031886 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch @@ -0,0 +1,75 @@ +From 0cb136f9882e4649ad6160bb7b48955ff728888c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 1 Nov 2015 08:17:21 +0100 +Subject: [PATCH V2] USB: bcma: switch to GPIO descriptor for power control +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +So far we were using simple (legacy) GPIO functions & some poor logic to +control power. It got many drawbacks: we were ignoring OF flags +(GPIO_ACTIVE_LOW), we were not setting direction to output and we were +assuming gpio_request success all the time. +Fix it by switching to gpiod functions and adding appropriate checks. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/usb/host/bcma-hcd.c | 21 ++++++++++----------- + 1 file changed, 10 insertions(+), 11 deletions(-) + +diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c +index 5398e3d..291aaa2 100644 +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -21,6 +21,7 @@ + */ + #include + #include ++#include + #include + #include + #include +@@ -36,6 +37,7 @@ MODULE_LICENSE("GPL"); + struct bcma_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; ++ struct gpio_desc *gpio_desc; + }; + + /* Wait for bitmask in a register to get set or cleared. +@@ -228,19 +230,12 @@ static void bcma_hcd_init_chip_arm(struct bcma_device *dev) + + static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val) + { +- int gpio; ++ struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + +- gpio = of_get_named_gpio(dev->dev.of_node, "vcc-gpio", 0); +- if (!gpio_is_valid(gpio)) ++ if (IS_ERR_OR_NULL(usb_dev->gpio_desc)) + return; + +- if (val) { +- gpio_request(gpio, "bcma-hcd-gpio"); +- gpio_set_value(gpio, 1); +- } else { +- gpio_set_value(gpio, 0); +- gpio_free(gpio); +- } ++ gpiod_set_value(usb_dev->gpio_desc, val); + } + + static const struct usb_ehci_pdata ehci_pdata = { +@@ -314,7 +309,11 @@ static int bcma_hcd_probe(struct bcma_device *dev) + if (!usb_dev) + return -ENOMEM; + +- bcma_hci_platform_power_gpio(dev, true); ++ if (dev->dev.of_node) ++ usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", ++ &dev->dev.of_node->fwnode); ++ if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) ++ gpiod_direction_output(usb_dev->gpio_desc, 1); + + switch (dev->id.id) { + case BCMA_CORE_NS_USB20: diff --git a/target/linux/bcm53xx/patches-4.1/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch b/target/linux/bcm53xx/patches-4.1/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch new file mode 100644 index 0000000..c404b7d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch @@ -0,0 +1,62 @@ +From 1420e53fc88673683f8990aa5342e7b2640ce165 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 18 Oct 2015 19:13:27 +0200 +Subject: [PATCH v3 1/6] usb: xhci: plat: fix adding usb3-lpm-capable quirk + +The xhci->quirks member is overwritten in xhci_gen_setup() with the +quirks given through the module load parameter. Without this patch the +usb3-lpm-capable quirk will be over written before it gets used. This +patch moves the quirks code to the xhci_plat_quirks() callback function +which gets called directly after the quirks member variable is +overwritten with the module load parameter. + +I do not have any hardware which is using usb3-lpm-capabls so I can not +test this on real hardware. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/xhci-plat.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -28,12 +28,20 @@ static struct hc_driver __read_mostly xh + + static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) + { ++ struct platform_device *pdev = to_platform_device(dev); ++ struct device_node *node = pdev->dev.of_node; ++ struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); ++ + /* + * As of now platform drivers don't provide MSI support so we ensure + * here that the generic code does not try to make a pci_dev from our + * dev struct in order to setup MSI + */ + xhci->quirks |= XHCI_PLAT; ++ ++ if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || ++ (pdata && pdata->usb3_lpm_capable)) ++ xhci->quirks |= XHCI_LPM_SUPPORT; + } + + /* called during probe() after chip reset completes */ +@@ -65,8 +73,6 @@ static int xhci_plat_start(struct usb_hc + + static int xhci_plat_probe(struct platform_device *pdev) + { +- struct device_node *node = pdev->dev.of_node; +- struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); + const struct hc_driver *driver; + struct xhci_hcd *xhci; + struct resource *res; +@@ -144,9 +150,6 @@ static int xhci_plat_probe(struct platfo + goto dealloc_usb2_hcd; + } + +- if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || +- (pdata && pdata->usb3_lpm_capable)) +- xhci->quirks |= XHCI_LPM_SUPPORT; + /* + * Set the xHCI pointer before xhci_plat_setup() (aka hcd_driver.reset) + * is called by usb_add_hcd(). diff --git a/target/linux/bcm53xx/patches-4.1/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch b/target/linux/bcm53xx/patches-4.1/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch new file mode 100644 index 0000000..f25a9e5 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch @@ -0,0 +1,135 @@ +From dd0e5f9a6a4aed849bdb80641c2a2350476cede7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 21 Jun 2015 11:10:49 +0200 +Subject: [PATCH v3 2/6] usb: xhci: add Broadcom specific fake doorbell +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This fixes problem with controller seeing devices only in some small +percentage of cold boots. +This quirk is also added to the platform data so we can activate it +when we register our platform driver. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/xhci-plat.c | 3 +++ + drivers/usb/host/xhci.c | 57 +++++++++++++++++++++++++++++++++++++--- + drivers/usb/host/xhci.h | 1 + + include/linux/usb/xhci_pdriver.h | 1 + + 4 files changed, 59 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -42,6 +42,9 @@ static void xhci_plat_quirks(struct devi + if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || + (pdata && pdata->usb3_lpm_capable)) + xhci->quirks |= XHCI_LPM_SUPPORT; ++ ++ if (pdata && pdata->usb3_fake_doorbell) ++ xhci->quirks |= XHCI_FAKE_DOORBELL; + } + + /* called during probe() after chip reset completes */ +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -121,6 +121,39 @@ int xhci_halt(struct xhci_hcd *xhci) + return ret; + } + ++static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id) ++{ ++ u32 temp; ++ ++ /* alloc a virt device for slot */ ++ if (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) { ++ xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); ++ return -ENOMEM; ++ } ++ ++ /* ring fake doorbell for slot_id ep 0 */ ++ xhci_ring_ep_doorbell(xhci, slot_id, 0, 0); ++ usleep_range(1000, 1500); ++ ++ /* read the status register to check if HSE is set or not? */ ++ temp = readl(&xhci->op_regs->status); ++ ++ /* clear HSE if set */ ++ if (temp & STS_FATAL) { ++ xhci_dbg(xhci, "HSE problem detected, status: 0x%x\n", temp); ++ temp &= ~(0x1fff); ++ temp |= STS_FATAL; ++ writel(temp, &xhci->op_regs->status); ++ usleep_range(1000, 1500); ++ readl(&xhci->op_regs->status); ++ } ++ ++ /* Free virt device */ ++ xhci_free_virt_device(xhci, slot_id); ++ ++ return 0; ++} ++ + /* + * Set the run bit and wait for the host to be running. + */ +@@ -557,10 +590,25 @@ int xhci_init(struct usb_hcd *hcd) + + static int xhci_run_finished(struct xhci_hcd *xhci) + { +- if (xhci_start(xhci)) { +- xhci_halt(xhci); +- return -ENODEV; ++ int err; ++ ++ err = xhci_start(xhci); ++ if (err) { ++ err = -ENODEV; ++ goto out_err; ++ } ++ if (xhci->quirks & XHCI_FAKE_DOORBELL) { ++ err = xhci_fake_doorbell(xhci, 1); ++ if (err) ++ goto out_err; ++ ++ err = xhci_start(xhci); ++ if (err) { ++ err = -ENODEV; ++ goto out_err; ++ } + } ++ + xhci->shared_hcd->state = HC_STATE_RUNNING; + xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; + +@@ -570,6 +618,9 @@ static int xhci_run_finished(struct xhci + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Finished xhci_run for USB3 roothub"); + return 0; ++out_err: ++ xhci_halt(xhci); ++ return err; + } + + /* +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1568,6 +1568,7 @@ struct xhci_hcd { + /* For controllers with a broken beyond repair streams implementation */ + #define XHCI_BROKEN_STREAMS (1 << 19) + #define XHCI_PME_STUCK_QUIRK (1 << 20) ++#define XHCI_FAKE_DOORBELL (1 << 21) + unsigned int num_active_eps; + unsigned int limit_active_eps; + /* There are two roothubs to keep track of bus suspend info for */ +--- a/include/linux/usb/xhci_pdriver.h ++++ b/include/linux/usb/xhci_pdriver.h +@@ -22,6 +22,7 @@ + */ + struct usb_xhci_pdata { + unsigned usb3_lpm_capable:1; ++ unsigned usb3_fake_doorbell:1; + }; + + #endif /* __USB_CORE_XHCI_PDRIVER_H */ diff --git a/target/linux/bcm53xx/patches-4.1/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch b/target/linux/bcm53xx/patches-4.1/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch new file mode 100644 index 0000000..17a9260 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch @@ -0,0 +1,75 @@ +From c7c7bf7fcbacadac7781783de25fe1e13e2a2c35 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 12:33:46 +0200 +Subject: [PATCH v3 3/6] usb: bcma: make helper creating platform dev more + generic +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Having "bool ohci" argument bounded us to two cases only and didn't +allow re-using this code for XHCI. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 24 +++++++++++++----------- + 1 file changed, 13 insertions(+), 11 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -244,7 +244,10 @@ static const struct usb_ehci_pdata ehci_ + static const struct usb_ohci_pdata ohci_pdata = { + }; + +-static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, bool ohci, u32 addr) ++static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, ++ const char *name, u32 addr, ++ const void *data, ++ size_t size) + { + struct platform_device *hci_dev; + struct resource hci_res[2]; +@@ -259,8 +262,7 @@ static struct platform_device *bcma_hcd_ + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + +- hci_dev = platform_device_alloc(ohci ? "ohci-platform" : +- "ehci-platform" , 0); ++ hci_dev = platform_device_alloc(name, 0); + if (!hci_dev) + return ERR_PTR(-ENOMEM); + +@@ -271,12 +273,8 @@ static struct platform_device *bcma_hcd_ + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; +- if (ohci) +- ret = platform_device_add_data(hci_dev, &ohci_pdata, +- sizeof(ohci_pdata)); +- else +- ret = platform_device_add_data(hci_dev, &ehci_pdata, +- sizeof(ehci_pdata)); ++ if (data) ++ ret = platform_device_add_data(hci_dev, data, size); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); +@@ -333,11 +331,15 @@ static int bcma_hcd_probe(struct bcma_de + && chipinfo->rev == 0) + ohci_addr = 0x18009000; + +- usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr); ++ usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, "ohci-platform", ++ ohci_addr, &ohci_pdata, ++ sizeof(ohci_pdata)); + if (IS_ERR(usb_dev->ohci_dev)) + return PTR_ERR(usb_dev->ohci_dev); + +- usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr); ++ usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, "ehci-platform", ++ dev->addr, &ehci_pdata, ++ sizeof(ehci_pdata)); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; diff --git a/target/linux/bcm53xx/patches-4.1/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch b/target/linux/bcm53xx/patches-4.1/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch new file mode 100644 index 0000000..262192b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch @@ -0,0 +1,112 @@ +From fa5622c2fadae573dd6b0f5bffe436b230b411f6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 12:52:07 +0200 +Subject: [PATCH v3 4/6] usb: bcma: use separated function for USB 2.0 + initialization +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This will allow adding USB 3.0 (XHCI) support cleanly. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 51 +++++++++++++++++++++++++++++++-------------- + 1 file changed, 35 insertions(+), 16 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -35,6 +35,7 @@ MODULE_DESCRIPTION("Common USB driver fo + MODULE_LICENSE("GPL"); + + struct bcma_hcd_device { ++ struct bcma_device *core; + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; + struct gpio_desc *gpio_desc; +@@ -288,31 +289,16 @@ err_alloc: + return ERR_PTR(ret); + } + +-static int bcma_hcd_probe(struct bcma_device *dev) ++static int bcma_hcd_usb20_init(struct bcma_hcd_device *usb_dev) + { +- int err; ++ struct bcma_device *dev = usb_dev->core; ++ struct bcma_chipinfo *chipinfo = &dev->bus->chipinfo; + u32 ohci_addr; +- struct bcma_hcd_device *usb_dev; +- struct bcma_chipinfo *chipinfo; +- +- chipinfo = &dev->bus->chipinfo; +- +- /* TODO: Probably need checks here; is the core connected? */ ++ int err; + + if (dma_set_mask_and_coherent(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + +- usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), +- GFP_KERNEL); +- if (!usb_dev) +- return -ENOMEM; +- +- if (dev->dev.of_node) +- usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", +- &dev->dev.of_node->fwnode); +- if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) +- gpiod_direction_output(usb_dev->gpio_desc, 1); +- + switch (dev->id.id) { + case BCMA_CORE_NS_USB20: + bcma_hcd_init_chip_arm(dev); +@@ -345,7 +331,6 @@ static int bcma_hcd_probe(struct bcma_de + goto err_unregister_ohci_dev; + } + +- bcma_set_drvdata(dev, usb_dev); + return 0; + + err_unregister_ohci_dev: +@@ -353,6 +338,40 @@ err_unregister_ohci_dev: + return err; + } + ++static int bcma_hcd_probe(struct bcma_device *dev) ++{ ++ int err; ++ struct bcma_hcd_device *usb_dev; ++ ++ /* TODO: Probably need checks here; is the core connected? */ ++ ++ usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), ++ GFP_KERNEL); ++ if (!usb_dev) ++ return -ENOMEM; ++ usb_dev->core = dev; ++ ++ if (dev->dev.of_node) ++ usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", ++ &dev->dev.of_node->fwnode); ++ if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) ++ gpiod_direction_output(usb_dev->gpio_desc, 1); ++ ++ switch (dev->id.id) { ++ case BCMA_CORE_USB20_HOST: ++ case BCMA_CORE_NS_USB20: ++ err = bcma_hcd_usb20_init(usb_dev); ++ if (err) ++ return err; ++ break; ++ default: ++ return -ENODEV; ++ } ++ ++ bcma_set_drvdata(dev, usb_dev); ++ return 0; ++} ++ + static void bcma_hcd_remove(struct bcma_device *dev) + { + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); diff --git a/target/linux/bcm53xx/patches-4.1/197-USB-bcma-add-USB-3.0-support.patch b/target/linux/bcm53xx/patches-4.1/197-USB-bcma-add-USB-3.0-support.patch new file mode 100644 index 0000000..34ab858 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/197-USB-bcma-add-USB-3.0-support.patch @@ -0,0 +1,295 @@ +From 121ec6539abedbc0e975cf35f48ee044b323e4c3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 17:14:26 +0200 +Subject: [PATCH v3 5/6] usb: bcma: add USB 3.0 support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 225 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 225 insertions(+) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + + MODULE_AUTHOR("Hauke Mehrtens"); + MODULE_DESCRIPTION("Common USB driver for BCMA Bus"); +@@ -38,6 +39,7 @@ struct bcma_hcd_device { + struct bcma_device *core; + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; ++ struct platform_device *xhci_dev; + struct gpio_desc *gpio_desc; + }; + +@@ -245,6 +247,10 @@ static const struct usb_ehci_pdata ehci_ + static const struct usb_ohci_pdata ohci_pdata = { + }; + ++static const struct usb_xhci_pdata xhci_pdata = { ++ .usb3_fake_doorbell = 1 ++}; ++ + static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, + const char *name, u32 addr, + const void *data, +@@ -338,6 +344,216 @@ err_unregister_ohci_dev: + return err; + } + ++static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, ++ u32 value, int timeout) ++{ ++ unsigned long deadline = jiffies + timeout; ++ u32 val; ++ ++ do { ++ val = readl(addr); ++ if ((val & mask) == value) ++ return true; ++ cpu_relax(); ++ udelay(10); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ pr_err("Timeout waiting for register %p\n", addr); ++ ++ return false; ++} ++ ++static void bcma_hcd_usb30_phy_init(struct bcma_hcd_device *bcma_hcd) ++{ ++ struct bcma_device *core = bcma_hcd->core; ++ struct bcma_bus *bus = core->bus; ++ struct bcma_chipinfo *chipinfo = &bus->chipinfo; ++ struct bcma_drv_cc_b *ccb = &bus->drv_cc_b; ++ struct bcma_device *arm_core; ++ void __iomem *dmu = NULL; ++ u32 cru_straps_ctrl; ++ ++ if (chipinfo->id != BCMA_CHIP_ID_BCM4707 && ++ chipinfo->id != BCMA_CHIP_ID_BCM53018) ++ return; ++ ++ arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9); ++ if (!arm_core) ++ return; ++ ++ dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000); ++ if (!dmu) ++ goto out; ++ ++ /* Check strapping of PCIE/USB3 SEL */ ++ cru_straps_ctrl = ioread32(dmu + 0x2a0); ++ if ((cru_straps_ctrl & 0x10) == 0) ++ goto out; ++ ++ /* Perform USB3 system soft reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); ++ ++ /* Enable MDIO. Setting MDCDIV as 26 */ ++ iowrite32(0x0000009a, ccb->mii + 0x000); ++ udelay(2); ++ ++ switch (chipinfo->id) { ++ case BCMA_CHIP_ID_BCM4707: ++ if (chipinfo->rev == 4) { ++ /* For NS-B0, USB3 PLL Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ /* Clear ana_pllSeqStart */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061000, ccb->mii + 0x004); ++ ++ /* CMOS Divider ratio to 25 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ /* Asserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582ec000, ccb->mii + 0x004); ++ ++ /* Deaaserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582e8000, ccb->mii + 0x004); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ ++ /* Set ana_pllSeqStart */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58069000, ccb->mii + 0x004); ++ ++ /* RXPMD block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8020, ccb->mii + 0x004); ++ ++ /* CDR int loop locking BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58120049, ccb->mii + 0x004); ++ ++ /* CDR int loop acquisition BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580e0049, ccb->mii + 0x004); ++ ++ /* CDR prop loop BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a005c, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ } else { ++ /* PLL30 block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e80e0, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a009c, ccb->mii + 0x004); ++ ++ /* Enable SSC */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8040, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a21d3, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061003, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ } ++ break; ++ case BCMA_CHIP_ID_BCM53018: ++ /* USB3 PLL Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ /* Assert Ana_Pllseq start */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061000, ccb->mii + 0x004); ++ ++ /* Assert CML Divider ratio to 26 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ /* Asserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582ec000, ccb->mii + 0x004); ++ ++ /* Deaaserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582e8000, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ ++ /* PLL frequency monitor enable */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58069000, ccb->mii + 0x004); ++ ++ /* PIPE Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8060, ccb->mii + 0x004); ++ ++ /* CMPMAX & CMPMINTH setting */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580af30d, ccb->mii + 0x004); ++ ++ /* DEGLITCH MIN & MAX setting */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580e6302, ccb->mii + 0x004); ++ ++ /* TXPMD block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8040, ccb->mii + 0x004); ++ ++ /* Enabling SSC */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061003, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ break; ++ } ++out: ++ if (dmu) ++ iounmap(dmu); ++} ++ ++static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd) ++{ ++ struct bcma_device *core = bcma_hcd->core; ++ ++ bcma_core_enable(core, 0); ++ ++ bcma_hcd_usb30_phy_init(bcma_hcd); ++ ++ bcma_hcd->xhci_dev = bcma_hcd_create_pdev(core, "xhci-hcd", core->addr, ++ &xhci_pdata, ++ sizeof(xhci_pdata)); ++ if (IS_ERR(bcma_hcd->ohci_dev)) ++ return PTR_ERR(bcma_hcd->ohci_dev); ++ ++ return 0; ++} ++ + static int bcma_hcd_probe(struct bcma_device *dev) + { + int err; +@@ -364,6 +580,11 @@ static int bcma_hcd_probe(struct bcma_de + if (err) + return err; + break; ++ case BCMA_CORE_NS_USB30: ++ err = bcma_hcd_usb30_init(usb_dev); ++ if (err) ++ return err; ++ break; + default: + return -ENODEV; + } +@@ -377,11 +598,14 @@ static void bcma_hcd_remove(struct bcma_ + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; ++ struct platform_device *xhci_dev = usb_dev->xhci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); ++ if (xhci_dev) ++ platform_device_unregister(xhci_dev); + + bcma_core_disable(dev, 0); + } +@@ -418,6 +642,7 @@ static int bcma_hcd_resume(struct bcma_d + static const struct bcma_device_id bcma_hcd_table[] = { + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS), ++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS), + {}, + }; + MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); diff --git a/target/linux/bcm53xx/patches-4.1/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch b/target/linux/bcm53xx/patches-4.1/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch new file mode 100644 index 0000000..06254b3 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch @@ -0,0 +1,86 @@ +From: Florian Fainelli +Subject: [PATCH] ARM: BCM5301x: Disable MMU and Dcache during decompression +Date: Tue, 14 Jul 2015 16:12:08 -0700 + +Use the existing __armv7_mmu_cache_flush() to perform the cache flush +since this does what we are after. + +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/compressed/Makefile | 4 +++ + arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 ++++++++++++++++++++++++ + arch/arm/boot/compressed/head.S | 2 ++ + 3 files changed, 43 insertions(+) + create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S + +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -31,6 +31,10 @@ ifeq ($(CONFIG_ARCH_ACORN),y) + OBJS += ll_char_wr.o font.o + endif + ++ifeq ($(CONFIG_ARCH_BCM_5301X),y) ++OBJS += head-bcm_5301x-mpcore.o ++endif ++ + ifeq ($(CONFIG_ARCH_SA1100),y) + OBJS += head-sa1100.o + endif +--- /dev/null ++++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S +@@ -0,0 +1,37 @@ ++/* ++ * ++ * Platform specific tweaks. This is merged into head.S by the linker. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++ .section ".start", "ax" ++ ++/* ++ * This code section is spliced into the head code by the linker ++ */ ++ ++__plat_uncompress_start: ++ ++ @ Preserve r8/r7 i.e. kernel entry values ++ mov r12, r8 ++ ++ @ Clear MMU enable and Dcache enable bits ++ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR ++ bic r0, #CR_C|CR_M ++ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR ++ nop ++ ++ @ Call the cache invalidation routine ++ bl __armv7_mmu_cache_flush_fn ++ nop ++ mov r0,#0 ++ ldr r3, =0x19022000 @ L2 cache controller, control reg ++ str r0, [r3, #0x100] @ Disable L2 cache ++ nop ++ ++ @ Restore ++ mov r8, r12 +--- a/arch/arm/boot/compressed/head.S ++++ b/arch/arm/boot/compressed/head.S +@@ -1152,6 +1152,7 @@ __armv7_mmu_cache_flush: + hierarchical: + mcr p15, 0, r10, c7, c10, 5 @ DMB + stmfd sp!, {r0-r7, r9-r11} ++ENTRY(__armv7_mmu_cache_flush_fn) + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field +@@ -1201,6 +1202,7 @@ iflush: + mcr p15, 0, r10, c7, c10, 4 @ DSB + mcr p15, 0, r10, c7, c5, 4 @ ISB + mov pc, lr ++ENDPROC(__armv7_mmu_cache_flush_fn) + + __armv5tej_mmu_cache_flush: + tst r4, #1 diff --git a/target/linux/bcm53xx/patches-4.1/301-ARM-BCM5301X-Add-SPROM.patch b/target/linux/bcm53xx/patches-4.1/301-ARM-BCM5301X-Add-SPROM.patch new file mode 100644 index 0000000..9ca76b3 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/301-ARM-BCM5301X-Add-SPROM.patch @@ -0,0 +1,26 @@ +From d404e0b22356078a51719fa911f6e09cb1a72d80 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 7 Jun 2015 16:18:18 +0200 +Subject: [PATCH] ARM: BCM5301X: Add SPROM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -105,6 +105,10 @@ + }; + }; + ++ sprom0: sprom@0 { ++ compatible = "brcm,bcm47xx-sprom"; ++ }; ++ + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; diff --git a/target/linux/bcm53xx/patches-4.1/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch b/target/linux/bcm53xx/patches-4.1/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch new file mode 100644 index 0000000..a1cbbe9 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch @@ -0,0 +1,69 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Subject: [PATCH] ARM: BCM5301X: Add DT for Linksys EA6300 V1 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-asus-rt-ac56u.dtb \ + bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wzr-1750dhp.dtb \ ++ bcm4708-linksys-ea6300-v1.dtb \ + bcm4708-luxul-xwc-1000.dtb \ + bcm4708-netgear-r6250.dtb \ + bcm4708-netgear-r6300-v2.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +@@ -0,0 +1,48 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Linksys EA6300 V1 ++ * ++ * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" ++ ++/ { ++ compatible = "linksys,ea6300v1", "brcm,bcm4708"; ++ model = "Linksys EA6300 V1"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.1/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch b/target/linux/bcm53xx/patches-4.1/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch new file mode 100644 index 0000000..802188d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch @@ -0,0 +1,41 @@ +From 504dba5b073a9009ae1e3f2fc53ea9c3aa10c38a Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Wed, 13 May 2015 20:56:38 +0200 +Subject: [PATCH] ARM: BCM5301X: Add Buffalo WXR-1900DHP clock and USB power + control +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Felix Fietkau +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -24,6 +24,23 @@ + reg = <0x00000000 0x08000000>; + }; + ++ clocks { ++ clk_periph: periph { ++ clock-frequency = <500000000>; ++ }; ++ }; ++ ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + diff --git a/target/linux/bcm53xx/patches-4.1/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch b/target/linux/bcm53xx/patches-4.1/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch new file mode 100644 index 0000000..ed4d1bc --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch @@ -0,0 +1,86 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Subject: [PATCH] ARM: BCM5301X: Set vcc-gpio for USB controllers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -24,6 +24,26 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -24,6 +24,17 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -24,6 +24,26 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + diff --git a/target/linux/bcm53xx/patches-4.1/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch b/target/linux/bcm53xx/patches-4.1/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch new file mode 100644 index 0000000..4e25647 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch @@ -0,0 +1,170 @@ +From eb1075cc48d3c315c7403822c33da9588ab76492 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 14 Jan 2015 08:33:25 +0100 +Subject: [PATCH] ARM: BCM5310X: Enable earlyprintk on tested devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 2 +- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 2 +- + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 2 +- + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 2 +- + 4 files changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-1750DHP (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -17,7 +17,7 @@ + model = "Netgear R6250 V1 (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-N18U (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-600DHP2 (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-900DHP (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -17,7 +17,7 @@ + model = "Netgear R8000 (BCM4709)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC56U (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC68U (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +@@ -17,7 +17,7 @@ + model = "Luxul XWC-1000 (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WXR-1900DHP"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -17,7 +17,7 @@ + model = "SmartRG SR400ac"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC87U"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -17,7 +17,7 @@ + model = "Netgear R7000"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts ++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +@@ -17,7 +17,7 @@ + model = "Linksys EA6300 V1"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { diff --git a/target/linux/bcm53xx/patches-4.1/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch b/target/linux/bcm53xx/patches-4.1/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch new file mode 100644 index 0000000..b53c57f --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch @@ -0,0 +1,173 @@ +From 36b2fbb3badf0e32b371e1f7579a95d4fe25c0e1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 14 Jan 2015 09:13:58 +0100 +Subject: [PATCH] ARM: BCM5301X: Specify RAM on devices by including HIGHMEM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 3 ++- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 3 ++- + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 3 ++- + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 3 ++- + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 3 ++- + 5 files changed, 10 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x18000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + spi { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + gpio-keys { +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x18000000>; + }; + + clocks { +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { diff --git a/target/linux/bcm53xx/patches-4.1/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch b/target/linux/bcm53xx/patches-4.1/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch new file mode 100644 index 0000000..f9ca7eb --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch @@ -0,0 +1,20 @@ +From: Felix Fietkau +Subject: [PATCH] ARM: BCM5301X: Add power button for Buffalo WZR-1750DHP + +Signed-off-by: Felix Fietkau +--- +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -123,6 +123,12 @@ + #address-cells = <1>; + #size-cells = <0>; + ++ power { ++ label = "Power"; ++ linux,code = ; ++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; ++ }; ++ + restart { + label = "Reset"; + linux,code = ; diff --git a/target/linux/bcm53xx/patches-4.1/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch b/target/linux/bcm53xx/patches-4.1/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch new file mode 100644 index 0000000..dad4f8a --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch @@ -0,0 +1,111 @@ +From b49d7bb4825654f81bcee8e219028712811515a5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 29 Jun 2015 08:11:36 +0200 +Subject: [PATCH] ARM: BCM5301X: Enable ChipCommon UART on untested devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 4 ++++ + arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 4 ++++ + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 4 ++++ + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 4 ++++ + arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 4 ++++ + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 5 +++++ + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 5 +++++ + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 5 +++++ + 8 files changed, 35 insertions(+) + +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -96,3 +96,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -83,3 +83,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -83,3 +83,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -77,3 +77,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -37,3 +37,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -65,3 +65,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -144,3 +144,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -127,3 +127,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -104,4 +104,5 @@ + + &uart0 { + status = "okay"; ++ clock-frequency = <125000000>; + }; diff --git a/target/linux/bcm53xx/patches-4.1/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch b/target/linux/bcm53xx/patches-4.1/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch new file mode 100644 index 0000000..ccdb28b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch @@ -0,0 +1,31 @@ +From d658c21d6697293a928434fd6ac19264b5a8948d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 30 Jan 2015 08:25:54 +0100 +Subject: [PATCH] mtd: bcm47xxpart: scan whole flash on ARCH_BCM_5301X +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/mtd/bcm47xxpart.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -120,9 +120,15 @@ static int bcm47xxpart_parse(struct mtd_ + /* Parse block by block looking for magics */ + for (offset = 0; offset <= master->size - blocksize; + offset += blocksize) { ++#ifndef CONFIG_ARCH_BCM_5301X ++ /* ++ * ARM routers may have partitions in higher memory. E.g. ++ * Netgear R8000 has board_data at 0x2600000. ++ */ + /* Nothing more in higher memory */ + if (offset >= 0x2000000) + break; ++#endif + + if (curr_part >= BCM47XXPART_MAX_PARTS) { + pr_warn("Reached maximum number of partitions, scanning stopped!\n"); diff --git a/target/linux/bcm53xx/patches-4.1/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch b/target/linux/bcm53xx/patches-4.1/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch new file mode 100644 index 0000000..41ef3b3 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch @@ -0,0 +1,19 @@ +--- a/drivers/mtd/spi-nor/Kconfig ++++ b/drivers/mtd/spi-nor/Kconfig +@@ -28,4 +28,10 @@ config SPI_FSL_QUADSPI + This enables support for the Quad SPI controller in master mode. + We only connect the NOR to this controller now. + ++config MTD_SPI_BCM53XXSPIFLASH ++ tristate "SPI-NOR flashes connected to the Broadcom ARM SoC" ++ depends on MTD_SPI_NOR ++ help ++ SPI driver for flashes used on Broadcom ARM SoCs. ++ + endif # MTD_SPI_NOR +--- a/drivers/mtd/spi-nor/Makefile ++++ b/drivers/mtd/spi-nor/Makefile +@@ -1,2 +1,3 @@ + obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o + obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o ++obj-$(CONFIG_MTD_SPI_BCM53XXSPIFLASH) += bcm53xxspiflash.o diff --git a/target/linux/bcm53xx/patches-4.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch b/target/linux/bcm53xx/patches-4.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch new file mode 100644 index 0000000..a3d0f75 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch @@ -0,0 +1,59 @@ +From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 16 Oct 2014 20:52:16 +0200 +Subject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/mtd/ubi/attach.c | 5 +++++ + drivers/mtd/ubi/io.c | 4 ++++ + drivers/mtd/ubi/ubi.h | 1 + + 3 files changed, 10 insertions(+) + +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -95,6 +95,9 @@ static int self_check_ai(struct ubi_devi + static struct ubi_ec_hdr *ech; + static struct ubi_vid_hdr *vidh; + ++/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */ ++bool erase_all_next; ++ + /** + * add_to_list - add physical eraseblock to a list. + * @ai: attaching information +@@ -1427,6 +1430,8 @@ int ubi_attach(struct ubi_device *ubi, i + if (!ai) + return -ENOMEM; + ++ erase_all_next = false; ++ + #ifdef CONFIG_MTD_UBI_FASTMAP + /* On small flash devices we disable fastmap in any case. */ + if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) { +--- a/drivers/mtd/ubi/io.c ++++ b/drivers/mtd/ubi/io.c +@@ -755,6 +755,10 @@ int ubi_io_read_ec_hdr(struct ubi_device + } + + magic = be32_to_cpu(ec_hdr->magic); ++ if (magic == 0xdeadc0de) ++ erase_all_next = true; ++ if (erase_all_next) ++ return read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF; + if (magic != UBI_EC_HDR_MAGIC) { + if (mtd_is_eccerr(read_err)) + return UBI_IO_BAD_HDR_EBADMSG; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -781,6 +781,7 @@ extern struct mutex ubi_devices_mutex; + extern struct blocking_notifier_head ubi_notifiers; + + /* attach.c */ ++extern bool erase_all_next; + int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum, + int ec, const struct ubi_vid_hdr *vid_hdr, int bitflips); + struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai, diff --git a/target/linux/bcm53xx/patches-4.1/700-bgmac-add-support-for-the-3rd-bus-core-device.patch b/target/linux/bcm53xx/patches-4.1/700-bgmac-add-support-for-the-3rd-bus-core-device.patch new file mode 100644 index 0000000..6be75bb --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/700-bgmac-add-support-for-the-3rd-bus-core-device.patch @@ -0,0 +1,63 @@ +From f5d5afc0b1402aae0f6a2350e43241603dbaff1e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 13 May 2015 10:46:47 +0200 +Subject: [PATCH] bgmac: add support for the 3rd bus core (device) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +So far we were supporting up to 2 cores but recent devices (e.g. Netgear +R8000) may use 3rd as well. Lower ones (1st, 2nd) are usually used for +some offloading then. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/net/ethernet/broadcom/bgmac.c | 28 +++++++++++++++++++++++----- + 1 file changed, 23 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1561,11 +1561,20 @@ static int bgmac_probe(struct bcma_devic + struct net_device *net_dev; + struct bgmac *bgmac; + struct ssb_sprom *sprom = &core->bus->sprom; +- u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac; ++ u8 *mac; + int err; + +- /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */ +- if (core->core_unit > 1) { ++ switch (core->core_unit) { ++ case 0: ++ mac = sprom->et0mac; ++ break; ++ case 1: ++ mac = sprom->et1mac; ++ break; ++ case 2: ++ mac = sprom->et2mac; ++ break; ++ default: + pr_err("Unsupported core_unit %d\n", core->core_unit); + return -ENOTSUPP; + } +@@ -1600,8 +1609,17 @@ static int bgmac_probe(struct bcma_devic + } + bgmac->cmn = core->bus->drv_gmac_cmn.core; + +- bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr : +- sprom->et0phyaddr; ++ switch (core->core_unit) { ++ case 0: ++ bgmac->phyaddr = sprom->et0phyaddr; ++ break; ++ case 1: ++ bgmac->phyaddr = sprom->et1phyaddr; ++ break; ++ case 2: ++ bgmac->phyaddr = sprom->et2phyaddr; ++ break; ++ } + bgmac->phyaddr &= BGMAC_PHY_MASK; + if (bgmac->phyaddr == BGMAC_PHY_MASK) { + bgmac_err(bgmac, "No PHY found\n"); diff --git a/target/linux/bcm53xx/patches-4.1/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch b/target/linux/bcm53xx/patches-4.1/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch new file mode 100644 index 0000000..dfc422e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch @@ -0,0 +1,42 @@ +From 4abdde3ad6bc0b3b157c4bf6ec0bf139d11d07e8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 13 May 2015 14:13:28 +0200 +Subject: [PATCH] b53: add hacky CPU port fixes for devices not using port 5 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/net/phy/b53/b53_common.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/phy/b53/b53_common.c ++++ b/drivers/net/phy/b53/b53_common.c +@@ -25,6 +25,7 @@ + #include + #include + #include ++#include + + #include "b53_regs.h" + #include "b53_priv.h" +@@ -1313,6 +1314,18 @@ static int b53_switch_init(struct b53_de + sw_dev->cpu_port = 5; + } + ++ if (of_machine_is_compatible("asus,rt-ac87u")) ++ sw_dev->cpu_port = 7; ++ else if (of_machine_is_compatible("netgear,r8000")) ++ sw_dev->cpu_port = 8; ++ ++ /* ++ * Workaround for devices using port 8 (connected to the 3rd iface). ++ * For some reason it doesn't work (no packets on eth2). ++ */ ++ if (of_machine_is_compatible("netgear,r8000")) ++ sw_dev->cpu_port = 5; ++ + /* cpu port is always last */ + sw_dev->ports = sw_dev->cpu_port + 1; + dev->enabled_ports |= BIT(sw_dev->cpu_port); diff --git a/target/linux/bcm53xx/patches-4.1/800-bcma-use-two-different-initcalls-if-built-in.patch b/target/linux/bcm53xx/patches-4.1/800-bcma-use-two-different-initcalls-if-built-in.patch new file mode 100644 index 0000000..9f2cd39 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/800-bcma-use-two-different-initcalls-if-built-in.patch @@ -0,0 +1,65 @@ +From 666bdfc027cde41a171862dc698987a378c8b66a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 9 Feb 2015 18:00:42 +0100 +Subject: [PATCH RFC] bcma: use two different initcalls if built-in +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is needed as we can't initialize bus during fs_initcall. +Initialization requires SPROM which depends on NVRAM which depends on +mtd. Since mtd, spi, nand, spi-nor use standard module_init, we have to +do the same in bcma. +Without this we'll try to initialize SPROM without having a ready SPROM +proviver registered using bcma_arch_register_fallback_sprom. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- +While this patch seems to work and I can compile bcma as built-in and +module, I'm not too proud of it. I don't really like these #if(n)def +tricks and I'm afraid bcma_modinit may be called even if +bcma_modinit_early failed. + +Do you see any better idea of solving this? +--- + drivers/bcma/main.c | 16 ++++++++++++++-- + 1 file changed, 14 insertions(+), 2 deletions(-) + +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -637,13 +637,25 @@ static int bcma_device_uevent(struct dev + core->id.rev, core->id.class); + } + ++/* Bus has to be registered early, before any bcma driver */ ++static int __init bcma_modinit_early(void) ++{ ++ return bus_register(&bcma_bus_type); ++} ++#ifndef MODULE ++fs_initcall(bcma_modinit_early); ++#endif ++ ++/* Initialization has to be done later with SPI/mtd/NAND/SPROM available */ + static int __init bcma_modinit(void) + { + int err; + +- err = bus_register(&bcma_bus_type); ++#ifdef MODULE ++ err = bcma_modinit_early(); + if (err) + return err; ++#endif + + err = bcma_host_soc_register_driver(); + if (err) { +@@ -660,7 +672,7 @@ static int __init bcma_modinit(void) + + return err; + } +-fs_initcall(bcma_modinit); ++module_init(bcma_modinit); + + static void __exit bcma_modexit(void) + { diff --git a/target/linux/bcm53xx/patches-4.1/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch b/target/linux/bcm53xx/patches-4.1/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch new file mode 100644 index 0000000..c1dfa92 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.1/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch @@ -0,0 +1,42 @@ +From 21500872c1dba33848ddcf6bea97d58772675d36 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 17 May 2015 14:00:52 +0200 +Subject: [PATCH] mtd: bcm47xxpart: workaround for Asus RT-AC87U "asus" + partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/mtd/bcm47xxpart.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + + #include + +@@ -135,6 +136,17 @@ static int bcm47xxpart_parse(struct mtd_ + break; + } + ++ /* ++ * Ugly workaround for Asus RT-AC87U and its "asus" partition. ++ * It uses JFFS2 which we don't (want to) detect. We should ++ * probably use DT to define partitions but we need a working ++ * TRX firmware splitter first. ++ */ ++ if (of_machine_is_compatible("asus,rt-ac87u") && offset == 0x7ec0000) { ++ bcm47xxpart_add_part(&parts[curr_part++], "asus", offset, MTD_WRITEABLE); ++ continue; ++ } ++ + /* Read beginning of the block */ + if (mtd_read(master, offset, BCM47XXPART_BYTES_TO_READ, + &bytes_read, (uint8_t *)buf) < 0) { diff --git a/target/linux/bcm53xx/patches-4.3/043-clk-iproc-Fix-PLL-output-frequency-calculation.patch b/target/linux/bcm53xx/patches-4.3/043-clk-iproc-Fix-PLL-output-frequency-calculation.patch new file mode 100644 index 0000000..20dd90e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/043-clk-iproc-Fix-PLL-output-frequency-calculation.patch @@ -0,0 +1,59 @@ +From 63243a4da7d0dfa19dcacd0a529782eeb2f86f92 Mon Sep 17 00:00:00 2001 +From: Simran Rai +Date: Mon, 19 Oct 2015 15:27:19 -0700 +Subject: [PATCH] clk: iproc: Fix PLL output frequency calculation + +This patch affects the clocks that use fractional ndivider in their +PLL output frequency calculation. Instead of 2^20 divide factor, the +clock's ndiv integer shift was used. Fixed the bug by replacing ndiv +integer shift with 2^20 factor. + +Signed-off-by: Simran Rai +Signed-off-by: Ray Jui +Reviewed-by: Scott Branden +Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support") +Cc: # v4.1+ +Signed-off-by: Michael Turquette +--- + drivers/clk/bcm/clk-iproc-pll.c | 13 +++++-------- + 1 file changed, 5 insertions(+), 8 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_ra + struct iproc_pll *pll = clk->pll; + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + u32 val; +- u64 ndiv; +- unsigned int ndiv_int, ndiv_frac, pdiv; ++ u64 ndiv, ndiv_int, ndiv_frac; ++ unsigned int pdiv; + + if (parent_rate == 0) + return 0; +@@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_ra + val = readl(pll->pll_base + ctrl->ndiv_int.offset); + ndiv_int = (val >> ctrl->ndiv_int.shift) & + bit_mask(ctrl->ndiv_int.width); +- ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift; ++ ndiv = ndiv_int << 20; + + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { + val = readl(pll->pll_base + ctrl->ndiv_frac.offset); + ndiv_frac = (val >> ctrl->ndiv_frac.shift) & + bit_mask(ctrl->ndiv_frac.width); +- +- if (ndiv_frac != 0) +- ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) | +- ndiv_frac; ++ ndiv += ndiv_frac; + } + + val = readl(pll->pll_base + ctrl->pdiv.offset); + pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); + +- clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift; ++ clk->rate = (ndiv * parent_rate) >> 20; + + if (pdiv == 0) + clk->rate *= 2; diff --git a/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch b/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch new file mode 100644 index 0000000..f65aa9c --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/044-clk-cygnus-Convert-all-macros-to-all-caps.patch @@ -0,0 +1,292 @@ +From b5116083e227fa478e20d5ed945430088aa1a00b Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 15:48:25 -0400 +Subject: [PATCH 44/50] clk: cygnus: Convert all macros to all caps + +The macros that are being used to initialize the values of the clk +structures should be all caps. Find and replace all of them with their +relevant counterparts. + +Signed-off-by: Jon Mason +--- + drivers/clk/bcm/clk-cygnus.c | 146 +++++++++++++++++++++---------------------- + 1 file changed, 73 insertions(+), 73 deletions(-) + +--- a/drivers/clk/bcm/clk-cygnus.c ++++ b/drivers/clk/bcm/clk-cygnus.c +@@ -23,28 +23,28 @@ + #include + #include "clk-iproc.h" + +-#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, } ++#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } + +-#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ ++#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ + .pwr_shift = ps, .iso_shift = is } + +-#define sw_ctrl_val(o, s) { .offset = o, .shift = s, } ++#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, } + +-#define asiu_div_val(o, es, hs, hw, ls, lw) \ ++#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \ + { .offset = o, .en_shift = es, .high_shift = hs, \ + .high_width = hw, .low_shift = ls, .low_width = lw } + +-#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ ++#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ + .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ + .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ + .ka_width = kaw } + +-#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo } ++#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } + +-#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \ ++#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ + .hold_shift = hs, .bypass_shift = bs } + +-#define asiu_gate_val(o, es) { .offset = o, .en_shift = es } ++#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es } + + static void __init cygnus_armpll_init(struct device_node *node) + { +@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygn + static const struct iproc_pll_ctrl genpll = { + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | + IPROC_CLK_PLL_NEEDS_SW_CFG, +- .aon = aon_val(0x0, 2, 1, 0), +- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3), +- .sw_ctrl = sw_ctrl_val(0x10, 31), +- .ndiv_int = reg_val(0x10, 20, 10), +- .ndiv_frac = reg_val(0x10, 0, 20), +- .pdiv = reg_val(0x14, 0, 4), +- .vco_ctrl = vco_ctrl_val(0x18, 0x1c), +- .status = reg_val(0x28, 12, 1), ++ .aon = AON_VAL(0x0, 2, 1, 0), ++ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), ++ .sw_ctrl = SW_CTRL_VAL(0x10, 31), ++ .ndiv_int = REG_VAL(0x10, 20, 10), ++ .ndiv_frac = REG_VAL(0x10, 0, 20), ++ .pdiv = REG_VAL(0x14, 0, 4), ++ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), ++ .status = REG_VAL(0x28, 12, 1), + }; + + static const struct iproc_clk_ctrl genpll_clk[] = { + [BCM_CYGNUS_GENPLL_AXI21_CLK] = { + .channel = BCM_CYGNUS_GENPLL_AXI21_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 6, 0, 12), +- .mdiv = reg_val(0x20, 0, 8), ++ .enable = ENABLE_VAL(0x4, 6, 0, 12), ++ .mdiv = REG_VAL(0x20, 0, 8), + }, + [BCM_CYGNUS_GENPLL_250MHZ_CLK] = { + .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 7, 1, 13), +- .mdiv = reg_val(0x20, 10, 8), ++ .enable = ENABLE_VAL(0x4, 7, 1, 13), ++ .mdiv = REG_VAL(0x20, 10, 8), + }, + [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = { + .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 8, 2, 14), +- .mdiv = reg_val(0x20, 20, 8), ++ .enable = ENABLE_VAL(0x4, 8, 2, 14), ++ .mdiv = REG_VAL(0x20, 20, 8), + }, + [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = { + .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 9, 3, 15), +- .mdiv = reg_val(0x24, 0, 8), ++ .enable = ENABLE_VAL(0x4, 9, 3, 15), ++ .mdiv = REG_VAL(0x24, 0, 8), + }, + [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = { + .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 10, 4, 16), +- .mdiv = reg_val(0x24, 10, 8), ++ .enable = ENABLE_VAL(0x4, 10, 4, 16), ++ .mdiv = REG_VAL(0x24, 10, 8), + }, + [BCM_CYGNUS_GENPLL_CAN_CLK] = { + .channel = BCM_CYGNUS_GENPLL_CAN_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x4, 11, 5, 17), +- .mdiv = reg_val(0x24, 20, 8), ++ .enable = ENABLE_VAL(0x4, 11, 5, 17), ++ .mdiv = REG_VAL(0x24, 20, 8), + }, + }; + +@@ -113,51 +113,51 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn + + static const struct iproc_pll_ctrl lcpll0 = { + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, +- .aon = aon_val(0x0, 2, 5, 4), +- .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4), +- .sw_ctrl = sw_ctrl_val(0x4, 31), +- .ndiv_int = reg_val(0x4, 16, 10), +- .pdiv = reg_val(0x4, 26, 4), +- .vco_ctrl = vco_ctrl_val(0x10, 0x14), +- .status = reg_val(0x18, 12, 1), ++ .aon = AON_VAL(0x0, 2, 5, 4), ++ .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), ++ .sw_ctrl = SW_CTRL_VAL(0x4, 31), ++ .ndiv_int = REG_VAL(0x4, 16, 10), ++ .pdiv = REG_VAL(0x4, 26, 4), ++ .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14), ++ .status = REG_VAL(0x18, 12, 1), + }; + + static const struct iproc_clk_ctrl lcpll0_clk[] = { + [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 7, 1, 13), +- .mdiv = reg_val(0x8, 0, 8), ++ .enable = ENABLE_VAL(0x0, 7, 1, 13), ++ .mdiv = REG_VAL(0x8, 0, 8), + }, + [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 8, 2, 14), +- .mdiv = reg_val(0x8, 10, 8), ++ .enable = ENABLE_VAL(0x0, 8, 2, 14), ++ .mdiv = REG_VAL(0x8, 10, 8), + }, + [BCM_CYGNUS_LCPLL0_SDIO_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 9, 3, 15), +- .mdiv = reg_val(0x8, 20, 8), ++ .enable = ENABLE_VAL(0x0, 9, 3, 15), ++ .mdiv = REG_VAL(0x8, 20, 8), + }, + [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 10, 4, 16), +- .mdiv = reg_val(0xc, 0, 8), ++ .enable = ENABLE_VAL(0x0, 10, 4, 16), ++ .mdiv = REG_VAL(0xc, 0, 8), + }, + [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = { + .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 11, 5, 17), +- .mdiv = reg_val(0xc, 10, 8), ++ .enable = ENABLE_VAL(0x0, 11, 5, 17), ++ .mdiv = REG_VAL(0xc, 10, 8), + }, + [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = { + .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED, + .flags = IPROC_CLK_AON, +- .enable = enable_val(0x0, 12, 6, 18), +- .mdiv = reg_val(0xc, 20, 8), ++ .enable = ENABLE_VAL(0x0, 12, 6, 18), ++ .mdiv = REG_VAL(0xc, 20, 8), + }, + }; + +@@ -189,52 +189,52 @@ static const struct iproc_pll_vco_param + static const struct iproc_pll_ctrl mipipll = { + .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC | + IPROC_CLK_NEEDS_READ_BACK, +- .aon = aon_val(0x0, 4, 17, 16), +- .asiu = asiu_gate_val(0x0, 3), +- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4), +- .ndiv_int = reg_val(0x10, 20, 10), +- .ndiv_frac = reg_val(0x10, 0, 20), +- .pdiv = reg_val(0x14, 0, 4), +- .vco_ctrl = vco_ctrl_val(0x18, 0x1c), +- .status = reg_val(0x28, 12, 1), ++ .aon = AON_VAL(0x0, 4, 17, 16), ++ .asiu = ASIU_GATE_VAL(0x0, 3), ++ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), ++ .ndiv_int = REG_VAL(0x10, 20, 10), ++ .ndiv_frac = REG_VAL(0x10, 0, 20), ++ .pdiv = REG_VAL(0x14, 0, 4), ++ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), ++ .status = REG_VAL(0x28, 12, 1), + }; + + static const struct iproc_clk_ctrl mipipll_clk[] = { + [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = { + .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 12, 6, 18), +- .mdiv = reg_val(0x20, 0, 8), ++ .enable = ENABLE_VAL(0x4, 12, 6, 18), ++ .mdiv = REG_VAL(0x20, 0, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH1_LCD] = { + .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 13, 7, 19), +- .mdiv = reg_val(0x20, 10, 8), ++ .enable = ENABLE_VAL(0x4, 13, 7, 19), ++ .mdiv = REG_VAL(0x20, 10, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH2_V3D] = { + .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 14, 8, 20), +- .mdiv = reg_val(0x20, 20, 8), ++ .enable = ENABLE_VAL(0x4, 14, 8, 20), ++ .mdiv = REG_VAL(0x20, 20, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = { + .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 15, 9, 21), +- .mdiv = reg_val(0x24, 0, 8), ++ .enable = ENABLE_VAL(0x4, 15, 9, 21), ++ .mdiv = REG_VAL(0x24, 0, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = { + .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 16, 10, 22), +- .mdiv = reg_val(0x24, 10, 8), ++ .enable = ENABLE_VAL(0x4, 16, 10, 22), ++ .mdiv = REG_VAL(0x24, 10, 8), + }, + [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = { + .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED, + .flags = IPROC_CLK_NEEDS_READ_BACK, +- .enable = enable_val(0x4, 17, 11, 23), +- .mdiv = reg_val(0x24, 20, 8), ++ .enable = ENABLE_VAL(0x4, 17, 11, 23), ++ .mdiv = REG_VAL(0x24, 20, 8), + }, + }; + +@@ -247,15 +247,15 @@ static void __init cygnus_mipipll_clk_in + CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init); + + static const struct iproc_asiu_div asiu_div[] = { +- [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10), +- [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10), +- [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10), ++ [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10), ++ [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10), ++ [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10), + }; + + static const struct iproc_asiu_gate asiu_gate[] = { +- [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7), +- [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9), +- [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0), ++ [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7), ++ [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9), ++ [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0), + }; + + static void __init cygnus_asiu_init(struct device_node *node) diff --git a/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch b/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch new file mode 100644 index 0000000..318bd5c --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/045-clk-iproc-Add-PWRCTRL-support.patch @@ -0,0 +1,120 @@ +From 7c70cb333deb6e2f88da9c94ddd6b3b00c97b93a Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 15:48:26 -0400 +Subject: [PATCH 45/50] clk: iproc: Add PWRCTRL support + +Some iProc SoC clocks use a different way to control clock power, via +the PWRDWN bit in the PLL control register. Since the PLL control +register is used to access the PWRDWN bit, there is no need for the +pwr_base when this is being used. A new flag, IPROC_CLK_EMBED_PWRCTRL, +has been added to identify this usage. We can use the AON interface to +write the values to enable/disable PWRDOWN. + +Signed-off-by: Jon Mason +--- + drivers/clk/bcm/clk-iproc-pll.c | 55 ++++++++++++++++++++++++++++------------- + drivers/clk/bcm/clk-iproc.h | 6 +++++ + 2 files changed, 44 insertions(+), 17 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -148,14 +148,25 @@ static void __pll_disable(struct iproc_p + writel(val, pll->asiu_base + ctrl->asiu.offset); + } + +- /* latch input value so core power can be shut down */ +- val = readl(pll->pwr_base + ctrl->aon.offset); +- val |= (1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); +- +- /* power down the core */ +- val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { ++ val = readl(pll->pll_base + ctrl->aon.offset); ++ val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); ++ writel(val, pll->pll_base + ctrl->aon.offset); ++ ++ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) ++ readl(pll->pll_base + ctrl->aon.offset); ++ } ++ ++ if (pll->pwr_base) { ++ /* latch input value so core power can be shut down */ ++ val = readl(pll->pwr_base + ctrl->aon.offset); ++ val |= (1 << ctrl->aon.iso_shift); ++ writel(val, pll->pwr_base + ctrl->aon.offset); ++ ++ /* power down the core */ ++ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); ++ writel(val, pll->pwr_base + ctrl->aon.offset); ++ } + } + + static int __pll_enable(struct iproc_pll *pll) +@@ -163,11 +174,22 @@ static int __pll_enable(struct iproc_pll + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + u32 val; + +- /* power up the PLL and make sure it's not latched */ +- val = readl(pll->pwr_base + ctrl->aon.offset); +- val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; +- val &= ~(1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { ++ val = readl(pll->pll_base + ctrl->aon.offset); ++ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); ++ writel(val, pll->pll_base + ctrl->aon.offset); ++ ++ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) ++ readl(pll->pll_base + ctrl->aon.offset); ++ } ++ ++ if (pll->pwr_base) { ++ /* power up the PLL and make sure it's not latched */ ++ val = readl(pll->pwr_base + ctrl->aon.offset); ++ val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; ++ val &= ~(1 << ctrl->aon.iso_shift); ++ writel(val, pll->pwr_base + ctrl->aon.offset); ++ } + + /* certain PLLs also need to be ungated from the ASIU top level */ + if (ctrl->flags & IPROC_CLK_PLL_ASIU) { +@@ -607,9 +629,8 @@ void __init iproc_pll_clk_setup(struct d + if (WARN_ON(!pll->pll_base)) + goto err_pll_iomap; + ++ /* Some SoCs do not require the pwr_base, thus failing is not fatal */ + pll->pwr_base = of_iomap(node, 1); +- if (WARN_ON(!pll->pwr_base)) +- goto err_pwr_iomap; + + /* some PLLs require gating control at the top ASIU level */ + if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { +@@ -692,9 +713,9 @@ err_pll_register: + iounmap(pll->asiu_base); + + err_asiu_iomap: +- iounmap(pll->pwr_base); ++ if (pll->pwr_base) ++ iounmap(pll->pwr_base); + +-err_pwr_iomap: + iounmap(pll->pll_base); + + err_pll_iomap: +--- a/drivers/clk/bcm/clk-iproc.h ++++ b/drivers/clk/bcm/clk-iproc.h +@@ -49,6 +49,12 @@ + #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4) + + /* ++ * Some PLLs use a different way to control clock power, via the PWRDWN bit in ++ * the PLL control register ++ */ ++#define IPROC_CLK_EMBED_PWRCTRL BIT(5) ++ ++/* + * Parameters for VCO frequency configuration + * + * VCO frequency = diff --git a/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch b/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch new file mode 100644 index 0000000..c8eda8d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch @@ -0,0 +1,219 @@ +From d358480591b34d081806ecb5a9474930a4d59f8a Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 15:48:27 -0400 +Subject: [PATCH 46/50] clk: nsp: add clock support for Broadcom Northstar Plus + SoC + +The Broadcom Northstar Plus SoC is architected under the iProc +architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all +derived from an onboard crystal. + +Signed-off-by: Jon Mason +--- + drivers/clk/bcm/Makefile | 2 + + drivers/clk/bcm/clk-nsp.c | 135 ++++++++++++++++++++++++++++++++++++ + include/dt-bindings/clock/bcm-nsp.h | 51 ++++++++++++++ + 3 files changed, 188 insertions(+) + create mode 100644 drivers/clk/bcm/clk-nsp.c + create mode 100644 include/dt-bindings/clock/bcm-nsp.h + +--- a/drivers/clk/bcm/Makefile ++++ b/drivers/clk/bcm/Makefile +@@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281 + obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o + obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o + obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o ++obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o ++obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o +--- /dev/null ++++ b/drivers/clk/bcm/clk-nsp.c +@@ -0,0 +1,135 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "clk-iproc.h" ++ ++#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } ++ ++#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ ++ .pwr_shift = ps, .iso_shift = is } ++ ++#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ ++ .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ ++ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ ++ .ka_width = kaw } ++ ++#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ ++ .hold_shift = hs, .bypass_shift = bs } ++ ++static void __init nsp_armpll_init(struct device_node *node) ++{ ++ iproc_armpll_setup(node); ++} ++CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init); ++ ++static const struct iproc_pll_ctrl genpll = { ++ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, ++ .aon = AON_VAL(0x0, 1, 12, 0), ++ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), ++ .ndiv_int = REG_VAL(0x14, 20, 10), ++ .ndiv_frac = REG_VAL(0x14, 0, 20), ++ .pdiv = REG_VAL(0x18, 24, 3), ++ .status = REG_VAL(0x20, 12, 1), ++}; ++ ++static const struct iproc_clk_ctrl genpll_clk[] = { ++ [BCM_NSP_GENPLL_PHY_CLK] = { ++ .channel = BCM_NSP_GENPLL_PHY_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 12, 6, 18), ++ .mdiv = REG_VAL(0x18, 16, 8), ++ }, ++ [BCM_NSP_GENPLL_ENET_SW_CLK] = { ++ .channel = BCM_NSP_GENPLL_ENET_SW_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 13, 7, 19), ++ .mdiv = REG_VAL(0x18, 8, 8), ++ }, ++ [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = { ++ .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 14, 8, 20), ++ .mdiv = REG_VAL(0x18, 0, 8), ++ }, ++ [BCM_NSP_GENPLL_IPROCFAST_CLK] = { ++ .channel = BCM_NSP_GENPLL_IPROCFAST_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 15, 9, 21), ++ .mdiv = REG_VAL(0x1c, 16, 8), ++ }, ++ [BCM_NSP_GENPLL_SATA1_CLK] = { ++ .channel = BCM_NSP_GENPLL_SATA1_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 16, 10, 22), ++ .mdiv = REG_VAL(0x1c, 8, 8), ++ }, ++ [BCM_NSP_GENPLL_SATA2_CLK] = { ++ .channel = BCM_NSP_GENPLL_SATA2_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x4, 17, 11, 23), ++ .mdiv = REG_VAL(0x1c, 0, 8), ++ }, ++}; ++ ++static void __init nsp_genpll_clk_init(struct device_node *node) ++{ ++ iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk, ++ ARRAY_SIZE(genpll_clk)); ++} ++CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init); ++ ++static const struct iproc_pll_ctrl lcpll0 = { ++ .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, ++ .aon = AON_VAL(0x0, 1, 24, 0), ++ .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4), ++ .ndiv_int = REG_VAL(0x4, 20, 8), ++ .ndiv_frac = REG_VAL(0x4, 0, 20), ++ .pdiv = REG_VAL(0x4, 28, 3), ++ .status = REG_VAL(0x10, 12, 1), ++}; ++ ++static const struct iproc_clk_ctrl lcpll0_clk[] = { ++ [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = { ++ .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x0, 6, 3, 9), ++ .mdiv = REG_VAL(0x8, 24, 8), ++ }, ++ [BCM_NSP_LCPLL0_SDIO_CLK] = { ++ .channel = BCM_NSP_LCPLL0_SDIO_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x0, 7, 4, 10), ++ .mdiv = REG_VAL(0x8, 16, 8), ++ }, ++ [BCM_NSP_LCPLL0_DDR_PHY_CLK] = { ++ .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK, ++ .flags = IPROC_CLK_AON, ++ .enable = ENABLE_VAL(0x0, 8, 5, 11), ++ .mdiv = REG_VAL(0x8, 8, 8), ++ }, ++}; ++ ++static void __init nsp_lcpll0_clk_init(struct device_node *node) ++{ ++ iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk, ++ ARRAY_SIZE(lcpll0_clk)); ++} ++CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init); +--- /dev/null ++++ b/include/dt-bindings/clock/bcm-nsp.h +@@ -0,0 +1,51 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef _CLOCK_BCM_NSP_H ++#define _CLOCK_BCM_NSP_H ++ ++/* GENPLL clock channel ID */ ++#define BCM_NSP_GENPLL 0 ++#define BCM_NSP_GENPLL_PHY_CLK 1 ++#define BCM_NSP_GENPLL_ENET_SW_CLK 2 ++#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 ++#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 ++#define BCM_NSP_GENPLL_SATA1_CLK 5 ++#define BCM_NSP_GENPLL_SATA2_CLK 6 ++ ++/* LCPLL0 clock channel ID */ ++#define BCM_NSP_LCPLL0 0 ++#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 ++#define BCM_NSP_LCPLL0_SDIO_CLK 2 ++#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 ++ ++#endif /* _CLOCK_BCM_NSP_H */ diff --git a/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch b/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch new file mode 100644 index 0000000..2f07cc6 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/047-clk-iproc-Add-PLL-base-write-function.patch @@ -0,0 +1,223 @@ +From acbb7a3de7e4d83b23c0bbb3eaf77d15a041d865 Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 15:48:28 -0400 +Subject: [PATCH 47/50] clk: iproc: Add PLL base write function + +All writes to the PLL base address must be flushed if the +IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the +necessary write and reads, we can make sure that any future code which +makes PLL base writes will do the correct thing. + +Signed-off-by: Jon Mason +--- + drivers/clk/bcm/clk-iproc-pll.c | 80 +++++++++++++++++------------------------ + 1 file changed, 33 insertions(+), 47 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct ipro + return -EIO; + } + ++static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, ++ const u32 offset, u32 val) ++{ ++ const struct iproc_pll_ctrl *ctrl = pll->ctrl; ++ ++ writel(val, base + offset); ++ ++ if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && ++ base == pll->pll_base)) ++ val = readl(base + offset); ++} ++ + static void __pll_disable(struct iproc_pll *pll) + { + const struct iproc_pll_ctrl *ctrl = pll->ctrl; +@@ -145,27 +157,24 @@ static void __pll_disable(struct iproc_p + if (ctrl->flags & IPROC_CLK_PLL_ASIU) { + val = readl(pll->asiu_base + ctrl->asiu.offset); + val &= ~(1 << ctrl->asiu.en_shift); +- writel(val, pll->asiu_base + ctrl->asiu.offset); ++ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); + } + + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { + val = readl(pll->pll_base + ctrl->aon.offset); + val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pll_base + ctrl->aon.offset); +- +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { + /* latch input value so core power can be shut down */ + val = readl(pll->pwr_base + ctrl->aon.offset); + val |= (1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + + /* power down the core */ + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + } + } + +@@ -177,10 +186,7 @@ static int __pll_enable(struct iproc_pll + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { + val = readl(pll->pll_base + ctrl->aon.offset); + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- writel(val, pll->pll_base + ctrl->aon.offset); +- +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { +@@ -188,14 +194,14 @@ static int __pll_enable(struct iproc_pll + val = readl(pll->pwr_base + ctrl->aon.offset); + val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; + val &= ~(1 << ctrl->aon.iso_shift); +- writel(val, pll->pwr_base + ctrl->aon.offset); ++ iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); + } + + /* certain PLLs also need to be ungated from the ASIU top level */ + if (ctrl->flags & IPROC_CLK_PLL_ASIU) { + val = readl(pll->asiu_base + ctrl->asiu.offset); + val |= (1 << ctrl->asiu.en_shift); +- writel(val, pll->asiu_base + ctrl->asiu.offset); ++ iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); + } + + return 0; +@@ -209,9 +215,7 @@ static void __pll_put_in_reset(struct ip + + val = readl(pll->pll_base + reset->offset); + val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); +- writel(val, pll->pll_base + reset->offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + reset->offset); ++ iproc_pll_write(pll, pll->pll_base, reset->offset, val); + } + + static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, +@@ -228,9 +232,7 @@ static void __pll_bring_out_reset(struct + val |= ki << reset->ki_shift | kp << reset->kp_shift | + ka << reset->ka_shift; + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; +- writel(val, pll->pll_base + reset->offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + reset->offset); ++ iproc_pll_write(pll, pll->pll_base, reset->offset, val); + } + + static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, +@@ -285,9 +287,8 @@ static int pll_set_rate(struct iproc_clk + /* put PLL in reset */ + __pll_put_in_reset(pll); + +- writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->vco_ctrl.u_offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); ++ + val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); + + if (rate >= VCO_LOW && rate < VCO_MID) +@@ -298,17 +299,13 @@ static int pll_set_rate(struct iproc_clk + else + val |= (1 << PLL_VCO_HIGH_SHIFT); + +- writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->vco_ctrl.l_offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); + + /* program integer part of NDIV */ + val = readl(pll->pll_base + ctrl->ndiv_int.offset); + val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); + val |= vco->ndiv_int << ctrl->ndiv_int.shift; +- writel(val, pll->pll_base + ctrl->ndiv_int.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->ndiv_int.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); + + /* program fractional part of NDIV */ + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { +@@ -316,18 +313,15 @@ static int pll_set_rate(struct iproc_clk + val &= ~(bit_mask(ctrl->ndiv_frac.width) << + ctrl->ndiv_frac.shift); + val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; +- writel(val, pll->pll_base + ctrl->ndiv_frac.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->ndiv_frac.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, ++ val); + } + + /* program PDIV */ + val = readl(pll->pll_base + ctrl->pdiv.offset); + val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); + val |= vco->pdiv << ctrl->pdiv.shift; +- writel(val, pll->pll_base + ctrl->pdiv.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->pdiv.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); + + __pll_bring_out_reset(pll, kp, ka, ki); + +@@ -464,14 +458,12 @@ static int iproc_clk_enable(struct clk_h + /* channel enable is active low */ + val = readl(pll->pll_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.enable_shift); +- writel(val, pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + + /* also make sure channel is not held */ + val = readl(pll->pll_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.hold_shift); +- writel(val, pll->pll_base + ctrl->enable.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + + return 0; + } +@@ -488,9 +480,7 @@ static void iproc_clk_disable(struct clk + + val = readl(pll->pll_base + ctrl->enable.offset); + val |= 1 << ctrl->enable.enable_shift; +- writel(val, pll->pll_base + ctrl->enable.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->enable.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); + } + + static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, +@@ -559,9 +549,7 @@ static int iproc_clk_set_rate(struct clk + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); + val |= div << ctrl->mdiv.shift; + } +- writel(val, pll->pll_base + ctrl->mdiv.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->mdiv.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); + clk->rate = parent_rate / div; + + return 0; +@@ -588,9 +576,7 @@ static void iproc_pll_sw_cfg(struct ipro + + val = readl(pll->pll_base + ctrl->sw_ctrl.offset); + val |= BIT(ctrl->sw_ctrl.shift); +- writel(val, pll->pll_base + ctrl->sw_ctrl.offset); +- if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) +- readl(pll->pll_base + ctrl->sw_ctrl.offset); ++ iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); + } + } + diff --git a/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch b/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch new file mode 100644 index 0000000..528311f --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/048-clk-iproc-Split-off-dig_filter.patch @@ -0,0 +1,158 @@ +From fb9e4932d17ad32786d03cb672fb62f2b337acf5 Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 15:48:29 -0400 +Subject: [PATCH 48/50] clk: iproc: Split off dig_filter + +The PLL loop filter/gain can be located in a separate register on some +SoCs. Split these off into a separate variable, so that an offset can +be added if necessary. Also, make the necessary modifications to the +Cygnus and NSP drivers for this change. + +Signed-off-by: Jon Mason +--- + drivers/clk/bcm/clk-cygnus.c | 17 +++++++++++------ + drivers/clk/bcm/clk-iproc-pll.c | 14 +++++++++----- + drivers/clk/bcm/clk-iproc.h | 10 +++++++++- + drivers/clk/bcm/clk-nsp.c | 14 +++++++++----- + 4 files changed, 38 insertions(+), 17 deletions(-) + +--- a/drivers/clk/bcm/clk-cygnus.c ++++ b/drivers/clk/bcm/clk-cygnus.c +@@ -34,9 +34,11 @@ + { .offset = o, .en_shift = es, .high_shift = hs, \ + .high_width = hw, .low_shift = ls, .low_width = lw } + +-#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ +- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ +- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ ++#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ ++ .p_reset_shift = prs } ++ ++#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ ++ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ + .ka_width = kaw } + + #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } +@@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpl + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | + IPROC_CLK_PLL_NEEDS_SW_CFG, + .aon = AON_VAL(0x0, 2, 1, 0), +- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), ++ .reset = RESET_VAL(0x0, 11, 10), ++ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), + .sw_ctrl = SW_CTRL_VAL(0x10, 31), + .ndiv_int = REG_VAL(0x10, 20, 10), + .ndiv_frac = REG_VAL(0x10, 0, 20), +@@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn + static const struct iproc_pll_ctrl lcpll0 = { + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, + .aon = AON_VAL(0x0, 2, 5, 4), +- .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), ++ .reset = RESET_VAL(0x0, 31, 30), ++ .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4), + .sw_ctrl = SW_CTRL_VAL(0x4, 31), + .ndiv_int = REG_VAL(0x4, 16, 10), + .pdiv = REG_VAL(0x4, 26, 4), +@@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipip + IPROC_CLK_NEEDS_READ_BACK, + .aon = AON_VAL(0x0, 4, 17, 16), + .asiu = ASIU_GATE_VAL(0x0, 3), +- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), ++ .reset = RESET_VAL(0x0, 11, 10), ++ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4), + .ndiv_int = REG_VAL(0x10, 20, 10), + .ndiv_frac = REG_VAL(0x10, 0, 20), + .pdiv = REG_VAL(0x14, 0, 4), +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct + u32 val; + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; ++ const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; ++ ++ val = readl(pll->pll_base + dig_filter->offset); ++ val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | ++ bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | ++ bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); ++ val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | ++ ka << dig_filter->ka_shift; ++ iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val); + + val = readl(pll->pll_base + reset->offset); +- val &= ~(bit_mask(reset->ki_width) << reset->ki_shift | +- bit_mask(reset->kp_width) << reset->kp_shift | +- bit_mask(reset->ka_width) << reset->ka_shift); +- val |= ki << reset->ki_shift | kp << reset->kp_shift | +- ka << reset->ka_shift; + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; + iproc_pll_write(pll, pll->pll_base, reset->offset, val); + } +--- a/drivers/clk/bcm/clk-iproc.h ++++ b/drivers/clk/bcm/clk-iproc.h +@@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl { + }; + + /* +- * Control of the PLL reset, with Ki, Kp, and Ka parameters ++ * Control of the PLL reset + */ + struct iproc_pll_reset_ctrl { + unsigned int offset; + unsigned int reset_shift; + unsigned int p_reset_shift; ++}; ++ ++/* ++ * Control of the Ki, Kp, and Ka parameters ++ */ ++struct iproc_pll_dig_filter_ctrl { ++ unsigned int offset; + unsigned int ki_shift; + unsigned int ki_width; + unsigned int kp_shift; +@@ -129,6 +136,7 @@ struct iproc_pll_ctrl { + struct iproc_pll_aon_pwr_ctrl aon; + struct iproc_asiu_gate asiu; + struct iproc_pll_reset_ctrl reset; ++ struct iproc_pll_dig_filter_ctrl dig_filter; + struct iproc_pll_sw_ctrl sw_ctrl; + struct iproc_clk_reg_op ndiv_int; + struct iproc_clk_reg_op ndiv_frac; +--- a/drivers/clk/bcm/clk-nsp.c ++++ b/drivers/clk/bcm/clk-nsp.c +@@ -26,9 +26,11 @@ + #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ + .pwr_shift = ps, .iso_shift = is } + +-#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ +- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ +- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ ++#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ ++ .p_reset_shift = prs } ++ ++#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ ++ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ + .ka_width = kaw } + + #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ +@@ -43,7 +45,8 @@ CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-arm + static const struct iproc_pll_ctrl genpll = { + .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, + .aon = AON_VAL(0x0, 1, 12, 0), +- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), ++ .reset = RESET_VAL(0x0, 11, 10), ++ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), + .ndiv_int = REG_VAL(0x14, 20, 10), + .ndiv_frac = REG_VAL(0x14, 0, 20), + .pdiv = REG_VAL(0x18, 24, 3), +@@ -99,7 +102,8 @@ CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp + static const struct iproc_pll_ctrl lcpll0 = { + .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, + .aon = AON_VAL(0x0, 1, 24, 0), +- .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4), ++ .reset = RESET_VAL(0x0, 23, 22), ++ .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4), + .ndiv_int = REG_VAL(0x4, 20, 8), + .ndiv_frac = REG_VAL(0x4, 0, 20), + .pdiv = REG_VAL(0x4, 28, 3), diff --git a/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch b/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch new file mode 100644 index 0000000..1e7cbc0 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/049-clk-iproc-Separate-status-and-control-variables.patch @@ -0,0 +1,319 @@ +From eeb32564795a3584dba6281f445ff2aa552be36b Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 15:48:30 -0400 +Subject: [PATCH 49/50] clk: iproc: Separate status and control variables + +Some PLLs have separate registers for Status and Control. The means the +pll_base needs to be split into 2 new variables, so that those PLLs can +specify device tree registers for those independently. Also, add a new +driver flag to identify this presence of the split, and let the driver +know that additional registers need to be used. + +Signed-off-by: Jon Mason +--- + drivers/clk/bcm/clk-iproc-pll.c | 96 ++++++++++++++++++++++++----------------- + drivers/clk/bcm/clk-iproc.h | 6 +++ + 2 files changed, 62 insertions(+), 40 deletions(-) + +--- a/drivers/clk/bcm/clk-iproc-pll.c ++++ b/drivers/clk/bcm/clk-iproc-pll.c +@@ -74,7 +74,8 @@ struct iproc_clk { + }; + + struct iproc_pll { +- void __iomem *pll_base; ++ void __iomem *status_base; ++ void __iomem *control_base; + void __iomem *pwr_base; + void __iomem *asiu_base; + +@@ -127,7 +128,7 @@ static int pll_wait_for_lock(struct ipro + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + + for (i = 0; i < LOCK_DELAY; i++) { +- u32 val = readl(pll->pll_base + ctrl->status.offset); ++ u32 val = readl(pll->status_base + ctrl->status.offset); + + if (val & (1 << ctrl->status.shift)) + return 0; +@@ -145,7 +146,7 @@ static void iproc_pll_write(const struct + writel(val, base + offset); + + if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && +- base == pll->pll_base)) ++ (base == pll->status_base || base == pll->control_base))) + val = readl(base + offset); + } + +@@ -161,9 +162,9 @@ static void __pll_disable(struct iproc_p + } + + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { +- val = readl(pll->pll_base + ctrl->aon.offset); ++ val = readl(pll->control_base + ctrl->aon.offset); + val |= (bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { +@@ -184,9 +185,9 @@ static int __pll_enable(struct iproc_pll + u32 val; + + if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { +- val = readl(pll->pll_base + ctrl->aon.offset); ++ val = readl(pll->control_base + ctrl->aon.offset); + val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); + } + + if (pll->pwr_base) { +@@ -213,9 +214,9 @@ static void __pll_put_in_reset(struct ip + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; + +- val = readl(pll->pll_base + reset->offset); ++ val = readl(pll->control_base + reset->offset); + val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); +- iproc_pll_write(pll, pll->pll_base, reset->offset, val); ++ iproc_pll_write(pll, pll->control_base, reset->offset, val); + } + + static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, +@@ -226,17 +227,17 @@ static void __pll_bring_out_reset(struct + const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; + const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; + +- val = readl(pll->pll_base + dig_filter->offset); ++ val = readl(pll->control_base + dig_filter->offset); + val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | + bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | + bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); + val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | + ka << dig_filter->ka_shift; +- iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val); ++ iproc_pll_write(pll, pll->control_base, dig_filter->offset, val); + +- val = readl(pll->pll_base + reset->offset); ++ val = readl(pll->control_base + reset->offset); + val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; +- iproc_pll_write(pll, pll->pll_base, reset->offset, val); ++ iproc_pll_write(pll, pll->control_base, reset->offset, val); + } + + static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, +@@ -291,9 +292,9 @@ static int pll_set_rate(struct iproc_clk + /* put PLL in reset */ + __pll_put_in_reset(pll); + +- iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); ++ iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0); + +- val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); ++ val = readl(pll->control_base + ctrl->vco_ctrl.l_offset); + + if (rate >= VCO_LOW && rate < VCO_MID) + val |= (1 << PLL_VCO_LOW_SHIFT); +@@ -303,29 +304,29 @@ static int pll_set_rate(struct iproc_clk + else + val |= (1 << PLL_VCO_HIGH_SHIFT); + +- iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val); + + /* program integer part of NDIV */ +- val = readl(pll->pll_base + ctrl->ndiv_int.offset); ++ val = readl(pll->control_base + ctrl->ndiv_int.offset); + val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); + val |= vco->ndiv_int << ctrl->ndiv_int.shift; +- iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val); + + /* program fractional part of NDIV */ + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { +- val = readl(pll->pll_base + ctrl->ndiv_frac.offset); ++ val = readl(pll->control_base + ctrl->ndiv_frac.offset); + val &= ~(bit_mask(ctrl->ndiv_frac.width) << + ctrl->ndiv_frac.shift); + val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; +- iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, ++ iproc_pll_write(pll, pll->control_base, ctrl->ndiv_frac.offset, + val); + } + + /* program PDIV */ +- val = readl(pll->pll_base + ctrl->pdiv.offset); ++ val = readl(pll->control_base + ctrl->pdiv.offset); + val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); + val |= vco->pdiv << ctrl->pdiv.shift; +- iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val); + + __pll_bring_out_reset(pll, kp, ka, ki); + +@@ -372,7 +373,7 @@ static unsigned long iproc_pll_recalc_ra + return 0; + + /* PLL needs to be locked */ +- val = readl(pll->pll_base + ctrl->status.offset); ++ val = readl(pll->status_base + ctrl->status.offset); + if ((val & (1 << ctrl->status.shift)) == 0) { + clk->rate = 0; + return 0; +@@ -383,19 +384,19 @@ static unsigned long iproc_pll_recalc_ra + * + * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv) + */ +- val = readl(pll->pll_base + ctrl->ndiv_int.offset); ++ val = readl(pll->control_base + ctrl->ndiv_int.offset); + ndiv_int = (val >> ctrl->ndiv_int.shift) & + bit_mask(ctrl->ndiv_int.width); + ndiv = ndiv_int << 20; + + if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { +- val = readl(pll->pll_base + ctrl->ndiv_frac.offset); ++ val = readl(pll->control_base + ctrl->ndiv_frac.offset); + ndiv_frac = (val >> ctrl->ndiv_frac.shift) & + bit_mask(ctrl->ndiv_frac.width); + ndiv += ndiv_frac; + } + +- val = readl(pll->pll_base + ctrl->pdiv.offset); ++ val = readl(pll->control_base + ctrl->pdiv.offset); + pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); + + clk->rate = (ndiv * parent_rate) >> 20; +@@ -460,14 +461,14 @@ static int iproc_clk_enable(struct clk_h + u32 val; + + /* channel enable is active low */ +- val = readl(pll->pll_base + ctrl->enable.offset); ++ val = readl(pll->control_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.enable_shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); + + /* also make sure channel is not held */ +- val = readl(pll->pll_base + ctrl->enable.offset); ++ val = readl(pll->control_base + ctrl->enable.offset); + val &= ~(1 << ctrl->enable.hold_shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); + + return 0; + } +@@ -482,9 +483,9 @@ static void iproc_clk_disable(struct clk + if (ctrl->flags & IPROC_CLK_AON) + return; + +- val = readl(pll->pll_base + ctrl->enable.offset); ++ val = readl(pll->control_base + ctrl->enable.offset); + val |= 1 << ctrl->enable.enable_shift; +- iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); + } + + static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, +@@ -499,7 +500,7 @@ static unsigned long iproc_clk_recalc_ra + if (parent_rate == 0) + return 0; + +- val = readl(pll->pll_base + ctrl->mdiv.offset); ++ val = readl(pll->control_base + ctrl->mdiv.offset); + mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); + if (mdiv == 0) + mdiv = 256; +@@ -546,14 +547,14 @@ static int iproc_clk_set_rate(struct clk + if (div > 256) + return -EINVAL; + +- val = readl(pll->pll_base + ctrl->mdiv.offset); ++ val = readl(pll->control_base + ctrl->mdiv.offset); + if (div == 256) { + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); + } else { + val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); + val |= div << ctrl->mdiv.shift; + } +- iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val); + clk->rate = parent_rate / div; + + return 0; +@@ -578,9 +579,10 @@ static void iproc_pll_sw_cfg(struct ipro + if (ctrl->flags & IPROC_CLK_PLL_NEEDS_SW_CFG) { + u32 val; + +- val = readl(pll->pll_base + ctrl->sw_ctrl.offset); ++ val = readl(pll->control_base + ctrl->sw_ctrl.offset); + val |= BIT(ctrl->sw_ctrl.shift); +- iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); ++ iproc_pll_write(pll, pll->control_base, ctrl->sw_ctrl.offset, ++ val); + } + } + +@@ -615,8 +617,8 @@ void __init iproc_pll_clk_setup(struct d + if (WARN_ON(!pll->clks)) + goto err_clks; + +- pll->pll_base = of_iomap(node, 0); +- if (WARN_ON(!pll->pll_base)) ++ pll->control_base = of_iomap(node, 0); ++ if (WARN_ON(!pll->control_base)) + goto err_pll_iomap; + + /* Some SoCs do not require the pwr_base, thus failing is not fatal */ +@@ -629,6 +631,16 @@ void __init iproc_pll_clk_setup(struct d + goto err_asiu_iomap; + } + ++ if (pll_ctrl->flags & IPROC_CLK_PLL_SPLIT_STAT_CTRL) { ++ /* Some SoCs have a split status/control. If this does not ++ * exist, assume they are unified. ++ */ ++ pll->status_base = of_iomap(node, 2); ++ if (!pll->status_base) ++ goto err_status_iomap; ++ } else ++ pll->status_base = pll->control_base; ++ + /* initialize and register the PLL itself */ + pll->ctrl = pll_ctrl; + +@@ -699,6 +711,10 @@ err_clk_register: + clk_unregister(pll->clk_data.clks[i]); + + err_pll_register: ++ if (pll->status_base != pll->control_base) ++ iounmap(pll->status_base); ++ ++err_status_iomap: + if (pll->asiu_base) + iounmap(pll->asiu_base); + +@@ -706,7 +722,7 @@ err_asiu_iomap: + if (pll->pwr_base) + iounmap(pll->pwr_base); + +- iounmap(pll->pll_base); ++ iounmap(pll->control_base); + + err_pll_iomap: + kfree(pll->clks); +--- a/drivers/clk/bcm/clk-iproc.h ++++ b/drivers/clk/bcm/clk-iproc.h +@@ -55,6 +55,12 @@ + #define IPROC_CLK_EMBED_PWRCTRL BIT(5) + + /* ++ * Some PLLs have separate registers for Status and Control. Identify this to ++ * let the driver know if additional registers need to be used ++ */ ++#define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6) ++ ++/* + * Parameters for VCO frequency configuration + * + * VCO frequency = diff --git a/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch b/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch new file mode 100644 index 0000000..a9a5246 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/050-ARM-dts-enable-clock-support-for-BCM5301X.patch @@ -0,0 +1,153 @@ +From e96ef422d0095fe9ae39b03c0805a0db8ff7e382 Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Tue, 13 Oct 2015 17:22:25 -0400 +Subject: [PATCH 50/50] ARM: dts: enable clock support for BCM5301X + +Replace current device tree dummy clocks with real clock support for +Broadcom Northstar SoCs. + +Signed-off-by: Jon Mason +--- + arch/arm/boot/dts/bcm5301x.dtsi | 88 ++++++++++++++++++++++++++++++++--------- + 1 file changed, 69 insertions(+), 19 deletions(-) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -8,6 +8,7 @@ + * Licensed under the GNU/GPL. See COPYING for details. + */ + ++#include + #include + #include + #include +@@ -42,41 +43,48 @@ + + mpcore { + compatible = "simple-bus"; +- ranges = <0x00000000 0x19020000 0x00003000>; ++ ranges = <0x00000000 0x19000000 0x00023000>; + #address-cells = <1>; + #size-cells = <1>; + +- scu@0000 { ++ a9pll: arm_clk@00000 { ++ #clock-cells = <0>; ++ compatible = "brcm,nsp-armpll"; ++ clocks = <&osc>; ++ reg = <0x00000 0x1000>; ++ }; ++ ++ scu@20000 { + compatible = "arm,cortex-a9-scu"; +- reg = <0x0000 0x100>; ++ reg = <0x20000 0x100>; + }; + +- timer@0200 { ++ timer@20200 { + compatible = "arm,cortex-a9-global-timer"; +- reg = <0x0200 0x100>; ++ reg = <0x20200 0x100>; + interrupts = ; +- clocks = <&clk_periph>; ++ clocks = <&periph_clk>; + }; + +- local-timer@0600 { ++ local-timer@20600 { + compatible = "arm,cortex-a9-twd-timer"; +- reg = <0x0600 0x100>; ++ reg = <0x20600 0x100>; + interrupts = ; +- clocks = <&clk_periph>; ++ clocks = <&periph_clk>; + }; + +- gic: interrupt-controller@1000 { ++ gic: interrupt-controller@21000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; +- reg = <0x1000 0x1000>, +- <0x0100 0x100>; ++ reg = <0x21000 0x1000>, ++ <0x20100 0x100>; + }; + +- L2: cache-controller@2000 { ++ L2: cache-controller@22000 { + compatible = "arm,pl310-cache"; +- reg = <0x2000 0x1000>; ++ reg = <0x22000 0x1000>; + cache-unified; + arm,shared-override; + prefetch-data = <1>; +@@ -94,14 +102,37 @@ + + clocks { + #address-cells = <1>; +- #size-cells = <0>; ++ #size-cells = <1>; ++ ranges; + +- /* As long as we do not have a real clock driver us this +- * fixed clock */ +- clk_periph: periph { ++ osc: oscillator { ++ #clock-cells = <0>; + compatible = "fixed-clock"; ++ clock-frequency = <25000000>; ++ }; ++ ++ iprocmed: iprocmed { + #clock-cells = <0>; +- clock-frequency = <400000000>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; ++ clock-div = <2>; ++ clock-mult = <1>; ++ }; ++ ++ iprocslow: iprocslow { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; ++ clock-div = <4>; ++ clock-mult = <1>; ++ }; ++ ++ periph_clk: periph_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&a9pll>; ++ clock-div = <2>; ++ clock-mult = <1>; + }; + }; + +@@ -189,4 +220,23 @@ + + brcm,nand-has-wp; + }; ++ ++ lcpll0: lcpll0@1800c100 { ++ #clock-cells = <1>; ++ compatible = "brcm,nsp-lcpll0"; ++ reg = <0x1800c100 0x14>; ++ clocks = <&osc>; ++ clock-output-names = "lcpll0", "pcie_phy", "sdio", ++ "ddr_phy"; ++ }; ++ ++ genpll: genpll@1800c140 { ++ #clock-cells = <1>; ++ compatible = "brcm,nsp-genpll"; ++ reg = <0x1800c140 0x24>; ++ clocks = <&osc>; ++ clock-output-names = "genpll", "phy", "ethernetclk", ++ "usbclk", "iprocfast", "sata1", ++ "sata2"; ++ }; + }; diff --git a/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch b/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch new file mode 100644 index 0000000..ccb8e27 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/067-ARM-BCM5301X-add-NAND-flash-chip-description-for-Asu.patch @@ -0,0 +1,32 @@ +From af8fe7176ec13de08b1bfb7ea2ae9cc147b2429a Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 12 Sep 2015 12:56:37 +0200 +Subject: [PATCH] ARM: BCM5301X: add NAND flash chip description for Asus + RT-AC87U + +The NAND flash chip description were not imported for the Asus RT-AC87U +dts file when this was done for all the other dts files, because these +patches were send in parallel. + +This adds a missing NAND flash chip description to this patch: +commit 9faa5960eef3204cae6637b530f5e23e53b5a9ef +Author: Hauke Mehrtens +Date: Fri May 29 23:39:47 2015 +0200 + +ARM: BCM5301X: add NAND flash chip description + +Signed-off-by: Hauke Mehrtens +--- + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -10,6 +10,7 @@ + /dts-v1/; + + #include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" + + / { + compatible = "asus,rt-ac87u", "brcm,bcm4709", "brcm,bcm4708"; diff --git a/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch b/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch new file mode 100644 index 0000000..044fb80 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/082-ARM-BCM5301X-Add-DT-for-Netgear-R7000.patch @@ -0,0 +1,128 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 26 Aug 2015 16:11:38 +0200 +Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7000 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm47081-buffalo-wzr-900dhp.dtb \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ ++ bcm4709-netgear-r7000.dtb \ + bcm4709-netgear-r8000.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ + bcm963138dvt.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -0,0 +1,106 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Netgear R7000 ++ * ++ * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" ++ ++/ { ++ compatible = "netgear,r7000", "brcm,bcm4709", "brcm,bcm4708"; ++ model = "Netgear R7000"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ power-white { ++ label = "bcm53xx:white:power"; ++ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ power-amber { ++ label = "bcm53xx:amber:power"; ++ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 5ghz { ++ label = "bcm53xx:white:5ghz"; ++ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 2ghz { ++ label = "bcm53xx:white:2ghz"; ++ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wps { ++ label = "bcm53xx:white:wps"; ++ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wireless { ++ label = "bcm53xx:white:wireless"; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb3 { ++ label = "bcm53xx:white:usb3"; ++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb2 { ++ label = "bcm53xx:white:usb2"; ++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ rfkill { ++ label = "WiFi"; ++ linux,code = ; ++ gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch b/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch new file mode 100644 index 0000000..0dae7c9 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/083-ARM-dts-bcm5301x-Add-BCM-SVK-DT-files.patch @@ -0,0 +1,218 @@ +From a0aef7fbab0d8b5a0d445c74990e5233beda246e Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Wed, 21 Oct 2015 18:46:04 -0400 +Subject: [PATCH] ARM: dts: bcm5301x: Add BCM SVK DT files + +Add device tree files for Broadcom Northstar based SVKs. Since the +bcm5301x.dtsi already exists, all that is necessary is the dts files to +enable the UARTs. With these files, the SVKs are able to boot to shell. + +Signed-off-by: Jon Mason +--- + arch/arm/boot/dts/Makefile | 5 +++- + arch/arm/boot/dts/bcm94708.dts | 56 +++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm94709.dts | 56 +++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/bcm953012k.dts | 63 ++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 179 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/bcm94708.dts + create mode 100644 arch/arm/boot/dts/bcm94709.dts + create mode 100644 arch/arm/boot/dts/bcm953012k.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -73,7 +73,10 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4709-asus-rt-ac87u.dtb \ + bcm4709-buffalo-wxr-1900dhp.dtb \ + bcm4709-netgear-r7000.dtb \ +- bcm4709-netgear-r8000.dtb ++ bcm4709-netgear-r8000.dtb \ ++ bcm94708.dtb \ ++ bcm94709.dtb \ ++ bcm953012k.dtb + dtb-$(CONFIG_ARCH_BCM_63XX) += \ + bcm963138dvt.dtb + dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm94708.dts +@@ -0,0 +1,56 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM94708)"; ++ compatible = "brcm,bcm94708", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm94709.dts +@@ -0,0 +1,56 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM94709)"; ++ compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm953012k.dts +@@ -0,0 +1,63 @@ ++/* ++ * BSD LICENSE ++ * ++ * Copyright(c) 2015 Broadcom Corporation. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Broadcom Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++ ++/ { ++ model = "NorthStar SVK (BCM953012K)"; ++ compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x10000000>; ++ }; ++}; ++ ++&uart0 { ++ clock-frequency = <62499840>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ clock-frequency = <62499840>; ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch b/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch new file mode 100644 index 0000000..8d48673 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/101-use-part-parser.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi ++++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi +@@ -19,6 +19,8 @@ + + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; ++ ++ linux,part-probe = "ofpart", "bcm47xxpart"; + }; + }; + }; diff --git a/target/linux/bcm53xx/patches-4.3/112-bcm53xx-sprom-add-sprom-driver.patch b/target/linux/bcm53xx/patches-4.3/112-bcm53xx-sprom-add-sprom-driver.patch new file mode 100644 index 0000000..70ab039 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/112-bcm53xx-sprom-add-sprom-driver.patch @@ -0,0 +1,69 @@ +From 4e0ab3269a6d260a41a3673157753147f5f71341 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 4 May 2014 13:19:20 +0200 +Subject: [PATCH 03/17] bcm47xx-sprom: add Broadcom sprom parser driver + +This driver needs an nvram driver and fetches the sprom values from the +nvram and provides it to any other driver. The calibration data for the +wifi chip the mac address and some more board description data is +stores in the sprom. + +This is based on a copy of arch/mips/bcm47xx/sprom.c and my plan is to +make the bcm47xx MIPS SoCs also use this driver some time later. + +Signed-off-by: Hauke Mehrtens +--- + .../devicetree/bindings/misc/bcm47xx-sprom.txt | 16 + + drivers/misc/Kconfig | 11 + + drivers/misc/Makefile | 1 + + drivers/misc/bcm47xx-sprom.c | 690 +++++++++++++++++++++ + 4 files changed, 718 insertions(+) + create mode 100644 Documentation/devicetree/bindings/misc/bcm47xx-sprom.txt + create mode 100644 drivers/misc/bcm47xx-sprom.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/misc/bcm47xx-sprom.txt +@@ -0,0 +1,16 @@ ++Broadcom bcm47xx/bcm53xx sprom converter ++ ++This driver provbides an sprom based on a given nvram. ++ ++Required properties: ++ ++- compatible : brcm,bcm47xx-sprom ++ ++- nvram : reference to a nvram driver, e.g. bcm47xx-nvram ++ ++Example: ++ ++sprom0: sprom@0 { ++ compatible = "brcm,bcm47xx-sprom"; ++ nvram = <&nvram0>; ++}; +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -525,6 +525,17 @@ config VEXPRESS_SYSCFG + bus. System Configuration interface is one of the possible means + of generating transactions on this bus. + ++config BCM47XX_SPROM ++ tristate "BCM47XX sprom driver" ++ help ++ This driver parses the sprom from a given nvram which is found on ++ Broadcom bcm47xx and bcm53xx SoCs. ++ ++ The sprom contains board configuration data like the ++ calibration data fro the wifi chips, the mac addresses used ++ by the board and many other board configuration data. This ++ driver will provide the sprom to bcma. ++ + source "drivers/misc/c2port/Kconfig" + source "drivers/misc/eeprom/Kconfig" + source "drivers/misc/cb710/Kconfig" +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -56,3 +56,4 @@ obj-$(CONFIG_GENWQE) += genwqe/ + obj-$(CONFIG_ECHO) += echo/ + obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o + obj-$(CONFIG_CXL_BASE) += cxl/ ++obj-$(CONFIG_BCM47XX_SPROM) += bcm47xx-sprom.o diff --git a/target/linux/bcm53xx/patches-4.3/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch b/target/linux/bcm53xx/patches-4.3/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch new file mode 100644 index 0000000..5e3bd77 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/130-ARM-BCM-Add-SMP-support-for-Broadcom-NSP.patch @@ -0,0 +1,635 @@ +From a0ad1511d5805b95ac4c454d7904c670a1696055 Mon Sep 17 00:00:00 2001 +From: Kapil Hali +Date: Wed, 14 Oct 2015 13:47:00 -0400 +Subject: [PATCH] ARM: BCM: Add SMP support for Broadcom NSP + +Add SMP support for Broadcom's Northstar Plus SoC, +cpu enable method and pen_release procedures. This +changes also consolidates iProc family's - BCM NSP +and BCM Kona, SMP handling in a common file. + +Northstar Plus SoC is based on ARM Cortex-A9 +revision r3p0 which requires configuration for ARM +Errata 764369 for SMP. This change adds the needed +configuration option. + +Signed-off-by: Kapil Hali +--- + arch/arm/mach-bcm/Makefile | 2 +- + arch/arm/mach-bcm/bcm_nsp.h | 19 +++ + arch/arm/mach-bcm/headsmp.S | 37 +++++ + arch/arm/mach-bcm/kona_smp.c | 202 --------------------------- + arch/arm/mach-bcm/platsmp.c | 326 +++++++++++++++++++++++++++++++++++++++++++ + 5 files changed, 383 insertions(+), 203 deletions(-) + create mode 100644 arch/arm/mach-bcm/bcm_nsp.h + create mode 100644 arch/arm/mach-bcm/headsmp.S + delete mode 100644 arch/arm/mach-bcm/kona_smp.c + create mode 100644 arch/arm/mach-bcm/platsmp.c + +--- a/arch/arm/mach-bcm/Makefile ++++ b/arch/arm/mach-bcm/Makefile +@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bc + obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o + + # BCM281XX and BCM21664 SMP support +-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o ++obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o + + # BCM281XX and BCM21664 L2 cache control + obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o +--- /dev/null ++++ b/arch/arm/mach-bcm/bcm_nsp.h +@@ -0,0 +1,19 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __BCM_NSP_H ++#define __BCM_NSP_H ++ ++extern void nsp_secondary_startup(void); ++ ++#endif /* __BCM_NSP_H */ +--- /dev/null ++++ b/arch/arm/mach-bcm/headsmp.S +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2015 Broadcom Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++ ++/* ++ * iProc specific entry point for secondary CPUs. This provides ++ * a "holding pen" into which all secondary cores are held until ++ * we are ready for them to initialise. ++ */ ++ENTRY(nsp_secondary_startup) ++ mrc p15, 0, r0, c0, c0, 5 ++ and r0, r0, #15 ++ adr r4, 1f ++ ldmia r4, {r5, r6} ++ sub r4, r4, r5 ++ add r6, r6, r4 ++pen: ldr r7, [r6] ++ cmp r7, r0 ++ bne pen ++ ++ b secondary_startup ++ ++1: .long . ++ .long pen_release ++ ++ENDPROC(nsp_secondary_startup) +--- a/arch/arm/mach-bcm/kona_smp.c ++++ /dev/null +@@ -1,202 +0,0 @@ +-/* +- * Copyright (C) 2014 Broadcom Corporation +- * Copyright 2014 Linaro Limited +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation version 2. +- * +- * This program is distributed "as is" WITHOUT ANY WARRANTY of any +- * kind, whether express or implied; without even the implied warranty +- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-/* Size of mapped Cortex A9 SCU address space */ +-#define CORTEX_A9_SCU_SIZE 0x58 +- +-#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ +-#define BOOT_ADDR_CPUID_MASK 0x3 +- +-/* Name of device node property defining secondary boot register location */ +-#define OF_SECONDARY_BOOT "secondary-boot-reg" +- +-/* I/O address of register used to coordinate secondary core startup */ +-static u32 secondary_boot; +- +-/* +- * Enable the Cortex A9 Snoop Control Unit +- * +- * By the time this is called we already know there are multiple +- * cores present. We assume we're running on a Cortex A9 processor, +- * so any trouble getting the base address register or getting the +- * SCU base is a problem. +- * +- * Return 0 if successful or an error code otherwise. +- */ +-static int __init scu_a9_enable(void) +-{ +- unsigned long config_base; +- void __iomem *scu_base; +- +- if (!scu_a9_has_base()) { +- pr_err("no configuration base address register!\n"); +- return -ENXIO; +- } +- +- /* Config base address register value is zero for uniprocessor */ +- config_base = scu_a9_get_base(); +- if (!config_base) { +- pr_err("hardware reports only one core\n"); +- return -ENOENT; +- } +- +- scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); +- if (!scu_base) { +- pr_err("failed to remap config base (%lu/%u) for SCU\n", +- config_base, CORTEX_A9_SCU_SIZE); +- return -ENOMEM; +- } +- +- scu_enable(scu_base); +- +- iounmap(scu_base); /* That's the last we'll need of this */ +- +- return 0; +-} +- +-static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) +-{ +- static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; +- struct device_node *node; +- int ret; +- +- BUG_ON(secondary_boot); /* We're called only once */ +- +- /* +- * This function is only called via smp_ops->smp_prepare_cpu(). +- * That only happens if a "/cpus" device tree node exists +- * and has an "enable-method" property that selects the SMP +- * operations defined herein. +- */ +- node = of_find_node_by_path("/cpus"); +- BUG_ON(!node); +- +- /* +- * Our secondary enable method requires a "secondary-boot-reg" +- * property to specify a register address used to request the +- * ROM code boot a secondary code. If we have any trouble +- * getting this we fall back to uniprocessor mode. +- */ +- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) { +- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n", +- node->name); +- ret = -ENOENT; /* Arrange to disable SMP */ +- goto out; +- } +- +- /* +- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is +- * returned, the SoC reported a uniprocessor configuration. +- * We bail on any other error. +- */ +- ret = scu_a9_enable(); +-out: +- of_node_put(node); +- if (ret) { +- /* Update the CPU present map to reflect uniprocessor mode */ +- BUG_ON(ret != -ENOENT); +- pr_warn("disabling SMP\n"); +- init_cpu_present(&only_cpu_0); +- } +-} +- +-/* +- * The ROM code has the secondary cores looping, waiting for an event. +- * When an event occurs each core examines the bottom two bits of the +- * secondary boot register. When a core finds those bits contain its +- * own core id, it performs initialization, including computing its boot +- * address by clearing the boot register value's bottom two bits. The +- * core signals that it is beginning its execution by writing its boot +- * address back to the secondary boot register, and finally jumps to +- * that address. +- * +- * So to start a core executing we need to: +- * - Encode the (hardware) CPU id with the bottom bits of the secondary +- * start address. +- * - Write that value into the secondary boot register. +- * - Generate an event to wake up the secondary CPU(s). +- * - Wait for the secondary boot register to be re-written, which +- * indicates the secondary core has started. +- */ +-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle) +-{ +- void __iomem *boot_reg; +- phys_addr_t boot_func; +- u64 start_clock; +- u32 cpu_id; +- u32 boot_val; +- bool timeout = false; +- +- cpu_id = cpu_logical_map(cpu); +- if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { +- pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); +- return -EINVAL; +- } +- +- if (!secondary_boot) { +- pr_err("required secondary boot register not specified\n"); +- return -EINVAL; +- } +- +- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32)); +- if (!boot_reg) { +- pr_err("unable to map boot register for cpu %u\n", cpu_id); +- return -ENOSYS; +- } +- +- /* +- * Secondary cores will start in secondary_startup(), +- * defined in "arch/arm/kernel/head.S" +- */ +- boot_func = virt_to_phys(secondary_startup); +- BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); +- BUG_ON(boot_func > (phys_addr_t)U32_MAX); +- +- /* The core to start is encoded in the low bits */ +- boot_val = (u32)boot_func | cpu_id; +- writel_relaxed(boot_val, boot_reg); +- +- sev(); +- +- /* The low bits will be cleared once the core has started */ +- start_clock = local_clock(); +- while (!timeout && readl_relaxed(boot_reg) == boot_val) +- timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; +- +- iounmap(boot_reg); +- +- if (!timeout) +- return 0; +- +- pr_err("timeout waiting for cpu %u to start\n", cpu_id); +- +- return -ENOSYS; +-} +- +-static struct smp_operations bcm_smp_ops __initdata = { +- .smp_prepare_cpus = bcm_smp_prepare_cpus, +- .smp_boot_secondary = bcm_boot_secondary, +-}; +-CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", +- &bcm_smp_ops); +--- /dev/null ++++ b/arch/arm/mach-bcm/platsmp.c +@@ -0,0 +1,326 @@ ++/* ++ * Copyright (C) 2014-2015 Broadcom Corporation ++ * Copyright 2014 Linaro Limited ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation version 2. ++ * ++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any ++ * kind, whether express or implied; without even the implied warranty ++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "bcm_nsp.h" ++ ++/* Size of mapped Cortex A9 SCU address space */ ++#define CORTEX_A9_SCU_SIZE 0x58 ++ ++#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ ++#define BOOT_ADDR_CPUID_MASK 0x3 ++ ++/* Name of device node property defining secondary boot register location */ ++#define OF_SECONDARY_BOOT "secondary-boot-reg" ++ ++/* I/O address of register used to coordinate secondary core startup */ ++static u32 secondary_boot; ++ ++static DEFINE_SPINLOCK(boot_lock); ++ ++/* ++ * Write pen_release in a way that is guaranteed to be visible to all ++ * observers, irrespective of whether they're taking part in coherency ++ * or not. This is necessary for the hotplug code to work reliably. ++ */ ++static void write_pen_release(int val) ++{ ++ pen_release = val; ++ /* ++ * Ensure write to pen_release is visible to the other cores, ++ * here - primary core ++ */ ++ smp_wmb(); ++ sync_cache_w(&pen_release); ++} ++ ++/* ++ * Enable the Cortex A9 Snoop Control Unit ++ * ++ * By the time this is called we already know there are multiple ++ * cores present. We assume we're running on a Cortex A9 processor, ++ * so any trouble getting the base address register or getting the ++ * SCU base is a problem. ++ * ++ * Return 0 if successful or an error code otherwise. ++ */ ++static int __init scu_a9_enable(void) ++{ ++ unsigned long config_base; ++ void __iomem *scu_base; ++ ++ if (!scu_a9_has_base()) { ++ pr_err("no configuration base address register!\n"); ++ return -ENXIO; ++ } ++ ++ /* Config base address register value is zero for uniprocessor */ ++ config_base = scu_a9_get_base(); ++ if (!config_base) { ++ pr_err("hardware reports only one core\n"); ++ return -ENOENT; ++ } ++ ++ scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); ++ if (!scu_base) { ++ pr_err("failed to remap config base (%lu/%u) for SCU\n", ++ config_base, CORTEX_A9_SCU_SIZE); ++ return -ENOMEM; ++ } ++ ++ scu_enable(scu_base); ++ ++ iounmap(scu_base); /* That's the last we'll need of this */ ++ ++ return 0; ++} ++ ++static int nsp_write_lut(void (*secondary_startup) (void)) ++{ ++ void __iomem *sku_rom_lut; ++ phys_addr_t secondary_startup_phy; ++ ++ if (!secondary_boot) { ++ pr_warn("required secondary boot register not specified\n"); ++ return -EINVAL; ++ } ++ ++ sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot, ++ sizeof(secondary_boot)); ++ if (!sku_rom_lut) { ++ pr_warn("unable to ioremap SKU-ROM LUT register\n"); ++ return -ENOMEM; ++ } ++ ++ secondary_startup_phy = virt_to_phys(secondary_startup); ++ BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX); ++ ++ writel_relaxed(secondary_startup_phy, sku_rom_lut); ++ /* ++ * Ensure the write is visible to the secondary core. ++ */ ++ smp_wmb(); ++ ++ iounmap(sku_rom_lut); ++ ++ return 0; ++} ++ ++static void nsp_secondary_init(unsigned int cpu) ++{ ++ /* ++ * Let the primary cpu know we are out of holding pen. ++ */ ++ write_pen_release(-1); ++ ++ /* ++ * Synchronise with the boot thread. ++ */ ++ spin_lock(&boot_lock); ++ spin_unlock(&boot_lock); ++} ++ ++static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; ++ struct device_node *node; ++ int ret; ++ ++ BUG_ON(secondary_boot); /* We're called only once */ ++ ++ /* ++ * This function is only called via smp_ops->smp_prepare_cpu(). ++ * That only happens if a "/cpus" device tree node exists ++ * and has an "enable-method" property that selects the SMP ++ * operations defined herein. ++ */ ++ node = of_find_node_by_path("/cpus"); ++ BUG_ON(!node); ++ ++ /* ++ * Our secondary enable method requires a "secondary-boot-reg" ++ * property to specify a register address used to request the ++ * ROM code boot a secondary core. If we have any trouble ++ * getting this we fall back to uniprocessor mode. ++ */ ++ if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) { ++ pr_warn("%s: missing/invalid " OF_SECONDARY_BOOT " property\n", ++ node->name); ++ ret = -ENOENT; /* Arrange to disable SMP */ ++ goto out; ++ } ++ ++ /* ++ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is ++ * returned, the SoC reported a uniprocessor configuration. ++ * We bail on any other error. ++ */ ++ ret = scu_a9_enable(); ++out: ++ of_node_put(node); ++ if (ret) { ++ /* Update the CPU present map to reflect uniprocessor mode */ ++ pr_warn("disabling SMP\n"); ++ init_cpu_present(&only_cpu_0); ++ } ++} ++ ++/* ++ * The ROM code has the secondary cores looping, waiting for an event. ++ * When an event occurs each core examines the bottom two bits of the ++ * secondary boot register. When a core finds those bits contain its ++ * own core id, it performs initialization, including computing its boot ++ * address by clearing the boot register value's bottom two bits. The ++ * core signals that it is beginning its execution by writing its boot ++ * address back to the secondary boot register, and finally jumps to ++ * that address. ++ * ++ * So to start a core executing we need to: ++ * - Encode the (hardware) CPU id with the bottom bits of the secondary ++ * start address. ++ * - Write that value into the secondary boot register. ++ * - Generate an event to wake up the secondary CPU(s). ++ * - Wait for the secondary boot register to be re-written, which ++ * indicates the secondary core has started. ++ */ ++static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ void __iomem *boot_reg; ++ phys_addr_t boot_func; ++ u64 start_clock; ++ u32 cpu_id; ++ u32 boot_val; ++ bool timeout = false; ++ ++ cpu_id = cpu_logical_map(cpu); ++ if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { ++ pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); ++ return -EINVAL; ++ } ++ ++ if (!secondary_boot) { ++ pr_err("required secondary boot register not specified\n"); ++ return -EINVAL; ++ } ++ ++ boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32)); ++ if (!boot_reg) { ++ pr_err("unable to map boot register for cpu %u\n", cpu_id); ++ return -ENOMEM; ++ } ++ ++ /* ++ * Secondary cores will start in secondary_startup(), ++ * defined in "arch/arm/kernel/head.S" ++ */ ++ boot_func = virt_to_phys(secondary_startup); ++ BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); ++ BUG_ON(boot_func > (phys_addr_t)U32_MAX); ++ ++ /* The core to start is encoded in the low bits */ ++ boot_val = (u32)boot_func | cpu_id; ++ writel_relaxed(boot_val, boot_reg); ++ ++ sev(); ++ ++ /* The low bits will be cleared once the core has started */ ++ start_clock = local_clock(); ++ while (!timeout && readl_relaxed(boot_reg) == boot_val) ++ timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; ++ ++ iounmap(boot_reg); ++ ++ if (!timeout) ++ return 0; ++ ++ pr_err("timeout waiting for cpu %u to start\n", cpu_id); ++ ++ return -ENXIO; ++} ++ ++static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ unsigned long timeout; ++ int ret; ++ ++ /* ++ * After wake up, secondary core branches to the startup ++ * address programmed at SKU ROM LUT location. ++ */ ++ ret = nsp_write_lut(nsp_secondary_startup); ++ if (ret) { ++ pr_err("unable to write startup addr to SKU ROM LUT\n"); ++ goto out; ++ } ++ ++ /* ++ * The secondary processor is waiting to be released from ++ * the holding pen - release it, then wait for it to flag ++ * that it has been released by resetting pen_release. ++ */ ++ spin_lock(&boot_lock); ++ ++ write_pen_release(cpu_logical_map(cpu)); ++ /* ++ * Send an Event to wake up the secondary core which is in ++ * WFE state. Updated pen_release should also be visible to ++ * the secondary core. ++ */ ++ dsb_sev(); ++ ++ timeout = jiffies + (1 * HZ); ++ while (time_before(jiffies, timeout)) { ++ /* Make sure loads on other CPU is visible */ ++ smp_rmb(); ++ if (pen_release == -1) ++ break; ++ ++ udelay(10); ++ } ++ ++ spin_unlock(&boot_lock); ++ ++ ret = pen_release != -1 ? -ENXIO : 0; ++ ++out: ++ return ret; ++} ++ ++static struct smp_operations bcm_smp_ops __initdata = { ++ .smp_prepare_cpus = bcm_smp_prepare_cpus, ++ .smp_boot_secondary = kona_boot_secondary, ++}; ++CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", ++ &bcm_smp_ops); ++ ++struct smp_operations nsp_smp_ops __initdata = { ++ .smp_prepare_cpus = bcm_smp_prepare_cpus, ++ .smp_secondary_init = nsp_secondary_init, ++ .smp_boot_secondary = nsp_boot_secondary, ++}; ++CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); diff --git a/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch b/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch new file mode 100644 index 0000000..ad1c771 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/131-ARM-BCM-Add-SMP-support-for-Broadcom-4708.patch @@ -0,0 +1,50 @@ +From ddbf0ad85be06948dd214c7beb7b315ef2749e65 Mon Sep 17 00:00:00 2001 +From: Jon Mason +Date: Thu, 15 Oct 2015 14:14:10 -0400 +Subject: [PATCH] ARM: BCM: Add SMP support for Broadcom 4708 + +ARM: BCM: Add SMP support for Broadcom 4708 + +Add SMP support for Broadcom's 4708 SoCs. + +Signed-off-by: Jon Mason +--- + arch/arm/boot/dts/bcm4708.dtsi | 2 ++ + arch/arm/mach-bcm/Kconfig | 2 ++ + arch/arm/mach-bcm/Makefile | 3 +++ + 3 files changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/bcm4708.dtsi ++++ b/arch/arm/boot/dts/bcm4708.dtsi +@@ -15,6 +15,8 @@ + cpus { + #address-cells = <1>; + #size-cells = <0>; ++ enable-method = "brcm,bcm-nsp-smp"; ++ secondary-boot-reg = <0xffff0400>; + + cpu@0 { + device_type = "cpu"; +--- a/arch/arm/mach-bcm/Kconfig ++++ b/arch/arm/mach-bcm/Kconfig +@@ -38,6 +38,8 @@ config ARCH_BCM_CYGNUS + config ARCH_BCM_5301X + bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 + select ARCH_BCM_IPROC ++ select ARM_ERRATA_764369 if SMP ++ select HAVE_SMP + help + Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores. + +--- a/arch/arm/mach-bcm/Makefile ++++ b/arch/arm/mach-bcm/Makefile +@@ -36,6 +36,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2 + + # BCM5301X + obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o ++ifeq ($(CONFIG_ARCH_BCM_5301X),y) ++obj-$(CONFIG_SMP) += headsmp.o platsmp.o ++endif + + # BCM63XXx + ifeq ($(CONFIG_ARCH_BCM_63XX),y) diff --git a/target/linux/bcm53xx/patches-4.3/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch b/target/linux/bcm53xx/patches-4.3/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch new file mode 100644 index 0000000..c117774 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/132-ARM-BCM5301X-Add-missing-Netgear-R8000-LEDs.patch @@ -0,0 +1,57 @@ +From b58682598541262f967ecd6db04bacac38026d3c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 30 Oct 2015 15:29:52 +0100 +Subject: [PATCH] ARM: BCM5301X: Add missing Netgear R8000 LEDs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 30 +++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +index 446c586..b52927c 100644 +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -50,6 +50,36 @@ + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; ++ ++ wireless { ++ label = "bcm53xx:white:wireless"; ++ gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ wps { ++ label = "bcm53xx:white:wps"; ++ gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ 5ghz-2 { ++ label = "bcm53xx:white:5ghz-2"; ++ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb3 { ++ label = "bcm53xx:white:usb3"; ++ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; ++ ++ usb2 { ++ label = "bcm53xx:white:usb2"; ++ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-off"; ++ }; + }; + + gpio-keys { +-- +1.8.4.5 + diff --git a/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch b/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch new file mode 100644 index 0000000..5031886 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/186-USB-bcma-switch-to-GPIO-descriptor-for-power-control.patch @@ -0,0 +1,75 @@ +From 0cb136f9882e4649ad6160bb7b48955ff728888c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 1 Nov 2015 08:17:21 +0100 +Subject: [PATCH V2] USB: bcma: switch to GPIO descriptor for power control +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +So far we were using simple (legacy) GPIO functions & some poor logic to +control power. It got many drawbacks: we were ignoring OF flags +(GPIO_ACTIVE_LOW), we were not setting direction to output and we were +assuming gpio_request success all the time. +Fix it by switching to gpiod functions and adding appropriate checks. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/usb/host/bcma-hcd.c | 21 ++++++++++----------- + 1 file changed, 10 insertions(+), 11 deletions(-) + +diff --git a/drivers/usb/host/bcma-hcd.c b/drivers/usb/host/bcma-hcd.c +index 5398e3d..291aaa2 100644 +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -21,6 +21,7 @@ + */ + #include + #include ++#include + #include + #include + #include +@@ -36,6 +37,7 @@ MODULE_LICENSE("GPL"); + struct bcma_hcd_device { + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; ++ struct gpio_desc *gpio_desc; + }; + + /* Wait for bitmask in a register to get set or cleared. +@@ -228,19 +230,12 @@ static void bcma_hcd_init_chip_arm(struct bcma_device *dev) + + static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val) + { +- int gpio; ++ struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + +- gpio = of_get_named_gpio(dev->dev.of_node, "vcc-gpio", 0); +- if (!gpio_is_valid(gpio)) ++ if (IS_ERR_OR_NULL(usb_dev->gpio_desc)) + return; + +- if (val) { +- gpio_request(gpio, "bcma-hcd-gpio"); +- gpio_set_value(gpio, 1); +- } else { +- gpio_set_value(gpio, 0); +- gpio_free(gpio); +- } ++ gpiod_set_value(usb_dev->gpio_desc, val); + } + + static const struct usb_ehci_pdata ehci_pdata = { +@@ -314,7 +309,11 @@ static int bcma_hcd_probe(struct bcma_device *dev) + if (!usb_dev) + return -ENOMEM; + +- bcma_hci_platform_power_gpio(dev, true); ++ if (dev->dev.of_node) ++ usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", ++ &dev->dev.of_node->fwnode); ++ if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) ++ gpiod_direction_output(usb_dev->gpio_desc, 1); + + switch (dev->id.id) { + case BCMA_CORE_NS_USB20: diff --git a/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch b/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch new file mode 100644 index 0000000..a769650 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/190-usb-xhci-plat-fix-adding-usb3-lpm-capable-quirk.patch @@ -0,0 +1,63 @@ +From 1420e53fc88673683f8990aa5342e7b2640ce165 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 18 Oct 2015 19:13:27 +0200 +Subject: [PATCH v3 1/6] usb: xhci: plat: fix adding usb3-lpm-capable quirk + +The xhci->quirks member is overwritten in xhci_gen_setup() with the +quirks given through the module load parameter. Without this patch the +usb3-lpm-capable quirk will be over written before it gets used. This +patch moves the quirks code to the xhci_plat_quirks() callback function +which gets called directly after the quirks member variable is +overwritten with the module load parameter. + +I do not have any hardware which is using usb3-lpm-capabls so I can not +test this on real hardware. + +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/xhci-plat.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -37,12 +37,20 @@ static const struct xhci_driver_override + + static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) + { ++ struct platform_device *pdev = to_platform_device(dev); ++ struct device_node *node = pdev->dev.of_node; ++ struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); ++ + /* + * As of now platform drivers don't provide MSI support so we ensure + * here that the generic code does not try to make a pci_dev from our + * dev struct in order to setup MSI + */ + xhci->quirks |= XHCI_PLAT; ++ ++ if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || ++ (pdata && pdata->usb3_lpm_capable)) ++ xhci->quirks |= XHCI_LPM_SUPPORT; + } + + /* called during probe() after chip reset completes */ +@@ -74,8 +82,6 @@ static int xhci_plat_start(struct usb_hc + + static int xhci_plat_probe(struct platform_device *pdev) + { +- struct device_node *node = pdev->dev.of_node; +- struct usb_xhci_pdata *pdata = dev_get_platdata(&pdev->dev); + const struct hc_driver *driver; + struct xhci_hcd *xhci; + struct resource *res; +@@ -148,10 +154,6 @@ static int xhci_plat_probe(struct platfo + goto disable_clk; + } + +- if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || +- (pdata && pdata->usb3_lpm_capable)) +- xhci->quirks |= XHCI_LPM_SUPPORT; +- + if (HCC_MAX_PSA(xhci->hcc_params) >= 4) + xhci->shared_hcd->can_do_streams = 1; + diff --git a/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch b/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch new file mode 100644 index 0000000..ae70f42 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/191-usb-xhci-add-Broadcom-specific-fake-doorbell.patch @@ -0,0 +1,135 @@ +From dd0e5f9a6a4aed849bdb80641c2a2350476cede7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 21 Jun 2015 11:10:49 +0200 +Subject: [PATCH v3 2/6] usb: xhci: add Broadcom specific fake doorbell +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This fixes problem with controller seeing devices only in some small +percentage of cold boots. +This quirk is also added to the platform data so we can activate it +when we register our platform driver. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/xhci-plat.c | 3 +++ + drivers/usb/host/xhci.c | 57 +++++++++++++++++++++++++++++++++++++--- + drivers/usb/host/xhci.h | 1 + + include/linux/usb/xhci_pdriver.h | 1 + + 4 files changed, 59 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -51,6 +51,9 @@ static void xhci_plat_quirks(struct devi + if ((node && of_property_read_bool(node, "usb3-lpm-capable")) || + (pdata && pdata->usb3_lpm_capable)) + xhci->quirks |= XHCI_LPM_SUPPORT; ++ ++ if (pdata && pdata->usb3_fake_doorbell) ++ xhci->quirks |= XHCI_FAKE_DOORBELL; + } + + /* called during probe() after chip reset completes */ +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -121,6 +121,39 @@ int xhci_halt(struct xhci_hcd *xhci) + return ret; + } + ++static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id) ++{ ++ u32 temp; ++ ++ /* alloc a virt device for slot */ ++ if (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) { ++ xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); ++ return -ENOMEM; ++ } ++ ++ /* ring fake doorbell for slot_id ep 0 */ ++ xhci_ring_ep_doorbell(xhci, slot_id, 0, 0); ++ usleep_range(1000, 1500); ++ ++ /* read the status register to check if HSE is set or not? */ ++ temp = readl(&xhci->op_regs->status); ++ ++ /* clear HSE if set */ ++ if (temp & STS_FATAL) { ++ xhci_dbg(xhci, "HSE problem detected, status: 0x%x\n", temp); ++ temp &= ~(0x1fff); ++ temp |= STS_FATAL; ++ writel(temp, &xhci->op_regs->status); ++ usleep_range(1000, 1500); ++ readl(&xhci->op_regs->status); ++ } ++ ++ /* Free virt device */ ++ xhci_free_virt_device(xhci, slot_id); ++ ++ return 0; ++} ++ + /* + * Set the run bit and wait for the host to be running. + */ +@@ -557,10 +590,25 @@ int xhci_init(struct usb_hcd *hcd) + + static int xhci_run_finished(struct xhci_hcd *xhci) + { +- if (xhci_start(xhci)) { +- xhci_halt(xhci); +- return -ENODEV; ++ int err; ++ ++ err = xhci_start(xhci); ++ if (err) { ++ err = -ENODEV; ++ goto out_err; ++ } ++ if (xhci->quirks & XHCI_FAKE_DOORBELL) { ++ err = xhci_fake_doorbell(xhci, 1); ++ if (err) ++ goto out_err; ++ ++ err = xhci_start(xhci); ++ if (err) { ++ err = -ENODEV; ++ goto out_err; ++ } + } ++ + xhci->shared_hcd->state = HC_STATE_RUNNING; + xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; + +@@ -570,6 +618,9 @@ static int xhci_run_finished(struct xhci + xhci_dbg_trace(xhci, trace_xhci_dbg_init, + "Finished xhci_run for USB3 roothub"); + return 0; ++out_err: ++ xhci_halt(xhci); ++ return err; + } + + /* +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1575,6 +1575,7 @@ struct xhci_hcd { + /* For controllers with a broken beyond repair streams implementation */ + #define XHCI_BROKEN_STREAMS (1 << 19) + #define XHCI_PME_STUCK_QUIRK (1 << 20) ++#define XHCI_FAKE_DOORBELL (1 << 21) + unsigned int num_active_eps; + unsigned int limit_active_eps; + /* There are two roothubs to keep track of bus suspend info for */ +--- a/include/linux/usb/xhci_pdriver.h ++++ b/include/linux/usb/xhci_pdriver.h +@@ -22,6 +22,7 @@ + */ + struct usb_xhci_pdata { + unsigned usb3_lpm_capable:1; ++ unsigned usb3_fake_doorbell:1; + }; + + #endif /* __USB_CORE_XHCI_PDRIVER_H */ diff --git a/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch b/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch new file mode 100644 index 0000000..17a9260 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/195-USB-bcma-make-helper-creating-platform-dev-more-gene.patch @@ -0,0 +1,75 @@ +From c7c7bf7fcbacadac7781783de25fe1e13e2a2c35 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 12:33:46 +0200 +Subject: [PATCH v3 3/6] usb: bcma: make helper creating platform dev more + generic +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Having "bool ohci" argument bounded us to two cases only and didn't +allow re-using this code for XHCI. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 24 +++++++++++++----------- + 1 file changed, 13 insertions(+), 11 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -244,7 +244,10 @@ static const struct usb_ehci_pdata ehci_ + static const struct usb_ohci_pdata ohci_pdata = { + }; + +-static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, bool ohci, u32 addr) ++static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, ++ const char *name, u32 addr, ++ const void *data, ++ size_t size) + { + struct platform_device *hci_dev; + struct resource hci_res[2]; +@@ -259,8 +262,7 @@ static struct platform_device *bcma_hcd_ + hci_res[1].start = dev->irq; + hci_res[1].flags = IORESOURCE_IRQ; + +- hci_dev = platform_device_alloc(ohci ? "ohci-platform" : +- "ehci-platform" , 0); ++ hci_dev = platform_device_alloc(name, 0); + if (!hci_dev) + return ERR_PTR(-ENOMEM); + +@@ -271,12 +273,8 @@ static struct platform_device *bcma_hcd_ + ARRAY_SIZE(hci_res)); + if (ret) + goto err_alloc; +- if (ohci) +- ret = platform_device_add_data(hci_dev, &ohci_pdata, +- sizeof(ohci_pdata)); +- else +- ret = platform_device_add_data(hci_dev, &ehci_pdata, +- sizeof(ehci_pdata)); ++ if (data) ++ ret = platform_device_add_data(hci_dev, data, size); + if (ret) + goto err_alloc; + ret = platform_device_add(hci_dev); +@@ -333,11 +331,15 @@ static int bcma_hcd_probe(struct bcma_de + && chipinfo->rev == 0) + ohci_addr = 0x18009000; + +- usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr); ++ usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, "ohci-platform", ++ ohci_addr, &ohci_pdata, ++ sizeof(ohci_pdata)); + if (IS_ERR(usb_dev->ohci_dev)) + return PTR_ERR(usb_dev->ohci_dev); + +- usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr); ++ usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, "ehci-platform", ++ dev->addr, &ehci_pdata, ++ sizeof(ehci_pdata)); + if (IS_ERR(usb_dev->ehci_dev)) { + err = PTR_ERR(usb_dev->ehci_dev); + goto err_unregister_ohci_dev; diff --git a/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch b/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch new file mode 100644 index 0000000..262192b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/196-USB-bcma-use-separated-function-for-USB-2.0-initiali.patch @@ -0,0 +1,112 @@ +From fa5622c2fadae573dd6b0f5bffe436b230b411f6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 12:52:07 +0200 +Subject: [PATCH v3 4/6] usb: bcma: use separated function for USB 2.0 + initialization +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This will allow adding USB 3.0 (XHCI) support cleanly. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 51 +++++++++++++++++++++++++++++++-------------- + 1 file changed, 35 insertions(+), 16 deletions(-) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -35,6 +35,7 @@ MODULE_DESCRIPTION("Common USB driver fo + MODULE_LICENSE("GPL"); + + struct bcma_hcd_device { ++ struct bcma_device *core; + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; + struct gpio_desc *gpio_desc; +@@ -288,31 +289,16 @@ err_alloc: + return ERR_PTR(ret); + } + +-static int bcma_hcd_probe(struct bcma_device *dev) ++static int bcma_hcd_usb20_init(struct bcma_hcd_device *usb_dev) + { +- int err; ++ struct bcma_device *dev = usb_dev->core; ++ struct bcma_chipinfo *chipinfo = &dev->bus->chipinfo; + u32 ohci_addr; +- struct bcma_hcd_device *usb_dev; +- struct bcma_chipinfo *chipinfo; +- +- chipinfo = &dev->bus->chipinfo; +- +- /* TODO: Probably need checks here; is the core connected? */ ++ int err; + + if (dma_set_mask_and_coherent(dev->dma_dev, DMA_BIT_MASK(32))) + return -EOPNOTSUPP; + +- usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), +- GFP_KERNEL); +- if (!usb_dev) +- return -ENOMEM; +- +- if (dev->dev.of_node) +- usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", +- &dev->dev.of_node->fwnode); +- if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) +- gpiod_direction_output(usb_dev->gpio_desc, 1); +- + switch (dev->id.id) { + case BCMA_CORE_NS_USB20: + bcma_hcd_init_chip_arm(dev); +@@ -345,7 +331,6 @@ static int bcma_hcd_probe(struct bcma_de + goto err_unregister_ohci_dev; + } + +- bcma_set_drvdata(dev, usb_dev); + return 0; + + err_unregister_ohci_dev: +@@ -353,6 +338,40 @@ err_unregister_ohci_dev: + return err; + } + ++static int bcma_hcd_probe(struct bcma_device *dev) ++{ ++ int err; ++ struct bcma_hcd_device *usb_dev; ++ ++ /* TODO: Probably need checks here; is the core connected? */ ++ ++ usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device), ++ GFP_KERNEL); ++ if (!usb_dev) ++ return -ENOMEM; ++ usb_dev->core = dev; ++ ++ if (dev->dev.of_node) ++ usb_dev->gpio_desc = devm_get_gpiod_from_child(&dev->dev, "vcc", ++ &dev->dev.of_node->fwnode); ++ if (!IS_ERR_OR_NULL(usb_dev->gpio_desc)) ++ gpiod_direction_output(usb_dev->gpio_desc, 1); ++ ++ switch (dev->id.id) { ++ case BCMA_CORE_USB20_HOST: ++ case BCMA_CORE_NS_USB20: ++ err = bcma_hcd_usb20_init(usb_dev); ++ if (err) ++ return err; ++ break; ++ default: ++ return -ENODEV; ++ } ++ ++ bcma_set_drvdata(dev, usb_dev); ++ return 0; ++} ++ + static void bcma_hcd_remove(struct bcma_device *dev) + { + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); diff --git a/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch b/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch new file mode 100644 index 0000000..34ab858 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/197-USB-bcma-add-USB-3.0-support.patch @@ -0,0 +1,295 @@ +From 121ec6539abedbc0e975cf35f48ee044b323e4c3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 17:14:26 +0200 +Subject: [PATCH v3 5/6] usb: bcma: add USB 3.0 support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Signed-off-by: Hauke Mehrtens +--- + drivers/usb/host/bcma-hcd.c | 225 ++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 225 insertions(+) + +--- a/drivers/usb/host/bcma-hcd.c ++++ b/drivers/usb/host/bcma-hcd.c +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + + MODULE_AUTHOR("Hauke Mehrtens"); + MODULE_DESCRIPTION("Common USB driver for BCMA Bus"); +@@ -38,6 +39,7 @@ struct bcma_hcd_device { + struct bcma_device *core; + struct platform_device *ehci_dev; + struct platform_device *ohci_dev; ++ struct platform_device *xhci_dev; + struct gpio_desc *gpio_desc; + }; + +@@ -245,6 +247,10 @@ static const struct usb_ehci_pdata ehci_ + static const struct usb_ohci_pdata ohci_pdata = { + }; + ++static const struct usb_xhci_pdata xhci_pdata = { ++ .usb3_fake_doorbell = 1 ++}; ++ + static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, + const char *name, u32 addr, + const void *data, +@@ -338,6 +344,216 @@ err_unregister_ohci_dev: + return err; + } + ++static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, ++ u32 value, int timeout) ++{ ++ unsigned long deadline = jiffies + timeout; ++ u32 val; ++ ++ do { ++ val = readl(addr); ++ if ((val & mask) == value) ++ return true; ++ cpu_relax(); ++ udelay(10); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ pr_err("Timeout waiting for register %p\n", addr); ++ ++ return false; ++} ++ ++static void bcma_hcd_usb30_phy_init(struct bcma_hcd_device *bcma_hcd) ++{ ++ struct bcma_device *core = bcma_hcd->core; ++ struct bcma_bus *bus = core->bus; ++ struct bcma_chipinfo *chipinfo = &bus->chipinfo; ++ struct bcma_drv_cc_b *ccb = &bus->drv_cc_b; ++ struct bcma_device *arm_core; ++ void __iomem *dmu = NULL; ++ u32 cru_straps_ctrl; ++ ++ if (chipinfo->id != BCMA_CHIP_ID_BCM4707 && ++ chipinfo->id != BCMA_CHIP_ID_BCM53018) ++ return; ++ ++ arm_core = bcma_find_core(bus, BCMA_CORE_ARMCA9); ++ if (!arm_core) ++ return; ++ ++ dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000); ++ if (!dmu) ++ goto out; ++ ++ /* Check strapping of PCIE/USB3 SEL */ ++ cru_straps_ctrl = ioread32(dmu + 0x2a0); ++ if ((cru_straps_ctrl & 0x10) == 0) ++ goto out; ++ ++ /* Perform USB3 system soft reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); ++ ++ /* Enable MDIO. Setting MDCDIV as 26 */ ++ iowrite32(0x0000009a, ccb->mii + 0x000); ++ udelay(2); ++ ++ switch (chipinfo->id) { ++ case BCMA_CHIP_ID_BCM4707: ++ if (chipinfo->rev == 4) { ++ /* For NS-B0, USB3 PLL Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ /* Clear ana_pllSeqStart */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061000, ccb->mii + 0x004); ++ ++ /* CMOS Divider ratio to 25 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ /* Asserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582ec000, ccb->mii + 0x004); ++ ++ /* Deaaserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582e8000, ccb->mii + 0x004); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ ++ /* Set ana_pllSeqStart */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58069000, ccb->mii + 0x004); ++ ++ /* RXPMD block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8020, ccb->mii + 0x004); ++ ++ /* CDR int loop locking BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58120049, ccb->mii + 0x004); ++ ++ /* CDR int loop acquisition BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580e0049, ccb->mii + 0x004); ++ ++ /* CDR prop loop BW to 1 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a005c, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ } else { ++ /* PLL30 block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e80e0, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a009c, ccb->mii + 0x004); ++ ++ /* Enable SSC */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8040, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580a21d3, ccb->mii + 0x004); ++ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061003, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ } ++ break; ++ case BCMA_CHIP_ID_BCM53018: ++ /* USB3 PLL Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8000, ccb->mii + 0x004); ++ ++ /* Assert Ana_Pllseq start */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061000, ccb->mii + 0x004); ++ ++ /* Assert CML Divider ratio to 26 */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582a6400, ccb->mii + 0x004); ++ ++ /* Asserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582ec000, ccb->mii + 0x004); ++ ++ /* Deaaserting PLL Reset */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x582e8000, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ /* Deasserting USB3 system reset */ ++ bcma_awrite32(core, BCMA_RESET_CTL, 0); ++ ++ /* PLL frequency monitor enable */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58069000, ccb->mii + 0x004); ++ ++ /* PIPE Block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8060, ccb->mii + 0x004); ++ ++ /* CMPMAX & CMPMINTH setting */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580af30d, ccb->mii + 0x004); ++ ++ /* DEGLITCH MIN & MAX setting */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x580e6302, ccb->mii + 0x004); ++ ++ /* TXPMD block */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x587e8040, ccb->mii + 0x004); ++ ++ /* Enabling SSC */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ iowrite32(0x58061003, ccb->mii + 0x004); ++ ++ /* Waiting MII Mgt interface idle */ ++ bcma_wait_reg(bus, ccb->mii + 0x000, 0x0100, 0x0000, 1000); ++ ++ break; ++ } ++out: ++ if (dmu) ++ iounmap(dmu); ++} ++ ++static int bcma_hcd_usb30_init(struct bcma_hcd_device *bcma_hcd) ++{ ++ struct bcma_device *core = bcma_hcd->core; ++ ++ bcma_core_enable(core, 0); ++ ++ bcma_hcd_usb30_phy_init(bcma_hcd); ++ ++ bcma_hcd->xhci_dev = bcma_hcd_create_pdev(core, "xhci-hcd", core->addr, ++ &xhci_pdata, ++ sizeof(xhci_pdata)); ++ if (IS_ERR(bcma_hcd->ohci_dev)) ++ return PTR_ERR(bcma_hcd->ohci_dev); ++ ++ return 0; ++} ++ + static int bcma_hcd_probe(struct bcma_device *dev) + { + int err; +@@ -364,6 +580,11 @@ static int bcma_hcd_probe(struct bcma_de + if (err) + return err; + break; ++ case BCMA_CORE_NS_USB30: ++ err = bcma_hcd_usb30_init(usb_dev); ++ if (err) ++ return err; ++ break; + default: + return -ENODEV; + } +@@ -377,11 +598,14 @@ static void bcma_hcd_remove(struct bcma_ + struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev); + struct platform_device *ohci_dev = usb_dev->ohci_dev; + struct platform_device *ehci_dev = usb_dev->ehci_dev; ++ struct platform_device *xhci_dev = usb_dev->xhci_dev; + + if (ohci_dev) + platform_device_unregister(ohci_dev); + if (ehci_dev) + platform_device_unregister(ehci_dev); ++ if (xhci_dev) ++ platform_device_unregister(xhci_dev); + + bcma_core_disable(dev, 0); + } +@@ -418,6 +642,7 @@ static int bcma_hcd_resume(struct bcma_d + static const struct bcma_device_id bcma_hcd_table[] = { + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS), + BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS), ++ BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB30, BCMA_ANY_REV, BCMA_ANY_CLASS), + {}, + }; + MODULE_DEVICE_TABLE(bcma, bcma_hcd_table); diff --git a/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch b/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch new file mode 100644 index 0000000..06254b3 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch @@ -0,0 +1,86 @@ +From: Florian Fainelli +Subject: [PATCH] ARM: BCM5301x: Disable MMU and Dcache during decompression +Date: Tue, 14 Jul 2015 16:12:08 -0700 + +Use the existing __armv7_mmu_cache_flush() to perform the cache flush +since this does what we are after. + +Signed-off-by: Florian Fainelli +--- + arch/arm/boot/compressed/Makefile | 4 +++ + arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 ++++++++++++++++++++++++ + arch/arm/boot/compressed/head.S | 2 ++ + 3 files changed, 43 insertions(+) + create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S + +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -31,6 +31,10 @@ ifeq ($(CONFIG_ARCH_ACORN),y) + OBJS += ll_char_wr.o font.o + endif + ++ifeq ($(CONFIG_ARCH_BCM_5301X),y) ++OBJS += head-bcm_5301x-mpcore.o ++endif ++ + ifeq ($(CONFIG_ARCH_SA1100),y) + OBJS += head-sa1100.o + endif +--- /dev/null ++++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S +@@ -0,0 +1,37 @@ ++/* ++ * ++ * Platform specific tweaks. This is merged into head.S by the linker. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++ .section ".start", "ax" ++ ++/* ++ * This code section is spliced into the head code by the linker ++ */ ++ ++__plat_uncompress_start: ++ ++ @ Preserve r8/r7 i.e. kernel entry values ++ mov r12, r8 ++ ++ @ Clear MMU enable and Dcache enable bits ++ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR ++ bic r0, #CR_C|CR_M ++ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR ++ nop ++ ++ @ Call the cache invalidation routine ++ bl __armv7_mmu_cache_flush_fn ++ nop ++ mov r0,#0 ++ ldr r3, =0x19022000 @ L2 cache controller, control reg ++ str r0, [r3, #0x100] @ Disable L2 cache ++ nop ++ ++ @ Restore ++ mov r8, r12 +--- a/arch/arm/boot/compressed/head.S ++++ b/arch/arm/boot/compressed/head.S +@@ -1152,6 +1152,7 @@ __armv7_mmu_cache_flush: + hierarchical: + mcr p15, 0, r10, c7, c10, 5 @ DMB + stmfd sp!, {r0-r7, r9-r11} ++ENTRY(__armv7_mmu_cache_flush_fn) + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field +@@ -1201,6 +1202,7 @@ iflush: + mcr p15, 0, r10, c7, c10, 4 @ DSB + mcr p15, 0, r10, c7, c5, 4 @ ISB + mov pc, lr ++ENDPROC(__armv7_mmu_cache_flush_fn) + + __armv5tej_mmu_cache_flush: + tst r4, #1 diff --git a/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch b/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch new file mode 100644 index 0000000..ed6cc73 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/301-ARM-BCM5301X-Add-SPROM.patch @@ -0,0 +1,26 @@ +From d404e0b22356078a51719fa911f6e09cb1a72d80 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 7 Jun 2015 16:18:18 +0200 +Subject: [PATCH] ARM: BCM5301X: Add SPROM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm/boot/dts/bcm5301x.dtsi ++++ b/arch/arm/boot/dts/bcm5301x.dtsi +@@ -136,6 +136,10 @@ + }; + }; + ++ sprom0: sprom@0 { ++ compatible = "brcm,bcm47xx-sprom"; ++ }; ++ + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; diff --git a/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch b/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch new file mode 100644 index 0000000..82ac24e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/305-ARM-BCM5301X-Add-DT-for-Linksys-EA6300-V1.patch @@ -0,0 +1,69 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Subject: [PATCH] ARM: BCM5301X: Add DT for Linksys EA6300 V1 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-asus-rt-ac56u.dtb \ + bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wzr-1750dhp.dtb \ ++ bcm4708-linksys-ea6300-v1.dtb \ + bcm4708-luxul-xwc-1000.dtb \ + bcm4708-netgear-r6250.dtb \ + bcm4708-netgear-r6300-v2.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +@@ -0,0 +1,48 @@ ++/* ++ * Broadcom BCM470X / BCM5301X ARM platform code. ++ * DTS for Linksys EA6300 V1 ++ * ++ * Copyright (C) 2015 RafaÅ‚ MiÅ‚ecki ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++/dts-v1/; ++ ++#include "bcm4708.dtsi" ++#include "bcm5301x-nand-cs0-bch8.dtsi" ++ ++/ { ++ compatible = "linksys,ea6300v1", "brcm,bcm4708"; ++ model = "Linksys EA6300 V1"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ memory { ++ reg = <0x00000000 0x08000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wps { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ++ }; ++ ++ restart { ++ label = "Reset"; ++ linux,code = ; ++ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; diff --git a/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch b/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch new file mode 100644 index 0000000..802188d --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/320-ARM-BCM5301X-Add-Buffalo-WXR-1900DHP-clock-and-USB-p.patch @@ -0,0 +1,41 @@ +From 504dba5b073a9009ae1e3f2fc53ea9c3aa10c38a Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Wed, 13 May 2015 20:56:38 +0200 +Subject: [PATCH] ARM: BCM5301X: Add Buffalo WXR-1900DHP clock and USB power + control +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Felix Fietkau +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -24,6 +24,23 @@ + reg = <0x00000000 0x08000000>; + }; + ++ clocks { ++ clk_periph: periph { ++ clock-frequency = <500000000>; ++ }; ++ }; ++ ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + diff --git a/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch b/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch new file mode 100644 index 0000000..ed4d1bc --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/321-ARM-BCM5301X-Set-vcc-gpio-for-USB-controllers.patch @@ -0,0 +1,86 @@ +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Subject: [PATCH] ARM: BCM5301X: Set vcc-gpio for USB controllers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -24,6 +24,26 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ + spi { + compatible = "spi-gpio"; + num-chipselects = <1>; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -24,6 +24,17 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -24,6 +24,26 @@ + reg = <0x00000000 0x08000000>; + }; + ++ axi@18000000 { ++ usb2@21000 { ++ reg = <0x00021000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ usb3@23000 { ++ reg = <0x00023000 0x1000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + diff --git a/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch b/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch new file mode 100644 index 0000000..4e25647 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/330-ARM-BCM5310X-Enable-earlyprintk-on-tested-devices.patch @@ -0,0 +1,170 @@ +From eb1075cc48d3c315c7403822c33da9588ab76492 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 14 Jan 2015 08:33:25 +0100 +Subject: [PATCH] ARM: BCM5310X: Enable earlyprintk on tested devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 2 +- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 2 +- + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 2 +- + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 2 +- + 4 files changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-1750DHP (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -17,7 +17,7 @@ + model = "Netgear R6250 V1 (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-N18U (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-600DHP2 (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WZR-900DHP (BCM47081)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -17,7 +17,7 @@ + model = "Netgear R8000 (BCM4709)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC56U (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC68U (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts ++++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +@@ -17,7 +17,7 @@ + model = "Luxul XWC-1000 (BCM4708)"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -17,7 +17,7 @@ + model = "Buffalo WXR-1900DHP"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -17,7 +17,7 @@ + model = "SmartRG SR400ac"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -17,7 +17,7 @@ + model = "Asus RT-AC87U"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -17,7 +17,7 @@ + model = "Netgear R7000"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { +--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts ++++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts +@@ -17,7 +17,7 @@ + model = "Linksys EA6300 V1"; + + chosen { +- bootargs = "console=ttyS0,115200"; ++ bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { diff --git a/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch b/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch new file mode 100644 index 0000000..b53c57f --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/331-ARM-BCM5301X-Specify-RAM-on-devices-by-including-HIG.patch @@ -0,0 +1,173 @@ +From 36b2fbb3badf0e32b371e1f7579a95d4fe25c0e1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 14 Jan 2015 09:13:58 +0100 +Subject: [PATCH] ARM: BCM5301X: Specify RAM on devices by including HIGHMEM +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 3 ++- + arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 3 ++- + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 3 ++- + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 3 ++- + arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 3 ++- + 5 files changed, 10 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x18000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + spi { +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + gpio-keys { +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + axi@18000000 { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x18000000>; + }; + + clocks { +--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts ++++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -21,7 +21,8 @@ + }; + + memory { +- reg = <0x00000000 0x08000000>; ++ reg = <0x00000000 0x08000000 ++ 0x88000000 0x08000000>; + }; + + leds { diff --git a/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch b/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch new file mode 100644 index 0000000..f9ca7eb --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/332-ARM-BCM5301X-Add-power-button-for-Buffalo-WZR-1750DHP.patch @@ -0,0 +1,20 @@ +From: Felix Fietkau +Subject: [PATCH] ARM: BCM5301X: Add power button for Buffalo WZR-1750DHP + +Signed-off-by: Felix Fietkau +--- +--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts ++++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +@@ -123,6 +123,12 @@ + #address-cells = <1>; + #size-cells = <0>; + ++ power { ++ label = "Power"; ++ linux,code = ; ++ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; ++ }; ++ + restart { + label = "Reset"; + linux,code = ; diff --git a/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch b/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch new file mode 100644 index 0000000..dad4f8a --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/351-ARM-BCM5301X-Enable-ChipCommon-UART-on-untested-devi.patch @@ -0,0 +1,111 @@ +From b49d7bb4825654f81bcee8e219028712811515a5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 29 Jun 2015 08:11:36 +0200 +Subject: [PATCH] ARM: BCM5301X: Enable ChipCommon UART on untested devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 4 ++++ + arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 4 ++++ + arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 4 ++++ + arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 4 ++++ + arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 4 ++++ + arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 5 +++++ + arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 5 +++++ + arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 5 +++++ + 8 files changed, 35 insertions(+) + +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +@@ -96,3 +96,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts ++++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +@@ -83,3 +83,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts ++++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +@@ -83,3 +83,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts ++++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +@@ -77,3 +77,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts ++++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +@@ -37,3 +37,7 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++}; +--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts ++++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +@@ -65,3 +65,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts ++++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +@@ -144,3 +144,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +@@ -127,3 +127,8 @@ + }; + }; + }; ++ ++&uart0 { ++ status = "okay"; ++ clock-frequency = <125000000>; ++}; +--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts ++++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +@@ -104,4 +104,5 @@ + + &uart0 { + status = "okay"; ++ clock-frequency = <125000000>; + }; diff --git a/target/linux/bcm53xx/patches-4.3/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch b/target/linux/bcm53xx/patches-4.3/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch new file mode 100644 index 0000000..ccdb28b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/400-mtd-bcm47xxpart-scan-whole-flash-on-ARCH_BCM_5301X.patch @@ -0,0 +1,31 @@ +From d658c21d6697293a928434fd6ac19264b5a8948d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 30 Jan 2015 08:25:54 +0100 +Subject: [PATCH] mtd: bcm47xxpart: scan whole flash on ARCH_BCM_5301X +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/mtd/bcm47xxpart.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -120,9 +120,15 @@ static int bcm47xxpart_parse(struct mtd_ + /* Parse block by block looking for magics */ + for (offset = 0; offset <= master->size - blocksize; + offset += blocksize) { ++#ifndef CONFIG_ARCH_BCM_5301X ++ /* ++ * ARM routers may have partitions in higher memory. E.g. ++ * Netgear R8000 has board_data at 0x2600000. ++ */ + /* Nothing more in higher memory */ + if (offset >= 0x2000000) + break; ++#endif + + if (curr_part >= BCM47XXPART_MAX_PARTS) { + pr_warn("Reached maximum number of partitions, scanning stopped!\n"); diff --git a/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch b/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch new file mode 100644 index 0000000..79af785 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/404-mtd-bcm53xxspiflash-new-driver-for-SPI-flahes-on-Bro.patch @@ -0,0 +1,20 @@ +--- a/drivers/mtd/spi-nor/Kconfig ++++ b/drivers/mtd/spi-nor/Kconfig +@@ -40,4 +40,10 @@ config SPI_NXP_SPIFI + Flash. Enable this option if you have a device with a SPIFI + controller and want to access the Flash as a mtd device. + ++config MTD_SPI_BCM53XXSPIFLASH ++ tristate "SPI-NOR flashes connected to the Broadcom ARM SoC" ++ depends on MTD_SPI_NOR ++ help ++ SPI driver for flashes used on Broadcom ARM SoCs. ++ + endif # MTD_SPI_NOR +--- a/drivers/mtd/spi-nor/Makefile ++++ b/drivers/mtd/spi-nor/Makefile +@@ -1,3 +1,4 @@ + obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o + obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o ++obj-$(CONFIG_MTD_SPI_BCM53XXSPIFLASH) += bcm53xxspiflash.o + obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o diff --git a/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch b/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch new file mode 100644 index 0000000..a3d0f75 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch @@ -0,0 +1,59 @@ +From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 16 Oct 2014 20:52:16 +0200 +Subject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/mtd/ubi/attach.c | 5 +++++ + drivers/mtd/ubi/io.c | 4 ++++ + drivers/mtd/ubi/ubi.h | 1 + + 3 files changed, 10 insertions(+) + +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -95,6 +95,9 @@ static int self_check_ai(struct ubi_devi + static struct ubi_ec_hdr *ech; + static struct ubi_vid_hdr *vidh; + ++/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */ ++bool erase_all_next; ++ + /** + * add_to_list - add physical eraseblock to a list. + * @ai: attaching information +@@ -1427,6 +1430,8 @@ int ubi_attach(struct ubi_device *ubi, i + if (!ai) + return -ENOMEM; + ++ erase_all_next = false; ++ + #ifdef CONFIG_MTD_UBI_FASTMAP + /* On small flash devices we disable fastmap in any case. */ + if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) { +--- a/drivers/mtd/ubi/io.c ++++ b/drivers/mtd/ubi/io.c +@@ -755,6 +755,10 @@ int ubi_io_read_ec_hdr(struct ubi_device + } + + magic = be32_to_cpu(ec_hdr->magic); ++ if (magic == 0xdeadc0de) ++ erase_all_next = true; ++ if (erase_all_next) ++ return read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF; + if (magic != UBI_EC_HDR_MAGIC) { + if (mtd_is_eccerr(read_err)) + return UBI_IO_BAD_HDR_EBADMSG; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -781,6 +781,7 @@ extern struct mutex ubi_devices_mutex; + extern struct blocking_notifier_head ubi_notifiers; + + /* attach.c */ ++extern bool erase_all_next; + int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum, + int ec, const struct ubi_vid_hdr *vid_hdr, int bitflips); + struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai, diff --git a/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch b/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch new file mode 100644 index 0000000..dfc422e --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/710-b53-add-hacky-CPU-port-fixes-for-devices-not-using-p.patch @@ -0,0 +1,42 @@ +From 4abdde3ad6bc0b3b157c4bf6ec0bf139d11d07e8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 13 May 2015 14:13:28 +0200 +Subject: [PATCH] b53: add hacky CPU port fixes for devices not using port 5 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/net/phy/b53/b53_common.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/phy/b53/b53_common.c ++++ b/drivers/net/phy/b53/b53_common.c +@@ -25,6 +25,7 @@ + #include + #include + #include ++#include + + #include "b53_regs.h" + #include "b53_priv.h" +@@ -1313,6 +1314,18 @@ static int b53_switch_init(struct b53_de + sw_dev->cpu_port = 5; + } + ++ if (of_machine_is_compatible("asus,rt-ac87u")) ++ sw_dev->cpu_port = 7; ++ else if (of_machine_is_compatible("netgear,r8000")) ++ sw_dev->cpu_port = 8; ++ ++ /* ++ * Workaround for devices using port 8 (connected to the 3rd iface). ++ * For some reason it doesn't work (no packets on eth2). ++ */ ++ if (of_machine_is_compatible("netgear,r8000")) ++ sw_dev->cpu_port = 5; ++ + /* cpu port is always last */ + sw_dev->ports = sw_dev->cpu_port + 1; + dev->enabled_ports |= BIT(sw_dev->cpu_port); diff --git a/target/linux/bcm53xx/patches-4.3/800-bcma-use-two-different-initcalls-if-built-in.patch b/target/linux/bcm53xx/patches-4.3/800-bcma-use-two-different-initcalls-if-built-in.patch new file mode 100644 index 0000000..4e5793b --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/800-bcma-use-two-different-initcalls-if-built-in.patch @@ -0,0 +1,65 @@ +From 666bdfc027cde41a171862dc698987a378c8b66a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Mon, 9 Feb 2015 18:00:42 +0100 +Subject: [PATCH RFC] bcma: use two different initcalls if built-in +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is needed as we can't initialize bus during fs_initcall. +Initialization requires SPROM which depends on NVRAM which depends on +mtd. Since mtd, spi, nand, spi-nor use standard module_init, we have to +do the same in bcma. +Without this we'll try to initialize SPROM without having a ready SPROM +proviver registered using bcma_arch_register_fallback_sprom. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- +While this patch seems to work and I can compile bcma as built-in and +module, I'm not too proud of it. I don't really like these #if(n)def +tricks and I'm afraid bcma_modinit may be called even if +bcma_modinit_early failed. + +Do you see any better idea of solving this? +--- + drivers/bcma/main.c | 16 ++++++++++++++-- + 1 file changed, 14 insertions(+), 2 deletions(-) + +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -673,13 +673,25 @@ static int bcma_device_uevent(struct dev + core->id.rev, core->id.class); + } + ++/* Bus has to be registered early, before any bcma driver */ ++static int __init bcma_modinit_early(void) ++{ ++ return bus_register(&bcma_bus_type); ++} ++#ifndef MODULE ++fs_initcall(bcma_modinit_early); ++#endif ++ ++/* Initialization has to be done later with SPI/mtd/NAND/SPROM available */ + static int __init bcma_modinit(void) + { + int err; + +- err = bus_register(&bcma_bus_type); ++#ifdef MODULE ++ err = bcma_modinit_early(); + if (err) + return err; ++#endif + + err = bcma_host_soc_register_driver(); + if (err) { +@@ -696,7 +708,7 @@ static int __init bcma_modinit(void) + + return err; + } +-fs_initcall(bcma_modinit); ++module_init(bcma_modinit); + + static void __exit bcma_modexit(void) + { diff --git a/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch b/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch new file mode 100644 index 0000000..c1dfa92 --- /dev/null +++ b/target/linux/bcm53xx/patches-4.3/901-mtd-bcm47xxpart-workaround-for-Asus-RT-AC87U-asus-pa.patch @@ -0,0 +1,42 @@ +From 21500872c1dba33848ddcf6bea97d58772675d36 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 17 May 2015 14:00:52 +0200 +Subject: [PATCH] mtd: bcm47xxpart: workaround for Asus RT-AC87U "asus" + partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/mtd/bcm47xxpart.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + + #include + +@@ -135,6 +136,17 @@ static int bcm47xxpart_parse(struct mtd_ + break; + } + ++ /* ++ * Ugly workaround for Asus RT-AC87U and its "asus" partition. ++ * It uses JFFS2 which we don't (want to) detect. We should ++ * probably use DT to define partitions but we need a working ++ * TRX firmware splitter first. ++ */ ++ if (of_machine_is_compatible("asus,rt-ac87u") && offset == 0x7ec0000) { ++ bcm47xxpart_add_part(&parts[curr_part++], "asus", offset, MTD_WRITEABLE); ++ continue; ++ } ++ + /* Read beginning of the block */ + if (mtd_read(master, offset, BCM47XXPART_BYTES_TO_READ, + &bytes_read, (uint8_t *)buf) < 0) { diff --git a/target/linux/bcm53xx/profiles/100-Generic.mk b/target/linux/bcm53xx/profiles/100-Generic.mk new file mode 100644 index 0000000..d7e9005 --- /dev/null +++ b/target/linux/bcm53xx/profiles/100-Generic.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Generic + NAME:=Broadcom SoC, BCM43xx WiFi (b43, brcmfmac, default) + PACKAGES:=kmod-b43 kmod-brcmfmac +endef + +define Profile/Generic/Description + Package set compatible with hardware any Broadcom BCM47xx or BCM535x + SoC with a ARM CPU like the BCM4707, BCM4708, BCM4709, BCM53010 +endef + +$(eval $(call Profile,Generic)) + diff --git a/target/linux/brcm2708/Makefile b/target/linux/brcm2708/Makefile new file mode 100644 index 0000000..f8c9347 --- /dev/null +++ b/target/linux/brcm2708/Makefile @@ -0,0 +1,31 @@ +# +# Copyright (C) 2012-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/host.mk + +ARCH:=arm +BOARD:=brcm2708 +BOARDNAME:=Broadcom BCM2708/BCM2709 +FEATURES:=ext4 audio usb usbgadget display gpio +MAINTAINER:=Florian Fainelli +CPU_TYPE:=arm1176jzf-s +CPU_SUBTYPE:=vfp +SUBTARGETS:=bcm2708 bcm2709 + +KERNEL_PATCHVER:=4.1 + +include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += brcm2708-gpu-fw kmod-usb-hid kmod-sound-core kmod-sound-arm-bcm2835 kmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 + +define Target/Description + Build firmware image for Broadcom BCM2708/BCM2709 SoC devices. + Currently produces SD Card image for Raspberry Pi. +endef + +KERNELNAME:=Image dtbs + +$(eval $(call BuildTarget)) diff --git a/target/linux/brcm2708/base-files/etc/diag.sh b/target/linux/brcm2708/base-files/etc/diag.sh new file mode 100644 index 0000000..55e68b1 --- /dev/null +++ b/target/linux/brcm2708/base-files/etc/diag.sh @@ -0,0 +1,25 @@ +#!/bin/sh +# +# Copyright (C) 2015 OpenWrt.org +# + +. /lib/functions/leds.sh + +set_state() { + status_led="led0" + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/brcm2708/base-files/etc/inittab b/target/linux/brcm2708/base-files/etc/inittab new file mode 100644 index 0000000..c05c555 --- /dev/null +++ b/target/linux/brcm2708/base-files/etc/inittab @@ -0,0 +1,4 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttyAMA0::askfirst:/bin/ash --login +tty1::askfirst:/bin/ash --login diff --git a/target/linux/brcm2708/base-files/etc/uci-defaults/02_network b/target/linux/brcm2708/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..e7e35c5 --- /dev/null +++ b/target/linux/brcm2708/base-files/etc/uci-defaults/02_network @@ -0,0 +1,15 @@ +#!/bin/sh +# Copyright (C) 2014 OpenWrt.org + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh + +ucidef_set_interface_loopback +ucidef_set_interface_lan "eth0" + +uci commit network + +exit 0 diff --git a/target/linux/brcm2708/base-files/lib/preinit/79_move_config b/target/linux/brcm2708/base-files/lib/preinit/79_move_config new file mode 100644 index 0000000..b0ee62a --- /dev/null +++ b/target/linux/brcm2708/base-files/lib/preinit/79_move_config @@ -0,0 +1,18 @@ +#!/bin/sh +# Copyright (C) 2015 OpenWrt.org + +BOOTPART=/dev/mmcblk0p1 + +move_config() { + if [ -b $BOOTPART ]; then + insmod nls_cp437 + insmod nls_iso8859-1 + insmod fat + insmod vfat + mkdir -p /boot + mount -t vfat -o rw,noatime $BOOTPART /boot + [ -f /boot/sysupgrade.tgz ] && mv -f /boot/sysupgrade.tgz / + fi +} + +boot_hook_add preinit_mount_root move_config diff --git a/target/linux/brcm2708/base-files/lib/upgrade/platform.sh b/target/linux/brcm2708/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..1d4b694 --- /dev/null +++ b/target/linux/brcm2708/base-files/lib/upgrade/platform.sh @@ -0,0 +1,18 @@ +platform_check_image() { + # i know no way to verify the image + return 0; +} + +platform_do_upgrade() { + sync + get_image "$1" | dd of=/dev/mmcblk0 bs=2M conv=fsync + sleep 1 +} + +platform_copy_config() { + mkdir -p /boot + [ -f /boot/kernel.img ] || mount -t vfat -o rw,noatime /dev/mmcblk0p1 /boot + cp -af "$CONF_TAR" /boot/ + sync + umount /boot +} diff --git a/target/linux/brcm2708/bcm2708/config-4.1 b/target/linux/brcm2708/bcm2708/config-4.1 new file mode 100644 index 0000000..055caa9 --- /dev/null +++ b/target/linux/brcm2708/bcm2708/config-4.1 @@ -0,0 +1,353 @@ +# CONFIG_AIO is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_AMBA_PL08X is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_BCM2708=y +# CONFIG_ARCH_BCM2709 is not set +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +# CONFIG_ARM_CPUIDLE is not set +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_411920=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_UNWIND=y +CONFIG_AVERAGE=y +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BCM2708_DT=y +CONFIG_BCM2708_GPIO=y +# CONFIG_BCM2708_NOL2CACHE is not set +CONFIG_BCM2708_VCHIQ=y +CONFIG_BCM2708_VCMEM=y +# CONFIG_BCM2708_WDT is not set +# CONFIG_BCM2835_DEVGPIOMEM is not set +CONFIG_BCM2835_MBOX=y +# CONFIG_BCM2835_SMI is not set +CONFIG_BCM2835_WDT=y +CONFIG_BCM_VCIO=y +CONFIG_BCM_VC_CMA=y +CONFIG_BCM_VC_SM=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_SD=y +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BUILD_BIN2C=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +CONFIG_COMMON_CLK=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_PM=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_V6=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_DEVTMPFS=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2708=y +CONFIG_DMA_BCM2708_LEGACY=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FB=y +CONFIG_FB_BCM2708=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +# CONFIG_FB_RPISENSE is not set +CONFIG_FIQ=y +CONFIG_FIRMWARE_IN_KERNEL=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FPE_FASTFPE is not set +# CONFIG_FPE_NWFPE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FREEZER=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_CONSOLE=y +CONFIG_HZ_FIXED=0 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INPUT=y +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_IOMMU_HELPER=y +CONFIG_IOSCHED_CFQ=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_TRIGGER_INPUT is not set +CONFIG_LIBFDT=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_MACH_BCM2708=y +CONFIG_MAC_PARTITION=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAILBOX=y +CONFIG_MAX_RAW_DEVS=256 +CONFIG_MEMORY_ISOLATION=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BCM2835=y +CONFIG_MMC_BCM2835_DMA=y +CONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2 +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_MACH_IO_H=y +CONFIG_NEED_MACH_MEMORY_H=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NLS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_OABI_COMPAT=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYS_OFFSET=0 +CONFIG_PINCTRL=y +CONFIG_PINCTRL_BCM2835=y +# CONFIG_PL330_DMA is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_POWER_SUPPLY=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_RAW_DRIVER=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +CONFIG_SCSI=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_PROC_FS is not set +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SQUASHFS is not set +CONFIG_SRCU=y +# CONFIG_STAGING is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_TEXTSEARCH is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_BCM2835=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_UID16 is not set +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWCOTG=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_UAS=y +CONFIG_USB_USBNET=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/brcm2708/bcm2708/profiles/RaspberryPi.mk b/target/linux/brcm2708/bcm2708/profiles/RaspberryPi.mk new file mode 100644 index 0000000..dcf6e05 --- /dev/null +++ b/target/linux/brcm2708/bcm2708/profiles/RaspberryPi.mk @@ -0,0 +1,38 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Raspberry Pi +endef +define Profile/Default/Description + Raspberry Pi +endef +$(eval $(call Profile,Default)) + +define Profile/RaspberryPi_B + NAME:=Raspberry Pi Model B +endef +define Profile/RaspberryPi_B/Description + Raspberry Pi Model B +endef +$(eval $(call Profile,RaspberryPi_B)) + +define Profile/RaspberryPi_BPlus + NAME:=Raspberry Pi Model B+ +endef +define Profile/RaspberryPi_BPlus/Description + Raspberry Pi Model B+ +endef +$(eval $(call Profile,RaspberryPi_BPlus)) + +define Profile/RaspberryPi_CM + NAME:=Raspberry Pi Compute Module +endef +define Profile/RaspberryPi_CM/Description + Raspberry Pi Model Compute Module +endef +$(eval $(call Profile,RaspberryPi_CM)) diff --git a/target/linux/brcm2708/bcm2708/target.mk b/target/linux/brcm2708/bcm2708/target.mk new file mode 100644 index 0000000..10fae2f --- /dev/null +++ b/target/linux/brcm2708/bcm2708/target.mk @@ -0,0 +1,10 @@ +# +# Copyright (C) 2015 OpenWrt.org +# + +SUBTARGET:=bcm2708 +BOARDNAME:=BCM2708 based boards + +define Target/Description + Build firmware image for Broadcom BCM2708 SoC devices. +endef diff --git a/target/linux/brcm2708/bcm2709/config-4.1 b/target/linux/brcm2708/bcm2709/config-4.1 new file mode 100644 index 0000000..8eb98af --- /dev/null +++ b/target/linux/brcm2708/bcm2709/config-4.1 @@ -0,0 +1,384 @@ +# CONFIG_AIO is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_AMBA_PL08X is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_ARCH_BCM2708 is not set +CONFIG_ARCH_BCM2709=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_BARRIERS=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_CPUIDLE is not set +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AVERAGE=y +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BCM2708_GPIO=y +CONFIG_BCM2708_NOL2CACHE=y +CONFIG_BCM2708_VCHIQ=y +CONFIG_BCM2708_VCMEM=y +# CONFIG_BCM2708_WDT is not set +CONFIG_BCM2709_DT=y +# CONFIG_BCM2835_DEVGPIOMEM is not set +CONFIG_BCM2835_MBOX=y +# CONFIG_BCM2835_SMI is not set +CONFIG_BCM2835_WDT=y +CONFIG_BCM_VCIO=y +CONFIG_BCM_VC_CMA=y +CONFIG_BCM_VC_SM=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_SD=y +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BUILD_BIN2C=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=16 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +CONFIG_COMMON_CLK=y +CONFIG_CONFIGFS_FS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_DEVTMPFS=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2708=y +CONFIG_DMA_BCM2708_LEGACY=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FB=y +CONFIG_FB_BCM2708=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +# CONFIG_FB_RPISENSE is not set +CONFIG_FIQ=y +CONFIG_FIRMWARE_IN_KERNEL=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FPE_FASTFPE is not set +# CONFIG_FPE_NWFPE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FREEZER=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HW_CONSOLE=y +CONFIG_HZ_FIXED=0 +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INPUT=y +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_IOMMU_HELPER=y +CONFIG_IOSCHED_CFQ=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_TRIGGER_INPUT is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_MACH_BCM2709=y +CONFIG_MAC_PARTITION=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAILBOX=y +CONFIG_MAX_RAW_DEVS=256 +CONFIG_MEMORY_ISOLATION=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BCM2835=y +CONFIG_MMC_BCM2835_DMA=y +CONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2 +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_MACH_IO_H=y +CONFIG_NEED_MACH_MEMORY_H=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OABI_COMPAT=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0x80000000 +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYS_OFFSET=0 +CONFIG_PINCTRL=y +CONFIG_PINCTRL_BCM2835=y +# CONFIG_PL330_DMA is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_SUPPLY=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_RAW_DRIVER=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +CONFIG_SCSI=y +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_PROC_FS is not set +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +# CONFIG_SQUASHFS is not set +CONFIG_SRCU=y +# CONFIG_STAGING is not set +CONFIG_STOP_MACHINE=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_TEXTSEARCH is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_BCM2835=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_OF=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TREE_RCU=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_UID16 is not set +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWCOTG=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_UAS=y +CONFIG_USB_USBNET=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/brcm2708/bcm2709/profiles/RaspberryPi2.mk b/target/linux/brcm2708/bcm2709/profiles/RaspberryPi2.mk new file mode 100644 index 0000000..ef7483d --- /dev/null +++ b/target/linux/brcm2708/bcm2709/profiles/RaspberryPi2.mk @@ -0,0 +1,14 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RaspberryPi_2 + NAME:=Raspberry Pi 2 Model B +endef +define Profile/RaspberryPi_2/Description + Raspberry Pi 2 Model B +endef +$(eval $(call Profile,RaspberryPi_2)) diff --git a/target/linux/brcm2708/bcm2709/target.mk b/target/linux/brcm2708/bcm2709/target.mk new file mode 100644 index 0000000..565c12a --- /dev/null +++ b/target/linux/brcm2708/bcm2709/target.mk @@ -0,0 +1,12 @@ +# +# Copyright (C) 2015 OpenWrt.org +# + +SUBTARGET:=bcm2709 +BOARDNAME:=BCM2709 based boards +CPU_TYPE:=cortex-a7 +CPU_SUBTYPE:=vfp + +define Target/Description + Build firmware image for Broadcom BCM2709 SoC devices. +endef diff --git a/target/linux/brcm2708/image/Config.in b/target/linux/brcm2708/image/Config.in new file mode 100644 index 0000000..f7abd9d --- /dev/null +++ b/target/linux/brcm2708/image/Config.in @@ -0,0 +1,5 @@ +config BRCM2708_SD_BOOT_PARTSIZE + int "Boot (SD Card) filesystem partition size (in MB)" + depends on TARGET_brcm2708 + default 20 + diff --git a/target/linux/brcm2708/image/Makefile b/target/linux/brcm2708/image/Makefile new file mode 100644 index 0000000..cf263bd --- /dev/null +++ b/target/linux/brcm2708/image/Makefile @@ -0,0 +1,94 @@ +# +# Copyright (C) 2012-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk +include $(INCLUDE_DIR)/host.mk + +FAT32_BLOCK_SIZE=1024 +FAT32_BLOCKS=$(shell echo $$(($(CONFIG_BRCM2708_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE)))) + +ifneq ($(CONFIG_TARGET_IMAGES_GZIP),) + define Image/gzip + gzip -9n -c $(1) > $(1).gz + mv $(1).gz $(BIN_DIR) + endef +else + define Image/gzip + endef +endif + +### Image scripts ### +define Build/gen-cfg + cat config.txt > $@.config + echo -e "\ndevice_tree=$(DEVICE_DTS).dtb" >> $@.config +endef + +define Build/boot-img + rm -f $@.boot + mkfs.fat -C $@.boot $(FAT32_BLOCKS) + mcopy -i $@.boot $(KDIR)/bootcode.bin :: + mcopy -i $@.boot $(KDIR)/COPYING.linux :: + mcopy -i $@.boot $(KDIR)/LICENCE.broadcom :: + mcopy -i $@.boot $(KDIR)/start.elf :: + mcopy -i $@.boot $(KDIR)/start_cd.elf :: + mcopy -i $@.boot $(KDIR)/fixup.dat :: + mcopy -i $@.boot $(KDIR)/fixup_cd.dat :: + mcopy -i $@.boot cmdline.txt :: + mcopy -i $@.boot $@.config ::config.txt + mcopy -i $@.boot $(word 1,$^) ::kernel.img + mcopy -i $@.boot $(DTS_DIR)/$(DEVICE_DTS).dtb ::$(DEVICE_DTS).dtb + mmd -i $@.boot ::/overlays + mcopy -i $@.boot $(DTS_DIR)/overlays/*.dtb ::/overlays/ + mcopy -i $@.boot $(DTS_DIR)/overlays/README ::/overlays/ +endef + +define Build/sdcard-img + ./gen_rpi_sdcard_img.sh $@ $@.boot $(word 2,$^) \ + $(CONFIG_BRCM2708_SD_BOOT_PARTSIZE) $(CONFIG_TARGET_ROOTFS_PARTSIZE) + $(call Image/gzip,$@) +endef + +### Device macros ### +define Device/Default + FILESYSTEMS := ext4 + PROFILES = Default $$(DEVICE_PROFILE) + KERNEL := kernel-bin + IMAGES := sdcard.bin + IMAGE/sdcard.bin := gen-cfg | boot-img | sdcard-img + DEVICE_PROFILE := + DEVICE_DTS := +endef +DEVICE_VARS += DEVICE_PROFILE DEVICE_DTS + +# $(1) = profile +# $(2) = image name +# $(3) = dts +define add_bcm2708 + define Device/$(2) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + endef + TARGET_DEVICES += $(2) +endef + +### BCM2708/BCM2835 ### +ifeq ($(SUBTARGET),bcm2708) + # Raspberry Pi Model B + $(eval $(call add_bcm2708,RaspberryPi_B,rpi-b,bcm2708-rpi-b)) + # Raspberry Pi Model B+ + $(eval $(call add_bcm2708,RaspberryPi_BPlus,rpi-b-plus,bcm2708-rpi-b-plus)) + # Raspberry Pi Compute Module + $(eval $(call add_bcm2708,RaspberryPi_CM,rpi-cm,bcm2708-rpi-cm)) +endif + +### BCM2709/BCM2836 ### +ifeq ($(SUBTARGET),bcm2709) + # Raspberry Pi 2 Model B + $(eval $(call add_bcm2708,RaspberryPi_2,rpi-2-b,bcm2709-rpi-2-b)) +endif + +$(eval $(call BuildImage)) diff --git a/target/linux/brcm2708/image/cmdline.txt b/target/linux/brcm2708/image/cmdline.txt new file mode 100644 index 0000000..95848bb --- /dev/null +++ b/target/linux/brcm2708/image/cmdline.txt @@ -0,0 +1 @@ +dwc_otg.lpm_enable=0 rpitestmode=1 console=tty1 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait diff --git a/target/linux/brcm2708/image/config.txt b/target/linux/brcm2708/image/config.txt new file mode 100644 index 0000000..1fb880f --- /dev/null +++ b/target/linux/brcm2708/image/config.txt @@ -0,0 +1,938 @@ +################################################################################ +## Raspberry Pi Configuration Settings +## +## Revision 14, 2012/10/22 +## +## Details taken from the eLinux wiki +## For up-to-date information please refer to wiki page. +## +## Wiki Location : http://elinux.org/RPi_config.txt +## +## +## Description: +## Details of each setting are described with each section that begins with +## a double hashed comment ('##') +## It is up to the user to remove the single hashed comment ('#') from each +## option they want to enable, and to set the specific value of that option. +## +## WARNING: Setting the following combination of parameters will set a +## permanent bit within the SOC and your warranty is void. +## over_voltage>0, and at least one of the following: +## force_turbo=1 +## current_limit_override=0x5A000020 +## temp_limit>85 +## +## Overclock settings will be disabled at runtime if the SoC reaches temp_limit +## +################################################################################ + +################################################################################ +## Standard Definition Video Settings +################################################################################ + +## sdtv_mode +## defines the TV standard for composite output +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Normal NTSC (Default) +## 1 Japanese version of NTSC - no pedestal +## 2 Normal PAL +## 3 Brazilian version of PAL - 525/60 rather than 625/50, different +## subcarrier +## +#sdtv_mode=0 + +## sdtv_aspect +## defines the aspect ratio for composite output +## +## Value Description +## ------------------------------------------------------------------------- +## 1 4:3 (Default) +## 2 14:9 +## 3 16:9 +## +#sdtv_aspect=1 + +## sdtv_disable_colourburst +## Disables colour burst on composite output. The picture will be +## monochrome, but possibly sharper +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Colour burst is enabled (Default) +## 1 Colour burst is disabled +## +#sdtv_disable_colourburst=1 + +################################################################################ +## High Definition Video Settings +################################################################################ + +## hdmi_safe +## Use "safe mode" settings to try to boot with maximum hdmi compatibility. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Disabled (Default) +## 1 Enabled (this does: hdmi_force_hotplug=1, config_hdmi_boost=4, +## hdmi_group=1, hdmi_mode=1, +## disable_overscan=0) +## +#hdmi_safe=1 + +## hdmi_force_hotplug +## Pretends HDMI hotplug signal is asserted so it appears a HDMI display +## is attached +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Disabled (Default) +## 1 Use HDMI mode even if no HDMI monitor is detected +## +#hdmi_force_hotplug=1 + +## hdmi_ignore_hotplug +## Pretends HDMI hotplug signal is not asserted so it appears a HDMI +## display is not attached +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Disabled (Default) +## 1 Use composite mode even if HDMI monitor is detected +## +#hdmi_ignore_hotplug=1 + +## hdmi_drive +## chooses between HDMI and DVI modes +## +## Value Description +## ------------------------------------------------------------------------- +## 1 Normal DVI mode (No sound) +## 2 Normal HDMI mode (Sound will be sent if supported and enabled) +## +#hdmi_drive=2 + +## hdmi_ignore_edid +## Enables the ignoring of EDID/display data +## +#hdmi_ignore_edid=0xa5000080 + +## hdmi_edid_file +## Read the EDID data from the edid.dat file instead of from the attached +## device +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Read EDID data from attached device (Default) +## 1 Read EDID data from edid.txt file +## +#hdmi_edid_file=1 + +## hdmi_force_edid_audio +## Pretends all audio formats are supported by display, allowing +## passthrough of DTS/AC3 even when not reported as supported. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Use EDID provided values (Default) +## 1 Pretend all audio formats are supported +## +#hdmi_force_edid_audio=1 + +## avoid_edid_fuzzy_match +## Avoid fuzzy matching of modes described in edid. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Use fuzzy matching (Default) +## 1 Avoid fuzzy matching +## +#avoid_edid_fuzzy_match=1 + +## hdmi_group +## Defines the HDMI type +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Use the preferred group reported by the edid (Default) +## 1 CEA +## 2 DMT +## +#hdmi_group=1 + +## hdmi_mode +## defines screen resolution in CEA or DMT format +## +## H means 16:9 variant (of a normally 4:3 mode). +## 2x means pixel doubled (i.e. higher clock rate, with each pixel repeated +## twice) +## 4x means pixel quadrupled (i.e. higher clock rate, with each pixel +## repeated four times) +## reduced blanking means fewer bytes are used for blanking within the data +## stream (i.e. lower clock rate, with fewer wasted bytes) +## +## Value hdmi_group=CEA hdmi_group=DMT +## ------------------------------------------------------------------------- +## 1 VGA 640x350 85Hz +## 2 480p 60Hz 640x400 85Hz +## 3 480p 60Hz H 720x400 85Hz +## 4 720p 60Hz 640x480 60Hz +## 5 1080i 60Hz 640x480 72Hz +## 6 480i 60Hz 640x480 75Hz +## 7 480i 60Hz H 640x480 85Hz +## 8 240p 60Hz 800x600 56Hz +## 9 240p 60Hz H 800x600 60Hz +## 10 480i 60Hz 4x 800x600 72Hz +## 11 480i 60Hz 4x H 800x600 75Hz +## 12 240p 60Hz 4x 800x600 85Hz +## 13 240p 60Hz 4x H 800x600 120Hz +## 14 480p 60Hz 2x 848x480 60Hz +## 15 480p 60Hz 2x H 1024x768 43Hz DO NOT USE +## 16 1080p 60Hz 1024x768 60Hz +## 17 576p 50Hz 1024x768 70Hz +## 18 576p 50Hz H 1024x768 75Hz +## 19 720p 50Hz 1024x768 85Hz +## 20 1080i 50Hz 1024x768 120Hz +## 21 576i 50Hz 1152x864 75Hz +## 22 576i 50Hz H 1280x768 reduced blanking +## 23 288p 50Hz 1280x768 60Hz +## 24 288p 50Hz H 1280x768 75Hz +## 25 576i 50Hz 4x 1280x768 85Hz +## 26 576i 50Hz 4x H 1280x768 120Hz reduced blanking +## 27 288p 50Hz 4x 1280x800 reduced blanking +## 28 288p 50Hz 4x H 1280x800 60Hz +## 29 576p 50Hz 2x 1280x800 75Hz +## 30 576p 50Hz 2x H 1280x800 85Hz +## 31 1080p 50Hz 1280x800 120Hz reduced blanking +## 32 1080p 24Hz 1280x960 60Hz +## 33 1080p 25Hz 1280x960 85Hz +## 34 1080p 30Hz 1280x960 120Hz reduced blanking +## 35 480p 60Hz 4x 1280x1024 60Hz +## 36 480p 60Hz 4x H 1280x1024 75Hz +## 37 576p 50Hz 4x 1280x1024 85Hz +## 38 576p 50Hz 4x H 1280x1024 120Hz reduced blanking +## 39 1080i 50Hz reduced blanking 1360x768 60Hz +## 40 1080i 100Hz 1360x768 120Hz reduced blanking +## 41 720p 100Hz 1400x1050 reduced blanking +## 42 576p 100Hz 1400x1050 60Hz +## 43 576p 100Hz H 1400x1050 75Hz +## 44 576i 100Hz 1400x1050 85Hz +## 45 576i 100Hz H 1400x1050 120Hz reduced blanking +## 46 1080i 120Hz 1440x900 reduced blanking +## 47 720p 120Hz 1440x900 60Hz +## 48 480p 120Hz 1440x900 75Hz +## 49 480p 120Hz H 1440x900 85Hz +## 50 480i 120Hz 1440x900 120Hz reduced blanking +## 51 480i 120Hz H 1600x1200 60Hz +## 52 576p 200Hz 1600x1200 65Hz +## 53 576p 200Hz H 1600x1200 70Hz +## 54 576i 200Hz 1600x1200 75Hz +## 55 576i 200Hz H 1600x1200 85Hz +## 56 480p 240Hz 1600x1200 120Hz reduced blanking +## 57 480p 240Hz H 1680x1050 reduced blanking +## 58 480i 240Hz 1680x1050 60Hz +## 59 480i 240Hz H 1680x1050 75Hz +## 60 1680x1050 85Hz +## 61 1680x1050 120Hz reduced blanking +## 62 1792x1344 60Hz +## 63 1792x1344 75Hz +## 64 1792x1344 120Hz reduced blanking +## 65 1856x1392 60Hz +## 66 1856x1392 75Hz +## 67 1856x1392 120Hz reduced blanking +## 68 1920x1200 reduced blanking +## 69 1920x1200 60Hz +## 70 1920x1200 75Hz +## 71 1920x1200 85Hz +## 72 1920x1200 120Hz reduced blanking +## 73 1920x1440 60Hz +## 74 1920x1440 75Hz +## 75 1920x1440 120Hz reduced blanking +## 76 2560x1600 reduced blanking +## 77 2560x1600 60Hz +## 78 2560x1600 75Hz +## 79 2560x1600 85Hz +## 80 2560x1600 120Hz reduced blanking +## 81 1366x768 60Hz +## 82 1080p 60Hz +## 83 1600x900 reduced blanking +## 84 2048x1152 reduced blanking +## 85 720p 60Hz +## 86 1366x768 reduced blanking +## +#hdmi_mode=1 + +## config_hdmi_boost +## configure the signal strength of the HDMI interface. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 (Default) +## 1 +## 2 +## 3 +## 4 Try if you have interference issues with HDMI +## 5 +## 6 +## 7 Maximum +## +#config_hdmi_boost=0 + +## hdmi_ignore_cec_init +## Doesn't sent initial active source message. Avoids bringing +## (CEC enabled) TV out of standby and channel switch when rebooting. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Normal behaviour (Default) +## 1 Doesn't sent initial active source message +## +#hdmi_ignore_cec_init=1 + +## hdmi_ignore_cec +## Pretends CEC is not supported at all by TV. +## No CEC functions will be supported. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Normal behaviour (Default) +## 1 Pretend CEC is not supported by TV +## +#hdmi_ignore_cec=1 + +################################################################################ +## Overscan Video Settings +################################################################################ + +## overscan_left +## Number of pixels to skip on left +## +#overscan_left=0 + +## overscan_right +## Number of pixels to skip on right +## +#overscan_right=0 + +## overscan_top +## Number of pixels to skip on top +## +#overscan_top=0 + +## overscan_bottom +## Number of pixels to skip on bottom +## +#overscan_bottom=0 + +## disable_overscan +## Set to 1 to disable overscan +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Overscan Enabled (Default) +## 1 Overscan Disabled +## +#disable_overscan=1 + +################################################################################ +## Framebuffer Video Settings +################################################################################ + +## framebuffer_width +## Console framebuffer width in pixels. Default is display width minus +## overscan. +## +#framebuffer_width=0 + +## framebuffer_height +## Console framebuffer height in pixels. Default is display height minus +## overscan. +## +#framebuffer_height=0 + +## framebuffer_depth +## Console framebuffer depth in bits per pixel. +## +## Value Description +## ------------------------------------------------------------------------- +## 8 Valid, but default RGB palette makes an unreadable screen +## 16 (Default) +## 24 Looks better but has corruption issues as of 2012/06/15 +## 32 Has no corruption issues but needs framebuffer_ignore_alpha=1 +## and shows the wrong colors as of 2012/06/15 +## +#framebuffer_depth=16 + +## framebuffer_ignore_alpha +## Set to 1 to disable alpha channel. Helps with 32bit. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Enable Alpha Channel (Default) +## 1 Disable Alpha Channel +## +#framebuffer_ignore_alpha=0 + +################################################################################ +## General Video Settings +################################################################################ + +## display_rotate +## Rotate the display clockwise or flip the display. +## The 90 and 270 degrees rotation options require additional memory on GPU, +## so won't work with the 16M GPU split. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 0 degrees (Default) +## 1 90 degrees +## 2 180 degrees +## 3 270 degrees +## 0x10000 Horizontal flip +## 0x20000 Vertical flip +## +#display_rotate=0 + +################################################################################ +## Licensed Codecs +## +## Hardware decoding of additional codecs can be enabled by purchasing a +## license that is locked to the CPU serial number of your Raspberry Pi. +## +## Up to 8 licenses per CODEC can be specified as a comma seperated list. +## +################################################################################ + +## decode_MPG2 +## License key to allow hardware MPEG-2 decoding. +## +#decode_MPG2=0x12345678 + +## decode_WVC1 +## License key to allow hardware VC-1 decoding. +## +#decode_WVC1=0x12345678 + +################################################################################ +## Test Settings +################################################################################ + +## test_mode +## Enable test sound/image during boot for manufacturing test. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Disable Test Mod (Default) +## 1 Enable Test Mode +## +#test_mode=0 + +################################################################################ +## Memory Settings +################################################################################ + +## disable_l2cache +## Disable arm access to GPU's L2 cache. Needs corresponding L2 disabled +## kernel. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Enable L2 Cache (Default) +## 1 Disable L2 cache +## +#disable_l2cache=0 + +## gpu_mem +## GPU memory allocation in MB for all board revisions. +## +## Default 64 +## +#gpu_mem=128 + +## gpu_mem_256 +## GPU memory allocation in MB for 256MB board revision. +## This option overrides gpu_mem. +## +#gpu_mem_256=128 + +## gpu_mem_512 +## GPU memory allocation in MB for 512MB board revision. +## This option overrides gpu_mem. +## +#gpu_mem_512=128 + +## gpu_mem_1024 +## GPU memory allocation in MB for 1024MB board revision. +## This option overrides gpu_mem. +## +#gpu_mem_1024=128 + +################################################################################ +## Boot Option Settings +################################################################################ + +## disable_commandline_tags +## Stop start.elf from filling in ATAGS (memory from 0x100) before +## launching kernel +## +disable_commandline_tags=1 + +## cmdline (string) +## Command line parameters. Can be used instead of cmdline.txt file +## +#cmdline="" + +## kernel (string) +## Alternative name to use when loading kernel. +## +#kernel="" + +## kernel_address +## Address to load kernel.img file at +## +kernel_address=0x8000 + +## ramfsfile (string) +## ramfs file to load +## +#ramfsfile="" + +## ramfsaddr +## Address to load ramfs file at +## +#ramfsaddr=0x00000000 + +## initramfs (string address) +## ramfs file and address to load it at (it's like ramfsfile+ramfsaddr in +## one option). +## +## NOTE: this option uses different syntax than all other options - you +## should not use "=" character here. +## +#initramfs initramf.gz 0x00800000 + +## device_tree_address +## Address to load device_tree at +## +device_tree_address=0x100 + +## init_uart_baud +## Initial uart baud rate. +## +## Default 115200 +## +init_uart_baud=115200 + +## init_uart_clock +## Initial uart clock. +## +## Default 3000000 (3MHz) +## +init_uart_clock=3000000 + +## init_emmc_clock +## Initial emmc clock, increasing this can speedup your SD-card. +## +## Default 100000000 (100mhz) +## +#init_emmc_clock=100000000 + +## boot_delay +## Wait for a given number of seconds in start.elf before loading +## kernel.img. +## +## delay = (1000 * boot_delay) + boot_delay_ms +## +## Default 1 +## +#boot_delay=0 + +## boot_delay_ms +## Wait for a given number of milliseconds in start.elf before loading +## kernel.img. +## +## delay = (1000 * boot_delay) + boot_delay_ms +## +## Default 0 +## +#boot_delay_ms=0 + +## avoid_safe_mode +## Adding a jumper between pins 5 & 6 of P1 enables a recovery Safe Mode. +## If pins 5 & 6 are used for connecting to external devices (e.g. GPIO), +## then this setting can be used to ensure Safe Mode is not triggered. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Respect Safe Mode input (Default) +## 1 Ignore Safe Mode input +## +#avoid_safe_mode=1 + +################################################################################ +## Overclocking Settings +## +## ARM, SDRAM and GPU each have their own PLLs and can have unrelated +## frequencies. +## +## The GPU core, h264, v3d and isp share a PLL, so need to have related +## frequencies. +## pll_freq = floor(2400 / (2 * core_freq)) * (2 * core_freq) +## gpu_freq = pll_freq / [even number] +## +## The effective gpu_freq is automatically rounded to nearest even integer, so +## asking for core_freq = 500 and gpu_freq = 300 will result in divisor of +## 2000/300 = 6.666 => 6 and so 333.33MHz. +## +## +## Standard Profiles: +## arm_freq core_freq sdram_freq over_voltage +## ------------------------------------------------------------------------- +## None 700 250 400 0 +## Modest 800 300 400 0 +## Medium 900 333 450 2 +## High 950 450 450 6 +## Turbo 1000 500 500 6 +## +################################################################################ + +## force_turbo +## Control the kernel "ondemand" governor. It has no effect if no overclock +## settings are specified. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Enable dynamic clocks and voltage for the ARM core, GPU core and +## SDRAM (Default). +## Overclocking of h264_freq, v3d_freq and isp_freq is ignored. +## 1 Disable dynamic clocks and voltage for the ARM core, GPU core +## and SDRAM. +## Overclocking of h264_freq, v3d_freq and isp_freq is allowed. +## +#force_turbo=0 + +## initial_turbo +## Enables turbo mode from boot for the given value in seconds (up to 60) +## or until cpufreq sets a frequency. Can help with sdcard corruption if +## overclocked. +## +## Default 0 +## +#initial_turbo=0 + +## temp_limit +## Overheat protection. Sets clocks and voltages to default when the SoC +## reaches this Celsius value. +## Setting this higher than default voids warranty. +## +## Default 85 +## +#temp_limit=85 + +## arm_freq +## Frequency of ARM in MHz. +## +## Default 700. +## +#arm_freq=700 + +## arm_freq_min +## Minimum frequency of ARM in MHz (used for dynamic clocking). +## +## Default 700. +## +#arm_freq_min=700 + +## gpu_freq +## Sets core_freq, h264_freq, isp_freq, v3d_freq together. +## +## Default 250. +## +#gpu_freq=250 + +## core_freq +## Frequency of GPU processor core in MHz. It has an impact on ARM +## performance since it drives L2 cache. +## +## Default 250. +## +#core_freq=250 + +## core_freq_min +## Minimum frequency of GPU processor core in MHz (used for dynamic +## clocking). It has an impact on ARM performance since it drives L2 cache. +## +## Default 250. +## +#core_freq_min=250 + +## h264_freq +## Frequency of hardware video block in MHz. +## +## Default 250. +## +#h264_freq=250 + +## isp_freq +## Frequency of image sensor pipeline block in MHz. +## +## Default 250. +## +#isp_freq=250 + +## v3d_freq +## Frequency of 3D block in MHz. +## +## Default 250. +## +#v3d_freq=250 + +## sdram_freq +## Frequency of SDRAM in MHz. +## +## Default 400. +## +#sdram_freq=400 + +## sdram_freq_min +## Minimum frequency of SDRAM in MHz (used for dynamic clocking). +## +## Default 400. +## +#sdram_freq_min=400 + +## avoid_pwm_pll +## Unlink core_freq from the rest of the gpu. Analog audio should still +## work, but from a fractional divider, so lower quality. +## +## Value Description +## ------------------------------------------------------------------------- +## 0 Linked core_freq (Default) +## 1 Unlinked core_freq +## +#avoid_pwm_pll=1 + +################################################################################ +## Voltage Settings +################################################################################ + +## current_limit_override +## Disables SMPS current limit protection. Can help if you are currently +## hitting a reboot failure when overclocking too high. +## +#current_limit_override=0x5A000020 + +## over_voltage +## ARM/GPU core voltage adjust. +## +## Value Description +## ------------------------------------------------------------------------- +## -16 0.8 V +## -15 0.825 V +## -14 0.85 V +## -13 0.875 V +## -12 0.9 V +## -11 0.925 V +## -10 0.95 V +## -9 0.975 V +## -8 1.0 V +## -7 1.025 V +## -6 1.05 V +## -5 1.075 V +## -4 1.1 V +## -3 1.125 V +## -2 1.15 V +## -1 1.175 V +## 0 1.2 V (Default) +## 1 1.225 V +## 2 1.25 V +## 3 1.275 V +## 4 1.3 V +## 5 1.325 V +## 6 1.35 V +## 7 1.375 V (requires force_turbo=1) +## 8 1.4 V (requires force_turbo=1) +## +#over_voltage=0 + +## over_voltage_min +## Minimum ARM/GPU core voltage adjust (used for dynamic clocking). +## +## Value Description +## ------------------------------------------------------------------------- +## -16 0.8 V +## -15 0.825 V +## -14 0.85 V +## -13 0.875 V +## -12 0.9 V +## -11 0.925 V +## -10 0.95 V +## -9 0.975 V +## -8 1.0 V +## -7 1.025 V +## -6 1.05 V +## -5 1.075 V +## -4 1.1 V +## -3 1.125 V +## -2 1.15 V +## -1 1.175 V +## 0 1.2 V (Default) +## 1 1.225 V +## 2 1.25 V +## 3 1.275 V +## 4 1.3 V +## 5 1.325 V +## 6 1.35 V +## 7 1.375 V (requires force_turbo=1) +## 8 1.4 V (requires force_turbo=1) +## +#over_voltage_min=0 + +## over_voltage_sdram +## Sets over_voltage_sdram_c, over_voltage_sdram_i, over_voltage_sdram_p +## together +## +## Value Description +## ------------------------------------------------------------------------- +## -16 0.8 V +## -15 0.825 V +## -14 0.85 V +## -13 0.875 V +## -12 0.9 V +## -11 0.925 V +## -10 0.95 V +## -9 0.975 V +## -8 1.0 V +## -7 1.025 V +## -6 1.05 V +## -5 1.075 V +## -4 1.1 V +## -3 1.125 V +## -2 1.15 V +## -1 1.175 V +## 0 1.2 V (Default) +## 1 1.225 V +## 2 1.25 V +## 3 1.275 V +## 4 1.3 V +## 5 1.325 V +## 6 1.35 V +## 7 1.375 V +## 8 1.4 V +## +#over_voltage_sdram=0 + +## over_voltage_sdram_c +## SDRAM controller voltage adjust. +## +## Value Description +## ------------------------------------------------------------------------- +## -16 0.8 V +## -15 0.825 V +## -14 0.85 V +## -13 0.875 V +## -12 0.9 V +## -11 0.925 V +## -10 0.95 V +## -9 0.975 V +## -8 1.0 V +## -7 1.025 V +## -6 1.05 V +## -5 1.075 V +## -4 1.1 V +## -3 1.125 V +## -2 1.15 V +## -1 1.175 V +## 0 1.2 V (Default) +## 1 1.225 V +## 2 1.25 V +## 3 1.275 V +## 4 1.3 V +## 5 1.325 V +## 6 1.35 V +## 7 1.375 V +## 8 1.4 V +## +#over_voltage_sdram_c=0 + +## over_voltage_sdram_i +## SDRAM I/O voltage adjust. +## +## Value Description +## ------------------------------------------------------------------------- +## -16 0.8 V +## -15 0.825 V +## -14 0.85 V +## -13 0.875 V +## -12 0.9 V +## -11 0.925 V +## -10 0.95 V +## -9 0.975 V +## -8 1.0 V +## -7 1.025 V +## -6 1.05 V +## -5 1.075 V +## -4 1.1 V +## -3 1.125 V +## -2 1.15 V +## -1 1.175 V +## 0 1.2 V (Default) +## 1 1.225 V +## 2 1.25 V +## 3 1.275 V +## 4 1.3 V +## 5 1.325 V +## 6 1.35 V +## 7 1.375 V +## 8 1.4 V +## +#over_voltage_sdram_i=0 + +## over_voltage_sdram_p +## SDRAM phy voltage adjust. +## +## Value Description +## ------------------------------------------------------------------------- +## -16 0.8 V +## -15 0.825 V +## -14 0.85 V +## -13 0.875 V +## -12 0.9 V +## -11 0.925 V +## -10 0.95 V +## -9 0.975 V +## -8 1.0 V +## -7 1.025 V +## -6 1.05 V +## -5 1.075 V +## -4 1.1 V +## -3 1.125 V +## -2 1.15 V +## -1 1.175 V +## 0 1.2 V (Default) +## 1 1.225 V +## 2 1.25 V +## 3 1.275 V +## 4 1.3 V +## 5 1.325 V +## 6 1.35 V +## 7 1.375 V +## 8 1.4 V +## +#over_voltage_sdram_p=0 + +################################################################################ +## Device Tree Settings +################################################################################ + +dtparam=random=on,watchdog=on,audio=on,i2c0=on,i2c1=on,spi=on + +#dtoverlay=hifiberry-amp-overlay +#dtoverlay=hifiberry-dac-overlay +#dtoverlay=hifiberry-dacplus-overlay +#dtoverlay=hifiberry-digi-overlay +#dtoverlay=iqaudio-dac-overlay +#dtoverlay=iqaudio-dacplus-overlay +#dtoverlay=raspidac3-overlay +#dtoverlay=rpi-proto-overlay diff --git a/target/linux/brcm2708/image/gen_rpi_sdcard_img.sh b/target/linux/brcm2708/image/gen_rpi_sdcard_img.sh new file mode 100755 index 0000000..ffe01fa --- /dev/null +++ b/target/linux/brcm2708/image/gen_rpi_sdcard_img.sh @@ -0,0 +1,29 @@ +#!/usr/bin/env bash + +set -x +[ $# -eq 5 ] || { + echo "SYNTAX: $0 " + exit 1 +} + +OUTPUT="$1" +BOOTFS="$2" +ROOTFS="$3" +BOOTFSSIZE="$4" +ROOTFSSIZE="$5" + +head=4 +sect=63 + +set `ptgen -o $OUTPUT -h $head -s $sect -l 4096 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M` + +BOOTOFFSET="$(($1 / 512))" +BOOTSIZE="$(($2 / 512))" +ROOTFSOFFSET="$(($3 / 512))" +ROOTFSSIZE="$(($4 / 512))" + +dd bs=512 if="$BOOTFS" of="$OUTPUT" seek="$BOOTOFFSET" conv=notrunc +dd bs=512 if="$ROOTFS" of="$OUTPUT" seek="$ROOTFSOFFSET" conv=notrunc + + + diff --git a/target/linux/brcm2708/modules.mk b/target/linux/brcm2708/modules.mk new file mode 100644 index 0000000..3bc592c --- /dev/null +++ b/target/linux/brcm2708/modules.mk @@ -0,0 +1,378 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/sound-arm-bcm2835 + TITLE:=BCM2835 ALSA driver + KCONFIG:= \ + CONFIG_SND_ARM=y \ + CONFIG_SND_BCM2835 \ + CONFIG_SND_ARMAACI=n + FILES:= \ + $(LINUX_DIR)/sound/arm/snd-bcm2835.ko + AUTOLOAD:=$(call AutoLoad,68,snd-bcm2835) + DEPENDS:=@TARGET_brcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-arm-bcm2835/description + This package contains the BCM2835 ALSA pcm card driver +endef + +$(eval $(call KernelPackage,sound-arm-bcm2835)) + + +define KernelPackage/sound-soc-bcm2708-i2s + TITLE:=SoC Audio support for the Broadcom 2708 I2S module + KCONFIG:= \ + CONFIG_BCM2708_SPIDEV=n \ + CONFIG_MFD_RPISENSE_CORE=n \ + CONFIG_SND_BCM2708_SOC_I2S \ + CONFIG_SND_SOC_DMAENGINE_PCM=y \ + CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y + FILES:= \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-bcm2708-i2s.ko + AUTOLOAD:=$(call AutoLoad,68,snd-soc-bcm2708-i2s) + DEPENDS:=@TARGET_brcm2708 +kmod-regmap +kmod-sound-soc-core + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-bcm2708-i2s/description + This package contains support for codecs attached to the Broadcom 2708 I2S interface +endef + +$(eval $(call KernelPackage,sound-soc-bcm2708-i2s)) + +define KernelPackage/sound-soc-hifiberry-dac + TITLE:=Support for HifiBerry DAC + KCONFIG:= \ + CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC \ + CONFIG_SND_SOC_PCM5102A + FILES:= \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-dac.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm5102a.ko + AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm5102a snd-soc-hifiberry-dac) + DEPENDS:=kmod-sound-soc-bcm2708-i2s +kmod-i2c-bcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-hifiberry-dac/description + This package contains support for HifiBerry DAC +endef + +$(eval $(call KernelPackage,sound-soc-hifiberry-dac)) + +define KernelPackage/sound-soc-hifiberry-dacplus + TITLE:=Support for HifiBerry DAC+ / DAC+ Pro + KCONFIG:= \ + CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS \ + CONFIG_SND_SOC_PCM512x + FILES:= \ + $(LINUX_DIR)/drivers/clk/clk-hifiberry-dacpro.ko \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-dacplus.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko + AUTOLOAD:=$(call AutoLoad,68,clk-hifiberry-dacpro snd-soc-pcm512x snd-soc-hifiberry-dacplus) + DEPENDS:=kmod-sound-soc-bcm2708-i2s +kmod-i2c-bcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-hifiberry-dacplus/description + This package contains support for HifiBerry DAC+ / DAC+ Pro +endef + +$(eval $(call KernelPackage,sound-soc-hifiberry-dacplus)) + +define KernelPackage/sound-soc-hifiberry-digi + TITLE:=Support for HifiBerry Digi + KCONFIG:= \ + CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI \ + CONFIG_SND_SOC_WM8804 + FILES:= \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-digi.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko + AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8804 snd-soc-hifiberry-digi) + DEPENDS:=kmod-sound-soc-bcm2708-i2s +kmod-i2c-bcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-hifiberry-digi/description + This package contains support for HifiBerry Digi +endef + +$(eval $(call KernelPackage,sound-soc-hifiberry-digi)) + +define KernelPackage/sound-soc-hifiberry-amp + TITLE:=Support for HifiBerry Amp + KCONFIG:= \ + CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP \ + CONFIG_SND_SOC_TAS5713 + FILES:= \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-amp.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-tas5713.ko + AUTOLOAD:=$(call AutoLoad,68,snd-soc-tas5713 snd-soc-hifiberry-amp) + DEPENDS:=kmod-sound-soc-bcm2708-i2s +kmod-i2c-bcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-hifiberry-amp/description + This package contains support for HifiBerry Amp +endef + +$(eval $(call KernelPackage,sound-soc-hifiberry-amp)) + +define KernelPackage/sound-soc-rpi-dac + TITLE:=Support for RPi-DAC + KCONFIG:= \ + CONFIG_SND_BCM2708_SOC_RPI_DAC \ + CONFIG_SND_SOC_PCM1794A + FILES:= \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-rpi-dac.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm1794a.ko + AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm1794a snd-soc-rpi-dac) + DEPENDS:=kmod-sound-soc-bcm2708-i2s +kmod-i2c-bcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-rpi-dac/description + This package contains support for RPi-DAC +endef + +$(eval $(call KernelPackage,sound-soc-rpi-dac)) + +define KernelPackage/sound-soc-rpi-proto + TITLE:=Support for RPi-PROTO + KCONFIG:= \ + CONFIG_SND_BCM2708_SOC_RPI_PROTO \ + CONFIG_SND_SOC_WM8731 + FILES:= \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-rpi-proto.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8731.ko + AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8731 snd-soc-rpi-proto) + DEPENDS:=kmod-sound-soc-bcm2708-i2s +kmod-i2c-bcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-rpi-proto/description + This package contains support for RPi-PROTO +endef + +$(eval $(call KernelPackage,sound-soc-rpi-proto)) + +define KernelPackage/sound-soc-iqaudio-dac + TITLE:=Support for IQaudIO-DAC + KCONFIG:= \ + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC \ + CONFIG_SND_SOC_PCM512x \ + CONFIG_SND_SOC_PCM512x_I2C + FILES:= \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-iqaudio-dac.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko + AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x snd-soc-pcm512x-i2c snd-soc-iqaudio-dac) + DEPENDS:=kmod-sound-soc-bcm2708-i2s +kmod-i2c-bcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-iqaudio-dac/description + This package contains support for IQaudIO-DAC +endef + +$(eval $(call KernelPackage,sound-soc-iqaudio-dac)) + +define KernelPackage/sound-soc-raspidac3 + TITLE:=Support for RaspiDAC Rev.3x + KCONFIG:= \ + CONFIG_SND_BCM2708_SOC_RASPIDAC3 \ + CONFIG_SND_SOC_PCM512x \ + CONFIG_SND_SOC_PCM512x_I2C \ + CONFIG_SND_SOC_TPA6130A2 + FILES:= \ + $(LINUX_DIR)/sound/soc/bcm/snd-soc-raspidac3.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-tpa6130a2.ko + AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x snd-soc-pcm512x-i2c snd-soc-tpa6130a2 snd-soc-raspidac3) + DEPENDS:=kmod-sound-soc-bcm2708-i2s +kmod-i2c-bcm2708 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-raspidac3/description + This package contains support for RaspiDAC Rev.3x +endef + +$(eval $(call KernelPackage,sound-soc-raspidac3)) + + +define KernelPackage/random-bcm2708 + SUBMENU:=$(OTHER_MENU) + TITLE:=BCM2708 HW Random Number Generator + KCONFIG:=CONFIG_HW_RANDOM_BCM2708 + FILES:=$(LINUX_DIR)/drivers/char/hw_random/bcm2708-rng.ko + AUTOLOAD:=$(call AutoLoad,11,bcm2708-rng) + DEPENDS:=@TARGET_brcm2708 +kmod-random-core +endef + +define KernelPackage/random-bcm2708/description + This package contains the Broadcom 2708 HW random number generator driver +endef + +$(eval $(call KernelPackage,random-bcm2708)) + +define KernelPackage/random-bcm2835 + SUBMENU:=$(OTHER_MENU) + TITLE:=BCM2835 HW Random Number Generator + KCONFIG:=CONFIG_HW_RANDOM_BCM2835 + FILES:=$(LINUX_DIR)/drivers/char/hw_random/bcm2835-rng.ko + AUTOLOAD:=$(call AutoLoad,11,bcm2835-rng) + DEPENDS:=@TARGET_brcm2708 +kmod-random-core +endef + +define KernelPackage/random-bcm2835/description + This package contains the Broadcom 2835 HW random number generator driver +endef + +$(eval $(call KernelPackage,random-bcm2835)) + + +define KernelPackage/smi-bcm2835 + SUBMENU:=$(OTHER_MENU) + TITLE:=BCM2835 SMI driver + KCONFIG:=CONFIG_BCM2835_SMI + FILES:=$(LINUX_DIR)/drivers/misc/bcm2835_smi.ko + AUTOLOAD:=$(call AutoLoad,20,bcm2835_smi) + DEPENDS:=@TARGET_brcm2708 +endef + +define KernelPackage/smi-bcm2835/description + This package contains the Character device driver for Broadcom Secondary + Memory Interface +endef + +$(eval $(call KernelPackage,smi-bcm2835)) + +define KernelPackage/smi-bcm2835-dev + SUBMENU:=$(OTHER_MENU) + TITLE:=BCM2835 SMI device driver + KCONFIG:=CONFIG_BCM2835_SMI_DEV + FILES:=$(LINUX_DIR)/drivers/char/broadcom/bcm2835_smi_dev.ko + AUTOLOAD:=$(call AutoLoad,21,bcm2835_smi_dev) + DEPENDS:=@TARGET_brcm2708 +kmod-smi-bcm2835 +endef + +define KernelPackage/smi-bcm2835-dev/description + This driver provides a character device interface (ioctl + read/write) to + Broadcom's Secondary Memory interface. The low-level functionality is provided + by the SMI driver itself. +endef + +$(eval $(call KernelPackage,smi-bcm2835-dev)) + + +define KernelPackage/spi-bcm2708 + SUBMENU:=$(SPI_MENU) + TITLE:=BCM2708 SPI controller driver + KCONFIG:= \ + CONFIG_BCM2708_SPIDEV=n \ + CONFIG_SPI=y \ + CONFIG_SPI_BCM2708 \ + CONFIG_SPI_MASTER=y + FILES:=$(LINUX_DIR)/drivers/spi/spi-bcm2708.ko + AUTOLOAD:=$(call AutoLoad,89,spi-bcm2708) + DEPENDS:=@TARGET_brcm2708 +endef + +define KernelPackage/spi-bcm2708/description + This package contains the Broadcom 2708 SPI master controller driver +endef + +$(eval $(call KernelPackage,spi-bcm2708)) + +define KernelPackage/spi-bcm2835 + SUBMENU:=$(SPI_MENU) + TITLE:=BCM2835 SPI controller driver + KCONFIG:=\ + CONFIG_BCM2708_SPIDEV=n \ + CONFIG_SPI=y \ + CONFIG_SPI_BCM2835 \ + CONFIG_SPI_MASTER=y + FILES:=$(LINUX_DIR)/drivers/spi/spi-bcm2835.ko + AUTOLOAD:=$(call AutoLoad,89,spi-bcm2835) + DEPENDS:=@TARGET_brcm2708 +endef + +define KernelPackage/spi-bcm2835/description + This package contains the Broadcom 2835 SPI master controller driver +endef + +$(eval $(call KernelPackage,spi-bcm2835)) + + +define KernelPackage/hwmon-bcm2835 + TITLE:=BCM2835 HWMON driver + KCONFIG:=CONFIG_SENSORS_BCM2835 + FILES:=$(LINUX_DIR)/drivers/hwmon/bcm2835-hwmon.ko + AUTOLOAD:=$(call AutoLoad,60,bcm2835-hwmon) + $(call AddDepends/hwmon,@TARGET_brcm2708) +endef + +define KernelPackage/hwmon-bcm2835/description + Kernel module for BCM2835 thermal monitor chip +endef + +$(eval $(call KernelPackage,hwmon-bcm2835)) + + +I2C_BCM2708_MODULES:=\ + CONFIG_I2C_BCM2708:drivers/i2c/busses/i2c-bcm2708 + +define KernelPackage/i2c-bcm2708 + $(call i2c_defaults,$(I2C_BCM2708_MODULES),59) + TITLE:=Broadcom BCM2708 I2C master controller driver + KCONFIG+= \ + CONFIG_I2C_BCM2708_BAUDRATE=100000 \ + CONFIG_MFD_RPISENSE_CORE=n + DEPENDS:=@TARGET_brcm2708 +kmod-i2c-core +endef + +define KernelPackage/i2c-bcm2708/description + This package contains the Broadcom 2708 I2C master controller driver +endef + +$(eval $(call KernelPackage,i2c-bcm2708)) + +I2C_BCM2835_MODULES:=\ + CONFIG_I2C_BCM2835:drivers/i2c/busses/i2c-bcm2835 + +define KernelPackage/i2c-bcm2835 + $(call i2c_defaults,$(I2C_BCM2835_MODULES),59) + TITLE:=Broadcom BCM2835 I2C master controller driver + KCONFIG+= \ + CONFIG_MFD_RPISENSE_CORE=n + DEPENDS:=@TARGET_brcm2708 +kmod-i2c-core +endef + +define KernelPackage/i2c-bcm2835/description + This package contains the Broadcom 2835 I2C master controller driver +endef + +$(eval $(call KernelPackage,i2c-bcm2835)) + + +define KernelPackage/video-bcm2835 + TITLE:=Broadcom BCM2835 camera interface driver + KCONFIG:= \ + CONFIG_VIDEO_BCM2835=y \ + CONFIG_VIDEO_BCM2835_MMAL + FILES:= $(LINUX_DIR)/drivers/media/platform/bcm2835/bcm2835-v4l2.ko + AUTOLOAD:=$(call AutoLoad,65,bcm2835-v4l2) + $(call AddDepends/video,@TARGET_brcm2708 +kmod-video-videobuf2) +endef + +define KernelPackage/video-bcm2835/description + This is a V4L2 driver for the Broadcom 2835 MMAL camera host interface +endef + +$(eval $(call KernelPackage,video-bcm2835)) diff --git a/target/linux/brcm2708/patches-4.1/0001-Main-bcm2708-bcm2709-linux-port.patch b/target/linux/brcm2708/patches-4.1/0001-Main-bcm2708-bcm2709-linux-port.patch new file mode 100644 index 0000000..08bb800 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0001-Main-bcm2708-bcm2709-linux-port.patch @@ -0,0 +1,6829 @@ +From 781a47e405cae18b69f4f76c2d945401366cb81f Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Sun, 12 May 2013 12:24:19 +0100 +Subject: [PATCH 001/203] Main bcm2708/bcm2709 linux port +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: popcornmix +Signed-off-by: Noralf Trønnes +--- + arch/arm/Kconfig | 39 ++ + arch/arm/Kconfig.debug | 8 + + arch/arm/Makefile | 2 + + arch/arm/kernel/head.S | 8 + + arch/arm/kernel/process.c | 10 + + arch/arm/mach-bcm2708/Kconfig | 30 + + arch/arm/mach-bcm2708/Makefile | 5 + + arch/arm/mach-bcm2708/Makefile.boot | 3 + + arch/arm/mach-bcm2708/armctrl.c | 304 +++++++++ + arch/arm/mach-bcm2708/armctrl.h | 27 + + arch/arm/mach-bcm2708/bcm2708.c | 622 ++++++++++++++++++ + arch/arm/mach-bcm2708/bcm2708.h | 49 ++ + arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 ++++++++++++ + arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 + + arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 + + arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 ++ + arch/arm/mach-bcm2708/include/mach/frc.h | 38 ++ + arch/arm/mach-bcm2708/include/mach/hardware.h | 28 + + arch/arm/mach-bcm2708/include/mach/io.h | 27 + + arch/arm/mach-bcm2708/include/mach/irqs.h | 196 ++++++ + arch/arm/mach-bcm2708/include/mach/memory.h | 57 ++ + arch/arm/mach-bcm2708/include/mach/platform.h | 228 +++++++ + arch/arm/mach-bcm2708/include/mach/system.h | 38 ++ + arch/arm/mach-bcm2708/include/mach/timex.h | 23 + + arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++ + arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 + + arch/arm/mach-bcm2709/Kconfig | 42 ++ + arch/arm/mach-bcm2709/Makefile | 6 + + arch/arm/mach-bcm2709/Makefile.boot | 3 + + arch/arm/mach-bcm2709/armctrl.c | 361 ++++++++++ + arch/arm/mach-bcm2709/armctrl.h | 27 + + arch/arm/mach-bcm2709/bcm2708_gpio.c | 426 ++++++++++++ + arch/arm/mach-bcm2709/bcm2709.c | 801 +++++++++++++++++++++++ + arch/arm/mach-bcm2709/bcm2709.h | 49 ++ + arch/arm/mach-bcm2709/delay.S | 21 + + arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 ++++++++++++++ + arch/arm/mach-bcm2709/include/mach/barriers.h | 3 + + arch/arm/mach-bcm2709/include/mach/clkdev.h | 7 + + arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 + + arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 ++++ + arch/arm/mach-bcm2709/include/mach/frc.h | 38 ++ + arch/arm/mach-bcm2709/include/mach/gpio.h | 17 + + arch/arm/mach-bcm2709/include/mach/hardware.h | 28 + + arch/arm/mach-bcm2709/include/mach/io.h | 27 + + arch/arm/mach-bcm2709/include/mach/irqs.h | 225 +++++++ + arch/arm/mach-bcm2709/include/mach/memory.h | 57 ++ + arch/arm/mach-bcm2709/include/mach/platform.h | 225 +++++++ + arch/arm/mach-bcm2709/include/mach/system.h | 38 ++ + arch/arm/mach-bcm2709/include/mach/timex.h | 23 + + arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 +++ + arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 + + arch/arm/mach-bcm2709/include/mach/vc_support.h | 69 ++ + arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 + + arch/arm/mach-bcm2709/vc_mem.c | 431 ++++++++++++ + arch/arm/mach-bcm2709/vc_support.c | 318 +++++++++ + arch/arm/mm/Kconfig | 2 +- + arch/arm/mm/proc-v6.S | 15 +- + arch/arm/mm/proc-v7.S | 1 + + arch/arm/tools/mach-types | 2 + + drivers/clocksource/arm_arch_timer.c | 36 + + drivers/tty/serial/amba-pl011.c | 2 +- + include/linux/mmc/host.h | 1 + + 62 files changed, 6436 insertions(+), 5 deletions(-) + create mode 100644 arch/arm/mach-bcm2708/Kconfig + create mode 100644 arch/arm/mach-bcm2708/Makefile + create mode 100644 arch/arm/mach-bcm2708/Makefile.boot + create mode 100644 arch/arm/mach-bcm2708/armctrl.c + create mode 100644 arch/arm/mach-bcm2708/armctrl.h + create mode 100644 arch/arm/mach-bcm2708/bcm2708.c + create mode 100644 arch/arm/mach-bcm2708/bcm2708.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S + create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S + create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h + create mode 100644 arch/arm/mach-bcm2709/Kconfig + create mode 100644 arch/arm/mach-bcm2709/Makefile + create mode 100644 arch/arm/mach-bcm2709/Makefile.boot + create mode 100644 arch/arm/mach-bcm2709/armctrl.c + create mode 100644 arch/arm/mach-bcm2709/armctrl.h + create mode 100644 arch/arm/mach-bcm2709/bcm2708_gpio.c + create mode 100644 arch/arm/mach-bcm2709/bcm2709.c + create mode 100644 arch/arm/mach-bcm2709/bcm2709.h + create mode 100644 arch/arm/mach-bcm2709/delay.S + create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/barriers.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/clkdev.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S + create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S + create mode 100644 arch/arm/mach-bcm2709/include/mach/frc.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/gpio.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/timex.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/uncompress.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/vc_mem.h + create mode 100755 arch/arm/mach-bcm2709/include/mach/vc_support.h + create mode 100644 arch/arm/mach-bcm2709/include/mach/vmalloc.h + create mode 100644 arch/arm/mach-bcm2709/vc_mem.c + create mode 100644 arch/arm/mach-bcm2709/vc_support.c + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -314,6 +314,42 @@ choice + default ARCH_VERSATILE if !MMU + default ARCH_MULTIPLATFORM if MMU + ++config ARCH_BCM2708 ++ bool "Broadcom BCM2708 family" ++ select CPU_V6 ++ select ARM_AMBA ++ select HAVE_SCHED_CLOCK ++ select NEED_MACH_GPIO_H ++ select NEED_MACH_MEMORY_H ++ select COMMON_CLK ++ select ARCH_HAS_CPUFREQ ++ select GENERIC_CLOCKEVENTS ++ select ARM_ERRATA_411920 ++ select MACH_BCM2708 ++ select VC4 ++ select FIQ ++ help ++ This enables support for Broadcom BCM2708 boards. ++ ++config ARCH_BCM2709 ++ bool "Broadcom BCM2709 family" ++ select ARCH_HAS_BARRIERS if SMP ++ select CPU_V7 ++ select HAVE_SMP ++ select ARM_AMBA ++ select MIGHT_HAVE_CACHE_L2X0 ++ select HAVE_SCHED_CLOCK ++ select NEED_MACH_MEMORY_H ++ select NEED_MACH_IO_H ++ select COMMON_CLK ++ select ARCH_HAS_CPUFREQ ++ select GENERIC_CLOCKEVENTS ++ select MACH_BCM2709 ++ select VC4 ++ select FIQ ++ help ++ This enables support for Broadcom BCM2709 boards. ++ + config ARCH_MULTIPLATFORM + bool "Allow multiple platforms to be selected" + depends on MMU +@@ -824,6 +860,9 @@ config ARCH_VIRT + # Kconfigs may be included either alphabetically (according to the + # plat- suffix) or along side the corresponding mach-* source. + # ++source "arch/arm/mach-bcm2708/Kconfig" ++source "arch/arm/mach-bcm2709/Kconfig" ++ + source "arch/arm/mach-mvebu/Kconfig" + + source "arch/arm/mach-alpine/Kconfig" +--- a/arch/arm/Kconfig.debug ++++ b/arch/arm/Kconfig.debug +@@ -1197,6 +1197,14 @@ choice + options; the platform specific options are deprecated + and will be soon removed. + ++ config DEBUG_BCM2708_UART0 ++ bool "Broadcom BCM2708 UART0 (PL011)" ++ depends on MACH_BCM2708 ++ help ++ Say Y here if you want the debug print routines to direct ++ their output to UART 0. The port must have been initialised ++ by the boot-loader before use. ++ + endchoice + + config DEBUG_AT91_UART +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -155,6 +155,8 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080 + + # Machine directory name. This list is sorted alphanumerically + # by CONFIG_* macro name. ++machine-$(CONFIG_ARCH_BCM2708) += bcm2708 ++machine-$(CONFIG_ARCH_BCM2709) += bcm2709 + machine-$(CONFIG_ARCH_ALPINE) += alpine + machine-$(CONFIG_ARCH_AT91) += at91 + machine-$(CONFIG_ARCH_AXXIA) += axxia +--- a/arch/arm/kernel/head.S ++++ b/arch/arm/kernel/head.S +@@ -680,6 +680,14 @@ ARM_BE8(rev16 ip, ip) + ldrcc r7, [r4], #4 @ use branch for delay slot + bcc 1b + ret lr ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop + #endif + ENDPROC(__fixup_a_pv_table) + +--- a/arch/arm/kernel/process.c ++++ b/arch/arm/kernel/process.c +@@ -98,6 +98,16 @@ void arch_cpu_idle_dead(void) + } + #endif + ++char bcm2708_reboot_mode = 'h'; ++ ++int __init reboot_setup(char *str) ++{ ++ bcm2708_reboot_mode = str[0]; ++ return 1; ++} ++ ++__setup("reboot=", reboot_setup); ++ + void __show_regs(struct pt_regs *regs) + { + unsigned long flags; +--- /dev/null ++++ b/arch/arm/mach-bcm2708/Kconfig +@@ -0,0 +1,30 @@ ++menu "Broadcom BCM2708 Implementations" ++ depends on ARCH_BCM2708 ++ ++config MACH_BCM2708 ++ bool "Broadcom BCM2708 Development Platform" ++ select NEED_MACH_MEMORY_H ++ select NEED_MACH_IO_H ++ select CPU_V6 ++ help ++ Include support for the Broadcom(R) BCM2708 platform. ++ ++config BCM2708_DT ++ bool "BCM2708 Device Tree support" ++ depends on MACH_BCM2708 ++ default n ++ select USE_OF ++ select ARCH_REQUIRE_GPIOLIB ++ select PINCTRL ++ select PINCTRL_BCM2835 ++ help ++ Enable Device Tree support for BCM2708 ++ ++config BCM2708_NOL2CACHE ++ bool "Videocore L2 cache disable" ++ depends on MACH_BCM2708 ++ default n ++ help ++ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. ++ ++endmenu +--- /dev/null ++++ b/arch/arm/mach-bcm2708/Makefile +@@ -0,0 +1,5 @@ ++# ++# Makefile for the linux kernel. ++# ++ ++obj-$(CONFIG_MACH_BCM2708) += bcm2708.o armctrl.o +--- /dev/null ++++ b/arch/arm/mach-bcm2708/Makefile.boot +@@ -0,0 +1,3 @@ ++ zreladdr-y := 0x00008000 ++params_phys-y := 0x00000100 ++initrd_phys-y := 0x00800000 +--- /dev/null ++++ b/arch/arm/mach-bcm2708/armctrl.c +@@ -0,0 +1,304 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "armctrl.h" ++ ++/* For support of kernels >= 3.0 assume only one VIC for now*/ ++static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { ++ INTERRUPT_VC_JPEG, ++ INTERRUPT_VC_USB, ++ INTERRUPT_VC_3D, ++ INTERRUPT_VC_DMA2, ++ INTERRUPT_VC_DMA3, ++ INTERRUPT_VC_I2C, ++ INTERRUPT_VC_SPI, ++ INTERRUPT_VC_I2SPCM, ++ INTERRUPT_VC_SDIO, ++ INTERRUPT_VC_UART, ++ INTERRUPT_VC_ARASANSDIO ++}; ++ ++static void armctrl_mask_irq(struct irq_data *d) ++{ ++ static const unsigned int disables[4] = { ++ ARM_IRQ_DIBL1, ++ ARM_IRQ_DIBL2, ++ ARM_IRQ_DIBL3, ++ 0 ++ }; ++ ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); ++} ++ ++static void armctrl_unmask_irq(struct irq_data *d) ++{ ++ static const unsigned int enables[4] = { ++ ARM_IRQ_ENBL1, ++ ARM_IRQ_ENBL2, ++ ARM_IRQ_ENBL3, ++ 0 ++ }; ++ ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); ++} ++ ++#ifdef CONFIG_OF ++ ++#define NR_IRQS_BANK0 21 ++#define NR_BANKS 3 ++#define IRQS_PER_BANK 32 ++ ++/* from drivers/irqchip/irq-bcm2835.c */ ++static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, ++ const u32 *intspec, unsigned int intsize, ++ unsigned long *out_hwirq, unsigned int *out_type) ++{ ++ if (WARN_ON(intsize != 2)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] >= NR_BANKS)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) ++ return -EINVAL; ++ ++ if (intspec[0] == 0) ++ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; ++ else if (intspec[0] == 1) ++ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; ++ else ++ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; ++ ++ /* reverse remap_irqs[] */ ++ switch (*out_hwirq) { ++ case INTERRUPT_VC_JPEG: ++ *out_hwirq = INTERRUPT_JPEG; ++ break; ++ case INTERRUPT_VC_USB: ++ *out_hwirq = INTERRUPT_USB; ++ break; ++ case INTERRUPT_VC_3D: ++ *out_hwirq = INTERRUPT_3D; ++ break; ++ case INTERRUPT_VC_DMA2: ++ *out_hwirq = INTERRUPT_DMA2; ++ break; ++ case INTERRUPT_VC_DMA3: ++ *out_hwirq = INTERRUPT_DMA3; ++ break; ++ case INTERRUPT_VC_I2C: ++ *out_hwirq = INTERRUPT_I2C; ++ break; ++ case INTERRUPT_VC_SPI: ++ *out_hwirq = INTERRUPT_SPI; ++ break; ++ case INTERRUPT_VC_I2SPCM: ++ *out_hwirq = INTERRUPT_I2SPCM; ++ break; ++ case INTERRUPT_VC_SDIO: ++ *out_hwirq = INTERRUPT_SDIO; ++ break; ++ case INTERRUPT_VC_UART: ++ *out_hwirq = INTERRUPT_UART; ++ break; ++ case INTERRUPT_VC_ARASANSDIO: ++ *out_hwirq = INTERRUPT_ARASANSDIO; ++ break; ++ } ++ ++ *out_type = IRQ_TYPE_NONE; ++ return 0; ++} ++ ++static struct irq_domain_ops armctrl_ops = { ++ .xlate = armctrl_xlate ++}; ++ ++void __init armctrl_dt_init(void) ++{ ++ struct device_node *np; ++ struct irq_domain *domain; ++ ++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); ++ if (!np) ++ return; ++ ++ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, ++ IRQ_ARMCTRL_START, 0, ++ &armctrl_ops, NULL); ++ WARN_ON(!domain); ++} ++#else ++void __init armctrl_dt_init(void) { } ++#endif /* CONFIG_OF */ ++ ++#if defined(CONFIG_PM) ++ ++/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ ++ ++/* Static defines ++ * struct armctrl_device - VIC PM device (< 3.xx) ++ * @sysdev: The system device which is registered. (< 3.xx) ++ * @irq: The IRQ number for the base of the VIC. ++ * @base: The register base for the VIC. ++ * @resume_sources: A bitmask of interrupts for resume. ++ * @resume_irqs: The IRQs enabled for resume. ++ * @int_select: Save for VIC_INT_SELECT. ++ * @int_enable: Save for VIC_INT_ENABLE. ++ * @soft_int: Save for VIC_INT_SOFT. ++ * @protect: Save for VIC_PROTECT. ++ */ ++struct armctrl_info { ++ void __iomem *base; ++ int irq; ++ u32 resume_sources; ++ u32 resume_irqs; ++ u32 int_select; ++ u32 int_enable; ++ u32 soft_int; ++ u32 protect; ++} armctrl; ++ ++static int armctrl_suspend(void) ++{ ++ return 0; ++} ++ ++static void armctrl_resume(void) ++{ ++ return; ++} ++ ++/** ++ * armctrl_pm_register - Register a VIC for later power management control ++ * @base: The base address of the VIC. ++ * @irq: The base IRQ for the VIC. ++ * @resume_sources: bitmask of interrupts allowed for resume sources. ++ * ++ * For older kernels (< 3.xx) do - ++ * Register the VIC with the system device tree so that it can be notified ++ * of suspend and resume requests and ensure that the correct actions are ++ * taken to re-instate the settings on resume. ++ */ ++static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 resume_sources) ++{ ++ armctrl.base = base; ++ armctrl.resume_sources = resume_sources; ++ armctrl.irq = irq; ++} ++ ++static int armctrl_set_wake(struct irq_data *d, unsigned int on) ++{ ++ unsigned int off = d->irq & 31; ++ u32 bit = 1 << off; ++ ++ if (!(bit & armctrl.resume_sources)) ++ return -EINVAL; ++ ++ if (on) ++ armctrl.resume_irqs |= bit; ++ else ++ armctrl.resume_irqs &= ~bit; ++ ++ return 0; ++} ++ ++#else ++static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 arg1) ++{ ++} ++ ++#define armctrl_suspend NULL ++#define armctrl_resume NULL ++#define armctrl_set_wake NULL ++#endif /* CONFIG_PM */ ++ ++static struct syscore_ops armctrl_syscore_ops = { ++ .suspend = armctrl_suspend, ++ .resume = armctrl_resume, ++}; ++ ++/** ++ * armctrl_syscore_init - initicall to register VIC pm functions ++ * ++ * This is called via late_initcall() to register ++ * the resources for the VICs due to the early ++ * nature of the VIC's registration. ++*/ ++static int __init armctrl_syscore_init(void) ++{ ++ register_syscore_ops(&armctrl_syscore_ops); ++ return 0; ++} ++ ++late_initcall(armctrl_syscore_init); ++ ++static struct irq_chip armctrl_chip = { ++ .name = "ARMCTRL", ++ .irq_ack = NULL, ++ .irq_mask = armctrl_mask_irq, ++ .irq_unmask = armctrl_unmask_irq, ++ .irq_set_wake = armctrl_set_wake, ++}; ++ ++/** ++ * armctrl_init - initialise a vectored interrupt controller ++ * @base: iomem base address ++ * @irq_start: starting interrupt number, must be muliple of 32 ++ * @armctrl_sources: bitmask of interrupt sources to allow ++ * @resume_sources: bitmask of interrupt sources to allow for resume ++ */ ++int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources) ++{ ++ unsigned int irq; ++ ++ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { ++ unsigned int data = irq; ++ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) ++ data = remap_irqs[irq - INTERRUPT_JPEG]; ++ ++ irq_set_chip(irq, &armctrl_chip); ++ irq_set_chip_data(irq, (void *)data); ++ irq_set_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ ++ armctrl_pm_register(base, irq_start, resume_sources); ++ armctrl_dt_init(); ++ return 0; ++} +--- /dev/null ++++ b/arch/arm/mach-bcm2708/armctrl.h +@@ -0,0 +1,27 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARMCTRL_H ++#define __BCM2708_ARMCTRL_H ++ ++extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources); ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -0,0 +1,622 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "bcm2708.h" ++#include "armctrl.h" ++ ++#ifdef CONFIG_BCM_VC_CMA ++#include ++#endif ++ ++ ++/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to ++ * give us IO access only to 64Mbytes of physical memory (26 bits). We could ++ * represent this window by setting our dmamasks to 26 bits but, in fact ++ * we're not going to use addresses outside this range (they're not in real ++ * memory) so we don't bother. ++ * ++ * In the future we might include code to use this IOMMU to remap other ++ * physical addresses onto VideoCore memory then the use of 32-bits would be ++ * more legitimate. ++ */ ++#define DMA_MASK_BITS_COMMON 32 ++ ++/* command line parameters */ ++static unsigned boardrev, serial; ++static unsigned uart_clock = UART0_CLOCK; ++static unsigned disk_led_gpio = 16; ++static unsigned disk_led_active_low = 1; ++static unsigned reboot_part = 0; ++ ++static unsigned use_dt = 0; ++ ++static void __init bcm2708_init_led(void); ++ ++void __init bcm2708_init_irq(void) ++{ ++ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); ++} ++ ++static struct map_desc bcm2708_io_desc[] __initdata = { ++ { ++ .virtual = IO_ADDRESS(ARMCTRL_BASE), ++ .pfn = __phys_to_pfn(ARMCTRL_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART0_BASE), ++ .pfn = __phys_to_pfn(UART0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART1_BASE), ++ .pfn = __phys_to_pfn(UART1_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(DMA_BASE), ++ .pfn = __phys_to_pfn(DMA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(MCORE_BASE), ++ .pfn = __phys_to_pfn(MCORE_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(ST_BASE), ++ .pfn = __phys_to_pfn(ST_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(USB_BASE), ++ .pfn = __phys_to_pfn(USB_BASE), ++ .length = SZ_128K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(PM_BASE), ++ .pfn = __phys_to_pfn(PM_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(GPIO_BASE), ++ .pfn = __phys_to_pfn(GPIO_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE} ++}; ++ ++void __init bcm2708_map_io(void) ++{ ++ iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc)); ++} ++ ++/* The STC is a free running counter that increments at the rate of 1MHz */ ++#define STC_FREQ_HZ 1000000 ++ ++static inline uint32_t timer_read(void) ++{ ++ /* STC: a free running counter that increments at the rate of 1MHz */ ++ return readl(__io_address(ST_BASE + 0x04)); ++} ++ ++static unsigned long bcm2708_read_current_timer(void) ++{ ++ return timer_read(); ++} ++ ++static u64 notrace bcm2708_read_sched_clock(void) ++{ ++ return timer_read(); ++} ++ ++static cycle_t clksrc_read(struct clocksource *cs) ++{ ++ return timer_read(); ++} ++ ++static struct clocksource clocksource_stc = { ++ .name = "stc", ++ .rating = 300, ++ .read = clksrc_read, ++ .mask = CLOCKSOURCE_MASK(32), ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++unsigned long frc_clock_ticks32(void) ++{ ++ return timer_read(); ++} ++ ++static void __init bcm2708_clocksource_init(void) ++{ ++ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { ++ printk(KERN_ERR "timer: failed to initialize clock " ++ "source %s\n", clocksource_stc.name); ++ } ++} ++ ++struct clk __init *bcm2708_clk_register(const char *name, unsigned long fixed_rate) ++{ ++ struct clk *clk; ++ ++ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, ++ fixed_rate); ++ if (IS_ERR(clk)) ++ pr_err("%s not registered\n", name); ++ ++ return clk; ++} ++ ++void __init bcm2708_register_clkdev(struct clk *clk, const char *name) ++{ ++ int ret; ++ ++ ret = clk_register_clkdev(clk, NULL, name); ++ if (ret) ++ pr_err("%s alias not registered\n", name); ++} ++ ++void __init bcm2708_init_clocks(void) ++{ ++ struct clk *clk; ++ ++ clk = bcm2708_clk_register("uart0_clk", uart_clock); ++ bcm2708_register_clkdev(clk, "dev:f1"); ++ ++ clk = bcm2708_clk_register("sdhost_clk", 250000000); ++ bcm2708_register_clkdev(clk, "mmc-bcm2835.0"); ++ bcm2708_register_clkdev(clk, "bcm2708_spi.0"); ++ bcm2708_register_clkdev(clk, "bcm2708_i2c.0"); ++ bcm2708_register_clkdev(clk, "bcm2708_i2c.1"); ++} ++ ++#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ } ++#define UART0_DMA { 15, 14 } ++ ++AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); ++ ++static struct amba_device *amba_devs[] __initdata = { ++ &uart0_device, ++}; ++ ++static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_fb_device = { ++ .name = "bcm2708_fb", ++ .id = -1, /* only one bcm2708_fb */ ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .dma_mask = &fb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_usb_resources[] = { ++ [0] = { ++ .start = USB_BASE, ++ .end = USB_BASE + SZ_128K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_USB, ++ .end = IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_usb_device = { ++ .name = "bcm2708_usb", ++ .id = -1, /* only one bcm2708_usb */ ++ .resource = bcm2708_usb_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_usb_resources), ++ .dev = { ++ .dma_mask = &usb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_vcio_resources[] = { ++ { ++ .start = ARMCTRL_0_MAIL0_BASE, ++ .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_ARM_MAILBOX, ++ .end = IRQ_ARM_MAILBOX, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vcio_device = { ++ .name = "bcm2708_vcio", ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_vcio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), ++ .dev = { ++ .dma_mask = &vcio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++int __init bcm_register_device(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = platform_device_register(pdev); ++ if (ret) ++ pr_debug("Unable to register platform device '%s': %d\n", ++ pdev->name, ret); ++ ++ return ret; ++} ++ ++/* ++ * Use these macros for platform and i2c devices that are present in the ++ * Device Tree. This way the devices are only added on non-DT systems. ++ */ ++#define bcm_register_device_dt(pdev) \ ++ if (!use_dt) bcm_register_device(pdev) ++ ++#define i2c_register_board_info_dt(busnum, info, n) \ ++ if (!use_dt) i2c_register_board_info(busnum, info, n) ++ ++int calc_rsts(int partition) ++{ ++ return PM_PASSWORD | ++ ((partition & (1 << 0)) << 0) | ++ ((partition & (1 << 1)) << 1) | ++ ((partition & (1 << 2)) << 2) | ++ ((partition & (1 << 3)) << 3) | ++ ((partition & (1 << 4)) << 4) | ++ ((partition & (1 << 5)) << 5); ++} ++ ++static void bcm2708_restart(enum reboot_mode mode, const char *cmd) ++{ ++ extern char bcm2708_reboot_mode; ++ uint32_t pm_rstc, pm_wdog; ++ uint32_t timeout = 10; ++ uint32_t pm_rsts = 0; ++ ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < 1.3 booting with reboot=q ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; ++ } ++ else if(bcm2708_reboot_mode == 'p') ++ { ++ // NOOBS < 1.3 halting ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET; ++ } ++ else ++ { ++ pm_rsts = calc_rsts(reboot_part); ++ } ++ ++ writel(pm_rsts, __io_address(PM_RSTS)); ++ ++ /* Setup watchdog for reset */ ++ pm_rstc = readl(__io_address(PM_RSTC)); ++ ++ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) ++ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; ++ ++ writel(pm_wdog, __io_address(PM_WDOG)); ++ writel(pm_rstc, __io_address(PM_RSTC)); ++} ++ ++/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ ++static void bcm2708_power_off(void) ++{ ++ extern char bcm2708_reboot_mode; ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < v1.3 ++ bcm2708_restart('p', ""); ++ } ++ else ++ { ++ /* partition 63 is special code for HALT the bootloader knows not to boot*/ ++ reboot_part = 63; ++ /* continue with normal reset mechanism */ ++ bcm2708_restart(0, ""); ++ } ++} ++ ++static void __init bcm2708_init_uart1(void) ++{ ++ struct device_node *np; ++ ++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart"); ++ if (of_device_is_available(np)) { ++ pr_info("bcm2708: Mini UART enabled\n"); ++ writel(1, __io_address(UART1_BASE + 0x4)); ++ } ++} ++ ++#ifdef CONFIG_OF ++static void __init bcm2708_dt_init(void) ++{ ++ int ret; ++ ++ of_clk_init(NULL); ++ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++ if (ret) { ++ pr_err("of_platform_populate failed: %d\n", ret); ++ /* Proceed as if CONFIG_OF was not defined */ ++ } else { ++ use_dt = 1; ++ } ++} ++#else ++static void __init bcm2708_dt_init(void) { } ++#endif /* CONFIG_OF */ ++ ++void __init bcm2708_init(void) ++{ ++ int i; ++ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_early_init(); ++#endif ++ printk("bcm2708.uart_clock = %d\n", uart_clock); ++ pm_power_off = bcm2708_power_off; ++ ++ bcm2708_init_clocks(); ++ bcm2708_dt_init(); ++ ++ bcm_register_device(&bcm2708_vcio_device); ++#ifdef CONFIG_BCM2708_GPIO ++ bcm_register_device_dt(&bcm2708_gpio_device); ++#endif ++ bcm_register_device_dt(&bcm2708_fb_device); ++ bcm_register_device_dt(&bcm2708_usb_device); ++ ++ bcm2708_init_led(); ++ bcm2708_init_uart1(); ++ ++ if (!use_dt) { ++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { ++ struct amba_device *d = amba_devs[i]; ++ amba_device_register(d, &iomem_resource); ++ } ++ } ++ system_rev = boardrev; ++ system_serial_low = serial; ++} ++ ++static void timer_set_mode(enum clock_event_mode mode, ++ struct clock_event_device *clk) ++{ ++ switch (mode) { ++ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ break; ++ case CLOCK_EVT_MODE_PERIODIC: ++ ++ case CLOCK_EVT_MODE_UNUSED: ++ case CLOCK_EVT_MODE_RESUME: ++ ++ default: ++ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", ++ (int)mode); ++ break; ++ } ++ ++} ++ ++static int timer_set_next_event(unsigned long cycles, ++ struct clock_event_device *unused) ++{ ++ unsigned long stc; ++ do { ++ stc = readl(__io_address(ST_BASE + 0x04)); ++ /* We could take a FIQ here, which may push ST above STC3 */ ++ writel(stc + cycles, __io_address(ST_BASE + 0x18)); ++ } while ((signed long) cycles >= 0 && ++ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) ++ >= (signed long) cycles); ++ return 0; ++} ++ ++static struct clock_event_device timer0_clockevent = { ++ .name = "timer0", ++ .shift = 32, ++ .features = CLOCK_EVT_FEAT_ONESHOT, ++ .set_mode = timer_set_mode, ++ .set_next_event = timer_set_next_event, ++}; ++ ++/* ++ * IRQ handler for the timer ++ */ ++static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id) ++{ ++ struct clock_event_device *evt = &timer0_clockevent; ++ ++ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ ++ ++ evt->event_handler(evt); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction bcm2708_timer_irq = { ++ .name = "BCM2708 Timer Tick", ++ .flags = IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = bcm2708_timer_interrupt, ++}; ++ ++/* ++ * Set up timer interrupt, and return the current time in seconds. ++ */ ++ ++static struct delay_timer bcm2708_delay_timer = { ++ .read_current_timer = bcm2708_read_current_timer, ++ .freq = STC_FREQ_HZ, ++}; ++ ++static void __init bcm2708_timer_init(void) ++{ ++ /* init high res timer */ ++ bcm2708_clocksource_init(); ++ ++ /* ++ * Make irqs happen for the system timer ++ */ ++ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); ++ ++ sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ); ++ ++ timer0_clockevent.mult = ++ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); ++ timer0_clockevent.max_delta_ns = ++ clockevent_delta2ns(0xffffffff, &timer0_clockevent); ++ timer0_clockevent.min_delta_ns = ++ clockevent_delta2ns(0xf, &timer0_clockevent); ++ ++ timer0_clockevent.cpumask = cpumask_of(0); ++ clockevents_register_device(&timer0_clockevent); ++ ++ register_current_timer_delay(&bcm2708_delay_timer); ++} ++ ++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) ++#include ++ ++static struct gpio_led bcm2708_leds[] = { ++ [0] = { ++ .gpio = 16, ++ .name = "led0", ++ .default_trigger = "mmc0", ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_led_platform_data bcm2708_led_pdata = { ++ .num_leds = ARRAY_SIZE(bcm2708_leds), ++ .leds = bcm2708_leds, ++}; ++ ++static struct platform_device bcm2708_led_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm2708_led_pdata, ++ }, ++}; ++ ++static void __init bcm2708_init_led(void) ++{ ++ bcm2708_leds[0].gpio = disk_led_gpio; ++ bcm2708_leds[0].active_low = disk_led_active_low; ++ bcm_register_device_dt(&bcm2708_led_device); ++} ++#else ++static inline void bcm2708_init_led(void) ++{ ++} ++#endif ++ ++void __init bcm2708_init_early(void) ++{ ++ /* ++ * Some devices allocate their coherent buffers from atomic ++ * context. Increase size of atomic coherent pool to make sure such ++ * the allocations won't fail. ++ */ ++ init_dma_coherent_pool_size(SZ_4M); ++} ++ ++static void __init board_reserve(void) ++{ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_reserve(); ++#endif ++} ++ ++static const char * const bcm2708_compat[] = { ++ "brcm,bcm2708", ++ NULL ++}; ++ ++MACHINE_START(BCM2708, "BCM2708") ++ /* Maintainer: Broadcom Europe Ltd. */ ++ .map_io = bcm2708_map_io, ++ .init_irq = bcm2708_init_irq, ++ .init_time = bcm2708_timer_init, ++ .init_machine = bcm2708_init, ++ .init_early = bcm2708_init_early, ++ .reserve = board_reserve, ++ .restart = bcm2708_restart, ++ .dt_compat = bcm2708_compat, ++MACHINE_END ++ ++module_param(boardrev, uint, 0644); ++module_param(serial, uint, 0644); ++module_param(uart_clock, uint, 0644); ++module_param(disk_led_gpio, uint, 0644); ++module_param(disk_led_active_low, uint, 0644); ++module_param(reboot_part, uint, 0644); +--- /dev/null ++++ b/arch/arm/mach-bcm2708/bcm2708.h +@@ -0,0 +1,49 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708.h ++ * ++ * BCM2708 machine support header ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_BCM2708_H ++#define __BCM2708_BCM2708_H ++ ++#include ++ ++extern void __init bcm2708_init(void); ++extern void __init bcm2708_init_irq(void); ++extern void __init bcm2708_map_io(void); ++extern struct sys_timer bcm2708_timer; ++extern unsigned int mmc_status(struct device *dev); ++ ++#define AMBA_DEVICE(name, busid, base, plat) \ ++static struct amba_device name##_device = { \ ++ .dev = { \ ++ .coherent_dma_mask = ~0, \ ++ .init_name = busid, \ ++ .platform_data = plat, \ ++ }, \ ++ .res = { \ ++ .start = base##_BASE, \ ++ .end = (base##_BASE) + SZ_4K - 1,\ ++ .flags = IORESOURCE_MEM, \ ++ }, \ ++ .irq = base##_IRQ, \ ++} ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h +@@ -0,0 +1,419 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/arm_control.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARM_CONTROL_H ++#define __BCM2708_ARM_CONTROL_H ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define ARM_BASE 0x7E00B000 ++ ++/* Basic configuration */ ++#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) ++#define ARM_C0_SIZ128M 0x00000000 ++#define ARM_C0_SIZ256M 0x00000001 ++#define ARM_C0_SIZ512M 0x00000002 ++#define ARM_C0_SIZ1G 0x00000003 ++#define ARM_C0_BRESP0 0x00000000 ++#define ARM_C0_BRESP1 0x00000004 ++#define ARM_C0_BRESP2 0x00000008 ++#define ARM_C0_BOOTHI 0x00000010 ++#define ARM_C0_UNUSED05 0x00000020 /* free */ ++#define ARM_C0_FULLPERI 0x00000040 ++#define ARM_C0_UNUSED78 0x00000180 /* free */ ++#define ARM_C0_JTAGMASK 0x00000E00 ++#define ARM_C0_JTAGOFF 0x00000000 ++#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ ++#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ ++#define ARM_C0_APROTMSK 0x0000F000 ++#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ ++#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ ++#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ ++#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ ++#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ ++#define ARM_C0_PRIO_L2 0x0F000000 ++#define ARM_C0_PRIO_UC 0xF0000000 ++ ++#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ ++#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ ++#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ ++ ++ ++#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) ++#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ ++#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ ++#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ ++#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ ++#define ARM_C1_PERSON 0x00000100 /* peripherals on */ ++#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ ++ ++#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) ++#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ ++#define ARM_S_READPEND 0x000003FF /* pending reads counter */ ++#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ ++ ++#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) ++#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ ++#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ ++#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ ++#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ ++#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ ++#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ ++ ++#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) ++#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) ++#define ARM_IDVAL 0x364D5241 ++ ++/* Translation memory */ ++#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) ++/* 32 locations: 0x100.. 0x17F */ ++/* 32 spare means we CAN go to 64 pages.... */ ++ ++ ++/* Interrupts */ ++#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ ++#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ ++#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ ++#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ ++ ++#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ ++/* todo: all I1_interrupt sources */ ++#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ ++/* todo: all I2_interrupt sources */ ++ ++#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ ++#define ARM_IF_INDEX 0x0000007F /* FIQ select */ ++#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ ++#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ ++#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ ++#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ ++#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ ++#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ ++#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ ++#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ ++#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ ++ ++#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ ++#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ ++#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ ++#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ ++#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ ++#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ ++#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ ++#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ ++#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ ++#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ ++ ++/* Timer */ ++/* For reg. fields see sp804 spec. */ ++#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) ++#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) ++#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) ++#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) ++#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) ++#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) ++#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) ++#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) ++#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) ++ ++#define TIMER_CTRL_ONESHOT (1 << 0) ++#define TIMER_CTRL_32BIT (1 << 1) ++#define TIMER_CTRL_DIV1 (0 << 2) ++#define TIMER_CTRL_DIV16 (1 << 2) ++#define TIMER_CTRL_DIV256 (2 << 2) ++#define TIMER_CTRL_IE (1 << 5) ++#define TIMER_CTRL_PERIODIC (1 << 6) ++#define TIMER_CTRL_ENABLE (1 << 7) ++#define TIMER_CTRL_DBGHALT (1 << 8) ++#define TIMER_CTRL_ENAFREE (1 << 9) ++#define TIMER_CTRL_FREEDIV_SHIFT 16) ++#define TIMER_CTRL_FREEDIV_MASK 0xff ++ ++/* Semaphores, Doorbells, Mailboxes */ ++#define ARM_SBM_OWN0 (ARM_BASE+0x800) ++#define ARM_SBM_OWN1 (ARM_BASE+0x900) ++#define ARM_SBM_OWN2 (ARM_BASE+0xA00) ++#define ARM_SBM_OWN3 (ARM_BASE+0xB00) ++ ++/* MAILBOXES ++ * Register flags are common across all ++ * owner registers. See end of this section ++ * ++ * Semaphores, Doorbells, Mailboxes Owner 0 ++ * ++ */ ++ ++#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) ++#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) ++#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) ++#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) ++#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) ++#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) ++#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) ++#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) ++#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) ++#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) ++#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Some addresses should ONLY be used by owner 0 */ ++#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ ++#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ ++#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ ++#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ ++#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ ++#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ ++/* MAILBOX 1 access in Owner 0 area */ ++/* Owner 0 should only WRITE to this mailbox */ ++#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ ++/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ ++#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ ++#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ ++#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 1 */ ++#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) ++#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) ++#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) ++#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) ++#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) ++#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) ++#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) ++#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) ++#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) ++#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) ++#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Owner 1 should only WRITE to this mailbox */ ++#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ ++/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 0 area */ ++#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ ++#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ ++#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ ++#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ ++#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ ++#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ ++#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ ++#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ ++#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 2 */ ++#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) ++#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) ++#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) ++#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) ++#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) ++#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) ++#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) ++#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) ++#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) ++#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) ++#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) ++/* MAILBOX 0 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ ++/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ ++/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ ++#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ ++#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ ++#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 3 */ ++#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) ++#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) ++#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) ++#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) ++#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) ++#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) ++#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) ++#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) ++#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) ++#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) ++#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) ++/* MAILBOX 0 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ ++/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ ++/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ ++#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ ++#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ ++#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ ++ ++ ++ ++/* Mailbox flags. Valid for all owners */ ++ ++/* Mailbox status register (...0x98) */ ++#define ARM_MS_FULL 0x80000000 ++#define ARM_MS_EMPTY 0x40000000 ++#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ ++ ++/* MAILBOX config/status register (...0x9C) */ ++/* ANY write to this register clears the error bits! */ ++#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ ++#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ ++#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ ++#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ ++#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ ++#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ ++#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ ++/* Bit 7 is unused */ ++#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ ++#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ ++#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ ++ ++/* Semaphore clear/debug register (...0xE0) */ ++#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ ++#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ ++#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ ++#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ ++#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ ++#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ ++#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ ++#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ ++#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ ++#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ ++#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ ++#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ ++#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ ++#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ ++#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ ++#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ ++ ++/* Doorbells clear/debug register (...0xE4) */ ++#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ ++#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ ++#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ ++#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ ++#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ ++#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ ++#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ ++#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ ++ ++/* MY IRQS register (...0xF8) */ ++#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ ++#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ ++ ++/* ALL IRQS register (...0xF8) */ ++#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ ++#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ ++#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ ++#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ ++#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ ++#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ ++#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ ++#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ ++#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ ++#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ ++/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ ++/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ ++/* */ ++/* ARM JTAG BASH */ ++/* */ ++#define AJB_BASE 0x7e2000c0 ++ ++#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) ++#define AJB_BITS0 0x000000 ++#define AJB_BITS4 0x000004 ++#define AJB_BITS8 0x000008 ++#define AJB_BITS12 0x00000C ++#define AJB_BITS16 0x000010 ++#define AJB_BITS20 0x000014 ++#define AJB_BITS24 0x000018 ++#define AJB_BITS28 0x00001C ++#define AJB_BITS32 0x000020 ++#define AJB_BITS34 0x000022 ++#define AJB_OUT_MS 0x000040 ++#define AJB_OUT_LS 0x000000 ++#define AJB_INV_CLK 0x000080 ++#define AJB_D0_RISE 0x000100 ++#define AJB_D0_FALL 0x000000 ++#define AJB_D1_RISE 0x000200 ++#define AJB_D1_FALL 0x000000 ++#define AJB_IN_RISE 0x000400 ++#define AJB_IN_FALL 0x000000 ++#define AJB_ENABLE 0x000800 ++#define AJB_HOLD0 0x000000 ++#define AJB_HOLD1 0x001000 ++#define AJB_HOLD2 0x002000 ++#define AJB_HOLD3 0x003000 ++#define AJB_RESETN 0x004000 ++#define AJB_CLKSHFT 16 ++#define AJB_BUSY 0x80000000 ++#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) ++#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) ++#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h +@@ -0,0 +1,7 @@ ++#ifndef __ASM_MACH_CLKDEV_H ++#define __ASM_MACH_CLKDEV_H ++ ++#define __clk_get(clk) ({ 1; }) ++#define __clk_put(clk) do { } while (0) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S +@@ -0,0 +1,22 @@ ++/* arch/arm/mach-bcm2708/include/mach/debug-macro.S ++ * ++ * Debugging macro include header ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 1994-1999 Russell King ++ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++ ++ .macro addruart, rp, rv, tmp ++ ldr \rp, =UART0_BASE ++ ldr \rv, =IO_ADDRESS(UART0_BASE) ++ .endm ++ ++#include +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S +@@ -0,0 +1,69 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/entry-macro.S ++ * ++ * Low-level IRQ helper macros for BCM2708 platforms ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ /* get masked status */ ++ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] ++ mov \irqnr, #(ARM_IRQ0_BASE + 31) ++ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 ++ /* clear bits 8 and 9, and test */ ++ bics \irqstat, \irqstat, #0x300 ++ bne 1010f ++ ++ tst \tmp, #0x100 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ1_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) ++ bicne \irqstat, #((1<<18) | (1<<19)) ++ bne 1010f ++ ++ tst \tmp, #0x200 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ2_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) ++ bicne \irqstat, #((1<<30)) ++ beq 1020f ++ ++1010: ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ @ N.B. CLZ is an ARM5 instruction. ++ sub \tmp, \irqstat, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++ ++1020: @ EQ will be set if no irqs pending ++ ++ .endm +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/frc.h +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 free running counter (timer) ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _MACH_FRC_H ++#define _MACH_FRC_H ++ ++#define FRC_TICK_RATE (1000000) ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ (slightly faster than frc_clock_ticks63() ++ */ ++extern unsigned long frc_clock_ticks32(void); ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ * Note - top bit should be ignored (see cnt32_to_63) ++ */ ++extern unsigned long long frc_clock_ticks63(void); ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/hardware.h +@@ -0,0 +1,28 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/hardware.h ++ * ++ * This file contains the hardware definitions of the BCM2708 devices. ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H ++ ++#include ++#include ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/io.h +@@ -0,0 +1,27 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/io.h ++ * ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARM_ARCH_IO_H ++#define __ASM_ARM_ARCH_IO_H ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#define __io(a) __typesafe_io(a) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/irqs.h +@@ -0,0 +1,196 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/irqs.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_IRQS_H_ ++#define _BCM2708_IRQS_H_ ++ ++#include ++ ++/* ++ * IRQ interrupts definitions are the same as the INT definitions ++ * held within platform.h ++ */ ++#define IRQ_ARMCTRL_START 0 ++#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) ++#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) ++#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) ++#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) ++#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) ++#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) ++#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) ++#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) ++#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) ++#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) ++#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) ++#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) ++#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) ++#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) ++#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) ++#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) ++#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) ++#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) ++#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) ++#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) ++#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) ++#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) ++#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) ++#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) ++#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) ++#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) ++#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) ++#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) ++#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) ++#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) ++#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) ++#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) ++#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) ++#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) ++#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) ++#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) ++#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) ++#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) ++#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) ++#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) ++#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) ++#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) ++#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) ++#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) ++#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) ++#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) ++#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) ++#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) ++#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) ++#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) ++#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) ++#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) ++#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) ++#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) ++#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) ++#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) ++#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) ++#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) ++#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) ++#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) ++#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) ++#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) ++#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) ++#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) ++ ++#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) ++#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) ++#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) ++#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) ++#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) ++#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) ++#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) ++#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) ++#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) ++#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) ++ ++/* ++ * FIQ interrupts definitions are the same as the INT definitions. ++ */ ++#define FIQ_TIMER0 INT_TIMER0 ++#define FIQ_TIMER1 INT_TIMER1 ++#define FIQ_TIMER2 INT_TIMER2 ++#define FIQ_TIMER3 INT_TIMER3 ++#define FIQ_CODEC0 INT_CODEC0 ++#define FIQ_CODEC1 INT_CODEC1 ++#define FIQ_CODEC2 INT_CODEC2 ++#define FIQ_JPEG INT_JPEG ++#define FIQ_ISP INT_ISP ++#define FIQ_USB INT_USB ++#define FIQ_3D INT_3D ++#define FIQ_TRANSPOSER INT_TRANSPOSER ++#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0 ++#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1 ++#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2 ++#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3 ++#define FIQ_DMA0 INT_DMA0 ++#define FIQ_DMA1 INT_DMA1 ++#define FIQ_DMA2 INT_DMA2 ++#define FIQ_DMA3 INT_DMA3 ++#define FIQ_DMA4 INT_DMA4 ++#define FIQ_DMA5 INT_DMA5 ++#define FIQ_DMA6 INT_DMA6 ++#define FIQ_DMA7 INT_DMA7 ++#define FIQ_DMA8 INT_DMA8 ++#define FIQ_DMA9 INT_DMA9 ++#define FIQ_DMA10 INT_DMA10 ++#define FIQ_DMA11 INT_DMA11 ++#define FIQ_DMA12 INT_DMA12 ++#define FIQ_AUX INT_AUX ++#define FIQ_ARM INT_ARM ++#define FIQ_VPUDMA INT_VPUDMA ++#define FIQ_HOSTPORT INT_HOSTPORT ++#define FIQ_VIDEOSCALER INT_VIDEOSCALER ++#define FIQ_CCP2TX INT_CCP2TX ++#define FIQ_SDC INT_SDC ++#define FIQ_DSI0 INT_DSI0 ++#define FIQ_AVE INT_AVE ++#define FIQ_CAM0 INT_CAM0 ++#define FIQ_CAM1 INT_CAM1 ++#define FIQ_HDMI0 INT_HDMI0 ++#define FIQ_HDMI1 INT_HDMI1 ++#define FIQ_PIXELVALVE1 INT_PIXELVALVE1 ++#define FIQ_I2CSPISLV INT_I2CSPISLV ++#define FIQ_DSI1 INT_DSI1 ++#define FIQ_PWA0 INT_PWA0 ++#define FIQ_PWA1 INT_PWA1 ++#define FIQ_CPR INT_CPR ++#define FIQ_SMI INT_SMI ++#define FIQ_GPIO0 INT_GPIO0 ++#define FIQ_GPIO1 INT_GPIO1 ++#define FIQ_GPIO2 INT_GPIO2 ++#define FIQ_GPIO3 INT_GPIO3 ++#define FIQ_I2C INT_I2C ++#define FIQ_SPI INT_SPI ++#define FIQ_I2SPCM INT_I2SPCM ++#define FIQ_SDIO INT_SDIO ++#define FIQ_UART INT_UART ++#define FIQ_SLIMBUS INT_SLIMBUS ++#define FIQ_VEC INT_VEC ++#define FIQ_CPG INT_CPG ++#define FIQ_RNG INT_RNG ++#define FIQ_ARASANSDIO INT_ARASANSDIO ++#define FIQ_AVSPMON INT_AVSPMON ++ ++#define FIQ_ARM_TIMER INT_ARM_TIMER ++#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX ++#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0 ++#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1 ++#define FIQ_VPU0_HALTED INT_VPU0_HALTED ++#define FIQ_VPU1_HALTED INT_VPU1_HALTED ++#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0 ++#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1 ++#define FIQ_PENDING1 INT_PENDING1 ++#define FIQ_PENDING2 INT_PENDING2 ++ ++#define HARD_IRQS (64 + 21) ++#define GPIO_IRQ_START (HARD_IRQS) ++#define GPIO_IRQS (32*5) ++#define SPARE_ALLOC_IRQS 64 ++#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) ++#define FREE_IRQS 128 ++#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) ++ ++#endif /* _BCM2708_IRQS_H_ */ +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/memory.h +@@ -0,0 +1,57 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/memory.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++/* Memory overview: ++ ++ [ARMcore] <--virtual addr--> ++ [ARMmmu] <--physical addr--> ++ [GERTmap] <--bus add--> ++ [VCperiph] ++ ++*/ ++ ++/* ++ * Physical DRAM offset. ++ */ ++#define BCM_PLAT_PHYS_OFFSET UL(0x00000000) ++#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ ++ ++#ifdef CONFIG_BCM2708_NOL2CACHE ++ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ ++#else ++ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ ++#endif ++ ++/* We're using the memory at 64M in the VideoCore for Linux - this adjustment ++ * will provide the offset into this area as well as setting the bits that ++ * stop the L1 and L2 cache from being used ++ * ++ * WARNING: this only works because the ARM is given memory at a fixed location ++ * (ARMMEM_OFFSET) ++ */ ++#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET) ++#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) ++#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) ++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/platform.h +@@ -0,0 +1,228 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/platform.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_PLATFORM_H ++#define _BCM2708_PLATFORM_H ++ ++ ++/* macros to get at IO space when running virtually */ ++#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) ++ ++#define __io_address(n) IOMEM(IO_ADDRESS(n)) ++ ++ ++/* ++ * SDRAM ++ */ ++#define BCM2708_SDRAM_BASE 0x00000000 ++ ++/* ++ * Logic expansion modules ++ * ++ */ ++ ++ ++/* ------------------------------------------------------------------------ ++ * BCM2708 ARMCTRL Registers ++ * ------------------------------------------------------------------------ ++ */ ++ ++#define HW_REGISTER_RW(addr) (addr) ++#define HW_REGISTER_RO(addr) (addr) ++ ++#include "arm_control.h" ++#undef ARM_BASE ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define BCM2708_PERI_BASE 0x20000000 ++#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) ++#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ ++#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ ++#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ ++#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ ++#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ ++#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ ++#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ ++#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ ++#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ ++#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ ++#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */ ++#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ ++#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ ++#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ ++#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ ++#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ ++#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ ++#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ ++#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ ++ ++#define ARMCTRL_BASE (ARM_BASE + 0x000) ++#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ ++#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ ++#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ ++ ++ ++/* ++ * Interrupt assignments ++ */ ++ ++#define ARM_IRQ1_BASE 0 ++#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) ++#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) ++#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) ++#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) ++#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) ++#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) ++#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) ++#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) ++#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) ++#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) ++#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) ++#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) ++#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) ++#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) ++#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) ++#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) ++#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) ++#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) ++#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) ++#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) ++#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) ++#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) ++#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) ++#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) ++#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) ++#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) ++#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) ++#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) ++#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) ++#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) ++#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) ++#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) ++ ++#define ARM_IRQ2_BASE 32 ++#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) ++#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) ++#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) ++#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) ++#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) ++#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) ++#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) ++#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) ++#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) ++#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) ++#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) ++#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) ++#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) ++#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) ++#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) ++#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) ++#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) ++#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) ++#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) ++#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) ++#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) ++#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) ++#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) ++#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) ++#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) ++#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) ++#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) ++#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) ++#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) ++#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) ++#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) ++#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) ++ ++#define ARM_IRQ0_BASE 64 ++#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) ++#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) ++#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) ++#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) ++#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) ++#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) ++#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) ++#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) ++#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) ++#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) ++#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) ++#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) ++#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) ++#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) ++#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) ++#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) ++#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) ++#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) ++#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) ++#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) ++#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) ++ ++#define MAXIRQNUM (32 + 32 + 20) ++#define MAXFIQNUM (32 + 32 + 20) ++ ++#define MAX_TIMER 2 ++#define MAX_PERIOD 699050 ++#define TICKS_PER_uSEC 1 ++ ++/* ++ * These are useconds NOT ticks. ++ * ++ */ ++#define mSEC_1 1000 ++#define mSEC_5 (mSEC_1 * 5) ++#define mSEC_10 (mSEC_1 * 10) ++#define mSEC_25 (mSEC_1 * 25) ++#define SEC_1 (mSEC_1 * 1000) ++ ++/* ++ * Watchdog ++ */ ++#define PM_RSTC (PM_BASE+0x1c) ++#define PM_RSTS (PM_BASE+0x20) ++#define PM_WDOG (PM_BASE+0x24) ++ ++#define PM_WDOG_RESET 0000000000 ++#define PM_PASSWORD 0x5a000000 ++#define PM_WDOG_TIME_SET 0x000fffff ++#define PM_RSTC_WRCFG_CLR 0xffffffcf ++#define PM_RSTC_WRCFG_SET 0x00000030 ++#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 ++#define PM_RSTC_RESET 0x00000102 ++ ++#define PM_RSTS_HADPOR_SET 0x00001000 ++#define PM_RSTS_HADSRH_SET 0x00000400 ++#define PM_RSTS_HADSRF_SET 0x00000200 ++#define PM_RSTS_HADSRQ_SET 0x00000100 ++#define PM_RSTS_HADWRH_SET 0x00000040 ++#define PM_RSTS_HADWRF_SET 0x00000020 ++#define PM_RSTS_HADWRQ_SET 0x00000010 ++#define PM_RSTS_HADDRH_SET 0x00000004 ++#define PM_RSTS_HADDRF_SET 0x00000002 ++#define PM_RSTS_HADDRQ_SET 0x00000001 ++ ++#define UART0_CLOCK 3000000 ++ ++#endif ++ ++/* END */ +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/system.h +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/system.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H ++ ++#include ++#include ++#include ++ ++static inline void arch_idle(void) ++{ ++ /* ++ * This should do all the clock switching ++ * and wait for interrupt tricks ++ */ ++ cpu_do_idle(); ++} ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/timex.h +@@ -0,0 +1,23 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 sysem clock frequency ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#define CLOCK_TICK_RATE (1000000) +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h +@@ -0,0 +1,84 @@ ++/* ++ * arch/arm/mach-bcn2708/include/mach/uncompress.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#define UART_BAUD 115200 ++ ++#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR) ++#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR) ++#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD) ++#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD) ++#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH) ++#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR) ++ ++/* ++ * This does not append a newline ++ */ ++static inline void putc(int c) ++{ ++ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF) ++ barrier(); ++ ++ __raw_writel(c, BCM2708_UART_DR); ++} ++ ++static inline void flush(void) ++{ ++ int fr; ++ ++ do { ++ fr = __raw_readl(BCM2708_UART_FR); ++ barrier(); ++ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); ++} ++ ++static inline void arch_decomp_setup(void) ++{ ++ int temp, div, rem, frac; ++ ++ temp = 16 * UART_BAUD; ++ div = UART0_CLOCK / temp; ++ rem = UART0_CLOCK % temp; ++ temp = (8 * rem) / UART_BAUD; ++ frac = (temp >> 1) + (temp & 1); ++ ++ /* Make sure the UART is disabled before we start */ ++ __raw_writel(0, BCM2708_UART_CR); ++ ++ /* Set the baud rate */ ++ __raw_writel(div, BCM2708_UART_IBRD); ++ __raw_writel(frac, BCM2708_UART_FBRD); ++ ++ /* Set the UART to 8n1, FIFO enabled */ ++ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH); ++ ++ /* Enable the UART */ ++ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE, ++ BCM2708_UART_CR); ++} ++ ++/* ++ * nothing to do ++ */ ++#define arch_decomp_wdog() +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h +@@ -0,0 +1,20 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/vmalloc.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#define VMALLOC_END (0xe8000000) +--- /dev/null ++++ b/arch/arm/mach-bcm2709/Kconfig +@@ -0,0 +1,42 @@ ++menu "Broadcom BCM2709 Implementations" ++ depends on ARCH_BCM2709 ++ ++config MACH_BCM2709 ++ bool "Broadcom BCM2709 Development Platform" ++ help ++ Include support for the Broadcom(R) BCM2709 platform. ++ ++config BCM2709_DT ++ bool "BCM2709 Device Tree support" ++ depends on MACH_BCM2709 ++ default n ++ select USE_OF ++ select ARCH_REQUIRE_GPIOLIB ++ select PINCTRL ++ select PINCTRL_BCM2835 ++ help ++ Enable Device Tree support for BCM2709 ++ ++config BCM2708_GPIO ++ bool "BCM2709 gpio support" ++ depends on MACH_BCM2709 ++ select ARCH_REQUIRE_GPIOLIB ++ default y ++ help ++ Include support for the Broadcom(R) BCM2709 gpio. ++ ++config BCM2708_NOL2CACHE ++ bool "Videocore L2 cache disable" ++ depends on MACH_BCM2709 ++ default y ++ help ++ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. ++ ++config BCM2708_SPIDEV ++ bool "Bind spidev to SPI0 master" ++ depends on MACH_BCM2709 ++ depends on SPI ++ default y ++ help ++ Binds spidev driver to the SPI0 master ++endmenu +--- /dev/null ++++ b/arch/arm/mach-bcm2709/Makefile +@@ -0,0 +1,6 @@ ++# ++# Makefile for the linux kernel. ++# ++ ++obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o ++obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o +--- /dev/null ++++ b/arch/arm/mach-bcm2709/Makefile.boot +@@ -0,0 +1,3 @@ ++ zreladdr-y := 0x00008000 ++params_phys-y := 0x00000100 ++initrd_phys-y := 0x00800000 +--- /dev/null ++++ b/arch/arm/mach-bcm2709/armctrl.c +@@ -0,0 +1,361 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "armctrl.h" ++ ++/* For support of kernels >= 3.0 assume only one VIC for now*/ ++static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { ++ INTERRUPT_VC_JPEG, ++ INTERRUPT_VC_USB, ++ INTERRUPT_VC_3D, ++ INTERRUPT_VC_DMA2, ++ INTERRUPT_VC_DMA3, ++ INTERRUPT_VC_I2C, ++ INTERRUPT_VC_SPI, ++ INTERRUPT_VC_I2SPCM, ++ INTERRUPT_VC_SDIO, ++ INTERRUPT_VC_UART, ++ INTERRUPT_VC_ARASANSDIO ++}; ++ ++static void armctrl_mask_irq(struct irq_data *d) ++{ ++ static const unsigned int disables[4] = { ++ ARM_IRQ_DIBL1, ++ ARM_IRQ_DIBL2, ++ ARM_IRQ_DIBL3, ++ 0 ++ }; ++ int i; ++ if (d->irq >= FIQ_START) { ++ writel(0, __io_address(ARM_IRQ_FAST)); ++ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { ++#if 1 ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; ++ for (i=0; i<4; i++) // i = raw_smp_processor_id(); // ++ { ++ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); ++ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); ++ } ++#endif ++ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { ++#if 0 ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; ++ for (i=0; i<4; i++) { ++ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); ++ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); ++ } ++#endif ++ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); ++ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { ++ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); ++ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } ++} ++ ++static void armctrl_unmask_irq(struct irq_data *d) ++{ ++ static const unsigned int enables[4] = { ++ ARM_IRQ_ENBL1, ++ ARM_IRQ_ENBL2, ++ ARM_IRQ_ENBL3, ++ 0 ++ }; ++ int i; ++ if (d->irq >= FIQ_START) { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; ++ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); ++ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { ++#if 1 ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; ++ for (i=0; i<4; i++) // i = raw_smp_processor_id(); ++ { ++ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); ++ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); ++ } ++#endif ++ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { ++#if 0 ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; ++ for (i=0; i<4; i++) { ++ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); ++ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); ++ } ++#endif ++ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); ++ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { ++ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); ++ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } ++} ++ ++#ifdef CONFIG_OF ++ ++#define NR_IRQS_BANK0 21 ++#define NR_BANKS 4 ++#define IRQS_PER_BANK 32 ++ ++/* from drivers/irqchip/irq-bcm2835.c */ ++static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, ++ const u32 *intspec, unsigned int intsize, ++ unsigned long *out_hwirq, unsigned int *out_type) ++{ ++ if (WARN_ON(intsize != 2)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] >= NR_BANKS)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) ++ return -EINVAL; ++ ++ if (intspec[0] == 0) ++ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; ++ else if (intspec[0] == 1) ++ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; ++ else if (intspec[0] == 2) ++ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; ++ else ++ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; ++ ++ /* reverse remap_irqs[] */ ++ switch (*out_hwirq) { ++ case INTERRUPT_VC_JPEG: ++ *out_hwirq = INTERRUPT_JPEG; ++ break; ++ case INTERRUPT_VC_USB: ++ *out_hwirq = INTERRUPT_USB; ++ break; ++ case INTERRUPT_VC_3D: ++ *out_hwirq = INTERRUPT_3D; ++ break; ++ case INTERRUPT_VC_DMA2: ++ *out_hwirq = INTERRUPT_DMA2; ++ break; ++ case INTERRUPT_VC_DMA3: ++ *out_hwirq = INTERRUPT_DMA3; ++ break; ++ case INTERRUPT_VC_I2C: ++ *out_hwirq = INTERRUPT_I2C; ++ break; ++ case INTERRUPT_VC_SPI: ++ *out_hwirq = INTERRUPT_SPI; ++ break; ++ case INTERRUPT_VC_I2SPCM: ++ *out_hwirq = INTERRUPT_I2SPCM; ++ break; ++ case INTERRUPT_VC_SDIO: ++ *out_hwirq = INTERRUPT_SDIO; ++ break; ++ case INTERRUPT_VC_UART: ++ *out_hwirq = INTERRUPT_UART; ++ break; ++ case INTERRUPT_VC_ARASANSDIO: ++ *out_hwirq = INTERRUPT_ARASANSDIO; ++ break; ++ } ++ ++ *out_type = IRQ_TYPE_NONE; ++ return 0; ++} ++ ++static struct irq_domain_ops armctrl_ops = { ++ .xlate = armctrl_xlate ++}; ++ ++void __init armctrl_dt_init(void) ++{ ++ struct device_node *np; ++ struct irq_domain *domain; ++ ++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); ++ if (!np) ++ return; ++ ++ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, ++ IRQ_ARMCTRL_START, 0, ++ &armctrl_ops, NULL); ++ WARN_ON(!domain); ++} ++#else ++void __init armctrl_dt_init(void) { } ++#endif /* CONFIG_OF */ ++ ++#if defined(CONFIG_PM) ++ ++/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ ++ ++/* Static defines ++ * struct armctrl_device - VIC PM device (< 3.xx) ++ * @sysdev: The system device which is registered. (< 3.xx) ++ * @irq: The IRQ number for the base of the VIC. ++ * @base: The register base for the VIC. ++ * @resume_sources: A bitmask of interrupts for resume. ++ * @resume_irqs: The IRQs enabled for resume. ++ * @int_select: Save for VIC_INT_SELECT. ++ * @int_enable: Save for VIC_INT_ENABLE. ++ * @soft_int: Save for VIC_INT_SOFT. ++ * @protect: Save for VIC_PROTECT. ++ */ ++struct armctrl_info { ++ void __iomem *base; ++ int irq; ++ u32 resume_sources; ++ u32 resume_irqs; ++ u32 int_select; ++ u32 int_enable; ++ u32 soft_int; ++ u32 protect; ++} armctrl; ++ ++static int armctrl_suspend(void) ++{ ++ return 0; ++} ++ ++static void armctrl_resume(void) ++{ ++ return; ++} ++ ++/** ++ * armctrl_pm_register - Register a VIC for later power management control ++ * @base: The base address of the VIC. ++ * @irq: The base IRQ for the VIC. ++ * @resume_sources: bitmask of interrupts allowed for resume sources. ++ * ++ * For older kernels (< 3.xx) do - ++ * Register the VIC with the system device tree so that it can be notified ++ * of suspend and resume requests and ensure that the correct actions are ++ * taken to re-instate the settings on resume. ++ */ ++static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 resume_sources) ++{ ++ armctrl.base = base; ++ armctrl.resume_sources = resume_sources; ++ armctrl.irq = irq; ++} ++ ++static int armctrl_set_wake(struct irq_data *d, unsigned int on) ++{ ++ unsigned int off = d->irq & 31; ++ u32 bit = 1 << off; ++ ++ if (!(bit & armctrl.resume_sources)) ++ return -EINVAL; ++ ++ if (on) ++ armctrl.resume_irqs |= bit; ++ else ++ armctrl.resume_irqs &= ~bit; ++ ++ return 0; ++} ++ ++#else ++static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 arg1) ++{ ++} ++ ++#define armctrl_suspend NULL ++#define armctrl_resume NULL ++#define armctrl_set_wake NULL ++#endif /* CONFIG_PM */ ++ ++static struct syscore_ops armctrl_syscore_ops = { ++ .suspend = armctrl_suspend, ++ .resume = armctrl_resume, ++}; ++ ++/** ++ * armctrl_syscore_init - initicall to register VIC pm functions ++ * ++ * This is called via late_initcall() to register ++ * the resources for the VICs due to the early ++ * nature of the VIC's registration. ++*/ ++static int __init armctrl_syscore_init(void) ++{ ++ register_syscore_ops(&armctrl_syscore_ops); ++ return 0; ++} ++ ++late_initcall(armctrl_syscore_init); ++ ++static struct irq_chip armctrl_chip = { ++ .name = "ARMCTRL", ++ .irq_ack = NULL, ++ .irq_mask = armctrl_mask_irq, ++ .irq_unmask = armctrl_unmask_irq, ++ .irq_set_wake = armctrl_set_wake, ++}; ++ ++/** ++ * armctrl_init - initialise a vectored interrupt controller ++ * @base: iomem base address ++ * @irq_start: starting interrupt number, must be muliple of 32 ++ * @armctrl_sources: bitmask of interrupt sources to allow ++ * @resume_sources: bitmask of interrupt sources to allow for resume ++ */ ++int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources) ++{ ++ unsigned int irq; ++ ++ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { ++ unsigned int data = irq; ++ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) ++ data = remap_irqs[irq - INTERRUPT_JPEG]; ++ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { ++ irq_set_percpu_devid(irq); ++ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); ++ } else { ++ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ irq_set_chip_data(irq, (void *)data); ++ } ++ ++ armctrl_pm_register(base, irq_start, resume_sources); ++ init_FIQ(FIQ_START); ++ armctrl_dt_init(); ++ return 0; ++} +--- /dev/null ++++ b/arch/arm/mach-bcm2709/armctrl.h +@@ -0,0 +1,27 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARMCTRL_H ++#define __BCM2708_ARMCTRL_H ++ ++extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources); ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/bcm2708_gpio.c +@@ -0,0 +1,426 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++#define DRIVER_NAME BCM_GPIO_DRIVER_NAME ++#define BCM_GPIO_USE_IRQ 1 ++ ++#define GPIOFSEL(x) (0x00+(x)*4) ++#define GPIOSET(x) (0x1c+(x)*4) ++#define GPIOCLR(x) (0x28+(x)*4) ++#define GPIOLEV(x) (0x34+(x)*4) ++#define GPIOEDS(x) (0x40+(x)*4) ++#define GPIOREN(x) (0x4c+(x)*4) ++#define GPIOFEN(x) (0x58+(x)*4) ++#define GPIOHEN(x) (0x64+(x)*4) ++#define GPIOLEN(x) (0x70+(x)*4) ++#define GPIOAREN(x) (0x7c+(x)*4) ++#define GPIOAFEN(x) (0x88+(x)*4) ++#define GPIOUD(x) (0x94+(x)*4) ++#define GPIOUDCLK(x) (0x98+(x)*4) ++ ++#define GPIO_BANKS 2 ++ ++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, ++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, ++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, ++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, ++}; ++ ++ /* Each of the two spinlocks protects a different set of hardware ++ * regiters and data structurs. This decouples the code of the IRQ from ++ * the GPIO code. This also makes the case of a GPIO routine call from ++ * the IRQ code simpler. ++ */ ++static DEFINE_SPINLOCK(lock); /* GPIO registers */ ++ ++struct bcm2708_gpio { ++ struct list_head list; ++ void __iomem *base; ++ struct gpio_chip gc; ++ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32]; ++}; ++ ++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, ++ int function) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned long flags; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++ ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= function << gpio_field_offset; ++ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); ++ spin_unlock_irqrestore(&lock, flags); ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ ++ return 0; ++} ++ ++static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) ++{ ++ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); ++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, ++ int value) ++{ ++ int ret; ++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); ++ if (ret >= 0) ++ bcm2708_gpio_set(gc, offset, value); ++ return ret; ++} ++ ++static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ unsigned lev; ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return 0; ++ lev = readl(gpio->base + GPIOLEV(gpio_bank)); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); ++ return 0x1 & (lev >> gpio_field_offset); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); ++ if (offset >= BCM2708_NR_GPIOS) ++ return; ++ if (value) ++ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); ++ else ++ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); ++} ++ ++/********************** ++ * extension to configure pullups ++ */ ++int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, ++ bcm2708_gpio_pull_t value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ switch (value) { ++ case BCM2708_PULL_UP: ++ writel(2, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_DOWN: ++ writel(1, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_OFF: ++ writel(0, gpio->base + GPIOUD(0)); ++ break; ++ } ++ ++ udelay(5); ++ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ udelay(5); ++ writel(0, gpio->base + GPIOUD(0)); ++ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcm2708_gpio_setpull); ++ ++/************************************************************************************************************************* ++ * bcm2708 GPIO IRQ ++ */ ++ ++#if BCM_GPIO_USE_IRQ ++ ++static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) ++{ ++ return gpio_to_irq(gpio); ++} ++ ++static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ ++ gpio->rising[gb] &= ~(1 << go); ++ gpio->falling[gb] &= ~(1 << go); ++ gpio->high[gb] &= ~(1 << go); ++ gpio->low[gb] &= ~(1 << go); ++ ++ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) ++ return -EINVAL; ++ ++ if (type & IRQ_TYPE_EDGE_RISING) ++ gpio->rising[gb] |= (1 << go); ++ if (type & IRQ_TYPE_EDGE_FALLING) ++ gpio->falling[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_HIGH) ++ gpio->high[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_LOW) ++ gpio->low[gb] |= (1 << go); ++ return 0; ++} ++ ++static void bcm2708_gpio_irq_mask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ gn = gn % 32; ++ ++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); ++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); ++ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); ++ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); ++} ++ ++static void bcm2708_gpio_irq_unmask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ if (gpio->rising[gb] & (1 << go)) { ++ writel(rising | (1 << go), gpio->base + GPIOREN(gb)); ++ } else { ++ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb)); ++ } ++ ++ if (gpio->falling[gb] & (1 << go)) { ++ writel(falling | (1 << go), gpio->base + GPIOFEN(gb)); ++ } else { ++ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb)); ++ } ++ ++ if (gpio->high[gb] & (1 << go)) { ++ writel(high | (1 << go), gpio->base + GPIOHEN(gb)); ++ } else { ++ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb)); ++ } ++ ++ if (gpio->low[gb] & (1 << go)) { ++ writel(low | (1 << go), gpio->base + GPIOLEN(gb)); ++ } else { ++ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb)); ++ } ++} ++ ++static struct irq_chip bcm2708_irqchip = { ++ .name = "GPIO", ++ .irq_enable = bcm2708_gpio_irq_unmask, ++ .irq_disable = bcm2708_gpio_irq_mask, ++ .irq_unmask = bcm2708_gpio_irq_unmask, ++ .irq_mask = bcm2708_gpio_irq_mask, ++ .irq_set_type = bcm2708_gpio_irq_set_type, ++}; ++ ++static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) ++{ ++ unsigned long edsr; ++ unsigned bank; ++ int i; ++ unsigned gpio; ++ unsigned level_bits; ++ struct bcm2708_gpio *gpio_data = dev_id; ++ ++ for (bank = 0; bank < GPIO_BANKS; bank++) { ++ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); ++ level_bits = gpio_data->high[bank] | gpio_data->low[bank]; ++ ++ for_each_set_bit(i, &edsr, 32) { ++ gpio = i + bank * 32; ++ /* ack edge triggered IRQs immediately */ ++ if (!(level_bits & (1<gc.to_irq = bcm2708_gpio_to_irq; ++ ++ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { ++ irq_set_chip_data(irq, ucb); ++ irq_set_chip_and_handler(irq, &bcm2708_irqchip, ++ handle_simple_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ bcm2708_gpio_irq.dev_id = ucb; ++ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); ++} ++ ++#else ++ ++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) ++{ ++} ++ ++#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ ++ ++static int bcm2708_gpio_probe(struct platform_device *dev) ++{ ++ struct bcm2708_gpio *ucb; ++ struct resource *res; ++ int bank; ++ int err = 0; ++ ++ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); ++ ++ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); ++ if (NULL == ucb) { ++ printk(KERN_ERR DRIVER_NAME ": failed to allocate " ++ "mailbox memory\n"); ++ err = -ENOMEM; ++ goto err; ++ } ++ ++ res = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ ++ platform_set_drvdata(dev, ucb); ++ ucb->base = __io_address(GPIO_BASE); ++ ++ ucb->gc.label = "bcm2708_gpio"; ++ ucb->gc.base = 0; ++ ucb->gc.ngpio = BCM2708_NR_GPIOS; ++ ucb->gc.owner = THIS_MODULE; ++ ++ ucb->gc.direction_input = bcm2708_gpio_dir_in; ++ ucb->gc.direction_output = bcm2708_gpio_dir_out; ++ ucb->gc.get = bcm2708_gpio_get; ++ ucb->gc.set = bcm2708_gpio_set; ++ ucb->gc.can_sleep = 0; ++ ++ for (bank = 0; bank < GPIO_BANKS; bank++) { ++ writel(0, ucb->base + GPIOREN(bank)); ++ writel(0, ucb->base + GPIOFEN(bank)); ++ writel(0, ucb->base + GPIOHEN(bank)); ++ writel(0, ucb->base + GPIOLEN(bank)); ++ writel(0, ucb->base + GPIOAREN(bank)); ++ writel(0, ucb->base + GPIOAFEN(bank)); ++ writel(~0, ucb->base + GPIOEDS(bank)); ++ } ++ ++ bcm2708_gpio_irq_init(ucb); ++ ++ err = gpiochip_add(&ucb->gc); ++ ++err: ++ return err; ++ ++} ++ ++static int bcm2708_gpio_remove(struct platform_device *dev) ++{ ++ int err = 0; ++ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); ++ ++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); ++ ++ gpiochip_remove(&ucb->gc); ++ ++ platform_set_drvdata(dev, NULL); ++ kfree(ucb); ++ ++ return err; ++} ++ ++static struct platform_driver bcm2708_gpio_driver = { ++ .probe = bcm2708_gpio_probe, ++ .remove = bcm2708_gpio_remove, ++ .driver = { ++ .name = "bcm2708_gpio"}, ++}; ++ ++static int __init bcm2708_gpio_init(void) ++{ ++ return platform_driver_register(&bcm2708_gpio_driver); ++} ++ ++static void __exit bcm2708_gpio_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_gpio_driver); ++} ++ ++module_init(bcm2708_gpio_init); ++module_exit(bcm2708_gpio_exit); ++ ++MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -0,0 +1,801 @@ ++/* ++ * linux/arch/arm/mach-bcm2709/bcm2709.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "bcm2709.h" ++#include "armctrl.h" ++ ++#ifdef CONFIG_BCM_VC_CMA ++#include ++#endif ++ ++//#define SYSTEM_TIMER ++ ++/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to ++ * give us IO access only to 64Mbytes of physical memory (26 bits). We could ++ * represent this window by setting our dmamasks to 26 bits but, in fact ++ * we're not going to use addresses outside this range (they're not in real ++ * memory) so we don't bother. ++ * ++ * In the future we might include code to use this IOMMU to remap other ++ * physical addresses onto VideoCore memory then the use of 32-bits would be ++ * more legitimate. ++ */ ++#define DMA_MASK_BITS_COMMON 32 ++ ++/* command line parameters */ ++static unsigned boardrev, serial; ++static unsigned uart_clock = UART0_CLOCK; ++static unsigned disk_led_gpio = 16; ++static unsigned disk_led_active_low = 1; ++static unsigned reboot_part = 0; ++ ++static unsigned use_dt = 0; ++ ++static void __init bcm2709_init_led(void); ++ ++void __init bcm2709_init_irq(void) ++{ ++ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); ++} ++ ++static struct map_desc bcm2709_io_desc[] __initdata = { ++ { ++ .virtual = IO_ADDRESS(ARMCTRL_BASE), ++ .pfn = __phys_to_pfn(ARMCTRL_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART0_BASE), ++ .pfn = __phys_to_pfn(UART0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART1_BASE), ++ .pfn = __phys_to_pfn(UART1_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(DMA_BASE), ++ .pfn = __phys_to_pfn(DMA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(MCORE_BASE), ++ .pfn = __phys_to_pfn(MCORE_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(ST_BASE), ++ .pfn = __phys_to_pfn(ST_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(USB_BASE), ++ .pfn = __phys_to_pfn(USB_BASE), ++ .length = SZ_128K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(PM_BASE), ++ .pfn = __phys_to_pfn(PM_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(GPIO_BASE), ++ .pfn = __phys_to_pfn(GPIO_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(ARM_LOCAL_BASE), ++ .pfn = __phys_to_pfn(ARM_LOCAL_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++}; ++ ++void __init bcm2709_map_io(void) ++{ ++ iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); ++} ++ ++#ifdef SYSTEM_TIMER ++ ++/* The STC is a free running counter that increments at the rate of 1MHz */ ++#define STC_FREQ_HZ 1000000 ++ ++static inline uint32_t timer_read(void) ++{ ++ /* STC: a free running counter that increments at the rate of 1MHz */ ++ return readl(__io_address(ST_BASE + 0x04)); ++} ++ ++static unsigned long bcm2709_read_current_timer(void) ++{ ++ return timer_read(); ++} ++ ++static u64 notrace bcm2709_read_sched_clock(void) ++{ ++ return timer_read(); ++} ++ ++static cycle_t clksrc_read(struct clocksource *cs) ++{ ++ return timer_read(); ++} ++ ++static struct clocksource clocksource_stc = { ++ .name = "stc", ++ .rating = 300, ++ .read = clksrc_read, ++ .mask = CLOCKSOURCE_MASK(32), ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++unsigned long frc_clock_ticks32(void) ++{ ++ return timer_read(); ++} ++ ++static void __init bcm2709_clocksource_init(void) ++{ ++ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { ++ printk(KERN_ERR "timer: failed to initialize clock " ++ "source %s\n", clocksource_stc.name); ++ } ++} ++#endif ++ ++struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate) ++{ ++ struct clk *clk; ++ ++ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, ++ fixed_rate); ++ if (IS_ERR(clk)) ++ pr_err("%s not registered\n", name); ++ ++ return clk; ++} ++ ++void __init bcm2709_register_clkdev(struct clk *clk, const char *name) ++{ ++ int ret; ++ ++ ret = clk_register_clkdev(clk, NULL, name); ++ if (ret) ++ pr_err("%s alias not registered\n", name); ++} ++ ++void __init bcm2709_init_clocks(void) ++{ ++ struct clk *clk; ++ ++ clk = bcm2709_clk_register("uart0_clk", uart_clock); ++ bcm2709_register_clkdev(clk, "dev:f1"); ++ ++ clk = bcm2709_clk_register("sdhost_clk", 250000000); ++ bcm2709_register_clkdev(clk, "mmc-bcm2835.0"); ++ bcm2709_register_clkdev(clk, "bcm2708_spi.0"); ++ bcm2709_register_clkdev(clk, "bcm2708_i2c.0"); ++ bcm2709_register_clkdev(clk, "bcm2708_i2c.1"); ++} ++ ++#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ } ++#define UART0_DMA { 15, 14 } ++ ++AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); ++ ++static struct amba_device *amba_devs[] __initdata = { ++ &uart0_device, ++}; ++ ++static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_fb_device = { ++ .name = "bcm2708_fb", ++ .id = -1, /* only one bcm2708_fb */ ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .dma_mask = &fb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_usb_resources[] = { ++ [0] = { ++ .start = USB_BASE, ++ .end = USB_BASE + SZ_128K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = MPHI_BASE, ++ .end = MPHI_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = IRQ_HOSTPORT, ++ .end = IRQ_HOSTPORT, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [3] = { ++ .start = IRQ_USB, ++ .end = IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [4] = { ++ .start = ARM_LOCAL_BASE, ++ .end = ARM_LOCAL_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [5] = { ++ .start = IRQ_ARM_LOCAL_MAILBOX1, ++ .end = IRQ_ARM_LOCAL_MAILBOX1, ++ .flags = IORESOURCE_IRQ ++ }, ++}; ++ ++ ++static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_usb_device = { ++ .name = "bcm2708_usb", ++ .id = -1, /* only one bcm2708_usb */ ++ .resource = bcm2708_usb_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_usb_resources), ++ .dev = { ++ .dma_mask = &usb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_vcio_resources[] = { ++ { ++ .start = ARMCTRL_0_MAIL0_BASE, ++ .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_ARM_MAILBOX, ++ .end = IRQ_ARM_MAILBOX, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vcio_device = { ++ .name = "bcm2708_vcio", ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_vcio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), ++ .dev = { ++ .dma_mask = &vcio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++int __init bcm_register_device(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = platform_device_register(pdev); ++ if (ret) ++ pr_debug("Unable to register platform device '%s': %d\n", ++ pdev->name, ret); ++ ++ return ret; ++} ++ ++/* ++ * Use these macros for platform and i2c devices that are present in the ++ * Device Tree. This way the devices are only added on non-DT systems. ++ */ ++#define bcm_register_device_dt(pdev) \ ++ if (!use_dt) bcm_register_device(pdev) ++ ++#define i2c_register_board_info_dt(busnum, info, n) \ ++ if (!use_dt) i2c_register_board_info(busnum, info, n) ++ ++int calc_rsts(int partition) ++{ ++ return PM_PASSWORD | ++ ((partition & (1 << 0)) << 0) | ++ ((partition & (1 << 1)) << 1) | ++ ((partition & (1 << 2)) << 2) | ++ ((partition & (1 << 3)) << 3) | ++ ((partition & (1 << 4)) << 4) | ++ ((partition & (1 << 5)) << 5); ++} ++ ++static void bcm2709_restart(enum reboot_mode mode, const char *cmd) ++{ ++ extern char bcm2708_reboot_mode; ++ uint32_t pm_rstc, pm_wdog; ++ uint32_t timeout = 10; ++ uint32_t pm_rsts = 0; ++ ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < 1.3 booting with reboot=q ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; ++ } ++ else if(bcm2708_reboot_mode == 'p') ++ { ++ // NOOBS < 1.3 halting ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET; ++ } ++ else ++ { ++ pm_rsts = calc_rsts(reboot_part); ++ } ++ ++ writel(pm_rsts, __io_address(PM_RSTS)); ++ ++ /* Setup watchdog for reset */ ++ pm_rstc = readl(__io_address(PM_RSTC)); ++ ++ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) ++ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; ++ ++ writel(pm_wdog, __io_address(PM_WDOG)); ++ writel(pm_rstc, __io_address(PM_RSTC)); ++} ++ ++/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ ++static void bcm2709_power_off(void) ++{ ++ extern char bcm2708_reboot_mode; ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < v1.3 ++ bcm2709_restart('p', ""); ++ } ++ else ++ { ++ /* partition 63 is special code for HALT the bootloader knows not to boot*/ ++ reboot_part = 63; ++ /* continue with normal reset mechanism */ ++ bcm2709_restart(0, ""); ++ } ++} ++ ++static void __init bcm2709_init_uart1(void) ++{ ++ struct device_node *np; ++ ++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart"); ++ if (of_device_is_available(np)) { ++ pr_info("bcm2709: Mini UART enabled\n"); ++ writel(1, __io_address(UART1_BASE + 0x4)); ++ } ++} ++ ++#ifdef CONFIG_OF ++static void __init bcm2709_dt_init(void) ++{ ++ int ret; ++ ++ of_clk_init(NULL); ++ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++ if (ret) { ++ pr_err("of_platform_populate failed: %d\n", ret); ++ /* Proceed as if CONFIG_OF was not defined */ ++ } else { ++ use_dt = 1; ++ } ++} ++#else ++static void __init bcm2709_dt_init(void) { } ++#endif /* CONFIG_OF */ ++ ++void __init bcm2709_init(void) ++{ ++ int i; ++ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_early_init(); ++#endif ++ printk("bcm2709.uart_clock = %d\n", uart_clock); ++ pm_power_off = bcm2709_power_off; ++ ++ bcm2709_init_clocks(); ++ bcm2709_dt_init(); ++ ++ bcm_register_device(&bcm2708_vcio_device); ++#ifdef CONFIG_BCM2708_GPIO ++ bcm_register_device_dt(&bcm2708_gpio_device); ++#endif ++ bcm_register_device_dt(&bcm2708_fb_device); ++ bcm_register_device_dt(&bcm2708_usb_device); ++ ++ bcm2708_init_led(); ++ bcm2708_init_uart1(); ++ ++ if (!use_dt) { ++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { ++ struct amba_device *d = amba_devs[i]; ++ amba_device_register(d, &iomem_resource); ++ } ++ } ++ system_rev = boardrev; ++ system_serial_low = serial; ++} ++ ++#ifdef SYSTEM_TIMER ++static void timer_set_mode(enum clock_event_mode mode, ++ struct clock_event_device *clk) ++{ ++ switch (mode) { ++ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ break; ++ case CLOCK_EVT_MODE_PERIODIC: ++ ++ case CLOCK_EVT_MODE_UNUSED: ++ case CLOCK_EVT_MODE_RESUME: ++ ++ default: ++ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", ++ (int)mode); ++ break; ++ } ++ ++} ++ ++static int timer_set_next_event(unsigned long cycles, ++ struct clock_event_device *unused) ++{ ++ unsigned long stc; ++ do { ++ stc = readl(__io_address(ST_BASE + 0x04)); ++ /* We could take a FIQ here, which may push ST above STC3 */ ++ writel(stc + cycles, __io_address(ST_BASE + 0x18)); ++ } while ((signed long) cycles >= 0 && ++ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) ++ >= (signed long) cycles); ++ return 0; ++} ++ ++static struct clock_event_device timer0_clockevent = { ++ .name = "timer0", ++ .shift = 32, ++ .features = CLOCK_EVT_FEAT_ONESHOT, ++ .set_mode = timer_set_mode, ++ .set_next_event = timer_set_next_event, ++}; ++ ++/* ++ * IRQ handler for the timer ++ */ ++static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) ++{ ++ struct clock_event_device *evt = &timer0_clockevent; ++ ++ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ ++ ++ evt->event_handler(evt); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction bcm2709_timer_irq = { ++ .name = "BCM2709 Timer Tick", ++ .flags = IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = bcm2709_timer_interrupt, ++}; ++ ++/* ++ * Set up timer interrupt, and return the current time in seconds. ++ */ ++ ++static struct delay_timer bcm2709_delay_timer = { ++ .read_current_timer = bcm2709_read_current_timer, ++ .freq = STC_FREQ_HZ, ++}; ++ ++static void __init bcm2709_timer_init(void) ++{ ++ /* init high res timer */ ++ bcm2709_clocksource_init(); ++ ++ /* ++ * Make irqs happen for the system timer ++ */ ++ setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); ++ ++ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); ++ ++ timer0_clockevent.mult = ++ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); ++ timer0_clockevent.max_delta_ns = ++ clockevent_delta2ns(0xffffffff, &timer0_clockevent); ++ timer0_clockevent.min_delta_ns = ++ clockevent_delta2ns(0xf, &timer0_clockevent); ++ ++ timer0_clockevent.cpumask = cpumask_of(0); ++ clockevents_register_device(&timer0_clockevent); ++ ++ register_current_timer_delay(&bcm2709_delay_timer); ++} ++ ++#else ++ ++static void __init bcm2709_timer_init(void) ++{ ++ extern void dc4_arch_timer_init(void); ++ // timer control ++ writel(0, __io_address(ARM_LOCAL_CONTROL)); ++ // timer pre_scaler ++ writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz ++ //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz ++ ++ if (use_dt) ++ { ++ of_clk_init(NULL); ++ clocksource_of_init(); ++ } ++ else ++ dc4_arch_timer_init(); ++} ++ ++#endif ++ ++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) ++#include ++ ++static struct gpio_led bcm2709_leds[] = { ++ [0] = { ++ .gpio = 16, ++ .name = "led0", ++ .default_trigger = "mmc0", ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_led_platform_data bcm2709_led_pdata = { ++ .num_leds = ARRAY_SIZE(bcm2709_leds), ++ .leds = bcm2709_leds, ++}; ++ ++static struct platform_device bcm2709_led_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm2709_led_pdata, ++ }, ++}; ++ ++static void __init bcm2709_init_led(void) ++{ ++ bcm2709_leds[0].gpio = disk_led_gpio; ++ bcm2709_leds[0].active_low = disk_led_active_low; ++ bcm_register_device_dt(&bcm2709_led_device); ++} ++#else ++static inline void bcm2709_init_led(void) ++{ ++} ++#endif ++ ++void __init bcm2709_init_early(void) ++{ ++ /* ++ * Some devices allocate their coherent buffers from atomic ++ * context. Increase size of atomic coherent pool to make sure such ++ * the allocations won't fail. ++ */ ++ init_dma_coherent_pool_size(SZ_4M); ++} ++ ++static void __init board_reserve(void) ++{ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_reserve(); ++#endif ++} ++ ++ ++#ifdef CONFIG_SMP ++#include ++ ++#include ++#include ++#include ++int dc4=0; ++//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); } ++void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); } ++ ++static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq) ++{ ++ int cpu; ++ /* ++ * Ensure that stores to Normal memory are visible to the ++ * other CPUs before issuing the IPI. ++ */ ++ dsb(); ++ ++ /* Convert our logical CPU mask into a physical one. */ ++ for_each_cpu(cpu, mask) ++ { ++ /* submit softirq */ ++ writel(1<%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10)); ++ printk("[%s] ncores=%d\n", __FUNCTION__, ncores); ++ ++ for (i = 0; i < ncores; i++) { ++ set_cpu_possible(i, true); ++ /* enable IRQ (not FIQ) */ ++ writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i)); ++ //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i)); ++ } ++ set_smp_cross_call(bcm2835_send_doorbell); ++} ++ ++/* ++ * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus) ++ */ ++void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ //void __iomem *scu_base; ++ ++ printk("[%s] enter\n", __FUNCTION__); ++ //scu_base = scu_base_addr(); ++ //scu_enable(scu_base); ++} ++ ++/* ++ * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void) ++ */ ++void __cpuinit bcm2709_secondary_init(unsigned int cpu) ++{ ++ printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu); ++ //gic_secondary_init(0); ++} ++ ++/* ++ * for linux/arch/arm/kernel/smp.c:__cpu_up(..) ++ */ ++int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ void secondary_startup(void); ++ void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)); ++ void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)); ++ unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup); ++ int timeout=20; ++ unsigned t = -1; ++ //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake)); ++ ++ dsb(); ++ BUG_ON(readl(mbox_clr) != 0); ++ writel(secondary_boot, mbox_set); ++ ++ while (--timeout > 0) { ++ t = readl(mbox_clr); ++ if (t == 0) break; ++ cpu_relax(); ++ } ++ if (timeout==0) ++ printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t); ++ else ++ printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout); ++ ++ return 0; ++} ++ ++ ++struct smp_operations bcm2709_smp_ops __initdata = { ++ .smp_init_cpus = bcm2709_smp_init_cpus, ++ .smp_prepare_cpus = bcm2709_smp_prepare_cpus, ++ .smp_secondary_init = bcm2709_secondary_init, ++ .smp_boot_secondary = bcm2709_boot_secondary, ++}; ++#endif ++ ++static const char * const bcm2709_compat[] = { ++ "brcm,bcm2709", ++ "brcm,bcm2708", /* Could use bcm2708 in a pinch */ ++ NULL ++}; ++ ++MACHINE_START(BCM2709, "BCM2709") ++ /* Maintainer: Broadcom Europe Ltd. */ ++#ifdef CONFIG_SMP ++ .smp = smp_ops(bcm2709_smp_ops), ++#endif ++ .map_io = bcm2709_map_io, ++ .init_irq = bcm2709_init_irq, ++ .init_time = bcm2709_timer_init, ++ .init_machine = bcm2709_init, ++ .init_early = bcm2709_init_early, ++ .reserve = board_reserve, ++ .restart = bcm2709_restart, ++ .dt_compat = bcm2709_compat, ++MACHINE_END ++ ++MACHINE_START(BCM2708, "BCM2709") ++ /* Maintainer: Broadcom Europe Ltd. */ ++#ifdef CONFIG_SMP ++ .smp = smp_ops(bcm2709_smp_ops), ++#endif ++ .map_io = bcm2709_map_io, ++ .init_irq = bcm2709_init_irq, ++ .init_time = bcm2709_timer_init, ++ .init_machine = bcm2709_init, ++ .init_early = bcm2709_init_early, ++ .reserve = board_reserve, ++ .restart = bcm2709_restart, ++ .dt_compat = bcm2709_compat, ++MACHINE_END ++ ++module_param(boardrev, uint, 0644); ++module_param(serial, uint, 0644); ++module_param(uart_clock, uint, 0644); ++module_param(disk_led_gpio, uint, 0644); ++module_param(disk_led_active_low, uint, 0644); ++module_param(reboot_part, uint, 0644); +--- /dev/null ++++ b/arch/arm/mach-bcm2709/bcm2709.h +@@ -0,0 +1,49 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708.h ++ * ++ * BCM2708 machine support header ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_BCM2708_H ++#define __BCM2708_BCM2708_H ++ ++#include ++ ++extern void __init bcm2708_init(void); ++extern void __init bcm2708_init_irq(void); ++extern void __init bcm2708_map_io(void); ++extern struct sys_timer bcm2708_timer; ++extern unsigned int mmc_status(struct device *dev); ++ ++#define AMBA_DEVICE(name, busid, base, plat) \ ++static struct amba_device name##_device = { \ ++ .dev = { \ ++ .coherent_dma_mask = ~0, \ ++ .init_name = busid, \ ++ .platform_data = plat, \ ++ }, \ ++ .res = { \ ++ .start = base##_BASE, \ ++ .end = (base##_BASE) + SZ_4K - 1,\ ++ .flags = IORESOURCE_MEM, \ ++ }, \ ++ .irq = base##_IRQ, \ ++} ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/delay.S +@@ -0,0 +1,21 @@ ++/* ++ * linux/arch/arm/lib/delay.S ++ * ++ * Copyright (C) 1995, 1996 Russell King ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++#include ++ ++ .text ++.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls ++@ Delay routine ++ENTRY(bcm2708_delay) ++ subs r0, r0, #1 ++ bhi bcm2708_delay ++ mov pc, lr ++ENDPROC(bcm2708_delay) +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/arm_control.h +@@ -0,0 +1,493 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/arm_control.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARM_CONTROL_H ++#define __BCM2708_ARM_CONTROL_H ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define ARM_BASE 0x7E00B000 ++ ++/* Basic configuration */ ++#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) ++#define ARM_C0_SIZ128M 0x00000000 ++#define ARM_C0_SIZ256M 0x00000001 ++#define ARM_C0_SIZ512M 0x00000002 ++#define ARM_C0_SIZ1G 0x00000003 ++#define ARM_C0_BRESP0 0x00000000 ++#define ARM_C0_BRESP1 0x00000004 ++#define ARM_C0_BRESP2 0x00000008 ++#define ARM_C0_BOOTHI 0x00000010 ++#define ARM_C0_UNUSED05 0x00000020 /* free */ ++#define ARM_C0_FULLPERI 0x00000040 ++#define ARM_C0_UNUSED78 0x00000180 /* free */ ++#define ARM_C0_JTAGMASK 0x00000E00 ++#define ARM_C0_JTAGOFF 0x00000000 ++#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ ++#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ ++#define ARM_C0_APROTMSK 0x0000F000 ++#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ ++#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ ++#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ ++#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ ++#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ ++#define ARM_C0_PRIO_L2 0x0F000000 ++#define ARM_C0_PRIO_UC 0xF0000000 ++ ++#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ ++#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ ++#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ ++ ++ ++#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) ++#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ ++#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ ++#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ ++#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ ++#define ARM_C1_PERSON 0x00000100 /* peripherals on */ ++#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ ++ ++#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) ++#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ ++#define ARM_S_READPEND 0x000003FF /* pending reads counter */ ++#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ ++ ++#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) ++#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ ++#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ ++#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ ++#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ ++#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ ++#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ ++ ++#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) ++#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) ++#define ARM_IDVAL 0x364D5241 ++ ++/* Translation memory */ ++#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) ++/* 32 locations: 0x100.. 0x17F */ ++/* 32 spare means we CAN go to 64 pages.... */ ++ ++ ++/* Interrupts */ ++#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ ++#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ ++#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ ++#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ ++ ++#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ ++/* todo: all I1_interrupt sources */ ++#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ ++/* todo: all I2_interrupt sources */ ++ ++#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ ++#define ARM_IF_INDEX 0x0000007F /* FIQ select */ ++#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ ++#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ ++#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ ++#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ ++#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ ++#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ ++#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ ++#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ ++#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ ++ ++#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ ++#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ ++#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ ++#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ ++#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ ++#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ ++#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ ++#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ ++#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ ++#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ ++ ++/* Timer */ ++/* For reg. fields see sp804 spec. */ ++#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) ++#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) ++#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) ++#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) ++#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) ++#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) ++#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) ++#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) ++#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) ++ ++#define TIMER_CTRL_ONESHOT (1 << 0) ++#define TIMER_CTRL_32BIT (1 << 1) ++#define TIMER_CTRL_DIV1 (0 << 2) ++#define TIMER_CTRL_DIV16 (1 << 2) ++#define TIMER_CTRL_DIV256 (2 << 2) ++#define TIMER_CTRL_IE (1 << 5) ++#define TIMER_CTRL_PERIODIC (1 << 6) ++#define TIMER_CTRL_ENABLE (1 << 7) ++#define TIMER_CTRL_DBGHALT (1 << 8) ++#define TIMER_CTRL_ENAFREE (1 << 9) ++#define TIMER_CTRL_FREEDIV_SHIFT 16) ++#define TIMER_CTRL_FREEDIV_MASK 0xff ++ ++/* Semaphores, Doorbells, Mailboxes */ ++#define ARM_SBM_OWN0 (ARM_BASE+0x800) ++#define ARM_SBM_OWN1 (ARM_BASE+0x900) ++#define ARM_SBM_OWN2 (ARM_BASE+0xA00) ++#define ARM_SBM_OWN3 (ARM_BASE+0xB00) ++ ++/* MAILBOXES ++ * Register flags are common across all ++ * owner registers. See end of this section ++ * ++ * Semaphores, Doorbells, Mailboxes Owner 0 ++ * ++ */ ++ ++#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) ++#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) ++#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) ++#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) ++#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) ++#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) ++#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) ++#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) ++#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) ++#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) ++#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Some addresses should ONLY be used by owner 0 */ ++#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ ++#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ ++#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ ++#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ ++#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ ++#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ ++/* MAILBOX 1 access in Owner 0 area */ ++/* Owner 0 should only WRITE to this mailbox */ ++#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ ++/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ ++#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ ++#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ ++#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 1 */ ++#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) ++#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) ++#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) ++#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) ++#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) ++#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) ++#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) ++#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) ++#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) ++#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) ++#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Owner 1 should only WRITE to this mailbox */ ++#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ ++/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 0 area */ ++#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ ++#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ ++#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ ++#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ ++#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ ++#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ ++#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ ++#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ ++#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 2 */ ++#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) ++#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) ++#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) ++#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) ++#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) ++#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) ++#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) ++#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) ++#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) ++#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) ++#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) ++/* MAILBOX 0 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ ++/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ ++/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ ++#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ ++#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ ++#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 3 */ ++#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) ++#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) ++#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) ++#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) ++#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) ++#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) ++#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) ++#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) ++#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) ++#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) ++#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) ++/* MAILBOX 0 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ ++/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ ++/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ ++#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ ++#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ ++#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ ++ ++ ++ ++/* Mailbox flags. Valid for all owners */ ++ ++/* Mailbox status register (...0x98) */ ++#define ARM_MS_FULL 0x80000000 ++#define ARM_MS_EMPTY 0x40000000 ++#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ ++ ++/* MAILBOX config/status register (...0x9C) */ ++/* ANY write to this register clears the error bits! */ ++#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ ++#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ ++#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ ++#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ ++#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ ++#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ ++#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ ++/* Bit 7 is unused */ ++#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ ++#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ ++#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ ++ ++/* Semaphore clear/debug register (...0xE0) */ ++#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ ++#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ ++#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ ++#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ ++#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ ++#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ ++#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ ++#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ ++#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ ++#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ ++#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ ++#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ ++#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ ++#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ ++#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ ++#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ ++ ++/* Doorbells clear/debug register (...0xE4) */ ++#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ ++#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ ++#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ ++#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ ++#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ ++#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ ++#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ ++#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ ++ ++/* MY IRQS register (...0xF8) */ ++#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ ++#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ ++ ++/* ALL IRQS register (...0xF8) */ ++#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ ++#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ ++#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ ++#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ ++#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ ++#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ ++#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ ++#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ ++#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ ++#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ ++/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ ++/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ ++/* */ ++/* ARM JTAG BASH */ ++/* */ ++#define AJB_BASE 0x7e2000c0 ++ ++#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) ++#define AJB_BITS0 0x000000 ++#define AJB_BITS4 0x000004 ++#define AJB_BITS8 0x000008 ++#define AJB_BITS12 0x00000C ++#define AJB_BITS16 0x000010 ++#define AJB_BITS20 0x000014 ++#define AJB_BITS24 0x000018 ++#define AJB_BITS28 0x00001C ++#define AJB_BITS32 0x000020 ++#define AJB_BITS34 0x000022 ++#define AJB_OUT_MS 0x000040 ++#define AJB_OUT_LS 0x000000 ++#define AJB_INV_CLK 0x000080 ++#define AJB_D0_RISE 0x000100 ++#define AJB_D0_FALL 0x000000 ++#define AJB_D1_RISE 0x000200 ++#define AJB_D1_FALL 0x000000 ++#define AJB_IN_RISE 0x000400 ++#define AJB_IN_FALL 0x000000 ++#define AJB_ENABLE 0x000800 ++#define AJB_HOLD0 0x000000 ++#define AJB_HOLD1 0x001000 ++#define AJB_HOLD2 0x002000 ++#define AJB_HOLD3 0x003000 ++#define AJB_RESETN 0x004000 ++#define AJB_CLKSHFT 16 ++#define AJB_BUSY 0x80000000 ++#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) ++#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) ++#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) ++ ++#define ARM_LOCAL_BASE 0x40000000 ++#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) ++#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) ++#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) ++#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) ++#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) ++#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) ++#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) ++#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) ++#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) ++#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) ++#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) ++#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) ++ ++#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) ++#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) ++#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) ++#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) ++ ++#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) ++ ++#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) ++#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) ++#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) ++#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) ++ ++#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) ++#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) ++#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) ++#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) ++ ++#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) ++#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) ++#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) ++#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) ++ ++#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) ++#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) ++#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) ++#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) ++ ++#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) ++#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) ++#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) ++#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) ++ ++#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) ++#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) ++#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) ++#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) ++#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) ++#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) ++#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) ++#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) ++#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) ++#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) ++#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) ++#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) ++#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) ++#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) ++#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) ++#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/barriers.h +@@ -0,0 +1,3 @@ ++#define mb() dsb() ++#define rmb() dsb() ++#define wmb() mb() +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/clkdev.h +@@ -0,0 +1,7 @@ ++#ifndef __ASM_MACH_CLKDEV_H ++#define __ASM_MACH_CLKDEV_H ++ ++#define __clk_get(clk) ({ 1; }) ++#define __clk_put(clk) do { } while (0) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/debug-macro.S +@@ -0,0 +1,22 @@ ++/* arch/arm/mach-bcm2708/include/mach/debug-macro.S ++ * ++ * Debugging macro include header ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 1994-1999 Russell King ++ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++ ++ .macro addruart, rp, rv, tmp ++ ldr \rp, =UART0_BASE ++ ldr \rv, =IO_ADDRESS(UART0_BASE) ++ .endm ++ ++#include +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S +@@ -0,0 +1,123 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/entry-macro.S ++ * ++ * Low-level IRQ helper macros for BCM2708 platforms ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ /* get core number */ ++ mrc p15, 0, \tmp, c0, c0, 5 ++ ubfx \tmp, \tmp, #0, #2 ++ ++ /* get core's local interrupt controller */ ++ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source ++ add \irqstat, \irqstat, \tmp, lsl #2 ++ ldr \tmp, [\irqstat] ++ /* ignore gpu interrupt */ ++ bic \tmp, #0x100 ++ /* ignore mailbox interrupts */ ++ bics \tmp, #0xf0 ++ beq 1005f ++ ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ @ N.B. CLZ is an ARM5 instruction. ++ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) ++ sub \irqstat, \tmp, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++ b 1020f ++1005: ++ /* get core number */ ++ mrc p15, 0, \tmp, c0, c0, 5 ++ ubfx \tmp, \tmp, #0, #2 ++ ++ cmp \tmp, #1 ++ beq 1020f ++ cmp \tmp, #2 ++ beq 1020f ++ cmp \tmp, #3 ++ beq 1020f ++ ++ /* get masked status */ ++ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] ++ mov \irqnr, #(ARM_IRQ0_BASE + 31) ++ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 ++ /* clear bits 8 and 9, and test */ ++ bics \irqstat, \irqstat, #0x300 ++ bne 1010f ++ ++ tst \tmp, #0x100 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ1_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) ++ bicne \irqstat, #((1<<18) | (1<<19)) ++ bne 1010f ++ ++ tst \tmp, #0x200 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ2_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) ++ bicne \irqstat, #((1<<30)) ++ beq 1020f ++ ++1010: ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ @ N.B. CLZ is an ARM5 instruction. ++ sub \tmp, \irqstat, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++ ++1020: @ EQ will be set if no irqs pending ++ ++ .endm ++ ++ .macro test_for_ipi, irqnr, irqstat, base, tmp ++ /* get core number */ ++ mrc p15, 0, \tmp, c0, c0, 5 ++ ubfx \tmp, \tmp, #0, #2 ++ /* get core's mailbox interrupt control */ ++ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr ++ add \irqstat, \irqstat, \tmp, lsl #4 ++ ldr \tmp, [\irqstat] ++ cmp \tmp, #0 ++ beq 1030f ++ clz \tmp, \tmp ++ rsb \irqnr, \tmp, #31 ++ mov \tmp, #1 ++ lsl \tmp, \irqnr ++ str \tmp, [\irqstat] @ clear interrupt source ++ dsb ++1030: @ EQ will be set if no irqs pending ++ .endm +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/frc.h +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 free running counter (timer) ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _MACH_FRC_H ++#define _MACH_FRC_H ++ ++#define FRC_TICK_RATE (1000000) ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ (slightly faster than frc_clock_ticks63() ++ */ ++extern unsigned long frc_clock_ticks32(void); ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ * Note - top bit should be ignored (see cnt32_to_63) ++ */ ++extern unsigned long long frc_clock_ticks63(void); ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/gpio.h +@@ -0,0 +1,17 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/gpio.h ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __ASM_ARCH_GPIO_H ++#define __ASM_ARCH_GPIO_H ++ ++#define BCM2708_NR_GPIOS 54 // number of gpio lines ++ ++#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) ++#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/hardware.h +@@ -0,0 +1,28 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/hardware.h ++ * ++ * This file contains the hardware definitions of the BCM2708 devices. ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H ++ ++#include ++#include ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/io.h +@@ -0,0 +1,27 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/io.h ++ * ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARM_ARCH_IO_H ++#define __ASM_ARM_ARCH_IO_H ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#define __io(a) __typesafe_io(a) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/irqs.h +@@ -0,0 +1,225 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/irqs.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_IRQS_H_ ++#define _BCM2708_IRQS_H_ ++ ++#include ++ ++/* ++ * IRQ interrupts definitions are the same as the INT definitions ++ * held within platform.h ++ */ ++#define IRQ_ARMCTRL_START 0 ++#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) ++#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) ++#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) ++#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) ++#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) ++#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) ++#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) ++#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) ++#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) ++#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) ++#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) ++#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) ++#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) ++#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) ++#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) ++#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) ++#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) ++#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) ++#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) ++#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) ++#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) ++#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) ++#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) ++#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) ++#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) ++#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) ++#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) ++#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) ++#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) ++#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) ++#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) ++#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) ++#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) ++#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) ++#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) ++#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) ++#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) ++#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) ++#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) ++#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) ++#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) ++#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) ++#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) ++#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) ++#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) ++#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) ++#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) ++#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) ++#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) ++#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) ++#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) ++#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) ++#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) ++#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) ++#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) ++#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) ++#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) ++#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) ++#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) ++#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) ++#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) ++#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) ++#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) ++#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) ++ ++#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) ++#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) ++#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) ++#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) ++#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) ++#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) ++#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) ++#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) ++#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) ++#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) ++ ++#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) ++#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) ++#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) ++#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) ++#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) ++#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) ++#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) ++#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) ++#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) ++#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) ++#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) ++#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) ++ ++#define FIQ_START HARD_IRQS ++ ++/* ++ * FIQ interrupts definitions are the same as the INT definitions. ++ */ ++#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) ++#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) ++#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) ++#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) ++#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) ++#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) ++#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) ++#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) ++#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) ++#define FIQ_USB (FIQ_START+INTERRUPT_USB) ++#define FIQ_3D (FIQ_START+INTERRUPT_3D) ++#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) ++#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) ++#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) ++#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) ++#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) ++#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) ++#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) ++#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) ++#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) ++#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) ++#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) ++#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) ++#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) ++#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) ++#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) ++#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) ++#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) ++#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) ++#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) ++#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) ++#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) ++#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) ++#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) ++#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) ++#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) ++#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) ++#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) ++#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) ++#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) ++#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) ++#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) ++#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) ++#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) ++#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) ++#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) ++#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) ++#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) ++#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) ++#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) ++#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) ++#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) ++#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) ++#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) ++#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) ++#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) ++#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) ++#define FIQ_UART (FIQ_START+INTERRUPT_UART) ++#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) ++#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) ++#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) ++#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) ++#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) ++#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) ++ ++#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) ++#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) ++#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) ++#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) ++#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) ++#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) ++#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) ++#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) ++#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) ++#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) ++ ++#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) ++#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) ++#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) ++#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) ++#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) ++#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) ++#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) ++#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) ++#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) ++#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) ++#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) ++#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) ++ ++#define HARD_IRQS (128) ++#define FIQ_IRQS (128) ++#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) ++#define GPIO_IRQS (32*5) ++#define SPARE_ALLOC_IRQS 64 ++#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) ++#define FREE_IRQS 128 ++#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) ++ ++#endif /* _BCM2708_IRQS_H_ */ +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/memory.h +@@ -0,0 +1,57 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/memory.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++/* Memory overview: ++ ++ [ARMcore] <--virtual addr--> ++ [ARMmmu] <--physical addr--> ++ [GERTmap] <--bus add--> ++ [VCperiph] ++ ++*/ ++ ++/* ++ * Physical DRAM offset. ++ */ ++#define BCM_PLAT_PHYS_OFFSET UL(0x00000000) ++#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ ++ ++#ifdef CONFIG_BCM2708_NOL2CACHE ++ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ ++#else ++ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ ++#endif ++ ++/* We're using the memory at 64M in the VideoCore for Linux - this adjustment ++ * will provide the offset into this area as well as setting the bits that ++ * stop the L1 and L2 cache from being used ++ * ++ * WARNING: this only works because the ARM is given memory at a fixed location ++ * (ARMMEM_OFFSET) ++ */ ++#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET) ++#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) ++#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) ++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/platform.h +@@ -0,0 +1,225 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/platform.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_PLATFORM_H ++#define _BCM2708_PLATFORM_H ++ ++ ++/* macros to get at IO space when running virtually */ ++#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) ++ ++#define __io_address(n) IOMEM(IO_ADDRESS(n)) ++ ++ ++/* ++ * SDRAM ++ */ ++#define BCM2708_SDRAM_BASE 0x00000000 ++ ++/* ++ * Logic expansion modules ++ * ++ */ ++ ++ ++/* ------------------------------------------------------------------------ ++ * BCM2708 ARMCTRL Registers ++ * ------------------------------------------------------------------------ ++ */ ++ ++#define HW_REGISTER_RW(addr) (addr) ++#define HW_REGISTER_RO(addr) (addr) ++ ++#include "arm_control.h" ++#undef ARM_BASE ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define BCM2708_PERI_BASE 0x3F000000 ++#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) ++#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ ++#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ ++#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ ++#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ ++#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ ++#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ ++#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ ++#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ ++#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ ++#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ ++#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */ ++#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ ++#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ ++#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ ++#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ ++#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ ++#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ ++#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ ++#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ ++ ++#define ARMCTRL_BASE (ARM_BASE + 0x000) ++#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ ++#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ ++#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ ++ ++ ++/* ++ * Interrupt assignments ++ */ ++ ++#define ARM_IRQ1_BASE 0 ++#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) ++#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) ++#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) ++#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) ++#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) ++#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) ++#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) ++#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) ++#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) ++#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) ++#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) ++#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) ++#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) ++#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) ++#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) ++#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) ++#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) ++#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) ++#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) ++#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) ++#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) ++#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) ++#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) ++#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) ++#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) ++#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) ++#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) ++#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) ++#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) ++#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) ++#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) ++#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) ++ ++#define ARM_IRQ2_BASE 32 ++#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) ++#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) ++#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) ++#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) ++#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) ++#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) ++#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) ++#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) ++#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) ++#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) ++#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) ++#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) ++#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) ++#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) ++#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) ++#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) ++#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) ++#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) ++#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) ++#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) ++#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) ++#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) ++#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) ++#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) ++#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) ++#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) ++#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) ++#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) ++#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) ++#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) ++#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) ++#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) ++ ++#define ARM_IRQ0_BASE 64 ++#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) ++#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) ++#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) ++#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) ++#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) ++#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) ++#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) ++#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) ++#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) ++#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) ++#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) ++#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) ++#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) ++#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) ++#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) ++#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) ++#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) ++#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) ++#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) ++#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) ++#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) ++ ++#define ARM_IRQ_LOCAL_BASE 96 ++#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) ++#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) ++#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) ++#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) ++#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) ++#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) ++#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) ++#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) ++#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) ++#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) ++#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) ++#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) ++ ++/* ++ * Watchdog ++ */ ++#define PM_RSTC (PM_BASE+0x1c) ++#define PM_RSTS (PM_BASE+0x20) ++#define PM_WDOG (PM_BASE+0x24) ++ ++#define PM_WDOG_RESET 0000000000 ++#define PM_PASSWORD 0x5a000000 ++#define PM_WDOG_TIME_SET 0x000fffff ++#define PM_RSTC_WRCFG_CLR 0xffffffcf ++#define PM_RSTC_WRCFG_SET 0x00000030 ++#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 ++#define PM_RSTC_RESET 0x00000102 ++ ++#define PM_RSTS_HADPOR_SET 0x00001000 ++#define PM_RSTS_HADSRH_SET 0x00000400 ++#define PM_RSTS_HADSRF_SET 0x00000200 ++#define PM_RSTS_HADSRQ_SET 0x00000100 ++#define PM_RSTS_HADWRH_SET 0x00000040 ++#define PM_RSTS_HADWRF_SET 0x00000020 ++#define PM_RSTS_HADWRQ_SET 0x00000010 ++#define PM_RSTS_HADDRH_SET 0x00000004 ++#define PM_RSTS_HADDRF_SET 0x00000002 ++#define PM_RSTS_HADDRQ_SET 0x00000001 ++ ++#define UART0_CLOCK 3000000 ++ ++#endif ++ ++/* END */ +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/system.h +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/system.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H ++ ++#include ++#include ++#include ++ ++static inline void arch_idle(void) ++{ ++ /* ++ * This should do all the clock switching ++ * and wait for interrupt tricks ++ */ ++ cpu_do_idle(); ++} ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/timex.h +@@ -0,0 +1,23 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 sysem clock frequency ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#define CLOCK_TICK_RATE (1000000) +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h +@@ -0,0 +1,84 @@ ++/* ++ * arch/arm/mach-bcn2708/include/mach/uncompress.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#define UART_BAUD 115200 ++ ++#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR) ++#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR) ++#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD) ++#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD) ++#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH) ++#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR) ++ ++/* ++ * This does not append a newline ++ */ ++static inline void putc(int c) ++{ ++ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF) ++ barrier(); ++ ++ __raw_writel(c, BCM2708_UART_DR); ++} ++ ++static inline void flush(void) ++{ ++ int fr; ++ ++ do { ++ fr = __raw_readl(BCM2708_UART_FR); ++ barrier(); ++ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); ++} ++ ++static inline void arch_decomp_setup(void) ++{ ++ int temp, div, rem, frac; ++ ++ temp = 16 * UART_BAUD; ++ div = UART0_CLOCK / temp; ++ rem = UART0_CLOCK % temp; ++ temp = (8 * rem) / UART_BAUD; ++ frac = (temp >> 1) + (temp & 1); ++ ++ /* Make sure the UART is disabled before we start */ ++ __raw_writel(0, BCM2708_UART_CR); ++ ++ /* Set the baud rate */ ++ __raw_writel(div, BCM2708_UART_IBRD); ++ __raw_writel(frac, BCM2708_UART_FBRD); ++ ++ /* Set the UART to 8n1, FIFO enabled */ ++ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH); ++ ++ /* Enable the UART */ ++ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE, ++ BCM2708_UART_CR); ++} ++ ++/* ++ * nothing to do ++ */ ++#define arch_decomp_wdog() +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/vc_mem.h +@@ -0,0 +1,35 @@ ++/***************************************************************************** ++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#if !defined( VC_MEM_H ) ++#define VC_MEM_H ++ ++#include ++ ++#define VC_MEM_IOC_MAGIC 'v' ++ ++#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) ++#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) ++#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int ) ++#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int ) ++ ++#if defined( __KERNEL__ ) ++#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF ++ ++extern unsigned long mm_vc_mem_phys_addr; ++extern unsigned int mm_vc_mem_size; ++extern int vc_mem_get_current_size( void ); ++#endif ++ ++#endif /* VC_MEM_H */ +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/vc_support.h +@@ -0,0 +1,69 @@ ++#ifndef _VC_SUPPORT_H_ ++#define _VC_SUPPORT_H_ ++ ++/* ++ * vc_support.h ++ * ++ * Created on: 25 Nov 2012 ++ * Author: Simon ++ */ ++ ++enum { ++/* ++ If a MEM_HANDLE_T is discardable, the memory manager may resize it to size ++ 0 at any time when it is not locked or retained. ++ */ ++ MEM_FLAG_DISCARDABLE = 1 << 0, ++ ++ /* ++ If a MEM_HANDLE_T is allocating (or normal), its block of memory will be ++ accessed in an allocating fashion through the cache. ++ */ ++ MEM_FLAG_NORMAL = 0 << 2, ++ MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL, ++ ++ /* ++ If a MEM_HANDLE_T is direct, its block of memory will be accessed ++ directly, bypassing the cache. ++ */ ++ MEM_FLAG_DIRECT = 1 << 2, ++ ++ /* ++ If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a ++ non-allocating fashion through the cache. ++ */ ++ MEM_FLAG_COHERENT = 2 << 2, ++ ++ /* ++ If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by ++ the VPU in a fashion which is allocating in L2, but only coherent in L1. ++ */ ++ MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT), ++ ++ /* ++ If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than ++ MEM_HANDLE_INVALID on allocation and resize up. ++ */ ++ MEM_FLAG_ZERO = 1 << 4, ++ ++ /* ++ If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value ++ (either zero, or all 1's) on allocation. ++ */ ++ MEM_FLAG_NO_INIT = 1 << 5, ++ ++ /* ++ Hints. ++ */ ++ MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */ ++}; ++ ++unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags); ++unsigned int ReleaseVcMemory(unsigned int handle); ++unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle); ++unsigned int UnlockVcMemory(unsigned int handle); ++ ++unsigned int ExecuteVcCode(unsigned int code, ++ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5); ++ ++#endif +--- /dev/null ++++ b/arch/arm/mach-bcm2709/include/mach/vmalloc.h +@@ -0,0 +1,20 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/vmalloc.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#define VMALLOC_END (0xff000000) +--- /dev/null ++++ b/arch/arm/mach-bcm2709/vc_mem.c +@@ -0,0 +1,431 @@ ++/***************************************************************************** ++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_ARCH_KONA ++#include ++#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709) ++#else ++#include ++#endif ++ ++#include "mach/vc_mem.h" ++ ++#define DRIVER_NAME "vc-mem" ++ ++// Device (/dev) related variables ++static dev_t vc_mem_devnum = 0; ++static struct class *vc_mem_class = NULL; ++static struct cdev vc_mem_cdev; ++static int vc_mem_inited = 0; ++ ++#ifdef CONFIG_DEBUG_FS ++static struct dentry *vc_mem_debugfs_entry; ++#endif ++ ++/* ++ * Videocore memory addresses and size ++ * ++ * Drivers that wish to know the videocore memory addresses and sizes should ++ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in ++ * headers. This allows the other drivers to not be tied down to a a certain ++ * address/size at compile time. ++ * ++ * In the future, the goal is to have the videocore memory virtual address and ++ * size be calculated at boot time rather than at compile time. The decision of ++ * where the videocore memory resides and its size would be in the hands of the ++ * bootloader (and/or kernel). When that happens, the values of these variables ++ * would be calculated and assigned in the init function. ++ */ ++// in the 2835 VC in mapped above ARM, but ARM has full access to VC space ++unsigned long mm_vc_mem_phys_addr = 0x00000000; ++unsigned int mm_vc_mem_size = 0; ++unsigned int mm_vc_mem_base = 0; ++ ++EXPORT_SYMBOL(mm_vc_mem_phys_addr); ++EXPORT_SYMBOL(mm_vc_mem_size); ++EXPORT_SYMBOL(mm_vc_mem_base); ++ ++static uint phys_addr = 0; ++static uint mem_size = 0; ++static uint mem_base = 0; ++ ++ ++/**************************************************************************** ++* ++* vc_mem_open ++* ++***************************************************************************/ ++ ++static int ++vc_mem_open(struct inode *inode, struct file *file) ++{ ++ (void) inode; ++ (void) file; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_release ++* ++***************************************************************************/ ++ ++static int ++vc_mem_release(struct inode *inode, struct file *file) ++{ ++ (void) inode; ++ (void) file; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_size ++* ++***************************************************************************/ ++ ++static void ++vc_mem_get_size(void) ++{ ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_base ++* ++***************************************************************************/ ++ ++static void ++vc_mem_get_base(void) ++{ ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_current_size ++* ++***************************************************************************/ ++ ++int ++vc_mem_get_current_size(void) ++{ ++ return mm_vc_mem_size; ++} ++ ++EXPORT_SYMBOL_GPL(vc_mem_get_current_size); ++ ++/**************************************************************************** ++* ++* vc_mem_ioctl ++* ++***************************************************************************/ ++ ++static long ++vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int rc = 0; ++ ++ (void) cmd; ++ (void) arg; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ switch (cmd) { ++ case VC_MEM_IOC_MEM_PHYS_ADDR: ++ { ++ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n", ++ __func__, (void *) mm_vc_mem_phys_addr); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr, ++ sizeof (mm_vc_mem_phys_addr)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_SIZE: ++ { ++ // Get the videocore memory size first ++ vc_mem_get_size(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__, ++ mm_vc_mem_size); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_size, ++ sizeof (mm_vc_mem_size)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_BASE: ++ { ++ // Get the videocore memory base ++ vc_mem_get_base(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__, ++ mm_vc_mem_base); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_base, ++ sizeof (mm_vc_mem_base)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_LOAD: ++ { ++ // Get the videocore memory base ++ vc_mem_get_base(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__, ++ mm_vc_mem_base); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_base, ++ sizeof (mm_vc_mem_base)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ default: ++ { ++ return -ENOTTY; ++ } ++ } ++ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc); ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_mmap ++* ++***************************************************************************/ ++ ++static int ++vc_mem_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ int rc = 0; ++ unsigned long length = vma->vm_end - vma->vm_start; ++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; ++ ++ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n", ++ __func__, (long) vma->vm_start, (long) vma->vm_end, ++ (long) vma->vm_pgoff); ++ ++ if (offset + length > mm_vc_mem_size) { ++ pr_err("%s: length %ld is too big\n", __func__, length); ++ return -EINVAL; ++ } ++ // Do not cache the memory map ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ rc = remap_pfn_range(vma, vma->vm_start, ++ (mm_vc_mem_phys_addr >> PAGE_SHIFT) + ++ vma->vm_pgoff, length, vma->vm_page_prot); ++ if (rc != 0) { ++ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc); ++ } ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* File Operations for the driver. ++* ++***************************************************************************/ ++ ++static const struct file_operations vc_mem_fops = { ++ .owner = THIS_MODULE, ++ .open = vc_mem_open, ++ .release = vc_mem_release, ++ .unlocked_ioctl = vc_mem_ioctl, ++ .mmap = vc_mem_mmap, ++}; ++ ++#ifdef CONFIG_DEBUG_FS ++static void vc_mem_debugfs_deinit(void) ++{ ++ debugfs_remove_recursive(vc_mem_debugfs_entry); ++ vc_mem_debugfs_entry = NULL; ++} ++ ++ ++static int vc_mem_debugfs_init( ++ struct device *dev) ++{ ++ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL); ++ if (!vc_mem_debugfs_entry) { ++ dev_warn(dev, "could not create debugfs entry\n"); ++ return -EFAULT; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_phys_addr", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_phys_addr)) { ++ dev_warn(dev, "%s:could not create vc_mem_phys entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_size", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_size)) { ++ dev_warn(dev, "%s:could not create vc_mem_size entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_base", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_base)) { ++ dev_warn(dev, "%s:could not create vc_mem_base entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ return 0; ++ ++fail: ++ vc_mem_debugfs_deinit(); ++ return -EFAULT; ++} ++ ++#endif /* CONFIG_DEBUG_FS */ ++ ++ ++/**************************************************************************** ++* ++* vc_mem_init ++* ++***************************************************************************/ ++ ++static int __init ++vc_mem_init(void) ++{ ++ int rc = -EFAULT; ++ struct device *dev; ++ ++ pr_debug("%s: called\n", __func__); ++ ++ mm_vc_mem_phys_addr = phys_addr; ++ mm_vc_mem_size = mem_size; ++ mm_vc_mem_base = mem_base; ++ ++ vc_mem_get_size(); ++ ++ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n", ++ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024)); ++ ++ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) { ++ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n", ++ __func__, rc); ++ goto out_err; ++ } ++ ++ cdev_init(&vc_mem_cdev, &vc_mem_fops); ++ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) { ++ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc); ++ goto out_unregister; ++ } ++ ++ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME); ++ if (IS_ERR(vc_mem_class)) { ++ rc = PTR_ERR(vc_mem_class); ++ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc); ++ goto out_cdev_del; ++ } ++ ++ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL, ++ DRIVER_NAME); ++ if (IS_ERR(dev)) { ++ rc = PTR_ERR(dev); ++ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc); ++ goto out_class_destroy; ++ } ++ ++#ifdef CONFIG_DEBUG_FS ++ /* don't fail if the debug entries cannot be created */ ++ vc_mem_debugfs_init(dev); ++#endif ++ ++ vc_mem_inited = 1; ++ return 0; ++ ++ device_destroy(vc_mem_class, vc_mem_devnum); ++ ++ out_class_destroy: ++ class_destroy(vc_mem_class); ++ vc_mem_class = NULL; ++ ++ out_cdev_del: ++ cdev_del(&vc_mem_cdev); ++ ++ out_unregister: ++ unregister_chrdev_region(vc_mem_devnum, 1); ++ ++ out_err: ++ return -1; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_exit ++* ++***************************************************************************/ ++ ++static void __exit ++vc_mem_exit(void) ++{ ++ pr_debug("%s: called\n", __func__); ++ ++ if (vc_mem_inited) { ++#if CONFIG_DEBUG_FS ++ vc_mem_debugfs_deinit(); ++#endif ++ device_destroy(vc_mem_class, vc_mem_devnum); ++ class_destroy(vc_mem_class); ++ cdev_del(&vc_mem_cdev); ++ unregister_chrdev_region(vc_mem_devnum, 1); ++ } ++} ++ ++module_init(vc_mem_init); ++module_exit(vc_mem_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); ++ ++module_param(phys_addr, uint, 0644); ++module_param(mem_size, uint, 0644); ++module_param(mem_base, uint, 0644); +--- /dev/null ++++ b/arch/arm/mach-bcm2709/vc_support.c +@@ -0,0 +1,318 @@ ++/* ++ * vc_support.c ++ * ++ * Created on: 25 Nov 2012 ++ * Author: Simon ++ */ ++ ++#include ++#include ++ ++#ifdef ECLIPSE_IGNORE ++ ++#define __user ++#define __init ++#define __exit ++#define __iomem ++#define KERN_DEBUG ++#define KERN_ERR ++#define KERN_WARNING ++#define KERN_INFO ++#define _IOWR(a, b, c) b ++#define _IOW(a, b, c) b ++#define _IO(a, b) b ++ ++#endif ++ ++/****** VC MAILBOX FUNCTIONALITY ******/ ++unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_size; ++ unsigned int m_handle; ++ }; ++ unsigned int m_alignment; ++ unsigned int m_flags; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the allocation command ++ msg.m_tag.m_tagId = 0x3000c; ++ msg.m_tag.m_sendBufferSize = 12; ++ msg.m_tag.m_sendDataSize = 12; ++ ++ //fill in our args ++ msg.m_tag.m_args.m_size = size; ++ msg.m_tag.m_args.m_alignment = alignment; ++ msg.m_tag.m_args.m_flags = flags; ++ ++ //run the command ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) ++ { ++ *pHandle = msg.m_tag.m_args.m_handle; ++ return 0; ++ } ++ else ++ { ++ printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize); ++ return 1; ++ } ++} ++ ++unsigned int ReleaseVcMemory(unsigned int handle) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_handle; ++ unsigned int m_error; ++ }; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the release command ++ msg.m_tag.m_tagId = 0x3000f; ++ msg.m_tag.m_sendBufferSize = 4; ++ msg.m_tag.m_sendDataSize = 4; ++ ++ //pass across the handle ++ msg.m_tag.m_args.m_handle = handle; ++ ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0) ++ return 0; ++ else ++ { ++ printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error); ++ return 1; ++ } ++} ++ ++unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_handle; ++ unsigned int m_busAddress; ++ }; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the lock command ++ msg.m_tag.m_tagId = 0x3000d; ++ msg.m_tag.m_sendBufferSize = 4; ++ msg.m_tag.m_sendDataSize = 4; ++ ++ //pass across the handle ++ msg.m_tag.m_args.m_handle = handle; ++ ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) ++ { ++ //pick out the bus address ++ *pBusAddress = msg.m_tag.m_args.m_busAddress; ++ return 0; ++ } ++ else ++ { ++ printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize); ++ return 1; ++ } ++} ++ ++unsigned int UnlockVcMemory(unsigned int handle) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_handle; ++ unsigned int m_error; ++ }; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the unlock command ++ msg.m_tag.m_tagId = 0x3000e; ++ msg.m_tag.m_sendBufferSize = 4; ++ msg.m_tag.m_sendDataSize = 4; ++ ++ //pass across the handle ++ msg.m_tag.m_args.m_handle = handle; ++ ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ //check the error code too ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0) ++ return 0; ++ else ++ { ++ printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error); ++ return 1; ++ } ++} ++ ++unsigned int ExecuteVcCode(unsigned int code, ++ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_pCode; ++ unsigned int m_return; ++ }; ++ unsigned int m_r0; ++ unsigned int m_r1; ++ unsigned int m_r2; ++ unsigned int m_r3; ++ unsigned int m_r4; ++ unsigned int m_r5; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the unlock command ++ msg.m_tag.m_tagId = 0x30010; ++ msg.m_tag.m_sendBufferSize = 28; ++ msg.m_tag.m_sendDataSize = 28; ++ ++ //pass across the handle ++ msg.m_tag.m_args.m_pCode = code; ++ msg.m_tag.m_args.m_r0 = r0; ++ msg.m_tag.m_args.m_r1 = r1; ++ msg.m_tag.m_args.m_r2 = r2; ++ msg.m_tag.m_args.m_r3 = r3; ++ msg.m_tag.m_args.m_r4 = r4; ++ msg.m_tag.m_args.m_r5 = r5; ++ ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ //check the error code too ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) ++ return msg.m_tag.m_args.m_return; ++ else ++ { ++ printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize); ++ return 1; ++ } ++} +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -358,7 +358,7 @@ config CPU_PJ4B + + # ARMv6 + config CPU_V6 +- bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX) ++ bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708) + select CPU_32v6 + select CPU_ABRT_EV6 + select CPU_CACHE_V6 +--- a/arch/arm/mm/proc-v6.S ++++ b/arch/arm/mm/proc-v6.S +@@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset) + * + * IRQs are already disabled. + */ ++ ++/* See jira SW-5991 for details of this workaround */ + ENTRY(cpu_v6_do_idle) +- mov r1, #0 +- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode +- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt ++ .align 5 ++ mov r1, #2 ++1: subs r1, #1 ++ nop ++ mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode ++ mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt ++ nop ++ nop ++ nop ++ bne 1b + ret lr + + ENTRY(cpu_v6_dcache_clean_area) +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -460,6 +460,7 @@ __v7_setup_cont: + orr r0, r0, r6 @ set them + THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions + ret lr @ return to head.S:__ret ++ .space 256 + ENDPROC(__v7_setup) + + .align 2 +--- a/arch/arm/tools/mach-types ++++ b/arch/arm/tools/mach-types +@@ -522,6 +522,8 @@ torbreck MACH_TORBRECK TORBRECK 3090 + prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103 + paz00 MACH_PAZ00 PAZ00 3128 + acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129 ++bcm2708 MACH_BCM2708 BCM2708 3138 ++bcm2709 MACH_BCM2709 BCM2709 3139 + ag5evm MACH_AG5EVM AG5EVM 3189 + ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 + wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -882,3 +882,39 @@ void __init acpi_generic_timer_init(void + acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init); + } + #endif ++ ++int __init dc4_arch_timer_init(void) ++{ ++ if (arch_timers_present & ARCH_CP15_TIMER) { ++ pr_warn("arch_timer: multiple nodes in dt, skipping\n"); ++ return -1; ++ } ++ ++ arch_timers_present |= ARCH_CP15_TIMER; ++ ++ /* Try to determine the frequency from the device tree or CNTFRQ */ ++ arch_timer_rate = 19200000; ++ ++ arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ; ++ arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ; ++ arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ; ++ arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ; ++ ++ /* ++ * If HYP mode is available, we know that the physical timer ++ * has been configured to be accessible from PL1. Use it, so ++ * that a guest can use the virtual timer instead. ++ * ++ * If no interrupt provided for virtual timer, we'll have to ++ * stick to the physical timer. It'd better be accessible... ++ */ ++ if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { ++ arch_timer_use_virtual = false; ++ } ++ ++ arch_timer_c3stop = 0; ++ ++ arch_timer_register(); ++ arch_timer_common_init(); ++ return 0; ++} +--- a/drivers/tty/serial/amba-pl011.c ++++ b/drivers/tty/serial/amba-pl011.c +@@ -85,7 +85,7 @@ struct vendor_data { + + static unsigned int get_fifosize_arm(struct amba_device *dev) + { +- return amba_rev(dev) < 3 ? 16 : 32; ++ return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32; + } + + static struct vendor_data vendor_arm = { +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -285,6 +285,7 @@ struct mmc_host { + MMC_CAP2_HS400_1_2V) + #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) + #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) ++#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */ + + mmc_pm_flag_t pm_caps; /* supported pm features */ + diff --git a/target/linux/brcm2708/patches-4.1/0002-Add-bcm2708_gpio-driver.patch b/target/linux/brcm2708/patches-4.1/0002-Add-bcm2708_gpio-driver.patch new file mode 100644 index 0000000..e79b45a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0002-Add-bcm2708_gpio-driver.patch @@ -0,0 +1,615 @@ +From 1b06d065cc1209ff7524486eae5dd9bf00a2db0e Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 8 Oct 2014 18:50:05 +0100 +Subject: [PATCH 002/203] Add bcm2708_gpio driver + +Signed-off-by: popcornmix + +bcm2708: Add extension to configure internal pulls + +The bcm2708 gpio controller supports internal pulls to be used as pull-up, +pull-down or being entirely disabled. As it can be useful for a driver to +change the pull configuration from it's default pull-down state, add an +extension which allows configuring the pull per gpio. + +Signed-off-by: Julian Scheel + +bcm2708-gpio: Revert the use of pinctrl_request_gpio + +In non-DT systems, pinctrl_request_gpio always fails causing +"requests probe deferral" messages. In DT systems, it isn't useful +because the reference counting is independent of the normal pinctrl +pin reservations. + +gpio: Only clear the currently occurring interrupt. Avoids losing interrupts + +See: linux #760 + +bcm2708_gpio: Avoid calling irq_unmask for all interrupts + +When setting up the interrupts, specify that the handle_simple_irq +handler should be used. This leaves interrupt acknowledgement to +the caller, and prevents irq_unmask from being called for all +interrupts. + +Issue: linux #760 +--- + arch/arm/mach-bcm2708/Kconfig | 8 + + arch/arm/mach-bcm2708/Makefile | 1 + + arch/arm/mach-bcm2708/bcm2708.c | 25 ++ + arch/arm/mach-bcm2708/bcm2708_gpio.c | 426 ++++++++++++++++++++++++++++++ + arch/arm/mach-bcm2708/include/mach/gpio.h | 17 ++ + arch/arm/mach-bcm2709/bcm2709.c | 25 ++ + include/linux/platform_data/bcm2708.h | 23 ++ + 7 files changed, 525 insertions(+) + create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c + create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h + create mode 100644 include/linux/platform_data/bcm2708.h + +--- a/arch/arm/mach-bcm2708/Kconfig ++++ b/arch/arm/mach-bcm2708/Kconfig +@@ -20,6 +20,14 @@ config BCM2708_DT + help + Enable Device Tree support for BCM2708 + ++config BCM2708_GPIO ++ bool "BCM2708 gpio support" ++ depends on MACH_BCM2708 ++ select ARCH_REQUIRE_GPIOLIB ++ default y ++ help ++ Include support for the Broadcom(R) BCM2708 gpio. ++ + config BCM2708_NOL2CACHE + bool "Videocore L2 cache disable" + depends on MACH_BCM2708 +--- a/arch/arm/mach-bcm2708/Makefile ++++ b/arch/arm/mach-bcm2708/Makefile +@@ -3,3 +3,4 @@ + # + + obj-$(CONFIG_MACH_BCM2708) += bcm2708.o armctrl.o ++obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -298,6 +298,31 @@ static struct platform_device bcm2708_vc + }, + }; + ++#ifdef CONFIG_BCM2708_GPIO ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++ ++static struct resource bcm2708_gpio_resources[] = { ++ [0] = { /* general purpose I/O */ ++ .start = GPIO_BASE, ++ .end = GPIO_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_gpio_device = { ++ .name = BCM_GPIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_gpio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), ++ .dev = { ++ .dma_mask = &gpio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +--- /dev/null ++++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c +@@ -0,0 +1,426 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++#define DRIVER_NAME BCM_GPIO_DRIVER_NAME ++#define BCM_GPIO_USE_IRQ 1 ++ ++#define GPIOFSEL(x) (0x00+(x)*4) ++#define GPIOSET(x) (0x1c+(x)*4) ++#define GPIOCLR(x) (0x28+(x)*4) ++#define GPIOLEV(x) (0x34+(x)*4) ++#define GPIOEDS(x) (0x40+(x)*4) ++#define GPIOREN(x) (0x4c+(x)*4) ++#define GPIOFEN(x) (0x58+(x)*4) ++#define GPIOHEN(x) (0x64+(x)*4) ++#define GPIOLEN(x) (0x70+(x)*4) ++#define GPIOAREN(x) (0x7c+(x)*4) ++#define GPIOAFEN(x) (0x88+(x)*4) ++#define GPIOUD(x) (0x94+(x)*4) ++#define GPIOUDCLK(x) (0x98+(x)*4) ++ ++#define GPIO_BANKS 2 ++ ++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, ++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, ++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, ++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, ++}; ++ ++ /* Each of the two spinlocks protects a different set of hardware ++ * regiters and data structurs. This decouples the code of the IRQ from ++ * the GPIO code. This also makes the case of a GPIO routine call from ++ * the IRQ code simpler. ++ */ ++static DEFINE_SPINLOCK(lock); /* GPIO registers */ ++ ++struct bcm2708_gpio { ++ struct list_head list; ++ void __iomem *base; ++ struct gpio_chip gc; ++ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32]; ++}; ++ ++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, ++ int function) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned long flags; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++ ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= function << gpio_field_offset; ++ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); ++ spin_unlock_irqrestore(&lock, flags); ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ ++ return 0; ++} ++ ++static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) ++{ ++ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); ++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, ++ int value) ++{ ++ int ret; ++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); ++ if (ret >= 0) ++ bcm2708_gpio_set(gc, offset, value); ++ return ret; ++} ++ ++static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ unsigned lev; ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return 0; ++ lev = readl(gpio->base + GPIOLEV(gpio_bank)); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); ++ return 0x1 & (lev >> gpio_field_offset); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); ++ if (offset >= BCM2708_NR_GPIOS) ++ return; ++ if (value) ++ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); ++ else ++ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); ++} ++ ++/********************** ++ * extension to configure pullups ++ */ ++int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, ++ bcm2708_gpio_pull_t value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ switch (value) { ++ case BCM2708_PULL_UP: ++ writel(2, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_DOWN: ++ writel(1, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_OFF: ++ writel(0, gpio->base + GPIOUD(0)); ++ break; ++ } ++ ++ udelay(5); ++ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ udelay(5); ++ writel(0, gpio->base + GPIOUD(0)); ++ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcm2708_gpio_setpull); ++ ++/************************************************************************************************************************* ++ * bcm2708 GPIO IRQ ++ */ ++ ++#if BCM_GPIO_USE_IRQ ++ ++static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) ++{ ++ return gpio_to_irq(gpio); ++} ++ ++static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ ++ gpio->rising[gb] &= ~(1 << go); ++ gpio->falling[gb] &= ~(1 << go); ++ gpio->high[gb] &= ~(1 << go); ++ gpio->low[gb] &= ~(1 << go); ++ ++ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) ++ return -EINVAL; ++ ++ if (type & IRQ_TYPE_EDGE_RISING) ++ gpio->rising[gb] |= (1 << go); ++ if (type & IRQ_TYPE_EDGE_FALLING) ++ gpio->falling[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_HIGH) ++ gpio->high[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_LOW) ++ gpio->low[gb] |= (1 << go); ++ return 0; ++} ++ ++static void bcm2708_gpio_irq_mask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ gn = gn % 32; ++ ++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); ++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); ++ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); ++ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); ++} ++ ++static void bcm2708_gpio_irq_unmask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ if (gpio->rising[gb] & (1 << go)) { ++ writel(rising | (1 << go), gpio->base + GPIOREN(gb)); ++ } else { ++ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb)); ++ } ++ ++ if (gpio->falling[gb] & (1 << go)) { ++ writel(falling | (1 << go), gpio->base + GPIOFEN(gb)); ++ } else { ++ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb)); ++ } ++ ++ if (gpio->high[gb] & (1 << go)) { ++ writel(high | (1 << go), gpio->base + GPIOHEN(gb)); ++ } else { ++ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb)); ++ } ++ ++ if (gpio->low[gb] & (1 << go)) { ++ writel(low | (1 << go), gpio->base + GPIOLEN(gb)); ++ } else { ++ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb)); ++ } ++} ++ ++static struct irq_chip bcm2708_irqchip = { ++ .name = "GPIO", ++ .irq_enable = bcm2708_gpio_irq_unmask, ++ .irq_disable = bcm2708_gpio_irq_mask, ++ .irq_unmask = bcm2708_gpio_irq_unmask, ++ .irq_mask = bcm2708_gpio_irq_mask, ++ .irq_set_type = bcm2708_gpio_irq_set_type, ++}; ++ ++static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) ++{ ++ unsigned long edsr; ++ unsigned bank; ++ int i; ++ unsigned gpio; ++ unsigned level_bits; ++ struct bcm2708_gpio *gpio_data = dev_id; ++ ++ for (bank = 0; bank < GPIO_BANKS; bank++) { ++ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); ++ level_bits = gpio_data->high[bank] | gpio_data->low[bank]; ++ ++ for_each_set_bit(i, &edsr, 32) { ++ gpio = i + bank * 32; ++ /* ack edge triggered IRQs immediately */ ++ if (!(level_bits & (1<gc.to_irq = bcm2708_gpio_to_irq; ++ ++ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { ++ irq_set_chip_data(irq, ucb); ++ irq_set_chip_and_handler(irq, &bcm2708_irqchip, ++ handle_simple_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ bcm2708_gpio_irq.dev_id = ucb; ++ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); ++} ++ ++#else ++ ++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) ++{ ++} ++ ++#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ ++ ++static int bcm2708_gpio_probe(struct platform_device *dev) ++{ ++ struct bcm2708_gpio *ucb; ++ struct resource *res; ++ int bank; ++ int err = 0; ++ ++ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); ++ ++ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); ++ if (NULL == ucb) { ++ printk(KERN_ERR DRIVER_NAME ": failed to allocate " ++ "mailbox memory\n"); ++ err = -ENOMEM; ++ goto err; ++ } ++ ++ res = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ ++ platform_set_drvdata(dev, ucb); ++ ucb->base = __io_address(GPIO_BASE); ++ ++ ucb->gc.label = "bcm2708_gpio"; ++ ucb->gc.base = 0; ++ ucb->gc.ngpio = BCM2708_NR_GPIOS; ++ ucb->gc.owner = THIS_MODULE; ++ ++ ucb->gc.direction_input = bcm2708_gpio_dir_in; ++ ucb->gc.direction_output = bcm2708_gpio_dir_out; ++ ucb->gc.get = bcm2708_gpio_get; ++ ucb->gc.set = bcm2708_gpio_set; ++ ucb->gc.can_sleep = 0; ++ ++ for (bank = 0; bank < GPIO_BANKS; bank++) { ++ writel(0, ucb->base + GPIOREN(bank)); ++ writel(0, ucb->base + GPIOFEN(bank)); ++ writel(0, ucb->base + GPIOHEN(bank)); ++ writel(0, ucb->base + GPIOLEN(bank)); ++ writel(0, ucb->base + GPIOAREN(bank)); ++ writel(0, ucb->base + GPIOAFEN(bank)); ++ writel(~0, ucb->base + GPIOEDS(bank)); ++ } ++ ++ bcm2708_gpio_irq_init(ucb); ++ ++ err = gpiochip_add(&ucb->gc); ++ ++err: ++ return err; ++ ++} ++ ++static int bcm2708_gpio_remove(struct platform_device *dev) ++{ ++ int err = 0; ++ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); ++ ++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); ++ ++ gpiochip_remove(&ucb->gc); ++ ++ platform_set_drvdata(dev, NULL); ++ kfree(ucb); ++ ++ return err; ++} ++ ++static struct platform_driver bcm2708_gpio_driver = { ++ .probe = bcm2708_gpio_probe, ++ .remove = bcm2708_gpio_remove, ++ .driver = { ++ .name = "bcm2708_gpio"}, ++}; ++ ++static int __init bcm2708_gpio_init(void) ++{ ++ return platform_driver_register(&bcm2708_gpio_driver); ++} ++ ++static void __exit bcm2708_gpio_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_gpio_driver); ++} ++ ++module_init(bcm2708_gpio_init); ++module_exit(bcm2708_gpio_exit); ++ ++MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/gpio.h +@@ -0,0 +1,17 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/gpio.h ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __ASM_ARCH_GPIO_H ++#define __ASM_ARCH_GPIO_H ++ ++#define BCM2708_NR_GPIOS 54 // number of gpio lines ++ ++#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) ++#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) ++ ++#endif +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -329,6 +329,31 @@ static struct platform_device bcm2708_vc + }, + }; + ++#ifdef CONFIG_BCM2708_GPIO ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++ ++static struct resource bcm2708_gpio_resources[] = { ++ [0] = { /* general purpose I/O */ ++ .start = GPIO_BASE, ++ .end = GPIO_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_gpio_device = { ++ .name = BCM_GPIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_gpio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), ++ .dev = { ++ .dma_mask = &gpio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +--- /dev/null ++++ b/include/linux/platform_data/bcm2708.h +@@ -0,0 +1,23 @@ ++/* ++ * include/linux/platform_data/bcm2708.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * (C) 2014 Julian Scheel ++ * ++ */ ++#ifndef __BCM2708_H_ ++#define __BCM2708_H_ ++ ++typedef enum { ++ BCM2708_PULL_OFF, ++ BCM2708_PULL_UP, ++ BCM2708_PULL_DOWN ++} bcm2708_gpio_pull_t; ++ ++extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, ++ bcm2708_gpio_pull_t value); ++ ++#endif diff --git a/target/linux/brcm2708/patches-4.1/0003-mailbox-bcm2708-Add-bcm2708-vcio.patch b/target/linux/brcm2708/patches-4.1/0003-mailbox-bcm2708-Add-bcm2708-vcio.patch new file mode 100644 index 0000000..57becd5 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0003-mailbox-bcm2708-Add-bcm2708-vcio.patch @@ -0,0 +1,623 @@ +From 0c1382bd36ed3bc31b953028083619990e4dadf6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 1 May 2015 19:11:03 +0200 +Subject: [PATCH 003/203] mailbox: bcm2708: Add bcm2708-vcio +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: popcornmix + +Copy the arch vcio.c driver to drivers/mailbox. +This is done to make it available on ARCH_BCM2835. + +Signed-off-by: Noralf Trønnes + +mailbox: bcm2708-vcio: Allocation does not need to be atomic + +No need to do atomic allocation in a context that can sleep. + +Signed-off-by: Noralf Trønnes + +mailbox: bcm2708-vcio: Check the correct status register before writing + +With the VC reader blocked and the ARM writing, MAIL0_STA reads +empty permanently while MAIL1_STA goes from empty (0x40000000) +to non-empty (0x00000001-0x00000007) to full (0x80000008). + +Suggested-by: Phil Elwell +Signed-off-by: Noralf Trønnes +--- + drivers/mailbox/Kconfig | 6 + + drivers/mailbox/Makefile | 2 + + drivers/mailbox/bcm2708-vcio.c | 427 ++++++++++++++++++++++++++ + include/linux/platform_data/mailbox-bcm2708.h | 126 ++++++++ + 4 files changed, 561 insertions(+) + create mode 100644 drivers/mailbox/bcm2708-vcio.c + create mode 100644 include/linux/platform_data/mailbox-bcm2708.h + +--- a/drivers/mailbox/Kconfig ++++ b/drivers/mailbox/Kconfig +@@ -7,6 +7,12 @@ menuconfig MAILBOX + + if MAILBOX + ++config BCM2708_MBOX ++ bool "Broadcom BCM2708 Mailbox (vcio)" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ help ++ Broadcom BCM2708 Mailbox (vcio) ++ + config ARM_MHU + tristate "ARM MHU Mailbox" + depends on ARM_AMBA +--- a/drivers/mailbox/Makefile ++++ b/drivers/mailbox/Makefile +@@ -2,6 +2,8 @@ + + obj-$(CONFIG_MAILBOX) += mailbox.o + ++obj-$(CONFIG_BCM2708_MBOX) += bcm2708-vcio.o ++ + obj-$(CONFIG_ARM_MHU) += arm_mhu.o + + obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o +--- /dev/null ++++ b/drivers/mailbox/bcm2708-vcio.c +@@ -0,0 +1,427 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/vcio.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This device provides a shared mechanism for writing to the mailboxes, ++ * semaphores, doorbells etc. that are shared between the ARM and the ++ * VideoCore processor ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "bcm2708_vcio" ++#define DEVICE_FILE_NAME "vcio" ++ ++/* offsets from a mail box base address */ ++#define MAIL0_RD 0x00 /* read - and next 4 words */ ++#define MAIL0_POL 0x10 /* read without popping the fifo */ ++#define MAIL0_SND 0x14 /* sender ID (bottom two bits) */ ++#define MAIL0_STA 0x18 /* status */ ++#define MAIL0_CNF 0x1C /* configuration */ ++#define MAIL1_WRT 0x20 /* write - and next 4 words */ ++#define MAIL1_STA 0x38 /* status */ ++ ++/* On MACH_BCM270x these come through (arm_control.h ) */ ++#ifndef ARM_MS_EMPTY ++#define ARM_MS_EMPTY BIT(30) ++#define ARM_MS_FULL BIT(31) ++ ++#define ARM_MC_IHAVEDATAIRQEN BIT(0) ++#endif ++ ++#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf)) ++#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf)) ++#define MBOX_CHAN(msg) ((msg) & 0xf) ++#define MBOX_DATA28(msg) ((msg) & ~0xf) ++#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4) ++ ++#define MBOX_MAGIC 0xd0d0c0de ++ ++#define MAJOR_NUM 100 ++#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *) ++ ++static struct class *vcio_class; ++ ++struct vc_mailbox { ++ void __iomem *regs; ++ uint32_t msg[MBOX_CHAN_COUNT]; ++ struct semaphore sema[MBOX_CHAN_COUNT]; ++ uint32_t magic; ++}; ++ ++static void mbox_init(struct vc_mailbox *mbox_out) ++{ ++ int i; ++ ++ for (i = 0; i < MBOX_CHAN_COUNT; i++) { ++ mbox_out->msg[i] = 0; ++ sema_init(&mbox_out->sema[i], 0); ++ } ++ ++ /* Enable the interrupt on data reception */ ++ writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->regs + MAIL0_CNF); ++ ++ mbox_out->magic = MBOX_MAGIC; ++} ++ ++static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28) ++{ ++ if (mbox->magic != MBOX_MAGIC) ++ return -EINVAL; ++ ++ /* wait for the mailbox FIFO to have some space in it */ ++ while (0 != (readl(mbox->regs + MAIL1_STA) & ARM_MS_FULL)) ++ cpu_relax(); ++ ++ writel(MBOX_MSG(chan, data28), mbox->regs + MAIL1_WRT); ++ ++ return 0; ++} ++ ++static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28) ++{ ++ if (mbox->magic != MBOX_MAGIC) ++ return -EINVAL; ++ ++ down(&mbox->sema[chan]); ++ *data28 = MBOX_DATA28(mbox->msg[chan]); ++ mbox->msg[chan] = 0; ++ ++ return 0; ++} ++ ++static irqreturn_t mbox_irq_handler(int irq, void *dev_id) ++{ ++ /* wait for the mailbox FIFO to have some data in it */ ++ struct vc_mailbox *mbox = (struct vc_mailbox *)dev_id; ++ int status = readl(mbox->regs + MAIL0_STA); ++ int ret = IRQ_NONE; ++ ++ while (!(status & ARM_MS_EMPTY)) { ++ uint32_t msg = readl(mbox->regs + MAIL0_RD); ++ int chan = MBOX_CHAN(msg); ++ ++ if (chan < MBOX_CHAN_COUNT) { ++ if (mbox->msg[chan]) { ++ pr_err(DRIVER_NAME ++ ": mbox chan %d overflow - drop %08x\n", ++ chan, msg); ++ } else { ++ mbox->msg[chan] = (msg | 0xf); ++ up(&mbox->sema[chan]); ++ } ++ } else { ++ pr_err(DRIVER_NAME ++ ": invalid channel selector (msg %08x)\n", msg); ++ } ++ ret = IRQ_HANDLED; ++ status = readl(mbox->regs + MAIL0_STA); ++ } ++ return ret; ++} ++ ++/* Mailbox Methods */ ++ ++static struct device *mbox_dev; /* we assume there's only one! */ ++ ++static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28) ++{ ++ struct vc_mailbox *mailbox = dev_get_drvdata(dev); ++ int rc; ++ ++ device_lock(dev); ++ rc = mbox_write(mailbox, chan, data28); ++ device_unlock(dev); ++ ++ return rc; ++} ++ ++static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28) ++{ ++ struct vc_mailbox *mailbox = dev_get_drvdata(dev); ++ int rc; ++ ++ device_lock(dev); ++ rc = mbox_read(mailbox, chan, data28); ++ device_unlock(dev); ++ ++ return rc; ++} ++ ++extern int bcm_mailbox_write(unsigned chan, uint32_t data28) ++{ ++ if (!mbox_dev) ++ return -ENODEV; ++ ++ return dev_mbox_write(mbox_dev, chan, data28); ++} ++EXPORT_SYMBOL_GPL(bcm_mailbox_write); ++ ++extern int bcm_mailbox_read(unsigned chan, uint32_t *data28) ++{ ++ if (!mbox_dev) ++ return -ENODEV; ++ ++ return dev_mbox_read(mbox_dev, chan, data28); ++} ++EXPORT_SYMBOL_GPL(bcm_mailbox_read); ++ ++static int mbox_copy_from_user(void *dst, const void *src, int size) ++{ ++ if ((uint32_t)src < TASK_SIZE) ++ return copy_from_user(dst, src, size); ++ ++ memcpy(dst, src, size); ++ ++ return 0; ++} ++ ++static int mbox_copy_to_user(void *dst, const void *src, int size) ++{ ++ if ((uint32_t)dst < TASK_SIZE) ++ return copy_to_user(dst, src, size); ++ ++ memcpy(dst, src, size); ++ ++ return 0; ++} ++ ++static DEFINE_MUTEX(mailbox_lock); ++extern int bcm_mailbox_property(void *data, int size) ++{ ++ uint32_t success; ++ dma_addr_t mem_bus; /* the memory address accessed from videocore */ ++ void *mem_kern; /* the memory address accessed from driver */ ++ int s = 0; ++ ++ mutex_lock(&mailbox_lock); ++ /* allocate some memory for the messages communicating with GPU */ ++ mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, ++ GFP_KERNEL); ++ if (mem_kern) { ++ /* create the message */ ++ mbox_copy_from_user(mem_kern, data, size); ++ ++ /* send the message */ ++ wmb(); ++ s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus); ++ if (s == 0) ++ s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success); ++ if (s == 0) { ++ /* copy the response */ ++ rmb(); ++ mbox_copy_to_user(data, mem_kern, size); ++ } ++ dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus); ++ } else { ++ s = -ENOMEM; ++ } ++ if (s != 0) ++ pr_err(DRIVER_NAME ": %s failed (%d)\n", __func__, s); ++ ++ mutex_unlock(&mailbox_lock); ++ return s; ++} ++EXPORT_SYMBOL_GPL(bcm_mailbox_property); ++ ++/* Platform Device for Mailbox */ ++ ++/* ++ * Is the device open right now? Used to prevent ++ * concurent access into the same device ++ */ ++static bool device_is_open; ++ ++/* This is called whenever a process attempts to open the device file */ ++static int device_open(struct inode *inode, struct file *file) ++{ ++ /* We don't want to talk to two processes at the same time */ ++ if (device_is_open) ++ return -EBUSY; ++ ++ device_is_open = true; ++ try_module_get(THIS_MODULE); ++ ++ return 0; ++} ++ ++static int device_release(struct inode *inode, struct file *file) ++{ ++ /* We're now ready for our next caller */ ++ device_is_open = false; ++ ++ module_put(THIS_MODULE); ++ ++ return 0; ++} ++ ++/* ++ * This function is called whenever a process tries to do an ioctl on our ++ * device file. We get two extra parameters (additional to the inode and file ++ * structures, which all device functions get): the number of the ioctl called ++ * and the parameter given to the ioctl function. ++ * ++ * If the ioctl is write or read/write (meaning output is returned to the ++ * calling process), the ioctl call returns the output of this function. ++ * ++ */ ++static long device_ioctl(struct file *file, unsigned int ioctl_num, ++ unsigned long ioctl_param) ++{ ++ unsigned size; ++ ++ switch (ioctl_num) { ++ case IOCTL_MBOX_PROPERTY: ++ /* ++ * Receive a pointer to a message (in user space) and set that ++ * to be the device's message. Get the parameter given to ++ * ioctl by the process. ++ */ ++ mbox_copy_from_user(&size, (void *)ioctl_param, sizeof(size)); ++ return bcm_mailbox_property((void *)ioctl_param, size); ++ default: ++ pr_err(DRIVER_NAME "unknown ioctl: %d\n", ioctl_num); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Module Declarations */ ++ ++/* ++ * This structure will hold the functions to be called ++ * when a process does something to the device we ++ * created. Since a pointer to this structure is kept in ++ * the devices table, it can't be local to ++ * init_module. NULL is for unimplemented functios. ++ */ ++const struct file_operations fops = { ++ .unlocked_ioctl = device_ioctl, ++ .open = device_open, ++ .release = device_release, /* a.k.a. close */ ++}; ++ ++static int bcm_vcio_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device *vdev; ++ struct vc_mailbox *mailbox; ++ struct resource *res; ++ int irq, ret; ++ ++ mailbox = devm_kzalloc(dev, sizeof(*mailbox), GFP_KERNEL); ++ if (!mailbox) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mailbox->regs = devm_ioremap_resource(dev, res); ++ if (IS_ERR(mailbox->regs)) ++ return PTR_ERR(mailbox->regs); ++ ++ irq = platform_get_irq(pdev, 0); ++ ret = devm_request_irq(dev, irq, mbox_irq_handler, ++ IRQF_IRQPOLL, ++ dev_name(dev), mailbox); ++ if (ret) { ++ dev_err(dev, "Interrupt request failed %d\n", ret); ++ return ret; ++ } ++ ++ ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops); ++ if (ret < 0) { ++ pr_err("Character device registration failed %d\n", ret); ++ return ret; ++ } ++ ++ vcio_class = class_create(THIS_MODULE, DRIVER_NAME); ++ if (IS_ERR(vcio_class)) { ++ ret = PTR_ERR(vcio_class); ++ pr_err("Class creation failed %d\n", ret); ++ goto err_class; ++ } ++ ++ vdev = device_create(vcio_class, NULL, MKDEV(MAJOR_NUM, 0), NULL, ++ "vcio"); ++ if (IS_ERR(vdev)) { ++ ret = PTR_ERR(vdev); ++ pr_err("Device creation failed %d\n", ret); ++ goto err_dev; ++ } ++ ++ mbox_init(mailbox); ++ platform_set_drvdata(pdev, mailbox); ++ mbox_dev = dev; ++ ++ dev_info(dev, "mailbox at %p\n", mailbox->regs); ++ ++ return 0; ++ ++err_dev: ++ class_destroy(vcio_class); ++err_class: ++ unregister_chrdev(MAJOR_NUM, DEVICE_FILE_NAME); ++ ++ return ret; ++} ++ ++static int bcm_vcio_remove(struct platform_device *pdev) ++{ ++ mbox_dev = NULL; ++ platform_set_drvdata(pdev, NULL); ++ device_destroy(vcio_class, MKDEV(MAJOR_NUM, 0)); ++ class_destroy(vcio_class); ++ unregister_chrdev(MAJOR_NUM, DEVICE_FILE_NAME); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm_vcio_of_match_table[] = { ++ { .compatible = "brcm,bcm2708-vcio", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm_vcio_of_match_table); ++ ++static struct platform_driver bcm_mbox_driver = { ++ .probe = bcm_vcio_probe, ++ .remove = bcm_vcio_remove, ++ ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm_vcio_of_match_table, ++ }, ++}; ++ ++static int __init bcm_mbox_init(void) ++{ ++ return platform_driver_register(&bcm_mbox_driver); ++} ++ ++static void __exit bcm_mbox_exit(void) ++{ ++ platform_driver_unregister(&bcm_mbox_driver); ++} ++ ++arch_initcall(bcm_mbox_init); /* Initialize early */ ++module_exit(bcm_mbox_exit); ++ ++MODULE_AUTHOR("Gray Girling"); ++MODULE_DESCRIPTION("ARM I/O to VideoCore processor"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/include/linux/platform_data/mailbox-bcm2708.h +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#ifndef _PLAT_MAILBOX_BCM2708_H ++#define _PLAT_MAILBOX_BCM2708_H ++ ++/* Routines to handle I/O via the VideoCore "ARM control" registers ++ * (semaphores, doorbells, mailboxes) ++ */ ++ ++/* Constants shared with the ARM identifying separate mailbox channels */ ++#define MBOX_CHAN_POWER 0 /* for use by the power management interface */ ++#define MBOX_CHAN_FB 1 /* for use by the frame buffer */ ++#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */ ++#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */ ++#define MBOX_CHAN_COUNT 9 ++ ++enum { ++ VCMSG_PROCESS_REQUEST = 0x00000000 ++}; ++ ++enum { ++ VCMSG_REQUEST_SUCCESSFUL = 0x80000000, ++ VCMSG_REQUEST_FAILED = 0x80000001 ++}; ++ ++/* Mailbox property tags */ ++enum { ++ VCMSG_PROPERTY_END = 0x00000000, ++ VCMSG_GET_FIRMWARE_REVISION = 0x00000001, ++ VCMSG_GET_BOARD_MODEL = 0x00010001, ++ VCMSG_GET_BOARD_REVISION = 0x00010002, ++ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003, ++ VCMSG_GET_BOARD_SERIAL = 0x00010004, ++ VCMSG_GET_ARM_MEMORY = 0x00010005, ++ VCMSG_GET_VC_MEMORY = 0x00010006, ++ VCMSG_GET_CLOCKS = 0x00010007, ++ VCMSG_GET_COMMAND_LINE = 0x00050001, ++ VCMSG_GET_DMA_CHANNELS = 0x00060001, ++ VCMSG_GET_POWER_STATE = 0x00020001, ++ VCMSG_GET_TIMING = 0x00020002, ++ VCMSG_SET_POWER_STATE = 0x00028001, ++ VCMSG_GET_CLOCK_STATE = 0x00030001, ++ VCMSG_SET_CLOCK_STATE = 0x00038001, ++ VCMSG_GET_CLOCK_RATE = 0x00030002, ++ VCMSG_SET_CLOCK_RATE = 0x00038002, ++ VCMSG_GET_VOLTAGE = 0x00030003, ++ VCMSG_SET_VOLTAGE = 0x00038003, ++ VCMSG_GET_MAX_CLOCK = 0x00030004, ++ VCMSG_GET_MAX_VOLTAGE = 0x00030005, ++ VCMSG_GET_TEMPERATURE = 0x00030006, ++ VCMSG_GET_MIN_CLOCK = 0x00030007, ++ VCMSG_GET_MIN_VOLTAGE = 0x00030008, ++ VCMSG_GET_TURBO = 0x00030009, ++ VCMSG_GET_MAX_TEMPERATURE = 0x0003000a, ++ VCMSG_GET_STC = 0x0003000b, ++ VCMSG_SET_TURBO = 0x00038009, ++ VCMSG_SET_ALLOCATE_MEM = 0x0003000c, ++ VCMSG_SET_LOCK_MEM = 0x0003000d, ++ VCMSG_SET_UNLOCK_MEM = 0x0003000e, ++ VCMSG_SET_RELEASE_MEM = 0x0003000f, ++ VCMSG_SET_EXECUTE_CODE = 0x00030010, ++ VCMSG_SET_EXECUTE_QPU = 0x00030011, ++ VCMSG_SET_ENABLE_QPU = 0x00030012, ++ VCMSG_GET_RESOURCE_HANDLE = 0x00030014, ++ VCMSG_GET_EDID_BLOCK = 0x00030020, ++ VCMSG_GET_CUSTOMER_OTP = 0x00030021, ++ VCMSG_SET_CUSTOMER_OTP = 0x00038021, ++ VCMSG_SET_ALLOCATE_BUFFER = 0x00040001, ++ VCMSG_SET_RELEASE_BUFFER = 0x00048001, ++ VCMSG_SET_BLANK_SCREEN = 0x00040002, ++ VCMSG_TST_BLANK_SCREEN = 0x00044002, ++ VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003, ++ VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003, ++ VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003, ++ VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004, ++ VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004, ++ VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004, ++ VCMSG_GET_DEPTH = 0x00040005, ++ VCMSG_TST_DEPTH = 0x00044005, ++ VCMSG_SET_DEPTH = 0x00048005, ++ VCMSG_GET_PIXEL_ORDER = 0x00040006, ++ VCMSG_TST_PIXEL_ORDER = 0x00044006, ++ VCMSG_SET_PIXEL_ORDER = 0x00048006, ++ VCMSG_GET_ALPHA_MODE = 0x00040007, ++ VCMSG_TST_ALPHA_MODE = 0x00044007, ++ VCMSG_SET_ALPHA_MODE = 0x00048007, ++ VCMSG_GET_PITCH = 0x00040008, ++ VCMSG_TST_PITCH = 0x00044008, ++ VCMSG_SET_PITCH = 0x00048008, ++ VCMSG_GET_VIRTUAL_OFFSET = 0x00040009, ++ VCMSG_TST_VIRTUAL_OFFSET = 0x00044009, ++ VCMSG_SET_VIRTUAL_OFFSET = 0x00048009, ++ VCMSG_GET_OVERSCAN = 0x0004000a, ++ VCMSG_TST_OVERSCAN = 0x0004400a, ++ VCMSG_SET_OVERSCAN = 0x0004800a, ++ VCMSG_GET_PALETTE = 0x0004000b, ++ VCMSG_TST_PALETTE = 0x0004400b, ++ VCMSG_SET_PALETTE = 0x0004800b, ++ VCMSG_GET_LAYER = 0x0004000c, ++ VCMSG_TST_LAYER = 0x0004400c, ++ VCMSG_SET_LAYER = 0x0004800c, ++ VCMSG_GET_TRANSFORM = 0x0004000d, ++ VCMSG_TST_TRANSFORM = 0x0004400d, ++ VCMSG_SET_TRANSFORM = 0x0004800d, ++ VCMSG_TST_VSYNC = 0x0004400e, ++ VCMSG_SET_VSYNC = 0x0004800e, ++ VCMSG_SET_CURSOR_INFO = 0x00008010, ++ VCMSG_SET_CURSOR_STATE = 0x00008011, ++}; ++ ++int bcm_mailbox_read(unsigned chan, uint32_t *data28); ++int bcm_mailbox_write(unsigned chan, uint32_t data28); ++int bcm_mailbox_property(void *data, int size); ++ ++#endif diff --git a/target/linux/brcm2708/patches-4.1/0004-Add-dwc_otg-driver.patch b/target/linux/brcm2708/patches-4.1/0004-Add-dwc_otg-driver.patch new file mode 100644 index 0000000..fefc9e9 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0004-Add-dwc_otg-driver.patch @@ -0,0 +1,61067 @@ +From bd316831fe1a05b9306054d48fb48db5226a6c92 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 1 May 2013 19:46:17 +0100 +Subject: [PATCH 004/203] Add dwc_otg driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: popcornmix + +usb: dwc: fix lockdep false positive + +Signed-off-by: Kari Suvanto + +usb: dwc: fix inconsistent lock state + +Signed-off-by: Kari Suvanto + +Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance. +Thanks to Gordon and Costas + +Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005. + +Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh + +Make sure we wait for the reset to finish + +dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel + memory corruption, escalating to OOPS under high USB load. + +dwc_otg: Fix unsafe access of QTD during URB enqueue + +In dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the +transaction could complete almost immediately after the qtd was assigned +to a host channel during URB enqueue, which meant the qtd pointer was no +longer valid having been completed and removed. Usually, this resulted in +an OOPS during URB submission. By predetermining whether transactions +need to be queued or not, this unsafe pointer access is avoided. + +This bug was only evident on the Pi model A where a device was attached +that had no periodic endpoints (e.g. USB pendrive or some wlan devices). + +dwc_otg: Fix incorrect URB allocation error handling + +If the memory allocation for a dwc_otg_urb failed, the kernel would OOPS +because for some reason a member of the *unallocated* struct was set to +zero. Error handling changed to fail correctly. + +dwc_otg: fix potential use-after-free case in interrupt handler + +If a transaction had previously aborted, certain interrupts are +enabled to track error counts and reset where necessary. On IN +endpoints the host generates an ACK interrupt near-simultaneously +with completion of transfer. In the case where this transfer had +previously had an error, this results in a use-after-free on +the QTD memory space with a 1-byte length being overwritten to +0x00. + +dwc_otg: add handling of SPLIT transaction data toggle errors + +Previously a data toggle error on packets from a USB1.1 device behind +a TT would result in the Pi locking up as the driver never handled +the associated interrupt. Patch adds basic retry mechanism and +interrupt acknowledgement to cater for either a chance toggle error or +for devices that have a broken initial toggle state (FT8U232/FT232BM). + +dwc_otg: implement tasklet for returning URBs to usbcore hcd layer + +The dwc_otg driver interrupt handler for transfer completion will spend +a very long time with interrupts disabled when a URB is completed - +this is because usb_hcd_giveback_urb is called from within the handler +which for a USB device driver with complicated processing (e.g. webcam) +will take an exorbitant amount of time to complete. This results in +missed completion interrupts for other USB packets which lead to them +being dropped due to microframe overruns. + +This patch splits returning the URB to the usb hcd layer into a +high-priority tasklet. This will have most benefit for isochronous IN +transfers but will also have incidental benefit where multiple periodic +devices are active at once. + +dwc_otg: fix NAK holdoff and allow on split transactions only + +This corrects a bug where if a single active non-periodic endpoint +had at least one transaction in its qh, on frnum == MAX_FRNUM the qh +would get skipped and never get queued again. This would result in +a silent device until error detection (automatic or otherwise) would +either reset the device or flush and requeue the URBs. + +Additionally the NAK holdoff was enabled for all transactions - this +would potentially stall a HS endpoint for 1ms if a previous error state +enabled this interrupt and the next response was a NAK. Fix so that +only split transactions get held off. + +dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler + +usb_hcd_unlink_urb_from_ep must be called with the HCD lock held. Calling it +asynchronously in the tasklet was not safe (regression in +c4564d4a1a0a9b10d4419e48239f5d99e88d2667). + +This change unlinks it from the endpoint prior to queueing it for handling in +the tasklet, and also adds a check to ensure the urb is OK to be unlinked +before doing so. + +NULL pointer dereference kernel oopses had been observed in usb_hcd_giveback_urb +when a USB device was unplugged/replugged during data transfer. This effect +was reproduced using automated USB port power control, hundreds of replug +events were performed during active transfers to confirm that the problem was +eliminated. + +USB fix using a FIQ to implement split transactions + +This commit adds a FIQ implementaion that schedules +the split transactions using a FIQ so we don't get +held off by the interrupt latency of Linux + +dwc_otg: fix device attributes and avoid kernel warnings on boot + +dcw_otg: avoid logging function that can cause panics + +See: https://github.com/raspberrypi/firmware/issues/21 +Thanks to cleverca22 for fix + +dwc_otg: mask correct interrupts after transaction error recovery + +The dwc_otg driver will unmask certain interrupts on a transaction +that previously halted in the error state in order to reset the +QTD error count. The various fine-grained interrupt handlers do not +consider that other interrupts besides themselves were unmasked. + +By disabling the two other interrupts only ever enabled in DMA mode +for this purpose, we can avoid unnecessary function calls in the +IRQ handler. This will also prevent an unneccesary FIQ interrupt +from being generated if the FIQ is enabled. + +dwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ + +In the case of a transaction to a device that had previously aborted +due to an error, several interrupts are enabled to reset the error +count when a device responds. This has the side-effect of making the +FIQ thrash because the hardware will generate multiple instances of +a NAK on an IN bulk/interrupt endpoint and multiple instances of ACK +on an OUT bulk/interrupt endpoint. Make the FIQ mask and clear the +associated interrupts. + +Additionally, on non-split transactions make sure that only unmasked +interrupts are cleared. This caused a hard-to-trigger but serious +race condition when you had the combination of an endpoint awaiting +error recovery and a transaction completed on an endpoint - due to +the sequencing and timing of interrupts generated by the dwc_otg core, +it was possible to confuse the IRQ handler. + +Fix function tracing + +dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue + +dwc_otg: prevent OOPSes during device disconnects + +The dwc_otg_urb_enqueue function is thread-unsafe. In particular the +access of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and +friends does not occur within a critical section and so if a device +was unplugged during activity there was a high chance that the +usbcore hub_thread would try to disable the endpoint with partially- +formed entries in the URB queue. This would result in BUG() or null +pointer dereferences. + +Fix so that access of urb->hcpriv, enqueuing to the hardware and +adding to usbcore endpoint URB lists is contained within a single +critical section. + +dwc_otg: prevent BUG() in TT allocation if hub address is > 16 + +A fixed-size array is used to track TT allocation. This was +previously set to 16 which caused a crash because +dwc_otg_hcd_allocate_port would read past the end of the array. + +This was hit if a hub was plugged in which enumerated as addr > 16, +due to previous device resets or unplugs. + +Also add #ifdef FIQ_DEBUG around hcd->hub_port_alloc[], which grows +to a large size if 128 hub addresses are supported. This field is +for debug only for tracking which frame an allocate happened in. + +dwc_otg: make channel halts with unknown state less damaging + +If the IRQ received a channel halt interrupt through the FIQ +with no other bits set, the IRQ would not release the host +channel and never complete the URB. + +Add catchall handling to treat as a transaction error and retry. + +dwc_otg: fiq_split: use TTs with more granularity + +This fixes certain issues with split transaction scheduling. + +- Isochronous multi-packet OUT transactions now hog the TT until + they are completed - this prevents hubs aborting transactions + if they get a periodic start-split out-of-order +- Don't perform TT allocation on non-periodic endpoints - this + allows simultaneous use of the TT's bulk/control and periodic + transaction buffers + +This commit will mainly affect USB audio playback. + +dwc_otg: fix potential sleep while atomic during urb enqueue + +Fixes a regression introduced with eb1b482a. Kmalloc called from +dwc_otg_hcd_qtd_add / dwc_otg_hcd_qtd_create did not always have +the GPF_ATOMIC flag set. Force this flag when inside the larger +critical section. + +dwc_otg: make fiq_split_enable imply fiq_fix_enable + +Failing to set up the FIQ correctly would result in +"IRQ 32: nobody cared" errors in dmesg. + +dwc_otg: prevent crashes on host port disconnects + +Fix several issues resulting in crashes or inconsistent state +if a Model A root port was disconnected. + +- Clean up queue heads properly in kill_urbs_in_qh_list by + removing the empty QHs from the schedule lists +- Set the halt status properly to prevent IRQ handlers from + using freed memory +- Add fiq_split related cleanup for saved registers +- Make microframe scheduling reclaim host channels if + active during a disconnect +- Abort URBs with -ESHUTDOWN status response, informing + device drivers so they respond in a more correct fashion + and don't try to resubmit URBs +- Prevent IRQ handlers from attempting to handle channel + interrupts if the associated URB was dequeued (and the + driver state was cleared) + +dwc_otg: prevent leaking URBs during enqueue + +A dwc_otg_urb would get leaked if the HCD enqueue function +failed for any reason. Free the URB at the appropriate points. + +dwc_otg: Enable NAK holdoff for control split transactions + +Certain low-speed devices take a very long time to complete a +data or status stage of a control transaction, producing NAK +responses until they complete internal processing - the USB2.0 +spec limit is up to 500mS. This causes the same type of interrupt +storm as seen with USB-serial dongles prior to c8edb238. + +In certain circumstances, usually while booting, this interrupt +storm could cause SD card timeouts. + +dwc_otg: Fix for occasional lockup on boot when doing a USB reset + +dwc_otg: Don't issue traffic to LS devices in FS mode + +Issuing low-speed packets when the root port is in full-speed mode +causes the root port to stop responding. Explicitly fail when +enqueuing URBs to a LS endpoint on a FS bus. + +Fix ARM architecture issue with local_irq_restore() + +If local_fiq_enable() is called before a local_irq_restore(flags) where +the flags variable has the F bit set, the FIQ will be erroneously disabled. + +Fixup arch_local_irq_restore to avoid trampling the F bit in CPSR. + +Also fix some of the hacks previously implemented for previous dwc_otg +incarnations. + +dwc_otg: fiq_fsm: Base commit for driver rewrite + +This commit removes the previous FIQ fixes entirely and adds fiq_fsm. + +This rewrite features much more complete support for split transactions +and takes into account several OTG hardware bugs. High-speed +isochronous transactions are also capable of being performed by fiq_fsm. + +All driver options have been removed and replaced with: + - dwc_otg.fiq_enable (bool) + - dwc_otg.fiq_fsm_enable (bool) + - dwc_otg.fiq_fsm_mask (bitmask) + - dwc_otg.nak_holdoff (unsigned int) + +Defaults are specified such that fiq_fsm behaves similarly to the +previously implemented FIQ fixes. + +fiq_fsm: Push error recovery into the FIQ when fiq_fsm is used + +If the transfer associated with a QTD failed due to a bus error, the HCD +would retry the transfer up to 3 times (implementing the USB2.0 +three-strikes retry in software). + +Due to the masking mechanism used by fiq_fsm, it is only possible to pass +a single interrupt through to the HCD per-transfer. + +In this instance host channels would fall off the radar because the error +reset would function, but the subsequent channel halt would be lost. + +Push the error count reset into the FIQ handler. + +fiq_fsm: Implement timeout mechanism + +For full-speed endpoints with a large packet size, interrupt latency +runs the risk of the FIQ starting a transaction too late in a full-speed +frame. If the device is still transmitting data when EOF2 for the +downstream frame occurs, the hub will disable the port. This change is +not reflected in the hub status endpoint and the device becomes +unresponsive. + +Prevent high-bandwidth transactions from being started too late in a +frame. The mechanism is not guaranteed: a combination of bit stuffing +and hub latency may still result in a device overrunning. + +fiq_fsm: fix bounce buffer utilisation for Isochronous OUT + +Multi-packet isochronous OUT transactions were subject to a few bounday +bugs. Fix them. + +Audio playback is now much more robust: however, an issue stands with +devices that have adaptive sinks - ALSA plays samples too fast. + +dwc_otg: Return full-speed frame numbers in HS mode + +The frame counter increments on every *microframe* in high-speed mode. +Most device drivers expect this number to be in full-speed frames - this +caused considerable confusion to e.g. snd_usb_audio which uses the +frame counter to estimate the number of samples played. + +fiq_fsm: save PID on completion of interrupt OUT transfers + +Also add edge case handling for interrupt transports. + +Note that for periodic split IN, data toggles are unimplemented in the +OTG host hardware - it unconditionally accepts any PID. + +fiq_fsm: add missing case for fiq_fsm_tt_in_use() + +Certain combinations of bitrate and endpoint activity could +result in a periodic transaction erroneously getting started +while the previous Isochronous OUT was still active. + +fiq_fsm: clear hcintmsk for aborted transactions + +Prevents the FIQ from erroneously handling interrupts +on a timed out channel. + +fiq_fsm: enable by default + +fiq_fsm: fix dequeues for non-periodic split transactions + +If a dequeue happened between the SSPLIT and CSPLIT phases of the +transaction, the HCD would never receive an interrupt. + +fiq_fsm: Disable by default + +fiq_fsm: Handle HC babble errors + +The HCTSIZ transfer size field raises a babble interrupt if +the counter wraps. Handle the resulting interrupt in this case. + +dwc_otg: fix interrupt registration for fiq_enable=0 + +Additionally make the module parameter conditional for wherever +hcd->fiq_state is touched. + +fiq_fsm: Enable by default + +dwc_otg: Fix various issues with root port and transaction errors + +Process the host port interrupts correctly (and don't trample them). +Root port hotplug now functional again. + +Fix a few thinkos with the transaction error passthrough for fiq_fsm. + +fiq_fsm: Implement hack for Split Interrupt transactions + +Hubs aren't too picky about which endpoint we send Control type split +transactions to. By treating Interrupt transfers as Control, it is +possible to use the non-periodic queue in the OTG core as well as the +non-periodic FIFOs in the hub itself. This massively reduces the +microframe exclusivity/contention that periodic split transactions +otherwise have to enforce. + +It goes without saying that this is a fairly egregious USB specification +violation, but it works. + +Original idea by Hans Petter Selasky @ FreeBSD.org. + +dwc_otg: FIQ support on SMP. Set up FIQ stack and handler on Core 0 only. + +dwc_otg: introduce fiq_fsm_spin(un|)lock() + +SMP safety for the FIQ relies on register read-modify write cycles being +completed in the correct order. Several places in the DWC code modify +registers also touched by the FIQ. Protect these by a bare-bones lock +mechanism. + +This also makes it possible to run the FIQ and IRQ handlers on different +cores. + +fiq_fsm: fix build on bcm2708 and bcm2709 platforms + +dwc_otg: put some barriers back where they should be for UP + +bcm2709/dwc_otg: Setup FIQ on core 1 if >1 core active + +dwc_otg: fixup read-modify-write in critical paths + +Be more careful about read-modify-write on registers that the FIQ +also touches. + +Guard fiq_fsm_spin_lock with fiq_enable check + +fiq_fsm: Falling out of the state machine isn't fatal + +This edge case can be hit if the port is disabled while the FIQ is +in the middle of a transaction. Make the effects less severe. + +Also get rid of the useless return value. + +squash: dwc_otg: Allow to build without SMP + +usb: core: make overcurrent messages more prominent + +Hub overcurrent messages are more serious than "debug". Increase loglevel. + +usb: dwc_otg: Don't use dma_to_virt() + +Commit 6ce0d20 changes dma_to_virt() which breaks this driver. +Open code the old dma_to_virt() implementation to work around this. + +Limit the use of __bus_to_virt() to cases where transfer_buffer_length +is set and transfer_buffer is not set. This is done to increase the +chance that this driver will also work on ARCH_BCM2835. + +transfer_buffer should not be NULL if the length is set, but the +comment in the code indicates that there are situations where this +might happen. drivers/usb/isp1760/isp1760-hcd.c also has a similar +comment pointing to a possible: 'usb storage / SCSI bug'. + +Signed-off-by: Noralf Trønnes + +dwc_otg: Fix crash when fiq_enable=0 +--- + arch/arm/include/asm/irqflags.h | 16 +- + arch/arm/kernel/fiqasm.S | 4 + + arch/arm/mach-bcm2708/armctrl.c | 19 +- + arch/arm/mach-bcm2708/bcm2708.c | 11 + + arch/arm/mach-bcm2708/include/mach/irqs.h | 153 +- + arch/arm/mach-bcm2709/armctrl.c | 10 +- + drivers/usb/Makefile | 1 + + drivers/usb/core/generic.c | 1 + + drivers/usb/core/hub.c | 2 +- + drivers/usb/core/message.c | 79 + + drivers/usb/core/otg_whitelist.h | 114 +- + drivers/usb/gadget/file_storage.c | 3676 ++++++++++ + drivers/usb/host/Kconfig | 13 + + drivers/usb/host/Makefile | 2 + + drivers/usb/host/dwc_common_port/Makefile | 58 + + drivers/usb/host/dwc_common_port/Makefile.fbsd | 17 + + drivers/usb/host/dwc_common_port/Makefile.linux | 49 + + drivers/usb/host/dwc_common_port/changes.txt | 174 + + drivers/usb/host/dwc_common_port/doc/doxygen.cfg | 270 + + drivers/usb/host/dwc_common_port/dwc_cc.c | 532 ++ + drivers/usb/host/dwc_common_port/dwc_cc.h | 224 + + drivers/usb/host/dwc_common_port/dwc_common_fbsd.c | 1308 ++++ + .../usb/host/dwc_common_port/dwc_common_linux.c | 1434 ++++ + drivers/usb/host/dwc_common_port/dwc_common_nbsd.c | 1275 ++++ + drivers/usb/host/dwc_common_port/dwc_crypto.c | 308 + + drivers/usb/host/dwc_common_port/dwc_crypto.h | 111 + + drivers/usb/host/dwc_common_port/dwc_dh.c | 291 + + drivers/usb/host/dwc_common_port/dwc_dh.h | 106 + + drivers/usb/host/dwc_common_port/dwc_list.h | 594 ++ + drivers/usb/host/dwc_common_port/dwc_mem.c | 245 + + drivers/usb/host/dwc_common_port/dwc_modpow.c | 636 ++ + drivers/usb/host/dwc_common_port/dwc_modpow.h | 34 + + drivers/usb/host/dwc_common_port/dwc_notifier.c | 319 + + drivers/usb/host/dwc_common_port/dwc_notifier.h | 122 + + drivers/usb/host/dwc_common_port/dwc_os.h | 1276 ++++ + drivers/usb/host/dwc_common_port/usb.h | 946 +++ + drivers/usb/host/dwc_otg/Makefile | 82 + + drivers/usb/host/dwc_otg/doc/doxygen.cfg | 224 + + drivers/usb/host/dwc_otg/dummy_audio.c | 1575 +++++ + drivers/usb/host/dwc_otg/dwc_cfi_common.h | 142 + + drivers/usb/host/dwc_otg/dwc_otg_adp.c | 854 +++ + drivers/usb/host/dwc_otg/dwc_otg_adp.h | 80 + + drivers/usb/host/dwc_otg/dwc_otg_attr.c | 1210 ++++ + drivers/usb/host/dwc_otg/dwc_otg_attr.h | 89 + + drivers/usb/host/dwc_otg/dwc_otg_cfi.c | 1876 +++++ + drivers/usb/host/dwc_otg/dwc_otg_cfi.h | 320 + + drivers/usb/host/dwc_otg/dwc_otg_cil.c | 7141 ++++++++++++++++++++ + drivers/usb/host/dwc_otg/dwc_otg_cil.h | 1464 ++++ + drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 1594 +++++ + drivers/usb/host/dwc_otg/dwc_otg_core_if.h | 705 ++ + drivers/usb/host/dwc_otg/dwc_otg_dbg.h | 117 + + drivers/usb/host/dwc_otg/dwc_otg_driver.c | 1756 +++++ + drivers/usb/host/dwc_otg/dwc_otg_driver.h | 86 + + drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 1346 ++++ + drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 367 + + drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S | 80 + + drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 4252 ++++++++++++ + drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 862 +++ + drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c | 1132 ++++ + drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h | 417 ++ + drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2713 ++++++++ + drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 995 +++ + drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 957 +++ + drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 188 + + drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 2712 ++++++++ + drivers/usb/host/dwc_otg/dwc_otg_pcd.h | 266 + + drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h | 360 + + drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c | 5147 ++++++++++++++ + drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c | 1360 ++++ + drivers/usb/host/dwc_otg/dwc_otg_regs.h | 2550 +++++++ + drivers/usb/host/dwc_otg/test/Makefile | 16 + + drivers/usb/host/dwc_otg/test/dwc_otg_test.pm | 337 + + drivers/usb/host/dwc_otg/test/test_mod_param.pl | 133 + + drivers/usb/host/dwc_otg/test/test_sysfs.pl | 193 + + 74 files changed, 60032 insertions(+), 96 deletions(-) + create mode 100644 drivers/usb/gadget/file_storage.c + create mode 100644 drivers/usb/host/dwc_common_port/Makefile + create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd + create mode 100644 drivers/usb/host/dwc_common_port/Makefile.linux + create mode 100644 drivers/usb/host/dwc_common_port/changes.txt + create mode 100644 drivers/usb/host/dwc_common_port/doc/doxygen.cfg + create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.h + create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_linux.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.h + create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.h + create mode 100644 drivers/usb/host/dwc_common_port/dwc_list.h + create mode 100644 drivers/usb/host/dwc_common_port/dwc_mem.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.h + create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.c + create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.h + create mode 100644 drivers/usb/host/dwc_common_port/dwc_os.h + create mode 100644 drivers/usb/host/dwc_common_port/usb.h + create mode 100644 drivers/usb/host/dwc_otg/Makefile + create mode 100644 drivers/usb/host/dwc_otg/doc/doxygen.cfg + create mode 100644 drivers/usb/host/dwc_otg/dummy_audio.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_cfi_common.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_core_if.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_dbg.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c + create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_regs.h + create mode 100644 drivers/usb/host/dwc_otg/test/Makefile + create mode 100644 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm + create mode 100644 drivers/usb/host/dwc_otg/test/test_mod_param.pl + create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl + +--- a/arch/arm/include/asm/irqflags.h ++++ b/arch/arm/include/asm/irqflags.h +@@ -145,12 +145,22 @@ static inline unsigned long arch_local_s + } + + /* +- * restore saved IRQ & FIQ state ++ * restore saved IRQ state + */ + static inline void arch_local_irq_restore(unsigned long flags) + { +- asm volatile( +- " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" ++ unsigned long temp = 0; ++ flags &= ~(1 << 6); ++ asm volatile ( ++ " mrs %0, cpsr" ++ : "=r" (temp) ++ : ++ : "memory", "cc"); ++ /* Preserve FIQ bit */ ++ temp &= (1 << 6); ++ flags = flags | temp; ++ asm volatile ( ++ " msr cpsr_c, %0 @ local_irq_restore" + : + : "r" (flags) + : "memory", "cc"); +--- a/arch/arm/kernel/fiqasm.S ++++ b/arch/arm/kernel/fiqasm.S +@@ -47,3 +47,7 @@ ENTRY(__get_fiq_regs) + mov r0, r0 @ avoid hazard prior to ARMv4 + ret lr + ENDPROC(__get_fiq_regs) ++ ++ENTRY(__FIQ_Branch) ++ mov pc, r8 ++ENDPROC(__FIQ_Branch) +--- a/arch/arm/mach-bcm2708/armctrl.c ++++ b/arch/arm/mach-bcm2708/armctrl.c +@@ -54,8 +54,12 @@ static void armctrl_mask_irq(struct irq_ + 0 + }; + +- unsigned int data = (unsigned int)irq_get_chip_data(d->irq); +- writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); ++ if (d->irq >= FIQ_START) { ++ writel(0, __io_address(ARM_IRQ_FAST)); ++ } else { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); ++ } + } + + static void armctrl_unmask_irq(struct irq_data *d) +@@ -67,8 +71,14 @@ static void armctrl_unmask_irq(struct ir + 0 + }; + +- unsigned int data = (unsigned int)irq_get_chip_data(d->irq); +- writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); ++ if (d->irq >= FIQ_START) { ++ unsigned int data = ++ (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; ++ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); ++ } else { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); ++ } + } + + #ifdef CONFIG_OF +@@ -299,6 +309,7 @@ int __init armctrl_init(void __iomem * b + } + + armctrl_pm_register(base, irq_start, resume_sources); ++ init_FIQ(FIQ_START); + armctrl_dt_init(); + return 0; + } +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -254,12 +254,23 @@ static struct resource bcm2708_usb_resou + .flags = IORESOURCE_MEM, + }, + [1] = { ++ .start = MPHI_BASE, ++ .end = MPHI_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = IRQ_HOSTPORT, ++ .end = IRQ_HOSTPORT, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [3] = { + .start = IRQ_USB, + .end = IRQ_USB, + .flags = IORESOURCE_IRQ, + }, + }; + ++ + static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_usb_device = { +--- a/arch/arm/mach-bcm2708/include/mach/irqs.h ++++ b/arch/arm/mach-bcm2708/include/mach/irqs.h +@@ -106,87 +106,90 @@ + #define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) + #define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) + ++#define FIQ_START HARD_IRQS ++ + /* + * FIQ interrupts definitions are the same as the INT definitions. + */ +-#define FIQ_TIMER0 INT_TIMER0 +-#define FIQ_TIMER1 INT_TIMER1 +-#define FIQ_TIMER2 INT_TIMER2 +-#define FIQ_TIMER3 INT_TIMER3 +-#define FIQ_CODEC0 INT_CODEC0 +-#define FIQ_CODEC1 INT_CODEC1 +-#define FIQ_CODEC2 INT_CODEC2 +-#define FIQ_JPEG INT_JPEG +-#define FIQ_ISP INT_ISP +-#define FIQ_USB INT_USB +-#define FIQ_3D INT_3D +-#define FIQ_TRANSPOSER INT_TRANSPOSER +-#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0 +-#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1 +-#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2 +-#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3 +-#define FIQ_DMA0 INT_DMA0 +-#define FIQ_DMA1 INT_DMA1 +-#define FIQ_DMA2 INT_DMA2 +-#define FIQ_DMA3 INT_DMA3 +-#define FIQ_DMA4 INT_DMA4 +-#define FIQ_DMA5 INT_DMA5 +-#define FIQ_DMA6 INT_DMA6 +-#define FIQ_DMA7 INT_DMA7 +-#define FIQ_DMA8 INT_DMA8 +-#define FIQ_DMA9 INT_DMA9 +-#define FIQ_DMA10 INT_DMA10 +-#define FIQ_DMA11 INT_DMA11 +-#define FIQ_DMA12 INT_DMA12 +-#define FIQ_AUX INT_AUX +-#define FIQ_ARM INT_ARM +-#define FIQ_VPUDMA INT_VPUDMA +-#define FIQ_HOSTPORT INT_HOSTPORT +-#define FIQ_VIDEOSCALER INT_VIDEOSCALER +-#define FIQ_CCP2TX INT_CCP2TX +-#define FIQ_SDC INT_SDC +-#define FIQ_DSI0 INT_DSI0 +-#define FIQ_AVE INT_AVE +-#define FIQ_CAM0 INT_CAM0 +-#define FIQ_CAM1 INT_CAM1 +-#define FIQ_HDMI0 INT_HDMI0 +-#define FIQ_HDMI1 INT_HDMI1 +-#define FIQ_PIXELVALVE1 INT_PIXELVALVE1 +-#define FIQ_I2CSPISLV INT_I2CSPISLV +-#define FIQ_DSI1 INT_DSI1 +-#define FIQ_PWA0 INT_PWA0 +-#define FIQ_PWA1 INT_PWA1 +-#define FIQ_CPR INT_CPR +-#define FIQ_SMI INT_SMI +-#define FIQ_GPIO0 INT_GPIO0 +-#define FIQ_GPIO1 INT_GPIO1 +-#define FIQ_GPIO2 INT_GPIO2 +-#define FIQ_GPIO3 INT_GPIO3 +-#define FIQ_I2C INT_I2C +-#define FIQ_SPI INT_SPI +-#define FIQ_I2SPCM INT_I2SPCM +-#define FIQ_SDIO INT_SDIO +-#define FIQ_UART INT_UART +-#define FIQ_SLIMBUS INT_SLIMBUS +-#define FIQ_VEC INT_VEC +-#define FIQ_CPG INT_CPG +-#define FIQ_RNG INT_RNG +-#define FIQ_ARASANSDIO INT_ARASANSDIO +-#define FIQ_AVSPMON INT_AVSPMON ++#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) ++#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) ++#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) ++#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) ++#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) ++#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) ++#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) ++#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) ++#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) ++#define FIQ_USB (FIQ_START+INTERRUPT_USB) ++#define FIQ_3D (FIQ_START+INTERRUPT_3D) ++#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) ++#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) ++#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) ++#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) ++#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) ++#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) ++#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) ++#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) ++#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) ++#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) ++#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) ++#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) ++#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) ++#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) ++#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) ++#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) ++#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) ++#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) ++#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) ++#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) ++#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) ++#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) ++#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) ++#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) ++#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) ++#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) ++#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) ++#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) ++#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) ++#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) ++#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) ++#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) ++#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) ++#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) ++#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) ++#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) ++#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) ++#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) ++#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) ++#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) ++#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) ++#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) ++#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) ++#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) ++#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) ++#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) ++#define FIQ_UART (FIQ_START+INTERRUPT_UART) ++#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) ++#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) ++#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) ++#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) ++#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) ++#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) + +-#define FIQ_ARM_TIMER INT_ARM_TIMER +-#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX +-#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0 +-#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1 +-#define FIQ_VPU0_HALTED INT_VPU0_HALTED +-#define FIQ_VPU1_HALTED INT_VPU1_HALTED +-#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0 +-#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1 +-#define FIQ_PENDING1 INT_PENDING1 +-#define FIQ_PENDING2 INT_PENDING2 ++#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) ++#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) ++#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) ++#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) ++#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) ++#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) ++#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) ++#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) ++#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) ++#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) + + #define HARD_IRQS (64 + 21) +-#define GPIO_IRQ_START (HARD_IRQS) ++#define FIQ_IRQS (64 + 21) ++#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) + #define GPIO_IRQS (32*5) + #define SPARE_ALLOC_IRQS 64 + #define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) +--- a/arch/arm/mach-bcm2709/armctrl.c ++++ b/arch/arm/mach-bcm2709/armctrl.c +@@ -91,7 +91,15 @@ static void armctrl_unmask_irq(struct ir + }; + int i; + if (d->irq >= FIQ_START) { +- unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; ++ unsigned int data; ++ if (num_online_cpus() > 1) { ++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ data &= ~0xc; ++ data |= (1 << 2); ++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ } ++ /* Unmask in ARMCTRL block after routing it properly */ ++ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; + writel(0x80 | data, __io_address(ARM_IRQ_FAST)); + } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { + #if 1 +--- a/drivers/usb/Makefile ++++ b/drivers/usb/Makefile +@@ -7,6 +7,7 @@ + obj-$(CONFIG_USB) += core/ + obj-$(CONFIG_USB_SUPPORT) += phy/ + ++obj-$(CONFIG_USB_DWCOTG) += host/ + obj-$(CONFIG_USB_DWC3) += dwc3/ + obj-$(CONFIG_USB_DWC2) += dwc2/ + obj-$(CONFIG_USB_ISP1760) += isp1760/ +--- a/drivers/usb/core/generic.c ++++ b/drivers/usb/core/generic.c +@@ -152,6 +152,7 @@ int usb_choose_configuration(struct usb_ + dev_warn(&udev->dev, + "no configuration chosen from %d choice%s\n", + num_configs, plural(num_configs)); ++ dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA); + } + return i; + } +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -4906,7 +4906,7 @@ static void port_event(struct usb_hub *h + if (portchange & USB_PORT_STAT_C_OVERCURRENT) { + u16 status = 0, unused; + +- dev_dbg(&port_dev->dev, "over-current change\n"); ++ dev_notice(&port_dev->dev, "over-current change\n"); + usb_clear_port_feature(hdev, port1, + USB_PORT_FEAT_C_OVER_CURRENT); + msleep(100); /* Cool down */ +--- a/drivers/usb/core/message.c ++++ b/drivers/usb/core/message.c +@@ -1872,6 +1872,85 @@ free_interfaces: + if (cp->string == NULL && + !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS)) + cp->string = usb_cache_string(dev, cp->desc.iConfiguration); ++/* Uncomment this define to enable the HS Electrical Test support */ ++#define DWC_HS_ELECT_TST 1 ++#ifdef DWC_HS_ELECT_TST ++ /* Here we implement the HS Electrical Test support. The ++ * tester uses a vendor ID of 0x1A0A to indicate we should ++ * run a special test sequence. The product ID tells us ++ * which sequence to run. We invoke the test sequence by ++ * sending a non-standard SetFeature command to our root ++ * hub port. Our dwc_otg_hcd_hub_control() routine will ++ * recognize the command and perform the desired test ++ * sequence. ++ */ ++ if (dev->descriptor.idVendor == 0x1A0A) { ++ /* HSOTG Electrical Test */ ++ dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n"); ++ ++ if (dev->bus && dev->bus->root_hub) { ++ struct usb_device *hdev = dev->bus->root_hub; ++ dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct); ++ ++ switch (dev->descriptor.idProduct) { ++ case 0x0101: /* TEST_SE0_NAK */ ++ dev_warn(&dev->dev, "TEST_SE0_NAK\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ); ++ break; ++ ++ case 0x0102: /* TEST_J */ ++ dev_warn(&dev->dev, "TEST_J\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ); ++ break; ++ ++ case 0x0103: /* TEST_K */ ++ dev_warn(&dev->dev, "TEST_K\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ); ++ break; ++ ++ case 0x0104: /* TEST_PACKET */ ++ dev_warn(&dev->dev, "TEST_PACKET\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ); ++ break; ++ ++ case 0x0105: /* TEST_FORCE_ENABLE */ ++ dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ); ++ break; ++ ++ case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */ ++ dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ); ++ break; ++ ++ case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ ++ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ); ++ break; ++ ++ case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ ++ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ); ++ } ++ } ++ } ++#endif /* DWC_HS_ELECT_TST */ + + /* Now that the interfaces are installed, re-enable LPM. */ + usb_unlocked_enable_lpm(dev); +--- a/drivers/usb/core/otg_whitelist.h ++++ b/drivers/usb/core/otg_whitelist.h +@@ -19,33 +19,82 @@ + static struct usb_device_id whitelist_table [] = { + + /* hubs are optional in OTG, but very handy ... */ ++#define CERT_WITHOUT_HUBS ++#if defined(CERT_WITHOUT_HUBS) ++{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/ ++#else + { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), }, + { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), }, ++{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), }, ++#endif + + #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */ + /* FIXME actually, printers are NOT supposed to use device classes; + * they're supposed to use interface classes... + */ +-{ USB_DEVICE_INFO(7, 1, 1) }, +-{ USB_DEVICE_INFO(7, 1, 2) }, +-{ USB_DEVICE_INFO(7, 1, 3) }, ++//{ USB_DEVICE_INFO(7, 1, 1) }, ++//{ USB_DEVICE_INFO(7, 1, 2) }, ++//{ USB_DEVICE_INFO(7, 1, 3) }, + #endif + + #ifdef CONFIG_USB_NET_CDCETHER + /* Linux-USB CDC Ethernet gadget */ +-{ USB_DEVICE(0x0525, 0xa4a1), }, ++//{ USB_DEVICE(0x0525, 0xa4a1), }, + /* Linux-USB CDC Ethernet + RNDIS gadget */ +-{ USB_DEVICE(0x0525, 0xa4a2), }, ++//{ USB_DEVICE(0x0525, 0xa4a2), }, + #endif + + #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE) + /* gadget zero, for testing */ +-{ USB_DEVICE(0x0525, 0xa4a0), }, ++//{ USB_DEVICE(0x0525, 0xa4a0), }, + #endif + ++/* OPT Tester */ ++{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */ ++{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */ ++{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */ ++{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */ ++{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */ ++{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */ ++{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */ ++{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */ ++ ++/* Sony cameras */ ++{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), }, ++ ++/* Memory Devices */ ++//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */ ++//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */ ++//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */ ++//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */ ++{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/ ++//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */ ++ ++/* HP Printers */ ++//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */ ++//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */ ++ ++/* Speakers */ ++//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */ ++//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */ ++ + { } /* Terminating entry */ + }; + ++static inline void report_errors(struct usb_device *dev) ++{ ++ /* OTG MESSAGE: report errors here, customize to match your product */ ++ dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n", ++ le16_to_cpu(dev->descriptor.idVendor), ++ le16_to_cpu(dev->descriptor.idProduct)); ++ if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){ ++ dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n"); ++ } else { ++ dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n"); ++ } ++} ++ ++ + static int is_targeted(struct usb_device *dev) + { + struct usb_device_id *id = whitelist_table; +@@ -95,16 +144,57 @@ static int is_targeted(struct usb_device + continue; + + return 1; +- } ++ /* NOTE: can't use usb_match_id() since interface caches ++ * aren't set up yet. this is cut/paste from that code. ++ */ ++ for (id = whitelist_table; id->match_flags; id++) { ++#ifdef DEBUG ++ dev_dbg(&dev->dev, ++ "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n", ++ id->idVendor, ++ id->idProduct, ++ id->bDeviceClass, ++ id->bDeviceSubClass, ++ id->bDeviceProtocol); ++#endif + +- /* add other match criteria here ... */ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) && ++ id->idVendor != le16_to_cpu(dev->descriptor.idVendor)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) && ++ id->idProduct != le16_to_cpu(dev->descriptor.idProduct)) ++ continue; ++ ++ /* No need to test id->bcdDevice_lo != 0, since 0 is never ++ greater than any unsigned number. */ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) && ++ (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice))) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) && ++ (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice))) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) && ++ (id->bDeviceClass != dev->descriptor.bDeviceClass)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) && ++ (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) && ++ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol)) ++ continue; + ++ return 1; ++ } ++ } + +- /* OTG MESSAGE: report errors here, customize to match your product */ +- dev_err(&dev->dev, "device v%04x p%04x is not supported\n", +- le16_to_cpu(dev->descriptor.idVendor), +- le16_to_cpu(dev->descriptor.idProduct)); ++ /* add other match criteria here ... */ + ++ report_errors(dev); + return 0; + } + +--- /dev/null ++++ b/drivers/usb/gadget/file_storage.c +@@ -0,0 +1,3676 @@ ++/* ++ * file_storage.c -- File-backed USB Storage Gadget, for USB development ++ * ++ * Copyright (C) 2003-2008 Alan Stern ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") as published by the Free Software ++ * Foundation, either version 2 of that License or (at your option) any ++ * later version. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* ++ * The File-backed Storage Gadget acts as a USB Mass Storage device, ++ * appearing to the host as a disk drive or as a CD-ROM drive. In addition ++ * to providing an example of a genuinely useful gadget driver for a USB ++ * device, it also illustrates a technique of double-buffering for increased ++ * throughput. Last but not least, it gives an easy way to probe the ++ * behavior of the Mass Storage drivers in a USB host. ++ * ++ * Backing storage is provided by a regular file or a block device, specified ++ * by the "file" module parameter. Access can be limited to read-only by ++ * setting the optional "ro" module parameter. (For CD-ROM emulation, ++ * access is always read-only.) The gadget will indicate that it has ++ * removable media if the optional "removable" module parameter is set. ++ * ++ * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI), ++ * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected ++ * by the optional "transport" module parameter. It also supports the ++ * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03), ++ * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by ++ * the optional "protocol" module parameter. In addition, the default ++ * Vendor ID, Product ID, release number and serial number can be overridden. ++ * ++ * There is support for multiple logical units (LUNs), each of which has ++ * its own backing file. The number of LUNs can be set using the optional ++ * "luns" module parameter (anywhere from 1 to 8), and the corresponding ++ * files are specified using comma-separated lists for "file" and "ro". ++ * The default number of LUNs is taken from the number of "file" elements; ++ * it is 1 if "file" is not given. If "removable" is not set then a backing ++ * file must be specified for each LUN. If it is set, then an unspecified ++ * or empty backing filename means the LUN's medium is not loaded. Ideally ++ * each LUN would be settable independently as a disk drive or a CD-ROM ++ * drive, but currently all LUNs have to be the same type. The CD-ROM ++ * emulation includes a single data track and no audio tracks; hence there ++ * need be only one backing file per LUN. ++ * ++ * Requirements are modest; only a bulk-in and a bulk-out endpoint are ++ * needed (an interrupt-out endpoint is also needed for CBI). The memory ++ * requirement amounts to two 16K buffers, size configurable by a parameter. ++ * Support is included for both full-speed and high-speed operation. ++ * ++ * Note that the driver is slightly non-portable in that it assumes a ++ * single memory/DMA buffer will be useable for bulk-in, bulk-out, and ++ * interrupt-in endpoints. With most device controllers this isn't an ++ * issue, but there may be some with hardware restrictions that prevent ++ * a buffer from being used by more than one endpoint. ++ * ++ * Module options: ++ * ++ * file=filename[,filename...] ++ * Required if "removable" is not set, names of ++ * the files or block devices used for ++ * backing storage ++ * serial=HHHH... Required serial number (string of hex chars) ++ * ro=b[,b...] Default false, booleans for read-only access ++ * removable Default false, boolean for removable media ++ * luns=N Default N = number of filenames, number of ++ * LUNs to support ++ * nofua=b[,b...] Default false, booleans for ignore FUA flag ++ * in SCSI WRITE(10,12) commands ++ * stall Default determined according to the type of ++ * USB device controller (usually true), ++ * boolean to permit the driver to halt ++ * bulk endpoints ++ * cdrom Default false, boolean for whether to emulate ++ * a CD-ROM drive ++ * transport=XXX Default BBB, transport name (CB, CBI, or BBB) ++ * protocol=YYY Default SCSI, protocol name (RBC, 8020 or ++ * ATAPI, QIC, UFI, 8070, or SCSI; ++ * also 1 - 6) ++ * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID ++ * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID ++ * release=0xRRRR Override the USB release number (bcdDevice) ++ * buflen=N Default N=16384, buffer size used (will be ++ * rounded down to a multiple of ++ * PAGE_CACHE_SIZE) ++ * ++ * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro", ++ * "removable", "luns", "nofua", "stall", and "cdrom" options are available; ++ * default values are used for everything else. ++ * ++ * The pathnames of the backing files and the ro settings are available in ++ * the attribute files "file", "nofua", and "ro" in the lun subdirectory of ++ * the gadget's sysfs directory. If the "removable" option is set, writing to ++ * these files will simulate ejecting/loading the medium (writing an empty ++ * line means eject) and adjusting a write-enable tab. Changes to the ro ++ * setting are not allowed when the medium is loaded or if CD-ROM emulation ++ * is being used. ++ * ++ * This gadget driver is heavily based on "Gadget Zero" by David Brownell. ++ * The driver's SCSI command interface was based on the "Information ++ * technology - Small Computer System Interface - 2" document from ++ * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at ++ * . The single exception ++ * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the ++ * "Universal Serial Bus Mass Storage Class UFI Command Specification" ++ * document, Revision 1.0, December 14, 1998, available at ++ * . ++ */ ++ ++ ++/* ++ * Driver Design ++ * ++ * The FSG driver is fairly straightforward. There is a main kernel ++ * thread that handles most of the work. Interrupt routines field ++ * callbacks from the controller driver: bulk- and interrupt-request ++ * completion notifications, endpoint-0 events, and disconnect events. ++ * Completion events are passed to the main thread by wakeup calls. Many ++ * ep0 requests are handled at interrupt time, but SetInterface, ++ * SetConfiguration, and device reset requests are forwarded to the ++ * thread in the form of "exceptions" using SIGUSR1 signals (since they ++ * should interrupt any ongoing file I/O operations). ++ * ++ * The thread's main routine implements the standard command/data/status ++ * parts of a SCSI interaction. It and its subroutines are full of tests ++ * for pending signals/exceptions -- all this polling is necessary since ++ * the kernel has no setjmp/longjmp equivalents. (Maybe this is an ++ * indication that the driver really wants to be running in userspace.) ++ * An important point is that so long as the thread is alive it keeps an ++ * open reference to the backing file. This will prevent unmounting ++ * the backing file's underlying filesystem and could cause problems ++ * during system shutdown, for example. To prevent such problems, the ++ * thread catches INT, TERM, and KILL signals and converts them into ++ * an EXIT exception. ++ * ++ * In normal operation the main thread is started during the gadget's ++ * fsg_bind() callback and stopped during fsg_unbind(). But it can also ++ * exit when it receives a signal, and there's no point leaving the ++ * gadget running when the thread is dead. So just before the thread ++ * exits, it deregisters the gadget driver. This makes things a little ++ * tricky: The driver is deregistered at two places, and the exiting ++ * thread can indirectly call fsg_unbind() which in turn can tell the ++ * thread to exit. The first problem is resolved through the use of the ++ * REGISTERED atomic bitflag; the driver will only be deregistered once. ++ * The second problem is resolved by having fsg_unbind() check ++ * fsg->state; it won't try to stop the thread if the state is already ++ * FSG_STATE_TERMINATED. ++ * ++ * To provide maximum throughput, the driver uses a circular pipeline of ++ * buffer heads (struct fsg_buffhd). In principle the pipeline can be ++ * arbitrarily long; in practice the benefits don't justify having more ++ * than 2 stages (i.e., double buffering). But it helps to think of the ++ * pipeline as being a long one. Each buffer head contains a bulk-in and ++ * a bulk-out request pointer (since the buffer can be used for both ++ * output and input -- directions always are given from the host's ++ * point of view) as well as a pointer to the buffer and various state ++ * variables. ++ * ++ * Use of the pipeline follows a simple protocol. There is a variable ++ * (fsg->next_buffhd_to_fill) that points to the next buffer head to use. ++ * At any time that buffer head may still be in use from an earlier ++ * request, so each buffer head has a state variable indicating whether ++ * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the ++ * buffer head to be EMPTY, filling the buffer either by file I/O or by ++ * USB I/O (during which the buffer head is BUSY), and marking the buffer ++ * head FULL when the I/O is complete. Then the buffer will be emptied ++ * (again possibly by USB I/O, during which it is marked BUSY) and ++ * finally marked EMPTY again (possibly by a completion routine). ++ * ++ * A module parameter tells the driver to avoid stalling the bulk ++ * endpoints wherever the transport specification allows. This is ++ * necessary for some UDCs like the SuperH, which cannot reliably clear a ++ * halt on a bulk endpoint. However, under certain circumstances the ++ * Bulk-only specification requires a stall. In such cases the driver ++ * will halt the endpoint and set a flag indicating that it should clear ++ * the halt in software during the next device reset. Hopefully this ++ * will permit everything to work correctly. Furthermore, although the ++ * specification allows the bulk-out endpoint to halt when the host sends ++ * too much data, implementing this would cause an unavoidable race. ++ * The driver will always use the "no-stall" approach for OUT transfers. ++ * ++ * One subtle point concerns sending status-stage responses for ep0 ++ * requests. Some of these requests, such as device reset, can involve ++ * interrupting an ongoing file I/O operation, which might take an ++ * arbitrarily long time. During that delay the host might give up on ++ * the original ep0 request and issue a new one. When that happens the ++ * driver should not notify the host about completion of the original ++ * request, as the host will no longer be waiting for it. So the driver ++ * assigns to each ep0 request a unique tag, and it keeps track of the ++ * tag value of the request associated with a long-running exception ++ * (device-reset, interface-change, or configuration-change). When the ++ * exception handler is finished, the status-stage response is submitted ++ * only if the current ep0 request tag is equal to the exception request ++ * tag. Thus only the most recently received ep0 request will get a ++ * status-stage response. ++ * ++ * Warning: This driver source file is too long. It ought to be split up ++ * into a header file plus about 3 separate .c files, to handle the details ++ * of the Gadget, USB Mass Storage, and SCSI protocols. ++ */ ++ ++ ++/* #define VERBOSE_DEBUG */ ++/* #define DUMP_MSGS */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "gadget_chips.h" ++ ++ ++ ++/* ++ * Kbuild is not very cooperative with respect to linking separately ++ * compiled library objects into one module. So for now we won't use ++ * separate compilation ... ensuring init/exit sections work to shrink ++ * the runtime footprint, and giving us at least some parts of what ++ * a "gcc --combine ... part1.c part2.c part3.c ... " build would. ++ */ ++#include "usbstring.c" ++#include "config.c" ++#include "epautoconf.c" ++ ++/*-------------------------------------------------------------------------*/ ++ ++#define DRIVER_DESC "File-backed Storage Gadget" ++#define DRIVER_NAME "g_file_storage" ++#define DRIVER_VERSION "1 September 2010" ++ ++static char fsg_string_manufacturer[64]; ++static const char fsg_string_product[] = DRIVER_DESC; ++static const char fsg_string_config[] = "Self-powered"; ++static const char fsg_string_interface[] = "Mass Storage"; ++ ++ ++#include "storage_common.c" ++ ++ ++MODULE_DESCRIPTION(DRIVER_DESC); ++MODULE_AUTHOR("Alan Stern"); ++MODULE_LICENSE("Dual BSD/GPL"); ++ ++/* ++ * This driver assumes self-powered hardware and has no way for users to ++ * trigger remote wakeup. It uses autoconfiguration to select endpoints ++ * and endpoint addresses. ++ */ ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++ ++/* Encapsulate the module parameter settings */ ++ ++static struct { ++ char *file[FSG_MAX_LUNS]; ++ char *serial; ++ bool ro[FSG_MAX_LUNS]; ++ bool nofua[FSG_MAX_LUNS]; ++ unsigned int num_filenames; ++ unsigned int num_ros; ++ unsigned int num_nofuas; ++ unsigned int nluns; ++ ++ bool removable; ++ bool can_stall; ++ bool cdrom; ++ ++ char *transport_parm; ++ char *protocol_parm; ++ unsigned short vendor; ++ unsigned short product; ++ unsigned short release; ++ unsigned int buflen; ++ ++ int transport_type; ++ char *transport_name; ++ int protocol_type; ++ char *protocol_name; ++ ++} mod_data = { // Default values ++ .transport_parm = "BBB", ++ .protocol_parm = "SCSI", ++ .removable = 0, ++ .can_stall = 1, ++ .cdrom = 0, ++ .vendor = FSG_VENDOR_ID, ++ .product = FSG_PRODUCT_ID, ++ .release = 0xffff, // Use controller chip type ++ .buflen = 16384, ++ }; ++ ++ ++module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames, ++ S_IRUGO); ++MODULE_PARM_DESC(file, "names of backing files or devices"); ++ ++module_param_named(serial, mod_data.serial, charp, S_IRUGO); ++MODULE_PARM_DESC(serial, "USB serial number"); ++ ++module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO); ++MODULE_PARM_DESC(ro, "true to force read-only"); ++ ++module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas, ++ S_IRUGO); ++MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit"); ++ ++module_param_named(luns, mod_data.nluns, uint, S_IRUGO); ++MODULE_PARM_DESC(luns, "number of LUNs"); ++ ++module_param_named(removable, mod_data.removable, bool, S_IRUGO); ++MODULE_PARM_DESC(removable, "true to simulate removable media"); ++ ++module_param_named(stall, mod_data.can_stall, bool, S_IRUGO); ++MODULE_PARM_DESC(stall, "false to prevent bulk stalls"); ++ ++module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO); ++MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk"); ++ ++/* In the non-TEST version, only the module parameters listed above ++ * are available. */ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++ ++module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO); ++MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)"); ++ ++module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO); ++MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, " ++ "8070, or SCSI)"); ++ ++module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO); ++MODULE_PARM_DESC(vendor, "USB Vendor ID"); ++ ++module_param_named(product, mod_data.product, ushort, S_IRUGO); ++MODULE_PARM_DESC(product, "USB Product ID"); ++ ++module_param_named(release, mod_data.release, ushort, S_IRUGO); ++MODULE_PARM_DESC(release, "USB release number"); ++ ++module_param_named(buflen, mod_data.buflen, uint, S_IRUGO); ++MODULE_PARM_DESC(buflen, "I/O buffer size"); ++ ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ ++/* ++ * These definitions will permit the compiler to avoid generating code for ++ * parts of the driver that aren't used in the non-TEST version. Even gcc ++ * can recognize when a test of a constant expression yields a dead code ++ * path. ++ */ ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++ ++#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK) ++#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI) ++#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI) ++ ++#else ++ ++#define transport_is_bbb() 1 ++#define transport_is_cbi() 0 ++#define protocol_is_scsi() 1 ++ ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++ ++struct fsg_dev { ++ /* lock protects: state, all the req_busy's, and cbbuf_cmnd */ ++ spinlock_t lock; ++ struct usb_gadget *gadget; ++ ++ /* filesem protects: backing files in use */ ++ struct rw_semaphore filesem; ++ ++ /* reference counting: wait until all LUNs are released */ ++ struct kref ref; ++ ++ struct usb_ep *ep0; // Handy copy of gadget->ep0 ++ struct usb_request *ep0req; // For control responses ++ unsigned int ep0_req_tag; ++ const char *ep0req_name; ++ ++ struct usb_request *intreq; // For interrupt responses ++ int intreq_busy; ++ struct fsg_buffhd *intr_buffhd; ++ ++ unsigned int bulk_out_maxpacket; ++ enum fsg_state state; // For exception handling ++ unsigned int exception_req_tag; ++ ++ u8 config, new_config; ++ ++ unsigned int running : 1; ++ unsigned int bulk_in_enabled : 1; ++ unsigned int bulk_out_enabled : 1; ++ unsigned int intr_in_enabled : 1; ++ unsigned int phase_error : 1; ++ unsigned int short_packet_received : 1; ++ unsigned int bad_lun_okay : 1; ++ ++ unsigned long atomic_bitflags; ++#define REGISTERED 0 ++#define IGNORE_BULK_OUT 1 ++#define SUSPENDED 2 ++ ++ struct usb_ep *bulk_in; ++ struct usb_ep *bulk_out; ++ struct usb_ep *intr_in; ++ ++ struct fsg_buffhd *next_buffhd_to_fill; ++ struct fsg_buffhd *next_buffhd_to_drain; ++ ++ int thread_wakeup_needed; ++ struct completion thread_notifier; ++ struct task_struct *thread_task; ++ ++ int cmnd_size; ++ u8 cmnd[MAX_COMMAND_SIZE]; ++ enum data_direction data_dir; ++ u32 data_size; ++ u32 data_size_from_cmnd; ++ u32 tag; ++ unsigned int lun; ++ u32 residue; ++ u32 usb_amount_left; ++ ++ /* The CB protocol offers no way for a host to know when a command ++ * has completed. As a result the next command may arrive early, ++ * and we will still have to handle it. For that reason we need ++ * a buffer to store new commands when using CB (or CBI, which ++ * does not oblige a host to wait for command completion either). */ ++ int cbbuf_cmnd_size; ++ u8 cbbuf_cmnd[MAX_COMMAND_SIZE]; ++ ++ unsigned int nluns; ++ struct fsg_lun *luns; ++ struct fsg_lun *curlun; ++ /* Must be the last entry */ ++ struct fsg_buffhd buffhds[]; ++}; ++ ++typedef void (*fsg_routine_t)(struct fsg_dev *); ++ ++static int exception_in_progress(struct fsg_dev *fsg) ++{ ++ return (fsg->state > FSG_STATE_IDLE); ++} ++ ++/* Make bulk-out requests be divisible by the maxpacket size */ ++static void set_bulk_out_req_length(struct fsg_dev *fsg, ++ struct fsg_buffhd *bh, unsigned int length) ++{ ++ unsigned int rem; ++ ++ bh->bulk_out_intended_length = length; ++ rem = length % fsg->bulk_out_maxpacket; ++ if (rem > 0) ++ length += fsg->bulk_out_maxpacket - rem; ++ bh->outreq->length = length; ++} ++ ++static struct fsg_dev *the_fsg; ++static struct usb_gadget_driver fsg_driver; ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep) ++{ ++ const char *name; ++ ++ if (ep == fsg->bulk_in) ++ name = "bulk-in"; ++ else if (ep == fsg->bulk_out) ++ name = "bulk-out"; ++ else ++ name = ep->name; ++ DBG(fsg, "%s set halt\n", name); ++ return usb_ep_set_halt(ep); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * DESCRIPTORS ... most are static, but strings and (full) configuration ++ * descriptors are built on demand. Also the (static) config and interface ++ * descriptors are adjusted during fsg_bind(). ++ */ ++ ++/* There is only one configuration. */ ++#define CONFIG_VALUE 1 ++ ++static struct usb_device_descriptor ++device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ ++ .bcdUSB = cpu_to_le16(0x0200), ++ .bDeviceClass = USB_CLASS_PER_INTERFACE, ++ ++ /* The next three values can be overridden by module parameters */ ++ .idVendor = cpu_to_le16(FSG_VENDOR_ID), ++ .idProduct = cpu_to_le16(FSG_PRODUCT_ID), ++ .bcdDevice = cpu_to_le16(0xffff), ++ ++ .iManufacturer = FSG_STRING_MANUFACTURER, ++ .iProduct = FSG_STRING_PRODUCT, ++ .iSerialNumber = FSG_STRING_SERIAL, ++ .bNumConfigurations = 1, ++}; ++ ++static struct usb_config_descriptor ++config_desc = { ++ .bLength = sizeof config_desc, ++ .bDescriptorType = USB_DT_CONFIG, ++ ++ /* wTotalLength computed by usb_gadget_config_buf() */ ++ .bNumInterfaces = 1, ++ .bConfigurationValue = CONFIG_VALUE, ++ .iConfiguration = FSG_STRING_CONFIG, ++ .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, ++ .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2, ++}; ++ ++ ++static struct usb_qualifier_descriptor ++dev_qualifier = { ++ .bLength = sizeof dev_qualifier, ++ .bDescriptorType = USB_DT_DEVICE_QUALIFIER, ++ ++ .bcdUSB = cpu_to_le16(0x0200), ++ .bDeviceClass = USB_CLASS_PER_INTERFACE, ++ ++ .bNumConfigurations = 1, ++}; ++ ++static int populate_bos(struct fsg_dev *fsg, u8 *buf) ++{ ++ memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE); ++ buf += USB_DT_BOS_SIZE; ++ ++ memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE); ++ buf += USB_DT_USB_EXT_CAP_SIZE; ++ ++ memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE); ++ ++ return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE ++ + USB_DT_USB_EXT_CAP_SIZE; ++} ++ ++/* ++ * Config descriptors must agree with the code that sets configurations ++ * and with code managing interfaces and their altsettings. They must ++ * also handle different speeds and other-speed requests. ++ */ ++static int populate_config_buf(struct usb_gadget *gadget, ++ u8 *buf, u8 type, unsigned index) ++{ ++ enum usb_device_speed speed = gadget->speed; ++ int len; ++ const struct usb_descriptor_header **function; ++ ++ if (index > 0) ++ return -EINVAL; ++ ++ if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG) ++ speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed; ++ function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH ++ ? (const struct usb_descriptor_header **)fsg_hs_function ++ : (const struct usb_descriptor_header **)fsg_fs_function; ++ ++ /* for now, don't advertise srp-only devices */ ++ if (!gadget_is_otg(gadget)) ++ function++; ++ ++ len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function); ++ ((struct usb_config_descriptor *) buf)->bDescriptorType = type; ++ return len; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* These routines may be called in process context or in_irq */ ++ ++/* Caller must hold fsg->lock */ ++static void wakeup_thread(struct fsg_dev *fsg) ++{ ++ /* Tell the main thread that something has happened */ ++ fsg->thread_wakeup_needed = 1; ++ if (fsg->thread_task) ++ wake_up_process(fsg->thread_task); ++} ++ ++ ++static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state) ++{ ++ unsigned long flags; ++ ++ /* Do nothing if a higher-priority exception is already in progress. ++ * If a lower-or-equal priority exception is in progress, preempt it ++ * and notify the main thread by sending it a signal. */ ++ spin_lock_irqsave(&fsg->lock, flags); ++ if (fsg->state <= new_state) { ++ fsg->exception_req_tag = fsg->ep0_req_tag; ++ fsg->state = new_state; ++ if (fsg->thread_task) ++ send_sig_info(SIGUSR1, SEND_SIG_FORCED, ++ fsg->thread_task); ++ } ++ spin_unlock_irqrestore(&fsg->lock, flags); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* The disconnect callback and ep0 routines. These always run in_irq, ++ * except that ep0_queue() is called in the main thread to acknowledge ++ * completion of various requests: set config, set interface, and ++ * Bulk-only device reset. */ ++ ++static void fsg_disconnect(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ ++ DBG(fsg, "disconnect or port reset\n"); ++ raise_exception(fsg, FSG_STATE_DISCONNECT); ++} ++ ++ ++static int ep0_queue(struct fsg_dev *fsg) ++{ ++ int rc; ++ ++ rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC); ++ if (rc != 0 && rc != -ESHUTDOWN) { ++ ++ /* We can't do much more than wait for a reset */ ++ WARNING(fsg, "error in submission: %s --> %d\n", ++ fsg->ep0->name, rc); ++ } ++ return rc; ++} ++ ++static void ep0_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct fsg_dev *fsg = ep->driver_data; ++ ++ if (req->actual > 0) ++ dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual); ++ if (req->status || req->actual != req->length) ++ DBG(fsg, "%s --> %d, %u/%u\n", __func__, ++ req->status, req->actual, req->length); ++ if (req->status == -ECONNRESET) // Request was cancelled ++ usb_ep_fifo_flush(ep); ++ ++ if (req->status == 0 && req->context) ++ ((fsg_routine_t) (req->context))(fsg); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Bulk and interrupt endpoint completion handlers. ++ * These always run in_irq. */ ++ ++static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct fsg_dev *fsg = ep->driver_data; ++ struct fsg_buffhd *bh = req->context; ++ ++ if (req->status || req->actual != req->length) ++ DBG(fsg, "%s --> %d, %u/%u\n", __func__, ++ req->status, req->actual, req->length); ++ if (req->status == -ECONNRESET) // Request was cancelled ++ usb_ep_fifo_flush(ep); ++ ++ /* Hold the lock while we update the request and buffer states */ ++ smp_wmb(); ++ spin_lock(&fsg->lock); ++ bh->inreq_busy = 0; ++ bh->state = BUF_STATE_EMPTY; ++ wakeup_thread(fsg); ++ spin_unlock(&fsg->lock); ++} ++ ++static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct fsg_dev *fsg = ep->driver_data; ++ struct fsg_buffhd *bh = req->context; ++ ++ dump_msg(fsg, "bulk-out", req->buf, req->actual); ++ if (req->status || req->actual != bh->bulk_out_intended_length) ++ DBG(fsg, "%s --> %d, %u/%u\n", __func__, ++ req->status, req->actual, ++ bh->bulk_out_intended_length); ++ if (req->status == -ECONNRESET) // Request was cancelled ++ usb_ep_fifo_flush(ep); ++ ++ /* Hold the lock while we update the request and buffer states */ ++ smp_wmb(); ++ spin_lock(&fsg->lock); ++ bh->outreq_busy = 0; ++ bh->state = BUF_STATE_FULL; ++ wakeup_thread(fsg); ++ spin_unlock(&fsg->lock); ++} ++ ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++static void intr_in_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct fsg_dev *fsg = ep->driver_data; ++ struct fsg_buffhd *bh = req->context; ++ ++ if (req->status || req->actual != req->length) ++ DBG(fsg, "%s --> %d, %u/%u\n", __func__, ++ req->status, req->actual, req->length); ++ if (req->status == -ECONNRESET) // Request was cancelled ++ usb_ep_fifo_flush(ep); ++ ++ /* Hold the lock while we update the request and buffer states */ ++ smp_wmb(); ++ spin_lock(&fsg->lock); ++ fsg->intreq_busy = 0; ++ bh->state = BUF_STATE_EMPTY; ++ wakeup_thread(fsg); ++ spin_unlock(&fsg->lock); ++} ++ ++#else ++static void intr_in_complete(struct usb_ep *ep, struct usb_request *req) ++{} ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Ep0 class-specific handlers. These always run in_irq. */ ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct usb_request *req = fsg->ep0req; ++ static u8 cbi_reset_cmnd[6] = { ++ SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff}; ++ ++ /* Error in command transfer? */ ++ if (req->status || req->length != req->actual || ++ req->actual < 6 || req->actual > MAX_COMMAND_SIZE) { ++ ++ /* Not all controllers allow a protocol stall after ++ * receiving control-out data, but we'll try anyway. */ ++ fsg_set_halt(fsg, fsg->ep0); ++ return; // Wait for reset ++ } ++ ++ /* Is it the special reset command? */ ++ if (req->actual >= sizeof cbi_reset_cmnd && ++ memcmp(req->buf, cbi_reset_cmnd, ++ sizeof cbi_reset_cmnd) == 0) { ++ ++ /* Raise an exception to stop the current operation ++ * and reinitialize our state. */ ++ DBG(fsg, "cbi reset request\n"); ++ raise_exception(fsg, FSG_STATE_RESET); ++ return; ++ } ++ ++ VDBG(fsg, "CB[I] accept device-specific command\n"); ++ spin_lock(&fsg->lock); ++ ++ /* Save the command for later */ ++ if (fsg->cbbuf_cmnd_size) ++ WARNING(fsg, "CB[I] overwriting previous command\n"); ++ fsg->cbbuf_cmnd_size = req->actual; ++ memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size); ++ ++ wakeup_thread(fsg); ++ spin_unlock(&fsg->lock); ++} ++ ++#else ++static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{} ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ ++static int class_setup_req(struct fsg_dev *fsg, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_request *req = fsg->ep0req; ++ int value = -EOPNOTSUPP; ++ u16 w_index = le16_to_cpu(ctrl->wIndex); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u16 w_length = le16_to_cpu(ctrl->wLength); ++ ++ if (!fsg->config) ++ return value; ++ ++ /* Handle Bulk-only class-specific requests */ ++ if (transport_is_bbb()) { ++ switch (ctrl->bRequest) { ++ ++ case US_BULK_RESET_REQUEST: ++ if (ctrl->bRequestType != (USB_DIR_OUT | ++ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) ++ break; ++ if (w_index != 0 || w_value != 0 || w_length != 0) { ++ value = -EDOM; ++ break; ++ } ++ ++ /* Raise an exception to stop the current operation ++ * and reinitialize our state. */ ++ DBG(fsg, "bulk reset request\n"); ++ raise_exception(fsg, FSG_STATE_RESET); ++ value = DELAYED_STATUS; ++ break; ++ ++ case US_BULK_GET_MAX_LUN: ++ if (ctrl->bRequestType != (USB_DIR_IN | ++ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) ++ break; ++ if (w_index != 0 || w_value != 0 || w_length != 1) { ++ value = -EDOM; ++ break; ++ } ++ VDBG(fsg, "get max LUN\n"); ++ *(u8 *) req->buf = fsg->nluns - 1; ++ value = 1; ++ break; ++ } ++ } ++ ++ /* Handle CBI class-specific requests */ ++ else { ++ switch (ctrl->bRequest) { ++ ++ case USB_CBI_ADSC_REQUEST: ++ if (ctrl->bRequestType != (USB_DIR_OUT | ++ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) ++ break; ++ if (w_index != 0 || w_value != 0) { ++ value = -EDOM; ++ break; ++ } ++ if (w_length > MAX_COMMAND_SIZE) { ++ value = -EOVERFLOW; ++ break; ++ } ++ value = w_length; ++ fsg->ep0req->context = received_cbi_adsc; ++ break; ++ } ++ } ++ ++ if (value == -EOPNOTSUPP) ++ VDBG(fsg, ++ "unknown class-specific control req " ++ "%02x.%02x v%04x i%04x l%u\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ le16_to_cpu(ctrl->wValue), w_index, w_length); ++ return value; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Ep0 standard request handlers. These always run in_irq. */ ++ ++static int standard_setup_req(struct fsg_dev *fsg, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_request *req = fsg->ep0req; ++ int value = -EOPNOTSUPP; ++ u16 w_index = le16_to_cpu(ctrl->wIndex); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ ++ /* Usually this just stores reply data in the pre-allocated ep0 buffer, ++ * but config change events will also reconfigure hardware. */ ++ switch (ctrl->bRequest) { ++ ++ case USB_REQ_GET_DESCRIPTOR: ++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | ++ USB_RECIP_DEVICE)) ++ break; ++ switch (w_value >> 8) { ++ ++ case USB_DT_DEVICE: ++ VDBG(fsg, "get device descriptor\n"); ++ device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket; ++ value = sizeof device_desc; ++ memcpy(req->buf, &device_desc, value); ++ break; ++ case USB_DT_DEVICE_QUALIFIER: ++ VDBG(fsg, "get device qualifier\n"); ++ if (!gadget_is_dualspeed(fsg->gadget) || ++ fsg->gadget->speed == USB_SPEED_SUPER) ++ break; ++ /* ++ * Assume ep0 uses the same maxpacket value for both ++ * speeds ++ */ ++ dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket; ++ value = sizeof dev_qualifier; ++ memcpy(req->buf, &dev_qualifier, value); ++ break; ++ ++ case USB_DT_OTHER_SPEED_CONFIG: ++ VDBG(fsg, "get other-speed config descriptor\n"); ++ if (!gadget_is_dualspeed(fsg->gadget) || ++ fsg->gadget->speed == USB_SPEED_SUPER) ++ break; ++ goto get_config; ++ case USB_DT_CONFIG: ++ VDBG(fsg, "get configuration descriptor\n"); ++get_config: ++ value = populate_config_buf(fsg->gadget, ++ req->buf, ++ w_value >> 8, ++ w_value & 0xff); ++ break; ++ ++ case USB_DT_STRING: ++ VDBG(fsg, "get string descriptor\n"); ++ ++ /* wIndex == language code */ ++ value = usb_gadget_get_string(&fsg_stringtab, ++ w_value & 0xff, req->buf); ++ break; ++ ++ case USB_DT_BOS: ++ VDBG(fsg, "get bos descriptor\n"); ++ ++ if (gadget_is_superspeed(fsg->gadget)) ++ value = populate_bos(fsg, req->buf); ++ break; ++ } ++ ++ break; ++ ++ /* One config, two speeds */ ++ case USB_REQ_SET_CONFIGURATION: ++ if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD | ++ USB_RECIP_DEVICE)) ++ break; ++ VDBG(fsg, "set configuration\n"); ++ if (w_value == CONFIG_VALUE || w_value == 0) { ++ fsg->new_config = w_value; ++ ++ /* Raise an exception to wipe out previous transaction ++ * state (queued bufs, etc) and set the new config. */ ++ raise_exception(fsg, FSG_STATE_CONFIG_CHANGE); ++ value = DELAYED_STATUS; ++ } ++ break; ++ case USB_REQ_GET_CONFIGURATION: ++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | ++ USB_RECIP_DEVICE)) ++ break; ++ VDBG(fsg, "get configuration\n"); ++ *(u8 *) req->buf = fsg->config; ++ value = 1; ++ break; ++ ++ case USB_REQ_SET_INTERFACE: ++ if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD | ++ USB_RECIP_INTERFACE)) ++ break; ++ if (fsg->config && w_index == 0) { ++ ++ /* Raise an exception to wipe out previous transaction ++ * state (queued bufs, etc) and install the new ++ * interface altsetting. */ ++ raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE); ++ value = DELAYED_STATUS; ++ } ++ break; ++ case USB_REQ_GET_INTERFACE: ++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | ++ USB_RECIP_INTERFACE)) ++ break; ++ if (!fsg->config) ++ break; ++ if (w_index != 0) { ++ value = -EDOM; ++ break; ++ } ++ VDBG(fsg, "get interface\n"); ++ *(u8 *) req->buf = 0; ++ value = 1; ++ break; ++ ++ default: ++ VDBG(fsg, ++ "unknown control req %02x.%02x v%04x i%04x l%u\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ w_value, w_index, le16_to_cpu(ctrl->wLength)); ++ } ++ ++ return value; ++} ++ ++ ++static int fsg_setup(struct usb_gadget *gadget, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ int rc; ++ int w_length = le16_to_cpu(ctrl->wLength); ++ ++ ++fsg->ep0_req_tag; // Record arrival of a new request ++ fsg->ep0req->context = NULL; ++ fsg->ep0req->length = 0; ++ dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl)); ++ ++ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) ++ rc = class_setup_req(fsg, ctrl); ++ else ++ rc = standard_setup_req(fsg, ctrl); ++ ++ /* Respond with data/status or defer until later? */ ++ if (rc >= 0 && rc != DELAYED_STATUS) { ++ rc = min(rc, w_length); ++ fsg->ep0req->length = rc; ++ fsg->ep0req->zero = rc < w_length; ++ fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ? ++ "ep0-in" : "ep0-out"); ++ rc = ep0_queue(fsg); ++ } ++ ++ /* Device either stalls (rc < 0) or reports success */ ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* All the following routines run in process context */ ++ ++ ++/* Use this for bulk or interrupt transfers, not ep0 */ ++static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep, ++ struct usb_request *req, int *pbusy, ++ enum fsg_buffer_state *state) ++{ ++ int rc; ++ ++ if (ep == fsg->bulk_in) ++ dump_msg(fsg, "bulk-in", req->buf, req->length); ++ else if (ep == fsg->intr_in) ++ dump_msg(fsg, "intr-in", req->buf, req->length); ++ ++ spin_lock_irq(&fsg->lock); ++ *pbusy = 1; ++ *state = BUF_STATE_BUSY; ++ spin_unlock_irq(&fsg->lock); ++ rc = usb_ep_queue(ep, req, GFP_KERNEL); ++ if (rc != 0) { ++ *pbusy = 0; ++ *state = BUF_STATE_EMPTY; ++ ++ /* We can't do much more than wait for a reset */ ++ ++ /* Note: currently the net2280 driver fails zero-length ++ * submissions if DMA is enabled. */ ++ if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP && ++ req->length == 0)) ++ WARNING(fsg, "error in submission: %s --> %d\n", ++ ep->name, rc); ++ } ++} ++ ++ ++static int sleep_thread(struct fsg_dev *fsg) ++{ ++ int rc = 0; ++ ++ /* Wait until a signal arrives or we are woken up */ ++ for (;;) { ++ try_to_freeze(); ++ set_current_state(TASK_INTERRUPTIBLE); ++ if (signal_pending(current)) { ++ rc = -EINTR; ++ break; ++ } ++ if (fsg->thread_wakeup_needed) ++ break; ++ schedule(); ++ } ++ __set_current_state(TASK_RUNNING); ++ fsg->thread_wakeup_needed = 0; ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int do_read(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u32 lba; ++ struct fsg_buffhd *bh; ++ int rc; ++ u32 amount_left; ++ loff_t file_offset, file_offset_tmp; ++ unsigned int amount; ++ ssize_t nread; ++ ++ /* Get the starting Logical Block Address and check that it's ++ * not too big */ ++ if (fsg->cmnd[0] == READ_6) ++ lba = get_unaligned_be24(&fsg->cmnd[1]); ++ else { ++ lba = get_unaligned_be32(&fsg->cmnd[2]); ++ ++ /* We allow DPO (Disable Page Out = don't save data in the ++ * cache) and FUA (Force Unit Access = don't read from the ++ * cache), but we don't implement them. */ ++ if ((fsg->cmnd[1] & ~0x18) != 0) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ } ++ if (lba >= curlun->num_sectors) { ++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ return -EINVAL; ++ } ++ file_offset = ((loff_t) lba) << curlun->blkbits; ++ ++ /* Carry out the file reads */ ++ amount_left = fsg->data_size_from_cmnd; ++ if (unlikely(amount_left == 0)) ++ return -EIO; // No default reply ++ ++ for (;;) { ++ ++ /* Figure out how much we need to read: ++ * Try to read the remaining amount. ++ * But don't read more than the buffer size. ++ * And don't try to read past the end of the file. ++ */ ++ amount = min((unsigned int) amount_left, mod_data.buflen); ++ amount = min((loff_t) amount, ++ curlun->file_length - file_offset); ++ ++ /* Wait for the next buffer to become available */ ++ bh = fsg->next_buffhd_to_fill; ++ while (bh->state != BUF_STATE_EMPTY) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ /* If we were asked to read past the end of file, ++ * end with an empty buffer. */ ++ if (amount == 0) { ++ curlun->sense_data = ++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ bh->inreq->length = 0; ++ bh->state = BUF_STATE_FULL; ++ break; ++ } ++ ++ /* Perform the read */ ++ file_offset_tmp = file_offset; ++ nread = vfs_read(curlun->filp, ++ (char __user *) bh->buf, ++ amount, &file_offset_tmp); ++ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, ++ (unsigned long long) file_offset, ++ (int) nread); ++ if (signal_pending(current)) ++ return -EINTR; ++ ++ if (nread < 0) { ++ LDBG(curlun, "error in file read: %d\n", ++ (int) nread); ++ nread = 0; ++ } else if (nread < amount) { ++ LDBG(curlun, "partial file read: %d/%u\n", ++ (int) nread, amount); ++ nread = round_down(nread, curlun->blksize); ++ } ++ file_offset += nread; ++ amount_left -= nread; ++ fsg->residue -= nread; ++ ++ /* Except at the end of the transfer, nread will be ++ * equal to the buffer size, which is divisible by the ++ * bulk-in maxpacket size. ++ */ ++ bh->inreq->length = nread; ++ bh->state = BUF_STATE_FULL; ++ ++ /* If an error occurred, report it and its position */ ++ if (nread < amount) { ++ curlun->sense_data = SS_UNRECOVERED_READ_ERROR; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ ++ if (amount_left == 0) ++ break; // No more left to read ++ ++ /* Send this buffer and go read some more */ ++ bh->inreq->zero = 0; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ } ++ ++ return -EIO; // No default reply ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int do_write(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u32 lba; ++ struct fsg_buffhd *bh; ++ int get_some_more; ++ u32 amount_left_to_req, amount_left_to_write; ++ loff_t usb_offset, file_offset, file_offset_tmp; ++ unsigned int amount; ++ ssize_t nwritten; ++ int rc; ++ ++ if (curlun->ro) { ++ curlun->sense_data = SS_WRITE_PROTECTED; ++ return -EINVAL; ++ } ++ spin_lock(&curlun->filp->f_lock); ++ curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait ++ spin_unlock(&curlun->filp->f_lock); ++ ++ /* Get the starting Logical Block Address and check that it's ++ * not too big */ ++ if (fsg->cmnd[0] == WRITE_6) ++ lba = get_unaligned_be24(&fsg->cmnd[1]); ++ else { ++ lba = get_unaligned_be32(&fsg->cmnd[2]); ++ ++ /* We allow DPO (Disable Page Out = don't save data in the ++ * cache) and FUA (Force Unit Access = write directly to the ++ * medium). We don't implement DPO; we implement FUA by ++ * performing synchronous output. */ ++ if ((fsg->cmnd[1] & ~0x18) != 0) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ /* FUA */ ++ if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) { ++ spin_lock(&curlun->filp->f_lock); ++ curlun->filp->f_flags |= O_DSYNC; ++ spin_unlock(&curlun->filp->f_lock); ++ } ++ } ++ if (lba >= curlun->num_sectors) { ++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ return -EINVAL; ++ } ++ ++ /* Carry out the file writes */ ++ get_some_more = 1; ++ file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits; ++ amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd; ++ ++ while (amount_left_to_write > 0) { ++ ++ /* Queue a request for more data from the host */ ++ bh = fsg->next_buffhd_to_fill; ++ if (bh->state == BUF_STATE_EMPTY && get_some_more) { ++ ++ /* Figure out how much we want to get: ++ * Try to get the remaining amount, ++ * but not more than the buffer size. ++ */ ++ amount = min(amount_left_to_req, mod_data.buflen); ++ ++ /* Beyond the end of the backing file? */ ++ if (usb_offset >= curlun->file_length) { ++ get_some_more = 0; ++ curlun->sense_data = ++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ curlun->sense_data_info = usb_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ continue; ++ } ++ ++ /* Get the next buffer */ ++ usb_offset += amount; ++ fsg->usb_amount_left -= amount; ++ amount_left_to_req -= amount; ++ if (amount_left_to_req == 0) ++ get_some_more = 0; ++ ++ /* Except at the end of the transfer, amount will be ++ * equal to the buffer size, which is divisible by ++ * the bulk-out maxpacket size. ++ */ ++ set_bulk_out_req_length(fsg, bh, amount); ++ start_transfer(fsg, fsg->bulk_out, bh->outreq, ++ &bh->outreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ continue; ++ } ++ ++ /* Write the received data to the backing file */ ++ bh = fsg->next_buffhd_to_drain; ++ if (bh->state == BUF_STATE_EMPTY && !get_some_more) ++ break; // We stopped early ++ if (bh->state == BUF_STATE_FULL) { ++ smp_rmb(); ++ fsg->next_buffhd_to_drain = bh->next; ++ bh->state = BUF_STATE_EMPTY; ++ ++ /* Did something go wrong with the transfer? */ ++ if (bh->outreq->status != 0) { ++ curlun->sense_data = SS_COMMUNICATION_FAILURE; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ ++ amount = bh->outreq->actual; ++ if (curlun->file_length - file_offset < amount) { ++ LERROR(curlun, ++ "write %u @ %llu beyond end %llu\n", ++ amount, (unsigned long long) file_offset, ++ (unsigned long long) curlun->file_length); ++ amount = curlun->file_length - file_offset; ++ } ++ ++ /* Don't accept excess data. The spec doesn't say ++ * what to do in this case. We'll ignore the error. ++ */ ++ amount = min(amount, bh->bulk_out_intended_length); ++ ++ /* Don't write a partial block */ ++ amount = round_down(amount, curlun->blksize); ++ if (amount == 0) ++ goto empty_write; ++ ++ /* Perform the write */ ++ file_offset_tmp = file_offset; ++ nwritten = vfs_write(curlun->filp, ++ (char __user *) bh->buf, ++ amount, &file_offset_tmp); ++ VLDBG(curlun, "file write %u @ %llu -> %d\n", amount, ++ (unsigned long long) file_offset, ++ (int) nwritten); ++ if (signal_pending(current)) ++ return -EINTR; // Interrupted! ++ ++ if (nwritten < 0) { ++ LDBG(curlun, "error in file write: %d\n", ++ (int) nwritten); ++ nwritten = 0; ++ } else if (nwritten < amount) { ++ LDBG(curlun, "partial file write: %d/%u\n", ++ (int) nwritten, amount); ++ nwritten = round_down(nwritten, curlun->blksize); ++ } ++ file_offset += nwritten; ++ amount_left_to_write -= nwritten; ++ fsg->residue -= nwritten; ++ ++ /* If an error occurred, report it and its position */ ++ if (nwritten < amount) { ++ curlun->sense_data = SS_WRITE_ERROR; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ ++ empty_write: ++ /* Did the host decide to stop early? */ ++ if (bh->outreq->actual < bh->bulk_out_intended_length) { ++ fsg->short_packet_received = 1; ++ break; ++ } ++ continue; ++ } ++ ++ /* Wait for something to happen */ ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ return -EIO; // No default reply ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int do_synchronize_cache(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int rc; ++ ++ /* We ignore the requested LBA and write out all file's ++ * dirty data buffers. */ ++ rc = fsg_lun_fsync_sub(curlun); ++ if (rc) ++ curlun->sense_data = SS_WRITE_ERROR; ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void invalidate_sub(struct fsg_lun *curlun) ++{ ++ struct file *filp = curlun->filp; ++ struct inode *inode = filp->f_path.dentry->d_inode; ++ unsigned long rc; ++ ++ rc = invalidate_mapping_pages(inode->i_mapping, 0, -1); ++ VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc); ++} ++ ++static int do_verify(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u32 lba; ++ u32 verification_length; ++ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill; ++ loff_t file_offset, file_offset_tmp; ++ u32 amount_left; ++ unsigned int amount; ++ ssize_t nread; ++ ++ /* Get the starting Logical Block Address and check that it's ++ * not too big */ ++ lba = get_unaligned_be32(&fsg->cmnd[2]); ++ if (lba >= curlun->num_sectors) { ++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ return -EINVAL; ++ } ++ ++ /* We allow DPO (Disable Page Out = don't save data in the ++ * cache) but we don't implement it. */ ++ if ((fsg->cmnd[1] & ~0x10) != 0) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ verification_length = get_unaligned_be16(&fsg->cmnd[7]); ++ if (unlikely(verification_length == 0)) ++ return -EIO; // No default reply ++ ++ /* Prepare to carry out the file verify */ ++ amount_left = verification_length << curlun->blkbits; ++ file_offset = ((loff_t) lba) << curlun->blkbits; ++ ++ /* Write out all the dirty buffers before invalidating them */ ++ fsg_lun_fsync_sub(curlun); ++ if (signal_pending(current)) ++ return -EINTR; ++ ++ invalidate_sub(curlun); ++ if (signal_pending(current)) ++ return -EINTR; ++ ++ /* Just try to read the requested blocks */ ++ while (amount_left > 0) { ++ ++ /* Figure out how much we need to read: ++ * Try to read the remaining amount, but not more than ++ * the buffer size. ++ * And don't try to read past the end of the file. ++ */ ++ amount = min((unsigned int) amount_left, mod_data.buflen); ++ amount = min((loff_t) amount, ++ curlun->file_length - file_offset); ++ if (amount == 0) { ++ curlun->sense_data = ++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ ++ /* Perform the read */ ++ file_offset_tmp = file_offset; ++ nread = vfs_read(curlun->filp, ++ (char __user *) bh->buf, ++ amount, &file_offset_tmp); ++ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, ++ (unsigned long long) file_offset, ++ (int) nread); ++ if (signal_pending(current)) ++ return -EINTR; ++ ++ if (nread < 0) { ++ LDBG(curlun, "error in file verify: %d\n", ++ (int) nread); ++ nread = 0; ++ } else if (nread < amount) { ++ LDBG(curlun, "partial file verify: %d/%u\n", ++ (int) nread, amount); ++ nread = round_down(nread, curlun->blksize); ++ } ++ if (nread == 0) { ++ curlun->sense_data = SS_UNRECOVERED_READ_ERROR; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ file_offset += nread; ++ amount_left -= nread; ++ } ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ u8 *buf = (u8 *) bh->buf; ++ ++ static char vendor_id[] = "Linux "; ++ static char product_disk_id[] = "File-Stor Gadget"; ++ static char product_cdrom_id[] = "File-CD Gadget "; ++ ++ if (!fsg->curlun) { // Unsupported LUNs are okay ++ fsg->bad_lun_okay = 1; ++ memset(buf, 0, 36); ++ buf[0] = 0x7f; // Unsupported, no device-type ++ buf[4] = 31; // Additional length ++ return 36; ++ } ++ ++ memset(buf, 0, 8); ++ buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK); ++ if (mod_data.removable) ++ buf[1] = 0x80; ++ buf[2] = 2; // ANSI SCSI level 2 ++ buf[3] = 2; // SCSI-2 INQUIRY data format ++ buf[4] = 31; // Additional length ++ // No special options ++ sprintf(buf + 8, "%-8s%-16s%04x", vendor_id, ++ (mod_data.cdrom ? product_cdrom_id : ++ product_disk_id), ++ mod_data.release); ++ return 36; ++} ++ ++ ++static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u8 *buf = (u8 *) bh->buf; ++ u32 sd, sdinfo; ++ int valid; ++ ++ /* ++ * From the SCSI-2 spec., section 7.9 (Unit attention condition): ++ * ++ * If a REQUEST SENSE command is received from an initiator ++ * with a pending unit attention condition (before the target ++ * generates the contingent allegiance condition), then the ++ * target shall either: ++ * a) report any pending sense data and preserve the unit ++ * attention condition on the logical unit, or, ++ * b) report the unit attention condition, may discard any ++ * pending sense data, and clear the unit attention ++ * condition on the logical unit for that initiator. ++ * ++ * FSG normally uses option a); enable this code to use option b). ++ */ ++#if 0 ++ if (curlun && curlun->unit_attention_data != SS_NO_SENSE) { ++ curlun->sense_data = curlun->unit_attention_data; ++ curlun->unit_attention_data = SS_NO_SENSE; ++ } ++#endif ++ ++ if (!curlun) { // Unsupported LUNs are okay ++ fsg->bad_lun_okay = 1; ++ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; ++ sdinfo = 0; ++ valid = 0; ++ } else { ++ sd = curlun->sense_data; ++ sdinfo = curlun->sense_data_info; ++ valid = curlun->info_valid << 7; ++ curlun->sense_data = SS_NO_SENSE; ++ curlun->sense_data_info = 0; ++ curlun->info_valid = 0; ++ } ++ ++ memset(buf, 0, 18); ++ buf[0] = valid | 0x70; // Valid, current error ++ buf[2] = SK(sd); ++ put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */ ++ buf[7] = 18 - 8; // Additional sense length ++ buf[12] = ASC(sd); ++ buf[13] = ASCQ(sd); ++ return 18; ++} ++ ++ ++static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u32 lba = get_unaligned_be32(&fsg->cmnd[2]); ++ int pmi = fsg->cmnd[8]; ++ u8 *buf = (u8 *) bh->buf; ++ ++ /* Check the PMI and LBA fields */ ++ if (pmi > 1 || (pmi == 0 && lba != 0)) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ put_unaligned_be32(curlun->num_sectors - 1, &buf[0]); ++ /* Max logical block */ ++ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */ ++ return 8; ++} ++ ++ ++static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int msf = fsg->cmnd[1] & 0x02; ++ u32 lba = get_unaligned_be32(&fsg->cmnd[2]); ++ u8 *buf = (u8 *) bh->buf; ++ ++ if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */ ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ if (lba >= curlun->num_sectors) { ++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ return -EINVAL; ++ } ++ ++ memset(buf, 0, 8); ++ buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */ ++ store_cdrom_address(&buf[4], msf, lba); ++ return 8; ++} ++ ++ ++static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int msf = fsg->cmnd[1] & 0x02; ++ int start_track = fsg->cmnd[6]; ++ u8 *buf = (u8 *) bh->buf; ++ ++ if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */ ++ start_track > 1) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ memset(buf, 0, 20); ++ buf[1] = (20-2); /* TOC data length */ ++ buf[2] = 1; /* First track number */ ++ buf[3] = 1; /* Last track number */ ++ buf[5] = 0x16; /* Data track, copying allowed */ ++ buf[6] = 0x01; /* Only track is number 1 */ ++ store_cdrom_address(&buf[8], msf, 0); ++ ++ buf[13] = 0x16; /* Lead-out track is data */ ++ buf[14] = 0xAA; /* Lead-out track number */ ++ store_cdrom_address(&buf[16], msf, curlun->num_sectors); ++ return 20; ++} ++ ++ ++static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int mscmnd = fsg->cmnd[0]; ++ u8 *buf = (u8 *) bh->buf; ++ u8 *buf0 = buf; ++ int pc, page_code; ++ int changeable_values, all_pages; ++ int valid_page = 0; ++ int len, limit; ++ ++ if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ pc = fsg->cmnd[2] >> 6; ++ page_code = fsg->cmnd[2] & 0x3f; ++ if (pc == 3) { ++ curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED; ++ return -EINVAL; ++ } ++ changeable_values = (pc == 1); ++ all_pages = (page_code == 0x3f); ++ ++ /* Write the mode parameter header. Fixed values are: default ++ * medium type, no cache control (DPOFUA), and no block descriptors. ++ * The only variable value is the WriteProtect bit. We will fill in ++ * the mode data length later. */ ++ memset(buf, 0, 8); ++ if (mscmnd == MODE_SENSE) { ++ buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA ++ buf += 4; ++ limit = 255; ++ } else { // MODE_SENSE_10 ++ buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA ++ buf += 8; ++ limit = 65535; // Should really be mod_data.buflen ++ } ++ ++ /* No block descriptors */ ++ ++ /* The mode pages, in numerical order. The only page we support ++ * is the Caching page. */ ++ if (page_code == 0x08 || all_pages) { ++ valid_page = 1; ++ buf[0] = 0x08; // Page code ++ buf[1] = 10; // Page length ++ memset(buf+2, 0, 10); // None of the fields are changeable ++ ++ if (!changeable_values) { ++ buf[2] = 0x04; // Write cache enable, ++ // Read cache not disabled ++ // No cache retention priorities ++ put_unaligned_be16(0xffff, &buf[4]); ++ /* Don't disable prefetch */ ++ /* Minimum prefetch = 0 */ ++ put_unaligned_be16(0xffff, &buf[8]); ++ /* Maximum prefetch */ ++ put_unaligned_be16(0xffff, &buf[10]); ++ /* Maximum prefetch ceiling */ ++ } ++ buf += 12; ++ } ++ ++ /* Check that a valid page was requested and the mode data length ++ * isn't too long. */ ++ len = buf - buf0; ++ if (!valid_page || len > limit) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ /* Store the mode data length */ ++ if (mscmnd == MODE_SENSE) ++ buf0[0] = len - 1; ++ else ++ put_unaligned_be16(len - 2, buf0); ++ return len; ++} ++ ++ ++static int do_start_stop(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int loej, start; ++ ++ if (!mod_data.removable) { ++ curlun->sense_data = SS_INVALID_COMMAND; ++ return -EINVAL; ++ } ++ ++ // int immed = fsg->cmnd[1] & 0x01; ++ loej = fsg->cmnd[4] & 0x02; ++ start = fsg->cmnd[4] & 0x01; ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++ if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed ++ (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ if (!start) { ++ ++ /* Are we allowed to unload the media? */ ++ if (curlun->prevent_medium_removal) { ++ LDBG(curlun, "unload attempt prevented\n"); ++ curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED; ++ return -EINVAL; ++ } ++ if (loej) { // Simulate an unload/eject ++ up_read(&fsg->filesem); ++ down_write(&fsg->filesem); ++ fsg_lun_close(curlun); ++ up_write(&fsg->filesem); ++ down_read(&fsg->filesem); ++ } ++ } else { ++ ++ /* Our emulation doesn't support mounting; the medium is ++ * available for use as soon as it is loaded. */ ++ if (!fsg_lun_is_open(curlun)) { ++ curlun->sense_data = SS_MEDIUM_NOT_PRESENT; ++ return -EINVAL; ++ } ++ } ++#endif ++ return 0; ++} ++ ++ ++static int do_prevent_allow(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int prevent; ++ ++ if (!mod_data.removable) { ++ curlun->sense_data = SS_INVALID_COMMAND; ++ return -EINVAL; ++ } ++ ++ prevent = fsg->cmnd[4] & 0x01; ++ if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ if (curlun->prevent_medium_removal && !prevent) ++ fsg_lun_fsync_sub(curlun); ++ curlun->prevent_medium_removal = prevent; ++ return 0; ++} ++ ++ ++static int do_read_format_capacities(struct fsg_dev *fsg, ++ struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u8 *buf = (u8 *) bh->buf; ++ ++ buf[0] = buf[1] = buf[2] = 0; ++ buf[3] = 8; // Only the Current/Maximum Capacity Descriptor ++ buf += 4; ++ ++ put_unaligned_be32(curlun->num_sectors, &buf[0]); ++ /* Number of blocks */ ++ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */ ++ buf[4] = 0x02; /* Current capacity */ ++ return 12; ++} ++ ++ ++static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ ++ /* We don't support MODE SELECT */ ++ curlun->sense_data = SS_INVALID_COMMAND; ++ return -EINVAL; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int halt_bulk_in_endpoint(struct fsg_dev *fsg) ++{ ++ int rc; ++ ++ rc = fsg_set_halt(fsg, fsg->bulk_in); ++ if (rc == -EAGAIN) ++ VDBG(fsg, "delayed bulk-in endpoint halt\n"); ++ while (rc != 0) { ++ if (rc != -EAGAIN) { ++ WARNING(fsg, "usb_ep_set_halt -> %d\n", rc); ++ rc = 0; ++ break; ++ } ++ ++ /* Wait for a short time and then try again */ ++ if (msleep_interruptible(100) != 0) ++ return -EINTR; ++ rc = usb_ep_set_halt(fsg->bulk_in); ++ } ++ return rc; ++} ++ ++static int wedge_bulk_in_endpoint(struct fsg_dev *fsg) ++{ ++ int rc; ++ ++ DBG(fsg, "bulk-in set wedge\n"); ++ rc = usb_ep_set_wedge(fsg->bulk_in); ++ if (rc == -EAGAIN) ++ VDBG(fsg, "delayed bulk-in endpoint wedge\n"); ++ while (rc != 0) { ++ if (rc != -EAGAIN) { ++ WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc); ++ rc = 0; ++ break; ++ } ++ ++ /* Wait for a short time and then try again */ ++ if (msleep_interruptible(100) != 0) ++ return -EINTR; ++ rc = usb_ep_set_wedge(fsg->bulk_in); ++ } ++ return rc; ++} ++ ++static int throw_away_data(struct fsg_dev *fsg) ++{ ++ struct fsg_buffhd *bh; ++ u32 amount; ++ int rc; ++ ++ while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY || ++ fsg->usb_amount_left > 0) { ++ ++ /* Throw away the data in a filled buffer */ ++ if (bh->state == BUF_STATE_FULL) { ++ smp_rmb(); ++ bh->state = BUF_STATE_EMPTY; ++ fsg->next_buffhd_to_drain = bh->next; ++ ++ /* A short packet or an error ends everything */ ++ if (bh->outreq->actual < bh->bulk_out_intended_length || ++ bh->outreq->status != 0) { ++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); ++ return -EINTR; ++ } ++ continue; ++ } ++ ++ /* Try to submit another request if we need one */ ++ bh = fsg->next_buffhd_to_fill; ++ if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) { ++ amount = min(fsg->usb_amount_left, ++ (u32) mod_data.buflen); ++ ++ /* Except at the end of the transfer, amount will be ++ * equal to the buffer size, which is divisible by ++ * the bulk-out maxpacket size. ++ */ ++ set_bulk_out_req_length(fsg, bh, amount); ++ start_transfer(fsg, fsg->bulk_out, bh->outreq, ++ &bh->outreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ fsg->usb_amount_left -= amount; ++ continue; ++ } ++ ++ /* Otherwise wait for something to happen */ ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ return 0; ++} ++ ++ ++static int finish_reply(struct fsg_dev *fsg) ++{ ++ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill; ++ int rc = 0; ++ ++ switch (fsg->data_dir) { ++ case DATA_DIR_NONE: ++ break; // Nothing to send ++ ++ /* If we don't know whether the host wants to read or write, ++ * this must be CB or CBI with an unknown command. We mustn't ++ * try to send or receive any data. So stall both bulk pipes ++ * if we can and wait for a reset. */ ++ case DATA_DIR_UNKNOWN: ++ if (mod_data.can_stall) { ++ fsg_set_halt(fsg, fsg->bulk_out); ++ rc = halt_bulk_in_endpoint(fsg); ++ } ++ break; ++ ++ /* All but the last buffer of data must have already been sent */ ++ case DATA_DIR_TO_HOST: ++ if (fsg->data_size == 0) ++ ; // Nothing to send ++ ++ /* If there's no residue, simply send the last buffer */ ++ else if (fsg->residue == 0) { ++ bh->inreq->zero = 0; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ } ++ ++ /* There is a residue. For CB and CBI, simply mark the end ++ * of the data with a short packet. However, if we are ++ * allowed to stall, there was no data at all (residue == ++ * data_size), and the command failed (invalid LUN or ++ * sense data is set), then halt the bulk-in endpoint ++ * instead. */ ++ else if (!transport_is_bbb()) { ++ if (mod_data.can_stall && ++ fsg->residue == fsg->data_size && ++ (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) { ++ bh->state = BUF_STATE_EMPTY; ++ rc = halt_bulk_in_endpoint(fsg); ++ } else { ++ bh->inreq->zero = 1; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ } ++ } ++ ++ /* ++ * For Bulk-only, mark the end of the data with a short ++ * packet. If we are allowed to stall, halt the bulk-in ++ * endpoint. (Note: This violates the Bulk-Only Transport ++ * specification, which requires us to pad the data if we ++ * don't halt the endpoint. Presumably nobody will mind.) ++ */ ++ else { ++ bh->inreq->zero = 1; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ if (mod_data.can_stall) ++ rc = halt_bulk_in_endpoint(fsg); ++ } ++ break; ++ ++ /* We have processed all we want from the data the host has sent. ++ * There may still be outstanding bulk-out requests. */ ++ case DATA_DIR_FROM_HOST: ++ if (fsg->residue == 0) ++ ; // Nothing to receive ++ ++ /* Did the host stop sending unexpectedly early? */ ++ else if (fsg->short_packet_received) { ++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); ++ rc = -EINTR; ++ } ++ ++ /* We haven't processed all the incoming data. Even though ++ * we may be allowed to stall, doing so would cause a race. ++ * The controller may already have ACK'ed all the remaining ++ * bulk-out packets, in which case the host wouldn't see a ++ * STALL. Not realizing the endpoint was halted, it wouldn't ++ * clear the halt -- leading to problems later on. */ ++#if 0 ++ else if (mod_data.can_stall) { ++ fsg_set_halt(fsg, fsg->bulk_out); ++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); ++ rc = -EINTR; ++ } ++#endif ++ ++ /* We can't stall. Read in the excess data and throw it ++ * all away. */ ++ else ++ rc = throw_away_data(fsg); ++ break; ++ } ++ return rc; ++} ++ ++ ++static int send_status(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ struct fsg_buffhd *bh; ++ int rc; ++ u8 status = US_BULK_STAT_OK; ++ u32 sd, sdinfo = 0; ++ ++ /* Wait for the next buffer to become available */ ++ bh = fsg->next_buffhd_to_fill; ++ while (bh->state != BUF_STATE_EMPTY) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ if (curlun) { ++ sd = curlun->sense_data; ++ sdinfo = curlun->sense_data_info; ++ } else if (fsg->bad_lun_okay) ++ sd = SS_NO_SENSE; ++ else ++ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; ++ ++ if (fsg->phase_error) { ++ DBG(fsg, "sending phase-error status\n"); ++ status = US_BULK_STAT_PHASE; ++ sd = SS_INVALID_COMMAND; ++ } else if (sd != SS_NO_SENSE) { ++ DBG(fsg, "sending command-failure status\n"); ++ status = US_BULK_STAT_FAIL; ++ VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;" ++ " info x%x\n", ++ SK(sd), ASC(sd), ASCQ(sd), sdinfo); ++ } ++ ++ if (transport_is_bbb()) { ++ struct bulk_cs_wrap *csw = bh->buf; ++ ++ /* Store and send the Bulk-only CSW */ ++ csw->Signature = cpu_to_le32(US_BULK_CS_SIGN); ++ csw->Tag = fsg->tag; ++ csw->Residue = cpu_to_le32(fsg->residue); ++ csw->Status = status; ++ ++ bh->inreq->length = US_BULK_CS_WRAP_LEN; ++ bh->inreq->zero = 0; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ ++ } else if (mod_data.transport_type == USB_PR_CB) { ++ ++ /* Control-Bulk transport has no status phase! */ ++ return 0; ++ ++ } else { // USB_PR_CBI ++ struct interrupt_data *buf = bh->buf; ++ ++ /* Store and send the Interrupt data. UFI sends the ASC ++ * and ASCQ bytes. Everything else sends a Type (which ++ * is always 0) and the status Value. */ ++ if (mod_data.protocol_type == USB_SC_UFI) { ++ buf->bType = ASC(sd); ++ buf->bValue = ASCQ(sd); ++ } else { ++ buf->bType = 0; ++ buf->bValue = status; ++ } ++ fsg->intreq->length = CBI_INTERRUPT_DATA_LEN; ++ ++ fsg->intr_buffhd = bh; // Point to the right buffhd ++ fsg->intreq->buf = bh->inreq->buf; ++ fsg->intreq->context = bh; ++ start_transfer(fsg, fsg->intr_in, fsg->intreq, ++ &fsg->intreq_busy, &bh->state); ++ } ++ ++ fsg->next_buffhd_to_fill = bh->next; ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Check whether the command is properly formed and whether its data size ++ * and direction agree with the values we already have. */ ++static int check_command(struct fsg_dev *fsg, int cmnd_size, ++ enum data_direction data_dir, unsigned int mask, ++ int needs_medium, const char *name) ++{ ++ int i; ++ int lun = fsg->cmnd[1] >> 5; ++ static const char dirletter[4] = {'u', 'o', 'i', 'n'}; ++ char hdlen[20]; ++ struct fsg_lun *curlun; ++ ++ /* Adjust the expected cmnd_size for protocol encapsulation padding. ++ * Transparent SCSI doesn't pad. */ ++ if (protocol_is_scsi()) ++ ; ++ ++ /* There's some disagreement as to whether RBC pads commands or not. ++ * We'll play it safe and accept either form. */ ++ else if (mod_data.protocol_type == USB_SC_RBC) { ++ if (fsg->cmnd_size == 12) ++ cmnd_size = 12; ++ ++ /* All the other protocols pad to 12 bytes */ ++ } else ++ cmnd_size = 12; ++ ++ hdlen[0] = 0; ++ if (fsg->data_dir != DATA_DIR_UNKNOWN) ++ sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir], ++ fsg->data_size); ++ VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n", ++ name, cmnd_size, dirletter[(int) data_dir], ++ fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen); ++ ++ /* We can't reply at all until we know the correct data direction ++ * and size. */ ++ if (fsg->data_size_from_cmnd == 0) ++ data_dir = DATA_DIR_NONE; ++ if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI ++ fsg->data_dir = data_dir; ++ fsg->data_size = fsg->data_size_from_cmnd; ++ ++ } else { // Bulk-only ++ if (fsg->data_size < fsg->data_size_from_cmnd) { ++ ++ /* Host data size < Device data size is a phase error. ++ * Carry out the command, but only transfer as much ++ * as we are allowed. */ ++ fsg->data_size_from_cmnd = fsg->data_size; ++ fsg->phase_error = 1; ++ } ++ } ++ fsg->residue = fsg->usb_amount_left = fsg->data_size; ++ ++ /* Conflicting data directions is a phase error */ ++ if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) { ++ fsg->phase_error = 1; ++ return -EINVAL; ++ } ++ ++ /* Verify the length of the command itself */ ++ if (cmnd_size != fsg->cmnd_size) { ++ ++ /* Special case workaround: There are plenty of buggy SCSI ++ * implementations. Many have issues with cbw->Length ++ * field passing a wrong command size. For those cases we ++ * always try to work around the problem by using the length ++ * sent by the host side provided it is at least as large ++ * as the correct command length. ++ * Examples of such cases would be MS-Windows, which issues ++ * REQUEST SENSE with cbw->Length == 12 where it should ++ * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and ++ * REQUEST SENSE with cbw->Length == 10 where it should ++ * be 6 as well. ++ */ ++ if (cmnd_size <= fsg->cmnd_size) { ++ DBG(fsg, "%s is buggy! Expected length %d " ++ "but we got %d\n", name, ++ cmnd_size, fsg->cmnd_size); ++ cmnd_size = fsg->cmnd_size; ++ } else { ++ fsg->phase_error = 1; ++ return -EINVAL; ++ } ++ } ++ ++ /* Check that the LUN values are consistent */ ++ if (transport_is_bbb()) { ++ if (fsg->lun != lun) ++ DBG(fsg, "using LUN %d from CBW, " ++ "not LUN %d from CDB\n", ++ fsg->lun, lun); ++ } ++ ++ /* Check the LUN */ ++ curlun = fsg->curlun; ++ if (curlun) { ++ if (fsg->cmnd[0] != REQUEST_SENSE) { ++ curlun->sense_data = SS_NO_SENSE; ++ curlun->sense_data_info = 0; ++ curlun->info_valid = 0; ++ } ++ } else { ++ fsg->bad_lun_okay = 0; ++ ++ /* INQUIRY and REQUEST SENSE commands are explicitly allowed ++ * to use unsupported LUNs; all others may not. */ ++ if (fsg->cmnd[0] != INQUIRY && ++ fsg->cmnd[0] != REQUEST_SENSE) { ++ DBG(fsg, "unsupported LUN %d\n", fsg->lun); ++ return -EINVAL; ++ } ++ } ++ ++ /* If a unit attention condition exists, only INQUIRY and ++ * REQUEST SENSE commands are allowed; anything else must fail. */ ++ if (curlun && curlun->unit_attention_data != SS_NO_SENSE && ++ fsg->cmnd[0] != INQUIRY && ++ fsg->cmnd[0] != REQUEST_SENSE) { ++ curlun->sense_data = curlun->unit_attention_data; ++ curlun->unit_attention_data = SS_NO_SENSE; ++ return -EINVAL; ++ } ++ ++ /* Check that only command bytes listed in the mask are non-zero */ ++ fsg->cmnd[1] &= 0x1f; // Mask away the LUN ++ for (i = 1; i < cmnd_size; ++i) { ++ if (fsg->cmnd[i] && !(mask & (1 << i))) { ++ if (curlun) ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ } ++ ++ /* If the medium isn't mounted and the command needs to access ++ * it, return an error. */ ++ if (curlun && !fsg_lun_is_open(curlun) && needs_medium) { ++ curlun->sense_data = SS_MEDIUM_NOT_PRESENT; ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* wrapper of check_command for data size in blocks handling */ ++static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size, ++ enum data_direction data_dir, unsigned int mask, ++ int needs_medium, const char *name) ++{ ++ if (fsg->curlun) ++ fsg->data_size_from_cmnd <<= fsg->curlun->blkbits; ++ return check_command(fsg, cmnd_size, data_dir, ++ mask, needs_medium, name); ++} ++ ++static int do_scsi_command(struct fsg_dev *fsg) ++{ ++ struct fsg_buffhd *bh; ++ int rc; ++ int reply = -EINVAL; ++ int i; ++ static char unknown[16]; ++ ++ dump_cdb(fsg); ++ ++ /* Wait for the next buffer to become available for data or status */ ++ bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill; ++ while (bh->state != BUF_STATE_EMPTY) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ fsg->phase_error = 0; ++ fsg->short_packet_received = 0; ++ ++ down_read(&fsg->filesem); // We're using the backing file ++ switch (fsg->cmnd[0]) { ++ ++ case INQUIRY: ++ fsg->data_size_from_cmnd = fsg->cmnd[4]; ++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, ++ (1<<4), 0, ++ "INQUIRY")) == 0) ++ reply = do_inquiry(fsg, bh); ++ break; ++ ++ case MODE_SELECT: ++ fsg->data_size_from_cmnd = fsg->cmnd[4]; ++ if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST, ++ (1<<1) | (1<<4), 0, ++ "MODE SELECT(6)")) == 0) ++ reply = do_mode_select(fsg, bh); ++ break; ++ ++ case MODE_SELECT_10: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST, ++ (1<<1) | (3<<7), 0, ++ "MODE SELECT(10)")) == 0) ++ reply = do_mode_select(fsg, bh); ++ break; ++ ++ case MODE_SENSE: ++ fsg->data_size_from_cmnd = fsg->cmnd[4]; ++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, ++ (1<<1) | (1<<2) | (1<<4), 0, ++ "MODE SENSE(6)")) == 0) ++ reply = do_mode_sense(fsg, bh); ++ break; ++ ++ case MODE_SENSE_10: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (1<<1) | (1<<2) | (3<<7), 0, ++ "MODE SENSE(10)")) == 0) ++ reply = do_mode_sense(fsg, bh); ++ break; ++ ++ case ALLOW_MEDIUM_REMOVAL: ++ fsg->data_size_from_cmnd = 0; ++ if ((reply = check_command(fsg, 6, DATA_DIR_NONE, ++ (1<<4), 0, ++ "PREVENT-ALLOW MEDIUM REMOVAL")) == 0) ++ reply = do_prevent_allow(fsg); ++ break; ++ ++ case READ_6: ++ i = fsg->cmnd[4]; ++ fsg->data_size_from_cmnd = (i == 0) ? 256 : i; ++ if ((reply = check_command_size_in_blocks(fsg, 6, ++ DATA_DIR_TO_HOST, ++ (7<<1) | (1<<4), 1, ++ "READ(6)")) == 0) ++ reply = do_read(fsg); ++ break; ++ ++ case READ_10: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command_size_in_blocks(fsg, 10, ++ DATA_DIR_TO_HOST, ++ (1<<1) | (0xf<<2) | (3<<7), 1, ++ "READ(10)")) == 0) ++ reply = do_read(fsg); ++ break; ++ ++ case READ_12: ++ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]); ++ if ((reply = check_command_size_in_blocks(fsg, 12, ++ DATA_DIR_TO_HOST, ++ (1<<1) | (0xf<<2) | (0xf<<6), 1, ++ "READ(12)")) == 0) ++ reply = do_read(fsg); ++ break; ++ ++ case READ_CAPACITY: ++ fsg->data_size_from_cmnd = 8; ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (0xf<<2) | (1<<8), 1, ++ "READ CAPACITY")) == 0) ++ reply = do_read_capacity(fsg, bh); ++ break; ++ ++ case READ_HEADER: ++ if (!mod_data.cdrom) ++ goto unknown_cmnd; ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (3<<7) | (0x1f<<1), 1, ++ "READ HEADER")) == 0) ++ reply = do_read_header(fsg, bh); ++ break; ++ ++ case READ_TOC: ++ if (!mod_data.cdrom) ++ goto unknown_cmnd; ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (7<<6) | (1<<1), 1, ++ "READ TOC")) == 0) ++ reply = do_read_toc(fsg, bh); ++ break; ++ ++ case READ_FORMAT_CAPACITIES: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (3<<7), 1, ++ "READ FORMAT CAPACITIES")) == 0) ++ reply = do_read_format_capacities(fsg, bh); ++ break; ++ ++ case REQUEST_SENSE: ++ fsg->data_size_from_cmnd = fsg->cmnd[4]; ++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, ++ (1<<4), 0, ++ "REQUEST SENSE")) == 0) ++ reply = do_request_sense(fsg, bh); ++ break; ++ ++ case START_STOP: ++ fsg->data_size_from_cmnd = 0; ++ if ((reply = check_command(fsg, 6, DATA_DIR_NONE, ++ (1<<1) | (1<<4), 0, ++ "START-STOP UNIT")) == 0) ++ reply = do_start_stop(fsg); ++ break; ++ ++ case SYNCHRONIZE_CACHE: ++ fsg->data_size_from_cmnd = 0; ++ if ((reply = check_command(fsg, 10, DATA_DIR_NONE, ++ (0xf<<2) | (3<<7), 1, ++ "SYNCHRONIZE CACHE")) == 0) ++ reply = do_synchronize_cache(fsg); ++ break; ++ ++ case TEST_UNIT_READY: ++ fsg->data_size_from_cmnd = 0; ++ reply = check_command(fsg, 6, DATA_DIR_NONE, ++ 0, 1, ++ "TEST UNIT READY"); ++ break; ++ ++ /* Although optional, this command is used by MS-Windows. We ++ * support a minimal version: BytChk must be 0. */ ++ case VERIFY: ++ fsg->data_size_from_cmnd = 0; ++ if ((reply = check_command(fsg, 10, DATA_DIR_NONE, ++ (1<<1) | (0xf<<2) | (3<<7), 1, ++ "VERIFY")) == 0) ++ reply = do_verify(fsg); ++ break; ++ ++ case WRITE_6: ++ i = fsg->cmnd[4]; ++ fsg->data_size_from_cmnd = (i == 0) ? 256 : i; ++ if ((reply = check_command_size_in_blocks(fsg, 6, ++ DATA_DIR_FROM_HOST, ++ (7<<1) | (1<<4), 1, ++ "WRITE(6)")) == 0) ++ reply = do_write(fsg); ++ break; ++ ++ case WRITE_10: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command_size_in_blocks(fsg, 10, ++ DATA_DIR_FROM_HOST, ++ (1<<1) | (0xf<<2) | (3<<7), 1, ++ "WRITE(10)")) == 0) ++ reply = do_write(fsg); ++ break; ++ ++ case WRITE_12: ++ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]); ++ if ((reply = check_command_size_in_blocks(fsg, 12, ++ DATA_DIR_FROM_HOST, ++ (1<<1) | (0xf<<2) | (0xf<<6), 1, ++ "WRITE(12)")) == 0) ++ reply = do_write(fsg); ++ break; ++ ++ /* Some mandatory commands that we recognize but don't implement. ++ * They don't mean much in this setting. It's left as an exercise ++ * for anyone interested to implement RESERVE and RELEASE in terms ++ * of Posix locks. */ ++ case FORMAT_UNIT: ++ case RELEASE: ++ case RESERVE: ++ case SEND_DIAGNOSTIC: ++ // Fall through ++ ++ default: ++ unknown_cmnd: ++ fsg->data_size_from_cmnd = 0; ++ sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]); ++ if ((reply = check_command(fsg, fsg->cmnd_size, ++ DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) { ++ fsg->curlun->sense_data = SS_INVALID_COMMAND; ++ reply = -EINVAL; ++ } ++ break; ++ } ++ up_read(&fsg->filesem); ++ ++ if (reply == -EINTR || signal_pending(current)) ++ return -EINTR; ++ ++ /* Set up the single reply buffer for finish_reply() */ ++ if (reply == -EINVAL) ++ reply = 0; // Error reply length ++ if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) { ++ reply = min((u32) reply, fsg->data_size_from_cmnd); ++ bh->inreq->length = reply; ++ bh->state = BUF_STATE_FULL; ++ fsg->residue -= reply; ++ } // Otherwise it's already set ++ ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct usb_request *req = bh->outreq; ++ struct bulk_cb_wrap *cbw = req->buf; ++ ++ /* Was this a real packet? Should it be ignored? */ ++ if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags)) ++ return -EINVAL; ++ ++ /* Is the CBW valid? */ ++ if (req->actual != US_BULK_CB_WRAP_LEN || ++ cbw->Signature != cpu_to_le32( ++ US_BULK_CB_SIGN)) { ++ DBG(fsg, "invalid CBW: len %u sig 0x%x\n", ++ req->actual, ++ le32_to_cpu(cbw->Signature)); ++ ++ /* The Bulk-only spec says we MUST stall the IN endpoint ++ * (6.6.1), so it's unavoidable. It also says we must ++ * retain this state until the next reset, but there's ++ * no way to tell the controller driver it should ignore ++ * Clear-Feature(HALT) requests. ++ * ++ * We aren't required to halt the OUT endpoint; instead ++ * we can simply accept and discard any data received ++ * until the next reset. */ ++ wedge_bulk_in_endpoint(fsg); ++ set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags); ++ return -EINVAL; ++ } ++ ++ /* Is the CBW meaningful? */ ++ if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN || ++ cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) { ++ DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, " ++ "cmdlen %u\n", ++ cbw->Lun, cbw->Flags, cbw->Length); ++ ++ /* We can do anything we want here, so let's stall the ++ * bulk pipes if we are allowed to. */ ++ if (mod_data.can_stall) { ++ fsg_set_halt(fsg, fsg->bulk_out); ++ halt_bulk_in_endpoint(fsg); ++ } ++ return -EINVAL; ++ } ++ ++ /* Save the command for later */ ++ fsg->cmnd_size = cbw->Length; ++ memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size); ++ if (cbw->Flags & US_BULK_FLAG_IN) ++ fsg->data_dir = DATA_DIR_TO_HOST; ++ else ++ fsg->data_dir = DATA_DIR_FROM_HOST; ++ fsg->data_size = le32_to_cpu(cbw->DataTransferLength); ++ if (fsg->data_size == 0) ++ fsg->data_dir = DATA_DIR_NONE; ++ fsg->lun = cbw->Lun; ++ fsg->tag = cbw->Tag; ++ return 0; ++} ++ ++ ++static int get_next_command(struct fsg_dev *fsg) ++{ ++ struct fsg_buffhd *bh; ++ int rc = 0; ++ ++ if (transport_is_bbb()) { ++ ++ /* Wait for the next buffer to become available */ ++ bh = fsg->next_buffhd_to_fill; ++ while (bh->state != BUF_STATE_EMPTY) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ /* Queue a request to read a Bulk-only CBW */ ++ set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN); ++ start_transfer(fsg, fsg->bulk_out, bh->outreq, ++ &bh->outreq_busy, &bh->state); ++ ++ /* We will drain the buffer in software, which means we ++ * can reuse it for the next filling. No need to advance ++ * next_buffhd_to_fill. */ ++ ++ /* Wait for the CBW to arrive */ ++ while (bh->state != BUF_STATE_FULL) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ smp_rmb(); ++ rc = received_cbw(fsg, bh); ++ bh->state = BUF_STATE_EMPTY; ++ ++ } else { // USB_PR_CB or USB_PR_CBI ++ ++ /* Wait for the next command to arrive */ ++ while (fsg->cbbuf_cmnd_size == 0) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ /* Is the previous status interrupt request still busy? ++ * The host is allowed to skip reading the status, ++ * so we must cancel it. */ ++ if (fsg->intreq_busy) ++ usb_ep_dequeue(fsg->intr_in, fsg->intreq); ++ ++ /* Copy the command and mark the buffer empty */ ++ fsg->data_dir = DATA_DIR_UNKNOWN; ++ spin_lock_irq(&fsg->lock); ++ fsg->cmnd_size = fsg->cbbuf_cmnd_size; ++ memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size); ++ fsg->cbbuf_cmnd_size = 0; ++ spin_unlock_irq(&fsg->lock); ++ ++ /* Use LUN from the command */ ++ fsg->lun = fsg->cmnd[1] >> 5; ++ } ++ ++ /* Update current lun */ ++ if (fsg->lun >= 0 && fsg->lun < fsg->nluns) ++ fsg->curlun = &fsg->luns[fsg->lun]; ++ else ++ fsg->curlun = NULL; ++ ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep, ++ const struct usb_endpoint_descriptor *d) ++{ ++ int rc; ++ ++ ep->driver_data = fsg; ++ ep->desc = d; ++ rc = usb_ep_enable(ep); ++ if (rc) ++ ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc); ++ return rc; ++} ++ ++static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep, ++ struct usb_request **preq) ++{ ++ *preq = usb_ep_alloc_request(ep, GFP_ATOMIC); ++ if (*preq) ++ return 0; ++ ERROR(fsg, "can't allocate request for %s\n", ep->name); ++ return -ENOMEM; ++} ++ ++/* ++ * Reset interface setting and re-init endpoint state (toggle etc). ++ * Call with altsetting < 0 to disable the interface. The only other ++ * available altsetting is 0, which enables the interface. ++ */ ++static int do_set_interface(struct fsg_dev *fsg, int altsetting) ++{ ++ int rc = 0; ++ int i; ++ const struct usb_endpoint_descriptor *d; ++ ++ if (fsg->running) ++ DBG(fsg, "reset interface\n"); ++ ++reset: ++ /* Deallocate the requests */ ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ struct fsg_buffhd *bh = &fsg->buffhds[i]; ++ ++ if (bh->inreq) { ++ usb_ep_free_request(fsg->bulk_in, bh->inreq); ++ bh->inreq = NULL; ++ } ++ if (bh->outreq) { ++ usb_ep_free_request(fsg->bulk_out, bh->outreq); ++ bh->outreq = NULL; ++ } ++ } ++ if (fsg->intreq) { ++ usb_ep_free_request(fsg->intr_in, fsg->intreq); ++ fsg->intreq = NULL; ++ } ++ ++ /* Disable the endpoints */ ++ if (fsg->bulk_in_enabled) { ++ usb_ep_disable(fsg->bulk_in); ++ fsg->bulk_in_enabled = 0; ++ } ++ if (fsg->bulk_out_enabled) { ++ usb_ep_disable(fsg->bulk_out); ++ fsg->bulk_out_enabled = 0; ++ } ++ if (fsg->intr_in_enabled) { ++ usb_ep_disable(fsg->intr_in); ++ fsg->intr_in_enabled = 0; ++ } ++ ++ fsg->running = 0; ++ if (altsetting < 0 || rc != 0) ++ return rc; ++ ++ DBG(fsg, "set interface %d\n", altsetting); ++ ++ /* Enable the endpoints */ ++ d = fsg_ep_desc(fsg->gadget, ++ &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc, ++ &fsg_ss_bulk_in_desc); ++ if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0) ++ goto reset; ++ fsg->bulk_in_enabled = 1; ++ ++ d = fsg_ep_desc(fsg->gadget, ++ &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc, ++ &fsg_ss_bulk_out_desc); ++ if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0) ++ goto reset; ++ fsg->bulk_out_enabled = 1; ++ fsg->bulk_out_maxpacket = usb_endpoint_maxp(d); ++ clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags); ++ ++ if (transport_is_cbi()) { ++ d = fsg_ep_desc(fsg->gadget, ++ &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc, ++ &fsg_ss_intr_in_desc); ++ if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0) ++ goto reset; ++ fsg->intr_in_enabled = 1; ++ } ++ ++ /* Allocate the requests */ ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ struct fsg_buffhd *bh = &fsg->buffhds[i]; ++ ++ if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0) ++ goto reset; ++ if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0) ++ goto reset; ++ bh->inreq->buf = bh->outreq->buf = bh->buf; ++ bh->inreq->context = bh->outreq->context = bh; ++ bh->inreq->complete = bulk_in_complete; ++ bh->outreq->complete = bulk_out_complete; ++ } ++ if (transport_is_cbi()) { ++ if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0) ++ goto reset; ++ fsg->intreq->complete = intr_in_complete; ++ } ++ ++ fsg->running = 1; ++ for (i = 0; i < fsg->nluns; ++i) ++ fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED; ++ return rc; ++} ++ ++ ++/* ++ * Change our operational configuration. This code must agree with the code ++ * that returns config descriptors, and with interface altsetting code. ++ * ++ * It's also responsible for power management interactions. Some ++ * configurations might not work with our current power sources. ++ * For now we just assume the gadget is always self-powered. ++ */ ++static int do_set_config(struct fsg_dev *fsg, u8 new_config) ++{ ++ int rc = 0; ++ ++ /* Disable the single interface */ ++ if (fsg->config != 0) { ++ DBG(fsg, "reset config\n"); ++ fsg->config = 0; ++ rc = do_set_interface(fsg, -1); ++ } ++ ++ /* Enable the interface */ ++ if (new_config != 0) { ++ fsg->config = new_config; ++ if ((rc = do_set_interface(fsg, 0)) != 0) ++ fsg->config = 0; // Reset on errors ++ else ++ INFO(fsg, "%s config #%d\n", ++ usb_speed_string(fsg->gadget->speed), ++ fsg->config); ++ } ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void handle_exception(struct fsg_dev *fsg) ++{ ++ siginfo_t info; ++ int sig; ++ int i; ++ int num_active; ++ struct fsg_buffhd *bh; ++ enum fsg_state old_state; ++ u8 new_config; ++ struct fsg_lun *curlun; ++ unsigned int exception_req_tag; ++ int rc; ++ ++ /* Clear the existing signals. Anything but SIGUSR1 is converted ++ * into a high-priority EXIT exception. */ ++ for (;;) { ++ sig = dequeue_signal_lock(current, ¤t->blocked, &info); ++ if (!sig) ++ break; ++ if (sig != SIGUSR1) { ++ if (fsg->state < FSG_STATE_EXIT) ++ DBG(fsg, "Main thread exiting on signal\n"); ++ raise_exception(fsg, FSG_STATE_EXIT); ++ } ++ } ++ ++ /* Cancel all the pending transfers */ ++ if (fsg->intreq_busy) ++ usb_ep_dequeue(fsg->intr_in, fsg->intreq); ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ bh = &fsg->buffhds[i]; ++ if (bh->inreq_busy) ++ usb_ep_dequeue(fsg->bulk_in, bh->inreq); ++ if (bh->outreq_busy) ++ usb_ep_dequeue(fsg->bulk_out, bh->outreq); ++ } ++ ++ /* Wait until everything is idle */ ++ for (;;) { ++ num_active = fsg->intreq_busy; ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ bh = &fsg->buffhds[i]; ++ num_active += bh->inreq_busy + bh->outreq_busy; ++ } ++ if (num_active == 0) ++ break; ++ if (sleep_thread(fsg)) ++ return; ++ } ++ ++ /* Clear out the controller's fifos */ ++ if (fsg->bulk_in_enabled) ++ usb_ep_fifo_flush(fsg->bulk_in); ++ if (fsg->bulk_out_enabled) ++ usb_ep_fifo_flush(fsg->bulk_out); ++ if (fsg->intr_in_enabled) ++ usb_ep_fifo_flush(fsg->intr_in); ++ ++ /* Reset the I/O buffer states and pointers, the SCSI ++ * state, and the exception. Then invoke the handler. */ ++ spin_lock_irq(&fsg->lock); ++ ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ bh = &fsg->buffhds[i]; ++ bh->state = BUF_STATE_EMPTY; ++ } ++ fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain = ++ &fsg->buffhds[0]; ++ ++ exception_req_tag = fsg->exception_req_tag; ++ new_config = fsg->new_config; ++ old_state = fsg->state; ++ ++ if (old_state == FSG_STATE_ABORT_BULK_OUT) ++ fsg->state = FSG_STATE_STATUS_PHASE; ++ else { ++ for (i = 0; i < fsg->nluns; ++i) { ++ curlun = &fsg->luns[i]; ++ curlun->prevent_medium_removal = 0; ++ curlun->sense_data = curlun->unit_attention_data = ++ SS_NO_SENSE; ++ curlun->sense_data_info = 0; ++ curlun->info_valid = 0; ++ } ++ fsg->state = FSG_STATE_IDLE; ++ } ++ spin_unlock_irq(&fsg->lock); ++ ++ /* Carry out any extra actions required for the exception */ ++ switch (old_state) { ++ default: ++ break; ++ ++ case FSG_STATE_ABORT_BULK_OUT: ++ send_status(fsg); ++ spin_lock_irq(&fsg->lock); ++ if (fsg->state == FSG_STATE_STATUS_PHASE) ++ fsg->state = FSG_STATE_IDLE; ++ spin_unlock_irq(&fsg->lock); ++ break; ++ ++ case FSG_STATE_RESET: ++ /* In case we were forced against our will to halt a ++ * bulk endpoint, clear the halt now. (The SuperH UDC ++ * requires this.) */ ++ if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags)) ++ usb_ep_clear_halt(fsg->bulk_in); ++ ++ if (transport_is_bbb()) { ++ if (fsg->ep0_req_tag == exception_req_tag) ++ ep0_queue(fsg); // Complete the status stage ++ ++ } else if (transport_is_cbi()) ++ send_status(fsg); // Status by interrupt pipe ++ ++ /* Technically this should go here, but it would only be ++ * a waste of time. Ditto for the INTERFACE_CHANGE and ++ * CONFIG_CHANGE cases. */ ++ // for (i = 0; i < fsg->nluns; ++i) ++ // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED; ++ break; ++ ++ case FSG_STATE_INTERFACE_CHANGE: ++ rc = do_set_interface(fsg, 0); ++ if (fsg->ep0_req_tag != exception_req_tag) ++ break; ++ if (rc != 0) // STALL on errors ++ fsg_set_halt(fsg, fsg->ep0); ++ else // Complete the status stage ++ ep0_queue(fsg); ++ break; ++ ++ case FSG_STATE_CONFIG_CHANGE: ++ rc = do_set_config(fsg, new_config); ++ if (fsg->ep0_req_tag != exception_req_tag) ++ break; ++ if (rc != 0) // STALL on errors ++ fsg_set_halt(fsg, fsg->ep0); ++ else // Complete the status stage ++ ep0_queue(fsg); ++ break; ++ ++ case FSG_STATE_DISCONNECT: ++ for (i = 0; i < fsg->nluns; ++i) ++ fsg_lun_fsync_sub(fsg->luns + i); ++ do_set_config(fsg, 0); // Unconfigured state ++ break; ++ ++ case FSG_STATE_EXIT: ++ case FSG_STATE_TERMINATED: ++ do_set_config(fsg, 0); // Free resources ++ spin_lock_irq(&fsg->lock); ++ fsg->state = FSG_STATE_TERMINATED; // Stop the thread ++ spin_unlock_irq(&fsg->lock); ++ break; ++ } ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int fsg_main_thread(void *fsg_) ++{ ++ struct fsg_dev *fsg = fsg_; ++ ++ /* Allow the thread to be killed by a signal, but set the signal mask ++ * to block everything but INT, TERM, KILL, and USR1. */ ++ allow_signal(SIGINT); ++ allow_signal(SIGTERM); ++ allow_signal(SIGKILL); ++ allow_signal(SIGUSR1); ++ ++ /* Allow the thread to be frozen */ ++ set_freezable(); ++ ++ /* Arrange for userspace references to be interpreted as kernel ++ * pointers. That way we can pass a kernel pointer to a routine ++ * that expects a __user pointer and it will work okay. */ ++ set_fs(get_ds()); ++ ++ /* The main loop */ ++ while (fsg->state != FSG_STATE_TERMINATED) { ++ if (exception_in_progress(fsg) || signal_pending(current)) { ++ handle_exception(fsg); ++ continue; ++ } ++ ++ if (!fsg->running) { ++ sleep_thread(fsg); ++ continue; ++ } ++ ++ if (get_next_command(fsg)) ++ continue; ++ ++ spin_lock_irq(&fsg->lock); ++ if (!exception_in_progress(fsg)) ++ fsg->state = FSG_STATE_DATA_PHASE; ++ spin_unlock_irq(&fsg->lock); ++ ++ if (do_scsi_command(fsg) || finish_reply(fsg)) ++ continue; ++ ++ spin_lock_irq(&fsg->lock); ++ if (!exception_in_progress(fsg)) ++ fsg->state = FSG_STATE_STATUS_PHASE; ++ spin_unlock_irq(&fsg->lock); ++ ++ if (send_status(fsg)) ++ continue; ++ ++ spin_lock_irq(&fsg->lock); ++ if (!exception_in_progress(fsg)) ++ fsg->state = FSG_STATE_IDLE; ++ spin_unlock_irq(&fsg->lock); ++ } ++ ++ spin_lock_irq(&fsg->lock); ++ fsg->thread_task = NULL; ++ spin_unlock_irq(&fsg->lock); ++ ++ /* If we are exiting because of a signal, unregister the ++ * gadget driver. */ ++ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags)) ++ usb_gadget_unregister_driver(&fsg_driver); ++ ++ /* Let the unbind and cleanup routines know the thread has exited */ ++ complete_and_exit(&fsg->thread_notifier, 0); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++ ++/* The write permissions and store_xxx pointers are set in fsg_bind() */ ++static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL); ++static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL); ++static DEVICE_ATTR(file, 0444, fsg_show_file, NULL); ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void fsg_release(struct kref *ref) ++{ ++ struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref); ++ ++ kfree(fsg->luns); ++ kfree(fsg); ++} ++ ++static void lun_release(struct device *dev) ++{ ++ struct rw_semaphore *filesem = dev_get_drvdata(dev); ++ struct fsg_dev *fsg = ++ container_of(filesem, struct fsg_dev, filesem); ++ ++ kref_put(&fsg->ref, fsg_release); ++} ++ ++static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ int i; ++ struct fsg_lun *curlun; ++ struct usb_request *req = fsg->ep0req; ++ ++ DBG(fsg, "unbind\n"); ++ clear_bit(REGISTERED, &fsg->atomic_bitflags); ++ ++ /* If the thread isn't already dead, tell it to exit now */ ++ if (fsg->state != FSG_STATE_TERMINATED) { ++ raise_exception(fsg, FSG_STATE_EXIT); ++ wait_for_completion(&fsg->thread_notifier); ++ ++ /* The cleanup routine waits for this completion also */ ++ complete(&fsg->thread_notifier); ++ } ++ ++ /* Unregister the sysfs attribute files and the LUNs */ ++ for (i = 0; i < fsg->nluns; ++i) { ++ curlun = &fsg->luns[i]; ++ if (curlun->registered) { ++ device_remove_file(&curlun->dev, &dev_attr_nofua); ++ device_remove_file(&curlun->dev, &dev_attr_ro); ++ device_remove_file(&curlun->dev, &dev_attr_file); ++ fsg_lun_close(curlun); ++ device_unregister(&curlun->dev); ++ curlun->registered = 0; ++ } ++ } ++ ++ /* Free the data buffers */ ++ for (i = 0; i < fsg_num_buffers; ++i) ++ kfree(fsg->buffhds[i].buf); ++ ++ /* Free the request and buffer for endpoint 0 */ ++ if (req) { ++ kfree(req->buf); ++ usb_ep_free_request(fsg->ep0, req); ++ } ++ ++ set_gadget_data(gadget, NULL); ++} ++ ++ ++static int __init check_parameters(struct fsg_dev *fsg) ++{ ++ int prot; ++ int gcnum; ++ ++ /* Store the default values */ ++ mod_data.transport_type = USB_PR_BULK; ++ mod_data.transport_name = "Bulk-only"; ++ mod_data.protocol_type = USB_SC_SCSI; ++ mod_data.protocol_name = "Transparent SCSI"; ++ ++ /* Some peripheral controllers are known not to be able to ++ * halt bulk endpoints correctly. If one of them is present, ++ * disable stalls. ++ */ ++ if (gadget_is_at91(fsg->gadget)) ++ mod_data.can_stall = 0; ++ ++ if (mod_data.release == 0xffff) { // Parameter wasn't set ++ gcnum = usb_gadget_controller_number(fsg->gadget); ++ if (gcnum >= 0) ++ mod_data.release = 0x0300 + gcnum; ++ else { ++ WARNING(fsg, "controller '%s' not recognized\n", ++ fsg->gadget->name); ++ mod_data.release = 0x0399; ++ } ++ } ++ ++ prot = simple_strtol(mod_data.protocol_parm, NULL, 0); ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++ if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) { ++ ; // Use default setting ++ } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) { ++ mod_data.transport_type = USB_PR_CB; ++ mod_data.transport_name = "Control-Bulk"; ++ } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) { ++ mod_data.transport_type = USB_PR_CBI; ++ mod_data.transport_name = "Control-Bulk-Interrupt"; ++ } else { ++ ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm); ++ return -EINVAL; ++ } ++ ++ if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 || ++ prot == USB_SC_SCSI) { ++ ; // Use default setting ++ } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 || ++ prot == USB_SC_RBC) { ++ mod_data.protocol_type = USB_SC_RBC; ++ mod_data.protocol_name = "RBC"; ++ } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 || ++ strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 || ++ prot == USB_SC_8020) { ++ mod_data.protocol_type = USB_SC_8020; ++ mod_data.protocol_name = "8020i (ATAPI)"; ++ } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 || ++ prot == USB_SC_QIC) { ++ mod_data.protocol_type = USB_SC_QIC; ++ mod_data.protocol_name = "QIC-157"; ++ } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 || ++ prot == USB_SC_UFI) { ++ mod_data.protocol_type = USB_SC_UFI; ++ mod_data.protocol_name = "UFI"; ++ } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 || ++ prot == USB_SC_8070) { ++ mod_data.protocol_type = USB_SC_8070; ++ mod_data.protocol_name = "8070i"; ++ } else { ++ ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm); ++ return -EINVAL; ++ } ++ ++ mod_data.buflen &= PAGE_CACHE_MASK; ++ if (mod_data.buflen <= 0) { ++ ERROR(fsg, "invalid buflen\n"); ++ return -ETOOSMALL; ++ } ++ ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ /* Serial string handling. ++ * On a real device, the serial string would be loaded ++ * from permanent storage. */ ++ if (mod_data.serial) { ++ const char *ch; ++ unsigned len = 0; ++ ++ /* Sanity check : ++ * The CB[I] specification limits the serial string to ++ * 12 uppercase hexadecimal characters. ++ * BBB need at least 12 uppercase hexadecimal characters, ++ * with a maximum of 126. */ ++ for (ch = mod_data.serial; *ch; ++ch) { ++ ++len; ++ if ((*ch < '0' || *ch > '9') && ++ (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */ ++ WARNING(fsg, ++ "Invalid serial string character: %c\n", ++ *ch); ++ goto no_serial; ++ } ++ } ++ if (len > 126 || ++ (mod_data.transport_type == USB_PR_BULK && len < 12) || ++ (mod_data.transport_type != USB_PR_BULK && len > 12)) { ++ WARNING(fsg, "Invalid serial string length!\n"); ++ goto no_serial; ++ } ++ fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial; ++ } else { ++ WARNING(fsg, "No serial-number string provided!\n"); ++ no_serial: ++ device_desc.iSerialNumber = 0; ++ } ++ ++ return 0; ++} ++ ++ ++static int __init fsg_bind(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = the_fsg; ++ int rc; ++ int i; ++ struct fsg_lun *curlun; ++ struct usb_ep *ep; ++ struct usb_request *req; ++ char *pathbuf, *p; ++ ++ fsg->gadget = gadget; ++ set_gadget_data(gadget, fsg); ++ fsg->ep0 = gadget->ep0; ++ fsg->ep0->driver_data = fsg; ++ ++ if ((rc = check_parameters(fsg)) != 0) ++ goto out; ++ ++ if (mod_data.removable) { // Enable the store_xxx attributes ++ dev_attr_file.attr.mode = 0644; ++ dev_attr_file.store = fsg_store_file; ++ if (!mod_data.cdrom) { ++ dev_attr_ro.attr.mode = 0644; ++ dev_attr_ro.store = fsg_store_ro; ++ } ++ } ++ ++ /* Only for removable media? */ ++ dev_attr_nofua.attr.mode = 0644; ++ dev_attr_nofua.store = fsg_store_nofua; ++ ++ /* Find out how many LUNs there should be */ ++ i = mod_data.nluns; ++ if (i == 0) ++ i = max(mod_data.num_filenames, 1u); ++ if (i > FSG_MAX_LUNS) { ++ ERROR(fsg, "invalid number of LUNs: %d\n", i); ++ rc = -EINVAL; ++ goto out; ++ } ++ ++ /* Create the LUNs, open their backing files, and register the ++ * LUN devices in sysfs. */ ++ fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL); ++ if (!fsg->luns) { ++ rc = -ENOMEM; ++ goto out; ++ } ++ fsg->nluns = i; ++ ++ for (i = 0; i < fsg->nluns; ++i) { ++ curlun = &fsg->luns[i]; ++ curlun->cdrom = !!mod_data.cdrom; ++ curlun->ro = mod_data.cdrom || mod_data.ro[i]; ++ curlun->initially_ro = curlun->ro; ++ curlun->removable = mod_data.removable; ++ curlun->nofua = mod_data.nofua[i]; ++ curlun->dev.release = lun_release; ++ curlun->dev.parent = &gadget->dev; ++ curlun->dev.driver = &fsg_driver.driver; ++ dev_set_drvdata(&curlun->dev, &fsg->filesem); ++ dev_set_name(&curlun->dev,"%s-lun%d", ++ dev_name(&gadget->dev), i); ++ ++ kref_get(&fsg->ref); ++ rc = device_register(&curlun->dev); ++ if (rc) { ++ INFO(fsg, "failed to register LUN%d: %d\n", i, rc); ++ put_device(&curlun->dev); ++ goto out; ++ } ++ curlun->registered = 1; ++ ++ rc = device_create_file(&curlun->dev, &dev_attr_ro); ++ if (rc) ++ goto out; ++ rc = device_create_file(&curlun->dev, &dev_attr_nofua); ++ if (rc) ++ goto out; ++ rc = device_create_file(&curlun->dev, &dev_attr_file); ++ if (rc) ++ goto out; ++ ++ if (mod_data.file[i] && *mod_data.file[i]) { ++ rc = fsg_lun_open(curlun, mod_data.file[i]); ++ if (rc) ++ goto out; ++ } else if (!mod_data.removable) { ++ ERROR(fsg, "no file given for LUN%d\n", i); ++ rc = -EINVAL; ++ goto out; ++ } ++ } ++ ++ /* Find all the endpoints we will use */ ++ usb_ep_autoconfig_reset(gadget); ++ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc); ++ if (!ep) ++ goto autoconf_fail; ++ ep->driver_data = fsg; // claim the endpoint ++ fsg->bulk_in = ep; ++ ++ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc); ++ if (!ep) ++ goto autoconf_fail; ++ ep->driver_data = fsg; // claim the endpoint ++ fsg->bulk_out = ep; ++ ++ if (transport_is_cbi()) { ++ ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc); ++ if (!ep) ++ goto autoconf_fail; ++ ep->driver_data = fsg; // claim the endpoint ++ fsg->intr_in = ep; ++ } ++ ++ /* Fix up the descriptors */ ++ device_desc.idVendor = cpu_to_le16(mod_data.vendor); ++ device_desc.idProduct = cpu_to_le16(mod_data.product); ++ device_desc.bcdDevice = cpu_to_le16(mod_data.release); ++ ++ i = (transport_is_cbi() ? 3 : 2); // Number of endpoints ++ fsg_intf_desc.bNumEndpoints = i; ++ fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type; ++ fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type; ++ fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL; ++ ++ if (gadget_is_dualspeed(gadget)) { ++ fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL; ++ ++ /* Assume endpoint addresses are the same for both speeds */ ++ fsg_hs_bulk_in_desc.bEndpointAddress = ++ fsg_fs_bulk_in_desc.bEndpointAddress; ++ fsg_hs_bulk_out_desc.bEndpointAddress = ++ fsg_fs_bulk_out_desc.bEndpointAddress; ++ fsg_hs_intr_in_desc.bEndpointAddress = ++ fsg_fs_intr_in_desc.bEndpointAddress; ++ } ++ ++ if (gadget_is_superspeed(gadget)) { ++ unsigned max_burst; ++ ++ fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL; ++ ++ /* Calculate bMaxBurst, we know packet size is 1024 */ ++ max_burst = min_t(unsigned, mod_data.buflen / 1024, 15); ++ ++ /* Assume endpoint addresses are the same for both speeds */ ++ fsg_ss_bulk_in_desc.bEndpointAddress = ++ fsg_fs_bulk_in_desc.bEndpointAddress; ++ fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst; ++ ++ fsg_ss_bulk_out_desc.bEndpointAddress = ++ fsg_fs_bulk_out_desc.bEndpointAddress; ++ fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst; ++ } ++ ++ if (gadget_is_otg(gadget)) ++ fsg_otg_desc.bmAttributes |= USB_OTG_HNP; ++ ++ rc = -ENOMEM; ++ ++ /* Allocate the request and buffer for endpoint 0 */ ++ fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL); ++ if (!req) ++ goto out; ++ req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL); ++ if (!req->buf) ++ goto out; ++ req->complete = ep0_complete; ++ ++ /* Allocate the data buffers */ ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ struct fsg_buffhd *bh = &fsg->buffhds[i]; ++ ++ /* Allocate for the bulk-in endpoint. We assume that ++ * the buffer will also work with the bulk-out (and ++ * interrupt-in) endpoint. */ ++ bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL); ++ if (!bh->buf) ++ goto out; ++ bh->next = bh + 1; ++ } ++ fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0]; ++ ++ /* This should reflect the actual gadget power source */ ++ usb_gadget_set_selfpowered(gadget); ++ ++ snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer, ++ "%s %s with %s", ++ init_utsname()->sysname, init_utsname()->release, ++ gadget->name); ++ ++ fsg->thread_task = kthread_create(fsg_main_thread, fsg, ++ "file-storage-gadget"); ++ if (IS_ERR(fsg->thread_task)) { ++ rc = PTR_ERR(fsg->thread_task); ++ goto out; ++ } ++ ++ INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n"); ++ INFO(fsg, "NOTE: This driver is deprecated. " ++ "Consider using g_mass_storage instead.\n"); ++ INFO(fsg, "Number of LUNs=%d\n", fsg->nluns); ++ ++ pathbuf = kmalloc(PATH_MAX, GFP_KERNEL); ++ for (i = 0; i < fsg->nluns; ++i) { ++ curlun = &fsg->luns[i]; ++ if (fsg_lun_is_open(curlun)) { ++ p = NULL; ++ if (pathbuf) { ++ p = d_path(&curlun->filp->f_path, ++ pathbuf, PATH_MAX); ++ if (IS_ERR(p)) ++ p = NULL; ++ } ++ LINFO(curlun, "ro=%d, nofua=%d, file: %s\n", ++ curlun->ro, curlun->nofua, (p ? p : "(error)")); ++ } ++ } ++ kfree(pathbuf); ++ ++ DBG(fsg, "transport=%s (x%02x)\n", ++ mod_data.transport_name, mod_data.transport_type); ++ DBG(fsg, "protocol=%s (x%02x)\n", ++ mod_data.protocol_name, mod_data.protocol_type); ++ DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n", ++ mod_data.vendor, mod_data.product, mod_data.release); ++ DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n", ++ mod_data.removable, mod_data.can_stall, ++ mod_data.cdrom, mod_data.buflen); ++ DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task)); ++ ++ set_bit(REGISTERED, &fsg->atomic_bitflags); ++ ++ /* Tell the thread to start working */ ++ wake_up_process(fsg->thread_task); ++ return 0; ++ ++autoconf_fail: ++ ERROR(fsg, "unable to autoconfigure all endpoints\n"); ++ rc = -ENOTSUPP; ++ ++out: ++ fsg->state = FSG_STATE_TERMINATED; // The thread is dead ++ fsg_unbind(gadget); ++ complete(&fsg->thread_notifier); ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void fsg_suspend(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ ++ DBG(fsg, "suspend\n"); ++ set_bit(SUSPENDED, &fsg->atomic_bitflags); ++} ++ ++static void fsg_resume(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ ++ DBG(fsg, "resume\n"); ++ clear_bit(SUSPENDED, &fsg->atomic_bitflags); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_gadget_driver fsg_driver = { ++ .max_speed = USB_SPEED_SUPER, ++ .function = (char *) fsg_string_product, ++ .unbind = fsg_unbind, ++ .disconnect = fsg_disconnect, ++ .setup = fsg_setup, ++ .suspend = fsg_suspend, ++ .resume = fsg_resume, ++ ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ // .release = ... ++ // .suspend = ... ++ // .resume = ... ++ }, ++}; ++ ++ ++static int __init fsg_alloc(void) ++{ ++ struct fsg_dev *fsg; ++ ++ fsg = kzalloc(sizeof *fsg + ++ fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL); ++ ++ if (!fsg) ++ return -ENOMEM; ++ spin_lock_init(&fsg->lock); ++ init_rwsem(&fsg->filesem); ++ kref_init(&fsg->ref); ++ init_completion(&fsg->thread_notifier); ++ ++ the_fsg = fsg; ++ return 0; ++} ++ ++ ++static int __init fsg_init(void) ++{ ++ int rc; ++ struct fsg_dev *fsg; ++ ++ rc = fsg_num_buffers_validate(); ++ if (rc != 0) ++ return rc; ++ ++ if ((rc = fsg_alloc()) != 0) ++ return rc; ++ fsg = the_fsg; ++ if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0) ++ kref_put(&fsg->ref, fsg_release); ++ return rc; ++} ++module_init(fsg_init); ++ ++ ++static void __exit fsg_cleanup(void) ++{ ++ struct fsg_dev *fsg = the_fsg; ++ ++ /* Unregister the driver iff the thread hasn't already done so */ ++ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags)) ++ usb_gadget_unregister_driver(&fsg_driver); ++ ++ /* Wait for the thread to finish up */ ++ wait_for_completion(&fsg->thread_notifier); ++ ++ kref_put(&fsg->ref, fsg_release); ++} ++module_exit(fsg_cleanup); +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -745,6 +745,19 @@ config USB_HWA_HCD + To compile this driver a module, choose M here: the module + will be called "hwa-hc". + ++config USB_DWCOTG ++ tristate "Synopsis DWC host support" ++ depends on USB ++ help ++ The Synopsis DWC controller is a dual-role ++ host/peripheral/OTG ("On The Go") USB controllers. ++ ++ Enable this option to support this IP in host controller mode. ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ modules built will be called dwc_otg and dwc_common_port. ++ + config USB_IMX21_HCD + tristate "i.MX21 HCD support" + depends on ARM && ARCH_MXC +--- a/drivers/usb/host/Makefile ++++ b/drivers/usb/host/Makefile +@@ -68,6 +68,8 @@ obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o + obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o + obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o + obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/ + obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o + obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o + obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/Makefile +@@ -0,0 +1,58 @@ ++# ++# Makefile for DWC_common library ++# ++ ++ifneq ($(KERNELRELEASE),) ++ ++ccflags-y += -DDWC_LINUX ++#ccflags-y += -DDEBUG ++#ccflags-y += -DDWC_DEBUG_REGS ++#ccflags-y += -DDWC_DEBUG_MEMORY ++ ++ccflags-y += -DDWC_LIBMODULE ++ccflags-y += -DDWC_CCLIB ++#ccflags-y += -DDWC_CRYPTOLIB ++ccflags-y += -DDWC_NOTIFYLIB ++ccflags-y += -DDWC_UTFLIB ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o ++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ ++ dwc_crypto.o dwc_notifier.o \ ++ dwc_common_linux.o dwc_mem.o ++ ++kernrelwd := $(subst ., ,$(KERNELRELEASE)) ++kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) ++ ++ifneq ($(kernrel3),2.6.20) ++# grayg - I only know that we use ccflags-y in 2.6.31 actually ++ccflags-y += $(CPPFLAGS) ++endif ++ ++else ++ ++#ifeq ($(KDIR),) ++#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) ++#endif ++ ++ifeq ($(ARCH),) ++$(error Must give "ARCH=" on command line or in environment. Also, if \ ++ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-") ++endif ++ ++ifeq ($(DOXYGEN),) ++DOXYGEN := doxygen ++endif ++ ++default: ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++endif ++ ++clean: ++ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/Makefile.fbsd +@@ -0,0 +1,17 @@ ++CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include ++CFLAGS += -DDWC_FREEBSD ++CFLAGS += -DDEBUG ++#CFLAGS += -DDWC_DEBUG_REGS ++#CFLAGS += -DDWC_DEBUG_MEMORY ++ ++#CFLAGS += -DDWC_LIBMODULE ++#CFLAGS += -DDWC_CCLIB ++#CFLAGS += -DDWC_CRYPTOLIB ++#CFLAGS += -DDWC_NOTIFYLIB ++#CFLAGS += -DDWC_UTFLIB ++ ++KMOD = dwc_common_port_lib ++SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \ ++ dwc_common_fbsd.c dwc_mem.c ++ ++.include +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/Makefile.linux +@@ -0,0 +1,49 @@ ++# ++# Makefile for DWC_common library ++# ++ifneq ($(KERNELRELEASE),) ++ ++ccflags-y += -DDWC_LINUX ++#ccflags-y += -DDEBUG ++#ccflags-y += -DDWC_DEBUG_REGS ++#ccflags-y += -DDWC_DEBUG_MEMORY ++ ++ccflags-y += -DDWC_LIBMODULE ++ccflags-y += -DDWC_CCLIB ++ccflags-y += -DDWC_CRYPTOLIB ++ccflags-y += -DDWC_NOTIFYLIB ++ccflags-y += -DDWC_UTFLIB ++ ++obj-m := dwc_common_port_lib.o ++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ ++ dwc_crypto.o dwc_notifier.o \ ++ dwc_common_linux.o dwc_mem.o ++ ++else ++ ++ifeq ($(KDIR),) ++$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) ++endif ++ ++ifeq ($(ARCH),) ++$(error Must give "ARCH=" on command line or in environment. Also, if \ ++ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-") ++endif ++ ++ifeq ($(DOXYGEN),) ++DOXYGEN := doxygen ++endif ++ ++default: ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++endif ++ ++clean: ++ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/changes.txt +@@ -0,0 +1,174 @@ ++ ++dwc_read_reg32() and friends now take an additional parameter, a pointer to an ++IO context struct. The IO context struct should live in an os-dependent struct ++in your driver. As an example, the dwc_usb3 driver has an os-dependent struct ++named 'os_dep' embedded in the main device struct. So there these calls look ++like this: ++ ++ dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg); ++ ++ dwc_write_reg32(&usb3_dev->os_dep.ioctx, ++ &pcd->dev_global_regs->dcfg, 0); ++ ++Note that for the existing Linux driver ports, it is not necessary to actually ++define the 'ioctx' member in the os-dependent struct. Since Linux does not ++require an IO context, its macros for dwc_read_reg32() and friends do not ++use the context pointer, so it is optimized away by the compiler. But it is ++necessary to add the pointer parameter to all of the call sites, to be ready ++for any future ports (such as FreeBSD) which do require an IO context. ++ ++ ++Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now ++take an additional parameter, a pointer to a memory context. Examples: ++ ++ addr = dwc_alloc(&usb3_dev->os_dep.memctx, size); ++ ++ dwc_free(&usb3_dev->os_dep.memctx, addr); ++ ++Again, for the Linux ports, it is not necessary to actually define the memctx ++member, but it is necessary to add the pointer parameter to all of the call ++sites. ++ ++ ++Same for dwc_dma_alloc() and dwc_dma_free(). Examples: ++ ++ virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr); ++ ++ dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr); ++ ++ ++Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples: ++ ++ mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx); ++ ++ dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex); ++ ++ ++Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples: ++ ++ lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx); ++ ++ dwc_spinlock_free(&usb3_dev->osdep.splctx, lock); ++ ++ ++Same for dwc_timer_alloc(). Example: ++ ++ timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1", ++ cb_func, cb_data); ++ ++ ++Same for dwc_waitq_alloc(). Example: ++ ++ waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx); ++ ++ ++Same for dwc_thread_run(). Example: ++ ++ thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func, ++ "dwc_usb3_thd1", data); ++ ++ ++Same for dwc_workq_alloc(). Example: ++ ++ workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1"); ++ ++ ++Same for dwc_task_alloc(). Example: ++ ++ task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1", ++ cb_func, cb_data); ++ ++ ++In addition to the context pointer additions, a few core functions have had ++other changes made to their parameters: ++ ++The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore() ++has been changed from a uint64_t to a dwc_irqflags_t. ++ ++dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the ++FreeBSD equivalent of that function requires it. ++ ++And, in addition to the context pointer, dwc_task_alloc() also adds a ++'char *name' parameter, to be consistent with dwc_thread_run() and ++dwc_workq_alloc(), and because the FreeBSD equivalent of that function ++requires a unique name. ++ ++ ++Here is a complete list of the core functions that now take a pointer to a ++context as their first parameter: ++ ++ dwc_read_reg32 ++ dwc_read_reg64 ++ dwc_write_reg32 ++ dwc_write_reg64 ++ dwc_modify_reg32 ++ dwc_modify_reg64 ++ dwc_alloc ++ dwc_alloc_atomic ++ dwc_strdup ++ dwc_free ++ dwc_dma_alloc ++ dwc_dma_free ++ dwc_mutex_alloc ++ dwc_mutex_free ++ dwc_spinlock_alloc ++ dwc_spinlock_free ++ dwc_timer_alloc ++ dwc_waitq_alloc ++ dwc_thread_run ++ dwc_workq_alloc ++ dwc_task_alloc Also adds a 'char *name' as its 2nd parameter ++ ++And here are the core functions that have other changes to their parameters: ++ ++ dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *' ++ dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t' ++ dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter ++ ++ ++ ++The changes to the core functions also require some of the other library ++functions to change: ++ ++ dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx' ++ (for memory allocation) as the 1st param and a 'void *mtxctx' ++ (for mutex allocation) as the 2nd param. ++ ++ dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(), ++ dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a ++ 'void *memctx' as the 1st param. ++ ++ dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a ++ 'void *memctx' as the 1st param. ++ ++ dwc_modpow() now takes a 'void *memctx' as the 1st param. ++ ++ dwc_alloc_notification_manager() now takes a 'void *memctx' as the ++ 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd ++ param, and also now returns an integer value that is non-zero if ++ allocation of its data structures or work queue fails. ++ ++ dwc_register_notifier() now takes a 'void *memctx' as the 1st param. ++ ++ dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first ++ param, and also now returns an integer value that is non-zero if ++ allocation of its data structures fails. ++ ++ ++ ++Other miscellaneous changes: ++ ++The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to ++DWC_DEBUG_MEMORY and DWC_DEBUG_REGS. ++ ++The following #define's have been added to allow selectively compiling library ++features: ++ ++ DWC_CCLIB ++ DWC_CRYPTOLIB ++ DWC_NOTIFYLIB ++ DWC_UTFLIB ++ ++A DWC_LIBMODULE #define has also been added. If this is not defined, then the ++module code in dwc_common_linux.c is not compiled in. This allows linking the ++library code directly into a driver module, instead of as a standalone module. +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg +@@ -0,0 +1,270 @@ ++# Doxyfile 1.4.5 ++ ++#--------------------------------------------------------------------------- ++# Project related configuration options ++#--------------------------------------------------------------------------- ++PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB" ++PROJECT_NUMBER = ++OUTPUT_DIRECTORY = doc ++CREATE_SUBDIRS = NO ++OUTPUT_LANGUAGE = English ++BRIEF_MEMBER_DESC = YES ++REPEAT_BRIEF = YES ++ABBREVIATE_BRIEF = "The $name class" \ ++ "The $name widget" \ ++ "The $name file" \ ++ is \ ++ provides \ ++ specifies \ ++ contains \ ++ represents \ ++ a \ ++ an \ ++ the ++ALWAYS_DETAILED_SEC = YES ++INLINE_INHERITED_MEMB = NO ++FULL_PATH_NAMES = NO ++STRIP_FROM_PATH = .. ++STRIP_FROM_INC_PATH = ++SHORT_NAMES = NO ++JAVADOC_AUTOBRIEF = YES ++MULTILINE_CPP_IS_BRIEF = NO ++DETAILS_AT_TOP = YES ++INHERIT_DOCS = YES ++SEPARATE_MEMBER_PAGES = NO ++TAB_SIZE = 8 ++ALIASES = ++OPTIMIZE_OUTPUT_FOR_C = YES ++OPTIMIZE_OUTPUT_JAVA = NO ++BUILTIN_STL_SUPPORT = NO ++DISTRIBUTE_GROUP_DOC = NO ++SUBGROUPING = NO ++#--------------------------------------------------------------------------- ++# Build related configuration options ++#--------------------------------------------------------------------------- ++EXTRACT_ALL = NO ++EXTRACT_PRIVATE = NO ++EXTRACT_STATIC = YES ++EXTRACT_LOCAL_CLASSES = NO ++EXTRACT_LOCAL_METHODS = NO ++HIDE_UNDOC_MEMBERS = NO ++HIDE_UNDOC_CLASSES = NO ++HIDE_FRIEND_COMPOUNDS = NO ++HIDE_IN_BODY_DOCS = NO ++INTERNAL_DOCS = NO ++CASE_SENSE_NAMES = YES ++HIDE_SCOPE_NAMES = NO ++SHOW_INCLUDE_FILES = NO ++INLINE_INFO = YES ++SORT_MEMBER_DOCS = NO ++SORT_BRIEF_DOCS = NO ++SORT_BY_SCOPE_NAME = NO ++GENERATE_TODOLIST = YES ++GENERATE_TESTLIST = YES ++GENERATE_BUGLIST = YES ++GENERATE_DEPRECATEDLIST= YES ++ENABLED_SECTIONS = ++MAX_INITIALIZER_LINES = 30 ++SHOW_USED_FILES = YES ++SHOW_DIRECTORIES = YES ++FILE_VERSION_FILTER = ++#--------------------------------------------------------------------------- ++# configuration options related to warning and progress messages ++#--------------------------------------------------------------------------- ++QUIET = YES ++WARNINGS = YES ++WARN_IF_UNDOCUMENTED = NO ++WARN_IF_DOC_ERROR = YES ++WARN_NO_PARAMDOC = YES ++WARN_FORMAT = "$file:$line: $text" ++WARN_LOGFILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the input files ++#--------------------------------------------------------------------------- ++INPUT = . ++FILE_PATTERNS = *.c \ ++ *.cc \ ++ *.cxx \ ++ *.cpp \ ++ *.c++ \ ++ *.d \ ++ *.java \ ++ *.ii \ ++ *.ixx \ ++ *.ipp \ ++ *.i++ \ ++ *.inl \ ++ *.h \ ++ *.hh \ ++ *.hxx \ ++ *.hpp \ ++ *.h++ \ ++ *.idl \ ++ *.odl \ ++ *.cs \ ++ *.php \ ++ *.php3 \ ++ *.inc \ ++ *.m \ ++ *.mm \ ++ *.dox \ ++ *.py \ ++ *.C \ ++ *.CC \ ++ *.C++ \ ++ *.II \ ++ *.I++ \ ++ *.H \ ++ *.HH \ ++ *.H++ \ ++ *.CS \ ++ *.PHP \ ++ *.PHP3 \ ++ *.M \ ++ *.MM \ ++ *.PY ++RECURSIVE = NO ++EXCLUDE = ++EXCLUDE_SYMLINKS = NO ++EXCLUDE_PATTERNS = ++EXAMPLE_PATH = ++EXAMPLE_PATTERNS = * ++EXAMPLE_RECURSIVE = NO ++IMAGE_PATH = ++INPUT_FILTER = ++FILTER_PATTERNS = ++FILTER_SOURCE_FILES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to source browsing ++#--------------------------------------------------------------------------- ++SOURCE_BROWSER = NO ++INLINE_SOURCES = NO ++STRIP_CODE_COMMENTS = YES ++REFERENCED_BY_RELATION = YES ++REFERENCES_RELATION = YES ++USE_HTAGS = NO ++VERBATIM_HEADERS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the alphabetical class index ++#--------------------------------------------------------------------------- ++ALPHABETICAL_INDEX = NO ++COLS_IN_ALPHA_INDEX = 5 ++IGNORE_PREFIX = ++#--------------------------------------------------------------------------- ++# configuration options related to the HTML output ++#--------------------------------------------------------------------------- ++GENERATE_HTML = YES ++HTML_OUTPUT = html ++HTML_FILE_EXTENSION = .html ++HTML_HEADER = ++HTML_FOOTER = ++HTML_STYLESHEET = ++HTML_ALIGN_MEMBERS = YES ++GENERATE_HTMLHELP = NO ++CHM_FILE = ++HHC_LOCATION = ++GENERATE_CHI = NO ++BINARY_TOC = NO ++TOC_EXPAND = NO ++DISABLE_INDEX = NO ++ENUM_VALUES_PER_LINE = 4 ++GENERATE_TREEVIEW = YES ++TREEVIEW_WIDTH = 250 ++#--------------------------------------------------------------------------- ++# configuration options related to the LaTeX output ++#--------------------------------------------------------------------------- ++GENERATE_LATEX = NO ++LATEX_OUTPUT = latex ++LATEX_CMD_NAME = latex ++MAKEINDEX_CMD_NAME = makeindex ++COMPACT_LATEX = NO ++PAPER_TYPE = a4wide ++EXTRA_PACKAGES = ++LATEX_HEADER = ++PDF_HYPERLINKS = NO ++USE_PDFLATEX = NO ++LATEX_BATCHMODE = NO ++LATEX_HIDE_INDICES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the RTF output ++#--------------------------------------------------------------------------- ++GENERATE_RTF = NO ++RTF_OUTPUT = rtf ++COMPACT_RTF = NO ++RTF_HYPERLINKS = NO ++RTF_STYLESHEET_FILE = ++RTF_EXTENSIONS_FILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the man page output ++#--------------------------------------------------------------------------- ++GENERATE_MAN = NO ++MAN_OUTPUT = man ++MAN_EXTENSION = .3 ++MAN_LINKS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the XML output ++#--------------------------------------------------------------------------- ++GENERATE_XML = NO ++XML_OUTPUT = xml ++XML_SCHEMA = ++XML_DTD = ++XML_PROGRAMLISTING = YES ++#--------------------------------------------------------------------------- ++# configuration options for the AutoGen Definitions output ++#--------------------------------------------------------------------------- ++GENERATE_AUTOGEN_DEF = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the Perl module output ++#--------------------------------------------------------------------------- ++GENERATE_PERLMOD = NO ++PERLMOD_LATEX = NO ++PERLMOD_PRETTY = YES ++PERLMOD_MAKEVAR_PREFIX = ++#--------------------------------------------------------------------------- ++# Configuration options related to the preprocessor ++#--------------------------------------------------------------------------- ++ENABLE_PREPROCESSING = YES ++MACRO_EXPANSION = NO ++EXPAND_ONLY_PREDEF = NO ++SEARCH_INCLUDES = YES ++INCLUDE_PATH = ++INCLUDE_FILE_PATTERNS = ++PREDEFINED = DEBUG DEBUG_MEMORY ++EXPAND_AS_DEFINED = ++SKIP_FUNCTION_MACROS = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to external references ++#--------------------------------------------------------------------------- ++TAGFILES = ++GENERATE_TAGFILE = ++ALLEXTERNALS = NO ++EXTERNAL_GROUPS = YES ++PERL_PATH = /usr/bin/perl ++#--------------------------------------------------------------------------- ++# Configuration options related to the dot tool ++#--------------------------------------------------------------------------- ++CLASS_DIAGRAMS = YES ++HIDE_UNDOC_RELATIONS = YES ++HAVE_DOT = NO ++CLASS_GRAPH = YES ++COLLABORATION_GRAPH = YES ++GROUP_GRAPHS = YES ++UML_LOOK = NO ++TEMPLATE_RELATIONS = NO ++INCLUDE_GRAPH = NO ++INCLUDED_BY_GRAPH = YES ++CALL_GRAPH = NO ++GRAPHICAL_HIERARCHY = YES ++DIRECTORY_GRAPH = YES ++DOT_IMAGE_FORMAT = png ++DOT_PATH = ++DOTFILE_DIRS = ++MAX_DOT_GRAPH_DEPTH = 1000 ++DOT_TRANSPARENT = NO ++DOT_MULTI_TARGETS = NO ++GENERATE_LEGEND = YES ++DOT_CLEANUP = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to the search engine ++#--------------------------------------------------------------------------- ++SEARCHENGINE = NO +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_cc.c +@@ -0,0 +1,532 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $ ++ * $Revision: #4 $ ++ * $Date: 2010/11/04 $ ++ * $Change: 1621692 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifdef DWC_CCLIB ++ ++#include "dwc_cc.h" ++ ++typedef struct dwc_cc ++{ ++ uint32_t uid; ++ uint8_t chid[16]; ++ uint8_t cdid[16]; ++ uint8_t ck[16]; ++ uint8_t *name; ++ uint8_t length; ++ DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry; ++} dwc_cc_t; ++ ++DWC_CIRCLEQ_HEAD(context_list, dwc_cc); ++ ++/** The main structure for CC management. */ ++struct dwc_cc_if ++{ ++ dwc_mutex_t *mutex; ++ char *filename; ++ ++ unsigned is_host:1; ++ ++ dwc_notifier_t *notifier; ++ ++ struct context_list list; ++}; ++ ++#ifdef DEBUG ++static inline void dump_bytes(char *name, uint8_t *bytes, int len) ++{ ++ int i; ++ DWC_PRINTF("%s: ", name); ++ for (i=0; ilength = length; ++ cc->name = dwc_alloc(mem_ctx, length); ++ if (!cc->name) { ++ dwc_free(mem_ctx, cc); ++ return NULL; ++ } ++ ++ DWC_MEMCPY(cc->name, name, length); ++ } ++ ++ return cc; ++} ++ ++static void free_cc(void *mem_ctx, dwc_cc_t *cc) ++{ ++ if (cc->name) { ++ dwc_free(mem_ctx, cc->name); ++ } ++ dwc_free(mem_ctx, cc); ++} ++ ++static uint32_t next_uid(dwc_cc_if_t *cc_if) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (cc->uid > uid) { ++ uid = cc->uid; ++ } ++ } ++ ++ if (uid == 0) { ++ uid = 255; ++ } ++ ++ return uid + 1; ++} ++ ++static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid) ++{ ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (cc->uid == uid) { ++ return cc; ++ } ++ } ++ return NULL; ++} ++ ++static unsigned int cc_data_size(dwc_cc_if_t *cc_if) ++{ ++ unsigned int size = 0; ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ size += (48 + 1); ++ if (cc->name) { ++ size += cc->length; ++ } ++ } ++ return size; ++} ++ ++static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (DWC_MEMCMP(cc->chid, chid, 16) == 0) { ++ uid = cc->uid; ++ break; ++ } ++ } ++ return uid; ++} ++static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) { ++ uid = cc->uid; ++ break; ++ } ++ } ++ return uid; ++} ++ ++/* Internal cc_add */ ++static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ dwc_cc_t *cc; ++ uint32_t uid; ++ ++ if (cc_if->is_host) { ++ uid = cc_match_cdid(cc_if, cdid); ++ } ++ else { ++ uid = cc_match_chid(cc_if, chid); ++ } ++ ++ if (uid) { ++ DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length); ++ cc = cc_find(cc_if, uid); ++ } ++ else { ++ cc = alloc_cc(mem_ctx, name, length); ++ cc->uid = next_uid(cc_if); ++ DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry); ++ } ++ ++ DWC_MEMCPY(&(cc->chid[0]), chid, 16); ++ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); ++ DWC_MEMCPY(&(cc->ck[0]), ck, 16); ++ ++ DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length); ++ dump_bytes("CHID", cc->chid, 16); ++ dump_bytes("CDID", cc->cdid, 16); ++ dump_bytes("CK", cc->ck, 16); ++ return cc->uid; ++} ++ ++/* Internal cc_clear */ ++static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if) ++{ ++ while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) { ++ dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list); ++ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); ++ free_cc(mem_ctx, cc); ++ } ++} ++ ++dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx, ++ dwc_notifier_t *notifier, unsigned is_host) ++{ ++ dwc_cc_if_t *cc_if = NULL; ++ ++ /* Allocate a common_cc_if structure */ ++ cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t)); ++ ++ if (!cc_if) ++ return NULL; ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++ DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex); ++#else ++ cc_if->mutex = dwc_mutex_alloc(mtx_ctx); ++#endif ++ if (!cc_if->mutex) { ++ dwc_free(mem_ctx, cc_if); ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_INIT(&cc_if->list); ++ cc_if->is_host = is_host; ++ cc_if->notifier = notifier; ++ return cc_if; ++} ++ ++void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if) ++{ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++ DWC_MUTEX_FREE(cc_if->mutex); ++#else ++ dwc_mutex_free(mtx_ctx, cc_if->mutex); ++#endif ++ cc_clear(mem_ctx, cc_if); ++ dwc_free(mem_ctx, cc_if); ++} ++ ++static void cc_changed(dwc_cc_if_t *cc_if) ++{ ++ if (cc_if->notifier) { ++ dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if); ++ } ++} ++ ++void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if) ++{ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc_clear(mem_ctx, cc_if); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ cc_changed(cc_if); ++} ++ ++int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ uint32_t uid; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ cc_changed(cc_if); ++ ++ return uid; ++} ++ ++void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ dwc_cc_t* cc; ++ ++ DWC_DEBUGC("Change connection context %d", id); ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (!cc) { ++ DWC_ERROR("Uid %d not found in cc list\n", id); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; ++ } ++ ++ if (chid) { ++ DWC_MEMCPY(&(cc->chid[0]), chid, 16); ++ } ++ if (cdid) { ++ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); ++ } ++ if (ck) { ++ DWC_MEMCPY(&(cc->ck[0]), ck, 16); ++ } ++ ++ if (name) { ++ if (cc->name) { ++ dwc_free(mem_ctx, cc->name); ++ } ++ cc->name = dwc_alloc(mem_ctx, length); ++ if (!cc->name) { ++ DWC_ERROR("Out of memory in dwc_cc_change()\n"); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; ++ } ++ cc->length = length; ++ DWC_MEMCPY(cc->name, name, length); ++ } ++ ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ cc_changed(cc_if); ++ ++ DWC_DEBUGC("Changed connection context id=%d\n", id); ++ dump_bytes("New CHID", cc->chid, 16); ++ dump_bytes("New CDID", cc->cdid, 16); ++ dump_bytes("New CK", cc->ck, 16); ++} ++ ++void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id) ++{ ++ dwc_cc_t *cc; ++ ++ DWC_DEBUGC("Removing connection context %d", id); ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (!cc) { ++ DWC_ERROR("Uid %d not found in cc list\n", id); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; ++ } ++ ++ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ free_cc(mem_ctx, cc); ++ ++ cc_changed(cc_if); ++} ++ ++uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length) ++{ ++ uint8_t *buf, *x; ++ uint8_t zero = 0; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ *length = cc_data_size(cc_if); ++ if (!(*length)) { ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return NULL; ++ } ++ ++ DWC_DEBUGC("Creating data for saving (length=%d)", *length); ++ ++ buf = dwc_alloc(mem_ctx, *length); ++ if (!buf) { ++ *length = 0; ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return NULL; ++ } ++ ++ x = buf; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ DWC_MEMCPY(x, cc->chid, 16); ++ x += 16; ++ DWC_MEMCPY(x, cc->cdid, 16); ++ x += 16; ++ DWC_MEMCPY(x, cc->ck, 16); ++ x += 16; ++ if (cc->name) { ++ DWC_MEMCPY(x, &cc->length, 1); ++ x += 1; ++ DWC_MEMCPY(x, cc->name, cc->length); ++ x += cc->length; ++ } ++ else { ++ DWC_MEMCPY(x, &zero, 1); ++ x += 1; ++ } ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return buf; ++} ++ ++void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length) ++{ ++ uint8_t name_length; ++ uint8_t *name; ++ uint8_t *chid; ++ uint8_t *cdid; ++ uint8_t *ck; ++ uint32_t i = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc_clear(mem_ctx, cc_if); ++ ++ while (i < length) { ++ chid = &data[i]; ++ i += 16; ++ cdid = &data[i]; ++ i += 16; ++ ck = &data[i]; ++ i += 16; ++ ++ name_length = data[i]; ++ i ++; ++ ++ if (name_length) { ++ name = &data[i]; ++ i += name_length; ++ } ++ else { ++ name = NULL; ++ } ++ ++ /* check to see if we haven't overflown the buffer */ ++ if (i > length) { ++ DWC_ERROR("Data format error while attempting to load CCs " ++ "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length); ++ break; ++ } ++ ++ cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length); ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ cc_changed(cc_if); ++} ++ ++uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid) ++{ ++ uint32_t uid = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_match_chid(cc_if, chid); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return uid; ++} ++uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid) ++{ ++ uint32_t uid = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_match_cdid(cc_if, cdid); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return uid; ++} ++ ++uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *ck = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ ck = cc->ck; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return ck; ++ ++} ++ ++uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ retval = cc->chid; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} ++ ++uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ retval = cc->cdid; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} ++ ++uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ *length = 0; ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ *length = cc->length; ++ retval = cc->name; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} ++ ++#endif /* DWC_CCLIB */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_cc.h +@@ -0,0 +1,224 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $ ++ * $Revision: #4 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifndef _DWC_CC_H_ ++#define _DWC_CC_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** @file ++ * ++ * This file defines the Context Context library. ++ * ++ * The main data structure is dwc_cc_if_t which is returned by either the ++ * dwc_cc_if_alloc function or returned by the module to the user via a provided ++ * function. The data structure is opaque and should only be manipulated via the ++ * functions provied in this API. ++ * ++ * It manages a list of connection contexts and operations can be performed to ++ * add, remove, query, search, and change, those contexts. Additionally, ++ * a dwc_notifier_t object can be requested from the manager so that ++ * the user can be notified whenever the context list has changed. ++ */ ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++#include "dwc_notifier.h" ++ ++ ++/* Notifications */ ++#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION" ++ ++struct dwc_cc_if; ++typedef struct dwc_cc_if dwc_cc_if_t; ++ ++ ++/** @name Connection Context Operations */ ++/** @{ */ ++ ++/** This function allocates memory for a dwc_cc_if_t structure, initializes ++ * fields to default values, and returns a pointer to the structure or NULL on ++ * error. */ ++extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx, ++ dwc_notifier_t *notifier, unsigned is_host); ++ ++/** Frees the memory for the specified CC structure allocated from ++ * dwc_cc_if_alloc(). */ ++extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if); ++ ++/** Removes all contexts from the connection context list */ ++extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if); ++ ++/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list. ++ * If a CHID already exists, the CK and name are overwritten. Statistics are ++ * not overwritten. ++ * ++ * @param cc_if The cc_if structure. ++ * @param chid A pointer to the 16-byte CHID. This value will be copied. ++ * @param ck A pointer to the 16-byte CK. This value will be copied. ++ * @param cdid A pointer to the 16-byte CDID. This value will be copied. ++ * @param name An optional host friendly name as defined in the association model ++ * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name. ++ * @param length The length othe unicode string. ++ * @return A unique identifier used to refer to this context that is valid for ++ * as long as this context is still in the list. */ ++extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, ++ uint8_t length); ++ ++/** Changes the CHID, CK, CDID, or Name values of a connection context in the ++ * list, preserving any accumulated statistics. This would typically be called ++ * if the host decideds to change the context with a SET_CONNECTION request. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL ++ * indicates no change. ++ * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL ++ * indicates no change. ++ * @param ck A pointer to the 16-byte CK. This value will be copied. NULL ++ * indicates no change. ++ * @param name Host friendly name UTF16-LE. NULL indicates no change. ++ * @param length Length of name. */ ++extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, ++ uint8_t *chid, uint8_t *cdid, uint8_t *ck, ++ uint8_t *name, uint8_t length); ++ ++/** Remove the specified connection context. ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context to remove. */ ++extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Get a binary block of data for the connection context list and attributes. ++ * This data can be used by the OS specific driver to save the connection ++ * context list into non-volatile memory. ++ * ++ * @param cc_if The cc_if structure. ++ * @param length Return the length of the data buffer. ++ * @return A pointer to the data buffer. The memory for this buffer should be ++ * freed with DWC_FREE() after use. */ ++extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, ++ unsigned int *length); ++ ++/** Restore the connection context list from the binary data that was previously ++ * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific ++ * driver to load a connection context list from non-volatile memory. ++ * ++ * @param cc_if The cc_if structure. ++ * @param data The data bytes as returned from dwc_cc_data_for_save. ++ * @param length The length of the data. */ ++extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, ++ uint8_t *data, unsigned int length); ++ ++/** Find the connection context from the specified CHID. ++ * ++ * @param cc_if The cc_if structure. ++ * @param chid A pointer to the CHID data. ++ * @return A non-zero identifier of the connection context if the CHID matches. ++ * Otherwise returns 0. */ ++extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid); ++ ++/** Find the connection context from the specified CDID. ++ * ++ * @param cc_if The cc_if structure. ++ * @param cdid A pointer to the CDID data. ++ * @return A non-zero identifier of the connection context if the CHID matches. ++ * Otherwise returns 0. */ ++extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid); ++ ++/** Retrieve the CK from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CK data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Retrieve the CHID from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CHID data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Retrieve the CDID from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CDID data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id); ++ ++extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length); ++ ++/** Checks a buffer for non-zero. ++ * @param id A pointer to a 16 byte buffer. ++ * @return true if the 16 byte value is non-zero. */ ++static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) { ++ int i; ++ for (i=0; i<16; i++) { ++ if (id[i]) return 1; ++ } ++ return 0; ++} ++ ++/** Checks a buffer for zero. ++ * @param id A pointer to a 16 byte buffer. ++ * @return true if the 16 byte value is zero. */ ++static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) { ++ return !dwc_assoc_is_not_zero_id(id); ++} ++ ++/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into ++ * buffer. */ ++static inline int dwc_print_id_string(char *buffer, uint8_t *id) { ++ char *ptr = buffer; ++ int i; ++ for (i=0; i<16; i++) { ++ ptr += DWC_SPRINTF(ptr, "%02x", id[i]); ++ if (i < 15) { ++ ptr += DWC_SPRINTF(ptr, " "); ++ } ++ } ++ return ptr - buffer; ++} ++ ++/** @} */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_CC_H_ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c +@@ -0,0 +1,1308 @@ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" ++#endif ++ ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */ ++ ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ bcopy(src, dest, size); ++ return dest; ++} ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++ ++char *DWC_STRCPY(char *to, char const *from) ++{ ++ return strcpy(to, from); ++} ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ ++ if (!new) { ++ return NULL; ++ } ++ ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++ ++int DWC_ATOI(char *str, int32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtol(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++int DWC_ATOUI(char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++ ++#ifdef DWC_UTFLIB ++/* From usbstring.c */ ++ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++#endif /* DWC_UTFLIB */ ++ ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++// return in_irq(); ++ return 0; ++} ++ ++dwc_bool_t DWC_IN_BH(void) ++{ ++// return in_softirq(); ++ return 0; ++} ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintf(format, args); ++} ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++// BUG_ON(1); ??? ++} ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++#endif ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(..); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++#endif ++ ++static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) ++{ ++ if (error) ++ return; ++ *(bus_addr_t *)arg = segs[0].ds_addr; ++} ++ ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ int error; ++ ++ error = bus_dma_tag_create( ++#if __FreeBSD_version >= 700000 ++ bus_get_dma_tag(dma->dev), /* parent */ ++#else ++ NULL, /* parent */ ++#endif ++ 4, 0, /* alignment, bounds */ ++ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ ++ BUS_SPACE_MAXADDR, /* highaddr */ ++ NULL, NULL, /* filter, filterarg */ ++ size, /* maxsize */ ++ 1, /* nsegments */ ++ size, /* maxsegsize */ ++ 0, /* flags */ ++ NULL, /* lockfunc */ ++ NULL, /* lockarg */ ++ &dma->dma_tag); ++ if (error) { ++ device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n", ++ __func__, error); ++ goto fail_0; ++ } ++ ++ error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr, ++ BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); ++ if (error) { ++ device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", ++ __func__, (uintmax_t)size, error); ++ goto fail_1; ++ } ++ ++ dma->dma_paddr = 0; ++ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size, ++ dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT); ++ if (error || dma->dma_paddr == 0) { ++ device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n", ++ __func__, error); ++ goto fail_2; ++ } ++ ++ *dma_addr = dma->dma_paddr; ++ return dma->dma_vaddr; ++ ++fail_2: ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++fail_1: ++ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); ++ bus_dma_tag_destroy(dma->dma_tag); ++fail_0: ++ dma->dma_map = NULL; ++ dma->dma_tag = NULL; ++ ++ return NULL; ++} ++ ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ ++ if (dma->dma_tag == NULL) ++ return; ++ if (dma->dma_map != NULL) { ++ bus_dmamap_sync(dma->dma_tag, dma->dma_map, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); ++ dma->dma_map = NULL; ++ } ++ ++ bus_dma_tag_destroy(dma->dma_tag); ++ dma->dma_tag = NULL; ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); ++} ++ ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); ++} ++ ++void __DWC_FREE(void *mem_ctx, void *addr) ++{ ++ free(addr, M_DEVBUF); ++} ++ ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_4(io->iot, io->ioh, ior); ++} ++ ++#if 0 ++uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_8(io->iot, io->ioh, ior); ++} ++#endif ++ ++void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, value); ++} ++ ++#if 0 ++void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, value); ++} ++#endif ++ ++void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, ++ uint32_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, ++ (bus_space_read_4(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++ ++#if 0 ++void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, ++ uint64_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, ++ (bus_space_read_8(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++#endif ++ ++ ++/* Locking */ ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ struct mtx *sl = DWC_ALLOC(sizeof(*sl)); ++ ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ return NULL; ++ } ++ ++ mtx_init(sl, "dw3spn", NULL, MTX_SPIN); ++ return (dwc_spinlock_t *)sl; ++} ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++ struct mtx *sl = (struct mtx *)lock; ++ ++ mtx_destroy(sl); ++ DWC_FREE(sl); ++} ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++ mtx_lock_spin((struct mtx *)lock); // ??? ++} ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++ mtx_unlock_spin((struct mtx *)lock); // ??? ++} ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) ++{ ++ mtx_lock_spin((struct mtx *)lock); ++} ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++ mtx_unlock_spin((struct mtx *)lock); ++} ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ struct mtx *m; ++ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex"); ++ return NULL; ++ } ++ ++ m = (struct mtx *)mutex; ++ mtx_init(m, "dw3mtx", NULL, MTX_DEF); ++ return mutex; ++} ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ mtx_destroy((struct mtx *)mutex); ++ DWC_FREE(mutex); ++} ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ mtx_lock(m); ++} ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ return mtx_trylock(m); ++} ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ mtx_unlock(m); ++} ++ ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ DELAY(usecs); ++} ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ do { ++ DELAY(1000); ++ } while (--msecs); ++} ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ pause("dw3slp", tvtohz(&tv)); ++} ++ ++uint32_t DWC_TIME(void) ++{ ++ struct timeval tv; ++ ++ microuptime(&tv); // or getmicrouptime? (less precise, but faster) ++ return tv.tv_sec * 1000 + tv.tv_usec / 1000; ++} ++ ++ ++/* Timers */ ++ ++struct dwc_timer { ++ struct callout t; ++ char *name; ++ dwc_spinlock_t *lock; ++ dwc_timer_callback_t cb; ++ void *data; ++}; ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ ++ callout_init(&t->t, 1); ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++ t->lock = DWC_SPINLOCK_ALLOC(); ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for lock"); ++ goto no_lock; ++ } ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t); ++ ++ return NULL; ++} ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data); ++} ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++} ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ struct mtx lock; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ return NULL; ++ } ++ ++ mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF); ++ wq->abort = 0; ++ ++ return wq; ++} ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ mtx_destroy(&wq->lock); ++ DWC_FREE(wq); ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) ++{ ++// intrmask_t ipl; ++ int result = 0; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++// splx(ipl); ++ result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout ++// ipl = splbio(); ++ } ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else if (wq->abort) { ++ result = -DWC_E_ABORT; ++ ++ } else { ++ result = 0; ++ } ++ ++ wq->abort = 0; ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++ return result; ++} ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) ++{ ++ struct timeval tv, tv1, tv2; ++// intrmask_t ipl; ++ int result = 0; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++// splx(ipl); ++ getmicrouptime(&tv1); ++ result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv)); ++ getmicrouptime(&tv2); ++// ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ result = -DWC_E_ABORT; ++ } else { ++ tv2.tv_usec -= tv1.tv_usec; ++ if (tv2.tv_usec < 0) { ++ tv2.tv_usec += 1000000; ++ tv2.tv_sec--; ++ } ++ ++ tv2.tv_sec -= tv1.tv_sec; ++ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000; ++ result = msecs - result; ++ if (result <= 0) ++ result = 1; ++ } ++ } else if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else { // timed out ++ result = -DWC_E_TIMEOUT; ++ } ++ ++ wq->abort = 0; ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++ return result; ++} ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wakeup(wq); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++// intrmask_t ipl; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ wq->abort = 1; ++ wakeup(wq); ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++} ++ ++ ++/* Threading */ ++ ++struct dwc_thread { ++ struct proc *proc; ++ int abort; ++}; ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) ++{ ++ int retval; ++ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread)); ++ ++ if (!thread) { ++ return NULL; ++ } ++ ++ thread->abort = 0; ++ retval = kthread_create((void (*)(void *))func, data, &thread->proc, ++ RFPROC | RFNOWAIT, 0, "%s", name); ++ if (retval) { ++ DWC_FREE(thread); ++ return NULL; ++ } ++ ++ return thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ int retval; ++ ++ thread->abort = 1; ++ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz); ++ ++ if (retval == 0) { ++ /* DWC_THREAD_EXIT() will free the thread struct */ ++ return 0; ++ } ++ ++ /* NOTE: We leak the thread struct if thread doesn't die */ ++ ++ if (retval == EWOULDBLOCK) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread) ++{ ++ return thread->abort; ++} ++ ++void DWC_THREAD_EXIT(dwc_thread_t *thread) ++{ ++ wakeup(&thread->abort); ++ DWC_FREE(thread); ++ kthread_exit(0); ++} ++ ++ ++/* tasklets ++ - Runs in interrupt context (cannot sleep) ++ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ] ++ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ] ++ */ ++struct dwc_tasklet { ++ struct task t; ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(void *data, int pending) // what to do with pending ??? ++{ ++ dwc_tasklet_t *task = (dwc_tasklet_t *)data; ++ ++ task->cb(task->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task)); ++ ++ if (task) { ++ task->cb = cb; ++ task->data = data; ++ TASK_INIT(&task->t, 0, tasklet_callback, task); ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet"); ++ } ++ ++ return task; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ taskqueue_drain(taskqueue_fast, &task->t); // ??? ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ /* Uses predefined system queue */ ++ taskqueue_enqueue_fast(taskqueue_fast, &task->t); ++} ++ ++ ++/* workqueues ++ - Runs in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ int hz; ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_ENTRY(work_container) entry; ++#endif ++ struct task task; ++} work_container_t; ++ ++#ifdef DEBUG ++DWC_CIRCLEQ_HEAD(work_container_queue, work_container); ++#endif ++ ++struct dwc_workq { ++ struct taskqueue *taskq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ ++#ifdef DEBUG ++ struct work_container_queue entries; ++#endif ++}; ++ ++static void do_work(void *data, int pending) // what to do with pending ??? ++{ ++ work_container_t *container = (work_container_t *)data; ++ dwc_workq_t *wq = container->wq; ++ dwc_irqflags_t flags; ++ ++ if (container->hz) { ++ pause("dw3wrk", container->hz); ++ } ++ ++ container->cb(container->data); ++ DWC_DEBUG("Work done: %s, container=%p", container->name, container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); ++#endif ++ if (container->name) ++ DWC_FREE(container->name); ++ DWC_FREE(container); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for workqueue"); ++ return NULL; ++ } ++ ++ wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq); ++ if (!wq->taskq) { ++ DWC_ERROR("Cannot allocate memory for taskqueue"); ++ goto no_taskq; ++ } ++ ++ wq->pending = 0; ++ ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++ if (!wq->lock) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ goto no_waitq; ++ } ++ ++ taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk"); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INIT(&wq->entries); ++#endif ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ taskqueue_free(wq->taskq); ++ no_taskq: ++ DWC_FREE(wq); ++ ++ return NULL; ++} ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++ if (wq->pending != 0) { ++ struct work_container *container; ++ ++ DWC_ERROR("Destroying work queue with pending work"); ++ ++ DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) { ++ DWC_ERROR("Work %s still pending", container->name); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++#endif ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ taskqueue_free(wq->taskq); ++ DWC_FREE(wq); ++} ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ container->hz = 0; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ ++ TASK_INIT(&container->task, 0, do_work, container); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ taskqueue_enqueue_fast(wq->taskq, &container->task); ++} ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ struct timeval tv; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ container->hz = tvtohz(&tv); ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ ++ TASK_INIT(&container->task, 0, do_work, container); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ taskqueue_enqueue_fast(wq->taskq, &container->task); ++} ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c +@@ -0,0 +1,1434 @@ ++#include ++#include ++#include ++#include ++ ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" ++#endif ++ ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the Linux kernel implementation of the DWC platform library. */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++# include ++#else ++# include ++#endif ++ ++#include ++#include ++#include ++#include ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ return memmove(dest, src, size); ++} ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++ ++char *DWC_STRCPY(char *to, char const *from) ++{ ++ return strcpy(to, from); ++} ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ ++ if (!new) { ++ return NULL; ++ } ++ ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++ ++int DWC_ATOI(const char *str, int32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = simple_strtol(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++int DWC_ATOUI(const char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = simple_strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++ ++#ifdef DWC_UTFLIB ++/* From usbstring.c */ ++ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++#endif /* DWC_UTFLIB */ ++ ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++ return in_irq(); ++} ++ ++dwc_bool_t DWC_IN_BH(void) ++{ ++ return in_softirq(); ++} ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintk(format, args); ++} ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_PRINTF(KERN_WARNING); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_PRINTF(KERN_ERR); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_PRINTF(KERN_ERR); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++ BUG_ON(1); ++} ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_PRINTF(KERN_DEBUG); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++#endif ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(..); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++#endif ++ ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++#ifdef xxCOSIM /* Only works for 32-bit cosim */ ++ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL); ++#else ++ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32); ++#endif ++ if (!buf) { ++ return NULL; ++ } ++ ++ memset(buf, 0, (size_t)size); ++ return buf; ++} ++ ++void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++ void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC); ++ if (!buf) { ++ return NULL; ++ } ++ memset(buf, 0, (size_t)size); ++ return buf; ++} ++ ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dma_free_coherent(dma_ctx, size, virt_addr, dma_addr); ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) ++{ ++ return kzalloc(size, GFP_KERNEL); ++} ++ ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) ++{ ++ return kzalloc(size, GFP_ATOMIC); ++} ++ ++void __DWC_FREE(void *mem_ctx, void *addr) ++{ ++ kfree(addr); ++} ++ ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(uint32_t volatile *reg) ++{ ++ return readl(reg); ++} ++ ++#if 0 ++uint64_t DWC_READ_REG64(uint64_t volatile *reg) ++{ ++} ++#endif ++ ++void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value) ++{ ++ writel(value, reg); ++} ++ ++#if 0 ++void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value) ++{ ++} ++#endif ++ ++void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask) ++{ ++ writel((readl(reg) & ~clear_mask) | set_mask, reg); ++} ++ ++#if 0 ++void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask) ++{ ++} ++#endif ++ ++ ++/* Locking */ ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ spinlock_t *sl = (spinlock_t *)1; ++ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ sl = DWC_ALLOC(sizeof(*sl)); ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock\n"); ++ return NULL; ++ } ++ ++ spin_lock_init(sl); ++#endif ++ return (dwc_spinlock_t *)sl; ++} ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ DWC_FREE(lock); ++#endif ++} ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_lock((spinlock_t *)lock); ++#endif ++} ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_unlock((spinlock_t *)lock); ++#endif ++} ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) ++{ ++ dwc_irqflags_t f; ++ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_lock_irqsave((spinlock_t *)lock, f); ++#else ++ local_irq_save(f); ++#endif ++ *flags = f; ++} ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_unlock_irqrestore((spinlock_t *)lock, flags); ++#else ++ local_irq_restore(flags); ++#endif ++} ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ struct mutex *m; ++ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex\n"); ++ return NULL; ++ } ++ ++ m = (struct mutex *)mutex; ++ mutex_init(m); ++ return mutex; ++} ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ mutex_destroy((struct mutex *)mutex); ++ DWC_FREE(mutex); ++} ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ mutex_lock(m); ++} ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ return mutex_trylock(m); ++} ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ mutex_unlock(m); ++} ++ ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ udelay(usecs); ++} ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ mdelay(msecs); ++} ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ msleep(msecs); ++} ++ ++uint32_t DWC_TIME(void) ++{ ++ return jiffies_to_msecs(jiffies); ++} ++ ++ ++/* Timers */ ++ ++struct dwc_timer { ++ struct timer_list *t; ++ char *name; ++ dwc_timer_callback_t cb; ++ void *data; ++ uint8_t scheduled; ++ dwc_spinlock_t *lock; ++}; ++ ++static void timer_callback(unsigned long data) ++{ ++ dwc_timer_t *timer = (dwc_timer_t *)data; ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ timer->scheduled = 0; ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); ++ DWC_DEBUGC("Timer %s callback", timer->name); ++ timer->cb(timer->data); ++} ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ ++ t->t = DWC_ALLOC(sizeof(*t->t)); ++ if (!t->t) { ++ DWC_ERROR("Cannot allocate memory for timer->t"); ++ goto no_timer; ++ } ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock); ++#else ++ t->lock = DWC_SPINLOCK_ALLOC(); ++#endif ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for lock"); ++ goto no_lock; ++ } ++ ++ t->scheduled = 0; ++ t->t->base = &boot_tvec_bases; ++ t->t->expires = jiffies; ++ setup_timer(t->t, timer_callback, (unsigned long)t); ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t->t); ++ no_timer: ++ DWC_FREE(t); ++ return NULL; ++} ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ ++ if (timer->scheduled) { ++ del_timer(timer->t); ++ timer->scheduled = 0; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->t); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ ++ if (!timer->scheduled) { ++ timer->scheduled = 1; ++ DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time); ++ timer->t->expires = jiffies + msecs_to_jiffies(time); ++ add_timer(timer->t); ++ } else { ++ DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time); ++ mod_timer(timer->t, jiffies + msecs_to_jiffies(time)); ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); ++} ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ del_timer(timer->t); ++} ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ wait_queue_head_t queue; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue\n"); ++ return NULL; ++ } ++ ++ init_waitqueue_head(&wq->queue); ++ wq->abort = 0; ++ return wq; ++} ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ DWC_FREE(wq); ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) ++{ ++ int result = wait_event_interruptible(wq->queue, ++ cond(data) || wq->abort); ++ if (result == -ERESTARTSYS) { ++ wq->abort = 0; ++ return -DWC_E_RESTART; ++ } ++ ++ if (wq->abort == 1) { ++ wq->abort = 0; ++ return -DWC_E_ABORT; ++ } ++ ++ wq->abort = 0; ++ ++ if (result == 0) { ++ return 0; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) ++{ ++ int32_t tmsecs; ++ int result = wait_event_interruptible_timeout(wq->queue, ++ cond(data) || wq->abort, ++ msecs_to_jiffies(msecs)); ++ if (result == -ERESTARTSYS) { ++ wq->abort = 0; ++ return -DWC_E_RESTART; ++ } ++ ++ if (wq->abort == 1) { ++ wq->abort = 0; ++ return -DWC_E_ABORT; ++ } ++ ++ wq->abort = 0; ++ ++ if (result > 0) { ++ tmsecs = jiffies_to_msecs(result); ++ if (!tmsecs) { ++ return 1; ++ } ++ ++ return tmsecs; ++ } ++ ++ if (result == 0) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wq->abort = 0; ++ wake_up_interruptible(&wq->queue); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++ wq->abort = 1; ++ wake_up_interruptible(&wq->queue); ++} ++ ++ ++/* Threading */ ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) ++{ ++ struct task_struct *thread = kthread_run(func, data, name); ++ ++ if (thread == ERR_PTR(-ENOMEM)) { ++ return NULL; ++ } ++ ++ return (dwc_thread_t *)thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ return kthread_stop((struct task_struct *)thread); ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(void) ++{ ++ return kthread_should_stop(); ++} ++ ++ ++/* tasklets ++ - run in interrupt context (cannot sleep) ++ - each tasklet runs on a single CPU ++ - different tasklets can be running simultaneously on different CPUs ++ */ ++struct dwc_tasklet { ++ struct tasklet_struct t; ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(unsigned long data) ++{ ++ dwc_tasklet_t *t = (dwc_tasklet_t *)data; ++ t->cb(t->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (t) { ++ t->cb = cb; ++ t->data = data; ++ tasklet_init(&t->t, tasklet_callback, (unsigned long)t); ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet\n"); ++ } ++ ++ return t; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_schedule(&task->t); ++} ++ ++void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_hi_schedule(&task->t); ++} ++ ++ ++/* workqueues ++ - run in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_ENTRY(work_container) entry; ++#endif ++ struct delayed_work work; ++} work_container_t; ++ ++#ifdef DEBUG ++DWC_CIRCLEQ_HEAD(work_container_queue, work_container); ++#endif ++ ++struct dwc_workq { ++ struct workqueue_struct *wq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ ++#ifdef DEBUG ++ struct work_container_queue entries; ++#endif ++}; ++ ++static void do_work(struct work_struct *work) ++{ ++ dwc_irqflags_t flags; ++ struct delayed_work *dw = container_of(work, struct delayed_work, work); ++ work_container_t *container = container_of(dw, struct work_container, work); ++ dwc_workq_t *wq = container->wq; ++ ++ container->cb(container->data); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); ++#endif ++ DWC_DEBUGC("Work done: %s, container=%p", container->name, container); ++ if (container->name) { ++ DWC_FREE(container->name); ++ } ++ DWC_FREE(container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ return NULL; ++ } ++ ++ wq->wq = create_singlethread_workqueue(name); ++ if (!wq->wq) { ++ goto no_wq; ++ } ++ ++ wq->pending = 0; ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock); ++#else ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++#endif ++ if (!wq->lock) { ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ goto no_waitq; ++ } ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INIT(&wq->entries); ++#endif ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ destroy_workqueue(wq->wq); ++ no_wq: ++ DWC_FREE(wq); ++ ++ return NULL; ++} ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ if (wq->pending != 0) { ++ struct work_container *wc; ++ DWC_ERROR("Destroying work queue with pending work"); ++ DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) { ++ DWC_ERROR("Work %s still pending", wc->name); ++ } ++ } ++#endif ++ destroy_workqueue(wq->wq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_FREE(wq); ++} ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container\n"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name\n"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container); ++ INIT_WORK(&container->work.work, do_work); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ queue_work(wq->wq, &container->work.work); ++} ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container\n"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name\n"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container); ++ INIT_DELAYED_WORK(&container->work, do_work); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time)); ++} ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} ++ ++ ++#ifdef DWC_LIBMODULE ++ ++#ifdef DWC_CCLIB ++/* CC */ ++EXPORT_SYMBOL(dwc_cc_if_alloc); ++EXPORT_SYMBOL(dwc_cc_if_free); ++EXPORT_SYMBOL(dwc_cc_clear); ++EXPORT_SYMBOL(dwc_cc_add); ++EXPORT_SYMBOL(dwc_cc_remove); ++EXPORT_SYMBOL(dwc_cc_change); ++EXPORT_SYMBOL(dwc_cc_data_for_save); ++EXPORT_SYMBOL(dwc_cc_restore_from_data); ++EXPORT_SYMBOL(dwc_cc_match_chid); ++EXPORT_SYMBOL(dwc_cc_match_cdid); ++EXPORT_SYMBOL(dwc_cc_ck); ++EXPORT_SYMBOL(dwc_cc_chid); ++EXPORT_SYMBOL(dwc_cc_cdid); ++EXPORT_SYMBOL(dwc_cc_name); ++#endif /* DWC_CCLIB */ ++ ++#ifdef DWC_CRYPTOLIB ++# ifndef CONFIG_MACH_IPMATE ++/* Modpow */ ++EXPORT_SYMBOL(dwc_modpow); ++ ++/* DH */ ++EXPORT_SYMBOL(dwc_dh_modpow); ++EXPORT_SYMBOL(dwc_dh_derive_keys); ++EXPORT_SYMBOL(dwc_dh_pk); ++# endif /* CONFIG_MACH_IPMATE */ ++ ++/* Crypto */ ++EXPORT_SYMBOL(dwc_wusb_aes_encrypt); ++EXPORT_SYMBOL(dwc_wusb_cmf); ++EXPORT_SYMBOL(dwc_wusb_prf); ++EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce); ++EXPORT_SYMBOL(dwc_wusb_gen_nonce); ++EXPORT_SYMBOL(dwc_wusb_gen_key); ++EXPORT_SYMBOL(dwc_wusb_gen_mic); ++#endif /* DWC_CRYPTOLIB */ ++ ++/* Notification */ ++#ifdef DWC_NOTIFYLIB ++EXPORT_SYMBOL(dwc_alloc_notification_manager); ++EXPORT_SYMBOL(dwc_free_notification_manager); ++EXPORT_SYMBOL(dwc_register_notifier); ++EXPORT_SYMBOL(dwc_unregister_notifier); ++EXPORT_SYMBOL(dwc_add_observer); ++EXPORT_SYMBOL(dwc_remove_observer); ++EXPORT_SYMBOL(dwc_notify); ++#endif ++ ++/* Memory Debugging Routines */ ++#ifdef DWC_DEBUG_MEMORY ++EXPORT_SYMBOL(dwc_alloc_debug); ++EXPORT_SYMBOL(dwc_alloc_atomic_debug); ++EXPORT_SYMBOL(dwc_free_debug); ++EXPORT_SYMBOL(dwc_dma_alloc_debug); ++EXPORT_SYMBOL(dwc_dma_free_debug); ++#endif ++ ++EXPORT_SYMBOL(DWC_MEMSET); ++EXPORT_SYMBOL(DWC_MEMCPY); ++EXPORT_SYMBOL(DWC_MEMMOVE); ++EXPORT_SYMBOL(DWC_MEMCMP); ++EXPORT_SYMBOL(DWC_STRNCMP); ++EXPORT_SYMBOL(DWC_STRCMP); ++EXPORT_SYMBOL(DWC_STRLEN); ++EXPORT_SYMBOL(DWC_STRCPY); ++EXPORT_SYMBOL(DWC_STRDUP); ++EXPORT_SYMBOL(DWC_ATOI); ++EXPORT_SYMBOL(DWC_ATOUI); ++ ++#ifdef DWC_UTFLIB ++EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE); ++#endif /* DWC_UTFLIB */ ++ ++EXPORT_SYMBOL(DWC_IN_IRQ); ++EXPORT_SYMBOL(DWC_IN_BH); ++EXPORT_SYMBOL(DWC_VPRINTF); ++EXPORT_SYMBOL(DWC_VSNPRINTF); ++EXPORT_SYMBOL(DWC_PRINTF); ++EXPORT_SYMBOL(DWC_SPRINTF); ++EXPORT_SYMBOL(DWC_SNPRINTF); ++EXPORT_SYMBOL(__DWC_WARN); ++EXPORT_SYMBOL(__DWC_ERROR); ++EXPORT_SYMBOL(DWC_EXCEPTION); ++ ++#ifdef DEBUG ++EXPORT_SYMBOL(__DWC_DEBUG); ++#endif ++ ++EXPORT_SYMBOL(__DWC_DMA_ALLOC); ++EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC); ++EXPORT_SYMBOL(__DWC_DMA_FREE); ++EXPORT_SYMBOL(__DWC_ALLOC); ++EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC); ++EXPORT_SYMBOL(__DWC_FREE); ++ ++#ifdef DWC_CRYPTOLIB ++EXPORT_SYMBOL(DWC_RANDOM_BYTES); ++EXPORT_SYMBOL(DWC_AES_CBC); ++EXPORT_SYMBOL(DWC_SHA256); ++EXPORT_SYMBOL(DWC_HMAC_SHA256); ++#endif ++ ++EXPORT_SYMBOL(DWC_CPU_TO_LE32); ++EXPORT_SYMBOL(DWC_CPU_TO_BE32); ++EXPORT_SYMBOL(DWC_LE32_TO_CPU); ++EXPORT_SYMBOL(DWC_BE32_TO_CPU); ++EXPORT_SYMBOL(DWC_CPU_TO_LE16); ++EXPORT_SYMBOL(DWC_CPU_TO_BE16); ++EXPORT_SYMBOL(DWC_LE16_TO_CPU); ++EXPORT_SYMBOL(DWC_BE16_TO_CPU); ++EXPORT_SYMBOL(DWC_READ_REG32); ++EXPORT_SYMBOL(DWC_WRITE_REG32); ++EXPORT_SYMBOL(DWC_MODIFY_REG32); ++ ++#if 0 ++EXPORT_SYMBOL(DWC_READ_REG64); ++EXPORT_SYMBOL(DWC_WRITE_REG64); ++EXPORT_SYMBOL(DWC_MODIFY_REG64); ++#endif ++ ++EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC); ++EXPORT_SYMBOL(DWC_SPINLOCK_FREE); ++EXPORT_SYMBOL(DWC_SPINLOCK); ++EXPORT_SYMBOL(DWC_SPINUNLOCK); ++EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE); ++EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE); ++EXPORT_SYMBOL(DWC_MUTEX_ALLOC); ++ ++#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES)) ++EXPORT_SYMBOL(DWC_MUTEX_FREE); ++#endif ++ ++EXPORT_SYMBOL(DWC_MUTEX_LOCK); ++EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK); ++EXPORT_SYMBOL(DWC_MUTEX_UNLOCK); ++EXPORT_SYMBOL(DWC_UDELAY); ++EXPORT_SYMBOL(DWC_MDELAY); ++EXPORT_SYMBOL(DWC_MSLEEP); ++EXPORT_SYMBOL(DWC_TIME); ++EXPORT_SYMBOL(DWC_TIMER_ALLOC); ++EXPORT_SYMBOL(DWC_TIMER_FREE); ++EXPORT_SYMBOL(DWC_TIMER_SCHEDULE); ++EXPORT_SYMBOL(DWC_TIMER_CANCEL); ++EXPORT_SYMBOL(DWC_WAITQ_ALLOC); ++EXPORT_SYMBOL(DWC_WAITQ_FREE); ++EXPORT_SYMBOL(DWC_WAITQ_WAIT); ++EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT); ++EXPORT_SYMBOL(DWC_WAITQ_TRIGGER); ++EXPORT_SYMBOL(DWC_WAITQ_ABORT); ++EXPORT_SYMBOL(DWC_THREAD_RUN); ++EXPORT_SYMBOL(DWC_THREAD_STOP); ++EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP); ++EXPORT_SYMBOL(DWC_TASK_ALLOC); ++EXPORT_SYMBOL(DWC_TASK_FREE); ++EXPORT_SYMBOL(DWC_TASK_SCHEDULE); ++EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE); ++EXPORT_SYMBOL(DWC_WORKQ_ALLOC); ++EXPORT_SYMBOL(DWC_WORKQ_FREE); ++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE); ++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED); ++EXPORT_SYMBOL(DWC_WORKQ_PENDING); ++ ++static int dwc_common_port_init_module(void) ++{ ++ int result = 0; ++ ++ printk(KERN_DEBUG "Module dwc_common_port init\n" ); ++ ++#ifdef DWC_DEBUG_MEMORY ++ result = dwc_memory_debug_start(NULL); ++ if (result) { ++ printk(KERN_ERR ++ "dwc_memory_debug_start() failed with error %d\n", ++ result); ++ return result; ++ } ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++ result = dwc_alloc_notification_manager(NULL, NULL); ++ if (result) { ++ printk(KERN_ERR ++ "dwc_alloc_notification_manager() failed with error %d\n", ++ result); ++ return result; ++ } ++#endif ++ return result; ++} ++ ++static void dwc_common_port_exit_module(void) ++{ ++ printk(KERN_DEBUG "Module dwc_common_port exit\n" ); ++ ++#ifdef DWC_NOTIFYLIB ++ dwc_free_notification_manager(); ++#endif ++ ++#ifdef DWC_DEBUG_MEMORY ++ dwc_memory_debug_stop(); ++#endif ++} ++ ++module_init(dwc_common_port_init_module); ++module_exit(dwc_common_port_exit_module); ++ ++MODULE_DESCRIPTION("DWC Common Library - Portable version"); ++MODULE_AUTHOR("Synopsys Inc."); ++MODULE_LICENSE ("GPL"); ++ ++#endif /* DWC_LIBMODULE */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c +@@ -0,0 +1,1275 @@ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" ++#endif ++ ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */ ++ ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ bcopy(src, dest, size); ++ return dest; ++} ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++ ++char *DWC_STRCPY(char *to, char const *from) ++{ ++ return strcpy(to, from); ++} ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ ++ if (!new) { ++ return NULL; ++ } ++ ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++ ++int DWC_ATOI(char *str, int32_t *value) ++{ ++ char *end = NULL; ++ ++ /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul' ++ * should be equivalent on 2's complement machines ++ */ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++int DWC_ATOUI(char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++ ++#ifdef DWC_UTFLIB ++/* From usbstring.c */ ++ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++#endif /* DWC_UTFLIB */ ++ ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++// return in_irq(); ++ return 0; ++} ++ ++dwc_bool_t DWC_IN_BH(void) ++{ ++// return in_softirq(); ++ return 0; ++} ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintf(format, args); ++} ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++// BUG_ON(1); ??? ++} ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++#endif ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(..); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++#endif ++ ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ int error; ++ ++ error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs, ++ sizeof(dma->segs) / sizeof(dma->segs[0]), ++ &dma->nsegs, BUS_DMA_NOWAIT); ++ if (error) { ++ printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__, ++ (uintmax_t)size, error); ++ goto fail_0; ++ } ++ ++ error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size, ++ (caddr_t *)&dma->dma_vaddr, ++ BUS_DMA_NOWAIT | BUS_DMA_COHERENT); ++ if (error) { ++ printf("%s: bus_dmamem_map failed: %d\n", __func__, error); ++ goto fail_1; ++ } ++ ++ error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0, ++ BUS_DMA_NOWAIT, &dma->dma_map); ++ if (error) { ++ printf("%s: bus_dmamap_create failed: %d\n", __func__, error); ++ goto fail_2; ++ } ++ ++ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, ++ size, NULL, BUS_DMA_NOWAIT); ++ if (error) { ++ printf("%s: bus_dmamap_load failed: %d\n", __func__, error); ++ goto fail_3; ++ } ++ ++ dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr; ++ *dma_addr = dma->dma_paddr; ++ return dma->dma_vaddr; ++ ++fail_3: ++ bus_dmamap_destroy(dma->dma_tag, dma->dma_map); ++fail_2: ++ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); ++fail_1: ++ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs); ++fail_0: ++ dma->dma_map = NULL; ++ dma->dma_vaddr = NULL; ++ dma->nsegs = 0; ++ ++ return NULL; ++} ++ ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ ++ if (dma->dma_map != NULL) { ++ bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++ bus_dmamap_destroy(dma->dma_tag, dma->dma_map); ++ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); ++ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs); ++ dma->dma_paddr = 0; ++ dma->dma_map = NULL; ++ dma->dma_vaddr = NULL; ++ dma->nsegs = 0; ++ } ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); ++} ++ ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); ++} ++ ++void __DWC_FREE(void *mem_ctx, void *addr) ++{ ++ free(addr, M_DEVBUF); ++} ++ ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_4(io->iot, io->ioh, ior); ++} ++ ++#if 0 ++uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_8(io->iot, io->ioh, ior); ++} ++#endif ++ ++void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, value); ++} ++ ++#if 0 ++void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, value); ++} ++#endif ++ ++void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, ++ uint32_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, ++ (bus_space_read_4(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++ ++#if 0 ++void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, ++ uint64_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, ++ (bus_space_read_8(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++#endif ++ ++ ++/* Locking */ ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ struct simplelock *sl = DWC_ALLOC(sizeof(*sl)); ++ ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ return NULL; ++ } ++ ++ simple_lock_init(sl); ++ return (dwc_spinlock_t *)sl; ++} ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++ struct simplelock *sl = (struct simplelock *)lock; ++ ++ DWC_FREE(sl); ++} ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++ simple_lock((struct simplelock *)lock); ++} ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++ simple_unlock((struct simplelock *)lock); ++} ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) ++{ ++ simple_lock((struct simplelock *)lock); ++ *flags = splbio(); ++} ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++ splx(flags); ++ simple_unlock((struct simplelock *)lock); ++} ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex"); ++ return NULL; ++ } ++ ++ lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0); ++ return mutex; ++} ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ DWC_FREE(mutex); ++} ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL); ++} ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ int status; ++ ++ status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL); ++ return status == 0; ++} ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ lockmgr((struct lock *)mutex, LK_RELEASE, NULL); ++} ++ ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ DELAY(usecs); ++} ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ do { ++ DELAY(1000); ++ } while (--msecs); ++} ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ tsleep(&tv, 0, "dw3slp", tvtohz(&tv)); ++} ++ ++uint32_t DWC_TIME(void) ++{ ++ struct timeval tv; ++ ++ microuptime(&tv); // or getmicrouptime? (less precise, but faster) ++ return tv.tv_sec * 1000 + tv.tv_usec / 1000; ++} ++ ++ ++/* Timers */ ++ ++struct dwc_timer { ++ struct callout t; ++ char *name; ++ dwc_spinlock_t *lock; ++ dwc_timer_callback_t cb; ++ void *data; ++}; ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ ++ callout_init(&t->t); ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++ t->lock = DWC_SPINLOCK_ALLOC(); ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for timer->lock"); ++ goto no_lock; ++ } ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t); ++ ++ return NULL; ++} ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data); ++} ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++} ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ struct simplelock lock; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ return NULL; ++ } ++ ++ simple_lock_init(&wq->lock); ++ wq->abort = 0; ++ ++ return wq; ++} ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ DWC_FREE(wq); ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) ++{ ++ int ipl; ++ int result = 0; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++ splx(ipl); ++ result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout ++ ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ wq->abort = 0; ++ result = -DWC_E_ABORT; ++ } else { ++ result = 0; ++ } ++ ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ } else { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ } else { // signaled - must be EINTR ++ result = -DWC_E_ABORT; ++ } ++ } ++ ++ return result; ++} ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) ++{ ++ struct timeval tv, tv1, tv2; ++ int ipl; ++ int result = 0; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++ splx(ipl); ++ getmicrouptime(&tv1); ++ result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock); ++ getmicrouptime(&tv2); ++ ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ result = -DWC_E_ABORT; ++ } else { ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ tv2.tv_usec -= tv1.tv_usec; ++ if (tv2.tv_usec < 0) { ++ tv2.tv_usec += 1000000; ++ tv2.tv_sec--; ++ } ++ ++ tv2.tv_sec -= tv1.tv_sec; ++ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000; ++ result = msecs - result; ++ if (result <= 0) ++ result = 1; ++ } ++ } else { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else { // timed out ++ result = -DWC_E_TIMEOUT; ++ } ++ } ++ ++ return result; ++} ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wakeup(wq); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++ int ipl; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ wq->abort = 1; ++ wakeup(wq); ++ splx(ipl); ++ simple_unlock(&wq->lock); ++} ++ ++ ++/* Threading */ ++ ++struct dwc_thread { ++ struct proc *proc; ++ int abort; ++}; ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) ++{ ++ int retval; ++ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread)); ++ ++ if (!thread) { ++ return NULL; ++ } ++ ++ thread->abort = 0; ++ retval = kthread_create1((void (*)(void *))func, data, &thread->proc, ++ "%s", name); ++ if (retval) { ++ DWC_FREE(thread); ++ return NULL; ++ } ++ ++ return thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ int retval; ++ ++ thread->abort = 1; ++ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz); ++ ++ if (retval == 0) { ++ /* DWC_THREAD_EXIT() will free the thread struct */ ++ return 0; ++ } ++ ++ /* NOTE: We leak the thread struct if thread doesn't die */ ++ ++ if (retval == EWOULDBLOCK) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread) ++{ ++ return thread->abort; ++} ++ ++void DWC_THREAD_EXIT(dwc_thread_t *thread) ++{ ++ wakeup(&thread->abort); ++ DWC_FREE(thread); ++ kthread_exit(0); ++} ++ ++/* tasklets ++ - Runs in interrupt context (cannot sleep) ++ - Each tasklet runs on a single CPU ++ - Different tasklets can be running simultaneously on different CPUs ++ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom- ++ halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ] ++ */ ++struct dwc_tasklet { ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(void *data) ++{ ++ dwc_tasklet_t *task = (dwc_tasklet_t *)data; ++ ++ task->cb(task->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task)); ++ ++ if (task) { ++ task->cb = cb; ++ task->data = data; ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet"); ++ } ++ ++ return task; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_callback(task); ++} ++ ++ ++/* workqueues ++ - Runs in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ int hz; ++ struct work task; ++} work_container_t; ++ ++struct dwc_workq { ++ struct workqueue *taskq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ struct work_container *container; ++}; ++ ++static void do_work(struct work *task, void *data) ++{ ++ dwc_workq_t *wq = (dwc_workq_t *)data; ++ work_container_t *container = wq->container; ++ dwc_irqflags_t flags; ++ ++ if (container->hz) { ++ tsleep(container, 0, "dw3wrk", container->hz); ++ } ++ ++ container->cb(container->data); ++ DWC_DEBUG("Work done: %s, container=%p", container->name, container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ if (container->name) ++ DWC_FREE(container->name); ++ DWC_FREE(container); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ int result; ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for workqueue"); ++ return NULL; ++ } ++ ++ result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/, ++ IPL_BIO, 0); ++ if (result) { ++ DWC_ERROR("Cannot create workqueue"); ++ goto no_taskq; ++ } ++ ++ wq->pending = 0; ++ ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++ if (!wq->lock) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ goto no_waitq; ++ } ++ ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ workqueue_destroy(wq->taskq); ++ no_taskq: ++ DWC_FREE(wq); ++ ++ return NULL; ++} ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++ if (wq->pending != 0) { ++ struct work_container *container = wq->container; ++ ++ DWC_ERROR("Destroying work queue with pending work"); ++ ++ if (container && container->name) { ++ DWC_ERROR("Work %s still pending", container->name); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++#endif ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ workqueue_destroy(wq->taskq); ++ DWC_FREE(wq); ++} ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ container->hz = 0; ++ wq->container = container; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ workqueue_enqueue(wq->taskq, &container->task); ++} ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ struct timeval tv; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ container->hz = tvtohz(&tv); ++ wq->container = container; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ workqueue_enqueue(wq->taskq, &container->task); ++} ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_crypto.c +@@ -0,0 +1,308 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $ ++ * $Revision: #5 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++ ++/** @file ++ * This file contains the WUSB cryptographic routines. ++ */ ++ ++#ifdef DWC_CRYPTOLIB ++ ++#include "dwc_crypto.h" ++#include "usb.h" ++ ++#ifdef DEBUG ++static inline void dump_bytes(char *name, uint8_t *bytes, int len) ++{ ++ int i; ++ DWC_PRINTF("%s: ", name); ++ for (i=0; idst == src, then the bytes will be encrypted ++ * in-place. ++ * ++ * @return 0 on success, negative error code on error. ++ */ ++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst) ++{ ++ u8 block_t[16]; ++ DWC_MEMSET(block_t, 0, 16); ++ ++ return DWC_AES_CBC(src, 16, key, 16, block_t, dst); ++} ++ ++/** ++ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. ++ * This function takes a data string and returns the encrypted CBC ++ * Counter-mode MIC. ++ * ++ * @param key The 128-bit symmetric key. ++ * @param nonce The CCM nonce. ++ * @param label The unique 14-byte ASCII text label. ++ * @param bytes The byte array to be encrypted. ++ * @param len Length of the byte array. ++ * @param result Byte array to receive the 8-byte encrypted MIC. ++ */ ++void dwc_wusb_cmf(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ u8 block_m[16]; ++ u8 block_x[16]; ++ u8 block_t[8]; ++ int idx, blkNum; ++ u16 la = (u16)(len + 14); ++ ++ /* Set the AES-128 key */ ++ //dwc_aes_setkey(tfm, key, 16); ++ ++ /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */ ++ block_m[0] = 0x59; ++ for (idx = 0; idx < 13; idx++) ++ block_m[idx + 1] = nonce[idx]; ++ block_m[14] = 0; ++ block_m[15] = 0; ++ ++ /* Produce the CBC IV */ ++ dwc_wusb_aes_encrypt(block_m, key, block_x); ++ show_block(block_m, "CBC IV in: ", "\n", 0); ++ show_block(block_x, "CBC IV out:", "\n", 0); ++ ++ /* Fill block B1 from l(a) = Blen + 14, and A */ ++ block_x[0] ^= (u8)(la >> 8); ++ block_x[1] ^= (u8)la; ++ for (idx = 0; idx < 14; idx++) ++ block_x[idx + 2] ^= label[idx]; ++ show_block(block_x, "After xor: ", "b1\n", 16); ++ ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "b1\n", 16); ++ ++ idx = 0; ++ blkNum = 0; ++ ++ /* Fill remaining blocks with B */ ++ while (len-- > 0) { ++ block_x[idx] ^= *bytes++; ++ if (++idx >= 16) { ++ idx = 0; ++ show_block(block_x, "After xor: ", "\n", blkNum); ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "\n", blkNum); ++ blkNum++; ++ } ++ } ++ ++ /* Handle partial last block */ ++ if (idx > 0) { ++ show_block(block_x, "After xor: ", "\n", blkNum); ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "\n", blkNum); ++ } ++ ++ /* Save the MIC tag */ ++ DWC_MEMCPY(block_t, block_x, 8); ++ show_block(block_t, "MIC tag : ", NULL, 8); ++ ++ /* Fill block A0 from flags = 0x01, N, and counter = 0 */ ++ block_m[0] = 0x01; ++ block_m[14] = 0; ++ block_m[15] = 0; ++ ++ /* Encrypt the counter */ ++ dwc_wusb_aes_encrypt(block_m, key, block_x); ++ show_block(block_x, "CTR[MIC] : ", NULL, 8); ++ ++ /* XOR with MIC tag */ ++ for (idx = 0; idx < 8; idx++) { ++ block_t[idx] ^= block_x[idx]; ++ } ++ ++ /* Return result to caller */ ++ DWC_MEMCPY(result, block_t, 8); ++ show_block(result, "CCM-MIC : ", NULL, 8); ++ ++} ++ ++/** ++ * The PRF function described in section 6.5 of the WUSB spec. This function ++ * concatenates MIC values returned from dwc_cmf() to create a value of ++ * the requested length. ++ * ++ * @param prf_len Length of the PRF function in bits (64, 128, or 256). ++ * @param key, nonce, label, bytes, len Same as for dwc_cmf(). ++ * @param result Byte array to receive the result. ++ */ ++void dwc_wusb_prf(int prf_len, u8 *key, ++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result) ++{ ++ int i; ++ ++ nonce[0] = 0; ++ for (i = 0; i < prf_len >> 6; i++, nonce[0]++) { ++ dwc_wusb_cmf(key, nonce, label, bytes, len, result); ++ result += 8; ++ } ++} ++ ++/** ++ * Fills in CCM Nonce per the WUSB spec. ++ * ++ * @param[in] haddr Host address. ++ * @param[in] daddr Device address. ++ * @param[in] tkid Session Key(PTK) identifier. ++ * @param[out] nonce Pointer to where the CCM Nonce output is to be written. ++ */ ++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, ++ uint8_t *nonce) ++{ ++ ++ DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr); ++ ++ DWC_MEMSET(&nonce[0], 0, 16); ++ ++ DWC_MEMCPY(&nonce[6], tkid, 3); ++ nonce[9] = daddr & 0xFF; ++ nonce[10] = (daddr >> 8) & 0xFF; ++ nonce[11] = haddr & 0xFF; ++ nonce[12] = (haddr >> 8) & 0xFF; ++ ++ dump_bytes("CCM nonce", nonce, 16); ++} ++ ++/** ++ * Generates a 16-byte cryptographic-grade random number for the Host/Device ++ * Nonce. ++ */ ++void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce) ++{ ++ uint8_t inonce[16]; ++ uint32_t temp[4]; ++ ++ /* Fill in the Nonce */ ++ DWC_MEMSET(&inonce[0], 0, sizeof(inonce)); ++ inonce[9] = addr & 0xFF; ++ inonce[10] = (addr >> 8) & 0xFF; ++ inonce[11] = inonce[9]; ++ inonce[12] = inonce[10]; ++ ++ /* Collect "randomness samples" */ ++ DWC_RANDOM_BYTES((uint8_t *)temp, 16); ++ ++ dwc_wusb_prf_128((uint8_t *)temp, nonce, ++ "Random Numbers", (uint8_t *)temp, sizeof(temp), ++ nonce); ++} ++ ++/** ++ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the ++ * WUSB spec. ++ * ++ * @param[in] ccm_nonce Pointer to CCM Nonce. ++ * @param[in] mk Master Key to derive the session from ++ * @param[in] hnonce Pointer to Host Nonce. ++ * @param[in] dnonce Pointer to Device Nonce. ++ * @param[out] kck Pointer to where the KCK output is to be written. ++ * @param[out] ptk Pointer to where the PTK output is to be written. ++ */ ++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, ++ uint8_t *dnonce, uint8_t *kck, uint8_t *ptk) ++{ ++ uint8_t idata[32]; ++ uint8_t odata[32]; ++ ++ dump_bytes("ck", mk, 16); ++ dump_bytes("hnonce", hnonce, 16); ++ dump_bytes("dnonce", dnonce, 16); ++ ++ /* The data is the HNonce and DNonce concatenated */ ++ DWC_MEMCPY(&idata[0], hnonce, 16); ++ DWC_MEMCPY(&idata[16], dnonce, 16); ++ ++ dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata); ++ ++ /* Low 16 bytes of the result is the KCK, high 16 is the PTK */ ++ DWC_MEMCPY(kck, &odata[0], 16); ++ DWC_MEMCPY(ptk, &odata[16], 16); ++ ++ dump_bytes("kck", kck, 16); ++ dump_bytes("ptk", ptk, 16); ++} ++ ++/** ++ * Generates the Message Integrity Code over the Handshake data per the ++ * WUSB spec. ++ * ++ * @param ccm_nonce Pointer to CCM Nonce. ++ * @param kck Pointer to Key Confirmation Key. ++ * @param data Pointer to Handshake data to be checked. ++ * @param mic Pointer to where the MIC output is to be written. ++ */ ++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck, ++ uint8_t *data, uint8_t *mic) ++{ ++ ++ dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC", ++ data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic); ++} ++ ++#endif /* DWC_CRYPTOLIB */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_crypto.h +@@ -0,0 +1,111 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $ ++ * $Revision: #3 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++ ++#ifndef _DWC_CRYPTO_H_ ++#define _DWC_CRYPTO_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** @file ++ * ++ * This file contains declarations for the WUSB Cryptographic routines as ++ * defined in the WUSB spec. They are only to be used internally by the DWC UWB ++ * modules. ++ */ ++ ++#include "dwc_os.h" ++ ++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst); ++ ++void dwc_wusb_cmf(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result); ++void dwc_wusb_prf(int prf_len, u8 *key, ++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result); ++ ++/** ++ * The PRF-64 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(64, key, nonce, label, bytes, len, result); ++} ++ ++/** ++ * The PRF-128 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(128, key, nonce, label, bytes, len, result); ++} ++ ++/** ++ * The PRF-256 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(256, key, nonce, label, bytes, len, result); ++} ++ ++ ++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, ++ uint8_t *nonce); ++void dwc_wusb_gen_nonce(uint16_t addr, ++ uint8_t *nonce); ++ ++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, ++ uint8_t *hnonce, uint8_t *dnonce, ++ uint8_t *kck, uint8_t *ptk); ++ ++ ++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t ++ *kck, uint8_t *data, uint8_t *mic); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_CRYPTO_H_ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_dh.c +@@ -0,0 +1,291 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $ ++ * $Revision: #3 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifdef DWC_CRYPTOLIB ++ ++#ifndef CONFIG_MACH_IPMATE ++ ++#include "dwc_dh.h" ++#include "dwc_modpow.h" ++ ++#ifdef DEBUG ++/* This function prints out a buffer in the format described in the Association ++ * Model specification. */ ++static void dh_dump(char *str, void *_num, int len) ++{ ++ uint8_t *num = _num; ++ int i; ++ DWC_PRINTF("%s\n", str); ++ for (i = 0; i < len; i ++) { ++ DWC_PRINTF("%02x", num[i]); ++ if (((i + 1) % 2) == 0) DWC_PRINTF(" "); ++ if (((i + 1) % 26) == 0) DWC_PRINTF("\n"); ++ } ++ ++ DWC_PRINTF("\n"); ++} ++#else ++#define dh_dump(_x...) do {; } while(0) ++#endif ++ ++/* Constant g value */ ++static __u32 dh_g[] = { ++ 0x02000000, ++}; ++ ++/* Constant p value */ ++static __u32 dh_p[] = { ++ 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A, ++ 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2, ++ 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4, ++ 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1, ++ 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520, ++ 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E, ++ 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895, ++ 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004, ++ 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6, ++ 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9, ++ 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA, ++ 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF, ++}; ++ ++static void dh_swap_bytes(void *_in, void *_out, uint32_t len) ++{ ++ uint8_t *in = _in; ++ uint8_t *out = _out; ++ int i; ++ for (i=0; inext = (link); \ ++ (link)->prev = (link); \ ++} while (0) ++ ++#define DWC_LIST_FIRST(link) ((link)->next) ++#define DWC_LIST_LAST(link) ((link)->prev) ++#define DWC_LIST_END(link) (link) ++#define DWC_LIST_NEXT(link) ((link)->next) ++#define DWC_LIST_PREV(link) ((link)->prev) ++#define DWC_LIST_EMPTY(link) \ ++ (DWC_LIST_FIRST(link) == DWC_LIST_END(link)) ++#define DWC_LIST_ENTRY(link, type, field) \ ++ (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field)) ++ ++#if 0 ++#define DWC_LIST_INSERT_HEAD(list, link) do { \ ++ (link)->next = (list)->next; \ ++ (link)->prev = (list); \ ++ (list)->next->prev = (link); \ ++ (list)->next = (link); \ ++} while (0) ++ ++#define DWC_LIST_INSERT_TAIL(list, link) do { \ ++ (link)->next = (list); \ ++ (link)->prev = (list)->prev; \ ++ (list)->prev->next = (link); \ ++ (list)->prev = (link); \ ++} while (0) ++#else ++#define DWC_LIST_INSERT_HEAD(list, link) do { \ ++ dwc_list_link_t *__next__ = (list)->next; \ ++ __next__->prev = (link); \ ++ (link)->next = __next__; \ ++ (link)->prev = (list); \ ++ (list)->next = (link); \ ++} while (0) ++ ++#define DWC_LIST_INSERT_TAIL(list, link) do { \ ++ dwc_list_link_t *__prev__ = (list)->prev; \ ++ (list)->prev = (link); \ ++ (link)->next = (list); \ ++ (link)->prev = __prev__; \ ++ __prev__->next = (link); \ ++} while (0) ++#endif ++ ++#if 0 ++static inline void __list_add(struct list_head *new, ++ struct list_head *prev, ++ struct list_head *next) ++{ ++ next->prev = new; ++ new->next = next; ++ new->prev = prev; ++ prev->next = new; ++} ++ ++static inline void list_add(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head, head->next); ++} ++ ++static inline void list_add_tail(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head->prev, head); ++} ++ ++static inline void __list_del(struct list_head * prev, struct list_head * next) ++{ ++ next->prev = prev; ++ prev->next = next; ++} ++ ++static inline void list_del(struct list_head *entry) ++{ ++ __list_del(entry->prev, entry->next); ++ entry->next = LIST_POISON1; ++ entry->prev = LIST_POISON2; ++} ++#endif ++ ++#define DWC_LIST_REMOVE(link) do { \ ++ (link)->next->prev = (link)->prev; \ ++ (link)->prev->next = (link)->next; \ ++} while (0) ++ ++#define DWC_LIST_REMOVE_INIT(link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INIT(link); \ ++} while (0) ++ ++#define DWC_LIST_MOVE_HEAD(list, link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INSERT_HEAD(list, link); \ ++} while (0) ++ ++#define DWC_LIST_MOVE_TAIL(list, link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INSERT_TAIL(list, link); \ ++} while (0) ++ ++#define DWC_LIST_FOREACH(var, list) \ ++ for((var) = DWC_LIST_FIRST(list); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = DWC_LIST_NEXT(var)) ++ ++#define DWC_LIST_FOREACH_SAFE(var, var2, list) \ ++ for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = (var2), (var2) = DWC_LIST_NEXT(var2)) ++ ++#define DWC_LIST_FOREACH_REVERSE(var, list) \ ++ for((var) = DWC_LIST_LAST(list); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = DWC_LIST_PREV(var)) ++ ++/* ++ * Singly-linked List definitions. ++ */ ++#define DWC_SLIST_HEAD(name, type) \ ++struct name { \ ++ struct type *slh_first; /* first element */ \ ++} ++ ++#define DWC_SLIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define DWC_SLIST_ENTRY(type) \ ++struct { \ ++ struct type *sle_next; /* next element */ \ ++} ++ ++/* ++ * Singly-linked List access methods. ++ */ ++#define DWC_SLIST_FIRST(head) ((head)->slh_first) ++#define DWC_SLIST_END(head) NULL ++#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head)) ++#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next) ++ ++#define DWC_SLIST_FOREACH(var, head, field) \ ++ for((var) = SLIST_FIRST(head); \ ++ (var) != SLIST_END(head); \ ++ (var) = SLIST_NEXT(var, field)) ++ ++#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ ++ for((varp) = &SLIST_FIRST((head)); \ ++ ((var) = *(varp)) != SLIST_END(head); \ ++ (varp) = &SLIST_NEXT((var), field)) ++ ++/* ++ * Singly-linked List functions. ++ */ ++#define DWC_SLIST_INIT(head) { \ ++ SLIST_FIRST(head) = SLIST_END(head); \ ++} ++ ++#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ ++ (elm)->field.sle_next = (slistelm)->field.sle_next; \ ++ (slistelm)->field.sle_next = (elm); \ ++} while (0) ++ ++#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.sle_next = (head)->slh_first; \ ++ (head)->slh_first = (elm); \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \ ++ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE_HEAD(head, field) do { \ ++ (head)->slh_first = (head)->slh_first->field.sle_next; \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE(head, elm, type, field) do { \ ++ if ((head)->slh_first == (elm)) { \ ++ SLIST_REMOVE_HEAD((head), field); \ ++ } \ ++ else { \ ++ struct type *curelm = (head)->slh_first; \ ++ while( curelm->field.sle_next != (elm) ) \ ++ curelm = curelm->field.sle_next; \ ++ curelm->field.sle_next = \ ++ curelm->field.sle_next->field.sle_next; \ ++ } \ ++} while (0) ++ ++/* ++ * Simple queue definitions. ++ */ ++#define DWC_SIMPLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *sqh_first; /* first element */ \ ++ struct type **sqh_last; /* addr of last next element */ \ ++} ++ ++#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).sqh_first } ++ ++#define DWC_SIMPLEQ_ENTRY(type) \ ++struct { \ ++ struct type *sqe_next; /* next element */ \ ++} ++ ++/* ++ * Simple queue access methods. ++ */ ++#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first) ++#define DWC_SIMPLEQ_END(head) NULL ++#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head)) ++#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) ++ ++#define DWC_SIMPLEQ_FOREACH(var, head, field) \ ++ for((var) = SIMPLEQ_FIRST(head); \ ++ (var) != SIMPLEQ_END(head); \ ++ (var) = SIMPLEQ_NEXT(var, field)) ++ ++/* ++ * Simple queue functions. ++ */ ++#define DWC_SIMPLEQ_INIT(head) do { \ ++ (head)->sqh_first = NULL; \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (head)->sqh_first = (elm); \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.sqe_next = NULL; \ ++ *(head)->sqh_last = (elm); \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (listelm)->field.sqe_next = (elm); \ ++} while (0) ++ ++#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \ ++ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++/* ++ * Tail queue definitions. ++ */ ++#define DWC_TAILQ_HEAD(name, type) \ ++struct name { \ ++ struct type *tqh_first; /* first element */ \ ++ struct type **tqh_last; /* addr of last next element */ \ ++} ++ ++#define DWC_TAILQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).tqh_first } ++ ++#define DWC_TAILQ_ENTRY(type) \ ++struct { \ ++ struct type *tqe_next; /* next element */ \ ++ struct type **tqe_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * tail queue access methods ++ */ ++#define DWC_TAILQ_FIRST(head) ((head)->tqh_first) ++#define DWC_TAILQ_END(head) NULL ++#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) ++#define DWC_TAILQ_LAST(head, headname) \ ++ (*(((struct headname *)((head)->tqh_last))->tqh_last)) ++/* XXX */ ++#define DWC_TAILQ_PREV(elm, headname, field) \ ++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) ++#define DWC_TAILQ_EMPTY(head) \ ++ (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head)) ++ ++#define DWC_TAILQ_FOREACH(var, head, field) \ ++ for ((var) = DWC_TAILQ_FIRST(head); \ ++ (var) != DWC_TAILQ_END(head); \ ++ (var) = DWC_TAILQ_NEXT(var, field)) ++ ++#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ ++ for ((var) = DWC_TAILQ_LAST(head, headname); \ ++ (var) != DWC_TAILQ_END(head); \ ++ (var) = DWC_TAILQ_PREV(var, headname, field)) ++ ++/* ++ * Tail queue functions. ++ */ ++#define DWC_TAILQ_INIT(head) do { \ ++ (head)->tqh_first = NULL; \ ++ (head)->tqh_last = &(head)->tqh_first; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ ++ (head)->tqh_first->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (head)->tqh_first = (elm); \ ++ (elm)->field.tqe_prev = &(head)->tqh_first; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.tqe_next = NULL; \ ++ (elm)->field.tqe_prev = (head)->tqh_last; \ ++ *(head)->tqh_last = (elm); \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (listelm)->field.tqe_next = (elm); \ ++ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ ++ (elm)->field.tqe_next = (listelm); \ ++ *(listelm)->field.tqe_prev = (elm); \ ++ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_REMOVE(head, elm, field) do { \ ++ if (((elm)->field.tqe_next) != NULL) \ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ (elm)->field.tqe_prev; \ ++ else \ ++ (head)->tqh_last = (elm)->field.tqe_prev; \ ++ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ ++ (elm2)->field.tqe_next->field.tqe_prev = \ ++ &(elm2)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm2)->field.tqe_next; \ ++ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ ++ *(elm2)->field.tqe_prev = (elm2); \ ++} while (0) ++ ++/* ++ * Circular queue definitions. ++ */ ++#define DWC_CIRCLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *cqh_first; /* first element */ \ ++ struct type *cqh_last; /* last element */ \ ++} ++ ++#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \ ++ { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) } ++ ++#define DWC_CIRCLEQ_ENTRY(type) \ ++struct { \ ++ struct type *cqe_next; /* next element */ \ ++ struct type *cqe_prev; /* previous element */ \ ++} ++ ++/* ++ * Circular queue access methods ++ */ ++#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first) ++#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last) ++#define DWC_CIRCLEQ_END(head) ((void *)(head)) ++#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) ++#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) ++#define DWC_CIRCLEQ_EMPTY(head) \ ++ (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head)) ++ ++#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL)) ++ ++#define DWC_CIRCLEQ_FOREACH(var, head, field) \ ++ for((var) = DWC_CIRCLEQ_FIRST(head); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = DWC_CIRCLEQ_NEXT(var, field)) ++ ++#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \ ++ for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field)) ++ ++#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ ++ for((var) = DWC_CIRCLEQ_LAST(head); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = DWC_CIRCLEQ_PREV(var, field)) ++ ++/* ++ * Circular queue functions. ++ */ ++#define DWC_CIRCLEQ_INIT(head) do { \ ++ (head)->cqh_first = DWC_CIRCLEQ_END(head); \ ++ (head)->cqh_last = DWC_CIRCLEQ_END(head); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \ ++ (elm)->field.cqe_next = NULL; \ ++ (elm)->field.cqe_prev = NULL; \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ ++ (elm)->field.cqe_prev = (listelm); \ ++ if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ ++ (listelm)->field.cqe_next = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm); \ ++ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ ++ if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ ++ (listelm)->field.cqe_prev = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.cqe_next = (head)->cqh_first; \ ++ (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \ ++ if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (head)->cqh_first->field.cqe_prev = (elm); \ ++ (head)->cqh_first = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \ ++ (elm)->field.cqe_prev = (head)->cqh_last; \ ++ if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (head)->cqh_last->field.cqe_next = (elm); \ ++ (head)->cqh_last = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \ ++ if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm)->field.cqe_prev; \ ++ else \ ++ (elm)->field.cqe_next->field.cqe_prev = \ ++ (elm)->field.cqe_prev; \ ++ if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm)->field.cqe_next; \ ++ else \ ++ (elm)->field.cqe_prev->field.cqe_next = \ ++ (elm)->field.cqe_next; \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \ ++ DWC_CIRCLEQ_REMOVE(head, elm, field); \ ++ DWC_CIRCLEQ_INIT_ENTRY(elm, field); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ ++ DWC_CIRCLEQ_END(head)) \ ++ (head).cqh_last = (elm2); \ ++ else \ ++ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ ++ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ ++ DWC_CIRCLEQ_END(head)) \ ++ (head).cqh_first = (elm2); \ ++ else \ ++ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ ++} while (0) ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_LIST_H_ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_mem.c +@@ -0,0 +1,245 @@ ++/* Memory Debugging */ ++#ifdef DWC_DEBUG_MEMORY ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++struct allocation { ++ void *addr; ++ void *ctx; ++ char *func; ++ int line; ++ uint32_t size; ++ int dma; ++ DWC_CIRCLEQ_ENTRY(allocation) entry; ++}; ++ ++DWC_CIRCLEQ_HEAD(allocation_queue, allocation); ++ ++struct allocation_manager { ++ void *mem_ctx; ++ struct allocation_queue allocations; ++ ++ /* statistics */ ++ int num; ++ int num_freed; ++ int num_active; ++ uint32_t total; ++ uint32_t cur; ++ uint32_t max; ++}; ++ ++static struct allocation_manager *manager = NULL; ++ ++static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr, ++ int dma) ++{ ++ struct allocation *a; ++ ++ DWC_ASSERT(manager != NULL, "manager not allocated"); ++ ++ a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a)); ++ if (!a) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1); ++ if (!a->func) { ++ __DWC_FREE(manager->mem_ctx, a); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1); ++ a->addr = addr; ++ a->ctx = ctx; ++ a->line = line; ++ a->size = size; ++ a->dma = dma; ++ DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry); ++ ++ /* Update stats */ ++ manager->num++; ++ manager->num_active++; ++ manager->total += size; ++ manager->cur += size; ++ ++ if (manager->max < manager->cur) { ++ manager->max = manager->cur; ++ } ++ ++ return 0; ++} ++ ++static struct allocation *find_allocation(void *ctx, void *addr) ++{ ++ struct allocation *a; ++ ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ if (a->ctx == ctx && a->addr == addr) { ++ return a; ++ } ++ } ++ ++ return NULL; ++} ++ ++static void free_allocation(void *ctx, void *addr, char const *func, int line) ++{ ++ struct allocation *a = find_allocation(ctx, addr); ++ ++ if (!a) { ++ DWC_ASSERT(0, ++ "Free of address %p that was never allocated or already freed %s:%d", ++ addr, func, line); ++ return; ++ } ++ ++ DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry); ++ ++ manager->num_active--; ++ manager->num_freed++; ++ manager->cur -= a->size; ++ __DWC_FREE(manager->mem_ctx, a->func); ++ __DWC_FREE(manager->mem_ctx, a); ++} ++ ++int dwc_memory_debug_start(void *mem_ctx) ++{ ++ DWC_ASSERT(manager == NULL, "Memory debugging has already started\n"); ++ ++ if (manager) { ++ return -DWC_E_BUSY; ++ } ++ ++ manager = __DWC_ALLOC(mem_ctx, sizeof(*manager)); ++ if (!manager) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_CIRCLEQ_INIT(&manager->allocations); ++ manager->mem_ctx = mem_ctx; ++ manager->num = 0; ++ manager->num_freed = 0; ++ manager->num_active = 0; ++ manager->total = 0; ++ manager->cur = 0; ++ manager->max = 0; ++ ++ return 0; ++} ++ ++void dwc_memory_debug_stop(void) ++{ ++ struct allocation *a; ++ ++ dwc_memory_debug_report(); ++ ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line); ++ free_allocation(a->ctx, a->addr, NULL, -1); ++ } ++ ++ __DWC_FREE(manager->mem_ctx, manager); ++} ++ ++void dwc_memory_debug_report(void) ++{ ++ struct allocation *a; ++ ++ DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n"); ++ DWC_PRINTF("Num Allocations = %d\n", manager->num); ++ DWC_PRINTF("Freed = %d\n", manager->num_freed); ++ DWC_PRINTF("Active = %d\n", manager->num_active); ++ DWC_PRINTF("Current Memory Used = %d\n", manager->cur); ++ DWC_PRINTF("Total Memory Used = %d\n", manager->total); ++ DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max); ++ DWC_PRINTF("Unfreed allocations:\n"); ++ ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n", ++ a->addr, a->size, a->func, a->line, a->dma); ++ } ++} ++ ++/* The replacement functions */ ++void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line) ++{ ++ void *addr = __DWC_ALLOC(mem_ctx, size); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(mem_ctx, size, func, line, addr, 0)) { ++ __DWC_FREE(mem_ctx, addr); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, ++ int line) ++{ ++ void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(mem_ctx, size, func, line, addr, 0)) { ++ __DWC_FREE(mem_ctx, addr); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line) ++{ ++ free_allocation(mem_ctx, addr, func, line); ++ __DWC_FREE(mem_ctx, addr); ++} ++ ++void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line) ++{ ++ void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(dma_ctx, size, func, line, addr, 1)) { ++ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, ++ dwc_dma_t *dma_addr, char const *func, int line) ++{ ++ void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(dma_ctx, size, func, line, addr, 1)) { ++ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr, ++ dwc_dma_t dma_addr, char const *func, int line) ++{ ++ free_allocation(dma_ctx, virt_addr, func, line); ++ __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr); ++} ++ ++#endif /* DWC_DEBUG_MEMORY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_modpow.c +@@ -0,0 +1,636 @@ ++/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows. ++ * ++ * PuTTY is copyright 1997-2007 Simon Tatham. ++ * ++ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian ++ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry, ++ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus ++ * Kuhn, and CORE SDI S.A. ++ * ++ * Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation files ++ * (the "Software"), to deal in the Software without restriction, ++ * including without limitation the rights to use, copy, modify, merge, ++ * publish, distribute, sublicense, and/or sell copies of the Software, ++ * and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifdef DWC_CRYPTOLIB ++ ++#ifndef CONFIG_MACH_IPMATE ++ ++#include "dwc_modpow.h" ++ ++#define BIGNUM_INT_MASK 0xFFFFFFFFUL ++#define BIGNUM_TOP_BIT 0x80000000UL ++#define BIGNUM_INT_BITS 32 ++ ++ ++static void *snmalloc(void *mem_ctx, size_t n, size_t size) ++{ ++ void *p; ++ size *= n; ++ if (size == 0) size = 1; ++ p = dwc_alloc(mem_ctx, size); ++ return p; ++} ++ ++#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type))) ++#define sfree dwc_free ++ ++/* ++ * Usage notes: ++ * * Do not call the DIVMOD_WORD macro with expressions such as array ++ * subscripts, as some implementations object to this (see below). ++ * * Note that none of the division methods below will cope if the ++ * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful ++ * to avoid this case. ++ * If this condition occurs, in the case of the x86 DIV instruction, ++ * an overflow exception will occur, which (according to a correspondent) ++ * will manifest on Windows as something like ++ * 0xC0000095: Integer overflow ++ * The C variant won't give the right answer, either. ++ */ ++ ++#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2) ++ ++#if defined __GNUC__ && defined __i386__ ++#define DIVMOD_WORD(q, r, hi, lo, w) \ ++ __asm__("div %2" : \ ++ "=d" (r), "=a" (q) : \ ++ "r" (w), "d" (hi), "a" (lo)) ++#else ++#define DIVMOD_WORD(q, r, hi, lo, w) do { \ ++ BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \ ++ q = n / w; \ ++ r = n % w; \ ++} while (0) ++#endif ++ ++// q = n / w; ++// r = n % w; ++ ++#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8) ++ ++#define BIGNUM_INTERNAL ++ ++static Bignum newbn(void *mem_ctx, int length) ++{ ++ Bignum b = snewn(mem_ctx, length + 1, BignumInt); ++ //if (!b) ++ //abort(); /* FIXME */ ++ DWC_MEMSET(b, 0, (length + 1) * sizeof(*b)); ++ b[0] = length; ++ return b; ++} ++ ++void freebn(void *mem_ctx, Bignum b) ++{ ++ /* ++ * Burn the evidence, just in case. ++ */ ++ DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1)); ++ sfree(mem_ctx, b); ++} ++ ++/* ++ * Compute c = a * b. ++ * Input is in the first len words of a and b. ++ * Result is returned in the first 2*len words of c. ++ */ ++static void internal_mul(BignumInt *a, BignumInt *b, ++ BignumInt *c, int len) ++{ ++ int i, j; ++ BignumDblInt t; ++ ++ for (j = 0; j < 2 * len; j++) ++ c[j] = 0; ++ ++ for (i = len - 1; i >= 0; i--) { ++ t = 0; ++ for (j = len - 1; j >= 0; j--) { ++ t += MUL_WORD(a[i], (BignumDblInt) b[j]); ++ t += (BignumDblInt) c[i + j + 1]; ++ c[i + j + 1] = (BignumInt) t; ++ t = t >> BIGNUM_INT_BITS; ++ } ++ c[i] = (BignumInt) t; ++ } ++} ++ ++static void internal_add_shifted(BignumInt *number, ++ unsigned n, int shift) ++{ ++ int word = 1 + (shift / BIGNUM_INT_BITS); ++ int bshift = shift % BIGNUM_INT_BITS; ++ BignumDblInt addend; ++ ++ addend = (BignumDblInt)n << bshift; ++ ++ while (addend) { ++ addend += number[word]; ++ number[word] = (BignumInt) addend & BIGNUM_INT_MASK; ++ addend >>= BIGNUM_INT_BITS; ++ word++; ++ } ++} ++ ++/* ++ * Compute a = a % m. ++ * Input in first alen words of a and first mlen words of m. ++ * Output in first alen words of a ++ * (of which first alen-mlen words will be zero). ++ * The MSW of m MUST have its high bit set. ++ * Quotient is accumulated in the `quotient' array, which is a Bignum ++ * rather than the internal bigendian format. Quotient parts are shifted ++ * left by `qshift' before adding into quot. ++ */ ++static void internal_mod(BignumInt *a, int alen, ++ BignumInt *m, int mlen, ++ BignumInt *quot, int qshift) ++{ ++ BignumInt m0, m1; ++ unsigned int h; ++ int i, k; ++ ++ m0 = m[0]; ++ if (mlen > 1) ++ m1 = m[1]; ++ else ++ m1 = 0; ++ ++ for (i = 0; i <= alen - mlen; i++) { ++ BignumDblInt t; ++ unsigned int q, r, c, ai1; ++ ++ if (i == 0) { ++ h = 0; ++ } else { ++ h = a[i - 1]; ++ a[i - 1] = 0; ++ } ++ ++ if (i == alen - 1) ++ ai1 = 0; ++ else ++ ai1 = a[i + 1]; ++ ++ /* Find q = h:a[i] / m0 */ ++ if (h >= m0) { ++ /* ++ * Special case. ++ * ++ * To illustrate it, suppose a BignumInt is 8 bits, and ++ * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then ++ * our initial division will be 0xA123 / 0xA1, which ++ * will give a quotient of 0x100 and a divide overflow. ++ * However, the invariants in this division algorithm ++ * are not violated, since the full number A1:23:... is ++ * _less_ than the quotient prefix A1:B2:... and so the ++ * following correction loop would have sorted it out. ++ * ++ * In this situation we set q to be the largest ++ * quotient we _can_ stomach (0xFF, of course). ++ */ ++ q = BIGNUM_INT_MASK; ++ } else { ++ /* Macro doesn't want an array subscript expression passed ++ * into it (see definition), so use a temporary. */ ++ BignumInt tmplo = a[i]; ++ DIVMOD_WORD(q, r, h, tmplo, m0); ++ ++ /* Refine our estimate of q by looking at ++ h:a[i]:a[i+1] / m0:m1 */ ++ t = MUL_WORD(m1, q); ++ if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) { ++ q--; ++ t -= m1; ++ r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */ ++ if (r >= (BignumDblInt) m0 && ++ t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--; ++ } ++ } ++ ++ /* Subtract q * m from a[i...] */ ++ c = 0; ++ for (k = mlen - 1; k >= 0; k--) { ++ t = MUL_WORD(q, m[k]); ++ t += c; ++ c = (unsigned)(t >> BIGNUM_INT_BITS); ++ if ((BignumInt) t > a[i + k]) ++ c++; ++ a[i + k] -= (BignumInt) t; ++ } ++ ++ /* Add back m in case of borrow */ ++ if (c != h) { ++ t = 0; ++ for (k = mlen - 1; k >= 0; k--) { ++ t += m[k]; ++ t += a[i + k]; ++ a[i + k] = (BignumInt) t; ++ t = t >> BIGNUM_INT_BITS; ++ } ++ q--; ++ } ++ if (quot) ++ internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i)); ++ } ++} ++ ++/* ++ * Compute p % mod. ++ * The most significant word of mod MUST be non-zero. ++ * We assume that the result array is the same size as the mod array. ++ * We optionally write out a quotient if `quotient' is non-NULL. ++ * We can avoid writing out the result if `result' is NULL. ++ */ ++void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient) ++{ ++ BignumInt *n, *m; ++ int mshift; ++ int plen, mlen, i, j; ++ ++ /* Allocate m of size mlen, copy mod to m */ ++ /* We use big endian internally */ ++ mlen = mod[0]; ++ m = snewn(mem_ctx, mlen, BignumInt); ++ //if (!m) ++ //abort(); /* FIXME */ ++ for (j = 0; j < mlen; j++) ++ m[j] = mod[mod[0] - j]; ++ ++ /* Shift m left to make msb bit set */ ++ for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++) ++ if ((m[0] << mshift) & BIGNUM_TOP_BIT) ++ break; ++ if (mshift) { ++ for (i = 0; i < mlen - 1; i++) ++ m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift)); ++ m[mlen - 1] = m[mlen - 1] << mshift; ++ } ++ ++ plen = p[0]; ++ /* Ensure plen > mlen */ ++ if (plen <= mlen) ++ plen = mlen + 1; ++ ++ /* Allocate n of size plen, copy p to n */ ++ n = snewn(mem_ctx, plen, BignumInt); ++ //if (!n) ++ //abort(); /* FIXME */ ++ for (j = 0; j < plen; j++) ++ n[j] = 0; ++ for (j = 1; j <= (int)p[0]; j++) ++ n[plen - j] = p[j]; ++ ++ /* Main computation */ ++ internal_mod(n, plen, m, mlen, quotient, mshift); ++ ++ /* Fixup result in case the modulus was shifted */ ++ if (mshift) { ++ for (i = plen - mlen - 1; i < plen - 1; i++) ++ n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift)); ++ n[plen - 1] = n[plen - 1] << mshift; ++ internal_mod(n, plen, m, mlen, quotient, 0); ++ for (i = plen - 1; i >= plen - mlen; i--) ++ n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift)); ++ } ++ ++ /* Copy result to buffer */ ++ if (result) { ++ for (i = 1; i <= (int)result[0]; i++) { ++ int j = plen - i; ++ result[i] = j >= 0 ? n[j] : 0; ++ } ++ } ++ ++ /* Free temporary arrays */ ++ for (i = 0; i < mlen; i++) ++ m[i] = 0; ++ sfree(mem_ctx, m); ++ for (i = 0; i < plen; i++) ++ n[i] = 0; ++ sfree(mem_ctx, n); ++} ++ ++/* ++ * Simple remainder. ++ */ ++Bignum bigmod(void *mem_ctx, Bignum a, Bignum b) ++{ ++ Bignum r = newbn(mem_ctx, b[0]); ++ bigdivmod(mem_ctx, a, b, r, NULL); ++ return r; ++} ++ ++/* ++ * Compute (base ^ exp) % mod. ++ */ ++Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod) ++{ ++ BignumInt *a, *b, *n, *m; ++ int mshift; ++ int mlen, i, j; ++ Bignum base, result; ++ ++ /* ++ * The most significant word of mod needs to be non-zero. It ++ * should already be, but let's make sure. ++ */ ++ //assert(mod[mod[0]] != 0); ++ ++ /* ++ * Make sure the base is smaller than the modulus, by reducing ++ * it modulo the modulus if not. ++ */ ++ base = bigmod(mem_ctx, base_in, mod); ++ ++ /* Allocate m of size mlen, copy mod to m */ ++ /* We use big endian internally */ ++ mlen = mod[0]; ++ m = snewn(mem_ctx, mlen, BignumInt); ++ //if (!m) ++ //abort(); /* FIXME */ ++ for (j = 0; j < mlen; j++) ++ m[j] = mod[mod[0] - j]; ++ ++ /* Shift m left to make msb bit set */ ++ for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++) ++ if ((m[0] << mshift) & BIGNUM_TOP_BIT) ++ break; ++ if (mshift) { ++ for (i = 0; i < mlen - 1; i++) ++ m[i] = ++ (m[i] << mshift) | (m[i + 1] >> ++ (BIGNUM_INT_BITS - mshift)); ++ m[mlen - 1] = m[mlen - 1] << mshift; ++ } ++ ++ /* Allocate n of size mlen, copy base to n */ ++ n = snewn(mem_ctx, mlen, BignumInt); ++ //if (!n) ++ //abort(); /* FIXME */ ++ i = mlen - base[0]; ++ for (j = 0; j < i; j++) ++ n[j] = 0; ++ for (j = 0; j < base[0]; j++) ++ n[i + j] = base[base[0] - j]; ++ ++ /* Allocate a and b of size 2*mlen. Set a = 1 */ ++ a = snewn(mem_ctx, 2 * mlen, BignumInt); ++ //if (!a) ++ //abort(); /* FIXME */ ++ b = snewn(mem_ctx, 2 * mlen, BignumInt); ++ //if (!b) ++ //abort(); /* FIXME */ ++ for (i = 0; i < 2 * mlen; i++) ++ a[i] = 0; ++ a[2 * mlen - 1] = 1; ++ ++ /* Skip leading zero bits of exp. */ ++ i = 0; ++ j = BIGNUM_INT_BITS - 1; ++ while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) { ++ j--; ++ if (j < 0) { ++ i++; ++ j = BIGNUM_INT_BITS - 1; ++ } ++ } ++ ++ /* Main computation */ ++ while (i < exp[0]) { ++ while (j >= 0) { ++ internal_mul(a + mlen, a + mlen, b, mlen); ++ internal_mod(b, mlen * 2, m, mlen, NULL, 0); ++ if ((exp[exp[0] - i] & (1 << j)) != 0) { ++ internal_mul(b + mlen, n, a, mlen); ++ internal_mod(a, mlen * 2, m, mlen, NULL, 0); ++ } else { ++ BignumInt *t; ++ t = a; ++ a = b; ++ b = t; ++ } ++ j--; ++ } ++ i++; ++ j = BIGNUM_INT_BITS - 1; ++ } ++ ++ /* Fixup result in case the modulus was shifted */ ++ if (mshift) { ++ for (i = mlen - 1; i < 2 * mlen - 1; i++) ++ a[i] = ++ (a[i] << mshift) | (a[i + 1] >> ++ (BIGNUM_INT_BITS - mshift)); ++ a[2 * mlen - 1] = a[2 * mlen - 1] << mshift; ++ internal_mod(a, mlen * 2, m, mlen, NULL, 0); ++ for (i = 2 * mlen - 1; i >= mlen; i--) ++ a[i] = ++ (a[i] >> mshift) | (a[i - 1] << ++ (BIGNUM_INT_BITS - mshift)); ++ } ++ ++ /* Copy result to buffer */ ++ result = newbn(mem_ctx, mod[0]); ++ for (i = 0; i < mlen; i++) ++ result[result[0] - i] = a[i + mlen]; ++ while (result[0] > 1 && result[result[0]] == 0) ++ result[0]--; ++ ++ /* Free temporary arrays */ ++ for (i = 0; i < 2 * mlen; i++) ++ a[i] = 0; ++ sfree(mem_ctx, a); ++ for (i = 0; i < 2 * mlen; i++) ++ b[i] = 0; ++ sfree(mem_ctx, b); ++ for (i = 0; i < mlen; i++) ++ m[i] = 0; ++ sfree(mem_ctx, m); ++ for (i = 0; i < mlen; i++) ++ n[i] = 0; ++ sfree(mem_ctx, n); ++ ++ freebn(mem_ctx, base); ++ ++ return result; ++} ++ ++ ++#ifdef UNITTEST ++ ++static __u32 dh_p[] = { ++ 96, ++ 0xFFFFFFFF, ++ 0xFFFFFFFF, ++ 0xA93AD2CA, ++ 0x4B82D120, ++ 0xE0FD108E, ++ 0x43DB5BFC, ++ 0x74E5AB31, ++ 0x08E24FA0, ++ 0xBAD946E2, ++ 0x770988C0, ++ 0x7A615D6C, ++ 0xBBE11757, ++ 0x177B200C, ++ 0x521F2B18, ++ 0x3EC86A64, ++ 0xD8760273, ++ 0xD98A0864, ++ 0xF12FFA06, ++ 0x1AD2EE6B, ++ 0xCEE3D226, ++ 0x4A25619D, ++ 0x1E8C94E0, ++ 0xDB0933D7, ++ 0xABF5AE8C, ++ 0xA6E1E4C7, ++ 0xB3970F85, ++ 0x5D060C7D, ++ 0x8AEA7157, ++ 0x58DBEF0A, ++ 0xECFB8504, ++ 0xDF1CBA64, ++ 0xA85521AB, ++ 0x04507A33, ++ 0xAD33170D, ++ 0x8AAAC42D, ++ 0x15728E5A, ++ 0x98FA0510, ++ 0x15D22618, ++ 0xEA956AE5, ++ 0x3995497C, ++ 0x95581718, ++ 0xDE2BCBF6, ++ 0x6F4C52C9, ++ 0xB5C55DF0, ++ 0xEC07A28F, ++ 0x9B2783A2, ++ 0x180E8603, ++ 0xE39E772C, ++ 0x2E36CE3B, ++ 0x32905E46, ++ 0xCA18217C, ++ 0xF1746C08, ++ 0x4ABC9804, ++ 0x670C354E, ++ 0x7096966D, ++ 0x9ED52907, ++ 0x208552BB, ++ 0x1C62F356, ++ 0xDCA3AD96, ++ 0x83655D23, ++ 0xFD24CF5F, ++ 0x69163FA8, ++ 0x1C55D39A, ++ 0x98DA4836, ++ 0xA163BF05, ++ 0xC2007CB8, ++ 0xECE45B3D, ++ 0x49286651, ++ 0x7C4B1FE6, ++ 0xAE9F2411, ++ 0x5A899FA5, ++ 0xEE386BFB, ++ 0xF406B7ED, ++ 0x0BFF5CB6, ++ 0xA637ED6B, ++ 0xF44C42E9, ++ 0x625E7EC6, ++ 0xE485B576, ++ 0x6D51C245, ++ 0x4FE1356D, ++ 0xF25F1437, ++ 0x302B0A6D, ++ 0xCD3A431B, ++ 0xEF9519B3, ++ 0x8E3404DD, ++ 0x514A0879, ++ 0x3B139B22, ++ 0x020BBEA6, ++ 0x8A67CC74, ++ 0x29024E08, ++ 0x80DC1CD1, ++ 0xC4C6628B, ++ 0x2168C234, ++ 0xC90FDAA2, ++ 0xFFFFFFFF, ++ 0xFFFFFFFF, ++}; ++ ++static __u32 dh_a[] = { ++ 8, ++ 0xdf367516, ++ 0x86459caa, ++ 0xe2d459a4, ++ 0xd910dae0, ++ 0x8a8b5e37, ++ 0x67ab31c6, ++ 0xf0b55ea9, ++ 0x440051d6, ++}; ++ ++static __u32 dh_b[] = { ++ 8, ++ 0xded92656, ++ 0xe07a048a, ++ 0x6fa452cd, ++ 0x2df89d30, ++ 0xc75f1b0f, ++ 0x8ce3578f, ++ 0x7980a324, ++ 0x5daec786, ++}; ++ ++static __u32 dh_g[] = { ++ 1, ++ 2, ++}; ++ ++int main(void) ++{ ++ int i; ++ __u32 *k; ++ k = dwc_modpow(NULL, dh_g, dh_a, dh_p); ++ ++ printf("\n\n"); ++ for (i=0; i> 16; ++ printf("%04x %04x ", m, l); ++ if (!((i + 1)%13)) printf("\n"); ++ } ++ printf("\n\n"); ++ ++ if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) { ++ printf("PASS\n\n"); ++ } ++ else { ++ printf("FAIL\n\n"); ++ } ++ ++} ++ ++#endif /* UNITTEST */ ++ ++#endif /* CONFIG_MACH_IPMATE */ ++ ++#endif /*DWC_CRYPTOLIB */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_modpow.h +@@ -0,0 +1,34 @@ ++/* ++ * dwc_modpow.h ++ * See dwc_modpow.c for license and changes ++ */ ++#ifndef _DWC_MODPOW_H ++#define _DWC_MODPOW_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "dwc_os.h" ++ ++/** @file ++ * ++ * This file defines the module exponentiation function which is only used ++ * internally by the DWC UWB modules for calculation of PKs during numeric ++ * association. The routine is taken from the PUTTY, an open source terminal ++ * emulator. The PUTTY License is preserved in the dwc_modpow.c file. ++ * ++ */ ++ ++typedef uint32_t BignumInt; ++typedef uint64_t BignumDblInt; ++typedef BignumInt *Bignum; ++ ++/* Compute modular exponentiaion */ ++extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _LINUX_BIGNUM_H */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_notifier.c +@@ -0,0 +1,319 @@ ++#ifdef DWC_NOTIFYLIB ++ ++#include "dwc_notifier.h" ++#include "dwc_list.h" ++ ++typedef struct dwc_observer { ++ void *observer; ++ dwc_notifier_callback_t callback; ++ void *data; ++ char *notification; ++ DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry; ++} observer_t; ++ ++DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer); ++ ++typedef struct dwc_notifier { ++ void *mem_ctx; ++ void *object; ++ struct observer_queue observers; ++ DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry; ++} notifier_t; ++ ++DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier); ++ ++typedef struct manager { ++ void *mem_ctx; ++ void *wkq_ctx; ++ dwc_workq_t *wq; ++// dwc_mutex_t *mutex; ++ struct notifier_queue notifiers; ++} manager_t; ++ ++static manager_t *manager = NULL; ++ ++static int create_manager(void *mem_ctx, void *wkq_ctx) ++{ ++ manager = dwc_alloc(mem_ctx, sizeof(manager_t)); ++ if (!manager) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_CIRCLEQ_INIT(&manager->notifiers); ++ ++ manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ"); ++ if (!manager->wq) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ return 0; ++} ++ ++static void free_manager(void) ++{ ++ dwc_workq_free(manager->wq); ++ ++ /* All notifiers must have unregistered themselves before this module ++ * can be removed. Hitting this assertion indicates a programmer ++ * error. */ ++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers), ++ "Notification manager being freed before all notifiers have been removed"); ++ dwc_free(manager->mem_ctx, manager); ++} ++ ++#ifdef DEBUG ++static void dump_manager(void) ++{ ++ notifier_t *n; ++ observer_t *o; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ DWC_DEBUG("List of all notifiers and observers:\n"); ++ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { ++ DWC_DEBUG("Notifier %p has observers:\n", n->object); ++ DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) { ++ DWC_DEBUG(" %p watching %s\n", o->observer, o->notification); ++ } ++ } ++} ++#else ++#define dump_manager(...) ++#endif ++ ++static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification, ++ dwc_notifier_callback_t callback, void *data) ++{ ++ observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t)); ++ ++ if (!new_observer) { ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry); ++ new_observer->observer = observer; ++ new_observer->notification = notification; ++ new_observer->callback = callback; ++ new_observer->data = data; ++ return new_observer; ++} ++ ++static void free_observer(void *mem_ctx, observer_t *observer) ++{ ++ dwc_free(mem_ctx, observer); ++} ++ ++static notifier_t *alloc_notifier(void *mem_ctx, void *object) ++{ ++ notifier_t *notifier; ++ ++ if (!object) { ++ return NULL; ++ } ++ ++ notifier = dwc_alloc(mem_ctx, sizeof(notifier_t)); ++ if (!notifier) { ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_INIT(¬ifier->observers); ++ DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry); ++ ++ notifier->mem_ctx = mem_ctx; ++ notifier->object = object; ++ return notifier; ++} ++ ++static void free_notifier(notifier_t *notifier) ++{ ++ observer_t *observer; ++ ++ DWC_CIRCLEQ_FOREACH(observer, ¬ifier->observers, list_entry) { ++ free_observer(notifier->mem_ctx, observer); ++ } ++ ++ dwc_free(notifier->mem_ctx, notifier); ++} ++ ++static notifier_t *find_notifier(void *object) ++{ ++ notifier_t *notifier; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ if (!object) { ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) { ++ if (notifier->object == object) { ++ return notifier; ++ } ++ } ++ ++ return NULL; ++} ++ ++int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx) ++{ ++ return create_manager(mem_ctx, wkq_ctx); ++} ++ ++void dwc_free_notification_manager(void) ++{ ++ free_manager(); ++} ++ ++dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object) ++{ ++ notifier_t *notifier; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ notifier = find_notifier(object); ++ if (notifier) { ++ DWC_ERROR("Notifier %p is already registered\n", object); ++ return NULL; ++ } ++ ++ notifier = alloc_notifier(mem_ctx, object); ++ if (!notifier) { ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry); ++ ++ DWC_INFO("Notifier %p registered", object); ++ dump_manager(); ++ ++ return notifier; ++} ++ ++void dwc_unregister_notifier(dwc_notifier_t *notifier) ++{ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ if (!DWC_CIRCLEQ_EMPTY(¬ifier->observers)) { ++ observer_t *o; ++ ++ DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object); ++ DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { ++ DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification); ++ } ++ ++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(¬ifier->observers), ++ "Notifier %p has active observers when removing", notifier); ++ } ++ ++ DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry); ++ free_notifier(notifier); ++ ++ DWC_INFO("Notifier unregistered"); ++ dump_manager(); ++} ++ ++/* Add an observer to observe the notifier for a particular state, event, or notification. */ ++int dwc_add_observer(void *observer, void *object, char *notification, ++ dwc_notifier_callback_t callback, void *data) ++{ ++ notifier_t *notifier = find_notifier(object); ++ observer_t *new_observer; ++ ++ if (!notifier) { ++ DWC_ERROR("Notifier %p is not found when adding observer\n", object); ++ return -DWC_E_INVALID; ++ } ++ ++ new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data); ++ if (!new_observer) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_CIRCLEQ_INSERT_TAIL(¬ifier->observers, new_observer, list_entry); ++ ++ DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p", ++ observer, object, notification, callback, data); ++ ++ dump_manager(); ++ return 0; ++} ++ ++int dwc_remove_observer(void *observer) ++{ ++ notifier_t *n; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { ++ observer_t *o; ++ observer_t *o2; ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) { ++ if (o->observer == observer) { ++ DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry); ++ DWC_INFO("Removing observer %p from notifier %p watching notification %s:", ++ o->observer, n->object, o->notification); ++ free_observer(n->mem_ctx, o); ++ } ++ } ++ } ++ ++ dump_manager(); ++ return 0; ++} ++ ++typedef struct callback_data { ++ void *mem_ctx; ++ dwc_notifier_callback_t cb; ++ void *observer; ++ void *data; ++ void *object; ++ char *notification; ++ void *notification_data; ++} cb_data_t; ++ ++static void cb_task(void *data) ++{ ++ cb_data_t *cb = (cb_data_t *)data; ++ ++ cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data); ++ dwc_free(cb->mem_ctx, cb); ++} ++ ++void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data) ++{ ++ observer_t *o; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { ++ int len = DWC_STRLEN(notification); ++ ++ if (DWC_STRLEN(o->notification) != len) { ++ continue; ++ } ++ ++ if (DWC_STRNCMP(o->notification, notification, len) == 0) { ++ cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t)); ++ ++ if (!cb_data) { ++ DWC_ERROR("Failed to allocate callback data\n"); ++ return; ++ } ++ ++ cb_data->mem_ctx = notifier->mem_ctx; ++ cb_data->cb = o->callback; ++ cb_data->observer = o->observer; ++ cb_data->data = o->data; ++ cb_data->object = notifier->object; ++ cb_data->notification = notification; ++ cb_data->notification_data = notification_data; ++ DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification); ++ DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data, ++ "Notify callback from %p for Notification %s, to observer %p", ++ cb_data->object, notification, cb_data->observer); ++ } ++ } ++} ++ ++#endif /* DWC_NOTIFYLIB */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_notifier.h +@@ -0,0 +1,122 @@ ++ ++#ifndef __DWC_NOTIFIER_H__ ++#define __DWC_NOTIFIER_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "dwc_os.h" ++ ++/** @file ++ * ++ * A simple implementation of the Observer pattern. Any "module" can ++ * register as an observer or notifier. The notion of "module" is abstract and ++ * can mean anything used to identify either an observer or notifier. Usually ++ * it will be a pointer to a data structure which contains some state, ie an ++ * object. ++ * ++ * Before any notifiers can be added, the global notification manager must be ++ * brought up with dwc_alloc_notification_manager(). ++ * dwc_free_notification_manager() will bring it down and free all resources. ++ * These would typically be called upon module load and unload. The ++ * notification manager is a single global instance that handles all registered ++ * observable modules and observers so this should be done only once. ++ * ++ * A module can be observable by using Notifications to publicize some general ++ * information about it's state or operation. It does not care who listens, or ++ * even if anyone listens, or what they do with the information. The observable ++ * modules do not need to know any information about it's observers or their ++ * interface, or their state or data. ++ * ++ * Any module can register to emit Notifications. It should publish a list of ++ * notifications that it can emit and their behavior, such as when they will get ++ * triggered, and what information will be provided to the observer. Then it ++ * should register itself as an observable module. See dwc_register_notifier(). ++ * ++ * Any module can observe any observable, registered module, provided it has a ++ * handle to the other module and knows what notifications to observe. See ++ * dwc_add_observer(). ++ * ++ * A function of type dwc_notifier_callback_t is called whenever a notification ++ * is triggered with one or more observers observing it. This function is ++ * called in it's own process so it may sleep or block if needed. It is ++ * guaranteed to be called sometime after the notification has occurred and will ++ * be called once per each time the notification is triggered. It will NOT be ++ * called in the same process context used to trigger the notification. ++ * ++ * @section Limitiations ++ * ++ * Keep in mind that Notifications that can be triggered in rapid sucession may ++ * schedule too many processes too handle. Be aware of this limitation when ++ * designing to use notifications, and only add notifications for appropriate ++ * observable information. ++ * ++ * Also Notification callbacks are not synchronous. If you need to synchronize ++ * the behavior between module/observer you must use other means. And perhaps ++ * that will mean Notifications are not the proper solution. ++ */ ++ ++struct dwc_notifier; ++typedef struct dwc_notifier dwc_notifier_t; ++ ++/** The callback function must be of this type. ++ * ++ * @param object This is the object that is being observed. ++ * @param notification This is the notification that was triggered. ++ * @param observer This is the observer ++ * @param notification_data This is notification-specific data that the notifier ++ * has included in this notification. The value of this should be published in ++ * the documentation of the observable module with the notifications. ++ * @param user_data This is any custom data that the observer provided when ++ * adding itself as an observer to the notification. */ ++typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer, ++ void *notification_data, void *user_data); ++ ++/** Brings up the notification manager. */ ++extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx); ++/** Brings down the notification manager. */ ++extern void dwc_free_notification_manager(void); ++ ++/** This function registers an observable module. A dwc_notifier_t object is ++ * returned to the observable module. This is an opaque object that is used by ++ * the observable module to trigger notifications. This object should only be ++ * accessible to functions that are authorized to trigger notifications for this ++ * module. Observers do not need this object. */ ++extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object); ++ ++/** This function unregisters an observable module. All observers have to be ++ * removed prior to unregistration. */ ++extern void dwc_unregister_notifier(dwc_notifier_t *notifier); ++ ++/** Add a module as an observer to the observable module. The observable module ++ * needs to have previously registered with the notification manager. ++ * ++ * @param observer The observer module ++ * @param object The module to observe ++ * @param notification The notification to observe ++ * @param callback The callback function to call ++ * @param user_data Any additional user data to pass into the callback function */ ++extern int dwc_add_observer(void *observer, void *object, char *notification, ++ dwc_notifier_callback_t callback, void *user_data); ++ ++/** Removes the specified observer from all notifications that it is currently ++ * observing. */ ++extern int dwc_remove_observer(void *observer); ++ ++/** This function triggers a Notification. It should be called by the ++ * observable module, or any module or library which the observable module ++ * allows to trigger notification on it's behalf. Such as the dwc_cc_t. ++ * ++ * dwc_notify is a non-blocking function. Callbacks are scheduled called in ++ * their own process context for each trigger. Callbacks can be blocking. ++ * dwc_notify can be called from interrupt context if needed. ++ * ++ */ ++void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* __DWC_NOTIFIER_H__ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/dwc_os.h +@@ -0,0 +1,1276 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $ ++ * $Revision: #14 $ ++ * $Date: 2010/11/04 $ ++ * $Change: 1621695 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifndef _DWC_OS_H_ ++#define _DWC_OS_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** @file ++ * ++ * DWC portability library, low level os-wrapper functions ++ * ++ */ ++ ++/* These basic types need to be defined by some OS header file or custom header ++ * file for your specific target architecture. ++ * ++ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t ++ * ++ * Any custom or alternate header file must be added and enabled here. ++ */ ++ ++#ifdef DWC_LINUX ++# include ++# ifdef CONFIG_DEBUG_MUTEXES ++# include ++# endif ++# include ++# include ++# include ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++# include ++#endif ++ ++ ++/** @name Primitive Types and Values */ ++ ++/** We define a boolean type for consistency. Can be either YES or NO */ ++typedef uint8_t dwc_bool_t; ++#define YES 1 ++#define NO 0 ++ ++#ifdef DWC_LINUX ++ ++/** @name Error Codes */ ++#define DWC_E_INVALID EINVAL ++#define DWC_E_NO_MEMORY ENOMEM ++#define DWC_E_NO_DEVICE ENODEV ++#define DWC_E_NOT_SUPPORTED EOPNOTSUPP ++#define DWC_E_TIMEOUT ETIMEDOUT ++#define DWC_E_BUSY EBUSY ++#define DWC_E_AGAIN EAGAIN ++#define DWC_E_RESTART ERESTART ++#define DWC_E_ABORT ECONNABORTED ++#define DWC_E_SHUTDOWN ESHUTDOWN ++#define DWC_E_NO_DATA ENODATA ++#define DWC_E_DISCONNECT ECONNRESET ++#define DWC_E_UNKNOWN EINVAL ++#define DWC_E_NO_STREAM_RES ENOSR ++#define DWC_E_COMMUNICATION ECOMM ++#define DWC_E_OVERFLOW EOVERFLOW ++#define DWC_E_PROTOCOL EPROTO ++#define DWC_E_IN_PROGRESS EINPROGRESS ++#define DWC_E_PIPE EPIPE ++#define DWC_E_IO EIO ++#define DWC_E_NO_SPACE ENOSPC ++ ++#else ++ ++/** @name Error Codes */ ++#define DWC_E_INVALID 1001 ++#define DWC_E_NO_MEMORY 1002 ++#define DWC_E_NO_DEVICE 1003 ++#define DWC_E_NOT_SUPPORTED 1004 ++#define DWC_E_TIMEOUT 1005 ++#define DWC_E_BUSY 1006 ++#define DWC_E_AGAIN 1007 ++#define DWC_E_RESTART 1008 ++#define DWC_E_ABORT 1009 ++#define DWC_E_SHUTDOWN 1010 ++#define DWC_E_NO_DATA 1011 ++#define DWC_E_DISCONNECT 2000 ++#define DWC_E_UNKNOWN 3000 ++#define DWC_E_NO_STREAM_RES 4001 ++#define DWC_E_COMMUNICATION 4002 ++#define DWC_E_OVERFLOW 4003 ++#define DWC_E_PROTOCOL 4004 ++#define DWC_E_IN_PROGRESS 4005 ++#define DWC_E_PIPE 4006 ++#define DWC_E_IO 4007 ++#define DWC_E_NO_SPACE 4008 ++ ++#endif ++ ++ ++/** @name Tracing/Logging Functions ++ * ++ * These function provide the capability to add tracing, debugging, and error ++ * messages, as well exceptions as assertions. The WUDEV uses these ++ * extensively. These could be logged to the main console, the serial port, an ++ * internal buffer, etc. These functions could also be no-op if they are too ++ * expensive on your system. By default undefining the DEBUG macro already ++ * no-ops some of these functions. */ ++ ++/** Returns non-zero if in interrupt context. */ ++extern dwc_bool_t DWC_IN_IRQ(void); ++#define dwc_in_irq DWC_IN_IRQ ++ ++/** Returns "IRQ" if DWC_IN_IRQ is true. */ ++static inline char *dwc_irq(void) { ++ return DWC_IN_IRQ() ? "IRQ" : ""; ++} ++ ++/** Returns non-zero if in bottom-half context. */ ++extern dwc_bool_t DWC_IN_BH(void); ++#define dwc_in_bh DWC_IN_BH ++ ++/** Returns "BH" if DWC_IN_BH is true. */ ++static inline char *dwc_bh(void) { ++ return DWC_IN_BH() ? "BH" : ""; ++} ++ ++/** ++ * A vprintf() clone. Just call vprintf if you've got it. ++ */ ++extern void DWC_VPRINTF(char *format, va_list args); ++#define dwc_vprintf DWC_VPRINTF ++ ++/** ++ * A vsnprintf() clone. Just call vprintf if you've got it. ++ */ ++extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args); ++#define dwc_vsnprintf DWC_VSNPRINTF ++ ++/** ++ * printf() clone. Just call printf if you've go it. ++ */ ++extern void DWC_PRINTF(char *format, ...) ++/* This provides compiler level static checking of the parameters if you're ++ * using GCC. */ ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#define dwc_printf DWC_PRINTF ++ ++/** ++ * sprintf() clone. Just call sprintf if you've got it. ++ */ ++extern int DWC_SPRINTF(char *string, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 2, 3))); ++#else ++ ; ++#endif ++#define dwc_sprintf DWC_SPRINTF ++ ++/** ++ * snprintf() clone. Just call snprintf if you've got it. ++ */ ++extern int DWC_SNPRINTF(char *string, int size, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 3, 4))); ++#else ++ ; ++#endif ++#define dwc_snprintf DWC_SNPRINTF ++ ++/** ++ * Prints a WARNING message. On systems that don't differentiate between ++ * warnings and regular log messages, just print it. Indicates that something ++ * may be wrong with the driver. Works like printf(). ++ * ++ * Use the DWC_WARN macro to call this function. ++ */ ++extern void __DWC_WARN(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++ ++/** ++ * Prints an error message. On systems that don't differentiate between errors ++ * and regular log messages, just print it. Indicates that something went wrong ++ * with the driver. Works like printf(). ++ * ++ * Use the DWC_ERROR macro to call this function. ++ */ ++extern void __DWC_ERROR(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++ ++/** ++ * Prints an exception error message and takes some user-defined action such as ++ * print out a backtrace or trigger a breakpoint. Indicates that something went ++ * abnormally wrong with the driver such as programmer error, or other ++ * exceptional condition. It should not be ignored so even on systems without ++ * printing capability, some action should be taken to notify the developer of ++ * it. Works like printf(). ++ */ ++extern void DWC_EXCEPTION(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#define dwc_exception DWC_EXCEPTION ++ ++#ifndef DWC_OTG_DEBUG_LEV ++#define DWC_OTG_DEBUG_LEV 0 ++#endif ++ ++#ifdef DEBUG ++/** ++ * Prints out a debug message. Used for logging/trace messages. ++ * ++ * Use the DWC_DEBUG macro to call this function ++ */ ++extern void __DWC_DEBUG(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#else ++#define __DWC_DEBUG printk ++#endif ++ ++/** ++ * Prints out a Debug message. ++ */ ++#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \ ++ __func__, dwc_irq(), ## _args) ++#define dwc_debug DWC_DEBUG ++/** ++ * Prints out a Debug message if enabled at compile time. ++ */ ++#if DWC_OTG_DEBUG_LEV > 0 ++#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args ) ++#else ++#define DWC_DEBUGC(_format, _args...) ++#endif ++#define dwc_debugc DWC_DEBUGC ++/** ++ * Prints out an informative message. ++ */ ++#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \ ++ dwc_irq(), ## _args) ++#define dwc_info DWC_INFO ++/** ++ * Prints out an informative message if enabled at compile time. ++ */ ++#if DWC_OTG_DEBUG_LEV > 1 ++#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args ) ++#else ++#define DWC_INFOC(_format, _args...) ++#endif ++#define dwc_infoc DWC_INFOC ++/** ++ * Prints out a warning message. ++ */ ++#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_warn DWC_WARN ++/** ++ * Prints out an error message. ++ */ ++#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_error DWC_ERROR ++ ++#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_proto_error DWC_PROTO_ERROR ++ ++#ifdef DEBUG ++/** Prints out a exception error message if the _expr expression fails. Disabled ++ * if DEBUG is not enabled. */ ++#define DWC_ASSERT(_expr, _format, _args...) do { \ ++ if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \ ++ __FILE__, __LINE__, ## _args); } \ ++ } while (0) ++#else ++#define DWC_ASSERT(_x...) ++#endif ++#define dwc_assert DWC_ASSERT ++ ++ ++/** @name Byte Ordering ++ * The following functions are for conversions between processor's byte ordering ++ * and specific ordering you want. ++ */ ++ ++/** Converts 32 bit data in CPU byte ordering to little endian. */ ++extern uint32_t DWC_CPU_TO_LE32(uint32_t *p); ++#define dwc_cpu_to_le32 DWC_CPU_TO_LE32 ++ ++/** Converts 32 bit data in CPU byte orderint to big endian. */ ++extern uint32_t DWC_CPU_TO_BE32(uint32_t *p); ++#define dwc_cpu_to_be32 DWC_CPU_TO_BE32 ++ ++/** Converts 32 bit little endian data to CPU byte ordering. */ ++extern uint32_t DWC_LE32_TO_CPU(uint32_t *p); ++#define dwc_le32_to_cpu DWC_LE32_TO_CPU ++ ++/** Converts 32 bit big endian data to CPU byte ordering. */ ++extern uint32_t DWC_BE32_TO_CPU(uint32_t *p); ++#define dwc_be32_to_cpu DWC_BE32_TO_CPU ++ ++/** Converts 16 bit data in CPU byte ordering to little endian. */ ++extern uint16_t DWC_CPU_TO_LE16(uint16_t *p); ++#define dwc_cpu_to_le16 DWC_CPU_TO_LE16 ++ ++/** Converts 16 bit data in CPU byte orderint to big endian. */ ++extern uint16_t DWC_CPU_TO_BE16(uint16_t *p); ++#define dwc_cpu_to_be16 DWC_CPU_TO_BE16 ++ ++/** Converts 16 bit little endian data to CPU byte ordering. */ ++extern uint16_t DWC_LE16_TO_CPU(uint16_t *p); ++#define dwc_le16_to_cpu DWC_LE16_TO_CPU ++ ++/** Converts 16 bit bi endian data to CPU byte ordering. */ ++extern uint16_t DWC_BE16_TO_CPU(uint16_t *p); ++#define dwc_be16_to_cpu DWC_BE16_TO_CPU ++ ++ ++/** @name Register Read/Write ++ * ++ * The following six functions should be implemented to read/write registers of ++ * 32-bit and 64-bit sizes. All modules use this to read/write register values. ++ * The reg value is a pointer to the register calculated from the void *base ++ * variable passed into the driver when it is started. */ ++ ++#ifdef DWC_LINUX ++/* Linux doesn't need any extra parameters for register read/write, so we ++ * just throw away the IO context parameter. ++ */ ++/** Reads the content of a 32-bit register. */ ++extern uint32_t DWC_READ_REG32(uint32_t volatile *reg); ++#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_) ++ ++/** Reads the content of a 64-bit register. */ ++extern uint64_t DWC_READ_REG64(uint64_t volatile *reg); ++#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_) ++ ++/** Writes to a 32-bit register. */ ++extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value); ++#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_) ++ ++/** Writes to a 64-bit register. */ ++extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value); ++#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_) ++ ++/** ++ * Modify bit values in a register. Using the ++ * algorithm: (reg_contents & ~clear_mask) | set_mask. ++ */ ++extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); ++#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_) ++extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask); ++#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_) ++ ++#endif /* DWC_LINUX */ ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++typedef struct dwc_ioctx { ++ struct device *dev; ++ bus_space_tag_t iot; ++ bus_space_handle_t ioh; ++} dwc_ioctx_t; ++ ++/** BSD needs two extra parameters for register read/write, so we pass ++ * them in using the IO context parameter. ++ */ ++/** Reads the content of a 32-bit register. */ ++extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg); ++#define dwc_read_reg32 DWC_READ_REG32 ++ ++/** Reads the content of a 64-bit register. */ ++extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg); ++#define dwc_read_reg64 DWC_READ_REG64 ++ ++/** Writes to a 32-bit register. */ ++extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value); ++#define dwc_write_reg32 DWC_WRITE_REG32 ++ ++/** Writes to a 64-bit register. */ ++extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value); ++#define dwc_write_reg64 DWC_WRITE_REG64 ++ ++/** ++ * Modify bit values in a register. Using the ++ * algorithm: (reg_contents & ~clear_mask) | set_mask. ++ */ ++extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); ++#define dwc_modify_reg32 DWC_MODIFY_REG32 ++extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask); ++#define dwc_modify_reg64 DWC_MODIFY_REG64 ++ ++#endif /* DWC_FREEBSD || DWC_NETBSD */ ++ ++/** @cond */ ++ ++/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the ++ * register writes. */ ++ ++#ifdef DWC_LINUX ++ ++# ifdef DWC_DEBUG_REGS ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ ++ return DWC_READ_REG32(&container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ ++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \ ++ &(((uint32_t*)container->regs->_reg)[num]), data); \ ++ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(_container_type *container) { \ ++ return DWC_READ_REG32(&container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ ++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ ++ DWC_WRITE_REG32(&container->regs->_reg, data); \ ++} ++ ++# else /* DWC_DEBUG_REGS */ ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ ++ return DWC_READ_REG32(&container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ ++ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(_container_type *container) { \ ++ return DWC_READ_REG32(&container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ ++ DWC_WRITE_REG32(&container->regs->_reg, data); \ ++} ++ ++# endif /* DWC_DEBUG_REGS */ ++ ++#endif /* DWC_LINUX */ ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++ ++# ifdef DWC_DEBUG_REGS ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \ ++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \ ++ &(((uint32_t*)container->regs->_reg)[num]), data); \ ++ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \ ++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ ++ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \ ++} ++ ++# else /* DWC_DEBUG_REGS */ ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \ ++ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \ ++ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \ ++} ++ ++# endif /* DWC_DEBUG_REGS */ ++ ++#endif /* DWC_FREEBSD || DWC_NETBSD */ ++ ++/** @endcond */ ++ ++ ++#ifdef DWC_CRYPTOLIB ++/** @name Crypto Functions ++ * ++ * These are the low-level cryptographic functions used by the driver. */ ++ ++/** Perform AES CBC */ ++extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out); ++#define dwc_aes_cbc DWC_AES_CBC ++ ++/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */ ++extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length); ++#define dwc_random_bytes DWC_RANDOM_BYTES ++ ++/** Perform the SHA-256 hash function */ ++extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out); ++#define dwc_sha256 DWC_SHA256 ++ ++/** Calculated the HMAC-SHA256 */ ++extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out); ++#define dwc_hmac_sha256 DWC_HMAC_SHA256 ++ ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/** @name Memory Allocation ++ * ++ * These function provide access to memory allocation. There are only 2 DMA ++ * functions and 3 Regular memory functions that need to be implemented. None ++ * of the memory debugging routines need to be implemented. The allocation ++ * routines all ZERO the contents of the memory. ++ * ++ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering. ++ * This checks for memory leaks, keeping track of alloc/free pairs. It also ++ * keeps track of how much memory the driver is using at any given time. */ ++ ++#define DWC_PAGE_SIZE 4096 ++#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff) ++#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0) ++ ++#define DWC_INVALID_DMA_ADDR 0x0 ++ ++#ifdef DWC_LINUX ++/** Type for a DMA address */ ++typedef dma_addr_t dwc_dma_t; ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++typedef bus_addr_t dwc_dma_t; ++#endif ++ ++#ifdef DWC_FREEBSD ++typedef struct dwc_dmactx { ++ struct device *dev; ++ bus_dma_tag_t dma_tag; ++ bus_dmamap_t dma_map; ++ bus_addr_t dma_paddr; ++ void *dma_vaddr; ++} dwc_dmactx_t; ++#endif ++ ++#ifdef DWC_NETBSD ++typedef struct dwc_dmactx { ++ struct device *dev; ++ bus_dma_tag_t dma_tag; ++ bus_dmamap_t dma_map; ++ bus_dma_segment_t segs[1]; ++ int nsegs; ++ bus_addr_t dma_paddr; ++ void *dma_vaddr; ++} dwc_dmactx_t; ++#endif ++ ++/* @todo these functions will be added in the future */ ++#if 0 ++/** ++ * Creates a DMA pool from which you can allocate DMA buffers. Buffers ++ * allocated from this pool will be guaranteed to meet the size, alignment, and ++ * boundary requirements specified. ++ * ++ * @param[in] size Specifies the size of the buffers that will be allocated from ++ * this pool. ++ * @param[in] align Specifies the byte alignment requirements of the buffers ++ * allocated from this pool. Must be a power of 2. ++ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from ++ * this pool must not cross. ++ * ++ * @returns A pointer to an internal opaque structure which is not to be ++ * accessed outside of these library functions. Use this handle to specify ++ * which pools to allocate/free DMA buffers from and also to destroy the pool, ++ * when you are done with it. ++ */ ++extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary); ++ ++/** ++ * Destroy a DMA pool. All buffers allocated from that pool must be freed first. ++ */ ++extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool); ++ ++/** ++ * Allocate a buffer from the specified DMA pool and zeros its contents. ++ */ ++extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr); ++ ++/** ++ * Free a previously allocated buffer from the DMA pool. ++ */ ++extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr); ++#endif ++ ++/** Allocates a DMA capable buffer and zeroes its contents. */ ++extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr); ++ ++/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */ ++extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr); ++ ++/** Frees a previously allocated buffer. */ ++extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr); ++ ++/** Allocates a block of memory and zeroes its contents. */ ++extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size); ++ ++/** Allocates a block of memory and zeroes its contents, in an atomic manner ++ * which can be used inside interrupt context. The size should be sufficiently ++ * small, a few KB at most, such that failures are not likely to occur. Can just call ++ * __DWC_ALLOC if it is atomic. */ ++extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size); ++ ++/** Frees a previously allocated buffer. */ ++extern void __DWC_FREE(void *mem_ctx, void *addr); ++ ++#ifndef DWC_DEBUG_MEMORY ++ ++#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_) ++#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_) ++#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_) ++ ++# ifdef DWC_LINUX ++#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_) ++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_) ++#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_) ++# endif ++ ++# if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++#define DWC_DMA_ALLOC __DWC_DMA_ALLOC ++#define DWC_DMA_FREE __DWC_DMA_FREE ++# endif ++extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line); ++ ++#else /* DWC_DEBUG_MEMORY */ ++ ++extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line); ++extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line); ++extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line); ++extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line); ++extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line); ++extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr, ++ dwc_dma_t dma_addr, char const *func, int line); ++ ++extern int dwc_memory_debug_start(void *mem_ctx); ++extern void dwc_memory_debug_stop(void); ++extern void dwc_memory_debug_report(void); ++ ++#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__) ++#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \ ++ __func__, __LINE__) ++#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__) ++ ++# ifdef DWC_LINUX ++#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \ ++ _virt_, _dma_, __func__, __LINE__) ++# endif ++ ++# if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \ ++ _virt_, _dma_, __func__, __LINE__) ++# endif ++ ++#endif /* DWC_DEBUG_MEMORY */ ++ ++#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_) ++#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_) ++#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_) ++ ++#ifdef DWC_LINUX ++/* Linux doesn't need any extra parameters for DMA buffer allocation, so we ++ * just throw away the DMA context parameter. ++ */ ++#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_) ++#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_) ++#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_) ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++/** BSD needs several extra parameters for DMA buffer allocation, so we pass ++ * them in using the DMA context parameter. ++ */ ++#define dwc_dma_alloc DWC_DMA_ALLOC ++#define dwc_dma_free DWC_DMA_FREE ++#endif ++ ++ ++/** @name Memory and String Processing */ ++ ++/** memset() clone */ ++extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size); ++#define dwc_memset DWC_MEMSET ++ ++/** memcpy() clone */ ++extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size); ++#define dwc_memcpy DWC_MEMCPY ++ ++/** memmove() clone */ ++extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size); ++#define dwc_memmove DWC_MEMMOVE ++ ++/** memcmp() clone */ ++extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size); ++#define dwc_memcmp DWC_MEMCMP ++ ++/** strcmp() clone */ ++extern int DWC_STRCMP(void *s1, void *s2); ++#define dwc_strcmp DWC_STRCMP ++ ++/** strncmp() clone */ ++extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size); ++#define dwc_strncmp DWC_STRNCMP ++ ++/** strlen() clone, for NULL terminated ASCII strings */ ++extern int DWC_STRLEN(char const *str); ++#define dwc_strlen DWC_STRLEN ++ ++/** strcpy() clone, for NULL terminated ASCII strings */ ++extern char *DWC_STRCPY(char *to, const char *from); ++#define dwc_strcpy DWC_STRCPY ++ ++/** strdup() clone. If you wish to use memory allocation debugging, this ++ * implementation of strdup should use the DWC_* memory routines instead of ++ * calling a predefined strdup. Otherwise the memory allocated by this routine ++ * will not be seen by the debugging routines. */ ++extern char *DWC_STRDUP(char const *str); ++#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_) ++ ++/** NOT an atoi() clone. Read the description carefully. Returns an integer ++ * converted from the string str in base 10 unless the string begins with a "0x" ++ * in which case it is base 16. String must be a NULL terminated sequence of ++ * ASCII characters and may optionally begin with whitespace, a + or -, and a ++ * "0x" prefix if base 16. The remaining characters must be valid digits for ++ * the number and end with a NULL character. If any invalid characters are ++ * encountered or it returns with a negative error code and the results of the ++ * conversion are undefined. On sucess it returns 0. Overflow conditions are ++ * undefined. An example implementation using atoi() can be referenced from the ++ * Linux implementation. */ ++extern int DWC_ATOI(const char *str, int32_t *value); ++#define dwc_atoi DWC_ATOI ++ ++/** Same as above but for unsigned. */ ++extern int DWC_ATOUI(const char *str, uint32_t *value); ++#define dwc_atoui DWC_ATOUI ++ ++#ifdef DWC_UTFLIB ++/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */ ++extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len); ++#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE ++#endif ++ ++ ++/** @name Wait queues ++ * ++ * Wait queues provide a means of synchronizing between threads or processes. A ++ * process can block on a waitq if some condition is not true, waiting for it to ++ * become true. When the waitq is triggered all waiting process will get ++ * unblocked and the condition will be check again. Waitqs should be triggered ++ * every time a condition can potentially change.*/ ++struct dwc_waitq; ++ ++/** Type for a waitq */ ++typedef struct dwc_waitq dwc_waitq_t; ++ ++/** The type of waitq condition callback function. This is called every time ++ * condition is evaluated. */ ++typedef int (*dwc_waitq_condition_t)(void *data); ++ ++/** Allocate a waitq */ ++extern dwc_waitq_t *DWC_WAITQ_ALLOC(void); ++#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC() ++ ++/** Free a waitq */ ++extern void DWC_WAITQ_FREE(dwc_waitq_t *wq); ++#define dwc_waitq_free DWC_WAITQ_FREE ++ ++/** Check the condition and if it is false, block on the waitq. When unblocked, check the ++ * condition again. The function returns when the condition becomes true. The return value ++ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */ ++extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data); ++#define dwc_waitq_wait DWC_WAITQ_WAIT ++ ++/** Check the condition and if it is false, block on the waitq. When unblocked, ++ * check the condition again. The function returns when the condition become ++ * true or the timeout has passed. The return value is 0 on condition true or ++ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on ++ * error. */ ++extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs); ++#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT ++ ++/** Trigger a waitq, unblocking all processes. This should be called whenever a condition ++ * has potentially changed. */ ++extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq); ++#define dwc_waitq_trigger DWC_WAITQ_TRIGGER ++ ++/** Unblock all processes waiting on the waitq with an ABORTED result. */ ++extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq); ++#define dwc_waitq_abort DWC_WAITQ_ABORT ++ ++ ++/** @name Threads ++ * ++ * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP ++ * whenever it is woken up, and then return. The DWC_THREAD_STOP function ++ * returns the value from the thread. ++ */ ++ ++struct dwc_thread; ++ ++/** Type for a thread */ ++typedef struct dwc_thread dwc_thread_t; ++ ++/** The thread function */ ++typedef int (*dwc_thread_function_t)(void *data); ++ ++/** Create a thread and start it running the thread_function. Returns a handle ++ * to the thread */ ++extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data); ++#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_) ++ ++/** Stops a thread. Return the value returned by the thread. Or will return ++ * DWC_ABORT if the thread never started. */ ++extern int DWC_THREAD_STOP(dwc_thread_t *thread); ++#define dwc_thread_stop DWC_THREAD_STOP ++ ++/** Signifies to the thread that it must stop. */ ++#ifdef DWC_LINUX ++/* Linux doesn't need any parameters for kthread_should_stop() */ ++extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void); ++#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP() ++ ++/* No thread_exit function in Linux */ ++#define dwc_thread_exit(_thrd_) ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++/** BSD needs the thread pointer for kthread_suspend_check() */ ++extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread); ++#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP ++ ++/** The thread must call this to exit. */ ++extern void DWC_THREAD_EXIT(dwc_thread_t *thread); ++#define dwc_thread_exit DWC_THREAD_EXIT ++#endif ++ ++ ++/** @name Work queues ++ * ++ * Workqs are used to queue a callback function to be called at some later time, ++ * in another thread. */ ++struct dwc_workq; ++ ++/** Type for a workq */ ++typedef struct dwc_workq dwc_workq_t; ++ ++/** The type of the callback function to be called. */ ++typedef void (*dwc_work_callback_t)(void *data); ++ ++/** Allocate a workq */ ++extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name); ++#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_) ++ ++/** Free a workq. All work must be completed before being freed. */ ++extern void DWC_WORKQ_FREE(dwc_workq_t *workq); ++#define dwc_workq_free DWC_WORKQ_FREE ++ ++/** Schedule a callback on the workq, passing in data. The function will be ++ * scheduled at some later time. */ ++extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb, ++ void *data, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 4, 5))); ++#else ++ ; ++#endif ++#define dwc_workq_schedule DWC_WORKQ_SCHEDULE ++ ++/** Schedule a callback on the workq, that will be called until at least ++ * given number miliseconds have passed. */ ++extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 5, 6))); ++#else ++ ; ++#endif ++#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED ++ ++/** The number of processes in the workq */ ++extern int DWC_WORKQ_PENDING(dwc_workq_t *workq); ++#define dwc_workq_pending DWC_WORKQ_PENDING ++ ++/** Blocks until all the work in the workq is complete or timed out. Returns < ++ * 0 on timeout. */ ++extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout); ++#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE ++ ++ ++/** @name Tasklets ++ * ++ */ ++struct dwc_tasklet; ++ ++/** Type for a tasklet */ ++typedef struct dwc_tasklet dwc_tasklet_t; ++ ++/** The type of the callback function to be called */ ++typedef void (*dwc_tasklet_callback_t)(void *data); ++ ++/** Allocates a tasklet */ ++extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data); ++#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_) ++ ++/** Frees a tasklet */ ++extern void DWC_TASK_FREE(dwc_tasklet_t *task); ++#define dwc_task_free DWC_TASK_FREE ++ ++/** Schedules a tasklet to run */ ++extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task); ++#define dwc_task_schedule DWC_TASK_SCHEDULE ++ ++extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task); ++#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE ++ ++/** @name Timer ++ * ++ * Callbacks must be small and atomic. ++ */ ++struct dwc_timer; ++ ++/** Type for a timer */ ++typedef struct dwc_timer dwc_timer_t; ++ ++/** The type of the callback function to be called */ ++typedef void (*dwc_timer_callback_t)(void *data); ++ ++/** Allocates a timer */ ++extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data); ++#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_) ++ ++/** Frees a timer */ ++extern void DWC_TIMER_FREE(dwc_timer_t *timer); ++#define dwc_timer_free DWC_TIMER_FREE ++ ++/** Schedules the timer to run at time ms from now. And will repeat at every ++ * repeat_interval msec therafter ++ * ++ * Modifies a timer that is still awaiting execution to a new expiration time. ++ * The mod_time is added to the old time. */ ++extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time); ++#define dwc_timer_schedule DWC_TIMER_SCHEDULE ++ ++/** Disables the timer from execution. */ ++extern void DWC_TIMER_CANCEL(dwc_timer_t *timer); ++#define dwc_timer_cancel DWC_TIMER_CANCEL ++ ++ ++/** @name Spinlocks ++ * ++ * These locks are used when the work between the lock/unlock is atomic and ++ * short. Interrupts are also disabled during the lock/unlock and thus they are ++ * suitable to lock between interrupt/non-interrupt context. They also lock ++ * between processes if you have multiple CPUs or Preemption. If you don't have ++ * multiple CPUS or Preemption, then the you can simply implement the ++ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because ++ * the work between the lock/unlock is atomic, the process context will never ++ * change, and so you never have to lock between processes. */ ++ ++struct dwc_spinlock; ++ ++/** Type for a spinlock */ ++typedef struct dwc_spinlock dwc_spinlock_t; ++ ++/** Type for the 'flags' argument to spinlock funtions */ ++typedef unsigned long dwc_irqflags_t; ++ ++/** Returns an initialized lock variable. This function should allocate and ++ * initialize the OS-specific data structure used for locking. This data ++ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should ++ * be freed by the DWC_FREE_LOCK when it is no longer used. ++ * ++ * For Linux Spinlock Debugging make it macro because the debugging routines use ++ * the symbol name to determine recursive locking. Using a wrapper function ++ * makes it falsely think recursive locking occurs. */ ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK) ++#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \ ++ lock = DWC_ALLOC(sizeof(spinlock_t)); \ ++ if (lock) { \ ++ spin_lock_init((spinlock_t *)lock); \ ++ } \ ++}) ++#else ++extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void); ++#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC() ++#endif ++ ++/** Frees an initialized lock variable. */ ++extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock); ++#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_) ++ ++/** Disables interrupts and blocks until it acquires the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ * @param flags Unsigned long for irq flags storage. ++ */ ++extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags); ++#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE ++ ++/** Re-enables the interrupt and releases the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ * @param flags Unsigned long for irq flags storage. Must be the same as was ++ * passed into DWC_LOCK. ++ */ ++extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags); ++#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE ++ ++/** Blocks until it acquires the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ */ ++extern void DWC_SPINLOCK(dwc_spinlock_t *lock); ++#define dwc_spinlock DWC_SPINLOCK ++ ++/** Releases the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ */ ++extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock); ++#define dwc_spinunlock DWC_SPINUNLOCK ++ ++ ++/** @name Mutexes ++ * ++ * Unlike spinlocks Mutexes lock only between processes and the work between the ++ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context. ++ */ ++ ++struct dwc_mutex; ++ ++/** Type for a mutex */ ++typedef struct dwc_mutex dwc_mutex_t; ++ ++/* For Linux Mutex Debugging make it inline because the debugging routines use ++ * the symbol to determine recursive locking. This makes it falsely think ++ * recursive locking occurs. */ ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES) ++#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \ ++ __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \ ++ mutex_init((struct mutex *)__mutexp); \ ++}) ++#endif ++ ++/** Allocate a mutex */ ++extern dwc_mutex_t *DWC_MUTEX_ALLOC(void); ++#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC() ++ ++/* For memory leak debugging when using Linux Mutex Debugging */ ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES) ++#define DWC_MUTEX_FREE(__mutexp) do { \ ++ mutex_destroy((struct mutex *)__mutexp); \ ++ DWC_FREE(__mutexp); \ ++} while(0) ++#else ++/** Free a mutex */ ++extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex); ++#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_) ++#endif ++ ++/** Lock a mutex */ ++extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_lock DWC_MUTEX_LOCK ++ ++/** Non-blocking lock returns 1 on successful lock. */ ++extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK ++ ++/** Unlock a mutex */ ++extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_unlock DWC_MUTEX_UNLOCK ++ ++ ++/** @name Time */ ++ ++/** Microsecond delay. ++ * ++ * @param usecs Microseconds to delay. ++ */ ++extern void DWC_UDELAY(uint32_t usecs); ++#define dwc_udelay DWC_UDELAY ++ ++/** Millisecond delay. ++ * ++ * @param msecs Milliseconds to delay. ++ */ ++extern void DWC_MDELAY(uint32_t msecs); ++#define dwc_mdelay DWC_MDELAY ++ ++/** Non-busy waiting. ++ * Sleeps for specified number of milliseconds. ++ * ++ * @param msecs Milliseconds to sleep. ++ */ ++extern void DWC_MSLEEP(uint32_t msecs); ++#define dwc_msleep DWC_MSLEEP ++ ++/** ++ * Returns number of milliseconds since boot. ++ */ ++extern uint32_t DWC_TIME(void); ++#define dwc_time DWC_TIME ++ ++ ++ ++ ++/* @mainpage DWC Portability and Common Library ++ * ++ * This is the documentation for the DWC Portability and Common Library. ++ * ++ * @section intro Introduction ++ * ++ * The DWC Portability library consists of wrapper calls and data structures to ++ * all low-level functions which are typically provided by the OS. The WUDEV ++ * driver uses only these functions. In order to port the WUDEV driver, only ++ * the functions in this library need to be re-implemented, with the same ++ * behavior as documented here. ++ * ++ * The Common library consists of higher level functions, which rely only on ++ * calling the functions from the DWC Portability library. These common ++ * routines are shared across modules. Some of the common libraries need to be ++ * used directly by the driver programmer when porting WUDEV. Such as the ++ * parameter and notification libraries. ++ * ++ * @section low Portability Library OS Wrapper Functions ++ * ++ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that ++ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of ++ * these functions are included in the dwc_os.h file. ++ * ++ * There are many functions here covering a wide array of OS services. Please ++ * see dwc_os.h for details, and implementation notes for each function. ++ * ++ * @section common Common Library Functions ++ * ++ * Any function starting with dwc and in all lowercase is a common library ++ * routine. These functions have a portable implementation and do not need to ++ * be reimplemented when porting. The common routines can be used by any ++ * driver, and some must be used by the end user to control the drivers. For ++ * example, you must use the Parameter common library in order to set the ++ * parameters in the WUDEV module. ++ * ++ * The common libraries consist of the following: ++ * ++ * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h ++ * - Parameters - Used internally and can be used by end-user. See dwc_params.h ++ * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h ++ * - Lists - Used internally and can be used by end-user. See dwc_list.h ++ * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h ++ * - Modpow - Used internally only. See dwc_modpow.h ++ * - DH - Used internally only. See dwc_dh.h ++ * - Crypto - Used internally only. See dwc_crypto.h ++ * ++ * ++ * @section prereq Prerequistes For dwc_os.h ++ * @subsection types Data Types ++ * ++ * The dwc_os.h file assumes that several low-level data types are pre defined for the ++ * compilation environment. These data types are: ++ * ++ * - uint8_t - unsigned 8-bit data type ++ * - int8_t - signed 8-bit data type ++ * - uint16_t - unsigned 16-bit data type ++ * - int16_t - signed 16-bit data type ++ * - uint32_t - unsigned 32-bit data type ++ * - int32_t - signed 32-bit data type ++ * - uint64_t - unsigned 64-bit data type ++ * - int64_t - signed 64-bit data type ++ * ++ * Ensure that these are defined before using dwc_os.h. The easiest way to do ++ * that is to modify the top of the file to include the appropriate header. ++ * This is already done for the Linux environment. If the DWC_LINUX macro is ++ * defined, the correct header will be added. A standard header is ++ * also used for environments where standard C headers are available. ++ * ++ * @subsection stdarg Variable Arguments ++ * ++ * Variable arguments are provided by a standard C header . it is ++ * available in Both the Linux and ANSI C enviornment. An equivalent must be ++ * provided in your enviornment in order to use dwc_os.h with the debug and ++ * tracing message functionality. ++ * ++ * @subsection thread Threading ++ * ++ * WUDEV Core must be run on an operating system that provides for multiple ++ * threads/processes. Threading can be implemented in many ways, even in ++ * embedded systems without an operating system. At the bare minimum, the ++ * system should be able to start any number of processes at any time to handle ++ * special work. It need not be a pre-emptive system. Process context can ++ * change upon a call to a blocking function. The hardware interrupt context ++ * that calls the module's ISR() function must be differentiable from process ++ * context, even if your processes are impemented via a hardware interrupt. ++ * Further locking mechanism between process must exist (or be implemented), and ++ * process context must have a way to disable interrupts for a period of time to ++ * lock them out. If all of this exists, the functions in dwc_os.h related to ++ * threading should be able to be implemented with the defined behavior. ++ * ++ */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_OS_H_ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_common_port/usb.h +@@ -0,0 +1,946 @@ ++/* ++ * Copyright (c) 1998 The NetBSD Foundation, Inc. ++ * All rights reserved. ++ * ++ * This code is derived from software contributed to The NetBSD Foundation ++ * by Lennart Augustsson (lennart@augustsson.net) at ++ * Carlstedt Research & Technology. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by the NetBSD ++ * Foundation, Inc. and its contributors. ++ * 4. Neither the name of The NetBSD Foundation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS ++ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* Modified by Synopsys, Inc, 12/12/2007 */ ++ ++ ++#ifndef _USB_H_ ++#define _USB_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++ * The USB records contain some unaligned little-endian word ++ * components. The U[SG]ETW macros take care of both the alignment ++ * and endian problem and should always be used to access non-byte ++ * values. ++ */ ++typedef u_int8_t uByte; ++typedef u_int8_t uWord[2]; ++typedef u_int8_t uDWord[4]; ++ ++#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h)) ++#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff } ++#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \ ++ ((x) >> 16) & 0xff, ((x) >> 24) & 0xff } ++ ++#if 1 ++#define UGETW(w) ((w)[0] | ((w)[1] << 8)) ++#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8)) ++#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24)) ++#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \ ++ (w)[1] = (u_int8_t)((v) >> 8), \ ++ (w)[2] = (u_int8_t)((v) >> 16), \ ++ (w)[3] = (u_int8_t)((v) >> 24)) ++#else ++/* ++ * On little-endian machines that can handle unanliged accesses ++ * (e.g. i386) these macros can be replaced by the following. ++ */ ++#define UGETW(w) (*(u_int16_t *)(w)) ++#define USETW(w,v) (*(u_int16_t *)(w) = (v)) ++#define UGETDW(w) (*(u_int32_t *)(w)) ++#define USETDW(w,v) (*(u_int32_t *)(w) = (v)) ++#endif ++ ++/* ++ * Macros for accessing UAS IU fields, which are big-endian ++ */ ++#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l)) ++#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff } ++#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \ ++ ((x) >> 8) & 0xff, (x) & 0xff } ++#define IUGETW(w) (((w)[0] << 8) | (w)[1]) ++#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v)) ++#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3]) ++#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \ ++ (w)[1] = (u_int8_t)((v) >> 16), \ ++ (w)[2] = (u_int8_t)((v) >> 8), \ ++ (w)[3] = (u_int8_t)(v)) ++ ++#define UPACKED __attribute__((__packed__)) ++ ++typedef struct { ++ uByte bmRequestType; ++ uByte bRequest; ++ uWord wValue; ++ uWord wIndex; ++ uWord wLength; ++} UPACKED usb_device_request_t; ++ ++#define UT_GET_DIR(a) ((a) & 0x80) ++#define UT_WRITE 0x00 ++#define UT_READ 0x80 ++ ++#define UT_GET_TYPE(a) ((a) & 0x60) ++#define UT_STANDARD 0x00 ++#define UT_CLASS 0x20 ++#define UT_VENDOR 0x40 ++ ++#define UT_GET_RECIPIENT(a) ((a) & 0x1f) ++#define UT_DEVICE 0x00 ++#define UT_INTERFACE 0x01 ++#define UT_ENDPOINT 0x02 ++#define UT_OTHER 0x03 ++ ++#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE) ++#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE) ++#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT) ++#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE) ++#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE) ++#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT) ++#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE) ++#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE) ++#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER) ++#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT) ++#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE) ++#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE) ++#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER) ++#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT) ++#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE) ++#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE) ++#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER) ++#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT) ++#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE) ++#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE) ++#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER) ++#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT) ++ ++/* Requests */ ++#define UR_GET_STATUS 0x00 ++#define USTAT_STANDARD_STATUS 0x00 ++#define WUSTAT_WUSB_FEATURE 0x01 ++#define WUSTAT_CHANNEL_INFO 0x02 ++#define WUSTAT_RECEIVED_DATA 0x03 ++#define WUSTAT_MAS_AVAILABILITY 0x04 ++#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05 ++#define UR_CLEAR_FEATURE 0x01 ++#define UR_SET_FEATURE 0x03 ++#define UR_SET_AND_TEST_FEATURE 0x0c ++#define UR_SET_ADDRESS 0x05 ++#define UR_GET_DESCRIPTOR 0x06 ++#define UDESC_DEVICE 0x01 ++#define UDESC_CONFIG 0x02 ++#define UDESC_STRING 0x03 ++#define UDESC_INTERFACE 0x04 ++#define UDESC_ENDPOINT 0x05 ++#define UDESC_SS_USB_COMPANION 0x30 ++#define UDESC_DEVICE_QUALIFIER 0x06 ++#define UDESC_OTHER_SPEED_CONFIGURATION 0x07 ++#define UDESC_INTERFACE_POWER 0x08 ++#define UDESC_OTG 0x09 ++#define WUDESC_SECURITY 0x0c ++#define WUDESC_KEY 0x0d ++#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf) ++#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4) ++#define WUD_KEY_TYPE_ASSOC 0x01 ++#define WUD_KEY_TYPE_GTK 0x02 ++#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6) ++#define WUD_KEY_ORIGIN_HOST 0x00 ++#define WUD_KEY_ORIGIN_DEVICE 0x01 ++#define WUDESC_ENCRYPTION_TYPE 0x0e ++#define WUDESC_BOS 0x0f ++#define WUDESC_DEVICE_CAPABILITY 0x10 ++#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11 ++#define UDESC_BOS 0x0f ++#define UDESC_DEVICE_CAPABILITY 0x10 ++#define UDESC_CS_DEVICE 0x21 /* class specific */ ++#define UDESC_CS_CONFIG 0x22 ++#define UDESC_CS_STRING 0x23 ++#define UDESC_CS_INTERFACE 0x24 ++#define UDESC_CS_ENDPOINT 0x25 ++#define UDESC_HUB 0x29 ++#define UR_SET_DESCRIPTOR 0x07 ++#define UR_GET_CONFIG 0x08 ++#define UR_SET_CONFIG 0x09 ++#define UR_GET_INTERFACE 0x0a ++#define UR_SET_INTERFACE 0x0b ++#define UR_SYNCH_FRAME 0x0c ++#define WUR_SET_ENCRYPTION 0x0d ++#define WUR_GET_ENCRYPTION 0x0e ++#define WUR_SET_HANDSHAKE 0x0f ++#define WUR_GET_HANDSHAKE 0x10 ++#define WUR_SET_CONNECTION 0x11 ++#define WUR_SET_SECURITY_DATA 0x12 ++#define WUR_GET_SECURITY_DATA 0x13 ++#define WUR_SET_WUSB_DATA 0x14 ++#define WUDATA_DRPIE_INFO 0x01 ++#define WUDATA_TRANSMIT_DATA 0x02 ++#define WUDATA_TRANSMIT_PARAMS 0x03 ++#define WUDATA_RECEIVE_PARAMS 0x04 ++#define WUDATA_TRANSMIT_POWER 0x05 ++#define WUR_LOOPBACK_DATA_WRITE 0x15 ++#define WUR_LOOPBACK_DATA_READ 0x16 ++#define WUR_SET_INTERFACE_DS 0x17 ++ ++/* Feature numbers */ ++#define UF_ENDPOINT_HALT 0 ++#define UF_DEVICE_REMOTE_WAKEUP 1 ++#define UF_TEST_MODE 2 ++#define UF_DEVICE_B_HNP_ENABLE 3 ++#define UF_DEVICE_A_HNP_SUPPORT 4 ++#define UF_DEVICE_A_ALT_HNP_SUPPORT 5 ++#define WUF_WUSB 3 ++#define WUF_TX_DRPIE 0x0 ++#define WUF_DEV_XMIT_PACKET 0x1 ++#define WUF_COUNT_PACKETS 0x2 ++#define WUF_CAPTURE_PACKETS 0x3 ++#define UF_FUNCTION_SUSPEND 0 ++#define UF_U1_ENABLE 48 ++#define UF_U2_ENABLE 49 ++#define UF_LTM_ENABLE 50 ++ ++/* Class requests from the USB 2.0 hub spec, table 11-15 */ ++#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE) ++#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE) ++#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR) ++#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS) ++#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS) ++#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE) ++#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE) ++#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE) ++ ++#ifdef _MSC_VER ++#include ++#endif ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDescriptorSubtype; ++} UPACKED usb_descriptor_t; ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++} UPACKED usb_descriptor_header_t; ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bcdUSB; ++#define UD_USB_2_0 0x0200 ++#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0) ++ uByte bDeviceClass; ++ uByte bDeviceSubClass; ++ uByte bDeviceProtocol; ++ uByte bMaxPacketSize; ++ /* The fields below are not part of the initial descriptor. */ ++ uWord idVendor; ++ uWord idProduct; ++ uWord bcdDevice; ++ uByte iManufacturer; ++ uByte iProduct; ++ uByte iSerialNumber; ++ uByte bNumConfigurations; ++} UPACKED usb_device_descriptor_t; ++#define USB_DEVICE_DESCRIPTOR_SIZE 18 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumInterface; ++ uByte bConfigurationValue; ++ uByte iConfiguration; ++#define UC_ATT_ONE (1 << 7) /* must be set */ ++#define UC_ATT_SELFPOWER (1 << 6) /* self powered */ ++#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */ ++#define UC_ATT_BATTERY (1 << 4) /* battery powered */ ++ uByte bmAttributes; ++#define UC_BUS_POWERED 0x80 ++#define UC_SELF_POWERED 0x40 ++#define UC_REMOTE_WAKEUP 0x20 ++ uByte bMaxPower; /* max current in 2 mA units */ ++#define UC_POWER_FACTOR 2 ++} UPACKED usb_config_descriptor_t; ++#define USB_CONFIG_DESCRIPTOR_SIZE 9 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bInterfaceNumber; ++ uByte bAlternateSetting; ++ uByte bNumEndpoints; ++ uByte bInterfaceClass; ++ uByte bInterfaceSubClass; ++ uByte bInterfaceProtocol; ++ uByte iInterface; ++} UPACKED usb_interface_descriptor_t; ++#define USB_INTERFACE_DESCRIPTOR_SIZE 9 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bEndpointAddress; ++#define UE_GET_DIR(a) ((a) & 0x80) ++#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7)) ++#define UE_DIR_IN 0x80 ++#define UE_DIR_OUT 0x00 ++#define UE_ADDR 0x0f ++#define UE_GET_ADDR(a) ((a) & UE_ADDR) ++ uByte bmAttributes; ++#define UE_XFERTYPE 0x03 ++#define UE_CONTROL 0x00 ++#define UE_ISOCHRONOUS 0x01 ++#define UE_BULK 0x02 ++#define UE_INTERRUPT 0x03 ++#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE) ++#define UE_ISO_TYPE 0x0c ++#define UE_ISO_ASYNC 0x04 ++#define UE_ISO_ADAPT 0x08 ++#define UE_ISO_SYNC 0x0c ++#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE) ++ uWord wMaxPacketSize; ++ uByte bInterval; ++} UPACKED usb_endpoint_descriptor_t; ++#define USB_ENDPOINT_DESCRIPTOR_SIZE 7 ++ ++typedef struct ss_endpoint_companion_descriptor { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bMaxBurst; ++#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f) ++#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f)) ++#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03) ++#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03)) ++ uByte bmAttributes; ++ uWord wBytesPerInterval; ++} UPACKED ss_endpoint_companion_descriptor_t; ++#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bString[127]; ++} UPACKED usb_string_descriptor_t; ++#define USB_MAX_STRING_LEN 128 ++#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */ ++ ++/* Hub specific request */ ++#define UR_GET_BUS_STATE 0x02 ++#define UR_CLEAR_TT_BUFFER 0x08 ++#define UR_RESET_TT 0x09 ++#define UR_GET_TT_STATE 0x0a ++#define UR_STOP_TT 0x0b ++ ++/* Hub features */ ++#define UHF_C_HUB_LOCAL_POWER 0 ++#define UHF_C_HUB_OVER_CURRENT 1 ++#define UHF_PORT_CONNECTION 0 ++#define UHF_PORT_ENABLE 1 ++#define UHF_PORT_SUSPEND 2 ++#define UHF_PORT_OVER_CURRENT 3 ++#define UHF_PORT_RESET 4 ++#define UHF_PORT_L1 5 ++#define UHF_PORT_POWER 8 ++#define UHF_PORT_LOW_SPEED 9 ++#define UHF_PORT_HIGH_SPEED 10 ++#define UHF_C_PORT_CONNECTION 16 ++#define UHF_C_PORT_ENABLE 17 ++#define UHF_C_PORT_SUSPEND 18 ++#define UHF_C_PORT_OVER_CURRENT 19 ++#define UHF_C_PORT_RESET 20 ++#define UHF_C_PORT_L1 23 ++#define UHF_PORT_TEST 21 ++#define UHF_PORT_INDICATOR 22 ++ ++typedef struct { ++ uByte bDescLength; ++ uByte bDescriptorType; ++ uByte bNbrPorts; ++ uWord wHubCharacteristics; ++#define UHD_PWR 0x0003 ++#define UHD_PWR_GANGED 0x0000 ++#define UHD_PWR_INDIVIDUAL 0x0001 ++#define UHD_PWR_NO_SWITCH 0x0002 ++#define UHD_COMPOUND 0x0004 ++#define UHD_OC 0x0018 ++#define UHD_OC_GLOBAL 0x0000 ++#define UHD_OC_INDIVIDUAL 0x0008 ++#define UHD_OC_NONE 0x0010 ++#define UHD_TT_THINK 0x0060 ++#define UHD_TT_THINK_8 0x0000 ++#define UHD_TT_THINK_16 0x0020 ++#define UHD_TT_THINK_24 0x0040 ++#define UHD_TT_THINK_32 0x0060 ++#define UHD_PORT_IND 0x0080 ++ uByte bPwrOn2PwrGood; /* delay in 2 ms units */ ++#define UHD_PWRON_FACTOR 2 ++ uByte bHubContrCurrent; ++ uByte DeviceRemovable[32]; /* max 255 ports */ ++#define UHD_NOT_REMOV(desc, i) \ ++ (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1) ++ /* deprecated */ uByte PortPowerCtrlMask[1]; ++} UPACKED usb_hub_descriptor_t; ++#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */ ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bcdUSB; ++ uByte bDeviceClass; ++ uByte bDeviceSubClass; ++ uByte bDeviceProtocol; ++ uByte bMaxPacketSize0; ++ uByte bNumConfigurations; ++ uByte bReserved; ++} UPACKED usb_device_qualifier_t; ++#define USB_DEVICE_QUALIFIER_SIZE 10 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bmAttributes; ++#define UOTG_SRP 0x01 ++#define UOTG_HNP 0x02 ++} UPACKED usb_otg_descriptor_t; ++ ++/* OTG feature selectors */ ++#define UOTG_B_HNP_ENABLE 3 ++#define UOTG_A_HNP_SUPPORT 4 ++#define UOTG_A_ALT_HNP_SUPPORT 5 ++ ++typedef struct { ++ uWord wStatus; ++/* Device status flags */ ++#define UDS_SELF_POWERED 0x0001 ++#define UDS_REMOTE_WAKEUP 0x0002 ++/* Endpoint status flags */ ++#define UES_HALT 0x0001 ++} UPACKED usb_status_t; ++ ++typedef struct { ++ uWord wHubStatus; ++#define UHS_LOCAL_POWER 0x0001 ++#define UHS_OVER_CURRENT 0x0002 ++ uWord wHubChange; ++} UPACKED usb_hub_status_t; ++ ++typedef struct { ++ uWord wPortStatus; ++#define UPS_CURRENT_CONNECT_STATUS 0x0001 ++#define UPS_PORT_ENABLED 0x0002 ++#define UPS_SUSPEND 0x0004 ++#define UPS_OVERCURRENT_INDICATOR 0x0008 ++#define UPS_RESET 0x0010 ++#define UPS_PORT_POWER 0x0100 ++#define UPS_LOW_SPEED 0x0200 ++#define UPS_HIGH_SPEED 0x0400 ++#define UPS_PORT_TEST 0x0800 ++#define UPS_PORT_INDICATOR 0x1000 ++ uWord wPortChange; ++#define UPS_C_CONNECT_STATUS 0x0001 ++#define UPS_C_PORT_ENABLED 0x0002 ++#define UPS_C_SUSPEND 0x0004 ++#define UPS_C_OVERCURRENT_INDICATOR 0x0008 ++#define UPS_C_PORT_RESET 0x0010 ++} UPACKED usb_port_status_t; ++ ++#ifdef _MSC_VER ++#include ++#endif ++ ++/* Device class codes */ ++#define UDCLASS_IN_INTERFACE 0x00 ++#define UDCLASS_COMM 0x02 ++#define UDCLASS_HUB 0x09 ++#define UDSUBCLASS_HUB 0x00 ++#define UDPROTO_FSHUB 0x00 ++#define UDPROTO_HSHUBSTT 0x01 ++#define UDPROTO_HSHUBMTT 0x02 ++#define UDCLASS_DIAGNOSTIC 0xdc ++#define UDCLASS_WIRELESS 0xe0 ++#define UDSUBCLASS_RF 0x01 ++#define UDPROTO_BLUETOOTH 0x01 ++#define UDCLASS_VENDOR 0xff ++ ++/* Interface class codes */ ++#define UICLASS_UNSPEC 0x00 ++ ++#define UICLASS_AUDIO 0x01 ++#define UISUBCLASS_AUDIOCONTROL 1 ++#define UISUBCLASS_AUDIOSTREAM 2 ++#define UISUBCLASS_MIDISTREAM 3 ++ ++#define UICLASS_CDC 0x02 /* communication */ ++#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1 ++#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2 ++#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3 ++#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4 ++#define UISUBCLASS_CAPI_CONTROLMODEL 5 ++#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6 ++#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7 ++#define UIPROTO_CDC_AT 1 ++ ++#define UICLASS_HID 0x03 ++#define UISUBCLASS_BOOT 1 ++#define UIPROTO_BOOT_KEYBOARD 1 ++ ++#define UICLASS_PHYSICAL 0x05 ++ ++#define UICLASS_IMAGE 0x06 ++ ++#define UICLASS_PRINTER 0x07 ++#define UISUBCLASS_PRINTER 1 ++#define UIPROTO_PRINTER_UNI 1 ++#define UIPROTO_PRINTER_BI 2 ++#define UIPROTO_PRINTER_1284 3 ++ ++#define UICLASS_MASS 0x08 ++#define UISUBCLASS_RBC 1 ++#define UISUBCLASS_SFF8020I 2 ++#define UISUBCLASS_QIC157 3 ++#define UISUBCLASS_UFI 4 ++#define UISUBCLASS_SFF8070I 5 ++#define UISUBCLASS_SCSI 6 ++#define UIPROTO_MASS_CBI_I 0 ++#define UIPROTO_MASS_CBI 1 ++#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */ ++#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */ ++ ++#define UICLASS_HUB 0x09 ++#define UISUBCLASS_HUB 0 ++#define UIPROTO_FSHUB 0 ++#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */ ++#define UIPROTO_HSHUBMTT 1 ++ ++#define UICLASS_CDC_DATA 0x0a ++#define UISUBCLASS_DATA 0 ++#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */ ++#define UIPROTO_DATA_HDLC 0x31 /* HDLC */ ++#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */ ++#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */ ++#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */ ++#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */ ++#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */ ++#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */ ++#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */ ++#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */ ++#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */ ++#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/ ++#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */ ++ ++#define UICLASS_SMARTCARD 0x0b ++ ++/*#define UICLASS_FIRM_UPD 0x0c*/ ++ ++#define UICLASS_SECURITY 0x0d ++ ++#define UICLASS_DIAGNOSTIC 0xdc ++ ++#define UICLASS_WIRELESS 0xe0 ++#define UISUBCLASS_RF 0x01 ++#define UIPROTO_BLUETOOTH 0x01 ++ ++#define UICLASS_APPL_SPEC 0xfe ++#define UISUBCLASS_FIRMWARE_DOWNLOAD 1 ++#define UISUBCLASS_IRDA 2 ++#define UIPROTO_IRDA 0 ++ ++#define UICLASS_VENDOR 0xff ++ ++#define USB_HUB_MAX_DEPTH 5 ++ ++/* ++ * Minimum time a device needs to be powered down to go through ++ * a power cycle. XXX Are these time in the spec? ++ */ ++#define USB_POWER_DOWN_TIME 200 /* ms */ ++#define USB_PORT_POWER_DOWN_TIME 100 /* ms */ ++ ++#if 0 ++/* These are the values from the spec. */ ++#define USB_PORT_RESET_DELAY 10 /* ms */ ++#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */ ++#define USB_PORT_RESET_RECOVERY 10 /* ms */ ++#define USB_PORT_POWERUP_DELAY 100 /* ms */ ++#define USB_SET_ADDRESS_SETTLE 2 /* ms */ ++#define USB_RESUME_DELAY (20*5) /* ms */ ++#define USB_RESUME_WAIT 10 /* ms */ ++#define USB_RESUME_RECOVERY 10 /* ms */ ++#define USB_EXTRA_POWER_UP_TIME 0 /* ms */ ++#else ++/* Allow for marginal (i.e. non-conforming) devices. */ ++#define USB_PORT_RESET_DELAY 50 /* ms */ ++#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */ ++#define USB_PORT_RESET_RECOVERY 250 /* ms */ ++#define USB_PORT_POWERUP_DELAY 300 /* ms */ ++#define USB_SET_ADDRESS_SETTLE 10 /* ms */ ++#define USB_RESUME_DELAY (50*5) /* ms */ ++#define USB_RESUME_WAIT 50 /* ms */ ++#define USB_RESUME_RECOVERY 50 /* ms */ ++#define USB_EXTRA_POWER_UP_TIME 20 /* ms */ ++#endif ++ ++#define USB_MIN_POWER 100 /* mA */ ++#define USB_MAX_POWER 500 /* mA */ ++ ++#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/ ++ ++#define USB_UNCONFIG_NO 0 ++#define USB_UNCONFIG_INDEX (-1) ++ ++/*** ioctl() related stuff ***/ ++ ++struct usb_ctl_request { ++ int ucr_addr; ++ usb_device_request_t ucr_request; ++ void *ucr_data; ++ int ucr_flags; ++#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */ ++ int ucr_actlen; /* actual length transferred */ ++}; ++ ++struct usb_alt_interface { ++ int uai_config_index; ++ int uai_interface_index; ++ int uai_alt_no; ++}; ++ ++#define USB_CURRENT_CONFIG_INDEX (-1) ++#define USB_CURRENT_ALT_INDEX (-1) ++ ++struct usb_config_desc { ++ int ucd_config_index; ++ usb_config_descriptor_t ucd_desc; ++}; ++ ++struct usb_interface_desc { ++ int uid_config_index; ++ int uid_interface_index; ++ int uid_alt_index; ++ usb_interface_descriptor_t uid_desc; ++}; ++ ++struct usb_endpoint_desc { ++ int ued_config_index; ++ int ued_interface_index; ++ int ued_alt_index; ++ int ued_endpoint_index; ++ usb_endpoint_descriptor_t ued_desc; ++}; ++ ++struct usb_full_desc { ++ int ufd_config_index; ++ u_int ufd_size; ++ u_char *ufd_data; ++}; ++ ++struct usb_string_desc { ++ int usd_string_index; ++ int usd_language_id; ++ usb_string_descriptor_t usd_desc; ++}; ++ ++struct usb_ctl_report_desc { ++ int ucrd_size; ++ u_char ucrd_data[1024]; /* filled data size will vary */ ++}; ++ ++typedef struct { u_int32_t cookie; } usb_event_cookie_t; ++ ++#define USB_MAX_DEVNAMES 4 ++#define USB_MAX_DEVNAMELEN 16 ++struct usb_device_info { ++ u_int8_t udi_bus; ++ u_int8_t udi_addr; /* device address */ ++ usb_event_cookie_t udi_cookie; ++ char udi_product[USB_MAX_STRING_LEN]; ++ char udi_vendor[USB_MAX_STRING_LEN]; ++ char udi_release[8]; ++ u_int16_t udi_productNo; ++ u_int16_t udi_vendorNo; ++ u_int16_t udi_releaseNo; ++ u_int8_t udi_class; ++ u_int8_t udi_subclass; ++ u_int8_t udi_protocol; ++ u_int8_t udi_config; ++ u_int8_t udi_speed; ++#define USB_SPEED_UNKNOWN 0 ++#define USB_SPEED_LOW 1 ++#define USB_SPEED_FULL 2 ++#define USB_SPEED_HIGH 3 ++#define USB_SPEED_VARIABLE 4 ++#define USB_SPEED_SUPER 5 ++ int udi_power; /* power consumption in mA, 0 if selfpowered */ ++ int udi_nports; ++ char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN]; ++ u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */ ++#define USB_PORT_ENABLED 0xff ++#define USB_PORT_SUSPENDED 0xfe ++#define USB_PORT_POWERED 0xfd ++#define USB_PORT_DISABLED 0xfc ++}; ++ ++struct usb_ctl_report { ++ int ucr_report; ++ u_char ucr_data[1024]; /* filled data size will vary */ ++}; ++ ++struct usb_device_stats { ++ u_long uds_requests[4]; /* indexed by transfer type UE_* */ ++}; ++ ++#define WUSB_MIN_IE 0x80 ++#define WUSB_WCTA_IE 0x80 ++#define WUSB_WCONNECTACK_IE 0x81 ++#define WUSB_WHOSTINFO_IE 0x82 ++#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3) ++#define WUHI_CA_RECONN 0x00 ++#define WUHI_CA_LIMITED 0x01 ++#define WUHI_CA_ALL 0x03 ++#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3) ++#define WUSB_WCHCHANGEANNOUNCE_IE 0x83 ++#define WUSB_WDEV_DISCONNECT_IE 0x84 ++#define WUSB_WHOST_DISCONNECT_IE 0x85 ++#define WUSB_WRELEASE_CHANNEL_IE 0x86 ++#define WUSB_WWORK_IE 0x87 ++#define WUSB_WCHANNEL_STOP_IE 0x88 ++#define WUSB_WDEV_KEEPALIVE_IE 0x89 ++#define WUSB_WISOCH_DISCARD_IE 0x8A ++#define WUSB_WRESETDEVICE_IE 0x8B ++#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C ++#define WUSB_MAX_IE 0x8C ++ ++/* Device Notification Types */ ++ ++#define WUSB_DN_MIN 0x01 ++#define WUSB_DN_CONNECT 0x01 ++# define WUSB_DA_OLDCONN 0x00 ++# define WUSB_DA_NEWCONN 0x01 ++# define WUSB_DA_SELF_BEACON 0x02 ++# define WUSB_DA_DIR_BEACON 0x04 ++# define WUSB_DA_NO_BEACON 0x06 ++#define WUSB_DN_DISCONNECT 0x02 ++#define WUSB_DN_EPRDY 0x03 ++#define WUSB_DN_MASAVAILCHANGED 0x04 ++#define WUSB_DN_REMOTEWAKEUP 0x05 ++#define WUSB_DN_SLEEP 0x06 ++#define WUSB_DN_ALIVE 0x07 ++#define WUSB_DN_MAX 0x07 ++ ++#ifdef _MSC_VER ++#include ++#endif ++ ++/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */ ++typedef struct wusb_hndshk_data { ++ uByte bMessageNumber; ++ uByte bStatus; ++ uByte tTKID[3]; ++ uByte bReserved; ++ uByte CDID[16]; ++ uByte Nonce[16]; ++ uByte MIC[8]; ++} UPACKED wusb_hndshk_data_t; ++#define WUSB_HANDSHAKE_LEN_FOR_MIC 38 ++ ++/* WUSB Connection Context */ ++typedef struct wusb_conn_context { ++ uByte CHID [16]; ++ uByte CDID [16]; ++ uByte CK [16]; ++} UPACKED wusb_conn_context_t; ++ ++/* WUSB Security Descriptor */ ++typedef struct wusb_security_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumEncryptionTypes; ++} UPACKED wusb_security_desc_t; ++ ++/* WUSB Encryption Type Descriptor */ ++typedef struct wusb_encrypt_type_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ ++ uByte bEncryptionType; ++#define WUETD_UNSECURE 0 ++#define WUETD_WIRED 1 ++#define WUETD_CCM_1 2 ++#define WUETD_RSA_1 3 ++ ++ uByte bEncryptionValue; ++ uByte bAuthKeyIndex; ++} UPACKED wusb_encrypt_type_desc_t; ++ ++/* WUSB Key Descriptor */ ++typedef struct wusb_key_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte tTKID[3]; ++ uByte bReserved; ++ uByte KeyData[1]; /* variable length */ ++} UPACKED wusb_key_desc_t; ++ ++/* WUSB BOS Descriptor (Binary device Object Store) */ ++typedef struct wusb_bos_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumDeviceCaps; ++} UPACKED wusb_bos_desc_t; ++ ++#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02 ++typedef struct usb_dev_cap_20_ext_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++#define USB_20_EXT_LPM 0x02 ++ uDWord bmAttributes; ++} UPACKED usb_dev_cap_20_ext_desc_t; ++ ++#define USB_DEVICE_CAPABILITY_SS_USB 0x03 ++typedef struct usb_dev_cap_ss_usb { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++#define USB_DC_SS_USB_LTM_CAPABLE 0x02 ++ uByte bmAttributes; ++#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01 ++#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02 ++#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04 ++#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08 ++ uWord wSpeedsSupported; ++ uByte bFunctionalitySupport; ++ uByte bU1DevExitLat; ++ uWord wU2DevExitLat; ++} UPACKED usb_dev_cap_ss_usb_t; ++ ++#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04 ++typedef struct usb_dev_cap_container_id { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte bReserved; ++ uByte containerID[16]; ++} UPACKED usb_dev_cap_container_id_t; ++ ++/* Device Capability Type Codes */ ++#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01 ++ ++/* Device Capability Descriptor */ ++typedef struct wusb_dev_cap_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte caps[1]; /* Variable length */ ++} UPACKED wusb_dev_cap_desc_t; ++ ++/* Device Capability Descriptor */ ++typedef struct wusb_dev_cap_uwb_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte bmAttributes; ++ uWord wPHYRates; /* Bitmap */ ++ uByte bmTFITXPowerInfo; ++ uByte bmFFITXPowerInfo; ++ uWord bmBandGroup; ++ uByte bReserved; ++} UPACKED wusb_dev_cap_uwb_desc_t; ++ ++/* Wireless USB Endpoint Companion Descriptor */ ++typedef struct wusb_endpoint_companion_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bMaxBurst; ++ uByte bMaxSequence; ++ uWord wMaxStreamDelay; ++ uWord wOverTheAirPacketSize; ++ uByte bOverTheAirInterval; ++ uByte bmCompAttributes; ++} UPACKED wusb_endpoint_companion_desc_t; ++ ++/* Wireless USB Numeric Association M1 Data Structure */ ++typedef struct wusb_m1_data { ++ uByte version; ++ uWord langId; ++ uByte deviceFriendlyNameLength; ++ uByte sha_256_m3[32]; ++ uByte deviceFriendlyName[256]; ++} UPACKED wusb_m1_data_t; ++ ++typedef struct wusb_m2_data { ++ uByte version; ++ uWord langId; ++ uByte hostFriendlyNameLength; ++ uByte pkh[384]; ++ uByte hostFriendlyName[256]; ++} UPACKED wusb_m2_data_t; ++ ++typedef struct wusb_m3_data { ++ uByte pkd[384]; ++ uByte nd; ++} UPACKED wusb_m3_data_t; ++ ++typedef struct wusb_m4_data { ++ uDWord _attributeTypeIdAndLength_1; ++ uWord associationTypeId; ++ ++ uDWord _attributeTypeIdAndLength_2; ++ uWord associationSubTypeId; ++ ++ uDWord _attributeTypeIdAndLength_3; ++ uDWord length; ++ ++ uDWord _attributeTypeIdAndLength_4; ++ uDWord associationStatus; ++ ++ uDWord _attributeTypeIdAndLength_5; ++ uByte chid[16]; ++ ++ uDWord _attributeTypeIdAndLength_6; ++ uByte cdid[16]; ++ ++ uDWord _attributeTypeIdAndLength_7; ++ uByte bandGroups[2]; ++} UPACKED wusb_m4_data_t; ++ ++#ifdef _MSC_VER ++#include ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _USB_H_ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/Makefile +@@ -0,0 +1,82 @@ ++# ++# Makefile for DWC_otg Highspeed USB controller driver ++# ++ ++ifneq ($(KERNELRELEASE),) ++ ++# Use the BUS_INTERFACE variable to compile the software for either ++# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus. ++ifeq ($(BUS_INTERFACE),) ++# BUS_INTERFACE = -DPCI_INTERFACE ++# BUS_INTERFACE = -DLM_INTERFACE ++ BUS_INTERFACE = -DPLATFORM_INTERFACE ++endif ++ ++#ccflags-y += -DDEBUG ++#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs ++ ++# Use one of the following flags to compile the software in host-only or ++# device-only mode. ++#ccflags-y += -DDWC_HOST_ONLY ++#ccflags-y += -DDWC_DEVICE_ONLY ++ ++ccflags-y += -Dlinux -DDWC_HS_ELECT_TST ++#ccflags-y += -DDWC_EN_ISOC ++ccflags-y += -I$(obj)/../dwc_common_port ++#ccflags-y += -I$(PORTLIB) ++ccflags-y += -DDWC_LINUX ++ccflags-y += $(CFI) ++ccflags-y += $(BUS_INTERFACE) ++#ccflags-y += -DDWC_DEV_SRPCAP ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o ++ ++dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o ++dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o ++dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o ++dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o ++dwc_otg-objs += dwc_otg_adp.o ++dwc_otg-objs += dwc_otg_fiq_fsm.o ++dwc_otg-objs += dwc_otg_fiq_stub.o ++ifneq ($(CFI),) ++dwc_otg-objs += dwc_otg_cfi.o ++endif ++ ++kernrelwd := $(subst ., ,$(KERNELRELEASE)) ++kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) ++ ++ifneq ($(kernrel3),2.6.20) ++ccflags-y += $(CPPFLAGS) ++endif ++ ++else ++ ++PWD := $(shell pwd) ++PORTLIB := $(PWD)/../dwc_common_port ++ ++# Command paths ++CTAGS := $(CTAGS) ++DOXYGEN := $(DOXYGEN) ++ ++default: portlib ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ ++install: default ++ $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install ++ $(MAKE) -C$(KDIR) M=$(PWD) modules_install ++ ++portlib: ++ $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ cp $(PORTLIB)/Module.symvers $(PWD)/ ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++ ++clean: ++ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers ++ ++endif +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/doc/doxygen.cfg +@@ -0,0 +1,224 @@ ++# Doxyfile 1.3.9.1 ++ ++#--------------------------------------------------------------------------- ++# Project related configuration options ++#--------------------------------------------------------------------------- ++PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver" ++PROJECT_NUMBER = v3.00a ++OUTPUT_DIRECTORY = ./doc/ ++CREATE_SUBDIRS = NO ++OUTPUT_LANGUAGE = English ++BRIEF_MEMBER_DESC = YES ++REPEAT_BRIEF = YES ++ABBREVIATE_BRIEF = "The $name class" \ ++ "The $name widget" \ ++ "The $name file" \ ++ is \ ++ provides \ ++ specifies \ ++ contains \ ++ represents \ ++ a \ ++ an \ ++ the ++ALWAYS_DETAILED_SEC = NO ++INLINE_INHERITED_MEMB = NO ++FULL_PATH_NAMES = NO ++STRIP_FROM_PATH = ++STRIP_FROM_INC_PATH = ++SHORT_NAMES = NO ++JAVADOC_AUTOBRIEF = YES ++MULTILINE_CPP_IS_BRIEF = NO ++INHERIT_DOCS = YES ++DISTRIBUTE_GROUP_DOC = NO ++TAB_SIZE = 8 ++ALIASES = ++OPTIMIZE_OUTPUT_FOR_C = YES ++OPTIMIZE_OUTPUT_JAVA = NO ++SUBGROUPING = YES ++#--------------------------------------------------------------------------- ++# Build related configuration options ++#--------------------------------------------------------------------------- ++EXTRACT_ALL = NO ++EXTRACT_PRIVATE = YES ++EXTRACT_STATIC = YES ++EXTRACT_LOCAL_CLASSES = YES ++EXTRACT_LOCAL_METHODS = NO ++HIDE_UNDOC_MEMBERS = NO ++HIDE_UNDOC_CLASSES = NO ++HIDE_FRIEND_COMPOUNDS = NO ++HIDE_IN_BODY_DOCS = NO ++INTERNAL_DOCS = NO ++CASE_SENSE_NAMES = NO ++HIDE_SCOPE_NAMES = NO ++SHOW_INCLUDE_FILES = YES ++INLINE_INFO = YES ++SORT_MEMBER_DOCS = NO ++SORT_BRIEF_DOCS = NO ++SORT_BY_SCOPE_NAME = NO ++GENERATE_TODOLIST = YES ++GENERATE_TESTLIST = YES ++GENERATE_BUGLIST = YES ++GENERATE_DEPRECATEDLIST= YES ++ENABLED_SECTIONS = ++MAX_INITIALIZER_LINES = 30 ++SHOW_USED_FILES = YES ++SHOW_DIRECTORIES = YES ++#--------------------------------------------------------------------------- ++# configuration options related to warning and progress messages ++#--------------------------------------------------------------------------- ++QUIET = YES ++WARNINGS = YES ++WARN_IF_UNDOCUMENTED = NO ++WARN_IF_DOC_ERROR = YES ++WARN_FORMAT = "$file:$line: $text" ++WARN_LOGFILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the input files ++#--------------------------------------------------------------------------- ++INPUT = . ++FILE_PATTERNS = *.c \ ++ *.h \ ++ ./linux/*.c \ ++ ./linux/*.h ++RECURSIVE = NO ++EXCLUDE = ./test/ \ ++ ./dwc_otg/.AppleDouble/ ++EXCLUDE_SYMLINKS = YES ++EXCLUDE_PATTERNS = *.mod.* ++EXAMPLE_PATH = ++EXAMPLE_PATTERNS = * ++EXAMPLE_RECURSIVE = NO ++IMAGE_PATH = ++INPUT_FILTER = ++FILTER_PATTERNS = ++FILTER_SOURCE_FILES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to source browsing ++#--------------------------------------------------------------------------- ++SOURCE_BROWSER = YES ++INLINE_SOURCES = NO ++STRIP_CODE_COMMENTS = YES ++REFERENCED_BY_RELATION = NO ++REFERENCES_RELATION = NO ++VERBATIM_HEADERS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the alphabetical class index ++#--------------------------------------------------------------------------- ++ALPHABETICAL_INDEX = NO ++COLS_IN_ALPHA_INDEX = 5 ++IGNORE_PREFIX = ++#--------------------------------------------------------------------------- ++# configuration options related to the HTML output ++#--------------------------------------------------------------------------- ++GENERATE_HTML = YES ++HTML_OUTPUT = html ++HTML_FILE_EXTENSION = .html ++HTML_HEADER = ++HTML_FOOTER = ++HTML_STYLESHEET = ++HTML_ALIGN_MEMBERS = YES ++GENERATE_HTMLHELP = NO ++CHM_FILE = ++HHC_LOCATION = ++GENERATE_CHI = NO ++BINARY_TOC = NO ++TOC_EXPAND = NO ++DISABLE_INDEX = NO ++ENUM_VALUES_PER_LINE = 4 ++GENERATE_TREEVIEW = YES ++TREEVIEW_WIDTH = 250 ++#--------------------------------------------------------------------------- ++# configuration options related to the LaTeX output ++#--------------------------------------------------------------------------- ++GENERATE_LATEX = NO ++LATEX_OUTPUT = latex ++LATEX_CMD_NAME = latex ++MAKEINDEX_CMD_NAME = makeindex ++COMPACT_LATEX = NO ++PAPER_TYPE = a4wide ++EXTRA_PACKAGES = ++LATEX_HEADER = ++PDF_HYPERLINKS = NO ++USE_PDFLATEX = NO ++LATEX_BATCHMODE = NO ++LATEX_HIDE_INDICES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the RTF output ++#--------------------------------------------------------------------------- ++GENERATE_RTF = NO ++RTF_OUTPUT = rtf ++COMPACT_RTF = NO ++RTF_HYPERLINKS = NO ++RTF_STYLESHEET_FILE = ++RTF_EXTENSIONS_FILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the man page output ++#--------------------------------------------------------------------------- ++GENERATE_MAN = NO ++MAN_OUTPUT = man ++MAN_EXTENSION = .3 ++MAN_LINKS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the XML output ++#--------------------------------------------------------------------------- ++GENERATE_XML = NO ++XML_OUTPUT = xml ++XML_SCHEMA = ++XML_DTD = ++XML_PROGRAMLISTING = YES ++#--------------------------------------------------------------------------- ++# configuration options for the AutoGen Definitions output ++#--------------------------------------------------------------------------- ++GENERATE_AUTOGEN_DEF = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the Perl module output ++#--------------------------------------------------------------------------- ++GENERATE_PERLMOD = NO ++PERLMOD_LATEX = NO ++PERLMOD_PRETTY = YES ++PERLMOD_MAKEVAR_PREFIX = ++#--------------------------------------------------------------------------- ++# Configuration options related to the preprocessor ++#--------------------------------------------------------------------------- ++ENABLE_PREPROCESSING = YES ++MACRO_EXPANSION = YES ++EXPAND_ONLY_PREDEF = YES ++SEARCH_INCLUDES = YES ++INCLUDE_PATH = ++INCLUDE_FILE_PATTERNS = ++PREDEFINED = DEVICE_ATTR DWC_EN_ISOC ++EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC ++SKIP_FUNCTION_MACROS = NO ++#--------------------------------------------------------------------------- ++# Configuration::additions related to external references ++#--------------------------------------------------------------------------- ++TAGFILES = ++GENERATE_TAGFILE = ++ALLEXTERNALS = NO ++EXTERNAL_GROUPS = YES ++PERL_PATH = /usr/bin/perl ++#--------------------------------------------------------------------------- ++# Configuration options related to the dot tool ++#--------------------------------------------------------------------------- ++CLASS_DIAGRAMS = YES ++HIDE_UNDOC_RELATIONS = YES ++HAVE_DOT = NO ++CLASS_GRAPH = YES ++COLLABORATION_GRAPH = YES ++UML_LOOK = NO ++TEMPLATE_RELATIONS = NO ++INCLUDE_GRAPH = YES ++INCLUDED_BY_GRAPH = YES ++CALL_GRAPH = NO ++GRAPHICAL_HIERARCHY = YES ++DOT_IMAGE_FORMAT = png ++DOT_PATH = ++DOTFILE_DIRS = ++MAX_DOT_GRAPH_DEPTH = 1000 ++GENERATE_LEGEND = YES ++DOT_CLEANUP = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to the search engine ++#--------------------------------------------------------------------------- ++SEARCHENGINE = NO +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dummy_audio.c +@@ -0,0 +1,1575 @@ ++/* ++ * zero.c -- Gadget Zero, for USB development ++ * ++ * Copyright (C) 2003-2004 David Brownell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") as published by the Free Software ++ * Foundation, either version 2 of that License or (at your option) any ++ * later version. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* ++ * Gadget Zero only needs two bulk endpoints, and is an example of how you ++ * can write a hardware-agnostic gadget driver running inside a USB device. ++ * ++ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't ++ * affect most of the driver. ++ * ++ * Use it with the Linux host/master side "usbtest" driver to get a basic ++ * functional test of your device-side usb stack, or with "usb-skeleton". ++ * ++ * It supports two similar configurations. One sinks whatever the usb host ++ * writes, and in return sources zeroes. The other loops whatever the host ++ * writes back, so the host can read it. Module options include: ++ * ++ * buflen=N default N=4096, buffer size used ++ * qlen=N default N=32, how many buffers in the loopback queue ++ * loopdefault default false, list loopback config first ++ * ++ * Many drivers will only have one configuration, letting them be much ++ * simpler if they also don't support high speed operation (like this ++ * driver does). ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++# include ++#else ++# include ++#endif ++ ++#include ++ ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++ ++/** ++ * usb_gadget_get_string - fill out a string descriptor ++ * @table: of c strings encoded using UTF-8 ++ * @id: string id, from low byte of wValue in get string descriptor ++ * @buf: at least 256 bytes ++ * ++ * Finds the UTF-8 string matching the ID, and converts it into a ++ * string descriptor in utf16-le. ++ * Returns length of descriptor (always even) or negative errno ++ * ++ * If your driver needs stings in multiple languages, you'll probably ++ * "switch (wIndex) { ... }" in your ep0 string descriptor logic, ++ * using this routine after choosing which set of UTF-8 strings to use. ++ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with ++ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1 ++ * characters (which are also widely used in C strings). ++ */ ++int ++usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf) ++{ ++ struct usb_string *s; ++ int len; ++ ++ /* descriptor 0 has the language id */ ++ if (id == 0) { ++ buf [0] = 4; ++ buf [1] = USB_DT_STRING; ++ buf [2] = (u8) table->language; ++ buf [3] = (u8) (table->language >> 8); ++ return 4; ++ } ++ for (s = table->strings; s && s->s; s++) ++ if (s->id == id) ++ break; ++ ++ /* unrecognized: stall. */ ++ if (!s || !s->s) ++ return -EINVAL; ++ ++ /* string descriptors have length, tag, then UTF16-LE text */ ++ len = min ((size_t) 126, strlen (s->s)); ++ memset (buf + 2, 0, 2 * len); /* zero all the bytes */ ++ len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len); ++ if (len < 0) ++ return -EINVAL; ++ buf [0] = (len + 1) * 2; ++ buf [1] = USB_DT_STRING; ++ return buf [0]; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++/** ++ * usb_descriptor_fillbuf - fill buffer with descriptors ++ * @buf: Buffer to be filled ++ * @buflen: Size of buf ++ * @src: Array of descriptor pointers, terminated by null pointer. ++ * ++ * Copies descriptors into the buffer, returning the length or a ++ * negative error code if they can't all be copied. Useful when ++ * assembling descriptors for an associated set of interfaces used ++ * as part of configuring a composite device; or in other cases where ++ * sets of descriptors need to be marshaled. ++ */ ++int ++usb_descriptor_fillbuf(void *buf, unsigned buflen, ++ const struct usb_descriptor_header **src) ++{ ++ u8 *dest = buf; ++ ++ if (!src) ++ return -EINVAL; ++ ++ /* fill buffer from src[] until null descriptor ptr */ ++ for (; 0 != *src; src++) { ++ unsigned len = (*src)->bLength; ++ ++ if (len > buflen) ++ return -EINVAL; ++ memcpy(dest, *src, len); ++ buflen -= len; ++ dest += len; ++ } ++ return dest - (u8 *)buf; ++} ++ ++ ++/** ++ * usb_gadget_config_buf - builts a complete configuration descriptor ++ * @config: Header for the descriptor, including characteristics such ++ * as power requirements and number of interfaces. ++ * @desc: Null-terminated vector of pointers to the descriptors (interface, ++ * endpoint, etc) defining all functions in this device configuration. ++ * @buf: Buffer for the resulting configuration descriptor. ++ * @length: Length of buffer. If this is not big enough to hold the ++ * entire configuration descriptor, an error code will be returned. ++ * ++ * This copies descriptors into the response buffer, building a descriptor ++ * for that configuration. It returns the buffer length or a negative ++ * status code. The config.wTotalLength field is set to match the length ++ * of the result, but other descriptor fields (including power usage and ++ * interface count) must be set by the caller. ++ * ++ * Gadget drivers could use this when constructing a config descriptor ++ * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the ++ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed. ++ */ ++int usb_gadget_config_buf( ++ const struct usb_config_descriptor *config, ++ void *buf, ++ unsigned length, ++ const struct usb_descriptor_header **desc ++) ++{ ++ struct usb_config_descriptor *cp = buf; ++ int len; ++ ++ /* config descriptor first */ ++ if (length < USB_DT_CONFIG_SIZE || !desc) ++ return -EINVAL; ++ *cp = *config; ++ ++ /* then interface/endpoint/class/vendor/... */ ++ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf, ++ length - USB_DT_CONFIG_SIZE, desc); ++ if (len < 0) ++ return len; ++ len += USB_DT_CONFIG_SIZE; ++ if (len > 0xffff) ++ return -EINVAL; ++ ++ /* patch up the config descriptor */ ++ cp->bLength = USB_DT_CONFIG_SIZE; ++ cp->bDescriptorType = USB_DT_CONFIG; ++ cp->wTotalLength = cpu_to_le16(len); ++ cp->bmAttributes |= USB_CONFIG_ATT_ONE; ++ return len; ++} ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++#define RBUF_LEN (1024*1024) ++static int rbuf_start; ++static int rbuf_len; ++static __u8 rbuf[RBUF_LEN]; ++ ++/*-------------------------------------------------------------------------*/ ++ ++#define DRIVER_VERSION "St Patrick's Day 2004" ++ ++static const char shortname [] = "zero"; ++static const char longname [] = "YAMAHA YST-MS35D USB Speaker "; ++ ++static const char source_sink [] = "source and sink data"; ++static const char loopback [] = "loop input to output"; ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * driver assumes self-powered hardware, and ++ * has no way for users to trigger remote wakeup. ++ * ++ * this version autoconfigures as much as possible, ++ * which is reasonable for most "bulk-only" drivers. ++ */ ++static const char *EP_IN_NAME; /* source */ ++static const char *EP_OUT_NAME; /* sink */ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* big enough to hold our biggest descriptor */ ++#define USB_BUFSIZ 512 ++ ++struct zero_dev { ++ spinlock_t lock; ++ struct usb_gadget *gadget; ++ struct usb_request *req; /* for control responses */ ++ ++ /* when configured, we have one of two configs: ++ * - source data (in to host) and sink it (out from host) ++ * - or loop it back (out from host back in to host) ++ */ ++ u8 config; ++ struct usb_ep *in_ep, *out_ep; ++ ++ /* autoresume timer */ ++ struct timer_list resume; ++}; ++ ++#define xprintk(d,level,fmt,args...) \ ++ dev_printk(level , &(d)->gadget->dev , fmt , ## args) ++ ++#ifdef DEBUG ++#define DBG(dev,fmt,args...) \ ++ xprintk(dev , KERN_DEBUG , fmt , ## args) ++#else ++#define DBG(dev,fmt,args...) \ ++ do { } while (0) ++#endif /* DEBUG */ ++ ++#ifdef VERBOSE ++#define VDBG DBG ++#else ++#define VDBG(dev,fmt,args...) \ ++ do { } while (0) ++#endif /* VERBOSE */ ++ ++#define ERROR(dev,fmt,args...) \ ++ xprintk(dev , KERN_ERR , fmt , ## args) ++#define WARN(dev,fmt,args...) \ ++ xprintk(dev , KERN_WARNING , fmt , ## args) ++#define INFO(dev,fmt,args...) \ ++ xprintk(dev , KERN_INFO , fmt , ## args) ++ ++/*-------------------------------------------------------------------------*/ ++ ++static unsigned buflen = 4096; ++static unsigned qlen = 32; ++static unsigned pattern = 0; ++ ++module_param (buflen, uint, S_IRUGO|S_IWUSR); ++module_param (qlen, uint, S_IRUGO|S_IWUSR); ++module_param (pattern, uint, S_IRUGO|S_IWUSR); ++ ++/* ++ * if it's nonzero, autoresume says how many seconds to wait ++ * before trying to wake up the host after suspend. ++ */ ++static unsigned autoresume = 0; ++module_param (autoresume, uint, 0); ++ ++/* ++ * Normally the "loopback" configuration is second (index 1) so ++ * it's not the default. Here's where to change that order, to ++ * work better with hosts where config changes are problematic. ++ * Or controllers (like superh) that only support one config. ++ */ ++static int loopdefault = 0; ++ ++module_param (loopdefault, bool, S_IRUGO|S_IWUSR); ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Thanks to NetChip Technologies for donating this product ID. ++ * ++ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!! ++ * Instead: allocate your own, using normal USB-IF procedures. ++ */ ++#ifndef CONFIG_USB_ZERO_HNPTEST ++#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */ ++#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */ ++#else ++#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */ ++#define DRIVER_PRODUCT_NUM 0xbadd ++#endif ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * DESCRIPTORS ... most are static, but strings and (full) ++ * configuration descriptors are built on demand. ++ */ ++ ++/* ++#define STRING_MANUFACTURER 25 ++#define STRING_PRODUCT 42 ++#define STRING_SERIAL 101 ++*/ ++#define STRING_MANUFACTURER 1 ++#define STRING_PRODUCT 2 ++#define STRING_SERIAL 3 ++ ++#define STRING_SOURCE_SINK 250 ++#define STRING_LOOPBACK 251 ++ ++/* ++ * This device advertises two configurations; these numbers work ++ * on a pxa250 as well as more flexible hardware. ++ */ ++#define CONFIG_SOURCE_SINK 3 ++#define CONFIG_LOOPBACK 2 ++ ++/* ++static struct usb_device_descriptor ++device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ ++ .bcdUSB = __constant_cpu_to_le16 (0x0200), ++ .bDeviceClass = USB_CLASS_VENDOR_SPEC, ++ ++ .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM), ++ .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM), ++ .iManufacturer = STRING_MANUFACTURER, ++ .iProduct = STRING_PRODUCT, ++ .iSerialNumber = STRING_SERIAL, ++ .bNumConfigurations = 2, ++}; ++*/ ++static struct usb_device_descriptor ++device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ .bcdUSB = __constant_cpu_to_le16 (0x0100), ++ .bDeviceClass = USB_CLASS_PER_INTERFACE, ++ .bDeviceSubClass = 0, ++ .bDeviceProtocol = 0, ++ .bMaxPacketSize0 = 64, ++ .bcdDevice = __constant_cpu_to_le16 (0x0100), ++ .idVendor = __constant_cpu_to_le16 (0x0499), ++ .idProduct = __constant_cpu_to_le16 (0x3002), ++ .iManufacturer = STRING_MANUFACTURER, ++ .iProduct = STRING_PRODUCT, ++ .iSerialNumber = STRING_SERIAL, ++ .bNumConfigurations = 1, ++}; ++ ++static struct usb_config_descriptor ++z_config = { ++ .bLength = sizeof z_config, ++ .bDescriptorType = USB_DT_CONFIG, ++ ++ /* compute wTotalLength on the fly */ ++ .bNumInterfaces = 2, ++ .bConfigurationValue = 1, ++ .iConfiguration = 0, ++ .bmAttributes = 0x40, ++ .bMaxPower = 0, /* self-powered */ ++}; ++ ++ ++static struct usb_otg_descriptor ++otg_descriptor = { ++ .bLength = sizeof otg_descriptor, ++ .bDescriptorType = USB_DT_OTG, ++ ++ .bmAttributes = USB_OTG_SRP, ++}; ++ ++/* one interface in each configuration */ ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ ++/* ++ * usb 2.0 devices need to expose both high speed and full speed ++ * descriptors, unless they only run at full speed. ++ * ++ * that means alternate endpoint descriptors (bigger packets) ++ * and a "device qualifier" ... plus more construction options ++ * for the config descriptor. ++ */ ++ ++static struct usb_qualifier_descriptor ++dev_qualifier = { ++ .bLength = sizeof dev_qualifier, ++ .bDescriptorType = USB_DT_DEVICE_QUALIFIER, ++ ++ .bcdUSB = __constant_cpu_to_le16 (0x0200), ++ .bDeviceClass = USB_CLASS_VENDOR_SPEC, ++ ++ .bNumConfigurations = 2, ++}; ++ ++ ++struct usb_cs_as_general_descriptor { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ ++ __u8 bDescriptorSubType; ++ __u8 bTerminalLink; ++ __u8 bDelay; ++ __u16 wFormatTag; ++} __attribute__ ((packed)); ++ ++struct usb_cs_as_format_descriptor { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ ++ __u8 bDescriptorSubType; ++ __u8 bFormatType; ++ __u8 bNrChannels; ++ __u8 bSubframeSize; ++ __u8 bBitResolution; ++ __u8 bSamfreqType; ++ __u8 tLowerSamFreq[3]; ++ __u8 tUpperSamFreq[3]; ++} __attribute__ ((packed)); ++ ++static const struct usb_interface_descriptor ++z_audio_control_if_desc = { ++ .bLength = sizeof z_audio_control_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x1, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_interface_descriptor ++z_audio_if_desc = { ++ .bLength = sizeof z_audio_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 1, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x2, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_interface_descriptor ++z_audio_if_desc2 = { ++ .bLength = sizeof z_audio_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 1, ++ .bAlternateSetting = 1, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x2, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_cs_as_general_descriptor ++z_audio_cs_as_if_desc = { ++ .bLength = 7, ++ .bDescriptorType = 0x24, ++ ++ .bDescriptorSubType = 0x01, ++ .bTerminalLink = 0x01, ++ .bDelay = 0x0, ++ .wFormatTag = __constant_cpu_to_le16 (0x0001) ++}; ++ ++ ++static const struct usb_cs_as_format_descriptor ++z_audio_cs_as_format_desc = { ++ .bLength = 0xe, ++ .bDescriptorType = 0x24, ++ ++ .bDescriptorSubType = 2, ++ .bFormatType = 1, ++ .bNrChannels = 1, ++ .bSubframeSize = 1, ++ .bBitResolution = 8, ++ .bSamfreqType = 0, ++ .tLowerSamFreq = {0x7e, 0x13, 0x00}, ++ .tUpperSamFreq = {0xe2, 0xd6, 0x00}, ++}; ++ ++static const struct usb_endpoint_descriptor ++z_iso_ep = { ++ .bLength = 0x09, ++ .bDescriptorType = 0x05, ++ .bEndpointAddress = 0x04, ++ .bmAttributes = 0x09, ++ .wMaxPacketSize = 0x0038, ++ .bInterval = 0x01, ++ .bRefresh = 0x00, ++ .bSynchAddress = 0x00, ++}; ++ ++static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++// 9 bytes ++static char z_ac_interface_header_desc[] = ++{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 }; ++ ++// 12 bytes ++static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, ++ 0x03, 0x00, 0x00, 0x00}; ++// 13 bytes ++static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, ++ 0x02, 0x00, 0x02, 0x00, 0x00}; ++// 9 bytes ++static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, ++ 0x00}; ++ ++static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00, ++ 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00, ++ 0x00}; ++ ++static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++ ++ ++static const struct usb_descriptor_header *z_function [] = { ++ (struct usb_descriptor_header *) &z_audio_control_if_desc, ++ (struct usb_descriptor_header *) &z_ac_interface_header_desc, ++ (struct usb_descriptor_header *) &z_0, ++ (struct usb_descriptor_header *) &z_1, ++ (struct usb_descriptor_header *) &z_2, ++ (struct usb_descriptor_header *) &z_audio_if_desc, ++ (struct usb_descriptor_header *) &z_audio_if_desc2, ++ (struct usb_descriptor_header *) &z_audio_cs_as_if_desc, ++ (struct usb_descriptor_header *) &z_audio_cs_as_format_desc, ++ (struct usb_descriptor_header *) &z_iso_ep, ++ (struct usb_descriptor_header *) &z_iso_ep2, ++ (struct usb_descriptor_header *) &za_0, ++ (struct usb_descriptor_header *) &za_1, ++ (struct usb_descriptor_header *) &za_2, ++ (struct usb_descriptor_header *) &za_3, ++ (struct usb_descriptor_header *) &za_4, ++ (struct usb_descriptor_header *) &za_5, ++ (struct usb_descriptor_header *) &za_6, ++ (struct usb_descriptor_header *) &za_7, ++ (struct usb_descriptor_header *) &za_8, ++ (struct usb_descriptor_header *) &za_9, ++ (struct usb_descriptor_header *) &za_10, ++ (struct usb_descriptor_header *) &za_11, ++ (struct usb_descriptor_header *) &za_12, ++ (struct usb_descriptor_header *) &za_13, ++ (struct usb_descriptor_header *) &za_14, ++ (struct usb_descriptor_header *) &za_15, ++ (struct usb_descriptor_header *) &za_16, ++ (struct usb_descriptor_header *) &za_17, ++ (struct usb_descriptor_header *) &za_18, ++ (struct usb_descriptor_header *) &za_19, ++ (struct usb_descriptor_header *) &za_20, ++ (struct usb_descriptor_header *) &za_21, ++ (struct usb_descriptor_header *) &za_22, ++ (struct usb_descriptor_header *) &za_23, ++ (struct usb_descriptor_header *) &za_24, ++ NULL, ++}; ++ ++/* maxpacket and other transfer characteristics vary by speed. */ ++#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs)) ++ ++#else ++ ++/* if there's no high speed support, maxpacket doesn't change. */ ++#define ep_desc(g,hs,fs) fs ++ ++#endif /* !CONFIG_USB_GADGET_DUALSPEED */ ++ ++static char manufacturer [40]; ++//static char serial [40]; ++static char serial [] = "Ser 00 em"; ++ ++/* static strings, in UTF-8 */ ++static struct usb_string strings [] = { ++ { STRING_MANUFACTURER, manufacturer, }, ++ { STRING_PRODUCT, longname, }, ++ { STRING_SERIAL, serial, }, ++ { STRING_LOOPBACK, loopback, }, ++ { STRING_SOURCE_SINK, source_sink, }, ++ { } /* end of list */ ++}; ++ ++static struct usb_gadget_strings stringtab = { ++ .language = 0x0409, /* en-us */ ++ .strings = strings, ++}; ++ ++/* ++ * config descriptors are also handcrafted. these must agree with code ++ * that sets configurations, and with code managing interfaces and their ++ * altsettings. other complexity may come from: ++ * ++ * - high speed support, including "other speed config" rules ++ * - multiple configurations ++ * - interfaces with alternate settings ++ * - embedded class or vendor-specific descriptors ++ * ++ * this handles high speed, and has a second config that could as easily ++ * have been an alternate interface setting (on most hardware). ++ * ++ * NOTE: to demonstrate (and test) more USB capabilities, this driver ++ * should include an altsetting to test interrupt transfers, including ++ * high bandwidth modes at high speed. (Maybe work like Intel's test ++ * device?) ++ */ ++static int ++config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index) ++{ ++ int len; ++ const struct usb_descriptor_header **function; ++ ++ function = z_function; ++ len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function); ++ if (len < 0) ++ return len; ++ ((struct usb_config_descriptor *) buf)->bDescriptorType = type; ++ return len; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_request * ++alloc_ep_req (struct usb_ep *ep, unsigned length) ++{ ++ struct usb_request *req; ++ ++ req = usb_ep_alloc_request (ep, GFP_ATOMIC); ++ if (req) { ++ req->length = length; ++ req->buf = usb_ep_alloc_buffer (ep, length, ++ &req->dma, GFP_ATOMIC); ++ if (!req->buf) { ++ usb_ep_free_request (ep, req); ++ req = NULL; ++ } ++ } ++ return req; ++} ++ ++static void free_ep_req (struct usb_ep *ep, struct usb_request *req) ++{ ++ if (req->buf) ++ usb_ep_free_buffer (ep, req->buf, req->dma, req->length); ++ usb_ep_free_request (ep, req); ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* optionally require specific source/sink data patterns */ ++ ++static int ++check_read_data ( ++ struct zero_dev *dev, ++ struct usb_ep *ep, ++ struct usb_request *req ++) ++{ ++ unsigned i; ++ u8 *buf = req->buf; ++ ++ for (i = 0; i < req->actual; i++, buf++) { ++ switch (pattern) { ++ /* all-zeroes has no synchronization issues */ ++ case 0: ++ if (*buf == 0) ++ continue; ++ break; ++ /* mod63 stays in sync with short-terminated transfers, ++ * or otherwise when host and gadget agree on how large ++ * each usb transfer request should be. resync is done ++ * with set_interface or set_config. ++ */ ++ case 1: ++ if (*buf == (u8)(i % 63)) ++ continue; ++ break; ++ } ++ ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf); ++ usb_ep_set_halt (ep); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void zero_reset_config (struct zero_dev *dev) ++{ ++ if (dev->config == 0) ++ return; ++ ++ DBG (dev, "reset config\n"); ++ ++ /* just disable endpoints, forcing completion of pending i/o. ++ * all our completion handlers free their requests in this case. ++ */ ++ if (dev->in_ep) { ++ usb_ep_disable (dev->in_ep); ++ dev->in_ep = NULL; ++ } ++ if (dev->out_ep) { ++ usb_ep_disable (dev->out_ep); ++ dev->out_ep = NULL; ++ } ++ dev->config = 0; ++ del_timer (&dev->resume); ++} ++ ++#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos)) ++ ++static void ++zero_isoc_complete (struct usb_ep *ep, struct usb_request *req) ++{ ++ struct zero_dev *dev = ep->driver_data; ++ int status = req->status; ++ int i, j; ++ ++ switch (status) { ++ ++ case 0: /* normal completion? */ ++ //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual); ++ for (i=0, j=rbuf_start; iactual; i++) { ++ //printk ("%02x ", ((__u8*)req->buf)[i]); ++ rbuf[j] = ((__u8*)req->buf)[i]; ++ j++; ++ if (j >= RBUF_LEN) j=0; ++ } ++ rbuf_start = j; ++ //printk ("\n\n"); ++ ++ if (rbuf_len < RBUF_LEN) { ++ rbuf_len += req->actual; ++ if (rbuf_len > RBUF_LEN) { ++ rbuf_len = RBUF_LEN; ++ } ++ } ++ ++ break; ++ ++ /* this endpoint is normally active while we're configured */ ++ case -ECONNABORTED: /* hardware forced ep reset */ ++ case -ECONNRESET: /* request dequeued */ ++ case -ESHUTDOWN: /* disconnect from host */ ++ VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status, ++ req->actual, req->length); ++ if (ep == dev->out_ep) ++ check_read_data (dev, ep, req); ++ free_ep_req (ep, req); ++ return; ++ ++ case -EOVERFLOW: /* buffer overrun on read means that ++ * we didn't provide a big enough ++ * buffer. ++ */ ++ default: ++#if 1 ++ DBG (dev, "%s complete --> %d, %d/%d\n", ep->name, ++ status, req->actual, req->length); ++#endif ++ case -EREMOTEIO: /* short read */ ++ break; ++ } ++ ++ status = usb_ep_queue (ep, req, GFP_ATOMIC); ++ if (status) { ++ ERROR (dev, "kill %s: resubmit %d bytes --> %d\n", ++ ep->name, req->length, status); ++ usb_ep_set_halt (ep); ++ /* FIXME recover later ... somehow */ ++ } ++} ++ ++static struct usb_request * ++zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags) ++{ ++ struct usb_request *req; ++ int status; ++ ++ req = alloc_ep_req (ep, 512); ++ if (!req) ++ return NULL; ++ ++ req->complete = zero_isoc_complete; ++ ++ status = usb_ep_queue (ep, req, gfp_flags); ++ if (status) { ++ struct zero_dev *dev = ep->driver_data; ++ ++ ERROR (dev, "start %s --> %d\n", ep->name, status); ++ free_ep_req (ep, req); ++ req = NULL; ++ } ++ ++ return req; ++} ++ ++/* change our operational config. this code must agree with the code ++ * that returns config descriptors, and altsetting code. ++ * ++ * it's also responsible for power management interactions. some ++ * configurations might not work with our current power sources. ++ * ++ * note that some device controller hardware will constrain what this ++ * code can do, perhaps by disallowing more than one configuration or ++ * by limiting configuration choices (like the pxa2xx). ++ */ ++static int ++zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags) ++{ ++ int result = 0; ++ struct usb_gadget *gadget = dev->gadget; ++ const struct usb_endpoint_descriptor *d; ++ struct usb_ep *ep; ++ ++ if (number == dev->config) ++ return 0; ++ ++ zero_reset_config (dev); ++ ++ gadget_for_each_ep (ep, gadget) { ++ ++ if (strcmp (ep->name, "ep4") == 0) { ++ ++ d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6 ++ result = usb_ep_enable (ep, d); ++ ++ if (result == 0) { ++ ep->driver_data = dev; ++ dev->in_ep = ep; ++ ++ if (zero_start_isoc_ep (ep, gfp_flags) != 0) { ++ ++ dev->in_ep = ep; ++ continue; ++ } ++ ++ usb_ep_disable (ep); ++ result = -EIO; ++ } ++ } ++ ++ } ++ ++ dev->config = number; ++ return result; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req) ++{ ++ if (req->status || req->actual != req->length) ++ DBG ((struct zero_dev *) ep->driver_data, ++ "setup complete --> %d, %d/%d\n", ++ req->status, req->actual, req->length); ++} ++ ++/* ++ * The setup() callback implements all the ep0 functionality that's ++ * not handled lower down, in hardware or the hardware driver (like ++ * device and endpoint feature flags, and their status). It's all ++ * housekeeping for the gadget function we're implementing. Most of ++ * the work is in config-specific setup. ++ */ ++static int ++zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ struct usb_request *req = dev->req; ++ int value = -EOPNOTSUPP; ++ ++ /* usually this stores reply data in the pre-allocated ep0 buffer, ++ * but config change events will reconfigure hardware. ++ */ ++ req->zero = 0; ++ switch (ctrl->bRequest) { ++ ++ case USB_REQ_GET_DESCRIPTOR: ++ ++ switch (ctrl->wValue >> 8) { ++ ++ case USB_DT_DEVICE: ++ value = min (ctrl->wLength, (u16) sizeof device_desc); ++ memcpy (req->buf, &device_desc, value); ++ break; ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ case USB_DT_DEVICE_QUALIFIER: ++ if (!gadget->is_dualspeed) ++ break; ++ value = min (ctrl->wLength, (u16) sizeof dev_qualifier); ++ memcpy (req->buf, &dev_qualifier, value); ++ break; ++ ++ case USB_DT_OTHER_SPEED_CONFIG: ++ if (!gadget->is_dualspeed) ++ break; ++ // FALLTHROUGH ++#endif /* CONFIG_USB_GADGET_DUALSPEED */ ++ case USB_DT_CONFIG: ++ value = config_buf (gadget, req->buf, ++ ctrl->wValue >> 8, ++ ctrl->wValue & 0xff); ++ if (value >= 0) ++ value = min (ctrl->wLength, (u16) value); ++ break; ++ ++ case USB_DT_STRING: ++ /* wIndex == language code. ++ * this driver only handles one language, you can ++ * add string tables for other languages, using ++ * any UTF-8 characters ++ */ ++ value = usb_gadget_get_string (&stringtab, ++ ctrl->wValue & 0xff, req->buf); ++ if (value >= 0) { ++ value = min (ctrl->wLength, (u16) value); ++ } ++ break; ++ } ++ break; ++ ++ /* currently two configs, two speeds */ ++ case USB_REQ_SET_CONFIGURATION: ++ if (ctrl->bRequestType != 0) ++ goto unknown; ++ ++ spin_lock (&dev->lock); ++ value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC); ++ spin_unlock (&dev->lock); ++ break; ++ case USB_REQ_GET_CONFIGURATION: ++ if (ctrl->bRequestType != USB_DIR_IN) ++ goto unknown; ++ *(u8 *)req->buf = dev->config; ++ value = min (ctrl->wLength, (u16) 1); ++ break; ++ ++ /* until we add altsetting support, or other interfaces, ++ * only 0/0 are possible. pxa2xx only supports 0/0 (poorly) ++ * and already killed pending endpoint I/O. ++ */ ++ case USB_REQ_SET_INTERFACE: ++ ++ if (ctrl->bRequestType != USB_RECIP_INTERFACE) ++ goto unknown; ++ spin_lock (&dev->lock); ++ if (dev->config) { ++ u8 config = dev->config; ++ ++ /* resets interface configuration, forgets about ++ * previous transaction state (queued bufs, etc) ++ * and re-inits endpoint state (toggle etc) ++ * no response queued, just zero status == success. ++ * if we had more than one interface we couldn't ++ * use this "reset the config" shortcut. ++ */ ++ zero_reset_config (dev); ++ zero_set_config (dev, config, GFP_ATOMIC); ++ value = 0; ++ } ++ spin_unlock (&dev->lock); ++ break; ++ case USB_REQ_GET_INTERFACE: ++ if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) { ++ value = ctrl->wLength; ++ break; ++ } ++ else { ++ if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)) ++ goto unknown; ++ if (!dev->config) ++ break; ++ if (ctrl->wIndex != 0) { ++ value = -EDOM; ++ break; ++ } ++ *(u8 *)req->buf = 0; ++ value = min (ctrl->wLength, (u16) 1); ++ } ++ break; ++ ++ /* ++ * These are the same vendor-specific requests supported by ++ * Intel's USB 2.0 compliance test devices. We exceed that ++ * device spec by allowing multiple-packet requests. ++ */ ++ case 0x5b: /* control WRITE test -- fill the buffer */ ++ if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR)) ++ goto unknown; ++ if (ctrl->wValue || ctrl->wIndex) ++ break; ++ /* just read that many bytes into the buffer */ ++ if (ctrl->wLength > USB_BUFSIZ) ++ break; ++ value = ctrl->wLength; ++ break; ++ case 0x5c: /* control READ test -- return the buffer */ ++ if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR)) ++ goto unknown; ++ if (ctrl->wValue || ctrl->wIndex) ++ break; ++ /* expect those bytes are still in the buffer; send back */ ++ if (ctrl->wLength > USB_BUFSIZ ++ || ctrl->wLength != req->length) ++ break; ++ value = ctrl->wLength; ++ break; ++ ++ case 0x01: // SET_CUR ++ case 0x02: ++ case 0x03: ++ case 0x04: ++ case 0x05: ++ value = ctrl->wLength; ++ break; ++ case 0x81: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0xe3; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x00; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x81; ++ //((u8*)req->buf)[1] = 0x81; ++ value = ctrl->wLength; ++ break; ++ case 0x82: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0xc3; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x00; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x82; ++ //((u8*)req->buf)[1] = 0x82; ++ value = ctrl->wLength; ++ break; ++ case 0x83: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0x00; ++ break; ++ case 0x0300: ++ ((u8*)req->buf)[0] = 0x60; ++ break; ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x18; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x83; ++ //((u8*)req->buf)[1] = 0x83; ++ value = ctrl->wLength; ++ break; ++ case 0x84: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0x01; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x08; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x84; ++ //((u8*)req->buf)[1] = 0x84; ++ value = ctrl->wLength; ++ break; ++ case 0x85: ++ ((u8*)req->buf)[0] = 0x85; ++ ((u8*)req->buf)[1] = 0x85; ++ value = ctrl->wLength; ++ break; ++ ++ ++ default: ++unknown: ++ printk("unknown control req%02x.%02x v%04x i%04x l%d\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ ctrl->wValue, ctrl->wIndex, ctrl->wLength); ++ } ++ ++ /* respond with data transfer before status phase? */ ++ if (value >= 0) { ++ req->length = value; ++ req->zero = value < ctrl->wLength ++ && (value % gadget->ep0->maxpacket) == 0; ++ value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC); ++ if (value < 0) { ++ DBG (dev, "ep_queue < 0 --> %d\n", value); ++ req->status = 0; ++ zero_setup_complete (gadget->ep0, req); ++ } ++ } ++ ++ /* device either stalls (value < 0) or reports success */ ++ return value; ++} ++ ++static void ++zero_disconnect (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ unsigned long flags; ++ ++ spin_lock_irqsave (&dev->lock, flags); ++ zero_reset_config (dev); ++ ++ /* a more significant application might have some non-usb ++ * activities to quiesce here, saving resources like power ++ * or pushing the notification up a network stack. ++ */ ++ spin_unlock_irqrestore (&dev->lock, flags); ++ ++ /* next we may get setup() calls to enumerate new connections; ++ * or an unbind() during shutdown (including removing module). ++ */ ++} ++ ++static void ++zero_autoresume (unsigned long _dev) ++{ ++ struct zero_dev *dev = (struct zero_dev *) _dev; ++ int status; ++ ++ /* normally the host would be woken up for something ++ * more significant than just a timer firing... ++ */ ++ if (dev->gadget->speed != USB_SPEED_UNKNOWN) { ++ status = usb_gadget_wakeup (dev->gadget); ++ DBG (dev, "wakeup --> %d\n", status); ++ } ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void ++zero_unbind (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ DBG (dev, "unbind\n"); ++ ++ /* we've already been disconnected ... no i/o is active */ ++ if (dev->req) ++ free_ep_req (gadget->ep0, dev->req); ++ del_timer_sync (&dev->resume); ++ kfree (dev); ++ set_gadget_data (gadget, NULL); ++} ++ ++static int ++zero_bind (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev; ++ //struct usb_ep *ep; ++ ++ printk("binding\n"); ++ /* ++ * DRIVER POLICY CHOICE: you may want to do this differently. ++ * One thing to avoid is reusing a bcdDevice revision code ++ * with different host-visible configurations or behavior ++ * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc ++ */ ++ //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201); ++ ++ ++ /* ok, we made sense of the hardware ... */ ++ dev = kmalloc (sizeof *dev, SLAB_KERNEL); ++ if (!dev) ++ return -ENOMEM; ++ memset (dev, 0, sizeof *dev); ++ spin_lock_init (&dev->lock); ++ dev->gadget = gadget; ++ set_gadget_data (gadget, dev); ++ ++ /* preallocate control response and buffer */ ++ dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL); ++ if (!dev->req) ++ goto enomem; ++ dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ, ++ &dev->req->dma, GFP_KERNEL); ++ if (!dev->req->buf) ++ goto enomem; ++ ++ dev->req->complete = zero_setup_complete; ++ ++ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket; ++ ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ /* assume ep0 uses the same value for both speeds ... */ ++ dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0; ++ ++ /* and that all endpoints are dual-speed */ ++ //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress; ++ //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress; ++#endif ++ ++ usb_gadget_set_selfpowered (gadget); ++ ++ init_timer (&dev->resume); ++ dev->resume.function = zero_autoresume; ++ dev->resume.data = (unsigned long) dev; ++ ++ gadget->ep0->driver_data = dev; ++ ++ INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname); ++ INFO (dev, "using %s, OUT %s IN %s\n", gadget->name, ++ EP_OUT_NAME, EP_IN_NAME); ++ ++ snprintf (manufacturer, sizeof manufacturer, ++ UTS_SYSNAME " " UTS_RELEASE " with %s", ++ gadget->name); ++ ++ return 0; ++ ++enomem: ++ zero_unbind (gadget); ++ return -ENOMEM; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void ++zero_suspend (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ if (gadget->speed == USB_SPEED_UNKNOWN) ++ return; ++ ++ if (autoresume) { ++ mod_timer (&dev->resume, jiffies + (HZ * autoresume)); ++ DBG (dev, "suspend, wakeup in %d seconds\n", autoresume); ++ } else ++ DBG (dev, "suspend\n"); ++} ++ ++static void ++zero_resume (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ DBG (dev, "resume\n"); ++ del_timer (&dev->resume); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_gadget_driver zero_driver = { ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ .speed = USB_SPEED_HIGH, ++#else ++ .speed = USB_SPEED_FULL, ++#endif ++ .function = (char *) longname, ++ .bind = zero_bind, ++ .unbind = zero_unbind, ++ ++ .setup = zero_setup, ++ .disconnect = zero_disconnect, ++ ++ .suspend = zero_suspend, ++ .resume = zero_resume, ++ ++ .driver = { ++ .name = (char *) shortname, ++ // .shutdown = ... ++ // .suspend = ... ++ // .resume = ... ++ }, ++}; ++ ++MODULE_AUTHOR ("David Brownell"); ++MODULE_LICENSE ("Dual BSD/GPL"); ++ ++static struct proc_dir_entry *pdir, *pfile; ++ ++static int isoc_read_data (char *page, char **start, ++ off_t off, int count, ++ int *eof, void *data) ++{ ++ int i; ++ static int c = 0; ++ static int done = 0; ++ static int s = 0; ++ ++/* ++ printk ("\ncount: %d\n", count); ++ printk ("rbuf_start: %d\n", rbuf_start); ++ printk ("rbuf_len: %d\n", rbuf_len); ++ printk ("off: %d\n", off); ++ printk ("start: %p\n\n", *start); ++*/ ++ if (done) { ++ c = 0; ++ done = 0; ++ *eof = 1; ++ return 0; ++ } ++ ++ if (c == 0) { ++ if (rbuf_len == RBUF_LEN) ++ s = rbuf_start; ++ else s = 0; ++ } ++ ++ for (i=0; i= rbuf_len) { ++ *eof = 1; ++ done = 1; ++ } ++ ++ ++ return i; ++} ++ ++static int __init init (void) ++{ ++ ++ int retval = 0; ++ ++ pdir = proc_mkdir("isoc_test", NULL); ++ if(pdir == NULL) { ++ retval = -ENOMEM; ++ printk("Error creating dir\n"); ++ goto done; ++ } ++ pdir->owner = THIS_MODULE; ++ ++ pfile = create_proc_read_entry("isoc_data", ++ 0444, pdir, ++ isoc_read_data, ++ NULL); ++ if (pfile == NULL) { ++ retval = -ENOMEM; ++ printk("Error creating file\n"); ++ goto no_file; ++ } ++ pfile->owner = THIS_MODULE; ++ ++ return usb_gadget_register_driver (&zero_driver); ++ ++ no_file: ++ remove_proc_entry("isoc_data", NULL); ++ done: ++ return retval; ++} ++module_init (init); ++ ++static void __exit cleanup (void) ++{ ++ ++ usb_gadget_unregister_driver (&zero_driver); ++ ++ remove_proc_entry("isoc_data", pdir); ++ remove_proc_entry("isoc_test", NULL); ++} ++module_exit (cleanup); +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_cfi_common.h +@@ -0,0 +1,142 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_CFI_COMMON_H__) ++#define __DWC_CFI_COMMON_H__ ++ ++//#include ++ ++/** ++ * @file ++ * ++ * This file contains the CFI specific common constants, interfaces ++ * (functions and macros) and structures for Linux. No PCD specific ++ * data structure or definition is to be included in this file. ++ * ++ */ ++ ++/** This is a request for all Core Features */ ++#define VEN_CORE_GET_FEATURES 0xB1 ++ ++/** This is a request to get the value of a specific Core Feature */ ++#define VEN_CORE_GET_FEATURE 0xB2 ++ ++/** This command allows the host to set the value of a specific Core Feature */ ++#define VEN_CORE_SET_FEATURE 0xB3 ++ ++/** This command allows the host to set the default values of ++ * either all or any specific Core Feature ++ */ ++#define VEN_CORE_RESET_FEATURES 0xB4 ++ ++/** This command forces the PCD to write the deferred values of a Core Features */ ++#define VEN_CORE_ACTIVATE_FEATURES 0xB5 ++ ++/** This request reads a DWORD value from a register at the specified offset */ ++#define VEN_CORE_READ_REGISTER 0xB6 ++ ++/** This request writes a DWORD value into a register at the specified offset */ ++#define VEN_CORE_WRITE_REGISTER 0xB7 ++ ++/** This structure is the header of the Core Features dataset returned to ++ * the Host ++ */ ++struct cfi_all_features_header { ++/** The features header structure length is */ ++#define CFI_ALL_FEATURES_HDR_LEN 8 ++ /** ++ * The total length of the features dataset returned to the Host ++ */ ++ uint16_t wTotalLen; ++ ++ /** ++ * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H). ++ * This field identifies the version of the CFI Specification with which ++ * the device is compliant. ++ */ ++ uint16_t wVersion; ++ ++ /** The ID of the Core */ ++ uint16_t wCoreID; ++#define CFI_CORE_ID_UDC 1 ++#define CFI_CORE_ID_OTG 2 ++#define CFI_CORE_ID_WUDEV 3 ++ ++ /** Number of features returned by VEN_CORE_GET_FEATURES request */ ++ uint16_t wNumFeatures; ++} UPACKED; ++ ++typedef struct cfi_all_features_header cfi_all_features_header_t; ++ ++/** This structure is a header of the Core Feature descriptor dataset returned to ++ * the Host after the VEN_CORE_GET_FEATURES request ++ */ ++struct cfi_feature_desc_header { ++#define CFI_FEATURE_DESC_HDR_LEN 8 ++ ++ /** The feature ID */ ++ uint16_t wFeatureID; ++ ++ /** Length of this feature descriptor in bytes - including the ++ * length of the feature name string ++ */ ++ uint16_t wLength; ++ ++ /** The data length of this feature in bytes */ ++ uint16_t wDataLength; ++ ++ /** ++ * Attributes of this features ++ * D0: Access rights ++ * 0 - Read/Write ++ * 1 - Read only ++ */ ++ uint8_t bmAttributes; ++#define CFI_FEATURE_ATTR_RO 1 ++#define CFI_FEATURE_ATTR_RW 0 ++ ++ /** Length of the feature name in bytes */ ++ uint8_t bNameLen; ++ ++ /** The feature name buffer */ ++ //uint8_t *name; ++} UPACKED; ++ ++typedef struct cfi_feature_desc_header cfi_feature_desc_header_t; ++ ++/** ++ * This structure describes a NULL terminated string referenced by its id field. ++ * It is very similar to usb_string structure but has the id field type set to 16-bit. ++ */ ++struct cfi_string { ++ uint16_t id; ++ const uint8_t *s; ++}; ++typedef struct cfi_string cfi_string_t; ++ ++#endif +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.c +@@ -0,0 +1,854 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $ ++ * $Revision: #12 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_adp.h" ++ ++/** @file ++ * ++ * This file contains the most of the Attach Detect Protocol implementation for ++ * the driver to support OTG Rev2.0. ++ * ++ */ ++ ++void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = value; ++ adpctl.b.ar = 0x2; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); ++ ++ while (adpctl.b.ar) { ++ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); ++ } ++ ++} ++ ++/** ++ * Function is called to read ADP registers ++ */ ++uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = 0; ++ adpctl.b.ar = 0x1; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); ++ ++ while (adpctl.b.ar) { ++ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); ++ } ++ ++ return adpctl.d32; ++} ++ ++/** ++ * Function is called to read ADPCTL register and filter Write-clear bits ++ */ ++uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_tmout_int = 0; ++ adpctl.b.adp_prb_int = 0; ++ adpctl.b.adp_tmout_int = 0; ++ ++ return adpctl.d32; ++} ++ ++/** ++ * Function is called to write ADP registers ++ */ ++void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr, ++ uint32_t set) ++{ ++ dwc_otg_adp_write_reg(core_if, ++ (dwc_otg_adp_read_reg(core_if) & (~clr)) | set); ++} ++ ++static void adp_sense_timeout(void *ptr) ++{ ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ core_if->adp.sense_timer_started = 0; ++ DWC_PRINTF("ADP SENSE TIMEOUT\n"); ++ if (core_if->adp_enable) { ++ dwc_otg_adp_sense_stop(core_if); ++ dwc_otg_adp_probe_start(core_if); ++ } ++} ++ ++/** ++ * This function is called when the ADP vbus timer expires. Timeout is 1.1s. ++ */ ++static void adp_vbuson_timeout(void *ptr) ++{ ++ gpwrdn_data_t gpwrdn; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__); ++ if (core_if) { ++ core_if->adp.vbuson_timer_started = 0; ++ /* Turn off vbus */ ++ hprt0.b.prtpwr = 1; ++ DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0); ++ gpwrdn.d32 = 0; ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ /* Enable Wakeup Logic */ ++// gpwrdn.b.wkupactiv = 1; ++ gpwrdn.b.pmuactv = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ ++ /* Suspend the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ /* Switch on VDD */ ++// gpwrdn.b.wkupactiv = 1; ++ gpwrdn.b.pmuactv = 1; ++ gpwrdn.b.pwrdnrstn = 1; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ } else { ++ /* Enable Power Down Logic */ ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ } ++ ++ /* Unmask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_probe_start(core_if); ++ dwc_otg_dump_global_registers(core_if); ++ dwc_otg_dump_host_registers(core_if); ++ } ++ ++} ++ ++/** ++ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is ++ * not asserted within 1.1 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.vbuson_timer_started = 1; ++ if (core_if->adp.vbuson_timer) ++ { ++ DWC_PRINTF("SCHEDULING VBUSON TIMER\n"); ++ /* 1.1 secs + 60ms necessary for cil_hcd_start*/ ++ DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160); ++ } else { ++ DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer); ++ } ++} ++ ++#if 0 ++/** ++ * Masks all DWC OTG core interrupts ++ * ++ */ ++static void mask_all_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ++ /* Mask Host Interrupts */ ++ ++ /* Clear and disable HCINTs */ ++ for (i = 0; i < core_if->core_params->host_channels; i++) { ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0); ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF); ++ ++ } ++ ++ /* Clear and disable HAINT */ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000); ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF); ++ ++ /* Mask Device Interrupts */ ++ if (!core_if->multiproc_int_enable) { ++ /* Clear and disable IN Endpoint interrupts */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0); ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> ++ diepint, 0xFFFFFFFF); ++ } ++ ++ /* Clear and disable OUT Endpoint interrupts */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0); ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> ++ doepint, 0xFFFFFFFF); ++ } ++ ++ /* Clear and disable DAINT */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint, ++ 0xFFFFFFFF); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0); ++ } else { ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[i], 0); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> ++ diepint, 0xFFFFFFFF); ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[i], 0); ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> ++ doepint, 0xFFFFFFFF); ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, ++ 0); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint, ++ 0xFFFFFFFF); ++ ++ } ++ ++ /* Disable interrupts */ ++ ahbcfg.b.glblintrmsk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); ++ ++ /* Disable all interrupts. */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Clear any pending OTG Interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF); ++} ++ ++/** ++ * Unmask Port Connection Detected interrupt ++ * ++ */ ++static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 }; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); ++} ++#endif ++ ++/** ++ * Starts the ADP Probing ++ * ++ * @param core_if the pointer to core_if structure. ++ */ ++uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if) ++{ ++ ++ adpctl_data_t adpctl = {.d32 = 0}; ++ gpwrdn_data_t gpwrdn; ++#if 0 ++ adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1, ++ .b.adp_sns_int = 1, b.adp_tmout_int}; ++#endif ++ dwc_otg_disable_global_interrupts(core_if); ++ DWC_PRINTF("ADP Probe Start\n"); ++ core_if->adp.probe_enabled = 1; ++ ++ adpctl.b.adpres = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ while (adpctl.b.adpres) { ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ } ++ ++ adpctl.d32 = 0; ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ /* In Host mode unmask SRP detected interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.sts_chngint_msk = 1; ++ if (!gpwrdn.b.idsts) { ++ gpwrdn.b.srp_det_msk = 1; ++ } ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ ++ adpctl.b.adp_tmout_int_msk = 1; ++ adpctl.b.adp_prb_int_msk = 1; ++ adpctl.b.prb_dschg = 1; ++ adpctl.b.prb_delta = 1; ++ adpctl.b.prb_per = 1; ++ adpctl.b.adpen = 1; ++ adpctl.b.enaprb = 1; ++ ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ DWC_PRINTF("ADP Probe Finish\n"); ++ return 0; ++} ++ ++/** ++ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted ++ * within 3 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.sense_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ ); ++} ++ ++/** ++ * Starts the ADP Sense ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ DWC_PRINTF("ADP Sense Start\n"); ++ ++ /* Unmask ADP sense interrupt and mask all other from the core */ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.adp_sns_int_msk = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ dwc_otg_disable_global_interrupts(core_if); // vahrama ++ ++ /* Set ADP reset bit*/ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.adpres = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ while (adpctl.b.adpres) { ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ } ++ ++ adpctl.b.adpres = 0; ++ adpctl.b.adpen = 1; ++ adpctl.b.enasns = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ dwc_otg_adp_sense_timer_start(core_if); ++ ++ return 0; ++} ++ ++/** ++ * Stops the ADP Probing ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if) ++{ ++ ++ adpctl_data_t adpctl; ++ DWC_PRINTF("Stop ADP probe\n"); ++ core_if->adp.probe_enabled = 0; ++ core_if->adp.probe_counter = 0; ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ ++ adpctl.b.adpen = 0; ++ adpctl.b.adp_prb_int = 1; ++ adpctl.b.adp_tmout_int = 1; ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * Stops the ADP Sensing ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ core_if->adp.sense_enabled = 0; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.enasns = 0; ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * Called to turn on the VBUS after initial ADP probe in host mode. ++ * If port power was already enabled in cil_hcd_start function then ++ * only schedule a timer. ++ * ++ * @param core_if the pointer to core_if structure. ++ */ ++void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr); ++ ++ if (hprt0.b.prtpwr == 0) { ++ hprt0.b.prtpwr = 1; ++ //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ ++ dwc_otg_adp_vbuson_timer_start(core_if); ++} ++ ++/** ++ * Called right after driver is loaded ++ * to perform initial actions for ADP ++ * ++ * @param core_if the pointer to core_if structure. ++ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN ++ */ ++void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host) ++{ ++ gpwrdn_data_t gpwrdn; ++ ++ DWC_PRINTF("ADP Initial Start\n"); ++ core_if->adp.adp_started = 1; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ dwc_otg_disable_global_interrupts(core_if); ++ if (is_host) { ++ DWC_PRINTF("HOST MODE\n"); ++ /* Enable Power Down Logic Interrupt*/ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ /* Initialize first ADP probe to obtain Ramp Time value */ ++ core_if->adp.initial_probe = 1; ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ gotgctl_data_t gotgctl; ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ DWC_PRINTF("DEVICE MODE\n"); ++ if (gotgctl.b.bsesvld == 0) { ++ /* Enable Power Down Logic Interrupt*/ ++ gpwrdn.d32 = 0; ++ DWC_PRINTF("VBUS is not valid - start ADP probe\n"); ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ core_if->adp.initial_probe = 1; ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ DWC_PRINTF("VBUS is valid - initialize core as a Device\n"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ dwc_otg_dump_global_registers(core_if); ++ dwc_otg_dump_dev_registers(core_if); ++ } ++ } ++} ++ ++void dwc_otg_adp_init(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.adp_started = 0; ++ core_if->adp.initial_probe = 0; ++ core_if->adp.probe_timer_values[0] = -1; ++ core_if->adp.probe_timer_values[1] = -1; ++ core_if->adp.probe_enabled = 0; ++ core_if->adp.sense_enabled = 0; ++ core_if->adp.sense_timer_started = 0; ++ core_if->adp.vbuson_timer_started = 0; ++ core_if->adp.probe_counter = 0; ++ core_if->adp.gpwrdn = 0; ++ core_if->adp.attached = DWC_OTG_ADP_UNKOWN; ++ /* Initialize timers */ ++ core_if->adp.sense_timer = ++ DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if); ++ core_if->adp.vbuson_timer = ++ DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if); ++ if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer) ++ { ++ DWC_ERROR("Could not allocate memory for ADP timers\n"); ++ } ++} ++ ++void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (core_if->adp.probe_enabled) ++ dwc_otg_adp_probe_stop(core_if); ++ if (core_if->adp.sense_enabled) ++ dwc_otg_adp_sense_stop(core_if); ++ if (core_if->adp.sense_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ if (core_if->adp.vbuson_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); ++ DWC_TIMER_FREE(core_if->adp.sense_timer); ++ DWC_TIMER_FREE(core_if->adp.vbuson_timer); ++} ++ ++///////////////////////////////////////////////////////////////////// ++////////////// ADP Interrupt Handlers /////////////////////////////// ++///////////////////////////////////////////////////////////////////// ++/** ++ * This function sets Ramp Timer values ++ */ ++static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ if (core_if->adp.probe_timer_values[0] == -1) { ++ core_if->adp.probe_timer_values[0] = val; ++ core_if->adp.probe_timer_values[1] = -1; ++ return 1; ++ } else { ++ core_if->adp.probe_timer_values[1] = ++ core_if->adp.probe_timer_values[0]; ++ core_if->adp.probe_timer_values[0] = val; ++ return 0; ++ } ++} ++ ++/** ++ * This function compares Ramp Timer values ++ */ ++static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t diff; ++ if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1]) ++ diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1]; ++ else ++ diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0]; ++ if(diff < 2) { ++ return 0; ++ } else { ++ return 1; ++ } ++} ++ ++/** ++ * This function handles ADP Probe Interrupts ++ */ ++static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if, ++ uint32_t val) ++{ ++ adpctl_data_t adpctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn, temp; ++ adpctl.d32 = val; ++ ++ temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ core_if->adp.probe_counter++; ++ core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (adpctl.b.rtim == 0 && !temp.b.idsts){ ++ DWC_PRINTF("RTIM value is 0\n"); ++ goto exit; ++ } ++ if (set_timer_value(core_if, adpctl.b.rtim) && ++ core_if->adp.initial_probe) { ++ core_if->adp.initial_probe = 0; ++ dwc_otg_adp_probe_stop(core_if); ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* check which value is for device mode and which for Host mode */ ++ if (!temp.b.idsts) { /* considered host mode value is 0 */ ++ /* ++ * Turn on VBUS after initial ADP probe. ++ */ ++ core_if->op_state = A_HOST; ++ dwc_otg_enable_global_interrupts(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_start(core_if); ++ dwc_otg_adp_turnon_vbus(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ } else { ++ /* ++ * Initiate SRP after initial ADP probe. ++ */ ++ dwc_otg_enable_global_interrupts(core_if); ++ dwc_otg_initiate_srp(core_if); ++ } ++ } else if (core_if->adp.probe_counter > 2){ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (compare_timer_values(core_if)) { ++ DWC_PRINTF("Difference in timer values !!! \n"); ++// core_if->adp.attached = DWC_OTG_ADP_ATTACHED; ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ /* check which value is for device mode and which for Host mode */ ++ if (!temp.b.idsts) { /* considered host mode value is 0 */ ++ /* Disable Interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } else { ++ gotgctl_data_t gotgctl; ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ if (!gotgctl.b.bsesvld) { ++ dwc_otg_initiate_srp(core_if); ++ } ++ } ++ } ++ if (core_if->power_down == 2) { ++ if (gpwrdn.b.bsessvld) { ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } ++ } ++exit: ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_prb_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * This function hadles ADP Sense Interrupt ++ */ ++static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ /* Stop ADP Sense timer */ ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ ++ /* Restart ADP Sense timer */ ++ dwc_otg_adp_sense_timer_start(core_if); ++ ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * This function handles ADP Probe Interrupts ++ */ ++static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if, ++ uint32_t val) ++{ ++ adpctl_data_t adpctl = {.d32 = 0 }; ++ adpctl.d32 = val; ++ set_timer_value(core_if, adpctl.b.rtim); ++ ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_tmout_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * ADP Interrupt handler. ++ * ++ */ ++int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ adpctl_data_t adpctl = {.d32 = 0}; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32); ++ ++ if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) { ++ DWC_PRINTF("ADP Sense interrupt\n"); ++ retval |= dwc_otg_adp_handle_sns_intr(core_if); ++ } ++ if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) { ++ DWC_PRINTF("ADP timeout interrupt\n"); ++ retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32); ++ } ++ if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) { ++ DWC_PRINTF("ADP Probe interrupt\n"); ++ adpctl.b.adp_prb_int = 1; ++ retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32); ++ } ++ ++// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0); ++ //dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ DWC_PRINTF("RETURN FROM ADP ISR\n"); ++ ++ return retval; ++} ++ ++/** ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if) ++{ ++ ++#ifndef DWC_HOST_ONLY ++ hprt0_data_t hprt0; ++ gpwrdn_data_t gpwrdn; ++ DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n"); ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ /* check which value is for device mode and which for Host mode */ ++ if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */ ++ DWC_PRINTF("SRP: Host mode\n"); ++ ++ if (core_if->adp_enable) { ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ ++ /* Turn on the port power bit. */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Start the Connection timer. So a message can be displayed ++ * if connect does not occur within 10 seconds. */ ++ cil_hcd_session_start(core_if); ++ } else { ++ DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__); ++ if (core_if->adp_enable) { ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 0; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } ++#endif ++ return 1; ++} +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.h +@@ -0,0 +1,80 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $ ++ * $Revision: #7 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871159 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_ADP_H__ ++#define __DWC_OTG_ADP_H__ ++ ++/** ++ * @file ++ * ++ * This file contains the Attach Detect Protocol interfaces and defines ++ * (functions) and structures for Linux. ++ * ++ */ ++ ++#define DWC_OTG_ADP_UNATTACHED 0 ++#define DWC_OTG_ADP_ATTACHED 1 ++#define DWC_OTG_ADP_UNKOWN 2 ++ ++typedef struct dwc_otg_adp { ++ uint32_t adp_started; ++ uint32_t initial_probe; ++ int32_t probe_timer_values[2]; ++ uint32_t probe_enabled; ++ uint32_t sense_enabled; ++ dwc_timer_t *sense_timer; ++ uint32_t sense_timer_started; ++ dwc_timer_t *vbuson_timer; ++ uint32_t vbuson_timer_started; ++ uint32_t attached; ++ uint32_t probe_counter; ++ uint32_t gpwrdn; ++} dwc_otg_adp_t; ++ ++/** ++ * Attach Detect Protocol functions ++ */ ++ ++extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value); ++extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); ++extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if); ++extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if); ++extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if); ++ ++#endif //__DWC_OTG_ADP_H__ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.c +@@ -0,0 +1,1210 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $ ++ * $Revision: #44 $ ++ * $Date: 2010/11/29 $ ++ * $Change: 1636033 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The diagnostic interface will provide access to the controller for ++ * bringing up the hardware and testing. The Linux driver attributes ++ * feature will be used to provide the Linux Diagnostic ++ * Interface. These attributes are accessed through sysfs. ++ */ ++ ++/** @page "Linux Module Attributes" ++ * ++ * The Linux module attributes feature is used to provide the Linux ++ * Diagnostic Interface. These attributes are accessed through sysfs. ++ * The diagnostic interface will provide access to the controller for ++ * bringing up the hardware and testing. ++ ++ The following table shows the attributes. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
Name Description Access
mode Returns the current mode: 0 for device mode, 1 for host mode Read
hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. ++ Read returns the current value. Read/Write
srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. ++ Read returns the current value. Read/Write
hsic_connect Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register. ++ Read returns the current value. Read/Write
inv_sel_hsic Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register. ++ Read returns the current value. Read/Write
hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write
srp Initiates the Session Request Protocol. Read returns the status. Read/Write
buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write
bussuspend Suspends the USB bus. Read/Write
busconnected Gets the connection status of the bus Read
gotgctl Gets or sets the Core Control Status Register. Read/Write
gusbcfg Gets or sets the Core USB Configuration Register Read/Write
grxfsiz Gets or sets the Receive FIFO Size Register Read/Write
gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write
gpvndctl Gets or sets the PHY Vendor Control Register Read/Write
ggpio Gets the value in the lower 16-bits of the General Purpose IO Register ++ or sets the upper 16 bits. Read/Write
guid Gets or sets the value of the User ID Register Read/Write
gsnpsid Gets the value of the Synopsys ID Regester Read
devspeed Gets or sets the device speed setting in the DCFG register Read/Write
enumspeed Gets the device enumeration Speed. Read
hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read
hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write
regoffset Sets the register offset for the next Register Access Read/Write
regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write
remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote ++ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote ++ Wakeup signalling bit in the Device Control Register is set for 1 ++ milli-second. Read/Write
rem_wakeup_pwrdn On read, shows the status core - hibernated or not. On write, initiates ++ a remote wakeup of the device from Hibernation. Read/Write
mode_ch_tim_en This bit is used to enable or disable the host core to wait for 200 PHY ++ clock cycles at the end of Resume to change the opmode signal to the PHY to 00 ++ after Suspend or LPM. Read/Write
fr_interval On read, shows the value of HFIR Frame Interval. On write, dynamically ++ reload HFIR register during runtime. The application can write a value to this ++ register only after the Port Enable bit of the Host Port Control and Status ++ register (HPRT.PrtEnaPort) has been set Read/Write
disconnect_us On read, shows the status of disconnect_device_us. On write, sets disconnect_us ++ which causes soft disconnect for 100us. Applicable only for device mode of operation. Read/Write
regdump Dumps the contents of core registers. Read
spramdump Dumps the contents of core registers. Read
hcddump Dumps the current HCD state. Read
hcd_frrem Shows the average value of the Frame Remaining ++ field in the Host Frame Number/Frame Remaining register when an SOF interrupt ++ occurs. This can be used to determine the average interrupt latency. Also ++ shows the average Frame Remaining value for start_transfer and the "a" and ++ "b" sample points. The "a" and "b" sample points may be used during debugging ++ bto determine how long it takes to execute a section of the HCD code. Read
rd_reg_test Displays the time required to read the GNPTXFSIZ register many times ++ (the output shows the number of times the register is read). ++ Read
wr_reg_test Displays the time required to write the GNPTXFSIZ register many times ++ (the output shows the number of times the register is written). ++ Read
lpm_response Gets or sets lpm_response mode. Applicable only in device mode. ++ Write
sleep_status Shows sleep status of device. ++ Read
++ ++ Example usage: ++ To get the current mode: ++ cat /sys/devices/lm0/mode ++ ++ To power down the USB: ++ echo 0 > /sys/devices/lm0/buspower ++ */ ++ ++#include "dwc_otg_os_dep.h" ++#include "dwc_os.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_attr.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_hcd_if.h" ++ ++/* ++ * MACROs for defining sysfs attribute ++ */ ++#ifdef LM_INTERFACE ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++ ++#elif defined(PCI_INTERFACE) ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++ ++#elif defined(PLATFORM_INTERFACE) ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct platform_device *platform_dev = \ ++ container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val; \ ++ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \ ++ __func__, _dev, platform_dev, otg_dev); \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++#endif ++ ++/* ++ * MACROs for defining sysfs attribute for 32-bit registers ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++ ++#elif defined(PLATFORM_INTERFACE) ++#include "dwc_otg_dbg.h" ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val; \ ++ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \ ++ __func__, _dev, platform_dev, otg_dev); \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++ ++#endif ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); ++ ++#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); ++ ++#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); ++ ++/** @name Functions for Show/Store of Attributes */ ++/**@{*/ ++ ++/** ++ * Helper function returning the otg_device structure of the given device ++ */ ++static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev) ++{ ++ dwc_otg_device_t *otg_dev; ++ DWC_OTG_GETDRVDEV(otg_dev, _dev); ++ return otg_dev; ++} ++ ++/** ++ * Show the register offset of the Register Access. ++ */ ++static ssize_t regoffset_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n", ++ otg_dev->os_dep.reg_offset); ++} ++ ++/** ++ * Set the register offset for the next Register Access Read/Write ++ */ ++static ssize_t regoffset_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t offset = simple_strtoul(buf, NULL, 16); ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ if (offset < SZ_256K) { ++#elif defined(PCI_INTERFACE) ++ if (offset < 0x00040000) { ++#endif ++ otg_dev->os_dep.reg_offset = offset; ++ } else { ++ dev_err(_dev, "invalid offset\n"); ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store); ++ ++/** ++ * Show the value of the register at the offset in the reg_offset ++ * attribute. ++ */ ++static ssize_t regvalue_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val; ++ volatile uint32_t *addr; ++ ++ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) { ++ /* Calculate the address */ ++ addr = (uint32_t *) (otg_dev->os_dep.reg_offset + ++ (uint8_t *) otg_dev->os_dep.base); ++ val = DWC_READ_REG32(addr); ++ return snprintf(buf, ++ sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1, ++ "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset, ++ val); ++ } else { ++ dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset); ++ return sprintf(buf, "invalid offset\n"); ++ } ++} ++ ++/** ++ * Store the value in the register at the offset in the reg_offset ++ * attribute. ++ * ++ */ ++static ssize_t regvalue_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ volatile uint32_t *addr; ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); ++ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) { ++ /* Calculate the address */ ++ addr = (uint32_t *) (otg_dev->os_dep.reg_offset + ++ (uint8_t *) otg_dev->os_dep.base); ++ DWC_WRITE_REG32(addr, val); ++ } else { ++ dev_err(_dev, "Invalid Register Offset (0x%08x)\n", ++ otg_dev->os_dep.reg_offset); ++ } ++ return count; ++} ++ ++DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store); ++ ++/* ++ * Attributes ++ */ ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC"); ++ ++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); ++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected"); ++ ++DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg, ++ &(otg_dev->core_if->core_global_regs->gusbcfg), ++ "GUSBCFG"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz, ++ &(otg_dev->core_if->core_global_regs->grxfsiz), ++ "GRXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz, ++ &(otg_dev->core_if->core_global_regs->gnptxfsiz), ++ "GNPTXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl, ++ &(otg_dev->core_if->core_global_regs->gpvndctl), ++ "GPVNDCTL"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio, ++ &(otg_dev->core_if->core_global_regs->ggpio), ++ "GGPIO"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid), ++ "GUID"); ++DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid, ++ &(otg_dev->core_if->core_global_regs->gsnpsid), ++ "GSNPSID"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed"); ++ ++DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz, ++ &(otg_dev->core_if->core_global_regs->hptxfsiz), ++ "HPTXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0"); ++ ++/** ++ * @todo Add code to initiate the HNP. ++ */ ++/** ++ * Show the HNP status bit ++ */ ++static ssize_t hnp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "HstNegScs = 0x%x\n", ++ dwc_otg_get_hnpstatus(otg_dev->core_if)); ++} ++ ++/** ++ * Set the HNP Request bit ++ */ ++static ssize_t hnp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_hnpreq(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); ++ ++/** ++ * @todo Add code to initiate the SRP. ++ */ ++/** ++ * Show the SRP status bit ++ */ ++static ssize_t srp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "SesReqScs = 0x%x\n", ++ dwc_otg_get_srpstatus(otg_dev->core_if)); ++#else ++ return sprintf(buf, "Host Only Mode!\n"); ++#endif ++} ++ ++/** ++ * Set the SRP Request bit ++ */ ++static ssize_t srp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_pcd_initiate_srp(otg_dev->pcd); ++#endif ++ return count; ++} ++ ++DEVICE_ATTR(srp, 0644, srp_show, srp_store); ++ ++/** ++ * @todo Need to do more for power on/off? ++ */ ++/** ++ * Show the Bus Power status ++ */ ++static ssize_t buspower_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Bus Power = 0x%x\n", ++ dwc_otg_get_prtpower(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Bus Power status ++ */ ++static ssize_t buspower_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t on = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_prtpower(otg_dev->core_if, on); ++ return count; ++} ++ ++DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); ++ ++/** ++ * @todo Need to do more for suspend? ++ */ ++/** ++ * Show the Bus Suspend status ++ */ ++static ssize_t bussuspend_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Bus Suspend = 0x%x\n", ++ dwc_otg_get_prtsuspend(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Bus Suspend status ++ */ ++static ssize_t bussuspend_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_prtsuspend(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); ++ ++/** ++ * Show the Mode Change Ready Timer status ++ */ ++static ssize_t mode_ch_tim_en_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n", ++ dwc_otg_get_mode_ch_tim(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Mode Change Ready Timer status ++ */ ++static ssize_t mode_ch_tim_en_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_mode_ch_tim(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store); ++ ++/** ++ * Show the value of HFIR Frame Interval bitfield ++ */ ++static ssize_t fr_interval_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Frame Interval = 0x%x\n", ++ dwc_otg_get_fr_interval(otg_dev->core_if)); ++} ++ ++/** ++ * Set the HFIR Frame Interval value ++ */ ++static ssize_t fr_interval_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 10); ++ dwc_otg_set_fr_interval(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store); ++ ++/** ++ * Show the status of Remote Wakeup. ++ */ ++static ssize_t remote_wakeup_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ return sprintf(buf, ++ "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n", ++ dwc_otg_get_remotewakesig(otg_dev->core_if), ++ dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd), ++ dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if)); ++#else ++ return sprintf(buf, "Host Only Mode!\n"); ++#endif /* DWC_HOST_ONLY */ ++} ++ ++/** ++ * Initiate a remote wakeup of the host. The Device control register ++ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable ++ * flag is set. ++ * ++ */ ++static ssize_t remote_wakeup_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ ++ if (val & 1) { ++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); ++ } else { ++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); ++ } ++#endif /* DWC_HOST_ONLY */ ++ return count; ++} ++ ++DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show, ++ remote_wakeup_store); ++ ++/** ++ * Show the whether core is hibernated or not. ++ */ ++static ssize_t rem_wakeup_pwrdn_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ if (dwc_otg_get_core_state(otg_dev->core_if)) { ++ DWC_PRINTF("Core is in hibernation\n"); ++ } else { ++ DWC_PRINTF("Core is not in hibernation\n"); ++ } ++#endif /* DWC_HOST_ONLY */ ++ return 0; ++} ++ ++extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset); ++ ++/** ++ * Initiate a remote wakeup of the device to exit from hibernation. ++ */ ++static ssize_t rem_wakeup_pwrdn_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0); ++#endif ++ return count; ++} ++ ++DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show, ++ rem_wakeup_pwrdn_store); ++ ++static ssize_t disconnect_us(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ DWC_PRINTF("The Passed value is %04x\n", val); ++ ++ dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50); ++ ++#endif /* DWC_HOST_ONLY */ ++ return count; ++} ++ ++DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us); ++ ++/** ++ * Dump global registers and either host or device registers (depending on the ++ * current mode of the core). ++ */ ++static ssize_t regdump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ dwc_otg_dump_global_registers(otg_dev->core_if); ++ if (dwc_otg_is_host_mode(otg_dev->core_if)) { ++ dwc_otg_dump_host_registers(otg_dev->core_if); ++ } else { ++ dwc_otg_dump_dev_registers(otg_dev->core_if); ++ ++ } ++ return sprintf(buf, "Register Dump\n"); ++} ++ ++DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0); ++ ++/** ++ * Dump global registers and either host or device registers (depending on the ++ * current mode of the core). ++ */ ++static ssize_t spramdump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ //dwc_otg_dump_spram(otg_dev->core_if); ++ ++ return sprintf(buf, "SPRAM Dump\n"); ++} ++ ++DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0); ++ ++/** ++ * Dump the current hcd state. ++ */ ++static ssize_t hcddump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_DEVICE_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_hcd_dump_state(otg_dev->hcd); ++#endif /* DWC_DEVICE_ONLY */ ++ return sprintf(buf, "HCD Dump\n"); ++} ++ ++DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0); ++ ++/** ++ * Dump the average frame remaining at SOF. This can be used to ++ * determine average interrupt latency. Frame remaining is also shown for ++ * start transfer and two additional sample points. ++ */ ++static ssize_t hcd_frrem_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_DEVICE_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ dwc_otg_hcd_dump_frrem(otg_dev->hcd); ++#endif /* DWC_DEVICE_ONLY */ ++ return sprintf(buf, "HCD Dump Frame Remaining\n"); ++} ++ ++DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0); ++ ++/** ++ * Displays the time required to read the GNPTXFSIZ register many times (the ++ * output shows the number of times the register is read). ++ */ ++#define RW_REG_COUNT 10000000 ++#define MSEC_PER_JIFFIE 1000/HZ ++static ssize_t rd_reg_test_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ int i; ++ int time; ++ int start_jiffies; ++ ++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", ++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); ++ start_jiffies = jiffies; ++ for (i = 0; i < RW_REG_COUNT; i++) { ++ dwc_otg_get_gnptxfsiz(otg_dev->core_if); ++ } ++ time = jiffies - start_jiffies; ++ return sprintf(buf, ++ "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", ++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); ++} ++ ++DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0); ++ ++/** ++ * Displays the time required to write the GNPTXFSIZ register many times (the ++ * output shows the number of times the register is written). ++ */ ++static ssize_t wr_reg_test_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t reg_val; ++ int i; ++ int time; ++ int start_jiffies; ++ ++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", ++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); ++ reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if); ++ start_jiffies = jiffies; ++ for (i = 0; i < RW_REG_COUNT; i++) { ++ dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val); ++ } ++ time = jiffies - start_jiffies; ++ return sprintf(buf, ++ "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", ++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); ++} ++ ++DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0); ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ ++/** ++* Show the lpm_response attribute. ++*/ ++static ssize_t lpmresp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) ++ return sprintf(buf, "** LPM is DISABLED **\n"); ++ ++ if (!dwc_otg_is_device_mode(otg_dev->core_if)) { ++ return sprintf(buf, "** Current mode is not device mode\n"); ++ } ++ return sprintf(buf, "lpm_response = %d\n", ++ dwc_otg_get_lpmresponse(otg_dev->core_if)); ++} ++ ++/** ++* Store the lpm_response attribute. ++*/ ++static ssize_t lpmresp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ ++ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) { ++ return 0; ++ } ++ ++ if (!dwc_otg_is_device_mode(otg_dev->core_if)) { ++ return 0; ++ } ++ ++ dwc_otg_set_lpmresponse(otg_dev->core_if, val); ++ return count; ++} ++ ++DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store); ++ ++/** ++* Show the sleep_status attribute. ++*/ ++static ssize_t sleepstatus_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Sleep Status = %d\n", ++ dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)); ++} ++ ++/** ++ * Store the sleep_status attribure. ++ */ ++static ssize_t sleepstatus_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) { ++ if (dwc_otg_is_host_mode(core_if)) { ++ ++ DWC_PRINTF("Host initiated resume\n"); ++ dwc_otg_set_prtresume(otg_dev->core_if, 1); ++ } ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show, ++ sleepstatus_store); ++ ++#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */ ++ ++/**@}*/ ++ ++/** ++ * Create the device files ++ */ ++void dwc_otg_attr_create( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ) ++{ ++ int error; ++ ++ error = device_create_file(&dev->dev, &dev_attr_regoffset); ++ error = device_create_file(&dev->dev, &dev_attr_regvalue); ++ error = device_create_file(&dev->dev, &dev_attr_mode); ++ error = device_create_file(&dev->dev, &dev_attr_hnpcapable); ++ error = device_create_file(&dev->dev, &dev_attr_srpcapable); ++ error = device_create_file(&dev->dev, &dev_attr_hsic_connect); ++ error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic); ++ error = device_create_file(&dev->dev, &dev_attr_hnp); ++ error = device_create_file(&dev->dev, &dev_attr_srp); ++ error = device_create_file(&dev->dev, &dev_attr_buspower); ++ error = device_create_file(&dev->dev, &dev_attr_bussuspend); ++ error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en); ++ error = device_create_file(&dev->dev, &dev_attr_fr_interval); ++ error = device_create_file(&dev->dev, &dev_attr_busconnected); ++ error = device_create_file(&dev->dev, &dev_attr_gotgctl); ++ error = device_create_file(&dev->dev, &dev_attr_gusbcfg); ++ error = device_create_file(&dev->dev, &dev_attr_grxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_gpvndctl); ++ error = device_create_file(&dev->dev, &dev_attr_ggpio); ++ error = device_create_file(&dev->dev, &dev_attr_guid); ++ error = device_create_file(&dev->dev, &dev_attr_gsnpsid); ++ error = device_create_file(&dev->dev, &dev_attr_devspeed); ++ error = device_create_file(&dev->dev, &dev_attr_enumspeed); ++ error = device_create_file(&dev->dev, &dev_attr_hptxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_hprt0); ++ error = device_create_file(&dev->dev, &dev_attr_remote_wakeup); ++ error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn); ++ error = device_create_file(&dev->dev, &dev_attr_disconnect_us); ++ error = device_create_file(&dev->dev, &dev_attr_regdump); ++ error = device_create_file(&dev->dev, &dev_attr_spramdump); ++ error = device_create_file(&dev->dev, &dev_attr_hcddump); ++ error = device_create_file(&dev->dev, &dev_attr_hcd_frrem); ++ error = device_create_file(&dev->dev, &dev_attr_rd_reg_test); ++ error = device_create_file(&dev->dev, &dev_attr_wr_reg_test); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ error = device_create_file(&dev->dev, &dev_attr_lpm_response); ++ error = device_create_file(&dev->dev, &dev_attr_sleep_status); ++#endif ++} ++ ++/** ++ * Remove the device files ++ */ ++void dwc_otg_attr_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ) ++{ ++ device_remove_file(&dev->dev, &dev_attr_regoffset); ++ device_remove_file(&dev->dev, &dev_attr_regvalue); ++ device_remove_file(&dev->dev, &dev_attr_mode); ++ device_remove_file(&dev->dev, &dev_attr_hnpcapable); ++ device_remove_file(&dev->dev, &dev_attr_srpcapable); ++ device_remove_file(&dev->dev, &dev_attr_hsic_connect); ++ device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic); ++ device_remove_file(&dev->dev, &dev_attr_hnp); ++ device_remove_file(&dev->dev, &dev_attr_srp); ++ device_remove_file(&dev->dev, &dev_attr_buspower); ++ device_remove_file(&dev->dev, &dev_attr_bussuspend); ++ device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en); ++ device_remove_file(&dev->dev, &dev_attr_fr_interval); ++ device_remove_file(&dev->dev, &dev_attr_busconnected); ++ device_remove_file(&dev->dev, &dev_attr_gotgctl); ++ device_remove_file(&dev->dev, &dev_attr_gusbcfg); ++ device_remove_file(&dev->dev, &dev_attr_grxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_gnptxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_gpvndctl); ++ device_remove_file(&dev->dev, &dev_attr_ggpio); ++ device_remove_file(&dev->dev, &dev_attr_guid); ++ device_remove_file(&dev->dev, &dev_attr_gsnpsid); ++ device_remove_file(&dev->dev, &dev_attr_devspeed); ++ device_remove_file(&dev->dev, &dev_attr_enumspeed); ++ device_remove_file(&dev->dev, &dev_attr_hptxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_hprt0); ++ device_remove_file(&dev->dev, &dev_attr_remote_wakeup); ++ device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn); ++ device_remove_file(&dev->dev, &dev_attr_disconnect_us); ++ device_remove_file(&dev->dev, &dev_attr_regdump); ++ device_remove_file(&dev->dev, &dev_attr_spramdump); ++ device_remove_file(&dev->dev, &dev_attr_hcddump); ++ device_remove_file(&dev->dev, &dev_attr_hcd_frrem); ++ device_remove_file(&dev->dev, &dev_attr_rd_reg_test); ++ device_remove_file(&dev->dev, &dev_attr_wr_reg_test); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ device_remove_file(&dev->dev, &dev_attr_lpm_response); ++ device_remove_file(&dev->dev, &dev_attr_sleep_status); ++#endif ++} +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.h +@@ -0,0 +1,89 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $ ++ * $Revision: #13 $ ++ * $Date: 2010/06/21 $ ++ * $Change: 1532021 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_ATTR_H__) ++#define __DWC_OTG_ATTR_H__ ++ ++/** @file ++ * This file contains the interface to the Linux device attributes. ++ */ ++extern struct device_attribute dev_attr_regoffset; ++extern struct device_attribute dev_attr_regvalue; ++ ++extern struct device_attribute dev_attr_mode; ++extern struct device_attribute dev_attr_hnpcapable; ++extern struct device_attribute dev_attr_srpcapable; ++extern struct device_attribute dev_attr_hnp; ++extern struct device_attribute dev_attr_srp; ++extern struct device_attribute dev_attr_buspower; ++extern struct device_attribute dev_attr_bussuspend; ++extern struct device_attribute dev_attr_mode_ch_tim_en; ++extern struct device_attribute dev_attr_fr_interval; ++extern struct device_attribute dev_attr_busconnected; ++extern struct device_attribute dev_attr_gotgctl; ++extern struct device_attribute dev_attr_gusbcfg; ++extern struct device_attribute dev_attr_grxfsiz; ++extern struct device_attribute dev_attr_gnptxfsiz; ++extern struct device_attribute dev_attr_gpvndctl; ++extern struct device_attribute dev_attr_ggpio; ++extern struct device_attribute dev_attr_guid; ++extern struct device_attribute dev_attr_gsnpsid; ++extern struct device_attribute dev_attr_devspeed; ++extern struct device_attribute dev_attr_enumspeed; ++extern struct device_attribute dev_attr_hptxfsiz; ++extern struct device_attribute dev_attr_hprt0; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++extern struct device_attribute dev_attr_lpm_response; ++extern struct device_attribute devi_attr_sleep_status; ++#endif ++ ++void dwc_otg_attr_create( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++ ++void dwc_otg_attr_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++#endif +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c +@@ -0,0 +1,1876 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * This file contains the most of the CFI(Core Feature Interface) ++ * implementation for the OTG. ++ */ ++ ++#ifdef DWC_UTE_CFI ++ ++#include "dwc_otg_pcd.h" ++#include "dwc_otg_cfi.h" ++ ++/** This definition should actually migrate to the Portability Library */ ++#define DWC_CONSTANT_CPU_TO_LE16(x) (x) ++ ++extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex); ++ ++static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen); ++static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen, ++ struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req); ++static int cfi_set_feature_value(struct dwc_otg_pcd *pcd); ++static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_preproc_reset(struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep); ++ ++static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if); ++static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue); ++static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue); ++ ++static uint8_t resize_fifos(dwc_otg_core_if_t * core_if); ++ ++/** This is the header of the all features descriptor */ ++static cfi_all_features_header_t all_props_desc_header = { ++ .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100), ++ .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG), ++ .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9), ++}; ++ ++/** This is an array of statically allocated feature descriptors */ ++static cfi_feature_desc_header_t prop_descs[] = { ++ ++ /* FT_ID_DMA_MODE */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1), ++ }, ++ ++ /* FT_ID_DMA_BUFFER_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DMA_BUFF_ALIGN */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_DMA_CONCAT_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DMA_CIRCULAR */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_THRESHOLD_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DFIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RO, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_TX_FIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_RX_FIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ } ++}; ++ ++/** The table of feature names */ ++cfi_string_t prop_name_table[] = { ++ {FT_ID_DMA_MODE, "dma_mode"}, ++ {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"}, ++ {FT_ID_DMA_BUFF_ALIGN, "buffer_align"}, ++ {FT_ID_DMA_CONCAT_SETUP, "concat_setup"}, ++ {FT_ID_DMA_CIRCULAR, "buffer_circular"}, ++ {FT_ID_THRESHOLD_SETUP, "threshold_setup"}, ++ {FT_ID_DFIFO_DEPTH, "dfifo_depth"}, ++ {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"}, ++ {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"}, ++ {} ++}; ++ ++/************************************************************************/ ++ ++/** ++ * Returns the name of the feature by its ID ++ * or NULL if no featute ID matches. ++ * ++ */ ++const uint8_t *get_prop_name(uint16_t prop_id, int *len) ++{ ++ cfi_string_t *pstr; ++ *len = 0; ++ ++ for (pstr = prop_name_table; pstr && pstr->s; pstr++) { ++ if (pstr->id == prop_id) { ++ *len = DWC_STRLEN(pstr->s); ++ return pstr->s; ++ } ++ } ++ return NULL; ++} ++ ++/** ++ * This function handles all CFI specific control requests. ++ * ++ * Return a negative value to stall the DCE. ++ */ ++int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl) ++{ ++ int retval = 0; ++ dwc_otg_pcd_ep_t *ep = NULL; ++ cfiobject_t *cfi = pcd->cfi; ++ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd); ++ uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength); ++ uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue); ++ uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex); ++ uint32_t regaddr = 0; ++ uint32_t regval = 0; ++ ++ /* Save this Control Request in the CFI object. ++ * The data field will be assigned in the data stage completion CB function. ++ */ ++ cfi->ctrl_req = *ctrl; ++ cfi->ctrl_req.data = NULL; ++ ++ cfi->need_gadget_att = 0; ++ cfi->need_status_in_complete = 0; ++ ++ switch (ctrl->bRequest) { ++ case VEN_CORE_GET_FEATURES: ++ retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN); ++ if (retval >= 0) { ++ //dump_msg(cfi->buf_in.buf, retval); ++ ep = &pcd->ep0; ++ ++ retval = min((uint16_t) retval, wLen); ++ /* Transfer this buffer to the host through the EP0-IN EP */ ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = retval; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ } ++ retval = 0; ++ break; ++ ++ case VEN_CORE_GET_FEATURE: ++ CFI_INFO("VEN_CORE_GET_FEATURE\n"); ++ retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN, ++ pcd, ctrl); ++ if (retval >= 0) { ++ ep = &pcd->ep0; ++ ++ retval = min((uint16_t) retval, wLen); ++ /* Transfer this buffer to the host through the EP0-IN EP */ ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = retval; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ } ++ CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval); ++ dump_msg(cfi->buf_in.buf, retval); ++ break; ++ ++ case VEN_CORE_SET_FEATURE: ++ CFI_INFO("VEN_CORE_SET_FEATURE\n"); ++ /* Set up an XFER to get the data stage of the control request, ++ * which is the new value of the feature to be modified. ++ */ ++ ep = &pcd->ep0; ++ ep->dwc_ep.is_in = 0; ++ ep->dwc_ep.dma_addr = cfi->buf_out.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ /* Read the control write's data stage */ ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ retval = 0; ++ break; ++ ++ case VEN_CORE_RESET_FEATURES: ++ CFI_INFO("VEN_CORE_RESET_FEATURES\n"); ++ cfi->need_gadget_att = 1; ++ cfi->need_status_in_complete = 1; ++ retval = cfi_preproc_reset(pcd, ctrl); ++ CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval); ++ break; ++ ++ case VEN_CORE_ACTIVATE_FEATURES: ++ CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n"); ++ break; ++ ++ case VEN_CORE_READ_REGISTER: ++ CFI_INFO("VEN_CORE_READ_REGISTER\n"); ++ /* wValue optionally contains the HI WORD of the register offset and ++ * wIndex contains the LOW WORD of the register offset ++ */ ++ if (wValue == 0) { ++ /* @TODO - MAS - fix the access to the base field */ ++ regaddr = 0; ++ //regaddr = (uint32_t) pcd->otg_dev->os_dep.base; ++ //GET_CORE_IF(pcd)->co ++ regaddr |= wIndex; ++ } else { ++ regaddr = (wValue << 16) | wIndex; ++ } ++ ++ /* Read a 32-bit value of the memory at the regaddr */ ++ regval = DWC_READ_REG32((uint32_t *) regaddr); ++ ++ ep = &pcd->ep0; ++ dwc_memcpy(cfi->buf_in.buf, ®val, sizeof(uint32_t)); ++ ep->dwc_ep.is_in = 1; ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ cfi->need_gadget_att = 0; ++ retval = 0; ++ break; ++ ++ case VEN_CORE_WRITE_REGISTER: ++ CFI_INFO("VEN_CORE_WRITE_REGISTER\n"); ++ /* Set up an XFER to get the data stage of the control request, ++ * which is the new value of the register to be modified. ++ */ ++ ep = &pcd->ep0; ++ ep->dwc_ep.is_in = 0; ++ ep->dwc_ep.dma_addr = cfi->buf_out.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ /* Read the control write's data stage */ ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ retval = 0; ++ break; ++ ++ default: ++ retval = -DWC_E_NOT_SUPPORTED; ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function prepares the core features descriptors and copies its ++ * raw representation into the buffer . ++ * ++ * The buffer structure is as follows: ++ * all_features_header (8 bytes) ++ * features_#1 (8 bytes + feature name string length) ++ * features_#2 (8 bytes + feature name string length) ++ * ..... ++ * features_#n - where n=the total count of feature descriptors ++ */ ++static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen) ++{ ++ cfi_feature_desc_header_t *prop_hdr = prop_descs; ++ cfi_feature_desc_header_t *prop; ++ cfi_all_features_header_t *all_props_hdr = &all_props_desc_header; ++ cfi_all_features_header_t *tmp; ++ uint8_t *tmpbuf = buf; ++ const uint8_t *pname = NULL; ++ int i, j, namelen = 0, totlen; ++ ++ /* Prepare and copy the core features into the buffer */ ++ CFI_INFO("%s:\n", __func__); ++ ++ tmp = (cfi_all_features_header_t *) tmpbuf; ++ *tmp = *all_props_hdr; ++ tmpbuf += CFI_ALL_FEATURES_HDR_LEN; ++ ++ j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t); ++ for (i = 0; i < j; i++, prop_hdr++) { ++ pname = get_prop_name(prop_hdr->wFeatureID, &namelen); ++ prop = (cfi_feature_desc_header_t *) tmpbuf; ++ *prop = *prop_hdr; ++ ++ prop->bNameLen = namelen; ++ prop->wLength = ++ DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN + ++ namelen); ++ ++ tmpbuf += CFI_FEATURE_DESC_HDR_LEN; ++ dwc_memcpy(tmpbuf, pname, namelen); ++ tmpbuf += namelen; ++ } ++ ++ totlen = tmpbuf - buf; ++ ++ if (totlen > 0) { ++ tmp = (cfi_all_features_header_t *) buf; ++ tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen); ++ } ++ ++ return totlen; ++} ++ ++/** ++ * This function releases all the dynamic memory in the CFI object. ++ */ ++static void cfi_release(cfiobject_t * cfiobj) ++{ ++ cfi_ep_t *cfiep; ++ dwc_list_link_t *tmp; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ if (cfiobj->buf_in.buf) { ++ DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf, ++ cfiobj->buf_in.addr); ++ cfiobj->buf_in.buf = NULL; ++ } ++ ++ if (cfiobj->buf_out.buf) { ++ DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf, ++ cfiobj->buf_out.addr); ++ cfiobj->buf_out.buf = NULL; ++ } ++ ++ /* Free the Buffer Setup values for each EP */ ++ //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ cfi_free_ep_bs_dyn_data(cfiep); ++ } ++} ++ ++/** ++ * This function frees the dynamically allocated EP buffer setup data. ++ */ ++static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep) ++{ ++ if (cfiep->bm_sg) { ++ DWC_FREE(cfiep->bm_sg); ++ cfiep->bm_sg = NULL; ++ } ++ ++ if (cfiep->bm_align) { ++ DWC_FREE(cfiep->bm_align); ++ cfiep->bm_align = NULL; ++ } ++ ++ if (cfiep->bm_concat) { ++ if (NULL != cfiep->bm_concat->wTxBytes) { ++ DWC_FREE(cfiep->bm_concat->wTxBytes); ++ cfiep->bm_concat->wTxBytes = NULL; ++ } ++ DWC_FREE(cfiep->bm_concat); ++ cfiep->bm_concat = NULL; ++ } ++} ++ ++/** ++ * This function initializes the default values of the features ++ * for a specific endpoint and should be called only once when ++ * the EP is enabled first time. ++ */ ++static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep) ++{ ++ int retval = 0; ++ ++ cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t)); ++ if (NULL == cfiep->bm_sg) { ++ CFI_INFO("Failed to allocate memory for SG feature value\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ ++ /* For the Concatenation feature's default value we do not allocate ++ * memory for the wTxBytes field - it will be done in the set_feature_value ++ * request handler. ++ */ ++ cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t)); ++ if (NULL == cfiep->bm_concat) { ++ CFI_INFO ++ ("Failed to allocate memory for CONCATENATION feature value\n"); ++ DWC_FREE(cfiep->bm_sg); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); ++ ++ cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t)); ++ if (NULL == cfiep->bm_align) { ++ CFI_INFO ++ ("Failed to allocate memory for Alignment feature value\n"); ++ DWC_FREE(cfiep->bm_sg); ++ DWC_FREE(cfiep->bm_concat); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t)); ++ ++ return retval; ++} ++ ++/** ++ * The callback function that notifies the CFI on the activation of ++ * an endpoint in the PCD. The following steps are done in this function: ++ * ++ * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's ++ * active endpoint) ++ * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP ++ * Set the Buffer Mode to standard ++ * Initialize the default values for all EP modes (SG, Circular, Concat, Align) ++ * Add the cfi_ep_t object to the list of active endpoints in the CFI object ++ */ ++static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep) ++{ ++ cfi_ep_t *cfiep; ++ int retval = -DWC_E_NOT_SUPPORTED; ++ ++ CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__, ++ "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress); ++ /* MAS - Check whether this endpoint already is in the list */ ++ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep); ++ ++ if (NULL == cfiep) { ++ /* Allocate a cfi_ep_t object */ ++ cfiep = DWC_ALLOC(sizeof(cfi_ep_t)); ++ if (NULL == cfiep) { ++ CFI_INFO ++ ("Unable to allocate memory for in function %s\n", ++ __func__); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep, 0, sizeof(cfi_ep_t)); ++ ++ /* Save the dwc_otg_pcd_ep pointer in the cfiep object */ ++ cfiep->ep = ep; ++ ++ /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */ ++ ep->dwc_ep.descs = ++ DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP * ++ sizeof(dwc_otg_dma_desc_t), ++ &ep->dwc_ep.descs_dma_addr); ++ ++ if (NULL == ep->dwc_ep.descs) { ++ DWC_FREE(cfiep); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_LIST_INIT(&cfiep->lh); ++ ++ /* Set the buffer mode to BM_STANDARD. It will be modified ++ * when building descriptors for a specific buffer mode */ ++ ep->dwc_ep.buff_mode = BM_STANDARD; ++ ++ /* Create and initialize the default values for this EP's Buffer modes */ ++ if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0) ++ return retval; ++ ++ /* Add the cfi_ep_t object to the CFI object's list of active endpoints */ ++ DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh); ++ retval = 0; ++ } else { /* The sought EP already is in the list */ ++ CFI_INFO("%s: The sought EP already is in the list\n", ++ __func__); ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function is called when the data stage of a 3-stage Control Write request ++ * is complete. ++ * ++ */ ++static int cfi_ctrl_write_complete(struct cfiobject *cfi, ++ struct dwc_otg_pcd *pcd) ++{ ++ uint32_t addr, reg_value; ++ uint16_t wIndex, wValue; ++ uint8_t bRequest; ++ uint8_t *buf = cfi->buf_out.buf; ++ //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved; ++ struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req; ++ int retval = -DWC_E_NOT_SUPPORTED; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ bRequest = ctrl_req->bRequest; ++ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex); ++ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue); ++ ++ /* ++ * Save the pointer to the data stage in the ctrl_req's field. ++ * The request should be already saved in the command stage by now. ++ */ ++ ctrl_req->data = cfi->buf_out.buf; ++ cfi->need_status_in_complete = 0; ++ cfi->need_gadget_att = 0; ++ ++ switch (bRequest) { ++ case VEN_CORE_WRITE_REGISTER: ++ /* The buffer contains raw data of the new value for the register */ ++ reg_value = *((uint32_t *) buf); ++ if (wValue == 0) { ++ addr = 0; ++ //addr = (uint32_t) pcd->otg_dev->os_dep.base; ++ addr += wIndex; ++ } else { ++ addr = (wValue << 16) | wIndex; ++ } ++ ++ //writel(reg_value, addr); ++ ++ retval = 0; ++ cfi->need_status_in_complete = 1; ++ break; ++ ++ case VEN_CORE_SET_FEATURE: ++ /* The buffer contains raw data of the new value of the feature */ ++ retval = cfi_set_feature_value(pcd); ++ if (retval < 0) ++ return retval; ++ ++ cfi->need_status_in_complete = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function builds the DMA descriptors for the SG buffer mode. ++ */ ++static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ int i; ++ uint32_t txsize, off; ++ ++ txsize = sgval->wSize; ++ off = sgval->bOffset; ++ ++// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", ++// __func__, cfiep->ep->ep.name, txsize, off); ++ ++ for (i = 0; i < sgval->bCount; i++) { ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->buf = buff_addr; ++ desc->status.b.l = 0; ++ desc->status.b.ioc = 0; ++ desc->status.b.sp = 0; ++ desc->status.b.bytes = txsize; ++ desc->status.b.bs = BS_HOST_READY; ++ ++ /* Set the next address of the buffer */ ++ buff_addr += txsize + off; ++ desc_last = desc; ++ desc++; ++ } ++ ++ /* Set the last, ioc and sp bits on the Last DMA Descriptor */ ++ desc_last->status.b.l = 1; ++ desc_last->status.b.ioc = 1; ++ desc_last->status.b.sp = ep->dwc_ep.sent_zlp; ++ /* Save the last DMA descriptor pointer */ ++ cfiep->dma_desc_last = desc_last; ++ cfiep->desc_count = sgval->bCount; ++} ++ ++/** ++ * This function builds the DMA descriptors for the Concatenation buffer mode. ++ */ ++static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ int i; ++ uint16_t *txsize; ++ ++ txsize = concatval->wTxBytes; ++ ++ for (i = 0; i < concatval->hdr.bDescCount; i++) { ++ desc->buf = buff_addr; ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->status.b.l = 0; ++ desc->status.b.ioc = 0; ++ desc->status.b.sp = 0; ++ desc->status.b.bytes = *txsize; ++ desc->status.b.bs = BS_HOST_READY; ++ ++ txsize++; ++ /* Set the next address of the buffer */ ++ buff_addr += UGETW(ep->desc->wMaxPacketSize); ++ desc_last = desc; ++ desc++; ++ } ++ ++ /* Set the last, ioc and sp bits on the Last DMA Descriptor */ ++ desc_last->status.b.l = 1; ++ desc_last->status.b.ioc = 1; ++ desc_last->status.b.sp = ep->dwc_ep.sent_zlp; ++ cfiep->dma_desc_last = desc_last; ++ cfiep->desc_count = concatval->hdr.bDescCount; ++} ++ ++/** ++ * This function builds the DMA descriptors for the Circular buffer mode ++ */ ++static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ /* @todo: MAS - add implementation when this feature needs to be tested */ ++} ++ ++/** ++ * This function builds the DMA descriptors for the Alignment buffer mode ++ */ ++static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_align_buffer_setup_t *alignval = cfiep->bm_align; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->status.b.l = 1; ++ desc->status.b.ioc = 1; ++ desc->status.b.sp = ep->dwc_ep.sent_zlp; ++ desc->status.b.bytes = req->length; ++ /* Adjust the buffer alignment */ ++ desc->buf = (buff_addr + alignval->bAlign); ++ desc->status.b.bs = BS_HOST_READY; ++ cfiep->dma_desc_last = desc; ++ cfiep->desc_count = 1; ++} ++ ++/** ++ * This function builds the DMA descriptors chain for different modes of the ++ * buffer setup of an endpoint. ++ */ ++static void cfi_build_descriptors(struct cfiobject *cfi, ++ struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep, ++ dwc_otg_pcd_request_t * req) ++{ ++ cfi_ep_t *cfiep; ++ ++ /* Get the cfiep by the dwc_otg_pcd_ep */ ++ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Unable to find a matching active endpoint\n", ++ __func__); ++ return; ++ } ++ ++ cfiep->xfer_len = req->length; ++ ++ /* Iterate through all the DMA descriptors */ ++ switch (cfiep->ep->dwc_ep.buff_mode) { ++ case BM_SG: ++ cfi_build_sg_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_CONCAT: ++ cfi_build_concat_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_CIRCULAR: ++ cfi_build_circ_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_ALIGN: ++ cfi_build_align_descs(cfi, cfiep, req); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++/** ++ * Allocate DMA buffer for different Buffer modes. ++ */ ++static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep, dma_addr_t * dma, ++ unsigned size, gfp_t flags) ++{ ++ return DWC_DMA_ALLOC(size, dma); ++} ++ ++/** ++ * This function initializes the CFI object. ++ */ ++int init_cfi(cfiobject_t * cfiobj) ++{ ++ CFI_INFO("%s\n", __func__); ++ ++ /* Allocate a buffer for IN XFERs */ ++ cfiobj->buf_in.buf = ++ DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr); ++ if (NULL == cfiobj->buf_in.buf) { ++ CFI_INFO("Unable to allocate buffer for INs\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Allocate a buffer for OUT XFERs */ ++ cfiobj->buf_out.buf = ++ DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr); ++ if (NULL == cfiobj->buf_out.buf) { ++ CFI_INFO("Unable to allocate buffer for OUT\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Initialize the callback function pointers */ ++ cfiobj->ops.release = cfi_release; ++ cfiobj->ops.ep_enable = cfi_ep_enable; ++ cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete; ++ cfiobj->ops.build_descriptors = cfi_build_descriptors; ++ cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf; ++ ++ /* Initialize the list of active endpoints in the CFI object */ ++ DWC_LIST_INIT(&cfiobj->active_eps); ++ ++ return 0; ++} ++ ++/** ++ * This function reads the required feature's current value into the buffer ++ * ++ * @retval: Returns negative as error, or the data length of the feature ++ */ ++static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen, ++ struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd); ++ uint16_t dfifo, rxfifo, txfifo; ++ ++ switch (ctrl_req->wIndex) { ++ /* Whether the DDMA is enabled or not */ ++ case FT_ID_DMA_MODE: ++ *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0; ++ retval = 1; ++ break; ++ ++ case FT_ID_DMA_BUFFER_SETUP: ++ retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ retval = cfi_ep_get_align_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_CIRCULAR: ++ CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n"); ++ break; ++ ++ case FT_ID_THRESHOLD_SETUP: ++ CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n"); ++ break; ++ ++ case FT_ID_DFIFO_DEPTH: ++ dfifo = get_dfifo_size(coreif); ++ *((uint16_t *) buf) = dfifo; ++ retval = sizeof(uint16_t); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ retval = get_txfifo_size(pcd, ctrl_req->wValue); ++ if (retval >= 0) { ++ txfifo = retval; ++ *((uint16_t *) buf) = txfifo; ++ retval = sizeof(uint16_t); ++ } ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ retval = get_rxfifo_size(coreif, ctrl_req->wValue); ++ if (retval >= 0) { ++ rxfifo = retval; ++ *((uint16_t *) buf) = rxfifo; ++ retval = sizeof(uint16_t); ++ } ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function resets the SG for the specified EP to its default value ++ */ ++static int cfi_reset_sg_val(cfi_ep_t * cfiep) ++{ ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets the Alignment for the specified EP to its default value ++ */ ++static int cfi_reset_align_val(cfi_ep_t * cfiep) ++{ ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets the Concatenation for the specified EP to its default value ++ * This function will also set the value of the wTxBytes field to NULL after ++ * freeing the memory previously allocated for this field. ++ */ ++static int cfi_reset_concat_val(cfi_ep_t * cfiep) ++{ ++ /* First we need to free the wTxBytes field */ ++ if (cfiep->bm_concat->wTxBytes) { ++ DWC_FREE(cfiep->bm_concat->wTxBytes); ++ cfiep->bm_concat->wTxBytes = NULL; ++ } ++ ++ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets all the buffer setups of the specified endpoint ++ */ ++static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep) ++{ ++ cfi_reset_sg_val(cfiep); ++ cfi_reset_align_val(cfiep); ++ cfi_reset_concat_val(cfiep); ++ return 0; ++} ++ ++static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr, ++ uint8_t rx_rst, uint8_t tx_rst) ++{ ++ int retval = -DWC_E_INVALID; ++ uint16_t tx_siz[15]; ++ uint16_t rx_siz = 0; ++ dwc_otg_pcd_ep_t *ep = NULL; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ ++ if (rx_rst) { ++ rx_siz = params->dev_rx_fifo_size; ++ params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz; ++ } ++ ++ if (tx_rst) { ++ if (ep_addr == 0) { ++ int i; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ tx_siz[i] = ++ core_if->core_params->dev_tx_fifo_size[i]; ++ core_if->core_params->dev_tx_fifo_size[i] = ++ core_if->init_txfsiz[i]; ++ } ++ } else { ++ ++ ep = get_ep_by_addr(pcd, ep_addr); ++ ++ if (NULL == ep) { ++ CFI_INFO ++ ("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, ep_addr); ++ return -DWC_E_INVALID; ++ } ++ ++ tx_siz[0] = ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - ++ 1]; ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = ++ GET_CORE_IF(pcd)->init_txfsiz[ep-> ++ dwc_ep.tx_fifo_num - ++ 1]; ++ } ++ } ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO ++ ("%s: Error resetting the feature Reset All(FIFO size)\n", ++ __func__); ++ if (rx_rst) { ++ params->dev_rx_fifo_size = rx_siz; ++ } ++ ++ if (tx_rst) { ++ if (ep_addr == 0) { ++ int i; ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++ i++) { ++ core_if-> ++ core_params->dev_tx_fifo_size[i] = ++ tx_siz[i]; ++ } ++ } else { ++ params->dev_tx_fifo_size[ep-> ++ dwc_ep.tx_fifo_num - ++ 1] = tx_siz[0]; ++ } ++ } ++ retval = -DWC_E_INVALID; ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1); ++ if (retval < 0) { ++ return retval; ++ } ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_ep_reset_all_setup_vals(cfiep); ++ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD; ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_ep_reset_all_setup_vals(cfiep); ++ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD; ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Reset All\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd, ++ uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_sg_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_sg_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Buffer Setup\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_concat_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_concat_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Concatenation Value\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_align_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_align_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Aliignment Value\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++ ++} ++ ++static int cfi_preproc_reset(struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = 0; ++ ++ switch (req->wIndex) { ++ case 0: ++ /* Reset all features */ ++ retval = cfi_handle_reset_all(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_BUFFER_SETUP: ++ /* Reset the SG buffer setup */ ++ retval = ++ cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ /* Reset the Concatenation buffer setup */ ++ retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ /* Reset the Alignment buffer setup */ ++ retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ retval = ++ cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1); ++ pcd->cfi->need_gadget_att = 0; ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0); ++ pcd->cfi->need_gadget_att = 0; ++ break; ++ default: ++ break; ++ } ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the SG buffer setup. ++ */ ++static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ uint8_t inaddr, outaddr; ++ cfi_ep_t *epin, *epout; ++ ddma_sg_buffer_setup_t *psgval; ++ uint32_t desccount, size; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ psgval = (ddma_sg_buffer_setup_t *) buf; ++ desccount = (uint32_t) psgval->bCount; ++ size = (uint32_t) psgval->wSize; ++ ++ /* Check the DMA descriptor count */ ++ if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) { ++ CFI_INFO ++ ("%s: The count of DMA Descriptors should be between 1 and %d\n", ++ __func__, MAX_DMA_DESCS_PER_EP); ++ return -DWC_E_INVALID; ++ } ++ ++ /* Check the DMA descriptor count */ ++ ++ if (size == 0) { ++ ++ CFI_INFO("%s: The transfer size should be at least 1 byte\n", ++ __func__); ++ ++ return -DWC_E_INVALID; ++ ++ } ++ ++ inaddr = psgval->bInEndpointAddress; ++ outaddr = psgval->bOutEndpointAddress; ++ ++ epin = get_cfi_ep_by_addr(pcd->cfi, inaddr); ++ epout = get_cfi_ep_by_addr(pcd->cfi, outaddr); ++ ++ if (NULL == epin || NULL == epout) { ++ CFI_INFO ++ ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n", ++ __func__, inaddr, outaddr); ++ return -DWC_E_INVALID; ++ } ++ ++ epin->ep->dwc_ep.buff_mode = BM_SG; ++ dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t)); ++ ++ epout->ep->dwc_ep.buff_mode = BM_SG; ++ dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t)); ++ ++ return 0; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ cfi_ep_t *ep; ++ uint8_t addr; ++ ddma_align_buffer_setup_t *palignval; ++ ++ palignval = (ddma_align_buffer_setup_t *) buf; ++ addr = palignval->bEndpointAddress; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ ++ ep->ep->dwc_ep.buff_mode = BM_ALIGN; ++ dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t)); ++ ++ return 0; ++} ++ ++/** ++ * This function sets a new value for the Concatenation buffer setup. ++ */ ++static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ uint8_t addr; ++ cfi_ep_t *ep; ++ struct _ddma_concat_buffer_setup_hdr *pConcatValHdr; ++ uint16_t *pVals; ++ uint32_t desccount; ++ int i; ++ uint16_t mps; ++ ++ pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf; ++ desccount = (uint32_t) pConcatValHdr->bDescCount; ++ pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN); ++ ++ /* Check the DMA descriptor count */ ++ if (desccount > MAX_DMA_DESCS_PER_EP) { ++ CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n", ++ __func__, MAX_DMA_DESCS_PER_EP); ++ return -DWC_E_INVALID; ++ } ++ ++ addr = pConcatValHdr->bEndpointAddress; ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ ++ mps = UGETW(ep->ep->desc->wMaxPacketSize); ++ ++#if 0 ++ for (i = 0; i < desccount; i++) { ++ CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]); ++ } ++ CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps); ++#endif ++ ++ /* Check the wTxSizes to be less than or equal to the mps */ ++ for (i = 0; i < desccount; i++) { ++ if (pVals[i] > mps) { ++ CFI_INFO ++ ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n", ++ __func__, i, pVals[i]); ++ return -DWC_E_INVALID; ++ } ++ } ++ ++ ep->ep->dwc_ep.buff_mode = BM_CONCAT; ++ dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN); ++ ++ /* Free the previously allocated storage for the wTxBytes */ ++ if (ep->bm_concat->wTxBytes) { ++ DWC_FREE(ep->bm_concat->wTxBytes); ++ } ++ ++ /* Allocate a new storage for the wTxBytes field */ ++ ep->bm_concat->wTxBytes = ++ DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount); ++ if (NULL == ep->bm_concat->wTxBytes) { ++ CFI_INFO("%s: Unable to allocate memory\n", __func__); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Copy the new values into the wTxBytes filed */ ++ dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN, ++ sizeof(uint16_t) * pConcatValHdr->bDescCount); ++ ++ return 0; ++} ++ ++/** ++ * This function calculates the total of all FIFO sizes ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint16_t dfifo_total = 0; ++ int i; ++ ++ /* The shared RxFIFO size */ ++ dfifo_total = ++ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size; ++ ++ /* Add up each TxFIFO size to the total */ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dfifo_total += params->dev_tx_fifo_size[i]; ++ } ++ ++ return dfifo_total; ++} ++ ++/** ++ * This function returns Rx FIFO size ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue) ++{ ++ switch (wValue >> 8) { ++ case 0: ++ return (core_if->pwron_rxfsiz < ++ 32768) ? core_if->pwron_rxfsiz : 32768; ++ break; ++ case 1: ++ return core_if->core_params->dev_rx_fifo_size; ++ break; ++ default: ++ return -DWC_E_INVALID; ++ break; ++ } ++} ++ ++/** ++ * This function returns Tx FIFO size for IN EP ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_ep_by_addr(pcd, wValue & 0xff); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, wValue & 0xff); ++ return -DWC_E_INVALID; ++ } ++ ++ if (!ep->dwc_ep.is_in) { ++ CFI_INFO ++ ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n", ++ __func__, wValue & 0xff); ++ return -DWC_E_INVALID; ++ } ++ ++ switch (wValue >> 8) { ++ case 0: ++ return (GET_CORE_IF(pcd)->pwron_txfsiz ++ [ep->dwc_ep.tx_fifo_num - 1] < ++ 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep-> ++ dwc_ep.tx_fifo_num ++ - 1] : 32768; ++ break; ++ case 1: ++ return GET_CORE_IF(pcd)->core_params-> ++ dev_tx_fifo_size[ep->dwc_ep.num - 1]; ++ break; ++ default: ++ return -DWC_E_INVALID; ++ break; ++ } ++} ++ ++/** ++ * This function checks if the submitted combination of ++ * device mode FIFO sizes is possible or not. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return 1 if possible, 0 otherwise. ++ * ++ */ ++static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if) ++{ ++ uint16_t dfifo_actual = 0; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint16_t start_addr = 0; ++ int i; ++ ++ dfifo_actual = ++ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dfifo_actual += params->dev_tx_fifo_size[i]; ++ } ++ ++ if (dfifo_actual > core_if->total_fifo_size) { ++ return 0; ++ } ++ ++ if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16) ++ return 0; ++ ++ if (params->dev_nperio_tx_fifo_size > 32768 ++ || params->dev_nperio_tx_fifo_size < 16) ++ return 0; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ if (params->dev_tx_fifo_size[i] > 768 ++ || params->dev_tx_fifo_size[i] < 4) ++ return 0; ++ } ++ ++ if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz) ++ return 0; ++ start_addr = params->dev_rx_fifo_size; ++ ++ if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz) ++ return 0; ++ start_addr += params->dev_nperio_tx_fifo_size; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i]) ++ return 0; ++ start_addr += params->dev_tx_fifo_size[i]; ++ } ++ ++ return 1; ++} ++ ++/** ++ * This function resizes Device mode FIFOs ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return 1 if successful, 0 otherwise ++ * ++ */ ++static uint8_t resize_fifos(dwc_otg_core_if_t * core_if) ++{ ++ int i = 0; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint32_t rx_fifo_size; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t txfifosize[15]; ++ ++ uint32_t rx_fsz_bak; ++ uint32_t nptxfsz_bak; ++ uint32_t txfsz_bak[15]; ++ ++ uint16_t start_address; ++ uint8_t retval = 1; ++ ++ if (!check_fifo_sizes(core_if)) { ++ return 0; ++ } ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz); ++ rx_fifo_size = params->dev_rx_fifo_size; ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size); ++ ++ /* ++ * Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_tx_fifo_size array and the FIFO size registers in ++ * the dtxfsiz array run from 0 to 14. ++ */ ++ ++ /* Non-periodic Tx FIFO */ ++ nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz); ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ start_address = params->dev_rx_fifo_size; ++ nptxfifosize.b.startaddr = start_address; ++ ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ ++ start_address += nptxfifosize.b.depth; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]); ++ ++ txfifosize[i].b.depth = params->dev_tx_fifo_size[i]; ++ txfifosize[i].b.startaddr = start_address; ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], ++ txfifosize[i].d32); ++ ++ start_address += txfifosize[i].b.depth; ++ } ++ ++ /** Check if register values are set correctly */ ++ if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) { ++ retval = 0; ++ } ++ ++ if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) { ++ retval = 0; ++ } ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ if (txfifosize[i].d32 != ++ DWC_READ_REG32(&global_regs->dtxfsiz[i])) { ++ retval = 0; ++ } ++ } ++ ++ /** If register values are not set correctly, reset old values */ ++ if (retval == 0) { ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak); ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak); ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], ++ txfsz_bak[i]); ++ } ++ } ++ } else { ++ return 0; ++ } ++ ++ /* Flush the FIFOs */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd) ++{ ++ int retval; ++ uint32_t fsiz; ++ uint16_t size; ++ uint16_t ep_addr; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ tx_fifo_size_setup_t *ptxfifoval; ++ ++ ptxfifoval = (tx_fifo_size_setup_t *) buf; ++ ep_addr = ptxfifoval->bEndpointAddress; ++ size = ptxfifoval->wDepth; ++ ++ ep = get_ep_by_addr(pcd, ep_addr); ++ ++ CFI_INFO ++ ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n", ++ __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, ep_addr); ++ return -DWC_E_INVALID; ++ } ++ ++ fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1]; ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size; ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO ++ ("%s: Error setting the feature Tx FIFO Size for EP%d\n", ++ __func__, ep_addr); ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz; ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd) ++{ ++ int retval; ++ uint32_t fsiz; ++ uint16_t size; ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ rx_fifo_size_setup_t *prxfifoval; ++ ++ prxfifoval = (rx_fifo_size_setup_t *) buf; ++ size = prxfifoval->wDepth; ++ ++ fsiz = params->dev_rx_fifo_size; ++ params->dev_rx_fifo_size = size; ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO("%s: Error setting the feature Rx FIFO Size\n", ++ __func__); ++ params->dev_rx_fifo_size = fsiz; ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function reads the SG of an EP's buffer setup into the buffer buf ++ */ ++static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN); ++ retval = BS_SG_VAL_DESC_LEN; ++ return retval; ++} ++ ++/** ++ * This function reads the Concatenation value of an EP's buffer mode into ++ * the buffer buf ++ */ ++static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ uint8_t desc_count; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ /* Copy the header to the buffer */ ++ dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN); ++ /* Advance the buffer pointer by the header size */ ++ buf += BS_CONCAT_VAL_HDR_LEN; ++ ++ desc_count = ep->bm_concat->hdr.bDescCount; ++ /* Copy alll the wTxBytes to the buffer */ ++ dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count); ++ ++ retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count; ++ return retval; ++} ++ ++/** ++ * This function reads the buffer Alignment value of an EP's buffer mode into ++ * the buffer buf ++ * ++ * @return The total number of bytes copied to the buffer or negative error code. ++ */ ++static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN); ++ retval = BS_ALIGN_VAL_HDR_LEN; ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the specified feature ++ * ++ * @param pcd A pointer to the PCD object ++ * ++ * @return 0 if successful, negative error code otherwise to stall the DCE. ++ */ ++static int cfi_set_feature_value(struct dwc_otg_pcd *pcd) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ uint16_t wIndex, wValue; ++ uint8_t bRequest; ++ struct dwc_otg_core_if *coreif; ++ cfiobject_t *cfi = pcd->cfi; ++ struct cfi_usb_ctrlrequest *ctrl_req; ++ uint8_t *buf; ++ ctrl_req = &cfi->ctrl_req; ++ ++ buf = pcd->cfi->ctrl_req.data; ++ ++ coreif = GET_CORE_IF(pcd); ++ bRequest = ctrl_req->bRequest; ++ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex); ++ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue); ++ ++ /* See which feature is to be modified */ ++ switch (wIndex) { ++ case FT_ID_DMA_BUFFER_SETUP: ++ /* Modify the feature */ ++ if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0) ++ return retval; ++ ++ /* And send this request to the gadget */ ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ /* Modify the feature */ ++ if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_CIRCULAR: ++ CFI_INFO("FT_ID_DMA_CIRCULAR\n"); ++ break; ++ ++ case FT_ID_THRESHOLD_SETUP: ++ CFI_INFO("FT_ID_THRESHOLD_SETUP\n"); ++ break; ++ ++ case FT_ID_DFIFO_DEPTH: ++ CFI_INFO("FT_ID_DFIFO_DEPTH\n"); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ CFI_INFO("FT_ID_TX_FIFO_DEPTH\n"); ++ if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 0; ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ CFI_INFO("FT_ID_RX_FIFO_DEPTH\n"); ++ if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 0; ++ break; ++ } ++ ++ return retval; ++} ++ ++#endif //DWC_UTE_CFI +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h +@@ -0,0 +1,320 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_CFI_H__) ++#define __DWC_OTG_CFI_H__ ++ ++#include "dwc_otg_pcd.h" ++#include "dwc_cfi_common.h" ++ ++/** ++ * @file ++ * This file contains the CFI related OTG PCD specific common constants, ++ * interfaces(functions and macros) and data structures.The CFI Protocol is an ++ * optional interface for internal testing purposes that a DUT may implement to ++ * support testing of configurable features. ++ * ++ */ ++ ++struct dwc_otg_pcd; ++struct dwc_otg_pcd_ep; ++ ++/** OTG CFI Features (properties) ID constants */ ++/** This is a request for all Core Features */ ++#define FT_ID_DMA_MODE 0x0001 ++#define FT_ID_DMA_BUFFER_SETUP 0x0002 ++#define FT_ID_DMA_BUFF_ALIGN 0x0003 ++#define FT_ID_DMA_CONCAT_SETUP 0x0004 ++#define FT_ID_DMA_CIRCULAR 0x0005 ++#define FT_ID_THRESHOLD_SETUP 0x0006 ++#define FT_ID_DFIFO_DEPTH 0x0007 ++#define FT_ID_TX_FIFO_DEPTH 0x0008 ++#define FT_ID_RX_FIFO_DEPTH 0x0009 ++ ++/**********************************************************/ ++#define CFI_INFO_DEF ++ ++#ifdef CFI_INFO_DEF ++#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt); ++#else ++#define CFI_INFO(fmt...) ++#endif ++ ++#define min(x,y) ({ \ ++ x < y ? x : y; }) ++ ++#define max(x,y) ({ \ ++ x > y ? x : y; }) ++ ++/** ++ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is ++ * also used for setting up a buffer for Circular DDMA. ++ */ ++struct _ddma_sg_buffer_setup { ++#define BS_SG_VAL_DESC_LEN 6 ++ /* The OUT EP address */ ++ uint8_t bOutEndpointAddress; ++ /* The IN EP address */ ++ uint8_t bInEndpointAddress; ++ /* Number of bytes to put between transfer segments (must be DWORD boundaries) */ ++ uint8_t bOffset; ++ /* The number of transfer segments (a DMA descriptors per each segment) */ ++ uint8_t bCount; ++ /* Size (in byte) of each transfer segment */ ++ uint16_t wSize; ++} __attribute__ ((packed)); ++typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t; ++ ++/** Descriptor DMA Concatenation Buffer setup structure */ ++struct _ddma_concat_buffer_setup_hdr { ++#define BS_CONCAT_VAL_HDR_LEN 4 ++ /* The endpoint for which the buffer is to be set up */ ++ uint8_t bEndpointAddress; ++ /* The count of descriptors to be used */ ++ uint8_t bDescCount; ++ /* The total size of the transfer */ ++ uint16_t wSize; ++} __attribute__ ((packed)); ++typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t; ++ ++/** Descriptor DMA Concatenation Buffer setup structure */ ++struct _ddma_concat_buffer_setup { ++ /* The SG header */ ++ ddma_concat_buffer_setup_hdr_t hdr; ++ ++ /* The XFER sizes pointer (allocated dynamically) */ ++ uint16_t *wTxBytes; ++} __attribute__ ((packed)); ++typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t; ++ ++/** Descriptor DMA Alignment Buffer setup structure */ ++struct _ddma_align_buffer_setup { ++#define BS_ALIGN_VAL_HDR_LEN 2 ++ uint8_t bEndpointAddress; ++ uint8_t bAlign; ++} __attribute__ ((packed)); ++typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t; ++ ++/** Transmit FIFO Size setup structure */ ++struct _tx_fifo_size_setup { ++ uint8_t bEndpointAddress; ++ uint16_t wDepth; ++} __attribute__ ((packed)); ++typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t; ++ ++/** Transmit FIFO Size setup structure */ ++struct _rx_fifo_size_setup { ++ uint16_t wDepth; ++} __attribute__ ((packed)); ++typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t; ++ ++/** ++ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest ++ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer ++ * to the data returned in the data stage of a 3-stage Control Write requests. ++ */ ++struct cfi_usb_ctrlrequest { ++ uint8_t bRequestType; ++ uint8_t bRequest; ++ uint16_t wValue; ++ uint16_t wIndex; ++ uint16_t wLength; ++ uint8_t *data; ++} UPACKED; ++ ++/*---------------------------------------------------------------------------*/ ++ ++/** ++ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. ++ * This structure is used to store the buffer setup data for any ++ * enabled endpoint in the PCD. ++ */ ++struct cfi_ep { ++ /* Entry for the list container */ ++ dwc_list_link_t lh; ++ /* Pointer to the active PCD endpoint structure */ ++ struct dwc_otg_pcd_ep *ep; ++ /* The last descriptor in the chain of DMA descriptors of the endpoint */ ++ struct dwc_otg_dma_desc *dma_desc_last; ++ /* The SG feature value */ ++ ddma_sg_buffer_setup_t *bm_sg; ++ /* The Circular feature value */ ++ ddma_sg_buffer_setup_t *bm_circ; ++ /* The Concatenation feature value */ ++ ddma_concat_buffer_setup_t *bm_concat; ++ /* The Alignment feature value */ ++ ddma_align_buffer_setup_t *bm_align; ++ /* XFER length */ ++ uint32_t xfer_len; ++ /* ++ * Count of DMA descriptors currently used. ++ * The total should not exceed the MAX_DMA_DESCS_PER_EP value ++ * defined in the dwc_otg_cil.h ++ */ ++ uint32_t desc_count; ++}; ++typedef struct cfi_ep cfi_ep_t; ++ ++typedef struct cfi_dma_buff { ++#define CFI_IN_BUF_LEN 1024 ++#define CFI_OUT_BUF_LEN 1024 ++ dma_addr_t addr; ++ uint8_t *buf; ++} cfi_dma_buff_t; ++ ++struct cfiobject; ++ ++/** ++ * This is the interface for the CFI operations. ++ * ++ * @param ep_enable Called when any endpoint is enabled and activated. ++ * @param release Called when the CFI object is released and it needs to correctly ++ * deallocate the dynamic memory ++ * @param ctrl_write_complete Called when the data stage of the request is complete ++ */ ++typedef struct cfi_ops { ++ int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep); ++ void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep, dma_addr_t * dma, ++ unsigned size, gfp_t flags); ++ void (*release) (struct cfiobject * cfi); ++ int (*ctrl_write_complete) (struct cfiobject * cfi, ++ struct dwc_otg_pcd * pcd); ++ void (*build_descriptors) (struct cfiobject * cfi, ++ struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep, ++ dwc_otg_pcd_request_t * req); ++} cfi_ops_t; ++ ++struct cfiobject { ++ cfi_ops_t ops; ++ struct dwc_otg_pcd *pcd; ++ struct usb_gadget *gadget; ++ ++ /* Buffers used to send/receive CFI-related request data */ ++ cfi_dma_buff_t buf_in; ++ cfi_dma_buff_t buf_out; ++ ++ /* CFI specific Control request wrapper */ ++ struct cfi_usb_ctrlrequest ctrl_req; ++ ++ /* The list of active EP's in the PCD of type cfi_ep_t */ ++ dwc_list_link_t active_eps; ++ ++ /* This flag shall control the propagation of a specific request ++ * to the gadget's processing routines. ++ * 0 - no gadget handling ++ * 1 - the gadget needs to know about this request (w/o completing a status ++ * phase - just return a 0 to the _setup callback) ++ */ ++ uint8_t need_gadget_att; ++ ++ /* Flag indicating whether the status IN phase needs to be ++ * completed by the PCD ++ */ ++ uint8_t need_status_in_complete; ++}; ++typedef struct cfiobject cfiobject_t; ++ ++#define DUMP_MSG ++ ++#if defined(DUMP_MSG) ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++ unsigned int start, num, i; ++ char line[52], *p; ++ ++ if (length >= 512) ++ return; ++ ++ start = 0; ++ while (length > 0) { ++ num = min(length, 16u); ++ p = line; ++ for (i = 0; i < num; ++i) { ++ if (i == 8) ++ *p++ = ' '; ++ DWC_SPRINTF(p, " %02x", buf[i]); ++ p += 3; ++ } ++ *p = 0; ++ DWC_DEBUG("%6x: %s\n", start, line); ++ buf += num; ++ start += num; ++ length -= num; ++ } ++} ++#else ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++} ++#endif ++ ++/** ++ * This function returns a pointer to cfi_ep_t object with the addr address. ++ */ ++static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi, ++ uint8_t addr) ++{ ++ struct cfi_ep *pcfiep; ++ dwc_list_link_t *tmp; ++ ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ ++ if (pcfiep->ep->desc->bEndpointAddress == addr) { ++ return pcfiep; ++ } ++ } ++ ++ return NULL; ++} ++ ++/** ++ * This function returns a pointer to cfi_ep_t object that matches ++ * the dwc_otg_pcd_ep object. ++ */ ++static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi, ++ struct dwc_otg_pcd_ep *ep) ++{ ++ struct cfi_ep *pcfiep = NULL; ++ dwc_list_link_t *tmp; ++ ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ if (pcfiep->ep == ep) { ++ return pcfiep; ++ } ++ } ++ return NULL; ++} ++ ++int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl); ++ ++#endif /* (__DWC_OTG_CFI_H__) */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c +@@ -0,0 +1,7141 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $ ++ * $Revision: #191 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The Core Interface Layer provides basic services for accessing and ++ * managing the DWC_otg hardware. These services are used by both the ++ * Host Controller Driver and the Peripheral Controller Driver. ++ * ++ * The CIL manages the memory map for the core so that the HCD and PCD ++ * don't have to do this separately. It also handles basic tasks like ++ * reading/writing the registers and data FIFOs in the controller. ++ * Some of the data access functions provide encapsulation of several ++ * operations required to perform a task, such as writing multiple ++ * registers to start a transfer. Finally, the CIL performs basic ++ * services that are not specific to either the host or device modes ++ * of operation. These services include management of the OTG Host ++ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A ++ * Diagnostic API is also provided to allow testing of the controller ++ * hardware. ++ * ++ * The Core Interface Layer has the following requirements: ++ * - Provides basic controller operations. ++ * - Minimal use of OS services. ++ * - The OS services used will be abstracted by using inline functions ++ * or macros. ++ * ++ */ ++ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++ ++static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if); ++ ++/** ++ * This function is called to initialize the DWC_otg CSR data ++ * structures. The register addresses in the device and host ++ * structures are initialized from the base address supplied by the ++ * caller. The calling function must make the OS calls to get the ++ * base address of the DWC_otg controller registers. The core_params ++ * argument holds the parameters that specify how the core should be ++ * configured. ++ * ++ * @param reg_base_addr Base address of DWC_otg core registers ++ * ++ */ ++dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr) ++{ ++ dwc_otg_core_if_t *core_if = 0; ++ dwc_otg_dev_if_t *dev_if = 0; ++ dwc_otg_host_if_t *host_if = 0; ++ uint8_t *reg_base = (uint8_t *) reg_base_addr; ++ int i = 0; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr); ++ ++ core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t)); ++ ++ if (core_if == NULL) { ++ DWC_DEBUGPL(DBG_CIL, ++ "Allocation of dwc_otg_core_if_t failed\n"); ++ return 0; ++ } ++ core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base; ++ ++ /* ++ * Allocate the Device Mode structures. ++ */ ++ dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t)); ++ ++ if (dev_if == NULL) { ++ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); ++ DWC_FREE(core_if); ++ return 0; ++ } ++ ++ dev_if->dev_global_regs = ++ (dwc_otg_device_global_regs_t *) (reg_base + ++ DWC_DEV_GLOBAL_REG_OFFSET); ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) ++ (reg_base + DWC_DEV_IN_EP_REG_OFFSET + ++ (i * DWC_EP_REG_OFFSET)); ++ ++ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) ++ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + ++ (i * DWC_EP_REG_OFFSET)); ++ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", ++ i, &dev_if->in_ep_regs[i]->diepctl); ++ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", ++ i, &dev_if->out_ep_regs[i]->doepctl); ++ } ++ ++ dev_if->speed = 0; // unknown ++ ++ core_if->dev_if = dev_if; ++ ++ /* ++ * Allocate the Host Mode structures. ++ */ ++ host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t)); ++ ++ if (host_if == NULL) { ++ DWC_DEBUGPL(DBG_CIL, ++ "Allocation of dwc_otg_host_if_t failed\n"); ++ DWC_FREE(dev_if); ++ DWC_FREE(core_if); ++ return 0; ++ } ++ ++ host_if->host_global_regs = (dwc_otg_host_global_regs_t *) ++ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); ++ ++ host_if->hprt0 = ++ (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *) ++ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + ++ (i * DWC_OTG_CHAN_REGS_OFFSET)); ++ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", ++ i, &host_if->hc_regs[i]->hcchar); ++ } ++ ++ host_if->num_host_channels = MAX_EPS_CHANNELS; ++ core_if->host_if = host_if; ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ core_if->data_fifo[i] = ++ (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET + ++ (i * DWC_OTG_DATA_FIFO_SIZE)); ++ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n", ++ i, (unsigned long)core_if->data_fifo[i]); ++ } ++ ++ core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET); ++ ++ /* Initiate lx_state to L3 disconnected state */ ++ core_if->lx_state = DWC_OTG_L3; ++ /* ++ * Store the contents of the hardware configuration registers here for ++ * easy access later. ++ */ ++ core_if->hwcfg1.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1); ++ core_if->hwcfg2.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2); ++ core_if->hwcfg3.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3); ++ core_if->hwcfg4.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4); ++ ++ /* Force host mode to get HPTXFSIZ exact power on value */ ++ { ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gusbcfg.b.force_host_mode = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ dwc_mdelay(100); ++ core_if->hptxfsiz.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gusbcfg.b.force_host_mode = 0; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ dwc_mdelay(100); ++ } ++ ++ DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32); ++ ++ core_if->hcfg.d32 = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ core_if->dcfg.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ ++ DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32); ++ DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode); ++ DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture); ++ DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep); ++ DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n", ++ core_if->hwcfg2.b.num_host_chan); ++ DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.nonperio_tx_q_depth); ++ DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.host_perio_tx_q_depth); ++ DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.dev_token_q_depth); ++ ++ DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n", ++ core_if->hwcfg3.b.dfifo_depth); ++ DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n", ++ core_if->hwcfg3.b.xfer_size_cntr_width); ++ ++ /* ++ * Set the SRP sucess bit for FS-I2c ++ */ ++ core_if->srp_success = 0; ++ core_if->srp_timer_started = 0; ++ ++ /* ++ * Create new workqueue and init works ++ */ ++ core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg"); ++ if (core_if->wq_otg == 0) { ++ DWC_WARN("DWC_WORKQ_ALLOC failed\n"); ++ DWC_FREE(host_if); ++ DWC_FREE(dev_if); ++ DWC_FREE(core_if); ++ return 0; ++ } ++ ++ core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid); ++ ++ DWC_PRINTF("Core Release: %x.%x%x%x\n", ++ (core_if->snpsid >> 12 & 0xF), ++ (core_if->snpsid >> 8 & 0xF), ++ (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF)); ++ ++ core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer", ++ w_wakeup_detected, core_if); ++ if (core_if->wkp_timer == 0) { ++ DWC_WARN("DWC_TIMER_ALLOC failed\n"); ++ DWC_FREE(host_if); ++ DWC_FREE(dev_if); ++ DWC_WORKQ_FREE(core_if->wq_otg); ++ DWC_FREE(core_if); ++ return 0; ++ } ++ ++ if (dwc_otg_setup_params(core_if)) { ++ DWC_WARN("Error while setting core params\n"); ++ } ++ ++ core_if->hibernation_suspend = 0; ++ ++ /** ADP initialization */ ++ dwc_otg_adp_init(core_if); ++ ++ return core_if; ++} ++ ++/** ++ * This function frees the structures allocated by dwc_otg_cil_init(). ++ * ++ * @param core_if The core interface pointer returned from ++ * dwc_otg_cil_init(). ++ * ++ */ ++void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if) ++{ ++ dctl_data_t dctl = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); ++ ++ /* Disable all interrupts */ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); ++ ++ dctl.b.sftdiscon = 1; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, ++ dctl.d32); ++ } ++ ++ if (core_if->wq_otg) { ++ DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500); ++ DWC_WORKQ_FREE(core_if->wq_otg); ++ } ++ if (core_if->dev_if) { ++ DWC_FREE(core_if->dev_if); ++ } ++ if (core_if->host_if) { ++ DWC_FREE(core_if->host_if); ++ } ++ ++ /** Remove ADP Stuff */ ++ dwc_otg_adp_remove(core_if); ++ if (core_if->core_params) { ++ DWC_FREE(core_if->core_params); ++ } ++ if (core_if->wkp_timer) { ++ DWC_TIMER_FREE(core_if->wkp_timer); ++ } ++ if (core_if->srp_timer) { ++ DWC_TIMER_FREE(core_if->srp_timer); ++ } ++ DWC_FREE(core_if); ++} ++ ++/** ++ * This function enables the controller's Global Interrupt in the AHB Config ++ * register. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); ++} ++ ++/** ++ * This function disables the controller's Global Interrupt in the AHB Config ++ * register. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); ++} ++ ++/** ++ * This function initializes the commmon interrupts, used in both ++ * device and host modes. ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ * ++ */ ++static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ /* Clear any pending OTG Interrupts */ ++ DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF); ++ ++ /* Clear any pending interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* ++ * Enable the interrupts in the GINTMSK. ++ */ ++ intr_mask.b.modemismatch = 1; ++ intr_mask.b.otgintr = 1; ++ ++ if (!core_if->dma_enable) { ++ intr_mask.b.rxstsqlvl = 1; ++ } ++ ++ intr_mask.b.conidstschng = 1; ++ intr_mask.b.wkupintr = 1; ++ intr_mask.b.disconnect = 0; ++ intr_mask.b.usbsuspend = 1; ++ intr_mask.b.sessreqintr = 1; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->core_params->lpm_enable) { ++ intr_mask.b.lpmtranrcvd = 1; ++ } ++#endif ++ DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32); ++} ++ ++/* ++ * The restore operation is modified to support Synopsys Emulated Powerdown and ++ * Hibernation. This function is for exiting from Device mode hibernation by ++ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. ++ * @param core_if Programming view of DWC_otg controller. ++ * @param rem_wakeup - indicates whether resume is initiated by Device or Host. ++ * @param reset - indicates whether resume is initiated by Reset. ++ */ ++int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ int timeout = 2000; ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__); ++ /* Switch-on voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Assert Restore signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (rem_wakeup) { ++ dwc_udelay(70); ++ } ++ ++ /* Deassert Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Mask interrupts from gpwrdn */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.connect_det_msk = 1; ++ gpwrdn.b.srp_det_msk = 1; ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are going out from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* ++ * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1 ++ * indicates restore from remote_wakeup ++ */ ++ restore_essential_regs(core_if, rem_wakeup, 0); ++ ++ /* ++ * Wait a little for seeing new value of variable hibernation_suspend if ++ * Restore done interrupt received before polling ++ */ ++ dwc_udelay(10); ++ ++ if (core_if->hibernation_suspend == 0) { ++ /* ++ * Wait For Restore_done Interrupt. This mechanism of polling the ++ * interrupt is introduced to avoid any possible race conditions ++ */ ++ do { ++ gintsts_data_t gintsts; ++ gintsts.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ DWC_PRINTF("Restore Done Interrupt seen\n"); ++ break; ++ } ++ dwc_udelay(10); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_PRINTF("Restore Done interrupt wasn't generated here\n"); ++ } ++ } ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* De-assert Restore */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (!rem_wakeup) { ++ pcgcctl.d32 = 0; ++ pcgcctl.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ } ++ ++ /* Restore GUSBCFG and DCFG */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ core_if->dr_backup->dcfg); ++ ++ /* De-assert Wakeup Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (!rem_wakeup) { ++ /* Set Device programming done bit */ ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } else { ++ /* Start Remote Wakeup Signaling */ ++ dctl.d32 = core_if->dr_backup->dctl; ++ dctl.b.rmtwkupsig = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ } ++ ++ dwc_mdelay(2); ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Restore global registers */ ++ dwc_otg_restore_global_regs(core_if); ++ /* Restore device global registers */ ++ dwc_otg_restore_dev_regs(core_if, rem_wakeup); ++ ++ if (rem_wakeup) { ++ dwc_mdelay(7); ++ dctl.d32 = 0; ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ } ++ ++ core_if->hibernation_suspend = 0; ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ DWC_PRINTF("Hibernation recovery completes here\n"); ++ ++ return 1; ++} ++ ++/* ++ * The restore operation is modified to support Synopsys Emulated Powerdown and ++ * Hibernation. This function is for exiting from Host mode hibernation by ++ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. ++ * @param core_if Programming view of DWC_otg controller. ++ * @param rem_wakeup - indicates whether resume is initiated by Device or Host. ++ * @param reset - indicates whether resume is initiated by Reset. ++ */ ++int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ int timeout = 2000; ++ ++ DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__); ++ /* Switch-on voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Assert Restore signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (!rem_wakeup) { ++ dwc_udelay(50); ++ } ++ ++ /* Deassert Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.connect_det_msk = 1; ++ gpwrdn.b.srp_det_msk = 1; ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are going out from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Set Restore Essential Regs bit in PCGCCTL register */ ++ restore_essential_regs(core_if, rem_wakeup, 1); ++ ++ /* Wait a little for seeing new value of variable hibernation_suspend if ++ * Restore done interrupt received before polling */ ++ dwc_udelay(10); ++ ++ if (core_if->hibernation_suspend == 0) { ++ /* Wait For Restore_done Interrupt. This mechanism of polling the ++ * interrupt is introduced to avoid any possible race conditions ++ */ ++ do { ++ gintsts_data_t gintsts; ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n"); ++ break; ++ } ++ dwc_udelay(10); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_WARN("Restore Done interrupt wasn't generated\n"); ++ } ++ } ++ ++ /* Set the flag's value to 0 again after receiving restore done interrupt */ ++ core_if->hibernation_suspend = 0; ++ ++ /* This step is not described in functional spec but if not wait for this ++ * delay, mismatch interrupts occurred because just after restore core is ++ * in Device mode(gintsts.curmode == 0) */ ++ dwc_mdelay(100); ++ ++ /* Clear all pending interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* De-assert Restore */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Restore GUSBCFG and HCFG */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, ++ core_if->hr_backup->hcfg_local); ++ ++ /* De-assert Wakeup Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Start the Resume operation by programming HPRT0 */ ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ DWC_PRINTF("Resume Starts Now\n"); ++ if (!reset) { // Indicates it is Resume Operation ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtres = 1; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ if (!rem_wakeup) ++ hprt0.b.prtres = 0; ++ /* Wait for Resume time and then program HPRT again */ ++ dwc_mdelay(100); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ } else { // Indicates it is Reset Operation ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtrst = 1; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ /* Wait for Reset time and then program HPRT again */ ++ dwc_mdelay(60); ++ hprt0.b.prtrst = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ /* Clear all interrupt status */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtconndet = 1; ++ hprt0.b.prtenchng = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Restore global registers */ ++ dwc_otg_restore_global_regs(core_if); ++ /* Restore host global registers */ ++ dwc_otg_restore_host_regs(core_if, reset); ++ ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ DWC_PRINTF("Hibernation recovery is complete here\n"); ++ return 0; ++} ++ ++/** Saves some register values into system memory. */ ++int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ int i; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ gr = DWC_ALLOC(sizeof(*gr)); ++ if (!gr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->gr_backup = gr; ++ } ++ ++ gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); ++ gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz); ++ gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++#endif ++ gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl); ++ gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl); ++ gr->gdfifocfg_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg); ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ gr->dtxfsiz_local[i] = ++ DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i])); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n", ++ gr->gnptxfsiz_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n", ++ gr->hptxfsiz_local); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local); ++#endif ++ DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local); ++ DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local); ++ ++ return 0; ++} ++ ++/** Saves GINTMSK register before setting the msk bits. */ ++int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ gr = DWC_ALLOC(sizeof(*gr)); ++ if (!gr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->gr_backup = gr; ++ } ++ ++ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ ++ DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local); ++ ++ return 0; ++} ++ ++int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_dev_regs_backup *dr; ++ int i; ++ ++ dr = core_if->dr_backup; ++ if (!dr) { ++ dr = DWC_ALLOC(sizeof(*dr)); ++ if (!dr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->dr_backup = dr; ++ } ++ ++ dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ dr->daintmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); ++ dr->diepmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk); ++ dr->doepmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk); ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ dr->diepctl[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl); ++ dr->dieptsiz[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz); ++ dr->diepdma[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "=============Backing Host registers==============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl); ++ DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n", ++ dr->daintmsk); ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk); ++ DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk); ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i, ++ dr->diepctl[i]); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n", ++ i, dr->dieptsiz[i]); ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i, ++ dr->diepdma[i]); ++ } ++ ++ return 0; ++} ++ ++int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_host_regs_backup *hr; ++ int i; ++ ++ hr = core_if->hr_backup; ++ if (!hr) { ++ hr = DWC_ALLOC(sizeof(*hr)); ++ if (!hr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->hr_backup = hr; ++ } ++ ++ hr->hcfg_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ hr->haintmsk_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ hr->hcintmsk_local[i] = ++ DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk); ++ } ++ hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0); ++ hr->hfir_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "=============Backing Host registers===============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n", ++ hr->hcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i, ++ hr->hcintmsk_local[i]); ++ } ++ DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n", ++ hr->hprt0_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n", ++ hr->hfir_local); ++ ++ return 0; ++} ++ ++int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ int i; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, ++ gr->gnptxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz, ++ gr->hptxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg, ++ gr->gdfifocfg_local); ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i], ++ gr->dtxfsiz_local[i]); ++ } ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, ++ (gr->gahbcfg_local)); ++ return 0; ++} ++ ++int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup) ++{ ++ struct dwc_otg_dev_regs_backup *dr; ++ int i; ++ ++ dr = core_if->dr_backup; ++ ++ if (!dr) { ++ return -DWC_E_INVALID; ++ } ++ ++ if (!rem_wakeup) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dr->dctl); ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk); ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]); ++ } ++ ++ return 0; ++} ++ ++int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset) ++{ ++ struct dwc_otg_host_regs_backup *hr; ++ int i; ++ hr = core_if->hr_backup; ++ ++ if (!hr) { ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local); ++ //if (!reset) ++ //{ ++ // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local); ++ //} ++ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, ++ hr->haintmsk_local); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, ++ hr->hcintmsk_local[i]); ++ } ++ ++ return 0; ++} ++ ++int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ ++ gr = core_if->gr_backup; ++ ++ /* Restore values for LPM and I2C */ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local); ++#endif ++ DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local); ++ ++ return 0; ++} ++ ++int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ /* Restore LPM and I2C registers */ ++ restore_lpm_i2c_regs(core_if); ++ ++ /* Set PCGCCTL to 0 */ ++ DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000); ++ ++ gr = core_if->gr_backup; ++ /* Load restore values for [31:14] bits */ ++ DWC_WRITE_REG32(core_if->pcgcctl, ++ ((gr->pcgcctl_local & 0xffffc000) | 0x00020000)); ++ ++ /* Umnask global Interrupt in GAHBCFG and restore it */ ++ gahbcfg.d32 = gr->gahbcfg_local; ++ gahbcfg.b.glblintrmsk = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32); ++ ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Unmask restore done interrupt */ ++ gintmsk.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); ++ ++ /* Restore GUSBCFG and HCFG/DCFG */ ++ gusbcfg.d32 = core_if->gr_backup->gusbcfg_local; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ ++ if (is_host) { ++ hcfg_data_t hcfg = {.d32 = 0 }; ++ hcfg.d32 = core_if->hr_backup->hcfg_local; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ ++ if (rmode) ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ /* Load restore values for [31:14] bits and set EssRegRestored bit */ ++ pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.b.ess_reg_restored = 1; ++ if (rmode) ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ } else { ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ dcfg.d32 = core_if->dr_backup->dcfg; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ if (!rmode) { ++ pcgcctl.d32 |= 0x208; ++ } ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ pcgcctl.b.ess_reg_restored = 1; ++ if (!rmode) ++ pcgcctl.d32 |= 0x208; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ } ++ ++ return 0; ++} ++ ++/** ++ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY ++ * type. ++ */ ++static void init_fslspclksel(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t val; ++ hcfg_data_t hcfg; ++ ++ if (((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) || ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* Full speed PHY */ ++ val = DWC_HCFG_48_MHZ; ++ } else { ++ /* High speed PHY running at full speed or high speed */ ++ val = DWC_HCFG_30_60_MHZ; ++ } ++ ++ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ hcfg.b.fslspclksel = val; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++/** ++ * Initializes the DevSpd field of the DCFG register depending on the PHY type ++ * and the enumeration speed of the device. ++ */ ++static void init_devspd(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t val; ++ dcfg_data_t dcfg; ++ ++ if (((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) || ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* Full speed PHY */ ++ val = 0x3; ++ } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { ++ /* High speed PHY running at full speed */ ++ val = 0x1; ++ } else { ++ /* High speed PHY running at high speed */ ++ val = 0x0; ++ } ++ ++ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); ++ ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.devspd = val; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++} ++ ++/** ++ * This function calculates the number of IN EPS ++ * using GHWCFG1 and GHWCFG2 registers values ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ */ ++static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t num_in_eps = 0; ++ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; ++ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3; ++ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps; ++ int i; ++ ++ for (i = 0; i < num_eps; ++i) { ++ if (!(hwcfg1 & 0x1)) ++ num_in_eps++; ++ ++ hwcfg1 >>= 2; ++ } ++ ++ if (core_if->hwcfg4.b.ded_fifo_en) { ++ num_in_eps = ++ (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; ++ } ++ ++ return num_in_eps; ++} ++ ++/** ++ * This function calculates the number of OUT EPS ++ * using GHWCFG1 and GHWCFG2 registers values ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ */ ++static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t num_out_eps = 0; ++ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; ++ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2; ++ int i; ++ ++ for (i = 0; i < num_eps; ++i) { ++ if (!(hwcfg1 & 0x1)) ++ num_out_eps++; ++ ++ hwcfg1 >>= 2; ++ } ++ return num_out_eps; ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers and ++ * prepares the core for device mode or host mode operation. ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ * ++ */ ++void dwc_otg_core_init(dwc_otg_core_if_t * core_if) ++{ ++ int i = 0; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ gusbcfg_data_t usbcfg = {.d32 = 0 }; ++ gi2cctl_data_t i2cctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n", ++ core_if, global_regs); ++ ++ /* Common Initialization */ ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ ++ /* Program the ULPI External VBUS bit if needed */ ++ usbcfg.b.ulpi_ext_vbus_drv = ++ (core_if->core_params->phy_ulpi_ext_vbus == ++ DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; ++ ++ /* Set external TS Dline pulsing */ ++ usbcfg.b.term_sel_dl_pulse = ++ (core_if->core_params->ts_dline == 1) ? 1 : 0; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset the Controller */ ++ dwc_otg_core_reset(core_if); ++ ++ core_if->adp_enable = core_if->core_params->adp_supp_enable; ++ core_if->power_down = core_if->core_params->power_down; ++ core_if->otg_sts = 0; ++ ++ /* Initialize parameters from Hardware configuration registers. */ ++ dev_if->num_in_eps = calc_num_in_eps(core_if); ++ dev_if->num_out_eps = calc_num_out_eps(core_if); ++ ++ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", ++ core_if->hwcfg4.b.num_dev_perio_in_ep); ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { ++ dev_if->perio_tx_fifo_size[i] = ++ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16; ++ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", ++ i, dev_if->perio_tx_fifo_size[i]); ++ } ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dev_if->tx_fifo_size[i] = ++ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16; ++ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", ++ i, dev_if->tx_fifo_size[i]); ++ } ++ ++ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth; ++ core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz); ++ core_if->nperio_tx_fifo_size = ++ DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16; ++ ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", ++ core_if->nperio_tx_fifo_size); ++ ++ /* This programming sequence needs to happen in FS mode before any other ++ * programming occurs */ ++ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* If FS mode with FS PHY */ ++ ++ /* core_init() is now called on every switch so only call the ++ * following for the first time through. */ ++ if (!core_if->phy_init_done) { ++ core_if->phy_init_done = 1; ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ usbcfg.b.physel = 1; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset after a PHY select */ ++ dwc_otg_core_reset(core_if); ++ } ++ ++ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also ++ * do this on HNP Dev/Host mode switches (done in dev_init and ++ * host_init). */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ init_fslspclksel(core_if); ++ } else { ++ init_devspd(core_if); ++ } ++ ++ if (core_if->core_params->i2c_enable) { ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); ++ /* Program GUSBCFG.OtgUtmifsSel to I2C */ ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ usbcfg.b.otgutmifssel = 1; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Program GI2CCTL.I2CEn */ ++ i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl); ++ i2cctl.b.i2cdevaddr = 1; ++ i2cctl.b.i2cen = 0; ++ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32); ++ i2cctl.b.i2cen = 1; ++ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32); ++ } ++ ++ } /* endif speed == DWC_SPEED_PARAM_FULL */ ++ else { ++ /* High speed PHY. */ ++ if (!core_if->phy_init_done) { ++ core_if->phy_init_done = 1; ++ /* HS PHY parameters. These parameters are preserved ++ * during soft reset so only program the first time. Do ++ * a soft reset immediately after setting phyif. */ ++ ++ if (core_if->core_params->phy_type == 2) { ++ /* ULPI interface */ ++ usbcfg.b.ulpi_utmi_sel = 1; ++ usbcfg.b.phyif = 0; ++ usbcfg.b.ddrsel = ++ core_if->core_params->phy_ulpi_ddr; ++ } else if (core_if->core_params->phy_type == 1) { ++ /* UTMI+ interface */ ++ usbcfg.b.ulpi_utmi_sel = 0; ++ if (core_if->core_params->phy_utmi_width == 16) { ++ usbcfg.b.phyif = 1; ++ ++ } else { ++ usbcfg.b.phyif = 0; ++ } ++ } else { ++ DWC_ERROR("FS PHY TYPE\n"); ++ } ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ /* Reset after setting the PHY parameters */ ++ dwc_otg_core_reset(core_if); ++ } ++ } ++ ++ if ((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) { ++ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ usbcfg.b.ulpi_fsls = 1; ++ usbcfg.b.ulpi_clk_sus_m = 1; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ } else { ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ usbcfg.b.ulpi_fsls = 0; ++ usbcfg.b.ulpi_clk_sus_m = 0; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ } ++ ++ /* Program the GAHBCFG Register. */ ++ switch (core_if->hwcfg2.b.architecture) { ++ ++ case DWC_SLAVE_ONLY_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); ++ ahbcfg.b.nptxfemplvl_txfemplvl = ++ DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; ++ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; ++ core_if->dma_enable = 0; ++ core_if->dma_desc_enable = 0; ++ break; ++ ++ case DWC_EXT_DMA_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); ++ { ++ uint8_t brst_sz = core_if->core_params->dma_burst_size; ++ ahbcfg.b.hburstlen = 0; ++ while (brst_sz > 1) { ++ ahbcfg.b.hburstlen++; ++ brst_sz >>= 1; ++ } ++ } ++ core_if->dma_enable = (core_if->core_params->dma_enable != 0); ++ core_if->dma_desc_enable = ++ (core_if->core_params->dma_desc_enable != 0); ++ break; ++ ++ case DWC_INT_DMA_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); ++ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for ++ Host mode ISOC in issue fix - vahrama */ ++ /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */ ++ ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4; ++ core_if->dma_enable = (core_if->core_params->dma_enable != 0); ++ core_if->dma_desc_enable = ++ (core_if->core_params->dma_desc_enable != 0); ++ break; ++ ++ } ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ DWC_PRINTF("Using Descriptor DMA mode\n"); ++ } else { ++ DWC_PRINTF("Using Buffer DMA mode\n"); ++ ++ } ++ } else { ++ DWC_PRINTF("Using Slave mode\n"); ++ core_if->dma_desc_enable = 0; ++ } ++ ++ if (core_if->core_params->ahb_single) { ++ ahbcfg.b.ahbsingle = 1; ++ } ++ ++ ahbcfg.b.dmaenable = core_if->dma_enable; ++ DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32); ++ ++ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en; ++ ++ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0; ++ core_if->multiproc_int_enable = core_if->core_params->mpi_enable; ++ DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n", ++ ((core_if->pti_enh_enable) ? "enabled" : "disabled")); ++ DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n", ++ ((core_if->multiproc_int_enable) ? "enabled" : "disabled")); ++ ++ /* ++ * Program the GUSBCFG register. ++ */ ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ ++ switch (core_if->hwcfg2.b.op_mode) { ++ case DWC_MODE_HNP_SRP_CAPABLE: ++ usbcfg.b.hnpcap = (core_if->core_params->otg_cap == ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_SRP_ONLY_CAPABLE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_HNP_SRP_CAPABLE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case DWC_MODE_SRP_CAPABLE_DEVICE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_SRP_CAPABLE_DEVICE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case DWC_MODE_SRP_CAPABLE_HOST: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_SRP_CAPABLE_HOST: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ } ++ ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->core_params->lpm_enable) { ++ glpmcfg_data_t lpmcfg = {.d32 = 0 }; ++ ++ /* To enable LPM support set lpm_cap_en bit */ ++ lpmcfg.b.lpm_cap_en = 1; ++ ++ /* Make AppL1Res ACK */ ++ lpmcfg.b.appl_resp = 1; ++ ++ /* Retry 3 times */ ++ lpmcfg.b.retry_count = 3; ++ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg, ++ 0, lpmcfg.d32); ++ ++ } ++#endif ++ if (core_if->core_params->ic_usb_cap) { ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gusbcfg.b.ic_usb_cap = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg, ++ 0, gusbcfg.d32); ++ } ++ { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.b.otgver = core_if->core_params->otg_ver; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0, ++ gotgctl.d32); ++ /* Set OTG version supported */ ++ core_if->otg_ver = core_if->core_params->otg_ver; ++ DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n", ++ core_if->core_params->otg_ver, core_if->otg_ver); ++ } ++ ++ ++ /* Enable common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* Do device or host intialization based on mode during PCD ++ * and HCD initialization */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ DWC_DEBUGPL(DBG_ANY, "Host Mode\n"); ++ core_if->op_state = A_HOST; ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "Device Mode\n"); ++ core_if->op_state = B_PERIPHERAL; ++#ifdef DWC_DEVICE_ONLY ++ dwc_otg_core_dev_init(core_if); ++#endif ++ } ++} ++ ++/** ++ * This function enables the Device mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ ++ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); ++ ++ /* Disable all interrupts. */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Enable the common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* Enable interrupts */ ++ intr_mask.b.usbreset = 1; ++ intr_mask.b.enumdone = 1; ++ /* Disable Disconnect interrupt in Device mode */ ++ intr_mask.b.disconnect = 0; ++ ++ if (!core_if->multiproc_int_enable) { ++ intr_mask.b.inepintr = 1; ++ intr_mask.b.outepintr = 1; ++ } ++ ++ intr_mask.b.erlysuspend = 1; ++ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.epmismatch = 1; ++ } ++ ++ //intr_mask.b.incomplisoout = 1; ++ intr_mask.b.incomplisoin = 1; ++ ++/* Enable the ignore frame number for ISOC xfers - MAS */ ++/* Disable to support high bandwith ISOC transfers - manukz */ ++#if 0 ++#ifdef DWC_UTE_PER_IO ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ dctl_data_t dctl1 = {.d32 = 0 }; ++ dctl1.b.ifrmnum = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl1.d32); ++ DWC_DEBUG("----Enabled Ignore frame number (0x%08x)", ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl)); ++ } ++ } ++#endif ++#endif ++#ifdef DWC_EN_ISOC ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ if (core_if->pti_enh_enable) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.ifrmnum = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dctl, ++ 0, dctl.d32); ++ } else { ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++ } ++ } ++ } else { ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ /** @todo NGS: Should this be a module parameter? */ ++#ifdef USE_PERIODIC_EP ++ intr_mask.b.isooutdrop = 1; ++ intr_mask.b.eopframe = 1; ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++#endif ++ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ++ DWC_READ_REG32(&global_regs->gintmsk)); ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers for ++ * device mode. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ */ ++void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ depctl_data_t diepctl = {.d32 = 0 }; ++ grstctl_t resetctl = {.d32 = 0 }; ++ uint32_t rx_fifo_size; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t txfifosize; ++ dthrctl_data_t dthrctl; ++ fifosize_data_t ptxfifosize; ++ uint16_t rxfsiz, nptxfsiz; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ hwcfg3_data_t hwcfg3 = {.d32 = 0 }; ++ ++ /* Restart the Phy Clock */ ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ ++ /* Device configuration register */ ++ init_devspd(core_if); ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0; ++ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; ++ /* Enable Device OUT NAK in case of DDMA mode*/ ++ if (core_if->core_params->dev_out_nak) { ++ dcfg.b.endevoutnak = 1; ++ } ++ ++ if (core_if->core_params->cont_on_bna) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.encontonbna = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ ++ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", ++ core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", ++ params->dev_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", ++ params->dev_nperio_tx_fifo_size); ++ ++ /* Rx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz); ++ core_if->init_rxfsiz = params->dev_rx_fifo_size; ++#endif ++ rx_fifo_size = params->dev_rx_fifo_size; ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size); ++ ++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ ++ /** Set Periodic Tx FIFO Mask all bits 0 */ ++ core_if->p_tx_msk = 0; ++ ++ /** Set Tx FIFO Mask all bits 0 */ ++ core_if->tx_msk = 0; ++ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; ++ ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, ++ nptxfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++ /**@todo NGS: Fix Periodic FIFO Sizing! */ ++ /* ++ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_perio_tx_fifo_size array and the FIFO size registers in ++ * the dptxfsiz array run from 0 to 14. ++ */ ++ /** @todo Finish debug of this */ ++ ptxfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { ++ ptxfifosize.b.depth = ++ params->dev_perio_tx_fifo_size[i]; ++ DWC_DEBUGPL(DBG_CIL, ++ "initial dtxfsiz[%d]=%08x\n", i, ++ DWC_READ_REG32(&global_regs->dtxfsiz ++ [i])); ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], ++ ptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n", ++ i, ++ DWC_READ_REG32(&global_regs->dtxfsiz ++ [i])); ++ ptxfifosize.b.startaddr += ptxfifosize.b.depth; ++ } ++ } else { ++ /* ++ * Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_tx_fifo_size array and the FIFO size registers in ++ * the dtxfsiz array run from 0 to 14. ++ */ ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_gnptxfsiz = ++ (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ core_if->init_gnptxfsiz = ++ params->dev_nperio_tx_fifo_size; ++#endif ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; ++ ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, ++ nptxfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++ txfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ txfifosize.b.depth = ++ params->dev_tx_fifo_size[i]; ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "initial dtxfsiz[%d]=%08x\n", ++ i, ++ DWC_READ_REG32(&global_regs->dtxfsiz ++ [i])); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_txfsiz[i] = ++ (DWC_READ_REG32 ++ (&global_regs->dtxfsiz[i]) >> 16); ++ core_if->init_txfsiz[i] = ++ params->dev_tx_fifo_size[i]; ++#endif ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], ++ txfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "new dtxfsiz[%d]=%08x\n", ++ i, ++ DWC_READ_REG32(&global_regs->dtxfsiz ++ [i])); ++ ++ txfifosize.b.startaddr += txfifosize.b.depth; ++ } ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */ ++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); ++ hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3); ++ gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16); ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); ++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz; ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ } ++ } ++ ++ /* Flush the FIFOs */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ /* Flush the Learning Queue. */ ++ resetctl.b.intknqflsh = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 0; ++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { ++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active ++ } ++ core_if->nextep_seq[0] = 0; ++ core_if->first_in_nextep_seq = 0; ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ diepctl.b.nextep = 0; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt = 2; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]); ++ } ++ DWC_DEBUGPL(DBG_CILV,"\n"); ++ } ++ ++ /* Clear all pending Device Interrupts */ ++ /** @todo - if the condition needed to be checked ++ * or in any case all pending interrutps should be cleared? ++ */ ++ if (core_if->multiproc_int_enable) { ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&dev_if-> ++ dev_global_regs->diepeachintmsk[i], 0); ++ } ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ DWC_WRITE_REG32(&dev_if-> ++ dev_global_regs->doepeachintmsk[i], 0); ++ } ++ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0); ++ } else { ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0); ++ } ++ ++ for (i = 0; i <= dev_if->num_in_eps; i++) { ++ depctl_data_t depctl; ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (depctl.b.epena) { ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } else { ++ depctl.d32 = 0; ++ } ++ ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF); ++ } ++ ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ depctl_data_t depctl; ++ depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); ++ if (depctl.b.epena) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintmsk_data_t gintsts = {.d32 = 0 }; ++ doepint_data_t doepint = {.d32 = 0 }; ++ dctl.b.sgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ do { ++ dwc_udelay(10); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ } while (!gintsts.b.goutnakeff); ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32); ++ do { ++ dwc_udelay(10); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[i]->doepint); ++ } while (!doepint.b.epdisabled); ++ ++ doepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32); ++ ++ dctl.d32 = 0; ++ dctl.b.cgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } else { ++ depctl.d32 = 0; ++ } ++ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32); ++ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF); ++ } ++ ++ if (core_if->en_multiple_tx_fifo && core_if->dma_enable) { ++ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1; ++ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1; ++ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1; ++ ++ dev_if->rx_thr_length = params->rx_thr_length; ++ dev_if->tx_thr_length = params->tx_thr_length; ++ ++ dev_if->setup_desc_index = 0; ++ ++ dthrctl.d32 = 0; ++ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; ++ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; ++ dthrctl.b.tx_thr_len = dev_if->tx_thr_length; ++ dthrctl.b.rx_thr_en = dev_if->rx_thr_en; ++ dthrctl.b.rx_thr_len = dev_if->rx_thr_length; ++ dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio; ++ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl, ++ dthrctl.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", ++ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, ++ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, ++ dthrctl.b.rx_thr_len); ++ ++ } ++ ++ dwc_otg_enable_device_interrupts(core_if); ++ ++ { ++ diepmsk_data_t msk = {.d32 = 0 }; ++ msk.b.txfifoundrn = 1; ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs-> ++ diepeachintmsk[0], msk.d32, msk.d32); ++ } else { ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, ++ msk.d32, msk.d32); ++ } ++ } ++ ++ if (core_if->multiproc_int_enable) { ++ /* Set NAK on Babble */ ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.nakonbble = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ ++ if (core_if->snpsid >= OTG_CORE_REV_2_94a) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl); ++ dctl.b.sftdiscon = 0; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32); ++ } ++} ++ ++/** ++ * This function enables the Host mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if); ++ ++ /* Disable all interrupts. */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts. */ ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Enable the common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* ++ * Enable host mode interrupts without disturbing common ++ * interrupts. ++ */ ++ ++ intr_mask.b.disconnect = 1; ++ intr_mask.b.portintr = 1; ++ intr_mask.b.hcintr = 1; ++ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++} ++ ++/** ++ * This function disables the Host Mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); ++ ++ /* ++ * Disable host mode interrupts without disturbing common ++ * interrupts. ++ */ ++ intr_mask.b.sofintr = 1; ++ intr_mask.b.portintr = 1; ++ intr_mask.b.hcintr = 1; ++ intr_mask.b.ptxfempty = 1; ++ intr_mask.b.nptxfempty = 1; ++ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0); ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers for ++ * host mode. ++ * ++ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the ++ * request queues. Host channels are reset to ensure that they are ready for ++ * performing transfers. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ */ ++void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_host_if_t *host_if = core_if->host_if; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t ptxfifosize; ++ uint16_t rxfsiz, nptxfsiz, hptxfsiz; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ int i; ++ hcchar_data_t hcchar; ++ hcfg_data_t hcfg; ++ hfir_data_t hfir; ++ dwc_otg_hc_regs_t *hc_regs; ++ int num_channels; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); ++ ++ /* Restart the Phy Clock */ ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ ++ /* Initialize Host Configuration Register */ ++ init_fslspclksel(core_if); ++ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { ++ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg); ++ hcfg.b.fslssupp = 1; ++ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ ++ } ++ ++ /* This bit allows dynamic reloading of the HFIR register ++ * during runtime. This bit needs to be programmed during ++ * initial configuration and its value must not be changed ++ * during runtime.*/ ++ if (core_if->core_params->reload_ctl == 1) { ++ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir); ++ hfir.b.hfirrldctrl = 1; ++ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32); ++ } ++ ++ if (core_if->core_params->dma_desc_enable) { ++ uint8_t op_mode = core_if->hwcfg2.b.op_mode; ++ if (! ++ (core_if->hwcfg4.b.desc_dma ++ && (core_if->snpsid >= OTG_CORE_REV_2_90a) ++ && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ || (op_mode == ++ DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) ++ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) ++ || (op_mode == ++ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) { ++ ++ DWC_ERROR("Host can't operate in Descriptor DMA mode.\n" ++ "Either core version is below 2.90a or " ++ "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n" ++ "To run the driver in Buffer DMA host mode set dma_desc_enable " ++ "module parameter to 0.\n"); ++ return; ++ } ++ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg); ++ hcfg.b.descdma = 1; ++ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ } ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", ++ core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", ++ params->host_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", ++ params->host_nperio_tx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n", ++ params->host_perio_tx_fifo_size); ++ ++ /* Rx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ DWC_WRITE_REG32(&global_regs->grxfsiz, ++ params->host_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->host_rx_fifo_size; ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++ /* Periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->hptxfsiz)); ++ ptxfifosize.b.depth = params->host_perio_tx_fifo_size; ++ ptxfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->hptxfsiz)); ++ ++ if (core_if->en_multiple_tx_fifo ++ && core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */ ++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); ++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); ++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16); ++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz; ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ } ++ } ++ ++ /* TODO - check this */ ++ /* Clear Host Set HNP Enable in the OTG Control Register */ ++ gotgctl.b.hstsethnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ /* Make sure the FIFOs are flushed. */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ ); ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ /* Clear Host Set HNP Enable in the OTG Control Register */ ++ gotgctl.b.hstsethnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ ++ if (!core_if->core_params->dma_desc_enable) { ++ /* Flush out any leftover queued requests. */ ++ num_channels = core_if->core_params->host_channels; ++ ++ for (i = 0; i < num_channels; i++) { ++ hc_regs = core_if->host_if->hc_regs[i]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.chen = 0; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ } ++ ++ /* Halt all channels to put them into a known state. */ ++ for (i = 0; i < num_channels; i++) { ++ int count = 0; ++ hc_regs = core_if->host_if->hc_regs[i]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs); ++ do { ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (++count > 1000) { ++ DWC_ERROR ++ ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n", ++ __func__, i, hcchar.d32, &hc_regs->hcchar); ++ break; ++ } ++ dwc_udelay(1); ++ } while (hcchar.b.chen); ++ } ++ } ++ ++ /* Turn on the vbus power. */ ++ DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state); ++ if (core_if->op_state == A_HOST) { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr); ++ if (hprt0.b.prtpwr == 0) { ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(host_if->hprt0, hprt0.d32); ++ } ++ } ++ ++ dwc_otg_enable_host_interrupts(core_if); ++} ++ ++/** ++ * Prepares a host channel for transferring packets to/from a specific ++ * endpoint. The HCCHARn register is set up with the characteristics specified ++ * in _hc. Host channel interrupts that may need to be serviced while this ++ * transfer is in progress are enabled. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * @param hc Information needed to initialize the host channel ++ */ ++void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ hcintmsk_data_t hc_intr_mask; ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ ++ uint8_t hc_num = hc->hc_num; ++ dwc_otg_host_if_t *host_if = core_if->host_if; ++ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; ++ ++ /* Clear old interrupt conditions for this host channel. */ ++ hc_intr_mask.d32 = 0xFFFFFFFF; ++ hc_intr_mask.b.reserved14_31 = 0; ++ DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32); ++ ++ /* Enable channel interrupts required for this transfer. */ ++ hc_intr_mask.d32 = 0; ++ hc_intr_mask.b.chhltd = 1; ++ if (core_if->dma_enable) { ++ /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */ ++ if (!core_if->dma_desc_enable) ++ hc_intr_mask.b.ahberr = 1; ++ else { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ hc_intr_mask.b.xfercompl = 1; ++ } ++ ++ if (hc->error_state && !hc->do_split && ++ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ hc_intr_mask.b.ack = 1; ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.datatglerr = 1; ++ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { ++ hc_intr_mask.b.nak = 1; ++ } ++ } ++ } ++ } else { ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.stall = 1; ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.datatglerr = 1; ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.bblerr = 1; ++ } else { ++ hc_intr_mask.b.nak = 1; ++ hc_intr_mask.b.nyet = 1; ++ if (hc->do_ping) { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ ++ if (hc->do_split) { ++ hc_intr_mask.b.nak = 1; ++ if (hc->complete_split) { ++ hc_intr_mask.b.nyet = 1; ++ } else { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ ++ if (hc->error_state) { ++ hc_intr_mask.b.ack = 1; ++ } ++ break; ++ case DWC_OTG_EP_TYPE_INTR: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.nak = 1; ++ hc_intr_mask.b.stall = 1; ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.datatglerr = 1; ++ hc_intr_mask.b.frmovrun = 1; ++ ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.bblerr = 1; ++ } ++ if (hc->error_state) { ++ hc_intr_mask.b.ack = 1; ++ } ++ if (hc->do_split) { ++ if (hc->complete_split) { ++ hc_intr_mask.b.nyet = 1; ++ } else { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ break; ++ case DWC_OTG_EP_TYPE_ISOC: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.frmovrun = 1; ++ hc_intr_mask.b.ack = 1; ++ ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.bblerr = 1; ++ } ++ break; ++ } ++ } ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32); ++ ++ /* ++ * Program the HCCHARn register with the endpoint characteristics for ++ * the current transfer. ++ */ ++ hcchar.d32 = 0; ++ hcchar.b.devaddr = hc->dev_addr; ++ hcchar.b.epnum = hc->ep_num; ++ hcchar.b.epdir = hc->ep_is_in; ++ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); ++ hcchar.b.eptype = hc->ep_type; ++ hcchar.b.mps = hc->max_packet; ++ ++ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n", ++ __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum); ++ DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, " ++ "Max Pkt %d, Multi Cnt %d\n", ++ hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype, ++ hcchar.b.mps, hcchar.b.multicnt); ++ ++ /* ++ * Program the HCSPLIT register for SPLITs ++ */ ++ hcsplt.d32 = 0; ++ if (hc->do_split) { ++ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", ++ hc->hc_num, ++ hc->complete_split ? "CSPLIT" : "SSPLIT"); ++ hcsplt.b.compsplt = hc->complete_split; ++ hcsplt.b.xactpos = hc->xact_pos; ++ hcsplt.b.hubaddr = hc->hub_addr; ++ hcsplt.b.prtaddr = hc->port_addr; ++ DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split); ++ DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos); ++ DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr); ++ DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr); ++ DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in); ++ DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps); ++ DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len); ++ } ++ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); ++ ++} ++ ++/** ++ * Attempts to halt a host channel. This function should only be called in ++ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under ++ * normal circumstances in DMA mode, the controller halts the channel when the ++ * transfer is complete or a condition occurs that requires application ++ * intervention. ++ * ++ * In slave mode, checks for a free request queue entry, then sets the Channel ++ * Enable and Channel Disable bits of the Host Channel Characteristics ++ * register of the specified channel to intiate the halt. If there is no free ++ * request queue entry, sets only the Channel Disable bit of the HCCHARn ++ * register to flush requests for this channel. In the latter case, sets a ++ * flag to indicate that the host channel needs to be halted when a request ++ * queue slot is open. ++ * ++ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the ++ * HCCHARn register. The controller ensures there is space in the request ++ * queue before submitting the halt request. ++ * ++ * Some time may elapse before the core flushes any posted requests for this ++ * host channel and halts. The Channel Halted interrupt handler completes the ++ * deactivation of the host channel. ++ * ++ * @param core_if Controller register interface. ++ * @param hc Host channel to halt. ++ * @param halt_status Reason for halting the channel. ++ */ ++void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc, dwc_otg_halt_status_e halt_status) ++{ ++ gnptxsts_data_t nptxsts; ++ hptxsts_data_t hptxsts; ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs; ++ dwc_otg_core_global_regs_t *global_regs; ++ dwc_otg_host_global_regs_t *host_global_regs; ++ ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ global_regs = core_if->core_global_regs; ++ host_global_regs = core_if->host_if->host_global_regs; ++ ++ DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS), ++ "halt_status = %d\n", halt_status); ++ ++ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || ++ halt_status == DWC_OTG_HC_XFER_AHB_ERR) { ++ /* ++ * Disable all channel interrupts except Ch Halted. The QTD ++ * and QH state associated with this transfer has been cleared ++ * (in the case of URB_DEQUEUE), so the channel needs to be ++ * shut down carefully to prevent crashes. ++ */ ++ hcintmsk_data_t hcintmsk; ++ hcintmsk.d32 = 0; ++ hcintmsk.b.chhltd = 1; ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32); ++ ++ /* ++ * Make sure no other interrupts besides halt are currently ++ * pending. Handling another interrupt could cause a crash due ++ * to the QTD and QH state. ++ */ ++ DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32); ++ ++ /* ++ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR ++ * even if the channel was already halted for some other ++ * reason. ++ */ ++ hc->halt_status = halt_status; ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen == 0) { ++ /* ++ * The channel is either already halted or it hasn't ++ * started yet. In DMA mode, the transfer may halt if ++ * it finishes normally or a condition occurs that ++ * requires driver intervention. Don't want to halt ++ * the channel again. In either Slave or DMA mode, ++ * it's possible that the transfer has been assigned ++ * to a channel, but not started yet when an URB is ++ * dequeued. Don't want to halt a channel that hasn't ++ * started yet. ++ */ ++ return; ++ } ++ } ++ if (hc->halt_pending) { ++ /* ++ * A halt has already been issued for this channel. This might ++ * happen when a transfer is aborted by a higher level in ++ * the stack. ++ */ ++#ifdef DEBUG ++ DWC_PRINTF ++ ("*** %s: Channel %d, _hc->halt_pending already set ***\n", ++ __func__, hc->hc_num); ++ ++#endif ++ return; ++ } ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* No need to set the bit in DDMA for disabling the channel */ ++ //TODO check it everywhere channel is disabled ++ if (!core_if->core_params->dma_desc_enable) ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 1; ++ ++ if (!core_if->dma_enable) { ++ /* Check for space in the request queue to issue the halt. */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK) { ++ nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ if (nptxsts.b.nptxqspcavail == 0) { ++ hcchar.b.chen = 0; ++ } ++ } else { ++ hptxsts.d32 = ++ DWC_READ_REG32(&host_global_regs->hptxsts); ++ if ((hptxsts.b.ptxqspcavail == 0) ++ || (core_if->queuing_high_bandwidth)) { ++ hcchar.b.chen = 0; ++ } ++ } ++ } ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->halt_status = halt_status; ++ ++ if (hcchar.b.chen) { ++ hc->halt_pending = 1; ++ hc->halt_on_queue = 0; ++ } else { ++ hc->halt_on_queue = 1; ++ } ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); ++ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending); ++ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue); ++ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status); ++ ++ return; ++} ++ ++/** ++ * Clears the transfer state for a host channel. This function is normally ++ * called after a transfer is done and the host channel is being released. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Identifies the host channel to clean up. ++ */ ++void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ dwc_otg_hc_regs_t *hc_regs; ++ ++ hc->xfer_started = 0; ++ ++ /* ++ * Clear channel interrupt enables and any unhandled channel interrupt ++ * conditions. ++ */ ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0); ++ DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF); ++#ifdef DEBUG ++ DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]); ++#endif ++} ++ ++/** ++ * Sets the channel property that indicates in which frame a periodic transfer ++ * should occur. This is always set to the _next_ frame. This function has no ++ * effect on non-periodic transfers. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Identifies the host channel to set up and its properties. ++ * @param hcchar Current value of the HCCHAR register for the specified host ++ * channel. ++ */ ++static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc, hcchar_data_t * hcchar) ++{ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ hfnum_data_t hfnum; ++ hfnum.d32 = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum); ++ ++ /* 1 if _next_ frame is odd, 0 if it's even */ ++ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; ++#ifdef DEBUG ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split ++ && !hc->complete_split) { ++ switch (hfnum.b.frnum & 0x7) { ++ case 7: ++ core_if->hfnum_7_samples++; ++ core_if->hfnum_7_frrem_accum += hfnum.b.frrem; ++ break; ++ case 0: ++ core_if->hfnum_0_samples++; ++ core_if->hfnum_0_frrem_accum += hfnum.b.frrem; ++ break; ++ default: ++ core_if->hfnum_other_samples++; ++ core_if->hfnum_other_frrem_accum += ++ hfnum.b.frrem; ++ break; ++ } ++ } ++#endif ++ } ++} ++ ++#ifdef DEBUG ++void hc_xfer_timeout(void *ptr) ++{ ++ hc_xfer_info_t *xfer_info = NULL; ++ int hc_num = 0; ++ ++ if (ptr) ++ xfer_info = (hc_xfer_info_t *) ptr; ++ ++ if (!xfer_info->hc) { ++ DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc); ++ return; ++ } ++ ++ hc_num = xfer_info->hc->hc_num; ++ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); ++ DWC_WARN(" start_hcchar_val 0x%08x\n", ++ xfer_info->core_if->start_hcchar_val[hc_num]); ++} ++#endif ++ ++void ep_xfer_timeout(void *ptr) ++{ ++ ep_xfer_info_t *xfer_info = NULL; ++ int ep_num = 0; ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintsts_data_t gintsts = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ if (ptr) ++ xfer_info = (ep_xfer_info_t *) ptr; ++ ++ if (!xfer_info->ep) { ++ DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep); ++ return; ++ } ++ ++ ep_num = xfer_info->ep->num; ++ DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num); ++ /* Put the sate to 2 as it was time outed */ ++ xfer_info->state = 2; ++ ++ dctl.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl); ++ gintsts.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts); ++ gintmsk.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk); ++ ++ if (!gintmsk.b.goutnakeff) { ++ /* Unmask it */ ++ gintmsk.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk, ++ gintmsk.d32); ++ ++ } ++ ++ if (!gintsts.b.goutnakeff) { ++ dctl.b.sgoutnak = 1; ++ } ++ DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ ++} ++ ++void set_pid_isoc(dwc_hc_t * hc) ++{ ++ /* Set up the initial PID for the transfer. */ ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) { ++ if (hc->ep_is_in) { ++ if (hc->multi_count == 1) { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } else if (hc->multi_count == 2) { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; ++ } else { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA2; ++ } ++ } else { ++ if (hc->multi_count == 1) { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } else { ++ hc->data_pid_start = DWC_OTG_HC_PID_MDATA; ++ } ++ } ++ } else { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for a host channel and ++ * starts the transfer. May be called in either Slave mode or DMA mode. In ++ * Slave mode, the caller must ensure that there is sufficient space in the ++ * request queue and Tx Data FIFO. ++ * ++ * For an OUT transfer in Slave mode, it loads a data packet into the ++ * appropriate FIFO. If necessary, additional data packets will be loaded in ++ * the Host ISR. ++ * ++ * For an IN transfer in Slave mode, a data packet is requested. The data ++ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, ++ * additional data packets are requested in the Host ISR. ++ * ++ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ ++ * register along with a packet count of 1 and the channel is enabled. This ++ * causes a single PING transaction to occur. Other fields in HCTSIZ are ++ * simply set to 0 since no data transfer occurs in this case. ++ * ++ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with ++ * all the information required to perform the subsequent data transfer. In ++ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the ++ * controller performs the entire PING protocol, then starts the data ++ * transfer. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Information needed to initialize the host channel. The xfer_len ++ * value may be reduced to accommodate the max widths of the XferSize and ++ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed ++ * to reflect the final xfer_len value. ++ */ ++void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ uint16_t num_packets; ++ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size; ++ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count; ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ ++ hctsiz.d32 = 0; ++ ++ if (hc->do_ping) { ++ if (!core_if->dma_enable) { ++ dwc_otg_hc_do_ping(core_if, hc); ++ hc->xfer_started = 1; ++ return; ++ } else { ++ hctsiz.b.dopng = 1; ++ } ++ } ++ ++ if (hc->do_split) { ++ num_packets = 1; ++ ++ if (hc->complete_split && !hc->ep_is_in) { ++ /* For CSPLIT OUT Transfer, set the size to 0 so the ++ * core doesn't expect any data written to the FIFO */ ++ hc->xfer_len = 0; ++ } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { ++ hc->xfer_len = hc->max_packet; ++ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { ++ hc->xfer_len = 188; ++ } ++ ++ hctsiz.b.xfersize = hc->xfer_len; ++ } else { ++ /* ++ * Ensure that the transfer length and packet count will fit ++ * in the widths allocated for them in the HCTSIZn register. ++ */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * Make sure the transfer size is no larger than one ++ * (micro)frame's worth of data. (A check was done ++ * when the periodic transfer was accepted to ensure ++ * that a (micro)frame's worth of data can be ++ * programmed into a channel.) ++ */ ++ uint32_t max_periodic_len = ++ hc->multi_count * hc->max_packet; ++ if (hc->xfer_len > max_periodic_len) { ++ hc->xfer_len = max_periodic_len; ++ } else { ++ } ++ } else if (hc->xfer_len > max_hc_xfer_size) { ++ /* Make sure that xfer_len is a multiple of max packet size. */ ++ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1; ++ } ++ ++ if (hc->xfer_len > 0) { ++ num_packets = ++ (hc->xfer_len + hc->max_packet - ++ 1) / hc->max_packet; ++ if (num_packets > max_hc_pkt_count) { ++ num_packets = max_hc_pkt_count; ++ hc->xfer_len = num_packets * hc->max_packet; ++ } ++ } else { ++ /* Need 1 packet for transfer length of 0. */ ++ num_packets = 1; ++ } ++ ++ if (hc->ep_is_in) { ++ /* Always program an integral # of max packets for IN transfers. */ ++ hc->xfer_len = num_packets * hc->max_packet; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * Make sure that the multi_count field matches the ++ * actual transfer length. ++ */ ++ hc->multi_count = num_packets; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ set_pid_isoc(hc); ++ ++ hctsiz.b.xfersize = hc->xfer_len; ++ } ++ ++ hc->start_pkt_count = num_packets; ++ hctsiz.b.pktcnt = num_packets; ++ hctsiz.b.pid = hc->data_pid_start; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); ++ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); ++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); ++ ++ if (core_if->dma_enable) { ++ dwc_dma_t dma_addr; ++ if (hc->align_buff) { ++ dma_addr = hc->align_buff; ++ } else { ++ dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff); ++ } ++ DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr); ++ } ++ ++ /* Start the split */ ++ if (hc->do_split) { ++ hcsplt_data_t hcsplt; ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ hcsplt.b.spltena = 1; ++ DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32); ++ } ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.multicnt = hc->multi_count; ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++#ifdef DEBUG ++ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", ++ __func__, hc->hc_num, hcchar.d32); ++ } ++#endif ++ ++ /* Set host channel enable after all other setup is complete. */ ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->xfer_started = 1; ++ hc->requests++; ++ ++ if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) { ++ /* Load OUT packet into the appropriate Tx FIFO. */ ++ dwc_otg_hc_write_packet(core_if, hc); ++ } ++#ifdef DEBUG ++ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { ++ DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n", ++ hc->hc_num, core_if);//GRAYG ++ core_if->hc_xfer_info[hc->hc_num].core_if = core_if; ++ core_if->hc_xfer_info[hc->hc_num].hc = hc; ++ ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); ++ } ++#endif ++} ++ ++/** ++ * This function does the setup for a data transfer for a host channel ++ * and starts the transfer in Descriptor DMA mode. ++ * ++ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. ++ * Sets PID and NTD values. For periodic transfers ++ * initializes SCHED_INFO field with micro-frame bitmap. ++ * ++ * Initializes HCDMA register with descriptor list address and CTD value ++ * then starts the transfer via enabling the channel. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Information needed to initialize the host channel. ++ */ ++void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcdma_data_t hcdma; ++ ++ hctsiz.d32 = 0; ++ ++ if (hc->do_ping) ++ hctsiz.b_ddma.dopng = 1; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ set_pid_isoc(hc); ++ ++ /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ ++ hctsiz.b_ddma.pid = hc->data_pid_start; ++ hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */ ++ hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */ ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); ++ DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd); ++ ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ hcdma.d32 = 0; ++ hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11; ++ ++ /* Always start from first descriptor. */ ++ hcdma.b.ctd = 0; ++ DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.multicnt = hc->multi_count; ++ ++#ifdef DEBUG ++ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", ++ __func__, hc->hc_num, hcchar.d32); ++ } ++#endif ++ ++ /* Set host channel enable after all other setup is complete. */ ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->xfer_started = 1; ++ hc->requests++; ++ ++#ifdef DEBUG ++ if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) ++ && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) { ++ DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n", ++ hc->hc_num, core_if);//GRAYG ++ core_if->hc_xfer_info[hc->hc_num].core_if = core_if; ++ core_if->hc_xfer_info[hc->hc_num].hc = hc; ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); ++ } ++#endif ++ ++} ++ ++/** ++ * This function continues a data transfer that was started by previous call ++ * to dwc_otg_hc_start_transfer. The caller must ensure there is ++ * sufficient space in the request queue and Tx Data FIFO. This function ++ * should only be called in Slave mode. In DMA mode, the controller acts ++ * autonomously to complete transfers programmed to a host channel. ++ * ++ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO ++ * if there is any data remaining to be queued. For an IN transfer, another ++ * data packet is always requested. For the SETUP phase of a control transfer, ++ * this function does nothing. ++ * ++ * @return 1 if a new request is queued, 0 if no more requests are required ++ * for this transfer. ++ */ ++int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ ++ if (hc->do_split) { ++ /* SPLITs always queue just once per channel */ ++ return 0; ++ } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { ++ /* SETUPs are queued only once since they can't be NAKed. */ ++ return 0; ++ } else if (hc->ep_is_in) { ++ /* ++ * Always queue another request for other IN transfers. If ++ * back-to-back INs are issued and NAKs are received for both, ++ * the driver may still be processing the first NAK when the ++ * second NAK is received. When the interrupt handler clears ++ * the NAK interrupt for the first NAK, the second NAK will ++ * not be seen. So we can't depend on the NAK interrupt ++ * handler to requeue a NAKed request. Instead, IN requests ++ * are issued each time this function is called. When the ++ * transfer completes, the extra requests for the channel will ++ * be flushed. ++ */ ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs = ++ core_if->host_if->hc_regs[hc->hc_num]; ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", ++ hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ hc->requests++; ++ return 1; ++ } else { ++ /* OUT transfers. */ ++ if (hc->xfer_count < hc->xfer_len) { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs; ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++ } ++ ++ /* Load OUT packet into the appropriate Tx FIFO. */ ++ dwc_otg_hc_write_packet(core_if, hc); ++ hc->requests++; ++ return 1; ++ } else { ++ return 0; ++ } ++ } ++} ++ ++/** ++ * Starts a PING transfer. This function should only be called in Slave mode. ++ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. ++ */ ++void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ ++ hctsiz.d32 = 0; ++ hctsiz.b.dopng = 1; ++ hctsiz.b.pktcnt = 1; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++} ++ ++/* ++ * This function writes a packet into the Tx FIFO associated with the Host ++ * Channel. For a channel associated with a non-periodic EP, the non-periodic ++ * Tx FIFO is written. For a channel associated with a periodic EP, the ++ * periodic Tx FIFO is written. This function should only be called in Slave ++ * mode. ++ * ++ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by ++ * then number of bytes written to the Tx FIFO. ++ */ ++void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ uint32_t i; ++ uint32_t remaining_count; ++ uint32_t byte_count; ++ uint32_t dword_count; ++ ++ uint32_t *data_buff = (uint32_t *) (hc->xfer_buff); ++ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num]; ++ ++ remaining_count = hc->xfer_len - hc->xfer_count; ++ if (remaining_count > hc->max_packet) { ++ byte_count = hc->max_packet; ++ } else { ++ byte_count = remaining_count; ++ } ++ ++ dword_count = (byte_count + 3) / 4; ++ ++ if ((((unsigned long)data_buff) & 0x3) == 0) { ++ /* xfer_buff is DWORD aligned. */ ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ DWC_WRITE_REG32(data_fifo, *data_buff); ++ } ++ } else { ++ /* xfer_buff is not DWORD aligned. */ ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ uint32_t data; ++ data = ++ (data_buff[0] | data_buff[1] << 8 | data_buff[2] << ++ 16 | data_buff[3] << 24); ++ DWC_WRITE_REG32(data_fifo, data); ++ } ++ } ++ ++ hc->xfer_count += byte_count; ++ hc->xfer_buff += byte_count; ++} ++ ++/** ++ * Gets the current USB frame number. This is the frame number from the last ++ * SOF packet. ++ */ ++uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ /* read current frame/microframe number from DSTS register */ ++ return dsts.b.soffn; ++} ++ ++/** ++ * Calculates and gets the frame Interval value of HFIR register according PHY ++ * type and speed.The application can modify a value of HFIR register only after ++ * the Port Enable bit of the Host Port Control and Status register ++ * (HPRT.PrtEnaPort) has been set. ++*/ ++ ++uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ hwcfg2_data_t hwcfg2; ++ hprt0_data_t hprt0; ++ int clock = 60; // default value ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2); ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif) ++ clock = 60; ++ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3) ++ clock = 48; ++ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif) ++ clock = 30; ++ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif) ++ clock = 60; ++ if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif) ++ clock = 48; ++ if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2) ++ clock = 48; ++ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1) ++ clock = 48; ++ if (hprt0.b.prtspd == 0) ++ /* High speed case */ ++ return 125 * clock; ++ else ++ /* FS/LS case */ ++ return 1000 * clock; ++} ++ ++/** ++ * This function reads a setup packet from the Rx FIFO into the destination ++ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) ++ * Interrupt routine when a SETUP packet has been received in Slave mode. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dest Destination buffer for packet data. ++ */ ++void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest) ++{ ++ device_grxsts_data_t status; ++ /* Get the 8 bytes of a setup transaction data */ ++ ++ /* Pop 2 DWORDS off the receive data FIFO into memory */ ++ dest[0] = DWC_READ_REG32(core_if->data_fifo[0]); ++ dest[1] = DWC_READ_REG32(core_if->data_fifo[0]); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ status.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->grxstsp); ++ DWC_DEBUGPL(DBG_ANY, ++ "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n", ++ status.b.epnum, status.b.bcnt, status.b.pktsts, ++ status.b.fn, status.b.fn); ++ } ++} ++ ++/** ++ * This function enables EP0 OUT to receive SETUP packets and configures EP0 ++ * IN for transmitting packets. It is normally called when the ++ * "Enumeration Done" interrupt occurs. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dsts_data_t dsts; ++ depctl_data_t diepctl; ++ depctl_data_t doepctl; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ ep->stp_rollover = 0; ++ /* Read the Device Status and Endpoint 0 Control registers */ ++ dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts); ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl); ++ ++ /* Set the MPS of the IN EP based on the enumeration speed */ ++ switch (dsts.b.enumspd) { ++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: ++ diepctl.b.mps = DWC_DEP0CTL_MPS_64; ++ break; ++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: ++ diepctl.b.mps = DWC_DEP0CTL_MPS_8; ++ break; ++ } ++ ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Enable OUT EP for receive */ ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ doepctl.b.epena = 1; ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ } ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", ++ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl)); ++#endif ++ dctl.b.cgnpinnak = 1; ++ ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n", ++ DWC_READ_REG32(&dev_if->dev_global_regs->dctl)); ++ ++} ++ ++/** ++ * This function activates an EP. The Device EP control register for ++ * the EP is configured as defined in the ep structure. Note: This ++ * function is not used for EP0. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to activate. ++ */ ++void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ depctl_data_t depctl; ++ volatile uint32_t *addr; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg; ++ uint8_t i; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++#ifdef DWC_UTE_PER_IO ++ ep->xiso_frame_num = 0xFFFFFFFF; ++ ep->xiso_active_xfers = 0; ++ ep->xiso_queued_xfers = 0; ++#endif ++ /* Read DEPCTLn register */ ++ if (ep->is_in == 1) { ++ addr = &dev_if->in_ep_regs[ep->num]->diepctl; ++ daintmsk.ep.in = 1 << ep->num; ++ } else { ++ addr = &dev_if->out_ep_regs[ep->num]->doepctl; ++ daintmsk.ep.out = 1 << ep->num; ++ } ++ ++ /* If the EP is already active don't change the EP Control ++ * register. */ ++ depctl.d32 = DWC_READ_REG32(addr); ++ if (!depctl.b.usbactep) { ++ depctl.b.mps = ep->maxpacket; ++ depctl.b.eptype = ep->type; ++ depctl.b.txfnum = ep->tx_fifo_num; ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ depctl.b.setd0pid = 1; // ??? ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ depctl.b.usbactep = 1; ++ ++ /* Update nextep_seq array and EPMSCNT in DCFG*/ ++ if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq) ++ break; ++ } ++ core_if->nextep_seq[i] = ep->num; ++ core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq; ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt++; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", ++ core_if->nextep_seq[i]); ++ } ++ ++ } ++ ++ ++ DWC_WRITE_REG32(addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr)); ++ } ++ ++ /* Enable the Interrupt for this EP */ ++ if (core_if->multiproc_int_enable) { ++ if (ep->is_in == 1) { ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ diepmsk.b.intknepmis = 1; ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; ++ diepmsk.b.txfifoundrn = 1; //????? ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ diepmsk.b.nak = 1; ++ } ++ ++ ++ ++/* ++ if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++*/ ++/* ++ if (core_if->dma_enable) { ++ doepmsk.b.nak = 1; ++ } ++*/ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs-> ++ diepeachintmsk[ep->num], diepmsk.d32); ++ ++ } else { ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) ++ doepmsk.b.outtknepdis = 1; ++ ++/* ++ ++ if (core_if->dma_desc_enable) { ++ doepmsk.b.bna = 1; ++ } ++*/ ++/* ++ doepmsk.b.babble = 1; ++ doepmsk.b.nyet = 1; ++ doepmsk.b.nak = 1; ++*/ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs-> ++ doepeachintmsk[ep->num], doepmsk.d32); ++ } ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk, ++ 0, daintmsk.d32); ++ } else { ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (ep->is_in) { ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.nak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32); ++ } else { ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ doepmsk.b.outtknepdis = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32); ++ } ++ } ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk, ++ 0, daintmsk.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n", ++ DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk)); ++ ++ ep->stall_clear_flag = 0; ++ ++ return; ++} ++ ++/** ++ * This function deactivates an EP. This is done by clearing the USB Active ++ * EP bit in the Device EP control register. Note: This function is not used ++ * for EP0. EP0 cannot be deactivated. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to deactivate. ++ */ ++void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg; ++ uint8_t i = 0; ++ ++#ifdef DWC_UTE_PER_IO ++ ep->xiso_frame_num = 0xFFFFFFFF; ++ ep->xiso_active_xfers = 0; ++ ep->xiso_queued_xfers = 0; ++#endif ++ ++ /* Read DEPCTLn register */ ++ if (ep->is_in == 1) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ daintmsk.ep.in = 1 << ep->num; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ daintmsk.ep.out = 1 << ep->num; ++ } ++ ++ depctl.d32 = DWC_READ_REG32(addr); ++ ++ depctl.b.usbactep = 0; ++ ++ /* Update nextep_seq array and EPMSCNT in DCFG*/ ++ if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == ep->num) ++ break; ++ } ++ core_if->nextep_seq[i] = core_if->nextep_seq[ep->num]; ++ if (core_if->first_in_nextep_seq == ep->num) ++ core_if->first_in_nextep_seq = i; ++ core_if->nextep_seq[ep->num] = 0xff; ++ depctl.b.nextep = 0; ++ dcfg.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt--; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); ++ } ++ } ++ ++ if (ep->is_in == 1) ++ depctl.b.txfnum = 0; ++ ++ if (core_if->dma_desc_enable) ++ depctl.b.epdis = 1; ++ ++ DWC_WRITE_REG32(addr, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); ++ if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC ++ && depctl.b.epena) { ++ depctl_data_t depctl = {.d32 = 0}; ++ if (ep->is_in) { ++ diepint_data_t diepint = {.d32 = 0}; ++ ++ depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepctl, depctl.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[ep->num]-> ++ diepint); ++ } while (!diepint.b.inepnakeff); ++ diepint.b.inepnakeff = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepint, diepint.d32); ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepctl, depctl.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[ep->num]-> ++ diepint); ++ } while (!diepint.b.epdisabled); ++ diepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepint, diepint.d32); ++ } else { ++ dctl_data_t dctl = {.d32 = 0}; ++ gintmsk_data_t gintsts = {.d32 = 0}; ++ doepint_data_t doepint = {.d32 = 0}; ++ dctl.b.sgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl.d32); ++ do { ++ dwc_udelay(10); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ } while (!gintsts.b.goutnakeff); ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32); ++ do ++ { ++ dwc_udelay(10); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doepint); ++ } while (!doepint.b.epdisabled); ++ ++ doepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32); ++ ++ dctl.d32 = 0; ++ dctl.b.cgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ } ++ ++ /* Disable the Interrupt for this EP */ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, ++ daintmsk.d32, 0); ++ ++ if (ep->is_in == 1) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[ep->num], 0); ++ } else { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[ep->num], 0); ++ } ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk, ++ daintmsk.d32, 0); ++ } ++ ++} ++ ++/** ++ * This function initializes dma descriptor chain. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ uint32_t offset; ++ uint32_t xfer_est; ++ int i; ++ unsigned maxxfer_local, total_len; ++ ++ if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR && ++ (ep->maxpacket%4)) { ++ maxxfer_local = ep->maxpacket; ++ total_len = ep->xfer_len; ++ } else { ++ maxxfer_local = ep->maxxfer; ++ total_len = ep->total_len; ++ } ++ ++ ep->desc_cnt = (total_len / maxxfer_local) + ++ ((total_len % maxxfer_local) ? 1 : 0); ++ ++ if (!ep->desc_cnt) ++ ep->desc_cnt = 1; ++ ++ if (ep->desc_cnt > MAX_DMA_DESC_CNT) ++ ep->desc_cnt = MAX_DMA_DESC_CNT; ++ ++ dma_desc = ep->desc_addr; ++ if (maxxfer_local == ep->maxpacket) { ++ if ((total_len % maxxfer_local) && ++ (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) { ++ xfer_est = (ep->desc_cnt - 1) * maxxfer_local + ++ (total_len % maxxfer_local); ++ } else ++ xfer_est = ep->desc_cnt * maxxfer_local; ++ } else ++ xfer_est = total_len; ++ offset = 0; ++ for (i = 0; i < ep->desc_cnt; ++i) { ++ /** DMA Descriptor Setup */ ++ if (xfer_est > maxxfer_local) { ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 0; ++ dma_desc->status.b.ioc = 0; ++ dma_desc->status.b.sp = 0; ++ dma_desc->status.b.bytes = maxxfer_local; ++ dma_desc->buf = ep->dma_addr + offset; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ xfer_est -= maxxfer_local; ++ offset += maxxfer_local; ++ } else { ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ if (ep->is_in) { ++ dma_desc->status.b.sp = ++ (xfer_est % ++ ep->maxpacket) ? 1 : ((ep-> ++ sent_zlp) ? 1 : 0); ++ dma_desc->status.b.bytes = xfer_est; ++ } else { ++ if (maxxfer_local == ep->maxpacket) ++ dma_desc->status.b.bytes = xfer_est; ++ else ++ dma_desc->status.b.bytes = ++ xfer_est + ((4 - (xfer_est & 0x3)) & 0x3); ++ } ++ ++ dma_desc->buf = ep->dma_addr + offset; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ } ++ dma_desc++; ++ } ++} ++/** ++ * This function is called when to write ISOC data into appropriate dedicated ++ * periodic FIFO. ++ */ ++static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ uint32_t len = 0; ++ int epnum = dwc_ep->num; ++ int dwords; ++ ++ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = dwc_ep->xfer_len - dwc_ep->xfer_count; ++ ++ if (len > dwc_ep->maxpacket) { ++ len = dwc_ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, dwc_ep, 0); ++ ++ len = dwc_ep->xfer_len - dwc_ep->xfer_count; ++ if (len > dwc_ep->maxpacket) { ++ len = dwc_ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, ++ txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts)); ++ ++ return 1; ++} ++/** ++ * This function does the setup for a data transfer for an EP and ++ * starts the transfer. For an IN transfer, the packets will be ++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, ++ * the packets are unloaded from the Rx FIFO in the ISR. the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n", ++ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len, ++ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff, ++ ep->total_len); ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[ep->num]; ++ ++ gnptxsts_data_t gtxstatus; ++ ++ gtxstatus.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); ++ ++ if (core_if->en_multiple_tx_fifo == 0 ++ && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) { ++#ifdef DEBUG ++ DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32); ++#endif ++ return; ++ } ++ ++ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz)); ++ ++ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT) ++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? ++ ep->maxxfer : (ep->total_len - ep->xfer_len); ++ else ++ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ? ++ MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len); ++ ++ ++ /* Zero Length Packet? */ ++ if ((ep->xfer_len - ep->xfer_count) == 0) { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - ep->xfer_count - 1 + ++ ep->maxpacket) / ep->maxpacket; ++ if (deptsiz.b.pktcnt > MAX_PKT_CNT) { ++ deptsiz.b.pktcnt = MAX_PKT_CNT; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ } ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) ++ deptsiz.b.mc = deptsiz.b.pktcnt; ++ } ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ if (ep->type != DWC_OTG_EP_TYPE_ISOC) ++ deptsiz.b.mc = 1; ++ DWC_WRITE_REG32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++#ifdef DWC_UTE_CFI ++ /* The descriptor chain should be already initialized by now */ ++ if (ep->buff_mode != BM_STANDARD) { ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ ep->descs_dma_addr); ++ } else { ++#endif ++ init_dma_desc_chain(core_if, ep); ++ /** DIEPDMAn Register write */ ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ ep->dma_desc_addr); ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ } ++ } else { ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ if (ep->type != DWC_OTG_EP_TYPE_ISOC) { ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, ++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, ++ * the data will be written into the fifo by the ISR. ++ */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk = 1 << ep->num; ++ DWC_MODIFY_REG32 ++ (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ ++ } ++ } ++ } else { ++ write_isoc_tx_fifo(core_if, ep); ++ } ++ } ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ dsts_data_t dsts = {.d32 = 0}; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dsts); ++ ep->frame_num = dsts.b.soffn + ep->bInterval; ++ if (ep->frame_num > 0x3FFF) { ++ ep->frm_overrun = 1; ++ ep->frame_num &= 0x3FFF; ++ } else ++ ep->frm_overrun = 0; ++ if (ep->frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } ++ } ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); ++ ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[ep->num]; ++ ++ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz)); ++ ++ if (!core_if->dma_desc_enable) { ++ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT) ++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? ++ ep->maxxfer : (ep->total_len - ep->xfer_len); ++ else ++ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len ++ - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len); ++ } ++ ++ /* Program the transfer size and packet count as follows: ++ * ++ * pktcnt = N ++ * xfersize = N * maxpacket ++ */ ++ if ((ep->xfer_len - ep->xfer_count) == 0) { ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - ep->xfer_count + ++ (ep->maxpacket - 1)) / ep->maxpacket; ++ if (deptsiz.b.pktcnt > MAX_PKT_CNT) { ++ deptsiz.b.pktcnt = MAX_PKT_CNT; ++ } ++ if (!core_if->dma_desc_enable) { ++ ep->xfer_len = ++ deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count; ++ } ++ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", ++ ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++#ifdef DWC_UTE_CFI ++ /* The descriptor chain should be already initialized by now */ ++ if (ep->buff_mode != BM_STANDARD) { ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ ep->descs_dma_addr); ++ } else { ++#endif ++ /** This is used for interrupt out transfers*/ ++ if (!ep->xfer_len) ++ ep->xfer_len = ep->total_len; ++ init_dma_desc_chain(core_if, ep); ++ ++ if (core_if->core_params->dev_out_nak) { ++ if (ep->type == DWC_OTG_EP_TYPE_BULK) { ++ deptsiz.b.pktcnt = (ep->total_len + ++ (ep->maxpacket - 1)) / ep->maxpacket; ++ deptsiz.b.xfersize = ep->total_len; ++ /* Remember initial value of doeptsiz */ ++ core_if->start_doeptsiz_val[ep->num] = deptsiz.d32; ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ } ++ } ++ /** DOEPDMAn Register write */ ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ ep->dma_desc_addr); ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ } ++ } else { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ dsts_data_t dsts = {.d32 = 0}; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dsts); ++ ep->frame_num = dsts.b.soffn + ep->bInterval; ++ if (ep->frame_num > 0x3FFF) { ++ ep->frm_overrun = 1; ++ ep->frame_num &= 0x3FFF; ++ } else ++ ep->frm_overrun = 0; ++ ++ if (ep->frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); ++ ++ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", ++ DWC_READ_REG32(&out_regs->doepctl), ++ DWC_READ_REG32(&out_regs->doeptsiz)); ++ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs-> ++ daintmsk), ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gintmsk)); ++ ++ /* Timer is scheduling only for out bulk transfers for ++ * "Device DDMA OUT NAK Enhancement" feature to inform user ++ * about received data payload in case of timeout ++ */ ++ if (core_if->core_params->dev_out_nak) { ++ if (ep->type == DWC_OTG_EP_TYPE_BULK) { ++ core_if->ep_xfer_info[ep->num].core_if = core_if; ++ core_if->ep_xfer_info[ep->num].ep = ep; ++ core_if->ep_xfer_info[ep->num].state = 1; ++ ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000); ++ } ++ } ++ } ++} ++ ++/** ++ * This function setup a zero length transfer in Buffer DMA and ++ * Slave modes for usb requests with zero field set ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ ++ depctl_data_t depctl; ++ deptsiz_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); ++ DWC_PRINTF("zero length transfer is called\n"); ++ ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[ep->num]; ++ ++ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz)); ++ ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.b.mc = 1; ++ DWC_WRITE_REG32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ } else { ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, ++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, ++ * the data will be written into the fifo by the ISR. ++ */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk = 1 << ep->num; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); ++ ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[ep->num]; ++ ++ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz)); ++ ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ } else { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); ++ ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for EP0 and starts ++ * the transfer. For an IN transfer, the packets will be loaded into ++ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are ++ * unloaded from the Rx FIFO in the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz0_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p \n", ++ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len, ++ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff); ++ ++ ep->total_len = ep->xfer_len; ++ ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[0]; ++ ++ gnptxsts_data_t gtxstatus; ++ ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ if (depctl.b.epena) ++ return; ++ } ++ ++ gtxstatus.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); ++ ++ /* If dedicated FIFO every time flush fifo before enable ep*/ ++ if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a) ++ dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num); ++ ++ if (core_if->en_multiple_tx_fifo == 0 ++ && gtxstatus.b.nptxqspcavail == 0 ++ && !core_if->dma_enable) { ++#ifdef DEBUG ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); ++ DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n", ++ DWC_READ_REG32(&in_regs->diepctl)); ++ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", ++ deptsiz.d32, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n", ++ gtxstatus.d32); ++#endif ++ return; ++ } ++ ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); ++ ++ /* Zero Length Packet? */ ++ if (ep->xfer_len == 0) { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ if (ep->xfer_len > ep->maxpacket) { ++ ep->xfer_len = ep->maxpacket; ++ deptsiz.b.xfersize = ep->maxpacket; ++ } else { ++ deptsiz.b.xfersize = ep->xfer_len; ++ } ++ deptsiz.b.pktcnt = 1; ++ ++ } ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ DWC_WRITE_REG32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++ dma_desc = core_if->dev_if->in_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.sp = ++ (ep->xfer_len == ep->maxpacket) ? 0 : 1; ++ dma_desc->status.b.bytes = ep->xfer_len; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DIEPDMA0 Register write */ ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ core_if-> ++ dev_if->dma_in_desc_addr); ++ } ++ } else { ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ } ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); ++ ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (!core_if->dma_enable) { ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk |= 1 << ep->num; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[0]; ++ ++ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl); ++ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz); ++ ++ /* Program the transfer size and packet count as follows: ++ * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) ++ * pktcnt = N */ ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) ++ deptsiz.b.supcnt = 3; ++ ++ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++ dma_desc = core_if->dev_if->out_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ dma_desc->status.b.mtrf = 0; ++ dma_desc->status.b.sr = 0; ++ } ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = ep->maxpacket; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ core_if->dev_if-> ++ dma_out_desc_addr); ++ } ++ } else { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32); ++ } ++} ++ ++/** ++ * This function continues control IN transfers started by ++ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a ++ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one ++ * bit for the packet count. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz0_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[0]; ++ gnptxsts_data_t tx_status = {.d32 = 0 }; ++ ++ tx_status.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); ++ /** @todo Should there be check for room in the Tx ++ * Status Queue. If not remove the code above this comment. */ ++ ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); ++ ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.b.xfersize = ++ (ep->total_len - ep->xfer_count) > ++ ep->maxpacket ? ep->maxpacket : (ep->total_len - ++ ep->xfer_count); ++ deptsiz.b.pktcnt = 1; ++ if (core_if->dma_enable == 0) { ++ ep->xfer_len += deptsiz.b.xfersize; ++ } else { ++ ep->xfer_len = deptsiz.b.xfersize; ++ } ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ } else { ++ ep->xfer_len = ++ (ep->total_len - ep->xfer_count) > ++ ep->maxpacket ? ep->maxpacket : (ep->total_len - ++ ep->xfer_count); ++ ++ dma_desc = core_if->dev_if->in_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.sp = ++ (ep->xfer_len == ep->maxpacket) ? 0 : 1; ++ dma_desc->status.b.bytes = ep->xfer_len; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DIEPDMA0 Register write */ ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ core_if->dev_if->dma_in_desc_addr); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { ++ if (core_if->dma_desc_enable == 0) ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); ++ ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (!core_if->dma_enable) { ++ if (core_if->en_multiple_tx_fifo == 0) { ++ /* First clear it from GINTSTS */ ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk |= 1 << ep->num; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ } else { ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[0]; ++ ++ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl); ++ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz); ++ ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ ++ if (core_if->dma_desc_enable == 0) { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } else { ++ dma_desc = core_if->dev_if->out_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = ep->maxpacket; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ core_if->dev_if->dma_out_desc_addr); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { ++ if (core_if->dma_desc_enable == 0) ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); ++ ++ } ++} ++ ++#ifdef DEBUG ++void dump_msg(const u8 * buf, unsigned int length) ++{ ++ unsigned int start, num, i; ++ char line[52], *p; ++ ++ if (length >= 512) ++ return; ++ start = 0; ++ while (length > 0) { ++ num = length < 16u ? length : 16u; ++ p = line; ++ for (i = 0; i < num; ++i) { ++ if (i == 8) ++ *p++ = ' '; ++ DWC_SPRINTF(p, " %02x", buf[i]); ++ p += 3; ++ } ++ *p = 0; ++ DWC_PRINTF("%6x: %s\n", start, line); ++ buf += num; ++ start += num; ++ length -= num; ++ } ++} ++#else ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++} ++#endif ++ ++/** ++ * This function writes a packet into the Tx FIFO associated with the ++ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For ++ * periodic EPs the periodic Tx FIFO associated with the EP is written ++ * with all packets for the next micro-frame. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to write packet for. ++ * @param dma Indicates if DMA is being used. ++ */ ++void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep, ++ int dma) ++{ ++ /** ++ * The buffer is padded to DWORD on a per packet basis in ++ * slave/dma mode if the MPS is not DWORD aligned. The last ++ * packet, if short, is also padded to a multiple of DWORD. ++ * ++ * ep->xfer_buff always starts DWORD aligned in memory and is a ++ * multiple of DWORD in length ++ * ++ * ep->xfer_len can be any number of bytes ++ * ++ * ep->xfer_count is a multiple of ep->maxpacket until the last ++ * packet ++ * ++ * FIFO access is DWORD */ ++ ++ uint32_t i; ++ uint32_t byte_count; ++ uint32_t dword_count; ++ uint32_t *fifo; ++ uint32_t *data_buff = (uint32_t *) ep->xfer_buff; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ++ ep); ++ if (ep->xfer_count >= ep->xfer_len) { ++ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num); ++ return; ++ } ++ ++ /* Find the byte length of the packet either short packet or MPS */ ++ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) { ++ byte_count = ep->xfer_len - ep->xfer_count; ++ } else { ++ byte_count = ep->maxpacket; ++ } ++ ++ /* Find the DWORD length, padded by extra bytes as neccessary if MPS ++ * is not a multiple of DWORD */ ++ dword_count = (byte_count + 3) / 4; ++ ++#ifdef VERBOSE ++ dump_msg(ep->xfer_buff, byte_count); ++#endif ++ ++ /**@todo NGS Where are the Periodic Tx FIFO addresses ++ * intialized? What should this be? */ ++ ++ fifo = core_if->data_fifo[ep->num]; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", ++ fifo, data_buff, *data_buff, byte_count); ++ ++ if (!dma) { ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ DWC_WRITE_REG32(fifo, *data_buff); ++ } ++ } ++ ++ ep->xfer_count += byte_count; ++ ep->xfer_buff += byte_count; ++ ep->dma_addr += byte_count; ++} ++ ++/** ++ * Set the EP STALL. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to set the stall on. ++ */ ++void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ volatile uint32_t *depctl_addr; ++ ++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++ if (ep->is_in == 1) { ++ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); ++ depctl.d32 = DWC_READ_REG32(depctl_addr); ++ ++ /* set the disable and stall bits */ ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ } ++ depctl.b.stall = 1; ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); ++ } else { ++ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); ++ depctl.d32 = DWC_READ_REG32(depctl_addr); ++ ++ /* set the stall bit */ ++ depctl.b.stall = 1; ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr)); ++ ++ return; ++} ++ ++/** ++ * Clear the EP STALL. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to clear stall from. ++ */ ++void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ volatile uint32_t *depctl_addr; ++ ++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++ if (ep->is_in == 1) { ++ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); ++ } else { ++ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); ++ } ++ ++ depctl.d32 = DWC_READ_REG32(depctl_addr); ++ ++ /* clear the stall bits */ ++ depctl.b.stall = 0; ++ ++ /* ++ * USB Spec 9.4.5: For endpoints using data toggle, regardless ++ * of whether an endpoint has the Halt feature set, a ++ * ClearFeature(ENDPOINT_HALT) request always results in the ++ * data toggle being reinitialized to DATA0. ++ */ ++ if (ep->type == DWC_OTG_EP_TYPE_INTR || ++ ep->type == DWC_OTG_EP_TYPE_BULK) { ++ depctl.b.setd0pid = 1; /* DATA0 */ ++ } ++ ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr)); ++ return; ++} ++ ++/** ++ * This function reads a packet from the Rx FIFO into the destination ++ * buffer. To read SETUP data use dwc_otg_read_setup_packet. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dest Destination buffer for the packet. ++ * @param bytes Number of bytes to copy to the destination. ++ */ ++void dwc_otg_read_packet(dwc_otg_core_if_t * core_if, ++ uint8_t * dest, uint16_t bytes) ++{ ++ int i; ++ int word_count = (bytes + 3) / 4; ++ ++ volatile uint32_t *fifo = core_if->data_fifo[0]; ++ uint32_t *data_buff = (uint32_t *) dest; ++ ++ /** ++ * @todo Account for the case where _dest is not dword aligned. This ++ * requires reading data from the FIFO into a uint32_t temp buffer, ++ * then moving it into the data buffer. ++ */ ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, ++ core_if, dest, bytes); ++ ++ for (i = 0; i < word_count; i++, data_buff++) { ++ *data_buff = DWC_READ_REG32(fifo); ++ } ++ ++ return; ++} ++ ++/** ++ * This functions reads the device registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINTF("Device Global Registers\n"); ++ addr = &core_if->dev_if->dev_global_regs->dcfg; ++ DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dctl; ++ DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dsts; ++ DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->diepmsk; ++ DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->doepmsk; ++ DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->daint; ++ DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->daintmsk; ++ DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dtknqr1; ++ DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ if (core_if->hwcfg2.b.dev_token_q_depth > 6) { ++ addr = &core_if->dev_if->dev_global_regs->dtknqr2; ++ DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ addr = &core_if->dev_if->dev_global_regs->dvbusdis; ++ DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ ++ addr = &core_if->dev_if->dev_global_regs->dvbuspulse; ++ DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ ++ addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; ++ DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ ++ if (core_if->hwcfg2.b.dev_token_q_depth > 22) { ++ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; ++ DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; ++ DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ ++ if (core_if->hwcfg2.b.multi_proc_int) { ++ ++ addr = &core_if->dev_if->dev_global_regs->deachint; ++ DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->deachintmsk; ++ DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ addr = ++ &core_if->dev_if-> ++ dev_global_regs->diepeachintmsk[i]; ++ DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", ++ i, (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ addr = ++ &core_if->dev_if-> ++ dev_global_regs->doepeachintmsk[i]; ++ DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", ++ i, (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ } ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_PRINTF("Device IN EP %d Registers\n", i); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepctl; ++ DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepint; ++ DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz; ++ DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepdma; ++ DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts; ++ DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepdmab; ++ DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ ); ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ DWC_PRINTF("Device OUT EP %d Registers\n", i); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepctl; ++ DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepint; ++ DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz; ++ DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepdma; ++ DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */ ++ addr = &core_if->dev_if->out_ep_regs[i]->doepdmab; ++ DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ } ++} ++ ++/** ++ * This functions reads the SPRAM and prints its content ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if) ++{ ++ volatile uint8_t *addr, *start_addr, *end_addr; ++ ++ DWC_PRINTF("SPRAM Data:\n"); ++ start_addr = (void *)core_if->core_global_regs; ++ DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr); ++ start_addr += 0x00028000; ++ end_addr = (void *)core_if->core_global_regs; ++ end_addr += 0x000280e0; ++ ++ for (addr = start_addr; addr < end_addr; addr += 16) { ++ DWC_PRINTF ++ ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", ++ (unsigned long)addr, addr[0], addr[1], addr[2], addr[3], ++ addr[4], addr[5], addr[6], addr[7], addr[8], addr[9], ++ addr[10], addr[11], addr[12], addr[13], addr[14], addr[15] ++ ); ++ } ++ ++ return; ++} ++ ++/** ++ * This function reads the host registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINTF("Host Global Registers\n"); ++ addr = &core_if->host_if->host_global_regs->hcfg; ++ DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->hfir; ++ DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->hfnum; ++ DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->hptxsts; ++ DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->haint; ++ DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->haintmsk; ++ DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ if (core_if->dma_desc_enable) { ++ addr = &core_if->host_if->host_global_regs->hflbaddr; ++ DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ addr = core_if->host_if->hprt0; ++ DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ ++ for (i = 0; i < core_if->core_params->host_channels; i++) { ++ DWC_PRINTF("Host Channel %d Specific Registers\n", i); ++ addr = &core_if->host_if->hc_regs[i]->hcchar; ++ DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcsplt; ++ DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcint; ++ DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcintmsk; ++ DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hctsiz; ++ DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcdma; ++ DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ if (core_if->dma_desc_enable) { ++ addr = &core_if->host_if->hc_regs[i]->hcdmab; ++ DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ } ++ return; ++} ++ ++/** ++ * This function reads the core global registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i, ep_num; ++ volatile uint32_t *addr; ++ char *txfsiz; ++ ++ DWC_PRINTF("Core Global Registers\n"); ++ addr = &core_if->core_global_regs->gotgctl; ++ DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gotgint; ++ DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gahbcfg; ++ DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gusbcfg; ++ DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->grstctl; ++ DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gintsts; ++ DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gintmsk; ++ DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->grxstsr; ++ DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->grxfsiz; ++ DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gnptxfsiz; ++ DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gnptxsts; ++ DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gi2cctl; ++ DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gpvndctl; ++ DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ggpio; ++ DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->guid; ++ DWC_PRINTF("GUID @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gsnpsid; ++ DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg1; ++ DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg2; ++ DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg3; ++ DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg4; ++ DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->glpmcfg; ++ DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gpwrdn; ++ DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gdfifocfg; ++ DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->adpctl; ++ DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ dwc_otg_adp_read_reg(core_if)); ++ addr = &core_if->core_global_regs->hptxfsiz; ++ DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep; ++ txfsiz = "DPTXFSIZ"; ++ } else { ++ ep_num = core_if->hwcfg4.b.num_in_eps; ++ txfsiz = "DIENPTXF"; ++ } ++ for (i = 0; i < ep_num; i++) { ++ addr = &core_if->core_global_regs->dtxfsiz[i]; ++ DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1, ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ addr = core_if->pcgcctl; ++ DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++} ++ ++/** ++ * Flush a Tx FIFO. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param num Tx FIFO to flush. ++ */ ++void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num); ++ ++ greset.b.txfflsh = 1; ++ greset.b.txfnum = num; ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); ++ ++ do { ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", ++ __func__, greset.d32, ++ DWC_READ_REG32(&global_regs->gnptxsts)); ++ break; ++ } ++ dwc_udelay(1); ++ } while (greset.b.txfflsh == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_udelay(1); ++} ++ ++/** ++ * Flush Rx FIFO. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__); ++ /* ++ * ++ */ ++ greset.b.rxfflsh = 1; ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); ++ ++ do { ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, ++ greset.d32); ++ break; ++ } ++ dwc_udelay(1); ++ } while (greset.b.rxfflsh == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_udelay(1); ++} ++ ++/** ++ * Do core a soft reset of the core. Be careful with this because it ++ * resets all the internal state machines of the core. ++ */ ++void dwc_otg_core_reset(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); ++ /* Wait for AHB master IDLE state. */ ++ do { ++ dwc_udelay(10); ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); ++ if (++count > 100000) { ++ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, ++ greset.d32); ++ return; ++ } ++ } ++ while (greset.b.ahbidle == 0); ++ ++ /* Core Soft Reset */ ++ count = 0; ++ greset.b.csftrst = 1; ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); ++ do { ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", ++ __func__, greset.d32); ++ break; ++ } ++ dwc_udelay(1); ++ } ++ while (greset.b.csftrst == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_mdelay(100); ++} ++ ++uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); ++} ++ ++uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); ++} ++ ++/** ++ * Register HCD callbacks. The callbacks are used to start and stop ++ * the HCD for interrupt processing. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param cb the HCD callback structure. ++ * @param p pointer to be passed to callback function (usb_hcd*). ++ */ ++void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if, ++ dwc_otg_cil_callbacks_t * cb, void *p) ++{ ++ core_if->hcd_cb = cb; ++ cb->p = p; ++} ++ ++/** ++ * Register PCD callbacks. The callbacks are used to start and stop ++ * the PCD for interrupt processing. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param cb the PCD callback structure. ++ * @param p pointer to be passed to callback function (pcd*). ++ */ ++void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if, ++ dwc_otg_cil_callbacks_t * cb, void *p) ++{ ++ core_if->pcd_cb = cb; ++ cb->p = p; ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function writes isoc data per 1 (micro)frame into tx fifo ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ uint32_t len = 0; ++ uint32_t dwords; ++ ++ ep->xfer_len = ep->data_per_frame; ++ ep->xfer_count = 0; ++ ++ ep_regs = core_if->dev_if->in_ep_regs[ep->num]; ++ ++ len = ep->xfer_len - ep->xfer_count; ++ ++ if (len > ep->maxpacket) { ++ len = ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, ep, 0); ++ ++ len = ep->xfer_len - ep->xfer_count; ++ if (len > ep->maxpacket) { ++ len = ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num, ++ txstatus.d32); ++ } ++} ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ ep->xfer_len = ep->data_per_frame; ++ ep->xfer_count = 0; ++ ep->xfer_buff = ep->cur_pkt_addr; ++ ep->dma_addr = ep->cur_pkt_dma_addr; ++ ++ if (ep->is_in) { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->xfer_len; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ deptsiz.b.mc = deptsiz.b.pktcnt; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ DWC_WRITE_REG32(& ++ (core_if->dev_if->in_ep_regs[ep->num]-> ++ diepdma), (uint32_t) ep->dma_addr); ++ } ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz, deptsiz.d32); ++ ++ if (core_if->dma_enable) { ++ DWC_WRITE_REG32(& ++ (core_if->dev_if-> ++ out_ep_regs[ep->num]->doepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ } ++ ++ /** Enable endpoint, clear nak */ ++ ++ depctl.d32 = 0; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ep->next_frame = dsts.b.soffn + ep->bInterval; ++ ++ if (ep->next_frame & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } else { ++ ep->next_frame += ep->bInterval; ++ ++ if (ep->next_frame & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ DWC_MODIFY_REG32(addr, 0, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); ++ ++ if (ep->is_in && core_if->dma_enable == 0) { ++ write_isoc_frame_data(core_if, ep); ++ } ++ ++} ++#endif /* DWC_EN_ISOC */ ++ ++static void dwc_otg_set_uninitialized(int32_t * p, int size) ++{ ++ int i; ++ for (i = 0; i < size; i++) { ++ p[i] = -1; ++ } ++} ++ ++static int dwc_otg_param_initialized(int32_t val) ++{ ++ return val != -1; ++} ++ ++static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params)); ++ if (!core_if->core_params) { ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_otg_set_uninitialized((int32_t *) core_if->core_params, ++ sizeof(*core_if->core_params) / ++ sizeof(int32_t)); ++ DWC_PRINTF("Setting default values for core params\n"); ++ dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default); ++ dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default); ++ dwc_otg_set_param_dma_desc_enable(core_if, ++ dwc_param_dma_desc_enable_default); ++ dwc_otg_set_param_opt(core_if, dwc_param_opt_default); ++ dwc_otg_set_param_dma_burst_size(core_if, ++ dwc_param_dma_burst_size_default); ++ dwc_otg_set_param_host_support_fs_ls_low_power(core_if, ++ dwc_param_host_support_fs_ls_low_power_default); ++ dwc_otg_set_param_enable_dynamic_fifo(core_if, ++ dwc_param_enable_dynamic_fifo_default); ++ dwc_otg_set_param_data_fifo_size(core_if, ++ dwc_param_data_fifo_size_default); ++ dwc_otg_set_param_dev_rx_fifo_size(core_if, ++ dwc_param_dev_rx_fifo_size_default); ++ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, ++ dwc_param_dev_nperio_tx_fifo_size_default); ++ dwc_otg_set_param_host_rx_fifo_size(core_if, ++ dwc_param_host_rx_fifo_size_default); ++ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, ++ dwc_param_host_nperio_tx_fifo_size_default); ++ dwc_otg_set_param_host_perio_tx_fifo_size(core_if, ++ dwc_param_host_perio_tx_fifo_size_default); ++ dwc_otg_set_param_max_transfer_size(core_if, ++ dwc_param_max_transfer_size_default); ++ dwc_otg_set_param_max_packet_count(core_if, ++ dwc_param_max_packet_count_default); ++ dwc_otg_set_param_host_channels(core_if, ++ dwc_param_host_channels_default); ++ dwc_otg_set_param_dev_endpoints(core_if, ++ dwc_param_dev_endpoints_default); ++ dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default); ++ dwc_otg_set_param_speed(core_if, dwc_param_speed_default); ++ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, ++ dwc_param_host_ls_low_power_phy_clk_default); ++ dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default); ++ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, ++ dwc_param_phy_ulpi_ext_vbus_default); ++ dwc_otg_set_param_phy_utmi_width(core_if, ++ dwc_param_phy_utmi_width_default); ++ dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default); ++ dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default); ++ dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default); ++ dwc_otg_set_param_en_multiple_tx_fifo(core_if, ++ dwc_param_en_multiple_tx_fifo_default); ++ for (i = 0; i < 15; i++) { ++ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, ++ dwc_param_dev_perio_tx_fifo_size_default, ++ i); ++ } ++ ++ for (i = 0; i < 15; i++) { ++ dwc_otg_set_param_dev_tx_fifo_size(core_if, ++ dwc_param_dev_tx_fifo_size_default, ++ i); ++ } ++ dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default); ++ dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default); ++ dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default); ++ dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default); ++ dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default); ++ dwc_otg_set_param_tx_thr_length(core_if, ++ dwc_param_tx_thr_length_default); ++ dwc_otg_set_param_rx_thr_length(core_if, ++ dwc_param_rx_thr_length_default); ++ dwc_otg_set_param_ahb_thr_ratio(core_if, ++ dwc_param_ahb_thr_ratio_default); ++ dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default); ++ dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default); ++ dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default); ++ dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default); ++ dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default); ++ dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default); ++ dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default); ++ DWC_PRINTF("Finished setting default values for core params\n"); ++ ++ return 0; ++} ++ ++uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->dma_enable; ++} ++ ++/* Checks if the parameter is outside of its valid range of values */ ++#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \ ++ (((_param_) < (_low_)) || \ ++ ((_param_) > (_high_))) ++ ++/* Parameter access functions */ ++int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int valid; ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { ++ DWC_WARN("Wrong value for otg_cap parameter\n"); ++ DWC_WARN("otg_cap parameter must be 0,1 or 2\n"); ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ valid = 1; ++ switch (val) { ++ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: ++ if (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ valid = 0; ++ break; ++ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: ++ if ((core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { ++ valid = 0; ++ } ++ break; ++ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: ++ /* always valid */ ++ break; ++ } ++ if (!valid) { ++ if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) { ++ DWC_ERROR ++ ("%d invalid for otg_cap paremter. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (((core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? ++ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->otg_cap = val; ++out: ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->otg_cap; ++} ++ ++int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for opt parameter\n"); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->opt = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->opt; ++} ++ ++int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for dma enable\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) { ++ DWC_ERROR ++ ("%d invalid for dma_enable paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dma_enable = val; ++ if (val == 0) { ++ dwc_otg_set_param_dma_desc_enable(core_if, 0); ++ } ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_enable; ++} ++ ++int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for dma_enable\n"); ++ DWC_WARN("dma_desc_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) ++ && ((dwc_otg_get_param_dma_enable(core_if) == 0) ++ || (core_if->hwcfg4.b.desc_dma == 0))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dma_desc_enable)) { ++ DWC_ERROR ++ ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->dma_desc_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_desc_enable; ++} ++ ++int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for host_support_fs_low_power\n"); ++ DWC_WARN("host_support_fs_low_power must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->host_support_fs_ls_low_power = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * ++ core_if) ++{ ++ return core_if->core_params->host_support_fs_ls_low_power; ++} ++ ++int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for enable_dynamic_fifo\n"); ++ DWC_WARN("enable_dynamic_fifo must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->enable_dynamic_fifo)) { ++ DWC_ERROR ++ ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->enable_dynamic_fifo = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->enable_dynamic_fifo; ++} ++ ++int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 32, 32768)) { ++ DWC_WARN("Wrong value for data_fifo_size\n"); ++ DWC_WARN("data_fifo_size must be 32-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > core_if->hwcfg3.b.dfifo_depth) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->data_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for data_fifo_size parameter. Check HW configuration.\n", ++ val); ++ } ++ val = core_if->hwcfg3.b.dfifo_depth; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->data_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->data_fifo_size; ++} ++ ++int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for dev_rx_fifo_size\n"); ++ DWC_WARN("dev_rx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) { ++ if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) { ++ DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val); ++ } ++ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_rx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_rx_fifo_size; ++} ++ ++int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for dev_nperio_tx_fifo\n"); ++ DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_nperio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> ++ 16); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_nperio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_nperio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_rx_fifo_size\n"); ++ DWC_WARN("host_rx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_rx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_rx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_rx_fifo_size = val; ++ return retval; ++ ++} ++ ++int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_rx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n"); ++ DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_nperio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> ++ 16); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_nperio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_nperio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_perio_tx_fifo_size\n"); ++ DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > ((core_if->hptxfsiz.d32) >> 16)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_perio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = (core_if->hptxfsiz.d32) >> 16; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_perio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_perio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) { ++ DWC_WARN("Wrong value for max_transfer_size\n"); ++ DWC_WARN("max_transfer_size must be 2047-524288\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->max_transfer_size)) { ++ DWC_ERROR ++ ("%d invalid for max_transfer_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) - ++ 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->max_transfer_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->max_transfer_size; ++} ++ ++int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 15, 511)) { ++ DWC_WARN("Wrong value for max_packet_count\n"); ++ DWC_WARN("max_packet_count must be 15-511\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->max_packet_count)) { ++ DWC_ERROR ++ ("%d invalid for max_packet_count. Check HW configuration.\n", ++ val); ++ } ++ val = ++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->max_packet_count = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->max_packet_count; ++} ++ ++int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 1, 16)) { ++ DWC_WARN("Wrong value for host_channels\n"); ++ DWC_WARN("host_channels must be 1-16\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (core_if->hwcfg2.b.num_host_chan + 1)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_channels)) { ++ DWC_ERROR ++ ("%d invalid for host_channels. Check HW configurations.\n", ++ val); ++ } ++ val = (core_if->hwcfg2.b.num_host_chan + 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_channels = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_channels; ++} ++ ++int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 1, 15)) { ++ DWC_WARN("Wrong value for dev_endpoints\n"); ++ DWC_WARN("dev_endpoints must be 1-15\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (core_if->hwcfg2.b.num_dev_ep)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_endpoints)) { ++ DWC_ERROR ++ ("%d invalid for dev_endpoints. Check HW configurations.\n", ++ val); ++ } ++ val = core_if->hwcfg2.b.num_dev_ep; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_endpoints = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_endpoints; ++} ++ ++int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { ++ DWC_WARN("Wrong value for phy_type\n"); ++ DWC_WARN("phy_type must be 0,1 or 2\n"); ++ return -DWC_E_INVALID; ++ } ++#ifndef NO_FS_PHY_HW_CHECKS ++ if ((val == DWC_PHY_TYPE_PARAM_UTMI) && ++ ((core_if->hwcfg2.b.hs_phy_type == 1) || ++ (core_if->hwcfg2.b.hs_phy_type == 3))) { ++ valid = 1; ++ } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) && ++ ((core_if->hwcfg2.b.hs_phy_type == 2) || ++ (core_if->hwcfg2.b.hs_phy_type == 3))) { ++ valid = 1; ++ } else if ((val == DWC_PHY_TYPE_PARAM_FS) && ++ (core_if->hwcfg2.b.fs_phy_type == 1)) { ++ valid = 1; ++ } ++ if (!valid) { ++ if (dwc_otg_param_initialized(core_if->core_params->phy_type)) { ++ DWC_ERROR ++ ("%d invalid for phy_type. Check HW configurations.\n", ++ val); ++ } ++ if (core_if->hwcfg2.b.hs_phy_type) { ++ if ((core_if->hwcfg2.b.hs_phy_type == 3) || ++ (core_if->hwcfg2.b.hs_phy_type == 1)) { ++ val = DWC_PHY_TYPE_PARAM_UTMI; ++ } else { ++ val = DWC_PHY_TYPE_PARAM_ULPI; ++ } ++ } ++ retval = -DWC_E_INVALID; ++ } ++#endif ++ core_if->core_params->phy_type = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_type; ++} ++ ++int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for speed parameter\n"); ++ DWC_WARN("max_speed parameter must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ if ((val == 0) ++ && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) { ++ if (dwc_otg_param_initialized(core_if->core_params->speed)) { ++ DWC_ERROR ++ ("%d invalid for speed paremter. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_otg_get_param_phy_type(core_if) == ++ DWC_PHY_TYPE_PARAM_FS ? 1 : 0); ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->speed = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->speed; ++} ++ ++int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN ++ ("Wrong value for host_ls_low_power_phy_clk parameter\n"); ++ DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) ++ && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_ls_low_power_phy_clk)) { ++ DWC_ERROR ++ ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_otg_get_param_phy_type(core_if) == ++ DWC_PHY_TYPE_PARAM_FS) ? ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_ls_low_power_phy_clk = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_ls_low_power_phy_clk; ++} ++ ++int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for phy_ulpi_ddr\n"); ++ DWC_WARN("phy_upli_ddr must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_ulpi_ddr = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_ulpi_ddr; ++} ++ ++int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n"); ++ DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_ulpi_ext_vbus = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_ulpi_ext_vbus; ++} ++ ++int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) { ++ DWC_WARN("Wrong valaue for phy_utmi_width\n"); ++ DWC_WARN("phy_utmi_width must be 8 or 16\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_utmi_width = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_utmi_width; ++} ++ ++int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for ulpi_fs_ls\n"); ++ DWC_WARN("ulpi_fs_ls must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->ulpi_fs_ls = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ulpi_fs_ls; ++} ++ ++int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for ts_dline\n"); ++ DWC_WARN("ts_dline must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->ts_dline = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ts_dline; ++} ++ ++int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for i2c_enable\n"); ++ DWC_WARN("i2c_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++#ifndef NO_FS_PHY_HW_CHECK ++ if (val == 1 && core_if->hwcfg3.b.i2c == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) { ++ DWC_ERROR ++ ("%d invalid for i2c_enable. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++#endif ++ ++ core_if->core_params->i2c_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->i2c_enable; ++} ++ ++int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val, int fifo_num) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 4, 768)) { ++ DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n"); ++ DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > ++ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) { ++ DWC_ERROR ++ ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", ++ val, fifo_num); ++ } ++ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num])); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num) ++{ ++ return core_if->core_params->dev_perio_tx_fifo_size[fifo_num]; ++} ++ ++int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n"); ++ DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->en_multiple_tx_fifo)) { ++ DWC_ERROR ++ ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->en_multiple_tx_fifo = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->en_multiple_tx_fifo; ++} ++ ++int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val, ++ int fifo_num) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 4, 768)) { ++ DWC_WARN("Wrong value for dev_tx_fifo_size\n"); ++ DWC_WARN("dev_tx_fifo_size must be 4-768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > ++ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_tx_fifo_size[fifo_num])) { ++ DWC_ERROR ++ ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n", ++ val, fifo_num); ++ } ++ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num])); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_tx_fifo_size[fifo_num] = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num) ++{ ++ return core_if->core_params->dev_tx_fifo_size[fifo_num]; ++} ++ ++int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 7)) { ++ DWC_WARN("Wrong value for thr_ctl\n"); ++ DWC_WARN("thr_ctl must be 0-7\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val != 0) && ++ (!dwc_otg_get_param_dma_enable(core_if) || ++ !core_if->hwcfg4.b.ded_fifo_en)) { ++ if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) { ++ DWC_ERROR ++ ("%d invalid for parameter thr_ctl. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->thr_ctl = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->thr_ctl; ++} ++ ++int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for lpm_enable\n"); ++ DWC_WARN("lpm_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val && !core_if->hwcfg3.b.otg_lpm_en) { ++ if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter lpm_enable. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->lpm_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->lpm_enable; ++} ++ ++int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 128)) { ++ DWC_WARN("Wrong valaue for tx_thr_length\n"); ++ DWC_WARN("tx_thr_length must be 8 - 128\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->tx_thr_length = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->tx_thr_length; ++} ++ ++int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 128)) { ++ DWC_WARN("Wrong valaue for rx_thr_length\n"); ++ DWC_WARN("rx_thr_length must be 8 - 128\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->rx_thr_length = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->rx_thr_length; ++} ++ ++int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 1, 1) && ++ DWC_OTG_PARAM_TEST(val, 4, 4) && ++ DWC_OTG_PARAM_TEST(val, 8, 8) && ++ DWC_OTG_PARAM_TEST(val, 16, 16) && ++ DWC_OTG_PARAM_TEST(val, 32, 32) && ++ DWC_OTG_PARAM_TEST(val, 64, 64) && ++ DWC_OTG_PARAM_TEST(val, 128, 128) && ++ DWC_OTG_PARAM_TEST(val, 256, 256)) { ++ DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->dma_burst_size = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_burst_size; ++} ++ ++int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) { ++ if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter pti_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->pti_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->pti_enable; ++} ++ ++int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter mpi_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->mpi_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->mpi_enable; ++} ++ ++int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->hwcfg3.b.adp_supp == 0)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->adp_supp_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter adp_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->adp_supp_enable = val; ++ /*Set OTG version 2.0 in case of enabling ADP*/ ++ if (val) ++ dwc_otg_set_param_otg_ver(core_if, 1); ++ ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->adp_supp_enable; ++} ++ ++int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val); ++ DWC_WARN("ic_usb_cap must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) { ++ DWC_ERROR ++ ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->ic_usb_cap = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ic_usb_cap; ++} ++ ++int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 3)) { ++ DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val); ++ DWC_WARN("ahb_thr_ratio must be 0 - 3\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val ++ && (core_if->snpsid < OTG_CORE_REV_2_81a ++ || !dwc_otg_get_param_thr_ctl(core_if))) { ++ valid = 0; ++ } else if (val ++ && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < ++ 4)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->ahb_thr_ratio)) { ++ DWC_ERROR ++ ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ ++ core_if->core_params->ahb_thr_ratio = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ahb_thr_ratio; ++} ++ ++int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ hwcfg4_data_t hwcfg4 = {.d32 = 0 }; ++ hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4); ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 3)) { ++ DWC_WARN("`%d' invalid for parameter `power_down'\n", val); ++ DWC_WARN("power_down must be 0 - 2\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) { ++ valid = 0; ++ } ++ if ((val == 3) ++ && ((core_if->snpsid < OTG_CORE_REV_3_00a) ++ || (hwcfg4.b.xhiber == 0))) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->power_down)) { ++ DWC_ERROR ++ ("%d invalid for parameter power_down. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->power_down = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->power_down; ++} ++ ++int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val); ++ DWC_WARN("reload_ctl must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) { ++ DWC_ERROR("%d invalid for parameter reload_ctl." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->reload_ctl = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->reload_ctl; ++} ++ ++int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val); ++ DWC_WARN("dev_out_nak must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) || ++ !(core_if->core_params->dma_desc_enable))) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) { ++ DWC_ERROR("%d invalid for parameter dev_out_nak." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->dev_out_nak = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_out_nak; ++} ++ ++int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val); ++ DWC_WARN("cont_on_bna must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) || ++ !(core_if->core_params->dma_desc_enable))) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) { ++ DWC_ERROR("%d invalid for parameter cont_on_bna." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->cont_on_bna = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->cont_on_bna; ++} ++ ++int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val); ++ DWC_WARN("ahb_single must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) { ++ DWC_ERROR("%d invalid for parameter ahb_single." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->ahb_single = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ahb_single; ++} ++ ++int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val); ++ DWC_WARN ++ ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->otg_ver = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->otg_ver; ++} ++ ++uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if) ++{ ++ gotgctl_data_t otgctl; ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ return otgctl.b.hstnegscs; ++} ++ ++uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if) ++{ ++ gotgctl_data_t otgctl; ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ return otgctl.b.sesreqscs; ++} ++ ++void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ if(core_if->otg_ver == 0) { ++ gotgctl_data_t otgctl; ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ otgctl.b.hnpreq = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32); ++ } else { ++ core_if->otg_sts = val; ++ } ++} ++ ++uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->snpsid; ++} ++ ++uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ return gintsts.b.curmode; ++} ++ ++uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ return usbcfg.b.hnpcap; ++} ++ ++void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.b.hnpcap = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); ++} ++ ++uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ return usbcfg.b.srpcap; ++} ++ ++void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.b.srpcap = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); ++} ++ ++uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if) ++{ ++ dcfg_data_t dcfg; ++ /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */ ++ ++ dcfg.d32 = -1; //GRAYG ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if); ++ if (NULL == core_if) ++ DWC_ERROR("reg request with NULL core_if\n"); ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__, ++ core_if, core_if->dev_if); ++ if (NULL == core_if->dev_if) ++ DWC_ERROR("reg request with NULL dev_if\n"); ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->" ++ "dev_global_regs(%p)\n", __func__, ++ core_if, core_if->dev_if, ++ core_if->dev_if->dev_global_regs); ++ if (NULL == core_if->dev_if->dev_global_regs) ++ DWC_ERROR("reg request with NULL dev_global_regs\n"); ++ else { ++ DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->" ++ "dev_global_regs(%p)->dcfg = %p\n", __func__, ++ core_if, core_if->dev_if, ++ core_if->dev_if->dev_global_regs, ++ &core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ } ++ return dcfg.b.devspd; ++} ++ ++void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dcfg_data_t dcfg; ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.devspd = val; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++} ++ ++uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ return hprt0.b.prtconnsts; ++} ++ ++uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ return dsts.b.enumspd; ++} ++ ++uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ return hprt0.b.prtpwr; ++ ++} ++ ++uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->hibernation_suspend; ++} ++ ++void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = val; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++} ++ ++uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ return hprt0.b.prtsusp; ++ ++} ++ ++void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = val; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++} ++ ++uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if) ++{ ++ hfir_data_t hfir; ++ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ return hfir.b.frint; ++ ++} ++ ++void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hfir_data_t hfir; ++ uint32_t fram_int; ++ fram_int = calc_frame_interval(core_if); ++ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ if (!core_if->core_params->reload_ctl) { ++ DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is" ++ "not set to 1.\nShould load driver with reload_ctl=1" ++ " module parameter\n"); ++ return; ++ } ++ switch (fram_int) { ++ case 3750: ++ if ((val < 3350) || (val > 4150)) { ++ DWC_WARN("HFIR interval for HS core and 30 MHz" ++ "clock freq should be from 3350 to 4150\n"); ++ return; ++ } ++ break; ++ case 30000: ++ if ((val < 26820) || (val > 33180)) { ++ DWC_WARN("HFIR interval for FS/LS core and 30 MHz" ++ "clock freq should be from 26820 to 33180\n"); ++ return; ++ } ++ break; ++ case 6000: ++ if ((val < 5360) || (val > 6640)) { ++ DWC_WARN("HFIR interval for HS core and 48 MHz" ++ "clock freq should be from 5360 to 6640\n"); ++ return; ++ } ++ break; ++ case 48000: ++ if ((val < 42912) || (val > 53088)) { ++ DWC_WARN("HFIR interval for FS/LS core and 48 MHz" ++ "clock freq should be from 42912 to 53088\n"); ++ return; ++ } ++ break; ++ case 7500: ++ if ((val < 6700) || (val > 8300)) { ++ DWC_WARN("HFIR interval for HS core and 60 MHz" ++ "clock freq should be from 6700 to 8300\n"); ++ return; ++ } ++ break; ++ case 60000: ++ if ((val < 53640) || (val > 65536)) { ++ DWC_WARN("HFIR interval for FS/LS core and 60 MHz" ++ "clock freq should be from 53640 to 65536\n"); ++ return; ++ } ++ break; ++ default: ++ DWC_WARN("Unknown frame interval\n"); ++ return; ++ break; ++ ++ } ++ hfir.b.frint = val; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32); ++} ++ ++uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if) ++{ ++ hcfg_data_t hcfg; ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ return hcfg.b.modechtimen; ++ ++} ++ ++void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hcfg_data_t hcfg; ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ hcfg.b.modechtimen = val; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = val; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++} ++ ++uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if) ++{ ++ dctl_data_t dctl; ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ return dctl.b.rmtwkupsig; ++} ++ ++uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ ++ DWC_ASSERT(! ++ ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts), ++ "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n", ++ core_if->lx_state, lpmcfg.b.prt_sleep_sts); ++ ++ return lpmcfg.b.prt_sleep_sts; ++} ++ ++uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.rem_wkup_en; ++} ++ ++uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.appl_resp; ++} ++ ++void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.appl_resp = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.hsic_connect; ++} ++ ++void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.hsic_connect = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.inv_sel_hsic; ++ ++} ++ ++void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.inv_sel_hsic = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++} ++ ++void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val); ++} ++ ++uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++} ++ ++void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val); ++} ++ ++uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++} ++ ++void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val); ++} ++ ++uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz); ++} ++ ++void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val); ++} ++ ++uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl); ++} ++ ++void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val); ++} ++ ++uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->ggpio); ++} ++ ++void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val); ++} ++ ++uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(core_if->host_if->hprt0); ++ ++} ++ ++void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(core_if->host_if->hprt0, val); ++} ++ ++uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->guid); ++} ++ ++void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->guid, val); ++} ++ ++uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++} ++ ++uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if) ++{ ++ return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103); ++} ++ ++/** ++ * Start the SRP timer to detect when the SRP does not complete within ++ * 6 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if) ++{ ++ core_if->srp_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ ); ++} ++ ++void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl); ++ gotgctl_data_t mem; ++ gotgctl_data_t val; ++ ++ val.d32 = DWC_READ_REG32(addr); ++ if (val.b.sesreq) { ++ DWC_ERROR("Session Request Already active!\n"); ++ return; ++ } ++ ++ DWC_INFO("Session Request Initated\n"); //NOTICE ++ mem.d32 = DWC_READ_REG32(addr); ++ mem.b.sesreq = 1; ++ DWC_WRITE_REG32(addr, mem.d32); ++ ++ /* Start the SRP timer */ ++ dwc_otg_pcd_start_srp_timer(core_if); ++ return; ++} +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.h +@@ -0,0 +1,1464 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $ ++ * $Revision: #123 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_CIL_H__) ++#define __DWC_CIL_H__ ++ ++#include "dwc_list.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_regs.h" ++ ++#include "dwc_otg_core_if.h" ++#include "dwc_otg_adp.h" ++ ++/** ++ * @file ++ * This file contains the interface to the Core Interface Layer. ++ */ ++ ++#ifdef DWC_UTE_CFI ++ ++#define MAX_DMA_DESCS_PER_EP 256 ++ ++/** ++ * Enumeration for the data buffer mode ++ */ ++typedef enum _data_buffer_mode { ++ BM_STANDARD = 0, /* data buffer is in normal mode */ ++ BM_SG = 1, /* data buffer uses the scatter/gather mode */ ++ BM_CONCAT = 2, /* data buffer uses the concatenation mode */ ++ BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */ ++ BM_ALIGN = 4 /* data buffer is in buffer alignment mode */ ++} data_buffer_mode_e; ++#endif //DWC_UTE_CFI ++ ++/** Macros defined for DWC OTG HW Release version */ ++ ++#define OTG_CORE_REV_2_60a 0x4F54260A ++#define OTG_CORE_REV_2_71a 0x4F54271A ++#define OTG_CORE_REV_2_72a 0x4F54272A ++#define OTG_CORE_REV_2_80a 0x4F54280A ++#define OTG_CORE_REV_2_81a 0x4F54281A ++#define OTG_CORE_REV_2_90a 0x4F54290A ++#define OTG_CORE_REV_2_91a 0x4F54291A ++#define OTG_CORE_REV_2_92a 0x4F54292A ++#define OTG_CORE_REV_2_93a 0x4F54293A ++#define OTG_CORE_REV_2_94a 0x4F54294A ++#define OTG_CORE_REV_3_00a 0x4F54300A ++ ++/** ++ * Information for each ISOC packet. ++ */ ++typedef struct iso_pkt_info { ++ uint32_t offset; ++ uint32_t length; ++ int32_t status; ++} iso_pkt_info_t; ++ ++/** ++ * The dwc_ep structure represents the state of a single ++ * endpoint when acting in device mode. It contains the data items ++ * needed for an endpoint to be activated and transfer packets. ++ */ ++typedef struct dwc_ep { ++ /** EP number used for register address lookup */ ++ uint8_t num; ++ /** EP direction 0 = OUT */ ++ unsigned is_in:1; ++ /** EP active. */ ++ unsigned active:1; ++ ++ /** ++ * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic ++ * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/ ++ unsigned tx_fifo_num:4; ++ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ ++ unsigned type:2; ++#define DWC_OTG_EP_TYPE_CONTROL 0 ++#define DWC_OTG_EP_TYPE_ISOC 1 ++#define DWC_OTG_EP_TYPE_BULK 2 ++#define DWC_OTG_EP_TYPE_INTR 3 ++ ++ /** DATA start PID for INTR and BULK EP */ ++ unsigned data_pid_start:1; ++ /** Frame (even/odd) for ISOC EP */ ++ unsigned even_odd_frame:1; ++ /** Max Packet bytes */ ++ unsigned maxpacket:11; ++ ++ /** Max Transfer size */ ++ uint32_t maxxfer; ++ ++ /** @name Transfer state */ ++ /** @{ */ ++ ++ /** ++ * Pointer to the beginning of the transfer buffer -- do not modify ++ * during transfer. ++ */ ++ ++ dwc_dma_t dma_addr; ++ ++ dwc_dma_t dma_desc_addr; ++ dwc_otg_dev_dma_desc_t *desc_addr; ++ ++ uint8_t *start_xfer_buff; ++ /** pointer to the transfer buffer */ ++ uint8_t *xfer_buff; ++ /** Number of bytes to transfer */ ++ unsigned xfer_len:19; ++ /** Number of bytes transferred. */ ++ unsigned xfer_count:19; ++ /** Sent ZLP */ ++ unsigned sent_zlp:1; ++ /** Total len for control transfer */ ++ unsigned total_len:19; ++ ++ /** stall clear flag */ ++ unsigned stall_clear_flag:1; ++ ++ /** SETUP pkt cnt rollover flag for EP0 out*/ ++ unsigned stp_rollover; ++ ++#ifdef DWC_UTE_CFI ++ /* The buffer mode */ ++ data_buffer_mode_e buff_mode; ++ ++ /* The chain of DMA descriptors. ++ * MAX_DMA_DESCS_PER_EP will be allocated for each active EP. ++ */ ++ dwc_otg_dma_desc_t *descs; ++ ++ /* The DMA address of the descriptors chain start */ ++ dma_addr_t descs_dma_addr; ++ /** This variable stores the length of the last enqueued request */ ++ uint32_t cfi_req_len; ++#endif //DWC_UTE_CFI ++ ++/** Max DMA Descriptor count for any EP */ ++#define MAX_DMA_DESC_CNT 256 ++ /** Allocated DMA Desc count */ ++ uint32_t desc_cnt; ++ ++ /** bInterval */ ++ uint32_t bInterval; ++ /** Next frame num to setup next ISOC transfer */ ++ uint32_t frame_num; ++ /** Indicates SOF number overrun in DSTS */ ++ uint8_t frm_overrun; ++ ++#ifdef DWC_UTE_PER_IO ++ /** Next frame num for which will be setup DMA Desc */ ++ uint32_t xiso_frame_num; ++ /** bInterval */ ++ uint32_t xiso_bInterval; ++ /** Count of currently active transfers - shall be either 0 or 1 */ ++ int xiso_active_xfers; ++ int xiso_queued_xfers; ++#endif ++#ifdef DWC_EN_ISOC ++ /** ++ * Variables specific for ISOC EPs ++ * ++ */ ++ /** DMA addresses of ISOC buffers */ ++ dwc_dma_t dma_addr0; ++ dwc_dma_t dma_addr1; ++ ++ dwc_dma_t iso_dma_desc_addr; ++ dwc_otg_dev_dma_desc_t *iso_desc_addr; ++ ++ /** pointer to the transfer buffers */ ++ uint8_t *xfer_buff0; ++ uint8_t *xfer_buff1; ++ ++ /** number of ISOC Buffer is processing */ ++ uint32_t proc_buf_num; ++ /** Interval of ISOC Buffer processing */ ++ uint32_t buf_proc_intrvl; ++ /** Data size for regular frame */ ++ uint32_t data_per_frame; ++ ++ /* todo - pattern data support is to be implemented in the future */ ++ /** Data size for pattern frame */ ++ uint32_t data_pattern_frame; ++ /** Frame number of pattern data */ ++ uint32_t sync_frame; ++ ++ /** bInterval */ ++ uint32_t bInterval; ++ /** ISO Packet number per frame */ ++ uint32_t pkt_per_frm; ++ /** Next frame num for which will be setup DMA Desc */ ++ uint32_t next_frame; ++ /** Number of packets per buffer processing */ ++ uint32_t pkt_cnt; ++ /** Info for all isoc packets */ ++ iso_pkt_info_t *pkt_info; ++ /** current pkt number */ ++ uint32_t cur_pkt; ++ /** current pkt number */ ++ uint8_t *cur_pkt_addr; ++ /** current pkt number */ ++ uint32_t cur_pkt_dma_addr; ++#endif /* DWC_EN_ISOC */ ++ ++/** @} */ ++} dwc_ep_t; ++ ++/* ++ * Reasons for halting a host channel. ++ */ ++typedef enum dwc_otg_halt_status { ++ DWC_OTG_HC_XFER_NO_HALT_STATUS, ++ DWC_OTG_HC_XFER_COMPLETE, ++ DWC_OTG_HC_XFER_URB_COMPLETE, ++ DWC_OTG_HC_XFER_ACK, ++ DWC_OTG_HC_XFER_NAK, ++ DWC_OTG_HC_XFER_NYET, ++ DWC_OTG_HC_XFER_STALL, ++ DWC_OTG_HC_XFER_XACT_ERR, ++ DWC_OTG_HC_XFER_FRAME_OVERRUN, ++ DWC_OTG_HC_XFER_BABBLE_ERR, ++ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, ++ DWC_OTG_HC_XFER_AHB_ERR, ++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, ++ DWC_OTG_HC_XFER_URB_DEQUEUE ++} dwc_otg_halt_status_e; ++ ++/** ++ * Host channel descriptor. This structure represents the state of a single ++ * host channel when acting in host mode. It contains the data items needed to ++ * transfer packets to an endpoint via a host channel. ++ */ ++typedef struct dwc_hc { ++ /** Host channel number used for register address lookup */ ++ uint8_t hc_num; ++ ++ /** Device to access */ ++ unsigned dev_addr:7; ++ ++ /** EP to access */ ++ unsigned ep_num:4; ++ ++ /** EP direction. 0: OUT, 1: IN */ ++ unsigned ep_is_in:1; ++ ++ /** ++ * EP speed. ++ * One of the following values: ++ * - DWC_OTG_EP_SPEED_LOW ++ * - DWC_OTG_EP_SPEED_FULL ++ * - DWC_OTG_EP_SPEED_HIGH ++ */ ++ unsigned speed:2; ++#define DWC_OTG_EP_SPEED_LOW 0 ++#define DWC_OTG_EP_SPEED_FULL 1 ++#define DWC_OTG_EP_SPEED_HIGH 2 ++ ++ /** ++ * Endpoint type. ++ * One of the following values: ++ * - DWC_OTG_EP_TYPE_CONTROL: 0 ++ * - DWC_OTG_EP_TYPE_ISOC: 1 ++ * - DWC_OTG_EP_TYPE_BULK: 2 ++ * - DWC_OTG_EP_TYPE_INTR: 3 ++ */ ++ unsigned ep_type:2; ++ ++ /** Max packet size in bytes */ ++ unsigned max_packet:11; ++ ++ /** ++ * PID for initial transaction. ++ * 0: DATA0,
++ * 1: DATA2,
++ * 2: DATA1,
++ * 3: MDATA (non-Control EP), ++ * SETUP (Control EP) ++ */ ++ unsigned data_pid_start:2; ++#define DWC_OTG_HC_PID_DATA0 0 ++#define DWC_OTG_HC_PID_DATA2 1 ++#define DWC_OTG_HC_PID_DATA1 2 ++#define DWC_OTG_HC_PID_MDATA 3 ++#define DWC_OTG_HC_PID_SETUP 3 ++ ++ /** Number of periodic transactions per (micro)frame */ ++ unsigned multi_count:2; ++ ++ /** @name Transfer State */ ++ /** @{ */ ++ ++ /** Pointer to the current transfer buffer position. */ ++ uint8_t *xfer_buff; ++ /** ++ * In Buffer DMA mode this buffer will be used ++ * if xfer_buff is not DWORD aligned. ++ */ ++ dwc_dma_t align_buff; ++ /** Total number of bytes to transfer. */ ++ uint32_t xfer_len; ++ /** Number of bytes transferred so far. */ ++ uint32_t xfer_count; ++ /** Packet count at start of transfer.*/ ++ uint16_t start_pkt_count; ++ ++ /** ++ * Flag to indicate whether the transfer has been started. Set to 1 if ++ * it has been started, 0 otherwise. ++ */ ++ uint8_t xfer_started; ++ ++ /** ++ * Set to 1 to indicate that a PING request should be issued on this ++ * channel. If 0, process normally. ++ */ ++ uint8_t do_ping; ++ ++ /** ++ * Set to 1 to indicate that the error count for this transaction is ++ * non-zero. Set to 0 if the error count is 0. ++ */ ++ uint8_t error_state; ++ ++ /** ++ * Set to 1 to indicate that this channel should be halted the next ++ * time a request is queued for the channel. This is necessary in ++ * slave mode if no request queue space is available when an attempt ++ * is made to halt the channel. ++ */ ++ uint8_t halt_on_queue; ++ ++ /** ++ * Set to 1 if the host channel has been halted, but the core is not ++ * finished flushing queued requests. Otherwise 0. ++ */ ++ uint8_t halt_pending; ++ ++ /** ++ * Reason for halting the host channel. ++ */ ++ dwc_otg_halt_status_e halt_status; ++ ++ /* ++ * Split settings for the host channel ++ */ ++ uint8_t do_split; /**< Enable split for the channel */ ++ uint8_t complete_split; /**< Enable complete split */ ++ uint8_t hub_addr; /**< Address of high speed hub */ ++ ++ uint8_t port_addr; /**< Port of the low/full speed device */ ++ /** Split transaction position ++ * One of the following values: ++ * - DWC_HCSPLIT_XACTPOS_MID ++ * - DWC_HCSPLIT_XACTPOS_BEGIN ++ * - DWC_HCSPLIT_XACTPOS_END ++ * - DWC_HCSPLIT_XACTPOS_ALL */ ++ uint8_t xact_pos; ++ ++ /** Set when the host channel does a short read. */ ++ uint8_t short_read; ++ ++ /** ++ * Number of requests issued for this channel since it was assigned to ++ * the current transfer (not counting PINGs). ++ */ ++ uint8_t requests; ++ ++ /** ++ * Queue Head for the transfer being processed by this channel. ++ */ ++ struct dwc_otg_qh *qh; ++ ++ /** @} */ ++ ++ /** Entry in list of host channels. */ ++ DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry; ++ ++ /** @name Descriptor DMA support */ ++ /** @{ */ ++ ++ /** Number of Transfer Descriptors */ ++ uint16_t ntd; ++ ++ /** Descriptor List DMA address */ ++ dwc_dma_t desc_list_addr; ++ ++ /** Scheduling micro-frame bitmap. */ ++ uint8_t schinfo; ++ ++ /** @} */ ++} dwc_hc_t; ++ ++/** ++ * The following parameters may be specified when starting the module. These ++ * parameters define how the DWC_otg controller should be configured. ++ */ ++typedef struct dwc_otg_core_params { ++ int32_t opt; ++ ++ /** ++ * Specifies the OTG capabilities. The driver will automatically ++ * detect the value for this parameter if none is specified. ++ * 0 - HNP and SRP capable (default) ++ * 1 - SRP Only capable ++ * 2 - No HNP/SRP capable ++ */ ++ int32_t otg_cap; ++ ++ /** ++ * Specifies whether to use slave or DMA mode for accessing the data ++ * FIFOs. The driver will automatically detect the value for this ++ * parameter if none is specified. ++ * 0 - Slave ++ * 1 - DMA (default, if available) ++ */ ++ int32_t dma_enable; ++ ++ /** ++ * When DMA mode is enabled specifies whether to use address DMA or DMA ++ * Descriptor mode for accessing the data FIFOs in device mode. The driver ++ * will automatically detect the value for this if none is specified. ++ * 0 - address DMA ++ * 1 - DMA Descriptor(default, if available) ++ */ ++ int32_t dma_desc_enable; ++ /** The DMA Burst size (applicable only for External DMA ++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++ */ ++ int32_t dma_burst_size; /* Translate this to GAHBCFG values */ ++ ++ /** ++ * Specifies the maximum speed of operation in host and device mode. ++ * The actual speed depends on the speed of the attached device and ++ * the value of phy_type. The actual speed depends on the speed of the ++ * attached device. ++ * 0 - High Speed (default) ++ * 1 - Full Speed ++ */ ++ int32_t speed; ++ /** Specifies whether low power mode is supported when attached ++ * to a Full Speed or Low Speed device in host mode. ++ * 0 - Don't support low power mode (default) ++ * 1 - Support low power mode ++ */ ++ int32_t host_support_fs_ls_low_power; ++ ++ /** Specifies the PHY clock rate in low power mode when connected to a ++ * Low Speed device in host mode. This parameter is applicable only if ++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS ++ * then defaults to 6 MHZ otherwise 48 MHZ. ++ * ++ * 0 - 48 MHz ++ * 1 - 6 MHz ++ */ ++ int32_t host_ls_low_power_phy_clk; ++ ++ /** ++ * 0 - Use cC FIFO size parameters ++ * 1 - Allow dynamic FIFO sizing (default) ++ */ ++ int32_t enable_dynamic_fifo; ++ ++ /** Total number of 4-byte words in the data FIFO memory. This ++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic ++ * Tx FIFOs. ++ * 32 to 32768 (default 8192) ++ * Note: The total FIFO memory depth in the FPGA configuration is 8192. ++ */ ++ int32_t data_fifo_size; ++ ++ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1064) ++ */ ++ int32_t dev_rx_fifo_size; ++ ++ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode ++ * when dynamic FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t dev_nperio_tx_fifo_size; ++ ++ /** Number of 4-byte words in each of the periodic Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ ++ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_rx_fifo_size; ++ ++ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode ++ * when Dynamic FIFO sizing is enabled in the core. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_nperio_tx_fifo_size; ++ ++ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_perio_tx_fifo_size; ++ ++ /** The maximum transfer size supported in bytes. ++ * 2047 to 65,535 (default 65,535) ++ */ ++ int32_t max_transfer_size; ++ ++ /** The maximum number of packets in a transfer. ++ * 15 to 511 (default 511) ++ */ ++ int32_t max_packet_count; ++ ++ /** The number of host channel registers to use. ++ * 1 to 16 (default 12) ++ * Note: The FPGA configuration supports a maximum of 12 host channels. ++ */ ++ int32_t host_channels; ++ ++ /** The number of endpoints in addition to EP0 available for device ++ * mode operations. ++ * 1 to 15 (default 6 IN and OUT) ++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT ++ * endpoints in addition to EP0. ++ */ ++ int32_t dev_endpoints; ++ ++ /** ++ * Specifies the type of PHY interface to use. By default, the driver ++ * will automatically detect the phy_type. ++ * ++ * 0 - Full Speed PHY ++ * 1 - UTMI+ (default) ++ * 2 - ULPI ++ */ ++ int32_t phy_type; ++ ++ /** ++ * Specifies the UTMI+ Data Width. This parameter is ++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI ++ * PHY_TYPE, this parameter indicates the data width between ++ * the MAC and the ULPI Wrapper.) Also, this parameter is ++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set ++ * to "8 and 16 bits", meaning that the core has been ++ * configured to work at either data path width. ++ * ++ * 8 or 16 bits (default 16) ++ */ ++ int32_t phy_utmi_width; ++ ++ /** ++ * Specifies whether the ULPI operates at double or single ++ * data rate. This parameter is only applicable if PHY_TYPE is ++ * ULPI. ++ * ++ * 0 - single data rate ULPI interface with 8 bit wide data ++ * bus (default) ++ * 1 - double data rate ULPI interface with 4 bit wide data ++ * bus ++ */ ++ int32_t phy_ulpi_ddr; ++ ++ /** ++ * Specifies whether to use the internal or external supply to ++ * drive the vbus with a ULPI phy. ++ */ ++ int32_t phy_ulpi_ext_vbus; ++ ++ /** ++ * Specifies whether to use the I2Cinterface for full speed PHY. This ++ * parameter is only applicable if PHY_TYPE is FS. ++ * 0 - No (default) ++ * 1 - Yes ++ */ ++ int32_t i2c_enable; ++ ++ int32_t ulpi_fs_ls; ++ ++ int32_t ts_dline; ++ ++ /** ++ * Specifies whether dedicated transmit FIFOs are ++ * enabled for non periodic IN endpoints in device mode ++ * 0 - No ++ * 1 - Yes ++ */ ++ int32_t en_multiple_tx_fifo; ++ ++ /** Number of 4-byte words in each of the Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; ++ ++ /** Thresholding enable flag- ++ * bit 0 - enable non-ISO Tx thresholding ++ * bit 1 - enable ISO Tx thresholding ++ * bit 2 - enable Rx thresholding ++ */ ++ uint32_t thr_ctl; ++ ++ /** Thresholding length for Tx ++ * FIFOs in 32 bit DWORDs ++ */ ++ uint32_t tx_thr_length; ++ ++ /** Thresholding length for Rx ++ * FIFOs in 32 bit DWORDs ++ */ ++ uint32_t rx_thr_length; ++ ++ /** ++ * Specifies whether LPM (Link Power Management) support is enabled ++ */ ++ int32_t lpm_enable; ++ ++ /** Per Transfer Interrupt ++ * mode enable flag ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t pti_enable; ++ ++ /** Multi Processor Interrupt ++ * mode enable flag ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t mpi_enable; ++ ++ /** IS_USB Capability ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t ic_usb_cap; ++ ++ /** AHB Threshold Ratio ++ * 2'b00 AHB Threshold = MAC Threshold ++ * 2'b01 AHB Threshold = 1/2 MAC Threshold ++ * 2'b10 AHB Threshold = 1/4 MAC Threshold ++ * 2'b11 AHB Threshold = 1/8 MAC Threshold ++ */ ++ int32_t ahb_thr_ratio; ++ ++ /** ADP Support ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t adp_supp_enable; ++ ++ /** HFIR Reload Control ++ * 0 - The HFIR cannot be reloaded dynamically. ++ * 1 - Allow dynamic reloading of the HFIR register during runtime. ++ */ ++ int32_t reload_ctl; ++ ++ /** DCFG: Enable device Out NAK ++ * 0 - The core does not set NAK after Bulk Out transfer complete. ++ * 1 - The core sets NAK after Bulk OUT transfer complete. ++ */ ++ int32_t dev_out_nak; ++ ++ /** DCFG: Enable Continue on BNA ++ * After receiving BNA interrupt the core disables the endpoint,when the ++ * endpoint is re-enabled by the application the core starts processing ++ * 0 - from the DOEPDMA descriptor ++ * 1 - from the descriptor which received the BNA. ++ */ ++ int32_t cont_on_bna; ++ ++ /** GAHBCFG: AHB Single Support ++ * This bit when programmed supports SINGLE transfers for remainder ++ * data in a transfer for DMA mode of operation. ++ * 0 - in this case the remainder data will be sent using INCR burst size. ++ * 1 - in this case the remainder data will be sent using SINGLE burst size. ++ */ ++ int32_t ahb_single; ++ ++ /** Core Power down mode ++ * 0 - No Power Down is enabled ++ * 1 - Reserved ++ * 2 - Complete Power Down (Hibernation) ++ */ ++ int32_t power_down; ++ ++ /** OTG revision supported ++ * 0 - OTG 1.3 revision ++ * 1 - OTG 2.0 revision ++ */ ++ int32_t otg_ver; ++ ++} dwc_otg_core_params_t; ++ ++#ifdef DEBUG ++struct dwc_otg_core_if; ++typedef struct hc_xfer_info { ++ struct dwc_otg_core_if *core_if; ++ dwc_hc_t *hc; ++} hc_xfer_info_t; ++#endif ++ ++typedef struct ep_xfer_info { ++ struct dwc_otg_core_if *core_if; ++ dwc_ep_t *ep; ++ uint8_t state; ++} ep_xfer_info_t; ++/* ++ * Device States ++ */ ++typedef enum dwc_otg_lx_state { ++ /** On state */ ++ DWC_OTG_L0, ++ /** LPM sleep state*/ ++ DWC_OTG_L1, ++ /** USB suspend state*/ ++ DWC_OTG_L2, ++ /** Off state*/ ++ DWC_OTG_L3 ++} dwc_otg_lx_state_e; ++ ++struct dwc_otg_global_regs_backup { ++ uint32_t gotgctl_local; ++ uint32_t gintmsk_local; ++ uint32_t gahbcfg_local; ++ uint32_t gusbcfg_local; ++ uint32_t grxfsiz_local; ++ uint32_t gnptxfsiz_local; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ uint32_t glpmcfg_local; ++#endif ++ uint32_t gi2cctl_local; ++ uint32_t hptxfsiz_local; ++ uint32_t pcgcctl_local; ++ uint32_t gdfifocfg_local; ++ uint32_t dtxfsiz_local[MAX_EPS_CHANNELS]; ++ uint32_t gpwrdn_local; ++ uint32_t xhib_pcgcctl; ++ uint32_t xhib_gpwrdn; ++}; ++ ++struct dwc_otg_host_regs_backup { ++ uint32_t hcfg_local; ++ uint32_t haintmsk_local; ++ uint32_t hcintmsk_local[MAX_EPS_CHANNELS]; ++ uint32_t hprt0_local; ++ uint32_t hfir_local; ++}; ++ ++struct dwc_otg_dev_regs_backup { ++ uint32_t dcfg; ++ uint32_t dctl; ++ uint32_t daintmsk; ++ uint32_t diepmsk; ++ uint32_t doepmsk; ++ uint32_t diepctl[MAX_EPS_CHANNELS]; ++ uint32_t dieptsiz[MAX_EPS_CHANNELS]; ++ uint32_t diepdma[MAX_EPS_CHANNELS]; ++}; ++/** ++ * The dwc_otg_core_if structure contains information needed to manage ++ * the DWC_otg controller acting in either host or device mode. It ++ * represents the programming view of the controller as a whole. ++ */ ++struct dwc_otg_core_if { ++ /** Parameters that define how the core should be configured.*/ ++ dwc_otg_core_params_t *core_params; ++ ++ /** Core Global registers starting at offset 000h. */ ++ dwc_otg_core_global_regs_t *core_global_regs; ++ ++ /** Device-specific information */ ++ dwc_otg_dev_if_t *dev_if; ++ /** Host-specific information */ ++ dwc_otg_host_if_t *host_if; ++ ++ /** Value from SNPSID register */ ++ uint32_t snpsid; ++ ++ /* ++ * Set to 1 if the core PHY interface bits in USBCFG have been ++ * initialized. ++ */ ++ uint8_t phy_init_done; ++ ++ /* ++ * SRP Success flag, set by srp success interrupt in FS I2C mode ++ */ ++ uint8_t srp_success; ++ uint8_t srp_timer_started; ++ /** Timer for SRP. If it expires before SRP is successful ++ * clear the SRP. */ ++ dwc_timer_t *srp_timer; ++ ++#ifdef DWC_DEV_SRPCAP ++ /* This timer is needed to power on the hibernated host core if SRP is not ++ * initiated on connected SRP capable device for limited period of time ++ */ ++ uint8_t pwron_timer_started; ++ dwc_timer_t *pwron_timer; ++#endif ++ /* Common configuration information */ ++ /** Power and Clock Gating Control Register */ ++ volatile uint32_t *pcgcctl; ++#define DWC_OTG_PCGCCTL_OFFSET 0xE00 ++ ++ /** Push/pop addresses for endpoints or host channels.*/ ++ uint32_t *data_fifo[MAX_EPS_CHANNELS]; ++#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 ++#define DWC_OTG_DATA_FIFO_SIZE 0x1000 ++ ++ /** Total RAM for FIFOs (Bytes) */ ++ uint16_t total_fifo_size; ++ /** Size of Rx FIFO (Bytes) */ ++ uint16_t rx_fifo_size; ++ /** Size of Non-periodic Tx FIFO (Bytes) */ ++ uint16_t nperio_tx_fifo_size; ++ ++ /** 1 if DMA is enabled, 0 otherwise. */ ++ uint8_t dma_enable; ++ ++ /** 1 if DMA descriptor is enabled, 0 otherwise. */ ++ uint8_t dma_desc_enable; ++ ++ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */ ++ uint8_t pti_enh_enable; ++ ++ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */ ++ uint8_t multiproc_int_enable; ++ ++ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ ++ uint8_t en_multiple_tx_fifo; ++ ++ /** Set to 1 if multiple packets of a high-bandwidth transfer is in ++ * process of being queued */ ++ uint8_t queuing_high_bandwidth; ++ ++ /** Hardware Configuration -- stored here for convenience.*/ ++ hwcfg1_data_t hwcfg1; ++ hwcfg2_data_t hwcfg2; ++ hwcfg3_data_t hwcfg3; ++ hwcfg4_data_t hwcfg4; ++ fifosize_data_t hptxfsiz; ++ ++ /** Host and Device Configuration -- stored here for convenience.*/ ++ hcfg_data_t hcfg; ++ dcfg_data_t dcfg; ++ ++ /** The operational State, during transations ++ * (a_host>>a_peripherial and b_device=>b_host) this may not ++ * match the core but allows the software to determine ++ * transitions. ++ */ ++ uint8_t op_state; ++ ++ /** ++ * Set to 1 if the HCD needs to be restarted on a session request ++ * interrupt. This is required if no connector ID status change has ++ * occurred since the HCD was last disconnected. ++ */ ++ uint8_t restart_hcd_on_session_req; ++ ++ /** HCD callbacks */ ++ /** A-Device is a_host */ ++#define A_HOST (1) ++ /** A-Device is a_suspend */ ++#define A_SUSPEND (2) ++ /** A-Device is a_peripherial */ ++#define A_PERIPHERAL (3) ++ /** B-Device is operating as a Peripheral. */ ++#define B_PERIPHERAL (4) ++ /** B-Device is operating as a Host. */ ++#define B_HOST (5) ++ ++ /** HCD callbacks */ ++ struct dwc_otg_cil_callbacks *hcd_cb; ++ /** PCD callbacks */ ++ struct dwc_otg_cil_callbacks *pcd_cb; ++ ++ /** Device mode Periodic Tx FIFO Mask */ ++ uint32_t p_tx_msk; ++ /** Device mode Periodic Tx FIFO Mask */ ++ uint32_t tx_msk; ++ ++ /** Workqueue object used for handling several interrupts */ ++ dwc_workq_t *wq_otg; ++ ++ /** Timer object used for handling "Wakeup Detected" Interrupt */ ++ dwc_timer_t *wkp_timer; ++ /** This arrays used for debug purposes for DEV OUT NAK enhancement */ ++ uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS]; ++ ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS]; ++ dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS]; ++#ifdef DEBUG ++ uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; ++ ++ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; ++ dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS]; ++ ++ uint32_t hfnum_7_samples; ++ uint64_t hfnum_7_frrem_accum; ++ uint32_t hfnum_0_samples; ++ uint64_t hfnum_0_frrem_accum; ++ uint32_t hfnum_other_samples; ++ uint64_t hfnum_other_frrem_accum; ++#endif ++ ++#ifdef DWC_UTE_CFI ++ uint16_t pwron_rxfsiz; ++ uint16_t pwron_gnptxfsiz; ++ uint16_t pwron_txfsiz[15]; ++ ++ uint16_t init_rxfsiz; ++ uint16_t init_gnptxfsiz; ++ uint16_t init_txfsiz[15]; ++#endif ++ ++ /** Lx state of device */ ++ dwc_otg_lx_state_e lx_state; ++ ++ /** Saved Core Global registers */ ++ struct dwc_otg_global_regs_backup *gr_backup; ++ /** Saved Host registers */ ++ struct dwc_otg_host_regs_backup *hr_backup; ++ /** Saved Device registers */ ++ struct dwc_otg_dev_regs_backup *dr_backup; ++ ++ /** Power Down Enable */ ++ uint32_t power_down; ++ ++ /** ADP support Enable */ ++ uint32_t adp_enable; ++ ++ /** ADP structure object */ ++ dwc_otg_adp_t adp; ++ ++ /** hibernation/suspend flag */ ++ int hibernation_suspend; ++ ++ /** Device mode extended hibernation flag */ ++ int xhib; ++ ++ /** OTG revision supported */ ++ uint32_t otg_ver; ++ ++ /** OTG status flag used for HNP polling */ ++ uint8_t otg_sts; ++ ++ /** Pointer to either hcd->lock or pcd->lock */ ++ dwc_spinlock_t *lock; ++ ++ /** Start predict NextEP based on Learning Queue if equal 1, ++ * also used as counter of disabled NP IN EP's */ ++ uint8_t start_predict; ++ ++ /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and ++ * active, 0xff otherwise */ ++ uint8_t nextep_seq[MAX_EPS_CHANNELS]; ++ ++ /** Index of fisrt EP in nextep_seq array which should be re-enabled **/ ++ uint8_t first_in_nextep_seq; ++ ++ /** Frame number while entering to ISR - needed for ISOCs **/ ++ uint32_t frame_num; ++ ++}; ++ ++#ifdef DEBUG ++/* ++ * This function is called when transfer is timed out. ++ */ ++extern void hc_xfer_timeout(void *ptr); ++#endif ++ ++/* ++ * This function is called when transfer is timed out on endpoint. ++ */ ++extern void ep_xfer_timeout(void *ptr); ++ ++/* ++ * The following functions are functions for works ++ * using during handling some interrupts ++ */ ++extern void w_conn_id_status_change(void *p); ++ ++extern void w_wakeup_detected(void *p); ++ ++/** Saves global register values into system memory. */ ++extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if); ++/** Saves device register values into system memory. */ ++extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if); ++/** Saves host register values into system memory. */ ++extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if); ++/** Restore global register values. */ ++extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if); ++/** Restore host register values. */ ++extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset); ++/** Restore device register values. */ ++extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, ++ int rem_wakeup); ++extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if); ++extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, ++ int is_host); ++ ++extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int restore_mode, int reset); ++extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset); ++ ++/* ++ * The following functions support initialization of the CIL driver component ++ * and the DWC_otg controller. ++ */ ++extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if); ++ ++/** @name Device CIL Functions ++ * The following functions support managing the DWC_otg controller in device ++ * mode. ++ */ ++/**@{*/ ++extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if, ++ uint32_t * _dest); ++extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep, int _dma); ++extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if); ++ ++#ifdef DWC_EN_ISOC ++extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep); ++extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep); ++#endif /* DWC_EN_ISOC */ ++/**@}*/ ++ ++/** @name Host CIL Functions ++ * The following functions support managing the DWC_otg controller in host ++ * mode. ++ */ ++/**@{*/ ++extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status); ++extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if); ++ ++extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc); ++ ++extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if); ++ ++/* Macro used to clear one channel interrupt */ ++#define clear_hc_int(_hc_regs_, _intr_) \ ++do { \ ++ hcint_data_t hcint_clear = {.d32 = 0}; \ ++ hcint_clear.b._intr_ = 1; \ ++ DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \ ++} while (0) ++ ++/* ++ * Macro used to disable one channel interrupt. Channel interrupts are ++ * disabled when the channel is halted or released by the interrupt handler. ++ * There is no need to handle further interrupts of that type until the ++ * channel is re-assigned. In fact, subsequent handling may cause crashes ++ * because the channel structures are cleaned up when the channel is released. ++ */ ++#define disable_hc_int(_hc_regs_, _intr_) \ ++do { \ ++ hcintmsk_data_t hcintmsk = {.d32 = 0}; \ ++ hcintmsk.b._intr_ = 1; \ ++ DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \ ++} while (0) ++ ++/** ++ * This function Reads HPRT0 in preparation to modify. It keeps the ++ * WC bits 0 so that if they are read as 1, they won't clear when you ++ * write it back ++ */ ++static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0); ++ hprt0.b.prtena = 0; ++ hprt0.b.prtconndet = 0; ++ hprt0.b.prtenchng = 0; ++ hprt0.b.prtovrcurrchng = 0; ++ return hprt0.d32; ++} ++ ++/**@}*/ ++ ++/** @name Common CIL Functions ++ * The following functions support managing the DWC_otg controller in either ++ * device or host mode. ++ */ ++/**@{*/ ++ ++extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if, ++ uint8_t * dest, uint16_t bytes); ++ ++extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num); ++extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if); ++ ++/** ++ * This function returns the Core Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if) ++{ ++ return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) & ++ DWC_READ_REG32(&core_if->core_global_regs->gintmsk)); ++} ++ ++/** ++ * This function returns the OTG Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if) ++{ ++ return (DWC_READ_REG32(&core_if->core_global_regs->gotgint)); ++} ++ ++/** ++ * This function reads the Device All Endpoints Interrupt register and ++ * returns the IN endpoint interrupt bits. ++ */ ++static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t * ++ core_if) ++{ ++ ++ uint32_t v; ++ ++ if (core_if->multiproc_int_enable) { ++ v = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->deachint) & ++ DWC_READ_REG32(&core_if-> ++ dev_if->dev_global_regs->deachintmsk); ++ } else { ++ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) & ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); ++ } ++ return (v & 0xffff); ++} ++ ++/** ++ * This function reads the Device All Endpoints Interrupt register and ++ * returns the OUT endpoint interrupt bits. ++ */ ++static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t * ++ core_if) ++{ ++ uint32_t v; ++ ++ if (core_if->multiproc_int_enable) { ++ v = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->deachint) & ++ DWC_READ_REG32(&core_if-> ++ dev_if->dev_global_regs->deachintmsk); ++ } else { ++ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) & ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); ++ } ++ ++ return ((v & 0xffff0000) >> 16); ++} ++ ++/** ++ * This function returns the Device IN EP Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ uint32_t v, msk, emp; ++ ++ if (core_if->multiproc_int_enable) { ++ msk = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->diepeachintmsk[ep->num]); ++ emp = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); ++ msk |= ((emp >> ep->num) & 0x1) << 7; ++ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; ++ } else { ++ msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk); ++ emp = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); ++ msk |= ((emp >> ep->num) & 0x1) << 7; ++ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; ++ } ++ ++ return v; ++} ++ ++/** ++ * This function returns the Device OUT EP Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t * ++ _core_if, dwc_ep_t * _ep) ++{ ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ uint32_t v; ++ doepmsk_data_t msk = {.d32 = 0 }; ++ ++ if (_core_if->multiproc_int_enable) { ++ msk.d32 = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->doepeachintmsk[_ep->num]); ++ if (_core_if->pti_enh_enable) { ++ msk.b.pktdrpsts = 1; ++ } ++ v = DWC_READ_REG32(&dev_if-> ++ out_ep_regs[_ep->num]->doepint) & msk.d32; ++ } else { ++ msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk); ++ if (_core_if->pti_enh_enable) { ++ msk.b.pktdrpsts = 1; ++ } ++ v = DWC_READ_REG32(&dev_if-> ++ out_ep_regs[_ep->num]->doepint) & msk.d32; ++ } ++ return v; ++} ++ ++/** ++ * This function returns the Host All Channel Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t * ++ _core_if) ++{ ++ return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint)); ++} ++ ++static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t * ++ _core_if, dwc_hc_t * _hc) ++{ ++ return (DWC_READ_REG32 ++ (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); ++} ++ ++/** ++ * This function returns the mode of the operation, host or device. ++ * ++ * @return 0 - Device Mode, 1 - Host Mode ++ */ ++static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1); ++} ++ ++/**@}*/ ++ ++/** ++ * DWC_otg CIL callback structure. This structure allows the HCD and ++ * PCD to register functions used for starting and stopping the PCD ++ * and HCD for role change on for a DRD. ++ */ ++typedef struct dwc_otg_cil_callbacks { ++ /** Start function for role change */ ++ int (*start) (void *_p); ++ /** Stop Function for role change */ ++ int (*stop) (void *_p); ++ /** Disconnect Function for role change */ ++ int (*disconnect) (void *_p); ++ /** Resume/Remote wakeup Function */ ++ int (*resume_wakeup) (void *_p); ++ /** Suspend function */ ++ int (*suspend) (void *_p); ++ /** Session Start (SRP) */ ++ int (*session_start) (void *_p); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ /** Sleep (switch to L0 state) */ ++ int (*sleep) (void *_p); ++#endif ++ /** Pointer passed to start() and stop() */ ++ void *p; ++} dwc_otg_cil_callbacks_t; ++ ++extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if, ++ dwc_otg_cil_callbacks_t * _cb, ++ void *_p); ++extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if, ++ dwc_otg_cil_callbacks_t * _cb, ++ void *_p); ++ ++void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if); ++ ++////////////////////////////////////////////////////////////////////// ++/** Start the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->start) { ++ core_if->hcd_cb->start(core_if->hcd_cb->p); ++ } ++} ++ ++/** Stop the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->stop) { ++ core_if->hcd_cb->stop(core_if->hcd_cb->p); ++ } ++} ++ ++/** Disconnect the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { ++ core_if->hcd_cb->disconnect(core_if->hcd_cb->p); ++ } ++} ++ ++/** Inform the HCD the a New Session has begun. Helper function for ++ * using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->session_start) { ++ core_if->hcd_cb->session_start(core_if->hcd_cb->p); ++ } ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * Inform the HCD about LPM sleep. ++ * Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->sleep) { ++ core_if->hcd_cb->sleep(core_if->hcd_cb->p); ++ } ++} ++#endif ++ ++/** Resume the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) { ++ core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p); ++ } ++} ++ ++/** Start the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->start) { ++ core_if->pcd_cb->start(core_if->pcd_cb->p); ++ } ++} ++ ++/** Stop the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->stop) { ++ core_if->pcd_cb->stop(core_if->pcd_cb->p); ++ } ++} ++ ++/** Suspend the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->suspend) { ++ core_if->pcd_cb->suspend(core_if->pcd_cb->p); ++ } ++} ++ ++/** Resume the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++} ++ ++////////////////////////////////////////////////////////////////////// ++ ++#endif +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c +@@ -0,0 +1,1594 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $ ++ * $Revision: #32 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The Core Interface Layer provides basic services for accessing and ++ * managing the DWC_otg hardware. These services are used by both the ++ * Host Controller Driver and the Peripheral Controller Driver. ++ * ++ * This file contains the Common Interrupt handlers. ++ */ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_pcd.h" ++#include "dwc_otg_hcd.h" ++ ++#ifdef DEBUG ++inline const char *op_state_str(dwc_otg_core_if_t * core_if) ++{ ++ return (core_if->op_state == A_HOST ? "a_host" : ++ (core_if->op_state == A_SUSPEND ? "a_suspend" : ++ (core_if->op_state == A_PERIPHERAL ? "a_peripheral" : ++ (core_if->op_state == B_PERIPHERAL ? "b_peripheral" : ++ (core_if->op_state == B_HOST ? "b_host" : "unknown"))))); ++} ++#endif ++ ++/** This function will log a debug message ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", ++ dwc_otg_mode(core_if) ? "Host" : "Device"); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.modemismatch = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This function handles the OTG Interrupts. It reads the OTG ++ * Interrupt Register (GOTGINT) to determine what interrupt has ++ * occurred. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gotgint_data_t gotgint; ++ gotgctl_data_t gotgctl; ++ gintmsk_data_t gintmsk; ++ gpwrdn_data_t gpwrdn; ++ ++ gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32, ++ op_state_str(core_if)); ++ ++ if (gotgint.b.sesenddet) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Session End Detected++ (%s)\n", ++ op_state_str(core_if)); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ ++ if (core_if->op_state == B_HOST) { ++ cil_pcd_start(core_if); ++ core_if->op_state = B_PERIPHERAL; ++ } else { ++ /* If not B_HOST and Device HNP still set. HNP ++ * Did not succeed!*/ ++ if (gotgctl.b.devhnpen) { ++ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); ++ __DWC_ERROR("Device Not Connected/Responding!\n"); ++ } ++ ++ /* If Session End Detected the B-Cable has ++ * been disconnected. */ ++ /* Reset PCD and Gadget driver to a ++ * clean state. */ ++ core_if->lx_state = DWC_OTG_L0; ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ ++ if (core_if->adp_enable) { ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_sense_start(core_if); ++ } ++ } ++ ++ gotgctl.d32 = 0; ++ gotgctl.b.devhnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ } ++ if (gotgint.b.sesreqsucstschng) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Session Reqeust Success Status Change++\n"); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ if (gotgctl.b.sesreqscs) { ++ ++ if ((core_if->core_params->phy_type == ++ DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) { ++ core_if->srp_success = 1; ++ } else { ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_resume(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ /* Clear Session Request */ ++ gotgctl.d32 = 0; ++ gotgctl.b.sesreq = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, ++ gotgctl.d32, 0); ++ } ++ } ++ } ++ if (gotgint.b.hstnegsucstschng) { ++ /* Print statements during the HNP interrupt handling ++ * can cause it to fail.*/ ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ /* WA for 3.00a- HW is not setting cur_mode, even sometimes ++ * this does not help*/ ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) ++ dwc_udelay(100); ++ if (gotgctl.b.hstnegscs) { ++ if (dwc_otg_is_host_mode(core_if)) { ++ core_if->op_state = B_HOST; ++ /* ++ * Need to disable SOF interrupt immediately. ++ * When switching from device to host, the PCD ++ * interrupt handler won't handle the ++ * interrupt if host mode is already set. The ++ * HCD interrupt handler won't get called if ++ * the HCD state is HALT. This means that the ++ * interrupt does not get handled and Linux ++ * complains loudly. ++ */ ++ gintmsk.d32 = 0; ++ gintmsk.b.sofintr = 1; ++ DWC_MODIFY_REG32(&global_regs->gintmsk, ++ gintmsk.d32, 0); ++ /* Call callback function with spin lock released */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = B_HOST; ++ } ++ } else { ++ gotgctl.d32 = 0; ++ gotgctl.b.hnpreq = 1; ++ gotgctl.b.devhnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n"); ++ __DWC_ERROR("Device Not Connected/Responding\n"); ++ } ++ } ++ if (gotgint.b.hstnegdet) { ++ /* The disconnect interrupt is set at the same time as ++ * Host Negotiation Detected. During the mode ++ * switch all interrupts are cleared so the disconnect ++ * interrupt handler will not get executed. ++ */ ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Host Negotiation Detected++ (%s)\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Device")); ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", ++ core_if->op_state); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = A_PERIPHERAL; ++ } else { ++ /* ++ * Need to disable SOF interrupt immediately. When ++ * switching from device to host, the PCD interrupt ++ * handler won't handle the interrupt if host mode is ++ * already set. The HCD interrupt handler won't get ++ * called if the HCD state is HALT. This means that ++ * the interrupt does not get handled and Linux ++ * complains loudly. ++ */ ++ gintmsk.d32 = 0; ++ gintmsk.b.sofintr = 1; ++ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = A_HOST; ++ } ++ } ++ if (gotgint.b.adevtoutchng) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "A-Device Timeout Change++\n"); ++ } ++ if (gotgint.b.debdone) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n"); ++ } ++ ++ /* Clear GOTGINT */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32); ++ ++ return 1; ++} ++ ++void w_conn_id_status_change(void *p) ++{ ++ dwc_otg_core_if_t *core_if = p; ++ uint32_t count = 0; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); ++ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); ++ ++ /* B-Device connector (Device Mode) */ ++ if (gotgctl.b.conidsts) { ++ /* Wait for switch to device mode. */ ++ while (!dwc_otg_is_device_mode(core_if)) { ++ DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Peripheral")); ++ dwc_mdelay(100); ++ if (++count > 10000) ++ break; ++ } ++ DWC_ASSERT(++count < 10000, ++ "Connection id status change timed out"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } else { ++ /* A-Device connector (Host Mode) */ ++ while (!dwc_otg_is_host_mode(core_if)) { ++ DWC_PRINTF("Waiting for Host Mode, Mode=%s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Peripheral")); ++ dwc_mdelay(100); ++ if (++count > 10000) ++ break; ++ } ++ DWC_ASSERT(++count < 10000, ++ "Connection id status change timed out"); ++ core_if->op_state = A_HOST; ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++} ++ ++/** ++ * This function handles the Connector ID Status Change Interrupt. It ++ * reads the OTG Interrupt Register (GOTCTL) to determine whether this ++ * is a Device to Host Mode transition or a Host Mode to Device ++ * Transition. ++ * ++ * This only occurs when the cable is connected/removed from the PHY ++ * connector. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if) ++{ ++ ++ /* ++ * Need to disable SOF interrupt immediately. If switching from device ++ * to host, the PCD interrupt handler won't handle the interrupt if ++ * host mode is already set. The HCD interrupt handler won't get ++ * called if the HCD state is HALT. This means that the interrupt does ++ * not get handled and Linux complains loudly. ++ */ ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ gintsts_data_t gintsts = {.d32 = 0 }; ++ ++ gintmsk.b.sofintr = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ " ++Connector ID Status Change Interrupt++ (%s)\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device")); ++ ++ DWC_SPINUNLOCK(core_if->lock); ++ ++ /* ++ * Need to schedule a work, as there are possible DELAY function calls ++ * Release lock before scheduling workq as it holds spinlock during scheduling ++ */ ++ ++ DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change, ++ core_if, "connection id status change"); ++ DWC_SPINLOCK(core_if->lock); ++ ++ /* Set flag and clear interrupt */ ++ gintsts.b.conidstschng = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that a device is initiating the Session ++ * Request Protocol to request the host to turn on bus power so a new ++ * session can begin. The handler responds by turning on bus power. If ++ * the DWC_otg controller is in low power mode, the handler brings the ++ * controller out of low power mode before turning on bus power. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ ++#ifndef DWC_HOST_ONLY ++ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_PRINTF("SRP: Device mode\n"); ++ } else { ++ hprt0_data_t hprt0; ++ DWC_PRINTF("SRP: Host mode\n"); ++ ++ /* Turn on the port power bit. */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Start the Connection timer. So a message can be displayed ++ * if connect does not occur within 10 seconds. */ ++ cil_hcd_session_start(core_if); ++ } ++#endif ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.sessreqintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++void w_wakeup_detected(void *p) ++{ ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p; ++ /* ++ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms ++ * so that OPT tests pass with all PHYs). ++ */ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++#if 0 ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ /* Restart the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ dwc_udelay(10); ++#endif //0 ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32); ++// dwc_mdelay(70); ++ hprt0.b.prtres = 0; /* Resume */ ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n", ++ DWC_READ_REG32(core_if->host_if->hprt0)); ++ ++ cil_hcd_resume(core_if); ++ ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++} ++ ++/** ++ * This interrupt indicates that the DWC_otg controller has detected a ++ * resume or remote wakeup sequence. If the DWC_otg controller is in ++ * low power mode, the handler must brings the controller out of low ++ * power mode. The controller automatically begins resume ++ * signaling. The handler schedules a time to stop resume signaling. ++ */ ++int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "++Resume and Remote Wakeup Detected Interrupt++\n"); ++ ++ DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs-> ++ dsts)); ++ if (core_if->lx_state == DWC_OTG_L2) { ++#ifdef PARTIAL_POWER_DOWN ++ if (core_if->hwcfg4.b.power_optimiz) { ++ pcgcctl_data_t power = {.d32 = 0 }; ++ ++ power.d32 = DWC_READ_REG32(core_if->pcgcctl); ++ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", ++ power.d32); ++ ++ power.b.stoppclk = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); ++ ++ power.b.pwrclmp = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); ++ ++ power.b.rstpdwnmodule = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); ++ } ++#endif ++ /* Clear the Remote Wakeup Signaling */ ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, dctl.d32, 0); ++ ++ DWC_SPINUNLOCK(core_if->lock); ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++ DWC_SPINLOCK(core_if->lock); ++ } else { ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ } ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++ } else { ++ if (core_if->lx_state != DWC_OTG_L1) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ ++ /* Restart the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71); ++ } else { ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++ } ++ } ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.wkupintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * Device disconnect. ++ */ ++static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if) ++{ ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = { .d32 = 0 }; ++ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps*/ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (gpwrdn_temp.b.idsts) { ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } else { ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * remote wakeup sequence. ++ */ ++static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_ANY, ++ "++Powerdown Remote Wakeup Detected Interrupt++\n"); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (gpwrdn.b.idsts) { // Device Mode ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ dwc_otg_device_hibernation_restore(core_if, 0, 0); ++ } ++ } else { ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ dwc_otg_host_hibernation_restore(core_if, 1, 0); ++ } ++ } ++ return 1; ++} ++ ++static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (core_if->power_down == 2) { ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n"); ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /*Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = core_if->gr_backup->gpwrdn_local; ++ if (gpwrdn.b.dis_vbus == 1) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ } ++ ++ if (gpwrdn_temp.b.idsts) { ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } else { ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ } ++ ++ if (core_if->adp_enable) { ++ uint8_t is_host = 0; ++ DWC_SPINUNLOCK(core_if->lock); ++ /* Change the core_if's lock to hcd/pcd lock depend on mode? */ ++#ifndef DWC_HOST_ONLY ++ if (gpwrdn_temp.b.idsts) ++ core_if->lock = otg_dev->pcd->lock; ++#endif ++#ifndef DWC_DEVICE_ONLY ++ if (!gpwrdn_temp.b.idsts) { ++ core_if->lock = otg_dev->hcd->lock; ++ is_host = 1; ++ } ++#endif ++ DWC_PRINTF("RESTART ADP\n"); ++ if (core_if->adp.probe_enabled) ++ dwc_otg_adp_probe_stop(core_if); ++ if (core_if->adp.sense_enabled) ++ dwc_otg_adp_sense_stop(core_if); ++ if (core_if->adp.sense_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ if (core_if->adp.vbuson_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); ++ core_if->adp.probe_timer_values[0] = -1; ++ core_if->adp.probe_timer_values[1] = -1; ++ core_if->adp.sense_timer_started = 0; ++ core_if->adp.vbuson_timer_started = 0; ++ core_if->adp.probe_counter = 0; ++ core_if->adp.gpwrdn = 0; ++ ++ /* Disable PMU and restart ADP */ ++ gpwrdn_temp.d32 = 0; ++ gpwrdn_temp.b.pmuactv = 1; ++ gpwrdn_temp.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ DWC_PRINTF("Check point 1\n"); ++ dwc_mdelay(110); ++ dwc_otg_adp_start(core_if, is_host); ++ DWC_SPINLOCK(core_if->lock); ++ } ++ ++ ++ return 1; ++} ++ ++static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (core_if->power_down == 2) { ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE || ++ otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) && ++ gpwrdn.b.bsessvld == 0) { ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */ ++ return 1; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /*Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE || ++ otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) { ++ /* ++ * Initiate SRP after initial ADP probe. ++ */ ++ dwc_otg_initiate_srp(core_if); ++ } ++ } ++ ++ return 1; ++} ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * status change either on IDDIG or BSessVld. ++ */ ++static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev) ++{ ++ int retval; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (core_if->power_down == 2) { ++ if (core_if->hibernation_suspend <= 0) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } else ++ gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local; ++ ++ } else { ++ gpwrdn_temp.d32 = core_if->adp.gpwrdn; ++ } ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) { ++ retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev); ++ } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) { ++ retval = dwc_otg_handle_pwrdn_session_change(core_if); ++ } ++ ++ return retval; ++} ++ ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * SRP. ++ */ ++static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++#ifdef DWC_DEV_SRPCAP ++ if (core_if->pwron_timer_started) { ++ core_if->pwron_timer_started = 0; ++ DWC_TIMER_CANCEL(core_if->pwron_timer); ++ } ++#endif ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Programm Disable VBUS to 0 */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /*Initialize the core as Host */ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ ++ return 1; ++} ++ ++/** This interrupt indicates that restore command after Hibernation ++ * was completed by the core. */ ++int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if) ++{ ++ pcgcctl_data_t pcgcctl; ++ DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n"); ++ ++ //TODO De-assert restore signal. 8.a ++ pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl); ++ if (pcgcctl.b.restoremode == 1) { ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ /* ++ * If restore mode is Remote Wakeup, ++ * unmask Remote Wakeup interrupt. ++ */ ++ gintmsk.b.wkupintr = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ 0, gintmsk.d32); ++ } ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that a device has been disconnected from ++ * the root port. ++ */ ++int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"), ++ op_state_str(core_if)); ++ ++/** @todo Consolidate this if statement. */ ++#ifndef DWC_HOST_ONLY ++ if (core_if->op_state == B_HOST) { ++ /* If in device mode Disconnect and stop the HCD, then ++ * start the PCD. */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = B_PERIPHERAL; ++ } else if (dwc_otg_is_device_mode(core_if)) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ if (gotgctl.b.hstsethnpen == 1) { ++ /* Do nothing, if HNP in process the OTG ++ * interrupt "Host Negotiation Detected" ++ * interrupt will do the mode switch. ++ */ ++ } else if (gotgctl.b.devhnpen == 0) { ++ /* If in device mode Disconnect and stop the HCD, then ++ * start the PCD. */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = B_PERIPHERAL; ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n"); ++ } ++ } else { ++ if (core_if->op_state == A_HOST) { ++ /* A-Cable still connected but device disconnected. */ ++ cil_hcd_disconnect(core_if); ++ if (core_if->adp_enable) { ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ cil_hcd_stop(core_if); ++ /* Enable Power Down Logic */ ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_otg_adp_probe_start(core_if); ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ } ++ } ++ } ++ } ++#endif ++ /* Change to L3(OFF) state */ ++ core_if->lx_state = DWC_OTG_L3; ++ ++ gintsts.d32 = 0; ++ gintsts.b.disconnect = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that SUSPEND state has been detected on ++ * the USB. ++ * ++ * For HNP the USB Suspend interrupt signals the change from ++ * "a_peripheral" to "a_host". ++ * ++ * When power management is enabled the core will be put in low power ++ * mode. ++ */ ++int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ gintsts_data_t gintsts; ++ dcfg_data_t dcfg; ++ ++ DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n"); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ /* Check the Device status register to determine if the Suspend ++ * state is active. */ ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); ++ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " ++ "HWCFG4.power Optimize=%d\n", ++ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz); ++ ++#ifdef PARTIAL_POWER_DOWN ++/** @todo Add a module parameter for power management. */ ++ ++ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) { ++ pcgcctl_data_t power = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_CIL, "suspend\n"); ++ ++ power.b.pwrclmp = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); ++ ++ power.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32); ++ ++ power.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32); ++ ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "disconnect?\n"); ++ } ++#endif ++ /* PCD callback for suspend. Release the lock inside of callback function */ ++ cil_pcd_suspend(core_if); ++ if (core_if->power_down == 2) ++ { ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state); ++ DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr); ++ ++ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ ++ /* Change to L2(suspend) state */ ++ core_if->lx_state = DWC_OTG_L2; ++ ++ /* Clear interrupt in gintsts */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ DWC_PRINTF("Start of hibernation completed\n"); ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_dev_regs(core_if); ++ ++ gusbcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gusbcfg); ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ /* Suspend the Phy Clock */ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } else { ++ /* UTMI+ Interface */ ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ } ++ ++ /* Set flag to indicate that we are in hibernation */ ++ core_if->hibernation_suspend = 1; ++ /* Enable interrupts from wake up logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Unmask device mode interrupts in GPWRDN */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ gpwrdn.b.sts_chngint_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Enable Power Down Clamp */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Switch off VDD */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ DWC_PRINTF("Hibernation completed\n"); ++ ++ return 1; ++ } ++ } else if (core_if->power_down == 3) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state); ++ DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr); ++ ++ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) { ++ DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n"); ++ core_if->xhib = 1; ++ ++ /* Clear interrupt in gintsts */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_dev_regs(core_if); ++ ++ /* Wait for 10 PHY clocks */ ++ dwc_udelay(10); ++ ++ /* Program GPIO register while entering to xHib */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1); ++ ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.extnd_hiber_pwrclmp = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.extnd_hiber_switch = 1; ++ core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n"); ++ ++ return 1; ++ } ++ } ++ } else { ++ if (core_if->op_state == A_PERIPHERAL) { ++ DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n"); ++ /* Clear the a_peripheral flag, back to a_host. */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = A_HOST; ++ } ++ } ++ ++ /* Change to L2(suspend) state */ ++ core_if->lx_state = DWC_OTG_L2; ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; ++ ++ dwc_udelay(10); ++ ++ /* Program GPIO register while entering to xHib */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0); ++ ++ pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl; ++ pcgcctl.b.extnd_hiber_pwrclmp = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn; ++ gpwrdn.b.restore = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ restore_lpm_i2c_regs(core_if); ++ ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.b.ess_reg_restored = 0; ++ pcgcctl.b.extnd_hiber_switch = 0; ++ pcgcctl.b.extnd_hiber_pwrclmp = 0; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ ++ gahbcfg.d32 = core_if->gr_backup->gahbcfg_local; ++ gahbcfg.b.glblintrmsk = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ core_if->dr_backup->dcfg); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.d32 |= 0x608; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.b.ess_reg_restored = 1; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ pcgcctl.b.rstpdwnmodule = 1; ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ ++ return 1; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * This function hadles LPM transaction received interrupt. ++ */ ++static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ gintsts_data_t gintsts; ++ ++ if (!core_if->core_params->lpm_enable) { ++ DWC_PRINTF("Unexpected LPM interrupt\n"); ++ } ++ ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32); ++ ++ if (dwc_otg_is_host_mode(core_if)) { ++ cil_hcd_sleep(core_if); ++ } else { ++ lpmcfg.b.hird_thres |= (1 << 4); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ } ++ ++ /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */ ++ dwc_udelay(10); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ /* Save the current state */ ++ core_if->lx_state = DWC_OTG_L1; ++ } ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.lpmtranrcvd = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ ++/** ++ * This function returns the Core Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd) ++{ ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ gintmsk_data_t gintmsk_common = {.d32 = 0 }; ++ gintmsk_common.b.wkupintr = 1; ++ gintmsk_common.b.sessreqintr = 1; ++ gintmsk_common.b.conidstschng = 1; ++ gintmsk_common.b.otgintr = 1; ++ gintmsk_common.b.modemismatch = 1; ++ gintmsk_common.b.disconnect = 1; ++ gintmsk_common.b.usbsuspend = 1; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ gintmsk_common.b.lpmtranrcvd = 1; ++#endif ++ gintmsk_common.b.restoredone = 1; ++ if(dwc_otg_is_device_mode(core_if)) ++ { ++ /** @todo: The port interrupt occurs while in device ++ * mode. Added code to CIL to clear the interrupt for now! ++ */ ++ gintmsk_common.b.portintr = 1; ++ } ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ if(fiq_enable) { ++ local_fiq_disable(); ++ /* Pull in the interrupts that the FIQ has masked */ ++ gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32); ++ gintmsk.d32 |= gintmsk_common.d32; ++ /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */ ++ reenable_gintmsk->d32 = gintmsk.d32; ++ local_fiq_enable(); ++ } ++ ++ gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); ++ ++#ifdef DEBUG ++ /* if any common interrupts set */ ++ if (gintsts.d32 & gintmsk_common.d32) { ++ DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x gintmsk=%08x\n", ++ gintsts.d32, gintmsk.d32); ++ } ++#endif ++ if (!fiq_enable){ ++ if (gahbcfg.b.glblintrmsk) ++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); ++ else ++ return 0; ++ } else { ++ /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface. ++ * Can't trust the global interrupt mask bit in this case. ++ */ ++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); ++ } ++ ++} ++ ++/* MACRO for clearing interupt bits in GPWRDN register */ ++#define CLEAR_GPWRDN_INTR(__core_if,__intr) \ ++do { \ ++ gpwrdn_data_t gpwrdn = {.d32=0}; \ ++ gpwrdn.b.__intr = 1; \ ++ DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \ ++ 0, gpwrdn.d32); \ ++} while (0) ++ ++/** ++ * Common interrupt handler. ++ * ++ * The common interrupts are those that occur in both Host and Device mode. ++ * This handler handles the following interrupts: ++ * - Mode Mismatch Interrupt ++ * - Disconnect Interrupt ++ * - OTG Interrupt ++ * - Connector ID Status Change Interrupt ++ * - Session Request Interrupt. ++ * - Resume / Remote Wakeup Detected Interrupt. ++ * - LPM Transaction Received Interrupt ++ * - ADP Transaction Received Interrupt ++ * ++ */ ++int32_t dwc_otg_handle_common_intr(void *dev) ++{ ++ int retval = 0; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk_reenable = { .d32 = 0 }; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ dwc_otg_device_t *otg_dev = dev; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (dwc_otg_is_device_mode(core_if)) ++ core_if->frame_num = dwc_otg_get_frame_number(core_if); ++ ++ if (core_if->lock) ++ DWC_SPINLOCK(core_if->lock); ++ ++ if (core_if->power_down == 3 && core_if->xhib == 1) { ++ DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n"); ++ retval |= dwc_otg_handle_xhib_exit_intr(core_if); ++ core_if->xhib = 2; ++ if (core_if->lock) ++ DWC_SPINUNLOCK(core_if->lock); ++ ++ return retval; ++ } ++ ++ if (core_if->hibernation_suspend <= 0) { ++ /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end ++ * of this handler - god only knows why it's done like this ++ */ ++ gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd); ++ ++ if (gintsts.b.modemismatch) { ++ retval |= dwc_otg_handle_mode_mismatch_intr(core_if); ++ } ++ if (gintsts.b.otgintr) { ++ retval |= dwc_otg_handle_otg_intr(core_if); ++ } ++ if (gintsts.b.conidstschng) { ++ retval |= ++ dwc_otg_handle_conn_id_status_change_intr(core_if); ++ } ++ if (gintsts.b.disconnect) { ++ retval |= dwc_otg_handle_disconnect_intr(core_if); ++ } ++ if (gintsts.b.sessreqintr) { ++ retval |= dwc_otg_handle_session_req_intr(core_if); ++ } ++ if (gintsts.b.wkupintr) { ++ retval |= dwc_otg_handle_wakeup_detected_intr(core_if); ++ } ++ if (gintsts.b.usbsuspend) { ++ retval |= dwc_otg_handle_usb_suspend_intr(core_if); ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (gintsts.b.lpmtranrcvd) { ++ retval |= dwc_otg_handle_lpm_intr(core_if); ++ } ++#endif ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ if (core_if->power_down == 2) ++ core_if->hibernation_suspend = -1; ++ else if (core_if->power_down == 3 && core_if->xhib == 2) { ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, 0xFFFFFFFF); ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "RESTORE DONE generated\n"); ++ ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ pcgcctl.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl); ++ dwc_udelay(50); ++ ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ dwc_udelay(10); ++ ++ dwc_otg_restore_global_regs(core_if); ++ dwc_otg_restore_dev_regs(core_if, 0); ++ ++ dctl.d32 = 0; ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ dwc_udelay(10); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ core_if->xhib = 0; ++ ++ DWC_SPINUNLOCK(core_if->lock); ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++ DWC_SPINLOCK(core_if->lock); ++ ++ } ++ ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); ++ DWC_PRINTF(" --Restore done interrupt received-- \n"); ++ retval |= 1; ++ } ++ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { ++ /* The port interrupt occurs while in device mode with HPRT0 ++ * Port Enable/Disable. ++ */ ++ gintsts.d32 = 0; ++ gintsts.b.portintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); ++ retval |= 1; ++ gintmsk_reenable.b.portintr = 1; ++ ++ } ++ /* Did we actually handle anything? if so, unmask the interrupt */ ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval); ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32); ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32); ++ if (retval && fiq_enable) { ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32); ++ } ++ ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32); ++ ++ if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, disconn_det); ++ if (gpwrdn.b.linestate == 0) { ++ dwc_otg_handle_pwrdn_disconnect_intr(core_if); ++ } else { ++ DWC_PRINTF("Disconnect detected while linestate is not 0\n"); ++ } ++ ++ retval |= 1; ++ } ++ if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) { ++ CLEAR_GPWRDN_INTR(core_if, lnstschng); ++ /* remote wakeup from hibernation */ ++ if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) { ++ dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if); ++ } else { ++ DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate); ++ } ++ retval |= 1; ++ } ++ if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, rst_det); ++ if (gpwrdn.b.linestate == 0) { ++ DWC_PRINTF("Reset detected\n"); ++ retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1); ++ } ++ } ++ if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, srp_det); ++ dwc_otg_handle_pwrdn_srp_intr(core_if); ++ retval |= 1; ++ } ++ } ++ /* Handle ADP interrupt here */ ++ if (gpwrdn.b.adp_int) { ++ DWC_PRINTF("ADP interrupt\n"); ++ CLEAR_GPWRDN_INTR(core_if, adp_int); ++ dwc_otg_adp_handle_intr(core_if); ++ retval |= 1; ++ } ++ if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) { ++ DWC_PRINTF("STS CHNG interrupt asserted\n"); ++ CLEAR_GPWRDN_INTR(core_if, sts_chngint); ++ dwc_otg_handle_pwrdn_stschng_intr(otg_dev); ++ ++ retval |= 1; ++ } ++ if (core_if->lock) ++ DWC_SPINUNLOCK(core_if->lock); ++ return retval; ++} +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h +@@ -0,0 +1,705 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $ ++ * $Revision: #13 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#if !defined(__DWC_CORE_IF_H__) ++#define __DWC_CORE_IF_H__ ++ ++#include "dwc_os.h" ++ ++/** @file ++ * This file defines DWC_OTG Core API ++ */ ++ ++struct dwc_otg_core_if; ++typedef struct dwc_otg_core_if dwc_otg_core_if_t; ++ ++/** Maximum number of Periodic FIFOs */ ++#define MAX_PERIO_FIFOS 15 ++/** Maximum number of Periodic FIFOs */ ++#define MAX_TX_FIFOS 15 ++ ++/** Maximum number of Endpoints/HostChannels */ ++#define MAX_EPS_CHANNELS 16 ++ ++extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr); ++extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if); ++ ++extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if); ++ ++extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if); ++extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if); ++ ++extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if); ++ ++/** This function should be called on every hardware interrupt. */ ++extern int32_t dwc_otg_handle_common_intr(void *otg_dev); ++ ++/** @name OTG Core Parameters */ ++/** @{ */ ++ ++/** ++ * Specifies the OTG capabilities. The driver will automatically ++ * detect the value for this parameter if none is specified. ++ * 0 - HNP and SRP capable (default) ++ * 1 - SRP Only capable ++ * 2 - No HNP/SRP capable ++ */ ++extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if); ++#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 ++#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 ++#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 ++#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ++ ++extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if); ++#define dwc_param_opt_default 1 ++ ++/** ++ * Specifies whether to use slave or DMA mode for accessing the data ++ * FIFOs. The driver will automatically detect the value for this ++ * parameter if none is specified. ++ * 0 - Slave ++ * 1 - DMA (default, if available) ++ */ ++extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_dma_enable_default 1 ++ ++/** ++ * When DMA mode is enabled specifies whether to use ++ * address DMA or DMA Descritor mode for accessing the data ++ * FIFOs in device mode. The driver will automatically detect ++ * the value for this parameter if none is specified. ++ * 0 - address DMA ++ * 1 - DMA Descriptor(default, if available) ++ */ ++extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if); ++//#define dwc_param_dma_desc_enable_default 1 ++#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708 ++ ++/** The DMA Burst size (applicable only for External DMA ++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++ */ ++extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_dma_burst_size_default 32 ++ ++/** ++ * Specifies the maximum speed of operation in host and device mode. ++ * The actual speed depends on the speed of the attached device and ++ * the value of phy_type. The actual speed depends on the speed of the ++ * attached device. ++ * 0 - High Speed (default) ++ * 1 - Full Speed ++ */ ++extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if); ++#define dwc_param_speed_default 0 ++#define DWC_SPEED_PARAM_HIGH 0 ++#define DWC_SPEED_PARAM_FULL 1 ++ ++/** Specifies whether low power mode is supported when attached ++ * to a Full Speed or Low Speed device in host mode. ++ * 0 - Don't support low power mode (default) ++ * 1 - Support low power mode ++ */ ++extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t ++ * core_if); ++#define dwc_param_host_support_fs_ls_low_power_default 0 ++ ++/** Specifies the PHY clock rate in low power mode when connected to a ++ * Low Speed device in host mode. This parameter is applicable only if ++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS ++ * then defaults to 6 MHZ otherwise 48 MHZ. ++ * ++ * 0 - 48 MHz ++ * 1 - 6 MHz ++ */ ++extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_host_ls_low_power_phy_clk_default 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 ++ ++/** ++ * 0 - Use cC FIFO size parameters ++ * 1 - Allow dynamic FIFO sizing (default) ++ */ ++extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_enable_dynamic_fifo_default 1 ++ ++/** Total number of 4-byte words in the data FIFO memory. This ++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic ++ * Tx FIFOs. ++ * 32 to 32768 (default 8192) ++ * Note: The total FIFO memory depth in the FPGA configuration is 8192. ++ */ ++extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if); ++//#define dwc_param_data_fifo_size_default 8192 ++#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1064) ++ */ ++extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_rx_fifo_size_default 1064 ++ ++/** Number of 4-byte words in the non-periodic Tx FIFO in device mode ++ * when dynamic FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_dev_nperio_tx_fifo_size_default 1024 ++ ++/** Number of 4-byte words in each of the periodic Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val, int fifo_num); ++extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int fifo_num); ++#define dwc_param_dev_perio_tx_fifo_size_default 256 ++ ++/** Number of 4-byte words in the Rx FIFO in host mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if); ++//#define dwc_param_host_rx_fifo_size_default 1024 ++#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the non-periodic Tx FIFO in host mode ++ * when Dynamic FIFO sizing is enabled in the core. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++//#define dwc_param_host_nperio_tx_fifo_size_default 1024 ++#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the host periodic Tx FIFO when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++//#define dwc_param_host_perio_tx_fifo_size_default 1024 ++#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708 ++ ++/** The maximum transfer size supported in bytes. ++ * 2047 to 65,535 (default 65,535) ++ */ ++extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_max_transfer_size_default 65535 ++ ++/** The maximum number of packets in a transfer. ++ * 15 to 511 (default 511) ++ */ ++extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if); ++#define dwc_param_max_packet_count_default 511 ++ ++/** The number of host channel registers to use. ++ * 1 to 16 (default 12) ++ * Note: The FPGA configuration supports a maximum of 12 host channels. ++ */ ++extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if); ++//#define dwc_param_host_channels_default 12 ++#define dwc_param_host_channels_default 8 // Broadcom BCM2708 ++ ++/** The number of endpoints in addition to EP0 available for device ++ * mode operations. ++ * 1 to 15 (default 6 IN and OUT) ++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT ++ * endpoints in addition to EP0. ++ */ ++extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_endpoints_default 6 ++ ++/** ++ * Specifies the type of PHY interface to use. By default, the driver ++ * will automatically detect the phy_type. ++ * ++ * 0 - Full Speed PHY ++ * 1 - UTMI+ (default) ++ * 2 - ULPI ++ */ ++extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if); ++#define DWC_PHY_TYPE_PARAM_FS 0 ++#define DWC_PHY_TYPE_PARAM_UTMI 1 ++#define DWC_PHY_TYPE_PARAM_ULPI 2 ++#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI ++ ++/** ++ * Specifies the UTMI+ Data Width. This parameter is ++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI ++ * PHY_TYPE, this parameter indicates the data width between ++ * the MAC and the ULPI Wrapper.) Also, this parameter is ++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set ++ * to "8 and 16 bits", meaning that the core has been ++ * configured to work at either data path width. ++ * ++ * 8 or 16 bits (default 16) ++ */ ++extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if); ++//#define dwc_param_phy_utmi_width_default 16 ++#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708 ++ ++/** ++ * Specifies whether the ULPI operates at double or single ++ * data rate. This parameter is only applicable if PHY_TYPE is ++ * ULPI. ++ * ++ * 0 - single data rate ULPI interface with 8 bit wide data ++ * bus (default) ++ * 1 - double data rate ULPI interface with 4 bit wide data ++ * bus ++ */ ++extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if); ++#define dwc_param_phy_ulpi_ddr_default 0 ++ ++/** ++ * Specifies whether to use the internal or external supply to ++ * drive the vbus with a ULPI phy. ++ */ ++extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if); ++#define DWC_PHY_ULPI_INTERNAL_VBUS 0 ++#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 ++#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS ++ ++/** ++ * Specifies whether to use the I2Cinterface for full speed PHY. This ++ * parameter is only applicable if PHY_TYPE is FS. ++ * 0 - No (default) ++ * 1 - Yes ++ */ ++extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_i2c_enable_default 0 ++ ++extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if); ++#define dwc_param_ulpi_fs_ls_default 0 ++ ++extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if); ++#define dwc_param_ts_dline_default 0 ++ ++/** ++ * Specifies whether dedicated transmit FIFOs are ++ * enabled for non periodic IN endpoints in device mode ++ * 0 - No ++ * 1 - Yes ++ */ ++extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_en_multiple_tx_fifo_default 1 ++ ++/** Number of 4-byte words in each of the Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num, int32_t val); ++extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num); ++#define dwc_param_dev_tx_fifo_size_default 768 ++ ++/** Thresholding enable flag- ++ * bit 0 - enable non-ISO Tx thresholding ++ * bit 1 - enable ISO Tx thresholding ++ * bit 2 - enable Rx thresholding ++ */ ++extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num); ++#define dwc_param_thr_ctl_default 0 ++ ++/** Thresholding length for Tx ++ * FIFOs in 32 bit DWORDs ++ */ ++extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if); ++#define dwc_param_tx_thr_length_default 64 ++ ++/** Thresholding length for Rx ++ * FIFOs in 32 bit DWORDs ++ */ ++extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if); ++#define dwc_param_rx_thr_length_default 64 ++ ++/** ++ * Specifies whether LPM (Link Power Management) support is enabled ++ */ ++extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_lpm_enable_default 1 ++ ++/** ++ * Specifies whether PTI enhancement is enabled ++ */ ++extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_pti_enable_default 0 ++ ++/** ++ * Specifies whether MPI enhancement is enabled ++ */ ++extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_mpi_enable_default 0 ++ ++/** ++ * Specifies whether ADP capability is enabled ++ */ ++extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_adp_enable_default 0 ++ ++/** ++ * Specifies whether IC_USB capability is enabled ++ */ ++ ++extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if); ++#define dwc_param_ic_usb_cap_default 0 ++ ++extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if); ++#define dwc_param_ahb_thr_ratio_default 0 ++ ++extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if); ++#define dwc_param_power_down_default 0 ++ ++extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if); ++#define dwc_param_reload_ctl_default 0 ++ ++extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_out_nak_default 0 ++ ++extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if); ++#define dwc_param_cont_on_bna_default 0 ++ ++extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if); ++#define dwc_param_ahb_single_default 0 ++ ++extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if); ++#define dwc_param_otg_ver_default 0 ++ ++/** @} */ ++ ++/** @name Access to registers and bit-fields */ ++ ++/** ++ * Dump core registers and SPRAM ++ */ ++extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if); ++ ++/** ++ * Get host negotiation status. ++ */ ++extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get srp status ++ */ ++extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Set hnpreq bit in the GOTGCTL register. ++ */ ++extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get Content of SNPSID register. ++ */ ++extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get current mode. ++ * Returns 0 if in device mode, and 1 if in host mode. ++ */ ++extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of hnpcapable field in the GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of hnpcapable field in the GUSBCFG register ++ */ ++extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of srpcapable field in the GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of srpcapable field in the GUSBCFG register ++ */ ++extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of devspeed field in the DCFG register ++ */ ++extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of devspeed field in the DCFG register ++ */ ++extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get the value of busconnected field from the HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Gets the device enumeration Speed. ++ */ ++extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of prtpwr field from the HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of flag indicating core state - hibernated or not ++ */ ++extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Set value of prtpwr field from the HPRT0 register ++ */ ++extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of prtsusp field from the HPRT0 regsiter ++ */ ++extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of prtpwr field from the HPRT0 register ++ */ ++extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of ModeChTimEn field from the HCFG regsiter ++ */ ++extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of ModeChTimEn field from the HCFG regsiter ++ */ ++extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of Fram Interval field from the HFIR regsiter ++ */ ++extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of Frame Interval field from the HFIR regsiter ++ */ ++extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Set value of prtres field from the HPRT0 register ++ *FIXME Remove? ++ */ ++extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of rmtwkupsig bit in DCTL register ++ */ ++extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of prt_sleep_sts field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of rem_wkup_en field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of appl_resp field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of appl_resp field from the GLPMCFG register ++ */ ++extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of hsic_connect field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of hsic_connect field from the GLPMCFG register ++ */ ++extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of inv_sel_hsic field from the GLPMCFG register. ++ */ ++extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of inv_sel_hsic field from the GLPMFG register. ++ */ ++extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/* ++ * Some functions for accessing registers ++ */ ++ ++/** ++ * GOTGCTL register ++ */ ++extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GRXFSIZ register ++ */ ++extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GNPTXFSIZ register ++ */ ++extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GGPIO register ++ */ ++extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GUID register ++ */ ++extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GHPTXFSIZE ++ */ ++extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if); ++ ++/** @} */ ++ ++#endif /* __DWC_CORE_IF_H__ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h +@@ -0,0 +1,117 @@ ++/* ========================================================================== ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_DBG_H__ ++#define __DWC_OTG_DBG_H__ ++ ++/** @file ++ * This file defines debug levels. ++ * Debugging support vanishes in non-debug builds. ++ */ ++ ++/** ++ * The Debug Level bit-mask variable. ++ */ ++extern uint32_t g_dbg_lvl; ++/** ++ * Set the Debug Level variable. ++ */ ++static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new) ++{ ++ uint32_t old = g_dbg_lvl; ++ g_dbg_lvl = new; ++ return old; ++} ++ ++#define DBG_USER (0x1) ++/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ ++#define DBG_CIL (0x2) ++/** When debug level has the DBG_CILV bit set, display CIL Verbose debug ++ * messages */ ++#define DBG_CILV (0x20) ++/** When debug level has the DBG_PCD bit set, display PCD (Device) debug ++ * messages */ ++#define DBG_PCD (0x4) ++/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug ++ * messages */ ++#define DBG_PCDV (0x40) ++/** When debug level has the DBG_HCD bit set, display Host debug messages */ ++#define DBG_HCD (0x8) ++/** When debug level has the DBG_HCDV bit set, display Verbose Host debug ++ * messages */ ++#define DBG_HCDV (0x80) ++/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host ++ * mode. */ ++#define DBG_HCD_URB (0x800) ++/** When debug level has the DBG_HCDI bit set, display host interrupt ++ * messages. */ ++#define DBG_HCDI (0x1000) ++ ++/** When debug level has any bit set, display debug messages */ ++#define DBG_ANY (0xFF) ++ ++/** All debug messages off */ ++#define DBG_OFF 0 ++ ++/** Prefix string for DWC_DEBUG print macros. */ ++#define USB_DWC "DWC_otg: " ++ ++/** ++ * Print a debug message when the Global debug level variable contains ++ * the bit defined in lvl. ++ * ++ * @param[in] lvl - Debug level, use one of the DBG_ constants above. ++ * @param[in] x - like printf ++ * ++ * Example:

++ * ++ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); ++ * ++ *
++ * results in:
++ * ++ * usb-DWC_otg: dwc_otg_cil_init(ca867000) ++ * ++ */ ++#ifdef DEBUG ++ ++# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0) ++# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) ++ ++# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) ++ ++#else ++ ++# define DWC_DEBUGPL(lvl, x...) do{}while(0) ++# define DWC_DEBUGP(x...) ++ ++# define CHK_DEBUG_LEVEL(level) (0) ++ ++#endif /*DEBUG*/ ++#endif +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c +@@ -0,0 +1,1756 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $ ++ * $Revision: #92 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * The dwc_otg_driver module provides the initialization and cleanup entry ++ * points for the DWC_otg driver. This module will be dynamically installed ++ * after Linux is booted using the insmod command. When the module is ++ * installed, the dwc_otg_driver_init function is called. When the module is ++ * removed (using rmmod), the dwc_otg_driver_cleanup function is called. ++ * ++ * This module also defines a data structure for the dwc_otg_driver, which is ++ * used in conjunction with the standard ARM lm_device structure. These ++ * structures allow the OTG driver to comply with the standard Linux driver ++ * model in which devices and drivers are registered with a bus driver. This ++ * has the benefit that Linux can expose attributes of the driver and device ++ * in its special sysfs file system. Users can then read or write files in ++ * this file system to perform diagnostics on the driver components or the ++ * device. ++ */ ++ ++#include "dwc_otg_os_dep.h" ++#include "dwc_os.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_attr.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_hcd_if.h" ++#include "dwc_otg_fiq_fsm.h" ++ ++#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012" ++#define DWC_DRIVER_DESC "HS OTG USB Controller driver" ++ ++bool microframe_schedule=true; ++ ++static const char dwc_driver_name[] = "dwc_otg"; ++ ++ ++extern int pcd_init( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++extern int hcd_init( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++ ++extern int pcd_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ); ++ ++extern void hcd_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ); ++ ++extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); ++ ++/*-------------------------------------------------------------------------*/ ++/* Encapsulate the module parameter settings */ ++ ++struct dwc_otg_driver_module_params { ++ int32_t opt; ++ int32_t otg_cap; ++ int32_t dma_enable; ++ int32_t dma_desc_enable; ++ int32_t dma_burst_size; ++ int32_t speed; ++ int32_t host_support_fs_ls_low_power; ++ int32_t host_ls_low_power_phy_clk; ++ int32_t enable_dynamic_fifo; ++ int32_t data_fifo_size; ++ int32_t dev_rx_fifo_size; ++ int32_t dev_nperio_tx_fifo_size; ++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ int32_t host_rx_fifo_size; ++ int32_t host_nperio_tx_fifo_size; ++ int32_t host_perio_tx_fifo_size; ++ int32_t max_transfer_size; ++ int32_t max_packet_count; ++ int32_t host_channels; ++ int32_t dev_endpoints; ++ int32_t phy_type; ++ int32_t phy_utmi_width; ++ int32_t phy_ulpi_ddr; ++ int32_t phy_ulpi_ext_vbus; ++ int32_t i2c_enable; ++ int32_t ulpi_fs_ls; ++ int32_t ts_dline; ++ int32_t en_multiple_tx_fifo; ++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; ++ uint32_t thr_ctl; ++ uint32_t tx_thr_length; ++ uint32_t rx_thr_length; ++ int32_t pti_enable; ++ int32_t mpi_enable; ++ int32_t lpm_enable; ++ int32_t ic_usb_cap; ++ int32_t ahb_thr_ratio; ++ int32_t power_down; ++ int32_t reload_ctl; ++ int32_t dev_out_nak; ++ int32_t cont_on_bna; ++ int32_t ahb_single; ++ int32_t otg_ver; ++ int32_t adp_enable; ++}; ++ ++static struct dwc_otg_driver_module_params dwc_otg_module_params = { ++ .opt = -1, ++ .otg_cap = -1, ++ .dma_enable = -1, ++ .dma_desc_enable = -1, ++ .dma_burst_size = -1, ++ .speed = -1, ++ .host_support_fs_ls_low_power = -1, ++ .host_ls_low_power_phy_clk = -1, ++ .enable_dynamic_fifo = -1, ++ .data_fifo_size = -1, ++ .dev_rx_fifo_size = -1, ++ .dev_nperio_tx_fifo_size = -1, ++ .dev_perio_tx_fifo_size = { ++ /* dev_perio_tx_fifo_size_1 */ ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1 ++ /* 15 */ ++ }, ++ .host_rx_fifo_size = -1, ++ .host_nperio_tx_fifo_size = -1, ++ .host_perio_tx_fifo_size = -1, ++ .max_transfer_size = -1, ++ .max_packet_count = -1, ++ .host_channels = -1, ++ .dev_endpoints = -1, ++ .phy_type = -1, ++ .phy_utmi_width = -1, ++ .phy_ulpi_ddr = -1, ++ .phy_ulpi_ext_vbus = -1, ++ .i2c_enable = -1, ++ .ulpi_fs_ls = -1, ++ .ts_dline = -1, ++ .en_multiple_tx_fifo = -1, ++ .dev_tx_fifo_size = { ++ /* dev_tx_fifo_size */ ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1 ++ /* 15 */ ++ }, ++ .thr_ctl = -1, ++ .tx_thr_length = -1, ++ .rx_thr_length = -1, ++ .pti_enable = -1, ++ .mpi_enable = -1, ++ .lpm_enable = 0, ++ .ic_usb_cap = -1, ++ .ahb_thr_ratio = -1, ++ .power_down = -1, ++ .reload_ctl = -1, ++ .dev_out_nak = -1, ++ .cont_on_bna = -1, ++ .ahb_single = -1, ++ .otg_ver = -1, ++ .adp_enable = -1, ++}; ++ ++//Global variable to switch the fiq fix on or off ++bool fiq_enable = 1; ++// Global variable to enable the split transaction fix ++bool fiq_fsm_enable = true; ++//Bulk split-transaction NAK holdoff in microframes ++uint16_t nak_holdoff = 8; ++ ++unsigned short fiq_fsm_mask = 0x07; ++ ++/** ++ * This function shows the Driver Version. ++ */ ++static ssize_t version_show(struct device_driver *dev, char *buf) ++{ ++ return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n", ++ DWC_DRIVER_VERSION); ++} ++ ++static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); ++ ++/** ++ * Global Debug Level Mask. ++ */ ++uint32_t g_dbg_lvl = 0; /* OFF */ ++ ++/** ++ * This function shows the driver Debug Level. ++ */ ++static ssize_t dbg_level_show(struct device_driver *drv, char *buf) ++{ ++ return sprintf(buf, "0x%0x\n", g_dbg_lvl); ++} ++ ++/** ++ * This function stores the driver Debug Level. ++ */ ++static ssize_t dbg_level_store(struct device_driver *drv, const char *buf, ++ size_t count) ++{ ++ g_dbg_lvl = simple_strtoul(buf, NULL, 16); ++ return count; ++} ++ ++static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show, ++ dbg_level_store); ++ ++/** ++ * This function is called during module intialization ++ * to pass module parameters to the DWC_OTG CORE. ++ */ ++static int set_parameters(dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ int i; ++ ++ if (dwc_otg_module_params.otg_cap != -1) { ++ retval += ++ dwc_otg_set_param_otg_cap(core_if, ++ dwc_otg_module_params.otg_cap); ++ } ++ if (dwc_otg_module_params.dma_enable != -1) { ++ retval += ++ dwc_otg_set_param_dma_enable(core_if, ++ dwc_otg_module_params. ++ dma_enable); ++ } ++ if (dwc_otg_module_params.dma_desc_enable != -1) { ++ retval += ++ dwc_otg_set_param_dma_desc_enable(core_if, ++ dwc_otg_module_params. ++ dma_desc_enable); ++ } ++ if (dwc_otg_module_params.opt != -1) { ++ retval += ++ dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt); ++ } ++ if (dwc_otg_module_params.dma_burst_size != -1) { ++ retval += ++ dwc_otg_set_param_dma_burst_size(core_if, ++ dwc_otg_module_params. ++ dma_burst_size); ++ } ++ if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) { ++ retval += ++ dwc_otg_set_param_host_support_fs_ls_low_power(core_if, ++ dwc_otg_module_params. ++ host_support_fs_ls_low_power); ++ } ++ if (dwc_otg_module_params.enable_dynamic_fifo != -1) { ++ retval += ++ dwc_otg_set_param_enable_dynamic_fifo(core_if, ++ dwc_otg_module_params. ++ enable_dynamic_fifo); ++ } ++ if (dwc_otg_module_params.data_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_data_fifo_size(core_if, ++ dwc_otg_module_params. ++ data_fifo_size); ++ } ++ if (dwc_otg_module_params.dev_rx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_dev_rx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_rx_fifo_size); ++ } ++ if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_nperio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_rx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_rx_fifo_size(core_if, ++ dwc_otg_module_params.host_rx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ host_nperio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_perio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ host_perio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.max_transfer_size != -1) { ++ retval += ++ dwc_otg_set_param_max_transfer_size(core_if, ++ dwc_otg_module_params. ++ max_transfer_size); ++ } ++ if (dwc_otg_module_params.max_packet_count != -1) { ++ retval += ++ dwc_otg_set_param_max_packet_count(core_if, ++ dwc_otg_module_params. ++ max_packet_count); ++ } ++ if (dwc_otg_module_params.host_channels != -1) { ++ retval += ++ dwc_otg_set_param_host_channels(core_if, ++ dwc_otg_module_params. ++ host_channels); ++ } ++ if (dwc_otg_module_params.dev_endpoints != -1) { ++ retval += ++ dwc_otg_set_param_dev_endpoints(core_if, ++ dwc_otg_module_params. ++ dev_endpoints); ++ } ++ if (dwc_otg_module_params.phy_type != -1) { ++ retval += ++ dwc_otg_set_param_phy_type(core_if, ++ dwc_otg_module_params.phy_type); ++ } ++ if (dwc_otg_module_params.speed != -1) { ++ retval += ++ dwc_otg_set_param_speed(core_if, ++ dwc_otg_module_params.speed); ++ } ++ if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) { ++ retval += ++ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, ++ dwc_otg_module_params. ++ host_ls_low_power_phy_clk); ++ } ++ if (dwc_otg_module_params.phy_ulpi_ddr != -1) { ++ retval += ++ dwc_otg_set_param_phy_ulpi_ddr(core_if, ++ dwc_otg_module_params. ++ phy_ulpi_ddr); ++ } ++ if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) { ++ retval += ++ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, ++ dwc_otg_module_params. ++ phy_ulpi_ext_vbus); ++ } ++ if (dwc_otg_module_params.phy_utmi_width != -1) { ++ retval += ++ dwc_otg_set_param_phy_utmi_width(core_if, ++ dwc_otg_module_params. ++ phy_utmi_width); ++ } ++ if (dwc_otg_module_params.ulpi_fs_ls != -1) { ++ retval += ++ dwc_otg_set_param_ulpi_fs_ls(core_if, ++ dwc_otg_module_params.ulpi_fs_ls); ++ } ++ if (dwc_otg_module_params.ts_dline != -1) { ++ retval += ++ dwc_otg_set_param_ts_dline(core_if, ++ dwc_otg_module_params.ts_dline); ++ } ++ if (dwc_otg_module_params.i2c_enable != -1) { ++ retval += ++ dwc_otg_set_param_i2c_enable(core_if, ++ dwc_otg_module_params. ++ i2c_enable); ++ } ++ if (dwc_otg_module_params.en_multiple_tx_fifo != -1) { ++ retval += ++ dwc_otg_set_param_en_multiple_tx_fifo(core_if, ++ dwc_otg_module_params. ++ en_multiple_tx_fifo); ++ } ++ for (i = 0; i < 15; i++) { ++ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { ++ retval += ++ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_perio_tx_fifo_size ++ [i], i); ++ } ++ } ++ ++ for (i = 0; i < 15; i++) { ++ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { ++ retval += dwc_otg_set_param_dev_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_tx_fifo_size ++ [i], i); ++ } ++ } ++ if (dwc_otg_module_params.thr_ctl != -1) { ++ retval += ++ dwc_otg_set_param_thr_ctl(core_if, ++ dwc_otg_module_params.thr_ctl); ++ } ++ if (dwc_otg_module_params.mpi_enable != -1) { ++ retval += ++ dwc_otg_set_param_mpi_enable(core_if, ++ dwc_otg_module_params. ++ mpi_enable); ++ } ++ if (dwc_otg_module_params.pti_enable != -1) { ++ retval += ++ dwc_otg_set_param_pti_enable(core_if, ++ dwc_otg_module_params. ++ pti_enable); ++ } ++ if (dwc_otg_module_params.lpm_enable != -1) { ++ retval += ++ dwc_otg_set_param_lpm_enable(core_if, ++ dwc_otg_module_params. ++ lpm_enable); ++ } ++ if (dwc_otg_module_params.ic_usb_cap != -1) { ++ retval += ++ dwc_otg_set_param_ic_usb_cap(core_if, ++ dwc_otg_module_params. ++ ic_usb_cap); ++ } ++ if (dwc_otg_module_params.tx_thr_length != -1) { ++ retval += ++ dwc_otg_set_param_tx_thr_length(core_if, ++ dwc_otg_module_params.tx_thr_length); ++ } ++ if (dwc_otg_module_params.rx_thr_length != -1) { ++ retval += ++ dwc_otg_set_param_rx_thr_length(core_if, ++ dwc_otg_module_params. ++ rx_thr_length); ++ } ++ if (dwc_otg_module_params.ahb_thr_ratio != -1) { ++ retval += ++ dwc_otg_set_param_ahb_thr_ratio(core_if, ++ dwc_otg_module_params.ahb_thr_ratio); ++ } ++ if (dwc_otg_module_params.power_down != -1) { ++ retval += ++ dwc_otg_set_param_power_down(core_if, ++ dwc_otg_module_params.power_down); ++ } ++ if (dwc_otg_module_params.reload_ctl != -1) { ++ retval += ++ dwc_otg_set_param_reload_ctl(core_if, ++ dwc_otg_module_params.reload_ctl); ++ } ++ ++ if (dwc_otg_module_params.dev_out_nak != -1) { ++ retval += ++ dwc_otg_set_param_dev_out_nak(core_if, ++ dwc_otg_module_params.dev_out_nak); ++ } ++ ++ if (dwc_otg_module_params.cont_on_bna != -1) { ++ retval += ++ dwc_otg_set_param_cont_on_bna(core_if, ++ dwc_otg_module_params.cont_on_bna); ++ } ++ ++ if (dwc_otg_module_params.ahb_single != -1) { ++ retval += ++ dwc_otg_set_param_ahb_single(core_if, ++ dwc_otg_module_params.ahb_single); ++ } ++ ++ if (dwc_otg_module_params.otg_ver != -1) { ++ retval += ++ dwc_otg_set_param_otg_ver(core_if, ++ dwc_otg_module_params.otg_ver); ++ } ++ if (dwc_otg_module_params.adp_enable != -1) { ++ retval += ++ dwc_otg_set_param_adp_enable(core_if, ++ dwc_otg_module_params. ++ adp_enable); ++ } ++ return retval; ++} ++ ++/** ++ * This function is the top level interrupt handler for the Common ++ * (Device and host modes) interrupts. ++ */ ++static irqreturn_t dwc_otg_common_irq(int irq, void *dev) ++{ ++ int32_t retval = IRQ_NONE; ++ ++ retval = dwc_otg_handle_common_intr(dev); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** ++ * This function is called when a lm_device is unregistered with the ++ * dwc_otg_driver. This happens, for example, when the rmmod command is ++ * executed. The device may or may not be electrically present. If it is ++ * present, the driver stops device processing. Any resources used on behalf ++ * of this device are freed. ++ * ++ * @param _dev ++ */ ++#ifdef LM_INTERFACE ++#define REM_RETVAL(n) ++static void dwc_otg_driver_remove( struct lm_device *_dev ) ++{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); ++#elif defined(PCI_INTERFACE) ++#define REM_RETVAL(n) ++static void dwc_otg_driver_remove( struct pci_dev *_dev ) ++{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++#define REM_RETVAL(n) n ++static int dwc_otg_driver_remove( struct platform_device *_dev ) ++{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++#endif ++ ++ DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); ++ ++ if (!otg_dev) { ++ /* Memory allocation for the dwc_otg_device failed. */ ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); ++ return REM_RETVAL(-ENOMEM); ++ } ++#ifndef DWC_DEVICE_ONLY ++ if (otg_dev->hcd) { ++ hcd_remove(_dev); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); ++ return REM_RETVAL(-EINVAL); ++ } ++#endif ++ ++#ifndef DWC_HOST_ONLY ++ if (otg_dev->pcd) { ++ pcd_remove(_dev); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__); ++ return REM_RETVAL(-EINVAL); ++ } ++#endif ++ /* ++ * Free the IRQ ++ */ ++ if (otg_dev->common_irq_installed) { ++#ifdef PLATFORM_INTERFACE ++ free_irq(platform_get_irq(_dev, 0), otg_dev); ++#else ++ free_irq(_dev->irq, otg_dev); ++#endif ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__); ++ return REM_RETVAL(-ENXIO); ++ } ++ ++ if (otg_dev->core_if) { ++ dwc_otg_cil_remove(otg_dev->core_if); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__); ++ return REM_RETVAL(-ENXIO); ++ } ++ ++ /* ++ * Remove the device attributes ++ */ ++ dwc_otg_attr_remove(_dev); ++ ++ /* ++ * Return the memory. ++ */ ++ if (otg_dev->os_dep.base) { ++ iounmap(otg_dev->os_dep.base); ++ } ++ DWC_FREE(otg_dev); ++ ++ /* ++ * Clear the drvdata pointer. ++ */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, 0); ++#elif defined(PCI_INTERFACE) ++ release_mem_region(otg_dev->os_dep.rsrc_start, ++ otg_dev->os_dep.rsrc_len); ++ pci_set_drvdata(_dev, 0); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, 0); ++#endif ++ return REM_RETVAL(0); ++} ++ ++/** ++ * This function is called when an lm_device is bound to a ++ * dwc_otg_driver. It creates the driver components required to ++ * control the device (CIL, HCD, and PCD) and it initializes the ++ * device. The driver components are stored in a dwc_otg_device ++ * structure. A reference to the dwc_otg_device is saved in the ++ * lm_device. This allows the driver to access the dwc_otg_device ++ * structure on subsequent calls to driver methods for this device. ++ * ++ * @param _dev Bus device ++ */ ++static int dwc_otg_driver_probe( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev, ++ const struct pci_device_id *id ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ) ++{ ++ int retval = 0; ++ dwc_otg_device_t *dwc_otg_device; ++ int devirq; ++ ++ dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev); ++#ifdef LM_INTERFACE ++ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start); ++#elif defined(PCI_INTERFACE) ++ if (!id) { ++ DWC_ERROR("Invalid pci_device_id %p", id); ++ return -EINVAL; ++ } ++ ++ if (!_dev || (pci_enable_device(_dev) < 0)) { ++ DWC_ERROR("Invalid pci_device %p", _dev); ++ return -ENODEV; ++ } ++ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0)); ++ /* other stuff needed as well? */ ++ ++#elif defined(PLATFORM_INTERFACE) ++ dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n", ++ (unsigned)_dev->resource->start, ++ (unsigned)(_dev->resource->end - _dev->resource->start)); ++#endif ++ ++ dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t)); ++ ++ if (!dwc_otg_device) { ++ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); ++ return -ENOMEM; ++ } ++ ++ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); ++ dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF; ++ ++ /* ++ * Map the DWC_otg Core memory into virtual address space. ++ */ ++#ifdef LM_INTERFACE ++ dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K); ++ ++ if (!dwc_otg_device->os_dep.base) { ++ dev_err(&_dev->dev, "ioremap() failed\n"); ++ DWC_FREE(dwc_otg_device); ++ return -ENOMEM; ++ } ++ dev_dbg(&_dev->dev, "base=0x%08x\n", ++ (unsigned)dwc_otg_device->os_dep.base); ++#elif defined(PCI_INTERFACE) ++ _dev->current_state = PCI_D0; ++ _dev->dev.power.power_state = PMSG_ON; ++ ++ if (!_dev->irq) { ++ DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", ++ pci_name(_dev)); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -ENODEV; ++ } ++ ++ dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0); ++ dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0); ++ DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n", ++ (unsigned)dwc_otg_device->os_dep.rsrc_start, ++ (unsigned)dwc_otg_device->os_dep.rsrc_len); ++ if (!request_mem_region ++ (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error requesting memory\n"); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -EFAULT; ++ } ++ ++ dwc_otg_device->os_dep.base = ++ ioremap_nocache(dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.rsrc_len); ++ if (dwc_otg_device->os_dep.base == NULL) { ++ dev_dbg(&_dev->dev, "error mapping memory\n"); ++ release_mem_region(dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.rsrc_len); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -EFAULT; ++ } ++ dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", ++ dwc_otg_device->os_dep.base); ++ dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base; ++ dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", ++ dwc_otg_device->os_dep.base); ++ dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__, ++ (unsigned)dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.base); ++ ++ pci_set_master(_dev); ++ pci_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PLATFORM_INTERFACE) ++ DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n", ++ _dev->resource->start, ++ _dev->resource->end - _dev->resource->start + 1); ++#if 1 ++ if (!request_mem_region(_dev->resource[0].start, ++ _dev->resource[0].end - _dev->resource[0].start + 1, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error reserving mapped memory\n"); ++ retval = -EFAULT; ++ goto fail; ++ } ++ ++ dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start, ++ _dev->resource[0].end - ++ _dev->resource[0].start+1); ++ if (fiq_enable) ++ { ++ if (!request_mem_region(_dev->resource[1].start, ++ _dev->resource[1].end - _dev->resource[1].start + 1, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error reserving mapped memory\n"); ++ retval = -EFAULT; ++ goto fail; ++ } ++ ++ dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start, ++ _dev->resource[1].end - ++ _dev->resource[1].start + 1); ++ } ++ ++#else ++ { ++ struct map_desc desc = { ++ .virtual = IO_ADDRESS((unsigned)_dev->resource->start), ++ .pfn = __phys_to_pfn((unsigned)_dev->resource->start), ++ .length = SZ_128K, ++ .type = MT_DEVICE ++ }; ++ iotable_init(&desc, 1); ++ dwc_otg_device->os_dep.base = (void *)desc.virtual; ++ } ++#endif ++ if (!dwc_otg_device->os_dep.base) { ++ dev_err(&_dev->dev, "ioremap() failed\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ dev_dbg(&_dev->dev, "base=0x%08x\n", ++ (unsigned)dwc_otg_device->os_dep.base); ++#endif ++ ++ /* ++ * Initialize driver data to point to the global DWC_otg ++ * Device structure. ++ */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, dwc_otg_device); ++#endif ++ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); ++ ++ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base); ++ DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n", ++ dwc_otg_device, dwc_otg_device->core_if);//GRAYG ++ ++ if (!dwc_otg_device->core_if) { ++ dev_err(&_dev->dev, "CIL initialization failed!\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ ++ dev_dbg(&_dev->dev, "Calling get_gsnpsid\n"); ++ /* ++ * Attempt to ensure this device is really a DWC_otg Controller. ++ * Read and verify the SNPSID register contents. The value should be ++ * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3", ++ * as in "OTG version 2.XX" or "OTG version 3.XX". ++ */ ++ ++ if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) && ++ ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) { ++ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", ++ dwc_otg_get_gsnpsid(dwc_otg_device->core_if)); ++ retval = -EINVAL; ++ goto fail; ++ } ++ ++ /* ++ * Validate parameter values. ++ */ ++ dev_dbg(&_dev->dev, "Calling set_parameters\n"); ++ if (set_parameters(dwc_otg_device->core_if)) { ++ retval = -EINVAL; ++ goto fail; ++ } ++ ++ /* ++ * Create Device Attributes in sysfs ++ */ ++ dev_dbg(&_dev->dev, "Calling attr_create\n"); ++ dwc_otg_attr_create(_dev); ++ ++ /* ++ * Disable the global interrupt until all the interrupt ++ * handlers are installed. ++ */ ++ dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n"); ++ dwc_otg_disable_global_interrupts(dwc_otg_device->core_if); ++ ++ /* ++ * Install the interrupt handler for the common interrupts before ++ * enabling common interrupts in core_init below. ++ */ ++ ++#if defined(PLATFORM_INTERFACE) ++ devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1); ++#else ++ devirq = _dev->irq; ++#endif ++ DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", ++ devirq); ++ dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq); ++ retval = request_irq(devirq, dwc_otg_common_irq, ++ IRQF_SHARED, ++ "dwc_otg", dwc_otg_device); ++ if (retval) { ++ DWC_ERROR("request of irq%d failed\n", devirq); ++ retval = -EBUSY; ++ goto fail; ++ } else { ++ dwc_otg_device->common_irq_installed = 1; ++ } ++ ++#ifndef IRQF_TRIGGER_LOW ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ dev_dbg(&_dev->dev, "Calling set_irq_type\n"); ++ set_irq_type(devirq, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ IRQT_LOW ++#else ++ IRQ_TYPE_LEVEL_LOW ++#endif ++ ); ++#endif ++#endif /*IRQF_TRIGGER_LOW*/ ++ ++ /* ++ * Initialize the DWC_otg core. ++ */ ++ dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n"); ++ dwc_otg_core_init(dwc_otg_device->core_if); ++ ++#ifndef DWC_HOST_ONLY ++ /* ++ * Initialize the PCD ++ */ ++ dev_dbg(&_dev->dev, "Calling pcd_init\n"); ++ retval = pcd_init(_dev); ++ if (retval != 0) { ++ DWC_ERROR("pcd_init failed\n"); ++ dwc_otg_device->pcd = NULL; ++ goto fail; ++ } ++#endif ++#ifndef DWC_DEVICE_ONLY ++ /* ++ * Initialize the HCD ++ */ ++ dev_dbg(&_dev->dev, "Calling hcd_init\n"); ++ retval = hcd_init(_dev); ++ if (retval != 0) { ++ DWC_ERROR("hcd_init failed\n"); ++ dwc_otg_device->hcd = NULL; ++ goto fail; ++ } ++#endif ++ /* Recover from drvdata having been overwritten by hcd_init() */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PCI_INTERFACE) ++ pci_set_drvdata(_dev, dwc_otg_device); ++ dwc_otg_device->os_dep.pcidev = _dev; ++#endif ++ ++ /* ++ * Enable the global interrupt after all the interrupt ++ * handlers are installed if there is no ADP support else ++ * perform initial actions required for Internal ADP logic. ++ */ ++ if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) { ++ dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n"); ++ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); ++ dev_dbg(&_dev->dev, "Done\n"); ++ } else ++ dwc_otg_adp_start(dwc_otg_device->core_if, ++ dwc_otg_is_host_mode(dwc_otg_device->core_if)); ++ ++ return 0; ++ ++fail: ++ dwc_otg_driver_remove(_dev); ++ return retval; ++} ++ ++/** ++ * This structure defines the methods to be called by a bus driver ++ * during the lifecycle of a device on that bus. Both drivers and ++ * devices are registered with a bus driver. The bus driver matches ++ * devices to drivers based on information in the device and driver ++ * structures. ++ * ++ * The probe function is called when the bus driver matches a device ++ * to this driver. The remove function is called when a device is ++ * unregistered with the bus driver. ++ */ ++#ifdef LM_INTERFACE ++static struct lm_driver dwc_otg_driver = { ++ .drv = {.name = (char *)dwc_driver_name,}, ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ // 'suspend' and 'resume' absent ++}; ++#elif defined(PCI_INTERFACE) ++static const struct pci_device_id pci_ids[] = { { ++ PCI_DEVICE(0x16c3, 0xabcd), ++ .driver_data = ++ (unsigned long)0xdeadbeef, ++ }, { /* end: all zeroes */ } ++}; ++ ++MODULE_DEVICE_TABLE(pci, pci_ids); ++ ++/* pci driver glue; this is a "new style" PCI driver module */ ++static struct pci_driver dwc_otg_driver = { ++ .name = "dwc_otg", ++ .id_table = pci_ids, ++ ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ ++ .driver = { ++ .name = (char *)dwc_driver_name, ++ }, ++}; ++#elif defined(PLATFORM_INTERFACE) ++static struct platform_device_id platform_ids[] = { ++ { ++ .name = "bcm2708_usb", ++ .driver_data = (kernel_ulong_t) 0xdeadbeef, ++ }, ++ { /* end: all zeroes */ } ++}; ++MODULE_DEVICE_TABLE(platform, platform_ids); ++ ++static const struct of_device_id dwc_otg_of_match_table[] = { ++ { .compatible = "brcm,bcm2708-usb", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table); ++ ++static struct platform_driver dwc_otg_driver = { ++ .driver = { ++ .name = (char *)dwc_driver_name, ++ .of_match_table = dwc_otg_of_match_table, ++ }, ++ .id_table = platform_ids, ++ ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early' ++}; ++#endif ++ ++/** ++ * This function is called when the dwc_otg_driver is installed with the ++ * insmod command. It registers the dwc_otg_driver structure with the ++ * appropriate bus driver. This will cause the dwc_otg_driver_probe function ++ * to be called. In addition, the bus driver will automatically expose ++ * attributes defined for the device and driver in the special sysfs file ++ * system. ++ * ++ * @return ++ */ ++static int __init dwc_otg_driver_init(void) ++{ ++ int retval = 0; ++ int error; ++ struct device_driver *drv; ++ ++ if(fiq_fsm_enable && !fiq_enable) { ++ printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n"); ++ fiq_enable = 1; ++ } ++ ++ printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name, ++ DWC_DRIVER_VERSION, ++#ifdef LM_INTERFACE ++ "logicmodule"); ++ retval = lm_driver_register(&dwc_otg_driver); ++ drv = &dwc_otg_driver.drv; ++#elif defined(PCI_INTERFACE) ++ "pci"); ++ retval = pci_register_driver(&dwc_otg_driver); ++ drv = &dwc_otg_driver.driver; ++#elif defined(PLATFORM_INTERFACE) ++ "platform"); ++ retval = platform_driver_register(&dwc_otg_driver); ++ drv = &dwc_otg_driver.driver; ++#endif ++ if (retval < 0) { ++ printk(KERN_ERR "%s retval=%d\n", __func__, retval); ++ return retval; ++ } ++ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled"); ++ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled"); ++ printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled"); ++ ++ error = driver_create_file(drv, &driver_attr_version); ++#ifdef DEBUG ++ error = driver_create_file(drv, &driver_attr_debuglevel); ++#endif ++ return retval; ++} ++ ++module_init(dwc_otg_driver_init); ++ ++/** ++ * This function is called when the driver is removed from the kernel ++ * with the rmmod command. The driver unregisters itself with its bus ++ * driver. ++ * ++ */ ++static void __exit dwc_otg_driver_cleanup(void) ++{ ++ printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n"); ++ ++#ifdef LM_INTERFACE ++ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version); ++ lm_driver_unregister(&dwc_otg_driver); ++#elif defined(PCI_INTERFACE) ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); ++ pci_unregister_driver(&dwc_otg_driver); ++#elif defined(PLATFORM_INTERFACE) ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); ++ platform_driver_unregister(&dwc_otg_driver); ++#endif ++ ++ printk(KERN_INFO "%s module removed\n", dwc_driver_name); ++} ++ ++module_exit(dwc_otg_driver_cleanup); ++ ++MODULE_DESCRIPTION(DWC_DRIVER_DESC); ++MODULE_AUTHOR("Synopsys Inc."); ++MODULE_LICENSE("GPL"); ++ ++module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); ++MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); ++module_param_named(opt, dwc_otg_module_params.opt, int, 0444); ++MODULE_PARM_DESC(opt, "OPT Mode"); ++module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); ++MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); ++ ++module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, ++ 0444); ++MODULE_PARM_DESC(dma_desc_enable, ++ "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled"); ++ ++module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, ++ 0444); ++MODULE_PARM_DESC(dma_burst_size, ++ "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); ++module_param_named(speed, dwc_otg_module_params.speed, int, 0444); ++MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); ++module_param_named(host_support_fs_ls_low_power, ++ dwc_otg_module_params.host_support_fs_ls_low_power, int, ++ 0444); ++MODULE_PARM_DESC(host_support_fs_ls_low_power, ++ "Support Low Power w/FS or LS 0=Support 1=Don't Support"); ++module_param_named(host_ls_low_power_phy_clk, ++ dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); ++MODULE_PARM_DESC(host_ls_low_power_phy_clk, ++ "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); ++module_param_named(enable_dynamic_fifo, ++ dwc_otg_module_params.enable_dynamic_fifo, int, 0444); ++MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); ++module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, ++ 0444); ++MODULE_PARM_DESC(data_fifo_size, ++ "Total number of words in the data FIFO memory 32-32768"); ++module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, ++ int, 0444); ++MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); ++module_param_named(dev_nperio_tx_fifo_size, ++ dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(dev_nperio_tx_fifo_size, ++ "Number of words in the non-periodic Tx FIFO 16-32768"); ++module_param_named(dev_perio_tx_fifo_size_1, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_2, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_3, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_4, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_5, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_6, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_7, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_8, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_9, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_10, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_11, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_12, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_13, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_14, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_15, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, ++ int, 0444); ++MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); ++module_param_named(host_nperio_tx_fifo_size, ++ dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_nperio_tx_fifo_size, ++ "Number of words in the non-periodic Tx FIFO 16-32768"); ++module_param_named(host_perio_tx_fifo_size, ++ dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_perio_tx_fifo_size, ++ "Number of words in the host periodic Tx FIFO 16-32768"); ++module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, ++ int, 0444); ++/** @todo Set the max to 512K, modify checks */ ++MODULE_PARM_DESC(max_transfer_size, ++ "The maximum transfer size supported in bytes 2047-65535"); ++module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, ++ int, 0444); ++MODULE_PARM_DESC(max_packet_count, ++ "The maximum number of packets in a transfer 15-511"); ++module_param_named(host_channels, dwc_otg_module_params.host_channels, int, ++ 0444); ++MODULE_PARM_DESC(host_channels, ++ "The number of host channel registers to use 1-16"); ++module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, ++ 0444); ++MODULE_PARM_DESC(dev_endpoints, ++ "The number of endpoints in addition to EP0 available for device mode 1-15"); ++module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); ++MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); ++module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, ++ 0444); ++MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); ++module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); ++MODULE_PARM_DESC(phy_ulpi_ddr, ++ "ULPI at double or single data rate 0=Single 1=Double"); ++module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, ++ int, 0444); ++MODULE_PARM_DESC(phy_ulpi_ext_vbus, ++ "ULPI PHY using internal or external vbus 0=Internal"); ++module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); ++MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); ++module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); ++MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); ++module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); ++MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); ++module_param_named(debug, g_dbg_lvl, int, 0444); ++MODULE_PARM_DESC(debug, ""); ++ ++module_param_named(en_multiple_tx_fifo, ++ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); ++MODULE_PARM_DESC(en_multiple_tx_fifo, ++ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); ++module_param_named(dev_tx_fifo_size_1, ++ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_2, ++ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_3, ++ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_4, ++ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_5, ++ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_6, ++ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_7, ++ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_8, ++ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_9, ++ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_10, ++ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_11, ++ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_12, ++ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_13, ++ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_14, ++ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_15, ++ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); ++ ++module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); ++MODULE_PARM_DESC(thr_ctl, ++ "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); ++module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, ++ 0444); ++MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); ++module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, ++ 0444); ++MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); ++ ++module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444); ++module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444); ++module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444); ++MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled"); ++module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444); ++MODULE_PARM_DESC(ic_usb_cap, ++ "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled"); ++module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, ++ 0444); ++MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio"); ++module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444); ++MODULE_PARM_DESC(power_down, "Power Down Mode"); ++module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444); ++MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control"); ++module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444); ++MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK"); ++module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444); ++MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA"); ++module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444); ++MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support"); ++module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444); ++MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled"); ++module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444); ++MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0"); ++module_param(microframe_schedule, bool, 0444); ++MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); ++ ++module_param(fiq_enable, bool, 0444); ++MODULE_PARM_DESC(fiq_enable, "Enable the FIQ"); ++module_param(nak_holdoff, ushort, 0644); ++MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8"); ++module_param(fiq_fsm_enable, bool, 0444); ++MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask"); ++module_param(fiq_fsm_mask, ushort, 0444); ++MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n" ++ "Bit 0 : Non-periodic split transactions\n" ++ "Bit 1 : Periodic split transactions\n" ++ "Bit 2 : High-speed multi-transfer isochronous\n" ++ "All other bits should be set 0."); ++ ++ ++/** @page "Module Parameters" ++ * ++ * The following parameters may be specified when starting the module. ++ * These parameters define how the DWC_otg controller should be ++ * configured. Parameter values are passed to the CIL initialization ++ * function dwc_otg_cil_init ++ * ++ * Example: modprobe dwc_otg speed=1 otg_cap=1 ++ * ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++*/ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.h +@@ -0,0 +1,86 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $ ++ * $Revision: #19 $ ++ * $Date: 2010/11/15 $ ++ * $Change: 1627671 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_DRIVER_H__ ++#define __DWC_OTG_DRIVER_H__ ++ ++/** @file ++ * This file contains the interface to the Linux driver. ++ */ ++#include "dwc_otg_os_dep.h" ++#include "dwc_otg_core_if.h" ++ ++/* Type declarations */ ++struct dwc_otg_pcd; ++struct dwc_otg_hcd; ++ ++/** ++ * This structure is a wrapper that encapsulates the driver components used to ++ * manage a single DWC_otg controller. ++ */ ++typedef struct dwc_otg_device { ++ /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE ++ * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD ++ * require this. */ ++ struct os_dependent os_dep; ++ ++ /** Pointer to the core interface structure. */ ++ dwc_otg_core_if_t *core_if; ++ ++ /** Pointer to the PCD structure. */ ++ struct dwc_otg_pcd *pcd; ++ ++ /** Pointer to the HCD structure. */ ++ struct dwc_otg_hcd *hcd; ++ ++ /** Flag to indicate whether the common IRQ handler is installed. */ ++ uint8_t common_irq_installed; ++ ++} dwc_otg_device_t; ++ ++/*We must clear S3C24XX_EINTPEND external interrupt register ++ * because after clearing in this register trigerred IRQ from ++ * H/W core in kernel interrupt can be occured again before OTG ++ * handlers clear all IRQ sources of Core registers because of ++ * timing latencies and Low Level IRQ Type. ++ */ ++#ifdef CONFIG_MACH_IPMATE ++#define S3C2410X_CLEAR_EINTPEND() \ ++do { \ ++ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \ ++} while (0) ++#else ++#define S3C2410X_CLEAR_EINTPEND() do { } while (0) ++#endif ++ ++#endif +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c +@@ -0,0 +1,1346 @@ ++/* ++ * dwc_otg_fiq_fsm.c - The finite state machine FIQ ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This FIQ implements functionality that performs split transactions on ++ * the dwc_otg hardware without any outside intervention. A split transaction ++ * is "queued" by nominating a specific host channel to perform the entirety ++ * of a split transaction. This FIQ will then perform the microframe-precise ++ * scheduling required in each phase of the transaction until completion. ++ * ++ * The FIQ functionality is glued into the Synopsys driver via the entry point ++ * in the FSM enqueue function, and at the exit point in handling a HC interrupt ++ * for a FSM-enabled channel. ++ * ++ * NB: Large parts of this implementation have architecture-specific code. ++ * For porting this functionality to other ARM machines, the minimum is required: ++ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed ++ * to the FIQ ++ * - A method of forcing a software generated interrupt from FIQ mode that then ++ * triggers an IRQ entry (with the dwc USB handler called by this IRQ number) ++ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same ++ * processor core - there is no locking between the FIQ and IRQ (aside from ++ * local_fiq_disable) ++ * ++ */ ++ ++#include "dwc_otg_fiq_fsm.h" ++ ++ ++char buffer[1000*16]; ++int wptr; ++void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...) ++{ ++ enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR; ++ va_list args; ++ char text[17]; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) }; ++ ++ if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR) ++ { ++ snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7); ++ va_start(args, fmt); ++ vsnprintf(text+8, 9, fmt, args); ++ va_end(args); ++ ++ memcpy(buffer + wptr, text, 16); ++ wptr = (wptr + 16) % sizeof(buffer); ++ } ++} ++ ++/** ++ * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock ++ * Must be called with local interrupts and FIQ disabled. ++ */ ++#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP) ++inline void fiq_fsm_spin_lock(fiq_lock_t *lock) ++{ ++ unsigned long tmp; ++ uint32_t newval; ++ fiq_lock_t lockval; ++ smp_mb__before_spinlock(); ++ /* Nested locking, yay. If we are on the same CPU as the fiq, then the disable ++ * will be sufficient. If we are on a different CPU, then the lock protects us. */ ++ prefetchw(&lock->slock); ++ asm volatile ( ++ "1: ldrex %0, [%3]\n" ++ " add %1, %0, %4\n" ++ " strex %2, %1, [%3]\n" ++ " teq %2, #0\n" ++ " bne 1b" ++ : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) ++ : "r" (&lock->slock), "I" (1 << 16) ++ : "cc"); ++ ++ while (lockval.tickets.next != lockval.tickets.owner) { ++ wfe(); ++ lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner); ++ } ++ smp_mb(); ++} ++#else ++inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { } ++#endif ++ ++/** ++ * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock ++ */ ++#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP) ++inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) ++{ ++ smp_mb(); ++ lock->tickets.owner++; ++ dsb_sev(); ++} ++#else ++inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { } ++#endif ++ ++/** ++ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction ++ * @channel: channel to re-enable ++ */ ++static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force) ++{ ++ hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) }; ++ ++ hcchar.b.chen = 0; ++ if (st->channel[n].hcchar_copy.b.eptype & 0x1) { ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ /* Hardware bug workaround: update the ssplit index */ ++ if (st->channel[n].hcsplt_copy.b.spltena) ++ st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; ++ ++ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; ++ } ++ ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); ++ hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ hcchar.b.chen = 1; ++ ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); ++ fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force); ++} ++ ++/** ++ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage ++ * @st: Pointer to the channel's state ++ * @n : channel number ++ * ++ * Change host channel registers to perform a complete-split transaction. Being mindful of the ++ * endpoint direction, set control regs up correctly. ++ */ ++static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n) ++{ ++ hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) }; ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ ++ hcsplt.b.compsplt = 1; ++ if (st->channel[n].hcchar_copy.b.epdir == 1) { ++ // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket. ++ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; ++ } else { ++ // If OUT, the CSPLIT result contains handshake only. ++ hctsiz.b.xfersize = 0; ++ } ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++ mb(); ++} ++ ++static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n) ++{ ++ /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */ ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ ++ if (st->channel[n].hcchar_copy.b.epdir == 0) { ++ return st->channel[n].hctsiz_copy.b.xfersize; ++ } else { ++ return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize; ++ } ++ ++} ++ ++ ++/** ++ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT ++ * ++ * Of use only for IN periodic transfers. ++ */ ++static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n) ++{ ++ hcdma_data_t hcdma; ++ int i = st->channel[n].dma_info.index; ++ int len; ++ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; ++ ++ len = fiq_get_xfer_len(st, n); ++ fiq_print(FIQDBG_INT, st, "LEN: %03d", len); ++ st->channel[n].dma_info.slot_len[i] = len; ++ i++; ++ if (i > 6) ++ BUG(); ++ ++ hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0]; ++ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ st->channel[n].dma_info.index = i; ++ return 0; ++} ++ ++/** ++ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ ++ */ ++static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n) ++{ ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; ++ hctsiz.b.pktcnt = 1; ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++} ++ ++/** ++ * fiq_iso_out_advance() - update DMA address and split position bits ++ * for isochronous OUT transactions. ++ * ++ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and ++ * Split-BEGIN states are not handled - this is done when the transaction was queued. ++ * ++ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state. ++ */ ++static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n) ++{ ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ hcdma_data_t hcdma; ++ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; ++ int last = 0; ++ int i = st->channel[n].dma_info.index; ++ ++ fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i); ++ i++; ++ if (i == 4) ++ last = 1; ++ if (st->channel[n].dma_info.slot_len[i+1] == 255) ++ last = 1; ++ ++ /* New DMA address - address of bounce buffer referred to in index */ ++ hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0]; ++ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n)); ++ //hcdma.d32 += st->channel[n].dma_info.slot_len[i]; ++ fiq_print(FIQDBG_INT, st, "LAST: %01d ", last); ++ fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]); ++ hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT); ++ hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ); ++ hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID; ++ /* Set up new packet length */ ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i]; ++ fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32); ++ ++ st->channel[n].dma_info.index++; ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ return last; ++} ++ ++/** ++ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT ++ * ++ * Despite the limitations of the DWC core, we can force a microframe pipeline of ++ * isochronous OUT start-split transactions while waiting for a corresponding other-type ++ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it ++ * is very unlikely that filling the start-split FIFO will cause data loss. ++ * This allows much better interleaving of transactions in an order-independent way- ++ * there is no requirement to prioritise isochronous, just a state-space search has ++ * to be performed on each periodic start-split complete interrupt. ++ */ ++static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n) ++{ ++ int hub_addr = st->channel[n].hub_addr; ++ int port_addr = st->channel[n].port_addr; ++ int i, poked = 0; ++ for (i = 0; i < num_channels; i++) { ++ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ if (st->channel[i].hub_addr == hub_addr && ++ st->channel[i].port_addr == port_addr) { ++ switch (st->channel[i].fsm) { ++ case FIQ_PER_ISO_OUT_PENDING: ++ if (st->channel[i].nrpackets == 1) { ++ st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ fiq_fsm_restart_channel(st, i, 0); ++ poked = 1; ++ break; ++ ++ default: ++ break; ++ } ++ } ++ if (poked) ++ break; ++ } ++ return poked; ++} ++ ++/** ++ * fiq_fsm_tt_in_use() - search for host channels using this TT ++ * @n: Channel to use as reference ++ * ++ */ ++int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n) ++{ ++ int hub_addr = st->channel[n].hub_addr; ++ int port_addr = st->channel[n].port_addr; ++ int i, in_use = 0; ++ for (i = 0; i < num_channels; i++) { ++ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ switch (st->channel[i].fsm) { ++ /* TT is reserved for channels that are in the middle of a periodic ++ * split transaction. ++ */ ++ case FIQ_PER_SSPLIT_STARTED: ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ //case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ case FIQ_PER_ISO_OUT_LAST: ++ if (st->channel[i].hub_addr == hub_addr && ++ st->channel[i].port_addr == port_addr) { ++ in_use = 1; ++ } ++ break; ++ default: ++ break; ++ } ++ if (in_use) ++ break; ++ } ++ return in_use; ++} ++ ++/** ++ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need ++ * to be issued for this IN transaction. ++ * ++ * We cannot tell the inbound PID of a data packet due to hardware limitations. ++ * we need to make an educated guess as to whether we need to queue another CSPLIT ++ * or not. A no-brainer is when we have received enough data to fill the endpoint ++ * size, but for endpoints that give variable-length data then we have to resort ++ * to heuristics. ++ * ++ * We also return whether this is the last CSPLIT to be queued, again based on ++ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions. ++ * Note: requires at least 1 CSPLIT to have been performed prior to being called. ++ */ ++ ++/* ++ * We need some way of guaranteeing if a returned periodic packet of size X ++ * has a DATA0 PID. ++ * The heuristic value of 144 bytes assumes that the received data has maximal ++ * bit-stuffing and the clock frequency of the transmitting device is at the lowest ++ * permissible limit. If the transfer length results in a final packet size ++ * 144 < p <= 188, then an erroneous CSPLIT will be issued. ++ * Also used to ensure that an endpoint will nominally only return a single ++ * complete-split worth of data. ++ */ ++#define DATA0_PID_HEURISTIC 144 ++ ++static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last) ++{ ++ ++ int i; ++ int total_len = 0; ++ int more_needed = 1; ++ struct fiq_channel_state *st = &state->channel[n]; ++ ++ for (i = 0; i < st->dma_info.index; i++) { ++ total_len += st->dma_info.slot_len[i]; ++ } ++ ++ *probably_last = 0; ++ ++ if (st->hcchar_copy.b.eptype == 0x3) { ++ /* ++ * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data ++ * then this is definitely the last CSPLIT. ++ */ ++ *probably_last = 1; ++ } else { ++ /* Isoc IN. This is a bit risky if we are the first transaction: ++ * we may have been held off slightly. */ ++ if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) { ++ more_needed = 0; ++ } ++ /* If in the next uframe we will receive enough data to fill the endpoint, ++ * then only issue 1 more csplit. ++ */ ++ if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC) ++ *probably_last = 1; ++ } ++ ++ if (total_len >= st->hctsiz_copy.b.xfersize || ++ i == 6 || total_len == 0) ++ /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for ++ * a single endpoint. Accepting more would completely break our scheduling mechanism though ++ * - in these extreme cases we will pass through a truncated packet. ++ */ ++ more_needed = 0; ++ ++ return more_needed; ++} ++ ++/** ++ * fiq_fsm_too_late() - Test transaction for lateness ++ * ++ * If a SSPLIT for a large IN transaction is issued too late in a frame, ++ * the hub will disable the port to the device and respond with ERR handshakes. ++ * The hub status endpoint will not reflect this change. ++ * Returns 1 if we will issue a SSPLIT that will result in a device babble. ++ */ ++int notrace fiq_fsm_too_late(struct fiq_state *st, int n) ++{ ++ int uframe; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ uframe = hfnum.b.frnum & 0x7; ++ if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) { ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++ ++/** ++ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline ++ * ++ * Search pending transactions in the start-split pending state and queue them. ++ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4). ++ * Note: we specifically don't do isochronous OUT transactions first because better ++ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT. ++ */ ++static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels) ++{ ++ int n; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ if ((hfnum.b.frnum & 0x7) == 5) ++ return; ++ for (n = 0; n < num_channels; n++) { ++ if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) { ++ /* Check to see if any other transactions are using this TT */ ++ if(!fiq_fsm_tt_in_use(st, num_channels, n)) { ++ if (!fiq_fsm_too_late(st, n)) { ++ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; ++ fiq_print(FIQDBG_INT, st, "NEXTPER "); ++ fiq_fsm_restart_channel(st, n, 0); ++ } else { ++ st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ } ++ break; ++ } ++ } ++ } ++ for (n = 0; n < num_channels; n++) { ++ if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) { ++ if (!fiq_fsm_tt_in_use(st, num_channels, n)) { ++ fiq_print(FIQDBG_INT, st, "NEXTISO "); ++ st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ fiq_fsm_restart_channel(st, n, 0); ++ break; ++ } ++ } ++ } ++} ++ ++/** ++ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data ++ * @state: Pointer to fiq_state ++ * @n: Channel transaction is active on ++ * @hcint: Copy of host channel interrupt register ++ * ++ * Returns 0 if there are no more transactions for this HC to do, 1 ++ * otherwise. ++ */ ++static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint) ++{ ++ struct fiq_channel_state *st = &state->channel[n]; ++ int xfer_len = 0, nrpackets = 0; ++ hcdma_data_t hcdma; ++ fiq_print(FIQDBG_INT, state, "HSISO %02d", n); ++ ++ xfer_len = fiq_get_xfer_len(state, n); ++ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len; ++ ++ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32; ++ ++ st->hs_isoc_info.index++; ++ if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) { ++ return 0; ++ } ++ ++ /* grab the next DMA address offset from the array */ ++ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset; ++ FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ ++ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as ++ * the core needs to be told to send the correct number. Caution: for IN transfers, ++ * this is always set to the maximum size of the endpoint. */ ++ xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length; ++ /* Integer divide in a FIQ: fun. FIXME: make this not suck */ ++ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; ++ if (nrpackets == 0) ++ nrpackets = 1; ++ st->hcchar_copy.b.multicnt = nrpackets; ++ st->hctsiz_copy.b.pktcnt = nrpackets; ++ ++ /* Initial PID also needs to be set */ ++ if (st->hcchar_copy.b.epdir == 0) { ++ st->hctsiz_copy.b.xfersize = xfer_len; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_MDATA; ++ break; ++ } ++ ++ } else { ++ switch (st->hcchar_copy.b.multicnt) { ++ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA1; ++ break; ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA2; ++ break; ++ } ++ } ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32); ++ /* Channel is enabled on hcint handler exit */ ++ fiq_print(FIQDBG_INT, state, "HSISOOUT"); ++ return 1; ++} ++ ++ ++/** ++ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler ++ * @state: Pointer to the state struct passed from banked FIQ mode registers. ++ * @num_channels: set according to the DWC hardware configuration ++ * ++ * The SOF handler in FSM mode has two functions ++ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's ++ * nothing to do ++ * 2. Advance certain FSM states that require either a microframe delay, or a microframe ++ * of holdoff. ++ * ++ * The second part is architecture-specific to mach-bcm2835 - ++ * a sane interrupt controller would have a mask register for ARM interrupt sources ++ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt ++ * number (USB) can be enabled. This means that certain parts of the USB specification ++ * that require "wait a little while, then issue another packet" cannot be fulfilled with ++ * the timing granularity required to achieve optimal throughout. The workaround is to use ++ * the SOF "timer" (125uS) to perform this task. ++ */ ++static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels) ++{ ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) }; ++ int n; ++ int kick_irq = 0; ++ ++ if ((hfnum.b.frnum & 0x7) == 1) { ++ /* We cannot issue csplits for transactions in the last frame past (n+1).1 ++ * Check to see if there are any transactions that are stale. ++ * Boot them out. ++ */ ++ for (n = 0; n < num_channels; n++) { ++ switch (state->channel[n].fsm) { ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_CSPLIT_LAST: ++ /* Check if we are no longer in the same full-speed frame. */ ++ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) < ++ (hfnum.b.frnum & ~0x7)) ++ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ ++ for (n = 0; n < num_channels; n++) { ++ switch (state->channel[n].fsm) { ++ ++ case FIQ_NP_SSPLIT_RETRY: ++ case FIQ_NP_IN_CSPLIT_RETRY: ++ case FIQ_NP_OUT_CSPLIT_RETRY: ++ fiq_fsm_restart_channel(state, n, 0); ++ break; ++ ++ case FIQ_HS_ISOC_SLEEPING: ++ state->channel[n].fsm = FIQ_HS_ISOC_TURBO; ++ fiq_fsm_restart_channel(state, n, 0); ++ break; ++ ++ case FIQ_PER_SSPLIT_QUEUED: ++ if ((hfnum.b.frnum & 0x7) == 5) ++ break; ++ if(!fiq_fsm_tt_in_use(state, num_channels, n)) { ++ if (!fiq_fsm_too_late(state, n)) { ++ fiq_print(FIQDBG_INT, st, "SOF GO %01d", n); ++ fiq_fsm_restart_channel(state, n, 0); ++ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ /* Transaction cannot be started without risking a device babble error */ ++ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ state->haintmsk_saved.b2.chint &= ~(1 << n); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); ++ kick_irq |= 1; ++ } ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_PENDING: ++ /* Ordinarily, this should be poked after the SSPLIT ++ * complete interrupt for a competing transfer on the same ++ * TT. Doesn't happen for aborted transactions though. ++ */ ++ if ((hfnum.b.frnum & 0x7) >= 5) ++ break; ++ if (!fiq_fsm_tt_in_use(state, num_channels, n)) { ++ /* Hardware bug. SOF can sometimes occur after the channel halt interrupt ++ * that caused this. ++ */ ++ fiq_fsm_restart_channel(state, n, 0); ++ fiq_print(FIQDBG_INT, state, "SOF ISOC"); ++ if (state->channel[n].nrpackets == 1) { ++ state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_WAIT: ++ /* we are guaranteed to be in this state if and only if the SSPLIT interrupt ++ * occurred when the bus transaction occurred. The SOF interrupt reversal bug ++ * will utterly bugger this up though. ++ */ ++ if (hfnum.b.frnum != state->channel[n].expected_uframe) { ++ fiq_print(FIQDBG_INT, state, "SOFCS %d ", n); ++ state->channel[n].fsm = FIQ_PER_CSPLIT_POLL; ++ fiq_fsm_restart_channel(state, n, 0); ++ fiq_fsm_start_next_periodic(state, num_channels); ++ ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ case FIQ_DEQUEUE_ISSUED: ++ /* Ugly: we have to force a HCD interrupt. ++ * Poke the mask for the channel in question. ++ * We will take a fake SOF because of this, but ++ * that's OK. ++ */ ++ state->haintmsk_saved.b2.chint &= ~(1 << n); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); ++ kick_irq |= 1; ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++ if (state->kick_np_queues || ++ dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum)) ++ kick_irq |= 1; ++ ++ return !kick_irq; ++} ++ ++ ++/** ++ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler ++ * @state: Pointer to the FIQ state struct ++ * @num_channels: Number of channels as per hardware config ++ * @n: channel for which HAINT(i) was raised ++ * ++ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well. ++ */ ++static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n) ++{ ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hcint_data_t hcint_probe; ++ hcchar_data_t hcchar; ++ int handled = 0; ++ int restart = 0; ++ int last_csplit = 0; ++ int start_next_periodic = 0; ++ struct fiq_channel_state *st = &state->channel[n]; ++ hfnum_data_t hfnum; ++ ++ hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT); ++ hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK); ++ hcint_probe.d32 = hcint.d32 & hcintmsk.d32; ++ ++ if (st->fsm != FIQ_PASSTHROUGH) { ++ fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm); ++ fiq_print(FIQDBG_INT, state, "%08x", hcint.d32); ++ } ++ ++ switch (st->fsm) { ++ ++ case FIQ_PASSTHROUGH: ++ case FIQ_DEQUEUE_ISSUED: ++ /* doesn't belong to us, kick it upstairs */ ++ break; ++ ++ case FIQ_PASSTHROUGH_ERRORSTATE: ++ /* We are here to emulate the error recovery mechanism of the dwc HCD. ++ * Several interrupts are unmasked if a previous transaction failed - it's ++ * death for the FIQ to attempt to handle them as the channel isn't halted. ++ * Emulate what the HCD does in this situation: mask and continue. ++ * The FSM has no other state setup so this has to be handled out-of-band. ++ */ ++ fiq_print(FIQDBG_ERR, state, "ERRST %02d", n); ++ if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) { ++ fiq_print(FIQDBG_ERR, state, "RESET %02d", n); ++ /* In some random cases we can get a NAK interrupt coincident with a Xacterr ++ * interrupt, after the device has disappeared. ++ */ ++ if (!hcint.b.xacterr) ++ st->nr_errors = 0; ++ hcintmsk.b.nak = 0; ++ hcintmsk.b.ack = 0; ++ hcintmsk.b.datatglerr = 0; ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32); ++ return 1; ++ } ++ if (hcint_probe.b.chhltd) { ++ fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n); ++ fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32); ++ return 0; ++ } ++ break; ++ ++ /* Non-periodic state groups */ ++ case FIQ_NP_SSPLIT_STARTED: ++ case FIQ_NP_SSPLIT_RETRY: ++ /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */ ++ if (hcint.b.ack) { ++ /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction ++ * will start shortly. SOF needs to kick the transaction to prevent a NYET flood. ++ */ ++ if(st->hcchar_copy.b.epdir == 1) ++ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; ++ else ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ st->nr_errors = 0; ++ handled = 1; ++ fiq_fsm_setup_csplit(state, n); ++ } else if (hcint.b.nak) { ++ // No buffer space in TT. Retry on a uframe boundary. ++ st->fsm = FIQ_NP_SSPLIT_RETRY; ++ handled = 1; ++ } else if (hcint.b.xacterr) { ++ // The only other one we care about is xacterr. This implies HS bus error - retry. ++ st->nr_errors++; ++ st->fsm = FIQ_NP_SSPLIT_RETRY; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else { ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ handled = 0; ++ restart = 0; ++ } ++ break; ++ ++ case FIQ_NP_IN_CSPLIT_RETRY: ++ /* Received a CSPLIT done interrupt. ++ * Expected Data/NAK/STALL/NYET for IN. ++ */ ++ if (hcint.b.xfercomp) { ++ /* For IN, data is present. */ ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nak) { ++ /* no endpoint data. Punt it upstairs */ ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nyet) { ++ /* CSPLIT NYET - retry on a uframe boundary. */ ++ handled = 1; ++ st->nr_errors = 0; ++ } else if (hcint.b.datatglerr) { ++ /* data toggle errors do not set the xfercomp bit. */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else if (hcint.b.xacterr) { ++ /* HS error. Retry immediate */ ++ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else if (hcint.b.stall || hcint.b.bblerr) { ++ /* A STALL implies either a LS bus error or a genuine STALL. */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else { ++ /* Hardware bug. It's possible in some cases to ++ * get a channel halt with nothing else set when ++ * the response was a NYET. Treat as local 3-strikes retry. ++ */ ++ hcint_data_t hcint_test = hcint; ++ hcint_test.b.chhltd = 0; ++ if (!hcint_test.d32) { ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ } ++ } else { ++ /* Bail out if something unexpected happened */ ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } ++ } ++ break; ++ ++ case FIQ_NP_OUT_CSPLIT_RETRY: ++ /* Received a CSPLIT done interrupt. ++ * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/ ++ if (hcint.b.xfercomp) { ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nak) { ++ // The HCD will implement the holdoff on frame boundaries. ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nyet) { ++ // Hub still processing. ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ handled = 1; ++ st->nr_errors = 0; ++ //restart = 1; ++ } else if (hcint.b.xacterr) { ++ /* HS error. retry immediate */ ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else if (hcint.b.stall) { ++ /* LS bus error or genuine stall */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else { ++ /* ++ * Hardware bug. It's possible in some cases to get a ++ * channel halt with nothing else set when the response was a NYET. ++ * Treat as local 3-strikes retry. ++ */ ++ hcint_data_t hcint_test = hcint; ++ hcint_test.b.chhltd = 0; ++ if (!hcint_test.d32) { ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ } ++ } else { ++ // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it. ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } ++ } ++ break; ++ ++ /* Periodic split states (except isoc out) */ ++ case FIQ_PER_SSPLIT_STARTED: ++ /* Expect an ACK or failure for SSPLIT */ ++ if (hcint.b.ack) { ++ /* ++ * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs. ++ * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1 ++ * point for microframe n-3, the packet will not appear on the bus until microframe n. ++ * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus ++ * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1 ++ * coincident with SOF for n+1. ++ * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place. ++ * These appear to be caused by timing/clock crossing bugs within the core itself. ++ * State machine workaround. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ fiq_fsm_setup_csplit(state, n); ++ /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct ++ * time. If not, then we're in the next SOF. ++ */ ++ if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) { ++ fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n); ++ st->expected_uframe = hfnum.b.frnum; ++ st->fsm = FIQ_PER_CSPLIT_WAIT; ++ } else { ++ fiq_print(FIQDBG_INT, state, "CSPOL %01d", n); ++ /* For isochronous IN endpoints, ++ * we need to hold off if we are expecting a lot of data */ ++ if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) { ++ start_next_periodic = 1; ++ } ++ /* Danger will robinson: we are in a broken state. If our first interrupt after ++ * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable ++ * lag. Unmask the NYET interrupt. ++ */ ++ st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; ++ st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1; ++ restart = 1; ++ } ++ handled = 1; ++ } else if (hcint.b.xacterr) { ++ /* 3-strikes retry is enabled, we have hit our max nr_errors */ ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ start_next_periodic = 1; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ start_next_periodic = 1; ++ } ++ /* We can now queue the next isochronous OUT transaction, if one is pending. */ ++ if(fiq_fsm_tt_next_isoc(state, num_channels, n)) { ++ fiq_print(FIQDBG_INT, state, "NEXTISO "); ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_NYET1: ++ /* First CSPLIT attempt was a NYET. If we get a subsequent NYET, ++ * we are too late and the TT has dropped its CSPLIT fifo. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ start_next_periodic = 1; ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ st->fsm = FIQ_PER_CSPLIT_POLL; ++ st->nr_errors = 0; ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ handled = 1; ++ restart = 1; ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ /* Doh. Data lost. */ ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_BROKEN_NYET1: ++ /* ++ * we got here because our host channel is in the delayed-interrupt ++ * state and we cannot take a NYET interrupt any later than when it ++ * occurred. Disable then re-enable the channel if this happens to force ++ * CSPLITs to occur at the right time. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ fiq_print(FIQDBG_INT, state, "BROK: %01d ", n); ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ start_next_periodic = 1; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ st->fsm = FIQ_PER_CSPLIT_POLL; ++ handled = 1; ++ restart = 1; ++ start_next_periodic = 1; ++ /* Reload HCTSIZ for the next transfer */ ++ fiq_fsm_reload_hctsiz(state, n); ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ start_next_periodic = 1; ++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { ++ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/ ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_POLL: ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ start_next_periodic = 1; ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ handled = 1; ++ restart = 1; ++ /* Reload HCTSIZ for the next transfer */ ++ fiq_fsm_reload_hctsiz(state, n); ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ /* Are we a NYET after the first data packet? */ ++ if (st->nrpackets == 0) { ++ st->fsm = FIQ_PER_CSPLIT_NYET1; ++ handled = 1; ++ restart = 1; ++ } else { ++ /* We got a NYET when polling CSPLITs. Can happen ++ * if our heuristic fails, or if someone disables us ++ * for any significant length of time. ++ */ ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } ++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { ++ /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/ ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ } ++ break; ++ ++ case FIQ_HS_ISOC_TURBO: ++ if (fiq_fsm_update_hs_isoc(state, n, hcint)) { ++ /* more transactions to come */ ++ handled = 1; ++ restart = 1; ++ fiq_print(FIQDBG_INT, state, "HSISO M "); ++ } else { ++ st->fsm = FIQ_HS_ISOC_DONE; ++ fiq_print(FIQDBG_INT, state, "HSISO F "); ++ } ++ break; ++ ++ case FIQ_HS_ISOC_ABORTED: ++ /* This abort is called by the driver rewriting the state mid-transaction ++ * which allows the dequeue mechanism to work more effectively. ++ */ ++ break; ++ ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ if (hcint.b.ack) { ++ if(fiq_iso_out_advance(state, num_channels, n)) { ++ /* last OUT transfer */ ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ /* ++ * Assuming the periodic FIFO in the dwc core ++ * actually does its job properly, we can queue ++ * the next ssplit now and in theory, the wire ++ * transactions will be in-order. ++ */ ++ // No it doesn't. It appears to process requests in host channel order. ++ //start_next_periodic = 1; ++ } ++ handled = 1; ++ restart = 1; ++ } else { ++ /* ++ * Isochronous transactions carry on regardless. Log the error ++ * and continue. ++ */ ++ //explode += 1; ++ st->nr_errors++; ++ if(fiq_iso_out_advance(state, num_channels, n)) { ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ //start_next_periodic = 1; ++ } ++ handled = 1; ++ restart = 1; ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_LAST: ++ if (hcint.b.ack) { ++ /* All done here */ ++ st->fsm = FIQ_PER_ISO_OUT_DONE; ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_DONE; ++ st->nr_errors++; ++ } ++ start_next_periodic = 1; ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ /* SOF kicked us because we overran. */ ++ start_next_periodic = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ if (handled) { ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32); ++ } else { ++ /* Copy the regs into the state so the IRQ knows what to do */ ++ st->hcint_copy.d32 = hcint.d32; ++ } ++ ++ if (restart) { ++ /* Restart always implies handled. */ ++ if (restart == 2) { ++ /* For complete-split INs, the show must go on. ++ * Force a channel restart */ ++ fiq_fsm_restart_channel(state, n, 1); ++ } else { ++ fiq_fsm_restart_channel(state, n, 0); ++ } ++ } ++ if (start_next_periodic) { ++ fiq_fsm_start_next_periodic(state, num_channels); ++ } ++ if (st->fsm != FIQ_PASSTHROUGH) ++ fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm); ++ ++ return handled; ++} ++ ++ ++/** ++ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ ++ * @state: pointer to state struct passed from the banked FIQ mode registers. ++ * @num_channels: set according to the DWC hardware configuration ++ * @dma: pointer to DMA bounce buffers for split transaction slots ++ * ++ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode ++ * inside an EHCI or similar host controller regarding split transactions. The DWC core ++ * interrupts each and every time a split transaction packet is received or sent successfully. ++ * This results in either an interrupt storm when everything is working "properly", or ++ * the interrupt latency of the system in general breaks time-sensitive periodic split ++ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ ++ * solves these problems. ++ * ++ * Return: void ++ */ ++void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels) ++{ ++ gintsts_data_t gintsts, gintsts_handled; ++ gintmsk_data_t gintmsk; ++ //hfnum_data_t hfnum; ++ haint_data_t haint, haint_handled; ++ haintmsk_data_t haintmsk; ++ int kick_irq = 0; ++ ++ gintsts_handled.d32 = 0; ++ haint_handled.d32 = 0; ++ ++ fiq_fsm_spin_lock(&state->lock); ++ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); ++ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); ++ gintsts.d32 &= gintmsk.d32; ++ ++ if (gintsts.b.sofintr) { ++ /* For FSM mode, SOF is required to keep the state machine advance for ++ * certain stages of the periodic pipeline. It's death to mask this ++ * interrupt in that case. ++ */ ++ ++ if (!fiq_fsm_do_sof(state, num_channels)) { ++ /* Kick IRQ once. Queue advancement means that all pending transactions ++ * will get serviced when the IRQ finally executes. ++ */ ++ if (state->gintmsk_saved.b.sofintr == 1) ++ kick_irq |= 1; ++ state->gintmsk_saved.b.sofintr = 0; ++ } ++ gintsts_handled.b.sofintr = 1; ++ } ++ ++ if (gintsts.b.hcintr) { ++ int i; ++ haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT); ++ haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK); ++ haint.d32 &= haintmsk.d32; ++ haint_handled.d32 = 0; ++ for (i=0; ihaintmsk_saved.b2.chint &= ~(1 << i); ++ } else { ++ /* do_hcintr cleaned up after itself, but clear haint */ ++ haint_handled.b2.chint |= (1 << i); ++ } ++ } ++ } ++ ++ if (haint_handled.b2.chint) { ++ FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32); ++ } ++ ++ if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) { ++ /* ++ * This is necessary to avoid multiple retriggers of the MPHI in the case ++ * where interrupts are held off and HCINTs start to pile up. ++ * Only wake up the IRQ if a new interrupt came in, was not handled and was ++ * masked. ++ */ ++ haintmsk.d32 &= state->haintmsk_saved.d32; ++ FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32); ++ kick_irq |= 1; ++ } ++ /* Top-Level interrupt - always handled because it's level-sensitive */ ++ gintsts_handled.b.hcintr = 1; ++ } ++ ++ ++ /* Clear the bits in the saved register that were not handled but were triggered. */ ++ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); ++ ++ /* FIQ didn't handle something - mask has changed - write new mask */ ++ if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) { ++ gintmsk.d32 &= state->gintmsk_saved.d32; ++ gintmsk.b.sofintr = 1; ++ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); ++// fiq_print(FIQDBG_INT, state, "KICKGINT"); ++// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32); ++// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32); ++ kick_irq |= 1; ++ } ++ ++ if (gintsts_handled.d32) { ++ /* Only applies to edge-sensitive bits in GINTSTS */ ++ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); ++ } ++ ++ /* We got an interrupt, didn't handle it. */ ++ if (kick_irq) { ++ state->mphi_int_count++; ++ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); ++ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); ++ ++ } ++ state->fiq_done++; ++ mb(); ++ fiq_fsm_spin_unlock(&state->lock); ++} ++ ++ ++/** ++ * dwc_otg_fiq_nop() - FIQ "lite" ++ * @state: pointer to state struct passed from the banked FIQ mode registers. ++ * ++ * The "nop" handler does not intervene on any interrupts other than SOF. ++ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals ++ * with non-periodic/periodic queues) needs to be kicked. ++ * ++ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second. ++ * ++ * Return: void ++ */ ++void notrace dwc_otg_fiq_nop(struct fiq_state *state) ++{ ++ gintsts_data_t gintsts, gintsts_handled; ++ gintmsk_data_t gintmsk; ++ hfnum_data_t hfnum; ++ ++ fiq_fsm_spin_lock(&state->lock); ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); ++ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); ++ gintsts.d32 &= gintmsk.d32; ++ gintsts_handled.d32 = 0; ++ ++ if (gintsts.b.sofintr) { ++ if (!state->kick_np_queues && ++ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) { ++ /* SOF handled, no work to do, just ACK interrupt */ ++ gintsts_handled.b.sofintr = 1; ++ } else { ++ /* Kick IRQ */ ++ state->gintmsk_saved.b.sofintr = 0; ++ } ++ } ++ ++ /* Reset handled interrupts */ ++ if(gintsts_handled.d32) { ++ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); ++ } ++ ++ /* Clear the bits in the saved register that were not handled but were triggered. */ ++ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); ++ ++ /* We got an interrupt, didn't handle it and want to mask it */ ++ if (~(state->gintmsk_saved.d32)) { ++ state->mphi_int_count++; ++ gintmsk.d32 &= state->gintmsk_saved.d32; ++ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); ++ /* Force a clear before another dummy send */ ++ FIQ_WRITE(state->mphi_regs.intstat, (1<<29)); ++ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); ++ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); ++ ++ } ++ state->fiq_done++; ++ mb(); ++ fiq_fsm_spin_unlock(&state->lock); ++} +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h +@@ -0,0 +1,367 @@ ++/* ++ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This FIQ implements functionality that performs split transactions on ++ * the dwc_otg hardware without any outside intervention. A split transaction ++ * is "queued" by nominating a specific host channel to perform the entirety ++ * of a split transaction. This FIQ will then perform the microframe-precise ++ * scheduling required in each phase of the transaction until completion. ++ * ++ * The FIQ functionality has been surgically implanted into the Synopsys ++ * vendor-provided driver. ++ * ++ */ ++ ++#ifndef DWC_OTG_FIQ_FSM_H_ ++#define DWC_OTG_FIQ_FSM_H_ ++ ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_hcd.h" ++#include ++#include ++#include ++#include ++ ++#if 0 ++#define FLAME_ON(x) \ ++do { \ ++ int gpioreg; \ ++ \ ++ gpioreg = readl(__io_address(0x20200000+0x8)); \ ++ gpioreg &= ~(7 << (x-20)*3); \ ++ gpioreg |= 0x1 << (x-20)*3; \ ++ writel(gpioreg, __io_address(0x20200000+0x8)); \ ++ \ ++ writel(1< 1, SOF wakes up the isochronous FSM */ ++ FIQ_HS_ISOC_SLEEPING = 24, ++ FIQ_HS_ISOC_DONE = 25, ++ FIQ_HS_ISOC_ABORTED = 26, ++ FIQ_DEQUEUE_ISSUED = 30, ++ FIQ_TEST = 32, ++}; ++ ++struct fiq_stack { ++ int magic1; ++ uint8_t stack[2048]; ++ int magic2; ++}; ++ ++ ++/** ++ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel) ++ * @index: Number of slots reported used for IN transactions / number of slots ++ * transmitted for an OUT transaction ++ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused) ++ * ++ * Split transaction transfers can have variable length depending on other bus ++ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore ++ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers ++ * can happen per-frame. ++ */ ++struct fiq_dma_info { ++ u8 index; ++ u8 slot_len[6]; ++}; ++ ++struct __attribute__((packed)) fiq_split_dma_slot { ++ u8 buf[188]; ++}; ++ ++struct fiq_dma_channel { ++ struct __attribute__((packed)) fiq_split_dma_slot index[6]; ++}; ++ ++struct fiq_dma_blob { ++ struct __attribute__((packed)) fiq_dma_channel channel[0]; ++}; ++ ++/** ++ * struct fiq_hs_isoc_info - USB2.0 isochronous data ++ * @iso_frame: Pointer to the array of OTG URB iso_frame_descs. ++ * @nrframes: Total length of iso_frame_desc array ++ * @index: Current index (FIQ-maintained) ++ * ++ */ ++struct fiq_hs_isoc_info { ++ struct dwc_otg_hcd_iso_packet_desc *iso_desc; ++ unsigned int nrframes; ++ unsigned int index; ++}; ++ ++/** ++ * struct fiq_channel_state - FIQ state machine storage ++ * @fsm: Current state of the channel as understood by the FIQ ++ * @nr_errors: Number of transaction errors on this split-transaction ++ * @hub_addr: SSPLIT/CSPLIT destination hub ++ * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub ++ * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For ++ * split-IN, number of CSPLIT data packets that were received. ++ * @hcchar_copy: ++ * @hcsplt_copy: ++ * @hcintmsk_copy: ++ * @hctsiz_copy: Copies of the host channel registers. ++ * For use as scratch, or for returning state. ++ * ++ * The fiq_channel_state is state storage between interrupts for a host channel. The ++ * FSM state is stored here. Members of this structure must only be set up by the ++ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ ++ * has updated the state to either a COMPLETE state group or ABORT state group. ++ */ ++ ++struct fiq_channel_state { ++ enum fiq_fsm_state fsm; ++ unsigned int nr_errors; ++ unsigned int hub_addr; ++ unsigned int port_addr; ++ /* Hardware bug workaround: sometimes channel halt interrupts are ++ * delayed until the next SOF. Keep track of when we expected to get interrupted. */ ++ unsigned int expected_uframe; ++ /* in/out for communicating number of dma buffers used, or number of ISOC to do */ ++ unsigned int nrpackets; ++ struct fiq_dma_info dma_info; ++ struct fiq_hs_isoc_info hs_isoc_info; ++ /* Copies of HC registers - in/out communication from/to IRQ handler ++ * and for ease of channel setup. A bit of mungeing is performed - for ++ * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint. ++ */ ++ hcchar_data_t hcchar_copy; ++ hcsplt_data_t hcsplt_copy; ++ hcint_data_t hcint_copy; ++ hcintmsk_data_t hcintmsk_copy; ++ hctsiz_data_t hctsiz_copy; ++ hcdma_data_t hcdma_copy; ++}; ++ ++/** ++ * struct fiq_state - top-level FIQ state machine storage ++ * @mphi_regs: virtual address of the MPHI peripheral register file ++ * @dwc_regs_base: virtual address of the base of the DWC core register file ++ * @dma_base: physical address for the base of the DMA bounce buffers ++ * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral ++ * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled. ++ * Used for determining which interrupts fired to set off the IRQ handler. ++ * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally. ++ * @np_count: Non-periodic transactions in the active queue ++ * @np_sent: Count of non-periodic transactions that have completed ++ * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism, ++ * this is the next frame on which a SOF interrupt is required. Used to hold off ++ * passing SOF through to the driver until necessary. ++ * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host ++ * channels configured into the core logic. ++ * ++ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub. ++ * It contains top-level state information. ++ */ ++struct fiq_state { ++ fiq_lock_t lock; ++ mphi_regs_t mphi_regs; ++ void *dwc_regs_base; ++ dma_addr_t dma_base; ++ struct fiq_dma_blob *fiq_dmab; ++ void *dummy_send; ++ gintmsk_data_t gintmsk_saved; ++ haintmsk_data_t haintmsk_saved; ++ int mphi_int_count; ++ unsigned int fiq_done; ++ unsigned int kick_np_queues; ++ unsigned int next_sched_frame; ++#ifdef FIQ_DEBUG ++ char * buffer; ++ unsigned int bufsiz; ++#endif ++ struct fiq_channel_state channel[0]; ++}; ++ ++extern void fiq_fsm_spin_lock(fiq_lock_t *lock); ++ ++extern void fiq_fsm_spin_unlock(fiq_lock_t *lock); ++ ++extern int fiq_fsm_too_late(struct fiq_state *st, int n); ++ ++extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n); ++ ++extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels); ++ ++extern void dwc_otg_fiq_nop(struct fiq_state *state); ++ ++#endif /* DWC_OTG_FIQ_FSM_H_ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S +@@ -0,0 +1,80 @@ ++/* ++ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++#include ++#include ++ ++ ++.text ++ ++.global _dwc_otg_fiq_stub_end; ++ ++/** ++ * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow ++ * a C-style function call with arguments from the FIQ banked registers. ++ * r0 = &hcd->fiq_state ++ * r1 = &hcd->num_channels ++ * r2 = &hcd->dma_buffers ++ * Tramples: r0, r1, r2, r4, fp, ip ++ */ ++ ++ENTRY(_dwc_otg_fiq_stub) ++ /* Stash unbanked regs - SP will have been set up for us */ ++ mov ip, sp; ++ stmdb sp!, {r0-r12, lr}; ++#ifdef FIQ_DEBUG ++ // Cycle profiling - read cycle counter at start ++ mrc p15, 0, r5, c15, c12, 1; ++#endif ++ /* r11 = fp, don't trample it */ ++ mov r4, fp; ++ /* set EABI frame size */ ++ sub fp, ip, #512; ++ ++ /* for fiq NOP mode - just need state */ ++ mov r0, r8; ++ /* r9 = num_channels */ ++ mov r1, r9; ++ /* r10 = struct *dma_bufs */ ++// mov r2, r10; ++ ++ /* r4 = &fiq_c_function */ ++ blx r4; ++#ifdef FIQ_DEBUG ++ mrc p15, 0, r4, c15, c12, 1; ++ subs r5, r5, r4; ++ // r5 is now the cycle count time for executing the FIQ. Store it somewhere? ++#endif ++ ldmia sp!, {r0-r12, lr}; ++ subs pc, lr, #4; ++_dwc_otg_fiq_stub_end: ++END(_dwc_otg_fiq_stub) +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +@@ -0,0 +1,4252 @@ ++ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ ++ * $Revision: #104 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871159 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** @file ++ * This file implements HCD Core. All code in this file is portable and doesn't ++ * use any OS specific functions. ++ * Interface provided by HCD Core is defined in ++ * header file. ++ */ ++ ++#include ++#include ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_fiq_fsm.h" ++ ++extern bool microframe_schedule; ++extern uint16_t fiq_fsm_mask, nak_holdoff; ++ ++//#define DEBUG_HOST_CHANNELS ++#ifdef DEBUG_HOST_CHANNELS ++static int last_sel_trans_num_per_scheduled = 0; ++static int last_sel_trans_num_nonper_scheduled = 0; ++static int last_sel_trans_num_avail_hc_at_start = 0; ++static int last_sel_trans_num_avail_hc_at_end = 0; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ ++dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) ++{ ++ return DWC_ALLOC(sizeof(dwc_otg_hcd_t)); ++} ++ ++/** ++ * Connection timeout function. An OTG host is required to display a ++ * message if the device does not connect within 10 seconds. ++ */ ++void dwc_otg_hcd_connect_timeout(void *ptr) ++{ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr); ++ DWC_PRINTF("Connect Timeout\n"); ++ __DWC_ERROR("Device Not Connected/Responding\n"); ++} ++ ++#if defined(DEBUG) ++static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ if (qh->channel != NULL) { ++ dwc_hc_t *hc = qh->channel; ++ dwc_list_link_t *item; ++ dwc_otg_qh_t *qh_item; ++ int num_channels = hcd->core_if->core_params->host_channels; ++ int i; ++ ++ dwc_otg_hc_regs_t *hc_regs; ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ uint32_t hcdma; ++ ++ hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcdma = DWC_READ_REG32(&hc_regs->hcdma); ++ ++ DWC_PRINTF(" Assigned to channel %p:\n", hc); ++ DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, ++ hcsplt.d32); ++ DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, ++ hcdma); ++ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", ++ hc->dev_addr, hc->ep_num, hc->ep_is_in); ++ DWC_PRINTF(" ep_type: %d\n", hc->ep_type); ++ DWC_PRINTF(" max_packet: %d\n", hc->max_packet); ++ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start); ++ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started); ++ DWC_PRINTF(" halt_status: %d\n", hc->halt_status); ++ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff); ++ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len); ++ DWC_PRINTF(" qh: %p\n", hc->qh); ++ DWC_PRINTF(" NP inactive sched:\n"); ++ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) { ++ qh_item = ++ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINTF(" %p\n", qh_item); ++ } ++ DWC_PRINTF(" NP active sched:\n"); ++ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) { ++ qh_item = ++ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINTF(" %p\n", qh_item); ++ } ++ DWC_PRINTF(" Channels: \n"); ++ for (i = 0; i < num_channels; i++) { ++ dwc_hc_t *hc = hcd->hc_ptr_array[i]; ++ DWC_PRINTF(" %2d: %p\n", i, hc); ++ } ++ } ++} ++#else ++#define dump_channel_info(hcd, qh) ++#endif /* DEBUG */ ++ ++/** ++ * Work queue function for starting the HCD when A-Cable is connected. ++ * The hcd_start() must be called in a process context. ++ */ ++static void hcd_start_func(void *_vp) ++{ ++ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd); ++ if (hcd) { ++ hcd->fops->start(hcd); ++ } ++} ++ ++static void del_xfer_timers(dwc_otg_hcd_t * hcd) ++{ ++#ifdef DEBUG ++ int i; ++ int num_channels = hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]); ++ } ++#endif ++} ++ ++static void del_timers(dwc_otg_hcd_t * hcd) ++{ ++ del_xfer_timers(hcd); ++ DWC_TIMER_CANCEL(hcd->conn_timer); ++} ++ ++/** ++ * Processes all the URBs in a single list of QHs. Completes them with ++ * -ESHUTDOWN and frees the QTD. ++ */ ++static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list) ++{ ++ dwc_list_link_t *qh_item, *qh_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ ++ DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) { ++ qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry); ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, ++ &qh->qtd_list, qtd_list_entry) { ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ if (qtd->urb != NULL) { ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_SHUTDOWN); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ } ++ ++ } ++ if(qh->channel) { ++ /* Using hcchar.chen == 1 is not a reliable test. ++ * It is possible that the channel has already halted ++ * but not yet been through the IRQ handler. ++ */ ++ dwc_otg_hc_halt(hcd->core_if, qh->channel, ++ DWC_OTG_HC_XFER_URB_DEQUEUE); ++ if(microframe_schedule) ++ hcd->available_host_channels++; ++ qh->channel = NULL; ++ } ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } ++} ++ ++/** ++ * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic ++ * and periodic schedules. The QTD associated with each URB is removed from ++ * the schedule and freed. This function may be called when a disconnect is ++ * detected or when the HCD is being stopped. ++ */ ++static void kill_all_urbs(dwc_otg_hcd_t * hcd) ++{ ++ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive); ++ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued); ++} ++ ++/** ++ * Start the connection timer. An OTG host is required to display a ++ * message if the device does not connect within 10 seconds. The ++ * timer is deleted if a port connect interrupt occurs before the ++ * timer expires. ++ */ ++static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd) ++{ ++ DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ ); ++} ++ ++/** ++ * HCD Callback function for disconnect of the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_session_start_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); ++ dwc_otg_hcd = p; ++ dwc_otg_hcd_start_connect_timer(dwc_otg_hcd); ++ return 1; ++} ++ ++/** ++ * HCD Callback function for starting the HCD when A-Cable is ++ * connected. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_start_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ dwc_otg_core_if_t *core_if; ++ hprt0_data_t hprt0; ++ ++ core_if = dwc_otg_hcd->core_if; ++ ++ if (core_if->op_state == B_HOST) { ++ /* ++ * Reset the port. During a HNP mode switch the reset ++ * needs to occur within 1ms and have a duration of at ++ * least 50ms. ++ */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtrst = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg, ++ hcd_start_func, dwc_otg_hcd, 50, ++ "start hcd"); ++ ++ return 1; ++} ++ ++/** ++ * HCD Callback function for disconnect of the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_disconnect_cb(void *p) ++{ ++ gintsts_data_t intr; ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ ++ /* ++ * Set status flags for the hub driver. ++ */ ++ dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ dwc_otg_hcd->flags.b.port_connect_status = 0; ++ if(fiq_enable) ++ local_fiq_disable(); ++ /* ++ * Shutdown any transfers in process by clearing the Tx FIFO Empty ++ * interrupt mask and status bits and disabling subsequent host ++ * channel interrupts. ++ */ ++ intr.d32 = 0; ++ intr.b.nptxfempty = 1; ++ intr.b.ptxfempty = 1; ++ intr.b.hcintr = 1; ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, ++ intr.d32, 0); ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, ++ intr.d32, 0); ++ ++ del_timers(dwc_otg_hcd); ++ ++ /* ++ * Turn off the vbus power only if the core has transitioned to device ++ * mode. If still in host mode, need to keep power on to detect a ++ * reconnection. ++ */ ++ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { ++ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ DWC_PRINTF("Disconnect: PortPower off\n"); ++ hprt0.b.prtpwr = 0; ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, ++ hprt0.d32); ++ } ++ ++ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); ++ } ++ ++ /* Respond with an error status to all URBs in the schedule. */ ++ kill_all_urbs(dwc_otg_hcd); ++ ++ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { ++ /* Clean up any host channels that were in use. */ ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ dwc_otg_hc_regs_t *hc_regs; ++ hcchar_data_t hcchar; ++ ++ num_channels = dwc_otg_hcd->core_if->core_params->host_channels; ++ ++ if (!dwc_otg_hcd->core_if->dma_enable) { ++ /* Flush out any channel requests in slave mode. */ ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_otg_hcd->hc_ptr_array[i]; ++ if (DWC_CIRCLEQ_EMPTY_ENTRY ++ (channel, hc_list_entry)) { ++ hc_regs = ++ dwc_otg_hcd->core_if-> ++ host_if->hc_regs[i]; ++ hcchar.d32 = ++ DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chen = 0; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ DWC_WRITE_REG32 ++ (&hc_regs->hcchar, ++ hcchar.d32); ++ } ++ } ++ } ++ } ++ ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_otg_hcd->hc_ptr_array[i]; ++ if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) { ++ hc_regs = ++ dwc_otg_hcd->core_if->host_if->hc_regs[i]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ /* Halt the channel. */ ++ hcchar.b.chdis = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, ++ hcchar.d32); ++ } ++ ++ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, ++ channel); ++ DWC_CIRCLEQ_INSERT_TAIL ++ (&dwc_otg_hcd->free_hc_list, channel, ++ hc_list_entry); ++ /* ++ * Added for Descriptor DMA to prevent channel double cleanup ++ * in release_channel_ddma(). Which called from ep_disable ++ * when device disconnect. ++ */ ++ channel->qh = NULL; ++ } ++ } ++ if(fiq_fsm_enable) { ++ for(i=0; i < 128; i++) { ++ dwc_otg_hcd->hub_port[i] = 0; ++ } ++ } ++ ++ } ++ ++ if(fiq_enable) ++ local_fiq_enable(); ++ ++ if (dwc_otg_hcd->fops->disconnect) { ++ dwc_otg_hcd->fops->disconnect(dwc_otg_hcd); ++ } ++ ++ return 1; ++} ++ ++/** ++ * HCD Callback function for stopping the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_stop_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); ++ dwc_otg_hcd_stop(dwc_otg_hcd); ++ return 1; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * HCD Callback function for sleep of HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int dwc_otg_hcd_sleep_cb(void *p) ++{ ++ dwc_otg_hcd_t *hcd = p; ++ ++ dwc_otg_hcd_free_hc_from_lpm(hcd); ++ ++ return 0; ++} ++#endif ++ ++ ++/** ++ * HCD Callback function for Remote Wakeup. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int dwc_otg_hcd_rem_wakeup_cb(void *p) ++{ ++ dwc_otg_hcd_t *hcd = p; ++ ++ if (hcd->core_if->lx_state == DWC_OTG_L2) { ++ hcd->flags.b.port_suspend_change = 1; ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ else { ++ hcd->flags.b.port_l1_change = 1; ++ } ++#endif ++ return 0; ++} ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ */ ++void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd) ++{ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); ++ ++ /* ++ * The root hub should be disconnected before this function is called. ++ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) ++ * and the QH lists (via ..._hcd_endpoint_disable). ++ */ ++ ++ /* Turn off all host-specific interrupts. */ ++ dwc_otg_disable_host_interrupts(hcd->core_if); ++ ++ /* Turn off the vbus power */ ++ DWC_PRINTF("PortPower off\n"); ++ hprt0.b.prtpwr = 0; ++ DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32); ++ dwc_mdelay(1); ++} ++ ++int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle, ++ int atomic_alloc) ++{ ++ int retval = 0; ++ uint8_t needs_scheduling = 0; ++ dwc_otg_transaction_type_e tr_type; ++ dwc_otg_qtd_t *qtd; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ hprt0_data_t hprt0 = { .d32 = 0 }; ++ ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (NULL == hcd->core_if) { ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n"); ++ /* No longer connected. */ ++ return -DWC_E_INVALID; ++ } ++#endif ++ if (!hcd->flags.b.port_connect_status) { ++ /* No longer connected. */ ++ DWC_ERROR("Not connected\n"); ++ return -DWC_E_NO_DEVICE; ++ } ++ ++ /* Some core configurations cannot support LS traffic on a FS root port */ ++ if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) && ++ (hcd->core_if->hwcfg2.b.fs_phy_type == 1) && ++ (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) { ++ hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0); ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) { ++ return -DWC_E_NO_DEVICE; ++ } ++ } ++ ++ qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc); ++ if (qtd == NULL) { ++ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (qtd->urb == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ if (qtd->urb->priv == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++#endif ++ intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk); ++ if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1; ++ if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) ++ /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */ ++ needs_scheduling = 0; ++ ++ retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc); ++ // creates a new queue in ep_handle if it doesn't exist already ++ if (retval < 0) { ++ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " ++ "Error status %d\n", retval); ++ dwc_otg_hcd_qtd_free(qtd); ++ return retval; ++ } ++ ++ if(needs_scheduling) { ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++ } ++ return retval; ++} ++ ++int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ dwc_otg_qh_t *qh; ++ dwc_otg_qtd_t *urb_qtd; ++ BUG_ON(!hcd); ++ BUG_ON(!dwc_otg_urb); ++ ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ ++ if (hcd == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n"); ++ return -DWC_E_INVALID; ++ } ++ if (dwc_otg_urb == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n"); ++ return -DWC_E_INVALID; ++ } ++ if (dwc_otg_urb->qtd == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n"); ++ return -DWC_E_INVALID; ++ } ++ urb_qtd = dwc_otg_urb->qtd; ++ BUG_ON(!urb_qtd); ++ if (urb_qtd->qh == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n"); ++ return -DWC_E_INVALID; ++ } ++#else ++ urb_qtd = dwc_otg_urb->qtd; ++ BUG_ON(!urb_qtd); ++#endif ++ qh = urb_qtd->qh; ++ BUG_ON(!qh); ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ if (urb_qtd->in_process) { ++ dump_channel_info(hcd, qh); ++ } ++ } ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (hcd->core_if == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n"); ++ return -DWC_E_INVALID; ++ } ++#endif ++ if (urb_qtd->in_process && qh->channel) { ++ /* The QTD is in process (it has been assigned to a channel). */ ++ if (hcd->flags.b.port_connect_status) { ++ int n = qh->channel->hc_num; ++ /* ++ * If still connected (i.e. in host mode), halt the ++ * channel so it can be used for other transfers. If ++ * no longer connected, the host registers can't be ++ * written to halt the channel since the core is in ++ * device mode. ++ */ ++ /* In FIQ FSM mode, we need to shut down carefully. ++ * The FIQ may attempt to restart a disabled channel */ ++ if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) { ++ qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE; ++ qh->channel->halt_pending = 1; ++ hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED; ++ } else { ++ dwc_otg_hc_halt(hcd->core_if, qh->channel, ++ DWC_OTG_HC_XFER_URB_DEQUEUE); ++ } ++ } ++ } ++ ++ /* ++ * Free the QTD and clean up the associated QH. Leave the QH in the ++ * schedule if it has any remaining QTDs. ++ */ ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - " ++ "delete %sQueue handler\n", ++ hcd->core_if->dma_desc_enable?"DMA ":""); ++ if (!hcd->core_if->dma_desc_enable) { ++ uint8_t b = urb_qtd->in_process; ++ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); ++ if (b) { ++ dwc_otg_hcd_qh_deactivate(hcd, qh, 0); ++ qh->channel = NULL; ++ } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } ++ } else { ++ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); ++ } ++ return 0; ++} ++ ++int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, ++ int retry) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ int retval = 0; ++ dwc_irqflags_t flags; ++ ++ if (retry < 0) { ++ retval = -DWC_E_INVALID; ++ goto done; ++ } ++ ++ if (!qh) { ++ retval = -DWC_E_INVALID; ++ goto done; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ ++ while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) { ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ retry--; ++ dwc_msleep(5); ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ } ++ ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ /* ++ * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove ++ * and qh_free to prevent stack dump on DWC_DMA_FREE() with ++ * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() ++ * and dwc_otg_hcd_frame_list_alloc(). ++ */ ++ dwc_otg_hcd_qh_free(hcd, qh); ++ ++done: ++ return retval; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ int retval = 0; ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ if (!qh) ++ return -DWC_E_INVALID; ++ ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ return retval; ++} ++#endif ++ ++/** ++ * HCD Callback structure for handling mode switching. ++ */ ++static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { ++ .start = dwc_otg_hcd_start_cb, ++ .stop = dwc_otg_hcd_stop_cb, ++ .disconnect = dwc_otg_hcd_disconnect_cb, ++ .session_start = dwc_otg_hcd_session_start_cb, ++ .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb, ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ .sleep = dwc_otg_hcd_sleep_cb, ++#endif ++ .p = 0, ++}; ++ ++/** ++ * Reset tasklet function ++ */ ++static void reset_tasklet_func(void *data) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data; ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ hprt0_data_t hprt0; ++ ++ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtrst = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_mdelay(60); ++ ++ hprt0.b.prtrst = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_otg_hcd->flags.b.port_reset_change = 1; ++} ++ ++static void completion_tasklet_func(void *ptr) ++{ ++ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr; ++ struct urb *urb; ++ urb_tq_entry_t *item; ++ dwc_irqflags_t flags; ++ ++ /* This could just be spin_lock_irq */ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) { ++ item = DWC_TAILQ_FIRST(&hcd->completed_urb_list); ++ urb = item->urb; ++ DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item, ++ urb_tq_entries); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ DWC_FREE(item); ++ ++ usb_hcd_giveback_urb(hcd->priv, urb, urb->status); ++ ++ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ return; ++} ++ ++static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list) ++{ ++ dwc_list_link_t *item; ++ dwc_otg_qh_t *qh; ++ dwc_irqflags_t flags; ++ ++ if (!qh_list->next) { ++ /* The list hasn't been initialized yet. */ ++ return; ++ } ++ /* ++ * Hold spinlock here. Not needed in that case if bellow ++ * function is being called from ISR ++ */ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ /* Ensure there are no QTDs or URBs left. */ ++ kill_urbs_in_qh_list(hcd, qh_list); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ ++ DWC_LIST_FOREACH(item, qh_list) { ++ qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ dwc_otg_hcd_qh_remove_and_free(hcd, qh); ++ } ++} ++ ++/** ++ * Exit from Hibernation if Host did not detect SRP from connected SRP capable ++ * Device during SRP time by host power up. ++ */ ++void dwc_otg_hcd_power_up(void *ptr) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Enable VBUS */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++} ++ ++void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num) ++{ ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ struct fiq_dma_blob *blob = hcd->fiq_dmab; ++ int i; ++ ++ st->fsm = FIQ_PASSTHROUGH; ++ st->hcchar_copy.d32 = 0; ++ st->hcsplt_copy.d32 = 0; ++ st->hcint_copy.d32 = 0; ++ st->hcintmsk_copy.d32 = 0; ++ st->hctsiz_copy.d32 = 0; ++ st->hcdma_copy.d32 = 0; ++ st->nr_errors = 0; ++ st->hub_addr = 0; ++ st->port_addr = 0; ++ st->expected_uframe = 0; ++ st->nrpackets = 0; ++ st->dma_info.index = 0; ++ for (i = 0; i < 6; i++) ++ st->dma_info.slot_len[i] = 255; ++ st->hs_isoc_info.index = 0; ++ st->hs_isoc_info.iso_desc = NULL; ++ st->hs_isoc_info.nrframes = 0; ++ ++ DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128); ++} ++ ++/** ++ * Frees secondary storage associated with the dwc_otg_hcd structure contained ++ * in the struct usb_hcd field. ++ */ ++static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int i; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); ++ ++ del_timers(dwc_otg_hcd); ++ ++ /* Free memory for QH/QTD lists */ ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); ++ ++ /* Free memory for the host channels. */ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; ++ ++#ifdef DEBUG ++ if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) { ++ DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]); ++ } ++#endif ++ if (hc != NULL) { ++ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", ++ i, hc); ++ DWC_FREE(hc); ++ } ++ } ++ ++ if (dwc_otg_hcd->core_if->dma_enable) { ++ if (dwc_otg_hcd->status_buf_dma) { ++ DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ dwc_otg_hcd->status_buf, ++ dwc_otg_hcd->status_buf_dma); ++ } ++ } else if (dwc_otg_hcd->status_buf != NULL) { ++ DWC_FREE(dwc_otg_hcd->status_buf); ++ } ++ DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock); ++ DWC_SPINLOCK_FREE(dwc_otg_hcd->lock); ++ /* Set core_if's lock pointer to NULL */ ++ dwc_otg_hcd->core_if->lock = NULL; ++ ++ DWC_TIMER_FREE(dwc_otg_hcd->conn_timer); ++ DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet); ++ DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet); ++ DWC_FREE(dwc_otg_hcd->fiq_state); ++ ++#ifdef DWC_DEV_SRPCAP ++ if (dwc_otg_hcd->core_if->power_down == 2 && ++ dwc_otg_hcd->core_if->pwron_timer) { ++ DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer); ++ } ++#endif ++ DWC_FREE(dwc_otg_hcd); ++} ++ ++int init_hcd_usecs(dwc_otg_hcd_t *_hcd); ++ ++int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock); ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock); ++#else ++ hcd->lock = DWC_SPINLOCK_ALLOC(); ++ hcd->channel_lock = DWC_SPINLOCK_ALLOC(); ++#endif ++ DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", ++ hcd, core_if); ++ if (!hcd->lock) { ++ DWC_ERROR("Could not allocate lock for pcd"); ++ DWC_FREE(hcd); ++ retval = -DWC_E_NO_MEMORY; ++ goto out; ++ } ++ hcd->core_if = core_if; ++ ++ /* Register the HCD CIL Callbacks */ ++ dwc_otg_cil_register_hcd_callbacks(hcd->core_if, ++ &hcd_cil_callbacks, hcd); ++ ++ /* Initialize the non-periodic schedule. */ ++ DWC_LIST_INIT(&hcd->non_periodic_sched_inactive); ++ DWC_LIST_INIT(&hcd->non_periodic_sched_active); ++ ++ /* Initialize the periodic schedule. */ ++ DWC_LIST_INIT(&hcd->periodic_sched_inactive); ++ DWC_LIST_INIT(&hcd->periodic_sched_ready); ++ DWC_LIST_INIT(&hcd->periodic_sched_assigned); ++ DWC_LIST_INIT(&hcd->periodic_sched_queued); ++ DWC_TAILQ_INIT(&hcd->completed_urb_list); ++ /* ++ * Create a host channel descriptor for each host channel implemented ++ * in the controller. Initialize the channel descriptor array. ++ */ ++ DWC_CIRCLEQ_INIT(&hcd->free_hc_list); ++ num_channels = hcd->core_if->core_params->host_channels; ++ DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array)); ++ for (i = 0; i < num_channels; i++) { ++ channel = DWC_ALLOC(sizeof(dwc_hc_t)); ++ if (channel == NULL) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: host channel allocation failed\n", ++ __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ channel->hc_num = i; ++ hcd->hc_ptr_array[i] = channel; ++#ifdef DEBUG ++ hcd->core_if->hc_xfer_timer[i] = ++ DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout, ++ &hcd->core_if->hc_xfer_info[i]); ++#endif ++ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, ++ channel); ++ } ++ ++ if (fiq_enable) { ++ hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)); ++ if (!hcd->fiq_state) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels))); ++ ++ for (i = 0; i < num_channels; i++) { ++ hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH; ++ } ++ hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16); ++ ++ hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack)); ++ if (!hcd->fiq_stack) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ hcd->fiq_stack->magic1 = 0xDEADBEEF; ++ hcd->fiq_stack->magic2 = 0xD00DFEED; ++ hcd->fiq_state->gintmsk_saved.d32 = ~0; ++ hcd->fiq_state->haintmsk_saved.b2.chint = ~0; ++ ++ /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools ++ * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels) ++ * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some ++ * moderately readable array casts. ++ */ ++ hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base); ++ DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d", ++ (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base, ++ sizeof(struct fiq_dma_channel) * num_channels); ++ ++ DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024); ++ ++ /* pointer for debug in fiq_print */ ++ hcd->fiq_state->fiq_dmab = hcd->fiq_dmab; ++ if (fiq_fsm_enable) { ++ int i; ++ for (i=0; i < hcd->core_if->core_params->host_channels; i++) { ++ dwc_otg_cleanup_fiq_channel(hcd, i); ++ } ++ DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s", ++ (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "", ++ (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "", ++ (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "", ++ (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : ""); ++ } ++ } ++ ++ /* Initialize the Connection timeout timer. */ ++ hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", ++ dwc_otg_hcd_connect_timeout, 0); ++ ++ printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled"); ++ if (microframe_schedule) ++ init_hcd_usecs(hcd); ++ ++ /* Initialize reset tasklet. */ ++ hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd); ++ ++ hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet", ++ completion_tasklet_func, hcd); ++#ifdef DWC_DEV_SRPCAP ++ if (hcd->core_if->power_down == 2) { ++ /* Initialize Power on timer for Host power up in case hibernation */ ++ hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER", ++ dwc_otg_hcd_power_up, core_if); ++ } ++#endif ++ ++ /* ++ * Allocate space for storing data on status transactions. Normally no ++ * data is sent, but this space acts as a bit bucket. This must be ++ * done after usb_add_hcd since that function allocates the DMA buffer ++ * pool. ++ */ ++ if (hcd->core_if->dma_enable) { ++ hcd->status_buf = ++ DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ &hcd->status_buf_dma); ++ } else { ++ hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE); ++ } ++ if (!hcd->status_buf) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: status_buf allocation failed\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ ++ hcd->otg_port = 1; ++ hcd->frame_list = NULL; ++ hcd->frame_list_dma = 0; ++ hcd->periodic_qh_count = 0; ++ ++ DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port)); ++#ifdef FIQ_DEBUG ++ DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc)); ++#endif ++ ++out: ++ return retval; ++} ++ ++void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd) ++{ ++ /* Turn off all host-specific interrupts. */ ++ dwc_otg_disable_host_interrupts(hcd->core_if); ++ ++ dwc_otg_hcd_free(hcd); ++} ++ ++/** ++ * Initializes dynamic portions of the DWC_otg HCD state. ++ */ ++static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd) ++{ ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ dwc_hc_t *channel_tmp; ++ ++ hcd->flags.d32 = 0; ++ ++ hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active; ++ if (!microframe_schedule) { ++ hcd->non_periodic_channels = 0; ++ hcd->periodic_channels = 0; ++ } else { ++ hcd->available_host_channels = hcd->core_if->core_params->host_channels; ++ } ++ /* ++ * Put all channels in the free channel list and clean up channel ++ * states. ++ */ ++ DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp, ++ &hcd->free_hc_list, hc_list_entry) { ++ DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry); ++ } ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ channel = hcd->hc_ptr_array[i]; ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel, ++ hc_list_entry); ++ dwc_otg_hc_cleanup(hcd->core_if, channel); ++ } ++ ++ /* Initialize the DWC core for host mode operation. */ ++ dwc_otg_core_host_init(hcd->core_if); ++ ++ /* Set core_if's lock pointer to the hcd->lock */ ++ hcd->core_if->lock = hcd->lock; ++} ++ ++/** ++ * Assigns transactions from a QTD to a free host channel and initializes the ++ * host channel to perform the transactions. The host channel is removed from ++ * the free list. ++ * ++ * @param hcd The HCD state structure. ++ * @param qh Transactions from the first QTD for this QH are selected and ++ * assigned to a free host channel. ++ */ ++static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ dwc_hc_t *hc; ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_hcd_urb_t *urb; ++ void* ptr = NULL; ++ uint32_t intr_enable; ++ unsigned long flags; ++ gintmsk_data_t gintmsk = { .d32 = 0, }; ++ ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ ++ urb = qtd->urb; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length); ++ ++ if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) ++ urb->actual_length = urb->length; ++ ++ ++ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); ++ ++ /* Remove the host channel from the free list. */ ++ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); ++ ++ qh->channel = hc; ++ ++ qtd->in_process = 1; ++ ++ /* ++ * Use usb_pipedevice to determine device address. This address is ++ * 0 before the SET_ADDRESS command and the correct address afterward. ++ */ ++ hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info); ++ hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info); ++ hc->speed = qh->dev_speed; ++ hc->max_packet = dwc_max_packet(qh->maxp); ++ ++ hc->xfer_started = 0; ++ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; ++ hc->error_state = (qtd->error_count > 0); ++ hc->halt_on_queue = 0; ++ hc->halt_pending = 0; ++ hc->requests = 0; ++ ++ /* ++ * The following values may be modified in the transfer type section ++ * below. The xfer_len value may be reduced when the transfer is ++ * started to accommodate the max widths of the XferSize and PktCnt ++ * fields in the HCTSIZn register. ++ */ ++ ++ hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0); ++ if (hc->ep_is_in) { ++ hc->do_ping = 0; ++ } else { ++ hc->do_ping = qh->ping_state; ++ } ++ ++ hc->data_pid_start = qh->data_toggle; ++ hc->multi_count = 1; ++ ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length; ++ ++ /* For non-dword aligned case */ ++ if (((unsigned long)hc->xfer_buff & 0x3) ++ && !hcd->core_if->dma_desc_enable) { ++ ptr = (uint8_t *) urb->buf + urb->actual_length; ++ } ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length; ++ } ++ hc->xfer_len = urb->length - urb->actual_length; ++ hc->xfer_count = 0; ++ ++ /* ++ * Set the split attributes ++ */ ++ hc->do_split = 0; ++ if (qh->do_split) { ++ uint32_t hub_addr, port_addr; ++ hc->do_split = 1; ++ hc->xact_pos = qtd->isoc_split_pos; ++ /* We don't need to do complete splits anymore */ ++// if(fiq_fsm_enable) ++ if (0) ++ hc->complete_split = qtd->complete_split = 0; ++ else ++ hc->complete_split = qtd->complete_split; ++ ++ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr); ++ hc->hub_addr = (uint8_t) hub_addr; ++ hc->port_addr = (uint8_t) port_addr; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { ++ case UE_CONTROL: ++ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; ++ switch (qtd->control_phase) { ++ case DWC_OTG_CONTROL_SETUP: ++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); ++ hc->do_ping = 0; ++ hc->ep_is_in = 0; ++ hc->data_pid_start = DWC_OTG_HC_PID_SETUP; ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->setup_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->setup_packet; ++ } ++ hc->xfer_len = 8; ++ ptr = NULL; ++ break; ++ case DWC_OTG_CONTROL_DATA: ++ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); ++ hc->data_pid_start = qtd->data_toggle; ++ break; ++ case DWC_OTG_CONTROL_STATUS: ++ /* ++ * Direction is opposite of data direction or IN if no ++ * data. ++ */ ++ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); ++ if (urb->length == 0) { ++ hc->ep_is_in = 1; ++ } else { ++ hc->ep_is_in = ++ dwc_otg_hcd_is_pipe_out(&urb->pipe_info); ++ } ++ if (hc->ep_is_in) { ++ hc->do_ping = 0; ++ } ++ ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; ++ ++ hc->xfer_len = 0; ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) hcd->status_buf_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) hcd->status_buf; ++ } ++ ptr = NULL; ++ break; ++ } ++ break; ++ case UE_BULK: ++ hc->ep_type = DWC_OTG_EP_TYPE_BULK; ++ break; ++ case UE_INTERRUPT: ++ hc->ep_type = DWC_OTG_EP_TYPE_INTR; ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ hc->ep_type = DWC_OTG_EP_TYPE_ISOC; ++ ++ if (hcd->core_if->dma_desc_enable) ++ break; ++ ++ frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; ++ ++ frame_desc->status = 0; ++ ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->buf; ++ } ++ hc->xfer_buff += ++ frame_desc->offset + qtd->isoc_split_offset; ++ hc->xfer_len = ++ frame_desc->length - qtd->isoc_split_offset; ++ ++ /* For non-dword aligned buffers */ ++ if (((unsigned long)hc->xfer_buff & 0x3) ++ && hcd->core_if->dma_enable) { ++ ptr = ++ (uint8_t *) urb->buf + frame_desc->offset + ++ qtd->isoc_split_offset; ++ } else ++ ptr = NULL; ++ ++ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { ++ if (hc->xfer_len <= 188) { ++ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ } else { ++ hc->xact_pos = ++ DWC_HCSPLIT_XACTPOS_BEGIN; ++ } ++ } ++ } ++ break; ++ } ++ /* non DWORD-aligned buffer case */ ++ if (ptr) { ++ uint32_t buf_size; ++ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ buf_size = hcd->core_if->core_params->max_transfer_size; ++ } else { ++ buf_size = 4096; ++ } ++ if (!qh->dw_align_buf) { ++ qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size, ++ &qh->dw_align_buf_dma); ++ if (!qh->dw_align_buf) { ++ DWC_ERROR ++ ("%s: Failed to allocate memory to handle " ++ "non-dword aligned buffer case\n", ++ __func__); ++ return; ++ } ++ } ++ if (!hc->ep_is_in) { ++ dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len); ++ } ++ hc->align_buff = qh->dw_align_buf_dma; ++ } else { ++ hc->align_buff = 0; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This value may be modified when the transfer is started to ++ * reflect the actual transfer length. ++ */ ++ hc->multi_count = dwc_hb_mult(qh->maxp); ++ } ++ ++ if (hcd->core_if->dma_desc_enable) ++ hc->desc_list_addr = qh->desc_list_dma; ++ ++ dwc_otg_hc_init(hcd->core_if, hc); ++ ++ local_irq_save(flags); ++ ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ } ++ ++ /* Enable the top level host channel interrupt. */ ++ intr_enable = (1 << hc->hc_num); ++ DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable); ++ ++ /* Make sure host channel interrupts are enabled. */ ++ gintmsk.b.hcintr = 1; ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ ++ if (fiq_enable) { ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } ++ ++ local_irq_restore(flags); ++ hc->qh = qh; ++} ++ ++ ++/** ++ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ ++ * @qh: pointer to the endpoint's queue head ++ * ++ * Transaction start/end control flow is grafted onto the existing dwc_otg ++ * mechanisms, to avoid spaghettifying the functions more than they already are. ++ * This function's eligibility check is altered by debug parameter. ++ * ++ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction. ++ */ ++ ++int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh) ++{ ++ if (qh->do_split) { ++ switch (qh->ep_type) { ++ case UE_CONTROL: ++ case UE_BULK: ++ if (fiq_fsm_mask & (1 << 0)) ++ return 1; ++ break; ++ case UE_INTERRUPT: ++ case UE_ISOCHRONOUS: ++ if (fiq_fsm_mask & (1 << 1)) ++ return 1; ++ break; ++ default: ++ break; ++ } ++ } else if (qh->ep_type == UE_ISOCHRONOUS) { ++ if (fiq_fsm_mask & (1 << 2)) { ++ /* HS ISOCH support. We test for compatibility: ++ * - DWORD aligned buffers ++ * - Must be at least 2 transfers (otherwise pointless to use the FIQ) ++ * If yes, then the fsm enqueue function will handle the state machine setup. ++ */ ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs; ++ int nr_iso_frames = urb->packet_count; ++ int i; ++ uint32_t ptr; ++ ++ if (nr_iso_frames < 2) ++ return 0; ++ for (i = 0; i < nr_iso_frames; i++) { ++ ptr = urb->dma + iso_descs[i]->offset; ++ if (ptr & 0x3) { ++ printk_ratelimited("%s: Non-Dword aligned isochronous frame offset." ++ " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n", ++ __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num); ++ return 0; ++ } ++ } ++ return 1; ++ } ++ } ++ return 0; ++} ++ ++/** ++ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers ++ * @hcd: Pointer to the dwc_otg_hcd struct ++ * @qh: Pointer to the endpoint's queue head ++ * ++ * Periodic split transactions are transmitted modulo 188 bytes. ++ * This necessitates slicing data up into buckets for isochronous out ++ * and fixing up the DMA address for all IN transfers. ++ * ++ * Returns 1 if the DMA bounce buffers have been used, 0 if the default ++ * HC buffer has been used. ++ */ ++int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh) ++ { ++ int frame_length, i = 0; ++ uint8_t *ptr = NULL; ++ dwc_hc_t *hc = qh->channel; ++ struct fiq_dma_blob *blob; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ for (i = 0; i < 6; i++) { ++ st->dma_info.slot_len[i] = 255; ++ } ++ st->dma_info.index = 0; ++ i = 0; ++ if (hc->ep_is_in) { ++ /* ++ * Set dma_regs to bounce buffer. FIQ will update the ++ * state depending on transaction progress. ++ */ ++ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; ++ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; ++ /* Calculate the max number of CSPLITS such that the FIQ can time out ++ * a transaction if it fails. ++ */ ++ frame_length = st->hcchar_copy.b.mps; ++ do { ++ i++; ++ frame_length -= 188; ++ } while (frame_length >= 0); ++ st->nrpackets = i; ++ return 1; ++ } else { ++ if (qh->ep_type == UE_ISOCHRONOUS) { ++ ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ frame_length = frame_desc->length; ++ ++ /* Virtual address for bounce buffers */ ++ blob = hcd->fiq_dmab; ++ ++ ptr = qtd->urb->buf + frame_desc->offset; ++ if (frame_length == 0) { ++ /* ++ * for isochronous transactions, we must still transmit a packet ++ * even if the length is zero. ++ */ ++ st->dma_info.slot_len[0] = 0; ++ st->nrpackets = 1; ++ } else { ++ do { ++ if (frame_length <= 188) { ++ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length); ++ st->dma_info.slot_len[i] = frame_length; ++ ptr += frame_length; ++ } else { ++ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188); ++ st->dma_info.slot_len[i] = 188; ++ ptr += 188; ++ } ++ i++; ++ frame_length -= 188; ++ } while (frame_length > 0); ++ st->nrpackets = i; ++ } ++ ptr = qtd->urb->buf + frame_desc->offset; ++ /* Point the HC at the DMA address of the bounce buffers */ ++ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; ++ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; ++ ++ /* fixup xfersize to the actual packet size */ ++ st->hctsiz_copy.b.pid = 0; ++ st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0]; ++ return 1; ++ } else { ++ /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */ ++ return 0; ++ } ++ } ++} ++ ++/* ++ * Pushing a periodic request into the queue near the EOF1 point ++ * in a microframe causes erroneous behaviour (frmovrun) interrupt. ++ * Usually, the request goes out on the bus causing a transfer but ++ * the core does not transfer the data to memory. ++ * This guard interval (in number of 60MHz clocks) is required which ++ * must cater for CPU latency between reading the value and enabling ++ * the channel. ++ */ ++#define PERIODIC_FRREM_BACKOFF 1000 ++ ++int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) ++{ ++ dwc_hc_t *hc = qh->channel; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ int frame; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; ++ int xfer_len, nrpackets; ++ hcdma_data_t hcdma; ++ hfnum_data_t hfnum; ++ ++ if (st->fsm != FIQ_PASSTHROUGH) ++ return 0; ++ ++ st->nr_errors = 0; ++ ++ st->hcchar_copy.d32 = 0; ++ st->hcchar_copy.b.mps = hc->max_packet; ++ st->hcchar_copy.b.epdir = hc->ep_is_in; ++ st->hcchar_copy.b.devaddr = hc->dev_addr; ++ st->hcchar_copy.b.epnum = hc->ep_num; ++ st->hcchar_copy.b.eptype = hc->ep_type; ++ ++ st->hcintmsk_copy.b.chhltd = 1; ++ ++ frame = dwc_otg_hcd_get_frame_number(hcd); ++ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; ++ ++ st->hcchar_copy.b.lspddev = 0; ++ /* Enable the channel later as a final register write. */ ++ ++ st->hcsplt_copy.d32 = 0; ++ ++ st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs; ++ st->hs_isoc_info.nrframes = qtd->urb->packet_count; ++ /* grab the next DMA address offset from the array */ ++ st->hcdma_copy.d32 = qtd->urb->dma; ++ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset; ++ ++ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as ++ * the core needs to be told to send the correct number. Caution: for IN transfers, ++ * this is always set to the maximum size of the endpoint. */ ++ xfer_len = st->hs_isoc_info.iso_desc[0].length; ++ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; ++ if (nrpackets == 0) ++ nrpackets = 1; ++ st->hcchar_copy.b.multicnt = nrpackets; ++ st->hctsiz_copy.b.pktcnt = nrpackets; ++ ++ /* Initial PID also needs to be set */ ++ if (st->hcchar_copy.b.epdir == 0) { ++ st->hctsiz_copy.b.xfersize = xfer_len; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_MDATA; ++ break; ++ } ++ ++ } else { ++ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA1; ++ break; ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA2; ++ break; ++ } ++ } ++ ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); ++ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); ++ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { ++ /* Prevent queueing near EOF1. Bad things happen if a periodic ++ * split transaction is queued very close to EOF. ++ */ ++ st->fsm = FIQ_HS_ISOC_SLEEPING; ++ } else { ++ st->fsm = FIQ_HS_ISOC_TURBO; ++ st->hcchar_copy.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ } ++ mb(); ++ st->hcchar_copy.b.chen = 0; ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ return 0; ++} ++ ++ ++/** ++ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state ++ * @hcd: Pointer to the dwc_otg_hcd struct ++ * @qh: Pointer to the endpoint's queue head ++ * ++ * This overrides the dwc_otg driver's normal method of queueing a transaction. ++ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup ++ * for the nominated host channel. ++ * ++ * For periodic transfers, it also peeks at the FIQ state to see if an immediate ++ * start is possible. If not, then the FIQ is left to start the transfer. ++ */ ++int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) ++{ ++ int start_immediate = 1, i; ++ hfnum_data_t hfnum; ++ dwc_hc_t *hc = qh->channel; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */ ++ int hub_addr, port_addr, frame, uframe; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; ++ ++ if (st->fsm != FIQ_PASSTHROUGH) ++ return 0; ++ st->nr_errors = 0; ++ ++ st->hcchar_copy.d32 = 0; ++ st->hcchar_copy.b.mps = hc->max_packet; ++ st->hcchar_copy.b.epdir = hc->ep_is_in; ++ st->hcchar_copy.b.devaddr = hc->dev_addr; ++ st->hcchar_copy.b.epnum = hc->ep_num; ++ st->hcchar_copy.b.eptype = hc->ep_type; ++ if (hc->ep_type & 0x1) { ++ if (hc->ep_is_in) ++ st->hcchar_copy.b.multicnt = 3; ++ else ++ /* Docs say set this to 1, but driver sets to 0! */ ++ st->hcchar_copy.b.multicnt = 0; ++ } else { ++ st->hcchar_copy.b.multicnt = 1; ++ st->hcchar_copy.b.oddfrm = 0; ++ } ++ st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0; ++ /* Enable the channel later as a final register write. */ ++ ++ st->hcsplt_copy.d32 = 0; ++ if(qh->do_split) { ++ hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); ++ st->hcsplt_copy.b.compsplt = 0; ++ st->hcsplt_copy.b.spltena = 1; ++ // XACTPOS is for isoc-out only but needs initialising anyway. ++ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL; ++ if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) { ++ /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL. ++ * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ ++ * will update as necessary. ++ */ ++ if (hc->xfer_len > 188) { ++ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN; ++ } ++ } ++ st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr; ++ st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr; ++ st->hub_addr = hub_addr; ++ st->port_addr = port_addr; ++ } ++ ++ st->hctsiz_copy.d32 = 0; ++ st->hctsiz_copy.b.dopng = 0; ++ st->hctsiz_copy.b.pid = hc->data_pid_start; ++ ++ if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { ++ hc->xfer_len = hc->max_packet; ++ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { ++ hc->xfer_len = 188; ++ } ++ st->hctsiz_copy.b.xfersize = hc->xfer_len; ++ ++ st->hctsiz_copy.b.pktcnt = 1; ++ ++ if (hc->ep_type & 0x1) { ++ /* ++ * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers, ++ * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array. ++ * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt ++ * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set ++ * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ ++ * must not touch internal driver state. ++ */ ++ if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) { ++ if (hc->align_buff) { ++ st->hcdma_copy.d32 = hc->align_buff; ++ } else { ++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); ++ } ++ } ++ } else { ++ if (hc->align_buff) { ++ st->hcdma_copy.d32 = hc->align_buff; ++ } else { ++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); ++ } ++ } ++ /* The FIQ depends upon no other interrupts being enabled except channel halt. ++ * Fixup channel interrupt mask. */ ++ st->hcintmsk_copy.d32 = 0; ++ st->hcintmsk_copy.b.chhltd = 1; ++ st->hcintmsk_copy.b.ahberr = 1; ++ ++ /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions ++ * as Control puts the transfer into the non-periodic request queue and the ++ * non-periodic handler in the hub. Makes things lots easier. ++ */ ++ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) { ++ st->hcchar_copy.b.multicnt = 0; ++ st->hcchar_copy.b.oddfrm = 0; ++ st->hcchar_copy.b.eptype = UE_CONTROL; ++ if (hc->align_buff) { ++ st->hcdma_copy.d32 = hc->align_buff; ++ } else { ++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); ++ } ++ } ++ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); ++ ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ ++ if (hc->ep_type & 0x1) { ++ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ frame = (hfnum.b.frnum & ~0x7) >> 3; ++ uframe = hfnum.b.frnum & 0x7; ++ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { ++ /* Prevent queueing near EOF1. Bad things happen if a periodic ++ * split transaction is queued very close to EOF. ++ */ ++ start_immediate = 0; ++ } else if (uframe == 5) { ++ start_immediate = 0; ++ } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) { ++ start_immediate = 0; ++ } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) { ++ start_immediate = 0; ++ } else { ++ /* Search through all host channels to determine if a transaction ++ * is currently in progress */ ++ for (i = 0; i < hcd->core_if->core_params->host_channels; i++) { ++ if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ switch (hcd->fiq_state->channel[i].fsm) { ++ /* TT is reserved for channels that are in the middle of a periodic ++ * split transaction. ++ */ ++ case FIQ_PER_SSPLIT_STARTED: ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ case FIQ_PER_ISO_OUT_LAST: ++ if (hcd->fiq_state->channel[i].hub_addr == hub_addr && ++ hcd->fiq_state->channel[i].port_addr == port_addr) { ++ start_immediate = 0; ++ } ++ break; ++ default: ++ break; ++ } ++ if (!start_immediate) ++ break; ++ } ++ } ++ } ++ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) ++ start_immediate = 1; ++ ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); ++ switch (hc->ep_type) { ++ case UE_CONTROL: ++ case UE_BULK: ++ st->fsm = FIQ_NP_SSPLIT_STARTED; ++ break; ++ case UE_ISOCHRONOUS: ++ if (hc->ep_is_in) { ++ if (start_immediate) { ++ st->fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ st->fsm = FIQ_PER_SSPLIT_QUEUED; ++ } ++ } else { ++ if (start_immediate) { ++ /* Single-isoc OUT packets don't require FIQ involvement */ ++ if (st->nrpackets == 1) { ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_PENDING; ++ } ++ } ++ break; ++ case UE_INTERRUPT: ++ if (fiq_fsm_mask & 0x8) { ++ st->fsm = FIQ_NP_SSPLIT_STARTED; ++ } else if (start_immediate) { ++ st->fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ st->fsm = FIQ_PER_SSPLIT_QUEUED; ++ } ++ default: ++ break; ++ } ++ if (start_immediate) { ++ /* Set the oddfrm bit as close as possible to actual queueing */ ++ frame = dwc_otg_hcd_get_frame_number(hcd); ++ st->expected_uframe = (frame + 1) & 0x3FFF; ++ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; ++ st->hcchar_copy.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ } ++ mb(); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ return 0; ++} ++ ++ ++/** ++ * This function selects transactions from the HCD transfer schedule and ++ * assigns them to available host channels. It is called from HCD interrupt ++ * handler functions. ++ * ++ * @param hcd The HCD state structure. ++ * ++ * @return The types of new transactions that were assigned to host channels. ++ */ ++dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) ++{ ++ dwc_list_link_t *qh_ptr; ++ dwc_otg_qh_t *qh; ++ int num_channels; ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; ++ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; ++ ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_per_scheduled = 0; ++ last_sel_trans_num_nonper_scheduled = 0; ++ last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ /* Process entries in the periodic ready list. */ ++ qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready); ++ ++ while (qh_ptr != &hcd->periodic_sched_ready && ++ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ ++ if (microframe_schedule) { ++ // Make sure we leave one channel for non periodic transactions. ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (hcd->available_host_channels <= 1) { ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ break; ++ } ++ hcd->available_host_channels--; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_per_scheduled++; ++#endif /* DEBUG_HOST_CHANNELS */ ++ } ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ assign_and_init_hc(hcd, qh); ++ ++ /* ++ * Move the QH from the periodic ready schedule to the ++ * periodic assigned schedule. ++ */ ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &qh->qh_list_entry); ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ } ++ ++ /* ++ * Process entries in the inactive portion of the non-periodic ++ * schedule. Some free host channels may not be used if they are ++ * reserved for periodic transfers. ++ */ ++ qh_ptr = hcd->non_periodic_sched_inactive.next; ++ num_channels = hcd->core_if->core_params->host_channels; ++ while (qh_ptr != &hcd->non_periodic_sched_inactive && ++ (microframe_schedule || hcd->non_periodic_channels < ++ num_channels - hcd->periodic_channels) && ++ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ /* ++ * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission ++ * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed ++ * cheeky devices that just hold off using NAKs ++ */ ++ if (fiq_enable && nak_holdoff && qh->do_split) { ++ if (qh->nak_frame != 0xffff) { ++ uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8); ++ uint16_t frame = dwc_otg_hcd_get_frame_number(hcd); ++ if (dwc_frame_num_le(frame, next_frame)) { ++ if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) { ++ hcd->fiq_state->next_sched_frame = next_frame; ++ } ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ continue; ++ } else { ++ qh->nak_frame = 0xFFFF; ++ } ++ } ++ } ++ ++ if (microframe_schedule) { ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (hcd->available_host_channels < 1) { ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ break; ++ } ++ hcd->available_host_channels--; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_nonper_scheduled++; ++#endif /* DEBUG_HOST_CHANNELS */ ++ } ++ ++ assign_and_init_hc(hcd, qh); ++ ++ /* ++ * Move the QH from the non-periodic inactive schedule to the ++ * non-periodic active schedule. ++ */ ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active, ++ &qh->qh_list_entry); ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ ++ ++ if (!microframe_schedule) ++ hcd->non_periodic_channels++; ++ } ++ /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty, ++ * stop the FIQ from kicking us. We could potentially still have elements here if we ++ * ran out of host channels. ++ */ ++ if (fiq_enable) { ++ if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) { ++ hcd->fiq_state->kick_np_queues = 0; ++ } else { ++ /* For each entry remaining in the NP inactive queue, ++ * if this a NAK'd retransmit then don't set the kick flag. ++ */ ++ if(nak_holdoff) { ++ DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) { ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ if (qh->nak_frame == 0xFFFF) { ++ hcd->fiq_state->kick_np_queues = 1; ++ } ++ } ++ } ++ } ++ } ++ if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) ++ ret_val |= DWC_OTG_TRANSACTION_PERIODIC; ++ ++ if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) ++ ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC; ++ ++ ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels; ++#endif /* DEBUG_HOST_CHANNELS */ ++ return ret_val; ++} ++ ++/** ++ * Attempts to queue a single transaction request for a host channel ++ * associated with either a periodic or non-periodic transfer. This function ++ * assumes that there is space available in the appropriate request queue. For ++ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space ++ * is available in the appropriate Tx FIFO. ++ * ++ * @param hcd The HCD state structure. ++ * @param hc Host channel descriptor associated with either a periodic or ++ * non-periodic transfer. ++ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx ++ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic ++ * transfers. ++ * ++ * @return 1 if a request is queued and more requests may be needed to ++ * complete the transfer, 0 if no more requests are required for this ++ * transfer, -1 if there is insufficient space in the Tx FIFO. ++ */ ++static int queue_transaction(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, uint16_t fifo_dwords_avail) ++{ ++ int retval; ++ ++ if (hcd->core_if->dma_enable) { ++ if (hcd->core_if->dma_desc_enable) { ++ if (!hc->xfer_started ++ || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { ++ dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh); ++ hc->qh->ping_state = 0; ++ } ++ } else if (!hc->xfer_started) { ++ if (fiq_fsm_enable && hc->error_state) { ++ hcd->fiq_state->channel[hc->hc_num].nr_errors = ++ DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count; ++ hcd->fiq_state->channel[hc->hc_num].fsm = ++ FIQ_PASSTHROUGH_ERRORSTATE; ++ } ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ hc->qh->ping_state = 0; ++ } ++ retval = 0; ++ } else if (hc->halt_pending) { ++ /* Don't queue a request if the channel has been halted. */ ++ retval = 0; ++ } else if (hc->halt_on_queue) { ++ dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status); ++ retval = 0; ++ } else if (hc->do_ping) { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ } ++ retval = 0; ++ } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { ++ if ((fifo_dwords_avail * 4) >= hc->max_packet) { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ retval = 1; ++ } else { ++ retval = ++ dwc_otg_hc_continue_transfer(hcd->core_if, ++ hc); ++ } ++ } else { ++ retval = -1; ++ } ++ } else { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ retval = 1; ++ } else { ++ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); ++ } ++ } ++ ++ return retval; ++} ++ ++/** ++ * Processes periodic channels for the next frame and queues transactions for ++ * these channels to the DWC_otg controller. After queueing transactions, the ++ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions ++ * to queue as Periodic Tx FIFO or request queue space becomes available. ++ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. ++ */ ++static void process_periodic_channels(dwc_otg_hcd_t * hcd) ++{ ++ hptxsts_data_t tx_status; ++ dwc_list_link_t *qh_ptr; ++ dwc_otg_qh_t *qh; ++ int status = 0; ++ int no_queue_space = 0; ++ int no_fifo_space = 0; ++ ++ dwc_otg_host_global_regs_t *host_regs; ++ host_regs = hcd->core_if->host_if->host_global_regs; ++ ++ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); ++#ifdef DEBUG ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx Req Queue Space Avail (before queue): %d\n", ++ tx_status.b.ptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", ++ tx_status.b.ptxfspcavail); ++#endif ++ ++ qh_ptr = hcd->periodic_sched_assigned.next; ++ while (qh_ptr != &hcd->periodic_sched_assigned) { ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); ++ if (tx_status.b.ptxqspcavail == 0) { ++ no_queue_space = 1; ++ break; ++ } ++ ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ ++ // Do not send a split start transaction any later than frame .6 ++ // Note, we have to schedule a periodic in .5 to make it go in .6 ++ if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) ++ { ++ qh_ptr = qh_ptr->next; ++ hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; ++ continue; ++ } ++ ++ if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { ++ if (qh->do_split) ++ fiq_fsm_queue_split_transaction(hcd, qh); ++ else ++ fiq_fsm_queue_isoc_transaction(hcd, qh); ++ } else { ++ ++ /* ++ * Set a flag if we're queueing high-bandwidth in slave mode. ++ * The flag prevents any halts to get into the request queue in ++ * the middle of multiple high-bandwidth packets getting queued. ++ */ ++ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) { ++ hcd->core_if->queuing_high_bandwidth = 1; ++ } ++ status = queue_transaction(hcd, qh->channel, ++ tx_status.b.ptxfspcavail); ++ if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } ++ } ++ ++ /* ++ * In Slave mode, stay on the current transfer until there is ++ * nothing more to do or the high-bandwidth request count is ++ * reached. In DMA mode, only need to queue one request. The ++ * controller automatically handles multiple packets for ++ * high-bandwidth transfers. ++ */ ++ if (hcd->core_if->dma_enable || status == 0 || ++ qh->channel->requests == qh->channel->multi_count) { ++ qh_ptr = qh_ptr->next; ++ /* ++ * Move the QH from the periodic assigned schedule to ++ * the periodic queued schedule. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued, ++ &qh->qh_list_entry); ++ ++ /* done queuing high bandwidth */ ++ hcd->core_if->queuing_high_bandwidth = 0; ++ } ++ } ++ ++ if (!hcd->core_if->dma_enable) { ++ dwc_otg_core_global_regs_t *global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ global_regs = hcd->core_if->core_global_regs; ++ intr_mask.b.ptxfempty = 1; ++#ifdef DEBUG ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx Req Queue Space Avail (after queue): %d\n", ++ tx_status.b.ptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx FIFO Space Avail (after queue): %d\n", ++ tx_status.b.ptxfspcavail); ++#endif ++ if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) || ++ no_queue_space || no_fifo_space) { ++ /* ++ * May need to queue more transactions as the request ++ * queue or Tx FIFO empties. Enable the periodic Tx ++ * FIFO empty interrupt. (Always use the half-empty ++ * level to ensure that new requests are loaded as ++ * soon as possible.) ++ */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, ++ intr_mask.d32); ++ } else { ++ /* ++ * Disable the Tx FIFO empty interrupt since there are ++ * no more transactions that need to be queued right ++ * now. This function is called from interrupt ++ * handlers to queue more transactions as transfer ++ * states change. ++ */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, ++ 0); ++ } ++ } ++} ++ ++/** ++ * Processes active non-periodic channels and queues transactions for these ++ * channels to the DWC_otg controller. After queueing transactions, the NP Tx ++ * FIFO Empty interrupt is enabled if there are more transactions to queue as ++ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx ++ * FIFO Empty interrupt is disabled. ++ */ ++static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) ++{ ++ gnptxsts_data_t tx_status; ++ dwc_list_link_t *orig_qh_ptr; ++ dwc_otg_qh_t *qh; ++ int status; ++ int no_queue_space = 0; ++ int no_fifo_space = 0; ++ int more_to_do = 0; ++ ++ dwc_otg_core_global_regs_t *global_regs = ++ hcd->core_if->core_global_regs; ++ ++ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); ++#ifdef DEBUG ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx Req Queue Space Avail (before queue): %d\n", ++ tx_status.b.nptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", ++ tx_status.b.nptxfspcavail); ++#endif ++ /* ++ * Keep track of the starting point. Skip over the start-of-list ++ * entry. ++ */ ++ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { ++ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; ++ } ++ orig_qh_ptr = hcd->non_periodic_qh_ptr; ++ ++ /* ++ * Process once through the active list or until no more space is ++ * available in the request queue or the Tx FIFO. ++ */ ++ do { ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { ++ no_queue_space = 1; ++ break; ++ } ++ ++ qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, ++ qh_list_entry); ++ ++ if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { ++ fiq_fsm_queue_split_transaction(hcd, qh); ++ } else { ++ status = queue_transaction(hcd, qh->channel, ++ tx_status.b.nptxfspcavail); ++ ++ if (status > 0) { ++ more_to_do = 1; ++ } else if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } ++ } ++ /* Advance to next QH, skipping start-of-list entry. */ ++ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; ++ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { ++ hcd->non_periodic_qh_ptr = ++ hcd->non_periodic_qh_ptr->next; ++ } ++ ++ } while (hcd->non_periodic_qh_ptr != orig_qh_ptr); ++ ++ if (!hcd->core_if->dma_enable) { ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ intr_mask.b.nptxfempty = 1; ++ ++#ifdef DEBUG ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx Req Queue Space Avail (after queue): %d\n", ++ tx_status.b.nptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx FIFO Space Avail (after queue): %d\n", ++ tx_status.b.nptxfspcavail); ++#endif ++ if (more_to_do || no_queue_space || no_fifo_space) { ++ /* ++ * May need to queue more transactions as the request ++ * queue or Tx FIFO empties. Enable the non-periodic ++ * Tx FIFO empty interrupt. (Always use the half-empty ++ * level to ensure that new requests are loaded as ++ * soon as possible.) ++ */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, ++ intr_mask.d32); ++ } else { ++ /* ++ * Disable the Tx FIFO empty interrupt since there are ++ * no more transactions that need to be queued right ++ * now. This function is called from interrupt ++ * handlers to queue more transactions as transfer ++ * states change. ++ */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, ++ 0); ++ } ++ } ++} ++ ++/** ++ * This function processes the currently active host channels and queues ++ * transactions for these channels to the DWC_otg controller. It is called ++ * from HCD interrupt handler functions. ++ * ++ * @param hcd The HCD state structure. ++ * @param tr_type The type(s) of transactions to queue (non-periodic, ++ * periodic, or both). ++ */ ++void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, ++ dwc_otg_transaction_type_e tr_type) ++{ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); ++#endif ++ /* Process host channels associated with periodic transfers. */ ++ if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC || ++ tr_type == DWC_OTG_TRANSACTION_ALL) && ++ !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) { ++ ++ process_periodic_channels(hcd); ++ } ++ ++ /* Process host channels associated with non-periodic transfers. */ ++ if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || ++ tr_type == DWC_OTG_TRANSACTION_ALL) { ++ if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) { ++ process_non_periodic_channels(hcd); ++ } else { ++ /* ++ * Ensure NP Tx FIFO empty interrupt is disabled when ++ * there are no non-periodic transfers to process. ++ */ ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ gintmsk.b.nptxfempty = 1; ++ ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ } ++ } ++ } ++} ++ ++#ifdef DWC_HS_ELECT_TST ++/* ++ * Quick and dirty hack to implement the HS Electrical Test ++ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. ++ * ++ * This code was copied from our userspace app "hset". It sends a ++ * Get Device Descriptor control sequence in two parts, first the ++ * Setup packet by itself, followed some time later by the In and ++ * Ack packets. Rather than trying to figure out how to add this ++ * functionality to the normal driver code, we just hijack the ++ * hardware, using these two function to drive the hardware ++ * directly. ++ */ ++ ++static dwc_otg_core_global_regs_t *global_regs; ++static dwc_otg_host_global_regs_t *hc_global_regs; ++static dwc_otg_hc_regs_t *hc_regs; ++static uint32_t *data_fifo; ++ ++static void do_setup(void) ++{ ++ gintsts_data_t gintsts; ++ hctsiz_data_t hctsiz; ++ hcchar_data_t hcchar; ++ haint_data_t haint; ++ hcint_data_t hcint; ++ ++ /* Enable HAINTs */ ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001); ++ ++ /* Enable HCINTs */ ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* ++ * Send Setup packet (Get Device Descriptor) ++ */ ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++// hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 8; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 0; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ /* Fill FIFO with Setup data for Get Device Descriptor */ ++ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); ++ DWC_WRITE_REG32(data_fifo++, 0x01000680); ++ DWC_WRITE_REG32(data_fifo++, 0x00080000); ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ /* Disable HCINTs */ ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000); ++ ++ /* Disable HAINTs */ ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++} ++ ++static void do_in_ack(void) ++{ ++ gintsts_data_t gintsts; ++ hctsiz_data_t hctsiz; ++ hcchar_data_t hcchar; ++ haint_data_t haint; ++ hcint_data_t hcint; ++ host_grxsts_data_t grxsts; ++ ++ /* Enable HAINTs */ ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001); ++ ++ /* Enable HCINTs */ ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* ++ * Receive Control In packet ++ */ ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 8; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 1; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for receive status queue interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.rxstsqlvl == 0); ++ ++ /* Read RXSTS */ ++ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp); ++ ++ /* Clear RXSTSQLVL in GINTSTS */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN: ++ /* Read the data into the host buffer */ ++ if (grxsts.b.bcnt > 0) { ++ int i; ++ int word_count = (grxsts.b.bcnt + 3) / 4; ++ ++ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); ++ ++ for (i = 0; i < word_count; i++) { ++ (void)DWC_READ_REG32(data_fifo++); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for receive status queue interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.rxstsqlvl == 0); ++ ++ /* Read RXSTS */ ++ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp); ++ ++ /* Clear RXSTSQLVL in GINTSTS */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: ++ break; ++ ++ default: ++ break; ++ } ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++// usleep(100000); ++// mdelay(100); ++ dwc_mdelay(1); ++ ++ /* ++ * Send handshake packet ++ */ ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 0; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 0; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ /* Disable HCINTs */ ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000); ++ ++ /* Disable HAINTs */ ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++} ++#endif ++ ++/** Handles hub class-specific requests. */ ++int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint16_t typeReq, ++ uint16_t wValue, ++ uint16_t wIndex, uint8_t * buf, uint16_t wLength) ++{ ++ int retval = 0; ++ ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ usb_hub_descriptor_t *hub_desc; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ uint32_t port_status; ++ ++ switch (typeReq) { ++ case UCR_CLEAR_HUB_FEATURE: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearHubFeature 0x%x\n", wValue); ++ switch (wValue) { ++ case UHF_C_HUB_LOCAL_POWER: ++ case UHF_C_HUB_OVER_CURRENT: ++ /* Nothing required here */ ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "ClearHubFeature request %xh unknown\n", ++ wValue); ++ } ++ break; ++ case UCR_CLEAR_PORT_FEATURE: ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (wValue != UHF_PORT_L1) ++#endif ++ if (!wIndex || wIndex > 1) ++ goto error; ++ ++ switch (wValue) { ++ case UHF_PORT_ENABLE: ++ DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtena = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_SUSPEND: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); ++ ++ if (core_if->power_down == 2) { ++ dwc_otg_host_hibernation_restore(core_if, 0, 0); ++ } else { ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ dwc_mdelay(5); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ hprt0.b.prtsusp = 0; ++ /* Clear Resume bit */ ++ dwc_mdelay(100); ++ hprt0.b.prtres = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UHF_PORT_L1: ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ glpmcfg_data_t lpmcfg = {.d32 = 0 }; ++ ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if-> ++ core_global_regs->glpmcfg); ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ lpmcfg.b.prt_sleep_sts = 1; ++ DWC_WRITE_REG32(&core_if-> ++ core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ ++ /* Clear Enbl_L1Gating bit. */ ++ pcgcctl.b.enbl_sleep_gating = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, ++ 0); ++ ++ dwc_mdelay(5); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++ /* This bit will be cleared in wakeup interrupt handle */ ++ break; ++ } ++#endif ++ case UHF_PORT_POWER: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_POWER\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_INDICATOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); ++ /* Port inidicator not supported */ ++ break; ++ case UHF_C_PORT_CONNECTION: ++ /* Clears drivers internal connect status change ++ * flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); ++ dwc_otg_hcd->flags.b.port_connect_status_change = 0; ++ break; ++ case UHF_C_PORT_RESET: ++ /* Clears the driver's internal Port Reset Change ++ * flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); ++ dwc_otg_hcd->flags.b.port_reset_change = 0; ++ break; ++ case UHF_C_PORT_ENABLE: ++ /* Clears the driver's internal Port ++ * Enable/Disable Change flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); ++ dwc_otg_hcd->flags.b.port_enable_change = 0; ++ break; ++ case UHF_C_PORT_SUSPEND: ++ /* Clears the driver's internal Port Suspend ++ * Change flag, which is set when resume signaling on ++ * the host port is complete */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); ++ dwc_otg_hcd->flags.b.port_suspend_change = 0; ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UHF_C_PORT_L1: ++ dwc_otg_hcd->flags.b.port_l1_change = 0; ++ break; ++#endif ++ case UHF_C_PORT_OVER_CURRENT: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); ++ dwc_otg_hcd->flags.b.port_over_current_change = 0; ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "ClearPortFeature request %xh " ++ "unknown or unsupported\n", wValue); ++ } ++ break; ++ case UCR_GET_HUB_DESCRIPTOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetHubDescriptor\n"); ++ hub_desc = (usb_hub_descriptor_t *) buf; ++ hub_desc->bDescLength = 9; ++ hub_desc->bDescriptorType = 0x29; ++ hub_desc->bNbrPorts = 1; ++ USETW(hub_desc->wHubCharacteristics, 0x08); ++ hub_desc->bPwrOn2PwrGood = 1; ++ hub_desc->bHubContrCurrent = 0; ++ hub_desc->DeviceRemovable[0] = 0; ++ hub_desc->DeviceRemovable[1] = 0xff; ++ break; ++ case UCR_GET_HUB_STATUS: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetHubStatus\n"); ++ DWC_MEMSET(buf, 0, 4); ++ break; ++ case UCR_GET_PORT_STATUS: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n", ++ wIndex, dwc_otg_hcd->flags.d32); ++ if (!wIndex || wIndex > 1) ++ goto error; ++ ++ port_status = 0; ++ ++ if (dwc_otg_hcd->flags.b.port_connect_status_change) ++ port_status |= (1 << UHF_C_PORT_CONNECTION); ++ ++ if (dwc_otg_hcd->flags.b.port_enable_change) ++ port_status |= (1 << UHF_C_PORT_ENABLE); ++ ++ if (dwc_otg_hcd->flags.b.port_suspend_change) ++ port_status |= (1 << UHF_C_PORT_SUSPEND); ++ ++ if (dwc_otg_hcd->flags.b.port_l1_change) ++ port_status |= (1 << UHF_C_PORT_L1); ++ ++ if (dwc_otg_hcd->flags.b.port_reset_change) { ++ port_status |= (1 << UHF_C_PORT_RESET); ++ } ++ ++ if (dwc_otg_hcd->flags.b.port_over_current_change) { ++ DWC_WARN("Overcurrent change detected\n"); ++ port_status |= (1 << UHF_C_PORT_OVER_CURRENT); ++ } ++ ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return 0's for the remainder of the port status ++ * since the port register can't be read if the core ++ * is in device mode. ++ */ ++ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); ++ break; ++ } ++ ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); ++ ++ if (hprt0.b.prtconnsts) ++ port_status |= (1 << UHF_PORT_CONNECTION); ++ ++ if (hprt0.b.prtena) ++ port_status |= (1 << UHF_PORT_ENABLE); ++ ++ if (hprt0.b.prtsusp) ++ port_status |= (1 << UHF_PORT_SUSPEND); ++ ++ if (hprt0.b.prtovrcurract) ++ port_status |= (1 << UHF_PORT_OVER_CURRENT); ++ ++ if (hprt0.b.prtrst) ++ port_status |= (1 << UHF_PORT_RESET); ++ ++ if (hprt0.b.prtpwr) ++ port_status |= (1 << UHF_PORT_POWER); ++ ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) ++ port_status |= (1 << UHF_PORT_HIGH_SPEED); ++ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) ++ port_status |= (1 << UHF_PORT_LOW_SPEED); ++ ++ if (hprt0.b.prttstctl) ++ port_status |= (1 << UHF_PORT_TEST); ++ if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) { ++ port_status |= (1 << UHF_PORT_L1); ++ } ++ /* ++ For Synopsys HW emulation of Power down wkup_control asserts the ++ hreset_n and prst_n on suspned. This causes the HPRT0 to be zero. ++ We intentionally tell the software that port is in L2Suspend state. ++ Only for STE. ++ */ ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ port_status |= (1 << UHF_PORT_SUSPEND); ++ } ++ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ ++ ++ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); ++ ++ break; ++ case UCR_SET_HUB_FEATURE: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetHubFeature\n"); ++ /* No HUB features supported */ ++ break; ++ case UCR_SET_PORT_FEATURE: ++ if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1)) ++ goto error; ++ ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return without doing anything since the port ++ * register can't be written if the core is in device ++ * mode. ++ */ ++ break; ++ } ++ ++ switch (wValue) { ++ case UHF_PORT_SUSPEND: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); ++ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) { ++ goto error; ++ } ++ if (core_if->power_down == 2) { ++ int timeout = 300; ++ dwc_irqflags_t flags; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++#ifdef DWC_DEV_SRPCAP ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++#endif ++ DWC_PRINTF("Preparing for complete power-off\n"); ++ ++ /* Save registers before hibernation */ ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_host_regs(core_if); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ hprt0.b.prtena = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ /* Spin hprt0.b.prtsusp to became 1 */ ++ do { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ if (hprt0.b.prtsusp) { ++ break; ++ } ++ dwc_mdelay(1); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_WARN("Suspend wasn't genereted\n"); ++ } ++ dwc_udelay(10); ++ ++ /* ++ * We need to disable interrupts to prevent servicing of any IRQ ++ * during going to hibernation ++ */ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ core_if->lx_state = DWC_OTG_L2; ++#ifdef DWC_DEV_SRPCAP ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 0; ++ hprt0.b.prtena = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++#endif ++ gusbcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gusbcfg); ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ /* Suspend the Phy Clock */ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } else { ++ /* UTMI+ Interface */ ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ dwc_udelay(10); ++ } ++#ifdef DWC_DEV_SRPCAP ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++#endif ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = 0; ++#ifdef DWC_DEV_SRPCAP ++ gpwrdn.b.srp_det_msk = 1; ++#endif ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ gpwrdn.b.sts_chngint_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Enable Power Down Clamp and all interrupts in GPWRDN */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Switch off VDD */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++#ifdef DWC_DEV_SRPCAP ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) ++ { ++ core_if->pwron_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ ); ++ } ++#endif ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ /* Set flag to indicate that we are in hibernation */ ++ core_if->hibernation_suspend = 1; ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags); ++ ++ DWC_PRINTF("Host hibernation completed\n"); ++ // Exit from case statement ++ break; ++ ++ } ++ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex && ++ dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.b.hstsethnpen = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gotgctl, 0, gotgctl.d32); ++ core_if->op_state = A_SUSPEND; ++ } ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ { ++ dwc_irqflags_t flags; ++ /* Update lx_state */ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ core_if->lx_state = DWC_OTG_L2; ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ } ++ /* Suspend the Phy Clock */ ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ } ++ ++ /* For HNP the bus must be suspended for at least 200ms. */ ++ if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ dwc_mdelay(200); ++ } ++ ++ /** @todo - check how sw can wait for 1 sec to check asesvld??? */ ++#if 0 //vahrama !!!!!!!!!!!!!!!!!! ++ if (core_if->adp_enable) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn; ++ ++ while (gotgctl.b.asesvld == 1) { ++ gotgctl.d32 = ++ DWC_READ_REG32(&core_if-> ++ core_global_regs-> ++ gotgctl); ++ dwc_mdelay(100); ++ } ++ ++ /* Enable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ /* Unmask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_probe_start(core_if); ++ } ++#endif ++ break; ++ case UHF_PORT_POWER: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_POWER\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_RESET: ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ /* If we are going to exit from Hibernated ++ * state via USB RESET. ++ */ ++ dwc_otg_host_hibernation_restore(core_if, 0, 1); ++ } else { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_RESET\n"); ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.enbl_sleep_gating = 1; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ { ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ DWC_WRITE_REG32 ++ (&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ dwc_mdelay(1); ++ } ++ } ++#endif ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ /* Clear suspend bit if resetting from suspended state. */ ++ hprt0.b.prtsusp = 0; ++ /* When B-Host the Port reset bit is set in ++ * the Start HCD Callback function, so that ++ * the reset is started within 1ms of the HNP ++ * success interrupt. */ ++ if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) { ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtrst = 1; ++ DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++ } ++ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ ++ dwc_mdelay(60); ++ hprt0.b.prtrst = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */ ++ } ++ break; ++#ifdef DWC_HS_ELECT_TST ++ case UHF_PORT_TEST: ++ { ++ uint32_t t; ++ gintmsk_data_t gintmsk; ++ ++ t = (wIndex >> 8); /* MSB wIndex USB */ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", ++ t); ++ DWC_WARN("USB_PORT_FEAT_TEST %d\n", t); ++ if (t < 6) { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prttstctl = t; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++ } else { ++ /* Setup global vars with reg addresses (quick and ++ * dirty hack, should be cleaned up) ++ */ ++ global_regs = core_if->core_global_regs; ++ hc_global_regs = ++ core_if->host_if->host_global_regs; ++ hc_regs = ++ (dwc_otg_hc_regs_t *) ((char *) ++ global_regs + ++ 0x500); ++ data_fifo = ++ (uint32_t *) ((char *)global_regs + ++ 0x1000); ++ ++ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ DWC_READ_REG32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Drive suspend on the root port */ ++ hprt0.d32 = ++ dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ hprt0.b.prtres = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Drive resume on the root port */ ++ hprt0.d32 = ++ dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 0; ++ hprt0.b.prtres = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_mdelay(100); ++ ++ /* Clear the resume bit */ ++ hprt0.b.prtres = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Restore interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); ++ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ DWC_READ_REG32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Send the Setup packet */ ++ do_setup(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Restore interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); ++ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ DWC_READ_REG32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* Send the Setup packet */ ++ do_setup(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Send the In and Ack packets */ ++ do_in_ack(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Restore interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); ++ } ++ } ++ break; ++ } ++#endif /* DWC_HS_ELECT_TST */ ++ ++ case UHF_PORT_INDICATOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); ++ /* Not supported */ ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "SetPortFeature request %xh " ++ "unknown or unsupported\n", wValue); ++ break; ++ } ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UCR_SET_AND_TEST_PORT_FEATURE: ++ if (wValue != UHF_PORT_L1) { ++ goto error; ++ } ++ { ++ int portnum, hird, devaddr, remwake; ++ glpmcfg_data_t lpmcfg; ++ uint32_t time_usecs; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ ++ if (!dwc_otg_get_param_lpm_enable(core_if)) { ++ goto error; ++ } ++ if (wValue != UHF_PORT_L1 || wLength != 1) { ++ goto error; ++ } ++ /* Check if the port currently is in SLEEP state */ ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ DWC_INFO("Port is already in sleep mode\n"); ++ buf[0] = 0; /* Return success */ ++ break; ++ } ++ ++ portnum = wIndex & 0xf; ++ hird = (wIndex >> 4) & 0xf; ++ devaddr = (wIndex >> 8) & 0x7f; ++ remwake = (wIndex >> 15); ++ ++ if (portnum != 1) { ++ retval = -DWC_E_INVALID; ++ DWC_WARN ++ ("Wrong port number(%d) in SetandTestPortFeature request\n", ++ portnum); ++ break; ++ } ++ ++ DWC_PRINTF ++ ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n", ++ portnum, hird, devaddr, remwake); ++ /* Disable LPM interrupt */ ++ gintmsk.d32 = 0; ++ gintmsk.b.lpmtranrcvd = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ gintmsk.d32, 0); ++ ++ if (dwc_otg_hcd_send_lpm ++ (dwc_otg_hcd, devaddr, hird, remwake)) { ++ retval = -DWC_E_INVALID; ++ break; ++ } ++ ++ time_usecs = 10 * (lpmcfg.b.retry_count + 1); ++ /* We will consider timeout if time_usecs microseconds pass, ++ * and we don't receive LPM transaction status. ++ * After receiving non-error responce(ACK/NYET/STALL) from device, ++ * core will set lpmtranrcvd bit. ++ */ ++ do { ++ gintsts.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (gintsts.b.lpmtranrcvd) { ++ break; ++ } ++ dwc_udelay(1); ++ } while (--time_usecs); ++ /* lpm_int bit will be cleared in LPM interrupt handler */ ++ ++ /* Now fill status ++ * 0x00 - Success ++ * 0x10 - NYET ++ * 0x11 - Timeout ++ */ ++ if (!gintsts.b.lpmtranrcvd) { ++ buf[0] = 0x3; /* Completion code is Timeout */ ++ dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd); ++ } else { ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.lpm_resp == 0x3) { ++ /* ACK responce from the device */ ++ buf[0] = 0x00; /* Success */ ++ } else if (lpmcfg.b.lpm_resp == 0x2) { ++ /* NYET responce from the device */ ++ buf[0] = 0x2; ++ } else { ++ /* Otherwise responce with Timeout */ ++ buf[0] = 0x3; ++ } ++ } ++ DWC_PRINTF("Device responce to LPM trans is %x\n", ++ lpmcfg.b.lpm_resp); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, ++ gintmsk.d32); ++ ++ break; ++ } ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ default: ++error: ++ retval = -DWC_E_INVALID; ++ DWC_WARN("DWC OTG HCD - " ++ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", ++ typeReq, wIndex, wValue); ++ break; ++ } ++ ++ return retval; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** Returns index of host channel to perform LPM transaction. */ ++int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr) ++{ ++ dwc_otg_core_if_t *core_if = hcd->core_if; ++ dwc_hc_t *hc; ++ hcchar_data_t hcchar; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ DWC_PRINTF("No free channel to select for LPM transaction\n"); ++ return -1; ++ } ++ ++ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); ++ ++ /* Mask host channel interrupts. */ ++ gintmsk.b.hcintr = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ ++ /* Fill fields that core needs for LPM transaction */ ++ hcchar.b.devaddr = devaddr; ++ hcchar.b.epnum = 0; ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.mps = 64; ++ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); ++ hcchar.b.epdir = 0; /* OUT */ ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar, ++ hcchar.d32); ++ ++ /* Remove the host channel from the free list. */ ++ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); ++ ++ DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr); ++ ++ return hc->hc_num; ++} ++ ++/** Release hc after performing LPM transaction */ ++void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd) ++{ ++ dwc_hc_t *hc; ++ glpmcfg_data_t lpmcfg; ++ uint8_t hc_num; ++ ++ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg); ++ hc_num = lpmcfg.b.lpm_chan_index; ++ ++ hc = hcd->hc_ptr_array[hc_num]; ++ ++ DWC_PRINTF("Freeing channel %d after LPM\n", hc_num); ++ /* Return host channel to free list */ ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++} ++ ++int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird, ++ uint8_t bRemoteWake) ++{ ++ glpmcfg_data_t lpmcfg; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ int channel; ++ ++ channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr); ++ if (channel < 0) { ++ return channel; ++ } ++ ++ pcgcctl.b.enbl_sleep_gating = 1; ++ DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ /* Read LPM config register */ ++ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg); ++ ++ /* Program LPM transaction fields */ ++ lpmcfg.b.rem_wkup_en = bRemoteWake; ++ lpmcfg.b.hird = hird; ++ lpmcfg.b.hird_thres = 0x1c; ++ lpmcfg.b.lpm_chan_index = channel; ++ lpmcfg.b.en_utmi_sleep = 1; ++ /* Program LPM config register */ ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ /* Send LPM transaction */ ++ lpmcfg.b.send_lpm = 1; ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ return 0; ++} ++ ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ ++int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port) ++{ ++ int retval; ++ ++ if (port != 1) { ++ return -DWC_E_INVALID; ++ } ++ ++ retval = (hcd->flags.b.port_connect_status_change || ++ hcd->flags.b.port_reset_change || ++ hcd->flags.b.port_enable_change || ++ hcd->flags.b.port_suspend_change || ++ hcd->flags.b.port_over_current_change); ++#ifdef DEBUG ++ if (retval) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" ++ " Root port status changed\n"); ++ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", ++ hcd->flags.b.port_connect_status_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", ++ hcd->flags.b.port_reset_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", ++ hcd->flags.b.port_enable_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", ++ hcd->flags.b.port_suspend_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", ++ hcd->flags.b.port_over_current_change); ++ } ++#endif ++ return retval; ++} ++ ++int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ hfnum_data_t hfnum; ++ hfnum.d32 = ++ DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs-> ++ hfnum); ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", ++ hfnum.b.frnum); ++#endif ++ return hfnum.b.frnum; ++} ++ ++int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd, ++ struct dwc_otg_hcd_function_ops *fops) ++{ ++ int retval = 0; ++ ++ hcd->fops = fops; ++ if (!dwc_otg_is_device_mode(hcd->core_if) && ++ (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) { ++ dwc_otg_hcd_reinit(hcd); ++ } else { ++ retval = -DWC_E_NO_DEVICE; ++ } ++ ++ return retval; ++} ++ ++void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd) ++{ ++ return hcd->priv; ++} ++ ++void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data) ++{ ++ hcd->priv = priv_data; ++} ++ ++uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd) ++{ ++ return hcd->otg_port; ++} ++ ++uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd) ++{ ++ uint32_t is_b_host; ++ if (hcd->core_if->op_state == B_HOST) { ++ is_b_host = 1; ++ } else { ++ is_b_host = 0; ++ } ++ ++ return is_b_host; ++} ++ ++dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, ++ int iso_desc_count, int atomic_alloc) ++{ ++ dwc_otg_hcd_urb_t *dwc_otg_urb; ++ uint32_t size; ++ ++ size = ++ sizeof(*dwc_otg_urb) + ++ iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc); ++ if (atomic_alloc) ++ dwc_otg_urb = DWC_ALLOC_ATOMIC(size); ++ else ++ dwc_otg_urb = DWC_ALLOC(size); ++ ++ if (dwc_otg_urb) ++ dwc_otg_urb->packet_count = iso_desc_count; ++ else { ++ DWC_ERROR("**** DWC OTG HCD URB alloc - " ++ "%salloc of %db failed\n", ++ atomic_alloc?"atomic ":"", size); ++ } ++ return dwc_otg_urb; ++} ++ ++void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ uint8_t dev_addr, uint8_t ep_num, ++ uint8_t ep_type, uint8_t ep_dir, uint16_t mps) ++{ ++ dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num, ++ ep_type, ep_dir, mps); ++#if 0 ++ DWC_PRINTF ++ ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n", ++ dev_addr, ep_num, ep_dir, ep_type, mps); ++#endif ++} ++ ++void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ void *urb_handle, void *buf, dwc_dma_t dma, ++ uint32_t buflen, void *setup_packet, ++ dwc_dma_t setup_dma, uint32_t flags, ++ uint16_t interval) ++{ ++ dwc_otg_urb->priv = urb_handle; ++ dwc_otg_urb->buf = buf; ++ dwc_otg_urb->dma = dma; ++ dwc_otg_urb->length = buflen; ++ dwc_otg_urb->setup_packet = setup_packet; ++ dwc_otg_urb->setup_dma = setup_dma; ++ dwc_otg_urb->flags = flags; ++ dwc_otg_urb->interval = interval; ++ dwc_otg_urb->status = -DWC_E_IN_PROGRESS; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->status; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->actual_length; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->error_count; ++} ++ ++void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num, uint32_t offset, ++ uint32_t length) ++{ ++ dwc_otg_urb->iso_descs[desc_num].offset = offset; ++ dwc_otg_urb->iso_descs[desc_num].length = length; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num) ++{ ++ return dwc_otg_urb->iso_descs[desc_num].status; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, int desc_num) ++{ ++ return dwc_otg_urb->iso_descs[desc_num].actual_length; ++} ++ ++int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ int allocated = 0; ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ ++ if (qh) { ++ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ allocated = 1; ++ } ++ } ++ return allocated; ++} ++ ++int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ int freed = 0; ++ DWC_ASSERT(qh, "qh is not allocated\n"); ++ ++ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ freed = 1; ++ } ++ ++ return freed; ++} ++ ++uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ DWC_ASSERT(qh, "qh is not allocated\n"); ++ return qh->usecs; ++} ++ ++void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd) ++{ ++#ifdef DEBUG ++ int num_channels; ++ int i; ++ gnptxsts_data_t np_tx_status; ++ hptxsts_data_t p_tx_status; ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ DWC_PRINTF("\n"); ++ DWC_PRINTF ++ ("************************************************************\n"); ++ DWC_PRINTF("HCD State:\n"); ++ DWC_PRINTF(" Num channels: %d\n", num_channels); ++ for (i = 0; i < num_channels; i++) { ++ dwc_hc_t *hc = hcd->hc_ptr_array[i]; ++ DWC_PRINTF(" Channel %d:\n", i); ++ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", ++ hc->dev_addr, hc->ep_num, hc->ep_is_in); ++ DWC_PRINTF(" speed: %d\n", hc->speed); ++ DWC_PRINTF(" ep_type: %d\n", hc->ep_type); ++ DWC_PRINTF(" max_packet: %d\n", hc->max_packet); ++ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start); ++ DWC_PRINTF(" multi_count: %d\n", hc->multi_count); ++ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started); ++ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff); ++ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len); ++ DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count); ++ DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue); ++ DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending); ++ DWC_PRINTF(" halt_status: %d\n", hc->halt_status); ++ DWC_PRINTF(" do_split: %d\n", hc->do_split); ++ DWC_PRINTF(" complete_split: %d\n", hc->complete_split); ++ DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr); ++ DWC_PRINTF(" port_addr: %d\n", hc->port_addr); ++ DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos); ++ DWC_PRINTF(" requests: %d\n", hc->requests); ++ DWC_PRINTF(" qh: %p\n", hc->qh); ++ if (hc->xfer_started) { ++ hfnum_data_t hfnum; ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hfnum.d32 = ++ DWC_READ_REG32(&hcd->core_if-> ++ host_if->host_global_regs->hfnum); ++ hcchar.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcchar); ++ hctsiz.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hctsiz); ++ hcint.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcint); ++ hcintmsk.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcintmsk); ++ DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32); ++ DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32); ++ DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32); ++ DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32); ++ DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32); ++ } ++ if (hc->xfer_started && hc->qh) { ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_hcd_urb_t *urb; ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) { ++ if (!qtd->in_process) ++ break; ++ ++ urb = qtd->urb; ++ DWC_PRINTF(" URB Info:\n"); ++ DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb); ++ if (urb) { ++ DWC_PRINTF(" Dev: %d, EP: %d %s\n", ++ dwc_otg_hcd_get_dev_addr(&urb-> ++ pipe_info), ++ dwc_otg_hcd_get_ep_num(&urb-> ++ pipe_info), ++ dwc_otg_hcd_is_pipe_in(&urb-> ++ pipe_info) ? ++ "IN" : "OUT"); ++ DWC_PRINTF(" Max packet size: %d\n", ++ dwc_otg_hcd_get_mps(&urb-> ++ pipe_info)); ++ DWC_PRINTF(" transfer_buffer: %p\n", ++ urb->buf); ++ DWC_PRINTF(" transfer_dma: %p\n", ++ (void *)urb->dma); ++ DWC_PRINTF(" transfer_buffer_length: %d\n", ++ urb->length); ++ DWC_PRINTF(" actual_length: %d\n", ++ urb->actual_length); ++ } ++ } ++ } ++ } ++ DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels); ++ DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels); ++ DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs); ++ np_tx_status.d32 = ++ DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts); ++ DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n", ++ np_tx_status.b.nptxqspcavail); ++ DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n", ++ np_tx_status.b.nptxfspcavail); ++ p_tx_status.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts); ++ DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n", ++ p_tx_status.b.ptxqspcavail); ++ DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); ++ dwc_otg_hcd_dump_frrem(hcd); ++ dwc_otg_dump_global_registers(hcd->core_if); ++ dwc_otg_dump_host_registers(hcd->core_if); ++ DWC_PRINTF ++ ("************************************************************\n"); ++ DWC_PRINTF("\n"); ++#endif ++} ++ ++#ifdef DEBUG ++void dwc_print_setup_data(uint8_t * setup) ++{ ++ int i; ++ if (CHK_DEBUG_LEVEL(DBG_HCD)) { ++ DWC_PRINTF("Setup Data = MSB "); ++ for (i = 7; i >= 0; i--) ++ DWC_PRINTF("%02x ", setup[i]); ++ DWC_PRINTF("\n"); ++ DWC_PRINTF(" bmRequestType Tranfer = %s\n", ++ (setup[0] & 0x80) ? "Device-to-Host" : ++ "Host-to-Device"); ++ DWC_PRINTF(" bmRequestType Type = "); ++ switch ((setup[0] & 0x60) >> 5) { ++ case 0: ++ DWC_PRINTF("Standard\n"); ++ break; ++ case 1: ++ DWC_PRINTF("Class\n"); ++ break; ++ case 2: ++ DWC_PRINTF("Vendor\n"); ++ break; ++ case 3: ++ DWC_PRINTF("Reserved\n"); ++ break; ++ } ++ DWC_PRINTF(" bmRequestType Recipient = "); ++ switch (setup[0] & 0x1f) { ++ case 0: ++ DWC_PRINTF("Device\n"); ++ break; ++ case 1: ++ DWC_PRINTF("Interface\n"); ++ break; ++ case 2: ++ DWC_PRINTF("Endpoint\n"); ++ break; ++ case 3: ++ DWC_PRINTF("Other\n"); ++ break; ++ default: ++ DWC_PRINTF("Reserved\n"); ++ break; ++ } ++ DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]); ++ DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2])); ++ DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4])); ++ DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6])); ++ } ++} ++#endif ++ ++void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd) ++{ ++#if 0 ++ DWC_PRINTF("Frame remaining at SOF:\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->frrem_samples, hcd->frrem_accum, ++ (hcd->frrem_samples > 0) ? ++ hcd->frrem_accum / hcd->frrem_samples : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_7_samples, ++ hcd->core_if->hfnum_7_frrem_accum, ++ (hcd->core_if->hfnum_7_samples > ++ 0) ? hcd->core_if->hfnum_7_frrem_accum / ++ hcd->core_if->hfnum_7_samples : 0); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_0_samples, ++ hcd->core_if->hfnum_0_frrem_accum, ++ (hcd->core_if->hfnum_0_samples > ++ 0) ? hcd->core_if->hfnum_0_frrem_accum / ++ hcd->core_if->hfnum_0_samples : 0); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_other_samples, ++ hcd->core_if->hfnum_other_frrem_accum, ++ (hcd->core_if->hfnum_other_samples > ++ 0) ? hcd->core_if->hfnum_other_frrem_accum / ++ hcd->core_if->hfnum_other_samples : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a, ++ (hcd->hfnum_7_samples_a > 0) ? ++ hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a, ++ (hcd->hfnum_0_samples_a > 0) ? ++ hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a, ++ (hcd->hfnum_other_samples_a > 0) ? ++ hcd->hfnum_other_frrem_accum_a / ++ hcd->hfnum_other_samples_a : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b, ++ (hcd->hfnum_7_samples_b > 0) ? ++ hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b, ++ (hcd->hfnum_0_samples_b > 0) ? ++ hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b, ++ (hcd->hfnum_other_samples_b > 0) ? ++ hcd->hfnum_other_frrem_accum_b / ++ hcd->hfnum_other_samples_b : 0); ++#endif ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +@@ -0,0 +1,862 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $ ++ * $Revision: #58 $ ++ * $Date: 2011/09/15 $ ++ * $Change: 1846647 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++#ifndef __DWC_HCD_H__ ++#define __DWC_HCD_H__ ++ ++#include "dwc_otg_os_dep.h" ++#include "usb.h" ++#include "dwc_otg_hcd_if.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_list.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_fiq_fsm.h" ++ ++ ++/** ++ * @file ++ * ++ * This file contains the structures, constants, and interfaces for ++ * the Host Contoller Driver (HCD). ++ * ++ * The Host Controller Driver (HCD) is responsible for translating requests ++ * from the USB Driver into the appropriate actions on the DWC_otg controller. ++ * It isolates the USBD from the specifics of the controller by providing an ++ * API to the USBD. ++ */ ++ ++struct dwc_otg_hcd_pipe_info { ++ uint8_t dev_addr; ++ uint8_t ep_num; ++ uint8_t pipe_type; ++ uint8_t pipe_dir; ++ uint16_t mps; ++}; ++ ++struct dwc_otg_hcd_iso_packet_desc { ++ uint32_t offset; ++ uint32_t length; ++ uint32_t actual_length; ++ uint32_t status; ++}; ++ ++struct dwc_otg_qtd; ++ ++struct dwc_otg_hcd_urb { ++ void *priv; ++ struct dwc_otg_qtd *qtd; ++ void *buf; ++ dwc_dma_t dma; ++ void *setup_packet; ++ dwc_dma_t setup_dma; ++ uint32_t length; ++ uint32_t actual_length; ++ uint32_t status; ++ uint32_t error_count; ++ uint32_t packet_count; ++ uint32_t flags; ++ uint16_t interval; ++ struct dwc_otg_hcd_pipe_info pipe_info; ++ struct dwc_otg_hcd_iso_packet_desc iso_descs[0]; ++}; ++ ++static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return pipe->ep_num; ++} ++ ++static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return pipe->pipe_type; ++} ++ ++static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return pipe->mps; ++} ++ ++static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return pipe->dev_addr; ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_ISOCHRONOUS); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_INTERRUPT); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_BULK); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_CONTROL); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return (pipe->pipe_dir == UE_DIR_IN); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (!dwc_otg_hcd_is_pipe_in(pipe)); ++} ++ ++static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe, ++ uint8_t devaddr, uint8_t ep_num, ++ uint8_t pipe_type, uint8_t pipe_dir, ++ uint16_t mps) ++{ ++ pipe->dev_addr = devaddr; ++ pipe->ep_num = ep_num; ++ pipe->pipe_type = pipe_type; ++ pipe->pipe_dir = pipe_dir; ++ pipe->mps = mps; ++} ++ ++/** ++ * Phases for control transfers. ++ */ ++typedef enum dwc_otg_control_phase { ++ DWC_OTG_CONTROL_SETUP, ++ DWC_OTG_CONTROL_DATA, ++ DWC_OTG_CONTROL_STATUS ++} dwc_otg_control_phase_e; ++ ++/** Transaction types. */ ++typedef enum dwc_otg_transaction_type { ++ DWC_OTG_TRANSACTION_NONE = 0, ++ DWC_OTG_TRANSACTION_PERIODIC = 1, ++ DWC_OTG_TRANSACTION_NON_PERIODIC = 2, ++ DWC_OTG_TRANSACTION_ALL = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC ++} dwc_otg_transaction_type_e; ++ ++struct dwc_otg_qh; ++ ++/** ++ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, ++ * interrupt, or isochronous transfer. A single QTD is created for each URB ++ * (of one of these types) submitted to the HCD. The transfer associated with ++ * a QTD may require one or multiple transactions. ++ * ++ * A QTD is linked to a Queue Head, which is entered in either the ++ * non-periodic or periodic schedule for execution. When a QTD is chosen for ++ * execution, some or all of its transactions may be executed. After ++ * execution, the state of the QTD is updated. The QTD may be retired if all ++ * its transactions are complete or if an error occurred. Otherwise, it ++ * remains in the schedule so more transactions can be executed later. ++ */ ++typedef struct dwc_otg_qtd { ++ /** ++ * Determines the PID of the next data packet for the data phase of ++ * control transfers. Ignored for other transfer types.
++ * One of the following values: ++ * - DWC_OTG_HC_PID_DATA0 ++ * - DWC_OTG_HC_PID_DATA1 ++ */ ++ uint8_t data_toggle; ++ ++ /** Current phase for control transfers (Setup, Data, or Status). */ ++ dwc_otg_control_phase_e control_phase; ++ ++ /** Keep track of the current split type ++ * for FS/LS endpoints on a HS Hub */ ++ uint8_t complete_split; ++ ++ /** How many bytes transferred during SSPLIT OUT */ ++ uint32_t ssplit_out_xfer_count; ++ ++ /** ++ * Holds the number of bus errors that have occurred for a transaction ++ * within this transfer. ++ */ ++ uint8_t error_count; ++ ++ /** ++ * Index of the next frame descriptor for an isochronous transfer. A ++ * frame descriptor describes the buffer position and length of the ++ * data to be transferred in the next scheduled (micro)frame of an ++ * isochronous transfer. It also holds status for that transaction. ++ * The frame index starts at 0. ++ */ ++ uint16_t isoc_frame_index; ++ ++ /** Position of the ISOC split on full/low speed */ ++ uint8_t isoc_split_pos; ++ ++ /** Position of the ISOC split in the buffer for the current frame */ ++ uint16_t isoc_split_offset; ++ ++ /** URB for this transfer */ ++ struct dwc_otg_hcd_urb *urb; ++ ++ struct dwc_otg_qh *qh; ++ ++ /** This list of QTDs */ ++ DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry; ++ ++ /** Indicates if this QTD is currently processed by HW. */ ++ uint8_t in_process; ++ ++ /** Number of DMA descriptors for this QTD */ ++ uint8_t n_desc; ++ ++ /** ++ * Last activated frame(packet) index. ++ * Used in Descriptor DMA mode only. ++ */ ++ uint16_t isoc_frame_index_last; ++ ++} dwc_otg_qtd_t; ++ ++DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd); ++ ++/** ++ * A Queue Head (QH) holds the static characteristics of an endpoint and ++ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may ++ * be entered in either the non-periodic or periodic schedule. ++ */ ++typedef struct dwc_otg_qh { ++ /** ++ * Endpoint type. ++ * One of the following values: ++ * - UE_CONTROL ++ * - UE_BULK ++ * - UE_INTERRUPT ++ * - UE_ISOCHRONOUS ++ */ ++ uint8_t ep_type; ++ uint8_t ep_is_in; ++ ++ /** wMaxPacketSize Field of Endpoint Descriptor. */ ++ uint16_t maxp; ++ ++ /** ++ * Device speed. ++ * One of the following values: ++ * - DWC_OTG_EP_SPEED_LOW ++ * - DWC_OTG_EP_SPEED_FULL ++ * - DWC_OTG_EP_SPEED_HIGH ++ */ ++ uint8_t dev_speed; ++ ++ /** ++ * Determines the PID of the next data packet for non-control ++ * transfers. Ignored for control transfers.
++ * One of the following values: ++ * - DWC_OTG_HC_PID_DATA0 ++ * - DWC_OTG_HC_PID_DATA1 ++ */ ++ uint8_t data_toggle; ++ ++ /** Ping state if 1. */ ++ uint8_t ping_state; ++ ++ /** ++ * List of QTDs for this QH. ++ */ ++ struct dwc_otg_qtd_list qtd_list; ++ ++ /** Host channel currently processing transfers for this QH. */ ++ struct dwc_hc *channel; ++ ++ /** Full/low speed endpoint on high-speed hub requires split. */ ++ uint8_t do_split; ++ ++ /** @name Periodic schedule information */ ++ /** @{ */ ++ ++ /** Bandwidth in microseconds per (micro)frame. */ ++ uint16_t usecs; ++ ++ /** Interval between transfers in (micro)frames. */ ++ uint16_t interval; ++ ++ /** ++ * (micro)frame to initialize a periodic transfer. The transfer ++ * executes in the following (micro)frame. ++ */ ++ uint16_t sched_frame; ++ ++ /* ++ ** Frame a NAK was received on this queue head, used to minimise NAK retransmission ++ */ ++ uint16_t nak_frame; ++ ++ /** (micro)frame at which last start split was initialized. */ ++ uint16_t start_split_frame; ++ ++ /** @} */ ++ ++ /** ++ * Used instead of original buffer if ++ * it(physical address) is not dword-aligned. ++ */ ++ uint8_t *dw_align_buf; ++ dwc_dma_t dw_align_buf_dma; ++ ++ /** Entry for QH in either the periodic or non-periodic schedule. */ ++ dwc_list_link_t qh_list_entry; ++ ++ /** @name Descriptor DMA support */ ++ /** @{ */ ++ ++ /** Descriptor List. */ ++ dwc_otg_host_dma_desc_t *desc_list; ++ ++ /** Descriptor List physical address. */ ++ dwc_dma_t desc_list_dma; ++ ++ /** ++ * Xfer Bytes array. ++ * Each element corresponds to a descriptor and indicates ++ * original XferSize size value for the descriptor. ++ */ ++ uint32_t *n_bytes; ++ ++ /** Actual number of transfer descriptors in a list. */ ++ uint16_t ntd; ++ ++ /** First activated isochronous transfer descriptor index. */ ++ uint8_t td_first; ++ /** Last activated isochronous transfer descriptor index. */ ++ uint8_t td_last; ++ ++ /** @} */ ++ ++ ++ uint16_t speed; ++ uint16_t frame_usecs[8]; ++ ++ uint32_t skip_count; ++} dwc_otg_qh_t; ++ ++DWC_CIRCLEQ_HEAD(hc_list, dwc_hc); ++ ++typedef struct urb_tq_entry { ++ struct urb *urb; ++ DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries; ++} urb_tq_entry_t; ++ ++DWC_TAILQ_HEAD(urb_list, urb_tq_entry); ++ ++/** ++ * This structure holds the state of the HCD, including the non-periodic and ++ * periodic schedules. ++ */ ++struct dwc_otg_hcd { ++ /** The DWC otg device pointer */ ++ struct dwc_otg_device *otg_dev; ++ /** DWC OTG Core Interface Layer */ ++ dwc_otg_core_if_t *core_if; ++ ++ /** Function HCD driver callbacks */ ++ struct dwc_otg_hcd_function_ops *fops; ++ ++ /** Internal DWC HCD Flags */ ++ volatile union dwc_otg_hcd_internal_flags { ++ uint32_t d32; ++ struct { ++ unsigned port_connect_status_change:1; ++ unsigned port_connect_status:1; ++ unsigned port_reset_change:1; ++ unsigned port_enable_change:1; ++ unsigned port_suspend_change:1; ++ unsigned port_over_current_change:1; ++ unsigned port_l1_change:1; ++ unsigned reserved:26; ++ } b; ++ } flags; ++ ++ /** ++ * Inactive items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are not ++ * currently assigned to a host channel. ++ */ ++ dwc_list_link_t non_periodic_sched_inactive; ++ ++ /** ++ * Active items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are ++ * currently assigned to a host channel. ++ */ ++ dwc_list_link_t non_periodic_sched_active; ++ ++ /** ++ * Pointer to the next Queue Head to process in the active ++ * non-periodic schedule. ++ */ ++ dwc_list_link_t *non_periodic_qh_ptr; ++ ++ /** ++ * Inactive items in the periodic schedule. This is a list of QHs for ++ * periodic transfers that are _not_ scheduled for the next frame. ++ * Each QH in the list has an interval counter that determines when it ++ * needs to be scheduled for execution. This scheduling mechanism ++ * allows only a simple calculation for periodic bandwidth used (i.e. ++ * must assume that all periodic transfers may need to execute in the ++ * same frame). However, it greatly simplifies scheduling and should ++ * be sufficient for the vast majority of OTG hosts, which need to ++ * connect to a small number of peripherals at one time. ++ * ++ * Items move from this list to periodic_sched_ready when the QH ++ * interval counter is 0 at SOF. ++ */ ++ dwc_list_link_t periodic_sched_inactive; ++ ++ /** ++ * List of periodic QHs that are ready for execution in the next ++ * frame, but have not yet been assigned to host channels. ++ * ++ * Items move from this list to periodic_sched_assigned as host ++ * channels become available during the current frame. ++ */ ++ dwc_list_link_t periodic_sched_ready; ++ ++ /** ++ * List of periodic QHs to be executed in the next frame that are ++ * assigned to host channels. ++ * ++ * Items move from this list to periodic_sched_queued as the ++ * transactions for the QH are queued to the DWC_otg controller. ++ */ ++ dwc_list_link_t periodic_sched_assigned; ++ ++ /** ++ * List of periodic QHs that have been queued for execution. ++ * ++ * Items move from this list to either periodic_sched_inactive or ++ * periodic_sched_ready when the channel associated with the transfer ++ * is released. If the interval for the QH is 1, the item moves to ++ * periodic_sched_ready because it must be rescheduled for the next ++ * frame. Otherwise, the item moves to periodic_sched_inactive. ++ */ ++ dwc_list_link_t periodic_sched_queued; ++ ++ /** ++ * Total bandwidth claimed so far for periodic transfers. This value ++ * is in microseconds per (micro)frame. The assumption is that all ++ * periodic transfers may occur in the same (micro)frame. ++ */ ++ uint16_t periodic_usecs; ++ ++ /** ++ * Total bandwidth claimed so far for all periodic transfers ++ * in a frame. ++ * This will include a mixture of HS and FS transfers. ++ * Units are microseconds per (micro)frame. ++ * We have a budget per frame and have to schedule ++ * transactions accordingly. ++ * Watch out for the fact that things are actually scheduled for the ++ * "next frame". ++ */ ++ uint16_t frame_usecs[8]; ++ ++ ++ /** ++ * Frame number read from the core at SOF. The value ranges from 0 to ++ * DWC_HFNUM_MAX_FRNUM. ++ */ ++ uint16_t frame_number; ++ ++ /** ++ * Count of periodic QHs, if using several eps. For SOF enable/disable. ++ */ ++ uint16_t periodic_qh_count; ++ ++ /** ++ * Free host channels in the controller. This is a list of ++ * dwc_hc_t items. ++ */ ++ struct hc_list free_hc_list; ++ /** ++ * Number of host channels assigned to periodic transfers. Currently ++ * assuming that there is a dedicated host channel for each periodic ++ * transaction and at least one host channel available for ++ * non-periodic transactions. ++ */ ++ int periodic_channels; /* microframe_schedule==0 */ ++ ++ /** ++ * Number of host channels assigned to non-periodic transfers. ++ */ ++ int non_periodic_channels; /* microframe_schedule==0 */ ++ ++ /** ++ * Number of host channels assigned to non-periodic transfers. ++ */ ++ int available_host_channels; ++ ++ /** ++ * Array of pointers to the host channel descriptors. Allows accessing ++ * a host channel descriptor given the host channel number. This is ++ * useful in interrupt handlers. ++ */ ++ struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS]; ++ ++ /** ++ * Buffer to use for any data received during the status phase of a ++ * control transfer. Normally no data is transferred during the status ++ * phase. This buffer is used as a bit bucket. ++ */ ++ uint8_t *status_buf; ++ ++ /** ++ * DMA address for status_buf. ++ */ ++ dma_addr_t status_buf_dma; ++#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 ++ ++ /** ++ * Connection timer. An OTG host must display a message if the device ++ * does not connect. Started when the VBus power is turned on via ++ * sysfs attribute "buspower". ++ */ ++ dwc_timer_t *conn_timer; ++ ++ /* Tasket to do a reset */ ++ dwc_tasklet_t *reset_tasklet; ++ ++ dwc_tasklet_t *completion_tasklet; ++ struct urb_list completed_urb_list; ++ ++ /* */ ++ dwc_spinlock_t *lock; ++ dwc_spinlock_t *channel_lock; ++ /** ++ * Private data that could be used by OS wrapper. ++ */ ++ void *priv; ++ ++ uint8_t otg_port; ++ ++ /** Frame List */ ++ uint32_t *frame_list; ++ ++ /** Hub - Port assignment */ ++ int hub_port[128]; ++#ifdef FIQ_DEBUG ++ int hub_port_alloc[2048]; ++#endif ++ ++ /** Frame List DMA address */ ++ dma_addr_t frame_list_dma; ++ ++ struct fiq_stack *fiq_stack; ++ struct fiq_state *fiq_state; ++ ++ /** Virtual address for split transaction DMA bounce buffers */ ++ struct fiq_dma_blob *fiq_dmab; ++ ++#ifdef DEBUG ++ uint32_t frrem_samples; ++ uint64_t frrem_accum; ++ ++ uint32_t hfnum_7_samples_a; ++ uint64_t hfnum_7_frrem_accum_a; ++ uint32_t hfnum_0_samples_a; ++ uint64_t hfnum_0_frrem_accum_a; ++ uint32_t hfnum_other_samples_a; ++ uint64_t hfnum_other_frrem_accum_a; ++ ++ uint32_t hfnum_7_samples_b; ++ uint64_t hfnum_7_frrem_accum_b; ++ uint32_t hfnum_0_samples_b; ++ uint64_t hfnum_0_frrem_accum_b; ++ uint32_t hfnum_other_samples_b; ++ uint64_t hfnum_other_frrem_accum_b; ++#endif ++}; ++ ++/** @name Transaction Execution Functions */ ++/** @{ */ ++extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t ++ * hcd); ++extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, ++ dwc_otg_transaction_type_e tr_type); ++ ++int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh); ++void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh); ++ ++extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); ++extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh); ++extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num); ++ ++/** @} */ ++ ++/** @name Interrupt Handler Functions */ ++/** @{ */ ++extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint32_t num); ++extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++/** @} */ ++ ++/** @name Schedule Queue Functions */ ++/** @{ */ ++ ++/* Implemented in dwc_otg_hcd_queue.c */ ++extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * urb, int atomic_alloc); ++extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ int sched_csplit); ++ ++/** Remove and free a QH */ ++static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd, ++ dwc_otg_qh_t * qh) ++{ ++ dwc_irqflags_t flags; ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ dwc_otg_hcd_qh_free(hcd, qh); ++} ++ ++/** Allocates memory for a QH structure. ++ * @return Returns the memory allocate or NULL on error. */ ++static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc) ++{ ++ if (atomic_alloc) ++ return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t)); ++ else ++ return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t)); ++} ++ ++extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, ++ int atomic_alloc); ++extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb); ++extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_qh_t ** qh, int atomic_alloc); ++ ++/** Allocates memory for a QTD structure. ++ * @return Returns the memory allocate or NULL on error. */ ++static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc) ++{ ++ if (atomic_alloc) ++ return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t)); ++ else ++ return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t)); ++} ++ ++/** Frees the memory for a QTD structure. QTD should already be removed from ++ * list. ++ * @param qtd QTD to free.*/ ++static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd) ++{ ++ DWC_FREE(qtd); ++} ++ ++/** Removes a QTD from list. ++ * @param hcd HCD instance. ++ * @param qtd QTD to remove from list. ++ * @param qh QTD belongs to. ++ */ ++static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_qh_t * qh) ++{ ++ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); ++} ++ ++/** Remove and free a QTD ++ * Need to disable IRQ and hold hcd lock while calling this function out of ++ * interrupt servicing chain */ ++static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_qh_t * qh) ++{ ++ dwc_otg_hcd_qtd_remove(hcd, qtd, qh); ++ dwc_otg_hcd_qtd_free(qtd); ++} ++ ++/** @} */ ++ ++/** @name Descriptor DMA Supporting Functions */ ++/** @{ */ ++ ++extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status); ++ ++extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++ ++/** @} */ ++ ++/** @name Internal Functions */ ++/** @{ */ ++dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb); ++/** @} */ ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, ++ uint8_t devaddr); ++extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd); ++#endif ++ ++/** Gets the QH that contains the list_head */ ++#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry) ++ ++/** Gets the QTD that contains the list_head */ ++#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry) ++ ++/** Check if QH is non-periodic */ ++#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \ ++ (_qh_ptr_->ep_type == UE_CONTROL)) ++ ++/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ ++#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) ++ ++/** Packet size for any kind of endpoint descriptor */ ++#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) ++ ++/** ++ * Returns true if _frame1 is less than or equal to _frame2. The comparison is ++ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the ++ * frame number when the max frame number is reached. ++ */ ++static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2) ++{ ++ return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <= ++ (DWC_HFNUM_MAX_FRNUM >> 1); ++} ++ ++/** ++ * Returns true if _frame1 is greater than _frame2. The comparison is done ++ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame ++ * number when the max frame number is reached. ++ */ ++static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2) ++{ ++ return (frame1 != frame2) && ++ (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) < ++ (DWC_HFNUM_MAX_FRNUM >> 1)); ++} ++ ++/** ++ * Increments _frame by the amount specified by _inc. The addition is done ++ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. ++ */ ++static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc) ++{ ++ return (frame + inc) & DWC_HFNUM_MAX_FRNUM; ++} ++ ++static inline uint16_t dwc_full_frame_num(uint16_t frame) ++{ ++ return (frame & DWC_HFNUM_MAX_FRNUM) >> 3; ++} ++ ++static inline uint16_t dwc_micro_frame_num(uint16_t frame) ++{ ++ return frame & 0x7; ++} ++ ++void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd); ++ ++#ifdef DEBUG ++/** ++ * Macro to sample the remaining PHY clocks left in the current frame. This ++ * may be used during debugging to determine the average time it takes to ++ * execute sections of code. There are two possible sample points, "a" and ++ * "b", so the _letter argument must be one of these values. ++ * ++ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For ++ * example, "cat /sys/devices/lm0/hcd_frrem". ++ */ ++#define dwc_sample_frrem(_hcd, _qh, _letter) \ ++{ \ ++ hfnum_data_t hfnum; \ ++ dwc_otg_qtd_t *qtd; \ ++ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ ++ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ ++ hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ ++ switch (hfnum.b.frnum & 0x7) { \ ++ case 7: \ ++ _hcd->hfnum_7_samples_##_letter++; \ ++ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ case 0: \ ++ _hcd->hfnum_0_samples_##_letter++; \ ++ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ default: \ ++ _hcd->hfnum_other_samples_##_letter++; \ ++ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ } \ ++ } \ ++} ++#else ++#define dwc_sample_frrem(_hcd, _qh, _letter) ++#endif ++#endif ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c +@@ -0,0 +1,1132 @@ ++/*========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $ ++ * $Revision: #10 $ ++ * $Date: 2011/10/20 $ ++ * $Change: 1869464 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** @file ++ * This file contains Descriptor DMA support implementation for host mode. ++ */ ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++extern bool microframe_schedule; ++ ++static inline uint8_t frame_list_idx(uint16_t frame) ++{ ++ return (frame & (MAX_FRLIST_EN_NUM - 1)); ++} ++ ++static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed) ++{ ++ return (idx + inc) & ++ (((speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : ++ MAX_DMA_DESC_NUM_GENERIC) - 1); ++} ++ ++static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed) ++{ ++ return (idx - inc) & ++ (((speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : ++ MAX_DMA_DESC_NUM_GENERIC) - 1); ++} ++ ++static inline uint16_t max_desc_num(dwc_otg_qh_t * qh) ++{ ++ return (((qh->ep_type == UE_ISOCHRONOUS) ++ && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) ++ ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC); ++} ++static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh) ++{ ++ return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ++ ? ((qh->interval + 8 - 1) / 8) ++ : qh->interval); ++} ++ ++static int desc_list_alloc(dwc_otg_qh_t * qh) ++{ ++ int retval = 0; ++ ++ qh->desc_list = (dwc_otg_host_dma_desc_t *) ++ DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh), ++ &qh->desc_list_dma); ++ ++ if (!qh->desc_list) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__); ++ ++ } ++ ++ dwc_memset(qh->desc_list, 0x00, ++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); ++ ++ qh->n_bytes = ++ (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh)); ++ ++ if (!qh->n_bytes) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR ++ ("%s: Failed to allocate array for descriptors' size actual values\n", ++ __func__); ++ ++ } ++ return retval; ++ ++} ++ ++static void desc_list_free(dwc_otg_qh_t * qh) ++{ ++ if (qh->desc_list) { ++ DWC_DMA_FREE(max_desc_num(qh), qh->desc_list, ++ qh->desc_list_dma); ++ qh->desc_list = NULL; ++ } ++ ++ if (qh->n_bytes) { ++ DWC_FREE(qh->n_bytes); ++ qh->n_bytes = NULL; ++ } ++} ++ ++static int frame_list_alloc(dwc_otg_hcd_t * hcd) ++{ ++ int retval = 0; ++ if (hcd->frame_list) ++ return 0; ++ ++ hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM, ++ &hcd->frame_list_dma); ++ if (!hcd->frame_list) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: Frame List allocation failed\n", __func__); ++ } ++ ++ dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM); ++ ++ return retval; ++} ++ ++static void frame_list_free(dwc_otg_hcd_t * hcd) ++{ ++ if (!hcd->frame_list) ++ return; ++ ++ DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma); ++ hcd->frame_list = NULL; ++} ++ ++static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en) ++{ ++ ++ hcfg_data_t hcfg; ++ ++ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg); ++ ++ if (hcfg.b.perschedena) { ++ /* already enabled */ ++ return; ++ } ++ ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr, ++ hcd->frame_list_dma); ++ ++ switch (fr_list_en) { ++ case 64: ++ hcfg.b.frlisten = 3; ++ break; ++ case 32: ++ hcfg.b.frlisten = 2; ++ break; ++ case 16: ++ hcfg.b.frlisten = 1; ++ break; ++ case 8: ++ hcfg.b.frlisten = 0; ++ break; ++ default: ++ break; ++ } ++ ++ hcfg.b.perschedena = 1; ++ ++ DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n"); ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++ ++} ++ ++static void per_sched_disable(dwc_otg_hcd_t * hcd) ++{ ++ hcfg_data_t hcfg; ++ ++ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg); ++ ++ if (!hcfg.b.perschedena) { ++ /* already disabled */ ++ return; ++ } ++ hcfg.b.perschedena = 0; ++ ++ DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n"); ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++/* ++ * Activates/Deactivates FrameList entries for the channel ++ * based on endpoint servicing period. ++ */ ++void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable) ++{ ++ uint16_t i, j, inc; ++ dwc_hc_t *hc = NULL; ++ ++ if (!qh->channel) { ++ DWC_ERROR("qh->channel = %p", qh->channel); ++ return; ++ } ++ ++ if (!hcd) { ++ DWC_ERROR("------hcd = %p", hcd); ++ return; ++ } ++ ++ if (!hcd->frame_list) { ++ DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list); ++ return; ++ } ++ ++ hc = qh->channel; ++ inc = frame_incr_val(qh); ++ if (qh->ep_type == UE_ISOCHRONOUS) ++ i = frame_list_idx(qh->sched_frame); ++ else ++ i = 0; ++ ++ j = i; ++ do { ++ if (enable) ++ hcd->frame_list[j] |= (1 << hc->hc_num); ++ else ++ hcd->frame_list[j] &= ~(1 << hc->hc_num); ++ j = (j + inc) & (MAX_FRLIST_EN_NUM - 1); ++ } ++ while (j != i); ++ if (!enable) ++ return; ++ hc->schinfo = 0; ++ if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) { ++ j = 1; ++ /* TODO - check this */ ++ inc = (8 + qh->interval - 1) / qh->interval; ++ for (i = 0; i < inc; i++) { ++ hc->schinfo |= j; ++ j = j << qh->interval; ++ } ++ } else { ++ hc->schinfo = 0xff; ++ } ++} ++ ++#if 1 ++void dump_frame_list(dwc_otg_hcd_t * hcd) ++{ ++ int i = 0; ++ DWC_PRINTF("--FRAME LIST (hex) --\n"); ++ for (i = 0; i < MAX_FRLIST_EN_NUM; i++) { ++ DWC_PRINTF("%x\t", hcd->frame_list[i]); ++ if (!(i % 8) && i) ++ DWC_PRINTF("\n"); ++ } ++ DWC_PRINTF("\n----\n"); ++ ++} ++#endif ++ ++static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; ++ ++ dwc_hc_t *hc = qh->channel; ++ if (dwc_qh_is_non_per(qh)) { ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (!microframe_schedule) ++ hcd->non_periodic_channels--; ++ else ++ hcd->available_host_channels++; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ } else ++ update_frame_list(hcd, qh, 0); ++ ++ /* ++ * The condition is added to prevent double cleanup try in case of device ++ * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb(). ++ */ ++ if (hc->qh) { ++ dwc_otg_hc_cleanup(hcd->core_if, hc); ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++ hc->qh = NULL; ++ } ++ ++ qh->channel = NULL; ++ qh->ntd = 0; ++ ++ if (qh->desc_list) { ++ dwc_memset(qh->desc_list, 0x00, ++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); ++ } ++} ++ ++/** ++ * Initializes a QH structure's Descriptor DMA related members. ++ * Allocates memory for descriptor list. ++ * On first periodic QH, allocates memory for FrameList ++ * and enables periodic scheduling. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int retval = 0; ++ ++ if (qh->do_split) { ++ DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n"); ++ return -1; ++ } ++ ++ retval = desc_list_alloc(qh); ++ ++ if ((retval == 0) ++ && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) { ++ if (!hcd->frame_list) { ++ retval = frame_list_alloc(hcd); ++ /* Enable periodic schedule on first periodic QH */ ++ if (retval == 0) ++ per_sched_enable(hcd, MAX_FRLIST_EN_NUM); ++ } ++ } ++ ++ qh->ntd = 0; ++ ++ return retval; ++} ++ ++/** ++ * Frees descriptor list memory associated with the QH. ++ * If QH is periodic and the last, frees FrameList memory ++ * and disables periodic scheduling. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ */ ++void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ desc_list_free(qh); ++ ++ /* ++ * Channel still assigned due to some reasons. ++ * Seen on Isoc URB dequeue. Channel halted but no subsequent ++ * ChHalted interrupt to release the channel. Afterwards ++ * when it comes here from endpoint disable routine ++ * channel remains assigned. ++ */ ++ if (qh->channel) ++ release_channel_ddma(hcd, qh); ++ ++ if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) ++ && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) { ++ ++ per_sched_disable(hcd); ++ frame_list_free(hcd); ++ } ++} ++ ++static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx) ++{ ++ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { ++ /* ++ * Descriptor set(8 descriptors) index ++ * which is 8-aligned. ++ */ ++ return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8; ++ } else { ++ return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1)); ++ } ++} ++ ++/* ++ * Determine starting frame for Isochronous transfer. ++ * Few frames skipped to prevent race condition with HC. ++ */ ++static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ uint8_t * skip_frames) ++{ ++ uint16_t frame = 0; ++ hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd); ++ ++ /* sched_frame is always frame number(not uFrame) both in FS and HS !! */ ++ ++ /* ++ * skip_frames is used to limit activated descriptors number ++ * to avoid the situation when HC services the last activated ++ * descriptor firstly. ++ * Example for FS: ++ * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor ++ * corresponding to curr_frame+1, the descriptor corresponding to frame 2 ++ * will be fetched. If the number of descriptors is max=64 (or greather) the ++ * list will be fully programmed with Active descriptors and it is possible ++ * case(rare) that the latest descriptor(considering rollback) corresponding ++ * to frame 2 will be serviced first. HS case is more probable because, in fact, ++ * up to 11 uframes(16 in the code) may be skipped. ++ */ ++ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { ++ /* ++ * Consider uframe counter also, to start xfer asap. ++ * If half of the frame elapsed skip 2 frames otherwise ++ * just 1 frame. ++ * Starting descriptor index must be 8-aligned, so ++ * if the current frame is near to complete the next one ++ * is skipped as well. ++ */ ++ ++ if (dwc_micro_frame_num(hcd->frame_number) >= 5) { ++ *skip_frames = 2 * 8; ++ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); ++ } else { ++ *skip_frames = 1 * 8; ++ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); ++ } ++ ++ frame = dwc_full_frame_num(frame); ++ } else { ++ /* ++ * Two frames are skipped for FS - the current and the next. ++ * But for descriptor programming, 1 frame(descriptor) is enough, ++ * see example above. ++ */ ++ *skip_frames = 1; ++ frame = dwc_frame_num_inc(hcd->frame_number, 2); ++ } ++ ++ return frame; ++} ++ ++/* ++ * Calculate initial descriptor index for isochronous transfer ++ * based on scheduled frame. ++ */ ++static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ uint16_t frame = 0, fr_idx, fr_idx_tmp; ++ uint8_t skip_frames = 0; ++ /* ++ * With current ISOC processing algorithm the channel is being ++ * released when no more QTDs in the list(qh->ntd == 0). ++ * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. ++ * ++ * So qh->channel != NULL branch is not used and just not removed from the ++ * source file. It is required for another possible approach which is, ++ * do not disable and release the channel when ISOC session completed, ++ * just move QH to inactive schedule until new QTD arrives. ++ * On new QTD, the QH moved back to 'ready' schedule, ++ * starting frame and therefore starting desc_index are recalculated. ++ * In this case channel is released only on ep_disable. ++ */ ++ ++ /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */ ++ if (qh->channel) { ++ frame = calc_starting_frame(hcd, qh, &skip_frames); ++ /* ++ * Calculate initial descriptor index based on FrameList current bitmap ++ * and servicing period. ++ */ ++ fr_idx_tmp = frame_list_idx(frame); ++ fr_idx = ++ (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - ++ fr_idx_tmp) ++ % frame_incr_val(qh); ++ fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM; ++ } else { ++ qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames); ++ fr_idx = frame_list_idx(qh->sched_frame); ++ } ++ ++ qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx); ++ ++ return skip_frames; ++} ++ ++#define ISOC_URB_GIVEBACK_ASAP ++ ++#define MAX_ISOC_XFER_SIZE_FS 1023 ++#define MAX_ISOC_XFER_SIZE_HS 3072 ++#define DESCNUM_THRESHOLD 4 ++ ++static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ uint8_t skip_frames) ++{ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint16_t idx, inc, n_desc, ntd_max, max_xfer_size; ++ ++ idx = qh->td_last; ++ inc = qh->interval; ++ n_desc = 0; ++ ++ ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval; ++ if (skip_frames && !qh->channel) ++ ntd_max = ntd_max - skip_frames / qh->interval; ++ ++ max_xfer_size = ++ (qh->dev_speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS : ++ MAX_ISOC_XFER_SIZE_FS; ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { ++ while ((qh->ntd < ntd_max) ++ && (qtd->isoc_frame_index_last < ++ qtd->urb->packet_count)) { ++ ++ dma_desc = &qh->desc_list[idx]; ++ dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t)); ++ ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last]; ++ ++ if (frame_desc->length > max_xfer_size) ++ qh->n_bytes[idx] = max_xfer_size; ++ else ++ qh->n_bytes[idx] = frame_desc->length; ++ dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx]; ++ dma_desc->status.b_isoc.a = 1; ++ dma_desc->status.b_isoc.sts = 0; ++ ++ dma_desc->buf = qtd->urb->dma + frame_desc->offset; ++ ++ qh->ntd++; ++ ++ qtd->isoc_frame_index_last++; ++ ++#ifdef ISOC_URB_GIVEBACK_ASAP ++ /* ++ * Set IOC for each descriptor corresponding to the ++ * last frame of the URB. ++ */ ++ if (qtd->isoc_frame_index_last == ++ qtd->urb->packet_count) ++ dma_desc->status.b_isoc.ioc = 1; ++ ++#endif ++ idx = desclist_idx_inc(idx, inc, qh->dev_speed); ++ n_desc++; ++ ++ } ++ qtd->in_process = 1; ++ } ++ ++ qh->td_last = idx; ++ ++#ifdef ISOC_URB_GIVEBACK_ASAP ++ /* Set IOC for the last descriptor if descriptor list is full */ ++ if (qh->ntd == ntd_max) { ++ idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed); ++ qh->desc_list[idx].status.b_isoc.ioc = 1; ++ } ++#else ++ /* ++ * Set IOC bit only for one descriptor. ++ * Always try to be ahead of HW processing, ++ * i.e. on IOC generation driver activates next descriptors but ++ * core continues to process descriptors followed the one with IOC set. ++ */ ++ ++ if (n_desc > DESCNUM_THRESHOLD) { ++ /* ++ * Move IOC "up". Required even if there is only one QTD ++ * in the list, cause QTDs migth continue to be queued, ++ * but during the activation it was only one queued. ++ * Actually more than one QTD might be in the list if this function called ++ * from XferCompletion - QTDs was queued during HW processing of the previous ++ * descriptor chunk. ++ */ ++ idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed); ++ } else { ++ /* ++ * Set the IOC for the latest descriptor ++ * if either number of descriptor is not greather than threshold ++ * or no more new descriptors activated. ++ */ ++ idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); ++ } ++ ++ qh->desc_list[idx].status.b_isoc.ioc = 1; ++#endif ++} ++ ++static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ ++ dwc_hc_t *hc; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ dwc_otg_qtd_t *qtd; ++ int num_packets, len, n_desc = 0; ++ ++ hc = qh->channel; ++ ++ /* ++ * Start with hc->xfer_buff initialized in ++ * assign_and_init_hc(), then if SG transfer consists of multiple URBs, ++ * this pointer re-assigned to the buffer of the currently processed QTD. ++ * For non-SG request there is always one QTD active. ++ */ ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { ++ ++ if (n_desc) { ++ /* SG request - more than 1 QTDs */ ++ hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length; ++ hc->xfer_len = qtd->urb->length - qtd->urb->actual_length; ++ } ++ ++ qtd->n_desc = 0; ++ ++ do { ++ dma_desc = &qh->desc_list[n_desc]; ++ len = hc->xfer_len; ++ ++ if (len > MAX_DMA_DESC_SIZE) ++ len = MAX_DMA_DESC_SIZE - hc->max_packet + 1; ++ ++ if (hc->ep_is_in) { ++ if (len > 0) { ++ num_packets = (len + hc->max_packet - 1) / hc->max_packet; ++ } else { ++ /* Need 1 packet for transfer length of 0. */ ++ num_packets = 1; ++ } ++ /* Always program an integral # of max packets for IN transfers. */ ++ len = num_packets * hc->max_packet; ++ } ++ ++ dma_desc->status.b.n_bytes = len; ++ ++ qh->n_bytes[n_desc] = len; ++ ++ if ((qh->ep_type == UE_CONTROL) ++ && (qtd->control_phase == DWC_OTG_CONTROL_SETUP)) ++ dma_desc->status.b.sup = 1; /* Setup Packet */ ++ ++ dma_desc->status.b.a = 1; /* Active descriptor */ ++ dma_desc->status.b.sts = 0; ++ ++ dma_desc->buf = ++ ((unsigned long)hc->xfer_buff & 0xffffffff); ++ ++ /* ++ * Last descriptor(or single) of IN transfer ++ * with actual size less than MaxPacket. ++ */ ++ if (len > hc->xfer_len) { ++ hc->xfer_len = 0; ++ } else { ++ hc->xfer_buff += len; ++ hc->xfer_len -= len; ++ } ++ ++ qtd->n_desc++; ++ n_desc++; ++ } ++ while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC)); ++ ++ ++ qtd->in_process = 1; ++ ++ if (qh->ep_type == UE_CONTROL) ++ break; ++ ++ if (n_desc == MAX_DMA_DESC_NUM_GENERIC) ++ break; ++ } ++ ++ if (n_desc) { ++ /* Request Transfer Complete interrupt for the last descriptor */ ++ qh->desc_list[n_desc - 1].status.b.ioc = 1; ++ /* End of List indicator */ ++ qh->desc_list[n_desc - 1].status.b.eol = 1; ++ ++ hc->ntd = n_desc; ++ } ++} ++ ++/** ++ * For Control and Bulk endpoints initializes descriptor list ++ * and starts the transfer. ++ * ++ * For Interrupt and Isochronous endpoints initializes descriptor list ++ * then updates FrameList, marking appropriate entries as active. ++ * In case of Isochronous, the starting descriptor index is calculated based ++ * on the scheduled frame, but only on the first transfer descriptor within a session. ++ * Then starts the transfer via enabling the channel. ++ * For Isochronous endpoint the channel is not halted on XferComplete ++ * interrupt so remains assigned to the endpoint(QH) until session is done. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ /* Channel is already assigned */ ++ dwc_hc_t *hc = qh->channel; ++ uint8_t skip_frames = 0; ++ ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ init_non_isoc_dma_desc(hcd, qh); ++ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ break; ++ case DWC_OTG_EP_TYPE_INTR: ++ init_non_isoc_dma_desc(hcd, qh); ++ ++ update_frame_list(hcd, qh, 1); ++ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ break; ++ case DWC_OTG_EP_TYPE_ISOC: ++ ++ if (!qh->ntd) ++ skip_frames = recalc_initial_desc_idx(hcd, qh); ++ ++ init_isoc_dma_desc(hcd, qh, skip_frames); ++ ++ if (!hc->xfer_started) { ++ ++ update_frame_list(hcd, qh, 1); ++ ++ /* ++ * Always set to max, instead of actual size. ++ * Otherwise ntd will be changed with ++ * channel being enabled. Not recommended. ++ * ++ */ ++ hc->ntd = max_desc_num(qh); ++ /* Enable channel only once for ISOC */ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ } ++ ++ break; ++ default: ++ ++ break; ++ } ++} ++ ++static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint16_t idx, remain; ++ uint8_t urb_compl; ++ ++ qh = hc->qh; ++ idx = qh->td_first; ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) ++ qtd->in_process = 0; ++ return; ++ } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || ++ (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) { ++ /* ++ * Channel is halted in these error cases. ++ * Considered as serious issues. ++ * Complete all URBs marking all frames as failed, ++ * irrespective whether some of the descriptors(frames) succeeded or no. ++ * Pass error code to completion routine as well, to ++ * update urb->status, some of class drivers might use it to stop ++ * queing transfer requests. ++ */ ++ int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) ++ ? (-DWC_E_IO) ++ : (-DWC_E_OVERFLOW); ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ for (idx = 0; idx < qtd->urb->packet_count; idx++) { ++ frame_desc = &qtd->urb->iso_descs[idx]; ++ frame_desc->status = err; ++ } ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ } ++ return; ++ } ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ ++ if (!qtd->in_process) ++ break; ++ ++ urb_compl = 0; ++ ++ do { ++ ++ dma_desc = &qh->desc_list[idx]; ++ ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0; ++ ++ if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) { ++ /* ++ * XactError or, unable to complete all the transactions ++ * in the scheduled micro-frame/frame, ++ * both indicated by DMA_DESC_STS_PKTERR. ++ */ ++ qtd->urb->error_count++; ++ frame_desc->actual_length = qh->n_bytes[idx] - remain; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } else { ++ /* Success */ ++ ++ frame_desc->actual_length = qh->n_bytes[idx] - remain; ++ frame_desc->status = 0; ++ } ++ ++ if (++qtd->isoc_frame_index == qtd->urb->packet_count) { ++ /* ++ * urb->status is not used for isoc transfers here. ++ * The individual frame_desc status are used instead. ++ */ ++ ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ ++ /* ++ * This check is necessary because urb_dequeue can be called ++ * from urb complete callback(sound driver example). ++ * All pending URBs are dequeued there, so no need for ++ * further processing. ++ */ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ return; ++ } ++ ++ urb_compl = 1; ++ ++ } ++ ++ qh->ntd--; ++ ++ /* Stop if IOC requested descriptor reached */ ++ if (dma_desc->status.b_isoc.ioc) { ++ idx = desclist_idx_inc(idx, qh->interval, hc->speed); ++ goto stop_scan; ++ } ++ ++ idx = desclist_idx_inc(idx, qh->interval, hc->speed); ++ ++ if (urb_compl) ++ break; ++ } ++ while (idx != qh->td_first); ++ } ++stop_scan: ++ qh->td_first = idx; ++} ++ ++uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_host_dma_desc_t * dma_desc, ++ dwc_otg_halt_status_e halt_status, ++ uint32_t n_bytes, uint8_t * xfer_done) ++{ ++ ++ uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0; ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) { ++ urb->status = -DWC_E_IO; ++ return 1; ++ } ++ if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) { ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_STALL: ++ urb->status = -DWC_E_PIPE; ++ break; ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ urb->status = -DWC_E_OVERFLOW; ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ urb->status = -DWC_E_PROTOCOL; ++ break; ++ default: ++ DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__, ++ halt_status); ++ break; ++ } ++ return 1; ++ } ++ ++ if (dma_desc->status.b.a == 1) { ++ DWC_DEBUGPL(DBG_HCDV, ++ "Active descriptor encountered on channel %d\n", ++ hc->hc_num); ++ return 0; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) { ++ if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ urb->actual_length += n_bytes - remain; ++ if (remain || urb->actual_length == urb->length) { ++ /* ++ * For Control Data stage do not set urb->status=0 to prevent ++ * URB callback. Set it when Status phase done. See below. ++ */ ++ *xfer_done = 1; ++ } ++ ++ } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) { ++ urb->status = 0; ++ *xfer_done = 1; ++ } ++ /* No handling for SETUP stage */ ++ } else { ++ /* BULK and INTR */ ++ urb->actual_length += n_bytes - remain; ++ if (remain || urb->actual_length == urb->length) { ++ urb->status = 0; ++ *xfer_done = 1; ++ } ++ } ++ ++ return 0; ++} ++ ++static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_hcd_urb_t *urb = NULL; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint32_t n_bytes, n_desc, i; ++ uint8_t failed = 0, xfer_done; ++ ++ n_desc = 0; ++ ++ qh = hc->qh; ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ qtd->in_process = 0; ++ } ++ return; ++ } ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { ++ ++ urb = qtd->urb; ++ ++ n_bytes = 0; ++ xfer_done = 0; ++ ++ for (i = 0; i < qtd->n_desc; i++) { ++ dma_desc = &qh->desc_list[n_desc]; ++ ++ n_bytes = qh->n_bytes[n_desc]; ++ ++ failed = ++ update_non_isoc_urb_state_ddma(hcd, hc, qtd, ++ dma_desc, ++ halt_status, n_bytes, ++ &xfer_done); ++ ++ if (failed ++ || (xfer_done ++ && (urb->status != -DWC_E_IN_PROGRESS))) { ++ ++ hcd->fops->complete(hcd, urb->priv, urb, ++ urb->status); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ ++ if (failed) ++ goto stop_scan; ++ } else if (qh->ep_type == UE_CONTROL) { ++ if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) { ++ if (urb->length > 0) { ++ qtd->control_phase = DWC_OTG_CONTROL_DATA; ++ } else { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ } ++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); ++ } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ if (xfer_done) { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); ++ } else if (i + 1 == qtd->n_desc) { ++ /* ++ * Last descriptor for Control data stage which is ++ * not completed yet. ++ */ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ } ++ } ++ ++ n_desc++; ++ } ++ ++ } ++ ++stop_scan: ++ ++ if (qh->ep_type != UE_CONTROL) { ++ /* ++ * Resetting the data toggle for bulk ++ * and interrupt endpoints in case of stall. See handle_hc_stall_intr() ++ */ ++ if (halt_status == DWC_OTG_HC_XFER_STALL) ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ else ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ hcint_data_t hcint; ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ if (hcint.b.nyet) { ++ /* ++ * Got a NYET on the last transaction of the transfer. It ++ * means that the endpoint should be in the PING state at the ++ * beginning of the next transfer. ++ */ ++ qh->ping_state = 1; ++ clear_hc_int(hc_regs, nyet); ++ } ++ ++ } ++ ++} ++ ++/** ++ * This function is called from interrupt handlers. ++ * Scans the descriptor list, updates URB's status and ++ * calls completion routine for the URB if it's done. ++ * Releases the channel to be used by other transfers. ++ * In case of Isochronous endpoint the channel is not halted until ++ * the end of the session, i.e. QTD list is empty. ++ * If periodic channel released the FrameList is updated accordingly. ++ * ++ * Calls transaction selection routines to activate pending transfers. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param hc Host channel, the transfer is completed on. ++ * @param hc_regs Host channel registers. ++ * @param halt_status Reason the channel is being halted, ++ * or just XferComplete for isochronous transfer ++ */ ++void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ uint8_t continue_isoc_xfer = 0; ++ dwc_otg_transaction_type_e tr_type; ++ dwc_otg_qh_t *qh = hc->qh; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ ++ complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ ++ /* Release the channel if halted or session completed */ ++ if (halt_status != DWC_OTG_HC_XFER_COMPLETE || ++ DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ ++ /* Halt the channel if session completed */ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ dwc_otg_hc_halt(hcd->core_if, hc, halt_status); ++ } ++ ++ release_channel_ddma(hcd, qh); ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } else { ++ /* Keep in assigned schedule to continue transfer */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &qh->qh_list_entry); ++ continue_isoc_xfer = 1; ++ ++ } ++ /** @todo Consider the case when period exceeds FrameList size. ++ * Frame Rollover interrupt should be used. ++ */ ++ } else { ++ /* Scan descriptor list to complete the URB(s), then release the channel */ ++ complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ ++ release_channel_ddma(hcd, qh); ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ ++ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ /* Add back to inactive non-periodic schedule on normal completion */ ++ dwc_otg_hcd_qh_add(hcd, qh); ++ } ++ ++ } ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) { ++ if (continue_isoc_xfer) { ++ if (tr_type == DWC_OTG_TRANSACTION_NONE) { ++ tr_type = DWC_OTG_TRANSACTION_PERIODIC; ++ } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) { ++ tr_type = DWC_OTG_TRANSACTION_ALL; ++ } ++ } ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h +@@ -0,0 +1,417 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $ ++ * $Revision: #12 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++#ifndef __DWC_HCD_IF_H__ ++#define __DWC_HCD_IF_H__ ++ ++#include "dwc_otg_core_if.h" ++ ++/** @file ++ * This file defines DWC_OTG HCD Core API. ++ */ ++ ++struct dwc_otg_hcd; ++typedef struct dwc_otg_hcd dwc_otg_hcd_t; ++ ++struct dwc_otg_hcd_urb; ++typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t; ++ ++/** @name HCD Function Driver Callbacks */ ++/** @{ */ ++ ++/** This function is called whenever core switches to host mode. */ ++typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd); ++ ++/** This function is called when device has been disconnected */ ++typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd); ++ ++/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */ ++typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle, ++ uint32_t * hub_addr, ++ uint32_t * port_addr); ++/** Via this function HCD core gets device speed */ ++typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle); ++ ++/** This function is called when urb is completed */ ++typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int32_t status); ++ ++/** Via this function HCD core gets b_hnp_enable parameter */ ++typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd); ++ ++struct dwc_otg_hcd_function_ops { ++ dwc_otg_hcd_start_cb_t start; ++ dwc_otg_hcd_disconnect_cb_t disconnect; ++ dwc_otg_hcd_hub_info_from_urb_cb_t hub_info; ++ dwc_otg_hcd_speed_from_urb_cb_t speed; ++ dwc_otg_hcd_complete_urb_cb_t complete; ++ dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable; ++}; ++/** @} */ ++ ++/** @name HCD Core API */ ++/** @{ */ ++/** This function allocates dwc_otg_hcd structure and returns pointer on it. */ ++extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void); ++ ++/** This function should be called to initiate HCD Core. ++ * ++ * @param hcd The HCD ++ * @param core_if The DWC_OTG Core ++ * ++ * Returns -DWC_E_NO_MEMORY if no enough memory. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if); ++ ++/** Frees HCD ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd); ++ ++/** This function should be called on every hardware interrupt. ++ * ++ * @param dwc_otg_hcd The HCD ++ * ++ * Returns non zero if interrupt is handled ++ * Return 0 if interrupt is not handled ++ */ ++extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++ ++/** This function is used to handle the fast interrupt ++ * ++ */ ++extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void); ++ ++/** ++ * Returns private data set by ++ * dwc_otg_hcd_set_priv_data function. ++ * ++ * @param hcd The HCD ++ */ ++extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Set private data. ++ * ++ * @param hcd The HCD ++ * @param priv_data pointer to be stored in private data ++ */ ++extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data); ++ ++/** ++ * This function initializes the HCD Core. ++ * ++ * @param hcd The HCD ++ * @param fops The Function Driver Operations data structure containing pointers to all callbacks. ++ * ++ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd, ++ struct dwc_otg_hcd_function_ops *fops); ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Handles hub class-specific requests. ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param typeReq Request Type ++ * @param wValue wValue from control request ++ * @param wIndex wIndex from control request ++ * @param buf data buffer ++ * @param wLength data buffer length ++ * ++ * Returns -DWC_E_INVALID if invalid argument is passed ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint16_t typeReq, uint16_t wValue, ++ uint16_t wIndex, uint8_t * buf, ++ uint16_t wLength); ++ ++/** ++ * Returns otg port number. ++ * ++ * @param hcd The HCD ++ */ ++extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Returns OTG version - either 1.3 or 2.0. ++ * ++ * @param core_if The core_if structure pointer ++ */ ++extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Returns 1 if currently core is acting as B host, and 0 otherwise. ++ * ++ * @param hcd The HCD ++ */ ++extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Returns current frame number. ++ * ++ * @param hcd The HCD ++ */ ++extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Dumps hcd state. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Dump the average frame remaining at SOF. This can be used to ++ * determine average interrupt latency. Frame remaining is also shown for ++ * start transfer and two additional sample points. ++ * Currently this function is not implemented. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Sends LPM transaction to the local device. ++ * ++ * @param hcd The HCD ++ * @param devaddr Device Address ++ * @param hird Host initiated resume duration ++ * @param bRemoteWake Value of bRemoteWake field in LPM transaction ++ * ++ * Returns negative value if sending LPM transaction was not succeeded. ++ * Returns 0 on success. ++ */ ++extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, ++ uint8_t hird, uint8_t bRemoteWake); ++ ++/* URB interface */ ++ ++/** ++ * Allocates memory for dwc_otg_hcd_urb structure. ++ * Allocated memory should be freed by call of DWC_FREE. ++ * ++ * @param hcd The HCD ++ * @param iso_desc_count Count of ISOC descriptors ++ * @param atomic_alloc Specefies whether to perform atomic allocation. ++ */ ++extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, ++ int iso_desc_count, ++ int atomic_alloc); ++ ++/** ++ * Set pipe information in URB. ++ * ++ * @param hcd_urb DWC_OTG URB ++ * @param devaddr Device Address ++ * @param ep_num Endpoint Number ++ * @param ep_type Endpoint Type ++ * @param ep_dir Endpoint Direction ++ * @param mps Max Packet Size ++ */ ++extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb, ++ uint8_t devaddr, uint8_t ep_num, ++ uint8_t ep_type, uint8_t ep_dir, ++ uint16_t mps); ++ ++/* Transfer flags */ ++#define URB_GIVEBACK_ASAP 0x1 ++#define URB_SEND_ZERO_PACKET 0x2 ++ ++/** ++ * Sets dwc_otg_hcd_urb parameters. ++ * ++ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function. ++ * @param urb_handle Unique handle for request, this will be passed back ++ * to function driver in completion callback. ++ * @param buf The buffer for the data ++ * @param dma The DMA buffer for the data ++ * @param buflen Transfer length ++ * @param sp Buffer for setup data ++ * @param sp_dma DMA address of setup data buffer ++ * @param flags Transfer flags ++ * @param interval Polling interval for interrupt or isochronous transfers. ++ */ ++extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb, ++ void *urb_handle, void *buf, ++ dwc_dma_t dma, uint32_t buflen, void *sp, ++ dwc_dma_t sp_dma, uint32_t flags, ++ uint16_t interval); ++ ++/** Gets status from dwc_otg_hcd_urb ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb); ++ ++/** Gets actual length from dwc_otg_hcd_urb ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb); ++ ++/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * ++ dwc_otg_urb); ++ ++/** Set ISOC descriptor offset and length ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ * @param offset Offset from beginig of buffer. ++ * @param length Transaction length ++ */ ++extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num, uint32_t offset, ++ uint32_t length); ++ ++/** Get status of ISOC descriptor, specified by desc_num ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, int desc_num); ++ ++/** Get actual length of ISOC descriptor, specified by desc_num ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, ++ int desc_num); ++ ++/** Queue URB. After transfer is completes, the complete callback will be called with the URB status ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param ep_handle Out parameter for returning endpoint handle ++ * @param atomic_alloc Flag to do atomic allocation if needed ++ * ++ * Returns -DWC_E_NO_DEVICE if no device is connected. ++ * Returns -DWC_E_NO_MEMORY if there is no enough memory. ++ * Returns 0 on success. ++ */ ++extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, ++ void **ep_handle, int atomic_alloc); ++ ++/** De-queue the specified URB ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb); ++ ++/** Frees resources in the DWC_otg controller related to a given endpoint. ++ * Any URBs for the endpoint must already be dequeued. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function ++ * @param retry Number of retries if there are queued transfers. ++ * ++ * Returns -DWC_E_INVALID if invalid arguments are passed. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, ++ int retry); ++ ++/* Resets the data toggle in qh structure. This function can be called from ++ * usb_clear_halt routine. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function ++ * ++ * Returns -DWC_E_INVALID if invalid arguments are passed. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle); ++ ++/** Returns 1 if status of specified port is changed and 0 otherwise. ++ * ++ * @param hcd The HCD ++ * @param port Port number ++ */ ++extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port); ++ ++/** Call this function to check if bandwidth was allocated for specified endpoint. ++ * Only for ISOC and INTERRUPT endpoints. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, ++ void *ep_handle); ++ ++/** Call this function to check if bandwidth was freed for specified endpoint. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle); ++ ++/** Returns bandwidth allocated for specified endpoint in microseconds. ++ * Only for ISOC and INTERRUPT endpoints. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, ++ void *ep_handle); ++ ++/** @} */ ++ ++#endif /* __DWC_HCD_IF_H__ */ ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +@@ -0,0 +1,2713 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $ ++ * $Revision: #89 $ ++ * $Date: 2011/10/20 $ ++ * $Change: 1869487 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++#include ++#include ++#include ++ ++ ++extern bool microframe_schedule; ++ ++/** @file ++ * This file contains the implementation of the HCD Interrupt handlers. ++ */ ++ ++int fiq_done, int_done; ++ ++#ifdef FIQ_DEBUG ++char buffer[1000*16]; ++int wptr; ++void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...) ++{ ++ FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB; ++ va_list args; ++ char text[17]; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) }; ++ ++ if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR) ++ { ++ local_fiq_disable(); ++ snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937); ++ va_start(args, fmt); ++ vsnprintf(text+8, 9, fmt, args); ++ va_end(args); ++ ++ memcpy(buffer + wptr, text, 16); ++ wptr = (wptr + 16) % sizeof(buffer); ++ local_fiq_enable(); ++ } ++} ++#endif ++ ++/** This function handles interrupts for the HCD. */ ++int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int retval = 0; ++ static int last_time; ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ hfnum_data_t hfnum; ++ haintmsk_data_t haintmsk; ++ ++#ifdef DEBUG ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ ++#endif ++ ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ ++ /* Exit from ISR if core is hibernated */ ++ if (core_if->hibernation_suspend == 1) { ++ goto exit_handler_routine; ++ } ++ DWC_SPINLOCK(dwc_otg_hcd->lock); ++ /* Check if HOST Mode */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); ++ /* Pull in from the FIQ's disabled mask */ ++ gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32); ++ dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0; ++ } ++ ++ if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) { ++ gintsts.b.hcintr = 1; ++ } ++ ++ /* Danger will robinson: fake a SOF if necessary */ ++ if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) { ++ gintsts.b.sofintr = 1; ++ } ++ gintsts.d32 &= gintmsk.d32; ++ ++ if (fiq_enable) { ++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } ++ ++ if (!gintsts.d32) { ++ goto exit_handler_routine; ++ } ++ ++#ifdef DEBUG ++ // We should be OK doing this because the common interrupts should already have been serviced ++ /* Don't print debug message in the interrupt handler on SOF */ ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCDI, "\n"); ++#endif ++ ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCDI, ++ "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n", ++ gintsts.d32, core_if); ++#endif ++ hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum); ++ if (gintsts.b.sofintr) { ++ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); ++ } ++ ++ if (gintsts.b.rxstsqlvl) { ++ retval |= ++ dwc_otg_hcd_handle_rx_status_q_level_intr ++ (dwc_otg_hcd); ++ } ++ if (gintsts.b.nptxfempty) { ++ retval |= ++ dwc_otg_hcd_handle_np_tx_fifo_empty_intr ++ (dwc_otg_hcd); ++ } ++ if (gintsts.b.i2cintr) { ++ /** @todo Implement i2cintr handler. */ ++ } ++ if (gintsts.b.portintr) { ++ ++ gintmsk_data_t gintmsk = { .b.portintr = 1}; ++ retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd); ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ } ++ } ++ if (gintsts.b.hcintr) { ++ retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd); ++ } ++ if (gintsts.b.ptxfempty) { ++ retval |= ++ dwc_otg_hcd_handle_perio_tx_fifo_empty_intr ++ (dwc_otg_hcd); ++ } ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ { ++ DWC_DEBUGPL(DBG_HCDI, ++ "DWC OTG HCD Finished Servicing Interrupts\n"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", ++ DWC_READ_REG32(&global_regs->gintsts)); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", ++ DWC_READ_REG32(&global_regs->gintmsk)); ++ } ++#endif ++ ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCDI, "\n"); ++#endif ++ ++ } ++ ++exit_handler_routine: ++ if (fiq_enable) { ++ gintmsk_data_t gintmsk_new; ++ haintmsk_data_t haintmsk_new; ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); ++ gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32; ++ if(fiq_fsm_enable) ++ haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32; ++ else ++ haintmsk_new.d32 = 0x0000FFFF; ++ ++ /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */ ++ if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) { ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16)); ++ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) { ++ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR"); ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16))); ++ while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17))) ++ ; ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31)); ++ dwc_otg_hcd->fiq_state->mphi_int_count = 0; ++ } ++ int_done++; ++ } ++ haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); ++ /* Re-enable interrupts that the FIQ masked (first time round) */ ++ FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32); ++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); ++ local_fiq_enable(); ++ ++ if ((jiffies / HZ) > last_time) { ++ //dwc_otg_qh_t *qh; ++ //dwc_list_link_t *cur; ++ /* Once a second output the fiq and irq numbers, useful for debug */ ++ last_time = jiffies / HZ; ++ // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d", ++ // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels, ++ // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done); ++ //printk(KERN_WARNING "Periodic queues:\n"); ++ } ++ } ++ ++ DWC_SPINUNLOCK(dwc_otg_hcd->lock); ++ return retval; ++} ++ ++#ifdef DWC_TRACK_MISSED_SOFS ++ ++#warning Compiling code to track missed SOFs ++#define FRAME_NUM_ARRAY_SIZE 1000 ++/** ++ * This function is for debug only. ++ */ ++static inline void track_missed_sofs(uint16_t curr_frame_number) ++{ ++ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; ++ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; ++ static int frame_num_idx = 0; ++ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; ++ static int dumped_frame_num_array = 0; ++ ++ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { ++ if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != ++ curr_frame_number) { ++ frame_num_array[frame_num_idx] = curr_frame_number; ++ last_frame_num_array[frame_num_idx++] = last_frame_num; ++ } ++ } else if (!dumped_frame_num_array) { ++ int i; ++ DWC_PRINTF("Frame Last Frame\n"); ++ DWC_PRINTF("----- ----------\n"); ++ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { ++ DWC_PRINTF("0x%04x 0x%04x\n", ++ frame_num_array[i], last_frame_num_array[i]); ++ } ++ dumped_frame_num_array = 1; ++ } ++ last_frame_num = curr_frame_number; ++} ++#endif ++ ++/** ++ * Handles the start-of-frame interrupt in host mode. Non-periodic ++ * transactions may be queued to the DWC_otg controller for the current ++ * (micro)frame. Periodic transactions may be queued to the controller for the ++ * next (micro)frame. ++ */ ++int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) ++{ ++ hfnum_data_t hfnum; ++ gintsts_data_t gintsts = { .d32 = 0 }; ++ dwc_list_link_t *qh_entry; ++ dwc_otg_qh_t *qh; ++ dwc_otg_transaction_type_e tr_type; ++ int did_something = 0; ++ int32_t next_sched_frame = -1; ++ ++ hfnum.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); ++#endif ++ hcd->frame_number = hfnum.b.frnum; ++ ++#ifdef DEBUG ++ hcd->frrem_accum += hfnum.b.frrem; ++ hcd->frrem_samples++; ++#endif ++ ++#ifdef DWC_TRACK_MISSED_SOFS ++ track_missed_sofs(hcd->frame_number); ++#endif ++ /* Determine whether any periodic QHs should be executed. */ ++ qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive); ++ while (qh_entry != &hcd->periodic_sched_inactive) { ++ qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry); ++ qh_entry = qh_entry->next; ++ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) { ++ ++ /* ++ * Move QH to the ready list to be executed next ++ * (micro)frame. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, ++ &qh->qh_list_entry); ++ ++ did_something = 1; ++ } ++ else ++ { ++ if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame)) ++ { ++ next_sched_frame = qh->sched_frame; ++ } ++ } ++ } ++ if (fiq_enable) ++ hcd->fiq_state->next_sched_frame = next_sched_frame; ++ ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ did_something = 1; ++ } ++ ++ /* Clear interrupt - but do not trample on the FIQ sof */ ++ if (!fiq_fsm_enable) { ++ gintsts.b.sofintr = 1; ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); ++ } ++ return 1; ++} ++ ++/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at ++ * least one packet in the Rx FIFO. The packets are moved from the FIFO to ++ * memory if the DWC_otg controller is operating in Slave mode. */ ++int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ host_grxsts_data_t grxsts; ++ dwc_hc_t *hc = NULL; ++ ++ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); ++ ++ grxsts.d32 = ++ DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp); ++ ++ hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; ++ if (!hc) { ++ DWC_ERROR("Unable to get corresponding channel\n"); ++ return 0; ++ } ++ ++ /* Packet Status */ ++ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); ++ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); ++ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, ++ hc->data_pid_start); ++ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN: ++ /* Read the data into the host buffer. */ ++ if (grxsts.b.bcnt > 0) { ++ dwc_otg_read_packet(dwc_otg_hcd->core_if, ++ hc->xfer_buff, grxsts.b.bcnt); ++ ++ /* Update the HC fields for the next packet received. */ ++ hc->xfer_count += grxsts.b.bcnt; ++ hc->xfer_buff += grxsts.b.bcnt; ++ } ++ ++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: ++ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: ++ case DWC_GRXSTS_PKTSTS_CH_HALTED: ++ /* Handled in interrupt, just ignore data */ ++ break; ++ default: ++ DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", ++ grxsts.b.pktsts); ++ break; ++ } ++ ++ return 1; ++} ++ ++/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More ++ * data packets may be written to the FIFO for OUT transfers. More requests ++ * may be written to the non-periodic request queue for IN transfers. This ++ * interrupt is enabled only in Slave mode. */ ++int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); ++ dwc_otg_hcd_queue_transactions(dwc_otg_hcd, ++ DWC_OTG_TRANSACTION_NON_PERIODIC); ++ return 1; ++} ++ ++/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data ++ * packets may be written to the FIFO for OUT transfers. More requests may be ++ * written to the periodic request queue for IN transfers. This interrupt is ++ * enabled only in Slave mode. */ ++int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); ++ dwc_otg_hcd_queue_transactions(dwc_otg_hcd, ++ DWC_OTG_TRANSACTION_PERIODIC); ++ return 1; ++} ++ ++/** There are multiple conditions that can cause a port interrupt. This function ++ * determines which interrupt conditions have occurred and handles them ++ * appropriately. */ ++int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int retval = 0; ++ hprt0_data_t hprt0; ++ hprt0_data_t hprt0_modify; ++ ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ ++ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in ++ * GINTSTS */ ++ ++ hprt0_modify.b.prtena = 0; ++ hprt0_modify.b.prtconndet = 0; ++ hprt0_modify.b.prtenchng = 0; ++ hprt0_modify.b.prtovrcurrchng = 0; ++ ++ /* Port Connect Detected ++ * Set flag and clear if detected */ ++ if (dwc_otg_hcd->core_if->hibernation_suspend == 1) { ++ // Dont modify port status if we are in hibernation state ++ hprt0_modify.b.prtconndet = 1; ++ hprt0_modify.b.prtenchng = 1; ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ return retval; ++ } ++ ++ if (hprt0.b.prtconndet) { ++ /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */ ++ if (dwc_otg_hcd->core_if->adp_enable && ++ dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) { ++ DWC_PRINTF("PORT CONNECT DETECTED ----------------\n"); ++ DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer); ++ dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0; ++ /* TODO - check if this is required, as ++ * host initialization was already performed ++ * after initial ADP probing ++ */ ++ /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0; ++ dwc_otg_core_init(dwc_otg_hcd->core_if); ++ dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if); ++ cil_hcd_start(dwc_otg_hcd->core_if);*/ ++ } else { ++ ++ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " ++ "Port Connect Detected--\n", hprt0.d32); ++ dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ dwc_otg_hcd->flags.b.port_connect_status = 1; ++ hprt0_modify.b.prtconndet = 1; ++ ++ /* B-Device has connected, Delete the connection timer. */ ++ DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer); ++ } ++ /* The Hub driver asserts a reset when it sees port connect ++ * status change flag */ ++ retval |= 1; ++ } ++ ++ /* Port Enable Changed ++ * Clear if detected - Set internal flag if disabled */ ++ if (hprt0.b.prtenchng) { ++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " ++ "Port Enable Changed--\n", hprt0.d32); ++ hprt0_modify.b.prtenchng = 1; ++ if (hprt0.b.prtena == 1) { ++ hfir_data_t hfir; ++ int do_reset = 0; ++ dwc_otg_core_params_t *params = ++ dwc_otg_hcd->core_if->core_params; ++ dwc_otg_core_global_regs_t *global_regs = ++ dwc_otg_hcd->core_if->core_global_regs; ++ dwc_otg_host_if_t *host_if = ++ dwc_otg_hcd->core_if->host_if; ++ ++ /* Every time when port enables calculate ++ * HFIR.FrInterval ++ */ ++ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir); ++ hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if); ++ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32); ++ ++ /* Check if we need to adjust the PHY clock speed for ++ * low power and adjust it */ ++ if (params->host_support_fs_ls_low_power) { ++ gusbcfg_data_t usbcfg; ++ ++ usbcfg.d32 = ++ DWC_READ_REG32(&global_regs->gusbcfg); ++ ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ++ || hprt0.b.prtspd == ++ DWC_HPRT0_PRTSPD_FULL_SPEED) { ++ /* ++ * Low power ++ */ ++ hcfg_data_t hcfg; ++ if (usbcfg.b.phylpwrclksel == 0) { ++ /* Set PHY low power clock select for FS/LS devices */ ++ usbcfg.b.phylpwrclksel = 1; ++ DWC_WRITE_REG32 ++ (&global_regs->gusbcfg, ++ usbcfg.d32); ++ do_reset = 1; ++ } ++ ++ hcfg.d32 = ++ DWC_READ_REG32 ++ (&host_if->host_global_regs->hcfg); ++ ++ if (hprt0.b.prtspd == ++ DWC_HPRT0_PRTSPD_LOW_SPEED ++ && params->host_ls_low_power_phy_clk ++ == ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) ++ { ++ /* 6 MHZ */ ++ DWC_DEBUGPL(DBG_CIL, ++ "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); ++ if (hcfg.b.fslspclksel != ++ DWC_HCFG_6_MHZ) { ++ hcfg.b.fslspclksel = ++ DWC_HCFG_6_MHZ; ++ DWC_WRITE_REG32 ++ (&host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ do_reset = 1; ++ } ++ } else { ++ /* 48 MHZ */ ++ DWC_DEBUGPL(DBG_CIL, ++ "FS_PHY programming HCFG to 48 MHz ()\n"); ++ if (hcfg.b.fslspclksel != ++ DWC_HCFG_48_MHZ) { ++ hcfg.b.fslspclksel = ++ DWC_HCFG_48_MHZ; ++ DWC_WRITE_REG32 ++ (&host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ do_reset = 1; ++ } ++ } ++ } else { ++ /* ++ * Not low power ++ */ ++ if (usbcfg.b.phylpwrclksel == 1) { ++ usbcfg.b.phylpwrclksel = 0; ++ DWC_WRITE_REG32 ++ (&global_regs->gusbcfg, ++ usbcfg.d32); ++ do_reset = 1; ++ } ++ } ++ ++ if (do_reset) { ++ DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet); ++ } ++ } ++ ++ if (!do_reset) { ++ /* Port has been enabled set the reset change flag */ ++ dwc_otg_hcd->flags.b.port_reset_change = 1; ++ } ++ } else { ++ dwc_otg_hcd->flags.b.port_enable_change = 1; ++ } ++ retval |= 1; ++ } ++ ++ /** Overcurrent Change Interrupt */ ++ if (hprt0.b.prtovrcurrchng) { ++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " ++ "Port Overcurrent Changed--\n", hprt0.d32); ++ dwc_otg_hcd->flags.b.port_over_current_change = 1; ++ hprt0_modify.b.prtovrcurrchng = 1; ++ retval |= 1; ++ } ++ ++ /* Clear Port Interrupts */ ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); ++ ++ return retval; ++} ++ ++/** This interrupt indicates that one or more host channels has a pending ++ * interrupt. There are multiple conditions that can cause each host channel ++ * interrupt. This function determines which conditions have occurred for each ++ * host channel interrupt and handles them appropriately. */ ++int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int i; ++ int retval = 0; ++ haint_data_t haint = { .d32 = 0 } ; ++ ++ /* Clear appropriate bits in HCINTn to clear the interrupt bit in ++ * GINTSTS */ ++ ++ if (!fiq_fsm_enable) ++ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); ++ ++ // Overwrite with saved interrupts from fiq handler ++ if(fiq_fsm_enable) ++ { ++ /* check the mask? */ ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); ++ haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint); ++ dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0; ++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } ++ ++ for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) { ++ if (haint.b2.chint & (1 << i)) { ++ retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i); ++ } ++ } ++ ++ return retval; ++} ++ ++/** ++ * Gets the actual length of a transfer after the transfer halts. _halt_status ++ * holds the reason for the halt. ++ * ++ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, ++ * *short_read is set to 1 upon return if less than the requested ++ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon ++ * return. short_read may also be NULL on entry, in which case it remains ++ * unchanged. ++ */ ++static uint32_t get_actual_xfer_length(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status, ++ int *short_read) ++{ ++ hctsiz_data_t hctsiz; ++ uint32_t length; ++ ++ if (short_read != NULL) { ++ *short_read = 0; ++ } ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ if (hc->ep_is_in) { ++ length = hc->xfer_len - hctsiz.b.xfersize; ++ if (short_read != NULL) { ++ *short_read = (hctsiz.b.xfersize != 0); ++ } ++ } else if (hc->qh->do_split) { ++ //length = split_out_xfersize[hc->hc_num]; ++ length = qtd->ssplit_out_xfer_count; ++ } else { ++ length = hc->xfer_len; ++ } ++ } else { ++ /* ++ * Must use the hctsiz.pktcnt field to determine how much data ++ * has been transferred. This field reflects the number of ++ * packets that have been transferred via the USB. This is ++ * always an integral number of packets if the transfer was ++ * halted before its normal completion. (Can't use the ++ * hctsiz.xfersize field because that reflects the number of ++ * bytes transferred via the AHB, not the USB). ++ */ ++ length = ++ (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet; ++ } ++ ++ return length; ++} ++ ++/** ++ * Updates the state of the URB after a Transfer Complete interrupt on the ++ * host channel. Updates the actual_length field of the URB based on the ++ * number of bytes transferred via the host channel. Sets the URB status ++ * if the data transfer is finished. ++ * ++ * @return 1 if the data transfer specified by the URB is completely finished, ++ * 0 otherwise. ++ */ ++static int update_urb_state_xfer_comp(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_hcd_urb_t * urb, ++ dwc_otg_qtd_t * qtd) ++{ ++ int xfer_done = 0; ++ int short_read = 0; ++ ++ int xfer_length; ++ ++ xfer_length = get_actual_xfer_length(hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE, ++ &short_read); ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && xfer_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, ++ xfer_length); ++ } ++ ++ urb->actual_length += xfer_length; ++ ++ if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) && ++ (urb->flags & URB_SEND_ZERO_PACKET) ++ && (urb->actual_length == urb->length) ++ && !(urb->length % hc->max_packet)) { ++ xfer_done = 0; ++ } else if (short_read || urb->actual_length >= urb->length) { ++ xfer_done = 1; ++ urb->status = 0; ++ } ++ ++#ifdef DEBUG ++ { ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", ++ __func__, (hc->ep_is_in ? "IN" : "OUT"), ++ hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len); ++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", ++ hctsiz.b.xfersize); ++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", ++ urb->length); ++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", ++ urb->actual_length); ++ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", ++ short_read, xfer_done); ++ } ++#endif ++ ++ return xfer_done; ++} ++ ++/* ++ * Save the starting data toggle for the next transfer. The data toggle is ++ * saved in the QH for non-control transfers and it's saved in the QTD for ++ * control transfers. ++ */ ++void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd) ++{ ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ ++ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { ++ dwc_otg_qh_t *qh = hc->qh; ++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } else { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA1; ++ } ++ } else { ++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } else { ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA1; ++ } ++ } ++} ++ ++/** ++ * Updates the state of an Isochronous URB when the transfer is stopped for ++ * any reason. The fields of the current entry in the frame descriptor array ++ * are set based on the transfer state and the input _halt_status. Completes ++ * the Isochronous URB if all the URB frames have been completed. ++ * ++ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be ++ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. ++ */ ++static dwc_otg_halt_status_e ++update_isoc_urb_state(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ dwc_otg_halt_status_e ret_val = halt_status; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_COMPLETE: ++ frame_desc->status = 0; ++ frame_desc->actual_length = ++ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ hc->qh->dw_align_buf, frame_desc->actual_length); ++ } ++ ++ break; ++ case DWC_OTG_HC_XFER_FRAME_OVERRUN: ++ urb->error_count++; ++ if (hc->ep_is_in) { ++ frame_desc->status = -DWC_E_NO_STREAM_RES; ++ } else { ++ frame_desc->status = -DWC_E_COMMUNICATION; ++ } ++ frame_desc->actual_length = 0; ++ break; ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ urb->error_count++; ++ frame_desc->status = -DWC_E_OVERFLOW; ++ /* Don't need to update actual_length in this case. */ ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ urb->error_count++; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ frame_desc->actual_length = ++ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ hc->qh->dw_align_buf, frame_desc->actual_length); ++ } ++ /* Skip whole frame */ ++ if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && ++ hc->ep_is_in && hcd->core_if->dma_enable) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ } ++ ++ break; ++ default: ++ DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status); ++ break; ++ } ++ if (++qtd->isoc_frame_index == urb->packet_count) { ++ /* ++ * urb->status is not used for isoc transfers. ++ * The individual frame_desc statuses are used instead. ++ */ ++ hcd->fops->complete(hcd, urb->priv, urb, 0); ++ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ ret_val = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ return ret_val; ++} ++ ++/** ++ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic ++ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are ++ * still linked to the QH, the QH is added to the end of the inactive ++ * non-periodic schedule. For periodic QHs, removes the QH from the periodic ++ * schedule if no more QTDs are linked to the QH. ++ */ ++static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd) ++{ ++ int continue_split = 0; ++ dwc_otg_qtd_t *qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd); ++ ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ ++ if (qtd->complete_split) { ++ continue_split = 1; ++ } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID || ++ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) { ++ continue_split = 1; ++ } ++ ++ if (free_qtd) { ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ continue_split = 0; ++ } ++ ++ qh->channel = NULL; ++ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split); ++} ++ ++/** ++ * Releases a host channel for use by other transfers. Attempts to select and ++ * queue more transactions since at least one host channel is available. ++ * ++ * @param hcd The HCD state structure. ++ * @param hc The host channel to release. ++ * @param qtd The QTD associated with the host channel. This QTD may be freed ++ * if the transfer is complete or an error has occurred. ++ * @param halt_status Reason the channel is being released. This status ++ * determines the actions taken by this function. ++ */ ++static void release_channel(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_transaction_type_e tr_type; ++ int free_qtd; ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; ++ ++ int hog_port = 0; ++ ++ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", ++ __func__, hc->hc_num, halt_status, hc->xfer_len); ++ ++ if(fiq_fsm_enable && hc->do_split) { ++ if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) { ++ if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID || ++ hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) { ++ hog_port = 0; ++ } ++ } ++ } ++ ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_URB_COMPLETE: ++ free_qtd = 1; ++ break; ++ case DWC_OTG_HC_XFER_AHB_ERR: ++ case DWC_OTG_HC_XFER_STALL: ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ free_qtd = 1; ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ if (qtd->error_count >= 3) { ++ DWC_DEBUGPL(DBG_HCDV, ++ " Complete URB with transaction error\n"); ++ free_qtd = 1; ++ qtd->urb->status = -DWC_E_PROTOCOL; ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_PROTOCOL); ++ } else { ++ free_qtd = 0; ++ } ++ break; ++ case DWC_OTG_HC_XFER_URB_DEQUEUE: ++ /* ++ * The QTD has already been removed and the QH has been ++ * deactivated. Don't want to do anything except release the ++ * host channel and try to queue more transfers. ++ */ ++ goto cleanup; ++ case DWC_OTG_HC_XFER_NO_HALT_STATUS: ++ free_qtd = 0; ++ break; ++ case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE: ++ DWC_DEBUGPL(DBG_HCDV, ++ " Complete URB with I/O error\n"); ++ free_qtd = 1; ++ qtd->urb->status = -DWC_E_IO; ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_IO); ++ break; ++ default: ++ free_qtd = 0; ++ break; ++ } ++ ++ deactivate_qh(hcd, hc->qh, free_qtd); ++ ++cleanup: ++ /* ++ * Release the host channel for use by other transfers. The cleanup ++ * function clears the channel interrupt enables and conditions, so ++ * there's no need to clear the Channel Halted interrupt separately. ++ */ ++ if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH) ++ dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num); ++ dwc_otg_hc_cleanup(hcd->core_if, hc); ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++ ++ if (!microframe_schedule) { ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ hcd->non_periodic_channels--; ++ break; ++ ++ default: ++ /* ++ * Don't release reservations for periodic channels here. ++ * That's done when a periodic transfer is descheduled (i.e. ++ * when the QH is removed from the periodic schedule). ++ */ ++ break; ++ } ++ } else { ++ ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ hcd->available_host_channels++; ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels); ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ } ++ ++ /* Try to queue more transfers now that there's a free channel. */ ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++} ++ ++/** ++ * Halts a host channel. If the channel cannot be halted immediately because ++ * the request queue is full, this function ensures that the FIFO empty ++ * interrupt for the appropriate queue is enabled so that the halt request can ++ * be queued when there is space in the request queue. ++ * ++ * This function may also be called in DMA mode. In that case, the channel is ++ * simply released since the core always halts the channel automatically in ++ * DMA mode. ++ */ ++static void halt_channel(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status) ++{ ++ if (hcd->core_if->dma_enable) { ++ release_channel(hcd, hc, qtd, halt_status); ++ return; ++ } ++ ++ /* Slave mode processing... */ ++ dwc_otg_hc_halt(hcd->core_if, hc, halt_status); ++ ++ if (hc->halt_on_queue) { ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ dwc_otg_core_global_regs_t *global_regs; ++ global_regs = hcd->core_if->core_global_regs; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK) { ++ /* ++ * Make sure the Non-periodic Tx FIFO empty interrupt ++ * is enabled so that the non-periodic schedule will ++ * be processed. ++ */ ++ gintmsk.b.nptxfempty = 1; ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); ++ } ++ } else { ++ /* ++ * Move the QH from the periodic queued schedule to ++ * the periodic assigned schedule. This allows the ++ * halt to be queued when the periodic schedule is ++ * processed. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &hc->qh->qh_list_entry); ++ ++ /* ++ * Make sure the Periodic Tx FIFO Empty interrupt is ++ * enabled so that the periodic schedule will be ++ * processed. ++ */ ++ gintmsk.b.ptxfempty = 1; ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); ++ } ++ } ++ } ++} ++ ++/** ++ * Performs common cleanup for non-periodic transfers after a Transfer ++ * Complete interrupt. This function should be called after any endpoint type ++ * specific handling is finished to release the host channel. ++ */ ++static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ hcint_data_t hcint; ++ ++ qtd->error_count = 0; ++ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ if (hcint.b.nyet) { ++ /* ++ * Got a NYET on the last transaction of the transfer. This ++ * means that the endpoint should be in the PING state at the ++ * beginning of the next transfer. ++ */ ++ hc->qh->ping_state = 1; ++ clear_hc_int(hc_regs, nyet); ++ } ++ ++ /* ++ * Always halt and release the host channel to make it available for ++ * more transfers. There may still be more phases for a control ++ * transfer or more data packets for a bulk transfer at this point, ++ * but the host channel is still halted. A channel will be reassigned ++ * to the transfer when the non-periodic schedule is processed after ++ * the channel is released. This allows transactions to be queued ++ * properly via dwc_otg_hcd_queue_transactions, which also enables the ++ * Tx FIFO Empty interrupt if necessary. ++ */ ++ if (hc->ep_is_in) { ++ /* ++ * IN transfers in Slave mode require an explicit disable to ++ * halt the channel. (In DMA mode, this call simply releases ++ * the channel.) ++ */ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } else { ++ /* ++ * The channel is automatically disabled by the core for OUT ++ * transfers in Slave mode. ++ */ ++ release_channel(hcd, hc, qtd, halt_status); ++ } ++} ++ ++/** ++ * Performs common cleanup for periodic transfers after a Transfer Complete ++ * interrupt. This function should be called after any endpoint type specific ++ * handling is finished to release the host channel. ++ */ ++static void complete_periodic_xfer(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ hctsiz_data_t hctsiz; ++ qtd->error_count = 0; ++ ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) { ++ /* Core halts channel in these cases. */ ++ release_channel(hcd, hc, qtd, halt_status); ++ } else { ++ /* Flush any outstanding requests from the Tx queue. */ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++} ++ ++static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ uint32_t len; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ ++ len = get_actual_xfer_length(hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE, NULL); ++ ++ if (!len) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ return 0; ++ } ++ frame_desc->actual_length += len; ++ ++ if (hc->align_buff && len) ++ dwc_memcpy(qtd->urb->buf + frame_desc->offset + ++ qtd->isoc_split_offset, hc->qh->dw_align_buf, len); ++ qtd->isoc_split_offset += len; ++ ++ if (frame_desc->length == frame_desc->actual_length) { ++ frame_desc->status = 0; ++ qtd->isoc_frame_index++; ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ } ++ ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ ++ return 1; /* Indicates that channel released */ ++} ++ ++/** ++ * Handles a host channel Transfer Complete interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ int urb_xfer_done; ++ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Transfer Complete--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ if (pipe_type == UE_ISOCHRONOUS) { ++ /* Do not disable the interrupt, just clear it */ ++ clear_hc_int(hc_regs, xfercomp); ++ return 1; ++ } ++ goto handle_xfercomp_done; ++ } ++ ++ /* ++ * Handle xfer complete on CSPLIT. ++ */ ++ ++ if (hc->qh->do_split) { ++ if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in ++ && hcd->core_if->dma_enable) { ++ if (qtd->complete_split ++ && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, ++ qtd)) ++ goto handle_xfercomp_done; ++ } else { ++ qtd->complete_split = 0; ++ } ++ } ++ ++ /* Update the QTD and URB states. */ ++ switch (pipe_type) { ++ case UE_CONTROL: ++ switch (qtd->control_phase) { ++ case DWC_OTG_CONTROL_SETUP: ++ if (urb->length > 0) { ++ qtd->control_phase = DWC_OTG_CONTROL_DATA; ++ } else { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ } ++ DWC_DEBUGPL(DBG_HCDV, ++ " Control setup transaction done\n"); ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ break; ++ case DWC_OTG_CONTROL_DATA:{ ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, ++ qtd); ++ if (urb_xfer_done) { ++ qtd->control_phase = ++ DWC_OTG_CONTROL_STATUS; ++ DWC_DEBUGPL(DBG_HCDV, ++ " Control data transfer done\n"); ++ } else { ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ break; ++ } ++ case DWC_OTG_CONTROL_STATUS: ++ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); ++ if (urb->status == -DWC_E_IN_PROGRESS) { ++ urb->status = 0; ++ } ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ break; ++ } ++ ++ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ case UE_BULK: ++ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); ++ if (urb_xfer_done) { ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ case UE_INTERRUPT: ++ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); ++ ++ /* ++ * Interrupt URB is done on the first transfer complete ++ * interrupt. ++ */ ++ if (urb_xfer_done) { ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ case UE_ISOCHRONOUS: ++ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); ++ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) { ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE); ++ } ++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ } ++ ++handle_xfercomp_done: ++ disable_hc_int(hc_regs, xfercompl); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel STALL interrupt. This handler may be called in ++ * either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "STALL Received--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL); ++ goto handle_stall_done; ++ } ++ ++ if (pipe_type == UE_CONTROL) { ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE); ++ } ++ ++ if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) { ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE); ++ /* ++ * USB protocol requires resetting the data toggle for bulk ++ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) ++ * setup command is issued to the endpoint. Anticipate the ++ * CLEAR_FEATURE command since a STALL has occurred and reset ++ * the data toggle now. ++ */ ++ hc->qh->data_toggle = 0; ++ } ++ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL); ++ ++handle_stall_done: ++ disable_hc_int(hc_regs, stall); ++ ++ return 1; ++} ++ ++/* ++ * Updates the state of the URB when a transfer has been stopped due to an ++ * abnormal condition before the transfer completes. Modifies the ++ * actual_length field of the URB to reflect the number of bytes that have ++ * actually been transferred via the host channel. ++ */ ++static void update_urb_state_xfer_intr(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_hcd_urb_t * urb, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd, ++ halt_status, NULL); ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && bytes_transferred && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, ++ bytes_transferred); ++ } ++ ++ urb->actual_length += bytes_transferred; ++ ++#ifdef DEBUG ++ { ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", ++ __func__, (hc->ep_is_in ? "IN" : "OUT"), ++ hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", ++ hc->start_pkt_count); ++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); ++ DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet); ++ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", ++ bytes_transferred); ++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", ++ urb->actual_length); ++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", ++ urb->length); ++ } ++#endif ++} ++ ++/** ++ * Handles a host channel NAK interrupt. This handler may be called in either ++ * DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "NAK Received--\n", hc->hc_num); ++ ++ /* ++ * When we get bulk NAKs then remember this so we holdoff on this qh until ++ * the beginning of the next frame ++ */ ++ switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_BULK: ++ case UE_CONTROL: ++ if (nak_holdoff && qtd->qh->do_split) ++ hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd); ++ } ++ ++ /* ++ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and ++ * interrupt. Re-start the SSPLIT transfer. ++ */ ++ if (hc->do_split) { ++ if (hc->complete_split) { ++ qtd->error_count = 0; ++ } ++ qtd->complete_split = 0; ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ goto handle_nak_done; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ if (hcd->core_if->dma_enable && hc->ep_is_in) { ++ /* ++ * NAK interrupts are enabled on bulk/control IN ++ * transfers in DMA mode for the sole purpose of ++ * resetting the error count after a transaction error ++ * occurs. The core will continue transferring data. ++ * Disable other interrupts unmasked for the same ++ * reason. ++ */ ++ disable_hc_int(hc_regs, datatglerr); ++ disable_hc_int(hc_regs, ack); ++ qtd->error_count = 0; ++ goto handle_nak_done; ++ } ++ ++ /* ++ * NAK interrupts normally occur during OUT transfers in DMA ++ * or Slave mode. For IN transfers, more requests will be ++ * queued as request queue space is available. ++ */ ++ qtd->error_count = 0; ++ ++ if (!hc->qh->ping_state) { ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, ++ DWC_OTG_HC_XFER_NAK); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) ++ hc->qh->ping_state = 1; ++ } ++ ++ /* ++ * Halt the channel so the transfer can be re-started from ++ * the appropriate point or the PING protocol will ++ * start/continue. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ break; ++ case UE_INTERRUPT: ++ qtd->error_count = 0; ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ break; ++ case UE_ISOCHRONOUS: ++ /* Should never get called for isochronous transfers. */ ++ DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n"); ++ break; ++ } ++ ++handle_nak_done: ++ disable_hc_int(hc_regs, nak); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel ACK interrupt. This interrupt is enabled when ++ * performing the PING protocol in Slave mode, when errors occur during ++ * either Slave mode or DMA mode, and during Start Split transactions. ++ */ ++static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "ACK Received--\n", hc->hc_num); ++ ++ if (hc->do_split) { ++ /* ++ * Handle ACK on SSPLIT. ++ * ACK should not occur in CSPLIT. ++ */ ++ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) { ++ qtd->ssplit_out_xfer_count = hc->xfer_len; ++ } ++ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) { ++ /* Don't need complete for isochronous out transfers. */ ++ qtd->complete_split = 1; ++ } ++ ++ /* ISOC OUT */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { ++ switch (hc->xact_pos) { ++ case DWC_HCSPLIT_XACTPOS_ALL: ++ break; ++ case DWC_HCSPLIT_XACTPOS_END: ++ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ qtd->isoc_split_offset = 0; ++ break; ++ case DWC_HCSPLIT_XACTPOS_BEGIN: ++ case DWC_HCSPLIT_XACTPOS_MID: ++ /* ++ * For BEGIN or MID, calculate the length for ++ * the next microframe to determine the correct ++ * SSPLIT token, either MID or END. ++ */ ++ { ++ struct dwc_otg_hcd_iso_packet_desc ++ *frame_desc; ++ ++ frame_desc = ++ &qtd->urb-> ++ iso_descs[qtd->isoc_frame_index]; ++ qtd->isoc_split_offset += 188; ++ ++ if ((frame_desc->length - ++ qtd->isoc_split_offset) <= 188) { ++ qtd->isoc_split_pos = ++ DWC_HCSPLIT_XACTPOS_END; ++ } else { ++ qtd->isoc_split_pos = ++ DWC_HCSPLIT_XACTPOS_MID; ++ } ++ ++ } ++ break; ++ } ++ } else { ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); ++ } ++ } else { ++ /* ++ * An unmasked ACK on a non-split DMA transaction is ++ * for the sole purpose of resetting error counts. Disable other ++ * interrupts unmasked for the same reason. ++ */ ++ if(hcd->core_if->dma_enable) { ++ disable_hc_int(hc_regs, datatglerr); ++ disable_hc_int(hc_regs, nak); ++ } ++ qtd->error_count = 0; ++ ++ if (hc->qh->ping_state) { ++ hc->qh->ping_state = 0; ++ /* ++ * Halt the channel so the transfer can be re-started ++ * from the appropriate point. This only happens in ++ * Slave mode. In DMA mode, the ping_state is cleared ++ * when the transfer is started because the core ++ * automatically executes the PING, then the transfer. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); ++ } ++ } ++ ++ /* ++ * If the ACK occurred when _not_ in the PING state, let the channel ++ * continue transferring data after clearing the error count. ++ */ ++ ++ disable_hc_int(hc_regs, ack); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel NYET interrupt. This interrupt should only occur on ++ * Bulk and Control OUT endpoints and for complete split transactions. If a ++ * NYET occurs at the same time as a Transfer Complete interrupt, it is ++ * handled in the xfercomp interrupt handler, not here. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "NYET Received--\n", hc->hc_num); ++ ++ /* ++ * NYET on CSPLIT ++ * re-do the CSPLIT immediately on non-periodic ++ */ ++ if (hc->do_split && hc->complete_split) { ++ if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ && hcd->core_if->dma_enable) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ if (++qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } ++ else ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ goto handle_nyet_done; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ int frnum = dwc_otg_hcd_get_frame_number(hcd); ++ ++ // With the FIQ running we only ever see the failed NYET ++ if (dwc_full_frame_num(frnum) != ++ dwc_full_frame_num(hc->qh->sched_frame) || ++ fiq_fsm_enable) { ++ /* ++ * No longer in the same full speed frame. ++ * Treat this as a transaction error. ++ */ ++#if 0 ++ /** @todo Fix system performance so this can ++ * be treated as an error. Right now complete ++ * splits cannot be scheduled precisely enough ++ * due to other system activity, so this error ++ * occurs regularly in Slave mode. ++ */ ++ qtd->error_count++; ++#endif ++ qtd->complete_split = 0; ++ halt_channel(hcd, hc, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ /** @todo add support for isoc release */ ++ goto handle_nyet_done; ++ } ++ } ++ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); ++ goto handle_nyet_done; ++ } ++ ++ hc->qh->ping_state = 1; ++ qtd->error_count = 0; ++ ++ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, ++ DWC_OTG_HC_XFER_NYET); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ ++ /* ++ * Halt the channel and re-start the transfer so the PING ++ * protocol will start. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); ++ ++handle_nyet_done: ++ disable_hc_int(hc_regs, nyet); ++ return 1; ++} ++ ++/** ++ * Handles a host channel babble interrupt. This handler may be called in ++ * either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Babble Error--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_BABBLE_ERR); ++ goto handle_babble_done; ++ } ++ ++ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_OVERFLOW); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR); ++ } else { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_BABBLE_ERR); ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ ++handle_babble_done: ++ disable_hc_int(hc_regs, bblerr); ++ return 1; ++} ++ ++/** ++ * Handles a host channel AHB error interrupt. This handler is only called in ++ * DMA mode. ++ */ ++static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ uint32_t hcdma; ++ char *pipetype, *speed; ++ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "AHB Error--\n", hc->hc_num); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcdma = DWC_READ_REG32(&hc_regs->hcdma); ++ ++ DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num); ++ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); ++ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); ++ DWC_ERROR(" Device address: %d\n", ++ dwc_otg_hcd_get_dev_addr(&urb->pipe_info)); ++ DWC_ERROR(" Endpoint: %d, %s\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), ++ (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT")); ++ ++ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { ++ case UE_CONTROL: ++ pipetype = "CONTROL"; ++ break; ++ case UE_BULK: ++ pipetype = "BULK"; ++ break; ++ case UE_INTERRUPT: ++ pipetype = "INTERRUPT"; ++ break; ++ case UE_ISOCHRONOUS: ++ pipetype = "ISOCHRONOUS"; ++ break; ++ default: ++ pipetype = "UNKNOWN"; ++ break; ++ } ++ ++ DWC_ERROR(" Endpoint type: %s\n", pipetype); ++ ++ switch (hc->speed) { ++ case DWC_OTG_EP_SPEED_HIGH: ++ speed = "HIGH"; ++ break; ++ case DWC_OTG_EP_SPEED_FULL: ++ speed = "FULL"; ++ break; ++ case DWC_OTG_EP_SPEED_LOW: ++ speed = "LOW"; ++ break; ++ default: ++ speed = "UNKNOWN"; ++ break; ++ }; ++ ++ DWC_ERROR(" Speed: %s\n", speed); ++ ++ DWC_ERROR(" Max packet size: %d\n", ++ dwc_otg_hcd_get_mps(&urb->pipe_info)); ++ DWC_ERROR(" Data buffer length: %d\n", urb->length); ++ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", ++ urb->buf, (void *)urb->dma); ++ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", ++ urb->setup_packet, (void *)urb->setup_dma); ++ DWC_ERROR(" Interval: %d\n", urb->interval); ++ ++ /* Core haltes the channel for Descriptor DMA mode */ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_AHB_ERR); ++ goto handle_ahberr_done; ++ } ++ ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO); ++ ++ /* ++ * Force a channel halt. Don't call halt_channel because that won't ++ * write to the HCCHARn register in DMA mode to force the halt. ++ */ ++ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR); ++handle_ahberr_done: ++ disable_hc_int(hc_regs, ahberr); ++ return 1; ++} ++ ++/** ++ * Handles a host channel transaction error interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Transaction Error--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ goto handle_xacterr_done; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ qtd->error_count++; ++ if (!hc->qh->ping_state) { ++ ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) { ++ hc->qh->ping_state = 1; ++ } ++ } ++ ++ /* ++ * Halt the channel so the transfer can be re-started from ++ * the appropriate point or the PING protocol will start. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ break; ++ case UE_INTERRUPT: ++ qtd->error_count++; ++ if (hc->do_split && hc->complete_split) { ++ qtd->complete_split = 0; ++ } ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ break; ++ } ++handle_xacterr_done: ++ disable_hc_int(hc_regs, xacterr); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel frame overrun interrupt. This handler may be called ++ * in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Frame Overrun--\n", hc->hc_num); ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ break; ++ case UE_INTERRUPT: ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN); ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_FRAME_OVERRUN); ++ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ break; ++ } ++ ++ disable_hc_int(hc_regs, frmovrun); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel data toggle error interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Data Toggle Error on %s transfer--\n", ++ hc->hc_num, (hc->ep_is_in ? "IN" : "OUT")); ++ ++ /* Data toggles on split transactions cause the hc to halt. ++ * restart transfer */ ++ if(hc->qh->do_split) ++ { ++ qtd->error_count++; ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ } else if (hc->ep_is_in) { ++ /* An unmasked data toggle error on a non-split DMA transaction is ++ * for the sole purpose of resetting error counts. Disable other ++ * interrupts unmasked for the same reason. ++ */ ++ if(hcd->core_if->dma_enable) { ++ disable_hc_int(hc_regs, ack); ++ disable_hc_int(hc_regs, nak); ++ } ++ qtd->error_count = 0; ++ } ++ ++ disable_hc_int(hc_regs, datatglerr); ++ ++ return 1; ++} ++ ++#ifdef DEBUG ++/** ++ * This function is for debug only. It checks that a valid halt status is set ++ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is ++ * taken and a warning is issued. ++ * @return 1 if halt status is ok, 0 otherwise. ++ */ ++static inline int halt_status_ok(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hcsplt_data_t hcsplt; ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { ++ /* ++ * This code is here only as a check. This condition should ++ * never happen. Ignore the halt if it does occur. ++ */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ DWC_WARN ++ ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, " ++ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " ++ "hcint 0x%08x, hcintmsk 0x%08x, " ++ "hcsplt 0x%08x, qtd->complete_split %d\n", __func__, ++ hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32, ++ hcintmsk.d32, hcsplt.d32, qtd->complete_split); ++ ++ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", ++ __func__, hc->hc_num); ++ DWC_WARN("\n"); ++ clear_hc_int(hc_regs, chhltd); ++ return 0; ++ } ++ ++ /* ++ * This code is here only as a check. hcchar.chdis should ++ * never be set when the halt interrupt occurs. Halt the ++ * channel again if it does occur. ++ */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: hcchar.chdis set unexpectedly, " ++ "hcchar 0x%08x, trying to halt again\n", ++ __func__, hcchar.d32); ++ clear_hc_int(hc_regs, chhltd); ++ hc->halt_pending = 0; ++ halt_channel(hcd, hc, qtd, hc->halt_status); ++ return 0; ++ } ++ ++ return 1; ++} ++#endif ++ ++/** ++ * Handles a host Channel Halted interrupt in DMA mode. This handler ++ * determines the reason the channel halted and proceeds accordingly. ++ */ ++static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ int out_nak_enh = 0; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ /* For core with OUT NAK enhancement, the flow for high- ++ * speed CONTROL/BULK OUT is handled a little differently. ++ */ ++ if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) { ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in && ++ (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK)) { ++ out_nak_enh = 1; ++ } ++ } ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || ++ (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR ++ && !hcd->core_if->dma_desc_enable)) { ++ /* ++ * Just release the channel. A dequeue can happen on a ++ * transfer timeout. In the case of an AHB Error, the channel ++ * was forced to halt because there's no way to gracefully ++ * recover. ++ */ ++ if (hcd->core_if->dma_desc_enable) ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ hc->halt_status); ++ else ++ release_channel(hcd, hc, qtd, hc->halt_status); ++ return; ++ } ++ ++ /* Read the HCINTn register to determine the cause for the halt. */ ++ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); ++ ++ if (hcint.b.xfercomp) { ++ /** @todo This is here because of a possible hardware bug. Spec ++ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT ++ * interrupt w/ACK bit set should occur, but I only see the ++ * XFERCOMP bit, even with it masked out. This is a workaround ++ * for that behavior. Should fix this when hardware is fixed. ++ */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { ++ handle_hc_ack_intr(hcd, hc, hc_regs, qtd); ++ } ++ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) { ++ if (out_nak_enh) { ++ if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) { ++ DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n"); ++ qtd->error_count = 0; ++ } else { ++ DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n"); ++ } ++ } ++ ++ /* ++ * Must handle xacterr before nak or ack. Could get a xacterr ++ * at the same time as either of these on a BULK/CONTROL OUT ++ * that started with a PING. The xacterr takes precedence. ++ */ ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) { ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.bblerr) { ++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.frmovrun) { ++ handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.datatglerr) { ++ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd); ++ } else if (!out_nak_enh) { ++ if (hcint.b.nyet) { ++ /* ++ * Must handle nyet before nak or ack. Could get a nyet at the ++ * same time as either of those on a BULK/CONTROL OUT that ++ * started with a PING. The nyet takes precedence. ++ */ ++ handle_hc_nyet_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.nak && !hcintmsk.b.nak) { ++ /* ++ * If nak is not masked, it's because a non-split IN transfer ++ * is in an error state. In that case, the nak is handled by ++ * the nak interrupt handler, not here. Handle nak here for ++ * BULK/CONTROL OUT transfers, which halt on a NAK to allow ++ * rewinding the buffer pointer. ++ */ ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ack && !hcintmsk.b.ack) { ++ /* ++ * If ack is not masked, it's because a non-split IN transfer ++ * is in an error state. In that case, the ack is handled by ++ * the ack interrupt handler, not here. Handle ack here for ++ * split transfers. Start splits halt on ACK. ++ */ ++ handle_hc_ack_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * A periodic transfer halted with no other channel ++ * interrupts set. Assume it was halted by the core ++ * because it could not be completed in its scheduled ++ * (micro)frame. ++ */ ++#ifdef DEBUG ++ DWC_PRINTF ++ ("%s: Halt channel %d (assume incomplete periodic transfer)\n", ++ __func__, hc->hc_num); ++#endif ++ halt_channel(hcd, hc, qtd, ++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE); ++ } else { ++ DWC_ERROR ++ ("%s: Channel %d, DMA Mode -- ChHltd set, but reason " ++ "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n", ++ __func__, hc->hc_num, hcint.d32, ++ DWC_READ_REG32(&hcd-> ++ core_if->core_global_regs-> ++ gintsts)); ++ /* Failthrough: use 3-strikes rule */ ++ qtd->error_count++; ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ } ++ ++ } ++ } else { ++ DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n", ++ hcint.d32); ++ /* Failthrough: use 3-strikes rule */ ++ qtd->error_count++; ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ } ++} ++ ++/** ++ * Handles a host channel Channel Halted interrupt. ++ * ++ * In slave mode, this handler is called only when the driver specifically ++ * requests a halt. This occurs during handling other host channel interrupts ++ * (e.g. nak, xacterr, stall, nyet, etc.). ++ * ++ * In DMA mode, this is the interrupt that occurs when the core has finished ++ * processing a transfer on a channel. Other host channel interrupts (except ++ * ahberr) are disabled in DMA mode. ++ */ ++static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Channel Halted--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_enable) { ++ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd); ++ } else { ++#ifdef DEBUG ++ if (!halt_status_ok(hcd, hc, hc_regs, qtd)) { ++ return 1; ++ } ++#endif ++ release_channel(hcd, hc, qtd, hc->halt_status); ++ } ++ ++ return 1; ++} ++ ++ ++/** ++ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on ++ * FIQ transfer completion ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * 1. Un-mangle the status as recorded in each iso_frame_desc status ++ * 2. Copy it from the dwc_otg_urb into the real URB ++ */ ++void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) ++{ ++ struct dwc_otg_hcd_urb *dwc_urb = qtd->urb; ++ int nr_frames = dwc_urb->packet_count; ++ int i; ++ hcint_data_t frame_hcint; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame_hcint.d32 = dwc_urb->iso_descs[i].status; ++ if (frame_hcint.b.xfercomp) { ++ dwc_urb->iso_descs[i].status = 0; ++ dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length; ++ } else if (frame_hcint.b.frmovrun) { ++ if (qh->ep_is_in) ++ dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES; ++ else ++ dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else if (frame_hcint.b.xacterr) { ++ dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else if (frame_hcint.b.bblerr) { ++ dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else { ++ /* Something went wrong */ ++ dwc_urb->iso_descs[i].status = -1; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ dwc_urb->error_count++; ++ } ++ } ++ //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n", ++ // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count); ++ hcd->fops->complete(hcd, dwc_urb->priv, dwc_urb, 0); ++ release_channel(hcd, qh->channel, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++} ++ ++/** ++ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state. ++ * Returns total length of data or -1 if the buffers were not used. ++ * ++ */ ++int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) ++{ ++ dwc_hc_t *hc = qh->channel; ++ struct fiq_dma_blob *blob = hcd->fiq_dmab; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ uint8_t *ptr = NULL; ++ int index = 0, len = 0; ++ int i = 0; ++ if (hc->ep_is_in) { ++ /* Copy data out of the DMA bounce buffers to the URB's buffer. ++ * The align_buf is ignored as this is ignored on FSM enqueue. */ ++ ptr = qtd->urb->buf; ++ if (qh->ep_type == UE_ISOCHRONOUS) { ++ /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */ ++ index = qtd->isoc_frame_index; ++ ptr += qtd->urb->iso_descs[index].offset; ++ } else { ++ /* Need to increment by actual_length for interrupt IN */ ++ ptr += qtd->urb->actual_length; ++ } ++ ++ for (i = 0; i < st->dma_info.index; i++) { ++ len += st->dma_info.slot_len[i]; ++ dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]); ++ ptr += st->dma_info.slot_len[i]; ++ } ++ return len; ++ } else { ++ /* OUT endpoints - nothing to do. */ ++ return -1; ++ } ++ ++} ++/** ++ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt ++ * from a channel handled in the FIQ ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * If a host channel interrupt was received by the IRQ and this was a channel ++ * used by the FIQ, the execution flow for transfer completion is substantially ++ * different from the normal (messy) path. This function and its friends handles ++ * channel cleanup and transaction completion from a FIQ transaction. ++ */ ++void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) ++{ ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ dwc_hc_t *hc = hcd->hc_ptr_array[num]; ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); ++ dwc_otg_qh_t *qh = hc->qh; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num]; ++ hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy; ++ int hostchannels = 0; ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm); ++ ++ hostchannels = hcd->available_host_channels; ++ switch (st->fsm) { ++ case FIQ_TEST: ++ break; ++ ++ case FIQ_DEQUEUE_ISSUED: ++ /* hc_halt was called. QTD no longer exists. */ ++ /* TODO: for a nonperiodic split transaction, need to issue a ++ * CLEAR_TT_BUFFER hub command if we were in the start-split phase. ++ */ ++ release_channel(hcd, hc, NULL, hc->halt_status); ++ break; ++ ++ case FIQ_NP_SPLIT_DONE: ++ /* Nonperiodic transaction complete. */ ++ if (!hc->ep_is_in) { ++ qtd->ssplit_out_xfer_count = hc->xfer_len; ++ } ++ if (hcint.b.xfercomp) { ++ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.nak) { ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } ++ break; ++ ++ case FIQ_NP_SPLIT_HS_ABORTED: ++ /* A HS abort is a 3-strikes on the HS bus at any point in the transaction. ++ * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that ++ * because there's no guarantee which order a non-periodic split happened in. ++ * We could end up clearing a perfectly good transaction out of the buffer. ++ */ ++ if (hcint.b.xacterr) { ++ qtd->error_count += st->nr_errors; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ local_fiq_disable(); ++ BUG(); ++ } ++ break; ++ ++ case FIQ_NP_SPLIT_LS_ABORTED: ++ /* A few cases can cause this - either an unknown state on a SSPLIT or ++ * STALL/data toggle error response on a CSPLIT */ ++ if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.datatglerr) { ++ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.bblerr) { ++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ local_fiq_disable(); ++ BUG(); ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_DONE: ++ /* Isoc IN or Interrupt IN/OUT */ ++ ++ /* Flow control here is different from the normal execution by the driver. ++ * We need to completely ignore most of the driver's method of handling ++ * split transactions and do it ourselves. ++ */ ++ if (hc->ep_type == UE_INTERRUPT) { ++ if (hcint.b.nak) { ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } else if (hc->ep_is_in) { ++ int len; ++ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num); ++ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length); ++ qtd->urb->actual_length += len; ++ if (qtd->urb->actual_length >= qtd->urb->length) { ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ /* Interrupt transfer not complete yet - is it a short read? */ ++ if (len < hc->max_packet) { ++ /* Interrupt transaction complete */ ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ /* Further transactions required */ ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ } else { ++ /* Interrupt OUT complete. */ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ qtd->urb->actual_length += hc->xfer_len; ++ if (qtd->urb->actual_length >= qtd->urb->length) { ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ } else { ++ /* ISOC IN complete. */ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ int len = 0; ++ /* Record errors, update qtd. */ ++ if (st->nr_errors) { ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } else { ++ frame_desc->status = 0; ++ /* Unswizzle dma */ ++ len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num); ++ frame_desc->actual_length = len; ++ } ++ qtd->isoc_frame_index++; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_DONE: { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ if (st->nr_errors) { ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } else { ++ frame_desc->status = 0; ++ frame_desc->actual_length = frame_desc->length; ++ } ++ qtd->isoc_frame_index++; ++ qtd->isoc_split_offset = 0; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_NYET_ABORTED: ++ /* Doh. lost the data. */ ++ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " ++ "- FIQ reported NYET. Data may have been lost.\n", ++ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); ++ if (hc->ep_type == UE_ISOCHRONOUS) { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ qtd->isoc_frame_index++; ++ qtd->isoc_split_offset = 0; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ case FIQ_HS_ISOC_DONE: ++ /* The FIQ has performed a whole pile of isochronous transactions. ++ * The status is recorded as the interrupt state should the transaction ++ * fail. ++ */ ++ dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num); ++ break; ++ ++ case FIQ_PER_SPLIT_LS_ABORTED: ++ if (hcint.b.xacterr) { ++ /* Hub has responded with an ERR packet. Device ++ * has been unplugged or the port has been disabled. ++ * TODO: need to issue a reset to the hub port. */ ++ qtd->error_count += 3; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.bblerr) { ++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " ++ "- FIQ reported FSM=%d. Data may have been lost.\n", ++ st->fsm, hc->dev_addr, hc->ep_num); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_HS_ABORTED: ++ /* Either the SSPLIT phase suffered transaction errors or something ++ * unexpected happened. ++ */ ++ qtd->error_count += 3; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ /* Couldn't complete in the nominated frame */ ++ printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " ++ "- FIQ timed out. Data may have been lost.\n", ++ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); ++ if (hc->ep_type == UE_ISOCHRONOUS) { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ frame_desc->actual_length = 0; ++ if (hc->ep_is_in) { ++ frame_desc->status = -DWC_E_NO_STREAM_RES; ++ } else { ++ frame_desc->status = -DWC_E_COMMUNICATION; ++ } ++ qtd->isoc_frame_index++; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ default: ++ DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x", ++ hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num); ++ qtd->error_count++; ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ return; ++} ++ ++/** Handles interrupt for a specific Host Channel */ ++int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) ++{ ++ int retval = 0; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ dwc_hc_t *hc; ++ dwc_otg_hc_regs_t *hc_regs; ++ dwc_otg_qtd_t *qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num); ++ ++ hc = dwc_otg_hcd->hc_ptr_array[num]; ++ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num]; ++ if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ /* We are responding to a channel disable. Driver ++ * state is cleared - our qtd has gone away. ++ */ ++ release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status); ++ return 1; ++ } ++ qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); ++ ++ /* ++ * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ. ++ * Execution path is fundamentally different for the channels after a FIQ has completed ++ * a split transaction. ++ */ ++ if (fiq_fsm_enable) { ++ switch (dwc_otg_hcd->fiq_state->channel[num].fsm) { ++ case FIQ_PASSTHROUGH: ++ break; ++ case FIQ_PASSTHROUGH_ERRORSTATE: ++ /* Hook into the error count */ ++ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num); ++ if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) { ++ qtd->error_count = 0; ++ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET "); ++ } ++ break; ++ default: ++ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num); ++ return 1; ++ } ++ } ++ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); ++ hcint.d32 = hcint.d32 & hcintmsk.d32; ++ if (!dwc_otg_hcd->core_if->dma_enable) { ++ if (hcint.b.chhltd && hcint.d32 != 0x2) { ++ hcint.b.chhltd = 0; ++ } ++ } ++ ++ if (hcint.b.xfercomp) { ++ retval |= ++ handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ /* ++ * If NYET occurred at same time as Xfer Complete, the NYET is ++ * handled by the Xfer Complete interrupt handler. Don't want ++ * to call the NYET interrupt handler in this case. ++ */ ++ hcint.b.nyet = 0; ++ } ++ if (hcint.b.chhltd) { ++ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.ahberr) { ++ retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.stall) { ++ retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.nak) { ++ retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.ack) { ++ if(!hcint.b.chhltd) ++ retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.nyet) { ++ retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.xacterr) { ++ retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.bblerr) { ++ retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.frmovrun) { ++ retval |= ++ handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.datatglerr) { ++ retval |= ++ handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ ++ return retval; ++} ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +@@ -0,0 +1,995 @@ ++ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $ ++ * $Revision: #20 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1872981 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** ++ * @file ++ * ++ * This file contains the implementation of the HCD. In Linux, the HCD ++ * implements the hc_driver API. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++#include <../drivers/usb/core/hcd.h> ++#else ++#include ++#endif ++#include ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++#define USB_URB_EP_LINKING 1 ++#else ++#define USB_URB_EP_LINKING 0 ++#endif ++ ++#include "dwc_otg_hcd_if.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_hcd.h" ++ ++extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end; ++ ++/** ++ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is ++ * qualified with its direction (possible 32 endpoints per device). ++ */ ++#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ ++ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) ++ ++static const char dwc_otg_hcd_name[] = "dwc_otg_hcd"; ++ ++extern bool fiq_enable; ++ ++/** @name Linux HC Driver API Functions */ ++/** @{ */ ++/* manage i/o requests, device state */ ++static int dwc_otg_urb_enqueue(struct usb_hcd *hcd, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ struct usb_host_endpoint *ep, ++#endif ++ struct urb *urb, gfp_t mem_flags); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb); ++#endif ++#else /* kernels at or post 2.6.30 */ ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, ++ struct urb *urb, int status); ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */ ++ ++static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); ++#endif ++static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd); ++extern int hcd_start(struct usb_hcd *hcd); ++extern void hcd_stop(struct usb_hcd *hcd); ++static int get_frame_number(struct usb_hcd *hcd); ++extern int hub_status_data(struct usb_hcd *hcd, char *buf); ++extern int hub_control(struct usb_hcd *hcd, ++ u16 typeReq, ++ u16 wValue, u16 wIndex, char *buf, u16 wLength); ++ ++struct wrapper_priv_data { ++ dwc_otg_hcd_t *dwc_otg_hcd; ++}; ++ ++/** @} */ ++ ++static struct hc_driver dwc_otg_hc_driver = { ++ ++ .description = dwc_otg_hcd_name, ++ .product_desc = "DWC OTG Controller", ++ .hcd_priv_size = sizeof(struct wrapper_priv_data), ++ ++ .irq = dwc_otg_hcd_irq, ++ ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ //.reset = ++ .start = hcd_start, ++ //.suspend = ++ //.resume = ++ .stop = hcd_stop, ++ ++ .urb_enqueue = dwc_otg_urb_enqueue, ++ .urb_dequeue = dwc_otg_urb_dequeue, ++ .endpoint_disable = endpoint_disable, ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++ .endpoint_reset = endpoint_reset, ++#endif ++ .get_frame_number = get_frame_number, ++ ++ .hub_status_data = hub_status_data, ++ .hub_control = hub_control, ++ //.bus_suspend = ++ //.bus_resume = ++}; ++ ++/** Gets the dwc_otg_hcd from a struct usb_hcd */ ++static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) ++{ ++ struct wrapper_priv_data *p; ++ p = (struct wrapper_priv_data *)(hcd->hcd_priv); ++ return p->dwc_otg_hcd; ++} ++ ++/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ ++static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ return dwc_otg_hcd_get_priv_data(dwc_otg_hcd); ++} ++ ++/** Gets the usb_host_endpoint associated with an URB. */ ++inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb) ++{ ++ struct usb_device *dev = urb->dev; ++ int ep_num = usb_pipeendpoint(urb->pipe); ++ ++ if (usb_pipein(urb->pipe)) ++ return dev->ep_in[ep_num]; ++ else ++ return dev->ep_out[ep_num]; ++} ++ ++static int _disconnect(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ ++ usb_hcd->self.is_b_host = 0; ++ return 0; ++} ++ ++static int _start(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ ++ usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd); ++ hcd_start(usb_hcd); ++ ++ return 0; ++} ++ ++static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr, ++ uint32_t * port_addr) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++ struct usb_bus *bus; ++#if 1 //GRAYG - temporary ++ if (NULL == urb_handle) ++ DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG ++ if (NULL == urb->dev) ++ DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG ++ if (NULL == port_addr) ++ DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG ++#endif ++ if (urb->dev->tt) { ++ if (NULL == urb->dev->tt->hub) { ++ DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n", ++ __func__); //GRAYG ++ //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG ++ *hub_addr = 0; //GRAYG ++ // we probably shouldn't have a transaction translator if ++ // there's no associated hub? ++ } else { ++ bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd)); ++ if (urb->dev->tt->hub == bus->root_hub) ++ *hub_addr = 0; ++ else ++ *hub_addr = urb->dev->tt->hub->devnum; ++ } ++ *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1; ++ } else { ++ *hub_addr = 0; ++ *port_addr = urb->dev->ttport; ++ } ++ return 0; ++} ++ ++static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++ return urb->dev->speed; ++} ++ ++static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ return usb_hcd->self.b_hnp_enable; ++} ++ ++static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw, ++ struct urb *urb) ++{ ++ hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval; ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ hcd_to_bus(hcd)->bandwidth_isoc_reqs++; ++ } else { ++ hcd_to_bus(hcd)->bandwidth_int_reqs++; ++ } ++} ++ ++static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw, ++ struct urb *urb) ++{ ++ hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval; ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ hcd_to_bus(hcd)->bandwidth_isoc_reqs--; ++ } else { ++ hcd_to_bus(hcd)->bandwidth_int_reqs--; ++ } ++} ++ ++/** ++ * Sets the final status of an URB and returns it to the device driver. Any ++ * required cleanup of the URB is performed. The HCD lock should be held on ++ * entry. ++ */ ++static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++ urb_tq_entry_t *new_entry; ++ int rc = 0; ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n", ++ __func__, urb, usb_pipedevice(urb->pipe), ++ usb_pipeendpoint(urb->pipe), ++ usb_pipein(urb->pipe) ? "IN" : "OUT", status); ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ for (i = 0; i < urb->number_of_packets; i++) { ++ DWC_PRINTF(" ISO Desc %d status: %d\n", ++ i, urb->iso_frame_desc[i].status); ++ } ++ } ++ } ++ new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t)); ++ urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb); ++ /* Convert status value. */ ++ switch (status) { ++ case -DWC_E_PROTOCOL: ++ status = -EPROTO; ++ break; ++ case -DWC_E_IN_PROGRESS: ++ status = -EINPROGRESS; ++ break; ++ case -DWC_E_PIPE: ++ status = -EPIPE; ++ break; ++ case -DWC_E_IO: ++ status = -EIO; ++ break; ++ case -DWC_E_TIMEOUT: ++ status = -ETIMEDOUT; ++ break; ++ case -DWC_E_OVERFLOW: ++ status = -EOVERFLOW; ++ break; ++ case -DWC_E_SHUTDOWN: ++ status = -ESHUTDOWN; ++ break; ++ default: ++ if (status) { ++ DWC_PRINTF("Uknown urb status %d\n", status); ++ ++ } ++ } ++ ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ ++ urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb); ++ for (i = 0; i < urb->number_of_packets; ++i) { ++ urb->iso_frame_desc[i].actual_length = ++ dwc_otg_hcd_urb_get_iso_desc_actual_length ++ (dwc_otg_urb, i); ++ urb->iso_frame_desc[i].status = ++ dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i); ++ } ++ } ++ ++ urb->status = status; ++ urb->hcpriv = NULL; ++ if (!status) { ++ if ((urb->transfer_flags & URB_SHORT_NOT_OK) && ++ (urb->actual_length < urb->transfer_buffer_length)) { ++ urb->status = -EREMOTEIO; ++ } ++ } ++ ++ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) || ++ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { ++ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); ++ if (ep) { ++ free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd), ++ dwc_otg_hcd_get_ep_bandwidth(hcd, ++ ep->hcpriv), ++ urb); ++ } ++ } ++ DWC_FREE(dwc_otg_urb); ++ if (!new_entry) { ++ DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n"); ++ urb->status = -EPROTO; ++ /* don't schedule the tasklet - ++ * directly return the packet here with error. */ ++#if USB_URB_EP_LINKING ++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); ++#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb); ++#else ++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status); ++#endif ++ } else { ++ new_entry->urb = urb; ++#if USB_URB_EP_LINKING ++ rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status); ++ if(0 == rc) { ++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); ++ } ++#endif ++ if(0 == rc) { ++ DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry, ++ urb_tq_entries); ++ DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet); ++ } ++ } ++ return 0; ++} ++ ++static struct dwc_otg_hcd_function_ops hcd_fops = { ++ .start = _start, ++ .disconnect = _disconnect, ++ .hub_info = _hub_info, ++ .speed = _speed, ++ .complete = _complete, ++ .get_b_hnp_enable = _get_b_hnp_enable, ++}; ++ ++static struct fiq_handler fh = { ++ .name = "usb_fiq", ++}; ++ ++static void hcd_init_fiq(void *cookie) ++{ ++ dwc_otg_device_t *otg_dev = cookie; ++ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd; ++ struct pt_regs regs; ++ ++ if (claim_fiq(&fh)) { ++ DWC_ERROR("Can't claim FIQ"); ++ BUG(); ++ } ++ DWC_WARN("FIQ on core %d at 0x%08x", ++ smp_processor_id(), ++ (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop)); ++ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub)); ++ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub); ++ memset(®s,0,sizeof(regs)); ++ ++ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state; ++ if (fiq_fsm_enable) { ++ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels; ++ //regs.ARM_r10 = dwc_otg_hcd->dma; ++ regs.ARM_fp = (long) dwc_otg_fiq_fsm; ++ } else { ++ regs.ARM_fp = (long) dwc_otg_fiq_nop; ++ } ++ ++ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4); ++ ++// __show_regs(®s); ++ set_fiq_regs(®s); ++ ++ //Set the mphi periph to the required registers ++ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base; ++ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c; ++ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28; ++ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c; ++ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50; ++ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base; ++ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base); ++ //Enable mphi peripheral ++ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl); ++#ifdef DEBUG ++ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000) ++ DWC_WARN("MPHI periph has been enabled"); ++ else ++ DWC_WARN("MPHI periph has NOT been enabled"); ++#endif ++ // Enable FIQ interrupt from USB peripheral ++ enable_fiq(INTERRUPT_VC_USB); ++ local_fiq_enable(); ++} ++ ++/** ++ * Initializes the HCD. This function allocates memory for and initializes the ++ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the ++ * USB bus with the core and calls the hc_driver->start() function. It returns ++ * a negative error on failure. ++ */ ++int hcd_init(dwc_bus_dev_t *_dev) ++{ ++ struct usb_hcd *hcd = NULL; ++ dwc_otg_hcd_t *dwc_otg_hcd = NULL; ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ int retval = 0; ++ u64 dmamask; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev); ++ ++ /* Set device flags indicating whether the HCD supports DMA. */ ++ if (dwc_otg_is_dma_enable(otg_dev->core_if)) ++ dmamask = DMA_BIT_MASK(32); ++ else ++ dmamask = 0; ++ ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ dma_set_mask(&_dev->dev, dmamask); ++ dma_set_coherent_mask(&_dev->dev, dmamask); ++#elif defined(PCI_INTERFACE) ++ pci_set_dma_mask(_dev, dmamask); ++ pci_set_consistent_dma_mask(_dev, dmamask); ++#endif ++ ++ /* ++ * Allocate memory for the base HCD plus the DWC OTG HCD. ++ * Initialize the base HCD. ++ */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id); ++#else ++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev)); ++ hcd->has_tt = 1; ++// hcd->uses_new_polling = 1; ++// hcd->poll_rh = 0; ++#endif ++ if (!hcd) { ++ retval = -ENOMEM; ++ goto error1; ++ } ++ ++ hcd->regs = otg_dev->os_dep.base; ++ ++ ++ /* Initialize the DWC OTG HCD. */ ++ dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); ++ if (!dwc_otg_hcd) { ++ goto error2; ++ } ++ ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd = ++ dwc_otg_hcd; ++ otg_dev->hcd = dwc_otg_hcd; ++ ++ if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) { ++ goto error2; ++ } ++ ++ if (fiq_enable) { ++ if (num_online_cpus() > 1) { ++ /* bcm2709: can run the FIQ on a separate core to IRQs */ ++ smp_call_function_single(1, hcd_init_fiq, otg_dev, 1); ++ } else { ++ smp_call_function_single(0, hcd_init_fiq, otg_dev, 1); ++ } ++ } ++ ++ otg_dev->hcd->otg_dev = otg_dev; ++ hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later ++ hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if); ++#endif ++ /* Don't support SG list at this point */ ++ hcd->self.sg_tablesize = 0; ++#endif ++ /* ++ * Finish generic HCD initialization and start the HCD. This function ++ * allocates the DMA buffer pool, registers the USB bus, requests the ++ * IRQ line, and calls hcd_start method. ++ */ ++#ifdef PLATFORM_INTERFACE ++ retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED); ++#else ++ retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED); ++#endif ++ if (retval < 0) { ++ goto error2; ++ } ++ ++ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd); ++ return 0; ++ ++error2: ++ usb_put_hcd(hcd); ++error1: ++ return retval; ++} ++ ++/** ++ * Removes the HCD. ++ * Frees memory and resources associated with the HCD and deregisters the bus. ++ */ ++void hcd_remove(dwc_bus_dev_t *_dev) ++{ ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ struct usb_hcd *hcd; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev); ++ ++ if (!otg_dev) { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); ++ return; ++ } ++ ++ dwc_otg_hcd = otg_dev->hcd; ++ ++ if (!dwc_otg_hcd) { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); ++ return; ++ } ++ ++ hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); ++ ++ if (!hcd) { ++ DWC_DEBUGPL(DBG_ANY, ++ "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", ++ __func__); ++ return; ++ } ++ usb_remove_hcd(hcd); ++ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL); ++ dwc_otg_hcd_remove(dwc_otg_hcd); ++ usb_put_hcd(hcd); ++} ++ ++/* ========================================================================= ++ * Linux HC Driver Functions ++ * ========================================================================= */ ++ ++/** Initializes the DWC_otg controller and its root hub and prepares it for host ++ * mode operation. Activates the root port. Returns 0 on success and a negative ++ * error code on failure. */ ++int hcd_start(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ struct usb_bus *bus; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); ++ bus = hcd_to_bus(hcd); ++ ++ hcd->state = HC_STATE_RUNNING; ++ if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) { ++ return 0; ++ } ++ ++ /* Initialize and connect root hub if one is not already attached */ ++ if (bus->root_hub) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); ++ /* Inform the HUB driver to resume. */ ++ usb_hcd_resume_root_hub(hcd); ++ } ++ ++ return 0; ++} ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ */ ++void hcd_stop(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ dwc_otg_hcd_stop(dwc_otg_hcd); ++} ++ ++/** Returns the current frame number. */ ++static int get_frame_number(struct usb_hcd *hcd) ++{ ++ hprt0_data_t hprt0; ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) ++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3; ++ else ++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd); ++} ++ ++#ifdef DEBUG ++static void dump_urb_info(struct urb *urb, char *fn_name) ++{ ++ DWC_PRINTF("%s, urb %p\n", fn_name, urb); ++ DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe)); ++ DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), ++ (usb_pipein(urb->pipe) ? "IN" : "OUT")); ++ DWC_PRINTF(" Endpoint type: %s\n", ( { ++ char *pipetype; ++ switch (usb_pipetype(urb->pipe)) { ++case PIPE_CONTROL: ++pipetype = "CONTROL"; break; case PIPE_BULK: ++pipetype = "BULK"; break; case PIPE_INTERRUPT: ++pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS: ++pipetype = "ISOCHRONOUS"; break; default: ++ pipetype = "UNKNOWN"; break;}; ++ pipetype;} ++ )) ; ++ DWC_PRINTF(" Speed: %s\n", ( { ++ char *speed; switch (urb->dev->speed) { ++case USB_SPEED_HIGH: ++speed = "HIGH"; break; case USB_SPEED_FULL: ++speed = "FULL"; break; case USB_SPEED_LOW: ++speed = "LOW"; break; default: ++ speed = "UNKNOWN"; break;}; ++ speed;} ++ )) ; ++ DWC_PRINTF(" Max packet size: %d\n", ++ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); ++ DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length); ++ DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n", ++ urb->transfer_buffer, (void *)urb->transfer_dma); ++ DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n", ++ urb->setup_packet, (void *)urb->setup_dma); ++ DWC_PRINTF(" Interval: %d\n", urb->interval); ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ for (i = 0; i < urb->number_of_packets; i++) { ++ DWC_PRINTF(" ISO Desc %d:\n", i); ++ DWC_PRINTF(" offset: %d, length %d\n", ++ urb->iso_frame_desc[i].offset, ++ urb->iso_frame_desc[i].length); ++ } ++ } ++} ++#endif ++ ++/** Starts processing a USB transfer request specified by a USB Request Block ++ * (URB). mem_flags indicates the type of memory allocation to use while ++ * processing this URB. */ ++static int dwc_otg_urb_enqueue(struct usb_hcd *hcd, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ struct usb_host_endpoint *ep, ++#endif ++ struct urb *urb, gfp_t mem_flags) ++{ ++ int retval = 0; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28) ++ struct usb_host_endpoint *ep = urb->ep; ++#endif ++ dwc_irqflags_t irqflags; ++ void **ref_ep_hcpriv = &ep->hcpriv; ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ dwc_otg_hcd_urb_t *dwc_otg_urb; ++ int i; ++ int alloc_bandwidth = 0; ++ uint8_t ep_type = 0; ++ uint32_t flags = 0; ++ void *buf; ++ ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ dump_urb_info(urb, "dwc_otg_urb_enqueue"); ++ } ++#endif ++ ++ if (!urb->transfer_buffer && urb->transfer_buffer_length) ++ return -EINVAL; ++ ++ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ++ || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { ++ if (!dwc_otg_hcd_is_bandwidth_allocated ++ (dwc_otg_hcd, ref_ep_hcpriv)) { ++ alloc_bandwidth = 1; ++ } ++ } ++ ++ switch (usb_pipetype(urb->pipe)) { ++ case PIPE_CONTROL: ++ ep_type = USB_ENDPOINT_XFER_CONTROL; ++ break; ++ case PIPE_ISOCHRONOUS: ++ ep_type = USB_ENDPOINT_XFER_ISOC; ++ break; ++ case PIPE_BULK: ++ ep_type = USB_ENDPOINT_XFER_BULK; ++ break; ++ case PIPE_INTERRUPT: ++ ep_type = USB_ENDPOINT_XFER_INT; ++ break; ++ default: ++ DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe)); ++ } ++ ++ /* # of packets is often 0 - do we really need to call this then? */ ++ dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd, ++ urb->number_of_packets, ++ mem_flags == GFP_ATOMIC ? 1 : 0); ++ ++ if(dwc_otg_urb == NULL) ++ return -ENOMEM; ++ ++ if (!dwc_otg_urb && urb->number_of_packets) ++ return -ENOMEM; ++ ++ dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe), ++ usb_pipeendpoint(urb->pipe), ep_type, ++ usb_pipein(urb->pipe), ++ usb_maxpacket(urb->dev, urb->pipe, ++ !(usb_pipein(urb->pipe)))); ++ ++ buf = urb->transfer_buffer; ++ if (hcd->self.uses_dma && !buf && urb->transfer_buffer_length) { ++ /* ++ * Calculate virtual address from physical address, ++ * because some class driver may not fill transfer_buffer. ++ * In Buffer DMA mode virual address is used, ++ * when handling non DWORD aligned buffers. ++ */ ++ buf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma); ++ dev_warn_once(&urb->dev->dev, ++ "USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\n", ++ &urb->transfer_dma, buf); ++ } ++ ++ if (!(urb->transfer_flags & URB_NO_INTERRUPT)) ++ flags |= URB_GIVEBACK_ASAP; ++ if (urb->transfer_flags & URB_ZERO_PACKET) ++ flags |= URB_SEND_ZERO_PACKET; ++ ++ dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf, ++ urb->transfer_dma, ++ urb->transfer_buffer_length, ++ urb->setup_packet, ++ urb->setup_dma, flags, urb->interval); ++ ++ for (i = 0; i < urb->number_of_packets; ++i) { ++ dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i, ++ urb-> ++ iso_frame_desc[i].offset, ++ urb-> ++ iso_frame_desc[i].length); ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags); ++ urb->hcpriv = dwc_otg_urb; ++#if USB_URB_EP_LINKING ++ retval = usb_hcd_link_urb_to_ep(hcd, urb); ++ if (0 == retval) ++#endif ++ { ++ retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, ++ /*(dwc_otg_qh_t **)*/ ++ ref_ep_hcpriv, 1); ++ if (0 == retval) { ++ if (alloc_bandwidth) { ++ allocate_bus_bandwidth(hcd, ++ dwc_otg_hcd_get_ep_bandwidth( ++ dwc_otg_hcd, *ref_ep_hcpriv), ++ urb); ++ } ++ } else { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval); ++#if USB_URB_EP_LINKING ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++#endif ++ DWC_FREE(dwc_otg_urb); ++ urb->hcpriv = NULL; ++ if (retval == -DWC_E_NO_DEVICE) ++ retval = -ENODEV; ++ } ++ } ++#if USB_URB_EP_LINKING ++ else ++ { ++ DWC_FREE(dwc_otg_urb); ++ urb->hcpriv = NULL; ++ } ++#endif ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags); ++ return retval; ++} ++ ++/** Aborts/cancels a USB transfer request. Always returns 0 to indicate ++ * success. */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) ++#else ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) ++#endif ++{ ++ dwc_irqflags_t flags; ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ int rc; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); ++ ++ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ dump_urb_info(urb, "dwc_otg_urb_dequeue"); ++ } ++#endif ++ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ rc = usb_hcd_check_unlink_urb(hcd, urb, status); ++ if (0 == rc) { ++ if(urb->hcpriv != NULL) { ++ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, ++ (dwc_otg_hcd_urb_t *)urb->hcpriv); ++ ++ DWC_FREE(urb->hcpriv); ++ urb->hcpriv = NULL; ++ } ++ } ++ ++ if (0 == rc) { ++ /* Higher layer software sets URB status. */ ++#if USB_URB_EP_LINKING ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++#endif ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ usb_hcd_giveback_urb(hcd, urb); ++#else ++ usb_hcd_giveback_urb(hcd, urb, status); ++#endif ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINTF("Called usb_hcd_giveback_urb() \n"); ++ DWC_PRINTF(" 1urb->status = %d\n", urb->status); ++ } ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n"); ++ } else { ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n", ++ rc); ++ } ++ ++ return rc; ++} ++ ++/* Frees resources in the DWC_otg controller related to a given endpoint. Also ++ * clears state in the HCD related to the endpoint. Any URBs for the endpoint ++ * must already be dequeued. */ ++static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " ++ "endpoint=%d\n", ep->desc.bEndpointAddress, ++ dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress)); ++ dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250); ++ ep->hcpriv = NULL; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++/* Resets endpoint specific parameter values, in current version used to reset ++ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */ ++static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++{ ++ dwc_irqflags_t flags; ++ struct usb_device *udev = NULL; ++ int epnum = usb_endpoint_num(&ep->desc); ++ int is_out = usb_endpoint_dir_out(&ep->desc); ++ int is_control = usb_endpoint_xfer_control(&ep->desc); ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep); ++ ++ if (dev) ++ udev = to_usb_device(dev); ++ else ++ return; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum); ++ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ usb_settoggle(udev, epnum, is_out, 0); ++ if (is_control) ++ usb_settoggle(udev, epnum, !is_out, 0); ++ ++ if (ep->hcpriv) { ++ dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv); ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++} ++#endif ++ ++/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if ++ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid ++ * interrupt. ++ * ++ * This function is called by the USB core when an interrupt occurs */ ++static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** Creates Status Change bitmap for the root hub and root port. The bitmap is ++ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 ++ * is the status change indicator for the single root port. Returns 1 if either ++ * change indicator is 1, otherwise returns 0. */ ++int hub_status_data(struct usb_hcd *hcd, char *buf) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ buf[0] = 0; ++ buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1; ++ ++ return (buf[0] != 0); ++} ++ ++/** Handles hub class-specific requests. */ ++int hub_control(struct usb_hcd *hcd, ++ u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength) ++{ ++ int retval; ++ ++ retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd), ++ typeReq, wValue, wIndex, buf, wLength); ++ ++ switch (retval) { ++ case -DWC_E_INVALID: ++ retval = -EINVAL; ++ break; ++ } ++ ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +@@ -0,0 +1,957 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $ ++ * $Revision: #44 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** ++ * @file ++ * ++ * This file contains the functions to manage Queue Heads and Queue ++ * Transfer Descriptors. ++ */ ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++extern bool microframe_schedule; ++ ++/** ++ * Free each QTD in the QH's QTD-list then free the QH. QH should already be ++ * removed from a list. QTD list should already be empty if called from URB ++ * Dequeue. ++ * ++ * @param hcd HCD instance. ++ * @param qh The QH to free. ++ */ ++void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_irqflags_t flags; ++ ++ /* Free each QTD in the QTD list */ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { ++ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); ++ dwc_otg_hcd_qtd_free(qtd); ++ } ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_qh_free_ddma(hcd, qh); ++ } else if (qh->dw_align_buf) { ++ uint32_t buf_size; ++ if (qh->ep_type == UE_ISOCHRONOUS) { ++ buf_size = 4096; ++ } else { ++ buf_size = hcd->core_if->core_params->max_transfer_size; ++ } ++ DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma); ++ } ++ ++ DWC_FREE(qh); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ return; ++} ++ ++#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6) ++#define HS_HOST_DELAY 5 /* nanoseconds */ ++#define FS_LS_HOST_DELAY 1000 /* nanoseconds */ ++#define HUB_LS_SETUP 333 /* nanoseconds */ ++#define NS_TO_US(ns) ((ns + 500) / 1000) ++ /* convert & round nanoseconds to microseconds */ ++ ++static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount) ++{ ++ unsigned long retval; ++ ++ switch (speed) { ++ case USB_SPEED_HIGH: ++ if (is_isoc) { ++ retval = ++ ((38 * 8 * 2083) + ++ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 + ++ HS_HOST_DELAY; ++ } else { ++ retval = ++ ((55 * 8 * 2083) + ++ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 + ++ HS_HOST_DELAY; ++ } ++ break; ++ case USB_SPEED_FULL: ++ if (is_isoc) { ++ retval = ++ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000; ++ if (is_in) { ++ retval = 7268 + FS_LS_HOST_DELAY + retval; ++ } else { ++ retval = 6265 + FS_LS_HOST_DELAY + retval; ++ } ++ } else { ++ retval = ++ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000; ++ retval = 9107 + FS_LS_HOST_DELAY + retval; ++ } ++ break; ++ case USB_SPEED_LOW: ++ if (is_in) { ++ retval = ++ (67667 * (31 + 10 * BitStuffTime(bytecount))) / ++ 1000; ++ retval = ++ 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + ++ retval; ++ } else { ++ retval = ++ (66700 * (31 + 10 * BitStuffTime(bytecount))) / ++ 1000; ++ retval = ++ 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + ++ retval; ++ } ++ break; ++ default: ++ DWC_WARN("Unknown device speed\n"); ++ retval = -1; ++ } ++ ++ return NS_TO_US(retval); ++} ++ ++/** ++ * Initializes a QH structure. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * @param urb Holds the information about the device/endpoint that we need ++ * to initialize the QH. ++ */ ++#define SCHEDULE_SLOP 10 ++void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb) ++{ ++ char *speed, *type; ++ int dev_speed; ++ uint32_t hub_addr, hub_port; ++ ++ dwc_memset(qh, 0, sizeof(dwc_otg_qh_t)); ++ ++ /* Initialize QH */ ++ qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; ++ ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info); ++ DWC_CIRCLEQ_INIT(&qh->qtd_list); ++ DWC_LIST_INIT(&qh->qh_list_entry); ++ qh->channel = NULL; ++ ++ /* FS/LS Enpoint on HS Hub ++ * NOT virtual root hub */ ++ dev_speed = hcd->fops->speed(hcd, urb->priv); ++ ++ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port); ++ qh->do_split = 0; ++ if (microframe_schedule) ++ qh->speed = dev_speed; ++ ++ qh->nak_frame = 0xffff; ++ ++ if (((dev_speed == USB_SPEED_LOW) || ++ (dev_speed == USB_SPEED_FULL)) && ++ (hub_addr != 0 && hub_addr != 1)) { ++ DWC_DEBUGPL(DBG_HCD, ++ "QH init: EP %d: TT found at hub addr %d, for port %d\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr, ++ hub_port); ++ qh->do_split = 1; ++ qh->skip_count = 0; ++ } ++ ++ if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) { ++ /* Compute scheduling parameters once and save them. */ ++ hprt0_data_t hprt; ++ ++ /** @todo Account for split transfers in the bus time. */ ++ int bytecount = ++ dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp); ++ ++ qh->usecs = ++ calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed), ++ qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS), ++ bytecount); ++ /* Start in a slightly future (micro)frame. */ ++ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number, ++ SCHEDULE_SLOP); ++ qh->interval = urb->interval; ++ ++#if 0 ++ /* Increase interrupt polling rate for debugging. */ ++ if (qh->ep_type == UE_INTERRUPT) { ++ qh->interval = 8; ++ } ++#endif ++ hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0); ++ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && ++ ((dev_speed == USB_SPEED_LOW) || ++ (dev_speed == USB_SPEED_FULL))) { ++ qh->interval *= 8; ++ qh->sched_frame |= 0x7; ++ qh->start_split_frame = qh->sched_frame; ++ } ++ ++ } ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", ++ dwc_otg_hcd_get_dev_addr(&urb->pipe_info)); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), ++ dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); ++ switch (dev_speed) { ++ case USB_SPEED_LOW: ++ qh->dev_speed = DWC_OTG_EP_SPEED_LOW; ++ speed = "low"; ++ break; ++ case USB_SPEED_FULL: ++ qh->dev_speed = DWC_OTG_EP_SPEED_FULL; ++ speed = "full"; ++ break; ++ case USB_SPEED_HIGH: ++ qh->dev_speed = DWC_OTG_EP_SPEED_HIGH; ++ speed = "high"; ++ break; ++ default: ++ speed = "?"; ++ break; ++ } ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed); ++ ++ switch (qh->ep_type) { ++ case UE_ISOCHRONOUS: ++ type = "isochronous"; ++ break; ++ case UE_INTERRUPT: ++ type = "interrupt"; ++ break; ++ case UE_CONTROL: ++ type = "control"; ++ break; ++ case UE_BULK: ++ type = "bulk"; ++ break; ++ default: ++ type = "?"; ++ break; ++ } ++ ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type); ++ ++#ifdef DEBUG ++ if (qh->ep_type == UE_INTERRUPT) { ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", ++ qh->usecs); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", ++ qh->interval); ++ } ++#endif ++ ++} ++ ++/** ++ * This function allocates and initializes a QH. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param urb Holds the information about the device/endpoint that we need ++ * to initialize the QH. ++ * @param atomic_alloc Flag to do atomic allocation if needed ++ * ++ * @return Returns pointer to the newly allocated QH, or NULL on error. */ ++dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * urb, int atomic_alloc) ++{ ++ dwc_otg_qh_t *qh; ++ ++ /* Allocate memory */ ++ /** @todo add memflags argument */ ++ qh = dwc_otg_hcd_qh_alloc(atomic_alloc); ++ if (qh == NULL) { ++ DWC_ERROR("qh allocation failed"); ++ return NULL; ++ } ++ ++ qh_init(hcd, qh, urb); ++ ++ if (hcd->core_if->dma_desc_enable ++ && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) { ++ dwc_otg_hcd_qh_free(hcd, qh); ++ return NULL; ++ } ++ ++ return qh; ++} ++ ++/* microframe_schedule=0 start */ ++ ++/** ++ * Checks that a channel is available for a periodic transfer. ++ * ++ * @return 0 if successful, negative error code otherise. ++ */ ++static int periodic_channel_available(dwc_otg_hcd_t * hcd) ++{ ++ /* ++ * Currently assuming that there is a dedicated host channnel for each ++ * periodic transaction plus at least one host channel for ++ * non-periodic transactions. ++ */ ++ int status; ++ int num_channels; ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) ++ && (hcd->periodic_channels < num_channels - 1)) { ++ status = 0; ++ } else { ++ DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", ++ __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++/** ++ * Checks that there is sufficient bandwidth for the specified QH in the ++ * periodic schedule. For simplicity, this calculation assumes that all the ++ * transfers in the periodic schedule may occur in the same (micro)frame. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH containing periodic bandwidth required. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status; ++ int16_t max_claimed_usecs; ++ ++ status = 0; ++ ++ if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) { ++ /* ++ * High speed mode. ++ * Max periodic usecs is 80% x 125 usec = 100 usec. ++ */ ++ ++ max_claimed_usecs = 100 - qh->usecs; ++ } else { ++ /* ++ * Full speed mode. ++ * Max periodic usecs is 90% x 1000 usec = 900 usec. ++ */ ++ max_claimed_usecs = 900 - qh->usecs; ++ } ++ ++ if (hcd->periodic_usecs > max_claimed_usecs) { ++ DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++/* microframe_schedule=0 end */ ++ ++/** ++ * Microframe scheduler ++ * track the total use in hcd->frame_usecs ++ * keep each qh use in qh->frame_usecs ++ * when surrendering the qh then donate the time back ++ */ ++const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 }; ++ ++/* ++ * called from dwc_otg_hcd.c:dwc_otg_hcd_init ++ */ ++int init_hcd_usecs(dwc_otg_hcd_t *_hcd) ++{ ++ int i; ++ for (i=0; i<8; i++) { ++ _hcd->frame_usecs[i] = max_uframe_usecs[i]; ++ } ++ return 0; ++} ++ ++static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int i; ++ unsigned short utime; ++ int t_left; ++ int ret; ++ int done; ++ ++ ret = -1; ++ utime = _qh->usecs; ++ t_left = utime; ++ i = 0; ++ done = 0; ++ while (done == 0) { ++ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */ ++ if (utime <= _hcd->frame_usecs[i]) { ++ _hcd->frame_usecs[i] -= utime; ++ _qh->frame_usecs[i] += utime; ++ t_left -= utime; ++ ret = i; ++ done = 1; ++ return ret; ++ } else { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ } ++ } ++ return ret; ++ } ++ ++/* ++ * use this for FS apps that can span multiple uframes ++ */ ++static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int i; ++ int j; ++ unsigned short utime; ++ int t_left; ++ int ret; ++ int done; ++ unsigned short xtime; ++ ++ ret = -1; ++ utime = _qh->usecs; ++ t_left = utime; ++ i = 0; ++ done = 0; ++loop: ++ while (done == 0) { ++ if(_hcd->frame_usecs[i] <= 0) { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ goto loop; ++ } ++ ++ /* ++ * we need n consecutive slots ++ * so use j as a start slot j plus j+1 must be enough time (for now) ++ */ ++ xtime= _hcd->frame_usecs[i]; ++ for (j = i+1 ; j < 8 ; j++ ) { ++ /* ++ * if we add this frame remaining time to xtime we may ++ * be OK, if not we need to test j for a complete frame ++ */ ++ if ((xtime+_hcd->frame_usecs[j]) < utime) { ++ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) { ++ j = 8; ++ ret = -1; ++ continue; ++ } ++ } ++ if (xtime >= utime) { ++ ret = i; ++ j = 8; /* stop loop with a good value ret */ ++ continue; ++ } ++ /* add the frame time to x time */ ++ xtime += _hcd->frame_usecs[j]; ++ /* we must have a fully available next frame or break */ ++ if ((xtime < utime) ++ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) { ++ ret = -1; ++ j = 8; /* stop loop with a bad value ret */ ++ continue; ++ } ++ } ++ if (ret >= 0) { ++ t_left = utime; ++ for (j = i; (t_left>0) && (j < 8); j++ ) { ++ t_left -= _hcd->frame_usecs[j]; ++ if ( t_left <= 0 ) { ++ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left; ++ _hcd->frame_usecs[j]= -t_left; ++ ret = i; ++ done = 1; ++ } else { ++ _qh->frame_usecs[j] += _hcd->frame_usecs[j]; ++ _hcd->frame_usecs[j] = 0; ++ } ++ } ++ } else { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ } ++ } ++ return ret; ++} ++ ++static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int ret; ++ ret = -1; ++ ++ if (_qh->speed == USB_SPEED_HIGH) { ++ /* if this is a hs transaction we need a full frame */ ++ ret = find_single_uframe(_hcd, _qh); ++ } else { ++ /* if this is a fs transaction we may need a sequence of frames */ ++ ret = find_multi_uframe(_hcd, _qh); ++ } ++ return ret; ++} ++ ++/** ++ * Checks that the max transfer size allowed in a host channel is large enough ++ * to handle the maximum data transfer in a single (micro)frame for a periodic ++ * transfer. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for a periodic endpoint. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status; ++ uint32_t max_xfer_size; ++ uint32_t max_channel_xfer_size; ++ ++ status = 0; ++ ++ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp); ++ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size; ++ ++ if (max_xfer_size > max_channel_xfer_size) { ++ DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n", ++ __func__, max_xfer_size, max_channel_xfer_size); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++ ++ ++/** ++ * Schedules an interrupt or isochronous transfer in the periodic schedule. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for the periodic transfer. The QH should already contain the ++ * scheduling information. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status = 0; ++ ++ if (microframe_schedule) { ++ int frame; ++ status = find_uframe(hcd, qh); ++ frame = -1; ++ if (status == 0) { ++ frame = 7; ++ } else { ++ if (status > 0 ) ++ frame = status-1; ++ } ++ ++ /* Set the new frame up */ ++ if (frame > -1) { ++ qh->sched_frame &= ~0x7; ++ qh->sched_frame |= (frame & 7); ++ } ++ ++ if (status != -1) ++ status = 0; ++ } else { ++ status = periodic_channel_available(hcd); ++ if (status) { ++ DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE ++ return status; ++ } ++ ++ status = check_periodic_bandwidth(hcd, qh); ++ } ++ if (status) { ++ DWC_INFO("%s: Insufficient periodic bandwidth for " ++ "periodic transfer.\n", __func__); ++ return status; ++ } ++ status = check_max_xfer_size(hcd, qh); ++ if (status) { ++ DWC_INFO("%s: Channel max transfer size too small " ++ "for periodic transfer.\n", __func__); ++ return status; ++ } ++ ++ if (hcd->core_if->dma_desc_enable) { ++ /* Don't rely on SOF and start in ready schedule */ ++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); ++ } ++ else { ++ if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame))) ++ { ++ hcd->fiq_state->next_sched_frame = qh->sched_frame; ++ ++ } ++ /* Always start in the inactive schedule. */ ++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry); ++ } ++ ++ if (!microframe_schedule) { ++ /* Reserve the periodic channel. */ ++ hcd->periodic_channels++; ++ } ++ ++ /* Update claimed usecs per (micro)frame. */ ++ hcd->periodic_usecs += qh->usecs; ++ ++ return status; ++} ++ ++ ++/** ++ * This function adds a QH to either the non periodic or periodic schedule if ++ * it is not already in the schedule. If the QH is already in the schedule, no ++ * action is taken. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status = 0; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ /* QH already in a schedule. */ ++ return status; ++ } ++ ++ /* Add the new QH to the appropriate schedule */ ++ if (dwc_qh_is_non_per(qh)) { ++ /* Always start in the inactive schedule. */ ++ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, ++ &qh->qh_list_entry); ++ //hcd->fiq_state->kick_np_queues = 1; ++ } else { ++ status = schedule_periodic(hcd, qh); ++ if ( !hcd->periodic_qh_count ) { ++ intr_mask.b.sofintr = 1; ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ } ++ } ++ hcd->periodic_qh_count++; ++ } ++ ++ return status; ++} ++ ++/** ++ * Removes an interrupt or isochronous transfer from the periodic schedule. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for the periodic transfer. ++ */ ++static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int i; ++ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); ++ ++ /* Update claimed usecs per (micro)frame. */ ++ hcd->periodic_usecs -= qh->usecs; ++ ++ if (!microframe_schedule) { ++ /* Release the periodic channel reservation. */ ++ hcd->periodic_channels--; ++ } else { ++ for (i = 0; i < 8; i++) { ++ hcd->frame_usecs[i] += qh->frame_usecs[i]; ++ qh->frame_usecs[i] = 0; ++ } ++ } ++} ++ ++/** ++ * Removes a QH from either the non-periodic or periodic schedule. Memory is ++ * not freed. ++ * ++ * @param hcd The HCD state structure. ++ * @param qh QH to remove from schedule. */ ++void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ /* QH is not in a schedule. */ ++ return; ++ } ++ ++ if (dwc_qh_is_non_per(qh)) { ++ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) { ++ hcd->non_periodic_qh_ptr = ++ hcd->non_periodic_qh_ptr->next; ++ } ++ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); ++ //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) ++ // hcd->fiq_state->kick_np_queues = 1; ++ } else { ++ deschedule_periodic(hcd, qh); ++ hcd->periodic_qh_count--; ++ if( !hcd->periodic_qh_count && !fiq_fsm_enable ) { ++ intr_mask.b.sofintr = 1; ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0); ++ } ++ } ++ } ++} ++ ++/** ++ * Deactivates a QH. For non-periodic QHs, removes the QH from the active ++ * non-periodic schedule. The QH is added to the inactive non-periodic ++ * schedule if any QTDs are still attached to the QH. ++ * ++ * For periodic QHs, the QH is removed from the periodic queued schedule. If ++ * there are any QTDs still attached to the QH, the QH is added to either the ++ * periodic inactive schedule or the periodic ready schedule and its next ++ * scheduled frame is calculated. The QH is placed in the ready schedule if ++ * the scheduled frame has been reached already. Otherwise it's placed in the ++ * inactive schedule. If there are no QTDs attached to the QH, the QH is ++ * completely removed from the periodic schedule. ++ */ ++void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ int sched_next_periodic_split) ++{ ++ if (dwc_qh_is_non_per(qh)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ /* Add back to inactive non-periodic schedule. */ ++ dwc_otg_hcd_qh_add(hcd, qh); ++ //hcd->fiq_state->kick_np_queues = 1; ++ } ++ } else { ++ uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd); ++ ++ if (qh->do_split) { ++ /* Schedule the next continuing periodic split transfer */ ++ if (sched_next_periodic_split) { ++ ++ qh->sched_frame = frame_number; ++ ++ if (dwc_frame_num_le(frame_number, ++ dwc_frame_num_inc ++ (qh->start_split_frame, ++ 1))) { ++ /* ++ * Allow one frame to elapse after start ++ * split microframe before scheduling ++ * complete split, but DONT if we are ++ * doing the next start split in the ++ * same frame for an ISOC out. ++ */ ++ if ((qh->ep_type != UE_ISOCHRONOUS) || ++ (qh->ep_is_in != 0)) { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->sched_frame, 1); ++ } ++ } ++ } else { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->start_split_frame, ++ qh->interval); ++ if (dwc_frame_num_le ++ (qh->sched_frame, frame_number)) { ++ qh->sched_frame = frame_number; ++ } ++ qh->sched_frame |= 0x7; ++ qh->start_split_frame = qh->sched_frame; ++ } ++ } else { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->sched_frame, qh->interval); ++ if (dwc_frame_num_le(qh->sched_frame, frame_number)) { ++ qh->sched_frame = frame_number; ++ } ++ } ++ ++ if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } else { ++ /* ++ * Remove from periodic_sched_queued and move to ++ * appropriate queue. ++ */ ++ if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) || ++ (!microframe_schedule && qh->sched_frame == frame_number)) { ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, ++ &qh->qh_list_entry); ++ } else { ++ if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame)) ++ { ++ hcd->fiq_state->next_sched_frame = qh->sched_frame; ++ } ++ ++ DWC_LIST_MOVE_HEAD ++ (&hcd->periodic_sched_inactive, ++ &qh->qh_list_entry); ++ } ++ } ++ } ++} ++ ++/** ++ * This function allocates and initializes a QTD. ++ * ++ * @param urb The URB to create a QTD from. Each URB-QTD pair will end up ++ * pointing to each other so each pair should have a unique correlation. ++ * @param atomic_alloc Flag to do atomic alloc if needed ++ * ++ * @return Returns pointer to the newly allocated QTD, or NULL on error. */ ++dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc) ++{ ++ dwc_otg_qtd_t *qtd; ++ ++ qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc); ++ if (qtd == NULL) { ++ return NULL; ++ } ++ ++ dwc_otg_hcd_qtd_init(qtd, urb); ++ return qtd; ++} ++ ++/** ++ * Initializes a QTD structure. ++ * ++ * @param qtd The QTD to initialize. ++ * @param urb The URB to use for initialization. */ ++void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb) ++{ ++ dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t)); ++ qtd->urb = urb; ++ if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) { ++ /* ++ * The only time the QTD data toggle is used is on the data ++ * phase of control transfers. This phase always starts with ++ * DATA1. ++ */ ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA1; ++ qtd->control_phase = DWC_OTG_CONTROL_SETUP; ++ } ++ ++ /* start split */ ++ qtd->complete_split = 0; ++ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ qtd->isoc_split_offset = 0; ++ qtd->in_process = 0; ++ ++ /* Store the qtd ptr in the urb to reference what QTD. */ ++ urb->qtd = qtd; ++ return; ++} ++ ++/** ++ * This function adds a QTD to the QTD-list of a QH. It will find the correct ++ * QH to place the QTD into. If it does not find a QH, then it will create a ++ * new QH. If the QH to which the QTD is added is not currently scheduled, it ++ * is placed into the proper schedule based on its EP type. ++ * HCD lock must be held and interrupts must be disabled on entry ++ * ++ * @param[in] qtd The QTD to add ++ * @param[in] hcd The DWC HCD structure ++ * @param[out] qh out parameter to return queue head ++ * @param atomic_alloc Flag to do atomic alloc if needed ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, ++ dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc) ++{ ++ int retval = 0; ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ /* ++ * Get the QH which holds the QTD-list to insert to. Create QH if it ++ * doesn't exist. ++ */ ++ if (*qh == NULL) { ++ *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc); ++ if (*qh == NULL) { ++ retval = -DWC_E_NO_MEMORY; ++ goto done; ++ } else { ++ if (fiq_enable) ++ hcd->fiq_state->kick_np_queues = 1; ++ } ++ } ++ retval = dwc_otg_hcd_qh_add(hcd, *qh); ++ if (retval == 0) { ++ DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd, ++ qtd_list_entry); ++ qtd->qh = *qh; ++ } ++done: ++ ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h +@@ -0,0 +1,188 @@ ++#ifndef _DWC_OS_DEP_H_ ++#define _DWC_OS_DEP_H_ ++ ++/** ++ * @file ++ * ++ * This file contains OS dependent structures. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++# include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++# include ++#else ++# include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++# include ++#else ++# include ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++# include ++#endif ++ ++#ifdef PCI_INTERFACE ++# include ++#endif ++ ++#ifdef LM_INTERFACE ++# include ++# include ++# include ++# include ++# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++# include ++# include ++# include ++# include ++# else ++/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure - ++ here we assume that the machine architecture provides definitions ++ in its own header ++*/ ++# include ++# include ++# endif ++#endif ++ ++#ifdef PLATFORM_INTERFACE ++#include ++#include ++#endif ++ ++/** The OS page size */ ++#define DWC_OS_PAGE_SIZE PAGE_SIZE ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ++typedef int gfp_t; ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++# define IRQF_SHARED SA_SHIRQ ++#endif ++ ++typedef struct os_dependent { ++ /** Base address returned from ioremap() */ ++ void *base; ++ ++ /** Register offset for Diagnostic API */ ++ uint32_t reg_offset; ++ ++ /** Base address for MPHI peripheral */ ++ void *mphi_base; ++ ++#ifdef LM_INTERFACE ++ struct lm_device *lmdev; ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *pcidev; ++ ++ /** Start address of a PCI region */ ++ resource_size_t rsrc_start; ++ ++ /** Length address of a PCI region */ ++ resource_size_t rsrc_len; ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platformdev; ++#endif ++ ++} os_dependent_t; ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++ ++/* Type for the our device on the chosen bus */ ++#if defined(LM_INTERFACE) ++typedef struct lm_device dwc_bus_dev_t; ++#elif defined(PCI_INTERFACE) ++typedef struct pci_dev dwc_bus_dev_t; ++#elif defined(PLATFORM_INTERFACE) ++typedef struct platform_device dwc_bus_dev_t; ++#endif ++ ++/* Helper macro to retrieve drvdata from the device on the chosen bus */ ++#if defined(LM_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev) ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev) ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev) ++#endif ++ ++/** ++ * Helper macro returning the otg_device structure of a given struct device ++ * ++ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev) ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ struct lm_device *lm_dev = \ ++ container_of(_dev, struct lm_device, dev); \ ++ _var = lm_get_drvdata(lm_dev); \ ++ } while (0) ++ ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ _var = dev_get_drvdata(_dev); \ ++ } while (0) ++ ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ struct platform_device *platform_dev = \ ++ container_of(_dev, struct platform_device, dev); \ ++ _var = platform_get_drvdata(platform_dev); \ ++ } while (0) ++#endif ++ ++ ++/** ++ * Helper macro returning the struct dev of the given struct os_dependent ++ * ++ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep) ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev) ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev) ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev) ++#endif ++ ++ ++ ++ ++#endif /* _DWC_OS_DEP_H_ */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c +@@ -0,0 +1,2712 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ ++ * $Revision: #101 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++/** @file ++ * This file implements PCD Core. All code in this file is portable and doesn't ++ * use any OS specific functions. ++ * PCD Core provides Interface, defined in ++ * header file, which can be used to implement OS specific PCD interface. ++ * ++ * An important function of the PCD is managing interrupts generated ++ * by the DWC_otg controller. The implementation of the DWC_otg device ++ * mode interrupt service routines is in dwc_otg_pcd_intr.c. ++ * ++ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc). ++ * @todo Does it work when the request size is greater than DEPTSIZ ++ * transfer size ++ * ++ */ ++ ++#include "dwc_otg_pcd.h" ++ ++#ifdef DWC_UTE_CFI ++#include "dwc_otg_cfi.h" ++ ++extern int init_cfi(cfiobject_t * cfiobj); ++#endif ++ ++/** ++ * Choose endpoint from ep arrays using usb_ep structure. ++ */ ++static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) ++{ ++ int i; ++ if (pcd->ep0.priv == handle) { ++ return &pcd->ep0; ++ } ++ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) { ++ if (pcd->in_ep[i].priv == handle) ++ return &pcd->in_ep[i]; ++ if (pcd->out_ep[i].priv == handle) ++ return &pcd->out_ep[i]; ++ } ++ ++ return NULL; ++} ++ ++/** ++ * This function completes a request. It call's the request call back. ++ */ ++void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req, ++ int32_t status) ++{ ++ unsigned stopped = ep->stopped; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req); ++ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); ++ ++ /* don't modify queue heads during completion callback */ ++ ep->stopped = 1; ++ /* spin_unlock/spin_lock now done in fops->complete() */ ++ ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status, ++ req->actual); ++ ++ if (ep->pcd->request_pending > 0) { ++ --ep->pcd->request_pending; ++ } ++ ++ ep->stopped = stopped; ++ DWC_FREE(req); ++} ++ ++/** ++ * This function terminates all the requsts in the EP request queue. ++ */ ++void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req; ++ ++ ep->stopped = 1; ++ ++ /* called with irqs blocked?? */ ++ while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN); ++ } ++} ++ ++void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd, ++ const struct dwc_otg_pcd_function_ops *fops) ++{ ++ pcd->fops = fops; ++} ++ ++/** ++ * PCD Callback function for initializing the PCD when switching to ++ * device mode. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_start_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ /* ++ * Initialized the Core for Device mode. ++ */ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dwc_otg_core_dev_init(core_if); ++ /* Set core_if's lock pointer to the pcd->lock */ ++ core_if->lock = pcd->lock; ++ } ++ return 1; ++} ++ ++/** CFI-specific buffer allocation function for EP */ ++#ifdef DWC_UTE_CFI ++uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr, ++ size_t buflen, int flags) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ ep = get_ep_from_handle(pcd, pep); ++ if (!ep) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen, ++ flags); ++} ++#else ++uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr, ++ size_t buflen, int flags); ++#endif ++ ++/** ++ * PCD Callback function for notifying the PCD when resuming from ++ * suspend. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_resume_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ ++ if (pcd->fops->resume) { ++ pcd->fops->resume(pcd); ++ } ++ ++ /* Stop the SRP timeout timer. */ ++ if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) ++ || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) { ++ if (GET_CORE_IF(pcd)->srp_timer_started) { ++ GET_CORE_IF(pcd)->srp_timer_started = 0; ++ DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer); ++ } ++ } ++ return 1; ++} ++ ++/** ++ * PCD Callback function for notifying the PCD device is suspended. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_suspend_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ ++ if (pcd->fops->suspend) { ++ DWC_SPINUNLOCK(pcd->lock); ++ pcd->fops->suspend(pcd); ++ DWC_SPINLOCK(pcd->lock); ++ } ++ ++ return 1; ++} ++ ++/** ++ * PCD Callback function for stopping the PCD when switching to Host ++ * mode. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_stop_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd); ++ ++ dwc_otg_pcd_stop(pcd); ++ return 1; ++} ++ ++/** ++ * PCD Callback structure for handling mode switching. ++ */ ++static dwc_otg_cil_callbacks_t pcd_callbacks = { ++ .start = dwc_otg_pcd_start_cb, ++ .stop = dwc_otg_pcd_stop_cb, ++ .suspend = dwc_otg_pcd_suspend_cb, ++ .resume_wakeup = dwc_otg_pcd_resume_cb, ++ .p = 0, /* Set at registration */ ++}; ++ ++/** ++ * This function allocates a DMA Descriptor chain for the Endpoint ++ * buffer to be used for a transfer to/from the specified endpoint. ++ */ ++dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr, ++ uint32_t count) ++{ ++ return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t), ++ dma_desc_addr); ++} ++ ++/** ++ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc. ++ */ ++void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr, ++ uint32_t dma_desc_addr, uint32_t count) ++{ ++ DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr, ++ dma_desc_addr); ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ ++ dsts_data_t dsts = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ int i, j; ++ uint32_t len; ++ ++ if (dwc_ep->is_in) ++ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval; ++ else ++ dwc_ep->desc_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ ++ /** Allocate descriptors for double buffering */ ++ dwc_ep->iso_desc_addr = ++ dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr, ++ dwc_ep->desc_cnt * 2); ++ if (dwc_ep->desc_addr) { ++ DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__); ++ return; ++ } ++ ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr; ++ dma_addr_t dma_ad; ++ uint32_t data_per_desc; ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[dwc_ep->num]; ++ int offset; ++ ++ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; ++ dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma)); ++ ++ /** Buffer 0 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr0; ++ ++ sts.b_iso_out.bs = BS_HOST_READY; ++ sts.b_iso_out.rxsts = 0; ++ sts.b_iso_out.l = 0; ++ sts.b_iso_out.sp = 0; ++ sts.b_iso_out.ioc = 0; ++ sts.b_iso_out.pid = 0; ++ sts.b_iso_out.framenum = 0; ++ ++ offset = 0; ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ /** Buffer 1 descriptors setup */ ++ sts.b_iso_out.ioc = 0; ++ dma_ad = dwc_ep->dma_addr1; ++ ++ offset = 0; ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ ++ data_per_desc = ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ } ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ sts.b_iso_out.l = 1; ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = 0; ++ ++ /** Write dma_ad into DOEPDMA register */ ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) dwc_ep->iso_dma_desc_addr); ++ ++ } ++ /** ISO IN EP */ ++ else { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr; ++ dma_addr_t dma_ad; ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[dwc_ep->num]; ++ unsigned int frmnumber; ++ fifosize_data_t txfifosize, rxfifosize; ++ ++ txfifosize.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]-> ++ dtxfsts); ++ rxfifosize.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ ++ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ ++ dma_ad = dwc_ep->dma_addr0; ++ ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ sts.b_iso_in.bs = BS_HOST_READY; ++ sts.b_iso_in.txsts = 0; ++ sts.b_iso_in.sp = ++ (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0; ++ sts.b_iso_in.ioc = 0; ++ sts.b_iso_in.pid = dwc_ep->pkt_per_frm; ++ ++ frmnumber = dwc_ep->next_frame; ++ ++ sts.b_iso_in.framenum = frmnumber; ++ sts.b_iso_in.txbytes = dwc_ep->data_per_frame; ++ sts.b_iso_in.l = 0; ++ ++ /** Buffer 0 descriptors setup */ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ dma_ad += dwc_ep->data_per_frame; ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ } ++ ++ sts.b_iso_in.ioc = 1; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++dma_desc; ++ ++ /** Buffer 1 descriptors setup */ ++ sts.b_iso_in.ioc = 0; ++ dma_ad = dwc_ep->dma_addr1; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ dma_ad += dwc_ep->data_per_frame; ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ ++ sts.b_iso_in.ioc = 0; ++ } ++ sts.b_iso_in.ioc = 1; ++ sts.b_iso_in.l = 1; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval; ++ ++ /** Write dma_ad into diepdma register */ ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) dwc_ep->iso_dma_desc_addr); ++ } ++ /** Enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ depctl.b.epena = 1; ++ depctl.b.usbactep = 1; ++ depctl.b.cnak = 1; ++ ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); ++} ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) { ++ return; ++ } else { ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ ++ ep->xfer_len = ++ ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval; ++ ep->pkt_cnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ ep->xfer_count = 0; ++ ep->xfer_buff = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; ++ ep->dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; ++ ++ if (ep->is_in) { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.mc = ep->pkt_per_frm; ++ deptsiz.b.xfersize = ep->xfer_len; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ DWC_WRITE_REG32(& ++ (core_if->dev_if->in_ep_regs[ep->num]-> ++ diepdma), (uint32_t) ep->dma_addr); ++ ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len + (ep->maxpacket - 1)) / ++ ep->maxpacket; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ DWC_WRITE_REG32(& ++ (core_if->dev_if->out_ep_regs[ep->num]-> ++ doepdma), (uint32_t) ep->dma_addr); ++ ++ } ++ /** Enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for an EP and ++ * starts the transfer. For an IN transfer, the packets will be ++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, ++ * the packets are unloaded from the Rx FIFO in the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ if (ep->is_in) { ++ ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm; ++ } else { ++ ep->desc_cnt = ep->pkt_cnt; ++ } ++ dwc_otg_iso_ep_start_ddma_transfer(core_if, ep); ++ } else { ++ if (core_if->pti_enh_enable) { ++ dwc_otg_iso_ep_start_buf_transfer(core_if, ep); ++ } else { ++ ep->cur_pkt_addr = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep-> ++ xfer_buff0; ++ ep->cur_pkt_dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep-> ++ dma_addr0; ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ep); ++ } ++ } ++ } else { ++ ep->cur_pkt_addr = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; ++ ep->cur_pkt_dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ep); ++ } ++} ++ ++/** ++ * This function stops transfer for an EP and ++ * resets the ep's variables. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in == 1) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ /* disable the ep */ ++ depctl.d32 = DWC_READ_REG32(addr); ++ ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ ++ DWC_WRITE_REG32(addr, depctl.d32); ++ ++ if (core_if->dma_desc_enable && ++ ep->iso_desc_addr && ep->iso_dma_desc_addr) { ++ dwc_otg_ep_free_desc_chain(ep->iso_desc_addr, ++ ep->iso_dma_desc_addr, ++ ep->desc_cnt * 2); ++ } ++ ++ /* reset varibales */ ++ ep->dma_addr0 = 0; ++ ep->dma_addr1 = 0; ++ ep->xfer_buff0 = 0; ++ ep->xfer_buff1 = 0; ++ ep->data_per_frame = 0; ++ ep->data_pattern_frame = 0; ++ ep->sync_frame = 0; ++ ep->buf_proc_intrvl = 0; ++ ep->bInterval = 0; ++ ep->proc_buf_num = 0; ++ ep->pkt_per_frm = 0; ++ ep->pkt_per_frm = 0; ++ ep->desc_cnt = 0; ++ ep->iso_desc_addr = 0; ++ ep->iso_dma_desc_addr = 0; ++} ++ ++int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0, ++ dwc_dma_t dma1, int sync_frame, int dp_frame, ++ int data_per_frame, int start_frame, ++ int buf_proc_intrvl, void *req_handle, ++ int atomic_alloc) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags = 0; ++ dwc_ep_t *dwc_ep; ++ int32_t frm_data; ++ dsts_data_t dsts; ++ dwc_otg_core_if_t *core_if; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if (!ep || !ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ core_if = GET_CORE_IF(pcd); ++ dwc_ep = &ep->dwc_ep; ++ ++ if (ep->iso_req_handle) { ++ DWC_WARN("ISO request in progress\n"); ++ } ++ ++ dwc_ep->dma_addr0 = dma0; ++ dwc_ep->dma_addr1 = dma1; ++ ++ dwc_ep->xfer_buff0 = buf0; ++ dwc_ep->xfer_buff1 = buf1; ++ ++ dwc_ep->data_per_frame = data_per_frame; ++ ++ /** @todo - pattern data support is to be implemented in the future */ ++ dwc_ep->data_pattern_frame = dp_frame; ++ dwc_ep->sync_frame = sync_frame; ++ ++ dwc_ep->buf_proc_intrvl = buf_proc_intrvl; ++ ++ dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1); ++ ++ dwc_ep->proc_buf_num = 0; ++ ++ dwc_ep->pkt_per_frm = 0; ++ frm_data = ep->dwc_ep.data_per_frame; ++ while (frm_data > 0) { ++ dwc_ep->pkt_per_frm++; ++ frm_data -= ep->dwc_ep.maxpacket; ++ } ++ ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ if (start_frame == -1) { ++ dwc_ep->next_frame = dsts.b.soffn + 1; ++ if (dwc_ep->bInterval != 1) { ++ dwc_ep->next_frame = ++ dwc_ep->next_frame + (dwc_ep->bInterval - 1 - ++ dwc_ep->next_frame % ++ dwc_ep->bInterval); ++ } ++ } else { ++ dwc_ep->next_frame = start_frame; ++ } ++ ++ if (!core_if->pti_enh_enable) { ++ dwc_ep->pkt_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ } else { ++ dwc_ep->pkt_cnt = ++ (dwc_ep->data_per_frame * ++ (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval) ++ - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket; ++ } ++ ++ if (core_if->dma_desc_enable) { ++ dwc_ep->desc_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ } ++ ++ if (atomic_alloc) { ++ dwc_ep->pkt_info = ++ DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } else { ++ dwc_ep->pkt_info = ++ DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } ++ if (!dwc_ep->pkt_info) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_NO_MEMORY; ++ } ++ if (core_if->pti_enh_enable) { ++ dwc_memset(dwc_ep->pkt_info, 0, ++ sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } ++ ++ dwc_ep->cur_pkt = 0; ++ ep->iso_req_handle = req_handle; ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ dwc_otg_iso_ep_start_transfer(core_if, dwc_ep); ++ return 0; ++} ++ ++int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle) ++{ ++ dwc_irqflags_t flags = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep || !ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ dwc_ep = &ep->dwc_ep; ++ ++ dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep); ++ ++ DWC_FREE(dwc_ep->pkt_info); ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (ep->iso_req_handle != req_handle) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ ep->iso_req_handle = 0; ++ return 0; ++} ++ ++/** ++ * This function is used for perodical data exchnage between PCD and gadget drivers. ++ * for Isochronous EPs ++ * ++ * - Every time a sync period completes this function is called to ++ * perform data exchange between PCD and gadget ++ */ ++void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, ++ void *req_handle) ++{ ++ int i; ++ dwc_ep_t *dwc_ep; ++ ++ dwc_ep = &ep->dwc_ep; ++ ++ DWC_SPINUNLOCK(ep->pcd->lock); ++ pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle, ++ dwc_ep->proc_buf_num ^ 0x1); ++ DWC_SPINLOCK(ep->pcd->lock); ++ ++ for (i = 0; i < dwc_ep->pkt_cnt; ++i) { ++ dwc_ep->pkt_info[i].status = 0; ++ dwc_ep->pkt_info[i].offset = 0; ++ dwc_ep->pkt_info[i].length = 0; ++ } ++} ++ ++int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *iso_req_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ dwc_ep = &ep->dwc_ep; ++ ++ return dwc_ep->pkt_cnt; ++} ++ ++void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *iso_req_handle, int packet, ++ int *status, int *actual, int *offset) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep) ++ DWC_WARN("bad ep\n"); ++ ++ dwc_ep = &ep->dwc_ep; ++ ++ *status = dwc_ep->pkt_info[packet].status; ++ *actual = dwc_ep->pkt_info[packet].length; ++ *offset = dwc_ep->pkt_info[packet].offset; ++} ++ ++#endif /* DWC_EN_ISOC */ ++ ++static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep, ++ uint32_t is_in, uint32_t ep_num) ++{ ++ /* Init EP structure */ ++ pcd_ep->desc = 0; ++ pcd_ep->pcd = pcd; ++ pcd_ep->stopped = 1; ++ pcd_ep->queue_sof = 0; ++ ++ /* Init DWC ep structure */ ++ pcd_ep->dwc_ep.is_in = is_in; ++ pcd_ep->dwc_ep.num = ep_num; ++ pcd_ep->dwc_ep.active = 0; ++ pcd_ep->dwc_ep.tx_fifo_num = 0; ++ /* Control until ep is actvated */ ++ pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; ++ pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; ++ pcd_ep->dwc_ep.dma_addr = 0; ++ pcd_ep->dwc_ep.start_xfer_buff = 0; ++ pcd_ep->dwc_ep.xfer_buff = 0; ++ pcd_ep->dwc_ep.xfer_len = 0; ++ pcd_ep->dwc_ep.xfer_count = 0; ++ pcd_ep->dwc_ep.sent_zlp = 0; ++ pcd_ep->dwc_ep.total_len = 0; ++ pcd_ep->dwc_ep.desc_addr = 0; ++ pcd_ep->dwc_ep.dma_desc_addr = 0; ++ DWC_CIRCLEQ_INIT(&pcd_ep->queue); ++} ++ ++/** ++ * Initialize ep's ++ */ ++static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd) ++{ ++ int i; ++ uint32_t hwcfg1; ++ dwc_otg_pcd_ep_t *ep; ++ int in_ep_cntr, out_ep_cntr; ++ uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps; ++ uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps; ++ ++ /** ++ * Initialize the EP0 structure. ++ */ ++ ep = &pcd->ep0; ++ dwc_otg_pcd_init_ep(pcd, ep, 0, 0); ++ ++ in_ep_cntr = 0; ++ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3; ++ for (i = 1; in_ep_cntr < num_in_eps; i++) { ++ if ((hwcfg1 & 0x1) == 0) { ++ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr]; ++ in_ep_cntr++; ++ /** ++ * @todo NGS: Add direction to EP, based on contents ++ * of HWCFG1. Need a copy of HWCFG1 in pcd structure? ++ * sprintf(";r ++ */ ++ dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i); ++ ++ DWC_CIRCLEQ_INIT(&ep->queue); ++ } ++ hwcfg1 >>= 2; ++ } ++ ++ out_ep_cntr = 0; ++ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2; ++ for (i = 1; out_ep_cntr < num_out_eps; i++) { ++ if ((hwcfg1 & 0x1) == 0) { ++ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr]; ++ out_ep_cntr++; ++ /** ++ * @todo NGS: Add direction to EP, based on contents ++ * of HWCFG1. Need a copy of HWCFG1 in pcd structure? ++ * sprintf(";r ++ */ ++ dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i); ++ DWC_CIRCLEQ_INIT(&ep->queue); ++ } ++ hwcfg1 >>= 2; ++ } ++ ++ pcd->ep0state = EP0_DISCONNECT; ++ pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE; ++ pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; ++} ++ ++/** ++ * This function is called when the SRP timer expires. The SRP should ++ * complete within 6 seconds. ++ */ ++static void srp_timeout(void *ptr) ++{ ++ gotgctl_data_t gotgctl; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ volatile uint32_t *addr = &core_if->core_global_regs->gotgctl; ++ ++ gotgctl.d32 = DWC_READ_REG32(addr); ++ ++ core_if->srp_timer_started = 0; ++ ++ if (core_if->adp_enable) { ++ if (gotgctl.b.bsesvld == 0) { ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ DWC_PRINTF("SRP Timeout BSESSVLD = 0\n"); ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ DWC_PRINTF("SRP Timeout BSESSVLD = 1\n"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } ++ ++ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && ++ (core_if->core_params->i2c_enable)) { ++ DWC_PRINTF("SRP Timeout\n"); ++ ++ if ((core_if->srp_success) && (gotgctl.b.bsesvld)) { ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++ ++ /* Clear Session Request */ ++ gotgctl.d32 = 0; ++ gotgctl.b.sesreq = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, ++ gotgctl.d32, 0); ++ ++ core_if->srp_success = 0; ++ } else { ++ __DWC_ERROR("Device not connected/responding\n"); ++ gotgctl.b.sesreq = 0; ++ DWC_WRITE_REG32(addr, gotgctl.d32); ++ } ++ } else if (gotgctl.b.sesreq) { ++ DWC_PRINTF("SRP Timeout\n"); ++ ++ __DWC_ERROR("Device not connected/responding\n"); ++ gotgctl.b.sesreq = 0; ++ DWC_WRITE_REG32(addr, gotgctl.d32); ++ } else { ++ DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32); ++ } ++} ++ ++/** ++ * Tasklet ++ * ++ */ ++extern void start_next_request(dwc_otg_pcd_ep_t * ep); ++ ++static void start_xfer_tasklet_func(void *data) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ int i; ++ depctl_data_t diepctl; ++ ++ DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n"); ++ ++ diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl); ++ ++ if (pcd->ep0.queue_sof) { ++ pcd->ep0.queue_sof = 0; ++ start_next_request(&pcd->ep0); ++ // break; ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; i++) { ++ depctl_data_t diepctl; ++ diepctl.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl); ++ ++ if (pcd->in_ep[i].queue_sof) { ++ pcd->in_ep[i].queue_sof = 0; ++ start_next_request(&pcd->in_ep[i]); ++ // break; ++ } ++ } ++ ++ return; ++} ++ ++/** ++ * This function initialized the PCD portion of the driver. ++ * ++ */ ++dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_pcd_t *pcd = NULL; ++ dwc_otg_dev_if_t *dev_if; ++ int i; ++ ++ /* ++ * Allocate PCD structure ++ */ ++ pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t)); ++ ++ if (pcd == NULL) { ++ return NULL; ++ } ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock); ++#else ++ pcd->lock = DWC_SPINLOCK_ALLOC(); ++#endif ++ DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n", ++ pcd, core_if);//GRAYG ++ if (!pcd->lock) { ++ DWC_ERROR("Could not allocate lock for pcd"); ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ /* Set core_if's lock pointer to hcd->lock */ ++ core_if->lock = pcd->lock; ++ pcd->core_if = core_if; ++ ++ dev_if = core_if->dev_if; ++ dev_if->isoc_ep = NULL; ++ ++ if (core_if->hwcfg4.b.ded_fifo_en) { ++ DWC_PRINTF("Dedicated Tx FIFOs mode\n"); ++ } else { ++ DWC_PRINTF("Shared Tx FIFO mode\n"); ++ } ++ ++ /* ++ * Initialized the Core for Device mode here if there is nod ADP support. ++ * Otherwise it will be done later in dwc_otg_adp_start routine. ++ */ ++ if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) { ++ dwc_otg_core_dev_init(core_if); ++ } ++ ++ /* ++ * Register the PCD Callbacks. ++ */ ++ dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd); ++ ++ /* ++ * Initialize the DMA buffer for SETUP packets ++ */ ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ pcd->setup_pkt = ++ DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5, ++ &pcd->setup_pkt_dma_handle); ++ if (pcd->setup_pkt == NULL) { ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ ++ pcd->status_buf = ++ DWC_DMA_ALLOC(sizeof(uint16_t), ++ &pcd->status_buf_dma_handle); ++ if (pcd->status_buf == NULL) { ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, ++ pcd->setup_pkt, pcd->setup_pkt_dma_handle); ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ dev_if->setup_desc_addr[0] = ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_setup_desc_addr[0], 1); ++ dev_if->setup_desc_addr[1] = ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_setup_desc_addr[1], 1); ++ dev_if->in_desc_addr = ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_in_desc_addr, 1); ++ dev_if->out_desc_addr = ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_out_desc_addr, 1); ++ pcd->data_terminated = 0; ++ ++ if (dev_if->setup_desc_addr[0] == 0 ++ || dev_if->setup_desc_addr[1] == 0 ++ || dev_if->in_desc_addr == 0 ++ || dev_if->out_desc_addr == 0) { ++ ++ if (dev_if->out_desc_addr) ++ dwc_otg_ep_free_desc_chain ++ (dev_if->out_desc_addr, ++ dev_if->dma_out_desc_addr, 1); ++ if (dev_if->in_desc_addr) ++ dwc_otg_ep_free_desc_chain ++ (dev_if->in_desc_addr, ++ dev_if->dma_in_desc_addr, 1); ++ if (dev_if->setup_desc_addr[1]) ++ dwc_otg_ep_free_desc_chain ++ (dev_if->setup_desc_addr[1], ++ dev_if->dma_setup_desc_addr[1], 1); ++ if (dev_if->setup_desc_addr[0]) ++ dwc_otg_ep_free_desc_chain ++ (dev_if->setup_desc_addr[0], ++ dev_if->dma_setup_desc_addr[0], 1); ++ ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, ++ pcd->setup_pkt, ++ pcd->setup_pkt_dma_handle); ++ DWC_DMA_FREE(sizeof(*pcd->status_buf), ++ pcd->status_buf, ++ pcd->status_buf_dma_handle); ++ ++ DWC_FREE(pcd); ++ ++ return NULL; ++ } ++ } ++ } else { ++ pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5); ++ if (pcd->setup_pkt == NULL) { ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ ++ pcd->status_buf = DWC_ALLOC(sizeof(uint16_t)); ++ if (pcd->status_buf == NULL) { ++ DWC_FREE(pcd->setup_pkt); ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ } ++ ++ dwc_otg_pcd_reinit(pcd); ++ ++ /* Allocate the cfi object for the PCD */ ++#ifdef DWC_UTE_CFI ++ pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t)); ++ if (NULL == pcd->cfi) ++ goto fail; ++ if (init_cfi(pcd->cfi)) { ++ CFI_INFO("%s: Failed to init the CFI object\n", __func__); ++ goto fail; ++ } ++#endif ++ ++ /* Initialize tasklets */ ++ pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet", ++ start_xfer_tasklet_func, pcd); ++ pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet", ++ do_test_mode, pcd); ++ ++ /* Initialize SRP timer */ ++ core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if); ++ ++ if (core_if->core_params->dev_out_nak) { ++ /** ++ * Initialize xfer timeout timer. Implemented for ++ * 2.93a feature "Device DDMA OUT NAK Enhancement" ++ */ ++ for(i = 0; i < MAX_EPS_CHANNELS; i++) { ++ pcd->core_if->ep_xfer_timer[i] = ++ DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout, ++ &pcd->core_if->ep_xfer_info[i]); ++ } ++ } ++ ++ return pcd; ++#ifdef DWC_UTE_CFI ++fail: ++#endif ++ if (pcd->setup_pkt) ++ DWC_FREE(pcd->setup_pkt); ++ if (pcd->status_buf) ++ DWC_FREE(pcd->status_buf); ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi) ++ DWC_FREE(pcd->cfi); ++#endif ++ if (pcd) ++ DWC_FREE(pcd); ++ return NULL; ++ ++} ++ ++/** ++ * Remove PCD specific data ++ */ ++void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ int i; ++ if (pcd->core_if->core_params->dev_out_nak) { ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]); ++ pcd->core_if->ep_xfer_info[i].state = 0; ++ } ++ } ++ ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt, ++ pcd->setup_pkt_dma_handle); ++ DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf, ++ pcd->status_buf_dma_handle); ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], ++ dev_if->dma_setup_desc_addr ++ [0], 1); ++ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], ++ dev_if->dma_setup_desc_addr ++ [1], 1); ++ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, ++ dev_if->dma_in_desc_addr, 1); ++ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, ++ dev_if->dma_out_desc_addr, ++ 1); ++ } ++ } else { ++ DWC_FREE(pcd->setup_pkt); ++ DWC_FREE(pcd->status_buf); ++ } ++ DWC_SPINLOCK_FREE(pcd->lock); ++ /* Set core_if's lock pointer to NULL */ ++ pcd->core_if->lock = NULL; ++ ++ DWC_TASK_FREE(pcd->start_xfer_tasklet); ++ DWC_TASK_FREE(pcd->test_mode_tasklet); ++ if (pcd->core_if->core_params->dev_out_nak) { ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ if (pcd->core_if->ep_xfer_timer[i]) { ++ DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]); ++ } ++ } ++ } ++ ++/* Release the CFI object's dynamic memory */ ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi->ops.release) { ++ pcd->cfi->ops.release(pcd->cfi); ++ } ++#endif ++ ++ DWC_FREE(pcd); ++} ++ ++/** ++ * Returns whether registered pcd is dual speed or not ++ */ ++uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) || ++ ((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls))) { ++ return 0; ++ } ++ ++ return 1; ++} ++ ++/** ++ * Returns whether registered pcd is OTG capable or not ++ */ ++uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ gusbcfg_data_t usbcfg = {.d32 = 0 }; ++ ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) { ++ return 0; ++ } ++ ++ return 1; ++} ++ ++/** ++ * This function assigns periodic Tx FIFO to an periodic EP ++ * in shared Tx FIFO mode ++ */ ++static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t TxMsk = 1; ++ int i; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) { ++ if ((TxMsk & core_if->tx_msk) == 0) { ++ core_if->tx_msk |= TxMsk; ++ return i + 1; ++ } ++ TxMsk <<= 1; ++ } ++ return 0; ++} ++ ++/** ++ * This function assigns periodic Tx FIFO to an periodic EP ++ * in shared Tx FIFO mode ++ */ ++static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t PerTxMsk = 1; ++ int i; ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) { ++ if ((PerTxMsk & core_if->p_tx_msk) == 0) { ++ core_if->p_tx_msk |= PerTxMsk; ++ return i + 1; ++ } ++ PerTxMsk <<= 1; ++ } ++ return 0; ++} ++ ++/** ++ * This function releases periodic Tx FIFO ++ * in shared Tx FIFO mode ++ */ ++static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if, ++ uint32_t fifo_num) ++{ ++ core_if->p_tx_msk = ++ (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk; ++} ++ ++/** ++ * This function releases periodic Tx FIFO ++ * in shared Tx FIFO mode ++ */ ++static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num) ++{ ++ core_if->tx_msk = ++ (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk; ++} ++ ++/** ++ * This function is being called from gadget ++ * to enable PCD endpoint. ++ */ ++int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, ++ const uint8_t * ep_desc, void *usb_ep) ++{ ++ int num, dir; ++ dwc_otg_pcd_ep_t *ep = NULL; ++ const usb_endpoint_descriptor_t *desc; ++ dwc_irqflags_t flags; ++ fifosize_data_t dptxfsiz = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 }; ++ int retval = 0; ++ int i, epcount; ++ ++ desc = (const usb_endpoint_descriptor_t *)ep_desc; ++ ++ if (!desc) { ++ pcd->ep0.priv = usb_ep; ++ ep = &pcd->ep0; ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ num = UE_GET_ADDR(desc->bEndpointAddress); ++ dir = UE_GET_DIR(desc->bEndpointAddress); ++ ++ if (!desc->wMaxPacketSize) { ++ DWC_WARN("bad maxpacketsize\n"); ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ if (dir == UE_DIR_IN) { ++ epcount = pcd->core_if->dev_if->num_in_eps; ++ for (i = 0; i < epcount; i++) { ++ if (num == pcd->in_ep[i].dwc_ep.num) { ++ ep = &pcd->in_ep[i]; ++ break; ++ } ++ } ++ } else { ++ epcount = pcd->core_if->dev_if->num_out_eps; ++ for (i = 0; i < epcount; i++) { ++ if (num == pcd->out_ep[i].dwc_ep.num) { ++ ep = &pcd->out_ep[i]; ++ break; ++ } ++ } ++ } ++ ++ if (!ep) { ++ DWC_WARN("bad address\n"); ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ ep->desc = desc; ++ ep->priv = usb_ep; ++ ++ /* ++ * Activate the EP ++ */ ++ ep->stopped = 0; ++ ++ ep->dwc_ep.is_in = (dir == UE_DIR_IN); ++ ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize); ++ ++ ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE; ++ ++ if (ep->dwc_ep.is_in) { ++ if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ ep->dwc_ep.tx_fifo_num = 0; ++ ++ if (ep->dwc_ep.type == UE_ISOCHRONOUS) { ++ /* ++ * if ISOC EP then assign a Periodic Tx FIFO. ++ */ ++ ep->dwc_ep.tx_fifo_num = ++ assign_perio_tx_fifo(GET_CORE_IF(pcd)); ++ } ++ } else { ++ /* ++ * if Dedicated FIFOs mode is on then assign a Tx FIFO. ++ */ ++ ep->dwc_ep.tx_fifo_num = ++ assign_tx_fifo(GET_CORE_IF(pcd)); ++ } ++ ++ /* Calculating EP info controller base address */ ++ if (ep->dwc_ep.tx_fifo_num ++ && GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ gdfifocfg.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->gdfifocfg); ++ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; ++ dptxfsiz.d32 = ++ (DWC_READ_REG32 ++ (&GET_CORE_IF(pcd)->core_global_regs-> ++ dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16); ++ gdfifocfg.b.epinfobase = ++ gdfifocfgbase.d32 + dptxfsiz.d32; ++ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) { ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->gdfifocfg, ++ gdfifocfg.d32); ++ } ++ } ++ } ++ /* Set initial data PID. */ ++ if (ep->dwc_ep.type == UE_BULK) { ++ ep->dwc_ep.data_pid_start = 0; ++ } ++ ++ /* Alloc DMA Descriptors */ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++#ifndef DWC_UTE_PER_IO ++ if (ep->dwc_ep.type != UE_ISOCHRONOUS) { ++#endif ++ ep->dwc_ep.desc_addr = ++ dwc_otg_ep_alloc_desc_chain(&ep-> ++ dwc_ep.dma_desc_addr, ++ MAX_DMA_DESC_CNT); ++ if (!ep->dwc_ep.desc_addr) { ++ DWC_WARN("%s, can't allocate DMA descriptor\n", ++ __func__); ++ retval = -DWC_E_SHUTDOWN; ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ goto out; ++ } ++#ifndef DWC_UTE_PER_IO ++ } ++#endif ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n", ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc); ++#ifdef DWC_UTE_PER_IO ++ ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1); ++#endif ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1); ++ ep->dwc_ep.frame_num = 0xFFFFFFFF; ++ } ++ ++ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi->ops.ep_enable) { ++ pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep); ++ } ++#endif ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++out: ++ return retval; ++} ++ ++/** ++ * This function is being called from gadget ++ * to disable PCD endpoint. ++ */ ++int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ dwc_otg_dev_dma_desc_t *desc_addr; ++ dwc_dma_t dma_desc_addr; ++ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ fifosize_data_t dptxfsiz = {.d32 = 0 }; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if (!ep || !ep->desc) { ++ DWC_DEBUGPL(DBG_PCD, "bad ep address\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ dwc_otg_request_nuke(ep); ++ ++ dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ if (pcd->core_if->core_params->dev_out_nak) { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]); ++ pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0; ++ } ++ ep->desc = NULL; ++ ep->stopped = 1; ++ ++ gdfifocfg.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg); ++ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; ++ ++ if (ep->dwc_ep.is_in) { ++ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ /* Flush the Tx FIFO */ ++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ++ ep->dwc_ep.tx_fifo_num); ++ } ++ release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ /* Decreasing EPinfo Base Addr */ ++ dptxfsiz.d32 = ++ (DWC_READ_REG32 ++ (&GET_CORE_IF(pcd)-> ++ core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16); ++ gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32; ++ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) { ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg, ++ gdfifocfg.d32); ++ } ++ } ++ } ++ ++ /* Free DMA Descriptors */ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ if (ep->dwc_ep.type != UE_ISOCHRONOUS) { ++ desc_addr = ep->dwc_ep.desc_addr; ++ dma_desc_addr = ep->dwc_ep.dma_desc_addr; ++ ++ /* Cannot call dma_free_coherent() with IRQs disabled */ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr, ++ MAX_DMA_DESC_CNT); ++ ++ goto out_unlocked; ++ } ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++out_unlocked: ++ DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ return 0; ++ ++} ++ ++/******************************************************************************/ ++#ifdef DWC_UTE_PER_IO ++ ++/** ++ * Free the request and its extended parts ++ * ++ */ ++void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req) ++{ ++ DWC_FREE(req->ext_req.per_io_frame_descs); ++ DWC_FREE(req); ++} ++ ++/** ++ * Start the next request in the endpoint's queue. ++ * ++ */ ++int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd, ++ dwc_otg_pcd_ep_t * ep) ++{ ++ int i; ++ dwc_otg_pcd_request_t *req = NULL; ++ dwc_ep_t *dwcep = NULL; ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_pkt_desc_port *ddesc_iso; ++ uint16_t nat; ++ depctl_data_t diepctl; ++ ++ dwcep = &ep->dwc_ep; ++ ++ if (dwcep->xiso_active_xfers > 0) { ++#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers ++ DWC_WARN("There are currently active transfers for EP%d \ ++ (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers, ++ dwcep->xiso_queued_xfers); ++#endif ++ return 0; ++ } ++ ++ nat = UGETW(ep->desc->wMaxPacketSize); ++ nat = (nat >> 11) & 0x03; ++ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ereq = &req->ext_req; ++ ep->stopped = 0; ++ ++ /* Get the frame number */ ++ dwcep->xiso_frame_num = ++ dwc_otg_get_frame_number(GET_CORE_IF(pcd)); ++ DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num); ++ ++ ddesc_iso = ereq->per_io_frame_descs; ++ ++ if (dwcep->is_in) { ++ /* Setup DMA Descriptor chain for IN Isoc request */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ //if ((i % (nat + 1)) == 0) ++ if ( i > 0 ) ++ dwcep->xiso_frame_num = ++ (dwcep->xiso_bInterval + ++ dwcep->xiso_frame_num) & 0x3FFF; ++ dwcep->desc_addr[i].buf = ++ req->dma + ddesc_iso[i].offset; ++ dwcep->desc_addr[i].status.b_iso_in.txbytes = ++ ddesc_iso[i].length; ++ dwcep->desc_addr[i].status.b_iso_in.framenum = ++ dwcep->xiso_frame_num; ++ dwcep->desc_addr[i].status.b_iso_in.bs = ++ BS_HOST_READY; ++ dwcep->desc_addr[i].status.b_iso_in.txsts = 0; ++ dwcep->desc_addr[i].status.b_iso_in.sp = ++ (ddesc_iso[i].length % ++ dwcep->maxpacket) ? 1 : 0; ++ dwcep->desc_addr[i].status.b_iso_in.ioc = 0; ++ dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1; ++ dwcep->desc_addr[i].status.b_iso_in.l = 0; ++ ++ /* Process the last descriptor */ ++ if (i == ereq->pio_pkt_count - 1) { ++ dwcep->desc_addr[i].status.b_iso_in.ioc = 1; ++ dwcep->desc_addr[i].status.b_iso_in.l = 1; ++ } ++ } ++ ++ /* Setup and start the transfer for this endpoint */ ++ dwcep->xiso_active_xfers++; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[dwcep->num]->diepdma, ++ dwcep->dma_desc_addr); ++ diepctl.d32 = 0; ++ diepctl.b.epena = 1; ++ diepctl.b.cnak = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[dwcep->num]->diepctl, 0, ++ diepctl.d32); ++ } else { ++ /* Setup DMA Descriptor chain for OUT Isoc request */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ //if ((i % (nat + 1)) == 0) ++ dwcep->xiso_frame_num = (dwcep->xiso_bInterval + ++ dwcep->xiso_frame_num) & 0x3FFF; ++ dwcep->desc_addr[i].buf = ++ req->dma + ddesc_iso[i].offset; ++ dwcep->desc_addr[i].status.b_iso_out.rxbytes = ++ ddesc_iso[i].length; ++ dwcep->desc_addr[i].status.b_iso_out.framenum = ++ dwcep->xiso_frame_num; ++ dwcep->desc_addr[i].status.b_iso_out.bs = ++ BS_HOST_READY; ++ dwcep->desc_addr[i].status.b_iso_out.rxsts = 0; ++ dwcep->desc_addr[i].status.b_iso_out.sp = ++ (ddesc_iso[i].length % ++ dwcep->maxpacket) ? 1 : 0; ++ dwcep->desc_addr[i].status.b_iso_out.ioc = 0; ++ dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1; ++ dwcep->desc_addr[i].status.b_iso_out.l = 0; ++ ++ /* Process the last descriptor */ ++ if (i == ereq->pio_pkt_count - 1) { ++ dwcep->desc_addr[i].status.b_iso_out.ioc = 1; ++ dwcep->desc_addr[i].status.b_iso_out.l = 1; ++ } ++ } ++ ++ /* Setup and start the transfer for this endpoint */ ++ dwcep->xiso_active_xfers++; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->out_ep_regs[dwcep->num]-> ++ doepdma, dwcep->dma_desc_addr); ++ diepctl.d32 = 0; ++ diepctl.b.epena = 1; ++ diepctl.b.cnak = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->out_ep_regs[dwcep->num]-> ++ doepctl, 0, diepctl.d32); ++ } ++ ++ } else { ++ ep->stopped = 1; ++ } ++ ++ return 0; ++} ++ ++/** ++ * - Remove the request from the queue ++ */ ++void complete_xiso_ep(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req = NULL; ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_pkt_desc_port *ddesc_iso = NULL; ++ dwc_ep_t *dwcep = NULL; ++ int i; ++ ++ //DWC_DEBUG(); ++ dwcep = &ep->dwc_ep; ++ ++ /* Get the first pending request from the queue */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ return; ++ } ++ dwcep->xiso_active_xfers--; ++ dwcep->xiso_queued_xfers--; ++ /* Remove this request from the queue */ ++ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ return; ++ } ++ ++ ep->stopped = 1; ++ ereq = &req->ext_req; ++ ddesc_iso = ereq->per_io_frame_descs; ++ ++ if (dwcep->xiso_active_xfers < 0) { ++ DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num, ++ dwcep->xiso_active_xfers); ++ } ++ ++ /* Fill the Isoc descs of portable extended req from dma descriptors */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ if (dwcep->is_in) { /* IN endpoints */ ++ ddesc_iso[i].actual_length = ddesc_iso[i].length - ++ dwcep->desc_addr[i].status.b_iso_in.txbytes; ++ ddesc_iso[i].status = ++ dwcep->desc_addr[i].status.b_iso_in.txsts; ++ } else { /* OUT endpoints */ ++ ddesc_iso[i].actual_length = ddesc_iso[i].length - ++ dwcep->desc_addr[i].status.b_iso_out.rxbytes; ++ ddesc_iso[i].status = ++ dwcep->desc_addr[i].status.b_iso_out.rxsts; ++ } ++ } ++ ++ DWC_SPINUNLOCK(ep->pcd->lock); ++ ++ /* Call the completion function in the non-portable logic */ ++ ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0, ++ &req->ext_req); ++ ++ DWC_SPINLOCK(ep->pcd->lock); ++ ++ /* Free the request - specific freeing needed for extended request object */ ++ dwc_pcd_xiso_ereq_free(ep, req); ++ ++ /* Start the next request */ ++ dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep); ++ ++ return; ++} ++ ++/** ++ * Create and initialize the Isoc pkt descriptors of the extended request. ++ * ++ */ ++static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req, ++ void *ereq_nonport, ++ int atomic_alloc) ++{ ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_xreq_port *req_mapped = NULL; ++ struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */ ++ uint32_t pkt_count; ++ int i; ++ ++ ereq = &req->ext_req; ++ req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport; ++ pkt_count = req_mapped->pio_pkt_count; ++ ++ /* Create the isoc descs */ ++ if (atomic_alloc) { ++ ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count); ++ } else { ++ ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count); ++ } ++ ++ if (!ipds) { ++ DWC_ERROR("Failed to allocate isoc descriptors"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Initialize the extended request fields */ ++ ereq->per_io_frame_descs = ipds; ++ ereq->error_count = 0; ++ ereq->pio_alloc_pkt_count = pkt_count; ++ ereq->pio_pkt_count = pkt_count; ++ ereq->tr_sub_flags = req_mapped->tr_sub_flags; ++ ++ /* Init the Isoc descriptors */ ++ for (i = 0; i < pkt_count; i++) { ++ ipds[i].length = req_mapped->per_io_frame_descs[i].length; ++ ipds[i].offset = req_mapped->per_io_frame_descs[i].offset; ++ ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */ ++ ipds[i].actual_length = ++ req_mapped->per_io_frame_descs[i].actual_length; ++ } ++ ++ return 0; ++} ++ ++static void prn_ext_request(struct dwc_iso_xreq_port *ereq) ++{ ++ struct dwc_iso_pkt_desc_port *xfd = NULL; ++ int i; ++ ++ DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs); ++ DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags); ++ DWC_DEBUG("error_count=%d", ereq->error_count); ++ DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count); ++ DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count); ++ DWC_DEBUG("res=%d", ereq->res); ++ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ xfd = &ereq->per_io_frame_descs[0]; ++ DWC_DEBUG("FD #%d", i); ++ ++ DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length); ++ DWC_DEBUG("xfd->length=%d", xfd->length); ++ DWC_DEBUG("xfd->offset=%d", xfd->offset); ++ DWC_DEBUG("xfd->status=%d", xfd->status); ++ } ++} ++ ++/** ++ * ++ */ ++int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, ++ int zero, void *req_handle, int atomic_alloc, ++ void *ereq_nonport) ++{ ++ dwc_otg_pcd_request_t *req = NULL; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ int res; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ /* We support this extension only for DDMA mode */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ if (!GET_CORE_IF(pcd)->dma_desc_enable) ++ return -DWC_E_INVALID; ++ ++ /* Create a dwc_otg_pcd_request_t object */ ++ if (atomic_alloc) { ++ req = DWC_ALLOC_ATOMIC(sizeof(*req)); ++ } else { ++ req = DWC_ALLOC(sizeof(*req)); ++ } ++ ++ if (!req) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Create the Isoc descs for this request which shall be the exact match ++ * of the structure sent to us from the non-portable logic */ ++ res = ++ dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc); ++ if (res) { ++ DWC_WARN("Failed to init the Isoc descriptors"); ++ DWC_FREE(req); ++ return res; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry); ++ req->buf = buf; ++ req->dma = dma_buf; ++ req->length = buflen; ++ req->sent_zlp = zero; ++ req->priv = req_handle; ++ ++ //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = buflen; ++ ++ /* Add this request to the tail */ ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ ep->dwc_ep.xiso_queued_xfers++; ++ ++//DWC_DEBUG("CP_0"); ++//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags); ++//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport); ++//prn_ext_request(&req->ext_req); ++ ++ //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ /* If the req->status == ASAP then check if there is any active transfer ++ * for this endpoint. If no active transfers, then get the first entry ++ * from the queue and start that transfer ++ */ ++ if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) { ++ res = dwc_otg_pcd_xiso_start_next_request(pcd, ep); ++ if (res) { ++ DWC_WARN("Failed to start the next Isoc transfer"); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ DWC_FREE(req); ++ return res; ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return 0; ++} ++ ++#endif ++/* END ifdef DWC_UTE_PER_IO ***************************************************/ ++int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, ++ int zero, void *req_handle, int atomic_alloc) ++{ ++ dwc_irqflags_t flags; ++ dwc_otg_pcd_request_t *req; ++ dwc_otg_pcd_ep_t *ep; ++ uint32_t max_transfer; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (atomic_alloc) { ++ req = DWC_ALLOC_ATOMIC(sizeof(*req)); ++ } else { ++ req = DWC_ALLOC(sizeof(*req)); ++ } ++ ++ if (!req) { ++ return -DWC_E_NO_MEMORY; ++ } ++ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry); ++ if (!GET_CORE_IF(pcd)->core_params->opt) { ++ if (ep->dwc_ep.num != 0) { ++ DWC_ERROR("queue req %p, len %d buf %p\n", ++ req_handle, buflen, buf); ++ } ++ } ++ ++ req->buf = buf; ++ req->dma = dma_buf; ++ req->length = buflen; ++ req->sent_zlp = zero; ++ req->priv = req_handle; ++ req->dw_align_buf = NULL; ++ if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable ++ && !GET_CORE_IF(pcd)->dma_desc_enable) ++ req->dw_align_buf = DWC_DMA_ALLOC(buflen, ++ &req->dw_align_buf_dma); ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ /* ++ * After adding request to the queue for IN ISOC wait for In Token Received ++ * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token ++ * Received when EP is disabled interrupt to obtain starting microframe ++ * (odd/even) start transfer ++ */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ if (req != 0) { ++ depctl_data_t depctl = {.d32 = ++ DWC_READ_REG32(&pcd->core_if->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]-> ++ diepctl) }; ++ ++pcd->request_pending; ++ ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ if (ep->dwc_ep.is_in) { ++ depctl.b.cnak = 1; ++ DWC_WRITE_REG32(&pcd->core_if->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]-> ++ diepctl, depctl.d32); ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ } ++ return 0; ++ } ++ ++ /* ++ * For EP0 IN without premature status, zlp is required? ++ */ ++ if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) { ++ DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num); ++ //_req->zero = 1; ++ } ++ ++ /* Start the transfer */ ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) { ++ /* EP0 Transfer? */ ++ if (ep->dwc_ep.num == 0) { ++ switch (pcd->ep0state) { ++ case EP0_IN_DATA_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_IN_DATA_PHASE\n", ++ __func__); ++ break; ++ ++ case EP0_OUT_DATA_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_OUT_DATA_PHASE\n", ++ __func__); ++ if (pcd->request_config) { ++ /* Complete STATUS PHASE */ ++ ep->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ } ++ break; ++ ++ case EP0_IN_STATUS_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_IN_STATUS_PHASE\n", ++ __func__); ++ break; ++ ++ default: ++ DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n", ++ pcd->ep0state); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_SHUTDOWN; ++ } ++ ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ ep->dwc_ep.xfer_len = buflen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ if (zero) { ++ if ((ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.xfer_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ ++ } ++ ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } // non-ep0 endpoints ++ else { ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ /* store the request length */ ++ ep->dwc_ep.cfi_req_len = buflen; ++ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ++ ep, req); ++ } else { ++#endif ++ max_transfer = ++ GET_CORE_IF(ep->pcd)->core_params-> ++ max_transfer_size; ++ ++ /* Setup and start the Transfer */ ++ if (req->dw_align_buf){ ++ if (ep->dwc_ep.is_in) ++ dwc_memcpy(req->dw_align_buf, ++ buf, buflen); ++ ep->dwc_ep.dma_addr = ++ req->dw_align_buf_dma; ++ ep->dwc_ep.start_xfer_buff = ++ req->dw_align_buf; ++ ep->dwc_ep.xfer_buff = ++ req->dw_align_buf; ++ } else { ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ } ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = buflen; ++ ++ ep->dwc_ep.maxxfer = max_transfer; ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ uint32_t out_max_xfer = ++ DDMA_MAX_TRANSFER_SIZE - ++ (DDMA_MAX_TRANSFER_SIZE % 4); ++ if (ep->dwc_ep.is_in) { ++ if (ep->dwc_ep.maxxfer > ++ DDMA_MAX_TRANSFER_SIZE) { ++ ep->dwc_ep.maxxfer = ++ DDMA_MAX_TRANSFER_SIZE; ++ } ++ } else { ++ if (ep->dwc_ep.maxxfer > ++ out_max_xfer) { ++ ep->dwc_ep.maxxfer = ++ out_max_xfer; ++ } ++ } ++ } ++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { ++ ep->dwc_ep.maxxfer -= ++ (ep->dwc_ep.maxxfer % ++ ep->dwc_ep.maxpacket); ++ } ++ ++ if (zero) { ++ if ((ep->dwc_ep.total_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.total_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } ++ ++ if (req != 0) { ++ ++pcd->request_pending; ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ if (ep->dwc_ep.is_in && ep->stopped ++ && !(GET_CORE_IF(pcd)->dma_enable)) { ++ /** @todo NGS Create a function for this. */ ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.intktxfemp = 1; ++ if (GET_CORE_IF(pcd)->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->dev_global_regs->diepeachintmsk ++ [ep->dwc_ep.num], 0, ++ diepmsk.d32); ++ } else { ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->dev_global_regs-> ++ diepmsk, 0, diepmsk.d32); ++ } ++ ++ } ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return 0; ++} ++ ++int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle) ++{ ++ dwc_irqflags_t flags; ++ dwc_otg_pcd_request_t *req; ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) { ++ DWC_WARN("bad argument\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ /* make sure it's actually queued on this endpoint */ ++ DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) { ++ if (req->priv == (void *)req_handle) { ++ break; ++ } ++ } ++ ++ if (req->priv != (void *)req_handle) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_INVALID; ++ } ++ ++ if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) { ++ dwc_otg_request_done(ep, req, -DWC_E_RESTART); ++ } else { ++ req = NULL; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return req ? 0 : -DWC_E_SHUTDOWN; ++ ++} ++ ++/** ++ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests ++ * ++ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) ++ * requests. If the gadget driver clears the halt status, it will ++ * automatically unwedge the endpoint. ++ * ++ * Returns zero on success, else negative DWC error code. ++ */ ++int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ int retval = 0; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if ((!ep->desc && ep != &pcd->ep0) || ++ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { ++ DWC_WARN("%s, bad ep\n", __func__); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ retval = -DWC_E_AGAIN; ++ } else { ++ /* This code needs to be reviewed */ ++ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) { ++ dtxfsts_data_t txstatus; ++ fifosize_data_t txfifosize; ++ ++ txfifosize.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->dtxfsiz[ep->dwc_ep. ++ tx_fifo_num]); ++ txstatus.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->in_ep_regs[ep->dwc_ep.num]-> ++ dtxfsts); ++ ++ if (txstatus.b.txfspcavail < txfifosize.b.depth) { ++ DWC_WARN("%s() Data In Tx Fifo\n", __func__); ++ retval = -DWC_E_AGAIN; ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return retval; ++} ++ ++int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ int retval = 0; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if (!ep || (!ep->desc && ep != &pcd->ep0) || ++ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { ++ DWC_WARN("%s, bad ep\n", __func__); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ retval = -DWC_E_AGAIN; ++ } else if (value == 0) { ++ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } else if (value == 1) { ++ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) { ++ dtxfsts_data_t txstatus; ++ fifosize_data_t txfifosize; ++ ++ txfifosize.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs-> ++ dtxfsiz[ep->dwc_ep.tx_fifo_num]); ++ txstatus.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]->dtxfsts); ++ ++ if (txstatus.b.txfspcavail < txfifosize.b.depth) { ++ DWC_WARN("%s() Data In Tx Fifo\n", __func__); ++ retval = -DWC_E_AGAIN; ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } ++ } else if (value == 2) { ++ ep->dwc_ep.stall_clear_flag = 0; ++ } else if (value == 3) { ++ ep->dwc_ep.stall_clear_flag = 1; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return retval; ++} ++ ++/** ++ * This function initiates remote wakeup of the host from suspend state. ++ */ ++void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set) ++{ ++ dctl_data_t dctl = { 0 }; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dsts_data_t dsts; ++ ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ if (!dsts.b.suspsts) { ++ DWC_WARN("Remote wakeup while is not in suspend state\n"); ++ } ++ /* Check if DEVICE_REMOTE_WAKEUP feature enabled */ ++ if (pcd->remote_wakeup_enable) { ++ if (set) { ++ ++ if (core_if->adp_enable) { ++ gpwrdn_data_t gpwrdn; ++ ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ dwc_otg_initiate_srp(core_if); ++ } ++ ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); ++ ++ dwc_mdelay(2); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, dctl.d32, 0); ++ DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n"); ++ } ++ } else { ++ DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n"); ++ } ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * This function initiates remote wakeup of the host from L1 sleep state. ++ */ ++void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set) ++{ ++ glpmcfg_data_t lpmcfg; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ ++ /* Check if we are in L1 state */ ++ if (!lpmcfg.b.prt_sleep_sts) { ++ DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n"); ++ return; ++ } ++ ++ /* Check if host allows remote wakeup */ ++ if (!lpmcfg.b.rem_wkup_en) { ++ DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n"); ++ return; ++ } ++ ++ /* Check if Resume OK */ ++ if (!lpmcfg.b.sleep_state_resumeok) { ++ DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n"); ++ return; ++ } ++ ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ if (set) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.rmtwkupsig = 1; ++ /* Set RmtWkUpSig bit to start remote wakup signaling. ++ * Hardware will automatically clear this bit. ++ */ ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ 0, dctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); ++ } ++ ++} ++#endif ++ ++/** ++ * Performs remote wakeup. ++ */ ++void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_irqflags_t flags; ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->lx_state == DWC_OTG_L1) { ++ dwc_otg_pcd_rem_wkup_from_sleep(pcd, set); ++ } else { ++#endif ++ dwc_otg_pcd_rem_wkup_from_suspend(pcd, set); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ } ++#endif ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ } ++ return; ++} ++ ++void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dctl_data_t dctl = { 0 }; ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dctl.b.sftdiscon = 1; ++ DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ dwc_udelay(no_of_usecs); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0); ++ ++ } else{ ++ DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n"); ++ } ++ return; ++ ++} ++ ++int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd) ++{ ++ dsts_data_t dsts; ++ gotgctl_data_t gotgctl; ++ ++ /* ++ * This function starts the Protocol if no session is in progress. If ++ * a session is already in progress, but the device is suspended, ++ * remote wakeup signaling is started. ++ */ ++ ++ /* Check if valid session */ ++ gotgctl.d32 = ++ DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl)); ++ if (gotgctl.b.bsesvld) { ++ /* Check if suspend state */ ++ dsts.d32 = ++ DWC_READ_REG32(& ++ (GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts)); ++ if (dsts.b.suspsts) { ++ dwc_otg_pcd_remote_wakeup(pcd, 1); ++ } ++ } else { ++ dwc_otg_pcd_initiate_srp(pcd); ++ } ++ ++ return 0; ++ ++} ++ ++/** ++ * Start the SRP timer to detect when the SRP does not complete within ++ * 6 seconds. ++ * ++ * @param pcd the pcd structure. ++ */ ++void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd) ++{ ++ dwc_irqflags_t flags; ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ dwc_otg_initiate_srp(GET_CORE_IF(pcd)); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++} ++ ++int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd) ++{ ++ return dwc_otg_get_frame_number(GET_CORE_IF(pcd)); ++} ++ ++int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd) ++{ ++ return GET_CORE_IF(pcd)->core_params->lpm_enable; ++} ++ ++uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->b_hnp_enable; ++} ++ ++uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->a_hnp_support; ++} ++ ++uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->a_alt_hnp_support; ++} ++ ++int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->remote_wakeup_enable; ++} ++ ++#endif /* DWC_HOST_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h +@@ -0,0 +1,266 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $ ++ * $Revision: #48 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++#if !defined(__DWC_PCD_H__) ++#define __DWC_PCD_H__ ++ ++#include "dwc_otg_os_dep.h" ++#include "usb.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_pcd_if.h" ++struct cfiobject; ++ ++/** ++ * @file ++ * ++ * This file contains the structures, constants, and interfaces for ++ * the Perpherial Contoller Driver (PCD). ++ * ++ * The Peripheral Controller Driver (PCD) for Linux will implement the ++ * Gadget API, so that the existing Gadget drivers can be used. For ++ * the Mass Storage Function driver the File-backed USB Storage Gadget ++ * (FBS) driver will be used. The FBS driver supports the ++ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only ++ * transports. ++ * ++ */ ++ ++/** Invalid DMA Address */ ++#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0) ++ ++/** Max Transfer size for any EP */ ++#define DDMA_MAX_TRANSFER_SIZE 65535 ++ ++/** ++ * Get the pointer to the core_if from the pcd pointer. ++ */ ++#define GET_CORE_IF( _pcd ) (_pcd->core_if) ++ ++/** ++ * States of EP0. ++ */ ++typedef enum ep0_state { ++ EP0_DISCONNECT, /* no host */ ++ EP0_IDLE, ++ EP0_IN_DATA_PHASE, ++ EP0_OUT_DATA_PHASE, ++ EP0_IN_STATUS_PHASE, ++ EP0_OUT_STATUS_PHASE, ++ EP0_STALL, ++} ep0state_e; ++ ++/** Fordward declaration.*/ ++struct dwc_otg_pcd; ++ ++/** DWC_otg iso request structure. ++ * ++ */ ++typedef struct usb_iso_request dwc_otg_pcd_iso_request_t; ++ ++#ifdef DWC_UTE_PER_IO ++ ++/** ++ * This shall be the exact analogy of the same type structure defined in the ++ * usb_gadget.h. Each descriptor contains ++ */ ++struct dwc_iso_pkt_desc_port { ++ uint32_t offset; ++ uint32_t length; /* expected length */ ++ uint32_t actual_length; ++ uint32_t status; ++}; ++ ++struct dwc_iso_xreq_port { ++ /** transfer/submission flag */ ++ uint32_t tr_sub_flags; ++ /** Start the request ASAP */ ++#define DWC_EREQ_TF_ASAP 0x00000002 ++ /** Just enqueue the request w/o initiating a transfer */ ++#define DWC_EREQ_TF_ENQUEUE 0x00000004 ++ ++ /** ++ * count of ISO packets attached to this request - shall ++ * not exceed the pio_alloc_pkt_count ++ */ ++ uint32_t pio_pkt_count; ++ /** count of ISO packets allocated for this request */ ++ uint32_t pio_alloc_pkt_count; ++ /** number of ISO packet errors */ ++ uint32_t error_count; ++ /** reserved for future extension */ ++ uint32_t res; ++ /** Will be allocated and freed in the UTE gadget and based on the CFC value */ ++ struct dwc_iso_pkt_desc_port *per_io_frame_descs; ++}; ++#endif ++/** DWC_otg request structure. ++ * This structure is a list of requests. ++ */ ++typedef struct dwc_otg_pcd_request { ++ void *priv; ++ void *buf; ++ dwc_dma_t dma; ++ uint32_t length; ++ uint32_t actual; ++ unsigned sent_zlp:1; ++ /** ++ * Used instead of original buffer if ++ * it(physical address) is not dword-aligned. ++ **/ ++ uint8_t *dw_align_buf; ++ dwc_dma_t dw_align_buf_dma; ++ ++ DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry; ++#ifdef DWC_UTE_PER_IO ++ struct dwc_iso_xreq_port ext_req; ++ //void *priv_ereq_nport; /* */ ++#endif ++} dwc_otg_pcd_request_t; ++ ++DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request); ++ ++/** PCD EP structure. ++ * This structure describes an EP, there is an array of EPs in the PCD ++ * structure. ++ */ ++typedef struct dwc_otg_pcd_ep { ++ /** USB EP Descriptor */ ++ const usb_endpoint_descriptor_t *desc; ++ ++ /** queue of dwc_otg_pcd_requests. */ ++ struct req_list queue; ++ unsigned stopped:1; ++ unsigned disabling:1; ++ unsigned dma:1; ++ unsigned queue_sof:1; ++ ++#ifdef DWC_EN_ISOC ++ /** ISOC req handle passed */ ++ void *iso_req_handle; ++#endif //_EN_ISOC_ ++ ++ /** DWC_otg ep data. */ ++ dwc_ep_t dwc_ep; ++ ++ /** Pointer to PCD */ ++ struct dwc_otg_pcd *pcd; ++ ++ void *priv; ++} dwc_otg_pcd_ep_t; ++ ++/** DWC_otg PCD Structure. ++ * This structure encapsulates the data for the dwc_otg PCD. ++ */ ++struct dwc_otg_pcd { ++ const struct dwc_otg_pcd_function_ops *fops; ++ /** The DWC otg device pointer */ ++ struct dwc_otg_device *otg_dev; ++ /** Core Interface */ ++ dwc_otg_core_if_t *core_if; ++ /** State of EP0 */ ++ ep0state_e ep0state; ++ /** EP0 Request is pending */ ++ unsigned ep0_pending:1; ++ /** Indicates when SET CONFIGURATION Request is in process */ ++ unsigned request_config:1; ++ /** The state of the Remote Wakeup Enable. */ ++ unsigned remote_wakeup_enable:1; ++ /** The state of the B-Device HNP Enable. */ ++ unsigned b_hnp_enable:1; ++ /** The state of A-Device HNP Support. */ ++ unsigned a_hnp_support:1; ++ /** The state of the A-Device Alt HNP support. */ ++ unsigned a_alt_hnp_support:1; ++ /** Count of pending Requests */ ++ unsigned request_pending; ++ ++ /** SETUP packet for EP0 ++ * This structure is allocated as a DMA buffer on PCD initialization ++ * with enough space for up to 3 setup packets. ++ */ ++ union { ++ usb_device_request_t req; ++ uint32_t d32[2]; ++ } *setup_pkt; ++ ++ dwc_dma_t setup_pkt_dma_handle; ++ ++ /* Additional buffer and flag for CTRL_WR premature case */ ++ uint8_t *backup_buf; ++ unsigned data_terminated; ++ ++ /** 2-byte dma buffer used to return status from GET_STATUS */ ++ uint16_t *status_buf; ++ dwc_dma_t status_buf_dma_handle; ++ ++ /** EP0 */ ++ dwc_otg_pcd_ep_t ep0; ++ ++ /** Array of IN EPs. */ ++ dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1]; ++ /** Array of OUT EPs. */ ++ dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1]; ++ /** number of valid EPs in the above array. */ ++// unsigned num_eps : 4; ++ dwc_spinlock_t *lock; ++ ++ /** Tasklet to defer starting of TEST mode transmissions until ++ * Status Phase has been completed. ++ */ ++ dwc_tasklet_t *test_mode_tasklet; ++ ++ /** Tasklet to delay starting of xfer in DMA mode */ ++ dwc_tasklet_t *start_xfer_tasklet; ++ ++ /** The test mode to enter when the tasklet is executed. */ ++ unsigned test_mode; ++ /** The cfi_api structure that implements most of the CFI API ++ * and OTG specific core configuration functionality ++ */ ++#ifdef DWC_UTE_CFI ++ struct cfiobject *cfi; ++#endif ++ ++}; ++ ++//FIXME this functions should be static, and this prototypes should be removed ++extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep); ++extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, ++ dwc_otg_pcd_request_t * req, int32_t status); ++ ++void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, ++ void *req_handle); ++ ++extern void do_test_mode(void *data); ++#endif ++#endif /* DWC_HOST_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h +@@ -0,0 +1,360 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $ ++ * $Revision: #11 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++#if !defined(__DWC_PCD_IF_H__) ++#define __DWC_PCD_IF_H__ ++ ++//#include "dwc_os.h" ++#include "dwc_otg_core_if.h" ++ ++/** @file ++ * This file defines DWC_OTG PCD Core API. ++ */ ++ ++struct dwc_otg_pcd; ++typedef struct dwc_otg_pcd dwc_otg_pcd_t; ++ ++/** Maxpacket size for EP0 */ ++#define MAX_EP0_SIZE 64 ++/** Maxpacket size for any EP */ ++#define MAX_PACKET_SIZE 1024 ++ ++/** @name Function Driver Callbacks */ ++/** @{ */ ++ ++/** This function will be called whenever a previously queued request has ++ * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a ++ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset, ++ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid ++ * parameters. */ ++typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, ++ uint32_t actual); ++/** ++ * This function will be called whenever a previousle queued ISOC request has ++ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count ++ * function. ++ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_* ++ * functions. ++ */ ++typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int proc_buf_num); ++/** This function should handle any SETUP request that cannot be handled by the ++ * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any ++ * class-specific requests, etc. The function must non-blocking. ++ * ++ * Returns 0 on success. ++ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported. ++ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes. ++ * Returns -DWC_E_SHUTDOWN on any other error. */ ++typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes); ++/** This is called whenever the device has been disconnected. The function ++ * driver should take appropriate action to clean up all pending requests in the ++ * PCD Core, remove all endpoints (except ep0), and initialize back to reset ++ * state. */ ++typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has been connected. */ ++typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed); ++/** This function is called when device has been suspended */ ++typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has received LPM tokens, i.e. ++ * device has been sent to sleep state. */ ++typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has been resumed ++ * from suspend(L2) or L1 sleep state. */ ++typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called whenever hnp params has been changed. ++ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions ++ * to get hnp parameters. */ ++typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called whenever USB RESET is detected. */ ++typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd); ++ ++typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes); ++ ++/** ++ * ++ * @param ep_handle Void pointer to the usb_ep structure ++ * @param ereq_port Pointer to the extended request structure created in the ++ * portable part. ++ */ ++typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, ++ void *ereq_port); ++/** Function Driver Ops Data Structure */ ++struct dwc_otg_pcd_function_ops { ++ dwc_connect_cb_t connect; ++ dwc_disconnect_cb_t disconnect; ++ dwc_setup_cb_t setup; ++ dwc_completion_cb_t complete; ++ dwc_isoc_completion_cb_t isoc_complete; ++ dwc_suspend_cb_t suspend; ++ dwc_sleep_cb_t sleep; ++ dwc_resume_cb_t resume; ++ dwc_reset_cb_t reset; ++ dwc_hnp_params_changed_cb_t hnp_changed; ++ cfi_setup_cb_t cfi_setup; ++#ifdef DWC_UTE_PER_IO ++ xiso_completion_cb_t xisoc_complete; ++#endif ++}; ++/** @} */ ++ ++/** @name Function Driver Functions */ ++/** @{ */ ++ ++/** Call this function to get pointer on dwc_otg_pcd_t, ++ * this pointer will be used for all PCD API functions. ++ * ++ * @param core_if The DWC_OTG Core ++ */ ++extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if); ++ ++/** Frees PCD allocated by dwc_otg_pcd_init ++ * ++ * @param pcd The PCD ++ */ ++extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd); ++ ++/** Call this to bind the function driver to the PCD Core. ++ * ++ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function. ++ * @param fops The Function Driver Ops data structure containing pointers to all callbacks. ++ */ ++extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd, ++ const struct dwc_otg_pcd_function_ops *fops); ++ ++/** Enables an endpoint for use. This function enables an endpoint in ++ * the PCD. The endpoint is described by the ep_desc which has the ++ * same format as a USB ep descriptor. The ep_handle parameter is used to refer ++ * to the endpoint from other API functions and in callbacks. Normally this ++ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the ++ * core for that interface. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. ++ * ++ * @param pcd The PCD ++ * @param ep_desc Endpoint descriptor ++ * @param usb_ep Handle on endpoint, that will be used to identify endpoint. ++ */ ++extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, ++ const uint8_t * ep_desc, void *usb_ep); ++ ++/** Disable the endpoint referenced by ep_handle. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error occurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle); ++ ++/** Queue a data transfer request on the endpoint referenced by ep_handle. ++ * After the transfer is completes, the complete callback will be called with ++ * the request status. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param buf The buffer for the data ++ * @param dma_buf The DMA buffer for the data ++ * @param buflen The length of the data transfer ++ * @param zero Specifies whether to send zero length last packet. ++ * @param req_handle Set this handle to any value to use to reference this ++ * request in the ep_dequeue function or from the complete callback ++ * @param atomic_alloc If driver need to perform atomic allocations ++ * for internal data structures. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, ++ uint32_t buflen, int zero, void *req_handle, ++ int atomic_alloc); ++#ifdef DWC_UTE_PER_IO ++/** ++ * ++ * @param ereq_nonport Pointer to the extended request part of the ++ * usb_request structure defined in usb_gadget.h file. ++ */ ++extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, ++ uint32_t buflen, int zero, ++ void *req_handle, int atomic_alloc, ++ void *ereq_nonport); ++ ++#endif ++ ++/** De-queue the specified data transfer that has not yet completed. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle); ++ ++/** Halt (STALL) an endpoint or clear it. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value); ++ ++/** This function */ ++extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle); ++ ++/** This function should be called on every hardware interrupt */ ++extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd); ++ ++/** This function returns current frame number */ ++extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd); ++ ++/** ++ * Start isochronous transfers on the endpoint referenced by ep_handle. ++ * For isochronous transfers duble buffering is used. ++ * After processing each of buffers comlete callback will be called with ++ * status for each transaction. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param buf0 The virtual address of first data buffer ++ * @param buf1 The virtual address of second data buffer ++ * @param dma0 The DMA address of first data buffer ++ * @param dma1 The DMA address of second data buffer ++ * @param sync_frame Data pattern frame number ++ * @param dp_frame Data size for pattern frame ++ * @param data_per_frame Data size for regular frame ++ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP. ++ * @param buf_proc_intrvl Interval of ISOC Buffer processing ++ * @param req_handle Handle of ISOC request ++ * @param atomic_alloc Specefies whether to perform atomic allocation for ++ * internal data structures. ++ * ++ * Returns -DWC_E_NO_MEMORY if there is no enough memory. ++ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function. ++ * Returns -DW_E_SHUTDOWN for any other error. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf0, uint8_t * buf1, ++ dwc_dma_t dma0, dwc_dma_t dma1, ++ int sync_frame, int dp_frame, ++ int data_per_frame, int start_frame, ++ int buf_proc_intrvl, void *req_handle, ++ int atomic_alloc); ++ ++/** Stop ISOC transfers on endpoint referenced by ep_handle. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param req_handle Handle of ISOC request ++ * ++ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function ++ * Returns 0 on success ++ */ ++int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle); ++ ++/** Get ISOC packet status. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param iso_req_handle Isochronoush request handle ++ * @param packet Number of packet ++ * @param status Out parameter for returning status ++ * @param actual Out parameter for returning actual length ++ * @param offset Out parameter for returning offset ++ * ++ */ ++extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, ++ void *ep_handle, ++ void *iso_req_handle, int packet, ++ int *status, int *actual, ++ int *offset); ++ ++/** Get ISOC packet count. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param iso_req_handle ++ */ ++extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, ++ void *ep_handle, ++ void *iso_req_handle); ++ ++/** This function starts the SRP Protocol if no session is in progress. If ++ * a session is already in progress, but the device is suspended, ++ * remote wakeup signaling is started. ++ */ ++extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd); ++ ++/** This function returns 1 if LPM support is enabled, and 0 otherwise. */ ++extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd); ++ ++/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */ ++extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd); ++ ++/** Initiate SRP */ ++extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd); ++ ++/** Starts remote wakeup signaling. */ ++extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set); ++ ++/** Starts micorsecond soft disconnect. */ ++extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs); ++/** This function returns whether device is dualspeed.*/ ++extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd); ++ ++/** This function returns whether device is otg. */ ++extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd); ++ ++/** These functions allow to get hnp parameters */ ++extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd); ++extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd); ++extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd); ++ ++/** CFI specific Interface functions */ ++/** Allocate a cfi buffer */ ++extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, ++ dwc_dma_t * addr, size_t buflen, ++ int flags); ++ ++/******************************************************************************/ ++ ++/** @} */ ++ ++#endif /* __DWC_PCD_IF_H__ */ ++ ++#endif /* DWC_HOST_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c +@@ -0,0 +1,5147 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $ ++ * $Revision: #116 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++#include "dwc_otg_pcd.h" ++ ++#ifdef DWC_UTE_CFI ++#include "dwc_otg_cfi.h" ++#endif ++ ++#ifdef DWC_UTE_PER_IO ++extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep); ++#endif ++//#define PRINT_CFI_DMA_DESCS ++ ++#define DEBUG_EP0 ++ ++/** ++ * This function updates OTG. ++ */ ++static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset) ++{ ++ ++ if (reset) { ++ pcd->b_hnp_enable = 0; ++ pcd->a_hnp_support = 0; ++ pcd->a_alt_hnp_support = 0; ++ } ++ ++ if (pcd->fops->hnp_changed) { ++ pcd->fops->hnp_changed(pcd); ++ } ++} ++ ++/** @file ++ * This file contains the implementation of the PCD Interrupt handlers. ++ * ++ * The PCD handles the device interrupts. Many conditions can cause a ++ * device interrupt. When an interrupt occurs, the device interrupt ++ * service routine determines the cause of the interrupt and ++ * dispatches handling to the appropriate function. These interrupt ++ * handling functions are described below. ++ * All interrupt registers are processed from LSB to MSB. ++ */ ++ ++/** ++ * This function prints the ep0 state for debug purposes. ++ */ ++static inline void print_ep0_state(dwc_otg_pcd_t * pcd) ++{ ++#ifdef DEBUG ++ char str[40]; ++ ++ switch (pcd->ep0state) { ++ case EP0_DISCONNECT: ++ dwc_strcpy(str, "EP0_DISCONNECT"); ++ break; ++ case EP0_IDLE: ++ dwc_strcpy(str, "EP0_IDLE"); ++ break; ++ case EP0_IN_DATA_PHASE: ++ dwc_strcpy(str, "EP0_IN_DATA_PHASE"); ++ break; ++ case EP0_OUT_DATA_PHASE: ++ dwc_strcpy(str, "EP0_OUT_DATA_PHASE"); ++ break; ++ case EP0_IN_STATUS_PHASE: ++ dwc_strcpy(str, "EP0_IN_STATUS_PHASE"); ++ break; ++ case EP0_OUT_STATUS_PHASE: ++ dwc_strcpy(str, "EP0_OUT_STATUS_PHASE"); ++ break; ++ case EP0_STALL: ++ dwc_strcpy(str, "EP0_STALL"); ++ break; ++ default: ++ dwc_strcpy(str, "EP0_INVALID"); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state); ++#endif ++} ++ ++/** ++ * This function calculate the size of the payload in the memory ++ * for out endpoints and prints size for debug purposes(used in ++ * 2.93a DevOutNak feature). ++ */ ++static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep) ++{ ++#ifdef DEBUG ++ deptsiz_data_t deptsiz_init = {.d32 = 0 }; ++ deptsiz_data_t deptsiz_updt = {.d32 = 0 }; ++ int pack_num; ++ unsigned payload; ++ ++ deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num]; ++ deptsiz_updt.d32 = ++ DWC_READ_REG32(&pcd->core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz); ++ /* Payload will be */ ++ payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize; ++ /* Packet count is decremented every time a packet ++ * is written to the RxFIFO not in to the external memory ++ * So, if payload == 0, then it means no packet was sent to ext memory*/ ++ pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Payload for EP%d-%s\n", ++ ep->num, (ep->is_in ? "IN" : "OUT")); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Number of transfered bytes = 0x%08x\n", payload); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Number of transfered packets = %d\n", pack_num); ++#endif ++} ++ ++ ++#ifdef DWC_UTE_CFI ++static inline void print_desc(struct dwc_otg_dma_desc *ddesc, ++ const uint8_t * epname, int descnum) ++{ ++ CFI_INFO ++ ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n", ++ epname, descnum, ddesc->buf, ddesc->status.b.bytes, ++ ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts, ++ ddesc->status.b.bs); ++} ++#endif ++ ++/** ++ * This function returns pointer to in ep struct with number ep_num ++ */ ++static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num) ++{ ++ int i; ++ int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; ++ if (ep_num == 0) { ++ return &pcd->ep0; ++ } else { ++ for (i = 0; i < num_in_eps; ++i) { ++ if (pcd->in_ep[i].dwc_ep.num == ep_num) ++ return &pcd->in_ep[i]; ++ } ++ return 0; ++ } ++} ++ ++/** ++ * This function returns pointer to out ep struct with number ep_num ++ */ ++static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num) ++{ ++ int i; ++ int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; ++ if (ep_num == 0) { ++ return &pcd->ep0; ++ } else { ++ for (i = 0; i < num_out_eps; ++i) { ++ if (pcd->out_ep[i].dwc_ep.num == ep_num) ++ return &pcd->out_ep[i]; ++ } ++ return 0; ++ } ++} ++ ++/** ++ * This functions gets a pointer to an EP from the wIndex address ++ * value of the control request. ++ */ ++dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ uint32_t ep_num = UE_GET_ADDR(wIndex); ++ ++ if (ep_num == 0) { ++ ep = &pcd->ep0; ++ } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */ ++ ep = &pcd->in_ep[ep_num - 1]; ++ } else { ++ ep = &pcd->out_ep[ep_num - 1]; ++ } ++ ++ return ep; ++} ++ ++/** ++ * This function checks the EP request queue, if the queue is not ++ * empty the next request is started. ++ */ ++void start_next_request(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req = 0; ++ uint32_t max_transfer = ++ GET_CORE_IF(ep->pcd)->core_params->max_transfer_size; ++ ++#ifdef DWC_UTE_CFI ++ struct dwc_otg_pcd *pcd; ++ pcd = ep->pcd; ++#endif ++ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ ep->dwc_ep.cfi_req_len = req->length; ++ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req); ++ } else { ++#endif ++ /* Setup and start the Transfer */ ++ if (req->dw_align_buf) { ++ ep->dwc_ep.dma_addr = req->dw_align_buf_dma; ++ ep->dwc_ep.start_xfer_buff = req->dw_align_buf; ++ ep->dwc_ep.xfer_buff = req->dw_align_buf; ++ } else { ++ ep->dwc_ep.dma_addr = req->dma; ++ ep->dwc_ep.start_xfer_buff = req->buf; ++ ep->dwc_ep.xfer_buff = req->buf; ++ } ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = req->length; ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ++ ep->dwc_ep.maxxfer = max_transfer; ++ if (GET_CORE_IF(ep->pcd)->dma_desc_enable) { ++ uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE ++ - (DDMA_MAX_TRANSFER_SIZE % 4); ++ if (ep->dwc_ep.is_in) { ++ if (ep->dwc_ep.maxxfer > ++ DDMA_MAX_TRANSFER_SIZE) { ++ ep->dwc_ep.maxxfer = ++ DDMA_MAX_TRANSFER_SIZE; ++ } ++ } else { ++ if (ep->dwc_ep.maxxfer > out_max_xfer) { ++ ep->dwc_ep.maxxfer = ++ out_max_xfer; ++ } ++ } ++ } ++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { ++ ep->dwc_ep.maxxfer -= ++ (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket); ++ } ++ if (req->sent_zlp) { ++ if ((ep->dwc_ep.total_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.total_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep); ++ } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ DWC_PRINTF("There are no more ISOC requests \n"); ++ ep->dwc_ep.frame_num = 0xFFFFFFFF; ++ } ++} ++ ++/** ++ * This function handles the SOF Interrupts. At this time the SOF ++ * Interrupt is disabled. ++ */ ++int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_PCD, "SOF\n"); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.sofintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function handles the Rx Status Queue Level Interrupt, which ++ * indicates that there is a least one packet in the Rx FIFO. The ++ * packets are moved from the FIFO to memory, where they will be ++ * processed when the Endpoint Interrupt Register indicates Transfer ++ * Complete or SETUP Phase Done. ++ * ++ * Repeat the following until the Rx Status Queue is empty: ++ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet ++ * info ++ * -# If Receive FIFO is empty then skip to step Clear the interrupt ++ * and exit ++ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the ++ * SETUP data to the buffer ++ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data ++ * to the destination buffer ++ */ ++int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t gintmask = {.d32 = 0 }; ++ device_grxsts_data_t status; ++ dwc_otg_pcd_ep_t *ep; ++ gintsts_data_t gintsts; ++#ifdef DEBUG ++ static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" }; ++#endif ++ ++ //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); ++ /* Disable the Rx Status Queue Level interrupt */ ++ gintmask.b.rxstsqlvl = 1; ++ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0); ++ ++ /* Get the Status from the top of the FIFO */ ++ status.d32 = DWC_READ_REG32(&global_regs->grxstsp); ++ ++ DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s " ++ "pktsts:%x Frame:%d(0x%0x)\n", ++ status.b.epnum, status.b.bcnt, ++ dpid_str[status.b.dpid], ++ status.b.pktsts, status.b.fn, status.b.fn); ++ /* Get pointer to EP structure */ ++ ep = get_out_ep(pcd, status.b.epnum); ++ ++ switch (status.b.pktsts) { ++ case DWC_DSTS_GOUT_NAK: ++ DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n"); ++ break; ++ case DWC_STS_DATA_UPDT: ++ DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n"); ++ if (status.b.bcnt && ep->dwc_ep.xfer_buff) { ++ /** @todo NGS Check for buffer overflow? */ ++ dwc_otg_read_packet(core_if, ++ ep->dwc_ep.xfer_buff, ++ status.b.bcnt); ++ ep->dwc_ep.xfer_count += status.b.bcnt; ++ ep->dwc_ep.xfer_buff += status.b.bcnt; ++ } ++ break; ++ case DWC_STS_XFER_COMP: ++ DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n"); ++ break; ++ case DWC_DSTS_SETUP_COMP: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n"); ++#endif ++ break; ++ case DWC_DSTS_SETUP_UPDT: ++ dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32); ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, ++ "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n", ++ pcd->setup_pkt->req.bmRequestType, ++ pcd->setup_pkt->req.bRequest, ++ UGETW(pcd->setup_pkt->req.wValue), ++ UGETW(pcd->setup_pkt->req.wIndex), ++ UGETW(pcd->setup_pkt->req.wLength)); ++#endif ++ ep->dwc_ep.xfer_count += status.b.bcnt; ++ break; ++ default: ++ DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n", ++ status.b.pktsts); ++ break; ++ } ++ ++ /* Enable the Rx Status Queue Level interrupt */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32); ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); ++ return 1; ++} ++ ++/** ++ * This function examines the Device IN Token Learning Queue to ++ * determine the EP number of the last IN token received. This ++ * implementation is for the Mass Storage device where there are only ++ * 2 IN EPs (Control-IN and BULK-IN). ++ * ++ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there ++ * are 8 EP Numbers in each of the other possible DTKNQ Registers. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * ++ */ ++static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_device_global_regs_t *dev_global_regs = ++ core_if->dev_if->dev_global_regs; ++ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; ++ /* Number of Token Queue Registers */ ++ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; ++ dtknq1_data_t dtknqr1; ++ uint32_t in_tkn_epnums[4]; ++ int ndx = 0; ++ int i = 0; ++ volatile uint32_t *addr = &dev_global_regs->dtknqr1; ++ int epnum = 0; ++ ++ //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); ++ ++ /* Read the DTKNQ Registers */ ++ for (i = 0; i < DTKNQ_REG_CNT; i++) { ++ in_tkn_epnums[i] = DWC_READ_REG32(addr); ++ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, ++ in_tkn_epnums[i]); ++ if (addr == &dev_global_regs->dvbusdis) { ++ addr = &dev_global_regs->dtknqr3_dthrctl; ++ } else { ++ ++addr; ++ } ++ ++ } ++ ++ /* Copy the DTKNQR1 data to the bit field. */ ++ dtknqr1.d32 = in_tkn_epnums[0]; ++ /* Get the EP numbers */ ++ in_tkn_epnums[0] = dtknqr1.b.epnums0_5; ++ ndx = dtknqr1.b.intknwptr - 1; ++ ++ //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx); ++ if (ndx == -1) { ++ /** @todo Find a simpler way to calculate the max ++ * queue position.*/ ++ int cnt = TOKEN_Q_DEPTH; ++ if (TOKEN_Q_DEPTH <= 6) { ++ cnt = TOKEN_Q_DEPTH - 1; ++ } else if (TOKEN_Q_DEPTH <= 14) { ++ cnt = TOKEN_Q_DEPTH - 7; ++ } else if (TOKEN_Q_DEPTH <= 22) { ++ cnt = TOKEN_Q_DEPTH - 15; ++ } else { ++ cnt = TOKEN_Q_DEPTH - 23; ++ } ++ epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF; ++ } else { ++ if (ndx <= 5) { ++ epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 13) { ++ ndx -= 6; ++ epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 21) { ++ ndx -= 14; ++ epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 29) { ++ ndx -= 22; ++ epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF; ++ } ++ } ++ //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum); ++ return epnum; ++} ++ ++/** ++ * This interrupt occurs when the non-periodic Tx FIFO is half-empty. ++ * The active request is checked for the next packet to be loaded into ++ * the non-periodic Tx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ gnptxsts_data_t txstatus = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ int epnum = 0; ++ dwc_otg_pcd_ep_t *ep = 0; ++ uint32_t len = 0; ++ int dwords; ++ ++ /* Get the epnum from the IN Token Learning Queue. */ ++ epnum = get_ep_of_last_in_token(core_if); ++ ep = get_in_ep(pcd, epnum); ++ ++ DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32); ++ ++ while (txstatus.b.nptxqspcavail > 0 && ++ txstatus.b.nptxfspcavail > dwords && ++ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxsts)); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.nptxfempty = 1; ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function is called when dedicated Tx FIFO Empty interrupt occurs. ++ * The active request is checked for the next packet to be loaded into ++ * apropriate Tx FIFO. ++ */ ++static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep = 0; ++ uint32_t len = 0; ++ int dwords; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len && ++ ep->dwc_ep.xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, ++ txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts)); ++ ++ return 1; ++} ++ ++/** ++ * This function is called when the Device is disconnected. It stops ++ * any active requests and informs the Gadget driver of the ++ * disconnect. ++ */ ++void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd) ++{ ++ int i, num_in_eps, num_out_eps; ++ dwc_otg_pcd_ep_t *ep; ++ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_SPINLOCK(pcd->lock); ++ ++ num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; ++ num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__); ++ /* don't disconnect drivers more than once */ ++ if (pcd->ep0state == EP0_DISCONNECT) { ++ DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__); ++ DWC_SPINUNLOCK(pcd->lock); ++ return; ++ } ++ pcd->ep0state = EP0_DISCONNECT; ++ ++ /* Reset the OTG state. */ ++ dwc_otg_pcd_update_otg(pcd, 1); ++ ++ /* Disable the NP Tx Fifo Empty Interrupt. */ ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Flush the FIFOs */ ++ /**@todo NGS Flush Periodic FIFOs */ ++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10); ++ dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd)); ++ ++ /* prevent new request submissions, kill any outstanding requests */ ++ ep = &pcd->ep0; ++ dwc_otg_request_nuke(ep); ++ /* prevent new request submissions, kill any outstanding requests */ ++ for (i = 0; i < num_in_eps; i++) { ++ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i]; ++ dwc_otg_request_nuke(ep); ++ } ++ /* prevent new request submissions, kill any outstanding requests */ ++ for (i = 0; i < num_out_eps; i++) { ++ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i]; ++ dwc_otg_request_nuke(ep); ++ } ++ ++ /* report disconnect; the driver is already quiesced */ ++ if (pcd->fops->disconnect) { ++ DWC_SPINUNLOCK(pcd->lock); ++ pcd->fops->disconnect(pcd); ++ DWC_SPINLOCK(pcd->lock); ++ } ++ DWC_SPINUNLOCK(pcd->lock); ++} ++ ++/** ++ * This interrupt indicates that ... ++ */ ++int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr"); ++ intr_mask.b.i2cintr = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.i2cintr = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that ... ++ */ ++int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++#if defined(VERBOSE) ++ DWC_PRINTF("Early Suspend Detected\n"); ++#endif ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.erlysuspend = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This function configures EPO to receive SETUP packets. ++ * ++ * @todo NGS: Update the comments from the HW FS. ++ * ++ * -# Program the following fields in the endpoint specific registers ++ * for Control OUT EP 0, in order to receive a setup packet ++ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back ++ * setup packets) ++ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back ++ * to back setup packets) ++ * - In DMA mode, DOEPDMA0 Register with a memory address to ++ * store any setup packets received ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param pcd Programming view of the PCD. ++ */ ++static inline void ep0_out_start(dwc_otg_core_if_t * core_if, ++ dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ depctl_data_t doepctl = {.d32 = 0 }; ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__, ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); ++#endif ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl); ++ if (doepctl.b.epena) { ++ return; ++ } ++ } ++ ++ doeptsize0.b.supcnt = 3; ++ doeptsize0.b.pktcnt = 1; ++ doeptsize0.b.xfersize = 8 * 3; ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ /** put here as for Hermes mode deptisz register should not be written */ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz, ++ doeptsize0.d32); ++ ++ /** @todo dma needs to handle multiple setup packets (up to 3) */ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, ++ pcd->setup_pkt_dma_handle); ++ } else { ++ dev_if->setup_desc_index = ++ (dev_if->setup_desc_index + 1) & 1; ++ dma_desc = ++ dev_if->setup_desc_addr[dev_if->setup_desc_index]; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ dma_desc->status.b.sr = 0; ++ dma_desc->status.b.mtrf = 0; ++ } ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket; ++ dma_desc->buf = pcd->setup_pkt_dma_handle; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, ++ dev_if->dma_setup_desc_addr ++ [dev_if->setup_desc_index]); ++ } ++ ++ } else { ++ /** put here as for Hermes mode deptisz register should not be written */ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz, ++ doeptsize0.d32); ++ } ++ ++ /** DOEPCTL0 Register write cnak will be set after setup interrupt */ ++ doepctl.d32 = 0; ++ doepctl.b.epena = 1; ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ doepctl.b.cnak = 1; ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ } else { ++ DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32); ++ } ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", ++ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl)); ++#endif ++} ++ ++/** ++ * This interrupt occurs when a USB Reset is detected. When the USB ++ * Reset Interrupt occurs the device state is set to DEFAULT and the ++ * EP0 state is set to IDLE. ++ * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1) ++ * -# Unmask the following interrupt bits ++ * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint) ++ * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint) ++ * - DOEPMSK.SETUP = 1 ++ * - DOEPMSK.XferCompl = 1 ++ * - DIEPMSK.XferCompl = 1 ++ * - DIEPMSK.TimeOut = 1 ++ * -# Program the following fields in the endpoint specific registers ++ * for Control OUT EP 0, in order to receive a setup packet ++ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back ++ * setup packets) ++ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back ++ * to back setup packets) ++ * - In DMA mode, DOEPDMA0 Register with a memory address to ++ * store any setup packets received ++ * At this point, all the required initialization, except for enabling ++ * the control 0 OUT endpoint is done, for receiving SETUP packets. ++ */ ++int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ depctl_data_t doepctl = {.d32 = 0 }; ++ depctl_data_t diepctl = {.d32 = 0 }; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ grstctl_t resetctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ int i = 0; ++ gintsts_data_t gintsts; ++ pcgcctl_data_t power = {.d32 = 0 }; ++ ++ power.d32 = DWC_READ_REG32(core_if->pcgcctl); ++ if (power.b.stoppclk) { ++ power.d32 = 0; ++ power.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); ++ ++ power.b.pwrclmp = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); ++ ++ power.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); ++ } ++ ++ core_if->lx_state = DWC_OTG_L0; ++ ++ DWC_PRINTF("USB RESET\n"); ++#ifdef DWC_EN_ISOC ++ for (i = 1; i < 16; ++i) { ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ep = get_in_ep(pcd, i); ++ if (ep != 0) { ++ dwc_ep = &ep->dwc_ep; ++ dwc_ep->next_frame = 0xffffffff; ++ } ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ /* reset the HNP settings */ ++ dwc_otg_pcd_update_otg(pcd, 1); ++ ++ /* Clear the Remote Wakeup Signalling */ ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ ++ /* Set NAK for all OUT EPs */ ++ doepctl.b.snak = 1; ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); ++ } ++ ++ /* Flush the NP Tx FIFO */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); ++ /* Flush the Learning Queue */ ++ resetctl.b.intknqflsh = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 0; ++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { ++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active ++ } ++ core_if->nextep_seq[0] = 0; ++ core_if->first_in_nextep_seq = 0; ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ diepctl.b.nextep = 0; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt = 2; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); ++ } ++ } ++ ++ if (core_if->multiproc_int_enable) { ++ daintmsk.b.inep0 = 1; ++ daintmsk.b.outep0 = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, ++ daintmsk.d32); ++ ++ doepmsk.b.setup = 1; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= OTG_CORE_REV_3_00a)) { ++ doepmsk.b.stsphsercvd = 1; ++ } ++ if (core_if->dma_desc_enable) ++ doepmsk.b.bna = 1; ++/* ++ doepmsk.b.babble = 1; ++ doepmsk.b.nyet = 1; ++ ++ if (core_if->dma_enable) { ++ doepmsk.b.nak = 1; ++ } ++*/ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0], ++ doepmsk.d32); ++ ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ diepmsk.b.intknepmis = 1; ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; ++ ++/* if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++*/ ++/* ++ if (core_if->dma_enable) { ++ diepmsk.b.nak = 1; ++ } ++*/ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0], ++ diepmsk.d32); ++ } else { ++ daintmsk.b.inep0 = 1; ++ daintmsk.b.outep0 = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, ++ daintmsk.d32); ++ ++ doepmsk.b.setup = 1; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= OTG_CORE_REV_3_00a)) { ++ doepmsk.b.stsphsercvd = 1; ++ } ++ if (core_if->dma_desc_enable) ++ doepmsk.b.bna = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); ++ ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; ++/* ++ if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++*/ ++ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32); ++ } ++ ++ /* Reset Device Address */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.devaddr = 0; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* setup EP0 to receive SETUP packets */ ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) ++ ep0_out_start(core_if, pcd); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.usbreset = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * Get the device speed from the device status register and convert it ++ * to USB speed constant. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static int get_device_speed(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ int speed = 0; ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ switch (dsts.b.enumspd) { ++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: ++ speed = USB_SPEED_HIGH; ++ break; ++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: ++ speed = USB_SPEED_FULL; ++ break; ++ ++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: ++ speed = USB_SPEED_LOW; ++ break; ++ } ++ ++ return speed; ++} ++ ++/** ++ * Read the device status register and set the device speed in the ++ * data structure. ++ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. ++ */ ++int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ gintsts_data_t gintsts; ++ gusbcfg_data_t gusbcfg; ++ dwc_otg_core_global_regs_t *global_regs = ++ GET_CORE_IF(pcd)->core_global_regs; ++ uint8_t utmi16b, utmi8b; ++ int speed; ++ DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n"); ++ ++ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) { ++ utmi16b = 6; //vahrama old value was 6; ++ utmi8b = 9; ++ } else { ++ utmi16b = 4; ++ utmi8b = 8; ++ } ++ dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) { ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++ } ++ ++#ifdef DEBUG_EP0 ++ print_ep0_state(pcd); ++#endif ++ ++ if (pcd->ep0state == EP0_DISCONNECT) { ++ pcd->ep0state = EP0_IDLE; ++ } else if (pcd->ep0state == EP0_STALL) { ++ pcd->ep0state = EP0_IDLE; ++ } ++ ++ pcd->ep0state = EP0_IDLE; ++ ++ ep0->stopped = 0; ++ ++ speed = get_device_speed(GET_CORE_IF(pcd)); ++ pcd->fops->connect(pcd, speed); ++ ++ /* Set USB turnaround time based on device speed and PHY interface. */ ++ gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ if (speed == USB_SPEED_HIGH) { ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_ULPI) { ++ /* ULPI interface */ ++ gusbcfg.b.usbtrdtim = 9; ++ } ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_UTMI) { ++ /* UTMI+ interface */ ++ if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } else if (GET_CORE_IF(pcd)->hwcfg4. ++ b.utmi_phy_data_width == 1) { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } else if (GET_CORE_IF(pcd)-> ++ core_params->phy_utmi_width == 8) { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } else { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } ++ } ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) { ++ /* UTMI+ OR ULPI interface */ ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ gusbcfg.b.usbtrdtim = 9; ++ } else { ++ /* UTMI+ interface */ ++ if (GET_CORE_IF(pcd)-> ++ core_params->phy_utmi_width == 16) { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } else { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } ++ } ++ } ++ } else { ++ /* Full or low speed */ ++ gusbcfg.b.usbtrdtim = 9; ++ } ++ DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.enumdone = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the ISO OUT Packet was dropped due to ++ * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs ++ * read all the data from the Rx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ DWC_WARN("INTERRUPT Handler not implemented for %s\n", ++ "ISOC Out Dropped"); ++ ++ intr_mask.b.isooutdrop = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.isooutdrop = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates the end of the portion of the micro-frame ++ * for periodic transactions. If there is a periodic transaction for ++ * the next frame, load the packets into the EP periodic Tx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP"); ++ ++ intr_mask.b.eopframe = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.eopframe = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that EP of the packet on the top of the ++ * non-periodic Tx FIFO does not match EP of the IN Token received. ++ * ++ * The "Device IN Token Queue" Registers are read to determine the ++ * order the IN Tokens have been received. The non-periodic Tx FIFO ++ * is flushed, so it can be reloaded in the order seen in the IN Token ++ * Queue. ++ */ ++int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dctl_data_t dctl; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 1; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); ++ ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (!gintsts.b.ginnakeff) { ++ /* Disable EP Mismatch interrupt */ ++ intr_mask.d32 = 0; ++ intr_mask.b.epmismatch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0); ++ /* Enable the Global IN NAK Effective Interrupt */ ++ intr_mask.d32 = 0; ++ intr_mask.b.ginnakeff = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); ++ /* Set the global non-periodic IN NAK handshake */ ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ dctl.b.sgnpinnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ } else { ++ DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n"); ++ } ++ /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective() ++ * handler after Global IN NAK Effective interrupt will be asserted */ ++ } ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.epmismatch = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt is valid only in DMA mode. This interrupt indicates that the ++ * core has stopped fetching data for IN endpoints due to the unavailability of ++ * TxFIFO space or Request Queue space. This interrupt is used by the ++ * application for an endpoint mismatch algorithm. ++ * ++ * @param pcd The PCD ++ */ ++int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk_data; ++ dctl_data_t dctl; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); ++ ++ /* Clear the global non-periodic IN NAK handshake */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ /* Mask GINTSTS.FETSUSP interrupt */ ++ gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ gintmsk_data.b.fetsusp = 0; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.fetsusp = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++/** ++ * This funcion stalls EP0. ++ */ ++static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ usb_device_request_t *ctrl = &pcd->setup_pkt->req; ++ DWC_WARN("req %02x.%02x protocol STALL; err %d\n", ++ ctrl->bmRequestType, ctrl->bRequest, err_val); ++ ++ ep0->dwc_ep.is_in = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ pcd->ep0.stopped = 1; ++ pcd->ep0state = EP0_IDLE; ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++} ++ ++/** ++ * This functions delegates the setup command to the gadget driver. ++ */ ++static inline void do_gadget_setup(dwc_otg_pcd_t * pcd, ++ usb_device_request_t * ctrl) ++{ ++ int ret = 0; ++ DWC_SPINUNLOCK(pcd->lock); ++ ret = pcd->fops->setup(pcd, (uint8_t *) ctrl); ++ DWC_SPINLOCK(pcd->lock); ++ if (ret < 0) { ++ ep0_do_stall(pcd, ret); ++ } ++ ++ /** @todo This is a g_file_storage gadget driver specific ++ * workaround: a DELAYED_STATUS result from the fsg_setup ++ * routine will result in the gadget queueing a EP0 IN status ++ * phase for a two-stage control transfer. Exactly the same as ++ * a SET_CONFIGURATION/SET_INTERFACE except that this is a class ++ * specific request. Need a generic way to know when the gadget ++ * driver will queue the status phase. Can we assume when we ++ * call the gadget driver setup() function that it will always ++ * queue and require the following flag? Need to look into ++ * this. ++ */ ++ ++ if (ret == 256 + 999) { ++ pcd->request_config = 1; ++ } ++} ++ ++#ifdef DWC_UTE_CFI ++/** ++ * This functions delegates the CFI setup commands to the gadget driver. ++ * This function will return a negative value to indicate a failure. ++ */ ++static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req) ++{ ++ int ret = 0; ++ ++ if (pcd->fops && pcd->fops->cfi_setup) { ++ DWC_SPINUNLOCK(pcd->lock); ++ ret = pcd->fops->cfi_setup(pcd, ctrl_req); ++ DWC_SPINLOCK(pcd->lock); ++ if (ret < 0) { ++ ep0_do_stall(pcd, ret); ++ return ret; ++ } ++ } ++ ++ return ret; ++} ++#endif ++ ++/** ++ * This function starts the Zero-Length Packet for the IN status phase ++ * of a 2 stage control transfer. ++ */ ++static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ if (pcd->ep0state == EP0_STALL) { ++ return; ++ } ++ ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ ++ /* Prepare for more SETUP Packets */ ++ DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n"); ++ if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) ++ && (pcd->core_if->dma_desc_enable) ++ && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "Data terminated wait next packet in out_desc_addr\n"); ++ pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr); ++ pcd->data_terminated = 1; ++ } ++ ep0->dwc_ep.xfer_len = 0; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.is_in = 1; ++ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ ++ /* Prepare for more SETUP Packets */ ++ //ep0_out_start(GET_CORE_IF(pcd), pcd); ++} ++ ++/** ++ * This function starts the Zero-Length Packet for the OUT status phase ++ * of a 2 stage control transfer. ++ */ ++static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ if (pcd->ep0state == EP0_STALL) { ++ DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n"); ++ return; ++ } ++ pcd->ep0state = EP0_OUT_STATUS_PHASE; ++ ++ DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n"); ++ ep0->dwc_ep.xfer_len = 0; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.is_in = 0; ++ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ ++ /* Prepare for more SETUP Packets */ ++ if (GET_CORE_IF(pcd)->dma_enable == 0) { ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++ } ++} ++ ++/** ++ * Clear the EP halt (STALL) and if pending requests start the ++ * transfer. ++ */ ++static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep) ++{ ++ if (ep->dwc_ep.stall_clear_flag == 0) ++ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ ++ /* Reactive the EP */ ++ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ if (ep->stopped) { ++ ep->stopped = 0; ++ /* If there is a request in the EP queue start it */ ++ ++ /** @todo FIXME: this causes an EP mismatch in DMA mode. ++ * epmismatch not yet implemented. */ ++ ++ /* ++ * Above fixme is solved by implmenting a tasklet to call the ++ * start_next_request(), outside of interrupt context at some ++ * time after the current time, after a clear-halt setup packet. ++ * Still need to implement ep mismatch in the future if a gadget ++ * ever uses more than one endpoint at once ++ */ ++ ep->queue_sof = 1; ++ DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet); ++ } ++ /* Start Control Status Phase */ ++ do_setup_in_status_phase(pcd); ++} ++ ++/** ++ * This function is called when the SET_FEATURE TEST_MODE Setup packet ++ * is sent from the host. The Device Control register is written with ++ * the Test Mode bits set to the specified Test Mode. This is done as ++ * a tasklet so that the "Status" phase of the control transfer ++ * completes before transmitting the TEST packets. ++ * ++ * @todo This has not been tested since the tasklet struct was put ++ * into the PCD struct! ++ * ++ */ ++void do_test_mode(void *data) ++{ ++ dctl_data_t dctl; ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ int test_mode = pcd->test_mode; ++ ++// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); ++ ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ switch (test_mode) { ++ case 1: // TEST_J ++ dctl.b.tstctl = 1; ++ break; ++ ++ case 2: // TEST_K ++ dctl.b.tstctl = 2; ++ break; ++ ++ case 3: // TEST_SE0_NAK ++ dctl.b.tstctl = 3; ++ break; ++ ++ case 4: // TEST_PACKET ++ dctl.b.tstctl = 4; ++ break; ++ ++ case 5: // TEST_FORCE_ENABLE ++ dctl.b.tstctl = 5; ++ break; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++} ++ ++/** ++ * This function process the GET_STATUS Setup Commands. ++ */ ++static inline void do_get_status(dwc_otg_pcd_t * pcd) ++{ ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ uint16_t *status = pcd->status_buf; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, ++ "GET_STATUS %02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++#endif ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */ ++ DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex)); ++ DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver); ++ DWC_PRINTF("OTG CAP - %d, %d\n", ++ core_if->core_params->otg_cap, ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); ++ if (core_if->otg_ver == 1 ++ && core_if->core_params->otg_cap == ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ uint8_t *otgsts = (uint8_t*)pcd->status_buf; ++ *otgsts = (core_if->otg_sts & 0x1); ++ pcd->ep0_pending = 1; ++ ep0->dwc_ep.start_xfer_buff = ++ (uint8_t *) otgsts; ++ ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts; ++ ep0->dwc_ep.dma_addr = ++ pcd->status_buf_dma_handle; ++ ep0->dwc_ep.xfer_len = 1; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ return; ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ } else { ++ *status = 0x1; /* Self powered */ ++ *status |= pcd->remote_wakeup_enable << 1; ++ break; ++ } ++ case UT_INTERFACE: ++ *status = 0; ++ break; ++ ++ case UT_ENDPOINT: ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0 || UGETW(ctrl.wLength) > 2) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ /** @todo check for EP stall */ ++ *status = ep->stopped; ++ break; ++ } ++ pcd->ep0_pending = 1; ++ ep0->dwc_ep.start_xfer_buff = (uint8_t *) status; ++ ep0->dwc_ep.xfer_buff = (uint8_t *) status; ++ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle; ++ ep0->dwc_ep.xfer_len = 2; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++} ++ ++/** ++ * This function process the SET_FEATURE Setup Commands. ++ */ ++static inline void do_set_feature(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep = 0; ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++ DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param); ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ switch (UGETW(ctrl.wValue)) { ++ case UF_DEVICE_REMOTE_WAKEUP: ++ pcd->remote_wakeup_enable = 1; ++ break; ++ ++ case UF_TEST_MODE: ++ /* Setup the Test Mode tasklet to do the Test ++ * Packet generation after the SETUP Status ++ * phase has completed. */ ++ ++ /** @todo This has not been tested since the ++ * tasklet struct was put into the PCD ++ * struct! */ ++ pcd->test_mode = UGETW(ctrl.wIndex) >> 8; ++ DWC_TASK_SCHEDULE(pcd->test_mode_tasklet); ++ break; ++ ++ case UF_DEVICE_B_HNP_ENABLE: ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); ++ ++ /* dev may initiate HNP */ ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->b_hnp_enable = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ DWC_DEBUGPL(DBG_PCD, "Request B HNP\n"); ++ /**@todo Is the gotgctl.devhnpen cleared ++ * by a USB Reset? */ ++ gotgctl.b.devhnpen = 1; ++ gotgctl.b.hnpreq = 1; ++ DWC_WRITE_REG32(&global_regs->gotgctl, ++ gotgctl.d32); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ ++ case UF_DEVICE_A_HNP_SUPPORT: ++ /* RH port supports HNP */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n"); ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->a_hnp_support = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ ++ case UF_DEVICE_A_ALT_HNP_SUPPORT: ++ /* other RH port does */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->a_alt_hnp_support = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ ++ default: ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ ++ case UT_INTERFACE: ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ case UT_ENDPOINT: ++ if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) { ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(core_if, &ep->dwc_ep); ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ } ++} ++ ++/** ++ * This function process the CLEAR_FEATURE Setup Commands. ++ */ ++static inline void do_clear_feature(dwc_otg_pcd_t * pcd) ++{ ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, ++ "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ switch (UGETW(ctrl.wValue)) { ++ case UF_DEVICE_REMOTE_WAKEUP: ++ pcd->remote_wakeup_enable = 0; ++ break; ++ ++ case UF_TEST_MODE: ++ /** @todo Add CLEAR_FEATURE for TEST modes. */ ++ break; ++ ++ default: ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ ++ case UT_ENDPOINT: ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ ++ pcd_clear_halt(pcd, ep); ++ ++ break; ++ } ++} ++ ++/** ++ * This function process the SET_ADDRESS Setup Commands. ++ */ ++static inline void do_set_address(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ ++ if (ctrl.bmRequestType == UT_DEVICE) { ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ ++#ifdef DEBUG_EP0 ++// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); ++#endif ++ dcfg.b.devaddr = UGETW(ctrl.wValue); ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32); ++ do_setup_in_status_phase(pcd); ++ } ++} ++ ++/** ++ * This function processes SETUP commands. In Linux, the USB Command ++ * processing is done in two places - the first being the PCD and the ++ * second in the Gadget Driver (for example, the File-Backed Storage ++ * Gadget Driver). ++ * ++ *
Parameter NameMeaning
otg_capSpecifies the OTG capabilities. The driver will automatically detect the ++ value for this parameter if none is specified. ++ - 0: HNP and SRP capable (default, if available) ++ - 1: SRP Only capable ++ - 2: No HNP/SRP capable ++
dma_enableSpecifies whether to use slave or DMA mode for accessing the data FIFOs. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Slave ++ - 1: DMA (default, if available) ++
dma_burst_sizeThe DMA Burst size (applicable only for External DMA Mode). ++ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++
speedSpecifies the maximum speed of operation in host and device mode. The ++ actual speed depends on the speed of the attached device and the value of ++ phy_type. ++ - 0: High Speed (default) ++ - 1: Full Speed ++
host_support_fs_ls_low_powerSpecifies whether low power mode is supported when attached to a Full ++ Speed or Low Speed device in host mode. ++ - 0: Don't support low power mode (default) ++ - 1: Support low power mode ++
host_ls_low_power_phy_clkSpecifies the PHY clock rate in low power mode when connected to a Low ++ Speed device in host mode. This parameter is applicable only if ++ HOST_SUPPORT_FS_LS_LOW_POWER is enabled. ++ - 0: 48 MHz (default) ++ - 1: 6 MHz ++
enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software. ++ - 0: Use cC FIFO size parameters ++ - 1: Allow dynamic FIFO sizing (default) ++
data_fifo_sizeTotal number of 4-byte words in the data FIFO memory. This memory ++ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. ++ - Values: 32 to 32768 (default 8192) ++ ++ Note: The total FIFO memory depth in the FPGA configuration is 8192. ++
dev_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in device mode when dynamic ++ FIFO sizing is enabled. ++ - Values: 16 to 32768 (default 1064) ++
dev_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in device mode when ++ dynamic FIFO sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
dev_perio_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the periodic Tx FIFOs in device mode ++ when dynamic FIFO sizing is enabled. ++ - Values: 4 to 768 (default 256) ++
host_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in host mode when dynamic FIFO ++ sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
host_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in host mode when ++ dynamic FIFO sizing is enabled in the core. ++ - Values: 16 to 32768 (default 1024) ++
host_perio_tx_fifo_sizeNumber of 4-byte words in the host periodic Tx FIFO when dynamic FIFO ++ sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
max_transfer_sizeThe maximum transfer size supported in bytes. ++ - Values: 2047 to 65,535 (default 65,535) ++
max_packet_countThe maximum number of packets in a transfer. ++ - Values: 15 to 511 (default 511) ++
host_channelsThe number of host channel registers to use. ++ - Values: 1 to 16 (default 12) ++ ++ Note: The FPGA configuration supports a maximum of 12 host channels. ++
dev_endpointsThe number of endpoints in addition to EP0 available for device mode ++ operations. ++ - Values: 1 to 15 (default 6 IN and OUT) ++ ++ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in ++ addition to EP0. ++
phy_typeSpecifies the type of PHY interface to use. By default, the driver will ++ automatically detect the phy_type. ++ - 0: Full Speed ++ - 1: UTMI+ (default, if available) ++ - 2: ULPI ++
phy_utmi_widthSpecifies the UTMI+ Data Width. This parameter is applicable for a ++ phy_type of UTMI+. Also, this parameter is applicable only if the ++ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the ++ core has been configured to work at either data path width. ++ - Values: 8 or 16 bits (default 16) ++
phy_ulpi_ddrSpecifies whether the ULPI operates at double or single data rate. This ++ parameter is only applicable if phy_type is ULPI. ++ - 0: single data rate ULPI interface with 8 bit wide data bus (default) ++ - 1: double data rate ULPI interface with 4 bit wide data bus ++
i2c_enableSpecifies whether to use the I2C interface for full speed PHY. This ++ parameter is only applicable if PHY_TYPE is FS. ++ - 0: Disabled (default) ++ - 1: Enabled ++
ulpi_fs_lsSpecifies whether to use ULPI FS/LS mode only. ++ - 0: Disabled (default) ++ - 1: Enabled ++
ts_dlineSpecifies whether term select D-Line pulsing for all PHYs is enabled. ++ - 0: Disabled (default) ++ - 1: Enabled ++
en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Disabled ++ - 1: Enabled (default, if available) ++
dev_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the Tx FIFOs in device mode ++ when dynamic FIFO sizing is enabled. ++ - Values: 4 to 768 (default 256) ++
tx_thr_lengthTransmit Threshold length in 32 bit double words ++ - Values: 8 to 128 (default 64) ++
rx_thr_lengthReceive Threshold length in 32 bit double words ++ - Values: 8 to 128 (default 64) ++
thr_ctlSpecifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of ++ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and ++ Rx transfers accordingly. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - Values: 0 to 7 (default 0) ++ Bit values indicate: ++ - 0: Thresholding disabled ++ - 1: Thresholding enabled ++
dma_desc_enableSpecifies whether to enable Descriptor DMA mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Descriptor DMA disabled ++ - 1: Descriptor DMA (default, if available) ++
mpi_enableSpecifies whether to enable MPI enhancement mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: MPI disabled (default) ++ - 1: MPI enable ++
pti_enableSpecifies whether to enable PTI enhancement support. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: PTI disabled (default) ++ - 1: PTI enable ++
lpm_enableSpecifies whether to enable LPM support. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: LPM disabled ++ - 1: LPM enable (default, if available) ++
ic_usb_capSpecifies whether to enable IC_USB capability. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: IC_USB disabled (default, if available) ++ - 1: IC_USB enable ++
ahb_thr_ratioSpecifies AHB Threshold ratio. ++ - Values: 0 to 3 (default 0) ++
power_downSpecifies Power Down(Hibernation) Mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Power Down disabled (default) ++ - 2: Power Down enabled ++
reload_ctlSpecifies whether dynamic reloading of the HFIR register is allowed during ++ run time. The driver will automatically detect the value for this parameter if ++ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0 ++ the core might misbehave. ++ - 0: Reload Control disabled (default) ++ - 1: Reload Control enabled ++
dev_out_nakSpecifies whether Device OUT NAK enhancement enabled or no. ++ The driver will automatically detect the value for this parameter if ++ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1. ++ - 0: The core does not set NAK after Bulk OUT transfer complete (default) ++ - 1: The core sets NAK after Bulk OUT transfer complete ++
cont_on_bnaSpecifies whether Enable Continue on BNA enabled or no. ++ After receiving BNA interrupt the core disables the endpoint,when the ++ endpoint is re-enabled by the application the ++ - 0: Core starts processing from the DOEPDMA descriptor (default) ++ - 1: Core starts processing from the descriptor which received the BNA. ++ This parameter is valid only when OTG_EN_DESC_DMA == 1b1. ++
ahb_singleThis bit when programmed supports SINGLE transfers for remainder data ++ in a transfer for DMA mode of operation. ++ - 0: The remainder data will be sent using INCR burst size (default) ++ - 1: The remainder data will be sent using SINGLE burst size. ++
adp_enableSpecifies whether ADP feature is enabled. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: ADP feature disabled (default) ++ - 1: ADP feature enabled ++
otg_verSpecifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3 ++ USB OTG device. ++ - 0: OTG 2.0 support disabled (default) ++ - 1: OTG 2.0 support enabled ++
++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ *
Command Driver Description
GET_STATUS PCD Command is processed as ++ * defined in chapter 9 of the USB 2.0 Specification chapter 9 ++ *
CLEAR_FEATURE PCD The Device and Endpoint ++ * requests are the ENDPOINT_HALT feature is procesed, all others the ++ * interface requests are ignored.
SET_FEATURE PCD The Device and Endpoint ++ * requests are processed by the PCD. Interface requests are passed ++ * to the Gadget Driver.
SET_ADDRESS PCD Program the DCFG reg, ++ * with device address received
GET_DESCRIPTOR Gadget Driver Return the ++ * requested descriptor
SET_DESCRIPTOR Gadget Driver Optional - ++ * not implemented by any of the existing Gadget Drivers.
SET_CONFIGURATION Gadget Driver Disable ++ * all EPs and enable EPs for new configuration.
GET_CONFIGURATION Gadget Driver Return ++ * the current configuration
SET_INTERFACE Gadget Driver Disable all ++ * EPs and enable EPs for new configuration.
GET_INTERFACE Gadget Driver Return the ++ * current interface.
SYNC_FRAME PCD Display debug ++ * message.
++ * ++ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are ++ * processed by pcd_setup. Calling the Function Driver's setup function from ++ * pcd_setup processes the gadget SETUP commands. ++ */ ++static inline void pcd_setup(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ ++#ifdef DWC_UTE_CFI ++ int retval = 0; ++ struct cfi_usb_ctrlrequest cfi_req; ++#endif ++ ++ doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz); ++ ++ /** In BDMA more then 1 setup packet is not supported till 3.00a */ ++ if (core_if->dma_enable && core_if->dma_desc_enable == 0 ++ && (doeptsize0.b.supcnt < 2) ++ && (core_if->snpsid < OTG_CORE_REV_2_94a)) { ++ DWC_ERROR ++ ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n"); ++ } ++ if ((core_if->snpsid >= OTG_CORE_REV_3_00a) ++ && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) { ++ ctrl = ++ (pcd->setup_pkt + ++ (3 - doeptsize0.b.supcnt - 1 + ++ ep0->dwc_ep.stp_rollover))->req; ++ } ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++#endif ++ ++ /* Clean up the request queue */ ++ dwc_otg_request_nuke(ep0); ++ ep0->stopped = 0; ++ ++ if (ctrl.bmRequestType & UE_DIR_IN) { ++ ep0->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_DATA_PHASE; ++ } else { ++ ep0->dwc_ep.is_in = 0; ++ pcd->ep0state = EP0_OUT_DATA_PHASE; ++ } ++ ++ if (UGETW(ctrl.wLength) == 0) { ++ ep0->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ } ++ ++ if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) { ++ ++#ifdef DWC_UTE_CFI ++ DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t)); ++ ++ //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ++ ctrl.bRequestType, ctrl.bRequest); ++ if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) { ++ if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) { ++ retval = cfi_setup(pcd, &cfi_req); ++ if (retval < 0) { ++ ep0_do_stall(pcd, retval); ++ pcd->ep0_pending = 0; ++ return; ++ } ++ ++ /* if need gadget setup then call it and check the retval */ ++ if (pcd->cfi->need_gadget_att) { ++ retval = ++ cfi_gadget_setup(pcd, ++ &pcd-> ++ cfi->ctrl_req); ++ if (retval < 0) { ++ pcd->ep0_pending = 0; ++ return; ++ } ++ } ++ ++ if (pcd->cfi->need_status_in_complete) { ++ do_setup_in_status_phase(pcd); ++ } ++ return; ++ } ++ } ++#endif ++ ++ /* handle non-standard (class/vendor) requests in the gadget driver */ ++ do_gadget_setup(pcd, &ctrl); ++ return; ++ } ++ ++ /** @todo NGS: Handle bad setup packet? */ ++ ++/////////////////////////////////////////// ++//// --- Standard Request handling --- //// ++ ++ switch (ctrl.bRequest) { ++ case UR_GET_STATUS: ++ do_get_status(pcd); ++ break; ++ ++ case UR_CLEAR_FEATURE: ++ do_clear_feature(pcd); ++ break; ++ ++ case UR_SET_FEATURE: ++ do_set_feature(pcd); ++ break; ++ ++ case UR_SET_ADDRESS: ++ do_set_address(pcd); ++ break; ++ ++ case UR_SET_INTERFACE: ++ case UR_SET_CONFIG: ++// _pcd->request_config = 1; /* Configuration changed */ ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ case UR_SYNCH_FRAME: ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ default: ++ /* Call the Gadget Driver's setup functions */ ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ } ++} ++ ++/** ++ * This function completes the ep0 control transfer. ++ */ ++static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs = ++ dev_if->in_ep_regs[ep->dwc_ep.num]; ++#ifdef DEBUG_EP0 ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs = ++ dev_if->out_ep_regs[ep->dwc_ep.num]; ++#endif ++ deptsiz0_data_t deptsiz; ++ dev_dma_desc_sts_t desc_sts; ++ dwc_otg_pcd_request_t *req; ++ int is_last = 0; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ ++#ifdef DWC_UTE_CFI ++ struct cfi_usb_ctrlrequest *ctrlreq; ++ int retval = -DWC_E_NOT_SUPPORTED; ++#endif ++ ++ desc_sts.b.bytes = 0; ++ ++ if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ if (ep->dwc_ep.is_in) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n"); ++#endif ++ do_setup_out_status_phase(pcd); ++ } else { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n"); ++#endif ++ ++#ifdef DWC_UTE_CFI ++ ctrlreq = &pcd->cfi->ctrl_req; ++ ++ if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) { ++ if (ctrlreq->bRequest > 0xB0 ++ && ctrlreq->bRequest < 0xBF) { ++ ++ /* Return if the PCD failed to handle the request */ ++ if ((retval = ++ pcd->cfi->ops. ++ ctrl_write_complete(pcd->cfi, ++ pcd)) < 0) { ++ CFI_INFO ++ ("ERROR setting a new value in the PCD(%d)\n", ++ retval); ++ ep0_do_stall(pcd, retval); ++ pcd->ep0_pending = 0; ++ return 0; ++ } ++ ++ /* If the gadget needs to be notified on the request */ ++ if (pcd->cfi->need_gadget_att == 1) { ++ //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req); ++ retval = ++ cfi_gadget_setup(pcd, ++ &pcd->cfi-> ++ ctrl_req); ++ ++ /* Return from the function if the gadget failed to process ++ * the request properly - this should never happen !!! ++ */ ++ if (retval < 0) { ++ CFI_INFO ++ ("ERROR setting a new value in the gadget(%d)\n", ++ retval); ++ pcd->ep0_pending = 0; ++ return 0; ++ } ++ } ++ ++ CFI_INFO("%s: RETVAL=%d\n", __func__, ++ retval); ++ /* If we hit here then the PCD and the gadget has properly ++ * handled the request - so send the ZLP IN to the host. ++ */ ++ /* @todo: MAS - decide whether we need to start the setup ++ * stage based on the need_setup value of the cfi object ++ */ ++ do_setup_in_status_phase(pcd); ++ pcd->ep0_pending = 0; ++ return 1; ++ } ++ } ++#endif ++ ++ do_setup_in_status_phase(pcd); ++ } ++ pcd->ep0_pending = 0; ++ return 1; ++ } ++ ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ return 0; ++ } ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ++ if (pcd->ep0state == EP0_OUT_STATUS_PHASE ++ || pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ is_last = 1; ++ } else if (ep->dwc_ep.is_in) { ++ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz); ++ if (core_if->dma_desc_enable != 0) ++ desc_sts = dev_if->in_desc_addr->status; ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++#endif ++ ++ if (((core_if->dma_desc_enable == 0) ++ && (deptsiz.b.xfersize == 0)) ++ || ((core_if->dma_desc_enable != 0) ++ && (desc_sts.b.bytes == 0))) { ++ req->actual = ep->dwc_ep.xfer_count; ++ /* Is a Zero Len Packet needed? */ ++ if (req->sent_zlp) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n"); ++#endif ++ req->sent_zlp = 0; ++ } ++ do_setup_out_status_phase(pcd); ++ } ++ } else { ++ /* ep0-OUT */ ++#ifdef DEBUG_EP0 ++ deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz); ++ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++#endif ++ req->actual = ep->dwc_ep.xfer_count; ++ ++ /* Is a Zero Len Packet needed? */ ++ if (req->sent_zlp) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n"); ++#endif ++ req->sent_zlp = 0; ++ } ++ /* For older cores do setup in status phase in Slave/BDMA modes, ++ * starting from 3.00 do that only in slave, and for DMA modes ++ * just re-enable ep 0 OUT here*/ ++ if (core_if->dma_enable == 0 ++ || (core_if->dma_desc_enable == 0 ++ && core_if->snpsid <= OTG_CORE_REV_2_94a)) { ++ do_setup_in_status_phase(pcd); ++ } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "Enable out ep before in status phase\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ ++ /* Complete the request */ ++ if (is_last) { ++ dwc_otg_request_done(ep, req, 0); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ return 1; ++ } ++ return 0; ++} ++ ++#ifdef DWC_UTE_CFI ++/** ++ * This function calculates traverses all the CFI DMA descriptors and ++ * and accumulates the bytes that are left to be transfered. ++ * ++ * @return The total bytes left to transfered, or a negative value as failure ++ */ ++static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep) ++{ ++ int32_t ret = 0; ++ int i; ++ struct dwc_otg_dma_desc *ddesc = NULL; ++ struct cfi_ep *cfiep; ++ ++ /* See if the pcd_ep has its respective cfi_ep mapped */ ++ cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep); ++ if (!cfiep) { ++ CFI_INFO("%s: Failed to find ep\n", __func__); ++ return -1; ++ } ++ ++ ddesc = ep->dwc_ep.descs; ++ ++ for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) { ++ ++#if defined(PRINT_CFI_DMA_DESCS) ++ print_desc(ddesc, ep->ep.name, i); ++#endif ++ ret += ddesc->status.b.bytes; ++ ddesc++; ++ } ++ ++ if (ret) ++ CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__, ++ ret); ++ ++ return ret; ++} ++#endif ++ ++/** ++ * This function completes the request for the EP. If there are ++ * additional requests for the EP in the queue they will be started. ++ */ ++static void complete_ep(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs = ++ dev_if->in_ep_regs[ep->dwc_ep.num]; ++ deptsiz_data_t deptsiz; ++ dev_dma_desc_sts_t desc_sts; ++ dwc_otg_pcd_request_t *req = 0; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ uint32_t byte_count = 0; ++ int is_last = 0; ++ int i; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT")); ++ ++ /* Get any pending requests */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ return; ++ } ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ return; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending); ++ ++ if (ep->dwc_ep.is_in) { ++ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz); ++ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ if (deptsiz.b.xfersize == 0 ++ && deptsiz.b.pktcnt == 0) { ++ byte_count = ++ ep->dwc_ep.xfer_len - ++ ep->dwc_ep.xfer_count; ++ ++ ep->dwc_ep.xfer_buff += byte_count; ++ ep->dwc_ep.dma_addr += byte_count; ++ ep->dwc_ep.xfer_count += byte_count; ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%d-%s len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep. ++ is_in ? "IN" : "OUT"), ++ ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ ++ if (ep->dwc_ep.xfer_len < ++ ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer ++ (core_if, &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length transfer in case if it is queued ++ * a transfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Descriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 length. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer ++ (core_if, &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ if (ep->dwc_ep.type == ++ DWC_OTG_EP_TYPE_ISOC) { ++ req->actual = 0; ++ dwc_otg_request_done(ep, req, 0); ++ ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ ++ /* If there is a request in the queue start it. */ ++ start_next_request(ep); ++ } else ++ DWC_WARN ++ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ } ++ } else { ++ dma_desc = ep->dwc_ep.desc_addr; ++ byte_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ++#ifdef DWC_UTE_CFI ++ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__, ++ ep->dwc_ep.buff_mode); ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ int residue; ++ ++ residue = cfi_calc_desc_residue(ep); ++ if (residue < 0) ++ return; ++ ++ byte_count = residue; ++ } else { ++#endif ++ for (i = 0; i < ep->dwc_ep.desc_cnt; ++ ++i) { ++ desc_sts = dma_desc->status; ++ byte_count += desc_sts.b.bytes; ++ dma_desc++; ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ if (byte_count == 0) { ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len; ++ is_last = 1; ++ } else { ++ DWC_WARN("Incomplete transfer\n"); ++ } ++ } ++ } else { ++ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "%d-%s len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT", ++ ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, ++ &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length trasfer in case if it is queued ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 legth. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ DWC_WARN ++ ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ } ++ } ++ } else { ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs = ++ dev_if->out_ep_regs[ep->dwc_ep.num]; ++ desc_sts.d32 = 0; ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ dma_desc = ep->dwc_ep.desc_addr; ++ byte_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ++#ifdef DWC_UTE_CFI ++ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__, ++ ep->dwc_ep.buff_mode); ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ int residue; ++ residue = cfi_calc_desc_residue(ep); ++ if (residue < 0) ++ return; ++ byte_count = residue; ++ } else { ++#endif ++ ++ for (i = 0; i < ep->dwc_ep.desc_cnt; ++ ++i) { ++ desc_sts = dma_desc->status; ++ byte_count += desc_sts.b.bytes; ++ dma_desc++; ++ } ++ ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ /* Checking for interrupt Out transfers with not ++ * dword aligned mps sizes ++ */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR && ++ (ep->dwc_ep.maxpacket%4)) { ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len - byte_count; ++ if ((ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket) ++ && (ep->dwc_ep.xfer_len / ++ ep->dwc_ep.maxpacket < ++ MAX_DMA_DESC_CNT)) ++ ep->dwc_ep.xfer_len -= ++ (ep->dwc_ep.desc_cnt - ++ 1) * ep->dwc_ep.maxpacket + ++ ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket; ++ else ++ ep->dwc_ep.xfer_len -= ++ ep->dwc_ep.desc_cnt * ++ ep->dwc_ep.maxpacket; ++ if (ep->dwc_ep.xfer_len > 0) { ++ dwc_otg_ep_start_transfer ++ (core_if, &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len - byte_count + ++ ((4 - ++ (ep->dwc_ep. ++ total_len & 0x3)) & 0x3); ++ is_last = 1; ++ } ++ } else { ++ deptsiz.d32 = 0; ++ deptsiz.d32 = ++ DWC_READ_REG32(&out_ep_regs->doeptsiz); ++ ++ byte_count = (ep->dwc_ep.xfer_len - ++ ep->dwc_ep.xfer_count - ++ deptsiz.b.xfersize); ++ ep->dwc_ep.xfer_buff += byte_count; ++ ep->dwc_ep.dma_addr += byte_count; ++ ep->dwc_ep.xfer_count += byte_count; ++ ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, ++ &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length trasfer in case if it is queued ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 legth. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } ++ } else { ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length transfer in case if it is queued ++ * a transfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Descriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 length. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n", ++ &out_ep_regs->doeptsiz, ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT", ++ ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ } ++ ++ /* Complete the request */ ++ if (is_last) { ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ req->actual = ep->dwc_ep.cfi_req_len - byte_count; ++ } else { ++#endif ++ req->actual = ep->dwc_ep.xfer_count; ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ if (req->dw_align_buf) { ++ if (!ep->dwc_ep.is_in) { ++ dwc_memcpy(req->buf, req->dw_align_buf, req->length); ++ } ++ DWC_DMA_FREE(req->length, req->dw_align_buf, ++ req->dw_align_buf_dma); ++ } ++ ++ dwc_otg_request_done(ep, req, 0); ++ ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ ++ /* If there is a request in the queue start it. */ ++ start_next_request(ep); ++ } ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function BNA interrupt for Isochronous EPs ++ * ++ */ ++static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ volatile uint32_t *addr; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ int i; ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num); ++ ++ if (dwc_ep->is_in) { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b_iso_in.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ } else { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b_iso_out.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ } ++ ++ if (dwc_ep->is_in == 0) { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep-> ++ num]->doepctl; ++ } else { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ depctl.b.epena = 1; ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); ++} ++ ++/** ++ * This function sets latest iso packet information(non-PTI mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ dma_addr_t dma_addr; ++ uint32_t offset; ++ ++ if (ep->proc_buf_num) ++ dma_addr = ep->dma_addr1; ++ else ++ dma_addr = ep->dma_addr0; ++ ++ if (ep->is_in) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->dieptsiz); ++ offset = ep->data_per_frame; ++ } else { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz); ++ offset = ++ ep->data_per_frame + ++ (0x4 & (0x4 - (ep->data_per_frame & 0x3))); ++ } ++ ++ if (!deptsiz.b.xfersize) { ++ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; ++ ep->pkt_info[ep->cur_pkt].offset = ++ ep->cur_pkt_dma_addr - dma_addr; ++ ep->pkt_info[ep->cur_pkt].status = 0; ++ } else { ++ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; ++ ep->pkt_info[ep->cur_pkt].offset = ++ ep->cur_pkt_dma_addr - dma_addr; ++ ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA; ++ } ++ ep->cur_pkt_addr += offset; ++ ep->cur_pkt_dma_addr += offset; ++ ep->cur_pkt++; ++} ++ ++/** ++ * This function sets latest iso packet information(DDMA mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ iso_pkt_info_t *iso_packet; ++ uint32_t data_per_desc; ++ uint32_t offset; ++ int i, j; ++ ++ iso_packet = dwc_ep->pkt_info; ++ ++ /** Reinit closed DMA Descriptors*/ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ offset = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep-> ++ data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - ++ data_per_desc % ++ 4) : 0; ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + ++ (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Received data length */ ++ if (!sts.b_iso_out.rxbytes) { ++ iso_packet->length = ++ data_per_desc - ++ sts.b_iso_out.rxbytes; ++ } else { ++ iso_packet->length = ++ data_per_desc - ++ sts.b_iso_out.rxbytes + (4 - ++ dwc_ep->data_per_frame ++ % 4); ++ } ++ ++ iso_packet->offset = offset; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ iso_packet++; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + ++ (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Received data length */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; ++ ++ iso_packet->offset = offset; ++ ++ offset += data_per_desc; ++ iso_packet++; ++ dma_desc++; ++ } ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ /* Received data length */ ++ if (!sts.b_iso_out.rxbytes) { ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; ++ } else { ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes + ++ (4 - dwc_ep->data_per_frame % 4); ++ } ++ ++ iso_packet->offset = offset; ++ } else { ++/** ISO IN EP */ ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso packet descriptor */ ++ iso_packet->status = ++ sts.b_iso_in.txsts + ++ (sts.b_iso_in.bs ^ BS_DMA_DONE); ++ if (iso_packet->status != 0) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ ++ } ++ /* Bytes has been transfered */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_in.txbytes; ++ ++ dma_desc++; ++ iso_packet++; ++ } ++ ++ sts.d32 = dma_desc->status.d32; ++ while (sts.b_iso_in.bs == BS_DMA_BUSY) { ++ sts.d32 = dma_desc->status.d32; ++ } ++ ++ /* Write status in iso packet descriptor ??? do be done with ERROR codes */ ++ iso_packet->status = ++ sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE); ++ if (iso_packet->status != 0) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Bytes has been transfered */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_in.txbytes; ++ } ++} ++ ++/** ++ * This function reinitialize DMA Descriptors for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep) ++{ ++ int i, j; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dma_addr_t dma_ad; ++ volatile uint32_t *addr; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ uint32_t data_per_desc; ++ ++ if (dwc_ep->is_in == 0) { ++ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; ++ } else { ++ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ ++ if (dwc_ep->proc_buf_num == 0) { ++ /** Buffer 0 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr0; ++ } else { ++ /** Buffer 1 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr1; ++ } ++ ++ /** Reinit closed DMA Descriptors*/ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ sts.b_iso_out.bs = BS_HOST_READY; ++ sts.b_iso_out.rxsts = 0; ++ sts.b_iso_out.l = 0; ++ sts.b_iso_out.sp = 0; ++ sts.b_iso_out.ioc = 0; ++ sts.b_iso_out.pid = 0; ++ sts.b_iso_out.framenum = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep-> ++ data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - ++ data_per_desc % ++ 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dma_ad += data_per_desc; ++ dma_desc++; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ sts.b_iso_out.l = dwc_ep->proc_buf_num; ++ ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ } else { ++/** ISO IN EP */ ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ sts.b_iso_in.bs = BS_HOST_READY; ++ sts.b_iso_in.txsts = 0; ++ sts.b_iso_in.sp = 0; ++ sts.b_iso_in.ioc = 0; ++ sts.b_iso_in.pid = dwc_ep->pkt_per_frm; ++ sts.b_iso_in.framenum = dwc_ep->next_frame; ++ sts.b_iso_in.txbytes = dwc_ep->data_per_frame; ++ sts.b_iso_in.l = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ dma_ad += dwc_ep->data_per_frame; ++ dma_desc++; ++ } ++ ++ sts.b_iso_in.ioc = 1; ++ sts.b_iso_in.l = dwc_ep->proc_buf_num; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = ++ sts.b_iso_in.framenum + dwc_ep->bInterval * 1; ++ } ++ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; ++} ++ ++/** ++ * This function is to handle Iso EP transfer complete interrupt ++ * in case Iso out packet was dropped ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP for wihich transfer complete was asserted ++ * ++ */ ++static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ uint32_t dma_addr; ++ uint32_t drp_pkt; ++ uint32_t drp_pkt_cnt; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ int i; ++ ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doeptsiz); ++ ++ drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt; ++ drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm); ++ ++ /* Setting dropped packets status */ ++ for (i = 0; i < drp_pkt_cnt; ++i) { ++ dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA; ++ drp_pkt++; ++ deptsiz.b.pktcnt--; ++ } ++ ++ if (deptsiz.b.pktcnt > 0) { ++ deptsiz.b.xfersize = ++ dwc_ep->xfer_len - (dwc_ep->pkt_cnt - ++ deptsiz.b.pktcnt) * dwc_ep->maxpacket; ++ } else { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 0; ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, ++ deptsiz.d32); ++ ++ if (deptsiz.b.pktcnt > 0) { ++ if (dwc_ep->proc_buf_num) { ++ dma_addr = ++ dwc_ep->dma_addr1 + dwc_ep->xfer_len - ++ deptsiz.b.xfersize; ++ } else { ++ dma_addr = ++ dwc_ep->dma_addr0 + dwc_ep->xfer_len - ++ deptsiz.b.xfersize;; ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doepdma, dma_addr); ++ ++ /** Re-enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ DWC_MODIFY_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doepctl, depctl.d32, ++ depctl.d32); ++ return 0; ++ } else { ++ return 1; ++ } ++} ++ ++/** ++ * This function sets iso packets information(PTI mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ int i, j; ++ dma_addr_t dma_ad; ++ iso_pkt_info_t *packet_info = ep->pkt_info; ++ uint32_t offset; ++ uint32_t frame_data; ++ deptsiz_data_t deptsiz; ++ ++ if (ep->proc_buf_num == 0) { ++ /** Buffer 0 descriptors setup */ ++ dma_ad = ep->dma_addr0; ++ } else { ++ /** Buffer 1 descriptors setup */ ++ dma_ad = ep->dma_addr1; ++ } ++ ++ if (ep->is_in) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz); ++ } else { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz); ++ } ++ ++ if (!deptsiz.b.xfersize) { ++ offset = 0; ++ for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) { ++ frame_data = ep->data_per_frame; ++ for (j = 0; j < ep->pkt_per_frm; ++j) { ++ ++ /* Packet status - is not set as initially ++ * it is set to 0 and if packet was sent ++ successfully, status field will remain 0*/ ++ ++ /* Bytes has been transfered */ ++ packet_info->length = ++ (ep->maxpacket < ++ frame_data) ? ep->maxpacket : frame_data; ++ ++ /* Received packet offset */ ++ packet_info->offset = offset; ++ offset += packet_info->length; ++ frame_data -= packet_info->length; ++ ++ packet_info++; ++ } ++ } ++ return 1; ++ } else { ++ /* This is a workaround for in case of Transfer Complete with ++ * PktDrpSts interrupts merging - in this case Transfer complete ++ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts ++ * set and with DOEPTSIZ register non zero. Investigations showed, ++ * that this happens when Out packet is dropped, but because of ++ * interrupts merging during first interrupt handling PktDrpSts ++ * bit is cleared and for next merged interrupts it is not reset. ++ * In this case SW hadles the interrupt as if PktDrpSts bit is set. ++ */ ++ if (ep->is_in) { ++ return 1; ++ } else { ++ return handle_iso_out_pkt_dropped(core_if, ep); ++ } ++ } ++} ++ ++/** ++ * This function is to handle Iso EP transfer complete interrupt ++ * ++ * @param pcd The PCD ++ * @param ep The EP for which transfer complete was asserted ++ * ++ */ ++static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ uint8_t is_last = 0; ++ ++ if (ep->dwc_ep.next_frame == 0xffffffff) { ++ DWC_WARN("Next frame is not set!\n"); ++ return; ++ } ++ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ set_ddma_iso_pkts_info(core_if, dwc_ep); ++ reinit_ddma_iso_xfer(core_if, dwc_ep); ++ is_last = 1; ++ } else { ++ if (core_if->pti_enh_enable) { ++ if (set_iso_pkts_info(core_if, dwc_ep)) { ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ dwc_otg_iso_ep_start_buf_transfer ++ (core_if, dwc_ep); ++ is_last = 1; ++ } ++ } else { ++ set_current_pkt_info(core_if, dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ is_last = 1; ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ++ dwc_ep); ++ } ++ } ++ } else { ++ set_current_pkt_info(core_if, dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ is_last = 1; ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; ++ } ++ ++ } ++ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep); ++ } ++ if (is_last) ++ dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle); ++} ++#endif /* DWC_EN_ISOC */ ++ ++/** ++ * This function handle BNA interrupt for Non Isochronous EPs ++ * ++ */ ++static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ volatile uint32_t *addr; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = ep->pcd->core_if; ++ int i, start; ++ ++ if (!dwc_ep->desc_cnt) ++ DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num, ++ (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt); ++ ++ if (core_if->core_params->cont_on_bna && !dwc_ep->is_in ++ && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) { ++ uint32_t doepdma; ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[dwc_ep->num]; ++ doepdma = DWC_READ_REG32(&(out_regs->doepdma)); ++ start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t); ++ dma_desc = &(dwc_ep->desc_addr[start]); ++ } else { ++ start = 0; ++ dma_desc = dwc_ep->desc_addr; ++ } ++ ++ ++ for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ ++ if (dwc_ep->is_in == 0) { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]-> ++ doepctl; ++ } else { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ DWC_MODIFY_REG32(addr, 0, depctl.d32); ++} ++ ++/** ++ * This function handles EP0 Control transfers. ++ * ++ * The state of the control transfers are tracked in ++ * ep0state. ++ */ ++static void handle_ep0(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ dev_dma_desc_sts_t desc_sts; ++ deptsiz0_data_t deptsiz; ++ uint32_t byte_count; ++ ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); ++ print_ep0_state(pcd); ++#endif ++ ++// DWC_PRINTF("HANDLE EP0\n"); ++ ++ switch (pcd->ep0state) { ++ case EP0_DISCONNECT: ++ break; ++ ++ case EP0_IDLE: ++ pcd->request_config = 0; ++ ++ pcd_setup(pcd); ++ break; ++ ++ case EP0_IN_DATA_PHASE: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n", ++ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"), ++ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); ++#endif ++ ++ if (core_if->dma_enable != 0) { ++ /* ++ * For EP0 we can only program 1 packet at a time so we ++ * need to do the make calculations after each complete. ++ * Call write_packet to make the calculations, as in ++ * slave mode, and use those values to determine if we ++ * can complete. ++ */ ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[0]-> ++ dieptsiz); ++ byte_count = ++ ep0->dwc_ep.xfer_len - deptsiz.b.xfersize; ++ } else { ++ desc_sts = ++ core_if->dev_if->in_desc_addr->status; ++ byte_count = ++ ep0->dwc_ep.xfer_len - desc_sts.b.bytes; ++ } ++ ep0->dwc_ep.xfer_count += byte_count; ++ ep0->dwc_ep.xfer_buff += byte_count; ++ ep0->dwc_ep.dma_addr += byte_count; ++ } ++ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ } else if (ep0->dwc_ep.sent_zlp) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ ep0->dwc_ep.sent_zlp = 0; ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n"); ++ } else { ++ ep0_complete_request(ep0); ++ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); ++ } ++ break; ++ case EP0_OUT_DATA_PHASE: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n", ++ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"), ++ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); ++#endif ++ if (core_if->dma_enable != 0) { ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->out_ep_regs[0]-> ++ doeptsiz); ++ byte_count = ++ ep0->dwc_ep.maxpacket - deptsiz.b.xfersize; ++ } else { ++ desc_sts = ++ core_if->dev_if->out_desc_addr->status; ++ byte_count = ++ ep0->dwc_ep.maxpacket - desc_sts.b.bytes; ++ } ++ ep0->dwc_ep.xfer_count += byte_count; ++ ep0->dwc_ep.xfer_buff += byte_count; ++ ep0->dwc_ep.dma_addr += byte_count; ++ } ++ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ } else if (ep0->dwc_ep.sent_zlp) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ ep0->dwc_ep.sent_zlp = 0; ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n"); ++ } else { ++ ep0_complete_request(ep0); ++ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); ++ } ++ break; ++ ++ case EP0_IN_STATUS_PHASE: ++ case EP0_OUT_STATUS_PHASE: ++ DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n"); ++ ep0_complete_request(ep0); ++ pcd->ep0state = EP0_IDLE; ++ ep0->stopped = 1; ++ ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */ ++ ++ /* Prepare for more SETUP Packets */ ++ if (core_if->dma_enable) { ++ ep0_out_start(core_if, pcd); ++ } ++ break; ++ ++ case EP0_STALL: ++ DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n"); ++ break; ++ } ++#ifdef DEBUG_EP0 ++ print_ep0_state(pcd); ++#endif ++} ++ ++/** ++ * Restart transfer ++ */ ++static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if; ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++#ifdef DWC_EN_ISOC ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ return; ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ core_if = GET_CORE_IF(pcd); ++ dev_if = core_if->dev_if; ++ ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ ++ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x" ++ " stopped=%d\n", ep->dwc_ep.xfer_buff, ++ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped); ++ /* ++ * If xfersize is 0 and pktcnt in not 0, resend the last packet. ++ */ ++ if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 && ++ ep->dwc_ep.start_xfer_buff != 0) { ++ if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) { ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff; ++ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; ++ } else { ++ ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket; ++ /* convert packet size to dwords. */ ++ ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket; ++ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; ++ } ++ ep->stopped = 0; ++ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x " ++ "xfer_len=%0x stopped=%d\n", ++ ep->dwc_ep.xfer_buff, ++ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ++ ep->stopped); ++ if (epnum == 0) { ++ dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep); ++ } else { ++ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); ++ } ++ } ++} ++ ++/* ++ * This function create new nextep sequnce based on Learn Queue. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void predict_nextep_seq( dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_device_global_regs_t *dev_global_regs = ++ core_if->dev_if->dev_global_regs; ++ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; ++ /* Number of Token Queue Registers */ ++ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; ++ dtknq1_data_t dtknqr1; ++ uint32_t in_tkn_epnums[4]; ++ uint8_t seqnum[MAX_EPS_CHANNELS]; ++ uint8_t intkn_seq[TOKEN_Q_DEPTH]; ++ grstctl_t resetctl = {.d32 = 0 }; ++ uint8_t temp; ++ int ndx = 0; ++ int start = 0; ++ int end = 0; ++ int sort_done = 0; ++ int i = 0; ++ volatile uint32_t *addr = &dev_global_regs->dtknqr1; ++ ++ ++ DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); ++ ++ /* Read the DTKNQ Registers */ ++ for (i = 0; i < DTKNQ_REG_CNT; i++) { ++ in_tkn_epnums[i] = DWC_READ_REG32(addr); ++ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, ++ in_tkn_epnums[i]); ++ if (addr == &dev_global_regs->dvbusdis) { ++ addr = &dev_global_regs->dtknqr3_dthrctl; ++ } else { ++ ++addr; ++ } ++ ++ } ++ ++ /* Copy the DTKNQR1 data to the bit field. */ ++ dtknqr1.d32 = in_tkn_epnums[0]; ++ if (dtknqr1.b.wrap_bit) { ++ ndx = dtknqr1.b.intknwptr; ++ end = ndx -1; ++ if (end < 0) ++ end = TOKEN_Q_DEPTH -1; ++ } else { ++ ndx = 0; ++ end = dtknqr1.b.intknwptr -1; ++ if (end < 0) ++ end = 0; ++ } ++ start = ndx; ++ ++ /* Fill seqnum[] by initial values: EP number + 31 */ ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ seqnum[i] = i +31; ++ } ++ ++ /* Fill intkn_seq[] from in_tkn_epnums[0] */ ++ for (i=0; i < 6; i++) ++ intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf; ++ ++ if (TOKEN_Q_DEPTH > 6) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=6; i < 14; i++) ++ intkn_seq[i] = ++ (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf; ++ } ++ ++ if (TOKEN_Q_DEPTH > 14) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=14; i < 22; i++) ++ intkn_seq[i] = ++ (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf; ++ } ++ ++ if (TOKEN_Q_DEPTH > 22) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=22; i < 30; i++) ++ intkn_seq[i] = ++ (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf; ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__, ++ start, end); ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == 0xff ) ++ seqnum[i] = 0xff; ++ } ++ ++ /* Sort seqnum[] */ ++ sort_done = 0; ++ while (!sort_done) { ++ sort_done = 1; ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (seqnum[i] > seqnum[i+1]) { ++ temp = seqnum[i]; ++ seqnum[i] = seqnum[i+1]; ++ seqnum[i+1] = temp; ++ sort_done = 0; ++ } ++ } ++ } ++ ++ ndx = start + seqnum[0]; ++ if (ndx >= TOKEN_Q_DEPTH) ++ ndx = ndx % TOKEN_Q_DEPTH; ++ core_if->first_in_nextep_seq = intkn_seq[ndx]; ++ ++ /* Update seqnum[] by EP numbers */ ++ for (i=0; i<=core_if->dev_if->num_in_eps; i++) { ++ ndx = start + i; ++ if (seqnum[i] < 31) { ++ ndx = start + seqnum[i]; ++ if (ndx >= TOKEN_Q_DEPTH) ++ ndx = ndx % TOKEN_Q_DEPTH; ++ seqnum[i] = intkn_seq[ndx]; ++ } else { ++ if (seqnum[i] < 0xff) { ++ seqnum[i] = seqnum[i] - 31; ++ } else { ++ break; ++ } ++ } ++ } ++ ++ /* Update nextep_seq[] based on seqnum[] */ ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (seqnum[i] != 0xff) { ++ if (seqnum[i+1] != 0xff) { ++ core_if->nextep_seq[seqnum[i]] = seqnum[i+1]; ++ } else { ++ core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq; ++ break; ++ } ++ } else { ++ break; ++ } ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]); ++ } ++ ++ /* Flush the Learning Queue */ ++ resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl); ++ resetctl.b.intknqflsh = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ ++} ++ ++/** ++ * handle the IN EP disable interrupt. ++ */ ++static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ gintmsk_data_t gintmsk_data; ++ depctl_data_t depctl; ++ uint32_t diepdma; ++ uint32_t remain_to_transfer = 0; ++ uint8_t i; ++ uint32_t xfer_size; ++ ++ ep = get_in_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); ++ complete_ep(ep); ++ return; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum, ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl)); ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); ++ ++ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", ++ dieptsiz.b.pktcnt, dieptsiz.b.xfersize); ++ ++ if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) { ++ if (ep->stopped) { ++ if (core_if->en_multiple_tx_fifo) ++ /* Flush the Tx FIFO */ ++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); ++ /* Clear the Global IN NP NAK */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ /* Restart the transaction */ ++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { ++ restart_transfer(pcd, epnum); ++ } ++ } else { ++ /* Restart the transaction */ ++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { ++ restart_transfer(pcd, epnum); ++ } ++ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n"); ++ } ++ return; ++ } ++ ++ if (core_if->start_predict > 2) { // NP IN EP ++ core_if->start_predict--; ++ return; ++ } ++ ++ core_if->start_predict--; ++ ++ if (core_if->start_predict == 1) { // All NP IN Ep's disabled now ++ ++ predict_nextep_seq(core_if); ++ ++ /* Update all active IN EP's NextEP field based of nextep_seq[] */ ++ for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP ++ depctl.b.nextep = core_if->nextep_seq[i]; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ } ++ } ++ /* Flush Shared NP TxFIFO */ ++ dwc_otg_flush_tx_fifo(core_if, 0); ++ /* Rewind buffers */ ++ if (!core_if->dma_desc_enable) { ++ i = core_if->first_in_nextep_seq; ++ do { ++ ep = get_in_ep(pcd, i); ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); ++ xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count; ++ if (xfer_size > ep->dwc_ep.maxxfer) ++ xfer_size = ep->dwc_ep.maxxfer; ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (dieptsiz.b.pktcnt != 0) { ++ if (xfer_size == 0) { ++ remain_to_transfer = 0; ++ } else { ++ if ((xfer_size % ep->dwc_ep.maxpacket) == 0) { ++ remain_to_transfer = ++ dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket; ++ } else { ++ remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket) ++ + (xfer_size % ep->dwc_ep.maxpacket); ++ } ++ } ++ diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma); ++ dieptsiz.b.xfersize = remain_to_transfer; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32); ++ diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma); ++ } ++ i = core_if->nextep_seq[i]; ++ } while (i != core_if->first_in_nextep_seq); ++ } else { // dma_desc_enable ++ DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__); ++ } ++ ++ /* Restart transfers in predicted sequences */ ++ i = core_if->first_in_nextep_seq; ++ do { ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (dieptsiz.b.pktcnt != 0) { ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ } ++ i = core_if->nextep_seq[i]; ++ } while (i != core_if->first_in_nextep_seq); ++ ++ /* Clear the global non-periodic IN NAK handshake */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ /* Unmask EP Mismatch interrupt */ ++ gintmsk_data.d32 = 0; ++ gintmsk_data.b.epmismatch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32); ++ ++ core_if->start_predict = 0; ++ ++ } ++} ++ ++/** ++ * Handler for the IN EP timeout handshake interrupt. ++ */ ++static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ ++#ifdef DEBUG ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ uint32_t num = 0; ++#endif ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++ /* Disable the NP Tx Fifo Empty Interrrupt */ ++ if (!core_if->dma_enable) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ } ++ /** @todo NGS Check EP type. ++ * Implement for Periodic EPs */ ++ /* ++ * Non-periodic EP ++ */ ++ /* Enable the Global IN NAK Effective Interrupt */ ++ intr_mask.b.ginnakeff = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); ++ ++ /* Set Global IN NAK */ ++ dctl.b.sgnpinnak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ ep->stopped = 1; ++ ++#ifdef DEBUG ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz); ++ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", ++ dieptsiz.b.pktcnt, dieptsiz.b.xfersize); ++#endif ++ ++#ifdef DISABLE_PERIODIC_EP ++ /* ++ * Set the NAK bit for this EP to ++ * start the disable process. ++ */ ++ diepctl.d32 = 0; ++ diepctl.b.snak = 1; ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, ++ diepctl.d32); ++ ep->disabling = 1; ++ ep->stopped = 1; ++#endif ++} ++ ++/** ++ * Handler for the IN EP NAK interrupt. ++ */ ++static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ diepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nak = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP Babble interrupt. ++ */ ++static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "OUT EP Babble"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.babble = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP NAK interrupt. ++ */ ++static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nak = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP NYET interrupt. ++ */ ++static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nyet = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that an IN EP has a pending Interrupt. ++ * The sequence for handling the IN EP interrupt is shown below: ++ * -# Read the Device All Endpoint Interrupt register ++ * -# Repeat the following for each IN EP interrupt bit set (from ++ * LSB to MSB). ++ * -# Read the Device Endpoint Interrupt (DIEPINTn) register ++ * -# If "Transfer Complete" call the request complete function ++ * -# If "Endpoint Disabled" complete the EP disable procedure. ++ * -# If "AHB Error Interrupt" log error ++ * -# If "Time-out Handshake" log error ++ * -# If "IN Token Received when TxFIFO Empty" write packet to Tx ++ * FIFO. ++ * -# If "IN Token EP Mismatch" (disable, this is handled by EP ++ * Mismatch Interrupt) ++ */ ++static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd) ++{ ++#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \ ++do { \ ++ diepint_data_t diepint = {.d32=0}; \ ++ diepint.b.__intr = 1; \ ++ DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \ ++ diepint.d32); \ ++} while (0) ++ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ diepint_data_t diepint = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ uint32_t ep_intr; ++ uint32_t epnum = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd); ++ ++ /* Read in the device interrupt bits */ ++ ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if); ++ ++ /* Service the Device IN interrupts for each endpoint */ ++ while (ep_intr) { ++ if (ep_intr & 0x1) { ++ uint32_t empty_msk; ++ /* Get EP pointer */ ++ ep = get_in_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); ++ empty_msk = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n", ++ epnum, empty_msk, depctl.d32); ++ ++ DWC_DEBUGPL(DBG_PCD, ++ "EP%d-%s: type=%d, mps=%d\n", ++ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"), ++ dwc_ep->type, dwc_ep->maxpacket); ++ ++ diepint.d32 = ++ dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP %d Interrupt Register - 0x%x\n", epnum, ++ diepint.d32); ++ /* Transfer complete */ ++ if (diepint.b.xfercompl) { ++ /* Disable the NP Tx FIFO Empty ++ * Interrupt */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ } else { ++ /* Disable the Tx FIFO Empty Interrupt for this EP */ ++ uint32_t fifoemptymsk = ++ 0x1 << dwc_ep->num; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ fifoemptymsk, 0); ++ } ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, xfercompl); ++ ++ /* Complete the transfer */ ++ if (epnum == 0) { ++ handle_ep0(pcd); ++ } ++#ifdef DWC_EN_ISOC ++ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (!ep->stopped) ++ complete_iso_ep(pcd, ep); ++ } ++#endif /* DWC_EN_ISOC */ ++#ifdef DWC_UTE_PER_IO ++ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (!ep->stopped) ++ complete_xiso_ep(ep); ++ } ++#endif /* DWC_UTE_PER_IO */ ++ else { ++ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC && ++ dwc_ep->bInterval > 1) { ++ dwc_ep->frame_num += dwc_ep->bInterval; ++ if (dwc_ep->frame_num > 0x3FFF) ++ { ++ dwc_ep->frm_overrun = 1; ++ dwc_ep->frame_num &= 0x3FFF; ++ } else ++ dwc_ep->frm_overrun = 0; ++ } ++ complete_ep(ep); ++ if(diepint.b.nak) ++ CLEAR_IN_EP_INTR(core_if, epnum, nak); ++ } ++ } ++ /* Endpoint disable */ ++ if (diepint.b.epdisabled) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n", ++ epnum); ++ handle_in_ep_disable_intr(pcd, epnum); ++ ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, epdisabled); ++ } ++ /* AHB Error */ ++ if (diepint.b.ahberr) { ++ DWC_ERROR("EP%d IN AHB Error\n", epnum); ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, ahberr); ++ } ++ /* TimeOUT Handshake (non-ISOC IN EPs) */ ++ if (diepint.b.timeout) { ++ DWC_ERROR("EP%d IN Time-out\n", epnum); ++ handle_in_ep_timeout_intr(pcd, epnum); ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, timeout); ++ } ++ /** IN Token received with TxF Empty */ ++ if (diepint.b.intktxfemp) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN TKN TxFifo Empty\n", ++ epnum); ++ if (!ep->stopped && epnum != 0) { ++ ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.intktxfemp = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32 ++ (&dev_if->dev_global_regs->diepeachintmsk ++ [epnum], diepmsk.d32, 0); ++ } else { ++ DWC_MODIFY_REG32 ++ (&dev_if->dev_global_regs->diepmsk, ++ diepmsk.d32, 0); ++ } ++ } else if (core_if->dma_desc_enable ++ && epnum == 0 ++ && pcd->ep0state == ++ EP0_OUT_STATUS_PHASE) { ++ // EP0 IN set STALL ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl); ++ ++ /* set the disable and stall bits */ ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ } ++ depctl.b.stall = 1; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl, ++ depctl.d32); ++ } ++ CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp); ++ } ++ /** IN Token Received with EP mismatch */ ++ if (diepint.b.intknepmis) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN TKN EP Mismatch\n", epnum); ++ CLEAR_IN_EP_INTR(core_if, epnum, intknepmis); ++ } ++ /** IN Endpoint NAK Effective */ ++ if (diepint.b.inepnakeff) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN EP NAK Effective\n", ++ epnum); ++ /* Periodic EP */ ++ if (ep->disabling) { ++ depctl.d32 = 0; ++ depctl.b.snak = 1; ++ depctl.b.epdis = 1; ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl, ++ depctl.d32, ++ depctl.d32); ++ } ++ CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff); ++ ++ } ++ ++ /** IN EP Tx FIFO Empty Intr */ ++ if (diepint.b.emptyintr) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d Tx FIFO Empty Intr \n", ++ epnum); ++ write_empty_tx_fifo(pcd, epnum); ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, emptyintr); ++ ++ } ++ ++ /** IN EP BNA Intr */ ++ if (diepint.b.bna) { ++ CLEAR_IN_EP_INTR(core_if, epnum, bna); ++ if (core_if->dma_desc_enable) { ++#ifdef DWC_EN_ISOC ++ if (dwc_ep->type == ++ DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This checking is performed to prevent first "false" BNA ++ * handling occuring right after reconnect ++ */ ++ if (dwc_ep->next_frame != ++ 0xffffffff) ++ dwc_otg_pcd_handle_iso_bna(ep); ++ } else ++#endif /* DWC_EN_ISOC */ ++ { ++ dwc_otg_pcd_handle_noniso_bna(ep); ++ } ++ } ++ } ++ /* NAK Interrutp */ ++ if (diepint.b.nak) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n", ++ epnum); ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ depctl_data_t depctl; ++ if (ep->dwc_ep.frame_num == 0xFFFFFFFF) { ++ ep->dwc_ep.frame_num = core_if->frame_num; ++ if (ep->dwc_ep.bInterval > 1) { ++ depctl.d32 = 0; ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); ++ if (ep->dwc_ep.frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ depctl.b.setd0pid = 0; ++ } else { ++ depctl.b.setd0pid = 1; ++ depctl.b.setd1pid = 0; ++ } ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32); ++ } ++ start_next_request(ep); ++ } ++ ep->dwc_ep.frame_num += ep->dwc_ep.bInterval; ++ if (dwc_ep->frame_num > 0x3FFF) { ++ dwc_ep->frm_overrun = 1; ++ dwc_ep->frame_num &= 0x3FFF; ++ } else ++ dwc_ep->frm_overrun = 0; ++ } ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, nak); ++ } ++ } ++ epnum++; ++ ep_intr >>= 1; ++ } ++ ++ return 1; ++#undef CLEAR_IN_EP_INTR ++} ++ ++/** ++ * This interrupt indicates that an OUT EP has a pending Interrupt. ++ * The sequence for handling the OUT EP interrupt is shown below: ++ * -# Read the Device All Endpoint Interrupt register ++ * -# Repeat the following for each OUT EP interrupt bit set (from ++ * LSB to MSB). ++ * -# Read the Device Endpoint Interrupt (DOEPINTn) register ++ * -# If "Transfer Complete" call the request complete function ++ * -# If "Endpoint Disabled" complete the EP disable procedure. ++ * -# If "AHB Error Interrupt" log error ++ * -# If "Setup Phase Done" process Setup Packet (See Standard USB ++ * Command Processing) ++ */ ++static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd) ++{ ++#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \ ++do { \ ++ doepint_data_t doepint = {.d32=0}; \ ++ doepint.b.__intr = 1; \ ++ DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \ ++ doepint.d32); \ ++} while (0) ++ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ uint32_t ep_intr; ++ doepint_data_t doepint = {.d32 = 0 }; ++ uint32_t epnum = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); ++ ++ /* Read in the device interrupt bits */ ++ ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if); ++ ++ while (ep_intr) { ++ if (ep_intr & 0x1) { ++ /* Get EP pointer */ ++ ep = get_out_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP%d-%s: type=%d, mps=%d\n", ++ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"), ++ dwc_ep->type, dwc_ep->maxpacket); ++#endif ++ doepint.d32 = ++ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep); ++ /* Moved this interrupt upper due to core deffect of asserting ++ * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */ ++ if (doepint.b.stsphsercvd) { ++ deptsiz0_data_t deptsiz; ++ CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd); ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doeptsiz); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a ++ && core_if->dma_enable ++ && core_if->dma_desc_enable == 0 ++ && doepint.b.xfercompl ++ && deptsiz.b.xfersize == 24) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, ++ xfercompl); ++ doepint.b.xfercompl = 0; ++ ep0_out_start(core_if, pcd); ++ } ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= ++ OTG_CORE_REV_3_00a)) { ++ do_setup_in_status_phase(pcd); ++ } ++ } ++ /* Transfer complete */ ++ if (doepint.b.xfercompl) { ++ ++ if (epnum == 0) { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n", ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint), ++ doepint.d32); ++ DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n", ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl)); ++ ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a ++ && core_if->dma_enable == 0) { ++ doepint_data_t doepint; ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if (pcd->ep0state == EP0_IDLE && doepint.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ goto exit_xfercompl; ++ } ++ } ++ /* In case of DDMA look at SR bit to go to the Data Stage */ ++ if (core_if->dma_desc_enable) { ++ dev_dma_desc_sts_t status = {.d32 = 0}; ++ if (pcd->ep0state == EP0_IDLE) { ++ status.d32 = core_if->dev_if->setup_desc_addr[core_if-> ++ dev_if->setup_desc_index]->status.d32; ++ if(pcd->data_terminated) { ++ pcd->data_terminated = 0; ++ status.d32 = core_if->dev_if->out_desc_addr->status.d32; ++ dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8); ++ } ++ if (status.b.sr) { ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n"); ++ /* Already started data stage, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for more setup packets */ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE || ++ pcd->ep0state == EP0_IN_DATA_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } else { ++ dwc_otg_pcd_request_t *req; ++ dev_dma_desc_sts_t status = {.d32 = 0}; ++ diepint_data_t diepint0; ++ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ ++ if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) { ++ DWC_ERROR("EP0 is stalled/disconnected\n"); ++ } ++ ++ /* Clear IN xfercompl if set */ ++ if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE ++ || pcd->ep0state == EP0_IN_DATA_PHASE)) { ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint0.d32); ++ } ++ ++ status.d32 = core_if->dev_if->setup_desc_addr[core_if-> ++ dev_if->setup_desc_index]->status.d32; ++ ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len ++ && (pcd->ep0state == EP0_OUT_DATA_PHASE)) ++ status.d32 = core_if->dev_if->out_desc_addr->status.d32; ++ if (pcd->ep0state == EP0_OUT_STATUS_PHASE) ++ status.d32 = core_if->dev_if-> ++ out_desc_addr->status.d32; ++ ++ if (status.b.sr) { ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n"); ++ } else { ++ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n"); ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && ++ pcd->ep0state == EP0_OUT_DATA_PHASE) { ++ /* Read arrived setup packet from req->buf */ ++ dwc_memcpy(&pcd->setup_pkt->req, ++ req->buf + ep->dwc_ep.xfer_count, 8); ++ } ++ req->actual = ep->dwc_ep.xfer_count; ++ dwc_otg_request_done(ep, req, -ECONNRESET); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ } ++ pcd->ep0state = EP0_IDLE; ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n"); ++ /* Data stage started, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for setup packets if ep0in was enabled*/ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes 2\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } ++ } ++ if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable ++ && core_if->dma_desc_enable == 0) { ++ doepint_data_t doepint_temp = {.d32 = 0}; ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doepint); ++ doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doeptsiz); ++ if (pcd->ep0state == EP0_IDLE) { ++ if (doepint_temp.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ } ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if (doeptsize0.b.supcnt == 3) { ++ DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n"); ++ ep->dwc_ep.stp_rollover = 1; ++ } ++ if (doepint.b.setup) { ++retry: ++ /* Already started data stage, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ ep->dwc_ep.stp_rollover = 0; ++ /* Prepare for more setup packets */ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE || ++ pcd->ep0state == EP0_IN_DATA_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_ANY, ++ "EP0_IDLE SR=1 setup=0 new setup comes\n"); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if(doepint.b.setup) ++ goto retry; ++ ep0_out_start(core_if, pcd); ++ } ++ } else { ++ dwc_otg_pcd_request_t *req; ++ diepint_data_t diepint0 = {.d32 = 0}; ++ doepint_data_t doepint_temp = {.d32 = 0}; ++ depctl_data_t diepctl0; ++ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepctl); ++ ++ if (pcd->ep0state == EP0_IN_DATA_PHASE ++ || pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ if (diepint0.b.xfercompl) { ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint0.d32); ++ } ++ if (diepctl0.b.epena) { ++ diepint_data_t diepint = {.d32 = 0}; ++ diepctl0.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepctl, diepctl0.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ } while (!diepint.b.inepnakeff); ++ diepint.b.inepnakeff = 1; ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint.d32); ++ diepctl0.d32 = 0; ++ diepctl0.b.epdis = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl, ++ diepctl0.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ } while (!diepint.b.epdisabled); ++ diepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint, ++ diepint.d32); ++ } ++ } ++ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doepint); ++ if (doepint_temp.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n"); ++ } else { ++ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n"); ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && ++ pcd->ep0state == EP0_OUT_DATA_PHASE) { ++ /* Read arrived setup packet from req->buf */ ++ dwc_memcpy(&pcd->setup_pkt->req, ++ req->buf + ep->dwc_ep.xfer_count, 8); ++ } ++ req->actual = ep->dwc_ep.xfer_count; ++ dwc_otg_request_done(ep, req, -ECONNRESET); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ } ++ pcd->ep0state = EP0_IDLE; ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n"); ++ /* Data stage started, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for setup packets if ep0in was enabled*/ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes 2\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } ++ } ++ if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE) ++ handle_ep0(pcd); ++exit_xfercompl: ++ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n", ++ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32); ++ } else { ++ if (core_if->dma_desc_enable == 0 ++ || pcd->ep0state != EP0_IDLE) ++ handle_ep0(pcd); ++ } ++#ifdef DWC_EN_ISOC ++ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (doepint.b.pktdrpsts == 0) { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, ++ epnum, ++ xfercompl); ++ complete_iso_ep(pcd, ep); ++ } else { ++ ++ doepint_data_t doepint = {.d32 = 0 }; ++ doepint.b.xfercompl = 1; ++ doepint.b.pktdrpsts = 1; ++ DWC_WRITE_REG32 ++ (&core_if->dev_if->out_ep_regs ++ [epnum]->doepint, ++ doepint.d32); ++ if (handle_iso_out_pkt_dropped ++ (core_if, dwc_ep)) { ++ complete_iso_ep(pcd, ++ ep); ++ } ++ } ++#endif /* DWC_EN_ISOC */ ++#ifdef DWC_UTE_PER_IO ++ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl); ++ if (!ep->stopped) ++ complete_xiso_ep(ep); ++#endif /* DWC_UTE_PER_IO */ ++ } else { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, ++ xfercompl); ++ ++ if (core_if->core_params->dev_out_nak) { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]); ++ pcd->core_if->ep_xfer_info[epnum].state = 0; ++#ifdef DEBUG ++ print_memory_payload(pcd, dwc_ep); ++#endif ++ } ++ complete_ep(ep); ++ } ++ ++ } ++ ++ /* Endpoint disable */ ++ if (doepint.b.epdisabled) { ++ ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled); ++ if (core_if->core_params->dev_out_nak) { ++#ifdef DEBUG ++ print_memory_payload(pcd, dwc_ep); ++#endif ++ /* In case of timeout condition */ ++ if (core_if->ep_xfer_info[epnum].state == 2) { ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ /* Unmask goutnakeff interrupt which was masked ++ * during handle nak out interrupt */ ++ gintmsk.b.goutnakeff = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ 0, gintmsk.d32); ++ ++ complete_ep(ep); ++ } ++ } ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ dctl_data_t dctl; ++ gintmsk_data_t intr_mask = {.d32 = 0}; ++ dwc_otg_pcd_request_t *req = 0; ++ ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ ++ intr_mask.d32 = 0; ++ intr_mask.b.incomplisoout = 1; ++ ++ /* Get any pending requests */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ } else { ++ dwc_otg_request_done(ep, req, 0); ++ start_next_request(ep); ++ } ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ } ++ } ++ } ++ /* AHB Error */ ++ if (doepint.b.ahberr) { ++ DWC_ERROR("EP%d OUT AHB Error\n", epnum); ++ DWC_ERROR("EP%d DEPDMA=0x%08x \n", ++ epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma); ++ CLEAR_OUT_EP_INTR(core_if, epnum, ahberr); ++ } ++ /* Setup Phase Done (contorl EPs) */ ++ if (doepint.b.setup) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum); ++#endif ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ ++ handle_ep0(pcd); ++ } ++ ++ /** OUT EP BNA Intr */ ++ if (doepint.b.bna) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, bna); ++ if (core_if->dma_desc_enable) { ++#ifdef DWC_EN_ISOC ++ if (dwc_ep->type == ++ DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This checking is performed to prevent first "false" BNA ++ * handling occuring right after reconnect ++ */ ++ if (dwc_ep->next_frame != ++ 0xffffffff) ++ dwc_otg_pcd_handle_iso_bna(ep); ++ } else ++#endif /* DWC_EN_ISOC */ ++ { ++ dwc_otg_pcd_handle_noniso_bna(ep); ++ } ++ } ++ } ++ /* Babble Interrupt */ ++ if (doepint.b.babble) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n", ++ epnum); ++ handle_out_ep_babble_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, babble); ++ } ++ if (doepint.b.outtknepdis) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \ ++ disabled\n",epnum); ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ doepmsk_data_t doepmsk = {.d32 = 0}; ++ ep->dwc_ep.frame_num = core_if->frame_num; ++ if (ep->dwc_ep.bInterval > 1) { ++ depctl_data_t depctl; ++ depctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[epnum]->doepctl); ++ if (ep->dwc_ep.frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ depctl.b.setd0pid = 0; ++ } else { ++ depctl.b.setd0pid = 1; ++ depctl.b.setd1pid = 0; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[epnum]->doepctl, depctl.d32); ++ } ++ start_next_request(ep); ++ doepmsk.b.outtknepdis = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ doepmsk.d32, 0); ++ } ++ CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis); ++ } ++ ++ /* NAK Interrutp */ ++ if (doepint.b.nak) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum); ++ handle_out_ep_nak_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, nak); ++ } ++ /* NYET Interrutp */ ++ if (doepint.b.nyet) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum); ++ handle_out_ep_nyet_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, nyet); ++ } ++ } ++ ++ epnum++; ++ ep_intr >>= 1; ++ } ++ ++ return 1; ++ ++#undef CLEAR_OUT_EP_INTR ++} ++static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun) ++{ ++ int retval = 0; ++ if(!frm_overrun && curr_fr >= trgt_fr) ++ retval = 1; ++ else if (frm_overrun ++ && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2))) ++ retval = 1; ++ return retval; ++} ++/** ++ * Incomplete ISO IN Transfer Interrupt. ++ * This interrupt indicates one of the following conditions occurred ++ * while transmitting an ISOC transaction. ++ * - Corrupted IN Token for ISOC EP. ++ * - Packet not complete in FIFO. ++ * The follow actions will be taken: ++ * -# Determine the EP ++ * -# Set incomplete flag in dwc_ep structure ++ * -# Disable EP; when "Endpoint Disabled" interrupt is received ++ * Flush FIFO ++ */ ++int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++ ++#ifdef DWC_EN_ISOC ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ int i; ++ ++ dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ for (i = 1; i <= dev_if->num_in_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i].dwc_ep; ++ if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ ++ if (depctl.b.epdis && deptsiz.d32) { ++ set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ ++ dsts.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts); ++ dwc_ep->next_frame = dsts.b.soffn; ++ ++ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF ++ (pcd), ++ dwc_ep); ++ } ++ } ++ } ++ ++#else ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ dwc_otg_dev_if_t *dev_if; ++ int i; ++ dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n"); ++ ++ for (i = 1; i <= dev_if->num_in_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i-1].dwc_ep; ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num, ++ dwc_ep->frm_overrun)) ++ { ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ depctl.b.snak = 1; ++ depctl.b.epdis = 1; ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32); ++ } ++ } ++ } ++ ++ /*intr_mask.b.incomplisoin = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); */ ++#endif //DWC_EN_ISOC ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.incomplisoin = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * Incomplete ISO OUT Transfer Interrupt. ++ * ++ * This interrupt indicates that the core has dropped an ISO OUT ++ * packet. The following conditions can be the cause: ++ * - FIFO Full, the entire packet would not fit in the FIFO. ++ * - CRC Error ++ * - Corrupted Token ++ * The follow actions will be taken: ++ * -# Determine the EP ++ * -# Set incomplete flag in dwc_ep structure ++ * -# Read any data from the FIFO ++ * -# Disable EP. When "Endpoint Disabled" interrupt is received ++ * re-enable EP. ++ */ ++int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd) ++{ ++ ++ gintsts_data_t gintsts; ++ ++#ifdef DWC_EN_ISOC ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ int i; ++ ++ dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ for (i = 1; i <= dev_if->num_out_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i].dwc_ep; ++ if (pcd->out_ep[i].dwc_ep.active && ++ pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz); ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); ++ ++ if (depctl.b.epdis && deptsiz.d32) { ++ set_current_pkt_info(GET_CORE_IF(pcd), ++ &pcd->out_ep[i].dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ ++ dsts.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts); ++ dwc_ep->next_frame = dsts.b.soffn; ++ ++ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF ++ (pcd), ++ dwc_ep); ++ } ++ } ++ } ++#else ++ /** @todo implement ISR */ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep = NULL; ++ int i; ++ core_if = GET_CORE_IF(pcd); ++ ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ dwc_ep = &pcd->out_ep[i].dwc_ep; ++ depctl.d32 = ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl); ++ if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) { ++ core_if->dev_if->isoc_ep = dwc_ep; ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz); ++ break; ++ } ++ } ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ ++ if (!intr_mask.b.goutnakeff) { ++ /* Unmask it */ ++ intr_mask.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32); ++ } ++ if (!gintsts.b.goutnakeff) { ++ dctl.b.sgoutnak = 1; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ ++ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl); ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32); ++ ++ intr_mask.d32 = 0; ++ intr_mask.b.incomplisoout = 1; ++ ++#endif /* DWC_EN_ISOC */ ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.incomplisoout = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function handles the Global IN NAK Effective interrupt. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ depctl_data_t diepctl = {.d32 = 0 }; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ int i; ++ ++ DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n"); ++ ++ /* Disable all active IN EPs */ ++ for (i = 0; i <= dev_if->num_in_eps; i++) { ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (!(diepctl.b.eptype & 1) && diepctl.b.epena) { ++ if (core_if->start_predict > 0) ++ core_if->start_predict++; ++ diepctl.b.epdis = 1; ++ diepctl.b.snak = 1; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32); ++ } ++ } ++ ++ ++ /* Disable the Global IN NAK Effective Interrupt */ ++ intr_mask.b.ginnakeff = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.ginnakeff = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * OUT NAK Effective. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ depctl_data_t doepctl; ++ int i; ++ ++ /* Disable the Global OUT NAK Effective Interrupt */ ++ intr_mask.b.goutnakeff = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* If DEV OUT NAK enabled*/ ++ if (pcd->core_if->core_params->dev_out_nak) { ++ /* Run over all out endpoints to determine the ep number on ++ * which the timeout has happened ++ */ ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ if ( pcd->core_if->ep_xfer_info[i].state == 2 ) ++ break; ++ } ++ if (i > dev_if->num_out_eps) { ++ dctl_data_t dctl; ++ dctl.d32 = ++ DWC_READ_REG32(&dev_if->dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ goto out; ++ } ++ ++ /* Disable the endpoint */ ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); ++ if (doepctl.b.epena) { ++ doepctl.b.epdis = 1; ++ doepctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); ++ return 1; ++ } ++ /* We come here from Incomplete ISO OUT handler */ ++ if (dev_if->isoc_ep) { ++ dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep; ++ uint32_t epnum = dwc_ep->num; ++ doepint_data_t doepint; ++ doepint.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint); ++ dev_if->isoc_ep = NULL; ++ doepctl.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl); ++ DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32); ++ if (doepctl.b.epena) { ++ doepctl.b.epdis = 1; ++ doepctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl, ++ doepctl.d32); ++ return 1; ++ } else ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "Global OUT NAK Effective\n"); ++ ++out: ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * PCD interrupt handler. ++ * ++ * The PCD handles the device interrupts. Many conditions can cause a ++ * device interrupt. When an interrupt occurs, the device interrupt ++ * service routine determines the cause of the interrupt and ++ * dispatches handling to the appropriate function. These interrupt ++ * handling functions are described below. ++ * ++ * All interrupt registers are processed from LSB to MSB. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++#ifdef VERBOSE ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++#endif ++ gintsts_data_t gintr_status; ++ int32_t retval = 0; ++ ++ /* Exit from ISR if core is hibernated */ ++ if (core_if->hibernation_suspend == 1) { ++ return retval; ++ } ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n", ++ __func__, ++ DWC_READ_REG32(&global_regs->gintsts), ++ DWC_READ_REG32(&global_regs->gintmsk)); ++#endif ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_SPINLOCK(pcd->lock); ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n", ++ __func__, ++ DWC_READ_REG32(&global_regs->gintsts), ++ DWC_READ_REG32(&global_regs->gintmsk)); ++#endif ++ ++ gintr_status.d32 = dwc_otg_read_core_intr(core_if); ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n", ++ __func__, gintr_status.d32); ++ ++ if (gintr_status.b.sofintr) { ++ retval |= dwc_otg_pcd_handle_sof_intr(pcd); ++ } ++ if (gintr_status.b.rxstsqlvl) { ++ retval |= ++ dwc_otg_pcd_handle_rx_status_q_level_intr(pcd); ++ } ++ if (gintr_status.b.nptxfempty) { ++ retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd); ++ } ++ if (gintr_status.b.goutnakeff) { ++ retval |= dwc_otg_pcd_handle_out_nak_effective(pcd); ++ } ++ if (gintr_status.b.i2cintr) { ++ retval |= dwc_otg_pcd_handle_i2c_intr(pcd); ++ } ++ if (gintr_status.b.erlysuspend) { ++ retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd); ++ } ++ if (gintr_status.b.usbreset) { ++ retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd); ++ } ++ if (gintr_status.b.enumdone) { ++ retval |= dwc_otg_pcd_handle_enum_done_intr(pcd); ++ } ++ if (gintr_status.b.isooutdrop) { ++ retval |= ++ dwc_otg_pcd_handle_isoc_out_packet_dropped_intr ++ (pcd); ++ } ++ if (gintr_status.b.eopframe) { ++ retval |= ++ dwc_otg_pcd_handle_end_periodic_frame_intr(pcd); ++ } ++ if (gintr_status.b.inepint) { ++ if (!core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); ++ } ++ } ++ if (gintr_status.b.outepintr) { ++ if (!core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); ++ } ++ } ++ if (gintr_status.b.epmismatch) { ++ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd); ++ } ++ if (gintr_status.b.fetsusp) { ++ retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd); ++ } ++ if (gintr_status.b.ginnakeff) { ++ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd); ++ } ++ if (gintr_status.b.incomplisoin) { ++ retval |= ++ dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd); ++ } ++ if (gintr_status.b.incomplisoout) { ++ retval |= ++ dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd); ++ } ++ ++ /* In MPI mode Device Endpoints interrupts are asserted ++ * without setting outepintr and inepint bits set, so these ++ * Interrupt handlers are called without checking these bit-fields ++ */ ++ if (core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); ++ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); ++ } ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__, ++ DWC_READ_REG32(&global_regs->gintsts)); ++#endif ++ DWC_SPINUNLOCK(pcd->lock); ++ } ++ return retval; ++} ++ ++#endif /* DWC_HOST_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c +@@ -0,0 +1,1360 @@ ++ /* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $ ++ * $Revision: #21 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++/** @file ++ * This file implements the Peripheral Controller Driver. ++ * ++ * The Peripheral Controller Driver (PCD) is responsible for ++ * translating requests from the Function Driver into the appropriate ++ * actions on the DWC_otg controller. It isolates the Function Driver ++ * from the specifics of the controller by providing an API to the ++ * Function Driver. ++ * ++ * The Peripheral Controller Driver for Linux will implement the ++ * Gadget API, so that the existing Gadget drivers can be used. ++ * (Gadget Driver is the Linux terminology for a Function Driver.) ++ * ++ * The Linux Gadget API is defined in the header file ++ * . The USB EP operations API is ++ * defined in the structure usb_ep_ops and the USB ++ * Controller API is defined in the structure ++ * usb_gadget_ops. ++ * ++ */ ++ ++#include "dwc_otg_os_dep.h" ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_pcd.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_dbg.h" ++ ++extern bool fiq_enable; ++ ++static struct gadget_wrapper { ++ dwc_otg_pcd_t *pcd; ++ ++ struct usb_gadget gadget; ++ struct usb_gadget_driver *driver; ++ ++ struct usb_ep ep0; ++ struct usb_ep in_ep[16]; ++ struct usb_ep out_ep[16]; ++ ++} *gadget_wrapper; ++ ++/* Display the contents of the buffer */ ++extern void dump_msg(const u8 * buf, unsigned int length); ++/** ++ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case ++ * if the endpoint is not found ++ */ ++static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) ++{ ++ int i; ++ if (pcd->ep0.priv == handle) { ++ return &pcd->ep0; ++ } ++ ++ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) { ++ if (pcd->in_ep[i].priv == handle) ++ return &pcd->in_ep[i]; ++ if (pcd->out_ep[i].priv == handle) ++ return &pcd->out_ep[i]; ++ } ++ ++ return NULL; ++} ++ ++/* USB Endpoint Operations */ ++/* ++ * The following sections briefly describe the behavior of the Gadget ++ * API endpoint operations implemented in the DWC_otg driver ++ * software. Detailed descriptions of the generic behavior of each of ++ * these functions can be found in the Linux header file ++ * include/linux/usb_gadget.h. ++ * ++ * The Gadget API provides wrapper functions for each of the function ++ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper ++ * function, which then calls the underlying PCD function. The ++ * following sections are named according to the wrapper ++ * functions. Within each section, the corresponding DWC_otg PCD ++ * function name is specified. ++ * ++ */ ++ ++/** ++ * This function is called by the Gadget Driver for each EP to be ++ * configured for the current configuration (SET_CONFIGURATION). ++ * ++ * This function initializes the dwc_otg_ep_t data structure, and then ++ * calls dwc_otg_ep_activate. ++ */ ++static int ep_enable(struct usb_ep *usb_ep, ++ const struct usb_endpoint_descriptor *ep_desc) ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc); ++ ++ if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) { ++ DWC_WARN("%s, bad ep or descriptor\n", __func__); ++ return -EINVAL; ++ } ++ if (usb_ep == &gadget_wrapper->ep0) { ++ DWC_WARN("%s, bad ep(0)\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* Check FIFO size? */ ++ if (!ep_desc->wMaxPacketSize) { ++ DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name); ++ return -ERANGE; ++ } ++ ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_WARN("%s, bogus device state\n", __func__); ++ return -ESHUTDOWN; ++ } ++ ++ /* Delete after check - MAS */ ++#if 0 ++ nat = (uint32_t) ep_desc->wMaxPacketSize; ++ printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat); ++ nat = (nat >> 11) & 0x03; ++ printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat); ++#endif ++ retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd, ++ (const uint8_t *)ep_desc, ++ (void *)usb_ep); ++ if (retval) { ++ DWC_WARN("dwc_otg_pcd_ep_enable failed\n"); ++ return -EINVAL; ++ } ++ ++ usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize); ++ ++ return 0; ++} ++ ++/** ++ * This function is called when an EP is disabled due to disconnect or ++ * change in configuration. Any pending requests will terminate with a ++ * status of -ESHUTDOWN. ++ * ++ * This function modifies the dwc_otg_ep_t data structure for this EP, ++ * and then calls dwc_otg_ep_deactivate. ++ */ ++static int ep_disable(struct usb_ep *usb_ep) ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep); ++ if (!usb_ep) { ++ DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__, ++ usb_ep ? usb_ep->name : NULL); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep); ++ if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function allocates a request object to use with the specified ++ * endpoint. ++ * ++ * @param ep The endpoint to be used with with the request ++ * @param gfp_flags the GFP_* flags to use. ++ */ ++static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep, ++ gfp_t gfp_flags) ++{ ++ struct usb_request *usb_req; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags); ++ if (0 == ep) { ++ DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n"); ++ return 0; ++ } ++ usb_req = kmalloc(sizeof(*usb_req), gfp_flags); ++ if (0 == usb_req) { ++ DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n"); ++ return 0; ++ } ++ memset(usb_req, 0, sizeof(*usb_req)); ++ usb_req->dma = DWC_DMA_ADDR_INVALID; ++ ++ return usb_req; ++} ++ ++/** ++ * This function frees a request object. ++ * ++ * @param ep The endpoint associated with the request ++ * @param req The request being freed ++ */ ++static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req); ++ ++ if (0 == ep || 0 == req) { ++ DWC_WARN("%s() %s\n", __func__, ++ "Invalid ep or req argument!\n"); ++ return; ++ } ++ ++ kfree(req); ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++/** ++ * This function allocates an I/O buffer to be used for a transfer ++ * to/from the specified endpoint. ++ * ++ * @param usb_ep The endpoint to be used with with the request ++ * @param bytes The desired number of bytes for the buffer ++ * @param dma Pointer to the buffer's DMA address; must be valid ++ * @param gfp_flags the GFP_* flags to use. ++ * @return address of a new buffer or null is buffer could not be allocated. ++ */ ++static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes, ++ dma_addr_t * dma, gfp_t gfp_flags) ++{ ++ void *buf; ++ dwc_otg_pcd_t *pcd = 0; ++ ++ pcd = gadget_wrapper->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes, ++ dma, gfp_flags); ++ ++ /* Check dword alignment */ ++ if ((bytes & 0x3UL) != 0) { ++ DWC_WARN("%s() Buffer size is not a multiple of" ++ "DWORD size (%d)", __func__, bytes); ++ } ++ ++ buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags); ++ ++ /* Check dword alignment */ ++ if (((int)buf & 0x3UL) != 0) { ++ DWC_WARN("%s() Buffer is not DWORD aligned (%p)", ++ __func__, buf); ++ } ++ ++ return buf; ++} ++ ++/** ++ * This function frees an I/O buffer that was allocated by alloc_buffer. ++ * ++ * @param usb_ep the endpoint associated with the buffer ++ * @param buf address of the buffer ++ * @param dma The buffer's DMA address ++ * @param bytes The number of bytes of the buffer ++ */ ++static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf, ++ dma_addr_t dma, unsigned bytes) ++{ ++ dwc_otg_pcd_t *pcd = 0; ++ ++ pcd = gadget_wrapper->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes); ++ ++ dma_free_coherent(NULL, bytes, buf, dma); ++} ++#endif ++ ++/** ++ * This function is used to submit an I/O Request to an EP. ++ * ++ * - When the request completes the request's completion callback ++ * is called to return the request to the driver. ++ * - An EP, except control EPs, may have multiple requests ++ * pending. ++ * - Once submitted the request cannot be examined or modified. ++ * - Each request is turned into one or more packets. ++ * - A BULK EP can queue any amount of data; the transfer is ++ * packetized. ++ * - Zero length Packets are specified with the request 'zero' ++ * flag. ++ */ ++static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req, ++ gfp_t gfp_flags) ++{ ++ dwc_otg_pcd_t *pcd; ++ struct dwc_otg_pcd_ep *ep = NULL; ++ int retval = 0, is_isoc_ep = 0; ++ dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n", ++ __func__, usb_ep, usb_req, gfp_flags); ++ ++ if (!usb_req || !usb_req->complete || !usb_req->buf) { ++ DWC_WARN("bad params\n"); ++ return -EINVAL; ++ } ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ pcd = gadget_wrapper->pcd; ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", ++ gadget_wrapper->gadget.speed); ++ DWC_WARN("bogus device state\n"); ++ return -ESHUTDOWN; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n", ++ usb_ep->name, usb_req, usb_req->length, usb_req->buf); ++ ++ usb_req->status = -EINPROGRESS; ++ usb_req->actual = 0; ++ ++ ep = ep_from_handle(pcd, usb_ep); ++ if (ep == NULL) ++ is_isoc_ep = 0; ++ else ++ is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ dma_addr = usb_req->dma; ++#else ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev; ++ struct device *dev = NULL; ++ ++ if (otg_dev != NULL) ++ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep); ++ ++ if (usb_req->length != 0 && ++ usb_req->dma == DWC_DMA_ADDR_INVALID) { ++ dma_addr = dma_map_single(dev, usb_req->buf, ++ usb_req->length, ++ ep->dwc_ep.is_in ? ++ DMA_TO_DEVICE: ++ DMA_FROM_DEVICE); ++ } ++ } ++#endif ++ ++#ifdef DWC_UTE_PER_IO ++ if (is_isoc_ep == 1) { ++ retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr, ++ usb_req->length, usb_req->zero, usb_req, ++ gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req); ++ if (retval) ++ return -EINVAL; ++ ++ return 0; ++ } ++#endif ++ retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr, ++ usb_req->length, usb_req->zero, usb_req, ++ gfp_flags == GFP_ATOMIC ? 1 : 0); ++ if (retval) { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/** ++ * This function cancels an I/O request from an EP. ++ */ ++static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req); ++ ++ if (!usb_ep || !usb_req) { ++ DWC_WARN("bad argument\n"); ++ return -EINVAL; ++ } ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_WARN("bogus device state\n"); ++ return -ESHUTDOWN; ++ } ++ if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/** ++ * usb_ep_set_halt stalls an endpoint. ++ * ++ * usb_ep_clear_halt clears an endpoint halt and resets its data ++ * toggle. ++ * ++ * Both of these functions are implemented with the same underlying ++ * function. The behavior depends on the value argument. ++ * ++ * @param[in] usb_ep the Endpoint to halt or clear halt. ++ * @param[in] value ++ * - 0 means clear_halt. ++ * - 1 means set_halt, ++ * - 2 means clear stall lock flag. ++ * - 3 means set stall lock flag. ++ */ ++static int ep_halt(struct usb_ep *usb_ep, int value) ++{ ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value); ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value); ++ if (retval == -DWC_E_AGAIN) { ++ return -EAGAIN; ++ } else if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++#if 0 ++/** ++ * ep_wedge: sets the halt feature and ignores clear requests ++ * ++ * @usb_ep: the endpoint being wedged ++ * ++ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) ++ * requests. If the gadget driver clears the halt status, it will ++ * automatically unwedge the endpoint. ++ * ++ * Returns zero on success, else negative errno. * ++ * Check usb_ep_set_wedge() at "usb_gadget.h" for details ++ */ ++static int ep_wedge(struct usb_ep *usb_ep) ++{ ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name); ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep); ++ if (retval == -DWC_E_AGAIN) { ++ retval = -EAGAIN; ++ } else if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++#endif ++ ++#ifdef DWC_EN_ISOC ++/** ++ * This function is used to submit an ISOC Transfer Request to an EP. ++ * ++ * - Every time a sync period completes the request's completion callback ++ * is called to provide data to the gadget driver. ++ * - Once submitted the request cannot be modified. ++ * - Each request is turned into periodic data packets untill ISO ++ * Transfer is stopped.. ++ */ ++static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req, ++ gfp_t gfp_flags) ++{ ++ int retval = 0; ++ ++ if (!req || !req->process_buffer || !req->buf0 || !req->buf1) { ++ DWC_WARN("bad params\n"); ++ return -EINVAL; ++ } ++ ++ if (!usb_ep) { ++ DWC_PRINTF("bad params\n"); ++ return -EINVAL; ++ } ++ ++ req->status = -EINPROGRESS; ++ ++ retval = ++ dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0, ++ req->buf1, req->dma0, req->dma1, ++ req->sync_frame, req->data_pattern_frame, ++ req->data_per_frame, ++ req-> ++ flags & USB_REQ_ISO_ASAP ? -1 : ++ req->start_frame, req->buf_proc_intrvl, ++ req, gfp_flags == GFP_ATOMIC ? 1 : 0); ++ ++ if (retval) { ++ return -EINVAL; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function stops ISO EP Periodic Data Transfer. ++ */ ++static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req) ++{ ++ int retval = 0; ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ } ++ ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", ++ gadget_wrapper->gadget.speed); ++ DWC_WARN("bogus device state\n"); ++ } ++ ++ dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req); ++ if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep, ++ int packets, gfp_t gfp_flags) ++{ ++ struct usb_iso_request *pReq = NULL; ++ uint32_t req_size; ++ ++ req_size = sizeof(struct usb_iso_request); ++ req_size += ++ (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor))); ++ ++ pReq = kmalloc(req_size, gfp_flags); ++ if (!pReq) { ++ DWC_WARN("Can't allocate Iso Request\n"); ++ return 0; ++ } ++ pReq->iso_packet_desc0 = (void *)(pReq + 1); ++ ++ pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets; ++ ++ return pReq; ++} ++ ++static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req) ++{ ++ kfree(req); ++} ++ ++static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = { ++ .ep_ops = { ++ .enable = ep_enable, ++ .disable = ep_disable, ++ ++ .alloc_request = dwc_otg_pcd_alloc_request, ++ .free_request = dwc_otg_pcd_free_request, ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ .alloc_buffer = dwc_otg_pcd_alloc_buffer, ++ .free_buffer = dwc_otg_pcd_free_buffer, ++#endif ++ ++ .queue = ep_queue, ++ .dequeue = ep_dequeue, ++ ++ .set_halt = ep_halt, ++ .fifo_status = 0, ++ .fifo_flush = 0, ++ }, ++ .iso_ep_start = iso_ep_start, ++ .iso_ep_stop = iso_ep_stop, ++ .alloc_iso_request = alloc_iso_request, ++ .free_iso_request = free_iso_request, ++}; ++ ++#else ++ ++ int (*enable) (struct usb_ep *ep, ++ const struct usb_endpoint_descriptor *desc); ++ int (*disable) (struct usb_ep *ep); ++ ++ struct usb_request *(*alloc_request) (struct usb_ep *ep, ++ gfp_t gfp_flags); ++ void (*free_request) (struct usb_ep *ep, struct usb_request *req); ++ ++ int (*queue) (struct usb_ep *ep, struct usb_request *req, ++ gfp_t gfp_flags); ++ int (*dequeue) (struct usb_ep *ep, struct usb_request *req); ++ ++ int (*set_halt) (struct usb_ep *ep, int value); ++ int (*set_wedge) (struct usb_ep *ep); ++ ++ int (*fifo_status) (struct usb_ep *ep); ++ void (*fifo_flush) (struct usb_ep *ep); ++static struct usb_ep_ops dwc_otg_pcd_ep_ops = { ++ .enable = ep_enable, ++ .disable = ep_disable, ++ ++ .alloc_request = dwc_otg_pcd_alloc_request, ++ .free_request = dwc_otg_pcd_free_request, ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ .alloc_buffer = dwc_otg_pcd_alloc_buffer, ++ .free_buffer = dwc_otg_pcd_free_buffer, ++#else ++ /* .set_wedge = ep_wedge, */ ++ .set_wedge = NULL, /* uses set_halt instead */ ++#endif ++ ++ .queue = ep_queue, ++ .dequeue = ep_dequeue, ++ ++ .set_halt = ep_halt, ++ .fifo_status = 0, ++ .fifo_flush = 0, ++ ++}; ++ ++#endif /* _EN_ISOC_ */ ++/* Gadget Operations */ ++/** ++ * The following gadget operations will be implemented in the DWC_otg ++ * PCD. Functions in the API that are not described below are not ++ * implemented. ++ * ++ * The Gadget API provides wrapper functions for each of the function ++ * pointers defined in usb_gadget_ops. The Gadget Driver calls the ++ * wrapper function, which then calls the underlying PCD function. The ++ * following sections are named according to the wrapper functions ++ * (except for ioctl, which doesn't have a wrapper function). Within ++ * each section, the corresponding DWC_otg PCD function name is ++ * specified. ++ * ++ */ ++ ++/** ++ *Gets the USB Frame number of the last SOF. ++ */ ++static int get_frame_number(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget); ++ ++ if (gadget == 0) { ++ return -ENODEV; ++ } ++ ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ return dwc_otg_pcd_get_frame_number(d->pcd); ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++static int test_lpm_enabled(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ ++ return dwc_otg_pcd_is_lpm_enabled(d->pcd); ++} ++#endif ++ ++/** ++ * Initiates Session Request Protocol (SRP) to wakeup the host if no ++ * session is in progress. If a session is already in progress, but ++ * the device is suspended, remote wakeup signaling is started. ++ * ++ */ ++static int wakeup(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget); ++ ++ if (gadget == 0) { ++ return -ENODEV; ++ } else { ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ } ++ dwc_otg_pcd_wakeup(d->pcd); ++ return 0; ++} ++ ++static const struct usb_gadget_ops dwc_otg_pcd_ops = { ++ .get_frame = get_frame_number, ++ .wakeup = wakeup, ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ .lpm_support = test_lpm_enabled, ++#endif ++ // current versions must always be self-powered ++}; ++ ++static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ if (gadget_wrapper->driver && gadget_wrapper->driver->setup) { ++ retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget, ++ (struct usb_ctrlrequest ++ *)bytes); ++ } ++ ++ if (retval == -ENOTSUPP) { ++ retval = -DWC_E_NOT_SUPPORTED; ++ } else if (retval < 0) { ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++#ifdef DWC_EN_ISOC ++static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int proc_buf_num) ++{ ++ int i, packet_count; ++ struct usb_gadget_iso_packet_descriptor *iso_packet = 0; ++ struct usb_iso_request *iso_req = req_handle; ++ ++ if (proc_buf_num) { ++ iso_packet = iso_req->iso_packet_desc1; ++ } else { ++ iso_packet = iso_req->iso_packet_desc0; ++ } ++ packet_count = ++ dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle); ++ for (i = 0; i < packet_count; ++i) { ++ int status; ++ int actual; ++ int offset; ++ dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle, ++ i, &status, &actual, &offset); ++ switch (status) { ++ case -DWC_E_NO_DATA: ++ status = -ENODATA; ++ break; ++ default: ++ if (status) { ++ DWC_PRINTF("unknown status in isoc packet\n"); ++ } ++ ++ } ++ iso_packet[i].status = status; ++ iso_packet[i].offset = offset; ++ iso_packet[i].actual_length = actual; ++ } ++ ++ iso_req->status = 0; ++ iso_req->process_buffer(ep_handle, iso_req); ++ ++ return 0; ++} ++#endif /* DWC_EN_ISOC */ ++ ++#ifdef DWC_UTE_PER_IO ++/** ++ * Copy the contents of the extended request to the Linux usb_request's ++ * extended part and call the gadget's completion. ++ * ++ * @param pcd Pointer to the pcd structure ++ * @param ep_handle Void pointer to the usb_ep structure ++ * @param req_handle Void pointer to the usb_request structure ++ * @param status Request status returned from the portable logic ++ * @param ereq_port Void pointer to the extended request structure ++ * created in the the portable part that contains the ++ * results of the processed iso packets. ++ */ ++static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, void *ereq_port) ++{ ++ struct dwc_ute_iso_req_ext *ereqorg = NULL; ++ struct dwc_iso_xreq_port *ereqport = NULL; ++ struct dwc_ute_iso_packet_descriptor *desc_org = NULL; ++ int i; ++ struct usb_request *req; ++ //struct dwc_ute_iso_packet_descriptor * ++ //int status = 0; ++ ++ req = (struct usb_request *)req_handle; ++ ereqorg = &req->ext_req; ++ ereqport = (struct dwc_iso_xreq_port *)ereq_port; ++ desc_org = ereqorg->per_io_frame_descs; ++ ++ if (req && req->complete) { ++ /* Copy the request data from the portable logic to our request */ ++ for (i = 0; i < ereqport->pio_pkt_count; i++) { ++ desc_org[i].actual_length = ++ ereqport->per_io_frame_descs[i].actual_length; ++ desc_org[i].status = ++ ereqport->per_io_frame_descs[i].status; ++ } ++ ++ switch (status) { ++ case -DWC_E_SHUTDOWN: ++ req->status = -ESHUTDOWN; ++ break; ++ case -DWC_E_RESTART: ++ req->status = -ECONNRESET; ++ break; ++ case -DWC_E_INVALID: ++ req->status = -EINVAL; ++ break; ++ case -DWC_E_TIMEOUT: ++ req->status = -ETIMEDOUT; ++ break; ++ default: ++ req->status = status; ++ } ++ ++ /* And call the gadget's completion */ ++ req->complete(ep_handle, req); ++ } ++ ++ return 0; ++} ++#endif /* DWC_UTE_PER_IO */ ++ ++static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, uint32_t actual) ++{ ++ struct usb_request *req = (struct usb_request *)req_handle; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27) ++ struct dwc_otg_pcd_ep *ep = NULL; ++#endif ++ ++ if (req && req->complete) { ++ switch (status) { ++ case -DWC_E_SHUTDOWN: ++ req->status = -ESHUTDOWN; ++ break; ++ case -DWC_E_RESTART: ++ req->status = -ECONNRESET; ++ break; ++ case -DWC_E_INVALID: ++ req->status = -EINVAL; ++ break; ++ case -DWC_E_TIMEOUT: ++ req->status = -ETIMEDOUT; ++ break; ++ default: ++ req->status = status; ++ ++ } ++ ++ req->actual = actual; ++ DWC_SPINUNLOCK(pcd->lock); ++ req->complete(ep_handle, req); ++ DWC_SPINLOCK(pcd->lock); ++ } ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27) ++ ep = ep_from_handle(pcd, ep_handle); ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ if (req->length != 0) { ++ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev; ++ struct device *dev = NULL; ++ ++ if (otg_dev != NULL) ++ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep); ++ ++ dma_unmap_single(dev, req->dma, req->length, ++ ep->dwc_ep.is_in ? ++ DMA_TO_DEVICE: DMA_FROM_DEVICE); ++ } ++ } ++#endif ++ ++ return 0; ++} ++ ++static int _connect(dwc_otg_pcd_t * pcd, int speed) ++{ ++ gadget_wrapper->gadget.speed = speed; ++ return 0; ++} ++ ++static int _disconnect(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) { ++ gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget); ++ } ++ return 0; ++} ++ ++static int _resume(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->resume) { ++ gadget_wrapper->driver->resume(&gadget_wrapper->gadget); ++ } ++ ++ return 0; ++} ++ ++static int _suspend(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) { ++ gadget_wrapper->driver->suspend(&gadget_wrapper->gadget); ++ } ++ return 0; ++} ++ ++/** ++ * This function updates the otg values in the gadget structure. ++ */ ++static int _hnp_changed(dwc_otg_pcd_t * pcd) ++{ ++ ++ if (!gadget_wrapper->gadget.is_otg) ++ return 0; ++ ++ gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd); ++ gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd); ++ gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd); ++ return 0; ++} ++ ++static int _reset(dwc_otg_pcd_t * pcd) ++{ ++ return 0; ++} ++ ++#ifdef DWC_UTE_CFI ++static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req) ++{ ++ int retval = -DWC_E_INVALID; ++ if (gadget_wrapper->driver->cfi_feature_setup) { ++ retval = ++ gadget_wrapper->driver-> ++ cfi_feature_setup(&gadget_wrapper->gadget, ++ (struct cfi_usb_ctrlrequest *)cfi_req); ++ } ++ ++ return retval; ++} ++#endif ++ ++static const struct dwc_otg_pcd_function_ops fops = { ++ .complete = _complete, ++#ifdef DWC_EN_ISOC ++ .isoc_complete = _isoc_complete, ++#endif ++ .setup = _setup, ++ .disconnect = _disconnect, ++ .connect = _connect, ++ .resume = _resume, ++ .suspend = _suspend, ++ .hnp_changed = _hnp_changed, ++ .reset = _reset, ++#ifdef DWC_UTE_CFI ++ .cfi_setup = _cfi_setup, ++#endif ++#ifdef DWC_UTE_PER_IO ++ .xisoc_complete = _xisoc_complete, ++#endif ++}; ++ ++/** ++ * This function is the top level PCD interrupt handler. ++ */ ++static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev) ++{ ++ dwc_otg_pcd_t *pcd = dev; ++ int32_t retval = IRQ_NONE; ++ ++ retval = dwc_otg_pcd_handle_intr(pcd); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** ++ * This function initialized the usb_ep structures to there default ++ * state. ++ * ++ * @param d Pointer on gadget_wrapper. ++ */ ++void gadget_add_eps(struct gadget_wrapper *d) ++{ ++ static const char *names[] = { ++ ++ "ep0", ++ "ep1in", ++ "ep2in", ++ "ep3in", ++ "ep4in", ++ "ep5in", ++ "ep6in", ++ "ep7in", ++ "ep8in", ++ "ep9in", ++ "ep10in", ++ "ep11in", ++ "ep12in", ++ "ep13in", ++ "ep14in", ++ "ep15in", ++ "ep1out", ++ "ep2out", ++ "ep3out", ++ "ep4out", ++ "ep5out", ++ "ep6out", ++ "ep7out", ++ "ep8out", ++ "ep9out", ++ "ep10out", ++ "ep11out", ++ "ep12out", ++ "ep13out", ++ "ep14out", ++ "ep15out" ++ }; ++ ++ int i; ++ struct usb_ep *ep; ++ int8_t dev_endpoints; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__); ++ ++ INIT_LIST_HEAD(&d->gadget.ep_list); ++ d->gadget.ep0 = &d->ep0; ++ d->gadget.speed = USB_SPEED_UNKNOWN; ++ ++ INIT_LIST_HEAD(&d->gadget.ep0->ep_list); ++ ++ /** ++ * Initialize the EP0 structure. ++ */ ++ ep = &d->ep0; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[0]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ dwc_otg_pcd_ep_enable(d->pcd, NULL, ep); ++ ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ ++ /** ++ * Initialize the EP structures. ++ */ ++ dev_endpoints = d->pcd->core_if->dev_if->num_in_eps; ++ ++ for (i = 0; i < dev_endpoints; i++) { ++ ep = &d->in_ep[i]; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[d->pcd->in_ep[i].dwc_ep.num]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ } ++ ++ dev_endpoints = d->pcd->core_if->dev_if->num_out_eps; ++ ++ for (i = 0; i < dev_endpoints; i++) { ++ ep = &d->out_ep[i]; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ } ++ ++ /* remove ep0 from the list. There is a ep0 pointer. */ ++ list_del_init(&d->ep0.ep_list); ++ ++ d->ep0.maxpacket = MAX_EP0_SIZE; ++} ++ ++/** ++ * This function releases the Gadget device. ++ * required by device_unregister(). ++ * ++ * @todo Should this do something? Should it free the PCD? ++ */ ++static void dwc_otg_pcd_gadget_release(struct device *dev) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev); ++} ++ ++static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev) ++{ ++ static char pcd_name[] = "dwc_otg_pcd"; ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ struct gadget_wrapper *d; ++ int retval; ++ ++ d = DWC_ALLOC(sizeof(*d)); ++ if (d == NULL) { ++ return NULL; ++ } ++ ++ memset(d, 0, sizeof(*d)); ++ ++ d->gadget.name = pcd_name; ++ d->pcd = otg_dev->pcd; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++ strcpy(d->gadget.dev.bus_id, "gadget"); ++#else ++ dev_set_name(&d->gadget.dev, "%s", "gadget"); ++#endif ++ ++ d->gadget.dev.parent = &_dev->dev; ++ d->gadget.dev.release = dwc_otg_pcd_gadget_release; ++ d->gadget.ops = &dwc_otg_pcd_ops; ++ d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL; ++ d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd); ++ ++ d->driver = 0; ++ /* Register the gadget device */ ++ retval = device_register(&d->gadget.dev); ++ if (retval != 0) { ++ DWC_ERROR("device_register failed\n"); ++ DWC_FREE(d); ++ return NULL; ++ } ++ ++ return d; ++} ++ ++static void free_wrapper(struct gadget_wrapper *d) ++{ ++ if (d->driver) { ++ /* should have been done already by driver model core */ ++ DWC_WARN("driver '%s' is still registered\n", ++ d->driver->driver.name); ++ usb_gadget_unregister_driver(d->driver); ++ } ++ ++ device_unregister(&d->gadget.dev); ++ DWC_FREE(d); ++} ++ ++/** ++ * This function initialized the PCD portion of the driver. ++ * ++ */ ++int pcd_init(dwc_bus_dev_t *_dev) ++{ ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev); ++ ++ otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if); ++ ++ if (!otg_dev->pcd) { ++ DWC_ERROR("dwc_otg_pcd_init failed\n"); ++ return -ENOMEM; ++ } ++ ++ otg_dev->pcd->otg_dev = otg_dev; ++ gadget_wrapper = alloc_wrapper(_dev); ++ ++ /* ++ * Initialize EP structures ++ */ ++ gadget_add_eps(gadget_wrapper); ++ /* ++ * Setup interupt handler ++ */ ++#ifdef PLATFORM_INTERFACE ++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", ++ platform_get_irq(_dev, fiq_enable ? 0 : 1)); ++ retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq, ++ IRQF_SHARED, gadget_wrapper->gadget.name, ++ otg_dev->pcd); ++ if (retval != 0) { ++ DWC_ERROR("request of irq%d failed\n", ++ platform_get_irq(_dev, fiq_enable ? 0 : 1)); ++ free_wrapper(gadget_wrapper); ++ return -EBUSY; ++ } ++#else ++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", ++ _dev->irq); ++ retval = request_irq(_dev->irq, dwc_otg_pcd_irq, ++ IRQF_SHARED | IRQF_DISABLED, ++ gadget_wrapper->gadget.name, otg_dev->pcd); ++ if (retval != 0) { ++ DWC_ERROR("request of irq%d failed\n", _dev->irq); ++ free_wrapper(gadget_wrapper); ++ return -EBUSY; ++ } ++#endif ++ ++ dwc_otg_pcd_start(gadget_wrapper->pcd, &fops); ++ ++ return retval; ++} ++ ++/** ++ * Cleanup the PCD. ++ */ ++void pcd_remove(dwc_bus_dev_t *_dev) ++{ ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ dwc_otg_pcd_t *pcd = otg_dev->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); ++ ++ /* ++ * Free the IRQ ++ */ ++#ifdef PLATFORM_INTERFACE ++ free_irq(platform_get_irq(_dev, 0), pcd); ++#else ++ free_irq(_dev->irq, pcd); ++#endif ++ dwc_otg_pcd_remove(otg_dev->pcd); ++ free_wrapper(gadget_wrapper); ++ otg_dev->pcd = 0; ++} ++ ++/** ++ * This function registers a gadget driver with the PCD. ++ * ++ * When a driver is successfully registered, it will receive control ++ * requests including set_configuration(), which enables non-control ++ * requests. then usb traffic follows until a disconnect is reported. ++ * then a host may connect again, or the driver might get unbound. ++ * ++ * @param driver The driver being registered ++ * @param bind The bind function of gadget driver ++ */ ++ ++int usb_gadget_probe_driver(struct usb_gadget_driver *driver) ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", ++ driver->driver.name); ++ ++ if (!driver || driver->max_speed == USB_SPEED_UNKNOWN || ++ !driver->bind || ++ !driver->unbind || !driver->disconnect || !driver->setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EINVAL\n"); ++ return -EINVAL; ++ } ++ if (gadget_wrapper == 0) { ++ DWC_DEBUGPL(DBG_PCDV, "ENODEV\n"); ++ return -ENODEV; ++ } ++ if (gadget_wrapper->driver != 0) { ++ DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver); ++ return -EBUSY; ++ } ++ ++ /* hook up the driver */ ++ gadget_wrapper->driver = driver; ++ gadget_wrapper->gadget.dev.driver = &driver->driver; ++ ++ DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name); ++ retval = driver->bind(&gadget_wrapper->gadget, gadget_wrapper->driver); ++ if (retval) { ++ DWC_ERROR("bind to driver %s --> error %d\n", ++ driver->driver.name, retval); ++ gadget_wrapper->driver = 0; ++ gadget_wrapper->gadget.dev.driver = 0; ++ return retval; ++ } ++ DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n", ++ driver->driver.name); ++ return 0; ++} ++EXPORT_SYMBOL(usb_gadget_probe_driver); ++ ++/** ++ * This function unregisters a gadget driver ++ * ++ * @param driver The driver being unregistered ++ */ ++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) ++{ ++ //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver); ++ ++ if (gadget_wrapper == 0) { ++ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__, ++ -ENODEV); ++ return -ENODEV; ++ } ++ if (driver == 0 || driver != gadget_wrapper->driver) { ++ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__, ++ -EINVAL); ++ return -EINVAL; ++ } ++ ++ driver->unbind(&gadget_wrapper->gadget); ++ gadget_wrapper->driver = 0; ++ ++ DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name); ++ return 0; ++} ++ ++EXPORT_SYMBOL(usb_gadget_unregister_driver); ++ ++#endif /* DWC_HOST_ONLY */ +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/dwc_otg_regs.h +@@ -0,0 +1,2550 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ ++ * $Revision: #98 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_REGS_H__ ++#define __DWC_OTG_REGS_H__ ++ ++#include "dwc_otg_core_if.h" ++ ++/** ++ * @file ++ * ++ * This file contains the data structures for accessing the DWC_otg core registers. ++ * ++ * The application interfaces with the HS OTG core by reading from and ++ * writing to the Control and Status Register (CSR) space through the ++ * AHB Slave interface. These registers are 32 bits wide, and the ++ * addresses are 32-bit-block aligned. ++ * CSRs are classified as follows: ++ * - Core Global Registers ++ * - Device Mode Registers ++ * - Device Global Registers ++ * - Device Endpoint Specific Registers ++ * - Host Mode Registers ++ * - Host Global Registers ++ * - Host Port CSRs ++ * - Host Channel Specific Registers ++ * ++ * Only the Core Global registers can be accessed in both Device and ++ * Host modes. When the HS OTG core is operating in one mode, either ++ * Device or Host, the application must not access registers from the ++ * other mode. When the core switches from one mode to another, the ++ * registers in the new mode of operation must be reprogrammed as they ++ * would be after a power-on reset. ++ */ ++ ++/****************************************************************************/ ++/** DWC_otg Core registers . ++ * The dwc_otg_core_global_regs structure defines the size ++ * and relative field offsets for the Core Global registers. ++ */ ++typedef struct dwc_otg_core_global_regs { ++ /** OTG Control and Status Register. Offset: 000h */ ++ volatile uint32_t gotgctl; ++ /** OTG Interrupt Register. Offset: 004h */ ++ volatile uint32_t gotgint; ++ /**Core AHB Configuration Register. Offset: 008h */ ++ volatile uint32_t gahbcfg; ++ ++#define DWC_GLBINTRMASK 0x0001 ++#define DWC_DMAENABLE 0x0020 ++#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 ++#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 ++#define DWC_PTXEMPTYLVL_EMPTY 0x0100 ++#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 ++ ++ /**Core USB Configuration Register. Offset: 00Ch */ ++ volatile uint32_t gusbcfg; ++ /**Core Reset Register. Offset: 010h */ ++ volatile uint32_t grstctl; ++ /**Core Interrupt Register. Offset: 014h */ ++ volatile uint32_t gintsts; ++ /**Core Interrupt Mask Register. Offset: 018h */ ++ volatile uint32_t gintmsk; ++ /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ ++ volatile uint32_t grxstsr; ++ /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ ++ volatile uint32_t grxstsp; ++ /**Receive FIFO Size Register. Offset: 024h */ ++ volatile uint32_t grxfsiz; ++ /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ ++ volatile uint32_t gnptxfsiz; ++ /**Non Periodic Transmit FIFO/Queue Status Register (Read ++ * Only). Offset: 02Ch */ ++ volatile uint32_t gnptxsts; ++ /**I2C Access Register. Offset: 030h */ ++ volatile uint32_t gi2cctl; ++ /**PHY Vendor Control Register. Offset: 034h */ ++ volatile uint32_t gpvndctl; ++ /**General Purpose Input/Output Register. Offset: 038h */ ++ volatile uint32_t ggpio; ++ /**User ID Register. Offset: 03Ch */ ++ volatile uint32_t guid; ++ /**Synopsys ID Register (Read Only). Offset: 040h */ ++ volatile uint32_t gsnpsid; ++ /**User HW Config1 Register (Read Only). Offset: 044h */ ++ volatile uint32_t ghwcfg1; ++ /**User HW Config2 Register (Read Only). Offset: 048h */ ++ volatile uint32_t ghwcfg2; ++#define DWC_SLAVE_ONLY_ARCH 0 ++#define DWC_EXT_DMA_ARCH 1 ++#define DWC_INT_DMA_ARCH 2 ++ ++#define DWC_MODE_HNP_SRP_CAPABLE 0 ++#define DWC_MODE_SRP_ONLY_CAPABLE 1 ++#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 ++#define DWC_MODE_SRP_CAPABLE_DEVICE 3 ++#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define DWC_MODE_SRP_CAPABLE_HOST 5 ++#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 ++ ++ /**User HW Config3 Register (Read Only). Offset: 04Ch */ ++ volatile uint32_t ghwcfg3; ++ /**User HW Config4 Register (Read Only). Offset: 050h*/ ++ volatile uint32_t ghwcfg4; ++ /** Core LPM Configuration register Offset: 054h*/ ++ volatile uint32_t glpmcfg; ++ /** Global PowerDn Register Offset: 058h */ ++ volatile uint32_t gpwrdn; ++ /** Global DFIFO SW Config Register Offset: 05Ch */ ++ volatile uint32_t gdfifocfg; ++ /** ADP Control Register Offset: 060h */ ++ volatile uint32_t adpctl; ++ /** Reserved Offset: 064h-0FFh */ ++ volatile uint32_t reserved39[39]; ++ /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ ++ volatile uint32_t hptxfsiz; ++ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, ++ otherwise Device Transmit FIFO#n Register. ++ * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ ++ volatile uint32_t dtxfsiz[15]; ++} dwc_otg_core_global_regs_t; ++ ++/** ++ * This union represents the bit fields of the Core OTG Control ++ * and Status Register (GOTGCTL). Set the bits using the bit ++ * fields then write the d32 value to the register. ++ */ ++typedef union gotgctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned sesreqscs:1; ++ unsigned sesreq:1; ++ unsigned vbvalidoven:1; ++ unsigned vbvalidovval:1; ++ unsigned avalidoven:1; ++ unsigned avalidovval:1; ++ unsigned bvalidoven:1; ++ unsigned bvalidovval:1; ++ unsigned hstnegscs:1; ++ unsigned hnpreq:1; ++ unsigned hstsethnpen:1; ++ unsigned devhnpen:1; ++ unsigned reserved12_15:4; ++ unsigned conidsts:1; ++ unsigned dbnctime:1; ++ unsigned asesvld:1; ++ unsigned bsesvld:1; ++ unsigned otgver:1; ++ unsigned reserved1:1; ++ unsigned multvalidbc:5; ++ unsigned chirpen:1; ++ unsigned reserved28_31:4; ++ } b; ++} gotgctl_data_t; ++ ++/** ++ * This union represents the bit fields of the Core OTG Interrupt Register ++ * (GOTGINT). Set/clear the bits using the bit fields then write the d32 ++ * value to the register. ++ */ ++typedef union gotgint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Current Mode */ ++ unsigned reserved0_1:2; ++ ++ /** Session End Detected */ ++ unsigned sesenddet:1; ++ ++ unsigned reserved3_7:5; ++ ++ /** Session Request Success Status Change */ ++ unsigned sesreqsucstschng:1; ++ /** Host Negotiation Success Status Change */ ++ unsigned hstnegsucstschng:1; ++ ++ unsigned reserved10_16:7; ++ ++ /** Host Negotiation Detected */ ++ unsigned hstnegdet:1; ++ /** A-Device Timeout Change */ ++ unsigned adevtoutchng:1; ++ /** Debounce Done */ ++ unsigned debdone:1; ++ /** Multi-Valued input changed */ ++ unsigned mvic:1; ++ ++ unsigned reserved31_21:11; ++ ++ } b; ++} gotgint_data_t; ++ ++/** ++ * This union represents the bit fields of the Core AHB Configuration ++ * Register (GAHBCFG). Set/clear the bits using the bit fields then ++ * write the d32 value to the register. ++ */ ++typedef union gahbcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned glblintrmsk:1; ++#define DWC_GAHBCFG_GLBINT_ENABLE 1 ++ ++ unsigned hburstlen:4; ++#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 ++ ++ unsigned dmaenable:1; ++#define DWC_GAHBCFG_DMAENABLE 1 ++ unsigned reserved:1; ++ unsigned nptxfemplvl_txfemplvl:1; ++ unsigned ptxfemplvl:1; ++#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 ++#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 ++ unsigned reserved9_20:12; ++ unsigned remmemsupp:1; ++ unsigned notialldmawrit:1; ++ unsigned ahbsingle:1; ++ unsigned reserved24_31:8; ++ } b; ++} gahbcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core USB Configuration ++ * Register (GUSBCFG). Set the bits using the bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union gusbcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned toutcal:3; ++ unsigned phyif:1; ++ unsigned ulpi_utmi_sel:1; ++ unsigned fsintf:1; ++ unsigned physel:1; ++ unsigned ddrsel:1; ++ unsigned srpcap:1; ++ unsigned hnpcap:1; ++ unsigned usbtrdtim:4; ++ unsigned reserved1:1; ++ unsigned phylpwrclksel:1; ++ unsigned otgutmifssel:1; ++ unsigned ulpi_fsls:1; ++ unsigned ulpi_auto_res:1; ++ unsigned ulpi_clk_sus_m:1; ++ unsigned ulpi_ext_vbus_drv:1; ++ unsigned ulpi_int_vbus_indicator:1; ++ unsigned term_sel_dl_pulse:1; ++ unsigned indicator_complement:1; ++ unsigned indicator_pass_through:1; ++ unsigned ulpi_int_prot_dis:1; ++ unsigned ic_usb_cap:1; ++ unsigned ic_traffic_pull_remove:1; ++ unsigned tx_end_delay:1; ++ unsigned force_host_mode:1; ++ unsigned force_dev_mode:1; ++ unsigned reserved31:1; ++ } b; ++} gusbcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core Reset Register ++ * (GRSTCTL). Set/clear the bits using the bit fields then write the ++ * d32 value to the register. ++ */ ++typedef union grstctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Core Soft Reset (CSftRst) (Device and Host) ++ * ++ * The application can flush the control logic in the ++ * entire core using this bit. This bit resets the ++ * pipelines in the AHB Clock domain as well as the ++ * PHY Clock domain. ++ * ++ * The state machines are reset to an IDLE state, the ++ * control bits in the CSRs are cleared, all the ++ * transmit FIFOs and the receive FIFO are flushed. ++ * ++ * The status mask bits that control the generation of ++ * the interrupt, are cleared, to clear the ++ * interrupt. The interrupt status bits are not ++ * cleared, so the application can get the status of ++ * any events that occurred in the core after it has ++ * set this bit. ++ * ++ * Any transactions on the AHB are terminated as soon ++ * as possible following the protocol. Any ++ * transactions on the USB are terminated immediately. ++ * ++ * The configuration settings in the CSRs are ++ * unchanged, so the software doesn't have to ++ * reprogram these registers (Device ++ * Configuration/Host Configuration/Core System ++ * Configuration/Core PHY Configuration). ++ * ++ * The application can write to this bit, any time it ++ * wants to reset the core. This is a self clearing ++ * bit and the core clears this bit after all the ++ * necessary logic is reset in the core, which may ++ * take several clocks, depending on the current state ++ * of the core. ++ */ ++ unsigned csftrst:1; ++ /** Hclk Soft Reset ++ * ++ * The application uses this bit to reset the control logic in ++ * the AHB clock domain. Only AHB clock domain pipelines are ++ * reset. ++ */ ++ unsigned hsftrst:1; ++ /** Host Frame Counter Reset (Host Only)
++ * ++ * The application can reset the (micro)frame number ++ * counter inside the core, using this bit. When the ++ * (micro)frame counter is reset, the subsequent SOF ++ * sent out by the core, will have a (micro)frame ++ * number of 0. ++ */ ++ unsigned hstfrm:1; ++ /** In Token Sequence Learning Queue Flush ++ * (INTknQFlsh) (Device Only) ++ */ ++ unsigned intknqflsh:1; ++ /** RxFIFO Flush (RxFFlsh) (Device and Host) ++ * ++ * The application can flush the entire Receive FIFO ++ * using this bit. The application must first ++ * ensure that the core is not in the middle of a ++ * transaction. The application should write into ++ * this bit, only after making sure that neither the ++ * DMA engine is reading from the RxFIFO nor the MAC ++ * is writing the data in to the FIFO. The ++ * application should wait until the bit is cleared ++ * before performing any other operations. This bit ++ * will takes 8 clocks (slowest of PHY or AHB clock) ++ * to clear. ++ */ ++ unsigned rxfflsh:1; ++ /** TxFIFO Flush (TxFFlsh) (Device and Host). ++ * ++ * This bit is used to selectively flush a single or ++ * all transmit FIFOs. The application must first ++ * ensure that the core is not in the middle of a ++ * transaction. The application should write into ++ * this bit, only after making sure that neither the ++ * DMA engine is writing into the TxFIFO nor the MAC ++ * is reading the data out of the FIFO. The ++ * application should wait until the core clears this ++ * bit, before performing any operations. This bit ++ * will takes 8 clocks (slowest of PHY or AHB clock) ++ * to clear. ++ */ ++ unsigned txfflsh:1; ++ ++ /** TxFIFO Number (TxFNum) (Device and Host). ++ * ++ * This is the FIFO number which needs to be flushed, ++ * using the TxFIFO Flush bit. This field should not ++ * be changed until the TxFIFO Flush bit is cleared by ++ * the core. ++ * - 0x0 : Non Periodic TxFIFO Flush ++ * - 0x1 : Periodic TxFIFO #1 Flush in device mode ++ * or Periodic TxFIFO in host mode ++ * - 0x2 : Periodic TxFIFO #2 Flush in device mode. ++ * - ... ++ * - 0xF : Periodic TxFIFO #15 Flush in device mode ++ * - 0x10: Flush all the Transmit NonPeriodic and ++ * Transmit Periodic FIFOs in the core ++ */ ++ unsigned txfnum:5; ++ /** Reserved */ ++ unsigned reserved11_29:19; ++ /** DMA Request Signal. Indicated DMA request is in ++ * probress. Used for debug purpose. */ ++ unsigned dmareq:1; ++ /** AHB Master Idle. Indicates the AHB Master State ++ * Machine is in IDLE condition. */ ++ unsigned ahbidle:1; ++ } b; ++} grstctl_t; ++ ++/** ++ * This union represents the bit fields of the Core Interrupt Mask ++ * Register (GINTMSK). Set/clear the bits using the bit fields then ++ * write the d32 value to the register. ++ */ ++typedef union gintmsk_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved0:1; ++ unsigned modemismatch:1; ++ unsigned otgintr:1; ++ unsigned sofintr:1; ++ unsigned rxstsqlvl:1; ++ unsigned nptxfempty:1; ++ unsigned ginnakeff:1; ++ unsigned goutnakeff:1; ++ unsigned ulpickint:1; ++ unsigned i2cintr:1; ++ unsigned erlysuspend:1; ++ unsigned usbsuspend:1; ++ unsigned usbreset:1; ++ unsigned enumdone:1; ++ unsigned isooutdrop:1; ++ unsigned eopframe:1; ++ unsigned restoredone:1; ++ unsigned epmismatch:1; ++ unsigned inepintr:1; ++ unsigned outepintr:1; ++ unsigned incomplisoin:1; ++ unsigned incomplisoout:1; ++ unsigned fetsusp:1; ++ unsigned resetdet:1; ++ unsigned portintr:1; ++ unsigned hcintr:1; ++ unsigned ptxfempty:1; ++ unsigned lpmtranrcvd:1; ++ unsigned conidstschng:1; ++ unsigned disconnect:1; ++ unsigned sessreqintr:1; ++ unsigned wkupintr:1; ++ } b; ++} gintmsk_data_t; ++/** ++ * This union represents the bit fields of the Core Interrupt Register ++ * (GINTSTS). Set/clear the bits using the bit fields then write the ++ * d32 value to the register. ++ */ ++typedef union gintsts_data { ++ /** raw register data */ ++ uint32_t d32; ++#define DWC_SOF_INTR_MASK 0x0008 ++ /** register bits */ ++ struct { ++#define DWC_HOST_MODE 1 ++ unsigned curmode:1; ++ unsigned modemismatch:1; ++ unsigned otgintr:1; ++ unsigned sofintr:1; ++ unsigned rxstsqlvl:1; ++ unsigned nptxfempty:1; ++ unsigned ginnakeff:1; ++ unsigned goutnakeff:1; ++ unsigned ulpickint:1; ++ unsigned i2cintr:1; ++ unsigned erlysuspend:1; ++ unsigned usbsuspend:1; ++ unsigned usbreset:1; ++ unsigned enumdone:1; ++ unsigned isooutdrop:1; ++ unsigned eopframe:1; ++ unsigned restoredone:1; ++ unsigned epmismatch:1; ++ unsigned inepint:1; ++ unsigned outepintr:1; ++ unsigned incomplisoin:1; ++ unsigned incomplisoout:1; ++ unsigned fetsusp:1; ++ unsigned resetdet:1; ++ unsigned portintr:1; ++ unsigned hcintr:1; ++ unsigned ptxfempty:1; ++ unsigned lpmtranrcvd:1; ++ unsigned conidstschng:1; ++ unsigned disconnect:1; ++ unsigned sessreqintr:1; ++ unsigned wkupintr:1; ++ } b; ++} gintsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 ++ * element then read out the bits using the bit elements. ++ */ ++typedef union device_grxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned epnum:4; ++ unsigned bcnt:11; ++ unsigned dpid:2; ++ ++#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet ++#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete ++ ++#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK ++#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete ++#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet ++ unsigned pktsts:4; ++ unsigned fn:4; ++ unsigned reserved25_31:7; ++ } b; ++} device_grxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 ++ * element then read out the bits using the bit elements. ++ */ ++typedef union host_grxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned chnum:4; ++ unsigned bcnt:11; ++ unsigned dpid:2; ++ ++ unsigned pktsts:4; ++#define DWC_GRXSTS_PKTSTS_IN 0x2 ++#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 ++#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 ++#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 ++ ++ unsigned reserved21_31:11; ++ } b; ++} host_grxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, ++ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element ++ * then read out the bits using the bit elements. ++ */ ++typedef union fifosize_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned startaddr:16; ++ unsigned depth:16; ++ } b; ++} fifosize_data_t; ++ ++/** ++ * This union represents the bit fields in the Non-Periodic Transmit ++ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the ++ * d32 element then read out the bits using the bit ++ * elements. ++ */ ++typedef union gnptxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned nptxfspcavail:16; ++ unsigned nptxqspcavail:8; ++ /** Top of the Non-Periodic Transmit Request Queue ++ * - bit 24 - Terminate (Last entry for the selected ++ * channel/EP) ++ * - bits 26:25 - Token Type ++ * - 2'b00 - IN/OUT ++ * - 2'b01 - Zero Length OUT ++ * - 2'b10 - PING/Complete Split ++ * - 2'b11 - Channel Halt ++ * - bits 30:27 - Channel/EP Number ++ */ ++ unsigned nptxqtop_terminate:1; ++ unsigned nptxqtop_token:2; ++ unsigned nptxqtop_chnep:4; ++ unsigned reserved:1; ++ } b; ++} gnptxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Transmit ++ * FIFO Status Register (DTXFSTS). Read the register into the ++ * d32 element then read out the bits using the bit ++ * elements. ++ */ ++typedef union dtxfsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned txfspcavail:16; ++ unsigned reserved:16; ++ } b; ++} dtxfsts_data_t; ++ ++/** ++ * This union represents the bit fields in the I2C Control Register ++ * (I2CCTL). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gi2cctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:8; ++ unsigned regaddr:8; ++ unsigned addr:7; ++ unsigned i2cen:1; ++ unsigned ack:1; ++ unsigned i2csuspctl:1; ++ unsigned i2cdevaddr:2; ++ unsigned i2cdatse0:1; ++ unsigned reserved:1; ++ unsigned rw:1; ++ unsigned bsydne:1; ++ } b; ++} gi2cctl_data_t; ++ ++/** ++ * This union represents the bit fields in the PHY Vendor Control Register ++ * (GPVNDCTL). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gpvndctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned regdata:8; ++ unsigned vctrl:8; ++ unsigned regaddr16_21:6; ++ unsigned regwr:1; ++ unsigned reserved23_24:2; ++ unsigned newregreq:1; ++ unsigned vstsbsy:1; ++ unsigned vstsdone:1; ++ unsigned reserved28_30:3; ++ unsigned disulpidrvr:1; ++ } b; ++} gpvndctl_data_t; ++ ++/** ++ * This union represents the bit fields in the General Purpose ++ * Input/Output Register (GGPIO). ++ * Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union ggpio_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned gpi:16; ++ unsigned gpo:16; ++ } b; ++} ggpio_data_t; ++ ++/** ++ * This union represents the bit fields in the User ID Register ++ * (GUID). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union guid_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:32; ++ } b; ++} guid_data_t; ++ ++/** ++ * This union represents the bit fields in the Synopsys ID Register ++ * (GSNPSID). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gsnpsid_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:32; ++ } b; ++} gsnpsid_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config1 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg1_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ep_dir0:2; ++ unsigned ep_dir1:2; ++ unsigned ep_dir2:2; ++ unsigned ep_dir3:2; ++ unsigned ep_dir4:2; ++ unsigned ep_dir5:2; ++ unsigned ep_dir6:2; ++ unsigned ep_dir7:2; ++ unsigned ep_dir8:2; ++ unsigned ep_dir9:2; ++ unsigned ep_dir10:2; ++ unsigned ep_dir11:2; ++ unsigned ep_dir12:2; ++ unsigned ep_dir13:2; ++ unsigned ep_dir14:2; ++ unsigned ep_dir15:2; ++ } b; ++} hwcfg1_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config2 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg2_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG2 */ ++ unsigned op_mode:3; ++#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 ++#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 ++#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 ++ ++ unsigned architecture:2; ++ unsigned point2point:1; ++ unsigned hs_phy_type:2; ++#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 ++#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 ++ ++ unsigned fs_phy_type:2; ++ unsigned num_dev_ep:4; ++ unsigned num_host_chan:4; ++ unsigned perio_ep_supported:1; ++ unsigned dynamic_fifo:1; ++ unsigned multi_proc_int:1; ++ unsigned reserved21:1; ++ unsigned nonperio_tx_q_depth:2; ++ unsigned host_perio_tx_q_depth:2; ++ unsigned dev_token_q_depth:5; ++ unsigned otg_enable_ic_usb:1; ++ } b; ++} hwcfg2_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config3 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg3_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG3 */ ++ unsigned xfer_size_cntr_width:4; ++ unsigned packet_size_cntr_width:3; ++ unsigned otg_func:1; ++ unsigned i2c:1; ++ unsigned vendor_ctrl_if:1; ++ unsigned optional_features:1; ++ unsigned synch_reset_type:1; ++ unsigned adp_supp:1; ++ unsigned otg_enable_hsic:1; ++ unsigned bc_support:1; ++ unsigned otg_lpm_en:1; ++ unsigned dfifo_depth:16; ++ } b; ++} hwcfg3_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config4 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg4_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned num_dev_perio_in_ep:4; ++ unsigned power_optimiz:1; ++ unsigned min_ahb_freq:1; ++ unsigned hiber:1; ++ unsigned xhiber:1; ++ unsigned reserved:6; ++ unsigned utmi_phy_data_width:2; ++ unsigned num_dev_mode_ctrl_ep:4; ++ unsigned iddig_filt_en:1; ++ unsigned vbus_valid_filt_en:1; ++ unsigned a_valid_filt_en:1; ++ unsigned b_valid_filt_en:1; ++ unsigned session_end_filt_en:1; ++ unsigned ded_fifo_en:1; ++ unsigned num_in_eps:4; ++ unsigned desc_dma:1; ++ unsigned desc_dma_dyn:1; ++ } b; ++} hwcfg4_data_t; ++ ++/** ++ * This union represents the bit fields of the Core LPM Configuration ++ * Register (GLPMCFG). Set the bits using bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union glpmctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** LPM-Capable (LPMCap) (Device and Host) ++ * The application uses this bit to control ++ * the DWC_otg core LPM capabilities. ++ */ ++ unsigned lpm_cap_en:1; ++ /** LPM response programmed by application (AppL1Res) (Device) ++ * Handshake response to LPM token pre-programmed ++ * by device application software. ++ */ ++ unsigned appl_resp:1; ++ /** Host Initiated Resume Duration (HIRD) (Device and Host) ++ * In Host mode this field indicates the value of HIRD ++ * to be sent in an LPM transaction. ++ * In Device mode this field is updated with the ++ * Received LPM Token HIRD bmAttribute ++ * when an ACK/NYET/STALL response is sent ++ * to an LPM transaction. ++ */ ++ unsigned hird:4; ++ /** RemoteWakeEnable (bRemoteWake) (Device and Host) ++ * In Host mode this bit indicates the value of remote ++ * wake up to be sent in wIndex field of LPM transaction. ++ * In Device mode this field is updated with the ++ * Received LPM Token bRemoteWake bmAttribute ++ * when an ACK/NYET/STALL response is sent ++ * to an LPM transaction. ++ */ ++ unsigned rem_wkup_en:1; ++ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) ++ * The application uses this bit to control ++ * the utmi_sleep_n assertion to the PHY when in L1 state. ++ */ ++ unsigned en_utmi_sleep:1; ++ /** HIRD Threshold (HIRD_Thres) (Device and Host) ++ */ ++ unsigned hird_thres:5; ++ /** LPM Response (CoreL1Res) (Device and Host) ++ * In Host mode this bit contains handsake response to ++ * LPM transaction. ++ * In Device mode the response of the core to ++ * LPM transaction received is reflected in these two bits. ++ - 0x0 : ERROR (No handshake response) ++ - 0x1 : STALL ++ - 0x2 : NYET ++ - 0x3 : ACK ++ */ ++ unsigned lpm_resp:2; ++ /** Port Sleep Status (SlpSts) (Device and Host) ++ * This bit is set as long as a Sleep condition ++ * is present on the USB bus. ++ */ ++ unsigned prt_sleep_sts:1; ++ /** Sleep State Resume OK (L1ResumeOK) (Device and Host) ++ * Indicates that the application or host ++ * can start resume from Sleep state. ++ */ ++ unsigned sleep_state_resumeok:1; ++ /** LPM channel Index (LPM_Chnl_Indx) (Host) ++ * The channel number on which the LPM transaction ++ * has to be applied while sending ++ * an LPM transaction to the local device. ++ */ ++ unsigned lpm_chan_index:4; ++ /** LPM Retry Count (LPM_Retry_Cnt) (Host) ++ * Number host retries that would be performed ++ * if the device response was not valid response. ++ */ ++ unsigned retry_count:3; ++ /** Send LPM Transaction (SndLPM) (Host) ++ * When set by application software, ++ * an LPM transaction containing two tokens ++ * is sent. ++ */ ++ unsigned send_lpm:1; ++ /** LPM Retry status (LPM_RetryCnt_Sts) (Host) ++ * Number of LPM Host Retries still remaining ++ * to be transmitted for the current LPM sequence ++ */ ++ unsigned retry_count_sts:3; ++ unsigned reserved28_29:2; ++ /** In host mode once this bit is set, the host ++ * configures to drive the HSIC Idle state on the bus. ++ * It then waits for the device to initiate the Connect sequence. ++ * In device mode once this bit is set, the device waits for ++ * the HSIC Idle line state on the bus. Upon receving the Idle ++ * line state, it initiates the HSIC Connect sequence. ++ */ ++ unsigned hsic_connect:1; ++ /** This bit overrides and functionally inverts ++ * the if_select_hsic input port signal. ++ */ ++ unsigned inv_sel_hsic:1; ++ } b; ++} glpmcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core ADP Timer, Control and ++ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union adpctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Probe Discharge (PRB_DSCHG) ++ * These bits set the times for TADP_DSCHG. ++ * These bits are defined as follows: ++ * 2'b00 - 4 msec ++ * 2'b01 - 8 msec ++ * 2'b10 - 16 msec ++ * 2'b11 - 32 msec ++ */ ++ unsigned prb_dschg:2; ++ /** Probe Delta (PRB_DELTA) ++ * These bits set the resolution for RTIM value. ++ * The bits are defined in units of 32 kHz clock cycles as follows: ++ * 2'b00 - 1 cycles ++ * 2'b01 - 2 cycles ++ * 2'b10 - 3 cycles ++ * 2'b11 - 4 cycles ++ * For example if this value is chosen to 2'b01, it means that RTIM ++ * increments for every 3(three) 32Khz clock cycles. ++ */ ++ unsigned prb_delta:2; ++ /** Probe Period (PRB_PER) ++ * These bits sets the TADP_PRD as shown in Figure 4 as follows: ++ * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) ++ * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) ++ * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) ++ * 2'b11 - Reserved ++ */ ++ unsigned prb_per:2; ++ /** These bits capture the latest time it took for VBUS to ramp from ++ * VADP_SINK to VADP_PRB. ++ * 0x000 - 1 cycles ++ * 0x001 - 2 cycles ++ * 0x002 - 3 cycles ++ * etc ++ * 0x7FF - 2048 cycles ++ * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. ++ */ ++ unsigned rtim:11; ++ /** Enable Probe (EnaPrb) ++ * When programmed to 1'b1, the core performs a probe operation. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned enaprb:1; ++ /** Enable Sense (EnaSns) ++ * When programmed to 1'b1, the core performs a Sense operation. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned enasns:1; ++ /** ADP Reset (ADPRes) ++ * When set, ADP controller is reset. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adpres:1; ++ /** ADP Enable (ADPEn) ++ * When set, the core performs either ADP probing or sensing ++ * based on EnaPrb or EnaSns. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adpen:1; ++ /** ADP Probe Interrupt (ADP_PRB_INT) ++ * When this bit is set, it means that the VBUS ++ * voltage is greater than VADP_PRB or VADP_PRB is reached. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_prb_int:1; ++ /** ++ * ADP Sense Interrupt (ADP_SNS_INT) ++ * When this bit is set, it means that the VBUS voltage is greater than ++ * VADP_SNS value or VADP_SNS is reached. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_sns_int:1; ++ /** ADP Tomeout Interrupt (ADP_TMOUT_INT) ++ * This bit is relevant only for an ADP probe. ++ * When this bit is set, it means that the ramp time has ++ * completed ie ADPCTL.RTIM has reached its terminal value ++ * of 0x7FF. This is a debug feature that allows software ++ * to read the ramp time after each cycle. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_tmout_int:1; ++ /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_prb_int_msk:1; ++ /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_sns_int_msk:1; ++ /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_tmout_int_msk:1; ++ /** Access Request ++ * 2'b00 - Read/Write Valid (updated by the core) ++ * 2'b01 - Read ++ * 2'b00 - Write ++ * 2'b00 - Reserved ++ */ ++ unsigned ar:2; ++ /** Reserved */ ++ unsigned reserved29_31:3; ++ } b; ++} adpctl_data_t; ++ ++//////////////////////////////////////////// ++// Device Registers ++/** ++ * Device Global Registers. Offsets 800h-BFFh ++ * ++ * The following structures define the size and relative field offsets ++ * for the Device Mode Registers. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_global_regs { ++ /** Device Configuration Register. Offset 800h */ ++ volatile uint32_t dcfg; ++ /** Device Control Register. Offset: 804h */ ++ volatile uint32_t dctl; ++ /** Device Status Register (Read Only). Offset: 808h */ ++ volatile uint32_t dsts; ++ /** Reserved. Offset: 80Ch */ ++ uint32_t unused; ++ /** Device IN Endpoint Common Interrupt Mask ++ * Register. Offset: 810h */ ++ volatile uint32_t diepmsk; ++ /** Device OUT Endpoint Common Interrupt Mask ++ * Register. Offset: 814h */ ++ volatile uint32_t doepmsk; ++ /** Device All Endpoints Interrupt Register. Offset: 818h */ ++ volatile uint32_t daint; ++ /** Device All Endpoints Interrupt Mask Register. Offset: ++ * 81Ch */ ++ volatile uint32_t daintmsk; ++ /** Device IN Token Queue Read Register-1 (Read Only). ++ * Offset: 820h */ ++ volatile uint32_t dtknqr1; ++ /** Device IN Token Queue Read Register-2 (Read Only). ++ * Offset: 824h */ ++ volatile uint32_t dtknqr2; ++ /** Device VBUS discharge Register. Offset: 828h */ ++ volatile uint32_t dvbusdis; ++ /** Device VBUS Pulse Register. Offset: 82Ch */ ++ volatile uint32_t dvbuspulse; ++ /** Device IN Token Queue Read Register-3 (Read Only). / ++ * Device Thresholding control register (Read/Write) ++ * Offset: 830h */ ++ volatile uint32_t dtknqr3_dthrctl; ++ /** Device IN Token Queue Read Register-4 (Read Only). / ++ * Device IN EPs empty Inr. Mask Register (Read/Write) ++ * Offset: 834h */ ++ volatile uint32_t dtknqr4_fifoemptymsk; ++ /** Device Each Endpoint Interrupt Register (Read Only). / ++ * Offset: 838h */ ++ volatile uint32_t deachint; ++ /** Device Each Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 83Ch */ ++ volatile uint32_t deachintmsk; ++ /** Device Each In Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 840h */ ++ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; ++ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 880h */ ++ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; ++} dwc_otg_device_global_regs_t; ++ ++/** ++ * This union represents the bit fields in the Device Configuration ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. Write the ++ * d32 member to the dcfg register. ++ */ ++typedef union dcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Device Speed */ ++ unsigned devspd:2; ++ /** Non Zero Length Status OUT Handshake */ ++ unsigned nzstsouthshk:1; ++#define DWC_DCFG_SEND_STALL 1 ++ ++ unsigned ena32khzs:1; ++ /** Device Addresses */ ++ unsigned devaddr:7; ++ /** Periodic Frame Interval */ ++ unsigned perfrint:2; ++#define DWC_DCFG_FRAME_INTERVAL_80 0 ++#define DWC_DCFG_FRAME_INTERVAL_85 1 ++#define DWC_DCFG_FRAME_INTERVAL_90 2 ++#define DWC_DCFG_FRAME_INTERVAL_95 3 ++ ++ /** Enable Device OUT NAK for bulk in DDMA mode */ ++ unsigned endevoutnak:1; ++ ++ unsigned reserved14_17:4; ++ /** In Endpoint Mis-match count */ ++ unsigned epmscnt:5; ++ /** Enable Descriptor DMA in Device mode */ ++ unsigned descdma:1; ++ unsigned perschintvl:2; ++ unsigned resvalid:6; ++ } b; ++} dcfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Control ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union dctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Remote Wakeup */ ++ unsigned rmtwkupsig:1; ++ /** Soft Disconnect */ ++ unsigned sftdiscon:1; ++ /** Global Non-Periodic IN NAK Status */ ++ unsigned gnpinnaksts:1; ++ /** Global OUT NAK Status */ ++ unsigned goutnaksts:1; ++ /** Test Control */ ++ unsigned tstctl:3; ++ /** Set Global Non-Periodic IN NAK */ ++ unsigned sgnpinnak:1; ++ /** Clear Global Non-Periodic IN NAK */ ++ unsigned cgnpinnak:1; ++ /** Set Global OUT NAK */ ++ unsigned sgoutnak:1; ++ /** Clear Global OUT NAK */ ++ unsigned cgoutnak:1; ++ /** Power-On Programming Done */ ++ unsigned pwronprgdone:1; ++ /** Reserved */ ++ unsigned reserved:1; ++ /** Global Multi Count */ ++ unsigned gmc:2; ++ /** Ignore Frame Number for ISOC EPs */ ++ unsigned ifrmnum:1; ++ /** NAK on Babble */ ++ unsigned nakonbble:1; ++ /** Enable Continue on BNA */ ++ unsigned encontonbna:1; ++ ++ unsigned reserved18_31:14; ++ } b; ++} dctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Status ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union dsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Suspend Status */ ++ unsigned suspsts:1; ++ /** Enumerated Speed */ ++ unsigned enumspd:2; ++#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 ++#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 ++#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 ++#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 ++ /** Erratic Error */ ++ unsigned errticerr:1; ++ unsigned reserved4_7:4; ++ /** Frame or Microframe Number of the received SOF */ ++ unsigned soffn:14; ++ unsigned reserved22_31:10; ++ } b; ++} dsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN EP Interrupt ++ * Register and the Device IN EP Common Mask Register. ++ * ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union diepint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer complete mask */ ++ unsigned xfercompl:1; ++ /** Endpoint disable mask */ ++ unsigned epdisabled:1; ++ /** AHB Error mask */ ++ unsigned ahberr:1; ++ /** TimeOUT Handshake mask (non-ISOC EPs) */ ++ unsigned timeout:1; ++ /** IN Token received with TxF Empty mask */ ++ unsigned intktxfemp:1; ++ /** IN Token Received with EP mismatch mask */ ++ unsigned intknepmis:1; ++ /** IN Endpoint NAK Effective mask */ ++ unsigned inepnakeff:1; ++ /** Reserved */ ++ unsigned emptyintr:1; ++ ++ unsigned txfifoundrn:1; ++ ++ /** BNA Interrupt mask */ ++ unsigned bna:1; ++ ++ unsigned reserved10_12:3; ++ /** BNA Interrupt mask */ ++ unsigned nak:1; ++ ++ unsigned reserved14_31:18; ++ } b; ++} diepint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN EP ++ * Common/Dedicated Interrupt Mask Register. ++ */ ++typedef union diepint_data diepmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Device OUT EP Interrupt ++ * Registerand Device OUT EP Common Interrupt Mask Register. ++ * ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union doepint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer complete */ ++ unsigned xfercompl:1; ++ /** Endpoint disable */ ++ unsigned epdisabled:1; ++ /** AHB Error */ ++ unsigned ahberr:1; ++ /** Setup Phase Done (contorl EPs) */ ++ unsigned setup:1; ++ /** OUT Token Received when Endpoint Disabled */ ++ unsigned outtknepdis:1; ++ ++ unsigned stsphsercvd:1; ++ /** Back-to-Back SETUP Packets Received */ ++ unsigned back2backsetup:1; ++ ++ unsigned reserved7:1; ++ /** OUT packet Error */ ++ unsigned outpkterr:1; ++ /** BNA Interrupt */ ++ unsigned bna:1; ++ ++ unsigned reserved10:1; ++ /** Packet Drop Status */ ++ unsigned pktdrpsts:1; ++ /** Babble Interrupt */ ++ unsigned babble:1; ++ /** NAK Interrupt */ ++ unsigned nak:1; ++ /** NYET Interrupt */ ++ unsigned nyet:1; ++ /** Bit indicating setup packet received */ ++ unsigned sr:1; ++ ++ unsigned reserved16_31:16; ++ } b; ++} doepint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device OUT EP ++ * Common/Dedicated Interrupt Mask Register. ++ */ ++typedef union doepint_data doepmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Device All EP Interrupt ++ * and Mask Registers. ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union daint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** IN Endpoint bits */ ++ unsigned in:16; ++ /** OUT Endpoint bits */ ++ unsigned out:16; ++ } ep; ++ struct { ++ /** IN Endpoint bits */ ++ unsigned inep0:1; ++ unsigned inep1:1; ++ unsigned inep2:1; ++ unsigned inep3:1; ++ unsigned inep4:1; ++ unsigned inep5:1; ++ unsigned inep6:1; ++ unsigned inep7:1; ++ unsigned inep8:1; ++ unsigned inep9:1; ++ unsigned inep10:1; ++ unsigned inep11:1; ++ unsigned inep12:1; ++ unsigned inep13:1; ++ unsigned inep14:1; ++ unsigned inep15:1; ++ /** OUT Endpoint bits */ ++ unsigned outep0:1; ++ unsigned outep1:1; ++ unsigned outep2:1; ++ unsigned outep3:1; ++ unsigned outep4:1; ++ unsigned outep5:1; ++ unsigned outep6:1; ++ unsigned outep7:1; ++ unsigned outep8:1; ++ unsigned outep9:1; ++ unsigned outep10:1; ++ unsigned outep11:1; ++ unsigned outep12:1; ++ unsigned outep13:1; ++ unsigned outep14:1; ++ unsigned outep15:1; ++ } b; ++} daint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN Token Queue ++ * Read Registers. ++ * - Read the register into the d32 member. ++ * - READ-ONLY Register ++ */ ++typedef union dtknq1_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** In Token Queue Write Pointer */ ++ unsigned intknwptr:5; ++ /** Reserved */ ++ unsigned reserved05_06:2; ++ /** write pointer has wrapped. */ ++ unsigned wrap_bit:1; ++ /** EP Numbers of IN Tokens 0 ... 4 */ ++ unsigned epnums0_5:24; ++ } b; ++} dtknq1_data_t; ++ ++/** ++ * This union represents Threshold control Register ++ * - Read and write the register into the d32 member. ++ * - READ-WRITABLE Register ++ */ ++typedef union dthrctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** non ISO Tx Thr. Enable */ ++ unsigned non_iso_thr_en:1; ++ /** ISO Tx Thr. Enable */ ++ unsigned iso_thr_en:1; ++ /** Tx Thr. Length */ ++ unsigned tx_thr_len:9; ++ /** AHB Threshold ratio */ ++ unsigned ahb_thr_ratio:2; ++ /** Reserved */ ++ unsigned reserved13_15:3; ++ /** Rx Thr. Enable */ ++ unsigned rx_thr_en:1; ++ /** Rx Thr. Length */ ++ unsigned rx_thr_len:9; ++ unsigned reserved26:1; ++ /** Arbiter Parking Enable*/ ++ unsigned arbprken:1; ++ /** Reserved */ ++ unsigned reserved28_31:4; ++ } b; ++} dthrctl_data_t; ++ ++/** ++ * Device Logical IN Endpoint-Specific Registers. Offsets ++ * 900h-AFCh ++ * ++ * There will be one set of endpoint registers per logical endpoint ++ * implemented. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_in_ep_regs { ++ /** Device IN Endpoint Control Register. Offset:900h + ++ * (ep_num * 20h) + 00h */ ++ volatile uint32_t diepctl; ++ /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ ++ uint32_t reserved04; ++ /** Device IN Endpoint Interrupt Register. Offset:900h + ++ * (ep_num * 20h) + 08h */ ++ volatile uint32_t diepint; ++ /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ ++ uint32_t reserved0C; ++ /** Device IN Endpoint Transfer Size ++ * Register. Offset:900h + (ep_num * 20h) + 10h */ ++ volatile uint32_t dieptsiz; ++ /** Device IN Endpoint DMA Address Register. Offset:900h + ++ * (ep_num * 20h) + 14h */ ++ volatile uint32_t diepdma; ++ /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + ++ * (ep_num * 20h) + 18h */ ++ volatile uint32_t dtxfsts; ++ /** Device IN Endpoint DMA Buffer Register. Offset:900h + ++ * (ep_num * 20h) + 1Ch */ ++ volatile uint32_t diepdmab; ++} dwc_otg_dev_in_ep_regs_t; ++ ++/** ++ * Device Logical OUT Endpoint-Specific Registers. Offsets: ++ * B00h-CFCh ++ * ++ * There will be one set of endpoint registers per logical endpoint ++ * implemented. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_out_ep_regs { ++ /** Device OUT Endpoint Control Register. Offset:B00h + ++ * (ep_num * 20h) + 00h */ ++ volatile uint32_t doepctl; ++ /** Reserved. Offset:B00h + (ep_num * 20h) + 04h */ ++ uint32_t reserved04; ++ /** Device OUT Endpoint Interrupt Register. Offset:B00h + ++ * (ep_num * 20h) + 08h */ ++ volatile uint32_t doepint; ++ /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ ++ uint32_t reserved0C; ++ /** Device OUT Endpoint Transfer Size Register. Offset: ++ * B00h + (ep_num * 20h) + 10h */ ++ volatile uint32_t doeptsiz; ++ /** Device OUT Endpoint DMA Address Register. Offset:B00h ++ * + (ep_num * 20h) + 14h */ ++ volatile uint32_t doepdma; ++ /** Reserved. Offset:B00h + * (ep_num * 20h) + 18h */ ++ uint32_t unused; ++ /** Device OUT Endpoint DMA Buffer Register. Offset:B00h ++ * + (ep_num * 20h) + 1Ch */ ++ uint32_t doepdmab; ++} dwc_otg_dev_out_ep_regs_t; ++ ++/** ++ * This union represents the bit fields in the Device EP Control ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union depctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Maximum Packet Size ++ * IN/OUT EPn ++ * IN/OUT EP0 - 2 bits ++ * 2'b00: 64 Bytes ++ * 2'b01: 32 ++ * 2'b10: 16 ++ * 2'b11: 8 */ ++ unsigned mps:11; ++#define DWC_DEP0CTL_MPS_64 0 ++#define DWC_DEP0CTL_MPS_32 1 ++#define DWC_DEP0CTL_MPS_16 2 ++#define DWC_DEP0CTL_MPS_8 3 ++ ++ /** Next Endpoint ++ * IN EPn/IN EP0 ++ * OUT EPn/OUT EP0 - reserved */ ++ unsigned nextep:4; ++ ++ /** USB Active Endpoint */ ++ unsigned usbactep:1; ++ ++ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) ++ * This field contains the PID of the packet going to ++ * be received or transmitted on this endpoint. The ++ * application should program the PID of the first ++ * packet going to be received or transmitted on this ++ * endpoint , after the endpoint is ++ * activated. Application use the SetD1PID and ++ * SetD0PID fields of this register to program either ++ * D0 or D1 PID. ++ * ++ * The encoding for this field is ++ * - 0: D0 ++ * - 1: D1 ++ */ ++ unsigned dpid:1; ++ ++ /** NAK Status */ ++ unsigned naksts:1; ++ ++ /** Endpoint Type ++ * 2'b00: Control ++ * 2'b01: Isochronous ++ * 2'b10: Bulk ++ * 2'b11: Interrupt */ ++ unsigned eptype:2; ++ ++ /** Snoop Mode ++ * OUT EPn/OUT EP0 ++ * IN EPn/IN EP0 - reserved */ ++ unsigned snp:1; ++ ++ /** Stall Handshake */ ++ unsigned stall:1; ++ ++ /** Tx Fifo Number ++ * IN EPn/IN EP0 ++ * OUT EPn/OUT EP0 - reserved */ ++ unsigned txfnum:4; ++ ++ /** Clear NAK */ ++ unsigned cnak:1; ++ /** Set NAK */ ++ unsigned snak:1; ++ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) ++ * Writing to this field sets the Endpoint DPID (DPID) ++ * field in this register to DATA0. Set Even ++ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) ++ * Writing to this field sets the Even/Odd ++ * (micro)frame (EO_FrNum) field to even (micro) ++ * frame. ++ */ ++ unsigned setd0pid:1; ++ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) ++ * Writing to this field sets the Endpoint DPID (DPID) ++ * field in this register to DATA1 Set Odd ++ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) ++ * Writing to this field sets the Even/Odd ++ * (micro)frame (EO_FrNum) field to odd (micro) frame. ++ */ ++ unsigned setd1pid:1; ++ ++ /** Endpoint Disable */ ++ unsigned epdis:1; ++ /** Endpoint Enable */ ++ unsigned epena:1; ++ } b; ++} depctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Device EP Transfer ++ * Size Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union deptsiz_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer size */ ++ unsigned xfersize:19; ++/** Max packet count for EP (pow(2,10)-1) */ ++#define MAX_PKT_CNT 1023 ++ /** Packet Count */ ++ unsigned pktcnt:10; ++ /** Multi Count - Periodic IN endpoints */ ++ unsigned mc:2; ++ unsigned reserved:1; ++ } b; ++} deptsiz_data_t; ++ ++/** ++ * This union represents the bit fields in the Device EP 0 Transfer ++ * Size Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union deptsiz0_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer size */ ++ unsigned xfersize:7; ++ /** Reserved */ ++ unsigned reserved7_18:12; ++ /** Packet Count */ ++ unsigned pktcnt:2; ++ /** Reserved */ ++ unsigned reserved21_28:8; ++ /**Setup Packet Count (DOEPTSIZ0 Only) */ ++ unsigned supcnt:2; ++ unsigned reserved31; ++ } b; ++} deptsiz0_data_t; ++ ++///////////////////////////////////////////////// ++// DMA Descriptor Specific Structures ++// ++ ++/** Buffer status definitions */ ++ ++#define BS_HOST_READY 0x0 ++#define BS_DMA_BUSY 0x1 ++#define BS_DMA_DONE 0x2 ++#define BS_HOST_BUSY 0x3 ++ ++/** Receive/Transmit status definitions */ ++ ++#define RTS_SUCCESS 0x0 ++#define RTS_BUFFLUSH 0x1 ++#define RTS_RESERVED 0x2 ++#define RTS_BUFERR 0x3 ++ ++/** ++ * This union represents the bit fields in the DMA Descriptor ++ * status quadlet. Read the quadlet into the d32 member then ++ * set/clear the bits using the bit, b_iso_out and ++ * b_iso_in elements. ++ */ ++typedef union dev_dma_desc_sts { ++ /** raw register data */ ++ uint32_t d32; ++ /** quadlet bits */ ++ struct { ++ /** Received number of bytes */ ++ unsigned bytes:16; ++ /** NAK bit - only for OUT EPs */ ++ unsigned nak:1; ++ unsigned reserved17_22:6; ++ /** Multiple Transfer - only for OUT EPs */ ++ unsigned mtrf:1; ++ /** Setup Packet received - only for OUT EPs */ ++ unsigned sr:1; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Receive Status */ ++ unsigned sts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b; ++ ++//#ifdef DWC_EN_ISOC ++ /** iso out quadlet bits */ ++ struct { ++ /** Received number of bytes */ ++ unsigned rxbytes:11; ++ ++ unsigned reserved11:1; ++ /** Frame Number */ ++ unsigned framenum:11; ++ /** Received ISO Data PID */ ++ unsigned pid:2; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Receive Status */ ++ unsigned rxsts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b_iso_out; ++ ++ /** iso in quadlet bits */ ++ struct { ++ /** Transmited number of bytes */ ++ unsigned txbytes:12; ++ /** Frame Number */ ++ unsigned framenum:11; ++ /** Transmited ISO Data PID */ ++ unsigned pid:2; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Transmit Status */ ++ unsigned txsts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b_iso_in; ++//#endif /* DWC_EN_ISOC */ ++} dev_dma_desc_sts_t; ++ ++/** ++ * DMA Descriptor structure ++ * ++ * DMA Descriptor structure contains two quadlets: ++ * Status quadlet and Data buffer pointer. ++ */ ++typedef struct dwc_otg_dev_dma_desc { ++ /** DMA Descriptor status quadlet */ ++ dev_dma_desc_sts_t status; ++ /** DMA Descriptor data buffer pointer */ ++ uint32_t buf; ++} dwc_otg_dev_dma_desc_t; ++ ++/** ++ * The dwc_otg_dev_if structure contains information needed to manage ++ * the DWC_otg controller acting in device mode. It represents the ++ * programming view of the device-specific aspects of the controller. ++ */ ++typedef struct dwc_otg_dev_if { ++ /** Pointer to device Global registers. ++ * Device Global Registers starting at offset 800h ++ */ ++ dwc_otg_device_global_regs_t *dev_global_regs; ++#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 ++ ++ /** ++ * Device Logical IN Endpoint-Specific Registers 900h-AFCh ++ */ ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; ++#define DWC_DEV_IN_EP_REG_OFFSET 0x900 ++#define DWC_EP_REG_OFFSET 0x20 ++ ++ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; ++#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 ++ ++ /* Device configuration information */ ++ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ ++ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ ++ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ ++ ++ /** Size of periodic FIFOs (Bytes) */ ++ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ ++ /** Size of Tx FIFOs (Bytes) */ ++ uint16_t tx_fifo_size[MAX_TX_FIFOS]; ++ ++ /** Thresholding enable flags and length varaiables **/ ++ uint16_t rx_thr_en; ++ uint16_t iso_tx_thr_en; ++ uint16_t non_iso_tx_thr_en; ++ ++ uint16_t rx_thr_length; ++ uint16_t tx_thr_length; ++ ++ /** ++ * Pointers to the DMA Descriptors for EP0 Control ++ * transfers (virtual and physical) ++ */ ++ ++ /** 2 descriptors for SETUP packets */ ++ dwc_dma_t dma_setup_desc_addr[2]; ++ dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; ++ ++ /** Pointer to Descriptor with latest SETUP packet */ ++ dwc_otg_dev_dma_desc_t *psetup; ++ ++ /** Index of current SETUP handler descriptor */ ++ uint32_t setup_desc_index; ++ ++ /** Descriptor for Data In or Status In phases */ ++ dwc_dma_t dma_in_desc_addr; ++ dwc_otg_dev_dma_desc_t *in_desc_addr; ++ ++ /** Descriptor for Data Out or Status Out phases */ ++ dwc_dma_t dma_out_desc_addr; ++ dwc_otg_dev_dma_desc_t *out_desc_addr; ++ ++ /** Setup Packet Detected - if set clear NAK when queueing */ ++ uint32_t spd; ++ /** Isoc ep pointer on which incomplete happens */ ++ void *isoc_ep; ++ ++} dwc_otg_dev_if_t; ++ ++///////////////////////////////////////////////// ++// Host Mode Register Structures ++// ++/** ++ * The Host Global Registers structure defines the size and relative ++ * field offsets for the Host Mode Global Registers. Host Global ++ * Registers offsets 400h-7FFh. ++*/ ++typedef struct dwc_otg_host_global_regs { ++ /** Host Configuration Register. Offset: 400h */ ++ volatile uint32_t hcfg; ++ /** Host Frame Interval Register. Offset: 404h */ ++ volatile uint32_t hfir; ++ /** Host Frame Number / Frame Remaining Register. Offset: 408h */ ++ volatile uint32_t hfnum; ++ /** Reserved. Offset: 40Ch */ ++ uint32_t reserved40C; ++ /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ ++ volatile uint32_t hptxsts; ++ /** Host All Channels Interrupt Register. Offset: 414h */ ++ volatile uint32_t haint; ++ /** Host All Channels Interrupt Mask Register. Offset: 418h */ ++ volatile uint32_t haintmsk; ++ /** Host Frame List Base Address Register . Offset: 41Ch */ ++ volatile uint32_t hflbaddr; ++} dwc_otg_host_global_regs_t; ++ ++/** ++ * This union represents the bit fields in the Host Configuration Register. ++ * Read the register into the d32 member then set/clear the bits using ++ * the bit elements. Write the d32 member to the hcfg register. ++ */ ++typedef union hcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** FS/LS Phy Clock Select */ ++ unsigned fslspclksel:2; ++#define DWC_HCFG_30_60_MHZ 0 ++#define DWC_HCFG_48_MHZ 1 ++#define DWC_HCFG_6_MHZ 2 ++ ++ /** FS/LS Only Support */ ++ unsigned fslssupp:1; ++ unsigned reserved3_6:4; ++ /** Enable 32-KHz Suspend Mode */ ++ unsigned ena32khzs:1; ++ /** Resume Validation Periiod */ ++ unsigned resvalid:8; ++ unsigned reserved16_22:7; ++ /** Enable Scatter/gather DMA in Host mode */ ++ unsigned descdma:1; ++ /** Frame List Entries */ ++ unsigned frlisten:2; ++ /** Enable Periodic Scheduling */ ++ unsigned perschedena:1; ++ unsigned reserved27_30:4; ++ unsigned modechtimen:1; ++ } b; ++} hcfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Frame Remaing/Number ++ * Register. ++ */ ++typedef union hfir_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned frint:16; ++ unsigned hfirrldctrl:1; ++ unsigned reserved:15; ++ } b; ++} hfir_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Frame Remaing/Number ++ * Register. ++ */ ++typedef union hfnum_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned frnum:16; ++#define DWC_HFNUM_MAX_FRNUM 0x3FFF ++ unsigned frrem:16; ++ } b; ++} hfnum_data_t; ++ ++typedef union hptxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned ptxfspcavail:16; ++ unsigned ptxqspcavail:8; ++ /** Top of the Periodic Transmit Request Queue ++ * - bit 24 - Terminate (last entry for the selected channel) ++ * - bits 26:25 - Token Type ++ * - 2'b00 - Zero length ++ * - 2'b01 - Ping ++ * - 2'b10 - Disable ++ * - bits 30:27 - Channel Number ++ * - bit 31 - Odd/even microframe ++ */ ++ unsigned ptxqtop_terminate:1; ++ unsigned ptxqtop_token:2; ++ unsigned ptxqtop_chnum:4; ++ unsigned ptxqtop_odd:1; ++ } b; ++} hptxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Port Control and Status ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hprt0 register. ++ */ ++typedef union hprt0_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned prtconnsts:1; ++ unsigned prtconndet:1; ++ unsigned prtena:1; ++ unsigned prtenchng:1; ++ unsigned prtovrcurract:1; ++ unsigned prtovrcurrchng:1; ++ unsigned prtres:1; ++ unsigned prtsusp:1; ++ unsigned prtrst:1; ++ unsigned reserved9:1; ++ unsigned prtlnsts:2; ++ unsigned prtpwr:1; ++ unsigned prttstctl:4; ++ unsigned prtspd:2; ++#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 ++#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 ++#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 ++ unsigned reserved19_31:13; ++ } b; ++} hprt0_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union haint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ch0:1; ++ unsigned ch1:1; ++ unsigned ch2:1; ++ unsigned ch3:1; ++ unsigned ch4:1; ++ unsigned ch5:1; ++ unsigned ch6:1; ++ unsigned ch7:1; ++ unsigned ch8:1; ++ unsigned ch9:1; ++ unsigned ch10:1; ++ unsigned ch11:1; ++ unsigned ch12:1; ++ unsigned ch13:1; ++ unsigned ch14:1; ++ unsigned ch15:1; ++ unsigned reserved:16; ++ } b; ++ ++ struct { ++ unsigned chint:16; ++ unsigned reserved:16; ++ } b2; ++} haint_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union haintmsk_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ch0:1; ++ unsigned ch1:1; ++ unsigned ch2:1; ++ unsigned ch3:1; ++ unsigned ch4:1; ++ unsigned ch5:1; ++ unsigned ch6:1; ++ unsigned ch7:1; ++ unsigned ch8:1; ++ unsigned ch9:1; ++ unsigned ch10:1; ++ unsigned ch11:1; ++ unsigned ch12:1; ++ unsigned ch13:1; ++ unsigned ch14:1; ++ unsigned ch15:1; ++ unsigned reserved:16; ++ } b; ++ ++ struct { ++ unsigned chint:16; ++ unsigned reserved:16; ++ } b2; ++} haintmsk_data_t; ++ ++/** ++ * Host Channel Specific Registers. 500h-5FCh ++ */ ++typedef struct dwc_otg_hc_regs { ++ /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ ++ volatile uint32_t hcchar; ++ /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ ++ volatile uint32_t hcsplt; ++ /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ ++ volatile uint32_t hcint; ++ /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ ++ volatile uint32_t hcintmsk; ++ /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ ++ volatile uint32_t hctsiz; ++ /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ ++ volatile uint32_t hcdma; ++ volatile uint32_t reserved; ++ /** Host Channel 0 DMA Buffer Address Register. Offset: 500h + (chan_num * 20h) + 1Ch */ ++ volatile uint32_t hcdmab; ++} dwc_otg_hc_regs_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Characteristics ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcchar register. ++ */ ++typedef union hcchar_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Maximum packet size in bytes */ ++ unsigned mps:11; ++ ++ /** Endpoint number */ ++ unsigned epnum:4; ++ ++ /** 0: OUT, 1: IN */ ++ unsigned epdir:1; ++ ++ unsigned reserved:1; ++ ++ /** 0: Full/high speed device, 1: Low speed device */ ++ unsigned lspddev:1; ++ ++ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ ++ unsigned eptype:2; ++ ++ /** Packets per frame for periodic transfers. 0 is reserved. */ ++ unsigned multicnt:2; ++ ++ /** Device address */ ++ unsigned devaddr:7; ++ ++ /** ++ * Frame to transmit periodic transaction. ++ * 0: even, 1: odd ++ */ ++ unsigned oddfrm:1; ++ ++ /** Channel disable */ ++ unsigned chdis:1; ++ ++ /** Channel enable */ ++ unsigned chen:1; ++ } b; ++} hcchar_data_t; ++ ++typedef union hcsplt_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Port Address */ ++ unsigned prtaddr:7; ++ ++ /** Hub Address */ ++ unsigned hubaddr:7; ++ ++ /** Transaction Position */ ++ unsigned xactpos:2; ++#define DWC_HCSPLIT_XACTPOS_MID 0 ++#define DWC_HCSPLIT_XACTPOS_END 1 ++#define DWC_HCSPLIT_XACTPOS_BEGIN 2 ++#define DWC_HCSPLIT_XACTPOS_ALL 3 ++ ++ /** Do Complete Split */ ++ unsigned compsplt:1; ++ ++ /** Reserved */ ++ unsigned reserved:14; ++ ++ /** Split Enble */ ++ unsigned spltena:1; ++ } b; ++} hcsplt_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union hcint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer Complete */ ++ unsigned xfercomp:1; ++ /** Channel Halted */ ++ unsigned chhltd:1; ++ /** AHB Error */ ++ unsigned ahberr:1; ++ /** STALL Response Received */ ++ unsigned stall:1; ++ /** NAK Response Received */ ++ unsigned nak:1; ++ /** ACK Response Received */ ++ unsigned ack:1; ++ /** NYET Response Received */ ++ unsigned nyet:1; ++ /** Transaction Err */ ++ unsigned xacterr:1; ++ /** Babble Error */ ++ unsigned bblerr:1; ++ /** Frame Overrun */ ++ unsigned frmovrun:1; ++ /** Data Toggle Error */ ++ unsigned datatglerr:1; ++ /** Buffer Not Available (only for DDMA mode) */ ++ unsigned bna:1; ++ /** Exessive transaction error (only for DDMA mode) */ ++ unsigned xcs_xact:1; ++ /** Frame List Rollover interrupt */ ++ unsigned frm_list_roll:1; ++ /** Reserved */ ++ unsigned reserved14_31:18; ++ } b; ++} hcint_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Interrupt Mask ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcintmsk register. ++ */ ++typedef union hcintmsk_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned xfercompl:1; ++ unsigned chhltd:1; ++ unsigned ahberr:1; ++ unsigned stall:1; ++ unsigned nak:1; ++ unsigned ack:1; ++ unsigned nyet:1; ++ unsigned xacterr:1; ++ unsigned bblerr:1; ++ unsigned frmovrun:1; ++ unsigned datatglerr:1; ++ unsigned bna:1; ++ unsigned xcs_xact:1; ++ unsigned frm_list_roll:1; ++ unsigned reserved14_31:18; ++ } b; ++} hcintmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Transfer Size ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcchar register. ++ */ ++ ++typedef union hctsiz_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Total transfer size in bytes */ ++ unsigned xfersize:19; ++ ++ /** Data packets to transfer */ ++ unsigned pktcnt:10; ++ ++ /** ++ * Packet ID for next data packet ++ * 0: DATA0 ++ * 1: DATA2 ++ * 2: DATA1 ++ * 3: MDATA (non-Control), SETUP (Control) ++ */ ++ unsigned pid:2; ++#define DWC_HCTSIZ_DATA0 0 ++#define DWC_HCTSIZ_DATA1 2 ++#define DWC_HCTSIZ_DATA2 1 ++#define DWC_HCTSIZ_MDATA 3 ++#define DWC_HCTSIZ_SETUP 3 ++ ++ /** Do PING protocol when 1 */ ++ unsigned dopng:1; ++ } b; ++ ++ /** register bits */ ++ struct { ++ /** Scheduling information */ ++ unsigned schinfo:8; ++ ++ /** Number of transfer descriptors. ++ * Max value: ++ * 64 in general, ++ * 256 only for HS isochronous endpoint. ++ */ ++ unsigned ntd:8; ++ ++ /** Data packets to transfer */ ++ unsigned reserved16_28:13; ++ ++ /** ++ * Packet ID for next data packet ++ * 0: DATA0 ++ * 1: DATA2 ++ * 2: DATA1 ++ * 3: MDATA (non-Control) ++ */ ++ unsigned pid:2; ++ ++ /** Do PING protocol when 1 */ ++ unsigned dopng:1; ++ } b_ddma; ++} hctsiz_data_t; ++ ++/** ++ * This union represents the bit fields in the Host DMA Address ++ * Register used in Descriptor DMA mode. ++ */ ++typedef union hcdma_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved0_2:3; ++ /** Current Transfer Descriptor. Not used for ISOC */ ++ unsigned ctd:8; ++ /** Start Address of Descriptor List */ ++ unsigned dma_addr:21; ++ } b; ++} hcdma_data_t; ++ ++/** ++ * This union represents the bit fields in the DMA Descriptor ++ * status quadlet for host mode. Read the quadlet into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union host_dma_desc_sts { ++ /** raw register data */ ++ uint32_t d32; ++ /** quadlet bits */ ++ ++ /* for non-isochronous */ ++ struct { ++ /** Number of bytes */ ++ unsigned n_bytes:17; ++ /** QTD offset to jump when Short Packet received - only for IN EPs */ ++ unsigned qtd_offset:6; ++ /** ++ * Set to request the core to jump to alternate QTD if ++ * Short Packet received - only for IN EPs ++ */ ++ unsigned a_qtd:1; ++ /** ++ * Setup Packet bit. When set indicates that buffer contains ++ * setup packet. ++ */ ++ unsigned sup:1; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** End of List */ ++ unsigned eol:1; ++ unsigned reserved27:1; ++ /** Rx/Tx Status */ ++ unsigned sts:2; ++#define DMA_DESC_STS_PKTERR 1 ++ unsigned reserved30:1; ++ /** Active Bit */ ++ unsigned a:1; ++ } b; ++ /* for isochronous */ ++ struct { ++ /** Number of bytes */ ++ unsigned n_bytes:12; ++ unsigned reserved12_24:13; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ unsigned reserved26_27:2; ++ /** Rx/Tx Status */ ++ unsigned sts:2; ++ unsigned reserved30:1; ++ /** Active Bit */ ++ unsigned a:1; ++ } b_isoc; ++} host_dma_desc_sts_t; ++ ++#define MAX_DMA_DESC_SIZE 131071 ++#define MAX_DMA_DESC_NUM_GENERIC 64 ++#define MAX_DMA_DESC_NUM_HS_ISOC 256 ++#define MAX_FRLIST_EN_NUM 64 ++/** ++ * Host-mode DMA Descriptor structure ++ * ++ * DMA Descriptor structure contains two quadlets: ++ * Status quadlet and Data buffer pointer. ++ */ ++typedef struct dwc_otg_host_dma_desc { ++ /** DMA Descriptor status quadlet */ ++ host_dma_desc_sts_t status; ++ /** DMA Descriptor data buffer pointer */ ++ uint32_t buf; ++} dwc_otg_host_dma_desc_t; ++ ++/** OTG Host Interface Structure. ++ * ++ * The OTG Host Interface Structure structure contains information ++ * needed to manage the DWC_otg controller acting in host mode. It ++ * represents the programming view of the host-specific aspects of the ++ * controller. ++ */ ++typedef struct dwc_otg_host_if { ++ /** Host Global Registers starting at offset 400h.*/ ++ dwc_otg_host_global_regs_t *host_global_regs; ++#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 ++ ++ /** Host Port 0 Control and Status Register */ ++ volatile uint32_t *hprt0; ++#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 ++ ++ /** Host Channel Specific Registers at offsets 500h-5FCh. */ ++ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; ++#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 ++#define DWC_OTG_CHAN_REGS_OFFSET 0x20 ++ ++ /* Host configuration information */ ++ /** Number of Host Channels (range: 1-16) */ ++ uint8_t num_host_channels; ++ /** Periodic EPs supported (0: no, 1: yes) */ ++ uint8_t perio_eps_supported; ++ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ ++ uint16_t perio_tx_fifo_size; ++ ++} dwc_otg_host_if_t; ++ ++/** ++ * This union represents the bit fields in the Power and Clock Gating Control ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union pcgcctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Stop Pclk */ ++ unsigned stoppclk:1; ++ /** Gate Hclk */ ++ unsigned gatehclk:1; ++ /** Power Clamp */ ++ unsigned pwrclmp:1; ++ /** Reset Power Down Modules */ ++ unsigned rstpdwnmodule:1; ++ /** Reserved */ ++ unsigned reserved:1; ++ /** Enable Sleep Clock Gating (Enbl_L1Gating) */ ++ unsigned enbl_sleep_gating:1; ++ /** PHY In Sleep (PhySleep) */ ++ unsigned phy_in_sleep:1; ++ /** Deep Sleep*/ ++ unsigned deep_sleep:1; ++ unsigned resetaftsusp:1; ++ unsigned restoremode:1; ++ unsigned enbl_extnd_hiber:1; ++ unsigned extnd_hiber_pwrclmp:1; ++ unsigned extnd_hiber_switch:1; ++ unsigned ess_reg_restored:1; ++ unsigned prt_clk_sel:2; ++ unsigned port_power:1; ++ unsigned max_xcvrselect:2; ++ unsigned max_termsel:1; ++ unsigned mac_dev_addr:7; ++ unsigned p2hd_dev_enum_spd:2; ++ unsigned p2hd_prt_spd:2; ++ unsigned if_dev_mode:1; ++ } b; ++} pcgcctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Global Data FIFO Software ++ * Configuration Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union gdfifocfg_data { ++ /* raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** OTG Data FIFO depth */ ++ unsigned gdfifocfg:16; ++ /** Start address of EP info controller */ ++ unsigned epinfobase:16; ++ } b; ++} gdfifocfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Global Power Down Register ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union gpwrdn_data { ++ /* raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** PMU Interrupt Select */ ++ unsigned pmuintsel:1; ++ /** PMU Active */ ++ unsigned pmuactv:1; ++ /** Restore */ ++ unsigned restore:1; ++ /** Power Down Clamp */ ++ unsigned pwrdnclmp:1; ++ /** Power Down Reset */ ++ unsigned pwrdnrstn:1; ++ /** Power Down Switch */ ++ unsigned pwrdnswtch:1; ++ /** Disable VBUS */ ++ unsigned dis_vbus:1; ++ /** Line State Change */ ++ unsigned lnstschng:1; ++ /** Line state change mask */ ++ unsigned lnstchng_msk:1; ++ /** Reset Detected */ ++ unsigned rst_det:1; ++ /** Reset Detect mask */ ++ unsigned rst_det_msk:1; ++ /** Disconnect Detected */ ++ unsigned disconn_det:1; ++ /** Disconnect Detect mask */ ++ unsigned disconn_det_msk:1; ++ /** Connect Detected*/ ++ unsigned connect_det:1; ++ /** Connect Detected Mask*/ ++ unsigned connect_det_msk:1; ++ /** SRP Detected */ ++ unsigned srp_det:1; ++ /** SRP Detect mask */ ++ unsigned srp_det_msk:1; ++ /** Status Change Interrupt */ ++ unsigned sts_chngint:1; ++ /** Status Change Interrupt Mask */ ++ unsigned sts_chngint_msk:1; ++ /** Line State */ ++ unsigned linestate:2; ++ /** Indicates current mode(status of IDDIG signal) */ ++ unsigned idsts:1; ++ /** B Session Valid signal status*/ ++ unsigned bsessvld:1; ++ /** ADP Event Detected */ ++ unsigned adp_int:1; ++ /** Multi Valued ID pin */ ++ unsigned mult_val_id_bc:5; ++ /** Reserved 24_31 */ ++ unsigned reserved29_31:3; ++ } b; ++} gpwrdn_data_t; ++ ++#endif +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/test/Makefile +@@ -0,0 +1,16 @@ ++ ++PERL=/usr/bin/perl ++PL_TESTS=test_sysfs.pl test_mod_param.pl ++ ++.PHONY : test ++test : perl_tests ++ ++perl_tests : ++ @echo ++ @echo Running perl tests ++ @for test in $(PL_TESTS); do \ ++ if $(PERL) ./$$test ; then \ ++ echo "=======> $$test, PASSED" ; \ ++ else echo "=======> $$test, FAILED" ; \ ++ fi \ ++ done +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm +@@ -0,0 +1,337 @@ ++package dwc_otg_test; ++ ++use strict; ++use Exporter (); ++ ++use vars qw(@ISA @EXPORT ++$sysfsdir $paramdir $errors $params ++); ++ ++@ISA = qw(Exporter); ++ ++# ++# Globals ++# ++$sysfsdir = "/sys/devices/lm0"; ++$paramdir = "/sys/module/dwc_otg"; ++$errors = 0; ++ ++$params = [ ++ { ++ NAME => "otg_cap", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 2 ++ }, ++ { ++ NAME => "dma_enable", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "dma_burst_size", ++ DEFAULT => 32, ++ ENUM => [1, 4, 8, 16, 32, 64, 128, 256], ++ LOW => 1, ++ HIGH => 256 ++ }, ++ { ++ NAME => "host_speed", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "host_support_fs_ls_low_power", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "host_ls_low_power_phy_clk", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "dev_speed", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "enable_dynamic_fifo", ++ DEFAULT => 1, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "data_fifo_size", ++ DEFAULT => 8192, ++ ENUM => [], ++ LOW => 32, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_rx_fifo_size", ++ DEFAULT => 1064, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_nperio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_1", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_2", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_3", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_4", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_5", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_6", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_7", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_8", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_9", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_10", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_11", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_12", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_13", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_14", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_15", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "host_rx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "host_nperio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "host_perio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "max_transfer_size", ++ DEFAULT => 65535, ++ ENUM => [], ++ LOW => 2047, ++ HIGH => 65535 ++ }, ++ { ++ NAME => "max_packet_count", ++ DEFAULT => 511, ++ ENUM => [], ++ LOW => 15, ++ HIGH => 511 ++ }, ++ { ++ NAME => "host_channels", ++ DEFAULT => 12, ++ ENUM => [], ++ LOW => 1, ++ HIGH => 16 ++ }, ++ { ++ NAME => "dev_endpoints", ++ DEFAULT => 6, ++ ENUM => [], ++ LOW => 1, ++ HIGH => 15 ++ }, ++ { ++ NAME => "phy_type", ++ DEFAULT => 1, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 2 ++ }, ++ { ++ NAME => "phy_utmi_width", ++ DEFAULT => 16, ++ ENUM => [8, 16], ++ LOW => 8, ++ HIGH => 16 ++ }, ++ { ++ NAME => "phy_ulpi_ddr", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ ]; ++ ++ ++# ++# ++sub check_arch { ++ $_ = `uname -m`; ++ chomp; ++ unless (m/armv4tl/) { ++ warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n"; ++ return 0; ++ } ++ return 1; ++} ++ ++# ++# ++sub load_module { ++ my $params = shift; ++ print "\nRemoving Module\n"; ++ system "rmmod dwc_otg"; ++ print "Loading Module\n"; ++ if ($params ne "") { ++ print "Module Parameters: $params\n"; ++ } ++ if (system("modprobe dwc_otg $params")) { ++ warn "Unable to load module\n"; ++ return 0; ++ } ++ return 1; ++} ++ ++# ++# ++sub test_status { ++ my $arg = shift; ++ ++ print "\n"; ++ ++ if (defined $arg) { ++ warn "WARNING: $arg\n"; ++ } ++ ++ if ($errors > 0) { ++ warn "TEST FAILED with $errors errors\n"; ++ return 0; ++ } else { ++ print "TEST PASSED\n"; ++ return 0 if (defined $arg); ++ } ++ return 1; ++} ++ ++# ++# ++@EXPORT = qw( ++$sysfsdir ++$paramdir ++$params ++$errors ++check_arch ++load_module ++test_status ++); ++ ++1; +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/test/test_mod_param.pl +@@ -0,0 +1,133 @@ ++#!/usr/bin/perl -w ++# ++# Run this program on the integrator. ++# ++# - Tests module parameter default values. ++# - Tests setting of valid module parameter values via modprobe. ++# - Tests invalid module parameter values. ++# ----------------------------------------------------------------------------- ++use strict; ++use dwc_otg_test; ++ ++check_arch() or die; ++ ++# ++# ++sub test { ++ my ($param,$expected) = @_; ++ my $value = get($param); ++ ++ if ($value == $expected) { ++ print "$param = $value, okay\n"; ++ } ++ ++ else { ++ warn "ERROR: value of $param != $expected, $value\n"; ++ $errors ++; ++ } ++} ++ ++# ++# ++sub get { ++ my $param = shift; ++ my $tmp = `cat $paramdir/$param`; ++ chomp $tmp; ++ return $tmp; ++} ++ ++# ++# ++sub test_main { ++ ++ print "\nTesting Module Parameters\n"; ++ ++ load_module("") or die; ++ ++ # Test initial values ++ print "\nTesting Default Values\n"; ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ # Test low value ++ print "\nTesting Low Value\n"; ++ my $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} "; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{LOW}); ++ } ++ ++ # Test high value ++ print "\nTesting High Value\n"; ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} "; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{HIGH}); ++ } ++ ++ # Test Enum ++ print "\nTesting Enumerated\n"; ++ foreach (@{$params}) { ++ if (defined $_->{ENUM}) { ++ my $value; ++ foreach $value (@{$_->{ENUM}}) { ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $value); ++ } ++ } ++ } ++ ++ # Test Invalid Values ++ print "\nTesting Invalid Values\n"; ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ print "\nTesting Enumerated\n"; ++ foreach (@{$params}) { ++ if (defined $_->{ENUM}) { ++ my $value; ++ foreach $value (@{$_->{ENUM}}) { ++ $value = $value + 1; ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $_->{DEFAULT}); ++ $value = $value - 2; ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ } ++ } ++ ++ test_status() or die; ++} ++ ++test_main(); ++0; +--- /dev/null ++++ b/drivers/usb/host/dwc_otg/test/test_sysfs.pl +@@ -0,0 +1,193 @@ ++#!/usr/bin/perl -w ++# ++# Run this program on the integrator ++# - Tests select sysfs attributes. ++# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc. ++# ----------------------------------------------------------------------------- ++use strict; ++use dwc_otg_test; ++ ++check_arch() or die; ++ ++# ++# ++sub test { ++ my ($attr,$expected) = @_; ++ my $string = get($attr); ++ ++ if ($string eq $expected) { ++ printf("$attr = $string, okay\n"); ++ } ++ else { ++ warn "ERROR: value of $attr != $expected, $string\n"; ++ $errors ++; ++ } ++} ++ ++# ++# ++sub set { ++ my ($reg, $value) = @_; ++ system "echo $value > $sysfsdir/$reg"; ++} ++ ++# ++# ++sub get { ++ my $attr = shift; ++ my $string = `cat $sysfsdir/$attr`; ++ chomp $string; ++ if ($string =~ m/\s\=\s/) { ++ my $tmp; ++ ($tmp, $string) = split /\s=\s/, $string; ++ } ++ return $string; ++} ++ ++# ++# ++sub test_main { ++ print("\nTesting Sysfs Attributes\n"); ++ ++ load_module("") or die; ++ ++ # Test initial values of regoffset/regvalue/guid/gsnpsid ++ print("\nTesting Default Values\n"); ++ ++ test("regoffset", "0xffffffff"); ++ test("regvalue", "invalid offset"); ++ test("guid", "0x12345678"); # this will fail if it has been changed ++ test("gsnpsid", "0x4f54200a"); ++ ++ # Test operation of regoffset/regvalue ++ print("\nTesting regoffset\n"); ++ set('regoffset', '5a5a5a5a'); ++ test("regoffset", "0xffffffff"); ++ ++ set('regoffset', '0'); ++ test("regoffset", "0x00000000"); ++ ++ set('regoffset', '40000'); ++ test("regoffset", "0x00000000"); ++ ++ set('regoffset', '3ffff'); ++ test("regoffset", "0x0003ffff"); ++ ++ set('regoffset', '1'); ++ test("regoffset", "0x00000001"); ++ ++ print("\nTesting regvalue\n"); ++ set('regoffset', '3c'); ++ test("regvalue", "0x12345678"); ++ set('regvalue', '5a5a5a5a'); ++ test("regvalue", "0x5a5a5a5a"); ++ set('regvalue','a5a5a5a5'); ++ test("regvalue", "0xa5a5a5a5"); ++ set('guid','12345678'); ++ ++ # Test HNP Capable ++ print("\nTesting HNP Capable bit\n"); ++ set('hnpcapable', '1'); ++ test("hnpcapable", "0x1"); ++ set('hnpcapable','0'); ++ test("hnpcapable", "0x0"); ++ ++ set('regoffset','0c'); ++ ++ my $old = get('gusbcfg'); ++ print("setting hnpcapable\n"); ++ set('hnpcapable', '1'); ++ test("hnpcapable", "0x1"); ++ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9))); ++ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9))); ++ ++ $old = get('gusbcfg'); ++ print("clearing hnpcapable\n"); ++ set('hnpcapable', '0'); ++ test("hnpcapable", "0x0"); ++ test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9))); ++ test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9))); ++ ++ # Test SRP Capable ++ print("\nTesting SRP Capable bit\n"); ++ set('srpcapable', '1'); ++ test("srpcapable", "0x1"); ++ set('srpcapable','0'); ++ test("srpcapable", "0x0"); ++ ++ set('regoffset','0c'); ++ ++ $old = get('gusbcfg'); ++ print("setting srpcapable\n"); ++ set('srpcapable', '1'); ++ test("srpcapable", "0x1"); ++ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8))); ++ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8))); ++ ++ $old = get('gusbcfg'); ++ print("clearing srpcapable\n"); ++ set('srpcapable', '0'); ++ test("srpcapable", "0x0"); ++ test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8))); ++ test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8))); ++ ++ # Test GGPIO ++ print("\nTesting GGPIO\n"); ++ set('ggpio','5a5a5a5a'); ++ test('ggpio','0x5a5a0000'); ++ set('ggpio','a5a5a5a5'); ++ test('ggpio','0xa5a50000'); ++ set('ggpio','11110000'); ++ test('ggpio','0x11110000'); ++ set('ggpio','00001111'); ++ test('ggpio','0x00000000'); ++ ++ # Test DEVSPEED ++ print("\nTesting DEVSPEED\n"); ++ set('regoffset','800'); ++ $old = get('regvalue'); ++ set('devspeed','0'); ++ test('devspeed','0x0'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3))); ++ set('devspeed','1'); ++ test('devspeed','0x1'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1)); ++ set('devspeed','2'); ++ test('devspeed','0x2'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2)); ++ set('devspeed','3'); ++ test('devspeed','0x3'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3)); ++ set('devspeed','4'); ++ test('devspeed','0x0'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3))); ++ set('devspeed','5'); ++ test('devspeed','0x1'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1)); ++ ++ ++ # mode Returns the current mode:0 for device mode1 for host mode Read ++ # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write ++ # srp Initiate the Session Request Protocol. Read returns the status. Read/Write ++ # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write ++ # bussuspend Suspend the USB bus. Read/Write ++ # busconnected Get the connection status of the bus Read ++ ++ # gotgctl Get or set the Core Control Status Register. Read/Write ++ ## gusbcfg Get or set the Core USB Configuration Register Read/Write ++ # grxfsiz Get or set the Receive FIFO Size Register Read/Write ++ # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write ++ # gpvndctl Get or set the PHY Vendor Control Register Read/Write ++ ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write ++ ## guid Get or set the value of the User ID Register Read/Write ++ ## gsnpsid Get the value of the Synopsys ID Regester Read ++ ## devspeed Get or set the device speed setting in the DCFG register Read/Write ++ # enumspeed Gets the device enumeration Speed. Read ++ # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read ++ # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write ++ ++ test_status("TEST NYI") or die; ++} ++ ++test_main(); ++0; diff --git a/target/linux/brcm2708/patches-4.1/0005-bcm2708-watchdog-driver.patch b/target/linux/brcm2708/patches-4.1/0005-bcm2708-watchdog-driver.patch new file mode 100644 index 0000000..6052a79 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0005-bcm2708-watchdog-driver.patch @@ -0,0 +1,432 @@ +From 128ae7510c357693222c635d3799b982142eb1b5 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 1 May 2013 19:54:32 +0100 +Subject: [PATCH 005/203] bcm2708 watchdog driver + +Signed-off-by: popcornmix +--- + drivers/watchdog/Kconfig | 8 +- + drivers/watchdog/Makefile | 1 + + drivers/watchdog/bcm2708_wdog.c | 382 ++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 390 insertions(+), 1 deletion(-) + create mode 100644 drivers/watchdog/bcm2708_wdog.c + +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -451,6 +451,12 @@ config RETU_WATCHDOG + To compile this driver as a module, choose M here: the + module will be called retu_wdt. + ++config BCM2708_WDT ++ tristate "BCM2708 Watchdog" ++ depends on ARCH_BCM2708 || ARCH_BCM2709 ++ help ++ Enables BCM2708 watchdog support. ++ + config MOXART_WDT + tristate "MOXART watchdog" + depends on ARCH_MOXART +@@ -1225,7 +1231,7 @@ config BCM63XX_WDT + + config BCM2835_WDT + tristate "Broadcom BCM2835 hardware watchdog" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + select WATCHDOG_CORE + help + Watchdog driver for the built in watchdog hardware in Broadcom +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -56,6 +56,7 @@ obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_ + obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o + obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o + obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o ++obj-$(CONFIG_BCM2708_WDT) += bcm2708_wdog.o + obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o + obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o + obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o +--- /dev/null ++++ b/drivers/watchdog/bcm2708_wdog.c +@@ -0,0 +1,382 @@ ++/* ++ * Broadcom BCM2708 watchdog driver. ++ * ++ * (c) Copyright 2010 Broadcom Europe Ltd ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * BCM2708 watchdog driver. Loosely based on wdt driver. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SECS_TO_WDOG_TICKS(x) ((x) << 16) ++#define WDOG_TICKS_TO_SECS(x) ((x) >> 16) ++ ++static unsigned long wdog_is_open; ++static uint32_t wdog_ticks; /* Ticks to load into wdog timer */ ++static char expect_close; ++ ++/* ++ * Module parameters ++ */ ++ ++#define WD_TIMO 10 /* Default heartbeat = 60 seconds */ ++static int heartbeat = WD_TIMO; /* Heartbeat in seconds */ ++ ++module_param(heartbeat, int, 0); ++MODULE_PARM_DESC(heartbeat, ++ "Watchdog heartbeat in seconds. (0 < heartbeat < 65536, default=" ++ __MODULE_STRING(WD_TIMO) ")"); ++ ++static int nowayout = WATCHDOG_NOWAYOUT; ++module_param(nowayout, int, 0); ++MODULE_PARM_DESC(nowayout, ++ "Watchdog cannot be stopped once started (default=" ++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); ++ ++static DEFINE_SPINLOCK(wdog_lock); ++ ++/** ++ * Start the watchdog driver. ++ */ ++ ++static int wdog_start(unsigned long timeout) ++{ ++ uint32_t cur; ++ unsigned long flags; ++ spin_lock_irqsave(&wdog_lock, flags); ++ ++ /* enable the watchdog */ ++ iowrite32(PM_PASSWORD | (timeout & PM_WDOG_TIME_SET), ++ __io_address(PM_WDOG)); ++ cur = ioread32(__io_address(PM_RSTC)); ++ iowrite32(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | ++ PM_RSTC_WRCFG_FULL_RESET, __io_address(PM_RSTC)); ++ ++ spin_unlock_irqrestore(&wdog_lock, flags); ++ return 0; ++} ++ ++/** ++ * Stop the watchdog driver. ++ */ ++ ++static int wdog_stop(void) ++{ ++ iowrite32(PM_PASSWORD | PM_RSTC_RESET, __io_address(PM_RSTC)); ++ printk(KERN_INFO "watchdog stopped\n"); ++ return 0; ++} ++ ++/** ++ * Reload counter one with the watchdog heartbeat. We don't bother ++ * reloading the cascade counter. ++ */ ++ ++static void wdog_ping(void) ++{ ++ wdog_start(wdog_ticks); ++} ++ ++/** ++ * @t: the new heartbeat value that needs to be set. ++ * ++ * Set a new heartbeat value for the watchdog device. If the heartbeat ++ * value is incorrect we keep the old value and return -EINVAL. If ++ * successful we return 0. ++ */ ++ ++static int wdog_set_heartbeat(int t) ++{ ++ if (t < 1 || t > WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET)) ++ return -EINVAL; ++ ++ heartbeat = t; ++ wdog_ticks = SECS_TO_WDOG_TICKS(t); ++ return 0; ++} ++ ++/** ++ * @file: file handle to the watchdog ++ * @buf: buffer to write (unused as data does not matter here ++ * @count: count of bytes ++ * @ppos: pointer to the position to write. No seeks allowed ++ * ++ * A write to a watchdog device is defined as a keepalive signal. ++ * ++ * if 'nowayout' is set then normally a close() is ignored. But ++ * if you write 'V' first then the close() will stop the timer. ++ */ ++ ++static ssize_t wdog_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ if (count) { ++ if (!nowayout) { ++ size_t i; ++ ++ /* In case it was set long ago */ ++ expect_close = 0; ++ ++ for (i = 0; i != count; i++) { ++ char c; ++ if (get_user(c, buf + i)) ++ return -EFAULT; ++ if (c == 'V') ++ expect_close = 42; ++ } ++ } ++ wdog_ping(); ++ } ++ return count; ++} ++ ++static int wdog_get_status(void) ++{ ++ unsigned long flags; ++ int status = 0; ++ spin_lock_irqsave(&wdog_lock, flags); ++ /* FIXME: readback reset reason */ ++ spin_unlock_irqrestore(&wdog_lock, flags); ++ return status; ++} ++ ++static uint32_t wdog_get_remaining(void) ++{ ++ uint32_t ret = ioread32(__io_address(PM_WDOG)); ++ return ret & PM_WDOG_TIME_SET; ++} ++ ++/** ++ * @file: file handle to the device ++ * @cmd: watchdog command ++ * @arg: argument pointer ++ * ++ * The watchdog API defines a common set of functions for all watchdogs ++ * according to their available features. We only actually usefully support ++ * querying capabilities and current status. ++ */ ++ ++static long wdog_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ void __user *argp = (void __user *)arg; ++ int __user *p = argp; ++ int new_heartbeat; ++ int status; ++ int options; ++ uint32_t remaining; ++ ++ struct watchdog_info ident = { ++ .options = WDIOF_SETTIMEOUT| ++ WDIOF_MAGICCLOSE| ++ WDIOF_KEEPALIVEPING, ++ .firmware_version = 1, ++ .identity = "BCM2708", ++ }; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; ++ case WDIOC_GETSTATUS: ++ status = wdog_get_status(); ++ return put_user(status, p); ++ case WDIOC_GETBOOTSTATUS: ++ return put_user(0, p); ++ case WDIOC_KEEPALIVE: ++ wdog_ping(); ++ return 0; ++ case WDIOC_SETTIMEOUT: ++ if (get_user(new_heartbeat, p)) ++ return -EFAULT; ++ if (wdog_set_heartbeat(new_heartbeat)) ++ return -EINVAL; ++ wdog_ping(); ++ /* Fall */ ++ case WDIOC_GETTIMEOUT: ++ return put_user(heartbeat, p); ++ case WDIOC_GETTIMELEFT: ++ remaining = WDOG_TICKS_TO_SECS(wdog_get_remaining()); ++ return put_user(remaining, p); ++ case WDIOC_SETOPTIONS: ++ if (get_user(options, p)) ++ return -EFAULT; ++ if (options & WDIOS_DISABLECARD) ++ wdog_stop(); ++ if (options & WDIOS_ENABLECARD) ++ wdog_start(wdog_ticks); ++ return 0; ++ default: ++ return -ENOTTY; ++ } ++} ++ ++/** ++ * @inode: inode of device ++ * @file: file handle to device ++ * ++ * The watchdog device has been opened. The watchdog device is single ++ * open and on opening we load the counters. ++ */ ++ ++static int wdog_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(0, &wdog_is_open)) ++ return -EBUSY; ++ /* ++ * Activate ++ */ ++ wdog_start(wdog_ticks); ++ return nonseekable_open(inode, file); ++} ++ ++/** ++ * @inode: inode to board ++ * @file: file handle to board ++ * ++ * The watchdog has a configurable API. There is a religious dispute ++ * between people who want their watchdog to be able to shut down and ++ * those who want to be sure if the watchdog manager dies the machine ++ * reboots. In the former case we disable the counters, in the latter ++ * case you have to open it again very soon. ++ */ ++ ++static int wdog_release(struct inode *inode, struct file *file) ++{ ++ if (expect_close == 42) { ++ wdog_stop(); ++ } else { ++ printk(KERN_CRIT ++ "wdt: WDT device closed unexpectedly. WDT will not stop!\n"); ++ wdog_ping(); ++ } ++ clear_bit(0, &wdog_is_open); ++ expect_close = 0; ++ return 0; ++} ++ ++/** ++ * @this: our notifier block ++ * @code: the event being reported ++ * @unused: unused ++ * ++ * Our notifier is called on system shutdowns. Turn the watchdog ++ * off so that it does not fire during the next reboot. ++ */ ++ ++static int wdog_notify_sys(struct notifier_block *this, unsigned long code, ++ void *unused) ++{ ++ if (code == SYS_DOWN || code == SYS_HALT) ++ wdog_stop(); ++ return NOTIFY_DONE; ++} ++ ++/* ++ * Kernel Interfaces ++ */ ++ ++ ++static const struct file_operations wdog_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = wdog_write, ++ .unlocked_ioctl = wdog_ioctl, ++ .open = wdog_open, ++ .release = wdog_release, ++}; ++ ++static struct miscdevice wdog_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &wdog_fops, ++}; ++ ++/* ++ * The WDT card needs to learn about soft shutdowns in order to ++ * turn the timebomb registers off. ++ */ ++ ++static struct notifier_block wdog_notifier = { ++ .notifier_call = wdog_notify_sys, ++}; ++ ++/** ++ * cleanup_module: ++ * ++ * Unload the watchdog. You cannot do this with any file handles open. ++ * If your watchdog is set to continue ticking on close and you unload ++ * it, well it keeps ticking. We won't get the interrupt but the board ++ * will not touch PC memory so all is fine. You just have to load a new ++ * module in 60 seconds or reboot. ++ */ ++ ++static void __exit wdog_exit(void) ++{ ++ misc_deregister(&wdog_miscdev); ++ unregister_reboot_notifier(&wdog_notifier); ++} ++ ++static int __init wdog_init(void) ++{ ++ int ret; ++ ++ /* Check that the heartbeat value is within it's range; ++ if not reset to the default */ ++ if (wdog_set_heartbeat(heartbeat)) { ++ wdog_set_heartbeat(WD_TIMO); ++ printk(KERN_INFO "bcm2708_wdog: heartbeat value must be " ++ "0 < heartbeat < %d, using %d\n", ++ WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), ++ WD_TIMO); ++ } ++ ++ ret = register_reboot_notifier(&wdog_notifier); ++ if (ret) { ++ printk(KERN_ERR ++ "wdt: cannot register reboot notifier (err=%d)\n", ret); ++ goto out_reboot; ++ } ++ ++ ret = misc_register(&wdog_miscdev); ++ if (ret) { ++ printk(KERN_ERR ++ "wdt: cannot register miscdev on minor=%d (err=%d)\n", ++ WATCHDOG_MINOR, ret); ++ goto out_misc; ++ } ++ ++ printk(KERN_INFO "bcm2708 watchdog, heartbeat=%d sec (nowayout=%d)\n", ++ heartbeat, nowayout); ++ return 0; ++ ++out_misc: ++ unregister_reboot_notifier(&wdog_notifier); ++out_reboot: ++ return ret; ++} ++ ++module_init(wdog_init); ++module_exit(wdog_exit); ++ ++MODULE_AUTHOR("Luke Diamand"); ++MODULE_DESCRIPTION("Driver for BCM2708 watchdog"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS_MISCDEV(TEMP_MINOR); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm2708/patches-4.1/0006-bcm2708-framebuffer-driver.patch b/target/linux/brcm2708/patches-4.1/0006-bcm2708-framebuffer-driver.patch new file mode 100644 index 0000000..b27d64c --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0006-bcm2708-framebuffer-driver.patch @@ -0,0 +1,3432 @@ +From 9c44d34f731221eb1f68a4f5454b33b11116de3d Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 17 Jun 2015 17:06:34 +0100 +Subject: [PATCH 006/203] bcm2708 framebuffer driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: popcornmix + +bcm2708_fb : Implement blanking support using the mailbox property interface + +bcm2708_fb: Add pan and vsync controls + +bcm2708_fb: DMA acceleration for fb_copyarea + +Based on http://www.raspberrypi.org/phpBB3/viewtopic.php?p=62425#p62425 +Also used Simon's dmaer_master module as a reference for tweaking DMA +settings for better performance. + +For now busylooping only. IRQ support might be added later. +With non-overclocked Raspberry Pi, the performance is ~360 MB/s +for simple copy or ~260 MB/s for two-pass copy (used when dragging +windows to the right). + +In the case of using DMA channel 0, the performance improves +to ~440 MB/s. + +For comparison, VFP optimized CPU copy can only do ~114 MB/s in +the same conditions (hindered by reading uncached source buffer). + +Signed-off-by: Siarhei Siamashka + +bcm2708_fb: report number of dma copies + +Add a counter (exported via debugfs) reporting the +number of dma copies that the framebuffer driver +has done, in order to help evaluate different +optimization strategies. + +Signed-off-by: Luke Diamand + +bcm2708_fb: use IRQ for DMA copies + +The copyarea ioctl() uses DMA to speed things along. This +was busy-waiting for completion. This change supports using +an interrupt instead for larger transfers. For small +transfers, busy-waiting is still likely to be faster. + +Signed-off-by: Luke Diamand + +bcm2708: Make ioctl logging quieter + +video: fbdev: bcm2708_fb: Don't panic on error + +No need to panic the kernel if the video driver fails. +Just print a message and return an error. + +Signed-off-by: Noralf Trønnes + +fbdev: bcm2708_fb: Add ARCH_BCM2835 support + +Add Device Tree support. +Pass the device to dma_alloc_coherent() in order to get the +correct bus address on ARCH_BCM2835. +Use the new DMA legacy API header file. +Including is not necessary. + +Signed-off-by: Noralf Trønnes + +BCM270x_DT: Add bcm2708-fb device + +Add bcm2708-fb to Device Tree and don't add the +platform device when booting in DT mode. + +Signed-off-by: Noralf Trønnes +--- + drivers/video/fbdev/Kconfig | 14 + + drivers/video/fbdev/Makefile | 1 + + drivers/video/fbdev/bcm2708_fb.c | 824 ++++++++++ + drivers/video/logo/logo_linux_clut224.ppm | 2483 ++++++++++------------------- + 4 files changed, 1720 insertions(+), 1602 deletions(-) + create mode 100644 drivers/video/fbdev/bcm2708_fb.c + +--- a/drivers/video/fbdev/Kconfig ++++ b/drivers/video/fbdev/Kconfig +@@ -224,6 +224,20 @@ config FB_TILEBLITTING + comment "Frame buffer hardware drivers" + depends on FB + ++config FB_BCM2708 ++ tristate "BCM2708 framebuffer support" ++ depends on FB && ARM && BCM2708_MBOX ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ help ++ This framebuffer device driver is for the BCM2708 framebuffer. ++ ++ If you want to compile this as a module (=code which can be ++ inserted into and removed from the running kernel), say M ++ here and read . The module ++ will be called bcm2708_fb. ++ + config FB_GRVGA + tristate "Aeroflex Gaisler framebuffer support" + depends on FB && SPARC +--- a/drivers/video/fbdev/Makefile ++++ b/drivers/video/fbdev/Makefile +@@ -12,6 +12,7 @@ obj-$(CONFIG_FB_MACMODES) += macmod + obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o + + # Hardware specific drivers go first ++obj-$(CONFIG_FB_BCM2708) += bcm2708_fb.o + obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o + obj-$(CONFIG_FB_ARC) += arcfb.o + obj-$(CONFIG_FB_CLPS711X) += clps711x-fb.o +--- /dev/null ++++ b/drivers/video/fbdev/bcm2708_fb.c +@@ -0,0 +1,824 @@ ++/* ++ * linux/drivers/video/bcm2708_fb.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Broadcom simple framebuffer driver ++ * ++ * This file is derived from cirrusfb.c ++ * Copyright 1999-2001 Jeff Garzik ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#define BCM2708_FB_DEBUG ++#define MODULE_NAME "bcm2708_fb" ++ ++#ifdef BCM2708_FB_DEBUG ++#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++ ++/* This is limited to 16 characters when displayed by X startup */ ++static const char *bcm2708_name = "BCM2708 FB"; ++ ++#define DRIVER_NAME "bcm2708_fb" ++ ++static int fbwidth = 800; /* module parameter */ ++static int fbheight = 480; /* module parameter */ ++static int fbdepth = 16; /* module parameter */ ++static int fbswap = 0; /* module parameter */ ++ ++static u32 dma_busy_wait_threshold = 1<<15; ++module_param(dma_busy_wait_threshold, int, 0644); ++MODULE_PARM_DESC(dma_busy_wait_threshold, "Busy-wait for DMA completion below this area"); ++ ++/* this data structure describes each frame buffer device we find */ ++ ++struct fbinfo_s { ++ u32 xres, yres, xres_virtual, yres_virtual; ++ u32 pitch, bpp; ++ u32 xoffset, yoffset; ++ u32 base; ++ u32 screen_size; ++ u16 cmap[256]; ++}; ++ ++struct bcm2708_fb_stats { ++ struct debugfs_regset32 regset; ++ u32 dma_copies; ++ u32 dma_irqs; ++}; ++ ++struct bcm2708_fb { ++ struct fb_info fb; ++ struct platform_device *dev; ++ struct fbinfo_s *info; ++ dma_addr_t dma; ++ u32 cmap[16]; ++ int dma_chan; ++ int dma_irq; ++ void __iomem *dma_chan_base; ++ void *cb_base; /* DMA control blocks */ ++ dma_addr_t cb_handle; ++ struct dentry *debugfs_dir; ++ wait_queue_head_t dma_waitq; ++ struct bcm2708_fb_stats stats; ++ unsigned long fb_bus_address; ++}; ++ ++#define to_bcm2708(info) container_of(info, struct bcm2708_fb, fb) ++ ++static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb) ++{ ++ debugfs_remove_recursive(fb->debugfs_dir); ++ fb->debugfs_dir = NULL; ++} ++ ++static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb) ++{ ++ static struct debugfs_reg32 stats_registers[] = { ++ { ++ "dma_copies", ++ offsetof(struct bcm2708_fb_stats, dma_copies) ++ }, ++ { ++ "dma_irqs", ++ offsetof(struct bcm2708_fb_stats, dma_irqs) ++ }, ++ }; ++ ++ fb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL); ++ if (!fb->debugfs_dir) { ++ pr_warn("%s: could not create debugfs entry\n", ++ __func__); ++ return -EFAULT; ++ } ++ ++ fb->stats.regset.regs = stats_registers; ++ fb->stats.regset.nregs = ARRAY_SIZE(stats_registers); ++ fb->stats.regset.base = &fb->stats; ++ ++ if (!debugfs_create_regset32( ++ "stats", 0444, fb->debugfs_dir, &fb->stats.regset)) { ++ pr_warn("%s: could not create statistics registers\n", ++ __func__); ++ goto fail; ++ } ++ return 0; ++ ++fail: ++ bcm2708_fb_debugfs_deinit(fb); ++ return -EFAULT; ++} ++ ++static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var) ++{ ++ int ret = 0; ++ ++ memset(&var->transp, 0, sizeof(var->transp)); ++ ++ var->red.msb_right = 0; ++ var->green.msb_right = 0; ++ var->blue.msb_right = 0; ++ ++ switch (var->bits_per_pixel) { ++ case 1: ++ case 2: ++ case 4: ++ case 8: ++ var->red.length = var->bits_per_pixel; ++ var->red.offset = 0; ++ var->green.length = var->bits_per_pixel; ++ var->green.offset = 0; ++ var->blue.length = var->bits_per_pixel; ++ var->blue.offset = 0; ++ break; ++ case 16: ++ var->red.length = 5; ++ var->blue.length = 5; ++ /* ++ * Green length can be 5 or 6 depending whether ++ * we're operating in RGB555 or RGB565 mode. ++ */ ++ if (var->green.length != 5 && var->green.length != 6) ++ var->green.length = 6; ++ break; ++ case 24: ++ var->red.length = 8; ++ var->blue.length = 8; ++ var->green.length = 8; ++ break; ++ case 32: ++ var->red.length = 8; ++ var->green.length = 8; ++ var->blue.length = 8; ++ var->transp.length = 8; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ /* ++ * >= 16bpp displays have separate colour component bitfields ++ * encoded in the pixel data. Calculate their position from ++ * the bitfield length defined above. ++ */ ++ if (ret == 0 && var->bits_per_pixel >= 24 && fbswap) { ++ var->blue.offset = 0; ++ var->green.offset = var->blue.offset + var->blue.length; ++ var->red.offset = var->green.offset + var->green.length; ++ var->transp.offset = var->red.offset + var->red.length; ++ } else if (ret == 0 && var->bits_per_pixel >= 24) { ++ var->red.offset = 0; ++ var->green.offset = var->red.offset + var->red.length; ++ var->blue.offset = var->green.offset + var->green.length; ++ var->transp.offset = var->blue.offset + var->blue.length; ++ } else if (ret == 0 && var->bits_per_pixel >= 16) { ++ var->blue.offset = 0; ++ var->green.offset = var->blue.offset + var->blue.length; ++ var->red.offset = var->green.offset + var->green.length; ++ var->transp.offset = var->red.offset + var->red.length; ++ } ++ ++ return ret; ++} ++ ++static int bcm2708_fb_check_var(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ /* info input, var output */ ++ int yres; ++ ++ /* info input, var output */ ++ print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info, ++ info->var.xres, info->var.yres, info->var.xres_virtual, ++ info->var.yres_virtual, (int)info->screen_size, ++ info->var.bits_per_pixel); ++ print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var, ++ var->xres, var->yres, var->xres_virtual, var->yres_virtual, ++ var->bits_per_pixel); ++ ++ if (!var->bits_per_pixel) ++ var->bits_per_pixel = 16; ++ ++ if (bcm2708_fb_set_bitfields(var) != 0) { ++ pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n", ++ var->bits_per_pixel); ++ return -EINVAL; ++ } ++ ++ ++ if (var->xres_virtual < var->xres) ++ var->xres_virtual = var->xres; ++ /* use highest possible virtual resolution */ ++ if (var->yres_virtual == -1) { ++ var->yres_virtual = 480; ++ ++ pr_err ++ ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n", ++ var->xres_virtual, var->yres_virtual); ++ } ++ if (var->yres_virtual < var->yres) ++ var->yres_virtual = var->yres; ++ ++ if (var->xoffset < 0) ++ var->xoffset = 0; ++ if (var->yoffset < 0) ++ var->yoffset = 0; ++ ++ /* truncate xoffset and yoffset to maximum if too high */ ++ if (var->xoffset > var->xres_virtual - var->xres) ++ var->xoffset = var->xres_virtual - var->xres - 1; ++ if (var->yoffset > var->yres_virtual - var->yres) ++ var->yoffset = var->yres_virtual - var->yres - 1; ++ ++ yres = var->yres; ++ if (var->vmode & FB_VMODE_DOUBLE) ++ yres *= 2; ++ else if (var->vmode & FB_VMODE_INTERLACED) ++ yres = (yres + 1) / 2; ++ ++ return 0; ++} ++ ++static int bcm2708_fb_set_par(struct fb_info *info) ++{ ++ uint32_t val = 0; ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ volatile struct fbinfo_s *fbinfo = fb->info; ++ fbinfo->xres = info->var.xres; ++ fbinfo->yres = info->var.yres; ++ fbinfo->xres_virtual = info->var.xres_virtual; ++ fbinfo->yres_virtual = info->var.yres_virtual; ++ fbinfo->bpp = info->var.bits_per_pixel; ++ fbinfo->xoffset = info->var.xoffset; ++ fbinfo->yoffset = info->var.yoffset; ++ fbinfo->base = 0; /* filled in by VC */ ++ fbinfo->pitch = 0; /* filled in by VC */ ++ ++ print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, ++ info->var.xres, info->var.yres, info->var.xres_virtual, ++ info->var.yres_virtual, (int)info->screen_size, ++ info->var.bits_per_pixel); ++ ++ /* ensure last write to fbinfo is visible to GPU */ ++ wmb(); ++ ++ /* inform vc about new framebuffer */ ++ bcm_mailbox_write(MBOX_CHAN_FB, fb->dma); ++ ++ /* TODO: replace fb driver with vchiq version */ ++ /* wait for response */ ++ bcm_mailbox_read(MBOX_CHAN_FB, &val); ++ ++ /* ensure GPU writes are visible to us */ ++ rmb(); ++ ++ if (val == 0) { ++ fb->fb.fix.line_length = fbinfo->pitch; ++ ++ if (info->var.bits_per_pixel <= 8) ++ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ else ++ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ ++ fb->fb_bus_address = fbinfo->base; ++ fbinfo->base &= ~0xc0000000; ++ fb->fb.fix.smem_start = fbinfo->base; ++ fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual; ++ fb->fb.screen_size = fbinfo->screen_size; ++ if (fb->fb.screen_base) ++ iounmap(fb->fb.screen_base); ++ fb->fb.screen_base = ++ (void *)ioremap_wc(fbinfo->base, fb->fb.screen_size); ++ if (!fb->fb.screen_base) { ++ /* the console may currently be locked */ ++ console_trylock(); ++ console_unlock(); ++ pr_err("bcm2708_fb_set_par: Failed to set screen_base\n"); ++ return -EIO; ++ } ++ } ++ print_debug ++ ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d success=%d\n", ++ (void *)fb->fb.screen_base, (void *)fb->fb_bus_address, ++ fbinfo->xres, fbinfo->yres, fbinfo->bpp, ++ fbinfo->pitch, (int)fb->fb.screen_size, val); ++ ++ return val; ++} ++ ++static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) ++{ ++ unsigned int mask = (1 << bf->length) - 1; ++ ++ return (val >> (16 - bf->length) & mask) << bf->offset; ++} ++ ++ ++static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red, ++ unsigned int green, unsigned int blue, ++ unsigned int transp, struct fb_info *info) ++{ ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ ++ /*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/ ++ if (fb->fb.var.bits_per_pixel <= 8) { ++ if (regno < 256) { ++ /* blue [0:4], green [5:10], red [11:15] */ ++ fb->info->cmap[regno] = ((red >> (16-5)) & 0x1f) << 11 | ++ ((green >> (16-6)) & 0x3f) << 5 | ++ ((blue >> (16-5)) & 0x1f) << 0; ++ } ++ /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */ ++ /* So just call it for what looks like the last colour in a list for now. */ ++ if (regno == 15 || regno == 255) ++ bcm2708_fb_set_par(info); ++ } else if (regno < 16) { ++ fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | ++ convert_bitfield(blue, &fb->fb.var.blue) | ++ convert_bitfield(green, &fb->fb.var.green) | ++ convert_bitfield(red, &fb->fb.var.red); ++ } ++ return regno > 255; ++} ++ ++static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) ++{ ++ s32 result = -1; ++ u32 p[7]; ++ if ( (blank_mode == FB_BLANK_NORMAL) || ++ (blank_mode == FB_BLANK_UNBLANK)) { ++ ++ p[0] = 28; // size = sizeof u32 * length of p ++ p[1] = VCMSG_PROCESS_REQUEST; // process request ++ p[2] = VCMSG_SET_BLANK_SCREEN; // (the tag id) ++ p[3] = 4; // (size of the response buffer) ++ p[4] = 4; // (size of the request data) ++ p[5] = blank_mode; ++ p[6] = VCMSG_PROPERTY_END; // end tag ++ ++ bcm_mailbox_property(&p, p[0]); ++ ++ if ( p[1] == VCMSG_REQUEST_SUCCESSFUL ) ++ result = 0; ++ else ++ pr_err("bcm2708_fb_blank(%d) returns=%d p[1]=0x%x\n", blank_mode, p[5], p[1]); ++ } ++ return result; ++} ++ ++static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ s32 result = -1; ++ info->var.xoffset = var->xoffset; ++ info->var.yoffset = var->yoffset; ++ result = bcm2708_fb_set_par(info); ++ if (result != 0) ++ pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result); ++ return result; ++} ++ ++static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) ++{ ++ s32 result = -1; ++ u32 p[7]; ++ if (cmd == FBIO_WAITFORVSYNC) { ++ p[0] = 28; // size = sizeof u32 * length of p ++ p[1] = VCMSG_PROCESS_REQUEST; // process request ++ p[2] = VCMSG_SET_VSYNC; // (the tag id) ++ p[3] = 4; // (size of the response buffer) ++ p[4] = 4; // (size of the request data) ++ p[5] = 0; // dummy ++ p[6] = VCMSG_PROPERTY_END; // end tag ++ ++ bcm_mailbox_property(&p, p[0]); ++ ++ if ( p[1] == VCMSG_REQUEST_SUCCESSFUL ) ++ result = 0; ++ else ++ pr_err("bcm2708_fb_ioctl %x,%lx returns=%d p[1]=0x%x\n", cmd, arg, p[5], p[1]); ++ } ++ return result; ++} ++static void bcm2708_fb_fillrect(struct fb_info *info, ++ const struct fb_fillrect *rect) ++{ ++ /* (is called) print_debug("bcm2708_fb_fillrect\n"); */ ++ cfb_fillrect(info, rect); ++} ++ ++/* A helper function for configuring dma control block */ ++static void set_dma_cb(struct bcm2708_dma_cb *cb, ++ int burst_size, ++ dma_addr_t dst, ++ int dst_stride, ++ dma_addr_t src, ++ int src_stride, ++ int w, ++ int h) ++{ ++ cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH | ++ BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH | ++ BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE; ++ cb->dst = dst; ++ cb->src = src; ++ /* ++ * This is not really obvious from the DMA documentation, ++ * but the top 16 bits must be programmmed to "height -1" ++ * and not "height" in 2D mode. ++ */ ++ cb->length = ((h - 1) << 16) | w; ++ cb->stride = ((dst_stride - w) << 16) | (u16)(src_stride - w); ++ cb->pad[0] = 0; ++ cb->pad[1] = 0; ++} ++ ++static void bcm2708_fb_copyarea(struct fb_info *info, ++ const struct fb_copyarea *region) ++{ ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ struct bcm2708_dma_cb *cb = fb->cb_base; ++ int bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3; ++ /* Channel 0 supports larger bursts and is a bit faster */ ++ int burst_size = (fb->dma_chan == 0) ? 8 : 2; ++ int pixels = region->width * region->height; ++ ++ /* Fallback to cfb_copyarea() if we don't like something */ ++ if (in_atomic() || ++ bytes_per_pixel > 4 || ++ info->var.xres * info->var.yres > 1920 * 1200 || ++ region->width <= 0 || region->width > info->var.xres || ++ region->height <= 0 || region->height > info->var.yres || ++ region->sx < 0 || region->sx >= info->var.xres || ++ region->sy < 0 || region->sy >= info->var.yres || ++ region->dx < 0 || region->dx >= info->var.xres || ++ region->dy < 0 || region->dy >= info->var.yres || ++ region->sx + region->width > info->var.xres || ++ region->dx + region->width > info->var.xres || ++ region->sy + region->height > info->var.yres || ++ region->dy + region->height > info->var.yres) { ++ cfb_copyarea(info, region); ++ return; ++ } ++ ++ if (region->dy == region->sy && region->dx > region->sx) { ++ /* ++ * A difficult case of overlapped copy. Because DMA can't ++ * copy individual scanlines in backwards direction, we need ++ * two-pass processing. We do it by programming a chain of dma ++ * control blocks in the first 16K part of the buffer and use ++ * the remaining 48K as the intermediate temporary scratch ++ * buffer. The buffer size is sufficient to handle up to ++ * 1920x1200 resolution at 32bpp pixel depth. ++ */ ++ int y; ++ dma_addr_t control_block_pa = fb->cb_handle; ++ dma_addr_t scratchbuf = fb->cb_handle + 16 * 1024; ++ int scanline_size = bytes_per_pixel * region->width; ++ int scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size; ++ ++ for (y = 0; y < region->height; y += scanlines_per_cb) { ++ dma_addr_t src = ++ fb->fb_bus_address + ++ bytes_per_pixel * region->sx + ++ (region->sy + y) * fb->fb.fix.line_length; ++ dma_addr_t dst = ++ fb->fb_bus_address + ++ bytes_per_pixel * region->dx + ++ (region->dy + y) * fb->fb.fix.line_length; ++ ++ if (region->height - y < scanlines_per_cb) ++ scanlines_per_cb = region->height - y; ++ ++ set_dma_cb(cb, burst_size, scratchbuf, scanline_size, ++ src, fb->fb.fix.line_length, ++ scanline_size, scanlines_per_cb); ++ control_block_pa += sizeof(struct bcm2708_dma_cb); ++ cb->next = control_block_pa; ++ cb++; ++ ++ set_dma_cb(cb, burst_size, dst, fb->fb.fix.line_length, ++ scratchbuf, scanline_size, ++ scanline_size, scanlines_per_cb); ++ control_block_pa += sizeof(struct bcm2708_dma_cb); ++ cb->next = control_block_pa; ++ cb++; ++ } ++ /* move the pointer back to the last dma control block */ ++ cb--; ++ } else { ++ /* A single dma control block is enough. */ ++ int sy, dy, stride; ++ if (region->dy <= region->sy) { ++ /* processing from top to bottom */ ++ dy = region->dy; ++ sy = region->sy; ++ stride = fb->fb.fix.line_length; ++ } else { ++ /* processing from bottom to top */ ++ dy = region->dy + region->height - 1; ++ sy = region->sy + region->height - 1; ++ stride = -fb->fb.fix.line_length; ++ } ++ set_dma_cb(cb, burst_size, ++ fb->fb_bus_address + dy * fb->fb.fix.line_length + ++ bytes_per_pixel * region->dx, ++ stride, ++ fb->fb_bus_address + sy * fb->fb.fix.line_length + ++ bytes_per_pixel * region->sx, ++ stride, ++ region->width * bytes_per_pixel, ++ region->height); ++ } ++ ++ /* end of dma control blocks chain */ ++ cb->next = 0; ++ ++ ++ if (pixels < dma_busy_wait_threshold) { ++ bcm_dma_start(fb->dma_chan_base, fb->cb_handle); ++ bcm_dma_wait_idle(fb->dma_chan_base); ++ } else { ++ void __iomem *dma_chan = fb->dma_chan_base; ++ cb->info |= BCM2708_DMA_INT_EN; ++ bcm_dma_start(fb->dma_chan_base, fb->cb_handle); ++ while (bcm_dma_is_busy(dma_chan)) { ++ wait_event_interruptible( ++ fb->dma_waitq, ++ !bcm_dma_is_busy(dma_chan)); ++ } ++ fb->stats.dma_irqs++; ++ } ++ fb->stats.dma_copies++; ++} ++ ++static void bcm2708_fb_imageblit(struct fb_info *info, ++ const struct fb_image *image) ++{ ++ /* (is called) print_debug("bcm2708_fb_imageblit\n"); */ ++ cfb_imageblit(info, image); ++} ++ ++static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt) ++{ ++ struct bcm2708_fb *fb = cxt; ++ ++ /* FIXME: should read status register to check if this is ++ * actually interrupting us or not, in case this interrupt ++ * ever becomes shared amongst several DMA channels ++ * ++ * readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_IRQ; ++ */ ++ ++ /* acknowledge the interrupt */ ++ writel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS); ++ ++ wake_up(&fb->dma_waitq); ++ return IRQ_HANDLED; ++} ++ ++static struct fb_ops bcm2708_fb_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = bcm2708_fb_check_var, ++ .fb_set_par = bcm2708_fb_set_par, ++ .fb_setcolreg = bcm2708_fb_setcolreg, ++ .fb_blank = bcm2708_fb_blank, ++ .fb_fillrect = bcm2708_fb_fillrect, ++ .fb_copyarea = bcm2708_fb_copyarea, ++ .fb_imageblit = bcm2708_fb_imageblit, ++ .fb_pan_display = bcm2708_fb_pan_display, ++ .fb_ioctl = bcm2708_ioctl, ++}; ++ ++static int bcm2708_fb_register(struct bcm2708_fb *fb) ++{ ++ int ret; ++ dma_addr_t dma; ++ void *mem; ++ ++ mem = ++ dma_alloc_coherent(&fb->dev->dev, PAGE_ALIGN(sizeof(*fb->info)), &dma, ++ GFP_KERNEL); ++ ++ if (NULL == mem) { ++ pr_err(": unable to allocate fbinfo buffer\n"); ++ ret = -ENOMEM; ++ } else { ++ fb->info = (struct fbinfo_s *)mem; ++ fb->dma = dma; ++ } ++ fb->fb.fbops = &bcm2708_fb_ops; ++ fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA; ++ fb->fb.pseudo_palette = fb->cmap; ++ ++ strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id)); ++ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; ++ fb->fb.fix.type_aux = 0; ++ fb->fb.fix.xpanstep = 1; ++ fb->fb.fix.ypanstep = 1; ++ fb->fb.fix.ywrapstep = 0; ++ fb->fb.fix.accel = FB_ACCEL_NONE; ++ ++ fb->fb.var.xres = fbwidth; ++ fb->fb.var.yres = fbheight; ++ fb->fb.var.xres_virtual = fbwidth; ++ fb->fb.var.yres_virtual = fbheight; ++ fb->fb.var.bits_per_pixel = fbdepth; ++ fb->fb.var.vmode = FB_VMODE_NONINTERLACED; ++ fb->fb.var.activate = FB_ACTIVATE_NOW; ++ fb->fb.var.nonstd = 0; ++ fb->fb.var.height = -1; /* height of picture in mm */ ++ fb->fb.var.width = -1; /* width of picture in mm */ ++ fb->fb.var.accel_flags = 0; ++ ++ fb->fb.monspecs.hfmin = 0; ++ fb->fb.monspecs.hfmax = 100000; ++ fb->fb.monspecs.vfmin = 0; ++ fb->fb.monspecs.vfmax = 400; ++ fb->fb.monspecs.dclkmin = 1000000; ++ fb->fb.monspecs.dclkmax = 100000000; ++ ++ bcm2708_fb_set_bitfields(&fb->fb.var); ++ init_waitqueue_head(&fb->dma_waitq); ++ ++ /* ++ * Allocate colourmap. ++ */ ++ ++ fb_set_var(&fb->fb, &fb->fb.var); ++ ret = bcm2708_fb_set_par(&fb->fb); ++ if (ret) ++ return ret; ++ ++ print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n", fbwidth, ++ fbheight, fbdepth, fbswap); ++ ++ ret = register_framebuffer(&fb->fb); ++ print_debug("BCM2708FB: register framebuffer (%d)\n", ret); ++ if (ret == 0) ++ goto out; ++ ++ print_debug("BCM2708FB: cannot register framebuffer (%d)\n", ret); ++out: ++ return ret; ++} ++ ++static int bcm2708_fb_probe(struct platform_device *dev) ++{ ++ struct bcm2708_fb *fb; ++ int ret; ++ ++ fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL); ++ if (!fb) { ++ dev_err(&dev->dev, ++ "could not allocate new bcm2708_fb struct\n"); ++ ret = -ENOMEM; ++ goto free_region; ++ } ++ ++ bcm2708_fb_debugfs_init(fb); ++ ++ fb->cb_base = dma_alloc_writecombine(&dev->dev, SZ_64K, ++ &fb->cb_handle, GFP_KERNEL); ++ if (!fb->cb_base) { ++ dev_err(&dev->dev, "cannot allocate DMA CBs\n"); ++ ret = -ENOMEM; ++ goto free_fb; ++ } ++ ++ pr_info("BCM2708FB: allocated DMA memory %08x\n", ++ fb->cb_handle); ++ ++ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK, ++ &fb->dma_chan_base, &fb->dma_irq); ++ if (ret < 0) { ++ dev_err(&dev->dev, "couldn't allocate a DMA channel\n"); ++ goto free_cb; ++ } ++ fb->dma_chan = ret; ++ ++ ret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq, ++ 0, "bcm2708_fb dma", fb); ++ if (ret) { ++ pr_err("%s: failed to request DMA irq\n", __func__); ++ goto free_dma_chan; ++ } ++ ++ ++ pr_info("BCM2708FB: allocated DMA channel %d @ %p\n", ++ fb->dma_chan, fb->dma_chan_base); ++ ++ fb->dev = dev; ++ ++ ret = bcm2708_fb_register(fb); ++ if (ret == 0) { ++ platform_set_drvdata(dev, fb); ++ goto out; ++ } ++ ++free_dma_chan: ++ bcm_dma_chan_free(fb->dma_chan); ++free_cb: ++ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle); ++free_fb: ++ kfree(fb); ++free_region: ++ dev_err(&dev->dev, "probe failed, err %d\n", ret); ++out: ++ return ret; ++} ++ ++static int bcm2708_fb_remove(struct platform_device *dev) ++{ ++ struct bcm2708_fb *fb = platform_get_drvdata(dev); ++ ++ platform_set_drvdata(dev, NULL); ++ ++ if (fb->fb.screen_base) ++ iounmap(fb->fb.screen_base); ++ unregister_framebuffer(&fb->fb); ++ ++ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle); ++ bcm_dma_chan_free(fb->dma_chan); ++ ++ dma_free_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), (void *)fb->info, ++ fb->dma); ++ bcm2708_fb_debugfs_deinit(fb); ++ ++ free_irq(fb->dma_irq, fb); ++ ++ kfree(fb); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm2708_fb_of_match_table[] = { ++ { .compatible = "brcm,bcm2708-fb", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2708_fb_of_match_table); ++ ++static struct platform_driver bcm2708_fb_driver = { ++ .probe = bcm2708_fb_probe, ++ .remove = bcm2708_fb_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2708_fb_of_match_table, ++ }, ++}; ++ ++static int __init bcm2708_fb_init(void) ++{ ++ return platform_driver_register(&bcm2708_fb_driver); ++} ++ ++module_init(bcm2708_fb_init); ++ ++static void __exit bcm2708_fb_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_fb_driver); ++} ++ ++module_exit(bcm2708_fb_exit); ++ ++module_param(fbwidth, int, 0644); ++module_param(fbheight, int, 0644); ++module_param(fbdepth, int, 0644); ++module_param(fbswap, int, 0644); ++ ++MODULE_DESCRIPTION("BCM2708 framebuffer driver"); ++MODULE_LICENSE("GPL"); ++ ++MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer"); ++MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer"); ++MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer"); ++MODULE_PARM_DESC(fbswap, "Swap order of red and blue in 24 and 32 bit modes"); +--- a/drivers/video/logo/logo_linux_clut224.ppm ++++ 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17 66 ++181 16 63 47 4 16 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 21 2 7 163 15 57 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++122 11 43 9 1 3 0 0 0 0 0 0 30 3 10 171 15 60 ++189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 190 17 67 146 13 51 10 1 4 ++0 0 0 38 3 13 166 15 58 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++183 17 64 52 5 18 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 13 1 5 154 14 54 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++186 17 65 79 7 28 0 0 0 0 0 0 14 1 5 156 14 54 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 191 17 67 124 11 43 2 0 1 ++5 0 2 122 11 43 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++182 16 64 47 4 16 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 3 0 1 126 14 44 191 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++190 17 67 158 14 55 23 2 8 0 0 0 1 0 0 113 10 40 ++191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 78 7 27 0 0 0 ++47 4 16 177 16 62 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 189 17 66 ++173 16 61 34 3 12 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 85 8 30 189 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 79 7 28 0 0 0 0 0 0 47 4 16 ++175 16 62 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 190 17 67 156 14 55 22 2 8 0 0 0 ++109 10 38 191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++151 14 53 13 1 5 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 35 3 12 173 16 61 189 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 191 17 67 134 12 47 7 1 2 0 0 0 3 0 1 ++99 9 35 188 17 66 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 181 16 63 68 6 24 0 0 0 18 2 6 ++156 14 55 190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++101 9 35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 3 0 1 118 13 41 191 17 67 188 17 66 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0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ++47 4 16 141 13 49 186 17 65 191 17 67 190 17 67 189 17 66 ++189 17 66 191 17 67 156 14 55 20 2 7 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 4 15 ++178 16 62 190 17 67 188 17 66 188 17 66 188 17 66 190 17 67 ++191 17 67 173 16 61 90 8 32 10 1 4 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 14 1 5 68 6 24 131 12 46 162 15 57 174 16 61 ++171 15 60 146 13 51 56 5 19 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 3 0 1 14 1 5 29 3 10 ++41 4 14 47 4 16 50 5 17 45 4 16 34 3 12 18 2 6 ++5 0 2 0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 ++90 8 32 169 15 59 185 17 65 187 17 66 182 16 64 163 15 57 ++113 10 40 41 4 14 2 0 1 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 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0 ++0 0 0 0 0 0 0 0 0 0 0 0 14 1 5 141 13 49 ++191 17 67 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 67 186 17 65 65 6 23 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 23 2 8 166 15 58 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 66 176 16 62 45 4 16 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 83 8 29 ++183 17 64 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 185 17 65 95 9 33 3 0 1 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 ++85 8 30 176 16 62 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++191 17 67 180 16 63 95 9 33 7 1 3 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++2 0 1 52 5 18 141 13 49 185 17 65 191 17 67 189 17 67 ++189 17 66 188 17 66 188 17 66 189 17 66 191 17 67 187 17 66 ++146 13 51 56 5 19 4 0 1 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 14 1 5 68 6 24 131 12 46 166 15 58 ++180 16 63 183 17 64 180 16 63 168 15 59 134 12 47 75 7 26 ++17 2 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 24 2 8 ++44 4 15 52 5 18 45 4 16 26 2 9 6 1 2 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 diff --git a/target/linux/brcm2708/patches-4.1/0007-dmaengine-Add-support-for-BCM2708.patch b/target/linux/brcm2708/patches-4.1/0007-dmaengine-Add-support-for-BCM2708.patch new file mode 100644 index 0000000..4b3a8ae --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0007-dmaengine-Add-support-for-BCM2708.patch @@ -0,0 +1,1756 @@ +From 6ba80b1f7e7404642d3f72203116a7969b4e84ed Mon Sep 17 00:00:00 2001 +From: Florian Meier +Date: Fri, 22 Nov 2013 14:22:53 +0100 +Subject: [PATCH 007/203] dmaengine: Add support for BCM2708 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add support for DMA controller of BCM2708 as used in the Raspberry Pi. +Currently it only supports cyclic DMA. + +Signed-off-by: Florian Meier + +dmaengine: expand functionality by supporting scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels + +DMA: fix cyclic LITE length overflow bug + +dmaengine: bcm2708: Remove chancnt affectations + +Mirror bcm2835-dma.c commit 9eba5536a7434c69d8c185d4bd1c70734d92287d: +chancnt is already filled by dma_async_device_register, which uses the channel +list to know how much channels there is. + +Since it's already filled, we can safely remove it from the drivers' probe +function. + +Signed-off-by: Noralf Trønnes + +dmaengine: bcm2708: overwrite dreq only if it is not set + +dreq is set when the DMA channel is fetched from Device Tree. +slave_id is set using dmaengine_slave_config(). +Only overwrite dreq with slave_id if it is not set. + +dreq/slave_id in the cyclic DMA case is not touched, because I don't +have hardware to test with. + +Signed-off-by: Noralf Trønnes + +dmaengine: bcm2708: do device registration in the board file + +Don't register the device in the driver. Do it in the board file. + +Signed-off-by: Noralf Trønnes + +dmaengine: bcm2708: don't restrict DT support to ARCH_BCM2835 + +Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now. +Add Device Tree support to the non ARCH_BCM2835 case. +Use the same driver name regardless of architecture. + +Signed-off-by: Noralf Trønnes + +BCM270x_DT: add bcm2835-dma entry + +Add Device Tree entry for bcm2835-dma. +The entry doesn't contain any resources since they are handled +by the arch/arm/mach-bcm270x/dma.c driver. +In non-DT mode, don't add the device in the board file. + +Signed-off-by: Noralf Trønnes + +bcm2708-dmaengine: Add debug options + +BCM270x: Add memory and irq resources to dmaengine device and DT + +Prepare for merging of the legacy DMA API arch driver dma.c +with bcm2708-dmaengine by adding memory and irq resources both +to platform file device and Device Tree node. +Don't use BCM_DMAMAN_DRIVER_NAME so we don't have to include mach/dma.h + +Signed-off-by: Noralf Trønnes + +dmaengine: bcm2708: Merge with arch dma.c driver and disable dma.c + +Merge the legacy DMA API driver with bcm2708-dmaengine. +This is done so we can use bcm2708_fb on ARCH_BCM2835 (mailbox +driver is also needed). + +Changes to the dma.c code: +- Use BIT() macro. +- Cutdown some comments to one line. +- Add mutex to vc_dmaman and use this, since the dev lock is locked + during probing of the engine part. +- Add global g_dmaman variable since drvdata is used by the engine part. +- Restructure for readability: + vc_dmaman_chan_alloc() + vc_dmaman_chan_free() + bcm_dma_chan_free() +- Restructure bcm_dma_chan_alloc() to simplify error handling. +- Use device irq resources instead of hardcoded bcm_dma_irqs table. +- Remove dev_dmaman_register() and code it directly. +- Remove dev_dmaman_deregister() and code it directly. +- Simplify bcm_dmaman_probe() using devm_* functions. +- Get dmachans from DT if available. +- Keep 'dma.dmachans' module argument name for backwards compatibility. + +Make it available on ARCH_BCM2835 as well. + +Signed-off-by: Noralf Trønnes + +dmaengine: bcm2708: set residue_granularity field + +bcm2708-dmaengine supports residue reporting at burst level +but didn't report this via the residue_granularity field. + +Without this field set properly we get playback issues with I2S cards. +--- + arch/arm/mach-bcm2708/bcm2708.c | 68 ++ + arch/arm/mach-bcm2709/bcm2709.c | 68 ++ + drivers/dma/Kconfig | 13 +- + drivers/dma/Makefile | 1 + + drivers/dma/bcm2708-dmaengine.c | 1298 +++++++++++++++++++++++++++++ + include/linux/platform_data/dma-bcm2708.h | 127 +++ + 6 files changed, 1574 insertions(+), 1 deletion(-) + create mode 100644 drivers/dma/bcm2708-dmaengine.c + create mode 100644 include/linux/platform_data/dma-bcm2708.h + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -234,6 +234,73 @@ static struct amba_device *amba_devs[] _ + &uart0_device, + }; + ++static struct resource bcm2708_dmaengine_resources[] = { ++ { ++ .start = DMA_BASE, ++ .end = DMA_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_DMA0, ++ .end = IRQ_DMA0, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA1, ++ .end = IRQ_DMA1, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA2, ++ .end = IRQ_DMA2, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA3, ++ .end = IRQ_DMA3, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA4, ++ .end = IRQ_DMA4, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA5, ++ .end = IRQ_DMA5, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA6, ++ .end = IRQ_DMA6, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA7, ++ .end = IRQ_DMA7, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA8, ++ .end = IRQ_DMA8, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA9, ++ .end = IRQ_DMA9, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA10, ++ .end = IRQ_DMA10, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA11, ++ .end = IRQ_DMA11, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA12, ++ .end = IRQ_DMA12, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_dmaengine_device = { ++ .name = "bcm2708-dmaengine", ++ .id = -1, ++ .resource = bcm2708_dmaengine_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources), ++}; ++ + static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_fb_device = { +@@ -463,6 +530,7 @@ void __init bcm2708_init(void) + bcm2708_init_clocks(); + bcm2708_dt_init(); + ++ bcm_register_device_dt(&bcm2708_dmaengine_device); + bcm_register_device(&bcm2708_vcio_device); + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -244,6 +244,73 @@ static struct amba_device *amba_devs[] _ + &uart0_device, + }; + ++static struct resource bcm2708_dmaengine_resources[] = { ++ { ++ .start = DMA_BASE, ++ .end = DMA_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_DMA0, ++ .end = IRQ_DMA0, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA1, ++ .end = IRQ_DMA1, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA2, ++ .end = IRQ_DMA2, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA3, ++ .end = IRQ_DMA3, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA4, ++ .end = IRQ_DMA4, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA5, ++ .end = IRQ_DMA5, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA6, ++ .end = IRQ_DMA6, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA7, ++ .end = IRQ_DMA7, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA8, ++ .end = IRQ_DMA8, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA9, ++ .end = IRQ_DMA9, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA10, ++ .end = IRQ_DMA10, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA11, ++ .end = IRQ_DMA11, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA12, ++ .end = IRQ_DMA12, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_dmaengine_device = { ++ .name = "bcm2708-dmaengine", ++ .id = -1, ++ .resource = bcm2708_dmaengine_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources), ++}; ++ + static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_fb_device = { +@@ -483,6 +550,7 @@ void __init bcm2709_init(void) + bcm2709_init_clocks(); + bcm2709_dt_init(); + ++ bcm_register_device_dt(&bcm2708_dmaengine_device); + bcm_register_device(&bcm2708_vcio_device); + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -337,6 +337,17 @@ config DMA_BCM2835 + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + ++config DMA_BCM2708 ++ tristate "BCM2708 DMA engine support" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ select DMA_ENGINE ++ select DMA_VIRTUAL_CHANNELS ++ ++config DMA_BCM2708_LEGACY ++ bool "BCM2708 DMA legacy API support" ++ depends on DMA_BCM2708 ++ default y ++ + config TI_CPPI41 + tristate "AM33xx CPPI41 DMA support" + depends on ARCH_OMAP +@@ -385,7 +396,7 @@ config MOXART_DMA + select DMA_VIRTUAL_CHANNELS + help + Enable support for the MOXA ART SoC DMA controller. +- ++ + config FSL_EDMA + tristate "Freescale eDMA engine support" + depends on OF +--- a/drivers/dma/Makefile ++++ b/drivers/dma/Makefile +@@ -39,6 +39,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o + obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o + obj-$(CONFIG_DMA_OMAP) += omap-dma.o + obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o ++obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o + obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o + obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o + obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o +--- /dev/null ++++ b/drivers/dma/bcm2708-dmaengine.c +@@ -0,0 +1,1298 @@ ++/* ++ * BCM2835 DMA engine support ++ * ++ * This driver supports cyclic and scatter/gather DMA transfers. ++ * ++ * Author: Florian Meier ++ * Gellert Weisz ++ * Copyright 2013-2014 ++ * ++ * Based on ++ * OMAP DMAengine support by Russell King ++ * ++ * BCM2708 DMA Driver ++ * Copyright (C) 2010 Broadcom ++ * ++ * Raspberry Pi PCM I2S ALSA Driver ++ * Copyright (c) by Phil Poole 2013 ++ * ++ * MARVELL MMP Peripheral DMA Driver ++ * Copyright 2012 Marvell International Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "virt-dma.h" ++ ++static unsigned dma_debug; ++ ++/* ++ * Legacy DMA API ++ */ ++ ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++ ++#define CACHE_LINE_MASK 31 ++#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */ ++ ++/* valid only for channels 0 - 14, 15 has its own base address */ ++#define BCM2708_DMA_CHAN(n) ((n) << 8) /* base address */ ++#define BCM2708_DMA_CHANIO(dma_base, n) \ ++ ((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n))) ++ ++struct vc_dmaman { ++ void __iomem *dma_base; ++ u32 chan_available; /* bitmap of available channels */ ++ u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */ ++ struct mutex lock; ++}; ++ ++static struct device *dmaman_dev; /* we assume there's only one! */ ++static struct vc_dmaman *g_dmaman; /* DMA manager */ ++static int dmachans = -1; /* module parameter */ ++ ++/* DMA Auxiliary Functions */ ++ ++/* A DMA buffer on an arbitrary boundary may separate a cache line into a ++ section inside the DMA buffer and another section outside it. ++ Even if we flush DMA buffers from the cache there is always the chance that ++ during a DMA someone will access the part of a cache line that is outside ++ the DMA buffer - which will then bring in unwelcome data. ++ Without being able to dictate our own buffer pools we must insist that ++ DMA buffers consist of a whole number of cache lines. ++*/ ++extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len) ++{ ++ int i; ++ ++ for (i = 0; i < sg_len; i++) { ++ if (sg_ptr[i].offset & CACHE_LINE_MASK || ++ sg_ptr[i].length & CACHE_LINE_MASK) ++ return 0; ++ } ++ ++ return 1; ++} ++EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma); ++ ++extern void bcm_dma_start(void __iomem *dma_chan_base, ++ dma_addr_t control_block) ++{ ++ dsb(); /* ARM data synchronization (push) operation */ ++ ++ writel(control_block, dma_chan_base + BCM2708_DMA_ADDR); ++ writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS); ++} ++EXPORT_SYMBOL_GPL(bcm_dma_start); ++ ++extern void bcm_dma_wait_idle(void __iomem *dma_chan_base) ++{ ++ dsb(); ++ ++ /* ugly busy wait only option for now */ ++ while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE) ++ cpu_relax(); ++} ++EXPORT_SYMBOL_GPL(bcm_dma_wait_idle); ++ ++extern bool bcm_dma_is_busy(void __iomem *dma_chan_base) ++{ ++ dsb(); ++ ++ return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_is_busy); ++ ++/* Complete an ongoing DMA (assuming its results are to be ignored) ++ Does nothing if there is no DMA in progress. ++ This routine waits for the current AXI transfer to complete before ++ terminating the current DMA. If the current transfer is hung on a DREQ used ++ by an uncooperative peripheral the AXI transfer may never complete. In this ++ case the routine times out and return a non-zero error code. ++ Use of this routine doesn't guarantee that the ongoing or aborted DMA ++ does not produce an interrupt. ++*/ ++extern int bcm_dma_abort(void __iomem *dma_chan_base) ++{ ++ unsigned long int cs; ++ int rc = 0; ++ ++ cs = readl(dma_chan_base + BCM2708_DMA_CS); ++ ++ if (BCM2708_DMA_ACTIVE & cs) { ++ long int timeout = 10000; ++ ++ /* write 0 to the active bit - pause the DMA */ ++ writel(0, dma_chan_base + BCM2708_DMA_CS); ++ ++ /* wait for any current AXI transfer to complete */ ++ while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0) ++ cs = readl(dma_chan_base + BCM2708_DMA_CS); ++ ++ if (0 != (cs & BCM2708_DMA_ISPAUSED)) { ++ /* we'll un-pause when we set of our next DMA */ ++ rc = -ETIMEDOUT; ++ ++ } else if (BCM2708_DMA_ACTIVE & cs) { ++ /* terminate the control block chain */ ++ writel(0, dma_chan_base + BCM2708_DMA_NEXTCB); ++ ++ /* abort the whole DMA */ ++ writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE, ++ dma_chan_base + BCM2708_DMA_CS); ++ } ++ } ++ ++ return rc; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_abort); ++ ++ /* DMA Manager Device Methods */ ++ ++static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base, ++ u32 chans_available) ++{ ++ dmaman->dma_base = dma_base; ++ dmaman->chan_available = chans_available; ++ dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* 2 & 3 */ ++ dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* 0 */ ++ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* 1 to 7 */ ++ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* 8 to 14 */ ++} ++ ++static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman, ++ unsigned preferred_feature_set) ++{ ++ u32 chans; ++ int chan = 0; ++ int feature; ++ ++ chans = dmaman->chan_available; ++ for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++) ++ /* select the subset of available channels with the desired ++ feature so long as some of the candidate channels have that ++ feature */ ++ if ((preferred_feature_set & (1 << feature)) && ++ (chans & dmaman->has_feature[feature])) ++ chans &= dmaman->has_feature[feature]; ++ ++ if (!chans) ++ return -ENOENT; ++ ++ /* return the ordinal of the first channel in the bitmap */ ++ while (chans != 0 && (chans & 1) == 0) { ++ chans >>= 1; ++ chan++; ++ } ++ /* claim the channel */ ++ dmaman->chan_available &= ~(1 << chan); ++ ++ return chan; ++} ++ ++static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan) ++{ ++ if (chan < 0) ++ return -EINVAL; ++ ++ if ((1 << chan) & dmaman->chan_available) ++ return -EIDRM; ++ ++ dmaman->chan_available |= (1 << chan); ++ ++ return 0; ++} ++ ++/* DMA Manager Monitor */ ++ ++extern int bcm_dma_chan_alloc(unsigned preferred_feature_set, ++ void __iomem **out_dma_base, int *out_dma_irq) ++{ ++ struct vc_dmaman *dmaman = g_dmaman; ++ struct platform_device *pdev = to_platform_device(dmaman_dev); ++ struct resource *r; ++ int chan; ++ ++ if (!dmaman_dev) ++ return -ENODEV; ++ ++ mutex_lock(&dmaman->lock); ++ chan = vc_dmaman_chan_alloc(dmaman, preferred_feature_set); ++ if (chan < 0) ++ goto out; ++ ++ r = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan); ++ if (!r) { ++ dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n", ++ chan); ++ vc_dmaman_chan_free(dmaman, chan); ++ chan = -ENOENT; ++ goto out; ++ } ++ ++ *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan); ++ *out_dma_irq = r->start; ++ dev_dbg(dmaman_dev, ++ "Legacy API allocated channel=%d, base=%p, irq=%i\n", ++ chan, *out_dma_base, *out_dma_irq); ++ ++out: ++ mutex_unlock(&dmaman->lock); ++ ++ return chan; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc); ++ ++extern int bcm_dma_chan_free(int channel) ++{ ++ struct vc_dmaman *dmaman = g_dmaman; ++ int rc; ++ ++ if (!dmaman_dev) ++ return -ENODEV; ++ ++ mutex_lock(&dmaman->lock); ++ rc = vc_dmaman_chan_free(dmaman, channel); ++ mutex_unlock(&dmaman->lock); ++ ++ return rc; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_chan_free); ++ ++static int bcm_dmaman_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct vc_dmaman *dmaman; ++ struct resource *r; ++ void __iomem *dma_base; ++ uint32_t val; ++ ++ if (!of_property_read_u32(dev->of_node, ++ "brcm,dma-channel-mask", &val)) ++ dmachans = val; ++ else if (dmachans == -1) ++ dmachans = DEFAULT_DMACHAN_BITMAP; ++ ++ dmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL); ++ if (!dmaman) ++ return -ENOMEM; ++ ++ mutex_init(&dmaman->lock); ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dma_base = devm_ioremap_resource(dev, r); ++ if (IS_ERR(dma_base)) ++ return PTR_ERR(dma_base); ++ ++ vc_dmaman_init(dmaman, dma_base, dmachans); ++ g_dmaman = dmaman; ++ dmaman_dev = dev; ++ ++ dev_info(dev, "DMA legacy API manager at %p, dmachans=0x%x\n", ++ dma_base, dmachans); ++ ++ return 0; ++} ++ ++static int bcm_dmaman_remove(struct platform_device *pdev) ++{ ++ dmaman_dev = NULL; ++ ++ return 0; ++} ++ ++#else /* CONFIG_DMA_BCM2708_LEGACY */ ++ ++static int bcm_dmaman_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++#endif /* CONFIG_DMA_BCM2708_LEGACY */ ++ ++/* ++ * DMA engine ++ */ ++ ++struct bcm2835_dmadev { ++ struct dma_device ddev; ++ spinlock_t lock; ++ void __iomem *base; ++ struct device_dma_parameters dma_parms; ++}; ++ ++struct bcm2835_dma_cb { ++ uint32_t info; ++ uint32_t src; ++ uint32_t dst; ++ uint32_t length; ++ uint32_t stride; ++ uint32_t next; ++ uint32_t pad[2]; ++}; ++ ++struct bcm2835_chan { ++ struct virt_dma_chan vc; ++ struct list_head node; ++ ++ struct dma_slave_config cfg; ++ bool cyclic; ++ ++ int ch; ++ struct bcm2835_desc *desc; ++ ++ void __iomem *chan_base; ++ int irq_number; ++ ++ unsigned int dreq; ++}; ++ ++struct bcm2835_desc { ++ struct virt_dma_desc vd; ++ enum dma_transfer_direction dir; ++ ++ unsigned int control_block_size; ++ struct bcm2835_dma_cb *control_block_base; ++ dma_addr_t control_block_base_phys; ++ ++ unsigned int frames; ++ size_t size; ++}; ++ ++#define BCM2835_DMA_CS 0x00 ++#define BCM2835_DMA_ADDR 0x04 ++#define BCM2835_DMA_SOURCE_AD 0x0c ++#define BCM2835_DMA_DEST_AD 0x10 ++#define BCM2835_DMA_NEXTCB 0x1C ++ ++/* DMA CS Control and Status bits */ ++#define BCM2835_DMA_ACTIVE BIT(0) ++#define BCM2835_DMA_INT BIT(2) ++#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ ++#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ ++#define BCM2835_DMA_ERR BIT(8) ++#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ ++#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ ++ ++#define BCM2835_DMA_INT_EN BIT(0) ++#define BCM2835_DMA_WAIT_RESP BIT(3) ++#define BCM2835_DMA_D_INC BIT(4) ++#define BCM2835_DMA_D_WIDTH BIT(5) ++#define BCM2835_DMA_D_DREQ BIT(6) ++#define BCM2835_DMA_S_INC BIT(8) ++#define BCM2835_DMA_S_WIDTH BIT(9) ++#define BCM2835_DMA_S_DREQ BIT(10) ++ ++#define BCM2835_DMA_PER_MAP(x) ((x) << 16) ++#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21) ++ ++#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */ ++ ++#define BCM2835_DMA_DATA_TYPE_S8 1 ++#define BCM2835_DMA_DATA_TYPE_S16 2 ++#define BCM2835_DMA_DATA_TYPE_S32 4 ++#define BCM2835_DMA_DATA_TYPE_S128 16 ++ ++#define BCM2835_DMA_BULK_MASK BIT(0) ++#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3)) ++ ++ ++/* Valid only for channels 0 - 14, 15 has its own base address */ ++#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ ++#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) ++ ++#define MAX_LITE_TRANSFER 32768 ++#define MAX_NORMAL_TRANSFER 1073741824 ++ ++static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) ++{ ++ return container_of(d, struct bcm2835_dmadev, ddev); ++} ++ ++static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) ++{ ++ return container_of(c, struct bcm2835_chan, vc.chan); ++} ++ ++static inline struct bcm2835_desc *to_bcm2835_dma_desc( ++ struct dma_async_tx_descriptor *t) ++{ ++ return container_of(t, struct bcm2835_desc, vd.tx); ++} ++ ++static void dma_dumpregs(struct bcm2835_chan *c) ++{ ++ pr_debug("-------------DMA DUMPREGS-------------\n"); ++ pr_debug("CS= %u\n", ++ readl(c->chan_base + BCM2835_DMA_CS)); ++ pr_debug("ADDR= %u\n", ++ readl(c->chan_base + BCM2835_DMA_ADDR)); ++ pr_debug("SOURCE_ADDR= %u\n", ++ readl(c->chan_base + BCM2835_DMA_SOURCE_AD)); ++ pr_debug("DEST_AD= %u\n", ++ readl(c->chan_base + BCM2835_DMA_DEST_AD)); ++ pr_debug("NEXTCB= %u\n", ++ readl(c->chan_base + BCM2835_DMA_NEXTCB)); ++ pr_debug("--------------------------------------\n"); ++} ++ ++static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) ++{ ++ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd); ++ dma_free_coherent(desc->vd.tx.chan->device->dev, ++ desc->control_block_size, ++ desc->control_block_base, ++ desc->control_block_base_phys); ++ kfree(desc); ++} ++ ++static int bcm2835_dma_abort(void __iomem *chan_base) ++{ ++ unsigned long cs; ++ long int timeout = 10000; ++ ++ cs = readl(chan_base + BCM2835_DMA_CS); ++ if (!(cs & BCM2835_DMA_ACTIVE)) ++ return 0; ++ ++ /* Write 0 to the active bit - Pause the DMA */ ++ writel(0, chan_base + BCM2835_DMA_CS); ++ ++ /* Wait for any current AXI transfer to complete */ ++ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) { ++ cpu_relax(); ++ cs = readl(chan_base + BCM2835_DMA_CS); ++ } ++ ++ /* We'll un-pause when we set of our next DMA */ ++ if (!timeout) ++ return -ETIMEDOUT; ++ ++ if (!(cs & BCM2835_DMA_ACTIVE)) ++ return 0; ++ ++ /* Terminate the control block chain */ ++ writel(0, chan_base + BCM2835_DMA_NEXTCB); ++ ++ /* Abort the whole DMA */ ++ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, ++ chan_base + BCM2835_DMA_CS); ++ ++ return 0; ++} ++ ++ ++static void bcm2835_dma_start_desc(struct bcm2835_chan *c) ++{ ++ struct virt_dma_desc *vd = vchan_next_desc(&c->vc); ++ struct bcm2835_desc *d; ++ ++ if (!vd) { ++ c->desc = NULL; ++ return; ++ } ++ ++ list_del(&vd->node); ++ ++ c->desc = d = to_bcm2835_dma_desc(&vd->tx); ++ ++ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR); ++ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); ++ ++} ++ ++static irqreturn_t bcm2835_dma_callback(int irq, void *data) ++{ ++ struct bcm2835_chan *c = data; ++ struct bcm2835_desc *d; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&c->vc.lock, flags); ++ ++ /* Acknowledge interrupt */ ++ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS); ++ ++ d = c->desc; ++ ++ if (d) { ++ if (c->cyclic) { ++ vchan_cyclic_callback(&d->vd); ++ ++ /* Keep the DMA engine running */ ++ writel(BCM2835_DMA_ACTIVE, ++ c->chan_base + BCM2835_DMA_CS); ++ ++ } else { ++ vchan_cookie_complete(&c->desc->vd); ++ bcm2835_dma_start_desc(c); ++ } ++ } ++ ++ spin_unlock_irqrestore(&c->vc.lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ int ret; ++ ++ dev_dbg(c->vc.chan.device->dev, ++ "Allocating DMA channel %d\n", c->ch); ++ ++ ret = request_irq(c->irq_number, ++ bcm2835_dma_callback, 0, "DMA IRQ", c); ++ ++ return ret; ++} ++ ++static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ ++ vchan_free_chan_resources(&c->vc); ++ free_irq(c->irq_number, c); ++ ++ dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); ++} ++ ++static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) ++{ ++ return d->size; ++} ++ ++static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) ++{ ++ unsigned int i; ++ size_t size; ++ ++ for (size = i = 0; i < d->frames; i++) { ++ struct bcm2835_dma_cb *control_block = ++ &d->control_block_base[i]; ++ size_t this_size = control_block->length; ++ dma_addr_t dma; ++ ++ if (d->dir == DMA_DEV_TO_MEM) ++ dma = control_block->dst; ++ else ++ dma = control_block->src; ++ ++ if (size) ++ size += this_size; ++ else if (addr >= dma && addr < dma + this_size) ++ size += dma + this_size - addr; ++ } ++ ++ return size; ++} ++ ++static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, ++ dma_cookie_t cookie, struct dma_tx_state *txstate) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ struct bcm2835_desc *d; ++ struct virt_dma_desc *vd; ++ enum dma_status ret; ++ unsigned long flags; ++ dma_addr_t pos; ++ ++ ret = dma_cookie_status(chan, cookie, txstate); ++ if (ret == DMA_COMPLETE || !txstate) ++ return ret; ++ ++ spin_lock_irqsave(&c->vc.lock, flags); ++ vd = vchan_find_desc(&c->vc, cookie); ++ if (vd) { ++ txstate->residue = ++ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); ++ } else if (c->desc && c->desc->vd.tx.cookie == cookie) { ++ d = c->desc; ++ ++ if (d->dir == DMA_MEM_TO_DEV) ++ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); ++ else if (d->dir == DMA_DEV_TO_MEM) ++ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); ++ else ++ pos = 0; ++ ++ txstate->residue = bcm2835_dma_desc_size_pos(d, pos); ++ } else { ++ txstate->residue = 0; ++ } ++ ++ spin_unlock_irqrestore(&c->vc.lock, flags); ++ ++ return ret; ++} ++ ++static void bcm2835_dma_issue_pending(struct dma_chan *chan) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&c->vc.lock, flags); ++ if (vchan_issue_pending(&c->vc) && !c->desc) ++ bcm2835_dma_start_desc(c); ++ ++ spin_unlock_irqrestore(&c->vc.lock, flags); ++} ++ ++static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( ++ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, ++ size_t period_len, enum dma_transfer_direction direction, ++ unsigned long flags) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ enum dma_slave_buswidth dev_width; ++ struct bcm2835_desc *d; ++ dma_addr_t dev_addr; ++ unsigned int es, sync_type; ++ unsigned int frame, max_size; ++ ++ /* Grab configuration */ ++ if (!is_slave_direction(direction)) { ++ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); ++ return NULL; ++ } ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ dev_addr = c->cfg.src_addr; ++ dev_width = c->cfg.src_addr_width; ++ sync_type = BCM2835_DMA_S_DREQ; ++ } else { ++ dev_addr = c->cfg.dst_addr; ++ dev_width = c->cfg.dst_addr_width; ++ sync_type = BCM2835_DMA_D_DREQ; ++ } ++ ++ /* Bus width translates to the element size (ES) */ ++ switch (dev_width) { ++ case DMA_SLAVE_BUSWIDTH_4_BYTES: ++ es = BCM2835_DMA_DATA_TYPE_S32; ++ break; ++ default: ++ return NULL; ++ } ++ ++ /* Now allocate and setup the descriptor. */ ++ d = kzalloc(sizeof(*d), GFP_NOWAIT); ++ if (!d) ++ return NULL; ++ ++ d->dir = direction; ++ ++ if (c->ch >= 8) /* we have a LITE channel */ ++ max_size = MAX_LITE_TRANSFER; ++ else ++ max_size = MAX_NORMAL_TRANSFER; ++ period_len = min(period_len, max_size); ++ ++ d->frames = (buf_len-1) / period_len + 1; ++ ++ /* Allocate memory for control blocks */ ++ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); ++ d->control_block_base = dma_zalloc_coherent(chan->device->dev, ++ d->control_block_size, &d->control_block_base_phys, ++ GFP_NOWAIT); ++ ++ if (!d->control_block_base) { ++ kfree(d); ++ return NULL; ++ } ++ ++ /* ++ * Iterate over all frames, create a control block ++ * for each frame and link them together. ++ */ ++ for (frame = 0; frame < d->frames; frame++) { ++ struct bcm2835_dma_cb *control_block = ++ &d->control_block_base[frame]; ++ ++ /* Setup adresses */ ++ if (d->dir == DMA_DEV_TO_MEM) { ++ control_block->info = BCM2835_DMA_D_INC; ++ control_block->src = dev_addr; ++ control_block->dst = buf_addr + frame * period_len; ++ } else { ++ control_block->info = BCM2835_DMA_S_INC; ++ control_block->src = buf_addr + frame * period_len; ++ control_block->dst = dev_addr; ++ } ++ ++ /* Enable interrupt */ ++ control_block->info |= BCM2835_DMA_INT_EN; ++ ++ /* Setup synchronization */ ++ if (sync_type != 0) ++ control_block->info |= sync_type; ++ ++ /* Setup DREQ channel */ ++ if (c->cfg.slave_id != 0) ++ control_block->info |= ++ BCM2835_DMA_PER_MAP(c->cfg.slave_id); ++ ++ /* Length of a frame */ ++ if (frame != d->frames-1) ++ control_block->length = period_len; ++ else ++ control_block->length = buf_len - (d->frames - 1) * period_len; ++ ++ d->size += control_block->length; ++ ++ /* ++ * Next block is the next frame. ++ * This function is called on cyclic DMA transfers. ++ * Therefore, wrap around at number of frames. ++ */ ++ control_block->next = d->control_block_base_phys + ++ sizeof(struct bcm2835_dma_cb) ++ * ((frame + 1) % d->frames); ++ } ++ ++ c->cyclic = true; ++ ++ return vchan_tx_prep(&c->vc, &d->vd, flags); ++} ++ ++ ++static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( ++ struct dma_chan *chan, struct scatterlist *sgl, ++ unsigned int sg_len, enum dma_transfer_direction direction, ++ unsigned long flags, void *context) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ enum dma_slave_buswidth dev_width; ++ struct bcm2835_desc *d; ++ dma_addr_t dev_addr; ++ struct scatterlist *sgent; ++ unsigned int es, sync_type; ++ unsigned int i, j, splitct, max_size; ++ ++ if (!is_slave_direction(direction)) { ++ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); ++ return NULL; ++ } ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ dev_addr = c->cfg.src_addr; ++ dev_width = c->cfg.src_addr_width; ++ sync_type = BCM2835_DMA_S_DREQ; ++ } else { ++ dev_addr = c->cfg.dst_addr; ++ dev_width = c->cfg.dst_addr_width; ++ sync_type = BCM2835_DMA_D_DREQ; ++ } ++ ++ /* Bus width translates to the element size (ES) */ ++ switch (dev_width) { ++ case DMA_SLAVE_BUSWIDTH_4_BYTES: ++ es = BCM2835_DMA_DATA_TYPE_S32; ++ break; ++ default: ++ return NULL; ++ } ++ ++ /* Now allocate and setup the descriptor. */ ++ d = kzalloc(sizeof(*d), GFP_NOWAIT); ++ if (!d) ++ return NULL; ++ ++ d->dir = direction; ++ ++ if (c->ch >= 8) /* we have a LITE channel */ ++ max_size = MAX_LITE_TRANSFER; ++ else ++ max_size = MAX_NORMAL_TRANSFER; ++ ++ /* We store the length of the SG list in d->frames ++ taking care to account for splitting up transfers ++ too large for a LITE channel */ ++ ++ d->frames = 0; ++ for_each_sg(sgl, sgent, sg_len, i) { ++ uint32_t len = sg_dma_len(sgent); ++ d->frames += 1 + len / max_size; ++ } ++ ++ /* Allocate memory for control blocks */ ++ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); ++ d->control_block_base = dma_zalloc_coherent(chan->device->dev, ++ d->control_block_size, &d->control_block_base_phys, ++ GFP_NOWAIT); ++ ++ if (!d->control_block_base) { ++ kfree(d); ++ return NULL; ++ } ++ ++ /* ++ * Iterate over all SG entries, create a control block ++ * for each frame and link them together. ++ */ ++ ++ /* we count the number of times an SG entry had to be splitct ++ as a result of using a LITE channel */ ++ splitct = 0; ++ ++ for_each_sg(sgl, sgent, sg_len, i) { ++ dma_addr_t addr = sg_dma_address(sgent); ++ uint32_t len = sg_dma_len(sgent); ++ ++ for (j = 0; j < len; j += max_size) { ++ struct bcm2835_dma_cb *control_block = ++ &d->control_block_base[i+splitct]; ++ ++ /* Setup adresses */ ++ if (d->dir == DMA_DEV_TO_MEM) { ++ control_block->info = BCM2835_DMA_D_INC | ++ BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ; ++ control_block->src = dev_addr; ++ control_block->dst = addr + (dma_addr_t)j; ++ } else { ++ control_block->info = BCM2835_DMA_S_INC | ++ BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ; ++ control_block->src = addr + (dma_addr_t)j; ++ control_block->dst = dev_addr; ++ } ++ ++ /* Common part */ ++ u32 waits = SDHCI_BCM_DMA_WAITS; ++ if ((dma_debug >> 0) & 0x1f) ++ waits = (dma_debug >> 0) & 0x1f; ++ control_block->info |= BCM2835_DMA_WAITS(waits); ++ control_block->info |= BCM2835_DMA_WAIT_RESP; ++ ++ /* Enable */ ++ if (i == sg_len-1 && len-j <= max_size) ++ control_block->info |= BCM2835_DMA_INT_EN; ++ ++ /* Setup synchronization */ ++ if (sync_type != 0) ++ control_block->info |= sync_type; ++ ++ /* Setup DREQ channel */ ++ if (c->dreq != 0) ++ control_block->info |= ++ BCM2835_DMA_PER_MAP(c->dreq); ++ ++ /* Length of a frame */ ++ control_block->length = min(len-j, max_size); ++ d->size += control_block->length; ++ ++ /* ++ * Next block is the next frame. ++ */ ++ if (i < sg_len-1 || len-j > max_size) { ++ /* next block is the next frame. */ ++ control_block->next = d->control_block_base_phys + ++ sizeof(struct bcm2835_dma_cb) * (i + splitct + 1); ++ } else { ++ /* next block is empty. */ ++ control_block->next = 0; ++ } ++ ++ if (len-j > max_size) ++ splitct++; ++ } ++ } ++ ++ c->cyclic = false; ++ ++ return vchan_tx_prep(&c->vc, &d->vd, flags); ++} ++ ++static int bcm2835_dma_slave_config(struct dma_chan *chan, ++ struct dma_slave_config *cfg) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ if ((cfg->direction == DMA_DEV_TO_MEM && ++ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || ++ (cfg->direction == DMA_MEM_TO_DEV && ++ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || ++ !is_slave_direction(cfg->direction)) { ++ return -EINVAL; ++ } ++ ++ c->cfg = *cfg; ++ if (!c->dreq) ++ c->dreq = cfg->slave_id; ++ ++ return 0; ++} ++ ++static int bcm2835_dma_terminate_all(struct dma_chan *chan) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); ++ unsigned long flags; ++ int timeout = 10000; ++ LIST_HEAD(head); ++ ++ spin_lock_irqsave(&c->vc.lock, flags); ++ ++ /* Prevent this channel being scheduled */ ++ spin_lock(&d->lock); ++ list_del_init(&c->node); ++ spin_unlock(&d->lock); ++ ++ /* ++ * Stop DMA activity: we assume the callback will not be called ++ * after bcm_dma_abort() returns (even if it does, it will see ++ * c->desc is NULL and exit.) ++ */ ++ if (c->desc) { ++ c->desc = NULL; ++ bcm2835_dma_abort(c->chan_base); ++ ++ /* Wait for stopping */ ++ while (--timeout) { ++ if (!(readl(c->chan_base + BCM2835_DMA_CS) & ++ BCM2835_DMA_ACTIVE)) ++ break; ++ ++ cpu_relax(); ++ } ++ ++ if (!timeout) ++ dev_err(d->ddev.dev, "DMA transfer could not be terminated\n"); ++ } ++ ++ vchan_get_all_descriptors(&c->vc, &head); ++ spin_unlock_irqrestore(&c->vc.lock, flags); ++ vchan_dma_desc_free_list(&c->vc, &head); ++ ++ return 0; ++} ++ ++#ifndef CONFIG_DMA_BCM2708_LEGACY ++static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq) ++{ ++ struct bcm2835_chan *c; ++ ++ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); ++ if (!c) ++ return -ENOMEM; ++ ++ c->vc.desc_free = bcm2835_dma_desc_free; ++ vchan_init(&c->vc, &d->ddev); ++ INIT_LIST_HEAD(&c->node); ++ ++ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); ++ c->ch = chan_id; ++ c->irq_number = irq; ++ ++ return 0; ++} ++#endif ++ ++static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d, ++ void __iomem *chan_base, int chan_id, int irq) ++{ ++ struct bcm2835_chan *c; ++ ++ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); ++ if (!c) ++ return -ENOMEM; ++ ++ c->vc.desc_free = bcm2835_dma_desc_free; ++ vchan_init(&c->vc, &d->ddev); ++ INIT_LIST_HEAD(&c->node); ++ ++ c->chan_base = chan_base; ++ c->ch = chan_id; ++ c->irq_number = irq; ++ ++ return 0; ++} ++ ++ ++static void bcm2835_dma_free(struct bcm2835_dmadev *od) ++{ ++ struct bcm2835_chan *c, *next; ++ ++ list_for_each_entry_safe(c, next, &od->ddev.channels, ++ vc.chan.device_node) { ++ list_del(&c->vc.chan.device_node); ++ tasklet_kill(&c->vc.task); ++ } ++} ++ ++static const struct of_device_id bcm2835_dma_of_match[] = { ++ { .compatible = "brcm,bcm2835-dma", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); ++ ++static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, ++ struct of_dma *ofdma) ++{ ++ struct bcm2835_dmadev *d = ofdma->of_dma_data; ++ struct dma_chan *chan; ++ ++ chan = dma_get_any_slave_channel(&d->ddev); ++ if (!chan) ++ return NULL; ++ ++ /* Set DREQ from param */ ++ to_bcm2835_dma_chan(chan)->dreq = spec->args[0]; ++ ++ return chan; ++} ++ ++static int bcm2835_dma_probe(struct platform_device *pdev) ++{ ++ struct bcm2835_dmadev *od; ++#ifndef CONFIG_DMA_BCM2708_LEGACY ++ struct resource *res; ++ void __iomem *base; ++ uint32_t chans_available; ++#endif ++ int rc; ++ int i; ++ int irq; ++ ++ ++ if (!pdev->dev.dma_mask) ++ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; ++ ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++ ++ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (rc) ++ return rc; ++ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ ++ ++ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); ++ if (!od) ++ return -ENOMEM; ++ ++ rc = bcm_dmaman_probe(pdev); ++ if (rc) ++ return rc; ++ ++ pdev->dev.dma_parms = &od->dma_parms; ++ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); ++ ++ ++ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); ++ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); ++ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); ++ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; ++ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; ++ od->ddev.device_tx_status = bcm2835_dma_tx_status; ++ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; ++ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; ++ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; ++ od->ddev.device_terminate_all = bcm2835_dma_terminate_all; ++ od->ddev.device_config = bcm2835_dma_slave_config; ++ od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); ++ od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; ++ od->ddev.dev = &pdev->dev; ++ INIT_LIST_HEAD(&od->ddev.channels); ++ spin_lock_init(&od->lock); ++ ++ platform_set_drvdata(pdev, od); ++ ++ for (i = 0; i < 5; i++) { ++ void __iomem *chan_base; ++ int chan_id; ++ ++ chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE, ++ &chan_base, ++ &irq); ++ ++ if (chan_id < 0) ++ break; ++ ++ rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq); ++ if (rc) ++ goto err_no_dma; ++ } ++ ++ if (pdev->dev.of_node) { ++ rc = of_dma_controller_register(pdev->dev.of_node, ++ bcm2835_dma_xlate, od); ++ if (rc) { ++ dev_err(&pdev->dev, ++ "Failed to register DMA controller\n"); ++ goto err_no_dma; ++ } ++ } ++ ++#else ++ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); ++ if (rc) ++ return rc; ++ ++ ++ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); ++ if (!od) ++ return -ENOMEM; ++ ++ pdev->dev.dma_parms = &od->dma_parms; ++ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); ++ ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ od->base = base; ++ ++ ++ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); ++ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); ++ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); ++ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; ++ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; ++ od->ddev.device_tx_status = bcm2835_dma_tx_status; ++ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; ++ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; ++ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; ++ od->ddev.device_terminate_all = bcm2835_dma_terminate_all; ++ od->ddev.device_config = bcm2835_dma_slave_config; ++ od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); ++ od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; ++ od->ddev.dev = &pdev->dev; ++ INIT_LIST_HEAD(&od->ddev.channels); ++ spin_lock_init(&od->lock); ++ ++ platform_set_drvdata(pdev, od); ++ ++ ++ /* Request DMA channel mask from device tree */ ++ if (of_property_read_u32(pdev->dev.of_node, ++ "brcm,dma-channel-mask", ++ &chans_available)) { ++ dev_err(&pdev->dev, "Failed to get channel mask\n"); ++ rc = -EINVAL; ++ goto err_no_dma; ++ } ++ ++ ++ /* ++ * Do not use the FIQ and BULK channels, ++ * because they are used by the GPU. ++ */ ++ chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK); ++ ++ ++ for (i = 0; i < pdev->num_resources; i++) { ++ irq = platform_get_irq(pdev, i); ++ if (irq < 0) ++ break; ++ ++ if (chans_available & (1 << i)) { ++ rc = bcm2835_dma_chan_init(od, i, irq); ++ if (rc) ++ goto err_no_dma; ++ } ++ } ++ ++ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); ++ ++ /* Device-tree DMA controller registration */ ++ rc = of_dma_controller_register(pdev->dev.of_node, ++ bcm2835_dma_xlate, od); ++ if (rc) { ++ dev_err(&pdev->dev, "Failed to register DMA controller\n"); ++ goto err_no_dma; ++ } ++#endif ++ ++ rc = dma_async_device_register(&od->ddev); ++ if (rc) { ++ dev_err(&pdev->dev, ++ "Failed to register slave DMA engine device: %d\n", rc); ++ goto err_no_dma; ++ } ++ ++ dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n"); ++ dev_info(&pdev->dev, "dma_debug:%x\n", dma_debug); ++ ++ return 0; ++ ++err_no_dma: ++ bcm2835_dma_free(od); ++ return rc; ++} ++ ++static int bcm2835_dma_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_dmadev *od = platform_get_drvdata(pdev); ++ ++ dma_async_device_unregister(&od->ddev); ++ bcm2835_dma_free(od); ++ bcm_dmaman_remove(pdev); ++ ++ return 0; ++} ++ ++static struct platform_driver bcm2835_dma_driver = { ++ .probe = bcm2835_dma_probe, ++ .remove = bcm2835_dma_remove, ++ .driver = { ++ .name = "bcm2708-dmaengine", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(bcm2835_dma_of_match), ++ }, ++}; ++ ++static int bcm2835_init(void) ++{ ++ return platform_driver_register(&bcm2835_dma_driver); ++} ++ ++static void bcm2835_exit(void) ++{ ++ platform_driver_unregister(&bcm2835_dma_driver); ++} ++ ++/* ++ * Load after serial driver (arch_initcall) so we see the messages if it fails, ++ * but before drivers (module_init) that need a DMA channel. ++ */ ++subsys_initcall(bcm2835_init); ++module_exit(bcm2835_exit); ++ ++module_param(dma_debug, uint, 0644); ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++/* Keep backward compatibility: dma.dmachans= */ ++#undef MODULE_PARAM_PREFIX ++#define MODULE_PARAM_PREFIX "dma." ++module_param(dmachans, int, 0644); ++#endif ++MODULE_ALIAS("platform:bcm2835-dma"); ++MODULE_DESCRIPTION("BCM2835 DMA engine driver"); ++MODULE_AUTHOR("Florian Meier "); ++MODULE_AUTHOR("Gellert Weisz "); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/include/linux/platform_data/dma-bcm2708.h +@@ -0,0 +1,127 @@ ++/* ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _PLAT_BCM2708_DMA_H ++#define _PLAT_BCM2708_DMA_H ++ ++/* DMA CS Control and Status bits */ ++#define BCM2708_DMA_ACTIVE BIT(0) ++#define BCM2708_DMA_INT BIT(2) ++#define BCM2708_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ ++#define BCM2708_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ ++#define BCM2708_DMA_ERR BIT(8) ++#define BCM2708_DMA_ABORT BIT(30) /* stop current CB, go to next, WO */ ++#define BCM2708_DMA_RESET BIT(31) /* WO, self clearing */ ++ ++/* DMA control block "info" field bits */ ++#define BCM2708_DMA_INT_EN BIT(0) ++#define BCM2708_DMA_TDMODE BIT(1) ++#define BCM2708_DMA_WAIT_RESP BIT(3) ++#define BCM2708_DMA_D_INC BIT(4) ++#define BCM2708_DMA_D_WIDTH BIT(5) ++#define BCM2708_DMA_D_DREQ BIT(6) ++#define BCM2708_DMA_S_INC BIT(8) ++#define BCM2708_DMA_S_WIDTH BIT(9) ++#define BCM2708_DMA_S_DREQ BIT(10) ++ ++#define BCM2708_DMA_BURST(x) (((x) & 0xf) << 12) ++#define BCM2708_DMA_PER_MAP(x) ((x) << 16) ++#define BCM2708_DMA_WAITS(x) (((x) & 0x1f) << 21) ++ ++#define BCM2708_DMA_DREQ_EMMC 11 ++#define BCM2708_DMA_DREQ_SDHOST 13 ++ ++#define BCM2708_DMA_CS 0x00 /* Control and Status */ ++#define BCM2708_DMA_ADDR 0x04 ++/* the current control block appears in the following registers - read only */ ++#define BCM2708_DMA_INFO 0x08 ++#define BCM2708_DMA_SOURCE_AD 0x0c ++#define BCM2708_DMA_DEST_AD 0x10 ++#define BCM2708_DMA_NEXTCB 0x1C ++#define BCM2708_DMA_DEBUG 0x20 ++ ++#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS) ++#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR) ++ ++#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w)) ++ ++/* When listing features we can ask for when allocating DMA channels give ++ those with higher priority smaller ordinal numbers */ ++#define BCM_DMA_FEATURE_FAST_ORD 0 ++#define BCM_DMA_FEATURE_BULK_ORD 1 ++#define BCM_DMA_FEATURE_NORMAL_ORD 2 ++#define BCM_DMA_FEATURE_LITE_ORD 3 ++#define BCM_DMA_FEATURE_FAST BIT(BCM_DMA_FEATURE_FAST_ORD) ++#define BCM_DMA_FEATURE_BULK BIT(BCM_DMA_FEATURE_BULK_ORD) ++#define BCM_DMA_FEATURE_NORMAL BIT(BCM_DMA_FEATURE_NORMAL_ORD) ++#define BCM_DMA_FEATURE_LITE BIT(BCM_DMA_FEATURE_LITE_ORD) ++#define BCM_DMA_FEATURE_COUNT 4 ++ ++struct bcm2708_dma_cb { ++ unsigned long info; ++ unsigned long src; ++ unsigned long dst; ++ unsigned long length; ++ unsigned long stride; ++ unsigned long next; ++ unsigned long pad[2]; ++}; ++ ++struct scatterlist; ++ ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++ ++int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len); ++void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block); ++void bcm_dma_wait_idle(void __iomem *dma_chan_base); ++bool bcm_dma_is_busy(void __iomem *dma_chan_base); ++int bcm_dma_abort(void __iomem *dma_chan_base); ++ ++/* return channel no or -ve error */ ++int bcm_dma_chan_alloc(unsigned preferred_feature_set, ++ void __iomem **out_dma_base, int *out_dma_irq); ++int bcm_dma_chan_free(int channel); ++ ++#else /* CONFIG_DMA_BCM2708_LEGACY */ ++ ++static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, ++ int sg_len) ++{ ++ return 0; ++} ++ ++static inline void bcm_dma_start(void __iomem *dma_chan_base, ++ dma_addr_t control_block) { } ++ ++static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { } ++ ++static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base) ++{ ++ return false; ++} ++ ++static inline int bcm_dma_abort(void __iomem *dma_chan_base) ++{ ++ return -EINVAL; ++} ++ ++static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set, ++ void __iomem **out_dma_base, ++ int *out_dma_irq) ++{ ++ return -EINVAL; ++} ++ ++static inline int bcm_dma_chan_free(int channel) ++{ ++ return -EINVAL; ++} ++ ++#endif /* CONFIG_DMA_BCM2708_LEGACY */ ++ ++#endif /* _PLAT_BCM2708_DMA_H */ diff --git a/target/linux/brcm2708/patches-4.1/0008-MMC-added-alternative-MMC-driver.patch b/target/linux/brcm2708/patches-4.1/0008-MMC-added-alternative-MMC-driver.patch new file mode 100644 index 0000000..6bce35d --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0008-MMC-added-alternative-MMC-driver.patch @@ -0,0 +1,1805 @@ +From f5d5650a56309979ebdd7835396688ef4f7b9625 Mon Sep 17 00:00:00 2001 +From: gellert +Date: Fri, 15 Aug 2014 16:35:06 +0100 +Subject: [PATCH 008/203] MMC: added alternative MMC driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +mmc: Disable CMD23 transfers on all cards + +Pending wire-level investigation of these types of transfers +and associated errors on bcm2835-mmc, disable for now. Fallback of +CMD18/CMD25 transfers will be used automatically by the MMC layer. + +Reported/Tested-by: Gellert Weisz + +mmc: bcm2835-mmc: enable DT support for all architectures + +Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now. +Enable Device Tree support for all architectures. + +Signed-off-by: Noralf Trønnes + +mmc: bcm2835-mmc: fix probe error handling + +Probe error handling is broken in several places. +Simplify error handling by using device managed functions. +Replace pr_{err,info} with dev_{err,info}. + +Signed-off-by: Noralf Trønnes + +bcm2835-mmc: Add locks when accessing sdhost registers + +bcm2835-mmc: Add range of debug options for slowing things down + +bcm2835-mmc: Add option to disable some delays + +bcm2835-mmc: Add option to disable MMC_QUIRK_BLK_NO_CMD23 + +bcm2835-mmc: Default to disabling MMC_QUIRK_BLK_NO_CMD23 + +bcm2835-mmc: Adding overclocking option + +Allow a different clock speed to be substitued for a requested 50MHz. +This option is exposed using the "overclock_50" DT parameter. +Note that the mmc interface is restricted to EVEN integer divisions of +250MHz, and the highest sensible option is 63 (250/4 = 62.5), the +next being 125 (250/2) which is much too high. + +Use at your own risk. + +bcm2835-mmc: Round up the overclock, so 62 works for 62.5Mhz + +Also only warn once for each overclock setting. + +mmc: bcm2835-mmc: Make available on ARCH_BCM2835 + +Make the bcm2835-mmc driver available for use on ARCH_BCM2835. + +Signed-off-by: Noralf Trønnes + +BCM270x_DT: add bcm2835-mmc entry + +Add Device Tree entry for bcm2835-mmc. +In non-DT mode, don't add the device in the board file. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/mach-bcm2708/bcm2708.c | 31 + + arch/arm/mach-bcm2709/bcm2709.c | 35 +- + drivers/mmc/core/quirks.c | 6 + + drivers/mmc/host/Kconfig | 29 + + drivers/mmc/host/Makefile | 1 + + drivers/mmc/host/bcm2835-mmc.c | 1558 +++++++++++++++++++++++++++++++++++++++ + 6 files changed, 1658 insertions(+), 2 deletions(-) + create mode 100644 drivers/mmc/host/bcm2835-mmc.c + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -401,6 +401,34 @@ static struct platform_device bcm2708_gp + }; + #endif + ++#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */ ++static struct resource bcm2835_emmc_resources[] = { ++ [0] = { ++ .start = EMMC_BASE, ++ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ ++ /* the memory map actually makes SZ_4K available */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_ARASANSDIO, ++ .end = IRQ_ARASANSDIO, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 bcm2835_emmc_dmamask = 0xffffffffUL; ++ ++struct platform_device bcm2835_emmc_device = { ++ .name = "mmc-bcm2835", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources), ++ .resource = bcm2835_emmc_resources, ++ .dev = { ++ .dma_mask = &bcm2835_emmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL}, ++}; ++#endif /* CONFIG_MMC_BCM2835 */ ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -538,6 +566,9 @@ void __init bcm2708_init(void) + bcm_register_device_dt(&bcm2708_fb_device); + bcm_register_device_dt(&bcm2708_usb_device); + ++#ifdef CONFIG_MMC_BCM2835 ++ bcm_register_device_dt(&bcm2835_emmc_device); ++#endif + bcm2708_init_led(); + bcm2708_init_uart1(); + +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -421,6 +421,34 @@ static struct platform_device bcm2708_gp + }; + #endif + ++#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */ ++static struct resource bcm2835_emmc_resources[] = { ++ [0] = { ++ .start = EMMC_BASE, ++ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ ++ /* the memory map actually makes SZ_4K available */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_ARASANSDIO, ++ .end = IRQ_ARASANSDIO, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 bcm2835_emmc_dmamask = 0xffffffffUL; ++ ++struct platform_device bcm2835_emmc_device = { ++ .name = "mmc-bcm2835", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources), ++ .resource = bcm2835_emmc_resources, ++ .dev = { ++ .dma_mask = &bcm2835_emmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL}, ++}; ++#endif /* CONFIG_MMC_BCM2835 */ ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -558,8 +586,11 @@ void __init bcm2709_init(void) + bcm_register_device_dt(&bcm2708_fb_device); + bcm_register_device_dt(&bcm2708_usb_device); + +- bcm2708_init_led(); +- bcm2708_init_uart1(); ++#ifdef CONFIG_MMC_BCM2835 ++ bcm_register_device_dt(&bcm2835_emmc_device); ++#endif ++ bcm2709_init_led(); ++ bcm2709_init_uart1(); + + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { +--- a/drivers/mmc/core/quirks.c ++++ b/drivers/mmc/core/quirks.c +@@ -71,6 +71,7 @@ static const struct mmc_fixup mmc_fixup_ + + void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table) + { ++ extern unsigned mmc_debug; + const struct mmc_fixup *f; + u64 rev = cid_rev_card(card); + +@@ -95,5 +96,10 @@ void mmc_fixup_device(struct mmc_card *c + f->vendor_fixup(card, f->data); + } + } ++ /* SDHCI on BCM2708 - bug causes a certain sequence of CMD23 operations to fail. ++ * Disable this flag for all cards (fall-back to CMD25/CMD18 multi-block transfers). ++ */ ++ if (mmc_debug & (1<<13)) ++ card->quirks |= MMC_QUIRK_BLK_NO_CMD23; + } + EXPORT_SYMBOL(mmc_fixup_device); +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -4,6 +4,35 @@ + + comment "MMC/SD/SDIO Host Controller Drivers" + ++config MMC_BCM2835 ++ tristate "MMC support on BCM2835" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ help ++ This selects the MMC Interface on BCM2835. ++ ++ If you have a controller with this interface, say Y or M here. ++ ++ If unsure, say N. ++ ++config MMC_BCM2835_DMA ++ bool "DMA support on BCM2835 Arasan controller" ++ depends on MMC_BCM2835 ++ help ++ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708 ++ based chips. ++ ++ If unsure, say N. ++ ++config MMC_BCM2835_PIO_DMA_BARRIER ++ int "Block count limit for PIO transfers" ++ depends on MMC_BCM2835 && MMC_BCM2835_DMA ++ range 0 256 ++ default 2 ++ help ++ The inclusive limit in bytes under which PIO will be used instead of DMA ++ ++ If unsure, say 2 here. ++ + config MMC_ARMMMCI + tristate "ARM AMBA Multimedia Card Interface support" + depends on ARM_AMBA +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c + obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o + obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o + obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o ++obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o + obj-$(CONFIG_MMC_WBSD) += wbsd.o + obj-$(CONFIG_MMC_AU1X) += au1xmmc.o + obj-$(CONFIG_MMC_OMAP) += omap.o +--- /dev/null ++++ b/drivers/mmc/host/bcm2835-mmc.c +@@ -0,0 +1,1558 @@ ++/* ++ * BCM2835 MMC host driver. ++ * ++ * Author: Gellert Weisz ++ * Copyright 2014 ++ * ++ * Based on ++ * sdhci-bcm2708.c by Broadcom ++ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko ++ * sdhci.c and sdhci-pci.c by Pierre Ossman ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "sdhci.h" ++ ++ ++#define DRIVER_NAME "mmc-bcm2835" ++ ++#define DBG(f, x...) \ ++pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) ++ ++#ifndef CONFIG_MMC_BCM2835_DMA ++ #define FORCE_PIO ++#endif ++ ++ ++/* the inclusive limit in bytes under which PIO will be used instead of DMA */ ++#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER ++#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER ++#else ++#define PIO_DMA_BARRIER 00 ++#endif ++ ++#define MIN_FREQ 400000 ++#define TIMEOUT_VAL 0xE ++#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1) ++ ++#ifndef BCM2708_PERI_BASE ++ #define BCM2708_PERI_BASE 0x20000000 ++#endif ++ ++/* FIXME: Needs IOMMU support */ ++#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) ++ ++ ++unsigned mmc_debug; ++unsigned mmc_debug2; ++ ++struct bcm2835_host { ++ spinlock_t lock; ++ ++ void __iomem *ioaddr; ++ u32 phys_addr; ++ ++ struct mmc_host *mmc; ++ ++ u32 timeout; ++ ++ int clock; /* Current clock speed */ ++ u8 pwr; /* Current voltage */ ++ ++ unsigned int max_clk; /* Max possible freq */ ++ unsigned int timeout_clk; /* Timeout freq (KHz) */ ++ unsigned int clk_mul; /* Clock Muliplier value */ ++ ++ struct tasklet_struct finish_tasklet; /* Tasklet structures */ ++ ++ struct timer_list timer; /* Timer for timeouts */ ++ ++ struct sg_mapping_iter sg_miter; /* SG state for PIO */ ++ unsigned int blocks; /* remaining PIO blocks */ ++ ++ int irq; /* Device IRQ */ ++ ++ ++ u32 ier; /* cached registers */ ++ ++ struct mmc_request *mrq; /* Current request */ ++ struct mmc_command *cmd; /* Current command */ ++ struct mmc_data *data; /* Current data request */ ++ unsigned int data_early:1; /* Data finished before cmd */ ++ ++ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ ++ ++ u32 thread_isr; ++ ++ u32 shadow; ++ ++ /*DMA part*/ ++ struct dma_chan *dma_chan_rx; /* DMA channel for reads */ ++ struct dma_chan *dma_chan_tx; /* DMA channel for writes */ ++ struct dma_async_tx_descriptor *tx_desc; /* descriptor */ ++ ++ bool have_dma; ++ bool use_dma; ++ /*end of DMA part*/ ++ ++ int max_delay; /* maximum length of time spent waiting */ ++ ++ int flags; /* Host attributes */ ++#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ ++#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ ++#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ ++#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ ++#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ ++ ++ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */ ++ u32 max_overclock; /* Highest reported */ ++}; ++ ++ ++static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from) ++{ ++ unsigned delay; ++ lockdep_assert_held_once(&host->lock); ++ writel(val, host->ioaddr + reg); ++ udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ))); ++ ++ delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf); ++ if (delay && !((1<lock); ++ writel(val, host->ioaddr + reg); ++ ++ delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf); ++ if (delay) ++ udelay(delay); ++} ++ ++static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg) ++{ ++ lockdep_assert_held_once(&host->lock); ++ return readl(host->ioaddr + reg); ++} ++ ++static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg) ++{ ++ u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow : ++ bcm2835_mmc_readl(host, reg & ~3); ++ u32 word_num = (reg >> 1) & 1; ++ u32 word_shift = word_num * 16; ++ u32 mask = 0xffff << word_shift; ++ u32 newval = (oldval & ~mask) | (val << word_shift); ++ ++ if (reg == SDHCI_TRANSFER_MODE) ++ host->shadow = newval; ++ else ++ bcm2835_mmc_writel(host, newval, reg & ~3, 0); ++ ++} ++ ++static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg) ++{ ++ u32 oldval = bcm2835_mmc_readl(host, reg & ~3); ++ u32 byte_num = reg & 3; ++ u32 byte_shift = byte_num * 8; ++ u32 mask = 0xff << byte_shift; ++ u32 newval = (oldval & ~mask) | (val << byte_shift); ++ ++ bcm2835_mmc_writel(host, newval, reg & ~3, 1); ++} ++ ++ ++static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg) ++{ ++ u32 val = bcm2835_mmc_readl(host, (reg & ~3)); ++ u32 word_num = (reg >> 1) & 1; ++ u32 word_shift = word_num * 16; ++ u32 word = (val >> word_shift) & 0xffff; ++ ++ return word; ++} ++ ++static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg) ++{ ++ u32 val = bcm2835_mmc_readl(host, (reg & ~3)); ++ u32 byte_num = reg & 3; ++ u32 byte_shift = byte_num * 8; ++ u32 byte = (val >> byte_shift) & 0xff; ++ ++ return byte; ++} ++ ++static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear) ++{ ++ u32 ier; ++ ++ ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE); ++ ier &= ~clear; ++ /* change which requests generate IRQs - makes no difference to ++ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */ ++ bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2); ++} ++ ++ ++static void bcm2835_mmc_dumpregs(struct bcm2835_host *host) ++{ ++ pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", ++ mmc_hostname(host->mmc)); ++ ++ pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS), ++ bcm2835_mmc_readw(host, SDHCI_HOST_VERSION)); ++ pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", ++ bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE), ++ bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT)); ++ pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_ARGUMENT), ++ bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE)); ++ pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE), ++ bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL)); ++ pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", ++ bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL), ++ bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL)); ++ pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", ++ bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL), ++ bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL)); ++ pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", ++ bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL), ++ bcm2835_mmc_readl(host, SDHCI_INT_STATUS)); ++ pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_INT_ENABLE), ++ bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE)); ++ pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", ++ bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR), ++ bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS)); ++ pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES), ++ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1)); ++ pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", ++ bcm2835_mmc_readw(host, SDHCI_COMMAND), ++ bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT)); ++ pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", ++ bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2)); ++ ++ pr_debug(DRIVER_NAME ": ===========================================\n"); ++} ++ ++ ++static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask) ++{ ++ unsigned long timeout; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET); ++ ++ if (mask & SDHCI_RESET_ALL) ++ host->clock = 0; ++ ++ /* Wait max 100 ms */ ++ timeout = 100; ++ ++ /* hw clears the bit when it's done */ ++ while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) { ++ if (timeout == 0) { ++ pr_err("%s: Reset 0x%x never completed.\n", ++ mmc_hostname(host->mmc), (int)mask); ++ bcm2835_mmc_dumpregs(host); ++ return; ++ } ++ timeout--; ++ spin_unlock_irqrestore(&host->lock, flags); ++ mdelay(1); ++ spin_lock_irqsave(&host->lock, flags); ++ } ++ ++ if (100-timeout > 10 && 100-timeout > host->max_delay) { ++ host->max_delay = 100-timeout; ++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); ++ } ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); ++ ++static void bcm2835_mmc_init(struct bcm2835_host *host, int soft) ++{ ++ unsigned long flags; ++ if (soft) ++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); ++ else ++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); ++ ++ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | ++ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | ++ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | ++ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | ++ SDHCI_INT_RESPONSE; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3); ++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3); ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (soft) { ++ /* force clock reconfiguration */ ++ host->clock = 0; ++ bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios); ++ } ++} ++ ++ ++ ++static void bcm2835_mmc_finish_data(struct bcm2835_host *host); ++ ++static void bcm2835_mmc_dma_complete(void *param) ++{ ++ struct bcm2835_host *host = param; ++ struct dma_chan *dma_chan; ++ unsigned long flags; ++ u32 dir_data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->data && !(host->data->flags & MMC_DATA_WRITE)) { ++ /* otherwise handled in SDHCI IRQ */ ++ dma_chan = host->dma_chan_rx; ++ dir_data = DMA_FROM_DEVICE; ++ ++ dma_unmap_sg(dma_chan->device->dev, ++ host->data->sg, host->data->sg_len, ++ dir_data); ++ ++ bcm2835_mmc_finish_data(host); ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host) ++{ ++ unsigned long flags; ++ size_t blksize, len, chunk; ++ ++ u32 uninitialized_var(scratch); ++ u8 *buf; ++ ++ blksize = host->data->blksz; ++ chunk = 0; ++ ++ local_irq_save(flags); ++ ++ while (blksize) { ++ if (!sg_miter_next(&host->sg_miter)) ++ BUG(); ++ ++ len = min(host->sg_miter.length, blksize); ++ ++ blksize -= len; ++ host->sg_miter.consumed = len; ++ ++ buf = host->sg_miter.addr; ++ ++ while (len) { ++ if (chunk == 0) { ++ scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER); ++ chunk = 4; ++ } ++ ++ *buf = scratch & 0xFF; ++ ++ buf++; ++ scratch >>= 8; ++ chunk--; ++ len--; ++ } ++ } ++ ++ sg_miter_stop(&host->sg_miter); ++ ++ local_irq_restore(flags); ++} ++ ++static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host) ++{ ++ unsigned long flags; ++ size_t blksize, len, chunk; ++ u32 scratch; ++ u8 *buf; ++ ++ blksize = host->data->blksz; ++ chunk = 0; ++ chunk = 0; ++ scratch = 0; ++ ++ local_irq_save(flags); ++ ++ while (blksize) { ++ if (!sg_miter_next(&host->sg_miter)) ++ BUG(); ++ ++ len = min(host->sg_miter.length, blksize); ++ ++ blksize -= len; ++ host->sg_miter.consumed = len; ++ ++ buf = host->sg_miter.addr; ++ ++ while (len) { ++ scratch |= (u32)*buf << (chunk * 8); ++ ++ buf++; ++ chunk++; ++ len--; ++ ++ if ((chunk == 4) || ((len == 0) && (blksize == 0))) { ++ mmc_raw_writel(host, scratch, SDHCI_BUFFER); ++ chunk = 0; ++ scratch = 0; ++ } ++ } ++ } ++ ++ sg_miter_stop(&host->sg_miter); ++ ++ local_irq_restore(flags); ++} ++ ++ ++static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host) ++{ ++ u32 mask; ++ ++ BUG_ON(!host->data); ++ ++ if (host->blocks == 0) ++ return; ++ ++ if (host->data->flags & MMC_DATA_READ) ++ mask = SDHCI_DATA_AVAILABLE; ++ else ++ mask = SDHCI_SPACE_AVAILABLE; ++ ++ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) { ++ ++ if (host->data->flags & MMC_DATA_READ) ++ bcm2835_bcm2835_mmc_read_block_pio(host); ++ else ++ bcm2835_bcm2835_mmc_write_block_pio(host); ++ ++ host->blocks--; ++ ++ /* QUIRK used in sdhci.c removes the 'if' */ ++ /* but it seems this is unnecessary */ ++ if (host->blocks == 0) ++ break; ++ ++ ++ } ++} ++ ++ ++static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host) ++{ ++ u32 len, dir_data, dir_slave; ++ struct dma_async_tx_descriptor *desc = NULL; ++ struct dma_chan *dma_chan; ++ ++ ++ WARN_ON(!host->data); ++ ++ if (!host->data) ++ return; ++ ++ if (host->blocks == 0) ++ return; ++ ++ if (host->data->flags & MMC_DATA_READ) { ++ dma_chan = host->dma_chan_rx; ++ dir_data = DMA_FROM_DEVICE; ++ dir_slave = DMA_DEV_TO_MEM; ++ } else { ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ dir_slave = DMA_MEM_TO_DEV; ++ } ++ ++ BUG_ON(!dma_chan->device); ++ BUG_ON(!dma_chan->device->dev); ++ BUG_ON(!host->data->sg); ++ ++ len = dma_map_sg(dma_chan->device->dev, host->data->sg, ++ host->data->sg_len, dir_data); ++ if (len > 0) { ++ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg, ++ len, dir_slave, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ } else { ++ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); ++ } ++ if (desc) { ++ unsigned long flags; ++ spin_lock_irqsave(&host->lock, flags); ++ bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL | ++ SDHCI_INT_SPACE_AVAIL); ++ host->tx_desc = desc; ++ desc->callback = bcm2835_mmc_dma_complete; ++ desc->callback_param = host; ++ spin_unlock_irqrestore(&host->lock, flags); ++ dmaengine_submit(desc); ++ dma_async_issue_pending(dma_chan); ++ } ++ ++} ++ ++ ++ ++static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host) ++{ ++ u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; ++ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; ++ ++ if (host->use_dma) ++ host->ier = (host->ier & ~pio_irqs) | dma_irqs; ++ else ++ host->ier = (host->ier & ~dma_irqs) | pio_irqs; ++ ++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4); ++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4); ++} ++ ++ ++static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) ++{ ++ u8 count; ++ struct mmc_data *data = cmd->data; ++ ++ WARN_ON(host->data); ++ ++ if (data || (cmd->flags & MMC_RSP_BUSY)) { ++ count = TIMEOUT_VAL; ++ bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL); ++ } ++ ++ if (!data) ++ return; ++ ++ /* Sanity checks */ ++ BUG_ON(data->blksz * data->blocks > 524288); ++ BUG_ON(data->blksz > host->mmc->max_blk_size); ++ BUG_ON(data->blocks > 65535); ++ ++ host->data = data; ++ host->data_early = 0; ++ host->data->bytes_xfered = 0; ++ ++ ++ if (!(host->flags & SDHCI_REQ_USE_DMA)) { ++ int flags; ++ ++ flags = SG_MITER_ATOMIC; ++ if (host->data->flags & MMC_DATA_READ) ++ flags |= SG_MITER_TO_SG; ++ else ++ flags |= SG_MITER_FROM_SG; ++ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); ++ host->blocks = data->blocks; ++ } ++ ++ host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER; ++ ++ bcm2835_mmc_set_transfer_irqs(host); ++ ++ /* Set the DMA boundary value and block size */ ++ bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, ++ data->blksz), SDHCI_BLOCK_SIZE); ++ bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT); ++ ++ BUG_ON(!host->data); ++} ++ ++static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host, ++ struct mmc_command *cmd) ++{ ++ u16 mode; ++ struct mmc_data *data = cmd->data; ++ ++ if (data == NULL) { ++ /* clear Auto CMD settings for no data CMDs */ ++ mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE); ++ bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | ++ SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); ++ return; ++ } ++ ++ WARN_ON(!host->data); ++ ++ mode = SDHCI_TRNS_BLK_CNT_EN; ++ ++ if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) { ++ mode |= SDHCI_TRNS_MULTI; ++ ++ /* ++ * If we are sending CMD23, CMD12 never gets sent ++ * on successful completion (so no Auto-CMD12). ++ */ ++ if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) ++ mode |= SDHCI_TRNS_AUTO_CMD12; ++ else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { ++ mode |= SDHCI_TRNS_AUTO_CMD23; ++ bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5); ++ } ++ } ++ ++ if (data->flags & MMC_DATA_READ) ++ mode |= SDHCI_TRNS_READ; ++ if (host->flags & SDHCI_REQ_USE_DMA) ++ mode |= SDHCI_TRNS_DMA; ++ ++ bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE); ++} ++ ++void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd) ++{ ++ int flags; ++ u32 mask; ++ unsigned long timeout; ++ ++ WARN_ON(host->cmd); ++ ++ /* Wait max 10 ms */ ++ timeout = 1000; ++ ++ mask = SDHCI_CMD_INHIBIT; ++ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) ++ mask |= SDHCI_DATA_INHIBIT; ++ ++ /* We shouldn't wait for data inihibit for stop commands, even ++ though they might use busy signaling */ ++ if (host->mrq->data && (cmd == host->mrq->data->stop)) ++ mask &= ~SDHCI_DATA_INHIBIT; ++ ++ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) { ++ if (timeout == 0) { ++ pr_err("%s: Controller never released inhibit bit(s).\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_mmc_dumpregs(host); ++ cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ timeout--; ++ udelay(10); ++ } ++ ++ if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) { ++ host->max_delay = (1000-timeout)/100; ++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); ++ } ++ ++ timeout = jiffies; ++#ifdef CONFIG_ARCH_BCM2835 ++ if (!cmd->data && cmd->busy_timeout > 9000) ++ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; ++ else ++#endif ++ timeout += 10 * HZ; ++ mod_timer(&host->timer, timeout); ++ ++ host->cmd = cmd; ++ ++ bcm2835_mmc_prepare_data(host, cmd); ++ ++ bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6); ++ ++ bcm2835_mmc_set_transfer_mode(host, cmd); ++ ++ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { ++ pr_err("%s: Unsupported response type!\n", ++ mmc_hostname(host->mmc)); ++ cmd->error = -EINVAL; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ if (!(cmd->flags & MMC_RSP_PRESENT)) ++ flags = SDHCI_CMD_RESP_NONE; ++ else if (cmd->flags & MMC_RSP_136) ++ flags = SDHCI_CMD_RESP_LONG; ++ else if (cmd->flags & MMC_RSP_BUSY) ++ flags = SDHCI_CMD_RESP_SHORT_BUSY; ++ else ++ flags = SDHCI_CMD_RESP_SHORT; ++ ++ if (cmd->flags & MMC_RSP_CRC) ++ flags |= SDHCI_CMD_CRC; ++ if (cmd->flags & MMC_RSP_OPCODE) ++ flags |= SDHCI_CMD_INDEX; ++ ++ if (cmd->data) ++ flags |= SDHCI_CMD_DATA; ++ ++ bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); ++} ++ ++ ++static void bcm2835_mmc_finish_data(struct bcm2835_host *host) ++{ ++ struct mmc_data *data; ++ ++ BUG_ON(!host->data); ++ ++ data = host->data; ++ host->data = NULL; ++ ++ if (data->error) ++ data->bytes_xfered = 0; ++ else ++ data->bytes_xfered = data->blksz * data->blocks; ++ ++ /* ++ * Need to send CMD12 if - ++ * a) open-ended multiblock transfer (no CMD23) ++ * b) error in multiblock transfer ++ */ ++ if (data->stop && ++ (data->error || ++ !host->mrq->sbc)) { ++ ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ if (data->error) { ++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD); ++ bcm2835_mmc_reset(host, SDHCI_RESET_DATA); ++ } ++ ++ bcm2835_mmc_send_command(host, data->stop); ++ } else ++ tasklet_schedule(&host->finish_tasklet); ++} ++ ++static void bcm2835_mmc_finish_command(struct bcm2835_host *host) ++{ ++ int i; ++ ++ BUG_ON(host->cmd == NULL); ++ ++ if (host->cmd->flags & MMC_RSP_PRESENT) { ++ if (host->cmd->flags & MMC_RSP_136) { ++ /* CRC is stripped so we need to do some shifting. */ ++ for (i = 0; i < 4; i++) { ++ host->cmd->resp[i] = bcm2835_mmc_readl(host, ++ SDHCI_RESPONSE + (3-i)*4) << 8; ++ if (i != 3) ++ host->cmd->resp[i] |= ++ bcm2835_mmc_readb(host, ++ SDHCI_RESPONSE + (3-i)*4-1); ++ } ++ } else { ++ host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE); ++ } ++ } ++ ++ host->cmd->error = 0; ++ ++ /* Finished CMD23, now send actual command. */ ++ if (host->cmd == host->mrq->sbc) { ++ host->cmd = NULL; ++ bcm2835_mmc_send_command(host, host->mrq->cmd); ++ ++ if (host->mrq->cmd->data && host->use_dma) { ++ /* DMA transfer starts now, PIO starts after interrupt */ ++ bcm2835_mmc_transfer_dma(host); ++ } ++ } else { ++ ++ /* Processed actual command. */ ++ if (host->data && host->data_early) ++ bcm2835_mmc_finish_data(host); ++ ++ if (!host->cmd->data) ++ tasklet_schedule(&host->finish_tasklet); ++ ++ host->cmd = NULL; ++ } ++} ++ ++ ++static void bcm2835_mmc_timeout_timer(unsigned long data) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = (struct bcm2835_host *)data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->mrq) { ++ pr_err("%s: Timeout waiting for hardware interrupt.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_mmc_dumpregs(host); ++ ++ if (host->data) { ++ host->data->error = -ETIMEDOUT; ++ bcm2835_mmc_finish_data(host); ++ } else { ++ if (host->cmd) ++ host->cmd->error = -ETIMEDOUT; ++ else ++ host->mrq->cmd->error = -ETIMEDOUT; ++ ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ } ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++ ++static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable) ++{ ++ if (!(host->flags & SDHCI_DEVICE_DEAD)) { ++ if (enable) ++ host->ier |= SDHCI_INT_CARD_INT; ++ else ++ host->ier &= ~SDHCI_INT_CARD_INT; ++ ++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7); ++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7); ++ mmiowb(); ++ } ++} ++ ++static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) ++{ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ if (enable) ++ host->flags |= SDHCI_SDIO_IRQ_ENABLED; ++ else ++ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; ++ ++ bcm2835_mmc_enable_sdio_irq_nolock(host, enable); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ ++ BUG_ON(intmask == 0); ++ ++ if (!host->cmd) { ++ pr_err("%s: Got command interrupt 0x%08x even " ++ "though no command operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_mmc_dumpregs(host); ++ return; ++ } ++ ++ if (intmask & SDHCI_INT_TIMEOUT) ++ host->cmd->error = -ETIMEDOUT; ++ else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | ++ SDHCI_INT_INDEX)) { ++ host->cmd->error = -EILSEQ; ++ } ++ ++ if (host->cmd->error) { ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ if (intmask & SDHCI_INT_RESPONSE) ++ bcm2835_mmc_finish_command(host); ++ ++} ++ ++static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ struct dma_chan *dma_chan; ++ u32 dir_data; ++ ++ BUG_ON(intmask == 0); ++ ++ if (!host->data) { ++ /* ++ * The "data complete" interrupt is also used to ++ * indicate that a busy state has ended. See comment ++ * above in sdhci_cmd_irq(). ++ */ ++ if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { ++ if (intmask & SDHCI_INT_DATA_END) { ++ bcm2835_mmc_finish_command(host); ++ return; ++ } ++ } ++ ++ pr_debug("%s: Got data interrupt 0x%08x even " ++ "though no data operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_mmc_dumpregs(host); ++ ++ return; ++ } ++ ++ if (intmask & SDHCI_INT_DATA_TIMEOUT) ++ host->data->error = -ETIMEDOUT; ++ else if (intmask & SDHCI_INT_DATA_END_BIT) ++ host->data->error = -EILSEQ; ++ else if ((intmask & SDHCI_INT_DATA_CRC) && ++ SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND)) ++ != MMC_BUS_TEST_R) ++ host->data->error = -EILSEQ; ++ ++ if (host->use_dma) { ++ if (host->data->flags & MMC_DATA_WRITE) { ++ /* IRQ handled here */ ++ ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ dma_unmap_sg(dma_chan->device->dev, ++ host->data->sg, host->data->sg_len, ++ dir_data); ++ ++ bcm2835_mmc_finish_data(host); ++ } ++ ++ } else { ++ if (host->data->error) ++ bcm2835_mmc_finish_data(host); ++ else { ++ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) ++ bcm2835_mmc_transfer_pio(host); ++ ++ if (intmask & SDHCI_INT_DATA_END) { ++ if (host->cmd) { ++ /* ++ * Data managed to finish before the ++ * command completed. Make sure we do ++ * things in the proper order. ++ */ ++ host->data_early = 1; ++ } else { ++ bcm2835_mmc_finish_data(host); ++ } ++ } ++ } ++ } ++} ++ ++ ++static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id) ++{ ++ irqreturn_t result = IRQ_NONE; ++ struct bcm2835_host *host = dev_id; ++ u32 intmask, mask, unexpected = 0; ++ int max_loops = 16; ++#ifndef CONFIG_ARCH_BCM2835 ++ int cardint = 0; ++#endif ++ ++ spin_lock(&host->lock); ++ ++ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); ++ ++ if (!intmask || intmask == 0xffffffff) { ++ result = IRQ_NONE; ++ goto out; ++ } ++ ++ do { ++ /* Clear selected interrupts. */ ++ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | ++ SDHCI_INT_BUS_POWER); ++ bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8); ++ ++ ++ if (intmask & SDHCI_INT_CMD_MASK) ++ bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); ++ ++ if (intmask & SDHCI_INT_DATA_MASK) ++ bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK); ++ ++ if (intmask & SDHCI_INT_BUS_POWER) ++ pr_err("%s: Card is consuming too much power!\n", ++ mmc_hostname(host->mmc)); ++ ++ if (intmask & SDHCI_INT_CARD_INT) { ++#ifndef CONFIG_ARCH_BCM2835 ++ cardint = 1; ++#else ++ bcm2835_mmc_enable_sdio_irq_nolock(host, false); ++ host->thread_isr |= SDHCI_INT_CARD_INT; ++ result = IRQ_WAKE_THREAD; ++#endif ++ } ++ ++ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | ++ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | ++ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | ++ SDHCI_INT_CARD_INT); ++ ++ if (intmask) { ++ unexpected |= intmask; ++ bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9); ++ } ++ ++ if (result == IRQ_NONE) ++ result = IRQ_HANDLED; ++ ++ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); ++ } while (intmask && --max_loops); ++out: ++ spin_unlock(&host->lock); ++ ++ if (unexpected) { ++ pr_err("%s: Unexpected interrupt 0x%08x.\n", ++ mmc_hostname(host->mmc), unexpected); ++ bcm2835_mmc_dumpregs(host); ++ } ++ ++#ifndef CONFIG_ARCH_BCM2835 ++ if (cardint) ++ mmc_signal_sdio_irq(host->mmc); ++#endif ++ ++ return result; ++} ++ ++#ifdef CONFIG_ARCH_BCM2835 ++static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) ++{ ++ struct bcm2835_host *host = dev_id; ++ unsigned long flags; ++ u32 isr; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ isr = host->thread_isr; ++ host->thread_isr = 0; ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (isr & SDHCI_INT_CARD_INT) { ++ sdio_run_irqs(host->mmc); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ if (host->flags & SDHCI_SDIO_IRQ_ENABLED) ++ bcm2835_mmc_enable_sdio_irq_nolock(host, true); ++ spin_unlock_irqrestore(&host->lock, flags); ++ } ++ ++ return isr ? IRQ_HANDLED : IRQ_NONE; ++} ++#endif ++ ++ ++ ++void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock) ++{ ++ int div = 0; /* Initialized for compiler warning */ ++ int real_div = div, clk_mul = 1; ++ u16 clk = 0; ++ unsigned long timeout; ++ unsigned int input_clock = clock; ++ ++ if (host->overclock_50 && (clock == 50000000)) ++ clock = host->overclock_50 * 1000000 + 999999; ++ ++ host->mmc->actual_clock = 0; ++ ++ bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL); ++ ++ if (clock == 0) ++ return; ++ ++ /* Version 3.00 divisors must be a multiple of 2. */ ++ if (host->max_clk <= clock) ++ div = 1; ++ else { ++ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; ++ div += 2) { ++ if ((host->max_clk / div) <= clock) ++ break; ++ } ++ } ++ ++ real_div = div; ++ div >>= 1; ++ ++ if (real_div) ++ clock = (host->max_clk * clk_mul) / real_div; ++ host->mmc->actual_clock = clock; ++ ++ if ((clock > input_clock) && (clock > host->max_overclock)) { ++ pr_warn("%s: Overclocking to %dHz\n", ++ mmc_hostname(host->mmc), clock); ++ host->max_overclock = clock; ++ } ++ ++ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; ++ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) ++ << SDHCI_DIVIDER_HI_SHIFT; ++ clk |= SDHCI_CLOCK_INT_EN; ++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ /* Wait max 20 ms */ ++ timeout = 20; ++ while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL)) ++ & SDHCI_CLOCK_INT_STABLE)) { ++ if (timeout == 0) { ++ pr_err("%s: Internal clock never " ++ "stabilised.\n", mmc_hostname(host->mmc)); ++ bcm2835_mmc_dumpregs(host); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++ ++ if (20-timeout > 10 && 20-timeout > host->max_delay) { ++ host->max_delay = 20-timeout; ++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); ++ } ++ ++ clk |= SDHCI_CLOCK_CARD_EN; ++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); ++} ++ ++static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = mmc_priv(mmc); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ WARN_ON(host->mrq != NULL); ++ ++ host->mrq = mrq; ++ ++ if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) ++ bcm2835_mmc_send_command(host, mrq->sbc); ++ else ++ bcm2835_mmc_send_command(host, mrq->cmd); ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) { ++ /* DMA transfer starts now, PIO starts after interrupt */ ++ bcm2835_mmc_transfer_dma(host); ++ } ++} ++ ++ ++static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ u8 ctrl; ++ u16 clk, ctrl_2; ++ ++ pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n", ++ ios->clock, ios->power_mode, ios->bus_width, ++ ios->timing, ios->signal_voltage, ios->drv_type); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (!ios->clock || ios->clock != host->clock) { ++ bcm2835_mmc_set_clock(host, ios->clock); ++ host->clock = ios->clock; ++ } ++ ++ if (host->pwr != SDHCI_POWER_330) { ++ host->pwr = SDHCI_POWER_330; ++ bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL); ++ } ++ ++ ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL); ++ ++ /* set bus width */ ++ ctrl &= ~SDHCI_CTRL_8BITBUS; ++ if (ios->bus_width == MMC_BUS_WIDTH_4) ++ ctrl |= SDHCI_CTRL_4BITBUS; ++ else ++ ctrl &= ~SDHCI_CTRL_4BITBUS; ++ ++ ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */ ++ ++ ++ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL); ++ /* ++ * We only need to set Driver Strength if the ++ * preset value enable is not set. ++ */ ++ ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2); ++ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; ++ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) ++ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; ++ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) ++ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; ++ ++ bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); ++ ++ /* Reset SD Clock Enable */ ++ clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL); ++ clk &= ~SDHCI_CLOCK_CARD_EN; ++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ /* Re-enable SD Clock */ ++ bcm2835_mmc_set_clock(host, host->clock); ++ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL); ++ ++ mmiowb(); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++ ++static struct mmc_host_ops bcm2835_ops = { ++ .request = bcm2835_mmc_request, ++ .set_ios = bcm2835_mmc_set_ios, ++ .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq, ++}; ++ ++ ++static void bcm2835_mmc_tasklet_finish(unsigned long param) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ struct mmc_request *mrq; ++ ++ host = (struct bcm2835_host *)param; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ /* ++ * If this tasklet gets rescheduled while running, it will ++ * be run again afterwards but without any active request. ++ */ ++ if (!host->mrq) { ++ spin_unlock_irqrestore(&host->lock, flags); ++ return; ++ } ++ ++ del_timer(&host->timer); ++ ++ mrq = host->mrq; ++ ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ if (!(host->flags & SDHCI_DEVICE_DEAD) && ++ ((mrq->cmd && mrq->cmd->error) || ++ (mrq->data && (mrq->data->error || ++ (mrq->data->stop && mrq->data->stop->error))))) { ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD); ++ bcm2835_mmc_reset(host, SDHCI_RESET_DATA); ++ spin_lock_irqsave(&host->lock, flags); ++ } ++ ++ host->mrq = NULL; ++ host->cmd = NULL; ++ host->data = NULL; ++ ++ mmiowb(); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ mmc_request_done(host->mmc, mrq); ++} ++ ++ ++ ++static int bcm2835_mmc_add_host(struct bcm2835_host *host) ++{ ++ struct mmc_host *mmc = host->mmc; ++ struct device *dev = mmc->parent; ++#ifndef FORCE_PIO ++ struct dma_slave_config cfg; ++#endif ++ int ret; ++ ++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); ++ ++ host->clk_mul = 0; ++ ++ mmc->f_max = host->max_clk; ++ mmc->f_max = host->max_clk; ++ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; ++ ++ /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ ++ host->timeout_clk = mmc->f_max / 1000; ++#ifdef CONFIG_ARCH_BCM2835 ++ mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; ++#endif ++ /* host controller capabilities */ ++ mmc->caps = MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ | ++ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; ++ ++ host->flags = SDHCI_AUTO_CMD23; ++ ++ dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2); ++#ifdef FORCE_PIO ++ dev_info(dev, "Forcing PIO mode\n"); ++ host->have_dma = false; ++#else ++ if (IS_ERR_OR_NULL(host->dma_chan_tx) || ++ IS_ERR_OR_NULL(host->dma_chan_rx)) { ++ dev_err(dev, "%s: Unable to initialise DMA channels. Falling back to PIO\n", ++ DRIVER_NAME); ++ host->have_dma = false; ++ } else { ++ dev_info(dev, "DMA channels allocated"); ++ host->have_dma = true; ++ ++ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cfg.slave_id = 11; /* DREQ channel */ ++ ++ cfg.direction = DMA_MEM_TO_DEV; ++ cfg.src_addr = 0; ++ cfg.dst_addr = host->phys_addr + SDHCI_BUFFER; ++ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); ++ ++ cfg.direction = DMA_DEV_TO_MEM; ++ cfg.src_addr = host->phys_addr + SDHCI_BUFFER; ++ cfg.dst_addr = 0; ++ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); ++ } ++#endif ++ mmc->max_segs = 128; ++ mmc->max_req_size = 524288; ++ mmc->max_seg_size = mmc->max_req_size; ++ mmc->max_blk_size = 512; ++ mmc->max_blk_count = 65535; ++ ++ /* report supported voltage ranges */ ++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ tasklet_init(&host->finish_tasklet, ++ bcm2835_mmc_tasklet_finish, (unsigned long)host); ++ ++ setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host); ++ init_waitqueue_head(&host->buf_ready_int); ++ ++ bcm2835_mmc_init(host, 0); ++#ifndef CONFIG_ARCH_BCM2835 ++ ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0, ++ mmc_hostname(mmc), host); ++#else ++ ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq, ++ bcm2835_mmc_thread_irq, IRQF_SHARED, ++ mmc_hostname(mmc), host); ++#endif ++ if (ret) { ++ dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret); ++ goto untasklet; ++ } ++ ++ mmiowb(); ++ mmc_add_host(mmc); ++ ++ return 0; ++ ++untasklet: ++ tasklet_kill(&host->finish_tasklet); ++ ++ return ret; ++} ++ ++static int bcm2835_mmc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct clk *clk; ++ struct resource *iomem; ++ struct bcm2835_host *host; ++ struct mmc_host *mmc; ++ int ret; ++ ++ mmc = mmc_alloc_host(sizeof(*host), dev); ++ if (!mmc) ++ return -ENOMEM; ++ ++ mmc->ops = &bcm2835_ops; ++ host = mmc_priv(mmc); ++ host->mmc = mmc; ++ host->timeout = msecs_to_jiffies(1000); ++ spin_lock_init(&host->lock); ++ ++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ host->ioaddr = devm_ioremap_resource(dev, iomem); ++ if (IS_ERR(host->ioaddr)) { ++ ret = PTR_ERR(host->ioaddr); ++ goto err; ++ } ++ ++ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; ++ ++#ifndef FORCE_PIO ++ if (node) { ++ host->dma_chan_tx = dma_request_slave_channel(dev, "tx"); ++ host->dma_chan_rx = dma_request_slave_channel(dev, "rx"); ++ } else { ++ dma_cap_mask_t mask; ++ ++ dma_cap_zero(mask); ++ /* we don't care about the channel, any would work */ ++ dma_cap_set(DMA_SLAVE, mask); ++ host->dma_chan_tx = dma_request_channel(mask, NULL, NULL); ++ host->dma_chan_rx = dma_request_channel(mask, NULL, NULL); ++ } ++#endif ++ clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(dev, "could not get clk\n"); ++ ret = PTR_ERR(clk); ++ goto err; ++ } ++ ++ host->max_clk = clk_get_rate(clk); ++ ++ host->irq = platform_get_irq(pdev, 0); ++ if (host->irq <= 0) { ++ dev_err(dev, "get IRQ failed\n"); ++ ret = -EINVAL; ++ goto err; ++ } ++ ++ if (node) { ++ mmc_of_parse(mmc); ++ ++ /* Read any custom properties */ ++ of_property_read_u32(node, ++ "brcm,overclock-50", ++ &host->overclock_50); ++ } else { ++ mmc->caps |= MMC_CAP_4_BIT_DATA; ++ } ++ ++ ret = bcm2835_mmc_add_host(host); ++ if (ret) ++ goto err; ++ ++ platform_set_drvdata(pdev, host); ++ ++ return 0; ++err: ++ mmc_free_host(mmc); ++ ++ return ret; ++} ++ ++static int bcm2835_mmc_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_host *host = platform_get_drvdata(pdev); ++ unsigned long flags; ++ int dead; ++ u32 scratch; ++ ++ dead = 0; ++ scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); ++ if (scratch == (u32)-1) ++ dead = 1; ++ ++ ++ if (dead) { ++ spin_lock_irqsave(&host->lock, flags); ++ ++ host->flags |= SDHCI_DEVICE_DEAD; ++ ++ if (host->mrq) { ++ pr_err("%s: Controller removed during " ++ " transfer!\n", mmc_hostname(host->mmc)); ++ ++ host->mrq->cmd->error = -ENOMEDIUM; ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ } ++ ++ mmc_remove_host(host->mmc); ++ ++ if (!dead) ++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); ++ ++ free_irq(host->irq, host); ++ ++ del_timer_sync(&host->timer); ++ ++ tasklet_kill(&host->finish_tasklet); ++ ++ mmc_free_host(host->mmc); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++ ++static const struct of_device_id bcm2835_mmc_match[] = { ++ { .compatible = "brcm,bcm2835-mmc" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_mmc_match); ++ ++ ++ ++static struct platform_driver bcm2835_mmc_driver = { ++ .probe = bcm2835_mmc_probe, ++ .remove = bcm2835_mmc_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_mmc_match, ++ }, ++}; ++module_platform_driver(bcm2835_mmc_driver); ++ ++module_param(mmc_debug, uint, 0644); ++module_param(mmc_debug2, uint, 0644); ++MODULE_ALIAS("platform:mmc-bcm2835"); ++MODULE_DESCRIPTION("BCM2835 SDHCI driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Gellert Weisz"); diff --git a/target/linux/brcm2708/patches-4.1/0009-Adding-bcm2835-sdhost-driver-and-an-overlay-to-enabl.patch b/target/linux/brcm2708/patches-4.1/0009-Adding-bcm2835-sdhost-driver-and-an-overlay-to-enabl.patch new file mode 100644 index 0000000..ce6d4f4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0009-Adding-bcm2835-sdhost-driver-and-an-overlay-to-enabl.patch @@ -0,0 +1,1765 @@ +From 8086ce054d96d5a9a2237e5bb1d270dbce759189 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 25 Mar 2015 17:49:47 +0000 +Subject: [PATCH 009/203] Adding bcm2835-sdhost driver, and an overlay to + enable it + +BCM2835 has two SD card interfaces. This driver uses the other one. + +bcm2835-sdhost: Error handling fix, and code clarification + +bcm2835-sdhost: Adding overclocking option + +Allow a different clock speed to be substitued for a requested 50MHz. +This option is exposed using the "overclock_50" DT parameter. +Note that the sdhost interface is restricted to integer divisions of +core_freq, and the highest sensible option for a core_freq of 250MHz +is 84 (250/3 = 83.3MHz), the next being 125 (250/2) which is much too +high. + +Use at your own risk. + +bcm2835-sdhost: Round up the overclock, so 62 works for 62.5Mhz + +Also only warn once for each overclock setting. +--- + drivers/mmc/host/Kconfig | 10 + + drivers/mmc/host/Makefile | 1 + + drivers/mmc/host/bcm2835-sdhost.c | 1702 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 1713 insertions(+) + create mode 100644 drivers/mmc/host/bcm2835-sdhost.c + +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -33,6 +33,16 @@ config MMC_BCM2835_PIO_DMA_BARRIER + + If unsure, say 2 here. + ++config MMC_BCM2835_SDHOST ++ tristate "Support for the SDHost controller on BCM2708/9" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ help ++ This selects the SDHost controller on BCM2835/6. ++ ++ If you have a controller with this interface, say Y or M here. ++ ++ If unsure, say N. ++ + config MMC_ARMMMCI + tristate "ARM AMBA Multimedia Card Interface support" + depends on ARM_AMBA +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c + obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o + obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o + obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o ++obj-$(CONFIG_MMC_BCM2835_SDHOST) += bcm2835-sdhost.o + obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o + obj-$(CONFIG_MMC_WBSD) += wbsd.o + obj-$(CONFIG_MMC_AU1X) += au1xmmc.o +--- /dev/null ++++ b/drivers/mmc/host/bcm2835-sdhost.c +@@ -0,0 +1,1702 @@ ++/* ++ * BCM2835 SD host driver. ++ * ++ * Author: Phil Elwell ++ * Copyright 2015 ++ * ++ * Based on ++ * mmc-bcm2835.c by Gellert Weisz ++ * which is, in turn, based on ++ * sdhci-bcm2708.c by Broadcom ++ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko ++ * sdhci.c and sdhci-pci.c by Pierre Ossman ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#define SAFE_READ_THRESHOLD 4 ++#define SAFE_WRITE_THRESHOLD 4 ++#define ALLOW_DMA 1 ++#define ALLOW_CMD23 0 ++#define ALLOW_FAST 1 ++#define USE_BLOCK_IRQ 1 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "sdhost-bcm2835" ++ ++#define SDCMD 0x00 /* Command to SD card - 16 R/W */ ++#define SDARG 0x04 /* Argument to SD card - 32 R/W */ ++#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ ++#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ ++#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ ++#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ ++#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ ++#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ ++#define SDHSTS 0x20 /* SD host status - 11 R */ ++#define SDVDD 0x30 /* SD card power control - 1 R/W */ ++#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ ++#define SDHCFG 0x38 /* Host configuration - 2 R/W */ ++#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ ++#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ ++#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ ++ ++#define SDCMD_NEW_FLAG 0x8000 ++#define SDCMD_FAIL_FLAG 0x4000 ++#define SDCMD_BUSYWAIT 0x800 ++#define SDCMD_NO_RESPONSE 0x400 ++#define SDCMD_LONG_RESPONSE 0x200 ++#define SDCMD_WRITE_CMD 0x80 ++#define SDCMD_READ_CMD 0x40 ++#define SDCMD_CMD_MASK 0x3f ++ ++#define SDCDIV_MAX_CDIV 0x7ff ++ ++#define SDHSTS_BUSY_IRPT 0x400 ++#define SDHSTS_BLOCK_IRPT 0x200 ++#define SDHSTS_SDIO_IRPT 0x100 ++#define SDHSTS_REW_TIME_OUT 0x80 ++#define SDHSTS_CMD_TIME_OUT 0x40 ++#define SDHSTS_CRC16_ERROR 0x20 ++#define SDHSTS_CRC7_ERROR 0x10 ++#define SDHSTS_FIFO_ERROR 0x08 ++/* Reserved */ ++/* Reserved */ ++#define SDHSTS_DATA_FLAG 0x01 ++ ++#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR) ++#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK) ++/* SDHSTS_CRC7_ERROR - ignore this as MMC cards generate this spuriously */ ++ ++#define SDHCFG_BUSY_IRPT_EN (1<<10) ++#define SDHCFG_BLOCK_IRPT_EN (1<<8) ++#define SDHCFG_SDIO_IRPT_EN (1<<5) ++#define SDHCFG_DATA_IRPT_EN (1<<4) ++#define SDHCFG_SLOW_CARD (1<<3) ++#define SDHCFG_WIDE_EXT_BUS (1<<2) ++#define SDHCFG_WIDE_INT_BUS (1<<1) ++#define SDHCFG_REL_CMD_LINE (1<<0) ++ ++#define SDEDM_FORCE_DATA_MODE (1<<19) ++#define SDEDM_CLOCK_PULSE (1<<20) ++#define SDEDM_BYPASS (1<<21) ++ ++#define SDEDM_WRITE_THRESHOLD_SHIFT 9 ++#define SDEDM_READ_THRESHOLD_SHIFT 14 ++#define SDEDM_THRESHOLD_MASK 0x1f ++ ++/* the inclusive limit in bytes under which PIO will be used instead of DMA */ ++#ifdef CONFIG_MMC_BCM2835_SDHOST_PIO_DMA_BARRIER ++#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_SDHOST_PIO_DMA_BARRIER ++#else ++#define PIO_DMA_BARRIER 0 ++#endif ++ ++#define MIN_FREQ 400000 ++#define TIMEOUT_VAL 0xE ++#define BCM2835_SDHOST_WRITE_DELAY(f) (((2 * 1000000) / f) + 1) ++ ++#ifndef BCM2708_PERI_BASE ++ #define BCM2708_PERI_BASE 0x20000000 ++#endif ++ ++/* FIXME: Needs IOMMU support */ ++#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) ++ ++ ++struct bcm2835_host { ++ spinlock_t lock; ++ ++ void __iomem *ioaddr; ++ u32 phys_addr; ++ ++ struct mmc_host *mmc; ++ ++ u32 timeout; ++ ++ int clock; /* Current clock speed */ ++ ++ bool slow_card; /* Force 11-bit divisor */ ++ ++ unsigned int max_clk; /* Max possible freq */ ++ unsigned int timeout_clk; /* Timeout freq (KHz) */ ++ ++ struct tasklet_struct finish_tasklet; /* Tasklet structures */ ++ ++ struct timer_list timer; /* Timer for timeouts */ ++ ++ struct sg_mapping_iter sg_miter; /* SG state for PIO */ ++ unsigned int blocks; /* remaining PIO blocks */ ++ ++ int irq; /* Device IRQ */ ++ ++ ++ /* cached registers */ ++ u32 hcfg; ++ u32 cdiv; ++ ++ struct mmc_request *mrq; /* Current request */ ++ struct mmc_command *cmd; /* Current command */ ++ struct mmc_data *data; /* Current data request */ ++ unsigned int data_complete:1; /* Data finished before cmd */ ++ ++ unsigned int flush_fifo:1; /* Drain the fifo when finishing */ ++ ++ unsigned int use_busy:1; /* Wait for busy interrupt */ ++ ++ u32 thread_isr; ++ ++ /*DMA part*/ ++ struct dma_chan *dma_chan_rx; /* DMA channel for reads */ ++ struct dma_chan *dma_chan_tx; /* DMA channel for writes */ ++ ++ bool allow_dma; ++ bool have_dma; ++ bool use_dma; ++ /*end of DMA part*/ ++ ++ int max_delay; /* maximum length of time spent waiting */ ++ struct timeval stop_time; /* when the last stop was issued */ ++ u32 delay_after_stop; /* minimum time between stop and subsequent data transfer */ ++ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */ ++ u32 max_overclock; /* Highest reported */ ++}; ++ ++ ++static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg) ++{ ++ writel(val, host->ioaddr + reg); ++} ++ ++static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg) ++{ ++ return readl(host->ioaddr + reg); ++} ++ ++static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg) ++{ ++ return readl_relaxed(host->ioaddr + reg); ++} ++ ++static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host) ++{ ++ pr_info(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", ++ mmc_hostname(host->mmc)); ++ ++ pr_info(DRIVER_NAME ": SDCMD 0x%08x\n", ++ bcm2835_sdhost_read(host, SDCMD)); ++ pr_info(DRIVER_NAME ": SDARG 0x%08x\n", ++ bcm2835_sdhost_read(host, SDARG)); ++ pr_info(DRIVER_NAME ": SDTOUT 0x%08x\n", ++ bcm2835_sdhost_read(host, SDTOUT)); ++ pr_info(DRIVER_NAME ": SDCDIV 0x%08x\n", ++ bcm2835_sdhost_read(host, SDCDIV)); ++ pr_info(DRIVER_NAME ": SDRSP0 0x%08x\n", ++ bcm2835_sdhost_read(host, SDRSP0)); ++ pr_info(DRIVER_NAME ": SDRSP1 0x%08x\n", ++ bcm2835_sdhost_read(host, SDRSP1)); ++ pr_info(DRIVER_NAME ": SDRSP2 0x%08x\n", ++ bcm2835_sdhost_read(host, SDRSP2)); ++ pr_info(DRIVER_NAME ": SDRSP3 0x%08x\n", ++ bcm2835_sdhost_read(host, SDRSP3)); ++ pr_info(DRIVER_NAME ": SDHSTS 0x%08x\n", ++ bcm2835_sdhost_read(host, SDHSTS)); ++ pr_info(DRIVER_NAME ": SDVDD 0x%08x\n", ++ bcm2835_sdhost_read(host, SDVDD)); ++ pr_info(DRIVER_NAME ": SDEDM 0x%08x\n", ++ bcm2835_sdhost_read(host, SDEDM)); ++ pr_info(DRIVER_NAME ": SDHCFG 0x%08x\n", ++ bcm2835_sdhost_read(host, SDHCFG)); ++ pr_info(DRIVER_NAME ": SDHBCT 0x%08x\n", ++ bcm2835_sdhost_read(host, SDHBCT)); ++ pr_info(DRIVER_NAME ": SDHBLC 0x%08x\n", ++ bcm2835_sdhost_read(host, SDHBLC)); ++ ++ pr_debug(DRIVER_NAME ": ===========================================\n"); ++} ++ ++ ++static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on) ++{ ++ bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD); ++} ++ ++ ++static void bcm2835_sdhost_reset(struct bcm2835_host *host) ++{ ++ u32 temp; ++ ++ pr_debug("bcm2835_sdhost_reset\n"); ++ ++ bcm2835_sdhost_set_power(host, false); ++ ++ bcm2835_sdhost_write(host, 0, SDCMD); ++ bcm2835_sdhost_write(host, 0, SDARG); ++ bcm2835_sdhost_write(host, 0xf00000, SDTOUT); ++ bcm2835_sdhost_write(host, 0, SDCDIV); ++ bcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */ ++ bcm2835_sdhost_write(host, 0, SDHCFG); ++ bcm2835_sdhost_write(host, 0, SDHBCT); ++ bcm2835_sdhost_write(host, 0, SDHBLC); ++ ++ /* Limit fifo usage due to silicon bug */ ++ temp = bcm2835_sdhost_read(host, SDEDM); ++ temp &= ~((SDEDM_THRESHOLD_MASK<clock = 0; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); ++ mmiowb(); ++} ++ ++static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); ++ ++static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft) ++{ ++ pr_debug("bcm2835_sdhost_init(%d)\n", soft); ++ ++ /* Set interrupt enables */ ++ host->hcfg = SDHCFG_BUSY_IRPT_EN; ++ ++ bcm2835_sdhost_reset(host); ++ ++ if (soft) { ++ /* force clock reconfiguration */ ++ host->clock = 0; ++ bcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios); ++ } ++} ++ ++static bool bcm2835_sdhost_is_write_complete(struct bcm2835_host *host) ++{ ++ bool write_complete = ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1); ++ ++ if (!write_complete) { ++ /* Request an IRQ for the last block */ ++ host->hcfg |= SDHCFG_BLOCK_IRPT_EN; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ if ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1) { ++ /* The write has now completed. Disable the interrupt ++ and clear the status flag */ ++ host->hcfg &= ~SDHCFG_BLOCK_IRPT_EN; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ bcm2835_sdhost_write(host, SDHSTS_BLOCK_IRPT, SDHSTS); ++ write_complete = true; ++ } ++ } ++ ++ return write_complete; ++} ++ ++static void bcm2835_sdhost_wait_write_complete(struct bcm2835_host *host) ++{ ++ int timediff; ++#ifdef DEBUG ++ static struct timeval start_time; ++ static int max_stall_time = 0; ++ static int total_stall_time = 0; ++ struct timeval before, after; ++ ++ do_gettimeofday(&before); ++ if (max_stall_time == 0) ++ start_time = before; ++#endif ++ ++ timediff = 0; ++ ++ while (1) { ++ u32 edm = bcm2835_sdhost_read(host, SDEDM); ++ if ((edm & 0xf) == 1) ++ break; ++ timediff++; ++ if (timediff > 5000000) { ++#ifdef DEBUG ++ do_gettimeofday(&after); ++ timediff = (after.tv_sec - before.tv_sec)*1000000 + ++ (after.tv_usec - before.tv_usec); ++ ++ pr_err(" wait_write_complete - still waiting after %dus\n", ++ timediff); ++#else ++ pr_err(" wait_write_complete - still waiting after %d retries\n", ++ timediff); ++#endif ++ bcm2835_sdhost_dumpregs(host); ++ host->data->error = -ETIMEDOUT; ++ return; ++ } ++ } ++ ++#ifdef DEBUG ++ do_gettimeofday(&after); ++ timediff = (after.tv_sec - before.tv_sec)*1000000 + (after.tv_usec - before.tv_usec); ++ ++ total_stall_time += timediff; ++ if (timediff > max_stall_time) ++ max_stall_time = timediff; ++ ++ if ((after.tv_sec - start_time.tv_sec) > 10) { ++ pr_debug(" wait_write_complete - max wait %dus, total %dus\n", ++ max_stall_time, total_stall_time); ++ start_time = after; ++ max_stall_time = 0; ++ total_stall_time = 0; ++ } ++#endif ++} ++ ++static void bcm2835_sdhost_finish_data(struct bcm2835_host *host); ++ ++static void bcm2835_sdhost_dma_complete(void *param) ++{ ++ struct bcm2835_host *host = param; ++ struct dma_chan *dma_chan; ++ unsigned long flags; ++ u32 dir_data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->data) { ++ bool write_complete; ++ if (USE_BLOCK_IRQ) ++ write_complete = bcm2835_sdhost_is_write_complete(host); ++ else { ++ bcm2835_sdhost_wait_write_complete(host); ++ write_complete = true; ++ } ++ pr_debug("dma_complete() - write_complete=%d\n", ++ write_complete); ++ ++ if (write_complete || (host->data->flags & MMC_DATA_READ)) ++ { ++ if (write_complete) { ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ } else { ++ dma_chan = host->dma_chan_rx; ++ dir_data = DMA_FROM_DEVICE; ++ } ++ ++ dma_unmap_sg(dma_chan->device->dev, ++ host->data->sg, host->data->sg_len, ++ dir_data); ++ ++ bcm2835_sdhost_finish_data(host); ++ } ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host) ++{ ++ unsigned long flags; ++ size_t blksize, len; ++ u32 *buf; ++ ++ blksize = host->data->blksz; ++ ++ local_irq_save(flags); ++ ++ while (blksize) { ++ if (!sg_miter_next(&host->sg_miter)) ++ BUG(); ++ ++ len = min(host->sg_miter.length, blksize); ++ BUG_ON(len % 4); ++ ++ blksize -= len; ++ host->sg_miter.consumed = len; ++ ++ buf = (u32 *)host->sg_miter.addr; ++ ++ while (len) { ++ while (1) { ++ u32 hsts; ++ hsts = bcm2835_sdhost_read(host, SDHSTS); ++ if (hsts & SDHSTS_DATA_FLAG) ++ break; ++ ++ if (hsts & SDHSTS_ERROR_MASK) { ++ pr_err("%s: Transfer error - HSTS %x, HBCT %x - %x left\n", ++ mmc_hostname(host->mmc), ++ hsts, ++ bcm2835_sdhost_read(host, SDHBCT), ++ blksize + len); ++ if (hsts & SDHSTS_REW_TIME_OUT) ++ host->data->error = -ETIMEDOUT; ++ else if (hsts & (SDHSTS_CRC16_ERROR || ++ SDHSTS_CRC7_ERROR)) ++ host->data->error = -EILSEQ; ++ else { ++ pr_err("%s: unexpected data error\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ host->cmd->error = -EIO; ++ } ++ } ++ } ++ ++ *(buf++) = bcm2835_sdhost_read(host, SDDATA); ++ len -= 4; ++ } ++ } ++ ++ sg_miter_stop(&host->sg_miter); ++ ++ local_irq_restore(flags); ++} ++ ++static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host) ++{ ++ unsigned long flags; ++ size_t blksize, len; ++ u32 *buf; ++ ++ blksize = host->data->blksz; ++ ++ local_irq_save(flags); ++ ++ while (blksize) { ++ if (!sg_miter_next(&host->sg_miter)) ++ BUG(); ++ ++ len = min(host->sg_miter.length, blksize); ++ BUG_ON(len % 4); ++ ++ blksize -= len; ++ host->sg_miter.consumed = len; ++ ++ buf = host->sg_miter.addr; ++ ++ while (len) { ++ while (!(bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG)) ++ continue; ++ bcm2835_sdhost_write(host, *(buf++), SDDATA); ++ len -= 4; ++ } ++ } ++ ++ sg_miter_stop(&host->sg_miter); ++ ++ local_irq_restore(flags); ++} ++ ++ ++static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host) ++{ ++ BUG_ON(!host->data); ++ ++ if (host->data->flags & MMC_DATA_READ) ++ bcm2835_sdhost_read_block_pio(host); ++ else ++ bcm2835_sdhost_write_block_pio(host); ++} ++ ++ ++static void bcm2835_sdhost_transfer_dma(struct bcm2835_host *host) ++{ ++ u32 len, dir_data, dir_slave; ++ struct dma_async_tx_descriptor *desc = NULL; ++ struct dma_chan *dma_chan; ++ ++ pr_debug("bcm2835_sdhost_transfer_dma()\n"); ++ ++ WARN_ON(!host->data); ++ ++ if (!host->data) ++ return; ++ ++ if (host->data->flags & MMC_DATA_READ) { ++ dma_chan = host->dma_chan_rx; ++ dir_data = DMA_FROM_DEVICE; ++ dir_slave = DMA_DEV_TO_MEM; ++ } else { ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ dir_slave = DMA_MEM_TO_DEV; ++ } ++ ++ BUG_ON(!dma_chan->device); ++ BUG_ON(!dma_chan->device->dev); ++ BUG_ON(!host->data->sg); ++ ++ len = dma_map_sg(dma_chan->device->dev, host->data->sg, ++ host->data->sg_len, dir_data); ++ if (len > 0) { ++ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg, ++ len, dir_slave, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ } else { ++ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); ++ } ++ if (desc) { ++ desc->callback = bcm2835_sdhost_dma_complete; ++ desc->callback_param = host; ++ dmaengine_submit(desc); ++ dma_async_issue_pending(dma_chan); ++ } ++ ++} ++ ++ ++static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host) ++{ ++ u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | ++ SDHCFG_BUSY_IRPT_EN; ++ if (host->use_dma) ++ host->hcfg = (host->hcfg & ~all_irqs) | ++ SDHCFG_BUSY_IRPT_EN; ++ else ++ host->hcfg = (host->hcfg & ~all_irqs) | ++ SDHCFG_DATA_IRPT_EN | ++ SDHCFG_BUSY_IRPT_EN; ++ ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++} ++ ++ ++static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) ++{ ++ struct mmc_data *data = cmd->data; ++ ++ WARN_ON(host->data); ++ ++ if (!data) ++ return; ++ ++ /* Sanity checks */ ++ BUG_ON(data->blksz * data->blocks > 524288); ++ BUG_ON(data->blksz > host->mmc->max_blk_size); ++ BUG_ON(data->blocks > 65535); ++ ++ host->data = data; ++ host->data_complete = 0; ++ host->flush_fifo = 0; ++ host->data->bytes_xfered = 0; ++ ++ if (!host->use_dma) { ++ int flags; ++ ++ flags = SG_MITER_ATOMIC; ++ if (data->flags & MMC_DATA_READ) ++ flags |= SG_MITER_TO_SG; ++ else ++ flags |= SG_MITER_FROM_SG; ++ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); ++ host->blocks = data->blocks; ++ } ++ ++ host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER; ++ ++ bcm2835_sdhost_set_transfer_irqs(host); ++ ++ bcm2835_sdhost_write(host, data->blksz, SDHBCT); ++ if (host->use_dma) ++ bcm2835_sdhost_write(host, data->blocks, SDHBLC); ++ ++ BUG_ON(!host->data); ++} ++ ++ ++void bcm2835_sdhost_send_command(struct bcm2835_host *host, struct mmc_command *cmd) ++{ ++ u32 sdcmd; ++ unsigned long timeout; ++ ++ WARN_ON(host->cmd); ++ ++ if (1) { ++ pr_debug("bcm2835_sdhost_send_command: %08x %08x (flags %x)\n", ++ cmd->opcode, cmd->arg, (cmd->flags & 0xff) | (cmd->data ? cmd->data->flags : 0)); ++ if (cmd->data) ++ pr_debug("bcm2835_sdhost_send_command: %s %d*%x\n", ++ (cmd->data->flags & MMC_DATA_READ) ? ++ "read" : "write", cmd->data->blocks, ++ cmd->data->blksz); ++ } ++ ++ /* Wait max 10 ms */ ++ timeout = 1000; ++ ++ while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) { ++ if (timeout == 0) { ++ pr_err("%s: Previous command never completed.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ timeout--; ++ udelay(10); ++ } ++ ++ if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) { ++ host->max_delay = (1000-timeout)/100; ++ pr_warning("Warning: SDHost controller hung for %d ms\n", host->max_delay); ++ } ++ ++ timeout = jiffies; ++#ifdef CONFIG_ARCH_BCM2835 ++ if (!cmd->data && cmd->busy_timeout > 9000) ++ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; ++ else ++#endif ++ timeout += 10 * HZ; ++ mod_timer(&host->timer, timeout); ++ ++ host->cmd = cmd; ++ ++ bcm2835_sdhost_prepare_data(host, cmd); ++ ++ bcm2835_sdhost_write(host, cmd->arg, SDARG); ++ ++ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { ++ pr_err("%s: Unsupported response type!\n", ++ mmc_hostname(host->mmc)); ++ cmd->error = -EINVAL; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ sdcmd = cmd->opcode & SDCMD_CMD_MASK; ++ ++ if (!(cmd->flags & MMC_RSP_PRESENT)) ++ sdcmd |= SDCMD_NO_RESPONSE; ++ else { ++ if (cmd->flags & MMC_RSP_136) ++ sdcmd |= SDCMD_LONG_RESPONSE; ++ if (cmd->flags & MMC_RSP_BUSY) { ++ sdcmd |= SDCMD_BUSYWAIT; ++ host->use_busy = 1; ++ } ++ } ++ ++ if (cmd->data) { ++ if (host->delay_after_stop) { ++ struct timeval now; ++ int time_since_stop; ++ do_gettimeofday(&now); ++ time_since_stop = (now.tv_sec - host->stop_time.tv_sec); ++ if (time_since_stop < 2) { ++ /* Possibly less than one second */ ++ time_since_stop = time_since_stop * 1000000 + ++ (now.tv_usec - host->stop_time.tv_usec); ++ if (time_since_stop < host->delay_after_stop) ++ udelay(host->delay_after_stop - ++ time_since_stop); ++ } ++ } ++ ++ if (cmd->data->flags & MMC_DATA_WRITE) ++ sdcmd |= SDCMD_WRITE_CMD; ++ if (cmd->data->flags & MMC_DATA_READ) ++ sdcmd |= SDCMD_READ_CMD; ++ } ++ ++ bcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD); ++} ++ ++ ++static void bcm2835_sdhost_finish_command(struct bcm2835_host *host); ++static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host); ++ ++static void bcm2835_sdhost_finish_data(struct bcm2835_host *host) ++{ ++ struct mmc_data *data; ++ ++ data = host->data; ++ BUG_ON(!data); ++ ++ pr_debug("finish_data(error %d, stop %d, sbc %d)\n", ++ data->error, data->stop ? 1 : 0, ++ host->mrq->sbc ? 1 : 0); ++ ++ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ ++ if (data->error) { ++ data->bytes_xfered = 0; ++ } else ++ data->bytes_xfered = data->blksz * data->blocks; ++ ++ host->data_complete = 1; ++ ++ if (host->cmd) { ++ /* ++ * Data managed to finish before the ++ * command completed. Make sure we do ++ * things in the proper order. ++ */ ++ pr_debug("Finished early - HSTS %x\n", ++ bcm2835_sdhost_read(host, SDHSTS)); ++ } ++ else ++ bcm2835_sdhost_transfer_complete(host); ++} ++ ++ ++static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host) ++{ ++ struct mmc_data *data; ++ ++ BUG_ON(host->cmd); ++ BUG_ON(!host->data); ++ BUG_ON(!host->data_complete); ++ ++ data = host->data; ++ host->data = NULL; ++ ++ pr_debug("transfer_complete(error %d, stop %d)\n", ++ data->error, data->stop ? 1 : 0); ++ ++ if (data->error) ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ bcm2835_sdhost_reset(host); ++ ++ /* ++ * Need to send CMD12 if - ++ * a) open-ended multiblock transfer (no CMD23) ++ * b) error in multiblock transfer ++ */ ++ if (data->stop && ++ (data->error || ++ !host->mrq->sbc)) { ++ host->flush_fifo = 1; ++ bcm2835_sdhost_send_command(host, data->stop); ++ if (host->delay_after_stop) ++ do_gettimeofday(&host->stop_time); ++ if (!host->use_busy) ++ bcm2835_sdhost_finish_command(host); ++ } else { ++ tasklet_schedule(&host->finish_tasklet); ++ } ++} ++ ++static void bcm2835_sdhost_finish_command(struct bcm2835_host *host) ++{ ++ u32 sdcmd; ++ int timeout = 1000; ++#ifdef DEBUG ++ struct timeval before, after; ++ int timediff = 0; ++#endif ++ ++ pr_debug("finish_command(%x)\n", bcm2835_sdhost_read(host, SDCMD)); ++ ++ BUG_ON(!host->cmd || !host->mrq); ++ ++#ifdef DEBUG ++ do_gettimeofday(&before); ++#endif ++ for (sdcmd = bcm2835_sdhost_read(host, SDCMD); ++ (sdcmd & SDCMD_NEW_FLAG) && timeout; ++ timeout--) { ++ if (host->flush_fifo) { ++ while (bcm2835_sdhost_read(host, SDHSTS) & ++ SDHSTS_DATA_FLAG) ++ (void)bcm2835_sdhost_read(host, SDDATA); ++ } ++ udelay(10); ++ sdcmd = bcm2835_sdhost_read(host, SDCMD); ++ } ++#ifdef DEBUG ++ do_gettimeofday(&after); ++ timediff = (after.tv_sec - before.tv_sec)*1000000 + ++ (after.tv_usec - before.tv_usec); ++ ++ pr_debug(" finish_command - waited %dus\n", timediff); ++#endif ++ ++ if (timeout == 0) { ++ pr_err("%s: Command never completed.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ host->cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ if (host->flush_fifo) { ++ for (timeout = 100; ++ (bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG) && timeout; ++ timeout--) { ++ (void)bcm2835_sdhost_read(host, SDDATA); ++ } ++ host->flush_fifo = 0; ++ if (timeout == 0) { ++ pr_err("%s: FIFO never drained.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ host->cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ } ++ ++ /* Check for errors */ ++ if (sdcmd & SDCMD_FAIL_FLAG) ++ { ++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ ++ pr_debug("%s: error detected - CMD %x, HSTS %03x, EDM %x\n", ++ mmc_hostname(host->mmc), sdcmd, sdhsts, ++ bcm2835_sdhost_read(host, SDEDM)); ++ ++ if (sdhsts & SDHSTS_CMD_TIME_OUT) ++ host->cmd->error = -ETIMEDOUT; ++ else ++ { ++ pr_err("%s: unexpected command error\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ host->cmd->error = -EIO; ++ } ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ if (host->cmd->flags & MMC_RSP_PRESENT) { ++ if (host->cmd->flags & MMC_RSP_136) { ++ int i; ++ for (i = 0; i < 4; i++) ++ host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4); ++ pr_debug("bcm2835_sdhost_finish_command: %08x %08x %08x %08x\n", ++ host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]); ++ } else { ++ host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0); ++ pr_debug("bcm2835_sdhost_finish_command: %08x\n", ++ host->cmd->resp[0]); ++ } ++ } ++ ++ host->cmd->error = 0; ++ ++ if (host->cmd == host->mrq->sbc) { ++ /* Finished CMD23, now send actual command. */ ++ host->cmd = NULL; ++ bcm2835_sdhost_send_command(host, host->mrq->cmd); ++ ++ if (host->cmd->data && host->use_dma) ++ /* DMA transfer starts now, PIO starts after irq */ ++ bcm2835_sdhost_transfer_dma(host); ++ ++ if (!host->use_busy) ++ bcm2835_sdhost_finish_command(host); ++ } else if (host->cmd == host->mrq->stop) ++ /* Finished CMD12 */ ++ tasklet_schedule(&host->finish_tasklet); ++ else { ++ /* Processed actual command. */ ++ host->cmd = NULL; ++ if (!host->data) ++ tasklet_schedule(&host->finish_tasklet); ++ else if (host->data_complete) ++ bcm2835_sdhost_transfer_complete(host); ++ } ++} ++ ++static void bcm2835_sdhost_timeout_timer(unsigned long data) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = (struct bcm2835_host *)data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->mrq) { ++ pr_err("%s: Timeout waiting for hardware interrupt.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ ++ if (host->data) { ++ host->data->error = -ETIMEDOUT; ++ bcm2835_sdhost_finish_data(host); ++ } else { ++ if (host->cmd) ++ host->cmd->error = -ETIMEDOUT; ++ else ++ host->mrq->cmd->error = -ETIMEDOUT; ++ ++ pr_debug("timeout_timer tasklet_schedule\n"); ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ } ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_sdhost_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable) ++{ ++ if (enable) ++ host->hcfg |= SDHCFG_SDIO_IRPT_EN; ++ else ++ host->hcfg &= ~SDHCFG_SDIO_IRPT_EN; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ mmiowb(); ++} ++ ++static void bcm2835_sdhost_enable_sdio_irq(struct mmc_host *mmc, int enable) ++{ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ pr_debug("bcm2835_sdhost_enable_sdio_irq(%d)\n", enable); ++ spin_lock_irqsave(&host->lock, flags); ++ bcm2835_sdhost_enable_sdio_irq_nolock(host, enable); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static u32 bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR | ++ SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR); ++ ++ if (!host->cmd) { ++ pr_err("%s: Got command busy interrupt 0x%08x even " ++ "though no command operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_sdhost_dumpregs(host); ++ return 0; ++ } ++ ++ if (!host->use_busy) { ++ pr_err("%s: Got command busy interrupt 0x%08x even " ++ "though not expecting one.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_sdhost_dumpregs(host); ++ return 0; ++ } ++ host->use_busy = 0; ++ ++ if (intmask & SDHSTS_CMD_TIME_OUT) ++ host->cmd->error = -ETIMEDOUT; ++ else if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR | ++ SDHSTS_FIFO_ERROR)) ++ host->cmd->error = -EILSEQ; ++ ++ if (host->cmd->error) ++ tasklet_schedule(&host->finish_tasklet); ++ else ++ bcm2835_sdhost_finish_command(host); ++ ++ return handled; ++} ++ ++static u32 bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR | ++ SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR); ++ ++ /* There are no dedicated data/space available interrupt ++ status bits, so it is necessary to use the single shared ++ data/space available FIFO status bits. It is therefore not ++ an error to get here when there is no data transfer in ++ progress. */ ++ if (!host->data) ++ return 0; ++ ++ // XXX FIFO_ERROR ++ if (intmask & SDHSTS_CMD_TIME_OUT) ++ host->cmd->error = -ETIMEDOUT; ++ else if ((intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR)) && ++ ((bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK) ++ != MMC_BUS_TEST_R)) ++ host->cmd->error = -EILSEQ; ++ ++ /* Use the block interrupt for writes after the first block */ ++ if (host->data->flags & MMC_DATA_WRITE) { ++ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); ++ host->hcfg |= SDHCFG_BLOCK_IRPT_EN; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ if (host->data->error) ++ bcm2835_sdhost_finish_data(host); ++ else ++ bcm2835_sdhost_transfer_pio(host); ++ } else { ++ if (!host->data->error) { ++ bcm2835_sdhost_transfer_pio(host); ++ host->blocks--; ++ } ++ if ((host->blocks == 0) || host->data->error) ++ bcm2835_sdhost_finish_data(host); ++ } ++ ++ return handled; ++} ++ ++static u32 bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ struct dma_chan *dma_chan; ++ u32 dir_data; ++ const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR | ++ SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR); ++ ++ if (!host->data) { ++ pr_err("%s: Got block interrupt 0x%08x even " ++ "though no data operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_sdhost_dumpregs(host); ++ return handled; ++ } ++ ++ if (intmask & SDHSTS_CMD_TIME_OUT) ++ host->cmd->error = -ETIMEDOUT; ++ else if ((intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR)) && ++ ((bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK) ++ != MMC_BUS_TEST_R)) ++ host->cmd->error = -EILSEQ; ++ ++ if (!host->use_dma) { ++ BUG_ON(!host->blocks); ++ host->blocks--; ++ if ((host->blocks == 0) || host->data->error) ++ bcm2835_sdhost_finish_data(host); ++ else ++ bcm2835_sdhost_transfer_pio(host); ++ } else if (host->data->flags & MMC_DATA_WRITE) { ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ dma_unmap_sg(dma_chan->device->dev, ++ host->data->sg, host->data->sg_len, ++ dir_data); ++ ++ bcm2835_sdhost_finish_data(host); ++ } ++ ++ return handled; ++} ++ ++ ++static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id) ++{ ++ irqreturn_t result = IRQ_NONE; ++ struct bcm2835_host *host = dev_id; ++ u32 unexpected = 0, early = 0; ++ int loops = 0; ++#ifndef CONFIG_ARCH_BCM2835 ++ int cardint = 0; ++#endif ++ spin_lock(&host->lock); ++ ++ for (loops = 0; loops < 1; loops++) { ++ u32 intmask, handled; ++ ++ intmask = bcm2835_sdhost_read(host, SDHSTS); ++ handled = intmask & (SDHSTS_BUSY_IRPT | ++ SDHSTS_BLOCK_IRPT | ++ SDHSTS_SDIO_IRPT | ++ SDHSTS_DATA_FLAG); ++ if ((handled == SDHSTS_DATA_FLAG) && // XXX ++ (loops == 0) && !host->data) { ++ pr_err("%s: sdhost_irq data interrupt 0x%08x even " ++ "though no data operation was in progress.\n", ++ mmc_hostname(host->mmc), ++ (unsigned)intmask); ++ ++ bcm2835_sdhost_dumpregs(host); ++ } ++ ++ if (!handled) ++ break; ++ ++ if (loops) ++ early |= handled; ++ ++ result = IRQ_HANDLED; ++ ++ /* Clear all interrupts and notifications */ ++ bcm2835_sdhost_write(host, intmask, SDHSTS); ++ ++ if (intmask & SDHSTS_BUSY_IRPT) ++ handled |= bcm2835_sdhost_busy_irq(host, intmask); ++ ++ /* There is no true data interrupt status bit, so it is ++ necessary to qualify the data flag with the interrupt ++ enable bit */ ++ if ((intmask & SDHSTS_DATA_FLAG) && ++ (host->hcfg & SDHCFG_DATA_IRPT_EN)) ++ handled |= bcm2835_sdhost_data_irq(host, intmask); ++ ++ if (intmask & SDHSTS_BLOCK_IRPT) ++ handled |= bcm2835_sdhost_block_irq(host, intmask); ++ ++ if (intmask & SDHSTS_SDIO_IRPT) { ++#ifndef CONFIG_ARCH_BCM2835 ++ cardint = 1; ++#else ++ bcm2835_sdhost_enable_sdio_irq_nolock(host, false); ++ host->thread_isr |= SDHSTS_SDIO_IRPT; ++ result = IRQ_WAKE_THREAD; ++#endif ++ } ++ ++ unexpected |= (intmask & ~handled); ++ } ++ ++ mmiowb(); ++ ++ spin_unlock(&host->lock); ++ ++ if (early) ++ pr_debug("%s: early %x (loops %d)\n", mmc_hostname(host->mmc), early, loops); ++ ++ if (unexpected) { ++ pr_err("%s: Unexpected interrupt 0x%08x.\n", ++ mmc_hostname(host->mmc), unexpected); ++ bcm2835_sdhost_dumpregs(host); ++ } ++ ++#ifndef CONFIG_ARCH_BCM2835 ++ if (cardint) ++ mmc_signal_sdio_irq(host->mmc); ++#endif ++ ++ return result; ++} ++ ++#ifdef CONFIG_ARCH_BCM2835 ++static irqreturn_t bcm2835_sdhost_thread_irq(int irq, void *dev_id) ++{ ++ struct bcm2835_host *host = dev_id; ++ unsigned long flags; ++ u32 isr; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ isr = host->thread_isr; ++ host->thread_isr = 0; ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (isr & SDHSTS_SDIO_IRPT) { ++ sdio_run_irqs(host->mmc); ++ ++/* Is this necessary? Why re-enable an interrupt which is enabled? ++ spin_lock_irqsave(&host->lock, flags); ++ if (host->flags & SDHSTS_SDIO_IRPT_ENABLED) ++ bcm2835_sdhost_enable_sdio_irq_nolock(host, true); ++ spin_unlock_irqrestore(&host->lock, flags); ++*/ ++ } ++ ++ return isr ? IRQ_HANDLED : IRQ_NONE; ++} ++#endif ++ ++ ++ ++void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock) ++{ ++ int div = 0; /* Initialized for compiler warning */ ++ unsigned int input_clock = clock; ++ ++ if (host->overclock_50 && (clock == 50000000)) ++ clock = host->overclock_50 * 1000000 + 999999; ++ ++ /* The SDCDIV register has 11 bits, and holds (div - 2). ++ But in data mode the max is 50MHz wihout a minimum, and only the ++ bottom 3 bits are used. Since the switch over is automatic (unless ++ we have marked the card as slow...), chosen values have to make ++ sense in both modes. ++ Ident mode must be 100-400KHz, so can range check the requested ++ clock. CMD15 must be used to return to data mode, so this can be ++ monitored. ++ ++ clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz ++ 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz ++ ++ 623->400KHz/27.8MHz ++ reset value (507)->491159/50MHz ++ ++ BUT, the 3-bit clock divisor in data mode is too small if the ++ core clock is higher than 250MHz, so instead use the SLOW_CARD ++ configuration bit to force the use of the ident clock divisor ++ at all times. ++ */ ++ ++ host->mmc->actual_clock = 0; ++ ++ if (clock < 100000) { ++ /* Can't stop the clock, but make it as slow as possible ++ * to show willing ++ */ ++ host->cdiv = SDCDIV_MAX_CDIV; ++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); ++ return; ++ } ++ ++ div = host->max_clk / clock; ++ if (div < 2) ++ div = 2; ++ if ((host->max_clk / div) > clock) ++ div++; ++ div -= 2; ++ ++ if (div > SDCDIV_MAX_CDIV) ++ div = SDCDIV_MAX_CDIV; ++ ++ clock = host->max_clk / (div + 2); ++ host->mmc->actual_clock = clock; ++ ++ if ((clock > input_clock) && (clock > host->max_overclock)) { ++ pr_warn("%s: Overclocking to %dHz\n", ++ mmc_hostname(host->mmc), clock); ++ host->max_overclock = clock; ++ } ++ ++ host->cdiv = div; ++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); ++ ++ pr_debug(DRIVER_NAME ": clock=%d -> max_clk=%d, cdiv=%x (actual clock %d)\n", ++ input_clock, host->max_clk, host->cdiv, host->mmc->actual_clock); ++} ++ ++static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ if (1) { ++ struct mmc_command *cmd = mrq->cmd; ++ const char *src = "cmd"; ++ BUG_ON(!cmd); ++ pr_debug("bcm2835_sdhost_request: %s %08x %08x (flags %x)\n", ++ src, cmd->opcode, cmd->arg, cmd->flags); ++ if (cmd->data) ++ pr_debug("bcm2835_sdhost_request: %s %d*%d\n", ++ (cmd->data->flags & MMC_DATA_READ) ? ++ "read" : "write", cmd->data->blocks, ++ cmd->data->blksz); ++ } ++ ++ if (mrq->data && !is_power_of_2(mrq->data->blksz)) { ++ pr_err("%s: Unsupported block size (%d bytes)\n", ++ mmc_hostname(mmc), mrq->data->blksz); ++ mrq->cmd->error = -EINVAL; ++ mmc_request_done(mmc, mrq); ++ return; ++ } ++ ++ host = mmc_priv(mmc); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ WARN_ON(host->mrq != NULL); ++ ++ host->mrq = mrq; ++ ++ if (mrq->sbc) ++ bcm2835_sdhost_send_command(host, mrq->sbc); ++ else ++ bcm2835_sdhost_send_command(host, mrq->cmd); ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (!mrq->sbc && mrq->cmd->data && host->use_dma) ++ /* DMA transfer starts now, PIO starts after irq */ ++ bcm2835_sdhost_transfer_dma(host); ++ ++ if (!host->use_busy) ++ bcm2835_sdhost_finish_command(host); ++} ++ ++ ++static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ pr_debug("bcm2835_sdhost_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n", ++ ios->clock, ios->power_mode, ios->bus_width, ++ ios->timing, ios->signal_voltage, ios->drv_type); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (!ios->clock || ios->clock != host->clock) { ++ bcm2835_sdhost_set_clock(host, ios->clock); ++ host->clock = ios->clock; ++ } ++ ++ /* set bus width */ ++ host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; ++ if (ios->bus_width == MMC_BUS_WIDTH_4) ++ host->hcfg |= SDHCFG_WIDE_EXT_BUS; ++ ++ host->hcfg |= SDHCFG_WIDE_INT_BUS; ++ ++ /* Disable clever clock switching, to cope with fast core clocks */ ++ host->hcfg |= SDHCFG_SLOW_CARD; ++ ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ ++ mmiowb(); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static int bcm2835_sdhost_multi_io_quirk(struct mmc_card *card, ++ unsigned int direction, ++ u32 blk_pos, int blk_size) ++{ ++ /* There is a bug in the host controller hardware that makes ++ reading the final sector of the card as part of a multiple read ++ problematic. Detect that case and shorten the read accordingly. ++ */ ++ /* csd.capacity is in weird units - convert to sectors */ ++ u32 card_sectors = (card->csd.capacity << (card->csd.read_blkbits - 9)); ++ ++ if ((direction == MMC_DATA_READ) && ++ ((blk_pos + blk_size) == card_sectors)) ++ blk_size--; ++ ++ return blk_size; ++} ++ ++ ++static struct mmc_host_ops bcm2835_sdhost_ops = { ++ .request = bcm2835_sdhost_request, ++ .set_ios = bcm2835_sdhost_set_ios, ++ .enable_sdio_irq = bcm2835_sdhost_enable_sdio_irq, ++ .multi_io_quirk = bcm2835_sdhost_multi_io_quirk, ++}; ++ ++ ++static void bcm2835_sdhost_tasklet_finish(unsigned long param) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ struct mmc_request *mrq; ++ ++ host = (struct bcm2835_host *)param; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ /* ++ * If this tasklet gets rescheduled while running, it will ++ * be run again afterwards but without any active request. ++ */ ++ if (!host->mrq) { ++ spin_unlock_irqrestore(&host->lock, flags); ++ return; ++ } ++ ++ del_timer(&host->timer); ++ ++ mrq = host->mrq; ++ ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ if (((mrq->cmd && mrq->cmd->error) || ++ (mrq->data && (mrq->data->error || ++ (mrq->data->stop && mrq->data->stop->error))))) { ++ ++ bcm2835_sdhost_reset(host); ++ } ++ ++ host->mrq = NULL; ++ host->cmd = NULL; ++ host->data = NULL; ++ ++ mmiowb(); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ mmc_request_done(host->mmc, mrq); ++} ++ ++ ++ ++int bcm2835_sdhost_add_host(struct bcm2835_host *host) ++{ ++ struct mmc_host *mmc; ++ struct dma_slave_config cfg; ++ int ret; ++ ++ mmc = host->mmc; ++ ++ bcm2835_sdhost_reset(host); ++ ++ mmc->f_max = host->max_clk; ++ mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; ++ ++ /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ ++ host->timeout_clk = mmc->f_max / 1000; ++#ifdef CONFIG_ARCH_BCM2835 ++ mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; ++#endif ++ /* host controller capabilities */ ++ mmc->caps |= /* MMC_CAP_SDIO_IRQ |*/ MMC_CAP_4_BIT_DATA | ++ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | ++ MMC_CAP_NEEDS_POLL | ++ (ALLOW_CMD23 * MMC_CAP_CMD23); ++ ++ spin_lock_init(&host->lock); ++ ++ if (host->allow_dma) { ++ if (!host->dma_chan_tx || !host->dma_chan_rx || ++ IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) { ++ pr_err("%s: Unable to initialise DMA channels. Falling back to PIO\n", DRIVER_NAME); ++ host->have_dma = false; ++ } else { ++ pr_info("DMA channels allocated for the SDHost driver"); ++ host->have_dma = true; ++ ++ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cfg.slave_id = 13; /* DREQ channel */ ++ ++ cfg.direction = DMA_MEM_TO_DEV; ++ cfg.src_addr = 0; ++ cfg.dst_addr = host->phys_addr + SDDATA; ++ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); ++ ++ cfg.direction = DMA_DEV_TO_MEM; ++ cfg.src_addr = host->phys_addr + SDDATA; ++ cfg.dst_addr = 0; ++ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); ++ } ++ } else { ++ pr_info("Forcing PIO mode\n"); ++ host->have_dma = false; ++ } ++ ++ mmc->max_segs = 128; ++ mmc->max_req_size = 524288; ++ mmc->max_seg_size = mmc->max_req_size; ++ mmc->max_blk_size = 512; ++ mmc->max_blk_count = 65535; ++ ++ /* report supported voltage ranges */ ++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ tasklet_init(&host->finish_tasklet, ++ bcm2835_sdhost_tasklet_finish, (unsigned long)host); ++ ++ setup_timer(&host->timer, bcm2835_sdhost_timeout_timer, (unsigned long)host); ++ ++ bcm2835_sdhost_init(host, 0); ++#ifndef CONFIG_ARCH_BCM2835 ++ ret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/, ++ mmc_hostname(mmc), host); ++#else ++ ret = request_threaded_irq(host->irq, bcm2835_sdhost_irq, bcm2835_sdhost_thread_irq, ++ IRQF_SHARED, mmc_hostname(mmc), host); ++#endif ++ if (ret) { ++ pr_err("%s: Failed to request IRQ %d: %d\n", ++ mmc_hostname(mmc), host->irq, ret); ++ goto untasklet; ++ } ++ ++ mmiowb(); ++ mmc_add_host(mmc); ++ ++ pr_info("Load BCM2835 SDHost driver\n"); ++ if (host->delay_after_stop) ++ pr_info("BCM2835 SDHost: delay_after_stop=%dus\n", ++ host->delay_after_stop); ++ ++ return 0; ++ ++untasklet: ++ tasklet_kill(&host->finish_tasklet); ++ ++ return ret; ++} ++ ++static int bcm2835_sdhost_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct clk *clk; ++ struct resource *iomem; ++ struct bcm2835_host *host; ++ struct mmc_host *mmc; ++ int ret; ++ ++ pr_debug("bcm2835_sdhost_probe\n"); ++ mmc = mmc_alloc_host(sizeof(*host), dev); ++ if (!mmc) ++ return -ENOMEM; ++ ++ mmc->ops = &bcm2835_sdhost_ops; ++ host = mmc_priv(mmc); ++ host->mmc = mmc; ++ host->timeout = msecs_to_jiffies(1000); ++ spin_lock_init(&host->lock); ++ ++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ host->ioaddr = devm_ioremap_resource(dev, iomem); ++ if (IS_ERR(host->ioaddr)) { ++ ret = PTR_ERR(host->ioaddr); ++ goto err; ++ } ++ ++ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; ++ pr_debug(" - ioaddr %lx, iomem->start %lx, phys_addr %lx\n", ++ (unsigned long)host->ioaddr, ++ (unsigned long)iomem->start, ++ (unsigned long)host->phys_addr); ++ ++ host->allow_dma = ALLOW_DMA; ++ ++ if (node) { ++ /* Read any custom properties */ ++ of_property_read_u32(node, ++ "brcm,delay-after-stop", ++ &host->delay_after_stop); ++ of_property_read_u32(node, ++ "brcm,overclock-50", ++ &host->overclock_50); ++ host->allow_dma = ALLOW_DMA && ++ !of_property_read_bool(node, "brcm,force-pio"); ++ } ++ ++ if (host->allow_dma) { ++ if (node) { ++ host->dma_chan_tx = ++ dma_request_slave_channel(dev, "tx"); ++ host->dma_chan_rx = ++ dma_request_slave_channel(dev, "rx"); ++ } else { ++ dma_cap_mask_t mask; ++ ++ dma_cap_zero(mask); ++ /* we don't care about the channel, any would work */ ++ dma_cap_set(DMA_SLAVE, mask); ++ host->dma_chan_tx = ++ dma_request_channel(mask, NULL, NULL); ++ host->dma_chan_rx = ++ dma_request_channel(mask, NULL, NULL); ++ } ++ } ++ ++ clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(dev, "could not get clk\n"); ++ ret = PTR_ERR(clk); ++ goto err; ++ } ++ ++ host->max_clk = clk_get_rate(clk); ++ ++ host->irq = platform_get_irq(pdev, 0); ++ if (host->irq <= 0) { ++ dev_err(dev, "get IRQ failed\n"); ++ ret = -EINVAL; ++ goto err; ++ } ++ ++ pr_debug(" - max_clk %lx, irq %d\n", ++ (unsigned long)host->max_clk, ++ (int)host->irq); ++ ++ if (node) ++ mmc_of_parse(mmc); ++ else ++ mmc->caps |= MMC_CAP_4_BIT_DATA; ++ ++ ret = bcm2835_sdhost_add_host(host); ++ if (ret) ++ goto err; ++ ++ platform_set_drvdata(pdev, host); ++ ++ pr_debug("bcm2835_sdhost_probe -> OK\n"); ++ ++ return 0; ++ ++err: ++ pr_debug("bcm2835_sdhost_probe -> err %d\n", ret); ++ mmc_free_host(mmc); ++ ++ return ret; ++} ++ ++static int bcm2835_sdhost_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_host *host = platform_get_drvdata(pdev); ++ ++ pr_debug("bcm2835_sdhost_remove\n"); ++ ++ mmc_remove_host(host->mmc); ++ ++ bcm2835_sdhost_set_power(host, false); ++ ++ free_irq(host->irq, host); ++ ++ del_timer_sync(&host->timer); ++ ++ tasklet_kill(&host->finish_tasklet); ++ ++ mmc_free_host(host->mmc); ++ platform_set_drvdata(pdev, NULL); ++ ++ pr_debug("bcm2835_sdhost_remove - OK\n"); ++ return 0; ++} ++ ++ ++static const struct of_device_id bcm2835_sdhost_match[] = { ++ { .compatible = "brcm,bcm2835-sdhost" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match); ++ ++ ++ ++static struct platform_driver bcm2835_sdhost_driver = { ++ .probe = bcm2835_sdhost_probe, ++ .remove = bcm2835_sdhost_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_sdhost_match, ++ }, ++}; ++module_platform_driver(bcm2835_sdhost_driver); ++ ++MODULE_ALIAS("platform:sdhost-bcm2835"); ++MODULE_DESCRIPTION("BCM2835 SDHost driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Phil Elwell"); diff --git a/target/linux/brcm2708/patches-4.1/0010-cma-Add-vc_cma-driver-to-enable-use-of-CMA.patch b/target/linux/brcm2708/patches-4.1/0010-cma-Add-vc_cma-driver-to-enable-use-of-CMA.patch new file mode 100644 index 0000000..0522f4a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0010-cma-Add-vc_cma-driver-to-enable-use-of-CMA.patch @@ -0,0 +1,1308 @@ +From 484bbb300f8c414aa66c555a5887e2e9dbac0cdd Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 3 Jul 2013 00:31:47 +0100 +Subject: [PATCH 010/203] cma: Add vc_cma driver to enable use of CMA + +Signed-off-by: popcornmix + +vc_cma: Make the vc_cma area the default contiguous DMA area +--- + drivers/char/Kconfig | 2 + + drivers/char/Makefile | 1 + + drivers/char/broadcom/Kconfig | 15 + + drivers/char/broadcom/Makefile | 1 + + drivers/char/broadcom/vc_cma/Makefile | 14 + + drivers/char/broadcom/vc_cma/vc_cma.c | 1193 +++++++++++++++++++++++++++++++++ + include/linux/broadcom/vc_cma.h | 29 + + 7 files changed, 1255 insertions(+) + create mode 100644 drivers/char/broadcom/Kconfig + create mode 100644 drivers/char/broadcom/Makefile + create mode 100644 drivers/char/broadcom/vc_cma/Makefile + create mode 100644 drivers/char/broadcom/vc_cma/vc_cma.c + create mode 100644 include/linux/broadcom/vc_cma.h + +--- a/drivers/char/Kconfig ++++ b/drivers/char/Kconfig +@@ -590,6 +590,8 @@ config DEVPORT + + source "drivers/s390/char/Kconfig" + ++source "drivers/char/broadcom/Kconfig" ++ + config MSM_SMD_PKT + bool "Enable device interface for some SMD packet ports" + default n +--- a/drivers/char/Makefile ++++ b/drivers/char/Makefile +@@ -62,3 +62,4 @@ js-rtc-y = rtc.o + + obj-$(CONFIG_TILE_SROM) += tile-srom.o + obj-$(CONFIG_XILLYBUS) += xillybus/ ++obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/ +--- /dev/null ++++ b/drivers/char/broadcom/Kconfig +@@ -0,0 +1,15 @@ ++# ++# Broadcom char driver config ++# ++ ++menuconfig BRCM_CHAR_DRIVERS ++ bool "Broadcom Char Drivers" ++ help ++ Broadcom's char drivers ++ ++config BCM_VC_CMA ++ bool "Videocore CMA" ++ depends on CMA && BRCM_CHAR_DRIVERS && BCM2708_VCHIQ ++ default n ++ help ++ Helper for videocore CMA access. +--- /dev/null ++++ b/drivers/char/broadcom/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_BCM_VC_CMA) += vc_cma/ +--- /dev/null ++++ b/drivers/char/broadcom/vc_cma/Makefile +@@ -0,0 +1,14 @@ ++ccflags-y += -Wall -Wstrict-prototypes -Wno-trigraphs ++ccflags-y += -Werror ++ccflags-y += -Iinclude/linux/broadcom ++ccflags-y += -Idrivers/misc/vc04_services ++ccflags-y += -Idrivers/misc/vc04_services/interface/vchi ++ccflags-y += -Idrivers/misc/vc04_services/interface/vchiq_arm ++ ++ccflags-y += -D__KERNEL__ ++ccflags-y += -D__linux__ ++ccflags-y += -Werror ++ ++obj-$(CONFIG_BCM_VC_CMA) += vc-cma.o ++ ++vc-cma-objs := vc_cma.o +--- /dev/null ++++ b/drivers/char/broadcom/vc_cma/vc_cma.c +@@ -0,0 +1,1193 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vc_cma.h" ++ ++#include "vchiq_util.h" ++#include "vchiq_connected.h" ++//#include "debug_sym.h" ++//#include "vc_mem.h" ++ ++#define DRIVER_NAME "vc-cma" ++ ++#define LOG_DBG(fmt, ...) \ ++ if (vc_cma_debug) \ ++ printk(KERN_INFO fmt "\n", ##__VA_ARGS__) ++#define LOG_INFO(fmt, ...) \ ++ printk(KERN_INFO fmt "\n", ##__VA_ARGS__) ++#define LOG_ERR(fmt, ...) \ ++ printk(KERN_ERR fmt "\n", ##__VA_ARGS__) ++ ++#define VC_CMA_FOURCC VCHIQ_MAKE_FOURCC('C', 'M', 'A', ' ') ++#define VC_CMA_VERSION 2 ++ ++#define VC_CMA_CHUNK_ORDER 6 /* 256K */ ++#define VC_CMA_CHUNK_SIZE (4096 << VC_CMA_CHUNK_ORDER) ++#define VC_CMA_MAX_PARAMS_PER_MSG \ ++ ((VCHIQ_MAX_MSG_SIZE - sizeof(unsigned short))/sizeof(unsigned short)) ++#define VC_CMA_RESERVE_COUNT_MAX 16 ++ ++#define PAGES_PER_CHUNK (VC_CMA_CHUNK_SIZE / PAGE_SIZE) ++ ++#define VCADDR_TO_PHYSADDR(vcaddr) (mm_vc_mem_phys_addr + vcaddr) ++ ++#define loud_error(...) \ ++ LOG_ERR("===== " __VA_ARGS__) ++ ++enum { ++ VC_CMA_MSG_QUIT, ++ VC_CMA_MSG_OPEN, ++ VC_CMA_MSG_TICK, ++ VC_CMA_MSG_ALLOC, /* chunk count */ ++ VC_CMA_MSG_FREE, /* chunk, chunk, ... */ ++ VC_CMA_MSG_ALLOCATED, /* chunk, chunk, ... */ ++ VC_CMA_MSG_REQUEST_ALLOC, /* chunk count */ ++ VC_CMA_MSG_REQUEST_FREE, /* chunk count */ ++ VC_CMA_MSG_RESERVE, /* bytes lo, bytes hi */ ++ VC_CMA_MSG_UPDATE_RESERVE, ++ VC_CMA_MSG_MAX ++}; ++ ++struct cma_msg { ++ unsigned short type; ++ unsigned short params[VC_CMA_MAX_PARAMS_PER_MSG]; ++}; ++ ++struct vc_cma_reserve_user { ++ unsigned int pid; ++ unsigned int reserve; ++}; ++ ++/* Device (/dev) related variables */ ++static dev_t vc_cma_devnum; ++static struct class *vc_cma_class; ++static struct cdev vc_cma_cdev; ++static int vc_cma_inited; ++static int vc_cma_debug; ++ ++/* Proc entry */ ++static struct proc_dir_entry *vc_cma_proc_entry; ++ ++phys_addr_t vc_cma_base; ++struct page *vc_cma_base_page; ++unsigned int vc_cma_size; ++EXPORT_SYMBOL(vc_cma_size); ++unsigned int vc_cma_initial; ++unsigned int vc_cma_chunks; ++unsigned int vc_cma_chunks_used; ++unsigned int vc_cma_chunks_reserved; ++ ++ ++void *vc_cma_dma_alloc; ++unsigned int vc_cma_dma_size; ++ ++static int in_loud_error; ++ ++unsigned int vc_cma_reserve_total; ++unsigned int vc_cma_reserve_count; ++struct vc_cma_reserve_user vc_cma_reserve_users[VC_CMA_RESERVE_COUNT_MAX]; ++static DEFINE_SEMAPHORE(vc_cma_reserve_mutex); ++static DEFINE_SEMAPHORE(vc_cma_worker_queue_push_mutex); ++ ++static u64 vc_cma_dma_mask = DMA_BIT_MASK(32); ++static struct platform_device vc_cma_device = { ++ .name = "vc-cma", ++ .id = 0, ++ .dev = { ++ .dma_mask = &vc_cma_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++static VCHIQ_INSTANCE_T cma_instance; ++static VCHIQ_SERVICE_HANDLE_T cma_service; ++static VCHIU_QUEUE_T cma_msg_queue; ++static struct task_struct *cma_worker; ++ ++static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid); ++static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply); ++static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T * header, ++ VCHIQ_SERVICE_HANDLE_T service, ++ void *bulk_userdata); ++static void send_vc_msg(unsigned short type, ++ unsigned short param1, unsigned short param2); ++static bool send_worker_msg(VCHIQ_HEADER_T * msg); ++ ++static int early_vc_cma_mem(char *p) ++{ ++ unsigned int new_size; ++ printk(KERN_NOTICE "early_vc_cma_mem(%s)", p); ++ vc_cma_size = memparse(p, &p); ++ vc_cma_initial = vc_cma_size; ++ if (*p == '/') ++ vc_cma_size = memparse(p + 1, &p); ++ if (*p == '@') ++ vc_cma_base = memparse(p + 1, &p); ++ ++ new_size = (vc_cma_size - ((-vc_cma_base) & (VC_CMA_CHUNK_SIZE - 1))) ++ & ~(VC_CMA_CHUNK_SIZE - 1); ++ if (new_size > vc_cma_size) ++ vc_cma_size = 0; ++ vc_cma_initial = (vc_cma_initial + VC_CMA_CHUNK_SIZE - 1) ++ & ~(VC_CMA_CHUNK_SIZE - 1); ++ if (vc_cma_initial > vc_cma_size) ++ vc_cma_initial = vc_cma_size; ++ vc_cma_base = (vc_cma_base + VC_CMA_CHUNK_SIZE - 1) ++ & ~(VC_CMA_CHUNK_SIZE - 1); ++ ++ printk(KERN_NOTICE " -> initial %x, size %x, base %x", vc_cma_initial, ++ vc_cma_size, (unsigned int)vc_cma_base); ++ ++ return 0; ++} ++ ++early_param("vc-cma-mem", early_vc_cma_mem); ++ ++void vc_cma_early_init(void) ++{ ++ LOG_DBG("vc_cma_early_init - vc_cma_chunks = %d", vc_cma_chunks); ++ if (vc_cma_size) { ++ int rc = platform_device_register(&vc_cma_device); ++ LOG_DBG("platform_device_register -> %d", rc); ++ } ++} ++ ++void vc_cma_reserve(void) ++{ ++ /* if vc_cma_size is set, then declare vc CMA area of the same ++ * size from the end of memory ++ */ ++ if (vc_cma_size) { ++ if (dma_declare_contiguous(&vc_cma_device.dev, vc_cma_size, ++ vc_cma_base, 0) == 0) { ++ if (!dev_get_cma_area(NULL)) { ++ /* There is no default CMA area - make this ++ the default */ ++ struct cma *vc_cma_area = dev_get_cma_area( ++ &vc_cma_device.dev); ++ dma_contiguous_set_default(vc_cma_area); ++ LOG_INFO("vc_cma_reserve - using vc_cma as " ++ "the default contiguous DMA area"); ++ } ++ } else { ++ LOG_ERR("vc_cma: dma_declare_contiguous(%x,%x) failed", ++ vc_cma_size, (unsigned int)vc_cma_base); ++ vc_cma_size = 0; ++ } ++ } ++ vc_cma_chunks = vc_cma_size / VC_CMA_CHUNK_SIZE; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_open ++* ++***************************************************************************/ ++ ++static int vc_cma_open(struct inode *inode, struct file *file) ++{ ++ (void)inode; ++ (void)file; ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_release ++* ++***************************************************************************/ ++ ++static int vc_cma_release(struct inode *inode, struct file *file) ++{ ++ (void)inode; ++ (void)file; ++ ++ vc_cma_set_reserve(0, current->tgid); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_ioctl ++* ++***************************************************************************/ ++ ++static long vc_cma_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int rc = 0; ++ ++ (void)cmd; ++ (void)arg; ++ ++ switch (cmd) { ++ case VC_CMA_IOC_RESERVE: ++ rc = vc_cma_set_reserve((unsigned int)arg, current->tgid); ++ if (rc >= 0) ++ rc = 0; ++ break; ++ default: ++ LOG_ERR("vc-cma: Unknown ioctl %x", cmd); ++ return -ENOTTY; ++ } ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* File Operations for the driver. ++* ++***************************************************************************/ ++ ++static const struct file_operations vc_cma_fops = { ++ .owner = THIS_MODULE, ++ .open = vc_cma_open, ++ .release = vc_cma_release, ++ .unlocked_ioctl = vc_cma_ioctl, ++}; ++ ++/**************************************************************************** ++* ++* vc_cma_proc_open ++* ++***************************************************************************/ ++ ++static int vc_cma_show_info(struct seq_file *m, void *v) ++{ ++ int i; ++ ++ seq_printf(m, "Videocore CMA:\n"); ++ seq_printf(m, " Base : %08x\n", (unsigned int)vc_cma_base); ++ seq_printf(m, " Length : %08x\n", vc_cma_size); ++ seq_printf(m, " Initial : %08x\n", vc_cma_initial); ++ seq_printf(m, " Chunk size : %08x\n", VC_CMA_CHUNK_SIZE); ++ seq_printf(m, " Chunks : %4d (%d bytes)\n", ++ (int)vc_cma_chunks, ++ (int)(vc_cma_chunks * VC_CMA_CHUNK_SIZE)); ++ seq_printf(m, " Used : %4d (%d bytes)\n", ++ (int)vc_cma_chunks_used, ++ (int)(vc_cma_chunks_used * VC_CMA_CHUNK_SIZE)); ++ seq_printf(m, " Reserved : %4d (%d bytes)\n", ++ (unsigned int)vc_cma_chunks_reserved, ++ (int)(vc_cma_chunks_reserved * VC_CMA_CHUNK_SIZE)); ++ ++ for (i = 0; i < vc_cma_reserve_count; i++) { ++ struct vc_cma_reserve_user *user = &vc_cma_reserve_users[i]; ++ seq_printf(m, " PID %5d: %d bytes\n", user->pid, ++ user->reserve); ++ } ++ seq_printf(m, " dma_alloc : %p (%d pages)\n", ++ vc_cma_dma_alloc ? page_address(vc_cma_dma_alloc) : 0, ++ vc_cma_dma_size); ++ ++ seq_printf(m, "\n"); ++ ++ return 0; ++} ++ ++static int vc_cma_proc_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, vc_cma_show_info, NULL); ++} ++ ++/**************************************************************************** ++* ++* vc_cma_proc_write ++* ++***************************************************************************/ ++ ++static int vc_cma_proc_write(struct file *file, ++ const char __user *buffer, ++ size_t size, loff_t *ppos) ++{ ++ int rc = -EFAULT; ++ char input_str[20]; ++ ++ memset(input_str, 0, sizeof(input_str)); ++ ++ if (size > sizeof(input_str)) { ++ LOG_ERR("%s: input string length too long", __func__); ++ goto out; ++ } ++ ++ if (copy_from_user(input_str, buffer, size - 1)) { ++ LOG_ERR("%s: failed to get input string", __func__); ++ goto out; ++ } ++#define ALLOC_STR "alloc" ++#define FREE_STR "free" ++#define DEBUG_STR "debug" ++#define RESERVE_STR "reserve" ++#define DMA_ALLOC_STR "dma_alloc" ++#define DMA_FREE_STR "dma_free" ++ if (strncmp(input_str, ALLOC_STR, strlen(ALLOC_STR)) == 0) { ++ int alloc_size; ++ char *p = input_str + strlen(ALLOC_STR); ++ ++ while (*p == ' ') ++ p++; ++ alloc_size = memparse(p, NULL); ++ LOG_INFO("/proc/vc-cma: alloc %d", alloc_size); ++ if (alloc_size) ++ send_vc_msg(VC_CMA_MSG_REQUEST_FREE, ++ alloc_size / VC_CMA_CHUNK_SIZE, 0); ++ else ++ LOG_ERR("invalid size '%s'", p); ++ rc = size; ++ } else if (strncmp(input_str, FREE_STR, strlen(FREE_STR)) == 0) { ++ int alloc_size; ++ char *p = input_str + strlen(FREE_STR); ++ ++ while (*p == ' ') ++ p++; ++ alloc_size = memparse(p, NULL); ++ LOG_INFO("/proc/vc-cma: free %d", alloc_size); ++ if (alloc_size) ++ send_vc_msg(VC_CMA_MSG_REQUEST_ALLOC, ++ alloc_size / VC_CMA_CHUNK_SIZE, 0); ++ else ++ LOG_ERR("invalid size '%s'", p); ++ rc = size; ++ } else if (strncmp(input_str, DEBUG_STR, strlen(DEBUG_STR)) == 0) { ++ char *p = input_str + strlen(DEBUG_STR); ++ while (*p == ' ') ++ p++; ++ if ((strcmp(p, "on") == 0) || (strcmp(p, "1") == 0)) ++ vc_cma_debug = 1; ++ else if ((strcmp(p, "off") == 0) || (strcmp(p, "0") == 0)) ++ vc_cma_debug = 0; ++ LOG_INFO("/proc/vc-cma: debug %s", vc_cma_debug ? "on" : "off"); ++ rc = size; ++ } else if (strncmp(input_str, RESERVE_STR, strlen(RESERVE_STR)) == 0) { ++ int alloc_size; ++ int reserved; ++ char *p = input_str + strlen(RESERVE_STR); ++ while (*p == ' ') ++ p++; ++ alloc_size = memparse(p, NULL); ++ ++ reserved = vc_cma_set_reserve(alloc_size, current->tgid); ++ rc = (reserved >= 0) ? size : reserved; ++ } else if (strncmp(input_str, DMA_ALLOC_STR, strlen(DMA_ALLOC_STR)) == 0) { ++ int alloc_size; ++ char *p = input_str + strlen(DMA_ALLOC_STR); ++ while (*p == ' ') ++ p++; ++ alloc_size = memparse(p, NULL); ++ ++ if (vc_cma_dma_alloc) { ++ dma_release_from_contiguous(NULL, vc_cma_dma_alloc, ++ vc_cma_dma_size); ++ vc_cma_dma_alloc = NULL; ++ vc_cma_dma_size = 0; ++ } ++ vc_cma_dma_alloc = dma_alloc_from_contiguous(NULL, alloc_size, 0); ++ vc_cma_dma_size = (vc_cma_dma_alloc ? alloc_size : 0); ++ if (vc_cma_dma_alloc) ++ LOG_INFO("dma_alloc(%d pages) -> %p", alloc_size, page_address(vc_cma_dma_alloc)); ++ else ++ LOG_ERR("dma_alloc(%d pages) failed", alloc_size); ++ rc = size; ++ } else if (strncmp(input_str, DMA_FREE_STR, strlen(DMA_FREE_STR)) == 0) { ++ if (vc_cma_dma_alloc) { ++ dma_release_from_contiguous(NULL, vc_cma_dma_alloc, ++ vc_cma_dma_size); ++ vc_cma_dma_alloc = NULL; ++ vc_cma_dma_size = 0; ++ } ++ rc = size; ++ } ++ ++out: ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* File Operations for /proc interface. ++* ++***************************************************************************/ ++ ++static const struct file_operations vc_cma_proc_fops = { ++ .open = vc_cma_proc_open, ++ .read = seq_read, ++ .write = vc_cma_proc_write, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++ ++static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid) ++{ ++ struct vc_cma_reserve_user *user = NULL; ++ int delta = 0; ++ int i; ++ ++ if (down_interruptible(&vc_cma_reserve_mutex)) ++ return -ERESTARTSYS; ++ ++ for (i = 0; i < vc_cma_reserve_count; i++) { ++ if (pid == vc_cma_reserve_users[i].pid) { ++ user = &vc_cma_reserve_users[i]; ++ delta = reserve - user->reserve; ++ if (reserve) ++ user->reserve = reserve; ++ else { ++ /* Remove this entry by copying downwards */ ++ while ((i + 1) < vc_cma_reserve_count) { ++ user[0].pid = user[1].pid; ++ user[0].reserve = user[1].reserve; ++ user++; ++ i++; ++ } ++ vc_cma_reserve_count--; ++ user = NULL; ++ } ++ break; ++ } ++ } ++ ++ if (reserve && !user) { ++ if (vc_cma_reserve_count == VC_CMA_RESERVE_COUNT_MAX) { ++ LOG_ERR("vc-cma: Too many reservations - " ++ "increase CMA_RESERVE_COUNT_MAX"); ++ up(&vc_cma_reserve_mutex); ++ return -EBUSY; ++ } ++ user = &vc_cma_reserve_users[vc_cma_reserve_count]; ++ user->pid = pid; ++ user->reserve = reserve; ++ delta = reserve; ++ vc_cma_reserve_count++; ++ } ++ ++ vc_cma_reserve_total += delta; ++ ++ send_vc_msg(VC_CMA_MSG_RESERVE, ++ vc_cma_reserve_total & 0xffff, vc_cma_reserve_total >> 16); ++ ++ send_worker_msg((VCHIQ_HEADER_T *) VC_CMA_MSG_UPDATE_RESERVE); ++ ++ LOG_DBG("/proc/vc-cma: reserve %d (PID %d) - total %u", ++ reserve, pid, vc_cma_reserve_total); ++ ++ up(&vc_cma_reserve_mutex); ++ ++ return vc_cma_reserve_total; ++} ++ ++static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T * header, ++ VCHIQ_SERVICE_HANDLE_T service, ++ void *bulk_userdata) ++{ ++ switch (reason) { ++ case VCHIQ_MESSAGE_AVAILABLE: ++ if (!send_worker_msg(header)) ++ return VCHIQ_RETRY; ++ break; ++ case VCHIQ_SERVICE_CLOSED: ++ LOG_DBG("CMA service closed"); ++ break; ++ default: ++ LOG_ERR("Unexpected CMA callback reason %d", reason); ++ break; ++ } ++ return VCHIQ_SUCCESS; ++} ++ ++static void send_vc_msg(unsigned short type, ++ unsigned short param1, unsigned short param2) ++{ ++ unsigned short msg[] = { type, param1, param2 }; ++ VCHIQ_ELEMENT_T elem = { &msg, sizeof(msg) }; ++ VCHIQ_STATUS_T ret; ++ vchiq_use_service(cma_service); ++ ret = vchiq_queue_message(cma_service, &elem, 1); ++ vchiq_release_service(cma_service); ++ if (ret != VCHIQ_SUCCESS) ++ LOG_ERR("vchiq_queue_message returned %x", ret); ++} ++ ++static bool send_worker_msg(VCHIQ_HEADER_T * msg) ++{ ++ if (down_interruptible(&vc_cma_worker_queue_push_mutex)) ++ return false; ++ vchiu_queue_push(&cma_msg_queue, msg); ++ up(&vc_cma_worker_queue_push_mutex); ++ return true; ++} ++ ++static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply) ++{ ++ int i; ++ for (i = 0; i < num_chunks; i++) { ++ struct page *chunk; ++ unsigned int chunk_num; ++ uint8_t *chunk_addr; ++ size_t chunk_size = PAGES_PER_CHUNK << PAGE_SHIFT; ++ ++ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev, ++ PAGES_PER_CHUNK, ++ VC_CMA_CHUNK_ORDER); ++ if (!chunk) ++ break; ++ ++ chunk_addr = page_address(chunk); ++ dmac_flush_range(chunk_addr, chunk_addr + chunk_size); ++ outer_inv_range(__pa(chunk_addr), __pa(chunk_addr) + ++ chunk_size); ++ ++ chunk_num = ++ (page_to_phys(chunk) - vc_cma_base) / VC_CMA_CHUNK_SIZE; ++ BUG_ON(((page_to_phys(chunk) - vc_cma_base) % ++ VC_CMA_CHUNK_SIZE) != 0); ++ if (chunk_num >= vc_cma_chunks) { ++ phys_addr_t _pa = vc_cma_base + vc_cma_size - 1; ++ LOG_ERR("%s: ===============================", ++ __func__); ++ LOG_ERR("%s: chunk phys %x, vc_cma %pa-%pa - " ++ "bad SPARSEMEM configuration?", ++ __func__, (unsigned int)page_to_phys(chunk), ++ &vc_cma_base, &_pa); ++ LOG_ERR("%s: dev->cma_area = %p", __func__, ++ (void*)0/*vc_cma_device.dev.cma_area*/); ++ LOG_ERR("%s: ===============================", ++ __func__); ++ break; ++ } ++ reply->params[i] = chunk_num; ++ vc_cma_chunks_used++; ++ } ++ ++ if (i < num_chunks) { ++ LOG_ERR("%s: dma_alloc_from_contiguous failed " ++ "for %x bytes (alloc %d of %d, %d free)", ++ __func__, VC_CMA_CHUNK_SIZE, i, ++ num_chunks, vc_cma_chunks - vc_cma_chunks_used); ++ num_chunks = i; ++ } ++ ++ LOG_DBG("CMA allocated %d chunks -> %d used", ++ num_chunks, vc_cma_chunks_used); ++ reply->type = VC_CMA_MSG_ALLOCATED; ++ ++ { ++ VCHIQ_ELEMENT_T elem = { ++ reply, ++ offsetof(struct cma_msg, params[0]) + ++ num_chunks * sizeof(reply->params[0]) ++ }; ++ VCHIQ_STATUS_T ret; ++ vchiq_use_service(cma_service); ++ ret = vchiq_queue_message(cma_service, &elem, 1); ++ vchiq_release_service(cma_service); ++ if (ret != VCHIQ_SUCCESS) ++ LOG_ERR("vchiq_queue_message return " "%x", ret); ++ } ++ ++ return num_chunks; ++} ++ ++static int cma_worker_proc(void *param) ++{ ++ static struct cma_msg reply; ++ (void)param; ++ ++ while (1) { ++ VCHIQ_HEADER_T *msg; ++ static struct cma_msg msg_copy; ++ struct cma_msg *cma_msg = &msg_copy; ++ int type, msg_size; ++ ++ msg = vchiu_queue_pop(&cma_msg_queue); ++ if ((unsigned int)msg >= VC_CMA_MSG_MAX) { ++ msg_size = msg->size; ++ memcpy(&msg_copy, msg->data, msg_size); ++ type = cma_msg->type; ++ vchiq_release_message(cma_service, msg); ++ } else { ++ msg_size = 0; ++ type = (int)msg; ++ if (type == VC_CMA_MSG_QUIT) ++ break; ++ else if (type == VC_CMA_MSG_UPDATE_RESERVE) { ++ msg = NULL; ++ cma_msg = NULL; ++ } else { ++ BUG(); ++ continue; ++ } ++ } ++ ++ switch (type) { ++ case VC_CMA_MSG_ALLOC:{ ++ int num_chunks, free_chunks; ++ num_chunks = cma_msg->params[0]; ++ free_chunks = ++ vc_cma_chunks - vc_cma_chunks_used; ++ LOG_DBG("CMA_MSG_ALLOC(%d chunks)", num_chunks); ++ if (num_chunks > VC_CMA_MAX_PARAMS_PER_MSG) { ++ LOG_ERR ++ ("CMA_MSG_ALLOC - chunk count (%d) " ++ "exceeds VC_CMA_MAX_PARAMS_PER_MSG (%d)", ++ num_chunks, ++ VC_CMA_MAX_PARAMS_PER_MSG); ++ num_chunks = VC_CMA_MAX_PARAMS_PER_MSG; ++ } ++ ++ if (num_chunks > free_chunks) { ++ LOG_ERR ++ ("CMA_MSG_ALLOC - chunk count (%d) " ++ "exceeds free chunks (%d)", ++ num_chunks, free_chunks); ++ num_chunks = free_chunks; ++ } ++ ++ vc_cma_alloc_chunks(num_chunks, &reply); ++ } ++ break; ++ ++ case VC_CMA_MSG_FREE:{ ++ int chunk_count = ++ (msg_size - ++ offsetof(struct cma_msg, ++ params)) / ++ sizeof(cma_msg->params[0]); ++ int i; ++ BUG_ON(chunk_count <= 0); ++ ++ LOG_DBG("CMA_MSG_FREE(%d chunks - %x, ...)", ++ chunk_count, cma_msg->params[0]); ++ for (i = 0; i < chunk_count; i++) { ++ int chunk_num = cma_msg->params[i]; ++ struct page *page = vc_cma_base_page + ++ chunk_num * PAGES_PER_CHUNK; ++ if (chunk_num >= vc_cma_chunks) { ++ LOG_ERR ++ ("CMA_MSG_FREE - chunk %d of %d" ++ " (value %x) exceeds maximum " ++ "(%x)", i, chunk_count, ++ chunk_num, ++ vc_cma_chunks - 1); ++ break; ++ } ++ ++ if (!dma_release_from_contiguous ++ (&vc_cma_device.dev, page, ++ PAGES_PER_CHUNK)) { ++ phys_addr_t _pa = page_to_phys(page); ++ LOG_ERR ++ ("CMA_MSG_FREE - failed to " ++ "release chunk %d (phys %pa, " ++ "page %x)", chunk_num, ++ &_pa, ++ (unsigned int)page); ++ } ++ vc_cma_chunks_used--; ++ } ++ LOG_DBG("CMA released %d chunks -> %d used", ++ i, vc_cma_chunks_used); ++ } ++ break; ++ ++ case VC_CMA_MSG_UPDATE_RESERVE:{ ++ int chunks_needed = ++ ((vc_cma_reserve_total + VC_CMA_CHUNK_SIZE - ++ 1) ++ / VC_CMA_CHUNK_SIZE) - ++ vc_cma_chunks_reserved; ++ ++ LOG_DBG ++ ("CMA_MSG_UPDATE_RESERVE(%d chunks needed)", ++ chunks_needed); ++ ++ /* Cap the reservations to what is available */ ++ if (chunks_needed > 0) { ++ if (chunks_needed > ++ (vc_cma_chunks - ++ vc_cma_chunks_used)) ++ chunks_needed = ++ (vc_cma_chunks - ++ vc_cma_chunks_used); ++ ++ chunks_needed = ++ vc_cma_alloc_chunks(chunks_needed, ++ &reply); ++ } ++ ++ LOG_DBG ++ ("CMA_MSG_UPDATE_RESERVE(%d chunks allocated)", ++ chunks_needed); ++ vc_cma_chunks_reserved += chunks_needed; ++ } ++ break; ++ ++ default: ++ LOG_ERR("unexpected msg type %d", type); ++ break; ++ } ++ } ++ ++ LOG_DBG("quitting..."); ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_connected_init ++* ++* This function is called once the videocore has been connected. ++* ++***************************************************************************/ ++ ++static void vc_cma_connected_init(void) ++{ ++ VCHIQ_SERVICE_PARAMS_T service_params; ++ ++ LOG_DBG("vc_cma_connected_init"); ++ ++ if (!vchiu_queue_init(&cma_msg_queue, 16)) { ++ LOG_ERR("could not create CMA msg queue"); ++ goto fail_queue; ++ } ++ ++ if (vchiq_initialise(&cma_instance) != VCHIQ_SUCCESS) ++ goto fail_vchiq_init; ++ ++ vchiq_connect(cma_instance); ++ ++ service_params.fourcc = VC_CMA_FOURCC; ++ service_params.callback = cma_service_callback; ++ service_params.userdata = NULL; ++ service_params.version = VC_CMA_VERSION; ++ service_params.version_min = VC_CMA_VERSION; ++ ++ if (vchiq_open_service(cma_instance, &service_params, ++ &cma_service) != VCHIQ_SUCCESS) { ++ LOG_ERR("failed to open service - already in use?"); ++ goto fail_vchiq_open; ++ } ++ ++ vchiq_release_service(cma_service); ++ ++ cma_worker = kthread_create(cma_worker_proc, NULL, "cma_worker"); ++ if (!cma_worker) { ++ LOG_ERR("could not create CMA worker thread"); ++ goto fail_worker; ++ } ++ set_user_nice(cma_worker, -20); ++ wake_up_process(cma_worker); ++ ++ return; ++ ++fail_worker: ++ vchiq_close_service(cma_service); ++fail_vchiq_open: ++ vchiq_shutdown(cma_instance); ++fail_vchiq_init: ++ vchiu_queue_delete(&cma_msg_queue); ++fail_queue: ++ return; ++} ++ ++void ++loud_error_header(void) ++{ ++ if (in_loud_error) ++ return; ++ ++ LOG_ERR("============================================================" ++ "================"); ++ LOG_ERR("============================================================" ++ "================"); ++ LOG_ERR("====="); ++ ++ in_loud_error = 1; ++} ++ ++void ++loud_error_footer(void) ++{ ++ if (!in_loud_error) ++ return; ++ ++ LOG_ERR("====="); ++ LOG_ERR("============================================================" ++ "================"); ++ LOG_ERR("============================================================" ++ "================"); ++ ++ in_loud_error = 0; ++} ++ ++#if 1 ++static int check_cma_config(void) { return 1; } ++#else ++static int ++read_vc_debug_var(VC_MEM_ACCESS_HANDLE_T handle, ++ const char *symbol, ++ void *buf, size_t bufsize) ++{ ++ VC_MEM_ADDR_T vcMemAddr; ++ size_t vcMemSize; ++ uint8_t *mapAddr; ++ off_t vcMapAddr; ++ ++ if (!LookupVideoCoreSymbol(handle, symbol, ++ &vcMemAddr, ++ &vcMemSize)) { ++ loud_error_header(); ++ loud_error( ++ "failed to find VC symbol \"%s\".", ++ symbol); ++ loud_error_footer(); ++ return 0; ++ } ++ ++ if (vcMemSize != bufsize) { ++ loud_error_header(); ++ loud_error( ++ "VC symbol \"%s\" is the wrong size.", ++ symbol); ++ loud_error_footer(); ++ return 0; ++ } ++ ++ vcMapAddr = (off_t)vcMemAddr & VC_MEM_TO_ARM_ADDR_MASK; ++ vcMapAddr += mm_vc_mem_phys_addr; ++ mapAddr = ioremap_nocache(vcMapAddr, vcMemSize); ++ if (mapAddr == 0) { ++ loud_error_header(); ++ loud_error( ++ "failed to ioremap \"%s\" @ 0x%x " ++ "(phys: 0x%x, size: %u).", ++ symbol, ++ (unsigned int)vcMapAddr, ++ (unsigned int)vcMemAddr, ++ (unsigned int)vcMemSize); ++ loud_error_footer(); ++ return 0; ++ } ++ ++ memcpy(buf, mapAddr, bufsize); ++ iounmap(mapAddr); ++ ++ return 1; ++} ++ ++ ++static int ++check_cma_config(void) ++{ ++ VC_MEM_ACCESS_HANDLE_T mem_hndl; ++ VC_MEM_ADDR_T mempool_start; ++ VC_MEM_ADDR_T mempool_end; ++ VC_MEM_ADDR_T mempool_offline_start; ++ VC_MEM_ADDR_T mempool_offline_end; ++ VC_MEM_ADDR_T cam_alloc_base; ++ VC_MEM_ADDR_T cam_alloc_size; ++ VC_MEM_ADDR_T cam_alloc_end; ++ int success = 0; ++ ++ if (OpenVideoCoreMemory(&mem_hndl) != 0) ++ goto out; ++ ++ /* Read the relevant VideoCore variables */ ++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_START", ++ &mempool_start, ++ sizeof(mempool_start))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_END", ++ &mempool_end, ++ sizeof(mempool_end))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_START", ++ &mempool_offline_start, ++ sizeof(mempool_offline_start))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_END", ++ &mempool_offline_end, ++ sizeof(mempool_offline_end))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "cam_alloc_base", ++ &cam_alloc_base, ++ sizeof(cam_alloc_base))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "cam_alloc_size", ++ &cam_alloc_size, ++ sizeof(cam_alloc_size))) ++ goto close; ++ ++ cam_alloc_end = cam_alloc_base + cam_alloc_size; ++ ++ success = 1; ++ ++ /* Now the sanity checks */ ++ if (!mempool_offline_start) ++ mempool_offline_start = mempool_start; ++ if (!mempool_offline_end) ++ mempool_offline_end = mempool_end; ++ ++ if (VCADDR_TO_PHYSADDR(mempool_offline_start) != vc_cma_base) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_START(%x -> %lx) doesn't match " ++ "vc_cma_base(%x)", ++ mempool_offline_start, ++ VCADDR_TO_PHYSADDR(mempool_offline_start), ++ vc_cma_base); ++ success = 0; ++ } ++ ++ if (VCADDR_TO_PHYSADDR(mempool_offline_end) != ++ (vc_cma_base + vc_cma_size)) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_END(%x -> %lx) doesn't match " ++ "vc_cma_base(%x) + vc_cma_size(%x) = %x", ++ mempool_offline_start, ++ VCADDR_TO_PHYSADDR(mempool_offline_end), ++ vc_cma_base, vc_cma_size, vc_cma_base + vc_cma_size); ++ success = 0; ++ } ++ ++ if (mempool_end < mempool_start) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_END(%x) must not be before " ++ "__MEMPOOL_START(%x)", ++ mempool_end, ++ mempool_start); ++ success = 0; ++ } ++ ++ if (mempool_offline_end < mempool_offline_start) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_END(%x) must not be before " ++ "__MEMPOOL_OFFLINE_START(%x)", ++ mempool_offline_end, ++ mempool_offline_start); ++ success = 0; ++ } ++ ++ if (mempool_offline_start < mempool_start) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_START(%x) must not be before " ++ "__MEMPOOL_START(%x)", ++ mempool_offline_start, ++ mempool_start); ++ success = 0; ++ } ++ ++ if (mempool_offline_end > mempool_end) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_END(%x) must not be after " ++ "__MEMPOOL_END(%x)", ++ mempool_offline_end, ++ mempool_end); ++ success = 0; ++ } ++ ++ if ((cam_alloc_base < mempool_end) && ++ (cam_alloc_end > mempool_start)) { ++ loud_error_header(); ++ loud_error( ++ "cam_alloc pool(%x-%x) overlaps " ++ "mempool(%x-%x)", ++ cam_alloc_base, cam_alloc_end, ++ mempool_start, mempool_end); ++ success = 0; ++ } ++ ++ loud_error_footer(); ++ ++close: ++ CloseVideoCoreMemory(mem_hndl); ++ ++out: ++ return success; ++} ++#endif ++ ++static int vc_cma_init(void) ++{ ++ int rc = -EFAULT; ++ struct device *dev; ++ ++ if (!check_cma_config()) ++ goto out_release; ++ ++ LOG_INFO("vc-cma: Videocore CMA driver"); ++ LOG_INFO("vc-cma: vc_cma_base = %pa", &vc_cma_base); ++ LOG_INFO("vc-cma: vc_cma_size = 0x%08x (%u MiB)", ++ vc_cma_size, vc_cma_size / (1024 * 1024)); ++ LOG_INFO("vc-cma: vc_cma_initial = 0x%08x (%u MiB)", ++ vc_cma_initial, vc_cma_initial / (1024 * 1024)); ++ ++ vc_cma_base_page = phys_to_page(vc_cma_base); ++ ++ if (vc_cma_chunks) { ++ int chunks_needed = vc_cma_initial / VC_CMA_CHUNK_SIZE; ++ ++ for (vc_cma_chunks_used = 0; ++ vc_cma_chunks_used < chunks_needed; vc_cma_chunks_used++) { ++ struct page *chunk; ++ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev, ++ PAGES_PER_CHUNK, ++ VC_CMA_CHUNK_ORDER); ++ if (!chunk) ++ break; ++ BUG_ON(((page_to_phys(chunk) - vc_cma_base) % ++ VC_CMA_CHUNK_SIZE) != 0); ++ } ++ if (vc_cma_chunks_used != chunks_needed) { ++ LOG_ERR("%s: dma_alloc_from_contiguous failed (%d " ++ "bytes, allocation %d of %d)", ++ __func__, VC_CMA_CHUNK_SIZE, ++ vc_cma_chunks_used, chunks_needed); ++ goto out_release; ++ } ++ ++ vchiq_add_connected_callback(vc_cma_connected_init); ++ } ++ ++ rc = alloc_chrdev_region(&vc_cma_devnum, 0, 1, DRIVER_NAME); ++ if (rc < 0) { ++ LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc); ++ goto out_release; ++ } ++ ++ cdev_init(&vc_cma_cdev, &vc_cma_fops); ++ rc = cdev_add(&vc_cma_cdev, vc_cma_devnum, 1); ++ if (rc != 0) { ++ LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc); ++ goto out_unregister; ++ } ++ ++ vc_cma_class = class_create(THIS_MODULE, DRIVER_NAME); ++ if (IS_ERR(vc_cma_class)) { ++ rc = PTR_ERR(vc_cma_class); ++ LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc); ++ goto out_cdev_del; ++ } ++ ++ dev = device_create(vc_cma_class, NULL, vc_cma_devnum, NULL, ++ DRIVER_NAME); ++ if (IS_ERR(dev)) { ++ rc = PTR_ERR(dev); ++ LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc); ++ goto out_class_destroy; ++ } ++ ++ vc_cma_proc_entry = proc_create(DRIVER_NAME, 0444, NULL, &vc_cma_proc_fops); ++ if (vc_cma_proc_entry == NULL) { ++ rc = -EFAULT; ++ LOG_ERR("%s: proc_create failed", __func__); ++ goto out_device_destroy; ++ } ++ ++ vc_cma_inited = 1; ++ return 0; ++ ++out_device_destroy: ++ device_destroy(vc_cma_class, vc_cma_devnum); ++ ++out_class_destroy: ++ class_destroy(vc_cma_class); ++ vc_cma_class = NULL; ++ ++out_cdev_del: ++ cdev_del(&vc_cma_cdev); ++ ++out_unregister: ++ unregister_chrdev_region(vc_cma_devnum, 1); ++ ++out_release: ++ /* It is tempting to try to clean up by calling ++ dma_release_from_contiguous for all allocated chunks, but it isn't ++ a very safe thing to do. If vc_cma_initial is non-zero it is because ++ VideoCore is already using that memory, so giving it back to Linux ++ is likely to be fatal. ++ */ ++ return -1; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_exit ++* ++***************************************************************************/ ++ ++static void __exit vc_cma_exit(void) ++{ ++ LOG_DBG("%s: called", __func__); ++ ++ if (vc_cma_inited) { ++ remove_proc_entry(DRIVER_NAME, NULL); ++ device_destroy(vc_cma_class, vc_cma_devnum); ++ class_destroy(vc_cma_class); ++ cdev_del(&vc_cma_cdev); ++ unregister_chrdev_region(vc_cma_devnum, 1); ++ } ++} ++ ++module_init(vc_cma_init); ++module_exit(vc_cma_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); +--- /dev/null ++++ b/include/linux/broadcom/vc_cma.h +@@ -0,0 +1,29 @@ ++/***************************************************************************** ++* Copyright 2012 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#if !defined( VC_CMA_H ) ++#define VC_CMA_H ++ ++#include ++ ++#define VC_CMA_IOC_MAGIC 0xc5 ++ ++#define VC_CMA_IOC_RESERVE _IO(VC_CMA_IOC_MAGIC, 0) ++ ++#ifdef __KERNEL__ ++extern void __init vc_cma_early_init(void); ++extern void __init vc_cma_reserve(void); ++#endif ++ ++#endif /* VC_CMA_H */ diff --git a/target/linux/brcm2708/patches-4.1/0011-bcm2708-alsa-sound-driver.patch b/target/linux/brcm2708/patches-4.1/0011-bcm2708-alsa-sound-driver.patch new file mode 100644 index 0000000..5d8eefb --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0011-bcm2708-alsa-sound-driver.patch @@ -0,0 +1,2818 @@ +From 830f064561e1908ba89b9479117b82db07de8c01 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Mon, 26 Mar 2012 22:15:50 +0100 +Subject: [PATCH 011/203] bcm2708: alsa sound driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: popcornmix + +alsa: add mmap support and some cleanups to bcm2835 ALSA driver + +snd-bcm2835: Add support for spdif/hdmi passthrough + +This adds a dedicated subdevice which can be used for passthrough of non-audio +formats (ie encoded a52) through the hdmi audio link. In addition to this +driver extension an appropriate card config is required to make alsa-lib +support the AES parameters for this device. + +snd-bcm2708: Add mutex, improve logging + +Fix for ALSA driver crash + +Avoids an issue when closing and opening vchiq where a message can arrive before service handle has been written + +alsa: reduce severity of expected warning message + +snd-bcm2708: Fix dmesg spam for non-error case + +alsa: Ensure mutexes are released through error paths + +alsa: Make interrupted close paths quieter + +BCM270x: Add onboard sound device to Device Tree + +Add Device Tree support to alsa driver. +Add device to Device Tree. +Don't add platform devices when booting in DT mode. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/mach-bcm2708/bcm2708.c | 53 +++ + arch/arm/mach-bcm2709/bcm2709.c | 53 +++ + sound/arm/Kconfig | 8 + + sound/arm/Makefile | 5 + + sound/arm/bcm2835-ctl.c | 323 +++++++++++++ + sound/arm/bcm2835-pcm.c | 557 +++++++++++++++++++++++ + sound/arm/bcm2835-vchiq.c | 902 +++++++++++++++++++++++++++++++++++++ + sound/arm/bcm2835.c | 511 +++++++++++++++++++++ + sound/arm/bcm2835.h | 167 +++++++ + sound/arm/vc_vchi_audioserv_defs.h | 116 +++++ + 10 files changed, 2695 insertions(+) + create mode 100755 sound/arm/bcm2835-ctl.c + create mode 100755 sound/arm/bcm2835-pcm.c + create mode 100755 sound/arm/bcm2835-vchiq.c + create mode 100644 sound/arm/bcm2835.c + create mode 100755 sound/arm/bcm2835.h + create mode 100644 sound/arm/vc_vchi_audioserv_defs.h + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -429,6 +429,57 @@ struct platform_device bcm2835_emmc_devi + }; + #endif /* CONFIG_MMC_BCM2835 */ + ++static struct platform_device bcm2708_alsa_devices[] = { ++ [0] = { ++ .name = "bcm2835_AUD0", ++ .id = 0, /* first audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [1] = { ++ .name = "bcm2835_AUD1", ++ .id = 1, /* second audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [2] = { ++ .name = "bcm2835_AUD2", ++ .id = 2, /* third audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [3] = { ++ .name = "bcm2835_AUD3", ++ .id = 3, /* forth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [4] = { ++ .name = "bcm2835_AUD4", ++ .id = 4, /* fifth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [5] = { ++ .name = "bcm2835_AUD5", ++ .id = 5, /* sixth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [6] = { ++ .name = "bcm2835_AUD6", ++ .id = 6, /* seventh audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [7] = { ++ .name = "bcm2835_AUD7", ++ .id = 7, /* eighth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++}; ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -571,6 +622,8 @@ void __init bcm2708_init(void) + #endif + bcm2708_init_led(); + bcm2708_init_uart1(); ++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) ++ bcm_register_device_dt(&bcm2708_alsa_devices[i]); + + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -449,6 +449,57 @@ struct platform_device bcm2835_emmc_devi + }; + #endif /* CONFIG_MMC_BCM2835 */ + ++static struct platform_device bcm2708_alsa_devices[] = { ++ [0] = { ++ .name = "bcm2835_AUD0", ++ .id = 0, /* first audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [1] = { ++ .name = "bcm2835_AUD1", ++ .id = 1, /* second audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [2] = { ++ .name = "bcm2835_AUD2", ++ .id = 2, /* third audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [3] = { ++ .name = "bcm2835_AUD3", ++ .id = 3, /* forth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [4] = { ++ .name = "bcm2835_AUD4", ++ .id = 4, /* fifth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [5] = { ++ .name = "bcm2835_AUD5", ++ .id = 5, /* sixth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [6] = { ++ .name = "bcm2835_AUD6", ++ .id = 6, /* seventh audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [7] = { ++ .name = "bcm2835_AUD7", ++ .id = 7, /* eighth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++}; ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -591,6 +642,8 @@ void __init bcm2709_init(void) + #endif + bcm2709_init_led(); + bcm2709_init_uart1(); ++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) ++ bcm_register_device_dt(&bcm2708_alsa_devices[i]); + + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { +--- a/sound/arm/Kconfig ++++ b/sound/arm/Kconfig +@@ -40,5 +40,13 @@ config SND_PXA2XX_AC97 + Say Y or M if you want to support any AC97 codec attached to + the PXA2xx AC97 interface. + ++config SND_BCM2835 ++ tristate "BCM2835 ALSA driver" ++ depends on (ARCH_BCM2708 || ARCH_BCM2709 || ARCH_BCM2835) \ ++ && BCM2708_VCHIQ && SND ++ select SND_PCM ++ help ++ Say Y or M if you want to support BCM2835 Alsa pcm card driver ++ + endif # SND_ARM + +--- a/sound/arm/Makefile ++++ b/sound/arm/Makefile +@@ -14,3 +14,8 @@ snd-pxa2xx-lib-$(CONFIG_SND_PXA2XX_LIB_A + + obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o + snd-pxa2xx-ac97-objs := pxa2xx-ac97.o ++ ++obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o ++snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o ++ ++ccflags-y += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 +--- /dev/null ++++ b/sound/arm/bcm2835-ctl.c +@@ -0,0 +1,323 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "bcm2835.h" ++ ++/* volume maximum and minimum in terms of 0.01dB */ ++#define CTRL_VOL_MAX 400 ++#define CTRL_VOL_MIN -10239 /* originally -10240 */ ++ ++ ++static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ audio_info(" ... IN\n"); ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = CTRL_VOL_MIN; ++ uinfo->value.integer.max = CTRL_VOL_MAX; /* 2303 */ ++ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = 1; ++ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = AUDIO_DEST_MAX-1; ++ } ++ audio_info(" ... OUT\n"); ++ return 0; ++} ++ ++/* toggles mute on or off depending on the value of nmute, and returns ++ * 1 if the mute value was changed, otherwise 0 ++ */ ++static int toggle_mute(struct bcm2835_chip *chip, int nmute) ++{ ++ /* if settings are ok, just return 0 */ ++ if(chip->mute == nmute) ++ return 0; ++ ++ /* if the sound is muted then we need to unmute */ ++ if(chip->mute == CTRL_VOL_MUTE) ++ { ++ chip->volume = chip->old_volume; /* copy the old volume back */ ++ audio_info("Unmuting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume); ++ } ++ else /* otherwise we mute */ ++ { ++ chip->old_volume = chip->volume; ++ chip->volume = 26214; /* set volume to minimum level AKA mute */ ++ audio_info("Muting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume); ++ } ++ ++ chip->mute = nmute; ++ return 1; ++} ++ ++static int snd_bcm2835_ctl_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ ++ BUG_ON(!chip && !(chip->avail_substreams & AVAIL_SUBSTREAMS_MASK)); ++ ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) ++ ucontrol->value.integer.value[0] = chip2alsa(chip->volume); ++ else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) ++ ucontrol->value.integer.value[0] = chip->mute; ++ else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) ++ ucontrol->value.integer.value[0] = chip->dest; ++ ++ return 0; ++} ++ ++static int snd_bcm2835_ctl_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ int changed = 0; ++ ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { ++ audio_info("Volume change attempted.. volume = %d new_volume = %d\n", chip->volume, (int)ucontrol->value.integer.value[0]); ++ if (chip->mute == CTRL_VOL_MUTE) { ++ /* changed = toggle_mute(chip, CTRL_VOL_UNMUTE); */ ++ return 1; /* should return 0 to signify no change but the mixer takes this as the opposite sign (no idea why) */ ++ } ++ if (changed ++ || (ucontrol->value.integer.value[0] != chip2alsa(chip->volume))) { ++ ++ chip->volume = alsa2chip(ucontrol->value.integer.value[0]); ++ changed = 1; ++ } ++ ++ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { ++ /* Now implemented */ ++ audio_info(" Mute attempted\n"); ++ changed = toggle_mute(chip, ucontrol->value.integer.value[0]); ++ ++ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { ++ if (ucontrol->value.integer.value[0] != chip->dest) { ++ chip->dest = ucontrol->value.integer.value[0]; ++ changed = 1; ++ } ++ } ++ ++ if (changed) { ++ if (bcm2835_audio_set_ctls(chip)) ++ printk(KERN_ERR "Failed to set ALSA controls..\n"); ++ } ++ ++ return changed; ++} ++ ++static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, CTRL_VOL_MIN, 1, 1); ++ ++static struct snd_kcontrol_new snd_bcm2835_ctl[] = { ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Volume", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, ++ .private_value = PCM_PLAYBACK_VOLUME, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ .tlv = {.p = snd_bcm2835_db_scale} ++ }, ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Switch", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .private_value = PCM_PLAYBACK_MUTE, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ }, ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Route", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .private_value = PCM_PLAYBACK_DEVICE, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ }, ++}; ++ ++static int snd_bcm2835_spdif_default_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; ++ uinfo->count = 1; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_default_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ int i; ++ ++ for (i = 0; i < 4; i++) ++ ucontrol->value.iec958.status[i] = ++ (chip->spdif_status >> (i * 8)) && 0xff; ++ ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_default_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ unsigned int val = 0; ++ int i, change; ++ ++ for (i = 0; i < 4; i++) ++ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); ++ ++ change = val != chip->spdif_status; ++ chip->spdif_status = val; ++ ++ return change; ++} ++ ++static int snd_bcm2835_spdif_mask_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; ++ uinfo->count = 1; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_mask_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ /* bcm2835 supports only consumer mode and sets all other format flags ++ * automatically. So the only thing left is signalling non-audio ++ * content */ ++ ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_stream_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; ++ uinfo->count = 1; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_stream_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ int i; ++ ++ for (i = 0; i < 4; i++) ++ ucontrol->value.iec958.status[i] = ++ (chip->spdif_status >> (i * 8)) & 0xff; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_stream_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ unsigned int val = 0; ++ int i, change; ++ ++ for (i = 0; i < 4; i++) ++ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); ++ change = val != chip->spdif_status; ++ chip->spdif_status = val; ++ ++ return change; ++} ++ ++static struct snd_kcontrol_new snd_bcm2835_spdif[] = { ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_PCM, ++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), ++ .info = snd_bcm2835_spdif_default_info, ++ .get = snd_bcm2835_spdif_default_get, ++ .put = snd_bcm2835_spdif_default_put ++ }, ++ { ++ .access = SNDRV_CTL_ELEM_ACCESS_READ, ++ .iface = SNDRV_CTL_ELEM_IFACE_PCM, ++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), ++ .info = snd_bcm2835_spdif_mask_info, ++ .get = snd_bcm2835_spdif_mask_get, ++ }, ++ { ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | ++ SNDRV_CTL_ELEM_ACCESS_INACTIVE, ++ .iface = SNDRV_CTL_ELEM_IFACE_PCM, ++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), ++ .info = snd_bcm2835_spdif_stream_info, ++ .get = snd_bcm2835_spdif_stream_get, ++ .put = snd_bcm2835_spdif_stream_put, ++ }, ++}; ++ ++int snd_bcm2835_new_ctl(bcm2835_chip_t * chip) ++{ ++ int err; ++ unsigned int idx; ++ ++ strcpy(chip->card->mixername, "Broadcom Mixer"); ++ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) { ++ err = ++ snd_ctl_add(chip->card, ++ snd_ctl_new1(&snd_bcm2835_ctl[idx], chip)); ++ if (err < 0) ++ return err; ++ } ++ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_spdif); idx++) { ++ err = snd_ctl_add(chip->card, ++ snd_ctl_new1(&snd_bcm2835_spdif[idx], chip)); ++ if (err < 0) ++ return err; ++ } ++ return 0; ++} +--- /dev/null ++++ b/sound/arm/bcm2835-pcm.c +@@ -0,0 +1,557 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++ ++#include ++ ++#include "bcm2835.h" ++ ++/* hardware definition */ ++static struct snd_pcm_hardware snd_bcm2835_playback_hw = { ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID), ++ .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, ++ .rate_min = 8000, ++ .rate_max = 48000, ++ .channels_min = 1, ++ .channels_max = 2, ++ .buffer_bytes_max = 128 * 1024, ++ .period_bytes_min = 1 * 1024, ++ .period_bytes_max = 128 * 1024, ++ .periods_min = 1, ++ .periods_max = 128, ++}; ++ ++static struct snd_pcm_hardware snd_bcm2835_playback_spdif_hw = { ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID), ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 | ++ SNDRV_PCM_RATE_48000, ++ .rate_min = 44100, ++ .rate_max = 48000, ++ .channels_min = 2, ++ .channels_max = 2, ++ .buffer_bytes_max = 128 * 1024, ++ .period_bytes_min = 1 * 1024, ++ .period_bytes_max = 128 * 1024, ++ .periods_min = 1, ++ .periods_max = 128, ++}; ++ ++static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime) ++{ ++ audio_info("Freeing up alsa stream here ..\n"); ++ if (runtime->private_data) ++ kfree(runtime->private_data); ++ runtime->private_data = NULL; ++} ++ ++static irqreturn_t bcm2835_playback_fifo_irq(int irq, void *dev_id) ++{ ++ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *) dev_id; ++ uint32_t consumed = 0; ++ int new_period = 0; ++ ++ audio_info(" .. IN\n"); ++ ++ audio_info("alsa_stream=%p substream=%p\n", alsa_stream, ++ alsa_stream ? alsa_stream->substream : 0); ++ ++ if (alsa_stream->open) ++ consumed = bcm2835_audio_retrieve_buffers(alsa_stream); ++ ++ /* We get called only if playback was triggered, So, the number of buffers we retrieve in ++ * each iteration are the buffers that have been played out already ++ */ ++ ++ if (alsa_stream->period_size) { ++ if ((alsa_stream->pos / alsa_stream->period_size) != ++ ((alsa_stream->pos + consumed) / alsa_stream->period_size)) ++ new_period = 1; ++ } ++ audio_debug("updating pos cur: %d + %d max:%d period_bytes:%d, hw_ptr: %d new_period:%d\n", ++ alsa_stream->pos, ++ consumed, ++ alsa_stream->buffer_size, ++ (int)(alsa_stream->period_size*alsa_stream->substream->runtime->periods), ++ frames_to_bytes(alsa_stream->substream->runtime, alsa_stream->substream->runtime->status->hw_ptr), ++ new_period); ++ if (alsa_stream->buffer_size) { ++ alsa_stream->pos += consumed &~ (1<<30); ++ alsa_stream->pos %= alsa_stream->buffer_size; ++ } ++ ++ if (alsa_stream->substream) { ++ if (new_period) ++ snd_pcm_period_elapsed(alsa_stream->substream); ++ } else { ++ audio_warning(" unexpected NULL substream\n"); ++ } ++ audio_info(" .. OUT\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++/* open callback */ ++static int snd_bcm2835_playback_open_generic( ++ struct snd_pcm_substream *substream, int spdif) ++{ ++ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream); ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int idx; ++ int err; ++ ++ audio_info(" .. IN (%d)\n", substream->number); ++ ++ if(mutex_lock_interruptible(&chip->audio_mutex)) ++ { ++ audio_error("Interrupted whilst waiting for lock\n"); ++ return -EINTR; ++ } ++ audio_info("Alsa open (%d)\n", substream->number); ++ idx = substream->number; ++ ++ if (spdif && chip->opened != 0) { ++ err = -EBUSY; ++ goto out; ++ } ++ else if (!spdif && (chip->opened & (1 << idx))) { ++ err = -EBUSY; ++ goto out; ++ } ++ if (idx > MAX_SUBSTREAMS) { ++ audio_error ++ ("substream(%d) device doesn't exist max(%d) substreams allowed\n", ++ idx, MAX_SUBSTREAMS); ++ err = -ENODEV; ++ goto out; ++ } ++ ++ /* Check if we are ready */ ++ if (!(chip->avail_substreams & (1 << idx))) { ++ /* We are not ready yet */ ++ audio_error("substream(%d) device is not ready yet\n", idx); ++ err = -EAGAIN; ++ goto out; ++ } ++ ++ alsa_stream = kzalloc(sizeof(bcm2835_alsa_stream_t), GFP_KERNEL); ++ if (alsa_stream == NULL) { ++ err = -ENOMEM; ++ goto out; ++ } ++ ++ /* Initialise alsa_stream */ ++ alsa_stream->chip = chip; ++ alsa_stream->substream = substream; ++ alsa_stream->idx = idx; ++ ++ sema_init(&alsa_stream->buffers_update_sem, 0); ++ sema_init(&alsa_stream->control_sem, 0); ++ spin_lock_init(&alsa_stream->lock); ++ ++ /* Enabled in start trigger, called on each "fifo irq" after that */ ++ alsa_stream->enable_fifo_irq = 0; ++ alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq; ++ ++ err = bcm2835_audio_open(alsa_stream); ++ if (err != 0) { ++ kfree(alsa_stream); ++ goto out; ++ } ++ runtime->private_data = alsa_stream; ++ runtime->private_free = snd_bcm2835_playback_free; ++ if (spdif) { ++ runtime->hw = snd_bcm2835_playback_spdif_hw; ++ } else { ++ /* clear spdif status, as we are not in spdif mode */ ++ chip->spdif_status = 0; ++ runtime->hw = snd_bcm2835_playback_hw; ++ } ++ /* minimum 16 bytes alignment (for vchiq bulk transfers) */ ++ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, ++ 16); ++ ++ chip->alsa_stream[idx] = alsa_stream; ++ ++ chip->opened |= (1 << idx); ++ alsa_stream->open = 1; ++ alsa_stream->draining = 1; ++ ++out: ++ mutex_unlock(&chip->audio_mutex); ++ ++ audio_info(" .. OUT =%d\n", err); ++ ++ return err; ++} ++ ++static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream) ++{ ++ return snd_bcm2835_playback_open_generic(substream, 0); ++} ++ ++static int snd_bcm2835_playback_spdif_open(struct snd_pcm_substream *substream) ++{ ++ return snd_bcm2835_playback_open_generic(substream, 1); ++} ++ ++/* close callback */ ++static int snd_bcm2835_playback_close(struct snd_pcm_substream *substream) ++{ ++ /* the hardware-specific codes will be here */ ++ ++ bcm2835_chip_t *chip; ++ struct snd_pcm_runtime *runtime; ++ bcm2835_alsa_stream_t *alsa_stream; ++ ++ audio_info(" .. IN\n"); ++ ++ chip = snd_pcm_substream_chip(substream); ++ if(mutex_lock_interruptible(&chip->audio_mutex)) ++ { ++ audio_error("Interrupted whilst waiting for lock\n"); ++ return -EINTR; ++ } ++ runtime = substream->runtime; ++ alsa_stream = runtime->private_data; ++ ++ audio_info("Alsa close\n"); ++ ++ /* ++ * Call stop if it's still running. This happens when app ++ * is force killed and we don't get a stop trigger. ++ */ ++ if (alsa_stream->running) { ++ int err; ++ err = bcm2835_audio_stop(alsa_stream); ++ alsa_stream->running = 0; ++ if (err != 0) ++ audio_error(" Failed to STOP alsa device\n"); ++ } ++ ++ alsa_stream->period_size = 0; ++ alsa_stream->buffer_size = 0; ++ ++ if (alsa_stream->open) { ++ alsa_stream->open = 0; ++ bcm2835_audio_close(alsa_stream); ++ } ++ if (alsa_stream->chip) ++ alsa_stream->chip->alsa_stream[alsa_stream->idx] = NULL; ++ /* ++ * Do not free up alsa_stream here, it will be freed up by ++ * runtime->private_free callback we registered in *_open above ++ */ ++ ++ chip->opened &= ~(1 << substream->number); ++ ++ mutex_unlock(&chip->audio_mutex); ++ audio_info(" .. OUT\n"); ++ ++ return 0; ++} ++ ++/* hw_params callback */ ++static int snd_bcm2835_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ int err; ++ ++ audio_info(" .. IN\n"); ++ ++ err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); ++ if (err < 0) { ++ audio_error ++ (" pcm_lib_malloc failed to allocated pages for buffers\n"); ++ return err; ++ } ++ ++ alsa_stream->channels = params_channels(params); ++ alsa_stream->params_rate = params_rate(params); ++ alsa_stream->pcm_format_width = snd_pcm_format_width(params_format (params)); ++ audio_info(" .. OUT\n"); ++ ++ return err; ++} ++ ++/* hw_free callback */ ++static int snd_bcm2835_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ audio_info(" .. IN\n"); ++ return snd_pcm_lib_free_pages(substream); ++} ++ ++/* prepare callback */ ++static int snd_bcm2835_pcm_prepare(struct snd_pcm_substream *substream) ++{ ++ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream); ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ int channels; ++ int err; ++ ++ audio_info(" .. IN\n"); ++ ++ /* notify the vchiq that it should enter spdif passthrough mode by ++ * setting channels=0 (see ++ * https://github.com/raspberrypi/linux/issues/528) */ ++ if (chip->spdif_status & IEC958_AES0_NONAUDIO) ++ channels = 0; ++ else ++ channels = alsa_stream->channels; ++ ++ err = bcm2835_audio_set_params(alsa_stream, channels, ++ alsa_stream->params_rate, ++ alsa_stream->pcm_format_width); ++ if (err < 0) { ++ audio_error(" error setting hw params\n"); ++ } ++ ++ bcm2835_audio_setup(alsa_stream); ++ ++ /* in preparation of the stream, set the controls (volume level) of the stream */ ++ bcm2835_audio_set_ctls(alsa_stream->chip); ++ ++ ++ memset(&alsa_stream->pcm_indirect, 0, sizeof(alsa_stream->pcm_indirect)); ++ ++ alsa_stream->pcm_indirect.hw_buffer_size = ++ alsa_stream->pcm_indirect.sw_buffer_size = ++ snd_pcm_lib_buffer_bytes(substream); ++ ++ alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream); ++ alsa_stream->period_size = snd_pcm_lib_period_bytes(substream); ++ alsa_stream->pos = 0; ++ ++ audio_debug("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n", ++ alsa_stream->buffer_size, alsa_stream->period_size, ++ alsa_stream->pos, runtime->frame_bits); ++ ++ audio_info(" .. OUT\n"); ++ return 0; ++} ++ ++static void snd_bcm2835_pcm_transfer(struct snd_pcm_substream *substream, ++ struct snd_pcm_indirect *rec, size_t bytes) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ void *src = (void *)(substream->runtime->dma_area + rec->sw_data); ++ int err; ++ ++ err = bcm2835_audio_write(alsa_stream, bytes, src); ++ if (err) ++ audio_error(" Failed to transfer to alsa device (%d)\n", err); ++ ++} ++ ++static int snd_bcm2835_pcm_ack(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ struct snd_pcm_indirect *pcm_indirect = &alsa_stream->pcm_indirect; ++ ++ pcm_indirect->hw_queue_size = runtime->hw.buffer_bytes_max; ++ snd_pcm_indirect_playback_transfer(substream, pcm_indirect, ++ snd_bcm2835_pcm_transfer); ++ return 0; ++} ++ ++/* trigger callback */ ++static int snd_bcm2835_pcm_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ int err = 0; ++ ++ audio_info(" .. IN\n"); ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ audio_debug("bcm2835_AUDIO_TRIGGER_START running=%d\n", ++ alsa_stream->running); ++ if (!alsa_stream->running) { ++ err = bcm2835_audio_start(alsa_stream); ++ if (err == 0) { ++ alsa_stream->pcm_indirect.hw_io = ++ alsa_stream->pcm_indirect.hw_data = ++ bytes_to_frames(runtime, ++ alsa_stream->pos); ++ substream->ops->ack(substream); ++ alsa_stream->running = 1; ++ alsa_stream->draining = 1; ++ } else { ++ audio_error(" Failed to START alsa device (%d)\n", err); ++ } ++ } ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ audio_debug ++ ("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n", ++ alsa_stream->running, runtime->status->state == SNDRV_PCM_STATE_DRAINING); ++ if (runtime->status->state == SNDRV_PCM_STATE_DRAINING) { ++ audio_info("DRAINING\n"); ++ alsa_stream->draining = 1; ++ } else { ++ audio_info("DROPPING\n"); ++ alsa_stream->draining = 0; ++ } ++ if (alsa_stream->running) { ++ err = bcm2835_audio_stop(alsa_stream); ++ if (err != 0) ++ audio_error(" Failed to STOP alsa device (%d)\n", err); ++ alsa_stream->running = 0; ++ } ++ break; ++ default: ++ err = -EINVAL; ++ } ++ ++ audio_info(" .. OUT\n"); ++ return err; ++} ++ ++/* pointer callback */ ++static snd_pcm_uframes_t ++snd_bcm2835_pcm_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ ++ audio_info(" .. IN\n"); ++ ++ audio_debug("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0, ++ frames_to_bytes(runtime, runtime->status->hw_ptr), ++ frames_to_bytes(runtime, runtime->control->appl_ptr), ++ alsa_stream->pos); ++ ++ audio_info(" .. OUT\n"); ++ return snd_pcm_indirect_playback_pointer(substream, ++ &alsa_stream->pcm_indirect, ++ alsa_stream->pos); ++} ++ ++static int snd_bcm2835_pcm_lib_ioctl(struct snd_pcm_substream *substream, ++ unsigned int cmd, void *arg) ++{ ++ int ret = snd_pcm_lib_ioctl(substream, cmd, arg); ++ audio_info(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream, ++ cmd, arg, arg ? *(unsigned *)arg : 0, ret); ++ return ret; ++} ++ ++/* operators */ ++static struct snd_pcm_ops snd_bcm2835_playback_ops = { ++ .open = snd_bcm2835_playback_open, ++ .close = snd_bcm2835_playback_close, ++ .ioctl = snd_bcm2835_pcm_lib_ioctl, ++ .hw_params = snd_bcm2835_pcm_hw_params, ++ .hw_free = snd_bcm2835_pcm_hw_free, ++ .prepare = snd_bcm2835_pcm_prepare, ++ .trigger = snd_bcm2835_pcm_trigger, ++ .pointer = snd_bcm2835_pcm_pointer, ++ .ack = snd_bcm2835_pcm_ack, ++}; ++ ++static struct snd_pcm_ops snd_bcm2835_playback_spdif_ops = { ++ .open = snd_bcm2835_playback_spdif_open, ++ .close = snd_bcm2835_playback_close, ++ .ioctl = snd_bcm2835_pcm_lib_ioctl, ++ .hw_params = snd_bcm2835_pcm_hw_params, ++ .hw_free = snd_bcm2835_pcm_hw_free, ++ .prepare = snd_bcm2835_pcm_prepare, ++ .trigger = snd_bcm2835_pcm_trigger, ++ .pointer = snd_bcm2835_pcm_pointer, ++ .ack = snd_bcm2835_pcm_ack, ++}; ++ ++/* create a pcm device */ ++int snd_bcm2835_new_pcm(bcm2835_chip_t * chip) ++{ ++ struct snd_pcm *pcm; ++ int err; ++ ++ audio_info(" .. IN\n"); ++ mutex_init(&chip->audio_mutex); ++ if(mutex_lock_interruptible(&chip->audio_mutex)) ++ { ++ audio_error("Interrupted whilst waiting for lock\n"); ++ return -EINTR; ++ } ++ err = ++ snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm); ++ if (err < 0) ++ goto out; ++ pcm->private_data = chip; ++ strcpy(pcm->name, "bcm2835 ALSA"); ++ chip->pcm = pcm; ++ chip->dest = AUDIO_DEST_AUTO; ++ chip->volume = alsa2chip(0); ++ chip->mute = CTRL_VOL_UNMUTE; /*disable mute on startup */ ++ /* set operators */ ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, ++ &snd_bcm2835_playback_ops); ++ ++ /* pre-allocation of buffers */ ++ /* NOTE: this may fail */ ++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, ++ snd_dma_continuous_data ++ (GFP_KERNEL), 64 * 1024, ++ 64 * 1024); ++ ++out: ++ mutex_unlock(&chip->audio_mutex); ++ audio_info(" .. OUT\n"); ++ ++ return 0; ++} ++ ++int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip) ++{ ++ struct snd_pcm *pcm; ++ int err; ++ ++ audio_info(" .. IN\n"); ++ if(mutex_lock_interruptible(&chip->audio_mutex)) ++ { ++ audio_error("Interrupted whilst waiting for lock\n"); ++ return -EINTR; ++ } ++ err = snd_pcm_new(chip->card, "bcm2835 ALSA", 1, 1, 0, &pcm); ++ if (err < 0) ++ goto out; ++ ++ pcm->private_data = chip; ++ strcpy(pcm->name, "bcm2835 IEC958/HDMI"); ++ chip->pcm_spdif = pcm; ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, ++ &snd_bcm2835_playback_spdif_ops); ++ ++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, ++ snd_dma_continuous_data (GFP_KERNEL), ++ 64 * 1024, 64 * 1024); ++out: ++ mutex_unlock(&chip->audio_mutex); ++ audio_info(" .. OUT\n"); ++ ++ return 0; ++} +--- /dev/null ++++ b/sound/arm/bcm2835-vchiq.c +@@ -0,0 +1,902 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "bcm2835.h" ++ ++/* ---- Include Files -------------------------------------------------------- */ ++ ++#include "interface/vchi/vchi.h" ++#include "vc_vchi_audioserv_defs.h" ++ ++/* ---- Private Constants and Types ------------------------------------------ */ ++ ++#define BCM2835_AUDIO_STOP 0 ++#define BCM2835_AUDIO_START 1 ++#define BCM2835_AUDIO_WRITE 2 ++ ++/* Logging macros (for remapping to other logging mechanisms, i.e., printf) */ ++#ifdef AUDIO_DEBUG_ENABLE ++ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_WARN( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_INFO( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_DBG( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++#else ++ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_WARN( fmt, arg... ) ++ #define LOG_INFO( fmt, arg... ) ++ #define LOG_DBG( fmt, arg... ) ++#endif ++ ++typedef struct opaque_AUDIO_INSTANCE_T { ++ uint32_t num_connections; ++ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS]; ++ struct completion msg_avail_comp; ++ struct mutex vchi_mutex; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int32_t result; ++ short peer_version; ++} AUDIO_INSTANCE_T; ++ ++bool force_bulk = false; ++ ++/* ---- Private Variables ---------------------------------------------------- */ ++ ++/* ---- Private Function Prototypes ------------------------------------------ */ ++ ++/* ---- Private Functions ---------------------------------------------------- */ ++ ++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream); ++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream); ++static int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream, ++ uint32_t count, void *src); ++ ++typedef struct { ++ struct work_struct my_work; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int cmd; ++ void *src; ++ uint32_t count; ++} my_work_t; ++ ++static void my_wq_function(struct work_struct *work) ++{ ++ my_work_t *w = (my_work_t *) work; ++ int ret = -9; ++ LOG_DBG(" .. IN %p:%d\n", w->alsa_stream, w->cmd); ++ switch (w->cmd) { ++ case BCM2835_AUDIO_START: ++ ret = bcm2835_audio_start_worker(w->alsa_stream); ++ break; ++ case BCM2835_AUDIO_STOP: ++ ret = bcm2835_audio_stop_worker(w->alsa_stream); ++ break; ++ case BCM2835_AUDIO_WRITE: ++ ret = bcm2835_audio_write_worker(w->alsa_stream, w->count, ++ w->src); ++ break; ++ default: ++ LOG_ERR(" Unexpected work: %p:%d\n", w->alsa_stream, w->cmd); ++ break; ++ } ++ kfree((void *)work); ++ LOG_DBG(" .. OUT %d\n", ret); ++} ++ ++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ int ret = -1; ++ LOG_DBG(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); ++ /*--- Queue some work (item 1) ---*/ ++ if (work) { ++ INIT_WORK((struct work_struct *)work, my_wq_function); ++ work->alsa_stream = alsa_stream; ++ work->cmd = BCM2835_AUDIO_START; ++ if (queue_work ++ (alsa_stream->my_wq, (struct work_struct *)work)) ++ ret = 0; ++ } else ++ LOG_ERR(" .. Error: NULL work kmalloc\n"); ++ } ++ LOG_DBG(" .. OUT %d\n", ret); ++ return ret; ++} ++ ++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ int ret = -1; ++ LOG_DBG(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); ++ /*--- Queue some work (item 1) ---*/ ++ if (work) { ++ INIT_WORK((struct work_struct *)work, my_wq_function); ++ work->alsa_stream = alsa_stream; ++ work->cmd = BCM2835_AUDIO_STOP; ++ if (queue_work ++ (alsa_stream->my_wq, (struct work_struct *)work)) ++ ret = 0; ++ } else ++ LOG_ERR(" .. Error: NULL work kmalloc\n"); ++ } ++ LOG_DBG(" .. OUT %d\n", ret); ++ return ret; ++} ++ ++int bcm2835_audio_write(bcm2835_alsa_stream_t *alsa_stream, ++ uint32_t count, void *src) ++{ ++ int ret = -1; ++ LOG_DBG(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); ++ /*--- Queue some work (item 1) ---*/ ++ if (work) { ++ INIT_WORK((struct work_struct *)work, my_wq_function); ++ work->alsa_stream = alsa_stream; ++ work->cmd = BCM2835_AUDIO_WRITE; ++ work->src = src; ++ work->count = count; ++ if (queue_work ++ (alsa_stream->my_wq, (struct work_struct *)work)) ++ ret = 0; ++ } else ++ LOG_ERR(" .. Error: NULL work kmalloc\n"); ++ } ++ LOG_DBG(" .. OUT %d\n", ret); ++ return ret; ++} ++ ++void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ alsa_stream->my_wq = alloc_workqueue("my_queue", WQ_HIGHPRI, 1); ++ return; ++} ++ ++void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ if (alsa_stream->my_wq) { ++ flush_workqueue(alsa_stream->my_wq); ++ destroy_workqueue(alsa_stream->my_wq); ++ alsa_stream->my_wq = NULL; ++ } ++ return; ++} ++ ++static void audio_vchi_callback(void *param, ++ const VCHI_CALLBACK_REASON_T reason, ++ void *msg_handle) ++{ ++ AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *) param; ++ int32_t status; ++ int32_t msg_len; ++ VC_AUDIO_MSG_T m; ++ LOG_DBG(" .. IN instance=%p, handle=%p, alsa=%p, reason=%d, handle=%p\n", ++ instance, instance ? instance->vchi_handle[0] : NULL, instance ? instance->alsa_stream : NULL, reason, msg_handle); ++ ++ if (reason != VCHI_CALLBACK_MSG_AVAILABLE) { ++ return; ++ } ++ if (!instance) { ++ LOG_ERR(" .. instance is null\n"); ++ BUG(); ++ return; ++ } ++ if (!instance->vchi_handle[0]) { ++ LOG_ERR(" .. instance->vchi_handle[0] is null\n"); ++ BUG(); ++ return; ++ } ++ status = vchi_msg_dequeue(instance->vchi_handle[0], ++ &m, sizeof m, &msg_len, VCHI_FLAGS_NONE); ++ if (m.type == VC_AUDIO_MSG_TYPE_RESULT) { ++ LOG_DBG ++ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n", ++ instance, m.u.result.success); ++ instance->result = m.u.result.success; ++ complete(&instance->msg_avail_comp); ++ } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) { ++ bcm2835_alsa_stream_t *alsa_stream = instance->alsa_stream; ++ irq_handler_t callback = (irq_handler_t) m.u.complete.callback; ++ LOG_DBG ++ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n", ++ instance, m.u.complete.count); ++ if (alsa_stream && callback) { ++ atomic_add(m.u.complete.count, &alsa_stream->retrieved); ++ callback(0, alsa_stream); ++ } else { ++ LOG_ERR(" .. unexpected alsa_stream=%p, callback=%p\n", ++ alsa_stream, callback); ++ } ++ } else { ++ LOG_ERR(" .. unexpected m.type=%d\n", m.type); ++ } ++ LOG_DBG(" .. OUT\n"); ++} ++ ++static AUDIO_INSTANCE_T *vc_vchi_audio_init(VCHI_INSTANCE_T vchi_instance, ++ VCHI_CONNECTION_T ** ++ vchi_connections, ++ uint32_t num_connections) ++{ ++ uint32_t i; ++ AUDIO_INSTANCE_T *instance; ++ int status; ++ ++ LOG_DBG("%s: start", __func__); ++ ++ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) { ++ LOG_ERR("%s: unsupported number of connections %u (max=%u)\n", ++ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS); ++ ++ return NULL; ++ } ++ /* Allocate memory for this instance */ ++ instance = kmalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) ++ return NULL; ++ ++ memset(instance, 0, sizeof(*instance)); ++ instance->num_connections = num_connections; ++ ++ /* Create a lock for exclusive, serialized VCHI connection access */ ++ mutex_init(&instance->vchi_mutex); ++ /* Open the VCHI service connections */ ++ for (i = 0; i < num_connections; i++) { ++ SERVICE_CREATION_T params = { ++ VCHI_VERSION_EX(VC_AUDIOSERV_VER, VC_AUDIOSERV_MIN_VER), ++ VC_AUDIO_SERVER_NAME, // 4cc service code ++ vchi_connections[i], // passed in fn pointers ++ 0, // rx fifo size (unused) ++ 0, // tx fifo size (unused) ++ audio_vchi_callback, // service callback ++ instance, // service callback parameter ++ 1, //TODO: remove VCOS_FALSE, // unaligned bulk recieves ++ 1, //TODO: remove VCOS_FALSE, // unaligned bulk transmits ++ 0 // want crc check on bulk transfers ++ }; ++ ++ LOG_DBG("%s: about to open %i\n", __func__, i); ++ status = vchi_service_open(vchi_instance, ¶ms, ++ &instance->vchi_handle[i]); ++ LOG_DBG("%s: opened %i: %p=%d\n", __func__, i, instance->vchi_handle[i], status); ++ if (status) { ++ LOG_ERR ++ ("%s: failed to open VCHI service connection (status=%d)\n", ++ __func__, status); ++ ++ goto err_close_services; ++ } ++ /* Finished with the service for now */ ++ vchi_service_release(instance->vchi_handle[i]); ++ } ++ ++ LOG_DBG("%s: okay\n", __func__); ++ return instance; ++ ++err_close_services: ++ for (i = 0; i < instance->num_connections; i++) { ++ LOG_ERR("%s: closing %i: %p\n", __func__, i, instance->vchi_handle[i]); ++ if (instance->vchi_handle[i]) ++ vchi_service_close(instance->vchi_handle[i]); ++ } ++ ++ kfree(instance); ++ LOG_ERR("%s: error\n", __func__); ++ ++ return NULL; ++} ++ ++static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T * instance) ++{ ++ uint32_t i; ++ ++ LOG_DBG(" .. IN\n"); ++ ++ if (instance == NULL) { ++ LOG_ERR("%s: invalid handle %p\n", __func__, instance); ++ ++ return -1; ++ } ++ ++ LOG_DBG(" .. about to lock (%d)\n", instance->num_connections); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ ++ /* Close all VCHI service connections */ ++ for (i = 0; i < instance->num_connections; i++) { ++ int32_t success; ++ LOG_DBG(" .. %i:closing %p\n", i, instance->vchi_handle[i]); ++ vchi_service_use(instance->vchi_handle[i]); ++ ++ success = vchi_service_close(instance->vchi_handle[i]); ++ if (success != 0) { ++ LOG_DBG ++ ("%s: failed to close VCHI service connection (status=%d)\n", ++ __func__, success); ++ } ++ } ++ ++ mutex_unlock(&instance->vchi_mutex); ++ ++ kfree(instance); ++ ++ LOG_DBG(" .. OUT\n"); ++ ++ return 0; ++} ++ ++static int bcm2835_audio_open_connection(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ static VCHI_INSTANCE_T vchi_instance; ++ static VCHI_CONNECTION_T *vchi_connection; ++ static int initted; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO("%s: start\n", __func__); ++ BUG_ON(instance); ++ if (instance) { ++ LOG_ERR("%s: VCHI instance already open (%p)\n", ++ __func__, instance); ++ instance->alsa_stream = alsa_stream; ++ alsa_stream->instance = instance; ++ ret = 0; // xxx todo -1; ++ goto err_free_mem; ++ } ++ ++ /* Initialize and create a VCHI connection */ ++ if (!initted) { ++ ret = vchi_initialise(&vchi_instance); ++ if (ret != 0) { ++ LOG_ERR("%s: failed to initialise VCHI instance (ret=%d)\n", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ ret = vchi_connect(NULL, 0, vchi_instance); ++ if (ret != 0) { ++ LOG_ERR("%s: failed to connect VCHI instance (ret=%d)\n", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ initted = 1; ++ } ++ ++ /* Initialize an instance of the audio service */ ++ instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1); ++ ++ if (instance == NULL) { ++ LOG_ERR("%s: failed to initialize audio service\n", __func__); ++ ++ ret = -EPERM; ++ goto err_free_mem; ++ } ++ ++ instance->alsa_stream = alsa_stream; ++ alsa_stream->instance = instance; ++ ++ LOG_DBG(" success !\n"); ++err_free_mem: ++ LOG_DBG(" .. OUT\n"); ++ ++ return ret; ++} ++ ++int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ AUDIO_INSTANCE_T *instance; ++ VC_AUDIO_MSG_T m; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ my_workqueue_init(alsa_stream); ++ ++ ret = bcm2835_audio_open_connection(alsa_stream); ++ if (ret != 0) { ++ ret = -1; ++ goto exit; ++ } ++ instance = alsa_stream->instance; ++ LOG_DBG(" instance (%p)\n", instance); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_OPEN; ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++exit: ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t * alsa_stream, ++ bcm2835_chip_t * chip) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO ++ (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ instance->result = -1; ++ ++ m.type = VC_AUDIO_MSG_TYPE_CONTROL; ++ m.u.control.dest = chip->dest; ++ m.u.control.volume = chip->volume; ++ ++ /* Create the message available completion */ ++ init_completion(&instance->msg_avail_comp); ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ /* We are expecting a reply from the videocore */ ++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); ++ if (ret) { ++ LOG_DBG("%s: failed on waiting for event (status=%d)\n", ++ __func__, success); ++ goto unlock; ++ } ++ ++ if (instance->result != 0) { ++ LOG_ERR("%s: result=%d\n", __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_set_ctls(bcm2835_chip_t * chip) ++{ ++ int i; ++ int ret = 0; ++ LOG_DBG(" .. IN\n"); ++ LOG_DBG(" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); ++ ++ /* change ctls for all substreams */ ++ for (i = 0; i < MAX_SUBSTREAMS; i++) { ++ if (chip->avail_substreams & (1 << i)) { ++ if (!chip->alsa_stream[i]) ++ { ++ LOG_DBG(" No ALSA stream available?! %i:%p (%x)\n", i, chip->alsa_stream[i], chip->avail_substreams); ++ ret = 0; ++ } ++ else if (bcm2835_audio_set_ctls_chan /* returns 0 on success */ ++ (chip->alsa_stream[i], chip) != 0) ++ { ++ LOG_ERR("Couldn't set the controls for stream %d\n", i); ++ ret = -1; ++ } ++ else LOG_DBG(" Controls set for stream %d\n", i); ++ } ++ } ++ LOG_DBG(" .. OUT ret=%d\n", ret); ++ return ret; ++} ++ ++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, ++ uint32_t channels, uint32_t samplerate, ++ uint32_t bps) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO ++ (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n", ++ channels, samplerate, bps); ++ ++ /* resend ctls - alsa_stream may not have been open when first send */ ++ ret = bcm2835_audio_set_ctls_chan(alsa_stream, alsa_stream->chip); ++ if (ret != 0) { ++ LOG_ERR(" Alsa controls not supported\n"); ++ return -EINVAL; ++ } ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ instance->result = -1; ++ ++ m.type = VC_AUDIO_MSG_TYPE_CONFIG; ++ m.u.config.channels = channels; ++ m.u.config.samplerate = samplerate; ++ m.u.config.bps = bps; ++ ++ /* Create the message available completion */ ++ init_completion(&instance->msg_avail_comp); ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ /* We are expecting a reply from the videocore */ ++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); ++ if (ret) { ++ LOG_DBG("%s: failed on waiting for event (status=%d)\n", ++ __func__, success); ++ goto unlock; ++ } ++ ++ if (instance->result != 0) { ++ LOG_ERR("%s: result=%d", __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_DBG(" .. OUT\n"); ++ ++ return 0; ++} ++ ++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_START; ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_STOP; ++ m.u.stop.draining = alsa_stream->draining; ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ my_workqueue_quit(alsa_stream); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_CLOSE; ++ ++ /* Create the message available completion */ ++ init_completion(&instance->msg_avail_comp); ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); ++ if (ret) { ++ LOG_DBG("%s: failed on waiting for event (status=%d)\n", ++ __func__, success); ++ goto unlock; ++ } ++ if (instance->result != 0) { ++ LOG_ERR("%s: failed result (status=%d)\n", ++ __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ ++ /* Stop the audio service */ ++ if (instance) { ++ vc_vchi_audio_deinit(instance); ++ alsa_stream->instance = NULL; ++ } ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream, ++ uint32_t count, void *src) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO(" Writing %d bytes from %p\n", count, src); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ if ( instance->peer_version==0 && vchi_get_peer_version(instance->vchi_handle[0], &instance->peer_version) == 0 ) { ++ LOG_DBG("%s: client version %d connected\n", __func__, instance->peer_version); ++ } ++ m.type = VC_AUDIO_MSG_TYPE_WRITE; ++ m.u.write.count = count; ++ // old version uses bulk, new version uses control ++ m.u.write.max_packet = instance->peer_version < 2 || force_bulk ? 0:4000; ++ m.u.write.callback = alsa_stream->fifo_irq_handler; ++ m.u.write.cookie = alsa_stream; ++ m.u.write.silence = src == NULL; ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ if (!m.u.write.silence) { ++ if (m.u.write.max_packet == 0) { ++ /* Send the message to the videocore */ ++ success = vchi_bulk_queue_transmit(instance->vchi_handle[0], ++ src, count, ++ 0 * ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED ++ + ++ 1 * ++ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ, ++ NULL); ++ } else { ++ while (count > 0) { ++ int bytes = min((int)m.u.write.max_packet, (int)count); ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ src, bytes, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ src = (char *)src + bytes; ++ count -= bytes; ++ } ++ } ++ if (success != 0) { ++ LOG_ERR ++ ("%s: failed on vchi_bulk_queue_transmit (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ } ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++/** ++ * Returns all buffers from arm->vc ++ */ ++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ LOG_DBG(" .. IN\n"); ++ LOG_DBG(" .. OUT\n"); ++ return; ++} ++ ++/** ++ * Forces VC to flush(drop) its filled playback buffers and ++ * return them the us. (VC->ARM) ++ */ ++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ LOG_DBG(" .. IN\n"); ++ LOG_DBG(" .. OUT\n"); ++} ++ ++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ uint32_t count = atomic_read(&alsa_stream->retrieved); ++ atomic_sub(count, &alsa_stream->retrieved); ++ return count; ++} ++ ++module_param(force_bulk, bool, 0444); ++MODULE_PARM_DESC(force_bulk, "Force use of vchiq bulk for audio"); +--- /dev/null ++++ b/sound/arm/bcm2835.c +@@ -0,0 +1,511 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "bcm2835.h" ++ ++/* module parameters (see "Module Parameters") */ ++/* SNDRV_CARDS: maximum number of cards supported by this module */ ++static int index[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = -1 }; ++static char *id[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = NULL }; ++static int enable[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = 1 }; ++ ++/* HACKY global pointers needed for successive probes to work : ssp ++ * But compared against the changes we will have to do in VC audio_ipc code ++ * to export 8 audio_ipc devices as a single IPC device and then monitor all ++ * four devices in a thread, this gets things done quickly and should be easier ++ * to debug if we run into issues ++ */ ++ ++static struct snd_card *g_card = NULL; ++static bcm2835_chip_t *g_chip = NULL; ++ ++static int snd_bcm2835_free(bcm2835_chip_t * chip) ++{ ++ kfree(chip); ++ return 0; ++} ++ ++/* component-destructor ++ * (see "Management of Cards and Components") ++ */ ++static int snd_bcm2835_dev_free(struct snd_device *device) ++{ ++ return snd_bcm2835_free(device->device_data); ++} ++ ++/* chip-specific constructor ++ * (see "Management of Cards and Components") ++ */ ++static int snd_bcm2835_create(struct snd_card *card, ++ struct platform_device *pdev, ++ bcm2835_chip_t ** rchip) ++{ ++ bcm2835_chip_t *chip; ++ int err; ++ static struct snd_device_ops ops = { ++ .dev_free = snd_bcm2835_dev_free, ++ }; ++ ++ *rchip = NULL; ++ ++ chip = kzalloc(sizeof(*chip), GFP_KERNEL); ++ if (chip == NULL) ++ return -ENOMEM; ++ ++ chip->card = card; ++ ++ err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); ++ if (err < 0) { ++ snd_bcm2835_free(chip); ++ return err; ++ } ++ ++ *rchip = chip; ++ return 0; ++} ++ ++static int snd_bcm2835_alsa_probe_dt(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ bcm2835_chip_t *chip; ++ struct snd_card *card; ++ u32 numchans; ++ int err, i; ++ ++ err = of_property_read_u32(dev->of_node, "brcm,pwm-channels", ++ &numchans); ++ if (err) { ++ dev_err(dev, "Failed to get DT property 'brcm,pwm-channels'"); ++ return err; ++ } ++ ++ if (numchans == 0 || numchans > MAX_SUBSTREAMS) { ++ numchans = MAX_SUBSTREAMS; ++ dev_warn(dev, "Illegal 'brcm,pwm-channels' value, will use %u\n", ++ numchans); ++ } ++ ++ err = snd_card_new(NULL, -1, NULL, THIS_MODULE, 0, &card); ++ if (err) { ++ dev_err(dev, "Failed to create soundcard structure\n"); ++ return err; ++ } ++ ++ snd_card_set_dev(card, dev); ++ strcpy(card->driver, "bcm2835"); ++ strcpy(card->shortname, "bcm2835 ALSA"); ++ sprintf(card->longname, "%s", card->shortname); ++ ++ err = snd_bcm2835_create(card, pdev, &chip); ++ if (err < 0) { ++ dev_err(dev, "Failed to create bcm2835 chip\n"); ++ goto err_free; ++ } ++ ++ err = snd_bcm2835_new_pcm(chip); ++ if (err < 0) { ++ dev_err(dev, "Failed to create new bcm2835 pcm device\n"); ++ goto err_free; ++ } ++ ++ err = snd_bcm2835_new_spdif_pcm(chip); ++ if (err < 0) { ++ dev_err(dev, "Failed to create new bcm2835 spdif pcm device\n"); ++ goto err_free; ++ } ++ ++ err = snd_bcm2835_new_ctl(chip); ++ if (err < 0) { ++ dev_err(dev, "Failed to create new bcm2835 ctl\n"); ++ goto err_free; ++ } ++ ++ for (i = 0; i < numchans; i++) { ++ chip->avail_substreams |= (1 << i); ++ chip->pdev[i] = pdev; ++ } ++ ++ err = snd_card_register(card); ++ if (err) { ++ dev_err(dev, "Failed to register bcm2835 ALSA card \n"); ++ goto err_free; ++ } ++ ++ g_card = card; ++ g_chip = chip; ++ platform_set_drvdata(pdev, card); ++ audio_info("bcm2835 ALSA card created with %u channels\n", numchans); ++ ++ return 0; ++ ++err_free: ++ snd_card_free(card); ++ ++ return err; ++} ++ ++static int snd_bcm2835_alsa_probe(struct platform_device *pdev) ++{ ++ static int dev; ++ bcm2835_chip_t *chip; ++ struct snd_card *card; ++ int err; ++ ++ if (pdev->dev.of_node) ++ return snd_bcm2835_alsa_probe_dt(pdev); ++ ++ if (dev >= MAX_SUBSTREAMS) ++ return -ENODEV; ++ ++ if (!enable[dev]) { ++ dev++; ++ return -ENOENT; ++ } ++ ++ if (dev > 0) ++ goto add_register_map; ++ ++ err = snd_card_new(NULL, index[dev], id[dev], THIS_MODULE, 0, &g_card); ++ if (err < 0) ++ goto out; ++ ++ snd_card_set_dev(g_card, &pdev->dev); ++ strcpy(g_card->driver, "bcm2835"); ++ strcpy(g_card->shortname, "bcm2835 ALSA"); ++ sprintf(g_card->longname, "%s", g_card->shortname); ++ ++ err = snd_bcm2835_create(g_card, pdev, &chip); ++ if (err < 0) { ++ dev_err(&pdev->dev, "Failed to create bcm2835 chip\n"); ++ goto out_bcm2835_create; ++ } ++ ++ g_chip = chip; ++ err = snd_bcm2835_new_pcm(chip); ++ if (err < 0) { ++ dev_err(&pdev->dev, "Failed to create new BCM2835 pcm device\n"); ++ goto out_bcm2835_new_pcm; ++ } ++ ++ err = snd_bcm2835_new_spdif_pcm(chip); ++ if (err < 0) { ++ dev_err(&pdev->dev, "Failed to create new BCM2835 spdif pcm device\n"); ++ goto out_bcm2835_new_spdif; ++ } ++ ++ err = snd_bcm2835_new_ctl(chip); ++ if (err < 0) { ++ dev_err(&pdev->dev, "Failed to create new BCM2835 ctl\n"); ++ goto out_bcm2835_new_ctl; ++ } ++ ++add_register_map: ++ card = g_card; ++ chip = g_chip; ++ ++ BUG_ON(!(card && chip)); ++ ++ chip->avail_substreams |= (1 << dev); ++ chip->pdev[dev] = pdev; ++ ++ if (dev == 0) { ++ err = snd_card_register(card); ++ if (err < 0) { ++ dev_err(&pdev->dev, ++ "Failed to register bcm2835 ALSA card \n"); ++ goto out_card_register; ++ } ++ platform_set_drvdata(pdev, card); ++ audio_info("bcm2835 ALSA card created!\n"); ++ } else { ++ audio_info("bcm2835 ALSA chip created!\n"); ++ platform_set_drvdata(pdev, (void *)dev); ++ } ++ ++ dev++; ++ ++ return 0; ++ ++out_card_register: ++out_bcm2835_new_ctl: ++out_bcm2835_new_spdif: ++out_bcm2835_new_pcm: ++out_bcm2835_create: ++ BUG_ON(!g_card); ++ if (snd_card_free(g_card)) ++ dev_err(&pdev->dev, "Failed to free Registered alsa card\n"); ++ g_card = NULL; ++out: ++ dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */ ++ dev_err(&pdev->dev, "BCM2835 ALSA Probe failed !!\n"); ++ return err; ++} ++ ++static int snd_bcm2835_alsa_remove(struct platform_device *pdev) ++{ ++ uint32_t idx; ++ void *drv_data; ++ ++ drv_data = platform_get_drvdata(pdev); ++ ++ if (drv_data == (void *)g_card) { ++ /* This is the card device */ ++ snd_card_free((struct snd_card *)drv_data); ++ g_card = NULL; ++ g_chip = NULL; ++ } else { ++ idx = (uint32_t) drv_data; ++ if (g_card != NULL) { ++ BUG_ON(!g_chip); ++ /* We pass chip device numbers in audio ipc devices ++ * other than the one we registered our card with ++ */ ++ idx = (uint32_t) drv_data; ++ BUG_ON(!idx || idx > MAX_SUBSTREAMS); ++ g_chip->avail_substreams &= ~(1 << idx); ++ /* There should be atleast one substream registered ++ * after we are done here, as it wil be removed when ++ * the *remove* is called for the card device ++ */ ++ BUG_ON(!g_chip->avail_substreams); ++ } ++ } ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int snd_bcm2835_alsa_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ return 0; ++} ++ ++static int snd_bcm2835_alsa_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++#endif ++ ++static const struct of_device_id snd_bcm2835_of_match_table[] = { ++ { .compatible = "brcm,bcm2835-audio", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_bcm2835_of_match_table); ++ ++static struct platform_driver bcm2835_alsa0_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD0", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_bcm2835_of_match_table, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa1_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD1", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa2_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD2", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa3_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD3", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa4_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD4", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa5_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD5", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa6_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD6", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa7_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD7", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int bcm2835_alsa_device_init(void) ++{ ++ int err; ++ err = platform_driver_register(&bcm2835_alsa0_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto out; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa1_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_0; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa2_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_1; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa3_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_2; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa4_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_3; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa5_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_4; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa6_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_5; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa7_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_6; ++ } ++ ++ return 0; ++ ++unregister_6: ++ platform_driver_unregister(&bcm2835_alsa6_driver); ++unregister_5: ++ platform_driver_unregister(&bcm2835_alsa5_driver); ++unregister_4: ++ platform_driver_unregister(&bcm2835_alsa4_driver); ++unregister_3: ++ platform_driver_unregister(&bcm2835_alsa3_driver); ++unregister_2: ++ platform_driver_unregister(&bcm2835_alsa2_driver); ++unregister_1: ++ platform_driver_unregister(&bcm2835_alsa1_driver); ++unregister_0: ++ platform_driver_unregister(&bcm2835_alsa0_driver); ++out: ++ return err; ++} ++ ++static void bcm2835_alsa_device_exit(void) ++{ ++ platform_driver_unregister(&bcm2835_alsa0_driver); ++ platform_driver_unregister(&bcm2835_alsa1_driver); ++ platform_driver_unregister(&bcm2835_alsa2_driver); ++ platform_driver_unregister(&bcm2835_alsa3_driver); ++ platform_driver_unregister(&bcm2835_alsa4_driver); ++ platform_driver_unregister(&bcm2835_alsa5_driver); ++ platform_driver_unregister(&bcm2835_alsa6_driver); ++ platform_driver_unregister(&bcm2835_alsa7_driver); ++} ++ ++late_initcall(bcm2835_alsa_device_init); ++module_exit(bcm2835_alsa_device_exit); ++ ++MODULE_AUTHOR("Dom Cobley"); ++MODULE_DESCRIPTION("Alsa driver for BCM2835 chip"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:bcm2835_alsa"); +--- /dev/null ++++ b/sound/arm/bcm2835.h +@@ -0,0 +1,167 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __SOUND_ARM_BCM2835_H ++#define __SOUND_ARM_BCM2835_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++#define AUDIO_DEBUG_ENABLE ++#define AUDIO_VERBOSE_DEBUG_ENABLE ++*/ ++ ++/* Debug macros */ ++ ++#ifdef AUDIO_DEBUG_ENABLE ++#ifdef AUDIO_VERBOSE_DEBUG_ENABLE ++ ++#define audio_debug(fmt, arg...) \ ++ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_info(fmt, arg...) \ ++ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#else ++ ++#define audio_debug(fmt, arg...) ++ ++#define audio_info(fmt, arg...) ++ ++#endif /* AUDIO_VERBOSE_DEBUG_ENABLE */ ++ ++#else ++ ++#define audio_debug(fmt, arg...) ++ ++#define audio_info(fmt, arg...) ++ ++#endif /* AUDIO_DEBUG_ENABLE */ ++ ++#define audio_error(fmt, arg...) \ ++ printk(KERN_ERR"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_warning(fmt, arg...) \ ++ printk(KERN_WARNING"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_alert(fmt, arg...) \ ++ printk(KERN_ALERT"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define MAX_SUBSTREAMS (8) ++#define AVAIL_SUBSTREAMS_MASK (0xff) ++enum { ++ CTRL_VOL_MUTE, ++ CTRL_VOL_UNMUTE ++}; ++ ++/* macros for alsa2chip and chip2alsa, instead of functions */ ++ ++#define alsa2chip(vol) (uint)(-((vol << 8) / 100)) /* convert alsa to chip volume (defined as macro rather than function call) */ ++#define chip2alsa(vol) -((vol * 100) >> 8) /* convert chip to alsa volume */ ++ ++/* Some constants for values .. */ ++typedef enum { ++ AUDIO_DEST_AUTO = 0, ++ AUDIO_DEST_HEADPHONES = 1, ++ AUDIO_DEST_HDMI = 2, ++ AUDIO_DEST_MAX, ++} SND_BCM2835_ROUTE_T; ++ ++typedef enum { ++ PCM_PLAYBACK_VOLUME, ++ PCM_PLAYBACK_MUTE, ++ PCM_PLAYBACK_DEVICE, ++} SND_BCM2835_CTRL_T; ++ ++/* definition of the chip-specific record */ ++typedef struct bcm2835_chip { ++ struct snd_card *card; ++ struct snd_pcm *pcm; ++ struct snd_pcm *pcm_spdif; ++ /* Bitmat for valid reg_base and irq numbers */ ++ uint32_t avail_substreams; ++ struct platform_device *pdev[MAX_SUBSTREAMS]; ++ struct bcm2835_alsa_stream *alsa_stream[MAX_SUBSTREAMS]; ++ ++ int volume; ++ int old_volume; /* stores the volume value whist muted */ ++ int dest; ++ int mute; ++ ++ unsigned int opened; ++ unsigned int spdif_status; ++ struct mutex audio_mutex; ++} bcm2835_chip_t; ++ ++typedef struct bcm2835_alsa_stream { ++ bcm2835_chip_t *chip; ++ struct snd_pcm_substream *substream; ++ struct snd_pcm_indirect pcm_indirect; ++ ++ struct semaphore buffers_update_sem; ++ struct semaphore control_sem; ++ spinlock_t lock; ++ volatile uint32_t control; ++ volatile uint32_t status; ++ ++ int open; ++ int running; ++ int draining; ++ ++ int channels; ++ int params_rate; ++ int pcm_format_width; ++ ++ unsigned int pos; ++ unsigned int buffer_size; ++ unsigned int period_size; ++ ++ uint32_t enable_fifo_irq; ++ irq_handler_t fifo_irq_handler; ++ ++ atomic_t retrieved; ++ struct opaque_AUDIO_INSTANCE_T *instance; ++ struct workqueue_struct *my_wq; ++ int idx; ++} bcm2835_alsa_stream_t; ++ ++int snd_bcm2835_new_ctl(bcm2835_chip_t * chip); ++int snd_bcm2835_new_pcm(bcm2835_chip_t * chip); ++int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip); ++ ++int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, ++ uint32_t channels, uint32_t samplerate, ++ uint32_t bps); ++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_set_ctls(bcm2835_chip_t * chip); ++int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count, ++ void *src); ++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream); ++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream); ++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream); ++ ++#endif /* __SOUND_ARM_BCM2835_H */ +--- /dev/null ++++ b/sound/arm/vc_vchi_audioserv_defs.h +@@ -0,0 +1,116 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef _VC_AUDIO_DEFS_H_ ++#define _VC_AUDIO_DEFS_H_ ++ ++#define VC_AUDIOSERV_MIN_VER 1 ++#define VC_AUDIOSERV_VER 2 ++ ++// FourCC code used for VCHI connection ++#define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS") ++ ++// Maximum message length ++#define VC_AUDIO_MAX_MSG_LEN (sizeof( VC_AUDIO_MSG_T )) ++ ++// List of screens that are currently supported ++// All message types supported for HOST->VC direction ++typedef enum { ++ VC_AUDIO_MSG_TYPE_RESULT, // Generic result ++ VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result ++ VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio ++ VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio ++ VC_AUDIO_MSG_TYPE_OPEN, // Configure audio ++ VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio ++ VC_AUDIO_MSG_TYPE_START, // Configure audio ++ VC_AUDIO_MSG_TYPE_STOP, // Configure audio ++ VC_AUDIO_MSG_TYPE_WRITE, // Configure audio ++ VC_AUDIO_MSG_TYPE_MAX ++} VC_AUDIO_MSG_TYPE; ++ ++// configure the audio ++typedef struct { ++ uint32_t channels; ++ uint32_t samplerate; ++ uint32_t bps; ++ ++} VC_AUDIO_CONFIG_T; ++ ++typedef struct { ++ uint32_t volume; ++ uint32_t dest; ++ ++} VC_AUDIO_CONTROL_T; ++ ++// audio ++typedef struct { ++ uint32_t dummy; ++ ++} VC_AUDIO_OPEN_T; ++ ++// audio ++typedef struct { ++ uint32_t dummy; ++ ++} VC_AUDIO_CLOSE_T; ++// audio ++typedef struct { ++ uint32_t dummy; ++ ++} VC_AUDIO_START_T; ++// audio ++typedef struct { ++ uint32_t draining; ++ ++} VC_AUDIO_STOP_T; ++ ++// configure the write audio samples ++typedef struct { ++ uint32_t count; // in bytes ++ void *callback; ++ void *cookie; ++ uint16_t silence; ++ uint16_t max_packet; ++} VC_AUDIO_WRITE_T; ++ ++// Generic result for a request (VC->HOST) ++typedef struct { ++ int32_t success; // Success value ++ ++} VC_AUDIO_RESULT_T; ++ ++// Generic result for a request (VC->HOST) ++typedef struct { ++ int32_t count; // Success value ++ void *callback; ++ void *cookie; ++} VC_AUDIO_COMPLETE_T; ++ ++// Message header for all messages in HOST->VC direction ++typedef struct { ++ int32_t type; // Message type (VC_AUDIO_MSG_TYPE) ++ union { ++ VC_AUDIO_CONFIG_T config; ++ VC_AUDIO_CONTROL_T control; ++ VC_AUDIO_OPEN_T open; ++ VC_AUDIO_CLOSE_T close; ++ VC_AUDIO_START_T start; ++ VC_AUDIO_STOP_T stop; ++ VC_AUDIO_WRITE_T write; ++ VC_AUDIO_RESULT_T result; ++ VC_AUDIO_COMPLETE_T complete; ++ } u; ++} VC_AUDIO_MSG_T; ++ ++#endif // _VC_AUDIO_DEFS_H_ diff --git a/target/linux/brcm2708/patches-4.1/0012-bcm2708-vchiq-driver.patch b/target/linux/brcm2708/patches-4.1/0012-bcm2708-vchiq-driver.patch new file mode 100644 index 0000000..f70d2cd --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0012-bcm2708-vchiq-driver.patch @@ -0,0 +1,13145 @@ +From a9ec42880d0dfd336819f699cc63dcf13c897286 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Tue, 2 Jul 2013 23:42:01 +0100 +Subject: [PATCH 012/203] bcm2708 vchiq driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: popcornmix + +vchiq: create_pagelist copes with vmalloc memory + +Signed-off-by: Daniel Stone + +vchiq: fix the shim message release + +Signed-off-by: Daniel Stone + +vchiq: export additional symbols + +Signed-off-by: Daniel Stone + +VCHIQ: Make service closure fully synchronous (drv) + +This is one half of a two-part patch, the other half of which is to +the vchiq_lib user library. With these patches, calls to +vchiq_close_service and vchiq_remove_service won't return until any +associated callbacks have been delivered to the callback thread. + +VCHIQ: Add per-service tracing + +The new service option VCHIQ_SERVICE_OPTION_TRACE is a boolean that +toggles tracing for the specified service. + +This commit also introduces vchi_service_set_option and the associated +option VCHI_SERVICE_OPTION_TRACE. + +vchiq: Make the synchronous-CLOSE logic more tolerant + +vchiq: Move logging control into debugfs + +vchiq: Take care of a corner case tickled by VCSM + +Closing a connection that isn't fully open requires care, since one +side does not know the other side's port number. Code was present to +handle the case where a CLOSE is sent immediately after an OPEN, i.e. +before the OPENACK has been received, but this was incorrectly being +used when an OPEN from a client using port 0 was rejected. + +(In the observed failure, the host was attempting to use the VCSM +service, which isn't present in the 'cutdown' firmware. The failure +was intermittent because sometimes the keepalive service would +grab port 0.) + +This case can be distinguished because the client's remoteport will +still be VCHIQ_PORT_FREE, and the srvstate will be OPENING. Either +condition is sufficient to differentiate it from the special case +described above. + +vchiq: Avoid high load when blocked and unkillable + +vchiq: Include SIGSTOP and SIGCONT in list of signals not-masked by vchiq to allow gdb to work + +vchiq_arm: Complete support for SYNCHRONOUS mode + +vchiq: Remove inline from suspend/resume + +vchiq: Allocation does not need to be atomic + +vchiq: Fix wrong condition check + +The log level is checked from within the log call. Remove the check in the call. + +Signed-off-by: Pranith Kumar + +BCM270x: Add vchiq device to platform file and Device Tree + +Prepare to turn the vchiq module into a driver. + +Signed-off-by: Noralf Trønnes + +bcm2708: vchiq: Add Device Tree support + +Turn vchiq into a driver and stop hardcoding resources. +Use devm_* functions in probe path to simplify cleanup. +A global variable is used to hold the register address. This is done +to keep this patch as small as possible. +Also make available on ARCH_BCM2835. +Based on work by Lubomir Rintel. + +Signed-off-by: Noralf Trønnes + +vchiq: Change logging level for inbound data +--- + arch/arm/mach-bcm2708/bcm2708.c | 26 + + arch/arm/mach-bcm2708/include/mach/platform.h | 2 + + arch/arm/mach-bcm2709/bcm2709.c | 26 + + arch/arm/mach-bcm2709/include/mach/platform.h | 2 + + drivers/misc/Kconfig | 1 + + drivers/misc/Makefile | 1 + + drivers/misc/vc04_services/Kconfig | 9 + + drivers/misc/vc04_services/Makefile | 14 + + .../interface/vchi/connections/connection.h | 328 ++ + .../interface/vchi/message_drivers/message.h | 204 + + drivers/misc/vc04_services/interface/vchi/vchi.h | 378 ++ + .../misc/vc04_services/interface/vchi/vchi_cfg.h | 224 ++ + .../interface/vchi/vchi_cfg_internal.h | 71 + + .../vc04_services/interface/vchi/vchi_common.h | 175 + + .../misc/vc04_services/interface/vchi/vchi_mh.h | 42 + + .../misc/vc04_services/interface/vchiq_arm/vchiq.h | 40 + + .../vc04_services/interface/vchiq_arm/vchiq_2835.h | 42 + + .../interface/vchiq_arm/vchiq_2835_arm.c | 547 +++ + .../vc04_services/interface/vchiq_arm/vchiq_arm.c | 2886 ++++++++++++++ + .../vc04_services/interface/vchiq_arm/vchiq_arm.h | 220 ++ + .../interface/vchiq_arm/vchiq_build_info.h | 37 + + .../vc04_services/interface/vchiq_arm/vchiq_cfg.h | 69 + + .../interface/vchiq_arm/vchiq_connected.c | 120 + + .../interface/vchiq_arm/vchiq_connected.h | 50 + + .../vc04_services/interface/vchiq_arm/vchiq_core.c | 3934 ++++++++++++++++++++ + .../vc04_services/interface/vchiq_arm/vchiq_core.h | 712 ++++ + .../interface/vchiq_arm/vchiq_debugfs.c | 383 ++ + .../interface/vchiq_arm/vchiq_debugfs.h | 52 + + .../interface/vchiq_arm/vchiq_genversion | 87 + + .../vc04_services/interface/vchiq_arm/vchiq_if.h | 189 + + .../interface/vchiq_arm/vchiq_ioctl.h | 131 + + .../interface/vchiq_arm/vchiq_kern_lib.c | 458 +++ + .../interface/vchiq_arm/vchiq_killable.h | 69 + + .../interface/vchiq_arm/vchiq_memdrv.h | 71 + + .../interface/vchiq_arm/vchiq_pagelist.h | 58 + + .../vc04_services/interface/vchiq_arm/vchiq_shim.c | 860 +++++ + .../vc04_services/interface/vchiq_arm/vchiq_util.c | 152 + + .../vc04_services/interface/vchiq_arm/vchiq_util.h | 81 + + .../interface/vchiq_arm/vchiq_version.c | 59 + + 39 files changed, 12810 insertions(+) + create mode 100644 drivers/misc/vc04_services/Kconfig + create mode 100644 drivers/misc/vc04_services/Makefile + create mode 100644 drivers/misc/vc04_services/interface/vchi/connections/connection.h + create mode 100644 drivers/misc/vc04_services/interface/vchi/message_drivers/message.h + create mode 100644 drivers/misc/vc04_services/interface/vchi/vchi.h + create mode 100644 drivers/misc/vc04_services/interface/vchi/vchi_cfg.h + create mode 100644 drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h + create mode 100644 drivers/misc/vc04_services/interface/vchi/vchi_common.h + create mode 100644 drivers/misc/vc04_services/interface/vchi/vchi_mh.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -376,6 +376,31 @@ static struct platform_device bcm2708_vc + }, + }; + ++static struct resource bcm2708_vchiq_resources[] = { ++ { ++ .start = ARMCTRL_0_BELL_BASE, ++ .end = ARMCTRL_0_BELL_BASE + 16, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_ARM_DOORBELL_0, ++ .end = IRQ_ARM_DOORBELL_0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 vchiq_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vchiq_device = { ++ .name = "bcm2835_vchiq", ++ .id = -1, ++ .resource = bcm2708_vchiq_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vchiq_resources), ++ .dev = { ++ .dma_mask = &vchiq_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ + #ifdef CONFIG_BCM2708_GPIO + #define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" + +@@ -611,6 +636,7 @@ void __init bcm2708_init(void) + + bcm_register_device_dt(&bcm2708_dmaengine_device); + bcm_register_device(&bcm2708_vcio_device); ++ bcm_register_device_dt(&bcm2708_vchiq_device); + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); + #endif +--- a/arch/arm/mach-bcm2708/include/mach/platform.h ++++ b/arch/arm/mach-bcm2708/include/mach/platform.h +@@ -81,6 +81,8 @@ + #define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ + #define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ + #define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ ++#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ ++#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ + + + /* +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -396,6 +396,31 @@ static struct platform_device bcm2708_vc + }, + }; + ++static struct resource bcm2708_vchiq_resources[] = { ++ { ++ .start = ARMCTRL_0_BELL_BASE, ++ .end = ARMCTRL_0_BELL_BASE + 16, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_ARM_DOORBELL_0, ++ .end = IRQ_ARM_DOORBELL_0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 vchiq_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vchiq_device = { ++ .name = "bcm2835_vchiq", ++ .id = -1, ++ .resource = bcm2708_vchiq_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vchiq_resources), ++ .dev = { ++ .dma_mask = &vchiq_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ + #ifdef CONFIG_BCM2708_GPIO + #define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" + +@@ -631,6 +656,7 @@ void __init bcm2709_init(void) + + bcm_register_device_dt(&bcm2708_dmaengine_device); + bcm_register_device(&bcm2708_vcio_device); ++ bcm_register_device_dt(&bcm2708_vchiq_device); + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); + #endif +--- a/arch/arm/mach-bcm2709/include/mach/platform.h ++++ b/arch/arm/mach-bcm2709/include/mach/platform.h +@@ -81,6 +81,8 @@ + #define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ + #define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ + #define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ ++#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ ++#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ + + + /* +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -524,6 +524,7 @@ source "drivers/misc/carma/Kconfig" + source "drivers/misc/altera-stapl/Kconfig" + source "drivers/misc/mei/Kconfig" + source "drivers/misc/vmw_vmci/Kconfig" ++source "drivers/misc/vc04_services/Kconfig" + source "drivers/misc/mic/Kconfig" + source "drivers/misc/genwqe/Kconfig" + source "drivers/misc/echo/Kconfig" +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -51,6 +51,7 @@ obj-$(CONFIG_INTEL_MEI) += mei/ + obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/ + obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o + obj-$(CONFIG_SRAM) += sram.o ++obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/ + obj-y += mic/ + obj-$(CONFIG_GENWQE) += genwqe/ + obj-$(CONFIG_ECHO) += echo/ +--- /dev/null ++++ b/drivers/misc/vc04_services/Kconfig +@@ -0,0 +1,9 @@ ++config BCM2708_VCHIQ ++ tristate "Videocore VCHIQ" ++ depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2708_MBOX ++ default y ++ help ++ Kernel to VideoCore communication interface for the ++ BCM2708 family of products. ++ Defaults to Y when the Broadcom Videocore services ++ are included in the build, N otherwise. +--- /dev/null ++++ b/drivers/misc/vc04_services/Makefile +@@ -0,0 +1,14 @@ ++obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o ++ ++vchiq-objs := \ ++ interface/vchiq_arm/vchiq_core.o \ ++ interface/vchiq_arm/vchiq_arm.o \ ++ interface/vchiq_arm/vchiq_kern_lib.o \ ++ interface/vchiq_arm/vchiq_2835_arm.o \ ++ interface/vchiq_arm/vchiq_debugfs.o \ ++ interface/vchiq_arm/vchiq_shim.o \ ++ interface/vchiq_arm/vchiq_util.o \ ++ interface/vchiq_arm/vchiq_connected.o \ ++ ++ccflags-y += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 ++ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchi/connections/connection.h +@@ -0,0 +1,328 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef CONNECTION_H_ ++#define CONNECTION_H_ ++ ++#include ++#include ++#include ++ ++#include "interface/vchi/vchi_cfg_internal.h" ++#include "interface/vchi/vchi_common.h" ++#include "interface/vchi/message_drivers/message.h" ++ ++/****************************************************************************** ++ Global defs ++ *****************************************************************************/ ++ ++// Opaque handle for a connection / service pair ++typedef struct opaque_vchi_connection_connected_service_handle_t *VCHI_CONNECTION_SERVICE_HANDLE_T; ++ ++// opaque handle to the connection state information ++typedef struct opaque_vchi_connection_info_t VCHI_CONNECTION_STATE_T; ++ ++typedef struct vchi_connection_t VCHI_CONNECTION_T; ++ ++ ++/****************************************************************************** ++ API ++ *****************************************************************************/ ++ ++// Routine to init a connection with a particular low level driver ++typedef VCHI_CONNECTION_STATE_T * (*VCHI_CONNECTION_INIT_T)( struct vchi_connection_t * connection, ++ const VCHI_MESSAGE_DRIVER_T * driver ); ++ ++// Routine to control CRC enabling at a connection level ++typedef int32_t (*VCHI_CONNECTION_CRC_CONTROL_T)( VCHI_CONNECTION_STATE_T *state_handle, ++ VCHI_CRC_CONTROL_T control ); ++ ++// Routine to create a service ++typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle, ++ int32_t service_id, ++ uint32_t rx_fifo_size, ++ uint32_t tx_fifo_size, ++ int server, ++ VCHI_CALLBACK_T callback, ++ void *callback_param, ++ int32_t want_crc, ++ int32_t want_unaligned_bulk_rx, ++ int32_t want_unaligned_bulk_tx, ++ VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle ); ++ ++// Routine to close a service ++typedef int32_t (*VCHI_CONNECTION_SERVICE_DISCONNECT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle ); ++ ++// Routine to queue a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// scatter-gather (vector) message queueing ++typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// Routine to dequeue a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to peek at a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to hold a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ void **message_handle ); ++ ++// Routine to initialise a received message iterator ++typedef int32_t (*VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ VCHI_MSG_ITER_T *iter, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to release a held message ++typedef int32_t (*VCHI_CONNECTION_HELD_MSG_RELEASE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *message_handle ); ++ ++// Routine to get info on a held message ++typedef int32_t (*VCHI_CONNECTION_HELD_MSG_INFO_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *message_handle, ++ void **data, ++ int32_t *msg_size, ++ uint32_t *tx_timestamp, ++ uint32_t *rx_timestamp ); ++ ++// Routine to check whether the iterator has a next message ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ const VCHI_MSG_ITER_T *iter ); ++ ++// Routine to advance the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter, ++ void **data, ++ uint32_t *msg_size ); ++ ++// Routine to remove the last message returned by the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_REMOVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter ); ++ ++// Routine to hold the last message returned by the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HOLD_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter, ++ void **msg_handle ); ++ ++// Routine to transmit bulk data ++typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle ); ++ ++// Routine to receive data ++typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle ); ++ ++// Routine to report if a server is available ++typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t peer_flags ); ++ ++// Routine to report the number of RX slots available ++typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state ); ++ ++// Routine to report the RX slot size ++typedef uint32_t (*VCHI_CONNECTION_RX_SLOT_SIZE)( const VCHI_CONNECTION_STATE_T *state ); ++ ++// Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO ++typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state, ++ int32_t service, ++ uint32_t length, ++ MESSAGE_TX_CHANNEL_T channel, ++ uint32_t channel_params, ++ uint32_t data_length, ++ uint32_t data_offset); ++ ++// Callback to inform a service that a Xon or Xoff message has been received ++typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t xoff); ++ ++// Callback to inform a service that a server available reply message has been received ++typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, uint32_t flags); ++ ++// Callback to indicate that bulk auxiliary messages have arrived ++typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state); ++ ++// Callback to indicate that bulk auxiliary messages have arrived ++typedef void (*VCHI_CONNECTION_BULK_AUX_TRANSMITTED)(VCHI_CONNECTION_STATE_T *state, void *handle); ++ ++// Callback with all the connection info you require ++typedef void (*VCHI_CONNECTION_INFO)(VCHI_CONNECTION_STATE_T *state, uint32_t protocol_version, uint32_t slot_size, uint32_t num_slots, uint32_t min_bulk_size); ++ ++// Callback to inform of a disconnect ++typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags); ++ ++// Callback to inform of a power control request ++typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, int32_t enable); ++ ++// allocate memory suitably aligned for this connection ++typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length); ++ ++// free memory allocated by buffer_allocate ++typedef void (*VCHI_BUFFER_FREE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, void * address); ++ ++ ++/****************************************************************************** ++ System driver struct ++ *****************************************************************************/ ++ ++struct opaque_vchi_connection_api_t ++{ ++ // Routine to init the connection ++ VCHI_CONNECTION_INIT_T init; ++ ++ // Connection-level CRC control ++ VCHI_CONNECTION_CRC_CONTROL_T crc_control; ++ ++ // Routine to connect to or create service ++ VCHI_CONNECTION_SERVICE_CONNECT_T service_connect; ++ ++ // Routine to disconnect from a service ++ VCHI_CONNECTION_SERVICE_DISCONNECT_T service_disconnect; ++ ++ // Routine to queue a message ++ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T service_queue_msg; ++ ++ // scatter-gather (vector) message queue ++ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T service_queue_msgv; ++ ++ // Routine to dequeue a message ++ VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T service_dequeue_msg; ++ ++ // Routine to peek at a message ++ VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T service_peek_msg; ++ ++ // Routine to hold a message ++ VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T service_hold_msg; ++ ++ // Routine to initialise a received message iterator ++ VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T service_look_ahead_msg; ++ ++ // Routine to release a message ++ VCHI_CONNECTION_HELD_MSG_RELEASE_T held_msg_release; ++ ++ // Routine to get information on a held message ++ VCHI_CONNECTION_HELD_MSG_INFO_T held_msg_info; ++ ++ // Routine to check for next message on iterator ++ VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T msg_iter_has_next; ++ ++ // Routine to get next message on iterator ++ VCHI_CONNECTION_MSG_ITER_NEXT_T msg_iter_next; ++ ++ // Routine to remove the last message returned by iterator ++ VCHI_CONNECTION_MSG_ITER_REMOVE_T msg_iter_remove; ++ ++ // Routine to hold the last message returned by iterator ++ VCHI_CONNECTION_MSG_ITER_HOLD_T msg_iter_hold; ++ ++ // Routine to transmit bulk data ++ VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T bulk_queue_transmit; ++ ++ // Routine to receive data ++ VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T bulk_queue_receive; ++ ++ // Routine to report the available servers ++ VCHI_CONNECTION_SERVER_PRESENT server_present; ++ ++ // Routine to report the number of RX slots available ++ VCHI_CONNECTION_RX_SLOTS_AVAILABLE connection_rx_slots_available; ++ ++ // Routine to report the RX slot size ++ VCHI_CONNECTION_RX_SLOT_SIZE connection_rx_slot_size; ++ ++ // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO ++ VCHI_CONNECTION_RX_BULK_BUFFER_ADDED rx_bulk_buffer_added; ++ ++ // Callback to inform a service that a Xon or Xoff message has been received ++ VCHI_CONNECTION_FLOW_CONTROL flow_control; ++ ++ // Callback to inform a service that a server available reply message has been received ++ VCHI_CONNECTION_SERVER_AVAILABLE_REPLY server_available_reply; ++ ++ // Callback to indicate that bulk auxiliary messages have arrived ++ VCHI_CONNECTION_BULK_AUX_RECEIVED bulk_aux_received; ++ ++ // Callback to indicate that a bulk auxiliary message has been transmitted ++ VCHI_CONNECTION_BULK_AUX_TRANSMITTED bulk_aux_transmitted; ++ ++ // Callback to provide information about the connection ++ VCHI_CONNECTION_INFO connection_info; ++ ++ // Callback to notify that peer has requested disconnect ++ VCHI_CONNECTION_DISCONNECT disconnect; ++ ++ // Callback to notify that peer has requested power change ++ VCHI_CONNECTION_POWER_CONTROL power_control; ++ ++ // allocate memory suitably aligned for this connection ++ VCHI_BUFFER_ALLOCATE buffer_allocate; ++ ++ // free memory allocated by buffer_allocate ++ VCHI_BUFFER_FREE buffer_free; ++ ++}; ++ ++struct vchi_connection_t { ++ const VCHI_CONNECTION_API_T *api; ++ VCHI_CONNECTION_STATE_T *state; ++#ifdef VCHI_COARSE_LOCKING ++ struct semaphore sem; ++#endif ++}; ++ ++ ++#endif /* CONNECTION_H_ */ ++ ++/****************************** End of file **********************************/ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h +@@ -0,0 +1,204 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef _VCHI_MESSAGE_H_ ++#define _VCHI_MESSAGE_H_ ++ ++#include ++#include ++#include ++ ++#include "interface/vchi/vchi_cfg_internal.h" ++#include "interface/vchi/vchi_common.h" ++ ++ ++typedef enum message_event_type { ++ MESSAGE_EVENT_NONE, ++ MESSAGE_EVENT_NOP, ++ MESSAGE_EVENT_MESSAGE, ++ MESSAGE_EVENT_SLOT_COMPLETE, ++ MESSAGE_EVENT_RX_BULK_PAUSED, ++ MESSAGE_EVENT_RX_BULK_COMPLETE, ++ MESSAGE_EVENT_TX_COMPLETE, ++ MESSAGE_EVENT_MSG_DISCARDED ++} MESSAGE_EVENT_TYPE_T; ++ ++typedef enum vchi_msg_flags ++{ ++ VCHI_MSG_FLAGS_NONE = 0x0, ++ VCHI_MSG_FLAGS_TERMINATE_DMA = 0x1 ++} VCHI_MSG_FLAGS_T; ++ ++typedef enum message_tx_channel ++{ ++ MESSAGE_TX_CHANNEL_MESSAGE = 0, ++ MESSAGE_TX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards ++} MESSAGE_TX_CHANNEL_T; ++ ++// Macros used for cycling through bulk channels ++#define MESSAGE_TX_CHANNEL_BULK_PREV(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION-1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) ++#define MESSAGE_TX_CHANNEL_BULK_NEXT(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) ++ ++typedef enum message_rx_channel ++{ ++ MESSAGE_RX_CHANNEL_MESSAGE = 0, ++ MESSAGE_RX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards ++} MESSAGE_RX_CHANNEL_T; ++ ++// Message receive slot information ++typedef struct rx_msg_slot_info { ++ ++ struct rx_msg_slot_info *next; ++ //struct slot_info *prev; ++#if !defined VCHI_COARSE_LOCKING ++ struct semaphore sem; ++#endif ++ ++ uint8_t *addr; // base address of slot ++ uint32_t len; // length of slot in bytes ++ ++ uint32_t write_ptr; // hardware causes this to advance ++ uint32_t read_ptr; // this module does the reading ++ int active; // is this slot in the hardware dma fifo? ++ uint32_t msgs_parsed; // count how many messages are in this slot ++ uint32_t msgs_released; // how many messages have been released ++ void *state; // connection state information ++ uint8_t ref_count[VCHI_MAX_SERVICES_PER_CONNECTION]; // reference count for slots held by services ++} RX_MSG_SLOTINFO_T; ++ ++// The message driver no longer needs to know about the fields of RX_BULK_SLOTINFO_T - sort this out. ++// In particular, it mustn't use addr and len - they're the client buffer, but the message ++// driver will be tasked with sending the aligned core section. ++typedef struct rx_bulk_slotinfo_t { ++ struct rx_bulk_slotinfo_t *next; ++ ++ struct semaphore *blocking; ++ ++ // needed by DMA ++ void *addr; ++ uint32_t len; ++ ++ // needed for the callback ++ void *service; ++ void *handle; ++ VCHI_FLAGS_T flags; ++} RX_BULK_SLOTINFO_T; ++ ++ ++/* ---------------------------------------------------------------------- ++ * each connection driver will have a pool of the following struct. ++ * ++ * the pool will be managed by vchi_qman_* ++ * this means there will be multiple queues (single linked lists) ++ * a given struct message_info will be on exactly one of these queues ++ * at any one time ++ * -------------------------------------------------------------------- */ ++typedef struct rx_message_info { ++ ++ struct message_info *next; ++ //struct message_info *prev; ++ ++ uint8_t *addr; ++ uint32_t len; ++ RX_MSG_SLOTINFO_T *slot; // points to whichever slot contains this message ++ uint32_t tx_timestamp; ++ uint32_t rx_timestamp; ++ ++} RX_MESSAGE_INFO_T; ++ ++typedef struct { ++ MESSAGE_EVENT_TYPE_T type; ++ ++ struct { ++ // for messages ++ void *addr; // address of message ++ uint16_t slot_delta; // whether this message indicated slot delta ++ uint32_t len; // length of message ++ RX_MSG_SLOTINFO_T *slot; // slot this message is in ++ int32_t service; // service id this message is destined for ++ uint32_t tx_timestamp; // timestamp from the header ++ uint32_t rx_timestamp; // timestamp when we parsed it ++ } message; ++ ++ // FIXME: cleanup slot reporting... ++ RX_MSG_SLOTINFO_T *rx_msg; ++ RX_BULK_SLOTINFO_T *rx_bulk; ++ void *tx_handle; ++ MESSAGE_TX_CHANNEL_T tx_channel; ++ ++} MESSAGE_EVENT_T; ++ ++ ++// callbacks ++typedef void VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T( void *state ); ++ ++typedef struct { ++ VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T *event_callback; ++} VCHI_MESSAGE_DRIVER_OPEN_T; ++ ++ ++// handle to this instance of message driver (as returned by ->open) ++typedef struct opaque_mhandle_t *VCHI_MDRIVER_HANDLE_T; ++ ++struct opaque_vchi_message_driver_t { ++ VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state ); ++ int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, int32_t enable ); ++ int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message ++ int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk) ++ int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk) ++ void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver ++ int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, int32_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void ++ *address, uint32_t length_avail, uint32_t max_total_length, int32_t pad_to_fill, int32_t allow_partial ); ++ ++ int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count ); ++ int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length ); ++ void * (*allocate_buffer)( VCHI_MDRIVER_HANDLE_T *handle, uint32_t *length ); ++ void (*free_buffer)( VCHI_MDRIVER_HANDLE_T *handle, void *address ); ++ int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); ++ int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); ++ ++ int32_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel ); ++ void (*form_bulk_aux)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, uint32_t chunk_size, const void **aux_data, int32_t *aux_len ); ++ void (*debug)( VCHI_MDRIVER_HANDLE_T *handle ); ++}; ++ ++ ++#endif // _VCHI_MESSAGE_H_ ++ ++/****************************** End of file ***********************************/ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchi/vchi.h +@@ -0,0 +1,378 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_H_ ++#define VCHI_H_ ++ ++#include "interface/vchi/vchi_cfg.h" ++#include "interface/vchi/vchi_common.h" ++#include "interface/vchi/connections/connection.h" ++#include "vchi_mh.h" ++ ++ ++/****************************************************************************** ++ Global defs ++ *****************************************************************************/ ++ ++#define VCHI_BULK_ROUND_UP(x) ((((unsigned long)(x))+VCHI_BULK_ALIGN-1) & ~(VCHI_BULK_ALIGN-1)) ++#define VCHI_BULK_ROUND_DOWN(x) (((unsigned long)(x)) & ~(VCHI_BULK_ALIGN-1)) ++#define VCHI_BULK_ALIGN_NBYTES(x) (VCHI_BULK_ALIGNED(x) ? 0 : (VCHI_BULK_ALIGN - ((unsigned long)(x) & (VCHI_BULK_ALIGN-1)))) ++ ++#ifdef USE_VCHIQ_ARM ++#define VCHI_BULK_ALIGNED(x) 1 ++#else ++#define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0) ++#endif ++ ++struct vchi_version { ++ uint32_t version; ++ uint32_t version_min; ++}; ++#define VCHI_VERSION(v_) { v_, v_ } ++#define VCHI_VERSION_EX(v_, m_) { v_, m_ } ++ ++typedef enum ++{ ++ VCHI_VEC_POINTER, ++ VCHI_VEC_HANDLE, ++ VCHI_VEC_LIST ++} VCHI_MSG_VECTOR_TYPE_T; ++ ++typedef struct vchi_msg_vector_ex { ++ ++ VCHI_MSG_VECTOR_TYPE_T type; ++ union ++ { ++ // a memory handle ++ struct ++ { ++ VCHI_MEM_HANDLE_T handle; ++ uint32_t offset; ++ int32_t vec_len; ++ } handle; ++ ++ // an ordinary data pointer ++ struct ++ { ++ const void *vec_base; ++ int32_t vec_len; ++ } ptr; ++ ++ // a nested vector list ++ struct ++ { ++ struct vchi_msg_vector_ex *vec; ++ uint32_t vec_len; ++ } list; ++ } u; ++} VCHI_MSG_VECTOR_EX_T; ++ ++ ++// Construct an entry in a msg vector for a pointer (p) of length (l) ++#define VCHI_VEC_POINTER(p,l) VCHI_VEC_POINTER, { { (VCHI_MEM_HANDLE_T)(p), (l) } } ++ ++// Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l) ++#define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } } ++ ++// Macros to manipulate 'FOURCC' values ++#define MAKE_FOURCC(x) ((int32_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] )) ++#define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF ++ ++ ++// Opaque service information ++struct opaque_vchi_service_t; ++ ++// Descriptor for a held message. Allocated by client, initialised by vchi_msg_hold, ++// vchi_msg_iter_hold or vchi_msg_iter_hold_next. Fields are for internal VCHI use only. ++typedef struct ++{ ++ struct opaque_vchi_service_t *service; ++ void *message; ++} VCHI_HELD_MSG_T; ++ ++ ++ ++// structure used to provide the information needed to open a server or a client ++typedef struct { ++ struct vchi_version version; ++ int32_t service_id; ++ VCHI_CONNECTION_T *connection; ++ uint32_t rx_fifo_size; ++ uint32_t tx_fifo_size; ++ VCHI_CALLBACK_T callback; ++ void *callback_param; ++ /* client intends to receive bulk transfers of ++ odd lengths or into unaligned buffers */ ++ int32_t want_unaligned_bulk_rx; ++ /* client intends to transmit bulk transfers of ++ odd lengths or out of unaligned buffers */ ++ int32_t want_unaligned_bulk_tx; ++ /* client wants to check CRCs on (bulk) xfers. ++ Only needs to be set at 1 end - will do both directions. */ ++ int32_t want_crc; ++} SERVICE_CREATION_T; ++ ++// Opaque handle for a VCHI instance ++typedef struct opaque_vchi_instance_handle_t *VCHI_INSTANCE_T; ++ ++// Opaque handle for a server or client ++typedef struct opaque_vchi_service_handle_t *VCHI_SERVICE_HANDLE_T; ++ ++// Service registration & startup ++typedef void (*VCHI_SERVICE_INIT)(VCHI_INSTANCE_T initialise_instance, VCHI_CONNECTION_T **connections, uint32_t num_connections); ++ ++typedef struct service_info_tag { ++ const char * const vll_filename; /* VLL to load to start this service. This is an empty string if VLL is "static" */ ++ VCHI_SERVICE_INIT init; /* Service initialisation function */ ++ void *vll_handle; /* VLL handle; NULL when unloaded or a "static VLL" in build */ ++} SERVICE_INFO_T; ++ ++/****************************************************************************** ++ Global funcs - implementation is specific to which side you are on (local / remote) ++ *****************************************************************************/ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++extern /*@observer@*/ VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, ++ const VCHI_MESSAGE_DRIVER_T * low_level); ++ ++ ++// Routine used to initialise the vchi on both local + remote connections ++extern int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle ); ++ ++extern int32_t vchi_exit( void ); ++ ++extern int32_t vchi_connect( VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle ); ++ ++//When this is called, ensure that all services have no data pending. ++//Bulk transfers can remain 'queued' ++extern int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle ); ++ ++// Global control over bulk CRC checking ++extern int32_t vchi_crc_control( VCHI_CONNECTION_T *connection, ++ VCHI_CRC_CONTROL_T control ); ++ ++// helper functions ++extern void * vchi_allocate_buffer(VCHI_SERVICE_HANDLE_T handle, uint32_t *length); ++extern void vchi_free_buffer(VCHI_SERVICE_HANDLE_T handle, void *address); ++extern uint32_t vchi_current_time(VCHI_INSTANCE_T instance_handle); ++ ++ ++/****************************************************************************** ++ Global service API ++ *****************************************************************************/ ++// Routine to create a named service ++extern int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle ); ++ ++// Routine to destory a service ++extern int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to open a named service ++extern int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle); ++ ++extern int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, ++ short *peer_version ); ++ ++// Routine to close a named service ++extern int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to increment ref count on a named service ++extern int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to decrement ref count on a named service ++extern int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to set a control option for a named service ++extern int32_t vchi_service_set_option( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_SERVICE_OPTION_T option, ++ int value); ++ ++// Routine to send a message across a service ++extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// scatter-gather (vector) and send message ++int32_t vchi_msg_queuev_ex( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_EX_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// legacy scatter-gather (vector) and send message, only handles pointers ++int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// Routine to receive a msg from a service ++// Dequeue is equivalent to hold, copy into client buffer, release ++extern int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to look at a message in place. ++// The message is not dequeued, so a subsequent call to peek or dequeue ++// will return the same message. ++extern int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to remove a message after it has been read in place with peek ++// The first message on the queue is dequeued. ++extern int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to look at a message in place. ++// The message is dequeued, so the caller is left holding it; the descriptor is ++// filled in and must be released when the user has finished with the message. ++extern int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, ++ void **data, // } may be NULL, as info can be ++ uint32_t *msg_size, // } obtained from HELD_MSG_T ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_descriptor ); ++ ++// Initialise an iterator to look through messages in place ++extern int32_t vchi_msg_look_ahead( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_ITER_T *iter, ++ VCHI_FLAGS_T flags ); ++ ++/****************************************************************************** ++ Global service support API - operations on held messages and message iterators ++ *****************************************************************************/ ++ ++// Routine to get the address of a held message ++extern void *vchi_held_msg_ptr( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the size of a held message ++extern int32_t vchi_held_msg_size( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the transmit timestamp as written into the header by the peer ++extern uint32_t vchi_held_msg_tx_timestamp( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the reception timestamp, written as we parsed the header ++extern uint32_t vchi_held_msg_rx_timestamp( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to release a held message after it has been processed ++extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ); ++ ++// Indicates whether the iterator has a next message. ++extern int32_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter ); ++ ++// Return the pointer and length for the next message and advance the iterator. ++extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter, ++ void **data, ++ uint32_t *msg_size ); ++ ++// Remove the last message returned by vchi_msg_iter_next. ++// Can only be called once after each call to vchi_msg_iter_next. ++extern int32_t vchi_msg_iter_remove( VCHI_MSG_ITER_T *iter ); ++ ++// Hold the last message returned by vchi_msg_iter_next. ++// Can only be called once after each call to vchi_msg_iter_next. ++extern int32_t vchi_msg_iter_hold( VCHI_MSG_ITER_T *iter, ++ VCHI_HELD_MSG_T *message ); ++ ++// Return information for the next message, and hold it, advancing the iterator. ++extern int32_t vchi_msg_iter_hold_next( VCHI_MSG_ITER_T *iter, ++ void **data, // } may be NULL ++ uint32_t *msg_size, // } ++ VCHI_HELD_MSG_T *message ); ++ ++ ++/****************************************************************************** ++ Global bulk API ++ *****************************************************************************/ ++ ++// Routine to prepare interface for a transfer from the other side ++extern int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++ ++ ++// Prepare interface for a transfer from the other side into relocatable memory. ++int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h_dst, ++ uint32_t offset, ++ uint32_t data_size, ++ const VCHI_FLAGS_T flags, ++ void * const bulk_handle ); ++ ++// Routine to queue up data ready for transfer to the other (once they have signalled they are ready) ++extern int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++ ++ ++/****************************************************************************** ++ Configuration plumbing ++ *****************************************************************************/ ++ ++// function prototypes for the different mid layers (the state info gives the different physical connections) ++extern const VCHI_CONNECTION_API_T *single_get_func_table( void ); ++//extern const VCHI_CONNECTION_API_T *local_server_get_func_table( void ); ++//extern const VCHI_CONNECTION_API_T *local_client_get_func_table( void ); ++ ++// declare all message drivers here ++const VCHI_MESSAGE_DRIVER_T *vchi_mphi_message_driver_func_table( void ); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++extern int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h_src, ++ uint32_t offset, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++#endif /* VCHI_H_ */ ++ ++/****************************** End of file **********************************/ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h +@@ -0,0 +1,224 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_CFG_H_ ++#define VCHI_CFG_H_ ++ ++/**************************************************************************************** ++ * Defines in this first section are part of the VCHI API and may be examined by VCHI ++ * services. ++ ***************************************************************************************/ ++ ++/* Required alignment of base addresses for bulk transfer, if unaligned transfers are not enabled */ ++/* Really determined by the message driver, and should be available from a run-time call. */ ++#ifndef VCHI_BULK_ALIGN ++# if __VCCOREVER__ >= 0x04000000 ++# define VCHI_BULK_ALIGN 32 // Allows for the need to do cache cleans ++# else ++# define VCHI_BULK_ALIGN 16 ++# endif ++#endif ++ ++/* Required length multiple for bulk transfers, if unaligned transfers are not enabled */ ++/* May be less than or greater than VCHI_BULK_ALIGN */ ++/* Really determined by the message driver, and should be available from a run-time call. */ ++#ifndef VCHI_BULK_GRANULARITY ++# if __VCCOREVER__ >= 0x04000000 ++# define VCHI_BULK_GRANULARITY 32 // Allows for the need to do cache cleans ++# else ++# define VCHI_BULK_GRANULARITY 16 ++# endif ++#endif ++ ++/* The largest possible message to be queued with vchi_msg_queue. */ ++#ifndef VCHI_MAX_MSG_SIZE ++# if defined VCHI_LOCAL_HOST_PORT ++# define VCHI_MAX_MSG_SIZE 16384 // makes file transfers fast, but should they be using bulk? ++# else ++# define VCHI_MAX_MSG_SIZE 4096 // NOTE: THIS MUST BE LARGER THAN OR EQUAL TO THE SIZE OF THE KHRONOS MERGE BUFFER!! ++# endif ++#endif ++ ++/****************************************************************************************** ++ * Defines below are system configuration options, and should not be used by VCHI services. ++ *****************************************************************************************/ ++ ++/* How many connections can we support? A localhost implementation uses 2 connections, ++ * 1 for host-app, 1 for VMCS, and these are hooked together by a loopback MPHI VCFW ++ * driver. */ ++#ifndef VCHI_MAX_NUM_CONNECTIONS ++# define VCHI_MAX_NUM_CONNECTIONS 3 ++#endif ++ ++/* How many services can we open per connection? Extending this doesn't cost processing time, just a small ++ * amount of static memory. */ ++#ifndef VCHI_MAX_SERVICES_PER_CONNECTION ++# define VCHI_MAX_SERVICES_PER_CONNECTION 36 ++#endif ++ ++/* Adjust if using a message driver that supports more logical TX channels */ ++#ifndef VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION ++# define VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION 9 // 1 MPHI + 8 CCP2 logical channels ++#endif ++ ++/* Adjust if using a message driver that supports more logical RX channels */ ++#ifndef VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION ++# define VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION 1 // 1 MPHI ++#endif ++ ++/* How many receive slots do we use. This times VCHI_MAX_MSG_SIZE gives the effective ++ * receive queue space, less message headers. */ ++#ifndef VCHI_NUM_READ_SLOTS ++# if defined(VCHI_LOCAL_HOST_PORT) ++# define VCHI_NUM_READ_SLOTS 4 ++# else ++# define VCHI_NUM_READ_SLOTS 48 ++# endif ++#endif ++ ++/* Do we utilise overrun facility for receive message slots? Can aid peer transmit ++ * performance. Only define on VideoCore end, talking to host. ++ */ ++//#define VCHI_MSG_RX_OVERRUN ++ ++/* How many transmit slots do we use. Generally don't need many, as the hardware driver ++ * underneath VCHI will usually have its own buffering. */ ++#ifndef VCHI_NUM_WRITE_SLOTS ++# define VCHI_NUM_WRITE_SLOTS 4 ++#endif ++ ++/* If a service has held or queued received messages in VCHI_XOFF_THRESHOLD or more slots, ++ * then it's taking up too much buffer space, and the peer service will be told to stop ++ * transmitting with an XOFF message. For this to be effective, the VCHI_NUM_READ_SLOTS ++ * needs to be considerably bigger than VCHI_NUM_WRITE_SLOTS, or the transmit latency ++ * is too high. */ ++#ifndef VCHI_XOFF_THRESHOLD ++# define VCHI_XOFF_THRESHOLD (VCHI_NUM_READ_SLOTS / 2) ++#endif ++ ++/* After we've sent an XOFF, the peer will be told to resume transmission once the local ++ * service has dequeued/released enough messages that it's now occupying ++ * VCHI_XON_THRESHOLD slots or fewer. */ ++#ifndef VCHI_XON_THRESHOLD ++# define VCHI_XON_THRESHOLD (VCHI_NUM_READ_SLOTS / 4) ++#endif ++ ++/* A size below which a bulk transfer omits the handshake completely and always goes ++ * via the message channel, if bulk auxiliary is being sent on that service. (The user ++ * can guarantee this by enabling unaligned transmits). ++ * Not API. */ ++#ifndef VCHI_MIN_BULK_SIZE ++# define VCHI_MIN_BULK_SIZE ( VCHI_MAX_MSG_SIZE / 2 < 4096 ? VCHI_MAX_MSG_SIZE / 2 : 4096 ) ++#endif ++ ++/* Maximum size of bulk transmission chunks, for each interface type. A trade-off between ++ * speed and latency; the smaller the chunk size the better change of messages and other ++ * bulk transmissions getting in when big bulk transfers are happening. Set to 0 to not ++ * break transmissions into chunks. ++ */ ++#ifndef VCHI_MAX_BULK_CHUNK_SIZE_MPHI ++# define VCHI_MAX_BULK_CHUNK_SIZE_MPHI (16 * 1024) ++#endif ++ ++/* NB Chunked CCP2 transmissions violate the letter of the CCP2 spec by using "JPEG8" mode ++ * with multiple-line frames. Only use if the receiver can cope. */ ++#ifndef VCHI_MAX_BULK_CHUNK_SIZE_CCP2 ++# define VCHI_MAX_BULK_CHUNK_SIZE_CCP2 0 ++#endif ++ ++/* How many TX messages can we have pending in our transmit slots. Once exhausted, ++ * vchi_msg_queue will be blocked. */ ++#ifndef VCHI_TX_MSG_QUEUE_SIZE ++# define VCHI_TX_MSG_QUEUE_SIZE 256 ++#endif ++ ++/* How many RX messages can we have parsed in the receive slots. Once exhausted, parsing ++ * will be suspended until older messages are dequeued/released. */ ++#ifndef VCHI_RX_MSG_QUEUE_SIZE ++# define VCHI_RX_MSG_QUEUE_SIZE 256 ++#endif ++ ++/* Really should be able to cope if we run out of received message descriptors, by ++ * suspending parsing as the comment above says, but we don't. This sweeps the issue ++ * under the carpet. */ ++#if VCHI_RX_MSG_QUEUE_SIZE < (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS ++# undef VCHI_RX_MSG_QUEUE_SIZE ++# define VCHI_RX_MSG_QUEUE_SIZE (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS ++#endif ++ ++/* How many bulk transmits can we have pending. Once exhausted, vchi_bulk_queue_transmit ++ * will be blocked. */ ++#ifndef VCHI_TX_BULK_QUEUE_SIZE ++# define VCHI_TX_BULK_QUEUE_SIZE 64 ++#endif ++ ++/* How many bulk receives can we have pending. Once exhausted, vchi_bulk_queue_receive ++ * will be blocked. */ ++#ifndef VCHI_RX_BULK_QUEUE_SIZE ++# define VCHI_RX_BULK_QUEUE_SIZE 64 ++#endif ++ ++/* A limit on how many outstanding bulk requests we expect the peer to give us. If ++ * the peer asks for more than this, VCHI will fail and assert. The number is determined ++ * by the peer's hardware - it's the number of outstanding requests that can be queued ++ * on all bulk channels. VC3's MPHI peripheral allows 16. */ ++#ifndef VCHI_MAX_PEER_BULK_REQUESTS ++# define VCHI_MAX_PEER_BULK_REQUESTS 32 ++#endif ++ ++/* Define VCHI_CCP2TX_MANUAL_POWER if the host tells us when to turn the CCP2 ++ * transmitter on and off. ++ */ ++/*#define VCHI_CCP2TX_MANUAL_POWER*/ ++ ++#ifndef VCHI_CCP2TX_MANUAL_POWER ++ ++/* Timeout (in milliseconds) for putting the CCP2TX interface into IDLE state. Set ++ * negative for no IDLE. ++ */ ++# ifndef VCHI_CCP2TX_IDLE_TIMEOUT ++# define VCHI_CCP2TX_IDLE_TIMEOUT 5 ++# endif ++ ++/* Timeout (in milliseconds) for putting the CCP2TX interface into OFF state. Set ++ * negative for no OFF. ++ */ ++# ifndef VCHI_CCP2TX_OFF_TIMEOUT ++# define VCHI_CCP2TX_OFF_TIMEOUT 1000 ++# endif ++ ++#endif /* VCHI_CCP2TX_MANUAL_POWER */ ++ ++#endif /* VCHI_CFG_H_ */ ++ ++/****************************** End of file **********************************/ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h +@@ -0,0 +1,71 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_CFG_INTERNAL_H_ ++#define VCHI_CFG_INTERNAL_H_ ++ ++/**************************************************************************************** ++ * Control optimisation attempts. ++ ***************************************************************************************/ ++ ++// Don't use lots of short-term locks - use great long ones, reducing the overall locks-per-second ++#define VCHI_COARSE_LOCKING ++ ++// Avoid lock then unlock on exit from blocking queue operations (msg tx, bulk rx/tx) ++// (only relevant if VCHI_COARSE_LOCKING) ++#define VCHI_ELIDE_BLOCK_EXIT_LOCK ++ ++// Avoid lock on non-blocking peek ++// (only relevant if VCHI_COARSE_LOCKING) ++#define VCHI_AVOID_PEEK_LOCK ++ ++// Use one slot-handler thread per connection, rather than 1 thread dealing with all connections in rotation. ++#define VCHI_MULTIPLE_HANDLER_THREADS ++ ++// Put free descriptors onto the head of the free queue, rather than the tail, so that we don't thrash ++// our way through the pool of descriptors. ++#define VCHI_PUSH_FREE_DESCRIPTORS_ONTO_HEAD ++ ++// Don't issue a MSG_AVAILABLE callback for every single message. Possibly only safe if VCHI_COARSE_LOCKING. ++#define VCHI_FEWER_MSG_AVAILABLE_CALLBACKS ++ ++// Don't use message descriptors for TX messages that don't need them ++#define VCHI_MINIMISE_TX_MSG_DESCRIPTORS ++ ++// Nano-locks for multiqueue ++//#define VCHI_MQUEUE_NANOLOCKS ++ ++// Lock-free(er) dequeuing ++//#define VCHI_RX_NANOLOCKS ++ ++#endif /*VCHI_CFG_INTERNAL_H_*/ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchi/vchi_common.h +@@ -0,0 +1,175 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_COMMON_H_ ++#define VCHI_COMMON_H_ ++ ++ ++//flags used when sending messages (must be bitmapped) ++typedef enum ++{ ++ VCHI_FLAGS_NONE = 0x0, ++ VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE = 0x1, // waits for message to be received, or sent (NB. not the same as being seen on other side) ++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE = 0x2, // run a callback when message sent ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED = 0x4, // return once the transfer is in a queue ready to go ++ VCHI_FLAGS_ALLOW_PARTIAL = 0x8, ++ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ = 0x10, ++ VCHI_FLAGS_CALLBACK_WHEN_DATA_READ = 0x20, ++ ++ VCHI_FLAGS_ALIGN_SLOT = 0x000080, // internal use only ++ VCHI_FLAGS_BULK_AUX_QUEUED = 0x010000, // internal use only ++ VCHI_FLAGS_BULK_AUX_COMPLETE = 0x020000, // internal use only ++ VCHI_FLAGS_BULK_DATA_QUEUED = 0x040000, // internal use only ++ VCHI_FLAGS_BULK_DATA_COMPLETE = 0x080000, // internal use only ++ VCHI_FLAGS_INTERNAL = 0xFF0000 ++} VCHI_FLAGS_T; ++ ++// constants for vchi_crc_control() ++typedef enum { ++ VCHI_CRC_NOTHING = -1, ++ VCHI_CRC_PER_SERVICE = 0, ++ VCHI_CRC_EVERYTHING = 1, ++} VCHI_CRC_CONTROL_T; ++ ++//callback reasons when an event occurs on a service ++typedef enum ++{ ++ VCHI_CALLBACK_REASON_MIN, ++ ++ //This indicates that there is data available ++ //handle is the msg id that was transmitted with the data ++ // When a message is received and there was no FULL message available previously, send callback ++ // Tasks get kicked by the callback, reset their event and try and read from the fifo until it fails ++ VCHI_CALLBACK_MSG_AVAILABLE, ++ VCHI_CALLBACK_MSG_SENT, ++ VCHI_CALLBACK_MSG_SPACE_AVAILABLE, // XXX not yet implemented ++ ++ // This indicates that a transfer from the other side has completed ++ VCHI_CALLBACK_BULK_RECEIVED, ++ //This indicates that data queued up to be sent has now gone ++ //handle is the msg id that was used when sending the data ++ VCHI_CALLBACK_BULK_SENT, ++ VCHI_CALLBACK_BULK_RX_SPACE_AVAILABLE, // XXX not yet implemented ++ VCHI_CALLBACK_BULK_TX_SPACE_AVAILABLE, // XXX not yet implemented ++ ++ VCHI_CALLBACK_SERVICE_CLOSED, ++ ++ // this side has sent XOFF to peer due to lack of data consumption by service ++ // (suggests the service may need to take some recovery action if it has ++ // been deliberately holding off consuming data) ++ VCHI_CALLBACK_SENT_XOFF, ++ VCHI_CALLBACK_SENT_XON, ++ ++ // indicates that a bulk transfer has finished reading the source buffer ++ VCHI_CALLBACK_BULK_DATA_READ, ++ ++ // power notification events (currently host side only) ++ VCHI_CALLBACK_PEER_OFF, ++ VCHI_CALLBACK_PEER_SUSPENDED, ++ VCHI_CALLBACK_PEER_ON, ++ VCHI_CALLBACK_PEER_RESUMED, ++ VCHI_CALLBACK_FORCED_POWER_OFF, ++ ++#ifdef USE_VCHIQ_ARM ++ // some extra notifications provided by vchiq_arm ++ VCHI_CALLBACK_SERVICE_OPENED, ++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, ++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, ++#endif ++ ++ VCHI_CALLBACK_REASON_MAX ++} VCHI_CALLBACK_REASON_T; ++ ++// service control options ++typedef enum ++{ ++ VCHI_SERVICE_OPTION_MIN, ++ ++ VCHI_SERVICE_OPTION_TRACE, ++ VCHI_SERVICE_OPTION_SYNCHRONOUS, ++ ++ VCHI_SERVICE_OPTION_MAX ++} VCHI_SERVICE_OPTION_T; ++ ++ ++//Callback used by all services / bulk transfers ++typedef void (*VCHI_CALLBACK_T)( void *callback_param, //my service local param ++ VCHI_CALLBACK_REASON_T reason, ++ void *handle ); //for transmitting msg's only ++ ++ ++ ++/* ++ * Define vector struct for scatter-gather (vector) operations ++ * Vectors can be nested - if a vector element has negative length, then ++ * the data pointer is treated as pointing to another vector array, with ++ * '-vec_len' elements. Thus to append a header onto an existing vector, ++ * you can do this: ++ * ++ * void foo(const VCHI_MSG_VECTOR_T *v, int n) ++ * { ++ * VCHI_MSG_VECTOR_T nv[2]; ++ * nv[0].vec_base = my_header; ++ * nv[0].vec_len = sizeof my_header; ++ * nv[1].vec_base = v; ++ * nv[1].vec_len = -n; ++ * ... ++ * ++ */ ++typedef struct vchi_msg_vector { ++ const void *vec_base; ++ int32_t vec_len; ++} VCHI_MSG_VECTOR_T; ++ ++// Opaque type for a connection API ++typedef struct opaque_vchi_connection_api_t VCHI_CONNECTION_API_T; ++ ++// Opaque type for a message driver ++typedef struct opaque_vchi_message_driver_t VCHI_MESSAGE_DRIVER_T; ++ ++ ++// Iterator structure for reading ahead through received message queue. Allocated by client, ++// initialised by vchi_msg_look_ahead. Fields are for internal VCHI use only. ++// Iterates over messages in queue at the instant of the call to vchi_msg_lookahead - ++// will not proceed to messages received since. Behaviour is undefined if an iterator ++// is used again after messages for that service are removed/dequeued by any ++// means other than vchi_msg_iter_... calls on the iterator itself. ++typedef struct { ++ struct opaque_vchi_service_t *service; ++ void *last; ++ void *next; ++ void *remove; ++} VCHI_MSG_ITER_T; ++ ++ ++#endif // VCHI_COMMON_H_ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchi/vchi_mh.h +@@ -0,0 +1,42 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_MH_H_ ++#define VCHI_MH_H_ ++ ++#include ++ ++typedef int32_t VCHI_MEM_HANDLE_T; ++#define VCHI_MEM_HANDLE_INVALID 0 ++ ++#endif +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h +@@ -0,0 +1,40 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_VCHIQ_H ++#define VCHIQ_VCHIQ_H ++ ++#include "vchiq_if.h" ++#include "vchiq_util.h" ++ ++#endif +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h +@@ -0,0 +1,42 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_2835_H ++#define VCHIQ_2835_H ++ ++#include "vchiq_pagelist.h" ++ ++#define VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX 0 ++#define VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX 1 ++ ++#endif /* VCHIQ_2835_H */ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +@@ -0,0 +1,547 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32) ++ ++#define VCHIQ_ARM_ADDRESS(x) ((void *)((char *)x + g_virt_to_bus_offset)) ++ ++#include "vchiq_arm.h" ++#include "vchiq_2835.h" ++#include "vchiq_connected.h" ++#include "vchiq_killable.h" ++ ++#define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2) ++ ++#define BELL0 0x00 ++#define BELL2 0x08 ++ ++typedef struct vchiq_2835_state_struct { ++ int inited; ++ VCHIQ_ARM_STATE_T arm_state; ++} VCHIQ_2835_ARM_STATE_T; ++ ++static void __iomem *g_regs; ++static FRAGMENTS_T *g_fragments_base; ++static FRAGMENTS_T *g_free_fragments; ++static struct semaphore g_free_fragments_sema; ++static unsigned long g_virt_to_bus_offset; ++ ++extern int vchiq_arm_log_level; ++ ++static DEFINE_SEMAPHORE(g_free_fragments_mutex); ++ ++static irqreturn_t ++vchiq_doorbell_irq(int irq, void *dev_id); ++ ++static int ++create_pagelist(char __user *buf, size_t count, unsigned short type, ++ struct task_struct *task, PAGELIST_T ** ppagelist); ++ ++static void ++free_pagelist(PAGELIST_T *pagelist, int actual); ++ ++int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state) ++{ ++ struct device *dev = &pdev->dev; ++ VCHIQ_SLOT_ZERO_T *vchiq_slot_zero; ++ struct resource *res; ++ void *slot_mem; ++ dma_addr_t slot_phys; ++ int slot_mem_size, frag_mem_size; ++ int err, irq, i; ++ ++ g_virt_to_bus_offset = virt_to_dma(dev, (void *)0); ++ ++ /* Allocate space for the channels in coherent memory */ ++ slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE); ++ frag_mem_size = PAGE_ALIGN(sizeof(FRAGMENTS_T) * MAX_FRAGMENTS); ++ ++ slot_mem = dmam_alloc_coherent(dev, slot_mem_size + frag_mem_size, ++ &slot_phys, GFP_KERNEL); ++ if (!slot_mem) { ++ dev_err(dev, "could not allocate DMA memory\n"); ++ return -ENOMEM; ++ } ++ ++ WARN_ON(((int)slot_mem & (PAGE_SIZE - 1)) != 0); ++ ++ vchiq_slot_zero = vchiq_init_slots(slot_mem, slot_mem_size); ++ if (!vchiq_slot_zero) ++ return -EINVAL; ++ ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = ++ (int)slot_phys + slot_mem_size; ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = ++ MAX_FRAGMENTS; ++ ++ g_fragments_base = (FRAGMENTS_T *)(slot_mem + slot_mem_size); ++ slot_mem_size += frag_mem_size; ++ ++ g_free_fragments = g_fragments_base; ++ for (i = 0; i < (MAX_FRAGMENTS - 1); i++) { ++ *(FRAGMENTS_T **)&g_fragments_base[i] = ++ &g_fragments_base[i + 1]; ++ } ++ *(FRAGMENTS_T **)&g_fragments_base[i] = NULL; ++ sema_init(&g_free_fragments_sema, MAX_FRAGMENTS); ++ ++ if (vchiq_init_state(state, vchiq_slot_zero, 0) != VCHIQ_SUCCESS) ++ return -EINVAL; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ g_regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(g_regs)) ++ return PTR_ERR(g_regs); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq <= 0) { ++ dev_err(dev, "failed to get IRQ\n"); ++ return irq; ++ } ++ ++ err = devm_request_irq(dev, irq, vchiq_doorbell_irq, IRQF_IRQPOLL, ++ "VCHIQ doorbell", state); ++ if (err) { ++ dev_err(dev, "failed to register irq=%d\n", irq); ++ return err; ++ } ++ ++ /* Send the base address of the slots to VideoCore */ ++ ++ dsb(); /* Ensure all writes have completed */ ++ ++ err = bcm_mailbox_write(MBOX_CHAN_VCHIQ, (unsigned int)slot_phys); ++ if (err) { ++ dev_err(dev, "mailbox write failed\n"); ++ return err; ++ } ++ ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq_init - done (slots %x, phys %pad)", ++ (unsigned int)vchiq_slot_zero, &slot_phys); ++ ++ vchiq_call_connected_callbacks(); ++ ++ return 0; ++} ++ ++VCHIQ_STATUS_T ++vchiq_platform_init_state(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ state->platform_state = kzalloc(sizeof(VCHIQ_2835_ARM_STATE_T), GFP_KERNEL); ++ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 1; ++ status = vchiq_arm_init_state(state, &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state); ++ if(status != VCHIQ_SUCCESS) ++ { ++ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 0; ++ } ++ return status; ++} ++ ++VCHIQ_ARM_STATE_T* ++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state) ++{ ++ if(!((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited) ++ { ++ BUG(); ++ } ++ return &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state; ++} ++ ++void ++remote_event_signal(REMOTE_EVENT_T *event) ++{ ++ wmb(); ++ ++ event->fired = 1; ++ ++ dsb(); /* data barrier operation */ ++ ++ if (event->armed) ++ writel(0, g_regs + BELL2); /* trigger vc interrupt */ ++} ++ ++int ++vchiq_copy_from_user(void *dst, const void *src, int size) ++{ ++ if ((uint32_t)src < TASK_SIZE) { ++ return copy_from_user(dst, src, size); ++ } else { ++ memcpy(dst, src, size); ++ return 0; ++ } ++} ++ ++VCHIQ_STATUS_T ++vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, VCHI_MEM_HANDLE_T memhandle, ++ void *offset, int size, int dir) ++{ ++ PAGELIST_T *pagelist; ++ int ret; ++ ++ WARN_ON(memhandle != VCHI_MEM_HANDLE_INVALID); ++ ++ ret = create_pagelist((char __user *)offset, size, ++ (dir == VCHIQ_BULK_RECEIVE) ++ ? PAGELIST_READ ++ : PAGELIST_WRITE, ++ current, ++ &pagelist); ++ if (ret != 0) ++ return VCHIQ_ERROR; ++ ++ bulk->handle = memhandle; ++ bulk->data = VCHIQ_ARM_ADDRESS(pagelist); ++ ++ /* Store the pagelist address in remote_data, which isn't used by the ++ slave. */ ++ bulk->remote_data = pagelist; ++ ++ return VCHIQ_SUCCESS; ++} ++ ++void ++vchiq_complete_bulk(VCHIQ_BULK_T *bulk) ++{ ++ if (bulk && bulk->remote_data && bulk->actual) ++ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual); ++} ++ ++void ++vchiq_transfer_bulk(VCHIQ_BULK_T *bulk) ++{ ++ /* ++ * This should only be called on the master (VideoCore) side, but ++ * provide an implementation to avoid the need for ifdefery. ++ */ ++ BUG(); ++} ++ ++void ++vchiq_dump_platform_state(void *dump_context) ++{ ++ char buf[80]; ++ int len; ++ len = snprintf(buf, sizeof(buf), ++ " Platform: 2835 (VC master)"); ++ vchiq_dump(dump_context, buf, len + 1); ++} ++ ++VCHIQ_STATUS_T ++vchiq_platform_suspend(VCHIQ_STATE_T *state) ++{ ++ return VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_platform_resume(VCHIQ_STATE_T *state) ++{ ++ return VCHIQ_SUCCESS; ++} ++ ++void ++vchiq_platform_paused(VCHIQ_STATE_T *state) ++{ ++} ++ ++void ++vchiq_platform_resumed(VCHIQ_STATE_T *state) ++{ ++} ++ ++int ++vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state) ++{ ++ return 1; // autosuspend not supported - videocore always wanted ++} ++ ++int ++vchiq_platform_use_suspend_timer(void) ++{ ++ return 0; ++} ++void ++vchiq_dump_platform_use_state(VCHIQ_STATE_T *state) ++{ ++ vchiq_log_info(vchiq_arm_log_level, "Suspend timer not in use"); ++} ++void ++vchiq_platform_handle_timeout(VCHIQ_STATE_T *state) ++{ ++ (void)state; ++} ++/* ++ * Local functions ++ */ ++ ++static irqreturn_t ++vchiq_doorbell_irq(int irq, void *dev_id) ++{ ++ VCHIQ_STATE_T *state = dev_id; ++ irqreturn_t ret = IRQ_NONE; ++ unsigned int status; ++ ++ /* Read (and clear) the doorbell */ ++ status = readl(g_regs + BELL0); ++ ++ if (status & 0x4) { /* Was the doorbell rung? */ ++ remote_event_pollall(state); ++ ret = IRQ_HANDLED; ++ } ++ ++ return ret; ++} ++ ++/* There is a potential problem with partial cache lines (pages?) ++** at the ends of the block when reading. If the CPU accessed anything in ++** the same line (page?) then it may have pulled old data into the cache, ++** obscuring the new data underneath. We can solve this by transferring the ++** partial cache lines separately, and allowing the ARM to copy into the ++** cached area. ++ ++** N.B. This implementation plays slightly fast and loose with the Linux ++** driver programming rules, e.g. its use of __virt_to_bus instead of ++** dma_map_single, but it isn't a multi-platform driver and it benefits ++** from increased speed as a result. ++*/ ++ ++static int ++create_pagelist(char __user *buf, size_t count, unsigned short type, ++ struct task_struct *task, PAGELIST_T ** ppagelist) ++{ ++ PAGELIST_T *pagelist; ++ struct page **pages; ++ struct page *page; ++ unsigned long *addrs; ++ unsigned int num_pages, offset, i; ++ char *addr, *base_addr, *next_addr; ++ int run, addridx, actual_pages; ++ unsigned long *need_release; ++ ++ offset = (unsigned int)buf & (PAGE_SIZE - 1); ++ num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ *ppagelist = NULL; ++ ++ /* Allocate enough storage to hold the page pointers and the page ++ ** list ++ */ ++ pagelist = kmalloc(sizeof(PAGELIST_T) + ++ (num_pages * sizeof(unsigned long)) + ++ sizeof(unsigned long) + ++ (num_pages * sizeof(pages[0])), ++ GFP_KERNEL); ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "create_pagelist - %x", (unsigned int)pagelist); ++ if (!pagelist) ++ return -ENOMEM; ++ ++ addrs = pagelist->addrs; ++ need_release = (unsigned long *)(addrs + num_pages); ++ pages = (struct page **)(addrs + num_pages + 1); ++ ++ if (is_vmalloc_addr(buf)) { ++ for (actual_pages = 0; actual_pages < num_pages; actual_pages++) { ++ pages[actual_pages] = vmalloc_to_page(buf + (actual_pages * PAGE_SIZE)); ++ } ++ *need_release = 0; /* do not try and release vmalloc pages */ ++ } else { ++ down_read(&task->mm->mmap_sem); ++ actual_pages = get_user_pages(task, task->mm, ++ (unsigned long)buf & ~(PAGE_SIZE - 1), ++ num_pages, ++ (type == PAGELIST_READ) /*Write */ , ++ 0 /*Force */ , ++ pages, ++ NULL /*vmas */); ++ up_read(&task->mm->mmap_sem); ++ ++ if (actual_pages != num_pages) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "create_pagelist - only %d/%d pages locked", ++ actual_pages, ++ num_pages); ++ ++ /* This is probably due to the process being killed */ ++ while (actual_pages > 0) ++ { ++ actual_pages--; ++ page_cache_release(pages[actual_pages]); ++ } ++ kfree(pagelist); ++ if (actual_pages == 0) ++ actual_pages = -ENOMEM; ++ return actual_pages; ++ } ++ *need_release = 1; /* release user pages */ ++ } ++ ++ pagelist->length = count; ++ pagelist->type = type; ++ pagelist->offset = offset; ++ ++ /* Group the pages into runs of contiguous pages */ ++ ++ base_addr = VCHIQ_ARM_ADDRESS(page_address(pages[0])); ++ next_addr = base_addr + PAGE_SIZE; ++ addridx = 0; ++ run = 0; ++ ++ for (i = 1; i < num_pages; i++) { ++ addr = VCHIQ_ARM_ADDRESS(page_address(pages[i])); ++ if ((addr == next_addr) && (run < (PAGE_SIZE - 1))) { ++ next_addr += PAGE_SIZE; ++ run++; ++ } else { ++ addrs[addridx] = (unsigned long)base_addr + run; ++ addridx++; ++ base_addr = addr; ++ next_addr = addr + PAGE_SIZE; ++ run = 0; ++ } ++ } ++ ++ addrs[addridx] = (unsigned long)base_addr + run; ++ addridx++; ++ ++ /* Partial cache lines (fragments) require special measures */ ++ if ((type == PAGELIST_READ) && ++ ((pagelist->offset & (CACHE_LINE_SIZE - 1)) || ++ ((pagelist->offset + pagelist->length) & ++ (CACHE_LINE_SIZE - 1)))) { ++ FRAGMENTS_T *fragments; ++ ++ if (down_interruptible(&g_free_fragments_sema) != 0) { ++ kfree(pagelist); ++ return -EINTR; ++ } ++ ++ WARN_ON(g_free_fragments == NULL); ++ ++ down(&g_free_fragments_mutex); ++ fragments = (FRAGMENTS_T *) g_free_fragments; ++ WARN_ON(fragments == NULL); ++ g_free_fragments = *(FRAGMENTS_T **) g_free_fragments; ++ up(&g_free_fragments_mutex); ++ pagelist->type = ++ PAGELIST_READ_WITH_FRAGMENTS + (fragments - ++ g_fragments_base); ++ } ++ ++ for (page = virt_to_page(pagelist); ++ page <= virt_to_page(addrs + num_pages - 1); page++) { ++ flush_dcache_page(page); ++ } ++ ++ *ppagelist = pagelist; ++ ++ return 0; ++} ++ ++static void ++free_pagelist(PAGELIST_T *pagelist, int actual) ++{ ++ unsigned long *need_release; ++ struct page **pages; ++ unsigned int num_pages, i; ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "free_pagelist - %x, %d", (unsigned int)pagelist, actual); ++ ++ num_pages = ++ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) / ++ PAGE_SIZE; ++ ++ need_release = (unsigned long *)(pagelist->addrs + num_pages); ++ pages = (struct page **)(pagelist->addrs + num_pages + 1); ++ ++ /* Deal with any partial cache lines (fragments) */ ++ if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) { ++ FRAGMENTS_T *fragments = g_fragments_base + ++ (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS); ++ int head_bytes, tail_bytes; ++ head_bytes = (CACHE_LINE_SIZE - pagelist->offset) & ++ (CACHE_LINE_SIZE - 1); ++ tail_bytes = (pagelist->offset + actual) & ++ (CACHE_LINE_SIZE - 1); ++ ++ if ((actual >= 0) && (head_bytes != 0)) { ++ if (head_bytes > actual) ++ head_bytes = actual; ++ ++ memcpy((char *)page_address(pages[0]) + ++ pagelist->offset, ++ fragments->headbuf, ++ head_bytes); ++ } ++ if ((actual >= 0) && (head_bytes < actual) && ++ (tail_bytes != 0)) { ++ memcpy((char *)page_address(pages[num_pages - 1]) + ++ ((pagelist->offset + actual) & ++ (PAGE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1)), ++ fragments->tailbuf, tail_bytes); ++ } ++ ++ down(&g_free_fragments_mutex); ++ *(FRAGMENTS_T **) fragments = g_free_fragments; ++ g_free_fragments = fragments; ++ up(&g_free_fragments_mutex); ++ up(&g_free_fragments_sema); ++ } ++ ++ if (*need_release) { ++ for (i = 0; i < num_pages; i++) { ++ if (pagelist->type != PAGELIST_WRITE) ++ set_page_dirty(pages[i]); ++ ++ page_cache_release(pages[i]); ++ } ++ } ++ ++ kfree(pagelist); ++} +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +@@ -0,0 +1,2886 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vchiq_core.h" ++#include "vchiq_ioctl.h" ++#include "vchiq_arm.h" ++#include "vchiq_debugfs.h" ++#include "vchiq_killable.h" ++ ++#define DEVICE_NAME "vchiq" ++ ++/* Override the default prefix, which would be vchiq_arm (from the filename) */ ++#undef MODULE_PARAM_PREFIX ++#define MODULE_PARAM_PREFIX DEVICE_NAME "." ++ ++#define VCHIQ_MINOR 0 ++ ++/* Some per-instance constants */ ++#define MAX_COMPLETIONS 16 ++#define MAX_SERVICES 64 ++#define MAX_ELEMENTS 8 ++#define MSG_QUEUE_SIZE 64 ++ ++#define KEEPALIVE_VER 1 ++#define KEEPALIVE_VER_MIN KEEPALIVE_VER ++ ++/* Run time control of log level, based on KERN_XXX level. */ ++int vchiq_arm_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_susp_log_level = VCHIQ_LOG_ERROR; ++ ++#define SUSPEND_TIMER_TIMEOUT_MS 100 ++#define SUSPEND_RETRY_TIMER_TIMEOUT_MS 1000 ++ ++#define VC_SUSPEND_NUM_OFFSET 3 /* number of values before idle which are -ve */ ++static const char *const suspend_state_names[] = { ++ "VC_SUSPEND_FORCE_CANCELED", ++ "VC_SUSPEND_REJECTED", ++ "VC_SUSPEND_FAILED", ++ "VC_SUSPEND_IDLE", ++ "VC_SUSPEND_REQUESTED", ++ "VC_SUSPEND_IN_PROGRESS", ++ "VC_SUSPEND_SUSPENDED" ++}; ++#define VC_RESUME_NUM_OFFSET 1 /* number of values before idle which are -ve */ ++static const char *const resume_state_names[] = { ++ "VC_RESUME_FAILED", ++ "VC_RESUME_IDLE", ++ "VC_RESUME_REQUESTED", ++ "VC_RESUME_IN_PROGRESS", ++ "VC_RESUME_RESUMED" ++}; ++/* The number of times we allow force suspend to timeout before actually ++** _forcing_ suspend. This is to cater for SW which fails to release vchiq ++** correctly - we don't want to prevent ARM suspend indefinitely in this case. ++*/ ++#define FORCE_SUSPEND_FAIL_MAX 8 ++ ++/* The time in ms allowed for videocore to go idle when force suspend has been ++ * requested */ ++#define FORCE_SUSPEND_TIMEOUT_MS 200 ++ ++ ++static void suspend_timer_callback(unsigned long context); ++ ++ ++typedef struct user_service_struct { ++ VCHIQ_SERVICE_T *service; ++ void *userdata; ++ VCHIQ_INSTANCE_T instance; ++ char is_vchi; ++ char dequeue_pending; ++ char close_pending; ++ int message_available_pos; ++ int msg_insert; ++ int msg_remove; ++ struct semaphore insert_event; ++ struct semaphore remove_event; ++ struct semaphore close_event; ++ VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE]; ++} USER_SERVICE_T; ++ ++struct bulk_waiter_node { ++ struct bulk_waiter bulk_waiter; ++ int pid; ++ struct list_head list; ++}; ++ ++struct vchiq_instance_struct { ++ VCHIQ_STATE_T *state; ++ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS]; ++ int completion_insert; ++ int completion_remove; ++ struct semaphore insert_event; ++ struct semaphore remove_event; ++ struct mutex completion_mutex; ++ ++ int connected; ++ int closing; ++ int pid; ++ int mark; ++ int use_close_delivered; ++ int trace; ++ ++ struct list_head bulk_waiter_list; ++ struct mutex bulk_waiter_list_mutex; ++ ++ VCHIQ_DEBUGFS_NODE_T debugfs_node; ++}; ++ ++typedef struct dump_context_struct { ++ char __user *buf; ++ size_t actual; ++ size_t space; ++ loff_t offset; ++} DUMP_CONTEXT_T; ++ ++static struct cdev vchiq_cdev; ++static dev_t vchiq_devid; ++static VCHIQ_STATE_T g_state; ++static struct class *vchiq_class; ++static struct device *vchiq_dev; ++static DEFINE_SPINLOCK(msg_queue_spinlock); ++ ++static const char *const ioctl_names[] = { ++ "CONNECT", ++ "SHUTDOWN", ++ "CREATE_SERVICE", ++ "REMOVE_SERVICE", ++ "QUEUE_MESSAGE", ++ "QUEUE_BULK_TRANSMIT", ++ "QUEUE_BULK_RECEIVE", ++ "AWAIT_COMPLETION", ++ "DEQUEUE_MESSAGE", ++ "GET_CLIENT_ID", ++ "GET_CONFIG", ++ "CLOSE_SERVICE", ++ "USE_SERVICE", ++ "RELEASE_SERVICE", ++ "SET_SERVICE_OPTION", ++ "DUMP_PHYS_MEM", ++ "LIB_VERSION", ++ "CLOSE_DELIVERED" ++}; ++ ++vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) == ++ (VCHIQ_IOC_MAX + 1)); ++ ++static void ++dump_phys_mem(void *virt_addr, uint32_t num_bytes); ++ ++/**************************************************************************** ++* ++* add_completion ++* ++***************************************************************************/ ++ ++static VCHIQ_STATUS_T ++add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, USER_SERVICE_T *user_service, ++ void *bulk_userdata) ++{ ++ VCHIQ_COMPLETION_DATA_T *completion; ++ DEBUG_INITIALISE(g_state.local) ++ ++ while (instance->completion_insert == ++ (instance->completion_remove + MAX_COMPLETIONS)) { ++ /* Out of space - wait for the client */ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ vchiq_log_trace(vchiq_arm_log_level, ++ "add_completion - completion queue full"); ++ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); ++ if (down_interruptible(&instance->remove_event) != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback interrupted"); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback closing"); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ } ++ ++ completion = ++ &instance->completions[instance->completion_insert & ++ (MAX_COMPLETIONS - 1)]; ++ ++ completion->header = header; ++ completion->reason = reason; ++ /* N.B. service_userdata is updated while processing AWAIT_COMPLETION */ ++ completion->service_userdata = user_service->service; ++ completion->bulk_userdata = bulk_userdata; ++ ++ if (reason == VCHIQ_SERVICE_CLOSED) { ++ /* Take an extra reference, to be held until ++ this CLOSED notification is delivered. */ ++ lock_service(user_service->service); ++ if (instance->use_close_delivered) ++ user_service->close_pending = 1; ++ } ++ ++ /* A write barrier is needed here to ensure that the entire completion ++ record is written out before the insert point. */ ++ wmb(); ++ ++ if (reason == VCHIQ_MESSAGE_AVAILABLE) ++ user_service->message_available_pos = ++ instance->completion_insert; ++ instance->completion_insert++; ++ ++ up(&instance->insert_event); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++/**************************************************************************** ++* ++* service_callback ++* ++***************************************************************************/ ++ ++static VCHIQ_STATUS_T ++service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, ++ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata) ++{ ++ /* How do we ensure the callback goes to the right client? ++ ** The service_user data points to a USER_SERVICE_T record containing ++ ** the original callback and the user state structure, which contains a ++ ** circular buffer for completion records. ++ */ ++ USER_SERVICE_T *user_service; ++ VCHIQ_SERVICE_T *service; ++ VCHIQ_INSTANCE_T instance; ++ DEBUG_INITIALISE(g_state.local) ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ ++ service = handle_to_service(handle); ++ BUG_ON(!service); ++ user_service = (USER_SERVICE_T *)service->base.userdata; ++ instance = user_service->instance; ++ ++ if (!instance || instance->closing) ++ return VCHIQ_SUCCESS; ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "service_callback - service %lx(%d,%p), reason %d, header %lx, " ++ "instance %lx, bulk_userdata %lx", ++ (unsigned long)user_service, ++ service->localport, user_service->userdata, ++ reason, (unsigned long)header, ++ (unsigned long)instance, (unsigned long)bulk_userdata); ++ ++ if (header && user_service->is_vchi) { ++ spin_lock(&msg_queue_spinlock); ++ while (user_service->msg_insert == ++ (user_service->msg_remove + MSG_QUEUE_SIZE)) { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); ++ vchiq_log_trace(vchiq_arm_log_level, ++ "service_callback - msg queue full"); ++ /* If there is no MESSAGE_AVAILABLE in the completion ++ ** queue, add one ++ */ ++ if ((user_service->message_available_pos - ++ instance->completion_remove) < 0) { ++ VCHIQ_STATUS_T status; ++ vchiq_log_info(vchiq_arm_log_level, ++ "Inserting extra MESSAGE_AVAILABLE"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ status = add_completion(instance, reason, ++ NULL, user_service, bulk_userdata); ++ if (status != VCHIQ_SUCCESS) { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return status; ++ } ++ } ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ if (down_interruptible(&user_service->remove_event) ++ != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback interrupted"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback closing"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ spin_lock(&msg_queue_spinlock); ++ } ++ ++ user_service->msg_queue[user_service->msg_insert & ++ (MSG_QUEUE_SIZE - 1)] = header; ++ user_service->msg_insert++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ up(&user_service->insert_event); ++ ++ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if ++ ** there is a MESSAGE_AVAILABLE in the completion queue then ++ ** bypass the completion queue. ++ */ ++ if (((user_service->message_available_pos - ++ instance->completion_remove) >= 0) || ++ user_service->dequeue_pending) { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ user_service->dequeue_pending = 0; ++ return VCHIQ_SUCCESS; ++ } ++ ++ header = NULL; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ ++ return add_completion(instance, reason, header, user_service, ++ bulk_userdata); ++} ++ ++/**************************************************************************** ++* ++* user_service_free ++* ++***************************************************************************/ ++static void ++user_service_free(void *userdata) ++{ ++ kfree(userdata); ++} ++ ++/**************************************************************************** ++* ++* close_delivered ++* ++***************************************************************************/ ++static void close_delivered(USER_SERVICE_T *user_service) ++{ ++ vchiq_log_info(vchiq_arm_log_level, ++ "close_delivered(handle=%x)", ++ user_service->service->handle); ++ ++ if (user_service->close_pending) { ++ /* Allow the underlying service to be culled */ ++ unlock_service(user_service->service); ++ ++ /* Wake the user-thread blocked in close_ or remove_service */ ++ up(&user_service->close_event); ++ ++ user_service->close_pending = 0; ++ } ++} ++ ++/**************************************************************************** ++* ++* vchiq_ioctl ++* ++***************************************************************************/ ++static long ++vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_SERVICE_T *service = NULL; ++ long ret = 0; ++ int i, rc; ++ DEBUG_INITIALISE(g_state.local) ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "vchiq_ioctl - instance %x, cmd %s, arg %lx", ++ (unsigned int)instance, ++ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) && ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ? ++ ioctl_names[_IOC_NR(cmd)] : "", arg); ++ ++ switch (cmd) { ++ case VCHIQ_IOC_SHUTDOWN: ++ if (!instance->connected) ++ break; ++ ++ /* Remove all services */ ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ status = vchiq_remove_service(service->handle); ++ unlock_service(service); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ service = NULL; ++ ++ if (status == VCHIQ_SUCCESS) { ++ /* Wake the completion thread and ask it to exit */ ++ instance->closing = 1; ++ up(&instance->insert_event); ++ } ++ ++ break; ++ ++ case VCHIQ_IOC_CONNECT: ++ if (instance->connected) { ++ ret = -EINVAL; ++ break; ++ } ++ rc = mutex_lock_interruptible(&instance->state->mutex); ++ if (rc != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq: connect: could not lock mutex for " ++ "state %d: %d", ++ instance->state->id, rc); ++ ret = -EINTR; ++ break; ++ } ++ status = vchiq_connect_internal(instance->state, instance); ++ mutex_unlock(&instance->state->mutex); ++ ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; ++ else ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq: could not connect: %d", status); ++ break; ++ ++ case VCHIQ_IOC_CREATE_SERVICE: { ++ VCHIQ_CREATE_SERVICE_T args; ++ USER_SERVICE_T *user_service = NULL; ++ void *userdata; ++ int srvstate; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ user_service = kmalloc(sizeof(USER_SERVICE_T), GFP_KERNEL); ++ if (!user_service) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ if (args.is_open) { ++ if (!instance->connected) { ++ ret = -ENOTCONN; ++ kfree(user_service); ++ break; ++ } ++ srvstate = VCHIQ_SRVSTATE_OPENING; ++ } else { ++ srvstate = ++ instance->connected ? ++ VCHIQ_SRVSTATE_LISTENING : ++ VCHIQ_SRVSTATE_HIDDEN; ++ } ++ ++ userdata = args.params.userdata; ++ args.params.callback = service_callback; ++ args.params.userdata = user_service; ++ service = vchiq_add_service_internal( ++ instance->state, ++ &args.params, srvstate, ++ instance, user_service_free); ++ ++ if (service != NULL) { ++ user_service->service = service; ++ user_service->userdata = userdata; ++ user_service->instance = instance; ++ user_service->is_vchi = (args.is_vchi != 0); ++ user_service->dequeue_pending = 0; ++ user_service->close_pending = 0; ++ user_service->message_available_pos = ++ instance->completion_remove - 1; ++ user_service->msg_insert = 0; ++ user_service->msg_remove = 0; ++ sema_init(&user_service->insert_event, 0); ++ sema_init(&user_service->remove_event, 0); ++ sema_init(&user_service->close_event, 0); ++ ++ if (args.is_open) { ++ status = vchiq_open_service_internal ++ (service, instance->pid); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_remove_service(service->handle); ++ service = NULL; ++ ret = (status == VCHIQ_RETRY) ? ++ -EINTR : -EIO; ++ break; ++ } ++ } ++ ++ if (copy_to_user((void __user *) ++ &(((VCHIQ_CREATE_SERVICE_T __user *) ++ arg)->handle), ++ (const void *)&service->handle, ++ sizeof(service->handle)) != 0) { ++ ret = -EFAULT; ++ vchiq_remove_service(service->handle); ++ } ++ ++ service = NULL; ++ } else { ++ ret = -EEXIST; ++ kfree(user_service); ++ } ++ } break; ++ ++ case VCHIQ_IOC_CLOSE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ /* close_pending is false on first entry, and when the ++ wait in vchiq_close_service has been interrupted. */ ++ if (!user_service->close_pending) { ++ status = vchiq_close_service(service->handle); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ ++ /* close_pending is true once the underlying service ++ has been closed until the client library calls the ++ CLOSE_DELIVERED ioctl, signalling close_event. */ ++ if (user_service->close_pending && ++ down_interruptible(&user_service->close_event)) ++ status = VCHIQ_RETRY; ++ } ++ else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_REMOVE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ /* close_pending is false on first entry, and when the ++ wait in vchiq_close_service has been interrupted. */ ++ if (!user_service->close_pending) { ++ status = vchiq_remove_service(service->handle); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ ++ /* close_pending is true once the underlying service ++ has been closed until the client library calls the ++ CLOSE_DELIVERED ioctl, signalling close_event. */ ++ if (user_service->close_pending && ++ down_interruptible(&user_service->close_event)) ++ status = VCHIQ_RETRY; ++ } ++ else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_USE_SERVICE: ++ case VCHIQ_IOC_RELEASE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) { ++ status = (cmd == VCHIQ_IOC_USE_SERVICE) ? ++ vchiq_use_service_internal(service) : ++ vchiq_release_service_internal(service); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s: cmd %s returned error %d for " ++ "service %c%c%c%c:%03d", ++ __func__, ++ (cmd == VCHIQ_IOC_USE_SERVICE) ? ++ "VCHIQ_IOC_USE_SERVICE" : ++ "VCHIQ_IOC_RELEASE_SERVICE", ++ status, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->client_id); ++ ret = -EINVAL; ++ } ++ } else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_QUEUE_MESSAGE: { ++ VCHIQ_QUEUE_MESSAGE_T args; ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ ++ if ((service != NULL) && (args.count <= MAX_ELEMENTS)) { ++ /* Copy elements into kernel space */ ++ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS]; ++ if (copy_from_user(elements, args.elements, ++ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0) ++ status = vchiq_queue_message ++ (args.handle, ++ elements, args.count); ++ else ++ ret = -EFAULT; ++ } else { ++ ret = -EINVAL; ++ } ++ } break; ++ ++ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT: ++ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: { ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ struct bulk_waiter_node *waiter = NULL; ++ VCHIQ_BULK_DIR_T dir = ++ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ? ++ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ if (args.mode == VCHIQ_BULK_MODE_BLOCKING) { ++ waiter = kzalloc(sizeof(struct bulk_waiter_node), ++ GFP_KERNEL); ++ if (!waiter) { ++ ret = -ENOMEM; ++ break; ++ } ++ args.userdata = &waiter->bulk_waiter; ++ } else if (args.mode == VCHIQ_BULK_MODE_WAITING) { ++ struct list_head *pos; ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_for_each(pos, &instance->bulk_waiter_list) { ++ if (list_entry(pos, struct bulk_waiter_node, ++ list)->pid == current->pid) { ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ break; ++ } ++ ++ } ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ if (!waiter) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "no bulk_waiter found for pid %d", ++ current->pid); ++ ret = -ESRCH; ++ break; ++ } ++ vchiq_log_info(vchiq_arm_log_level, ++ "found bulk_waiter %x for pid %d", ++ (unsigned int)waiter, current->pid); ++ args.userdata = &waiter->bulk_waiter; ++ } ++ status = vchiq_bulk_transfer ++ (args.handle, ++ VCHI_MEM_HANDLE_INVALID, ++ args.data, args.size, ++ args.userdata, args.mode, ++ dir); ++ if (!waiter) ++ break; ++ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || ++ !waiter->bulk_waiter.bulk) { ++ if (waiter->bulk_waiter.bulk) { ++ /* Cancel the signal when the transfer ++ ** completes. */ ++ spin_lock(&bulk_waiter_spinlock); ++ waiter->bulk_waiter.bulk->userdata = NULL; ++ spin_unlock(&bulk_waiter_spinlock); ++ } ++ kfree(waiter); ++ } else { ++ const VCHIQ_BULK_MODE_T mode_waiting = ++ VCHIQ_BULK_MODE_WAITING; ++ waiter->pid = current->pid; ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_add(&waiter->list, &instance->bulk_waiter_list); ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ vchiq_log_info(vchiq_arm_log_level, ++ "saved bulk_waiter %x for pid %d", ++ (unsigned int)waiter, current->pid); ++ ++ if (copy_to_user((void __user *) ++ &(((VCHIQ_QUEUE_BULK_TRANSFER_T __user *) ++ arg)->mode), ++ (const void *)&mode_waiting, ++ sizeof(mode_waiting)) != 0) ++ ret = -EFAULT; ++ } ++ } break; ++ ++ case VCHIQ_IOC_AWAIT_COMPLETION: { ++ VCHIQ_AWAIT_COMPLETION_T args; ++ ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ if (!instance->connected) { ++ ret = -ENOTCONN; ++ break; ++ } ++ ++ if (copy_from_user(&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ mutex_lock(&instance->completion_mutex); ++ ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ while ((instance->completion_remove == ++ instance->completion_insert) ++ && !instance->closing) { ++ int rc; ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ mutex_unlock(&instance->completion_mutex); ++ rc = down_interruptible(&instance->insert_event); ++ mutex_lock(&instance->completion_mutex); ++ if (rc != 0) { ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ vchiq_log_info(vchiq_arm_log_level, ++ "AWAIT_COMPLETION interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ } ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ ++ /* A read memory barrier is needed to stop prefetch of a stale ++ ** completion record ++ */ ++ rmb(); ++ ++ if (ret == 0) { ++ int msgbufcount = args.msgbufcount; ++ for (ret = 0; ret < args.count; ret++) { ++ VCHIQ_COMPLETION_DATA_T *completion; ++ VCHIQ_SERVICE_T *service; ++ USER_SERVICE_T *user_service; ++ VCHIQ_HEADER_T *header; ++ if (instance->completion_remove == ++ instance->completion_insert) ++ break; ++ completion = &instance->completions[ ++ instance->completion_remove & ++ (MAX_COMPLETIONS - 1)]; ++ ++ service = completion->service_userdata; ++ user_service = service->base.userdata; ++ completion->service_userdata = ++ user_service->userdata; ++ ++ header = completion->header; ++ if (header) { ++ void __user *msgbuf; ++ int msglen; ++ ++ msglen = header->size + ++ sizeof(VCHIQ_HEADER_T); ++ /* This must be a VCHIQ-style service */ ++ if (args.msgbufsize < msglen) { ++ vchiq_log_error( ++ vchiq_arm_log_level, ++ "header %x: msgbufsize" ++ " %x < msglen %x", ++ (unsigned int)header, ++ args.msgbufsize, ++ msglen); ++ WARN(1, "invalid message " ++ "size\n"); ++ if (ret == 0) ++ ret = -EMSGSIZE; ++ break; ++ } ++ if (msgbufcount <= 0) ++ /* Stall here for lack of a ++ ** buffer for the message. */ ++ break; ++ /* Get the pointer from user space */ ++ msgbufcount--; ++ if (copy_from_user(&msgbuf, ++ (const void __user *) ++ &args.msgbufs[msgbufcount], ++ sizeof(msgbuf)) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Copy the message to user space */ ++ if (copy_to_user(msgbuf, header, ++ msglen) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Now it has been copied, the message ++ ** can be released. */ ++ vchiq_release_message(service->handle, ++ header); ++ ++ /* The completion must point to the ++ ** msgbuf. */ ++ completion->header = msgbuf; ++ } ++ ++ if ((completion->reason == ++ VCHIQ_SERVICE_CLOSED) && ++ !instance->use_close_delivered) ++ unlock_service(service); ++ ++ if (copy_to_user((void __user *)( ++ (size_t)args.buf + ++ ret * sizeof(VCHIQ_COMPLETION_DATA_T)), ++ completion, ++ sizeof(VCHIQ_COMPLETION_DATA_T)) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ instance->completion_remove++; ++ } ++ ++ if (msgbufcount != args.msgbufcount) { ++ if (copy_to_user((void __user *) ++ &((VCHIQ_AWAIT_COMPLETION_T *)arg)-> ++ msgbufcount, ++ &msgbufcount, ++ sizeof(msgbufcount)) != 0) { ++ ret = -EFAULT; ++ } ++ } ++ } ++ ++ if (ret != 0) ++ up(&instance->remove_event); ++ mutex_unlock(&instance->completion_mutex); ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ } break; ++ ++ case VCHIQ_IOC_DEQUEUE_MESSAGE: { ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ USER_SERVICE_T *user_service; ++ VCHIQ_HEADER_T *header; ++ ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ user_service = (USER_SERVICE_T *)service->base.userdata; ++ if (user_service->is_vchi == 0) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ spin_lock(&msg_queue_spinlock); ++ if (user_service->msg_remove == user_service->msg_insert) { ++ if (!args.blocking) { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ ret = -EWOULDBLOCK; ++ break; ++ } ++ user_service->dequeue_pending = 1; ++ do { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (down_interruptible( ++ &user_service->insert_event) != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "DEQUEUE_MESSAGE interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ spin_lock(&msg_queue_spinlock); ++ } while (user_service->msg_remove == ++ user_service->msg_insert); ++ ++ if (ret) ++ break; ++ } ++ ++ BUG_ON((int)(user_service->msg_insert - ++ user_service->msg_remove) < 0); ++ ++ header = user_service->msg_queue[user_service->msg_remove & ++ (MSG_QUEUE_SIZE - 1)]; ++ user_service->msg_remove++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ up(&user_service->remove_event); ++ if (header == NULL) ++ ret = -ENOTCONN; ++ else if (header->size <= args.bufsize) { ++ /* Copy to user space if msgbuf is not NULL */ ++ if ((args.buf == NULL) || ++ (copy_to_user((void __user *)args.buf, ++ header->data, ++ header->size) == 0)) { ++ ret = header->size; ++ vchiq_release_message( ++ service->handle, ++ header); ++ } else ++ ret = -EFAULT; ++ } else { ++ vchiq_log_error(vchiq_arm_log_level, ++ "header %x: bufsize %x < size %x", ++ (unsigned int)header, args.bufsize, ++ header->size); ++ WARN(1, "invalid size\n"); ++ ret = -EMSGSIZE; ++ } ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ } break; ++ ++ case VCHIQ_IOC_GET_CLIENT_ID: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ ret = vchiq_get_client_id(handle); ++ } break; ++ ++ case VCHIQ_IOC_GET_CONFIG: { ++ VCHIQ_GET_CONFIG_T args; ++ VCHIQ_CONFIG_T config; ++ ++ if (copy_from_user(&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ if (args.config_size > sizeof(config)) { ++ ret = -EINVAL; ++ break; ++ } ++ status = vchiq_get_config(instance, args.config_size, &config); ++ if (status == VCHIQ_SUCCESS) { ++ if (copy_to_user((void __user *)args.pconfig, ++ &config, args.config_size) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ } ++ } break; ++ ++ case VCHIQ_IOC_SET_SERVICE_OPTION: { ++ VCHIQ_SET_SERVICE_OPTION_T args; ++ ++ if (copy_from_user( ++ &args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ status = vchiq_set_service_option( ++ args.handle, args.option, args.value); ++ } break; ++ ++ case VCHIQ_IOC_DUMP_PHYS_MEM: { ++ VCHIQ_DUMP_MEM_T args; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ dump_phys_mem(args.virt_addr, args.num_bytes); ++ } break; ++ ++ case VCHIQ_IOC_LIB_VERSION: { ++ unsigned int lib_version = (unsigned int)arg; ++ ++ if (lib_version < VCHIQ_VERSION_MIN) ++ ret = -EINVAL; ++ else if (lib_version >= VCHIQ_VERSION_CLOSE_DELIVERED) ++ instance->use_close_delivered = 1; ++ } break; ++ ++ case VCHIQ_IOC_CLOSE_DELIVERED: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_closed_service_for_instance(instance, handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ close_delivered(user_service); ++ } ++ else ++ ret = -EINVAL; ++ } break; ++ ++ default: ++ ret = -ENOTTY; ++ break; ++ } ++ ++ if (service) ++ unlock_service(service); ++ ++ if (ret == 0) { ++ if (status == VCHIQ_ERROR) ++ ret = -EIO; ++ else if (status == VCHIQ_RETRY) ++ ret = -EINTR; ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) && ++ (ret != -EWOULDBLOCK)) ++ vchiq_log_info(vchiq_arm_log_level, ++ " ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ++ ioctl_names[_IOC_NR(cmd)] : ++ "", ++ status, ret); ++ else ++ vchiq_log_trace(vchiq_arm_log_level, ++ " ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ++ ioctl_names[_IOC_NR(cmd)] : ++ "", ++ status, ret); ++ ++ return ret; ++} ++ ++/**************************************************************************** ++* ++* vchiq_open ++* ++***************************************************************************/ ++ ++static int ++vchiq_open(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode) & 0x0f; ++ vchiq_log_info(vchiq_arm_log_level, "vchiq_open"); ++ switch (dev) { ++ case VCHIQ_MINOR: { ++ int ret; ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ VCHIQ_INSTANCE_T instance; ++ ++ if (!state) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq has no connection to VideoCore"); ++ return -ENOTCONN; ++ } ++ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) ++ return -ENOMEM; ++ ++ instance->state = state; ++ instance->pid = current->tgid; ++ ++ ret = vchiq_debugfs_add_instance(instance); ++ if (ret != 0) { ++ kfree(instance); ++ return ret; ++ } ++ ++ sema_init(&instance->insert_event, 0); ++ sema_init(&instance->remove_event, 0); ++ mutex_init(&instance->completion_mutex); ++ mutex_init(&instance->bulk_waiter_list_mutex); ++ INIT_LIST_HEAD(&instance->bulk_waiter_list); ++ ++ file->private_data = instance; ++ } break; ++ ++ default: ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unknown minor device: %d", dev); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vchiq_release ++* ++***************************************************************************/ ++ ++static int ++vchiq_release(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode) & 0x0f; ++ int ret = 0; ++ switch (dev) { ++ case VCHIQ_MINOR: { ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ VCHIQ_SERVICE_T *service; ++ int i; ++ ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq_release: instance=%lx", ++ (unsigned long)instance); ++ ++ if (!state) { ++ ret = -EPERM; ++ goto out; ++ } ++ ++ /* Ensure videocore is awake to allow termination. */ ++ vchiq_use_internal(instance->state, NULL, ++ USE_TYPE_VCHIQ); ++ ++ mutex_lock(&instance->completion_mutex); ++ ++ /* Wake the completion thread and ask it to exit */ ++ instance->closing = 1; ++ up(&instance->insert_event); ++ ++ mutex_unlock(&instance->completion_mutex); ++ ++ /* Wake the slot handler if the completion queue is full. */ ++ up(&instance->remove_event); ++ ++ /* Mark all services for termination... */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ USER_SERVICE_T *user_service = service->base.userdata; ++ ++ /* Wake the slot handler if the msg queue is full. */ ++ up(&user_service->remove_event); ++ ++ vchiq_terminate_service_internal(service); ++ unlock_service(service); ++ } ++ ++ /* ...and wait for them to die */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, &i)) ++ != NULL) { ++ USER_SERVICE_T *user_service = service->base.userdata; ++ ++ down(&service->remove_event); ++ ++ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); ++ ++ spin_lock(&msg_queue_spinlock); ++ ++ while (user_service->msg_remove != ++ user_service->msg_insert) { ++ VCHIQ_HEADER_T *header = user_service-> ++ msg_queue[user_service->msg_remove & ++ (MSG_QUEUE_SIZE - 1)]; ++ user_service->msg_remove++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ if (header) ++ vchiq_release_message( ++ service->handle, ++ header); ++ spin_lock(&msg_queue_spinlock); ++ } ++ ++ spin_unlock(&msg_queue_spinlock); ++ ++ unlock_service(service); ++ } ++ ++ /* Release any closed services */ ++ while (instance->completion_remove != ++ instance->completion_insert) { ++ VCHIQ_COMPLETION_DATA_T *completion; ++ VCHIQ_SERVICE_T *service; ++ completion = &instance->completions[ ++ instance->completion_remove & ++ (MAX_COMPLETIONS - 1)]; ++ service = completion->service_userdata; ++ if (completion->reason == VCHIQ_SERVICE_CLOSED) ++ { ++ USER_SERVICE_T *user_service = ++ service->base.userdata; ++ ++ /* Wake any blocked user-thread */ ++ if (instance->use_close_delivered) ++ up(&user_service->close_event); ++ unlock_service(service); ++ } ++ instance->completion_remove++; ++ } ++ ++ /* Release the PEER service count. */ ++ vchiq_release_internal(instance->state, NULL); ++ ++ { ++ struct list_head *pos, *next; ++ list_for_each_safe(pos, next, ++ &instance->bulk_waiter_list) { ++ struct bulk_waiter_node *waiter; ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ vchiq_log_info(vchiq_arm_log_level, ++ "bulk_waiter - cleaned up %x " ++ "for pid %d", ++ (unsigned int)waiter, waiter->pid); ++ kfree(waiter); ++ } ++ } ++ ++ vchiq_debugfs_remove_instance(instance); ++ ++ kfree(instance); ++ file->private_data = NULL; ++ } break; ++ ++ default: ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unknown minor device: %d", dev); ++ ret = -ENXIO; ++ } ++ ++out: ++ return ret; ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump ++* ++***************************************************************************/ ++ ++void ++vchiq_dump(void *dump_context, const char *str, int len) ++{ ++ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context; ++ ++ if (context->actual < context->space) { ++ int copy_bytes; ++ if (context->offset > 0) { ++ int skip_bytes = min(len, (int)context->offset); ++ str += skip_bytes; ++ len -= skip_bytes; ++ context->offset -= skip_bytes; ++ if (context->offset > 0) ++ return; ++ } ++ copy_bytes = min(len, (int)(context->space - context->actual)); ++ if (copy_bytes == 0) ++ return; ++ if (copy_to_user(context->buf + context->actual, str, ++ copy_bytes)) ++ context->actual = -EFAULT; ++ context->actual += copy_bytes; ++ len -= copy_bytes; ++ ++ /* If tne terminating NUL is included in the length, then it ++ ** marks the end of a line and should be replaced with a ++ ** carriage return. */ ++ if ((len == 0) && (str[copy_bytes - 1] == '\0')) { ++ char cr = '\n'; ++ if (copy_to_user(context->buf + context->actual - 1, ++ &cr, 1)) ++ context->actual = -EFAULT; ++ } ++ } ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump_platform_instance_state ++* ++***************************************************************************/ ++ ++void ++vchiq_dump_platform_instances(void *dump_context) ++{ ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ char buf[80]; ++ int len; ++ int i; ++ ++ /* There is no list of instances, so instead scan all services, ++ marking those that have been dumped. */ ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service && (service->base.callback == service_callback)) { ++ instance = service->instance; ++ if (instance) ++ instance->mark = 0; ++ } ++ } ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service && (service->base.callback == service_callback)) { ++ instance = service->instance; ++ if (instance && !instance->mark) { ++ len = snprintf(buf, sizeof(buf), ++ "Instance %x: pid %d,%s completions " ++ "%d/%d", ++ (unsigned int)instance, instance->pid, ++ instance->connected ? " connected, " : ++ "", ++ instance->completion_insert - ++ instance->completion_remove, ++ MAX_COMPLETIONS); ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ instance->mark = 1; ++ } ++ } ++ } ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump_platform_service_state ++* ++***************************************************************************/ ++ ++void ++vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service) ++{ ++ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata; ++ char buf[80]; ++ int len; ++ ++ len = snprintf(buf, sizeof(buf), " instance %x", ++ (unsigned int)service->instance); ++ ++ if ((service->base.callback == service_callback) && ++ user_service->is_vchi) { ++ len += snprintf(buf + len, sizeof(buf) - len, ++ ", %d/%d messages", ++ user_service->msg_insert - user_service->msg_remove, ++ MSG_QUEUE_SIZE); ++ ++ if (user_service->dequeue_pending) ++ len += snprintf(buf + len, sizeof(buf) - len, ++ " (dequeue pending)"); ++ } ++ ++ vchiq_dump(dump_context, buf, len + 1); ++} ++ ++/**************************************************************************** ++* ++* dump_user_mem ++* ++***************************************************************************/ ++ ++static void ++dump_phys_mem(void *virt_addr, uint32_t num_bytes) ++{ ++ int rc; ++ uint8_t *end_virt_addr = virt_addr + num_bytes; ++ int num_pages; ++ int offset; ++ int end_offset; ++ int page_idx; ++ int prev_idx; ++ struct page *page; ++ struct page **pages; ++ uint8_t *kmapped_virt_ptr; ++ ++ /* Align virtAddr and endVirtAddr to 16 byte boundaries. */ ++ ++ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL); ++ end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) & ++ ~0x0fuL); ++ ++ offset = (int)(long)virt_addr & (PAGE_SIZE - 1); ++ end_offset = (int)(long)end_virt_addr & (PAGE_SIZE - 1); ++ ++ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL); ++ if (pages == NULL) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to allocation memory for %d pages\n", ++ num_pages); ++ return; ++ } ++ ++ down_read(¤t->mm->mmap_sem); ++ rc = get_user_pages(current, /* task */ ++ current->mm, /* mm */ ++ (unsigned long)virt_addr, /* start */ ++ num_pages, /* len */ ++ 0, /* write */ ++ 0, /* force */ ++ pages, /* pages (array of page pointers) */ ++ NULL); /* vmas */ ++ up_read(¤t->mm->mmap_sem); ++ ++ prev_idx = -1; ++ page = NULL; ++ ++ while (offset < end_offset) { ++ ++ int page_offset = offset % PAGE_SIZE; ++ page_idx = offset / PAGE_SIZE; ++ ++ if (page_idx != prev_idx) { ++ ++ if (page != NULL) ++ kunmap(page); ++ page = pages[page_idx]; ++ kmapped_virt_ptr = kmap(page); ++ ++ prev_idx = page_idx; ++ } ++ ++ if (vchiq_arm_log_level >= VCHIQ_LOG_TRACE) ++ vchiq_log_dump_mem("ph", ++ (uint32_t)(unsigned long)&kmapped_virt_ptr[ ++ page_offset], ++ &kmapped_virt_ptr[page_offset], 16); ++ ++ offset += 16; ++ } ++ if (page != NULL) ++ kunmap(page); ++ ++ for (page_idx = 0; page_idx < num_pages; page_idx++) ++ page_cache_release(pages[page_idx]); ++ ++ kfree(pages); ++} ++ ++/**************************************************************************** ++* ++* vchiq_read ++* ++***************************************************************************/ ++ ++static ssize_t ++vchiq_read(struct file *file, char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ DUMP_CONTEXT_T context; ++ context.buf = buf; ++ context.actual = 0; ++ context.space = count; ++ context.offset = *ppos; ++ ++ vchiq_dump_state(&context, &g_state); ++ ++ *ppos += context.actual; ++ ++ return context.actual; ++} ++ ++VCHIQ_STATE_T * ++vchiq_get_state(void) ++{ ++ ++ if (g_state.remote == NULL) ++ printk(KERN_ERR "%s: g_state.remote == NULL\n", __func__); ++ else if (g_state.remote->initialised != 1) ++ printk(KERN_NOTICE "%s: g_state.remote->initialised != 1 (%d)\n", ++ __func__, g_state.remote->initialised); ++ ++ return ((g_state.remote != NULL) && ++ (g_state.remote->initialised == 1)) ? &g_state : NULL; ++} ++ ++static const struct file_operations ++vchiq_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = vchiq_ioctl, ++ .open = vchiq_open, ++ .release = vchiq_release, ++ .read = vchiq_read ++}; ++ ++/* ++ * Autosuspend related functionality ++ */ ++ ++int ++vchiq_videocore_wanted(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ if (!arm_state) ++ /* autosuspend not supported - always return wanted */ ++ return 1; ++ else if (arm_state->blocked_count) ++ return 1; ++ else if (!arm_state->videocore_use_count) ++ /* usage count zero - check for override unless we're forcing */ ++ if (arm_state->resume_blocked) ++ return 0; ++ else ++ return vchiq_platform_videocore_wanted(state); ++ else ++ /* non-zero usage count - videocore still required */ ++ return 1; ++} ++ ++static VCHIQ_STATUS_T ++vchiq_keepalive_vchiq_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, ++ VCHIQ_SERVICE_HANDLE_T service_user, ++ void *bulk_user) ++{ ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s callback reason %d", __func__, reason); ++ return 0; ++} ++ ++static int ++vchiq_keepalive_thread_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ VCHIQ_STATUS_T status; ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_SERVICE_HANDLE_T ka_handle; ++ ++ VCHIQ_SERVICE_PARAMS_T params = { ++ .fourcc = VCHIQ_MAKE_FOURCC('K', 'E', 'E', 'P'), ++ .callback = vchiq_keepalive_vchiq_callback, ++ .version = KEEPALIVE_VER, ++ .version_min = KEEPALIVE_VER_MIN ++ }; ++ ++ status = vchiq_initialise(&instance); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_initialise failed %d", __func__, status); ++ goto exit; ++ } ++ ++ status = vchiq_connect(instance); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_connect failed %d", __func__, status); ++ goto shutdown; ++ } ++ ++ status = vchiq_add_service(instance, ¶ms, &ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_open_service failed %d", __func__, status); ++ goto shutdown; ++ } ++ ++ while (1) { ++ long rc = 0, uc = 0; ++ if (wait_for_completion_interruptible(&arm_state->ka_evt) ++ != 0) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s interrupted", __func__); ++ flush_signals(current); ++ continue; ++ } ++ ++ /* read and clear counters. Do release_count then use_count to ++ * prevent getting more releases than uses */ ++ rc = atomic_xchg(&arm_state->ka_release_count, 0); ++ uc = atomic_xchg(&arm_state->ka_use_count, 0); ++ ++ /* Call use/release service the requisite number of times. ++ * Process use before release so use counts don't go negative */ ++ while (uc--) { ++ atomic_inc(&arm_state->ka_use_ack_count); ++ status = vchiq_use_service(ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_use_service error %d", ++ __func__, status); ++ } ++ } ++ while (rc--) { ++ status = vchiq_release_service(ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_release_service error %d", ++ __func__, status); ++ } ++ } ++ } ++ ++shutdown: ++ vchiq_shutdown(instance); ++exit: ++ return 0; ++} ++ ++ ++ ++VCHIQ_STATUS_T ++vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (arm_state) { ++ rwlock_init(&arm_state->susp_res_lock); ++ ++ init_completion(&arm_state->ka_evt); ++ atomic_set(&arm_state->ka_use_count, 0); ++ atomic_set(&arm_state->ka_use_ack_count, 0); ++ atomic_set(&arm_state->ka_release_count, 0); ++ ++ init_completion(&arm_state->vc_suspend_complete); ++ ++ init_completion(&arm_state->vc_resume_complete); ++ /* Initialise to 'done' state. We only want to block on resume ++ * completion while videocore is suspended. */ ++ set_resume_state(arm_state, VC_RESUME_RESUMED); ++ ++ init_completion(&arm_state->resume_blocker); ++ /* Initialise to 'done' state. We only want to block on this ++ * completion while resume is blocked */ ++ complete_all(&arm_state->resume_blocker); ++ ++ init_completion(&arm_state->blocked_blocker); ++ /* Initialise to 'done' state. We only want to block on this ++ * completion while things are waiting on the resume blocker */ ++ complete_all(&arm_state->blocked_blocker); ++ ++ arm_state->suspend_timer_timeout = SUSPEND_TIMER_TIMEOUT_MS; ++ arm_state->suspend_timer_running = 0; ++ init_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer.data = (unsigned long)(state); ++ arm_state->suspend_timer.function = suspend_timer_callback; ++ ++ arm_state->first_connect = 0; ++ ++ } ++ return status; ++} ++ ++/* ++** Functions to modify the state variables; ++** set_suspend_state ++** set_resume_state ++** ++** There are more state variables than we might like, so ensure they remain in ++** step. Suspend and resume state are maintained separately, since most of ++** these state machines can operate independently. However, there are a few ++** states where state transitions in one state machine cause a reset to the ++** other state machine. In addition, there are some completion events which ++** need to occur on state machine reset and end-state(s), so these are also ++** dealt with in these functions. ++** ++** In all states we set the state variable according to the input, but in some ++** cases we perform additional steps outlined below; ++** ++** VC_SUSPEND_IDLE - Initialise the suspend completion at the same time. ++** The suspend completion is completed after any suspend ++** attempt. When we reset the state machine we also reset ++** the completion. This reset occurs when videocore is ++** resumed, and also if we initiate suspend after a suspend ++** failure. ++** ++** VC_SUSPEND_IN_PROGRESS - This state is considered the point of no return for ++** suspend - ie from this point on we must try to suspend ++** before resuming can occur. We therefore also reset the ++** resume state machine to VC_RESUME_IDLE in this state. ++** ++** VC_SUSPEND_SUSPENDED - Suspend has completed successfully. Also call ++** complete_all on the suspend completion to notify ++** anything waiting for suspend to happen. ++** ++** VC_SUSPEND_REJECTED - Videocore rejected suspend. Videocore will also ++** initiate resume, so no need to alter resume state. ++** We call complete_all on the suspend completion to notify ++** of suspend rejection. ++** ++** VC_SUSPEND_FAILED - We failed to initiate videocore suspend. We notify the ++** suspend completion and reset the resume state machine. ++** ++** VC_RESUME_IDLE - Initialise the resume completion at the same time. The ++** resume completion is in it's 'done' state whenever ++** videcore is running. Therfore, the VC_RESUME_IDLE state ++** implies that videocore is suspended. ++** Hence, any thread which needs to wait until videocore is ++** running can wait on this completion - it will only block ++** if videocore is suspended. ++** ++** VC_RESUME_RESUMED - Resume has completed successfully. Videocore is running. ++** Call complete_all on the resume completion to unblock ++** any threads waiting for resume. Also reset the suspend ++** state machine to it's idle state. ++** ++** VC_RESUME_FAILED - Currently unused - no mechanism to fail resume exists. ++*/ ++ ++void ++set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_suspend_status new_state) ++{ ++ /* set the state in all cases */ ++ arm_state->vc_suspend_state = new_state; ++ ++ /* state specific additional actions */ ++ switch (new_state) { ++ case VC_SUSPEND_FORCE_CANCELED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_REJECTED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_FAILED: ++ complete_all(&arm_state->vc_suspend_complete); ++ arm_state->vc_resume_state = VC_RESUME_RESUMED; ++ complete_all(&arm_state->vc_resume_complete); ++ break; ++ case VC_SUSPEND_IDLE: ++ reinit_completion(&arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_REQUESTED: ++ break; ++ case VC_SUSPEND_IN_PROGRESS: ++ set_resume_state(arm_state, VC_RESUME_IDLE); ++ break; ++ case VC_SUSPEND_SUSPENDED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ default: ++ BUG(); ++ break; ++ } ++} ++ ++void ++set_resume_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_resume_status new_state) ++{ ++ /* set the state in all cases */ ++ arm_state->vc_resume_state = new_state; ++ ++ /* state specific additional actions */ ++ switch (new_state) { ++ case VC_RESUME_FAILED: ++ break; ++ case VC_RESUME_IDLE: ++ reinit_completion(&arm_state->vc_resume_complete); ++ break; ++ case VC_RESUME_REQUESTED: ++ break; ++ case VC_RESUME_IN_PROGRESS: ++ break; ++ case VC_RESUME_RESUMED: ++ complete_all(&arm_state->vc_resume_complete); ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ break; ++ default: ++ BUG(); ++ break; ++ } ++} ++ ++ ++/* should be called with the write lock held */ ++inline void ++start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ del_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer.expires = jiffies + ++ msecs_to_jiffies(arm_state-> ++ suspend_timer_timeout); ++ add_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer_running = 1; ++} ++ ++/* should be called with the write lock held */ ++static inline void ++stop_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ if (arm_state->suspend_timer_running) { ++ del_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer_running = 0; ++ } ++} ++ ++static inline int ++need_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ return (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) && ++ (arm_state->vc_resume_state < VC_RESUME_REQUESTED) && ++ vchiq_videocore_wanted(state); ++} ++ ++static int ++block_resume(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ int status = VCHIQ_SUCCESS; ++ const unsigned long timeout_val = ++ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS); ++ int resume_count = 0; ++ ++ /* Allow any threads which were blocked by the last force suspend to ++ * complete if they haven't already. Only give this one shot; if ++ * blocked_count is incremented after blocked_blocker is completed ++ * (which only happens when blocked_count hits 0) then those threads ++ * will have to wait until next time around */ ++ if (arm_state->blocked_count) { ++ reinit_completion(&arm_state->blocked_blocker); ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s wait for previously " ++ "blocked clients", __func__); ++ if (wait_for_completion_interruptible_timeout( ++ &arm_state->blocked_blocker, timeout_val) ++ <= 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s wait for " ++ "previously blocked clients failed" , __func__); ++ status = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s previously blocked " ++ "clients resumed", __func__); ++ write_lock_bh(&arm_state->susp_res_lock); ++ } ++ ++ /* We need to wait for resume to complete if it's in process */ ++ while (arm_state->vc_resume_state != VC_RESUME_RESUMED && ++ arm_state->vc_resume_state > VC_RESUME_IDLE) { ++ if (resume_count > 1) { ++ status = VCHIQ_ERROR; ++ vchiq_log_error(vchiq_susp_log_level, "%s waited too " ++ "many times for resume" , __func__); ++ goto out; ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s wait for resume", ++ __func__); ++ if (wait_for_completion_interruptible_timeout( ++ &arm_state->vc_resume_complete, timeout_val) ++ <= 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s wait for " ++ "resume failed (%s)", __func__, ++ resume_state_names[arm_state->vc_resume_state + ++ VC_RESUME_NUM_OFFSET]); ++ status = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s resumed", __func__); ++ write_lock_bh(&arm_state->susp_res_lock); ++ resume_count++; ++ } ++ reinit_completion(&arm_state->resume_blocker); ++ arm_state->resume_blocked = 1; ++ ++out: ++ return status; ++} ++ ++static inline void ++unblock_resume(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ complete_all(&arm_state->resume_blocker); ++ arm_state->resume_blocked = 0; ++} ++ ++/* Initiate suspend via slot handler. Should be called with the write lock ++ * held */ ++VCHIQ_STATUS_T ++vchiq_arm_vcsuspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ status = VCHIQ_SUCCESS; ++ ++ ++ switch (arm_state->vc_suspend_state) { ++ case VC_SUSPEND_REQUESTED: ++ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already " ++ "requested", __func__); ++ break; ++ case VC_SUSPEND_IN_PROGRESS: ++ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already in " ++ "progress", __func__); ++ break; ++ ++ default: ++ /* We don't expect to be in other states, so log but continue ++ * anyway */ ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s unexpected suspend state %s", __func__, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ /* fall through */ ++ case VC_SUSPEND_REJECTED: ++ case VC_SUSPEND_FAILED: ++ /* Ensure any idle state actions have been run */ ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ /* fall through */ ++ case VC_SUSPEND_IDLE: ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: suspending", __func__); ++ set_suspend_state(arm_state, VC_SUSPEND_REQUESTED); ++ /* kick the slot handler thread to initiate suspend */ ++ request_poll(state, NULL, 0); ++ break; ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); ++ return status; ++} ++ ++void ++vchiq_platform_check_suspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int susp = 0; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state == VC_SUSPEND_REQUESTED && ++ arm_state->vc_resume_state == VC_RESUME_RESUMED) { ++ set_suspend_state(arm_state, VC_SUSPEND_IN_PROGRESS); ++ susp = 1; ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (susp) ++ vchiq_platform_suspend(state); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; ++} ++ ++ ++static void ++output_timeout_error(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ char service_err[50] = ""; ++ int vc_use_count = arm_state->videocore_use_count; ++ int active_services = state->unused_service; ++ int i; ++ ++ if (!arm_state->videocore_use_count) { ++ snprintf(service_err, 50, " Videocore usecount is 0"); ++ goto output_msg; ++ } ++ for (i = 0; i < active_services; i++) { ++ VCHIQ_SERVICE_T *service_ptr = state->services[i]; ++ if (service_ptr && service_ptr->service_use_count && ++ (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) { ++ snprintf(service_err, 50, " %c%c%c%c(%d) service has " ++ "use count %d%s", VCHIQ_FOURCC_AS_4CHARS( ++ service_ptr->base.fourcc), ++ service_ptr->client_id, ++ service_ptr->service_use_count, ++ service_ptr->service_use_count == ++ vc_use_count ? "" : " (+ more)"); ++ break; ++ } ++ } ++ ++output_msg: ++ vchiq_log_error(vchiq_susp_log_level, ++ "timed out waiting for vc suspend (%d).%s", ++ arm_state->autosuspend_override, service_err); ++ ++} ++ ++/* Try to get videocore into suspended state, regardless of autosuspend state. ++** We don't actually force suspend, since videocore may get into a bad state ++** if we force suspend at a bad time. Instead, we wait for autosuspend to ++** determine a good point to suspend. If this doesn't happen within 100ms we ++** report failure. ++** ++** Returns VCHIQ_SUCCESS if videocore suspended successfully, VCHIQ_RETRY if ++** videocore failed to suspend in time or VCHIQ_ERROR if interrupted. ++*/ ++VCHIQ_STATUS_T ++vchiq_arm_force_suspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ long rc = 0; ++ int repeat = -1; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ ++ status = block_resume(arm_state); ++ if (status != VCHIQ_SUCCESS) ++ goto unlock; ++ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { ++ /* Already suspended - just block resume and exit */ ++ vchiq_log_info(vchiq_susp_log_level, "%s already suspended", ++ __func__); ++ status = VCHIQ_SUCCESS; ++ goto unlock; ++ } else if (arm_state->vc_suspend_state <= VC_SUSPEND_IDLE) { ++ /* initiate suspend immediately in the case that we're waiting ++ * for the timeout */ ++ stop_suspend_timer(arm_state); ++ if (!vchiq_videocore_wanted(state)) { ++ vchiq_log_info(vchiq_susp_log_level, "%s videocore " ++ "idle, initiating suspend", __func__); ++ status = vchiq_arm_vcsuspend(state); ++ } else if (arm_state->autosuspend_override < ++ FORCE_SUSPEND_FAIL_MAX) { ++ vchiq_log_info(vchiq_susp_log_level, "%s letting " ++ "videocore go idle", __func__); ++ status = VCHIQ_SUCCESS; ++ } else { ++ vchiq_log_warning(vchiq_susp_log_level, "%s failed too " ++ "many times - attempting suspend", __func__); ++ status = vchiq_arm_vcsuspend(state); ++ } ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, "%s videocore suspend " ++ "in progress - wait for completion", __func__); ++ status = VCHIQ_SUCCESS; ++ } ++ ++ /* Wait for suspend to happen due to system idle (not forced..) */ ++ if (status != VCHIQ_SUCCESS) ++ goto unblock_resume; ++ ++ do { ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ rc = wait_for_completion_interruptible_timeout( ++ &arm_state->vc_suspend_complete, ++ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS)); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (rc < 0) { ++ vchiq_log_warning(vchiq_susp_log_level, "%s " ++ "interrupted waiting for suspend", __func__); ++ status = VCHIQ_ERROR; ++ goto unblock_resume; ++ } else if (rc == 0) { ++ if (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) { ++ /* Repeat timeout once if in progress */ ++ if (repeat < 0) { ++ repeat = 1; ++ continue; ++ } ++ } ++ arm_state->autosuspend_override++; ++ output_timeout_error(state); ++ ++ status = VCHIQ_RETRY; ++ goto unblock_resume; ++ } ++ } while (0 < (repeat--)); ++ ++ /* Check and report state in case we need to abort ARM suspend */ ++ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED) { ++ status = VCHIQ_RETRY; ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s videocore suspend failed (state %s)", __func__, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ /* Reset the state only if it's still in an error state. ++ * Something could have already initiated another suspend. */ ++ if (arm_state->vc_suspend_state < VC_SUSPEND_IDLE) ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ ++ goto unblock_resume; ++ } ++ ++ /* successfully suspended - unlock and exit */ ++ goto unlock; ++ ++unblock_resume: ++ /* all error states need to unblock resume before exit */ ++ unblock_resume(arm_state); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); ++ return status; ++} ++ ++void ++vchiq_check_suspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED && ++ arm_state->first_connect && ++ !vchiq_videocore_wanted(state)) { ++ vchiq_arm_vcsuspend(state); ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; ++} ++ ++ ++int ++vchiq_arm_allow_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int resume = 0; ++ int ret = -1; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ unblock_resume(arm_state); ++ resume = vchiq_check_resume(state); ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (resume) { ++ if (wait_for_completion_interruptible( ++ &arm_state->vc_resume_complete) < 0) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s interrupted", __func__); ++ /* failed, cannot accurately derive suspend ++ * state, so exit early. */ ++ goto out; ++ } ++ } ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: Videocore remains suspended", __func__); ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: Videocore resumed", __func__); ++ ret = 0; ++ } ++ read_unlock_bh(&arm_state->susp_res_lock); ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; ++} ++ ++/* This function should be called with the write lock held */ ++int ++vchiq_check_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int resume = 0; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ if (need_resume(state)) { ++ set_resume_state(arm_state, VC_RESUME_REQUESTED); ++ request_poll(state, NULL, 0); ++ resume = 1; ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return resume; ++} ++ ++void ++vchiq_platform_check_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int res = 0; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->wake_address == 0) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: already awake", __func__); ++ goto unlock; ++ } ++ if (arm_state->vc_resume_state == VC_RESUME_IN_PROGRESS) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: already resuming", __func__); ++ goto unlock; ++ } ++ ++ if (arm_state->vc_resume_state == VC_RESUME_REQUESTED) { ++ set_resume_state(arm_state, VC_RESUME_IN_PROGRESS); ++ res = 1; ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s: not resuming (resume state %s)", __func__, ++ resume_state_names[arm_state->vc_resume_state + ++ VC_RESUME_NUM_OFFSET]); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (res) ++ vchiq_platform_resume(state); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; ++ ++} ++ ++ ++ ++VCHIQ_STATUS_T ++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ enum USE_TYPE_E use_type) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[16]; ++ int *entity_uc; ++ int local_uc, local_entity_uc; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ if (use_type == USE_TYPE_VCHIQ) { ++ sprintf(entity, "VCHIQ: "); ++ entity_uc = &arm_state->peer_use_count; ++ } else if (service) { ++ sprintf(entity, "%c%c%c%c:%03d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id); ++ entity_uc = &service->service_use_count; ++ } else { ++ vchiq_log_error(vchiq_susp_log_level, "%s null service " ++ "ptr", __func__); ++ ret = VCHIQ_ERROR; ++ goto out; ++ } ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ while (arm_state->resume_blocked) { ++ /* If we call 'use' while force suspend is waiting for suspend, ++ * then we're about to block the thread which the force is ++ * waiting to complete, so we're bound to just time out. In this ++ * case, set the suspend state such that the wait will be ++ * canceled, so we can complete as quickly as possible. */ ++ if (arm_state->resume_blocked && arm_state->vc_suspend_state == ++ VC_SUSPEND_IDLE) { ++ set_suspend_state(arm_state, VC_SUSPEND_FORCE_CANCELED); ++ break; ++ } ++ /* If suspend is already in progress then we need to block */ ++ if (!try_wait_for_completion(&arm_state->resume_blocker)) { ++ /* Indicate that there are threads waiting on the resume ++ * blocker. These need to be allowed to complete before ++ * a _second_ call to force suspend can complete, ++ * otherwise low priority threads might never actually ++ * continue */ ++ arm_state->blocked_count++; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resume " ++ "blocked - waiting...", __func__, entity); ++ if (wait_for_completion_killable( ++ &arm_state->resume_blocker) != 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s %s " ++ "wait for resume blocker interrupted", ++ __func__, entity); ++ ret = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ arm_state->blocked_count--; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resume " ++ "unblocked", __func__, entity); ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (--arm_state->blocked_count == 0) ++ complete_all(&arm_state->blocked_blocker); ++ } ++ } ++ ++ stop_suspend_timer(arm_state); ++ ++ local_uc = ++arm_state->videocore_use_count; ++ local_entity_uc = ++(*entity_uc); ++ ++ /* If there's a pending request which hasn't yet been serviced then ++ * just clear it. If we're past VC_SUSPEND_REQUESTED state then ++ * vc_resume_complete will block until we either resume or fail to ++ * suspend */ ++ if (arm_state->vc_suspend_state <= VC_SUSPEND_REQUESTED) ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ ++ if ((use_type != USE_TYPE_SERVICE_NO_RESUME) && need_resume(state)) { ++ set_resume_state(arm_state, VC_RESUME_REQUESTED); ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, local_entity_uc, local_uc); ++ request_poll(state, NULL, 0); ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, *entity_uc, local_uc); ++ ++ ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ /* Completion is in a done state when we're not suspended, so this won't ++ * block for the non-suspended case. */ ++ if (!try_wait_for_completion(&arm_state->vc_resume_complete)) { ++ vchiq_log_info(vchiq_susp_log_level, "%s %s wait for resume", ++ __func__, entity); ++ if (wait_for_completion_killable( ++ &arm_state->vc_resume_complete) != 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s %s wait for " ++ "resume interrupted", __func__, entity); ++ ret = VCHIQ_ERROR; ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resumed", __func__, ++ entity); ++ } ++ ++ if (ret == VCHIQ_SUCCESS) { ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0); ++ while (ack_cnt && (status == VCHIQ_SUCCESS)) { ++ /* Send the use notify to videocore */ ++ status = vchiq_send_remote_use_active(state); ++ if (status == VCHIQ_SUCCESS) ++ ack_cnt--; ++ else ++ atomic_add(ack_cnt, ++ &arm_state->ka_use_ack_count); ++ } ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[16]; ++ int *entity_uc; ++ int local_uc, local_entity_uc; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ if (service) { ++ sprintf(entity, "%c%c%c%c:%03d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id); ++ entity_uc = &service->service_use_count; ++ } else { ++ sprintf(entity, "PEER: "); ++ entity_uc = &arm_state->peer_use_count; ++ } ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (!arm_state->videocore_use_count || !(*entity_uc)) { ++ /* Don't use BUG_ON - don't allow user thread to crash kernel */ ++ WARN_ON(!arm_state->videocore_use_count); ++ WARN_ON(!(*entity_uc)); ++ ret = VCHIQ_ERROR; ++ goto unlock; ++ } ++ local_uc = --arm_state->videocore_use_count; ++ local_entity_uc = --(*entity_uc); ++ ++ if (!vchiq_videocore_wanted(state)) { ++ if (vchiq_platform_use_suspend_timer() && ++ !arm_state->resume_blocked) { ++ /* Only use the timer if we're not trying to force ++ * suspend (=> resume_blocked) */ ++ start_suspend_timer(arm_state); ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s %s count %d, state count %d - suspending", ++ __func__, entity, *entity_uc, ++ arm_state->videocore_use_count); ++ vchiq_arm_vcsuspend(state); ++ } ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, *entity_uc, ++ arm_state->videocore_use_count); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; ++} ++ ++void ++vchiq_on_remote_use(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ atomic_inc(&arm_state->ka_use_count); ++ complete(&arm_state->ka_evt); ++} ++ ++void ++vchiq_on_remote_release(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ atomic_inc(&arm_state->ka_release_count); ++ complete(&arm_state->ka_evt); ++} ++ ++VCHIQ_STATUS_T ++vchiq_use_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ return vchiq_use_internal(service->state, service, USE_TYPE_SERVICE); ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ return vchiq_release_internal(service->state, service); ++} ++ ++VCHIQ_DEBUGFS_NODE_T * ++vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance) ++{ ++ return &instance->debugfs_node; ++} ++ ++int ++vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T *service; ++ int use_count = 0, i; ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ use_count += service->service_use_count; ++ unlock_service(service); ++ } ++ return use_count; ++} ++ ++int ++vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->pid; ++} ++ ++int ++vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->trace; ++} ++ ++void ++vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace) ++{ ++ VCHIQ_SERVICE_T *service; ++ int i; ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ service->trace = trace; ++ unlock_service(service); ++ } ++ instance->trace = (trace != 0); ++} ++ ++static void suspend_timer_callback(unsigned long context) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ if (!arm_state) ++ goto out; ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s - suspend timer expired - check suspend", __func__); ++ vchiq_check_suspend(state); ++out: ++ return; ++} ++ ++VCHIQ_STATUS_T ++vchiq_use_service_no_resume(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ if (service) { ++ ret = vchiq_use_internal(service->state, service, ++ USE_TYPE_SERVICE_NO_RESUME); ++ unlock_service(service); ++ } ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ if (service) { ++ ret = vchiq_use_internal(service->state, service, ++ USE_TYPE_SERVICE); ++ unlock_service(service); ++ } ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ if (service) { ++ ret = vchiq_release_internal(service->state, service); ++ unlock_service(service); ++ } ++ return ret; ++} ++ ++void ++vchiq_dump_service_use_state(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int i, j = 0; ++ /* Only dump 64 services */ ++ static const int local_max_services = 64; ++ /* If there's more than 64 services, only dump ones with ++ * non-zero counts */ ++ int only_nonzero = 0; ++ static const char *nz = "<-- preventing suspend"; ++ ++ enum vc_suspend_status vc_suspend_state; ++ enum vc_resume_status vc_resume_state; ++ int peer_count; ++ int vc_use_count; ++ int active_services; ++ struct service_data_struct { ++ int fourcc; ++ int clientid; ++ int use_count; ++ } service_data[local_max_services]; ++ ++ if (!arm_state) ++ return; ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ vc_suspend_state = arm_state->vc_suspend_state; ++ vc_resume_state = arm_state->vc_resume_state; ++ peer_count = arm_state->peer_use_count; ++ vc_use_count = arm_state->videocore_use_count; ++ active_services = state->unused_service; ++ if (active_services > local_max_services) ++ only_nonzero = 1; ++ ++ for (i = 0; (i < active_services) && (j < local_max_services); i++) { ++ VCHIQ_SERVICE_T *service_ptr = state->services[i]; ++ if (!service_ptr) ++ continue; ++ ++ if (only_nonzero && !service_ptr->service_use_count) ++ continue; ++ ++ if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) { ++ service_data[j].fourcc = service_ptr->base.fourcc; ++ service_data[j].clientid = service_ptr->client_id; ++ service_data[j++].use_count = service_ptr-> ++ service_use_count; ++ } ++ } ++ ++ read_unlock_bh(&arm_state->susp_res_lock); ++ ++ vchiq_log_warning(vchiq_susp_log_level, ++ "-- Videcore suspend state: %s --", ++ suspend_state_names[vc_suspend_state + VC_SUSPEND_NUM_OFFSET]); ++ vchiq_log_warning(vchiq_susp_log_level, ++ "-- Videcore resume state: %s --", ++ resume_state_names[vc_resume_state + VC_RESUME_NUM_OFFSET]); ++ ++ if (only_nonzero) ++ vchiq_log_warning(vchiq_susp_log_level, "Too many active " ++ "services (%d). Only dumping up to first %d services " ++ "with non-zero use-count", active_services, ++ local_max_services); ++ ++ for (i = 0; i < j; i++) { ++ vchiq_log_warning(vchiq_susp_log_level, ++ "----- %c%c%c%c:%d service count %d %s", ++ VCHIQ_FOURCC_AS_4CHARS(service_data[i].fourcc), ++ service_data[i].clientid, ++ service_data[i].use_count, ++ service_data[i].use_count ? nz : ""); ++ } ++ vchiq_log_warning(vchiq_susp_log_level, ++ "----- VCHIQ use count count %d", peer_count); ++ vchiq_log_warning(vchiq_susp_log_level, ++ "--- Overall vchiq instance use count %d", vc_use_count); ++ ++ vchiq_dump_platform_use_state(state); ++} ++ ++VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_ARM_STATE_T *arm_state; ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ ++ if (!service || !service->state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ arm_state = vchiq_platform_get_arm_state(service->state); ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ if (service->service_use_count) ++ ret = VCHIQ_SUCCESS; ++ read_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (ret == VCHIQ_ERROR) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s ERROR - %c%c%c%c:%d service count %d, " ++ "state count %d, videocore suspend state %s", __func__, ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id, service->service_use_count, ++ arm_state->videocore_use_count, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ vchiq_dump_service_use_state(service->state); ++ } ++out: ++ return ret; ++} ++ ++/* stub functions */ ++void vchiq_on_remote_use_active(VCHIQ_STATE_T *state) ++{ ++ (void)state; ++} ++ ++void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, ++ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_info(vchiq_susp_log_level, "%d: %s->%s", state->id, ++ get_conn_state_name(oldstate), get_conn_state_name(newstate)); ++ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTED) { ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (!arm_state->first_connect) { ++ char threadname[10]; ++ arm_state->first_connect = 1; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ snprintf(threadname, sizeof(threadname), "VCHIQka-%d", ++ state->id); ++ arm_state->ka_thread = kthread_create( ++ &vchiq_keepalive_thread_func, ++ (void *)state, ++ threadname); ++ if (arm_state->ka_thread == NULL) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "vchiq: FATAL: couldn't create thread %s", ++ threadname); ++ } else { ++ wake_up_process(arm_state->ka_thread); ++ } ++ } else ++ write_unlock_bh(&arm_state->susp_res_lock); ++ } ++} ++ ++static int vchiq_probe(struct platform_device *pdev) ++{ ++ int err; ++ void *ptr_err; ++ ++ /* create debugfs entries */ ++ err = vchiq_debugfs_init(); ++ if (err != 0) ++ goto failed_debugfs_init; ++ ++ err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME); ++ if (err != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to allocate device number"); ++ goto failed_alloc_chrdev; ++ } ++ cdev_init(&vchiq_cdev, &vchiq_fops); ++ vchiq_cdev.owner = THIS_MODULE; ++ err = cdev_add(&vchiq_cdev, vchiq_devid, 1); ++ if (err != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to register device"); ++ goto failed_cdev_add; ++ } ++ ++ /* create sysfs entries */ ++ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME); ++ ptr_err = vchiq_class; ++ if (IS_ERR(ptr_err)) ++ goto failed_class_create; ++ ++ vchiq_dev = device_create(vchiq_class, NULL, ++ vchiq_devid, NULL, "vchiq"); ++ ptr_err = vchiq_dev; ++ if (IS_ERR(ptr_err)) ++ goto failed_device_create; ++ ++ err = vchiq_platform_init(pdev, &g_state); ++ if (err != 0) ++ goto failed_platform_init; ++ ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq: initialised - version %d (min %d), device %d.%d", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN, ++ MAJOR(vchiq_devid), MINOR(vchiq_devid)); ++ ++ return 0; ++ ++failed_platform_init: ++ device_destroy(vchiq_class, vchiq_devid); ++failed_device_create: ++ class_destroy(vchiq_class); ++failed_class_create: ++ cdev_del(&vchiq_cdev); ++ err = PTR_ERR(ptr_err); ++failed_cdev_add: ++ unregister_chrdev_region(vchiq_devid, 1); ++failed_alloc_chrdev: ++ vchiq_debugfs_deinit(); ++failed_debugfs_init: ++ vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq"); ++ return err; ++} ++ ++static int vchiq_remove(struct platform_device *pdev) ++{ ++ device_destroy(vchiq_class, vchiq_devid); ++ class_destroy(vchiq_class); ++ cdev_del(&vchiq_cdev); ++ unregister_chrdev_region(vchiq_devid, 1); ++ ++ return 0; ++} ++ ++static const struct of_device_id vchiq_of_match[] = { ++ { .compatible = "brcm,bcm2835-vchiq", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, vchiq_of_match); ++ ++static struct platform_driver vchiq_driver = { ++ .driver = { ++ .name = "bcm2835_vchiq", ++ .owner = THIS_MODULE, ++ .of_match_table = vchiq_of_match, ++ }, ++ .probe = vchiq_probe, ++ .remove = vchiq_remove, ++}; ++module_platform_driver(vchiq_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h +@@ -0,0 +1,220 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_ARM_H ++#define VCHIQ_ARM_H ++ ++#include ++#include ++#include ++#include ++#include "vchiq_core.h" ++#include "vchiq_debugfs.h" ++ ++ ++enum vc_suspend_status { ++ VC_SUSPEND_FORCE_CANCELED = -3, /* Force suspend canceled, too busy */ ++ VC_SUSPEND_REJECTED = -2, /* Videocore rejected suspend request */ ++ VC_SUSPEND_FAILED = -1, /* Videocore suspend failed */ ++ VC_SUSPEND_IDLE = 0, /* VC active, no suspend actions */ ++ VC_SUSPEND_REQUESTED, /* User has requested suspend */ ++ VC_SUSPEND_IN_PROGRESS, /* Slot handler has recvd suspend request */ ++ VC_SUSPEND_SUSPENDED /* Videocore suspend succeeded */ ++}; ++ ++enum vc_resume_status { ++ VC_RESUME_FAILED = -1, /* Videocore resume failed */ ++ VC_RESUME_IDLE = 0, /* VC suspended, no resume actions */ ++ VC_RESUME_REQUESTED, /* User has requested resume */ ++ VC_RESUME_IN_PROGRESS, /* Slot handler has received resume request */ ++ VC_RESUME_RESUMED /* Videocore resumed successfully (active) */ ++}; ++ ++ ++enum USE_TYPE_E { ++ USE_TYPE_SERVICE, ++ USE_TYPE_SERVICE_NO_RESUME, ++ USE_TYPE_VCHIQ ++}; ++ ++ ++ ++typedef struct vchiq_arm_state_struct { ++ /* Keepalive-related data */ ++ struct task_struct *ka_thread; ++ struct completion ka_evt; ++ atomic_t ka_use_count; ++ atomic_t ka_use_ack_count; ++ atomic_t ka_release_count; ++ ++ struct completion vc_suspend_complete; ++ struct completion vc_resume_complete; ++ ++ rwlock_t susp_res_lock; ++ enum vc_suspend_status vc_suspend_state; ++ enum vc_resume_status vc_resume_state; ++ ++ unsigned int wake_address; ++ ++ struct timer_list suspend_timer; ++ int suspend_timer_timeout; ++ int suspend_timer_running; ++ ++ /* Global use count for videocore. ++ ** This is equal to the sum of the use counts for all services. When ++ ** this hits zero the videocore suspend procedure will be initiated. ++ */ ++ int videocore_use_count; ++ ++ /* Use count to track requests from videocore peer. ++ ** This use count is not associated with a service, so needs to be ++ ** tracked separately with the state. ++ */ ++ int peer_use_count; ++ ++ /* Flag to indicate whether resume is blocked. This happens when the ++ ** ARM is suspending ++ */ ++ struct completion resume_blocker; ++ int resume_blocked; ++ struct completion blocked_blocker; ++ int blocked_count; ++ ++ int autosuspend_override; ++ ++ /* Flag to indicate that the first vchiq connect has made it through. ++ ** This means that both sides should be fully ready, and we should ++ ** be able to suspend after this point. ++ */ ++ int first_connect; ++ ++ unsigned long long suspend_start_time; ++ unsigned long long sleep_start_time; ++ unsigned long long resume_start_time; ++ unsigned long long last_wake_time; ++ ++} VCHIQ_ARM_STATE_T; ++ ++extern int vchiq_arm_log_level; ++extern int vchiq_susp_log_level; ++ ++int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATE_T * ++vchiq_get_state(void); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_vcsuspend(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_force_suspend(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_arm_allow_resume(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_vcresume(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state); ++ ++extern int ++vchiq_check_resume(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_check_suspend(VCHIQ_STATE_T *state); ++ VCHIQ_STATUS_T ++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_STATUS_T ++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_suspend(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_platform_videocore_wanted(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_platform_use_suspend_timer(void); ++ ++extern void ++vchiq_dump_platform_use_state(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump_service_use_state(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_ARM_STATE_T* ++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_videocore_wanted(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ enum USE_TYPE_E use_type); ++extern VCHIQ_STATUS_T ++vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_DEBUGFS_NODE_T * ++vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance); ++ ++extern void ++vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace); ++ ++extern void ++set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_suspend_status new_state); ++ ++extern void ++set_resume_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_resume_status new_state); ++ ++extern void ++start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state); ++ ++ ++#endif /* VCHIQ_ARM_H */ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h +@@ -0,0 +1,37 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++const char *vchiq_get_build_hostname(void); ++const char *vchiq_get_build_version(void); ++const char *vchiq_get_build_time(void); ++const char *vchiq_get_build_date(void); +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h +@@ -0,0 +1,69 @@ ++/** ++ * Copyright (c) 2010-2014 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_CFG_H ++#define VCHIQ_CFG_H ++ ++#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I') ++/* The version of VCHIQ - change with any non-trivial change */ ++#define VCHIQ_VERSION 8 ++/* The minimum compatible version - update to match VCHIQ_VERSION with any ++** incompatible change */ ++#define VCHIQ_VERSION_MIN 3 ++ ++/* The version that introduced the VCHIQ_IOC_LIB_VERSION ioctl */ ++#define VCHIQ_VERSION_LIB_VERSION 7 ++ ++/* The version that introduced the VCHIQ_IOC_CLOSE_DELIVERED ioctl */ ++#define VCHIQ_VERSION_CLOSE_DELIVERED 7 ++ ++/* The version that made it safe to use SYNCHRONOUS mode */ ++#define VCHIQ_VERSION_SYNCHRONOUS_MODE 8 ++ ++#define VCHIQ_MAX_STATES 1 ++#define VCHIQ_MAX_SERVICES 4096 ++#define VCHIQ_MAX_SLOTS 128 ++#define VCHIQ_MAX_SLOTS_PER_SIDE 64 ++ ++#define VCHIQ_NUM_CURRENT_BULKS 32 ++#define VCHIQ_NUM_SERVICE_BULKS 4 ++ ++#ifndef VCHIQ_ENABLE_DEBUG ++#define VCHIQ_ENABLE_DEBUG 1 ++#endif ++ ++#ifndef VCHIQ_ENABLE_STATS ++#define VCHIQ_ENABLE_STATS 1 ++#endif ++ ++#endif /* VCHIQ_CFG_H */ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c +@@ -0,0 +1,120 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "vchiq_connected.h" ++#include "vchiq_core.h" ++#include "vchiq_killable.h" ++#include ++#include ++ ++#define MAX_CALLBACKS 10 ++ ++static int g_connected; ++static int g_num_deferred_callbacks; ++static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS]; ++static int g_once_init; ++static struct mutex g_connected_mutex; ++ ++/**************************************************************************** ++* ++* Function to initialize our lock. ++* ++***************************************************************************/ ++ ++static void connected_init(void) ++{ ++ if (!g_once_init) { ++ mutex_init(&g_connected_mutex); ++ g_once_init = 1; ++ } ++} ++ ++/**************************************************************************** ++* ++* This function is used to defer initialization until the vchiq stack is ++* initialized. If the stack is already initialized, then the callback will ++* be made immediately, otherwise it will be deferred until ++* vchiq_call_connected_callbacks is called. ++* ++***************************************************************************/ ++ ++void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback) ++{ ++ connected_init(); ++ ++ if (mutex_lock_interruptible(&g_connected_mutex) != 0) ++ return; ++ ++ if (g_connected) ++ /* We're already connected. Call the callback immediately. */ ++ ++ callback(); ++ else { ++ if (g_num_deferred_callbacks >= MAX_CALLBACKS) ++ vchiq_log_error(vchiq_core_log_level, ++ "There already %d callback registered - " ++ "please increase MAX_CALLBACKS", ++ g_num_deferred_callbacks); ++ else { ++ g_deferred_callback[g_num_deferred_callbacks] = ++ callback; ++ g_num_deferred_callbacks++; ++ } ++ } ++ mutex_unlock(&g_connected_mutex); ++} ++ ++/**************************************************************************** ++* ++* This function is called by the vchiq stack once it has been connected to ++* the videocore and clients can start to use the stack. ++* ++***************************************************************************/ ++ ++void vchiq_call_connected_callbacks(void) ++{ ++ int i; ++ ++ connected_init(); ++ ++ if (mutex_lock_interruptible(&g_connected_mutex) != 0) ++ return; ++ ++ for (i = 0; i < g_num_deferred_callbacks; i++) ++ g_deferred_callback[i](); ++ ++ g_num_deferred_callbacks = 0; ++ g_connected = 1; ++ mutex_unlock(&g_connected_mutex); ++} ++EXPORT_SYMBOL(vchiq_add_connected_callback); +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h +@@ -0,0 +1,50 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_CONNECTED_H ++#define VCHIQ_CONNECTED_H ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++typedef void (*VCHIQ_CONNECTED_CALLBACK_T)(void); ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback); ++void vchiq_call_connected_callbacks(void); ++ ++#endif /* VCHIQ_CONNECTED_H */ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +@@ -0,0 +1,3934 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "vchiq_core.h" ++#include "vchiq_killable.h" ++ ++#define VCHIQ_SLOT_HANDLER_STACK 8192 ++ ++#define HANDLE_STATE_SHIFT 12 ++ ++#define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index)) ++#define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index)) ++#define SLOT_INDEX_FROM_DATA(state, data) \ ++ (((unsigned int)((char *)data - (char *)state->slot_data)) / \ ++ VCHIQ_SLOT_SIZE) ++#define SLOT_INDEX_FROM_INFO(state, info) \ ++ ((unsigned int)(info - state->slot_info)) ++#define SLOT_QUEUE_INDEX_FROM_POS(pos) \ ++ ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) ++ ++#define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) ++ ++#define SRVTRACE_LEVEL(srv) \ ++ (((srv) && (srv)->trace) ? VCHIQ_LOG_TRACE : vchiq_core_msg_log_level) ++#define SRVTRACE_ENABLED(srv, lev) \ ++ (((srv) && (srv)->trace) || (vchiq_core_msg_log_level >= (lev))) ++ ++struct vchiq_open_payload { ++ int fourcc; ++ int client_id; ++ short version; ++ short version_min; ++}; ++ ++struct vchiq_openack_payload { ++ short version; ++}; ++ ++enum ++{ ++ QMFLAGS_IS_BLOCKING = (1 << 0), ++ QMFLAGS_NO_MUTEX_LOCK = (1 << 1), ++ QMFLAGS_NO_MUTEX_UNLOCK = (1 << 2) ++}; ++ ++/* we require this for consistency between endpoints */ ++vchiq_static_assert(sizeof(VCHIQ_HEADER_T) == 8); ++vchiq_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T))); ++vchiq_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS)); ++vchiq_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SERVICES)); ++vchiq_static_assert(VCHIQ_VERSION >= VCHIQ_VERSION_MIN); ++ ++/* Run time control of log level, based on KERN_XXX level. */ ++int vchiq_core_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_core_msg_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_sync_log_level = VCHIQ_LOG_DEFAULT; ++ ++static atomic_t pause_bulks_count = ATOMIC_INIT(0); ++ ++static DEFINE_SPINLOCK(service_spinlock); ++DEFINE_SPINLOCK(bulk_waiter_spinlock); ++DEFINE_SPINLOCK(quota_spinlock); ++ ++VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; ++static unsigned int handle_seq; ++ ++static const char *const srvstate_names[] = { ++ "FREE", ++ "HIDDEN", ++ "LISTENING", ++ "OPENING", ++ "OPEN", ++ "OPENSYNC", ++ "CLOSESENT", ++ "CLOSERECVD", ++ "CLOSEWAIT", ++ "CLOSED" ++}; ++ ++static const char *const reason_names[] = { ++ "SERVICE_OPENED", ++ "SERVICE_CLOSED", ++ "MESSAGE_AVAILABLE", ++ "BULK_TRANSMIT_DONE", ++ "BULK_RECEIVE_DONE", ++ "BULK_TRANSMIT_ABORTED", ++ "BULK_RECEIVE_ABORTED" ++}; ++ ++static const char *const conn_state_names[] = { ++ "DISCONNECTED", ++ "CONNECTING", ++ "CONNECTED", ++ "PAUSING", ++ "PAUSE_SENT", ++ "PAUSED", ++ "RESUMING", ++ "PAUSE_TIMEOUT", ++ "RESUME_TIMEOUT" ++}; ++ ++ ++static void ++release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header); ++ ++static const char *msg_type_str(unsigned int msg_type) ++{ ++ switch (msg_type) { ++ case VCHIQ_MSG_PADDING: return "PADDING"; ++ case VCHIQ_MSG_CONNECT: return "CONNECT"; ++ case VCHIQ_MSG_OPEN: return "OPEN"; ++ case VCHIQ_MSG_OPENACK: return "OPENACK"; ++ case VCHIQ_MSG_CLOSE: return "CLOSE"; ++ case VCHIQ_MSG_DATA: return "DATA"; ++ case VCHIQ_MSG_BULK_RX: return "BULK_RX"; ++ case VCHIQ_MSG_BULK_TX: return "BULK_TX"; ++ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE"; ++ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE"; ++ case VCHIQ_MSG_PAUSE: return "PAUSE"; ++ case VCHIQ_MSG_RESUME: return "RESUME"; ++ case VCHIQ_MSG_REMOTE_USE: return "REMOTE_USE"; ++ case VCHIQ_MSG_REMOTE_RELEASE: return "REMOTE_RELEASE"; ++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: return "REMOTE_USE_ACTIVE"; ++ } ++ return "???"; ++} ++ ++static inline void ++vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate) ++{ ++ vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate], ++ srvstate_names[newstate]); ++ service->srvstate = newstate; ++} ++ ++VCHIQ_SERVICE_T * ++find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->handle == handle)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++find_service_by_port(VCHIQ_STATE_T *state, int localport) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ if ((unsigned int)localport <= VCHIQ_PORT_MAX) { ++ spin_lock(&service_spinlock); ++ service = state->services[localport]; ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ } ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid port %d", localport); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++find_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle) { ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->handle == handle) && ++ (service->instance == instance)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle) { ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && ++ ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) && ++ (service->handle == handle) && ++ (service->instance == instance)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, ++ int *pidx) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ int idx = *pidx; ++ ++ spin_lock(&service_spinlock); ++ while (idx < state->unused_service) { ++ VCHIQ_SERVICE_T *srv = state->services[idx++]; ++ if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (srv->instance == instance)) { ++ service = srv; ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ break; ++ } ++ } ++ spin_unlock(&service_spinlock); ++ ++ *pidx = idx; ++ ++ return service; ++} ++ ++void ++lock_service(VCHIQ_SERVICE_T *service) ++{ ++ spin_lock(&service_spinlock); ++ BUG_ON(!service || (service->ref_count == 0)); ++ if (service) ++ service->ref_count++; ++ spin_unlock(&service_spinlock); ++} ++ ++void ++unlock_service(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ spin_lock(&service_spinlock); ++ BUG_ON(!service || (service->ref_count == 0)); ++ if (service && service->ref_count) { ++ service->ref_count--; ++ if (!service->ref_count) { ++ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); ++ state->services[service->localport] = NULL; ++ } else ++ service = NULL; ++ } ++ spin_unlock(&service_spinlock); ++ ++ if (service && service->userdata_term) ++ service->userdata_term(service->base.userdata); ++ ++ kfree(service); ++} ++ ++int ++vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ int id; ++ ++ id = service ? service->client_id : 0; ++ if (service) ++ unlock_service(service); ++ ++ return id; ++} ++ ++void * ++vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = handle_to_service(handle); ++ ++ return service ? service->base.userdata : NULL; ++} ++ ++int ++vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = handle_to_service(handle); ++ ++ return service ? service->base.fourcc : 0; ++} ++ ++static void ++mark_service_closing_internal(VCHIQ_SERVICE_T *service, int sh_thread) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ VCHIQ_SERVICE_QUOTA_T *service_quota; ++ ++ service->closing = 1; ++ ++ /* Synchronise with other threads. */ ++ mutex_lock(&state->recycle_mutex); ++ mutex_unlock(&state->recycle_mutex); ++ if (!sh_thread || (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT)) { ++ /* If we're pausing then the slot_mutex is held until resume ++ * by the slot handler. Therefore don't try to acquire this ++ * mutex if we're the slot handler and in the pause sent state. ++ * We don't need to in this case anyway. */ ++ mutex_lock(&state->slot_mutex); ++ mutex_unlock(&state->slot_mutex); ++ } ++ ++ /* Unblock any sending thread. */ ++ service_quota = &state->service_quotas[service->localport]; ++ up(&service_quota->quota_event); ++} ++ ++static void ++mark_service_closing(VCHIQ_SERVICE_T *service) ++{ ++ mark_service_closing_internal(service, 0); ++} ++ ++static inline VCHIQ_STATUS_T ++make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, void *bulk_userdata) ++{ ++ VCHIQ_STATUS_T status; ++ vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %x, %x)", ++ service->state->id, service->localport, reason_names[reason], ++ (unsigned int)header, (unsigned int)bulk_userdata); ++ status = service->base.callback(reason, header, service->handle, ++ bulk_userdata); ++ if (status == VCHIQ_ERROR) { ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: ignoring ERROR from callback to service %x", ++ service->state->id, service->handle); ++ status = VCHIQ_SUCCESS; ++ } ++ return status; ++} ++ ++inline void ++vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate) ++{ ++ VCHIQ_CONNSTATE_T oldstate = state->conn_state; ++ vchiq_log_info(vchiq_core_log_level, "%d: %s->%s", state->id, ++ conn_state_names[oldstate], ++ conn_state_names[newstate]); ++ state->conn_state = newstate; ++ vchiq_platform_conn_state_changed(state, oldstate, newstate); ++} ++ ++static inline void ++remote_event_create(REMOTE_EVENT_T *event) ++{ ++ event->armed = 0; ++ /* Don't clear the 'fired' flag because it may already have been set ++ ** by the other side. */ ++ sema_init(event->event, 0); ++} ++ ++static inline void ++remote_event_destroy(REMOTE_EVENT_T *event) ++{ ++ (void)event; ++} ++ ++static inline int ++remote_event_wait(REMOTE_EVENT_T *event) ++{ ++ if (!event->fired) { ++ event->armed = 1; ++ dsb(); ++ if (!event->fired) { ++ if (down_interruptible(event->event) != 0) { ++ event->armed = 0; ++ return 0; ++ } ++ } ++ event->armed = 0; ++ wmb(); ++ } ++ ++ event->fired = 0; ++ return 1; ++} ++ ++static inline void ++remote_event_signal_local(REMOTE_EVENT_T *event) ++{ ++ event->armed = 0; ++ up(event->event); ++} ++ ++static inline void ++remote_event_poll(REMOTE_EVENT_T *event) ++{ ++ if (event->fired && event->armed) ++ remote_event_signal_local(event); ++} ++ ++void ++remote_event_pollall(VCHIQ_STATE_T *state) ++{ ++ remote_event_poll(&state->local->sync_trigger); ++ remote_event_poll(&state->local->sync_release); ++ remote_event_poll(&state->local->trigger); ++ remote_event_poll(&state->local->recycle); ++} ++ ++/* Round up message sizes so that any space at the end of a slot is always big ++** enough for a header. This relies on header size being a power of two, which ++** has been verified earlier by a static assertion. */ ++ ++static inline unsigned int ++calc_stride(unsigned int size) ++{ ++ /* Allow room for the header */ ++ size += sizeof(VCHIQ_HEADER_T); ++ ++ /* Round up */ ++ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T) ++ - 1); ++} ++ ++/* Called by the slot handler thread */ ++static VCHIQ_SERVICE_T * ++get_listening_service(VCHIQ_STATE_T *state, int fourcc) ++{ ++ int i; ++ ++ WARN_ON(fourcc == VCHIQ_FOURCC_INVALID); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && ++ (service->public_fourcc == fourcc) && ++ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) && ++ (service->remoteport == VCHIQ_PORT_FREE)))) { ++ lock_service(service); ++ return service; ++ } ++ } ++ ++ return NULL; ++} ++ ++/* Called by the slot handler thread */ ++static VCHIQ_SERVICE_T * ++get_connected_service(VCHIQ_STATE_T *state, unsigned int port) ++{ ++ int i; ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN) ++ && (service->remoteport == port)) { ++ lock_service(service); ++ return service; ++ } ++ } ++ return NULL; ++} ++ ++inline void ++request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type) ++{ ++ uint32_t value; ++ ++ if (service) { ++ do { ++ value = atomic_read(&service->poll_flags); ++ } while (atomic_cmpxchg(&service->poll_flags, value, ++ value | (1 << poll_type)) != value); ++ ++ do { ++ value = atomic_read(&state->poll_services[ ++ service->localport>>5]); ++ } while (atomic_cmpxchg( ++ &state->poll_services[service->localport>>5], ++ value, value | (1 << (service->localport & 0x1f))) ++ != value); ++ } ++ ++ state->poll_needed = 1; ++ wmb(); ++ ++ /* ... and ensure the slot handler runs. */ ++ remote_event_signal_local(&state->local->trigger); ++} ++ ++/* Called from queue_message, by the slot handler and application threads, ++** with slot_mutex held */ ++static VCHIQ_HEADER_T * ++reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking) ++{ ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ int tx_pos = state->local_tx_pos; ++ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK); ++ ++ if (space > slot_space) { ++ VCHIQ_HEADER_T *header; ++ /* Fill the remaining space with padding */ ++ WARN_ON(state->tx_data == NULL); ++ header = (VCHIQ_HEADER_T *) ++ (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++ header->msgid = VCHIQ_MSGID_PADDING; ++ header->size = slot_space - sizeof(VCHIQ_HEADER_T); ++ ++ tx_pos += slot_space; ++ } ++ ++ /* If necessary, get the next slot. */ ++ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) { ++ int slot_index; ++ ++ /* If there is no free slot... */ ++ ++ if (down_trylock(&state->slot_available_event) != 0) { ++ /* ...wait for one. */ ++ ++ VCHIQ_STATS_INC(state, slot_stalls); ++ ++ /* But first, flush through the last slot. */ ++ state->local_tx_pos = tx_pos; ++ local->tx_pos = tx_pos; ++ remote_event_signal(&state->remote->trigger); ++ ++ if (!is_blocking || ++ (down_interruptible( ++ &state->slot_available_event) != 0)) ++ return NULL; /* No space available */ ++ } ++ ++ BUG_ON(tx_pos == ++ (state->slot_queue_available * VCHIQ_SLOT_SIZE)); ++ ++ slot_index = local->slot_queue[ ++ SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ state->tx_data = ++ (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ } ++ ++ state->local_tx_pos = tx_pos + space; ++ ++ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++} ++ ++/* Called by the recycle thread. */ ++static void ++process_free_queue(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ int slot_queue_available; ++ ++ /* Use a read memory barrier to ensure that any state that may have ++ ** been modified by another thread is not masked by stale prefetched ++ ** values. */ ++ rmb(); ++ ++ /* Find slots which have been freed by the other side, and return them ++ ** to the available queue. */ ++ slot_queue_available = state->slot_queue_available; ++ ++ while (slot_queue_available != local->slot_queue_recycle) { ++ unsigned int pos; ++ int slot_index = local->slot_queue[slot_queue_available++ & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ int data_found = 0; ++ ++ vchiq_log_trace(vchiq_core_log_level, "%d: pfq %d=%x %x %x", ++ state->id, slot_index, (unsigned int)data, ++ local->slot_queue_recycle, slot_queue_available); ++ ++ /* Initialise the bitmask for services which have used this ++ ** slot */ ++ BITSET_ZERO(service_found); ++ ++ pos = 0; ++ ++ while (pos < VCHIQ_SLOT_SIZE) { ++ VCHIQ_HEADER_T *header = ++ (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) { ++ int port = VCHIQ_MSG_SRCPORT(msgid); ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[port]; ++ int count; ++ spin_lock("a_spinlock); ++ count = service_quota->message_use_count; ++ if (count > 0) ++ service_quota->message_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ ++ if (count == service_quota->message_quota) ++ /* Signal the service that it ++ ** has dropped below its quota ++ */ ++ up(&service_quota->quota_event); ++ else if (count == 0) { ++ vchiq_log_error(vchiq_core_log_level, ++ "service %d " ++ "message_use_count=%d " ++ "(header %x, msgid %x, " ++ "header->msgid %x, " ++ "header->size %x)", ++ port, ++ service_quota-> ++ message_use_count, ++ (unsigned int)header, msgid, ++ header->msgid, ++ header->size); ++ WARN(1, "invalid message use count\n"); ++ } ++ if (!BITSET_IS_SET(service_found, port)) { ++ /* Set the found bit for this service */ ++ BITSET_SET(service_found, port); ++ ++ spin_lock("a_spinlock); ++ count = service_quota->slot_use_count; ++ if (count > 0) ++ service_quota->slot_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ ++ if (count > 0) { ++ /* Signal the service in case ++ ** it has dropped below its ++ ** quota */ ++ up(&service_quota->quota_event); ++ vchiq_log_trace( ++ vchiq_core_log_level, ++ "%d: pfq:%d %x@%x - " ++ "slot_use->%d", ++ state->id, port, ++ header->size, ++ (unsigned int)header, ++ count - 1); ++ } else { ++ vchiq_log_error( ++ vchiq_core_log_level, ++ "service %d " ++ "slot_use_count" ++ "=%d (header %x" ++ ", msgid %x, " ++ "header->msgid" ++ " %x, header->" ++ "size %x)", ++ port, count, ++ (unsigned int)header, ++ msgid, ++ header->msgid, ++ header->size); ++ WARN(1, "bad slot use count\n"); ++ } ++ } ++ ++ data_found = 1; ++ } ++ ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "pfq - pos %x: header %x, msgid %x, " ++ "header->msgid %x, header->size %x", ++ pos, (unsigned int)header, msgid, ++ header->msgid, header->size); ++ WARN(1, "invalid slot position\n"); ++ } ++ } ++ ++ if (data_found) { ++ int count; ++ spin_lock("a_spinlock); ++ count = state->data_use_count; ++ if (count > 0) ++ state->data_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ if (count == state->data_quota) ++ up(&state->data_quota_event); ++ } ++ ++ state->slot_queue_available = slot_queue_available; ++ up(&state->slot_available_event); ++ } ++} ++ ++/* Called by the slot handler and application threads */ ++static VCHIQ_STATUS_T ++queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ int msgid, const VCHIQ_ELEMENT_T *elements, ++ int count, int size, int flags) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL; ++ VCHIQ_HEADER_T *header; ++ int type = VCHIQ_MSG_TYPE(msgid); ++ ++ unsigned int stride; ++ ++ local = state->local; ++ ++ stride = calc_stride(size); ++ ++ WARN_ON(!(stride <= VCHIQ_SLOT_SIZE)); ++ ++ if (!(flags & QMFLAGS_NO_MUTEX_LOCK) && ++ (mutex_lock_interruptible(&state->slot_mutex) != 0)) ++ return VCHIQ_RETRY; ++ ++ if (type == VCHIQ_MSG_DATA) { ++ int tx_end_index; ++ ++ BUG_ON(!service); ++ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | ++ QMFLAGS_NO_MUTEX_UNLOCK)) != 0); ++ ++ if (service->closing) { ++ /* The service has been closed */ ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_ERROR; ++ } ++ ++ service_quota = &state->service_quotas[service->localport]; ++ ++ spin_lock("a_spinlock); ++ ++ /* Ensure this service doesn't use more than its quota of ++ ** messages or slots */ ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ ++ /* Ensure data messages don't use more than their quota of ++ ** slots */ ++ while ((tx_end_index != state->previous_data_index) && ++ (state->data_use_count == state->data_quota)) { ++ VCHIQ_STATS_INC(state, data_stalls); ++ spin_unlock("a_spinlock); ++ mutex_unlock(&state->slot_mutex); ++ ++ if (down_interruptible(&state->data_quota_event) ++ != 0) ++ return VCHIQ_RETRY; ++ ++ mutex_lock(&state->slot_mutex); ++ spin_lock("a_spinlock); ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ if ((tx_end_index == state->previous_data_index) || ++ (state->data_use_count < state->data_quota)) { ++ /* Pass the signal on to other waiters */ ++ up(&state->data_quota_event); ++ break; ++ } ++ } ++ ++ while ((service_quota->message_use_count == ++ service_quota->message_quota) || ++ ((tx_end_index != service_quota->previous_tx_index) && ++ (service_quota->slot_use_count == ++ service_quota->slot_quota))) { ++ spin_unlock("a_spinlock); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: qm:%d %s,%x - quota stall " ++ "(msg %d, slot %d)", ++ state->id, service->localport, ++ msg_type_str(type), size, ++ service_quota->message_use_count, ++ service_quota->slot_use_count); ++ VCHIQ_SERVICE_STATS_INC(service, quota_stalls); ++ mutex_unlock(&state->slot_mutex); ++ if (down_interruptible(&service_quota->quota_event) ++ != 0) ++ return VCHIQ_RETRY; ++ if (service->closing) ++ return VCHIQ_ERROR; ++ if (mutex_lock_interruptible(&state->slot_mutex) != 0) ++ return VCHIQ_RETRY; ++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { ++ /* The service has been closed */ ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_ERROR; ++ } ++ spin_lock("a_spinlock); ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ } ++ ++ spin_unlock("a_spinlock); ++ } ++ ++ header = reserve_space(state, stride, flags & QMFLAGS_IS_BLOCKING); ++ ++ if (!header) { ++ if (service) ++ VCHIQ_SERVICE_STATS_INC(service, slot_stalls); ++ /* In the event of a failure, return the mutex to the ++ state it was in */ ++ if (!(flags & QMFLAGS_NO_MUTEX_LOCK)) ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_RETRY; ++ } ++ ++ if (type == VCHIQ_MSG_DATA) { ++ int i, pos; ++ int tx_end_index; ++ int slot_use_count; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: qm %s@%x,%x (%d->%d)", ++ state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ ++ BUG_ON(!service); ++ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | ++ QMFLAGS_NO_MUTEX_UNLOCK)) != 0); ++ ++ for (i = 0, pos = 0; i < (unsigned int)count; ++ pos += elements[i++].size) ++ if (elements[i].size) { ++ if (vchiq_copy_from_user ++ (header->data + pos, elements[i].data, ++ (size_t) elements[i].size) != ++ VCHIQ_SUCCESS) { ++ mutex_unlock(&state->slot_mutex); ++ VCHIQ_SERVICE_STATS_INC(service, ++ error_count); ++ return VCHIQ_ERROR; ++ } ++ if (i == 0) { ++ if (SRVTRACE_ENABLED(service, ++ VCHIQ_LOG_INFO)) ++ vchiq_log_dump_mem("Sent", 0, ++ header->data + pos, ++ min(64u, ++ elements[0].size)); ++ } ++ } ++ ++ spin_lock("a_spinlock); ++ service_quota->message_use_count++; ++ ++ tx_end_index = ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1); ++ ++ /* If this transmission can't fit in the last slot used by any ++ ** service, the data_use_count must be increased. */ ++ if (tx_end_index != state->previous_data_index) { ++ state->previous_data_index = tx_end_index; ++ state->data_use_count++; ++ } ++ ++ /* If this isn't the same slot last used by this service, ++ ** the service's slot_use_count must be increased. */ ++ if (tx_end_index != service_quota->previous_tx_index) { ++ service_quota->previous_tx_index = tx_end_index; ++ slot_use_count = ++service_quota->slot_use_count; ++ } else { ++ slot_use_count = 0; ++ } ++ ++ spin_unlock("a_spinlock); ++ ++ if (slot_use_count) ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: qm:%d %s,%x - slot_use->%d (hdr %p)", ++ state->id, service->localport, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, ++ slot_use_count, header); ++ ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); ++ } else { ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: qm %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ if (size != 0) { ++ WARN_ON(!((count == 1) && (size == elements[0].size))); ++ memcpy(header->data, elements[0].data, ++ elements[0].size); ++ } ++ VCHIQ_STATS_INC(state, ctrl_tx_count); ++ } ++ ++ header->msgid = msgid; ++ header->size = size; ++ ++ { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ VCHIQ_MSG_TYPE(msgid), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid), ++ size); ++ } ++ ++ /* Make sure the new header is visible to the peer. */ ++ wmb(); ++ ++ /* Make the new tx_pos visible to the peer. */ ++ local->tx_pos = state->local_tx_pos; ++ wmb(); ++ ++ if (service && (type == VCHIQ_MSG_CLOSE)) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); ++ ++ if (!(flags & QMFLAGS_NO_MUTEX_UNLOCK)) ++ mutex_unlock(&state->slot_mutex); ++ ++ remote_event_signal(&state->remote->trigger); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++/* Called by the slot handler and application threads */ ++static VCHIQ_STATUS_T ++queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ int msgid, const VCHIQ_ELEMENT_T *elements, ++ int count, int size, int is_blocking) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_HEADER_T *header; ++ ++ local = state->local; ++ ++ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) && ++ (mutex_lock_interruptible(&state->sync_mutex) != 0)) ++ return VCHIQ_RETRY; ++ ++ remote_event_wait(&local->sync_release); ++ ++ rmb(); ++ ++ header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, ++ local->slot_sync); ++ ++ { ++ int oldmsgid = header->msgid; ++ if (oldmsgid != VCHIQ_MSGID_PADDING) ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: qms - msgid %x, not PADDING", ++ state->id, oldmsgid); ++ } ++ ++ if (service) { ++ int i, pos; ++ ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: qms %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ ++ for (i = 0, pos = 0; i < (unsigned int)count; ++ pos += elements[i++].size) ++ if (elements[i].size) { ++ if (vchiq_copy_from_user ++ (header->data + pos, elements[i].data, ++ (size_t) elements[i].size) != ++ VCHIQ_SUCCESS) { ++ mutex_unlock(&state->sync_mutex); ++ VCHIQ_SERVICE_STATS_INC(service, ++ error_count); ++ return VCHIQ_ERROR; ++ } ++ if (i == 0) { ++ if (vchiq_sync_log_level >= ++ VCHIQ_LOG_TRACE) ++ vchiq_log_dump_mem("Sent Sync", ++ 0, header->data + pos, ++ min(64u, ++ elements[0].size)); ++ } ++ } ++ ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); ++ } else { ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: qms %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ if (size != 0) { ++ WARN_ON(!((count == 1) && (size == elements[0].size))); ++ memcpy(header->data, elements[0].data, ++ elements[0].size); ++ } ++ VCHIQ_STATS_INC(state, ctrl_tx_count); ++ } ++ ++ header->size = size; ++ header->msgid = msgid; ++ ++ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ ++ vchiq_log_trace(vchiq_sync_log_level, ++ "Sent Sync Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ VCHIQ_MSG_TYPE(msgid), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid), ++ size); ++ } ++ ++ /* Make sure the new header is visible to the peer. */ ++ wmb(); ++ ++ remote_event_signal(&state->remote->sync_trigger); ++ ++ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) ++ mutex_unlock(&state->sync_mutex); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++static inline void ++claim_slot(VCHIQ_SLOT_INFO_T *slot) ++{ ++ slot->use_count++; ++} ++ ++static void ++release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info, ++ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_T *service) ++{ ++ int release_count; ++ ++ mutex_lock(&state->recycle_mutex); ++ ++ if (header) { ++ int msgid = header->msgid; ++ if (((msgid & VCHIQ_MSGID_CLAIMED) == 0) || ++ (service && service->closing)) { ++ mutex_unlock(&state->recycle_mutex); ++ return; ++ } ++ ++ /* Rewrite the message header to prevent a double ++ ** release */ ++ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; ++ } ++ ++ release_count = slot_info->release_count; ++ slot_info->release_count = ++release_count; ++ ++ if (release_count == slot_info->use_count) { ++ int slot_queue_recycle; ++ /* Add to the freed queue */ ++ ++ /* A read barrier is necessary here to prevent speculative ++ ** fetches of remote->slot_queue_recycle from overtaking the ++ ** mutex. */ ++ rmb(); ++ ++ slot_queue_recycle = state->remote->slot_queue_recycle; ++ state->remote->slot_queue[slot_queue_recycle & ++ VCHIQ_SLOT_QUEUE_MASK] = ++ SLOT_INDEX_FROM_INFO(state, slot_info); ++ state->remote->slot_queue_recycle = slot_queue_recycle + 1; ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: release_slot %d - recycle->%x", ++ state->id, SLOT_INDEX_FROM_INFO(state, slot_info), ++ state->remote->slot_queue_recycle); ++ ++ /* A write barrier is necessary, but remote_event_signal ++ ** contains one. */ ++ remote_event_signal(&state->remote->recycle); ++ } ++ ++ mutex_unlock(&state->recycle_mutex); ++} ++ ++/* Called by the slot handler - don't hold the bulk mutex */ ++static VCHIQ_STATUS_T ++notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue, ++ int retry_poll) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: nb:%d %cx - p=%x rn=%x r=%x", ++ service->state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->process, queue->remote_notify, queue->remove); ++ ++ if (service->state->is_master) { ++ while (queue->remote_notify != queue->process) { ++ VCHIQ_BULK_T *bulk = ++ &queue->bulks[BULK_INDEX(queue->remote_notify)]; ++ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE; ++ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport, ++ service->remoteport); ++ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 }; ++ /* Only reply to non-dummy bulk requests */ ++ if (bulk->remote_data) { ++ status = queue_message(service->state, NULL, ++ msgid, &element, 1, 4, 0); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ queue->remote_notify++; ++ } ++ } else { ++ queue->remote_notify = queue->process; ++ } ++ ++ if (status == VCHIQ_SUCCESS) { ++ while (queue->remove != queue->remote_notify) { ++ VCHIQ_BULK_T *bulk = ++ &queue->bulks[BULK_INDEX(queue->remove)]; ++ ++ /* Only generate callbacks for non-dummy bulk ++ ** requests, and non-terminated services */ ++ if (bulk->data && service->instance) { ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) { ++ if (bulk->dir == VCHIQ_BULK_TRANSMIT) { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ++ bulk_tx_bytes, ++ bulk->actual); ++ } else { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ++ bulk_rx_bytes, ++ bulk->actual); ++ } ++ } else { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_aborted_count); ++ } ++ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) { ++ struct bulk_waiter *waiter; ++ spin_lock(&bulk_waiter_spinlock); ++ waiter = bulk->userdata; ++ if (waiter) { ++ waiter->actual = bulk->actual; ++ up(&waiter->event); ++ } ++ spin_unlock(&bulk_waiter_spinlock); ++ } else if (bulk->mode == ++ VCHIQ_BULK_MODE_CALLBACK) { ++ VCHIQ_REASON_T reason = (bulk->dir == ++ VCHIQ_BULK_TRANSMIT) ? ++ ((bulk->actual == ++ VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_TRANSMIT_ABORTED : ++ VCHIQ_BULK_TRANSMIT_DONE) : ++ ((bulk->actual == ++ VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_RECEIVE_ABORTED : ++ VCHIQ_BULK_RECEIVE_DONE); ++ status = make_service_callback(service, ++ reason, NULL, bulk->userdata); ++ if (status == VCHIQ_RETRY) ++ break; ++ } ++ } ++ ++ queue->remove++; ++ up(&service->bulk_remove_event); ++ } ++ if (!retry_poll) ++ status = VCHIQ_SUCCESS; ++ } ++ ++ if (status == VCHIQ_RETRY) ++ request_poll(service->state, service, ++ (queue == &service->bulk_tx) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ ++ return status; ++} ++ ++/* Called by the slot handler thread */ ++static void ++poll_services(VCHIQ_STATE_T *state) ++{ ++ int group, i; ++ ++ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) { ++ uint32_t flags; ++ flags = atomic_xchg(&state->poll_services[group], 0); ++ for (i = 0; flags; i++) { ++ if (flags & (1 << i)) { ++ VCHIQ_SERVICE_T *service = ++ find_service_by_port(state, ++ (group<<5) + i); ++ uint32_t service_flags; ++ flags &= ~(1 << i); ++ if (!service) ++ continue; ++ service_flags = ++ atomic_xchg(&service->poll_flags, 0); ++ if (service_flags & ++ (1 << VCHIQ_POLL_REMOVE)) { ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: ps - remove %d<->%d", ++ state->id, service->localport, ++ service->remoteport); ++ ++ /* Make it look like a client, because ++ it must be removed and not left in ++ the LISTENING state. */ ++ service->public_fourcc = ++ VCHIQ_FOURCC_INVALID; ++ ++ if (vchiq_close_service_internal( ++ service, 0/*!close_recvd*/) != ++ VCHIQ_SUCCESS) ++ request_poll(state, service, ++ VCHIQ_POLL_REMOVE); ++ } else if (service_flags & ++ (1 << VCHIQ_POLL_TERMINATE)) { ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: ps - terminate %d<->%d", ++ state->id, service->localport, ++ service->remoteport); ++ if (vchiq_close_service_internal( ++ service, 0/*!close_recvd*/) != ++ VCHIQ_SUCCESS) ++ request_poll(state, service, ++ VCHIQ_POLL_TERMINATE); ++ } ++ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY)) ++ notify_bulks(service, ++ &service->bulk_tx, ++ 1/*retry_poll*/); ++ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY)) ++ notify_bulks(service, ++ &service->bulk_rx, ++ 1/*retry_poll*/); ++ unlock_service(service); ++ } ++ } ++ } ++} ++ ++/* Called by the slot handler or application threads, holding the bulk mutex. */ ++static int ++resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ int resolved = 0; ++ int rc; ++ ++ while ((queue->process != queue->local_insert) && ++ (queue->process != queue->remote_insert)) { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: rb:%d %cx - li=%x ri=%x p=%x", ++ state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, ++ queue->process); ++ ++ WARN_ON(!((int)(queue->local_insert - queue->process) > 0)); ++ WARN_ON(!((int)(queue->remote_insert - queue->process) > 0)); ++ ++ rc = mutex_lock_interruptible(&state->bulk_transfer_mutex); ++ if (rc != 0) ++ break; ++ ++ vchiq_transfer_bulk(bulk); ++ mutex_unlock(&state->bulk_transfer_mutex); ++ ++ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) { ++ const char *header = (queue == &service->bulk_tx) ? ++ "Send Bulk to" : "Recv Bulk from"; ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "%s %c%c%c%c d:%d len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data); ++ else ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d," ++ " rx len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data); ++ } ++ ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ resolved++; ++ } ++ return resolved; ++} ++ ++/* Called with the bulk_mutex held */ ++static void ++abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) ++{ ++ int is_tx = (queue == &service->bulk_tx); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: aob:%d %cx - li=%x ri=%x p=%x", ++ service->state->id, service->localport, is_tx ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++ WARN_ON(!((int)(queue->local_insert - queue->process) >= 0)); ++ WARN_ON(!((int)(queue->remote_insert - queue->process) >= 0)); ++ ++ while ((queue->process != queue->local_insert) || ++ (queue->process != queue->remote_insert)) { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ if (queue->process == queue->remote_insert) { ++ /* fabricate a matching dummy bulk */ ++ bulk->remote_data = NULL; ++ bulk->remote_size = 0; ++ queue->remote_insert++; ++ } ++ ++ if (queue->process != queue->local_insert) { ++ vchiq_complete_bulk(bulk); ++ ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d, " ++ "rx len:%d", ++ is_tx ? "Send Bulk to" : "Recv Bulk from", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size); ++ } else { ++ /* fabricate a matching dummy bulk */ ++ bulk->data = NULL; ++ bulk->size = 0; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT : ++ VCHIQ_BULK_RECEIVE; ++ queue->local_insert++; ++ } ++ ++ queue->process++; ++ } ++} ++ ++/* Called from the slot handler thread */ ++static void ++pause_bulks(VCHIQ_STATE_T *state) ++{ ++ if (unlikely(atomic_inc_return(&pause_bulks_count) != 1)) { ++ WARN_ON_ONCE(1); ++ atomic_set(&pause_bulks_count, 1); ++ return; ++ } ++ ++ /* Block bulk transfers from all services */ ++ mutex_lock(&state->bulk_transfer_mutex); ++} ++ ++/* Called from the slot handler thread */ ++static void ++resume_bulks(VCHIQ_STATE_T *state) ++{ ++ int i; ++ if (unlikely(atomic_dec_return(&pause_bulks_count) != 0)) { ++ WARN_ON_ONCE(1); ++ atomic_set(&pause_bulks_count, 0); ++ return; ++ } ++ ++ /* Allow bulk transfers from all services */ ++ mutex_unlock(&state->bulk_transfer_mutex); ++ ++ if (state->deferred_bulks == 0) ++ return; ++ ++ /* Deal with any bulks which had to be deferred due to being in ++ * paused state. Don't try to match up to number of deferred bulks ++ * in case we've had something come and close the service in the ++ * interim - just process all bulk queues for all services */ ++ vchiq_log_info(vchiq_core_log_level, "%s: processing %d deferred bulks", ++ __func__, state->deferred_bulks); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ int resolved_rx = 0; ++ int resolved_tx = 0; ++ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) ++ continue; ++ ++ mutex_lock(&service->bulk_mutex); ++ resolved_rx = resolve_bulks(service, &service->bulk_rx); ++ resolved_tx = resolve_bulks(service, &service->bulk_tx); ++ mutex_unlock(&service->bulk_mutex); ++ if (resolved_rx) ++ notify_bulks(service, &service->bulk_rx, 1); ++ if (resolved_tx) ++ notify_bulks(service, &service->bulk_tx, 1); ++ } ++ state->deferred_bulks = 0; ++} ++ ++static int ++parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ msgid = header->msgid; ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ if (size >= sizeof(struct vchiq_open_payload)) { ++ const struct vchiq_open_payload *payload = ++ (struct vchiq_open_payload *)header->data; ++ unsigned int fourcc; ++ ++ fourcc = payload->fourcc; ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs OPEN@%x (%d->'%c%c%c%c')", ++ state->id, (unsigned int)header, ++ localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc)); ++ ++ service = get_listening_service(state, fourcc); ++ ++ if (service) { ++ /* A matching service exists */ ++ short version = payload->version; ++ short version_min = payload->version_min; ++ if ((service->version < version_min) || ++ (version < service->version_min)) { ++ /* Version mismatch */ ++ vchiq_loud_error_header(); ++ vchiq_loud_error("%d: service %d (%c%c%c%c) " ++ "version mismatch - local (%d, min %d)" ++ " vs. remote (%d, min %d)", ++ state->id, service->localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ service->version, service->version_min, ++ version, version_min); ++ vchiq_loud_error_footer(); ++ unlock_service(service); ++ service = NULL; ++ goto fail_open; ++ } ++ service->peer_version = version; ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { ++ struct vchiq_openack_payload ack_payload = { ++ service->version ++ }; ++ VCHIQ_ELEMENT_T body = { ++ &ack_payload, ++ sizeof(ack_payload) ++ }; ++ ++ if (state->version_common < ++ VCHIQ_VERSION_SYNCHRONOUS_MODE) ++ service->sync = 0; ++ ++ /* Acknowledge the OPEN */ ++ if (service->sync && ++ (state->version_common >= ++ VCHIQ_VERSION_SYNCHRONOUS_MODE)) { ++ if (queue_message_sync(state, NULL, ++ VCHIQ_MAKE_MSG( ++ VCHIQ_MSG_OPENACK, ++ service->localport, ++ remoteport), ++ &body, 1, sizeof(ack_payload), ++ 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ } else { ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG( ++ VCHIQ_MSG_OPENACK, ++ service->localport, ++ remoteport), ++ &body, 1, sizeof(ack_payload), ++ 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ } ++ ++ /* The service is now open */ ++ vchiq_set_service_state(service, ++ service->sync ? VCHIQ_SRVSTATE_OPENSYNC ++ : VCHIQ_SRVSTATE_OPEN); ++ } ++ ++ service->remoteport = remoteport; ++ service->client_id = ((int *)header->data)[1]; ++ if (make_service_callback(service, VCHIQ_SERVICE_OPENED, ++ NULL, NULL) == VCHIQ_RETRY) { ++ /* Bail out if not ready */ ++ service->remoteport = VCHIQ_PORT_FREE; ++ goto bail_not_ready; ++ } ++ ++ /* Success - the message has been dealt with */ ++ unlock_service(service); ++ return 1; ++ } ++ } ++ ++fail_open: ++ /* No available service, or an invalid request - send a CLOSE */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ ++ return 1; ++ ++bail_not_ready: ++ if (service) ++ unlock_service(service); ++ ++ return 0; ++} ++ ++/* Called by the slot handler thread */ ++static void ++parse_rx_slots(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_SHARED_STATE_T *remote = state->remote; ++ VCHIQ_SERVICE_T *service = NULL; ++ int tx_pos; ++ DEBUG_INITIALISE(state->local) ++ ++ tx_pos = remote->tx_pos; ++ ++ while (state->rx_pos != tx_pos) { ++ VCHIQ_HEADER_T *header; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (!state->rx_data) { ++ int rx_index; ++ WARN_ON(!((state->rx_pos & VCHIQ_SLOT_MASK) == 0)); ++ rx_index = remote->slot_queue[ ++ SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state, ++ rx_index); ++ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index); ++ ++ /* Initialise use_count to one, and increment ++ ** release_count at the end of the slot to avoid ++ ** releasing the slot prematurely. */ ++ state->rx_info->use_count = 1; ++ state->rx_info->release_count = 0; ++ } ++ ++ header = (VCHIQ_HEADER_T *)(state->rx_data + ++ (state->rx_pos & VCHIQ_SLOT_MASK)); ++ DEBUG_VALUE(PARSE_HEADER, (int)header); ++ msgid = header->msgid; ++ DEBUG_VALUE(PARSE_MSGID, msgid); ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ ++ if (type != VCHIQ_MSG_DATA) ++ VCHIQ_STATS_INC(state, ctrl_rx_count); ++ ++ switch (type) { ++ case VCHIQ_MSG_OPENACK: ++ case VCHIQ_MSG_CLOSE: ++ case VCHIQ_MSG_DATA: ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ service = find_service_by_port(state, localport); ++ if ((!service || ++ ((service->remoteport != remoteport) && ++ (service->remoteport != VCHIQ_PORT_FREE))) && ++ (localport == 0) && ++ (type == VCHIQ_MSG_CLOSE)) { ++ /* This could be a CLOSE from a client which ++ hadn't yet received the OPENACK - look for ++ the connected service */ ++ if (service) ++ unlock_service(service); ++ service = get_connected_service(state, ++ remoteport); ++ if (service) ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) - " ++ "found connected service %d", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ service->localport); ++ } ++ ++ if (!service) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) - " ++ "invalid/closed service %d", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, localport); ++ goto skip_message; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d " ++ "len:%d", ++ msg_type_str(type), type, ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ remoteport, localport, size); ++ if (size > 0) ++ vchiq_log_dump_mem("Rcvd", 0, header->data, ++ min(64, size)); ++ } ++ ++ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size) ++ > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "header %x (msgid %x) - size %x too big for " ++ "slot", ++ (unsigned int)header, (unsigned int)msgid, ++ (unsigned int)size); ++ WARN(1, "oversized for slot\n"); ++ } ++ ++ switch (type) { ++ case VCHIQ_MSG_OPEN: ++ WARN_ON(!(VCHIQ_MSG_DSTPORT(msgid) == 0)); ++ if (!parse_open(state, header)) ++ goto bail_not_ready; ++ break; ++ case VCHIQ_MSG_OPENACK: ++ if (size >= sizeof(struct vchiq_openack_payload)) { ++ const struct vchiq_openack_payload *payload = ++ (struct vchiq_openack_payload *) ++ header->data; ++ service->peer_version = payload->version; ++ } ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs OPENACK@%x,%x (%d->%d) v:%d", ++ state->id, (unsigned int)header, size, ++ remoteport, localport, service->peer_version); ++ if (service->srvstate == ++ VCHIQ_SRVSTATE_OPENING) { ++ service->remoteport = remoteport; ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_OPEN); ++ up(&service->remove_event); ++ } else ++ vchiq_log_error(vchiq_core_log_level, ++ "OPENACK received in state %s", ++ srvstate_names[service->srvstate]); ++ break; ++ case VCHIQ_MSG_CLOSE: ++ WARN_ON(size != 0); /* There should be no data */ ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs CLOSE@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ ++ mark_service_closing_internal(service, 1); ++ ++ if (vchiq_close_service_internal(service, ++ 1/*close_recvd*/) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "Close Service %c%c%c%c s:%u d:%d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->localport, ++ service->remoteport); ++ break; ++ case VCHIQ_MSG_DATA: ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs DATA@%x,%x (%d->%d)", ++ state->id, (unsigned int)header, size, ++ remoteport, localport); ++ ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) { ++ header->msgid = msgid | VCHIQ_MSGID_CLAIMED; ++ claim_slot(state->rx_info); ++ DEBUG_TRACE(PARSE_LINE); ++ if (make_service_callback(service, ++ VCHIQ_MESSAGE_AVAILABLE, header, ++ NULL) == VCHIQ_RETRY) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes, ++ size); ++ } else { ++ VCHIQ_STATS_INC(state, error_count); ++ } ++ break; ++ case VCHIQ_MSG_CONNECT: ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs CONNECT@%x", ++ state->id, (unsigned int)header); ++ state->version_common = ((VCHIQ_SLOT_ZERO_T *) ++ state->slot_data)->version; ++ up(&state->connect); ++ break; ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: { ++ VCHIQ_BULK_QUEUE_T *queue; ++ WARN_ON(!state->is_master); ++ queue = (type == VCHIQ_MSG_BULK_RX) ? ++ &service->bulk_tx : &service->bulk_rx; ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) { ++ VCHIQ_BULK_T *bulk; ++ int resolved = 0; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (mutex_lock_interruptible( ++ &service->bulk_mutex) != 0) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ ++ WARN_ON(!(queue->remote_insert < queue->remove + ++ VCHIQ_NUM_SERVICE_BULKS)); ++ bulk = &queue->bulks[ ++ BULK_INDEX(queue->remote_insert)]; ++ bulk->remote_data = ++ (void *)((int *)header->data)[0]; ++ bulk->remote_size = ((int *)header->data)[1]; ++ wmb(); ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->remote_size, ++ (unsigned int)bulk->remote_data); ++ ++ queue->remote_insert++; ++ ++ if (atomic_read(&pause_bulks_count)) { ++ state->deferred_bulks++; ++ vchiq_log_info(vchiq_core_log_level, ++ "%s: deferring bulk (%d)", ++ __func__, ++ state->deferred_bulks); ++ if (state->conn_state != ++ VCHIQ_CONNSTATE_PAUSE_SENT) ++ vchiq_log_error( ++ vchiq_core_log_level, ++ "%s: bulks paused in " ++ "unexpected state %s", ++ __func__, ++ conn_state_names[ ++ state->conn_state]); ++ } else if (state->conn_state == ++ VCHIQ_CONNSTATE_CONNECTED) { ++ DEBUG_TRACE(PARSE_LINE); ++ resolved = resolve_bulks(service, ++ queue); ++ } ++ ++ mutex_unlock(&service->bulk_mutex); ++ if (resolved) ++ notify_bulks(service, queue, ++ 1/*retry_poll*/); ++ } ++ } break; ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ WARN_ON(state->is_master); ++ if ((service->remoteport == remoteport) ++ && (service->srvstate != ++ VCHIQ_SRVSTATE_FREE)) { ++ VCHIQ_BULK_QUEUE_T *queue; ++ VCHIQ_BULK_T *bulk; ++ ++ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ? ++ &service->bulk_rx : &service->bulk_tx; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (mutex_lock_interruptible( ++ &service->bulk_mutex) != 0) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ if ((int)(queue->remote_insert - ++ queue->local_insert) >= 0) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) " ++ "unexpected (ri=%d,li=%d)", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ queue->remote_insert, ++ queue->local_insert); ++ mutex_unlock(&service->bulk_mutex); ++ break; ++ } ++ ++ BUG_ON(queue->process == queue->local_insert); ++ BUG_ON(queue->process != queue->remote_insert); ++ ++ bulk = &queue->bulks[ ++ BULK_INDEX(queue->remote_insert)]; ++ bulk->actual = *(int *)header->data; ++ queue->remote_insert++; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->actual, (unsigned int)bulk->data); ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs:%d %cx li=%x ri=%x p=%x", ++ state->id, localport, ++ (type == VCHIQ_MSG_BULK_RX_DONE) ? ++ 'r' : 't', ++ queue->local_insert, ++ queue->remote_insert, queue->process); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ WARN_ON(queue->process == queue->local_insert); ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ mutex_unlock(&service->bulk_mutex); ++ DEBUG_TRACE(PARSE_LINE); ++ notify_bulks(service, queue, 1/*retry_poll*/); ++ DEBUG_TRACE(PARSE_LINE); ++ } ++ break; ++ case VCHIQ_MSG_PADDING: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs PADDING@%x,%x", ++ state->id, (unsigned int)header, size); ++ break; ++ case VCHIQ_MSG_PAUSE: ++ /* If initiated, signal the application thread */ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs PAUSE@%x,%x", ++ state->id, (unsigned int)header, size); ++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: PAUSE received in state PAUSED", ++ state->id); ++ break; ++ } ++ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) { ++ /* Send a PAUSE in response */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), ++ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK) ++ == VCHIQ_RETRY) ++ goto bail_not_ready; ++ if (state->is_master) ++ pause_bulks(state); ++ } ++ /* At this point slot_mutex is held */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED); ++ vchiq_platform_paused(state); ++ break; ++ case VCHIQ_MSG_RESUME: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs RESUME@%x,%x", ++ state->id, (unsigned int)header, size); ++ /* Release the slot mutex */ ++ mutex_unlock(&state->slot_mutex); ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ break; ++ ++ case VCHIQ_MSG_REMOTE_USE: ++ vchiq_on_remote_use(state); ++ break; ++ case VCHIQ_MSG_REMOTE_RELEASE: ++ vchiq_on_remote_release(state); ++ break; ++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: ++ vchiq_on_remote_use_active(state); ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs invalid msgid %x@%x,%x", ++ state->id, msgid, (unsigned int)header, size); ++ WARN(1, "invalid message\n"); ++ break; ++ } ++ ++skip_message: ++ if (service) { ++ unlock_service(service); ++ service = NULL; ++ } ++ ++ state->rx_pos += calc_stride(size); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ /* Perform some housekeeping when the end of the slot is ++ ** reached. */ ++ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) { ++ /* Remove the extra reference count. */ ++ release_slot(state, state->rx_info, NULL, NULL); ++ state->rx_data = NULL; ++ } ++ } ++ ++bail_not_ready: ++ if (service) ++ unlock_service(service); ++} ++ ++/* Called by the slot handler thread */ ++static int ++slot_handler_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ DEBUG_INITIALISE(local) ++ ++ while (1) { ++ DEBUG_COUNT(SLOT_HANDLER_COUNT); ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ remote_event_wait(&local->trigger); ++ ++ rmb(); ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ if (state->poll_needed) { ++ /* Check if we need to suspend - may change our ++ * conn_state */ ++ vchiq_platform_check_suspend(state); ++ ++ state->poll_needed = 0; ++ ++ /* Handle service polling and other rare conditions here ++ ** out of the mainline code */ ++ switch (state->conn_state) { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Poll the services as requested */ ++ poll_services(state); ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSING: ++ if (state->is_master) ++ pause_bulks(state); ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), ++ NULL, 0, 0, ++ QMFLAGS_NO_MUTEX_UNLOCK) ++ != VCHIQ_RETRY) { ++ vchiq_set_conn_state(state, ++ VCHIQ_CONNSTATE_PAUSE_SENT); ++ } else { ++ if (state->is_master) ++ resume_bulks(state); ++ /* Retry later */ ++ state->poll_needed = 1; ++ } ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSED: ++ vchiq_platform_resume(state); ++ break; ++ ++ case VCHIQ_CONNSTATE_RESUMING: ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0), ++ NULL, 0, 0, QMFLAGS_NO_MUTEX_LOCK) ++ != VCHIQ_RETRY) { ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, ++ VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ } else { ++ /* This should really be impossible, ++ ** since the PAUSE should have flushed ++ ** through outstanding messages. */ ++ vchiq_log_error(vchiq_core_log_level, ++ "Failed to send RESUME " ++ "message"); ++ BUG(); ++ } ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSE_TIMEOUT: ++ case VCHIQ_CONNSTATE_RESUME_TIMEOUT: ++ vchiq_platform_handle_timeout(state); ++ break; ++ default: ++ break; ++ } ++ ++ ++ } ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ parse_rx_slots(state); ++ } ++ return 0; ++} ++ ++ ++/* Called by the recycle thread */ ++static int ++recycle_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ ++ while (1) { ++ remote_event_wait(&local->recycle); ++ ++ process_free_queue(state); ++ } ++ return 0; ++} ++ ++ ++/* Called by the sync thread */ ++static int ++sync_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, ++ state->remote->slot_sync); ++ ++ while (1) { ++ VCHIQ_SERVICE_T *service; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ remote_event_wait(&local->sync_trigger); ++ ++ rmb(); ++ ++ msgid = header->msgid; ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ ++ service = find_service_by_port(state, localport); ++ ++ if (!service) { ++ vchiq_log_error(vchiq_sync_log_level, ++ "%d: sf %s@%x (%d->%d) - " ++ "invalid/closed service %d", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, localport); ++ release_message_sync(state, header); ++ continue; ++ } ++ ++ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ vchiq_log_trace(vchiq_sync_log_level, ++ "Rcvd Msg %s from %c%c%c%c s:%d d:%d len:%d", ++ msg_type_str(type), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ remoteport, localport, size); ++ if (size > 0) ++ vchiq_log_dump_mem("Rcvd", 0, header->data, ++ min(64, size)); ++ } ++ ++ switch (type) { ++ case VCHIQ_MSG_OPENACK: ++ if (size >= sizeof(struct vchiq_openack_payload)) { ++ const struct vchiq_openack_payload *payload = ++ (struct vchiq_openack_payload *) ++ header->data; ++ service->peer_version = payload->version; ++ } ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: sf OPENACK@%x,%x (%d->%d) v:%d", ++ state->id, (unsigned int)header, size, ++ remoteport, localport, service->peer_version); ++ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) { ++ service->remoteport = remoteport; ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_OPENSYNC); ++ service->sync = 1; ++ up(&service->remove_event); ++ } ++ release_message_sync(state, header); ++ break; ++ ++ case VCHIQ_MSG_DATA: ++ vchiq_log_trace(vchiq_sync_log_level, ++ "%d: sf DATA@%x,%x (%d->%d)", ++ state->id, (unsigned int)header, size, ++ remoteport, localport); ++ ++ if ((service->remoteport == remoteport) && ++ (service->srvstate == ++ VCHIQ_SRVSTATE_OPENSYNC)) { ++ if (make_service_callback(service, ++ VCHIQ_MESSAGE_AVAILABLE, header, ++ NULL) == VCHIQ_RETRY) ++ vchiq_log_error(vchiq_sync_log_level, ++ "synchronous callback to " ++ "service %d returns " ++ "VCHIQ_RETRY", ++ localport); ++ } ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_sync_log_level, ++ "%d: sf unexpected msgid %x@%x,%x", ++ state->id, msgid, (unsigned int)header, size); ++ release_message_sync(state, header); ++ break; ++ } ++ ++ unlock_service(service); ++ } ++ ++ return 0; ++} ++ ++ ++static void ++init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue) ++{ ++ queue->local_insert = 0; ++ queue->remote_insert = 0; ++ queue->process = 0; ++ queue->remote_notify = 0; ++ queue->remove = 0; ++} ++ ++ ++inline const char * ++get_conn_state_name(VCHIQ_CONNSTATE_T conn_state) ++{ ++ return conn_state_names[conn_state]; ++} ++ ++ ++VCHIQ_SLOT_ZERO_T * ++vchiq_init_slots(void *mem_base, int mem_size) ++{ ++ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK; ++ VCHIQ_SLOT_ZERO_T *slot_zero = ++ (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align); ++ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE; ++ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS; ++ ++ /* Ensure there is enough memory to run an absolutely minimum system */ ++ num_slots -= first_data_slot; ++ ++ if (num_slots < 4) { ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_init_slots - insufficient memory %x bytes", ++ mem_size); ++ return NULL; ++ } ++ ++ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T)); ++ ++ slot_zero->magic = VCHIQ_MAGIC; ++ slot_zero->version = VCHIQ_VERSION; ++ slot_zero->version_min = VCHIQ_VERSION_MIN; ++ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T); ++ slot_zero->slot_size = VCHIQ_SLOT_SIZE; ++ slot_zero->max_slots = VCHIQ_MAX_SLOTS; ++ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE; ++ ++ slot_zero->master.slot_sync = first_data_slot; ++ slot_zero->master.slot_first = first_data_slot + 1; ++ slot_zero->master.slot_last = first_data_slot + (num_slots/2) - 1; ++ slot_zero->slave.slot_sync = first_data_slot + (num_slots/2); ++ slot_zero->slave.slot_first = first_data_slot + (num_slots/2) + 1; ++ slot_zero->slave.slot_last = first_data_slot + num_slots - 1; ++ ++ return slot_zero; ++} ++ ++VCHIQ_STATUS_T ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, ++ int is_master) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_STATUS_T status; ++ char threadname[10]; ++ static int id; ++ int i; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%s: slot_zero = 0x%08lx, is_master = %d", ++ __func__, (unsigned long)slot_zero, is_master); ++ ++ /* Check the input configuration */ ++ ++ if (slot_zero->magic != VCHIQ_MAGIC) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Invalid VCHIQ magic value found."); ++ vchiq_loud_error("slot_zero=%x: magic=%x (expected %x)", ++ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->version < VCHIQ_VERSION_MIN) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Incompatible VCHIQ versions found."); ++ vchiq_loud_error("slot_zero=%x: VideoCore version=%d " ++ "(minimum %d)", ++ (unsigned int)slot_zero, slot_zero->version, ++ VCHIQ_VERSION_MIN); ++ vchiq_loud_error("Restart with a newer VideoCore image."); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (VCHIQ_VERSION < slot_zero->version_min) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Incompatible VCHIQ versions found."); ++ vchiq_loud_error("slot_zero=%x: version=%d (VideoCore " ++ "minimum %d)", ++ (unsigned int)slot_zero, VCHIQ_VERSION, ++ slot_zero->version_min); ++ vchiq_loud_error("Restart with a newer kernel."); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if ((slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) || ++ (slot_zero->slot_size != VCHIQ_SLOT_SIZE) || ++ (slot_zero->max_slots != VCHIQ_MAX_SLOTS) || ++ (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)) { ++ vchiq_loud_error_header(); ++ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) ++ vchiq_loud_error("slot_zero=%x: slot_zero_size=%x " ++ "(expected %x)", ++ (unsigned int)slot_zero, ++ slot_zero->slot_zero_size, ++ sizeof(VCHIQ_SLOT_ZERO_T)); ++ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE) ++ vchiq_loud_error("slot_zero=%x: slot_size=%d " ++ "(expected %d", ++ (unsigned int)slot_zero, slot_zero->slot_size, ++ VCHIQ_SLOT_SIZE); ++ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS) ++ vchiq_loud_error("slot_zero=%x: max_slots=%d " ++ "(expected %d)", ++ (unsigned int)slot_zero, slot_zero->max_slots, ++ VCHIQ_MAX_SLOTS); ++ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE) ++ vchiq_loud_error("slot_zero=%x: max_slots_per_side=%d " ++ "(expected %d)", ++ (unsigned int)slot_zero, ++ slot_zero->max_slots_per_side, ++ VCHIQ_MAX_SLOTS_PER_SIDE); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (VCHIQ_VERSION < slot_zero->version) ++ slot_zero->version = VCHIQ_VERSION; ++ ++ if (is_master) { ++ local = &slot_zero->master; ++ remote = &slot_zero->slave; ++ } else { ++ local = &slot_zero->slave; ++ remote = &slot_zero->master; ++ } ++ ++ if (local->initialised) { ++ vchiq_loud_error_header(); ++ if (remote->initialised) ++ vchiq_loud_error("local state has already been " ++ "initialised"); ++ else ++ vchiq_loud_error("master/slave mismatch - two %ss", ++ is_master ? "master" : "slave"); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ memset(state, 0, sizeof(VCHIQ_STATE_T)); ++ ++ state->id = id++; ++ state->is_master = is_master; ++ ++ /* ++ initialize shared state pointers ++ */ ++ ++ state->local = local; ++ state->remote = remote; ++ state->slot_data = (VCHIQ_SLOT_T *)slot_zero; ++ ++ /* ++ initialize events and mutexes ++ */ ++ ++ sema_init(&state->connect, 0); ++ mutex_init(&state->mutex); ++ sema_init(&state->trigger_event, 0); ++ sema_init(&state->recycle_event, 0); ++ sema_init(&state->sync_trigger_event, 0); ++ sema_init(&state->sync_release_event, 0); ++ ++ mutex_init(&state->slot_mutex); ++ mutex_init(&state->recycle_mutex); ++ mutex_init(&state->sync_mutex); ++ mutex_init(&state->bulk_transfer_mutex); ++ ++ sema_init(&state->slot_available_event, 0); ++ sema_init(&state->slot_remove_event, 0); ++ sema_init(&state->data_quota_event, 0); ++ ++ state->slot_queue_available = 0; ++ ++ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[i]; ++ sema_init(&service_quota->quota_event, 0); ++ } ++ ++ for (i = local->slot_first; i <= local->slot_last; i++) { ++ local->slot_queue[state->slot_queue_available++] = i; ++ up(&state->slot_available_event); ++ } ++ ++ state->default_slot_quota = state->slot_queue_available/2; ++ state->default_message_quota = ++ min((unsigned short)(state->default_slot_quota * 256), ++ (unsigned short)~0); ++ ++ state->previous_data_index = -1; ++ state->data_use_count = 0; ++ state->data_quota = state->slot_queue_available - 1; ++ ++ local->trigger.event = &state->trigger_event; ++ remote_event_create(&local->trigger); ++ local->tx_pos = 0; ++ ++ local->recycle.event = &state->recycle_event; ++ remote_event_create(&local->recycle); ++ local->slot_queue_recycle = state->slot_queue_available; ++ ++ local->sync_trigger.event = &state->sync_trigger_event; ++ remote_event_create(&local->sync_trigger); ++ ++ local->sync_release.event = &state->sync_release_event; ++ remote_event_create(&local->sync_release); ++ ++ /* At start-of-day, the slot is empty and available */ ++ ((VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, local->slot_sync))->msgid ++ = VCHIQ_MSGID_PADDING; ++ remote_event_signal_local(&local->sync_release); ++ ++ local->debug[DEBUG_ENTRIES] = DEBUG_MAX; ++ ++ status = vchiq_platform_init_state(state); ++ ++ /* ++ bring up slot handler thread ++ */ ++ snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); ++ state->slot_handler_thread = kthread_create(&slot_handler_func, ++ (void *)state, ++ threadname); ++ ++ if (state->slot_handler_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->slot_handler_thread, -19); ++ wake_up_process(state->slot_handler_thread); ++ ++ snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); ++ state->recycle_thread = kthread_create(&recycle_func, ++ (void *)state, ++ threadname); ++ if (state->recycle_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->recycle_thread, -19); ++ wake_up_process(state->recycle_thread); ++ ++ snprintf(threadname, sizeof(threadname), "VCHIQs-%d", state->id); ++ state->sync_thread = kthread_create(&sync_func, ++ (void *)state, ++ threadname); ++ if (state->sync_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->sync_thread, -20); ++ wake_up_process(state->sync_thread); ++ ++ BUG_ON(state->id >= VCHIQ_MAX_STATES); ++ vchiq_states[state->id] = state; ++ ++ /* Indicate readiness to the other side */ ++ local->initialised = 1; ++ ++ return status; ++} ++ ++/* Called from application thread when a client or server service is created. */ ++VCHIQ_SERVICE_T * ++vchiq_add_service_internal(VCHIQ_STATE_T *state, ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term) ++{ ++ VCHIQ_SERVICE_T *service; ++ ++ service = kmalloc(sizeof(VCHIQ_SERVICE_T), GFP_KERNEL); ++ if (service) { ++ service->base.fourcc = params->fourcc; ++ service->base.callback = params->callback; ++ service->base.userdata = params->userdata; ++ service->handle = VCHIQ_SERVICE_HANDLE_INVALID; ++ service->ref_count = 1; ++ service->srvstate = VCHIQ_SRVSTATE_FREE; ++ service->userdata_term = userdata_term; ++ service->localport = VCHIQ_PORT_FREE; ++ service->remoteport = VCHIQ_PORT_FREE; ++ ++ service->public_fourcc = (srvstate == VCHIQ_SRVSTATE_OPENING) ? ++ VCHIQ_FOURCC_INVALID : params->fourcc; ++ service->client_id = 0; ++ service->auto_close = 1; ++ service->sync = 0; ++ service->closing = 0; ++ service->trace = 0; ++ atomic_set(&service->poll_flags, 0); ++ service->version = params->version; ++ service->version_min = params->version_min; ++ service->state = state; ++ service->instance = instance; ++ service->service_use_count = 0; ++ init_bulk_queue(&service->bulk_tx); ++ init_bulk_queue(&service->bulk_rx); ++ sema_init(&service->remove_event, 0); ++ sema_init(&service->bulk_remove_event, 0); ++ mutex_init(&service->bulk_mutex); ++ memset(&service->stats, 0, sizeof(service->stats)); ++ } else { ++ vchiq_log_error(vchiq_core_log_level, ++ "Out of memory"); ++ } ++ ++ if (service) { ++ VCHIQ_SERVICE_T **pservice = NULL; ++ int i; ++ ++ /* Although it is perfectly possible to use service_spinlock ++ ** to protect the creation of services, it is overkill as it ++ ** disables interrupts while the array is searched. ++ ** The only danger is of another thread trying to create a ++ ** service - service deletion is safe. ++ ** Therefore it is preferable to use state->mutex which, ++ ** although slower to claim, doesn't block interrupts while ++ ** it is held. ++ */ ++ ++ mutex_lock(&state->mutex); ++ ++ /* Prepare to use a previously unused service */ ++ if (state->unused_service < VCHIQ_MAX_SERVICES) ++ pservice = &state->services[state->unused_service]; ++ ++ if (srvstate == VCHIQ_SRVSTATE_OPENING) { ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) { ++ pservice = &state->services[i]; ++ break; ++ } ++ } ++ } else { ++ for (i = (state->unused_service - 1); i >= 0; i--) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) ++ pservice = &state->services[i]; ++ else if ((srv->public_fourcc == params->fourcc) ++ && ((srv->instance != instance) || ++ (srv->base.callback != ++ params->callback))) { ++ /* There is another server using this ++ ** fourcc which doesn't match. */ ++ pservice = NULL; ++ break; ++ } ++ } ++ } ++ ++ if (pservice) { ++ service->localport = (pservice - state->services); ++ if (!handle_seq) ++ handle_seq = VCHIQ_MAX_STATES * ++ VCHIQ_MAX_SERVICES; ++ service->handle = handle_seq | ++ (state->id * VCHIQ_MAX_SERVICES) | ++ service->localport; ++ handle_seq += VCHIQ_MAX_STATES * VCHIQ_MAX_SERVICES; ++ *pservice = service; ++ if (pservice == &state->services[state->unused_service]) ++ state->unused_service++; ++ } ++ ++ mutex_unlock(&state->mutex); ++ ++ if (!pservice) { ++ kfree(service); ++ service = NULL; ++ } ++ } ++ ++ if (service) { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[service->localport]; ++ service_quota->slot_quota = state->default_slot_quota; ++ service_quota->message_quota = state->default_message_quota; ++ if (service_quota->slot_use_count == 0) ++ service_quota->previous_tx_index = ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) ++ - 1; ++ ++ /* Bring this service online */ ++ vchiq_set_service_state(service, srvstate); ++ ++ vchiq_log_info(vchiq_core_msg_log_level, ++ "%s Service %c%c%c%c SrcPort:%d", ++ (srvstate == VCHIQ_SRVSTATE_OPENING) ++ ? "Open" : "Add", ++ VCHIQ_FOURCC_AS_4CHARS(params->fourcc), ++ service->localport); ++ } ++ ++ /* Don't unlock the service - leave it with a ref_count of 1. */ ++ ++ return service; ++} ++ ++VCHIQ_STATUS_T ++vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id) ++{ ++ struct vchiq_open_payload payload = { ++ service->base.fourcc, ++ client_id, ++ service->version, ++ service->version_min ++ }; ++ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) }; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ service->client_id = client_id; ++ vchiq_use_service_internal(service); ++ status = queue_message(service->state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), ++ &body, 1, sizeof(payload), QMFLAGS_IS_BLOCKING); ++ if (status == VCHIQ_SUCCESS) { ++ /* Wait for the ACK/NAK */ ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ vchiq_release_service_internal(service); ++ } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) && ++ (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) { ++ if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: osi - srvstate = %s (ref %d)", ++ service->state->id, ++ srvstate_names[service->srvstate], ++ service->ref_count); ++ status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ vchiq_release_service_internal(service); ++ } ++ } ++ return status; ++} ++ ++static void ++release_service_messages(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ int slot_last = state->remote->slot_last; ++ int i; ++ ++ /* Release any claimed messages aimed at this service */ ++ ++ if (service->sync) { ++ VCHIQ_HEADER_T *header = ++ (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, ++ state->remote->slot_sync); ++ if (VCHIQ_MSG_DSTPORT(header->msgid) == service->localport) ++ release_message_sync(state, header); ++ ++ return; ++ } ++ ++ for (i = state->remote->slot_first; i <= slot_last; i++) { ++ VCHIQ_SLOT_INFO_T *slot_info = ++ SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info->release_count != slot_info->use_count) { ++ char *data = ++ (char *)SLOT_DATA_FROM_INDEX(state, i); ++ unsigned int pos, end; ++ ++ end = VCHIQ_SLOT_SIZE; ++ if (data == state->rx_data) ++ /* This buffer is still being read from - stop ++ ** at the current read position */ ++ end = state->rx_pos & VCHIQ_SLOT_MASK; ++ ++ pos = 0; ++ ++ while (pos < end) { ++ VCHIQ_HEADER_T *header = ++ (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ int port = VCHIQ_MSG_DSTPORT(msgid); ++ if ((port == service->localport) && ++ (msgid & VCHIQ_MSGID_CLAIMED)) { ++ vchiq_log_info(vchiq_core_log_level, ++ " fsi - hdr %x", ++ (unsigned int)header); ++ release_slot(state, slot_info, header, ++ NULL); ++ } ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "fsi - pos %x: header %x, " ++ "msgid %x, header->msgid %x, " ++ "header->size %x", ++ pos, (unsigned int)header, ++ msgid, header->msgid, ++ header->size); ++ WARN(1, "invalid slot position\n"); ++ } ++ } ++ } ++ } ++} ++ ++static int ++do_abort_bulks(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATUS_T status; ++ ++ /* Abort any outstanding bulk transfers */ ++ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) ++ return 0; ++ abort_outstanding_bulks(service, &service->bulk_tx); ++ abort_outstanding_bulks(service, &service->bulk_rx); ++ mutex_unlock(&service->bulk_mutex); ++ ++ status = notify_bulks(service, &service->bulk_tx, 0/*!retry_poll*/); ++ if (status == VCHIQ_SUCCESS) ++ status = notify_bulks(service, &service->bulk_rx, ++ 0/*!retry_poll*/); ++ return (status == VCHIQ_SUCCESS); ++} ++ ++static VCHIQ_STATUS_T ++close_service_complete(VCHIQ_SERVICE_T *service, int failstate) ++{ ++ VCHIQ_STATUS_T status; ++ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); ++ int newstate; ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPEN: ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ case VCHIQ_SRVSTATE_CLOSERECVD: ++ if (is_server) { ++ if (service->auto_close) { ++ service->client_id = 0; ++ service->remoteport = VCHIQ_PORT_FREE; ++ newstate = VCHIQ_SRVSTATE_LISTENING; ++ } else ++ newstate = VCHIQ_SRVSTATE_CLOSEWAIT; ++ } else ++ newstate = VCHIQ_SRVSTATE_CLOSED; ++ vchiq_set_service_state(service, newstate); ++ break; ++ case VCHIQ_SRVSTATE_LISTENING: ++ break; ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "close_service_complete(%x) called in state %s", ++ service->handle, srvstate_names[service->srvstate]); ++ WARN(1, "close_service_complete in unexpected state\n"); ++ return VCHIQ_ERROR; ++ } ++ ++ status = make_service_callback(service, ++ VCHIQ_SERVICE_CLOSED, NULL, NULL); ++ ++ if (status != VCHIQ_RETRY) { ++ int uc = service->service_use_count; ++ int i; ++ /* Complete the close process */ ++ for (i = 0; i < uc; i++) ++ /* cater for cases where close is forced and the ++ ** client may not close all it's handles */ ++ vchiq_release_service_internal(service); ++ ++ service->client_id = 0; ++ service->remoteport = VCHIQ_PORT_FREE; ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSED) ++ vchiq_free_service_internal(service); ++ else if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) { ++ if (is_server) ++ service->closing = 0; ++ ++ up(&service->remove_event); ++ } ++ } else ++ vchiq_set_service_state(service, failstate); ++ ++ return status; ++} ++ ++/* Called by the slot handler */ ++VCHIQ_STATUS_T ++vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); ++ ++ vchiq_log_info(vchiq_core_log_level, "%d: csi:%d,%d (%s)", ++ service->state->id, service->localport, close_recvd, ++ srvstate_names[service->srvstate]); ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_CLOSED: ++ case VCHIQ_SRVSTATE_HIDDEN: ++ case VCHIQ_SRVSTATE_LISTENING: ++ case VCHIQ_SRVSTATE_CLOSEWAIT: ++ if (close_recvd) ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_close_service_internal(1) called " ++ "in state %s", ++ srvstate_names[service->srvstate]); ++ else if (is_server) { ++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { ++ status = VCHIQ_ERROR; ++ } else { ++ service->client_id = 0; ++ service->remoteport = VCHIQ_PORT_FREE; ++ if (service->srvstate == ++ VCHIQ_SRVSTATE_CLOSEWAIT) ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ } ++ up(&service->remove_event); ++ } else ++ vchiq_free_service_internal(service); ++ break; ++ case VCHIQ_SRVSTATE_OPENING: ++ if (close_recvd) { ++ /* The open was rejected - tell the user */ ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_CLOSEWAIT); ++ up(&service->remove_event); ++ } else { ++ /* Shutdown mid-open - let the other side know */ ++ status = queue_message(state, service, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, 0); ++ } ++ break; ++ ++ case VCHIQ_SRVSTATE_OPENSYNC: ++ mutex_lock(&state->sync_mutex); ++ /* Drop through */ ++ ++ case VCHIQ_SRVSTATE_OPEN: ++ if (state->is_master || close_recvd) { ++ if (!do_abort_bulks(service)) ++ status = VCHIQ_RETRY; ++ } ++ ++ release_service_messages(service); ++ ++ if (status == VCHIQ_SUCCESS) ++ status = queue_message(state, service, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK); ++ ++ if (status == VCHIQ_SUCCESS) { ++ if (!close_recvd) { ++ /* Change the state while the mutex is ++ still held */ ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_CLOSESENT); ++ mutex_unlock(&state->slot_mutex); ++ if (service->sync) ++ mutex_unlock(&state->sync_mutex); ++ break; ++ } ++ } else if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) { ++ mutex_unlock(&state->sync_mutex); ++ break; ++ } else ++ break; ++ ++ /* Change the state while the mutex is still held */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSERECVD); ++ mutex_unlock(&state->slot_mutex); ++ if (service->sync) ++ mutex_unlock(&state->sync_mutex); ++ ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ if (!close_recvd) ++ /* This happens when a process is killed mid-close */ ++ break; ++ ++ if (!state->is_master) { ++ if (!do_abort_bulks(service)) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSERECVD: ++ if (!close_recvd && is_server) ++ /* Force into LISTENING mode */ ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_close_service_internal(%d) called in state %s", ++ close_recvd, srvstate_names[service->srvstate]); ++ break; ++ } ++ ++ return status; ++} ++ ++/* Called from the application process upon process death */ ++void ++vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ ++ vchiq_log_info(vchiq_core_log_level, "%d: tsi - (%d<->%d)", ++ state->id, service->localport, service->remoteport); ++ ++ mark_service_closing(service); ++ ++ /* Mark the service for removal by the slot handler */ ++ request_poll(state, service, VCHIQ_POLL_REMOVE); ++} ++ ++/* Called from the slot handler */ ++void ++vchiq_free_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ ++ vchiq_log_info(vchiq_core_log_level, "%d: fsi - (%d)", ++ state->id, service->localport); ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPENING: ++ case VCHIQ_SRVSTATE_CLOSED: ++ case VCHIQ_SRVSTATE_HIDDEN: ++ case VCHIQ_SRVSTATE_LISTENING: ++ case VCHIQ_SRVSTATE_CLOSEWAIT: ++ break; ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: fsi - (%d) in state %s", ++ state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ return; ++ } ++ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE); ++ ++ up(&service->remove_event); ++ ++ /* Release the initial lock */ ++ unlock_service(service); ++} ++ ++VCHIQ_STATUS_T ++vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T *service; ++ int i; ++ ++ /* Find all services registered to this client and enable them. */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ unlock_service(service); ++ } ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0, ++ 0, QMFLAGS_IS_BLOCKING) == VCHIQ_RETRY) ++ return VCHIQ_RETRY; ++ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING); ++ } ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) { ++ if (down_interruptible(&state->connect) != 0) ++ return VCHIQ_RETRY; ++ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ up(&state->connect); ++ } ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T *service; ++ int i; ++ ++ /* Find all services registered to this client and enable them. */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ (void)vchiq_remove_service(service->handle); ++ unlock_service(service); ++ } ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_pause_internal(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ switch (state->conn_state) { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Request a pause */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING); ++ request_poll(state, NULL, 0); ++ break; ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_pause_internal in state %s\n", ++ conn_state_names[state->conn_state]); ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ break; ++ } ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_resume_internal(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING); ++ request_poll(state, NULL, 0); ++ } else { ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ } ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (!service) ++ return VCHIQ_ERROR; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: close_service:%d", ++ service->state->id, service->localport); ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)) { ++ unlock_service(service); ++ return VCHIQ_ERROR; ++ } ++ ++ mark_service_closing(service); ++ ++ if (current == service->state->slot_handler_thread) { ++ status = vchiq_close_service_internal(service, ++ 0/*!close_recvd*/); ++ BUG_ON(status == VCHIQ_RETRY); ++ } else { ++ /* Mark the service for termination by the slot handler */ ++ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); ++ } ++ ++ while (1) { ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ (service->srvstate == VCHIQ_SRVSTATE_OPEN)) ++ break; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: close_service:%d - waiting in state %s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && ++ (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ status = VCHIQ_ERROR; ++ ++ unlock_service(service); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (!service) ++ return VCHIQ_ERROR; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: remove_service:%d", ++ service->state->id, service->localport); ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_FREE) { ++ unlock_service(service); ++ return VCHIQ_ERROR; ++ } ++ ++ mark_service_closing(service); ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) || ++ (current == service->state->slot_handler_thread)) { ++ /* Make it look like a client, because it must be removed and ++ not left in the LISTENING state. */ ++ service->public_fourcc = VCHIQ_FOURCC_INVALID; ++ ++ status = vchiq_close_service_internal(service, ++ 0/*!close_recvd*/); ++ BUG_ON(status == VCHIQ_RETRY); ++ } else { ++ /* Mark the service for removal by the slot handler */ ++ request_poll(service->state, service, VCHIQ_POLL_REMOVE); ++ } ++ while (1) { ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_OPEN)) ++ break; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: remove_service:%d - waiting in state %s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && ++ (service->srvstate != VCHIQ_SRVSTATE_FREE)) ++ status = VCHIQ_ERROR; ++ ++ unlock_service(service); ++ ++ return status; ++} ++ ++ ++/* This function may be called by kernel threads or user threads. ++ * User threads may receive VCHIQ_RETRY to indicate that a signal has been ++ * received and the call should be retried after being returned to user ++ * context. ++ * When called in blocking mode, the userdata field points to a bulk_waiter ++ * structure. ++ */ ++VCHIQ_STATUS_T ++vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_BULK_QUEUE_T *queue; ++ VCHIQ_BULK_T *bulk; ++ VCHIQ_STATE_T *state; ++ struct bulk_waiter *bulk_waiter = NULL; ++ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; ++ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (!service || ++ (service->srvstate != VCHIQ_SRVSTATE_OPEN) || ++ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) ++ goto error_exit; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ bulk_waiter = (struct bulk_waiter *)userdata; ++ sema_init(&bulk_waiter->event, 0); ++ bulk_waiter->actual = 0; ++ bulk_waiter->bulk = NULL; ++ break; ++ case VCHIQ_BULK_MODE_WAITING: ++ bulk_waiter = (struct bulk_waiter *)userdata; ++ bulk = bulk_waiter->bulk; ++ goto waiting; ++ default: ++ goto error_exit; ++ } ++ ++ state = service->state; ++ ++ queue = (dir == VCHIQ_BULK_TRANSMIT) ? ++ &service->bulk_tx : &service->bulk_rx; ++ ++ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ ++ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls); ++ do { ++ mutex_unlock(&service->bulk_mutex); ++ if (down_interruptible(&service->bulk_remove_event) ++ != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ if (mutex_lock_interruptible(&service->bulk_mutex) ++ != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ } while (queue->local_insert == queue->remove + ++ VCHIQ_NUM_SERVICE_BULKS); ++ } ++ ++ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)]; ++ ++ bulk->mode = mode; ++ bulk->dir = dir; ++ bulk->userdata = userdata; ++ bulk->size = size; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ ++ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) != ++ VCHIQ_SUCCESS) ++ goto unlock_error_exit; ++ ++ wmb(); ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: bt (%d->%d) %cx %x@%x %x", ++ state->id, ++ service->localport, service->remoteport, dir_char, ++ size, (unsigned int)bulk->data, (unsigned int)userdata); ++ ++ /* The slot mutex must be held when the service is being closed, so ++ claim it here to ensure that isn't happening */ ++ if (mutex_lock_interruptible(&state->slot_mutex) != 0) { ++ status = VCHIQ_RETRY; ++ goto cancel_bulk_error_exit; ++ } ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) ++ goto unlock_both_error_exit; ++ ++ if (state->is_master) { ++ queue->local_insert++; ++ if (resolve_bulks(service, queue)) ++ request_poll(state, service, ++ (dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ } else { ++ int payload[2] = { (int)bulk->data, bulk->size }; ++ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) }; ++ ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(dir_msgtype, ++ service->localport, service->remoteport), ++ &element, 1, sizeof(payload), ++ QMFLAGS_IS_BLOCKING | ++ QMFLAGS_NO_MUTEX_LOCK | ++ QMFLAGS_NO_MUTEX_UNLOCK); ++ if (status != VCHIQ_SUCCESS) { ++ goto unlock_both_error_exit; ++ } ++ queue->local_insert++; ++ } ++ ++ mutex_unlock(&state->slot_mutex); ++ mutex_unlock(&service->bulk_mutex); ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: bt:%d %cx li=%x ri=%x p=%x", ++ state->id, ++ service->localport, dir_char, ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++waiting: ++ unlock_service(service); ++ ++ status = VCHIQ_SUCCESS; ++ ++ if (bulk_waiter) { ++ bulk_waiter->bulk = bulk; ++ if (down_interruptible(&bulk_waiter->event) != 0) ++ status = VCHIQ_RETRY; ++ else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED) ++ status = VCHIQ_ERROR; ++ } ++ ++ return status; ++ ++unlock_both_error_exit: ++ mutex_unlock(&state->slot_mutex); ++cancel_bulk_error_exit: ++ vchiq_complete_bulk(bulk); ++unlock_error_exit: ++ mutex_unlock(&service->bulk_mutex); ++ ++error_exit: ++ if (service) ++ unlock_service(service); ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, ++ const VCHIQ_ELEMENT_T *elements, unsigned int count) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ unsigned int size = 0; ++ unsigned int i; ++ ++ if (!service || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) ++ goto error_exit; ++ ++ for (i = 0; i < (unsigned int)count; i++) { ++ if (elements[i].size) { ++ if (elements[i].data == NULL) { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ goto error_exit; ++ } ++ size += elements[i].size; ++ } ++ } ++ ++ if (size > VCHIQ_MAX_MSG_SIZE) { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ goto error_exit; ++ } ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPEN: ++ status = queue_message(service->state, service, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, ++ service->localport, ++ service->remoteport), ++ elements, count, size, 1); ++ break; ++ case VCHIQ_SRVSTATE_OPENSYNC: ++ status = queue_message_sync(service->state, service, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, ++ service->localport, ++ service->remoteport), ++ elements, count, size, 1); ++ break; ++ default: ++ status = VCHIQ_ERROR; ++ break; ++ } ++ ++error_exit: ++ if (service) ++ unlock_service(service); ++ ++ return status; ++} ++ ++void ++vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_STATE_T *state; ++ int slot_index; ++ ++ if (!service) ++ return; ++ ++ state = service->state; ++ remote = state->remote; ++ ++ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header); ++ ++ if ((slot_index >= remote->slot_first) && ++ (slot_index <= remote->slot_last)) { ++ int msgid = header->msgid; ++ if (msgid & VCHIQ_MSGID_CLAIMED) { ++ VCHIQ_SLOT_INFO_T *slot_info = ++ SLOT_INFO_FROM_INDEX(state, slot_index); ++ ++ release_slot(state, slot_info, header, service); ++ } ++ } else if (slot_index == remote->slot_sync) ++ release_message_sync(state, header); ++ ++ unlock_service(service); ++} ++ ++static void ++release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) ++{ ++ header->msgid = VCHIQ_MSGID_PADDING; ++ wmb(); ++ remote_event_signal(&state->remote->sync_release); ++} ++ ++VCHIQ_STATUS_T ++vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, short *peer_version) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ ++ if (!service || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS) || ++ !peer_version) ++ goto exit; ++ *peer_version = service->peer_version; ++ status = VCHIQ_SUCCESS; ++ ++exit: ++ if (service) ++ unlock_service(service); ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_get_config(VCHIQ_INSTANCE_T instance, ++ int config_size, VCHIQ_CONFIG_T *pconfig) ++{ ++ VCHIQ_CONFIG_T config; ++ ++ (void)instance; ++ ++ config.max_msg_size = VCHIQ_MAX_MSG_SIZE; ++ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE; ++ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS; ++ config.max_services = VCHIQ_MAX_SERVICES; ++ config.version = VCHIQ_VERSION; ++ config.version_min = VCHIQ_VERSION_MIN; ++ ++ if (config_size > sizeof(VCHIQ_CONFIG_T)) ++ return VCHIQ_ERROR; ++ ++ memcpy(pconfig, &config, ++ min(config_size, (int)(sizeof(VCHIQ_CONFIG_T)))); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHIQ_SERVICE_OPTION_T option, int value) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (service) { ++ switch (option) { ++ case VCHIQ_SERVICE_OPTION_AUTOCLOSE: ++ service->auto_close = value; ++ status = VCHIQ_SUCCESS; ++ break; ++ ++ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[ ++ service->localport]; ++ if (value == 0) ++ value = service->state->default_slot_quota; ++ if ((value >= service_quota->slot_use_count) && ++ (value < (unsigned short)~0)) { ++ service_quota->slot_quota = value; ++ if ((value >= service_quota->slot_use_count) && ++ (service_quota->message_quota >= ++ service_quota->message_use_count)) { ++ /* Signal the service that it may have ++ ** dropped below its quota */ ++ up(&service_quota->quota_event); ++ } ++ status = VCHIQ_SUCCESS; ++ } ++ } break; ++ ++ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[ ++ service->localport]; ++ if (value == 0) ++ value = service->state->default_message_quota; ++ if ((value >= service_quota->message_use_count) && ++ (value < (unsigned short)~0)) { ++ service_quota->message_quota = value; ++ if ((value >= ++ service_quota->message_use_count) && ++ (service_quota->slot_quota >= ++ service_quota->slot_use_count)) ++ /* Signal the service that it may have ++ ** dropped below its quota */ ++ up(&service_quota->quota_event); ++ status = VCHIQ_SUCCESS; ++ } ++ } break; ++ ++ case VCHIQ_SERVICE_OPTION_SYNCHRONOUS: ++ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) || ++ (service->srvstate == ++ VCHIQ_SRVSTATE_LISTENING)) { ++ service->sync = value; ++ status = VCHIQ_SUCCESS; ++ } ++ break; ++ ++ case VCHIQ_SERVICE_OPTION_TRACE: ++ service->trace = value; ++ status = VCHIQ_SUCCESS; ++ break; ++ ++ default: ++ break; ++ } ++ unlock_service(service); ++ } ++ ++ return status; ++} ++ ++void ++vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state, ++ VCHIQ_SHARED_STATE_T *shared, const char *label) ++{ ++ static const char *const debug_names[] = { ++ "", ++ "SLOT_HANDLER_COUNT", ++ "SLOT_HANDLER_LINE", ++ "PARSE_LINE", ++ "PARSE_HEADER", ++ "PARSE_MSGID", ++ "AWAIT_COMPLETION_LINE", ++ "DEQUEUE_MESSAGE_LINE", ++ "SERVICE_CALLBACK_LINE", ++ "MSG_QUEUE_FULL_COUNT", ++ "COMPLETION_QUEUE_FULL_COUNT" ++ }; ++ int i; ++ ++ char buf[80]; ++ int len; ++ len = snprintf(buf, sizeof(buf), ++ " %s: slots %d-%d tx_pos=%x recycle=%x", ++ label, shared->slot_first, shared->slot_last, ++ shared->tx_pos, shared->slot_queue_recycle); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Slots claimed:"); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ for (i = shared->slot_first; i <= shared->slot_last; i++) { ++ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info.use_count != slot_info.release_count) { ++ len = snprintf(buf, sizeof(buf), ++ " %d: %d/%d", i, slot_info.use_count, ++ slot_info.release_count); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ } ++ ++ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) { ++ len = snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)", ++ debug_names[i], shared->debug[i], shared->debug[i]); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++} ++ ++void ++vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state) ++{ ++ char buf[80]; ++ int len; ++ int i; ++ ++ len = snprintf(buf, sizeof(buf), "State %d: %s", state->id, ++ conn_state_names[state->conn_state]); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " tx_pos=%x(@%x), rx_pos=%x(@%x)", ++ state->local->tx_pos, ++ (uint32_t)state->tx_data + ++ (state->local_tx_pos & VCHIQ_SLOT_MASK), ++ state->rx_pos, ++ (uint32_t)state->rx_data + ++ (state->rx_pos & VCHIQ_SLOT_MASK)); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Version: %d (min %d)", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ if (VCHIQ_ENABLE_STATS) { ++ len = snprintf(buf, sizeof(buf), ++ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, " ++ "error_count=%d", ++ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count, ++ state->stats.error_count); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ ++ len = snprintf(buf, sizeof(buf), ++ " Slots: %d available (%d data), %d recyclable, %d stalls " ++ "(%d data)", ++ ((state->slot_queue_available * VCHIQ_SLOT_SIZE) - ++ state->local_tx_pos) / VCHIQ_SLOT_SIZE, ++ state->data_quota - state->data_use_count, ++ state->local->slot_queue_recycle - state->slot_queue_available, ++ state->stats.slot_stalls, state->stats.data_stalls); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ vchiq_dump_platform_state(dump_context); ++ ++ vchiq_dump_shared_state(dump_context, state, state->local, "Local"); ++ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote"); ++ ++ vchiq_dump_platform_instances(dump_context); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = find_service_by_port(state, i); ++ ++ if (service) { ++ vchiq_dump_service_state(dump_context, service); ++ unlock_service(service); ++ } ++ } ++} ++ ++void ++vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service) ++{ ++ char buf[80]; ++ int len; ++ ++ len = snprintf(buf, sizeof(buf), "Service %d: %s (ref %u)", ++ service->localport, srvstate_names[service->srvstate], ++ service->ref_count - 1); /*Don't include the lock just taken*/ ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) { ++ char remoteport[30]; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ int fourcc = service->base.fourcc; ++ int tx_pending, rx_pending; ++ if (service->remoteport != VCHIQ_PORT_FREE) { ++ int len2 = snprintf(remoteport, sizeof(remoteport), ++ "%d", service->remoteport); ++ if (service->public_fourcc != VCHIQ_FOURCC_INVALID) ++ snprintf(remoteport + len2, ++ sizeof(remoteport) - len2, ++ " (client %x)", service->client_id); ++ } else ++ strcpy(remoteport, "n/a"); ++ ++ len += snprintf(buf + len, sizeof(buf) - len, ++ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)", ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ remoteport, ++ service_quota->message_use_count, ++ service_quota->message_quota, ++ service_quota->slot_use_count, ++ service_quota->slot_quota); ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ tx_pending = service->bulk_tx.local_insert - ++ service->bulk_tx.remote_insert; ++ ++ rx_pending = service->bulk_rx.local_insert - ++ service->bulk_rx.remote_insert; ++ ++ len = snprintf(buf, sizeof(buf), ++ " Bulk: tx_pending=%d (size %d)," ++ " rx_pending=%d (size %d)", ++ tx_pending, ++ tx_pending ? service->bulk_tx.bulks[ ++ BULK_INDEX(service->bulk_tx.remove)].size : 0, ++ rx_pending, ++ rx_pending ? service->bulk_rx.bulks[ ++ BULK_INDEX(service->bulk_rx.remove)].size : 0); ++ ++ if (VCHIQ_ENABLE_STATS) { ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Ctrl: tx_count=%d, tx_bytes=%llu, " ++ "rx_count=%d, rx_bytes=%llu", ++ service->stats.ctrl_tx_count, ++ service->stats.ctrl_tx_bytes, ++ service->stats.ctrl_rx_count, ++ service->stats.ctrl_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Bulk: tx_count=%d, tx_bytes=%llu, " ++ "rx_count=%d, rx_bytes=%llu", ++ service->stats.bulk_tx_count, ++ service->stats.bulk_tx_bytes, ++ service->stats.bulk_rx_count, ++ service->stats.bulk_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " %d quota stalls, %d slot stalls, " ++ "%d bulk stalls, %d aborted, %d errors", ++ service->stats.quota_stalls, ++ service->stats.slot_stalls, ++ service->stats.bulk_stalls, ++ service->stats.bulk_aborted_count, ++ service->stats.error_count); ++ } ++ } ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) ++ vchiq_dump_platform_service_state(dump_context, service); ++} ++ ++ ++void ++vchiq_loud_error_header(void) ++{ ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, "====="); ++} ++ ++void ++vchiq_loud_error_footer(void) ++{ ++ vchiq_log_error(vchiq_core_log_level, "====="); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++} ++ ++ ++VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++void vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, ++ size_t numBytes) ++{ ++ const uint8_t *mem = (const uint8_t *)voidMem; ++ size_t offset; ++ char lineBuf[100]; ++ char *s; ++ ++ while (numBytes > 0) { ++ s = lineBuf; ++ ++ for (offset = 0; offset < 16; offset++) { ++ if (offset < numBytes) ++ s += snprintf(s, 4, "%02x ", mem[offset]); ++ else ++ s += snprintf(s, 4, " "); ++ } ++ ++ for (offset = 0; offset < 16; offset++) { ++ if (offset < numBytes) { ++ uint8_t ch = mem[offset]; ++ ++ if ((ch < ' ') || (ch > '~')) ++ ch = '.'; ++ *s++ = (char)ch; ++ } ++ } ++ *s++ = '\0'; ++ ++ if ((label != NULL) && (*label != '\0')) ++ vchiq_log_trace(VCHIQ_LOG_TRACE, ++ "%s: %08x: %s", label, addr, lineBuf); ++ else ++ vchiq_log_trace(VCHIQ_LOG_TRACE, ++ "%08x: %s", addr, lineBuf); ++ ++ addr += 16; ++ mem += 16; ++ if (numBytes > 16) ++ numBytes -= 16; ++ else ++ numBytes = 0; ++ } ++} +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h +@@ -0,0 +1,712 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_CORE_H ++#define VCHIQ_CORE_H ++ ++#include ++#include ++#include ++ ++#include "vchiq_cfg.h" ++ ++#include "vchiq.h" ++ ++/* Run time control of log level, based on KERN_XXX level. */ ++#define VCHIQ_LOG_DEFAULT 4 ++#define VCHIQ_LOG_ERROR 3 ++#define VCHIQ_LOG_WARNING 4 ++#define VCHIQ_LOG_INFO 6 ++#define VCHIQ_LOG_TRACE 7 ++ ++#define VCHIQ_LOG_PREFIX KERN_INFO "vchiq: " ++ ++#ifndef vchiq_log_error ++#define vchiq_log_error(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_ERROR) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_warning ++#define vchiq_log_warning(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_WARNING) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_info ++#define vchiq_log_info(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_INFO) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_trace ++#define vchiq_log_trace(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_TRACE) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++ ++#define vchiq_loud_error(...) \ ++ vchiq_log_error(vchiq_core_log_level, "===== " __VA_ARGS__) ++ ++#ifndef vchiq_static_assert ++#define vchiq_static_assert(cond) __attribute__((unused)) \ ++ extern int vchiq_static_assert[(cond) ? 1 : -1] ++#endif ++ ++#define IS_POW2(x) (x && ((x & (x - 1)) == 0)) ++ ++/* Ensure that the slot size and maximum number of slots are powers of 2 */ ++vchiq_static_assert(IS_POW2(VCHIQ_SLOT_SIZE)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE)); ++ ++#define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1) ++#define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1) ++#define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \ ++ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE) ++ ++#define VCHIQ_MSG_PADDING 0 /* - */ ++#define VCHIQ_MSG_CONNECT 1 /* - */ ++#define VCHIQ_MSG_OPEN 2 /* + (srcport, -), fourcc, client_id */ ++#define VCHIQ_MSG_OPENACK 3 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_CLOSE 4 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_DATA 5 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_BULK_RX 6 /* + (srcport, dstport), data, size */ ++#define VCHIQ_MSG_BULK_TX 7 /* + (srcport, dstport), data, size */ ++#define VCHIQ_MSG_BULK_RX_DONE 8 /* + (srcport, dstport), actual */ ++#define VCHIQ_MSG_BULK_TX_DONE 9 /* + (srcport, dstport), actual */ ++#define VCHIQ_MSG_PAUSE 10 /* - */ ++#define VCHIQ_MSG_RESUME 11 /* - */ ++#define VCHIQ_MSG_REMOTE_USE 12 /* - */ ++#define VCHIQ_MSG_REMOTE_RELEASE 13 /* - */ ++#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 /* - */ ++ ++#define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1) ++#define VCHIQ_PORT_FREE 0x1000 ++#define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE) ++#define VCHIQ_MAKE_MSG(type, srcport, dstport) \ ++ ((type<<24) | (srcport<<12) | (dstport<<0)) ++#define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24) ++#define VCHIQ_MSG_SRCPORT(msgid) \ ++ (unsigned short)(((unsigned int)msgid >> 12) & 0xfff) ++#define VCHIQ_MSG_DSTPORT(msgid) \ ++ ((unsigned short)msgid & 0xfff) ++ ++#define VCHIQ_FOURCC_AS_4CHARS(fourcc) \ ++ ((fourcc) >> 24) & 0xff, \ ++ ((fourcc) >> 16) & 0xff, \ ++ ((fourcc) >> 8) & 0xff, \ ++ (fourcc) & 0xff ++ ++/* Ensure the fields are wide enough */ ++vchiq_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0, 0, VCHIQ_PORT_MAX)) ++ == 0); ++vchiq_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0, VCHIQ_PORT_MAX, 0)) == 0); ++vchiq_static_assert((unsigned int)VCHIQ_PORT_MAX < ++ (unsigned int)VCHIQ_PORT_FREE); ++ ++#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING, 0, 0) ++#define VCHIQ_MSGID_CLAIMED 0x40000000 ++ ++#define VCHIQ_FOURCC_INVALID 0x00000000 ++#define VCHIQ_FOURCC_IS_LEGAL(fourcc) (fourcc != VCHIQ_FOURCC_INVALID) ++ ++#define VCHIQ_BULK_ACTUAL_ABORTED -1 ++ ++typedef uint32_t BITSET_T; ++ ++vchiq_static_assert((sizeof(BITSET_T) * 8) == 32); ++ ++#define BITSET_SIZE(b) ((b + 31) >> 5) ++#define BITSET_WORD(b) (b >> 5) ++#define BITSET_BIT(b) (1 << (b & 31)) ++#define BITSET_ZERO(bs) memset(bs, 0, sizeof(bs)) ++#define BITSET_IS_SET(bs, b) (bs[BITSET_WORD(b)] & BITSET_BIT(b)) ++#define BITSET_SET(bs, b) (bs[BITSET_WORD(b)] |= BITSET_BIT(b)) ++#define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b)) ++ ++#if VCHIQ_ENABLE_STATS ++#define VCHIQ_STATS_INC(state, stat) (state->stats. stat++) ++#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat++) ++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) \ ++ (service->stats. stat += addend) ++#else ++#define VCHIQ_STATS_INC(state, stat) ((void)0) ++#define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0) ++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0) ++#endif ++ ++enum { ++ DEBUG_ENTRIES, ++#if VCHIQ_ENABLE_DEBUG ++ DEBUG_SLOT_HANDLER_COUNT, ++ DEBUG_SLOT_HANDLER_LINE, ++ DEBUG_PARSE_LINE, ++ DEBUG_PARSE_HEADER, ++ DEBUG_PARSE_MSGID, ++ DEBUG_AWAIT_COMPLETION_LINE, ++ DEBUG_DEQUEUE_MESSAGE_LINE, ++ DEBUG_SERVICE_CALLBACK_LINE, ++ DEBUG_MSG_QUEUE_FULL_COUNT, ++ DEBUG_COMPLETION_QUEUE_FULL_COUNT, ++#endif ++ DEBUG_MAX ++}; ++ ++#if VCHIQ_ENABLE_DEBUG ++ ++#define DEBUG_INITIALISE(local) int *debug_ptr = (local)->debug; ++#define DEBUG_TRACE(d) \ ++ do { debug_ptr[DEBUG_ ## d] = __LINE__; dsb(); } while (0) ++#define DEBUG_VALUE(d, v) \ ++ do { debug_ptr[DEBUG_ ## d] = (v); dsb(); } while (0) ++#define DEBUG_COUNT(d) \ ++ do { debug_ptr[DEBUG_ ## d]++; dsb(); } while (0) ++ ++#else /* VCHIQ_ENABLE_DEBUG */ ++ ++#define DEBUG_INITIALISE(local) ++#define DEBUG_TRACE(d) ++#define DEBUG_VALUE(d, v) ++#define DEBUG_COUNT(d) ++ ++#endif /* VCHIQ_ENABLE_DEBUG */ ++ ++typedef enum { ++ VCHIQ_CONNSTATE_DISCONNECTED, ++ VCHIQ_CONNSTATE_CONNECTING, ++ VCHIQ_CONNSTATE_CONNECTED, ++ VCHIQ_CONNSTATE_PAUSING, ++ VCHIQ_CONNSTATE_PAUSE_SENT, ++ VCHIQ_CONNSTATE_PAUSED, ++ VCHIQ_CONNSTATE_RESUMING, ++ VCHIQ_CONNSTATE_PAUSE_TIMEOUT, ++ VCHIQ_CONNSTATE_RESUME_TIMEOUT ++} VCHIQ_CONNSTATE_T; ++ ++enum { ++ VCHIQ_SRVSTATE_FREE, ++ VCHIQ_SRVSTATE_HIDDEN, ++ VCHIQ_SRVSTATE_LISTENING, ++ VCHIQ_SRVSTATE_OPENING, ++ VCHIQ_SRVSTATE_OPEN, ++ VCHIQ_SRVSTATE_OPENSYNC, ++ VCHIQ_SRVSTATE_CLOSESENT, ++ VCHIQ_SRVSTATE_CLOSERECVD, ++ VCHIQ_SRVSTATE_CLOSEWAIT, ++ VCHIQ_SRVSTATE_CLOSED ++}; ++ ++enum { ++ VCHIQ_POLL_TERMINATE, ++ VCHIQ_POLL_REMOVE, ++ VCHIQ_POLL_TXNOTIFY, ++ VCHIQ_POLL_RXNOTIFY, ++ VCHIQ_POLL_COUNT ++}; ++ ++typedef enum { ++ VCHIQ_BULK_TRANSMIT, ++ VCHIQ_BULK_RECEIVE ++} VCHIQ_BULK_DIR_T; ++ ++typedef void (*VCHIQ_USERDATA_TERM_T)(void *userdata); ++ ++typedef struct vchiq_bulk_struct { ++ short mode; ++ short dir; ++ void *userdata; ++ VCHI_MEM_HANDLE_T handle; ++ void *data; ++ int size; ++ void *remote_data; ++ int remote_size; ++ int actual; ++} VCHIQ_BULK_T; ++ ++typedef struct vchiq_bulk_queue_struct { ++ int local_insert; /* Where to insert the next local bulk */ ++ int remote_insert; /* Where to insert the next remote bulk (master) */ ++ int process; /* Bulk to transfer next */ ++ int remote_notify; /* Bulk to notify the remote client of next (mstr) */ ++ int remove; /* Bulk to notify the local client of, and remove, ++ ** next */ ++ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS]; ++} VCHIQ_BULK_QUEUE_T; ++ ++typedef struct remote_event_struct { ++ int armed; ++ int fired; ++ struct semaphore *event; ++} REMOTE_EVENT_T; ++ ++typedef struct opaque_platform_state_t *VCHIQ_PLATFORM_STATE_T; ++ ++typedef struct vchiq_state_struct VCHIQ_STATE_T; ++ ++typedef struct vchiq_slot_struct { ++ char data[VCHIQ_SLOT_SIZE]; ++} VCHIQ_SLOT_T; ++ ++typedef struct vchiq_slot_info_struct { ++ /* Use two counters rather than one to avoid the need for a mutex. */ ++ short use_count; ++ short release_count; ++} VCHIQ_SLOT_INFO_T; ++ ++typedef struct vchiq_service_struct { ++ VCHIQ_SERVICE_BASE_T base; ++ VCHIQ_SERVICE_HANDLE_T handle; ++ unsigned int ref_count; ++ int srvstate; ++ VCHIQ_USERDATA_TERM_T userdata_term; ++ unsigned int localport; ++ unsigned int remoteport; ++ int public_fourcc; ++ int client_id; ++ char auto_close; ++ char sync; ++ char closing; ++ char trace; ++ atomic_t poll_flags; ++ short version; ++ short version_min; ++ short peer_version; ++ ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance; ++ ++ int service_use_count; ++ ++ VCHIQ_BULK_QUEUE_T bulk_tx; ++ VCHIQ_BULK_QUEUE_T bulk_rx; ++ ++ struct semaphore remove_event; ++ struct semaphore bulk_remove_event; ++ struct mutex bulk_mutex; ++ ++ struct service_stats_struct { ++ int quota_stalls; ++ int slot_stalls; ++ int bulk_stalls; ++ int error_count; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int bulk_tx_count; ++ int bulk_rx_count; ++ int bulk_aborted_count; ++ uint64_t ctrl_tx_bytes; ++ uint64_t ctrl_rx_bytes; ++ uint64_t bulk_tx_bytes; ++ uint64_t bulk_rx_bytes; ++ } stats; ++} VCHIQ_SERVICE_T; ++ ++/* The quota information is outside VCHIQ_SERVICE_T so that it can be ++ statically allocated, since for accounting reasons a service's slot ++ usage is carried over between users of the same port number. ++ */ ++typedef struct vchiq_service_quota_struct { ++ unsigned short slot_quota; ++ unsigned short slot_use_count; ++ unsigned short message_quota; ++ unsigned short message_use_count; ++ struct semaphore quota_event; ++ int previous_tx_index; ++} VCHIQ_SERVICE_QUOTA_T; ++ ++typedef struct vchiq_shared_state_struct { ++ ++ /* A non-zero value here indicates that the content is valid. */ ++ int initialised; ++ ++ /* The first and last (inclusive) slots allocated to the owner. */ ++ int slot_first; ++ int slot_last; ++ ++ /* The slot allocated to synchronous messages from the owner. */ ++ int slot_sync; ++ ++ /* Signalling this event indicates that owner's slot handler thread ++ ** should run. */ ++ REMOTE_EVENT_T trigger; ++ ++ /* Indicates the byte position within the stream where the next message ++ ** will be written. The least significant bits are an index into the ++ ** slot. The next bits are the index of the slot in slot_queue. */ ++ int tx_pos; ++ ++ /* This event should be signalled when a slot is recycled. */ ++ REMOTE_EVENT_T recycle; ++ ++ /* The slot_queue index where the next recycled slot will be written. */ ++ int slot_queue_recycle; ++ ++ /* This event should be signalled when a synchronous message is sent. */ ++ REMOTE_EVENT_T sync_trigger; ++ ++ /* This event should be signalled when a synchronous message has been ++ ** released. */ ++ REMOTE_EVENT_T sync_release; ++ ++ /* A circular buffer of slot indexes. */ ++ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE]; ++ ++ /* Debugging state */ ++ int debug[DEBUG_MAX]; ++} VCHIQ_SHARED_STATE_T; ++ ++typedef struct vchiq_slot_zero_struct { ++ int magic; ++ short version; ++ short version_min; ++ int slot_zero_size; ++ int slot_size; ++ int max_slots; ++ int max_slots_per_side; ++ int platform_data[2]; ++ VCHIQ_SHARED_STATE_T master; ++ VCHIQ_SHARED_STATE_T slave; ++ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS]; ++} VCHIQ_SLOT_ZERO_T; ++ ++struct vchiq_state_struct { ++ int id; ++ int initialised; ++ VCHIQ_CONNSTATE_T conn_state; ++ int is_master; ++ short version_common; ++ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_SLOT_T *slot_data; ++ ++ unsigned short default_slot_quota; ++ unsigned short default_message_quota; ++ ++ /* Event indicating connect message received */ ++ struct semaphore connect; ++ ++ /* Mutex protecting services */ ++ struct mutex mutex; ++ VCHIQ_INSTANCE_T *instance; ++ ++ /* Processes incoming messages */ ++ struct task_struct *slot_handler_thread; ++ ++ /* Processes recycled slots */ ++ struct task_struct *recycle_thread; ++ ++ /* Processes synchronous messages */ ++ struct task_struct *sync_thread; ++ ++ /* Local implementation of the trigger remote event */ ++ struct semaphore trigger_event; ++ ++ /* Local implementation of the recycle remote event */ ++ struct semaphore recycle_event; ++ ++ /* Local implementation of the sync trigger remote event */ ++ struct semaphore sync_trigger_event; ++ ++ /* Local implementation of the sync release remote event */ ++ struct semaphore sync_release_event; ++ ++ char *tx_data; ++ char *rx_data; ++ VCHIQ_SLOT_INFO_T *rx_info; ++ ++ struct mutex slot_mutex; ++ ++ struct mutex recycle_mutex; ++ ++ struct mutex sync_mutex; ++ ++ struct mutex bulk_transfer_mutex; ++ ++ /* Indicates the byte position within the stream from where the next ++ ** message will be read. The least significant bits are an index into ++ ** the slot.The next bits are the index of the slot in ++ ** remote->slot_queue. */ ++ int rx_pos; ++ ++ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read ++ from remote->tx_pos. */ ++ int local_tx_pos; ++ ++ /* The slot_queue index of the slot to become available next. */ ++ int slot_queue_available; ++ ++ /* A flag to indicate if any poll has been requested */ ++ int poll_needed; ++ ++ /* Ths index of the previous slot used for data messages. */ ++ int previous_data_index; ++ ++ /* The number of slots occupied by data messages. */ ++ unsigned short data_use_count; ++ ++ /* The maximum number of slots to be occupied by data messages. */ ++ unsigned short data_quota; ++ ++ /* An array of bit sets indicating which services must be polled. */ ++ atomic_t poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ ++ /* The number of the first unused service */ ++ int unused_service; ++ ++ /* Signalled when a free slot becomes available. */ ++ struct semaphore slot_available_event; ++ ++ struct semaphore slot_remove_event; ++ ++ /* Signalled when a free data slot becomes available. */ ++ struct semaphore data_quota_event; ++ ++ /* Incremented when there are bulk transfers which cannot be processed ++ * whilst paused and must be processed on resume */ ++ int deferred_bulks; ++ ++ struct state_stats_struct { ++ int slot_stalls; ++ int data_stalls; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int error_count; ++ } stats; ++ ++ VCHIQ_SERVICE_T * services[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; ++ ++ VCHIQ_PLATFORM_STATE_T platform_state; ++}; ++ ++struct bulk_waiter { ++ VCHIQ_BULK_T *bulk; ++ struct semaphore event; ++ int actual; ++}; ++ ++extern spinlock_t bulk_waiter_spinlock; ++ ++extern int vchiq_core_log_level; ++extern int vchiq_core_msg_log_level; ++extern int vchiq_sync_log_level; ++ ++extern VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; ++ ++extern const char * ++get_conn_state_name(VCHIQ_CONNSTATE_T conn_state); ++ ++extern VCHIQ_SLOT_ZERO_T * ++vchiq_init_slots(void *mem_base, int mem_size); ++ ++extern VCHIQ_STATUS_T ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, ++ int is_master); ++ ++extern VCHIQ_STATUS_T ++vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_SERVICE_T * ++vchiq_add_service_internal(VCHIQ_STATE_T *state, ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term); ++ ++extern VCHIQ_STATUS_T ++vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id); ++ ++extern VCHIQ_STATUS_T ++vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd); ++ ++extern void ++vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_free_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_STATUS_T ++vchiq_pause_internal(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_resume_internal(VCHIQ_STATE_T *state); ++ ++extern void ++remote_event_pollall(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir); ++ ++extern void ++vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_loud_error_header(void); ++ ++extern void ++vchiq_loud_error_footer(void); ++ ++extern void ++request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type); ++ ++static inline VCHIQ_SERVICE_T * ++handle_to_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATE_T *state = vchiq_states[(handle / VCHIQ_MAX_SERVICES) & ++ (VCHIQ_MAX_STATES - 1)]; ++ if (!state) ++ return NULL; ++ ++ return state->services[handle & (VCHIQ_MAX_SERVICES - 1)]; ++} ++ ++extern VCHIQ_SERVICE_T * ++find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * ++find_service_by_port(VCHIQ_STATE_T *state, int localport); ++ ++extern VCHIQ_SERVICE_T * ++find_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * ++find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * ++next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, ++ int *pidx); ++ ++extern void ++lock_service(VCHIQ_SERVICE_T *service); ++ ++extern void ++unlock_service(VCHIQ_SERVICE_T *service); ++ ++/* The following functions are called from vchiq_core, and external ++** implementations must be provided. */ ++ ++extern VCHIQ_STATUS_T ++vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir); ++ ++extern void ++vchiq_transfer_bulk(VCHIQ_BULK_T *bulk); ++ ++extern void ++vchiq_complete_bulk(VCHIQ_BULK_T *bulk); ++ ++extern VCHIQ_STATUS_T ++vchiq_copy_from_user(void *dst, const void *src, int size); ++ ++extern void ++remote_event_signal(REMOTE_EVENT_T *event); ++ ++void ++vchiq_platform_check_suspend(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_platform_paused(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_resume(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_platform_resumed(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump(void *dump_context, const char *str, int len); ++ ++extern void ++vchiq_dump_platform_state(void *dump_context); ++ ++extern void ++vchiq_dump_platform_instances(void *dump_context); ++ ++extern void ++vchiq_dump_platform_service_state(void *dump_context, ++ VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_use_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_release_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_on_remote_use(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_on_remote_release(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_init_state(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_on_remote_use_active(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_use(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_release(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_use_active(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, ++ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate); ++ ++extern void ++vchiq_platform_handle_timeout(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate); ++ ++ ++extern void ++vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, ++ size_t numBytes); ++ ++#endif +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c +@@ -0,0 +1,383 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++#include ++#include "vchiq_core.h" ++#include "vchiq_arm.h" ++#include "vchiq_debugfs.h" ++ ++#ifdef CONFIG_DEBUG_FS ++ ++/**************************************************************************** ++* ++* log category entries ++* ++***************************************************************************/ ++#define DEBUGFS_WRITE_BUF_SIZE 256 ++ ++#define VCHIQ_LOG_ERROR_STR "error" ++#define VCHIQ_LOG_WARNING_STR "warning" ++#define VCHIQ_LOG_INFO_STR "info" ++#define VCHIQ_LOG_TRACE_STR "trace" ++ ++ ++/* Top-level debug info */ ++struct vchiq_debugfs_info { ++ /* Global 'vchiq' debugfs entry used by all instances */ ++ struct dentry *vchiq_cfg_dir; ++ ++ /* one entry per client process */ ++ struct dentry *clients; ++ ++ /* log categories */ ++ struct dentry *log_categories; ++}; ++ ++static struct vchiq_debugfs_info debugfs_info; ++ ++/* Log category debugfs entries */ ++struct vchiq_debugfs_log_entry { ++ const char *name; ++ int *plevel; ++ struct dentry *dir; ++}; ++ ++static struct vchiq_debugfs_log_entry vchiq_debugfs_log_entries[] = { ++ { "core", &vchiq_core_log_level }, ++ { "msg", &vchiq_core_msg_log_level }, ++ { "sync", &vchiq_sync_log_level }, ++ { "susp", &vchiq_susp_log_level }, ++ { "arm", &vchiq_arm_log_level }, ++}; ++static int n_log_entries = ++ sizeof(vchiq_debugfs_log_entries)/sizeof(vchiq_debugfs_log_entries[0]); ++ ++ ++static struct dentry *vchiq_clients_top(void); ++static struct dentry *vchiq_debugfs_top(void); ++ ++static int debugfs_log_show(struct seq_file *f, void *offset) ++{ ++ int *levp = f->private; ++ char *log_value = NULL; ++ ++ switch (*levp) { ++ case VCHIQ_LOG_ERROR: ++ log_value = VCHIQ_LOG_ERROR_STR; ++ break; ++ case VCHIQ_LOG_WARNING: ++ log_value = VCHIQ_LOG_WARNING_STR; ++ break; ++ case VCHIQ_LOG_INFO: ++ log_value = VCHIQ_LOG_INFO_STR; ++ break; ++ case VCHIQ_LOG_TRACE: ++ log_value = VCHIQ_LOG_TRACE_STR; ++ break; ++ default: ++ break; ++ } ++ ++ seq_printf(f, "%s\n", log_value ? log_value : "(null)"); ++ ++ return 0; ++} ++ ++static int debugfs_log_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_log_show, inode->i_private); ++} ++ ++static int debugfs_log_write(struct file *file, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *f = (struct seq_file *)file->private_data; ++ int *levp = f->private; ++ char kbuf[DEBUGFS_WRITE_BUF_SIZE + 1]; ++ ++ memset(kbuf, 0, DEBUGFS_WRITE_BUF_SIZE + 1); ++ if (count >= DEBUGFS_WRITE_BUF_SIZE) ++ count = DEBUGFS_WRITE_BUF_SIZE; ++ ++ if (copy_from_user(kbuf, buffer, count) != 0) ++ return -EFAULT; ++ kbuf[count - 1] = 0; ++ ++ if (strncmp("error", kbuf, strlen("error")) == 0) ++ *levp = VCHIQ_LOG_ERROR; ++ else if (strncmp("warning", kbuf, strlen("warning")) == 0) ++ *levp = VCHIQ_LOG_WARNING; ++ else if (strncmp("info", kbuf, strlen("info")) == 0) ++ *levp = VCHIQ_LOG_INFO; ++ else if (strncmp("trace", kbuf, strlen("trace")) == 0) ++ *levp = VCHIQ_LOG_TRACE; ++ else ++ *levp = VCHIQ_LOG_DEFAULT; ++ ++ *ppos += count; ++ ++ return count; ++} ++ ++static const struct file_operations debugfs_log_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_log_open, ++ .write = debugfs_log_write, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/* create an entry under /vchiq/log for each log category */ ++static int vchiq_debugfs_create_log_entries(struct dentry *top) ++{ ++ struct dentry *dir; ++ size_t i; ++ int ret = 0; ++ dir = debugfs_create_dir("log", vchiq_debugfs_top()); ++ if (!dir) ++ return -ENOMEM; ++ debugfs_info.log_categories = dir; ++ ++ for (i = 0; i < n_log_entries; i++) { ++ void *levp = (void *)vchiq_debugfs_log_entries[i].plevel; ++ dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name, ++ 0644, ++ debugfs_info.log_categories, ++ levp, ++ &debugfs_log_fops); ++ if (!dir) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ vchiq_debugfs_log_entries[i].dir = dir; ++ } ++ return ret; ++} ++ ++static int debugfs_usecount_show(struct seq_file *f, void *offset) ++{ ++ VCHIQ_INSTANCE_T instance = f->private; ++ int use_count; ++ ++ use_count = vchiq_instance_get_use_count(instance); ++ seq_printf(f, "%d\n", use_count); ++ ++ return 0; ++} ++ ++static int debugfs_usecount_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_usecount_show, inode->i_private); ++} ++ ++static const struct file_operations debugfs_usecount_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_usecount_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static int debugfs_trace_show(struct seq_file *f, void *offset) ++{ ++ VCHIQ_INSTANCE_T instance = f->private; ++ int trace; ++ ++ trace = vchiq_instance_get_trace(instance); ++ seq_printf(f, "%s\n", trace ? "Y" : "N"); ++ ++ return 0; ++} ++ ++static int debugfs_trace_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_trace_show, inode->i_private); ++} ++ ++static int debugfs_trace_write(struct file *file, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *f = (struct seq_file *)file->private_data; ++ VCHIQ_INSTANCE_T instance = f->private; ++ char firstchar; ++ ++ if (copy_from_user(&firstchar, buffer, 1) != 0) ++ return -EFAULT; ++ ++ switch (firstchar) { ++ case 'Y': ++ case 'y': ++ case '1': ++ vchiq_instance_set_trace(instance, 1); ++ break; ++ case 'N': ++ case 'n': ++ case '0': ++ vchiq_instance_set_trace(instance, 0); ++ break; ++ default: ++ break; ++ } ++ ++ *ppos += count; ++ ++ return count; ++} ++ ++static const struct file_operations debugfs_trace_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_trace_open, ++ .write = debugfs_trace_write, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/* add an instance (process) to the debugfs entries */ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance) ++{ ++ char pidstr[16]; ++ struct dentry *top, *use_count, *trace; ++ struct dentry *clients = vchiq_clients_top(); ++ ++ snprintf(pidstr, sizeof(pidstr), "%d", ++ vchiq_instance_get_pid(instance)); ++ ++ top = debugfs_create_dir(pidstr, clients); ++ if (!top) ++ goto fail_top; ++ ++ use_count = debugfs_create_file("use_count", ++ 0444, top, ++ instance, ++ &debugfs_usecount_fops); ++ if (!use_count) ++ goto fail_use_count; ++ ++ trace = debugfs_create_file("trace", ++ 0644, top, ++ instance, ++ &debugfs_trace_fops); ++ if (!trace) ++ goto fail_trace; ++ ++ vchiq_instance_get_debugfs_node(instance)->dentry = top; ++ ++ return 0; ++ ++fail_trace: ++ debugfs_remove(use_count); ++fail_use_count: ++ debugfs_remove(top); ++fail_top: ++ return -ENOMEM; ++} ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_DEBUGFS_NODE_T *node = vchiq_instance_get_debugfs_node(instance); ++ debugfs_remove_recursive(node->dentry); ++} ++ ++ ++int vchiq_debugfs_init(void) ++{ ++ BUG_ON(debugfs_info.vchiq_cfg_dir != NULL); ++ ++ debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL); ++ if (debugfs_info.vchiq_cfg_dir == NULL) ++ goto fail; ++ ++ debugfs_info.clients = debugfs_create_dir("clients", ++ vchiq_debugfs_top()); ++ if (!debugfs_info.clients) ++ goto fail; ++ ++ if (vchiq_debugfs_create_log_entries(vchiq_debugfs_top()) != 0) ++ goto fail; ++ ++ return 0; ++ ++fail: ++ vchiq_debugfs_deinit(); ++ vchiq_log_error(vchiq_arm_log_level, ++ "%s: failed to create debugfs directory", ++ __func__); ++ ++ return -ENOMEM; ++} ++ ++/* remove all the debugfs entries */ ++void vchiq_debugfs_deinit(void) ++{ ++ debugfs_remove_recursive(vchiq_debugfs_top()); ++} ++ ++static struct dentry *vchiq_clients_top(void) ++{ ++ return debugfs_info.clients; ++} ++ ++static struct dentry *vchiq_debugfs_top(void) ++{ ++ BUG_ON(debugfs_info.vchiq_cfg_dir == NULL); ++ return debugfs_info.vchiq_cfg_dir; ++} ++ ++#else /* CONFIG_DEBUG_FS */ ++ ++int vchiq_debugfs_init(void) ++{ ++ return 0; ++} ++ ++void vchiq_debugfs_deinit(void) ++{ ++} ++ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance) ++{ ++ return 0; ++} ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance) ++{ ++} ++ ++#endif /* CONFIG_DEBUG_FS */ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h +@@ -0,0 +1,52 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_DEBUGFS_H ++#define VCHIQ_DEBUGFS_H ++ ++#include "vchiq_core.h" ++ ++typedef struct vchiq_debugfs_node_struct ++{ ++ struct dentry *dentry; ++} VCHIQ_DEBUGFS_NODE_T; ++ ++int vchiq_debugfs_init(void); ++ ++void vchiq_debugfs_deinit(void); ++ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance); ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance); ++ ++#endif /* VCHIQ_DEBUGFS_H */ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion +@@ -0,0 +1,87 @@ ++#!/usr/bin/perl -w ++ ++use strict; ++ ++# ++# Generate a version from available information ++# ++ ++my $prefix = shift @ARGV; ++my $root = shift @ARGV; ++ ++ ++if ( not defined $root ) { ++ die "usage: $0 prefix root-dir\n"; ++} ++ ++if ( ! -d $root ) { ++ die "root directory $root not found\n"; ++} ++ ++my $version = "unknown"; ++my $tainted = ""; ++ ++if ( -d "$root/.git" ) { ++ # attempt to work out git version. only do so ++ # on a linux build host, as cygwin builds are ++ # already slow enough ++ ++ if ( -f "/usr/bin/git" || -f "/usr/local/bin/git" ) { ++ if (not open(F, "git --git-dir $root/.git rev-parse --verify HEAD|")) { ++ $version = "no git version"; ++ } ++ else { ++ $version = ; ++ $version =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++ $version =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ } ++ ++ if (open(G, "git --git-dir $root/.git status --porcelain|")) { ++ $tainted = ; ++ $tainted =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++ $tainted =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ if (length $tainted) { ++ $version = join ' ', $version, "(tainted)"; ++ } ++ else { ++ $version = join ' ', $version, "(clean)"; ++ } ++ } ++ } ++} ++ ++my $hostname = `hostname`; ++$hostname =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++$hostname =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ ++ ++print STDERR "Version $version\n"; ++print < ++ ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_hostname, "$hostname" ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_version, "$version" ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_time, __TIME__ ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_date, __DATE__ ); ++ ++const char *vchiq_get_build_hostname( void ) ++{ ++ return vchiq_build_hostname; ++} ++ ++const char *vchiq_get_build_version( void ) ++{ ++ return vchiq_build_version; ++} ++ ++const char *vchiq_get_build_date( void ) ++{ ++ return vchiq_build_date; ++} ++ ++const char *vchiq_get_build_time( void ) ++{ ++ return vchiq_build_time; ++} ++EOF +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h +@@ -0,0 +1,189 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_IF_H ++#define VCHIQ_IF_H ++ ++#include "interface/vchi/vchi_mh.h" ++ ++#define VCHIQ_SERVICE_HANDLE_INVALID 0 ++ ++#define VCHIQ_SLOT_SIZE 4096 ++#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T)) ++#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */ ++ ++#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) \ ++ (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3)) ++#define VCHIQ_GET_SERVICE_USERDATA(service) vchiq_get_service_userdata(service) ++#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service) ++ ++typedef enum { ++ VCHIQ_SERVICE_OPENED, /* service, -, - */ ++ VCHIQ_SERVICE_CLOSED, /* service, -, - */ ++ VCHIQ_MESSAGE_AVAILABLE, /* service, header, - */ ++ VCHIQ_BULK_TRANSMIT_DONE, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_RECEIVE_DONE, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_TRANSMIT_ABORTED, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */ ++} VCHIQ_REASON_T; ++ ++typedef enum { ++ VCHIQ_ERROR = -1, ++ VCHIQ_SUCCESS = 0, ++ VCHIQ_RETRY = 1 ++} VCHIQ_STATUS_T; ++ ++typedef enum { ++ VCHIQ_BULK_MODE_CALLBACK, ++ VCHIQ_BULK_MODE_BLOCKING, ++ VCHIQ_BULK_MODE_NOCALLBACK, ++ VCHIQ_BULK_MODE_WAITING /* Reserved for internal use */ ++} VCHIQ_BULK_MODE_T; ++ ++typedef enum { ++ VCHIQ_SERVICE_OPTION_AUTOCLOSE, ++ VCHIQ_SERVICE_OPTION_SLOT_QUOTA, ++ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA, ++ VCHIQ_SERVICE_OPTION_SYNCHRONOUS, ++ VCHIQ_SERVICE_OPTION_TRACE ++} VCHIQ_SERVICE_OPTION_T; ++ ++typedef struct vchiq_header_struct { ++ /* The message identifier - opaque to applications. */ ++ int msgid; ++ ++ /* Size of message data. */ ++ unsigned int size; ++ ++ char data[0]; /* message */ ++} VCHIQ_HEADER_T; ++ ++typedef struct { ++ const void *data; ++ unsigned int size; ++} VCHIQ_ELEMENT_T; ++ ++typedef unsigned int VCHIQ_SERVICE_HANDLE_T; ++ ++typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *, ++ VCHIQ_SERVICE_HANDLE_T, void *); ++ ++typedef struct vchiq_service_base_struct { ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++} VCHIQ_SERVICE_BASE_T; ++ ++typedef struct vchiq_service_params_struct { ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++ short version; /* Increment for non-trivial changes */ ++ short version_min; /* Update for incompatible changes */ ++} VCHIQ_SERVICE_PARAMS_T; ++ ++typedef struct vchiq_config_struct { ++ unsigned int max_msg_size; ++ unsigned int bulk_threshold; /* The message size above which it ++ is better to use a bulk transfer ++ (<= max_msg_size) */ ++ unsigned int max_outstanding_bulks; ++ unsigned int max_services; ++ short version; /* The version of VCHIQ */ ++ short version_min; /* The minimum compatible version of VCHIQ */ ++} VCHIQ_CONFIG_T; ++ ++typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T; ++typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void *cb_arg); ++ ++extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance); ++extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance); ++extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance); ++extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_use_service_no_resume( ++ VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service); ++ ++extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service, ++ const VCHIQ_ELEMENT_T *elements, unsigned int count); ++extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service, ++ VCHIQ_HEADER_T *header); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, ++ const void *data, unsigned int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, ++ void *data, unsigned int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle( ++ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, ++ const void *offset, unsigned int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle( ++ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, ++ void *offset, unsigned int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, ++ const void *data, unsigned int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, ++ void *data, unsigned int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, ++ VCHI_MEM_HANDLE_T handle, const void *offset, unsigned int size, ++ void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, ++ VCHI_MEM_HANDLE_T handle, void *offset, unsigned int size, ++ void *userdata, VCHIQ_BULK_MODE_T mode); ++extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service); ++extern void *vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T service); ++extern int vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, ++ int config_size, VCHIQ_CONFIG_T *pconfig); ++extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, ++ VCHIQ_SERVICE_OPTION_T option, int value); ++ ++extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance, ++ VCHIQ_REMOTE_USE_CALLBACK_T callback, void *cb_arg); ++extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_STATUS_T vchiq_dump_phys_mem(VCHIQ_SERVICE_HANDLE_T service, ++ void *ptr, size_t num_bytes); ++ ++extern VCHIQ_STATUS_T vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, ++ short *peer_version); ++ ++#endif /* VCHIQ_IF_H */ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h +@@ -0,0 +1,131 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_IOCTLS_H ++#define VCHIQ_IOCTLS_H ++ ++#include ++#include "vchiq_if.h" ++ ++#define VCHIQ_IOC_MAGIC 0xc4 ++#define VCHIQ_INVALID_HANDLE (~0) ++ ++typedef struct { ++ VCHIQ_SERVICE_PARAMS_T params; ++ int is_open; ++ int is_vchi; ++ unsigned int handle; /* OUT */ ++} VCHIQ_CREATE_SERVICE_T; ++ ++typedef struct { ++ unsigned int handle; ++ unsigned int count; ++ const VCHIQ_ELEMENT_T *elements; ++} VCHIQ_QUEUE_MESSAGE_T; ++ ++typedef struct { ++ unsigned int handle; ++ void *data; ++ unsigned int size; ++ void *userdata; ++ VCHIQ_BULK_MODE_T mode; ++} VCHIQ_QUEUE_BULK_TRANSFER_T; ++ ++typedef struct { ++ VCHIQ_REASON_T reason; ++ VCHIQ_HEADER_T *header; ++ void *service_userdata; ++ void *bulk_userdata; ++} VCHIQ_COMPLETION_DATA_T; ++ ++typedef struct { ++ unsigned int count; ++ VCHIQ_COMPLETION_DATA_T *buf; ++ unsigned int msgbufsize; ++ unsigned int msgbufcount; /* IN/OUT */ ++ void **msgbufs; ++} VCHIQ_AWAIT_COMPLETION_T; ++ ++typedef struct { ++ unsigned int handle; ++ int blocking; ++ unsigned int bufsize; ++ void *buf; ++} VCHIQ_DEQUEUE_MESSAGE_T; ++ ++typedef struct { ++ unsigned int config_size; ++ VCHIQ_CONFIG_T *pconfig; ++} VCHIQ_GET_CONFIG_T; ++ ++typedef struct { ++ unsigned int handle; ++ VCHIQ_SERVICE_OPTION_T option; ++ int value; ++} VCHIQ_SET_SERVICE_OPTION_T; ++ ++typedef struct { ++ void *virt_addr; ++ size_t num_bytes; ++} VCHIQ_DUMP_MEM_T; ++ ++#define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0) ++#define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1) ++#define VCHIQ_IOC_CREATE_SERVICE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T) ++#define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3) ++#define VCHIQ_IOC_QUEUE_MESSAGE \ ++ _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) ++#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT \ ++ _IOWR(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_QUEUE_BULK_RECEIVE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_AWAIT_COMPLETION \ ++ _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) ++#define VCHIQ_IOC_DEQUEUE_MESSAGE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) ++#define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9) ++#define VCHIQ_IOC_GET_CONFIG \ ++ _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) ++#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11) ++#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12) ++#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13) ++#define VCHIQ_IOC_SET_SERVICE_OPTION \ ++ _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) ++#define VCHIQ_IOC_DUMP_PHYS_MEM \ ++ _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) ++#define VCHIQ_IOC_LIB_VERSION _IO(VCHIQ_IOC_MAGIC, 16) ++#define VCHIQ_IOC_CLOSE_DELIVERED _IO(VCHIQ_IOC_MAGIC, 17) ++#define VCHIQ_IOC_MAX 17 ++ ++#endif +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c +@@ -0,0 +1,458 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#include ++#include ++#include ++ ++#include "vchiq_core.h" ++#include "vchiq_arm.h" ++#include "vchiq_killable.h" ++ ++/* ---- Public Variables ------------------------------------------------- */ ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++struct bulk_waiter_node { ++ struct bulk_waiter bulk_waiter; ++ int pid; ++ struct list_head list; ++}; ++ ++struct vchiq_instance_struct { ++ VCHIQ_STATE_T *state; ++ ++ int connected; ++ ++ struct list_head bulk_waiter_list; ++ struct mutex bulk_waiter_list_mutex; ++}; ++ ++static VCHIQ_STATUS_T ++vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data, ++ unsigned int size, VCHIQ_BULK_DIR_T dir); ++ ++/**************************************************************************** ++* ++* vchiq_initialise ++* ++***************************************************************************/ ++#define VCHIQ_INIT_RETRIES 10 ++VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instanceOut) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance = NULL; ++ int i; ++ ++ vchiq_log_trace(vchiq_core_log_level, "%s called", __func__); ++ ++ /* VideoCore may not be ready due to boot up timing. ++ It may never be ready if kernel and firmware are mismatched, so don't block forever. */ ++ for (i=0; i0) { ++ vchiq_log_warning(vchiq_core_log_level, ++ "%s: videocore initialized after %d retries\n", __func__, i); ++ } ++ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%s: error allocating vchiq instance\n", __func__); ++ goto failed; ++ } ++ ++ instance->connected = 0; ++ instance->state = state; ++ mutex_init(&instance->bulk_waiter_list_mutex); ++ INIT_LIST_HEAD(&instance->bulk_waiter_list); ++ ++ *instanceOut = instance; ++ ++ status = VCHIQ_SUCCESS; ++ ++failed: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_initialise); ++ ++/**************************************************************************** ++* ++* vchiq_shutdown ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ if (mutex_lock_interruptible(&state->mutex) != 0) ++ return VCHIQ_RETRY; ++ ++ /* Remove all services */ ++ status = vchiq_shutdown_internal(state, instance); ++ ++ mutex_unlock(&state->mutex); ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ if (status == VCHIQ_SUCCESS) { ++ struct list_head *pos, *next; ++ list_for_each_safe(pos, next, ++ &instance->bulk_waiter_list) { ++ struct bulk_waiter_node *waiter; ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ vchiq_log_info(vchiq_arm_log_level, ++ "bulk_waiter - cleaned up %x " ++ "for pid %d", ++ (unsigned int)waiter, waiter->pid); ++ kfree(waiter); ++ } ++ kfree(instance); ++ } ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_shutdown); ++ ++/**************************************************************************** ++* ++* vchiq_is_connected ++* ++***************************************************************************/ ++ ++int vchiq_is_connected(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->connected; ++} ++ ++/**************************************************************************** ++* ++* vchiq_connect ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ if (mutex_lock_interruptible(&state->mutex) != 0) { ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s: call to mutex_lock failed", __func__); ++ status = VCHIQ_RETRY; ++ goto failed; ++ } ++ status = vchiq_connect_internal(state, instance); ++ ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; ++ ++ mutex_unlock(&state->mutex); ++ ++failed: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_connect); ++ ++/**************************************************************************** ++* ++* vchiq_add_service ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_add_service( ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *phandle) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service = NULL; ++ int srvstate; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; ++ ++ srvstate = vchiq_is_connected(instance) ++ ? VCHIQ_SRVSTATE_LISTENING ++ : VCHIQ_SRVSTATE_HIDDEN; ++ ++ service = vchiq_add_service_internal( ++ state, ++ params, ++ srvstate, ++ instance, ++ NULL); ++ ++ if (service) { ++ *phandle = service->handle; ++ status = VCHIQ_SUCCESS; ++ } else ++ status = VCHIQ_ERROR; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_add_service); ++ ++/**************************************************************************** ++* ++* vchiq_open_service ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_open_service( ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *phandle) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service = NULL; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; ++ ++ if (!vchiq_is_connected(instance)) ++ goto failed; ++ ++ service = vchiq_add_service_internal(state, ++ params, ++ VCHIQ_SRVSTATE_OPENING, ++ instance, ++ NULL); ++ ++ if (service) { ++ *phandle = service->handle; ++ status = vchiq_open_service_internal(service, current->pid); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_remove_service(service->handle); ++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; ++ } ++ } ++ ++failed: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_open_service); ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, ++ const void *data, unsigned int size, void *userdata) ++{ ++ return vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); ++} ++EXPORT_SYMBOL(vchiq_queue_bulk_transmit); ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, ++ unsigned int size, void *userdata) ++{ ++ return vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); ++} ++EXPORT_SYMBOL(vchiq_queue_bulk_receive); ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data, ++ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode) ++{ ++ VCHIQ_STATUS_T status; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ status = vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ mode, VCHIQ_BULK_TRANSMIT); ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ status = vchiq_blocking_bulk_transfer(handle, ++ (void *)data, size, VCHIQ_BULK_TRANSMIT); ++ break; ++ default: ++ return VCHIQ_ERROR; ++ } ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_bulk_transmit); ++ ++VCHIQ_STATUS_T ++vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, ++ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode) ++{ ++ VCHIQ_STATUS_T status; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ status = vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ mode, VCHIQ_BULK_RECEIVE); ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ status = vchiq_blocking_bulk_transfer(handle, ++ (void *)data, size, VCHIQ_BULK_RECEIVE); ++ break; ++ default: ++ return VCHIQ_ERROR; ++ } ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_bulk_receive); ++ ++static VCHIQ_STATUS_T ++vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data, ++ unsigned int size, VCHIQ_BULK_DIR_T dir) ++{ ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_SERVICE_T *service; ++ VCHIQ_STATUS_T status; ++ struct bulk_waiter_node *waiter = NULL; ++ struct list_head *pos; ++ ++ service = find_service_by_handle(handle); ++ if (!service) ++ return VCHIQ_ERROR; ++ ++ instance = service->instance; ++ ++ unlock_service(service); ++ ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_for_each(pos, &instance->bulk_waiter_list) { ++ if (list_entry(pos, struct bulk_waiter_node, ++ list)->pid == current->pid) { ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ break; ++ } ++ } ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ ++ if (waiter) { ++ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk; ++ if (bulk) { ++ /* This thread has an outstanding bulk transfer. */ ++ if ((bulk->data != data) || ++ (bulk->size != size)) { ++ /* This is not a retry of the previous one. ++ ** Cancel the signal when the transfer ++ ** completes. */ ++ spin_lock(&bulk_waiter_spinlock); ++ bulk->userdata = NULL; ++ spin_unlock(&bulk_waiter_spinlock); ++ } ++ } ++ } ++ ++ if (!waiter) { ++ waiter = kzalloc(sizeof(struct bulk_waiter_node), GFP_KERNEL); ++ if (!waiter) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%s - out of memory", __func__); ++ return VCHIQ_ERROR; ++ } ++ } ++ ++ status = vchiq_bulk_transfer(handle, VCHI_MEM_HANDLE_INVALID, ++ data, size, &waiter->bulk_waiter, VCHIQ_BULK_MODE_BLOCKING, ++ dir); ++ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || ++ !waiter->bulk_waiter.bulk) { ++ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk; ++ if (bulk) { ++ /* Cancel the signal when the transfer ++ ** completes. */ ++ spin_lock(&bulk_waiter_spinlock); ++ bulk->userdata = NULL; ++ spin_unlock(&bulk_waiter_spinlock); ++ } ++ kfree(waiter); ++ } else { ++ waiter->pid = current->pid; ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_add(&waiter->list, &instance->bulk_waiter_list); ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ vchiq_log_info(vchiq_arm_log_level, ++ "saved bulk_waiter %x for pid %d", ++ (unsigned int)waiter, current->pid); ++ } ++ ++ return status; ++} +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h +@@ -0,0 +1,69 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_KILLABLE_H ++#define VCHIQ_KILLABLE_H ++ ++#include ++#include ++ ++#define SHUTDOWN_SIGS (sigmask(SIGKILL) | sigmask(SIGINT) | sigmask(SIGQUIT) | sigmask(SIGTRAP) | sigmask(SIGSTOP) | sigmask(SIGCONT)) ++ ++static inline int __must_check down_interruptible_killable(struct semaphore *sem) ++{ ++ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */ ++ int ret; ++ sigset_t blocked, oldset; ++ siginitsetinv(&blocked, SHUTDOWN_SIGS); ++ sigprocmask(SIG_SETMASK, &blocked, &oldset); ++ ret = down_interruptible(sem); ++ sigprocmask(SIG_SETMASK, &oldset, NULL); ++ return ret; ++} ++#define down_interruptible down_interruptible_killable ++ ++ ++static inline int __must_check mutex_lock_interruptible_killable(struct mutex *lock) ++{ ++ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */ ++ int ret; ++ sigset_t blocked, oldset; ++ siginitsetinv(&blocked, SHUTDOWN_SIGS); ++ sigprocmask(SIG_SETMASK, &blocked, &oldset); ++ ret = mutex_lock_interruptible(lock); ++ sigprocmask(SIG_SETMASK, &oldset, NULL); ++ return ret; ++} ++#define mutex_lock_interruptible mutex_lock_interruptible_killable ++ ++#endif +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h +@@ -0,0 +1,71 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_MEMDRV_H ++#define VCHIQ_MEMDRV_H ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++#include ++#include "vchiq_if.h" ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++typedef struct { ++ void *armSharedMemVirt; ++ dma_addr_t armSharedMemPhys; ++ size_t armSharedMemSize; ++ ++ void *vcSharedMemVirt; ++ dma_addr_t vcSharedMemPhys; ++ size_t vcSharedMemSize; ++} VCHIQ_SHARED_MEM_INFO_T; ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++void vchiq_get_shared_mem_info(VCHIQ_SHARED_MEM_INFO_T *info); ++ ++VCHIQ_STATUS_T vchiq_memdrv_initialise(void); ++ ++VCHIQ_STATUS_T vchiq_userdrv_create_instance( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ ++VCHIQ_STATUS_T vchiq_userdrv_suspend( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ ++VCHIQ_STATUS_T vchiq_userdrv_resume( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ ++#endif +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h +@@ -0,0 +1,58 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_PAGELIST_H ++#define VCHIQ_PAGELIST_H ++ ++#ifndef PAGE_SIZE ++#define PAGE_SIZE 4096 ++#endif ++#define CACHE_LINE_SIZE 32 ++#define PAGELIST_WRITE 0 ++#define PAGELIST_READ 1 ++#define PAGELIST_READ_WITH_FRAGMENTS 2 ++ ++typedef struct pagelist_struct { ++ unsigned long length; ++ unsigned short type; ++ unsigned short offset; ++ unsigned long addrs[1]; /* N.B. 12 LSBs hold the number of following ++ pages at consecutive addresses. */ ++} PAGELIST_T; ++ ++typedef struct fragments_struct { ++ char headbuf[CACHE_LINE_SIZE]; ++ char tailbuf[CACHE_LINE_SIZE]; ++} FRAGMENTS_T; ++ ++#endif /* VCHIQ_PAGELIST_H */ +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c +@@ -0,0 +1,860 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++#include ++#include ++ ++#include "interface/vchi/vchi.h" ++#include "vchiq.h" ++#include "vchiq_core.h" ++ ++#include "vchiq_util.h" ++ ++#include ++ ++#define vchiq_status_to_vchi(status) ((int32_t)status) ++ ++typedef struct { ++ VCHIQ_SERVICE_HANDLE_T handle; ++ ++ VCHIU_QUEUE_T queue; ++ ++ VCHI_CALLBACK_T callback; ++ void *callback_param; ++} SHIM_SERVICE_T; ++ ++/* ---------------------------------------------------------------------- ++ * return pointer to the mphi message driver function table ++ * -------------------------------------------------------------------- */ ++const VCHI_MESSAGE_DRIVER_T * ++vchi_mphi_message_driver_func_table(void) ++{ ++ return NULL; ++} ++ ++/* ---------------------------------------------------------------------- ++ * return a pointer to the 'single' connection driver fops ++ * -------------------------------------------------------------------- */ ++const VCHI_CONNECTION_API_T * ++single_get_func_table(void) ++{ ++ return NULL; ++} ++ ++VCHI_CONNECTION_T *vchi_create_connection( ++ const VCHI_CONNECTION_API_T *function_table, ++ const VCHI_MESSAGE_DRIVER_T *low_level) ++{ ++ (void)function_table; ++ (void)low_level; ++ return NULL; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_peek ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ ++ ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to return a pointer to the current message (to allow in ++ * place processing). The message can be removed using ++ * vchi_msg_remove when you're finished ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_peek(VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_peek(&service->queue); ++ ++ *data = header->data; ++ *msg_size = header->size; ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_msg_peek); ++ ++/*********************************************************** ++ * Name: vchi_msg_remove ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * ++ * Description: Routine to remove a message (after it has been read with ++ * vchi_msg_peek) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_remove(VCHI_SERVICE_HANDLE_T handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ vchiq_release_message(service->handle, header); ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_msg_remove); ++ ++/*********************************************************** ++ * Name: vchi_msg_queue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * const void *data, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle, ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_ELEMENT_T element = {data, data_size}; ++ VCHIQ_STATUS_T status; ++ ++ (void)msg_handle; ++ ++ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ status = vchiq_queue_message(service->handle, &element, 1); ++ ++ /* vchiq_queue_message() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_queue_message(service->handle, &element, 1); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++EXPORT_SYMBOL(vchi_msg_queue); ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_receive ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * void *data_dst, ++ * const uint32_t data_size, ++ * VCHI_FLAGS_T flags ++ * void *bulk_handle ++ * ++ * Description: Routine to setup a rcv buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_bulk_queue_receive(VCHI_SERVICE_HANDLE_T handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE ++ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ WARN_ON(!service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ WARN(1, "unsupported message\n"); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_receive(service->handle, data_dst, data_size, ++ bulk_handle, mode); ++ ++ /* vchiq_bulk_receive() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_bulk_receive(service->handle, data_dst, ++ data_size, bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++EXPORT_SYMBOL(vchi_bulk_queue_receive); ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_transmit ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * const void *data_src, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *bulk_handle ++ * ++ * Description: Routine to transmit some data ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_bulk_queue_transmit(VCHI_SERVICE_HANDLE_T handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE ++ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ WARN_ON(!service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ WARN(1, "unsupported message\n"); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_transmit(service->handle, data_src, data_size, ++ bulk_handle, mode); ++ ++ /* vchiq_bulk_transmit() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_bulk_transmit(service->handle, data_src, ++ data_size, bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++EXPORT_SYMBOL(vchi_bulk_queue_transmit); ++ ++/*********************************************************** ++ * Name: vchi_msg_dequeue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void *data, ++ * uint32_t max_data_size_to_read, ++ * uint32_t *actual_msg_size ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to dequeue a message into the supplied buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ memcpy(data, header->data, header->size < max_data_size_to_read ? ++ header->size : max_data_size_to_read); ++ ++ *actual_msg_size = header->size; ++ ++ vchiq_release_message(service->handle, header); ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_msg_dequeue); ++ ++/*********************************************************** ++ * Name: vchi_msg_queuev ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * VCHI_MSG_VECTOR_T *vector, ++ * uint32_t count, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); ++vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == ++ offsetof(VCHIQ_ELEMENT_T, data)); ++vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == ++ offsetof(VCHIQ_ELEMENT_T, size)); ++ ++int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ ++ (void)msg_handle; ++ ++ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ return vchiq_status_to_vchi(vchiq_queue_message(service->handle, ++ (const VCHIQ_ELEMENT_T *)vector, count)); ++} ++EXPORT_SYMBOL(vchi_msg_queuev); ++ ++/*********************************************************** ++ * Name: vchi_held_msg_release ++ * ++ * Arguments: VCHI_HELD_MSG_T *message ++ * ++ * Description: Routine to release a held message (after it has been read with ++ * vchi_msg_hold) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_held_msg_release(VCHI_HELD_MSG_T *message) ++{ ++ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service, ++ (VCHIQ_HEADER_T *)message->message); ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_held_msg_release); ++ ++/*********************************************************** ++ * Name: vchi_msg_hold ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ * VCHI_FLAGS_T flags, ++ * VCHI_HELD_MSG_T *message_handle ++ * ++ * Description: Routine to return a pointer to the current message (to allow ++ * in place processing). The message is dequeued - don't forget ++ * to release the message using vchi_held_msg_release when you're ++ * finished. ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_hold(VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ *data = header->data; ++ *msg_size = header->size; ++ ++ message_handle->service = ++ (struct opaque_vchi_service_t *)service->handle; ++ message_handle->message = header; ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_msg_hold); ++ ++/*********************************************************** ++ * Name: vchi_initialise ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * ++ * Description: Initialises the hardware but does not transmit anything ++ * When run as a Host App this will be called twice hence the need ++ * to malloc the state information ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++ ++int32_t vchi_initialise(VCHI_INSTANCE_T *instance_handle) ++{ ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_STATUS_T status; ++ ++ status = vchiq_initialise(&instance); ++ ++ *instance_handle = (VCHI_INSTANCE_T)instance; ++ ++ return vchiq_status_to_vchi(status); ++} ++EXPORT_SYMBOL(vchi_initialise); ++ ++/*********************************************************** ++ * Name: vchi_connect ++ * ++ * Arguments: VCHI_CONNECTION_T **connections ++ * const uint32_t num_connections ++ * VCHI_INSTANCE_T instance_handle) ++ * ++ * Description: Starts the command service on each connection, ++ * causing INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t vchi_connect(VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ ++ (void)connections; ++ (void)num_connections; ++ ++ return vchiq_connect(instance); ++} ++EXPORT_SYMBOL(vchi_connect); ++ ++ ++/*********************************************************** ++ * Name: vchi_disconnect ++ * ++ * Arguments: VCHI_INSTANCE_T instance_handle ++ * ++ * Description: Stops the command service on each connection, ++ * causing DE-INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t vchi_disconnect(VCHI_INSTANCE_T instance_handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ return vchiq_status_to_vchi(vchiq_shutdown(instance)); ++} ++EXPORT_SYMBOL(vchi_disconnect); ++ ++ ++/*********************************************************** ++ * Name: vchi_service_open ++ * Name: vchi_service_create ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * SERVICE_CREATION_T *setup, ++ * VCHI_SERVICE_HANDLE_T *handle ++ * ++ * Description: Routine to open a service ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user) ++{ ++ SHIM_SERVICE_T *service = ++ (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle); ++ ++ if (!service->callback) ++ goto release; ++ ++ switch (reason) { ++ case VCHIQ_MESSAGE_AVAILABLE: ++ vchiu_queue_push(&service->queue, header); ++ ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_MSG_AVAILABLE, NULL); ++ ++ goto done; ++ break; ++ ++ case VCHIQ_BULK_TRANSMIT_DONE: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_SENT, bulk_user); ++ break; ++ ++ case VCHIQ_BULK_RECEIVE_DONE: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_RECEIVED, bulk_user); ++ break; ++ ++ case VCHIQ_SERVICE_CLOSED: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_SERVICE_CLOSED, NULL); ++ break; ++ ++ case VCHIQ_SERVICE_OPENED: ++ /* No equivalent VCHI reason */ ++ break; ++ ++ case VCHIQ_BULK_TRANSMIT_ABORTED: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, ++ bulk_user); ++ break; ++ ++ case VCHIQ_BULK_RECEIVE_ABORTED: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, ++ bulk_user); ++ break; ++ ++ default: ++ WARN(1, "not supported\n"); ++ break; ++ } ++ ++release: ++ vchiq_release_message(service->handle, header); ++done: ++ return VCHIQ_SUCCESS; ++} ++ ++static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance, ++ SERVICE_CREATION_T *setup) ++{ ++ SHIM_SERVICE_T *service = kzalloc(sizeof(SHIM_SERVICE_T), GFP_KERNEL); ++ ++ (void)instance; ++ ++ if (service) { ++ if (vchiu_queue_init(&service->queue, 64)) { ++ service->callback = setup->callback; ++ service->callback_param = setup->callback_param; ++ } else { ++ kfree(service); ++ service = NULL; ++ } ++ } ++ ++ return service; ++} ++ ++static void service_free(SHIM_SERVICE_T *service) ++{ ++ if (service) { ++ vchiu_queue_delete(&service->queue); ++ kfree(service); ++ } ++} ++ ++int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ if (service) { ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.callback = shim_callback; ++ params.userdata = service; ++ params.version = setup->version.version; ++ params.version_min = setup->version.version_min; ++ ++ status = vchiq_open_service(instance, ¶ms, ++ &service->handle); ++ if (status != VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ *handle = NULL; ++ } ++ } ++ ++ return (service != NULL) ? 0 : -1; ++} ++EXPORT_SYMBOL(vchi_service_open); ++ ++int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ if (service) { ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.callback = shim_callback; ++ params.userdata = service; ++ params.version = setup->version.version; ++ params.version_min = setup->version.version_min; ++ status = vchiq_add_service(instance, ¶ms, &service->handle); ++ ++ if (status != VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ *handle = NULL; ++ } ++ } ++ ++ return (service != NULL) ? 0 : -1; ++} ++EXPORT_SYMBOL(vchi_service_create); ++ ++int32_t vchi_service_close(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) { ++ VCHIQ_STATUS_T status = vchiq_close_service(service->handle); ++ if (status == VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_close); ++ ++int32_t vchi_service_destroy(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) { ++ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle); ++ if (status == VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_destroy); ++ ++int32_t vchi_service_set_option(const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_SERVICE_OPTION_T option, ++ int value) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_SERVICE_OPTION_T vchiq_option; ++ switch (option) { ++ case VCHI_SERVICE_OPTION_TRACE: ++ vchiq_option = VCHIQ_SERVICE_OPTION_TRACE; ++ break; ++ case VCHI_SERVICE_OPTION_SYNCHRONOUS: ++ vchiq_option = VCHIQ_SERVICE_OPTION_SYNCHRONOUS; ++ break; ++ default: ++ service = NULL; ++ break; ++ } ++ if (service) { ++ VCHIQ_STATUS_T status = ++ vchiq_set_service_option(service->handle, ++ vchiq_option, ++ value); ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_set_option); ++ ++int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, short *peer_version ) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ VCHIQ_STATUS_T status = vchiq_get_peer_version(service->handle, peer_version); ++ ret = vchiq_status_to_vchi( status ); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_get_peer_version); ++ ++/* ---------------------------------------------------------------------- ++ * read a uint32_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint32_t ++vchi_readbuf_uint32(const void *_ptr) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint32_t to buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint32(void *_ptr, uint32_t value) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (unsigned char)((value >> 0) & 0xFF); ++ ptr[1] = (unsigned char)((value >> 8) & 0xFF); ++ ptr[2] = (unsigned char)((value >> 16) & 0xFF); ++ ptr[3] = (unsigned char)((value >> 24) & 0xFF); ++} ++ ++/* ---------------------------------------------------------------------- ++ * read a uint16_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint16_t ++vchi_readbuf_uint16(const void *_ptr) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint16_t into the buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint16(void *_ptr, uint16_t value) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (value >> 0) & 0xFF; ++ ptr[1] = (value >> 8) & 0xFF; ++} ++ ++/*********************************************************** ++ * Name: vchi_service_use ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to increment refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t vchi_service_use(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) ++ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_use); ++ ++/*********************************************************** ++ * Name: vchi_service_release ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to decrement refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t vchi_service_release(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) ++ ret = vchiq_status_to_vchi( ++ vchiq_release_service(service->handle)); ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_release); +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c +@@ -0,0 +1,152 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "vchiq_util.h" ++#include "vchiq_killable.h" ++ ++static inline int is_pow2(int i) ++{ ++ return i && !(i & (i - 1)); ++} ++ ++int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size) ++{ ++ WARN_ON(!is_pow2(size)); ++ ++ queue->size = size; ++ queue->read = 0; ++ queue->write = 0; ++ ++ sema_init(&queue->pop, 0); ++ sema_init(&queue->push, 0); ++ ++ queue->storage = kzalloc(size * sizeof(VCHIQ_HEADER_T *), GFP_KERNEL); ++ if (queue->storage == NULL) { ++ vchiu_queue_delete(queue); ++ return 0; ++ } ++ return 1; ++} ++ ++void vchiu_queue_delete(VCHIU_QUEUE_T *queue) ++{ ++ if (queue->storage != NULL) ++ kfree(queue->storage); ++} ++ ++int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue) ++{ ++ return queue->read == queue->write; ++} ++ ++int vchiu_queue_is_full(VCHIU_QUEUE_T *queue) ++{ ++ return queue->write == queue->read + queue->size; ++} ++ ++void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header) ++{ ++ while (queue->write == queue->read + queue->size) { ++ if (down_interruptible(&queue->pop) != 0) { ++ flush_signals(current); ++ } ++ } ++ ++ /* ++ * Write to queue->storage must be visible after read from ++ * queue->read ++ */ ++ smp_mb(); ++ ++ queue->storage[queue->write & (queue->size - 1)] = header; ++ ++ /* ++ * Write to queue->storage must be visible before write to ++ * queue->write ++ */ ++ smp_wmb(); ++ ++ queue->write++; ++ ++ up(&queue->push); ++} ++ ++VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue) ++{ ++ while (queue->write == queue->read) { ++ if (down_interruptible(&queue->push) != 0) { ++ flush_signals(current); ++ } ++ } ++ ++ up(&queue->push); // We haven't removed anything from the queue. ++ ++ /* ++ * Read from queue->storage must be visible after read from ++ * queue->write ++ */ ++ smp_rmb(); ++ ++ return queue->storage[queue->read & (queue->size - 1)]; ++} ++ ++VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue) ++{ ++ VCHIQ_HEADER_T *header; ++ ++ while (queue->write == queue->read) { ++ if (down_interruptible(&queue->push) != 0) { ++ flush_signals(current); ++ } ++ } ++ ++ /* ++ * Read from queue->storage must be visible after read from ++ * queue->write ++ */ ++ smp_rmb(); ++ ++ header = queue->storage[queue->read & (queue->size - 1)]; ++ ++ /* ++ * Read from queue->storage must be visible before write to ++ * queue->read ++ */ ++ smp_mb(); ++ ++ queue->read++; ++ ++ up(&queue->pop); ++ ++ return header; ++} +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h +@@ -0,0 +1,81 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_UTIL_H ++#define VCHIQ_UTIL_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* for time_t */ ++#include ++#include ++ ++#include "vchiq_if.h" ++ ++typedef struct { ++ int size; ++ int read; ++ int write; ++ ++ struct semaphore pop; ++ struct semaphore push; ++ ++ VCHIQ_HEADER_T **storage; ++} VCHIU_QUEUE_T; ++ ++extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size); ++extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue); ++ ++extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue); ++extern int vchiu_queue_is_full(VCHIU_QUEUE_T *queue); ++ ++extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header); ++ ++extern VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue); ++extern VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue); ++ ++#endif +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c +@@ -0,0 +1,59 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++#include "vchiq_build_info.h" ++#include ++ ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_hostname, "dc4-arm-01" ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_version, "9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 (tainted)" ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_time, __TIME__ ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_date, __DATE__ ); ++ ++const char *vchiq_get_build_hostname( void ) ++{ ++ return vchiq_build_hostname; ++} ++ ++const char *vchiq_get_build_version( void ) ++{ ++ return vchiq_build_version; ++} ++ ++const char *vchiq_get_build_date( void ) ++{ ++ return vchiq_build_date; ++} ++ ++const char *vchiq_get_build_time( void ) ++{ ++ return vchiq_build_time; ++} diff --git a/target/linux/brcm2708/patches-4.1/0013-vc_mem-Add-vc_mem-driver.patch b/target/linux/brcm2708/patches-4.1/0013-vc_mem-Add-vc_mem-driver.patch new file mode 100644 index 0000000..7c19cf9 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0013-vc_mem-Add-vc_mem-driver.patch @@ -0,0 +1,992 @@ +From c281e92ad16639d2b5bcce1302f78372f29b8cc0 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 17 Jun 2015 16:07:06 +0100 +Subject: [PATCH 013/203] vc_mem: Add vc_mem driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: popcornmix + +BCM270x: Move vc_mem + +Make the vc_mem module available for ARCH_BCM2835 by moving it. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 --- + arch/arm/mach-bcm2709/vc_mem.c | 431 ---------------------------- + drivers/char/broadcom/Kconfig | 12 +- + drivers/char/broadcom/Makefile | 1 + + drivers/char/broadcom/vc_mem.c | 423 +++++++++++++++++++++++++++ + include/linux/broadcom/vc_mem.h | 35 +++ + 6 files changed, 470 insertions(+), 467 deletions(-) + delete mode 100644 arch/arm/mach-bcm2709/include/mach/vc_mem.h + delete mode 100644 arch/arm/mach-bcm2709/vc_mem.c + create mode 100644 drivers/char/broadcom/vc_mem.c + create mode 100644 include/linux/broadcom/vc_mem.h + +--- a/arch/arm/mach-bcm2709/include/mach/vc_mem.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-/***************************************************************************** +-* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +-#if !defined( VC_MEM_H ) +-#define VC_MEM_H +- +-#include +- +-#define VC_MEM_IOC_MAGIC 'v' +- +-#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) +-#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) +-#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int ) +-#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int ) +- +-#if defined( __KERNEL__ ) +-#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF +- +-extern unsigned long mm_vc_mem_phys_addr; +-extern unsigned int mm_vc_mem_size; +-extern int vc_mem_get_current_size( void ); +-#endif +- +-#endif /* VC_MEM_H */ +--- a/arch/arm/mach-bcm2709/vc_mem.c ++++ /dev/null +@@ -1,431 +0,0 @@ +-/***************************************************************************** +-* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#ifdef CONFIG_ARCH_KONA +-#include +-#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709) +-#else +-#include +-#endif +- +-#include "mach/vc_mem.h" +- +-#define DRIVER_NAME "vc-mem" +- +-// Device (/dev) related variables +-static dev_t vc_mem_devnum = 0; +-static struct class *vc_mem_class = NULL; +-static struct cdev vc_mem_cdev; +-static int vc_mem_inited = 0; +- +-#ifdef CONFIG_DEBUG_FS +-static struct dentry *vc_mem_debugfs_entry; +-#endif +- +-/* +- * Videocore memory addresses and size +- * +- * Drivers that wish to know the videocore memory addresses and sizes should +- * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in +- * headers. This allows the other drivers to not be tied down to a a certain +- * address/size at compile time. +- * +- * In the future, the goal is to have the videocore memory virtual address and +- * size be calculated at boot time rather than at compile time. The decision of +- * where the videocore memory resides and its size would be in the hands of the +- * bootloader (and/or kernel). When that happens, the values of these variables +- * would be calculated and assigned in the init function. +- */ +-// in the 2835 VC in mapped above ARM, but ARM has full access to VC space +-unsigned long mm_vc_mem_phys_addr = 0x00000000; +-unsigned int mm_vc_mem_size = 0; +-unsigned int mm_vc_mem_base = 0; +- +-EXPORT_SYMBOL(mm_vc_mem_phys_addr); +-EXPORT_SYMBOL(mm_vc_mem_size); +-EXPORT_SYMBOL(mm_vc_mem_base); +- +-static uint phys_addr = 0; +-static uint mem_size = 0; +-static uint mem_base = 0; +- +- +-/**************************************************************************** +-* +-* vc_mem_open +-* +-***************************************************************************/ +- +-static int +-vc_mem_open(struct inode *inode, struct file *file) +-{ +- (void) inode; +- (void) file; +- +- pr_debug("%s: called file = 0x%p\n", __func__, file); +- +- return 0; +-} +- +-/**************************************************************************** +-* +-* vc_mem_release +-* +-***************************************************************************/ +- +-static int +-vc_mem_release(struct inode *inode, struct file *file) +-{ +- (void) inode; +- (void) file; +- +- pr_debug("%s: called file = 0x%p\n", __func__, file); +- +- return 0; +-} +- +-/**************************************************************************** +-* +-* vc_mem_get_size +-* +-***************************************************************************/ +- +-static void +-vc_mem_get_size(void) +-{ +-} +- +-/**************************************************************************** +-* +-* vc_mem_get_base +-* +-***************************************************************************/ +- +-static void +-vc_mem_get_base(void) +-{ +-} +- +-/**************************************************************************** +-* +-* vc_mem_get_current_size +-* +-***************************************************************************/ +- +-int +-vc_mem_get_current_size(void) +-{ +- return mm_vc_mem_size; +-} +- +-EXPORT_SYMBOL_GPL(vc_mem_get_current_size); +- +-/**************************************************************************** +-* +-* vc_mem_ioctl +-* +-***************************************************************************/ +- +-static long +-vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +-{ +- int rc = 0; +- +- (void) cmd; +- (void) arg; +- +- pr_debug("%s: called file = 0x%p\n", __func__, file); +- +- switch (cmd) { +- case VC_MEM_IOC_MEM_PHYS_ADDR: +- { +- pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n", +- __func__, (void *) mm_vc_mem_phys_addr); +- +- if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr, +- sizeof (mm_vc_mem_phys_addr)) != 0) { +- rc = -EFAULT; +- } +- break; +- } +- case VC_MEM_IOC_MEM_SIZE: +- { +- // Get the videocore memory size first +- vc_mem_get_size(); +- +- pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__, +- mm_vc_mem_size); +- +- if (copy_to_user((void *) arg, &mm_vc_mem_size, +- sizeof (mm_vc_mem_size)) != 0) { +- rc = -EFAULT; +- } +- break; +- } +- case VC_MEM_IOC_MEM_BASE: +- { +- // Get the videocore memory base +- vc_mem_get_base(); +- +- pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__, +- mm_vc_mem_base); +- +- if (copy_to_user((void *) arg, &mm_vc_mem_base, +- sizeof (mm_vc_mem_base)) != 0) { +- rc = -EFAULT; +- } +- break; +- } +- case VC_MEM_IOC_MEM_LOAD: +- { +- // Get the videocore memory base +- vc_mem_get_base(); +- +- pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__, +- mm_vc_mem_base); +- +- if (copy_to_user((void *) arg, &mm_vc_mem_base, +- sizeof (mm_vc_mem_base)) != 0) { +- rc = -EFAULT; +- } +- break; +- } +- default: +- { +- return -ENOTTY; +- } +- } +- pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc); +- +- return rc; +-} +- +-/**************************************************************************** +-* +-* vc_mem_mmap +-* +-***************************************************************************/ +- +-static int +-vc_mem_mmap(struct file *filp, struct vm_area_struct *vma) +-{ +- int rc = 0; +- unsigned long length = vma->vm_end - vma->vm_start; +- unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; +- +- pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n", +- __func__, (long) vma->vm_start, (long) vma->vm_end, +- (long) vma->vm_pgoff); +- +- if (offset + length > mm_vc_mem_size) { +- pr_err("%s: length %ld is too big\n", __func__, length); +- return -EINVAL; +- } +- // Do not cache the memory map +- vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); +- +- rc = remap_pfn_range(vma, vma->vm_start, +- (mm_vc_mem_phys_addr >> PAGE_SHIFT) + +- vma->vm_pgoff, length, vma->vm_page_prot); +- if (rc != 0) { +- pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc); +- } +- +- return rc; +-} +- +-/**************************************************************************** +-* +-* File Operations for the driver. +-* +-***************************************************************************/ +- +-static const struct file_operations vc_mem_fops = { +- .owner = THIS_MODULE, +- .open = vc_mem_open, +- .release = vc_mem_release, +- .unlocked_ioctl = vc_mem_ioctl, +- .mmap = vc_mem_mmap, +-}; +- +-#ifdef CONFIG_DEBUG_FS +-static void vc_mem_debugfs_deinit(void) +-{ +- debugfs_remove_recursive(vc_mem_debugfs_entry); +- vc_mem_debugfs_entry = NULL; +-} +- +- +-static int vc_mem_debugfs_init( +- struct device *dev) +-{ +- vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL); +- if (!vc_mem_debugfs_entry) { +- dev_warn(dev, "could not create debugfs entry\n"); +- return -EFAULT; +- } +- +- if (!debugfs_create_x32("vc_mem_phys_addr", +- 0444, +- vc_mem_debugfs_entry, +- (u32 *)&mm_vc_mem_phys_addr)) { +- dev_warn(dev, "%s:could not create vc_mem_phys entry\n", +- __func__); +- goto fail; +- } +- +- if (!debugfs_create_x32("vc_mem_size", +- 0444, +- vc_mem_debugfs_entry, +- (u32 *)&mm_vc_mem_size)) { +- dev_warn(dev, "%s:could not create vc_mem_size entry\n", +- __func__); +- goto fail; +- } +- +- if (!debugfs_create_x32("vc_mem_base", +- 0444, +- vc_mem_debugfs_entry, +- (u32 *)&mm_vc_mem_base)) { +- dev_warn(dev, "%s:could not create vc_mem_base entry\n", +- __func__); +- goto fail; +- } +- +- return 0; +- +-fail: +- vc_mem_debugfs_deinit(); +- return -EFAULT; +-} +- +-#endif /* CONFIG_DEBUG_FS */ +- +- +-/**************************************************************************** +-* +-* vc_mem_init +-* +-***************************************************************************/ +- +-static int __init +-vc_mem_init(void) +-{ +- int rc = -EFAULT; +- struct device *dev; +- +- pr_debug("%s: called\n", __func__); +- +- mm_vc_mem_phys_addr = phys_addr; +- mm_vc_mem_size = mem_size; +- mm_vc_mem_base = mem_base; +- +- vc_mem_get_size(); +- +- pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n", +- mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024)); +- +- if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) { +- pr_err("%s: alloc_chrdev_region failed (rc=%d)\n", +- __func__, rc); +- goto out_err; +- } +- +- cdev_init(&vc_mem_cdev, &vc_mem_fops); +- if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) { +- pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc); +- goto out_unregister; +- } +- +- vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME); +- if (IS_ERR(vc_mem_class)) { +- rc = PTR_ERR(vc_mem_class); +- pr_err("%s: class_create failed (rc=%d)\n", __func__, rc); +- goto out_cdev_del; +- } +- +- dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL, +- DRIVER_NAME); +- if (IS_ERR(dev)) { +- rc = PTR_ERR(dev); +- pr_err("%s: device_create failed (rc=%d)\n", __func__, rc); +- goto out_class_destroy; +- } +- +-#ifdef CONFIG_DEBUG_FS +- /* don't fail if the debug entries cannot be created */ +- vc_mem_debugfs_init(dev); +-#endif +- +- vc_mem_inited = 1; +- return 0; +- +- device_destroy(vc_mem_class, vc_mem_devnum); +- +- out_class_destroy: +- class_destroy(vc_mem_class); +- vc_mem_class = NULL; +- +- out_cdev_del: +- cdev_del(&vc_mem_cdev); +- +- out_unregister: +- unregister_chrdev_region(vc_mem_devnum, 1); +- +- out_err: +- return -1; +-} +- +-/**************************************************************************** +-* +-* vc_mem_exit +-* +-***************************************************************************/ +- +-static void __exit +-vc_mem_exit(void) +-{ +- pr_debug("%s: called\n", __func__); +- +- if (vc_mem_inited) { +-#if CONFIG_DEBUG_FS +- vc_mem_debugfs_deinit(); +-#endif +- device_destroy(vc_mem_class, vc_mem_devnum); +- class_destroy(vc_mem_class); +- cdev_del(&vc_mem_cdev); +- unregister_chrdev_region(vc_mem_devnum, 1); +- } +-} +- +-module_init(vc_mem_init); +-module_exit(vc_mem_exit); +-MODULE_LICENSE("GPL"); +-MODULE_AUTHOR("Broadcom Corporation"); +- +-module_param(phys_addr, uint, 0644); +-module_param(mem_size, uint, 0644); +-module_param(mem_base, uint, 0644); +--- a/drivers/char/broadcom/Kconfig ++++ b/drivers/char/broadcom/Kconfig +@@ -7,9 +7,19 @@ menuconfig BRCM_CHAR_DRIVERS + help + Broadcom's char drivers + ++if BRCM_CHAR_DRIVERS ++ + config BCM_VC_CMA + bool "Videocore CMA" +- depends on CMA && BRCM_CHAR_DRIVERS && BCM2708_VCHIQ ++ depends on CMA && BCM2708_VCHIQ + default n + help + Helper for videocore CMA access. ++ ++config BCM2708_VCMEM ++ bool "Videocore Memory" ++ default y ++ help ++ Helper for videocore memory access and total size allocation. ++ ++endif +--- a/drivers/char/broadcom/Makefile ++++ b/drivers/char/broadcom/Makefile +@@ -1 +1,2 @@ + obj-$(CONFIG_BCM_VC_CMA) += vc_cma/ ++obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o +--- /dev/null ++++ b/drivers/char/broadcom/vc_mem.c +@@ -0,0 +1,423 @@ ++/***************************************************************************** ++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "vc-mem" ++ ++// Device (/dev) related variables ++static dev_t vc_mem_devnum = 0; ++static struct class *vc_mem_class = NULL; ++static struct cdev vc_mem_cdev; ++static int vc_mem_inited = 0; ++ ++#ifdef CONFIG_DEBUG_FS ++static struct dentry *vc_mem_debugfs_entry; ++#endif ++ ++/* ++ * Videocore memory addresses and size ++ * ++ * Drivers that wish to know the videocore memory addresses and sizes should ++ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in ++ * headers. This allows the other drivers to not be tied down to a a certain ++ * address/size at compile time. ++ * ++ * In the future, the goal is to have the videocore memory virtual address and ++ * size be calculated at boot time rather than at compile time. The decision of ++ * where the videocore memory resides and its size would be in the hands of the ++ * bootloader (and/or kernel). When that happens, the values of these variables ++ * would be calculated and assigned in the init function. ++ */ ++// in the 2835 VC in mapped above ARM, but ARM has full access to VC space ++unsigned long mm_vc_mem_phys_addr = 0x00000000; ++unsigned int mm_vc_mem_size = 0; ++unsigned int mm_vc_mem_base = 0; ++ ++EXPORT_SYMBOL(mm_vc_mem_phys_addr); ++EXPORT_SYMBOL(mm_vc_mem_size); ++EXPORT_SYMBOL(mm_vc_mem_base); ++ ++static uint phys_addr = 0; ++static uint mem_size = 0; ++static uint mem_base = 0; ++ ++ ++/**************************************************************************** ++* ++* vc_mem_open ++* ++***************************************************************************/ ++ ++static int ++vc_mem_open(struct inode *inode, struct file *file) ++{ ++ (void) inode; ++ (void) file; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_release ++* ++***************************************************************************/ ++ ++static int ++vc_mem_release(struct inode *inode, struct file *file) ++{ ++ (void) inode; ++ (void) file; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_size ++* ++***************************************************************************/ ++ ++static void ++vc_mem_get_size(void) ++{ ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_base ++* ++***************************************************************************/ ++ ++static void ++vc_mem_get_base(void) ++{ ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_current_size ++* ++***************************************************************************/ ++ ++int ++vc_mem_get_current_size(void) ++{ ++ return mm_vc_mem_size; ++} ++ ++EXPORT_SYMBOL_GPL(vc_mem_get_current_size); ++ ++/**************************************************************************** ++* ++* vc_mem_ioctl ++* ++***************************************************************************/ ++ ++static long ++vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int rc = 0; ++ ++ (void) cmd; ++ (void) arg; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ switch (cmd) { ++ case VC_MEM_IOC_MEM_PHYS_ADDR: ++ { ++ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n", ++ __func__, (void *) mm_vc_mem_phys_addr); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr, ++ sizeof (mm_vc_mem_phys_addr)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_SIZE: ++ { ++ // Get the videocore memory size first ++ vc_mem_get_size(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__, ++ mm_vc_mem_size); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_size, ++ sizeof (mm_vc_mem_size)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_BASE: ++ { ++ // Get the videocore memory base ++ vc_mem_get_base(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__, ++ mm_vc_mem_base); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_base, ++ sizeof (mm_vc_mem_base)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_LOAD: ++ { ++ // Get the videocore memory base ++ vc_mem_get_base(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__, ++ mm_vc_mem_base); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_base, ++ sizeof (mm_vc_mem_base)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ default: ++ { ++ return -ENOTTY; ++ } ++ } ++ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc); ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_mmap ++* ++***************************************************************************/ ++ ++static int ++vc_mem_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ int rc = 0; ++ unsigned long length = vma->vm_end - vma->vm_start; ++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; ++ ++ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n", ++ __func__, (long) vma->vm_start, (long) vma->vm_end, ++ (long) vma->vm_pgoff); ++ ++ if (offset + length > mm_vc_mem_size) { ++ pr_err("%s: length %ld is too big\n", __func__, length); ++ return -EINVAL; ++ } ++ // Do not cache the memory map ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ rc = remap_pfn_range(vma, vma->vm_start, ++ (mm_vc_mem_phys_addr >> PAGE_SHIFT) + ++ vma->vm_pgoff, length, vma->vm_page_prot); ++ if (rc != 0) { ++ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc); ++ } ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* File Operations for the driver. ++* ++***************************************************************************/ ++ ++static const struct file_operations vc_mem_fops = { ++ .owner = THIS_MODULE, ++ .open = vc_mem_open, ++ .release = vc_mem_release, ++ .unlocked_ioctl = vc_mem_ioctl, ++ .mmap = vc_mem_mmap, ++}; ++ ++#ifdef CONFIG_DEBUG_FS ++static void vc_mem_debugfs_deinit(void) ++{ ++ debugfs_remove_recursive(vc_mem_debugfs_entry); ++ vc_mem_debugfs_entry = NULL; ++} ++ ++ ++static int vc_mem_debugfs_init( ++ struct device *dev) ++{ ++ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL); ++ if (!vc_mem_debugfs_entry) { ++ dev_warn(dev, "could not create debugfs entry\n"); ++ return -EFAULT; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_phys_addr", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_phys_addr)) { ++ dev_warn(dev, "%s:could not create vc_mem_phys entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_size", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_size)) { ++ dev_warn(dev, "%s:could not create vc_mem_size entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_base", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_base)) { ++ dev_warn(dev, "%s:could not create vc_mem_base entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ return 0; ++ ++fail: ++ vc_mem_debugfs_deinit(); ++ return -EFAULT; ++} ++ ++#endif /* CONFIG_DEBUG_FS */ ++ ++ ++/**************************************************************************** ++* ++* vc_mem_init ++* ++***************************************************************************/ ++ ++static int __init ++vc_mem_init(void) ++{ ++ int rc = -EFAULT; ++ struct device *dev; ++ ++ pr_debug("%s: called\n", __func__); ++ ++ mm_vc_mem_phys_addr = phys_addr; ++ mm_vc_mem_size = mem_size; ++ mm_vc_mem_base = mem_base; ++ ++ vc_mem_get_size(); ++ ++ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n", ++ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024)); ++ ++ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) { ++ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n", ++ __func__, rc); ++ goto out_err; ++ } ++ ++ cdev_init(&vc_mem_cdev, &vc_mem_fops); ++ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) { ++ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc); ++ goto out_unregister; ++ } ++ ++ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME); ++ if (IS_ERR(vc_mem_class)) { ++ rc = PTR_ERR(vc_mem_class); ++ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc); ++ goto out_cdev_del; ++ } ++ ++ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL, ++ DRIVER_NAME); ++ if (IS_ERR(dev)) { ++ rc = PTR_ERR(dev); ++ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc); ++ goto out_class_destroy; ++ } ++ ++#ifdef CONFIG_DEBUG_FS ++ /* don't fail if the debug entries cannot be created */ ++ vc_mem_debugfs_init(dev); ++#endif ++ ++ vc_mem_inited = 1; ++ return 0; ++ ++ device_destroy(vc_mem_class, vc_mem_devnum); ++ ++ out_class_destroy: ++ class_destroy(vc_mem_class); ++ vc_mem_class = NULL; ++ ++ out_cdev_del: ++ cdev_del(&vc_mem_cdev); ++ ++ out_unregister: ++ unregister_chrdev_region(vc_mem_devnum, 1); ++ ++ out_err: ++ return -1; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_exit ++* ++***************************************************************************/ ++ ++static void __exit ++vc_mem_exit(void) ++{ ++ pr_debug("%s: called\n", __func__); ++ ++ if (vc_mem_inited) { ++#if CONFIG_DEBUG_FS ++ vc_mem_debugfs_deinit(); ++#endif ++ device_destroy(vc_mem_class, vc_mem_devnum); ++ class_destroy(vc_mem_class); ++ cdev_del(&vc_mem_cdev); ++ unregister_chrdev_region(vc_mem_devnum, 1); ++ } ++} ++ ++module_init(vc_mem_init); ++module_exit(vc_mem_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); ++ ++module_param(phys_addr, uint, 0644); ++module_param(mem_size, uint, 0644); ++module_param(mem_base, uint, 0644); +--- /dev/null ++++ b/include/linux/broadcom/vc_mem.h +@@ -0,0 +1,35 @@ ++/***************************************************************************** ++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef _VC_MEM_H ++#define _VC_MEM_H ++ ++#include ++ ++#define VC_MEM_IOC_MAGIC 'v' ++ ++#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) ++#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) ++#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int ) ++#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int ) ++ ++#if defined( __KERNEL__ ) ++#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF ++ ++extern unsigned long mm_vc_mem_phys_addr; ++extern unsigned int mm_vc_mem_size; ++extern int vc_mem_get_current_size( void ); ++#endif ++ ++#endif /* _VC_MEM_H */ diff --git a/target/linux/brcm2708/patches-4.1/0014-vcsm-VideoCore-shared-memory-service-for-BCM2835.patch b/target/linux/brcm2708/patches-4.1/0014-vcsm-VideoCore-shared-memory-service-for-BCM2835.patch new file mode 100644 index 0000000..51b0bef --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0014-vcsm-VideoCore-shared-memory-service-for-BCM2835.patch @@ -0,0 +1,4387 @@ +From e56c5f50ab632450c34df97f088f6fe10612ca29 Mon Sep 17 00:00:00 2001 +From: Tim Gover +Date: Tue, 22 Jul 2014 15:41:04 +0100 +Subject: [PATCH 014/203] vcsm: VideoCore shared memory service for BCM2835 + +Add experimental support for the VideoCore shared memory service. +This allows user processes to allocate memory from VideoCore's +GPU relocatable heap and mmap the buffers. Additionally, the memory +handles can passed to other VideoCore services such as MMAL, OpenMax +and DispmanX + +TODO +* This driver was originally released for BCM28155 which has a different + cache architecture to BCM2835. Consequently, in this release only + uncached mappings are supported. However, there's no fundamental + reason which cached mappings cannot be support or BCM2835 +* More refactoring is required to remove the typedefs. +* Re-enable the some of the commented out debug-fs statistics which were + disabled when migrating code from proc-fs. +* There's a lot of code to support sharing of VCSM in order to support + Android. This could probably done more cleanly or perhaps just + removed. + +Signed-off-by: Tim Gover + +config: Disable VC_SM for now to fix hang with cutdown kernel + +vcsm: Use boolean as it cannot be built as module + +On building the bcm_vc_sm as a module we get the following error: + +v7_dma_flush_range and do_munmap are undefined in vc-sm.ko. + +Fix by making it not an option to build as module + +vcsm: Add ioctl for custom cache flushing +--- + arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h | 181 ++ + arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h | 55 + + arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h | 82 + + arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h | 248 ++ + drivers/char/broadcom/Kconfig | 9 + + drivers/char/broadcom/Makefile | 1 + + drivers/char/broadcom/vc_sm/Makefile | 21 + + drivers/char/broadcom/vc_sm/vc_vchi_sm.c | 492 +++ + drivers/char/broadcom/vc_sm/vmcs_sm.c | 3211 ++++++++++++++++++++ + 9 files changed, 4300 insertions(+) + create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h + create mode 100644 arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h + create mode 100644 drivers/char/broadcom/vc_sm/Makefile + create mode 100644 drivers/char/broadcom/vc_sm/vc_vchi_sm.c + create mode 100644 drivers/char/broadcom/vc_sm/vmcs_sm.c + +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h +@@ -0,0 +1,181 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __VC_SM_DEFS_H__INCLUDED__ ++#define __VC_SM_DEFS_H__INCLUDED__ ++ ++/* FourCC code used for VCHI connection */ ++#define VC_SM_SERVER_NAME MAKE_FOURCC("SMEM") ++ ++/* Maximum message length */ ++#define VC_SM_MAX_MSG_LEN (sizeof(VC_SM_MSG_UNION_T) + \ ++ sizeof(VC_SM_MSG_HDR_T)) ++#define VC_SM_MAX_RSP_LEN (sizeof(VC_SM_MSG_UNION_T)) ++ ++/* Resource name maximum size */ ++#define VC_SM_RESOURCE_NAME 32 ++ ++/* All message types supported for HOST->VC direction */ ++typedef enum { ++ /* Allocate shared memory block */ ++ VC_SM_MSG_TYPE_ALLOC, ++ /* Lock allocated shared memory block */ ++ VC_SM_MSG_TYPE_LOCK, ++ /* Unlock allocated shared memory block */ ++ VC_SM_MSG_TYPE_UNLOCK, ++ /* Unlock allocated shared memory block, do not answer command */ ++ VC_SM_MSG_TYPE_UNLOCK_NOANS, ++ /* Free shared memory block */ ++ VC_SM_MSG_TYPE_FREE, ++ /* Resize a shared memory block */ ++ VC_SM_MSG_TYPE_RESIZE, ++ /* Walk the allocated shared memory block(s) */ ++ VC_SM_MSG_TYPE_WALK_ALLOC, ++ ++ /* A previously applied action will need to be reverted */ ++ VC_SM_MSG_TYPE_ACTION_CLEAN, ++ VC_SM_MSG_TYPE_MAX ++} VC_SM_MSG_TYPE; ++ ++/* Type of memory to be allocated */ ++typedef enum { ++ VC_SM_ALLOC_CACHED, ++ VC_SM_ALLOC_NON_CACHED, ++ ++} VC_SM_ALLOC_TYPE_T; ++ ++/* Message header for all messages in HOST->VC direction */ ++typedef struct { ++ int32_t type; ++ uint32_t trans_id; ++ uint8_t body[0]; ++ ++} VC_SM_MSG_HDR_T; ++ ++/* Request to allocate memory (HOST->VC) */ ++typedef struct { ++ /* type of memory to allocate */ ++ VC_SM_ALLOC_TYPE_T type; ++ /* byte amount of data to allocate per unit */ ++ uint32_t base_unit; ++ /* number of unit to allocate */ ++ uint32_t num_unit; ++ /* alignement to be applied on allocation */ ++ uint32_t alignement; ++ /* identity of who allocated this block */ ++ uint32_t allocator; ++ /* resource name (for easier tracking on vc side) */ ++ char name[VC_SM_RESOURCE_NAME]; ++ ++} VC_SM_ALLOC_T; ++ ++/* Result of a requested memory allocation (VC->HOST) */ ++typedef struct { ++ /* Transaction identifier */ ++ uint32_t trans_id; ++ ++ /* Resource handle */ ++ uint32_t res_handle; ++ /* Pointer to resource buffer */ ++ void *res_mem; ++ /* Resource base size (bytes) */ ++ uint32_t res_base_size; ++ /* Resource number */ ++ uint32_t res_num; ++ ++} VC_SM_ALLOC_RESULT_T; ++ ++/* Request to free a previously allocated memory (HOST->VC) */ ++typedef struct { ++ /* Resource handle (returned from alloc) */ ++ uint32_t res_handle; ++ /* Resource buffer (returned from alloc) */ ++ void *res_mem; ++ ++} VC_SM_FREE_T; ++ ++/* Request to lock a previously allocated memory (HOST->VC) */ ++typedef struct { ++ /* Resource handle (returned from alloc) */ ++ uint32_t res_handle; ++ /* Resource buffer (returned from alloc) */ ++ void *res_mem; ++ ++} VC_SM_LOCK_UNLOCK_T; ++ ++/* Request to resize a previously allocated memory (HOST->VC) */ ++typedef struct { ++ /* Resource handle (returned from alloc) */ ++ uint32_t res_handle; ++ /* Resource buffer (returned from alloc) */ ++ void *res_mem; ++ /* Resource *new* size requested (bytes) */ ++ uint32_t res_new_size; ++ ++} VC_SM_RESIZE_T; ++ ++/* Result of a requested memory lock (VC->HOST) */ ++typedef struct { ++ /* Transaction identifier */ ++ uint32_t trans_id; ++ ++ /* Resource handle */ ++ uint32_t res_handle; ++ /* Pointer to resource buffer */ ++ void *res_mem; ++ /* Pointer to former resource buffer if the memory ++ * was reallocated */ ++ void *res_old_mem; ++ ++} VC_SM_LOCK_RESULT_T; ++ ++/* Generic result for a request (VC->HOST) */ ++typedef struct { ++ /* Transaction identifier */ ++ uint32_t trans_id; ++ ++ int32_t success; ++ ++} VC_SM_RESULT_T; ++ ++/* Request to revert a previously applied action (HOST->VC) */ ++typedef struct { ++ /* Action of interest */ ++ VC_SM_MSG_TYPE res_action; ++ /* Transaction identifier for the action of interest */ ++ uint32_t action_trans_id; ++ ++} VC_SM_ACTION_CLEAN_T; ++ ++/* Request to remove all data associated with a given allocator (HOST->VC) */ ++typedef struct { ++ /* Allocator identifier */ ++ uint32_t allocator; ++ ++} VC_SM_FREE_ALL_T; ++ ++/* Union of ALL messages */ ++typedef union { ++ VC_SM_ALLOC_T alloc; ++ VC_SM_ALLOC_RESULT_T alloc_result; ++ VC_SM_FREE_T free; ++ VC_SM_ACTION_CLEAN_T action_clean; ++ VC_SM_RESIZE_T resize; ++ VC_SM_LOCK_RESULT_T lock_result; ++ VC_SM_RESULT_T result; ++ VC_SM_FREE_ALL_T free_all; ++ ++} VC_SM_MSG_UNION_T; ++ ++#endif /* __VC_SM_DEFS_H__INCLUDED__ */ +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h +@@ -0,0 +1,55 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __VC_SM_KNL_H__INCLUDED__ ++#define __VC_SM_KNL_H__INCLUDED__ ++ ++#if !defined(__KERNEL__) ++#error "This interface is for kernel use only..." ++#endif ++ ++/* Type of memory to be locked (ie mapped) */ ++typedef enum { ++ VC_SM_LOCK_CACHED, ++ VC_SM_LOCK_NON_CACHED, ++ ++} VC_SM_LOCK_CACHE_MODE_T; ++ ++/* Allocate a shared memory handle and block. ++*/ ++int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle); ++ ++/* Free a previously allocated shared memory handle and block. ++*/ ++int vc_sm_free(int handle); ++ ++/* Lock a memory handle for use by kernel. ++*/ ++int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode, ++ long unsigned int *data); ++ ++/* Unlock a memory handle in use by kernel. ++*/ ++int vc_sm_unlock(int handle, int flush, int no_vc_unlock); ++ ++/* Get an internal resource handle mapped from the external one. ++*/ ++int vc_sm_int_handle(int handle); ++ ++/* Map a shared memory region for use by kernel. ++*/ ++int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode, ++ long unsigned int *data); ++ ++#endif /* __VC_SM_KNL_H__INCLUDED__ */ +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h +@@ -0,0 +1,82 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __VC_VCHI_SM_H__INCLUDED__ ++#define __VC_VCHI_SM_H__INCLUDED__ ++ ++#include "interface/vchi/vchi.h" ++ ++#include "vc_sm_defs.h" ++ ++/* Forward declare. ++*/ ++typedef struct sm_instance *VC_VCHI_SM_HANDLE_T; ++ ++/* Initialize the shared memory service, opens up vchi connection to talk to it. ++*/ ++VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance, ++ VCHI_CONNECTION_T **vchi_connections, ++ uint32_t num_connections); ++ ++/* Terminates the shared memory service. ++*/ ++int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle); ++ ++/* Ask the shared memory service to allocate some memory on videocre and ++** return the result of this allocation (which upon success will be a pointer ++** to some memory in videocore space). ++*/ ++int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_ALLOC_T *alloc, ++ VC_SM_ALLOC_RESULT_T *alloc_result, uint32_t *trans_id); ++ ++/* Ask the shared memory service to free up some memory that was previously ++** allocated by the vc_vchi_sm_alloc function call. ++*/ ++int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_FREE_T *free, uint32_t *trans_id); ++ ++/* Ask the shared memory service to lock up some memory that was previously ++** allocated by the vc_vchi_sm_alloc function call. ++*/ ++int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_LOCK_UNLOCK_T *lock_unlock, ++ VC_SM_LOCK_RESULT_T *lock_result, uint32_t *trans_id); ++ ++/* Ask the shared memory service to unlock some memory that was previously ++** allocated by the vc_vchi_sm_alloc function call. ++*/ ++int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_LOCK_UNLOCK_T *lock_unlock, ++ uint32_t *trans_id, uint8_t wait_reply); ++ ++/* Ask the shared memory service to resize some memory that was previously ++** allocated by the vc_vchi_sm_alloc function call. ++*/ ++int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_RESIZE_T *resize, uint32_t *trans_id); ++ ++/* Walk the allocated resources on the videocore side, the allocation will ++** show up in the log. This is purely for debug/information and takes no ++** specific actions. ++*/ ++int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle); ++ ++/* Clean up following a previously interrupted action which left the system ++** in a bad state of some sort. ++*/ ++int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_ACTION_CLEAN_T *action_clean); ++ ++#endif /* __VC_VCHI_SM_H__INCLUDED__ */ +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h +@@ -0,0 +1,248 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++* ++*****************************************************************************/ ++ ++#if !defined(__VMCS_SM_IOCTL_H__INCLUDED__) ++#define __VMCS_SM_IOCTL_H__INCLUDED__ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#if defined(__KERNEL__) ++#include /* Needed for standard types */ ++#else ++#include ++#endif ++ ++#include ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++#define VMCS_SM_RESOURCE_NAME 32 ++#define VMCS_SM_RESOURCE_NAME_DEFAULT "sm-host-resource" ++ ++/* Type define used to create unique IOCTL number */ ++#define VMCS_SM_MAGIC_TYPE 'I' ++ ++/* IOCTL commands */ ++enum vmcs_sm_cmd_e { ++ VMCS_SM_CMD_ALLOC = 0x5A, /* Start at 0x5A arbitrarily */ ++ VMCS_SM_CMD_ALLOC_SHARE, ++ VMCS_SM_CMD_LOCK, ++ VMCS_SM_CMD_LOCK_CACHE, ++ VMCS_SM_CMD_UNLOCK, ++ VMCS_SM_CMD_RESIZE, ++ VMCS_SM_CMD_UNMAP, ++ VMCS_SM_CMD_FREE, ++ VMCS_SM_CMD_FLUSH, ++ VMCS_SM_CMD_INVALID, ++ ++ VMCS_SM_CMD_SIZE_USR_HANDLE, ++ VMCS_SM_CMD_CHK_USR_HANDLE, ++ ++ VMCS_SM_CMD_MAPPED_USR_HANDLE, ++ VMCS_SM_CMD_MAPPED_USR_ADDRESS, ++ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR, ++ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL, ++ VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL, ++ ++ VMCS_SM_CMD_VC_WALK_ALLOC, ++ VMCS_SM_CMD_HOST_WALK_MAP, ++ VMCS_SM_CMD_HOST_WALK_PID_ALLOC, ++ VMCS_SM_CMD_HOST_WALK_PID_MAP, ++ ++ VMCS_SM_CMD_CLEAN_INVALID, ++ ++ VMCS_SM_CMD_LAST /* Do no delete */ ++}; ++ ++/* Cache type supported, conveniently matches the user space definition in ++** user-vcsm.h. ++*/ ++enum vmcs_sm_cache_e { ++ VMCS_SM_CACHE_NONE, ++ VMCS_SM_CACHE_HOST, ++ VMCS_SM_CACHE_VC, ++ VMCS_SM_CACHE_BOTH, ++}; ++ ++/* IOCTL Data structures */ ++struct vmcs_sm_ioctl_alloc { ++ /* user -> kernel */ ++ unsigned int size; ++ unsigned int num; ++ enum vmcs_sm_cache_e cached; ++ char name[VMCS_SM_RESOURCE_NAME]; ++ ++ /* kernel -> user */ ++ unsigned int handle; ++ /* unsigned int base_addr; */ ++}; ++ ++struct vmcs_sm_ioctl_alloc_share { ++ /* user -> kernel */ ++ unsigned int handle; ++ unsigned int size; ++}; ++ ++struct vmcs_sm_ioctl_free { ++ /* user -> kernel */ ++ unsigned int handle; ++ /* unsigned int base_addr; */ ++}; ++ ++struct vmcs_sm_ioctl_lock_unlock { ++ /* user -> kernel */ ++ unsigned int handle; ++ ++ /* kernel -> user */ ++ unsigned int addr; ++}; ++ ++struct vmcs_sm_ioctl_lock_cache { ++ /* user -> kernel */ ++ unsigned int handle; ++ enum vmcs_sm_cache_e cached; ++}; ++ ++struct vmcs_sm_ioctl_resize { ++ /* user -> kernel */ ++ unsigned int handle; ++ unsigned int new_size; ++ ++ /* kernel -> user */ ++ unsigned int old_size; ++}; ++ ++struct vmcs_sm_ioctl_map { ++ /* user -> kernel */ ++ /* and kernel -> user */ ++ unsigned int pid; ++ unsigned int handle; ++ unsigned int addr; ++ ++ /* kernel -> user */ ++ unsigned int size; ++}; ++ ++struct vmcs_sm_ioctl_walk { ++ /* user -> kernel */ ++ unsigned int pid; ++}; ++ ++struct vmcs_sm_ioctl_chk { ++ /* user -> kernel */ ++ unsigned int handle; ++ ++ /* kernel -> user */ ++ unsigned int addr; ++ unsigned int size; ++ enum vmcs_sm_cache_e cache; ++}; ++ ++struct vmcs_sm_ioctl_size { ++ /* user -> kernel */ ++ unsigned int handle; ++ ++ /* kernel -> user */ ++ unsigned int size; ++}; ++ ++struct vmcs_sm_ioctl_cache { ++ /* user -> kernel */ ++ unsigned int handle; ++ unsigned int addr; ++ unsigned int size; ++}; ++ ++struct vmcs_sm_ioctl_clean_invalid { ++ /* user -> kernel */ ++ struct { ++ unsigned int cmd; ++ unsigned int handle; ++ unsigned int addr; ++ unsigned int size; ++ } s[8]; ++}; ++ ++/* IOCTL numbers */ ++#define VMCS_SM_IOCTL_MEM_ALLOC\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC,\ ++ struct vmcs_sm_ioctl_alloc) ++#define VMCS_SM_IOCTL_MEM_ALLOC_SHARE\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC_SHARE,\ ++ struct vmcs_sm_ioctl_alloc_share) ++#define VMCS_SM_IOCTL_MEM_LOCK\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK,\ ++ struct vmcs_sm_ioctl_lock_unlock) ++#define VMCS_SM_IOCTL_MEM_LOCK_CACHE\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK_CACHE,\ ++ struct vmcs_sm_ioctl_lock_cache) ++#define VMCS_SM_IOCTL_MEM_UNLOCK\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_UNLOCK,\ ++ struct vmcs_sm_ioctl_lock_unlock) ++#define VMCS_SM_IOCTL_MEM_RESIZE\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_RESIZE,\ ++ struct vmcs_sm_ioctl_resize) ++#define VMCS_SM_IOCTL_MEM_FREE\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FREE,\ ++ struct vmcs_sm_ioctl_free) ++#define VMCS_SM_IOCTL_MEM_FLUSH\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FLUSH,\ ++ struct vmcs_sm_ioctl_cache) ++#define VMCS_SM_IOCTL_MEM_INVALID\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_INVALID,\ ++ struct vmcs_sm_ioctl_cache) ++#define VMCS_SM_IOCTL_MEM_CLEAN_INVALID\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CLEAN_INVALID,\ ++ struct vmcs_sm_ioctl_clean_invalid) ++ ++#define VMCS_SM_IOCTL_SIZE_USR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_SIZE_USR_HANDLE,\ ++ struct vmcs_sm_ioctl_size) ++#define VMCS_SM_IOCTL_CHK_USR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CHK_USR_HANDLE,\ ++ struct vmcs_sm_ioctl_chk) ++ ++#define VMCS_SM_IOCTL_MAP_USR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_HANDLE,\ ++ struct vmcs_sm_ioctl_map) ++#define VMCS_SM_IOCTL_MAP_USR_ADDRESS\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_ADDRESS,\ ++ struct vmcs_sm_ioctl_map) ++#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_ADDR\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,\ ++ struct vmcs_sm_ioctl_map) ++#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,\ ++ struct vmcs_sm_ioctl_map) ++#define VMCS_SM_IOCTL_MAP_VC_ADDR_FR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,\ ++ struct vmcs_sm_ioctl_map) ++ ++#define VMCS_SM_IOCTL_VC_WALK_ALLOC\ ++ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_VC_WALK_ALLOC) ++#define VMCS_SM_IOCTL_HOST_WALK_MAP\ ++ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_MAP) ++#define VMCS_SM_IOCTL_HOST_WALK_PID_ALLOC\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_ALLOC,\ ++ struct vmcs_sm_ioctl_walk) ++#define VMCS_SM_IOCTL_HOST_WALK_PID_MAP\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_MAP,\ ++ struct vmcs_sm_ioctl_walk) ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++#endif /* __VMCS_SM_IOCTL_H__INCLUDED__ */ +--- a/drivers/char/broadcom/Kconfig ++++ b/drivers/char/broadcom/Kconfig +@@ -23,3 +23,12 @@ config BCM2708_VCMEM + Helper for videocore memory access and total size allocation. + + endif ++ ++config BCM_VC_SM ++ bool "VMCS Shared Memory" ++ depends on BCM2708_VCHIQ ++ select BCM2708_VCMEM ++ default n ++ help ++ Support for the VC shared memory on the Broadcom reference ++ design. Uses the VCHIQ stack. +--- a/drivers/char/broadcom/Makefile ++++ b/drivers/char/broadcom/Makefile +@@ -1,2 +1,3 @@ + obj-$(CONFIG_BCM_VC_CMA) += vc_cma/ + obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o ++obj-$(CONFIG_BCM_VC_SM) += vc_sm/ +--- /dev/null ++++ b/drivers/char/broadcom/vc_sm/Makefile +@@ -0,0 +1,21 @@ ++EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2 ++ ++EXTRA_CFLAGS += -I"./arch/arm/mach-bcm2708/include/mach" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchi" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm" ++EXTRA_CFLAGS += -I"$(srctree)/fs/" ++ ++EXTRA_CFLAGS += -DOS_ASSERT_FAILURE ++EXTRA_CFLAGS += -D__STDC_VERSION=199901L ++EXTRA_CFLAGS += -D__STDC_VERSION__=199901L ++EXTRA_CFLAGS += -D__VCCOREVER__=0 ++EXTRA_CFLAGS += -D__KERNEL__ ++EXTRA_CFLAGS += -D__linux__ ++EXTRA_CFLAGS += -Werror ++ ++obj-$(CONFIG_BCM_VC_SM) := vc-sm.o ++ ++vc-sm-objs := \ ++ vmcs_sm.o \ ++ vc_vchi_sm.o +--- /dev/null ++++ b/drivers/char/broadcom/vc_sm/vc_vchi_sm.c +@@ -0,0 +1,492 @@ ++/***************************************************************************** ++* Copyright 2011-2012 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/* ---- Include Files ----------------------------------------------------- */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vc_vchi_sm.h" ++ ++#define VC_SM_VER 1 ++#define VC_SM_MIN_VER 0 ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++/* Command blocks come from a pool */ ++#define SM_MAX_NUM_CMD_RSP_BLKS 32 ++ ++struct sm_cmd_rsp_blk { ++ struct list_head head; /* To create lists */ ++ struct semaphore sema; /* To be signaled when the response is there */ ++ ++ uint16_t id; ++ uint16_t length; ++ ++ uint8_t msg[VC_SM_MAX_MSG_LEN]; ++ ++ uint32_t wait:1; ++ uint32_t sent:1; ++ uint32_t alloc:1; ++ ++}; ++ ++struct sm_instance { ++ uint32_t num_connections; ++ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS]; ++ struct task_struct *io_thread; ++ struct semaphore io_sema; ++ ++ uint32_t trans_id; ++ ++ struct mutex lock; ++ struct list_head cmd_list; ++ struct list_head rsp_list; ++ struct list_head dead_list; ++ ++ struct sm_cmd_rsp_blk free_blk[SM_MAX_NUM_CMD_RSP_BLKS]; ++ struct list_head free_list; ++ struct mutex free_lock; ++ struct semaphore free_sema; ++ ++}; ++ ++/* ---- Private Variables ------------------------------------------------ */ ++ ++/* ---- Private Function Prototypes -------------------------------------- */ ++ ++/* ---- Private Functions ------------------------------------------------ */ ++static struct ++sm_cmd_rsp_blk *vc_vchi_cmd_create(struct sm_instance *instance, ++ VC_SM_MSG_TYPE id, void *msg, ++ uint32_t size, int wait) ++{ ++ struct sm_cmd_rsp_blk *blk; ++ VC_SM_MSG_HDR_T *hdr; ++ ++ if (down_interruptible(&instance->free_sema)) { ++ blk = kmalloc(sizeof(*blk), GFP_KERNEL); ++ if (!blk) ++ return NULL; ++ ++ blk->alloc = 1; ++ sema_init(&blk->sema, 0); ++ } else { ++ mutex_lock(&instance->free_lock); ++ blk = ++ list_first_entry(&instance->free_list, ++ struct sm_cmd_rsp_blk, head); ++ list_del(&blk->head); ++ mutex_unlock(&instance->free_lock); ++ } ++ ++ blk->sent = 0; ++ blk->wait = wait; ++ blk->length = sizeof(*hdr) + size; ++ ++ hdr = (VC_SM_MSG_HDR_T *) blk->msg; ++ hdr->type = id; ++ mutex_lock(&instance->lock); ++ hdr->trans_id = blk->id = ++instance->trans_id; ++ mutex_unlock(&instance->lock); ++ ++ if (size) ++ memcpy(hdr->body, msg, size); ++ ++ return blk; ++} ++ ++static void ++vc_vchi_cmd_delete(struct sm_instance *instance, struct sm_cmd_rsp_blk *blk) ++{ ++ if (blk->alloc) { ++ kfree(blk); ++ return; ++ } ++ ++ mutex_lock(&instance->free_lock); ++ list_add(&blk->head, &instance->free_list); ++ mutex_unlock(&instance->free_lock); ++ up(&instance->free_sema); ++} ++ ++static int vc_vchi_sm_videocore_io(void *arg) ++{ ++ struct sm_instance *instance = arg; ++ struct sm_cmd_rsp_blk *cmd = NULL, *cmd_tmp; ++ VC_SM_RESULT_T *reply; ++ uint32_t reply_len; ++ int32_t status; ++ int svc_use = 1; ++ ++ while (1) { ++ if (svc_use) ++ vchi_service_release(instance->vchi_handle[0]); ++ svc_use = 0; ++ if (!down_interruptible(&instance->io_sema)) { ++ vchi_service_use(instance->vchi_handle[0]); ++ svc_use = 1; ++ ++ do { ++ unsigned int flags; ++ /* ++ * Get new command and move it to response list ++ */ ++ mutex_lock(&instance->lock); ++ if (list_empty(&instance->cmd_list)) { ++ /* no more commands to process */ ++ mutex_unlock(&instance->lock); ++ break; ++ } ++ cmd = ++ list_first_entry(&instance->cmd_list, ++ struct sm_cmd_rsp_blk, ++ head); ++ list_move(&cmd->head, &instance->rsp_list); ++ cmd->sent = 1; ++ mutex_unlock(&instance->lock); ++ ++ /* Send the command */ ++ flags = VCHI_FLAGS_BLOCK_UNTIL_QUEUED; ++ status = vchi_msg_queue( ++ instance->vchi_handle[0], ++ cmd->msg, cmd->length, ++ flags, NULL); ++ if (status) { ++ pr_err("%s: failed to queue message (%d)", ++ __func__, status); ++ } ++ ++ /* If no reply is needed then we're done */ ++ if (!cmd->wait) { ++ mutex_lock(&instance->lock); ++ list_del(&cmd->head); ++ mutex_unlock(&instance->lock); ++ vc_vchi_cmd_delete(instance, cmd); ++ continue; ++ } ++ ++ if (status) { ++ up(&cmd->sema); ++ continue; ++ } ++ ++ } while (1); ++ ++ while (!vchi_msg_peek ++ (instance->vchi_handle[0], (void **)&reply, ++ &reply_len, VCHI_FLAGS_NONE)) { ++ mutex_lock(&instance->lock); ++ list_for_each_entry(cmd, &instance->rsp_list, ++ head) { ++ if (cmd->id == reply->trans_id) ++ break; ++ } ++ mutex_unlock(&instance->lock); ++ ++ if (&cmd->head == &instance->rsp_list) { ++ pr_debug("%s: received response %u, throw away...", ++ __func__, reply->trans_id); ++ } else if (reply_len > sizeof(cmd->msg)) { ++ pr_err("%s: reply too big (%u) %u, throw away...", ++ __func__, reply_len, ++ reply->trans_id); ++ } else { ++ memcpy(cmd->msg, reply, reply_len); ++ up(&cmd->sema); ++ } ++ ++ vchi_msg_remove(instance->vchi_handle[0]); ++ } ++ ++ /* Go through the dead list and free them */ ++ mutex_lock(&instance->lock); ++ list_for_each_entry_safe(cmd, cmd_tmp, ++ &instance->dead_list, head) { ++ list_del(&cmd->head); ++ vc_vchi_cmd_delete(instance, cmd); ++ } ++ mutex_unlock(&instance->lock); ++ } ++ } ++ ++ return 0; ++} ++ ++static void vc_sm_vchi_callback(void *param, ++ const VCHI_CALLBACK_REASON_T reason, ++ void *msg_handle) ++{ ++ struct sm_instance *instance = param; ++ ++ (void)msg_handle; ++ ++ switch (reason) { ++ case VCHI_CALLBACK_MSG_AVAILABLE: ++ up(&instance->io_sema); ++ break; ++ ++ case VCHI_CALLBACK_SERVICE_CLOSED: ++ pr_info("%s: service CLOSED!!", __func__); ++ default: ++ break; ++ } ++} ++ ++VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance, ++ VCHI_CONNECTION_T **vchi_connections, ++ uint32_t num_connections) ++{ ++ uint32_t i; ++ struct sm_instance *instance; ++ int status; ++ ++ pr_debug("%s: start", __func__); ++ ++ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) { ++ pr_err("%s: unsupported number of connections %u (max=%u)", ++ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS); ++ ++ goto err_null; ++ } ++ /* Allocate memory for this instance */ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ ++ /* Misc initialisations */ ++ mutex_init(&instance->lock); ++ sema_init(&instance->io_sema, 0); ++ INIT_LIST_HEAD(&instance->cmd_list); ++ INIT_LIST_HEAD(&instance->rsp_list); ++ INIT_LIST_HEAD(&instance->dead_list); ++ INIT_LIST_HEAD(&instance->free_list); ++ sema_init(&instance->free_sema, SM_MAX_NUM_CMD_RSP_BLKS); ++ mutex_init(&instance->free_lock); ++ for (i = 0; i < SM_MAX_NUM_CMD_RSP_BLKS; i++) { ++ sema_init(&instance->free_blk[i].sema, 0); ++ list_add(&instance->free_blk[i].head, &instance->free_list); ++ } ++ ++ /* Open the VCHI service connections */ ++ instance->num_connections = num_connections; ++ for (i = 0; i < num_connections; i++) { ++ SERVICE_CREATION_T params = { ++ VCHI_VERSION_EX(VC_SM_VER, VC_SM_MIN_VER), ++ VC_SM_SERVER_NAME, ++ vchi_connections[i], ++ 0, ++ 0, ++ vc_sm_vchi_callback, ++ instance, ++ 0, ++ 0, ++ 0, ++ }; ++ ++ status = vchi_service_open(vchi_instance, ++ ¶ms, &instance->vchi_handle[i]); ++ if (status) { ++ pr_err("%s: failed to open VCHI service (%d)", ++ __func__, status); ++ ++ goto err_close_services; ++ } ++ } ++ ++ /* Create the thread which takes care of all io to/from videoocore. */ ++ instance->io_thread = kthread_create(&vc_vchi_sm_videocore_io, ++ (void *)instance, "SMIO"); ++ if (instance->io_thread == NULL) { ++ pr_err("%s: failed to create SMIO thread", __func__); ++ ++ goto err_close_services; ++ } ++ set_user_nice(instance->io_thread, -10); ++ wake_up_process(instance->io_thread); ++ ++ pr_debug("%s: success - instance 0x%x", __func__, (unsigned)instance); ++ return instance; ++ ++err_close_services: ++ for (i = 0; i < instance->num_connections; i++) { ++ if (instance->vchi_handle[i] != NULL) ++ vchi_service_close(instance->vchi_handle[i]); ++ } ++ kfree(instance); ++err_null: ++ pr_debug("%s: FAILED", __func__); ++ return NULL; ++} ++ ++int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle) ++{ ++ struct sm_instance *instance; ++ uint32_t i; ++ ++ if (handle == NULL) { ++ pr_err("%s: invalid pointer to handle %p", __func__, handle); ++ goto lock; ++ } ++ ++ if (*handle == NULL) { ++ pr_err("%s: invalid handle %p", __func__, *handle); ++ goto lock; ++ } ++ ++ instance = *handle; ++ ++ /* Close all VCHI service connections */ ++ for (i = 0; i < instance->num_connections; i++) { ++ int32_t success; ++ vchi_service_use(instance->vchi_handle[i]); ++ ++ success = vchi_service_close(instance->vchi_handle[i]); ++ } ++ ++ kfree(instance); ++ ++ *handle = NULL; ++ return 0; ++ ++lock: ++ return -EINVAL; ++} ++ ++int vc_vchi_sm_send_msg(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_MSG_TYPE msg_id, ++ void *msg, uint32_t msg_size, ++ void *result, uint32_t result_size, ++ uint32_t *cur_trans_id, uint8_t wait_reply) ++{ ++ int status = 0; ++ struct sm_instance *instance = handle; ++ struct sm_cmd_rsp_blk *cmd_blk; ++ ++ if (handle == NULL) { ++ pr_err("%s: invalid handle", __func__); ++ return -EINVAL; ++ } ++ if (msg == NULL) { ++ pr_err("%s: invalid msg pointer", __func__); ++ return -EINVAL; ++ } ++ ++ cmd_blk = ++ vc_vchi_cmd_create(instance, msg_id, msg, msg_size, wait_reply); ++ if (cmd_blk == NULL) { ++ pr_err("[%s]: failed to allocate global tracking resource", ++ __func__); ++ return -ENOMEM; ++ } ++ ++ if (cur_trans_id != NULL) ++ *cur_trans_id = cmd_blk->id; ++ ++ mutex_lock(&instance->lock); ++ list_add_tail(&cmd_blk->head, &instance->cmd_list); ++ mutex_unlock(&instance->lock); ++ up(&instance->io_sema); ++ ++ if (!wait_reply) ++ /* We're done */ ++ return 0; ++ ++ /* Wait for the response */ ++ if (down_interruptible(&cmd_blk->sema)) { ++ mutex_lock(&instance->lock); ++ if (!cmd_blk->sent) { ++ list_del(&cmd_blk->head); ++ mutex_unlock(&instance->lock); ++ vc_vchi_cmd_delete(instance, cmd_blk); ++ return -ENXIO; ++ } ++ mutex_unlock(&instance->lock); ++ ++ mutex_lock(&instance->lock); ++ list_move(&cmd_blk->head, &instance->dead_list); ++ mutex_unlock(&instance->lock); ++ up(&instance->io_sema); ++ return -EINTR; /* We're done */ ++ } ++ ++ if (result && result_size) { ++ memcpy(result, cmd_blk->msg, result_size); ++ } else { ++ VC_SM_RESULT_T *res = (VC_SM_RESULT_T *) cmd_blk->msg; ++ status = (res->success == 0) ? 0 : -ENXIO; ++ } ++ ++ mutex_lock(&instance->lock); ++ list_del(&cmd_blk->head); ++ mutex_unlock(&instance->lock); ++ vc_vchi_cmd_delete(instance, cmd_blk); ++ return status; ++} ++ ++int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, VC_SM_ALLOC_T *msg, ++ VC_SM_ALLOC_RESULT_T *result, uint32_t *cur_trans_id) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ALLOC, ++ msg, sizeof(*msg), result, sizeof(*result), ++ cur_trans_id, 1); ++} ++ ++int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_FREE_T *msg, uint32_t *cur_trans_id) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_FREE, ++ msg, sizeof(*msg), 0, 0, cur_trans_id, 0); ++} ++ ++int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_LOCK_UNLOCK_T *msg, ++ VC_SM_LOCK_RESULT_T *result, uint32_t *cur_trans_id) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_LOCK, ++ msg, sizeof(*msg), result, sizeof(*result), ++ cur_trans_id, 1); ++} ++ ++int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_LOCK_UNLOCK_T *msg, ++ uint32_t *cur_trans_id, uint8_t wait_reply) ++{ ++ return vc_vchi_sm_send_msg(handle, wait_reply ? ++ VC_SM_MSG_TYPE_UNLOCK : ++ VC_SM_MSG_TYPE_UNLOCK_NOANS, msg, ++ sizeof(*msg), 0, 0, cur_trans_id, ++ wait_reply); ++} ++ ++int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, VC_SM_RESIZE_T *msg, ++ uint32_t *cur_trans_id) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_RESIZE, ++ msg, sizeof(*msg), 0, 0, cur_trans_id, 1); ++} ++ ++int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_WALK_ALLOC, ++ 0, 0, 0, 0, 0, 0); ++} ++ ++int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, VC_SM_ACTION_CLEAN_T *msg) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ACTION_CLEAN, ++ msg, sizeof(*msg), 0, 0, 0, 0); ++} +--- /dev/null ++++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c +@@ -0,0 +1,3211 @@ ++/***************************************************************************** ++* Copyright 2011-2012 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vchiq_connected.h" ++#include "vc_vchi_sm.h" ++ ++#include ++#include "vc_sm_knl.h" ++ ++/* ---- Private Constants and Types --------------------------------------- */ ++ ++#define DEVICE_NAME "vcsm" ++#define DEVICE_MINOR 0 ++ ++#define VC_SM_DIR_ROOT_NAME "vc-smem" ++#define VC_SM_DIR_ALLOC_NAME "alloc" ++#define VC_SM_STATE "state" ++#define VC_SM_STATS "statistics" ++#define VC_SM_RESOURCES "resources" ++#define VC_SM_DEBUG "debug" ++#define VC_SM_WRITE_BUF_SIZE 128 ++ ++/* Statistics tracked per resource and globally. ++*/ ++enum SM_STATS_T { ++ /* Attempt. */ ++ ALLOC, ++ FREE, ++ LOCK, ++ UNLOCK, ++ MAP, ++ FLUSH, ++ INVALID, ++ ++ END_ATTEMPT, ++ ++ /* Failure. */ ++ ALLOC_FAIL, ++ FREE_FAIL, ++ LOCK_FAIL, ++ UNLOCK_FAIL, ++ MAP_FAIL, ++ FLUSH_FAIL, ++ INVALID_FAIL, ++ ++ END_ALL, ++ ++}; ++ ++static const char *const sm_stats_human_read[] = { ++ "Alloc", ++ "Free", ++ "Lock", ++ "Unlock", ++ "Map", ++ "Cache Flush", ++ "Cache Invalidate", ++}; ++ ++typedef int (*VC_SM_SHOW) (struct seq_file *s, void *v); ++struct SM_PDE_T { ++ VC_SM_SHOW show; /* Debug fs function hookup. */ ++ struct dentry *dir_entry; /* Debug fs directory entry. */ ++ void *priv_data; /* Private data */ ++ ++}; ++ ++/* Single resource allocation tracked for all devices. ++*/ ++struct sm_mmap { ++ struct list_head map_list; /* Linked list of maps. */ ++ ++ struct SM_RESOURCE_T *resource; /* Pointer to the resource. */ ++ ++ pid_t res_pid; /* PID owning that resource. */ ++ unsigned int res_vc_hdl; /* Resource handle (videocore). */ ++ unsigned int res_usr_hdl; /* Resource handle (user). */ ++ ++ long unsigned int res_addr; /* Mapped virtual address. */ ++ struct vm_area_struct *vma; /* VM area for this mapping. */ ++ unsigned int ref_count; /* Reference count to this vma. */ ++ ++ /* Used to link maps associated with a resource. */ ++ struct list_head resource_map_list; ++}; ++ ++/* Single resource allocation tracked for each opened device. ++*/ ++struct SM_RESOURCE_T { ++ struct list_head resource_list; /* List of resources. */ ++ struct list_head global_resource_list; /* Global list of resources. */ ++ ++ pid_t pid; /* PID owning that resource. */ ++ uint32_t res_guid; /* Unique identifier. */ ++ uint32_t lock_count; /* Lock count for this resource. */ ++ uint32_t ref_count; /* Ref count for this resource. */ ++ ++ uint32_t res_handle; /* Resource allocation handle. */ ++ void *res_base_mem; /* Resource base memory address. */ ++ uint32_t res_size; /* Resource size allocated. */ ++ enum vmcs_sm_cache_e res_cached; /* Resource cache type. */ ++ struct SM_RESOURCE_T *res_shared; /* Shared resource */ ++ ++ enum SM_STATS_T res_stats[END_ALL]; /* Resource statistics. */ ++ ++ uint8_t map_count; /* Counter of mappings for this resource. */ ++ struct list_head map_list; /* Maps associated with a resource. */ ++ ++ struct SM_PRIV_DATA_T *private; ++}; ++ ++/* Private file data associated with each opened device. ++*/ ++struct SM_PRIV_DATA_T { ++ struct list_head resource_list; /* List of resources. */ ++ ++ pid_t pid; /* PID of creator. */ ++ ++ struct dentry *dir_pid; /* Debug fs entries root. */ ++ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */ ++ struct SM_PDE_T dir_res; /* Debug fs resource sub-tree. */ ++ ++ int restart_sys; /* Tracks restart on interrupt. */ ++ VC_SM_MSG_TYPE int_action; /* Interrupted action. */ ++ uint32_t int_trans_id; /* Interrupted transaction. */ ++ ++}; ++ ++/* Global state information. ++*/ ++struct SM_STATE_T { ++ VC_VCHI_SM_HANDLE_T sm_handle; /* Handle for videocore service. */ ++ struct dentry *dir_root; /* Debug fs entries root. */ ++ struct dentry *dir_alloc; /* Debug fs entries allocations. */ ++ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */ ++ struct SM_PDE_T dir_state; /* Debug fs entries state sub-tree. */ ++ struct dentry *debug; /* Debug fs entries debug. */ ++ ++ struct mutex map_lock; /* Global map lock. */ ++ struct list_head map_list; /* List of maps. */ ++ struct list_head resource_list; /* List of resources. */ ++ ++ enum SM_STATS_T deceased[END_ALL]; /* Natural termination stats. */ ++ enum SM_STATS_T terminated[END_ALL]; /* Forced termination stats. */ ++ uint32_t res_deceased_cnt; /* Natural termination counter. */ ++ uint32_t res_terminated_cnt; /* Forced termination counter. */ ++ ++ struct cdev sm_cdev; /* Device. */ ++ dev_t sm_devid; /* Device identifier. */ ++ struct class *sm_class; /* Class. */ ++ struct device *sm_dev; /* Device. */ ++ ++ struct SM_PRIV_DATA_T *data_knl; /* Kernel internal data tracking. */ ++ ++ struct mutex lock; /* Global lock. */ ++ uint32_t guid; /* GUID (next) tracker. */ ++ ++}; ++ ++/* ---- Private Variables ----------------------------------------------- */ ++ ++static struct SM_STATE_T *sm_state; ++static int sm_inited; ++ ++static const char *const sm_cache_map_vector[] = { ++ "(null)", ++ "host", ++ "videocore", ++ "host+videocore", ++}; ++ ++/* ---- Private Function Prototypes -------------------------------------- */ ++ ++/* ---- Private Functions ------------------------------------------------ */ ++ ++static inline unsigned vcaddr_to_pfn(unsigned long vc_addr) ++{ ++ unsigned long pfn = vc_addr & 0x3FFFFFFF; ++ pfn += mm_vc_mem_phys_addr; ++ pfn >>= PAGE_SHIFT; ++ return pfn; ++} ++ ++/* Carries over to the state statistics the statistics once owned by a deceased ++** resource. ++*/ ++static void vc_sm_resource_deceased(struct SM_RESOURCE_T *p_res, int terminated) ++{ ++ if (sm_state != NULL) { ++ if (p_res != NULL) { ++ int ix; ++ ++ if (terminated) ++ sm_state->res_terminated_cnt++; ++ else ++ sm_state->res_deceased_cnt++; ++ ++ for (ix = 0; ix < END_ALL; ix++) { ++ if (terminated) ++ sm_state->terminated[ix] += ++ p_res->res_stats[ix]; ++ else ++ sm_state->deceased[ix] += ++ p_res->res_stats[ix]; ++ } ++ } ++ } ++} ++ ++/* Fetch a videocore handle corresponding to a mapping of the pid+address ++** returns 0 (ie NULL) if no such handle exists in the global map. ++*/ ++static unsigned int vmcs_sm_vc_handle_from_pid_and_address(unsigned int pid, ++ unsigned int addr) ++{ ++ struct sm_mmap *map = NULL; ++ unsigned int handle = 0; ++ ++ if (!sm_state || addr == 0) ++ goto out; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Lookup the resource. ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (map->res_pid != pid || map->res_addr != addr) ++ continue; ++ ++ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n", ++ __func__, map, map->res_pid, map->res_addr, ++ map->res_vc_hdl, map->res_usr_hdl); ++ ++ handle = map->res_vc_hdl; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++out: ++ /* Use a debug log here as it may be a valid situation that we query ++ ** for something that is not mapped, we do not want a kernel log each ++ ** time around. ++ ** ++ ** There are other error log that would pop up accordingly if someone ++ ** subsequently tries to use something invalid after being told not to ++ ** use it... ++ */ ++ if (handle == 0) { ++ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n", ++ __func__, pid, addr); ++ } ++ ++ return handle; ++} ++ ++/* Fetch a user handle corresponding to a mapping of the pid+address ++** returns 0 (ie NULL) if no such handle exists in the global map. ++*/ ++static unsigned int vmcs_sm_usr_handle_from_pid_and_address(unsigned int pid, ++ unsigned int addr) ++{ ++ struct sm_mmap *map = NULL; ++ unsigned int handle = 0; ++ ++ if (!sm_state || addr == 0) ++ goto out; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Lookup the resource. ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (map->res_pid != pid || map->res_addr != addr) ++ continue; ++ ++ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n", ++ __func__, map, map->res_pid, map->res_addr, ++ map->res_usr_hdl, map->res_vc_hdl); ++ ++ handle = map->res_usr_hdl; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++out: ++ /* Use a debug log here as it may be a valid situation that we query ++ * for something that is not mapped yet. ++ * ++ * There are other error log that would pop up accordingly if someone ++ * subsequently tries to use something invalid after being told not to ++ * use it... ++ */ ++ if (handle == 0) ++ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n", ++ __func__, pid, addr); ++ ++ return handle; ++} ++ ++#if defined(DO_NOT_USE) ++/* Fetch an address corresponding to a mapping of the pid+handle ++** returns 0 (ie NULL) if no such address exists in the global map. ++*/ ++static unsigned int vmcs_sm_usr_address_from_pid_and_vc_handle(unsigned int pid, ++ unsigned int hdl) ++{ ++ struct sm_mmap *map = NULL; ++ unsigned int addr = 0; ++ ++ if (sm_state == NULL || hdl == 0) ++ goto out; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Lookup the resource. ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (map->res_pid != pid || map->res_vc_hdl != hdl) ++ continue; ++ ++ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n", ++ __func__, map, map->res_pid, map->res_vc_hdl, ++ map->res_usr_hdl, map->res_addr); ++ ++ addr = map->res_addr; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++out: ++ /* Use a debug log here as it may be a valid situation that we query ++ ** for something that is not mapped, we do not want a kernel log each ++ ** time around. ++ ** ++ ** There are other error log that would pop up accordingly if someone ++ ** subsequently tries to use something invalid after being told not to ++ ** use it... ++ */ ++ if (addr == 0) ++ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", ++ __func__, pid, hdl); ++ ++ return addr; ++} ++#endif ++ ++/* Fetch an address corresponding to a mapping of the pid+handle ++** returns 0 (ie NULL) if no such address exists in the global map. ++*/ ++static unsigned int vmcs_sm_usr_address_from_pid_and_usr_handle(unsigned int ++ pid, ++ unsigned int ++ hdl) ++{ ++ struct sm_mmap *map = NULL; ++ unsigned int addr = 0; ++ ++ if (sm_state == NULL || hdl == 0) ++ goto out; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Lookup the resource. ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (map->res_pid != pid || map->res_usr_hdl != hdl) ++ continue; ++ ++ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n", ++ __func__, map, map->res_pid, map->res_vc_hdl, ++ map->res_usr_hdl, map->res_addr); ++ ++ addr = map->res_addr; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++out: ++ /* Use a debug log here as it may be a valid situation that we query ++ * for something that is not mapped, we do not want a kernel log each ++ * time around. ++ * ++ * There are other error log that would pop up accordingly if someone ++ * subsequently tries to use something invalid after being told not to ++ * use it... ++ */ ++ if (addr == 0) ++ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", __func__, ++ pid, hdl); ++ ++ return addr; ++} ++ ++/* Adds a resource mapping to the global data list. ++*/ ++static void vmcs_sm_add_map(struct SM_STATE_T *state, ++ struct SM_RESOURCE_T *resource, struct sm_mmap *map) ++{ ++ mutex_lock(&(state->map_lock)); ++ ++ /* Add to the global list of mappings ++ */ ++ list_add(&map->map_list, &state->map_list); ++ ++ /* Add to the list of mappings for this resource ++ */ ++ list_add(&map->resource_map_list, &resource->map_list); ++ resource->map_count++; ++ ++ mutex_unlock(&(state->map_lock)); ++ ++ pr_debug("[%s]: added map %p (pid %u, vc-hdl %x, usr-hdl %x, addr %lx)\n", ++ __func__, map, map->res_pid, map->res_vc_hdl, ++ map->res_usr_hdl, map->res_addr); ++} ++ ++/* Removes a resource mapping from the global data list. ++*/ ++static void vmcs_sm_remove_map(struct SM_STATE_T *state, ++ struct SM_RESOURCE_T *resource, ++ struct sm_mmap *map) ++{ ++ mutex_lock(&(state->map_lock)); ++ ++ /* Remove from the global list of mappings ++ */ ++ list_del(&map->map_list); ++ ++ /* Remove from the list of mapping for this resource ++ */ ++ list_del(&map->resource_map_list); ++ if (resource->map_count > 0) ++ resource->map_count--; ++ ++ mutex_unlock(&(state->map_lock)); ++ ++ pr_debug("[%s]: removed map %p (pid %d, vc-hdl %x, usr-hdl %x, addr %lx)\n", ++ __func__, map, map->res_pid, map->res_vc_hdl, map->res_usr_hdl, ++ map->res_addr); ++ ++ kfree(map); ++} ++ ++/* Read callback for the global state proc entry. ++*/ ++static int vc_sm_global_state_show(struct seq_file *s, void *v) ++{ ++ struct sm_mmap *map = NULL; ++ int map_count = 0; ++ ++ if (sm_state == NULL) ++ return 0; ++ ++ seq_printf(s, "\nVC-ServiceHandle 0x%x\n", ++ (unsigned int)sm_state->sm_handle); ++ ++ /* Log all applicable mapping(s). ++ */ ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ map_count++; ++ ++ seq_printf(s, "\nMapping 0x%x\n", ++ (unsigned int)map); ++ seq_printf(s, " TGID %u\n", ++ map->res_pid); ++ seq_printf(s, " VC-HDL 0x%x\n", ++ map->res_vc_hdl); ++ seq_printf(s, " USR-HDL 0x%x\n", ++ map->res_usr_hdl); ++ seq_printf(s, " USR-ADDR 0x%lx\n", ++ map->res_addr); ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ seq_printf(s, "\n\nTotal map count: %d\n\n", map_count); ++ ++ return 0; ++} ++ ++static int vc_sm_global_statistics_show(struct seq_file *s, void *v) ++{ ++ int ix; ++ ++ /* Global state tracked statistics. ++ */ ++ if (sm_state != NULL) { ++ seq_puts(s, "\nDeceased Resources Statistics\n"); ++ ++ seq_printf(s, "\nNatural Cause (%u occurences)\n", ++ sm_state->res_deceased_cnt); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (sm_state->deceased[ix] > 0) { ++ seq_printf(s, " %u\t%s\n", ++ sm_state->deceased[ix], ++ sm_stats_human_read[ix]); ++ } ++ } ++ seq_puts(s, "\n"); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (sm_state->deceased[ix + END_ATTEMPT] > 0) { ++ seq_printf(s, " %u\tFAILED %s\n", ++ sm_state->deceased[ix + END_ATTEMPT], ++ sm_stats_human_read[ix]); ++ } ++ } ++ ++ seq_printf(s, "\nForcefull (%u occurences)\n", ++ sm_state->res_terminated_cnt); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (sm_state->terminated[ix] > 0) { ++ seq_printf(s, " %u\t%s\n", ++ sm_state->terminated[ix], ++ sm_stats_human_read[ix]); ++ } ++ } ++ seq_puts(s, "\n"); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (sm_state->terminated[ix + END_ATTEMPT] > 0) { ++ seq_printf(s, " %u\tFAILED %s\n", ++ sm_state->terminated[ix + ++ END_ATTEMPT], ++ sm_stats_human_read[ix]); ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++#if 0 ++/* Read callback for the statistics proc entry. ++*/ ++static int vc_sm_statistics_show(struct seq_file *s, void *v) ++{ ++ int ix; ++ struct SM_PRIV_DATA_T *file_data; ++ struct SM_RESOURCE_T *resource; ++ int res_count = 0; ++ struct SM_PDE_T *p_pde; ++ ++ p_pde = (struct SM_PDE_T *)(s->private); ++ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data); ++ ++ if (file_data == NULL) ++ return 0; ++ ++ /* Per process statistics. ++ */ ++ ++ seq_printf(s, "\nStatistics for TGID %d\n", file_data->pid); ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (!list_empty(&file_data->resource_list)) { ++ list_for_each_entry(resource, &file_data->resource_list, ++ resource_list) { ++ res_count++; ++ ++ seq_printf(s, "\nGUID: 0x%x\n\n", ++ resource->res_guid); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (resource->res_stats[ix] > 0) { ++ seq_printf(s, ++ " %u\t%s\n", ++ resource->res_stats[ix], ++ sm_stats_human_read[ix]); ++ } ++ } ++ seq_puts(s, "\n"); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (resource->res_stats[ix + END_ATTEMPT] > 0) { ++ seq_printf(s, ++ " %u\tFAILED %s\n", ++ resource->res_stats[ ++ ix + END_ATTEMPT], ++ sm_stats_human_read[ix]); ++ } ++ } ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ seq_printf(s, "\nResources Count %d\n", res_count); ++ ++ return 0; ++} ++#endif ++ ++#if 0 ++/* Read callback for the allocation proc entry. */ ++static int vc_sm_alloc_show(struct seq_file *s, void *v) ++{ ++ struct SM_PRIV_DATA_T *file_data; ++ struct SM_RESOURCE_T *resource; ++ int alloc_count = 0; ++ struct SM_PDE_T *p_pde; ++ ++ p_pde = (struct SM_PDE_T *)(s->private); ++ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data); ++ ++ if (!file_data) ++ return 0; ++ ++ /* Per process statistics. */ ++ seq_printf(s, "\nAllocation for TGID %d\n", file_data->pid); ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (!list_empty(&file_data->resource_list)) { ++ list_for_each_entry(resource, &file_data->resource_list, ++ resource_list) { ++ alloc_count++; ++ ++ seq_printf(s, "\nGUID: 0x%x\n", ++ resource->res_guid); ++ seq_printf(s, "Lock Count: %u\n", ++ resource->lock_count); ++ seq_printf(s, "Mapped: %s\n", ++ (resource->map_count ? "yes" : "no")); ++ seq_printf(s, "VC-handle: 0x%x\n", ++ resource->res_handle); ++ seq_printf(s, "VC-address: 0x%p\n", ++ resource->res_base_mem); ++ seq_printf(s, "VC-size (bytes): %u\n", ++ resource->res_size); ++ seq_printf(s, "Cache: %s\n", ++ sm_cache_map_vector[resource->res_cached]); ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ seq_printf(s, "\n\nTotal allocation count: %d\n\n", alloc_count); ++ ++ return 0; ++} ++#endif ++ ++static int vc_sm_seq_file_show(struct seq_file *s, void *v) ++{ ++ struct SM_PDE_T *sm_pde; ++ ++ sm_pde = (struct SM_PDE_T *)(s->private); ++ ++ if (sm_pde && sm_pde->show) ++ sm_pde->show(s, v); ++ ++ return 0; ++} ++ ++static int vc_sm_single_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, vc_sm_seq_file_show, inode->i_private); ++} ++ ++static const struct file_operations vc_sm_debug_fs_fops = { ++ .open = vc_sm_single_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/* Adds a resource to the private data list which tracks all the allocated ++** data. ++*/ ++static void vmcs_sm_add_resource(struct SM_PRIV_DATA_T *privdata, ++ struct SM_RESOURCE_T *resource) ++{ ++ mutex_lock(&(sm_state->map_lock)); ++ list_add(&resource->resource_list, &privdata->resource_list); ++ list_add(&resource->global_resource_list, &sm_state->resource_list); ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ pr_debug("[%s]: added resource %p (base addr %p, hdl %x, size %u, cache %u)\n", ++ __func__, resource, resource->res_base_mem, ++ resource->res_handle, resource->res_size, resource->res_cached); ++} ++ ++/* Locates a resource and acquire a reference on it. ++** The resource won't be deleted while there is a reference on it. ++*/ ++static struct SM_RESOURCE_T *vmcs_sm_acquire_resource(struct SM_PRIV_DATA_T ++ *private, ++ unsigned int res_guid) ++{ ++ struct SM_RESOURCE_T *resource, *ret = NULL; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ list_for_each_entry(resource, &private->resource_list, resource_list) { ++ if (resource->res_guid != res_guid) ++ continue; ++ ++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", ++ __func__, resource, resource->res_guid, ++ resource->res_base_mem, resource->res_handle, ++ resource->res_size, resource->res_cached); ++ resource->ref_count++; ++ ret = resource; ++ break; ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return ret; ++} ++ ++/* Locates a resource and acquire a reference on it. ++** The resource won't be deleted while there is a reference on it. ++*/ ++static struct SM_RESOURCE_T *vmcs_sm_acquire_first_resource( ++ struct SM_PRIV_DATA_T *private) ++{ ++ struct SM_RESOURCE_T *resource, *ret = NULL; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ list_for_each_entry(resource, &private->resource_list, resource_list) { ++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", ++ __func__, resource, resource->res_guid, ++ resource->res_base_mem, resource->res_handle, ++ resource->res_size, resource->res_cached); ++ resource->ref_count++; ++ ret = resource; ++ break; ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return ret; ++} ++ ++/* Locates a resource and acquire a reference on it. ++** The resource won't be deleted while there is a reference on it. ++*/ ++static struct SM_RESOURCE_T *vmcs_sm_acquire_global_resource(unsigned int ++ res_guid) ++{ ++ struct SM_RESOURCE_T *resource, *ret = NULL; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ list_for_each_entry(resource, &sm_state->resource_list, ++ global_resource_list) { ++ if (resource->res_guid != res_guid) ++ continue; ++ ++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", ++ __func__, resource, resource->res_guid, ++ resource->res_base_mem, resource->res_handle, ++ resource->res_size, resource->res_cached); ++ resource->ref_count++; ++ ret = resource; ++ break; ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return ret; ++} ++ ++/* Release a previously acquired resource. ++** The resource will be deleted when its refcount reaches 0. ++*/ ++static void vmcs_sm_release_resource(struct SM_RESOURCE_T *resource, int force) ++{ ++ struct SM_PRIV_DATA_T *private = resource->private; ++ struct sm_mmap *map, *map_tmp; ++ struct SM_RESOURCE_T *res_tmp; ++ int ret; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (--resource->ref_count) { ++ if (force) ++ pr_err("[%s]: resource %p in use\n", __func__, resource); ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ return; ++ } ++ ++ /* Time to free the resource. Start by removing it from the list */ ++ list_del(&resource->resource_list); ++ list_del(&resource->global_resource_list); ++ ++ /* Walk the global resource list, find out if the resource is used ++ * somewhere else. In which case we don't want to delete it. ++ */ ++ list_for_each_entry(res_tmp, &sm_state->resource_list, ++ global_resource_list) { ++ if (res_tmp->res_handle == resource->res_handle) { ++ resource->res_handle = 0; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ pr_debug("[%s]: freeing data - guid %x, hdl %x, base address %p\n", ++ __func__, resource->res_guid, resource->res_handle, ++ resource->res_base_mem); ++ resource->res_stats[FREE]++; ++ ++ /* Make sure the resource we're removing is unmapped first */ ++ if (resource->map_count && !list_empty(&resource->map_list)) { ++ down_write(¤t->mm->mmap_sem); ++ list_for_each_entry_safe(map, map_tmp, &resource->map_list, ++ resource_map_list) { ++ ret = ++ do_munmap(current->mm, map->res_addr, ++ resource->res_size); ++ if (ret) { ++ pr_err("[%s]: could not unmap resource %p\n", ++ __func__, resource); ++ } ++ } ++ up_write(¤t->mm->mmap_sem); ++ } ++ ++ /* Free up the videocore allocated resource. ++ */ ++ if (resource->res_handle) { ++ VC_SM_FREE_T free = { ++ resource->res_handle, resource->res_base_mem ++ }; ++ int status = vc_vchi_sm_free(sm_state->sm_handle, &free, ++ &private->int_trans_id); ++ if (status != 0 && status != -EINTR) { ++ pr_err("[%s]: failed to free memory on videocore (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ resource->res_stats[FREE_FAIL]++; ++ ret = -EPERM; ++ } ++ } ++ ++ /* Free up the shared resource. ++ */ ++ if (resource->res_shared) ++ vmcs_sm_release_resource(resource->res_shared, 0); ++ ++ /* Free up the local resource tracking this allocation. ++ */ ++ vc_sm_resource_deceased(resource, force); ++ kfree(resource); ++} ++ ++/* Dump the map table for the driver. If process is -1, dumps the whole table, ++** if process is a valid pid (non -1) dump only the entries associated with the ++** pid of interest. ++*/ ++static void vmcs_sm_host_walk_map_per_pid(int pid) ++{ ++ struct sm_mmap *map = NULL; ++ ++ /* Make sure the device was started properly. ++ */ ++ if (sm_state == NULL) { ++ pr_err("[%s]: invalid device\n", __func__); ++ return; ++ } ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Log all applicable mapping(s). ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (pid == -1 || map->res_pid == pid) { ++ pr_info("[%s]: tgid: %u - vc-hdl: %x, usr-hdl: %x, usr-addr: %lx\n", ++ __func__, map->res_pid, map->res_vc_hdl, ++ map->res_usr_hdl, map->res_addr); ++ } ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return; ++} ++ ++/* Dump the allocation table from host side point of view. This only dumps the ++** data allocated for this process/device referenced by the file_data. ++*/ ++static void vmcs_sm_host_walk_alloc(struct SM_PRIV_DATA_T *file_data) ++{ ++ struct SM_RESOURCE_T *resource = NULL; ++ ++ /* Make sure the device was started properly. ++ */ ++ if ((sm_state == NULL) || (file_data == NULL)) { ++ pr_err("[%s]: invalid device\n", __func__); ++ return; ++ } ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (!list_empty(&file_data->resource_list)) { ++ list_for_each_entry(resource, &file_data->resource_list, ++ resource_list) { ++ pr_info("[%s]: guid: %x - hdl: %x, vc-mem: %p, size: %u, cache: %u\n", ++ __func__, resource->res_guid, resource->res_handle, ++ resource->res_base_mem, resource->res_size, ++ resource->res_cached); ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return; ++} ++ ++/* Create support for private data tracking. ++*/ ++static struct SM_PRIV_DATA_T *vc_sm_create_priv_data(pid_t id) ++{ ++ char alloc_name[32]; ++ struct SM_PRIV_DATA_T *file_data = NULL; ++ ++ /* Allocate private structure. */ ++ file_data = kzalloc(sizeof(*file_data), GFP_KERNEL); ++ ++ if (!file_data) { ++ pr_err("[%s]: cannot allocate file data\n", __func__); ++ goto out; ++ } ++ ++ snprintf(alloc_name, sizeof(alloc_name), "%d", id); ++ ++ INIT_LIST_HEAD(&file_data->resource_list); ++ file_data->pid = id; ++ file_data->dir_pid = debugfs_create_dir(alloc_name, ++ sm_state->dir_alloc); ++#if 0 ++ /* TODO: fix this to support querying statistics per pid */ ++ ++ if (IS_ERR_OR_NULL(file_data->dir_pid)) { ++ file_data->dir_pid = NULL; ++ } else { ++ struct dentry *dir_entry; ++ ++ dir_entry = debugfs_create_file(VC_SM_RESOURCES, S_IRUGO, ++ file_data->dir_pid, file_data, ++ vc_sm_debug_fs_fops); ++ ++ file_data->dir_res.dir_entry = dir_entry; ++ file_data->dir_res.priv_data = file_data; ++ file_data->dir_res.show = &vc_sm_alloc_show; ++ ++ dir_entry = debugfs_create_file(VC_SM_STATS, S_IRUGO, ++ file_data->dir_pid, file_data, ++ vc_sm_debug_fs_fops); ++ ++ file_data->dir_res.dir_entry = dir_entry; ++ file_data->dir_res.priv_data = file_data; ++ file_data->dir_res.show = &vc_sm_statistics_show; ++ } ++ pr_debug("[%s]: private data allocated %p\n", __func__, file_data); ++ ++#endif ++out: ++ return file_data; ++} ++ ++/* Open the device. Creates a private state to help track all allocation ++** associated with this device. ++*/ ++static int vc_sm_open(struct inode *inode, struct file *file) ++{ ++ int ret = 0; ++ ++ /* Make sure the device was started properly. ++ */ ++ if (!sm_state) { ++ pr_err("[%s]: invalid device\n", __func__); ++ ret = -EPERM; ++ goto out; ++ } ++ ++ file->private_data = vc_sm_create_priv_data(current->tgid); ++ if (file->private_data == NULL) { ++ pr_err("[%s]: failed to create data tracker\n", __func__); ++ ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++out: ++ return ret; ++} ++ ++/* Close the device. Free up all resources still associated with this device ++** at the time. ++*/ ++static int vc_sm_release(struct inode *inode, struct file *file) ++{ ++ struct SM_PRIV_DATA_T *file_data = ++ (struct SM_PRIV_DATA_T *)file->private_data; ++ struct SM_RESOURCE_T *resource; ++ int ret = 0; ++ ++ /* Make sure the device was started properly. ++ */ ++ if (sm_state == NULL || file_data == NULL) { ++ pr_err("[%s]: invalid device\n", __func__); ++ ret = -EPERM; ++ goto out; ++ } ++ ++ pr_debug("[%s]: using private data %p\n", __func__, file_data); ++ ++ if (file_data->restart_sys == -EINTR) { ++ VC_SM_ACTION_CLEAN_T action_clean; ++ ++ pr_debug("[%s]: releasing following EINTR on %u (trans_id: %u) (likely due to signal)...\n", ++ __func__, file_data->int_action, ++ file_data->int_trans_id); ++ ++ action_clean.res_action = file_data->int_action; ++ action_clean.action_trans_id = file_data->int_trans_id; ++ ++ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean); ++ } ++ ++ while ((resource = vmcs_sm_acquire_first_resource(file_data)) != NULL) { ++ vmcs_sm_release_resource(resource, 0); ++ vmcs_sm_release_resource(resource, 1); ++ } ++ ++ /* Remove the corresponding proc entry. */ ++ debugfs_remove_recursive(file_data->dir_pid); ++ ++ /* Terminate the private data. ++ */ ++ kfree(file_data); ++ ++out: ++ return ret; ++} ++ ++static void vcsm_vma_open(struct vm_area_struct *vma) ++{ ++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; ++ ++ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n", ++ __func__, vma->vm_start, vma->vm_end, (int)current->tgid, ++ (int)vma->vm_pgoff); ++ ++ map->ref_count++; ++} ++ ++static void vcsm_vma_close(struct vm_area_struct *vma) ++{ ++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; ++ ++ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n", ++ __func__, vma->vm_start, vma->vm_end, (int)current->tgid, ++ (int)vma->vm_pgoff); ++ ++ map->ref_count--; ++ ++ /* Remove from the map table. ++ */ ++ if (map->ref_count == 0) ++ vmcs_sm_remove_map(sm_state, map->resource, map); ++} ++ ++static int vcsm_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf) ++{ ++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; ++ struct SM_RESOURCE_T *resource = map->resource; ++ pgoff_t page_offset; ++ unsigned long pfn; ++ int ret = 0; ++ ++ /* Lock the resource if necessary. ++ */ ++ if (!resource->lock_count) { ++ VC_SM_LOCK_UNLOCK_T lock_unlock; ++ VC_SM_LOCK_RESULT_T lock_result; ++ int status; ++ ++ lock_unlock.res_handle = resource->res_handle; ++ lock_unlock.res_mem = resource->res_base_mem; ++ ++ pr_debug("[%s]: attempt to lock data - hdl %x, base address %p\n", ++ __func__, lock_unlock.res_handle, lock_unlock.res_mem); ++ ++ /* Lock the videocore allocated resource. ++ */ ++ status = vc_vchi_sm_lock(sm_state->sm_handle, ++ &lock_unlock, &lock_result, 0); ++ if ((status != 0) || ++ ((status == 0) && (lock_result.res_mem == NULL))) { ++ pr_err("[%s]: failed to lock memory on videocore (status: %u)\n", ++ __func__, status); ++ resource->res_stats[LOCK_FAIL]++; ++ return VM_FAULT_SIGBUS; ++ } ++ ++ pfn = vcaddr_to_pfn((unsigned long)resource->res_base_mem); ++ outer_inv_range(__pfn_to_phys(pfn), ++ __pfn_to_phys(pfn) + resource->res_size); ++ ++ resource->res_stats[LOCK]++; ++ resource->lock_count++; ++ ++ /* Keep track of the new base memory. ++ */ ++ if ((lock_result.res_mem != NULL) && ++ (lock_result.res_old_mem != NULL) && ++ (lock_result.res_mem != lock_result.res_old_mem)) { ++ resource->res_base_mem = lock_result.res_mem; ++ } ++ } ++ ++ /* We don't use vmf->pgoff since that has the fake offset */ ++ page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start); ++ pfn = (uint32_t)resource->res_base_mem & 0x3FFFFFFF; ++ pfn += mm_vc_mem_phys_addr; ++ pfn += page_offset; ++ pfn >>= PAGE_SHIFT; ++ ++ /* Finally, remap it */ ++ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); ++ ++ switch (ret) { ++ case 0: ++ case -ERESTARTSYS: ++ return VM_FAULT_NOPAGE; ++ case -ENOMEM: ++ case -EAGAIN: ++ return VM_FAULT_OOM; ++ default: ++ return VM_FAULT_SIGBUS; ++ } ++} ++ ++static struct vm_operations_struct vcsm_vm_ops = { ++ .open = vcsm_vma_open, ++ .close = vcsm_vma_close, ++ .fault = vcsm_vma_fault, ++}; ++ ++/* Walks a VMA and clean each valid page from the cache */ ++static void vcsm_vma_cache_clean_page_range(unsigned long addr, ++ unsigned long end) ++{ ++ pgd_t *pgd; ++ pud_t *pud; ++ pmd_t *pmd; ++ pte_t *pte; ++ unsigned long pgd_next, pud_next, pmd_next; ++ ++ if (addr >= end) ++ return; ++ ++ /* Walk PGD */ ++ pgd = pgd_offset(current->mm, addr); ++ do { ++ pgd_next = pgd_addr_end(addr, end); ++ ++ if (pgd_none(*pgd) || pgd_bad(*pgd)) ++ continue; ++ ++ /* Walk PUD */ ++ pud = pud_offset(pgd, addr); ++ do { ++ pud_next = pud_addr_end(addr, pgd_next); ++ if (pud_none(*pud) || pud_bad(*pud)) ++ continue; ++ ++ /* Walk PMD */ ++ pmd = pmd_offset(pud, addr); ++ do { ++ pmd_next = pmd_addr_end(addr, pud_next); ++ if (pmd_none(*pmd) || pmd_bad(*pmd)) ++ continue; ++ ++ /* Walk PTE */ ++ pte = pte_offset_map(pmd, addr); ++ do { ++ if (pte_none(*pte) ++ || !pte_present(*pte)) ++ continue; ++ ++ /* Clean + invalidate */ ++ dmac_flush_range((const void *) addr, ++ (const void *) ++ (addr + PAGE_SIZE)); ++ ++ } while (pte++, addr += ++ PAGE_SIZE, addr != pmd_next); ++ pte_unmap(pte); ++ ++ } while (pmd++, addr = pmd_next, addr != pud_next); ++ ++ } while (pud++, addr = pud_next, addr != pgd_next); ++ } while (pgd++, addr = pgd_next, addr != end); ++} ++ ++/* Map an allocated data into something that the user space. ++*/ ++static int vc_sm_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ int ret = 0; ++ struct SM_PRIV_DATA_T *file_data = ++ (struct SM_PRIV_DATA_T *)file->private_data; ++ struct SM_RESOURCE_T *resource = NULL; ++ struct sm_mmap *map = NULL; ++ ++ /* Make sure the device was started properly. ++ */ ++ if ((sm_state == NULL) || (file_data == NULL)) { ++ pr_err("[%s]: invalid device\n", __func__); ++ return -EPERM; ++ } ++ ++ pr_debug("[%s]: private data %p, guid %x\n", __func__, file_data, ++ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT)); ++ ++ /* We lookup to make sure that the data we are being asked to mmap is ++ ** something that we allocated. ++ ** ++ ** We use the offset information as the key to tell us which resource ++ ** we are mapping. ++ */ ++ resource = vmcs_sm_acquire_resource(file_data, ++ ((unsigned int)vma->vm_pgoff << ++ PAGE_SHIFT)); ++ if (resource == NULL) { ++ pr_err("[%s]: failed to locate resource for guid %x\n", __func__, ++ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT)); ++ return -ENOMEM; ++ } ++ ++ pr_debug("[%s]: guid %x, tgid %u, %u, %u\n", ++ __func__, resource->res_guid, current->tgid, resource->pid, ++ file_data->pid); ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", ++ __func__, current->tgid, resource->pid); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ /* Verify that what we are asked to mmap is proper. ++ */ ++ if (resource->res_size != (unsigned int)(vma->vm_end - vma->vm_start)) { ++ pr_err("[%s]: size inconsistency (resource: %u - mmap: %u)\n", ++ __func__, ++ resource->res_size, ++ (unsigned int)(vma->vm_end - vma->vm_start)); ++ ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ /* Keep track of the tuple in the global resource list such that one ++ * can do a mapping lookup for address/memory handle. ++ */ ++ map = kzalloc(sizeof(*map), GFP_KERNEL); ++ if (map == NULL) { ++ pr_err("[%s]: failed to allocate global tracking resource\n", ++ __func__); ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ map->res_pid = current->tgid; ++ map->res_vc_hdl = resource->res_handle; ++ map->res_usr_hdl = resource->res_guid; ++ map->res_addr = (long unsigned int)vma->vm_start; ++ map->resource = resource; ++ map->vma = vma; ++ vmcs_sm_add_map(sm_state, resource, map); ++ ++ /* We are not actually mapping the pages, we just provide a fault ++ ** handler to allow pages to be mapped when accessed ++ */ ++ vma->vm_flags |= ++ VM_IO | VM_PFNMAP | VM_DONTCOPY | VM_DONTEXPAND; ++ vma->vm_ops = &vcsm_vm_ops; ++ vma->vm_private_data = map; ++ ++ /* vm_pgoff is the first PFN of the mapped memory */ ++ vma->vm_pgoff = (unsigned long)resource->res_base_mem & 0x3FFFFFFF; ++ vma->vm_pgoff += mm_vc_mem_phys_addr; ++ vma->vm_pgoff >>= PAGE_SHIFT; ++ ++ if ((resource->res_cached == VMCS_SM_CACHE_NONE) || ++ (resource->res_cached == VMCS_SM_CACHE_VC)) { ++ /* Allocated non host cached memory, honour it. ++ */ ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ } ++ ++ pr_debug("[%s]: resource %p (guid %x) - cnt %u, base address %p, handle %x, size %u (%u), cache %u\n", ++ __func__, ++ resource, resource->res_guid, resource->lock_count, ++ resource->res_base_mem, resource->res_handle, ++ resource->res_size, (unsigned int)(vma->vm_end - vma->vm_start), ++ resource->res_cached); ++ ++ pr_debug("[%s]: resource %p (base address %p, handle %x) - map-count %d, usr-addr %x\n", ++ __func__, resource, resource->res_base_mem, ++ resource->res_handle, resource->map_count, ++ (unsigned int)vma->vm_start); ++ ++ vcsm_vma_open(vma); ++ resource->res_stats[MAP]++; ++ vmcs_sm_release_resource(resource, 0); ++ return 0; ++ ++error: ++ vmcs_sm_release_resource(resource, 0); ++ resource->res_stats[MAP_FAIL]++; ++ return ret; ++} ++ ++/* Allocate a shared memory handle and block. ++*/ ++int vc_sm_ioctl_alloc(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_alloc *ioparam) ++{ ++ int ret = 0; ++ int status; ++ struct SM_RESOURCE_T *resource; ++ VC_SM_ALLOC_T alloc = { 0 }; ++ VC_SM_ALLOC_RESULT_T result = { 0 }; ++ ++ /* Setup our allocation parameters */ ++ alloc.type = ((ioparam->cached == VMCS_SM_CACHE_VC) ++ || (ioparam->cached == ++ VMCS_SM_CACHE_BOTH)) ? VC_SM_ALLOC_CACHED : ++ VC_SM_ALLOC_NON_CACHED; ++ alloc.base_unit = ioparam->size; ++ alloc.num_unit = ioparam->num; ++ alloc.allocator = current->tgid; ++ /* Align to kernel page size */ ++ alloc.alignement = 4096; ++ /* Align the size to the kernel page size */ ++ alloc.base_unit = ++ (alloc.base_unit + alloc.alignement - 1) & ~(alloc.alignement - 1); ++ if (*ioparam->name) { ++ memcpy(alloc.name, ioparam->name, sizeof(alloc.name) - 1); ++ } else { ++ memcpy(alloc.name, VMCS_SM_RESOURCE_NAME_DEFAULT, ++ sizeof(VMCS_SM_RESOURCE_NAME_DEFAULT)); ++ } ++ ++ pr_debug("[%s]: attempt to allocate \"%s\" data - type %u, base %u (%u), num %u, alignement %u\n", ++ __func__, alloc.name, alloc.type, ioparam->size, ++ alloc.base_unit, alloc.num_unit, alloc.alignement); ++ ++ /* Allocate local resource to track this allocation. ++ */ ++ resource = kzalloc(sizeof(*resource), GFP_KERNEL); ++ if (!resource) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ INIT_LIST_HEAD(&resource->map_list); ++ resource->ref_count++; ++ resource->pid = current->tgid; ++ ++ /* Allocate the videocore resource. ++ */ ++ status = vc_vchi_sm_alloc(sm_state->sm_handle, &alloc, &result, ++ &private->int_trans_id); ++ if (status == -EINTR) { ++ pr_debug("[%s]: requesting allocate memory action restart (trans_id: %u)\n", ++ __func__, private->int_trans_id); ++ ret = -ERESTARTSYS; ++ private->restart_sys = -EINTR; ++ private->int_action = VC_SM_MSG_TYPE_ALLOC; ++ goto error; ++ } else if (status != 0 || (status == 0 && result.res_mem == NULL)) { ++ pr_err("[%s]: failed to allocate memory on videocore (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ ret = -ENOMEM; ++ resource->res_stats[ALLOC_FAIL]++; ++ goto error; ++ } ++ ++ /* Keep track of the resource we created. ++ */ ++ resource->private = private; ++ resource->res_handle = result.res_handle; ++ resource->res_base_mem = result.res_mem; ++ resource->res_size = alloc.base_unit * alloc.num_unit; ++ resource->res_cached = ioparam->cached; ++ ++ /* Kernel/user GUID. This global identifier is used for mmap'ing the ++ * allocated region from user space, it is passed as the mmap'ing ++ * offset, we use it to 'hide' the videocore handle/address. ++ */ ++ mutex_lock(&sm_state->lock); ++ resource->res_guid = ++sm_state->guid; ++ mutex_unlock(&sm_state->lock); ++ resource->res_guid <<= PAGE_SHIFT; ++ ++ vmcs_sm_add_resource(private, resource); ++ ++ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n", ++ __func__, resource->res_guid, resource->res_handle, ++ resource->res_base_mem, resource->res_size, ++ resource->res_cached); ++ ++ /* We're done */ ++ resource->res_stats[ALLOC]++; ++ ioparam->handle = resource->res_guid; ++ return 0; ++ ++error: ++ pr_err("[%s]: failed to allocate \"%s\" data (%i) - type %u, base %u (%u), num %u, alignment %u\n", ++ __func__, alloc.name, ret, alloc.type, ioparam->size, ++ alloc.base_unit, alloc.num_unit, alloc.alignement); ++ if (resource != NULL) { ++ vc_sm_resource_deceased(resource, 1); ++ kfree(resource); ++ } ++ return ret; ++} ++ ++/* Share an allocate memory handle and block. ++*/ ++int vc_sm_ioctl_alloc_share(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_alloc_share *ioparam) ++{ ++ struct SM_RESOURCE_T *resource, *shared_resource; ++ int ret = 0; ++ ++ pr_debug("[%s]: attempt to share resource %u\n", __func__, ++ ioparam->handle); ++ ++ shared_resource = vmcs_sm_acquire_global_resource(ioparam->handle); ++ if (shared_resource == NULL) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ /* Allocate local resource to track this allocation. ++ */ ++ resource = kzalloc(sizeof(*resource), GFP_KERNEL); ++ if (resource == NULL) { ++ pr_err("[%s]: failed to allocate local tracking resource\n", ++ __func__); ++ ret = -ENOMEM; ++ goto error; ++ } ++ INIT_LIST_HEAD(&resource->map_list); ++ resource->ref_count++; ++ resource->pid = current->tgid; ++ ++ /* Keep track of the resource we created. ++ */ ++ resource->private = private; ++ resource->res_handle = shared_resource->res_handle; ++ resource->res_base_mem = shared_resource->res_base_mem; ++ resource->res_size = shared_resource->res_size; ++ resource->res_cached = shared_resource->res_cached; ++ resource->res_shared = shared_resource; ++ ++ mutex_lock(&sm_state->lock); ++ resource->res_guid = ++sm_state->guid; ++ mutex_unlock(&sm_state->lock); ++ resource->res_guid <<= PAGE_SHIFT; ++ ++ vmcs_sm_add_resource(private, resource); ++ ++ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n", ++ __func__, resource->res_guid, resource->res_handle, ++ resource->res_base_mem, resource->res_size, ++ resource->res_cached); ++ ++ /* We're done */ ++ resource->res_stats[ALLOC]++; ++ ioparam->handle = resource->res_guid; ++ ioparam->size = resource->res_size; ++ return 0; ++ ++error: ++ pr_err("[%s]: failed to share %u\n", __func__, ioparam->handle); ++ if (shared_resource != NULL) ++ vmcs_sm_release_resource(shared_resource, 0); ++ ++ return ret; ++} ++ ++/* Free a previously allocated shared memory handle and block. ++*/ ++static int vc_sm_ioctl_free(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_free *ioparam) ++{ ++ struct SM_RESOURCE_T *resource = ++ vmcs_sm_acquire_resource(private, ioparam->handle); ++ ++ if (resource == NULL) { ++ pr_err("[%s]: resource for guid %u does not exist\n", __func__, ++ ioparam->handle); ++ return -EINVAL; ++ } ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", ++ __func__, current->tgid, resource->pid); ++ vmcs_sm_release_resource(resource, 0); ++ return -EPERM; ++ } ++ ++ vmcs_sm_release_resource(resource, 0); ++ vmcs_sm_release_resource(resource, 0); ++ return 0; ++} ++ ++/* Resize a previously allocated shared memory handle and block. ++*/ ++static int vc_sm_ioctl_resize(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_resize *ioparam) ++{ ++ int ret = 0; ++ int status; ++ VC_SM_RESIZE_T resize; ++ struct SM_RESOURCE_T *resource; ++ ++ /* Locate resource from GUID. ++ */ ++ resource = vmcs_sm_acquire_resource(private, ioparam->handle); ++ if (!resource) { ++ pr_err("[%s]: failed resource - guid %x\n", ++ __func__, ioparam->handle); ++ ret = -EFAULT; ++ goto error; ++ } ++ ++ /* If the resource is locked, its reference count will be not NULL, ++ ** in which case we will not be allowed to resize it anyways, so ++ ** reject the attempt here. ++ */ ++ if (resource->lock_count != 0) { ++ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n", ++ __func__, ioparam->handle, resource->lock_count); ++ ret = -EFAULT; ++ goto error; ++ } ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", __func__, ++ current->tgid, resource->pid); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ if (resource->map_count != 0) { ++ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n", ++ __func__, ioparam->handle, resource->map_count); ++ ret = -EFAULT; ++ goto error; ++ } ++ ++ resize.res_handle = resource->res_handle; ++ resize.res_mem = resource->res_base_mem; ++ resize.res_new_size = ioparam->new_size; ++ ++ pr_debug("[%s]: attempt to resize data - guid %x, hdl %x, base address %p\n", ++ __func__, ioparam->handle, resize.res_handle, resize.res_mem); ++ ++ /* Resize the videocore allocated resource. ++ */ ++ status = vc_vchi_sm_resize(sm_state->sm_handle, &resize, ++ &private->int_trans_id); ++ if (status == -EINTR) { ++ pr_debug("[%s]: requesting resize memory action restart (trans_id: %u)\n", ++ __func__, private->int_trans_id); ++ ret = -ERESTARTSYS; ++ private->restart_sys = -EINTR; ++ private->int_action = VC_SM_MSG_TYPE_RESIZE; ++ goto error; ++ } else if (status != 0) { ++ pr_err("[%s]: failed to resize memory on videocore (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ pr_debug("[%s]: success to resize data - hdl %x, size %d -> %d\n", ++ __func__, resize.res_handle, resource->res_size, ++ resize.res_new_size); ++ ++ /* Successfully resized, save the information and inform the user. ++ */ ++ ioparam->old_size = resource->res_size; ++ resource->res_size = resize.res_new_size; ++ ++error: ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ return ret; ++} ++ ++/* Lock a previously allocated shared memory handle and block. ++*/ ++static int vc_sm_ioctl_lock(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_lock_unlock *ioparam, ++ int change_cache, enum vmcs_sm_cache_e cache_type, ++ unsigned int vc_addr) ++{ ++ int status; ++ VC_SM_LOCK_UNLOCK_T lock; ++ VC_SM_LOCK_RESULT_T result; ++ struct SM_RESOURCE_T *resource; ++ int ret = 0; ++ struct sm_mmap *map, *map_tmp; ++ long unsigned int phys_addr; ++ ++ map = NULL; ++ ++ /* Locate resource from GUID. ++ */ ++ resource = vmcs_sm_acquire_resource(private, ioparam->handle); ++ if (resource == NULL) { ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", __func__, ++ current->tgid, resource->pid); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ lock.res_handle = resource->res_handle; ++ lock.res_mem = resource->res_base_mem; ++ ++ /* Take the lock and get the address to be mapped. ++ */ ++ if (vc_addr == 0) { ++ pr_debug("[%s]: attempt to lock data - guid %x, hdl %x, base address %p\n", ++ __func__, ioparam->handle, lock.res_handle, ++ lock.res_mem); ++ ++ /* Lock the videocore allocated resource. ++ */ ++ status = vc_vchi_sm_lock(sm_state->sm_handle, &lock, &result, ++ &private->int_trans_id); ++ if (status == -EINTR) { ++ pr_debug("[%s]: requesting lock memory action restart (trans_id: %u)\n", ++ __func__, private->int_trans_id); ++ ret = -ERESTARTSYS; ++ private->restart_sys = -EINTR; ++ private->int_action = VC_SM_MSG_TYPE_LOCK; ++ goto error; ++ } else if (status != 0 || ++ (status == 0 && result.res_mem == NULL)) { ++ pr_err("[%s]: failed to lock memory on videocore (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ ret = -EPERM; ++ resource->res_stats[LOCK_FAIL]++; ++ goto error; ++ } ++ ++ pr_debug("[%s]: succeed to lock data - hdl %x, base address %p (%p), ref-cnt %d\n", ++ __func__, lock.res_handle, result.res_mem, ++ lock.res_mem, resource->lock_count); ++ } ++ /* Lock assumed taken already, address to be mapped is known. ++ */ ++ else ++ resource->res_base_mem = (void *)vc_addr; ++ ++ resource->res_stats[LOCK]++; ++ resource->lock_count++; ++ ++ /* Keep track of the new base memory allocation if it has changed. ++ */ ++ if ((vc_addr == 0) && ++ (result.res_mem != NULL) && ++ (result.res_old_mem != NULL) && ++ (result.res_mem != result.res_old_mem)) { ++ resource->res_base_mem = result.res_mem; ++ ++ /* Kernel allocated resources. ++ */ ++ if (resource->pid == 0) { ++ if (!list_empty(&resource->map_list)) { ++ list_for_each_entry_safe(map, map_tmp, ++ &resource->map_list, ++ resource_map_list) { ++ if (map->res_addr) { ++ iounmap((void *)map->res_addr); ++ map->res_addr = 0; ++ ++ vmcs_sm_remove_map(sm_state, ++ map->resource, ++ map); ++ break; ++ } ++ } ++ } ++ } ++ } ++ ++ if (change_cache) ++ resource->res_cached = cache_type; ++ ++ if (resource->map_count) { ++ ioparam->addr = ++ vmcs_sm_usr_address_from_pid_and_usr_handle( ++ current->tgid, ioparam->handle); ++ ++ pr_debug("[%s] map_count %d private->pid %d current->tgid %d hnd %x addr %u\n", ++ __func__, resource->map_count, private->pid, ++ current->tgid, ioparam->handle, ioparam->addr); ++ } else { ++ /* Kernel allocated resources. ++ */ ++ if (resource->pid == 0) { ++ pr_debug("[%s]: attempt mapping kernel resource - guid %x, hdl %x\n", ++ __func__, ioparam->handle, lock.res_handle); ++ ++ ioparam->addr = 0; ++ ++ map = kzalloc(sizeof(*map), GFP_KERNEL); ++ if (map == NULL) { ++ pr_err("[%s]: failed allocating tracker\n", ++ __func__); ++ ret = -ENOMEM; ++ goto error; ++ } else { ++ phys_addr = (uint32_t)resource->res_base_mem & ++ 0x3FFFFFFF; ++ phys_addr += mm_vc_mem_phys_addr; ++ if (resource->res_cached ++ == VMCS_SM_CACHE_HOST) { ++ ioparam->addr = (long unsigned int) ++ /* TODO - make cached work */ ++ ioremap_nocache(phys_addr, ++ resource->res_size); ++ ++ pr_debug("[%s]: mapping kernel - guid %x, hdl %x - cached mapping %u\n", ++ __func__, ioparam->handle, ++ lock.res_handle, ioparam->addr); ++ } else { ++ ioparam->addr = (long unsigned int) ++ ioremap_nocache(phys_addr, ++ resource->res_size); ++ ++ pr_debug("[%s]: mapping kernel- guid %x, hdl %x - non cached mapping %u\n", ++ __func__, ioparam->handle, ++ lock.res_handle, ioparam->addr); ++ } ++ ++ map->res_pid = 0; ++ map->res_vc_hdl = resource->res_handle; ++ map->res_usr_hdl = resource->res_guid; ++ map->res_addr = ioparam->addr; ++ map->resource = resource; ++ map->vma = NULL; ++ ++ vmcs_sm_add_map(sm_state, resource, map); ++ } ++ } else ++ ioparam->addr = 0; ++ } ++ ++error: ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ return ret; ++} ++ ++/* Unlock a previously allocated shared memory handle and block. ++*/ ++static int vc_sm_ioctl_unlock(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_lock_unlock *ioparam, ++ int flush, int wait_reply, int no_vc_unlock) ++{ ++ int status; ++ VC_SM_LOCK_UNLOCK_T unlock; ++ struct sm_mmap *map, *map_tmp; ++ struct SM_RESOURCE_T *resource; ++ int ret = 0; ++ ++ map = NULL; ++ ++ /* Locate resource from GUID. ++ */ ++ resource = vmcs_sm_acquire_resource(private, ioparam->handle); ++ if (resource == NULL) { ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", ++ __func__, current->tgid, resource->pid); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ unlock.res_handle = resource->res_handle; ++ unlock.res_mem = resource->res_base_mem; ++ ++ pr_debug("[%s]: attempt to unlock data - guid %x, hdl %x, base address %p\n", ++ __func__, ioparam->handle, unlock.res_handle, unlock.res_mem); ++ ++ /* User space allocated resources. ++ */ ++ if (resource->pid) { ++ /* Flush if requested */ ++ if (resource->res_cached && flush) { ++ dma_addr_t phys_addr = 0; ++ resource->res_stats[FLUSH]++; ++ ++ phys_addr = ++ (dma_addr_t)((uint32_t)resource->res_base_mem & ++ 0x3FFFFFFF); ++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; ++ ++ /* L1 cache flush */ ++ down_read(¤t->mm->mmap_sem); ++ list_for_each_entry(map, &resource->map_list, ++ resource_map_list) { ++ if (map->vma) { ++ unsigned long start; ++ unsigned long end; ++ start = map->vma->vm_start; ++ end = map->vma->vm_end; ++ ++ vcsm_vma_cache_clean_page_range( ++ start, end); ++ } ++ } ++ up_read(¤t->mm->mmap_sem); ++ ++ /* L2 cache flush */ ++ outer_clean_range(phys_addr, ++ phys_addr + ++ (size_t) resource->res_size); ++ } ++ ++ /* We need to zap all the vmas associated with this resource */ ++ if (resource->lock_count == 1) { ++ down_read(¤t->mm->mmap_sem); ++ list_for_each_entry(map, &resource->map_list, ++ resource_map_list) { ++ if (map->vma) { ++ zap_vma_ptes(map->vma, ++ map->vma->vm_start, ++ map->vma->vm_end - ++ map->vma->vm_start); ++ } ++ } ++ up_read(¤t->mm->mmap_sem); ++ } ++ } ++ /* Kernel allocated resources. */ ++ else { ++ /* Global + Taken in this context */ ++ if (resource->ref_count == 2) { ++ if (!list_empty(&resource->map_list)) { ++ list_for_each_entry_safe(map, map_tmp, ++ &resource->map_list, ++ resource_map_list) { ++ if (map->res_addr) { ++ if (flush && ++ (resource->res_cached == ++ VMCS_SM_CACHE_HOST)) { ++ long unsigned int ++ phys_addr; ++ phys_addr = (uint32_t) ++ resource->res_base_mem & 0x3FFFFFFF; ++ phys_addr += ++ mm_vc_mem_phys_addr; ++ ++ /* L1 cache flush */ ++ dmac_flush_range((const ++ void ++ *) ++ map->res_addr, (const void *) ++ (map->res_addr + resource->res_size)); ++ ++ /* L2 cache flush */ ++ outer_clean_range ++ (phys_addr, ++ phys_addr + ++ (size_t) ++ resource->res_size); ++ } ++ ++ iounmap((void *)map->res_addr); ++ map->res_addr = 0; ++ ++ vmcs_sm_remove_map(sm_state, ++ map->resource, ++ map); ++ break; ++ } ++ } ++ } ++ } ++ } ++ ++ if (resource->lock_count) { ++ /* Bypass the videocore unlock. ++ */ ++ if (no_vc_unlock) ++ status = 0; ++ /* Unlock the videocore allocated resource. ++ */ ++ else { ++ status = ++ vc_vchi_sm_unlock(sm_state->sm_handle, &unlock, ++ &private->int_trans_id, ++ wait_reply); ++ if (status == -EINTR) { ++ pr_debug("[%s]: requesting unlock memory action restart (trans_id: %u)\n", ++ __func__, private->int_trans_id); ++ ++ ret = -ERESTARTSYS; ++ resource->res_stats[UNLOCK]--; ++ private->restart_sys = -EINTR; ++ private->int_action = VC_SM_MSG_TYPE_UNLOCK; ++ goto error; ++ } else if (status != 0) { ++ pr_err("[%s]: failed to unlock vc mem (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ ++ ret = -EPERM; ++ resource->res_stats[UNLOCK_FAIL]++; ++ goto error; ++ } ++ } ++ ++ resource->res_stats[UNLOCK]++; ++ resource->lock_count--; ++ } ++ ++ pr_debug("[%s]: success to unlock data - hdl %x, base address %p, ref-cnt %d\n", ++ __func__, unlock.res_handle, unlock.res_mem, ++ resource->lock_count); ++ ++error: ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ return ret; ++} ++ ++/* Handle control from host. */ ++static long vc_sm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int ret = 0; ++ unsigned int cmdnr = _IOC_NR(cmd); ++ struct SM_PRIV_DATA_T *file_data = ++ (struct SM_PRIV_DATA_T *)file->private_data; ++ struct SM_RESOURCE_T *resource = NULL; ++ ++ /* Validate we can work with this device. */ ++ if ((sm_state == NULL) || (file_data == NULL)) { ++ pr_err("[%s]: invalid device\n", __func__); ++ ret = -EPERM; ++ goto out; ++ } ++ ++ pr_debug("[%s]: cmd %x tgid %u, owner %u\n", __func__, cmdnr, ++ current->tgid, file_data->pid); ++ ++ /* Action is a re-post of a previously interrupted action? */ ++ if (file_data->restart_sys == -EINTR) { ++ VC_SM_ACTION_CLEAN_T action_clean; ++ ++ pr_debug("[%s]: clean up of action %u (trans_id: %u) following EINTR\n", ++ __func__, file_data->int_action, ++ file_data->int_trans_id); ++ ++ action_clean.res_action = file_data->int_action; ++ action_clean.action_trans_id = file_data->int_trans_id; ++ ++ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean); ++ ++ file_data->restart_sys = 0; ++ } ++ ++ /* Now process the command. ++ */ ++ switch (cmdnr) { ++ /* New memory allocation. ++ */ ++ case VMCS_SM_CMD_ALLOC: ++ { ++ struct vmcs_sm_ioctl_alloc ioparam; ++ ++ /* Get the parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_alloc(file_data, &ioparam); ++ if (!ret && ++ (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0)) { ++ struct vmcs_sm_ioctl_free freeparam = { ++ ioparam.handle ++ }; ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ vc_sm_ioctl_free(file_data, &freeparam); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Share existing memory allocation. ++ */ ++ case VMCS_SM_CMD_ALLOC_SHARE: ++ { ++ struct vmcs_sm_ioctl_alloc_share ioparam; ++ ++ /* Get the parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_alloc_share(file_data, &ioparam); ++ ++ /* Copy result back to user. ++ */ ++ if (!ret ++ && copy_to_user((void *)arg, &ioparam, ++ sizeof(ioparam)) != 0) { ++ struct vmcs_sm_ioctl_free freeparam = { ++ ioparam.handle ++ }; ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ vc_sm_ioctl_free(file_data, &freeparam); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Lock (attempt to) *and* register a cache behavior change. ++ */ ++ case VMCS_SM_CMD_LOCK_CACHE: ++ { ++ struct vmcs_sm_ioctl_lock_cache ioparam; ++ struct vmcs_sm_ioctl_lock_unlock lock; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ lock.handle = ioparam.handle; ++ ret = ++ vc_sm_ioctl_lock(file_data, &lock, 1, ++ ioparam.cached, 0); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Lock (attempt to) existing memory allocation. ++ */ ++ case VMCS_SM_CMD_LOCK: ++ { ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_lock(file_data, &ioparam, 0, 0, 0); ++ ++ /* Copy result back to user. ++ */ ++ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam)) ++ != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Unlock (attempt to) existing memory allocation. ++ */ ++ case VMCS_SM_CMD_UNLOCK: ++ { ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_unlock(file_data, &ioparam, 0, 1, 0); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Resize (attempt to) existing memory allocation. ++ */ ++ case VMCS_SM_CMD_RESIZE: ++ { ++ struct vmcs_sm_ioctl_resize ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_resize(file_data, &ioparam); ++ ++ /* Copy result back to user. ++ */ ++ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam)) ++ != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Terminate existing memory allocation. ++ */ ++ case VMCS_SM_CMD_FREE: ++ { ++ struct vmcs_sm_ioctl_free ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_free(file_data, &ioparam); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Walk allocation on videocore, information shows up in the ++ ** videocore log. ++ */ ++ case VMCS_SM_CMD_VC_WALK_ALLOC: ++ { ++ pr_debug("[%s]: invoking walk alloc\n", __func__); ++ ++ if (vc_vchi_sm_walk_alloc(sm_state->sm_handle) != 0) ++ pr_err("[%s]: failed to walk-alloc on videocore\n", ++ __func__); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++/* Walk mapping table on host, information shows up in the ++ ** kernel log. ++ */ ++ case VMCS_SM_CMD_HOST_WALK_MAP: ++ { ++ /* Use pid of -1 to tell to walk the whole map. */ ++ vmcs_sm_host_walk_map_per_pid(-1); ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Walk mapping table per process on host. */ ++ case VMCS_SM_CMD_HOST_WALK_PID_ALLOC: ++ { ++ struct vmcs_sm_ioctl_walk ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ vmcs_sm_host_walk_alloc(file_data); ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Walk allocation per process on host. */ ++ case VMCS_SM_CMD_HOST_WALK_PID_MAP: ++ { ++ struct vmcs_sm_ioctl_walk ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ vmcs_sm_host_walk_map_per_pid(ioparam.pid); ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Gets the size of the memory associated with a user handle. */ ++ case VMCS_SM_CMD_SIZE_USR_HANDLE: ++ { ++ struct vmcs_sm_ioctl_size ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if (resource != NULL) { ++ ioparam.size = resource->res_size; ++ vmcs_sm_release_resource(resource, 0); ++ } else { ++ ioparam.size = 0; ++ } ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Verify we are dealing with a valid resource. */ ++ case VMCS_SM_CMD_CHK_USR_HANDLE: ++ { ++ struct vmcs_sm_ioctl_chk ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if (resource == NULL) ++ ret = -EINVAL; ++ /* If the resource is cacheable, return additional ++ * information that may be needed to flush the cache. ++ */ ++ else if ((resource->res_cached == VMCS_SM_CACHE_HOST) || ++ (resource->res_cached == VMCS_SM_CACHE_BOTH)) { ++ ioparam.addr = ++ vmcs_sm_usr_address_from_pid_and_usr_handle ++ (current->tgid, ioparam.handle); ++ ioparam.size = resource->res_size; ++ ioparam.cache = resource->res_cached; ++ } else { ++ ioparam.addr = 0; ++ ioparam.size = 0; ++ ioparam.cache = resource->res_cached; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* ++ * Maps a user handle given the process and the virtual address. ++ */ ++ case VMCS_SM_CMD_MAPPED_USR_HANDLE: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ioparam.handle = ++ vmcs_sm_usr_handle_from_pid_and_address( ++ ioparam.pid, ioparam.addr); ++ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if ((resource != NULL) ++ && ((resource->res_cached == VMCS_SM_CACHE_HOST) ++ || (resource->res_cached == ++ VMCS_SM_CACHE_BOTH))) { ++ ioparam.size = resource->res_size; ++ } else { ++ ioparam.size = 0; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* ++ * Maps a videocore handle given process and virtual address. ++ */ ++ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ioparam.handle = vmcs_sm_vc_handle_from_pid_and_address( ++ ioparam.pid, ioparam.addr); ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Maps a videocore handle given process and user handle. */ ++ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if (resource != NULL) { ++ ioparam.handle = resource->res_handle; ++ vmcs_sm_release_resource(resource, 0); ++ } else { ++ ioparam.handle = 0; ++ } ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* ++ * Maps a videocore address given process and videocore handle. ++ */ ++ case VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if (resource != NULL) { ++ ioparam.addr = ++ (unsigned int)resource->res_base_mem; ++ vmcs_sm_release_resource(resource, 0); ++ } else { ++ ioparam.addr = 0; ++ } ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Maps a user address given process and vc handle. ++ */ ++ case VMCS_SM_CMD_MAPPED_USR_ADDRESS: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* ++ * Return the address information from the mapping, ++ * 0 (ie NULL) if it cannot locate the actual mapping. ++ */ ++ ioparam.addr = ++ vmcs_sm_usr_address_from_pid_and_usr_handle ++ (ioparam.pid, ioparam.handle); ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Flush the cache for a given mapping. */ ++ case VMCS_SM_CMD_FLUSH: ++ { ++ struct vmcs_sm_ioctl_cache ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ ++ if ((resource != NULL) && resource->res_cached) { ++ dma_addr_t phys_addr = 0; ++ ++ resource->res_stats[FLUSH]++; ++ ++ phys_addr = ++ (dma_addr_t)((uint32_t) ++ resource->res_base_mem & ++ 0x3FFFFFFF); ++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; ++ ++ /* L1 cache flush */ ++ down_read(¤t->mm->mmap_sem); ++ vcsm_vma_cache_clean_page_range((unsigned long) ++ ioparam.addr, ++ (unsigned long) ++ ioparam.addr + ++ ioparam.size); ++ up_read(¤t->mm->mmap_sem); ++ ++ /* L2 cache flush */ ++ outer_clean_range(phys_addr, ++ phys_addr + ++ (size_t) ioparam.size); ++ } else if (resource == NULL) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Invalidate the cache for a given mapping. */ ++ case VMCS_SM_CMD_INVALID: ++ { ++ struct vmcs_sm_ioctl_cache ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. ++ */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ ++ if ((resource != NULL) && resource->res_cached) { ++ dma_addr_t phys_addr = 0; ++ ++ resource->res_stats[INVALID]++; ++ ++ phys_addr = ++ (dma_addr_t)((uint32_t) ++ resource->res_base_mem & ++ 0x3FFFFFFF); ++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; ++ ++ /* L2 cache invalidate */ ++ outer_inv_range(phys_addr, ++ phys_addr + ++ (size_t) ioparam.size); ++ ++ /* L1 cache invalidate */ ++ down_read(¤t->mm->mmap_sem); ++ vcsm_vma_cache_clean_page_range((unsigned long) ++ ioparam.addr, ++ (unsigned long) ++ ioparam.addr + ++ ioparam.size); ++ up_read(¤t->mm->mmap_sem); ++ } else if (resource == NULL) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Flush/Invalidate the cache for a given mapping. */ ++ case VMCS_SM_CMD_CLEAN_INVALID: ++ { ++ int i; ++ struct vmcs_sm_ioctl_clean_invalid ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ for (i=0; ires_cached) { ++ unsigned long base = ioparam.s[i].addr & ~(PAGE_SIZE-1); ++ unsigned long end = (ioparam.s[i].addr + ioparam.s[i].size + PAGE_SIZE-1) & ~(PAGE_SIZE-1); ++ resource->res_stats[ioparam.s[i].cmd == 1 ? INVALID:FLUSH]++; ++ ++ /* L1/L2 cache flush */ ++ down_read(¤t->mm->mmap_sem); ++ vcsm_vma_cache_clean_page_range(base, end); ++ up_read(¤t->mm->mmap_sem); ++ } else if (resource == NULL) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ } ++ break; ++ } ++ } ++ } ++ break; ++ ++ default: ++ { ++ ret = -EINVAL; ++ goto out; ++ } ++ break; ++ } ++ ++out: ++ return ret; ++} ++ ++/* Device operations that we managed in this driver. ++*/ ++static const struct file_operations vmcs_sm_ops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = vc_sm_ioctl, ++ .open = vc_sm_open, ++ .release = vc_sm_release, ++ .mmap = vc_sm_mmap, ++}; ++ ++/* Creation of device. ++*/ ++static int vc_sm_create_sharedmemory(void) ++{ ++ int ret; ++ ++ if (sm_state == NULL) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ /* Create a device class for creating dev nodes. ++ */ ++ sm_state->sm_class = class_create(THIS_MODULE, "vc-sm"); ++ if (IS_ERR(sm_state->sm_class)) { ++ pr_err("[%s]: unable to create device class\n", __func__); ++ ret = PTR_ERR(sm_state->sm_class); ++ goto out; ++ } ++ ++ /* Create a character driver. ++ */ ++ ret = alloc_chrdev_region(&sm_state->sm_devid, ++ DEVICE_MINOR, 1, DEVICE_NAME); ++ if (ret != 0) { ++ pr_err("[%s]: unable to allocate device number\n", __func__); ++ goto out_dev_class_destroy; ++ } ++ ++ cdev_init(&sm_state->sm_cdev, &vmcs_sm_ops); ++ ret = cdev_add(&sm_state->sm_cdev, sm_state->sm_devid, 1); ++ if (ret != 0) { ++ pr_err("[%s]: unable to register device\n", __func__); ++ goto out_chrdev_unreg; ++ } ++ ++ /* Create a device node. ++ */ ++ sm_state->sm_dev = device_create(sm_state->sm_class, ++ NULL, ++ MKDEV(MAJOR(sm_state->sm_devid), ++ DEVICE_MINOR), NULL, ++ DEVICE_NAME); ++ if (IS_ERR(sm_state->sm_dev)) { ++ pr_err("[%s]: unable to create device node\n", __func__); ++ ret = PTR_ERR(sm_state->sm_dev); ++ goto out_chrdev_del; ++ } ++ ++ goto out; ++ ++out_chrdev_del: ++ cdev_del(&sm_state->sm_cdev); ++out_chrdev_unreg: ++ unregister_chrdev_region(sm_state->sm_devid, 1); ++out_dev_class_destroy: ++ class_destroy(sm_state->sm_class); ++ sm_state->sm_class = NULL; ++out: ++ return ret; ++} ++ ++/* Termination of the device. ++*/ ++static int vc_sm_remove_sharedmemory(void) ++{ ++ int ret; ++ ++ if (sm_state == NULL) { ++ /* Nothing to do. ++ */ ++ ret = 0; ++ goto out; ++ } ++ ++ /* Remove the sharedmemory character driver. ++ */ ++ cdev_del(&sm_state->sm_cdev); ++ ++ /* Unregister region. ++ */ ++ unregister_chrdev_region(sm_state->sm_devid, 1); ++ ++ ret = 0; ++ goto out; ++ ++out: ++ return ret; ++} ++ ++/* Videocore connected. */ ++static void vc_sm_connected_init(void) ++{ ++ int ret; ++ VCHI_INSTANCE_T vchi_instance; ++ VCHI_CONNECTION_T *vchi_connection = NULL; ++ ++ pr_info("[%s]: start\n", __func__); ++ ++ /* Allocate memory for the state structure. ++ */ ++ sm_state = kzalloc(sizeof(struct SM_STATE_T), GFP_KERNEL); ++ if (sm_state == NULL) { ++ pr_err("[%s]: failed to allocate memory\n", __func__); ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ mutex_init(&sm_state->lock); ++ mutex_init(&sm_state->map_lock); ++ ++ /* Initialize and create a VCHI connection for the shared memory service ++ ** running on videocore. ++ */ ++ ret = vchi_initialise(&vchi_instance); ++ if (ret != 0) { ++ pr_err("[%s]: failed to initialise VCHI instance (ret=%d)\n", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ ++ ret = vchi_connect(NULL, 0, vchi_instance); ++ if (ret != 0) { ++ pr_err("[%s]: failed to connect VCHI instance (ret=%d)\n", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ ++ /* Initialize an instance of the shared memory service. */ ++ sm_state->sm_handle = ++ vc_vchi_sm_init(vchi_instance, &vchi_connection, 1); ++ if (sm_state->sm_handle == NULL) { ++ pr_err("[%s]: failed to initialize shared memory service\n", ++ __func__); ++ ++ ret = -EPERM; ++ goto err_free_mem; ++ } ++ ++ /* Create a debug fs directory entry (root). */ ++ sm_state->dir_root = debugfs_create_dir(VC_SM_DIR_ROOT_NAME, NULL); ++ if (!sm_state->dir_root) { ++ pr_err("[%s]: failed to create \'%s\' directory entry\n", ++ __func__, VC_SM_DIR_ROOT_NAME); ++ ++ ret = -EPERM; ++ goto err_stop_sm_service; ++ } ++ ++ sm_state->dir_state.show = &vc_sm_global_state_show; ++ sm_state->dir_state.dir_entry = debugfs_create_file(VC_SM_STATE, ++ S_IRUGO, sm_state->dir_root, &sm_state->dir_state, ++ &vc_sm_debug_fs_fops); ++ ++ sm_state->dir_stats.show = &vc_sm_global_statistics_show; ++ sm_state->dir_stats.dir_entry = debugfs_create_file(VC_SM_STATS, ++ S_IRUGO, sm_state->dir_root, &sm_state->dir_stats, ++ &vc_sm_debug_fs_fops); ++ ++ /* Create the proc entry children. */ ++ sm_state->dir_alloc = debugfs_create_dir(VC_SM_DIR_ALLOC_NAME, ++ sm_state->dir_root); ++ ++ /* Create a shared memory device. */ ++ ret = vc_sm_create_sharedmemory(); ++ if (ret != 0) { ++ pr_err("[%s]: failed to create shared memory device\n", ++ __func__); ++ goto err_remove_debugfs; ++ } ++ ++ INIT_LIST_HEAD(&sm_state->map_list); ++ INIT_LIST_HEAD(&sm_state->resource_list); ++ ++ sm_state->data_knl = vc_sm_create_priv_data(0); ++ if (sm_state->data_knl == NULL) { ++ pr_err("[%s]: failed to create kernel private data tracker\n", ++ __func__); ++ goto err_remove_shared_memory; ++ } ++ ++ /* Done! ++ */ ++ sm_inited = 1; ++ goto out; ++ ++err_remove_shared_memory: ++ vc_sm_remove_sharedmemory(); ++err_remove_debugfs: ++ debugfs_remove_recursive(sm_state->dir_root); ++err_stop_sm_service: ++ vc_vchi_sm_stop(&sm_state->sm_handle); ++err_free_mem: ++ kfree(sm_state); ++out: ++ pr_info("[%s]: end - returning %d\n", __func__, ret); ++} ++ ++/* Driver loading. */ ++static int __init vc_sm_init(void) ++{ ++ pr_info("vc-sm: Videocore shared memory driver\n"); ++ vchiq_add_connected_callback(vc_sm_connected_init); ++ return 0; ++} ++ ++/* Driver unloading. */ ++static void __exit vc_sm_exit(void) ++{ ++ pr_debug("[%s]: start\n", __func__); ++ if (sm_inited) { ++ /* Remove shared memory device. ++ */ ++ vc_sm_remove_sharedmemory(); ++ ++ /* Remove all proc entries. ++ */ ++ debugfs_remove_recursive(sm_state->dir_root); ++ ++ /* Stop the videocore shared memory service. ++ */ ++ vc_vchi_sm_stop(&sm_state->sm_handle); ++ ++ /* Free the memory for the state structure. ++ */ ++ mutex_destroy(&(sm_state->map_lock)); ++ kfree(sm_state); ++ } ++ ++ pr_debug("[%s]: end\n", __func__); ++} ++ ++#if defined(__KERNEL__) ++/* Allocate a shared memory handle and block. */ ++int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle) ++{ ++ struct vmcs_sm_ioctl_alloc ioparam = { 0 }; ++ int ret; ++ struct SM_RESOURCE_T *resource; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || alloc == NULL || handle == NULL) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ ioparam.size = alloc->base_unit; ++ ioparam.num = alloc->num_unit; ++ ioparam.cached = ++ alloc->type == VC_SM_ALLOC_CACHED ? VMCS_SM_CACHE_VC : 0; ++ ++ ret = vc_sm_ioctl_alloc(sm_state->data_knl, &ioparam); ++ ++ if (ret == 0) { ++ resource = ++ vmcs_sm_acquire_resource(sm_state->data_knl, ++ ioparam.handle); ++ if (resource) { ++ resource->pid = 0; ++ vmcs_sm_release_resource(resource, 0); ++ ++ /* Assign valid handle at this time. ++ */ ++ *handle = ioparam.handle; ++ } else { ++ ret = -ENOMEM; ++ } ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(vc_sm_alloc); ++ ++/* Get an internal resource handle mapped from the external one. ++*/ ++int vc_sm_int_handle(int handle) ++{ ++ struct SM_RESOURCE_T *resource; ++ int ret = 0; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return 0; ++ } ++ ++ /* Locate resource from GUID. ++ */ ++ resource = vmcs_sm_acquire_resource(sm_state->data_knl, handle); ++ if (resource) { ++ ret = resource->res_handle; ++ vmcs_sm_release_resource(resource, 0); ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(vc_sm_int_handle); ++ ++/* Free a previously allocated shared memory handle and block. ++*/ ++int vc_sm_free(int handle) ++{ ++ struct vmcs_sm_ioctl_free ioparam = { handle }; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ return vc_sm_ioctl_free(sm_state->data_knl, &ioparam); ++} ++EXPORT_SYMBOL_GPL(vc_sm_free); ++ ++/* Lock a memory handle for use by kernel. ++*/ ++int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode, ++ long unsigned int *data) ++{ ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ int ret; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0 || data == NULL) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ *data = 0; ++ ++ ioparam.handle = handle; ++ ret = vc_sm_ioctl_lock(sm_state->data_knl, ++ &ioparam, ++ 1, ++ ((mode == ++ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST : ++ VMCS_SM_CACHE_NONE), 0); ++ ++ *data = ioparam.addr; ++ return ret; ++} ++EXPORT_SYMBOL_GPL(vc_sm_lock); ++ ++/* Unlock a memory handle in use by kernel. ++*/ ++int vc_sm_unlock(int handle, int flush, int no_vc_unlock) ++{ ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ ioparam.handle = handle; ++ return vc_sm_ioctl_unlock(sm_state->data_knl, ++ &ioparam, flush, 0, no_vc_unlock); ++} ++EXPORT_SYMBOL_GPL(vc_sm_unlock); ++ ++/* Map a shared memory region for use by kernel. ++*/ ++int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode, ++ long unsigned int *data) ++{ ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ int ret; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0 || data == NULL || sm_addr == 0) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ *data = 0; ++ ++ ioparam.handle = handle; ++ ret = vc_sm_ioctl_lock(sm_state->data_knl, ++ &ioparam, ++ 1, ++ ((mode == ++ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST : ++ VMCS_SM_CACHE_NONE), sm_addr); ++ ++ *data = ioparam.addr; ++ return ret; ++} ++EXPORT_SYMBOL_GPL(vc_sm_map); ++#endif ++ ++late_initcall(vc_sm_init); ++module_exit(vc_sm_exit); ++ ++MODULE_AUTHOR("Broadcom"); ++MODULE_DESCRIPTION("VideoCore SharedMemory Driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0015-Add-hwrng-hardware-random-number-generator-driver.patch b/target/linux/brcm2708/patches-4.1/0015-Add-hwrng-hardware-random-number-generator-driver.patch new file mode 100644 index 0000000..a22e219 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0015-Add-hwrng-hardware-random-number-generator-driver.patch @@ -0,0 +1,172 @@ +From 5922c92d5e4be4c4cc9b59d8a8cd2bfeaebdebbb Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 3 Jul 2013 00:51:55 +0100 +Subject: [PATCH 015/203] Add hwrng (hardware random number generator) driver + +--- + drivers/char/hw_random/Kconfig | 13 +++- + drivers/char/hw_random/Makefile | 1 + + drivers/char/hw_random/bcm2708-rng.c | 118 +++++++++++++++++++++++++++++++++++ + 3 files changed, 131 insertions(+), 1 deletion(-) + create mode 100755 drivers/char/hw_random/bcm2708-rng.c + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -90,7 +90,7 @@ config HW_RANDOM_BCM63XX + + config HW_RANDOM_BCM2835 + tristate "Broadcom BCM2835 Random Number Generator support" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + default HW_RANDOM + ---help--- + This driver provides kernel-side support for the Random Number +@@ -333,6 +333,17 @@ config HW_RANDOM_TPM + + If unsure, say Y. + ++config HW_RANDOM_BCM2708 ++ tristate "BCM2708 generic true random number generator support" ++ depends on HW_RANDOM && (ARCH_BCM2708 || ARCH_BCM2709) ++ ---help--- ++ This driver provides the kernel-side support for the BCM2708 hardware. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called bcm2708-rng. ++ ++ If unsure, say N. ++ + config HW_RANDOM_MSM + tristate "Qualcomm SoCs Random Number Generator support" + depends on HW_RANDOM && ARCH_QCOM +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -4,6 +4,7 @@ + + obj-$(CONFIG_HW_RANDOM) += rng-core.o + rng-core-y := core.o ++obj-$(CONFIG_HW_RANDOM_BCM2708) += bcm2708-rng.o + obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o + obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o + obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o +--- /dev/null ++++ b/drivers/char/hw_random/bcm2708-rng.c +@@ -0,0 +1,118 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define RNG_CTRL (0x0) ++#define RNG_STATUS (0x4) ++#define RNG_DATA (0x8) ++#define RNG_FF_THRESHOLD (0xc) ++ ++/* enable rng */ ++#define RNG_RBGEN 0x1 ++/* double speed, less random mode */ ++#define RNG_RBG2X 0x2 ++ ++/* the initial numbers generated are "less random" so will be discarded */ ++#define RNG_WARMUP_COUNT 0x40000 ++ ++static int bcm2708_rng_data_read(struct hwrng *rng, u32 *buffer) ++{ ++ void __iomem *rng_base = (void __iomem *)rng->priv; ++ unsigned words; ++ /* wait for a random number to be in fifo */ ++ do { ++ words = __raw_readl(rng_base + RNG_STATUS)>>24; ++ } ++ while (words == 0); ++ /* read the random number */ ++ *buffer = __raw_readl(rng_base + RNG_DATA); ++ return 4; ++} ++ ++static struct hwrng bcm2708_rng_ops = { ++ .name = "bcm2708", ++ .data_read = bcm2708_rng_data_read, ++}; ++ ++static int __init bcm2708_rng_init(void) ++{ ++ void __iomem *rng_base; ++ int err; ++ ++ /* map peripheral */ ++ rng_base = ioremap(RNG_BASE, 0x10); ++ pr_info("bcm2708_rng_init=%p\n", rng_base); ++ if (!rng_base) { ++ pr_err("bcm2708_rng_init failed to ioremap\n"); ++ return -ENOMEM; ++ } ++ bcm2708_rng_ops.priv = (unsigned long)rng_base; ++ ++ /* set warm-up count & enable */ ++ __raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS); ++ __raw_writel(RNG_RBGEN, rng_base + RNG_CTRL); ++ ++ /* register driver */ ++ err = hwrng_register(&bcm2708_rng_ops); ++ if (err) { ++ pr_err("bcm2708_rng_init hwrng_register()=%d\n", err); ++ iounmap(rng_base); ++ } ++ return err; ++} ++ ++static void __exit bcm2708_rng_exit(void) ++{ ++ void __iomem *rng_base = (void __iomem *)bcm2708_rng_ops.priv; ++ pr_info("bcm2708_rng_exit\n"); ++ /* disable rng hardware */ ++ __raw_writel(0, rng_base + RNG_CTRL); ++ /* unregister driver */ ++ hwrng_unregister(&bcm2708_rng_ops); ++ iounmap(rng_base); ++} ++ ++module_init(bcm2708_rng_init); ++module_exit(bcm2708_rng_exit); ++ ++MODULE_DESCRIPTION("BCM2708 H/W Random Number Generator (RNG) driver"); ++MODULE_LICENSE("GPL and additional rights"); diff --git a/target/linux/brcm2708/patches-4.1/0016-lirc-added-support-for-RaspberryPi-GPIO.patch b/target/linux/brcm2708/patches-4.1/0016-lirc-added-support-for-RaspberryPi-GPIO.patch new file mode 100644 index 0000000..99af70e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0016-lirc-added-support-for-RaspberryPi-GPIO.patch @@ -0,0 +1,848 @@ +From a46ef8c727cf42ab2434d5f19eea7b9a88649d22 Mon Sep 17 00:00:00 2001 +From: Aron Szabo +Date: Sat, 16 Jun 2012 12:15:55 +0200 +Subject: [PATCH 016/203] lirc: added support for RaspberryPi GPIO + +lirc_rpi: Use read_current_timer to determine transmitter delay. Thanks to jjmz and others +See: https://github.com/raspberrypi/linux/issues/525 + +lirc: Remove restriction on gpio pins that can be used with lirc + +Compute Module, for example could use different pins + +lirc_rpi: Add parameter to specify input pin pull + +Depending on the connected IR circuitry it might be desirable to change the +gpios internal pull from it pull-down default behaviour. Add a module +parameter to allow the user to set it explicitly. + +Signed-off-by: Julian Scheel + +lirc-rpi: Use the higher-level irq control functions + +This module used to access the irq_chip methods of the +gpio controller directly, rather than going through the +standard enable_irq/irq_set_irq_type functions. This +caused problems on pinctrl-bcm2835 which only implements +the irq_enable/disable methods and not irq_unmask/mask. + +lirc-rpi: Correct the interrupt usage + +1) Correct the use of enable_irq (i.e. don't call it so often) +2) Correct the shutdown sequence. +3) Avoid a bcm2708_gpio driver quirk by setting the irq flags earlier + +lirc-rpi: use getnstimeofday instead of read_current_timer + +read_current_timer isn't guaranteed to return values in +microseconds, and indeed it doesn't on a Pi2. + +Issue: linux#827 + +lirc-rpi: Add device tree support, and a suitable overlay + +The overlay supports DT parameters that match the old module +parameters, except that gpio_in_pull should be set using the +strings "up", "down" or "off". + +lirc-rpi: Also support pinctrl-bcm2835 in non-DT mode +--- + drivers/staging/media/lirc/Kconfig | 6 + + drivers/staging/media/lirc/Makefile | 1 + + drivers/staging/media/lirc/lirc_rpi.c | 765 ++++++++++++++++++++++++++++++++++ + 3 files changed, 772 insertions(+) + create mode 100644 drivers/staging/media/lirc/lirc_rpi.c + +--- a/drivers/staging/media/lirc/Kconfig ++++ b/drivers/staging/media/lirc/Kconfig +@@ -32,6 +32,12 @@ config LIRC_PARALLEL + help + Driver for Homebrew Parallel Port Receivers + ++config LIRC_RPI ++ tristate "Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi" ++ depends on LIRC ++ help ++ Driver for Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi ++ + config LIRC_SASEM + tristate "Sasem USB IR Remote" + depends on LIRC && USB +--- a/drivers/staging/media/lirc/Makefile ++++ b/drivers/staging/media/lirc/Makefile +@@ -6,6 +6,7 @@ + obj-$(CONFIG_LIRC_BT829) += lirc_bt829.o + obj-$(CONFIG_LIRC_IMON) += lirc_imon.o + obj-$(CONFIG_LIRC_PARALLEL) += lirc_parallel.o ++obj-$(CONFIG_LIRC_RPI) += lirc_rpi.o + obj-$(CONFIG_LIRC_SASEM) += lirc_sasem.o + obj-$(CONFIG_LIRC_SERIAL) += lirc_serial.o + obj-$(CONFIG_LIRC_SIR) += lirc_sir.o +--- /dev/null ++++ b/drivers/staging/media/lirc/lirc_rpi.c +@@ -0,0 +1,765 @@ ++/* ++ * lirc_rpi.c ++ * ++ * lirc_rpi - Device driver that records pulse- and pause-lengths ++ * (space-lengths) (just like the lirc_serial driver does) ++ * between GPIO interrupt events on the Raspberry Pi. ++ * Lots of code has been taken from the lirc_serial module, ++ * so I would like say thanks to the authors. ++ * ++ * Copyright (C) 2012 Aron Robert Szabo , ++ * Michael Bishop ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define LIRC_DRIVER_NAME "lirc_rpi" ++#define RBUF_LEN 256 ++#define LIRC_TRANSMITTER_LATENCY 50 ++ ++#ifndef MAX_UDELAY_MS ++#define MAX_UDELAY_US 5000 ++#else ++#define MAX_UDELAY_US (MAX_UDELAY_MS*1000) ++#endif ++ ++#define dprintk(fmt, args...) \ ++ do { \ ++ if (debug) \ ++ printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ ++ fmt, ## args); \ ++ } while (0) ++ ++/* module parameters */ ++ ++/* set the default GPIO input pin */ ++static int gpio_in_pin = 18; ++/* set the default pull behaviour for input pin */ ++static int gpio_in_pull = BCM2708_PULL_DOWN; ++/* set the default GPIO output pin */ ++static int gpio_out_pin = 17; ++/* enable debugging messages */ ++static bool debug; ++/* -1 = auto, 0 = active high, 1 = active low */ ++static int sense = -1; ++/* use softcarrier by default */ ++static bool softcarrier = 1; ++/* 0 = do not invert output, 1 = invert output */ ++static bool invert = 0; ++ ++struct gpio_chip *gpiochip; ++static int irq_num; ++ ++/* forward declarations */ ++static long send_pulse(unsigned long length); ++static void send_space(long length); ++static void lirc_rpi_exit(void); ++ ++static struct platform_device *lirc_rpi_dev; ++static struct timeval lasttv = { 0, 0 }; ++static struct lirc_buffer rbuf; ++static spinlock_t lock; ++ ++/* initialized/set in init_timing_params() */ ++static unsigned int freq = 38000; ++static unsigned int duty_cycle = 50; ++static unsigned long period; ++static unsigned long pulse_width; ++static unsigned long space_width; ++ ++static void safe_udelay(unsigned long usecs) ++{ ++ while (usecs > MAX_UDELAY_US) { ++ udelay(MAX_UDELAY_US); ++ usecs -= MAX_UDELAY_US; ++ } ++ udelay(usecs); ++} ++ ++static unsigned long read_current_us(void) ++{ ++ struct timespec now; ++ getnstimeofday(&now); ++ return (now.tv_sec * 1000000) + (now.tv_nsec/1000); ++} ++ ++static int init_timing_params(unsigned int new_duty_cycle, ++ unsigned int new_freq) ++{ ++ if (1000 * 1000000L / new_freq * new_duty_cycle / 100 <= ++ LIRC_TRANSMITTER_LATENCY) ++ return -EINVAL; ++ if (1000 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <= ++ LIRC_TRANSMITTER_LATENCY) ++ return -EINVAL; ++ duty_cycle = new_duty_cycle; ++ freq = new_freq; ++ period = 1000 * 1000000L / freq; ++ pulse_width = period * duty_cycle / 100; ++ space_width = period - pulse_width; ++ dprintk("in init_timing_params, freq=%d pulse=%ld, " ++ "space=%ld\n", freq, pulse_width, space_width); ++ return 0; ++} ++ ++static long send_pulse_softcarrier(unsigned long length) ++{ ++ int flag; ++ unsigned long actual, target; ++ unsigned long actual_us, initial_us, target_us; ++ ++ length *= 1000; ++ ++ actual = 0; target = 0; flag = 0; ++ actual_us = read_current_us(); ++ ++ while (actual < length) { ++ if (flag) { ++ gpiochip->set(gpiochip, gpio_out_pin, invert); ++ target += space_width; ++ } else { ++ gpiochip->set(gpiochip, gpio_out_pin, !invert); ++ target += pulse_width; ++ } ++ initial_us = actual_us; ++ target_us = actual_us + (target - actual) / 1000; ++ /* ++ * Note - we've checked in ioctl that the pulse/space ++ * widths are big enough so that d is > 0 ++ */ ++ if ((int)(target_us - actual_us) > 0) ++ udelay(target_us - actual_us); ++ actual_us = read_current_us(); ++ actual += (actual_us - initial_us) * 1000; ++ flag = !flag; ++ } ++ return (actual-length) / 1000; ++} ++ ++static long send_pulse(unsigned long length) ++{ ++ if (length <= 0) ++ return 0; ++ ++ if (softcarrier) { ++ return send_pulse_softcarrier(length); ++ } else { ++ gpiochip->set(gpiochip, gpio_out_pin, !invert); ++ safe_udelay(length); ++ return 0; ++ } ++} ++ ++static void send_space(long length) ++{ ++ gpiochip->set(gpiochip, gpio_out_pin, invert); ++ if (length <= 0) ++ return; ++ safe_udelay(length); ++} ++ ++static void rbwrite(int l) ++{ ++ if (lirc_buffer_full(&rbuf)) { ++ /* no new signals will be accepted */ ++ dprintk("Buffer overrun\n"); ++ return; ++ } ++ lirc_buffer_write(&rbuf, (void *)&l); ++} ++ ++static void frbwrite(int l) ++{ ++ /* simple noise filter */ ++ static int pulse, space; ++ static unsigned int ptr; ++ ++ if (ptr > 0 && (l & PULSE_BIT)) { ++ pulse += l & PULSE_MASK; ++ if (pulse > 250) { ++ rbwrite(space); ++ rbwrite(pulse | PULSE_BIT); ++ ptr = 0; ++ pulse = 0; ++ } ++ return; ++ } ++ if (!(l & PULSE_BIT)) { ++ if (ptr == 0) { ++ if (l > 20000) { ++ space = l; ++ ptr++; ++ return; ++ } ++ } else { ++ if (l > 20000) { ++ space += pulse; ++ if (space > PULSE_MASK) ++ space = PULSE_MASK; ++ space += l; ++ if (space > PULSE_MASK) ++ space = PULSE_MASK; ++ pulse = 0; ++ return; ++ } ++ rbwrite(space); ++ rbwrite(pulse | PULSE_BIT); ++ ptr = 0; ++ pulse = 0; ++ } ++ } ++ rbwrite(l); ++} ++ ++static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs) ++{ ++ struct timeval tv; ++ long deltv; ++ int data; ++ int signal; ++ ++ /* use the GPIO signal level */ ++ signal = gpiochip->get(gpiochip, gpio_in_pin); ++ ++ if (sense != -1) { ++ /* get current time */ ++ do_gettimeofday(&tv); ++ ++ /* calc time since last interrupt in microseconds */ ++ deltv = tv.tv_sec-lasttv.tv_sec; ++ if (tv.tv_sec < lasttv.tv_sec || ++ (tv.tv_sec == lasttv.tv_sec && ++ tv.tv_usec < lasttv.tv_usec)) { ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": AIEEEE: your clock just jumped backwards\n"); ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": %d %d %lx %lx %lx %lx\n", signal, sense, ++ tv.tv_sec, lasttv.tv_sec, ++ tv.tv_usec, lasttv.tv_usec); ++ data = PULSE_MASK; ++ } else if (deltv > 15) { ++ data = PULSE_MASK; /* really long time */ ++ if (!(signal^sense)) { ++ /* sanity check */ ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": AIEEEE: %d %d %lx %lx %lx %lx\n", ++ signal, sense, tv.tv_sec, lasttv.tv_sec, ++ tv.tv_usec, lasttv.tv_usec); ++ /* ++ * detecting pulse while this ++ * MUST be a space! ++ */ ++ sense = sense ? 0 : 1; ++ } ++ } else { ++ data = (int) (deltv*1000000 + ++ (tv.tv_usec - lasttv.tv_usec)); ++ } ++ frbwrite(signal^sense ? data : (data|PULSE_BIT)); ++ lasttv = tv; ++ wake_up_interruptible(&rbuf.wait_poll); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int is_right_chip(struct gpio_chip *chip, void *data) ++{ ++ dprintk("is_right_chip %s %d\n", chip->label, strcmp(data, chip->label)); ++ ++ if (strcmp(data, chip->label) == 0) ++ return 1; ++ return 0; ++} ++ ++static inline int read_bool_property(const struct device_node *np, ++ const char *propname, ++ bool *out_value) ++{ ++ u32 value = 0; ++ int err = of_property_read_u32(np, propname, &value); ++ if (err == 0) ++ *out_value = (value != 0); ++ return err; ++} ++ ++static void read_pin_settings(struct device_node *node) ++{ ++ u32 pin; ++ int index; ++ ++ for (index = 0; ++ of_property_read_u32_index( ++ node, ++ "brcm,pins", ++ index, ++ &pin) == 0; ++ index++) { ++ u32 function; ++ int err; ++ err = of_property_read_u32_index( ++ node, ++ "brcm,function", ++ index, ++ &function); ++ if (err == 0) { ++ if (function == 1) /* Output */ ++ gpio_out_pin = pin; ++ else if (function == 0) /* Input */ ++ gpio_in_pin = pin; ++ } ++ } ++} ++ ++static int init_port(void) ++{ ++ int i, nlow, nhigh, ret; ++ struct device_node *node; ++ ++ node = lirc_rpi_dev->dev.of_node; ++ ++ gpiochip = gpiochip_find("bcm2708_gpio", is_right_chip); ++ ++ /* ++ * Because of the lack of a setpull function, only support ++ * pinctrl-bcm2835 if using device tree. ++ */ ++ if (!gpiochip && node) ++ gpiochip = gpiochip_find("pinctrl-bcm2835", is_right_chip); ++ ++ if (!gpiochip) { ++ pr_err(LIRC_DRIVER_NAME ": gpio chip not found!\n"); ++ return -ENODEV; ++ } ++ ++ if (node) { ++ struct device_node *pins_node; ++ ++ pins_node = of_parse_phandle(node, "pinctrl-0", 0); ++ if (!pins_node) { ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": pinctrl settings not found!\n"); ++ ret = -EINVAL; ++ goto exit_init_port; ++ } ++ ++ read_pin_settings(pins_node); ++ ++ of_property_read_u32(node, "rpi,sense", &sense); ++ ++ read_bool_property(node, "rpi,softcarrier", &softcarrier); ++ ++ read_bool_property(node, "rpi,invert", &invert); ++ ++ read_bool_property(node, "rpi,debug", &debug); ++ ++ } ++ else ++ { ++ if (gpio_in_pin >= BCM2708_NR_GPIOS || ++ gpio_out_pin >= BCM2708_NR_GPIOS) { ++ ret = -EINVAL; ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": invalid GPIO pin(s) specified!\n"); ++ goto exit_init_port; ++ } ++ ++ if (gpio_request(gpio_out_pin, LIRC_DRIVER_NAME " ir/out")) { ++ printk(KERN_ALERT LIRC_DRIVER_NAME ++ ": cant claim gpio pin %d\n", gpio_out_pin); ++ ret = -ENODEV; ++ goto exit_init_port; ++ } ++ ++ if (gpio_request(gpio_in_pin, LIRC_DRIVER_NAME " ir/in")) { ++ printk(KERN_ALERT LIRC_DRIVER_NAME ++ ": cant claim gpio pin %d\n", gpio_in_pin); ++ ret = -ENODEV; ++ goto exit_gpio_free_out_pin; ++ } ++ ++ bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull); ++ gpiochip->direction_input(gpiochip, gpio_in_pin); ++ gpiochip->direction_output(gpiochip, gpio_out_pin, 1); ++ } ++ ++ gpiochip->set(gpiochip, gpio_out_pin, invert); ++ ++ irq_num = gpiochip->to_irq(gpiochip, gpio_in_pin); ++ dprintk("to_irq %d\n", irq_num); ++ ++ /* if pin is high, then this must be an active low receiver. */ ++ if (sense == -1) { ++ /* wait 1/2 sec for the power supply */ ++ msleep(500); ++ ++ /* ++ * probe 9 times every 0.04s, collect "votes" for ++ * active high/low ++ */ ++ nlow = 0; ++ nhigh = 0; ++ for (i = 0; i < 9; i++) { ++ if (gpiochip->get(gpiochip, gpio_in_pin)) ++ nlow++; ++ else ++ nhigh++; ++ msleep(40); ++ } ++ sense = (nlow >= nhigh ? 1 : 0); ++ printk(KERN_INFO LIRC_DRIVER_NAME ++ ": auto-detected active %s receiver on GPIO pin %d\n", ++ sense ? "low" : "high", gpio_in_pin); ++ } else { ++ printk(KERN_INFO LIRC_DRIVER_NAME ++ ": manually using active %s receiver on GPIO pin %d\n", ++ sense ? "low" : "high", gpio_in_pin); ++ } ++ ++ return 0; ++ ++ exit_gpio_free_out_pin: ++ gpio_free(gpio_out_pin); ++ ++ exit_init_port: ++ return ret; ++} ++ ++// called when the character device is opened ++static int set_use_inc(void *data) ++{ ++ int result; ++ ++ /* initialize timestamp */ ++ do_gettimeofday(&lasttv); ++ ++ result = request_irq(irq_num, ++ (irq_handler_t) irq_handler, ++ IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING, ++ LIRC_DRIVER_NAME, (void*) 0); ++ ++ switch (result) { ++ case -EBUSY: ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": IRQ %d is busy\n", ++ irq_num); ++ return -EBUSY; ++ case -EINVAL: ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": Bad irq number or handler\n"); ++ return -EINVAL; ++ default: ++ dprintk("Interrupt %d obtained\n", ++ irq_num); ++ break; ++ }; ++ ++ /* initialize pulse/space widths */ ++ init_timing_params(duty_cycle, freq); ++ ++ return 0; ++} ++ ++static void set_use_dec(void *data) ++{ ++ /* GPIO Pin Falling/Rising Edge Detect Disable */ ++ irq_set_irq_type(irq_num, 0); ++ disable_irq(irq_num); ++ ++ free_irq(irq_num, (void *) 0); ++ ++ dprintk(KERN_INFO LIRC_DRIVER_NAME ++ ": freed IRQ %d\n", irq_num); ++} ++ ++static ssize_t lirc_write(struct file *file, const char *buf, ++ size_t n, loff_t *ppos) ++{ ++ int i, count; ++ unsigned long flags; ++ long delta = 0; ++ int *wbuf; ++ ++ count = n / sizeof(int); ++ if (n % sizeof(int) || count % 2 == 0) ++ return -EINVAL; ++ wbuf = memdup_user(buf, n); ++ if (IS_ERR(wbuf)) ++ return PTR_ERR(wbuf); ++ spin_lock_irqsave(&lock, flags); ++ ++ for (i = 0; i < count; i++) { ++ if (i%2) ++ send_space(wbuf[i] - delta); ++ else ++ delta = send_pulse(wbuf[i]); ++ } ++ gpiochip->set(gpiochip, gpio_out_pin, invert); ++ ++ spin_unlock_irqrestore(&lock, flags); ++ kfree(wbuf); ++ return n; ++} ++ ++static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) ++{ ++ int result; ++ __u32 value; ++ ++ switch (cmd) { ++ case LIRC_GET_SEND_MODE: ++ return -ENOIOCTLCMD; ++ break; ++ ++ case LIRC_SET_SEND_MODE: ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ /* only LIRC_MODE_PULSE supported */ ++ if (value != LIRC_MODE_PULSE) ++ return -ENOSYS; ++ break; ++ ++ case LIRC_GET_LENGTH: ++ return -ENOSYS; ++ break; ++ ++ case LIRC_SET_SEND_DUTY_CYCLE: ++ dprintk("SET_SEND_DUTY_CYCLE\n"); ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ if (value <= 0 || value > 100) ++ return -EINVAL; ++ return init_timing_params(value, freq); ++ break; ++ ++ case LIRC_SET_SEND_CARRIER: ++ dprintk("SET_SEND_CARRIER\n"); ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ if (value > 500000 || value < 20000) ++ return -EINVAL; ++ return init_timing_params(duty_cycle, value); ++ break; ++ ++ default: ++ return lirc_dev_fop_ioctl(filep, cmd, arg); ++ } ++ return 0; ++} ++ ++static const struct file_operations lirc_fops = { ++ .owner = THIS_MODULE, ++ .write = lirc_write, ++ .unlocked_ioctl = lirc_ioctl, ++ .read = lirc_dev_fop_read, ++ .poll = lirc_dev_fop_poll, ++ .open = lirc_dev_fop_open, ++ .release = lirc_dev_fop_close, ++ .llseek = no_llseek, ++}; ++ ++static struct lirc_driver driver = { ++ .name = LIRC_DRIVER_NAME, ++ .minor = -1, ++ .code_length = 1, ++ .sample_rate = 0, ++ .data = NULL, ++ .add_to_buf = NULL, ++ .rbuf = &rbuf, ++ .set_use_inc = set_use_inc, ++ .set_use_dec = set_use_dec, ++ .fops = &lirc_fops, ++ .dev = NULL, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct of_device_id lirc_rpi_of_match[] = { ++ { .compatible = "rpi,lirc-rpi", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, lirc_rpi_of_match); ++ ++static struct platform_driver lirc_rpi_driver = { ++ .driver = { ++ .name = LIRC_DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(lirc_rpi_of_match), ++ }, ++}; ++ ++static int __init lirc_rpi_init(void) ++{ ++ struct device_node *node; ++ int result; ++ ++ /* Init read buffer. */ ++ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN); ++ if (result < 0) ++ return -ENOMEM; ++ ++ result = platform_driver_register(&lirc_rpi_driver); ++ if (result) { ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": lirc register returned %d\n", result); ++ goto exit_buffer_free; ++ } ++ ++ node = of_find_compatible_node(NULL, NULL, ++ lirc_rpi_of_match[0].compatible); ++ ++ if (node) { ++ /* DT-enabled */ ++ lirc_rpi_dev = of_find_device_by_node(node); ++ WARN_ON(lirc_rpi_dev->dev.of_node != node); ++ of_node_put(node); ++ } ++ else { ++ lirc_rpi_dev = platform_device_alloc(LIRC_DRIVER_NAME, 0); ++ if (!lirc_rpi_dev) { ++ result = -ENOMEM; ++ goto exit_driver_unregister; ++ } ++ ++ result = platform_device_add(lirc_rpi_dev); ++ if (result) ++ goto exit_device_put; ++ } ++ ++ return 0; ++ ++ exit_device_put: ++ platform_device_put(lirc_rpi_dev); ++ ++ exit_driver_unregister: ++ platform_driver_unregister(&lirc_rpi_driver); ++ ++ exit_buffer_free: ++ lirc_buffer_free(&rbuf); ++ ++ return result; ++} ++ ++static void lirc_rpi_exit(void) ++{ ++ if (!lirc_rpi_dev->dev.of_node) ++ platform_device_unregister(lirc_rpi_dev); ++ platform_driver_unregister(&lirc_rpi_driver); ++ lirc_buffer_free(&rbuf); ++} ++ ++static int __init lirc_rpi_init_module(void) ++{ ++ int result; ++ ++ result = lirc_rpi_init(); ++ if (result) ++ return result; ++ ++ result = init_port(); ++ if (result < 0) ++ goto exit_rpi; ++ ++ driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE | ++ LIRC_CAN_SET_SEND_CARRIER | ++ LIRC_CAN_SEND_PULSE | ++ LIRC_CAN_REC_MODE2; ++ ++ driver.dev = &lirc_rpi_dev->dev; ++ driver.minor = lirc_register_driver(&driver); ++ ++ if (driver.minor < 0) { ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": device registration failed with %d\n", result); ++ result = -EIO; ++ goto exit_rpi; ++ } ++ ++ printk(KERN_INFO LIRC_DRIVER_NAME ": driver registered!\n"); ++ ++ return 0; ++ ++ exit_rpi: ++ lirc_rpi_exit(); ++ ++ return result; ++} ++ ++static void __exit lirc_rpi_exit_module(void) ++{ ++ lirc_unregister_driver(driver.minor); ++ ++ gpio_free(gpio_out_pin); ++ gpio_free(gpio_in_pin); ++ ++ lirc_rpi_exit(); ++ ++ printk(KERN_INFO LIRC_DRIVER_NAME ": cleaned up module\n"); ++} ++ ++module_init(lirc_rpi_init_module); ++module_exit(lirc_rpi_exit_module); ++ ++MODULE_DESCRIPTION("Infra-red receiver and blaster driver for Raspberry Pi GPIO."); ++MODULE_AUTHOR("Aron Robert Szabo "); ++MODULE_AUTHOR("Michael Bishop "); ++MODULE_LICENSE("GPL"); ++ ++module_param(gpio_out_pin, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM" ++ " processor. (default 17"); ++ ++module_param(gpio_in_pin, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor." ++ " (default 18"); ++ ++module_param(gpio_in_pull, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration." ++ " (0 = off, 1 = up, 2 = down, default down)"); ++ ++module_param(sense, int, S_IRUGO); ++MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit" ++ " (0 = active high, 1 = active low )"); ++ ++module_param(softcarrier, bool, S_IRUGO); ++MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)"); ++ ++module_param(invert, bool, S_IRUGO); ++MODULE_PARM_DESC(invert, "Invert output (0 = off, 1 = on, default off"); ++ ++module_param(debug, bool, S_IRUGO | S_IWUSR); ++MODULE_PARM_DESC(debug, "Enable debugging messages"); diff --git a/target/linux/brcm2708/patches-4.1/0017-Add-cpufreq-driver.patch b/target/linux/brcm2708/patches-4.1/0017-Add-cpufreq-driver.patch new file mode 100644 index 0000000..ef12d45 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0017-Add-cpufreq-driver.patch @@ -0,0 +1,268 @@ +From 048e47374e6f6d6f10850316a07159e88b9ed406 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 3 Jul 2013 00:49:20 +0100 +Subject: [PATCH 017/203] Add cpufreq driver + +Signed-off-by: popcornmix +--- + drivers/cpufreq/Kconfig.arm | 9 ++ + drivers/cpufreq/Makefile | 1 + + drivers/cpufreq/bcm2835-cpufreq.c | 224 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 234 insertions(+) + create mode 100644 drivers/cpufreq/bcm2835-cpufreq.c + +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -258,6 +258,15 @@ config ARM_SPEAR_CPUFREQ + help + This adds the CPUFreq driver support for SPEAr SOCs. + ++config ARM_BCM2835_CPUFREQ ++ depends on BCM2708_MBOX ++ bool "BCM2835 Driver" ++ default y ++ help ++ This adds the CPUFreq driver for BCM2835 ++ ++ If in doubt, say N. ++ + config ARM_TEGRA_CPUFREQ + bool "TEGRA CPUFreq support" + depends on ARCH_TEGRA +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -77,6 +77,7 @@ obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5p + obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o + obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o + obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o ++obj-$(CONFIG_ARM_BCM2835_CPUFREQ) += bcm2835-cpufreq.o + obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o + obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o + +--- /dev/null ++++ b/drivers/cpufreq/bcm2835-cpufreq.c +@@ -0,0 +1,224 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/***************************************************************************** ++* FILENAME: bcm2835-cpufreq.h ++* DESCRIPTION: This driver dynamically manages the CPU Frequency of the ARM ++* processor. Messages are sent to Videocore either setting or requesting the ++* frequency of the ARM in order to match an appropiate frequency to the current ++* usage of the processor. The policy which selects the frequency to use is ++* defined in the kernel .config file, but can be changed during runtime. ++*****************************************************************************/ ++ ++/* ---------- INCLUDES ---------- */ ++#include ++#include ++#include ++#include ++#include ++ ++/* ---------- DEFINES ---------- */ ++/*#define CPUFREQ_DEBUG_ENABLE*/ /* enable debugging */ ++#define MODULE_NAME "bcm2835-cpufreq" ++ ++#define VCMSG_ID_ARM_CLOCK 0x000000003 /* Clock/Voltage ID's */ ++ ++/* debug printk macros */ ++#ifdef CPUFREQ_DEBUG_ENABLE ++#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++#define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) ++#define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__) ++ ++/* tag part of the message */ ++struct vc_msg_tag { ++ uint32_t tag_id; /* the message id */ ++ uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */ ++ uint32_t data_size; /* amount of data being sent or received */ ++ uint32_t dev_id; /* the ID of the clock/voltage to get or set */ ++ uint32_t val; /* the value (e.g. rate (in Hz)) to set */ ++}; ++ ++/* message structure to be sent to videocore */ ++struct vc_msg { ++ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ ++ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ ++ struct vc_msg_tag tag; /* the tag structure above to make */ ++ uint32_t end_tag; /* an end identifier, should be set to NULL */ ++}; ++ ++/* ---------- GLOBALS ---------- */ ++static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */ ++ ++static struct cpufreq_frequency_table bcm2835_freq_table[] = { ++ {0, 0, 0}, ++ {0, 0, 0}, ++ {0, 0, CPUFREQ_TABLE_END}, ++}; ++ ++/* ++ =============================================== ++ clk_rate either gets or sets the clock rates. ++ =============================================== ++*/ ++static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate) ++{ ++ int s, actual_rate=0; ++ struct vc_msg msg; ++ ++ /* wipe all previous message data */ ++ memset(&msg, 0, sizeof msg); ++ ++ msg.msg_size = sizeof msg; ++ ++ msg.tag.tag_id = VCMSG_SET_CLOCK_RATE; ++ msg.tag.buffer_size = 8; ++ msg.tag.data_size = 8; /* we're sending the clock ID and the new rates which is a total of 2 words */ ++ msg.tag.dev_id = VCMSG_ID_ARM_CLOCK; ++ msg.tag.val = arm_rate * 1000; ++ ++ /* send the message */ ++ s = bcm_mailbox_property(&msg, sizeof msg); ++ ++ /* check if it was all ok and return the rate in KHz */ ++ if (s == 0 && (msg.request_code & 0x80000000)) ++ actual_rate = msg.tag.val/1000; ++ ++ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, actual_rate); ++ return actual_rate; ++} ++ ++static uint32_t bcm2835_cpufreq_get_clock(int tag) ++{ ++ int s; ++ int arm_rate = 0; ++ struct vc_msg msg; ++ ++ /* wipe all previous message data */ ++ memset(&msg, 0, sizeof msg); ++ ++ msg.msg_size = sizeof msg; ++ msg.tag.tag_id = tag; ++ msg.tag.buffer_size = 8; ++ msg.tag.data_size = 4; /* we're just sending the clock ID which is one word long */ ++ msg.tag.dev_id = VCMSG_ID_ARM_CLOCK; ++ ++ /* send the message */ ++ s = bcm_mailbox_property(&msg, sizeof msg); ++ ++ /* check if it was all ok and return the rate in KHz */ ++ if (s == 0 && (msg.request_code & 0x80000000)) ++ arm_rate = msg.tag.val/1000; ++ ++ print_debug("%s frequency = %d\n", ++ tag == VCMSG_GET_CLOCK_RATE ? "Current": ++ tag == VCMSG_GET_MIN_CLOCK ? "Min": ++ tag == VCMSG_GET_MAX_CLOCK ? "Max": ++ "Unexpected", arm_rate); ++ ++ return arm_rate; ++} ++ ++/* ++ ==================================================== ++ Module Initialisation registers the cpufreq driver ++ ==================================================== ++*/ ++static int __init bcm2835_cpufreq_module_init(void) ++{ ++ print_debug("IN\n"); ++ return cpufreq_register_driver(&bcm2835_cpufreq_driver); ++} ++ ++/* ++ ============= ++ Module exit ++ ============= ++*/ ++static void __exit bcm2835_cpufreq_module_exit(void) ++{ ++ print_debug("IN\n"); ++ cpufreq_unregister_driver(&bcm2835_cpufreq_driver); ++ return; ++} ++ ++/* ++ ============================================================== ++ Initialisation function sets up the CPU policy for first use ++ ============================================================== ++*/ ++static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy) ++{ ++ /* measured value of how long it takes to change frequency */ ++ const unsigned int transition_latency = 355000; /* ns */ ++ ++ /* now find out what the maximum and minimum frequencies are */ ++ bcm2835_freq_table[0].frequency = bcm2835_cpufreq_get_clock(VCMSG_GET_MIN_CLOCK); ++ bcm2835_freq_table[1].frequency = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK); ++ ++ print_info("min=%d max=%d\n", bcm2835_freq_table[0].frequency, bcm2835_freq_table[1].frequency); ++ return cpufreq_generic_init(policy, bcm2835_freq_table, transition_latency); ++} ++ ++/* ++ ===================================================================== ++ Target index function chooses the requested frequency from the table ++ ===================================================================== ++*/ ++ ++static int bcm2835_cpufreq_driver_target_index(struct cpufreq_policy *policy, unsigned int state) ++{ ++ unsigned int target_freq = bcm2835_freq_table[state].frequency; ++ unsigned int cur = bcm2835_cpufreq_set_clock(policy->cur, target_freq); ++ ++ if (!cur) ++ { ++ print_err("Error occurred setting a new frequency (%d)\n", target_freq); ++ return -EINVAL; ++ } ++ print_debug("%s: %i: freq %d->%d\n", policy->governor->name, state, policy->cur, cur); ++ return 0; ++} ++ ++/* ++ ====================================================== ++ Get function returns the current frequency from table ++ ====================================================== ++*/ ++ ++static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) ++{ ++ unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); ++ print_debug("%d: freq=%d\n", cpu, actual_rate); ++ return actual_rate <= bcm2835_freq_table[0].frequency ? bcm2835_freq_table[0].frequency : bcm2835_freq_table[1].frequency; ++} ++ ++/* the CPUFreq driver */ ++static struct cpufreq_driver bcm2835_cpufreq_driver = { ++ .name = "BCM2835 CPUFreq", ++ .init = bcm2835_cpufreq_driver_init, ++ .verify = cpufreq_generic_frequency_table_verify, ++ .target_index = bcm2835_cpufreq_driver_target_index, ++ .get = bcm2835_cpufreq_driver_get, ++ .attr = cpufreq_generic_attr, ++}; ++ ++MODULE_AUTHOR("Dorian Peake and Dom Cobley"); ++MODULE_DESCRIPTION("CPU frequency driver for BCM2835 chip"); ++MODULE_LICENSE("GPL"); ++ ++module_init(bcm2835_cpufreq_module_init); ++module_exit(bcm2835_cpufreq_module_exit); diff --git a/target/linux/brcm2708/patches-4.1/0018-Added-hwmon-thermal-driver-for-reporting-core-temper.patch b/target/linux/brcm2708/patches-4.1/0018-Added-hwmon-thermal-driver-for-reporting-core-temper.patch new file mode 100644 index 0000000..14595f1 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0018-Added-hwmon-thermal-driver-for-reporting-core-temper.patch @@ -0,0 +1,288 @@ +From 5298ba74d7c98c9b4dcb5eebdb5528fec4512cba Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Tue, 26 Mar 2013 19:24:24 +0000 +Subject: [PATCH 018/203] Added hwmon/thermal driver for reporting core + temperature. Thanks Dorian +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +BCM270x: Move thermal sensor to Device Tree + +Add Device Tree support to bcm2835-thermal driver. +Add thermal sensor device to Device Tree. +Don't add platform device when booting in DT mode. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/mach-bcm2708/bcm2708.c | 6 ++ + arch/arm/mach-bcm2709/bcm2709.c | 6 ++ + drivers/thermal/Kconfig | 7 ++ + drivers/thermal/Makefile | 1 + + drivers/thermal/bcm2835-thermal.c | 190 ++++++++++++++++++++++++++++++++++++++ + 5 files changed, 210 insertions(+) + create mode 100644 drivers/thermal/bcm2835-thermal.c + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -505,6 +505,10 @@ static struct platform_device bcm2708_al + }, + }; + ++static struct platform_device bcm2835_thermal_device = { ++ .name = "bcm2835_thermal", ++}; ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -651,6 +655,8 @@ void __init bcm2708_init(void) + for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) + bcm_register_device_dt(&bcm2708_alsa_devices[i]); + ++ bcm_register_device_dt(&bcm2835_thermal_device); ++ + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -525,6 +525,10 @@ static struct platform_device bcm2708_al + }, + }; + ++static struct platform_device bcm2835_thermal_device = { ++ .name = "bcm2835_thermal", ++}; ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -671,6 +675,8 @@ void __init bcm2709_init(void) + for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) + bcm_register_device_dt(&bcm2708_alsa_devices[i]); + ++ bcm_register_device_dt(&bcm2835_thermal_device); ++ + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -238,6 +238,13 @@ config INTEL_POWERCLAMP + enforce idle time which results in more package C-state residency. The + user interface is exposed via generic thermal framework. + ++config THERMAL_BCM2835 ++ depends on BCM2708_MBOX ++ tristate "BCM2835 Thermal Driver" ++ help ++ This will enable temperature monitoring for the Broadcom BCM2835 ++ chip. If built as a module, it will be called 'bcm2835-thermal'. ++ + config X86_PKG_TEMP_THERMAL + tristate "X86 package temperature thermal driver" + depends on X86_THERMAL_VECTOR +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_ARMADA_THERMAL) += armada_t + obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o + obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o + obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o ++obj-$(CONFIG_THERMAL_BCM2835) += bcm2835-thermal.o + obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o + obj-$(CONFIG_INTEL_SOC_DTS_THERMAL) += intel_soc_dts_thermal.o + obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/ +--- /dev/null ++++ b/drivers/thermal/bcm2835-thermal.c +@@ -0,0 +1,190 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++/* --- DEFINITIONS --- */ ++#define MODULE_NAME "bcm2835_thermal" ++ ++/*#define THERMAL_DEBUG_ENABLE*/ ++ ++#ifdef THERMAL_DEBUG_ENABLE ++#define print_debug(fmt,...) printk(KERN_INFO "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++#define print_err(fmt,...) printk(KERN_ERR "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) ++ ++#define VC_TAG_GET_TEMP 0x00030006 ++#define VC_TAG_GET_MAX_TEMP 0x0003000A ++ ++typedef enum { ++ TEMP, ++ MAX_TEMP, ++} temp_type; ++ ++/* --- STRUCTS --- */ ++/* tag part of the message */ ++struct vc_msg_tag { ++ uint32_t tag_id; /* the tag ID for the temperature */ ++ uint32_t buffer_size; /* size of the buffer (should be 8) */ ++ uint32_t request_code; /* identifies message as a request (should be 0) */ ++ uint32_t id; /* extra ID field (should be 0) */ ++ uint32_t val; /* returned value of the temperature */ ++}; ++ ++/* message structure to be sent to videocore */ ++struct vc_msg { ++ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ ++ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ ++ struct vc_msg_tag tag; /* the tag structure above to make */ ++ uint32_t end_tag; /* an end identifier, should be set to NULL */ ++}; ++ ++struct bcm2835_thermal_data { ++ struct thermal_zone_device *thermal_dev; ++ struct vc_msg msg; ++}; ++ ++/* --- GLOBALS --- */ ++static struct bcm2835_thermal_data bcm2835_data; ++ ++/* Thermal Device Operations */ ++static struct thermal_zone_device_ops ops; ++ ++/* --- FUNCTIONS --- */ ++ ++static int bcm2835_get_temp_or_max(struct thermal_zone_device *thermal_dev, unsigned long *temp, unsigned tag_id) ++{ ++ int result = -1, retry = 3; ++ print_debug("IN"); ++ ++ *temp = 0; ++ while (result != 0 && retry-- > 0) { ++ /* wipe all previous message data */ ++ memset(&bcm2835_data.msg, 0, sizeof bcm2835_data.msg); ++ ++ /* prepare message */ ++ bcm2835_data.msg.msg_size = sizeof bcm2835_data.msg; ++ bcm2835_data.msg.tag.buffer_size = 8; ++ bcm2835_data.msg.tag.tag_id = tag_id; ++ ++ /* send the message */ ++ result = bcm_mailbox_property(&bcm2835_data.msg, sizeof bcm2835_data.msg); ++ print_debug("Got %stemperature as %u (%d,%x)\n", tag_id==VC_TAG_GET_MAX_TEMP ? "max ":"", (uint)bcm2835_data.msg.tag.val, result, bcm2835_data.msg.request_code); ++ if (!(bcm2835_data.msg.request_code & 0x80000000)) ++ result = -1; ++ } ++ ++ /* check if it was all ok and return the rate in milli degrees C */ ++ if (result == 0) ++ *temp = (uint)bcm2835_data.msg.tag.val; ++ else ++ print_err("Failed to get temperature! (%x:%d)\n", tag_id, result); ++ print_debug("OUT"); ++ return result; ++} ++ ++static int bcm2835_get_temp(struct thermal_zone_device *thermal_dev, unsigned long *temp) ++{ ++ return bcm2835_get_temp_or_max(thermal_dev, temp, VC_TAG_GET_TEMP); ++} ++ ++static int bcm2835_get_max_temp(struct thermal_zone_device *thermal_dev, int trip_num, unsigned long *temp) ++{ ++ return bcm2835_get_temp_or_max(thermal_dev, temp, VC_TAG_GET_MAX_TEMP); ++} ++ ++static int bcm2835_get_trip_type(struct thermal_zone_device * thermal_dev, int trip_num, enum thermal_trip_type *trip_type) ++{ ++ *trip_type = THERMAL_TRIP_HOT; ++ return 0; ++} ++ ++ ++static int bcm2835_get_mode(struct thermal_zone_device *thermal_dev, enum thermal_device_mode *dev_mode) ++{ ++ *dev_mode = THERMAL_DEVICE_ENABLED; ++ return 0; ++} ++ ++ ++static int bcm2835_thermal_probe(struct platform_device *pdev) ++{ ++ print_debug("IN"); ++ print_debug("THERMAL Driver has been probed!"); ++ ++ /* check that the device isn't null!*/ ++ if(pdev == NULL) ++ { ++ print_debug("Platform device is empty!"); ++ return -ENODEV; ++ } ++ ++ if(!(bcm2835_data.thermal_dev = thermal_zone_device_register("bcm2835_thermal", 1, 0, NULL, &ops, NULL, 0, 0))) ++ { ++ print_debug("Unable to register the thermal device!"); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++ ++static int bcm2835_thermal_remove(struct platform_device *pdev) ++{ ++ print_debug("IN"); ++ ++ thermal_zone_device_unregister(bcm2835_data.thermal_dev); ++ ++ print_debug("OUT"); ++ ++ return 0; ++} ++ ++static struct thermal_zone_device_ops ops = { ++ .get_temp = bcm2835_get_temp, ++ .get_trip_temp = bcm2835_get_max_temp, ++ .get_trip_type = bcm2835_get_trip_type, ++ .get_mode = bcm2835_get_mode, ++}; ++ ++static const struct of_device_id bcm2835_thermal_of_match_table[] = { ++ { .compatible = "brcm,bcm2835-thermal", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_thermal_of_match_table); ++ ++static struct platform_driver bcm2835_thermal_driver = { ++ .probe = bcm2835_thermal_probe, ++ .remove = bcm2835_thermal_remove, ++ .driver = { ++ .name = "bcm2835_thermal", ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_thermal_of_match_table, ++ }, ++}; ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Dorian Peake"); ++MODULE_DESCRIPTION("Thermal driver for bcm2835 chip"); ++ ++module_platform_driver(bcm2835_thermal_driver); diff --git a/target/linux/brcm2708/patches-4.1/0019-Add-Chris-Boot-s-spi-driver.patch b/target/linux/brcm2708/patches-4.1/0019-Add-Chris-Boot-s-spi-driver.patch new file mode 100644 index 0000000..03d594c --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0019-Add-Chris-Boot-s-spi-driver.patch @@ -0,0 +1,901 @@ +From f5d52c99c98af7b3d50c6c9650422cb9fd8b495e Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 17 Jun 2015 15:41:33 +0100 +Subject: [PATCH 019/203] Add Chris Boot's spi driver. + +spi: bcm2708: add device tree support + +Add DT support to driver and add to .dtsi file. +Setup pins and spidev in .dts file. +SPI is disabled by default. + +Signed-off-by: Noralf Tronnes + +BCM2708: don't register SPI controller when using DT + +The device for the SPI controller is in the Device Tree. +Only register the device when not using DT. + +Signed-off-by: Noralf Tronnes + +spi: bcm2835: make driver available on ARCH_BCM2708 + +Make this driver available on ARCH_BCM2708 + +Signed-off-by: Noralf Tronnes + +bcm2708: Remove the prohibition on mixing SPIDEV and DT + +spi-bcm2708: Prepare for Common Clock Framework migration + +As part of migrating to use the Common Clock Framework, replace clk_enable() +with clk_prepare_enable() and clk_disable() with clk_disable_unprepare(). +This does not affect behaviour under the current clock implementation. + +Also add a missing clk_disable_unprepare() in the probe error path. + +Signed-off-by: Noralf Tronnes +--- + arch/arm/mach-bcm2708/Kconfig | 7 + + arch/arm/mach-bcm2708/bcm2708.c | 53 ++++ + arch/arm/mach-bcm2709/bcm2709.c | 53 ++++ + drivers/spi/Kconfig | 10 +- + drivers/spi/Makefile | 1 + + drivers/spi/spi-bcm2708.c | 635 ++++++++++++++++++++++++++++++++++++++++ + 6 files changed, 758 insertions(+), 1 deletion(-) + create mode 100644 drivers/spi/spi-bcm2708.c + +--- a/arch/arm/mach-bcm2708/Kconfig ++++ b/arch/arm/mach-bcm2708/Kconfig +@@ -35,4 +35,11 @@ config BCM2708_NOL2CACHE + help + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. + ++config BCM2708_SPIDEV ++ bool "Bind spidev to SPI0 master" ++ depends on MACH_BCM2708 ++ depends on SPI ++ default y ++ help ++ Binds spidev driver to the SPI0 master + endmenu +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -34,6 +34,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -505,6 +506,50 @@ static struct platform_device bcm2708_al + }, + }; + ++static struct resource bcm2708_spi_resources[] = { ++ { ++ .start = SPI0_BASE, ++ .end = SPI0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_SPI, ++ .end = IRQ_SPI, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++static struct platform_device bcm2708_spi_device = { ++ .name = "bcm2708_spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_spi_resources), ++ .resource = bcm2708_spi_resources, ++ .dev = { ++ .dma_mask = &bcm2708_spi_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)}, ++}; ++ ++#ifdef CONFIG_BCM2708_SPIDEV ++static struct spi_board_info bcm2708_spi_devices[] = { ++#ifdef CONFIG_SPI_SPIDEV ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 0, ++ .mode = SPI_MODE_0, ++ }, { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 1, ++ .mode = SPI_MODE_0, ++ } ++#endif ++}; ++#endif ++ + static struct platform_device bcm2835_thermal_device = { + .name = "bcm2835_thermal", + }; +@@ -655,6 +700,8 @@ void __init bcm2708_init(void) + for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) + bcm_register_device_dt(&bcm2708_alsa_devices[i]); + ++ bcm_register_device_dt(&bcm2708_spi_device); ++ + bcm_register_device_dt(&bcm2835_thermal_device); + + if (!use_dt) { +@@ -665,6 +712,12 @@ void __init bcm2708_init(void) + } + system_rev = boardrev; + system_serial_low = serial; ++ ++#ifdef CONFIG_BCM2708_SPIDEV ++ if (!use_dt) ++ spi_register_board_info(bcm2708_spi_devices, ++ ARRAY_SIZE(bcm2708_spi_devices)); ++#endif + } + + static void timer_set_mode(enum clock_event_mode mode, +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -34,6 +34,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -525,6 +526,50 @@ static struct platform_device bcm2708_al + }, + }; + ++static struct resource bcm2708_spi_resources[] = { ++ { ++ .start = SPI0_BASE, ++ .end = SPI0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_SPI, ++ .end = IRQ_SPI, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++static struct platform_device bcm2708_spi_device = { ++ .name = "bcm2708_spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_spi_resources), ++ .resource = bcm2708_spi_resources, ++ .dev = { ++ .dma_mask = &bcm2708_spi_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)}, ++}; ++ ++#ifdef CONFIG_BCM2708_SPIDEV ++static struct spi_board_info bcm2708_spi_devices[] = { ++#ifdef CONFIG_SPI_SPIDEV ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 0, ++ .mode = SPI_MODE_0, ++ }, { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 1, ++ .mode = SPI_MODE_0, ++ } ++#endif ++}; ++#endif ++ + static struct platform_device bcm2835_thermal_device = { + .name = "bcm2835_thermal", + }; +@@ -675,6 +720,8 @@ void __init bcm2709_init(void) + for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) + bcm_register_device_dt(&bcm2708_alsa_devices[i]); + ++ bcm_register_device_dt(&bcm2708_spi_device); ++ + bcm_register_device_dt(&bcm2835_thermal_device); + + if (!use_dt) { +@@ -685,6 +732,12 @@ void __init bcm2709_init(void) + } + system_rev = boardrev; + system_serial_low = serial; ++ ++#ifdef CONFIG_BCM2708_SPIDEV ++ if (!use_dt) ++ spi_register_board_info(bcm2708_spi_devices, ++ ARRAY_SIZE(bcm2708_spi_devices)); ++#endif + } + + #ifdef SYSTEM_TIMER +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -77,7 +77,7 @@ config SPI_ATMEL + + config SPI_BCM2835 + tristate "BCM2835 SPI controller" +- depends on ARCH_BCM2835 || COMPILE_TEST ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 || COMPILE_TEST + depends on GPIOLIB + help + This selects a driver for the Broadcom BCM2835 SPI master. +@@ -87,6 +87,14 @@ config SPI_BCM2835 + is for the regular SPI controller. Slave mode operation is not also + not supported. + ++config SPI_BCM2708 ++ tristate "BCM2708 SPI controller driver (SPI0)" ++ depends on MACH_BCM2708 || MACH_BCM2709 ++ help ++ This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This ++ driver is not compatible with the "Universal SPI Master" or the SPI slave ++ device. ++ + config SPI_BFIN5XX + tristate "SPI controller driver for ADI Blackfin5xx" + depends on BLACKFIN && !BF60x +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63x + obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o + obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o + obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o ++obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o + obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o + obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o + obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o +--- /dev/null ++++ b/drivers/spi/spi-bcm2708.c +@@ -0,0 +1,635 @@ ++/* ++ * Driver for Broadcom BCM2708 SPI Controllers ++ * ++ * Copyright (C) 2012 Chris Boot ++ * ++ * This driver is inspired by: ++ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos ++ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* SPI register offsets */ ++#define SPI_CS 0x00 ++#define SPI_FIFO 0x04 ++#define SPI_CLK 0x08 ++#define SPI_DLEN 0x0c ++#define SPI_LTOH 0x10 ++#define SPI_DC 0x14 ++ ++/* Bitfields in CS */ ++#define SPI_CS_LEN_LONG 0x02000000 ++#define SPI_CS_DMA_LEN 0x01000000 ++#define SPI_CS_CSPOL2 0x00800000 ++#define SPI_CS_CSPOL1 0x00400000 ++#define SPI_CS_CSPOL0 0x00200000 ++#define SPI_CS_RXF 0x00100000 ++#define SPI_CS_RXR 0x00080000 ++#define SPI_CS_TXD 0x00040000 ++#define SPI_CS_RXD 0x00020000 ++#define SPI_CS_DONE 0x00010000 ++#define SPI_CS_LEN 0x00002000 ++#define SPI_CS_REN 0x00001000 ++#define SPI_CS_ADCS 0x00000800 ++#define SPI_CS_INTR 0x00000400 ++#define SPI_CS_INTD 0x00000200 ++#define SPI_CS_DMAEN 0x00000100 ++#define SPI_CS_TA 0x00000080 ++#define SPI_CS_CSPOL 0x00000040 ++#define SPI_CS_CLEAR_RX 0x00000020 ++#define SPI_CS_CLEAR_TX 0x00000010 ++#define SPI_CS_CPOL 0x00000008 ++#define SPI_CS_CPHA 0x00000004 ++#define SPI_CS_CS_10 0x00000002 ++#define SPI_CS_CS_01 0x00000001 ++ ++#define SPI_TIMEOUT_MS 150 ++ ++#define DRV_NAME "bcm2708_spi" ++ ++struct bcm2708_spi { ++ spinlock_t lock; ++ void __iomem *base; ++ int irq; ++ struct clk *clk; ++ bool stopping; ++ ++ struct list_head queue; ++ struct workqueue_struct *workq; ++ struct work_struct work; ++ struct completion done; ++ ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++}; ++ ++struct bcm2708_spi_state { ++ u32 cs; ++ u16 cdiv; ++}; ++ ++/* ++ * This function sets the ALT mode on the SPI pins so that we can use them with ++ * the SPI hardware. ++ * ++ * FIXME: This is a hack. Use pinmux / pinctrl. ++ */ ++static void bcm2708_init_pinmode(void) ++{ ++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) ++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) ++ ++ int pin; ++ u32 *gpio = ioremap(GPIO_BASE, SZ_16K); ++ ++ /* SPI is on GPIO 7..11 */ ++ for (pin = 7; pin <= 11; pin++) { ++ INP_GPIO(pin); /* set mode to GPIO input first */ ++ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ ++ } ++ ++ iounmap(gpio); ++ ++#undef INP_GPIO ++#undef SET_GPIO_ALT ++} ++ ++static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg) ++{ ++ return readl(bs->base + reg); ++} ++ ++static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val) ++{ ++ writel(val, bs->base + reg); ++} ++ ++static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len) ++{ ++ u8 byte; ++ ++ while (len--) { ++ byte = bcm2708_rd(bs, SPI_FIFO); ++ if (bs->rx_buf) ++ *bs->rx_buf++ = byte; ++ } ++} ++ ++static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len) ++{ ++ u8 byte; ++ u16 val; ++ ++ if (len > bs->len) ++ len = bs->len; ++ ++ if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) { ++ /* LoSSI mode */ ++ if (unlikely(len % 2)) { ++ printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n"); ++ bs->len = 0; ++ return; ++ } ++ while (len) { ++ if (bs->tx_buf) { ++ val = *(const u16 *)bs->tx_buf; ++ bs->tx_buf += 2; ++ } else ++ val = 0; ++ bcm2708_wr(bs, SPI_FIFO, val); ++ bs->len -= 2; ++ len -= 2; ++ } ++ return; ++ } ++ ++ while (len--) { ++ byte = bs->tx_buf ? *bs->tx_buf++ : 0; ++ bcm2708_wr(bs, SPI_FIFO, byte); ++ bs->len--; ++ } ++} ++ ++static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ u32 cs; ++ ++ spin_lock(&bs->lock); ++ ++ cs = bcm2708_rd(bs, SPI_CS); ++ ++ if (cs & SPI_CS_DONE) { ++ if (bs->len) { /* first interrupt in a transfer */ ++ /* fill the TX fifo with up to 16 bytes */ ++ bcm2708_wr_fifo(bs, 16); ++ } else { /* transfer complete */ ++ /* disable interrupts */ ++ cs &= ~(SPI_CS_INTR | SPI_CS_INTD); ++ bcm2708_wr(bs, SPI_CS, cs); ++ ++ /* drain RX FIFO */ ++ while (cs & SPI_CS_RXD) { ++ bcm2708_rd_fifo(bs, 1); ++ cs = bcm2708_rd(bs, SPI_CS); ++ } ++ ++ /* wake up our bh */ ++ complete(&bs->done); ++ } ++ } else if (cs & SPI_CS_RXR) { ++ /* read 12 bytes of data */ ++ bcm2708_rd_fifo(bs, 12); ++ ++ /* write up to 12 bytes */ ++ bcm2708_wr_fifo(bs, 12); ++ } ++ ++ spin_unlock(&bs->lock); ++ ++ return IRQ_HANDLED; ++} ++ ++static int bcm2708_setup_state(struct spi_master *master, ++ struct device *dev, struct bcm2708_spi_state *state, ++ u32 hz, u8 csel, u8 mode, u8 bpw) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ int cdiv; ++ unsigned long bus_hz; ++ u32 cs = 0; ++ ++ bus_hz = clk_get_rate(bs->clk); ++ ++ if (hz >= bus_hz) { ++ cdiv = 2; /* bus_hz / 2 is as fast as we can go */ ++ } else if (hz) { ++ cdiv = DIV_ROUND_UP(bus_hz, hz); ++ ++ /* CDIV must be a power of 2, so round up */ ++ cdiv = roundup_pow_of_two(cdiv); ++ ++ if (cdiv > 65536) { ++ dev_dbg(dev, ++ "setup: %d Hz too slow, cdiv %u; min %ld Hz\n", ++ hz, cdiv, bus_hz / 65536); ++ return -EINVAL; ++ } else if (cdiv == 65536) { ++ cdiv = 0; ++ } else if (cdiv == 1) { ++ cdiv = 2; /* 1 gets rounded down to 0; == 65536 */ ++ } ++ } else { ++ cdiv = 0; ++ } ++ ++ switch (bpw) { ++ case 8: ++ break; ++ case 9: ++ /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */ ++ cs |= SPI_CS_LEN; ++ break; ++ default: ++ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n", ++ bpw); ++ return -EINVAL; ++ } ++ ++ if (mode & SPI_CPOL) ++ cs |= SPI_CS_CPOL; ++ if (mode & SPI_CPHA) ++ cs |= SPI_CS_CPHA; ++ ++ if (!(mode & SPI_NO_CS)) { ++ if (mode & SPI_CS_HIGH) { ++ cs |= SPI_CS_CSPOL; ++ cs |= SPI_CS_CSPOL0 << csel; ++ } ++ ++ cs |= csel; ++ } else { ++ cs |= SPI_CS_CS_10 | SPI_CS_CS_01; ++ } ++ ++ if (state) { ++ state->cs = cs; ++ state->cdiv = cdiv; ++ dev_dbg(dev, "setup: want %d Hz; " ++ "bus_hz=%lu / cdiv=%u == %lu Hz; " ++ "mode %u: cs 0x%08X\n", ++ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs); ++ } ++ ++ return 0; ++} ++ ++static int bcm2708_process_transfer(struct bcm2708_spi *bs, ++ struct spi_message *msg, struct spi_transfer *xfer) ++{ ++ struct spi_device *spi = msg->spi; ++ struct bcm2708_spi_state state, *stp; ++ int ret; ++ u32 cs; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ if (xfer->bits_per_word || xfer->speed_hz) { ++ ret = bcm2708_setup_state(spi->master, &spi->dev, &state, ++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, ++ spi->chip_select, spi->mode, ++ xfer->bits_per_word ? xfer->bits_per_word : ++ spi->bits_per_word); ++ if (ret) ++ return ret; ++ ++ stp = &state; ++ } else { ++ stp = spi->controller_state; ++ } ++ ++ reinit_completion(&bs->done); ++ bs->tx_buf = xfer->tx_buf; ++ bs->rx_buf = xfer->rx_buf; ++ bs->len = xfer->len; ++ ++ cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA; ++ ++ bcm2708_wr(bs, SPI_CLK, stp->cdiv); ++ bcm2708_wr(bs, SPI_CS, cs); ++ ++ ret = wait_for_completion_timeout(&bs->done, ++ msecs_to_jiffies(SPI_TIMEOUT_MS)); ++ if (ret == 0) { ++ dev_err(&spi->dev, "transfer timed out\n"); ++ return -ETIMEDOUT; ++ } ++ ++ if (xfer->delay_usecs) ++ udelay(xfer->delay_usecs); ++ ++ if (list_is_last(&xfer->transfer_list, &msg->transfers) || ++ xfer->cs_change) { ++ /* clear TA and interrupt flags */ ++ bcm2708_wr(bs, SPI_CS, stp->cs); ++ } ++ ++ msg->actual_length += (xfer->len - bs->len); ++ ++ return 0; ++} ++ ++static void bcm2708_work(struct work_struct *work) ++{ ++ struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work); ++ unsigned long flags; ++ struct spi_message *msg; ++ struct spi_transfer *xfer; ++ int status = 0; ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ while (!list_empty(&bs->queue)) { ++ msg = list_first_entry(&bs->queue, struct spi_message, queue); ++ list_del_init(&msg->queue); ++ spin_unlock_irqrestore(&bs->lock, flags); ++ ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ status = bcm2708_process_transfer(bs, msg, xfer); ++ if (status) ++ break; ++ } ++ ++ msg->status = status; ++ msg->complete(msg->context); ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ } ++ spin_unlock_irqrestore(&bs->lock, flags); ++} ++ ++static int bcm2708_spi_setup(struct spi_device *spi) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master); ++ struct bcm2708_spi_state *state; ++ int ret; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ if (!(spi->mode & SPI_NO_CS) && ++ (spi->chip_select > spi->master->num_chipselect)) { ++ dev_dbg(&spi->dev, ++ "setup: invalid chipselect %u (%u defined)\n", ++ spi->chip_select, spi->master->num_chipselect); ++ return -EINVAL; ++ } ++ ++ state = spi->controller_state; ++ if (!state) { ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (!state) ++ return -ENOMEM; ++ ++ spi->controller_state = state; ++ } ++ ++ ret = bcm2708_setup_state(spi->master, &spi->dev, state, ++ spi->max_speed_hz, spi->chip_select, spi->mode, ++ spi->bits_per_word); ++ if (ret < 0) { ++ kfree(state); ++ spi->controller_state = NULL; ++ return ret; ++ } ++ ++ dev_dbg(&spi->dev, ++ "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n", ++ spi->chip_select, spi->max_speed_hz, spi->bits_per_word, ++ spi->mode, state->cs, state->cdiv); ++ ++ return 0; ++} ++ ++static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master); ++ struct spi_transfer *xfer; ++ int ret; ++ unsigned long flags; ++ ++ if (unlikely(list_empty(&msg->transfers))) ++ return -EINVAL; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { ++ dev_dbg(&spi->dev, "missing rx or tx buf\n"); ++ return -EINVAL; ++ } ++ ++ if (!xfer->bits_per_word || xfer->speed_hz) ++ continue; ++ ++ ret = bcm2708_setup_state(spi->master, &spi->dev, NULL, ++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, ++ spi->chip_select, spi->mode, ++ xfer->bits_per_word ? xfer->bits_per_word : ++ spi->bits_per_word); ++ if (ret) ++ return ret; ++ } ++ ++ msg->status = -EINPROGRESS; ++ msg->actual_length = 0; ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ list_add_tail(&msg->queue, &bs->queue); ++ queue_work(bs->workq, &bs->work); ++ spin_unlock_irqrestore(&bs->lock, flags); ++ ++ return 0; ++} ++ ++static void bcm2708_spi_cleanup(struct spi_device *spi) ++{ ++ if (spi->controller_state) { ++ kfree(spi->controller_state); ++ spi->controller_state = NULL; ++ } ++} ++ ++static int bcm2708_spi_probe(struct platform_device *pdev) ++{ ++ struct resource *regs; ++ int irq, err = -ENOMEM; ++ struct clk *clk; ++ struct spi_master *master; ++ struct bcm2708_spi *bs; ++ ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!regs) { ++ dev_err(&pdev->dev, "could not get IO memory\n"); ++ return -ENXIO; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(&pdev->dev, "could not get IRQ\n"); ++ return irq; ++ } ++ ++ clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk)); ++ return PTR_ERR(clk); ++ } ++ ++ bcm2708_init_pinmode(); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ goto out_clk_put; ++ } ++ ++ /* the spi->mode bits understood by this driver: */ ++ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; ++ ++ master->bus_num = pdev->id; ++ master->num_chipselect = 3; ++ master->setup = bcm2708_spi_setup; ++ master->transfer = bcm2708_spi_transfer; ++ master->cleanup = bcm2708_spi_cleanup; ++ master->dev.of_node = pdev->dev.of_node; ++ platform_set_drvdata(pdev, master); ++ ++ bs = spi_master_get_devdata(master); ++ ++ spin_lock_init(&bs->lock); ++ INIT_LIST_HEAD(&bs->queue); ++ init_completion(&bs->done); ++ INIT_WORK(&bs->work, bcm2708_work); ++ ++ bs->base = ioremap(regs->start, resource_size(regs)); ++ if (!bs->base) { ++ dev_err(&pdev->dev, "could not remap memory\n"); ++ goto out_master_put; ++ } ++ ++ bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev)); ++ if (!bs->workq) { ++ dev_err(&pdev->dev, "could not create workqueue\n"); ++ goto out_iounmap; ++ } ++ ++ bs->irq = irq; ++ bs->clk = clk; ++ bs->stopping = false; ++ ++ err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev), ++ master); ++ if (err) { ++ dev_err(&pdev->dev, "could not request IRQ: %d\n", err); ++ goto out_workqueue; ++ } ++ ++ /* initialise the hardware */ ++ clk_prepare_enable(clk); ++ bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX); ++ ++ err = spi_register_master(master); ++ if (err) { ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_free_irq; ++ } ++ ++ dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n", ++ (unsigned long)regs->start, irq); ++ ++ return 0; ++ ++out_free_irq: ++ free_irq(bs->irq, master); ++ clk_disable_unprepare(bs->clk); ++out_workqueue: ++ destroy_workqueue(bs->workq); ++out_iounmap: ++ iounmap(bs->base); ++out_master_put: ++ spi_master_put(master); ++out_clk_put: ++ clk_put(clk); ++ return err; ++} ++ ++static int bcm2708_spi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ ++ /* reset the hardware and block queue progress */ ++ spin_lock_irq(&bs->lock); ++ bs->stopping = true; ++ bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX); ++ spin_unlock_irq(&bs->lock); ++ ++ flush_work(&bs->work); ++ ++ clk_disable_unprepare(bs->clk); ++ clk_put(bs->clk); ++ free_irq(bs->irq, master); ++ iounmap(bs->base); ++ ++ spi_unregister_master(master); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm2708_spi_match[] = { ++ { .compatible = "brcm,bcm2708-spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, bcm2708_spi_match); ++ ++static struct platform_driver bcm2708_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2708_spi_match, ++ }, ++ .probe = bcm2708_spi_probe, ++ .remove = bcm2708_spi_remove, ++}; ++ ++ ++static int __init bcm2708_spi_init(void) ++{ ++ return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe); ++} ++module_init(bcm2708_spi_init); ++ ++static void __exit bcm2708_spi_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_spi_driver); ++} ++module_exit(bcm2708_spi_exit); ++ ++ ++//module_platform_driver(bcm2708_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRV_NAME); diff --git a/target/linux/brcm2708/patches-4.1/0020-Add-Chris-Boot-s-i2c-driver.patch b/target/linux/brcm2708/patches-4.1/0020-Add-Chris-Boot-s-i2c-driver.patch new file mode 100644 index 0000000..2580429 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0020-Add-Chris-Boot-s-i2c-driver.patch @@ -0,0 +1,792 @@ +From 088993fea0e74f22da3f97c7a3212d0cc9a1afea Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 17 Jun 2015 15:44:08 +0100 +Subject: [PATCH 020/203] Add Chris Boot's i2c driver + +i2c-bcm2708: fixed baudrate + +Fixed issue where the wrong CDIV value was set for baudrates below 3815 Hz (for 250MHz bus clock). +In that case the computed CDIV value was more than 0xffff. However the CDIV register width is only 16 bits. +This resulted in incorrect setting of CDIV and higher baudrate than intended. +Example: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0x1704 -> 42430Hz +After correction: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0xffff -> 3815Hz +The correct baudrate is shown in the log after the cdiv > 0xffff correction. + +Perform I2C combined transactions when possible + +Perform I2C combined transactions whenever possible, within the +restrictions of the Broadcomm Serial Controller. + +Disable DONE interrupt during TA poll + +Prevent interrupt from being triggered if poll is missed and transfer +starts and finishes. + +i2c: Make combined transactions optional and disabled by default + +i2c: bcm2708: add device tree support + +Add DT support to driver and add to .dtsi file. +Setup pins in .dts file. +i2c is disabled by default. + +Signed-off-by: Noralf Tronnes + +bcm2708: don't register i2c controllers when using DT + +The devices for the i2c controllers are in the Device Tree. +Only register devices when not using DT. + +Signed-off-by: Noralf Tronnes + +I2C: Only register the I2C device for the current board revision + +i2c_bcm2708: Fix clock reference counting + +Fix grabbing lock from atomic context in i2c driver + +2 main changes: +- check for timeouts in the bcm2708_bsc_setup function as indicated by this comment: + /* poll for transfer start bit (should only take 1-20 polls) */ + This implies that the setup function can now fail so account for this everywhere it's called +- Removed the clk_get_rate call from inside the setup function as it locks a mutex and that's not ok since we call it from under a spin lock. + +i2c-bcm2708: When using DT, leave the GPIO setup to pinctrl +--- + arch/arm/mach-bcm2708/bcm2708.c | 51 ++++ + arch/arm/mach-bcm2709/bcm2709.c | 51 ++++ + drivers/i2c/busses/Kconfig | 21 +- + drivers/i2c/busses/Makefile | 2 + + drivers/i2c/busses/i2c-bcm2708.c | 522 +++++++++++++++++++++++++++++++++++++++ + 5 files changed, 646 insertions(+), 1 deletion(-) + create mode 100644 drivers/i2c/busses/i2c-bcm2708.c + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -83,6 +83,7 @@ static unsigned uart_clock = UART0_CLOCK + static unsigned disk_led_gpio = 16; + static unsigned disk_led_active_low = 1; + static unsigned reboot_part = 0; ++static bool vc_i2c_override = false; + + static unsigned use_dt = 0; + +@@ -550,6 +551,45 @@ static struct spi_board_info bcm2708_spi + }; + #endif + ++static struct resource bcm2708_bsc0_resources[] = { ++ { ++ .start = BSC0_BASE, ++ .end = BSC0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc0_device = { ++ .name = "bcm2708_i2c", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources), ++ .resource = bcm2708_bsc0_resources, ++}; ++ ++ ++static struct resource bcm2708_bsc1_resources[] = { ++ { ++ .start = BSC1_BASE, ++ .end = BSC1_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc1_device = { ++ .name = "bcm2708_i2c", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources), ++ .resource = bcm2708_bsc1_resources, ++}; ++ + static struct platform_device bcm2835_thermal_device = { + .name = "bcm2835_thermal", + }; +@@ -702,6 +742,15 @@ void __init bcm2708_init(void) + + bcm_register_device_dt(&bcm2708_spi_device); + ++ if (vc_i2c_override) { ++ bcm_register_device_dt(&bcm2708_bsc0_device); ++ bcm_register_device_dt(&bcm2708_bsc1_device); ++ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) { ++ bcm_register_device_dt(&bcm2708_bsc0_device); ++ } else { ++ bcm_register_device_dt(&bcm2708_bsc1_device); ++ } ++ + bcm_register_device_dt(&bcm2835_thermal_device); + + if (!use_dt) { +@@ -893,3 +942,5 @@ module_param(uart_clock, uint, 0644); + module_param(disk_led_gpio, uint, 0644); + module_param(disk_led_active_low, uint, 0644); + module_param(reboot_part, uint, 0644); ++module_param(vc_i2c_override, bool, 0644); ++MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -85,6 +85,7 @@ static unsigned uart_clock = UART0_CLOCK + static unsigned disk_led_gpio = 16; + static unsigned disk_led_active_low = 1; + static unsigned reboot_part = 0; ++static bool vc_i2c_override = false; + + static unsigned use_dt = 0; + +@@ -570,6 +571,45 @@ static struct spi_board_info bcm2708_spi + }; + #endif + ++static struct resource bcm2708_bsc0_resources[] = { ++ { ++ .start = BSC0_BASE, ++ .end = BSC0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc0_device = { ++ .name = "bcm2708_i2c", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources), ++ .resource = bcm2708_bsc0_resources, ++}; ++ ++ ++static struct resource bcm2708_bsc1_resources[] = { ++ { ++ .start = BSC1_BASE, ++ .end = BSC1_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc1_device = { ++ .name = "bcm2708_i2c", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources), ++ .resource = bcm2708_bsc1_resources, ++}; ++ + static struct platform_device bcm2835_thermal_device = { + .name = "bcm2835_thermal", + }; +@@ -722,6 +762,15 @@ void __init bcm2709_init(void) + + bcm_register_device_dt(&bcm2708_spi_device); + ++ if (vc_i2c_override) { ++ bcm_register_device_dt(&bcm2708_bsc0_device); ++ bcm_register_device_dt(&bcm2708_bsc1_device); ++ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) { ++ bcm_register_device_dt(&bcm2708_bsc0_device); ++ } else { ++ bcm_register_device_dt(&bcm2708_bsc1_device); ++ } ++ + bcm_register_device_dt(&bcm2835_thermal_device); + + if (!use_dt) { +@@ -1061,3 +1110,5 @@ module_param(uart_clock, uint, 0644); + module_param(disk_led_gpio, uint, 0644); + module_param(disk_led_active_low, uint, 0644); + module_param(reboot_part, uint, 0644); ++module_param(vc_i2c_override, bool, 0644); ++MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -8,6 +8,25 @@ menu "I2C Hardware Bus support" + comment "PC SMBus host controller drivers" + depends on PCI + ++config I2C_BCM2708 ++ tristate "BCM2708 BSC" ++ depends on MACH_BCM2708 || MACH_BCM2709 ++ help ++ Enabling this option will add BSC (Broadcom Serial Controller) ++ support for the BCM2708. BSC is a Broadcom proprietary bus compatible ++ with I2C/TWI/SMBus. ++ ++config I2C_BCM2708_BAUDRATE ++ prompt "BCM2708 I2C baudrate" ++ depends on I2C_BCM2708 ++ int ++ default 100000 ++ help ++ Set the I2C baudrate. This will alter the default value. A ++ different baudrate can be set by using a module parameter as well. If ++ no parameter is provided when loading, this is the value that will be ++ used. ++ + config I2C_ALI1535 + tristate "ALI 1535" + depends on PCI +@@ -362,7 +381,7 @@ config I2C_AXXIA + + config I2C_BCM2835 + tristate "Broadcom BCM2835 I2C controller" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + help + If you say yes to this option, support will be included for the + BCM2835 I2C controller. +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -2,6 +2,8 @@ + # Makefile for the i2c bus drivers. + # + ++obj-$(CONFIG_I2C_BCM2708) += i2c-bcm2708.o ++ + # ACPI drivers + obj-$(CONFIG_I2C_SCMI) += i2c-scmi.o + +--- /dev/null ++++ b/drivers/i2c/busses/i2c-bcm2708.c +@@ -0,0 +1,522 @@ ++/* ++ * Driver for Broadcom BCM2708 BSC Controllers ++ * ++ * Copyright (C) 2012 Chris Boot & Frank Buss ++ * ++ * This driver is inspired by: ++ * i2c-ocores.c, by Peter Korsgaard ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* BSC register offsets */ ++#define BSC_C 0x00 ++#define BSC_S 0x04 ++#define BSC_DLEN 0x08 ++#define BSC_A 0x0c ++#define BSC_FIFO 0x10 ++#define BSC_DIV 0x14 ++#define BSC_DEL 0x18 ++#define BSC_CLKT 0x1c ++ ++/* Bitfields in BSC_C */ ++#define BSC_C_I2CEN 0x00008000 ++#define BSC_C_INTR 0x00000400 ++#define BSC_C_INTT 0x00000200 ++#define BSC_C_INTD 0x00000100 ++#define BSC_C_ST 0x00000080 ++#define BSC_C_CLEAR_1 0x00000020 ++#define BSC_C_CLEAR_2 0x00000010 ++#define BSC_C_READ 0x00000001 ++ ++/* Bitfields in BSC_S */ ++#define BSC_S_CLKT 0x00000200 ++#define BSC_S_ERR 0x00000100 ++#define BSC_S_RXF 0x00000080 ++#define BSC_S_TXE 0x00000040 ++#define BSC_S_RXD 0x00000020 ++#define BSC_S_TXD 0x00000010 ++#define BSC_S_RXR 0x00000008 ++#define BSC_S_TXW 0x00000004 ++#define BSC_S_DONE 0x00000002 ++#define BSC_S_TA 0x00000001 ++ ++#define I2C_TIMEOUT_MS 150 ++#define I2C_WAIT_LOOP_COUNT 40 ++ ++#define DRV_NAME "bcm2708_i2c" ++ ++static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE; ++module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); ++MODULE_PARM_DESC(baudrate, "The I2C baudrate"); ++ ++static bool combined = false; ++module_param(combined, bool, 0644); ++MODULE_PARM_DESC(combined, "Use combined transactions"); ++ ++struct bcm2708_i2c { ++ struct i2c_adapter adapter; ++ ++ spinlock_t lock; ++ void __iomem *base; ++ int irq; ++ struct clk *clk; ++ u32 cdiv; ++ ++ struct completion done; ++ ++ struct i2c_msg *msg; ++ int pos; ++ int nmsgs; ++ bool error; ++}; ++ ++/* ++ * This function sets the ALT mode on the I2C pins so that we can use them with ++ * the BSC hardware. ++ * ++ * FIXME: This is a hack. Use pinmux / pinctrl. ++ */ ++static void bcm2708_i2c_init_pinmode(int id) ++{ ++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) ++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) ++ ++ int pin; ++ u32 *gpio = ioremap(GPIO_BASE, SZ_16K); ++ ++ BUG_ON(id != 0 && id != 1); ++ /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */ ++ for (pin = id*2+0; pin <= id*2+1; pin++) { ++ printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin); ++ INP_GPIO(pin); /* set mode to GPIO input first */ ++ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ ++ } ++ ++ iounmap(gpio); ++ ++#undef INP_GPIO ++#undef SET_GPIO_ALT ++} ++ ++static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg) ++{ ++ return readl(bi->base + reg); ++} ++ ++static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val) ++{ ++ writel(val, bi->base + reg); ++} ++ ++static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi) ++{ ++ bcm2708_wr(bi, BSC_C, 0); ++ bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE); ++} ++ ++static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi) ++{ ++ while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len)) ++ bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO); ++} ++ ++static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi) ++{ ++ while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len)) ++ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]); ++} ++ ++static inline int bcm2708_bsc_setup(struct bcm2708_i2c *bi) ++{ ++ u32 cdiv, s; ++ u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1; ++ int wait_loops = I2C_WAIT_LOOP_COUNT; ++ ++ /* Can't call clk_get_rate as it locks a mutex and here we are spinlocked. ++ * Use the value that we cached in the probe. ++ */ ++ cdiv = bi->cdiv; ++ ++ if (bi->msg->flags & I2C_M_RD) ++ c |= BSC_C_INTR | BSC_C_READ; ++ else ++ c |= BSC_C_INTT; ++ ++ bcm2708_wr(bi, BSC_DIV, cdiv); ++ bcm2708_wr(bi, BSC_A, bi->msg->addr); ++ bcm2708_wr(bi, BSC_DLEN, bi->msg->len); ++ if (combined) ++ { ++ /* Do the next two messages meet combined transaction criteria? ++ - Current message is a write, next message is a read ++ - Both messages to same slave address ++ - Write message can fit inside FIFO (16 bytes or less) */ ++ if ( (bi->nmsgs > 1) && ++ !(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) && ++ (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) { ++ /* Fill FIFO with entire write message (16 byte FIFO) */ ++ while (bi->pos < bi->msg->len) { ++ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]); ++ } ++ /* Start write transfer (no interrupts, don't clear FIFO) */ ++ bcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST); ++ ++ /* poll for transfer start bit (should only take 1-20 polls) */ ++ do { ++ s = bcm2708_rd(bi, BSC_S); ++ } while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)) && --wait_loops >= 0); ++ ++ /* did we time out or some error occured? */ ++ if (wait_loops < 0 || (s & (BSC_S_ERR | BSC_S_CLKT))) { ++ return -1; ++ } ++ ++ /* Send next read message before the write transfer finishes. */ ++ bi->nmsgs--; ++ bi->msg++; ++ bi->pos = 0; ++ bcm2708_wr(bi, BSC_DLEN, bi->msg->len); ++ c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ; ++ } ++ } ++ bcm2708_wr(bi, BSC_C, c); ++ ++ return 0; ++} ++ ++static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id) ++{ ++ struct bcm2708_i2c *bi = dev_id; ++ bool handled = true; ++ u32 s; ++ int ret; ++ ++ spin_lock(&bi->lock); ++ ++ /* we may see camera interrupts on the "other" I2C channel ++ Just return if we've not sent anything */ ++ if (!bi->nmsgs || !bi->msg) { ++ goto early_exit; ++ } ++ ++ s = bcm2708_rd(bi, BSC_S); ++ ++ if (s & (BSC_S_CLKT | BSC_S_ERR)) { ++ bcm2708_bsc_reset(bi); ++ bi->error = true; ++ ++ bi->msg = 0; /* to inform the that all work is done */ ++ bi->nmsgs = 0; ++ /* wake up our bh */ ++ complete(&bi->done); ++ } else if (s & BSC_S_DONE) { ++ bi->nmsgs--; ++ ++ if (bi->msg->flags & I2C_M_RD) { ++ bcm2708_bsc_fifo_drain(bi); ++ } ++ ++ bcm2708_bsc_reset(bi); ++ ++ if (bi->nmsgs) { ++ /* advance to next message */ ++ bi->msg++; ++ bi->pos = 0; ++ ret = bcm2708_bsc_setup(bi); ++ if (ret < 0) { ++ bcm2708_bsc_reset(bi); ++ bi->error = true; ++ bi->msg = 0; /* to inform the that all work is done */ ++ bi->nmsgs = 0; ++ /* wake up our bh */ ++ complete(&bi->done); ++ goto early_exit; ++ } ++ } else { ++ bi->msg = 0; /* to inform the that all work is done */ ++ bi->nmsgs = 0; ++ /* wake up our bh */ ++ complete(&bi->done); ++ } ++ } else if (s & BSC_S_TXW) { ++ bcm2708_bsc_fifo_fill(bi); ++ } else if (s & BSC_S_RXR) { ++ bcm2708_bsc_fifo_drain(bi); ++ } else { ++ handled = false; ++ } ++ ++early_exit: ++ spin_unlock(&bi->lock); ++ ++ return handled ? IRQ_HANDLED : IRQ_NONE; ++} ++ ++static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap, ++ struct i2c_msg *msgs, int num) ++{ ++ struct bcm2708_i2c *bi = adap->algo_data; ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&bi->lock, flags); ++ ++ reinit_completion(&bi->done); ++ bi->msg = msgs; ++ bi->pos = 0; ++ bi->nmsgs = num; ++ bi->error = false; ++ ++ ret = bcm2708_bsc_setup(bi); ++ ++ spin_unlock_irqrestore(&bi->lock, flags); ++ ++ /* check the result of the setup */ ++ if (ret < 0) ++ { ++ dev_err(&adap->dev, "transfer setup timed out\n"); ++ goto error_timeout; ++ } ++ ++ ret = wait_for_completion_timeout(&bi->done, msecs_to_jiffies(I2C_TIMEOUT_MS)); ++ if (ret == 0) { ++ dev_err(&adap->dev, "transfer timed out\n"); ++ goto error_timeout; ++ } ++ ++ ret = bi->error ? -EIO : num; ++ return ret; ++ ++error_timeout: ++ spin_lock_irqsave(&bi->lock, flags); ++ bcm2708_bsc_reset(bi); ++ bi->msg = 0; /* to inform the interrupt handler that there's nothing else to be done */ ++ bi->nmsgs = 0; ++ spin_unlock_irqrestore(&bi->lock, flags); ++ return -ETIMEDOUT; ++} ++ ++static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm bcm2708_i2c_algorithm = { ++ .master_xfer = bcm2708_i2c_master_xfer, ++ .functionality = bcm2708_i2c_functionality, ++}; ++ ++static int bcm2708_i2c_probe(struct platform_device *pdev) ++{ ++ struct resource *regs; ++ int irq, err = -ENOMEM; ++ struct clk *clk; ++ struct bcm2708_i2c *bi; ++ struct i2c_adapter *adap; ++ unsigned long bus_hz; ++ u32 cdiv; ++ ++ if (pdev->dev.of_node) { ++ u32 bus_clk_rate; ++ pdev->id = of_alias_get_id(pdev->dev.of_node, "i2c"); ++ if (pdev->id < 0) { ++ dev_err(&pdev->dev, "alias is missing\n"); ++ return -EINVAL; ++ } ++ if (!of_property_read_u32(pdev->dev.of_node, ++ "clock-frequency", &bus_clk_rate)) ++ baudrate = bus_clk_rate; ++ else ++ dev_warn(&pdev->dev, ++ "Could not read clock-frequency property\n"); ++ } ++ ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!regs) { ++ dev_err(&pdev->dev, "could not get IO memory\n"); ++ return -ENXIO; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(&pdev->dev, "could not get IRQ\n"); ++ return irq; ++ } ++ ++ clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk)); ++ return PTR_ERR(clk); ++ } ++ ++ err = clk_prepare_enable(clk); ++ if (err) { ++ dev_err(&pdev->dev, "could not enable clk: %d\n", err); ++ goto out_clk_put; ++ } ++ ++ if (!pdev->dev.of_node) ++ bcm2708_i2c_init_pinmode(pdev->id); ++ ++ bi = kzalloc(sizeof(*bi), GFP_KERNEL); ++ if (!bi) ++ goto out_clk_disable; ++ ++ platform_set_drvdata(pdev, bi); ++ ++ adap = &bi->adapter; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC; ++ adap->algo = &bcm2708_i2c_algorithm; ++ adap->algo_data = bi; ++ adap->dev.parent = &pdev->dev; ++ adap->nr = pdev->id; ++ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); ++ adap->dev.of_node = pdev->dev.of_node; ++ ++ switch (pdev->id) { ++ case 0: ++ adap->class = I2C_CLASS_HWMON; ++ break; ++ case 1: ++ adap->class = I2C_CLASS_DDC; ++ break; ++ default: ++ dev_err(&pdev->dev, "can only bind to BSC 0 or 1\n"); ++ err = -ENXIO; ++ goto out_free_bi; ++ } ++ ++ spin_lock_init(&bi->lock); ++ init_completion(&bi->done); ++ ++ bi->base = ioremap(regs->start, resource_size(regs)); ++ if (!bi->base) { ++ dev_err(&pdev->dev, "could not remap memory\n"); ++ goto out_free_bi; ++ } ++ ++ bi->irq = irq; ++ bi->clk = clk; ++ ++ err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED, ++ dev_name(&pdev->dev), bi); ++ if (err) { ++ dev_err(&pdev->dev, "could not request IRQ: %d\n", err); ++ goto out_iounmap; ++ } ++ ++ bcm2708_bsc_reset(bi); ++ ++ err = i2c_add_numbered_adapter(adap); ++ if (err < 0) { ++ dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err); ++ goto out_free_irq; ++ } ++ ++ bus_hz = clk_get_rate(bi->clk); ++ cdiv = bus_hz / baudrate; ++ if (cdiv > 0xffff) { ++ cdiv = 0xffff; ++ baudrate = bus_hz / cdiv; ++ } ++ bi->cdiv = cdiv; ++ ++ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n", ++ pdev->id, (unsigned long)regs->start, irq, baudrate); ++ ++ return 0; ++ ++out_free_irq: ++ free_irq(bi->irq, bi); ++out_iounmap: ++ iounmap(bi->base); ++out_free_bi: ++ kfree(bi); ++out_clk_disable: ++ clk_disable_unprepare(clk); ++out_clk_put: ++ clk_put(clk); ++ return err; ++} ++ ++static int bcm2708_i2c_remove(struct platform_device *pdev) ++{ ++ struct bcm2708_i2c *bi = platform_get_drvdata(pdev); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ i2c_del_adapter(&bi->adapter); ++ free_irq(bi->irq, bi); ++ iounmap(bi->base); ++ clk_disable_unprepare(bi->clk); ++ clk_put(bi->clk); ++ kfree(bi); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm2708_i2c_of_match[] = { ++ { .compatible = "brcm,bcm2708-i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2708_i2c_of_match); ++ ++static struct platform_driver bcm2708_i2c_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2708_i2c_of_match, ++ }, ++ .probe = bcm2708_i2c_probe, ++ .remove = bcm2708_i2c_remove, ++}; ++ ++// module_platform_driver(bcm2708_i2c_driver); ++ ++ ++static int __init bcm2708_i2c_init(void) ++{ ++ return platform_driver_register(&bcm2708_i2c_driver); ++} ++ ++static void __exit bcm2708_i2c_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_i2c_driver); ++} ++ ++module_init(bcm2708_i2c_init); ++module_exit(bcm2708_i2c_exit); ++ ++ ++ ++MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRV_NAME); diff --git a/target/linux/brcm2708/patches-4.1/0021-bcm2835-add-v4l2-camera-device.patch b/target/linux/brcm2708/patches-4.1/0021-bcm2835-add-v4l2-camera-device.patch new file mode 100644 index 0000000..a7cd4e4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0021-bcm2835-add-v4l2-camera-device.patch @@ -0,0 +1,7280 @@ +From 0cb249ef323fd1e4f85d88953c61525f10318424 Mon Sep 17 00:00:00 2001 +From: Vincent Sanders +Date: Wed, 30 Jan 2013 12:45:18 +0000 +Subject: [PATCH 021/203] bcm2835: add v4l2 camera device + +- Supports raw YUV capture, preview, JPEG and H264. +- Uses videobuf2 for data transfer, using dma_buf. +- Uses 3.6.10 timestamping +- Camera power based on use +- Uses immutable input mode on video encoder + +Signed-off-by: Daniel Stone +Signed-off-by: Luke Diamand + +V4L2: Fixes from 6by9 + +V4L2: Fix EV values. Add manual shutter speed control + +V4L2 EV values should be in units of 1/1000. Corrected. +Add support for V4L2_CID_EXPOSURE_ABSOLUTE which should +give manual shutter control. Requires manual exposure mode +to be selected first. + +Signed-off-by: Dave Stevenson + +V4L2: Correct JPEG Q-factor range + +Should be 1-100, not 0-100 + +Signed-off-by: Dave Stevenson + +V4L2: Fix issue of driver jamming if STREAMON failed. + +Fix issue where the driver was left in a partially enabled +state if STREAMON failed, and would then reject many IOCTLs +as it thought it was streaming. + +Signed-off-by: Dave Stevenson + +V4L2: Fix ISO controls. + +Driver was passing the index to the GPU, and not the desired +ISO value. + +Signed-off-by: Dave Stevenson + +V4L2: Add flicker avoidance controls + +Add support for V4L2_CID_POWER_LINE_FREQUENCY to set flicker +avoidance frequencies. + +Signed-off-by: Dave Stevenson + +V4L2: Add support for frame rate control. + +Add support for frame rate (or time per frame as V4L2 +inverts it) control via s_parm. + +Signed-off-by: Dave Stevenson + +V4L2: Improve G_FBUF handling so we pass conformance + +Return some sane numbers for get framebuffer so that +we pass conformance. + +Signed-off-by: Dave Stevenson + +V4L2: Fix information advertised through g_vidfmt + +Width and height were being stored based on incorrect +values. + +Signed-off-by: Dave Stevenson + +V4L2: Add support for inline H264 headers + +Add support for V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER +to control H264 inline headers. +Requires firmware fix to work correctly, otherwise format +has to be set to H264 before this parameter is set. + +Signed-off-by: Dave Stevenson + +V4L2: Fix JPEG timestamp issue + +JPEG images were coming through from the GPU with timestamp +of 0. Detect this and give current system time instead +of some invalid value. + +Signed-off-by: Dave Stevenson + +V4L2: Fix issue when switching down JPEG resolution. + +JPEG buffer size calculation is based on input resolution. +Input resolution was being configured after output port +format. Caused failures if switching from one JPEG resolution +to a smaller one. + +Signed-off-by: Dave Stevenson + +V4L2: Enable MJPEG encoding + +Requires GPU firmware update to support MJPEG encoder. + +Signed-off-by: Dave Stevenson + +V4L2: Correct flag settings for compressed formats + +Set flags field correctly on enum_fmt_vid_cap for compressed +image formats. + +Signed-off-by: Dave Stevenson + +V4L2: H264 profile & level ctrls, FPS control and auto exp pri + +Several control handling updates. +H264 profile and level controls. +Timeperframe/FPS reworked to add V4L2_CID_EXPOSURE_AUTO_PRIORITY to +select whether AE is allowed to override the framerate specified. + +Signed-off-by: Dave Stevenson + +V4L2: Correct BGR24 to RGB24 in format table + +Signed-off-by: Dave Stevenson + +V4L2: Add additional pixel formats. Correct colourspace + +Adds the other flavours of YUYV, and NV12. +Corrects the overlay advertised colourspace. + +Signed-off-by: Dave Stevenson + +V4L2: Drop logging msg from info to debug + +Signed-off-by: Dave Stevenson + +V4L2: Initial pass at scene modes. + +Only supports exposure mode and metering modes. + +Signed-off-by: Dave Stevenson + +V4L2: Add manual white balance control. + +Adds support for V4L2_CID_RED_BALANCE and +V4L2_CID_BLUE_BALANCE. Only has an effect if +V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE has +V4L2_WHITE_BALANCE_MANUAL selected. + +Signed-off-by: Dave Stevenson + +config: Enable V4L / MMAL driver + +V4L2: Increase the MMAL timeout to 3sec + +MJPEG codec flush is now taking longer and results +in a kernel panic if the driver has stopped waiting for +the result when it finally completes. +Increase the timeout value from 1 to 3secs. + +Signed-off-by: Dave Stevenson + +V4L2: Add support for setting H264_I_PERIOD + +Adds support for the parameter V4L2_CID_MPEG_VIDEO_H264_I_PERIOD +to set the frequency with which I frames are produced. + +Signed-off-by: Dave Stevenson + +V4L2: Enable GPU function for removing padding from images. + +GPU can now support arbitrary strides, although may require +additional processing to achieve it. Enable this feature +so that the images delivered are the size requested. + +Signed-off-by: Dave Stevenson + +V4L2: Add support for V4L2_PIX_FMT_BGR32 + +Signed-off-by: Dave Stevenson + +V4L2: Set the colourspace to avoid odd YUV-RGB conversions + +Removes the amiguity from the conversion routines and stops +them dropping back to the SD vs HD choice of coeffs. + +Signed-off-by: Dave Stevenson + +V4L2: Make video/still threshold a run-time param + +Move the define for at what resolution the driver +switches from a video mode capture to a stills mode +capture to module parameters. + +Signed-off-by: Dave Stevenson + +V4L2: Fix incorrect pool sizing + +Signed-off-by: Dave Stevenson + +V4L2: Add option to disable enum_framesizes. + +Gstreamer's handling of a driver that advertises +V4L2_FRMSIZE_TYPE_STEPWISE to define the supported +resolutions is broken. See bug +https://bugzilla.gnome.org/show_bug.cgi?id=726521 + +Optional parameter of gst_v4l2src_is_broken added. +If non-zero, the driver claims not to support that +ioctl, and gstreamer should be happy again (it +guesses a set of defaults for itself). + +Signed-off-by: Dave Stevenson + +V4L2: Add support for more image formats + +Adds YVU420 (YV12), YVU420SP (NV21), and BGR888. + +Signed-off-by: Dave Stevenson + +V4L2: Extend range for V4L2_CID_MPEG_VIDEO_H264_I_PERIOD + +Request to extend the range from the fairly arbitrary +1000 frames (33 seconds at 30fps). Extend out to the +max range supported (int32 value). +Also allow 0, which is handled by the codec as only +send an I-frame on the first frame and never again. +There may be an exception if it detects a significant +scene change, but there's no easy way around that. + +Signed-off-by: Dave Stevenson + +bcm2835-camera: stop_streaming now has a void return + +BCM2835-V4L2: Fix compliance test failures + +VIDIOC_TRY_FMT and VIDIOC_S_FMT tests were faling due +to reporting V4L2_COLORSPACE_JPEG when the colour +format wasn't V4L2_PIX_FMT_JPEG. +Now reports V4L2_COLORSPACE_SMPTE170M for YUV formats. +--- + Documentation/video4linux/bcm2835-v4l2.txt | 60 + + drivers/media/platform/Kconfig | 2 + + drivers/media/platform/Makefile | 2 + + drivers/media/platform/bcm2835/Kconfig | 25 + + drivers/media/platform/bcm2835/Makefile | 5 + + drivers/media/platform/bcm2835/bcm2835-camera.c | 1828 +++++++++++++++++++++ + drivers/media/platform/bcm2835/bcm2835-camera.h | 126 ++ + drivers/media/platform/bcm2835/controls.c | 1322 +++++++++++++++ + drivers/media/platform/bcm2835/mmal-common.h | 52 + + drivers/media/platform/bcm2835/mmal-encodings.h | 127 ++ + drivers/media/platform/bcm2835/mmal-msg-common.h | 50 + + drivers/media/platform/bcm2835/mmal-msg-format.h | 81 + + drivers/media/platform/bcm2835/mmal-msg-port.h | 107 ++ + drivers/media/platform/bcm2835/mmal-msg.h | 404 +++++ + drivers/media/platform/bcm2835/mmal-parameters.h | 656 ++++++++ + drivers/media/platform/bcm2835/mmal-vchiq.c | 1916 ++++++++++++++++++++++ + drivers/media/platform/bcm2835/mmal-vchiq.h | 178 ++ + 17 files changed, 6941 insertions(+) + create mode 100644 Documentation/video4linux/bcm2835-v4l2.txt + create mode 100644 drivers/media/platform/bcm2835/Kconfig + create mode 100644 drivers/media/platform/bcm2835/Makefile + create mode 100644 drivers/media/platform/bcm2835/bcm2835-camera.c + create mode 100644 drivers/media/platform/bcm2835/bcm2835-camera.h + create mode 100644 drivers/media/platform/bcm2835/controls.c + create mode 100644 drivers/media/platform/bcm2835/mmal-common.h + create mode 100644 drivers/media/platform/bcm2835/mmal-encodings.h + create mode 100644 drivers/media/platform/bcm2835/mmal-msg-common.h + create mode 100644 drivers/media/platform/bcm2835/mmal-msg-format.h + create mode 100644 drivers/media/platform/bcm2835/mmal-msg-port.h + create mode 100644 drivers/media/platform/bcm2835/mmal-msg.h + create mode 100644 drivers/media/platform/bcm2835/mmal-parameters.h + create mode 100644 drivers/media/platform/bcm2835/mmal-vchiq.c + create mode 100644 drivers/media/platform/bcm2835/mmal-vchiq.h + +--- /dev/null ++++ b/Documentation/video4linux/bcm2835-v4l2.txt +@@ -0,0 +1,60 @@ ++ ++BCM2835 (aka Raspberry Pi) V4L2 driver ++====================================== ++ ++1. Copyright ++============ ++ ++Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ ++2. License ++========== ++ ++This program is free software; you can redistribute it and/or modify ++it under the terms of the GNU General Public License as published by ++the Free Software Foundation; either version 2 of the License, or ++(at your option) any later version. ++ ++This program is distributed in the hope that it will be useful, ++but WITHOUT ANY WARRANTY; without even the implied warranty of ++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++GNU General Public License for more details. ++ ++You should have received a copy of the GNU General Public License ++along with this program; if not, write to the Free Software ++Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ ++3. Quick Start ++============== ++ ++You need a version 1.0 or later of v4l2-ctl, available from: ++ git://git.linuxtv.org/v4l-utils.git ++ ++$ sudo modprobe bcm2835-v4l2 ++ ++Turn on the overlay: ++ ++$ v4l2-ctl --overlay=1 ++ ++Turn off the overlay: ++ ++$ v4l2-ctl --overlay=0 ++ ++Set the capture format for video: ++ ++$ v4l2-ctl --set-fmt-video=width=1920,height=1088,pixelformat=4 ++ ++(Note: 1088 not 1080). ++ ++Capture: ++ ++$ v4l2-ctl --stream-mmap=3 --stream-count=100 --stream-to=somefile.h264 ++ ++Stills capture: ++ ++$ v4l2-ctl --set-fmt-video=width=2592,height=1944,pixelformat=3 ++$ v4l2-ctl --stream-mmap=3 --stream-count=1 --stream-to=somefile.jpg ++ ++List of available formats: ++ ++$ v4l2-ctl --list-formats +--- a/drivers/media/platform/Kconfig ++++ b/drivers/media/platform/Kconfig +@@ -11,6 +11,8 @@ menuconfig V4L_PLATFORM_DRIVERS + + if V4L_PLATFORM_DRIVERS + ++source "drivers/media/platform/bcm2835/Kconfig" ++ + source "drivers/media/platform/marvell-ccic/Kconfig" + + config VIDEO_VIA_CAMERA +--- a/drivers/media/platform/Makefile ++++ b/drivers/media/platform/Makefile +@@ -2,6 +2,8 @@ + # Makefile for the video capture/playback device drivers. + # + ++obj-$(CONFIG_VIDEO_BCM2835) += bcm2835/ ++ + obj-$(CONFIG_VIDEO_TIMBERDALE) += timblogiw.o + obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o + +--- /dev/null ++++ b/drivers/media/platform/bcm2835/Kconfig +@@ -0,0 +1,25 @@ ++# Broadcom VideoCore IV v4l2 camera support ++ ++config VIDEO_BCM2835 ++ bool "Broadcom BCM2835 camera interface driver" ++ depends on VIDEO_V4L2 && (ARCH_BCM2708 || ARCH_BCM2709 || ARCH_BCM2835) ++ ---help--- ++ Say Y here to enable camera host interface devices for ++ Broadcom BCM2835 SoC. This operates over the VCHIQ interface ++ to a service running on VideoCore. ++ ++ ++if VIDEO_BCM2835 ++ ++config VIDEO_BCM2835_MMAL ++ tristate "Broadcom BM2835 MMAL camera interface driver" ++ depends on BCM2708_VCHIQ ++ select VIDEOBUF2_VMALLOC ++ ---help--- ++ This is a V4L2 driver for the Broadcom BCM2835 MMAL camera host interface ++ ++ To compile this driver as a module, choose M here: the ++ module will be called bcm2835-v4l2.o ++ ++ ++endif # VIDEO_BM2835 +--- /dev/null ++++ b/drivers/media/platform/bcm2835/Makefile +@@ -0,0 +1,5 @@ ++bcm2835-v4l2-objs := bcm2835-camera.o controls.o mmal-vchiq.o ++ ++obj-$(CONFIG_VIDEO_BCM2835_MMAL) += bcm2835-v4l2.o ++ ++ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 +--- /dev/null ++++ b/drivers/media/platform/bcm2835/bcm2835-camera.c +@@ -0,0 +1,1828 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mmal-common.h" ++#include "mmal-encodings.h" ++#include "mmal-vchiq.h" ++#include "mmal-msg.h" ++#include "mmal-parameters.h" ++#include "bcm2835-camera.h" ++ ++#define BM2835_MMAL_VERSION "0.0.2" ++#define BM2835_MMAL_MODULE_NAME "bcm2835-v4l2" ++#define MIN_WIDTH 16 ++#define MIN_HEIGHT 16 ++#define MAX_WIDTH 2592 ++#define MAX_HEIGHT 1944 ++#define MIN_BUFFER_SIZE (80*1024) ++ ++#define MAX_VIDEO_MODE_WIDTH 1280 ++#define MAX_VIDEO_MODE_HEIGHT 720 ++ ++MODULE_DESCRIPTION("Broadcom 2835 MMAL video capture"); ++MODULE_AUTHOR("Vincent Sanders"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(BM2835_MMAL_VERSION); ++ ++int bcm2835_v4l2_debug; ++module_param_named(debug, bcm2835_v4l2_debug, int, 0644); ++MODULE_PARM_DESC(bcm2835_v4l2_debug, "Debug level 0-2"); ++ ++int max_video_width = MAX_VIDEO_MODE_WIDTH; ++int max_video_height = MAX_VIDEO_MODE_HEIGHT; ++module_param(max_video_width, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); ++MODULE_PARM_DESC(max_video_width, "Threshold for video mode"); ++module_param(max_video_height, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); ++MODULE_PARM_DESC(max_video_height, "Threshold for video mode"); ++ ++/* Gstreamer bug https://bugzilla.gnome.org/show_bug.cgi?id=726521 ++ * v4l2src does bad (and actually wrong) things when the vidioc_enum_framesizes ++ * function says type V4L2_FRMSIZE_TYPE_STEPWISE, which we do by default. ++ * It's happier if we just don't say anything at all, when it then ++ * sets up a load of defaults that it thinks might work. ++ * If gst_v4l2src_is_broken is non-zero, then we remove the function from ++ * our function table list (actually switch to an alternate set, but same ++ * result). ++ */ ++int gst_v4l2src_is_broken = 0; ++module_param(gst_v4l2src_is_broken, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); ++MODULE_PARM_DESC(gst_v4l2src_is_broken, "If non-zero, enable workaround for Gstreamer"); ++ ++static struct bm2835_mmal_dev *gdev; /* global device data */ ++ ++#define FPS_MIN 1 ++#define FPS_MAX 90 ++ ++/* timeperframe: min/max and default */ ++static const struct v4l2_fract ++ tpf_min = {.numerator = 1, .denominator = FPS_MAX}, ++ tpf_max = {.numerator = 1, .denominator = FPS_MIN}, ++ tpf_default = {.numerator = 1000, .denominator = 30000}; ++ ++/* video formats */ ++static struct mmal_fmt formats[] = { ++ { ++ .name = "4:2:0, packed YUV", ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_I420, ++ .depth = 12, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "4:2:2, packed, YUYV", ++ .fourcc = V4L2_PIX_FMT_YUYV, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_YUYV, ++ .depth = 16, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "RGB24 (LE)", ++ .fourcc = V4L2_PIX_FMT_RGB24, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_BGR24, ++ .depth = 24, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "JPEG", ++ .fourcc = V4L2_PIX_FMT_JPEG, ++ .flags = V4L2_FMT_FLAG_COMPRESSED, ++ .mmal = MMAL_ENCODING_JPEG, ++ .depth = 8, ++ .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE, ++ }, ++ { ++ .name = "H264", ++ .fourcc = V4L2_PIX_FMT_H264, ++ .flags = V4L2_FMT_FLAG_COMPRESSED, ++ .mmal = MMAL_ENCODING_H264, ++ .depth = 8, ++ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE, ++ }, ++ { ++ .name = "MJPEG", ++ .fourcc = V4L2_PIX_FMT_MJPEG, ++ .flags = V4L2_FMT_FLAG_COMPRESSED, ++ .mmal = MMAL_ENCODING_MJPEG, ++ .depth = 8, ++ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE, ++ }, ++ { ++ .name = "4:2:2, packed, YVYU", ++ .fourcc = V4L2_PIX_FMT_YVYU, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_YVYU, ++ .depth = 16, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "4:2:2, packed, VYUY", ++ .fourcc = V4L2_PIX_FMT_VYUY, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_VYUY, ++ .depth = 16, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "4:2:2, packed, UYVY", ++ .fourcc = V4L2_PIX_FMT_UYVY, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_UYVY, ++ .depth = 16, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "4:2:0, packed, NV12", ++ .fourcc = V4L2_PIX_FMT_NV12, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_NV12, ++ .depth = 12, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "RGB24 (BE)", ++ .fourcc = V4L2_PIX_FMT_BGR24, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_RGB24, ++ .depth = 24, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "4:2:0, packed YVU", ++ .fourcc = V4L2_PIX_FMT_YVU420, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_YV12, ++ .depth = 12, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "4:2:0, packed, NV21", ++ .fourcc = V4L2_PIX_FMT_NV21, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_NV21, ++ .depth = 12, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++ { ++ .name = "RGB32 (BE)", ++ .fourcc = V4L2_PIX_FMT_BGR32, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_BGRA, ++ .depth = 32, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ }, ++}; ++ ++static struct mmal_fmt *get_format(struct v4l2_format *f) ++{ ++ struct mmal_fmt *fmt; ++ unsigned int k; ++ ++ for (k = 0; k < ARRAY_SIZE(formats); k++) { ++ fmt = &formats[k]; ++ if (fmt->fourcc == f->fmt.pix.pixelformat) ++ break; ++ } ++ ++ if (k == ARRAY_SIZE(formats)) ++ return NULL; ++ ++ return &formats[k]; ++} ++ ++/* ------------------------------------------------------------------ ++ Videobuf queue operations ++ ------------------------------------------------------------------*/ ++ ++static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, ++ unsigned int *nbuffers, unsigned int *nplanes, ++ unsigned int sizes[], void *alloc_ctxs[]) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ unsigned long size; ++ ++ /* refuse queue setup if port is not configured */ ++ if (dev->capture.port == NULL) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s: capture port not configured\n", __func__); ++ return -EINVAL; ++ } ++ ++ size = dev->capture.port->current_buffer.size; ++ if (size == 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s: capture port buffer size is zero\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (*nbuffers < (dev->capture.port->current_buffer.num + 2)) ++ *nbuffers = (dev->capture.port->current_buffer.num + 2); ++ ++ *nplanes = 1; ++ ++ sizes[0] = size; ++ ++ /* ++ * videobuf2-vmalloc allocator is context-less so no need to set ++ * alloc_ctxs array. ++ */ ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", ++ __func__, dev); ++ ++ return 0; ++} ++ ++static int buffer_prepare(struct vb2_buffer *vb) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); ++ unsigned long size; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", ++ __func__, dev); ++ ++ BUG_ON(dev->capture.port == NULL); ++ BUG_ON(dev->capture.fmt == NULL); ++ ++ size = dev->capture.stride * dev->capture.height; ++ if (vb2_plane_size(vb, 0) < size) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s data will not fit into plane (%lu < %lu)\n", ++ __func__, vb2_plane_size(vb, 0), size); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static inline bool is_capturing(struct bm2835_mmal_dev *dev) ++{ ++ return dev->capture.camera_port == ++ &dev-> ++ component[MMAL_COMPONENT_CAMERA]->output[MMAL_CAMERA_PORT_CAPTURE]; ++} ++ ++static void buffer_cb(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ int status, ++ struct mmal_buffer *buf, ++ unsigned long length, u32 mmal_flags, s64 dts, s64 pts) ++{ ++ struct bm2835_mmal_dev *dev = port->cb_ctx; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: status:%d, buf:%p, length:%lu, flags %u, pts %lld\n", ++ __func__, status, buf, length, mmal_flags, pts); ++ ++ if (status != 0) { ++ /* error in transfer */ ++ if (buf != NULL) { ++ /* there was a buffer with the error so return it */ ++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ } ++ return; ++ } else if (length == 0) { ++ /* stream ended */ ++ if (buf != NULL) { ++ /* this should only ever happen if the port is ++ * disabled and there are buffers still queued ++ */ ++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ pr_debug("Empty buffer"); ++ } else if (dev->capture.frame_count) { ++ /* grab another frame */ ++ if (is_capturing(dev)) { ++ pr_debug("Grab another frame"); ++ vchiq_mmal_port_parameter_set( ++ instance, ++ dev->capture. ++ camera_port, ++ MMAL_PARAMETER_CAPTURE, ++ &dev->capture. ++ frame_count, ++ sizeof(dev->capture.frame_count)); ++ } ++ } else { ++ /* signal frame completion */ ++ complete(&dev->capture.frame_cmplt); ++ } ++ } else { ++ if (dev->capture.frame_count) { ++ if (dev->capture.vc_start_timestamp != -1 && ++ pts != 0) { ++ s64 runtime_us = pts - ++ dev->capture.vc_start_timestamp; ++ u32 div = 0; ++ u32 rem = 0; ++ ++ div = ++ div_u64_rem(runtime_us, USEC_PER_SEC, &rem); ++ buf->vb.v4l2_buf.timestamp.tv_sec = ++ dev->capture.kernel_start_ts.tv_sec - 1 + ++ div; ++ buf->vb.v4l2_buf.timestamp.tv_usec = ++ dev->capture.kernel_start_ts.tv_usec + rem; ++ ++ if (buf->vb.v4l2_buf.timestamp.tv_usec >= ++ USEC_PER_SEC) { ++ buf->vb.v4l2_buf.timestamp.tv_sec++; ++ buf->vb.v4l2_buf.timestamp.tv_usec -= ++ USEC_PER_SEC; ++ } ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Convert start time %d.%06d and %llu " ++ "with offset %llu to %d.%06d\n", ++ (int)dev->capture.kernel_start_ts. ++ tv_sec, ++ (int)dev->capture.kernel_start_ts. ++ tv_usec, ++ dev->capture.vc_start_timestamp, pts, ++ (int)buf->vb.v4l2_buf.timestamp.tv_sec, ++ (int)buf->vb.v4l2_buf.timestamp. ++ tv_usec); ++ } else { ++ v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); ++ } ++ ++ vb2_set_plane_payload(&buf->vb, 0, length); ++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); ++ ++ if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS && ++ is_capturing(dev)) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Grab another frame as buffer has EOS"); ++ vchiq_mmal_port_parameter_set( ++ instance, ++ dev->capture. ++ camera_port, ++ MMAL_PARAMETER_CAPTURE, ++ &dev->capture. ++ frame_count, ++ sizeof(dev->capture.frame_count)); ++ } ++ } else { ++ /* signal frame completion */ ++ complete(&dev->capture.frame_cmplt); ++ } ++ } ++} ++ ++static int enable_camera(struct bm2835_mmal_dev *dev) ++{ ++ int ret; ++ if (!dev->camera_use_count) { ++ ret = vchiq_mmal_component_enable( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_CAMERA]); ++ if (ret < 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed enabling camera, ret %d\n", ret); ++ return -EINVAL; ++ } ++ } ++ dev->camera_use_count++; ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, "enabled camera (refcount %d)\n", ++ dev->camera_use_count); ++ return 0; ++} ++ ++static int disable_camera(struct bm2835_mmal_dev *dev) ++{ ++ int ret; ++ if (!dev->camera_use_count) { ++ v4l2_err(&dev->v4l2_dev, ++ "Disabled the camera when already disabled\n"); ++ return -EINVAL; ++ } ++ dev->camera_use_count--; ++ if (!dev->camera_use_count) { ++ unsigned int i = 0xFFFFFFFF; ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Disabling camera\n"); ++ ret = ++ vchiq_mmal_component_disable( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_CAMERA]); ++ if (ret < 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed disabling camera, ret %d\n", ret); ++ return -EINVAL; ++ } ++ vchiq_mmal_port_parameter_set( ++ dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]->control, ++ MMAL_PARAMETER_CAMERA_NUM, &i, ++ sizeof(i)); ++ } ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Camera refcount now %d\n", dev->camera_use_count); ++ return 0; ++} ++ ++static void buffer_queue(struct vb2_buffer *vb) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); ++ struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb); ++ int ret; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: dev:%p buf:%p\n", __func__, dev, buf); ++ ++ buf->buffer = vb2_plane_vaddr(&buf->vb, 0); ++ buf->buffer_size = vb2_plane_size(&buf->vb, 0); ++ ++ ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf); ++ if (ret < 0) ++ v4l2_err(&dev->v4l2_dev, "%s: error submitting buffer\n", ++ __func__); ++} ++ ++static int start_streaming(struct vb2_queue *vq, unsigned int count) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ int ret; ++ int parameter_size; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", ++ __func__, dev); ++ ++ /* ensure a format has actually been set */ ++ if (dev->capture.port == NULL) ++ return -EINVAL; ++ ++ if (enable_camera(dev) < 0) { ++ v4l2_err(&dev->v4l2_dev, "Failed to enable camera\n"); ++ return -EINVAL; ++ } ++ ++ /*init_completion(&dev->capture.frame_cmplt); */ ++ ++ /* enable frame capture */ ++ dev->capture.frame_count = 1; ++ ++ /* if the preview is not already running, wait for a few frames for AGC ++ * to settle down. ++ */ ++ if (!dev->component[MMAL_COMPONENT_PREVIEW]->enabled) ++ msleep(300); ++ ++ /* enable the connection from camera to encoder (if applicable) */ ++ if (dev->capture.camera_port != dev->capture.port ++ && dev->capture.camera_port) { ++ ret = vchiq_mmal_port_enable(dev->instance, ++ dev->capture.camera_port, NULL); ++ if (ret) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to enable encode tunnel - error %d\n", ++ ret); ++ return -1; ++ } ++ } ++ ++ /* Get VC timestamp at this point in time */ ++ parameter_size = sizeof(dev->capture.vc_start_timestamp); ++ if (vchiq_mmal_port_parameter_get(dev->instance, ++ dev->capture.camera_port, ++ MMAL_PARAMETER_SYSTEM_TIME, ++ &dev->capture.vc_start_timestamp, ++ ¶meter_size)) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to get VC start time - update your VC f/w\n"); ++ ++ /* Flag to indicate just to rely on kernel timestamps */ ++ dev->capture.vc_start_timestamp = -1; ++ } else ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Start time %lld size %d\n", ++ dev->capture.vc_start_timestamp, parameter_size); ++ ++ v4l2_get_timestamp(&dev->capture.kernel_start_ts); ++ ++ /* enable the camera port */ ++ dev->capture.port->cb_ctx = dev; ++ ret = ++ vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb); ++ if (ret) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to enable capture port - error %d. " ++ "Disabling camera port again\n", ret); ++ ++ vchiq_mmal_port_disable(dev->instance, ++ dev->capture.camera_port); ++ if (disable_camera(dev) < 0) { ++ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n"); ++ return -EINVAL; ++ } ++ return -1; ++ } ++ ++ /* capture the first frame */ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ dev->capture.camera_port, ++ MMAL_PARAMETER_CAPTURE, ++ &dev->capture.frame_count, ++ sizeof(dev->capture.frame_count)); ++ return 0; ++} ++ ++/* abort streaming and wait for last buffer */ ++static void stop_streaming(struct vb2_queue *vq) ++{ ++ int ret; ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", ++ __func__, dev); ++ ++ init_completion(&dev->capture.frame_cmplt); ++ dev->capture.frame_count = 0; ++ ++ /* ensure a format has actually been set */ ++ if (dev->capture.port == NULL) { ++ v4l2_err(&dev->v4l2_dev, ++ "no capture port - stream not started?\n"); ++ return; ++ } ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "stopping capturing\n"); ++ ++ /* stop capturing frames */ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ dev->capture.camera_port, ++ MMAL_PARAMETER_CAPTURE, ++ &dev->capture.frame_count, ++ sizeof(dev->capture.frame_count)); ++ ++ /* wait for last frame to complete */ ++ ret = wait_for_completion_timeout(&dev->capture.frame_cmplt, HZ); ++ if (ret <= 0) ++ v4l2_err(&dev->v4l2_dev, ++ "error %d waiting for frame completion\n", ret); ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "disabling connection\n"); ++ ++ /* disable the connection from camera to encoder */ ++ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.camera_port); ++ if (!ret && dev->capture.camera_port != dev->capture.port) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "disabling port\n"); ++ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.port); ++ } else if (dev->capture.camera_port != dev->capture.port) { ++ v4l2_err(&dev->v4l2_dev, "port_disable failed, error %d\n", ++ ret); ++ } ++ ++ if (disable_camera(dev) < 0) ++ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n"); ++} ++ ++static void bm2835_mmal_lock(struct vb2_queue *vq) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ mutex_lock(&dev->mutex); ++} ++ ++static void bm2835_mmal_unlock(struct vb2_queue *vq) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ mutex_unlock(&dev->mutex); ++} ++ ++static struct vb2_ops bm2835_mmal_video_qops = { ++ .queue_setup = queue_setup, ++ .buf_prepare = buffer_prepare, ++ .buf_queue = buffer_queue, ++ .start_streaming = start_streaming, ++ .stop_streaming = stop_streaming, ++ .wait_prepare = bm2835_mmal_unlock, ++ .wait_finish = bm2835_mmal_lock, ++}; ++ ++/* ------------------------------------------------------------------ ++ IOCTL operations ++ ------------------------------------------------------------------*/ ++ ++/* overlay ioctl */ ++static int vidioc_enum_fmt_vid_overlay(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct mmal_fmt *fmt; ++ ++ if (f->index >= ARRAY_SIZE(formats)) ++ return -EINVAL; ++ ++ fmt = &formats[f->index]; ++ ++ strlcpy(f->description, fmt->name, sizeof(f->description)); ++ f->pixelformat = fmt->fourcc; ++ f->flags = fmt->flags; ++ ++ return 0; ++} ++ ++static int vidioc_g_fmt_vid_overlay(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ ++ f->fmt.win = dev->overlay; ++ ++ return 0; ++} ++ ++static int vidioc_try_fmt_vid_overlay(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ /* Only support one format so get the current one. */ ++ vidioc_g_fmt_vid_overlay(file, priv, f); ++ ++ /* todo: allow the size and/or offset to be changed. */ ++ return 0; ++} ++ ++static int vidioc_s_fmt_vid_overlay(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ ++ vidioc_try_fmt_vid_overlay(file, priv, f); ++ ++ dev->overlay = f->fmt.win; ++ ++ /* todo: program the preview port parameters */ ++ return 0; ++} ++ ++static int vidioc_overlay(struct file *file, void *f, unsigned int on) ++{ ++ int ret; ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct vchiq_mmal_port *src; ++ struct vchiq_mmal_port *dst; ++ struct mmal_parameter_displayregion prev_config = { ++ .set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA | ++ MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN, ++ .layer = PREVIEW_LAYER, ++ .alpha = 255, ++ .fullscreen = 0, ++ .dest_rect = { ++ .x = dev->overlay.w.left, ++ .y = dev->overlay.w.top, ++ .width = dev->overlay.w.width, ++ .height = dev->overlay.w.height, ++ }, ++ }; ++ ++ if ((on && dev->component[MMAL_COMPONENT_PREVIEW]->enabled) || ++ (!on && !dev->component[MMAL_COMPONENT_PREVIEW]->enabled)) ++ return 0; /* already in requested state */ ++ ++ src = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW]; ++ ++ if (!on) { ++ /* disconnect preview ports and disable component */ ++ ret = vchiq_mmal_port_disable(dev->instance, src); ++ if (!ret) ++ ret = ++ vchiq_mmal_port_connect_tunnel(dev->instance, src, ++ NULL); ++ if (ret >= 0) ++ ret = vchiq_mmal_component_disable( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_PREVIEW]); ++ ++ disable_camera(dev); ++ return ret; ++ } ++ ++ /* set preview port format and connect it to output */ ++ dst = &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]; ++ ++ ret = vchiq_mmal_port_set_format(dev->instance, src); ++ if (ret < 0) ++ goto error; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, dst, ++ MMAL_PARAMETER_DISPLAYREGION, ++ &prev_config, sizeof(prev_config)); ++ if (ret < 0) ++ goto error; ++ ++ if (enable_camera(dev) < 0) ++ goto error; ++ ++ ret = vchiq_mmal_component_enable( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_PREVIEW]); ++ if (ret < 0) ++ goto error; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "connecting %p to %p\n", ++ src, dst); ++ ret = vchiq_mmal_port_connect_tunnel(dev->instance, src, dst); ++ if (!ret) ++ ret = vchiq_mmal_port_enable(dev->instance, src, NULL); ++error: ++ return ret; ++} ++ ++static int vidioc_g_fbuf(struct file *file, void *fh, ++ struct v4l2_framebuffer *a) ++{ ++ /* The video overlay must stay within the framebuffer and can't be ++ positioned independently. */ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct vchiq_mmal_port *preview_port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW]; ++ a->flags = V4L2_FBUF_FLAG_OVERLAY; ++ a->fmt.width = preview_port->es.video.width; ++ a->fmt.height = preview_port->es.video.height; ++ a->fmt.pixelformat = V4L2_PIX_FMT_YUV420; ++ a->fmt.bytesperline = (preview_port->es.video.width * 3)>>1; ++ a->fmt.sizeimage = (preview_port->es.video.width * ++ preview_port->es.video.height * 3)>>1; ++ a->fmt.colorspace = V4L2_COLORSPACE_SMPTE170M; ++ ++ return 0; ++} ++ ++/* input ioctls */ ++static int vidioc_enum_input(struct file *file, void *priv, ++ struct v4l2_input *inp) ++{ ++ /* only a single camera input */ ++ if (inp->index != 0) ++ return -EINVAL; ++ ++ inp->type = V4L2_INPUT_TYPE_CAMERA; ++ sprintf(inp->name, "Camera %u", inp->index); ++ return 0; ++} ++ ++static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) ++{ ++ *i = 0; ++ return 0; ++} ++ ++static int vidioc_s_input(struct file *file, void *priv, unsigned int i) ++{ ++ if (i != 0) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++/* capture ioctls */ ++static int vidioc_querycap(struct file *file, void *priv, ++ struct v4l2_capability *cap) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ u32 major; ++ u32 minor; ++ ++ vchiq_mmal_version(dev->instance, &major, &minor); ++ ++ strcpy(cap->driver, "bm2835 mmal"); ++ snprintf(cap->card, sizeof(cap->card), "mmal service %d.%d", ++ major, minor); ++ ++ snprintf(cap->bus_info, sizeof(cap->bus_info), ++ "platform:%s", dev->v4l2_dev.name); ++ cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY | ++ V4L2_CAP_STREAMING | V4L2_CAP_READWRITE; ++ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; ++ ++ return 0; ++} ++ ++static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct mmal_fmt *fmt; ++ ++ if (f->index >= ARRAY_SIZE(formats)) ++ return -EINVAL; ++ ++ fmt = &formats[f->index]; ++ ++ strlcpy(f->description, fmt->name, sizeof(f->description)); ++ f->pixelformat = fmt->fourcc; ++ f->flags = fmt->flags; ++ ++ return 0; ++} ++ ++static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ ++ f->fmt.pix.width = dev->capture.width; ++ f->fmt.pix.height = dev->capture.height; ++ f->fmt.pix.field = V4L2_FIELD_NONE; ++ f->fmt.pix.pixelformat = dev->capture.fmt->fourcc; ++ f->fmt.pix.bytesperline = dev->capture.stride; ++ f->fmt.pix.sizeimage = dev->capture.buffersize; ++ ++ if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_RGB24) ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB; ++ else if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_JPEG) ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; ++ else ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; ++ f->fmt.pix.priv = 0; ++ ++ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix, ++ __func__); ++ return 0; ++} ++ ++static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct mmal_fmt *mfmt; ++ ++ mfmt = get_format(f); ++ if (!mfmt) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Fourcc format (0x%08x) unknown.\n", ++ f->fmt.pix.pixelformat); ++ f->fmt.pix.pixelformat = formats[0].fourcc; ++ mfmt = get_format(f); ++ } ++ ++ f->fmt.pix.field = V4L2_FIELD_NONE; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Clipping/aligning %dx%d format %08X\n", ++ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat); ++ ++ v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 1, ++ &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 1, 0); ++ f->fmt.pix.bytesperline = (f->fmt.pix.width * mfmt->depth)>>3; ++ ++ /* Image buffer has to be padded to allow for alignment, even though ++ * we then remove that padding before delivering the buffer. ++ */ ++ f->fmt.pix.sizeimage = ((f->fmt.pix.height+15)&~15) * ++ (((f->fmt.pix.width+31)&~31) * mfmt->depth) >> 3; ++ ++ if ((mfmt->flags & V4L2_FMT_FLAG_COMPRESSED) && ++ f->fmt.pix.sizeimage < MIN_BUFFER_SIZE) ++ f->fmt.pix.sizeimage = MIN_BUFFER_SIZE; ++ ++ if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB; ++ else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_JPEG) ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; ++ else ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; ++ f->fmt.pix.priv = 0; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Now %dx%d format %08X\n", ++ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat); ++ ++ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix, ++ __func__); ++ return 0; ++} ++ ++static int mmal_setup_components(struct bm2835_mmal_dev *dev, ++ struct v4l2_format *f) ++{ ++ int ret; ++ struct vchiq_mmal_port *port = NULL, *camera_port = NULL; ++ struct vchiq_mmal_component *encode_component = NULL; ++ struct mmal_fmt *mfmt = get_format(f); ++ ++ BUG_ON(!mfmt); ++ ++ if (dev->capture.encode_component) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "vid_cap - disconnect previous tunnel\n"); ++ ++ /* Disconnect any previous connection */ ++ vchiq_mmal_port_connect_tunnel(dev->instance, ++ dev->capture.camera_port, NULL); ++ dev->capture.camera_port = NULL; ++ ret = vchiq_mmal_component_disable(dev->instance, ++ dev->capture. ++ encode_component); ++ if (ret) ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to disable encode component %d\n", ++ ret); ++ ++ dev->capture.encode_component = NULL; ++ } ++ /* format dependant port setup */ ++ switch (mfmt->mmal_component) { ++ case MMAL_COMPONENT_CAMERA: ++ /* Make a further decision on port based on resolution */ ++ if (f->fmt.pix.width <= max_video_width ++ && f->fmt.pix.height <= max_video_height) ++ camera_port = port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO]; ++ else ++ camera_port = port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE]; ++ break; ++ case MMAL_COMPONENT_IMAGE_ENCODE: ++ encode_component = dev->component[MMAL_COMPONENT_IMAGE_ENCODE]; ++ port = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0]; ++ camera_port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE]; ++ break; ++ case MMAL_COMPONENT_VIDEO_ENCODE: ++ encode_component = dev->component[MMAL_COMPONENT_VIDEO_ENCODE]; ++ port = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ camera_port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO]; ++ break; ++ default: ++ break; ++ } ++ ++ if (!port) ++ return -EINVAL; ++ ++ if (encode_component) ++ camera_port->format.encoding = MMAL_ENCODING_OPAQUE; ++ else ++ camera_port->format.encoding = mfmt->mmal; ++ ++ camera_port->format.encoding_variant = 0; ++ camera_port->es.video.width = f->fmt.pix.width; ++ camera_port->es.video.height = f->fmt.pix.height; ++ camera_port->es.video.crop.x = 0; ++ camera_port->es.video.crop.y = 0; ++ camera_port->es.video.crop.width = f->fmt.pix.width; ++ camera_port->es.video.crop.height = f->fmt.pix.height; ++ camera_port->es.video.frame_rate.num = 0; ++ camera_port->es.video.frame_rate.den = 1; ++ camera_port->es.video.color_space = MMAL_COLOR_SPACE_JPEG_JFIF; ++ ++ ret = vchiq_mmal_port_set_format(dev->instance, camera_port); ++ ++ if (!ret ++ && camera_port == ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO]) { ++ bool overlay_enabled = ++ !!dev->component[MMAL_COMPONENT_PREVIEW]->enabled; ++ struct vchiq_mmal_port *preview_port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW]; ++ /* Preview and encode ports need to match on resolution */ ++ if (overlay_enabled) { ++ /* Need to disable the overlay before we can update ++ * the resolution ++ */ ++ ret = ++ vchiq_mmal_port_disable(dev->instance, ++ preview_port); ++ if (!ret) ++ ret = ++ vchiq_mmal_port_connect_tunnel( ++ dev->instance, ++ preview_port, ++ NULL); ++ } ++ preview_port->es.video.width = f->fmt.pix.width; ++ preview_port->es.video.height = f->fmt.pix.height; ++ preview_port->es.video.crop.x = 0; ++ preview_port->es.video.crop.y = 0; ++ preview_port->es.video.crop.width = f->fmt.pix.width; ++ preview_port->es.video.crop.height = f->fmt.pix.height; ++ preview_port->es.video.frame_rate.num = ++ dev->capture.timeperframe.denominator; ++ preview_port->es.video.frame_rate.den = ++ dev->capture.timeperframe.numerator; ++ ret = vchiq_mmal_port_set_format(dev->instance, preview_port); ++ if (overlay_enabled) { ++ ret = vchiq_mmal_port_connect_tunnel( ++ dev->instance, ++ preview_port, ++ &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]); ++ if (!ret) ++ ret = vchiq_mmal_port_enable(dev->instance, ++ preview_port, ++ NULL); ++ } ++ } ++ ++ if (ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s failed to set format %dx%d %08X\n", __func__, ++ f->fmt.pix.width, f->fmt.pix.height, ++ f->fmt.pix.pixelformat); ++ /* ensure capture is not going to be tried */ ++ dev->capture.port = NULL; ++ } else { ++ if (encode_component) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "vid_cap - set up encode comp\n"); ++ ++ /* configure buffering */ ++ camera_port->current_buffer.size = ++ camera_port->recommended_buffer.size; ++ camera_port->current_buffer.num = ++ camera_port->recommended_buffer.num; ++ ++ ret = ++ vchiq_mmal_port_connect_tunnel( ++ dev->instance, ++ camera_port, ++ &encode_component->input[0]); ++ if (ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "%s failed to create connection\n", ++ __func__); ++ /* ensure capture is not going to be tried */ ++ dev->capture.port = NULL; ++ } else { ++ port->es.video.width = f->fmt.pix.width; ++ port->es.video.height = f->fmt.pix.height; ++ port->es.video.crop.x = 0; ++ port->es.video.crop.y = 0; ++ port->es.video.crop.width = f->fmt.pix.width; ++ port->es.video.crop.height = f->fmt.pix.height; ++ port->es.video.frame_rate.num = ++ dev->capture.timeperframe.denominator; ++ port->es.video.frame_rate.den = ++ dev->capture.timeperframe.numerator; ++ ++ port->format.encoding = mfmt->mmal; ++ port->format.encoding_variant = 0; ++ /* Set any encoding specific parameters */ ++ switch (mfmt->mmal_component) { ++ case MMAL_COMPONENT_VIDEO_ENCODE: ++ port->format.bitrate = ++ dev->capture.encode_bitrate; ++ break; ++ case MMAL_COMPONENT_IMAGE_ENCODE: ++ /* Could set EXIF parameters here */ ++ break; ++ default: ++ break; ++ } ++ ret = vchiq_mmal_port_set_format(dev->instance, ++ port); ++ if (ret) ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "%s failed to set format %dx%d fmt %08X\n", ++ __func__, ++ f->fmt.pix.width, ++ f->fmt.pix.height, ++ f->fmt.pix.pixelformat ++ ); ++ } ++ ++ if (!ret) { ++ ret = vchiq_mmal_component_enable( ++ dev->instance, ++ encode_component); ++ if (ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "%s Failed to enable encode components\n", ++ __func__); ++ } ++ } ++ if (!ret) { ++ /* configure buffering */ ++ port->current_buffer.num = 1; ++ port->current_buffer.size = ++ f->fmt.pix.sizeimage; ++ if (port->format.encoding == ++ MMAL_ENCODING_JPEG) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "JPG - buf size now %d was %d\n", ++ f->fmt.pix.sizeimage, ++ port->current_buffer.size); ++ port->current_buffer.size = ++ (f->fmt.pix.sizeimage < ++ (100 << 10)) ++ ? (100 << 10) : f->fmt.pix. ++ sizeimage; ++ } ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "vid_cap - cur_buf.size set to %d\n", ++ f->fmt.pix.sizeimage); ++ port->current_buffer.alignment = 0; ++ } ++ } else { ++ /* configure buffering */ ++ camera_port->current_buffer.num = 1; ++ camera_port->current_buffer.size = f->fmt.pix.sizeimage; ++ camera_port->current_buffer.alignment = 0; ++ } ++ ++ if (!ret) { ++ dev->capture.fmt = mfmt; ++ dev->capture.stride = f->fmt.pix.bytesperline; ++ dev->capture.width = camera_port->es.video.crop.width; ++ dev->capture.height = camera_port->es.video.crop.height; ++ dev->capture.buffersize = port->current_buffer.size; ++ ++ /* select port for capture */ ++ dev->capture.port = port; ++ dev->capture.camera_port = camera_port; ++ dev->capture.encode_component = encode_component; ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "Set dev->capture.fmt %08X, %dx%d, stride %d, size %d", ++ port->format.encoding, ++ dev->capture.width, dev->capture.height, ++ dev->capture.stride, dev->capture.buffersize); ++ } ++ } ++ ++ /* todo: Need to convert the vchiq/mmal error into a v4l2 error. */ ++ return ret; ++} ++ ++static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ int ret; ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct mmal_fmt *mfmt; ++ ++ /* try the format to set valid parameters */ ++ ret = vidioc_try_fmt_vid_cap(file, priv, f); ++ if (ret) { ++ v4l2_err(&dev->v4l2_dev, ++ "vid_cap - vidioc_try_fmt_vid_cap failed\n"); ++ return ret; ++ } ++ ++ /* if a capture is running refuse to set format */ ++ if (vb2_is_busy(&dev->capture.vb_vidq)) { ++ v4l2_info(&dev->v4l2_dev, "%s device busy\n", __func__); ++ return -EBUSY; ++ } ++ ++ /* If the format is unsupported v4l2 says we should switch to ++ * a supported one and not return an error. */ ++ mfmt = get_format(f); ++ if (!mfmt) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Fourcc format (0x%08x) unknown.\n", ++ f->fmt.pix.pixelformat); ++ f->fmt.pix.pixelformat = formats[0].fourcc; ++ mfmt = get_format(f); ++ } ++ ++ ret = mmal_setup_components(dev, f); ++ if (ret != 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s: failed to setup mmal components: %d\n", ++ __func__, ret); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++int vidioc_enum_framesizes(struct file *file, void *fh, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ static const struct v4l2_frmsize_stepwise sizes = { ++ MIN_WIDTH, MAX_WIDTH, 2, ++ MIN_HEIGHT, MAX_HEIGHT, 2 ++ }; ++ int i; ++ ++ if (fsize->index) ++ return -EINVAL; ++ for (i = 0; i < ARRAY_SIZE(formats); i++) ++ if (formats[i].fourcc == fsize->pixel_format) ++ break; ++ if (i == ARRAY_SIZE(formats)) ++ return -EINVAL; ++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; ++ fsize->stepwise = sizes; ++ return 0; ++} ++ ++/* timeperframe is arbitrary and continous */ ++static int vidioc_enum_frameintervals(struct file *file, void *priv, ++ struct v4l2_frmivalenum *fival) ++{ ++ int i; ++ ++ if (fival->index) ++ return -EINVAL; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) ++ if (formats[i].fourcc == fival->pixel_format) ++ break; ++ if (i == ARRAY_SIZE(formats)) ++ return -EINVAL; ++ ++ /* regarding width & height - we support any within range */ ++ if (fival->width < MIN_WIDTH || fival->width > MAX_WIDTH || ++ fival->height < MIN_HEIGHT || fival->height > MAX_HEIGHT) ++ return -EINVAL; ++ ++ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; ++ ++ /* fill in stepwise (step=1.0 is requred by V4L2 spec) */ ++ fival->stepwise.min = tpf_min; ++ fival->stepwise.max = tpf_max; ++ fival->stepwise.step = (struct v4l2_fract) {1, 1}; ++ ++ return 0; ++} ++ ++static int vidioc_g_parm(struct file *file, void *priv, ++ struct v4l2_streamparm *parm) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ ++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; ++ parm->parm.capture.timeperframe = dev->capture.timeperframe; ++ parm->parm.capture.readbuffers = 1; ++ return 0; ++} ++ ++#define FRACT_CMP(a, OP, b) \ ++ ((u64)(a).numerator * (b).denominator OP \ ++ (u64)(b).numerator * (a).denominator) ++ ++static int vidioc_s_parm(struct file *file, void *priv, ++ struct v4l2_streamparm *parm) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct v4l2_fract tpf; ++ struct mmal_parameter_rational fps_param; ++ ++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ tpf = parm->parm.capture.timeperframe; ++ ++ /* tpf: {*, 0} resets timing; clip to [min, max]*/ ++ tpf = tpf.denominator ? tpf : tpf_default; ++ tpf = FRACT_CMP(tpf, <, tpf_min) ? tpf_min : tpf; ++ tpf = FRACT_CMP(tpf, >, tpf_max) ? tpf_max : tpf; ++ ++ dev->capture.timeperframe = tpf; ++ parm->parm.capture.timeperframe = tpf; ++ parm->parm.capture.readbuffers = 1; ++ ++ fps_param.num = 0; /* Select variable fps, and then use ++ * FPS_RANGE to select the actual limits. ++ */ ++ fps_param.den = 1; ++ set_framerate_params(dev); ++ ++ return 0; ++} ++ ++static const struct v4l2_ioctl_ops camera0_ioctl_ops = { ++ /* overlay */ ++ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay, ++ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay, ++ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay, ++ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay, ++ .vidioc_overlay = vidioc_overlay, ++ .vidioc_g_fbuf = vidioc_g_fbuf, ++ ++ /* inputs */ ++ .vidioc_enum_input = vidioc_enum_input, ++ .vidioc_g_input = vidioc_g_input, ++ .vidioc_s_input = vidioc_s_input, ++ ++ /* capture */ ++ .vidioc_querycap = vidioc_querycap, ++ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, ++ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, ++ ++ /* buffer management */ ++ .vidioc_reqbufs = vb2_ioctl_reqbufs, ++ .vidioc_create_bufs = vb2_ioctl_create_bufs, ++ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, ++ .vidioc_querybuf = vb2_ioctl_querybuf, ++ .vidioc_qbuf = vb2_ioctl_qbuf, ++ .vidioc_dqbuf = vb2_ioctl_dqbuf, ++ .vidioc_enum_framesizes = vidioc_enum_framesizes, ++ .vidioc_enum_frameintervals = vidioc_enum_frameintervals, ++ .vidioc_g_parm = vidioc_g_parm, ++ .vidioc_s_parm = vidioc_s_parm, ++ .vidioc_streamon = vb2_ioctl_streamon, ++ .vidioc_streamoff = vb2_ioctl_streamoff, ++ ++ .vidioc_log_status = v4l2_ctrl_log_status, ++ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, ++ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, ++}; ++ ++static const struct v4l2_ioctl_ops camera0_ioctl_ops_gstreamer = { ++ /* overlay */ ++ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay, ++ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay, ++ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay, ++ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay, ++ .vidioc_overlay = vidioc_overlay, ++ .vidioc_g_fbuf = vidioc_g_fbuf, ++ ++ /* inputs */ ++ .vidioc_enum_input = vidioc_enum_input, ++ .vidioc_g_input = vidioc_g_input, ++ .vidioc_s_input = vidioc_s_input, ++ ++ /* capture */ ++ .vidioc_querycap = vidioc_querycap, ++ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, ++ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, ++ ++ /* buffer management */ ++ .vidioc_reqbufs = vb2_ioctl_reqbufs, ++ .vidioc_create_bufs = vb2_ioctl_create_bufs, ++ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, ++ .vidioc_querybuf = vb2_ioctl_querybuf, ++ .vidioc_qbuf = vb2_ioctl_qbuf, ++ .vidioc_dqbuf = vb2_ioctl_dqbuf, ++ /* Remove this function ptr to fix gstreamer bug ++ .vidioc_enum_framesizes = vidioc_enum_framesizes, */ ++ .vidioc_enum_frameintervals = vidioc_enum_frameintervals, ++ .vidioc_g_parm = vidioc_g_parm, ++ .vidioc_s_parm = vidioc_s_parm, ++ .vidioc_streamon = vb2_ioctl_streamon, ++ .vidioc_streamoff = vb2_ioctl_streamoff, ++ ++ .vidioc_log_status = v4l2_ctrl_log_status, ++ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, ++ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, ++}; ++ ++/* ------------------------------------------------------------------ ++ Driver init/finalise ++ ------------------------------------------------------------------*/ ++ ++static const struct v4l2_file_operations camera0_fops = { ++ .owner = THIS_MODULE, ++ .open = v4l2_fh_open, ++ .release = vb2_fop_release, ++ .read = vb2_fop_read, ++ .poll = vb2_fop_poll, ++ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ ++ .mmap = vb2_fop_mmap, ++}; ++ ++static struct video_device vdev_template = { ++ .name = "camera0", ++ .fops = &camera0_fops, ++ .ioctl_ops = &camera0_ioctl_ops, ++ .release = video_device_release_empty, ++}; ++ ++static int set_camera_parameters(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *camera) ++{ ++ int ret; ++ struct mmal_parameter_camera_config cam_config = { ++ .max_stills_w = MAX_WIDTH, ++ .max_stills_h = MAX_HEIGHT, ++ .stills_yuv422 = 1, ++ .one_shot_stills = 1, ++ .max_preview_video_w = (max_video_width > 1920) ? ++ max_video_width : 1920, ++ .max_preview_video_h = (max_video_height > 1088) ? ++ max_video_height : 1088, ++ .num_preview_video_frames = 3, ++ .stills_capture_circular_buffer_height = 0, ++ .fast_preview_resume = 0, ++ .use_stc_timestamp = MMAL_PARAM_TIMESTAMP_MODE_RAW_STC ++ }; ++ ++ ret = vchiq_mmal_port_parameter_set(instance, &camera->control, ++ MMAL_PARAMETER_CAMERA_CONFIG, ++ &cam_config, sizeof(cam_config)); ++ return ret; ++} ++ ++/* MMAL instance and component init */ ++static int __init mmal_init(struct bm2835_mmal_dev *dev) ++{ ++ int ret; ++ struct mmal_es_format *format; ++ u32 bool_true = 1; ++ ++ ret = vchiq_mmal_init(&dev->instance); ++ if (ret < 0) ++ return ret; ++ ++ /* get the camera component ready */ ++ ret = vchiq_mmal_component_init(dev->instance, "ril.camera", ++ &dev->component[MMAL_COMPONENT_CAMERA]); ++ if (ret < 0) ++ goto unreg_mmal; ++ ++ if (dev->component[MMAL_COMPONENT_CAMERA]->outputs < ++ MMAL_CAMERA_PORT_COUNT) { ++ ret = -EINVAL; ++ goto unreg_camera; ++ } ++ ++ ret = set_camera_parameters(dev->instance, ++ dev->component[MMAL_COMPONENT_CAMERA]); ++ if (ret < 0) ++ goto unreg_camera; ++ ++ format = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW].format; ++ ++ format->encoding = MMAL_ENCODING_OPAQUE; ++ format->encoding_variant = MMAL_ENCODING_I420; ++ ++ format->es->video.width = 1024; ++ format->es->video.height = 768; ++ format->es->video.crop.x = 0; ++ format->es->video.crop.y = 0; ++ format->es->video.crop.width = 1024; ++ format->es->video.crop.height = 768; ++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ ++ format->es->video.frame_rate.den = 1; ++ ++ format = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO].format; ++ ++ format->encoding = MMAL_ENCODING_OPAQUE; ++ format->encoding_variant = MMAL_ENCODING_I420; ++ ++ format->es->video.width = 1024; ++ format->es->video.height = 768; ++ format->es->video.crop.x = 0; ++ format->es->video.crop.y = 0; ++ format->es->video.crop.width = 1024; ++ format->es->video.crop.height = 768; ++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ ++ format->es->video.frame_rate.den = 1; ++ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO], ++ MMAL_PARAMETER_NO_IMAGE_PADDING, ++ &bool_true, sizeof(bool_true)); ++ ++ format = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE].format; ++ ++ format->encoding = MMAL_ENCODING_OPAQUE; ++ ++ format->es->video.width = 2592; ++ format->es->video.height = 1944; ++ format->es->video.crop.x = 0; ++ format->es->video.crop.y = 0; ++ format->es->video.crop.width = 2592; ++ format->es->video.crop.height = 1944; ++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ ++ format->es->video.frame_rate.den = 1; ++ ++ dev->capture.width = format->es->video.width; ++ dev->capture.height = format->es->video.height; ++ dev->capture.fmt = &formats[0]; ++ dev->capture.encode_component = NULL; ++ dev->capture.timeperframe = tpf_default; ++ dev->capture.enc_profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; ++ dev->capture.enc_level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0; ++ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE], ++ MMAL_PARAMETER_NO_IMAGE_PADDING, ++ &bool_true, sizeof(bool_true)); ++ ++ /* get the preview component ready */ ++ ret = vchiq_mmal_component_init( ++ dev->instance, "ril.video_render", ++ &dev->component[MMAL_COMPONENT_PREVIEW]); ++ if (ret < 0) ++ goto unreg_camera; ++ ++ if (dev->component[MMAL_COMPONENT_PREVIEW]->inputs < 1) { ++ ret = -EINVAL; ++ pr_debug("too few input ports %d needed %d\n", ++ dev->component[MMAL_COMPONENT_PREVIEW]->inputs, 1); ++ goto unreg_preview; ++ } ++ ++ /* get the image encoder component ready */ ++ ret = vchiq_mmal_component_init( ++ dev->instance, "ril.image_encode", ++ &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]); ++ if (ret < 0) ++ goto unreg_preview; ++ ++ if (dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs < 1) { ++ ret = -EINVAL; ++ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n", ++ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs, ++ 1); ++ goto unreg_image_encoder; ++ } ++ ++ /* get the video encoder component ready */ ++ ret = vchiq_mmal_component_init(dev->instance, "ril.video_encode", ++ &dev-> ++ component[MMAL_COMPONENT_VIDEO_ENCODE]); ++ if (ret < 0) ++ goto unreg_image_encoder; ++ ++ if (dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs < 1) { ++ ret = -EINVAL; ++ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n", ++ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs, ++ 1); ++ goto unreg_vid_encoder; ++ } ++ ++ { ++ struct vchiq_mmal_port *encoder_port = ++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ encoder_port->format.encoding = MMAL_ENCODING_H264; ++ ret = vchiq_mmal_port_set_format(dev->instance, ++ encoder_port); ++ } ++ ++ { ++ unsigned int enable = 1; ++ vchiq_mmal_port_parameter_set( ++ dev->instance, ++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control, ++ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT, ++ &enable, sizeof(enable)); ++ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control, ++ MMAL_PARAMETER_MINIMISE_FRAGMENTATION, ++ &enable, ++ sizeof(enable)); ++ } ++ ret = bm2835_mmal_set_all_camera_controls(dev); ++ if (ret < 0) ++ goto unreg_vid_encoder; ++ ++ return 0; ++ ++unreg_vid_encoder: ++ pr_err("Cleanup: Destroy video encoder\n"); ++ vchiq_mmal_component_finalise( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]); ++ ++unreg_image_encoder: ++ pr_err("Cleanup: Destroy image encoder\n"); ++ vchiq_mmal_component_finalise( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]); ++ ++unreg_preview: ++ pr_err("Cleanup: Destroy video render\n"); ++ vchiq_mmal_component_finalise(dev->instance, ++ dev->component[MMAL_COMPONENT_PREVIEW]); ++ ++unreg_camera: ++ pr_err("Cleanup: Destroy camera\n"); ++ vchiq_mmal_component_finalise(dev->instance, ++ dev->component[MMAL_COMPONENT_CAMERA]); ++ ++unreg_mmal: ++ vchiq_mmal_finalise(dev->instance); ++ return ret; ++} ++ ++static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev, ++ struct video_device *vfd) ++{ ++ int ret; ++ ++ *vfd = vdev_template; ++ if (gst_v4l2src_is_broken) { ++ v4l2_info(&dev->v4l2_dev, ++ "Work-around for gstreamer issue is active.\n"); ++ vfd->ioctl_ops = &camera0_ioctl_ops_gstreamer; ++ } ++ ++ vfd->v4l2_dev = &dev->v4l2_dev; ++ ++ vfd->lock = &dev->mutex; ++ ++ vfd->queue = &dev->capture.vb_vidq; ++ ++ /* video device needs to be able to access instance data */ ++ video_set_drvdata(vfd, dev); ++ ++ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1); ++ if (ret < 0) ++ return ret; ++ ++ v4l2_info(vfd->v4l2_dev, ++ "V4L2 device registered as %s - stills mode > %dx%d\n", ++ video_device_node_name(vfd), max_video_width, max_video_height); ++ ++ return 0; ++} ++ ++static struct v4l2_format default_v4l2_format = { ++ .fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG, ++ .fmt.pix.width = 1024, ++ .fmt.pix.bytesperline = 1024, ++ .fmt.pix.height = 768, ++ .fmt.pix.sizeimage = 1024*768, ++}; ++ ++static int __init bm2835_mmal_init(void) ++{ ++ int ret; ++ struct bm2835_mmal_dev *dev; ++ struct vb2_queue *q; ++ ++ dev = kzalloc(sizeof(*gdev), GFP_KERNEL); ++ if (!dev) ++ return -ENOMEM; ++ ++ /* setup device defaults */ ++ dev->overlay.w.left = 150; ++ dev->overlay.w.top = 50; ++ dev->overlay.w.width = 1024; ++ dev->overlay.w.height = 768; ++ dev->overlay.clipcount = 0; ++ dev->overlay.field = V4L2_FIELD_NONE; ++ ++ dev->capture.fmt = &formats[3]; /* JPEG */ ++ ++ /* v4l device registration */ ++ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), ++ "%s", BM2835_MMAL_MODULE_NAME); ++ ret = v4l2_device_register(NULL, &dev->v4l2_dev); ++ if (ret) ++ goto free_dev; ++ ++ /* setup v4l controls */ ++ ret = bm2835_mmal_init_controls(dev, &dev->ctrl_handler); ++ if (ret < 0) ++ goto unreg_dev; ++ dev->v4l2_dev.ctrl_handler = &dev->ctrl_handler; ++ ++ /* mmal init */ ++ ret = mmal_init(dev); ++ if (ret < 0) ++ goto unreg_dev; ++ ++ /* initialize queue */ ++ q = &dev->capture.vb_vidq; ++ memset(q, 0, sizeof(*q)); ++ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ; ++ q->drv_priv = dev; ++ q->buf_struct_size = sizeof(struct mmal_buffer); ++ q->ops = &bm2835_mmal_video_qops; ++ q->mem_ops = &vb2_vmalloc_memops; ++ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ++ ret = vb2_queue_init(q); ++ if (ret < 0) ++ goto unreg_dev; ++ ++ /* v4l2 core mutex used to protect all fops and v4l2 ioctls. */ ++ mutex_init(&dev->mutex); ++ ++ /* initialise video devices */ ++ ret = bm2835_mmal_init_device(dev, &dev->vdev); ++ if (ret < 0) ++ goto unreg_dev; ++ ++ /* Really want to call vidioc_s_fmt_vid_cap with the default ++ * format, but currently the APIs don't join up. ++ */ ++ ret = mmal_setup_components(dev, &default_v4l2_format); ++ if (ret < 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s: could not setup components\n", __func__); ++ goto unreg_dev; ++ } ++ ++ v4l2_info(&dev->v4l2_dev, ++ "Broadcom 2835 MMAL video capture ver %s loaded.\n", ++ BM2835_MMAL_VERSION); ++ ++ gdev = dev; ++ return 0; ++ ++unreg_dev: ++ v4l2_ctrl_handler_free(&dev->ctrl_handler); ++ v4l2_device_unregister(&dev->v4l2_dev); ++ ++free_dev: ++ kfree(dev); ++ ++ v4l2_err(&dev->v4l2_dev, ++ "%s: error %d while loading driver\n", ++ BM2835_MMAL_MODULE_NAME, ret); ++ ++ return ret; ++} ++ ++static void __exit bm2835_mmal_exit(void) ++{ ++ if (!gdev) ++ return; ++ ++ v4l2_info(&gdev->v4l2_dev, "unregistering %s\n", ++ video_device_node_name(&gdev->vdev)); ++ ++ video_unregister_device(&gdev->vdev); ++ ++ if (gdev->capture.encode_component) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &gdev->v4l2_dev, ++ "mmal_exit - disconnect tunnel\n"); ++ vchiq_mmal_port_connect_tunnel(gdev->instance, ++ gdev->capture.camera_port, NULL); ++ vchiq_mmal_component_disable(gdev->instance, ++ gdev->capture.encode_component); ++ } ++ vchiq_mmal_component_disable(gdev->instance, ++ gdev->component[MMAL_COMPONENT_CAMERA]); ++ ++ vchiq_mmal_component_finalise(gdev->instance, ++ gdev-> ++ component[MMAL_COMPONENT_VIDEO_ENCODE]); ++ ++ vchiq_mmal_component_finalise(gdev->instance, ++ gdev-> ++ component[MMAL_COMPONENT_IMAGE_ENCODE]); ++ ++ vchiq_mmal_component_finalise(gdev->instance, ++ gdev->component[MMAL_COMPONENT_PREVIEW]); ++ ++ vchiq_mmal_component_finalise(gdev->instance, ++ gdev->component[MMAL_COMPONENT_CAMERA]); ++ ++ vchiq_mmal_finalise(gdev->instance); ++ ++ v4l2_ctrl_handler_free(&gdev->ctrl_handler); ++ ++ v4l2_device_unregister(&gdev->v4l2_dev); ++ ++ kfree(gdev); ++} ++ ++module_init(bm2835_mmal_init); ++module_exit(bm2835_mmal_exit); +--- /dev/null ++++ b/drivers/media/platform/bcm2835/bcm2835-camera.h +@@ -0,0 +1,126 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ * ++ * core driver device ++ */ ++ ++#define V4L2_CTRL_COUNT 28 /* number of v4l controls */ ++ ++enum { ++ MMAL_COMPONENT_CAMERA = 0, ++ MMAL_COMPONENT_PREVIEW, ++ MMAL_COMPONENT_IMAGE_ENCODE, ++ MMAL_COMPONENT_VIDEO_ENCODE, ++ MMAL_COMPONENT_COUNT ++}; ++ ++enum { ++ MMAL_CAMERA_PORT_PREVIEW = 0, ++ MMAL_CAMERA_PORT_VIDEO, ++ MMAL_CAMERA_PORT_CAPTURE, ++ MMAL_CAMERA_PORT_COUNT ++}; ++ ++#define PREVIEW_LAYER 2 ++ ++extern int bcm2835_v4l2_debug; ++ ++struct bm2835_mmal_dev { ++ /* v4l2 devices */ ++ struct v4l2_device v4l2_dev; ++ struct video_device vdev; ++ struct mutex mutex; ++ ++ /* controls */ ++ struct v4l2_ctrl_handler ctrl_handler; ++ struct v4l2_ctrl *ctrls[V4L2_CTRL_COUNT]; ++ enum v4l2_scene_mode scene_mode; ++ struct mmal_colourfx colourfx; ++ int hflip; ++ int vflip; ++ int red_gain; ++ int blue_gain; ++ enum mmal_parameter_exposuremode exposure_mode_user; ++ enum v4l2_exposure_auto_type exposure_mode_v4l2_user; ++ /* active exposure mode may differ if selected via a scene mode */ ++ enum mmal_parameter_exposuremode exposure_mode_active; ++ enum mmal_parameter_exposuremeteringmode metering_mode; ++ unsigned int manual_shutter_speed; ++ bool exp_auto_priority; ++ ++ /* allocated mmal instance and components */ ++ struct vchiq_mmal_instance *instance; ++ struct vchiq_mmal_component *component[MMAL_COMPONENT_COUNT]; ++ int camera_use_count; ++ ++ struct v4l2_window overlay; ++ ++ struct { ++ unsigned int width; /* width */ ++ unsigned int height; /* height */ ++ unsigned int stride; /* stride */ ++ unsigned int buffersize; /* buffer size with padding */ ++ struct mmal_fmt *fmt; ++ struct v4l2_fract timeperframe; ++ ++ /* H264 encode bitrate */ ++ int encode_bitrate; ++ /* H264 bitrate mode. CBR/VBR */ ++ int encode_bitrate_mode; ++ /* H264 profile */ ++ enum v4l2_mpeg_video_h264_profile enc_profile; ++ /* H264 level */ ++ enum v4l2_mpeg_video_h264_level enc_level; ++ /* JPEG Q-factor */ ++ int q_factor; ++ ++ struct vb2_queue vb_vidq; ++ ++ /* VC start timestamp for streaming */ ++ s64 vc_start_timestamp; ++ /* Kernel start timestamp for streaming */ ++ struct timeval kernel_start_ts; ++ ++ struct vchiq_mmal_port *port; /* port being used for capture */ ++ /* camera port being used for capture */ ++ struct vchiq_mmal_port *camera_port; ++ /* component being used for encode */ ++ struct vchiq_mmal_component *encode_component; ++ /* number of frames remaining which driver should capture */ ++ unsigned int frame_count; ++ /* last frame completion */ ++ struct completion frame_cmplt; ++ ++ } capture; ++ ++}; ++ ++int bm2835_mmal_init_controls( ++ struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl_handler *hdl); ++ ++int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev); ++int set_framerate_params(struct bm2835_mmal_dev *dev); ++ ++/* Debug helpers */ ++ ++#define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \ ++{ \ ++ v4l2_dbg(level, debug, dev, \ ++"%s: w %u h %u field %u pfmt 0x%x bpl %u sz_img %u colorspace 0x%x priv %u\n", \ ++ desc == NULL ? "" : desc, \ ++ (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \ ++ (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \ ++ (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \ ++} +--- /dev/null ++++ b/drivers/media/platform/bcm2835/controls.c +@@ -0,0 +1,1322 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mmal-common.h" ++#include "mmal-vchiq.h" ++#include "mmal-parameters.h" ++#include "bcm2835-camera.h" ++ ++/* The supported V4L2_CID_AUTO_EXPOSURE_BIAS values are from -4.0 to +4.0. ++ * MMAL values are in 1/6th increments so the MMAL range is -24 to +24. ++ * V4L2 docs say value "is expressed in terms of EV, drivers should interpret ++ * the values as 0.001 EV units, where the value 1000 stands for +1 EV." ++ * V4L2 is limited to a max of 32 values in a menu, so count in 1/3rds from ++ * -4 to +4 ++ */ ++static const s64 ev_bias_qmenu[] = { ++ -4000, -3667, -3333, ++ -3000, -2667, -2333, ++ -2000, -1667, -1333, ++ -1000, -667, -333, ++ 0, 333, 667, ++ 1000, 1333, 1667, ++ 2000, 2333, 2667, ++ 3000, 3333, 3667, ++ 4000 ++}; ++ ++/* Supported ISO values ++ * ISOO = auto ISO ++ */ ++static const s64 iso_qmenu[] = { ++ 0, 100, 200, 400, 800, ++}; ++ ++static const s64 mains_freq_qmenu[] = { ++ V4L2_CID_POWER_LINE_FREQUENCY_DISABLED, ++ V4L2_CID_POWER_LINE_FREQUENCY_50HZ, ++ V4L2_CID_POWER_LINE_FREQUENCY_60HZ, ++ V4L2_CID_POWER_LINE_FREQUENCY_AUTO ++}; ++ ++/* Supported video encode modes */ ++static const s64 bitrate_mode_qmenu[] = { ++ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, ++ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, ++}; ++ ++enum bm2835_mmal_ctrl_type { ++ MMAL_CONTROL_TYPE_STD, ++ MMAL_CONTROL_TYPE_STD_MENU, ++ MMAL_CONTROL_TYPE_INT_MENU, ++ MMAL_CONTROL_TYPE_CLUSTER, /* special cluster entry */ ++}; ++ ++struct bm2835_mmal_v4l2_ctrl; ++ ++typedef int(bm2835_mmal_v4l2_ctrl_cb)( ++ struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl); ++ ++struct bm2835_mmal_v4l2_ctrl { ++ u32 id; /* v4l2 control identifier */ ++ enum bm2835_mmal_ctrl_type type; ++ /* control minimum value or ++ * mask for MMAL_CONTROL_TYPE_STD_MENU */ ++ s32 min; ++ s32 max; /* maximum value of control */ ++ s32 def; /* default value of control */ ++ s32 step; /* step size of the control */ ++ const s64 *imenu; /* integer menu array */ ++ u32 mmal_id; /* mmal parameter id */ ++ bm2835_mmal_v4l2_ctrl_cb *setter; ++ bool ignore_errors; ++}; ++ ++struct v4l2_to_mmal_effects_setting { ++ u32 v4l2_effect; ++ u32 mmal_effect; ++ s32 col_fx_enable; ++ s32 col_fx_fixed_cbcr; ++ u32 u; ++ u32 v; ++ u32 num_effect_params; ++ u32 effect_params[MMAL_MAX_IMAGEFX_PARAMETERS]; ++}; ++ ++static const struct v4l2_to_mmal_effects_setting ++ v4l2_to_mmal_effects_values[] = { ++ { V4L2_COLORFX_NONE, MMAL_PARAM_IMAGEFX_NONE, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_BW, MMAL_PARAM_IMAGEFX_NONE, ++ 1, 0, 128, 128, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SEPIA, MMAL_PARAM_IMAGEFX_NONE, ++ 1, 0, 87, 151, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_NEGATIVE, MMAL_PARAM_IMAGEFX_NEGATIVE, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_EMBOSS, MMAL_PARAM_IMAGEFX_EMBOSS, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SKETCH, MMAL_PARAM_IMAGEFX_SKETCH, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SKY_BLUE, MMAL_PARAM_IMAGEFX_PASTEL, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_GRASS_GREEN, MMAL_PARAM_IMAGEFX_WATERCOLOUR, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SKIN_WHITEN, MMAL_PARAM_IMAGEFX_WASHEDOUT, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_VIVID, MMAL_PARAM_IMAGEFX_SATURATION, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_AQUA, MMAL_PARAM_IMAGEFX_NONE, ++ 1, 0, 171, 121, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_ART_FREEZE, MMAL_PARAM_IMAGEFX_HATCH, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SILHOUETTE, MMAL_PARAM_IMAGEFX_FILM, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SOLARIZATION, MMAL_PARAM_IMAGEFX_SOLARIZE, ++ 0, 0, 0, 0, 5, {1, 128, 160, 160, 48} }, ++ { V4L2_COLORFX_ANTIQUE, MMAL_PARAM_IMAGEFX_COLOURBALANCE, ++ 0, 0, 0, 0, 3, {108, 274, 238, 0, 0} }, ++ { V4L2_COLORFX_SET_CBCR, MMAL_PARAM_IMAGEFX_NONE, ++ 1, 1, 0, 0, 0, {0, 0, 0, 0, 0} } ++}; ++ ++struct v4l2_mmal_scene_config { ++ enum v4l2_scene_mode v4l2_scene; ++ enum mmal_parameter_exposuremode exposure_mode; ++ enum mmal_parameter_exposuremeteringmode metering_mode; ++}; ++ ++static const struct v4l2_mmal_scene_config scene_configs[] = { ++ /* V4L2_SCENE_MODE_NONE automatically added */ ++ { ++ V4L2_SCENE_MODE_NIGHT, ++ MMAL_PARAM_EXPOSUREMODE_NIGHT, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE ++ }, ++ { ++ V4L2_SCENE_MODE_SPORTS, ++ MMAL_PARAM_EXPOSUREMODE_SPORTS, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE ++ }, ++}; ++ ++/* control handlers*/ ++ ++static int ctrl_set_rational(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ struct mmal_parameter_rational rational_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ rational_value.num = ctrl->val; ++ rational_value.den = 100; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &rational_value, ++ sizeof(rational_value)); ++} ++ ++static int ctrl_set_value(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ u32_value = ctrl->val; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_value_menu(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *control; ++ ++ if (ctrl->val > mmal_ctrl->max || ctrl->val < mmal_ctrl->min) ++ return 1; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ u32_value = mmal_ctrl->imenu[ctrl->val]; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_value_ev(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ s32 s32_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ s32_value = (ctrl->val-12)*2; /* Convert from index to 1/6ths */ ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &s32_value, sizeof(s32_value)); ++} ++ ++static int ctrl_set_rotate(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret; ++ u32 u32_value; ++ struct vchiq_mmal_component *camera; ++ ++ camera = dev->component[MMAL_COMPONENT_CAMERA]; ++ ++ u32_value = ((ctrl->val % 360) / 90) * 90; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ if (ret < 0) ++ return ret; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ if (ret < 0) ++ return ret; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ ++ return ret; ++} ++ ++static int ctrl_set_flip(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret; ++ u32 u32_value; ++ struct vchiq_mmal_component *camera; ++ ++ if (ctrl->id == V4L2_CID_HFLIP) ++ dev->hflip = ctrl->val; ++ else ++ dev->vflip = ctrl->val; ++ ++ camera = dev->component[MMAL_COMPONENT_CAMERA]; ++ ++ if (dev->hflip && dev->vflip) ++ u32_value = MMAL_PARAM_MIRROR_BOTH; ++ else if (dev->hflip) ++ u32_value = MMAL_PARAM_MIRROR_HORIZONTAL; ++ else if (dev->vflip) ++ u32_value = MMAL_PARAM_MIRROR_VERTICAL; ++ else ++ u32_value = MMAL_PARAM_MIRROR_NONE; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ if (ret < 0) ++ return ret; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ if (ret < 0) ++ return ret; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ ++ return ret; ++ ++} ++ ++static int ctrl_set_exposure(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ enum mmal_parameter_exposuremode exp_mode = dev->exposure_mode_user; ++ u32 shutter_speed = 0; ++ struct vchiq_mmal_port *control; ++ int ret = 0; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ if (mmal_ctrl->mmal_id == MMAL_PARAMETER_SHUTTER_SPEED) { ++ /* V4L2 is in 100usec increments. ++ * MMAL is 1usec. ++ */ ++ dev->manual_shutter_speed = ctrl->val * 100; ++ } else if (mmal_ctrl->mmal_id == MMAL_PARAMETER_EXPOSURE_MODE) { ++ switch (ctrl->val) { ++ case V4L2_EXPOSURE_AUTO: ++ exp_mode = MMAL_PARAM_EXPOSUREMODE_AUTO; ++ break; ++ ++ case V4L2_EXPOSURE_MANUAL: ++ exp_mode = MMAL_PARAM_EXPOSUREMODE_OFF; ++ break; ++ } ++ dev->exposure_mode_user = exp_mode; ++ dev->exposure_mode_v4l2_user = ctrl->val; ++ } else if (mmal_ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) { ++ dev->exp_auto_priority = ctrl->val; ++ } ++ ++ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) { ++ if (exp_mode == MMAL_PARAM_EXPOSUREMODE_OFF) ++ shutter_speed = dev->manual_shutter_speed; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_SHUTTER_SPEED, ++ &shutter_speed, ++ sizeof(shutter_speed)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &exp_mode, ++ sizeof(u32)); ++ dev->exposure_mode_active = exp_mode; ++ } ++ /* exposure_dynamic_framerate (V4L2_CID_EXPOSURE_AUTO_PRIORITY) should ++ * always apply irrespective of scene mode. ++ */ ++ ret += set_framerate_params(dev); ++ ++ return ret; ++} ++ ++static int ctrl_set_metering_mode(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ switch (ctrl->val) { ++ case V4L2_EXPOSURE_METERING_AVERAGE: ++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE; ++ break; ++ ++ case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED: ++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT; ++ break; ++ ++ case V4L2_EXPOSURE_METERING_SPOT: ++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT; ++ break; ++ ++ /* todo matrix weighting not added to Linux API till 3.9 ++ case V4L2_EXPOSURE_METERING_MATRIX: ++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX; ++ break; ++ */ ++ ++ } ++ ++ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) { ++ struct vchiq_mmal_port *control; ++ u32 u32_value = dev->metering_mode; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ } else ++ return 0; ++} ++ ++static int ctrl_set_flicker_avoidance(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ switch (ctrl->val) { ++ case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED: ++ u32_value = MMAL_PARAM_FLICKERAVOID_OFF; ++ break; ++ case V4L2_CID_POWER_LINE_FREQUENCY_50HZ: ++ u32_value = MMAL_PARAM_FLICKERAVOID_50HZ; ++ break; ++ case V4L2_CID_POWER_LINE_FREQUENCY_60HZ: ++ u32_value = MMAL_PARAM_FLICKERAVOID_60HZ; ++ break; ++ case V4L2_CID_POWER_LINE_FREQUENCY_AUTO: ++ u32_value = MMAL_PARAM_FLICKERAVOID_AUTO; ++ break; ++ } ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_awb_mode(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ switch (ctrl->val) { ++ case V4L2_WHITE_BALANCE_MANUAL: ++ u32_value = MMAL_PARAM_AWBMODE_OFF; ++ break; ++ ++ case V4L2_WHITE_BALANCE_AUTO: ++ u32_value = MMAL_PARAM_AWBMODE_AUTO; ++ break; ++ ++ case V4L2_WHITE_BALANCE_INCANDESCENT: ++ u32_value = MMAL_PARAM_AWBMODE_INCANDESCENT; ++ break; ++ ++ case V4L2_WHITE_BALANCE_FLUORESCENT: ++ u32_value = MMAL_PARAM_AWBMODE_FLUORESCENT; ++ break; ++ ++ case V4L2_WHITE_BALANCE_FLUORESCENT_H: ++ u32_value = MMAL_PARAM_AWBMODE_TUNGSTEN; ++ break; ++ ++ case V4L2_WHITE_BALANCE_HORIZON: ++ u32_value = MMAL_PARAM_AWBMODE_HORIZON; ++ break; ++ ++ case V4L2_WHITE_BALANCE_DAYLIGHT: ++ u32_value = MMAL_PARAM_AWBMODE_SUNLIGHT; ++ break; ++ ++ case V4L2_WHITE_BALANCE_FLASH: ++ u32_value = MMAL_PARAM_AWBMODE_FLASH; ++ break; ++ ++ case V4L2_WHITE_BALANCE_CLOUDY: ++ u32_value = MMAL_PARAM_AWBMODE_CLOUDY; ++ break; ++ ++ case V4L2_WHITE_BALANCE_SHADE: ++ u32_value = MMAL_PARAM_AWBMODE_SHADE; ++ break; ++ ++ } ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_awb_gains(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ struct vchiq_mmal_port *control; ++ struct mmal_parameter_awbgains gains; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ if (ctrl->id == V4L2_CID_RED_BALANCE) ++ dev->red_gain = ctrl->val; ++ else if (ctrl->id == V4L2_CID_BLUE_BALANCE) ++ dev->blue_gain = ctrl->val; ++ ++ gains.r_gain.num = dev->red_gain; ++ gains.b_gain.num = dev->blue_gain; ++ gains.r_gain.den = gains.b_gain.den = 1000; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &gains, sizeof(gains)); ++} ++ ++static int ctrl_set_image_effect(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret = -EINVAL; ++ int i, j; ++ struct vchiq_mmal_port *control; ++ struct mmal_parameter_imagefx_parameters imagefx; ++ ++ for (i = 0; i < ARRAY_SIZE(v4l2_to_mmal_effects_values); i++) { ++ if (ctrl->val == v4l2_to_mmal_effects_values[i].v4l2_effect) { ++ ++ imagefx.effect = ++ v4l2_to_mmal_effects_values[i].mmal_effect; ++ imagefx.num_effect_params = ++ v4l2_to_mmal_effects_values[i].num_effect_params; ++ ++ if (imagefx.num_effect_params > MMAL_MAX_IMAGEFX_PARAMETERS) ++ imagefx.num_effect_params = MMAL_MAX_IMAGEFX_PARAMETERS; ++ ++ for (j = 0; j < imagefx.num_effect_params; j++) ++ imagefx.effect_parameter[j] = ++ v4l2_to_mmal_effects_values[i].effect_params[j]; ++ ++ dev->colourfx.enable = ++ v4l2_to_mmal_effects_values[i].col_fx_enable; ++ if (!v4l2_to_mmal_effects_values[i].col_fx_fixed_cbcr) { ++ dev->colourfx.u = ++ v4l2_to_mmal_effects_values[i].u; ++ dev->colourfx.v = ++ v4l2_to_mmal_effects_values[i].v; ++ } ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ ret = vchiq_mmal_port_parameter_set( ++ dev->instance, control, ++ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS, ++ &imagefx, sizeof(imagefx)); ++ if (ret) ++ goto exit; ++ ++ ret = vchiq_mmal_port_parameter_set( ++ dev->instance, control, ++ MMAL_PARAMETER_COLOUR_EFFECT, ++ &dev->colourfx, sizeof(dev->colourfx)); ++ } ++ } ++ ++exit: ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "mmal_ctrl:%p ctrl id:0x%x ctrl val:%d imagefx:0x%x color_effect:%s u:%d v:%d ret %d(%d)\n", ++ mmal_ctrl, ctrl->id, ctrl->val, imagefx.effect, ++ dev->colourfx.enable ? "true" : "false", ++ dev->colourfx.u, dev->colourfx.v, ++ ret, (ret == 0 ? 0 : -EINVAL)); ++ return (ret == 0 ? 0 : EINVAL); ++} ++ ++static int ctrl_set_colfx(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret = -EINVAL; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ dev->colourfx.enable = (ctrl->val & 0xff00) >> 8; ++ dev->colourfx.enable = ctrl->val & 0xff; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, control, ++ MMAL_PARAMETER_COLOUR_EFFECT, ++ &dev->colourfx, sizeof(dev->colourfx)); ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: After: mmal_ctrl:%p ctrl id:0x%x ctrl val:%d ret %d(%d)\n", ++ __func__, mmal_ctrl, ctrl->id, ctrl->val, ret, ++ (ret == 0 ? 0 : -EINVAL)); ++ return (ret == 0 ? 0 : EINVAL); ++} ++ ++static int ctrl_set_bitrate(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret; ++ struct vchiq_mmal_port *encoder_out; ++ ++ dev->capture.encode_bitrate = ctrl->val; ++ ++ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, encoder_out, ++ mmal_ctrl->mmal_id, ++ &ctrl->val, sizeof(ctrl->val)); ++ ret = 0; ++ return ret; ++} ++ ++static int ctrl_set_bitrate_mode(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 bitrate_mode; ++ struct vchiq_mmal_port *encoder_out; ++ ++ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ ++ dev->capture.encode_bitrate_mode = ctrl->val; ++ switch (ctrl->val) { ++ default: ++ case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR: ++ bitrate_mode = MMAL_VIDEO_RATECONTROL_VARIABLE; ++ break; ++ case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR: ++ bitrate_mode = MMAL_VIDEO_RATECONTROL_CONSTANT; ++ break; ++ } ++ ++ vchiq_mmal_port_parameter_set(dev->instance, encoder_out, ++ mmal_ctrl->mmal_id, ++ &bitrate_mode, ++ sizeof(bitrate_mode)); ++ return 0; ++} ++ ++static int ctrl_set_image_encode_output(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *jpeg_out; ++ ++ jpeg_out = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0]; ++ ++ u32_value = ctrl->val; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, jpeg_out, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_video_encode_param_output(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *vid_enc_ctl; ++ ++ vid_enc_ctl = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ ++ u32_value = ctrl->val; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, vid_enc_ctl, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_video_encode_profile_level(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ struct mmal_parameter_video_profile param; ++ int ret = 0; ++ ++ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) { ++ switch (ctrl->val) { ++ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: ++ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: ++ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: ++ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: ++ dev->capture.enc_profile = ctrl->val; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) { ++ switch (ctrl->val) { ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1B: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: ++ dev->capture.enc_level = ctrl->val; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ } ++ ++ if (!ret) { ++ switch (dev->capture.enc_profile) { ++ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: ++ param.profile = MMAL_VIDEO_PROFILE_H264_BASELINE; ++ break; ++ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: ++ param.profile = ++ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE; ++ break; ++ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: ++ param.profile = MMAL_VIDEO_PROFILE_H264_MAIN; ++ break; ++ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: ++ param.profile = MMAL_VIDEO_PROFILE_H264_HIGH; ++ break; ++ default: ++ /* Should never get here */ ++ break; ++ } ++ ++ switch (dev->capture.enc_level) { ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: ++ param.level = MMAL_VIDEO_LEVEL_H264_1; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1B: ++ param.level = MMAL_VIDEO_LEVEL_H264_1b; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: ++ param.level = MMAL_VIDEO_LEVEL_H264_11; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: ++ param.level = MMAL_VIDEO_LEVEL_H264_12; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: ++ param.level = MMAL_VIDEO_LEVEL_H264_13; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: ++ param.level = MMAL_VIDEO_LEVEL_H264_2; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: ++ param.level = MMAL_VIDEO_LEVEL_H264_21; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: ++ param.level = MMAL_VIDEO_LEVEL_H264_22; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: ++ param.level = MMAL_VIDEO_LEVEL_H264_3; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: ++ param.level = MMAL_VIDEO_LEVEL_H264_31; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: ++ param.level = MMAL_VIDEO_LEVEL_H264_32; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: ++ param.level = MMAL_VIDEO_LEVEL_H264_4; ++ break; ++ default: ++ /* Should never get here */ ++ break; ++ } ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0], ++ mmal_ctrl->mmal_id, ++ ¶m, sizeof(param)); ++ } ++ return ret; ++} ++ ++static int ctrl_set_scene_mode(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret = 0; ++ int shutter_speed; ++ struct vchiq_mmal_port *control; ++ ++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "scene mode selected %d, was %d\n", ctrl->val, ++ dev->scene_mode); ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ if (ctrl->val == dev->scene_mode) ++ return 0; ++ ++ if (ctrl->val == V4L2_SCENE_MODE_NONE) { ++ /* Restore all user selections */ ++ dev->scene_mode = V4L2_SCENE_MODE_NONE; ++ ++ if (dev->exposure_mode_user == MMAL_PARAM_EXPOSUREMODE_OFF) ++ shutter_speed = dev->manual_shutter_speed; ++ else ++ shutter_speed = 0; ++ ++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n", ++ __func__, shutter_speed, dev->exposure_mode_user, ++ dev->metering_mode); ++ ret = vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_SHUTTER_SPEED, ++ &shutter_speed, ++ sizeof(shutter_speed)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &dev->exposure_mode_user, ++ sizeof(u32)); ++ dev->exposure_mode_active = dev->exposure_mode_user; ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_EXP_METERING_MODE, ++ &dev->metering_mode, ++ sizeof(u32)); ++ ret += set_framerate_params(dev); ++ } else { ++ /* Set up scene mode */ ++ int i; ++ const struct v4l2_mmal_scene_config *scene = NULL; ++ int shutter_speed; ++ enum mmal_parameter_exposuremode exposure_mode; ++ enum mmal_parameter_exposuremeteringmode metering_mode; ++ ++ for (i = 0; i < ARRAY_SIZE(scene_configs); i++) { ++ if (scene_configs[i].v4l2_scene == ++ ctrl->val) { ++ scene = &scene_configs[i]; ++ break; ++ } ++ } ++ if (i >= ARRAY_SIZE(scene_configs)) ++ return -EINVAL; ++ ++ /* Set all the values */ ++ dev->scene_mode = ctrl->val; ++ ++ if (scene->exposure_mode == MMAL_PARAM_EXPOSUREMODE_OFF) ++ shutter_speed = dev->manual_shutter_speed; ++ else ++ shutter_speed = 0; ++ exposure_mode = scene->exposure_mode; ++ metering_mode = scene->metering_mode; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n", ++ __func__, shutter_speed, exposure_mode, metering_mode); ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, control, ++ MMAL_PARAMETER_SHUTTER_SPEED, ++ &shutter_speed, ++ sizeof(shutter_speed)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &exposure_mode, ++ sizeof(u32)); ++ dev->exposure_mode_active = exposure_mode; ++ ret += vchiq_mmal_port_parameter_set(dev->instance, control, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &exposure_mode, ++ sizeof(u32)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, control, ++ MMAL_PARAMETER_EXP_METERING_MODE, ++ &metering_mode, ++ sizeof(u32)); ++ ret += set_framerate_params(dev); ++ } ++ if (ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: Setting scene to %d, ret=%d\n", ++ __func__, ctrl->val, ret); ++ ret = -EINVAL; ++ } ++ return 0; ++} ++ ++static int bm2835_mmal_s_ctrl(struct v4l2_ctrl *ctrl) ++{ ++ struct bm2835_mmal_dev *dev = ++ container_of(ctrl->handler, struct bm2835_mmal_dev, ++ ctrl_handler); ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl = ctrl->priv; ++ int ret; ++ ++ if ((mmal_ctrl == NULL) || ++ (mmal_ctrl->id != ctrl->id) || ++ (mmal_ctrl->setter == NULL)) { ++ pr_warn("mmal_ctrl:%p ctrl id:%d\n", mmal_ctrl, ctrl->id); ++ return -EINVAL; ++ } ++ ++ ret = mmal_ctrl->setter(dev, ctrl, mmal_ctrl); ++ if (ret) ++ pr_warn("ctrl id:%d/MMAL param %08X- returned ret %d\n", ++ ctrl->id, mmal_ctrl->mmal_id, ret); ++ if (mmal_ctrl->ignore_errors) ++ ret = 0; ++ return ret; ++} ++ ++static const struct v4l2_ctrl_ops bm2835_mmal_ctrl_ops = { ++ .s_ctrl = bm2835_mmal_s_ctrl, ++}; ++ ++ ++ ++static const struct bm2835_mmal_v4l2_ctrl v4l2_ctrls[V4L2_CTRL_COUNT] = { ++ { ++ V4L2_CID_SATURATION, MMAL_CONTROL_TYPE_STD, ++ -100, 100, 0, 1, NULL, ++ MMAL_PARAMETER_SATURATION, ++ &ctrl_set_rational, ++ false ++ }, ++ { ++ V4L2_CID_SHARPNESS, MMAL_CONTROL_TYPE_STD, ++ -100, 100, 0, 1, NULL, ++ MMAL_PARAMETER_SHARPNESS, ++ &ctrl_set_rational, ++ false ++ }, ++ { ++ V4L2_CID_CONTRAST, MMAL_CONTROL_TYPE_STD, ++ -100, 100, 0, 1, NULL, ++ MMAL_PARAMETER_CONTRAST, ++ &ctrl_set_rational, ++ false ++ }, ++ { ++ V4L2_CID_BRIGHTNESS, MMAL_CONTROL_TYPE_STD, ++ 0, 100, 50, 1, NULL, ++ MMAL_PARAMETER_BRIGHTNESS, ++ &ctrl_set_rational, ++ false ++ }, ++ { ++ V4L2_CID_ISO_SENSITIVITY, MMAL_CONTROL_TYPE_INT_MENU, ++ 0, ARRAY_SIZE(iso_qmenu) - 1, 0, 1, iso_qmenu, ++ MMAL_PARAMETER_ISO, ++ &ctrl_set_value_menu, ++ false ++ }, ++ { ++ V4L2_CID_IMAGE_STABILIZATION, MMAL_CONTROL_TYPE_STD, ++ 0, 1, 0, 1, NULL, ++ MMAL_PARAMETER_VIDEO_STABILISATION, ++ &ctrl_set_value, ++ false ++ }, ++/* { ++ 0, MMAL_CONTROL_TYPE_CLUSTER, 3, 1, 0, NULL, 0, NULL ++ }, */ ++ { ++ V4L2_CID_EXPOSURE_AUTO, MMAL_CONTROL_TYPE_STD_MENU, ++ ~0x03, 3, V4L2_EXPOSURE_AUTO, 0, NULL, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &ctrl_set_exposure, ++ false ++ }, ++/* todo this needs mixing in with set exposure ++ { ++ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU, ++ }, ++ */ ++ { ++ V4L2_CID_EXPOSURE_ABSOLUTE, MMAL_CONTROL_TYPE_STD, ++ /* Units of 100usecs */ ++ 1, 1*1000*10, 100*10, 1, NULL, ++ MMAL_PARAMETER_SHUTTER_SPEED, ++ &ctrl_set_exposure, ++ false ++ }, ++ { ++ V4L2_CID_AUTO_EXPOSURE_BIAS, MMAL_CONTROL_TYPE_INT_MENU, ++ 0, ARRAY_SIZE(ev_bias_qmenu) - 1, ++ (ARRAY_SIZE(ev_bias_qmenu)+1)/2 - 1, 0, ev_bias_qmenu, ++ MMAL_PARAMETER_EXPOSURE_COMP, ++ &ctrl_set_value_ev, ++ false ++ }, ++ { ++ V4L2_CID_EXPOSURE_AUTO_PRIORITY, MMAL_CONTROL_TYPE_STD, ++ 0, 1, ++ 0, 1, NULL, ++ 0, /* Dummy MMAL ID as it gets mapped into FPS range*/ ++ &ctrl_set_exposure, ++ false ++ }, ++ { ++ V4L2_CID_EXPOSURE_METERING, ++ MMAL_CONTROL_TYPE_STD_MENU, ++ ~0x7, 2, V4L2_EXPOSURE_METERING_AVERAGE, 0, NULL, ++ MMAL_PARAMETER_EXP_METERING_MODE, ++ &ctrl_set_metering_mode, ++ false ++ }, ++ { ++ V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, ++ MMAL_CONTROL_TYPE_STD_MENU, ++ ~0x3ff, 9, V4L2_WHITE_BALANCE_AUTO, 0, NULL, ++ MMAL_PARAMETER_AWB_MODE, ++ &ctrl_set_awb_mode, ++ false ++ }, ++ { ++ V4L2_CID_RED_BALANCE, MMAL_CONTROL_TYPE_STD, ++ 1, 7999, 1000, 1, NULL, ++ MMAL_PARAMETER_CUSTOM_AWB_GAINS, ++ &ctrl_set_awb_gains, ++ false ++ }, ++ { ++ V4L2_CID_BLUE_BALANCE, MMAL_CONTROL_TYPE_STD, ++ 1, 7999, 1000, 1, NULL, ++ MMAL_PARAMETER_CUSTOM_AWB_GAINS, ++ &ctrl_set_awb_gains, ++ false ++ }, ++ { ++ V4L2_CID_COLORFX, MMAL_CONTROL_TYPE_STD_MENU, ++ 0, 15, V4L2_COLORFX_NONE, 0, NULL, ++ MMAL_PARAMETER_IMAGE_EFFECT, ++ &ctrl_set_image_effect, ++ false ++ }, ++ { ++ V4L2_CID_COLORFX_CBCR, MMAL_CONTROL_TYPE_STD, ++ 0, 0xffff, 0x8080, 1, NULL, ++ MMAL_PARAMETER_COLOUR_EFFECT, ++ &ctrl_set_colfx, ++ false ++ }, ++ { ++ V4L2_CID_ROTATE, MMAL_CONTROL_TYPE_STD, ++ 0, 360, 0, 90, NULL, ++ MMAL_PARAMETER_ROTATION, ++ &ctrl_set_rotate, ++ false ++ }, ++ { ++ V4L2_CID_HFLIP, MMAL_CONTROL_TYPE_STD, ++ 0, 1, 0, 1, NULL, ++ MMAL_PARAMETER_MIRROR, ++ &ctrl_set_flip, ++ false ++ }, ++ { ++ V4L2_CID_VFLIP, MMAL_CONTROL_TYPE_STD, ++ 0, 1, 0, 1, NULL, ++ MMAL_PARAMETER_MIRROR, ++ &ctrl_set_flip, ++ false ++ }, ++ { ++ V4L2_CID_MPEG_VIDEO_BITRATE_MODE, MMAL_CONTROL_TYPE_STD_MENU, ++ 0, ARRAY_SIZE(bitrate_mode_qmenu) - 1, ++ 0, 0, bitrate_mode_qmenu, ++ MMAL_PARAMETER_RATECONTROL, ++ &ctrl_set_bitrate_mode, ++ false ++ }, ++ { ++ V4L2_CID_MPEG_VIDEO_BITRATE, MMAL_CONTROL_TYPE_STD, ++ 25*1000, 25*1000*1000, 10*1000*1000, 25*1000, NULL, ++ MMAL_PARAMETER_VIDEO_BIT_RATE, ++ &ctrl_set_bitrate, ++ false ++ }, ++ { ++ V4L2_CID_JPEG_COMPRESSION_QUALITY, MMAL_CONTROL_TYPE_STD, ++ 1, 100, ++ 30, 1, NULL, ++ MMAL_PARAMETER_JPEG_Q_FACTOR, ++ &ctrl_set_image_encode_output, ++ false ++ }, ++ { ++ V4L2_CID_POWER_LINE_FREQUENCY, MMAL_CONTROL_TYPE_STD_MENU, ++ 0, ARRAY_SIZE(mains_freq_qmenu) - 1, ++ 1, 1, NULL, ++ MMAL_PARAMETER_FLICKER_AVOID, ++ &ctrl_set_flicker_avoidance, ++ false ++ }, ++ { ++ V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER, MMAL_CONTROL_TYPE_STD, ++ 0, 1, ++ 0, 1, NULL, ++ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER, ++ &ctrl_set_video_encode_param_output, ++ true /* Errors ignored as requires latest firmware to work */ ++ }, ++ { ++ V4L2_CID_MPEG_VIDEO_H264_PROFILE, ++ MMAL_CONTROL_TYPE_STD_MENU, ++ ~((1<ctrls[c]) && (v4l2_ctrls[c].setter)) { ++ ret = v4l2_ctrls[c].setter(dev, dev->ctrls[c], ++ &v4l2_ctrls[c]); ++ if (!v4l2_ctrls[c].ignore_errors && ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Failed when setting default values for ctrl %d\n", ++ c); ++ break; ++ } ++ } ++ } ++ return ret; ++} ++ ++int set_framerate_params(struct bm2835_mmal_dev *dev) ++{ ++ struct mmal_parameter_fps_range fps_range; ++ int ret; ++ ++ if ((dev->exposure_mode_active != MMAL_PARAM_EXPOSUREMODE_OFF) && ++ (dev->exp_auto_priority)) { ++ /* Variable FPS. Define min FPS as 1fps. ++ * Max as max defined FPS. ++ */ ++ fps_range.fps_low.num = 1; ++ fps_range.fps_low.den = 1; ++ fps_range.fps_high.num = dev->capture.timeperframe.denominator; ++ fps_range.fps_high.den = dev->capture.timeperframe.numerator; ++ } else { ++ /* Fixed FPS - set min and max to be the same */ ++ fps_range.fps_low.num = fps_range.fps_high.num = ++ dev->capture.timeperframe.denominator; ++ fps_range.fps_low.den = fps_range.fps_high.den = ++ dev->capture.timeperframe.numerator; ++ } ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Set fps range to %d/%d to %d/%d\n", ++ fps_range.fps_low.num, ++ fps_range.fps_low.den, ++ fps_range.fps_high.num, ++ fps_range.fps_high.den ++ ); ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW], ++ MMAL_PARAMETER_FPS_RANGE, ++ &fps_range, sizeof(fps_range)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO], ++ MMAL_PARAMETER_FPS_RANGE, ++ &fps_range, sizeof(fps_range)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE], ++ MMAL_PARAMETER_FPS_RANGE, ++ &fps_range, sizeof(fps_range)); ++ if (ret) ++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Failed to set fps ret %d\n", ++ ret); ++ ++ return ret; ++ ++} ++ ++int bm2835_mmal_init_controls(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl_handler *hdl) ++{ ++ int c; ++ const struct bm2835_mmal_v4l2_ctrl *ctrl; ++ ++ v4l2_ctrl_handler_init(hdl, V4L2_CTRL_COUNT); ++ ++ for (c = 0; c < V4L2_CTRL_COUNT; c++) { ++ ctrl = &v4l2_ctrls[c]; ++ ++ switch (ctrl->type) { ++ case MMAL_CONTROL_TYPE_STD: ++ dev->ctrls[c] = v4l2_ctrl_new_std(hdl, ++ &bm2835_mmal_ctrl_ops, ctrl->id, ++ ctrl->min, ctrl->max, ctrl->step, ctrl->def); ++ break; ++ ++ case MMAL_CONTROL_TYPE_STD_MENU: ++ { ++ int mask = ctrl->min; ++ ++ if (ctrl->id == V4L2_CID_SCENE_MODE) { ++ /* Special handling to work out the mask ++ * value based on the scene_configs array ++ * at runtime. Reduces the chance of ++ * mismatches. ++ */ ++ int i; ++ mask = 1<ctrls[c] = v4l2_ctrl_new_std_menu(hdl, ++ &bm2835_mmal_ctrl_ops, ctrl->id, ++ ctrl->max, mask, ctrl->def); ++ break; ++ } ++ ++ case MMAL_CONTROL_TYPE_INT_MENU: ++ dev->ctrls[c] = v4l2_ctrl_new_int_menu(hdl, ++ &bm2835_mmal_ctrl_ops, ctrl->id, ++ ctrl->max, ctrl->def, ctrl->imenu); ++ break; ++ ++ case MMAL_CONTROL_TYPE_CLUSTER: ++ /* skip this entry when constructing controls */ ++ continue; ++ } ++ ++ if (hdl->error) ++ break; ++ ++ dev->ctrls[c]->priv = (void *)ctrl; ++ } ++ ++ if (hdl->error) { ++ pr_err("error adding control %d/%d id 0x%x\n", c, ++ V4L2_CTRL_COUNT, ctrl->id); ++ return hdl->error; ++ } ++ ++ for (c = 0; c < V4L2_CTRL_COUNT; c++) { ++ ctrl = &v4l2_ctrls[c]; ++ ++ switch (ctrl->type) { ++ case MMAL_CONTROL_TYPE_CLUSTER: ++ v4l2_ctrl_auto_cluster(ctrl->min, ++ &dev->ctrls[c+1], ++ ctrl->max, ++ ctrl->def); ++ break; ++ ++ case MMAL_CONTROL_TYPE_STD: ++ case MMAL_CONTROL_TYPE_STD_MENU: ++ case MMAL_CONTROL_TYPE_INT_MENU: ++ break; ++ } ++ ++ } ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-common.h +@@ -0,0 +1,52 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ * ++ * MMAL structures ++ * ++ */ ++ ++#define MMAL_FOURCC(a, b, c, d) ((a) | (b << 8) | (c << 16) | (d << 24)) ++#define MMAL_MAGIC MMAL_FOURCC('m', 'm', 'a', 'l') ++ ++/** Special value signalling that time is not known */ ++#define MMAL_TIME_UNKNOWN (1LL<<63) ++ ++/* mapping between v4l and mmal video modes */ ++struct mmal_fmt { ++ char *name; ++ u32 fourcc; /* v4l2 format id */ ++ int flags; /* v4l2 flags field */ ++ u32 mmal; ++ int depth; ++ u32 mmal_component; /* MMAL component index to be used to encode */ ++}; ++ ++/* buffer for one video frame */ ++struct mmal_buffer { ++ /* v4l buffer data -- must be first */ ++ struct vb2_buffer vb; ++ ++ /* list of buffers available */ ++ struct list_head list; ++ ++ void *buffer; /* buffer pointer */ ++ unsigned long buffer_size; /* size of allocated buffer */ ++}; ++ ++/* */ ++struct mmal_colourfx { ++ s32 enable; ++ u32 u; ++ u32 v; ++}; +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-encodings.h +@@ -0,0 +1,127 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++#ifndef MMAL_ENCODINGS_H ++#define MMAL_ENCODINGS_H ++ ++#define MMAL_ENCODING_H264 MMAL_FOURCC('H', '2', '6', '4') ++#define MMAL_ENCODING_H263 MMAL_FOURCC('H', '2', '6', '3') ++#define MMAL_ENCODING_MP4V MMAL_FOURCC('M', 'P', '4', 'V') ++#define MMAL_ENCODING_MP2V MMAL_FOURCC('M', 'P', '2', 'V') ++#define MMAL_ENCODING_MP1V MMAL_FOURCC('M', 'P', '1', 'V') ++#define MMAL_ENCODING_WMV3 MMAL_FOURCC('W', 'M', 'V', '3') ++#define MMAL_ENCODING_WMV2 MMAL_FOURCC('W', 'M', 'V', '2') ++#define MMAL_ENCODING_WMV1 MMAL_FOURCC('W', 'M', 'V', '1') ++#define MMAL_ENCODING_WVC1 MMAL_FOURCC('W', 'V', 'C', '1') ++#define MMAL_ENCODING_VP8 MMAL_FOURCC('V', 'P', '8', ' ') ++#define MMAL_ENCODING_VP7 MMAL_FOURCC('V', 'P', '7', ' ') ++#define MMAL_ENCODING_VP6 MMAL_FOURCC('V', 'P', '6', ' ') ++#define MMAL_ENCODING_THEORA MMAL_FOURCC('T', 'H', 'E', 'O') ++#define MMAL_ENCODING_SPARK MMAL_FOURCC('S', 'P', 'R', 'K') ++#define MMAL_ENCODING_MJPEG MMAL_FOURCC('M', 'J', 'P', 'G') ++ ++#define MMAL_ENCODING_JPEG MMAL_FOURCC('J', 'P', 'E', 'G') ++#define MMAL_ENCODING_GIF MMAL_FOURCC('G', 'I', 'F', ' ') ++#define MMAL_ENCODING_PNG MMAL_FOURCC('P', 'N', 'G', ' ') ++#define MMAL_ENCODING_PPM MMAL_FOURCC('P', 'P', 'M', ' ') ++#define MMAL_ENCODING_TGA MMAL_FOURCC('T', 'G', 'A', ' ') ++#define MMAL_ENCODING_BMP MMAL_FOURCC('B', 'M', 'P', ' ') ++ ++#define MMAL_ENCODING_I420 MMAL_FOURCC('I', '4', '2', '0') ++#define MMAL_ENCODING_I420_SLICE MMAL_FOURCC('S', '4', '2', '0') ++#define MMAL_ENCODING_YV12 MMAL_FOURCC('Y', 'V', '1', '2') ++#define MMAL_ENCODING_I422 MMAL_FOURCC('I', '4', '2', '2') ++#define MMAL_ENCODING_I422_SLICE MMAL_FOURCC('S', '4', '2', '2') ++#define MMAL_ENCODING_YUYV MMAL_FOURCC('Y', 'U', 'Y', 'V') ++#define MMAL_ENCODING_YVYU MMAL_FOURCC('Y', 'V', 'Y', 'U') ++#define MMAL_ENCODING_UYVY MMAL_FOURCC('U', 'Y', 'V', 'Y') ++#define MMAL_ENCODING_VYUY MMAL_FOURCC('V', 'Y', 'U', 'Y') ++#define MMAL_ENCODING_NV12 MMAL_FOURCC('N', 'V', '1', '2') ++#define MMAL_ENCODING_NV21 MMAL_FOURCC('N', 'V', '2', '1') ++#define MMAL_ENCODING_ARGB MMAL_FOURCC('A', 'R', 'G', 'B') ++#define MMAL_ENCODING_RGBA MMAL_FOURCC('R', 'G', 'B', 'A') ++#define MMAL_ENCODING_ABGR MMAL_FOURCC('A', 'B', 'G', 'R') ++#define MMAL_ENCODING_BGRA MMAL_FOURCC('B', 'G', 'R', 'A') ++#define MMAL_ENCODING_RGB16 MMAL_FOURCC('R', 'G', 'B', '2') ++#define MMAL_ENCODING_RGB24 MMAL_FOURCC('R', 'G', 'B', '3') ++#define MMAL_ENCODING_RGB32 MMAL_FOURCC('R', 'G', 'B', '4') ++#define MMAL_ENCODING_BGR16 MMAL_FOURCC('B', 'G', 'R', '2') ++#define MMAL_ENCODING_BGR24 MMAL_FOURCC('B', 'G', 'R', '3') ++#define MMAL_ENCODING_BGR32 MMAL_FOURCC('B', 'G', 'R', '4') ++ ++/** SAND Video (YUVUV128) format, native format understood by VideoCore. ++ * This format is *not* opaque - if requested you will receive full frames ++ * of YUV_UV video. ++ */ ++#define MMAL_ENCODING_YUVUV128 MMAL_FOURCC('S', 'A', 'N', 'D') ++ ++/** VideoCore opaque image format, image handles are returned to ++ * the host but not the actual image data. ++ */ ++#define MMAL_ENCODING_OPAQUE MMAL_FOURCC('O', 'P', 'Q', 'V') ++ ++/** An EGL image handle ++ */ ++#define MMAL_ENCODING_EGL_IMAGE MMAL_FOURCC('E', 'G', 'L', 'I') ++ ++/* }@ */ ++ ++/** \name Pre-defined audio encodings */ ++/* @{ */ ++#define MMAL_ENCODING_PCM_UNSIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'U') ++#define MMAL_ENCODING_PCM_UNSIGNED_LE MMAL_FOURCC('p', 'c', 'm', 'u') ++#define MMAL_ENCODING_PCM_SIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'S') ++#define MMAL_ENCODING_PCM_SIGNED_LE MMAL_FOURCC('p', 'c', 'm', 's') ++#define MMAL_ENCODING_PCM_FLOAT_BE MMAL_FOURCC('P', 'C', 'M', 'F') ++#define MMAL_ENCODING_PCM_FLOAT_LE MMAL_FOURCC('p', 'c', 'm', 'f') ++ ++/* Pre-defined H264 encoding variants */ ++ ++/** ISO 14496-10 Annex B byte stream format */ ++#define MMAL_ENCODING_VARIANT_H264_DEFAULT 0 ++/** ISO 14496-15 AVC stream format */ ++#define MMAL_ENCODING_VARIANT_H264_AVC1 MMAL_FOURCC('A', 'V', 'C', '1') ++/** Implicitly delineated NAL units without emulation prevention */ ++#define MMAL_ENCODING_VARIANT_H264_RAW MMAL_FOURCC('R', 'A', 'W', ' ') ++ ++ ++/** \defgroup MmalColorSpace List of pre-defined video color spaces ++ * This defines a list of common color spaces. This list isn't exhaustive and ++ * is only provided as a convenience to avoid clients having to use FourCC ++ * codes directly. However components are allowed to define and use their own ++ * FourCC codes. ++ */ ++/* @{ */ ++ ++/** Unknown color space */ ++#define MMAL_COLOR_SPACE_UNKNOWN 0 ++/** ITU-R BT.601-5 [SDTV] */ ++#define MMAL_COLOR_SPACE_ITUR_BT601 MMAL_FOURCC('Y', '6', '0', '1') ++/** ITU-R BT.709-3 [HDTV] */ ++#define MMAL_COLOR_SPACE_ITUR_BT709 MMAL_FOURCC('Y', '7', '0', '9') ++/** JPEG JFIF */ ++#define MMAL_COLOR_SPACE_JPEG_JFIF MMAL_FOURCC('Y', 'J', 'F', 'I') ++/** Title 47 Code of Federal Regulations (2003) 73.682 (a) (20) */ ++#define MMAL_COLOR_SPACE_FCC MMAL_FOURCC('Y', 'F', 'C', 'C') ++/** Society of Motion Picture and Television Engineers 240M (1999) */ ++#define MMAL_COLOR_SPACE_SMPTE240M MMAL_FOURCC('Y', '2', '4', '0') ++/** ITU-R BT.470-2 System M */ ++#define MMAL_COLOR_SPACE_BT470_2_M MMAL_FOURCC('Y', '_', '_', 'M') ++/** ITU-R BT.470-2 System BG */ ++#define MMAL_COLOR_SPACE_BT470_2_BG MMAL_FOURCC('Y', '_', 'B', 'G') ++/** JPEG JFIF, but with 16..255 luma */ ++#define MMAL_COLOR_SPACE_JFIF_Y16_255 MMAL_FOURCC('Y', 'Y', '1', '6') ++/* @} MmalColorSpace List */ ++ ++#endif /* MMAL_ENCODINGS_H */ +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-msg-common.h +@@ -0,0 +1,50 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++#ifndef MMAL_MSG_COMMON_H ++#define MMAL_MSG_COMMON_H ++ ++enum mmal_msg_status { ++ MMAL_MSG_STATUS_SUCCESS = 0, /**< Success */ ++ MMAL_MSG_STATUS_ENOMEM, /**< Out of memory */ ++ MMAL_MSG_STATUS_ENOSPC, /**< Out of resources other than memory */ ++ MMAL_MSG_STATUS_EINVAL, /**< Argument is invalid */ ++ MMAL_MSG_STATUS_ENOSYS, /**< Function not implemented */ ++ MMAL_MSG_STATUS_ENOENT, /**< No such file or directory */ ++ MMAL_MSG_STATUS_ENXIO, /**< No such device or address */ ++ MMAL_MSG_STATUS_EIO, /**< I/O error */ ++ MMAL_MSG_STATUS_ESPIPE, /**< Illegal seek */ ++ MMAL_MSG_STATUS_ECORRUPT, /**< Data is corrupt \attention */ ++ MMAL_MSG_STATUS_ENOTREADY, /**< Component is not ready */ ++ MMAL_MSG_STATUS_ECONFIG, /**< Component is not configured */ ++ MMAL_MSG_STATUS_EISCONN, /**< Port is already connected */ ++ MMAL_MSG_STATUS_ENOTCONN, /**< Port is disconnected */ ++ MMAL_MSG_STATUS_EAGAIN, /**< Resource temporarily unavailable. */ ++ MMAL_MSG_STATUS_EFAULT, /**< Bad address */ ++}; ++ ++struct mmal_rect { ++ s32 x; /**< x coordinate (from left) */ ++ s32 y; /**< y coordinate (from top) */ ++ s32 width; /**< width */ ++ s32 height; /**< height */ ++}; ++ ++struct mmal_rational { ++ s32 num; /**< Numerator */ ++ s32 den; /**< Denominator */ ++}; ++ ++#endif /* MMAL_MSG_COMMON_H */ +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-msg-format.h +@@ -0,0 +1,81 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++#ifndef MMAL_MSG_FORMAT_H ++#define MMAL_MSG_FORMAT_H ++ ++#include "mmal-msg-common.h" ++ ++/* MMAL_ES_FORMAT_T */ ++ ++ ++struct mmal_audio_format { ++ u32 channels; /**< Number of audio channels */ ++ u32 sample_rate; /**< Sample rate */ ++ ++ u32 bits_per_sample; /**< Bits per sample */ ++ u32 block_align; /**< Size of a block of data */ ++}; ++ ++struct mmal_video_format { ++ u32 width; /**< Width of frame in pixels */ ++ u32 height; /**< Height of frame in rows of pixels */ ++ struct mmal_rect crop; /**< Visible region of the frame */ ++ struct mmal_rational frame_rate; /**< Frame rate */ ++ struct mmal_rational par; /**< Pixel aspect ratio */ ++ ++ /* FourCC specifying the color space of the video stream. See the ++ * \ref MmalColorSpace "pre-defined color spaces" for some examples. ++ */ ++ u32 color_space; ++}; ++ ++struct mmal_subpicture_format { ++ u32 x_offset; ++ u32 y_offset; ++}; ++ ++union mmal_es_specific_format { ++ struct mmal_audio_format audio; ++ struct mmal_video_format video; ++ struct mmal_subpicture_format subpicture; ++}; ++ ++/** Definition of an elementary stream format (MMAL_ES_FORMAT_T) */ ++struct mmal_es_format { ++ u32 type; /* enum mmal_es_type */ ++ ++ u32 encoding; /* FourCC specifying encoding of the elementary stream.*/ ++ u32 encoding_variant; /* FourCC specifying the specific ++ * encoding variant of the elementary ++ * stream. ++ */ ++ ++ union mmal_es_specific_format *es; /* TODO: pointers in ++ * message serialisation?!? ++ */ ++ /* Type specific ++ * information for the ++ * elementary stream ++ */ ++ ++ u32 bitrate; /**< Bitrate in bits per second */ ++ u32 flags; /**< Flags describing properties of the elementary stream. */ ++ ++ u32 extradata_size; /**< Size of the codec specific data */ ++ u8 *extradata; /**< Codec specific data */ ++}; ++ ++#endif /* MMAL_MSG_FORMAT_H */ +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-msg-port.h +@@ -0,0 +1,107 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++/* MMAL_PORT_TYPE_T */ ++enum mmal_port_type { ++ MMAL_PORT_TYPE_UNKNOWN = 0, /**< Unknown port type */ ++ MMAL_PORT_TYPE_CONTROL, /**< Control port */ ++ MMAL_PORT_TYPE_INPUT, /**< Input port */ ++ MMAL_PORT_TYPE_OUTPUT, /**< Output port */ ++ MMAL_PORT_TYPE_CLOCK, /**< Clock port */ ++}; ++ ++/** The port is pass-through and doesn't need buffer headers allocated */ ++#define MMAL_PORT_CAPABILITY_PASSTHROUGH 0x01 ++/** The port wants to allocate the buffer payloads. ++ * This signals a preference that payload allocation should be done ++ * on this port for efficiency reasons. */ ++#define MMAL_PORT_CAPABILITY_ALLOCATION 0x02 ++/** The port supports format change events. ++ * This applies to input ports and is used to let the client know ++ * whether the port supports being reconfigured via a format ++ * change event (i.e. without having to disable the port). */ ++#define MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE 0x04 ++ ++/* mmal port structure (MMAL_PORT_T) ++ * ++ * most elements are informational only, the pointer values for ++ * interogation messages are generally provided as additional ++ * strucures within the message. When used to set values only teh ++ * buffer_num, buffer_size and userdata parameters are writable. ++ */ ++struct mmal_port { ++ void *priv; /* Private member used by the framework */ ++ const char *name; /* Port name. Used for debugging purposes (RO) */ ++ ++ u32 type; /* Type of the port (RO) enum mmal_port_type */ ++ u16 index; /* Index of the port in its type list (RO) */ ++ u16 index_all; /* Index of the port in the list of all ports (RO) */ ++ ++ u32 is_enabled; /* Indicates whether the port is enabled or not (RO) */ ++ struct mmal_es_format *format; /* Format of the elementary stream */ ++ ++ u32 buffer_num_min; /* Minimum number of buffers the port ++ * requires (RO). This is set by the ++ * component. ++ */ ++ ++ u32 buffer_size_min; /* Minimum size of buffers the port ++ * requires (RO). This is set by the ++ * component. ++ */ ++ ++ u32 buffer_alignment_min; /* Minimum alignment requirement for ++ * the buffers (RO). A value of ++ * zero means no special alignment ++ * requirements. This is set by the ++ * component. ++ */ ++ ++ u32 buffer_num_recommended; /* Number of buffers the port ++ * recommends for optimal ++ * performance (RO). A value of ++ * zero means no special ++ * recommendation. This is set ++ * by the component. ++ */ ++ ++ u32 buffer_size_recommended; /* Size of buffers the port ++ * recommends for optimal ++ * performance (RO). A value of ++ * zero means no special ++ * recommendation. This is set ++ * by the component. ++ */ ++ ++ u32 buffer_num; /* Actual number of buffers the port will use. ++ * This is set by the client. ++ */ ++ ++ u32 buffer_size; /* Actual maximum size of the buffers that ++ * will be sent to the port. This is set by ++ * the client. ++ */ ++ ++ void *component; /* Component this port belongs to (Read Only) */ ++ ++ void *userdata; /* Field reserved for use by the client */ ++ ++ u32 capabilities; /* Flags describing the capabilities of a ++ * port (RO). Bitwise combination of \ref ++ * portcapabilities "Port capabilities" ++ * values. ++ */ ++ ++}; +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-msg.h +@@ -0,0 +1,404 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++/* all the data structures which serialise the MMAL protocol. note ++ * these are directly mapped onto the recived message data. ++ * ++ * BEWARE: They seem to *assume* pointers are u32 and that there is no ++ * structure padding! ++ * ++ * NOTE: this implementation uses kernel types to ensure sizes. Rather ++ * than assigning values to enums to force their size the ++ * implementation uses fixed size types and not the enums (though the ++ * comments have the actual enum type ++ */ ++ ++#define VC_MMAL_VER 15 ++#define VC_MMAL_MIN_VER 10 ++#define VC_MMAL_SERVER_NAME MAKE_FOURCC("mmal") ++ ++/* max total message size is 512 bytes */ ++#define MMAL_MSG_MAX_SIZE 512 ++/* with six 32bit header elements max payload is therefore 488 bytes */ ++#define MMAL_MSG_MAX_PAYLOAD 488 ++ ++#include "mmal-msg-common.h" ++#include "mmal-msg-format.h" ++#include "mmal-msg-port.h" ++ ++enum mmal_msg_type { ++ MMAL_MSG_TYPE_QUIT = 1, ++ MMAL_MSG_TYPE_SERVICE_CLOSED, ++ MMAL_MSG_TYPE_GET_VERSION, ++ MMAL_MSG_TYPE_COMPONENT_CREATE, ++ MMAL_MSG_TYPE_COMPONENT_DESTROY, /* 5 */ ++ MMAL_MSG_TYPE_COMPONENT_ENABLE, ++ MMAL_MSG_TYPE_COMPONENT_DISABLE, ++ MMAL_MSG_TYPE_PORT_INFO_GET, ++ MMAL_MSG_TYPE_PORT_INFO_SET, ++ MMAL_MSG_TYPE_PORT_ACTION, /* 10 */ ++ MMAL_MSG_TYPE_BUFFER_FROM_HOST, ++ MMAL_MSG_TYPE_BUFFER_TO_HOST, ++ MMAL_MSG_TYPE_GET_STATS, ++ MMAL_MSG_TYPE_PORT_PARAMETER_SET, ++ MMAL_MSG_TYPE_PORT_PARAMETER_GET, /* 15 */ ++ MMAL_MSG_TYPE_EVENT_TO_HOST, ++ MMAL_MSG_TYPE_GET_CORE_STATS_FOR_PORT, ++ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR, ++ MMAL_MSG_TYPE_CONSUME_MEM, ++ MMAL_MSG_TYPE_LMK, /* 20 */ ++ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR_DESC, ++ MMAL_MSG_TYPE_DRM_GET_LHS32, ++ MMAL_MSG_TYPE_DRM_GET_TIME, ++ MMAL_MSG_TYPE_BUFFER_FROM_HOST_ZEROLEN, ++ MMAL_MSG_TYPE_PORT_FLUSH, /* 25 */ ++ MMAL_MSG_TYPE_HOST_LOG, ++ MMAL_MSG_TYPE_MSG_LAST ++}; ++ ++/* port action request messages differ depending on the action type */ ++enum mmal_msg_port_action_type { ++ MMAL_MSG_PORT_ACTION_TYPE_UNKNOWN = 0, /* Unkown action */ ++ MMAL_MSG_PORT_ACTION_TYPE_ENABLE, /* Enable a port */ ++ MMAL_MSG_PORT_ACTION_TYPE_DISABLE, /* Disable a port */ ++ MMAL_MSG_PORT_ACTION_TYPE_FLUSH, /* Flush a port */ ++ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, /* Connect ports */ ++ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, /* Disconnect ports */ ++ MMAL_MSG_PORT_ACTION_TYPE_SET_REQUIREMENTS, /* Set buffer requirements*/ ++}; ++ ++struct mmal_msg_header { ++ u32 magic; ++ u32 type; /** enum mmal_msg_type */ ++ ++ /* Opaque handle to the control service */ ++ struct mmal_control_service *control_service; ++ ++ struct mmal_msg_context *context; /** a u32 per message context */ ++ u32 status; /** The status of the vchiq operation */ ++ u32 padding; ++}; ++ ++/* Send from VC to host to report version */ ++struct mmal_msg_version { ++ u32 flags; ++ u32 major; ++ u32 minor; ++ u32 minimum; ++}; ++ ++/* request to VC to create component */ ++struct mmal_msg_component_create { ++ void *client_component; /* component context */ ++ char name[128]; ++ u32 pid; /* For debug */ ++}; ++ ++/* reply from VC to component creation request */ ++struct mmal_msg_component_create_reply { ++ u32 status; /** enum mmal_msg_status - how does this differ to ++ * the one in the header? ++ */ ++ u32 component_handle; /* VideoCore handle for component */ ++ u32 input_num; /* Number of input ports */ ++ u32 output_num; /* Number of output ports */ ++ u32 clock_num; /* Number of clock ports */ ++}; ++ ++/* request to VC to destroy a component */ ++struct mmal_msg_component_destroy { ++ u32 component_handle; ++}; ++ ++struct mmal_msg_component_destroy_reply { ++ u32 status; /** The component destruction status */ ++}; ++ ++ ++/* request and reply to VC to enable a component */ ++struct mmal_msg_component_enable { ++ u32 component_handle; ++}; ++ ++struct mmal_msg_component_enable_reply { ++ u32 status; /** The component enable status */ ++}; ++ ++ ++/* request and reply to VC to disable a component */ ++struct mmal_msg_component_disable { ++ u32 component_handle; ++}; ++ ++struct mmal_msg_component_disable_reply { ++ u32 status; /** The component disable status */ ++}; ++ ++/* request to VC to get port information */ ++struct mmal_msg_port_info_get { ++ u32 component_handle; /* component handle port is associated with */ ++ u32 port_type; /* enum mmal_msg_port_type */ ++ u32 index; /* port index to query */ ++}; ++ ++/* reply from VC to get port info request */ ++struct mmal_msg_port_info_get_reply { ++ u32 status; /** enum mmal_msg_status */ ++ u32 component_handle; /* component handle port is associated with */ ++ u32 port_type; /* enum mmal_msg_port_type */ ++ u32 port_index; /* port indexed in query */ ++ s32 found; /* unused */ ++ u32 port_handle; /**< Handle to use for this port */ ++ struct mmal_port port; ++ struct mmal_es_format format; /* elementry stream format */ ++ union mmal_es_specific_format es; /* es type specific data */ ++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; /* es extra data */ ++}; ++ ++/* request to VC to set port information */ ++struct mmal_msg_port_info_set { ++ u32 component_handle; ++ u32 port_type; /* enum mmal_msg_port_type */ ++ u32 port_index; /* port indexed in query */ ++ struct mmal_port port; ++ struct mmal_es_format format; ++ union mmal_es_specific_format es; ++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; ++}; ++ ++/* reply from VC to port info set request */ ++struct mmal_msg_port_info_set_reply { ++ u32 status; ++ u32 component_handle; /* component handle port is associated with */ ++ u32 port_type; /* enum mmal_msg_port_type */ ++ u32 index; /* port indexed in query */ ++ s32 found; /* unused */ ++ u32 port_handle; /**< Handle to use for this port */ ++ struct mmal_port port; ++ struct mmal_es_format format; ++ union mmal_es_specific_format es; ++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; ++}; ++ ++ ++/* port action requests that take a mmal_port as a parameter */ ++struct mmal_msg_port_action_port { ++ u32 component_handle; ++ u32 port_handle; ++ u32 action; /* enum mmal_msg_port_action_type */ ++ struct mmal_port port; ++}; ++ ++/* port action requests that take handles as a parameter */ ++struct mmal_msg_port_action_handle { ++ u32 component_handle; ++ u32 port_handle; ++ u32 action; /* enum mmal_msg_port_action_type */ ++ u32 connect_component_handle; ++ u32 connect_port_handle; ++}; ++ ++struct mmal_msg_port_action_reply { ++ u32 status; /** The port action operation status */ ++}; ++ ++ ++ ++ ++/* MMAL buffer transfer */ ++ ++/** Size of space reserved in a buffer message for short messages. */ ++#define MMAL_VC_SHORT_DATA 128 ++ ++/** Signals that the current payload is the end of the stream of data */ ++#define MMAL_BUFFER_HEADER_FLAG_EOS (1<<0) ++/** Signals that the start of the current payload starts a frame */ ++#define MMAL_BUFFER_HEADER_FLAG_FRAME_START (1<<1) ++/** Signals that the end of the current payload ends a frame */ ++#define MMAL_BUFFER_HEADER_FLAG_FRAME_END (1<<2) ++/** Signals that the current payload contains only complete frames (>1) */ ++#define MMAL_BUFFER_HEADER_FLAG_FRAME \ ++ (MMAL_BUFFER_HEADER_FLAG_FRAME_START|MMAL_BUFFER_HEADER_FLAG_FRAME_END) ++/** Signals that the current payload is a keyframe (i.e. self decodable) */ ++#define MMAL_BUFFER_HEADER_FLAG_KEYFRAME (1<<3) ++/** Signals a discontinuity in the stream of data (e.g. after a seek). ++ * Can be used for instance by a decoder to reset its state */ ++#define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY (1<<4) ++/** Signals a buffer containing some kind of config data for the component ++ * (e.g. codec config data) */ ++#define MMAL_BUFFER_HEADER_FLAG_CONFIG (1<<5) ++/** Signals an encrypted payload */ ++#define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED (1<<6) ++/** Signals a buffer containing side information */ ++#define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO (1<<7) ++/** Signals a buffer which is the snapshot/postview image from a stills ++ * capture ++ */ ++#define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT (1<<8) ++/** Signals a buffer which contains data known to be corrupted */ ++#define MMAL_BUFFER_HEADER_FLAG_CORRUPTED (1<<9) ++/** Signals that a buffer failed to be transmitted */ ++#define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED (1<<10) ++ ++struct mmal_driver_buffer { ++ u32 magic; ++ u32 component_handle; ++ u32 port_handle; ++ void *client_context; ++}; ++ ++/* buffer header */ ++struct mmal_buffer_header { ++ struct mmal_buffer_header *next; /* next header */ ++ void *priv; /* framework private data */ ++ u32 cmd; ++ void *data; ++ u32 alloc_size; ++ u32 length; ++ u32 offset; ++ u32 flags; ++ s64 pts; ++ s64 dts; ++ void *type; ++ void *user_data; ++}; ++ ++struct mmal_buffer_header_type_specific { ++ union { ++ struct { ++ u32 planes; ++ u32 offset[4]; ++ u32 pitch[4]; ++ u32 flags; ++ } video; ++ } u; ++}; ++ ++struct mmal_msg_buffer_from_host { ++ /* The front 32 bytes of the buffer header are copied ++ * back to us in the reply to allow for context. This ++ * area is used to store two mmal_driver_buffer structures to ++ * allow for multiple concurrent service users. ++ */ ++ /* control data */ ++ struct mmal_driver_buffer drvbuf; ++ ++ /* referenced control data for passthrough buffer management */ ++ struct mmal_driver_buffer drvbuf_ref; ++ struct mmal_buffer_header buffer_header; /* buffer header itself */ ++ struct mmal_buffer_header_type_specific buffer_header_type_specific; ++ s32 is_zero_copy; ++ s32 has_reference; ++ ++ /** allows short data to be xfered in control message */ ++ u32 payload_in_message; ++ u8 short_data[MMAL_VC_SHORT_DATA]; ++}; ++ ++ ++/* port parameter setting */ ++ ++#define MMAL_WORKER_PORT_PARAMETER_SPACE 96 ++ ++struct mmal_msg_port_parameter_set { ++ u32 component_handle; /* component */ ++ u32 port_handle; /* port */ ++ u32 id; /* Parameter ID */ ++ u32 size; /* Parameter size */ ++ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE]; ++}; ++ ++struct mmal_msg_port_parameter_set_reply { ++ u32 status; /** enum mmal_msg_status todo: how does this ++ * differ to the one in the header? ++ */ ++}; ++ ++/* port parameter getting */ ++ ++struct mmal_msg_port_parameter_get { ++ u32 component_handle; /* component */ ++ u32 port_handle; /* port */ ++ u32 id; /* Parameter ID */ ++ u32 size; /* Parameter size */ ++}; ++ ++struct mmal_msg_port_parameter_get_reply { ++ u32 status; /* Status of mmal_port_parameter_get call */ ++ u32 id; /* Parameter ID */ ++ u32 size; /* Parameter size */ ++ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE]; ++}; ++ ++/* event messages */ ++#define MMAL_WORKER_EVENT_SPACE 256 ++ ++struct mmal_msg_event_to_host { ++ void *client_component; /* component context */ ++ ++ u32 port_type; ++ u32 port_num; ++ ++ u32 cmd; ++ u32 length; ++ u8 data[MMAL_WORKER_EVENT_SPACE]; ++ struct mmal_buffer_header *delayed_buffer; ++}; ++ ++/* all mmal messages are serialised through this structure */ ++struct mmal_msg { ++ /* header */ ++ struct mmal_msg_header h; ++ /* payload */ ++ union { ++ struct mmal_msg_version version; ++ ++ struct mmal_msg_component_create component_create; ++ struct mmal_msg_component_create_reply component_create_reply; ++ ++ struct mmal_msg_component_destroy component_destroy; ++ struct mmal_msg_component_destroy_reply component_destroy_reply; ++ ++ struct mmal_msg_component_enable component_enable; ++ struct mmal_msg_component_enable_reply component_enable_reply; ++ ++ struct mmal_msg_component_disable component_disable; ++ struct mmal_msg_component_disable_reply component_disable_reply; ++ ++ struct mmal_msg_port_info_get port_info_get; ++ struct mmal_msg_port_info_get_reply port_info_get_reply; ++ ++ struct mmal_msg_port_info_set port_info_set; ++ struct mmal_msg_port_info_set_reply port_info_set_reply; ++ ++ struct mmal_msg_port_action_port port_action_port; ++ struct mmal_msg_port_action_handle port_action_handle; ++ struct mmal_msg_port_action_reply port_action_reply; ++ ++ struct mmal_msg_buffer_from_host buffer_from_host; ++ ++ struct mmal_msg_port_parameter_set port_parameter_set; ++ struct mmal_msg_port_parameter_set_reply ++ port_parameter_set_reply; ++ struct mmal_msg_port_parameter_get ++ port_parameter_get; ++ struct mmal_msg_port_parameter_get_reply ++ port_parameter_get_reply; ++ ++ struct mmal_msg_event_to_host event_to_host; ++ ++ u8 payload[MMAL_MSG_MAX_PAYLOAD]; ++ } u; ++}; +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-parameters.h +@@ -0,0 +1,656 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++/* common parameters */ ++ ++/** @name Parameter groups ++ * Parameters are divided into groups, and then allocated sequentially within ++ * a group using an enum. ++ * @{ ++ */ ++ ++/** Common parameter ID group, used with many types of component. */ ++#define MMAL_PARAMETER_GROUP_COMMON (0<<16) ++/** Camera-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_CAMERA (1<<16) ++/** Video-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_VIDEO (2<<16) ++/** Audio-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_AUDIO (3<<16) ++/** Clock-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_CLOCK (4<<16) ++/** Miracast-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_MIRACAST (5<<16) ++ ++/* Common parameters */ ++enum mmal_parameter_common_type { ++ MMAL_PARAMETER_UNUSED /**< Never a valid parameter ID */ ++ = MMAL_PARAMETER_GROUP_COMMON, ++ MMAL_PARAMETER_SUPPORTED_ENCODINGS, /**< MMAL_PARAMETER_ENCODING_T */ ++ MMAL_PARAMETER_URI, /**< MMAL_PARAMETER_URI_T */ ++ ++ /** MMAL_PARAMETER_CHANGE_EVENT_REQUEST_T */ ++ MMAL_PARAMETER_CHANGE_EVENT_REQUEST, ++ ++ /** MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_ZERO_COPY, ++ ++ /**< MMAL_PARAMETER_BUFFER_REQUIREMENTS_T */ ++ MMAL_PARAMETER_BUFFER_REQUIREMENTS, ++ ++ MMAL_PARAMETER_STATISTICS, /**< MMAL_PARAMETER_STATISTICS_T */ ++ MMAL_PARAMETER_CORE_STATISTICS, /**< MMAL_PARAMETER_CORE_STATISTICS_T */ ++ MMAL_PARAMETER_MEM_USAGE, /**< MMAL_PARAMETER_MEM_USAGE_T */ ++ MMAL_PARAMETER_BUFFER_FLAG_FILTER, /**< MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_SEEK, /**< MMAL_PARAMETER_SEEK_T */ ++ MMAL_PARAMETER_POWERMON_ENABLE, /**< MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_LOGGING, /**< MMAL_PARAMETER_LOGGING_T */ ++ MMAL_PARAMETER_SYSTEM_TIME, /**< MMAL_PARAMETER_UINT64_T */ ++ MMAL_PARAMETER_NO_IMAGE_PADDING /**< MMAL_PARAMETER_BOOLEAN_T */ ++}; ++ ++/* camera parameters */ ++ ++enum mmal_parameter_camera_type { ++ /* 0 */ ++ /** @ref MMAL_PARAMETER_THUMBNAIL_CONFIG_T */ ++ MMAL_PARAMETER_THUMBNAIL_CONFIGURATION ++ = MMAL_PARAMETER_GROUP_CAMERA, ++ MMAL_PARAMETER_CAPTURE_QUALITY, /**< Unused? */ ++ MMAL_PARAMETER_ROTATION, /**< @ref MMAL_PARAMETER_INT32_T */ ++ MMAL_PARAMETER_EXIF_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_EXIF, /**< @ref MMAL_PARAMETER_EXIF_T */ ++ MMAL_PARAMETER_AWB_MODE, /**< @ref MMAL_PARAM_AWBMODE_T */ ++ MMAL_PARAMETER_IMAGE_EFFECT, /**< @ref MMAL_PARAMETER_IMAGEFX_T */ ++ MMAL_PARAMETER_COLOUR_EFFECT, /**< @ref MMAL_PARAMETER_COLOURFX_T */ ++ MMAL_PARAMETER_FLICKER_AVOID, /**< @ref MMAL_PARAMETER_FLICKERAVOID_T */ ++ MMAL_PARAMETER_FLASH, /**< @ref MMAL_PARAMETER_FLASH_T */ ++ MMAL_PARAMETER_REDEYE, /**< @ref MMAL_PARAMETER_REDEYE_T */ ++ MMAL_PARAMETER_FOCUS, /**< @ref MMAL_PARAMETER_FOCUS_T */ ++ MMAL_PARAMETER_FOCAL_LENGTHS, /**< Unused? */ ++ MMAL_PARAMETER_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */ ++ MMAL_PARAMETER_ZOOM, /**< @ref MMAL_PARAMETER_SCALEFACTOR_T */ ++ MMAL_PARAMETER_MIRROR, /**< @ref MMAL_PARAMETER_MIRROR_T */ ++ ++ /* 0x10 */ ++ MMAL_PARAMETER_CAMERA_NUM, /**< @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_EXPOSURE_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMODE_T */ ++ MMAL_PARAMETER_EXP_METERING_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMETERINGMODE_T */ ++ MMAL_PARAMETER_FOCUS_STATUS, /**< @ref MMAL_PARAMETER_FOCUS_STATUS_T */ ++ MMAL_PARAMETER_CAMERA_CONFIG, /**< @ref MMAL_PARAMETER_CAMERA_CONFIG_T */ ++ MMAL_PARAMETER_CAPTURE_STATUS, /**< @ref MMAL_PARAMETER_CAPTURE_STATUS_T */ ++ MMAL_PARAMETER_FACE_TRACK, /**< @ref MMAL_PARAMETER_FACE_TRACK_T */ ++ MMAL_PARAMETER_DRAW_BOX_FACES_AND_FOCUS, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_JPEG_Q_FACTOR, /**< @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_FRAME_RATE, /**< @ref MMAL_PARAMETER_FRAME_RATE_T */ ++ MMAL_PARAMETER_USE_STC, /**< @ref MMAL_PARAMETER_CAMERA_STC_MODE_T */ ++ MMAL_PARAMETER_CAMERA_INFO, /**< @ref MMAL_PARAMETER_CAMERA_INFO_T */ ++ MMAL_PARAMETER_VIDEO_STABILISATION, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_FACE_TRACK_RESULTS, /**< @ref MMAL_PARAMETER_FACE_TRACK_RESULTS_T */ ++ MMAL_PARAMETER_ENABLE_RAW_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ ++ /* 0x20 */ ++ MMAL_PARAMETER_DPF_FILE, /**< @ref MMAL_PARAMETER_URI_T */ ++ MMAL_PARAMETER_ENABLE_DPF_FILE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_DPF_FAIL_IS_FATAL, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_CAPTURE_MODE, /**< @ref MMAL_PARAMETER_CAPTUREMODE_T */ ++ MMAL_PARAMETER_FOCUS_REGIONS, /**< @ref MMAL_PARAMETER_FOCUS_REGIONS_T */ ++ MMAL_PARAMETER_INPUT_CROP, /**< @ref MMAL_PARAMETER_INPUT_CROP_T */ ++ MMAL_PARAMETER_SENSOR_INFORMATION, /**< @ref MMAL_PARAMETER_SENSOR_INFORMATION_T */ ++ MMAL_PARAMETER_FLASH_SELECT, /**< @ref MMAL_PARAMETER_FLASH_SELECT_T */ ++ MMAL_PARAMETER_FIELD_OF_VIEW, /**< @ref MMAL_PARAMETER_FIELD_OF_VIEW_T */ ++ MMAL_PARAMETER_HIGH_DYNAMIC_RANGE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_DYNAMIC_RANGE_COMPRESSION, /**< @ref MMAL_PARAMETER_DRC_T */ ++ MMAL_PARAMETER_ALGORITHM_CONTROL, /**< @ref MMAL_PARAMETER_ALGORITHM_CONTROL_T */ ++ MMAL_PARAMETER_SHARPNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */ ++ MMAL_PARAMETER_CONTRAST, /**< @ref MMAL_PARAMETER_RATIONAL_T */ ++ MMAL_PARAMETER_BRIGHTNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */ ++ MMAL_PARAMETER_SATURATION, /**< @ref MMAL_PARAMETER_RATIONAL_T */ ++ ++ /* 0x30 */ ++ MMAL_PARAMETER_ISO, /**< @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_ANTISHAKE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ ++ /** @ref MMAL_PARAMETER_IMAGEFX_PARAMETERS_T */ ++ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_CAMERA_BURST_CAPTURE, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_CAMERA_MIN_ISO, ++ ++ /** @ref MMAL_PARAMETER_CAMERA_USE_CASE_T */ ++ MMAL_PARAMETER_CAMERA_USE_CASE, ++ ++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_CAPTURE_STATS_PASS, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_CAMERA_CUSTOM_SENSOR_CONFIG, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_ENABLE_REGISTER_FILE, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_REGISTER_FAIL_IS_FATAL, ++ ++ /** @ref MMAL_PARAMETER_CONFIGFILE_T */ ++ MMAL_PARAMETER_CONFIGFILE_REGISTERS, ++ ++ /** @ref MMAL_PARAMETER_CONFIGFILE_CHUNK_T */ ++ MMAL_PARAMETER_CONFIGFILE_CHUNK_REGISTERS, ++ MMAL_PARAMETER_JPEG_ATTACH_LOG, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_ZERO_SHUTTER_LAG, /**< @ref MMAL_PARAMETER_ZEROSHUTTERLAG_T */ ++ MMAL_PARAMETER_FPS_RANGE, /**< @ref MMAL_PARAMETER_FPS_RANGE_T */ ++ MMAL_PARAMETER_CAPTURE_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */ ++ ++ /* 0x40 */ ++ MMAL_PARAMETER_SW_SHARPEN_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_FLASH_REQUIRED, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_SW_SATURATION_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_SHUTTER_SPEED, /**< Takes a @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_CUSTOM_AWB_GAINS, /**< Takes a @ref MMAL_PARAMETER_AWB_GAINS_T */ ++}; ++ ++struct mmal_parameter_rational { ++ s32 num; /**< Numerator */ ++ s32 den; /**< Denominator */ ++}; ++ ++enum mmal_parameter_camera_config_timestamp_mode { ++ MMAL_PARAM_TIMESTAMP_MODE_ZERO = 0, /* Always timestamp frames as 0 */ ++ MMAL_PARAM_TIMESTAMP_MODE_RAW_STC, /* Use the raw STC value ++ * for the frame timestamp ++ */ ++ MMAL_PARAM_TIMESTAMP_MODE_RESET_STC, /* Use the STC timestamp ++ * but subtract the ++ * timestamp of the first ++ * frame sent to give a ++ * zero based timestamp. ++ */ ++}; ++ ++struct mmal_parameter_fps_range { ++ /**< Low end of the permitted framerate range */ ++ struct mmal_parameter_rational fps_low; ++ /**< High end of the permitted framerate range */ ++ struct mmal_parameter_rational fps_high; ++}; ++ ++ ++/* camera configuration parameter */ ++struct mmal_parameter_camera_config { ++ /* Parameters for setting up the image pools */ ++ u32 max_stills_w; /* Max size of stills capture */ ++ u32 max_stills_h; ++ u32 stills_yuv422; /* Allow YUV422 stills capture */ ++ u32 one_shot_stills; /* Continuous or one shot stills captures. */ ++ ++ u32 max_preview_video_w; /* Max size of the preview or video ++ * capture frames ++ */ ++ u32 max_preview_video_h; ++ u32 num_preview_video_frames; ++ ++ /** Sets the height of the circular buffer for stills capture. */ ++ u32 stills_capture_circular_buffer_height; ++ ++ /** Allows preview/encode to resume as fast as possible after the stills ++ * input frame has been received, and then processes the still frame in ++ * the background whilst preview/encode has resumed. ++ * Actual mode is controlled by MMAL_PARAMETER_CAPTURE_MODE. ++ */ ++ u32 fast_preview_resume; ++ ++ /** Selects algorithm for timestamping frames if ++ * there is no clock component connected. ++ * enum mmal_parameter_camera_config_timestamp_mode ++ */ ++ s32 use_stc_timestamp; ++}; ++ ++ ++enum mmal_parameter_exposuremode { ++ MMAL_PARAM_EXPOSUREMODE_OFF, ++ MMAL_PARAM_EXPOSUREMODE_AUTO, ++ MMAL_PARAM_EXPOSUREMODE_NIGHT, ++ MMAL_PARAM_EXPOSUREMODE_NIGHTPREVIEW, ++ MMAL_PARAM_EXPOSUREMODE_BACKLIGHT, ++ MMAL_PARAM_EXPOSUREMODE_SPOTLIGHT, ++ MMAL_PARAM_EXPOSUREMODE_SPORTS, ++ MMAL_PARAM_EXPOSUREMODE_SNOW, ++ MMAL_PARAM_EXPOSUREMODE_BEACH, ++ MMAL_PARAM_EXPOSUREMODE_VERYLONG, ++ MMAL_PARAM_EXPOSUREMODE_FIXEDFPS, ++ MMAL_PARAM_EXPOSUREMODE_ANTISHAKE, ++ MMAL_PARAM_EXPOSUREMODE_FIREWORKS, ++}; ++ ++enum mmal_parameter_exposuremeteringmode { ++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX, ++}; ++ ++enum mmal_parameter_awbmode { ++ MMAL_PARAM_AWBMODE_OFF, ++ MMAL_PARAM_AWBMODE_AUTO, ++ MMAL_PARAM_AWBMODE_SUNLIGHT, ++ MMAL_PARAM_AWBMODE_CLOUDY, ++ MMAL_PARAM_AWBMODE_SHADE, ++ MMAL_PARAM_AWBMODE_TUNGSTEN, ++ MMAL_PARAM_AWBMODE_FLUORESCENT, ++ MMAL_PARAM_AWBMODE_INCANDESCENT, ++ MMAL_PARAM_AWBMODE_FLASH, ++ MMAL_PARAM_AWBMODE_HORIZON, ++}; ++ ++enum mmal_parameter_imagefx { ++ MMAL_PARAM_IMAGEFX_NONE, ++ MMAL_PARAM_IMAGEFX_NEGATIVE, ++ MMAL_PARAM_IMAGEFX_SOLARIZE, ++ MMAL_PARAM_IMAGEFX_POSTERIZE, ++ MMAL_PARAM_IMAGEFX_WHITEBOARD, ++ MMAL_PARAM_IMAGEFX_BLACKBOARD, ++ MMAL_PARAM_IMAGEFX_SKETCH, ++ MMAL_PARAM_IMAGEFX_DENOISE, ++ MMAL_PARAM_IMAGEFX_EMBOSS, ++ MMAL_PARAM_IMAGEFX_OILPAINT, ++ MMAL_PARAM_IMAGEFX_HATCH, ++ MMAL_PARAM_IMAGEFX_GPEN, ++ MMAL_PARAM_IMAGEFX_PASTEL, ++ MMAL_PARAM_IMAGEFX_WATERCOLOUR, ++ MMAL_PARAM_IMAGEFX_FILM, ++ MMAL_PARAM_IMAGEFX_BLUR, ++ MMAL_PARAM_IMAGEFX_SATURATION, ++ MMAL_PARAM_IMAGEFX_COLOURSWAP, ++ MMAL_PARAM_IMAGEFX_WASHEDOUT, ++ MMAL_PARAM_IMAGEFX_POSTERISE, ++ MMAL_PARAM_IMAGEFX_COLOURPOINT, ++ MMAL_PARAM_IMAGEFX_COLOURBALANCE, ++ MMAL_PARAM_IMAGEFX_CARTOON, ++}; ++ ++enum MMAL_PARAM_FLICKERAVOID_T { ++ MMAL_PARAM_FLICKERAVOID_OFF, ++ MMAL_PARAM_FLICKERAVOID_AUTO, ++ MMAL_PARAM_FLICKERAVOID_50HZ, ++ MMAL_PARAM_FLICKERAVOID_60HZ, ++ MMAL_PARAM_FLICKERAVOID_MAX = 0x7FFFFFFF ++}; ++ ++struct mmal_parameter_awbgains { ++ struct mmal_parameter_rational r_gain; /**< Red gain */ ++ struct mmal_parameter_rational b_gain; /**< Blue gain */ ++}; ++ ++/** Manner of video rate control */ ++enum mmal_parameter_rate_control_mode { ++ MMAL_VIDEO_RATECONTROL_DEFAULT, ++ MMAL_VIDEO_RATECONTROL_VARIABLE, ++ MMAL_VIDEO_RATECONTROL_CONSTANT, ++ MMAL_VIDEO_RATECONTROL_VARIABLE_SKIP_FRAMES, ++ MMAL_VIDEO_RATECONTROL_CONSTANT_SKIP_FRAMES ++}; ++ ++enum mmal_video_profile { ++ MMAL_VIDEO_PROFILE_H263_BASELINE, ++ MMAL_VIDEO_PROFILE_H263_H320CODING, ++ MMAL_VIDEO_PROFILE_H263_BACKWARDCOMPATIBLE, ++ MMAL_VIDEO_PROFILE_H263_ISWV2, ++ MMAL_VIDEO_PROFILE_H263_ISWV3, ++ MMAL_VIDEO_PROFILE_H263_HIGHCOMPRESSION, ++ MMAL_VIDEO_PROFILE_H263_INTERNET, ++ MMAL_VIDEO_PROFILE_H263_INTERLACE, ++ MMAL_VIDEO_PROFILE_H263_HIGHLATENCY, ++ MMAL_VIDEO_PROFILE_MP4V_SIMPLE, ++ MMAL_VIDEO_PROFILE_MP4V_SIMPLESCALABLE, ++ MMAL_VIDEO_PROFILE_MP4V_CORE, ++ MMAL_VIDEO_PROFILE_MP4V_MAIN, ++ MMAL_VIDEO_PROFILE_MP4V_NBIT, ++ MMAL_VIDEO_PROFILE_MP4V_SCALABLETEXTURE, ++ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFACE, ++ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFBA, ++ MMAL_VIDEO_PROFILE_MP4V_BASICANIMATED, ++ MMAL_VIDEO_PROFILE_MP4V_HYBRID, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDREALTIME, ++ MMAL_VIDEO_PROFILE_MP4V_CORESCALABLE, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCODING, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCORE, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSCALABLE, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSIMPLE, ++ MMAL_VIDEO_PROFILE_H264_BASELINE, ++ MMAL_VIDEO_PROFILE_H264_MAIN, ++ MMAL_VIDEO_PROFILE_H264_EXTENDED, ++ MMAL_VIDEO_PROFILE_H264_HIGH, ++ MMAL_VIDEO_PROFILE_H264_HIGH10, ++ MMAL_VIDEO_PROFILE_H264_HIGH422, ++ MMAL_VIDEO_PROFILE_H264_HIGH444, ++ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE, ++ MMAL_VIDEO_PROFILE_DUMMY = 0x7FFFFFFF ++}; ++ ++enum mmal_video_level { ++ MMAL_VIDEO_LEVEL_H263_10, ++ MMAL_VIDEO_LEVEL_H263_20, ++ MMAL_VIDEO_LEVEL_H263_30, ++ MMAL_VIDEO_LEVEL_H263_40, ++ MMAL_VIDEO_LEVEL_H263_45, ++ MMAL_VIDEO_LEVEL_H263_50, ++ MMAL_VIDEO_LEVEL_H263_60, ++ MMAL_VIDEO_LEVEL_H263_70, ++ MMAL_VIDEO_LEVEL_MP4V_0, ++ MMAL_VIDEO_LEVEL_MP4V_0b, ++ MMAL_VIDEO_LEVEL_MP4V_1, ++ MMAL_VIDEO_LEVEL_MP4V_2, ++ MMAL_VIDEO_LEVEL_MP4V_3, ++ MMAL_VIDEO_LEVEL_MP4V_4, ++ MMAL_VIDEO_LEVEL_MP4V_4a, ++ MMAL_VIDEO_LEVEL_MP4V_5, ++ MMAL_VIDEO_LEVEL_MP4V_6, ++ MMAL_VIDEO_LEVEL_H264_1, ++ MMAL_VIDEO_LEVEL_H264_1b, ++ MMAL_VIDEO_LEVEL_H264_11, ++ MMAL_VIDEO_LEVEL_H264_12, ++ MMAL_VIDEO_LEVEL_H264_13, ++ MMAL_VIDEO_LEVEL_H264_2, ++ MMAL_VIDEO_LEVEL_H264_21, ++ MMAL_VIDEO_LEVEL_H264_22, ++ MMAL_VIDEO_LEVEL_H264_3, ++ MMAL_VIDEO_LEVEL_H264_31, ++ MMAL_VIDEO_LEVEL_H264_32, ++ MMAL_VIDEO_LEVEL_H264_4, ++ MMAL_VIDEO_LEVEL_H264_41, ++ MMAL_VIDEO_LEVEL_H264_42, ++ MMAL_VIDEO_LEVEL_H264_5, ++ MMAL_VIDEO_LEVEL_H264_51, ++ MMAL_VIDEO_LEVEL_DUMMY = 0x7FFFFFFF ++}; ++ ++struct mmal_parameter_video_profile { ++ enum mmal_video_profile profile; ++ enum mmal_video_level level; ++}; ++ ++/* video parameters */ ++ ++enum mmal_parameter_video_type { ++ /** @ref MMAL_DISPLAYREGION_T */ ++ MMAL_PARAMETER_DISPLAYREGION = MMAL_PARAMETER_GROUP_VIDEO, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */ ++ MMAL_PARAMETER_SUPPORTED_PROFILES, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */ ++ MMAL_PARAMETER_PROFILE, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_INTRAPERIOD, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_RATECONTROL_T */ ++ MMAL_PARAMETER_RATECONTROL, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_NALUNITFORMAT_T */ ++ MMAL_PARAMETER_NALUNITFORMAT, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_MINIMISE_FRAGMENTATION, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. ++ * Setting the value to zero resets to the default (one slice per frame). ++ */ ++ MMAL_PARAMETER_MB_ROWS_PER_SLICE, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION_T */ ++ MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_EEDE_ENABLE_T */ ++ MMAL_PARAMETER_VIDEO_EEDE_ENABLE, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE_T */ ++ MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. Request an I-frame. */ ++ MMAL_PARAMETER_VIDEO_REQUEST_I_FRAME, ++ /** @ref MMAL_PARAMETER_VIDEO_INTRA_REFRESH_T */ ++ MMAL_PARAMETER_VIDEO_INTRA_REFRESH, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. Run-time bit rate control */ ++ MMAL_PARAMETER_VIDEO_BIT_RATE, ++ ++ /** @ref MMAL_PARAMETER_FRAME_RATE_T */ ++ MMAL_PARAMETER_VIDEO_FRAME_RATE, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_MIN_QUANT, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_MAX_QUANT, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL, ++ ++ MMAL_PARAMETER_EXTRA_BUFFERS, /**< @ref MMAL_PARAMETER_UINT32_T. */ ++ /** @ref MMAL_PARAMETER_UINT32_T. ++ * Changing this parameter from the default can reduce frame rate ++ * because image buffers need to be re-pitched. ++ */ ++ MMAL_PARAMETER_VIDEO_ALIGN_HORIZ, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. ++ * Changing this parameter from the default can reduce frame rate ++ * because image buffers need to be re-pitched. ++ */ ++ MMAL_PARAMETER_VIDEO_ALIGN_VERT, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_DROPPABLE_PFRAMES, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_INITIAL_QUANT, ++ ++ /**< @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_QP_P, ++ ++ /**< @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_RC_SLICE_DQUANT, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_FRAME_LIMIT_BITS, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_PEAK_RATE, ++ ++ /* H264 specific parameters */ ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_DISABLE_CABAC, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_LATENCY, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_AU_DELIMITERS, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_DEBLOCK_IDC, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_ENCODER_H264_MB_INTRA_MODES_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_MB_INTRA_MODE, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_HEADER_ON_OPEN, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_PRECODE_FOR_QP, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_DRM_INIT_INFO_T. */ ++ MMAL_PARAMETER_VIDEO_DRM_INIT_INFO, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_TIMESTAMP_FIFO, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_DECODE_ERROR_CONCEALMENT, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER_T. */ ++ MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER, ++ ++ /** @ref MMAL_PARAMETER_BYTES_T */ ++ MMAL_PARAMETER_VIDEO_DECODE_CONFIG_VD3, ++ ++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_VCL_HRD_PARAMETERS, ++ ++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_DELAY_HRD_FLAG, ++ ++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER ++}; ++ ++/** Valid mirror modes */ ++enum mmal_parameter_mirror { ++ MMAL_PARAM_MIRROR_NONE, ++ MMAL_PARAM_MIRROR_VERTICAL, ++ MMAL_PARAM_MIRROR_HORIZONTAL, ++ MMAL_PARAM_MIRROR_BOTH, ++}; ++ ++enum mmal_parameter_displaytransform { ++ MMAL_DISPLAY_ROT0 = 0, ++ MMAL_DISPLAY_MIRROR_ROT0 = 1, ++ MMAL_DISPLAY_MIRROR_ROT180 = 2, ++ MMAL_DISPLAY_ROT180 = 3, ++ MMAL_DISPLAY_MIRROR_ROT90 = 4, ++ MMAL_DISPLAY_ROT270 = 5, ++ MMAL_DISPLAY_ROT90 = 6, ++ MMAL_DISPLAY_MIRROR_ROT270 = 7, ++}; ++ ++enum mmal_parameter_displaymode { ++ MMAL_DISPLAY_MODE_FILL = 0, ++ MMAL_DISPLAY_MODE_LETTERBOX = 1, ++}; ++ ++enum mmal_parameter_displayset { ++ MMAL_DISPLAY_SET_NONE = 0, ++ MMAL_DISPLAY_SET_NUM = 1, ++ MMAL_DISPLAY_SET_FULLSCREEN = 2, ++ MMAL_DISPLAY_SET_TRANSFORM = 4, ++ MMAL_DISPLAY_SET_DEST_RECT = 8, ++ MMAL_DISPLAY_SET_SRC_RECT = 0x10, ++ MMAL_DISPLAY_SET_MODE = 0x20, ++ MMAL_DISPLAY_SET_PIXEL = 0x40, ++ MMAL_DISPLAY_SET_NOASPECT = 0x80, ++ MMAL_DISPLAY_SET_LAYER = 0x100, ++ MMAL_DISPLAY_SET_COPYPROTECT = 0x200, ++ MMAL_DISPLAY_SET_ALPHA = 0x400, ++}; ++ ++struct mmal_parameter_displayregion { ++ /** Bitfield that indicates which fields are set and should be ++ * used. All other fields will maintain their current value. ++ * \ref MMAL_DISPLAYSET_T defines the bits that can be ++ * combined. ++ */ ++ u32 set; ++ ++ /** Describes the display output device, with 0 typically ++ * being a directly connected LCD display. The actual values ++ * will depend on the hardware. Code using hard-wired numbers ++ * (e.g. 2) is certain to fail. ++ */ ++ ++ u32 display_num; ++ /** Indicates that we are using the full device screen area, ++ * rather than a window of the display. If zero, then ++ * dest_rect is used to specify a region of the display to ++ * use. ++ */ ++ ++ s32 fullscreen; ++ /** Indicates any rotation or flipping used to map frames onto ++ * the natural display orientation. ++ */ ++ u32 transform; /* enum mmal_parameter_displaytransform */ ++ ++ /** Where to display the frame within the screen, if ++ * fullscreen is zero. ++ */ ++ struct vchiq_mmal_rect dest_rect; ++ ++ /** Indicates which area of the frame to display. If all ++ * values are zero, the whole frame will be used. ++ */ ++ struct vchiq_mmal_rect src_rect; ++ ++ /** If set to non-zero, indicates that any display scaling ++ * should disregard the aspect ratio of the frame region being ++ * displayed. ++ */ ++ s32 noaspect; ++ ++ /** Indicates how the image should be scaled to fit the ++ * display. \code MMAL_DISPLAY_MODE_FILL \endcode indicates ++ * that the image should fill the screen by potentially ++ * cropping the frames. Setting \code mode \endcode to \code ++ * MMAL_DISPLAY_MODE_LETTERBOX \endcode indicates that all the ++ * source region should be displayed and black bars added if ++ * necessary. ++ */ ++ u32 mode; /* enum mmal_parameter_displaymode */ ++ ++ /** If non-zero, defines the width of a source pixel relative ++ * to \code pixel_y \endcode. If zero, then pixels default to ++ * being square. ++ */ ++ u32 pixel_x; ++ ++ /** If non-zero, defines the height of a source pixel relative ++ * to \code pixel_x \endcode. If zero, then pixels default to ++ * being square. ++ */ ++ u32 pixel_y; ++ ++ /** Sets the relative depth of the images, with greater values ++ * being in front of smaller values. ++ */ ++ u32 layer; ++ ++ /** Set to non-zero to ensure copy protection is used on ++ * output. ++ */ ++ s32 copyprotect_required; ++ ++ /** Level of opacity of the layer, where zero is fully ++ * transparent and 255 is fully opaque. ++ */ ++ u32 alpha; ++}; ++ ++#define MMAL_MAX_IMAGEFX_PARAMETERS 5 ++ ++struct mmal_parameter_imagefx_parameters { ++ enum mmal_parameter_imagefx effect; ++ u32 num_effect_params; ++ u32 effect_parameter[MMAL_MAX_IMAGEFX_PARAMETERS]; ++}; +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-vchiq.c +@@ -0,0 +1,1916 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ * ++ * V4L2 driver MMAL vchiq interface code ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mmal-common.h" ++#include "mmal-vchiq.h" ++#include "mmal-msg.h" ++ ++#define USE_VCHIQ_ARM ++#include "interface/vchi/vchi.h" ++ ++/* maximum number of components supported */ ++#define VCHIQ_MMAL_MAX_COMPONENTS 4 ++ ++/*#define FULL_MSG_DUMP 1*/ ++ ++#ifdef DEBUG ++static const char *const msg_type_names[] = { ++ "UNKNOWN", ++ "QUIT", ++ "SERVICE_CLOSED", ++ "GET_VERSION", ++ "COMPONENT_CREATE", ++ "COMPONENT_DESTROY", ++ "COMPONENT_ENABLE", ++ "COMPONENT_DISABLE", ++ "PORT_INFO_GET", ++ "PORT_INFO_SET", ++ "PORT_ACTION", ++ "BUFFER_FROM_HOST", ++ "BUFFER_TO_HOST", ++ "GET_STATS", ++ "PORT_PARAMETER_SET", ++ "PORT_PARAMETER_GET", ++ "EVENT_TO_HOST", ++ "GET_CORE_STATS_FOR_PORT", ++ "OPAQUE_ALLOCATOR", ++ "CONSUME_MEM", ++ "LMK", ++ "OPAQUE_ALLOCATOR_DESC", ++ "DRM_GET_LHS32", ++ "DRM_GET_TIME", ++ "BUFFER_FROM_HOST_ZEROLEN", ++ "PORT_FLUSH", ++ "HOST_LOG", ++}; ++#endif ++ ++static const char *const port_action_type_names[] = { ++ "UNKNOWN", ++ "ENABLE", ++ "DISABLE", ++ "FLUSH", ++ "CONNECT", ++ "DISCONNECT", ++ "SET_REQUIREMENTS", ++}; ++ ++#if defined(DEBUG) ++#if defined(FULL_MSG_DUMP) ++#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \ ++ do { \ ++ pr_debug(TITLE" type:%s(%d) length:%d\n", \ ++ msg_type_names[(MSG)->h.type], \ ++ (MSG)->h.type, (MSG_LEN)); \ ++ print_hex_dump(KERN_DEBUG, "<h.type], \ ++ (MSG)->h.type, (MSG_LEN)); \ ++ } ++#endif ++#else ++#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) ++#endif ++ ++/* normal message context */ ++struct mmal_msg_context { ++ union { ++ struct { ++ /* work struct for defered callback - must come first */ ++ struct work_struct work; ++ /* mmal instance */ ++ struct vchiq_mmal_instance *instance; ++ /* mmal port */ ++ struct vchiq_mmal_port *port; ++ /* actual buffer used to store bulk reply */ ++ struct mmal_buffer *buffer; ++ /* amount of buffer used */ ++ unsigned long buffer_used; ++ /* MMAL buffer flags */ ++ u32 mmal_flags; ++ /* Presentation and Decode timestamps */ ++ s64 pts; ++ s64 dts; ++ ++ int status; /* context status */ ++ ++ } bulk; /* bulk data */ ++ ++ struct { ++ /* message handle to release */ ++ VCHI_HELD_MSG_T msg_handle; ++ /* pointer to received message */ ++ struct mmal_msg *msg; ++ /* received message length */ ++ u32 msg_len; ++ /* completion upon reply */ ++ struct completion cmplt; ++ } sync; /* synchronous response */ ++ } u; ++ ++}; ++ ++struct vchiq_mmal_instance { ++ VCHI_SERVICE_HANDLE_T handle; ++ ++ /* ensure serialised access to service */ ++ struct mutex vchiq_mutex; ++ ++ /* ensure serialised access to bulk operations */ ++ struct mutex bulk_mutex; ++ ++ /* vmalloc page to receive scratch bulk xfers into */ ++ void *bulk_scratch; ++ ++ /* component to use next */ ++ int component_idx; ++ struct vchiq_mmal_component component[VCHIQ_MMAL_MAX_COMPONENTS]; ++}; ++ ++static struct mmal_msg_context *get_msg_context(struct vchiq_mmal_instance ++ *instance) ++{ ++ struct mmal_msg_context *msg_context; ++ ++ /* todo: should this be allocated from a pool to avoid kmalloc */ ++ msg_context = kmalloc(sizeof(*msg_context), GFP_KERNEL); ++ memset(msg_context, 0, sizeof(*msg_context)); ++ ++ return msg_context; ++} ++ ++static void release_msg_context(struct mmal_msg_context *msg_context) ++{ ++ kfree(msg_context); ++} ++ ++/* deals with receipt of event to host message */ ++static void event_to_host_cb(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, u32 msg_len) ++{ ++ pr_debug("unhandled event\n"); ++ pr_debug("component:%p port type:%d num:%d cmd:0x%x length:%d\n", ++ msg->u.event_to_host.client_component, ++ msg->u.event_to_host.port_type, ++ msg->u.event_to_host.port_num, ++ msg->u.event_to_host.cmd, msg->u.event_to_host.length); ++} ++ ++/* workqueue scheduled callback ++ * ++ * we do this because it is important we do not call any other vchiq ++ * sync calls from witin the message delivery thread ++ */ ++static void buffer_work_cb(struct work_struct *work) ++{ ++ struct mmal_msg_context *msg_context = (struct mmal_msg_context *)work; ++ ++ msg_context->u.bulk.port->buffer_cb(msg_context->u.bulk.instance, ++ msg_context->u.bulk.port, ++ msg_context->u.bulk.status, ++ msg_context->u.bulk.buffer, ++ msg_context->u.bulk.buffer_used, ++ msg_context->u.bulk.mmal_flags, ++ msg_context->u.bulk.dts, ++ msg_context->u.bulk.pts); ++ ++ /* release message context */ ++ release_msg_context(msg_context); ++} ++ ++/* enqueue a bulk receive for a given message context */ ++static int bulk_receive(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, ++ struct mmal_msg_context *msg_context) ++{ ++ unsigned long rd_len; ++ unsigned long flags = 0; ++ int ret; ++ ++ /* bulk mutex stops other bulk operations while we have a ++ * receive in progress - released in callback ++ */ ++ ret = mutex_lock_interruptible(&instance->bulk_mutex); ++ if (ret != 0) ++ return ret; ++ ++ rd_len = msg->u.buffer_from_host.buffer_header.length; ++ ++ /* take buffer from queue */ ++ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags); ++ if (list_empty(&msg_context->u.bulk.port->buffers)) { ++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); ++ pr_err("buffer list empty trying to submit bulk receive\n"); ++ ++ /* todo: this is a serious error, we should never have ++ * commited a buffer_to_host operation to the mmal ++ * port without the buffer to back it up (underflow ++ * handling) and there is no obvious way to deal with ++ * this - how is the mmal servie going to react when ++ * we fail to do the xfer and reschedule a buffer when ++ * it arrives? perhaps a starved flag to indicate a ++ * waiting bulk receive? ++ */ ++ ++ mutex_unlock(&instance->bulk_mutex); ++ ++ return -EINVAL; ++ } ++ ++ msg_context->u.bulk.buffer = ++ list_entry(msg_context->u.bulk.port->buffers.next, ++ struct mmal_buffer, list); ++ list_del(&msg_context->u.bulk.buffer->list); ++ ++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); ++ ++ /* ensure we do not overrun the available buffer */ ++ if (rd_len > msg_context->u.bulk.buffer->buffer_size) { ++ rd_len = msg_context->u.bulk.buffer->buffer_size; ++ pr_warn("short read as not enough receive buffer space\n"); ++ /* todo: is this the correct response, what happens to ++ * the rest of the message data? ++ */ ++ } ++ ++ /* store length */ ++ msg_context->u.bulk.buffer_used = rd_len; ++ msg_context->u.bulk.mmal_flags = ++ msg->u.buffer_from_host.buffer_header.flags; ++ msg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts; ++ msg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts; ++ ++ // only need to flush L1 cache here, as VCHIQ takes care of the L2 ++ // cache. ++ __cpuc_flush_dcache_area(msg_context->u.bulk.buffer->buffer, rd_len); ++ ++ /* queue the bulk submission */ ++ vchi_service_use(instance->handle); ++ ret = vchi_bulk_queue_receive(instance->handle, ++ msg_context->u.bulk.buffer->buffer, ++ /* Actual receive needs to be a multiple ++ * of 4 bytes ++ */ ++ (rd_len + 3) & ~3, ++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, ++ msg_context); ++ ++ vchi_service_release(instance->handle); ++ ++ if (ret != 0) { ++ /* callback will not be clearing the mutex */ ++ mutex_unlock(&instance->bulk_mutex); ++ } ++ ++ return ret; ++} ++ ++/* enque a dummy bulk receive for a given message context */ ++static int dummy_bulk_receive(struct vchiq_mmal_instance *instance, ++ struct mmal_msg_context *msg_context) ++{ ++ int ret; ++ ++ /* bulk mutex stops other bulk operations while we have a ++ * receive in progress - released in callback ++ */ ++ ret = mutex_lock_interruptible(&instance->bulk_mutex); ++ if (ret != 0) ++ return ret; ++ ++ /* zero length indicates this was a dummy transfer */ ++ msg_context->u.bulk.buffer_used = 0; ++ ++ /* queue the bulk submission */ ++ vchi_service_use(instance->handle); ++ ++ ret = vchi_bulk_queue_receive(instance->handle, ++ instance->bulk_scratch, ++ 8, ++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, ++ msg_context); ++ ++ vchi_service_release(instance->handle); ++ ++ if (ret != 0) { ++ /* callback will not be clearing the mutex */ ++ mutex_unlock(&instance->bulk_mutex); ++ } ++ ++ return ret; ++} ++ ++/* data in message, memcpy from packet into output buffer */ ++static int inline_receive(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, ++ struct mmal_msg_context *msg_context) ++{ ++ unsigned long flags = 0; ++ ++ /* take buffer from queue */ ++ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags); ++ if (list_empty(&msg_context->u.bulk.port->buffers)) { ++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); ++ pr_err("buffer list empty trying to receive inline\n"); ++ ++ /* todo: this is a serious error, we should never have ++ * commited a buffer_to_host operation to the mmal ++ * port without the buffer to back it up (with ++ * underflow handling) and there is no obvious way to ++ * deal with this. Less bad than the bulk case as we ++ * can just drop this on the floor but...unhelpful ++ */ ++ return -EINVAL; ++ } ++ ++ msg_context->u.bulk.buffer = ++ list_entry(msg_context->u.bulk.port->buffers.next, ++ struct mmal_buffer, list); ++ list_del(&msg_context->u.bulk.buffer->list); ++ ++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); ++ ++ memcpy(msg_context->u.bulk.buffer->buffer, ++ msg->u.buffer_from_host.short_data, ++ msg->u.buffer_from_host.payload_in_message); ++ ++ msg_context->u.bulk.buffer_used = ++ msg->u.buffer_from_host.payload_in_message; ++ ++ return 0; ++} ++ ++/* queue the buffer availability with MMAL_MSG_TYPE_BUFFER_FROM_HOST */ ++static int ++buffer_from_host(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, struct mmal_buffer *buf) ++{ ++ struct mmal_msg_context *msg_context; ++ struct mmal_msg m; ++ int ret; ++ ++ pr_debug("instance:%p buffer:%p\n", instance->handle, buf); ++ ++ /* bulk mutex stops other bulk operations while we ++ * have a receive in progress ++ */ ++ if (mutex_lock_interruptible(&instance->bulk_mutex)) ++ return -EINTR; ++ ++ /* get context */ ++ msg_context = get_msg_context(instance); ++ if (msg_context == NULL) ++ return -ENOMEM; ++ ++ /* store bulk message context for when data arrives */ ++ msg_context->u.bulk.instance = instance; ++ msg_context->u.bulk.port = port; ++ msg_context->u.bulk.buffer = NULL; /* not valid until bulk xfer */ ++ msg_context->u.bulk.buffer_used = 0; ++ ++ /* initialise work structure ready to schedule callback */ ++ INIT_WORK(&msg_context->u.bulk.work, buffer_work_cb); ++ ++ /* prep the buffer from host message */ ++ memset(&m, 0xbc, sizeof(m)); /* just to make debug clearer */ ++ ++ m.h.type = MMAL_MSG_TYPE_BUFFER_FROM_HOST; ++ m.h.magic = MMAL_MAGIC; ++ m.h.context = msg_context; ++ m.h.status = 0; ++ ++ /* drvbuf is our private data passed back */ ++ m.u.buffer_from_host.drvbuf.magic = MMAL_MAGIC; ++ m.u.buffer_from_host.drvbuf.component_handle = port->component->handle; ++ m.u.buffer_from_host.drvbuf.port_handle = port->handle; ++ m.u.buffer_from_host.drvbuf.client_context = msg_context; ++ ++ /* buffer header */ ++ m.u.buffer_from_host.buffer_header.cmd = 0; ++ m.u.buffer_from_host.buffer_header.data = buf->buffer; ++ m.u.buffer_from_host.buffer_header.alloc_size = buf->buffer_size; ++ m.u.buffer_from_host.buffer_header.length = 0; /* nothing used yet */ ++ m.u.buffer_from_host.buffer_header.offset = 0; /* no offset */ ++ m.u.buffer_from_host.buffer_header.flags = 0; /* no flags */ ++ m.u.buffer_from_host.buffer_header.pts = MMAL_TIME_UNKNOWN; ++ m.u.buffer_from_host.buffer_header.dts = MMAL_TIME_UNKNOWN; ++ ++ /* clear buffer type sepecific data */ ++ memset(&m.u.buffer_from_host.buffer_header_type_specific, 0, ++ sizeof(m.u.buffer_from_host.buffer_header_type_specific)); ++ ++ /* no payload in message */ ++ m.u.buffer_from_host.payload_in_message = 0; ++ ++ vchi_service_use(instance->handle); ++ ++ ret = vchi_msg_queue(instance->handle, &m, ++ sizeof(struct mmal_msg_header) + ++ sizeof(m.u.buffer_from_host), ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (ret != 0) { ++ release_msg_context(msg_context); ++ /* todo: is this correct error value? */ ++ } ++ ++ vchi_service_release(instance->handle); ++ ++ mutex_unlock(&instance->bulk_mutex); ++ ++ return ret; ++} ++ ++/* submit a buffer to the mmal sevice ++ * ++ * the buffer_from_host uses size data from the ports next available ++ * mmal_buffer and deals with there being no buffer available by ++ * incrementing the underflow for later ++ */ ++static int port_buffer_from_host(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ struct mmal_buffer *buf; ++ unsigned long flags = 0; ++ ++ if (!port->enabled) ++ return -EINVAL; ++ ++ /* peek buffer from queue */ ++ spin_lock_irqsave(&port->slock, flags); ++ if (list_empty(&port->buffers)) { ++ port->buffer_underflow++; ++ spin_unlock_irqrestore(&port->slock, flags); ++ return -ENOSPC; ++ } ++ ++ buf = list_entry(port->buffers.next, struct mmal_buffer, list); ++ ++ spin_unlock_irqrestore(&port->slock, flags); ++ ++ /* issue buffer to mmal service */ ++ ret = buffer_from_host(instance, port, buf); ++ if (ret) { ++ pr_err("adding buffer header failed\n"); ++ /* todo: how should this be dealt with */ ++ } ++ ++ return ret; ++} ++ ++/* deals with receipt of buffer to host message */ ++static void buffer_to_host_cb(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, u32 msg_len) ++{ ++ struct mmal_msg_context *msg_context; ++ ++ pr_debug("buffer_to_host_cb: instance:%p msg:%p msg_len:%d\n", ++ instance, msg, msg_len); ++ ++ if (msg->u.buffer_from_host.drvbuf.magic == MMAL_MAGIC) { ++ msg_context = msg->u.buffer_from_host.drvbuf.client_context; ++ } else { ++ pr_err("MMAL_MSG_TYPE_BUFFER_TO_HOST with bad magic\n"); ++ return; ++ } ++ ++ if (msg->h.status != MMAL_MSG_STATUS_SUCCESS) { ++ /* message reception had an error */ ++ pr_warn("error %d in reply\n", msg->h.status); ++ ++ msg_context->u.bulk.status = msg->h.status; ++ ++ } else if (msg->u.buffer_from_host.buffer_header.length == 0) { ++ /* empty buffer */ ++ if (msg->u.buffer_from_host.buffer_header.flags & ++ MMAL_BUFFER_HEADER_FLAG_EOS) { ++ msg_context->u.bulk.status = ++ dummy_bulk_receive(instance, msg_context); ++ if (msg_context->u.bulk.status == 0) ++ return; /* successful bulk submission, bulk ++ * completion will trigger callback ++ */ ++ } else { ++ /* do callback with empty buffer - not EOS though */ ++ msg_context->u.bulk.status = 0; ++ msg_context->u.bulk.buffer_used = 0; ++ } ++ } else if (msg->u.buffer_from_host.payload_in_message == 0) { ++ /* data is not in message, queue a bulk receive */ ++ msg_context->u.bulk.status = ++ bulk_receive(instance, msg, msg_context); ++ if (msg_context->u.bulk.status == 0) ++ return; /* successful bulk submission, bulk ++ * completion will trigger callback ++ */ ++ ++ /* failed to submit buffer, this will end badly */ ++ pr_err("error %d on bulk submission\n", ++ msg_context->u.bulk.status); ++ ++ } else if (msg->u.buffer_from_host.payload_in_message <= ++ MMAL_VC_SHORT_DATA) { ++ /* data payload within message */ ++ msg_context->u.bulk.status = inline_receive(instance, msg, ++ msg_context); ++ } else { ++ pr_err("message with invalid short payload\n"); ++ ++ /* signal error */ ++ msg_context->u.bulk.status = -EINVAL; ++ msg_context->u.bulk.buffer_used = ++ msg->u.buffer_from_host.payload_in_message; ++ } ++ ++ /* replace the buffer header */ ++ port_buffer_from_host(instance, msg_context->u.bulk.port); ++ ++ /* schedule the port callback */ ++ schedule_work(&msg_context->u.bulk.work); ++} ++ ++static void bulk_receive_cb(struct vchiq_mmal_instance *instance, ++ struct mmal_msg_context *msg_context) ++{ ++ /* bulk receive operation complete */ ++ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex); ++ ++ /* replace the buffer header */ ++ port_buffer_from_host(msg_context->u.bulk.instance, ++ msg_context->u.bulk.port); ++ ++ msg_context->u.bulk.status = 0; ++ ++ /* schedule the port callback */ ++ schedule_work(&msg_context->u.bulk.work); ++} ++ ++static void bulk_abort_cb(struct vchiq_mmal_instance *instance, ++ struct mmal_msg_context *msg_context) ++{ ++ pr_err("%s: bulk ABORTED msg_context:%p\n", __func__, msg_context); ++ ++ /* bulk receive operation complete */ ++ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex); ++ ++ /* replace the buffer header */ ++ port_buffer_from_host(msg_context->u.bulk.instance, ++ msg_context->u.bulk.port); ++ ++ msg_context->u.bulk.status = -EINTR; ++ ++ schedule_work(&msg_context->u.bulk.work); ++} ++ ++/* incoming event service callback */ ++static void service_callback(void *param, ++ const VCHI_CALLBACK_REASON_T reason, ++ void *bulk_ctx) ++{ ++ struct vchiq_mmal_instance *instance = param; ++ int status; ++ u32 msg_len; ++ struct mmal_msg *msg; ++ VCHI_HELD_MSG_T msg_handle; ++ ++ if (!instance) { ++ pr_err("Message callback passed NULL instance\n"); ++ return; ++ } ++ ++ switch (reason) { ++ case VCHI_CALLBACK_MSG_AVAILABLE: ++ status = vchi_msg_hold(instance->handle, (void **)&msg, ++ &msg_len, VCHI_FLAGS_NONE, &msg_handle); ++ if (status) { ++ pr_err("Unable to dequeue a message (%d)\n", status); ++ break; ++ } ++ ++ DBG_DUMP_MSG(msg, msg_len, "<<< reply message"); ++ ++ /* handling is different for buffer messages */ ++ switch (msg->h.type) { ++ ++ case MMAL_MSG_TYPE_BUFFER_FROM_HOST: ++ vchi_held_msg_release(&msg_handle); ++ break; ++ ++ case MMAL_MSG_TYPE_EVENT_TO_HOST: ++ event_to_host_cb(instance, msg, msg_len); ++ vchi_held_msg_release(&msg_handle); ++ ++ break; ++ ++ case MMAL_MSG_TYPE_BUFFER_TO_HOST: ++ buffer_to_host_cb(instance, msg, msg_len); ++ vchi_held_msg_release(&msg_handle); ++ break; ++ ++ default: ++ /* messages dependant on header context to complete */ ++ ++ /* todo: the msg.context really ought to be sanity ++ * checked before we just use it, afaict it comes back ++ * and is used raw from the videocore. Perhaps it ++ * should be verified the address lies in the kernel ++ * address space. ++ */ ++ if (msg->h.context == NULL) { ++ pr_err("received message context was null!\n"); ++ vchi_held_msg_release(&msg_handle); ++ break; ++ } ++ ++ /* fill in context values */ ++ msg->h.context->u.sync.msg_handle = msg_handle; ++ msg->h.context->u.sync.msg = msg; ++ msg->h.context->u.sync.msg_len = msg_len; ++ ++ /* todo: should this check (completion_done() ++ * == 1) for no one waiting? or do we need a ++ * flag to tell us the completion has been ++ * interrupted so we can free the message and ++ * its context. This probably also solves the ++ * message arriving after interruption todo ++ * below ++ */ ++ ++ /* complete message so caller knows it happened */ ++ complete(&msg->h.context->u.sync.cmplt); ++ break; ++ } ++ ++ break; ++ ++ case VCHI_CALLBACK_BULK_RECEIVED: ++ bulk_receive_cb(instance, bulk_ctx); ++ break; ++ ++ case VCHI_CALLBACK_BULK_RECEIVE_ABORTED: ++ bulk_abort_cb(instance, bulk_ctx); ++ break; ++ ++ case VCHI_CALLBACK_SERVICE_CLOSED: ++ /* TODO: consider if this requires action if received when ++ * driver is not explicitly closing the service ++ */ ++ break; ++ ++ default: ++ pr_err("Received unhandled message reason %d\n", reason); ++ break; ++ } ++} ++ ++static int send_synchronous_mmal_msg(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, ++ unsigned int payload_len, ++ struct mmal_msg **msg_out, ++ VCHI_HELD_MSG_T *msg_handle_out) ++{ ++ struct mmal_msg_context msg_context; ++ int ret; ++ ++ /* payload size must not cause message to exceed max size */ ++ if (payload_len > ++ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))) { ++ pr_err("payload length %d exceeds max:%d\n", payload_len, ++ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))); ++ return -EINVAL; ++ } ++ ++ init_completion(&msg_context.u.sync.cmplt); ++ ++ msg->h.magic = MMAL_MAGIC; ++ msg->h.context = &msg_context; ++ msg->h.status = 0; ++ ++ DBG_DUMP_MSG(msg, (sizeof(struct mmal_msg_header) + payload_len), ++ ">>> sync message"); ++ ++ vchi_service_use(instance->handle); ++ ++ ret = vchi_msg_queue(instance->handle, ++ msg, ++ sizeof(struct mmal_msg_header) + payload_len, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ vchi_service_release(instance->handle); ++ ++ if (ret) { ++ pr_err("error %d queuing message\n", ret); ++ return ret; ++ } ++ ++ ret = wait_for_completion_timeout(&msg_context.u.sync.cmplt, 3*HZ); ++ if (ret <= 0) { ++ pr_err("error %d waiting for sync completion\n", ret); ++ if (ret == 0) ++ ret = -ETIME; ++ /* todo: what happens if the message arrives after aborting */ ++ return ret; ++ } ++ ++ *msg_out = msg_context.u.sync.msg; ++ *msg_handle_out = msg_context.u.sync.msg_handle; ++ ++ return 0; ++} ++ ++static void dump_port_info(struct vchiq_mmal_port *port) ++{ ++ pr_debug("port handle:0x%x enabled:%d\n", port->handle, port->enabled); ++ ++ pr_debug("buffer minimum num:%d size:%d align:%d\n", ++ port->minimum_buffer.num, ++ port->minimum_buffer.size, port->minimum_buffer.alignment); ++ ++ pr_debug("buffer recommended num:%d size:%d align:%d\n", ++ port->recommended_buffer.num, ++ port->recommended_buffer.size, ++ port->recommended_buffer.alignment); ++ ++ pr_debug("buffer current values num:%d size:%d align:%d\n", ++ port->current_buffer.num, ++ port->current_buffer.size, port->current_buffer.alignment); ++ ++ pr_debug("elementry stream: type:%d encoding:0x%x varient:0x%x\n", ++ port->format.type, ++ port->format.encoding, port->format.encoding_variant); ++ ++ pr_debug(" bitrate:%d flags:0x%x\n", ++ port->format.bitrate, port->format.flags); ++ ++ if (port->format.type == MMAL_ES_TYPE_VIDEO) { ++ pr_debug ++ ("es video format: width:%d height:%d colourspace:0x%x\n", ++ port->es.video.width, port->es.video.height, ++ port->es.video.color_space); ++ ++ pr_debug(" : crop xywh %d,%d,%d,%d\n", ++ port->es.video.crop.x, ++ port->es.video.crop.y, ++ port->es.video.crop.width, port->es.video.crop.height); ++ pr_debug(" : framerate %d/%d aspect %d/%d\n", ++ port->es.video.frame_rate.num, ++ port->es.video.frame_rate.den, ++ port->es.video.par.num, port->es.video.par.den); ++ } ++} ++ ++static void port_to_mmal_msg(struct vchiq_mmal_port *port, struct mmal_port *p) ++{ ++ ++ /* todo do readonly fields need setting at all? */ ++ p->type = port->type; ++ p->index = port->index; ++ p->index_all = 0; ++ p->is_enabled = port->enabled; ++ p->buffer_num_min = port->minimum_buffer.num; ++ p->buffer_size_min = port->minimum_buffer.size; ++ p->buffer_alignment_min = port->minimum_buffer.alignment; ++ p->buffer_num_recommended = port->recommended_buffer.num; ++ p->buffer_size_recommended = port->recommended_buffer.size; ++ ++ /* only three writable fields in a port */ ++ p->buffer_num = port->current_buffer.num; ++ p->buffer_size = port->current_buffer.size; ++ p->userdata = port; ++} ++ ++static int port_info_set(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ pr_debug("setting port info port %p\n", port); ++ if (!port) ++ return -1; ++ dump_port_info(port); ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_INFO_SET; ++ ++ m.u.port_info_set.component_handle = port->component->handle; ++ m.u.port_info_set.port_type = port->type; ++ m.u.port_info_set.port_index = port->index; ++ ++ port_to_mmal_msg(port, &m.u.port_info_set.port); ++ ++ /* elementry stream format setup */ ++ m.u.port_info_set.format.type = port->format.type; ++ m.u.port_info_set.format.encoding = port->format.encoding; ++ m.u.port_info_set.format.encoding_variant = ++ port->format.encoding_variant; ++ m.u.port_info_set.format.bitrate = port->format.bitrate; ++ m.u.port_info_set.format.flags = port->format.flags; ++ ++ memcpy(&m.u.port_info_set.es, &port->es, ++ sizeof(union mmal_es_specific_format)); ++ ++ m.u.port_info_set.format.extradata_size = port->format.extradata_size; ++ memcpy(rmsg->u.port_info_set.extradata, port->format.extradata, ++ port->format.extradata_size); ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.port_info_set), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_SET) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ /* return operation status */ ++ ret = -rmsg->u.port_info_get_reply.status; ++ ++ pr_debug("%s:result:%d component:0x%x port:%d\n", __func__, ret, ++ port->component->handle, port->handle); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++ ++} ++ ++/* use port info get message to retrive port information */ ++static int port_info_get(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ /* port info time */ ++ m.h.type = MMAL_MSG_TYPE_PORT_INFO_GET; ++ m.u.port_info_get.component_handle = port->component->handle; ++ m.u.port_info_get.port_type = port->type; ++ m.u.port_info_get.index = port->index; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.port_info_get), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_GET) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ /* return operation status */ ++ ret = -rmsg->u.port_info_get_reply.status; ++ if (ret != MMAL_MSG_STATUS_SUCCESS) ++ goto release_msg; ++ ++ if (rmsg->u.port_info_get_reply.port.is_enabled == 0) ++ port->enabled = false; ++ else ++ port->enabled = true; ++ ++ /* copy the values out of the message */ ++ port->handle = rmsg->u.port_info_get_reply.port_handle; ++ ++ /* port type and index cached to use on port info set becuase ++ * it does not use a port handle ++ */ ++ port->type = rmsg->u.port_info_get_reply.port_type; ++ port->index = rmsg->u.port_info_get_reply.port_index; ++ ++ port->minimum_buffer.num = ++ rmsg->u.port_info_get_reply.port.buffer_num_min; ++ port->minimum_buffer.size = ++ rmsg->u.port_info_get_reply.port.buffer_size_min; ++ port->minimum_buffer.alignment = ++ rmsg->u.port_info_get_reply.port.buffer_alignment_min; ++ ++ port->recommended_buffer.alignment = ++ rmsg->u.port_info_get_reply.port.buffer_alignment_min; ++ port->recommended_buffer.num = ++ rmsg->u.port_info_get_reply.port.buffer_num_recommended; ++ ++ port->current_buffer.num = rmsg->u.port_info_get_reply.port.buffer_num; ++ port->current_buffer.size = ++ rmsg->u.port_info_get_reply.port.buffer_size; ++ ++ /* stream format */ ++ port->format.type = rmsg->u.port_info_get_reply.format.type; ++ port->format.encoding = rmsg->u.port_info_get_reply.format.encoding; ++ port->format.encoding_variant = ++ rmsg->u.port_info_get_reply.format.encoding_variant; ++ port->format.bitrate = rmsg->u.port_info_get_reply.format.bitrate; ++ port->format.flags = rmsg->u.port_info_get_reply.format.flags; ++ ++ /* elementry stream format */ ++ memcpy(&port->es, ++ &rmsg->u.port_info_get_reply.es, ++ sizeof(union mmal_es_specific_format)); ++ port->format.es = &port->es; ++ ++ port->format.extradata_size = ++ rmsg->u.port_info_get_reply.format.extradata_size; ++ memcpy(port->format.extradata, ++ rmsg->u.port_info_get_reply.extradata, ++ port->format.extradata_size); ++ ++ pr_debug("received port info\n"); ++ dump_port_info(port); ++ ++release_msg: ++ ++ pr_debug("%s:result:%d component:0x%x port:%d\n", ++ __func__, ret, port->component->handle, port->handle); ++ ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* create comonent on vc */ ++static int create_component(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component, ++ const char *name) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ /* build component create message */ ++ m.h.type = MMAL_MSG_TYPE_COMPONENT_CREATE; ++ m.u.component_create.client_component = component; ++ strncpy(m.u.component_create.name, name, ++ sizeof(m.u.component_create.name)); ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.component_create), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.component_create_reply.status; ++ if (ret != MMAL_MSG_STATUS_SUCCESS) ++ goto release_msg; ++ ++ /* a valid component response received */ ++ component->handle = rmsg->u.component_create_reply.component_handle; ++ component->inputs = rmsg->u.component_create_reply.input_num; ++ component->outputs = rmsg->u.component_create_reply.output_num; ++ component->clocks = rmsg->u.component_create_reply.clock_num; ++ ++ pr_debug("Component handle:0x%x in:%d out:%d clock:%d\n", ++ component->handle, ++ component->inputs, component->outputs, component->clocks); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* destroys a component on vc */ ++static int destroy_component(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_COMPONENT_DESTROY; ++ m.u.component_destroy.component_handle = component->handle; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.component_destroy), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.component_destroy_reply.status; ++ ++release_msg: ++ ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* enable a component on vc */ ++static int enable_component(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_COMPONENT_ENABLE; ++ m.u.component_enable.component_handle = component->handle; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.component_enable), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.component_enable_reply.status; ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* disable a component on vc */ ++static int disable_component(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_COMPONENT_DISABLE; ++ m.u.component_disable.component_handle = component->handle; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.component_disable), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.component_disable_reply.status; ++ ++release_msg: ++ ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* get version of mmal implementation */ ++static int get_version(struct vchiq_mmal_instance *instance, ++ u32 *major_out, u32 *minor_out) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_GET_VERSION; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.version), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ *major_out = rmsg->u.version.major; ++ *minor_out = rmsg->u.version.minor; ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* do a port action with a port as a parameter */ ++static int port_action_port(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ enum mmal_msg_port_action_type action_type) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_ACTION; ++ m.u.port_action_port.component_handle = port->component->handle; ++ m.u.port_action_port.port_handle = port->handle; ++ m.u.port_action_port.action = action_type; ++ ++ port_to_mmal_msg(port, &m.u.port_action_port.port); ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.port_action_port), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.port_action_reply.status; ++ ++ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)\n", ++ __func__, ++ ret, port->component->handle, port->handle, ++ port_action_type_names[action_type], action_type); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* do a port action with handles as parameters */ ++static int port_action_handle(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ enum mmal_msg_port_action_type action_type, ++ u32 connect_component_handle, ++ u32 connect_port_handle) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_ACTION; ++ ++ m.u.port_action_handle.component_handle = port->component->handle; ++ m.u.port_action_handle.port_handle = port->handle; ++ m.u.port_action_handle.action = action_type; ++ ++ m.u.port_action_handle.connect_component_handle = ++ connect_component_handle; ++ m.u.port_action_handle.connect_port_handle = connect_port_handle; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.port_action_handle), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.port_action_reply.status; ++ ++ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)" \ ++ " connect component:0x%x connect port:%d\n", ++ __func__, ++ ret, port->component->handle, port->handle, ++ port_action_type_names[action_type], ++ action_type, connect_component_handle, connect_port_handle); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++static int port_parameter_set(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter_id, void *value, u32 value_size) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_SET; ++ ++ m.u.port_parameter_set.component_handle = port->component->handle; ++ m.u.port_parameter_set.port_handle = port->handle; ++ m.u.port_parameter_set.id = parameter_id; ++ m.u.port_parameter_set.size = (2 * sizeof(u32)) + value_size; ++ memcpy(&m.u.port_parameter_set.value, value, value_size); ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ (4 * sizeof(u32)) + value_size, ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_SET) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.port_parameter_set_reply.status; ++ ++ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", ++ __func__, ++ ret, port->component->handle, port->handle, parameter_id); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++static int port_parameter_get(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter_id, void *value, u32 *value_size) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_GET; ++ ++ m.u.port_parameter_get.component_handle = port->component->handle; ++ m.u.port_parameter_get.port_handle = port->handle; ++ m.u.port_parameter_get.id = parameter_id; ++ m.u.port_parameter_get.size = (2 * sizeof(u32)) + *value_size; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(struct ++ mmal_msg_port_parameter_get), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_GET) { ++ /* got an unexpected message type in reply */ ++ pr_err("Incorrect reply type %d\n", rmsg->h.type); ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.port_parameter_get_reply.status; ++ if (ret) { ++ /* Copy only as much as we have space for ++ * but report true size of parameter ++ */ ++ memcpy(value, &rmsg->u.port_parameter_get_reply.value, ++ *value_size); ++ *value_size = rmsg->u.port_parameter_get_reply.size; ++ } else ++ memcpy(value, &rmsg->u.port_parameter_get_reply.value, ++ rmsg->u.port_parameter_get_reply.size); ++ ++ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", __func__, ++ ret, port->component->handle, port->handle, parameter_id); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* disables a port and drains buffers from it */ ++static int port_disable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ struct list_head *q, *buf_head; ++ unsigned long flags = 0; ++ ++ if (!port->enabled) ++ return 0; ++ ++ port->enabled = false; ++ ++ ret = port_action_port(instance, port, ++ MMAL_MSG_PORT_ACTION_TYPE_DISABLE); ++ if (ret == 0) { ++ ++ /* drain all queued buffers on port */ ++ spin_lock_irqsave(&port->slock, flags); ++ ++ list_for_each_safe(buf_head, q, &port->buffers) { ++ struct mmal_buffer *mmalbuf; ++ mmalbuf = list_entry(buf_head, struct mmal_buffer, ++ list); ++ list_del(buf_head); ++ if (port->buffer_cb) ++ port->buffer_cb(instance, ++ port, 0, mmalbuf, 0, 0, ++ MMAL_TIME_UNKNOWN, ++ MMAL_TIME_UNKNOWN); ++ } ++ ++ spin_unlock_irqrestore(&port->slock, flags); ++ ++ ret = port_info_get(instance, port); ++ } ++ ++ return ret; ++} ++ ++/* enable a port */ ++static int port_enable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ unsigned int hdr_count; ++ struct list_head *buf_head; ++ int ret; ++ ++ if (port->enabled) ++ return 0; ++ ++ /* ensure there are enough buffers queued to cover the buffer headers */ ++ if (port->buffer_cb != NULL) { ++ hdr_count = 0; ++ list_for_each(buf_head, &port->buffers) { ++ hdr_count++; ++ } ++ if (hdr_count < port->current_buffer.num) ++ return -ENOSPC; ++ } ++ ++ ret = port_action_port(instance, port, ++ MMAL_MSG_PORT_ACTION_TYPE_ENABLE); ++ if (ret) ++ goto done; ++ ++ port->enabled = true; ++ ++ if (port->buffer_cb) { ++ /* send buffer headers to videocore */ ++ hdr_count = 1; ++ list_for_each(buf_head, &port->buffers) { ++ struct mmal_buffer *mmalbuf; ++ mmalbuf = list_entry(buf_head, struct mmal_buffer, ++ list); ++ ret = buffer_from_host(instance, port, mmalbuf); ++ if (ret) ++ goto done; ++ ++ hdr_count++; ++ if (hdr_count > port->current_buffer.num) ++ break; ++ } ++ } ++ ++ ret = port_info_get(instance, port); ++ ++done: ++ return ret; ++} ++ ++/* ------------------------------------------------------------------ ++ * Exported API ++ *------------------------------------------------------------------*/ ++ ++int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ ret = port_info_set(instance, port); ++ if (ret) ++ goto release_unlock; ++ ++ /* read what has actually been set */ ++ ret = port_info_get(instance, port); ++ ++release_unlock: ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++ ++} ++ ++int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter, void *value, u32 value_size) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ ret = port_parameter_set(instance, port, parameter, value, value_size); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter, void *value, u32 *value_size) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ ret = port_parameter_get(instance, port, parameter, value, value_size); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* enable a port ++ * ++ * enables a port and queues buffers for satisfying callbacks if we ++ * provide a callback handler ++ */ ++int vchiq_mmal_port_enable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ vchiq_mmal_buffer_cb buffer_cb) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ /* already enabled - noop */ ++ if (port->enabled) { ++ ret = 0; ++ goto unlock; ++ } ++ ++ port->buffer_cb = buffer_cb; ++ ++ ret = port_enable(instance, port); ++ ++unlock: ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (!port->enabled) { ++ mutex_unlock(&instance->vchiq_mutex); ++ return 0; ++ } ++ ++ ret = port_disable(instance, port); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* ports will be connected in a tunneled manner so data buffers ++ * are not handled by client. ++ */ ++int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *src, ++ struct vchiq_mmal_port *dst) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ /* disconnect ports if connected */ ++ if (src->connected != NULL) { ++ ret = port_disable(instance, src); ++ if (ret) { ++ pr_err("failed disabling src port(%d)\n", ret); ++ goto release_unlock; ++ } ++ ++ /* do not need to disable the destination port as they ++ * are connected and it is done automatically ++ */ ++ ++ ret = port_action_handle(instance, src, ++ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, ++ src->connected->component->handle, ++ src->connected->handle); ++ if (ret < 0) { ++ pr_err("failed disconnecting src port\n"); ++ goto release_unlock; ++ } ++ src->connected->enabled = false; ++ src->connected = NULL; ++ } ++ ++ if (dst == NULL) { ++ /* do not make new connection */ ++ ret = 0; ++ pr_debug("not making new connection\n"); ++ goto release_unlock; ++ } ++ ++ /* copy src port format to dst */ ++ dst->format.encoding = src->format.encoding; ++ dst->es.video.width = src->es.video.width; ++ dst->es.video.height = src->es.video.height; ++ dst->es.video.crop.x = src->es.video.crop.x; ++ dst->es.video.crop.y = src->es.video.crop.y; ++ dst->es.video.crop.width = src->es.video.crop.width; ++ dst->es.video.crop.height = src->es.video.crop.height; ++ dst->es.video.frame_rate.num = src->es.video.frame_rate.num; ++ dst->es.video.frame_rate.den = src->es.video.frame_rate.den; ++ ++ /* set new format */ ++ ret = port_info_set(instance, dst); ++ if (ret) { ++ pr_debug("setting port info failed\n"); ++ goto release_unlock; ++ } ++ ++ /* read what has actually been set */ ++ ret = port_info_get(instance, dst); ++ if (ret) { ++ pr_debug("read back port info failed\n"); ++ goto release_unlock; ++ } ++ ++ /* connect two ports together */ ++ ret = port_action_handle(instance, src, ++ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, ++ dst->component->handle, dst->handle); ++ if (ret < 0) { ++ pr_debug("connecting port %d:%d to %d:%d failed\n", ++ src->component->handle, src->handle, ++ dst->component->handle, dst->handle); ++ goto release_unlock; ++ } ++ src->connected = dst; ++ ++release_unlock: ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ struct mmal_buffer *buffer) ++{ ++ unsigned long flags = 0; ++ ++ spin_lock_irqsave(&port->slock, flags); ++ list_add_tail(&buffer->list, &port->buffers); ++ spin_unlock_irqrestore(&port->slock, flags); ++ ++ /* the port previously underflowed because it was missing a ++ * mmal_buffer which has just been added, submit that buffer ++ * to the mmal service. ++ */ ++ if (port->buffer_underflow) { ++ port_buffer_from_host(instance, port); ++ port->buffer_underflow--; ++ } ++ ++ return 0; ++} ++ ++/* Initialise a mmal component and its ports ++ * ++ */ ++int vchiq_mmal_component_init(struct vchiq_mmal_instance *instance, ++ const char *name, ++ struct vchiq_mmal_component **component_out) ++{ ++ int ret; ++ int idx; /* port index */ ++ struct vchiq_mmal_component *component; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (instance->component_idx == VCHIQ_MMAL_MAX_COMPONENTS) { ++ ret = -EINVAL; /* todo is this correct error? */ ++ goto unlock; ++ } ++ ++ component = &instance->component[instance->component_idx]; ++ ++ ret = create_component(instance, component, name); ++ if (ret < 0) ++ goto unlock; ++ ++ /* ports info needs gathering */ ++ component->control.type = MMAL_PORT_TYPE_CONTROL; ++ component->control.index = 0; ++ component->control.component = component; ++ spin_lock_init(&component->control.slock); ++ INIT_LIST_HEAD(&component->control.buffers); ++ ret = port_info_get(instance, &component->control); ++ if (ret < 0) ++ goto release_component; ++ ++ for (idx = 0; idx < component->inputs; idx++) { ++ component->input[idx].type = MMAL_PORT_TYPE_INPUT; ++ component->input[idx].index = idx; ++ component->input[idx].component = component; ++ spin_lock_init(&component->input[idx].slock); ++ INIT_LIST_HEAD(&component->input[idx].buffers); ++ ret = port_info_get(instance, &component->input[idx]); ++ if (ret < 0) ++ goto release_component; ++ } ++ ++ for (idx = 0; idx < component->outputs; idx++) { ++ component->output[idx].type = MMAL_PORT_TYPE_OUTPUT; ++ component->output[idx].index = idx; ++ component->output[idx].component = component; ++ spin_lock_init(&component->output[idx].slock); ++ INIT_LIST_HEAD(&component->output[idx].buffers); ++ ret = port_info_get(instance, &component->output[idx]); ++ if (ret < 0) ++ goto release_component; ++ } ++ ++ for (idx = 0; idx < component->clocks; idx++) { ++ component->clock[idx].type = MMAL_PORT_TYPE_CLOCK; ++ component->clock[idx].index = idx; ++ component->clock[idx].component = component; ++ spin_lock_init(&component->clock[idx].slock); ++ INIT_LIST_HEAD(&component->clock[idx].buffers); ++ ret = port_info_get(instance, &component->clock[idx]); ++ if (ret < 0) ++ goto release_component; ++ } ++ ++ instance->component_idx++; ++ ++ *component_out = component; ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return 0; ++ ++release_component: ++ destroy_component(instance, component); ++unlock: ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* ++ * cause a mmal component to be destroyed ++ */ ++int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (component->enabled) ++ ret = disable_component(instance, component); ++ ++ ret = destroy_component(instance, component); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* ++ * cause a mmal component to be enabled ++ */ ++int vchiq_mmal_component_enable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (component->enabled) { ++ mutex_unlock(&instance->vchiq_mutex); ++ return 0; ++ } ++ ++ ret = enable_component(instance, component); ++ if (ret == 0) ++ component->enabled = true; ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* ++ * cause a mmal component to be enabled ++ */ ++int vchiq_mmal_component_disable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (!component->enabled) { ++ mutex_unlock(&instance->vchiq_mutex); ++ return 0; ++ } ++ ++ ret = disable_component(instance, component); ++ if (ret == 0) ++ component->enabled = false; ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_version(struct vchiq_mmal_instance *instance, ++ u32 *major_out, u32 *minor_out) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ ret = get_version(instance, major_out, minor_out); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance) ++{ ++ int status = 0; ++ ++ if (instance == NULL) ++ return -EINVAL; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ vchi_service_use(instance->handle); ++ ++ status = vchi_service_close(instance->handle); ++ if (status != 0) ++ pr_err("mmal-vchiq: VCHIQ close failed"); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ vfree(instance->bulk_scratch); ++ ++ kfree(instance); ++ ++ return status; ++} ++ ++int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance) ++{ ++ int status; ++ struct vchiq_mmal_instance *instance; ++ static VCHI_CONNECTION_T *vchi_connection; ++ static VCHI_INSTANCE_T vchi_instance; ++ SERVICE_CREATION_T params = { ++ VCHI_VERSION_EX(VC_MMAL_VER, VC_MMAL_MIN_VER), ++ VC_MMAL_SERVER_NAME, ++ vchi_connection, ++ 0, /* rx fifo size (unused) */ ++ 0, /* tx fifo size (unused) */ ++ service_callback, ++ NULL, /* service callback parameter */ ++ 1, /* unaligned bulk receives */ ++ 1, /* unaligned bulk transmits */ ++ 0 /* want crc check on bulk transfers */ ++ }; ++ ++ /* compile time checks to ensure structure size as they are ++ * directly (de)serialised from memory. ++ */ ++ ++ /* ensure the header structure has packed to the correct size */ ++ BUILD_BUG_ON(sizeof(struct mmal_msg_header) != 24); ++ ++ /* ensure message structure does not exceed maximum length */ ++ BUILD_BUG_ON(sizeof(struct mmal_msg) > MMAL_MSG_MAX_SIZE); ++ ++ /* mmal port struct is correct size */ ++ BUILD_BUG_ON(sizeof(struct mmal_port) != 64); ++ ++ /* create a vchi instance */ ++ status = vchi_initialise(&vchi_instance); ++ if (status) { ++ pr_err("Failed to initialise VCHI instance (status=%d)\n", ++ status); ++ return -EIO; ++ } ++ ++ status = vchi_connect(NULL, 0, vchi_instance); ++ if (status) { ++ pr_err("Failed to connect VCHI instance (status=%d)\n", status); ++ return -EIO; ++ } ++ ++ instance = kmalloc(sizeof(*instance), GFP_KERNEL); ++ memset(instance, 0, sizeof(*instance)); ++ ++ mutex_init(&instance->vchiq_mutex); ++ mutex_init(&instance->bulk_mutex); ++ ++ instance->bulk_scratch = vmalloc(PAGE_SIZE); ++ ++ params.callback_param = instance; ++ ++ status = vchi_service_open(vchi_instance, ¶ms, &instance->handle); ++ if (status) { ++ pr_err("Failed to open VCHI service connection (status=%d)\n", ++ status); ++ goto err_close_services; ++ } ++ ++ vchi_service_release(instance->handle); ++ ++ *out_instance = instance; ++ ++ return 0; ++ ++err_close_services: ++ ++ vchi_service_close(instance->handle); ++ vfree(instance->bulk_scratch); ++ kfree(instance); ++ return -ENODEV; ++} +--- /dev/null ++++ b/drivers/media/platform/bcm2835/mmal-vchiq.h +@@ -0,0 +1,178 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ * ++ * MMAL interface to VCHIQ message passing ++ */ ++ ++#ifndef MMAL_VCHIQ_H ++#define MMAL_VCHIQ_H ++ ++#include "mmal-msg-format.h" ++ ++#define MAX_PORT_COUNT 4 ++ ++/* Maximum size of the format extradata. */ ++#define MMAL_FORMAT_EXTRADATA_MAX_SIZE 128 ++ ++struct vchiq_mmal_instance; ++ ++enum vchiq_mmal_es_type { ++ MMAL_ES_TYPE_UNKNOWN, /**< Unknown elementary stream type */ ++ MMAL_ES_TYPE_CONTROL, /**< Elementary stream of control commands */ ++ MMAL_ES_TYPE_AUDIO, /**< Audio elementary stream */ ++ MMAL_ES_TYPE_VIDEO, /**< Video elementary stream */ ++ MMAL_ES_TYPE_SUBPICTURE /**< Sub-picture elementary stream */ ++}; ++ ++/* rectangle, used lots so it gets its own struct */ ++struct vchiq_mmal_rect { ++ s32 x; ++ s32 y; ++ s32 width; ++ s32 height; ++}; ++ ++struct vchiq_mmal_port_buffer { ++ unsigned int num; /* number of buffers */ ++ u32 size; /* size of buffers */ ++ u32 alignment; /* alignment of buffers */ ++}; ++ ++struct vchiq_mmal_port; ++ ++typedef void (*vchiq_mmal_buffer_cb)( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ int status, struct mmal_buffer *buffer, ++ unsigned long length, u32 mmal_flags, s64 dts, s64 pts); ++ ++struct vchiq_mmal_port { ++ bool enabled; ++ u32 handle; ++ u32 type; /* port type, cached to use on port info set */ ++ u32 index; /* port index, cached to use on port info set */ ++ ++ /* component port belongs to, allows simple deref */ ++ struct vchiq_mmal_component *component; ++ ++ struct vchiq_mmal_port *connected; /* port conencted to */ ++ ++ /* buffer info */ ++ struct vchiq_mmal_port_buffer minimum_buffer; ++ struct vchiq_mmal_port_buffer recommended_buffer; ++ struct vchiq_mmal_port_buffer current_buffer; ++ ++ /* stream format */ ++ struct mmal_es_format format; ++ /* elementry stream format */ ++ union mmal_es_specific_format es; ++ ++ /* data buffers to fill */ ++ struct list_head buffers; ++ /* lock to serialise adding and removing buffers from list */ ++ spinlock_t slock; ++ /* count of how many buffer header refils have failed because ++ * there was no buffer to satisfy them ++ */ ++ int buffer_underflow; ++ /* callback on buffer completion */ ++ vchiq_mmal_buffer_cb buffer_cb; ++ /* callback context */ ++ void *cb_ctx; ++}; ++ ++struct vchiq_mmal_component { ++ bool enabled; ++ u32 handle; /* VideoCore handle for component */ ++ u32 inputs; /* Number of input ports */ ++ u32 outputs; /* Number of output ports */ ++ u32 clocks; /* Number of clock ports */ ++ struct vchiq_mmal_port control; /* control port */ ++ struct vchiq_mmal_port input[MAX_PORT_COUNT]; /* input ports */ ++ struct vchiq_mmal_port output[MAX_PORT_COUNT]; /* output ports */ ++ struct vchiq_mmal_port clock[MAX_PORT_COUNT]; /* clock ports */ ++}; ++ ++ ++int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance); ++int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance); ++ ++/* Initialise a mmal component and its ports ++* ++*/ ++int vchiq_mmal_component_init( ++ struct vchiq_mmal_instance *instance, ++ const char *name, ++ struct vchiq_mmal_component **component_out); ++ ++int vchiq_mmal_component_finalise( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component); ++ ++int vchiq_mmal_component_enable( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component); ++ ++int vchiq_mmal_component_disable( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component); ++ ++ ++ ++/* enable a mmal port ++ * ++ * enables a port and if a buffer callback provided enque buffer ++ * headers as apropriate for the port. ++ */ ++int vchiq_mmal_port_enable( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ vchiq_mmal_buffer_cb buffer_cb); ++ ++/* disable a port ++ * ++ * disable a port will dequeue any pending buffers ++ */ ++int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port); ++ ++ ++int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter, ++ void *value, ++ u32 value_size); ++ ++int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter, ++ void *value, ++ u32 *value_size); ++ ++int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port); ++ ++int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *src, ++ struct vchiq_mmal_port *dst); ++ ++int vchiq_mmal_version(struct vchiq_mmal_instance *instance, ++ u32 *major_out, ++ u32 *minor_out); ++ ++int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ struct mmal_buffer *buf); ++ ++#endif /* MMAL_VCHIQ_H */ diff --git a/target/linux/brcm2708/patches-4.1/0022-scripts-dtc-Update-to-upstream-version-with-overlay-.patch b/target/linux/brcm2708/patches-4.1/0022-scripts-dtc-Update-to-upstream-version-with-overlay-.patch new file mode 100644 index 0000000..2a42491 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0022-scripts-dtc-Update-to-upstream-version-with-overlay-.patch @@ -0,0 +1,5175 @@ +From ee7658ee2a268e93a57c507cac4bed85b2c7e8f0 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 23 Jan 2015 14:48:55 +0000 +Subject: [PATCH 022/203] scripts/dtc: Update to upstream version with overlay + patches + +--- + scripts/dtc/checks.c | 151 ++- + scripts/dtc/data.c | 12 +- + scripts/dtc/dtc-lexer.l | 70 +- + scripts/dtc/dtc-lexer.lex.c_shipped | 540 +++++----- + scripts/dtc/dtc-parser.tab.c_shipped | 1783 ++++++++++++++++------------------ + scripts/dtc/dtc-parser.tab.h_shipped | 116 ++- + scripts/dtc/dtc-parser.y | 158 +-- + scripts/dtc/dtc.c | 23 +- + scripts/dtc/dtc.h | 56 +- + scripts/dtc/flattree.c | 145 ++- + scripts/dtc/fstree.c | 16 +- + scripts/dtc/livetree.c | 4 +- + scripts/dtc/srcpos.c | 49 +- + scripts/dtc/srcpos.h | 15 +- + scripts/dtc/treesource.c | 14 +- + scripts/dtc/util.c | 18 +- + scripts/dtc/util.h | 4 +- + scripts/dtc/version_gen.h | 2 +- + 18 files changed, 1697 insertions(+), 1479 deletions(-) + +--- a/scripts/dtc/checks.c ++++ b/scripts/dtc/checks.c +@@ -53,7 +53,7 @@ struct check { + void *data; + bool warn, error; + enum checkstatus status; +- int inprogress; ++ bool inprogress; + int num_prereqs; + struct check **prereq; + }; +@@ -113,6 +113,7 @@ static inline void check_msg(struct chec + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + } ++ va_end(ap); + } + + #define FAIL(c, ...) \ +@@ -141,9 +142,9 @@ static void check_nodes_props(struct che + check_nodes_props(c, dt, child); + } + +-static int run_check(struct check *c, struct node *dt) ++static bool run_check(struct check *c, struct node *dt) + { +- int error = 0; ++ bool error = false; + int i; + + assert(!c->inprogress); +@@ -151,11 +152,11 @@ static int run_check(struct check *c, st + if (c->status != UNCHECKED) + goto out; + +- c->inprogress = 1; ++ c->inprogress = true; + + for (i = 0; i < c->num_prereqs; i++) { + struct check *prq = c->prereq[i]; +- error |= run_check(prq, dt); ++ error = error || run_check(prq, dt); + if (prq->status != PASSED) { + c->status = PREREQ; + check_msg(c, "Failed prerequisite '%s'", +@@ -177,9 +178,9 @@ static int run_check(struct check *c, st + TRACE(c, "\tCompleted, status %d", c->status); + + out: +- c->inprogress = 0; ++ c->inprogress = false; + if ((c->status != PASSED) && (c->error)) +- error = 1; ++ error = true; + return error; + } + +@@ -457,22 +458,93 @@ static void fixup_phandle_references(str + struct node *node, struct property *prop) + { + struct marker *m = prop->val.markers; ++ struct fixup *f, **fp; ++ struct fixup_entry *fe, **fep; + struct node *refnode; + cell_t phandle; ++ int has_phandle_refs; ++ ++ has_phandle_refs = 0; ++ for_each_marker_of_type(m, REF_PHANDLE) { ++ has_phandle_refs = 1; ++ break; ++ } ++ ++ if (!has_phandle_refs) ++ return; + + for_each_marker_of_type(m, REF_PHANDLE) { + assert(m->offset + sizeof(cell_t) <= prop->val.len); + + refnode = get_node_by_ref(dt, m->ref); +- if (! refnode) { ++ if (!refnode && !symbol_fixup_support) { + FAIL(c, "Reference to non-existent node or label \"%s\"\n", +- m->ref); ++ m->ref); + continue; + } + +- phandle = get_node_phandle(dt, refnode); +- *((cell_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle); ++ if (!refnode) { ++ /* allocate fixup entry */ ++ fe = xmalloc(sizeof(*fe)); ++ ++ fe->node = node; ++ fe->prop = prop; ++ fe->offset = m->offset; ++ fe->next = NULL; ++ ++ /* search for an already existing fixup */ ++ for_each_fixup(dt, f) ++ if (strcmp(f->ref, m->ref) == 0) ++ break; ++ ++ /* no fixup found, add new */ ++ if (f == NULL) { ++ f = xmalloc(sizeof(*f)); ++ f->ref = m->ref; ++ f->entries = NULL; ++ f->next = NULL; ++ ++ /* add it to the tree */ ++ fp = &dt->fixups; ++ while (*fp) ++ fp = &(*fp)->next; ++ *fp = f; ++ } ++ ++ /* and now append fixup entry */ ++ fep = &f->entries; ++ while (*fep) ++ fep = &(*fep)->next; ++ *fep = fe; ++ ++ /* mark the entry as unresolved */ ++ phandle = 0xdeadbeef; ++ } else { ++ phandle = get_node_phandle(dt, refnode); ++ ++ /* if it's a plugin, we need to record it */ ++ if (symbol_fixup_support && dt->is_plugin) { ++ ++ /* allocate a new local fixup entry */ ++ fe = xmalloc(sizeof(*fe)); ++ ++ fe->node = node; ++ fe->prop = prop; ++ fe->offset = m->offset; ++ fe->next = NULL; ++ ++ /* append it to the local fixups */ ++ fep = &dt->local_fixups; ++ while (*fep) ++ fep = &(*fep)->next; ++ *fep = fe; ++ } ++ } ++ ++ *((cell_t *)(prop->val.val + m->offset)) = ++ cpu_to_fdt32(phandle); + } ++ + } + ERROR(phandle_references, NULL, NULL, fixup_phandle_references, NULL, + &duplicate_node_names, &explicit_phandles); +@@ -624,11 +696,11 @@ static void check_avoid_default_addr_siz + if (!reg && !ranges) + return; + +- if ((node->parent->addr_cells == -1)) ++ if (node->parent->addr_cells == -1) + FAIL(c, "Relying on default #address-cells value for %s", + node->fullpath); + +- if ((node->parent->size_cells == -1)) ++ if (node->parent->size_cells == -1) + FAIL(c, "Relying on default #size-cells value for %s", + node->fullpath); + } +@@ -651,6 +723,45 @@ static void check_obsolete_chosen_interr + } + TREE_WARNING(obsolete_chosen_interrupt_controller, NULL); + ++static void check_auto_label_phandles(struct check *c, struct node *dt, ++ struct node *node) ++{ ++ struct label *l; ++ struct symbol *s, **sp; ++ int has_label; ++ ++ if (!symbol_fixup_support) ++ return; ++ ++ has_label = 0; ++ for_each_label(node->labels, l) { ++ has_label = 1; ++ break; ++ } ++ ++ if (!has_label) ++ return; ++ ++ /* force allocation of a phandle for this node */ ++ (void)get_node_phandle(dt, node); ++ ++ /* add the symbol */ ++ for_each_label(node->labels, l) { ++ ++ s = xmalloc(sizeof(*s)); ++ s->label = l; ++ s->node = node; ++ s->next = NULL; ++ ++ /* add it to the symbols list */ ++ sp = &dt->symbols; ++ while (*sp) ++ sp = &((*sp)->next); ++ *sp = s; ++ } ++} ++NODE_WARNING(auto_label_phandles, NULL); ++ + static struct check *check_table[] = { + &duplicate_node_names, &duplicate_property_names, + &node_name_chars, &node_name_format, &property_name_chars, +@@ -669,6 +780,8 @@ static struct check *check_table[] = { + &avoid_default_addr_size, + &obsolete_chosen_interrupt_controller, + ++ &auto_label_phandles, ++ + &always_fail, + }; + +@@ -706,15 +819,15 @@ static void disable_warning_error(struct + c->error = c->error && !error; + } + +-void parse_checks_option(bool warn, bool error, const char *optarg) ++void parse_checks_option(bool warn, bool error, const char *arg) + { + int i; +- const char *name = optarg; ++ const char *name = arg; + bool enable = true; + +- if ((strncmp(optarg, "no-", 3) == 0) +- || (strncmp(optarg, "no_", 3) == 0)) { +- name = optarg + 3; ++ if ((strncmp(arg, "no-", 3) == 0) ++ || (strncmp(arg, "no_", 3) == 0)) { ++ name = arg + 3; + enable = false; + } + +@@ -733,7 +846,7 @@ void parse_checks_option(bool warn, bool + die("Unrecognized check name \"%s\"\n", name); + } + +-void process_checks(int force, struct boot_info *bi) ++void process_checks(bool force, struct boot_info *bi) + { + struct node *dt = bi->dt; + int i; +--- a/scripts/dtc/data.c ++++ b/scripts/dtc/data.c +@@ -74,7 +74,7 @@ struct data data_copy_escape_string(cons + struct data d; + char *q; + +- d = data_grow_for(empty_data, strlen(s)+1); ++ d = data_grow_for(empty_data, len + 1); + + q = d.val; + while (i < len) { +@@ -250,20 +250,20 @@ struct data data_add_marker(struct data + return data_append_markers(d, m); + } + +-int data_is_one_string(struct data d) ++bool data_is_one_string(struct data d) + { + int i; + int len = d.len; + + if (len == 0) +- return 0; ++ return false; + + for (i = 0; i < len-1; i++) + if (d.val[i] == '\0') +- return 0; ++ return false; + + if (d.val[len-1] != '\0') +- return 0; ++ return false; + +- return 1; ++ return true; + } +--- a/scripts/dtc/dtc-lexer.l ++++ b/scripts/dtc/dtc-lexer.l +@@ -20,7 +20,6 @@ + + %option noyywrap nounput noinput never-interactive + +-%x INCLUDE + %x BYTESTRING + %x PROPNODENAME + %s V1 +@@ -40,6 +39,7 @@ LINECOMMENT "//".*\n + #include "dtc-parser.tab.h" + + YYLTYPE yylloc; ++extern bool treesource_error; + + /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ + #define YY_USER_ACTION \ +@@ -61,7 +61,8 @@ static int dts_version = 1; + BEGIN(V1); \ + + static void push_input_file(const char *filename); +-static int pop_input_file(void); ++static bool pop_input_file(void); ++static void lexical_error(const char *fmt, ...); + %} + + %% +@@ -75,11 +76,11 @@ static int pop_input_file(void); + char *line, *tmp, *fn; + /* skip text before line # */ + line = yytext; +- while (!isdigit(*line)) ++ while (!isdigit((unsigned char)*line)) + line++; + /* skip digits in line # */ + tmp = line; +- while (!isspace(*tmp)) ++ while (!isspace((unsigned char)*tmp)) + tmp++; + /* "NULL"-terminate line # */ + *tmp = '\0'; +@@ -112,6 +113,11 @@ static int pop_input_file(void); + return DT_V1; + } + ++<*>"/plugin/" { ++ DPRINT("Keyword: /plugin/\n"); ++ return DT_PLUGIN; ++ } ++ + <*>"/memreserve/" { + DPRINT("Keyword: /memreserve/\n"); + BEGIN_DEFAULT(); +@@ -146,15 +152,42 @@ static int pop_input_file(void); + } + + ([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? { +- yylval.literal = xstrdup(yytext); +- DPRINT("Literal: '%s'\n", yylval.literal); ++ char *e; ++ DPRINT("Integer Literal: '%s'\n", yytext); ++ ++ errno = 0; ++ yylval.integer = strtoull(yytext, &e, 0); ++ ++ assert(!(*e) || !e[strspn(e, "UL")]); ++ ++ if (errno == ERANGE) ++ lexical_error("Integer literal '%s' out of range", ++ yytext); ++ else ++ /* ERANGE is the only strtoull error triggerable ++ * by strings matching the pattern */ ++ assert(errno == 0); + return DT_LITERAL; + } + + <*>{CHAR_LITERAL} { +- yytext[yyleng-1] = '\0'; +- yylval.literal = xstrdup(yytext+1); +- DPRINT("Character literal: %s\n", yylval.literal); ++ struct data d; ++ DPRINT("Character literal: %s\n", yytext); ++ ++ d = data_copy_escape_string(yytext+1, yyleng-2); ++ if (d.len == 1) { ++ lexical_error("Empty character literal"); ++ yylval.integer = 0; ++ return DT_CHAR_LITERAL; ++ } ++ ++ yylval.integer = (unsigned char)d.val[0]; ++ ++ if (d.len > 2) ++ lexical_error("Character literal has %d" ++ " characters instead of 1", ++ d.len - 1); ++ + return DT_CHAR_LITERAL; + } + +@@ -164,7 +197,7 @@ static int pop_input_file(void); + return DT_REF; + } + +-<*>"&{/"{PATHCHAR}+\} { /* new-style path reference */ ++<*>"&{/"{PATHCHAR}*\} { /* new-style path reference */ + yytext[yyleng-1] = '\0'; + DPRINT("Ref: %s\n", yytext+2); + yylval.labelref = xstrdup(yytext+2); +@@ -238,13 +271,24 @@ static void push_input_file(const char * + } + + +-static int pop_input_file(void) ++static bool pop_input_file(void) + { + if (srcfile_pop() == 0) +- return 0; ++ return false; + + yypop_buffer_state(); + yyin = current_srcfile->f; + +- return 1; ++ return true; ++} ++ ++static void lexical_error(const char *fmt, ...) ++{ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ srcpos_verror(&yylloc, "Lexical error", fmt, ap); ++ va_end(ap); ++ ++ treesource_error = true; + } +--- a/scripts/dtc/dtc-lexer.lex.c_shipped ++++ b/scripts/dtc/dtc-lexer.lex.c_shipped +@@ -372,8 +372,8 @@ static void yy_fatal_error (yyconst char + *yy_cp = '\0'; \ + (yy_c_buf_p) = yy_cp; + +-#define YY_NUM_RULES 30 +-#define YY_END_OF_BUFFER 31 ++#define YY_NUM_RULES 31 ++#define YY_END_OF_BUFFER 32 + /* This struct is not used in this scanner, + but its presence is necessary. */ + struct yy_trans_info +@@ -381,25 +381,26 @@ struct yy_trans_info + flex_int32_t yy_verify; + flex_int32_t yy_nxt; + }; +-static yyconst flex_int16_t yy_accept[161] = ++static yyconst flex_int16_t yy_accept[166] = + { 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 32, 30, ++ 19, 19, 30, 30, 30, 30, 30, 30, 30, 30, ++ 30, 30, 30, 30, 30, 30, 16, 17, 17, 30, ++ 17, 11, 11, 19, 27, 0, 3, 0, 28, 13, ++ 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, ++ 0, 22, 24, 26, 25, 23, 0, 10, 29, 0, ++ 0, 0, 15, 15, 17, 17, 17, 11, 11, 11, ++ 0, 13, 0, 12, 0, 0, 0, 21, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 17, 11, 11, ++ 11, 0, 14, 20, 0, 0, 0, 0, 0, 0, ++ ++ 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 17, 7, 0, 0, 0, ++ 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 4, 18, 0, 0, 5, 2, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 31, 29, 18, 18, 29, 29, 29, 29, 29, 29, +- 29, 29, 29, 29, 29, 29, 29, 29, 15, 16, +- 16, 29, 16, 10, 10, 18, 26, 0, 3, 0, +- 27, 12, 0, 0, 11, 0, 0, 0, 0, 0, +- 0, 0, 21, 23, 25, 24, 22, 0, 9, 28, +- 0, 0, 0, 14, 14, 16, 16, 16, 10, 10, +- 10, 0, 12, 0, 11, 0, 0, 0, 20, 0, +- 0, 0, 0, 0, 0, 0, 0, 16, 10, 10, +- 10, 0, 19, 0, 0, 0, 0, 0, 0, 0, +- +- 0, 0, 16, 13, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 16, 6, 0, 0, 0, 0, 0, +- 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, +- 4, 17, 0, 0, 2, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, +- 0, 0, 5, 8, 0, 0, 0, 0, 7, 0 ++ 0, 0, 1, 0, 0, 0, 0, 6, 9, 0, ++ 0, 0, 0, 8, 0 + } ; + + static yyconst flex_int32_t yy_ec[256] = +@@ -415,9 +416,9 @@ static yyconst flex_int32_t yy_ec[256] = + 22, 22, 22, 22, 24, 22, 22, 25, 22, 22, + 1, 26, 27, 1, 22, 1, 21, 28, 29, 30, + +- 31, 21, 22, 22, 32, 22, 22, 33, 34, 35, +- 36, 37, 22, 38, 39, 40, 41, 42, 22, 25, +- 43, 22, 44, 45, 46, 1, 1, 1, 1, 1, ++ 31, 21, 32, 22, 33, 22, 22, 34, 35, 36, ++ 37, 38, 22, 39, 40, 41, 42, 43, 22, 25, ++ 44, 22, 45, 46, 47, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, +@@ -434,163 +435,165 @@ static yyconst flex_int32_t yy_ec[256] = + 1, 1, 1, 1, 1 + } ; + +-static yyconst flex_int32_t yy_meta[47] = ++static yyconst flex_int32_t yy_meta[48] = + { 0, + 1, 1, 1, 1, 1, 1, 2, 3, 1, 2, + 2, 2, 4, 5, 5, 5, 6, 1, 1, 1, + 7, 8, 8, 8, 8, 1, 1, 7, 7, 7, + 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, +- 8, 8, 8, 3, 1, 1 ++ 8, 8, 8, 8, 3, 1, 4 + } ; + +-static yyconst flex_int16_t yy_base[175] = ++static yyconst flex_int16_t yy_base[180] = + { 0, +- 0, 385, 378, 40, 41, 383, 72, 382, 34, 44, +- 388, 393, 61, 117, 368, 116, 115, 115, 115, 48, +- 367, 107, 368, 339, 127, 120, 0, 147, 393, 0, +- 127, 0, 133, 156, 168, 153, 393, 125, 393, 380, +- 393, 0, 369, 127, 393, 160, 371, 377, 347, 21, +- 343, 346, 393, 393, 393, 393, 393, 359, 393, 393, +- 183, 343, 339, 393, 356, 0, 183, 340, 187, 348, +- 347, 0, 0, 0, 178, 359, 195, 365, 354, 326, +- 332, 325, 334, 328, 204, 326, 331, 324, 393, 335, +- 150, 311, 343, 342, 315, 322, 340, 179, 313, 207, +- +- 319, 316, 317, 393, 337, 333, 305, 302, 311, 301, +- 310, 190, 338, 337, 393, 307, 322, 301, 305, 277, +- 208, 311, 307, 278, 271, 270, 248, 246, 213, 130, +- 393, 393, 263, 235, 207, 221, 218, 229, 213, 213, +- 206, 234, 218, 210, 208, 193, 219, 393, 223, 204, +- 176, 157, 393, 393, 120, 106, 97, 119, 393, 393, +- 245, 251, 259, 263, 267, 273, 280, 284, 292, 300, +- 304, 310, 318, 326 ++ 0, 393, 35, 392, 66, 391, 38, 107, 397, 401, ++ 55, 113, 377, 112, 111, 111, 114, 42, 376, 106, ++ 377, 347, 126, 120, 0, 147, 401, 0, 124, 0, ++ 137, 158, 170, 163, 401, 153, 401, 389, 401, 0, ++ 378, 120, 401, 131, 380, 386, 355, 139, 351, 355, ++ 351, 401, 401, 401, 401, 401, 367, 401, 401, 185, ++ 350, 346, 401, 364, 0, 185, 347, 189, 356, 355, ++ 0, 0, 330, 180, 366, 141, 372, 361, 332, 338, ++ 331, 341, 334, 326, 205, 331, 337, 329, 401, 341, ++ 167, 316, 401, 349, 348, 320, 328, 346, 180, 318, ++ ++ 324, 209, 324, 320, 322, 342, 338, 309, 306, 315, ++ 305, 315, 312, 192, 342, 341, 401, 293, 306, 282, ++ 268, 252, 255, 203, 285, 282, 272, 268, 252, 233, ++ 232, 239, 208, 107, 401, 401, 238, 211, 401, 211, ++ 212, 208, 228, 203, 215, 207, 233, 222, 212, 211, ++ 203, 227, 401, 237, 225, 204, 185, 401, 401, 149, ++ 128, 88, 42, 401, 401, 253, 259, 267, 271, 275, ++ 281, 288, 292, 300, 308, 312, 318, 326, 334 + } ; + +-static yyconst flex_int16_t yy_def[175] = ++static yyconst flex_int16_t yy_def[180] = + { 0, +- 160, 1, 1, 1, 1, 5, 160, 7, 1, 1, +- 160, 160, 160, 160, 160, 161, 162, 163, 160, 160, +- 160, 160, 164, 160, 160, 160, 165, 164, 160, 166, +- 167, 166, 166, 160, 160, 160, 160, 161, 160, 161, +- 160, 168, 160, 163, 160, 163, 169, 170, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 164, 160, 160, +- 160, 160, 160, 160, 164, 166, 167, 166, 160, 160, +- 160, 171, 168, 172, 163, 169, 169, 170, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 166, 160, 160, +- 171, 172, 160, 160, 160, 160, 160, 160, 160, 160, +- +- 160, 160, 166, 160, 160, 160, 160, 160, 160, 160, +- 160, 173, 160, 166, 160, 160, 160, 160, 160, 160, +- 173, 160, 173, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 174, 160, 160, 160, 174, 160, 174, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 0, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160 ++ 165, 1, 1, 3, 165, 5, 1, 1, 165, 165, ++ 165, 165, 165, 166, 167, 168, 165, 165, 165, 165, ++ 169, 165, 165, 165, 170, 169, 165, 171, 172, 171, ++ 171, 165, 165, 165, 165, 166, 165, 166, 165, 173, ++ 165, 168, 165, 168, 174, 175, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 169, 165, 165, 165, ++ 165, 165, 165, 169, 171, 172, 171, 165, 165, 165, ++ 176, 173, 177, 168, 174, 174, 175, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 171, 165, 165, ++ 176, 177, 165, 165, 165, 165, 165, 165, 165, 165, ++ ++ 165, 165, 165, 165, 171, 165, 165, 165, 165, 165, ++ 165, 165, 165, 178, 165, 171, 165, 165, 165, 165, ++ 165, 165, 165, 178, 165, 178, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 179, 165, 165, ++ 165, 179, 165, 179, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 0, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165 + } ; + +-static yyconst flex_int16_t yy_nxt[440] = ++static yyconst flex_int16_t yy_nxt[449] = + { 0, +- 12, 13, 14, 13, 15, 16, 12, 17, 18, 12, +- 12, 12, 19, 12, 12, 12, 12, 20, 21, 22, +- 23, 23, 23, 23, 23, 12, 12, 23, 23, 23, +- 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, +- 23, 23, 23, 12, 24, 12, 25, 34, 35, 35, +- 25, 81, 26, 26, 27, 27, 27, 34, 35, 35, +- 82, 28, 36, 36, 36, 53, 54, 29, 28, 28, +- 28, 28, 12, 13, 14, 13, 15, 16, 30, 17, +- 18, 30, 30, 30, 26, 30, 30, 30, 12, 20, +- 21, 22, 31, 31, 31, 31, 31, 32, 12, 31, +- +- 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, +- 31, 31, 31, 31, 31, 12, 24, 12, 36, 36, +- 36, 39, 41, 45, 47, 56, 57, 48, 61, 47, +- 39, 159, 48, 66, 61, 45, 66, 66, 66, 158, +- 46, 40, 49, 59, 50, 157, 51, 49, 52, 50, +- 40, 63, 46, 52, 36, 36, 36, 156, 43, 62, +- 65, 65, 65, 59, 136, 68, 137, 65, 75, 69, +- 69, 69, 70, 71, 65, 65, 65, 65, 70, 71, +- 72, 69, 69, 69, 61, 46, 45, 155, 154, 66, +- 70, 71, 66, 66, 66, 122, 85, 85, 85, 59, +- +- 69, 69, 69, 46, 77, 100, 109, 93, 100, 70, +- 71, 110, 112, 122, 129, 123, 153, 85, 85, 85, +- 135, 135, 135, 148, 148, 160, 135, 135, 135, 152, +- 142, 142, 142, 123, 143, 142, 142, 142, 151, 143, +- 150, 146, 145, 149, 149, 38, 38, 38, 38, 38, +- 38, 38, 38, 42, 144, 141, 140, 42, 42, 44, +- 44, 44, 44, 44, 44, 44, 44, 58, 58, 58, +- 58, 64, 139, 64, 66, 138, 134, 66, 133, 66, +- 66, 67, 132, 131, 67, 67, 67, 67, 73, 130, +- 73, 73, 76, 76, 76, 76, 76, 76, 76, 76, +- +- 78, 78, 78, 78, 78, 78, 78, 78, 91, 160, +- 91, 92, 129, 92, 92, 128, 92, 92, 121, 121, +- 121, 121, 121, 121, 121, 121, 147, 147, 147, 147, +- 147, 147, 147, 147, 127, 126, 125, 124, 61, 61, +- 120, 119, 118, 117, 116, 115, 47, 114, 110, 113, +- 111, 108, 107, 106, 48, 105, 104, 89, 103, 102, +- 101, 99, 98, 97, 96, 95, 94, 79, 77, 90, +- 89, 88, 59, 87, 86, 59, 84, 83, 80, 79, +- 77, 74, 160, 60, 59, 55, 37, 160, 33, 25, +- 26, 25, 11, 160, 160, 160, 160, 160, 160, 160, +- +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160 ++ 10, 11, 12, 11, 13, 14, 10, 15, 16, 10, ++ 10, 10, 17, 10, 10, 10, 10, 18, 19, 20, ++ 21, 21, 21, 21, 21, 10, 10, 21, 21, 21, ++ 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, ++ 21, 21, 21, 21, 10, 22, 10, 24, 25, 25, ++ 25, 32, 33, 33, 164, 26, 34, 34, 34, 52, ++ 53, 27, 26, 26, 26, 26, 10, 11, 12, 11, ++ 13, 14, 28, 15, 16, 28, 28, 28, 24, 28, ++ 28, 28, 10, 18, 19, 20, 29, 29, 29, 29, ++ 29, 30, 10, 29, 29, 29, 29, 29, 29, 29, ++ ++ 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, ++ 10, 22, 10, 23, 34, 34, 34, 37, 39, 43, ++ 32, 33, 33, 45, 55, 56, 46, 60, 43, 45, ++ 65, 163, 46, 65, 65, 65, 44, 38, 60, 74, ++ 58, 47, 141, 48, 142, 44, 49, 47, 50, 48, ++ 76, 51, 62, 94, 50, 41, 44, 51, 37, 61, ++ 64, 64, 64, 58, 34, 34, 34, 64, 162, 80, ++ 67, 68, 68, 68, 64, 64, 64, 64, 38, 81, ++ 69, 70, 71, 68, 68, 68, 60, 161, 43, 69, ++ 70, 65, 69, 70, 65, 65, 65, 125, 85, 85, ++ ++ 85, 58, 68, 68, 68, 44, 102, 110, 125, 133, ++ 102, 69, 70, 111, 114, 160, 159, 126, 85, 85, ++ 85, 140, 140, 140, 140, 140, 140, 153, 126, 147, ++ 147, 147, 153, 148, 147, 147, 147, 158, 148, 165, ++ 157, 156, 155, 151, 150, 149, 146, 154, 145, 144, ++ 143, 139, 154, 36, 36, 36, 36, 36, 36, 36, ++ 36, 40, 138, 137, 136, 40, 40, 42, 42, 42, ++ 42, 42, 42, 42, 42, 57, 57, 57, 57, 63, ++ 135, 63, 65, 134, 165, 65, 133, 65, 65, 66, ++ 132, 131, 66, 66, 66, 66, 72, 130, 72, 72, ++ ++ 75, 75, 75, 75, 75, 75, 75, 75, 77, 77, ++ 77, 77, 77, 77, 77, 77, 91, 129, 91, 92, ++ 128, 92, 92, 127, 92, 92, 124, 124, 124, 124, ++ 124, 124, 124, 124, 152, 152, 152, 152, 152, 152, ++ 152, 152, 60, 60, 123, 122, 121, 120, 119, 118, ++ 117, 45, 116, 111, 115, 113, 112, 109, 108, 107, ++ 46, 106, 93, 89, 105, 104, 103, 101, 100, 99, ++ 98, 97, 96, 95, 78, 76, 93, 90, 89, 88, ++ 58, 87, 86, 58, 84, 83, 82, 79, 78, 76, ++ 73, 165, 59, 58, 54, 35, 165, 31, 23, 23, ++ ++ 9, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165 + } ; + +-static yyconst flex_int16_t yy_chk[440] = ++static yyconst flex_int16_t yy_chk[449] = + { 0, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, +- 1, 1, 1, 1, 1, 1, 4, 9, 9, 9, +- 10, 50, 4, 5, 5, 5, 5, 10, 10, 10, +- 50, 5, 13, 13, 13, 20, 20, 5, 5, 5, +- 5, 5, 7, 7, 7, 7, 7, 7, 7, 7, +- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +- +- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +- 7, 7, 7, 7, 7, 7, 7, 7, 14, 14, +- 14, 16, 17, 18, 19, 22, 22, 19, 25, 26, +- 38, 158, 26, 31, 33, 44, 31, 31, 31, 157, +- 18, 16, 19, 31, 19, 156, 19, 26, 19, 26, +- 38, 26, 44, 26, 36, 36, 36, 155, 17, 25, +- 28, 28, 28, 28, 130, 33, 130, 28, 46, 34, +- 34, 34, 91, 91, 28, 28, 28, 28, 34, 34, +- 34, 35, 35, 35, 61, 46, 75, 152, 151, 67, +- 35, 35, 67, 67, 67, 112, 61, 61, 61, 67, +- +- 69, 69, 69, 75, 77, 85, 98, 77, 100, 69, +- 69, 98, 100, 121, 129, 112, 150, 85, 85, 85, +- 135, 135, 135, 143, 147, 149, 129, 129, 129, 146, +- 138, 138, 138, 121, 138, 142, 142, 142, 145, 142, +- 144, 141, 140, 143, 147, 161, 161, 161, 161, 161, +- 161, 161, 161, 162, 139, 137, 136, 162, 162, 163, +- 163, 163, 163, 163, 163, 163, 163, 164, 164, 164, +- 164, 165, 134, 165, 166, 133, 128, 166, 127, 166, +- 166, 167, 126, 125, 167, 167, 167, 167, 168, 124, +- 168, 168, 169, 169, 169, 169, 169, 169, 169, 169, +- +- 170, 170, 170, 170, 170, 170, 170, 170, 171, 123, +- 171, 172, 122, 172, 172, 120, 172, 172, 173, 173, +- 173, 173, 173, 173, 173, 173, 174, 174, 174, 174, +- 174, 174, 174, 174, 119, 118, 117, 116, 114, 113, +- 111, 110, 109, 108, 107, 106, 105, 103, 102, 101, +- 99, 97, 96, 95, 94, 93, 92, 90, 88, 87, +- 86, 84, 83, 82, 81, 80, 79, 78, 76, 71, +- 70, 68, 65, 63, 62, 58, 52, 51, 49, 48, +- 47, 43, 40, 24, 23, 21, 15, 11, 8, 6, +- 3, 2, 160, 160, 160, 160, 160, 160, 160, 160, +- +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160 ++ 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, ++ 3, 7, 7, 7, 163, 3, 11, 11, 11, 18, ++ 18, 3, 3, 3, 3, 3, 5, 5, 5, 5, ++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ ++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ 5, 5, 5, 8, 12, 12, 12, 14, 15, 16, ++ 8, 8, 8, 17, 20, 20, 17, 23, 42, 24, ++ 29, 162, 24, 29, 29, 29, 16, 14, 31, 44, ++ 29, 17, 134, 17, 134, 42, 17, 24, 17, 24, ++ 76, 17, 24, 76, 24, 15, 44, 24, 36, 23, ++ 26, 26, 26, 26, 34, 34, 34, 26, 161, 48, ++ 31, 32, 32, 32, 26, 26, 26, 26, 36, 48, ++ 32, 32, 32, 33, 33, 33, 60, 160, 74, 91, ++ 91, 66, 33, 33, 66, 66, 66, 114, 60, 60, ++ ++ 60, 66, 68, 68, 68, 74, 85, 99, 124, 133, ++ 102, 68, 68, 99, 102, 157, 156, 114, 85, 85, ++ 85, 133, 133, 133, 140, 140, 140, 148, 124, 143, ++ 143, 143, 152, 143, 147, 147, 147, 155, 147, 154, ++ 151, 150, 149, 146, 145, 144, 142, 148, 141, 138, ++ 137, 132, 152, 166, 166, 166, 166, 166, 166, 166, ++ 166, 167, 131, 130, 129, 167, 167, 168, 168, 168, ++ 168, 168, 168, 168, 168, 169, 169, 169, 169, 170, ++ 128, 170, 171, 127, 126, 171, 125, 171, 171, 172, ++ 123, 122, 172, 172, 172, 172, 173, 121, 173, 173, ++ ++ 174, 174, 174, 174, 174, 174, 174, 174, 175, 175, ++ 175, 175, 175, 175, 175, 175, 176, 120, 176, 177, ++ 119, 177, 177, 118, 177, 177, 178, 178, 178, 178, ++ 178, 178, 178, 178, 179, 179, 179, 179, 179, 179, ++ 179, 179, 116, 115, 113, 112, 111, 110, 109, 108, ++ 107, 106, 105, 104, 103, 101, 100, 98, 97, 96, ++ 95, 94, 92, 90, 88, 87, 86, 84, 83, 82, ++ 81, 80, 79, 78, 77, 75, 73, 70, 69, 67, ++ 64, 62, 61, 57, 51, 50, 49, 47, 46, 45, ++ 41, 38, 22, 21, 19, 13, 9, 6, 4, 2, ++ ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165 + } ; + + static yy_state_type yy_last_accepting_state; +@@ -631,13 +634,13 @@ char *yytext; + + + +- +-#line 38 "dtc-lexer.l" ++#line 37 "dtc-lexer.l" + #include "dtc.h" + #include "srcpos.h" + #include "dtc-parser.tab.h" + + YYLTYPE yylloc; ++extern bool treesource_error; + + /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ + #define YY_USER_ACTION \ +@@ -659,14 +662,14 @@ static int dts_version = 1; + BEGIN(V1); \ + + static void push_input_file(const char *filename); +-static int pop_input_file(void); +-#line 664 "dtc-lexer.lex.c" ++static bool pop_input_file(void); ++static void lexical_error(const char *fmt, ...); ++#line 668 "dtc-lexer.lex.c" + + #define INITIAL 0 +-#define INCLUDE 1 +-#define BYTESTRING 2 +-#define PROPNODENAME 3 +-#define V1 4 ++#define BYTESTRING 1 ++#define PROPNODENAME 2 ++#define V1 3 + + #ifndef YY_NO_UNISTD_H + /* Special case for "unistd.h", since it is non-ANSI. We include it way +@@ -852,9 +855,9 @@ YY_DECL + register char *yy_cp, *yy_bp; + register int yy_act; + +-#line 67 "dtc-lexer.l" ++#line 68 "dtc-lexer.l" + +-#line 858 "dtc-lexer.lex.c" ++#line 861 "dtc-lexer.lex.c" + + if ( !(yy_init) ) + { +@@ -908,13 +911,13 @@ yy_match: + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 161 ) ++ if ( yy_current_state >= 166 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; + ++yy_cp; + } +- while ( yy_current_state != 160 ); ++ while ( yy_current_state != 165 ); + yy_cp = (yy_last_accepting_cpos); + yy_current_state = (yy_last_accepting_state); + +@@ -937,7 +940,7 @@ do_action: /* This label is used only to + case 1: + /* rule 1 can match eol */ + YY_RULE_SETUP +-#line 68 "dtc-lexer.l" ++#line 69 "dtc-lexer.l" + { + char *name = strchr(yytext, '\"') + 1; + yytext[yyleng-1] = '\0'; +@@ -947,16 +950,16 @@ YY_RULE_SETUP + case 2: + /* rule 2 can match eol */ + YY_RULE_SETUP +-#line 74 "dtc-lexer.l" ++#line 75 "dtc-lexer.l" + { + char *line, *tmp, *fn; + /* skip text before line # */ + line = yytext; +- while (!isdigit(*line)) ++ while (!isdigit((unsigned char)*line)) + line++; + /* skip digits in line # */ + tmp = line; +- while (!isspace(*tmp)) ++ while (!isspace((unsigned char)*tmp)) + tmp++; + /* "NULL"-terminate line # */ + *tmp = '\0'; +@@ -970,11 +973,10 @@ YY_RULE_SETUP + } + YY_BREAK + case YY_STATE_EOF(INITIAL): +-case YY_STATE_EOF(INCLUDE): + case YY_STATE_EOF(BYTESTRING): + case YY_STATE_EOF(PROPNODENAME): + case YY_STATE_EOF(V1): +-#line 95 "dtc-lexer.l" ++#line 96 "dtc-lexer.l" + { + if (!pop_input_file()) { + yyterminate(); +@@ -984,7 +986,7 @@ case YY_STATE_EOF(V1): + case 3: + /* rule 3 can match eol */ + YY_RULE_SETUP +-#line 101 "dtc-lexer.l" ++#line 102 "dtc-lexer.l" + { + DPRINT("String: %s\n", yytext); + yylval.data = data_copy_escape_string(yytext+1, +@@ -994,7 +996,7 @@ YY_RULE_SETUP + YY_BREAK + case 4: + YY_RULE_SETUP +-#line 108 "dtc-lexer.l" ++#line 109 "dtc-lexer.l" + { + DPRINT("Keyword: /dts-v1/\n"); + dts_version = 1; +@@ -1004,25 +1006,33 @@ YY_RULE_SETUP + YY_BREAK + case 5: + YY_RULE_SETUP +-#line 115 "dtc-lexer.l" ++#line 116 "dtc-lexer.l" ++{ ++ DPRINT("Keyword: /plugin/\n"); ++ return DT_PLUGIN; ++ } ++ YY_BREAK ++case 6: ++YY_RULE_SETUP ++#line 121 "dtc-lexer.l" + { + DPRINT("Keyword: /memreserve/\n"); + BEGIN_DEFAULT(); + return DT_MEMRESERVE; + } + YY_BREAK +-case 6: ++case 7: + YY_RULE_SETUP +-#line 121 "dtc-lexer.l" ++#line 127 "dtc-lexer.l" + { + DPRINT("Keyword: /bits/\n"); + BEGIN_DEFAULT(); + return DT_BITS; + } + YY_BREAK +-case 7: ++case 8: + YY_RULE_SETUP +-#line 127 "dtc-lexer.l" ++#line 133 "dtc-lexer.l" + { + DPRINT("Keyword: /delete-property/\n"); + DPRINT("\n"); +@@ -1030,9 +1040,9 @@ YY_RULE_SETUP + return DT_DEL_PROP; + } + YY_BREAK +-case 8: ++case 9: + YY_RULE_SETUP +-#line 134 "dtc-lexer.l" ++#line 140 "dtc-lexer.l" + { + DPRINT("Keyword: /delete-node/\n"); + DPRINT("\n"); +@@ -1040,9 +1050,9 @@ YY_RULE_SETUP + return DT_DEL_NODE; + } + YY_BREAK +-case 9: ++case 10: + YY_RULE_SETUP +-#line 141 "dtc-lexer.l" ++#line 147 "dtc-lexer.l" + { + DPRINT("Label: %s\n", yytext); + yylval.labelref = xstrdup(yytext); +@@ -1050,38 +1060,65 @@ YY_RULE_SETUP + return DT_LABEL; + } + YY_BREAK +-case 10: ++case 11: + YY_RULE_SETUP +-#line 148 "dtc-lexer.l" ++#line 154 "dtc-lexer.l" + { +- yylval.literal = xstrdup(yytext); +- DPRINT("Literal: '%s'\n", yylval.literal); ++ char *e; ++ DPRINT("Integer Literal: '%s'\n", yytext); ++ ++ errno = 0; ++ yylval.integer = strtoull(yytext, &e, 0); ++ ++ assert(!(*e) || !e[strspn(e, "UL")]); ++ ++ if (errno == ERANGE) ++ lexical_error("Integer literal '%s' out of range", ++ yytext); ++ else ++ /* ERANGE is the only strtoull error triggerable ++ * by strings matching the pattern */ ++ assert(errno == 0); + return DT_LITERAL; + } + YY_BREAK +-case 11: +-/* rule 11 can match eol */ ++case 12: ++/* rule 12 can match eol */ + YY_RULE_SETUP +-#line 154 "dtc-lexer.l" ++#line 173 "dtc-lexer.l" + { +- yytext[yyleng-1] = '\0'; +- yylval.literal = xstrdup(yytext+1); +- DPRINT("Character literal: %s\n", yylval.literal); ++ struct data d; ++ DPRINT("Character literal: %s\n", yytext); ++ ++ d = data_copy_escape_string(yytext+1, yyleng-2); ++ if (d.len == 1) { ++ lexical_error("Empty character literal"); ++ yylval.integer = 0; ++ return DT_CHAR_LITERAL; ++ } ++ ++ yylval.integer = (unsigned char)d.val[0]; ++ ++ if (d.len > 2) ++ lexical_error("Character literal has %d" ++ " characters instead of 1", ++ d.len - 1); ++ + return DT_CHAR_LITERAL; + } + YY_BREAK +-case 12: ++case 13: + YY_RULE_SETUP +-#line 161 "dtc-lexer.l" ++#line 194 "dtc-lexer.l" + { /* label reference */ + DPRINT("Ref: %s\n", yytext+1); + yylval.labelref = xstrdup(yytext+1); + return DT_REF; + } + YY_BREAK +-case 13: ++case 14: + YY_RULE_SETUP +-#line 167 "dtc-lexer.l" ++#line 200 "dtc-lexer.l" + { /* new-style path reference */ + yytext[yyleng-1] = '\0'; + DPRINT("Ref: %s\n", yytext+2); +@@ -1089,27 +1126,27 @@ YY_RULE_SETUP + return DT_REF; + } + YY_BREAK +-case 14: ++case 15: + YY_RULE_SETUP +-#line 174 "dtc-lexer.l" ++#line 207 "dtc-lexer.l" + { + yylval.byte = strtol(yytext, NULL, 16); + DPRINT("Byte: %02x\n", (int)yylval.byte); + return DT_BYTE; + } + YY_BREAK +-case 15: ++case 16: + YY_RULE_SETUP +-#line 180 "dtc-lexer.l" ++#line 213 "dtc-lexer.l" + { + DPRINT("/BYTESTRING\n"); + BEGIN_DEFAULT(); + return ']'; + } + YY_BREAK +-case 16: ++case 17: + YY_RULE_SETUP +-#line 186 "dtc-lexer.l" ++#line 219 "dtc-lexer.l" + { + DPRINT("PropNodeName: %s\n", yytext); + yylval.propnodename = xstrdup((yytext[0] == '\\') ? +@@ -1118,75 +1155,75 @@ YY_RULE_SETUP + return DT_PROPNODENAME; + } + YY_BREAK +-case 17: ++case 18: + YY_RULE_SETUP +-#line 194 "dtc-lexer.l" ++#line 227 "dtc-lexer.l" + { + DPRINT("Binary Include\n"); + return DT_INCBIN; + } + YY_BREAK +-case 18: +-/* rule 18 can match eol */ +-YY_RULE_SETUP +-#line 199 "dtc-lexer.l" +-/* eat whitespace */ +- YY_BREAK + case 19: + /* rule 19 can match eol */ + YY_RULE_SETUP +-#line 200 "dtc-lexer.l" +-/* eat C-style comments */ ++#line 232 "dtc-lexer.l" ++/* eat whitespace */ + YY_BREAK + case 20: + /* rule 20 can match eol */ + YY_RULE_SETUP +-#line 201 "dtc-lexer.l" +-/* eat C++-style comments */ ++#line 233 "dtc-lexer.l" ++/* eat C-style comments */ + YY_BREAK + case 21: ++/* rule 21 can match eol */ + YY_RULE_SETUP +-#line 203 "dtc-lexer.l" +-{ return DT_LSHIFT; }; ++#line 234 "dtc-lexer.l" ++/* eat C++-style comments */ + YY_BREAK + case 22: + YY_RULE_SETUP +-#line 204 "dtc-lexer.l" +-{ return DT_RSHIFT; }; ++#line 236 "dtc-lexer.l" ++{ return DT_LSHIFT; }; + YY_BREAK + case 23: + YY_RULE_SETUP +-#line 205 "dtc-lexer.l" +-{ return DT_LE; }; ++#line 237 "dtc-lexer.l" ++{ return DT_RSHIFT; }; + YY_BREAK + case 24: + YY_RULE_SETUP +-#line 206 "dtc-lexer.l" +-{ return DT_GE; }; ++#line 238 "dtc-lexer.l" ++{ return DT_LE; }; + YY_BREAK + case 25: + YY_RULE_SETUP +-#line 207 "dtc-lexer.l" +-{ return DT_EQ; }; ++#line 239 "dtc-lexer.l" ++{ return DT_GE; }; + YY_BREAK + case 26: + YY_RULE_SETUP +-#line 208 "dtc-lexer.l" +-{ return DT_NE; }; ++#line 240 "dtc-lexer.l" ++{ return DT_EQ; }; + YY_BREAK + case 27: + YY_RULE_SETUP +-#line 209 "dtc-lexer.l" +-{ return DT_AND; }; ++#line 241 "dtc-lexer.l" ++{ return DT_NE; }; + YY_BREAK + case 28: + YY_RULE_SETUP +-#line 210 "dtc-lexer.l" +-{ return DT_OR; }; ++#line 242 "dtc-lexer.l" ++{ return DT_AND; }; + YY_BREAK + case 29: + YY_RULE_SETUP +-#line 212 "dtc-lexer.l" ++#line 243 "dtc-lexer.l" ++{ return DT_OR; }; ++ YY_BREAK ++case 30: ++YY_RULE_SETUP ++#line 245 "dtc-lexer.l" + { + DPRINT("Char: %c (\\x%02x)\n", yytext[0], + (unsigned)yytext[0]); +@@ -1202,12 +1239,12 @@ YY_RULE_SETUP + return yytext[0]; + } + YY_BREAK +-case 30: ++case 31: + YY_RULE_SETUP +-#line 227 "dtc-lexer.l" ++#line 260 "dtc-lexer.l" + ECHO; + YY_BREAK +-#line 1211 "dtc-lexer.lex.c" ++#line 1248 "dtc-lexer.lex.c" + + case YY_END_OF_BUFFER: + { +@@ -1499,7 +1536,7 @@ static int yy_get_next_buffer (void) + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 161 ) ++ if ( yy_current_state >= 166 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; +@@ -1527,11 +1564,11 @@ static int yy_get_next_buffer (void) + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 161 ) ++ if ( yy_current_state >= 166 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; +- yy_is_jam = (yy_current_state == 160); ++ yy_is_jam = (yy_current_state == 165); + + return yy_is_jam ? 0 : yy_current_state; + } +@@ -2166,7 +2203,7 @@ void yyfree (void * ptr ) + + #define YYTABLES_NAME "yytables" + +-#line 227 "dtc-lexer.l" ++#line 260 "dtc-lexer.l" + + + +@@ -2182,14 +2219,25 @@ static void push_input_file(const char * + } + + +-static int pop_input_file(void) ++static bool pop_input_file(void) + { + if (srcfile_pop() == 0) +- return 0; ++ return false; + + yypop_buffer_state(); + yyin = current_srcfile->f; + +- return 1; ++ return true; ++} ++ ++static void lexical_error(const char *fmt, ...) ++{ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ srcpos_verror(&yylloc, "Lexical error", fmt, ap); ++ va_end(ap); ++ ++ treesource_error = true; + } + +--- a/scripts/dtc/dtc-parser.tab.c_shipped ++++ b/scripts/dtc/dtc-parser.tab.c_shipped +@@ -1,19 +1,19 @@ +-/* A Bison parser, made by GNU Bison 2.7.12-4996. */ ++/* A Bison parser, made by GNU Bison 3.0.2. */ + + /* Bison implementation for Yacc-like parsers in C +- +- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. +- ++ ++ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. ++ + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. +- ++ + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. +- ++ + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +@@ -26,7 +26,7 @@ + special exception, which will cause the skeleton and the resulting + Bison output files to be licensed under the GNU General Public + License without this special exception. +- ++ + This special exception was added by the Free Software Foundation in + version 2.2 of Bison. */ + +@@ -44,7 +44,7 @@ + #define YYBISON 1 + + /* Bison version. */ +-#define YYBISON_VERSION "2.7.12-4996" ++#define YYBISON_VERSION "3.0.2" + + /* Skeleton name. */ + #define YYSKELETON_NAME "yacc.c" +@@ -62,34 +62,32 @@ + + + /* Copy the first part of user declarations. */ +-/* Line 371 of yacc.c */ +-#line 21 "dtc-parser.y" ++#line 20 "dtc-parser.y" /* yacc.c:339 */ + + #include ++#include + + #include "dtc.h" + #include "srcpos.h" + +-YYLTYPE yylloc; +- + extern int yylex(void); +-extern void print_error(char const *fmt, ...); + extern void yyerror(char const *s); ++#define ERROR(loc, ...) \ ++ do { \ ++ srcpos_error((loc), "Error", __VA_ARGS__); \ ++ treesource_error = true; \ ++ } while (0) + + extern struct boot_info *the_boot_info; +-extern int treesource_error; +- +-static unsigned long long eval_literal(const char *s, int base, int bits); +-static unsigned char eval_char_literal(const char *s); ++extern bool treesource_error; + +-/* Line 371 of yacc.c */ +-#line 87 "dtc-parser.tab.c" ++#line 85 "dtc-parser.tab.c" /* yacc.c:339 */ + +-# ifndef YY_NULL ++# ifndef YY_NULLPTR + # if defined __cplusplus && 201103L <= __cplusplus +-# define YY_NULL nullptr ++# define YY_NULLPTR nullptr + # else +-# define YY_NULL 0 ++# define YY_NULLPTR 0 + # endif + # endif + +@@ -105,7 +103,7 @@ static unsigned char eval_char_literal(c + by #include "dtc-parser.tab.h". */ + #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED + # define YY_YY_DTC_PARSER_TAB_H_INCLUDED +-/* Enabling traces. */ ++/* Debug traces. */ + #ifndef YYDEBUG + # define YYDEBUG 0 + #endif +@@ -113,48 +111,45 @@ static unsigned char eval_char_literal(c + extern int yydebug; + #endif + +-/* Tokens. */ ++/* Token type. */ + #ifndef YYTOKENTYPE + # define YYTOKENTYPE +- /* Put the tokens into the symbol table, so that GDB and other debuggers +- know about them. */ +- enum yytokentype { +- DT_V1 = 258, +- DT_MEMRESERVE = 259, +- DT_LSHIFT = 260, +- DT_RSHIFT = 261, +- DT_LE = 262, +- DT_GE = 263, +- DT_EQ = 264, +- DT_NE = 265, +- DT_AND = 266, +- DT_OR = 267, +- DT_BITS = 268, +- DT_DEL_PROP = 269, +- DT_DEL_NODE = 270, +- DT_PROPNODENAME = 271, +- DT_LITERAL = 272, +- DT_CHAR_LITERAL = 273, +- DT_BASE = 274, +- DT_BYTE = 275, +- DT_STRING = 276, +- DT_LABEL = 277, +- DT_REF = 278, +- DT_INCBIN = 279 +- }; ++ enum yytokentype ++ { ++ DT_V1 = 258, ++ DT_PLUGIN = 259, ++ DT_MEMRESERVE = 260, ++ DT_LSHIFT = 261, ++ DT_RSHIFT = 262, ++ DT_LE = 263, ++ DT_GE = 264, ++ DT_EQ = 265, ++ DT_NE = 266, ++ DT_AND = 267, ++ DT_OR = 268, ++ DT_BITS = 269, ++ DT_DEL_PROP = 270, ++ DT_DEL_NODE = 271, ++ DT_PROPNODENAME = 272, ++ DT_LITERAL = 273, ++ DT_CHAR_LITERAL = 274, ++ DT_BYTE = 275, ++ DT_STRING = 276, ++ DT_LABEL = 277, ++ DT_REF = 278, ++ DT_INCBIN = 279 ++ }; + #endif + +- ++/* Value type. */ + #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED +-typedef union YYSTYPE ++typedef union YYSTYPE YYSTYPE; ++union YYSTYPE + { +-/* Line 387 of yacc.c */ +-#line 40 "dtc-parser.y" ++#line 39 "dtc-parser.y" /* yacc.c:355 */ + + char *propnodename; +- char *literal; + char *labelref; +- unsigned int cbase; + uint8_t byte; + struct data data; + +@@ -169,38 +164,38 @@ typedef union YYSTYPE + struct node *nodelist; + struct reserve_info *re; + uint64_t integer; ++ int is_plugin; + +- +-/* Line 387 of yacc.c */ +-#line 176 "dtc-parser.tab.c" +-} YYSTYPE; ++#line 170 "dtc-parser.tab.c" /* yacc.c:355 */ ++}; + # define YYSTYPE_IS_TRIVIAL 1 +-# define yystype YYSTYPE /* obsolescent; will be withdrawn */ + # define YYSTYPE_IS_DECLARED 1 + #endif + +-extern YYSTYPE yylval; +- +-#ifdef YYPARSE_PARAM +-#if defined __STDC__ || defined __cplusplus +-int yyparse (void *YYPARSE_PARAM); +-#else +-int yyparse (); ++/* Location type. */ ++#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED ++typedef struct YYLTYPE YYLTYPE; ++struct YYLTYPE ++{ ++ int first_line; ++ int first_column; ++ int last_line; ++ int last_column; ++}; ++# define YYLTYPE_IS_DECLARED 1 ++# define YYLTYPE_IS_TRIVIAL 1 + #endif +-#else /* ! YYPARSE_PARAM */ +-#if defined __STDC__ || defined __cplusplus ++ ++ ++extern YYSTYPE yylval; ++extern YYLTYPE yylloc; + int yyparse (void); +-#else +-int yyparse (); +-#endif +-#endif /* ! YYPARSE_PARAM */ + + #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */ + + /* Copy the second part of user declarations. */ + +-/* Line 390 of yacc.c */ +-#line 204 "dtc-parser.tab.c" ++#line 199 "dtc-parser.tab.c" /* yacc.c:358 */ + + #ifdef short + # undef short +@@ -214,11 +209,8 @@ typedef unsigned char yytype_uint8; + + #ifdef YYTYPE_INT8 + typedef YYTYPE_INT8 yytype_int8; +-#elif (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-typedef signed char yytype_int8; + #else +-typedef short int yytype_int8; ++typedef signed char yytype_int8; + #endif + + #ifdef YYTYPE_UINT16 +@@ -238,8 +230,7 @@ typedef short int yytype_int16; + # define YYSIZE_T __SIZE_TYPE__ + # elif defined size_t + # define YYSIZE_T size_t +-# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) ++# elif ! defined YYSIZE_T + # include /* INFRINGES ON USER NAME SPACE */ + # define YYSIZE_T size_t + # else +@@ -261,11 +252,30 @@ typedef short int yytype_int16; + # endif + #endif + +-#ifndef __attribute__ +-/* This feature is available in gcc versions 2.5 and later. */ +-# if (! defined __GNUC__ || __GNUC__ < 2 \ +- || (__GNUC__ == 2 && __GNUC_MINOR__ < 5)) +-# define __attribute__(Spec) /* empty */ ++#ifndef YY_ATTRIBUTE ++# if (defined __GNUC__ \ ++ && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \ ++ || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C ++# define YY_ATTRIBUTE(Spec) __attribute__(Spec) ++# else ++# define YY_ATTRIBUTE(Spec) /* empty */ ++# endif ++#endif ++ ++#ifndef YY_ATTRIBUTE_PURE ++# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__)) ++#endif ++ ++#ifndef YY_ATTRIBUTE_UNUSED ++# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__)) ++#endif ++ ++#if !defined _Noreturn \ ++ && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112) ++# if defined _MSC_VER && 1200 <= _MSC_VER ++# define _Noreturn __declspec (noreturn) ++# else ++# define _Noreturn YY_ATTRIBUTE ((__noreturn__)) + # endif + #endif + +@@ -276,24 +286,25 @@ typedef short int yytype_int16; + # define YYUSE(E) /* empty */ + #endif + +- +-/* Identity function, used to suppress warnings about constant conditions. */ +-#ifndef lint +-# define YYID(N) (N) +-#else +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static int +-YYID (int yyi) ++#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ ++/* Suppress an incorrect diagnostic about yylval being uninitialized. */ ++# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ ++ _Pragma ("GCC diagnostic push") \ ++ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\ ++ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") ++# define YY_IGNORE_MAYBE_UNINITIALIZED_END \ ++ _Pragma ("GCC diagnostic pop") + #else +-static int +-YYID (yyi) +- int yyi; ++# define YY_INITIAL_VALUE(Value) Value + #endif +-{ +- return yyi; +-} ++#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN ++# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN ++# define YY_IGNORE_MAYBE_UNINITIALIZED_END + #endif ++#ifndef YY_INITIAL_VALUE ++# define YY_INITIAL_VALUE(Value) /* Nothing. */ ++#endif ++ + + #if ! defined yyoverflow || YYERROR_VERBOSE + +@@ -312,8 +323,7 @@ YYID (yyi) + # define alloca _alloca + # else + # define YYSTACK_ALLOC alloca +-# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) ++# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS + # include /* INFRINGES ON USER NAME SPACE */ + /* Use EXIT_SUCCESS as a witness for stdlib.h. */ + # ifndef EXIT_SUCCESS +@@ -325,8 +335,8 @@ YYID (yyi) + # endif + + # ifdef YYSTACK_ALLOC +- /* Pacify GCC's `empty if-body' warning. */ +-# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0)) ++ /* Pacify GCC's 'empty if-body' warning. */ ++# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0) + # ifndef YYSTACK_ALLOC_MAXIMUM + /* The OS might guarantee only one guard page at the bottom of the stack, + and a page size can be as small as 4096 bytes. So we cannot safely +@@ -342,7 +352,7 @@ YYID (yyi) + # endif + # if (defined __cplusplus && ! defined EXIT_SUCCESS \ + && ! ((defined YYMALLOC || defined malloc) \ +- && (defined YYFREE || defined free))) ++ && (defined YYFREE || defined free))) + # include /* INFRINGES ON USER NAME SPACE */ + # ifndef EXIT_SUCCESS + # define EXIT_SUCCESS 0 +@@ -350,15 +360,13 @@ YYID (yyi) + # endif + # ifndef YYMALLOC + # define YYMALLOC malloc +-# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) ++# if ! defined malloc && ! defined EXIT_SUCCESS + void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ + # endif + # endif + # ifndef YYFREE + # define YYFREE free +-# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) ++# if ! defined free && ! defined EXIT_SUCCESS + void free (void *); /* INFRINGES ON USER NAME SPACE */ + # endif + # endif +@@ -368,13 +376,15 @@ void free (void *); /* INFRINGES ON USER + + #if (! defined yyoverflow \ + && (! defined __cplusplus \ +- || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) ++ || (defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL \ ++ && defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) + + /* A type that is properly aligned for any stack member. */ + union yyalloc + { + yytype_int16 yyss_alloc; + YYSTYPE yyvs_alloc; ++ YYLTYPE yyls_alloc; + }; + + /* The size of the maximum gap between one aligned stack and the next. */ +@@ -383,8 +393,8 @@ union yyalloc + /* The size of an array large to enough to hold all stacks, each with + N elements. */ + # define YYSTACK_BYTES(N) \ +- ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \ +- + YYSTACK_GAP_MAXIMUM) ++ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE) + sizeof (YYLTYPE)) \ ++ + 2 * YYSTACK_GAP_MAXIMUM) + + # define YYCOPY_NEEDED 1 + +@@ -393,16 +403,16 @@ union yyalloc + elements in the stack, and YYPTR gives the new location of the + stack. Advance YYPTR to a properly aligned location for the next + stack. */ +-# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ +- do \ +- { \ +- YYSIZE_T yynewbytes; \ +- YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ +- Stack = &yyptr->Stack_alloc; \ +- yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ +- yyptr += yynewbytes / sizeof (*yyptr); \ +- } \ +- while (YYID (0)) ++# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ ++ do \ ++ { \ ++ YYSIZE_T yynewbytes; \ ++ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ ++ Stack = &yyptr->Stack_alloc; \ ++ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ ++ yyptr += yynewbytes / sizeof (*yyptr); \ ++ } \ ++ while (0) + + #endif + +@@ -421,7 +431,7 @@ union yyalloc + for (yyi = 0; yyi < (Count); yyi++) \ + (Dst)[yyi] = (Src)[yyi]; \ + } \ +- while (YYID (0)) ++ while (0) + # endif + # endif + #endif /* !YYCOPY_NEEDED */ +@@ -429,25 +439,27 @@ union yyalloc + /* YYFINAL -- State number of the termination state. */ + #define YYFINAL 4 + /* YYLAST -- Last index in YYTABLE. */ +-#define YYLAST 133 ++#define YYLAST 135 + + /* YYNTOKENS -- Number of terminals. */ + #define YYNTOKENS 48 + /* YYNNTS -- Number of nonterminals. */ +-#define YYNNTS 28 ++#define YYNNTS 29 + /* YYNRULES -- Number of rules. */ +-#define YYNRULES 79 +-/* YYNRULES -- Number of states. */ +-#define YYNSTATES 141 ++#define YYNRULES 81 ++/* YYNSTATES -- Number of states. */ ++#define YYNSTATES 144 + +-/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ ++/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned ++ by yylex, with out-of-bounds checking. */ + #define YYUNDEFTOK 2 + #define YYMAXUTOK 279 + +-#define YYTRANSLATE(YYX) \ ++#define YYTRANSLATE(YYX) \ + ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) + +-/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */ ++/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM ++ as returned by yylex, without out-of-bounds checking. */ + static const yytype_uint8 yytranslate[] = + { + 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, +@@ -481,63 +493,18 @@ static const yytype_uint8 yytranslate[] + }; + + #if YYDEBUG +-/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in +- YYRHS. */ +-static const yytype_uint16 yyprhs[] = +-{ +- 0, 0, 3, 8, 9, 12, 17, 20, 23, 27, +- 31, 36, 42, 43, 46, 51, 54, 58, 61, 64, +- 68, 73, 76, 86, 92, 95, 96, 99, 102, 106, +- 108, 111, 114, 117, 119, 121, 125, 127, 129, 135, +- 137, 141, 143, 147, 149, 153, 155, 159, 161, 165, +- 167, 171, 175, 177, 181, 185, 189, 193, 197, 201, +- 203, 207, 211, 213, 217, 221, 225, 227, 229, 232, +- 235, 238, 239, 242, 245, 246, 249, 252, 255, 259 +-}; +- +-/* YYRHS -- A `-1'-separated list of the rules' RHS. */ +-static const yytype_int8 yyrhs[] = +-{ +- 49, 0, -1, 3, 25, 50, 52, -1, -1, 51, +- 50, -1, 4, 59, 59, 25, -1, 22, 51, -1, +- 26, 53, -1, 52, 26, 53, -1, 52, 23, 53, +- -1, 52, 15, 23, 25, -1, 27, 54, 74, 28, +- 25, -1, -1, 54, 55, -1, 16, 29, 56, 25, +- -1, 16, 25, -1, 14, 16, 25, -1, 22, 55, +- -1, 57, 21, -1, 57, 58, 30, -1, 57, 31, +- 73, 32, -1, 57, 23, -1, 57, 24, 33, 21, +- 34, 59, 34, 59, 35, -1, 57, 24, 33, 21, +- 35, -1, 56, 22, -1, -1, 56, 34, -1, 57, +- 22, -1, 13, 17, 36, -1, 36, -1, 58, 59, +- -1, 58, 23, -1, 58, 22, -1, 17, -1, 18, +- -1, 33, 60, 35, -1, 61, -1, 62, -1, 62, +- 37, 60, 38, 61, -1, 63, -1, 62, 12, 63, +- -1, 64, -1, 63, 11, 64, -1, 65, -1, 64, +- 39, 65, -1, 66, -1, 65, 40, 66, -1, 67, +- -1, 66, 41, 67, -1, 68, -1, 67, 9, 68, +- -1, 67, 10, 68, -1, 69, -1, 68, 36, 69, +- -1, 68, 30, 69, -1, 68, 7, 69, -1, 68, +- 8, 69, -1, 69, 5, 70, -1, 69, 6, 70, +- -1, 70, -1, 70, 42, 71, -1, 70, 43, 71, +- -1, 71, -1, 71, 44, 72, -1, 71, 26, 72, +- -1, 71, 45, 72, -1, 72, -1, 59, -1, 43, +- 72, -1, 46, 72, -1, 47, 72, -1, -1, 73, +- 20, -1, 73, 22, -1, -1, 75, 74, -1, 75, +- 55, -1, 16, 53, -1, 15, 16, 25, -1, 22, +- 75, -1 +-}; +- +-/* YYRLINE[YYN] -- source line where rule number YYN was defined. */ ++ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ + static const yytype_uint16 yyrline[] = + { +- 0, 109, 109, 118, 121, 128, 132, 140, 144, 148, +- 158, 172, 180, 183, 190, 194, 198, 202, 210, 214, +- 218, 222, 226, 243, 253, 261, 264, 268, 275, 290, +- 295, 315, 329, 336, 340, 344, 351, 355, 356, 360, +- 361, 365, 366, 370, 371, 375, 376, 380, 381, 385, +- 386, 387, 391, 392, 393, 394, 395, 399, 400, 401, +- 405, 406, 407, 411, 412, 413, 414, 418, 419, 420, +- 421, 426, 429, 433, 441, 444, 448, 456, 460, 464 ++ 0, 108, 108, 119, 122, 130, 133, 140, 144, 152, ++ 156, 160, 170, 185, 193, 196, 203, 207, 211, 215, ++ 223, 227, 231, 235, 239, 255, 265, 273, 276, 280, ++ 287, 303, 308, 327, 341, 348, 349, 350, 357, 361, ++ 362, 366, 367, 371, 372, 376, 377, 381, 382, 386, ++ 387, 391, 392, 393, 397, 398, 399, 400, 401, 405, ++ 406, 407, 411, 412, 413, 417, 418, 419, 420, 424, ++ 425, 426, 427, 432, 435, 439, 447, 450, 454, 462, ++ 466, 470 + }; + #endif + +@@ -546,25 +513,25 @@ static const yytype_uint16 yyrline[] = + First, the terminals, then, starting at YYNTOKENS, nonterminals. */ + static const char *const yytname[] = + { +- "$end", "error", "$undefined", "DT_V1", "DT_MEMRESERVE", "DT_LSHIFT", +- "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND", "DT_OR", +- "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME", "DT_LITERAL", +- "DT_CHAR_LITERAL", "DT_BASE", "DT_BYTE", "DT_STRING", "DT_LABEL", ++ "$end", "error", "$undefined", "DT_V1", "DT_PLUGIN", "DT_MEMRESERVE", ++ "DT_LSHIFT", "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND", ++ "DT_OR", "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME", ++ "DT_LITERAL", "DT_CHAR_LITERAL", "DT_BYTE", "DT_STRING", "DT_LABEL", + "DT_REF", "DT_INCBIN", "';'", "'/'", "'{'", "'}'", "'='", "'>'", "'['", + "']'", "'('", "','", "')'", "'<'", "'?'", "':'", "'|'", "'^'", "'&'", + "'+'", "'-'", "'*'", "'%'", "'~'", "'!'", "$accept", "sourcefile", +- "memreserves", "memreserve", "devicetree", "nodedef", "proplist", +- "propdef", "propdata", "propdataprefix", "arrayprefix", "integer_prim", +- "integer_expr", "integer_trinary", "integer_or", "integer_and", +- "integer_bitor", "integer_bitxor", "integer_bitand", "integer_eq", +- "integer_rela", "integer_shift", "integer_add", "integer_mul", +- "integer_unary", "bytestring", "subnodes", "subnode", YY_NULL ++ "plugindecl", "memreserves", "memreserve", "devicetree", "nodedef", ++ "proplist", "propdef", "propdata", "propdataprefix", "arrayprefix", ++ "integer_prim", "integer_expr", "integer_trinary", "integer_or", ++ "integer_and", "integer_bitor", "integer_bitxor", "integer_bitand", ++ "integer_eq", "integer_rela", "integer_shift", "integer_add", ++ "integer_mul", "integer_unary", "bytestring", "subnodes", "subnode", YY_NULLPTR + }; + #endif + + # ifdef YYPRINT +-/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to +- token YYLEX-NUM. */ ++/* YYTOKNUM[NUM] -- (External) token number corresponding to the ++ (internal) symbol number NUM (which must be that of a token). */ + static const yytype_uint16 yytoknum[] = + { + 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, +@@ -575,183 +542,173 @@ static const yytype_uint16 yytoknum[] = + }; + # endif + +-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ +-static const yytype_uint8 yyr1[] = +-{ +- 0, 48, 49, 50, 50, 51, 51, 52, 52, 52, +- 52, 53, 54, 54, 55, 55, 55, 55, 56, 56, +- 56, 56, 56, 56, 56, 57, 57, 57, 58, 58, +- 58, 58, 58, 59, 59, 59, 60, 61, 61, 62, +- 62, 63, 63, 64, 64, 65, 65, 66, 66, 67, +- 67, 67, 68, 68, 68, 68, 68, 69, 69, 69, +- 70, 70, 70, 71, 71, 71, 71, 72, 72, 72, +- 72, 73, 73, 73, 74, 74, 74, 75, 75, 75 +-}; ++#define YYPACT_NINF -41 + +-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ +-static const yytype_uint8 yyr2[] = ++#define yypact_value_is_default(Yystate) \ ++ (!!((Yystate) == (-41))) ++ ++#define YYTABLE_NINF -1 ++ ++#define yytable_value_is_error(Yytable_value) \ ++ 0 ++ ++ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing ++ STATE-NUM. */ ++static const yytype_int8 yypact[] = + { +- 0, 2, 4, 0, 2, 4, 2, 2, 3, 3, +- 4, 5, 0, 2, 4, 2, 3, 2, 2, 3, +- 4, 2, 9, 5, 2, 0, 2, 2, 3, 1, +- 2, 2, 2, 1, 1, 3, 1, 1, 5, 1, +- 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, +- 3, 3, 1, 3, 3, 3, 3, 3, 3, 1, +- 3, 3, 1, 3, 3, 3, 1, 1, 2, 2, +- 2, 0, 2, 2, 0, 2, 2, 2, 3, 2 ++ 37, 10, 24, 78, -41, 20, 9, -41, 8, 9, ++ 59, 9, -41, -41, -10, 8, -41, 60, 39, -41, ++ -10, -10, -10, -41, 51, -41, -7, 76, 50, 52, ++ 53, 49, 2, 65, 32, -1, -41, 66, -41, -41, ++ 67, 60, 60, -41, -41, -41, -41, -10, -10, -10, ++ -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, ++ -10, -10, -10, -10, -10, -10, -41, 41, 68, -41, ++ -41, 76, 57, 50, 52, 53, 49, 2, 2, 65, ++ 65, 65, 65, 32, 32, -1, -1, -41, -41, -41, ++ 79, 80, -12, 41, -41, 70, 41, -41, -10, 74, ++ 75, -41, -41, -41, -41, -41, 77, -41, -41, -41, ++ -41, -41, 17, -2, -41, -41, -41, -41, 83, -41, ++ -41, -41, 71, -41, -41, 31, 69, 82, -4, -41, ++ -41, -41, -41, -41, 42, -41, -41, -41, 8, -41, ++ 72, 8, 73, -41 + }; + +-/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM. +- Performed when YYTABLE doesn't specify something else to do. Zero +- means the default is an error. */ ++ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. ++ Performed when YYTABLE does not specify something else to do. Zero ++ means the default is an error. */ + static const yytype_uint8 yydefact[] = + { +- 0, 0, 0, 3, 1, 0, 0, 0, 3, 33, +- 34, 0, 0, 6, 0, 2, 4, 0, 0, 0, +- 67, 0, 36, 37, 39, 41, 43, 45, 47, 49, +- 52, 59, 62, 66, 0, 12, 7, 0, 0, 0, +- 68, 69, 70, 35, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 3, 1, 0, 5, 4, 0, 0, ++ 0, 5, 35, 36, 0, 0, 8, 0, 2, 6, ++ 0, 0, 0, 69, 0, 38, 39, 41, 43, 45, ++ 47, 49, 51, 54, 61, 64, 68, 0, 14, 9, ++ 0, 0, 0, 70, 71, 72, 37, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 5, 74, 0, 9, 8, 40, 0, +- 42, 44, 46, 48, 50, 51, 55, 56, 54, 53, +- 57, 58, 60, 61, 64, 63, 65, 0, 0, 0, +- 0, 13, 0, 74, 10, 0, 0, 0, 15, 25, +- 77, 17, 79, 0, 76, 75, 38, 16, 78, 0, +- 0, 11, 24, 14, 26, 0, 18, 27, 21, 0, +- 71, 29, 0, 0, 0, 0, 32, 31, 19, 30, +- 28, 0, 72, 73, 20, 0, 23, 0, 0, 0, +- 22 ++ 0, 0, 0, 0, 0, 0, 7, 76, 0, 11, ++ 10, 42, 0, 44, 46, 48, 50, 52, 53, 57, ++ 58, 56, 55, 59, 60, 62, 63, 66, 65, 67, ++ 0, 0, 0, 0, 15, 0, 76, 12, 0, 0, ++ 0, 17, 27, 79, 19, 81, 0, 78, 77, 40, ++ 18, 80, 0, 0, 13, 26, 16, 28, 0, 20, ++ 29, 23, 0, 73, 31, 0, 0, 0, 0, 34, ++ 33, 21, 32, 30, 0, 74, 75, 22, 0, 25, ++ 0, 0, 0, 24 + }; + +-/* YYDEFGOTO[NTERM-NUM]. */ +-static const yytype_int8 yydefgoto[] = ++ /* YYPGOTO[NTERM-NUM]. */ ++static const yytype_int8 yypgoto[] = + { +- -1, 2, 7, 8, 15, 36, 64, 91, 109, 110, +- 122, 20, 21, 22, 23, 24, 25, 26, 27, 28, +- 29, 30, 31, 32, 33, 125, 92, 93 ++ -41, -41, -41, 96, 100, -41, -40, -41, -23, -41, ++ -41, -41, -8, 62, 13, -41, 81, 63, 64, 84, ++ 61, 25, 11, 21, 22, -17, -41, 19, 23 + }; + +-/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing +- STATE-NUM. */ +-#define YYPACT_NINF -78 +-static const yytype_int8 yypact[] = ++ /* YYDEFGOTO[NTERM-NUM]. */ ++static const yytype_int16 yydefgoto[] = + { +- 22, 11, 51, 10, -78, 23, 10, 2, 10, -78, +- -78, -9, 23, -78, 30, 38, -78, -9, -9, -9, +- -78, 35, -78, -6, 52, 29, 48, 49, 33, 3, +- 71, 36, 0, -78, 64, -78, -78, 68, 30, 30, +- -78, -78, -78, -78, -9, -9, -9, -9, -9, -9, +- -9, -9, -9, -9, -9, -9, -9, -9, -9, -9, +- -9, -9, -9, -78, 44, 67, -78, -78, 52, 55, +- 29, 48, 49, 33, 3, 3, 71, 71, 71, 71, +- 36, 36, 0, 0, -78, -78, -78, 78, 79, 42, +- 44, -78, 69, 44, -78, -9, 73, 74, -78, -78, +- -78, -78, -78, 75, -78, -78, -78, -78, -78, -7, +- -1, -78, -78, -78, -78, 84, -78, -78, -78, 63, +- -78, -78, 32, 66, 82, -3, -78, -78, -78, -78, +- -78, 46, -78, -78, -78, 23, -78, 70, 23, 72, +- -78 ++ -1, 2, 6, 10, 11, 18, 39, 67, 94, 112, ++ 113, 125, 23, 24, 25, 26, 27, 28, 29, 30, ++ 31, 32, 33, 34, 35, 36, 128, 95, 96 + }; + +-/* YYPGOTO[NTERM-NUM]. */ +-static const yytype_int8 yypgoto[] = ++ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If ++ positive, shift that token. If negative, reduce the rule whose ++ number is the opposite. If YYTABLE_NINF, syntax error. */ ++static const yytype_uint8 yytable[] = + { +- -78, -78, 97, 100, -78, -37, -78, -77, -78, -78, +- -78, -5, 65, 13, -78, 76, 77, 62, 80, 83, +- 34, 20, 26, 28, -14, -78, 18, 24 ++ 15, 69, 70, 43, 44, 45, 47, 37, 12, 13, ++ 55, 56, 118, 101, 8, 38, 135, 102, 136, 119, ++ 120, 121, 122, 14, 4, 63, 12, 13, 137, 123, ++ 48, 9, 57, 20, 124, 3, 21, 22, 58, 115, ++ 1, 14, 116, 64, 65, 7, 87, 88, 89, 12, ++ 13, 117, 103, 129, 130, 40, 90, 91, 92, 53, ++ 54, 131, 41, 93, 14, 42, 79, 80, 81, 82, ++ 104, 59, 60, 107, 61, 62, 138, 139, 77, 78, ++ 83, 84, 5, 85, 86, 17, 46, 38, 49, 50, ++ 68, 66, 51, 97, 52, 98, 99, 100, 106, 110, ++ 111, 126, 114, 134, 127, 133, 141, 19, 143, 16, ++ 72, 109, 73, 76, 74, 108, 105, 132, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 71, 0, ++ 140, 0, 0, 142, 0, 75 + }; + +-/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If +- positive, shift that token. If negative, reduce the rule which +- number is the opposite. If YYTABLE_NINF, syntax error. */ +-#define YYTABLE_NINF -1 +-static const yytype_uint8 yytable[] = ++static const yytype_int16 yycheck[] = + { +- 12, 66, 67, 40, 41, 42, 44, 34, 9, 10, +- 52, 53, 115, 101, 5, 112, 104, 132, 113, 133, +- 116, 117, 118, 119, 11, 1, 60, 114, 14, 134, +- 120, 45, 6, 54, 17, 121, 3, 18, 19, 55, +- 9, 10, 50, 51, 61, 62, 84, 85, 86, 9, +- 10, 4, 100, 37, 126, 127, 11, 35, 87, 88, +- 89, 38, 128, 46, 39, 11, 90, 98, 47, 35, +- 43, 99, 76, 77, 78, 79, 56, 57, 58, 59, +- 135, 136, 80, 81, 74, 75, 82, 83, 48, 63, +- 49, 65, 94, 95, 96, 97, 124, 103, 107, 108, +- 111, 123, 130, 131, 138, 16, 13, 140, 106, 71, +- 69, 105, 0, 0, 102, 0, 0, 129, 0, 0, +- 68, 0, 0, 70, 0, 0, 0, 0, 72, 0, +- 137, 0, 73, 139 ++ 8, 41, 42, 20, 21, 22, 13, 15, 18, 19, ++ 8, 9, 14, 25, 5, 27, 20, 29, 22, 21, ++ 22, 23, 24, 33, 0, 26, 18, 19, 32, 31, ++ 37, 22, 30, 43, 36, 25, 46, 47, 36, 22, ++ 3, 33, 25, 44, 45, 25, 63, 64, 65, 18, ++ 19, 34, 92, 22, 23, 16, 15, 16, 17, 10, ++ 11, 30, 23, 22, 33, 26, 55, 56, 57, 58, ++ 93, 6, 7, 96, 42, 43, 34, 35, 53, 54, ++ 59, 60, 4, 61, 62, 26, 35, 27, 12, 39, ++ 23, 25, 40, 25, 41, 38, 17, 17, 28, 25, ++ 25, 18, 25, 21, 33, 36, 34, 11, 35, 9, ++ 48, 98, 49, 52, 50, 96, 93, 125, -1, -1, ++ -1, -1, -1, -1, -1, -1, -1, -1, 47, -1, ++ 138, -1, -1, 141, -1, 51 + }; + +-#define yypact_value_is_default(Yystate) \ +- (!!((Yystate) == (-78))) +- +-#define yytable_value_is_error(Yytable_value) \ +- YYID (0) ++ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing ++ symbol of state STATE-NUM. */ ++static const yytype_uint8 yystos[] = ++{ ++ 0, 3, 49, 25, 0, 4, 50, 25, 5, 22, ++ 51, 52, 18, 19, 33, 60, 52, 26, 53, 51, ++ 43, 46, 47, 60, 61, 62, 63, 64, 65, 66, ++ 67, 68, 69, 70, 71, 72, 73, 60, 27, 54, ++ 16, 23, 26, 73, 73, 73, 35, 13, 37, 12, ++ 39, 40, 41, 10, 11, 8, 9, 30, 36, 6, ++ 7, 42, 43, 26, 44, 45, 25, 55, 23, 54, ++ 54, 64, 61, 65, 66, 67, 68, 69, 69, 70, ++ 70, 70, 70, 71, 71, 72, 72, 73, 73, 73, ++ 15, 16, 17, 22, 56, 75, 76, 25, 38, 17, ++ 17, 25, 29, 54, 56, 76, 28, 56, 75, 62, ++ 25, 25, 57, 58, 25, 22, 25, 34, 14, 21, ++ 22, 23, 24, 31, 36, 59, 18, 33, 74, 22, ++ 23, 30, 60, 36, 21, 20, 22, 32, 34, 35, ++ 60, 34, 60, 35 ++}; + +-static const yytype_int16 yycheck[] = ++ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ ++static const yytype_uint8 yyr1[] = + { +- 5, 38, 39, 17, 18, 19, 12, 12, 17, 18, +- 7, 8, 13, 90, 4, 22, 93, 20, 25, 22, +- 21, 22, 23, 24, 33, 3, 26, 34, 26, 32, +- 31, 37, 22, 30, 43, 36, 25, 46, 47, 36, +- 17, 18, 9, 10, 44, 45, 60, 61, 62, 17, +- 18, 0, 89, 15, 22, 23, 33, 27, 14, 15, +- 16, 23, 30, 11, 26, 33, 22, 25, 39, 27, +- 35, 29, 52, 53, 54, 55, 5, 6, 42, 43, +- 34, 35, 56, 57, 50, 51, 58, 59, 40, 25, +- 41, 23, 25, 38, 16, 16, 33, 28, 25, 25, +- 25, 17, 36, 21, 34, 8, 6, 35, 95, 47, +- 45, 93, -1, -1, 90, -1, -1, 122, -1, -1, +- 44, -1, -1, 46, -1, -1, -1, -1, 48, -1, +- 135, -1, 49, 138 ++ 0, 48, 49, 50, 50, 51, 51, 52, 52, 53, ++ 53, 53, 53, 54, 55, 55, 56, 56, 56, 56, ++ 57, 57, 57, 57, 57, 57, 57, 58, 58, 58, ++ 59, 59, 59, 59, 59, 60, 60, 60, 61, 62, ++ 62, 63, 63, 64, 64, 65, 65, 66, 66, 67, ++ 67, 68, 68, 68, 69, 69, 69, 69, 69, 70, ++ 70, 70, 71, 71, 71, 72, 72, 72, 72, 73, ++ 73, 73, 73, 74, 74, 74, 75, 75, 75, 76, ++ 76, 76 + }; + +-/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing +- symbol of state STATE-NUM. */ +-static const yytype_uint8 yystos[] = ++ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ ++static const yytype_uint8 yyr2[] = + { +- 0, 3, 49, 25, 0, 4, 22, 50, 51, 17, +- 18, 33, 59, 51, 26, 52, 50, 43, 46, 47, +- 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, +- 69, 70, 71, 72, 59, 27, 53, 15, 23, 26, +- 72, 72, 72, 35, 12, 37, 11, 39, 40, 41, +- 9, 10, 7, 8, 30, 36, 5, 6, 42, 43, +- 26, 44, 45, 25, 54, 23, 53, 53, 63, 60, +- 64, 65, 66, 67, 68, 68, 69, 69, 69, 69, +- 70, 70, 71, 71, 72, 72, 72, 14, 15, 16, +- 22, 55, 74, 75, 25, 38, 16, 16, 25, 29, +- 53, 55, 75, 28, 55, 74, 61, 25, 25, 56, +- 57, 25, 22, 25, 34, 13, 21, 22, 23, 24, +- 31, 36, 58, 17, 33, 73, 22, 23, 30, 59, +- 36, 21, 20, 22, 32, 34, 35, 59, 34, 59, +- 35 ++ 0, 2, 5, 0, 2, 0, 2, 4, 2, 2, ++ 3, 3, 4, 5, 0, 2, 4, 2, 3, 2, ++ 2, 3, 4, 2, 9, 5, 2, 0, 2, 2, ++ 3, 1, 2, 2, 2, 1, 1, 3, 1, 1, ++ 5, 1, 3, 1, 3, 1, 3, 1, 3, 1, ++ 3, 1, 3, 3, 1, 3, 3, 3, 3, 3, ++ 3, 1, 3, 3, 1, 3, 3, 3, 1, 1, ++ 2, 2, 2, 0, 2, 2, 0, 2, 2, 2, ++ 3, 2 + }; + +-#define yyerrok (yyerrstatus = 0) +-#define yyclearin (yychar = YYEMPTY) +-#define YYEMPTY (-2) +-#define YYEOF 0 +- +-#define YYACCEPT goto yyacceptlab +-#define YYABORT goto yyabortlab +-#define YYERROR goto yyerrorlab +- +- +-/* Like YYERROR except do call yyerror. This remains here temporarily +- to ease the transition to the new meaning of YYERROR, for GCC. +- Once GCC version 2 has supplanted version 1, this can go. However, +- YYFAIL appears to be in use. Nevertheless, it is formally deprecated +- in Bison 2.4.2's NEWS entry, where a plan to phase it out is +- discussed. */ +- +-#define YYFAIL goto yyerrlab +-#if defined YYFAIL +- /* This is here to suppress warnings from the GCC cpp's +- -Wunused-macros. Normally we don't worry about that warning, but +- some users do, and we want to make it easy for users to remove +- YYFAIL uses, which will produce warnings from Bison 2.5. */ +-#endif ++ ++#define yyerrok (yyerrstatus = 0) ++#define yyclearin (yychar = YYEMPTY) ++#define YYEMPTY (-2) ++#define YYEOF 0 ++ ++#define YYACCEPT goto yyacceptlab ++#define YYABORT goto yyabortlab ++#define YYERROR goto yyerrorlab ++ + + #define YYRECOVERING() (!!yyerrstatus) + +@@ -768,27 +725,41 @@ do + else \ + { \ + yyerror (YY_("syntax error: cannot back up")); \ +- YYERROR; \ +- } \ +-while (YYID (0)) ++ YYERROR; \ ++ } \ ++while (0) + + /* Error token number */ +-#define YYTERROR 1 +-#define YYERRCODE 256 ++#define YYTERROR 1 ++#define YYERRCODE 256 + + +-/* This macro is provided for backward compatibility. */ +-#ifndef YY_LOCATION_PRINT +-# define YY_LOCATION_PRINT(File, Loc) ((void) 0) ++/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N]. ++ If N is 0, then set CURRENT to the empty location which ends ++ the previous symbol: RHS[0] (always defined). */ ++ ++#ifndef YYLLOC_DEFAULT ++# define YYLLOC_DEFAULT(Current, Rhs, N) \ ++ do \ ++ if (N) \ ++ { \ ++ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \ ++ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \ ++ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \ ++ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \ ++ } \ ++ else \ ++ { \ ++ (Current).first_line = (Current).last_line = \ ++ YYRHSLOC (Rhs, 0).last_line; \ ++ (Current).first_column = (Current).last_column = \ ++ YYRHSLOC (Rhs, 0).last_column; \ ++ } \ ++ while (0) + #endif + ++#define YYRHSLOC(Rhs, K) ((Rhs)[K]) + +-/* YYLEX -- calling `yylex' with the right arguments. */ +-#ifdef YYLEX_PARAM +-# define YYLEX yylex (YYLEX_PARAM) +-#else +-# define YYLEX yylex () +-#endif + + /* Enable debugging if requested. */ + #if YYDEBUG +@@ -798,50 +769,84 @@ while (YYID (0)) + # define YYFPRINTF fprintf + # endif + +-# define YYDPRINTF(Args) \ +-do { \ +- if (yydebug) \ +- YYFPRINTF Args; \ +-} while (YYID (0)) +- +-# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ +-do { \ +- if (yydebug) \ +- { \ +- YYFPRINTF (stderr, "%s ", Title); \ +- yy_symbol_print (stderr, \ +- Type, Value); \ +- YYFPRINTF (stderr, "\n"); \ +- } \ +-} while (YYID (0)) ++# define YYDPRINTF(Args) \ ++do { \ ++ if (yydebug) \ ++ YYFPRINTF Args; \ ++} while (0) + + +-/*--------------------------------. +-| Print this symbol on YYOUTPUT. | +-`--------------------------------*/ ++/* YY_LOCATION_PRINT -- Print the location on the stream. ++ This macro was not mandated originally: define only if we know ++ we won't break user code: when these are the locations we know. */ + +-/*ARGSUSED*/ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static void +-yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) +-#else +-static void +-yy_symbol_value_print (yyoutput, yytype, yyvaluep) +- FILE *yyoutput; +- int yytype; +- YYSTYPE const * const yyvaluep; ++#ifndef YY_LOCATION_PRINT ++# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL ++ ++/* Print *YYLOCP on YYO. Private, do not rely on its existence. */ ++ ++YY_ATTRIBUTE_UNUSED ++static unsigned ++yy_location_print_ (FILE *yyo, YYLTYPE const * const yylocp) ++{ ++ unsigned res = 0; ++ int end_col = 0 != yylocp->last_column ? yylocp->last_column - 1 : 0; ++ if (0 <= yylocp->first_line) ++ { ++ res += YYFPRINTF (yyo, "%d", yylocp->first_line); ++ if (0 <= yylocp->first_column) ++ res += YYFPRINTF (yyo, ".%d", yylocp->first_column); ++ } ++ if (0 <= yylocp->last_line) ++ { ++ if (yylocp->first_line < yylocp->last_line) ++ { ++ res += YYFPRINTF (yyo, "-%d", yylocp->last_line); ++ if (0 <= end_col) ++ res += YYFPRINTF (yyo, ".%d", end_col); ++ } ++ else if (0 <= end_col && yylocp->first_column < end_col) ++ res += YYFPRINTF (yyo, "-%d", end_col); ++ } ++ return res; ++ } ++ ++# define YY_LOCATION_PRINT(File, Loc) \ ++ yy_location_print_ (File, &(Loc)) ++ ++# else ++# define YY_LOCATION_PRINT(File, Loc) ((void) 0) ++# endif + #endif ++ ++ ++# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ ++do { \ ++ if (yydebug) \ ++ { \ ++ YYFPRINTF (stderr, "%s ", Title); \ ++ yy_symbol_print (stderr, \ ++ Type, Value, Location); \ ++ YYFPRINTF (stderr, "\n"); \ ++ } \ ++} while (0) ++ ++ ++/*----------------------------------------. ++| Print this symbol's value on YYOUTPUT. | ++`----------------------------------------*/ ++ ++static void ++yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp) + { + FILE *yyo = yyoutput; + YYUSE (yyo); ++ YYUSE (yylocationp); + if (!yyvaluep) + return; + # ifdef YYPRINT + if (yytype < YYNTOKENS) + YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep); +-# else +- YYUSE (yyoutput); + # endif + YYUSE (yytype); + } +@@ -851,24 +856,15 @@ yy_symbol_value_print (yyoutput, yytype, + | Print this symbol on YYOUTPUT. | + `--------------------------------*/ + +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static void +-yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) +-#else + static void +-yy_symbol_print (yyoutput, yytype, yyvaluep) +- FILE *yyoutput; +- int yytype; +- YYSTYPE const * const yyvaluep; +-#endif ++yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp) + { +- if (yytype < YYNTOKENS) +- YYFPRINTF (yyoutput, "token %s (", yytname[yytype]); +- else +- YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]); ++ YYFPRINTF (yyoutput, "%s %s (", ++ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); + +- yy_symbol_value_print (yyoutput, yytype, yyvaluep); ++ YY_LOCATION_PRINT (yyoutput, *yylocationp); ++ YYFPRINTF (yyoutput, ": "); ++ yy_symbol_value_print (yyoutput, yytype, yyvaluep, yylocationp); + YYFPRINTF (yyoutput, ")"); + } + +@@ -877,16 +873,8 @@ yy_symbol_print (yyoutput, yytype, yyval + | TOP (included). | + `------------------------------------------------------------------*/ + +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) + static void + yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop) +-#else +-static void +-yy_stack_print (yybottom, yytop) +- yytype_int16 *yybottom; +- yytype_int16 *yytop; +-#endif + { + YYFPRINTF (stderr, "Stack now"); + for (; yybottom <= yytop; yybottom++) +@@ -897,49 +885,42 @@ yy_stack_print (yybottom, yytop) + YYFPRINTF (stderr, "\n"); + } + +-# define YY_STACK_PRINT(Bottom, Top) \ +-do { \ +- if (yydebug) \ +- yy_stack_print ((Bottom), (Top)); \ +-} while (YYID (0)) ++# define YY_STACK_PRINT(Bottom, Top) \ ++do { \ ++ if (yydebug) \ ++ yy_stack_print ((Bottom), (Top)); \ ++} while (0) + + + /*------------------------------------------------. + | Report that the YYRULE is going to be reduced. | + `------------------------------------------------*/ + +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static void +-yy_reduce_print (YYSTYPE *yyvsp, int yyrule) +-#else + static void +-yy_reduce_print (yyvsp, yyrule) +- YYSTYPE *yyvsp; +- int yyrule; +-#endif ++yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, YYLTYPE *yylsp, int yyrule) + { ++ unsigned long int yylno = yyrline[yyrule]; + int yynrhs = yyr2[yyrule]; + int yyi; +- unsigned long int yylno = yyrline[yyrule]; + YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n", +- yyrule - 1, yylno); ++ yyrule - 1, yylno); + /* The symbols being reduced. */ + for (yyi = 0; yyi < yynrhs; yyi++) + { + YYFPRINTF (stderr, " $%d = ", yyi + 1); +- yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi], +- &(yyvsp[(yyi + 1) - (yynrhs)]) +- ); ++ yy_symbol_print (stderr, ++ yystos[yyssp[yyi + 1 - yynrhs]], ++ &(yyvsp[(yyi + 1) - (yynrhs)]) ++ , &(yylsp[(yyi + 1) - (yynrhs)]) ); + YYFPRINTF (stderr, "\n"); + } + } + +-# define YY_REDUCE_PRINT(Rule) \ +-do { \ +- if (yydebug) \ +- yy_reduce_print (yyvsp, Rule); \ +-} while (YYID (0)) ++# define YY_REDUCE_PRINT(Rule) \ ++do { \ ++ if (yydebug) \ ++ yy_reduce_print (yyssp, yyvsp, yylsp, Rule); \ ++} while (0) + + /* Nonzero means print parse trace. It is left uninitialized so that + multiple parsers can coexist. */ +@@ -953,7 +934,7 @@ int yydebug; + + + /* YYINITDEPTH -- initial size of the parser's stacks. */ +-#ifndef YYINITDEPTH ++#ifndef YYINITDEPTH + # define YYINITDEPTH 200 + #endif + +@@ -976,15 +957,8 @@ int yydebug; + # define yystrlen strlen + # else + /* Return the length of YYSTR. */ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) + static YYSIZE_T + yystrlen (const char *yystr) +-#else +-static YYSIZE_T +-yystrlen (yystr) +- const char *yystr; +-#endif + { + YYSIZE_T yylen; + for (yylen = 0; yystr[yylen]; yylen++) +@@ -1000,16 +974,8 @@ yystrlen (yystr) + # else + /* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in + YYDEST. */ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) + static char * + yystpcpy (char *yydest, const char *yysrc) +-#else +-static char * +-yystpcpy (yydest, yysrc) +- char *yydest; +- const char *yysrc; +-#endif + { + char *yyd = yydest; + const char *yys = yysrc; +@@ -1039,27 +1005,27 @@ yytnamerr (char *yyres, const char *yyst + char const *yyp = yystr; + + for (;;) +- switch (*++yyp) +- { +- case '\'': +- case ',': +- goto do_not_strip_quotes; +- +- case '\\': +- if (*++yyp != '\\') +- goto do_not_strip_quotes; +- /* Fall through. */ +- default: +- if (yyres) +- yyres[yyn] = *yyp; +- yyn++; +- break; +- +- case '"': +- if (yyres) +- yyres[yyn] = '\0'; +- return yyn; +- } ++ switch (*++yyp) ++ { ++ case '\'': ++ case ',': ++ goto do_not_strip_quotes; ++ ++ case '\\': ++ if (*++yyp != '\\') ++ goto do_not_strip_quotes; ++ /* Fall through. */ ++ default: ++ if (yyres) ++ yyres[yyn] = *yyp; ++ yyn++; ++ break; ++ ++ case '"': ++ if (yyres) ++ yyres[yyn] = '\0'; ++ return yyn; ++ } + do_not_strip_quotes: ; + } + +@@ -1082,11 +1048,11 @@ static int + yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, + yytype_int16 *yyssp, int yytoken) + { +- YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]); ++ YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); + YYSIZE_T yysize = yysize0; + enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; + /* Internationalized format string. */ +- const char *yyformat = YY_NULL; ++ const char *yyformat = YY_NULLPTR; + /* Arguments of yyformat. */ + char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; + /* Number of reported tokens (one for the "unexpected", one per +@@ -1094,10 +1060,6 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, c + int yycount = 0; + + /* There are many possibilities here to consider: +- - Assume YYFAIL is not used. It's too flawed to consider. See +- +- for details. YYERROR is fine as it does not invoke this +- function. + - If this state is a consistent state with a default action, then + the only way this function was invoked is if the default action + is an error action. In that case, don't check for expected +@@ -1147,7 +1109,7 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, c + } + yyarg[yycount++] = yytname[yyx]; + { +- YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]); ++ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); + if (! (yysize <= yysize1 + && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + return 2; +@@ -1214,26 +1176,18 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, c + | Release the memory associated to this symbol. | + `-----------------------------------------------*/ + +-/*ARGSUSED*/ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static void +-yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) +-#else + static void +-yydestruct (yymsg, yytype, yyvaluep) +- const char *yymsg; +- int yytype; +- YYSTYPE *yyvaluep; +-#endif ++yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep, YYLTYPE *yylocationp) + { + YYUSE (yyvaluep); +- ++ YYUSE (yylocationp); + if (!yymsg) + yymsg = "Deleting"; + YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); + ++ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN + YYUSE (yytype); ++ YY_IGNORE_MAYBE_UNINITIALIZED_END + } + + +@@ -1242,18 +1196,14 @@ yydestruct (yymsg, yytype, yyvaluep) + /* The lookahead symbol. */ + int yychar; + +- +-#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN +-# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN +-# define YY_IGNORE_MAYBE_UNINITIALIZED_END +-#endif +-#ifndef YY_INITIAL_VALUE +-# define YY_INITIAL_VALUE(Value) /* Nothing. */ +-#endif +- + /* The semantic value of the lookahead symbol. */ +-YYSTYPE yylval YY_INITIAL_VALUE(yyval_default); +- ++YYSTYPE yylval; ++/* Location data for the lookahead symbol. */ ++YYLTYPE yylloc ++# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL ++ = { 1, 1, 1, 1 } ++# endif ++; + /* Number of syntax errors so far. */ + int yynerrs; + +@@ -1262,35 +1212,17 @@ int yynerrs; + | yyparse. | + `----------*/ + +-#ifdef YYPARSE_PARAM +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-int +-yyparse (void *YYPARSE_PARAM) +-#else +-int +-yyparse (YYPARSE_PARAM) +- void *YYPARSE_PARAM; +-#endif +-#else /* ! YYPARSE_PARAM */ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) + int + yyparse (void) +-#else +-int +-yyparse () +- +-#endif +-#endif + { + int yystate; + /* Number of tokens to shift before error messages enabled. */ + int yyerrstatus; + + /* The stacks and their tools: +- `yyss': related to states. +- `yyvs': related to semantic values. ++ 'yyss': related to states. ++ 'yyvs': related to semantic values. ++ 'yyls': related to locations. + + Refer to the stacks through separate pointers, to allow yyoverflow + to reallocate them elsewhere. */ +@@ -1305,6 +1237,14 @@ yyparse () + YYSTYPE *yyvs; + YYSTYPE *yyvsp; + ++ /* The location stack. */ ++ YYLTYPE yylsa[YYINITDEPTH]; ++ YYLTYPE *yyls; ++ YYLTYPE *yylsp; ++ ++ /* The locations where the error started and ended. */ ++ YYLTYPE yyerror_range[3]; ++ + YYSIZE_T yystacksize; + + int yyn; +@@ -1314,6 +1254,7 @@ yyparse () + /* The variables used to return semantic value and location from the + action routines. */ + YYSTYPE yyval; ++ YYLTYPE yyloc; + + #if YYERROR_VERBOSE + /* Buffer for error messages, and its allocated size. */ +@@ -1322,7 +1263,7 @@ yyparse () + YYSIZE_T yymsg_alloc = sizeof yymsgbuf; + #endif + +-#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) ++#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N), yylsp -= (N)) + + /* The number of symbols on the RHS of the reduced rule. + Keep to zero when no symbol should be popped. */ +@@ -1330,6 +1271,7 @@ yyparse () + + yyssp = yyss = yyssa; + yyvsp = yyvs = yyvsa; ++ yylsp = yyls = yylsa; + yystacksize = YYINITDEPTH; + + YYDPRINTF ((stderr, "Starting parse\n")); +@@ -1338,6 +1280,7 @@ yyparse () + yyerrstatus = 0; + yynerrs = 0; + yychar = YYEMPTY; /* Cause a token to be read. */ ++ yylsp[0] = yylloc; + goto yysetstate; + + /*------------------------------------------------------------. +@@ -1358,23 +1301,26 @@ yyparse () + + #ifdef yyoverflow + { +- /* Give user a chance to reallocate the stack. Use copies of +- these so that the &'s don't force the real ones into +- memory. */ +- YYSTYPE *yyvs1 = yyvs; +- yytype_int16 *yyss1 = yyss; +- +- /* Each stack pointer address is followed by the size of the +- data in use in that stack, in bytes. This used to be a +- conditional around just the two extra args, but that might +- be undefined if yyoverflow is a macro. */ +- yyoverflow (YY_("memory exhausted"), +- &yyss1, yysize * sizeof (*yyssp), +- &yyvs1, yysize * sizeof (*yyvsp), +- &yystacksize); +- +- yyss = yyss1; +- yyvs = yyvs1; ++ /* Give user a chance to reallocate the stack. Use copies of ++ these so that the &'s don't force the real ones into ++ memory. */ ++ YYSTYPE *yyvs1 = yyvs; ++ yytype_int16 *yyss1 = yyss; ++ YYLTYPE *yyls1 = yyls; ++ ++ /* Each stack pointer address is followed by the size of the ++ data in use in that stack, in bytes. This used to be a ++ conditional around just the two extra args, but that might ++ be undefined if yyoverflow is a macro. */ ++ yyoverflow (YY_("memory exhausted"), ++ &yyss1, yysize * sizeof (*yyssp), ++ &yyvs1, yysize * sizeof (*yyvsp), ++ &yyls1, yysize * sizeof (*yylsp), ++ &yystacksize); ++ ++ yyls = yyls1; ++ yyss = yyss1; ++ yyvs = yyvs1; + } + #else /* no yyoverflow */ + # ifndef YYSTACK_RELOCATE +@@ -1382,34 +1328,36 @@ yyparse () + # else + /* Extend the stack our own way. */ + if (YYMAXDEPTH <= yystacksize) +- goto yyexhaustedlab; ++ goto yyexhaustedlab; + yystacksize *= 2; + if (YYMAXDEPTH < yystacksize) +- yystacksize = YYMAXDEPTH; ++ yystacksize = YYMAXDEPTH; + + { +- yytype_int16 *yyss1 = yyss; +- union yyalloc *yyptr = +- (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); +- if (! yyptr) +- goto yyexhaustedlab; +- YYSTACK_RELOCATE (yyss_alloc, yyss); +- YYSTACK_RELOCATE (yyvs_alloc, yyvs); ++ yytype_int16 *yyss1 = yyss; ++ union yyalloc *yyptr = ++ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); ++ if (! yyptr) ++ goto yyexhaustedlab; ++ YYSTACK_RELOCATE (yyss_alloc, yyss); ++ YYSTACK_RELOCATE (yyvs_alloc, yyvs); ++ YYSTACK_RELOCATE (yyls_alloc, yyls); + # undef YYSTACK_RELOCATE +- if (yyss1 != yyssa) +- YYSTACK_FREE (yyss1); ++ if (yyss1 != yyssa) ++ YYSTACK_FREE (yyss1); + } + # endif + #endif /* no yyoverflow */ + + yyssp = yyss + yysize - 1; + yyvsp = yyvs + yysize - 1; ++ yylsp = yyls + yysize - 1; + + YYDPRINTF ((stderr, "Stack size increased to %lu\n", +- (unsigned long int) yystacksize)); ++ (unsigned long int) yystacksize)); + + if (yyss + yystacksize - 1 <= yyssp) +- YYABORT; ++ YYABORT; + } + + YYDPRINTF ((stderr, "Entering state %d\n", yystate)); +@@ -1438,7 +1386,7 @@ yybackup: + if (yychar == YYEMPTY) + { + YYDPRINTF ((stderr, "Reading a token: ")); +- yychar = YYLEX; ++ yychar = yylex (); + } + + if (yychar <= YYEOF) +@@ -1481,7 +1429,7 @@ yybackup: + YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN + *++yyvsp = yylval; + YY_IGNORE_MAYBE_UNINITIALIZED_END +- ++ *++yylsp = yylloc; + goto yynewstate; + + +@@ -1503,7 +1451,7 @@ yyreduce: + yylen = yyr2[yyn]; + + /* If YYLEN is nonzero, implement the default value of the action: +- `$$ = $1'. ++ '$$ = $1'. + + Otherwise, the following line sets YYVAL to garbage. + This behavior is undocumented and Bison +@@ -1512,287 +1460,306 @@ yyreduce: + GCC warning that YYVAL may be used uninitialized. */ + yyval = yyvsp[1-yylen]; + +- ++ /* Default location. */ ++ YYLLOC_DEFAULT (yyloc, (yylsp - yylen), yylen); + YY_REDUCE_PRINT (yyn); + switch (yyn) + { + case 2: +-/* Line 1787 of yacc.c */ +-#line 110 "dtc-parser.y" ++#line 109 "dtc-parser.y" /* yacc.c:1646 */ + { +- the_boot_info = build_boot_info((yyvsp[(3) - (4)].re), (yyvsp[(4) - (4)].node), +- guess_boot_cpuid((yyvsp[(4) - (4)].node))); ++ (yyvsp[0].node)->is_plugin = (yyvsp[-2].is_plugin); ++ (yyvsp[0].node)->is_root = 1; ++ the_boot_info = build_boot_info((yyvsp[-1].re), (yyvsp[0].node), ++ guess_boot_cpuid((yyvsp[0].node))); + } ++#line 1477 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 3: +-/* Line 1787 of yacc.c */ +-#line 118 "dtc-parser.y" ++#line 119 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.re) = NULL; ++ (yyval.is_plugin) = 0; + } ++#line 1485 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 4: +-/* Line 1787 of yacc.c */ +-#line 122 "dtc-parser.y" ++#line 123 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.re) = chain_reserve_entry((yyvsp[(1) - (2)].re), (yyvsp[(2) - (2)].re)); ++ (yyval.is_plugin) = 1; + } ++#line 1493 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 5: +-/* Line 1787 of yacc.c */ +-#line 129 "dtc-parser.y" ++#line 130 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.re) = build_reserve_entry((yyvsp[(2) - (4)].integer), (yyvsp[(3) - (4)].integer)); ++ (yyval.re) = NULL; + } ++#line 1501 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 6: +-/* Line 1787 of yacc.c */ +-#line 133 "dtc-parser.y" ++#line 134 "dtc-parser.y" /* yacc.c:1646 */ + { +- add_label(&(yyvsp[(2) - (2)].re)->labels, (yyvsp[(1) - (2)].labelref)); +- (yyval.re) = (yyvsp[(2) - (2)].re); ++ (yyval.re) = chain_reserve_entry((yyvsp[-1].re), (yyvsp[0].re)); + } ++#line 1509 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 7: +-/* Line 1787 of yacc.c */ +-#line 141 "dtc-parser.y" ++#line 141 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = name_node((yyvsp[(2) - (2)].node), ""); ++ (yyval.re) = build_reserve_entry((yyvsp[-2].integer), (yyvsp[-1].integer)); + } ++#line 1517 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 8: +-/* Line 1787 of yacc.c */ +-#line 145 "dtc-parser.y" ++#line 145 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = merge_nodes((yyvsp[(1) - (3)].node), (yyvsp[(3) - (3)].node)); ++ add_label(&(yyvsp[0].re)->labels, (yyvsp[-1].labelref)); ++ (yyval.re) = (yyvsp[0].re); + } ++#line 1526 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 9: +-/* Line 1787 of yacc.c */ +-#line 149 "dtc-parser.y" ++#line 153 "dtc-parser.y" /* yacc.c:1646 */ + { +- struct node *target = get_node_by_ref((yyvsp[(1) - (3)].node), (yyvsp[(2) - (3)].labelref)); +- +- if (target) +- merge_nodes(target, (yyvsp[(3) - (3)].node)); +- else +- print_error("label or path, '%s', not found", (yyvsp[(2) - (3)].labelref)); +- (yyval.node) = (yyvsp[(1) - (3)].node); ++ (yyval.node) = name_node((yyvsp[0].node), ""); + } ++#line 1534 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 10: +-/* Line 1787 of yacc.c */ +-#line 159 "dtc-parser.y" ++#line 157 "dtc-parser.y" /* yacc.c:1646 */ + { +- struct node *target = get_node_by_ref((yyvsp[(1) - (4)].node), (yyvsp[(3) - (4)].labelref)); +- +- if (!target) +- print_error("label or path, '%s', not found", (yyvsp[(3) - (4)].labelref)); +- else +- delete_node(target); +- +- (yyval.node) = (yyvsp[(1) - (4)].node); ++ (yyval.node) = merge_nodes((yyvsp[-2].node), (yyvsp[0].node)); + } ++#line 1542 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 11: +-/* Line 1787 of yacc.c */ +-#line 173 "dtc-parser.y" ++#line 161 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = build_node((yyvsp[(2) - (5)].proplist), (yyvsp[(3) - (5)].nodelist)); ++ struct node *target = get_node_by_ref((yyvsp[-2].node), (yyvsp[-1].labelref)); ++ ++ if (target) ++ merge_nodes(target, (yyvsp[0].node)); ++ else ++ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref)); ++ (yyval.node) = (yyvsp[-2].node); + } ++#line 1556 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 12: +-/* Line 1787 of yacc.c */ +-#line 180 "dtc-parser.y" ++#line 171 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.proplist) = NULL; ++ struct node *target = get_node_by_ref((yyvsp[-3].node), (yyvsp[-1].labelref)); ++ ++ if (target) ++ delete_node(target); ++ else ++ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref)); ++ ++ ++ (yyval.node) = (yyvsp[-3].node); + } ++#line 1572 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 13: +-/* Line 1787 of yacc.c */ +-#line 184 "dtc-parser.y" ++#line 186 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.proplist) = chain_property((yyvsp[(2) - (2)].prop), (yyvsp[(1) - (2)].proplist)); ++ (yyval.node) = build_node((yyvsp[-3].proplist), (yyvsp[-2].nodelist)); + } ++#line 1580 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 14: +-/* Line 1787 of yacc.c */ +-#line 191 "dtc-parser.y" ++#line 193 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.prop) = build_property((yyvsp[(1) - (4)].propnodename), (yyvsp[(3) - (4)].data)); ++ (yyval.proplist) = NULL; + } ++#line 1588 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 15: +-/* Line 1787 of yacc.c */ +-#line 195 "dtc-parser.y" ++#line 197 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.prop) = build_property((yyvsp[(1) - (2)].propnodename), empty_data); ++ (yyval.proplist) = chain_property((yyvsp[0].prop), (yyvsp[-1].proplist)); + } ++#line 1596 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 16: +-/* Line 1787 of yacc.c */ +-#line 199 "dtc-parser.y" ++#line 204 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.prop) = build_property_delete((yyvsp[(2) - (3)].propnodename)); ++ (yyval.prop) = build_property((yyvsp[-3].propnodename), (yyvsp[-1].data)); + } ++#line 1604 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 17: +-/* Line 1787 of yacc.c */ +-#line 203 "dtc-parser.y" ++#line 208 "dtc-parser.y" /* yacc.c:1646 */ + { +- add_label(&(yyvsp[(2) - (2)].prop)->labels, (yyvsp[(1) - (2)].labelref)); +- (yyval.prop) = (yyvsp[(2) - (2)].prop); ++ (yyval.prop) = build_property((yyvsp[-1].propnodename), empty_data); + } ++#line 1612 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 18: +-/* Line 1787 of yacc.c */ +-#line 211 "dtc-parser.y" ++#line 212 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_merge((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].data)); ++ (yyval.prop) = build_property_delete((yyvsp[-1].propnodename)); + } ++#line 1620 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 19: +-/* Line 1787 of yacc.c */ +-#line 215 "dtc-parser.y" ++#line 216 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_merge((yyvsp[(1) - (3)].data), (yyvsp[(2) - (3)].array).data); ++ add_label(&(yyvsp[0].prop)->labels, (yyvsp[-1].labelref)); ++ (yyval.prop) = (yyvsp[0].prop); + } ++#line 1629 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 20: +-/* Line 1787 of yacc.c */ +-#line 219 "dtc-parser.y" ++#line 224 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_merge((yyvsp[(1) - (4)].data), (yyvsp[(3) - (4)].data)); ++ (yyval.data) = data_merge((yyvsp[-1].data), (yyvsp[0].data)); + } ++#line 1637 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 21: +-/* Line 1787 of yacc.c */ +-#line 223 "dtc-parser.y" ++#line 228 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), REF_PATH, (yyvsp[(2) - (2)].labelref)); ++ (yyval.data) = data_merge((yyvsp[-2].data), (yyvsp[-1].array).data); + } ++#line 1645 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 22: +-/* Line 1787 of yacc.c */ +-#line 227 "dtc-parser.y" ++#line 232 "dtc-parser.y" /* yacc.c:1646 */ + { +- FILE *f = srcfile_relative_open((yyvsp[(4) - (9)].data).val, NULL); ++ (yyval.data) = data_merge((yyvsp[-3].data), (yyvsp[-1].data)); ++ } ++#line 1653 "dtc-parser.tab.c" /* yacc.c:1646 */ ++ break; ++ ++ case 23: ++#line 236 "dtc-parser.y" /* yacc.c:1646 */ ++ { ++ (yyval.data) = data_add_marker((yyvsp[-1].data), REF_PATH, (yyvsp[0].labelref)); ++ } ++#line 1661 "dtc-parser.tab.c" /* yacc.c:1646 */ ++ break; ++ ++ case 24: ++#line 240 "dtc-parser.y" /* yacc.c:1646 */ ++ { ++ FILE *f = srcfile_relative_open((yyvsp[-5].data).val, NULL); + struct data d; + +- if ((yyvsp[(6) - (9)].integer) != 0) +- if (fseek(f, (yyvsp[(6) - (9)].integer), SEEK_SET) != 0) +- print_error("Couldn't seek to offset %llu in \"%s\": %s", +- (unsigned long long)(yyvsp[(6) - (9)].integer), +- (yyvsp[(4) - (9)].data).val, +- strerror(errno)); ++ if ((yyvsp[-3].integer) != 0) ++ if (fseek(f, (yyvsp[-3].integer), SEEK_SET) != 0) ++ die("Couldn't seek to offset %llu in \"%s\": %s", ++ (unsigned long long)(yyvsp[-3].integer), (yyvsp[-5].data).val, ++ strerror(errno)); + +- d = data_copy_file(f, (yyvsp[(8) - (9)].integer)); ++ d = data_copy_file(f, (yyvsp[-1].integer)); + +- (yyval.data) = data_merge((yyvsp[(1) - (9)].data), d); ++ (yyval.data) = data_merge((yyvsp[-8].data), d); + fclose(f); + } ++#line 1681 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 23: +-/* Line 1787 of yacc.c */ +-#line 244 "dtc-parser.y" ++ case 25: ++#line 256 "dtc-parser.y" /* yacc.c:1646 */ + { +- FILE *f = srcfile_relative_open((yyvsp[(4) - (5)].data).val, NULL); ++ FILE *f = srcfile_relative_open((yyvsp[-1].data).val, NULL); + struct data d = empty_data; + + d = data_copy_file(f, -1); + +- (yyval.data) = data_merge((yyvsp[(1) - (5)].data), d); ++ (yyval.data) = data_merge((yyvsp[-4].data), d); + fclose(f); + } ++#line 1695 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 24: +-/* Line 1787 of yacc.c */ +-#line 254 "dtc-parser.y" ++ case 26: ++#line 266 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); ++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); + } ++#line 1703 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 25: +-/* Line 1787 of yacc.c */ +-#line 261 "dtc-parser.y" ++ case 27: ++#line 273 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.data) = empty_data; + } ++#line 1711 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 26: +-/* Line 1787 of yacc.c */ +-#line 265 "dtc-parser.y" ++ case 28: ++#line 277 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = (yyvsp[(1) - (2)].data); ++ (yyval.data) = (yyvsp[-1].data); + } ++#line 1719 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 27: +-/* Line 1787 of yacc.c */ +-#line 269 "dtc-parser.y" ++ case 29: ++#line 281 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); ++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); + } ++#line 1727 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 28: +-/* Line 1787 of yacc.c */ +-#line 276 "dtc-parser.y" ++ case 30: ++#line 288 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.array).data = empty_data; +- (yyval.array).bits = eval_literal((yyvsp[(2) - (3)].literal), 0, 7); ++ unsigned long long bits; + +- if (((yyval.array).bits != 8) && +- ((yyval.array).bits != 16) && +- ((yyval.array).bits != 32) && +- ((yyval.array).bits != 64)) +- { +- print_error("Only 8, 16, 32 and 64-bit elements" +- " are currently supported"); +- (yyval.array).bits = 32; ++ bits = (yyvsp[-1].integer); ++ ++ if ((bits != 8) && (bits != 16) && ++ (bits != 32) && (bits != 64)) { ++ ERROR(&(yylsp[-1]), "Array elements must be" ++ " 8, 16, 32 or 64-bits"); ++ bits = 32; + } ++ ++ (yyval.array).data = empty_data; ++ (yyval.array).bits = bits; + } ++#line 1747 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 29: +-/* Line 1787 of yacc.c */ +-#line 291 "dtc-parser.y" ++ case 31: ++#line 304 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.array).data = empty_data; + (yyval.array).bits = 32; + } ++#line 1756 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 30: +-/* Line 1787 of yacc.c */ +-#line 296 "dtc-parser.y" ++ case 32: ++#line 309 "dtc-parser.y" /* yacc.c:1646 */ + { +- if ((yyvsp[(1) - (2)].array).bits < 64) { +- uint64_t mask = (1ULL << (yyvsp[(1) - (2)].array).bits) - 1; ++ if ((yyvsp[-1].array).bits < 64) { ++ uint64_t mask = (1ULL << (yyvsp[-1].array).bits) - 1; + /* + * Bits above mask must either be all zero + * (positive within range of mask) or all one +@@ -1801,275 +1768,258 @@ yyreduce: + * within the mask to one (i.e. | in the + * mask), all bits are one. + */ +- if (((yyvsp[(2) - (2)].integer) > mask) && (((yyvsp[(2) - (2)].integer) | mask) != -1ULL)) +- print_error( +- "integer value out of range " +- "%016lx (%d bits)", (yyvsp[(1) - (2)].array).bits); ++ if (((yyvsp[0].integer) > mask) && (((yyvsp[0].integer) | mask) != -1ULL)) ++ ERROR(&(yylsp[0]), "Value out of range for" ++ " %d-bit array element", (yyvsp[-1].array).bits); + } + +- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, (yyvsp[(2) - (2)].integer), (yyvsp[(1) - (2)].array).bits); ++ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, (yyvsp[0].integer), (yyvsp[-1].array).bits); + } ++#line 1779 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 31: +-/* Line 1787 of yacc.c */ +-#line 316 "dtc-parser.y" ++ case 33: ++#line 328 "dtc-parser.y" /* yacc.c:1646 */ + { +- uint64_t val = ~0ULL >> (64 - (yyvsp[(1) - (2)].array).bits); ++ uint64_t val = ~0ULL >> (64 - (yyvsp[-1].array).bits); + +- if ((yyvsp[(1) - (2)].array).bits == 32) +- (yyvsp[(1) - (2)].array).data = data_add_marker((yyvsp[(1) - (2)].array).data, ++ if ((yyvsp[-1].array).bits == 32) ++ (yyvsp[-1].array).data = data_add_marker((yyvsp[-1].array).data, + REF_PHANDLE, +- (yyvsp[(2) - (2)].labelref)); ++ (yyvsp[0].labelref)); + else +- print_error("References are only allowed in " ++ ERROR(&(yylsp[0]), "References are only allowed in " + "arrays with 32-bit elements."); + +- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, val, (yyvsp[(1) - (2)].array).bits); +- } +- break; +- +- case 32: +-/* Line 1787 of yacc.c */ +-#line 330 "dtc-parser.y" +- { +- (yyval.array).data = data_add_marker((yyvsp[(1) - (2)].array).data, LABEL, (yyvsp[(2) - (2)].labelref)); +- } +- break; +- +- case 33: +-/* Line 1787 of yacc.c */ +-#line 337 "dtc-parser.y" +- { +- (yyval.integer) = eval_literal((yyvsp[(1) - (1)].literal), 0, 64); ++ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, val, (yyvsp[-1].array).bits); + } ++#line 1797 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 34: +-/* Line 1787 of yacc.c */ +-#line 341 "dtc-parser.y" ++#line 342 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.integer) = eval_char_literal((yyvsp[(1) - (1)].literal)); ++ (yyval.array).data = data_add_marker((yyvsp[-1].array).data, LABEL, (yyvsp[0].labelref)); + } ++#line 1805 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 35: +-/* Line 1787 of yacc.c */ +-#line 345 "dtc-parser.y" ++ case 37: ++#line 351 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.integer) = (yyvsp[(2) - (3)].integer); ++ (yyval.integer) = (yyvsp[-1].integer); + } +- break; +- +- case 38: +-/* Line 1787 of yacc.c */ +-#line 356 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); } ++#line 1813 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 40: +-/* Line 1787 of yacc.c */ +-#line 361 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); } ++#line 362 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-4].integer) ? (yyvsp[-2].integer) : (yyvsp[0].integer); } ++#line 1819 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 42: +-/* Line 1787 of yacc.c */ +-#line 366 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); } ++#line 367 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) || (yyvsp[0].integer); } ++#line 1825 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 44: +-/* Line 1787 of yacc.c */ +-#line 371 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); } ++#line 372 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) && (yyvsp[0].integer); } ++#line 1831 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 46: +-/* Line 1787 of yacc.c */ +-#line 376 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); } ++#line 377 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) | (yyvsp[0].integer); } ++#line 1837 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 48: +-/* Line 1787 of yacc.c */ +-#line 381 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); } ++#line 382 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) ^ (yyvsp[0].integer); } ++#line 1843 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 50: +-/* Line 1787 of yacc.c */ +-#line 386 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); } ++#line 387 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) & (yyvsp[0].integer); } ++#line 1849 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 51: +-/* Line 1787 of yacc.c */ +-#line 387 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); } ++ case 52: ++#line 392 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) == (yyvsp[0].integer); } ++#line 1855 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 53: +-/* Line 1787 of yacc.c */ +-#line 392 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); } +- break; +- +- case 54: +-/* Line 1787 of yacc.c */ +-#line 393 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); } ++#line 393 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) != (yyvsp[0].integer); } ++#line 1861 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 55: +-/* Line 1787 of yacc.c */ +-#line 394 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); } ++#line 398 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) < (yyvsp[0].integer); } ++#line 1867 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 56: +-/* Line 1787 of yacc.c */ +-#line 395 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); } ++#line 399 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) > (yyvsp[0].integer); } ++#line 1873 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 57: +-/* Line 1787 of yacc.c */ +-#line 399 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); } ++#line 400 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) <= (yyvsp[0].integer); } ++#line 1879 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 58: +-/* Line 1787 of yacc.c */ +-#line 400 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); } ++#line 401 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) >= (yyvsp[0].integer); } ++#line 1885 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 60: +-/* Line 1787 of yacc.c */ +-#line 405 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); } ++ case 59: ++#line 405 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) << (yyvsp[0].integer); } ++#line 1891 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 61: +-/* Line 1787 of yacc.c */ +-#line 406 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); } ++ case 60: ++#line 406 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) >> (yyvsp[0].integer); } ++#line 1897 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 63: +-/* Line 1787 of yacc.c */ +-#line 411 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); } ++ case 62: ++#line 411 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) + (yyvsp[0].integer); } ++#line 1903 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 64: +-/* Line 1787 of yacc.c */ +-#line 412 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); } ++ case 63: ++#line 412 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) - (yyvsp[0].integer); } ++#line 1909 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 65: +-/* Line 1787 of yacc.c */ +-#line 413 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); } ++#line 417 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) * (yyvsp[0].integer); } ++#line 1915 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 68: +-/* Line 1787 of yacc.c */ +-#line 419 "dtc-parser.y" +- { (yyval.integer) = -(yyvsp[(2) - (2)].integer); } ++ case 66: ++#line 418 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) / (yyvsp[0].integer); } ++#line 1921 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 69: +-/* Line 1787 of yacc.c */ +-#line 420 "dtc-parser.y" +- { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); } ++ case 67: ++#line 419 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) % (yyvsp[0].integer); } ++#line 1927 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 70: +-/* Line 1787 of yacc.c */ +-#line 421 "dtc-parser.y" +- { (yyval.integer) = !(yyvsp[(2) - (2)].integer); } ++#line 425 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = -(yyvsp[0].integer); } ++#line 1933 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 71: +-/* Line 1787 of yacc.c */ +-#line 426 "dtc-parser.y" +- { +- (yyval.data) = empty_data; +- } ++#line 426 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = ~(yyvsp[0].integer); } ++#line 1939 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 72: +-/* Line 1787 of yacc.c */ +-#line 430 "dtc-parser.y" +- { +- (yyval.data) = data_append_byte((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].byte)); +- } ++#line 427 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = !(yyvsp[0].integer); } ++#line 1945 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 73: +-/* Line 1787 of yacc.c */ +-#line 434 "dtc-parser.y" ++#line 432 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); ++ (yyval.data) = empty_data; + } ++#line 1953 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 74: +-/* Line 1787 of yacc.c */ +-#line 441 "dtc-parser.y" ++#line 436 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.nodelist) = NULL; ++ (yyval.data) = data_append_byte((yyvsp[-1].data), (yyvsp[0].byte)); + } ++#line 1961 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 75: +-/* Line 1787 of yacc.c */ +-#line 445 "dtc-parser.y" ++#line 440 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.nodelist) = chain_node((yyvsp[(1) - (2)].node), (yyvsp[(2) - (2)].nodelist)); ++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); + } ++#line 1969 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 76: +-/* Line 1787 of yacc.c */ +-#line 449 "dtc-parser.y" ++#line 447 "dtc-parser.y" /* yacc.c:1646 */ + { +- print_error("syntax error: properties must precede subnodes"); +- YYERROR; ++ (yyval.nodelist) = NULL; + } ++#line 1977 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 77: +-/* Line 1787 of yacc.c */ +-#line 457 "dtc-parser.y" ++#line 451 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = name_node((yyvsp[(2) - (2)].node), (yyvsp[(1) - (2)].propnodename)); ++ (yyval.nodelist) = chain_node((yyvsp[-1].node), (yyvsp[0].nodelist)); + } ++#line 1985 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 78: +-/* Line 1787 of yacc.c */ +-#line 461 "dtc-parser.y" ++#line 455 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = name_node(build_node_delete(), (yyvsp[(2) - (3)].propnodename)); ++ ERROR(&(yylsp[0]), "Properties must precede subnodes"); ++ YYERROR; + } ++#line 1994 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 79: +-/* Line 1787 of yacc.c */ +-#line 465 "dtc-parser.y" ++#line 463 "dtc-parser.y" /* yacc.c:1646 */ + { +- add_label(&(yyvsp[(2) - (2)].node)->labels, (yyvsp[(1) - (2)].labelref)); +- (yyval.node) = (yyvsp[(2) - (2)].node); ++ (yyval.node) = name_node((yyvsp[0].node), (yyvsp[-1].propnodename)); + } ++#line 2002 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + ++ case 80: ++#line 467 "dtc-parser.y" /* yacc.c:1646 */ ++ { ++ (yyval.node) = name_node(build_node_delete(), (yyvsp[-1].propnodename)); ++ } ++#line 2010 "dtc-parser.tab.c" /* yacc.c:1646 */ ++ break; ++ ++ case 81: ++#line 471 "dtc-parser.y" /* yacc.c:1646 */ ++ { ++ add_label(&(yyvsp[0].node)->labels, (yyvsp[-1].labelref)); ++ (yyval.node) = (yyvsp[0].node); ++ } ++#line 2019 "dtc-parser.tab.c" /* yacc.c:1646 */ ++ break; + +-/* Line 1787 of yacc.c */ +-#line 2073 "dtc-parser.tab.c" ++ ++#line 2023 "dtc-parser.tab.c" /* yacc.c:1646 */ + default: break; + } + /* User semantic actions sometimes alter yychar, and that requires +@@ -2090,8 +2040,9 @@ yyreduce: + YY_STACK_PRINT (yyss, yyssp); + + *++yyvsp = yyval; ++ *++yylsp = yyloc; + +- /* Now `shift' the result of the reduction. Determine what state ++ /* Now 'shift' the result of the reduction. Determine what state + that goes to, based on the state we popped back to and the rule + number reduced by. */ + +@@ -2106,9 +2057,9 @@ yyreduce: + goto yynewstate; + + +-/*------------------------------------. +-| yyerrlab -- here on detecting error | +-`------------------------------------*/ ++/*--------------------------------------. ++| yyerrlab -- here on detecting error. | ++`--------------------------------------*/ + yyerrlab: + /* Make sure we have latest lookahead translation. See comments at + user semantic actions for why this is necessary. */ +@@ -2154,25 +2105,25 @@ yyerrlab: + #endif + } + +- ++ yyerror_range[1] = yylloc; + + if (yyerrstatus == 3) + { + /* If just tried and failed to reuse lookahead token after an +- error, discard it. */ ++ error, discard it. */ + + if (yychar <= YYEOF) +- { +- /* Return failure if at end of input. */ +- if (yychar == YYEOF) +- YYABORT; +- } ++ { ++ /* Return failure if at end of input. */ ++ if (yychar == YYEOF) ++ YYABORT; ++ } + else +- { +- yydestruct ("Error: discarding", +- yytoken, &yylval); +- yychar = YYEMPTY; +- } ++ { ++ yydestruct ("Error: discarding", ++ yytoken, &yylval, &yylloc); ++ yychar = YYEMPTY; ++ } + } + + /* Else will try to reuse lookahead token after shifting the error +@@ -2191,7 +2142,8 @@ yyerrorlab: + if (/*CONSTCOND*/ 0) + goto yyerrorlab; + +- /* Do not reclaim the symbols of the rule which action triggered ++ yyerror_range[1] = yylsp[1-yylen]; ++ /* Do not reclaim the symbols of the rule whose action triggered + this YYERROR. */ + YYPOPSTACK (yylen); + yylen = 0; +@@ -2204,29 +2156,29 @@ yyerrorlab: + | yyerrlab1 -- common code for both syntax error and YYERROR. | + `-------------------------------------------------------------*/ + yyerrlab1: +- yyerrstatus = 3; /* Each real token shifted decrements this. */ ++ yyerrstatus = 3; /* Each real token shifted decrements this. */ + + for (;;) + { + yyn = yypact[yystate]; + if (!yypact_value_is_default (yyn)) +- { +- yyn += YYTERROR; +- if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) +- { +- yyn = yytable[yyn]; +- if (0 < yyn) +- break; +- } +- } ++ { ++ yyn += YYTERROR; ++ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) ++ { ++ yyn = yytable[yyn]; ++ if (0 < yyn) ++ break; ++ } ++ } + + /* Pop the current state because it cannot handle the error token. */ + if (yyssp == yyss) +- YYABORT; +- ++ YYABORT; + ++ yyerror_range[1] = *yylsp; + yydestruct ("Error: popping", +- yystos[yystate], yyvsp); ++ yystos[yystate], yyvsp, yylsp); + YYPOPSTACK (1); + yystate = *yyssp; + YY_STACK_PRINT (yyss, yyssp); +@@ -2236,6 +2188,11 @@ yyerrlab1: + *++yyvsp = yylval; + YY_IGNORE_MAYBE_UNINITIALIZED_END + ++ yyerror_range[2] = yylloc; ++ /* Using YYLLOC is tempting, but would change the location of ++ the lookahead. YYLOC is available though. */ ++ YYLLOC_DEFAULT (yyloc, yyerror_range, 2); ++ *++yylsp = yyloc; + + /* Shift the error token. */ + YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); +@@ -2275,16 +2232,16 @@ yyreturn: + user semantic actions for why this is necessary. */ + yytoken = YYTRANSLATE (yychar); + yydestruct ("Cleanup: discarding lookahead", +- yytoken, &yylval); ++ yytoken, &yylval, &yylloc); + } +- /* Do not reclaim the symbols of the rule which action triggered ++ /* Do not reclaim the symbols of the rule whose action triggered + this YYABORT or YYACCEPT. */ + YYPOPSTACK (yylen); + YY_STACK_PRINT (yyss, yyssp); + while (yyssp != yyss) + { + yydestruct ("Cleanup: popping", +- yystos[*yyssp], yyvsp); ++ yystos[*yyssp], yyvsp, yylsp); + YYPOPSTACK (1); + } + #ifndef yyoverflow +@@ -2295,72 +2252,12 @@ yyreturn: + if (yymsg != yymsgbuf) + YYSTACK_FREE (yymsg); + #endif +- /* Make sure YYID is used. */ +- return YYID (yyresult); ++ return yyresult; + } ++#line 477 "dtc-parser.y" /* yacc.c:1906 */ + + +-/* Line 2050 of yacc.c */ +-#line 471 "dtc-parser.y" +- +- +-void print_error(char const *fmt, ...) ++void yyerror(char const *s) + { +- va_list va; +- +- va_start(va, fmt); +- srcpos_verror(&yylloc, fmt, va); +- va_end(va); +- +- treesource_error = 1; +-} +- +-void yyerror(char const *s) { +- print_error("%s", s); +-} +- +-static unsigned long long eval_literal(const char *s, int base, int bits) +-{ +- unsigned long long val; +- char *e; +- +- errno = 0; +- val = strtoull(s, &e, base); +- if (*e) { +- size_t uls = strspn(e, "UL"); +- if (e[uls]) +- print_error("bad characters in literal"); +- } +- if ((errno == ERANGE) +- || ((bits < 64) && (val >= (1ULL << bits)))) +- print_error("literal out of range"); +- else if (errno != 0) +- print_error("bad literal"); +- return val; +-} +- +-static unsigned char eval_char_literal(const char *s) +-{ +- int i = 1; +- char c = s[0]; +- +- if (c == '\0') +- { +- print_error("empty character literal"); +- return 0; +- } +- +- /* +- * If the first character in the character literal is a \ then process +- * the remaining characters as an escape encoding. If the first +- * character is neither an escape or a terminator it should be the only +- * character in the literal and will be returned. +- */ +- if (c == '\\') +- c = get_escape_char(s, &i); +- +- if (s[i] != '\0') +- print_error("malformed character literal"); +- +- return c; ++ ERROR(&yylloc, "%s", s); + } +--- a/scripts/dtc/dtc-parser.tab.h_shipped ++++ b/scripts/dtc/dtc-parser.tab.h_shipped +@@ -1,19 +1,19 @@ +-/* A Bison parser, made by GNU Bison 2.7.12-4996. */ ++/* A Bison parser, made by GNU Bison 3.0.2. */ + + /* Bison interface for Yacc-like parsers in C +- +- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. +- ++ ++ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. ++ + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. +- ++ + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. +- ++ + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +@@ -26,13 +26,13 @@ + special exception, which will cause the skeleton and the resulting + Bison output files to be licensed under the GNU General Public + License without this special exception. +- ++ + This special exception was added by the Free Software Foundation in + version 2.2 of Bison. */ + + #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED + # define YY_YY_DTC_PARSER_TAB_H_INCLUDED +-/* Enabling traces. */ ++/* Debug traces. */ + #ifndef YYDEBUG + # define YYDEBUG 0 + #endif +@@ -40,48 +40,45 @@ + extern int yydebug; + #endif + +-/* Tokens. */ ++/* Token type. */ + #ifndef YYTOKENTYPE + # define YYTOKENTYPE +- /* Put the tokens into the symbol table, so that GDB and other debuggers +- know about them. */ +- enum yytokentype { +- DT_V1 = 258, +- DT_MEMRESERVE = 259, +- DT_LSHIFT = 260, +- DT_RSHIFT = 261, +- DT_LE = 262, +- DT_GE = 263, +- DT_EQ = 264, +- DT_NE = 265, +- DT_AND = 266, +- DT_OR = 267, +- DT_BITS = 268, +- DT_DEL_PROP = 269, +- DT_DEL_NODE = 270, +- DT_PROPNODENAME = 271, +- DT_LITERAL = 272, +- DT_CHAR_LITERAL = 273, +- DT_BASE = 274, +- DT_BYTE = 275, +- DT_STRING = 276, +- DT_LABEL = 277, +- DT_REF = 278, +- DT_INCBIN = 279 +- }; ++ enum yytokentype ++ { ++ DT_V1 = 258, ++ DT_PLUGIN = 259, ++ DT_MEMRESERVE = 260, ++ DT_LSHIFT = 261, ++ DT_RSHIFT = 262, ++ DT_LE = 263, ++ DT_GE = 264, ++ DT_EQ = 265, ++ DT_NE = 266, ++ DT_AND = 267, ++ DT_OR = 268, ++ DT_BITS = 269, ++ DT_DEL_PROP = 270, ++ DT_DEL_NODE = 271, ++ DT_PROPNODENAME = 272, ++ DT_LITERAL = 273, ++ DT_CHAR_LITERAL = 274, ++ DT_BYTE = 275, ++ DT_STRING = 276, ++ DT_LABEL = 277, ++ DT_REF = 278, ++ DT_INCBIN = 279 ++ }; + #endif + +- ++/* Value type. */ + #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED +-typedef union YYSTYPE ++typedef union YYSTYPE YYSTYPE; ++union YYSTYPE + { +-/* Line 2053 of yacc.c */ +-#line 40 "dtc-parser.y" ++#line 39 "dtc-parser.y" /* yacc.c:1909 */ + + char *propnodename; +- char *literal; + char *labelref; +- unsigned int cbase; + uint8_t byte; + struct data data; + +@@ -96,30 +93,31 @@ typedef union YYSTYPE + struct node *nodelist; + struct reserve_info *re; + uint64_t integer; ++ int is_plugin; + +- +-/* Line 2053 of yacc.c */ +-#line 103 "dtc-parser.tab.h" +-} YYSTYPE; ++#line 99 "dtc-parser.tab.h" /* yacc.c:1909 */ ++}; + # define YYSTYPE_IS_TRIVIAL 1 +-# define yystype YYSTYPE /* obsolescent; will be withdrawn */ + # define YYSTYPE_IS_DECLARED 1 + #endif + +-extern YYSTYPE yylval; +- +-#ifdef YYPARSE_PARAM +-#if defined __STDC__ || defined __cplusplus +-int yyparse (void *YYPARSE_PARAM); +-#else +-int yyparse (); ++/* Location type. */ ++#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED ++typedef struct YYLTYPE YYLTYPE; ++struct YYLTYPE ++{ ++ int first_line; ++ int first_column; ++ int last_line; ++ int last_column; ++}; ++# define YYLTYPE_IS_DECLARED 1 ++# define YYLTYPE_IS_TRIVIAL 1 + #endif +-#else /* ! YYPARSE_PARAM */ +-#if defined __STDC__ || defined __cplusplus ++ ++ ++extern YYSTYPE yylval; ++extern YYLTYPE yylloc; + int yyparse (void); +-#else +-int yyparse (); +-#endif +-#endif /* ! YYPARSE_PARAM */ + + #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */ +--- a/scripts/dtc/dtc-parser.y ++++ b/scripts/dtc/dtc-parser.y +@@ -17,31 +17,28 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ +- + %{ + #include ++#include + + #include "dtc.h" + #include "srcpos.h" + +-YYLTYPE yylloc; +- + extern int yylex(void); +-extern void print_error(char const *fmt, ...); + extern void yyerror(char const *s); ++#define ERROR(loc, ...) \ ++ do { \ ++ srcpos_error((loc), "Error", __VA_ARGS__); \ ++ treesource_error = true; \ ++ } while (0) + + extern struct boot_info *the_boot_info; +-extern int treesource_error; +- +-static unsigned long long eval_literal(const char *s, int base, int bits); +-static unsigned char eval_char_literal(const char *s); ++extern bool treesource_error; + %} + + %union { + char *propnodename; +- char *literal; + char *labelref; +- unsigned int cbase; + uint8_t byte; + struct data data; + +@@ -56,18 +53,19 @@ static unsigned char eval_char_literal(c + struct node *nodelist; + struct reserve_info *re; + uint64_t integer; ++ int is_plugin; + } + + %token DT_V1 ++%token DT_PLUGIN + %token DT_MEMRESERVE + %token DT_LSHIFT DT_RSHIFT DT_LE DT_GE DT_EQ DT_NE DT_AND DT_OR + %token DT_BITS + %token DT_DEL_PROP + %token DT_DEL_NODE + %token DT_PROPNODENAME +-%token DT_LITERAL +-%token DT_CHAR_LITERAL +-%token DT_BASE ++%token DT_LITERAL ++%token DT_CHAR_LITERAL + %token DT_BYTE + %token DT_STRING + %token DT_LABEL +@@ -76,6 +74,7 @@ static unsigned char eval_char_literal(c + + %type propdata + %type propdataprefix ++%type plugindecl + %type memreserve + %type memreserves + %type arrayprefix +@@ -106,10 +105,23 @@ static unsigned char eval_char_literal(c + %% + + sourcefile: +- DT_V1 ';' memreserves devicetree ++ DT_V1 ';' plugindecl memreserves devicetree ++ { ++ $5->is_plugin = $3; ++ $5->is_root = 1; ++ the_boot_info = build_boot_info($4, $5, ++ guess_boot_cpuid($5)); ++ } ++ ; ++ ++plugindecl: ++ /* empty */ ++ { ++ $$ = 0; ++ } ++ | DT_PLUGIN ';' + { +- the_boot_info = build_boot_info($3, $4, +- guess_boot_cpuid($4)); ++ $$ = 1; + } + ; + +@@ -152,17 +164,18 @@ devicetree: + if (target) + merge_nodes(target, $3); + else +- print_error("label or path, '%s', not found", $2); ++ ERROR(&@2, "Label or path %s not found", $2); + $$ = $1; + } + | devicetree DT_DEL_NODE DT_REF ';' + { + struct node *target = get_node_by_ref($1, $3); + +- if (!target) +- print_error("label or path, '%s', not found", $3); +- else ++ if (target) + delete_node(target); ++ else ++ ERROR(&@3, "Label or path %s not found", $3); ++ + + $$ = $1; + } +@@ -230,10 +243,9 @@ propdata: + + if ($6 != 0) + if (fseek(f, $6, SEEK_SET) != 0) +- print_error("Couldn't seek to offset %llu in \"%s\": %s", +- (unsigned long long)$6, +- $4.val, +- strerror(errno)); ++ die("Couldn't seek to offset %llu in \"%s\": %s", ++ (unsigned long long)$6, $4.val, ++ strerror(errno)); + + d = data_copy_file(f, $8); + +@@ -274,18 +286,19 @@ propdataprefix: + arrayprefix: + DT_BITS DT_LITERAL '<' + { +- $$.data = empty_data; +- $$.bits = eval_literal($2, 0, 7); ++ unsigned long long bits; + +- if (($$.bits != 8) && +- ($$.bits != 16) && +- ($$.bits != 32) && +- ($$.bits != 64)) +- { +- print_error("Only 8, 16, 32 and 64-bit elements" +- " are currently supported"); +- $$.bits = 32; ++ bits = $2; ++ ++ if ((bits != 8) && (bits != 16) && ++ (bits != 32) && (bits != 64)) { ++ ERROR(&@2, "Array elements must be" ++ " 8, 16, 32 or 64-bits"); ++ bits = 32; + } ++ ++ $$.data = empty_data; ++ $$.bits = bits; + } + | '<' + { +@@ -305,9 +318,8 @@ arrayprefix: + * mask), all bits are one. + */ + if (($2 > mask) && (($2 | mask) != -1ULL)) +- print_error( +- "integer value out of range " +- "%016lx (%d bits)", $1.bits); ++ ERROR(&@2, "Value out of range for" ++ " %d-bit array element", $1.bits); + } + + $$.data = data_append_integer($1.data, $2, $1.bits); +@@ -321,7 +333,7 @@ arrayprefix: + REF_PHANDLE, + $2); + else +- print_error("References are only allowed in " ++ ERROR(&@2, "References are only allowed in " + "arrays with 32-bit elements."); + + $$.data = data_append_integer($1.data, val, $1.bits); +@@ -334,13 +346,7 @@ arrayprefix: + + integer_prim: + DT_LITERAL +- { +- $$ = eval_literal($1, 0, 64); +- } + | DT_CHAR_LITERAL +- { +- $$ = eval_char_literal($1); +- } + | '(' integer_expr ')' + { + $$ = $2; +@@ -447,7 +453,7 @@ subnodes: + } + | subnode propdef + { +- print_error("syntax error: properties must precede subnodes"); ++ ERROR(&@2, "Properties must precede subnodes"); + YYERROR; + } + ; +@@ -470,63 +476,7 @@ subnode: + + %% + +-void print_error(char const *fmt, ...) ++void yyerror(char const *s) + { +- va_list va; +- +- va_start(va, fmt); +- srcpos_verror(&yylloc, fmt, va); +- va_end(va); +- +- treesource_error = 1; +-} +- +-void yyerror(char const *s) { +- print_error("%s", s); +-} +- +-static unsigned long long eval_literal(const char *s, int base, int bits) +-{ +- unsigned long long val; +- char *e; +- +- errno = 0; +- val = strtoull(s, &e, base); +- if (*e) { +- size_t uls = strspn(e, "UL"); +- if (e[uls]) +- print_error("bad characters in literal"); +- } +- if ((errno == ERANGE) +- || ((bits < 64) && (val >= (1ULL << bits)))) +- print_error("literal out of range"); +- else if (errno != 0) +- print_error("bad literal"); +- return val; +-} +- +-static unsigned char eval_char_literal(const char *s) +-{ +- int i = 1; +- char c = s[0]; +- +- if (c == '\0') +- { +- print_error("empty character literal"); +- return 0; +- } +- +- /* +- * If the first character in the character literal is a \ then process +- * the remaining characters as an escape encoding. If the first +- * character is neither an escape or a terminator it should be the only +- * character in the literal and will be returned. +- */ +- if (c == '\\') +- c = get_escape_char(s, &i); +- +- if (s[i] != '\0') +- print_error("malformed character literal"); +- +- return c; ++ ERROR(&yylloc, "%s", s); + } +--- a/scripts/dtc/dtc.c ++++ b/scripts/dtc/dtc.c +@@ -29,6 +29,7 @@ int reservenum; /* Number of memory res + int minsize; /* Minimum blob size */ + int padsize; /* Additional padding to blob */ + int phandle_format = PHANDLE_BOTH; /* Use linux,phandle or phandle properties */ ++int symbol_fixup_support = 0; + + static void fill_fullpaths(struct node *tree, const char *prefix) + { +@@ -48,8 +49,10 @@ static void fill_fullpaths(struct node * + } + + /* Usage related data. */ ++#define FDT_VERSION(version) _FDT_VERSION(version) ++#define _FDT_VERSION(version) #version + static const char usage_synopsis[] = "dtc [options] "; +-static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv"; ++static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv@"; + static struct option const usage_long_opts[] = { + {"quiet", no_argument, NULL, 'q'}, + {"in-format", a_argument, NULL, 'I'}, +@@ -67,6 +70,7 @@ static struct option const usage_long_op + {"phandle", a_argument, NULL, 'H'}, + {"warning", a_argument, NULL, 'W'}, + {"error", a_argument, NULL, 'E'}, ++ {"symbols", a_argument, NULL, '@'}, + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'v'}, + {NULL, no_argument, NULL, 0x0}, +@@ -82,9 +86,9 @@ static const char * const usage_opts_hel + "\t\tdts - device tree source text\n" + "\t\tdtb - device tree blob\n" + "\t\tasm - assembler source", +- "\n\tBlob version to produce, defaults to %d (for dtb and asm output)", //, DEFAULT_FDT_VERSION); ++ "\n\tBlob version to produce, defaults to "FDT_VERSION(DEFAULT_FDT_VERSION)" (for dtb and asm output)", + "\n\tOutput dependency file", +- "\n\ttMake space for reserve map entries (for dtb and asm output)", ++ "\n\tMake space for reserve map entries (for dtb and asm output)", + "\n\tMake the blob at least long (extra space)", + "\n\tAdd padding to the blob of long (extra space)", + "\n\tSet the physical boot cpu", +@@ -97,6 +101,7 @@ static const char * const usage_opts_hel + "\t\tboth - Both \"linux,phandle\" and \"phandle\" properties", + "\n\tEnable/disable warnings (prefix with \"no-\")", + "\n\tEnable/disable errors (prefix with \"no-\")", ++ "\n\tSymbols and Fixups support", + "\n\tPrint this help and exit", + "\n\tPrint version and exit", + NULL, +@@ -109,7 +114,7 @@ int main(int argc, char *argv[]) + const char *outform = "dts"; + const char *outname = "-"; + const char *depname = NULL; +- int force = 0, sort = 0; ++ bool force = false, sort = false; + const char *arg; + int opt; + FILE *outf = NULL; +@@ -148,7 +153,7 @@ int main(int argc, char *argv[]) + padsize = strtol(optarg, NULL, 0); + break; + case 'f': +- force = 1; ++ force = true; + break; + case 'q': + quiet++; +@@ -174,7 +179,7 @@ int main(int argc, char *argv[]) + break; + + case 's': +- sort = 1; ++ sort = true; + break; + + case 'W': +@@ -184,7 +189,9 @@ int main(int argc, char *argv[]) + case 'E': + parse_checks_option(false, true, optarg); + break; +- ++ case '@': ++ symbol_fixup_support = 1; ++ break; + case 'h': + usage(NULL); + default: +@@ -237,7 +244,7 @@ int main(int argc, char *argv[]) + if (streq(outname, "-")) { + outf = stdout; + } else { +- outf = fopen(outname, "w"); ++ outf = fopen(outname, "wb"); + if (! outf) + die("Couldn't open output file %s: %s\n", + outname, strerror(errno)); +--- a/scripts/dtc/dtc.h ++++ b/scripts/dtc/dtc.h +@@ -38,9 +38,9 @@ + #include "util.h" + + #ifdef DEBUG +-#define debug(fmt,args...) printf(fmt, ##args) ++#define debug(...) printf(__VA_ARGS__) + #else +-#define debug(fmt,args...) ++#define debug(...) + #endif + + +@@ -54,6 +54,7 @@ extern int reservenum; /* Number of mem + extern int minsize; /* Minimum blob size */ + extern int padsize; /* Additional padding to blob */ + extern int phandle_format; /* Use linux,phandle or phandle properties */ ++extern int symbol_fixup_support;/* enable symbols & fixup support */ + + #define PHANDLE_LEGACY 0x1 + #define PHANDLE_EPAPR 0x2 +@@ -88,7 +89,7 @@ struct data { + }; + + +-#define empty_data ((struct data){ /* all .members = 0 or NULL */ }) ++#define empty_data ((struct data){ 0 /* all .members = 0 or NULL */ }) + + #define for_each_marker(m) \ + for (; (m); (m) = (m)->next) +@@ -118,7 +119,7 @@ struct data data_append_align(struct dat + + struct data data_add_marker(struct data d, enum markertype type, char *ref); + +-int data_is_one_string(struct data d); ++bool data_is_one_string(struct data d); + + /* DT constraints */ + +@@ -127,13 +128,32 @@ int data_is_one_string(struct data d); + + /* Live trees */ + struct label { +- int deleted; ++ bool deleted; + char *label; + struct label *next; + }; + ++struct fixup_entry { ++ int offset; ++ struct node *node; ++ struct property *prop; ++ struct fixup_entry *next; ++}; ++ ++struct fixup { ++ char *ref; ++ struct fixup_entry *entries; ++ struct fixup *next; ++}; ++ ++struct symbol { ++ struct label *label; ++ struct node *node; ++ struct symbol *next; ++}; ++ + struct property { +- int deleted; ++ bool deleted; + char *name; + struct data val; + +@@ -143,7 +163,7 @@ struct property { + }; + + struct node { +- int deleted; ++ bool deleted; + char *name; + struct property *proplist; + struct node *children; +@@ -158,6 +178,12 @@ struct node { + int addr_cells, size_cells; + + struct label *labels; ++ ++ int is_root; ++ int is_plugin; ++ struct fixup *fixups; ++ struct symbol *symbols; ++ struct fixup_entry *local_fixups; + }; + + #define for_each_label_withdel(l0, l) \ +@@ -181,6 +207,18 @@ struct node { + for_each_child_withdel(n, c) \ + if (!(c)->deleted) + ++#define for_each_fixup(n, f) \ ++ for ((f) = (n)->fixups; (f); (f) = (f)->next) ++ ++#define for_each_fixup_entry(f, fe) \ ++ for ((fe) = (f)->entries; (fe); (fe) = (fe)->next) ++ ++#define for_each_symbol(n, s) \ ++ for ((s) = (n)->symbols; (s); (s) = (s)->next) ++ ++#define for_each_local_fixup_entry(n, fe) \ ++ for ((fe) = (n)->local_fixups; (fe); (fe) = (fe)->next) ++ + void add_label(struct label **labels, char *label); + void delete_labels(struct label **labels); + +@@ -247,8 +285,8 @@ void sort_tree(struct boot_info *bi); + + /* Checks */ + +-void parse_checks_option(bool warn, bool error, const char *optarg); +-void process_checks(int force, struct boot_info *bi); ++void parse_checks_option(bool warn, bool error, const char *arg); ++void process_checks(bool force, struct boot_info *bi); + + /* Flattened trees */ + +--- a/scripts/dtc/flattree.c ++++ b/scripts/dtc/flattree.c +@@ -261,7 +261,13 @@ static void flatten_tree(struct node *tr + { + struct property *prop; + struct node *child; +- int seen_name_prop = 0; ++ bool seen_name_prop = false; ++ struct symbol *sym; ++ struct fixup *f; ++ struct fixup_entry *fe; ++ char *name, *s; ++ const char *fullpath; ++ int namesz, nameoff, vallen; + + if (tree->deleted) + return; +@@ -276,10 +282,8 @@ static void flatten_tree(struct node *tr + emit->align(etarget, sizeof(cell_t)); + + for_each_property(tree, prop) { +- int nameoff; +- + if (streq(prop->name, "name")) +- seen_name_prop = 1; ++ seen_name_prop = true; + + nameoff = stringtable_insert(strbuf, prop->name); + +@@ -310,6 +314,139 @@ static void flatten_tree(struct node *tr + flatten_tree(child, emit, etarget, strbuf, vi); + } + ++ if (!symbol_fixup_support) ++ goto no_symbols; ++ ++ /* add the symbol nodes (if any) */ ++ if (tree->symbols) { ++ ++ emit->beginnode(etarget, NULL); ++ emit->string(etarget, "__symbols__", 0); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ for_each_symbol(tree, sym) { ++ ++ vallen = strlen(sym->node->fullpath); ++ ++ nameoff = stringtable_insert(strbuf, sym->label->label); ++ ++ emit->property(etarget, NULL); ++ emit->cell(etarget, vallen + 1); ++ emit->cell(etarget, nameoff); ++ ++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) ++ emit->align(etarget, 8); ++ ++ emit->string(etarget, sym->node->fullpath, ++ strlen(sym->node->fullpath)); ++ emit->align(etarget, sizeof(cell_t)); ++ } ++ ++ emit->endnode(etarget, NULL); ++ } ++ ++ /* add the fixup nodes */ ++ if (tree->fixups) { ++ ++ /* emit the external fixups */ ++ emit->beginnode(etarget, NULL); ++ emit->string(etarget, "__fixups__", 0); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ for_each_fixup(tree, f) { ++ ++ namesz = 0; ++ for_each_fixup_entry(f, fe) { ++ fullpath = fe->node->fullpath; ++ if (fullpath[0] == '\0') ++ fullpath = "/"; ++ namesz += strlen(fullpath) + 1; ++ namesz += strlen(fe->prop->name) + 1; ++ namesz += 32; /* space for : + '\0' */ ++ } ++ ++ name = xmalloc(namesz); ++ ++ s = name; ++ for_each_fixup_entry(f, fe) { ++ fullpath = fe->node->fullpath; ++ if (fullpath[0] == '\0') ++ fullpath = "/"; ++ snprintf(s, name + namesz - s, "%s:%s:%d", ++ fullpath, ++ fe->prop->name, fe->offset); ++ s += strlen(s) + 1; ++ } ++ ++ nameoff = stringtable_insert(strbuf, f->ref); ++ vallen = s - name - 1; ++ ++ emit->property(etarget, NULL); ++ emit->cell(etarget, vallen + 1); ++ emit->cell(etarget, nameoff); ++ ++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) ++ emit->align(etarget, 8); ++ ++ emit->string(etarget, name, vallen); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ free(name); ++ } ++ ++ emit->endnode(etarget, tree->labels); ++ } ++ ++ /* add the local fixup property */ ++ if (tree->local_fixups) { ++ ++ /* emit the external fixups */ ++ emit->beginnode(etarget, NULL); ++ emit->string(etarget, "__local_fixups__", 0); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ namesz = 0; ++ for_each_local_fixup_entry(tree, fe) { ++ fullpath = fe->node->fullpath; ++ if (fullpath[0] == '\0') ++ fullpath = "/"; ++ namesz += strlen(fullpath) + 1; ++ namesz += strlen(fe->prop->name) + 1; ++ namesz += 32; /* space for : + '\0' */ ++ } ++ ++ name = xmalloc(namesz); ++ ++ s = name; ++ for_each_local_fixup_entry(tree, fe) { ++ fullpath = fe->node->fullpath; ++ if (fullpath[0] == '\0') ++ fullpath = "/"; ++ snprintf(s, name + namesz - s, "%s:%s:%d", ++ fullpath, fe->prop->name, ++ fe->offset); ++ s += strlen(s) + 1; ++ } ++ ++ nameoff = stringtable_insert(strbuf, "fixup"); ++ vallen = s - name - 1; ++ ++ emit->property(etarget, NULL); ++ emit->cell(etarget, vallen + 1); ++ emit->cell(etarget, nameoff); ++ ++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) ++ emit->align(etarget, 8); ++ ++ emit->string(etarget, name, vallen); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ free(name); ++ ++ emit->endnode(etarget, tree->labels); ++ } ++ ++no_symbols: + emit->endnode(etarget, tree->labels); + } + +--- a/scripts/dtc/fstree.c ++++ b/scripts/dtc/fstree.c +@@ -37,26 +37,26 @@ static struct node *read_fstree(const ch + tree = build_node(NULL, NULL); + + while ((de = readdir(d)) != NULL) { +- char *tmpnam; ++ char *tmpname; + + if (streq(de->d_name, ".") + || streq(de->d_name, "..")) + continue; + +- tmpnam = join_path(dirname, de->d_name); ++ tmpname = join_path(dirname, de->d_name); + +- if (lstat(tmpnam, &st) < 0) +- die("stat(%s): %s\n", tmpnam, strerror(errno)); ++ if (lstat(tmpname, &st) < 0) ++ die("stat(%s): %s\n", tmpname, strerror(errno)); + + if (S_ISREG(st.st_mode)) { + struct property *prop; + FILE *pfile; + +- pfile = fopen(tmpnam, "r"); ++ pfile = fopen(tmpname, "rb"); + if (! pfile) { + fprintf(stderr, + "WARNING: Cannot open %s: %s\n", +- tmpnam, strerror(errno)); ++ tmpname, strerror(errno)); + } else { + prop = build_property(xstrdup(de->d_name), + data_copy_file(pfile, +@@ -67,12 +67,12 @@ static struct node *read_fstree(const ch + } else if (S_ISDIR(st.st_mode)) { + struct node *newchild; + +- newchild = read_fstree(tmpnam); ++ newchild = read_fstree(tmpname); + newchild = name_node(newchild, xstrdup(de->d_name)); + add_child(tree, newchild); + } + +- free(tmpnam); ++ free(tmpname); + } + + closedir(d); +--- a/scripts/dtc/livetree.c ++++ b/scripts/dtc/livetree.c +@@ -511,7 +511,9 @@ struct node *get_node_by_phandle(struct + + struct node *get_node_by_ref(struct node *tree, const char *ref) + { +- if (ref[0] == '/') ++ if (streq(ref, "/")) ++ return tree; ++ else if (ref[0] == '/') + return get_node_by_path(tree, ref); + else + return get_node_by_label(tree, ref); +--- a/scripts/dtc/srcpos.c ++++ b/scripts/dtc/srcpos.c +@@ -34,7 +34,7 @@ struct search_path { + static struct search_path *search_path_head, **search_path_tail; + + +-static char *dirname(const char *path) ++static char *get_dirname(const char *path) + { + const char *slash = strrchr(path, '/'); + +@@ -77,7 +77,7 @@ static char *try_open(const char *dirnam + else + fullname = join_path(dirname, fname); + +- *fp = fopen(fullname, "r"); ++ *fp = fopen(fullname, "rb"); + if (!*fp) { + free(fullname); + fullname = NULL; +@@ -150,7 +150,7 @@ void srcfile_push(const char *fname) + srcfile = xmalloc(sizeof(*srcfile)); + + srcfile->f = srcfile_relative_open(fname, &srcfile->name); +- srcfile->dir = dirname(srcfile->name); ++ srcfile->dir = get_dirname(srcfile->name); + srcfile->prev = current_srcfile; + + srcfile->lineno = 1; +@@ -159,7 +159,7 @@ void srcfile_push(const char *fname) + current_srcfile = srcfile; + } + +-int srcfile_pop(void) ++bool srcfile_pop(void) + { + struct srcfile_state *srcfile = current_srcfile; + +@@ -177,7 +177,7 @@ int srcfile_pop(void) + * fix this we could either allocate all the files from a + * table, or use a pool allocator. */ + +- return current_srcfile ? 1 : 0; ++ return current_srcfile ? true : false; + } + + void srcfile_add_search_path(const char *dirname) +@@ -290,42 +290,27 @@ srcpos_string(struct srcpos *pos) + return pos_str; + } + +-void +-srcpos_verror(struct srcpos *pos, char const *fmt, va_list va) ++void srcpos_verror(struct srcpos *pos, const char *prefix, ++ const char *fmt, va_list va) + { +- const char *srcstr; +- +- srcstr = srcpos_string(pos); ++ char *srcstr; + +- fprintf(stderr, "Error: %s ", srcstr); +- vfprintf(stderr, fmt, va); +- fprintf(stderr, "\n"); +-} ++ srcstr = srcpos_string(pos); + +-void +-srcpos_error(struct srcpos *pos, char const *fmt, ...) +-{ +- va_list va; ++ fprintf(stderr, "%s: %s ", prefix, srcstr); ++ vfprintf(stderr, fmt, va); ++ fprintf(stderr, "\n"); + +- va_start(va, fmt); +- srcpos_verror(pos, fmt, va); +- va_end(va); ++ free(srcstr); + } + +- +-void +-srcpos_warn(struct srcpos *pos, char const *fmt, ...) ++void srcpos_error(struct srcpos *pos, const char *prefix, ++ const char *fmt, ...) + { +- const char *srcstr; + va_list va; +- va_start(va, fmt); +- +- srcstr = srcpos_string(pos); +- +- fprintf(stderr, "Warning: %s ", srcstr); +- vfprintf(stderr, fmt, va); +- fprintf(stderr, "\n"); + ++ va_start(va, fmt); ++ srcpos_verror(pos, prefix, fmt, va); + va_end(va); + } + +--- a/scripts/dtc/srcpos.h ++++ b/scripts/dtc/srcpos.h +@@ -21,6 +21,7 @@ + #define _SRCPOS_H_ + + #include ++#include + + struct srcfile_state { + FILE *f; +@@ -55,7 +56,7 @@ extern struct srcfile_state *current_src + FILE *srcfile_relative_open(const char *fname, char **fullnamep); + + void srcfile_push(const char *fname); +-int srcfile_pop(void); ++bool srcfile_pop(void); + + /** + * Add a new directory to the search path for input files +@@ -106,12 +107,12 @@ extern struct srcpos *srcpos_copy(struct + extern char *srcpos_string(struct srcpos *pos); + extern void srcpos_dump(struct srcpos *pos); + +-extern void srcpos_verror(struct srcpos *pos, char const *, va_list va) +- __attribute__((format(printf, 2, 0))); +-extern void srcpos_error(struct srcpos *pos, char const *, ...) +- __attribute__((format(printf, 2, 3))); +-extern void srcpos_warn(struct srcpos *pos, char const *, ...) +- __attribute__((format(printf, 2, 3))); ++extern void srcpos_verror(struct srcpos *pos, const char *prefix, ++ const char *fmt, va_list va) ++ __attribute__((format(printf, 3, 0))); ++extern void srcpos_error(struct srcpos *pos, const char *prefix, ++ const char *fmt, ...) ++ __attribute__((format(printf, 3, 4))); + + extern void srcpos_set_line(char *f, int l); + +--- a/scripts/dtc/treesource.c ++++ b/scripts/dtc/treesource.c +@@ -26,12 +26,12 @@ extern int yyparse(void); + extern YYLTYPE yylloc; + + struct boot_info *the_boot_info; +-int treesource_error; ++bool treesource_error; + + struct boot_info *dt_from_source(const char *fname) + { + the_boot_info = NULL; +- treesource_error = 0; ++ treesource_error = false; + + srcfile_push(fname); + yyin = current_srcfile->f; +@@ -54,9 +54,9 @@ static void write_prefix(FILE *f, int le + fputc('\t', f); + } + +-static int isstring(char c) ++static bool isstring(char c) + { +- return (isprint(c) ++ return (isprint((unsigned char)c) + || (c == '\0') + || strchr("\a\b\t\n\v\f\r", c)); + } +@@ -109,7 +109,7 @@ static void write_propval_string(FILE *f + break; + case '\0': + fprintf(f, "\", "); +- while (m && (m->offset < i)) { ++ while (m && (m->offset <= (i + 1))) { + if (m->type == LABEL) { + assert(m->offset == (i+1)); + fprintf(f, "%s: ", m->ref); +@@ -119,7 +119,7 @@ static void write_propval_string(FILE *f + fprintf(f, "\""); + break; + default: +- if (isprint(c)) ++ if (isprint((unsigned char)c)) + fprintf(f, "%c", c); + else + fprintf(f, "\\x%02hhx", c); +@@ -178,7 +178,7 @@ static void write_propval_bytes(FILE *f, + m = m->next; + } + +- fprintf(f, "%02hhx", *bp++); ++ fprintf(f, "%02hhx", (unsigned char)(*bp++)); + if ((const void *)bp >= propend) + break; + fprintf(f, " "); +--- a/scripts/dtc/util.c ++++ b/scripts/dtc/util.c +@@ -39,11 +39,11 @@ + char *xstrdup(const char *s) + { + int len = strlen(s) + 1; +- char *dup = xmalloc(len); ++ char *d = xmalloc(len); + +- memcpy(dup, s, len); ++ memcpy(d, s, len); + +- return dup; ++ return d; + } + + char *join_path(const char *path, const char *name) +@@ -70,7 +70,7 @@ char *join_path(const char *path, const + return str; + } + +-int util_is_printable_string(const void *data, int len) ++bool util_is_printable_string(const void *data, int len) + { + const char *s = data; + const char *ss, *se; +@@ -87,7 +87,7 @@ int util_is_printable_string(const void + + while (s < se) { + ss = s; +- while (s < se && *s && isprint(*s)) ++ while (s < se && *s && isprint((unsigned char)*s)) + s++; + + /* not zero, or not done yet */ +@@ -219,10 +219,6 @@ int utilfdt_read_err_len(const char *fil + if (offset == bufsize) { + bufsize *= 2; + buf = xrealloc(buf, bufsize); +- if (!buf) { +- ret = ENOMEM; +- break; +- } + } + + ret = read(fd, &buf[offset], bufsize - offset); +@@ -375,9 +371,9 @@ void utilfdt_print_data(const char *data + const uint32_t *cell = (const uint32_t *)data; + + printf(" = <"); +- for (i = 0; i < len; i += 4) ++ for (i = 0, len /= 4; i < len; i++) + printf("0x%08x%s", fdt32_to_cpu(cell[i]), +- i < (len - 4) ? " " : ""); ++ i < (len - 1) ? " " : ""); + printf(">"); + } else { + printf(" = ["); +--- a/scripts/dtc/util.h ++++ b/scripts/dtc/util.h +@@ -2,6 +2,7 @@ + #define _UTIL_H + + #include ++#include + #include + + /* +@@ -33,6 +34,7 @@ static inline void __attribute__((noretu + va_start(ap, str); + fprintf(stderr, "FATAL ERROR: "); + vfprintf(stderr, str, ap); ++ va_end(ap); + exit(1); + } + +@@ -68,7 +70,7 @@ extern char *join_path(const char *path, + * @param len The string length including terminator + * @return 1 if a valid printable string, 0 if not + */ +-int util_is_printable_string(const void *data, int len); ++bool util_is_printable_string(const void *data, int len); + + /* + * Parse an escaped character starting at index i in string s. The resulting +--- a/scripts/dtc/version_gen.h ++++ b/scripts/dtc/version_gen.h +@@ -1 +1 @@ +-#define DTC_VERSION "DTC 1.4.0-dirty" ++#define DTC_VERSION "DTC 1.4.1-g36c70742" diff --git a/target/linux/brcm2708/patches-4.1/0023-scripts-Add-mkknlimg-and-knlinfo-scripts-from-tools-.patch b/target/linux/brcm2708/patches-4.1/0023-scripts-Add-mkknlimg-and-knlinfo-scripts-from-tools-.patch new file mode 100644 index 0000000..525dbdc --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0023-scripts-Add-mkknlimg-and-knlinfo-scripts-from-tools-.patch @@ -0,0 +1,481 @@ +From 59cf4bf51eea78b4314cfabff3023f1a95358fa6 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 11 May 2015 09:00:42 +0100 +Subject: [PATCH 023/203] scripts: Add mkknlimg and knlinfo scripts from tools + repo + +The Raspberry Pi firmware looks for a trailer on the kernel image to +determine whether it was compiled with Device Tree support enabled. +If the firmware finds a kernel without this trailer, or which has a +trailer indicating that it isn't DT-capable, it disables DT support +and reverts to using ATAGs. + +The mkknlimg utility adds that trailer, having first analysed the +image to look for signs of DT support and the kernel version string. + +knlinfo displays the contents of the trailer in the given kernel image. + +scripts/mkknlimg: Add support for ARCH_BCM2835 + +Add a new trailer field indicating whether this is an ARCH_BCM2835 +build, as opposed to MACH_BCM2708/9. If the loader finds this flag +is set it changes the default base dtb file name from bcm270x... +to bcm283y... + +Also update knlinfo to show the status of the field. +--- + scripts/knlinfo | 168 +++++++++++++++++++++++++++++++++ + scripts/mkknlimg | 275 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 443 insertions(+) + create mode 100755 scripts/knlinfo + create mode 100755 scripts/mkknlimg + +--- /dev/null ++++ b/scripts/knlinfo +@@ -0,0 +1,168 @@ ++#!/usr/bin/env perl ++# ---------------------------------------------------------------------- ++# knlinfo by Phil Elwell for Raspberry Pi ++# ++# (c) 2014,2015 Raspberry Pi (Trading) Limited ++# ++# Licensed under the terms of the GNU General Public License. ++# ---------------------------------------------------------------------- ++ ++use strict; ++use integer; ++ ++use Fcntl ":seek"; ++ ++my $trailer_magic = 'RPTL'; ++ ++my %atom_formats = ++( ++ 'DTOK' => \&format_bool, ++ 'KVer' => \&format_string, ++ '283x' => \&format_bool, ++); ++ ++if (@ARGV != 1) ++{ ++ print ("Usage: knlinfo \n"); ++ exit(1); ++} ++ ++my $kernel_file = $ARGV[0]; ++ ++ ++my ($atoms, $pos) = read_trailer($kernel_file); ++ ++exit(1) if (!$atoms); ++ ++printf("Kernel trailer found at %d/0x%x:\n", $pos, $pos); ++ ++foreach my $atom (@$atoms) ++{ ++ printf(" %s: %s\n", $atom->[0], format_atom($atom)); ++} ++ ++exit(0); ++ ++sub read_trailer ++{ ++ my ($kernel_file) = @_; ++ my $fh; ++ ++ if (!open($fh, '<', $kernel_file)) ++ { ++ print ("* Failed to open '$kernel_file'\n"); ++ return undef; ++ } ++ ++ if (!seek($fh, -12, SEEK_END)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ ++ my $last_bytes; ++ sysread($fh, $last_bytes, 12); ++ ++ my ($trailer_len, $data_len, $magic) = unpack('VVa4', $last_bytes); ++ ++ if (($magic ne $trailer_magic) || ($data_len != 4)) ++ { ++ print ("* no trailer\n"); ++ return undef; ++ } ++ if (!seek($fh, -12, SEEK_END)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ ++ $trailer_len -= 12; ++ ++ while ($trailer_len > 0) ++ { ++ if ($trailer_len < 8) ++ { ++ print ("* truncated atom header in trailer\n"); ++ return undef; ++ } ++ if (!seek($fh, -8, SEEK_CUR)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ $trailer_len -= 8; ++ ++ my $atom_hdr; ++ sysread($fh, $atom_hdr, 8); ++ my ($atom_len, $atom_type) = unpack('Va4', $atom_hdr); ++ ++ if ($trailer_len < $atom_len) ++ { ++ print ("* truncated atom data in trailer\n"); ++ return undef; ++ } ++ ++ my $rounded_len = (($atom_len + 3) & ~3); ++ if (!seek($fh, -(8 + $rounded_len), SEEK_CUR)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ $trailer_len -= $rounded_len; ++ ++ my $atom_data; ++ sysread($fh, $atom_data, $atom_len); ++ ++ if (!seek($fh, -$atom_len, SEEK_CUR)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ ++ push @$atoms, [ $atom_type, $atom_data ]; ++ } ++ ++ if (($$atoms[-1][0] eq "\x00\x00\x00\x00") && ++ ($$atoms[-1][1] eq "")) ++ { ++ pop @$atoms; ++ } ++ else ++ { ++ print ("* end marker missing from trailer\n"); ++ } ++ ++ return ($atoms, tell($fh)); ++} ++ ++sub format_atom ++{ ++ my ($atom) = @_; ++ ++ my $format_func = $atom_formats{$atom->[0]} || \&format_hex; ++ return $format_func->($atom->[1]); ++} ++ ++sub format_bool ++{ ++ my ($data) = @_; ++ return unpack('V', $data) ? 'true' : 'false'; ++} ++ ++sub format_int ++{ ++ my ($data) = @_; ++ return unpack('V', $data); ++} ++ ++sub format_string ++{ ++ my ($data) = @_; ++ return '"'.$data.'"'; ++} ++ ++sub format_hex ++{ ++ my ($data) = @_; ++ return unpack('H*', $data); ++} +--- /dev/null ++++ b/scripts/mkknlimg +@@ -0,0 +1,275 @@ ++#!/usr/bin/env perl ++# ---------------------------------------------------------------------- ++# mkknlimg by Phil Elwell for Raspberry Pi ++# based on extract-ikconfig by Dick Streefland ++# ++# (c) 2009,2010 Dick Streefland ++# (c) 2014,2015 Raspberry Pi (Trading) Limited ++# ++# Licensed under the terms of the GNU General Public License. ++# ---------------------------------------------------------------------- ++ ++use strict; ++use warnings; ++use integer; ++ ++my $trailer_magic = 'RPTL'; ++ ++my $tmpfile1 = "/tmp/mkknlimg_$$.1"; ++my $tmpfile2 = "/tmp/mkknlimg_$$.2"; ++ ++my $dtok = 0; ++my $is_283x = 0; ++ ++while (@ARGV && ($ARGV[0] =~ /^-/)) ++{ ++ my $arg = shift(@ARGV); ++ if ($arg eq '--dtok') ++ { ++ $dtok = 1; ++ } ++ elsif ($arg eq '--283x') ++ { ++ $is_283x = 1; ++ } ++ else ++ { ++ print ("* Unknown option '$arg'\n"); ++ usage(); ++ } ++} ++ ++usage() if (@ARGV != 2); ++ ++my $kernel_file = $ARGV[0]; ++my $out_file = $ARGV[1]; ++ ++if (! -r $kernel_file) ++{ ++ print ("* File '$kernel_file' not found\n"); ++ usage(); ++} ++ ++my @wanted_config_lines = ++( ++ 'CONFIG_BCM2708_DT', ++ 'CONFIG_ARCH_BCM2835' ++); ++ ++my @wanted_strings = ++( ++ 'bcm2708_fb', ++ 'brcm,bcm2835-mmc', ++ 'brcm,bcm2835-sdhost', ++ 'brcm,bcm2708-pinctrl', ++ 'brcm,bcm2835-gpio', ++ 'brcm,bcm2835-pm-wdt' ++); ++ ++my $res = try_extract($kernel_file, $tmpfile1); ++$res = try_decompress('\037\213\010', 'xy', 'gunzip', 0, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('\3757zXZ\000', 'abcde', 'unxz --single-stream', -1, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('BZh', 'xy', 'bunzip2', 0, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('\135\0\0\0', 'xxx', 'unlzma', 0, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('\211\114\132', 'xy', 'lzop -d', 0, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('\002\041\114\030', 'xy', 'lz4 -d', 1, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++ ++my $append_trailer; ++my $trailer; ++my $kver = '?'; ++ ++$append_trailer = $dtok; ++ ++if ($res) ++{ ++ $kver = $res->{''} || '?'; ++ print("Version: $kver\n"); ++ ++ $append_trailer = $dtok; ++ if (!$dtok) ++ { ++ if (config_bool($res, 'bcm2708_fb') || ++ config_bool($res, 'brcm,bcm2835-mmc') || ++ config_bool($res, 'brcm,bcm2835-sdhost')) ++ { ++ $dtok ||= config_bool($res, 'CONFIG_BCM2708_DT'); ++ $dtok ||= config_bool($res, 'CONFIG_ARCH_BCM2835'); ++ $dtok ||= config_bool($res, 'brcm,bcm2708-pinctrl'); ++ $dtok ||= config_bool($res, 'brcm,bcm2835-gpio'); ++ $is_283x ||= config_bool($res, 'CONFIG_ARCH_BCM2835'); ++ $is_283x ||= config_bool($res, 'brcm,bcm2835-pm-wdt'); ++ $append_trailer = 1; ++ } ++ else ++ { ++ print ("* This doesn't look like a Raspberry Pi kernel. In pass-through mode.\n"); ++ } ++ } ++} ++elsif (!$dtok) ++{ ++ print ("* Is this a valid kernel? In pass-through mode.\n"); ++} ++ ++if ($append_trailer) ++{ ++ printf("DT: %s\n", $dtok ? "y" : "n"); ++ printf("283x: %s\n", $is_283x ? "y" : "n"); ++ ++ my @atoms; ++ ++ push @atoms, [ $trailer_magic, pack('V', 0) ]; ++ push @atoms, [ 'KVer', $kver ]; ++ push @atoms, [ 'DTOK', pack('V', $dtok) ]; ++ push @atoms, [ '283x', pack('V', $is_283x) ]; ++ ++ $trailer = pack_trailer(\@atoms); ++ $atoms[0]->[1] = pack('V', length($trailer)); ++ ++ $trailer = pack_trailer(\@atoms); ++} ++ ++my $ofh; ++my $total_len = 0; ++ ++if ($out_file eq $kernel_file) ++{ ++ die "* Failed to open '$out_file' for append\n" ++ if (!open($ofh, '>>', $out_file)); ++ $total_len = tell($ofh); ++} ++else ++{ ++ die "* Failed to open '$kernel_file'\n" ++ if (!open(my $ifh, '<', $kernel_file)); ++ die "* Failed to create '$out_file'\n" ++ if (!open($ofh, '>', $out_file)); ++ ++ my $copybuf; ++ while (1) ++ { ++ my $bytes = sysread($ifh, $copybuf, 64*1024); ++ last if (!$bytes); ++ syswrite($ofh, $copybuf, $bytes); ++ $total_len += $bytes; ++ } ++ close($ifh); ++} ++ ++if ($trailer) ++{ ++ # Pad to word-alignment ++ syswrite($ofh, "\x000\x000\x000", (-$total_len & 0x3)); ++ syswrite($ofh, $trailer); ++} ++ ++close($ofh); ++ ++exit($trailer ? 0 : 1); ++ ++END { ++ unlink($tmpfile1) if ($tmpfile1); ++ unlink($tmpfile2) if ($tmpfile2); ++} ++ ++ ++sub usage ++{ ++ print ("Usage: mkknlimg [--dtok] [--283x] \n"); ++ exit(1); ++} ++ ++sub try_extract ++{ ++ my ($knl, $tmp) = @_; ++ ++ my $ver = `strings "$knl" | grep -a -E "^Linux version [1-9]"`; ++ ++ return undef if (!$ver); ++ ++ chomp($ver); ++ ++ my $res = { ''=>$ver }; ++ my $string_pattern = '^('.join('|', @wanted_strings).')$'; ++ ++ my @matches = `strings \"$knl\" | grep -E \"$string_pattern\"`; ++ foreach my $match (@matches) ++ { ++ chomp($match); ++ $res->{$match} = 1; ++ } ++ ++ my $config_pattern = '^('.join('|', @wanted_config_lines).')=(.*)$'; ++ my $cf1 = 'IKCFG_ST\037\213\010'; ++ my $cf2 = '0123456789'; ++ ++ my $pos = `tr "$cf1\n$cf2" "\n$cf2=" < "$knl" | grep -abo "^$cf2"`; ++ if ($pos) ++ { ++ $pos =~ s/:.*[\r\n]*$//s; ++ $pos += 8; ++ my $err = (system("tail -c+$pos \"$knl\" | zcat > $tmp 2> /dev/null") >> 8); ++ if (($err == 0) || ($err == 2)) ++ { ++ if (open(my $fh, '<', $tmp)) ++ { ++ while (my $line = <$fh>) ++ { ++ chomp($line); ++ $res->{$1} = $2 if ($line =~ /$config_pattern/); ++ } ++ ++ close($fh); ++ } ++ } ++ } ++ ++ return $res; ++} ++ ++ ++sub try_decompress ++{ ++ my ($magic, $subst, $zcat, $idx, $knl, $tmp1, $tmp2) = @_; ++ ++ my $pos = `tr "$magic\n$subst" "\n$subst=" < "$knl" | grep -abo "^$subst"`; ++ if ($pos) ++ { ++ chomp($pos); ++ $pos = (split(/[\r\n]+/, $pos))[$idx]; ++ return undef if (!defined($pos)); ++ $pos =~ s/:.*[\r\n]*$//s; ++ my $cmd = "tail -c+$pos \"$knl\" | $zcat > $tmp2 2> /dev/null"; ++ my $err = (system($cmd) >> 8); ++ return undef if (($err != 0) && ($err != 2)); ++ ++ return try_extract($tmp2, $tmp1); ++ } ++ ++ return undef; ++} ++ ++sub pack_trailer ++{ ++ my ($atoms) = @_; ++ my $trailer = pack('VV', 0, 0); ++ for (my $i = $#$atoms; $i>=0; $i--) ++ { ++ my $atom = $atoms->[$i]; ++ $trailer .= pack('a*x!4Va4', $atom->[1], length($atom->[1]), $atom->[0]); ++ } ++ return $trailer; ++} ++ ++sub config_bool ++{ ++ my ($configs, $wanted) = @_; ++ my $val = $configs->{$wanted} || 'n'; ++ return (($val eq 'y') || ($val eq '1')); ++} diff --git a/target/linux/brcm2708/patches-4.1/0024-fdt-Add-support-for-the-CONFIG_CMDLINE_EXTEND-option.patch b/target/linux/brcm2708/patches-4.1/0024-fdt-Add-support-for-the-CONFIG_CMDLINE_EXTEND-option.patch new file mode 100755 index 0000000..e68d7b3 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0024-fdt-Add-support-for-the-CONFIG_CMDLINE_EXTEND-option.patch @@ -0,0 +1,58 @@ +From e2ca00ccfecacf743841367a3dab7092f2ce3ffc Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 5 Dec 2014 17:26:26 +0000 +Subject: [PATCH 024/203] fdt: Add support for the CONFIG_CMDLINE_EXTEND option + +--- + drivers/of/fdt.c | 29 ++++++++++++++++++++++++----- + 1 file changed, 24 insertions(+), 5 deletions(-) + +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -933,22 +933,38 @@ int __init early_init_dt_scan_chosen(uns + + /* Retrieve command line */ + p = of_get_flat_dt_prop(node, "bootargs", &l); +- if (p != NULL && l > 0) +- strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); +- p = of_get_flat_dt_prop(node, "bootargs-append", &l); +- if (p != NULL && l > 0) +- strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else + * managed to set the command line, unless CONFIG_CMDLINE_FORCE + * is set in which case we override whatever was found earlier. ++ * ++ * However, it can be useful to be able to treat the default as ++ * a starting point to be extended using CONFIG_CMDLINE_EXTEND. + */ ++ ((char *)data)[0] = '\0'; ++ + #ifdef CONFIG_CMDLINE +-#ifndef CONFIG_CMDLINE_FORCE +- if (!((char *)data)[0]) ++ strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); ++ ++ if (p != NULL && l > 0) { ++#if defined(CONFIG_CMDLINE_EXTEND) ++ int len = strlen(data); ++ if (len > 0) { ++ strlcat(data, " ", COMMAND_LINE_SIZE); ++ len++; ++ } ++ strlcpy((char *)data + len, p, min((int)l, COMMAND_LINE_SIZE - len)); ++#elif defined(CONFIG_CMDLINE_FORCE) ++ pr_warning("Ignoring bootargs property (using the default kernel command line)\n"); ++#else ++ /* Neither extend nor force - just override */ ++ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); + #endif +- strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); ++ } ++#else /* CONFIG_CMDLINE */ ++ if (p != NULL && l > 0) ++ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); + #endif /* CONFIG_CMDLINE */ + + pr_debug("Command line is: %s\n", (char*)data); diff --git a/target/linux/brcm2708/patches-4.1/0025-BCM2708-Add-core-Device-Tree-support.patch b/target/linux/brcm2708/patches-4.1/0025-BCM2708-Add-core-Device-Tree-support.patch new file mode 100644 index 0000000..c3dad4c --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0025-BCM2708-Add-core-Device-Tree-support.patch @@ -0,0 +1,3750 @@ +From 00bde9c19f378c337830838a67fb9bdf14019ebc Mon Sep 17 00:00:00 2001 +From: notro +Date: Wed, 9 Jul 2014 14:46:08 +0200 +Subject: [PATCH 025/203] BCM2708: Add core Device Tree support + +Add the bare minimum needed to boot BCM2708 from a Device Tree. + +Signed-off-by: Noralf Tronnes + +BCM2708: DT: change 'axi' nodename to 'soc' + +Change DT node named 'axi' to 'soc' so it matches ARCH_BCM2835. +The VC4 bootloader fills in certain properties in the 'axi' subtree, +but since this is part of an upstreaming effort, the name is changed. + +Signed-off-by: Noralf Tronnes notro@tronnes.org + +BCM2708_DT: Correct length of the peripheral space +--- + arch/arm/boot/dts/Makefile | 27 ++ + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 140 ++++++ + arch/arm/boot/dts/bcm2708-rpi-b.dts | 130 ++++++ + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 18 + + arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 51 +++ + arch/arm/boot/dts/bcm2708.dtsi | 19 + + arch/arm/boot/dts/bcm2708_common.dtsi | 230 ++++++++++ + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 140 ++++++ + arch/arm/boot/dts/bcm2709.dtsi | 70 +++ + arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 45 +- + arch/arm/boot/dts/bcm2835-rpi-b.dts | 29 +- + arch/arm/boot/dts/bcm2835-rpi.dtsi | 97 +++- + arch/arm/boot/dts/bcm2835.dtsi | 45 +- + arch/arm/boot/dts/overlays/Makefile | 57 +++ + arch/arm/boot/dts/overlays/README | 493 +++++++++++++++++++++ + arch/arm/boot/dts/overlays/ads7846-overlay.dts | 83 ++++ + .../dts/overlays/bmp085_i2c-sensor-overlay.dts | 23 + + arch/arm/boot/dts/overlays/dht11-overlay.dts | 39 ++ + arch/arm/boot/dts/overlays/enc28j60-overlay.dts | 50 +++ + .../boot/dts/overlays/hifiberry-amp-overlay.dts | 39 ++ + .../boot/dts/overlays/hifiberry-dac-overlay.dts | 34 ++ + .../dts/overlays/hifiberry-dacplus-overlay.dts | 39 ++ + .../boot/dts/overlays/hifiberry-digi-overlay.dts | 39 ++ + arch/arm/boot/dts/overlays/hy28a-overlay.dts | 87 ++++ + arch/arm/boot/dts/overlays/hy28b-overlay.dts | 142 ++++++ + arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts | 49 ++ + arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts | 13 + + arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts | 39 ++ + .../boot/dts/overlays/iqaudio-dacplus-overlay.dts | 39 ++ + arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts | 57 +++ + .../arm/boot/dts/overlays/mcp2515-can0-overlay.dts | 69 +++ + arch/arm/boot/dts/overlays/mmc-overlay.dts | 19 + + arch/arm/boot/dts/overlays/mz61581-overlay.dts | 109 +++++ + arch/arm/boot/dts/overlays/piscreen-overlay.dts | 96 ++++ + .../dts/overlays/pitft28-resistive-overlay.dts | 115 +++++ + arch/arm/boot/dts/overlays/pps-gpio-overlay.dts | 34 ++ + arch/arm/boot/dts/overlays/rpi-dac-overlay.dts | 34 ++ + arch/arm/boot/dts/overlays/rpi-display-overlay.dts | 82 ++++ + arch/arm/boot/dts/overlays/rpi-proto-overlay.dts | 39 ++ + arch/arm/boot/dts/overlays/sdhost-overlay.dts | 78 ++++ + arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts | 18 + + arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts | 18 + + arch/arm/boot/dts/overlays/tinylcd35-overlay.dts | 216 +++++++++ + arch/arm/boot/dts/overlays/w1-gpio-overlay.dts | 39 ++ + .../boot/dts/overlays/w1-gpio-pullup-overlay.dts | 41 ++ + 45 files changed, 3316 insertions(+), 54 deletions(-) + create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b-plus.dts + create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b.dts + create mode 100755 arch/arm/boot/dts/bcm2708-rpi-cm.dts + create mode 100644 arch/arm/boot/dts/bcm2708-rpi-cm.dtsi + create mode 100644 arch/arm/boot/dts/bcm2708.dtsi + create mode 100644 arch/arm/boot/dts/bcm2708_common.dtsi + create mode 100644 arch/arm/boot/dts/bcm2709-rpi-2-b.dts + create mode 100644 arch/arm/boot/dts/bcm2709.dtsi + create mode 100644 arch/arm/boot/dts/overlays/Makefile + create mode 100644 arch/arm/boot/dts/overlays/README + create mode 100644 arch/arm/boot/dts/overlays/ads7846-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/dht11-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/enc28j60-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hy28a-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hy28b-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts + create mode 100755 arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/mmc-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/mz61581-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/piscreen-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/pps-gpio-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/rpi-dac-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/rpi-display-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/rpi-proto-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/sdhost-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/tinylcd35-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1,5 +1,21 @@ + ifeq ($(CONFIG_OF),y) + ++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb ++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb ++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-cm.dtb ++dtb-$(CONFIG_BCM2709_DT) += bcm2709-rpi-2-b.dtb ++ ++# Raspberry Pi ++ifeq ($(CONFIG_BCM2708_DT),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(CONFIG_BCM2709_DT),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(CONFIG_ARCH_BCM2835),y) ++ RPI_DT_OVERLAYS=y ++endif ++ + dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb + dtb-$(CONFIG_MACH_ASM9260) += \ +@@ -660,7 +676,18 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt6592-evb.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb ++ ++targets += dtbs dtbs_install ++targets += $(dtb-y) ++ + endif + + always := $(dtb-y) + clean-files := *.dtb ++ ++# Enable fixups to support overlays on BCM2708 platforms ++ifeq ($(RPI_DT_OVERLAYS),y) ++ DTC_FLAGS ?= -@ ++endif ++ ++subdir-y += overlays +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +@@ -0,0 +1,140 @@ ++/dts-v1/; ++ ++/include/ "bcm2708.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ model = "Raspberry Pi Model B+"; ++ ++ aliases { ++ soc = &soc; ++ spi0 = &spi0; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2s = &i2s; ++ gpio = &gpio; ++ intc = &intc; ++ leds = &leds; ++ audio = &audio; ++ sound = &sound; ++ uart0 = &uart0; ++ uart1 = &uart1; ++ clocks = &clocks; ++ }; ++ ++ sound: sound { ++ }; ++}; ++ ++&gpio { ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <18 19 20 21>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&mmc { ++ status = "okay"; ++ bus-width = <4>; ++}; ++ ++&fb { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&leds { ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio 47 0>; ++ }; ++ ++ pwr_led: pwr { ++ label = "led1"; ++ linux,default-trigger = "input"; ++ gpios = <&gpio 35 0>; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ uart0 = <&uart0>,"status"; ++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&pwr_led>,"gpios:4"; ++ pwr_led_activelow = <&pwr_led>,"gpios:8"; ++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ ++ audio = <&audio>,"status"; ++ watchdog = <&watchdog>,"status"; ++ random = <&random>,"status"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts +@@ -0,0 +1,130 @@ ++/dts-v1/; ++ ++/include/ "bcm2708.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ model = "Raspberry Pi Model B"; ++ ++ aliases { ++ soc = &soc; ++ spi0 = &spi0; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2s = &i2s; ++ gpio = &gpio; ++ intc = &intc; ++ leds = &leds; ++ audio = &audio; ++ sound = &sound; ++ uart0 = &uart0; ++ uart1 = &uart1; ++ clocks = &clocks; ++ }; ++ ++ sound: sound { ++ }; ++}; ++ ++&gpio { ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <28 29 30 31>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&mmc { ++ status = "okay"; ++ bus-width = <4>; ++}; ++ ++&fb { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&leds { ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio 16 1>; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ uart0 = <&uart0>,"status"; ++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ ++ audio = <&audio>,"status"; ++ watchdog = <&watchdog>,"status"; ++ random = <&random>,"status"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++ ++/include/ "bcm2708-rpi-cm.dtsi" ++ ++/ { ++ model = "Raspberry Pi Compute Module"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++/ { ++ __overrides__ { ++ uart0 = <&uart0>,"status"; ++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi +@@ -0,0 +1,51 @@ ++/include/ "bcm2708.dtsi" ++ ++/ { ++ aliases { ++ soc = &soc; ++ spi0 = &spi0; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2s = &i2s; ++ gpio = &gpio; ++ intc = &intc; ++ leds = &leds; ++ audio = &audio; ++ sound = &sound; ++ uart0 = &uart0; ++ uart1 = &uart1; ++ clocks = &clocks; ++ }; ++ ++ sound: sound { ++ }; ++}; ++ ++&leds { ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio 47 0>; ++ }; ++}; ++ ++&mmc { ++ status = "okay"; ++ bus-width = <4>; ++}; ++ ++&fb { ++ status = "okay"; ++}; ++ ++&audio { ++ status = "okay"; ++}; ++ ++/ { ++ __overrides__ { ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2708.dtsi +@@ -0,0 +1,19 @@ ++/include/ "bcm2708_common.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ model = "BCM2708"; ++ ++ chosen { ++ /* No padding required - the boot loader can do that. */ ++ bootargs = ""; ++ }; ++ ++ soc { ++ ranges = <0x7e000000 0x20000000 0x01000000>; ++ ++ arm-pmu { ++ compatible = "arm,arm1176-pmu"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -0,0 +1,230 @@ ++/include/ "skeleton.dtsi" ++ ++/ { ++ interrupt-parent = <&intc>; ++ ++ /* Onboard audio */ ++ audio: audio { ++ compatible = "brcm,bcm2835-audio"; ++ brcm,pwm-channels = <8>; ++ status = "disabled"; ++ }; ++ ++ soc: soc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ dma: dma@7e007000 { ++ compatible = "brcm,bcm2835-dma"; ++ reg = <0x7e007000 0xf00>; ++ interrupts = <1 16>, ++ <1 17>, ++ <1 18>, ++ <1 19>, ++ <1 20>, ++ <1 21>, ++ <1 22>, ++ <1 23>, ++ <1 24>, ++ <1 25>, ++ <1 26>, ++ <1 27>, ++ <1 28>; ++ ++ #dma-cells = <1>; ++ brcm,dma-channel-mask = <0x7f35>; ++ }; ++ ++ intc: interrupt-controller { ++ compatible = "brcm,bcm2708-armctrl-ic"; ++ reg = <0x7e00b200 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ watchdog: watchdog@7e100000 { ++ compatible = "brcm,bcm2835-pm-wdt"; ++ reg = <0x7e100000 0x28>; ++ status = "disabled"; ++ }; ++ ++ random: rng@7e104000 { ++ compatible = "brcm,bcm2835-rng"; ++ reg = <0x7e104000 0x10>; ++ status = "disabled"; ++ }; ++ ++ mailbox: mailbox@7e00b800 { ++ compatible = "brcm,bcm2708-vcio"; ++ reg = <0x7e00b880 0x40>; ++ interrupts = <0 1>; ++ }; ++ ++ gpio: gpio { ++ compatible = "brcm,bcm2835-gpio"; ++ reg = <0x7e200000 0xb4>; ++ interrupts = <2 17>, <2 18>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ mmc: mmc@7e300000 { ++ compatible = "brcm,bcm2835-mmc"; ++ reg = <0x7e300000 0x100>; ++ interrupts = <2 30>; ++ clocks = <&clk_mmc>; ++ dmas = <&dma 11>, ++ <&dma 11>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ uart0: uart@7e201000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x7e201000 0x1000>; ++ interrupts = <2 25>; ++ clocks = <&clk_uart0 &clk_apb_p>; ++ clock-names = "uartclk","apb_pclk"; ++ arm,primecell-periphid = <0x00241011>; // For an explanation, see ++ // https://github.com/raspberrypi/linux/commit/13731d862cf5219216533a3b0de052cee4cc5038 ++ status = "disabled"; ++ }; ++ ++ i2s: i2s@7e203000 { ++ compatible = "brcm,bcm2708-i2s"; ++ reg = <0x7e203000 0x20>, ++ <0x7e101098 0x02>; ++ ++ //dmas = <&dma 2>, ++ // <&dma 3>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ spi0: spi@7e204000 { ++ compatible = "brcm,bcm2835-spi"; ++ reg = <0x7e204000 0x1000>; ++ interrupts = <2 22>; ++ clocks = <&clk_spi>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ /* the dma channels */ ++ dmas = <&dma 6>, <&dma 7>; ++ dma-names = "tx", "rx"; ++ /* the chipselects used - <0> means native GPIO ++ * add more gpios if necessary as <&gpio 6 1> ++ * (but do not forget to make them output!) ++ */ ++ cs-gpios = <0>, <0>; ++ }; ++ ++ i2c0: i2c@7e205000 { ++ compatible = "brcm,bcm2708-i2c"; ++ reg = <0x7e205000 0x1000>; ++ interrupts = <2 21>; ++ clocks = <&clk_i2c>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart1: uart@7e215040 { ++ compatible = "brcm,bcm2835-aux-uart", "ns16550"; ++ reg = <0x7e215040 0x40>; ++ interrupts = <1 29>; ++ clock-frequency = <500000000>; ++ reg-shift = <2>; ++ no-loopback-test; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@7e804000 { ++ compatible = "brcm,bcm2708-i2c"; ++ reg = <0x7e804000 0x1000>; ++ interrupts = <2 21>; ++ clocks = <&clk_i2c>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usb: usb@7e980000 { ++ compatible = "brcm,bcm2708-usb"; ++ reg = <0x7e980000 0x10000>, ++ <0x7e006000 0x1000>; ++ interrupts = <2 0>, ++ <1 9>; ++ }; ++ ++ leds: leds { ++ compatible = "gpio-leds"; ++ }; ++ ++ fb: fb { ++ compatible = "brcm,bcm2708-fb"; ++ status = "disabled"; ++ }; ++ ++ vchiq: vchiq { ++ compatible = "brcm,bcm2835-vchiq"; ++ reg = <0x7e00b840 0xf>; ++ interrupts = <0 2>; ++ }; ++ ++ thermal: thermal { ++ compatible = "brcm,bcm2835-thermal"; ++ }; ++ }; ++ ++ clocks: clocks { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ clk_mmc: clock@0 { ++ compatible = "fixed-clock"; ++ reg = <0>; ++ #clock-cells = <0>; ++ clock-output-names = "mmc"; ++ clock-frequency = <250000000>; ++ }; ++ ++ clk_i2c: clock@1 { ++ compatible = "fixed-clock"; ++ reg = <1>; ++ #clock-cells = <0>; ++ clock-output-names = "i2c"; ++ clock-frequency = <250000000>; ++ }; ++ ++ clk_spi: clock@2 { ++ compatible = "fixed-clock"; ++ reg = <2>; ++ #clock-cells = <0>; ++ clock-output-names = "spi"; ++ clock-frequency = <250000000>; ++ }; ++ ++ clk_uart0: clock@3 { ++ compatible = "fixed-clock"; ++ reg = <3>; ++ #clock-cells = <0>; ++ clock-output-names = "uart0_pclk"; ++ clock-frequency = <3000000>; ++ }; ++ ++ clk_apb_p: clock@4 { ++ compatible = "fixed-clock"; ++ reg = <4>; ++ #clock-cells = <0>; ++ clock-output-names = "apb_pclk"; ++ clock-frequency = <126000000>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +@@ -0,0 +1,140 @@ ++/dts-v1/; ++ ++/include/ "bcm2709.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2709"; ++ model = "Raspberry Pi 2 Model B"; ++ ++ aliases { ++ soc = &soc; ++ spi0 = &spi0; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2s = &i2s; ++ gpio = &gpio; ++ intc = &intc; ++ leds = &leds; ++ audio = &audio; ++ sound = &sound; ++ uart0 = &uart0; ++ uart1 = &uart1; ++ clocks = &clocks; ++ }; ++ ++ sound: sound { ++ }; ++}; ++ ++&gpio { ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <18 19 20 21>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&mmc { ++ status = "okay"; ++ bus-width = <4>; ++}; ++ ++&fb { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&leds { ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio 47 0>; ++ }; ++ ++ pwr_led: pwr { ++ label = "led1"; ++ linux,default-trigger = "input"; ++ gpios = <&gpio 35 0>; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ uart0 = <&uart0>,"status"; ++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&pwr_led>,"gpios:4"; ++ pwr_led_activelow = <&pwr_led>,"gpios:8"; ++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ ++ audio = <&audio>,"status"; ++ watchdog = <&watchdog>,"status"; ++ random = <&random>,"status"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/bcm2709.dtsi +@@ -0,0 +1,70 @@ ++/include/ "bcm2708_common.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2709"; ++ model = "BCM2709"; ++ ++ chosen { ++ /* No padding required - the boot loader can do that. */ ++ bootargs = ""; ++ }; ++ ++ soc { ++ ranges = <0x7e000000 0x3f000000 0x01000000>; ++ ++ arm-pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupts = <3 9>; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv7-timer"; ++ clock-frequency = <19200000>; ++ interrupts = <3 0>, // PHYS_SECURE_PPI ++ <3 1>, // PHYS_NONSECURE_PPI ++ <3 3>, // VIRT_PPI ++ <3 2>; // HYP_PPI ++ always-on; ++ }; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ v7_cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0xf00>; ++ clock-frequency = <800000000>; ++ }; ++ ++ v7_cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0xf01>; ++ clock-frequency = <800000000>; ++ }; ++ ++ v7_cpu2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0xf02>; ++ clock-frequency = <800000000>; ++ }; ++ ++ v7_cpu3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0xf03>; ++ clock-frequency = <800000000>; ++ }; ++ }; ++ ++ __overrides__ { ++ arm_freq = <&v7_cpu0>, "clock-frequency:0", ++ <&v7_cpu1>, "clock-frequency:0", ++ <&v7_cpu2>, "clock-frequency:0", ++ <&v7_cpu3>, "clock-frequency:0"; ++ }; ++}; +--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +@@ -4,27 +4,40 @@ + / { + compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; + model = "Raspberry Pi Model B+"; +- +- leds { +- act { +- gpios = <&gpio 47 0>; +- }; +- +- pwr { +- label = "PWR"; +- gpios = <&gpio 35 0>; +- default-state = "keep"; +- linux,default-trigger = "default-on"; +- }; +- }; + }; + + &gpio { +- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; +- +- /* I2S interface */ +- i2s_alt0: i2s_alt0 { ++ i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + }; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&act_led { ++ gpios = <&gpio 47 0>; ++}; ++ ++&leds { ++ pwr_led: pwr { ++ label = "led1"; ++ linux,default-trigger = "input"; ++ gpios = <&gpio 35 0>; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ ++ pwr_led_gpio = <&pwr_led>,"gpios:4"; ++ pwr_led_activelow = <&pwr_led>,"gpios:8"; ++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ }; ++}; +--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts ++++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts +@@ -5,19 +5,28 @@ + compatible = "raspberrypi,model-b", "brcm,bcm2835"; + model = "Raspberry Pi Model B"; + +- leds { +- act { +- gpios = <&gpio 16 1>; +- }; +- }; + }; + + &gpio { +- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; +- +- /* I2S interface */ +- i2s_alt2: i2s_alt2 { ++ i2s_pins: i2s { + brcm,pins = <28 29 30 31>; +- brcm,function = <6>; /* alt2 */ ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&act_led { ++ gpios = <&gpio 16 1>; ++}; ++ ++/ { ++ __overrides__ { ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; + }; + }; +--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi ++++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi +@@ -1,51 +1,112 @@ + /include/ "bcm2835.dtsi" + + / { ++ /* This is left here in case u-boot needs it */ + memory { + reg = <0 0x10000000>; + }; + +- leds { ++ aliases { ++ soc = &soc; ++ spi0 = &spi0; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2s = &i2s; ++ gpio = &gpio; ++ intc = &intc; ++ leds = &leds; ++ sound = &sound; ++ }; ++ ++ leds: leds { + compatible = "gpio-leds"; + +- act { +- label = "ACT"; +- default-state = "keep"; +- linux,default-trigger = "heartbeat"; ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; + }; + }; ++ ++ /* Onboard audio */ ++ audio: audio { ++ compatible = "brcm,bcm2835-audio"; ++ brcm,pwm-channels = <8>; ++ status = "disabled"; ++ }; ++ ++ /* External sound card */ ++ sound: sound { ++ }; + }; + + &gpio { +- pinctrl-names = "default"; ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; + +- gpioout: gpioout { +- brcm,pins = <6>; +- brcm,function = <1>; /* GPIO out */ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; + }; + +- alt0: alt0 { +- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; +- brcm,function = <4>; /* alt0 */ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; + }; + +- alt3: alt3 { +- brcm,pins = <48 49 50 51 52 53>; +- brcm,function = <7>; /* alt3 */ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; + }; + }; + + &i2c0 { +- status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + }; + + &i2c1 { +- status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + }; + +-&sdhci { ++&mmc { + status = "okay"; + bus-width = <4>; + }; ++ ++&fb { ++ status = "okay"; ++}; ++ ++/ { ++ __overrides__ { ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&audio>,"status"; ++ }; ++}; +--- a/arch/arm/boot/dts/bcm2835.dtsi ++++ b/arch/arm/boot/dts/bcm2835.dtsi +@@ -6,14 +6,15 @@ + interrupt-parent = <&intc>; + + chosen { +- bootargs = "earlyprintk console=ttyAMA0"; ++ bootargs = ""; + }; + +- soc { ++ soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x7e000000 0x20000000 0x02000000>; ++ dma-ranges = <0x40000000 0x00000000 0x20000000>; + + timer@7e003000 { + compatible = "brcm,bcm2835-system-timer"; +@@ -50,16 +51,22 @@ + #interrupt-cells = <2>; + }; + +- watchdog@7e100000 { ++ watchdog: watchdog@7e100000 { + compatible = "brcm,bcm2835-pm-wdt"; + reg = <0x7e100000 0x28>; + }; + +- rng@7e104000 { ++ random: rng@7e104000 { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; + }; + ++ mailbox: mailbox@7e00b800 { ++ compatible = "brcm,bcm2708-vcio"; ++ reg = <0x7e00b880 0x40>; ++ interrupts = <0 1>; ++ }; ++ + gpio: gpio@7e200000 { + compatible = "brcm,bcm2835-gpio"; + reg = <0x7e200000 0xb4>; +@@ -83,7 +90,7 @@ + #interrupt-cells = <2>; + }; + +- uart@7e201000 { ++ uart0: uart@7e201000 { + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x1000>; + interrupts = <2 25>; +@@ -102,7 +109,7 @@ + status = "disabled"; + }; + +- spi: spi@7e204000 { ++ spi0: spi@7e204000 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204000 0x1000>; + interrupts = <2 22>; +@@ -122,11 +129,14 @@ + status = "disabled"; + }; + +- sdhci: sdhci@7e300000 { +- compatible = "brcm,bcm2835-sdhci"; ++ mmc: mmc@7e300000 { ++ compatible = "brcm,bcm2835-mmc"; + reg = <0x7e300000 0x100>; + interrupts = <2 30>; + clocks = <&clk_mmc>; ++ dmas = <&dma 11>, ++ <&dma 11>; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + +@@ -140,7 +150,7 @@ + status = "disabled"; + }; + +- usb@7e980000 { ++ usb: usb@7e980000 { + compatible = "brcm,bcm2835-usb"; + reg = <0x7e980000 0x10000>; + interrupts = <1 9>; +@@ -149,6 +159,21 @@ + arm-pmu { + compatible = "arm,arm1176-pmu"; + }; ++ ++ fb: fb { ++ compatible = "brcm,bcm2708-fb"; ++ status = "disabled"; ++ }; ++ ++ vchiq: vchiq { ++ compatible = "brcm,bcm2835-vchiq"; ++ reg = <0x7e00b840 0xf>; ++ interrupts = <0 2>; ++ }; ++ ++ thermal: thermal { ++ compatible = "brcm,bcm2835-thermal"; ++ }; + }; + + clocks { +@@ -161,7 +186,7 @@ + reg = <0>; + #clock-cells = <0>; + clock-output-names = "mmc"; +- clock-frequency = <100000000>; ++ clock-frequency = <250000000>; + }; + + clk_i2c: clock@1 { +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -0,0 +1,57 @@ ++ifeq ($(CONFIG_OF),y) ++ ++# Overlays for the Raspberry Pi platform ++ ++ifeq ($(CONFIG_BCM2708_DT),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(CONFIG_BCM2709_DT),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(CONFIG_ARCH_BCM2835),y) ++ RPI_DT_OVERLAYS=y ++endif ++ ++dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hifiberry-dacplus-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hifiberry-digi-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hy28a-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hy28b-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += i2c-rtc-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += i2s-mmap-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += lirc-rpi-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += mcp2515-can0-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += mmc-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += mz61581-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pitft28-resistive-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-proto-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += w1-gpio-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += w1-gpio-pullup-overlay.dtb ++ ++targets += dtbs dtbs_install ++targets += $(dtb-y) ++ ++endif ++ ++always := $(dtb-y) ++clean-files := *.dtb ++ ++# Enable fixups to support overlays on BCM2708 platforms ++ifeq ($(RPI_DT_OVERLAYS),y) ++ DTC_FLAGS ?= -@ ++endif +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/README +@@ -0,0 +1,493 @@ ++Introduction ++============ ++ ++This directory contains Device Tree overlays. Device Tree makes it possible ++to support many hardware configurations with a single kernel and without the ++need to explicitly load or blacklist kernel modules. Note that this isn't a ++"pure" Device Tree configuration (c.f. MACH_BCM2835) - some on-board devices ++are still configured by the board support code, but the intention is to ++eventually reach that goal. ++ ++On Raspberry Pi, Device Tree usage is controlled from /boot/config.txt. By ++default, the Raspberry Pi kernel boots with device tree enabled. You can ++completely disable DT usage (for now) by adding: ++ ++ device_tree= ++ ++to your config.txt, which should cause your Pi to revert to the old way of ++doing things after a reboot. ++ ++In /boot you will find a .dtb for each base platform. This describes the ++hardware that is part of the Raspberry Pi board. The loader (start.elf and its ++siblings) selects the .dtb file appropriate for the platform by name, and reads ++it into memory. At this point, all of the optional interfaces (i2c, i2s, spi) ++are disabled, but they can be enabled using Device Tree parameters: ++ ++ dtparam=i2c=on,i2s=on,spi=on ++ ++However, this shouldn't be necessary in many use cases because loading an ++overlay that requires one of those interfaces will cause it to be enabled ++automatically, and it is advisable to only enable interfaces if they are ++needed. ++ ++Configuring additional, optional hardware is done using Device Tree overlays ++(see below). ++ ++raspi-config ++============ ++ ++The Advanced Options section of the raspi-config utility can enable and disable ++Device Tree use, as well as toggling the I2C and SPI interfaces. Note that it ++is possible to both enable an interface and blacklist the driver, if for some ++reason you should want to defer the loading. ++ ++Modules ++======= ++ ++As well as describing the hardware, Device Tree also gives enough information ++to allow suitable driver modules to be located and loaded, with the corollary ++that unneeded modules are not loaded. As a result it should be possible to ++remove lines from /etc/modules, and /etc/modprobe.d/raspi-blacklist.conf can ++have its contents deleted (or commented out). ++ ++Using Overlays ++============== ++ ++Overlays are loaded using the "dtoverlay" directive. As an example, consider the ++popular lirc-rpi module, the Linux Infrared Remote Control driver. In the ++pre-DT world this would be loaded from /etc/modules, with an explicit ++"modprobe lirc-rpi" command, or programmatically by lircd. With DT enabled, ++this becomes a line in config.txt: ++ ++ dtoverlay=lirc-rpi ++ ++This causes the file /boot/overlays/lirc-rpi-overlay.dtb to be loaded. By ++default it will use GPIOs 17 (out) and 18 (in), but this can be modified using ++DT parameters: ++ ++ dtoverlay=lirc-rpi,gpio_out_pin=17,gpio_in_pin=13 ++ ++Parameters always have default values, although in some cases (e.g. "w1-gpio") ++it is necessary to provided multiple overlays in order to get the desired ++behaviour. See the list of overlays below for a description of the parameters and their defaults. ++ ++The Overlay and Parameter Reference ++=================================== ++ ++Name: ++Info: Configures the base Raspberry Pi hardware ++Load: ++Params: ++ audio Set to "on" to disable the onboard ALSA audio ++ interface (default "off") ++ ++ i2c_arm Set to "on" to enable the ARM's i2c interface ++ (default "off") ++ ++ i2c_vc Set to "on" to enable the i2c interface ++ usually reserved for the VideoCore processor ++ (default "off") ++ ++ i2c An alias for i2c_arm ++ ++ i2c_arm_baudrate Set the baudrate of the ARM's i2c interface ++ (default "100000") ++ ++ i2c_vc_baudrate Set the baudrate of the VideoCore i2c interface ++ (default "100000") ++ ++ i2c_baudrate An alias for i2c_arm_baudrate ++ ++ i2s Set to "on" to enable the i2s interface ++ (default "off") ++ ++ spi Set to "on" to enable the spi interfaces ++ (default "off") ++ ++ random Set to "on" to enable the hardware random ++ number generator (default "off") ++ ++ uart0 Set to "off" to disable uart0 (default "on") ++ ++ watchdog Set to "on" to enable the hardware watchdog ++ (default "off") ++ ++ act_led_trigger Choose which activity the LED tracks. ++ Use "heartbeat" for a nice load indicator. ++ (default "mmc") ++ ++ act_led_activelow Set to "on" to invert the sense of the LED ++ (default "off") ++ ++ act_led_gpio Set which GPIO to use for the activity LED ++ (in case you want to connect it to an external ++ device) ++ (default "16" on a non-Plus board, "47" on a ++ Plus or Pi 2) ++ ++ pwr_led_trigger ++ pwr_led_activelow ++ pwr_led_gpio ++ As for act_led_*, but using the PWR LED. ++ Not available on Model A/B boards. ++ ++ N.B. It is recommended to only enable those interfaces that are needed. ++ Leaving all interfaces enabled can lead to unwanted behaviour (i2c_vc ++ interfering with Pi Camera, I2S and SPI hogging GPIO pins, etc.) ++ Note also that i2c, i2c_arm and i2c_vc are aliases for the physical ++ interfaces i2c0 and i2c1. Use of the numeric variants is still possible ++ but deprecated because the ARM/VC assignments differ between board ++ revisions. The same board-specific mapping applies to i2c_baudrate, ++ and the other i2c baudrate parameters. ++ ++ ++Name: ads7846 ++Info: ADS7846 Touch controller ++Load: dtoverlay=ads7846,= ++Params: cs SPI bus Chip Select (default 1) ++ speed SPI bus speed (default 2Mhz, max 3.25MHz) ++ penirq GPIO used for PENIRQ. REQUIRED ++ penirq_pull Set GPIO pull (default 0=none, 2=pullup) ++ swapxy Swap x and y axis ++ xmin Minimum value on the X axis (default 0) ++ ymin Minimum value on the Y axis (default 0) ++ xmax Maximum value on the X axis (default 4095) ++ ymax Maximum value on the Y axis (default 4095) ++ pmin Minimum reported pressure value (default 0) ++ pmax Maximum reported pressure value (default 65535) ++ xohms Touchpanel sensitivity (X-plate resistance) ++ (default 400) ++ ++ penirq is required and usually xohms (60-100) has to be set as well. ++ Apart from that, pmax (255) and swapxy are also common. ++ The rest of the calibration can be done with xinput-calibrator. ++ See: github.com/notro/fbtft/wiki/FBTFT-on-Raspian ++ Device Tree binding document: ++ www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt ++ ++ ++Name: bmp085_i2c-sensor ++Info: Configures the BMP085/BMP180 digital barometric pressure and temperature ++ sensors from Bosch Sensortec ++Load: dtoverlay=bmp085_i2c-sensor ++Params: ++ ++ ++[ The ds1307-rtc overlay has been deleted. See i2c-rtc. ] ++ ++ ++Name: enc28j60 ++Info: Overlay for the Microchip ENC28J60 Ethernet Controller (SPI) ++Load: dtoverlay=enc28j60,= ++Params: int_pin GPIO used for INT (default 25) ++ ++ speed SPI bus speed (default 12000000) ++ ++ ++Name: hifiberry-amp ++Info: Configures the HifiBerry Amp and Amp+ audio cards ++Load: dtoverlay=hifiberry-amp ++Params: ++ ++ ++Name: hifiberry-dac ++Info: Configures the HifiBerry DAC audio card ++Load: dtoverlay=hifiberry-dac ++Params: ++ ++ ++Name: hifiberry-dacplus ++Info: Configures the HifiBerry DAC+ audio card ++Load: dtoverlay=hifiberry-dacplus ++Params: ++ ++ ++Name: hifiberry-digi ++Info: Configures the HifiBerry Digi audio card ++Load: dtoverlay=hifiberry-digi ++Params: ++ ++ ++Name: hy28a ++Info: HY28A - 2.8" TFT LCD Display Module by HAOYU Electronics ++ Default values match Texy's display shield ++Load: dtoverlay=hy28a,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ resetgpio GPIO used to reset controller ++ ++ ledgpio GPIO used to control backlight ++ ++ ++Name: hy28b ++Info: HY28B - 2.8" TFT LCD Display Module by HAOYU Electronics ++ Default values match Texy's display shield ++Load: dtoverlay=hy28b,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ resetgpio GPIO used to reset controller ++ ++ ledgpio GPIO used to control backlight ++ ++ ++Name: i2c-rtc ++Info: Adds support for a number of I2C Real Time Clock devices ++Load: dtoverlay=i2c-rtc, ++Params: ds1307 Select the DS1307 device ++ ++ ds3231 Select the DS3231 device ++ ++ pcf2127 Select the PCF2127 device ++ ++ pcf8523 Select the PCF8523 device ++ ++ pcf8563 Select the PCF8563 device ++ ++ ++Name: iqaudio-dac ++Info: Configures the IQaudio DAC audio card ++Load: dtoverlay=iqaudio-dac ++Params: ++ ++ ++Name: iqaudio-dacplus ++Info: Configures the IQaudio DAC+ audio card ++Load: dtoverlay=iqaudio-dacplus ++Params: ++ ++ ++Name: lirc-rpi ++Info: Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi) ++ Consult the module documentation for more details. ++Load: dtoverlay=lirc-rpi,=,... ++Params: gpio_out_pin GPIO for output (default "17") ++ ++ gpio_in_pin GPIO for input (default "18") ++ ++ gpio_in_pull Pull up/down/off on the input pin ++ (default "down") ++ ++ sense Override the IR receive auto-detection logic: ++ "1" = force active high ++ "0" = force active low ++ "-1" = use auto-detection ++ (default "-1") ++ ++ softcarrier Turn the software carrier "on" or "off" ++ (default "on") ++ ++ invert "on" = invert the output pin (default "off") ++ ++ debug "on" = enable additional debug messages ++ (default "off") ++ ++ ++Name: mcp2515-can0 ++Info: Configures the MCP2515 CAN controller ++Load: dtoverlay=mcp2515-can0,= ++Params: oscillator Clock frequency for the CAN controller (Hz) ++ ++ spimaxfrequency Maximum SPI frequence (Hz) ++ ++ interrupt GPIO for interrupt signal ++ ++ ++Name: mmc ++Info: Selects the bcm2835-mmc SD/MMC driver, optionally with overclock ++Load: dtoverlay=mmc,= ++Params: overclock_50 Clock (in MHz) to use when the MMC framework ++ requests 50MHz ++ force_pio Disable DMA support ++ ++ ++Name: mz61581 ++Info: MZ61581 display by Tontec ++Load: dtoverlay=mz61581,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ ++[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ] ++ ++ ++[ The pcf8523-rtc overlay has been deleted. See i2c-rtc. ] ++ ++ ++[ The pcf8563-rtc overlay has been deleted. See i2c-rtc. ] ++ ++ ++Name: piscreen ++Info: PiScreen display by OzzMaker.com ++Load: dtoverlay=piscreen,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ ++Name: pitft28-resistive ++Info: Adafruit PiTFT 2.8" resistive touch screen ++Load: dtoverlay=pitft28-resistive,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ ++Name: pps-gpio ++Info: Configures the pps-gpio (pulse-per-second time signal via GPIO). ++Load: dtoverlay=pps-gpio,= ++Params: gpiopin Input GPIO (default "18") ++ ++ ++Name: rpi-dac ++Info: Configures the RPi DAC audio card ++Load: dtoverlay=rpi-dac ++Params: ++ ++ ++Name: rpi-display ++Info: RPi-Display - 2.8" Touch Display by Watterott ++Load: dtoverlay=rpi-display,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ ++Name: rpi-proto ++Info: Configures the RPi Proto audio card ++Load: dtoverlay=rpi-proto ++Params: ++ ++ ++Name: sdhost ++Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock ++Load: dtoverlay=sdhost,= ++Params: overclock_50 Clock (in MHz) to use when the MMC framework ++ requests 50MHz ++ force_pio Disable DMA support ++ ++ ++Name: spi-bcm2708 ++Info: Selects the bcm2708-spi SPI driver ++Load: dtoverlay=spi-bcm2708 ++Params: ++ ++ ++Name: spi-bcm2835 ++Info: Selects the bcm2835-spi SPI driver ++Load: dtoverlay=spi-bcm2835 ++Params: ++ ++ ++Name: tinylcd35 ++Info: 3.5" Color TFT Display by www.tinylcd.com ++ Options: Touch, RTC, keypad ++Load: dtoverlay=tinylcd35,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ touch Enable touch panel ++ ++ touchgpio Touch controller IRQ GPIO ++ ++ xohms Touchpanel: Resistance of X-plate in ohms ++ ++ rtc-pcf PCF8563 Real Time Clock ++ ++ rtc-ds DS1307 Real Time Clock ++ ++ keypad Enable keypad ++ ++ Examples: ++ Display with touchpanel, PCF8563 RTC and keypad: ++ dtoverlay=tinylcd35,touch,rtc-pcf,keypad ++ Old touch display: ++ dtoverlay=tinylcd35,touch,touchgpio=3 ++ ++ ++Name: w1-gpio ++Info: Configures the w1-gpio Onewire interface module. ++ Use this overlay if you *don't* need a GPIO to drive an external pullup. ++Load: dtoverlay=w1-gpio,= ++Params: gpiopin GPIO for I/O (default "4") ++ ++ pullup Non-zero, "on", or "y" to enable the parasitic ++ power (2-wire, power-on-data) feature ++ ++ ++Name: w1-gpio-pullup ++Info: Configures the w1-gpio Onewire interface module. ++ Use this overlay if you *do* need a GPIO to drive an external pullup. ++Load: dtoverlay=w1-gpio-pullup,=,... ++Params: gpiopin GPIO for I/O (default "4") ++ ++ pullup Non-zero, "on", or "y" to enable the parasitic ++ power (2-wire, power-on-data) feature ++ ++ extpullup GPIO for external pullup (default "5") ++ ++ ++Troubleshooting ++=============== ++ ++If you are experiencing problems that you think are DT-related, enable DT ++diagnostic output by adding this to /boot/config.txt: ++ ++ dtdebug=on ++ ++and rebooting. Then run: ++ ++ sudo vcdbg log msg ++ ++and look for relevant messages. ++ ++Further reading ++=============== ++ ++This is only meant to be a quick introduction to the subject of Device Tree on ++Raspberry Pi. There is a more complete explanation here: ++ ++http://www.raspberrypi.org/documentation/configuration/device-tree.md +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ads7846-overlay.dts +@@ -0,0 +1,83 @@ ++/* ++ * Generic Device Tree overlay for the ADS7846 touch controller ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ ads7846_pins: ads7846_pins { ++ brcm,pins = <255>; /* illegal default value */ ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ads7846: ads7846@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ads7846_pins>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <255 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 255 0>; ++ ++ /* driver defaults */ ++ ti,x-min = /bits/ 16 <0>; ++ ti,y-min = /bits/ 16 <0>; ++ ti,x-max = /bits/ 16 <0x0FFF>; ++ ti,y-max = /bits/ 16 <0x0FFF>; ++ ti,pressure-min = /bits/ 16 <0>; ++ ti,pressure-max = /bits/ 16 <0xFFFF>; ++ ti,x-plate-ohms = /bits/ 16 <400>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ cs = <&ads7846>,"reg:0"; ++ speed = <&ads7846>,"spi-max-frequency:0"; ++ penirq = <&ads7846_pins>,"brcm,pins:0", /* REQUIRED */ ++ <&ads7846>,"interrupts:0", ++ <&ads7846>,"pendown-gpio:4"; ++ penirq_pull = <&ads7846_pins>,"brcm,pull:0"; ++ swapxy = <&ads7846>,"ti,swap-xy?"; ++ xmin = <&ads7846>,"ti,x-min;0"; ++ ymin = <&ads7846>,"ti,y-min;0"; ++ xmax = <&ads7846>,"ti,x-max;0"; ++ ymax = <&ads7846>,"ti,y-max;0"; ++ pmin = <&ads7846>,"ti,pressure-min;0"; ++ pmax = <&ads7846>,"ti,pressure-max;0"; ++ xohms = <&ads7846>,"ti,x-plate-ohms;0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts +@@ -0,0 +1,23 @@ ++// Definitions for BMP085/BMP180 digital barometric pressure and temperature sensors from Bosch Sensortec ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ bmp085@77 { ++ compatible = "bosch,bmp085"; ++ reg = <0x77>; ++ default-oversampling = <3>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/dht11-overlay.dts +@@ -0,0 +1,39 @@ ++/* ++ * Overlay for the DHT11/21/22 humidity/temperature sensor modules. ++ */ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ ++ dht11: dht11@0 { ++ compatible = "dht11"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dht11_pins>; ++ gpios = <&gpio 4 0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ dht11_pins: dht11_pins { ++ brcm,pins = <4>; ++ brcm,function = <0>; // in ++ brcm,pull = <0>; // off ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&dht11_pins>,"brcm,pins:0", ++ <&dht11>,"gpios:4"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/enc28j60-overlay.dts +@@ -0,0 +1,50 @@ ++// Overlay for the Microchip ENC28J60 Ethernet Controller ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ eth1: enc28j60@0{ ++ compatible = "microchip,enc28j60"; ++ reg = <0>; /* CE0 */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <ð1_pins>; ++ interrupt-parent = <&gpio>; ++ interrupts = <25 0x2>; /* falling edge */ ++ spi-max-frequency = <12000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ eth1_pins: eth1_pins { ++ brcm,pins = <25>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ int_pin = <ð1>, "interrupts:0", ++ <ð1_pins>, "brcm,pins:0"; ++ speed = <ð1>, "spi-max-frequency:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for HiFiBerry Amp/Amp+ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-amp"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ tas5713@1b { ++ #sound-dai-cells = <0>; ++ compatible = "ti,tas5713"; ++ reg = <0x1b>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts +@@ -0,0 +1,34 @@ ++// Definitions for HiFiBerry DAC ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-dac"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target-path = "/"; ++ __overlay__ { ++ pcm5102a-codec { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5102a"; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for HiFiBerry DAC+ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-dacplus"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4d { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4d>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for HiFiBerry Digi ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-digi"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ wm8804@3b { ++ #sound-dai-cells = <0>; ++ compatible = "wlf,wm8804"; ++ reg = <0x3b>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hy28a-overlay.dts +@@ -0,0 +1,87 @@ ++/* ++ * Device Tree overlay for HY28A display ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ hy28a_pins: hy28a_pins { ++ brcm,pins = <17 25 18>; ++ brcm,function = <0 1 1>; /* in out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hy28a: hy28a@0{ ++ compatible = "ilitek,ili9320"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hy28a_pins>; ++ ++ spi-max-frequency = <32000000>; ++ spi-cpol; ++ spi-cpha; ++ rotate = <270>; ++ bgr; ++ fps = <50>; ++ buswidth = <8>; ++ startbyte = <0x70>; ++ reset-gpios = <&gpio 25 0>; ++ led-gpios = <&gpio 18 1>; ++ debug = <0>; ++ }; ++ ++ hy28a_ts: hy28a-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <17 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 17 0>; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&hy28a>,"spi-max-frequency:0"; ++ rotate = <&hy28a>,"rotate:0"; ++ fps = <&hy28a>,"fps:0"; ++ debug = <&hy28a>,"debug:0"; ++ xohms = <&hy28a_ts>,"ti,x-plate-ohms;0"; ++ resetgpio = <&hy28a>,"reset-gpios:4", ++ <&hy28a_pins>, "brcm,pins:1"; ++ ledgpio = <&hy28a>,"led-gpios:4", ++ <&hy28a_pins>, "brcm,pins:2"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hy28b-overlay.dts +@@ -0,0 +1,142 @@ ++/* ++ * Device Tree overlay for HY28b display shield by Texy ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ hy28b_pins: hy28b_pins { ++ brcm,pins = <17 25 18>; ++ brcm,function = <0 1 1>; /* in out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hy28b: hy28b@0{ ++ compatible = "ilitek,ili9325"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hy28b_pins>; ++ ++ spi-max-frequency = <48000000>; ++ spi-cpol; ++ spi-cpha; ++ rotate = <270>; ++ bgr; ++ fps = <50>; ++ buswidth = <8>; ++ startbyte = <0x70>; ++ reset-gpios = <&gpio 25 0>; ++ led-gpios = <&gpio 18 1>; ++ ++ gamma = "04 1F 4 7 7 0 7 7 6 0\n0F 00 1 7 4 0 0 0 6 7"; ++ ++ init = <0x10000e7 0x0010 ++ 0x1000000 0x0001 ++ 0x1000001 0x0100 ++ 0x1000002 0x0700 ++ 0x1000003 0x1030 ++ 0x1000004 0x0000 ++ 0x1000008 0x0207 ++ 0x1000009 0x0000 ++ 0x100000a 0x0000 ++ 0x100000c 0x0001 ++ 0x100000d 0x0000 ++ 0x100000f 0x0000 ++ 0x1000010 0x0000 ++ 0x1000011 0x0007 ++ 0x1000012 0x0000 ++ 0x1000013 0x0000 ++ 0x2000032 ++ 0x1000010 0x1590 ++ 0x1000011 0x0227 ++ 0x2000032 ++ 0x1000012 0x009c ++ 0x2000032 ++ 0x1000013 0x1900 ++ 0x1000029 0x0023 ++ 0x100002b 0x000e ++ 0x2000032 ++ 0x1000020 0x0000 ++ 0x1000021 0x0000 ++ 0x2000032 ++ 0x1000050 0x0000 ++ 0x1000051 0x00ef ++ 0x1000052 0x0000 ++ 0x1000053 0x013f ++ 0x1000060 0xa700 ++ 0x1000061 0x0001 ++ 0x100006a 0x0000 ++ 0x1000080 0x0000 ++ 0x1000081 0x0000 ++ 0x1000082 0x0000 ++ 0x1000083 0x0000 ++ 0x1000084 0x0000 ++ 0x1000085 0x0000 ++ 0x1000090 0x0010 ++ 0x1000092 0x0000 ++ 0x1000093 0x0003 ++ 0x1000095 0x0110 ++ 0x1000097 0x0000 ++ 0x1000098 0x0000 ++ 0x1000007 0x0133 ++ 0x1000020 0x0000 ++ 0x1000021 0x0000 ++ 0x2000064>; ++ debug = <0>; ++ }; ++ ++ hy28b_ts: hy28b-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <17 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 17 0>; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&hy28b>,"spi-max-frequency:0"; ++ rotate = <&hy28b>,"rotate:0"; ++ fps = <&hy28b>,"fps:0"; ++ debug = <&hy28b>,"debug:0"; ++ xohms = <&hy28b_ts>,"ti,x-plate-ohms;0"; ++ resetgpio = <&hy28b>,"reset-gpios:4", ++ <&hy28b_pins>, "brcm,pins:1"; ++ ledgpio = <&hy28b>,"led-gpios:4", ++ <&hy28b_pins>, "brcm,pins:2"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts +@@ -0,0 +1,49 @@ ++// Definitions for several I2C based Real Time Clocks ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ds1307: ds1307@68 { ++ compatible = "maxim,ds1307"; ++ reg = <0x68>; ++ status = "disable"; ++ }; ++ ds3231: ds3231@68 { ++ compatible = "maxim,ds3231"; ++ reg = <0x68>; ++ status = "disable"; ++ }; ++ pcf2127: pcf2127@51 { ++ compatible = "nxp,pcf2127"; ++ reg = <0x51>; ++ status = "disable"; ++ }; ++ pcf8523: pcf8523@68 { ++ compatible = "nxp,pcf8523"; ++ reg = <0x68>; ++ status = "disable"; ++ }; ++ pcf8563: pcf8563@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ status = "disable"; ++ }; ++ }; ++ }; ++ __overrides__ { ++ ds1307 = <&ds1307>,"status"; ++ ds3231 = <&ds3231>,"status"; ++ pcf2127 = <&pcf2127>,"status"; ++ pcf8523 = <&pcf8523>,"status"; ++ pcf8563 = <&pcf8563>,"status"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&i2s>; ++ __overlay__ { ++ brcm,enable-mmap; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for IQaudIO DAC ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "iqaudio,iqaudio-dac"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4c { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4c>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for IQaudIO DAC+ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "iqaudio,iqaudio-dac"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4c { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4c>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts +@@ -0,0 +1,57 @@ ++// Definitions for lirc-rpi module ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ lirc_rpi: lirc_rpi { ++ compatible = "rpi,lirc-rpi"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lirc_pins>; ++ status = "okay"; ++ ++ // Override autodetection of IR receiver circuit ++ // (0 = active high, 1 = active low, -1 = no override ) ++ rpi,sense = <0xffffffff>; ++ ++ // Software carrier ++ // (0 = off, 1 = on) ++ rpi,softcarrier = <1>; ++ ++ // Invert output ++ // (0 = off, 1 = on) ++ rpi,invert = <0>; ++ ++ // Enable debugging messages ++ // (0 = off, 1 = on) ++ rpi,debug = <0>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ lirc_pins: lirc_pins { ++ brcm,pins = <17 18>; ++ brcm,function = <1 0>; // out in ++ brcm,pull = <0 1>; // off down ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpio_out_pin = <&lirc_pins>,"brcm,pins:0"; ++ gpio_in_pin = <&lirc_pins>,"brcm,pins:4"; ++ gpio_in_pull = <&lirc_pins>,"brcm,pull:4"; ++ ++ sense = <&lirc_rpi>,"rpi,sense:0"; ++ softcarrier = <&lirc_rpi>,"rpi,softcarrier:0"; ++ invert = <&lirc_rpi>,"rpi,invert:0"; ++ debug = <&lirc_rpi>,"rpi,debug:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts +@@ -0,0 +1,69 @@ ++/* ++ * Device tree overlay for mcp251x/can0 on spi0.0 ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ /* disable spi-dev for spi0.0 */ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ spidev@0{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ /* the interrupt pin of the can-controller */ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ can0_pins: can0_pins { ++ brcm,pins = <25>; ++ brcm,function = <0>; /* input */ ++ }; ++ }; ++ }; ++ ++ /* the clock/oscillator of the can-controller */ ++ fragment@2 { ++ target-path = "/clocks"; ++ __overlay__ { ++ /* external oscillator of mcp2515 on SPI0.0 */ ++ can0_osc: can0_osc { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ }; ++ }; ++ }; ++ ++ /* the spi config of the can-controller itself binding everything together */ ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ can0: mcp2515@0 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pins>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&gpio>; ++ interrupts = <25 0x2>; ++ clocks = <&can0_osc>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ oscillator = <&can0_osc>,"clock-frequency:0"; ++ spimaxfrequency = <&can0>,"spi-max-frequency:0"; ++ interrupt = <&can0_pins>,"brcm,pins:0",<&can0>,"interrupts:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts +@@ -0,0 +1,19 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&mmc>; ++ ++ __overlay__ { ++ brcm,overclock-50 = <0>; ++ }; ++ }; ++ ++ __overrides__ { ++ overclock_50 = <&mmc>,"brcm,overclock-50:0"; ++ force_pio = <&mmc>,"brcm,force-pio?"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/mz61581-overlay.dts +@@ -0,0 +1,109 @@ ++/* ++ * Device Tree overlay for MZ61581-PI-EXT 2014.12.28 by Tontec ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ mz61581_pins: mz61581_pins { ++ brcm,pins = <4 15 18 25>; ++ brcm,function = <0 1 1 1>; /* in out out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mz61581: mz61581@0{ ++ compatible = "samsung,s6d02a1"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mz61581_pins>; ++ ++ spi-max-frequency = <128000000>; ++ spi-cpol; ++ spi-cpha; ++ ++ width = <320>; ++ height = <480>; ++ rotate = <270>; ++ bgr; ++ fps = <30>; ++ buswidth = <8>; ++ ++ reset-gpios = <&gpio 15 0>; ++ dc-gpios = <&gpio 25 0>; ++ led-gpios = <&gpio 18 0>; ++ ++ init = <0x10000b0 00 ++ 0x1000011 ++ 0x20000ff ++ 0x10000b3 0x02 0x00 0x00 0x00 ++ 0x10000c0 0x13 0x3b 0x00 0x02 0x00 0x01 0x00 0x43 ++ 0x10000c1 0x08 0x16 0x08 0x08 ++ 0x10000c4 0x11 0x07 0x03 0x03 ++ 0x10000c6 0x00 ++ 0x10000c8 0x03 0x03 0x13 0x5c 0x03 0x07 0x14 0x08 0x00 0x21 0x08 0x14 0x07 0x53 0x0c 0x13 0x03 0x03 0x21 0x00 ++ 0x1000035 0x00 ++ 0x1000036 0xa0 ++ 0x100003a 0x55 ++ 0x1000044 0x00 0x01 ++ 0x10000d0 0x07 0x07 0x1d 0x03 ++ 0x10000d1 0x03 0x30 0x10 ++ 0x10000d2 0x03 0x14 0x04 ++ 0x1000029 ++ 0x100002c>; ++ ++ /* This is a workaround to make sure the init sequence slows down and doesn't fail */ ++ debug = <3>; ++ }; ++ ++ mz61581_ts: mz61581_ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <4 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 4 0>; ++ ++ ti,x-plate-ohms = /bits/ 16 <60>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&mz61581>, "spi-max-frequency:0"; ++ rotate = <&mz61581>, "rotate:0"; ++ fps = <&mz61581>, "fps:0"; ++ debug = <&mz61581>, "debug:0"; ++ xohms = <&mz61581_ts>,"ti,x-plate-ohms;0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/piscreen-overlay.dts +@@ -0,0 +1,96 @@ ++/* ++ * Device Tree overlay for PiScreen 3.5" display shield by Ozzmaker ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ piscreen_pins: piscreen_pins { ++ brcm,pins = <17 25 24 22>; ++ brcm,function = <0 1 1 1>; /* in out out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ piscreen: piscreen@0{ ++ compatible = "ilitek,ili9486"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&piscreen_pins>; ++ ++ spi-max-frequency = <24000000>; ++ rotate = <270>; ++ bgr; ++ fps = <30>; ++ buswidth = <8>; ++ regwidth = <16>; ++ reset-gpios = <&gpio 25 0>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 22 1>; ++ debug = <0>; ++ ++ init = <0x10000b0 0x00 ++ 0x1000011 ++ 0x20000ff ++ 0x100003a 0x55 ++ 0x1000036 0x28 ++ 0x10000c2 0x44 ++ 0x10000c5 0x00 0x00 0x00 0x00 ++ 0x10000e0 0x0f 0x1f 0x1c 0x0c 0x0f 0x08 0x48 0x98 0x37 0x0a 0x13 0x04 0x11 0x0d 0x00 ++ 0x10000e1 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00 ++ 0x10000e2 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00 ++ 0x1000011 ++ 0x1000029>; ++ }; ++ ++ piscreen_ts: piscreen-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <17 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 17 0>; ++ ti,swap-xy; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&piscreen>,"spi-max-frequency:0"; ++ rotate = <&piscreen>,"rotate:0"; ++ fps = <&piscreen>,"fps:0"; ++ debug = <&piscreen>,"debug:0"; ++ xohms = <&piscreen_ts>,"ti,x-plate-ohms;0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts +@@ -0,0 +1,115 @@ ++/* ++ * Device Tree overlay for Adafruit PiTFT 2.8" resistive touch screen ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ pitft_pins: pitft_pins { ++ brcm,pins = <24 25>; ++ brcm,function = <0 1>; /* in out */ ++ brcm,pull = <2 0>; /* pullup none */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pitft: pitft@0{ ++ compatible = "ilitek,ili9340"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pitft_pins>; ++ ++ spi-max-frequency = <32000000>; ++ rotate = <90>; ++ fps = <25>; ++ bgr; ++ buswidth = <8>; ++ dc-gpios = <&gpio 25 0>; ++ debug = <0>; ++ }; ++ ++ pitft_ts@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stmpe610"; ++ reg = <1>; ++ ++ spi-max-frequency = <500000>; ++ irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */ ++ interrupts = <24 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ interrupt-controller; ++ ++ stmpe_touchscreen { ++ compatible = "st,stmpe-ts"; ++ st,sample-time = <4>; ++ st,mod-12b = <1>; ++ st,ref-sel = <0>; ++ st,adc-freq = <2>; ++ st,ave-ctrl = <3>; ++ st,touch-det-delay = <4>; ++ st,settling = <2>; ++ st,fraction-z = <7>; ++ st,i-drive = <0>; ++ }; ++ ++ stmpe_gpio: stmpe_gpio { ++ #gpio-cells = <2>; ++ compatible = "st,stmpe-gpio"; ++ /* ++ * only GPIO2 is wired/available ++ * and it is wired to the backlight ++ */ ++ st,norequest-mask = <0x7b>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target-path = "/soc"; ++ __overlay__ { ++ backlight { ++ compatible = "gpio-backlight"; ++ gpios = <&stmpe_gpio 2 0>; ++ default-on; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ speed = <&pitft>,"spi-max-frequency:0"; ++ rotate = <&pitft>,"rotate:0"; ++ fps = <&pitft>,"fps:0"; ++ debug = <&pitft>,"debug:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts +@@ -0,0 +1,34 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ pps: pps { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&gpio 18 0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ brcm,pins = <18>; ++ brcm,function = <0>; // in ++ brcm,pull = <0>; // off ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&pps>,"gpios:4", ++ <&pps_pins>,"brcm,pins:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts +@@ -0,0 +1,34 @@ ++// Definitions for RPi DAC ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "rpi,rpi-dac"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target-path = "/"; ++ __overlay__ { ++ pcm1794a-codec { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm1794a"; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-display-overlay.dts +@@ -0,0 +1,82 @@ ++/* ++ * Device Tree overlay for rpi-display by Watterott ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ rpi_display_pins: rpi_display_pins { ++ brcm,pins = <18 23 24 25>; ++ brcm,function = <1 1 1 0>; /* out out out in */ ++ brcm,pull = <0 0 0 2>; /* - - - up */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rpidisplay: rpi-display@0{ ++ compatible = "ilitek,ili9341"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rpi_display_pins>; ++ ++ spi-max-frequency = <32000000>; ++ rotate = <270>; ++ bgr; ++ fps = <30>; ++ buswidth = <8>; ++ reset-gpios = <&gpio 23 0>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 18 1>; ++ debug = <0>; ++ }; ++ ++ rpidisplay_ts: rpi-display-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <25 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 25 0>; ++ ti,x-plate-ohms = /bits/ 16 <60>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&rpidisplay>,"spi-max-frequency:0"; ++ rotate = <&rpidisplay>,"rotate:0"; ++ fps = <&rpidisplay>,"fps:0"; ++ debug = <&rpidisplay>,"debug:0"; ++ xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for Rpi-Proto ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "rpi,rpi-proto"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ wm8731@1a { ++ #sound-dai-cells = <0>; ++ compatible = "wlf,wm8731"; ++ reg = <0x1a>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts +@@ -0,0 +1,78 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&soc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ sdhost: sdhost@7e202000 { ++ compatible = "brcm,bcm2835-sdhost"; ++ reg = <0x7e202000 0x100>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; ++ interrupts = <2 24>; ++ clocks = <&clk_sdhost>; ++ dmas = <&dma 13>, ++ <&dma 13>; ++ dma-names = "tx", "rx"; ++ brcm,delay-after-stop = <0>; ++ brcm,overclock-50 = <0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&clocks>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ clk_sdhost: sdhost { ++ compatible = "fixed-clock"; ++ reg = <0>; ++ #clock-cells = <0>; ++ clock-output-names = "sdhost"; ++ clock-frequency = <250000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&mmc>; ++ __overlay__ { ++ /* Find a way to disable the other driver */ ++ compatible = ""; ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@4 { ++ target-path = "/__overrides__"; ++ __overlay__ { ++ sdhost_freq = <&clk_sdhost>,"clock-frequency:0"; ++ }; ++ }; ++ ++ __overrides__ { ++ delay_after_stop = <&sdhost>,"brcm,delay-after-stop:0"; ++ overclock_50 = <&sdhost>,"brcm,overclock-50:0"; ++ force_pio = <&sdhost>,"brcm,force-pio?"; ++ sdhost_freq = <&clk_sdhost>,"clock-frequency:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts +@@ -0,0 +1,18 @@ ++/* ++ * Device tree overlay for spi-bcm2835 ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ /* setting up compatiblity to allow loading the spi-bcm2835 driver */ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ compatible = "brcm,bcm2708-spi"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts +@@ -0,0 +1,18 @@ ++/* ++ * Device tree overlay for spi-bcm2835 ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ /* setting up compatiblity to allow loading the spi-bcm2835 driver */ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ compatible = "brcm,bcm2835-spi"; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts +@@ -0,0 +1,216 @@ ++/* ++ * tinylcd35-overlay.dts ++ * ++ * ------------------------------------------------- ++ * www.tinlylcd.com ++ * ------------------------------------------------- ++ * Device---Driver-----BUS GPIO's ++ * display tinylcd35 spi0.0 25 24 18 ++ * touch ads7846 spi0.1 5 ++ * rtc ds1307 i2c1-0068 ++ * rtc pcf8563 i2c1-0051 ++ * keypad gpio-keys --------- 17 22 27 23 28 ++ * ++ * ++ * TinyLCD.com 3.5 inch TFT ++ * ++ * Version 001 ++ * 5/3/2015 -- Noralf Trønnes Initial Device tree framework ++ * 10/3/2015 -- tinylcd@gmail.com added ds1307 support. ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ tinylcd35_pins: tinylcd35_pins { ++ brcm,pins = <25 24 18>; ++ brcm,function = <1>; /* out */ ++ }; ++ tinylcd35_ts_pins: tinylcd35_ts_pins { ++ brcm,pins = <5>; ++ brcm,function = <0>; /* in */ ++ }; ++ keypad_pins: keypad_pins { ++ brcm,pins = <4 17 22 23 27>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <1>; /* down */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ tinylcd35: tinylcd35@0{ ++ compatible = "neosec,tinylcd"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&tinylcd35_pins>, ++ <&tinylcd35_ts_pins>; ++ ++ spi-max-frequency = <48000000>; ++ rotate = <270>; ++ fps = <20>; ++ bgr; ++ buswidth = <8>; ++ reset-gpios = <&gpio 25 0>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 18 1>; ++ debug = <0>; ++ ++ init = <0x10000B0 0x80 ++ 0x10000C0 0x0A 0x0A ++ 0x10000C1 0x01 0x01 ++ 0x10000C2 0x33 ++ 0x10000C5 0x00 0x42 0x80 ++ 0x10000B1 0xD0 0x11 ++ 0x10000B4 0x02 ++ 0x10000B6 0x00 0x22 0x3B ++ 0x10000B7 0x07 ++ 0x1000036 0x58 ++ 0x10000F0 0x36 0xA5 0xD3 ++ 0x10000E5 0x80 ++ 0x10000E5 0x01 ++ 0x10000B3 0x00 ++ 0x10000E5 0x00 ++ 0x10000F0 0x36 0xA5 0x53 ++ 0x10000E0 0x00 0x35 0x33 0x00 0x00 0x00 0x00 0x35 0x33 0x00 0x00 0x00 ++ 0x100003A 0x55 ++ 0x1000011 ++ 0x2000001 ++ 0x1000029>; ++ }; ++ ++ tinylcd35_ts: tinylcd35_ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ status = "disabled"; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <5 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 5 0>; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ ++ /* RTC */ ++ ++ fragment@3 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pcf8563: pcf8563@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ds1307: ds1307@68 { ++ compatible = "maxim,ds1307"; ++ reg = <0x68>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ /* ++ * Values for input event code is found under the ++ * 'Keys and buttons' heading in include/uapi/linux/input.h ++ */ ++ fragment@5 { ++ target-path = "/soc"; ++ __overlay__ { ++ keypad: keypad { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&keypad_pins>; ++ status = "disabled"; ++ autorepeat; ++ ++ button@17 { ++ label = "GPIO KEY_UP"; ++ linux,code = <103>; ++ gpios = <&gpio 17 0>; ++ }; ++ button@22 { ++ label = "GPIO KEY_DOWN"; ++ linux,code = <108>; ++ gpios = <&gpio 22 0>; ++ }; ++ button@27 { ++ label = "GPIO KEY_LEFT"; ++ linux,code = <105>; ++ gpios = <&gpio 27 0>; ++ }; ++ button@23 { ++ label = "GPIO KEY_RIGHT"; ++ linux,code = <106>; ++ gpios = <&gpio 23 0>; ++ }; ++ button@4 { ++ label = "GPIO KEY_ENTER"; ++ linux,code = <28>; ++ gpios = <&gpio 4 0>; ++ }; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ speed = <&tinylcd35>,"spi-max-frequency:0"; ++ rotate = <&tinylcd35>,"rotate:0"; ++ fps = <&tinylcd35>,"fps:0"; ++ debug = <&tinylcd35>,"debug:0"; ++ touch = <&tinylcd35_ts>,"status"; ++ touchgpio = <&tinylcd35_ts_pins>,"brcm,pins:0", ++ <&tinylcd35_ts>,"interrupts:0", ++ <&tinylcd35_ts>,"pendown-gpio:4"; ++ xohms = <&tinylcd35_ts>,"ti,x-plate-ohms;0"; ++ rtc-pcf = <&i2c1>,"status", ++ <&pcf8563>,"status"; ++ rtc-ds = <&i2c1>,"status", ++ <&ds1307>,"status"; ++ keypad = <&keypad>,"status"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for w1-gpio module (without external pullup) ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ ++ w1: onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&gpio 4 0>; ++ rpi,parasitic-power = <0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ brcm,pins = <4>; ++ brcm,function = <0>; // in (initially) ++ brcm,pull = <0>; // off ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&w1>,"gpios:4", ++ <&w1_pins>,"brcm,pins:0"; ++ pullup = <&w1>,"rpi,parasitic-power:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts +@@ -0,0 +1,41 @@ ++// Definitions for w1-gpio module (with external pullup) ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ ++ w1: onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&gpio 4 0>, <&gpio 5 1>; ++ rpi,parasitic-power = <0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ brcm,pins = <4 5>; ++ brcm,function = <0 1>; // in out ++ brcm,pull = <0 0>; // off off ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&w1>,"gpios:4", ++ <&w1_pins>,"brcm,pins:0"; ++ extpullup = <&w1>,"gpios:16", ++ <&w1_pins>,"brcm,pins:4"; ++ pullup = <&w1>,"rpi,parasitic-power:0"; ++ }; ++}; diff --git a/target/linux/brcm2708/patches-4.1/0026-fbdev-add-FBIOCOPYAREA-ioctl.patch b/target/linux/brcm2708/patches-4.1/0026-fbdev-add-FBIOCOPYAREA-ioctl.patch new file mode 100644 index 0000000..5148748 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0026-fbdev-add-FBIOCOPYAREA-ioctl.patch @@ -0,0 +1,91 @@ +From 968d9983a0ff154cf772006f39d72100b8c3dd79 Mon Sep 17 00:00:00 2001 +From: Siarhei Siamashka +Date: Mon, 17 Jun 2013 13:32:11 +0300 +Subject: [PATCH 026/203] fbdev: add FBIOCOPYAREA ioctl + +Based on the patch authored by Ali Gholami Rudi at + https://lkml.org/lkml/2009/7/13/153 + +Provide an ioctl for userspace applications, but only if this operation +is hardware accelerated (otherwide it does not make any sense). + +Signed-off-by: Siarhei Siamashka +--- + drivers/video/fbdev/core/fbmem.c | 30 ++++++++++++++++++++++++++++++ + include/uapi/linux/fb.h | 5 +++++ + 2 files changed, 35 insertions(+) + +--- a/drivers/video/fbdev/core/fbmem.c ++++ b/drivers/video/fbdev/core/fbmem.c +@@ -1084,6 +1084,25 @@ fb_blank(struct fb_info *info, int blank + } + EXPORT_SYMBOL(fb_blank); + ++static int fb_copyarea_user(struct fb_info *info, ++ struct fb_copyarea *copy) ++{ ++ int ret = 0; ++ if (!lock_fb_info(info)) ++ return -ENODEV; ++ if (copy->dx + copy->width > info->var.xres || ++ copy->sx + copy->width > info->var.xres || ++ copy->dy + copy->height > info->var.yres || ++ copy->sy + copy->height > info->var.yres) { ++ ret = -EINVAL; ++ goto out; ++ } ++ info->fbops->fb_copyarea(info, copy); ++out: ++ unlock_fb_info(info); ++ return ret; ++} ++ + static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg) + { +@@ -1094,6 +1113,7 @@ static long do_fb_ioctl(struct fb_info * + struct fb_cmap cmap_from; + struct fb_cmap_user cmap; + struct fb_event event; ++ struct fb_copyarea copy; + void __user *argp = (void __user *)arg; + long ret = 0; + +@@ -1211,6 +1231,15 @@ static long do_fb_ioctl(struct fb_info * + unlock_fb_info(info); + console_unlock(); + break; ++ case FBIOCOPYAREA: ++ if (info->flags & FBINFO_HWACCEL_COPYAREA) { ++ /* only provide this ioctl if it is accelerated */ ++ if (copy_from_user(©, argp, sizeof(copy))) ++ return -EFAULT; ++ ret = fb_copyarea_user(info, ©); ++ break; ++ } ++ /* fall through */ + default: + if (!lock_fb_info(info)) + return -ENODEV; +@@ -1365,6 +1394,7 @@ static long fb_compat_ioctl(struct file + case FBIOPAN_DISPLAY: + case FBIOGET_CON2FBMAP: + case FBIOPUT_CON2FBMAP: ++ case FBIOCOPYAREA: + arg = (unsigned long) compat_ptr(arg); + case FBIOBLANK: + ret = do_fb_ioctl(info, cmd, arg); +--- a/include/uapi/linux/fb.h ++++ b/include/uapi/linux/fb.h +@@ -34,6 +34,11 @@ + #define FBIOPUT_MODEINFO 0x4617 + #define FBIOGET_DISPINFO 0x4618 + #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32) ++/* ++ * HACK: use 'z' in order not to clash with any other ioctl numbers which might ++ * be concurrently added to the mainline kernel ++ */ ++#define FBIOCOPYAREA _IOW('z', 0x21, struct fb_copyarea) + + #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ + #define FB_TYPE_PLANES 1 /* Non interleaved planes */ diff --git a/target/linux/brcm2708/patches-4.1/0029-Speed-up-console-framebuffer-imageblit-function.patch b/target/linux/brcm2708/patches-4.1/0029-Speed-up-console-framebuffer-imageblit-function.patch new file mode 100644 index 0000000..e70db87 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0029-Speed-up-console-framebuffer-imageblit-function.patch @@ -0,0 +1,209 @@ +From 00637200a8710623f0514c98765e2c6bc3a34a37 Mon Sep 17 00:00:00 2001 +From: Harm Hanemaaijer +Date: Thu, 20 Jun 2013 20:21:39 +0200 +Subject: [PATCH 029/203] Speed up console framebuffer imageblit function + +Especially on platforms with a slower CPU but a relatively high +framebuffer fill bandwidth, like current ARM devices, the existing +console monochrome imageblit function used to draw console text is +suboptimal for common pixel depths such as 16bpp and 32bpp. The existing +code is quite general and can deal with several pixel depths. By creating +special case functions for 16bpp and 32bpp, by far the most common pixel +formats used on modern systems, a significant speed-up is attained +which can be readily felt on ARM-based devices like the Raspberry Pi +and the Allwinner platform, but should help any platform using the +fb layer. + +The special case functions allow constant folding, eliminating a number +of instructions including divide operations, and allow the use of an +unrolled loop, eliminating instructions with a variable shift size, +reducing source memory access instructions, and eliminating excessive +branching. These unrolled loops also allow much better code optimization +by the C compiler. The code that selects which optimized variant is used +is also simplified, eliminating integer divide instructions. + +The speed-up, measured by timing 'cat file.txt' in the console, varies +between 40% and 70%, when testing on the Raspberry Pi and Allwinner +ARM-based platforms, depending on font size and the pixel depth, with +the greater benefit for 32bpp. + +Signed-off-by: Harm Hanemaaijer +--- + drivers/video/fbdev/core/cfbimgblt.c | 152 +++++++++++++++++++++++++++++++++-- + 1 file changed, 147 insertions(+), 5 deletions(-) + +--- a/drivers/video/fbdev/core/cfbimgblt.c ++++ b/drivers/video/fbdev/core/cfbimgblt.c +@@ -28,6 +28,11 @@ + * + * Also need to add code to deal with cards endians that are different than + * the native cpu endians. I also need to deal with MSB position in the word. ++ * Modified by Harm Hanemaaijer (fgenfb@yahoo.com) 2013: ++ * - Provide optimized versions of fast_imageblit for 16 and 32bpp that are ++ * significantly faster than the previous implementation. ++ * - Simplify the fast/slow_imageblit selection code, avoiding integer ++ * divides. + */ + #include + #include +@@ -262,6 +267,133 @@ static inline void fast_imageblit(const + } + } + ++/* ++ * Optimized fast_imageblit for bpp == 16. ppw = 2, bit_mask = 3 folded ++ * into the code, main loop unrolled. ++ */ ++ ++static inline void fast_imageblit16(const struct fb_image *image, ++ struct fb_info *p, u8 __iomem * dst1, ++ u32 fgcolor, u32 bgcolor) ++{ ++ u32 fgx = fgcolor, bgx = bgcolor; ++ u32 spitch = (image->width + 7) / 8; ++ u32 end_mask, eorx; ++ const char *s = image->data, *src; ++ u32 __iomem *dst; ++ const u32 *tab = NULL; ++ int i, j, k; ++ ++ tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le; ++ ++ fgx <<= 16; ++ bgx <<= 16; ++ fgx |= fgcolor; ++ bgx |= bgcolor; ++ ++ eorx = fgx ^ bgx; ++ k = image->width / 2; ++ ++ for (i = image->height; i--;) { ++ dst = (u32 __iomem *) dst1; ++ src = s; ++ ++ j = k; ++ while (j >= 4) { ++ u8 bits = *src; ++ end_mask = tab[(bits >> 6) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 4) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 2) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[bits & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ src++; ++ j -= 4; ++ } ++ if (j != 0) { ++ u8 bits = *src; ++ end_mask = tab[(bits >> 6) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ if (j >= 2) { ++ end_mask = tab[(bits >> 4) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ if (j == 3) { ++ end_mask = tab[(bits >> 2) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst); ++ } ++ } ++ } ++ dst1 += p->fix.line_length; ++ s += spitch; ++ } ++} ++ ++/* ++ * Optimized fast_imageblit for bpp == 32. ppw = 1, bit_mask = 1 folded ++ * into the code, main loop unrolled. ++ */ ++ ++static inline void fast_imageblit32(const struct fb_image *image, ++ struct fb_info *p, u8 __iomem * dst1, ++ u32 fgcolor, u32 bgcolor) ++{ ++ u32 fgx = fgcolor, bgx = bgcolor; ++ u32 spitch = (image->width + 7) / 8; ++ u32 end_mask, eorx; ++ const char *s = image->data, *src; ++ u32 __iomem *dst; ++ const u32 *tab = NULL; ++ int i, j, k; ++ ++ tab = cfb_tab32; ++ ++ eorx = fgx ^ bgx; ++ k = image->width; ++ ++ for (i = image->height; i--;) { ++ dst = (u32 __iomem *) dst1; ++ src = s; ++ ++ j = k; ++ while (j >= 8) { ++ u8 bits = *src; ++ end_mask = tab[(bits >> 7) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 6) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 5) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 4) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 3) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 2) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 1) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[bits & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ src++; ++ j -= 8; ++ } ++ if (j != 0) { ++ u32 bits = (u32) * src; ++ while (j > 1) { ++ end_mask = tab[(bits >> 7) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ bits <<= 1; ++ j--; ++ } ++ end_mask = tab[(bits >> 7) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst); ++ } ++ dst1 += p->fix.line_length; ++ s += spitch; ++ } ++} ++ + void cfb_imageblit(struct fb_info *p, const struct fb_image *image) + { + u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0; +@@ -294,11 +426,21 @@ void cfb_imageblit(struct fb_info *p, co + bgcolor = image->bg_color; + } + +- if (32 % bpp == 0 && !start_index && !pitch_index && +- ((width & (32/bpp-1)) == 0) && +- bpp >= 8 && bpp <= 32) +- fast_imageblit(image, p, dst1, fgcolor, bgcolor); +- else ++ if (!start_index && !pitch_index) { ++ if (bpp == 32) ++ fast_imageblit32(image, p, dst1, fgcolor, ++ bgcolor); ++ else if (bpp == 16 && (width & 1) == 0) ++ fast_imageblit16(image, p, dst1, fgcolor, ++ bgcolor); ++ else if (bpp == 8 && (width & 3) == 0) ++ fast_imageblit(image, p, dst1, fgcolor, ++ bgcolor); ++ else ++ slow_imageblit(image, p, dst1, fgcolor, ++ bgcolor, ++ start_index, pitch_index); ++ } else + slow_imageblit(image, p, dst1, fgcolor, bgcolor, + start_index, pitch_index); + } else diff --git a/target/linux/brcm2708/patches-4.1/0030-Allow-mac-address-to-be-set-in-smsc95xx.patch b/target/linux/brcm2708/patches-4.1/0030-Allow-mac-address-to-be-set-in-smsc95xx.patch new file mode 100644 index 0000000..4417b1a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0030-Allow-mac-address-to-be-set-in-smsc95xx.patch @@ -0,0 +1,91 @@ +From 9ac3c3e6aea4f2dccdf5f04b7992e03b58869fd3 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Tue, 26 Mar 2013 17:26:38 +0000 +Subject: [PATCH 030/203] Allow mac address to be set in smsc95xx + +Signed-off-by: popcornmix +--- + drivers/net/usb/smsc95xx.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 56 insertions(+) + +--- a/drivers/net/usb/smsc95xx.c ++++ b/drivers/net/usb/smsc95xx.c +@@ -59,6 +59,7 @@ + #define SUSPEND_SUSPEND3 (0x08) + #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \ + SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3) ++#define MAC_ADDR_LEN (6) + + struct smsc95xx_priv { + u32 mac_cr; +@@ -74,6 +75,10 @@ static bool turbo_mode = true; + module_param(turbo_mode, bool, 0644); + MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); + ++static char *macaddr = ":"; ++module_param(macaddr, charp, 0); ++MODULE_PARM_DESC(macaddr, "MAC address"); ++ + static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index, + u32 *data, int in_pm) + { +@@ -763,8 +768,59 @@ static int smsc95xx_ioctl(struct net_dev + return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); + } + ++/* Check the macaddr module parameter for a MAC address */ ++static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac) ++{ ++ int i, j, got_num, num; ++ u8 mtbl[MAC_ADDR_LEN]; ++ ++ if (macaddr[0] == ':') ++ return 0; ++ ++ i = 0; ++ j = 0; ++ num = 0; ++ got_num = 0; ++ while (j < MAC_ADDR_LEN) { ++ if (macaddr[i] && macaddr[i] != ':') { ++ got_num++; ++ if ('0' <= macaddr[i] && macaddr[i] <= '9') ++ num = num * 16 + macaddr[i] - '0'; ++ else if ('A' <= macaddr[i] && macaddr[i] <= 'F') ++ num = num * 16 + 10 + macaddr[i] - 'A'; ++ else if ('a' <= macaddr[i] && macaddr[i] <= 'f') ++ num = num * 16 + 10 + macaddr[i] - 'a'; ++ else ++ break; ++ i++; ++ } else if (got_num == 2) { ++ mtbl[j++] = (u8) num; ++ num = 0; ++ got_num = 0; ++ i++; ++ } else { ++ break; ++ } ++ } ++ ++ if (j == MAC_ADDR_LEN) { ++ netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: " ++ "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2], ++ mtbl[3], mtbl[4], mtbl[5]); ++ for (i = 0; i < MAC_ADDR_LEN; i++) ++ dev_mac[i] = mtbl[i]; ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ + static void smsc95xx_init_mac_address(struct usbnet *dev) + { ++ /* Check module parameters */ ++ if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr)) ++ return; ++ + /* try reading mac address from EEPROM */ + if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, + dev->net->dev_addr) == 0) { diff --git a/target/linux/brcm2708/patches-4.1/0031-enabling-the-realtime-clock-1-wire-chip-DS1307-and-1.patch b/target/linux/brcm2708/patches-4.1/0031-enabling-the-realtime-clock-1-wire-chip-DS1307-and-1.patch new file mode 100644 index 0000000..90f5c88 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0031-enabling-the-realtime-clock-1-wire-chip-DS1307-and-1.patch @@ -0,0 +1,386 @@ +From ec1be1680332a4676db86178ce9f24917aeeca67 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 8 May 2013 11:46:50 +0100 +Subject: [PATCH 031/203] enabling the realtime clock 1-wire chip DS1307 and + 1-wire on GPIO4 (as a module) + +1-wire: Add support for configuring pin for w1-gpio kernel module +See: https://github.com/raspberrypi/linux/pull/457 + +Add bitbanging pullups, use them for w1-gpio + +Allows parasite power to work, uses module option pullup=1 + +bcm2708: Ensure 1-wire pullup is disabled by default, and expose as module parameter + +Signed-off-by: Alex J Lennon + +w1-gpio: Add gpiopin module parameter and correctly free up gpio pull-up pin, if set + +Signed-off-by: Alex J Lennon + +w1-gpio: Sort out the pullup/parasitic power tangle +--- + arch/arm/mach-bcm2708/bcm2708.c | 29 +++++++++++++++++ + arch/arm/mach-bcm2709/bcm2709.c | 29 +++++++++++++++++ + drivers/w1/masters/w1-gpio.c | 69 +++++++++++++++++++++++++++++++++++++---- + drivers/w1/w1.h | 6 ++++ + drivers/w1/w1_int.c | 14 +++++++++ + drivers/w1/w1_io.c | 18 +++++++++-- + include/linux/w1-gpio.h | 1 + + 7 files changed, 157 insertions(+), 9 deletions(-) + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -77,12 +78,19 @@ + */ + #define DMA_MASK_BITS_COMMON 32 + ++// use GPIO 4 for the one-wire GPIO pin, if enabled ++#define W1_GPIO 4 ++// ensure one-wire GPIO pullup is disabled by default ++#define W1_PULLUP -1 ++ + /* command line parameters */ + static unsigned boardrev, serial; + static unsigned uart_clock = UART0_CLOCK; + static unsigned disk_led_gpio = 16; + static unsigned disk_led_active_low = 1; + static unsigned reboot_part = 0; ++static unsigned w1_gpio_pin = W1_GPIO; ++static unsigned w1_gpio_pullup = W1_PULLUP; + static bool vc_i2c_override = false; + + static unsigned use_dt = 0; +@@ -303,6 +311,20 @@ static struct platform_device bcm2708_dm + .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources), + }; + ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++static struct w1_gpio_platform_data w1_gpio_pdata = { ++ .pin = W1_GPIO, ++ .ext_pullup_enable_pin = W1_PULLUP, ++ .is_open_drain = 0, ++}; ++ ++static struct platform_device w1_device = { ++ .name = "w1-gpio", ++ .id = -1, ++ .dev.platform_data = &w1_gpio_pdata, ++}; ++#endif ++ + static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_fb_device = { +@@ -729,6 +751,11 @@ void __init bcm2708_init(void) + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); + #endif ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++ w1_gpio_pdata.pin = w1_gpio_pin; ++ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup; ++ bcm_register_device_dt(&w1_device); ++#endif + bcm_register_device_dt(&bcm2708_fb_device); + bcm_register_device_dt(&bcm2708_usb_device); + +@@ -942,5 +969,7 @@ module_param(uart_clock, uint, 0644); + module_param(disk_led_gpio, uint, 0644); + module_param(disk_led_active_low, uint, 0644); + module_param(reboot_part, uint, 0644); ++module_param(w1_gpio_pin, uint, 0644); ++module_param(w1_gpio_pullup, uint, 0644); + module_param(vc_i2c_override, bool, 0644); + MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -79,12 +80,19 @@ + */ + #define DMA_MASK_BITS_COMMON 32 + ++// use GPIO 4 for the one-wire GPIO pin, if enabled ++#define W1_GPIO 4 ++// ensure one-wire GPIO pullup is disabled by default ++#define W1_PULLUP -1 ++ + /* command line parameters */ + static unsigned boardrev, serial; + static unsigned uart_clock = UART0_CLOCK; + static unsigned disk_led_gpio = 16; + static unsigned disk_led_active_low = 1; + static unsigned reboot_part = 0; ++static unsigned w1_gpio_pin = W1_GPIO; ++static unsigned w1_gpio_pullup = W1_PULLUP; + static bool vc_i2c_override = false; + + static unsigned use_dt = 0; +@@ -313,6 +321,20 @@ static struct platform_device bcm2708_dm + .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources), + }; + ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++static struct w1_gpio_platform_data w1_gpio_pdata = { ++ .pin = W1_GPIO, ++ .ext_pullup_enable_pin = W1_PULLUP, ++ .is_open_drain = 0, ++}; ++ ++static struct platform_device w1_device = { ++ .name = "w1-gpio", ++ .id = -1, ++ .dev.platform_data = &w1_gpio_pdata, ++}; ++#endif ++ + static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_fb_device = { +@@ -749,6 +771,11 @@ void __init bcm2709_init(void) + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); + #endif ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++ w1_gpio_pdata.pin = w1_gpio_pin; ++ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup; ++ bcm_register_device_dt(&w1_device); ++#endif + bcm_register_device_dt(&bcm2708_fb_device); + bcm_register_device_dt(&bcm2708_usb_device); + +@@ -1110,5 +1137,7 @@ module_param(uart_clock, uint, 0644); + module_param(disk_led_gpio, uint, 0644); + module_param(disk_led_active_low, uint, 0644); + module_param(reboot_part, uint, 0644); ++module_param(w1_gpio_pin, uint, 0644); ++module_param(w1_gpio_pullup, uint, 0644); + module_param(vc_i2c_override, bool, 0644); + MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); +--- a/drivers/w1/masters/w1-gpio.c ++++ b/drivers/w1/masters/w1-gpio.c +@@ -23,6 +23,19 @@ + #include "../w1.h" + #include "../w1_int.h" + ++static int w1_gpio_pullup = 0; ++static int w1_gpio_pullup_orig = 0; ++module_param_named(pullup, w1_gpio_pullup, int, 0); ++MODULE_PARM_DESC(pullup, "Enable parasitic power (power on data) mode"); ++static int w1_gpio_pullup_pin = -1; ++static int w1_gpio_pullup_pin_orig = -1; ++module_param_named(extpullup, w1_gpio_pullup_pin, int, 0); ++MODULE_PARM_DESC(extpullup, "GPIO external pullup pin number"); ++static int w1_gpio_pin = -1; ++static int w1_gpio_pin_orig = -1; ++module_param_named(gpiopin, w1_gpio_pin, int, 0); ++MODULE_PARM_DESC(gpiopin, "GPIO pin number"); ++ + static u8 w1_gpio_set_pullup(void *data, int delay) + { + struct w1_gpio_platform_data *pdata = data; +@@ -67,6 +80,16 @@ static u8 w1_gpio_read_bit(void *data) + return gpio_get_value(pdata->pin) ? 1 : 0; + } + ++static void w1_gpio_bitbang_pullup(void *data, u8 on) ++{ ++ struct w1_gpio_platform_data *pdata = data; ++ ++ if (on) ++ gpio_direction_output(pdata->pin, 1); ++ else ++ gpio_direction_input(pdata->pin); ++} ++ + #if defined(CONFIG_OF) + static const struct of_device_id w1_gpio_dt_ids[] = { + { .compatible = "w1-gpio" }, +@@ -80,6 +103,7 @@ static int w1_gpio_probe_dt(struct platf + struct w1_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct device_node *np = pdev->dev.of_node; + int gpio; ++ u32 value; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) +@@ -88,6 +112,9 @@ static int w1_gpio_probe_dt(struct platf + if (of_get_property(np, "linux,open-drain", NULL)) + pdata->is_open_drain = 1; + ++ if (of_property_read_u32(np, "rpi,parasitic-power", &value) == 0) ++ pdata->parasitic_power = (value != 0); ++ + gpio = of_get_gpio(np, 0); + if (gpio < 0) { + if (gpio != -EPROBE_DEFER) +@@ -103,7 +130,7 @@ static int w1_gpio_probe_dt(struct platf + if (gpio == -EPROBE_DEFER) + return gpio; + /* ignore other errors as the pullup gpio is optional */ +- pdata->ext_pullup_enable_pin = gpio; ++ pdata->ext_pullup_enable_pin = (gpio >= 0) ? gpio : -1; + + pdev->dev.platform_data = pdata; + +@@ -113,13 +140,15 @@ static int w1_gpio_probe_dt(struct platf + static int w1_gpio_probe(struct platform_device *pdev) + { + struct w1_bus_master *master; +- struct w1_gpio_platform_data *pdata; ++ struct w1_gpio_platform_data *pdata = pdev->dev.platform_data; + int err; + +- if (of_have_populated_dt()) { +- err = w1_gpio_probe_dt(pdev); +- if (err < 0) +- return err; ++ if(pdata == NULL) { ++ if (of_have_populated_dt()) { ++ err = w1_gpio_probe_dt(pdev); ++ if (err < 0) ++ return err; ++ } + } + + pdata = dev_get_platdata(&pdev->dev); +@@ -136,6 +165,22 @@ static int w1_gpio_probe(struct platform + return -ENOMEM; + } + ++ w1_gpio_pin_orig = pdata->pin; ++ w1_gpio_pullup_pin_orig = pdata->ext_pullup_enable_pin; ++ w1_gpio_pullup_orig = pdata->parasitic_power; ++ ++ if(gpio_is_valid(w1_gpio_pin)) { ++ pdata->pin = w1_gpio_pin; ++ pdata->ext_pullup_enable_pin = -1; ++ pdata->parasitic_power = -1; ++ } ++ pdata->parasitic_power |= w1_gpio_pullup; ++ if(gpio_is_valid(w1_gpio_pullup_pin)) { ++ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin; ++ } ++ ++ dev_info(&pdev->dev, "gpio pin %d, external pullup pin %d, parasitic power %d\n", pdata->pin, pdata->ext_pullup_enable_pin, pdata->parasitic_power); ++ + err = devm_gpio_request(&pdev->dev, pdata->pin, "w1"); + if (err) { + dev_err(&pdev->dev, "gpio_request (pin) failed\n"); +@@ -165,6 +210,14 @@ static int w1_gpio_probe(struct platform + master->set_pullup = w1_gpio_set_pullup; + } + ++ if (pdata->parasitic_power) { ++ if (pdata->is_open_drain) ++ printk(KERN_ERR "w1-gpio 'pullup'(parasitic power) " ++ "option doesn't work with open drain GPIO\n"); ++ else ++ master->bitbang_pullup = w1_gpio_bitbang_pullup; ++ } ++ + err = w1_add_master_device(master); + if (err) { + dev_err(&pdev->dev, "w1_add_master device failed\n"); +@@ -195,6 +248,10 @@ static int w1_gpio_remove(struct platfor + + w1_remove_master_device(master); + ++ pdata->pin = w1_gpio_pin_orig; ++ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin_orig; ++ pdata->parasitic_power = w1_gpio_pullup_orig; ++ + return 0; + } + +--- a/drivers/w1/w1.h ++++ b/drivers/w1/w1.h +@@ -171,6 +171,12 @@ struct w1_bus_master + + u8 (*set_pullup)(void *, int); + ++ /** ++ * Turns the pullup on/off in bitbanging mode, takes an on/off argument. ++ * @return -1=Error, 0=completed ++ */ ++ void (*bitbang_pullup) (void *, u8); ++ + void (*search)(void *, struct w1_master *, + u8, w1_slave_found_callback); + }; +--- a/drivers/w1/w1_int.c ++++ b/drivers/w1/w1_int.c +@@ -123,6 +123,20 @@ int w1_add_master_device(struct w1_bus_m + return(-EINVAL); + } + ++ /* bitbanging hardware uses bitbang_pullup, other hardware uses set_pullup ++ * and takes care of timing itself */ ++ if (!master->write_byte && !master->touch_bit && master->set_pullup) { ++ printk(KERN_ERR "w1_add_master_device: set_pullup requires " ++ "write_byte or touch_bit, disabling\n"); ++ master->set_pullup = NULL; ++ } ++ ++ if (master->set_pullup && master->bitbang_pullup) { ++ printk(KERN_ERR "w1_add_master_device: set_pullup should not " ++ "be set when bitbang_pullup is used, disabling\n"); ++ master->set_pullup = NULL; ++ } ++ + /* Lock until the device is added (or not) to w1_masters. */ + mutex_lock(&w1_mlock); + /* Search for the first available id (starting at 1). */ +--- a/drivers/w1/w1_io.c ++++ b/drivers/w1/w1_io.c +@@ -134,10 +134,22 @@ static void w1_pre_write(struct w1_maste + static void w1_post_write(struct w1_master *dev) + { + if (dev->pullup_duration) { +- if (dev->enable_pullup && dev->bus_master->set_pullup) +- dev->bus_master->set_pullup(dev->bus_master->data, 0); +- else ++ if (dev->enable_pullup) { ++ if (dev->bus_master->set_pullup) { ++ dev->bus_master->set_pullup(dev-> ++ bus_master->data, ++ 0); ++ } else if (dev->bus_master->bitbang_pullup) { ++ dev->bus_master-> ++ bitbang_pullup(dev->bus_master->data, 1); + msleep(dev->pullup_duration); ++ dev->bus_master-> ++ bitbang_pullup(dev->bus_master->data, 0); ++ } ++ } else { ++ msleep(dev->pullup_duration); ++ } ++ + dev->pullup_duration = 0; + } + } +--- a/include/linux/w1-gpio.h ++++ b/include/linux/w1-gpio.h +@@ -18,6 +18,7 @@ + struct w1_gpio_platform_data { + unsigned int pin; + unsigned int is_open_drain:1; ++ unsigned int parasitic_power:1; + void (*enable_external_pullup)(int enable); + unsigned int ext_pullup_enable_pin; + unsigned int pullup_duration; diff --git a/target/linux/brcm2708/patches-4.1/0032-Added-Device-IDs-for-August-DVB-T-205.patch b/target/linux/brcm2708/patches-4.1/0032-Added-Device-IDs-for-August-DVB-T-205.patch new file mode 100644 index 0000000..f8cf485 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0032-Added-Device-IDs-for-August-DVB-T-205.patch @@ -0,0 +1,22 @@ +From 37da06d2b47b67624a9f2b8c8eec76429f46f10d Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 3 Jul 2013 00:54:08 +0100 +Subject: [PATCH 032/203] Added Device IDs for August DVB-T 205 + +--- + drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c ++++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +@@ -1744,6 +1744,10 @@ static const struct usb_device_id rtl28x + &rtl28xxu_props, "Compro VideoMate U620F", NULL) }, + { DVB_USB_DEVICE(USB_VID_KWORLD_2, 0xd394, + &rtl28xxu_props, "MaxMedia HU394-T", NULL) }, ++ { DVB_USB_DEVICE(USB_VID_GTEK, 0xb803 /*USB_PID_AUGUST_DVBT205*/, ++ &rtl28xxu_props, "August DVB-T 205", NULL) }, ++ { DVB_USB_DEVICE(USB_VID_GTEK, 0xa803 /*USB_PID_AUGUST_DVBT205*/, ++ &rtl28xxu_props, "August DVB-T 205", NULL) }, + { DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a03, + &rtl28xxu_props, "Leadtek WinFast DTV Dongle mini", NULL) }, + { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A, diff --git a/target/linux/brcm2708/patches-4.1/0033-config-Enable-CONFIG_MEMCG-but-leave-it-disabled-due.patch b/target/linux/brcm2708/patches-4.1/0033-config-Enable-CONFIG_MEMCG-but-leave-it-disabled-due.patch new file mode 100644 index 0000000..00a9532 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0033-config-Enable-CONFIG_MEMCG-but-leave-it-disabled-due.patch @@ -0,0 +1,53 @@ +From efd60949b03b034da398f15fc9b74d3f3a06c48a Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 18 Dec 2013 22:16:19 +0000 +Subject: [PATCH 033/203] config: Enable CONFIG_MEMCG, but leave it disabled + (due to memory cost). Enable with cgroup_enable=memory. + +--- + kernel/cgroup.c | 23 +++++++++++++++++++++++ + mm/memcontrol.c | 1 + + 2 files changed, 24 insertions(+) + +--- a/kernel/cgroup.c ++++ b/kernel/cgroup.c +@@ -5394,6 +5394,29 @@ static int __init cgroup_disable(char *s + } + __setup("cgroup_disable=", cgroup_disable); + ++static int __init cgroup_enable(char *str) ++{ ++ struct cgroup_subsys *ss; ++ char *token; ++ int i; ++ ++ while ((token = strsep(&str, ",")) != NULL) { ++ if (!*token) ++ continue; ++ ++ for_each_subsys(ss, i) { ++ if (!strcmp(token, ss->name)) { ++ ss->disabled = 0; ++ printk(KERN_INFO "Enabling %s control group" ++ " subsystem\n", ss->name); ++ break; ++ } ++ } ++ } ++ return 1; ++} ++__setup("cgroup_enable=", cgroup_enable); ++ + static int __init cgroup_set_legacy_files_on_dfl(char *str) + { + printk("cgroup: using legacy files on the default hierarchy\n"); +--- a/mm/memcontrol.c ++++ b/mm/memcontrol.c +@@ -5388,6 +5388,7 @@ struct cgroup_subsys memory_cgrp_subsys + .dfl_cftypes = memory_files, + .legacy_cftypes = mem_cgroup_legacy_files, + .early_init = 0, ++ .disabled = 1, + }; + + /** diff --git a/target/linux/brcm2708/patches-4.1/0034-ASoC-Add-support-for-BCM2708.patch b/target/linux/brcm2708/patches-4.1/0034-ASoC-Add-support-for-BCM2708.patch new file mode 100644 index 0000000..d54690f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0034-ASoC-Add-support-for-BCM2708.patch @@ -0,0 +1,1135 @@ +From 6a93789e8d9296b68c43d10d5ea4a95b73932e44 Mon Sep 17 00:00:00 2001 +From: Florian Meier +Date: Fri, 22 Nov 2013 14:33:38 +0100 +Subject: [PATCH 034/203] ASoC: Add support for BCM2708 + +This driver adds support for digital audio (I2S) +for the BCM2708 SoC that is used by the +Raspberry Pi. External audio codecs can be +connected to the Raspberry Pi via P5 header. + +It relies on cyclic DMA engine support for BCM2708. + +Signed-off-by: Florian Meier + +ASoC: BCM2708: Add 24 bit support + +This adds 24 bit support to the I2S driver of the BCM2708. +Besides enabling the 24 bit flags, it includes two bug fixes: + +MMAP is not supported. Claiming this leads to strange issues +when the format of driver and file do not match. + +The datasheet states that the width extension bit should be set +for widths greater than 24, but greater or equal would be correct. +This follows from the definition of the width field. + +Signed-off-by: Florian Meier + +bcm2708-i2s: Update bclk_ratio to more correct values + +Move GPIO setup to hw_params. + +This is used to stop the I2S driver from breaking +the GPIO setup for other uses of the PCM interface + +Configure GPIOs for I2S based on revision/card settings + +With RPi model B+, assignment of the I2S GPIO pins has changed. +This patch uses the board revision to auto-detect the GPIOs used +for I2S. It also allows sound card drivers to set the GPIOs that +should be used. This is especially important with the Compute +Module. + +bcm2708-i2s: Avoid leak from iomap when accessing gpio + +bcm2708: Eliminate i2s debugfs directory error + +Qualify the two regmap ranges uses by bcm2708-i2s ('-i2s' and '-clk') +to avoid the name clash when registering debugfs entries. +--- + sound/soc/bcm/Kconfig | 11 + + sound/soc/bcm/Makefile | 4 + + sound/soc/bcm/bcm2708-i2s.c | 1009 +++++++++++++++++++++++++++++++++++++++++++ + sound/soc/bcm/bcm2708-i2s.h | 35 ++ + 4 files changed, 1059 insertions(+) + create mode 100644 sound/soc/bcm/bcm2708-i2s.c + create mode 100644 sound/soc/bcm/bcm2708-i2s.h + +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -7,3 +7,14 @@ config SND_BCM2835_SOC_I2S + Say Y or M if you want to add support for codecs attached to + the BCM2835 I2S interface. You will also need + to select the audio interfaces to support below. ++ ++config SND_BCM2708_SOC_I2S ++ tristate "SoC Audio support for the Broadcom BCM2708 I2S module" ++ depends on MACH_BCM2708 || MACH_BCM2709 ++ select REGMAP_MMIO ++ select SND_SOC_DMAENGINE_PCM ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the BCM2708 I2S interface. You will also need ++ to select the audio interfaces to support below. +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -3,3 +3,7 @@ snd-soc-bcm2835-i2s-objs := bcm2835-i2s. + + obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o + ++# BCM2708 Platform Support ++snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o ++ ++obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o +--- /dev/null ++++ b/sound/soc/bcm/bcm2708-i2s.c +@@ -0,0 +1,1009 @@ ++/* ++ * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * Based on ++ * Raspberry Pi PCM I2S ALSA Driver ++ * Copyright (c) by Phil Poole 2013 ++ * ++ * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor ++ * Vladimir Barinov, ++ * Copyright (C) 2007 MontaVista Software, Inc., ++ * ++ * OMAP ALSA SoC DAI driver using McBSP port ++ * Copyright (C) 2008 Nokia Corporation ++ * Contact: Jarkko Nikula ++ * Peter Ujfalusi ++ * ++ * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver ++ * Author: Timur Tabi ++ * Copyright 2007-2010 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include "bcm2708-i2s.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* Clock registers */ ++#define BCM2708_CLK_PCMCTL_REG 0x00 ++#define BCM2708_CLK_PCMDIV_REG 0x04 ++ ++/* Clock register settings */ ++#define BCM2708_CLK_PASSWD (0x5a000000) ++#define BCM2708_CLK_PASSWD_MASK (0xff000000) ++#define BCM2708_CLK_MASH(v) ((v) << 9) ++#define BCM2708_CLK_FLIP BIT(8) ++#define BCM2708_CLK_BUSY BIT(7) ++#define BCM2708_CLK_KILL BIT(5) ++#define BCM2708_CLK_ENAB BIT(4) ++#define BCM2708_CLK_SRC(v) (v) ++ ++#define BCM2708_CLK_SHIFT (12) ++#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT) ++#define BCM2708_CLK_DIVF(v) (v) ++#define BCM2708_CLK_DIVF_MASK (0xFFF) ++ ++enum { ++ BCM2708_CLK_MASH_0 = 0, ++ BCM2708_CLK_MASH_1, ++ BCM2708_CLK_MASH_2, ++ BCM2708_CLK_MASH_3, ++}; ++ ++enum { ++ BCM2708_CLK_SRC_GND = 0, ++ BCM2708_CLK_SRC_OSC, ++ BCM2708_CLK_SRC_DBG0, ++ BCM2708_CLK_SRC_DBG1, ++ BCM2708_CLK_SRC_PLLA, ++ BCM2708_CLK_SRC_PLLC, ++ BCM2708_CLK_SRC_PLLD, ++ BCM2708_CLK_SRC_HDMI, ++}; ++ ++/* Most clocks are not useable (freq = 0) */ ++static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = { ++ [BCM2708_CLK_SRC_GND] = 0, ++ [BCM2708_CLK_SRC_OSC] = 19200000, ++ [BCM2708_CLK_SRC_DBG0] = 0, ++ [BCM2708_CLK_SRC_DBG1] = 0, ++ [BCM2708_CLK_SRC_PLLA] = 0, ++ [BCM2708_CLK_SRC_PLLC] = 0, ++ [BCM2708_CLK_SRC_PLLD] = 500000000, ++ [BCM2708_CLK_SRC_HDMI] = 0, ++}; ++ ++/* I2S registers */ ++#define BCM2708_I2S_CS_A_REG 0x00 ++#define BCM2708_I2S_FIFO_A_REG 0x04 ++#define BCM2708_I2S_MODE_A_REG 0x08 ++#define BCM2708_I2S_RXC_A_REG 0x0c ++#define BCM2708_I2S_TXC_A_REG 0x10 ++#define BCM2708_I2S_DREQ_A_REG 0x14 ++#define BCM2708_I2S_INTEN_A_REG 0x18 ++#define BCM2708_I2S_INTSTC_A_REG 0x1c ++#define BCM2708_I2S_GRAY_REG 0x20 ++ ++/* I2S register settings */ ++#define BCM2708_I2S_STBY BIT(25) ++#define BCM2708_I2S_SYNC BIT(24) ++#define BCM2708_I2S_RXSEX BIT(23) ++#define BCM2708_I2S_RXF BIT(22) ++#define BCM2708_I2S_TXE BIT(21) ++#define BCM2708_I2S_RXD BIT(20) ++#define BCM2708_I2S_TXD BIT(19) ++#define BCM2708_I2S_RXR BIT(18) ++#define BCM2708_I2S_TXW BIT(17) ++#define BCM2708_I2S_CS_RXERR BIT(16) ++#define BCM2708_I2S_CS_TXERR BIT(15) ++#define BCM2708_I2S_RXSYNC BIT(14) ++#define BCM2708_I2S_TXSYNC BIT(13) ++#define BCM2708_I2S_DMAEN BIT(9) ++#define BCM2708_I2S_RXTHR(v) ((v) << 7) ++#define BCM2708_I2S_TXTHR(v) ((v) << 5) ++#define BCM2708_I2S_RXCLR BIT(4) ++#define BCM2708_I2S_TXCLR BIT(3) ++#define BCM2708_I2S_TXON BIT(2) ++#define BCM2708_I2S_RXON BIT(1) ++#define BCM2708_I2S_EN (1) ++ ++#define BCM2708_I2S_CLKDIS BIT(28) ++#define BCM2708_I2S_PDMN BIT(27) ++#define BCM2708_I2S_PDME BIT(26) ++#define BCM2708_I2S_FRXP BIT(25) ++#define BCM2708_I2S_FTXP BIT(24) ++#define BCM2708_I2S_CLKM BIT(23) ++#define BCM2708_I2S_CLKI BIT(22) ++#define BCM2708_I2S_FSM BIT(21) ++#define BCM2708_I2S_FSI BIT(20) ++#define BCM2708_I2S_FLEN(v) ((v) << 10) ++#define BCM2708_I2S_FSLEN(v) (v) ++ ++#define BCM2708_I2S_CHWEX BIT(15) ++#define BCM2708_I2S_CHEN BIT(14) ++#define BCM2708_I2S_CHPOS(v) ((v) << 4) ++#define BCM2708_I2S_CHWID(v) (v) ++#define BCM2708_I2S_CH1(v) ((v) << 16) ++#define BCM2708_I2S_CH2(v) (v) ++ ++#define BCM2708_I2S_TX_PANIC(v) ((v) << 24) ++#define BCM2708_I2S_RX_PANIC(v) ((v) << 16) ++#define BCM2708_I2S_TX(v) ((v) << 8) ++#define BCM2708_I2S_RX(v) (v) ++ ++#define BCM2708_I2S_INT_RXERR BIT(3) ++#define BCM2708_I2S_INT_TXERR BIT(2) ++#define BCM2708_I2S_INT_RXR BIT(1) ++#define BCM2708_I2S_INT_TXW BIT(0) ++ ++/* I2S DMA interface */ ++#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004 ++#define BCM2708_DMA_DREQ_PCM_TX 2 ++#define BCM2708_DMA_DREQ_PCM_RX 3 ++ ++/* I2S pin configuration */ ++static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO; ++ ++/* General device struct */ ++struct bcm2708_i2s_dev { ++ struct device *dev; ++ struct snd_dmaengine_dai_dma_data dma_data[2]; ++ unsigned int fmt; ++ unsigned int bclk_ratio; ++ ++ struct regmap *i2s_regmap; ++ struct regmap *clk_regmap; ++}; ++ ++void bcm2708_i2s_set_gpio(int gpio) { ++ bcm2708_i2s_gpio=gpio; ++} ++EXPORT_SYMBOL(bcm2708_i2s_set_gpio); ++ ++ ++static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev) ++{ ++ /* Start the clock if in master mode */ ++ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; ++ ++ switch (master) { ++ case SND_SOC_DAIFMT_CBS_CFS: ++ case SND_SOC_DAIFMT_CBS_CFM: ++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, ++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, ++ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev) ++{ ++ uint32_t clkreg; ++ int timeout = 1000; ++ ++ /* Stop clock */ ++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, ++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, ++ BCM2708_CLK_PASSWD); ++ ++ /* Wait for the BUSY flag going down */ ++ while (--timeout) { ++ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg); ++ if (!(clkreg & BCM2708_CLK_BUSY)) ++ break; ++ } ++ ++ if (!timeout) { ++ /* KILL the clock */ ++ dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n"); ++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, ++ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK, ++ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD); ++ } ++} ++ ++static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev, ++ bool tx, bool rx) ++{ ++ int timeout = 1000; ++ uint32_t syncval; ++ uint32_t csreg; ++ uint32_t i2s_active_state; ++ uint32_t clkreg; ++ uint32_t clk_active_state; ++ uint32_t off; ++ uint32_t clr; ++ ++ off = tx ? BCM2708_I2S_TXON : 0; ++ off |= rx ? BCM2708_I2S_RXON : 0; ++ ++ clr = tx ? BCM2708_I2S_TXCLR : 0; ++ clr |= rx ? BCM2708_I2S_RXCLR : 0; ++ ++ /* Backup the current state */ ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); ++ i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON); ++ ++ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg); ++ clk_active_state = clkreg & BCM2708_CLK_ENAB; ++ ++ /* Start clock if not running */ ++ if (!clk_active_state) { ++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, ++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, ++ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB); ++ } ++ ++ /* Stop I2S module */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0); ++ ++ /* ++ * Clear the FIFOs ++ * Requires at least 2 PCM clock cycles to take effect ++ */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr); ++ ++ /* Wait for 2 PCM clock cycles */ ++ ++ /* ++ * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back ++ * FIXME: This does not seem to work for slave mode! ++ */ ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval); ++ syncval &= BCM2708_I2S_SYNC; ++ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_SYNC, ~syncval); ++ ++ /* Wait for the SYNC flag changing it's state */ ++ while (--timeout) { ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); ++ if ((csreg & BCM2708_I2S_SYNC) != syncval) ++ break; ++ } ++ ++ if (!timeout) ++ dev_err(dev->dev, "I2S SYNC error!\n"); ++ ++ /* Stop clock if it was not running before */ ++ if (!clk_active_state) ++ bcm2708_i2s_stop_clock(dev); ++ ++ /* Restore I2S state */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state); ++} ++ ++static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai, ++ unsigned int fmt) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ dev->fmt = fmt; ++ return 0; ++} ++ ++static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, ++ unsigned int ratio) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ dev->bclk_ratio = ratio; ++ return 0; ++} ++ ++ ++static int bcm2708_i2s_set_function(unsigned offset, int function) ++{ ++ #define GPIOFSEL(x) (0x00+(x)*4) ++ void __iomem *gpio = __io_address(GPIO_BASE); ++ unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ gpiodir = readl(gpio + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= alt << gpio_field_offset; ++ writel(gpiodir, gpio + GPIOFSEL(gpio_bank)); ++ return 0; ++} ++ ++static void bcm2708_i2s_setup_gpio(void) ++{ ++ /* ++ * This is the common way to handle the GPIO pins for ++ * the Raspberry Pi. ++ * TODO Better way would be to handle ++ * this in the device tree! ++ */ ++ int pin,pinconfig,startpin,alt; ++ ++ /* SPI is on different GPIOs on different boards */ ++ /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */ ++ if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) { ++ if ((system_rev & 0xffffff) >= 0x10) { ++ /* Model B+ */ ++ pinconfig=BCM2708_I2S_GPIO_PIN18; ++ } else { ++ /* original */ ++ pinconfig=BCM2708_I2S_GPIO_PIN28; ++ } ++ } else { ++ pinconfig=bcm2708_i2s_gpio; ++ } ++ ++ if (pinconfig==BCM2708_I2S_GPIO_PIN18) { ++ startpin=18; ++ alt=BCM2708_I2S_GPIO_PIN18_ALT; ++ } else if (pinconfig==BCM2708_I2S_GPIO_PIN28) { ++ startpin=28; ++ alt=BCM2708_I2S_GPIO_PIN28_ALT; ++ } else { ++ printk(KERN_INFO "Can't configure I2S GPIOs, unknown pin mode for I2S: %i\n",pinconfig); ++ return; ++ } ++ ++ /* configure I2S pins to correct ALT mode */ ++ for (pin = startpin; pin <= startpin+3; pin++) { ++ bcm2708_i2s_set_function(pin, alt); ++ } ++} ++ ++static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ ++ unsigned int sampling_rate = params_rate(params); ++ unsigned int data_length, data_delay, bclk_ratio; ++ unsigned int ch1pos, ch2pos, mode, format; ++ unsigned int mash = BCM2708_CLK_MASH_1; ++ unsigned int divi, divf, target_frequency; ++ int clk_src = -1; ++ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; ++ bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS ++ || master == SND_SOC_DAIFMT_CBS_CFM); ++ ++ bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS ++ || master == SND_SOC_DAIFMT_CBM_CFS); ++ uint32_t csreg; ++ ++ /* ++ * If a stream is already enabled, ++ * the registers are already set properly. ++ */ ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); ++ ++ if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON)) ++ return 0; ++ ++ ++ bcm2708_i2s_setup_gpio(); ++ ++ /* ++ * Adjust the data length according to the format. ++ * We prefill the half frame length with an integer ++ * divider of 2400 as explained at the clock settings. ++ * Maybe it is overwritten there, if the Integer mode ++ * does not apply. ++ */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ data_length = 16; ++ bclk_ratio = 50; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ data_length = 24; ++ bclk_ratio = 50; ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ data_length = 32; ++ bclk_ratio = 100; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* If bclk_ratio already set, use that one. */ ++ if (dev->bclk_ratio) ++ bclk_ratio = dev->bclk_ratio; ++ ++ /* ++ * Clock Settings ++ * ++ * The target frequency of the bit clock is ++ * sampling rate * frame length ++ * ++ * Integer mode: ++ * Sampling rates that are multiples of 8000 kHz ++ * can be driven by the oscillator of 19.2 MHz ++ * with an integer divider as long as the frame length ++ * is an integer divider of 19200000/8000=2400 as set up above. ++ * This is no longer possible if the sampling rate ++ * is too high (e.g. 192 kHz), because the oscillator is too slow. ++ * ++ * MASH mode: ++ * For all other sampling rates, it is not possible to ++ * have an integer divider. Approximate the clock ++ * with the MASH module that induces a slight frequency ++ * variance. To minimize that it is best to have the fastest ++ * clock here. That is PLLD with 500 MHz. ++ */ ++ target_frequency = sampling_rate * bclk_ratio; ++ clk_src = BCM2708_CLK_SRC_OSC; ++ mash = BCM2708_CLK_MASH_0; ++ ++ if (bcm2708_clk_freq[clk_src] % target_frequency == 0 ++ && bit_master && frame_master) { ++ divi = bcm2708_clk_freq[clk_src] / target_frequency; ++ divf = 0; ++ } else { ++ uint64_t dividend; ++ ++ if (!dev->bclk_ratio) { ++ /* ++ * Overwrite bclk_ratio, because the ++ * above trick is not needed or can ++ * not be used. ++ */ ++ bclk_ratio = 2 * data_length; ++ } ++ ++ target_frequency = sampling_rate * bclk_ratio; ++ ++ clk_src = BCM2708_CLK_SRC_PLLD; ++ mash = BCM2708_CLK_MASH_1; ++ ++ dividend = bcm2708_clk_freq[clk_src]; ++ dividend <<= BCM2708_CLK_SHIFT; ++ do_div(dividend, target_frequency); ++ divi = dividend >> BCM2708_CLK_SHIFT; ++ divf = dividend & BCM2708_CLK_DIVF_MASK; ++ } ++ ++ /* Clock should only be set up here if CPU is clock master */ ++ if (((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFS) || ++ ((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFM)) { ++ /* Set clock divider */ ++ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD ++ | BCM2708_CLK_DIVI(divi) ++ | BCM2708_CLK_DIVF(divf)); ++ ++ /* Setup clock, but don't start it yet */ ++ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD ++ | BCM2708_CLK_MASH(mash) ++ | BCM2708_CLK_SRC(clk_src)); ++ } ++ ++ /* Setup the frame format */ ++ format = BCM2708_I2S_CHEN; ++ ++ if (data_length >= 24) ++ format |= BCM2708_I2S_CHWEX; ++ ++ format |= BCM2708_I2S_CHWID((data_length-8)&0xf); ++ ++ switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ data_delay = 1; ++ break; ++ default: ++ /* ++ * TODO ++ * Others are possible but are not implemented at the moment. ++ */ ++ dev_err(dev->dev, "%s:bad format\n", __func__); ++ return -EINVAL; ++ } ++ ++ ch1pos = data_delay; ++ ch2pos = bclk_ratio / 2 + data_delay; ++ ++ switch (params_channels(params)) { ++ case 2: ++ format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format); ++ format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos)); ++ format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos)); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* ++ * Set format for both streams. ++ * We cannot set another frame length ++ * (and therefore word length) anyway, ++ * so the format will be the same. ++ */ ++ regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format); ++ regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format); ++ ++ /* Setup the I2S mode */ ++ mode = 0; ++ ++ if (data_length <= 16) { ++ /* ++ * Use frame packed mode (2 channels per 32 bit word) ++ * We cannot set another frame length in the second stream ++ * (and therefore word length) anyway, ++ * so the format will be the same. ++ */ ++ mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP; ++ } ++ ++ mode |= BCM2708_I2S_FLEN(bclk_ratio - 1); ++ mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2); ++ ++ /* Master or slave? */ ++ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBS_CFS: ++ /* CPU is master */ ++ break; ++ case SND_SOC_DAIFMT_CBM_CFS: ++ /* ++ * CODEC is bit clock master ++ * CPU is frame master ++ */ ++ mode |= BCM2708_I2S_CLKM; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFM: ++ /* ++ * CODEC is frame master ++ * CPU is bit clock master ++ */ ++ mode |= BCM2708_I2S_FSM; ++ break; ++ case SND_SOC_DAIFMT_CBM_CFM: ++ /* CODEC is master */ ++ mode |= BCM2708_I2S_CLKM; ++ mode |= BCM2708_I2S_FSM; ++ break; ++ default: ++ dev_err(dev->dev, "%s:bad master\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Invert clocks? ++ * ++ * The BCM approach seems to be inverted to the classical I2S approach. ++ */ ++ switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ /* None. Therefore, both for BCM */ ++ mode |= BCM2708_I2S_CLKI; ++ mode |= BCM2708_I2S_FSI; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ /* Both. Therefore, none for BCM */ ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ /* ++ * Invert only frame sync. Therefore, ++ * invert only bit clock for BCM ++ */ ++ mode |= BCM2708_I2S_CLKI; ++ break; ++ case SND_SOC_DAIFMT_IB_NF: ++ /* ++ * Invert only bit clock. Therefore, ++ * invert only frame sync for BCM ++ */ ++ mode |= BCM2708_I2S_FSI; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode); ++ ++ /* Setup the DMA parameters */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_RXTHR(1) ++ | BCM2708_I2S_TXTHR(1) ++ | BCM2708_I2S_DMAEN, 0xffffffff); ++ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG, ++ BCM2708_I2S_TX_PANIC(0x10) ++ | BCM2708_I2S_RX_PANIC(0x30) ++ | BCM2708_I2S_TX(0x30) ++ | BCM2708_I2S_RX(0x20), 0xffffffff); ++ ++ /* Clear FIFOs */ ++ bcm2708_i2s_clear_fifos(dev, true, true); ++ ++ return 0; ++} ++ ++static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ uint32_t cs_reg; ++ ++ bcm2708_i2s_start_clock(dev); ++ ++ /* ++ * Clear both FIFOs if the one that should be started ++ * is not empty at the moment. This should only happen ++ * after overrun. Otherwise, hw_params would have cleared ++ * the FIFO. ++ */ ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ++ && !(cs_reg & BCM2708_I2S_TXE)) ++ bcm2708_i2s_clear_fifos(dev, true, false); ++ else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE ++ && (cs_reg & BCM2708_I2S_RXD)) ++ bcm2708_i2s_clear_fifos(dev, false, true); ++ ++ return 0; ++} ++ ++static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev, ++ struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ uint32_t mask; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ mask = BCM2708_I2S_RXON; ++ else ++ mask = BCM2708_I2S_TXON; ++ ++ regmap_update_bits(dev->i2s_regmap, ++ BCM2708_I2S_CS_A_REG, mask, 0); ++ ++ /* Stop also the clock when not SND_SOC_DAIFMT_CONT */ ++ if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT)) ++ bcm2708_i2s_stop_clock(dev); ++} ++ ++static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ uint32_t mask; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ bcm2708_i2s_start_clock(dev); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ mask = BCM2708_I2S_RXON; ++ else ++ mask = BCM2708_I2S_TXON; ++ ++ regmap_update_bits(dev->i2s_regmap, ++ BCM2708_I2S_CS_A_REG, mask, mask); ++ break; ++ ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ bcm2708_i2s_stop(dev, substream, dai); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int bcm2708_i2s_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ ++ if (dai->active) ++ return 0; ++ ++ /* Should this still be running stop it */ ++ bcm2708_i2s_stop_clock(dev); ++ ++ /* Enable PCM block */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_EN, BCM2708_I2S_EN); ++ ++ /* ++ * Disable STBY. ++ * Requires at least 4 PCM clock cycles to take effect. ++ */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_STBY, BCM2708_I2S_STBY); ++ ++ return 0; ++} ++ ++static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ ++ bcm2708_i2s_stop(dev, substream, dai); ++ ++ /* If both streams are stopped, disable module and clock */ ++ if (dai->active) ++ return; ++ ++ /* Disable the module */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_EN, 0); ++ ++ /* ++ * Stopping clock is necessary, because stop does ++ * not stop the clock when SND_SOC_DAIFMT_CONT ++ */ ++ bcm2708_i2s_stop_clock(dev); ++} ++ ++static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = { ++ .startup = bcm2708_i2s_startup, ++ .shutdown = bcm2708_i2s_shutdown, ++ .prepare = bcm2708_i2s_prepare, ++ .trigger = bcm2708_i2s_trigger, ++ .hw_params = bcm2708_i2s_hw_params, ++ .set_fmt = bcm2708_i2s_set_dai_fmt, ++ .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio ++}; ++ ++static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ ++ dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; ++ dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]; ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_driver bcm2708_i2s_dai = { ++ .name = "bcm2708-i2s", ++ .probe = bcm2708_i2s_dai_probe, ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE ++ }, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE ++ }, ++ .ops = &bcm2708_i2s_dai_ops, ++ .symmetric_rates = 1 ++}; ++ ++static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case BCM2708_I2S_CS_A_REG: ++ case BCM2708_I2S_FIFO_A_REG: ++ case BCM2708_I2S_INTSTC_A_REG: ++ case BCM2708_I2S_GRAY_REG: ++ return true; ++ default: ++ return false; ++ }; ++} ++ ++static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case BCM2708_I2S_FIFO_A_REG: ++ return true; ++ default: ++ return false; ++ }; ++} ++ ++static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case BCM2708_CLK_PCMCTL_REG: ++ return true; ++ default: ++ return false; ++ }; ++} ++ ++static const struct regmap_config bcm2708_regmap_config[] = { ++ { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = BCM2708_I2S_GRAY_REG, ++ .precious_reg = bcm2708_i2s_precious_reg, ++ .volatile_reg = bcm2708_i2s_volatile_reg, ++ .cache_type = REGCACHE_RBTREE, ++ .name = "i2s", ++ }, ++ { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = BCM2708_CLK_PCMDIV_REG, ++ .volatile_reg = bcm2708_clk_volatile_reg, ++ .cache_type = REGCACHE_RBTREE, ++ .name = "clk", ++ }, ++}; ++ ++static const struct snd_soc_component_driver bcm2708_i2s_component = { ++ .name = "bcm2708-i2s-comp", ++}; ++ ++static const struct snd_pcm_hardware bcm2708_pcm_hardware = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_JOINT_DUPLEX, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE, ++ .period_bytes_min = 32, ++ .period_bytes_max = 64 * PAGE_SIZE, ++ .periods_min = 2, ++ .periods_max = 255, ++ .buffer_bytes_max = 128 * PAGE_SIZE, ++}; ++ ++static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = { ++ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, ++ .pcm_hardware = &bcm2708_pcm_hardware, ++ .prealloc_buffer_size = 256 * PAGE_SIZE, ++}; ++ ++ ++static int bcm2708_i2s_probe(struct platform_device *pdev) ++{ ++ struct bcm2708_i2s_dev *dev; ++ int i; ++ int ret; ++ struct regmap *regmap[2]; ++ struct resource *mem[2]; ++ ++ /* Request both ioareas */ ++ for (i = 0; i <= 1; i++) { ++ void __iomem *base; ++ ++ mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ base = devm_ioremap_resource(&pdev->dev, mem[i]); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ regmap[i] = devm_regmap_init_mmio(&pdev->dev, base, ++ &bcm2708_regmap_config[i]); ++ if (IS_ERR(regmap[i])) { ++ dev_err(&pdev->dev, "I2S probe: regmap init failed\n"); ++ return PTR_ERR(regmap[i]); ++ } ++ } ++ ++ dev = devm_kzalloc(&pdev->dev, sizeof(*dev), ++ GFP_KERNEL); ++ if (IS_ERR(dev)) ++ return PTR_ERR(dev); ++ ++ dev->i2s_regmap = regmap[0]; ++ dev->clk_regmap = regmap[1]; ++ ++ /* Set the DMA address */ ++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = ++ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR; ++ ++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = ++ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR; ++ ++ /* Set the DREQ */ ++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id = ++ BCM2708_DMA_DREQ_PCM_TX; ++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id = ++ BCM2708_DMA_DREQ_PCM_RX; ++ ++ /* Set the bus width */ ++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width = ++ DMA_SLAVE_BUSWIDTH_4_BYTES; ++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width = ++ DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ++ /* Set burst */ ++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2; ++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2; ++ ++ /* BCLK ratio - use default */ ++ dev->bclk_ratio = 0; ++ ++ /* Store the pdev */ ++ dev->dev = &pdev->dev; ++ dev_set_drvdata(&pdev->dev, dev); ++ ++ ret = snd_soc_register_component(&pdev->dev, ++ &bcm2708_i2s_component, &bcm2708_i2s_dai, 1); ++ ++ if (ret) { ++ dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); ++ ret = -ENOMEM; ++ return ret; ++ } ++ ++ ret = snd_dmaengine_pcm_register(&pdev->dev, ++ &bcm2708_dmaengine_pcm_config, ++ SND_DMAENGINE_PCM_FLAG_COMPAT); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); ++ snd_soc_unregister_component(&pdev->dev); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int bcm2708_i2s_remove(struct platform_device *pdev) ++{ ++ snd_dmaengine_pcm_unregister(&pdev->dev); ++ snd_soc_unregister_component(&pdev->dev); ++ return 0; ++} ++ ++static const struct of_device_id bcm2708_i2s_of_match[] = { ++ { .compatible = "brcm,bcm2708-i2s", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2708_i2s_of_match); ++ ++static struct platform_driver bcm2708_i2s_driver = { ++ .probe = bcm2708_i2s_probe, ++ .remove = bcm2708_i2s_remove, ++ .driver = { ++ .name = "bcm2708-i2s", ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2708_i2s_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2708_i2s_driver); ++ ++MODULE_ALIAS("platform:bcm2708-i2s"); ++MODULE_DESCRIPTION("BCM2708 I2S interface"); ++MODULE_AUTHOR("Florian Meier "); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/sound/soc/bcm/bcm2708-i2s.h +@@ -0,0 +1,35 @@ ++/* ++ * I2S configuration for sound cards. ++ * ++ * Copyright (c) 2014 Daniel Matuschek ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef BCM2708_I2S_H ++#define BCM2708_I2S_H ++ ++/* I2S pin assignment */ ++#define BCM2708_I2S_GPIO_AUTO 0 ++#define BCM2708_I2S_GPIO_PIN18 1 ++#define BCM2708_I2S_GPIO_PIN28 2 ++ ++/* Alt mode to enable I2S */ ++#define BCM2708_I2S_GPIO_PIN18_ALT 0 ++#define BCM2708_I2S_GPIO_PIN28_ALT 2 ++ ++extern void bcm2708_i2s_set_gpio(int gpio); ++ ++#endif diff --git a/target/linux/brcm2708/patches-4.1/0035-ASoC-Add-support-for-PCM5102A-codec.patch b/target/linux/brcm2708/patches-4.1/0035-ASoC-Add-support-for-PCM5102A-codec.patch new file mode 100644 index 0000000..7f1ce76 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0035-ASoC-Add-support-for-PCM5102A-codec.patch @@ -0,0 +1,120 @@ +From f5d02596d7770a458ca6a99e250369fdecfdb763 Mon Sep 17 00:00:00 2001 +From: Florian Meier +Date: Fri, 22 Nov 2013 14:59:51 +0100 +Subject: [PATCH 035/203] ASoC: Add support for PCM5102A codec + +Some definitions to support the PCM5102A codec +by Texas Instruments. + +Signed-off-by: Florian Meier +--- + sound/soc/codecs/Kconfig | 4 +++ + sound/soc/codecs/Makefile | 2 ++ + sound/soc/codecs/pcm5102a.c | 63 +++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 69 insertions(+) + create mode 100644 sound/soc/codecs/pcm5102a.c + +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -83,6 +83,7 @@ config SND_SOC_ALL_CODECS + select SND_SOC_PCM512x_I2C if I2C + select SND_SOC_PCM512x_SPI if SPI_MASTER + select SND_SOC_RT286 if I2C ++ select SND_SOC_PCM5102A if I2C + select SND_SOC_RT5631 if I2C + select SND_SOC_RT5640 if I2C + select SND_SOC_RT5645 if I2C +@@ -511,6 +512,9 @@ config SND_SOC_RT286 + tristate + depends on I2C + ++config SND_SOC_PCM5102A ++ tristate ++ + config SND_SOC_RT5631 + tristate "Realtek ALC5631/RT5631 CODEC" + depends on I2C +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -78,6 +78,7 @@ snd-soc-pcm512x-i2c-objs := pcm512x-i2c. + snd-soc-pcm512x-spi-objs := pcm512x-spi.o + snd-soc-rl6231-objs := rl6231.o + snd-soc-rt286-objs := rt286.o ++snd-soc-pcm5102a-objs := pcm5102a.o + snd-soc-rt5631-objs := rt5631.o + snd-soc-rt5640-objs := rt5640.o + snd-soc-rt5645-objs := rt5645.o +@@ -263,6 +264,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd + obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o + obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o + obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o ++obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o + obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o + obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o + obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o +--- /dev/null ++++ b/sound/soc/codecs/pcm5102a.c +@@ -0,0 +1,63 @@ ++/* ++ * Driver for the PCM5102A codec ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++ ++#include ++#include ++#include ++ ++#include ++ ++static struct snd_soc_dai_driver pcm5102a_dai = { ++ .name = "pcm5102a-hifi", ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE ++ }, ++}; ++ ++static struct snd_soc_codec_driver soc_codec_dev_pcm5102a; ++ ++static int pcm5102a_probe(struct platform_device *pdev) ++{ ++ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm5102a, ++ &pcm5102a_dai, 1); ++} ++ ++static int pcm5102a_remove(struct platform_device *pdev) ++{ ++ snd_soc_unregister_codec(&pdev->dev); ++ return 0; ++} ++ ++static struct platform_driver pcm5102a_codec_driver = { ++ .probe = pcm5102a_probe, ++ .remove = pcm5102a_remove, ++ .driver = { ++ .name = "pcm5102a-codec", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(pcm5102a_codec_driver); ++ ++MODULE_DESCRIPTION("ASoC PCM5102A codec driver"); ++MODULE_AUTHOR("Florian Meier "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0036-BCM2708-Add-I2S-support-to-board-file.patch b/target/linux/brcm2708/patches-4.1/0036-BCM2708-Add-I2S-support-to-board-file.patch new file mode 100644 index 0000000..223b6a0 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0036-BCM2708-Add-I2S-support-to-board-file.patch @@ -0,0 +1,87 @@ +From 272e93911327e40ec57facd1fbc37e98b06c8c79 Mon Sep 17 00:00:00 2001 +From: Florian Meier +Date: Fri, 22 Nov 2013 19:04:54 +0100 +Subject: [PATCH 036/203] BCM2708: Add I2S support to board file + +Adds the required initializations for I2S +to the board file of mach-bcm2708. + +Signed-off-by: Florian Meier + +bcm2708-i2s: Enable MMAP support via a DT property and overlay + +The i2s driver used to claim to support MMAP, but that feature was disabled +when some problems were found. Add the ability to enable this feature +through Device Tree, using the i2s-mmap overlay. + +See: #1004 +--- + arch/arm/mach-bcm2708/bcm2708.c | 26 ++++++++++++++++++++++++++ + sound/soc/bcm/bcm2708-i2s.c | 7 ++++++- + 2 files changed, 32 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -616,6 +616,28 @@ static struct platform_device bcm2835_th + .name = "bcm2835_thermal", + }; + ++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) ++static struct resource bcm2708_i2s_resources[] = { ++ { ++ .start = I2S_BASE, ++ .end = I2S_BASE + 0x20, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = PCM_CLOCK_BASE, ++ .end = PCM_CLOCK_BASE + 0x02, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct platform_device bcm2708_i2s_device = { ++ .name = "bcm2708-i2s", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources), ++ .resource = bcm2708_i2s_resources, ++}; ++#endif ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -780,6 +802,10 @@ void __init bcm2708_init(void) + + bcm_register_device_dt(&bcm2835_thermal_device); + ++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) ++ bcm_register_device_dt(&bcm2708_i2s_device); ++#endif ++ + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; +--- a/sound/soc/bcm/bcm2708-i2s.c ++++ b/sound/soc/bcm/bcm2708-i2s.c +@@ -874,7 +874,7 @@ static const struct snd_soc_component_dr + .name = "bcm2708-i2s-comp", + }; + +-static const struct snd_pcm_hardware bcm2708_pcm_hardware = { ++static struct snd_pcm_hardware bcm2708_pcm_hardware = { + .info = SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_JOINT_DUPLEX, + .formats = SNDRV_PCM_FMTBIT_S16_LE | +@@ -902,6 +902,11 @@ static int bcm2708_i2s_probe(struct plat + struct regmap *regmap[2]; + struct resource *mem[2]; + ++ if (of_property_read_bool(pdev->dev.of_node, "brcm,enable-mmap")) ++ bcm2708_pcm_hardware.info |= ++ SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID; ++ + /* Request both ioareas */ + for (i = 0; i <= 1; i++) { + void __iomem *base; diff --git a/target/linux/brcm2708/patches-4.1/0037-ASoC-Add-support-for-HifiBerry-DAC.patch b/target/linux/brcm2708/patches-4.1/0037-ASoC-Add-support-for-HifiBerry-DAC.patch new file mode 100644 index 0000000..66aa907 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0037-ASoC-Add-support-for-HifiBerry-DAC.patch @@ -0,0 +1,144 @@ +From 1c2bf7278b4ac192fed80b01b404a2d44b68b124 Mon Sep 17 00:00:00 2001 +From: Florian Meier +Date: Fri, 22 Nov 2013 19:19:08 +0100 +Subject: [PATCH 037/203] ASoC: Add support for HifiBerry DAC + +This adds a machine driver for the HifiBerry DAC. +It is a sound card that can +be stacked onto the Raspberry Pi. + +Signed-off-by: Florian Meier +--- + sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Makefile | 5 +++ + sound/soc/bcm/hifiberry_dac.c | 100 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 112 insertions(+) + create mode 100644 sound/soc/bcm/hifiberry_dac.c + +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -18,3 +18,10 @@ config SND_BCM2708_SOC_I2S + Say Y or M if you want to add support for codecs attached to + the BCM2708 I2S interface. You will also need + to select the audio interfaces to support below. ++ ++config SND_BCM2708_SOC_HIFIBERRY_DAC ++ tristate "Support for HifiBerry DAC" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_PCM5102A ++ help ++ Say Y or M if you want to add support for HifiBerry DAC. +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -7,3 +7,8 @@ obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd + snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o + + obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o ++ ++# BCM2708 Machine Support ++snd-soc-hifiberry-dac-objs := hifiberry_dac.o ++ ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o +--- /dev/null ++++ b/sound/soc/bcm/hifiberry_dac.c +@@ -0,0 +1,100 @@ ++/* ++ * ASoC Driver for HifiBerry DAC ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static int snd_rpi_hifiberry_dac_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_dac_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ unsigned int sample_bits = ++ snd_pcm_format_physical_width(params_format(params)); ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_hifiberry_dac_ops = { ++ .hw_params = snd_rpi_hifiberry_dac_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_hifiberry_dac_dai[] = { ++{ ++ .name = "HifiBerry DAC", ++ .stream_name = "HifiBerry DAC HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm5102a-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm5102a-codec", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_hifiberry_dac_ops, ++ .init = snd_rpi_hifiberry_dac_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_hifiberry_dac = { ++ .name = "snd_rpi_hifiberry_dac", ++ .dai_link = snd_rpi_hifiberry_dac_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dac_dai), ++}; ++ ++static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_hifiberry_dac.dev = &pdev->dev; ++ ret = snd_soc_register_card(&snd_rpi_hifiberry_dac); ++ if (ret) ++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_hifiberry_dac); ++} ++ ++static struct platform_driver snd_rpi_hifiberry_dac_driver = { ++ .driver = { ++ .name = "snd-hifiberry-dac", ++ .owner = THIS_MODULE, ++ }, ++ .probe = snd_rpi_hifiberry_dac_probe, ++ .remove = snd_rpi_hifiberry_dac_remove, ++}; ++ ++module_platform_driver(snd_rpi_hifiberry_dac_driver); ++ ++MODULE_AUTHOR("Florian Meier "); ++MODULE_DESCRIPTION("ASoC Driver for HifiBerry DAC"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0038-BCM2708-Add-HifiBerry-DAC-to-board-file.patch b/target/linux/brcm2708/patches-4.1/0038-BCM2708-Add-HifiBerry-DAC-to-board-file.patch new file mode 100644 index 0000000..8186b22 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0038-BCM2708-Add-HifiBerry-DAC-to-board-file.patch @@ -0,0 +1,48 @@ +From 66cb299f5c712d92e1bb69468cdbb7ca481ab777 Mon Sep 17 00:00:00 2001 +From: Florian Meier +Date: Fri, 22 Nov 2013 19:21:34 +0100 +Subject: [PATCH 038/203] BCM2708: Add HifiBerry DAC to board file + +This adds the initalization of the HifiBerry DAC +to the mach-bcm2708 board file. + +Signed-off-by: Florian Meier +--- + arch/arm/mach-bcm2708/bcm2708.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -638,6 +638,20 @@ static struct platform_device bcm2708_i2 + }; + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) ++static struct platform_device snd_hifiberry_dac_device = { ++ .name = "snd-hifiberry-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct platform_device snd_pcm5102a_codec_device = { ++ .name = "pcm5102a-codec", ++ .id = -1, ++ .num_resources = 0, ++}; ++#endif ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -806,6 +820,11 @@ void __init bcm2708_init(void) + bcm_register_device_dt(&bcm2708_i2s_device); + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_dac_device); ++ bcm_register_device_dt(&snd_pcm5102a_codec_device); ++#endif ++ + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; diff --git a/target/linux/brcm2708/patches-4.1/0039-ASoC-BCM2708-Add-support-for-RPi-DAC.patch b/target/linux/brcm2708/patches-4.1/0039-ASoC-BCM2708-Add-support-for-RPi-DAC.patch new file mode 100644 index 0000000..baa13cf --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0039-ASoC-BCM2708-Add-support-for-RPi-DAC.patch @@ -0,0 +1,281 @@ +From c3a1a7754a288b6c49041fcc69f79c51b36caa73 Mon Sep 17 00:00:00 2001 +From: Florian Meier +Date: Fri, 6 Dec 2013 20:50:28 +0100 +Subject: [PATCH 039/203] ASoC: BCM2708: Add support for RPi-DAC + +This adds a machine driver for the RPi-DAC. + +Signed-off-by: Florian Meier +--- + arch/arm/mach-bcm2708/bcm2708.c | 19 ++++++++ + sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/rpi-dac.c | 97 +++++++++++++++++++++++++++++++++++++++++ + sound/soc/codecs/Kconfig | 4 ++ + sound/soc/codecs/Makefile | 2 + + sound/soc/codecs/pcm1794a.c | 62 ++++++++++++++++++++++++++ + 7 files changed, 193 insertions(+) + create mode 100644 sound/soc/bcm/rpi-dac.c + create mode 100644 sound/soc/codecs/pcm1794a.c + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -652,6 +652,20 @@ static struct platform_device snd_pcm510 + }; + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) ++static struct platform_device snd_rpi_dac_device = { ++ .name = "snd-rpi-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct platform_device snd_pcm1794a_codec_device = { ++ .name = "pcm1794a-codec", ++ .id = -1, ++ .num_resources = 0, ++}; ++#endif ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -825,6 +839,11 @@ void __init bcm2708_init(void) + bcm_register_device_dt(&snd_pcm5102a_codec_device); + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) ++ bcm_register_device_dt(&snd_rpi_dac_device); ++ bcm_register_device_dt(&snd_pcm1794a_codec_device); ++#endif ++ + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -25,3 +25,10 @@ config SND_BCM2708_SOC_HIFIBERRY_DAC + select SND_SOC_PCM5102A + help + Say Y or M if you want to add support for HifiBerry DAC. ++ ++config SND_BCM2708_SOC_RPI_DAC ++ tristate "Support for RPi-DAC" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_PCM1794A ++ help ++ Say Y or M if you want to add support for RPi-DAC. +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -10,5 +10,7 @@ obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd + + # BCM2708 Machine Support + snd-soc-hifiberry-dac-objs := hifiberry_dac.o ++snd-soc-rpi-dac-objs := rpi-dac.o + + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o +--- /dev/null ++++ b/sound/soc/bcm/rpi-dac.c +@@ -0,0 +1,97 @@ ++/* ++ * ASoC Driver for RPi-DAC. ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static int snd_rpi_rpi_dac_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ return 0; ++} ++ ++static int snd_rpi_rpi_dac_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_rpi_dac_ops = { ++ .hw_params = snd_rpi_rpi_dac_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = { ++{ ++ .name = "RPi-DAC", ++ .stream_name = "RPi-DAC HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm1794a-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm1794a-codec", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_rpi_dac_ops, ++ .init = snd_rpi_rpi_dac_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_rpi_dac = { ++ .name = "snd_rpi_rpi_dac", ++ .dai_link = snd_rpi_rpi_dac_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_rpi_dac_dai), ++}; ++ ++static int snd_rpi_rpi_dac_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_rpi_dac.dev = &pdev->dev; ++ ret = snd_soc_register_card(&snd_rpi_rpi_dac); ++ if (ret) ++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_rpi_dac_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_rpi_dac); ++} ++ ++static struct platform_driver snd_rpi_rpi_dac_driver = { ++ .driver = { ++ .name = "snd-rpi-dac", ++ .owner = THIS_MODULE, ++ }, ++ .probe = snd_rpi_rpi_dac_probe, ++ .remove = snd_rpi_rpi_dac_remove, ++}; ++ ++module_platform_driver(snd_rpi_rpi_dac_driver); ++ ++MODULE_AUTHOR("Florian Meier "); ++MODULE_DESCRIPTION("ASoC Driver for RPi-DAC"); ++MODULE_LICENSE("GPL v2"); +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -84,6 +84,7 @@ config SND_SOC_ALL_CODECS + select SND_SOC_PCM512x_SPI if SPI_MASTER + select SND_SOC_RT286 if I2C + select SND_SOC_PCM5102A if I2C ++ select SND_SOC_PCM1794A if I2C + select SND_SOC_RT5631 if I2C + select SND_SOC_RT5640 if I2C + select SND_SOC_RT5645 if I2C +@@ -512,6 +513,9 @@ config SND_SOC_RT286 + tristate + depends on I2C + ++config SND_SOC_PCM1794A ++ tristate ++ + config SND_SOC_PCM5102A + tristate + +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -78,6 +78,7 @@ snd-soc-pcm512x-i2c-objs := pcm512x-i2c. + snd-soc-pcm512x-spi-objs := pcm512x-spi.o + snd-soc-rl6231-objs := rl6231.o + snd-soc-rt286-objs := rt286.o ++snd-soc-pcm1794a-objs := pcm1794a.o + snd-soc-pcm5102a-objs := pcm5102a.o + snd-soc-rt5631-objs := rt5631.o + snd-soc-rt5640-objs := rt5640.o +@@ -264,6 +265,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd + obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o + obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o + obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o ++obj-$(CONFIG_SND_SOC_PCM1794A) += snd-soc-pcm1794a.o + obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o + obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o + obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o +--- /dev/null ++++ b/sound/soc/codecs/pcm1794a.c +@@ -0,0 +1,62 @@ ++/* ++ * Driver for the PCM1794A codec ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++ ++#include ++#include ++#include ++ ++#include ++ ++static struct snd_soc_dai_driver pcm1794a_dai = { ++ .name = "pcm1794a-hifi", ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE ++ }, ++}; ++ ++static struct snd_soc_codec_driver soc_codec_dev_pcm1794a; ++ ++static int pcm1794a_probe(struct platform_device *pdev) ++{ ++ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm1794a, ++ &pcm1794a_dai, 1); ++} ++ ++static int pcm1794a_remove(struct platform_device *pdev) ++{ ++ snd_soc_unregister_codec(&pdev->dev); ++ return 0; ++} ++ ++static struct platform_driver pcm1794a_codec_driver = { ++ .probe = pcm1794a_probe, ++ .remove = pcm1794a_remove, ++ .driver = { ++ .name = "pcm1794a-codec", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(pcm1794a_codec_driver); ++ ++MODULE_DESCRIPTION("ASoC PCM1794A codec driver"); ++MODULE_AUTHOR("Florian Meier "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0040-ASoC-wm8804-Implement-MCLK-configuration-options-add.patch b/target/linux/brcm2708/patches-4.1/0040-ASoC-wm8804-Implement-MCLK-configuration-options-add.patch new file mode 100644 index 0000000..70640a5 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0040-ASoC-wm8804-Implement-MCLK-configuration-options-add.patch @@ -0,0 +1,40 @@ +From 1000a38e381ea718d8daa07edcd371da44b0b855 Mon Sep 17 00:00:00 2001 +From: Daniel Matuschek +Date: Wed, 15 Jan 2014 21:41:23 +0100 +Subject: [PATCH 040/203] ASoC: wm8804: Implement MCLK configuration options, + add 32bit support WM8804 can run with PLL frequencies of 256xfs and 128xfs + for most sample rates. At 192kHz only 128xfs is supported. The existing + driver selects 128xfs automatically for some lower samples rates. By using an + additional mclk_div divider, it is now possible to control the behaviour. + This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It + should allow lower jitter and better signal quality. The behavior has to be + controlled by the sound card driver, because some sample frequency share the + same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only + difference is the MCLK divider. + +This also added support for 32bit data. + +Signed-off-by: Daniel Matuschek +--- + sound/soc/codecs/wm8804.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/sound/soc/codecs/wm8804.c ++++ b/sound/soc/codecs/wm8804.c +@@ -304,6 +304,7 @@ static int wm8804_hw_params(struct snd_p + blen = 0x1; + break; + case 24: ++ case 32: + blen = 0x2; + break; + default: +@@ -515,7 +516,7 @@ static const struct snd_soc_dai_ops wm88 + }; + + #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ +- SNDRV_PCM_FMTBIT_S24_LE) ++ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) + + #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ diff --git a/target/linux/brcm2708/patches-4.1/0041-ASoC-BCM-Add-support-for-HiFiBerry-Digi.-Driver-is-b.patch b/target/linux/brcm2708/patches-4.1/0041-ASoC-BCM-Add-support-for-HiFiBerry-Digi.-Driver-is-b.patch new file mode 100644 index 0000000..aff58e0 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0041-ASoC-BCM-Add-support-for-HiFiBerry-Digi.-Driver-is-b.patch @@ -0,0 +1,260 @@ +From dcb8a2f0beafb6bdf057ac2cf51efc9eb12afce5 Mon Sep 17 00:00:00 2001 +From: Daniel Matuschek +Date: Wed, 15 Jan 2014 21:42:08 +0100 +Subject: [PATCH 041/203] ASoC: BCM:Add support for HiFiBerry Digi. Driver is + based on the patched WM8804 driver. + +Signed-off-by: Daniel Matuschek + +Add a parameter to turn off SPDIF output if no audio is playing + +This patch adds the paramater auto_shutdown_output to the kernel module. +Default behaviour of the module is the same, but when auto_shutdown_output +is set to 1, the SPDIF oputput will shutdown if no stream is playing. + +bugfix for 32kHz sample rate, was missing + +HiFiBerry Digi: set SPDIF status bits for sample rate + +The HiFiBerry Digi driver did not signal the sample rate in the SPDIF status bits. +While this is optional, some DACs and receivers do not accept this signal. This patch +adds the sample rate bits in the SPDIF status block. +--- + sound/soc/bcm/Kconfig | 7 ++ + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/hifiberry_digi.c | 201 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 210 insertions(+) + create mode 100644 sound/soc/bcm/hifiberry_digi.c + +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -26,6 +26,13 @@ config SND_BCM2708_SOC_HIFIBERRY_DAC + help + Say Y or M if you want to add support for HifiBerry DAC. + ++config SND_BCM2708_SOC_HIFIBERRY_DIGI ++ tristate "Support for HifiBerry Digi" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_WM8804 ++ help ++ Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board. ++ + config SND_BCM2708_SOC_RPI_DAC + tristate "Support for RPi-DAC" + depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -10,7 +10,9 @@ obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd + + # BCM2708 Machine Support + snd-soc-hifiberry-dac-objs := hifiberry_dac.o ++snd-soc-hifiberry-digi-objs := hifiberry_digi.o + snd-soc-rpi-dac-objs := rpi-dac.o + + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o + obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o +--- /dev/null ++++ b/sound/soc/bcm/hifiberry_digi.c +@@ -0,0 +1,201 @@ ++/* ++ * ASoC Driver for HifiBerry Digi ++ * ++ * Author: Daniel Matuschek ++ * based on the HifiBerry DAC driver by Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/wm8804.h" ++ ++static short int auto_shutdown_output = 0; ++module_param(auto_shutdown_output, short, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); ++MODULE_PARM_DESC(auto_shutdown_output, "Shutdown SP/DIF output if playback is stopped"); ++ ++ ++static int samplerate=44100; ++ ++static int snd_rpi_hifiberry_digi_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ struct snd_soc_codec *codec = rtd->codec; ++ ++ /* enable TX output */ ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0); ++ ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_digi_startup(struct snd_pcm_substream *substream) { ++ /* turn on digital output */ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00); ++ return 0; ++} ++ ++static void snd_rpi_hifiberry_digi_shutdown(struct snd_pcm_substream *substream) { ++ /* turn off output */ ++ if (auto_shutdown_output) { ++ /* turn off output */ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c); ++ } ++} ++ ++ ++static int snd_rpi_hifiberry_digi_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *codec_dai = rtd->codec_dai; ++ struct snd_soc_codec *codec = rtd->codec; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ int sysclk = 27000000; /* This is fixed on this board */ ++ ++ long mclk_freq=0; ++ int mclk_div=1; ++ int sampling_freq=1; ++ ++ int ret; ++ ++ samplerate = params_rate(params); ++ ++ if (samplerate<=96000) { ++ mclk_freq=samplerate*256; ++ mclk_div=WM8804_MCLKDIV_256FS; ++ } else { ++ mclk_freq=samplerate*128; ++ mclk_div=WM8804_MCLKDIV_128FS; ++ } ++ ++ switch (samplerate) { ++ case 32000: ++ sampling_freq=0x03; ++ break; ++ case 44100: ++ sampling_freq=0x00; ++ break; ++ case 48000: ++ sampling_freq=0x02; ++ break; ++ case 88200: ++ sampling_freq=0x08; ++ break; ++ case 96000: ++ sampling_freq=0x0a; ++ break; ++ case 176400: ++ sampling_freq=0x0c; ++ break; ++ case 192000: ++ sampling_freq=0x0e; ++ break; ++ default: ++ dev_err(codec->dev, ++ "Failed to set WM8804 SYSCLK, unsupported samplerate %d\n", ++ samplerate); ++ } ++ ++ snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div); ++ snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq); ++ ++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL, ++ sysclk, SND_SOC_CLOCK_OUT); ++ if (ret < 0) { ++ dev_err(codec->dev, ++ "Failed to set WM8804 SYSCLK: %d\n", ret); ++ return ret; ++ } ++ ++ /* Enable TX output */ ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0); ++ ++ /* Power on */ ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0); ++ ++ /* set sampling frequency status bits */ ++ snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq); ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai,64); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_hifiberry_digi_ops = { ++ .hw_params = snd_rpi_hifiberry_digi_hw_params, ++ .startup = snd_rpi_hifiberry_digi_startup, ++ .shutdown = snd_rpi_hifiberry_digi_shutdown, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_hifiberry_digi_dai[] = { ++{ ++ .name = "HifiBerry Digi", ++ .stream_name = "HifiBerry Digi HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "wm8804-spdif", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "wm8804.1-003b", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM, ++ .ops = &snd_rpi_hifiberry_digi_ops, ++ .init = snd_rpi_hifiberry_digi_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_hifiberry_digi = { ++ .name = "snd_rpi_hifiberry_digi", ++ .dai_link = snd_rpi_hifiberry_digi_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_digi_dai), ++}; ++ ++static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_hifiberry_digi.dev = &pdev->dev; ++ ret = snd_soc_register_card(&snd_rpi_hifiberry_digi); ++ if (ret) ++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_hifiberry_digi); ++} ++ ++static struct platform_driver snd_rpi_hifiberry_digi_driver = { ++ .driver = { ++ .name = "snd-hifiberry-digi", ++ .owner = THIS_MODULE, ++ }, ++ .probe = snd_rpi_hifiberry_digi_probe, ++ .remove = snd_rpi_hifiberry_digi_remove, ++}; ++ ++module_platform_driver(snd_rpi_hifiberry_digi_driver); ++ ++MODULE_AUTHOR("Daniel Matuschek "); ++MODULE_DESCRIPTION("ASoC Driver for HifiBerry Digi"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0042-BCM2708-Added-support-for-HiFiBerry-Digi-board-Board.patch b/target/linux/brcm2708/patches-4.1/0042-BCM2708-Added-support-for-HiFiBerry-Digi-board-Board.patch new file mode 100644 index 0000000..25b236d --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0042-BCM2708-Added-support-for-HiFiBerry-Digi-board-Board.patch @@ -0,0 +1,47 @@ +From b6472b32e6f5a3d38a90351b4ccc82f89a5d1167 Mon Sep 17 00:00:00 2001 +From: Daniel Matuschek +Date: Thu, 16 Jan 2014 07:26:08 +0100 +Subject: [PATCH 042/203] BCM2708: Added support for HiFiBerry Digi board Board + initalization by I2C + +Signed-off-by: Daniel Matuschek +--- + arch/arm/mach-bcm2708/bcm2708.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -652,6 +652,21 @@ static struct platform_device snd_pcm510 + }; + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) ++static struct platform_device snd_hifiberry_digi_device = { ++ .name = "snd-hifiberry-digi", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("wm8804", 0x3b) ++ }, ++}; ++ ++#endif ++ + #if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) + static struct platform_device snd_rpi_dac_device = { + .name = "snd-rpi-dac", +@@ -839,6 +854,11 @@ void __init bcm2708_init(void) + bcm_register_device_dt(&snd_pcm5102a_codec_device); + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_digi_device); ++ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); ++#endif ++ + #if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) + bcm_register_device_dt(&snd_rpi_dac_device); + bcm_register_device_dt(&snd_pcm1794a_codec_device); diff --git a/target/linux/brcm2708/patches-4.1/0043-ASoC-wm8804-Set-idle_bias_off-to-false-Idle-bias-has.patch b/target/linux/brcm2708/patches-4.1/0043-ASoC-wm8804-Set-idle_bias_off-to-false-Idle-bias-has.patch new file mode 100644 index 0000000..d57ca69 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0043-ASoC-wm8804-Set-idle_bias_off-to-false-Idle-bias-has.patch @@ -0,0 +1,22 @@ +From 59cdf99d9532afce061f452a14c565e1d4a54a50 Mon Sep 17 00:00:00 2001 +From: Daniel Matuschek +Date: Thu, 16 Jan 2014 07:36:35 +0100 +Subject: [PATCH 043/203] ASoC: wm8804: Set idle_bias_off to false Idle bias + has been change to remove warning on driver startup + +Signed-off-by: Daniel Matuschek +--- + sound/soc/codecs/wm8804.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/sound/soc/codecs/wm8804.c ++++ b/sound/soc/codecs/wm8804.c +@@ -544,7 +544,7 @@ static struct snd_soc_dai_driver wm8804_ + }; + + static const struct snd_soc_codec_driver soc_codec_dev_wm8804 = { +- .idle_bias_off = true, ++ .idle_bias_off = false, + + .dapm_widgets = wm8804_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(wm8804_dapm_widgets), diff --git a/target/linux/brcm2708/patches-4.1/0044-Add-IQaudIO-Sound-Card-support-for-Raspberry-Pi.patch b/target/linux/brcm2708/patches-4.1/0044-Add-IQaudIO-Sound-Card-support-for-Raspberry-Pi.patch new file mode 100644 index 0000000..dc11dc9 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0044-Add-IQaudIO-Sound-Card-support-for-Raspberry-Pi.patch @@ -0,0 +1,201 @@ +From fc8ea110c58a5bf56acf6465e6b8e170a0035686 Mon Sep 17 00:00:00 2001 +From: Gordon Garrity +Date: Sat, 8 Mar 2014 16:56:57 +0000 +Subject: [PATCH 044/203] Add IQaudIO Sound Card support for Raspberry Pi + +Set a limit of 0dB on Digital Volume Control + +The main volume control in the PCM512x DAC has a range up to ++24dB. This is dangerously loud and can potentially cause massive +clipping in the output stages. Therefore this sets a sensible +limit of 0dB for this control. +--- + arch/arm/mach-bcm2708/bcm2708.c | 21 ++++++++ + sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/iqaudio-dac.c | 117 ++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 147 insertions(+) + create mode 100644 sound/soc/bcm/iqaudio-dac.c + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -681,6 +681,22 @@ static struct platform_device snd_pcm179 + }; + #endif + ++ ++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) ++static struct platform_device snd_rpi_iqaudio_dac_device = { ++ .name = "snd-rpi-iqaudio-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++// Use the actual device name rather than generic driver name ++static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("pcm5122", 0x4c) ++ }, ++}; ++#endif ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -864,6 +880,11 @@ void __init bcm2708_init(void) + bcm_register_device_dt(&snd_pcm1794a_codec_device); + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) ++ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device); ++ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices)); ++#endif ++ + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -39,3 +39,10 @@ config SND_BCM2708_SOC_RPI_DAC + select SND_SOC_PCM1794A + help + Say Y or M if you want to add support for RPi-DAC. ++ ++config SND_BCM2708_SOC_IQAUDIO_DAC ++ tristate "Support for IQaudIO-DAC" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_PCM512x_I2C ++ help ++ Say Y or M if you want to add support for IQaudIO-DAC. +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -12,7 +12,9 @@ obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd + snd-soc-hifiberry-dac-objs := hifiberry_dac.o + snd-soc-hifiberry-digi-objs := hifiberry_digi.o + snd-soc-rpi-dac-objs := rpi-dac.o ++snd-soc-iqaudio-dac-objs := iqaudio-dac.o + + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o + obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o +--- /dev/null ++++ b/sound/soc/bcm/iqaudio-dac.c +@@ -0,0 +1,117 @@ ++/* ++ * ASoC Driver for IQaudIO DAC ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static int snd_rpi_iqaudio_dac_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ int ret; ++ struct snd_soc_card *card = rtd->card; ++ struct snd_soc_codec *codec = rtd->codec; ++ ++ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); ++ if (ret < 0) ++ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); ++ ++ return 0; ++} ++ ++static int snd_rpi_iqaudio_dac_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++// NOT USED struct snd_soc_dai *codec_dai = rtd->codec_dai; ++// NOT USED struct snd_soc_codec *codec = rtd->codec; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ unsigned int sample_bits = ++ snd_pcm_format_physical_width(params_format(params)); ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_iqaudio_dac_ops = { ++ .hw_params = snd_rpi_iqaudio_dac_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = { ++{ ++ .name = "IQaudIO DAC", ++ .stream_name = "IQaudIO DAC HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm512x-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm512x.1-004c", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_iqaudio_dac_ops, ++ .init = snd_rpi_iqaudio_dac_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_iqaudio_dac = { ++ .name = "IQaudIODAC", ++ .dai_link = snd_rpi_iqaudio_dac_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai), ++}; ++ ++static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_iqaudio_dac.dev = &pdev->dev; ++ ret = snd_soc_register_card(&snd_rpi_iqaudio_dac); ++ if (ret) ++ dev_err(&pdev->dev, ++ "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_iqaudio_dac_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_iqaudio_dac); ++} ++ ++static const struct of_device_id iqaudio_of_match[] = { ++ { .compatible = "iqaudio,iqaudio-dac", }, ++ {}, ++}; ++ ++static struct platform_driver snd_rpi_iqaudio_dac_driver = { ++ .driver = { ++ .name = "snd-rpi-iqaudio-dac", ++ .owner = THIS_MODULE, ++ .of_match_table = iqaudio_of_match, ++ }, ++ .probe = snd_rpi_iqaudio_dac_probe, ++ .remove = snd_rpi_iqaudio_dac_remove, ++}; ++ ++module_platform_driver(snd_rpi_iqaudio_dac_driver); ++ ++MODULE_AUTHOR("Florian Meier "); ++MODULE_DESCRIPTION("ASoC Driver for IQAudio DAC"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0045-vmstat-Workaround-for-issue-where-dirty-page-count-g.patch b/target/linux/brcm2708/patches-4.1/0045-vmstat-Workaround-for-issue-where-dirty-page-count-g.patch new file mode 100644 index 0000000..764e277 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0045-vmstat-Workaround-for-issue-where-dirty-page-count-g.patch @@ -0,0 +1,27 @@ +From b1ef48d91499449783ae92a90d5234e5fb6c1692 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 18 Jun 2014 13:42:01 +0100 +Subject: [PATCH 045/203] vmstat: Workaround for issue where dirty page count + goes negative + +See: +https://github.com/raspberrypi/linux/issues/617 +http://www.spinics.net/lists/linux-mm/msg72236.html +--- + include/linux/vmstat.h | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/include/linux/vmstat.h ++++ b/include/linux/vmstat.h +@@ -241,7 +241,11 @@ static inline void __inc_zone_state(stru + static inline void __dec_zone_state(struct zone *zone, enum zone_stat_item item) + { + atomic_long_dec(&zone->vm_stat[item]); ++ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&zone->vm_stat[item]) < 0)) ++ atomic_long_set(&zone->vm_stat[item], 0); + atomic_long_dec(&vm_stat[item]); ++ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&vm_stat[item]) < 0)) ++ atomic_long_set(&vm_stat[item], 0); + } + + static inline void __inc_zone_page_state(struct page *page, diff --git a/target/linux/brcm2708/patches-4.1/0046-hid-Reduce-default-mouse-polling-interval-to-60Hz.patch b/target/linux/brcm2708/patches-4.1/0046-hid-Reduce-default-mouse-polling-interval-to-60Hz.patch new file mode 100644 index 0000000..5e086d1 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0046-hid-Reduce-default-mouse-polling-interval-to-60Hz.patch @@ -0,0 +1,36 @@ +From d2bb9e17cccd1b6d986013538259b90dc199aefb Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Mon, 14 Jul 2014 22:02:09 +0100 +Subject: [PATCH 046/203] hid: Reduce default mouse polling interval to 60Hz + +Reduces overhead when using X +--- + drivers/hid/usbhid/hid-core.c | 10 +++++++--- + 1 file changed, 7 insertions(+), 3 deletions(-) + +--- a/drivers/hid/usbhid/hid-core.c ++++ b/drivers/hid/usbhid/hid-core.c +@@ -49,7 +49,7 @@ + * Module parameters. + */ + +-static unsigned int hid_mousepoll_interval; ++static unsigned int hid_mousepoll_interval = ~0; + module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644); + MODULE_PARM_DESC(mousepoll, "Polling interval of mice"); + +@@ -1090,8 +1090,12 @@ static int usbhid_start(struct hid_devic + } + + /* Change the polling interval of mice. */ +- if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0) +- interval = hid_mousepoll_interval; ++ if (hid->collection->usage == HID_GD_MOUSE) { ++ if (hid_mousepoll_interval == ~0 && interval < 16) ++ interval = 16; ++ else if (hid_mousepoll_interval != ~0 && hid_mousepoll_interval != 0) ++ interval = hid_mousepoll_interval; ++ } + + ret = -ENOMEM; + if (usb_endpoint_dir_in(endpoint)) { diff --git a/target/linux/brcm2708/patches-4.1/0047-Added-support-for-HiFiBerry-DAC.patch b/target/linux/brcm2708/patches-4.1/0047-Added-support-for-HiFiBerry-DAC.patch new file mode 100644 index 0000000..42c7e39 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0047-Added-support-for-HiFiBerry-DAC.patch @@ -0,0 +1,204 @@ +From 14fd2e85f4a92ef464a7abae5e19b3dd682f5a89 Mon Sep 17 00:00:00 2001 +From: Daniel Matuschek +Date: Mon, 4 Aug 2014 10:06:56 +0200 +Subject: [PATCH 047/203] Added support for HiFiBerry DAC+ + +The driver is based on the HiFiBerry DAC driver. However HiFiBerry DAC+ uses +a different codec chip (PCM5122), therefore a new driver is necessary. +--- + arch/arm/mach-bcm2708/bcm2708.c | 19 ++++++ + sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/hifiberry_dacplus.c | 119 ++++++++++++++++++++++++++++++++++++++ + 4 files changed, 147 insertions(+) + create mode 100644 sound/soc/bcm/hifiberry_dacplus.c + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -652,6 +652,20 @@ static struct platform_device snd_pcm510 + }; + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) ++static struct platform_device snd_rpi_hifiberry_dacplus_device = { ++ .name = "snd-rpi-hifiberry-dacplus", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("pcm5122", 0x4d) ++ }, ++}; ++#endif ++ + #if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) + static struct platform_device snd_hifiberry_digi_device = { + .name = "snd-hifiberry-digi", +@@ -870,6 +884,11 @@ void __init bcm2708_init(void) + bcm_register_device_dt(&snd_pcm5102a_codec_device); + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) ++ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device); ++ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices)); ++#endif ++ + #if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) + bcm_register_device_dt(&snd_hifiberry_digi_device); + i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -26,6 +26,13 @@ config SND_BCM2708_SOC_HIFIBERRY_DAC + help + Say Y or M if you want to add support for HifiBerry DAC. + ++config SND_BCM2708_SOC_HIFIBERRY_DACPLUS ++ tristate "Support for HifiBerry DAC+" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_PCM512x ++ help ++ Say Y or M if you want to add support for HifiBerry DAC+. ++ + config SND_BCM2708_SOC_HIFIBERRY_DIGI + tristate "Support for HifiBerry Digi" + depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -10,11 +10,13 @@ obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd + + # BCM2708 Machine Support + snd-soc-hifiberry-dac-objs := hifiberry_dac.o ++snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o + snd-soc-hifiberry-digi-objs := hifiberry_digi.o + snd-soc-rpi-dac-objs := rpi-dac.o + snd-soc-iqaudio-dac-objs := iqaudio-dac.o + + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o + obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o + obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o +--- /dev/null ++++ b/sound/soc/bcm/hifiberry_dacplus.c +@@ -0,0 +1,119 @@ ++/* ++ * ASoC Driver for HiFiBerry DAC+ ++ * ++ * Author: Daniel Matuschek ++ * Copyright 2014 ++ * based on code by Florian Meier ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/pcm512x.h" ++ ++static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02); ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08); ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_dacplus_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64); ++} ++ ++static int snd_rpi_hifiberry_dacplus_startup(struct snd_pcm_substream *substream) { ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08); ++ return 0; ++} ++ ++static void snd_rpi_hifiberry_dacplus_shutdown(struct snd_pcm_substream *substream) { ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_hifiberry_dacplus_ops = { ++ .hw_params = snd_rpi_hifiberry_dacplus_hw_params, ++ .startup = snd_rpi_hifiberry_dacplus_startup, ++ .shutdown = snd_rpi_hifiberry_dacplus_shutdown, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_hifiberry_dacplus_dai[] = { ++{ ++ .name = "HiFiBerry DAC+", ++ .stream_name = "HiFiBerry DAC+ HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm512x-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm512x.1-004d", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_hifiberry_dacplus_ops, ++ .init = snd_rpi_hifiberry_dacplus_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_hifiberry_dacplus = { ++ .name = "snd_rpi_hifiberry_dacplus", ++ .dai_link = snd_rpi_hifiberry_dacplus_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dacplus_dai), ++}; ++ ++static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_hifiberry_dacplus.dev = &pdev->dev; ++ ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); ++ if (ret) ++ dev_err(&pdev->dev, ++ "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus); ++} ++ ++static struct platform_driver snd_rpi_hifiberry_dacplus_driver = { ++ .driver = { ++ .name = "snd-rpi-hifiberry-dacplus", ++ .owner = THIS_MODULE, ++ }, ++ .probe = snd_rpi_hifiberry_dacplus_probe, ++ .remove = snd_rpi_hifiberry_dacplus_remove, ++}; ++ ++module_platform_driver(snd_rpi_hifiberry_dacplus_driver); ++ ++MODULE_AUTHOR("Daniel Matuschek "); ++MODULE_DESCRIPTION("ASoC Driver for HiFiBerry DAC+"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0048-Added-driver-for-HiFiBerry-Amp-amplifier-add-on-boar.patch b/target/linux/brcm2708/patches-4.1/0048-Added-driver-for-HiFiBerry-Amp-amplifier-add-on-boar.patch new file mode 100644 index 0000000..bc36813 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0048-Added-driver-for-HiFiBerry-Amp-amplifier-add-on-boar.patch @@ -0,0 +1,852 @@ +From d6f6a3e2752f14210dd13b6d3d19bddc13bd9f79 Mon Sep 17 00:00:00 2001 +From: Daniel Matuschek +Date: Mon, 4 Aug 2014 11:09:58 +0200 +Subject: [PATCH 048/203] Added driver for HiFiBerry Amp amplifier add-on board + +The driver contains a low-level hardware driver for the TAS5713 and the +drivers for the Raspberry Pi I2S subsystem. + +TAS5713: return error if initialisation fails + +Existing TAS5713 driver logs errors during initialisation, but does not return +an error code. Therefore even if initialisation fails, the driver will still be +loaded, but won't work. This patch fixes this. I2C communication error will now +reported correctly by a non-zero return code. + +HiFiBerry Amp: fix device-tree problems + +Some code to load the driver based on device-tree-overlays was missing. This is added by this patch. +--- + arch/arm/mach-bcm2708/bcm2708.c | 19 +++ + sound/soc/bcm/Kconfig | 7 + + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/hifiberry_amp.c | 127 ++++++++++++++ + sound/soc/codecs/Kconfig | 4 + + sound/soc/codecs/Makefile | 2 + + sound/soc/codecs/tas5713.c | 369 ++++++++++++++++++++++++++++++++++++++++ + sound/soc/codecs/tas5713.h | 210 +++++++++++++++++++++++ + 8 files changed, 740 insertions(+) + create mode 100644 sound/soc/bcm/hifiberry_amp.c + create mode 100644 sound/soc/codecs/tas5713.c + create mode 100644 sound/soc/codecs/tas5713.h + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -681,6 +681,20 @@ static struct i2c_board_info __initdata + + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) ++static struct platform_device snd_hifiberry_amp_device = { ++ .name = "snd-hifiberry-amp", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("tas5713", 0x1b) ++ }, ++}; ++#endif ++ + #if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) + static struct platform_device snd_rpi_dac_device = { + .name = "snd-rpi-dac", +@@ -894,6 +908,11 @@ void __init bcm2708_init(void) + i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); + #endif + ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_amp_device); ++ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices)); ++#endif ++ + #if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) + bcm_register_device_dt(&snd_rpi_dac_device); + bcm_register_device_dt(&snd_pcm1794a_codec_device); +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -40,6 +40,13 @@ config SND_BCM2708_SOC_HIFIBERRY_DIGI + help + Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board. + ++config SND_BCM2708_SOC_HIFIBERRY_AMP ++ tristate "Support for the HifiBerry Amp" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_TAS5713 ++ help ++ Say Y or M if you want to add support for the HifiBerry Amp amplifier board. ++ + config SND_BCM2708_SOC_RPI_DAC + tristate "Support for RPi-DAC" + depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -12,11 +12,13 @@ obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd + snd-soc-hifiberry-dac-objs := hifiberry_dac.o + snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o + snd-soc-hifiberry-digi-objs := hifiberry_digi.o ++snd-soc-hifiberry-amp-objs := hifiberry_amp.o + snd-soc-rpi-dac-objs := rpi-dac.o + snd-soc-iqaudio-dac-objs := iqaudio-dac.o + + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o + obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o + obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o +--- /dev/null ++++ b/sound/soc/bcm/hifiberry_amp.c +@@ -0,0 +1,127 @@ ++/* ++ * ASoC Driver for HifiBerry AMP ++ * ++ * Author: Sebastian Eickhoff ++ * Copyright 2014 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static int snd_rpi_hifiberry_amp_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ // ToDo: init of the dsp-registers. ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_amp_hw_params( struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params ) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64); ++} ++ ++static struct snd_soc_ops snd_rpi_hifiberry_amp_ops = { ++ .hw_params = snd_rpi_hifiberry_amp_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_hifiberry_amp_dai[] = { ++ { ++ .name = "HifiBerry AMP", ++ .stream_name = "HifiBerry AMP HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "tas5713-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "tas5713.1-001b", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_hifiberry_amp_ops, ++ .init = snd_rpi_hifiberry_amp_init, ++ }, ++}; ++ ++ ++static struct snd_soc_card snd_rpi_hifiberry_amp = { ++ .name = "snd_rpi_hifiberry_amp", ++ .dai_link = snd_rpi_hifiberry_amp_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_amp_dai), ++}; ++ ++static const struct of_device_id snd_rpi_hifiberry_amp_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-amp", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_amp_of_match); ++ ++ ++static int snd_rpi_hifiberry_amp_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_hifiberry_amp.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_amp_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_hifiberry_amp); ++ ++ if (ret != 0) { ++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); ++ } ++ ++ return ret; ++} ++ ++ ++static int snd_rpi_hifiberry_amp_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_hifiberry_amp); ++} ++ ++ ++static struct platform_driver snd_rpi_hifiberry_amp_driver = { ++ .driver = { ++ .name = "snd-hifiberry-amp", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_amp_of_match, ++ }, ++ .probe = snd_rpi_hifiberry_amp_probe, ++ .remove = snd_rpi_hifiberry_amp_remove, ++}; ++ ++ ++module_platform_driver(snd_rpi_hifiberry_amp_driver); ++ ++ ++MODULE_AUTHOR("Sebastian Eickhoff "); ++MODULE_DESCRIPTION("ASoC driver for HiFiBerry-AMP"); ++MODULE_LICENSE("GPL v2"); +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -109,6 +109,7 @@ config SND_SOC_ALL_CODECS + select SND_SOC_TFA9879 if I2C + select SND_SOC_TLV320AIC23_I2C if I2C + select SND_SOC_TLV320AIC23_SPI if SPI_MASTER ++ select SND_SOC_TAS5713 if I2C + select SND_SOC_TLV320AIC26 if SPI_MASTER + select SND_SOC_TLV320AIC31XX if I2C + select SND_SOC_TLV320AIC32X4 if I2C +@@ -623,6 +624,9 @@ config SND_SOC_TFA9879 + tristate "NXP Semiconductors TFA9879 amplifier" + depends on I2C + ++config SND_SOC_TAS5713 ++ tristate ++ + config SND_SOC_TLV320AIC23 + tristate + +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -109,6 +109,7 @@ snd-soc-sta529-objs := sta529.o + snd-soc-stac9766-objs := stac9766.o + snd-soc-tas5086-objs := tas5086.o + snd-soc-tfa9879-objs := tfa9879.o ++snd-soc-tas5713-objs := tas5713.o + snd-soc-tlv320aic23-objs := tlv320aic23.o + snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o + snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o +@@ -293,6 +294,7 @@ obj-$(CONFIG_SND_SOC_STAC9766) += snd-so + obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o + obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o + obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o ++obj-$(CONFIG_SND_SOC_TAS5713) += snd-soc-tas5713.o + obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o + obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o + obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI) += snd-soc-tlv320aic23-spi.o +--- /dev/null ++++ b/sound/soc/codecs/tas5713.c +@@ -0,0 +1,369 @@ ++/* ++ * ASoC Driver for TAS5713 ++ * ++ * Author: Sebastian Eickhoff ++ * Copyright 2014 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "tas5713.h" ++ ++ ++static struct i2c_client *i2c; ++ ++struct tas5713_priv { ++ struct regmap *regmap; ++ int mclk_div; ++ struct snd_soc_codec *codec; ++}; ++ ++static struct tas5713_priv *priv_data; ++ ++ ++ ++ ++/* ++ * _ _ ___ _ ___ _ _ ++ * /_\ | | / __| /_\ / __|___ _ _| |_ _ _ ___| |___ ++ * / _ \| |__\__ \/ _ \ | (__/ _ \ ' \ _| '_/ _ \ (_-< ++ * /_/ \_\____|___/_/ \_\ \___\___/_||_\__|_| \___/_/__/ ++ * ++ */ ++ ++static const DECLARE_TLV_DB_SCALE(tas5713_vol_tlv, -10000, 50, 1); ++ ++ ++static const struct snd_kcontrol_new tas5713_snd_controls[] = { ++ SOC_SINGLE_TLV ("Master" , TAS5713_VOL_MASTER, 0, 248, 1, tas5713_vol_tlv), ++ SOC_DOUBLE_R_TLV("Channels" , TAS5713_VOL_CH1, TAS5713_VOL_CH2, 0, 248, 1, tas5713_vol_tlv) ++}; ++ ++ ++ ++ ++/* ++ * __ __ _ _ ___ _ ++ * | \/ |__ _ __| |_ (_)_ _ ___ | \ _ _(_)_ _____ _ _ ++ * | |\/| / _` / _| ' \| | ' \/ -_) | |) | '_| \ V / -_) '_| ++ * |_| |_\__,_\__|_||_|_|_||_\___| |___/|_| |_|\_/\___|_| ++ * ++ */ ++ ++static int tas5713_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ u16 blen = 0x00; ++ ++ struct snd_soc_codec *codec; ++ codec = dai->codec; ++ priv_data->codec = dai->codec; ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ blen = 0x03; ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ blen = 0x1; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ blen = 0x04; ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ blen = 0x05; ++ break; ++ default: ++ dev_err(dai->dev, "Unsupported word length: %u\n", ++ params_format(params)); ++ return -EINVAL; ++ } ++ ++ // set word length ++ snd_soc_update_bits(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x7, blen); ++ ++ return 0; ++} ++ ++ ++static int tas5713_mute_stream(struct snd_soc_dai *dai, int mute, int stream) ++{ ++ unsigned int val = 0; ++ ++ struct tas5713_priv *tas5713; ++ struct snd_soc_codec *codec = dai->codec; ++ tas5713 = snd_soc_codec_get_drvdata(codec); ++ ++ if (mute) { ++ val = TAS5713_SOFT_MUTE_ALL; ++ } ++ ++ return regmap_write(tas5713->regmap, TAS5713_SOFT_MUTE, val); ++} ++ ++ ++static const struct snd_soc_dai_ops tas5713_dai_ops = { ++ .hw_params = tas5713_hw_params, ++ .mute_stream = tas5713_mute_stream, ++}; ++ ++ ++static struct snd_soc_dai_driver tas5713_dai = { ++ .name = "tas5713-hifi", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_48000, ++ .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE ), ++ }, ++ .ops = &tas5713_dai_ops, ++}; ++ ++ ++ ++ ++/* ++ * ___ _ ___ _ ++ * / __|___ __| |___ __ | \ _ _(_)_ _____ _ _ ++ * | (__/ _ \/ _` / -_) _| | |) | '_| \ V / -_) '_| ++ * \___\___/\__,_\___\__| |___/|_| |_|\_/\___|_| ++ * ++ */ ++ ++static int tas5713_remove(struct snd_soc_codec *codec) ++{ ++ struct tas5713_priv *tas5713; ++ ++ tas5713 = snd_soc_codec_get_drvdata(codec); ++ ++ return 0; ++} ++ ++ ++static int tas5713_probe(struct snd_soc_codec *codec) ++{ ++ struct tas5713_priv *tas5713; ++ int i, ret; ++ ++ i2c = container_of(codec->dev, struct i2c_client, dev); ++ ++ tas5713 = snd_soc_codec_get_drvdata(codec); ++ ++ // Reset error ++ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00); ++ if (ret < 0) return ret; ++ ++ // Trim oscillator ++ ret = snd_soc_write(codec, TAS5713_OSC_TRIM, 0x00); ++ if (ret < 0) return ret; ++ msleep(1000); ++ ++ // Reset error ++ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00); ++ if (ret < 0) return ret; ++ ++ // Clock mode: 44/48kHz, MCLK=64xfs ++ ret = snd_soc_write(codec, TAS5713_CLOCK_CTRL, 0x60); ++ if (ret < 0) return ret; ++ ++ // I2S 24bit ++ ret = snd_soc_write(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x05); ++ if (ret < 0) return ret; ++ ++ // Unmute ++ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00); ++ if (ret < 0) return ret; ++ ret = snd_soc_write(codec, TAS5713_SOFT_MUTE, 0x00); ++ if (ret < 0) return ret; ++ ++ // Set volume to 0db ++ ret = snd_soc_write(codec, TAS5713_VOL_MASTER, 0x00); ++ if (ret < 0) return ret; ++ ++ // Now start programming the default initialization sequence ++ for (i = 0; i < ARRAY_SIZE(tas5713_init_sequence); ++i) { ++ ret = i2c_master_send(i2c, ++ tas5713_init_sequence[i].data, ++ tas5713_init_sequence[i].size); ++ if (ret < 0) { ++ printk(KERN_INFO "TAS5713 CODEC PROBE: InitSeq returns: %d\n", ret); ++ } ++ } ++ ++ // Unmute ++ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00); ++ if (ret < 0) return ret; ++ ++ return 0; ++} ++ ++ ++static struct snd_soc_codec_driver soc_codec_dev_tas5713 = { ++ .probe = tas5713_probe, ++ .remove = tas5713_remove, ++ .controls = tas5713_snd_controls, ++ .num_controls = ARRAY_SIZE(tas5713_snd_controls), ++}; ++ ++ ++ ++ ++/* ++ * ___ ___ ___ ___ _ ++ * |_ _|_ ) __| | \ _ _(_)_ _____ _ _ ++ * | | / / (__ | |) | '_| \ V / -_) '_| ++ * |___/___\___| |___/|_| |_|\_/\___|_| ++ * ++ */ ++ ++static const struct reg_default tas5713_reg_defaults[] = { ++ { 0x07 ,0x80 }, // R7 - VOL_MASTER - -40dB ++ { 0x08 , 30 }, // R8 - VOL_CH1 - 0dB ++ { 0x09 , 30 }, // R9 - VOL_CH2 - 0dB ++ { 0x0A ,0x80 }, // R10 - VOL_HEADPHONE - -40dB ++}; ++ ++ ++static bool tas5713_reg_volatile(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case TAS5713_DEVICE_ID: ++ case TAS5713_ERROR_STATUS: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++ ++static const struct of_device_id tas5713_of_match[] = { ++ { .compatible = "ti,tas5713", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, tas5713_of_match); ++ ++ ++static struct regmap_config tas5713_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ ++ .max_register = TAS5713_MAX_REGISTER, ++ .volatile_reg = tas5713_reg_volatile, ++ ++ .cache_type = REGCACHE_RBTREE, ++ .reg_defaults = tas5713_reg_defaults, ++ .num_reg_defaults = ARRAY_SIZE(tas5713_reg_defaults), ++}; ++ ++ ++static int tas5713_i2c_probe(struct i2c_client *i2c, ++ const struct i2c_device_id *id) ++{ ++ int ret; ++ ++ priv_data = devm_kzalloc(&i2c->dev, sizeof *priv_data, GFP_KERNEL); ++ if (!priv_data) ++ return -ENOMEM; ++ ++ priv_data->regmap = devm_regmap_init_i2c(i2c, &tas5713_regmap_config); ++ if (IS_ERR(priv_data->regmap)) { ++ ret = PTR_ERR(priv_data->regmap); ++ return ret; ++ } ++ ++ i2c_set_clientdata(i2c, priv_data); ++ ++ ret = snd_soc_register_codec(&i2c->dev, ++ &soc_codec_dev_tas5713, &tas5713_dai, 1); ++ ++ return ret; ++} ++ ++ ++static int tas5713_i2c_remove(struct i2c_client *i2c) ++{ ++ snd_soc_unregister_codec(&i2c->dev); ++ i2c_set_clientdata(i2c, NULL); ++ ++ kfree(priv_data); ++ ++ return 0; ++} ++ ++ ++static const struct i2c_device_id tas5713_i2c_id[] = { ++ { "tas5713", 0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(i2c, tas5713_i2c_id); ++ ++ ++static struct i2c_driver tas5713_i2c_driver = { ++ .driver = { ++ .name = "tas5713", ++ .owner = THIS_MODULE, ++ .of_match_table = tas5713_of_match, ++ }, ++ .probe = tas5713_i2c_probe, ++ .remove = tas5713_i2c_remove, ++ .id_table = tas5713_i2c_id ++}; ++ ++ ++static int __init tas5713_modinit(void) ++{ ++ int ret = 0; ++ ++ ret = i2c_add_driver(&tas5713_i2c_driver); ++ if (ret) { ++ printk(KERN_ERR "Failed to register tas5713 I2C driver: %d\n", ++ ret); ++ } ++ ++ return ret; ++} ++module_init(tas5713_modinit); ++ ++ ++static void __exit tas5713_exit(void) ++{ ++ i2c_del_driver(&tas5713_i2c_driver); ++} ++module_exit(tas5713_exit); ++ ++ ++MODULE_AUTHOR("Sebastian Eickhoff "); ++MODULE_DESCRIPTION("ASoC driver for TAS5713"); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/sound/soc/codecs/tas5713.h +@@ -0,0 +1,210 @@ ++/* ++ * ASoC Driver for TAS5713 ++ * ++ * Author: Sebastian Eickhoff ++ * Copyright 2014 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#ifndef _TAS5713_H ++#define _TAS5713_H ++ ++ ++// TAS5713 I2C-bus register addresses ++ ++#define TAS5713_CLOCK_CTRL 0x00 ++#define TAS5713_DEVICE_ID 0x01 ++#define TAS5713_ERROR_STATUS 0x02 ++#define TAS5713_SYSTEM_CTRL1 0x03 ++#define TAS5713_SERIAL_DATA_INTERFACE 0x04 ++#define TAS5713_SYSTEM_CTRL2 0x05 ++#define TAS5713_SOFT_MUTE 0x06 ++#define TAS5713_VOL_MASTER 0x07 ++#define TAS5713_VOL_CH1 0x08 ++#define TAS5713_VOL_CH2 0x09 ++#define TAS5713_VOL_HEADPHONE 0x0A ++#define TAS5713_VOL_CONFIG 0x0E ++#define TAS5713_MODULATION_LIMIT 0x10 ++#define TAS5713_IC_DLY_CH1 0x11 ++#define TAS5713_IC_DLY_CH2 0x12 ++#define TAS5713_IC_DLY_CH3 0x13 ++#define TAS5713_IC_DLY_CH4 0x14 ++ ++#define TAS5713_START_STOP_PERIOD 0x1A ++#define TAS5713_OSC_TRIM 0x1B ++#define TAS5713_BKND_ERR 0x1C ++ ++#define TAS5713_INPUT_MUX 0x20 ++#define TAS5713_SRC_SELECT_CH4 0x21 ++#define TAS5713_PWM_MUX 0x25 ++ ++#define TAS5713_CH1_BQ0 0x29 ++#define TAS5713_CH1_BQ1 0x2A ++#define TAS5713_CH1_BQ2 0x2B ++#define TAS5713_CH1_BQ3 0x2C ++#define TAS5713_CH1_BQ4 0x2D ++#define TAS5713_CH1_BQ5 0x2E ++#define TAS5713_CH1_BQ6 0x2F ++#define TAS5713_CH1_BQ7 0x58 ++#define TAS5713_CH1_BQ8 0x59 ++ ++#define TAS5713_CH2_BQ0 0x30 ++#define TAS5713_CH2_BQ1 0x31 ++#define TAS5713_CH2_BQ2 0x32 ++#define TAS5713_CH2_BQ3 0x33 ++#define TAS5713_CH2_BQ4 0x34 ++#define TAS5713_CH2_BQ5 0x35 ++#define TAS5713_CH2_BQ6 0x36 ++#define TAS5713_CH2_BQ7 0x5C ++#define TAS5713_CH2_BQ8 0x5D ++ ++#define TAS5713_CH4_BQ0 0x5A ++#define TAS5713_CH4_BQ1 0x5B ++#define TAS5713_CH3_BQ0 0x5E ++#define TAS5713_CH3_BQ1 0x5F ++ ++#define TAS5713_DRC1_SOFTENING_FILTER_ALPHA_OMEGA 0x3B ++#define TAS5713_DRC1_ATTACK_RELEASE_RATE 0x3C ++#define TAS5713_DRC2_SOFTENING_FILTER_ALPHA_OMEGA 0x3E ++#define TAS5713_DRC2_ATTACK_RELEASE_RATE 0x3F ++#define TAS5713_DRC1_ATTACK_RELEASE_THRES 0x40 ++#define TAS5713_DRC2_ATTACK_RELEASE_THRES 0x43 ++#define TAS5713_DRC_CTRL 0x46 ++ ++#define TAS5713_BANK_SW_CTRL 0x50 ++#define TAS5713_CH1_OUTPUT_MIXER 0x51 ++#define TAS5713_CH2_OUTPUT_MIXER 0x52 ++#define TAS5713_CH1_INPUT_MIXER 0x53 ++#define TAS5713_CH2_INPUT_MIXER 0x54 ++#define TAS5713_OUTPUT_POST_SCALE 0x56 ++#define TAS5713_OUTPUT_PRESCALE 0x57 ++ ++#define TAS5713_IDF_POST_SCALE 0x62 ++ ++#define TAS5713_CH1_INLINE_MIXER 0x70 ++#define TAS5713_CH1_INLINE_DRC_EN_MIXER 0x71 ++#define TAS5713_CH1_R_CHANNEL_MIXER 0x72 ++#define TAS5713_CH1_L_CHANNEL_MIXER 0x73 ++#define TAS5713_CH2_INLINE_MIXER 0x74 ++#define TAS5713_CH2_INLINE_DRC_EN_MIXER 0x75 ++#define TAS5713_CH2_L_CHANNEL_MIXER 0x76 ++#define TAS5713_CH2_R_CHANNEL_MIXER 0x77 ++ ++#define TAS5713_UPDATE_DEV_ADDR_KEY 0xF8 ++#define TAS5713_UPDATE_DEV_ADDR_REG 0xF9 ++ ++#define TAS5713_REGISTER_COUNT 0x46 ++#define TAS5713_MAX_REGISTER 0xF9 ++ ++ ++// Bitmasks for registers ++#define TAS5713_SOFT_MUTE_ALL 0x07 ++ ++ ++ ++struct tas5713_init_command { ++ const int size; ++ const char *const data; ++}; ++ ++static const struct tas5713_init_command tas5713_init_sequence[] = { ++ ++ // Trim oscillator ++ { .size = 2, .data = "\x1B\x00" }, ++ // System control register 1 (0x03): block DC ++ { .size = 2, .data = "\x03\x80" }, ++ // Mute everything ++ { .size = 2, .data = "\x05\x40" }, ++ // Modulation limit register (0x10): 97.7% ++ { .size = 2, .data = "\x10\x02" }, ++ // Interchannel delay registers ++ // (0x11, 0x12, 0x13, and 0x14): BD mode ++ { .size = 2, .data = "\x11\xB8" }, ++ { .size = 2, .data = "\x12\x60" }, ++ { .size = 2, .data = "\x13\xA0" }, ++ { .size = 2, .data = "\x14\x48" }, ++ // PWM shutdown group register (0x19): no shutdown ++ { .size = 2, .data = "\x19\x00" }, ++ // Input multiplexer register (0x20): BD mode ++ { .size = 2, .data = "\x20\x00\x89\x77\x72" }, ++ // PWM output mux register (0x25) ++ // Channel 1 --> OUTA, channel 1 neg --> OUTB ++ // Channel 2 --> OUTC, channel 2 neg --> OUTD ++ { .size = 5, .data = "\x25\x01\x02\x13\x45" }, ++ // DRC control (0x46): DRC off ++ { .size = 5, .data = "\x46\x00\x00\x00\x00" }, ++ // BKND_ERR register (0x1C): 299ms reset period ++ { .size = 2, .data = "\x1C\x07" }, ++ // Mute channel 3 ++ { .size = 2, .data = "\x0A\xFF" }, ++ // Volume configuration register (0x0E): volume slew 512 steps ++ { .size = 2, .data = "\x0E\x90" }, ++ // Clock control register (0x00): 44/48kHz, MCLK=64xfs ++ { .size = 2, .data = "\x00\x60" }, ++ // Bank switch and eq control (0x50): no bank switching ++ { .size = 5, .data = "\x50\x00\x00\x00\x00" }, ++ // Volume registers (0x07, 0x08, 0x09, 0x0A) ++ { .size = 2, .data = "\x07\x20" }, ++ { .size = 2, .data = "\x08\x30" }, ++ { .size = 2, .data = "\x09\x30" }, ++ { .size = 2, .data = "\x0A\xFF" }, ++ // 0x72, 0x73, 0x76, 0x77 input mixer: ++ // no intermix between channels ++ { .size = 5, .data = "\x72\x00\x00\x00\x00" }, ++ { .size = 5, .data = "\x73\x00\x80\x00\x00" }, ++ { .size = 5, .data = "\x76\x00\x00\x00\x00" }, ++ { .size = 5, .data = "\x77\x00\x80\x00\x00" }, ++ // 0x70, 0x71, 0x74, 0x75 inline DRC mixer: ++ // no inline DRC inmix ++ { .size = 5, .data = "\x70\x00\x80\x00\x00" }, ++ { .size = 5, .data = "\x71\x00\x00\x00\x00" }, ++ { .size = 5, .data = "\x74\x00\x80\x00\x00" }, ++ { .size = 5, .data = "\x75\x00\x00\x00\x00" }, ++ // 0x56, 0x57 Output scale ++ { .size = 5, .data = "\x56\x00\x80\x00\x00" }, ++ { .size = 5, .data = "\x57\x00\x02\x00\x00" }, ++ // 0x3B, 0x3c ++ { .size = 9, .data = "\x3B\x00\x08\x00\x00\x00\x78\x00\x00" }, ++ { .size = 9, .data = "\x3C\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, ++ { .size = 9, .data = "\x3E\x00\x08\x00\x00\x00\x78\x00\x00" }, ++ { .size = 9, .data = "\x3F\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, ++ { .size = 9, .data = "\x40\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, ++ { .size = 9, .data = "\x43\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, ++ // 0x51, 0x52: output mixer ++ { .size = 9, .data = "\x51\x00\x80\x00\x00\x00\x00\x00\x00" }, ++ { .size = 9, .data = "\x52\x00\x80\x00\x00\x00\x00\x00\x00" }, ++ // PEQ defaults ++ { .size = 21, .data = "\x29\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x30\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x31\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x32\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x33\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x34\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x35\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x36\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x58\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x59\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++}; ++ ++ ++#endif /* _TAS5713_H */ diff --git a/target/linux/brcm2708/patches-4.1/0049-bcm2708-Allow-option-card-devices-to-be-configured-v.patch b/target/linux/brcm2708/patches-4.1/0049-bcm2708-Allow-option-card-devices-to-be-configured-v.patch new file mode 100644 index 0000000..9dcaa46 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0049-bcm2708-Allow-option-card-devices-to-be-configured-v.patch @@ -0,0 +1,25 @@ +From 9791bbe1abe1228c0726314e4e1b8baeff8233ce Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 13 Apr 2015 19:14:18 +0100 +Subject: [PATCH 049/203] bcm2708: Allow option card devices to be configured + via DT + +If the kernel is built with Device Tree support, and if a DT blob +is provided for the kernel at boot time, then the platform devices +for option cards are not created. This avoids both the need to +blacklist unwanted devices, and the need to update the board +support code with each new device. +--- + sound/soc/bcm/bcm2835-i2s.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/sound/soc/bcm/bcm2835-i2s.c ++++ b/sound/soc/bcm/bcm2835-i2s.c +@@ -861,6 +861,7 @@ static const struct of_device_id bcm2835 + { .compatible = "brcm,bcm2835-i2s", }, + {}, + }; ++MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match); + + static struct platform_driver bcm2835_i2s_driver = { + .probe = bcm2835_i2s_probe, diff --git a/target/linux/brcm2708/patches-4.1/0050-Adding-Device-Tree-support-for-some-RPi-audio-cards.patch b/target/linux/brcm2708/patches-4.1/0050-Adding-Device-Tree-support-for-some-RPi-audio-cards.patch new file mode 100644 index 0000000..c723e69 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0050-Adding-Device-Tree-support-for-some-RPi-audio-cards.patch @@ -0,0 +1,353 @@ +From a6bc94bfd95cb3351ebac3ccff75cd915a8d9e86 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Mon, 13 Apr 2015 18:45:39 +0100 +Subject: [PATCH 050/203] Adding Device Tree support for some RPi audio cards + +--- + arch/arm/mach-bcm2709/bcm2709.c | 143 ++++++++++++++++++++++++++++++++++++++ + sound/soc/bcm/hifiberry_dac.c | 22 ++++++ + sound/soc/bcm/hifiberry_dacplus.c | 22 ++++++ + sound/soc/bcm/hifiberry_digi.c | 22 ++++++ + sound/soc/bcm/iqaudio-dac.c | 16 +++++ + sound/soc/codecs/pcm5102a.c | 7 ++ + 6 files changed, 232 insertions(+) + +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -636,6 +636,115 @@ static struct platform_device bcm2835_th + .name = "bcm2835_thermal", + }; + ++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) ++static struct resource bcm2708_i2s_resources[] = { ++ { ++ .start = I2S_BASE, ++ .end = I2S_BASE + 0x20, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = PCM_CLOCK_BASE, ++ .end = PCM_CLOCK_BASE + 0x02, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct platform_device bcm2708_i2s_device = { ++ .name = "bcm2708-i2s", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources), ++ .resource = bcm2708_i2s_resources, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) ++static struct platform_device snd_hifiberry_dac_device = { ++ .name = "snd-hifiberry-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct platform_device snd_pcm5102a_codec_device = { ++ .name = "pcm5102a-codec", ++ .id = -1, ++ .num_resources = 0, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) ++static struct platform_device snd_rpi_hifiberry_dacplus_device = { ++ .name = "snd-rpi-hifiberry-dacplus", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("pcm5122", 0x4d) ++ }, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) ++static struct platform_device snd_hifiberry_digi_device = { ++ .name = "snd-hifiberry-digi", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("wm8804", 0x3b) ++ }, ++}; ++ ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) ++static struct platform_device snd_hifiberry_amp_device = { ++ .name = "snd-hifiberry-amp", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("tas5713", 0x1b) ++ }, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) ++static struct platform_device snd_rpi_dac_device = { ++ .name = "snd-rpi-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct platform_device snd_pcm1794a_codec_device = { ++ .name = "pcm1794a-codec", ++ .id = -1, ++ .num_resources = 0, ++}; ++#endif ++ ++ ++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) ++static struct platform_device snd_rpi_iqaudio_dac_device = { ++ .name = "snd-rpi-iqaudio-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++// Use the actual device name rather than generic driver name ++static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("pcm5122", 0x4c) ++ }, ++}; ++#endif ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -800,6 +909,40 @@ void __init bcm2709_init(void) + + bcm_register_device_dt(&bcm2835_thermal_device); + ++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) ++ bcm_register_device_dt(&bcm2708_i2s_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_dac_device); ++ bcm_register_device_dt(&snd_pcm5102a_codec_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) ++ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device); ++ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_digi_device); ++ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_amp_device); ++ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) ++ bcm_register_device_dt(&snd_rpi_dac_device); ++ bcm_register_device_dt(&snd_pcm1794a_codec_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) ++ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device); ++ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices)); ++#endif ++ + if (!use_dt) { + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; +--- a/sound/soc/bcm/hifiberry_dac.c ++++ b/sound/soc/bcm/hifiberry_dac.c +@@ -72,6 +72,21 @@ static int snd_rpi_hifiberry_dac_probe(s + int ret = 0; + + snd_rpi_hifiberry_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_dac); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); +@@ -84,10 +99,17 @@ static int snd_rpi_hifiberry_dac_remove( + return snd_soc_unregister_card(&snd_rpi_hifiberry_dac); + } + ++static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match); ++ + static struct platform_driver snd_rpi_hifiberry_dac_driver = { + .driver = { + .name = "snd-hifiberry-dac", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_dac_of_match, + }, + .probe = snd_rpi_hifiberry_dac_probe, + .remove = snd_rpi_hifiberry_dac_remove, +--- a/sound/soc/bcm/hifiberry_dacplus.c ++++ b/sound/soc/bcm/hifiberry_dacplus.c +@@ -90,6 +90,21 @@ static int snd_rpi_hifiberry_dacplus_pro + int ret = 0; + + snd_rpi_hifiberry_dacplus.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dacplus_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); + if (ret) + dev_err(&pdev->dev, +@@ -103,10 +118,17 @@ static int snd_rpi_hifiberry_dacplus_rem + return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus); + } + ++static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-dacplus", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match); ++ + static struct platform_driver snd_rpi_hifiberry_dacplus_driver = { + .driver = { + .name = "snd-rpi-hifiberry-dacplus", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_dacplus_of_match, + }, + .probe = snd_rpi_hifiberry_dacplus_probe, + .remove = snd_rpi_hifiberry_dacplus_remove, +--- a/sound/soc/bcm/hifiberry_digi.c ++++ b/sound/soc/bcm/hifiberry_digi.c +@@ -173,6 +173,21 @@ static int snd_rpi_hifiberry_digi_probe( + int ret = 0; + + snd_rpi_hifiberry_digi.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_hifiberry_digi); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); +@@ -185,10 +200,17 @@ static int snd_rpi_hifiberry_digi_remove + return snd_soc_unregister_card(&snd_rpi_hifiberry_digi); + } + ++static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-digi", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match); ++ + static struct platform_driver snd_rpi_hifiberry_digi_driver = { + .driver = { + .name = "snd-hifiberry-digi", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_digi_of_match, + }, + .probe = snd_rpi_hifiberry_digi_probe, + .remove = snd_rpi_hifiberry_digi_remove, +--- a/sound/soc/bcm/iqaudio-dac.c ++++ b/sound/soc/bcm/iqaudio-dac.c +@@ -82,6 +82,21 @@ static int snd_rpi_iqaudio_dac_probe(str + int ret = 0; + + snd_rpi_iqaudio_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_iqaudio_dac); + if (ret) + dev_err(&pdev->dev, +@@ -99,6 +114,7 @@ static const struct of_device_id iqaudio + { .compatible = "iqaudio,iqaudio-dac", }, + {}, + }; ++MODULE_DEVICE_TABLE(of, iqaudio_of_match); + + static struct platform_driver snd_rpi_iqaudio_dac_driver = { + .driver = { +--- a/sound/soc/codecs/pcm5102a.c ++++ b/sound/soc/codecs/pcm5102a.c +@@ -47,12 +47,19 @@ static int pcm5102a_remove(struct platfo + return 0; + } + ++static const struct of_device_id pcm5102a_of_match[] = { ++ { .compatible = "ti,pcm5102a", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pcm5102a_of_match); ++ + static struct platform_driver pcm5102a_codec_driver = { + .probe = pcm5102a_probe, + .remove = pcm5102a_remove, + .driver = { + .name = "pcm5102a-codec", + .owner = THIS_MODULE, ++ .of_match_table = pcm5102a_of_match, + }, + }; + diff --git a/target/linux/brcm2708/patches-4.1/0051-Added-support-to-reserve-enable-a-GPIO-pin-to-be-use.patch b/target/linux/brcm2708/patches-4.1/0051-Added-support-to-reserve-enable-a-GPIO-pin-to-be-use.patch new file mode 100644 index 0000000..b367e62 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0051-Added-support-to-reserve-enable-a-GPIO-pin-to-be-use.patch @@ -0,0 +1,134 @@ +From 4d818efc09ca08d42fabd91c10c75556b0ab9164 Mon Sep 17 00:00:00 2001 +From: Timo Kokkonen +Date: Wed, 29 Oct 2014 23:30:30 -0700 +Subject: [PATCH 051/203] Added support to reserve/enable a GPIO pin to be used + from pps-gpio module (LinuxPPS). Enable PPS modules in default config for + RPi. + +--- + arch/arm/mach-bcm2708/bcm2708.c | 27 +++++++++++++++++++++++++++ + arch/arm/mach-bcm2709/bcm2709.c | 27 +++++++++++++++++++++++++++ + 2 files changed, 54 insertions(+) + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -92,6 +93,7 @@ static unsigned reboot_part = 0; + static unsigned w1_gpio_pin = W1_GPIO; + static unsigned w1_gpio_pullup = W1_PULLUP; + static bool vc_i2c_override = false; ++static int pps_gpio_pin = -1; + + static unsigned use_dt = 0; + +@@ -325,6 +327,19 @@ static struct platform_device w1_device + }; + #endif + ++static struct pps_gpio_platform_data pps_gpio_info = { ++ .assert_falling_edge = false, ++ .capture_clear = false, ++ .gpio_pin = -1, ++ .gpio_label = "PPS", ++}; ++ ++static struct platform_device pps_gpio_device = { ++ .name = "pps-gpio", ++ .id = PLATFORM_DEVID_NONE, ++ .dev.platform_data = &pps_gpio_info, ++}; ++ + static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_fb_device = { +@@ -860,6 +875,16 @@ void __init bcm2708_init(void) + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); + #endif ++ ++#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE) ++ if (!use_dt && (pps_gpio_pin >= 0)) { ++ pr_info("bcm2708: GPIO %d setup as pps-gpio device\n", pps_gpio_pin); ++ pps_gpio_info.gpio_pin = pps_gpio_pin; ++ pps_gpio_device.id = pps_gpio_pin; ++ bcm_register_device(&pps_gpio_device); ++ } ++#endif ++ + #if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) + w1_gpio_pdata.pin = w1_gpio_pin; + w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup; +@@ -1116,3 +1141,5 @@ module_param(w1_gpio_pin, uint, 0644); + module_param(w1_gpio_pullup, uint, 0644); + module_param(vc_i2c_override, bool, 0644); + MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); ++module_param(pps_gpio_pin, int, 0644); ++MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS"); +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -94,6 +95,7 @@ static unsigned reboot_part = 0; + static unsigned w1_gpio_pin = W1_GPIO; + static unsigned w1_gpio_pullup = W1_PULLUP; + static bool vc_i2c_override = false; ++static int pps_gpio_pin = -1; + + static unsigned use_dt = 0; + +@@ -335,6 +337,19 @@ static struct platform_device w1_device + }; + #endif + ++static struct pps_gpio_platform_data pps_gpio_info = { ++ .assert_falling_edge = false, ++ .capture_clear = false, ++ .gpio_pin = -1, ++ .gpio_label = "PPS", ++}; ++ ++static struct platform_device pps_gpio_device = { ++ .name = "pps-gpio", ++ .id = PLATFORM_DEVID_NONE, ++ .dev.platform_data = &pps_gpio_info, ++}; ++ + static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_fb_device = { +@@ -880,6 +895,16 @@ void __init bcm2709_init(void) + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); + #endif ++ ++#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE) ++ if (!use_dt && (pps_gpio_pin >= 0)) { ++ pr_info("bcm2709: GPIO %d setup as pps-gpio device\n", pps_gpio_pin); ++ pps_gpio_info.gpio_pin = pps_gpio_pin; ++ pps_gpio_device.id = pps_gpio_pin; ++ bcm_register_device(&pps_gpio_device); ++ } ++#endif ++ + #if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) + w1_gpio_pdata.pin = w1_gpio_pin; + w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup; +@@ -1284,3 +1309,5 @@ module_param(w1_gpio_pin, uint, 0644); + module_param(w1_gpio_pullup, uint, 0644); + module_param(vc_i2c_override, bool, 0644); + MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); ++module_param(pps_gpio_pin, int, 0644); ++MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS"); diff --git a/target/linux/brcm2708/patches-4.1/0052-Update-ds1307-driver-for-device-tree-support.patch b/target/linux/brcm2708/patches-4.1/0052-Update-ds1307-driver-for-device-tree-support.patch new file mode 100644 index 0000000..e7524ba --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0052-Update-ds1307-driver-for-device-tree-support.patch @@ -0,0 +1,27 @@ +From b6d5a7c02f67e35ff3e56ecbb4ef24e65ffdc5bc Mon Sep 17 00:00:00 2001 +From: Ryan Coe +Date: Sat, 31 Jan 2015 18:25:49 -0700 +Subject: [PATCH 052/203] Update ds1307 driver for device-tree support + +Signed-off-by: Ryan Coe +--- + drivers/rtc/rtc-ds1307.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/rtc/rtc-ds1307.c ++++ b/drivers/rtc/rtc-ds1307.c +@@ -1242,6 +1242,14 @@ static int ds1307_remove(struct i2c_clie + return 0; + } + ++#ifdef CONFIG_OF ++static const struct of_device_id ds1307_of_match[] = { ++ { .compatible = "maxim,ds1307" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ds1307_of_match); ++#endif ++ + static struct i2c_driver ds1307_driver = { + .driver = { + .name = "rtc-ds1307", diff --git a/target/linux/brcm2708/patches-4.1/0053-BCM270x_DT-Add-pwr_led-and-the-required-input-trigge.patch b/target/linux/brcm2708/patches-4.1/0053-BCM270x_DT-Add-pwr_led-and-the-required-input-trigge.patch new file mode 100644 index 0000000..1a662a8 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0053-BCM270x_DT-Add-pwr_led-and-the-required-input-trigge.patch @@ -0,0 +1,106 @@ +From a4c686a6a8cc5938de37451714add5ea872f67c2 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 6 Feb 2015 13:50:57 +0000 +Subject: [PATCH 053/203] BCM270x_DT: Add pwr_led, and the required "input" + trigger + +The "input" trigger makes the associated GPIO an input. This is to support +the Raspberry Pi PWR LED, which is driven by external hardware in normal use. + +N.B. pwr_led is not available on Model A or B boards. +--- + drivers/leds/trigger/Kconfig | 7 ++++ + drivers/leds/trigger/Makefile | 1 + + drivers/leds/trigger/ledtrig-input.c | 65 ++++++++++++++++++++++++++++++++++++ + 3 files changed, 73 insertions(+) + create mode 100644 drivers/leds/trigger/ledtrig-input.c + +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -126,4 +126,11 @@ config LEDS_TRIGGER_USBDEV + This allows LEDs to be controlled by the presence/activity of + an USB device. If unsure, say N. + ++config LEDS_TRIGGER_INPUT ++ tristate "LED Input Trigger" ++ depends on LEDS_TRIGGERS ++ help ++ This allows the GPIOs assigned to be LEDs to be initialised to inputs. ++ If unsure, say Y. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/trigger/Makefile ++++ b/drivers/leds/trigger/Makefile +@@ -8,3 +8,4 @@ obj-$(CONFIG_LEDS_TRIGGER_CPU) += ledtr + obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o + obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT) += ledtrig-transient.o + obj-$(CONFIG_LEDS_TRIGGER_CAMERA) += ledtrig-camera.o ++obj-$(CONFIG_LEDS_TRIGGER_INPUT) += ledtrig-input.o +--- /dev/null ++++ b/drivers/leds/trigger/ledtrig-input.c +@@ -0,0 +1,65 @@ ++/* ++ * Set LED GPIO to Input "Trigger" ++ * ++ * Copyright 2015 Phil Elwell ++ * ++ * Based on Nick Forbes's ledtrig-default-on.c. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "../leds.h" ++ ++/* This is a hack to get at the private 'gpio' member */ ++ ++struct gpio_led_data { ++ struct led_classdev cdev; ++ unsigned gpio; ++}; ++ ++static void input_trig_activate(struct led_classdev *led_cdev) ++{ ++ struct gpio_led_data *led_dat = ++ container_of(led_cdev, struct gpio_led_data, cdev); ++ if (gpio_is_valid(led_dat->gpio)) ++ gpio_direction_input(led_dat->gpio); ++} ++ ++static void input_trig_deactivate(struct led_classdev *led_cdev) ++{ ++ struct gpio_led_data *led_dat = ++ container_of(led_cdev, struct gpio_led_data, cdev); ++ if (gpio_is_valid(led_dat->gpio)) ++ gpio_direction_output(led_dat->gpio, 0); ++} ++ ++static struct led_trigger input_led_trigger = { ++ .name = "input", ++ .activate = input_trig_activate, ++ .deactivate = input_trig_deactivate, ++}; ++ ++static int __init input_trig_init(void) ++{ ++ return led_trigger_register(&input_led_trigger); ++} ++ ++static void __exit input_trig_exit(void) ++{ ++ led_trigger_unregister(&input_led_trigger); ++} ++ ++module_init(input_trig_init); ++module_exit(input_trig_exit); ++ ++MODULE_AUTHOR("Phil Elwell "); ++MODULE_DESCRIPTION("Set LED GPIO to Input \"trigger\""); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm2708/patches-4.1/0054-bcm2709-Simplify-and-strip-down-IRQ-handler.patch b/target/linux/brcm2708/patches-4.1/0054-bcm2709-Simplify-and-strip-down-IRQ-handler.patch new file mode 100644 index 0000000..58edd01 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0054-bcm2709-Simplify-and-strip-down-IRQ-handler.patch @@ -0,0 +1,222 @@ +From 4427da11c90fced3efd244e90d408d12bfdeb8c2 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Fri, 20 Jun 2014 17:19:27 +0100 +Subject: [PATCH 054/203] bcm2709: Simplify and strip down IRQ handler + +--- + arch/arm/include/asm/entry-macro-multi.S | 2 + + arch/arm/mach-bcm2709/include/mach/entry-macro.S | 173 +++++++++++------------ + 2 files changed, 87 insertions(+), 88 deletions(-) + +--- a/arch/arm/include/asm/entry-macro-multi.S ++++ b/arch/arm/include/asm/entry-macro-multi.S +@@ -1,5 +1,6 @@ + #include + ++#ifndef CONFIG_ARCH_BCM2709 + /* + * Interrupt handling. Preserves r7, r8, r9 + */ +@@ -28,6 +29,7 @@ + #endif + 9997: + .endm ++#endif + + .macro arch_irq_handler, symbol_name + .align 5 +--- a/arch/arm/mach-bcm2709/include/mach/entry-macro.S ++++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S +@@ -22,102 +22,99 @@ + #include + #include + +- .macro disable_fiq +- .endm ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm + +- .macro get_irqnr_preamble, base, tmp +- ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) +- .endm +- +- .macro arch_ret_to_user, tmp1, tmp2 +- .endm +- +- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +- /* get core number */ +- mrc p15, 0, \tmp, c0, c0, 5 +- ubfx \tmp, \tmp, #0, #2 +- +- /* get core's local interrupt controller */ +- ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source +- add \irqstat, \irqstat, \tmp, lsl #2 +- ldr \tmp, [\irqstat] +- /* ignore gpu interrupt */ +- bic \tmp, #0x100 +- /* ignore mailbox interrupts */ +- bics \tmp, #0xf0 +- beq 1005f +- +- @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) +- @ N.B. CLZ is an ARM5 instruction. +- mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) +- sub \irqstat, \tmp, #1 +- eor \irqstat, \irqstat, \tmp +- clz \tmp, \irqstat +- sub \irqnr, \tmp +- b 1020f +-1005: +- /* get core number */ +- mrc p15, 0, \tmp, c0, c0, 5 +- ubfx \tmp, \tmp, #0, #2 +- +- cmp \tmp, #1 +- beq 1020f +- cmp \tmp, #2 +- beq 1020f +- cmp \tmp, #3 +- beq 1020f +- +- /* get masked status */ +- ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] +- mov \irqnr, #(ARM_IRQ0_BASE + 31) +- and \tmp, \irqstat, #0x300 @ save bits 8 and 9 +- /* clear bits 8 and 9, and test */ +- bics \irqstat, \irqstat, #0x300 +- bne 1010f +- +- tst \tmp, #0x100 +- ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] +- movne \irqnr, #(ARM_IRQ1_BASE + 31) +- @ Mask out the interrupts also present in PEND0 - see SW-5809 +- bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) +- bicne \irqstat, #((1<<18) | (1<<19)) +- bne 1010f +- +- tst \tmp, #0x200 +- ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] +- movne \irqnr, #(ARM_IRQ2_BASE + 31) +- @ Mask out the interrupts also present in PEND0 - see SW-5809 +- bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) +- bicne \irqstat, #((1<<30)) +- beq 1020f ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ++ /* get core number */ ++ mrc p15, 0, \base, c0, c0, 5 ++ ubfx \base, \base, #0, #2 ++ ++ /* get core's local interrupt controller */ ++ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source ++ add \irqstat, \irqstat, \base, lsl #2 ++ ldr \tmp, [\irqstat] ++#ifdef CONFIG_SMP ++ /* test for mailbox0 (IPI) interrupt */ ++ tst \tmp, #0x10 ++ beq 1030f ++ ++ /* get core's mailbox interrupt control */ ++ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr ++ add \irqstat, \irqstat, \base, lsl #4 ++ ldr \tmp, [\irqstat] ++ clz \tmp, \tmp ++ rsb \irqnr, \tmp, #31 ++ mov \tmp, #1 ++ lsl \tmp, \irqnr ++ str \tmp, [\irqstat] @ clear interrupt source ++ dsb ++ mov r1, sp ++ adr lr, BSYM(1b) ++ b do_IPI ++#endif ++1030: ++ /* check gpu interrupt */ ++ tst \tmp, #0x100 ++ beq 1040f ++ ++ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) ++ /* get masked status */ ++ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] ++ mov \irqnr, #(ARM_IRQ0_BASE + 31) ++ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 ++ /* clear bits 8 and 9, and test */ ++ bics \irqstat, \irqstat, #0x300 ++ bne 1010f ++ ++ tst \tmp, #0x100 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ1_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) ++ bicne \irqstat, #((1<<18) | (1<<19)) ++ bne 1010f ++ ++ tst \tmp, #0x200 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ2_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) ++ bicne \irqstat, #((1<<30)) ++ beq 1020f + 1010: +- @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) +- @ N.B. CLZ is an ARM5 instruction. +- sub \tmp, \irqstat, #1 +- eor \irqstat, \irqstat, \tmp +- clz \tmp, \irqstat +- sub \irqnr, \tmp ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ sub \tmp, \irqstat, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++ b 1050f ++1040: ++ cmp \tmp, #0 ++ beq 1020f ++ ++ /* handle local (e.g. timer) interrupts */ ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) ++ sub \irqstat, \tmp, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++1050: ++ mov r1, sp ++ @ ++ @ routine called with r0 = irq number, r1 = struct pt_regs * ++ @ ++ adr lr, BSYM(1b) ++ b asm_do_IRQ + + 1020: @ EQ will be set if no irqs pending ++ .endm + +- .endm +- +- .macro test_for_ipi, irqnr, irqstat, base, tmp +- /* get core number */ +- mrc p15, 0, \tmp, c0, c0, 5 +- ubfx \tmp, \tmp, #0, #2 +- /* get core's mailbox interrupt control */ +- ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr +- add \irqstat, \irqstat, \tmp, lsl #4 +- ldr \tmp, [\irqstat] +- cmp \tmp, #0 +- beq 1030f +- clz \tmp, \tmp +- rsb \irqnr, \tmp, #31 +- mov \tmp, #1 +- lsl \tmp, \irqnr +- str \tmp, [\irqstat] @ clear interrupt source +- dsb +-1030: @ EQ will be set if no irqs pending +- .endm ++/* ++ * Interrupt handling. Preserves r7, r8, r9 ++ */ ++ .macro arch_irq_handler_default ++1: get_irqnr_and_base r0, r2, r6, lr ++ .endm diff --git a/target/linux/brcm2708/patches-4.1/0055-Fix-LED-input-trigger-implementation-for-3.19.patch b/target/linux/brcm2708/patches-4.1/0055-Fix-LED-input-trigger-implementation-for-3.19.patch new file mode 100644 index 0000000..0d15152 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0055-Fix-LED-input-trigger-implementation-for-3.19.patch @@ -0,0 +1,83 @@ +From 730ac9d3f596df543a2bd15b5b299da977966cc9 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 12 Feb 2015 11:17:53 +0000 +Subject: [PATCH 055/203] Fix LED "input" trigger implementation for 3.19 + +--- + drivers/leds/leds-gpio.c | 10 +++++++++- + drivers/leds/trigger/ledtrig-input.c | 19 ++++--------------- + include/linux/leds.h | 3 +++ + 3 files changed, 16 insertions(+), 16 deletions(-) + +--- a/drivers/leds/leds-gpio.c ++++ b/drivers/leds/leds-gpio.c +@@ -41,6 +41,13 @@ static void gpio_led_work(struct work_st + led_dat->platform_gpio_blink_set(led_dat->gpiod, + led_dat->new_level, NULL, NULL); + led_dat->blinking = 0; ++ } else if (led_dat->cdev.flags & SET_GPIO_INPUT) { ++ gpiod_direction_input(led_dat->gpiod); ++ led_dat->cdev.flags &= ~SET_GPIO_INPUT; ++ } ++ else if (led_dat->cdev.flags & SET_GPIO_OUTPUT) { ++ gpiod_direction_output(led_dat->gpiod, led_dat->new_level); ++ led_dat->cdev.flags &= ~SET_GPIO_OUTPUT; + } else + gpiod_set_value_cansleep(led_dat->gpiod, led_dat->new_level); + } +@@ -61,7 +68,8 @@ static void gpio_led_set(struct led_clas + * seem to have a reliable way to know if we're already in one; so + * let's just assume the worst. + */ +- if (led_dat->can_sleep) { ++ if (led_dat->can_sleep || ++ (led_dat->cdev.flags & (SET_GPIO_INPUT | SET_GPIO_OUTPUT) )) { + led_dat->new_level = level; + schedule_work(&led_dat->work); + } else { +--- a/drivers/leds/trigger/ledtrig-input.c ++++ b/drivers/leds/trigger/ledtrig-input.c +@@ -18,27 +18,16 @@ + #include + #include "../leds.h" + +-/* This is a hack to get at the private 'gpio' member */ +- +-struct gpio_led_data { +- struct led_classdev cdev; +- unsigned gpio; +-}; +- + static void input_trig_activate(struct led_classdev *led_cdev) + { +- struct gpio_led_data *led_dat = +- container_of(led_cdev, struct gpio_led_data, cdev); +- if (gpio_is_valid(led_dat->gpio)) +- gpio_direction_input(led_dat->gpio); ++ led_cdev->flags |= SET_GPIO_INPUT; ++ led_set_brightness_async(led_cdev, 0); + } + + static void input_trig_deactivate(struct led_classdev *led_cdev) + { +- struct gpio_led_data *led_dat = +- container_of(led_cdev, struct gpio_led_data, cdev); +- if (gpio_is_valid(led_dat->gpio)) +- gpio_direction_output(led_dat->gpio, 0); ++ led_cdev->flags |= SET_GPIO_OUTPUT; ++ led_set_brightness_async(led_cdev, 0); + } + + static struct led_trigger input_led_trigger = { +--- a/include/linux/leds.h ++++ b/include/linux/leds.h +@@ -47,6 +47,9 @@ struct led_classdev { + #define SET_BRIGHTNESS_ASYNC (1 << 21) + #define SET_BRIGHTNESS_SYNC (1 << 22) + #define LED_DEV_CAP_FLASH (1 << 23) ++ /* Additions for Raspberry Pi PWR LED */ ++#define SET_GPIO_INPUT (1 << 30) ++#define SET_GPIO_OUTPUT (1 << 31) + + /* Set LED brightness level */ + /* Must not sleep, use a workqueue if needed */ diff --git a/target/linux/brcm2708/patches-4.1/0056-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch b/target/linux/brcm2708/patches-4.1/0056-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch new file mode 100644 index 0000000..2dee1de --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0056-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch @@ -0,0 +1,22 @@ +From e338dddb10d7d0b02b123305a31832f8818af000 Mon Sep 17 00:00:00 2001 +From: notro +Date: Thu, 10 Jul 2014 13:59:47 +0200 +Subject: [PATCH 056/203] pinctrl-bcm2835: Set base to 0 give expected gpio + numbering + +Signed-off-by: Noralf Tronnes +--- + drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c ++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c +@@ -382,7 +382,7 @@ static struct gpio_chip bcm2835_gpio_chi + .get = bcm2835_gpio_get, + .set = bcm2835_gpio_set, + .to_irq = bcm2835_gpio_to_irq, +- .base = -1, ++ .base = 0, + .ngpio = BCM2835_NUM_GPIOS, + .can_sleep = false, + }; diff --git a/target/linux/brcm2708/patches-4.1/0057-pinctrl-bcm2835-bcm2835_gpio_direction_output-must-s.patch b/target/linux/brcm2708/patches-4.1/0057-pinctrl-bcm2835-bcm2835_gpio_direction_output-must-s.patch new file mode 100644 index 0000000..bfb6797 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0057-pinctrl-bcm2835-bcm2835_gpio_direction_output-must-s.patch @@ -0,0 +1,28 @@ +From 8eed7ff146c26b290b51011f72b5262909dcd878 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 4 Feb 2015 10:02:24 +0000 +Subject: [PATCH 057/203] pinctrl-bcm2835: bcm2835_gpio_direction_output must + set the value + +--- + drivers/pinctrl/bcm/pinctrl-bcm2835.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c ++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c +@@ -355,7 +355,14 @@ static int bcm2835_gpio_get(struct gpio_ + static int bcm2835_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) + { +- return pinctrl_gpio_direction_output(chip->base + offset); ++ struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); ++ int ret; ++ ++ ret = pinctrl_gpio_direction_output(chip->base + offset); ++ if (ret >= 0) ++ bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); ++ ++ return ret; + } + + static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) diff --git a/target/linux/brcm2708/patches-4.1/0058-pinctrl-bcm2835-Fix-interrupt-handling-for-GPIOs-28-.patch b/target/linux/brcm2708/patches-4.1/0058-pinctrl-bcm2835-Fix-interrupt-handling-for-GPIOs-28-.patch new file mode 100644 index 0000000..fb74af2 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0058-pinctrl-bcm2835-Fix-interrupt-handling-for-GPIOs-28-.patch @@ -0,0 +1,146 @@ +From ac7db17a7b836e64616f6e556b43969f4ed7ace2 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 24 Feb 2015 13:40:50 +0000 +Subject: [PATCH 058/203] pinctrl-bcm2835: Fix interrupt handling for GPIOs + 28-31 and 46-53 + +Contrary to the documentation, the BCM2835 GPIO controller actually has +four interrupt lines - one each for the three IRQ groups and one common. Rather +confusingly, the GPIO interrupt groups don't correspond directly with the GPIO +control banks. Instead, GPIOs 0-27 generate IRQ GPIO0, 28-45 GPIO1 and +46-53 GPIO2. + +Awkwardly, the GPIOS for IRQ GPIO1 straddle two 32-entry GPIO banks, so it is +cleaner to split out a function to process the interrupts for a single GPIO +bank. + +This bug has only just been observed because GPIOs above 27 can only be +accessed on an old Raspberry Pi with the optional P5 header fitted, where +the pins are often used for I2S instead. +--- + drivers/pinctrl/bcm/pinctrl-bcm2835.c | 51 ++++++++++++++++++++++++++--------- + 1 file changed, 39 insertions(+), 12 deletions(-) + +--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c ++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c +@@ -47,6 +47,7 @@ + #define MODULE_NAME "pinctrl-bcm2835" + #define BCM2835_NUM_GPIOS 54 + #define BCM2835_NUM_BANKS 2 ++#define BCM2835_NUM_IRQS 3 + + #define BCM2835_PIN_BITMAP_SZ \ + DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8) +@@ -88,13 +89,13 @@ enum bcm2835_pinconf_pull { + + struct bcm2835_gpio_irqdata { + struct bcm2835_pinctrl *pc; +- int bank; ++ int irqgroup; + }; + + struct bcm2835_pinctrl { + struct device *dev; + void __iomem *base; +- int irq[BCM2835_NUM_BANKS]; ++ int irq[BCM2835_NUM_IRQS]; + + /* note: locking assumes each bank will have its own unsigned long */ + unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; +@@ -105,7 +106,7 @@ struct bcm2835_pinctrl { + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range gpio_range; + +- struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS]; ++ struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS]; + spinlock_t irq_lock[BCM2835_NUM_BANKS]; + }; + +@@ -394,17 +395,16 @@ static struct gpio_chip bcm2835_gpio_chi + .can_sleep = false, + }; + +-static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) ++static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, ++ unsigned int bank, u32 mask) + { +- struct bcm2835_gpio_irqdata *irqdata = dev_id; +- struct bcm2835_pinctrl *pc = irqdata->pc; +- int bank = irqdata->bank; + unsigned long events; + unsigned offset; + unsigned gpio; + unsigned int type; + + events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); ++ events &= mask; + events &= pc->enabled_irq_map[bank]; + for_each_set_bit(offset, &events, 32) { + gpio = (32 * bank) + offset; +@@ -412,7 +412,30 @@ static irqreturn_t bcm2835_gpio_irq_hand + + generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); + } +- return events ? IRQ_HANDLED : IRQ_NONE; ++ ++ return (events != 0); ++} ++ ++static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) ++{ ++ struct bcm2835_gpio_irqdata *irqdata = dev_id; ++ struct bcm2835_pinctrl *pc = irqdata->pc; ++ int handled = 0; ++ ++ switch (irqdata->irqgroup) { ++ case 0: /* IRQ0 covers GPIOs 0-27 */ ++ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); ++ break; ++ case 1: /* IRQ1 covers GPIOs 28-45 */ ++ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) | ++ bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); ++ break; ++ case 2: /* IRQ2 covers GPIOs 46-53 */ ++ handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); ++ break; ++ } ++ ++ return handled ? IRQ_HANDLED : IRQ_NONE; + } + + static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, +@@ -1000,8 +1023,6 @@ static int bcm2835_pinctrl_probe(struct + for (i = 0; i < BCM2835_NUM_BANKS; i++) { + unsigned long events; + unsigned offset; +- int len; +- char *name; + + /* clear event detection flags */ + bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); +@@ -1016,10 +1037,15 @@ static int bcm2835_pinctrl_probe(struct + for_each_set_bit(offset, &events, 32) + bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); + ++ spin_lock_init(&pc->irq_lock[i]); ++ } ++ ++ for (i = 0; i < BCM2835_NUM_IRQS; i++) { ++ int len; ++ char *name; + pc->irq[i] = irq_of_parse_and_map(np, i); + pc->irq_data[i].pc = pc; +- pc->irq_data[i].bank = i; +- spin_lock_init(&pc->irq_lock[i]); ++ pc->irq_data[i].irqgroup = i; + + len = strlen(dev_name(pc->dev)) + 16; + name = devm_kzalloc(pc->dev, len, GFP_KERNEL); +@@ -1077,6 +1103,7 @@ static struct platform_driver bcm2835_pi + .remove = bcm2835_pinctrl_remove, + .driver = { + .name = MODULE_NAME, ++ .owner = THIS_MODULE, + .of_match_table = bcm2835_pinctrl_match, + }, + }; diff --git a/target/linux/brcm2708/patches-4.1/0059-pinctrl-bcm2835-Only-request-the-interrupts-listed-i.patch b/target/linux/brcm2708/patches-4.1/0059-pinctrl-bcm2835-Only-request-the-interrupts-listed-i.patch new file mode 100644 index 0000000..13b5d9e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0059-pinctrl-bcm2835-Only-request-the-interrupts-listed-i.patch @@ -0,0 +1,27 @@ +From c8aa040735dccf98d20506578874a9c8fa0a87f4 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 26 Feb 2015 09:58:22 +0000 +Subject: [PATCH 059/203] pinctrl-bcm2835: Only request the interrupts listed + in the DTB + +Although the GPIO controller can generate three interrupts (four counting +the common one), the device tree files currently only specify two. In the +absence of the third, simply don't register that interrupt (as opposed to +registering 0), which has the effect of making it impossible to generate +interrupts for GPIOs 46-53 which, since they share pins with the SD card +interface, is unlikely to be a problem. +--- + drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c ++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c +@@ -1044,6 +1044,8 @@ static int bcm2835_pinctrl_probe(struct + int len; + char *name; + pc->irq[i] = irq_of_parse_and_map(np, i); ++ if (pc->irq[i] == 0) ++ break; + pc->irq_data[i].pc = pc; + pc->irq_data[i].irqgroup = i; + diff --git a/target/linux/brcm2708/patches-4.1/0060-enc28j60-Add-device-tree-compatible-string-and-an-ov.patch b/target/linux/brcm2708/patches-4.1/0060-enc28j60-Add-device-tree-compatible-string-and-an-ov.patch new file mode 100644 index 0000000..809ebc4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0060-enc28j60-Add-device-tree-compatible-string-and-an-ov.patch @@ -0,0 +1,34 @@ +From 91ab8311ca5802198aae08730ae4883cabfa6600 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 27 Feb 2015 15:10:24 +0000 +Subject: [PATCH 060/203] enc28j60: Add device tree compatible string and an + overlay + +--- + drivers/net/ethernet/microchip/enc28j60.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/drivers/net/ethernet/microchip/enc28j60.c ++++ b/drivers/net/ethernet/microchip/enc28j60.c +@@ -1630,10 +1630,21 @@ static int enc28j60_remove(struct spi_de + return 0; + } + ++#ifdef CONFIG_OF ++static const struct of_device_id enc28j60_of_match[] = { ++ { .compatible = "microchip,enc28j60", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, enc28j60_of_match); ++#endif ++ + static struct spi_driver enc28j60_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, ++#ifdef CONFIG_OF ++ .of_match_table = enc28j60_of_match, ++#endif + }, + .probe = enc28j60_probe, + .remove = enc28j60_remove, diff --git a/target/linux/brcm2708/patches-4.1/0061-Add-driver-for-rpi-proto.patch b/target/linux/brcm2708/patches-4.1/0061-Add-driver-for-rpi-proto.patch new file mode 100644 index 0000000..5b4011f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0061-Add-driver-for-rpi-proto.patch @@ -0,0 +1,210 @@ +From 24580cf7424fd50f99667d7fd74973c6be768835 Mon Sep 17 00:00:00 2001 +From: Waldemar Brodkorb +Date: Wed, 25 Mar 2015 09:26:17 +0100 +Subject: [PATCH 061/203] Add driver for rpi-proto + +Forward port of 3.10.x driver from https://github.com/koalo +We are using a custom board and would like to use rpi 3.18.x +kernel. Patch works fine for our embedded system. + +URL to the audio chip: +http://www.mikroe.com/add-on-boards/audio-voice/audio-codec-proto/ + +Playback tested with devicetree enabled. + +Signed-off-by: Waldemar Brodkorb +--- + sound/soc/bcm/Kconfig | 7 +++ + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/rpi-proto.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 162 insertions(+) + create mode 100644 sound/soc/bcm/rpi-proto.c + +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -54,6 +54,13 @@ config SND_BCM2708_SOC_RPI_DAC + help + Say Y or M if you want to add support for RPi-DAC. + ++config SND_BCM2708_SOC_RPI_PROTO ++ tristate "Support for Rpi-PROTO" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_WM8731 ++ help ++ Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731). ++ + config SND_BCM2708_SOC_IQAUDIO_DAC + tristate "Support for IQaudIO-DAC" + depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -14,6 +14,7 @@ snd-soc-hifiberry-dacplus-objs := hifibe + snd-soc-hifiberry-digi-objs := hifiberry_digi.o + snd-soc-hifiberry-amp-objs := hifiberry_amp.o + snd-soc-rpi-dac-objs := rpi-dac.o ++snd-soc-rpi-proto-objs := rpi-proto.o + snd-soc-iqaudio-dac-objs := iqaudio-dac.o + + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o +@@ -21,4 +22,5 @@ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_D + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o + obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o + obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o +--- /dev/null ++++ b/sound/soc/bcm/rpi-proto.c +@@ -0,0 +1,153 @@ ++/* ++ * ASoC driver for PROTO AudioCODEC (with a WM8731) ++ * connected to a Raspberry Pi ++ * ++ * Author: Florian Meier, ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "../codecs/wm8731.h" ++ ++static const unsigned int wm8731_rates_12288000[] = { ++ 8000, 32000, 48000, 96000, ++}; ++ ++static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = { ++ .list = wm8731_rates_12288000, ++ .count = ARRAY_SIZE(wm8731_rates_12288000), ++}; ++ ++static int snd_rpi_proto_startup(struct snd_pcm_substream *substream) ++{ ++ /* Setup constraints, because there is a 12.288 MHz XTAL on the board */ ++ snd_pcm_hw_constraint_list(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, ++ &wm8731_constraints_12288000); ++ return 0; ++} ++ ++static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ struct snd_soc_dai *codec_dai = rtd->codec_dai; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ int sysclk = 12288000; /* This is fixed on this board */ ++ ++ /* Set proto bclk */ ++ int ret = snd_soc_dai_set_bclk_ratio(cpu_dai,32*2); ++ if (ret < 0){ ++ dev_err(codec->dev, ++ "Failed to set BCLK ratio %d\n", ret); ++ return ret; ++ } ++ ++ /* Set proto sysclk */ ++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL, ++ sysclk, SND_SOC_CLOCK_IN); ++ if (ret < 0) { ++ dev_err(codec->dev, ++ "Failed to set WM8731 SYSCLK: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_proto_ops = { ++ .startup = snd_rpi_proto_startup, ++ .hw_params = snd_rpi_proto_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_proto_dai[] = { ++{ ++ .name = "WM8731", ++ .stream_name = "WM8731 HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "wm8731-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "wm8731.1-001a", ++ .dai_fmt = SND_SOC_DAIFMT_I2S ++ | SND_SOC_DAIFMT_NB_NF ++ | SND_SOC_DAIFMT_CBM_CFM, ++ .ops = &snd_rpi_proto_ops, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_proto = { ++ .name = "snd_rpi_proto", ++ .dai_link = snd_rpi_proto_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_proto_dai), ++}; ++ ++static int snd_rpi_proto_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_proto.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_proto_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_proto); ++ if (ret) { ++ dev_err(&pdev->dev, ++ "snd_soc_register_card() failed: %d\n", ret); ++ } ++ ++ return ret; ++} ++ ++ ++static int snd_rpi_proto_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_proto); ++} ++ ++static const struct of_device_id snd_rpi_proto_of_match[] = { ++ { .compatible = "rpi,rpi-proto", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_proto_of_match); ++ ++static struct platform_driver snd_rpi_proto_driver = { ++ .driver = { ++ .name = "snd-rpi-proto", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_proto_of_match, ++ }, ++ .probe = snd_rpi_proto_probe, ++ .remove = snd_rpi_proto_remove, ++}; ++ ++module_platform_driver(snd_rpi_proto_driver); ++ ++MODULE_AUTHOR("Florian Meier"); ++MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm2708/patches-4.1/0062-Add-Device-Tree-support-for-RPi-DAC.patch b/target/linux/brcm2708/patches-4.1/0062-Add-Device-Tree-support-for-RPi-DAC.patch new file mode 100644 index 0000000..5a66fa2 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0062-Add-Device-Tree-support-for-RPi-DAC.patch @@ -0,0 +1,73 @@ +From a7154ea03e9acec217e3d1cb70d0aed869e55669 Mon Sep 17 00:00:00 2001 +From: Clive Messer +Date: Thu, 2 Apr 2015 12:22:55 +0100 +Subject: [PATCH 062/203] Add Device Tree support for RPi-DAC. + +--- + sound/soc/bcm/rpi-dac.c | 21 +++++++++++++++++++++ + sound/soc/codecs/pcm1794a.c | 7 +++++++ + 2 files changed, 28 insertions(+) + +--- a/sound/soc/bcm/rpi-dac.c ++++ b/sound/soc/bcm/rpi-dac.c +@@ -69,6 +69,20 @@ static int snd_rpi_rpi_dac_probe(struct + int ret = 0; + + snd_rpi_rpi_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ + ret = snd_soc_register_card(&snd_rpi_rpi_dac); + if (ret) + dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); +@@ -81,10 +95,17 @@ static int snd_rpi_rpi_dac_remove(struct + return snd_soc_unregister_card(&snd_rpi_rpi_dac); + } + ++static const struct of_device_id snd_rpi_rpi_dac_of_match[] = { ++ { .compatible = "rpi,rpi-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match); ++ + static struct platform_driver snd_rpi_rpi_dac_driver = { + .driver = { + .name = "snd-rpi-dac", + .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_rpi_dac_of_match, + }, + .probe = snd_rpi_rpi_dac_probe, + .remove = snd_rpi_rpi_dac_remove, +--- a/sound/soc/codecs/pcm1794a.c ++++ b/sound/soc/codecs/pcm1794a.c +@@ -46,12 +46,19 @@ static int pcm1794a_remove(struct platfo + return 0; + } + ++static const struct of_device_id pcm1794a_of_match[] = { ++ { .compatible = "ti,pcm1794a", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pcm1794a_of_match); ++ + static struct platform_driver pcm1794a_codec_driver = { + .probe = pcm1794a_probe, + .remove = pcm1794a_remove, + .driver = { + .name = "pcm1794a-codec", + .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(pcm1794a_of_match), + }, + }; + diff --git a/target/linux/brcm2708/patches-4.1/0063-config-Add-default-configs.patch b/target/linux/brcm2708/patches-4.1/0063-config-Add-default-configs.patch new file mode 100644 index 0000000..6cb9934 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0063-config-Add-default-configs.patch @@ -0,0 +1,2421 @@ +From dedcf4042bd975ee5df588f103f7fc5effb61baa Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Mon, 13 Apr 2015 17:16:29 +0100 +Subject: [PATCH 063/203] config: Add default configs + +--- + arch/arm/configs/bcm2709_defconfig | 1204 ++++++++++++++++++++++++++++++++++++ + arch/arm/configs/bcmrpi_defconfig | 1199 +++++++++++++++++++++++++++++++++++ + 2 files changed, 2403 insertions(+) + create mode 100644 arch/arm/configs/bcm2709_defconfig + create mode 100644 arch/arm/configs/bcmrpi_defconfig + +--- /dev/null ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -0,0 +1,1204 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0 ++CONFIG_LOCALVERSION="-v7" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_FHANDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_IKCONFIG=m ++CONFIG_IKCONFIG_PROC=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_MEMCG=y ++CONFIG_BLK_CGROUP=y ++CONFIG_NAMESPACES=y ++CONFIG_SCHED_AUTOGROUP=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_PROFILING=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y ++CONFIG_JUMP_LABEL=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_CFQ_GROUP_IOSCHED=y ++CONFIG_ARCH_BCM2709=y ++CONFIG_BCM2709_DT=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_SMP=y ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_2G=y ++CONFIG_PREEMPT=y ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_CLEANCACHE=y ++CONFIG_FRONTSWAP=y ++CONFIG_CMA=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_SECCOMP=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=m ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_VFP=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_BINFMT_MISC=m ++# CONFIG_SUSPEND is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=m ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE_DEMUX=m ++CONFIG_NET_IPGRE=m ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=m ++CONFIG_INET_LRO=m ++CONFIG_INET_DIAG=m ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_TUNNEL=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_IPV6_MROUTE=y ++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IPV6_PIMSM_V2=y ++CONFIG_NETFILTER=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_CLUSTERIP=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_IP6_NF_NAT=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_ATM=m ++CONFIG_L2TP=m ++CONFIG_L2TP_V3=y ++CONFIG_L2TP_IP=m ++CONFIG_L2TP_ETH=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_ATALK=m ++CONFIG_6LOWPAN=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_BATMAN_ADV=m ++CONFIG_OPENVSWITCH=m ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++CONFIG_CAN=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRNET=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_6LOWPAN=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_BT_WILINK=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_DRBD=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_ATA_OVER_ETH=m ++CONFIG_EEPROM_AT24=m ++CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set ++CONFIG_BLK_DEV_SD=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_CHR_DEV_SG=m ++CONFIG_SCSI_ISCSI_ATTRS=y ++CONFIG_ISCSI_TCP=m ++CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_MD=y ++CONFIG_MD_LINEAR=m ++CONFIG_MD_RAID0=m ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_DELAY=m ++CONFIG_NETDEVICES=y ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++CONFIG_IFB=m ++CONFIG_MACVLAN=m ++CONFIG_NETCONSOLE=m ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_ENC28J60=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_AX88179_178A=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_CDC_NCM=m ++CONFIG_USB_NET_HUAWEI_CDC_NCM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SR9700=m ++CONFIG_USB_NET_SR9800=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_CARDS=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_USB=m ++CONFIG_AR5523=m ++CONFIG_B43=m ++# CONFIG_B43_PHY_N is not set ++CONFIG_B43LEGACY=m ++CONFIG_BRCMFMAC=m ++CONFIG_BRCMFMAC_USB=y ++CONFIG_HOSTAP=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT3573=y ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_RT55XX=y ++CONFIG_RT2800USB_UNKNOWN=y ++CONFIG_RTL8192CU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_INPUT_POLLDEV=m ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=m ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=y ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_ADS7846=m ++CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_TTY_PRINTK=y ++CONFIG_HW_RANDOM=y ++CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_HW_RANDOM_BCM2708=m ++CONFIG_RAW_DRIVER=y ++CONFIG_BRCM_CHAR_DRIVERS=y ++CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VC_SM=y ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_BCM2708=m ++CONFIG_SPI=y ++CONFIG_SPI_BCM2835=m ++CONFIG_SPI_BCM2708=m ++CONFIG_SPI_SPIDEV=y ++CONFIG_PPS=m ++CONFIG_PPS_CLIENT_LDISC=m ++CONFIG_PPS_CLIENT_GPIO=m ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_ARIZONA=m ++CONFIG_GPIO_STMPE=y ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2413=m ++CONFIG_W1_SLAVE_DS2406=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2760=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_DS2781=m ++CONFIG_W1_SLAVE_DS28E04=m ++CONFIG_W1_SLAVE_BQ27000=m ++CONFIG_BATTERY_DS2760=m ++# CONFIG_HWMON is not set ++CONFIG_THERMAL=y ++CONFIG_THERMAL_BCM2835=y ++CONFIG_WATCHDOG=y ++CONFIG_BCM2708_WDT=m ++CONFIG_BCM2835_WDT=m ++CONFIG_UCB1400_CORE=m ++CONFIG_MFD_STMPE=y ++CONFIG_STMPE_SPI=y ++CONFIG_MFD_ARIZONA_I2C=m ++CONFIG_MFD_ARIZONA_SPI=m ++CONFIG_MFD_WM5102=y ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_RC_SUPPORT=y ++CONFIG_MEDIA_CONTROLLER=y ++CONFIG_LIRC=m ++CONFIG_RC_DEVICES=y ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_IR_GPIO_CIR=m ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_DTCS033=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STK1135=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_VIDEO_STK1160_AC97=y ++CONFIG_VIDEO_GO7007=m ++CONFIG_VIDEO_GO7007_USB=m ++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_AU0828_RC=y ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_TM6000=m ++CONFIG_VIDEO_TM6000_ALSA=m ++CONFIG_VIDEO_TM6000_DVB=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_DVB_USB_DVBSKY=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_DVB_AS102=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_V4L2=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_BCM2835=y ++CONFIG_VIDEO_BCM2835_MMAL=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_I2C_SI470X=m ++CONFIG_RADIO_SI4713=m ++CONFIG_I2C_SI4713=m ++CONFIG_USB_MR800=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_RADIO_WL128X=m ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_TVP5150=m ++CONFIG_VIDEO_TW2804=m ++CONFIG_VIDEO_TW9903=m ++CONFIG_VIDEO_TW9906=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_FB=y ++CONFIG_FB_BCM2708=y ++CONFIG_FB_SSD1307=m ++# CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_GPIO=m ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_SOC=m ++CONFIG_SND_BCM2708_SOC_I2S=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m ++CONFIG_SND_BCM2708_SOC_RPI_DAC=m ++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_SIMPLE_CARD=m ++CONFIG_SOUND_PRIME=m ++CONFIG_HIDRAW=y ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_XINMO=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_DWCOTG=y ++CONFIG_USB_PRINTER=m ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USBIP_CORE=m ++CONFIG_USBIP_VHCI_HCD=m ++CONFIG_USBIP_HOST=m ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_XSENS_MT=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m ++CONFIG_MMC=y ++CONFIG_MMC_BLOCK_MINORS=32 ++CONFIG_MMC_BCM2835=y ++CONFIG_MMC_BCM2835_DMA=y ++CONFIG_MMC_BCM2835_SDHOST=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SPI=m ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_GPIO=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=m ++CONFIG_LEDS_TRIGGER_CAMERA=m ++CONFIG_LEDS_TRIGGER_INPUT=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_HCTOSYS is not set ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_ISL12057=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_DS3234=m ++CONFIG_RTC_DRV_PCF2123=m ++CONFIG_RTC_DRV_RX4581=m ++CONFIG_DMADEVICES=y ++CONFIG_DMA_BCM2708=y ++CONFIG_UIO=m ++CONFIG_UIO_PDRV_GENIRQ=m ++CONFIG_STAGING=y ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_R8188EU=m ++CONFIG_R8723AU=m ++CONFIG_VT6656=m ++CONFIG_SPEAKUP=m ++CONFIG_SPEAKUP_SYNTH_SOFT=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_LIRC_STAGING=y ++CONFIG_LIRC_IMON=m ++CONFIG_LIRC_RPI=m ++CONFIG_LIRC_SASEM=m ++CONFIG_LIRC_SERIAL=m ++CONFIG_FB_TFT=m ++CONFIG_FB_TFT_AGM1264K_FL=m ++CONFIG_FB_TFT_BD663474=m ++CONFIG_FB_TFT_HX8340BN=m ++CONFIG_FB_TFT_HX8347D=m ++CONFIG_FB_TFT_HX8353D=m ++CONFIG_FB_TFT_ILI9320=m ++CONFIG_FB_TFT_ILI9325=m ++CONFIG_FB_TFT_ILI9340=m ++CONFIG_FB_TFT_ILI9341=m ++CONFIG_FB_TFT_ILI9481=m ++CONFIG_FB_TFT_ILI9486=m ++CONFIG_FB_TFT_PCD8544=m ++CONFIG_FB_TFT_RA8875=m ++CONFIG_FB_TFT_S6D02A1=m ++CONFIG_FB_TFT_S6D1121=m ++CONFIG_FB_TFT_SSD1289=m ++CONFIG_FB_TFT_SSD1306=m ++CONFIG_FB_TFT_SSD1331=m ++CONFIG_FB_TFT_SSD1351=m ++CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_TINYLCD=m ++CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1701=m ++CONFIG_FB_TFT_UPD161704=m ++CONFIG_FB_TFT_WATTEROTT=m ++CONFIG_FB_FLEX=m ++CONFIG_FB_TFT_FBTFT_DEVICE=m ++CONFIG_MAILBOX=y ++CONFIG_BCM2708_MBOX=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXTCON=m ++CONFIG_EXTCON_ARIZONA=m ++CONFIG_IIO=m ++CONFIG_IIO_BUFFER=y ++CONFIG_IIO_BUFFER_CB=y ++CONFIG_IIO_KFIFO_BUF=m ++CONFIG_DHT11=m ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_FANOTIFY=y ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++CONFIG_NTFS_RW=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_F2FS_FS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_SWAP=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_DLM=m ++CONFIG_PRINTK_TIME=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_DEBUG_MEMORY_INIT=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_TIMER_STATS=y ++# CONFIG_DEBUG_PREEMPT is not set ++CONFIG_IRQSOFF_TRACER=y ++CONFIG_SCHED_TRACER=y ++CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++# CONFIG_KPROBE_EVENT is not set ++CONFIG_FUNCTION_PROFILER=y ++CONFIG_KGDB=y ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y ++CONFIG_CRYPTO_USER=m ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTS=m ++CONFIG_CRYPTO_XTS=m ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_SHA1_ARM_NEON=m ++CONFIG_CRYPTO_SHA512_ARM_NEON=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_AES_ARM_BS=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_HW is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y +--- /dev/null ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -0,0 +1,1199 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0 ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_FHANDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_IKCONFIG=m ++CONFIG_IKCONFIG_PROC=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_MEMCG=y ++CONFIG_BLK_CGROUP=y ++CONFIG_NAMESPACES=y ++CONFIG_SCHED_AUTOGROUP=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_PROFILING=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y ++CONFIG_JUMP_LABEL=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_CFQ_GROUP_IOSCHED=y ++CONFIG_ARCH_BCM2708=y ++CONFIG_BCM2708_DT=y ++CONFIG_PREEMPT=y ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_CLEANCACHE=y ++CONFIG_FRONTSWAP=y ++CONFIG_CMA=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_SECCOMP=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=m ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_VFP=y ++CONFIG_BINFMT_MISC=m ++# CONFIG_SUSPEND is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=m ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE_DEMUX=m ++CONFIG_NET_IPGRE=m ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=m ++CONFIG_INET_LRO=m ++CONFIG_INET_DIAG=m ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_TUNNEL=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_IPV6_MROUTE=y ++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IPV6_PIMSM_V2=y ++CONFIG_NETFILTER=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_CLUSTERIP=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_IP6_NF_NAT=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_ATM=m ++CONFIG_L2TP=m ++CONFIG_L2TP_V3=y ++CONFIG_L2TP_IP=m ++CONFIG_L2TP_ETH=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_ATALK=m ++CONFIG_6LOWPAN=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_BATMAN_ADV=m ++CONFIG_OPENVSWITCH=m ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++CONFIG_CAN=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRNET=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_6LOWPAN=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_BT_WILINK=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_DRBD=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_ATA_OVER_ETH=m ++CONFIG_EEPROM_AT24=m ++CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set ++CONFIG_BLK_DEV_SD=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_CHR_DEV_SG=m ++CONFIG_SCSI_ISCSI_ATTRS=y ++CONFIG_ISCSI_TCP=m ++CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_MD=y ++CONFIG_MD_LINEAR=m ++CONFIG_MD_RAID0=m ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_DELAY=m ++CONFIG_NETDEVICES=y ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++CONFIG_IFB=m ++CONFIG_MACVLAN=m ++CONFIG_NETCONSOLE=m ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_ENC28J60=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_AX88179_178A=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_CDC_NCM=m ++CONFIG_USB_NET_HUAWEI_CDC_NCM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SR9700=m ++CONFIG_USB_NET_SR9800=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_CARDS=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_USB=m ++CONFIG_AR5523=m ++CONFIG_B43=m ++# CONFIG_B43_PHY_N is not set ++CONFIG_B43LEGACY=m ++CONFIG_BRCMFMAC=m ++CONFIG_BRCMFMAC_USB=y ++CONFIG_HOSTAP=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT3573=y ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_RT55XX=y ++CONFIG_RT2800USB_UNKNOWN=y ++CONFIG_RTL8192CU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_INPUT_POLLDEV=m ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=m ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=y ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_ADS7846=m ++CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_TTY_PRINTK=y ++CONFIG_HW_RANDOM=y ++CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_HW_RANDOM_BCM2708=m ++CONFIG_RAW_DRIVER=y ++CONFIG_BRCM_CHAR_DRIVERS=y ++CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VC_SM=y ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_BCM2708=m ++CONFIG_SPI=y ++CONFIG_SPI_BCM2835=m ++CONFIG_SPI_BCM2708=m ++CONFIG_SPI_SPIDEV=y ++CONFIG_PPS=m ++CONFIG_PPS_CLIENT_LDISC=m ++CONFIG_PPS_CLIENT_GPIO=m ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_ARIZONA=m ++CONFIG_GPIO_STMPE=y ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2413=m ++CONFIG_W1_SLAVE_DS2406=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2760=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_DS2781=m ++CONFIG_W1_SLAVE_DS28E04=m ++CONFIG_W1_SLAVE_BQ27000=m ++CONFIG_BATTERY_DS2760=m ++# CONFIG_HWMON is not set ++CONFIG_THERMAL=y ++CONFIG_THERMAL_BCM2835=y ++CONFIG_WATCHDOG=y ++CONFIG_BCM2708_WDT=m ++CONFIG_BCM2835_WDT=m ++CONFIG_UCB1400_CORE=m ++CONFIG_MFD_STMPE=y ++CONFIG_STMPE_SPI=y ++CONFIG_MFD_ARIZONA_I2C=m ++CONFIG_MFD_ARIZONA_SPI=m ++CONFIG_MFD_WM5102=y ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_RC_SUPPORT=y ++CONFIG_MEDIA_CONTROLLER=y ++CONFIG_LIRC=m ++CONFIG_RC_DEVICES=y ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_IR_GPIO_CIR=m ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_DTCS033=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STK1135=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_VIDEO_STK1160_AC97=y ++CONFIG_VIDEO_GO7007=m ++CONFIG_VIDEO_GO7007_USB=m ++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_AU0828_RC=y ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_TM6000=m ++CONFIG_VIDEO_TM6000_ALSA=m ++CONFIG_VIDEO_TM6000_DVB=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_DVB_USB_DVBSKY=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_DVB_AS102=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_V4L2=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_BCM2835=y ++CONFIG_VIDEO_BCM2835_MMAL=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_I2C_SI470X=m ++CONFIG_RADIO_SI4713=m ++CONFIG_I2C_SI4713=m ++CONFIG_USB_MR800=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_RADIO_WL128X=m ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_TVP5150=m ++CONFIG_VIDEO_TW2804=m ++CONFIG_VIDEO_TW9903=m ++CONFIG_VIDEO_TW9906=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_FB=y ++CONFIG_FB_BCM2708=y ++CONFIG_FB_SSD1307=m ++# CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_GPIO=m ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_SOC=m ++CONFIG_SND_BCM2708_SOC_I2S=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m ++CONFIG_SND_BCM2708_SOC_RPI_DAC=m ++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_SIMPLE_CARD=m ++CONFIG_SOUND_PRIME=m ++CONFIG_HIDRAW=y ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_XINMO=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_DWCOTG=y ++CONFIG_USB_PRINTER=m ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USBIP_CORE=m ++CONFIG_USBIP_VHCI_HCD=m ++CONFIG_USBIP_HOST=m ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_XSENS_MT=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m ++CONFIG_MMC=y ++CONFIG_MMC_BLOCK_MINORS=32 ++CONFIG_MMC_BCM2835=y ++CONFIG_MMC_BCM2835_DMA=y ++CONFIG_MMC_BCM2835_SDHOST=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SPI=m ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_GPIO=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=m ++CONFIG_LEDS_TRIGGER_CAMERA=m ++CONFIG_LEDS_TRIGGER_INPUT=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_HCTOSYS is not set ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_ISL12057=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_DS3234=m ++CONFIG_RTC_DRV_PCF2123=m ++CONFIG_RTC_DRV_RX4581=m ++CONFIG_DMADEVICES=y ++CONFIG_DMA_BCM2708=y ++CONFIG_UIO=m ++CONFIG_UIO_PDRV_GENIRQ=m ++CONFIG_STAGING=y ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_R8188EU=m ++CONFIG_R8723AU=m ++CONFIG_VT6656=m ++CONFIG_SPEAKUP=m ++CONFIG_SPEAKUP_SYNTH_SOFT=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_LIRC_STAGING=y ++CONFIG_LIRC_IMON=m ++CONFIG_LIRC_RPI=m ++CONFIG_LIRC_SASEM=m ++CONFIG_LIRC_SERIAL=m ++CONFIG_FB_TFT=m ++CONFIG_FB_TFT_AGM1264K_FL=m ++CONFIG_FB_TFT_BD663474=m ++CONFIG_FB_TFT_HX8340BN=m ++CONFIG_FB_TFT_HX8347D=m ++CONFIG_FB_TFT_HX8353D=m ++CONFIG_FB_TFT_ILI9320=m ++CONFIG_FB_TFT_ILI9325=m ++CONFIG_FB_TFT_ILI9340=m ++CONFIG_FB_TFT_ILI9341=m ++CONFIG_FB_TFT_ILI9481=m ++CONFIG_FB_TFT_ILI9486=m ++CONFIG_FB_TFT_PCD8544=m ++CONFIG_FB_TFT_RA8875=m ++CONFIG_FB_TFT_S6D02A1=m ++CONFIG_FB_TFT_S6D1121=m ++CONFIG_FB_TFT_SSD1289=m ++CONFIG_FB_TFT_SSD1306=m ++CONFIG_FB_TFT_SSD1331=m ++CONFIG_FB_TFT_SSD1351=m ++CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_TINYLCD=m ++CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1701=m ++CONFIG_FB_TFT_UPD161704=m ++CONFIG_FB_TFT_WATTEROTT=m ++CONFIG_FB_FLEX=m ++CONFIG_FB_TFT_FBTFT_DEVICE=m ++CONFIG_MAILBOX=y ++CONFIG_BCM2708_MBOX=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXTCON=m ++CONFIG_EXTCON_ARIZONA=m ++CONFIG_IIO=m ++CONFIG_IIO_BUFFER=y ++CONFIG_IIO_BUFFER_CB=y ++CONFIG_IIO_KFIFO_BUF=m ++CONFIG_DHT11=m ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_FANOTIFY=y ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++CONFIG_NTFS_RW=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_F2FS_FS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_SWAP=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_DLM=m ++CONFIG_PRINTK_TIME=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_DEBUG_MEMORY_INIT=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_TIMER_STATS=y ++# CONFIG_DEBUG_PREEMPT is not set ++CONFIG_LATENCYTOP=y ++CONFIG_IRQSOFF_TRACER=y ++CONFIG_SCHED_TRACER=y ++CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++# CONFIG_KPROBE_EVENT is not set ++CONFIG_FUNCTION_PROFILER=y ++CONFIG_KGDB=y ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y ++CONFIG_CRYPTO_USER=m ++CONFIG_CRYPTO_CRYPTD=m ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTS=m ++CONFIG_CRYPTO_XTS=m ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_SHA1_ARM=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_AES_ARM=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_HW is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y diff --git a/target/linux/brcm2708/patches-4.1/0064-smsx95xx-fix-crimes-against-truesize.patch b/target/linux/brcm2708/patches-4.1/0064-smsx95xx-fix-crimes-against-truesize.patch new file mode 100644 index 0000000..1522a40 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0064-smsx95xx-fix-crimes-against-truesize.patch @@ -0,0 +1,33 @@ +From df86d2a4a92db44754fa0139b37a197a6d70b107 Mon Sep 17 00:00:00 2001 +From: Steve Glendinning +Date: Thu, 19 Feb 2015 18:47:12 +0000 +Subject: [PATCH 064/203] smsx95xx: fix crimes against truesize + +smsc95xx is adjusting truesize when it shouldn't, and following a recent patch from Eric this is now triggering warnings. + +This patch stops smsc95xx from changing truesize. + +Signed-off-by: Steve Glendinning +--- + drivers/net/usb/smsc95xx.c | 2 -- + 1 file changed, 2 deletions(-) + mode change 100644 => 100755 drivers/net/usb/smsc95xx.c + +--- a/drivers/net/usb/smsc95xx.c ++++ b/drivers/net/usb/smsc95xx.c +@@ -1841,7 +1841,6 @@ static int smsc95xx_rx_fixup(struct usbn + if (dev->net->features & NETIF_F_RXCSUM) + smsc95xx_rx_csum_offload(skb); + skb_trim(skb, skb->len - 4); /* remove fcs */ +- skb->truesize = size + sizeof(struct sk_buff); + + return 1; + } +@@ -1859,7 +1858,6 @@ static int smsc95xx_rx_fixup(struct usbn + if (dev->net->features & NETIF_F_RXCSUM) + smsc95xx_rx_csum_offload(ax_skb); + skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ +- ax_skb->truesize = size + sizeof(struct sk_buff); + + usbnet_skb_return(dev, ax_skb); + } diff --git a/target/linux/brcm2708/patches-4.1/0065-smsc95xx-Disable-turbo-mode-by-default.patch b/target/linux/brcm2708/patches-4.1/0065-smsc95xx-Disable-turbo-mode-by-default.patch new file mode 100644 index 0000000..4299574 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0065-smsc95xx-Disable-turbo-mode-by-default.patch @@ -0,0 +1,20 @@ +From f55a40b960df22fd85166f0059039415a70893d7 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Fri, 17 Apr 2015 16:58:45 +0100 +Subject: [PATCH 065/203] smsc95xx: Disable turbo mode by default + +--- + drivers/net/usb/smsc95xx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/usb/smsc95xx.c ++++ b/drivers/net/usb/smsc95xx.c +@@ -71,7 +71,7 @@ struct smsc95xx_priv { + u8 suspend_flags; + }; + +-static bool turbo_mode = true; ++static bool turbo_mode = false; + module_param(turbo_mode, bool, 0644); + MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); + diff --git a/target/linux/brcm2708/patches-4.1/0066-Add-blk_pos-parameter-to-mmc-multi_io_quirk-callback.patch b/target/linux/brcm2708/patches-4.1/0066-Add-blk_pos-parameter-to-mmc-multi_io_quirk-callback.patch new file mode 100644 index 0000000..1e9bee6 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0066-Add-blk_pos-parameter-to-mmc-multi_io_quirk-callback.patch @@ -0,0 +1,75 @@ +From 96d14e8df0b8209526f76f890404151d58554ada Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 17 Apr 2015 19:30:22 +0100 +Subject: [PATCH 066/203] Add blk_pos parameter to mmc multi_io_quirk callback + +--- + drivers/mmc/card/block.c | 1 + + drivers/mmc/host/omap_hsmmc.c | 4 +++- + drivers/mmc/host/sh_mobile_sdhi.c | 4 +++- + drivers/mmc/host/tmio_mmc_pio.c | 4 +++- + include/linux/mmc/host.h | 4 +++- + 5 files changed, 13 insertions(+), 4 deletions(-) + +--- a/drivers/mmc/card/block.c ++++ b/drivers/mmc/card/block.c +@@ -1415,6 +1415,7 @@ static void mmc_blk_rw_rq_prep(struct mm + brq->data.blocks = card->host->ops->multi_io_quirk(card, + (rq_data_dir(req) == READ) ? + MMC_DATA_READ : MMC_DATA_WRITE, ++ blk_rq_pos(req), + brq->data.blocks); + } + +--- a/drivers/mmc/host/omap_hsmmc.c ++++ b/drivers/mmc/host/omap_hsmmc.c +@@ -1749,7 +1749,9 @@ static void omap_hsmmc_conf_bus_power(st + } + + static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, +- unsigned int direction, int blk_size) ++ unsigned int direction, ++ u32 blk_pos, ++ int blk_size) + { + /* This controller can't do multiblock reads due to hw bugs */ + if (direction == MMC_DATA_READ) +--- a/drivers/mmc/host/sh_mobile_sdhi.c ++++ b/drivers/mmc/host/sh_mobile_sdhi.c +@@ -170,7 +170,9 @@ static int sh_mobile_sdhi_write16_hook(s + } + + static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card, +- unsigned int direction, int blk_size) ++ unsigned int direction, ++ u32 blk_pos, ++ int blk_size) + { + /* + * In Renesas controllers, when performing a +--- a/drivers/mmc/host/tmio_mmc_pio.c ++++ b/drivers/mmc/host/tmio_mmc_pio.c +@@ -1001,7 +1001,9 @@ static int tmio_mmc_get_ro(struct mmc_ho + } + + static int tmio_multi_io_quirk(struct mmc_card *card, +- unsigned int direction, int blk_size) ++ unsigned int direction, ++ u32 blk_pos, ++ int blk_size) + { + struct tmio_mmc_host *host = mmc_priv(card->host); + +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -140,7 +140,9 @@ struct mmc_host_ops { + * I/O. Returns the number of supported blocks for the request. + */ + int (*multi_io_quirk)(struct mmc_card *card, +- unsigned int direction, int blk_size); ++ unsigned int direction, ++ u32 blk_pos, ++ int blk_size); + }; + + struct mmc_card; diff --git a/target/linux/brcm2708/patches-4.1/0067-bcm2835-bcm2835_defconfig.patch b/target/linux/brcm2708/patches-4.1/0067-bcm2835-bcm2835_defconfig.patch new file mode 100644 index 0000000..5cebdc4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0067-bcm2835-bcm2835_defconfig.patch @@ -0,0 +1,1330 @@ +From 73e03bc0ad554dbd4e4d040d90e46f3d9d31d3c4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Wed, 29 Apr 2015 17:24:02 +0200 +Subject: [PATCH 067/203] bcm2835: bcm2835_defconfig +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Some options in bcm2835_defconfig are now the default and +some have changed. Update to keep functionality. + +No longer available: SCSI_MULTI_LUN and RESOURCE_COUNTERS. + +Signed-off-by: Noralf Trønnes + +bcm2835: bcm2835_defconfig enable MMC_BCM2835 + +Enable the downstream bcm2835-mmc driver and DMA support. + +Signed-off-by: Noralf Trønnes + +bcm2835: bcm2835_defconfig enable BCM2708_MBOX + +Enable the mailbox driver. + +Signed-off-by: Noralf Trønnes + +bcm2835: bcm2835_defconfig use FB_BCM2708 + +Enable the bcm2708 framebuffer driver. +Disable the simple framebuffer driver, which matches the +device handed over by u-boot. + +Signed-off-by: Noralf Trønnes + +bcm2835: Merge bcm2835_defconfig with bcmrpi_defconfig + +These commands where used to make this commit: + +./scripts/diffconfig -m arch/arm/configs/bcm2835_defconfig arch/arm/configs/bcmrpi_defconfig > merge.cfg + +cat << EOF > filter +CONFIG_ARCH_BCM2708 +CONFIG_BCM2708_DT +CONFIG_ARM_PATCH_PHYS_VIRT +CONFIG_PHYS_OFFSET +CONFIG_CMDLINE +CONFIG_BCM2708_WDT +CONFIG_HW_RANDOM_BCM2708 +CONFIG_I2C_BCM2708 +CONFIG_SPI_BCM2708 +CONFIG_SND_BCM2708_SOC_I2S +CONFIG_USB_DWCOTG +CONFIG_LIRC_RPI +EOF + +grep -F -v -f filter merge.cfg > filtered.cfg + +cat << EOF > added.cfg +CONFIG_WATCHDOG=y +CONFIG_BCM2835_WDT=y +CONFIG_MISC_FILESYSTEMS=y +CONFIG_SND_BCM2835_SOC_I2S=m +EOF + +ARCH=arm scripts/kconfig/merge_config.sh arch/arm/configs/bcm2835_defconfig filtered.cfg added.cfg +ARCH=arm make oldconfig + +ARCH=arm make savedefconfig +cp defconfig arch/arm/configs/bcm2835_defconfig + +rm merge.cfg filter filtered.cfg added.cfg defconfig + +ARCH=arm make bcm2835_defconfig +ARCH=arm make oldconfig + +Signed-off-by: Noralf Trønnes +--- + arch/arm/configs/bcm2835_defconfig | 1132 +++++++++++++++++++++++++++++++++++- + 1 file changed, 1107 insertions(+), 25 deletions(-) + +--- a/arch/arm/configs/bcm2835_defconfig ++++ b/arch/arm/configs/bcm2835_defconfig +@@ -1,105 +1,1071 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y + CONFIG_FHANDLE=y + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_BSD_PROCESS_ACCT=y + CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_IKCONFIG=m ++CONFIG_IKCONFIG_PROC=y + CONFIG_LOG_BUF_SHIFT=18 + CONFIG_CGROUP_FREEZER=y + CONFIG_CGROUP_DEVICE=y + CONFIG_CPUSETS=y + CONFIG_CGROUP_CPUACCT=y +-CONFIG_RESOURCE_COUNTERS=y ++CONFIG_MEMCG=y + CONFIG_CGROUP_PERF=y + CONFIG_CFS_BANDWIDTH=y + CONFIG_RT_GROUP_SCHED=y ++CONFIG_BLK_CGROUP=y + CONFIG_NAMESPACES=y + CONFIG_SCHED_AUTOGROUP=y +-CONFIG_RELAY=y + CONFIG_BLK_DEV_INITRD=y +-CONFIG_RD_BZIP2=y +-CONFIG_RD_LZMA=y +-CONFIG_RD_XZ=y +-CONFIG_RD_LZO=y + CONFIG_CC_OPTIMIZE_FOR_SIZE=y +-CONFIG_KALLSYMS_ALL=y + CONFIG_EMBEDDED=y + # CONFIG_COMPAT_BRK is not set + CONFIG_PROFILING=y +-CONFIG_OPROFILE=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y + CONFIG_JUMP_LABEL=y ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_CFQ_GROUP_IOSCHED=y + CONFIG_ARCH_MULTI_V6=y + # CONFIG_ARCH_MULTI_V7 is not set + CONFIG_ARCH_BCM=y + CONFIG_ARCH_BCM2835=y +-CONFIG_PREEMPT_VOLUNTARY=y ++CONFIG_PREEMPT=y + CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y + CONFIG_KSM=y + CONFIG_CLEANCACHE=y ++CONFIG_FRONTSWAP=y ++CONFIG_CMA=y ++CONFIG_UACCESS_WITH_MEMCPY=y + CONFIG_SECCOMP=y +-CONFIG_CC_STACKPROTECTOR=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_KEXEC=y + CONFIG_CRASH_DUMP=y ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=m ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + CONFIG_VFP=y + # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_BINFMT_MISC=m + # CONFIG_SUSPEND is not set + CONFIG_NET=y + CONFIG_PACKET=y + CONFIG_UNIX=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=m + CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE_DEMUX=m ++CONFIG_NET_IPGRE=m ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=m ++CONFIG_INET_LRO=m ++CONFIG_INET_DIAG=m ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_TUNNEL=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_IPV6_MROUTE=y ++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IPV6_PIMSM_V2=y + CONFIG_NETWORK_SECMARK=y + CONFIG_NETFILTER=y +-CONFIG_CFG80211=y +-CONFIG_MAC80211=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_CLUSTERIP=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_IP6_NF_NAT=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_ATM=m ++CONFIG_L2TP=m ++CONFIG_L2TP_V3=y ++CONFIG_L2TP_IP=m ++CONFIG_L2TP_ETH=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_ATALK=m ++CONFIG_6LOWPAN=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_BATMAN_ADV=m ++CONFIG_OPENVSWITCH=m ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++CONFIG_CAN=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRNET=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_6LOWPAN=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_BT_WILINK=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m + CONFIG_DEVTMPFS=y + CONFIG_DEVTMPFS_MOUNT=y + # CONFIG_STANDALONE is not set ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_DRBD=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_ATA_OVER_ETH=m ++CONFIG_EEPROM_AT24=m + CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=y +-CONFIG_SCSI_MULTI_LUN=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_CHR_DEV_SG=m + CONFIG_SCSI_CONSTANTS=y + CONFIG_SCSI_SCAN_ASYNC=y ++CONFIG_SCSI_ISCSI_ATTRS=y ++CONFIG_ISCSI_TCP=m ++CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_MD=y ++CONFIG_MD_LINEAR=m ++CONFIG_MD_RAID0=m ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_DELAY=m + CONFIG_NETDEVICES=y ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++CONFIG_IFB=m ++CONFIG_MACVLAN=m ++CONFIG_NETCONSOLE=m ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_ENC28J60=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=m + CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_AX88179_178A=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_CDC_NCM=m ++CONFIG_USB_NET_HUAWEI_CDC_NCM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SR9700=m ++CONFIG_USB_NET_SR9800=m ++CONFIG_USB_NET_SMSC75XX=m + CONFIG_USB_NET_SMSC95XX=y +-CONFIG_ZD1211RW=y +-CONFIG_INPUT_EVDEV=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_CARDS=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_USB=m ++CONFIG_AR5523=m ++CONFIG_B43=m ++# CONFIG_B43_PHY_N is not set ++CONFIG_B43LEGACY=m ++CONFIG_BRCMFMAC=m ++CONFIG_BRCMFMAC_USB=y ++CONFIG_HOSTAP=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT3573=y ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_RT55XX=y ++CONFIG_RT2800USB_UNKNOWN=y ++CONFIG_RTL8192CU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_INPUT_POLLDEV=m ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=m ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=y ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_ADS7846=m ++CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y + # CONFIG_LEGACY_PTYS is not set + # CONFIG_DEVKMEM is not set + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y + CONFIG_TTY_PRINTK=y ++CONFIG_HW_RANDOM=y ++CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_RAW_DRIVER=y ++CONFIG_BRCM_CHAR_DRIVERS=y ++CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VC_SM=y + CONFIG_I2C=y +-CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_CHARDEV=m + CONFIG_I2C_BCM2835=y + CONFIG_SPI=y +-CONFIG_SPI_BCM2835=y ++CONFIG_SPI_BCM2835=m ++CONFIG_SPI_SPIDEV=y ++CONFIG_PPS=m ++CONFIG_PPS_CLIENT_LDISC=m ++CONFIG_PPS_CLIENT_GPIO=m + CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_ARIZONA=m ++CONFIG_GPIO_STMPE=y ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2413=m ++CONFIG_W1_SLAVE_DS2406=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2760=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_DS2781=m ++CONFIG_W1_SLAVE_DS28E04=m ++CONFIG_W1_SLAVE_BQ27000=m ++CONFIG_BATTERY_DS2760=m + # CONFIG_HWMON is not set ++CONFIG_THERMAL=y ++CONFIG_THERMAL_BCM2835=y ++CONFIG_WATCHDOG=y ++CONFIG_BCM2835_WDT=y ++CONFIG_UCB1400_CORE=m ++CONFIG_MFD_STMPE=y ++CONFIG_STMPE_SPI=y ++CONFIG_MFD_ARIZONA_I2C=m ++CONFIG_MFD_ARIZONA_SPI=m ++CONFIG_MFD_WM5102=y ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_RC_SUPPORT=y ++CONFIG_MEDIA_CONTROLLER=y ++CONFIG_LIRC=m ++CONFIG_RC_DEVICES=y ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_IR_GPIO_CIR=m ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_DTCS033=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STK1135=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_VIDEO_STK1160_AC97=y ++CONFIG_VIDEO_GO7007=m ++CONFIG_VIDEO_GO7007_USB=m ++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_AU0828_RC=y ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_TM6000=m ++CONFIG_VIDEO_TM6000_ALSA=m ++CONFIG_VIDEO_TM6000_DVB=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_DVB_USB_DVBSKY=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_DVB_AS102=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_V4L2=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_BCM2835=y ++CONFIG_VIDEO_BCM2835_MMAL=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_I2C_SI470X=m ++CONFIG_RADIO_SI4713=m ++CONFIG_I2C_SI4713=m ++CONFIG_USB_MR800=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_RADIO_WL128X=m ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_TVP5150=m ++CONFIG_VIDEO_TW2804=m ++CONFIG_VIDEO_TW9903=m ++CONFIG_VIDEO_TW9906=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_MT9V011=m + CONFIG_FB=y +-CONFIG_FB_SIMPLE=y ++CONFIG_FB_BCM2708=y ++CONFIG_FB_SSD1307=m ++# CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_GPIO=m + CONFIG_FRAMEBUFFER_CONSOLE=y + CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_SOC=m ++CONFIG_SND_BCM2835_SOC_I2S=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m ++CONFIG_SND_BCM2708_SOC_RPI_DAC=m ++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_SIMPLE_CARD=m ++CONFIG_SOUND_PRIME=m ++CONFIG_HIDRAW=y ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_XINMO=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y + CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_PRINTER=m + CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USBIP_CORE=m ++CONFIG_USBIP_VHCI_HCD=m ++CONFIG_USBIP_HOST=m ++CONFIG_USB_DWC2=y ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_XSENS_MT=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m + CONFIG_MMC=y ++CONFIG_MMC_BLOCK_MINORS=32 ++CONFIG_MMC_BCM2835=y ++CONFIG_MMC_BCM2835_DMA=y ++CONFIG_MMC_BCM2835_SDHOST=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_PLTFM=y + CONFIG_MMC_SDHCI_BCM2835=y ++CONFIG_MMC_SPI=m ++CONFIG_LEDS_CLASS=y + CONFIG_LEDS_GPIO=y + CONFIG_LEDS_TRIGGER_TIMER=y + CONFIG_LEDS_TRIGGER_ONESHOT=y + CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y + CONFIG_LEDS_TRIGGER_CPU=y + CONFIG_LEDS_TRIGGER_GPIO=y + CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +-CONFIG_LEDS_TRIGGER_TRANSIENT=y +-CONFIG_LEDS_TRIGGER_CAMERA=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=m ++CONFIG_LEDS_TRIGGER_CAMERA=m ++CONFIG_LEDS_TRIGGER_INPUT=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_HCTOSYS is not set ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_ISL12057=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_DS3234=m ++CONFIG_RTC_DRV_PCF2123=m ++CONFIG_RTC_DRV_RX4581=m ++CONFIG_DMADEVICES=y ++CONFIG_DMA_BCM2708=y ++CONFIG_UIO=m ++CONFIG_UIO_PDRV_GENIRQ=m + CONFIG_STAGING=y +-CONFIG_USB_DWC2=y +-CONFIG_USB_DWC2_HOST=y ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_R8188EU=m ++CONFIG_R8723AU=m ++CONFIG_VT6656=m ++CONFIG_SPEAKUP=m ++CONFIG_SPEAKUP_SYNTH_SOFT=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_LIRC_STAGING=y ++CONFIG_LIRC_IMON=m ++CONFIG_LIRC_SASEM=m ++CONFIG_LIRC_SERIAL=m ++CONFIG_FB_TFT=m ++CONFIG_FB_TFT_AGM1264K_FL=m ++CONFIG_FB_TFT_BD663474=m ++CONFIG_FB_TFT_HX8340BN=m ++CONFIG_FB_TFT_HX8347D=m ++CONFIG_FB_TFT_HX8353D=m ++CONFIG_FB_TFT_ILI9320=m ++CONFIG_FB_TFT_ILI9325=m ++CONFIG_FB_TFT_ILI9340=m ++CONFIG_FB_TFT_ILI9341=m ++CONFIG_FB_TFT_ILI9481=m ++CONFIG_FB_TFT_ILI9486=m ++CONFIG_FB_TFT_PCD8544=m ++CONFIG_FB_TFT_RA8875=m ++CONFIG_FB_TFT_S6D02A1=m ++CONFIG_FB_TFT_S6D1121=m ++CONFIG_FB_TFT_SSD1289=m ++CONFIG_FB_TFT_SSD1306=m ++CONFIG_FB_TFT_SSD1331=m ++CONFIG_FB_TFT_SSD1351=m ++CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_TINYLCD=m ++CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1701=m ++CONFIG_FB_TFT_UPD161704=m ++CONFIG_FB_TFT_WATTEROTT=m ++CONFIG_FB_FLEX=m ++CONFIG_FB_TFT_FBTFT_DEVICE=m ++CONFIG_MAILBOX=y ++CONFIG_BCM2708_MBOX=y + # CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXTCON=m ++CONFIG_EXTCON_ARIZONA=m + CONFIG_EXT2_FS=y + CONFIG_EXT2_FS_XATTR=y + CONFIG_EXT2_FS_POSIX_ACL=y +@@ -107,18 +1073,110 @@ CONFIG_EXT3_FS=y + CONFIG_EXT3_FS_POSIX_ACL=y + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m + CONFIG_FANOTIFY=y ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m + CONFIG_MSDOS_FS=y + CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++CONFIG_NTFS_RW=y + CONFIG_TMPFS=y + CONFIG_TMPFS_POSIX_ACL=y +-# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_F2FS_FS=y + CONFIG_NFS_FS=y +-CONFIG_NFSD=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_SWAP=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_NLS_DEFAULT="utf8" + CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m + CONFIG_NLS_ASCII=y +-CONFIG_NLS_ISO8859_1=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m + CONFIG_NLS_UTF8=y ++CONFIG_DLM=m + CONFIG_PRINTK_TIME=y + CONFIG_BOOT_PRINTK_DELAY=y + CONFIG_DYNAMIC_DEBUG=y +@@ -128,14 +1186,38 @@ CONFIG_DEBUG_INFO=y + CONFIG_UNUSED_SYMBOLS=y + CONFIG_DEBUG_MEMORY_INIT=y + CONFIG_LOCKUP_DETECTOR=y ++CONFIG_TIMER_STATS=y ++# CONFIG_DEBUG_PREEMPT is not set ++CONFIG_LATENCYTOP=y ++CONFIG_IRQSOFF_TRACER=y + CONFIG_SCHED_TRACER=y + CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++# CONFIG_KPROBE_EVENT is not set + CONFIG_FUNCTION_PROFILER=y + CONFIG_TEST_KSTRTOX=y + CONFIG_KGDB=y + CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y + CONFIG_STRICT_DEVMEM=y + CONFIG_DEBUG_LL=y + CONFIG_EARLY_PRINTK=y ++CONFIG_CRYPTO_USER=m ++CONFIG_CRYPTO_CRYPTD=m ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTS=m ++CONFIG_CRYPTO_XTS=m ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_SHA1_ARM=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_AES_ARM=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_HW is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y + # CONFIG_XZ_DEC_ARM is not set + # CONFIG_XZ_DEC_ARMTHUMB is not set diff --git a/target/linux/brcm2708/patches-4.1/0068-BCM270x_DT-Add-mailbox-bcm2708-vcio.patch b/target/linux/brcm2708/patches-4.1/0068-BCM270x_DT-Add-mailbox-bcm2708-vcio.patch new file mode 100644 index 0000000..83d5197 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0068-BCM270x_DT-Add-mailbox-bcm2708-vcio.patch @@ -0,0 +1,39 @@ +From edd20d21ede3ec226ef4b93a844e75a758a28daa Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 1 May 2015 23:00:15 +0200 +Subject: [PATCH 068/203] BCM270x_DT: Add mailbox bcm2708-vcio +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add bcm2708-vcio to Device Tree and don't add the +platform device when booting in DT mode. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/mach-bcm2708/bcm2708.c | 2 +- + arch/arm/mach-bcm2709/bcm2709.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -870,7 +870,7 @@ void __init bcm2708_init(void) + bcm2708_dt_init(); + + bcm_register_device_dt(&bcm2708_dmaengine_device); +- bcm_register_device(&bcm2708_vcio_device); ++ bcm_register_device_dt(&bcm2708_vcio_device); + bcm_register_device_dt(&bcm2708_vchiq_device); + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -890,7 +890,7 @@ void __init bcm2709_init(void) + bcm2709_dt_init(); + + bcm_register_device_dt(&bcm2708_dmaengine_device); +- bcm_register_device(&bcm2708_vcio_device); ++ bcm_register_device_dt(&bcm2708_vcio_device); + bcm_register_device_dt(&bcm2708_vchiq_device); + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); diff --git a/target/linux/brcm2708/patches-4.1/0069-rpi-ft5406-Add-touchscreen-driver-for-pi-LCD-display.patch b/target/linux/brcm2708/patches-4.1/0069-rpi-ft5406-Add-touchscreen-driver-for-pi-LCD-display.patch new file mode 100644 index 0000000..d13607a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0069-rpi-ft5406-Add-touchscreen-driver-for-pi-LCD-display.patch @@ -0,0 +1,310 @@ +From 04e299dffec7ed7c7d88fe8568a6833005dd9558 Mon Sep 17 00:00:00 2001 +From: Gordon Hollingworth +Date: Tue, 12 May 2015 14:47:56 +0100 +Subject: [PATCH 069/203] rpi-ft5406: Add touchscreen driver for pi LCD display + +--- + drivers/input/touchscreen/Kconfig | 7 + + drivers/input/touchscreen/Makefile | 1 + + drivers/input/touchscreen/rpi-ft5406.c | 258 ++++++++++++++++++++++++++ + include/linux/platform_data/mailbox-bcm2708.h | 1 + + 4 files changed, 267 insertions(+) + create mode 100644 drivers/input/touchscreen/rpi-ft5406.c + +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -583,6 +583,13 @@ config TOUCHSCREEN_EDT_FT5X06 + To compile this driver as a module, choose M here: the + module will be called edt-ft5x06. + ++config TOUCHSCREEN_RPI_FT5406 ++ tristate "Raspberry Pi FT5406 driver" ++ depends on ARCH_BCM2708 || ARCH_BCM2709 ++ help ++ Say Y here to enable the Raspberry Pi memory based FT5406 device ++ ++ + config TOUCHSCREEN_MIGOR + tristate "Renesas MIGO-R touchscreen" + depends on SH_MIGOR && I2C +--- a/drivers/input/touchscreen/Makefile ++++ b/drivers/input/touchscreen/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_TOUCHSCREEN_DA9034) += da90 + obj-$(CONFIG_TOUCHSCREEN_DA9052) += da9052_tsi.o + obj-$(CONFIG_TOUCHSCREEN_DYNAPRO) += dynapro.o + obj-$(CONFIG_TOUCHSCREEN_EDT_FT5X06) += edt-ft5x06.o ++obj-$(CONFIG_TOUCHSCREEN_RPI_FT5406) += rpi-ft5406.o + obj-$(CONFIG_TOUCHSCREEN_HAMPSHIRE) += hampshire.o + obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o + obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o +--- /dev/null ++++ b/drivers/input/touchscreen/rpi-ft5406.c +@@ -0,0 +1,258 @@ ++/* ++ * Driver for memory based ft5406 touchscreen ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MAXIMUM_SUPPORTED_POINTS 10 ++struct ft5406_regs { ++ uint8_t device_mode; ++ uint8_t gesture_id; ++ uint8_t num_points; ++ struct ft5406_touch { ++ uint8_t xh; ++ uint8_t xl; ++ uint8_t yh; ++ uint8_t yl; ++ uint8_t res1; ++ uint8_t res2; ++ } point[MAXIMUM_SUPPORTED_POINTS]; ++}; ++ ++#define SCREEN_WIDTH 800 ++#define SCREEN_HEIGHT 480 ++ ++struct ft5406 { ++ struct platform_device * pdev; ++ struct input_dev * input_dev; ++ void __iomem * ts_base; ++ struct ft5406_regs * regs; ++ struct task_struct * thread; ++}; ++ ++ ++/* tag part of the message */ ++struct vc_msg_tag { ++ uint32_t tag_id; /* the message id */ ++ uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */ ++ uint32_t data_size; /* amount of data being sent or received */ ++ uint32_t val; /* data buffer */ ++}; ++ ++/* message structure to be sent to videocore */ ++struct vc_msg { ++ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ ++ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ ++ struct vc_msg_tag tag; /* the tag structure above to make */ ++ uint32_t end_tag; /* an end identifier, should be set to NULL */ ++}; ++ ++/* Thread to poll for touchscreen events ++ * ++ * This thread polls the memory based register copy of the ft5406 registers ++ * using the number of points register to know whether the copy has been ++ * updated (we write 99 to the memory copy, the GPU will write between ++ * 0 - 10 points) ++ */ ++static int ft5406_thread(void *arg) ++{ ++ struct ft5406 *ts = (struct ft5406 *) arg; ++ struct ft5406_regs regs; ++ int known_ids = 0; ++ ++ while(!kthread_should_stop()) ++ { ++ // 60fps polling ++ msleep(17); ++ memcpy_fromio(®s, ts->regs, sizeof(*ts->regs)); ++ writel(99, &ts->regs->num_points); ++ // Do not output if theres no new information (num_points is 99) ++ // or we have no touch points and don't need to release any ++ if(!(regs.num_points == 99 || (regs.num_points == 0 && known_ids == 0))) ++ { ++ int i; ++ int modified_ids = 0, released_ids; ++ for(i = 0; i < regs.num_points; i++) ++ { ++ int x = (((int) regs.point[i].xh & 0xf) << 8) + regs.point[i].xl; ++ int y = (((int) regs.point[i].yh & 0xf) << 8) + regs.point[i].yl; ++ int touchid = (regs.point[i].yh >> 4) & 0xf; ++ ++ modified_ids |= 1 << touchid; ++ ++ if(!((1 << touchid) & known_ids)) ++ dev_dbg(&ts->pdev->dev, "x = %d, y = %d, touchid = %d\n", x, y, touchid); ++ ++ input_mt_slot(ts->input_dev, touchid); ++ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 1); ++ ++ input_report_abs(ts->input_dev, ABS_MT_POSITION_X, x); ++ input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, y); ++ ++ } ++ ++ released_ids = known_ids & ~modified_ids; ++ for(i = 0; released_ids && i < MAXIMUM_SUPPORTED_POINTS; i++) ++ { ++ if(released_ids & (1<pdev->dev, "Released %d, known = %x modified = %x\n", i, known_ids, modified_ids); ++ input_mt_slot(ts->input_dev, i); ++ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 0); ++ modified_ids &= ~(1 << i); ++ } ++ } ++ known_ids = modified_ids; ++ ++ input_mt_report_pointer_emulation(ts->input_dev, true); ++ input_sync(ts->input_dev); ++ } ++ ++ } ++ ++ return 0; ++} ++ ++static int ft5406_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct input_dev * input_dev = input_allocate_device(); ++ struct vc_msg request; ++ struct ft5406 * ts; ++ ++ dev_info(&pdev->dev, "Probing device\n"); ++ ++ ts = kzalloc(sizeof(struct ft5406), GFP_KERNEL); ++ ++ if (!ts || !input_dev) { ++ ret = -ENOMEM; ++ dev_err(&pdev->dev, "Failed to allocate memory\n"); ++ return ret; ++ } ++ ts->input_dev = input_dev; ++ platform_set_drvdata(pdev, ts); ++ ts->pdev = pdev; ++ ++ input_dev->name = "FT5406 memory based driver"; ++ ++ __set_bit(EV_KEY, input_dev->evbit); ++ __set_bit(EV_SYN, input_dev->evbit); ++ __set_bit(EV_ABS, input_dev->evbit); ++ ++ input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0, ++ SCREEN_WIDTH, 0, 0); ++ input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0, ++ SCREEN_HEIGHT, 0, 0); ++ ++ input_mt_init_slots(input_dev, MAXIMUM_SUPPORTED_POINTS, INPUT_MT_DIRECT); ++ ++ input_set_drvdata(input_dev, ts); ++ ++ ret = input_register_device(input_dev); ++ if (ret) { ++ dev_err(&pdev->dev, "could not register input device, %d\n", ++ ret); ++ return ret; ++ } ++ ++ memset(&request, 0, sizeof request); ++ ++ request.msg_size = sizeof request; ++ request.request_code = VCMSG_PROCESS_REQUEST; ++ request.tag.tag_id = VCMSG_GET_TOUCHBUF; ++ request.tag.buffer_size = 4; ++ request.tag.data_size = 4; ++ ++ bcm_mailbox_property(&request, sizeof(request)); ++ ++ if(request.request_code == VCMSG_REQUEST_SUCCESSFUL) ++ { ++ dev_dbg(&pdev->dev, "Got TS buffer 0x%x\n", request.tag.val); ++ } ++ else ++ { ++ input_unregister_device(input_dev); ++ kzfree(ts); ++ return -1; ++ } ++ ++ // mmap the physical memory ++ request.tag.val &= ~0xc0000000; ++ ts->ts_base = ioremap(request.tag.val, sizeof(*ts->regs)); ++ if(ts->ts_base == NULL) ++ { ++ dev_err(&pdev->dev, "Failed to map physical address\n"); ++ input_unregister_device(input_dev); ++ kzfree(ts); ++ return -1; ++ } ++ ++ ts->regs = (struct ft5406_regs *) ts->ts_base; ++ ++ // create thread to poll the touch events ++ ts->thread = kthread_run(ft5406_thread, ts, "ft5406"); ++ if(ts->thread == NULL) ++ { ++ dev_err(&pdev->dev, "Failed to create kernel thread"); ++ iounmap(ts->ts_base); ++ input_unregister_device(input_dev); ++ kzfree(ts); ++ } ++ ++ return 0; ++} ++ ++static int ft5406_remove(struct platform_device *pdev) ++{ ++ struct ft5406 *ts = (struct ft5406 *) platform_get_drvdata(pdev); ++ ++ dev_info(&pdev->dev, "Removing rpi-ft5406\n"); ++ ++ kthread_stop(ts->thread); ++ iounmap(ts->ts_base); ++ input_unregister_device(ts->input_dev); ++ kzfree(ts); ++ ++ return 0; ++} ++ ++static const struct of_device_id ft5406_match[] = { ++ { .compatible = "rpi,rpi-ft5406", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ft5406_match); ++ ++static struct platform_driver ft5406_driver = { ++ .driver = { ++ .name = "rpi-ft5406", ++ .owner = THIS_MODULE, ++ .of_match_table = ft5406_match, ++ }, ++ .probe = ft5406_probe, ++ .remove = ft5406_remove, ++}; ++ ++module_platform_driver(ft5406_driver); ++ ++MODULE_AUTHOR("Gordon Hollingworth"); ++MODULE_DESCRIPTION("Touchscreen driver for memory based FT5406"); ++MODULE_LICENSE("GPL"); +--- a/include/linux/platform_data/mailbox-bcm2708.h ++++ b/include/linux/platform_data/mailbox-bcm2708.h +@@ -115,6 +115,7 @@ enum { + VCMSG_SET_TRANSFORM = 0x0004800d, + VCMSG_TST_VSYNC = 0x0004400e, + VCMSG_SET_VSYNC = 0x0004800e, ++ VCMSG_GET_TOUCHBUF = 0x0004000f, + VCMSG_SET_CURSOR_INFO = 0x00008010, + VCMSG_SET_CURSOR_STATE = 0x00008011, + }; diff --git a/target/linux/brcm2708/patches-4.1/0070-Improve-__copy_to_user-and-__copy_from_user-performa.patch b/target/linux/brcm2708/patches-4.1/0070-Improve-__copy_to_user-and-__copy_from_user-performa.patch new file mode 100644 index 0000000..3e12a13 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0070-Improve-__copy_to_user-and-__copy_from_user-performa.patch @@ -0,0 +1,1496 @@ +From 5929da3d7ce831709884de3e3564de028fafc28c Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 13 Oct 2014 11:47:53 +0100 +Subject: [PATCH 070/203] Improve __copy_to_user and __copy_from_user + performance + +Provide a __copy_from_user that uses memcpy. On BCM2708, use +optimised memcpy/memmove/memcmp/memset implementations. +--- + arch/arm/include/asm/string.h | 5 + + arch/arm/include/asm/uaccess.h | 1 + + arch/arm/lib/Makefile | 15 +- + arch/arm/lib/arm-mem.h | 159 ++++++++++++ + arch/arm/lib/copy_from_user.S | 4 +- + arch/arm/lib/exports_rpi.c | 37 +++ + arch/arm/lib/memcmp_rpi.S | 285 +++++++++++++++++++++ + arch/arm/lib/memcpy_rpi.S | 59 +++++ + arch/arm/lib/memcpymove.h | 506 +++++++++++++++++++++++++++++++++++++ + arch/arm/lib/memmove_rpi.S | 61 +++++ + arch/arm/lib/memset_rpi.S | 121 +++++++++ + arch/arm/lib/uaccess_with_memcpy.c | 112 +++++++- + 12 files changed, 1359 insertions(+), 6 deletions(-) + create mode 100644 arch/arm/lib/arm-mem.h + create mode 100644 arch/arm/lib/exports_rpi.c + create mode 100644 arch/arm/lib/memcmp_rpi.S + create mode 100644 arch/arm/lib/memcpy_rpi.S + create mode 100644 arch/arm/lib/memcpymove.h + create mode 100644 arch/arm/lib/memmove_rpi.S + create mode 100644 arch/arm/lib/memset_rpi.S + +--- a/arch/arm/include/asm/string.h ++++ b/arch/arm/include/asm/string.h +@@ -24,6 +24,11 @@ extern void * memchr(const void *, int, + #define __HAVE_ARCH_MEMSET + extern void * memset(void *, int, __kernel_size_t); + ++#ifdef CONFIG_MACH_BCM2708 ++#define __HAVE_ARCH_MEMCMP ++extern int memcmp(const void *, const void *, size_t); ++#endif ++ + extern void __memzero(void *ptr, __kernel_size_t n); + + #define memset(p,v,n) \ +--- a/arch/arm/include/asm/uaccess.h ++++ b/arch/arm/include/asm/uaccess.h +@@ -475,6 +475,7 @@ do { \ + + #ifdef CONFIG_MMU + extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); ++extern unsigned long __must_check __copy_from_user_std(void *to, const void __user *from, unsigned long n); + extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); + extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n); + extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +--- a/arch/arm/lib/Makefile ++++ b/arch/arm/lib/Makefile +@@ -6,9 +6,8 @@ + + lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ + csumpartialcopy.o csumpartialcopyuser.o clearbit.o \ +- delay.o delay-loop.o findbit.o memchr.o memcpy.o \ +- memmove.o memset.o memzero.o setbit.o \ +- strchr.o strrchr.o \ ++ delay.o delay-loop.o findbit.o memchr.o memzero.o \ ++ setbit.o strchr.o strrchr.o \ + testchangebit.o testclearbit.o testsetbit.o \ + ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ + ucmpdi2.o lib1funcs.o div64.o \ +@@ -18,6 +17,16 @@ lib-y := backtrace.o changebit.o csumip + mmu-y := clear_user.o copy_page.o getuser.o putuser.o \ + copy_from_user.o copy_to_user.o + ++# Choose optimised implementations for Raspberry Pi ++ifeq ($(CONFIG_MACH_BCM2708),y) ++ CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600 ++ CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672 ++ obj-$(CONFIG_MODULES) += exports_rpi.o ++ lib-y += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o ++else ++ lib-y += memcpy.o memmove.o memset.o ++endif ++ + # using lib_ here won't override already available weak symbols + obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o + +--- /dev/null ++++ b/arch/arm/lib/arm-mem.h +@@ -0,0 +1,159 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++.macro myfunc fname ++ .func fname ++ .global fname ++fname: ++.endm ++ ++.macro preload_leading_step1 backwards, ptr, base ++/* If the destination is already 16-byte aligned, then we need to preload ++ * between 0 and prefetch_distance (inclusive) cache lines ahead so there ++ * are no gaps when the inner loop starts. ++ */ ++ .if backwards ++ sub ptr, base, #1 ++ bic ptr, ptr, #31 ++ .else ++ bic ptr, base, #31 ++ .endif ++ .set OFFSET, 0 ++ .rept prefetch_distance+1 ++ pld [ptr, #OFFSET] ++ .if backwards ++ .set OFFSET, OFFSET-32 ++ .else ++ .set OFFSET, OFFSET+32 ++ .endif ++ .endr ++.endm ++ ++.macro preload_leading_step2 backwards, ptr, base, leading_bytes, tmp ++/* However, if the destination is not 16-byte aligned, we may need to ++ * preload one more cache line than that. The question we need to ask is: ++ * are the leading bytes more than the amount by which the source ++ * pointer will be rounded down for preloading, and if so, by how many ++ * cache lines? ++ */ ++ .if backwards ++/* Here we compare against how many bytes we are into the ++ * cache line, counting down from the highest such address. ++ * Effectively, we want to calculate ++ * leading_bytes = dst&15 ++ * cacheline_offset = 31-((src-leading_bytes-1)&31) ++ * extra_needed = leading_bytes - cacheline_offset ++ * and test if extra_needed is <= 0, or rearranging: ++ * leading_bytes + (src-leading_bytes-1)&31 <= 31 ++ */ ++ mov tmp, base, lsl #32-5 ++ sbc tmp, tmp, leading_bytes, lsl #32-5 ++ adds tmp, tmp, leading_bytes, lsl #32-5 ++ bcc 61f ++ pld [ptr, #-32*(prefetch_distance+1)] ++ .else ++/* Effectively, we want to calculate ++ * leading_bytes = (-dst)&15 ++ * cacheline_offset = (src+leading_bytes)&31 ++ * extra_needed = leading_bytes - cacheline_offset ++ * and test if extra_needed is <= 0. ++ */ ++ mov tmp, base, lsl #32-5 ++ add tmp, tmp, leading_bytes, lsl #32-5 ++ rsbs tmp, tmp, leading_bytes, lsl #32-5 ++ bls 61f ++ pld [ptr, #32*(prefetch_distance+1)] ++ .endif ++61: ++.endm ++ ++.macro preload_trailing backwards, base, remain, tmp ++ /* We need either 0, 1 or 2 extra preloads */ ++ .if backwards ++ rsb tmp, base, #0 ++ mov tmp, tmp, lsl #32-5 ++ .else ++ mov tmp, base, lsl #32-5 ++ .endif ++ adds tmp, tmp, remain, lsl #32-5 ++ adceqs tmp, tmp, #0 ++ /* The instruction above has two effects: ensures Z is only ++ * set if C was clear (so Z indicates that both shifted quantities ++ * were 0), and clears C if Z was set (so C indicates that the sum ++ * of the shifted quantities was greater and not equal to 32) */ ++ beq 82f ++ .if backwards ++ sub tmp, base, #1 ++ bic tmp, tmp, #31 ++ .else ++ bic tmp, base, #31 ++ .endif ++ bcc 81f ++ .if backwards ++ pld [tmp, #-32*(prefetch_distance+1)] ++81: ++ pld [tmp, #-32*prefetch_distance] ++ .else ++ pld [tmp, #32*(prefetch_distance+2)] ++81: ++ pld [tmp, #32*(prefetch_distance+1)] ++ .endif ++82: ++.endm ++ ++.macro preload_all backwards, narrow_case, shift, base, remain, tmp0, tmp1 ++ .if backwards ++ sub tmp0, base, #1 ++ bic tmp0, tmp0, #31 ++ pld [tmp0] ++ sub tmp1, base, remain, lsl #shift ++ .else ++ bic tmp0, base, #31 ++ pld [tmp0] ++ add tmp1, base, remain, lsl #shift ++ sub tmp1, tmp1, #1 ++ .endif ++ bic tmp1, tmp1, #31 ++ cmp tmp1, tmp0 ++ beq 92f ++ .if narrow_case ++ /* In this case, all the data fits in either 1 or 2 cache lines */ ++ pld [tmp1] ++ .else ++91: ++ .if backwards ++ sub tmp0, tmp0, #32 ++ .else ++ add tmp0, tmp0, #32 ++ .endif ++ cmp tmp0, tmp1 ++ pld [tmp0] ++ bne 91b ++ .endif ++92: ++.endm +--- a/arch/arm/lib/copy_from_user.S ++++ b/arch/arm/lib/copy_from_user.S +@@ -89,11 +89,13 @@ + + .text + +-ENTRY(__copy_from_user) ++ENTRY(__copy_from_user_std) ++WEAK(__copy_from_user) + + #include "copy_template.S" + + ENDPROC(__copy_from_user) ++ENDPROC(__copy_from_user_std) + + .pushsection .fixup,"ax" + .align 0 +--- /dev/null ++++ b/arch/arm/lib/exports_rpi.c +@@ -0,0 +1,37 @@ ++/** ++ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++ ++EXPORT_SYMBOL(memcmp); +--- /dev/null ++++ b/arch/arm/lib/memcmp_rpi.S +@@ -0,0 +1,285 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++.macro memcmp_process_head unaligned ++ .if unaligned ++ ldr DAT0, [S_1], #4 ++ ldr DAT1, [S_1], #4 ++ ldr DAT2, [S_1], #4 ++ ldr DAT3, [S_1], #4 ++ .else ++ ldmia S_1!, {DAT0, DAT1, DAT2, DAT3} ++ .endif ++ ldmia S_2!, {DAT4, DAT5, DAT6, DAT7} ++.endm ++ ++.macro memcmp_process_tail ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ cmpeq DAT3, DAT7 ++ bne 200f ++.endm ++ ++.macro memcmp_leading_31bytes ++ movs DAT0, OFF, lsl #31 ++ ldrmib DAT0, [S_1], #1 ++ ldrcsh DAT1, [S_1], #2 ++ ldrmib DAT4, [S_2], #1 ++ ldrcsh DAT5, [S_2], #2 ++ movpl DAT0, #0 ++ movcc DAT1, #0 ++ movpl DAT4, #0 ++ movcc DAT5, #0 ++ submi N, N, #1 ++ subcs N, N, #2 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ bne 200f ++ movs DAT0, OFF, lsl #29 ++ ldrmi DAT0, [S_1], #4 ++ ldrcs DAT1, [S_1], #4 ++ ldrcs DAT2, [S_1], #4 ++ ldrmi DAT4, [S_2], #4 ++ ldmcsia S_2!, {DAT5, DAT6} ++ movpl DAT0, #0 ++ movcc DAT1, #0 ++ movcc DAT2, #0 ++ movpl DAT4, #0 ++ movcc DAT5, #0 ++ movcc DAT6, #0 ++ submi N, N, #4 ++ subcs N, N, #8 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ bne 200f ++ tst OFF, #16 ++ beq 105f ++ memcmp_process_head 1 ++ sub N, N, #16 ++ memcmp_process_tail ++105: ++.endm ++ ++.macro memcmp_trailing_15bytes unaligned ++ movs N, N, lsl #29 ++ .if unaligned ++ ldrcs DAT0, [S_1], #4 ++ ldrcs DAT1, [S_1], #4 ++ .else ++ ldmcsia S_1!, {DAT0, DAT1} ++ .endif ++ ldrmi DAT2, [S_1], #4 ++ ldmcsia S_2!, {DAT4, DAT5} ++ ldrmi DAT6, [S_2], #4 ++ movcc DAT0, #0 ++ movcc DAT1, #0 ++ movpl DAT2, #0 ++ movcc DAT4, #0 ++ movcc DAT5, #0 ++ movpl DAT6, #0 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ bne 200f ++ movs N, N, lsl #2 ++ ldrcsh DAT0, [S_1], #2 ++ ldrmib DAT1, [S_1] ++ ldrcsh DAT4, [S_2], #2 ++ ldrmib DAT5, [S_2] ++ movcc DAT0, #0 ++ movpl DAT1, #0 ++ movcc DAT4, #0 ++ movpl DAT5, #0 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ bne 200f ++.endm ++ ++.macro memcmp_long_inner_loop unaligned ++110: ++ memcmp_process_head unaligned ++ pld [S_2, #prefetch_distance*32 + 16] ++ memcmp_process_tail ++ memcmp_process_head unaligned ++ pld [S_1, OFF] ++ memcmp_process_tail ++ subs N, N, #32 ++ bhs 110b ++ /* Just before the final (prefetch_distance+1) 32-byte blocks, ++ * deal with final preloads */ ++ preload_trailing 0, S_1, N, DAT0 ++ preload_trailing 0, S_2, N, DAT0 ++ add N, N, #(prefetch_distance+2)*32 - 16 ++120: ++ memcmp_process_head unaligned ++ memcmp_process_tail ++ subs N, N, #16 ++ bhs 120b ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcmp_trailing_15bytes unaligned ++199: /* Reached end without detecting a difference */ ++ mov a1, #0 ++ setend le ++ pop {DAT1-DAT6, pc} ++.endm ++ ++.macro memcmp_short_inner_loop unaligned ++ subs N, N, #16 /* simplifies inner loop termination */ ++ blo 122f ++120: ++ memcmp_process_head unaligned ++ memcmp_process_tail ++ subs N, N, #16 ++ bhs 120b ++122: /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcmp_trailing_15bytes unaligned ++199: /* Reached end without detecting a difference */ ++ mov a1, #0 ++ setend le ++ pop {DAT1-DAT6, pc} ++.endm ++ ++/* ++ * int memcmp(const void *s1, const void *s2, size_t n); ++ * On entry: ++ * a1 = pointer to buffer 1 ++ * a2 = pointer to buffer 2 ++ * a3 = number of bytes to compare (as unsigned chars) ++ * On exit: ++ * a1 = >0/=0/<0 if s1 >/=/< s2 ++ */ ++ ++.set prefetch_distance, 2 ++ ++ENTRY(memcmp) ++ S_1 .req a1 ++ S_2 .req a2 ++ N .req a3 ++ DAT0 .req a4 ++ DAT1 .req v1 ++ DAT2 .req v2 ++ DAT3 .req v3 ++ DAT4 .req v4 ++ DAT5 .req v5 ++ DAT6 .req v6 ++ DAT7 .req ip ++ OFF .req lr ++ ++ push {DAT1-DAT6, lr} ++ setend be /* lowest-addressed bytes are most significant */ ++ ++ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ ++ cmp N, #(prefetch_distance+3)*32 - 1 ++ blo 170f ++ ++ /* Long case */ ++ /* Adjust N so that the decrement instruction can also test for ++ * inner loop termination. We want it to stop when there are ++ * (prefetch_distance+1) complete blocks to go. */ ++ sub N, N, #(prefetch_distance+2)*32 ++ preload_leading_step1 0, DAT0, S_1 ++ preload_leading_step1 0, DAT1, S_2 ++ tst S_2, #31 ++ beq 154f ++ rsb OFF, S_2, #0 /* no need to AND with 15 here */ ++ preload_leading_step2 0, DAT0, S_1, OFF, DAT2 ++ preload_leading_step2 0, DAT1, S_2, OFF, DAT2 ++ memcmp_leading_31bytes ++154: /* Second source now cacheline (32-byte) aligned; we have at ++ * least one prefetch to go. */ ++ /* Prefetch offset is best selected such that it lies in the ++ * first 8 of each 32 bytes - but it's just as easy to aim for ++ * the first one */ ++ and OFF, S_1, #31 ++ rsb OFF, OFF, #32*prefetch_distance ++ tst S_1, #3 ++ bne 140f ++ memcmp_long_inner_loop 0 ++140: memcmp_long_inner_loop 1 ++ ++170: /* Short case */ ++ teq N, #0 ++ beq 199f ++ preload_all 0, 0, 0, S_1, N, DAT0, DAT1 ++ preload_all 0, 0, 0, S_2, N, DAT0, DAT1 ++ tst S_2, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199f ++ ldrb DAT0, [S_1], #1 ++ ldrb DAT4, [S_2], #1 ++ cmp DAT0, DAT4 ++ bne 200f ++ tst S_2, #3 ++ bne 172b ++174: /* Second source now 4-byte aligned; we have 0 or more bytes to go */ ++ tst S_1, #3 ++ bne 140f ++ memcmp_short_inner_loop 0 ++140: memcmp_short_inner_loop 1 ++ ++200: /* Difference found: determine sign. */ ++ movhi a1, #1 ++ movlo a1, #-1 ++ setend le ++ pop {DAT1-DAT6, pc} ++ ++ .unreq S_1 ++ .unreq S_2 ++ .unreq N ++ .unreq DAT0 ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ .unreq DAT4 ++ .unreq DAT5 ++ .unreq DAT6 ++ .unreq DAT7 ++ .unreq OFF ++ENDPROC(memcmp) +--- /dev/null ++++ b/arch/arm/lib/memcpy_rpi.S +@@ -0,0 +1,59 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++#include "memcpymove.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n); ++ * On entry: ++ * a1 = pointer to destination ++ * a2 = pointer to source ++ * a3 = number of bytes to copy ++ * On exit: ++ * a1 preserved ++ */ ++ ++.set prefetch_distance, 3 ++ ++ENTRY(memcpy) ++ memcpy 0 ++ENDPROC(memcpy) +--- /dev/null ++++ b/arch/arm/lib/memcpymove.h +@@ -0,0 +1,506 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++.macro unaligned_words backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8 ++ .if words == 1 ++ .if backwards ++ mov r1, r0, lsl #32-align*8 ++ ldr r0, [S, #-4]! ++ orr r1, r1, r0, lsr #align*8 ++ str r1, [D, #-4]! ++ .else ++ mov r0, r1, lsr #align*8 ++ ldr r1, [S, #4]! ++ orr r0, r0, r1, lsl #32-align*8 ++ str r0, [D], #4 ++ .endif ++ .elseif words == 2 ++ .if backwards ++ ldr r1, [S, #-4]! ++ mov r2, r0, lsl #32-align*8 ++ ldr r0, [S, #-4]! ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r1, r2} ++ .else ++ ldr r1, [S, #4]! ++ mov r0, r2, lsr #align*8 ++ ldr r2, [S, #4]! ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ stmia D!, {r0, r1} ++ .endif ++ .elseif words == 4 ++ .if backwards ++ ldmdb S!, {r2, r3} ++ mov r4, r0, lsl #32-align*8 ++ ldmdb S!, {r0, r1} ++ orr r4, r4, r3, lsr #align*8 ++ mov r3, r3, lsl #32-align*8 ++ orr r3, r3, r2, lsr #align*8 ++ mov r2, r2, lsl #32-align*8 ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r1, r2, r3, r4} ++ .else ++ ldmib S!, {r1, r2} ++ mov r0, r4, lsr #align*8 ++ ldmib S!, {r3, r4} ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ mov r2, r2, lsr #align*8 ++ orr r2, r2, r3, lsl #32-align*8 ++ mov r3, r3, lsr #align*8 ++ orr r3, r3, r4, lsl #32-align*8 ++ stmia D!, {r0, r1, r2, r3} ++ .endif ++ .elseif words == 8 ++ .if backwards ++ ldmdb S!, {r4, r5, r6, r7} ++ mov r8, r0, lsl #32-align*8 ++ ldmdb S!, {r0, r1, r2, r3} ++ .if use_pld ++ pld [S, OFF] ++ .endif ++ orr r8, r8, r7, lsr #align*8 ++ mov r7, r7, lsl #32-align*8 ++ orr r7, r7, r6, lsr #align*8 ++ mov r6, r6, lsl #32-align*8 ++ orr r6, r6, r5, lsr #align*8 ++ mov r5, r5, lsl #32-align*8 ++ orr r5, r5, r4, lsr #align*8 ++ mov r4, r4, lsl #32-align*8 ++ orr r4, r4, r3, lsr #align*8 ++ mov r3, r3, lsl #32-align*8 ++ orr r3, r3, r2, lsr #align*8 ++ mov r2, r2, lsl #32-align*8 ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r5, r6, r7, r8} ++ stmdb D!, {r1, r2, r3, r4} ++ .else ++ ldmib S!, {r1, r2, r3, r4} ++ mov r0, r8, lsr #align*8 ++ ldmib S!, {r5, r6, r7, r8} ++ .if use_pld ++ pld [S, OFF] ++ .endif ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ mov r2, r2, lsr #align*8 ++ orr r2, r2, r3, lsl #32-align*8 ++ mov r3, r3, lsr #align*8 ++ orr r3, r3, r4, lsl #32-align*8 ++ mov r4, r4, lsr #align*8 ++ orr r4, r4, r5, lsl #32-align*8 ++ mov r5, r5, lsr #align*8 ++ orr r5, r5, r6, lsl #32-align*8 ++ mov r6, r6, lsr #align*8 ++ orr r6, r6, r7, lsl #32-align*8 ++ mov r7, r7, lsr #align*8 ++ orr r7, r7, r8, lsl #32-align*8 ++ stmia D!, {r0, r1, r2, r3} ++ stmia D!, {r4, r5, r6, r7} ++ .endif ++ .endif ++.endm ++ ++.macro memcpy_leading_15bytes backwards, align ++ movs DAT1, DAT2, lsl #31 ++ sub N, N, DAT2 ++ .if backwards ++ ldrmib DAT0, [S, #-1]! ++ ldrcsh DAT1, [S, #-2]! ++ strmib DAT0, [D, #-1]! ++ strcsh DAT1, [D, #-2]! ++ .else ++ ldrmib DAT0, [S], #1 ++ ldrcsh DAT1, [S], #2 ++ strmib DAT0, [D], #1 ++ strcsh DAT1, [D], #2 ++ .endif ++ movs DAT1, DAT2, lsl #29 ++ .if backwards ++ ldrmi DAT0, [S, #-4]! ++ .if align == 0 ++ ldmcsdb S!, {DAT1, DAT2} ++ .else ++ ldrcs DAT2, [S, #-4]! ++ ldrcs DAT1, [S, #-4]! ++ .endif ++ strmi DAT0, [D, #-4]! ++ stmcsdb D!, {DAT1, DAT2} ++ .else ++ ldrmi DAT0, [S], #4 ++ .if align == 0 ++ ldmcsia S!, {DAT1, DAT2} ++ .else ++ ldrcs DAT1, [S], #4 ++ ldrcs DAT2, [S], #4 ++ .endif ++ strmi DAT0, [D], #4 ++ stmcsia D!, {DAT1, DAT2} ++ .endif ++.endm ++ ++.macro memcpy_trailing_15bytes backwards, align ++ movs N, N, lsl #29 ++ .if backwards ++ .if align == 0 ++ ldmcsdb S!, {DAT0, DAT1} ++ .else ++ ldrcs DAT1, [S, #-4]! ++ ldrcs DAT0, [S, #-4]! ++ .endif ++ ldrmi DAT2, [S, #-4]! ++ stmcsdb D!, {DAT0, DAT1} ++ strmi DAT2, [D, #-4]! ++ .else ++ .if align == 0 ++ ldmcsia S!, {DAT0, DAT1} ++ .else ++ ldrcs DAT0, [S], #4 ++ ldrcs DAT1, [S], #4 ++ .endif ++ ldrmi DAT2, [S], #4 ++ stmcsia D!, {DAT0, DAT1} ++ strmi DAT2, [D], #4 ++ .endif ++ movs N, N, lsl #2 ++ .if backwards ++ ldrcsh DAT0, [S, #-2]! ++ ldrmib DAT1, [S, #-1] ++ strcsh DAT0, [D, #-2]! ++ strmib DAT1, [D, #-1] ++ .else ++ ldrcsh DAT0, [S], #2 ++ ldrmib DAT1, [S] ++ strcsh DAT0, [D], #2 ++ strmib DAT1, [D] ++ .endif ++.endm ++ ++.macro memcpy_long_inner_loop backwards, align ++ .if align != 0 ++ .if backwards ++ ldr DAT0, [S, #-align]! ++ .else ++ ldr LAST, [S, #-align]! ++ .endif ++ .endif ++110: ++ .if align == 0 ++ .if backwards ++ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ pld [S, OFF] ++ stmdb D!, {DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT0, DAT1, DAT2, DAT3} ++ .else ++ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ pld [S, OFF] ++ stmia D!, {DAT0, DAT1, DAT2, DAT3} ++ stmia D!, {DAT4, DAT5, DAT6, LAST} ++ .endif ++ .else ++ unaligned_words backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST ++ .endif ++ subs N, N, #32 ++ bhs 110b ++ /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */ ++ preload_trailing backwards, S, N, OFF ++ add N, N, #(prefetch_distance+2)*32 - 32 ++120: ++ .if align == 0 ++ .if backwards ++ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT0, DAT1, DAT2, DAT3} ++ .else ++ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ stmia D!, {DAT0, DAT1, DAT2, DAT3} ++ stmia D!, {DAT4, DAT5, DAT6, LAST} ++ .endif ++ .else ++ unaligned_words backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST ++ .endif ++ subs N, N, #32 ++ bhs 120b ++ tst N, #16 ++ .if align == 0 ++ .if backwards ++ ldmnedb S!, {DAT0, DAT1, DAT2, LAST} ++ stmnedb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldmneia S!, {DAT0, DAT1, DAT2, LAST} ++ stmneia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ .else ++ beq 130f ++ unaligned_words backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST ++130: ++ .endif ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ .if align != 0 ++ add S, S, #align ++ .endif ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {DAT3, DAT4, DAT5, DAT6, DAT7} ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy_medium_inner_loop backwards, align ++120: ++ .if backwards ++ .if align == 0 ++ ldmdb S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldr LAST, [S, #-4]! ++ ldr DAT2, [S, #-4]! ++ ldr DAT1, [S, #-4]! ++ ldr DAT0, [S, #-4]! ++ .endif ++ stmdb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ .if align == 0 ++ ldmia S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldr DAT0, [S], #4 ++ ldr DAT1, [S], #4 ++ ldr DAT2, [S], #4 ++ ldr LAST, [S], #4 ++ .endif ++ stmia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ subs N, N, #16 ++ bhs 120b ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy_short_inner_loop backwards, align ++ tst N, #16 ++ .if backwards ++ .if align == 0 ++ ldmnedb S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldrne LAST, [S, #-4]! ++ ldrne DAT2, [S, #-4]! ++ ldrne DAT1, [S, #-4]! ++ ldrne DAT0, [S, #-4]! ++ .endif ++ stmnedb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ .if align == 0 ++ ldmneia S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldrne DAT0, [S], #4 ++ ldrne DAT1, [S], #4 ++ ldrne DAT2, [S], #4 ++ ldrne LAST, [S], #4 ++ .endif ++ stmneia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy backwards ++ D .req a1 ++ S .req a2 ++ N .req a3 ++ DAT0 .req a4 ++ DAT1 .req v1 ++ DAT2 .req v2 ++ DAT3 .req v3 ++ DAT4 .req v4 ++ DAT5 .req v5 ++ DAT6 .req v6 ++ DAT7 .req sl ++ LAST .req ip ++ OFF .req lr ++ ++ .cfi_startproc ++ ++ push {D, DAT1, DAT2, lr} ++ ++ .cfi_def_cfa_offset 16 ++ .cfi_rel_offset D, 0 ++ .cfi_undefined S ++ .cfi_undefined N ++ .cfi_undefined DAT0 ++ .cfi_rel_offset DAT1, 4 ++ .cfi_rel_offset DAT2, 8 ++ .cfi_undefined LAST ++ .cfi_rel_offset lr, 12 ++ ++ .if backwards ++ add D, D, N ++ add S, S, N ++ .endif ++ ++ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ ++ cmp N, #31 ++ blo 170f ++ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ ++ cmp N, #(prefetch_distance+3)*32 - 1 ++ blo 160f ++ ++ /* Long case */ ++ push {DAT3, DAT4, DAT5, DAT6, DAT7} ++ ++ .cfi_def_cfa_offset 36 ++ .cfi_rel_offset D, 20 ++ .cfi_rel_offset DAT1, 24 ++ .cfi_rel_offset DAT2, 28 ++ .cfi_rel_offset DAT3, 0 ++ .cfi_rel_offset DAT4, 4 ++ .cfi_rel_offset DAT5, 8 ++ .cfi_rel_offset DAT6, 12 ++ .cfi_rel_offset DAT7, 16 ++ .cfi_rel_offset lr, 32 ++ ++ /* Adjust N so that the decrement instruction can also test for ++ * inner loop termination. We want it to stop when there are ++ * (prefetch_distance+1) complete blocks to go. */ ++ sub N, N, #(prefetch_distance+2)*32 ++ preload_leading_step1 backwards, DAT0, S ++ .if backwards ++ /* Bug in GAS: it accepts, but mis-assembles the instruction ++ * ands DAT2, D, #60, 2 ++ * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow) ++ */ ++ .word 0xE210513C ++ beq 154f ++ .else ++ ands DAT2, D, #15 ++ beq 154f ++ rsb DAT2, DAT2, #16 /* number of leading bytes until destination aligned */ ++ .endif ++ preload_leading_step2 backwards, DAT0, S, DAT2, OFF ++ memcpy_leading_15bytes backwards, 1 ++154: /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */ ++ /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */ ++ .if backwards ++ rsb OFF, S, #3 ++ and OFF, OFF, #28 ++ sub OFF, OFF, #32*(prefetch_distance+1) ++ .else ++ and OFF, S, #28 ++ rsb OFF, OFF, #32*prefetch_distance ++ .endif ++ movs DAT0, S, lsl #31 ++ bhi 157f ++ bcs 156f ++ bmi 155f ++ memcpy_long_inner_loop backwards, 0 ++155: memcpy_long_inner_loop backwards, 1 ++156: memcpy_long_inner_loop backwards, 2 ++157: memcpy_long_inner_loop backwards, 3 ++ ++ .cfi_def_cfa_offset 16 ++ .cfi_rel_offset D, 0 ++ .cfi_rel_offset DAT1, 4 ++ .cfi_rel_offset DAT2, 8 ++ .cfi_same_value DAT3 ++ .cfi_same_value DAT4 ++ .cfi_same_value DAT5 ++ .cfi_same_value DAT6 ++ .cfi_same_value DAT7 ++ .cfi_rel_offset lr, 12 ++ ++160: /* Medium case */ ++ preload_all backwards, 0, 0, S, N, DAT2, OFF ++ sub N, N, #16 /* simplifies inner loop termination */ ++ .if backwards ++ ands DAT2, D, #15 ++ beq 164f ++ .else ++ ands DAT2, D, #15 ++ beq 164f ++ rsb DAT2, DAT2, #16 ++ .endif ++ memcpy_leading_15bytes backwards, align ++164: /* Destination now 16-byte aligned; we have at least one 16-byte output block */ ++ tst S, #3 ++ bne 140f ++ memcpy_medium_inner_loop backwards, 0 ++140: memcpy_medium_inner_loop backwards, 1 ++ ++170: /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */ ++ teq N, #0 ++ beq 199f ++ preload_all backwards, 1, 0, S, N, DAT2, LAST ++ tst D, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199f ++ .if backwards ++ ldrb DAT0, [S, #-1]! ++ strb DAT0, [D, #-1]! ++ .else ++ ldrb DAT0, [S], #1 ++ strb DAT0, [D], #1 ++ .endif ++ tst D, #3 ++ bne 172b ++174: /* Destination now 4-byte aligned; we have 0 or more output bytes to go */ ++ tst S, #3 ++ bne 140f ++ memcpy_short_inner_loop backwards, 0 ++140: memcpy_short_inner_loop backwards, 1 ++ ++ .cfi_endproc ++ ++ .unreq D ++ .unreq S ++ .unreq N ++ .unreq DAT0 ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ .unreq DAT4 ++ .unreq DAT5 ++ .unreq DAT6 ++ .unreq DAT7 ++ .unreq LAST ++ .unreq OFF ++.endm +--- /dev/null ++++ b/arch/arm/lib/memmove_rpi.S +@@ -0,0 +1,61 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++#include "memcpymove.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memmove(void *s1, const void *s2, size_t n); ++ * On entry: ++ * a1 = pointer to destination ++ * a2 = pointer to source ++ * a3 = number of bytes to copy ++ * On exit: ++ * a1 preserved ++ */ ++ ++.set prefetch_distance, 3 ++ ++ENTRY(memmove) ++ cmp a2, a1 ++ bpl memcpy /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */ ++ memcpy 1 ++ENDPROC(memmove) +--- /dev/null ++++ b/arch/arm/lib/memset_rpi.S +@@ -0,0 +1,121 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memset(void *s, int c, size_t n); ++ * On entry: ++ * a1 = pointer to buffer to fill ++ * a2 = byte pattern to fill with (caller-narrowed) ++ * a3 = number of bytes to fill ++ * On exit: ++ * a1 preserved ++ */ ++ENTRY(memset) ++ S .req a1 ++ DAT0 .req a2 ++ N .req a3 ++ DAT1 .req a4 ++ DAT2 .req ip ++ DAT3 .req lr ++ ++ orr DAT0, DAT0, lsl #8 ++ push {S, lr} ++ orr DAT0, DAT0, lsl #16 ++ mov DAT1, DAT0 ++ ++ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ ++ cmp N, #31 ++ blo 170f ++ ++161: sub N, N, #16 /* simplifies inner loop termination */ ++ /* Leading words and bytes */ ++ tst S, #15 ++ beq 164f ++ rsb DAT3, S, #0 /* bits 0-3 = number of leading bytes until aligned */ ++ movs DAT2, DAT3, lsl #31 ++ submi N, N, #1 ++ strmib DAT0, [S], #1 ++ subcs N, N, #2 ++ strcsh DAT0, [S], #2 ++ movs DAT2, DAT3, lsl #29 ++ submi N, N, #4 ++ strmi DAT0, [S], #4 ++ subcs N, N, #8 ++ stmcsia S!, {DAT0, DAT1} ++164: /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */ ++ mov DAT2, DAT0 ++ mov DAT3, DAT0 ++ /* Now the inner loop of 16-byte stores */ ++165: stmia S!, {DAT0, DAT1, DAT2, DAT3} ++ subs N, N, #16 ++ bhs 165b ++166: /* Trailing words and bytes */ ++ movs N, N, lsl #29 ++ stmcsia S!, {DAT0, DAT1} ++ strmi DAT0, [S], #4 ++ movs N, N, lsl #2 ++ strcsh DAT0, [S], #2 ++ strmib DAT0, [S] ++199: pop {S, pc} ++ ++170: /* Short case */ ++ mov DAT2, DAT0 ++ mov DAT3, DAT0 ++ tst S, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199b ++ strb DAT0, [S], #1 ++ tst S, #3 ++ bne 172b ++174: tst N, #16 ++ stmneia S!, {DAT0, DAT1, DAT2, DAT3} ++ b 166b ++ ++ .unreq S ++ .unreq DAT0 ++ .unreq N ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ENDPROC(memset) +--- a/arch/arm/lib/uaccess_with_memcpy.c ++++ b/arch/arm/lib/uaccess_with_memcpy.c +@@ -22,6 +22,14 @@ + #include + #include + ++#ifndef COPY_FROM_USER_THRESHOLD ++#define COPY_FROM_USER_THRESHOLD 64 ++#endif ++ ++#ifndef COPY_TO_USER_THRESHOLD ++#define COPY_TO_USER_THRESHOLD 64 ++#endif ++ + static int + pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) + { +@@ -85,7 +93,44 @@ pin_page_for_write(const void __user *_a + return 1; + } + +-static unsigned long noinline ++static int ++pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) ++{ ++ unsigned long addr = (unsigned long)_addr; ++ pgd_t *pgd; ++ pmd_t *pmd; ++ pte_t *pte; ++ pud_t *pud; ++ spinlock_t *ptl; ++ ++ pgd = pgd_offset(current->mm, addr); ++ if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd))) ++ { ++ return 0; ++ } ++ pud = pud_offset(pgd, addr); ++ if (unlikely(pud_none(*pud) || pud_bad(*pud))) ++ { ++ return 0; ++ } ++ ++ pmd = pmd_offset(pud, addr); ++ if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd))) ++ return 0; ++ ++ pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl); ++ if (unlikely(!pte_present(*pte) || !pte_young(*pte))) { ++ pte_unmap_unlock(pte, ptl); ++ return 0; ++ } ++ ++ *ptep = pte; ++ *ptlp = ptl; ++ ++ return 1; ++} ++ ++unsigned long noinline + __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) + { + int atomic; +@@ -135,6 +180,54 @@ out: + return n; + } + ++unsigned long noinline ++__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n) ++{ ++ int atomic; ++ ++ if (unlikely(segment_eq(get_fs(), KERNEL_DS))) { ++ memcpy(to, (const void *)from, n); ++ return 0; ++ } ++ ++ /* the mmap semaphore is taken only if not in an atomic context */ ++ atomic = in_atomic(); ++ ++ if (!atomic) ++ down_read(¤t->mm->mmap_sem); ++ while (n) { ++ pte_t *pte; ++ spinlock_t *ptl; ++ int tocopy; ++ ++ while (!pin_page_for_read(from, &pte, &ptl)) { ++ char temp; ++ if (!atomic) ++ up_read(¤t->mm->mmap_sem); ++ if (__get_user(temp, (char __user *)from)) ++ goto out; ++ if (!atomic) ++ down_read(¤t->mm->mmap_sem); ++ } ++ ++ tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1; ++ if (tocopy > n) ++ tocopy = n; ++ ++ memcpy(to, (const void *)from, tocopy); ++ to += tocopy; ++ from += tocopy; ++ n -= tocopy; ++ ++ pte_unmap_unlock(pte, ptl); ++ } ++ if (!atomic) ++ up_read(¤t->mm->mmap_sem); ++ ++out: ++ return n; ++} ++ + unsigned long + __copy_to_user(void __user *to, const void *from, unsigned long n) + { +@@ -145,10 +238,25 @@ __copy_to_user(void __user *to, const vo + * With frame pointer disabled, tail call optimization kicks in + * as well making this test almost invisible. + */ +- if (n < 64) ++ if (n < COPY_TO_USER_THRESHOLD) + return __copy_to_user_std(to, from, n); + return __copy_to_user_memcpy(to, from, n); + } ++ ++unsigned long ++__copy_from_user(void *to, const void __user *from, unsigned long n) ++{ ++ /* ++ * This test is stubbed out of the main function above to keep ++ * the overhead for small copies low by avoiding a large ++ * register dump on the stack just to reload them right away. ++ * With frame pointer disabled, tail call optimization kicks in ++ * as well making this test almost invisible. ++ */ ++ if (n < COPY_FROM_USER_THRESHOLD) ++ return __copy_from_user_std(to, from, n); ++ return __copy_from_user_memcpy(to, from, n); ++} + + static unsigned long noinline + __clear_user_memset(void __user *addr, unsigned long n) diff --git a/target/linux/brcm2708/patches-4.1/0071-bcm2835-audio-Create-the-platform-device-if-the-DT-n.patch b/target/linux/brcm2708/patches-4.1/0071-bcm2835-audio-Create-the-platform-device-if-the-DT-n.patch new file mode 100644 index 0000000..784809e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0071-bcm2835-audio-Create-the-platform-device-if-the-DT-n.patch @@ -0,0 +1,52 @@ +From b53b8765c5fe676b590ee450756321746fb84813 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 27 May 2015 17:22:15 +0100 +Subject: [PATCH 071/203] bcm2835-audio: Create the platform device if the DT + node is disabled + +For backwards compatibility, allow the built-in ALSA driver to be enabled +either by loading the module from /etc/modules or by enabling the "/audio" +node in DT. +--- + arch/arm/mach-bcm2708/bcm2708.c | 10 ++++++++-- + arch/arm/mach-bcm2709/bcm2709.c | 10 ++++++++-- + 2 files changed, 16 insertions(+), 4 deletions(-) + +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -898,8 +898,14 @@ void __init bcm2708_init(void) + #endif + bcm2708_init_led(); + bcm2708_init_uart1(); +- for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) +- bcm_register_device_dt(&bcm2708_alsa_devices[i]); ++ ++ /* Only create the platform devices for the ALSA driver in the ++ absence of an enabled "audio" DT node */ ++ if (!use_dt || ++ !of_device_is_available(of_find_node_by_path("/audio"))) { ++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) ++ bcm_register_device(&bcm2708_alsa_devices[i]); ++ } + + bcm_register_device_dt(&bcm2708_spi_device); + +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -918,8 +918,14 @@ void __init bcm2709_init(void) + #endif + bcm2709_init_led(); + bcm2709_init_uart1(); +- for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) +- bcm_register_device_dt(&bcm2708_alsa_devices[i]); ++ ++ /* Only create the platform devices for the ALSA driver in the ++ absence of an enabled "audio" DT node */ ++ if (!use_dt || ++ !of_device_is_available(of_find_node_by_path("/audio"))) { ++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) ++ bcm_register_device(&bcm2708_alsa_devices[i]); ++ } + + bcm_register_device_dt(&bcm2708_spi_device); + diff --git a/target/linux/brcm2708/patches-4.1/0072-ARM-bcm2835-Set-Serial-number-and-Revision.patch b/target/linux/brcm2708/patches-4.1/0072-ARM-bcm2835-Set-Serial-number-and-Revision.patch new file mode 100644 index 0000000..4d337e8 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0072-ARM-bcm2835-Set-Serial-number-and-Revision.patch @@ -0,0 +1,59 @@ +From 1f410ca7ae3475c5683dc1ae4e8d9837ee4df9cb Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Wed, 3 Jun 2015 12:26:13 +0200 +Subject: [PATCH 072/203] ARM: bcm2835: Set Serial number and Revision +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The VideoCore bootloader passes in Serial number and +Revision number through Device Tree. Make these available to +userspace through /proc/cpuinfo. + +Mainline status: + +There is a commit in linux-next that standardize passing the serial +number through Device Tree (string: /serial-number): +ARM: 8355/1: arch: Show the serial number from devicetree in cpuinfo + +There was an attempt to do the same with the revision number, but it +didn't get in: +[PATCH v2 1/2] arm: devtree: Set system_rev from DT revision + +Signed-off-by: Noralf Trønnes +--- + arch/arm/mach-bcm/board_bcm2835.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm/mach-bcm/board_bcm2835.c ++++ b/arch/arm/mach-bcm/board_bcm2835.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -107,6 +108,9 @@ static void __init bcm2835_map_io(void) + + static void __init bcm2835_init(void) + { ++ struct device_node *np = of_find_node_by_path("/system"); ++ u32 val; ++ u64 val64; + int ret; + + bcm2835_setup_restart(); +@@ -121,6 +125,11 @@ static void __init bcm2835_init(void) + pr_err("of_platform_populate failed: %d\n", ret); + BUG(); + } ++ ++ if (!of_property_read_u32(np, "linux,revision", &val)) ++ system_rev = val; ++ if (!of_property_read_u64(np, "linux,serial", &val64)) ++ system_serial_low = val64; + } + + static const char * const bcm2835_compat[] = { diff --git a/target/linux/brcm2708/patches-4.1/0073-platform-Add-force_core-command-line-setting-to-boot.patch b/target/linux/brcm2708/patches-4.1/0073-platform-Add-force_core-command-line-setting-to-boot.patch new file mode 100644 index 0000000..a737e5b --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0073-platform-Add-force_core-command-line-setting-to-boot.patch @@ -0,0 +1,69 @@ +From 3d0419451c7e9b5299ab34b856ce5fc6c5188a60 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Tue, 16 Jun 2015 17:47:27 +0100 +Subject: [PATCH 073/203] platform: Add force_core command line setting to boot + from a different core number + +--- + arch/arm/mach-bcm2709/armctrl.c | 17 ++++++++++++++++- + arch/arm/mach-bcm2709/bcm2709.c | 2 ++ + 2 files changed, 18 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-bcm2709/armctrl.c ++++ b/arch/arm/mach-bcm2709/armctrl.c +@@ -45,6 +45,8 @@ static unsigned int remap_irqs[(INTERRUP + INTERRUPT_VC_ARASANSDIO + }; + ++extern unsigned force_core; ++ + static void armctrl_mask_irq(struct irq_data *d) + { + static const unsigned int disables[4] = { +@@ -92,7 +94,13 @@ static void armctrl_unmask_irq(struct ir + int i; + if (d->irq >= FIQ_START) { + unsigned int data; +- if (num_online_cpus() > 1) { ++ if (force_core) { ++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ data &= ~0xc; ++ data |= ((force_core-1) << 2); ++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ } ++ else if (num_online_cpus() > 1) { + data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); + data &= ~0xc; + data |= (1 << 2); +@@ -119,6 +127,13 @@ static void armctrl_unmask_irq(struct ir + } + #endif + } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { ++ if (force_core) { ++ unsigned int data; ++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ data &= ~0x3; ++ data |= ((force_core-1) << 0); ++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ } + unsigned int data = (unsigned int)irq_get_chip_data(d->irq); + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); + } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -96,6 +96,7 @@ static unsigned w1_gpio_pin = W1_GPIO; + static unsigned w1_gpio_pullup = W1_PULLUP; + static bool vc_i2c_override = false; + static int pps_gpio_pin = -1; ++unsigned force_core; + + static unsigned use_dt = 0; + +@@ -1305,6 +1306,7 @@ MACHINE_START(BCM2708, "BCM2709") + .dt_compat = bcm2709_compat, + MACHINE_END + ++module_param(force_core, uint, 0644); + module_param(boardrev, uint, 0644); + module_param(serial, uint, 0644); + module_param(uart_clock, uint, 0644); diff --git a/target/linux/brcm2708/patches-4.1/0074-mach-bcm270x-Enable-the-building-of-pinctrl-bcm2835.patch b/target/linux/brcm2708/patches-4.1/0074-mach-bcm270x-Enable-the-building-of-pinctrl-bcm2835.patch new file mode 100644 index 0000000..d33bafb --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0074-mach-bcm270x-Enable-the-building-of-pinctrl-bcm2835.patch @@ -0,0 +1,19 @@ +From 5711c6e7c1290bca377c8fe624abca2048dabfa2 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 18 Jun 2015 17:46:17 +0100 +Subject: [PATCH 074/203] mach-bcm270x: Enable the building of pinctrl-bcm2835 + +--- + drivers/pinctrl/Makefile | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -38,6 +38,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-t + obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o + obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o + ++obj-$(CONFIG_ARCH_BCM2708)$(CONFIG_ARCH_BCM2709) += bcm/ + obj-$(CONFIG_ARCH_BCM) += bcm/ + obj-$(CONFIG_ARCH_BERLIN) += berlin/ + obj-y += freescale/ diff --git a/target/linux/brcm2708/patches-4.1/0075-BCM270X_DT-Document-the-i2s-mmap-overlay.patch b/target/linux/brcm2708/patches-4.1/0075-BCM270X_DT-Document-the-i2s-mmap-overlay.patch new file mode 100644 index 0000000..3814d98 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0075-BCM270X_DT-Document-the-i2s-mmap-overlay.patch @@ -0,0 +1,24 @@ +From 1b19ac4dd61353af67984ca6acc076e88b67f1a6 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 19 Jun 2015 16:41:39 +0100 +Subject: [PATCH 075/203] BCM270X_DT: Document the i2s-mmap overlay + +--- + arch/arm/boot/dts/overlays/README | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -260,6 +260,12 @@ Params: ds1307 Select + pcf8563 Select the PCF8563 device + + ++Name: i2s-mmap ++Info: Enables mmap support in the bcm2708-i2s driver ++Load: dtoverlay=i2s-mmap ++Params: ++ ++ + Name: iqaudio-dac + Info: Configures the IQaudio DAC audio card + Load: dtoverlay=iqaudio-dac diff --git a/target/linux/brcm2708/patches-4.1/0076-bcm2835-sdhost-Improve-error-handling-and-recovery.patch b/target/linux/brcm2708/patches-4.1/0076-bcm2835-sdhost-Improve-error-handling-and-recovery.patch new file mode 100644 index 0000000..750e10f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0076-bcm2835-sdhost-Improve-error-handling-and-recovery.patch @@ -0,0 +1,1088 @@ +From 59435defecf72f8e5c9f4ee28591df33ffa78939 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 17 Jun 2015 11:36:53 +0100 +Subject: [PATCH 076/203] bcm2835-sdhost: Improve error handling and recovery + +1) Expose the hw_reset method to the MMC framework, removing many + internal calls by the driver. + +2) Reduce overclock setting on error. + +3) Increase timeout to cope with high capacity cards. + +4) Add properties and parameters to control pio_limit and debug. + +5) Reduce messages at probe time. +--- + arch/arm/boot/dts/overlays/README | 8 +- + arch/arm/boot/dts/overlays/sdhost-overlay.dts | 4 +- + drivers/mmc/host/bcm2835-sdhost.c | 578 ++++++++++++++++++-------- + 3 files changed, 404 insertions(+), 186 deletions(-) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -408,7 +408,13 @@ Info: Selects the bcm2835-sdhost SD/MM + Load: dtoverlay=sdhost,= + Params: overclock_50 Clock (in MHz) to use when the MMC framework + requests 50MHz +- force_pio Disable DMA support ++ ++ force_pio Disable DMA support (default off) ++ ++ pio_limit Number of blocks above which to use DMA ++ (default 2) ++ ++ debug Enable debug output (default off) + + + Name: spi-bcm2708 +--- a/arch/arm/boot/dts/overlays/sdhost-overlay.dts ++++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts +@@ -22,6 +22,7 @@ + dma-names = "tx", "rx"; + brcm,delay-after-stop = <0>; + brcm,overclock-50 = <0>; ++ brcm,pio-limit = <2>; + status = "okay"; + }; + }; +@@ -70,9 +71,10 @@ + }; + + __overrides__ { +- delay_after_stop = <&sdhost>,"brcm,delay-after-stop:0"; + overclock_50 = <&sdhost>,"brcm,overclock-50:0"; + force_pio = <&sdhost>,"brcm,force-pio?"; ++ pio_limit = <&sdhost>,"brcm,pio-limit:0"; ++ debug = <&sdhost>,"brcm,debug?"; + sdhost_freq = <&clk_sdhost>,"clock-frequency:0"; + }; + }; +--- a/drivers/mmc/host/bcm2835-sdhost.c ++++ b/drivers/mmc/host/bcm2835-sdhost.c +@@ -90,9 +90,8 @@ + /* Reserved */ + #define SDHSTS_DATA_FLAG 0x01 + +-#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR) ++#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR) + #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK) +-/* SDHSTS_CRC7_ERROR - ignore this as MMC cards generate this spuriously */ + + #define SDHCFG_BUSY_IRPT_EN (1<<10) + #define SDHCFG_BLOCK_IRPT_EN (1<<8) +@@ -111,16 +110,7 @@ + #define SDEDM_READ_THRESHOLD_SHIFT 14 + #define SDEDM_THRESHOLD_MASK 0x1f + +-/* the inclusive limit in bytes under which PIO will be used instead of DMA */ +-#ifdef CONFIG_MMC_BCM2835_SDHOST_PIO_DMA_BARRIER +-#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_SDHOST_PIO_DMA_BARRIER +-#else +-#define PIO_DMA_BARRIER 0 +-#endif +- +-#define MIN_FREQ 400000 +-#define TIMEOUT_VAL 0xE +-#define BCM2835_SDHOST_WRITE_DELAY(f) (((2 * 1000000) / f) + 1) ++#define MHZ 1000000 + + #ifndef BCM2708_PERI_BASE + #define BCM2708_PERI_BASE 0x20000000 +@@ -138,19 +128,20 @@ struct bcm2835_host { + + struct mmc_host *mmc; + +- u32 timeout; ++ u32 pio_timeout; /* In jiffies */ + + int clock; /* Current clock speed */ + + bool slow_card; /* Force 11-bit divisor */ + + unsigned int max_clk; /* Max possible freq */ +- unsigned int timeout_clk; /* Timeout freq (KHz) */ + + struct tasklet_struct finish_tasklet; /* Tasklet structures */ + + struct timer_list timer; /* Timer for timeouts */ + ++ struct timer_list pio_timer; /* PIO error detection timer */ ++ + struct sg_mapping_iter sg_miter; /* SG state for PIO */ + unsigned int blocks; /* remaining PIO blocks */ + +@@ -170,6 +161,10 @@ struct bcm2835_host { + + unsigned int use_busy:1; /* Wait for busy interrupt */ + ++ unsigned int reduce_overclock:1; /* ...at the next opportunity */ ++ ++ unsigned int debug:1; /* Enable debug output */ ++ + u32 thread_isr; + + /*DMA part*/ +@@ -185,7 +180,8 @@ struct bcm2835_host { + struct timeval stop_time; /* when the last stop was issued */ + u32 delay_after_stop; /* minimum time between stop and subsequent data transfer */ + u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */ +- u32 max_overclock; /* Highest reported */ ++ u32 overclock; /* Current frequency if overclocked, else zero */ ++ u32 pio_limit; /* Maximum block count for PIO (0 = always DMA) */ + }; + + +@@ -204,41 +200,79 @@ static inline u32 bcm2835_sdhost_read_re + return readl_relaxed(host->ioaddr + reg); + } + ++static void bcm2835_sdhost_dumpcmd(struct bcm2835_host *host, ++ struct mmc_command *cmd, ++ const char *label) ++{ ++ if (cmd) ++ pr_info("%s:%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n", ++ mmc_hostname(host->mmc), ++ (cmd == host->cmd) ? '>' : ' ', ++ label, cmd->opcode, cmd->arg, cmd->flags, ++ cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], ++ cmd->error); ++} ++ + static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host) + { +- pr_info(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", ++ bcm2835_sdhost_dumpcmd(host, host->mrq->sbc, "sbc"); ++ bcm2835_sdhost_dumpcmd(host, host->mrq->cmd, "cmd"); ++ if (host->mrq->data) ++ pr_err("%s: data blocks %x blksz %x - err %d\n", ++ mmc_hostname(host->mmc), ++ host->mrq->data->blocks, ++ host->mrq->data->blksz, ++ host->mrq->data->error); ++ bcm2835_sdhost_dumpcmd(host, host->mrq->stop, "stop"); ++ ++ pr_info("%s: =========== REGISTER DUMP ===========\n", + mmc_hostname(host->mmc)); + +- pr_info(DRIVER_NAME ": SDCMD 0x%08x\n", ++ pr_info("%s: SDCMD 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDCMD)); +- pr_info(DRIVER_NAME ": SDARG 0x%08x\n", ++ pr_info("%s: SDARG 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDARG)); +- pr_info(DRIVER_NAME ": SDTOUT 0x%08x\n", ++ pr_info("%s: SDTOUT 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDTOUT)); +- pr_info(DRIVER_NAME ": SDCDIV 0x%08x\n", ++ pr_info("%s: SDCDIV 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDCDIV)); +- pr_info(DRIVER_NAME ": SDRSP0 0x%08x\n", ++ pr_info("%s: SDRSP0 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDRSP0)); +- pr_info(DRIVER_NAME ": SDRSP1 0x%08x\n", ++ pr_info("%s: SDRSP1 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDRSP1)); +- pr_info(DRIVER_NAME ": SDRSP2 0x%08x\n", ++ pr_info("%s: SDRSP2 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDRSP2)); +- pr_info(DRIVER_NAME ": SDRSP3 0x%08x\n", ++ pr_info("%s: SDRSP3 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDRSP3)); +- pr_info(DRIVER_NAME ": SDHSTS 0x%08x\n", ++ pr_info("%s: SDHSTS 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDHSTS)); +- pr_info(DRIVER_NAME ": SDVDD 0x%08x\n", ++ pr_info("%s: SDVDD 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDVDD)); +- pr_info(DRIVER_NAME ": SDEDM 0x%08x\n", ++ pr_info("%s: SDEDM 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDEDM)); +- pr_info(DRIVER_NAME ": SDHCFG 0x%08x\n", ++ pr_info("%s: SDHCFG 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDHCFG)); +- pr_info(DRIVER_NAME ": SDHBCT 0x%08x\n", ++ pr_info("%s: SDHBCT 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDHBCT)); +- pr_info(DRIVER_NAME ": SDHBLC 0x%08x\n", ++ pr_info("%s: SDHBLC 0x%08x\n", ++ mmc_hostname(host->mmc), + bcm2835_sdhost_read(host, SDHBLC)); + +- pr_debug(DRIVER_NAME ": ===========================================\n"); ++ pr_info("%s: ===========================================\n", ++ mmc_hostname(host->mmc)); + } + + +@@ -248,12 +282,10 @@ static void bcm2835_sdhost_set_power(str + } + + +-static void bcm2835_sdhost_reset(struct bcm2835_host *host) ++static void bcm2835_sdhost_reset_internal(struct bcm2835_host *host) + { + u32 temp; + +- pr_debug("bcm2835_sdhost_reset\n"); +- + bcm2835_sdhost_set_power(host, false); + + bcm2835_sdhost_write(host, 0, SDCMD); +@@ -281,6 +313,20 @@ static void bcm2835_sdhost_reset(struct + mmiowb(); + } + ++ ++static void bcm2835_sdhost_reset(struct mmc_host *mmc) ++{ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ if (host->debug) ++ pr_info("%s: reset\n", mmc_hostname(mmc)); ++ spin_lock_irqsave(&host->lock, flags); ++ ++ bcm2835_sdhost_reset_internal(host); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ + static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); + + static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft) +@@ -290,7 +336,7 @@ static void bcm2835_sdhost_init(struct b + /* Set interrupt enables */ + host->hcfg = SDHCFG_BUSY_IRPT_EN; + +- bcm2835_sdhost_reset(host); ++ bcm2835_sdhost_reset_internal(host); + + if (soft) { + /* force clock reconfiguration */ +@@ -420,6 +466,40 @@ static void bcm2835_sdhost_dma_complete( + spin_unlock_irqrestore(&host->lock, flags); + } + ++static bool data_transfer_wait(struct bcm2835_host *host, const char *caller) ++{ ++ unsigned long timeout = 1000000; ++ u32 hsts; ++ while (timeout) ++ { ++ hsts = bcm2835_sdhost_read(host, SDHSTS); ++ if (hsts & (SDHSTS_TRANSFER_ERROR_MASK | ++ SDHSTS_DATA_FLAG)) { ++ bcm2835_sdhost_write(host, SDHSTS_TRANSFER_ERROR_MASK, ++ SDHSTS); ++ break; ++ } ++ timeout--; ++ } ++ ++ if (hsts & (SDHSTS_CRC16_ERROR | ++ SDHSTS_CRC7_ERROR | ++ SDHSTS_FIFO_ERROR)) { ++ pr_err("%s: data error in %s - HSTS %x\n", ++ mmc_hostname(host->mmc), caller, hsts); ++ host->data->error = -EILSEQ; ++ return false; ++ } else if ((timeout == 0) || ++ (hsts & (SDHSTS_CMD_TIME_OUT | ++ SDHSTS_REW_TIME_OUT))) { ++ pr_err("%s: timeout in %s - HSTS %x\n", ++ mmc_hostname(host->mmc), caller, hsts); ++ host->data->error = -ETIMEDOUT; ++ return false; ++ } ++ return true; ++} ++ + static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host) + { + unsigned long flags; +@@ -443,35 +523,15 @@ static void bcm2835_sdhost_read_block_pi + buf = (u32 *)host->sg_miter.addr; + + while (len) { +- while (1) { +- u32 hsts; +- hsts = bcm2835_sdhost_read(host, SDHSTS); +- if (hsts & SDHSTS_DATA_FLAG) +- break; +- +- if (hsts & SDHSTS_ERROR_MASK) { +- pr_err("%s: Transfer error - HSTS %x, HBCT %x - %x left\n", +- mmc_hostname(host->mmc), +- hsts, +- bcm2835_sdhost_read(host, SDHBCT), +- blksize + len); +- if (hsts & SDHSTS_REW_TIME_OUT) +- host->data->error = -ETIMEDOUT; +- else if (hsts & (SDHSTS_CRC16_ERROR || +- SDHSTS_CRC7_ERROR)) +- host->data->error = -EILSEQ; +- else { +- pr_err("%s: unexpected data error\n", +- mmc_hostname(host->mmc)); +- bcm2835_sdhost_dumpregs(host); +- host->cmd->error = -EIO; +- } +- } +- } ++ if (!data_transfer_wait(host, "read_block_pio")) ++ break; + + *(buf++) = bcm2835_sdhost_read(host, SDDATA); + len -= 4; + } ++ ++ if (host->data->error) ++ break; + } + + sg_miter_stop(&host->sg_miter); +@@ -502,11 +562,15 @@ static void bcm2835_sdhost_write_block_p + buf = host->sg_miter.addr; + + while (len) { +- while (!(bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG)) +- continue; ++ if (!data_transfer_wait(host, "write_block_pio")) ++ break; ++ + bcm2835_sdhost_write(host, *(buf++), SDDATA); + len -= 4; + } ++ ++ if (host->data->error) ++ break; + } + + sg_miter_stop(&host->sg_miter); +@@ -519,10 +583,15 @@ static void bcm2835_sdhost_transfer_pio( + { + BUG_ON(!host->data); + +- if (host->data->flags & MMC_DATA_READ) ++ if (host->data->flags & MMC_DATA_READ) { + bcm2835_sdhost_read_block_pio(host); +- else ++ } else { + bcm2835_sdhost_write_block_pio(host); ++ ++ /* Start a timer in case a transfer error occurs because ++ there is no error interrupt */ ++ mod_timer(&host->pio_timer, jiffies + host->pio_timeout); ++ } + } + + +@@ -607,6 +676,7 @@ static void bcm2835_sdhost_prepare_data( + host->flush_fifo = 0; + host->data->bytes_xfered = 0; + ++ host->use_dma = host->have_dma && (data->blocks > host->pio_limit); + if (!host->use_dma) { + int flags; + +@@ -619,8 +689,6 @@ static void bcm2835_sdhost_prepare_data( + host->blocks = data->blocks; + } + +- host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER; +- + bcm2835_sdhost_set_transfer_irqs(host); + + bcm2835_sdhost_write(host, data->blksz, SDHBCT); +@@ -638,22 +706,25 @@ void bcm2835_sdhost_send_command(struct + + WARN_ON(host->cmd); + +- if (1) { +- pr_debug("bcm2835_sdhost_send_command: %08x %08x (flags %x)\n", +- cmd->opcode, cmd->arg, (cmd->flags & 0xff) | (cmd->data ? cmd->data->flags : 0)); +- if (cmd->data) +- pr_debug("bcm2835_sdhost_send_command: %s %d*%x\n", +- (cmd->data->flags & MMC_DATA_READ) ? +- "read" : "write", cmd->data->blocks, +- cmd->data->blksz); +- } ++ if (cmd->data) ++ pr_debug("%s: send_command %d 0x%x " ++ "(flags 0x%x) - %s %d*%d\n", ++ mmc_hostname(host->mmc), ++ cmd->opcode, cmd->arg, cmd->flags, ++ (cmd->data->flags & MMC_DATA_READ) ? ++ "read" : "write", cmd->data->blocks, ++ cmd->data->blksz); ++ else ++ pr_debug("%s: send_command %d 0x%x (flags 0x%x)\n", ++ mmc_hostname(host->mmc), ++ cmd->opcode, cmd->arg, cmd->flags); + + /* Wait max 10 ms */ + timeout = 1000; + + while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) { + if (timeout == 0) { +- pr_err("%s: Previous command never completed.\n", ++ pr_err("%s: previous command never completed.\n", + mmc_hostname(host->mmc)); + bcm2835_sdhost_dumpregs(host); + cmd->error = -EIO; +@@ -666,16 +737,16 @@ void bcm2835_sdhost_send_command(struct + + if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) { + host->max_delay = (1000-timeout)/100; +- pr_warning("Warning: SDHost controller hung for %d ms\n", host->max_delay); ++ pr_warning("%s: controller hung for %d ms\n", ++ mmc_hostname(host->mmc), ++ host->max_delay); + } + + timeout = jiffies; +-#ifdef CONFIG_ARCH_BCM2835 + if (!cmd->data && cmd->busy_timeout > 9000) + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; + else +-#endif +- timeout += 10 * HZ; ++ timeout += 10 * HZ; + mod_timer(&host->timer, timeout); + + host->cmd = cmd; +@@ -685,7 +756,7 @@ void bcm2835_sdhost_send_command(struct + bcm2835_sdhost_write(host, cmd->arg, SDARG); + + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { +- pr_err("%s: Unsupported response type!\n", ++ pr_err("%s: unsupported response type!\n", + mmc_hostname(host->mmc)); + cmd->error = -EINVAL; + tasklet_schedule(&host->finish_tasklet); +@@ -783,13 +854,6 @@ static void bcm2835_sdhost_transfer_comp + pr_debug("transfer_complete(error %d, stop %d)\n", + data->error, data->stop ? 1 : 0); + +- if (data->error) +- /* +- * The controller needs a reset of internal state machines +- * upon error conditions. +- */ +- bcm2835_sdhost_reset(host); +- + /* + * Need to send CMD12 if - + * a) open-ended multiblock transfer (no CMD23) +@@ -845,7 +909,7 @@ static void bcm2835_sdhost_finish_comman + #endif + + if (timeout == 0) { +- pr_err("%s: Command never completed.\n", ++ pr_err("%s: command never completed.\n", + mmc_hostname(host->mmc)); + bcm2835_sdhost_dumpregs(host); + host->cmd->error = -EIO; +@@ -875,14 +939,23 @@ static void bcm2835_sdhost_finish_comman + { + u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); + +- pr_debug("%s: error detected - CMD %x, HSTS %03x, EDM %x\n", +- mmc_hostname(host->mmc), sdcmd, sdhsts, +- bcm2835_sdhost_read(host, SDEDM)); +- +- if (sdhsts & SDHSTS_CMD_TIME_OUT) ++ if (host->debug) ++ pr_info("%s: error detected - CMD %x, HSTS %03x, EDM %x\n", ++ mmc_hostname(host->mmc), sdcmd, sdhsts, ++ bcm2835_sdhost_read(host, SDEDM)); ++ ++ if (sdhsts & SDHSTS_CMD_TIME_OUT) { ++ switch (host->cmd->opcode) { ++ case 5: case 52: case 53: ++ /* Don't warn about SDIO commands */ ++ break; ++ default: ++ pr_err("%s: command timeout\n", ++ mmc_hostname(host->mmc)); ++ break; ++ } + host->cmd->error = -ETIMEDOUT; +- else +- { ++ } else { + pr_err("%s: unexpected command error\n", + mmc_hostname(host->mmc)); + bcm2835_sdhost_dumpregs(host); +@@ -897,11 +970,13 @@ static void bcm2835_sdhost_finish_comman + int i; + for (i = 0; i < 4; i++) + host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4); +- pr_debug("bcm2835_sdhost_finish_command: %08x %08x %08x %08x\n", ++ pr_debug("%s: finish_command %08x %08x %08x %08x\n", ++ mmc_hostname(host->mmc), + host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]); + } else { + host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0); +- pr_debug("bcm2835_sdhost_finish_command: %08x\n", ++ pr_debug("%s: finish_command %08x\n", ++ mmc_hostname(host->mmc), + host->cmd->resp[0]); + } + } +@@ -932,7 +1007,7 @@ static void bcm2835_sdhost_finish_comman + } + } + +-static void bcm2835_sdhost_timeout_timer(unsigned long data) ++static void bcm2835_sdhost_timeout(unsigned long data) + { + struct bcm2835_host *host; + unsigned long flags; +@@ -942,7 +1017,7 @@ static void bcm2835_sdhost_timeout_timer + spin_lock_irqsave(&host->lock, flags); + + if (host->mrq) { +- pr_err("%s: Timeout waiting for hardware interrupt.\n", ++ pr_err("%s: timeout waiting for hardware interrupt.\n", + mmc_hostname(host->mmc)); + bcm2835_sdhost_dumpregs(host); + +@@ -964,6 +1039,41 @@ static void bcm2835_sdhost_timeout_timer + spin_unlock_irqrestore(&host->lock, flags); + } + ++static void bcm2835_sdhost_pio_timeout(unsigned long data) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = (struct bcm2835_host *)data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->data) { ++ u32 hsts = bcm2835_sdhost_read(host, SDHSTS); ++ ++ if (hsts & SDHSTS_REW_TIME_OUT) { ++ pr_err("%s: transfer timeout\n", ++ mmc_hostname(host->mmc)); ++ if (host->debug) ++ bcm2835_sdhost_dumpregs(host); ++ } else { ++ pr_err("%s: unexpected transfer timeout\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ } ++ ++ bcm2835_sdhost_write(host, SDHSTS_TRANSFER_ERROR_MASK, ++ SDHSTS); ++ ++ host->data->error = -ETIMEDOUT; ++ ++ bcm2835_sdhost_finish_data(host); ++ } ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ + static void bcm2835_sdhost_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable) + { + if (enable) +@@ -979,7 +1089,7 @@ static void bcm2835_sdhost_enable_sdio_i + struct bcm2835_host *host = mmc_priv(mmc); + unsigned long flags; + +- pr_debug("bcm2835_sdhost_enable_sdio_irq(%d)\n", enable); ++ pr_debug("%s: enable_sdio_irq(%d)\n", mmc_hostname(mmc), enable); + spin_lock_irqsave(&host->lock, flags); + bcm2835_sdhost_enable_sdio_irq_nolock(host, enable); + spin_unlock_irqrestore(&host->lock, flags); +@@ -987,11 +1097,12 @@ static void bcm2835_sdhost_enable_sdio_i + + static u32 bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask) + { +- const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR | +- SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR); ++ const u32 handled = (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT | ++ SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR | ++ SDHSTS_FIFO_ERROR); + + if (!host->cmd) { +- pr_err("%s: Got command busy interrupt 0x%08x even " ++ pr_err("%s: got command busy interrupt 0x%08x even " + "though no command operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + bcm2835_sdhost_dumpregs(host); +@@ -999,7 +1110,7 @@ static u32 bcm2835_sdhost_busy_irq(struc + } + + if (!host->use_busy) { +- pr_err("%s: Got command busy interrupt 0x%08x even " ++ pr_err("%s: got command busy interrupt 0x%08x even " + "though not expecting one.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + bcm2835_sdhost_dumpregs(host); +@@ -1007,14 +1118,28 @@ static u32 bcm2835_sdhost_busy_irq(struc + } + host->use_busy = 0; + +- if (intmask & SDHSTS_CMD_TIME_OUT) +- host->cmd->error = -ETIMEDOUT; +- else if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR | +- SDHSTS_FIFO_ERROR)) +- host->cmd->error = -EILSEQ; ++ if (intmask & SDHSTS_ERROR_MASK) ++ { ++ pr_err("sdhost_busy_irq: intmask %x, data %p\n", intmask, host->mrq->data); ++ if (intmask & SDHSTS_CRC7_ERROR) ++ host->cmd->error = -EILSEQ; ++ else if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR)) { ++ if (host->mrq->data) ++ host->mrq->data->error = -EILSEQ; ++ else ++ host->cmd->error = -EILSEQ; ++ } else if (intmask & SDHSTS_REW_TIME_OUT) { ++ if (host->mrq->data) ++ host->mrq->data->error = -ETIMEDOUT; ++ else ++ host->cmd->error = -ETIMEDOUT; ++ } else if (intmask & SDHSTS_CMD_TIME_OUT) ++ host->cmd->error = -ETIMEDOUT; + +- if (host->cmd->error) ++ bcm2835_sdhost_dumpregs(host); + tasklet_schedule(&host->finish_tasklet); ++ } + else + bcm2835_sdhost_finish_command(host); + +@@ -1023,8 +1148,9 @@ static u32 bcm2835_sdhost_busy_irq(struc + + static u32 bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask) + { +- const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR | +- SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR); ++ const u32 handled = (SDHSTS_REW_TIME_OUT | ++ SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR); + + /* There are no dedicated data/space available interrupt + status bits, so it is necessary to use the single shared +@@ -1034,13 +1160,19 @@ static u32 bcm2835_sdhost_data_irq(struc + if (!host->data) + return 0; + +- // XXX FIFO_ERROR +- if (intmask & SDHSTS_CMD_TIME_OUT) +- host->cmd->error = -ETIMEDOUT; +- else if ((intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR)) && +- ((bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK) +- != MMC_BUS_TEST_R)) +- host->cmd->error = -EILSEQ; ++ if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR | ++ SDHSTS_REW_TIME_OUT)) { ++ if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR)) ++ host->data->error = -EILSEQ; ++ else ++ host->data->error = -ETIMEDOUT; ++ ++ bcm2835_sdhost_dumpregs(host); ++ tasklet_schedule(&host->finish_tasklet); ++ return handled; ++ } + + /* Use the block interrupt for writes after the first block */ + if (host->data->flags & MMC_DATA_WRITE) { +@@ -1067,31 +1199,48 @@ static u32 bcm2835_sdhost_block_irq(stru + { + struct dma_chan *dma_chan; + u32 dir_data; +- const u32 handled = (SDHSTS_CMD_TIME_OUT | SDHSTS_CRC16_ERROR | +- SDHSTS_CRC7_ERROR | SDHSTS_FIFO_ERROR); ++ const u32 handled = (SDHSTS_REW_TIME_OUT | ++ SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR); + + if (!host->data) { +- pr_err("%s: Got block interrupt 0x%08x even " ++ pr_err("%s: got block interrupt 0x%08x even " + "though no data operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + bcm2835_sdhost_dumpregs(host); + return handled; + } + +- if (intmask & SDHSTS_CMD_TIME_OUT) +- host->cmd->error = -ETIMEDOUT; +- else if ((intmask & (SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR)) && +- ((bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK) +- != MMC_BUS_TEST_R)) +- host->cmd->error = -EILSEQ; ++ if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR | ++ SDHSTS_REW_TIME_OUT)) { ++ if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR)) ++ host->data->error = -EILSEQ; ++ else ++ host->data->error = -ETIMEDOUT; ++ ++ if (host->debug) ++ bcm2835_sdhost_dumpregs(host); ++ tasklet_schedule(&host->finish_tasklet); ++ return handled; ++ } + + if (!host->use_dma) { + BUG_ON(!host->blocks); + host->blocks--; +- if ((host->blocks == 0) || host->data->error) ++ if ((host->blocks == 0) || host->data->error) { ++ /* Cancel the timer */ ++ del_timer(&host->pio_timer); ++ + bcm2835_sdhost_finish_data(host); +- else ++ } else { + bcm2835_sdhost_transfer_pio(host); ++ ++ /* Reset the timer */ ++ mod_timer(&host->pio_timer, ++ jiffies + host->pio_timeout); ++ } + } else if (host->data->flags & MMC_DATA_WRITE) { + dma_chan = host->dma_chan_tx; + dir_data = DMA_TO_DEVICE; +@@ -1125,7 +1274,7 @@ static irqreturn_t bcm2835_sdhost_irq(in + SDHSTS_BLOCK_IRPT | + SDHSTS_SDIO_IRPT | + SDHSTS_DATA_FLAG); +- if ((handled == SDHSTS_DATA_FLAG) && // XXX ++ if ((handled == SDHSTS_DATA_FLAG) && + (loops == 0) && !host->data) { + pr_err("%s: sdhost_irq data interrupt 0x%08x even " + "though no data operation was in progress.\n", +@@ -1177,10 +1326,11 @@ static irqreturn_t bcm2835_sdhost_irq(in + spin_unlock(&host->lock); + + if (early) +- pr_debug("%s: early %x (loops %d)\n", mmc_hostname(host->mmc), early, loops); ++ pr_debug("%s: early %x (loops %d)\n", ++ mmc_hostname(host->mmc), early, loops); + + if (unexpected) { +- pr_err("%s: Unexpected interrupt 0x%08x.\n", ++ pr_err("%s: unexpected interrupt 0x%08x.\n", + mmc_hostname(host->mmc), unexpected); + bcm2835_sdhost_dumpregs(host); + } +@@ -1227,8 +1377,22 @@ void bcm2835_sdhost_set_clock(struct bcm + int div = 0; /* Initialized for compiler warning */ + unsigned int input_clock = clock; + +- if (host->overclock_50 && (clock == 50000000)) +- clock = host->overclock_50 * 1000000 + 999999; ++ if (host->debug) ++ pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock); ++ ++ if ((clock == 0) && host->reduce_overclock) { ++ /* This is a reset following data corruption - reduce any ++ overclock */ ++ host->reduce_overclock = 0; ++ if (host->overclock_50 > 50) { ++ pr_warn("%s: reducing overclock due to errors\n", ++ mmc_hostname(host->mmc)); ++ host->overclock_50--; ++ } ++ } ++ ++ if (host->overclock_50 && (clock == 50*MHZ)) ++ clock = host->overclock_50 * MHZ + (MHZ - 1); + + /* The SDCDIV register has 11 bits, and holds (div - 2). + But in data mode the max is 50MHz wihout a minimum, and only the +@@ -1275,17 +1439,34 @@ void bcm2835_sdhost_set_clock(struct bcm + clock = host->max_clk / (div + 2); + host->mmc->actual_clock = clock; + +- if ((clock > input_clock) && (clock > host->max_overclock)) { +- pr_warn("%s: Overclocking to %dHz\n", +- mmc_hostname(host->mmc), clock); +- host->max_overclock = clock; ++ if (clock > input_clock) { ++ /* Save the closest value, to make it easier ++ to reduce in the event of error */ ++ host->overclock_50 = (clock/MHZ); ++ ++ if (clock != host->overclock) { ++ pr_warn("%s: overclocking to %dHz\n", ++ mmc_hostname(host->mmc), clock); ++ host->overclock = clock; ++ } ++ } ++ else if ((clock == 50 * MHZ) && host->overclock) ++ { ++ pr_warn("%s: cancelling overclock\n", ++ mmc_hostname(host->mmc)); ++ host->overclock = 0; + } + + host->cdiv = div; + bcm2835_sdhost_write(host, host->cdiv, SDCDIV); + +- pr_debug(DRIVER_NAME ": clock=%d -> max_clk=%d, cdiv=%x (actual clock %d)\n", +- input_clock, host->max_clk, host->cdiv, host->mmc->actual_clock); ++ /* Set the timeout to 500ms */ ++ bcm2835_sdhost_write(host, host->mmc->actual_clock/2, SDTOUT); ++ ++ if (host->debug) ++ pr_info("%s: clock=%d -> max_clk=%d, cdiv=%x (actual clock %d)\n", ++ mmc_hostname(host->mmc), input_clock, ++ host->max_clk, host->cdiv, host->mmc->actual_clock); + } + + static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq) +@@ -1293,29 +1474,32 @@ static void bcm2835_sdhost_request(struc + struct bcm2835_host *host; + unsigned long flags; + +- if (1) { ++ host = mmc_priv(mmc); ++ ++ if (host->debug) { + struct mmc_command *cmd = mrq->cmd; +- const char *src = "cmd"; + BUG_ON(!cmd); +- pr_debug("bcm2835_sdhost_request: %s %08x %08x (flags %x)\n", +- src, cmd->opcode, cmd->arg, cmd->flags); + if (cmd->data) +- pr_debug("bcm2835_sdhost_request: %s %d*%d\n", +- (cmd->data->flags & MMC_DATA_READ) ? +- "read" : "write", cmd->data->blocks, +- cmd->data->blksz); ++ pr_info("%s: cmd %d 0x%x (flags 0x%x) - %s %d*%d\n", ++ mmc_hostname(mmc), ++ cmd->opcode, cmd->arg, cmd->flags, ++ (cmd->data->flags & MMC_DATA_READ) ? ++ "read" : "write", cmd->data->blocks, ++ cmd->data->blksz); ++ else ++ pr_info("%s: cmd %d 0x%x (flags 0x%x)\n", ++ mmc_hostname(mmc), ++ cmd->opcode, cmd->arg, cmd->flags); + } + + if (mrq->data && !is_power_of_2(mrq->data->blksz)) { +- pr_err("%s: Unsupported block size (%d bytes)\n", ++ pr_err("%s: unsupported block size (%d bytes)\n", + mmc_hostname(mmc), mrq->data->blksz); + mrq->cmd->error = -EINVAL; + mmc_request_done(mmc, mrq); + return; + } + +- host = mmc_priv(mmc); +- + spin_lock_irqsave(&host->lock, flags); + + WARN_ON(host->mrq != NULL); +@@ -1345,9 +1529,12 @@ static void bcm2835_sdhost_set_ios(struc + struct bcm2835_host *host = mmc_priv(mmc); + unsigned long flags; + +- pr_debug("bcm2835_sdhost_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n", +- ios->clock, ios->power_mode, ios->bus_width, +- ios->timing, ios->signal_voltage, ios->drv_type); ++ if (host->debug) ++ pr_info("%s: ios clock %d, pwr %d, bus_width %d, " ++ "timing %d, vdd %d, drv_type %d\n", ++ mmc_hostname(mmc), ++ ios->clock, ios->power_mode, ios->bus_width, ++ ios->timing, ios->signal_voltage, ios->drv_type); + + spin_lock_irqsave(&host->lock, flags); + +@@ -1396,6 +1583,7 @@ static struct mmc_host_ops bcm2835_sdhos + .request = bcm2835_sdhost_request, + .set_ios = bcm2835_sdhost_set_ios, + .enable_sdio_irq = bcm2835_sdhost_enable_sdio_irq, ++ .hw_reset = bcm2835_sdhost_reset, + .multi_io_quirk = bcm2835_sdhost_multi_io_quirk, + }; + +@@ -1423,15 +1611,24 @@ static void bcm2835_sdhost_tasklet_finis + + mrq = host->mrq; + +- /* +- * The controller needs a reset of internal state machines +- * upon error conditions. +- */ +- if (((mrq->cmd && mrq->cmd->error) || +- (mrq->data && (mrq->data->error || +- (mrq->data->stop && mrq->data->stop->error))))) { ++ /* Drop the overclock after any data corruption, or after any ++ error overclocked */ ++ if (mrq->data && (mrq->data->error == -EILSEQ)) ++ host->reduce_overclock = 1; ++ else if (host->overclock) { ++ /* Convert timeout errors while overclocked to data errors, ++ because the system recovers better. */ ++ if (mrq->cmd && mrq->cmd->error) { ++ host->reduce_overclock = 1; ++ if (mrq->cmd->error == -ETIMEDOUT) ++ mrq->cmd->error = -EILSEQ; ++ } + +- bcm2835_sdhost_reset(host); ++ if (mrq->data && mrq->data->error) { ++ host->reduce_overclock = 1; ++ if (mrq->data->error == -ETIMEDOUT) ++ mrq->data->error = -EILSEQ; ++ } + } + + host->mrq = NULL; +@@ -1450,35 +1647,37 @@ int bcm2835_sdhost_add_host(struct bcm28 + { + struct mmc_host *mmc; + struct dma_slave_config cfg; ++ char pio_limit_string[20]; + int ret; + + mmc = host->mmc; + +- bcm2835_sdhost_reset(host); ++ bcm2835_sdhost_reset_internal(host); + + mmc->f_max = host->max_clk; + mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; + +- /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ +- host->timeout_clk = mmc->f_max / 1000; +-#ifdef CONFIG_ARCH_BCM2835 +- mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; +-#endif ++ mmc->max_busy_timeout = (~(unsigned int)0)/(mmc->f_max/1000); ++ ++ pr_debug("f_max %d, f_min %d, max_busy_timeout %d\n", ++ mmc->f_max, mmc->f_min, mmc->max_busy_timeout); ++ + /* host controller capabilities */ + mmc->caps |= /* MMC_CAP_SDIO_IRQ |*/ MMC_CAP_4_BIT_DATA | + MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | +- MMC_CAP_NEEDS_POLL | ++ MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | + (ALLOW_CMD23 * MMC_CAP_CMD23); + + spin_lock_init(&host->lock); + + if (host->allow_dma) { +- if (!host->dma_chan_tx || !host->dma_chan_rx || +- IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) { +- pr_err("%s: Unable to initialise DMA channels. Falling back to PIO\n", DRIVER_NAME); ++ if (IS_ERR_OR_NULL(host->dma_chan_tx) || ++ IS_ERR_OR_NULL(host->dma_chan_rx)) { ++ pr_err("%s: unable to initialise DMA channels. " ++ "Falling back to PIO\n", ++ mmc_hostname(mmc)); + host->have_dma = false; + } else { +- pr_info("DMA channels allocated for the SDHost driver"); + host->have_dma = true; + + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; +@@ -1496,7 +1695,6 @@ int bcm2835_sdhost_add_host(struct bcm28 + ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); + } + } else { +- pr_info("Forcing PIO mode\n"); + host->have_dma = false; + } + +@@ -1512,18 +1710,23 @@ int bcm2835_sdhost_add_host(struct bcm28 + tasklet_init(&host->finish_tasklet, + bcm2835_sdhost_tasklet_finish, (unsigned long)host); + +- setup_timer(&host->timer, bcm2835_sdhost_timeout_timer, (unsigned long)host); ++ setup_timer(&host->timer, bcm2835_sdhost_timeout, ++ (unsigned long)host); ++ ++ setup_timer(&host->pio_timer, bcm2835_sdhost_pio_timeout, ++ (unsigned long)host); + + bcm2835_sdhost_init(host, 0); + #ifndef CONFIG_ARCH_BCM2835 + ret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/, + mmc_hostname(mmc), host); + #else +- ret = request_threaded_irq(host->irq, bcm2835_sdhost_irq, bcm2835_sdhost_thread_irq, ++ ret = request_threaded_irq(host->irq, bcm2835_sdhost_irq, ++ bcm2835_sdhost_thread_irq, + IRQF_SHARED, mmc_hostname(mmc), host); + #endif + if (ret) { +- pr_err("%s: Failed to request IRQ %d: %d\n", ++ pr_err("%s: failed to request IRQ %d: %d\n", + mmc_hostname(mmc), host->irq, ret); + goto untasklet; + } +@@ -1531,10 +1734,13 @@ int bcm2835_sdhost_add_host(struct bcm28 + mmiowb(); + mmc_add_host(mmc); + +- pr_info("Load BCM2835 SDHost driver\n"); +- if (host->delay_after_stop) +- pr_info("BCM2835 SDHost: delay_after_stop=%dus\n", +- host->delay_after_stop); ++ pio_limit_string[0] = '\0'; ++ if (host->have_dma && (host->pio_limit > 0)) ++ sprintf(pio_limit_string, " (>%d)", host->pio_limit); ++ pr_info("%s: %s loaded - DMA %s%s\n", ++ mmc_hostname(mmc), DRIVER_NAME, ++ host->have_dma ? "enabled" : "disabled", ++ pio_limit_string); + + return 0; + +@@ -1562,7 +1768,7 @@ static int bcm2835_sdhost_probe(struct p + mmc->ops = &bcm2835_sdhost_ops; + host = mmc_priv(mmc); + host->mmc = mmc; +- host->timeout = msecs_to_jiffies(1000); ++ host->pio_timeout = msecs_to_jiffies(500); + spin_lock_init(&host->lock); + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); +@@ -1588,8 +1794,12 @@ static int bcm2835_sdhost_probe(struct p + of_property_read_u32(node, + "brcm,overclock-50", + &host->overclock_50); ++ of_property_read_u32(node, ++ "brcm,pio-limit", ++ &host->pio_limit); + host->allow_dma = ALLOW_DMA && + !of_property_read_bool(node, "brcm,force-pio"); ++ host->debug = of_property_read_bool(node, "brcm,debug"); + } + + if (host->allow_dma) { diff --git a/target/linux/brcm2708/patches-4.1/0077-ARM-bcm2835-Add-the-Raspberry-Pi-firmware-driver.patch b/target/linux/brcm2708/patches-4.1/0077-ARM-bcm2835-Add-the-Raspberry-Pi-firmware-driver.patch new file mode 100644 index 0000000..d266722 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0077-ARM-bcm2835-Add-the-Raspberry-Pi-firmware-driver.patch @@ -0,0 +1,426 @@ +From 139af060398effb2c9a9dfd8d4878e4efaf57150 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Thu, 4 Jun 2015 13:11:46 -0700 +Subject: [PATCH 077/203] ARM: bcm2835: Add the Raspberry Pi firmware driver + +This gives us a function for making mailbox property channel requests +of the firmware, which is most notable in that it will let us get and +set clock rates. + +Signed-off-by: Eric Anholt +--- + drivers/firmware/Kconfig | 7 + + drivers/firmware/Makefile | 1 + + drivers/firmware/raspberrypi.c | 260 +++++++++++++++++++++++++++++ + include/soc/bcm2835/raspberrypi-firmware.h | 115 +++++++++++++ + 4 files changed, 383 insertions(+) + create mode 100644 drivers/firmware/raspberrypi.c + create mode 100644 include/soc/bcm2835/raspberrypi-firmware.h + +--- a/drivers/firmware/Kconfig ++++ b/drivers/firmware/Kconfig +@@ -136,6 +136,13 @@ config QCOM_SCM + bool + depends on ARM || ARM64 + ++config RASPBERRYPI_FIRMWARE ++ tristate "Raspberry Pi Firmware Driver" ++ depends on BCM2835_MBOX ++ help ++ This option enables support for communicating with the firmware on the ++ Raspberry Pi. ++ + source "drivers/firmware/google/Kconfig" + source "drivers/firmware/efi/Kconfig" + +--- a/drivers/firmware/Makefile ++++ b/drivers/firmware/Makefile +@@ -13,6 +13,7 @@ obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o + obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o + obj-$(CONFIG_QCOM_SCM) += qcom_scm.o + CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) ++obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o + + obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ + obj-$(CONFIG_EFI) += efi/ +--- /dev/null ++++ b/drivers/firmware/raspberrypi.c +@@ -0,0 +1,260 @@ ++/* ++ * Defines interfaces for interacting wtih the Raspberry Pi firmware's ++ * property channel. ++ * ++ * Copyright © 2015 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf)) ++#define MBOX_CHAN(msg) ((msg) & 0xf) ++#define MBOX_DATA28(msg) ((msg) & ~0xf) ++#define MBOX_CHAN_PROPERTY 8 ++ ++struct rpi_firmware { ++ struct mbox_client cl; ++ struct mbox_chan *chan; /* The property channel. */ ++ struct completion c; ++ u32 enabled; ++}; ++ ++static DEFINE_MUTEX(transaction_lock); ++ ++static void response_callback(struct mbox_client *cl, void *msg) ++{ ++ struct rpi_firmware *fw = container_of(cl, struct rpi_firmware, cl); ++ complete(&fw->c); ++} ++ ++/* ++ * Sends a request to the firmware through the BCM2835 mailbox driver, ++ * and synchronously waits for the reply. ++ */ ++static int ++rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data) ++{ ++ u32 message = MBOX_MSG(chan, data); ++ int ret; ++ ++ WARN_ON(data & 0xf); ++ ++ mutex_lock(&transaction_lock); ++ reinit_completion(&fw->c); ++ ret = mbox_send_message(fw->chan, &message); ++ if (ret >= 0) { ++ wait_for_completion(&fw->c); ++ ret = 0; ++ } else { ++ dev_err(fw->cl.dev, "mbox_send_message returned %d\n", ret); ++ } ++ mutex_unlock(&transaction_lock); ++ ++ return ret; ++} ++ ++/** ++ * rpi_firmware_property_list - Submit firmware property list ++ * @fw: Pointer to firmware structure from rpi_firmware_get(). ++ * @data: Buffer holding tags. ++ * @tag_size: Size of tags buffer. ++ * ++ * Submits a set of concatenated tags to the VPU firmware through the ++ * mailbox property interface. ++ * ++ * The buffer header and the ending tag are added by this function and ++ * don't need to be supplied, just the actual tags for your operation. ++ * See struct rpi_firmware_property_tag_header for the per-tag ++ * structure. ++ */ ++int rpi_firmware_property_list(struct rpi_firmware *fw, ++ void *data, size_t tag_size) ++{ ++ size_t size = tag_size + 12; ++ u32 *buf; ++ dma_addr_t bus_addr; ++ int ret; ++ ++ /* Packets are processed a dword at a time. */ ++ if (size & 3) ++ return -EINVAL; ++ ++ buf = dma_alloc_coherent(fw->cl.dev, PAGE_ALIGN(size), &bus_addr, ++ GFP_ATOMIC); ++ if (!buf) ++ return -ENOMEM; ++ ++ /* The firmware will error out without parsing in this case. */ ++ WARN_ON(size >= 1024 * 1024); ++ ++ buf[0] = size; ++ buf[1] = RPI_FIRMWARE_STATUS_REQUEST; ++ memcpy(&buf[2], data, tag_size); ++ buf[size / 4 - 1] = RPI_FIRMWARE_PROPERTY_END; ++ wmb(); ++ ++ ret = rpi_firmware_transaction(fw, MBOX_CHAN_PROPERTY, bus_addr); ++ ++ rmb(); ++ memcpy(data, &buf[2], tag_size); ++ if (ret == 0 && buf[1] != RPI_FIRMWARE_STATUS_SUCCESS) { ++ /* ++ * The tag name here might not be the one causing the ++ * error, if there were multiple tags in the request. ++ * But single-tag is the most common, so go with it. ++ */ ++ dev_err(fw->cl.dev, "Request 0x%08x returned status 0x%08x\n", ++ buf[2], buf[1]); ++ ret = -EINVAL; ++ } ++ ++ dma_free_coherent(fw->cl.dev, PAGE_ALIGN(size), buf, bus_addr); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rpi_firmware_property_list); ++ ++/** ++ * rpi_firmware_property - Submit single firmware property ++ * @fw: Pointer to firmware structure from rpi_firmware_get(). ++ * @tag: One of enum_mbox_property_tag. ++ * @tag_data: Tag data buffer. ++ * @buf_size: Buffer size. ++ * ++ * Submits a single tag to the VPU firmware through the mailbox ++ * property interface. ++ * ++ * This is a convenience wrapper around ++ * rpi_firmware_property_list() to avoid some of the ++ * boilerplate in property calls. ++ */ ++int rpi_firmware_property(struct rpi_firmware *fw, ++ u32 tag, void *tag_data, size_t buf_size) ++{ ++ /* Single tags are very small (generally 8 bytes), so the ++ * stack should be safe. ++ */ ++ u8 data[buf_size + sizeof(struct rpi_firmware_property_tag_header)]; ++ struct rpi_firmware_property_tag_header *header = ++ (struct rpi_firmware_property_tag_header *)data; ++ int ret; ++ ++ header->tag = tag; ++ header->buf_size = buf_size; ++ header->req_resp_size = 0; ++ memcpy(data + sizeof(struct rpi_firmware_property_tag_header), ++ tag_data, buf_size); ++ ++ ret = rpi_firmware_property_list(fw, &data, sizeof(data)); ++ memcpy(tag_data, ++ data + sizeof(struct rpi_firmware_property_tag_header), ++ buf_size); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rpi_firmware_property); ++ ++static void ++rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) ++{ ++ u32 packet; ++ int ret = rpi_firmware_property(fw, ++ RPI_FIRMWARE_GET_FIRMWARE_REVISION, ++ &packet, sizeof(packet)); ++ ++ if (ret == 0) { ++ struct tm tm; ++ ++ time_to_tm(packet, 0, &tm); ++ ++ dev_info(fw->cl.dev, ++ "Attached to firmware from %04ld-%02d-%02d %02d:%02d\n", ++ tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, ++ tm.tm_hour, tm.tm_min); ++ } ++} ++ ++static int rpi_firmware_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rpi_firmware *fw; ++ ++ fw = devm_kzalloc(dev, sizeof(*fw), GFP_KERNEL); ++ if (!fw) ++ return -ENOMEM; ++ ++ fw->cl.dev = dev; ++ fw->cl.rx_callback = response_callback; ++ fw->cl.tx_block = true; ++ ++ fw->chan = mbox_request_channel(&fw->cl, 0); ++ if (IS_ERR(fw->chan)) { ++ int ret = PTR_ERR(fw->chan); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "Failed to get mbox channel: %d\n", ret); ++ return ret; ++ } ++ ++ init_completion(&fw->c); ++ ++ platform_set_drvdata(pdev, fw); ++ ++ rpi_firmware_print_firmware_revision(fw); ++ ++ return 0; ++} ++ ++static int rpi_firmware_remove(struct platform_device *pdev) ++{ ++ struct rpi_firmware *fw = platform_get_drvdata(pdev); ++ ++ mbox_free_channel(fw->chan); ++ ++ return 0; ++} ++ ++/** ++ * rpi_firmware_get - Get pointer to rpi_firmware structure. ++ * @firmware_node: Pointer to the firmware Device Tree node. ++ * ++ * Returns NULL is the firmware device is not ready. ++ */ ++struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node) ++{ ++ struct platform_device *pdev = of_find_device_by_node(firmware_node); ++ ++ if (!pdev) ++ return NULL; ++ ++ return platform_get_drvdata(pdev); ++} ++EXPORT_SYMBOL_GPL(rpi_firmware_get); ++ ++static const struct of_device_id rpi_firmware_of_match[] = { ++ { .compatible = "raspberrypi,bcm2835-firmware", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, rpi_firmware_of_match); ++ ++static struct platform_driver rpi_firmware_driver = { ++ .driver = { ++ .name = "raspberrypi-firmware", ++ .of_match_table = rpi_firmware_of_match, ++ }, ++ .probe = rpi_firmware_probe, ++ .remove = rpi_firmware_remove, ++}; ++module_platform_driver(rpi_firmware_driver); ++ ++MODULE_AUTHOR("Eric Anholt "); ++MODULE_DESCRIPTION("Raspberry Pi firmware driver"); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/include/soc/bcm2835/raspberrypi-firmware.h +@@ -0,0 +1,115 @@ ++/* ++ * Copyright © 2015 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++struct rpi_firmware; ++ ++enum rpi_firmware_property_status { ++ RPI_FIRMWARE_STATUS_REQUEST = 0, ++ RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000, ++ RPI_FIRMWARE_STATUS_ERROR = 0x80000001, ++}; ++ ++/** ++ * struct rpi_firmware_property_tag_header - Firmware property tag header ++ * @tag: One of enum_mbox_property_tag. ++ * @buf_size: The number of bytes in the value buffer following this ++ * struct. ++ * @req_resp_size: On submit, the length of the request (though it doesn't ++ * appear to be currently used by the firmware). On return, ++ * the length of the response (always 4 byte aligned), with ++ * the low bit set. ++ */ ++struct rpi_firmware_property_tag_header { ++ u32 tag; ++ u32 buf_size; ++ u32 req_resp_size; ++}; ++ ++enum rpi_firmware_property_tag { ++ RPI_FIRMWARE_PROPERTY_END = 0, ++ RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001, ++ ++ RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010, ++ RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011, ++ ++ RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001, ++ RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002, ++ RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003, ++ RPI_FIRMWARE_GET_BOARD_SERIAL = 0x00010004, ++ RPI_FIRMWARE_GET_ARM_MEMORY = 0x00010005, ++ RPI_FIRMWARE_GET_VC_MEMORY = 0x00010006, ++ RPI_FIRMWARE_GET_CLOCKS = 0x00010007, ++ RPI_FIRMWARE_GET_POWER_STATE = 0x00020001, ++ RPI_FIRMWARE_GET_TIMING = 0x00020002, ++ RPI_FIRMWARE_SET_POWER_STATE = 0x00028001, ++ RPI_FIRMWARE_GET_CLOCK_STATE = 0x00030001, ++ RPI_FIRMWARE_GET_CLOCK_RATE = 0x00030002, ++ RPI_FIRMWARE_GET_VOLTAGE = 0x00030003, ++ RPI_FIRMWARE_GET_MAX_CLOCK_RATE = 0x00030004, ++ RPI_FIRMWARE_GET_MAX_VOLTAGE = 0x00030005, ++ RPI_FIRMWARE_GET_TEMPERATURE = 0x00030006, ++ RPI_FIRMWARE_GET_MIN_CLOCK_RATE = 0x00030007, ++ RPI_FIRMWARE_GET_MIN_VOLTAGE = 0x00030008, ++ RPI_FIRMWARE_GET_TURBO = 0x00030009, ++ RPI_FIRMWARE_GET_MAX_TEMPERATURE = 0x0003000a, ++ RPI_FIRMWARE_ALLOCATE_MEMORY = 0x0003000c, ++ RPI_FIRMWARE_LOCK_MEMORY = 0x0003000d, ++ RPI_FIRMWARE_UNLOCK_MEMORY = 0x0003000e, ++ RPI_FIRMWARE_RELEASE_MEMORY = 0x0003000f, ++ RPI_FIRMWARE_EXECUTE_CODE = 0x00030010, ++ RPI_FIRMWARE_EXECUTE_QPU = 0x00030011, ++ RPI_FIRMWARE_SET_ENABLE_QPU = 0x00030012, ++ RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014, ++ RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020, ++ RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001, ++ RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002, ++ RPI_FIRMWARE_SET_VOLTAGE = 0x00038003, ++ RPI_FIRMWARE_SET_TURBO = 0x00038009, ++ ++ /* Dispmanx TAGS */ ++ RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 0x00040001, ++ RPI_FIRMWARE_FRAMEBUFFER_BLANK = 0x00040002, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_DEPTH = 0x00040005, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_PIXEL_ORDER = 0x00040006, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_ALPHA_MODE = 0x00040007, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH = 0x00040008, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 0x00040009, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN = 0x0004000a, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE = 0x0004000b, ++ RPI_FIRMWARE_FRAMEBUFFER_RELEASE = 0x00048001, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 0x00044004, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH = 0x00044005, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER = 0x00044006, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_ALPHA_MODE = 0x00044007, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 0x00044009, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN = 0x0004400a, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE = 0x0004400b, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH = 0x00048005, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER = 0x00048006, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE = 0x00048007, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 0x00048009, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 0x0004800b, ++ ++ RPI_FIRMWARE_GET_COMMAND_LINE = 0x00050001, ++ RPI_FIRMWARE_GET_DMA_CHANNELS = 0x00060001, ++}; ++ ++int rpi_firmware_property(struct rpi_firmware *fw, ++ u32 tag, void *data, size_t len); ++int rpi_firmware_property_list(struct rpi_firmware *fw, ++ void *data, size_t tag_size); ++struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node); diff --git a/target/linux/brcm2708/patches-4.1/0078-config-Enable-ZSMALLOC-ZRAM-and-PGTABLE_MAPPING.patch b/target/linux/brcm2708/patches-4.1/0078-config-Enable-ZSMALLOC-ZRAM-and-PGTABLE_MAPPING.patch new file mode 100644 index 0000000..e693eb8 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0078-config-Enable-ZSMALLOC-ZRAM-and-PGTABLE_MAPPING.patch @@ -0,0 +1,50 @@ +From 860bf6384964fbbaf4ffddeffe7fc86ecf1b2d3f Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Sun, 22 Mar 2015 13:33:23 +0000 +Subject: [PATCH 078/203] config: Enable ZSMALLOC, ZRAM and PGTABLE_MAPPING + +--- + arch/arm/configs/bcm2709_defconfig | 4 ++++ + arch/arm/configs/bcmrpi_defconfig | 4 ++++ + 2 files changed, 8 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -49,6 +49,8 @@ CONFIG_OABI_COMPAT=y + CONFIG_CLEANCACHE=y + CONFIG_FRONTSWAP=y + CONFIG_CMA=y ++CONFIG_ZSMALLOC=m ++CONFIG_PGTABLE_MAPPING=y + CONFIG_UACCESS_WITH_MEMCPY=y + CONFIG_SECCOMP=y + CONFIG_ZBOOT_ROM_TEXT=0x0 +@@ -389,6 +391,8 @@ CONFIG_DEVTMPFS=y + CONFIG_DEVTMPFS_MOUNT=y + CONFIG_DMA_CMA=y + CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_ZRAM=m ++CONFIG_ZRAM_LZ4_COMPRESS=y + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_DRBD=m +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -44,6 +44,8 @@ CONFIG_OABI_COMPAT=y + CONFIG_CLEANCACHE=y + CONFIG_FRONTSWAP=y + CONFIG_CMA=y ++CONFIG_ZSMALLOC=m ++CONFIG_PGTABLE_MAPPING=y + CONFIG_UACCESS_WITH_MEMCPY=y + CONFIG_SECCOMP=y + CONFIG_ZBOOT_ROM_TEXT=0x0 +@@ -382,6 +384,8 @@ CONFIG_DEVTMPFS=y + CONFIG_DEVTMPFS_MOUNT=y + CONFIG_DMA_CMA=y + CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_ZRAM=m ++CONFIG_ZRAM_LZ4_COMPRESS=y + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_DRBD=m diff --git a/target/linux/brcm2708/patches-4.1/0079-Add-rpi-ft5406-overlay-Add-rpi-ft5406-driver-as-modu.patch b/target/linux/brcm2708/patches-4.1/0079-Add-rpi-ft5406-overlay-Add-rpi-ft5406-driver-as-modu.patch new file mode 100644 index 0000000..1393e1a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0079-Add-rpi-ft5406-overlay-Add-rpi-ft5406-driver-as-modu.patch @@ -0,0 +1,78 @@ +From 4cfd7572f78d82a3e30c213f142ecc0d7f7cde7d Mon Sep 17 00:00:00 2001 +From: Gordon Hollingworth +Date: Mon, 22 Jun 2015 16:27:07 +0100 +Subject: [PATCH 079/203] Add rpi-ft5406 overlay Add rpi-ft5406 driver as + module + +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 5 +++++ + arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts | 16 ++++++++++++++++ + arch/arm/configs/bcm2709_defconfig | 1 + + arch/arm/configs/bcmrpi_defconfig | 1 + + 5 files changed, 24 insertions(+) + create mode 100644 arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -35,6 +35,7 @@ dtb-$(RPI_DT_OVERLAYS) += pitft28-resist + dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-proto-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -396,6 +396,11 @@ Params: speed Display + + xohms Touchpanel sensitivity (X-plate resistance) + ++Name: rpi-ft5406 ++Info: Official Raspberry Pi display touchscreen ++Load: dtoverlay=rpi-ft5406 ++Params: ++ + + Name: rpi-proto + Info: Configures the RPi Proto audio card +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts +@@ -0,0 +1,16 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ rpi_ft5406: rpi_ft5406 { ++ compatible = "rpi,rpi-ft5406"; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -535,6 +535,7 @@ CONFIG_JOYSTICK_XPAD_FF=y + CONFIG_INPUT_TOUCHSCREEN=y + CONFIG_TOUCHSCREEN_ADS7846=m + CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_RPI_FT5406=m + CONFIG_TOUCHSCREEN_USB_COMPOSITE=m + CONFIG_TOUCHSCREEN_STMPE=m + CONFIG_INPUT_MISC=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -528,6 +528,7 @@ CONFIG_JOYSTICK_XPAD_FF=y + CONFIG_INPUT_TOUCHSCREEN=y + CONFIG_TOUCHSCREEN_ADS7846=m + CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_RPI_FT5406=m + CONFIG_TOUCHSCREEN_USB_COMPOSITE=m + CONFIG_TOUCHSCREEN_STMPE=m + CONFIG_INPUT_MISC=y diff --git a/target/linux/brcm2708/patches-4.1/0080-Fix-driver-detection-failure-Check-that-the-buffer-r.patch b/target/linux/brcm2708/patches-4.1/0080-Fix-driver-detection-failure-Check-that-the-buffer-r.patch new file mode 100644 index 0000000..caed159 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0080-Fix-driver-detection-failure-Check-that-the-buffer-r.patch @@ -0,0 +1,21 @@ +From 1cefedfe457ea7c738ab1c10ec88fd8a5632444a Mon Sep 17 00:00:00 2001 +From: Gordon Hollingworth +Date: Tue, 23 Jun 2015 09:53:40 +0100 +Subject: [PATCH 080/203] Fix driver detection failure Check that the buffer + response is non-zero meaning the touchscreen was detected + +--- + drivers/input/touchscreen/rpi-ft5406.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/input/touchscreen/rpi-ft5406.c ++++ b/drivers/input/touchscreen/rpi-ft5406.c +@@ -184,7 +184,7 @@ static int ft5406_probe(struct platform_ + + bcm_mailbox_property(&request, sizeof(request)); + +- if(request.request_code == VCMSG_REQUEST_SUCCESSFUL) ++ if(request.request_code == VCMSG_REQUEST_SUCCESSFUL && request.tag.val != 0) + { + dev_dbg(&pdev->dev, "Got TS buffer 0x%x\n", request.tag.val); + } diff --git a/target/linux/brcm2708/patches-4.1/0081-config-Enable-8250-serial-port.patch b/target/linux/brcm2708/patches-4.1/0081-config-Enable-8250-serial-port.patch new file mode 100644 index 0000000..61c5e9e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0081-config-Enable-8250-serial-port.patch @@ -0,0 +1,46 @@ +From 35a332275ed70e1740874efbc34b22528995c213 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Tue, 23 Jun 2015 13:24:01 +0100 +Subject: [PATCH 081/203] config: Enable 8250 serial port + +--- + arch/arm/configs/bcm2709_defconfig | 7 +++++++ + arch/arm/configs/bcmrpi_defconfig | 7 +++++++ + 2 files changed, 14 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -557,8 +557,15 @@ CONFIG_GAMEPORT_L4=m + CONFIG_DEVPTS_MULTIPLE_INSTANCES=y + # CONFIG_LEGACY_PTYS is not set + # CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set ++CONFIG_SERIAL_8250_CONSOLE=y ++# CONFIG_SERIAL_8250_DMA is not set ++CONFIG_SERIAL_8250_NR_UARTS=1 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=1 + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_SERIAL_OF_PLATFORM=y + CONFIG_TTY_PRINTK=y + CONFIG_HW_RANDOM=y + CONFIG_HW_RANDOM_BCM2835=m +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -550,8 +550,15 @@ CONFIG_GAMEPORT_L4=m + CONFIG_DEVPTS_MULTIPLE_INSTANCES=y + # CONFIG_LEGACY_PTYS is not set + # CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set ++CONFIG_SERIAL_8250_CONSOLE=y ++# CONFIG_SERIAL_8250_DMA is not set ++CONFIG_SERIAL_8250_NR_UARTS=1 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=1 + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_SERIAL_OF_PLATFORM=y + CONFIG_TTY_PRINTK=y + CONFIG_HW_RANDOM=y + CONFIG_HW_RANDOM_BCM2835=m diff --git a/target/linux/brcm2708/patches-4.1/0082-config-Enable-POWER_RESET_GPIO.patch b/target/linux/brcm2708/patches-4.1/0082-config-Enable-POWER_RESET_GPIO.patch new file mode 100644 index 0000000..d87a865 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0082-config-Enable-POWER_RESET_GPIO.patch @@ -0,0 +1,32 @@ +From f8fad3ba247648ef30b116a12a45672fb11e8ade Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Tue, 23 Jun 2015 14:10:58 +0100 +Subject: [PATCH 082/203] config: Enable POWER_RESET_GPIO + +--- + arch/arm/configs/bcm2709_defconfig | 2 ++ + arch/arm/configs/bcmrpi_defconfig | 2 ++ + 2 files changed, 4 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -606,6 +606,8 @@ CONFIG_W1_SLAVE_DS2781=m + CONFIG_W1_SLAVE_DS28E04=m + CONFIG_W1_SLAVE_BQ27000=m + CONFIG_BATTERY_DS2760=m ++CONFIG_POWER_RESET=y ++CONFIG_POWER_RESET_GPIO=y + # CONFIG_HWMON is not set + CONFIG_THERMAL=y + CONFIG_THERMAL_BCM2835=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -599,6 +599,8 @@ CONFIG_W1_SLAVE_DS2781=m + CONFIG_W1_SLAVE_DS28E04=m + CONFIG_W1_SLAVE_BQ27000=m + CONFIG_BATTERY_DS2760=m ++CONFIG_POWER_RESET=y ++CONFIG_POWER_RESET_GPIO=y + # CONFIG_HWMON is not set + CONFIG_THERMAL=y + CONFIG_THERMAL_BCM2835=y diff --git a/target/linux/brcm2708/patches-4.1/0083-bcm2708-vcio-Remove-restriction-of-only-a-single-ins.patch b/target/linux/brcm2708/patches-4.1/0083-bcm2708-vcio-Remove-restriction-of-only-a-single-ins.patch new file mode 100644 index 0000000..bf98fbd --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0083-bcm2708-vcio-Remove-restriction-of-only-a-single-ins.patch @@ -0,0 +1,45 @@ +From f789239f3014997243c1f46e74c7f653d3826503 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Fri, 26 Jun 2015 17:37:38 +0100 +Subject: [PATCH 083/203] bcm2708-vcio: Remove restriction of only a single + instance being open + +We need more than one process to be able to use mailbox interface (e.g. HW cursor in fbturbo and hello_fft). +Locking should be handled on each mailbox access +--- + drivers/mailbox/bcm2708-vcio.c | 14 -------------- + 1 file changed, 14 deletions(-) + +--- a/drivers/mailbox/bcm2708-vcio.c ++++ b/drivers/mailbox/bcm2708-vcio.c +@@ -242,20 +242,9 @@ EXPORT_SYMBOL_GPL(bcm_mailbox_property); + + /* Platform Device for Mailbox */ + +-/* +- * Is the device open right now? Used to prevent +- * concurent access into the same device +- */ +-static bool device_is_open; +- + /* This is called whenever a process attempts to open the device file */ + static int device_open(struct inode *inode, struct file *file) + { +- /* We don't want to talk to two processes at the same time */ +- if (device_is_open) +- return -EBUSY; +- +- device_is_open = true; + try_module_get(THIS_MODULE); + + return 0; +@@ -263,9 +252,6 @@ static int device_open(struct inode *ino + + static int device_release(struct inode *inode, struct file *file) + { +- /* We're now ready for our next caller */ +- device_is_open = false; +- + module_put(THIS_MODULE); + + return 0; diff --git a/target/linux/brcm2708/patches-4.1/0084-BCM270X_DT-Create-a-core-clock-use-it-for-SPI-and-sd.patch b/target/linux/brcm2708/patches-4.1/0084-BCM270X_DT-Create-a-core-clock-use-it-for-SPI-and-sd.patch new file mode 100644 index 0000000..3b7c875 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0084-BCM270X_DT-Create-a-core-clock-use-it-for-SPI-and-sd.patch @@ -0,0 +1,141 @@ +From 9e38795e9be092bf1197991af1ab9ea7a511fbad Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 26 Jun 2015 08:39:19 +0100 +Subject: [PATCH 084/203] BCM270X_DT: Create a "core" clock, use it for SPI and + sdhost + +--- + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 1 + + arch/arm/boot/dts/bcm2708-rpi-b.dts | 1 + + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 1 + + arch/arm/boot/dts/bcm2708_common.dtsi | 6 +++--- + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 1 + + arch/arm/boot/dts/overlays/sdhost-overlay.dts | 28 ++------------------------- + 6 files changed, 9 insertions(+), 29 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +@@ -124,6 +124,7 @@ + i2c1 = <&i2c1>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ core_freq = <&clk_core>,"clock-frequency:0"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; +--- a/arch/arm/boot/dts/bcm2708-rpi-b.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts +@@ -118,6 +118,7 @@ + i2c1 = <&i2c1>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ core_freq = <&clk_core>,"clock-frequency:0"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +@@ -14,5 +14,6 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ core_freq = <&clk_core>,"clock-frequency:0"; + }; + }; +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -110,7 +110,7 @@ + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204000 0x1000>; + interrupts = <2 22>; +- clocks = <&clk_spi>; ++ clocks = <&clk_core>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; +@@ -203,11 +203,11 @@ + clock-frequency = <250000000>; + }; + +- clk_spi: clock@2 { ++ clk_core: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + #clock-cells = <0>; +- clock-output-names = "spi"; ++ clock-output-names = "core"; + clock-frequency = <250000000>; + }; + +--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts ++++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +@@ -124,6 +124,7 @@ + i2c1 = <&i2c1>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ core_freq = <&clk_core>,"clock-frequency:0"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; +--- a/arch/arm/boot/dts/overlays/sdhost-overlay.dts ++++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts +@@ -16,7 +16,7 @@ + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_pins>; + interrupts = <2 24>; +- clocks = <&clk_sdhost>; ++ clocks = <&clk_core>; + dmas = <&dma 13>, + <&dma 13>; + dma-names = "tx", "rx"; +@@ -29,22 +29,6 @@ + }; + + fragment@1 { +- target = <&clocks>; +- __overlay__ { +- #address-cells = <1>; +- #size-cells = <0>; +- +- clk_sdhost: sdhost { +- compatible = "fixed-clock"; +- reg = <0>; +- #clock-cells = <0>; +- clock-output-names = "sdhost"; +- clock-frequency = <250000000>; +- }; +- }; +- }; +- +- fragment@2 { + target = <&gpio>; + __overlay__ { + sdhost_pins: sdhost_pins { +@@ -54,7 +38,7 @@ + }; + }; + +- fragment@3 { ++ fragment@2 { + target = <&mmc>; + __overlay__ { + /* Find a way to disable the other driver */ +@@ -63,18 +47,10 @@ + }; + }; + +- fragment@4 { +- target-path = "/__overrides__"; +- __overlay__ { +- sdhost_freq = <&clk_sdhost>,"clock-frequency:0"; +- }; +- }; +- + __overrides__ { + overclock_50 = <&sdhost>,"brcm,overclock-50:0"; + force_pio = <&sdhost>,"brcm,force-pio?"; + pio_limit = <&sdhost>,"brcm,pio-limit:0"; + debug = <&sdhost>,"brcm,debug?"; +- sdhost_freq = <&clk_sdhost>,"clock-frequency:0"; + }; + }; diff --git a/target/linux/brcm2708/patches-4.1/0085-BCM270X_DT-Add-MCP7941X-to-i2c-rtc-overlay.patch b/target/linux/brcm2708/patches-4.1/0085-BCM270X_DT-Add-MCP7941X-to-i2c-rtc-overlay.patch new file mode 100644 index 0000000..8143dc5 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0085-BCM270X_DT-Add-MCP7941X-to-i2c-rtc-overlay.patch @@ -0,0 +1,51 @@ +From 3d715851687737bec0ecee73b8f04d47d7a29bed Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 24 Jun 2015 09:24:31 +0100 +Subject: [PATCH 085/203] BCM270X_DT: Add MCP7941X to i2c-rtc overlay + +--- + arch/arm/boot/dts/overlays/README | 3 +++ + arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts | 6 ++++++ + 2 files changed, 9 insertions(+) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -253,6 +253,8 @@ Params: ds1307 Select + + ds3231 Select the DS3231 device + ++ mcp7941x Select the MCP7941x device ++ + pcf2127 Select the PCF2127 device + + pcf8523 Select the PCF8523 device +@@ -396,6 +398,7 @@ Params: speed Display + + xohms Touchpanel sensitivity (X-plate resistance) + ++ + Name: rpi-ft5406 + Info: Official Raspberry Pi display touchscreen + Load: dtoverlay=rpi-ft5406 +--- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts ++++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts +@@ -17,6 +17,11 @@ + reg = <0x68>; + status = "disable"; + }; ++ mcp7941x: mcp7941x@6f { ++ compatible = "microchip,mcp7941x"; ++ reg = <0x6f>; ++ status = "disable"; ++ }; + ds3231: ds3231@68 { + compatible = "maxim,ds3231"; + reg = <0x68>; +@@ -42,6 +47,7 @@ + __overrides__ { + ds1307 = <&ds1307>,"status"; + ds3231 = <&ds3231>,"status"; ++ mcp7941x = <&mcp7941x>,"status"; + pcf2127 = <&pcf2127>,"status"; + pcf8523 = <&pcf8523>,"status"; + pcf8563 = <&pcf8563>,"status"; diff --git a/target/linux/brcm2708/patches-4.1/0086-dts-overlays-document-DHT11-overlay.patch b/target/linux/brcm2708/patches-4.1/0086-dts-overlays-document-DHT11-overlay.patch new file mode 100644 index 0000000..e7a15c2 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0086-dts-overlays-document-DHT11-overlay.patch @@ -0,0 +1,26 @@ +From 243585439bab9e3181082c6422a51bddce2e1535 Mon Sep 17 00:00:00 2001 +From: P33M +Date: Wed, 24 Jun 2015 11:23:06 +0100 +Subject: [PATCH 086/203] dts/overlays: document DHT11 overlay + +--- + arch/arm/boot/dts/overlays/README | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -173,6 +173,14 @@ Load: dtoverlay=bmp085_i2c-sensor + Params: + + ++Name: dht11 ++Info: Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors ++ Also sometimes found with the part number(s) AM230x. ++Load: dtoverlay=dht11,= ++Params: gpiopin GPIO connected to the sensor's DATA output. ++ (default 4) ++ ++ + [ The ds1307-rtc overlay has been deleted. See i2c-rtc. ] + + diff --git a/target/linux/brcm2708/patches-4.1/0087-gpio-poweroff-Allow-it-to-work-on-Raspberry-Pi.patch b/target/linux/brcm2708/patches-4.1/0087-gpio-poweroff-Allow-it-to-work-on-Raspberry-Pi.patch new file mode 100644 index 0000000..5c71a05 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0087-gpio-poweroff-Allow-it-to-work-on-Raspberry-Pi.patch @@ -0,0 +1,108 @@ +From 1e890a091e0fbd61101fac37c8570c414deda17f Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 25 Jun 2015 12:16:11 +0100 +Subject: [PATCH 087/203] gpio-poweroff: Allow it to work on Raspberry Pi + +The Raspberry Pi firmware manages the power-down and reboot +process. To do this it installs a pm_power_off handler, causing +the gpio-poweroff module to abort the probe function. + +This patch introduces a "force" DT property that overrides that +behaviour, and also adds a DT overlay to enable and control it. + +Note that running in an active-low configuration (DT parameter +"active_low") requires a custom dt-blob.bin and probably won't +allow a reboot without switching off, so an external inversion +of the trigger signal may be preferable. +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 13 +++++++++ + .../boot/dts/overlays/gpio-poweroff-overlay.dts | 34 ++++++++++++++++++++++ + drivers/power/reset/gpio-poweroff.c | 4 ++- + 4 files changed, 51 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -16,6 +16,7 @@ dtb-$(RPI_DT_OVERLAYS) += ads7846-overla + dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += gpio-poweroff-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += hifiberry-dacplus-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -192,6 +192,19 @@ Params: int_pin GPIO us + speed SPI bus speed (default 12000000) + + ++Name: gpio-poweroff ++Info: Drives a GPIO high or low on reboot ++Load: gpio-poweroff,= ++Params: gpiopin GPIO for signalling (default 26) ++ ++ active_low Set if the power control device requires a ++ high->low transition to trigger a power-down. ++ Note that this will require the support of a ++ custom dt-blob.bin to prevent a power-down ++ during the boot process, and that a reboot ++ will also cause the pin to go low. ++ ++ + Name: hifiberry-amp + Info: Configures the HifiBerry Amp and Amp+ audio cards + Load: dtoverlay=hifiberry-amp +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts +@@ -0,0 +1,34 @@ ++// Definitions for gpio-poweroff module ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ power_ctrl: power_ctrl { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio 26 0>; ++ force; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ power_ctrl_pins: power_ctrl_pins { ++ brcm,pins = <26>; ++ brcm,function = <1>; // out ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&power_ctrl>,"gpios:4", ++ <&power_ctrl_pins>,"brcm,pins:0"; ++ active_low = <&power_ctrl>,"gpios:8"; ++ }; ++}; +--- a/drivers/power/reset/gpio-poweroff.c ++++ b/drivers/power/reset/gpio-poweroff.c +@@ -48,9 +48,11 @@ static void gpio_poweroff_do_poweroff(vo + static int gpio_poweroff_probe(struct platform_device *pdev) + { + bool input = false; ++ bool force = false; + + /* If a pm_power_off function has already been added, leave it alone */ +- if (pm_power_off != NULL) { ++ force = of_property_read_bool(pdev->dev.of_node, "force"); ++ if (!force && (pm_power_off != NULL)) { + dev_err(&pdev->dev, + "%s: pm_power_off function already registered", + __func__); diff --git a/target/linux/brcm2708/patches-4.1/0088-BCM270x_DT-Default-Compute-Module-i2c-i2s-and-spi-su.patch b/target/linux/brcm2708/patches-4.1/0088-BCM270x_DT-Default-Compute-Module-i2c-i2s-and-spi-su.patch new file mode 100644 index 0000000..c1bef5f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0088-BCM270x_DT-Default-Compute-Module-i2c-i2s-and-spi-su.patch @@ -0,0 +1,90 @@ +From 80dc9b95432ba5c368ef61925390c44de4211e83 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 17 Jun 2015 17:10:40 +0100 +Subject: [PATCH 088/203] BCM270x_DT: Default Compute Module i2c, i2s and spi + support + +--- + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 67 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 67 insertions(+) + +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +@@ -10,10 +10,77 @@ + status = "okay"; + }; + ++&gpio { ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <18 19 20 21>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ + / { + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; + core_freq = <&clk_core>,"clock-frequency:0"; + }; + }; diff --git a/target/linux/brcm2708/patches-4.1/0089-BCM270X_DT-Sort-nodes-by-bus-address-and-consolidate.patch b/target/linux/brcm2708/patches-4.1/0089-BCM270X_DT-Sort-nodes-by-bus-address-and-consolidate.patch new file mode 100644 index 0000000..2d43a7b --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0089-BCM270X_DT-Sort-nodes-by-bus-address-and-consolidate.patch @@ -0,0 +1,234 @@ +From 63e7ed7e81a19be754aa1515835599b9d97b3467 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 22 Jun 2015 14:21:55 +0100 +Subject: [PATCH 089/203] BCM270X_DT: Sort nodes by bus address, and + consolidate aliases + +--- + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 19 ---------- + arch/arm/boot/dts/bcm2708-rpi-b.dts | 19 ---------- + arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 21 ----------- + arch/arm/boot/dts/bcm2708_common.dtsi | 63 +++++++++++++++++++++++--------- + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 19 ---------- + 5 files changed, 46 insertions(+), 95 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +@@ -5,25 +5,6 @@ + / { + compatible = "brcm,bcm2708"; + model = "Raspberry Pi Model B+"; +- +- aliases { +- soc = &soc; +- spi0 = &spi0; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2s = &i2s; +- gpio = &gpio; +- intc = &intc; +- leds = &leds; +- audio = &audio; +- sound = &sound; +- uart0 = &uart0; +- uart1 = &uart1; +- clocks = &clocks; +- }; +- +- sound: sound { +- }; + }; + + &gpio { +--- a/arch/arm/boot/dts/bcm2708-rpi-b.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts +@@ -5,25 +5,6 @@ + / { + compatible = "brcm,bcm2708"; + model = "Raspberry Pi Model B"; +- +- aliases { +- soc = &soc; +- spi0 = &spi0; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2s = &i2s; +- gpio = &gpio; +- intc = &intc; +- leds = &leds; +- audio = &audio; +- sound = &sound; +- uart0 = &uart0; +- uart1 = &uart1; +- clocks = &clocks; +- }; +- +- sound: sound { +- }; + }; + + &gpio { +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi +@@ -1,26 +1,5 @@ + /include/ "bcm2708.dtsi" + +-/ { +- aliases { +- soc = &soc; +- spi0 = &spi0; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2s = &i2s; +- gpio = &gpio; +- intc = &intc; +- leds = &leds; +- audio = &audio; +- sound = &sound; +- uart0 = &uart0; +- uart1 = &uart1; +- clocks = &clocks; +- }; +- +- sound: sound { +- }; +-}; +- + &leds { + act_led: act { + label = "led0"; +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -3,6 +3,31 @@ + / { + interrupt-parent = <&intc>; + ++ aliases { ++ audio = &audio; ++ sound = &sound; ++ soc = &soc; ++ dma = &dma; ++ intc = &intc; ++ watchdog = &watchdog; ++ random = &random; ++ mailbox = &mailbox; ++ gpio = &gpio; ++ uart0 = &uart0; ++ i2s = &i2s; ++ spi0 = &spi0; ++ i2c0 = &i2c0; ++ uart1 = &uart1; ++ mmc = &mmc; ++ i2c1 = &i2c1; ++ usb = &usb; ++ leds = &leds; ++ fb = &fb; ++ vchiq = &vchiq; ++ thermal = &thermal; ++ clocks = &clocks; ++ }; ++ + /* Onboard audio */ + audio: audio { + compatible = "brcm,bcm2835-audio"; +@@ -10,6 +35,10 @@ + status = "disabled"; + }; + ++ /* External sound card */ ++ sound: sound { ++ }; ++ + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; +@@ -43,6 +72,12 @@ + #interrupt-cells = <2>; + }; + ++ mailbox: mailbox@7e00b800 { ++ compatible = "brcm,bcm2708-vcio"; ++ reg = <0x7e00b880 0x40>; ++ interrupts = <0 1>; ++ }; ++ + watchdog: watchdog@7e100000 { + compatible = "brcm,bcm2835-pm-wdt"; + reg = <0x7e100000 0x28>; +@@ -55,12 +90,6 @@ + status = "disabled"; + }; + +- mailbox: mailbox@7e00b800 { +- compatible = "brcm,bcm2708-vcio"; +- reg = <0x7e00b880 0x40>; +- interrupts = <0 1>; +- }; +- + gpio: gpio { + compatible = "brcm,bcm2835-gpio"; + reg = <0x7e200000 0xb4>; +@@ -73,17 +102,6 @@ + #interrupt-cells = <2>; + }; + +- mmc: mmc@7e300000 { +- compatible = "brcm,bcm2835-mmc"; +- reg = <0x7e300000 0x100>; +- interrupts = <2 30>; +- clocks = <&clk_mmc>; +- dmas = <&dma 11>, +- <&dma 11>; +- dma-names = "tx", "rx"; +- status = "disabled"; +- }; +- + uart0: uart@7e201000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x1000>; +@@ -144,6 +162,17 @@ + status = "disabled"; + }; + ++ mmc: mmc@7e300000 { ++ compatible = "brcm,bcm2835-mmc"; ++ reg = <0x7e300000 0x100>; ++ interrupts = <2 30>; ++ clocks = <&clk_mmc>; ++ dmas = <&dma 11>, ++ <&dma 11>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ + i2c1: i2c@7e804000 { + compatible = "brcm,bcm2708-i2c"; + reg = <0x7e804000 0x1000>; +--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts ++++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +@@ -5,25 +5,6 @@ + / { + compatible = "brcm,bcm2709"; + model = "Raspberry Pi 2 Model B"; +- +- aliases { +- soc = &soc; +- spi0 = &spi0; +- i2c0 = &i2c0; +- i2c1 = &i2c1; +- i2s = &i2s; +- gpio = &gpio; +- intc = &intc; +- leds = &leds; +- audio = &audio; +- sound = &sound; +- uart0 = &uart0; +- uart1 = &uart1; +- clocks = &clocks; +- }; +- +- sound: sound { +- }; + }; + + &gpio { diff --git a/target/linux/brcm2708/patches-4.1/0090-i2c-bcm2708-BCM270X_DT-Add-support-for-I2C2.patch b/target/linux/brcm2708/patches-4.1/0090-i2c-bcm2708-BCM270X_DT-Add-support-for-I2C2.patch new file mode 100644 index 0000000..3aa4f79 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0090-i2c-bcm2708-BCM270X_DT-Add-support-for-I2C2.patch @@ -0,0 +1,163 @@ +From 5130d7fdc237418537e377b951dd388723de1502 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 22 Jun 2015 14:23:03 +0100 +Subject: [PATCH 090/203] i2c-bcm2708/BCM270X_DT: Add support for I2C2 + +The third I2C bus (I2C2) is normally reserved for HDMI use. Careless +use of this bus can break an attached display - use with caution. + +It is recommended to disable accesses by VideoCore by setting +hdmi_ignore_edid=1 or hdmi_edid_file=1 in config.txt. + +The interface is disabled by default - enable using the +i2c2_iknowwhatimdoing DT parameter. +--- + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 6 ++++++ + arch/arm/boot/dts/bcm2708-rpi-b.dts | 6 ++++++ + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 6 ++++++ + arch/arm/boot/dts/bcm2708_common.dtsi | 14 ++++++++++++++ + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 6 ++++++ + drivers/i2c/busses/i2c-bcm2708.c | 5 ++++- + 6 files changed, 42 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +@@ -75,6 +75,10 @@ + clock-frequency = <100000>; + }; + ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ + &i2s { + #sound-dai-cells = <0>; + pinctrl-names = "default"; +@@ -103,8 +107,10 @@ + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; + i2c1 = <&i2c1>,"status"; ++ i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; + core_freq = <&clk_core>,"clock-frequency:0"; + + act_led_gpio = <&act_led>,"gpios:4"; +--- a/arch/arm/boot/dts/bcm2708-rpi-b.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts +@@ -75,6 +75,10 @@ + clock-frequency = <100000>; + }; + ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ + &i2s { + #sound-dai-cells = <0>; + pinctrl-names = "default"; +@@ -97,8 +101,10 @@ + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; + i2c1 = <&i2c1>,"status"; ++ i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; + core_freq = <&clk_core>,"clock-frequency:0"; + + act_led_gpio = <&act_led>,"gpios:4"; +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +@@ -65,6 +65,10 @@ + clock-frequency = <100000>; + }; + ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ + &i2s { + #sound-dai-cells = <0>; + pinctrl-names = "default"; +@@ -79,8 +83,10 @@ + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; + i2c1 = <&i2c1>,"status"; ++ i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; + core_freq = <&clk_core>,"clock-frequency:0"; + }; + }; +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -20,6 +20,7 @@ + uart1 = &uart1; + mmc = &mmc; + i2c1 = &i2c1; ++ i2c2 = &i2c2; + usb = &usb; + leds = &leds; + fb = &fb; +@@ -179,6 +180,19 @@ + interrupts = <2 21>; + clocks = <&clk_i2c>; + #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@7e805000 { ++ // Beware - this is shared with the HDMI module. ++ // Careless use may break (really) your display. ++ // Caveat emptor. ++ compatible = "brcm,bcm2708-i2c"; ++ reg = <0x7e805000 0x1000>; ++ interrupts = <2 21>; ++ clocks = <&clk_i2c>; ++ #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts ++++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +@@ -75,6 +75,10 @@ + clock-frequency = <100000>; + }; + ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ + &i2s { + #sound-dai-cells = <0>; + pinctrl-names = "default"; +@@ -103,8 +107,10 @@ + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; + i2c1 = <&i2c1>,"status"; ++ i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; + core_freq = <&clk_core>,"clock-frequency:0"; + + act_led_gpio = <&act_led>,"gpios:4"; +--- a/drivers/i2c/busses/i2c-bcm2708.c ++++ b/drivers/i2c/busses/i2c-bcm2708.c +@@ -407,8 +407,11 @@ static int bcm2708_i2c_probe(struct plat + case 1: + adap->class = I2C_CLASS_DDC; + break; ++ case 2: ++ adap->class = I2C_CLASS_DDC; ++ break; + default: +- dev_err(&pdev->dev, "can only bind to BSC 0 or 1\n"); ++ dev_err(&pdev->dev, "can only bind to BSC 0, 1 or 2\n"); + err = -ENXIO; + goto out_free_bi; + } diff --git a/target/linux/brcm2708/patches-4.1/0091-BCM270X_DT-Correct-the-lirc-rpi-overlay-documentatio.patch b/target/linux/brcm2708/patches-4.1/0091-BCM270X_DT-Correct-the-lirc-rpi-overlay-documentatio.patch new file mode 100644 index 0000000..a79969b --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0091-BCM270X_DT-Correct-the-lirc-rpi-overlay-documentatio.patch @@ -0,0 +1,26 @@ +From 148fa81647d603e3ed8d38f7b9f37b6c04cace24 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 29 Jun 2015 12:14:02 +0100 +Subject: [PATCH 091/203] BCM270X_DT: Correct the lirc-rpi overlay + documentation + +The polarity of the "sense" parameter was inverted with respect to reality. + +See: https://github.com/raspberrypi/linux/issues/1038 +--- + arch/arm/boot/dts/overlays/README | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -313,8 +313,8 @@ Params: gpio_out_pin GPIO fo + (default "down") + + sense Override the IR receive auto-detection logic: +- "1" = force active high +- "0" = force active low ++ "0" = force active-high ++ "1" = force active-low + "-1" = use auto-detection + (default "-1") + diff --git a/target/linux/brcm2708/patches-4.1/0092-bcm2835-sdhost-Further-improve-overclock-back-off.patch b/target/linux/brcm2708/patches-4.1/0092-bcm2835-sdhost-Further-improve-overclock-back-off.patch new file mode 100644 index 0000000..2005627 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0092-bcm2835-sdhost-Further-improve-overclock-back-off.patch @@ -0,0 +1,292 @@ +From 8509eb475ed00c7d581cf05866a27fa48c4c007c Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 25 Jun 2015 08:47:09 +0100 +Subject: [PATCH 092/203] bcm2835-sdhost: Further improve overclock back-off + +--- + drivers/mmc/host/bcm2835-sdhost.c | 144 +++++++++++++++++++++----------------- + 1 file changed, 78 insertions(+), 66 deletions(-) + +--- a/drivers/mmc/host/bcm2835-sdhost.c ++++ b/drivers/mmc/host/bcm2835-sdhost.c +@@ -161,8 +161,6 @@ struct bcm2835_host { + + unsigned int use_busy:1; /* Wait for busy interrupt */ + +- unsigned int reduce_overclock:1; /* ...at the next opportunity */ +- + unsigned int debug:1; /* Enable debug output */ + + u32 thread_isr; +@@ -466,36 +464,25 @@ static void bcm2835_sdhost_dma_complete( + spin_unlock_irqrestore(&host->lock, flags); + } + +-static bool data_transfer_wait(struct bcm2835_host *host, const char *caller) ++static bool data_transfer_wait(struct bcm2835_host *host) + { + unsigned long timeout = 1000000; +- u32 hsts; + while (timeout) + { +- hsts = bcm2835_sdhost_read(host, SDHSTS); +- if (hsts & (SDHSTS_TRANSFER_ERROR_MASK | +- SDHSTS_DATA_FLAG)) { +- bcm2835_sdhost_write(host, SDHSTS_TRANSFER_ERROR_MASK, +- SDHSTS); ++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ if (sdhsts & SDHSTS_DATA_FLAG) { ++ bcm2835_sdhost_write(host, SDHSTS_DATA_FLAG, SDHSTS); + break; + } + timeout--; + } +- +- if (hsts & (SDHSTS_CRC16_ERROR | +- SDHSTS_CRC7_ERROR | +- SDHSTS_FIFO_ERROR)) { +- pr_err("%s: data error in %s - HSTS %x\n", +- mmc_hostname(host->mmc), caller, hsts); +- host->data->error = -EILSEQ; +- return false; +- } else if ((timeout == 0) || +- (hsts & (SDHSTS_CMD_TIME_OUT | +- SDHSTS_REW_TIME_OUT))) { +- pr_err("%s: timeout in %s - HSTS %x\n", +- mmc_hostname(host->mmc), caller, hsts); +- host->data->error = -ETIMEDOUT; +- return false; ++ if (timeout == 0) { ++ pr_err("%s: Data %s timeout\n", ++ mmc_hostname(host->mmc), ++ (host->data->flags & MMC_DATA_READ) ? "read" : "write"); ++ bcm2835_sdhost_dumpregs(host); ++ host->data->error = -ETIMEDOUT; ++ return false; + } + return true; + } +@@ -523,7 +510,7 @@ static void bcm2835_sdhost_read_block_pi + buf = (u32 *)host->sg_miter.addr; + + while (len) { +- if (!data_transfer_wait(host, "read_block_pio")) ++ if (!data_transfer_wait(host)) + break; + + *(buf++) = bcm2835_sdhost_read(host, SDDATA); +@@ -562,7 +549,7 @@ static void bcm2835_sdhost_write_block_p + buf = host->sg_miter.addr; + + while (len) { +- if (!data_transfer_wait(host, "write_block_pio")) ++ if (!data_transfer_wait(host)) + break; + + bcm2835_sdhost_write(host, *(buf++), SDDATA); +@@ -581,13 +568,33 @@ static void bcm2835_sdhost_write_block_p + + static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host) + { ++ u32 sdhsts; ++ bool is_read; + BUG_ON(!host->data); + +- if (host->data->flags & MMC_DATA_READ) { ++ is_read = (host->data->flags & MMC_DATA_READ) != 0; ++ if (is_read) + bcm2835_sdhost_read_block_pio(host); +- } else { ++ else + bcm2835_sdhost_write_block_pio(host); + ++ sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ if (sdhsts & (SDHSTS_CRC16_ERROR | ++ SDHSTS_CRC7_ERROR | ++ SDHSTS_FIFO_ERROR)) { ++ pr_err("%s: %s transfer error - HSTS %x\n", ++ mmc_hostname(host->mmc), ++ is_read ? "read" : "write", ++ sdhsts); ++ host->data->error = -EILSEQ; ++ } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | ++ SDHSTS_REW_TIME_OUT))) { ++ pr_err("%s: %s timeout error - HSTS %x\n", ++ mmc_hostname(host->mmc), ++ is_read ? "read" : "write", ++ sdhsts); ++ host->data->error = -ETIMEDOUT; ++ } else if (!is_read && !host->data->error) { + /* Start a timer in case a transfer error occurs because + there is no error interrupt */ + mod_timer(&host->pio_timer, jiffies + host->pio_timeout); +@@ -701,8 +708,9 @@ static void bcm2835_sdhost_prepare_data( + + void bcm2835_sdhost_send_command(struct bcm2835_host *host, struct mmc_command *cmd) + { +- u32 sdcmd; ++ u32 sdcmd, sdhsts; + unsigned long timeout; ++ int delay; + + WARN_ON(host->cmd); + +@@ -719,8 +727,8 @@ void bcm2835_sdhost_send_command(struct + mmc_hostname(host->mmc), + cmd->opcode, cmd->arg, cmd->flags); + +- /* Wait max 10 ms */ +- timeout = 1000; ++ /* Wait max 100 ms */ ++ timeout = 10000; + + while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) { + if (timeout == 0) { +@@ -735,8 +743,9 @@ void bcm2835_sdhost_send_command(struct + udelay(10); + } + +- if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) { +- host->max_delay = (1000-timeout)/100; ++ delay = (10000 - timeout)/100; ++ if (delay > host->max_delay) { ++ host->max_delay = delay; + pr_warning("%s: controller hung for %d ms\n", + mmc_hostname(host->mmc), + host->max_delay); +@@ -751,6 +760,11 @@ void bcm2835_sdhost_send_command(struct + + host->cmd = cmd; + ++ /* Clear any error flags */ ++ sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ if (sdhsts & SDHSTS_ERROR_MASK) ++ bcm2835_sdhost_write(host, sdhsts, SDHSTS); ++ + bcm2835_sdhost_prepare_data(host, cmd); + + bcm2835_sdhost_write(host, cmd->arg, SDARG); +@@ -876,7 +890,7 @@ static void bcm2835_sdhost_transfer_comp + static void bcm2835_sdhost_finish_command(struct bcm2835_host *host) + { + u32 sdcmd; +- int timeout = 1000; ++ unsigned long timeout; + #ifdef DEBUG + struct timeval before, after; + int timediff = 0; +@@ -889,6 +903,8 @@ static void bcm2835_sdhost_finish_comman + #ifdef DEBUG + do_gettimeofday(&before); + #endif ++ /* Wait max 100 ms */ ++ timeout = 10000; + for (sdcmd = bcm2835_sdhost_read(host, SDCMD); + (sdcmd & SDCMD_NEW_FLAG) && timeout; + timeout--) { +@@ -1049,9 +1065,9 @@ static void bcm2835_sdhost_pio_timeout(u + spin_lock_irqsave(&host->lock, flags); + + if (host->data) { +- u32 hsts = bcm2835_sdhost_read(host, SDHSTS); ++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); + +- if (hsts & SDHSTS_REW_TIME_OUT) { ++ if (sdhsts & SDHSTS_REW_TIME_OUT) { + pr_err("%s: transfer timeout\n", + mmc_hostname(host->mmc)); + if (host->debug) +@@ -1380,19 +1396,10 @@ void bcm2835_sdhost_set_clock(struct bcm + if (host->debug) + pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock); + +- if ((clock == 0) && host->reduce_overclock) { +- /* This is a reset following data corruption - reduce any +- overclock */ +- host->reduce_overclock = 0; +- if (host->overclock_50 > 50) { +- pr_warn("%s: reducing overclock due to errors\n", +- mmc_hostname(host->mmc)); +- host->overclock_50--; +- } +- } +- +- if (host->overclock_50 && (clock == 50*MHZ)) ++ if ((host->overclock_50 > 50) && ++ (clock == 50*MHZ)) { + clock = host->overclock_50 * MHZ + (MHZ - 1); ++ } + + /* The SDCDIV register has 11 bits, and holds (div - 2). + But in data mode the max is 50MHz wihout a minimum, and only the +@@ -1450,11 +1457,12 @@ void bcm2835_sdhost_set_clock(struct bcm + host->overclock = clock; + } + } +- else if ((clock == 50 * MHZ) && host->overclock) ++ else if (host->overclock) + { +- pr_warn("%s: cancelling overclock\n", +- mmc_hostname(host->mmc)); + host->overclock = 0; ++ if (clock == 50 * MHZ) ++ pr_warn("%s: cancelling overclock\n", ++ mmc_hostname(host->mmc)); + } + + host->cdiv = div; +@@ -1492,6 +1500,14 @@ static void bcm2835_sdhost_request(struc + cmd->opcode, cmd->arg, cmd->flags); + } + ++ /* Reset the error statuses in case this is a retry */ ++ if (mrq->cmd) ++ mrq->cmd->error = 0; ++ if (mrq->data) ++ mrq->data->error = 0; ++ if (mrq->stop) ++ mrq->stop->error = 0; ++ + if (mrq->data && !is_power_of_2(mrq->data->blksz)) { + pr_err("%s: unsupported block size (%d bytes)\n", + mmc_hostname(mmc), mrq->data->blksz); +@@ -1613,21 +1629,16 @@ static void bcm2835_sdhost_tasklet_finis + + /* Drop the overclock after any data corruption, or after any + error overclocked */ +- if (mrq->data && (mrq->data->error == -EILSEQ)) +- host->reduce_overclock = 1; +- else if (host->overclock) { +- /* Convert timeout errors while overclocked to data errors, +- because the system recovers better. */ +- if (mrq->cmd && mrq->cmd->error) { +- host->reduce_overclock = 1; +- if (mrq->cmd->error == -ETIMEDOUT) +- mrq->cmd->error = -EILSEQ; +- } +- +- if (mrq->data && mrq->data->error) { +- host->reduce_overclock = 1; +- if (mrq->data->error == -ETIMEDOUT) +- mrq->data->error = -EILSEQ; ++ if (host->overclock) { ++ if ((mrq->cmd && mrq->cmd->error) || ++ (mrq->data && mrq->data->error) || ++ (mrq->stop && mrq->stop->error)) { ++ host->overclock_50--; ++ pr_warn("%s: reducing overclock due to errors\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_set_clock(host,50*MHZ); ++ mrq->cmd->error = -EILSEQ; ++ mrq->cmd->retries = 1; + } + } + +@@ -1769,6 +1780,7 @@ static int bcm2835_sdhost_probe(struct p + host = mmc_priv(mmc); + host->mmc = mmc; + host->pio_timeout = msecs_to_jiffies(500); ++ host->max_delay = 1; /* Warn if over 1ms */ + spin_lock_init(&host->lock); + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/brcm2708/patches-4.1/0093-i2c-bcm2708-Increase-timeouts-to-allow-larger-transf.patch b/target/linux/brcm2708/patches-4.1/0093-i2c-bcm2708-Increase-timeouts-to-allow-larger-transf.patch new file mode 100644 index 0000000..0be04df --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0093-i2c-bcm2708-Increase-timeouts-to-allow-larger-transf.patch @@ -0,0 +1,38 @@ +From 40a4a1cc61a3e3e7baa9d623d8f4f68ffa815dd6 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 30 Jun 2015 10:28:59 +0100 +Subject: [PATCH 093/203] i2c-bcm2708: Increase timeouts to allow larger + transfers + +Use the timeout value provided by the I2C_TIMEOUT ioctl when waiting +for completion. The default timeout is 1 second. + +See: https://github.com/raspberrypi/linux/issues/260 +--- + drivers/i2c/busses/i2c-bcm2708.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +--- a/drivers/i2c/busses/i2c-bcm2708.c ++++ b/drivers/i2c/busses/i2c-bcm2708.c +@@ -67,10 +67,9 @@ + #define BSC_S_DONE 0x00000002 + #define BSC_S_TA 0x00000001 + +-#define I2C_TIMEOUT_MS 150 +-#define I2C_WAIT_LOOP_COUNT 40 ++#define I2C_WAIT_LOOP_COUNT 200 + +-#define DRV_NAME "bcm2708_i2c" ++#define DRV_NAME "bcm2708_i2c" + + static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE; + module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); +@@ -305,7 +304,7 @@ static int bcm2708_i2c_master_xfer(struc + goto error_timeout; + } + +- ret = wait_for_completion_timeout(&bi->done, msecs_to_jiffies(I2C_TIMEOUT_MS)); ++ ret = wait_for_completion_timeout(&bi->done, adap->timeout); + if (ret == 0) { + dev_err(&adap->dev, "transfer timed out\n"); + goto error_timeout; diff --git a/target/linux/brcm2708/patches-4.1/0094-spi-bcm2708-Increase-timeout-from-150ms-to-1s.patch b/target/linux/brcm2708/patches-4.1/0094-spi-bcm2708-Increase-timeout-from-150ms-to-1s.patch new file mode 100644 index 0000000..9707e89 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0094-spi-bcm2708-Increase-timeout-from-150ms-to-1s.patch @@ -0,0 +1,24 @@ +From 5b546cecc9b35f45c752c063d43c24dbfcc7328d Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 30 Jun 2015 10:33:52 +0100 +Subject: [PATCH 094/203] spi-bcm2708: Increase timeout from 150ms to 1s + +See: https://github.com/raspberrypi/linux/issues/260 +--- + drivers/spi/spi-bcm2708.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/spi/spi-bcm2708.c ++++ b/drivers/spi/spi-bcm2708.c +@@ -70,9 +70,9 @@ + #define SPI_CS_CS_10 0x00000002 + #define SPI_CS_CS_01 0x00000001 + +-#define SPI_TIMEOUT_MS 150 ++#define SPI_TIMEOUT_MS 1000 + +-#define DRV_NAME "bcm2708_spi" ++#define DRV_NAME "bcm2708_spi" + + struct bcm2708_spi { + spinlock_t lock; diff --git a/target/linux/brcm2708/patches-4.1/0095-bcm2708-spi-Don-t-use-static-pin-configuration-with-.patch b/target/linux/brcm2708/patches-4.1/0095-bcm2708-spi-Don-t-use-static-pin-configuration-with-.patch new file mode 100644 index 0000000..2d24617 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0095-bcm2708-spi-Don-t-use-static-pin-configuration-with-.patch @@ -0,0 +1,39 @@ +From 37f8282b8ba61d7f79cb5538d6331a04c6bdf883 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 15 Jun 2015 09:59:38 +0100 +Subject: [PATCH 095/203] bcm2708-spi: Don't use static pin configuration with + DT + +Also remove superfluous error checking - the SPI framework ensures the +validity of the chip_select value. +--- + drivers/spi/spi-bcm2708.c | 11 ++--------- + 1 file changed, 2 insertions(+), 9 deletions(-) + +--- a/drivers/spi/spi-bcm2708.c ++++ b/drivers/spi/spi-bcm2708.c +@@ -386,14 +386,6 @@ static int bcm2708_spi_setup(struct spi_ + if (bs->stopping) + return -ESHUTDOWN; + +- if (!(spi->mode & SPI_NO_CS) && +- (spi->chip_select > spi->master->num_chipselect)) { +- dev_dbg(&spi->dev, +- "setup: invalid chipselect %u (%u defined)\n", +- spi->chip_select, spi->master->num_chipselect); +- return -EINVAL; +- } +- + state = spi->controller_state; + if (!state) { + state = kzalloc(sizeof(*state), GFP_KERNEL); +@@ -496,7 +488,8 @@ static int bcm2708_spi_probe(struct plat + return PTR_ERR(clk); + } + +- bcm2708_init_pinmode(); ++ if (!pdev->dev.of_node) ++ bcm2708_init_pinmode(); + + master = spi_alloc_master(&pdev->dev, sizeof(*bs)); + if (!master) { diff --git a/target/linux/brcm2708/patches-4.1/0096-bcm2708-i2s-Don-t-use-static-pin-configuration-with-.patch b/target/linux/brcm2708/patches-4.1/0096-bcm2708-i2s-Don-t-use-static-pin-configuration-with-.patch new file mode 100644 index 0000000..88f6dc9 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0096-bcm2708-i2s-Don-t-use-static-pin-configuration-with-.patch @@ -0,0 +1,23 @@ +From f556b04eb5357a2571077799babd135d65f1d7ee Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 15 Jun 2015 10:10:59 +0100 +Subject: [PATCH 096/203] bcm2708-i2s: Don't use static pin configuration with + DT + +--- + sound/soc/bcm/bcm2708-i2s.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/sound/soc/bcm/bcm2708-i2s.c ++++ b/sound/soc/bcm/bcm2708-i2s.c +@@ -409,8 +409,8 @@ static int bcm2708_i2s_hw_params(struct + if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON)) + return 0; + +- +- bcm2708_i2s_setup_gpio(); ++ if (!dev->dev->of_node) ++ bcm2708_i2s_setup_gpio(); + + /* + * Adjust the data length according to the format. diff --git a/target/linux/brcm2708/patches-4.1/0097-serial-8250-Don-t-crash-when-nr_uarts-is-0.patch b/target/linux/brcm2708/patches-4.1/0097-serial-8250-Don-t-crash-when-nr_uarts-is-0.patch new file mode 100644 index 0000000..3cdffb4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0097-serial-8250-Don-t-crash-when-nr_uarts-is-0.patch @@ -0,0 +1,20 @@ +From 32560a31ee4fc921356d69d8dea4c271781b32df Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 30 Jun 2015 14:12:42 +0100 +Subject: [PATCH 097/203] serial: 8250: Don't crash when nr_uarts is 0 + +--- + drivers/tty/serial/8250/8250_core.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -3270,6 +3270,8 @@ static void __init serial8250_isa_init_p + + if (nr_uarts > UART_NR) + nr_uarts = UART_NR; ++ if (!nr_uarts) ++ return; + + for (i = 0; i < nr_uarts; i++) { + struct uart_8250_port *up = &serial8250_ports[i]; diff --git a/target/linux/brcm2708/patches-4.1/0098-BCM270X_DT-Add-overlay-to-enable-uart1.patch b/target/linux/brcm2708/patches-4.1/0098-BCM270X_DT-Add-overlay-to-enable-uart1.patch new file mode 100644 index 0000000..bb1bc1b --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0098-BCM270X_DT-Add-overlay-to-enable-uart1.patch @@ -0,0 +1,152 @@ +From f0ba1d983da479141dc41829d75d68efa446b426 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 26 Jun 2015 08:50:11 +0100 +Subject: [PATCH 098/203] BCM270X_DT: Add overlay to enable uart1 + +N.B. The UART1 clock is derived from the core clock. The firmware +will update clock-frequency if core_freq is set, but be aware +that unless force_turbo=1 while overclocking then the baud rate +will vary with ARM activity. +--- + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 1 + + arch/arm/boot/dts/bcm2708-rpi-b.dts | 1 + + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 1 + + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 1 + + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 8 ++++++ + arch/arm/boot/dts/overlays/uart1-overlay.dts | 38 ++++++++++++++++++++++++++++ + arch/arm/configs/bcm2709_defconfig | 2 +- + arch/arm/configs/bcmrpi_defconfig | 2 +- + 9 files changed, 53 insertions(+), 2 deletions(-) + create mode 100644 arch/arm/boot/dts/overlays/uart1-overlay.dts + +--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +@@ -103,6 +103,7 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; +--- a/arch/arm/boot/dts/bcm2708-rpi-b.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts +@@ -97,6 +97,7 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +@@ -79,6 +79,7 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; +--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts ++++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +@@ -103,6 +103,7 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -42,6 +42,7 @@ dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += uart1-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += w1-gpio-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += w1-gpio-pullup-overlay.dtb + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -489,6 +489,14 @@ Params: speed Display + dtoverlay=tinylcd35,touch,touchgpio=3 + + ++Name: uart1 ++Info: Enable uart1 in place of uart0 ++Load: dtoverlay=uart1,= ++Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14) ++ ++ rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15) ++ ++ + Name: w1-gpio + Info: Configures the w1-gpio Onewire interface module. + Use this overlay if you *don't* need a GPIO to drive an external pullup. +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/uart1-overlay.dts +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ uart1_pins: uart1_pins { ++ brcm,pins = <14 15>; ++ brcm,function = <2>; /* alt5 */ ++ brcm,pull = <0 2>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target-path = "/chosen"; ++ __overlay__ { ++ bootargs = "8250.nr_uarts=1"; ++ }; ++ }; ++ ++ __overrides__ { ++ txd1_pin = <&uart1_pins>,"brcm,pins:0"; ++ rxd1_pin = <&uart1_pins>,"brcm,pins:4"; ++ }; ++}; +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -562,7 +562,7 @@ CONFIG_SERIAL_8250=y + CONFIG_SERIAL_8250_CONSOLE=y + # CONFIG_SERIAL_8250_DMA is not set + CONFIG_SERIAL_8250_NR_UARTS=1 +-CONFIG_SERIAL_8250_RUNTIME_UARTS=1 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=0 + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y + CONFIG_SERIAL_OF_PLATFORM=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -555,7 +555,7 @@ CONFIG_SERIAL_8250=y + CONFIG_SERIAL_8250_CONSOLE=y + # CONFIG_SERIAL_8250_DMA is not set + CONFIG_SERIAL_8250_NR_UARTS=1 +-CONFIG_SERIAL_8250_RUNTIME_UARTS=1 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=0 + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y + CONFIG_SERIAL_OF_PLATFORM=y diff --git a/target/linux/brcm2708/patches-4.1/0099-spi-bcm2835-Support-pin-groups-other-than-7-11.patch b/target/linux/brcm2708/patches-4.1/0099-spi-bcm2835-Support-pin-groups-other-than-7-11.patch new file mode 100644 index 0000000..4835bce --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0099-spi-bcm2835-Support-pin-groups-other-than-7-11.patch @@ -0,0 +1,80 @@ +From e3e8ae5998017712471c53db877bd01dd297ad01 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 24 Jun 2015 14:10:44 +0100 +Subject: [PATCH 099/203] spi-bcm2835: Support pin groups other than 7-11 + +The spi-bcm2835 driver automatically uses GPIO chip-selects due to +some unreliability of the native ones. In doing so it chooses the +same pins as the native chip-selects would use, but the existing +code always uses pins 7 and 8, wherever the SPI function is mapped. + +Search the pinctrl group assigned to the driver for pins that +correspond to native chip-selects, and use those for GPIO chip- +selects. + +Signed-off-by: Phil Elwell +--- + drivers/spi/spi-bcm2835.c | 45 +++++++++++++++++++++++++++++++++++++-------- + 1 file changed, 37 insertions(+), 8 deletions(-) + +--- a/drivers/spi/spi-bcm2835.c ++++ b/drivers/spi/spi-bcm2835.c +@@ -376,6 +376,8 @@ static int bcm2835_spi_setup(struct spi_ + { + int err; + struct gpio_chip *chip; ++ struct device_node *pins; ++ u32 pingroup_index; + /* + * sanity checking the native-chipselects + */ +@@ -392,15 +394,42 @@ static int bcm2835_spi_setup(struct spi_ + "setup: only two native chip-selects are supported\n"); + return -EINVAL; + } +- /* now translate native cs to GPIO */ + +- /* get the gpio chip for the base */ +- chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); +- if (!chip) +- return 0; ++ /* now translate native cs to GPIO */ ++ /* first look for chip select pins in the devices pin groups */ ++ for (pingroup_index = 0; ++ (pins = of_parse_phandle(spi->master->dev.of_node, ++ "pinctrl-0", ++ pingroup_index)) != 0; ++ pingroup_index++) { ++ u32 pin; ++ u32 pin_index; ++ for (pin_index = 0; ++ of_property_read_u32_index(pins, ++ "brcm,pins", ++ pin_index, ++ &pin) == 0; ++ pin_index++) { ++ if (((spi->chip_select == 0) && ++ ((pin == 8) || (pin == 36) || (pin == 46))) || ++ ((spi->chip_select == 1) && ++ ((pin == 7) || (pin == 35)))) { ++ spi->cs_gpio = pin; ++ break; ++ } ++ } ++ of_node_put(pins); ++ } ++ /* if that fails, assume GPIOs 7-11 are used */ ++ if (!gpio_is_valid(spi->cs_gpio) ) { ++ /* get the gpio chip for the base */ ++ chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); ++ if (!chip) ++ return 0; + +- /* and calculate the real CS */ +- spi->cs_gpio = chip->base + 8 - spi->chip_select; ++ /* and calculate the real CS */ ++ spi->cs_gpio = chip->base + 8 - spi->chip_select; ++ } + + /* and set up the "mode" and level */ + dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", diff --git a/target/linux/brcm2708/patches-4.1/0100-BCM270X_DT-Change-pio_limit-of-sdhost-driver-to-1.patch b/target/linux/brcm2708/patches-4.1/0100-BCM270X_DT-Change-pio_limit-of-sdhost-driver-to-1.patch new file mode 100644 index 0000000..0021dcb --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0100-BCM270X_DT-Change-pio_limit-of-sdhost-driver-to-1.patch @@ -0,0 +1,20 @@ +From 53fadd064d2efab96564df3c50a6f1a9fdf8071a Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 30 Jun 2015 17:37:38 +0100 +Subject: [PATCH 100/203] BCM270X_DT: Change pio_limit of sdhost driver to 1 + +--- + arch/arm/boot/dts/overlays/sdhost-overlay.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/overlays/sdhost-overlay.dts ++++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts +@@ -22,7 +22,7 @@ + dma-names = "tx", "rx"; + brcm,delay-after-stop = <0>; + brcm,overclock-50 = <0>; +- brcm,pio-limit = <2>; ++ brcm,pio-limit = <1>; + status = "okay"; + }; + }; diff --git a/target/linux/brcm2708/patches-4.1/0101-bcm2835-sdhost-Clear-HBLC-for-PIO-mode.patch b/target/linux/brcm2708/patches-4.1/0101-bcm2835-sdhost-Clear-HBLC-for-PIO-mode.patch new file mode 100644 index 0000000..bfc6f5f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0101-bcm2835-sdhost-Clear-HBLC-for-PIO-mode.patch @@ -0,0 +1,34 @@ +From b43892ab64a2acc92d25cfd30f0fecba2c925cd2 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 1 Jul 2015 12:51:52 +0100 +Subject: [PATCH 101/203] bcm2835-sdhost: Clear HBLC for PIO mode + +Also update pio_limit default in overlay README. +--- + arch/arm/boot/dts/overlays/README | 2 +- + drivers/mmc/host/bcm2835-sdhost.c | 3 +-- + 2 files changed, 2 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -441,7 +441,7 @@ Params: overclock_50 Clock ( + force_pio Disable DMA support (default off) + + pio_limit Number of blocks above which to use DMA +- (default 2) ++ (default 1) + + debug Enable debug output (default off) + +--- a/drivers/mmc/host/bcm2835-sdhost.c ++++ b/drivers/mmc/host/bcm2835-sdhost.c +@@ -699,8 +699,7 @@ static void bcm2835_sdhost_prepare_data( + bcm2835_sdhost_set_transfer_irqs(host); + + bcm2835_sdhost_write(host, data->blksz, SDHBCT); +- if (host->use_dma) +- bcm2835_sdhost_write(host, data->blocks, SDHBLC); ++ bcm2835_sdhost_write(host, host->use_dma ? data->blocks : 0, SDHBLC); + + BUG_ON(!host->data); + } diff --git a/target/linux/brcm2708/patches-4.1/0102-BCM270X_DT-I2S-needs-function-Alt2.patch b/target/linux/brcm2708/patches-4.1/0102-BCM270X_DT-I2S-needs-function-Alt2.patch new file mode 100644 index 0000000..d6a05ba --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0102-BCM270X_DT-I2S-needs-function-Alt2.patch @@ -0,0 +1,56 @@ +From d81d0b4029bd1b2fb2d9ac65750c3cfa0f243f0c Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 3 Jul 2015 12:21:01 +0100 +Subject: [PATCH 102/203] BCM270X_DT: I2S needs function Alt2 + +--- + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 2 +- + arch/arm/boot/dts/bcm2708-rpi-b.dts | 2 +- + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 2 +- + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 2 +- + 4 files changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +@@ -25,7 +25,7 @@ + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; +- brcm,function = <4>; /* alt0 */ ++ brcm,function = <6>; /* alt2 */ + }; + }; + +--- a/arch/arm/boot/dts/bcm2708-rpi-b.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts +@@ -25,7 +25,7 @@ + + i2s_pins: i2s { + brcm,pins = <28 29 30 31>; +- brcm,function = <4>; /* alt0 */ ++ brcm,function = <6>; /* alt2 */ + }; + }; + +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +@@ -28,7 +28,7 @@ + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; +- brcm,function = <4>; /* alt0 */ ++ brcm,function = <6>; /* alt2 */ + }; + }; + +--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts ++++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +@@ -25,7 +25,7 @@ + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; +- brcm,function = <4>; /* alt0 */ ++ brcm,function = <6>; /* alt2 */ + }; + }; + diff --git a/target/linux/brcm2708/patches-4.1/0103-configs-Incorporate-v4.1-dependency-changes.patch b/target/linux/brcm2708/patches-4.1/0103-configs-Incorporate-v4.1-dependency-changes.patch new file mode 100644 index 0000000..6dff673 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0103-configs-Incorporate-v4.1-dependency-changes.patch @@ -0,0 +1,159 @@ +From 735143fada086487577915861a15ed4822caa9db Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 26 Jun 2015 14:16:15 +0200 +Subject: [PATCH 103/203] configs: Incorporate v4.1 dependency changes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Commit 78e9b7de78bb53e8bc7f4c4a60ebacb250c0c190 added a +dependency on TI_ST instead of selecting it, disabling: +CONFIG_BT_WILINK=m +CONFIG_RADIO_WL128X=m + +Commit 652ccae5cc4e1305fb0a4619947f9ee89d8c7f5a added a +depency on ARM_CRYPTO, disabling: +CONFIG_CRYPTO_SHA*_ARM*=m +CONFIG_CRYPTO_AES_ARM*=m + +Signed-off-by: Noralf Trønnes +--- + arch/arm/configs/bcm2709_defconfig | 10 ++++++---- + arch/arm/configs/bcm2835_defconfig | 8 +++++--- + arch/arm/configs/bcmrpi_defconfig | 8 +++++--- + 3 files changed, 16 insertions(+), 10 deletions(-) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -401,6 +401,7 @@ CONFIG_BLK_DEV_RAM=y + CONFIG_CDROM_PKTCDVD=m + CONFIG_ATA_OVER_ETH=m + CONFIG_EEPROM_AT24=m ++CONFIG_TI_ST=m + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=y +@@ -1100,6 +1101,7 @@ CONFIG_OCFS2_FS=m + CONFIG_BTRFS_FS=m + CONFIG_BTRFS_FS_POSIX_ACL=y + CONFIG_NILFS2_FS=m ++CONFIG_F2FS_FS=y + CONFIG_FANOTIFY=y + CONFIG_QFMT_V1=m + CONFIG_QFMT_V2=m +@@ -1129,7 +1131,6 @@ CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y + CONFIG_SQUASHFS_XZ=y +-CONFIG_F2FS_FS=y + CONFIG_NFS_FS=y + CONFIG_NFS_V3_ACL=y + CONFIG_NFS_V4=y +@@ -1205,14 +1206,15 @@ CONFIG_CRYPTO_CBC=y + CONFIG_CRYPTO_CTS=m + CONFIG_CRYPTO_XTS=m + CONFIG_CRYPTO_XCBC=m +-CONFIG_CRYPTO_SHA1_ARM_NEON=m +-CONFIG_CRYPTO_SHA512_ARM_NEON=m + CONFIG_CRYPTO_TGR192=m + CONFIG_CRYPTO_WP512=m +-CONFIG_CRYPTO_AES_ARM_BS=m + CONFIG_CRYPTO_CAST5=m + CONFIG_CRYPTO_DES=y + # CONFIG_CRYPTO_ANSI_CPRNG is not set + # CONFIG_CRYPTO_HW is not set ++CONFIG_ARM_CRYPTO=y ++CONFIG_CRYPTO_SHA1_ARM_NEON=m ++CONFIG_CRYPTO_SHA512_ARM_NEON=m ++CONFIG_CRYPTO_AES_ARM_BS=m + CONFIG_CRC_ITU_T=y + CONFIG_LIBCRC32C=y +--- a/arch/arm/configs/bcm2835_defconfig ++++ b/arch/arm/configs/bcm2835_defconfig +@@ -402,6 +402,7 @@ CONFIG_BLK_DEV_RAM=y + CONFIG_CDROM_PKTCDVD=m + CONFIG_ATA_OVER_ETH=m + CONFIG_EEPROM_AT24=m ++CONFIG_TI_ST=m + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=y +@@ -1091,6 +1092,7 @@ CONFIG_OCFS2_FS=m + CONFIG_BTRFS_FS=m + CONFIG_BTRFS_FS_POSIX_ACL=y + CONFIG_NILFS2_FS=m ++CONFIG_F2FS_FS=y + CONFIG_FANOTIFY=y + CONFIG_QFMT_V1=m + CONFIG_QFMT_V2=m +@@ -1120,7 +1122,6 @@ CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y + CONFIG_SQUASHFS_XZ=y +-CONFIG_F2FS_FS=y + CONFIG_NFS_FS=y + CONFIG_NFS_V3_ACL=y + CONFIG_NFS_V4=y +@@ -1208,15 +1209,16 @@ CONFIG_CRYPTO_CBC=y + CONFIG_CRYPTO_CTS=m + CONFIG_CRYPTO_XTS=m + CONFIG_CRYPTO_XCBC=m +-CONFIG_CRYPTO_SHA1_ARM=m + CONFIG_CRYPTO_SHA512=m + CONFIG_CRYPTO_TGR192=m + CONFIG_CRYPTO_WP512=m +-CONFIG_CRYPTO_AES_ARM=m + CONFIG_CRYPTO_CAST5=m + CONFIG_CRYPTO_DES=y + # CONFIG_CRYPTO_ANSI_CPRNG is not set + # CONFIG_CRYPTO_HW is not set ++CONFIG_ARM_CRYPTO=y ++CONFIG_CRYPTO_SHA1_ARM=m ++CONFIG_CRYPTO_AES_ARM=m + CONFIG_CRC_ITU_T=y + CONFIG_LIBCRC32C=y + # CONFIG_XZ_DEC_ARM is not set +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -394,6 +394,7 @@ CONFIG_BLK_DEV_RAM=y + CONFIG_CDROM_PKTCDVD=m + CONFIG_ATA_OVER_ETH=m + CONFIG_EEPROM_AT24=m ++CONFIG_TI_ST=m + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=y +@@ -1093,6 +1094,7 @@ CONFIG_OCFS2_FS=m + CONFIG_BTRFS_FS=m + CONFIG_BTRFS_FS_POSIX_ACL=y + CONFIG_NILFS2_FS=m ++CONFIG_F2FS_FS=y + CONFIG_FANOTIFY=y + CONFIG_QFMT_V1=m + CONFIG_QFMT_V2=m +@@ -1122,7 +1124,6 @@ CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y + CONFIG_SQUASHFS_XZ=y +-CONFIG_F2FS_FS=y + CONFIG_NFS_FS=y + CONFIG_NFS_V3_ACL=y + CONFIG_NFS_V4=y +@@ -1200,14 +1201,15 @@ CONFIG_CRYPTO_CBC=y + CONFIG_CRYPTO_CTS=m + CONFIG_CRYPTO_XTS=m + CONFIG_CRYPTO_XCBC=m +-CONFIG_CRYPTO_SHA1_ARM=m + CONFIG_CRYPTO_SHA512=m + CONFIG_CRYPTO_TGR192=m + CONFIG_CRYPTO_WP512=m +-CONFIG_CRYPTO_AES_ARM=m + CONFIG_CRYPTO_CAST5=m + CONFIG_CRYPTO_DES=y + # CONFIG_CRYPTO_ANSI_CPRNG is not set + # CONFIG_CRYPTO_HW is not set ++CONFIG_ARM_CRYPTO=y ++CONFIG_CRYPTO_SHA1_ARM=m ++CONFIG_CRYPTO_AES_ARM=m + CONFIG_CRC_ITU_T=y + CONFIG_LIBCRC32C=y diff --git a/target/linux/brcm2708/patches-4.1/0104-bcmrpi_defconfigs-Add-SND_SOC_WM8804_I2C-for-HifiBer.patch b/target/linux/brcm2708/patches-4.1/0104-bcmrpi_defconfigs-Add-SND_SOC_WM8804_I2C-for-HifiBer.patch new file mode 100644 index 0000000..56298bb --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0104-bcmrpi_defconfigs-Add-SND_SOC_WM8804_I2C-for-HifiBer.patch @@ -0,0 +1,33 @@ +From 0740517729ffa954f7cde3504c107502a1309e12 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 3 Jul 2015 15:47:33 +0100 +Subject: [PATCH 104/203] bcmrpi_defconfigs: Add SND_SOC_WM8804_I2C (for + HifiBerry Digi) + +4.1 has split out support for the I2C and SPI variants, so it now +necessary to explicitly enable the I2C support. +--- + arch/arm/configs/bcm2709_defconfig | 1 + + arch/arm/configs/bcmrpi_defconfig | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -823,6 +823,7 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m + CONFIG_SND_BCM2708_SOC_RPI_DAC=m + CONFIG_SND_BCM2708_SOC_RPI_PROTO=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_SOC_WM8804_I2C=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m + CONFIG_HIDRAW=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -816,6 +816,7 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m + CONFIG_SND_BCM2708_SOC_RPI_DAC=m + CONFIG_SND_BCM2708_SOC_RPI_PROTO=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_SOC_WM8804_I2C=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m + CONFIG_HIDRAW=y diff --git a/target/linux/brcm2708/patches-4.1/0105-squash-BCM270X_DT-I2S-only-needs-Alt2-on-28-31.patch b/target/linux/brcm2708/patches-4.1/0105-squash-BCM270X_DT-I2S-only-needs-Alt2-on-28-31.patch new file mode 100644 index 0000000..105503f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0105-squash-BCM270X_DT-I2S-only-needs-Alt2-on-28-31.patch @@ -0,0 +1,45 @@ +From ca8981f1b4a0c6855240895cb0dfc9fdf2d4b6ba Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Sat, 4 Jul 2015 19:55:23 +0100 +Subject: [PATCH 105/203] squash: BCM270X_DT: I2S only needs Alt2 on 28-31 + +See: https://github.com/raspberrypi/linux/issues/1046 +--- + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 2 +- + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 2 +- + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +@@ -25,7 +25,7 @@ + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; +- brcm,function = <6>; /* alt2 */ ++ brcm,function = <4>; /* alt0 */ + }; + }; + +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +@@ -28,7 +28,7 @@ + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; +- brcm,function = <6>; /* alt2 */ ++ brcm,function = <4>; /* alt0 */ + }; + }; + +--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts ++++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +@@ -25,7 +25,7 @@ + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; +- brcm,function = <6>; /* alt2 */ ++ brcm,function = <4>; /* alt0 */ + }; + }; + diff --git a/target/linux/brcm2708/patches-4.1/0106-vchiq_arm-Two-cacheing-fixes.patch b/target/linux/brcm2708/patches-4.1/0106-vchiq_arm-Two-cacheing-fixes.patch new file mode 100644 index 0000000..6a69019 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0106-vchiq_arm-Two-cacheing-fixes.patch @@ -0,0 +1,268 @@ +From e657f5479bc871209287e26432f013fc395336ab Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 8 Jul 2015 14:48:57 +0100 +Subject: [PATCH 106/203] vchiq_arm: Two cacheing fixes + +1) Make fragment size vary with cache line size +Without this patch, non-cache-line-aligned transfers may corrupt +(or be corrupted by) adjacent data structures. + +Both ARM and VC need to be updated to enable this feature. This is +ensured by having the loader apply a new DT parameter - +cache-line-size. The existence of this parameter guarantees that the +kernel is capable, and the parameter will only be modified from the +safe default if the loader is capable. + +2) Flush/invalidate vmalloc'd memory, and invalidate after reads +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 5 + + .../interface/vchiq_arm/vchiq_2835_arm.c | 112 +++++++++++++-------- + 2 files changed, 77 insertions(+), 40 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -218,6 +218,7 @@ + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; ++ cache-line-size = <32>; + }; + + thermal: thermal { +@@ -270,4 +271,8 @@ + clock-frequency = <126000000>; + }; + }; ++ ++ __overrides__ { ++ cache_line_size = <&vchiq>, "cache-line-size:0"; ++ }; + }; +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +@@ -42,6 +42,7 @@ + #include + #include + #include ++#include + #include + + #define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32) +@@ -64,8 +65,10 @@ typedef struct vchiq_2835_state_struct { + } VCHIQ_2835_ARM_STATE_T; + + static void __iomem *g_regs; +-static FRAGMENTS_T *g_fragments_base; +-static FRAGMENTS_T *g_free_fragments; ++static unsigned int g_cache_line_size = sizeof(CACHE_LINE_SIZE); ++static unsigned int g_fragments_size; ++static char *g_fragments_base; ++static char *g_free_fragments; + static struct semaphore g_free_fragments_sema; + static unsigned long g_virt_to_bus_offset; + +@@ -95,9 +98,13 @@ int vchiq_platform_init(struct platform_ + + g_virt_to_bus_offset = virt_to_dma(dev, (void *)0); + ++ (void)of_property_read_u32(dev->of_node, "cache-line-size", ++ &g_cache_line_size); ++ g_fragments_size = 2 * g_cache_line_size; ++ + /* Allocate space for the channels in coherent memory */ + slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE); +- frag_mem_size = PAGE_ALIGN(sizeof(FRAGMENTS_T) * MAX_FRAGMENTS); ++ frag_mem_size = PAGE_ALIGN(g_fragments_size * MAX_FRAGMENTS); + + slot_mem = dmam_alloc_coherent(dev, slot_mem_size + frag_mem_size, + &slot_phys, GFP_KERNEL); +@@ -117,15 +124,15 @@ int vchiq_platform_init(struct platform_ + vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = + MAX_FRAGMENTS; + +- g_fragments_base = (FRAGMENTS_T *)(slot_mem + slot_mem_size); ++ g_fragments_base = (char *)slot_mem + slot_mem_size; + slot_mem_size += frag_mem_size; + + g_free_fragments = g_fragments_base; + for (i = 0; i < (MAX_FRAGMENTS - 1); i++) { +- *(FRAGMENTS_T **)&g_fragments_base[i] = +- &g_fragments_base[i + 1]; ++ *(char **)&g_fragments_base[i*g_fragments_size] = ++ &g_fragments_base[(i + 1)*g_fragments_size]; + } +- *(FRAGMENTS_T **)&g_fragments_base[i] = NULL; ++ *(char **)&g_fragments_base[i * g_fragments_size] = NULL; + sema_init(&g_free_fragments_sema, MAX_FRAGMENTS); + + if (vchiq_init_state(state, vchiq_slot_zero, 0) != VCHIQ_SUCCESS) +@@ -344,7 +351,7 @@ vchiq_doorbell_irq(int irq, void *dev_id + ** cached area. + + ** N.B. This implementation plays slightly fast and loose with the Linux +-** driver programming rules, e.g. its use of __virt_to_bus instead of ++** driver programming rules, e.g. its use of dmac_map_area instead of + ** dma_map_single, but it isn't a multi-platform driver and it benefits + ** from increased speed as a result. + */ +@@ -355,7 +362,6 @@ create_pagelist(char __user *buf, size_t + { + PAGELIST_T *pagelist; + struct page **pages; +- struct page *page; + unsigned long *addrs; + unsigned int num_pages, offset, i; + char *addr, *base_addr, *next_addr; +@@ -386,10 +392,25 @@ create_pagelist(char __user *buf, size_t + pages = (struct page **)(addrs + num_pages + 1); + + if (is_vmalloc_addr(buf)) { +- for (actual_pages = 0; actual_pages < num_pages; actual_pages++) { +- pages[actual_pages] = vmalloc_to_page(buf + (actual_pages * PAGE_SIZE)); ++ int dir = (type == PAGELIST_WRITE) ? ++ DMA_TO_DEVICE : DMA_FROM_DEVICE; ++ unsigned long length = pagelist->length; ++ unsigned int offset = pagelist->offset; ++ ++ for (actual_pages = 0; actual_pages < num_pages; ++ actual_pages++) { ++ struct page *pg = vmalloc_to_page(buf + (actual_pages * ++ PAGE_SIZE)); ++ size_t bytes = PAGE_SIZE - offset; ++ ++ if (bytes > length) ++ bytes = length; ++ pages[actual_pages] = pg; ++ dmac_map_area(page_address(pg) + offset, bytes, dir); ++ length -= bytes; ++ offset = 0; + } +- *need_release = 0; /* do not try and release vmalloc pages */ ++ *need_release = 0; /* do not try and release vmalloc pages */ + } else { + down_read(&task->mm->mmap_sem); + actual_pages = get_user_pages(task, task->mm, +@@ -418,7 +439,7 @@ create_pagelist(char __user *buf, size_t + actual_pages = -ENOMEM; + return actual_pages; + } +- *need_release = 1; /* release user pages */ ++ *need_release = 1; /* release user pages */ + } + + pagelist->length = count; +@@ -451,10 +472,10 @@ create_pagelist(char __user *buf, size_t + + /* Partial cache lines (fragments) require special measures */ + if ((type == PAGELIST_READ) && +- ((pagelist->offset & (CACHE_LINE_SIZE - 1)) || ++ ((pagelist->offset & (g_cache_line_size - 1)) || + ((pagelist->offset + pagelist->length) & +- (CACHE_LINE_SIZE - 1)))) { +- FRAGMENTS_T *fragments; ++ (g_cache_line_size - 1)))) { ++ char *fragments; + + if (down_interruptible(&g_free_fragments_sema) != 0) { + kfree(pagelist); +@@ -464,19 +485,15 @@ create_pagelist(char __user *buf, size_t + WARN_ON(g_free_fragments == NULL); + + down(&g_free_fragments_mutex); +- fragments = (FRAGMENTS_T *) g_free_fragments; ++ fragments = g_free_fragments; + WARN_ON(fragments == NULL); +- g_free_fragments = *(FRAGMENTS_T **) g_free_fragments; ++ g_free_fragments = *(char **) g_free_fragments; + up(&g_free_fragments_mutex); +- pagelist->type = +- PAGELIST_READ_WITH_FRAGMENTS + (fragments - +- g_fragments_base); ++ pagelist->type = PAGELIST_READ_WITH_FRAGMENTS + ++ (fragments - g_fragments_base) / g_fragments_size; + } + +- for (page = virt_to_page(pagelist); +- page <= virt_to_page(addrs + num_pages - 1); page++) { +- flush_dcache_page(page); +- } ++ dmac_flush_range(pagelist, addrs + num_pages); + + *ppagelist = pagelist; + +@@ -502,13 +519,14 @@ free_pagelist(PAGELIST_T *pagelist, int + + /* Deal with any partial cache lines (fragments) */ + if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) { +- FRAGMENTS_T *fragments = g_fragments_base + +- (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS); ++ char *fragments = g_fragments_base + ++ (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS) * ++ g_fragments_size; + int head_bytes, tail_bytes; +- head_bytes = (CACHE_LINE_SIZE - pagelist->offset) & +- (CACHE_LINE_SIZE - 1); ++ head_bytes = (g_cache_line_size - pagelist->offset) & ++ (g_cache_line_size - 1); + tail_bytes = (pagelist->offset + actual) & +- (CACHE_LINE_SIZE - 1); ++ (g_cache_line_size - 1); + + if ((actual >= 0) && (head_bytes != 0)) { + if (head_bytes > actual) +@@ -516,32 +534,46 @@ free_pagelist(PAGELIST_T *pagelist, int + + memcpy((char *)page_address(pages[0]) + + pagelist->offset, +- fragments->headbuf, ++ fragments, + head_bytes); + } + if ((actual >= 0) && (head_bytes < actual) && + (tail_bytes != 0)) { + memcpy((char *)page_address(pages[num_pages - 1]) + + ((pagelist->offset + actual) & +- (PAGE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1)), +- fragments->tailbuf, tail_bytes); ++ (PAGE_SIZE - 1) & ~(g_cache_line_size - 1)), ++ fragments + g_cache_line_size, ++ tail_bytes); + } + + down(&g_free_fragments_mutex); +- *(FRAGMENTS_T **) fragments = g_free_fragments; ++ *(char **)fragments = g_free_fragments; + g_free_fragments = fragments; + up(&g_free_fragments_mutex); + up(&g_free_fragments_sema); + } + +- if (*need_release) { ++ if (*need_release) { ++ unsigned int length = pagelist->length; ++ unsigned int offset = pagelist->offset; ++ + for (i = 0; i < num_pages; i++) { +- if (pagelist->type != PAGELIST_WRITE) +- set_page_dirty(pages[i]); ++ struct page *pg = pages[i]; + +- page_cache_release(pages[i]); ++ if (pagelist->type != PAGELIST_WRITE) { ++ unsigned int bytes = PAGE_SIZE - offset; ++ ++ if (bytes > length) ++ bytes = length; ++ dmac_unmap_area(page_address(pg) + offset, ++ bytes, DMA_FROM_DEVICE); ++ length -= bytes; ++ offset = 0; ++ set_page_dirty(pg); ++ } ++ page_cache_release(pg); + } +- } ++ } + + kfree(pagelist); + } diff --git a/target/linux/brcm2708/patches-4.1/0107-BCM270X_DT-Overlay-for-the-Fen-Logic-VGA666-board.patch b/target/linux/brcm2708/patches-4.1/0107-BCM270X_DT-Overlay-for-the-Fen-Logic-VGA666-board.patch new file mode 100644 index 0000000..7be3abb --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0107-BCM270X_DT-Overlay-for-the-Fen-Logic-VGA666-board.patch @@ -0,0 +1,77 @@ +From bb7843be4cd8584ab8d3cfbd209220ccf2499327 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 30 Jun 2015 09:10:36 +0100 +Subject: [PATCH 107/203] BCM270X_DT: Overlay for the Fen Logic VGA666 board + +The VGA666 board requires GPIOs 2-21 (so no I2C or UART). Using the +overlay (instead of a custom dt-blob.bin) has the advantage that it will +reserve those pins and stop other devices using them (except for GPIO), +but it does delay the point at which the output becomes valid until 2-3 +seconds after the kernel has started. +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 8 +++++++ + arch/arm/boot/dts/overlays/vga666-overlay.dts | 30 +++++++++++++++++++++++++++ + 3 files changed, 39 insertions(+) + create mode 100644 arch/arm/boot/dts/overlays/vga666-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -43,6 +43,7 @@ dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-ov + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += uart1-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += vga666-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += w1-gpio-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += w1-gpio-pullup-overlay.dtb + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -497,6 +497,14 @@ Params: txd1_pin GPIO pi + rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15) + + ++Name: vga666 ++Info: Overlay for the Fen Logic VGA666 board ++ This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds ++ after the kernel has started. ++Load: dtoverlay=vga666 ++Params: ++ ++ + Name: w1-gpio + Info: Configures the w1-gpio Onewire interface module. + Use this overlay if you *don't* need a GPIO to drive an external pullup. +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vga666-overlay.dts +@@ -0,0 +1,30 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ // There is no VGA driver module, but we need a platform device ++ // node (that doesn't already use pinctrl) to hang the pinctrl ++ // reference on - leds will do ++ ++ fragment@0 { ++ target = <&leds>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vga666_pins>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ vga666_pins: vga666_pins { ++ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 ++ 13 14 15 16 17 18 19 20 21>; ++ brcm,function = <6>; /* alt2 */ ++ brcm,pull = <0>; /* no pull */ ++ }; ++ }; ++ }; ++}; diff --git a/target/linux/brcm2708/patches-4.1/0108-Added-support-for-2-mcp2515-CAN-Bus-IC.patch b/target/linux/brcm2708/patches-4.1/0108-Added-support-for-2-mcp2515-CAN-Bus-IC.patch new file mode 100644 index 0000000..9a7d27e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0108-Added-support-for-2-mcp2515-CAN-Bus-IC.patch @@ -0,0 +1,122 @@ +From 585e94da2a9d370fc462c08641dc12adc7d7a641 Mon Sep 17 00:00:00 2001 +From: petit-miner +Date: Fri, 10 Jul 2015 13:59:18 +0200 +Subject: [PATCH 108/203] Added support for 2 mcp2515 CAN Bus IC + +See: https://github.com/raspberrypi/linux/issues/1018 + https://github.com/raspberrypi/linux/pull/1049 + https://github.com/raspberrypi/linux/pull/1052 +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 12 +++- + .../arm/boot/dts/overlays/mcp2515-can1-overlay.dts | 69 ++++++++++++++++++++++ + 3 files changed, 81 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -29,6 +29,7 @@ dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-ov + dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += lirc-rpi-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += mcp2515-can0-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += mcp2515-can1-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += mmc-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += mz61581-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -328,11 +328,21 @@ Params: gpio_out_pin GPIO fo + + + Name: mcp2515-can0 +-Info: Configures the MCP2515 CAN controller ++Info: Configures the MCP2515 CAN controller on spi0.0 + Load: dtoverlay=mcp2515-can0,= + Params: oscillator Clock frequency for the CAN controller (Hz) + + spimaxfrequency Maximum SPI frequence (Hz) ++ ++ interrupt GPIO for interrupt signal ++ ++ ++Name: mcp2515-can1 ++Info: Configures the MCP2515 CAN controller on spi0.1 ++Load: dtoverlay=mcp2515-can1,= ++Params: oscillator Clock frequency for the CAN controller (Hz) ++ ++ spimaxfrequency Maximum SPI frequence (Hz) + + interrupt GPIO for interrupt signal + +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts +@@ -0,0 +1,69 @@ ++/* ++ * Device tree overlay for mcp251x/can1 on spi0.1 edited by petit_miner ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ /* disable spi-dev for spi0.1 */ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ /* the interrupt pin of the can-controller */ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ can1_pins: can1_pins { ++ brcm,pins = <25>; ++ brcm,function = <0>; /* input */ ++ }; ++ }; ++ }; ++ ++ /* the clock/oscillator of the can-controller */ ++ fragment@2 { ++ target-path = "/clocks"; ++ __overlay__ { ++ /* external oscillator of mcp2515 on spi0.1 */ ++ can1_osc: can1_osc { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ }; ++ }; ++ }; ++ ++ /* the spi config of the can-controller itself binding everything together */ ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ can1: mcp2515@1 { ++ reg = <1>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can1_pins>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&gpio>; ++ interrupts = <25 0x2>; ++ clocks = <&can1_osc>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ oscillator = <&can1_osc>,"clock-frequency:0"; ++ spimaxfrequency = <&can1>,"spi-max-frequency:0"; ++ interrupt = <&can1_pins>,"brcm,pins:0",<&can1>,"interrupts:0"; ++ }; ++}; diff --git a/target/linux/brcm2708/patches-4.1/0109-mailbox-Enable-BCM2835-mailbox-support.patch b/target/linux/brcm2708/patches-4.1/0109-mailbox-Enable-BCM2835-mailbox-support.patch new file mode 100644 index 0000000..0fe6249 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0109-mailbox-Enable-BCM2835-mailbox-support.patch @@ -0,0 +1,274 @@ +From 4222b39965e1639c0d7a5b4e8b8c8ee91803f799 Mon Sep 17 00:00:00 2001 +From: Lubomir Rintel +Date: Tue, 5 May 2015 13:27:45 -0700 +Subject: [PATCH 109/203] mailbox: Enable BCM2835 mailbox support + +This mailbox driver provides a single mailbox channel to write 32-bit +values to the VPU and get a 32-bit response. The Raspberry Pi +firmware uses this mailbox channel to implement firmware calls, while +Roku 2 (despite being derived from the same firmware tree) doesn't. + +The driver was originally submitted by Lubomir, based on the +out-of-tree 2708 mailbox driver. Eric Anholt fixed it up for +upstreaming, with the major functional change being that it now has no +notion of multiple channels (since that is a firmware-dependent +concept) and instead the raspberrypi-firmware driver will do that +bit-twiddling in its own messages. +[Jassi: made the 'mbox_chan_ops' struct as const and removed a redundant +variable] + +Signed-off-by: Lubomir Rintel +Signed-off-by: Craig McGeachie +Signed-off-by: Eric Anholt +Acked-by: Stephen Warren +Signed-off-by: Jassi Brar +--- + drivers/mailbox/Kconfig | 9 ++ + drivers/mailbox/Makefile | 2 + + drivers/mailbox/bcm2835-mailbox.c | 216 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 227 insertions(+) + create mode 100644 drivers/mailbox/bcm2835-mailbox.c + +--- a/drivers/mailbox/Kconfig ++++ b/drivers/mailbox/Kconfig +@@ -66,4 +66,13 @@ config ALTERA_MBOX + An implementation of the Altera Mailbox soft core. It is used + to send message between processors. Say Y here if you want to use the + Altera mailbox support. ++ ++config BCM2835_MBOX ++ tristate "BCM2835 Mailbox" ++ depends on ARCH_BCM2835 ++ help ++ An implementation of the BCM2385 Mailbox. It is used to invoke ++ the services of the Videocore. Say Y here if you want to use the ++ BCM2835 Mailbox. ++ + endif +--- a/drivers/mailbox/Makefile ++++ b/drivers/mailbox/Makefile +@@ -13,3 +13,5 @@ obj-$(CONFIG_OMAP2PLUS_MBOX) += omap-mai + obj-$(CONFIG_PCC) += pcc.o + + obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o ++ ++obj-$(CONFIG_BCM2835_MBOX) += bcm2835-mailbox.o +--- /dev/null ++++ b/drivers/mailbox/bcm2835-mailbox.c +@@ -0,0 +1,216 @@ ++/* ++ * Copyright (C) 2010,2015 Broadcom ++ * Copyright (C) 2013-2014 Lubomir Rintel ++ * Copyright (C) 2013 Craig McGeachie ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This device provides a mechanism for writing to the mailboxes, ++ * that are shared between the ARM and the VideoCore processor ++ * ++ * Parts of the driver are based on: ++ * - arch/arm/mach-bcm2708/vcio.c file written by Gray Girling that was ++ * obtained from branch "rpi-3.6.y" of git://github.com/raspberrypi/ ++ * linux.git ++ * - drivers/mailbox/bcm2835-ipc.c by Lubomir Rintel at ++ * https://github.com/hackerspace/rpi-linux/blob/lr-raspberry-pi/drivers/ ++ * mailbox/bcm2835-ipc.c ++ * - documentation available on the following web site: ++ * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Mailboxes */ ++#define ARM_0_MAIL0 0x00 ++#define ARM_0_MAIL1 0x20 ++ ++/* ++ * Mailbox registers. We basically only support mailbox 0 & 1. We ++ * deliver to the VC in mailbox 1, it delivers to us in mailbox 0. See ++ * BCM2835-ARM-Peripherals.pdf section 1.3 for an explanation about ++ * the placement of memory barriers. ++ */ ++#define MAIL0_RD (ARM_0_MAIL0 + 0x00) ++#define MAIL0_POL (ARM_0_MAIL0 + 0x10) ++#define MAIL0_STA (ARM_0_MAIL0 + 0x18) ++#define MAIL0_CNF (ARM_0_MAIL0 + 0x1C) ++#define MAIL1_WRT (ARM_0_MAIL1 + 0x00) ++ ++/* Status register: FIFO state. */ ++#define ARM_MS_FULL BIT(31) ++#define ARM_MS_EMPTY BIT(30) ++ ++/* Configuration register: Enable interrupts. */ ++#define ARM_MC_IHAVEDATAIRQEN BIT(0) ++ ++struct bcm2835_mbox { ++ void __iomem *regs; ++ spinlock_t lock; ++ struct mbox_controller controller; ++}; ++ ++static struct bcm2835_mbox *bcm2835_link_mbox(struct mbox_chan *link) ++{ ++ return container_of(link->mbox, struct bcm2835_mbox, controller); ++} ++ ++static irqreturn_t bcm2835_mbox_irq(int irq, void *dev_id) ++{ ++ struct bcm2835_mbox *mbox = dev_id; ++ struct device *dev = mbox->controller.dev; ++ struct mbox_chan *link = &mbox->controller.chans[0]; ++ ++ while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) { ++ u32 msg = readl(mbox->regs + MAIL0_RD); ++ dev_dbg(dev, "Reply 0x%08X\n", msg); ++ mbox_chan_received_data(link, &msg); ++ } ++ return IRQ_HANDLED; ++} ++ ++static int bcm2835_send_data(struct mbox_chan *link, void *data) ++{ ++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); ++ u32 msg = *(u32 *)data; ++ ++ spin_lock(&mbox->lock); ++ writel(msg, mbox->regs + MAIL1_WRT); ++ dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); ++ spin_unlock(&mbox->lock); ++ return 0; ++} ++ ++static int bcm2835_startup(struct mbox_chan *link) ++{ ++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); ++ ++ /* Enable the interrupt on data reception */ ++ writel(ARM_MC_IHAVEDATAIRQEN, mbox->regs + MAIL0_CNF); ++ ++ return 0; ++} ++ ++static void bcm2835_shutdown(struct mbox_chan *link) ++{ ++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); ++ ++ writel(0, mbox->regs + MAIL0_CNF); ++} ++ ++static bool bcm2835_last_tx_done(struct mbox_chan *link) ++{ ++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); ++ bool ret; ++ ++ spin_lock(&mbox->lock); ++ ret = !(readl(mbox->regs + MAIL0_STA) & ARM_MS_FULL); ++ spin_unlock(&mbox->lock); ++ return ret; ++} ++ ++static const struct mbox_chan_ops bcm2835_mbox_chan_ops = { ++ .send_data = bcm2835_send_data, ++ .startup = bcm2835_startup, ++ .shutdown = bcm2835_shutdown, ++ .last_tx_done = bcm2835_last_tx_done ++}; ++ ++static struct mbox_chan *bcm2835_mbox_index_xlate(struct mbox_controller *mbox, ++ const struct of_phandle_args *sp) ++{ ++ if (sp->args_count != 0) ++ return NULL; ++ ++ return &mbox->chans[0]; ++} ++ ++static int bcm2835_mbox_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ int ret = 0; ++ struct resource *iomem; ++ struct bcm2835_mbox *mbox; ++ ++ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); ++ if (mbox == NULL) ++ return -ENOMEM; ++ spin_lock_init(&mbox->lock); ++ ++ ret = devm_request_irq(dev, irq_of_parse_and_map(dev->of_node, 0), ++ bcm2835_mbox_irq, 0, dev_name(dev), mbox); ++ if (ret) { ++ dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n", ++ ret); ++ return -ENODEV; ++ } ++ ++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mbox->regs = devm_ioremap_resource(&pdev->dev, iomem); ++ if (IS_ERR(mbox->regs)) { ++ ret = PTR_ERR(mbox->regs); ++ dev_err(&pdev->dev, "Failed to remap mailbox regs: %d\n", ret); ++ return ret; ++ } ++ ++ mbox->controller.txdone_poll = true; ++ mbox->controller.txpoll_period = 5; ++ mbox->controller.ops = &bcm2835_mbox_chan_ops; ++ mbox->controller.of_xlate = &bcm2835_mbox_index_xlate; ++ mbox->controller.dev = dev; ++ mbox->controller.num_chans = 1; ++ mbox->controller.chans = devm_kzalloc(dev, ++ sizeof(*mbox->controller.chans), GFP_KERNEL); ++ if (!mbox->controller.chans) ++ return -ENOMEM; ++ ++ ret = mbox_controller_register(&mbox->controller); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, mbox); ++ dev_info(dev, "mailbox enabled\n"); ++ ++ return ret; ++} ++ ++static int bcm2835_mbox_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_mbox *mbox = platform_get_drvdata(pdev); ++ mbox_controller_unregister(&mbox->controller); ++ return 0; ++} ++ ++static const struct of_device_id bcm2835_mbox_of_match[] = { ++ { .compatible = "brcm,bcm2835-mbox", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_mbox_of_match); ++ ++static struct platform_driver bcm2835_mbox_driver = { ++ .driver = { ++ .name = "bcm2835-mbox", ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_mbox_of_match, ++ }, ++ .probe = bcm2835_mbox_probe, ++ .remove = bcm2835_mbox_remove, ++}; ++module_platform_driver(bcm2835_mbox_driver); ++ ++MODULE_AUTHOR("Lubomir Rintel "); ++MODULE_DESCRIPTION("BCM2835 mailbox IPC driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0110-mailbox-bcm2835-Fix-mailbox-full-detection.patch b/target/linux/brcm2708/patches-4.1/0110-mailbox-bcm2835-Fix-mailbox-full-detection.patch new file mode 100644 index 0000000..43c2560 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0110-mailbox-bcm2835-Fix-mailbox-full-detection.patch @@ -0,0 +1,39 @@ +From dbacf38b4227ffcd9a7eafdb49d395208229286c Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Wed, 13 May 2015 13:10:32 -0700 +Subject: [PATCH 110/203] mailbox/bcm2835: Fix mailbox full detection. + +With the VC reader blocked and the ARM writing, MAIL0_STA reads empty +permanently while MAIL1_STA goes from empty (0x40000000) to non-empty +(0x00000001-0x00000007) to full (0x80000008). + +This bug ended up having no effect on us, because all of our +transactions in the client driver were synchronous and under a mutex. + +Suggested-by: Phil Elwell +Signed-off-by: Eric Anholt +Acked-by: Stephen Warren +Signed-off-by: Jassi Brar +--- + drivers/mailbox/bcm2835-mailbox.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/mailbox/bcm2835-mailbox.c ++++ b/drivers/mailbox/bcm2835-mailbox.c +@@ -49,6 +49,7 @@ + #define MAIL0_STA (ARM_0_MAIL0 + 0x18) + #define MAIL0_CNF (ARM_0_MAIL0 + 0x1C) + #define MAIL1_WRT (ARM_0_MAIL1 + 0x00) ++#define MAIL1_STA (ARM_0_MAIL1 + 0x18) + + /* Status register: FIFO state. */ + #define ARM_MS_FULL BIT(31) +@@ -117,7 +118,7 @@ static bool bcm2835_last_tx_done(struct + bool ret; + + spin_lock(&mbox->lock); +- ret = !(readl(mbox->regs + MAIL0_STA) & ARM_MS_FULL); ++ ret = !(readl(mbox->regs + MAIL1_STA) & ARM_MS_FULL); + spin_unlock(&mbox->lock); + return ret; + } diff --git a/target/linux/brcm2708/patches-4.1/0111-mailbox-bcm2835-Support-ARCH_BCM270x.patch b/target/linux/brcm2708/patches-4.1/0111-mailbox-bcm2835-Support-ARCH_BCM270x.patch new file mode 100644 index 0000000..d117f6a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0111-mailbox-bcm2835-Support-ARCH_BCM270x.patch @@ -0,0 +1,112 @@ +From 2d03b90e245bb0c556b1e67b2572cb51c114bf5a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 26 Jun 2015 14:19:30 +0200 +Subject: [PATCH 111/203] mailbox: bcm2835: Support ARCH_BCM270x +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Make it possible to use bcm2835-mailbox without Device Tree. +Load driver early because of lacking support for deferred probing +in many drivers. + +Signed-off-by: Noralf Trønnes +--- + drivers/mailbox/Kconfig | 2 +- + drivers/mailbox/bcm2835-mailbox.c | 18 ++++++++++++++++-- + drivers/mailbox/mailbox.c | 13 ++++++++++++- + 3 files changed, 29 insertions(+), 4 deletions(-) + +--- a/drivers/mailbox/Kconfig ++++ b/drivers/mailbox/Kconfig +@@ -69,7 +69,7 @@ config ALTERA_MBOX + + config BCM2835_MBOX + tristate "BCM2835 Mailbox" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + help + An implementation of the BCM2385 Mailbox. It is used to invoke + the services of the Videocore. Say Y here if you want to use the +--- a/drivers/mailbox/bcm2835-mailbox.c ++++ b/drivers/mailbox/bcm2835-mailbox.c +@@ -51,12 +51,15 @@ + #define MAIL1_WRT (ARM_0_MAIL1 + 0x00) + #define MAIL1_STA (ARM_0_MAIL1 + 0x18) + ++/* On ARCH_BCM270x these come through (arm_control.h ) */ ++#ifndef ARM_MS_FULL + /* Status register: FIFO state. */ + #define ARM_MS_FULL BIT(31) + #define ARM_MS_EMPTY BIT(30) + + /* Configuration register: Enable interrupts. */ + #define ARM_MC_IHAVEDATAIRQEN BIT(0) ++#endif + + struct bcm2835_mbox { + void __iomem *regs; +@@ -151,7 +154,7 @@ static int bcm2835_mbox_probe(struct pla + return -ENOMEM; + spin_lock_init(&mbox->lock); + +- ret = devm_request_irq(dev, irq_of_parse_and_map(dev->of_node, 0), ++ ret = devm_request_irq(dev, platform_get_irq(pdev, 0), + bcm2835_mbox_irq, 0, dev_name(dev), mbox); + if (ret) { + dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n", +@@ -210,7 +213,18 @@ static struct platform_driver bcm2835_mb + .probe = bcm2835_mbox_probe, + .remove = bcm2835_mbox_remove, + }; +-module_platform_driver(bcm2835_mbox_driver); ++ ++static int __init bcm2835_mbox_init(void) ++{ ++ return platform_driver_register(&bcm2835_mbox_driver); ++} ++arch_initcall(bcm2835_mbox_init); ++ ++static void __init bcm2835_mbox_exit(void) ++{ ++ platform_driver_unregister(&bcm2835_mbox_driver); ++} ++module_exit(bcm2835_mbox_exit); + + MODULE_AUTHOR("Lubomir Rintel "); + MODULE_DESCRIPTION("BCM2835 mailbox IPC driver"); +--- a/drivers/mailbox/mailbox.c ++++ b/drivers/mailbox/mailbox.c +@@ -304,13 +304,23 @@ struct mbox_chan *mbox_request_channel(s + unsigned long flags; + int ret; + +- if (!dev || !dev->of_node) { ++ if (!dev) { + pr_debug("%s: No owner device node\n", __func__); + return ERR_PTR(-ENODEV); + } + + mutex_lock(&con_mutex); + ++ if (!dev->of_node) { ++ chan = NULL; ++ /* pick the first controller in the list */ ++ list_for_each_entry(mbox, &mbox_cons, node) { ++ chan = &mbox->chans[0]; ++ break; ++ } ++ goto skip_dt; ++ } ++ + if (of_parse_phandle_with_args(dev->of_node, "mboxes", + "#mbox-cells", index, &spec)) { + dev_dbg(dev, "%s: can't parse \"mboxes\" property\n", __func__); +@@ -327,6 +337,7 @@ struct mbox_chan *mbox_request_channel(s + + of_node_put(spec.np); + ++skip_dt: + if (!chan || chan->cl || !try_module_get(mbox->dev->driver->owner)) { + dev_dbg(dev, "%s: mailbox not free\n", __func__); + mutex_unlock(&con_mutex); diff --git a/target/linux/brcm2708/patches-4.1/0112-ARM-bcm2835-Add-the-firmware-driver-information-to-t.patch b/target/linux/brcm2708/patches-4.1/0112-ARM-bcm2835-Add-the-firmware-driver-information-to-t.patch new file mode 100644 index 0000000..66e61b6 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0112-ARM-bcm2835-Add-the-firmware-driver-information-to-t.patch @@ -0,0 +1,34 @@ +From 39394c602fcefa762aa9cd527d0f4afe26245c18 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Thu, 4 Jun 2015 13:11:47 -0700 +Subject: [PATCH 112/203] ARM: bcm2835: Add the firmware driver information to + the RPi DT +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Eric Anholt +Acked-by: Lee Jones (previous version with pm-domains) +Acked-by: Stephen Warren +[Rebased on rpi-4.1.y] +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/bcm2835-rpi.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi ++++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi +@@ -27,6 +27,13 @@ + }; + }; + ++ soc { ++ firmware: firmware { ++ compatible = "raspberrypi,bcm2835-firmware"; ++ mboxes = <&mailbox>; ++ }; ++ }; ++ + /* Onboard audio */ + audio: audio { + compatible = "brcm,bcm2835-audio"; diff --git a/target/linux/brcm2708/patches-4.1/0113-firmware-bcm2835-Add-missing-property-tags.patch b/target/linux/brcm2708/patches-4.1/0113-firmware-bcm2835-Add-missing-property-tags.patch new file mode 100644 index 0000000..5facbed --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0113-firmware-bcm2835-Add-missing-property-tags.patch @@ -0,0 +1,62 @@ +From 4811a6764a8ed78a3917a19bf757659c2ed7e390 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 26 Jun 2015 14:21:20 +0200 +Subject: [PATCH 113/203] firmware: bcm2835: Add missing property tags +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Noralf Trønnes +--- + include/soc/bcm2835/raspberrypi-firmware.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/include/soc/bcm2835/raspberrypi-firmware.h ++++ b/include/soc/bcm2835/raspberrypi-firmware.h +@@ -60,6 +60,7 @@ enum rpi_firmware_property_tag { + RPI_FIRMWARE_GET_MIN_VOLTAGE = 0x00030008, + RPI_FIRMWARE_GET_TURBO = 0x00030009, + RPI_FIRMWARE_GET_MAX_TEMPERATURE = 0x0003000a, ++ RPI_FIRMWARE_GET_STC = 0x0003000b, + RPI_FIRMWARE_ALLOCATE_MEMORY = 0x0003000c, + RPI_FIRMWARE_LOCK_MEMORY = 0x0003000d, + RPI_FIRMWARE_UNLOCK_MEMORY = 0x0003000e, +@@ -69,10 +70,12 @@ enum rpi_firmware_property_tag { + RPI_FIRMWARE_SET_ENABLE_QPU = 0x00030012, + RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014, + RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020, ++ RPI_FIRMWARE_GET_CUSTOMER_OTP = 0x00030021, + RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001, + RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002, + RPI_FIRMWARE_SET_VOLTAGE = 0x00038003, + RPI_FIRMWARE_SET_TURBO = 0x00038009, ++ RPI_FIRMWARE_SET_CUSTOMER_OTP = 0x00038021, + + /* Dispmanx TAGS */ + RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 0x00040001, +@@ -86,6 +89,7 @@ enum rpi_firmware_property_tag { + RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 0x00040009, + RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN = 0x0004000a, + RPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE = 0x0004000b, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF = 0x0004000f, + RPI_FIRMWARE_FRAMEBUFFER_RELEASE = 0x00048001, + RPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003, + RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 0x00044004, +@@ -95,6 +99,7 @@ enum rpi_firmware_property_tag { + RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 0x00044009, + RPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN = 0x0004400a, + RPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE = 0x0004400b, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC = 0x0004400e, + RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003, + RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004, + RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH = 0x00048005, +@@ -103,6 +108,9 @@ enum rpi_firmware_property_tag { + RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 0x00048009, + RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a, + RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 0x0004800b, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC = 0x0004800e, ++ ++ RPI_FIRMWARE_VCHIQ_INIT = 0x00048010, + + RPI_FIRMWARE_GET_COMMAND_LINE = 0x00050001, + RPI_FIRMWARE_GET_DMA_CHANNELS = 0x00060001, diff --git a/target/linux/brcm2708/patches-4.1/0114-firmware-bcm2835-Support-ARCH_BCM270x.patch b/target/linux/brcm2708/patches-4.1/0114-firmware-bcm2835-Support-ARCH_BCM270x.patch new file mode 100644 index 0000000..5d4f3c6 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0114-firmware-bcm2835-Support-ARCH_BCM270x.patch @@ -0,0 +1,106 @@ +From e79b76cd146c42e446b034c7b782569ff2ac9219 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 26 Jun 2015 14:25:01 +0200 +Subject: [PATCH 114/203] firmware: bcm2835: Support ARCH_BCM270x +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Support booting without Device Tree. +Turn on USB power. +Load driver early because of lacking support for deferred probing +in many drivers. + +Signed-off-by: Noralf Trønnes +--- + drivers/firmware/raspberrypi.c | 41 +++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 39 insertions(+), 2 deletions(-) + +--- a/drivers/firmware/raspberrypi.c ++++ b/drivers/firmware/raspberrypi.c +@@ -28,6 +28,8 @@ struct rpi_firmware { + u32 enabled; + }; + ++static struct platform_device *g_pdev; ++ + static DEFINE_MUTEX(transaction_lock); + + static void response_callback(struct mbox_client *cl, void *msg) +@@ -183,6 +185,25 @@ rpi_firmware_print_firmware_revision(str + } + } + ++static int raspberrypi_firmware_set_power(struct rpi_firmware *fw, ++ u32 domain, bool on) ++{ ++ struct { ++ u32 domain; ++ u32 on; ++ } packet; ++ int ret; ++ ++ packet.domain = domain; ++ packet.on = on; ++ ret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POWER_STATE, ++ &packet, sizeof(packet)); ++ if (!ret && packet.on != on) ++ ret = -EINVAL; ++ ++ return ret; ++} ++ + static int rpi_firmware_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; +@@ -207,9 +228,13 @@ static int rpi_firmware_probe(struct pla + init_completion(&fw->c); + + platform_set_drvdata(pdev, fw); ++ g_pdev = pdev; + + rpi_firmware_print_firmware_revision(fw); + ++ if (raspberrypi_firmware_set_power(fw, 3, true)) ++ dev_err(dev, "failed to turn on USB power\n"); ++ + return 0; + } + +@@ -218,6 +243,7 @@ static int rpi_firmware_remove(struct pl + struct rpi_firmware *fw = platform_get_drvdata(pdev); + + mbox_free_channel(fw->chan); ++ g_pdev = NULL; + + return 0; + } +@@ -230,7 +256,7 @@ static int rpi_firmware_remove(struct pl + */ + struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node) + { +- struct platform_device *pdev = of_find_device_by_node(firmware_node); ++ struct platform_device *pdev = g_pdev; + + if (!pdev) + return NULL; +@@ -253,7 +279,18 @@ static struct platform_driver rpi_firmwa + .probe = rpi_firmware_probe, + .remove = rpi_firmware_remove, + }; +-module_platform_driver(rpi_firmware_driver); ++ ++static int __init rpi_firmware_init(void) ++{ ++ return platform_driver_register(&rpi_firmware_driver); ++} ++subsys_initcall(rpi_firmware_init); ++ ++static void __init rpi_firmware_exit(void) ++{ ++ platform_driver_unregister(&rpi_firmware_driver); ++} ++module_exit(rpi_firmware_exit); + + MODULE_AUTHOR("Eric Anholt "); + MODULE_DESCRIPTION("Raspberry Pi firmware driver"); diff --git a/target/linux/brcm2708/patches-4.1/0115-firmware-bcm2835-Support-legacy-mailbox-API.patch b/target/linux/brcm2708/patches-4.1/0115-firmware-bcm2835-Support-legacy-mailbox-API.patch new file mode 100644 index 0000000..e66e979 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0115-firmware-bcm2835-Support-legacy-mailbox-API.patch @@ -0,0 +1,88 @@ +From 24337b253d6911bc1697d107460b4d9837e712f6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 26 Jun 2015 14:26:10 +0200 +Subject: [PATCH 115/203] firmware: bcm2835: Support legacy mailbox API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add support for the bcm_mailbox_*() functions. +This is temporary until all drivers have been converted to the +firmware API (rpi_firmware_property*()). + +Signed-off-by: Noralf Trønnes +--- + drivers/firmware/raspberrypi.c | 15 +++++++++++++-- + include/soc/bcm2835/raspberrypi-firmware.h | 2 ++ + 2 files changed, 15 insertions(+), 2 deletions(-) + +--- a/drivers/firmware/raspberrypi.c ++++ b/drivers/firmware/raspberrypi.c +@@ -19,6 +19,7 @@ + #define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf)) + #define MBOX_CHAN(msg) ((msg) & 0xf) + #define MBOX_DATA28(msg) ((msg) & ~0xf) ++#define MBOX_CHAN_VCHIQ 3 + #define MBOX_CHAN_PROPERTY 8 + + struct rpi_firmware { +@@ -26,6 +27,7 @@ struct rpi_firmware { + struct mbox_chan *chan; /* The property channel. */ + struct completion c; + u32 enabled; ++ u32 received; + }; + + static struct platform_device *g_pdev; +@@ -35,6 +37,7 @@ static DEFINE_MUTEX(transaction_lock); + static void response_callback(struct mbox_client *cl, void *msg) + { + struct rpi_firmware *fw = container_of(cl, struct rpi_firmware, cl); ++ fw->received = *(u32 *)msg; + complete(&fw->c); + } + +@@ -42,7 +45,7 @@ static void response_callback(struct mbo + * Sends a request to the firmware through the BCM2835 mailbox driver, + * and synchronously waits for the reply. + */ +-static int ++int + rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data) + { + u32 message = MBOX_MSG(chan, data); +@@ -54,7 +57,8 @@ rpi_firmware_transaction(struct rpi_firm + reinit_completion(&fw->c); + ret = mbox_send_message(fw->chan, &message); + if (ret >= 0) { +- wait_for_completion(&fw->c); ++ if (chan != MBOX_CHAN_VCHIQ) ++ wait_for_completion(&fw->c); + ret = 0; + } else { + dev_err(fw->cl.dev, "mbox_send_message returned %d\n", ret); +@@ -63,6 +67,13 @@ rpi_firmware_transaction(struct rpi_firm + + return ret; + } ++EXPORT_SYMBOL(rpi_firmware_transaction); ++ ++u32 rpi_firmware_transaction_received(struct rpi_firmware *fw) ++{ ++ return MBOX_DATA28(fw->received); ++} ++EXPORT_SYMBOL(rpi_firmware_transaction_received); + + /** + * rpi_firmware_property_list - Submit firmware property list +--- a/include/soc/bcm2835/raspberrypi-firmware.h ++++ b/include/soc/bcm2835/raspberrypi-firmware.h +@@ -116,6 +116,8 @@ enum rpi_firmware_property_tag { + RPI_FIRMWARE_GET_DMA_CHANNELS = 0x00060001, + }; + ++int rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data); ++u32 rpi_firmware_transaction_received(struct rpi_firmware *fw); + int rpi_firmware_property(struct rpi_firmware *fw, + u32 tag, void *data, size_t len); + int rpi_firmware_property_list(struct rpi_firmware *fw, diff --git a/target/linux/brcm2708/patches-4.1/0116-char-broadcom-Add-vcio-module.patch b/target/linux/brcm2708/patches-4.1/0116-char-broadcom-Add-vcio-module.patch new file mode 100644 index 0000000..0e7ae00 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0116-char-broadcom-Add-vcio-module.patch @@ -0,0 +1,219 @@ +From 7de8f9adc447ba0709ad29ad8af13da0085c8491 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 26 Jun 2015 14:27:06 +0200 +Subject: [PATCH 116/203] char: broadcom: Add vcio module +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add module for accessing the mailbox property channel through +/dev/vcio. Was previously in bcm2708-vcio. + +Signed-off-by: Noralf Trønnes +--- + drivers/char/broadcom/Kconfig | 6 ++ + drivers/char/broadcom/Makefile | 1 + + drivers/char/broadcom/vcio.c | 175 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 182 insertions(+) + create mode 100644 drivers/char/broadcom/vcio.c + +--- a/drivers/char/broadcom/Kconfig ++++ b/drivers/char/broadcom/Kconfig +@@ -22,6 +22,12 @@ config BCM2708_VCMEM + help + Helper for videocore memory access and total size allocation. + ++config BCM_VCIO ++ tristate "Mailbox userspace access" ++ depends on BCM2835_MBOX ++ help ++ Gives access to the mailbox property channel from userspace. ++ + endif + + config BCM_VC_SM +--- a/drivers/char/broadcom/Makefile ++++ b/drivers/char/broadcom/Makefile +@@ -1,3 +1,4 @@ + obj-$(CONFIG_BCM_VC_CMA) += vc_cma/ + obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o ++obj-$(CONFIG_BCM_VCIO) += vcio.o + obj-$(CONFIG_BCM_VC_SM) += vc_sm/ +--- /dev/null ++++ b/drivers/char/broadcom/vcio.c +@@ -0,0 +1,175 @@ ++/* ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2015 Noralf Trønnes ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MBOX_CHAN_PROPERTY 8 ++ ++#define VCIO_IOC_MAGIC 100 ++#define IOCTL_MBOX_PROPERTY _IOWR(VCIO_IOC_MAGIC, 0, char *) ++ ++static struct { ++ dev_t devt; ++ struct cdev cdev; ++ struct class *class; ++ struct rpi_firmware *fw; ++} vcio; ++ ++static int vcio_user_property_list(void *user) ++{ ++ u32 *buf, size; ++ int ret; ++ ++ /* The first 32-bit is the size of the buffer */ ++ if (copy_from_user(&size, user, sizeof(size))) ++ return -EFAULT; ++ ++ buf = kmalloc(size, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ if (copy_from_user(buf, user, size)) { ++ kfree(buf); ++ return -EFAULT; ++ } ++ ++ /* Strip off protocol encapsulation */ ++ ret = rpi_firmware_property_list(vcio.fw, &buf[2], size - 12); ++ if (ret) { ++ kfree(buf); ++ return ret; ++ } ++ ++ buf[1] = RPI_FIRMWARE_STATUS_SUCCESS; ++ if (copy_to_user(user, buf, size)) ++ ret = -EFAULT; ++ ++ kfree(buf); ++ ++ return ret; ++} ++ ++static int vcio_device_open(struct inode *inode, struct file *file) ++{ ++ try_module_get(THIS_MODULE); ++ ++ return 0; ++} ++ ++static int vcio_device_release(struct inode *inode, struct file *file) ++{ ++ module_put(THIS_MODULE); ++ ++ return 0; ++} ++ ++static long vcio_device_ioctl(struct file *file, unsigned int ioctl_num, ++ unsigned long ioctl_param) ++{ ++ switch (ioctl_num) { ++ case IOCTL_MBOX_PROPERTY: ++ return vcio_user_property_list((void *)ioctl_param); ++ default: ++ pr_err("unknown ioctl: %d\n", ioctl_num); ++ return -EINVAL; ++ } ++} ++ ++const struct file_operations vcio_fops = { ++ .unlocked_ioctl = vcio_device_ioctl, ++ .open = vcio_device_open, ++ .release = vcio_device_release, ++}; ++ ++static int __init vcio_init(void) ++{ ++ struct device_node *np; ++ static struct device *dev; ++ int ret; ++ ++ np = of_find_compatible_node(NULL, NULL, ++ "raspberrypi,bcm2835-firmware"); ++/* Uncomment this when we only boot with Device Tree ++ if (!of_device_is_available(np)) ++ return -ENODEV; ++*/ ++ vcio.fw = rpi_firmware_get(np); ++ if (!vcio.fw) ++ return -ENODEV; ++ ++ ret = alloc_chrdev_region(&vcio.devt, 0, 1, "vcio"); ++ if (ret) { ++ pr_err("failed to allocate device number\n"); ++ return ret; ++ } ++ ++ cdev_init(&vcio.cdev, &vcio_fops); ++ vcio.cdev.owner = THIS_MODULE; ++ ret = cdev_add(&vcio.cdev, vcio.devt, 1); ++ if (ret) { ++ pr_err("failed to register device\n"); ++ goto err_unregister_chardev; ++ } ++ ++ /* ++ * Create sysfs entries ++ * 'bcm2708_vcio' is used for backwards compatibility so we don't break ++ * userspace. Raspian has a udev rule that changes the permissions. ++ */ ++ vcio.class = class_create(THIS_MODULE, "bcm2708_vcio"); ++ if (IS_ERR(vcio.class)) { ++ ret = PTR_ERR(vcio.class); ++ pr_err("failed to create class\n"); ++ goto err_cdev_del; ++ } ++ ++ dev = device_create(vcio.class, NULL, vcio.devt, NULL, "vcio"); ++ if (IS_ERR(dev)) { ++ ret = PTR_ERR(dev); ++ pr_err("failed to create device\n"); ++ goto err_class_destroy; ++ } ++ ++ return 0; ++ ++err_class_destroy: ++ class_destroy(vcio.class); ++err_cdev_del: ++ cdev_del(&vcio.cdev); ++err_unregister_chardev: ++ unregister_chrdev_region(vcio.devt, 1); ++ ++ return ret; ++} ++module_init(vcio_init); ++ ++static void __exit vcio_exit(void) ++{ ++ device_destroy(vcio.class, vcio.devt); ++ class_destroy(vcio.class); ++ cdev_del(&vcio.cdev); ++ unregister_chrdev_region(vcio.devt, 1); ++} ++module_exit(vcio_exit); ++ ++MODULE_AUTHOR("Gray Girling"); ++MODULE_AUTHOR("Noralf Trønnes"); ++MODULE_DESCRIPTION("Mailbox userspace access"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm2708/patches-4.1/0117-BCM270x-Switch-to-firmware-driver.patch b/target/linux/brcm2708/patches-4.1/0117-BCM270x-Switch-to-firmware-driver.patch new file mode 100644 index 0000000..5301741 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0117-BCM270x-Switch-to-firmware-driver.patch @@ -0,0 +1,595 @@ +From 9b331e3fe3724b92be61ec369c61c5c0b2cfbdbf Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 26 Jun 2015 14:37:19 +0200 +Subject: [PATCH 117/203] BCM270x: Switch to firmware driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +defconfig: enable BCM2835_MBOX, RASPBERRYPI_FIRMWARE and BCM_VCIO. +Add firmware node and change mailbox node in Device Tree. +Add/update platform file for firmware and mailbox. +Strip bcm2708-vcio of everything except the legacy API and hook it +up with the firmware driver. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 8 +- + arch/arm/configs/bcm2709_defconfig | 3 + + arch/arm/configs/bcmrpi_defconfig | 3 + + arch/arm/mach-bcm2708/bcm2708.c | 13 +- + arch/arm/mach-bcm2709/bcm2709.c | 13 +- + drivers/mailbox/Kconfig | 2 +- + drivers/mailbox/bcm2708-vcio.c | 353 ++-------------------------------- + 7 files changed, 51 insertions(+), 344 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -74,9 +74,10 @@ + }; + + mailbox: mailbox@7e00b800 { +- compatible = "brcm,bcm2708-vcio"; ++ compatible = "brcm,bcm2835-mbox"; + reg = <0x7e00b880 0x40>; + interrupts = <0 1>; ++ #mbox-cells = <0>; + }; + + watchdog: watchdog@7e100000 { +@@ -205,6 +206,11 @@ + <1 9>; + }; + ++ firmware: firmware { ++ compatible = "raspberrypi,bcm2835-firmware"; ++ mboxes = <&mailbox>; ++ }; ++ + leds: leds { + compatible = "gpio-leds"; + }; +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -574,6 +574,7 @@ CONFIG_HW_RANDOM_BCM2708=m + CONFIG_RAW_DRIVER=y + CONFIG_BRCM_CHAR_DRIVERS=y + CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VCIO=y + CONFIG_BCM_VC_SM=y + CONFIG_I2C=y + CONFIG_I2C_CHARDEV=m +@@ -1074,6 +1075,7 @@ CONFIG_FB_FLEX=m + CONFIG_FB_TFT_FBTFT_DEVICE=m + CONFIG_MAILBOX=y + CONFIG_BCM2708_MBOX=y ++CONFIG_BCM2835_MBOX=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXTCON=m + CONFIG_EXTCON_ARIZONA=m +@@ -1082,6 +1084,7 @@ CONFIG_IIO_BUFFER=y + CONFIG_IIO_BUFFER_CB=y + CONFIG_IIO_KFIFO_BUF=m + CONFIG_DHT11=m ++CONFIG_RASPBERRYPI_FIRMWARE=y + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y + CONFIG_EXT4_FS_SECURITY=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -567,6 +567,7 @@ CONFIG_HW_RANDOM_BCM2708=m + CONFIG_RAW_DRIVER=y + CONFIG_BRCM_CHAR_DRIVERS=y + CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VCIO=y + CONFIG_BCM_VC_SM=y + CONFIG_I2C=y + CONFIG_I2C_CHARDEV=m +@@ -1067,6 +1068,7 @@ CONFIG_FB_FLEX=m + CONFIG_FB_TFT_FBTFT_DEVICE=m + CONFIG_MAILBOX=y + CONFIG_BCM2708_MBOX=y ++CONFIG_BCM2835_MBOX=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXTCON=m + CONFIG_EXTCON_ARIZONA=m +@@ -1075,6 +1077,7 @@ CONFIG_IIO_BUFFER=y + CONFIG_IIO_BUFFER_CB=y + CONFIG_IIO_KFIFO_BUF=m + CONFIG_DHT11=m ++CONFIG_RASPBERRYPI_FIRMWARE=y + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y + CONFIG_EXT4_FS_SECURITY=y +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -405,7 +405,7 @@ static struct resource bcm2708_vcio_reso + static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_vcio_device = { +- .name = "bcm2708_vcio", ++ .name = "bcm2835-mbox", + .id = -1, /* only one VideoCore I/O area */ + .resource = bcm2708_vcio_resources, + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), +@@ -415,6 +415,16 @@ static struct platform_device bcm2708_vc + }, + }; + ++static u64 rpifw_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_rpifw_device = { ++ .name = "raspberrypi-firmware", ++ .dev = { ++ .dma_mask = &rpifw_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ + static struct resource bcm2708_vchiq_resources[] = { + { + .start = ARMCTRL_0_BELL_BASE, +@@ -871,6 +881,7 @@ void __init bcm2708_init(void) + + bcm_register_device_dt(&bcm2708_dmaengine_device); + bcm_register_device_dt(&bcm2708_vcio_device); ++ bcm_register_device_dt(&bcm2708_rpifw_device); + bcm_register_device_dt(&bcm2708_vchiq_device); + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); +--- a/arch/arm/mach-bcm2709/bcm2709.c ++++ b/arch/arm/mach-bcm2709/bcm2709.c +@@ -426,7 +426,7 @@ static struct resource bcm2708_vcio_reso + static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_vcio_device = { +- .name = "bcm2708_vcio", ++ .name = "bcm2835-mbox", + .id = -1, /* only one VideoCore I/O area */ + .resource = bcm2708_vcio_resources, + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), +@@ -436,6 +436,16 @@ static struct platform_device bcm2708_vc + }, + }; + ++static u64 rpifw_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_rpifw_device = { ++ .name = "raspberrypi-firmware", ++ .dev = { ++ .dma_mask = &rpifw_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ + static struct resource bcm2708_vchiq_resources[] = { + { + .start = ARMCTRL_0_BELL_BASE, +@@ -892,6 +902,7 @@ void __init bcm2709_init(void) + + bcm_register_device_dt(&bcm2708_dmaengine_device); + bcm_register_device_dt(&bcm2708_vcio_device); ++ bcm_register_device_dt(&bcm2708_rpifw_device); + bcm_register_device_dt(&bcm2708_vchiq_device); + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device_dt(&bcm2708_gpio_device); +--- a/drivers/mailbox/Kconfig ++++ b/drivers/mailbox/Kconfig +@@ -9,7 +9,7 @@ if MAILBOX + + config BCM2708_MBOX + bool "Broadcom BCM2708 Mailbox (vcio)" +- depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ depends on BCM2835_MBOX + help + Broadcom BCM2708 Mailbox (vcio) + +--- a/drivers/mailbox/bcm2708-vcio.c ++++ b/drivers/mailbox/bcm2708-vcio.c +@@ -1,6 +1,4 @@ + /* +- * linux/arch/arm/mach-bcm2708/vcio.c +- * + * Copyright (C) 2010 Broadcom + * + * This program is free software; you can redistribute it and/or modify +@@ -12,195 +10,38 @@ + * VideoCore processor + */ + +-#include + #include +-#include +-#include +-#include + #include +-#include +-#include +-#include ++#include + #include +-#include + #include ++#include + + #define DRIVER_NAME "bcm2708_vcio" +-#define DEVICE_FILE_NAME "vcio" +- +-/* offsets from a mail box base address */ +-#define MAIL0_RD 0x00 /* read - and next 4 words */ +-#define MAIL0_POL 0x10 /* read without popping the fifo */ +-#define MAIL0_SND 0x14 /* sender ID (bottom two bits) */ +-#define MAIL0_STA 0x18 /* status */ +-#define MAIL0_CNF 0x1C /* configuration */ +-#define MAIL1_WRT 0x20 /* write - and next 4 words */ +-#define MAIL1_STA 0x38 /* status */ +- +-/* On MACH_BCM270x these come through (arm_control.h ) */ +-#ifndef ARM_MS_EMPTY +-#define ARM_MS_EMPTY BIT(30) +-#define ARM_MS_FULL BIT(31) +- +-#define ARM_MC_IHAVEDATAIRQEN BIT(0) +-#endif +- +-#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf)) +-#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf)) +-#define MBOX_CHAN(msg) ((msg) & 0xf) +-#define MBOX_DATA28(msg) ((msg) & ~0xf) +-#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4) +- +-#define MBOX_MAGIC 0xd0d0c0de +- +-#define MAJOR_NUM 100 +-#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *) +- +-static struct class *vcio_class; +- +-struct vc_mailbox { +- void __iomem *regs; +- uint32_t msg[MBOX_CHAN_COUNT]; +- struct semaphore sema[MBOX_CHAN_COUNT]; +- uint32_t magic; +-}; +- +-static void mbox_init(struct vc_mailbox *mbox_out) +-{ +- int i; +- +- for (i = 0; i < MBOX_CHAN_COUNT; i++) { +- mbox_out->msg[i] = 0; +- sema_init(&mbox_out->sema[i], 0); +- } +- +- /* Enable the interrupt on data reception */ +- writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->regs + MAIL0_CNF); +- +- mbox_out->magic = MBOX_MAGIC; +-} +- +-static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28) +-{ +- if (mbox->magic != MBOX_MAGIC) +- return -EINVAL; +- +- /* wait for the mailbox FIFO to have some space in it */ +- while (0 != (readl(mbox->regs + MAIL1_STA) & ARM_MS_FULL)) +- cpu_relax(); +- +- writel(MBOX_MSG(chan, data28), mbox->regs + MAIL1_WRT); +- +- return 0; +-} +- +-static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28) +-{ +- if (mbox->magic != MBOX_MAGIC) +- return -EINVAL; +- +- down(&mbox->sema[chan]); +- *data28 = MBOX_DATA28(mbox->msg[chan]); +- mbox->msg[chan] = 0; +- +- return 0; +-} +- +-static irqreturn_t mbox_irq_handler(int irq, void *dev_id) +-{ +- /* wait for the mailbox FIFO to have some data in it */ +- struct vc_mailbox *mbox = (struct vc_mailbox *)dev_id; +- int status = readl(mbox->regs + MAIL0_STA); +- int ret = IRQ_NONE; +- +- while (!(status & ARM_MS_EMPTY)) { +- uint32_t msg = readl(mbox->regs + MAIL0_RD); +- int chan = MBOX_CHAN(msg); +- +- if (chan < MBOX_CHAN_COUNT) { +- if (mbox->msg[chan]) { +- pr_err(DRIVER_NAME +- ": mbox chan %d overflow - drop %08x\n", +- chan, msg); +- } else { +- mbox->msg[chan] = (msg | 0xf); +- up(&mbox->sema[chan]); +- } +- } else { +- pr_err(DRIVER_NAME +- ": invalid channel selector (msg %08x)\n", msg); +- } +- ret = IRQ_HANDLED; +- status = readl(mbox->regs + MAIL0_STA); +- } +- return ret; +-} +- +-/* Mailbox Methods */ +- +-static struct device *mbox_dev; /* we assume there's only one! */ +- +-static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28) +-{ +- struct vc_mailbox *mailbox = dev_get_drvdata(dev); +- int rc; +- +- device_lock(dev); +- rc = mbox_write(mailbox, chan, data28); +- device_unlock(dev); +- +- return rc; +-} +- +-static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28) +-{ +- struct vc_mailbox *mailbox = dev_get_drvdata(dev); +- int rc; +- +- device_lock(dev); +- rc = mbox_read(mailbox, chan, data28); +- device_unlock(dev); +- +- return rc; +-} + + extern int bcm_mailbox_write(unsigned chan, uint32_t data28) + { +- if (!mbox_dev) ++ struct rpi_firmware *fw = rpi_firmware_get(NULL); ++ ++ if (!fw) + return -ENODEV; + +- return dev_mbox_write(mbox_dev, chan, data28); ++ return rpi_firmware_transaction(fw, chan, data28); + } + EXPORT_SYMBOL_GPL(bcm_mailbox_write); + + extern int bcm_mailbox_read(unsigned chan, uint32_t *data28) + { +- if (!mbox_dev) +- return -ENODEV; +- +- return dev_mbox_read(mbox_dev, chan, data28); +-} +-EXPORT_SYMBOL_GPL(bcm_mailbox_read); +- +-static int mbox_copy_from_user(void *dst, const void *src, int size) +-{ +- if ((uint32_t)src < TASK_SIZE) +- return copy_from_user(dst, src, size); +- +- memcpy(dst, src, size); ++ struct rpi_firmware *fw = rpi_firmware_get(NULL); + +- return 0; +-} +- +-static int mbox_copy_to_user(void *dst, const void *src, int size) +-{ +- if ((uint32_t)dst < TASK_SIZE) +- return copy_to_user(dst, src, size); ++ if (!fw) ++ return -ENODEV; + +- memcpy(dst, src, size); ++ *data28 = rpi_firmware_transaction_received(fw); + + return 0; + } ++EXPORT_SYMBOL_GPL(bcm_mailbox_read); + + static DEFINE_MUTEX(mailbox_lock); + extern int bcm_mailbox_property(void *data, int size) +@@ -216,7 +57,7 @@ extern int bcm_mailbox_property(void *da + GFP_KERNEL); + if (mem_kern) { + /* create the message */ +- mbox_copy_from_user(mem_kern, data, size); ++ memcpy(mem_kern, data, size); + + /* send the message */ + wmb(); +@@ -226,7 +67,7 @@ extern int bcm_mailbox_property(void *da + if (s == 0) { + /* copy the response */ + rmb(); +- mbox_copy_to_user(data, mem_kern, size); ++ memcpy(data, mem_kern, size); + } + dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus); + } else { +@@ -240,174 +81,6 @@ extern int bcm_mailbox_property(void *da + } + EXPORT_SYMBOL_GPL(bcm_mailbox_property); + +-/* Platform Device for Mailbox */ +- +-/* This is called whenever a process attempts to open the device file */ +-static int device_open(struct inode *inode, struct file *file) +-{ +- try_module_get(THIS_MODULE); +- +- return 0; +-} +- +-static int device_release(struct inode *inode, struct file *file) +-{ +- module_put(THIS_MODULE); +- +- return 0; +-} +- +-/* +- * This function is called whenever a process tries to do an ioctl on our +- * device file. We get two extra parameters (additional to the inode and file +- * structures, which all device functions get): the number of the ioctl called +- * and the parameter given to the ioctl function. +- * +- * If the ioctl is write or read/write (meaning output is returned to the +- * calling process), the ioctl call returns the output of this function. +- * +- */ +-static long device_ioctl(struct file *file, unsigned int ioctl_num, +- unsigned long ioctl_param) +-{ +- unsigned size; +- +- switch (ioctl_num) { +- case IOCTL_MBOX_PROPERTY: +- /* +- * Receive a pointer to a message (in user space) and set that +- * to be the device's message. Get the parameter given to +- * ioctl by the process. +- */ +- mbox_copy_from_user(&size, (void *)ioctl_param, sizeof(size)); +- return bcm_mailbox_property((void *)ioctl_param, size); +- default: +- pr_err(DRIVER_NAME "unknown ioctl: %d\n", ioctl_num); +- return -EINVAL; +- } +- +- return 0; +-} +- +-/* Module Declarations */ +- +-/* +- * This structure will hold the functions to be called +- * when a process does something to the device we +- * created. Since a pointer to this structure is kept in +- * the devices table, it can't be local to +- * init_module. NULL is for unimplemented functios. +- */ +-const struct file_operations fops = { +- .unlocked_ioctl = device_ioctl, +- .open = device_open, +- .release = device_release, /* a.k.a. close */ +-}; +- +-static int bcm_vcio_probe(struct platform_device *pdev) +-{ +- struct device *dev = &pdev->dev; +- struct device *vdev; +- struct vc_mailbox *mailbox; +- struct resource *res; +- int irq, ret; +- +- mailbox = devm_kzalloc(dev, sizeof(*mailbox), GFP_KERNEL); +- if (!mailbox) +- return -ENOMEM; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- mailbox->regs = devm_ioremap_resource(dev, res); +- if (IS_ERR(mailbox->regs)) +- return PTR_ERR(mailbox->regs); +- +- irq = platform_get_irq(pdev, 0); +- ret = devm_request_irq(dev, irq, mbox_irq_handler, +- IRQF_IRQPOLL, +- dev_name(dev), mailbox); +- if (ret) { +- dev_err(dev, "Interrupt request failed %d\n", ret); +- return ret; +- } +- +- ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops); +- if (ret < 0) { +- pr_err("Character device registration failed %d\n", ret); +- return ret; +- } +- +- vcio_class = class_create(THIS_MODULE, DRIVER_NAME); +- if (IS_ERR(vcio_class)) { +- ret = PTR_ERR(vcio_class); +- pr_err("Class creation failed %d\n", ret); +- goto err_class; +- } +- +- vdev = device_create(vcio_class, NULL, MKDEV(MAJOR_NUM, 0), NULL, +- "vcio"); +- if (IS_ERR(vdev)) { +- ret = PTR_ERR(vdev); +- pr_err("Device creation failed %d\n", ret); +- goto err_dev; +- } +- +- mbox_init(mailbox); +- platform_set_drvdata(pdev, mailbox); +- mbox_dev = dev; +- +- dev_info(dev, "mailbox at %p\n", mailbox->regs); +- +- return 0; +- +-err_dev: +- class_destroy(vcio_class); +-err_class: +- unregister_chrdev(MAJOR_NUM, DEVICE_FILE_NAME); +- +- return ret; +-} +- +-static int bcm_vcio_remove(struct platform_device *pdev) +-{ +- mbox_dev = NULL; +- platform_set_drvdata(pdev, NULL); +- device_destroy(vcio_class, MKDEV(MAJOR_NUM, 0)); +- class_destroy(vcio_class); +- unregister_chrdev(MAJOR_NUM, DEVICE_FILE_NAME); +- +- return 0; +-} +- +-static const struct of_device_id bcm_vcio_of_match_table[] = { +- { .compatible = "brcm,bcm2708-vcio", }, +- {}, +-}; +-MODULE_DEVICE_TABLE(of, bcm_vcio_of_match_table); +- +-static struct platform_driver bcm_mbox_driver = { +- .probe = bcm_vcio_probe, +- .remove = bcm_vcio_remove, +- +- .driver = { +- .name = DRIVER_NAME, +- .owner = THIS_MODULE, +- .of_match_table = bcm_vcio_of_match_table, +- }, +-}; +- +-static int __init bcm_mbox_init(void) +-{ +- return platform_driver_register(&bcm_mbox_driver); +-} +- +-static void __exit bcm_mbox_exit(void) +-{ +- platform_driver_unregister(&bcm_mbox_driver); +-} +- +-arch_initcall(bcm_mbox_init); /* Initialize early */ +-module_exit(bcm_mbox_exit); +- + MODULE_AUTHOR("Gray Girling"); + MODULE_DESCRIPTION("ARM I/O to VideoCore processor"); + MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm2708/patches-4.1/0118-bcm2835-Switch-to-firmware-driver.patch b/target/linux/brcm2708/patches-4.1/0118-bcm2835-Switch-to-firmware-driver.patch new file mode 100644 index 0000000..ad5bed0 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0118-bcm2835-Switch-to-firmware-driver.patch @@ -0,0 +1,54 @@ +From 60ceda26c37c133a537ed1f64ddb7044732884f6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 26 Jun 2015 14:39:21 +0200 +Subject: [PATCH 118/203] bcm2835: Switch to firmware driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +defconfig: enable BCM2835_MBOX, RASPBERRYPI_FIRMWARE and BCM_VCIO. + +Add firmware node and change mailbox node in Device Tree. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/bcm2835.dtsi | 3 ++- + arch/arm/configs/bcm2835_defconfig | 3 +++ + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/bcm2835.dtsi ++++ b/arch/arm/boot/dts/bcm2835.dtsi +@@ -62,9 +62,10 @@ + }; + + mailbox: mailbox@7e00b800 { +- compatible = "brcm,bcm2708-vcio"; ++ compatible = "brcm,bcm2835-mbox"; + reg = <0x7e00b880 0x40>; + interrupts = <0 1>; ++ #mbox-cells = <0>; + }; + + gpio: gpio@7e200000 { +--- a/arch/arm/configs/bcm2835_defconfig ++++ b/arch/arm/configs/bcm2835_defconfig +@@ -568,6 +568,7 @@ CONFIG_HW_RANDOM_BCM2835=m + CONFIG_RAW_DRIVER=y + CONFIG_BRCM_CHAR_DRIVERS=y + CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VCIO=y + CONFIG_BCM_VC_SM=y + CONFIG_I2C=y + CONFIG_I2C_CHARDEV=m +@@ -1064,9 +1065,11 @@ CONFIG_FB_FLEX=m + CONFIG_FB_TFT_FBTFT_DEVICE=m + CONFIG_MAILBOX=y + CONFIG_BCM2708_MBOX=y ++CONFIG_BCM2835_MBOX=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXTCON=m + CONFIG_EXTCON_ARIZONA=m ++CONFIG_RASPBERRYPI_FIRMWARE=y + CONFIG_EXT2_FS=y + CONFIG_EXT2_FS_XATTR=y + CONFIG_EXT2_FS_POSIX_ACL=y diff --git a/target/linux/brcm2708/patches-4.1/0119-Merge-pull-request-1059-from-pelwell-rpi-4.0.y.patch b/target/linux/brcm2708/patches-4.1/0119-Merge-pull-request-1059-from-pelwell-rpi-4.0.y.patch new file mode 100644 index 0000000..5ae3104 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0119-Merge-pull-request-1059-from-pelwell-rpi-4.0.y.patch @@ -0,0 +1,190 @@ +From f58127f1cc42ee92a87fc7a88ea88071f1b48340 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 13 Jul 2015 13:25:31 +0100 +Subject: [PATCH 119/203] Merge pull request #1059 from pelwell/rpi-4.0.y + +w1_therm: Back-port locking improvements from 4.2-rc1 +--- + Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 | 6 ++ + Documentation/w1/slaves/w1_therm | 11 ++- + drivers/w1/slaves/w1_therm.c | 102 +++++++++++++++++++++- + 3 files changed, 117 insertions(+), 2 deletions(-) + create mode 100644 Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 + +--- /dev/null ++++ b/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 +@@ -0,0 +1,6 @@ ++What: /sys/bus/w1/devices/.../w1_seq ++Date: Apr 2015 ++Contact: Matt Campbell ++Description: Support for the DS28EA00 chain sequence function ++ see Documentation/w1/slaves/w1_therm for detailed information ++Users: any user space application which wants to communicate with DS28EA00 +--- a/Documentation/w1/slaves/w1_therm ++++ b/Documentation/w1/slaves/w1_therm +@@ -11,12 +11,14 @@ Author: Evgeniy Polyakov master->bus_mutex); ++ /* Place all devices in CHAIN state */ ++ if (w1_reset_bus(sl->master)) ++ goto error; ++ w1_write_8(sl->master, W1_SKIP_ROM); ++ w1_write_8(sl->master, W1_42_CHAIN); ++ w1_write_8(sl->master, W1_42_CHAIN_ON); ++ w1_write_8(sl->master, W1_42_CHAIN_ON_INV); ++ msleep(sl->master->pullup_duration); ++ ++ /* check for acknowledgment */ ++ ack = w1_read_8(sl->master); ++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) ++ goto error; ++ ++ /* In case the bus fails to send 0xFF, limit*/ ++ for (i = 0; i <= 64; i++) { ++ if (w1_reset_bus(sl->master)) ++ goto error; ++ ++ w1_write_8(sl->master, W1_42_COND_READ); ++ rv = w1_read_block(sl->master, (u8 *)&rn, 8); ++ reg_num = (struct w1_reg_num *) &rn; ++ if (reg_num->family == W1_42_FINISHED_BYTE) ++ break; ++ if (sl->reg_num.id == reg_num->id) ++ seq = i; ++ ++ w1_write_8(sl->master, W1_42_CHAIN); ++ w1_write_8(sl->master, W1_42_CHAIN_DONE); ++ w1_write_8(sl->master, W1_42_CHAIN_DONE_INV); ++ w1_read_block(sl->master, &ack, sizeof(ack)); ++ ++ /* check for acknowledgment */ ++ ack = w1_read_8(sl->master); ++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) ++ goto error; ++ ++ } ++ ++ /* Exit from CHAIN state */ ++ if (w1_reset_bus(sl->master)) ++ goto error; ++ w1_write_8(sl->master, W1_SKIP_ROM); ++ w1_write_8(sl->master, W1_42_CHAIN); ++ w1_write_8(sl->master, W1_42_CHAIN_OFF); ++ w1_write_8(sl->master, W1_42_CHAIN_OFF_INV); ++ ++ /* check for acknowledgment */ ++ ack = w1_read_8(sl->master); ++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) ++ goto error; ++ mutex_unlock(&sl->master->bus_mutex); ++ ++ c -= snprintf(buf + PAGE_SIZE - c, c, "%d\n", seq); ++ return PAGE_SIZE - c; ++error: ++ mutex_unlock(&sl->master->bus_mutex); ++ return -EIO; ++} ++ + static int __init w1_therm_init(void) + { + int err, i; diff --git a/target/linux/brcm2708/patches-4.1/0120-vchiq_arm-Sort-out-the-vmalloc-case.patch b/target/linux/brcm2708/patches-4.1/0120-vchiq_arm-Sort-out-the-vmalloc-case.patch new file mode 100644 index 0000000..9c0c7c1 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0120-vchiq_arm-Sort-out-the-vmalloc-case.patch @@ -0,0 +1,39 @@ +From 2b4d5c82da3850c7bf04c069b8eca966e931512f Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 14 Jul 2015 11:11:51 +0100 +Subject: [PATCH 120/203] vchiq_arm: Sort out the vmalloc case + +See: https://github.com/raspberrypi/linux/issues/1055 +--- + .../misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +@@ -394,21 +394,21 @@ create_pagelist(char __user *buf, size_t + if (is_vmalloc_addr(buf)) { + int dir = (type == PAGELIST_WRITE) ? + DMA_TO_DEVICE : DMA_FROM_DEVICE; +- unsigned long length = pagelist->length; +- unsigned int offset = pagelist->offset; ++ unsigned long length = count; ++ unsigned int off = offset; + + for (actual_pages = 0; actual_pages < num_pages; + actual_pages++) { + struct page *pg = vmalloc_to_page(buf + (actual_pages * + PAGE_SIZE)); +- size_t bytes = PAGE_SIZE - offset; ++ size_t bytes = PAGE_SIZE - off; + + if (bytes > length) + bytes = length; + pages[actual_pages] = pg; +- dmac_map_area(page_address(pg) + offset, bytes, dir); ++ dmac_map_area(page_address(pg) + off, bytes, dir); + length -= bytes; +- offset = 0; ++ off = 0; + } + *need_release = 0; /* do not try and release vmalloc pages */ + } else { diff --git a/target/linux/brcm2708/patches-4.1/0121-spidev-Add-spidev-compatible-string-to-silence-warni.patch b/target/linux/brcm2708/patches-4.1/0121-spidev-Add-spidev-compatible-string-to-silence-warni.patch new file mode 100644 index 0000000..20e3cff --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0121-spidev-Add-spidev-compatible-string-to-silence-warni.patch @@ -0,0 +1,21 @@ +From 6e185e181f581341f34f7d7d288a2c4204202031 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 14 Jul 2015 10:26:09 +0100 +Subject: [PATCH 121/203] spidev: Add "spidev" compatible string to silence + warning + +See: https://github.com/raspberrypi/linux/issues/1054 +--- + drivers/spi/spidev.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/spi/spidev.c ++++ b/drivers/spi/spidev.c +@@ -707,6 +707,7 @@ static struct class *spidev_class; + #ifdef CONFIG_OF + static const struct of_device_id spidev_dt_ids[] = { + { .compatible = "rohm,dh2228fv" }, ++ { .compatible = "spidev" }, + {}, + }; + MODULE_DEVICE_TABLE(of, spidev_dt_ids); diff --git a/target/linux/brcm2708/patches-4.1/0122-Merge-pull-request-1043-from-XECDesign-sense-4.0.patch b/target/linux/brcm2708/patches-4.1/0122-Merge-pull-request-1043-from-XECDesign-sense-4.0.patch new file mode 100644 index 0000000..cc51079 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0122-Merge-pull-request-1043-from-XECDesign-sense-4.0.patch @@ -0,0 +1,894 @@ +From aa6bc84a28af9acd24d457944700b7880c86a343 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 14 Jul 2015 14:32:47 +0100 +Subject: [PATCH 122/203] Merge pull request #1043 from XECDesign/sense-4.0 + +mfd: Add Raspberry Pi Sense HAT core driver +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 6 + + arch/arm/boot/dts/overlays/rpi-sense-overlay.dts | 47 +++++ + arch/arm/configs/bcm2709_defconfig | 2 + + arch/arm/configs/bcmrpi_defconfig | 2 + + drivers/input/joystick/Kconfig | 8 + + drivers/input/joystick/Makefile | 1 + + drivers/input/joystick/rpisense-js.c | 153 +++++++++++++++ + drivers/mfd/Kconfig | 8 + + drivers/mfd/Makefile | 2 + + drivers/mfd/rpisense-core.c | 157 +++++++++++++++ + drivers/video/fbdev/Kconfig | 13 ++ + drivers/video/fbdev/Makefile | 1 + + drivers/video/fbdev/rpisense-fb.c | 235 +++++++++++++++++++++++ + include/linux/mfd/rpisense/core.h | 47 +++++ + include/linux/mfd/rpisense/framebuffer.h | 28 +++ + include/linux/mfd/rpisense/joystick.h | 35 ++++ + 17 files changed, 746 insertions(+) + create mode 100644 arch/arm/boot/dts/overlays/rpi-sense-overlay.dts + create mode 100644 drivers/input/joystick/rpisense-js.c + create mode 100644 drivers/mfd/rpisense-core.c + create mode 100644 drivers/video/fbdev/rpisense-fb.c + create mode 100644 include/linux/mfd/rpisense/core.h + create mode 100644 include/linux/mfd/rpisense/framebuffer.h + create mode 100644 include/linux/mfd/rpisense/joystick.h + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -39,6 +39,7 @@ dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overla + dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-proto-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-sense-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -442,6 +442,12 @@ Load: dtoverlay=rpi-proto + Params: + + ++Name: rpi-sense ++Info: Raspberry Pi Sense HAT ++Load: dtoverlay=rpi-sense ++Params: ++ ++ + Name: sdhost + Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock + Load: dtoverlay=sdhost,= +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts +@@ -0,0 +1,47 @@ ++// rpi-sense HAT ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ rpi-sense@46 { ++ compatible = "rpi,rpi-sense"; ++ reg = <0x46>; ++ keys-int-gpios = <&gpio 23 1>; ++ status = "okay"; ++ }; ++ ++ lsm9ds1-magn@1c { ++ compatible = "st,lsm9ds1-magn"; ++ reg = <0x1c>; ++ status = "okay"; ++ }; ++ ++ lsm9ds1-accel6a { ++ compatible = "st,lsm9ds1-accel"; ++ reg = <0x6a>; ++ status = "okay"; ++ }; ++ ++ lps25h-press@5c { ++ compatible = "st,lps25h-press"; ++ reg = <0x5c>; ++ status = "okay"; ++ }; ++ ++ hts221-humid@5f { ++ compatible = "st,hts221-humid"; ++ reg = <0x5f>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -533,6 +533,7 @@ CONFIG_JOYSTICK_IFORCE=m + CONFIG_JOYSTICK_IFORCE_USB=y + CONFIG_JOYSTICK_XPAD=m + CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_JOYSTICK_RPISENSE=m + CONFIG_INPUT_TOUCHSCREEN=y + CONFIG_TOUCHSCREEN_ADS7846=m + CONFIG_TOUCHSCREEN_EGALAX=m +@@ -789,6 +790,7 @@ CONFIG_VIDEO_MT9V011=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FB_SSD1307=m ++CONFIG_FB_RPISENSE=m + # CONFIG_BACKLIGHT_GENERIC is not set + CONFIG_BACKLIGHT_GPIO=m + CONFIG_FRAMEBUFFER_CONSOLE=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -526,6 +526,7 @@ CONFIG_JOYSTICK_IFORCE=m + CONFIG_JOYSTICK_IFORCE_USB=y + CONFIG_JOYSTICK_XPAD=m + CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_JOYSTICK_RPISENSE=m + CONFIG_INPUT_TOUCHSCREEN=y + CONFIG_TOUCHSCREEN_ADS7846=m + CONFIG_TOUCHSCREEN_EGALAX=m +@@ -782,6 +783,7 @@ CONFIG_VIDEO_MT9V011=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FB_SSD1307=m ++CONFIG_FB_RPISENSE=m + # CONFIG_BACKLIGHT_GENERIC is not set + CONFIG_BACKLIGHT_GPIO=m + CONFIG_FRAMEBUFFER_CONSOLE=y +--- a/drivers/input/joystick/Kconfig ++++ b/drivers/input/joystick/Kconfig +@@ -329,4 +329,12 @@ config JOYSTICK_MAPLE + To compile this as a module choose M here: the module will be called + maplecontrol. + ++config JOYSTICK_RPISENSE ++ tristate "Raspberry Pi Sense HAT joystick" ++ depends on GPIOLIB && INPUT ++ select MFD_RPISENSE_CORE ++ ++ help ++ This is the joystick driver for the Raspberry Pi Sense HAT ++ + endif +--- a/drivers/input/joystick/Makefile ++++ b/drivers/input/joystick/Makefile +@@ -32,4 +32,5 @@ obj-$(CONFIG_JOYSTICK_WARRIOR) += warri + obj-$(CONFIG_JOYSTICK_XPAD) += xpad.o + obj-$(CONFIG_JOYSTICK_ZHENHUA) += zhenhua.o + obj-$(CONFIG_JOYSTICK_WALKERA0701) += walkera0701.o ++obj-$(CONFIG_JOYSTICK_RPISENSE) += rpisense-js.o + +--- /dev/null ++++ b/drivers/input/joystick/rpisense-js.c +@@ -0,0 +1,153 @@ ++/* ++ * Raspberry Pi Sense HAT joystick driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++ ++#include ++#include ++ ++struct rpisense *rpisense; ++unsigned char keymap[5] = {KEY_DOWN, KEY_RIGHT, KEY_UP, KEY_ENTER, KEY_LEFT,}; ++ ++static void keys_work_fn(struct work_struct *work) ++{ ++ int i; ++ static s32 prev_keys; ++ struct rpisense_js *rpisense_js = &rpisense->joystick; ++ s32 keys = rpisense_reg_read(rpisense, RPISENSE_KEYS); ++ s32 changes = keys ^ prev_keys; ++ ++ prev_keys = keys; ++ for (i = 0; i < 5; i++) { ++ if (changes & 1) { ++ input_report_key(rpisense_js->keys_dev, ++ keymap[i], keys & 1); ++ } ++ changes >>= 1; ++ keys >>= 1; ++ } ++ input_sync(rpisense_js->keys_dev); ++} ++ ++static irqreturn_t keys_irq_handler(int irq, void *pdev) ++{ ++ struct rpisense_js *rpisense_js = &rpisense->joystick; ++ ++ schedule_work(&rpisense_js->keys_work_s); ++ return IRQ_HANDLED; ++} ++ ++static int rpisense_js_probe(struct platform_device *pdev) ++{ ++ int ret; ++ int i; ++ struct rpisense_js *rpisense_js; ++ ++ rpisense = rpisense_get_dev(); ++ rpisense_js = &rpisense->joystick; ++ ++ INIT_WORK(&rpisense_js->keys_work_s, keys_work_fn); ++ ++ rpisense_js->keys_dev = input_allocate_device(); ++ if (!rpisense_js->keys_dev) { ++ dev_err(&pdev->dev, "Could not allocate input device.\n"); ++ return -ENOMEM; ++ } ++ ++ rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY); ++ for (i = 0; i < ARRAY_SIZE(keymap); i++) { ++ set_bit(keymap[i], ++ rpisense_js->keys_dev->keybit); ++ } ++ ++ rpisense_js->keys_dev->name = "Raspberry Pi Sense HAT Joystick"; ++ rpisense_js->keys_dev->phys = "rpi-sense-joy/input0"; ++ rpisense_js->keys_dev->id.bustype = BUS_I2C; ++ rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP); ++ rpisense_js->keys_dev->keycode = keymap; ++ rpisense_js->keys_dev->keycodesize = sizeof(unsigned char); ++ rpisense_js->keys_dev->keycodemax = ARRAY_SIZE(keymap); ++ ++ ret = input_register_device(rpisense_js->keys_dev); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not register input device.\n"); ++ goto err_keys_alloc; ++ } ++ ++ ret = gpiod_direction_input(rpisense_js->keys_desc); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not set keys-int direction.\n"); ++ goto err_keys_reg; ++ } ++ ++ rpisense_js->keys_irq = gpiod_to_irq(rpisense_js->keys_desc); ++ if (rpisense_js->keys_irq < 0) { ++ dev_err(&pdev->dev, "Could not determine keys-int IRQ.\n"); ++ ret = rpisense_js->keys_irq; ++ goto err_keys_reg; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, rpisense_js->keys_irq, ++ keys_irq_handler, IRQF_TRIGGER_RISING, ++ "keys", &pdev->dev); ++ if (ret) { ++ dev_err(&pdev->dev, "IRQ request failed.\n"); ++ goto err_keys_reg; ++ } ++ return 0; ++err_keys_reg: ++ input_unregister_device(rpisense_js->keys_dev); ++err_keys_alloc: ++ input_free_device(rpisense_js->keys_dev); ++ return ret; ++} ++ ++static int rpisense_js_remove(struct platform_device *pdev) ++{ ++ struct rpisense_js *rpisense_js = &rpisense->joystick; ++ ++ input_unregister_device(rpisense_js->keys_dev); ++ input_free_device(rpisense_js->keys_dev); ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id rpisense_js_id[] = { ++ { .compatible = "rpi,rpi-sense-js" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rpisense_js_id); ++#endif ++ ++static struct platform_device_id rpisense_js_device_id[] = { ++ { .name = "rpi-sense-js" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(platform, rpisense_js_device_id); ++ ++static struct platform_driver rpisense_js_driver = { ++ .probe = rpisense_js_probe, ++ .remove = rpisense_js_remove, ++ .driver = { ++ .name = "rpi-sense-js", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(rpisense_js_driver); ++ ++MODULE_DESCRIPTION("Raspberry Pi Sense HAT joystick driver"); ++MODULE_AUTHOR("Serge Schneider "); ++MODULE_LICENSE("GPL"); +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -10,6 +10,14 @@ config MFD_CORE + select IRQ_DOMAIN + default n + ++config MFD_RPISENSE_CORE ++ tristate "Raspberry Pi Sense HAT core functions" ++ depends on I2C ++ select MFD_CORE ++ help ++ This is the core driver for the Raspberry Pi Sense HAT. This provides ++ the necessary functions to communicate with the hardware. ++ + config MFD_CS5535 + tristate "AMD CS5535 and CS5536 southbridge core functions" + select MFD_CORE +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -185,3 +185,5 @@ obj-$(CONFIG_MFD_SKY81452) += sky81452.o + intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o + obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o + obj-$(CONFIG_MFD_MT6397) += mt6397-core.o ++ ++obj-$(CONFIG_MFD_RPISENSE_CORE) += rpisense-core.o +--- /dev/null ++++ b/drivers/mfd/rpisense-core.c +@@ -0,0 +1,157 @@ ++/* ++ * Raspberry Pi Sense HAT core driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This driver is based on wm8350 implementation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct rpisense *rpisense; ++ ++static void rpisense_client_dev_register(struct rpisense *rpisense, ++ const char *name, ++ struct platform_device **pdev) ++{ ++ int ret; ++ ++ *pdev = platform_device_alloc(name, -1); ++ if (*pdev == NULL) { ++ dev_err(rpisense->dev, "Failed to allocate %s\n", name); ++ return; ++ } ++ ++ (*pdev)->dev.parent = rpisense->dev; ++ platform_set_drvdata(*pdev, rpisense); ++ ret = platform_device_add(*pdev); ++ if (ret != 0) { ++ dev_err(rpisense->dev, "Failed to register %s: %d\n", ++ name, ret); ++ platform_device_put(*pdev); ++ *pdev = NULL; ++ } ++} ++ ++static int rpisense_probe(struct i2c_client *i2c, ++ const struct i2c_device_id *id) ++{ ++ int ret; ++ struct rpisense_js *rpisense_js; ++ ++ rpisense = devm_kzalloc(&i2c->dev, sizeof(struct rpisense), GFP_KERNEL); ++ if (rpisense == NULL) ++ return -ENOMEM; ++ ++ i2c_set_clientdata(i2c, rpisense); ++ rpisense->dev = &i2c->dev; ++ rpisense->i2c_client = i2c; ++ ++ ret = rpisense_reg_read(rpisense, RPISENSE_WAI); ++ if (ret > 0) { ++ if (ret != 's') ++ return -EINVAL; ++ } else { ++ return ret; ++ } ++ ret = rpisense_reg_read(rpisense, RPISENSE_VER); ++ if (ret < 0) ++ return ret; ++ ++ dev_info(rpisense->dev, ++ "Raspberry Pi Sense HAT firmware version %i\n", ret); ++ ++ rpisense_js = &rpisense->joystick; ++ rpisense_js->keys_desc = devm_gpiod_get(&i2c->dev, ++ "keys-int", GPIOD_IN); ++ if (IS_ERR(rpisense_js->keys_desc)) { ++ dev_warn(&i2c->dev, "Failed to get keys-int descriptor.\n"); ++ rpisense_js->keys_desc = gpio_to_desc(23); ++ if (rpisense_js->keys_desc == NULL) { ++ dev_err(&i2c->dev, "GPIO23 fallback failed.\n"); ++ return PTR_ERR(rpisense_js->keys_desc); ++ } ++ } ++ rpisense_client_dev_register(rpisense, "rpi-sense-js", ++ &(rpisense->joystick.pdev)); ++ rpisense_client_dev_register(rpisense, "rpi-sense-fb", ++ &(rpisense->framebuffer.pdev)); ++ ++ return 0; ++} ++ ++static int rpisense_remove(struct i2c_client *i2c) ++{ ++ struct rpisense *rpisense = i2c_get_clientdata(i2c); ++ ++ platform_device_unregister(rpisense->joystick.pdev); ++ return 0; ++} ++ ++struct rpisense *rpisense_get_dev(void) ++{ ++ return rpisense; ++} ++EXPORT_SYMBOL_GPL(rpisense_get_dev); ++ ++s32 rpisense_reg_read(struct rpisense *rpisense, int reg) ++{ ++ int ret = i2c_smbus_read_byte_data(rpisense->i2c_client, reg); ++ ++ if (ret < 0) ++ dev_err(rpisense->dev, "Read from reg %d failed\n", reg); ++ /* Due to the BCM270x I2C clock stretching bug, some values ++ * may have MSB set. Clear it to avoid incorrect values. ++ * */ ++ return ret & 0x7F; ++} ++EXPORT_SYMBOL_GPL(rpisense_reg_read); ++ ++int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count) ++{ ++ int ret = i2c_master_send(rpisense->i2c_client, buf, count); ++ ++ if (ret < 0) ++ dev_err(rpisense->dev, "Block write failed\n"); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rpisense_block_write); ++ ++static const struct i2c_device_id rpisense_i2c_id[] = { ++ { "rpi-sense", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, rpisense_i2c_id); ++ ++ ++static struct i2c_driver rpisense_driver = { ++ .driver = { ++ .name = "rpi-sense", ++ .owner = THIS_MODULE, ++ }, ++ .probe = rpisense_probe, ++ .remove = rpisense_remove, ++ .id_table = rpisense_i2c_id, ++}; ++ ++module_i2c_driver(rpisense_driver); ++ ++MODULE_DESCRIPTION("Raspberry Pi Sense HAT core driver"); ++MODULE_AUTHOR("Serge Schneider "); ++MODULE_LICENSE("GPL"); ++ +--- a/drivers/video/fbdev/Kconfig ++++ b/drivers/video/fbdev/Kconfig +@@ -2495,3 +2495,16 @@ config FB_SSD1307 + help + This driver implements support for the Solomon SSD1307 + OLED controller over I2C. ++ ++config FB_RPISENSE ++ tristate "Raspberry Pi Sense HAT framebuffer" ++ depends on FB ++ select MFD_RPISENSE_CORE ++ select FB_SYS_FOPS ++ select FB_SYS_FILLRECT ++ select FB_SYS_COPYAREA ++ select FB_SYS_IMAGEBLIT ++ select FB_DEFERRED_IO ++ ++ help ++ This is the framebuffer driver for the Raspberry Pi Sense HAT +--- a/drivers/video/fbdev/Makefile ++++ b/drivers/video/fbdev/Makefile +@@ -150,6 +150,7 @@ obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o + obj-$(CONFIG_FB_MXS) += mxsfb.o + obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o + obj-$(CONFIG_FB_SIMPLE) += simplefb.o ++obj-$(CONFIG_FB_RPISENSE) += rpisense-fb.o + + # the test framebuffer is last + obj-$(CONFIG_FB_VIRTUAL) += vfb.o +--- /dev/null ++++ b/drivers/video/fbdev/rpisense-fb.c +@@ -0,0 +1,235 @@ ++/* ++ * Raspberry Pi Sense HAT framebuffer driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct rpisense *rpisense; ++ ++struct rpisense_fb_param { ++ char __iomem *vmem; ++ u8 *vmem_work; ++ u32 vmemsize; ++ u8 gamma[32]; ++}; ++ ++static struct rpisense_fb_param rpisense_fb_param = { ++ .vmem = NULL, ++ .vmemsize = 128, ++ .gamma = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, ++ 0x02, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0E, 0x0F, 0x11, ++ 0x12, 0x14, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,}, ++}; ++ ++static struct fb_deferred_io rpisense_fb_defio; ++ ++static struct fb_fix_screeninfo rpisense_fb_fix = { ++ .id = "RPi-Sense FB", ++ .type = FB_TYPE_PACKED_PIXELS, ++ .visual = FB_VISUAL_TRUECOLOR, ++ .xpanstep = 0, ++ .ypanstep = 0, ++ .ywrapstep = 0, ++ .accel = FB_ACCEL_NONE, ++ .line_length = 16, ++}; ++ ++static struct fb_var_screeninfo rpisense_fb_var = { ++ .xres = 8, ++ .yres = 8, ++ .xres_virtual = 8, ++ .yres_virtual = 8, ++ .bits_per_pixel = 16, ++ .red = {11, 5, 0}, ++ .green = {5, 6, 0}, ++ .blue = {0, 5, 0}, ++}; ++ ++static ssize_t rpisense_fb_write(struct fb_info *info, ++ const char __user *buf, size_t count, ++ loff_t *ppos) ++{ ++ ssize_t res = fb_sys_write(info, buf, count, ppos); ++ ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++ return res; ++} ++ ++static void rpisense_fb_fillrect(struct fb_info *info, ++ const struct fb_fillrect *rect) ++{ ++ sys_fillrect(info, rect); ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++} ++ ++static void rpisense_fb_copyarea(struct fb_info *info, ++ const struct fb_copyarea *area) ++{ ++ sys_copyarea(info, area); ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++} ++ ++static void rpisense_fb_imageblit(struct fb_info *info, ++ const struct fb_image *image) ++{ ++ sys_imageblit(info, image); ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++} ++ ++static void rpisense_fb_deferred_io(struct fb_info *info, ++ struct list_head *pagelist) ++{ ++ int i; ++ int j; ++ u8 *vmem_work = rpisense_fb_param.vmem_work; ++ u16 *mem = (u16 *)rpisense_fb_param.vmem; ++ u8 *gamma = rpisense_fb_param.gamma; ++ ++ vmem_work[0] = 0; ++ for (j = 0; j < 8; j++) { ++ for (i = 0; i < 8; i++) { ++ vmem_work[(j * 24) + i + 1] = ++ gamma[(mem[(j * 8) + i] >> 11) & 0x1F]; ++ vmem_work[(j * 24) + (i + 8) + 1] = ++ gamma[(mem[(j * 8) + i] >> 6) & 0x1F]; ++ vmem_work[(j * 24) + (i + 16) + 1] = ++ gamma[(mem[(j * 8) + i]) & 0x1F]; ++ } ++ } ++ rpisense_block_write(rpisense, vmem_work, 193); ++} ++ ++static struct fb_deferred_io rpisense_fb_defio = { ++ .delay = HZ/100, ++ .deferred_io = rpisense_fb_deferred_io, ++}; ++ ++static struct fb_ops rpisense_fb_ops = { ++ .owner = THIS_MODULE, ++ .fb_read = fb_sys_read, ++ .fb_write = rpisense_fb_write, ++ .fb_fillrect = rpisense_fb_fillrect, ++ .fb_copyarea = rpisense_fb_copyarea, ++ .fb_imageblit = rpisense_fb_imageblit, ++}; ++ ++static int rpisense_fb_probe(struct platform_device *pdev) ++{ ++ struct fb_info *info; ++ int ret = -ENOMEM; ++ struct rpisense_fb *rpisense_fb; ++ ++ rpisense = rpisense_get_dev(); ++ rpisense_fb = &rpisense->framebuffer; ++ ++ rpisense_fb_param.vmem = vzalloc(rpisense_fb_param.vmemsize); ++ if (!rpisense_fb_param.vmem) ++ return ret; ++ ++ rpisense_fb_param.vmem_work = devm_kmalloc(&pdev->dev, 193, GFP_KERNEL); ++ if (!rpisense_fb_param.vmem_work) ++ goto err_malloc; ++ ++ info = framebuffer_alloc(0, &pdev->dev); ++ if (!info) { ++ dev_err(&pdev->dev, "Could not allocate framebuffer.\n"); ++ goto err_malloc; ++ } ++ rpisense_fb->info = info; ++ ++ rpisense_fb_fix.smem_start = (unsigned long)rpisense_fb_param.vmem; ++ rpisense_fb_fix.smem_len = rpisense_fb_param.vmemsize; ++ ++ info->fbops = &rpisense_fb_ops; ++ info->fix = rpisense_fb_fix; ++ info->var = rpisense_fb_var; ++ info->fbdefio = &rpisense_fb_defio; ++ info->flags = FBINFO_FLAG_DEFAULT | FBINFO_VIRTFB; ++ info->screen_base = rpisense_fb_param.vmem; ++ info->screen_size = rpisense_fb_param.vmemsize; ++ ++ fb_deferred_io_init(info); ++ ++ ret = register_framebuffer(info); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Could not register framebuffer.\n"); ++ goto err_fballoc; ++ } ++ ++ fb_info(info, "%s frame buffer device\n", info->fix.id); ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++ return 0; ++err_fballoc: ++ framebuffer_release(info); ++err_malloc: ++ vfree(rpisense_fb_param.vmem); ++ return ret; ++} ++ ++static int rpisense_fb_remove(struct platform_device *pdev) ++{ ++ struct rpisense_fb *rpisense_fb = &rpisense->framebuffer; ++ struct fb_info *info = rpisense_fb->info; ++ ++ if (info) { ++ unregister_framebuffer(info); ++ fb_deferred_io_cleanup(info); ++ framebuffer_release(info); ++ vfree(rpisense_fb_param.vmem); ++ } ++ ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id rpisense_fb_id[] = { ++ { .compatible = "rpi,rpi-sense-fb" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rpisense_fb_id); ++#endif ++ ++static struct platform_device_id rpisense_fb_device_id[] = { ++ { .name = "rpi-sense-fb" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(platform, rpisense_fb_device_id); ++ ++static struct platform_driver rpisense_fb_driver = { ++ .probe = rpisense_fb_probe, ++ .remove = rpisense_fb_remove, ++ .driver = { ++ .name = "rpi-sense-fb", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(rpisense_fb_driver); ++ ++MODULE_DESCRIPTION("Raspberry Pi Sense HAT framebuffer driver"); ++MODULE_AUTHOR("Serge Schneider "); ++MODULE_LICENSE("GPL"); ++ +--- /dev/null ++++ b/include/linux/mfd/rpisense/core.h +@@ -0,0 +1,47 @@ ++/* ++ * Raspberry Pi Sense HAT core driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef __LINUX_MFD_RPISENSE_CORE_H_ ++#define __LINUX_MFD_RPISENSE_CORE_H_ ++ ++#include ++#include ++ ++/* ++ * Register values. ++ */ ++#define RPISENSE_FB 0x00 ++#define RPISENSE_WAI 0xF0 ++#define RPISENSE_VER 0xF1 ++#define RPISENSE_KEYS 0xF2 ++#define RPISENSE_EE_WP 0xF3 ++ ++#define RPISENSE_ID 's' ++ ++struct rpisense { ++ struct device *dev; ++ struct i2c_client *i2c_client; ++ ++ /* Client devices */ ++ struct rpisense_js joystick; ++ struct rpisense_fb framebuffer; ++}; ++ ++struct rpisense *rpisense_get_dev(void); ++s32 rpisense_reg_read(struct rpisense *rpisense, int reg); ++int rpisense_reg_write(struct rpisense *rpisense, int reg, u16 val); ++int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count); ++ ++#endif +--- /dev/null ++++ b/include/linux/mfd/rpisense/framebuffer.h +@@ -0,0 +1,28 @@ ++/* ++ * Raspberry Pi Sense HAT framebuffer driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef __LINUX_RPISENSE_FB_H_ ++#define __LINUX_RPISENSE_FB_H_ ++ ++#include ++ ++struct rpisense; ++ ++struct rpisense_fb { ++ struct platform_device *pdev; ++ struct fb_info *info; ++}; ++ ++#endif +--- /dev/null ++++ b/include/linux/mfd/rpisense/joystick.h +@@ -0,0 +1,35 @@ ++/* ++ * Raspberry Pi Sense HAT joystick driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef __LINUX_RPISENSE_JOYSTICK_H_ ++#define __LINUX_RPISENSE_JOYSTICK_H_ ++ ++#include ++#include ++#include ++#include ++ ++struct rpisense; ++ ++struct rpisense_js { ++ struct platform_device *pdev; ++ struct input_dev *keys_dev; ++ struct gpio_desc *keys_desc; ++ struct work_struct keys_work_s; ++ int keys_irq; ++}; ++ ++ ++#endif diff --git a/target/linux/brcm2708/patches-4.1/0123-leds-gpio-Implement-the-brightness_get-method.patch b/target/linux/brcm2708/patches-4.1/0123-leds-gpio-Implement-the-brightness_get-method.patch new file mode 100644 index 0000000..4c1e2ce --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0123-leds-gpio-Implement-the-brightness_get-method.patch @@ -0,0 +1,43 @@ +From 5a3324e4eb8898d293fdc562117877cb313718a1 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 15 Jul 2015 13:46:08 +0100 +Subject: [PATCH 123/203] leds-gpio: Implement the brightness_get method + +The power LED uses some clever logic that means it is driven +by a voltage measuring circuit when configured as input, otherwise +it is driven by the GPIO output value. This patch wires up the +brightness_get method for leds-gpio so that user-space can monitor +the LED value via /sys/class/gpio/led1/brightness. Using the input +trigger this returns an indication of the system power health, +otherwise it is just whatever value the trigger has written most +recently. + +See: https://github.com/raspberrypi/linux/issues/1064 +--- + drivers/leds/leds-gpio.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/leds/leds-gpio.c ++++ b/drivers/leds/leds-gpio.c +@@ -82,6 +82,13 @@ static void gpio_led_set(struct led_clas + } + } + ++static enum led_brightness gpio_led_get(struct led_classdev *led_cdev) ++{ ++ struct gpio_led_data *led_dat = ++ container_of(led_cdev, struct gpio_led_data, cdev); ++ return gpiod_get_value_cansleep(led_dat->gpiod) ? LED_FULL : LED_OFF; ++} ++ + static int gpio_blink_set(struct led_classdev *led_cdev, + unsigned long *delay_on, unsigned long *delay_off) + { +@@ -138,6 +145,7 @@ static int create_gpio_led(const struct + led_dat->cdev.blink_set = gpio_blink_set; + } + led_dat->cdev.brightness_set = gpio_led_set; ++ led_dat->cdev.brightness_get = gpio_led_get; + if (template->default_state == LEDS_GPIO_DEFSTATE_KEEP) + state = !!gpiod_get_value_cansleep(led_dat->gpiod); + else diff --git a/target/linux/brcm2708/patches-4.1/0124-dmaengine-bcm2708-dmaengine-Fix-memory-leak-when-sto.patch b/target/linux/brcm2708/patches-4.1/0124-dmaengine-bcm2708-dmaengine-Fix-memory-leak-when-sto.patch new file mode 100644 index 0000000..cf82527 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0124-dmaengine-bcm2708-dmaengine-Fix-memory-leak-when-sto.patch @@ -0,0 +1,20 @@ +From e5c8a89d140e14ac6d393fd13b7b63ed1c860799 Mon Sep 17 00:00:00 2001 +From: Robert Tiemann +Date: Fri, 17 Jul 2015 09:50:55 +0200 +Subject: [PATCH 124/203] dmaengine: bcm2708-dmaengine: Fix memory leak when + stopping a running transfer + +--- + drivers/dma/bcm2708-dmaengine.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/dma/bcm2708-dmaengine.c ++++ b/drivers/dma/bcm2708-dmaengine.c +@@ -964,6 +964,7 @@ static int bcm2835_dma_terminate_all(str + * c->desc is NULL and exit.) + */ + if (c->desc) { ++ bcm2835_dma_desc_free(&c->desc->vd); + c->desc = NULL; + bcm2835_dma_abort(c->chan_base); + diff --git a/target/linux/brcm2708/patches-4.1/0125-BCM270X_DT-Fix-I2S-register-map.patch b/target/linux/brcm2708/patches-4.1/0125-BCM270X_DT-Fix-I2S-register-map.patch new file mode 100644 index 0000000..21619e9 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0125-BCM270X_DT-Fix-I2S-register-map.patch @@ -0,0 +1,22 @@ +From 0e3c310017ae1a6491ac908502ab2999133f9517 Mon Sep 17 00:00:00 2001 +From: Robert Tiemann +Date: Mon, 20 Jul 2015 11:01:13 +0200 +Subject: [PATCH 125/203] BCM270X_DT: Fix I2S register map + +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -117,8 +117,8 @@ + + i2s: i2s@7e203000 { + compatible = "brcm,bcm2708-i2s"; +- reg = <0x7e203000 0x20>, +- <0x7e101098 0x02>; ++ reg = <0x7e203000 0x24>, ++ <0x7e101098 0x08>; + + //dmas = <&dma 2>, + // <&dma 3>; diff --git a/target/linux/brcm2708/patches-4.1/0126-BCM2835_DT-Fix-I2S-register-map.patch b/target/linux/brcm2708/patches-4.1/0126-BCM2835_DT-Fix-I2S-register-map.patch new file mode 100644 index 0000000..13a5777 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0126-BCM2835_DT-Fix-I2S-register-map.patch @@ -0,0 +1,50 @@ +From 81e9e11782bc1ed34d1ada5f019aa7baa03ecf29 Mon Sep 17 00:00:00 2001 +From: Robert Tiemann +Date: Mon, 20 Jul 2015 11:01:25 +0200 +Subject: [PATCH 126/203] BCM2835_DT: Fix I2S register map + +--- + Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt | 4 ++-- + Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt | 4 ++-- + arch/arm/boot/dts/bcm2835.dtsi | 4 ++-- + 3 files changed, 6 insertions(+), 6 deletions(-) + +--- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt ++++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt +@@ -48,8 +48,8 @@ Example: + + bcm2835_i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; +- reg = < 0x7e203000 0x20>, +- < 0x7e101098 0x02>; ++ reg = < 0x7e203000 0x24>, ++ < 0x7e101098 0x08>; + + dmas = <&dma 2>, + <&dma 3>; +--- a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt ++++ b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt +@@ -16,8 +16,8 @@ Example: + + bcm2835_i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; +- reg = <0x7e203000 0x20>, +- <0x7e101098 0x02>; ++ reg = <0x7e203000 0x24>, ++ <0x7e101098 0x08>; + + dmas = <&dma 2>, + <&dma 3>; +--- a/arch/arm/boot/dts/bcm2835.dtsi ++++ b/arch/arm/boot/dts/bcm2835.dtsi +@@ -101,8 +101,8 @@ + + i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; +- reg = <0x7e203000 0x20>, +- <0x7e101098 0x02>; ++ reg = <0x7e203000 0x24>, ++ <0x7e101098 0x08>; + + dmas = <&dma 2>, + <&dma 3>; diff --git a/target/linux/brcm2708/patches-4.1/0127-config-Enable-SHT-drivers-for-raspberry-pi.patch b/target/linux/brcm2708/patches-4.1/0127-config-Enable-SHT-drivers-for-raspberry-pi.patch new file mode 100644 index 0000000..829d6f4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0127-config-Enable-SHT-drivers-for-raspberry-pi.patch @@ -0,0 +1,40 @@ +From 8613a587054df5b7932fbe309cd23b9ff0418b2f Mon Sep 17 00:00:00 2001 +From: David Frey +Date: Tue, 14 Jul 2015 15:57:36 +0200 +Subject: [PATCH 127/203] config: Enable SHT drivers for raspberry pi + +The SHT temperature and humidity sensors are often used in weather +station projects. + +Signed-off-by: David Frey +--- + arch/arm/configs/bcm2709_defconfig | 4 +++- + arch/arm/configs/bcmrpi_defconfig | 4 +++- + 2 files changed, 6 insertions(+), 2 deletions(-) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -611,7 +611,9 @@ CONFIG_W1_SLAVE_BQ27000=m + CONFIG_BATTERY_DS2760=m + CONFIG_POWER_RESET=y + CONFIG_POWER_RESET_GPIO=y +-# CONFIG_HWMON is not set ++CONFIG_HWMON=m ++CONFIG_SENSORS_SHT21=m ++CONFIG_SENSORS_SHTC1=m + CONFIG_THERMAL=y + CONFIG_THERMAL_BCM2835=y + CONFIG_WATCHDOG=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -604,7 +604,9 @@ CONFIG_W1_SLAVE_BQ27000=m + CONFIG_BATTERY_DS2760=m + CONFIG_POWER_RESET=y + CONFIG_POWER_RESET_GPIO=y +-# CONFIG_HWMON is not set ++CONFIG_HWMON=m ++CONFIG_SENSORS_SHT21=m ++CONFIG_SENSORS_SHTC1=m + CONFIG_THERMAL=y + CONFIG_THERMAL_BCM2835=y + CONFIG_WATCHDOG=y diff --git a/target/linux/brcm2708/patches-4.1/0128-BCM270X_DT-Correct-typo-in-overlays-README.patch b/target/linux/brcm2708/patches-4.1/0128-BCM270X_DT-Correct-typo-in-overlays-README.patch new file mode 100644 index 0000000..d9bc905 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0128-BCM270X_DT-Correct-typo-in-overlays-README.patch @@ -0,0 +1,20 @@ +From 2cad6845b413edda55d780d830d1facaca7406d7 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 20 Jul 2015 14:07:14 +0100 +Subject: [PATCH 128/203] BCM270X_DT: Correct typo in overlays/README + +--- + arch/arm/boot/dts/overlays/README | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -78,7 +78,7 @@ Name: + Info: Configures the base Raspberry Pi hardware + Load: + Params: +- audio Set to "on" to disable the onboard ALSA audio ++ audio Set to "on" to enable the onboard ALSA audio + interface (default "off") + + i2c_arm Set to "on" to enable the ARM's i2c interface diff --git a/target/linux/brcm2708/patches-4.1/0129-bcm2835-sdhost-Add-the-ERASE-capability.patch b/target/linux/brcm2708/patches-4.1/0129-bcm2835-sdhost-Add-the-ERASE-capability.patch new file mode 100644 index 0000000..8aa47e8 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0129-bcm2835-sdhost-Add-the-ERASE-capability.patch @@ -0,0 +1,21 @@ +From d9866cb6e1c088b399f9fbe52827499f2d973204 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 20 Jul 2015 10:53:26 +0100 +Subject: [PATCH 129/203] bcm2835-sdhost: Add the ERASE capability + +See: https://github.com/raspberrypi/linux/issues/1076 +--- + drivers/mmc/host/bcm2835-sdhost.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mmc/host/bcm2835-sdhost.c ++++ b/drivers/mmc/host/bcm2835-sdhost.c +@@ -1675,7 +1675,7 @@ int bcm2835_sdhost_add_host(struct bcm28 + /* host controller capabilities */ + mmc->caps |= /* MMC_CAP_SDIO_IRQ |*/ MMC_CAP_4_BIT_DATA | + MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | +- MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | ++ MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE | + (ALLOW_CMD23 * MMC_CAP_CMD23); + + spin_lock_init(&host->lock); diff --git a/target/linux/brcm2708/patches-4.1/0130-bcm2835-sdhost-Ignore-CRC7-for-MMC-CMD1.patch b/target/linux/brcm2708/patches-4.1/0130-bcm2835-sdhost-Ignore-CRC7-for-MMC-CMD1.patch new file mode 100644 index 0000000..ff80ffc --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0130-bcm2835-sdhost-Ignore-CRC7-for-MMC-CMD1.patch @@ -0,0 +1,64 @@ +From abc4d789f9fd535f05a3dcb08712dfd6bada45b6 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 20 Jul 2015 17:32:18 +0100 +Subject: [PATCH 130/203] bcm2835-sdhost: Ignore CRC7 for MMC CMD1 + +It seems that the sdhost interface returns CRC7 errors for CMD1, +which is the MMC-specific SEND_OP_COND. Returning these errors to +the MMC layer causes a downward spiral, but ignoring them seems +to be harmless. +--- + drivers/mmc/host/bcm2835-sdhost.c | 39 +++++++++++++++++++++++---------------- + 1 file changed, 23 insertions(+), 16 deletions(-) + +--- a/drivers/mmc/host/bcm2835-sdhost.c ++++ b/drivers/mmc/host/bcm2835-sdhost.c +@@ -959,25 +959,32 @@ static void bcm2835_sdhost_finish_comman + mmc_hostname(host->mmc), sdcmd, sdhsts, + bcm2835_sdhost_read(host, SDEDM)); + +- if (sdhsts & SDHSTS_CMD_TIME_OUT) { +- switch (host->cmd->opcode) { +- case 5: case 52: case 53: +- /* Don't warn about SDIO commands */ +- break; +- default: +- pr_err("%s: command timeout\n", ++ if ((sdhsts & SDHSTS_CRC7_ERROR) && ++ (host->cmd->opcode == 1)) { ++ if (host->debug) ++ pr_info("%s: ignoring CRC7 error for CMD1\n", ++ mmc_hostname(host->mmc)); ++ } else { ++ if (sdhsts & SDHSTS_CMD_TIME_OUT) { ++ switch (host->cmd->opcode) { ++ case 5: case 52: case 53: ++ /* Don't warn about SDIO commands */ ++ break; ++ default: ++ pr_err("%s: command timeout\n", ++ mmc_hostname(host->mmc)); ++ break; ++ } ++ host->cmd->error = -ETIMEDOUT; ++ } else { ++ pr_err("%s: unexpected command error\n", + mmc_hostname(host->mmc)); +- break; ++ bcm2835_sdhost_dumpregs(host); ++ host->cmd->error = -EIO; + } +- host->cmd->error = -ETIMEDOUT; +- } else { +- pr_err("%s: unexpected command error\n", +- mmc_hostname(host->mmc)); +- bcm2835_sdhost_dumpregs(host); +- host->cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; + } +- tasklet_schedule(&host->finish_tasklet); +- return; + } + + if (host->cmd->flags & MMC_RSP_PRESENT) { diff --git a/target/linux/brcm2708/patches-4.1/0131-BCM270X_DT-Add-unit-address-to-gpio-node-name.patch b/target/linux/brcm2708/patches-4.1/0131-BCM270X_DT-Add-unit-address-to-gpio-node-name.patch new file mode 100644 index 0000000..3779020 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0131-BCM270X_DT-Add-unit-address-to-gpio-node-name.patch @@ -0,0 +1,20 @@ +From 60fce832707c7c02890a8842ae264d27a738c0e7 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 20 Jul 2015 14:48:21 +0100 +Subject: [PATCH 131/203] BCM270X_DT: Add unit address to gpio node name + +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -92,7 +92,7 @@ + status = "disabled"; + }; + +- gpio: gpio { ++ gpio: gpio@7e200000 { + compatible = "brcm,bcm2835-gpio"; + reg = <0x7e200000 0xb4>; + interrupts = <2 17>, <2 18>; diff --git a/target/linux/brcm2708/patches-4.1/0132-BCM270X_DT-Use-i2c_arm-for-rtc-and-bmp085-overlays.patch b/target/linux/brcm2708/patches-4.1/0132-BCM270X_DT-Use-i2c_arm-for-rtc-and-bmp085-overlays.patch new file mode 100644 index 0000000..1a6166e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0132-BCM270X_DT-Use-i2c_arm-for-rtc-and-bmp085-overlays.patch @@ -0,0 +1,32 @@ +From e7827fda51b1e1a87bc749fdd45ecf756efb12d1 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 24 Jul 2015 10:36:32 +0100 +Subject: [PATCH 132/203] BCM270X_DT: Use i2c_arm for rtc and bmp085 overlays + +--- + arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts | 2 +- + arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts ++++ b/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts +@@ -6,7 +6,7 @@ + compatible = "brcm,bcm2708"; + + fragment@0 { +- target = <&i2c1>; ++ target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; +--- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts ++++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts +@@ -6,7 +6,7 @@ + compatible = "brcm,bcm2708"; + + fragment@0 { +- target = <&i2c1>; ++ target = <&i2c_arm>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; diff --git a/target/linux/brcm2708/patches-4.1/0133-BCM2708_DT-CM-dtparams-for-audio-watchdog-and-RNG.patch b/target/linux/brcm2708/patches-4.1/0133-BCM2708_DT-CM-dtparams-for-audio-watchdog-and-RNG.patch new file mode 100644 index 0000000..36f5567 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0133-BCM2708_DT-CM-dtparams-for-audio-watchdog-and-RNG.patch @@ -0,0 +1,30 @@ +From 80612a8dd0dae6bb6245080d938dc6748e68e6a6 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 24 Jul 2015 12:11:31 +0100 +Subject: [PATCH 133/203] BCM2708_DT: CM dtparams for audio, watchdog and RNG + +--- + arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi +@@ -17,14 +17,14 @@ + status = "okay"; + }; + +-&audio { +- status = "okay"; +-}; +- + / { + __overrides__ { + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; ++ ++ audio = <&audio>,"status"; ++ watchdog = <&watchdog>,"status"; ++ random = <&random>,"status"; + }; + }; diff --git a/target/linux/brcm2708/patches-4.1/0134-vchiq-Use-firmware-API.patch b/target/linux/brcm2708/patches-4.1/0134-vchiq-Use-firmware-API.patch new file mode 100644 index 0000000..b8e5e55 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0134-vchiq-Use-firmware-API.patch @@ -0,0 +1,112 @@ +From 5334f431eec498e36a589867e73adb36b476fa3f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Mon, 20 Jul 2015 12:13:18 +0200 +Subject: [PATCH 134/203] vchiq: Use firmware API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use the new firmware API instead of the legacy mailbox API. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 1 + + .../vc04_services/interface/vchiq_arm/vchiq_2835_arm.c | 17 +++++++++-------- + .../misc/vc04_services/interface/vchiq_arm/vchiq_arm.c | 17 +++++++++++++++++ + 3 files changed, 27 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -225,6 +225,7 @@ + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; + cache-line-size = <32>; ++ firmware = <&firmware>; + }; + + thermal: thermal { +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +@@ -39,11 +39,11 @@ + #include + #include + #include +-#include + #include + #include + #include + #include ++#include + + #define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32) + +@@ -89,10 +89,12 @@ free_pagelist(PAGELIST_T *pagelist, int + int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state) + { + struct device *dev = &pdev->dev; ++ struct rpi_firmware *fw = platform_get_drvdata(pdev); + VCHIQ_SLOT_ZERO_T *vchiq_slot_zero; + struct resource *res; + void *slot_mem; + dma_addr_t slot_phys; ++ u32 channelbase; + int slot_mem_size, frag_mem_size; + int err, irq, i; + +@@ -157,13 +159,12 @@ int vchiq_platform_init(struct platform_ + } + + /* Send the base address of the slots to VideoCore */ +- +- dsb(); /* Ensure all writes have completed */ +- +- err = bcm_mailbox_write(MBOX_CHAN_VCHIQ, (unsigned int)slot_phys); +- if (err) { +- dev_err(dev, "mailbox write failed\n"); +- return err; ++ channelbase = slot_phys; ++ err = rpi_firmware_property(fw, RPI_FIRMWARE_VCHIQ_INIT, ++ &channelbase, sizeof(channelbase)); ++ if (err || channelbase) { ++ dev_err(dev, "failed to set channelbase\n"); ++ return err ? : -ENXIO; + } + + vchiq_log_info(vchiq_arm_log_level, +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +@@ -45,7 +45,9 @@ + #include + #include + #include ++#include + #include ++#include + + #include "vchiq_core.h" + #include "vchiq_ioctl.h" +@@ -2793,9 +2795,24 @@ void vchiq_platform_conn_state_changed(V + + static int vchiq_probe(struct platform_device *pdev) + { ++ struct device_node *fw_node; ++ struct rpi_firmware *fw; + int err; + void *ptr_err; + ++ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); ++/* Remove comment when booting without Device Tree is no longer supported ++ if (!fw_node) { ++ dev_err(&pdev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++*/ ++ fw = rpi_firmware_get(fw_node); ++ if (!fw) ++ return -EPROBE_DEFER; ++ ++ platform_set_drvdata(pdev, fw); ++ + /* create debugfs entries */ + err = vchiq_debugfs_init(); + if (err != 0) diff --git a/target/linux/brcm2708/patches-4.1/0135-thermal-bcm2835-Use-firmware-API.patch b/target/linux/brcm2708/patches-4.1/0135-thermal-bcm2835-Use-firmware-API.patch new file mode 100644 index 0000000..291ea48 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0135-thermal-bcm2835-Use-firmware-API.patch @@ -0,0 +1,281 @@ +From fb11a46fed3871b67fcf71631910afba21e6fc22 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Mon, 20 Jul 2015 12:17:10 +0200 +Subject: [PATCH 135/203] thermal: bcm2835: Use firmware API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use the new firmware API instead of the legacy mailbox API. +Remove retry loop on failure to read temperature. +Clean up code. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 1 + + drivers/thermal/bcm2835-thermal.c | 197 +++++++++++++--------------------- + 2 files changed, 75 insertions(+), 123 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -230,6 +230,7 @@ + + thermal: thermal { + compatible = "brcm,bcm2835-thermal"; ++ firmware = <&firmware>; + }; + }; + +--- a/drivers/thermal/bcm2835-thermal.c ++++ b/drivers/thermal/bcm2835-thermal.c +@@ -12,161 +12,113 @@ + * consent. + *****************************************************************************/ + +-#include + #include +-#include +-#include + #include +-#include +-#include + #include ++#include + +- +-/* --- DEFINITIONS --- */ +-#define MODULE_NAME "bcm2835_thermal" +- +-/*#define THERMAL_DEBUG_ENABLE*/ +- +-#ifdef THERMAL_DEBUG_ENABLE +-#define print_debug(fmt,...) printk(KERN_INFO "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) +-#else +-#define print_debug(fmt,...) +-#endif +-#define print_err(fmt,...) printk(KERN_ERR "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) +- +-#define VC_TAG_GET_TEMP 0x00030006 +-#define VC_TAG_GET_MAX_TEMP 0x0003000A +- +-typedef enum { +- TEMP, +- MAX_TEMP, +-} temp_type; +- +-/* --- STRUCTS --- */ +-/* tag part of the message */ +-struct vc_msg_tag { +- uint32_t tag_id; /* the tag ID for the temperature */ +- uint32_t buffer_size; /* size of the buffer (should be 8) */ +- uint32_t request_code; /* identifies message as a request (should be 0) */ +- uint32_t id; /* extra ID field (should be 0) */ +- uint32_t val; /* returned value of the temperature */ +-}; +- +-/* message structure to be sent to videocore */ +-struct vc_msg { +- uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ +- uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ +- struct vc_msg_tag tag; /* the tag structure above to make */ +- uint32_t end_tag; /* an end identifier, should be set to NULL */ +-}; +- +-struct bcm2835_thermal_data { +- struct thermal_zone_device *thermal_dev; +- struct vc_msg msg; +-}; +- +-/* --- GLOBALS --- */ +-static struct bcm2835_thermal_data bcm2835_data; +- +-/* Thermal Device Operations */ +-static struct thermal_zone_device_ops ops; +- +-/* --- FUNCTIONS --- */ +- +-static int bcm2835_get_temp_or_max(struct thermal_zone_device *thermal_dev, unsigned long *temp, unsigned tag_id) ++static int bcm2835_thermal_get_property(struct thermal_zone_device *tz, ++ unsigned long *temp, u32 tag) + { +- int result = -1, retry = 3; +- print_debug("IN"); ++ struct rpi_firmware *fw = tz->devdata; ++ struct { ++ u32 id; ++ u32 val; ++ } packet; ++ int ret; + + *temp = 0; +- while (result != 0 && retry-- > 0) { +- /* wipe all previous message data */ +- memset(&bcm2835_data.msg, 0, sizeof bcm2835_data.msg); +- +- /* prepare message */ +- bcm2835_data.msg.msg_size = sizeof bcm2835_data.msg; +- bcm2835_data.msg.tag.buffer_size = 8; +- bcm2835_data.msg.tag.tag_id = tag_id; +- +- /* send the message */ +- result = bcm_mailbox_property(&bcm2835_data.msg, sizeof bcm2835_data.msg); +- print_debug("Got %stemperature as %u (%d,%x)\n", tag_id==VC_TAG_GET_MAX_TEMP ? "max ":"", (uint)bcm2835_data.msg.tag.val, result, bcm2835_data.msg.request_code); +- if (!(bcm2835_data.msg.request_code & 0x80000000)) +- result = -1; ++ packet.id = 0; ++ ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet)); ++ if (ret) { ++ dev_err(&tz->device, "Failed to get temperature\n"); ++ return ret; + } + +- /* check if it was all ok and return the rate in milli degrees C */ +- if (result == 0) +- *temp = (uint)bcm2835_data.msg.tag.val; +- else +- print_err("Failed to get temperature! (%x:%d)\n", tag_id, result); +- print_debug("OUT"); +- return result; ++ *temp = packet.val; ++ dev_dbg(&tz->device, "%stemp=%lu\n", ++ tag == RPI_FIRMWARE_GET_MAX_TEMPERATURE ? "max" : "", *temp); ++ ++ return 0; + } + +-static int bcm2835_get_temp(struct thermal_zone_device *thermal_dev, unsigned long *temp) ++static int bcm2835_thermal_get_temp(struct thermal_zone_device *tz, ++ unsigned long *temp) + { +- return bcm2835_get_temp_or_max(thermal_dev, temp, VC_TAG_GET_TEMP); ++ return bcm2835_thermal_get_property(tz, temp, ++ RPI_FIRMWARE_GET_TEMPERATURE); + } + +-static int bcm2835_get_max_temp(struct thermal_zone_device *thermal_dev, int trip_num, unsigned long *temp) ++static int bcm2835_thermal_get_max_temp(struct thermal_zone_device *tz, ++ int trip, unsigned long *temp) + { +- return bcm2835_get_temp_or_max(thermal_dev, temp, VC_TAG_GET_MAX_TEMP); ++ /* ++ * The maximum safe temperature of the SoC. ++ * Overclock may be disabled above this temperature. ++ */ ++ return bcm2835_thermal_get_property(tz, temp, ++ RPI_FIRMWARE_GET_MAX_TEMPERATURE); + } + +-static int bcm2835_get_trip_type(struct thermal_zone_device * thermal_dev, int trip_num, enum thermal_trip_type *trip_type) ++static int bcm2835_thermal_get_trip_type(struct thermal_zone_device *tz, ++ int trip, enum thermal_trip_type *type) + { +- *trip_type = THERMAL_TRIP_HOT; ++ *type = THERMAL_TRIP_HOT; ++ + return 0; + } + +- +-static int bcm2835_get_mode(struct thermal_zone_device *thermal_dev, enum thermal_device_mode *dev_mode) ++static int bcm2835_thermal_get_mode(struct thermal_zone_device *tz, ++ enum thermal_device_mode *mode) + { +- *dev_mode = THERMAL_DEVICE_ENABLED; ++ *mode = THERMAL_DEVICE_ENABLED; ++ + return 0; + } + ++static struct thermal_zone_device_ops ops = { ++ .get_temp = bcm2835_thermal_get_temp, ++ .get_trip_temp = bcm2835_thermal_get_max_temp, ++ .get_trip_type = bcm2835_thermal_get_trip_type, ++ .get_mode = bcm2835_thermal_get_mode, ++}; + + static int bcm2835_thermal_probe(struct platform_device *pdev) + { +- print_debug("IN"); +- print_debug("THERMAL Driver has been probed!"); +- +- /* check that the device isn't null!*/ +- if(pdev == NULL) +- { +- print_debug("Platform device is empty!"); +- return -ENODEV; ++ struct device_node *fw_np; ++ struct rpi_firmware *fw; ++ struct thermal_zone_device *tz; ++ ++ fw_np = of_parse_phandle(pdev->dev.of_node, "firmware", 0); ++/* Remove comment when booting without Device Tree is no longer supported ++ if (!fw_np) { ++ dev_err(&pdev->dev, "Missing firmware node\n"); ++ return -ENOENT; + } +- +- if(!(bcm2835_data.thermal_dev = thermal_zone_device_register("bcm2835_thermal", 1, 0, NULL, &ops, NULL, 0, 0))) +- { +- print_debug("Unable to register the thermal device!"); +- return -EFAULT; ++*/ ++ fw = rpi_firmware_get(fw_np); ++ if (!fw) ++ return -EPROBE_DEFER; ++ ++ tz = thermal_zone_device_register("bcm2835_thermal", 1, 0, fw, &ops, ++ NULL, 0, 0); ++ if (IS_ERR(tz)) { ++ dev_err(&pdev->dev, "Failed to register the thermal device\n"); ++ return PTR_ERR(tz); + } ++ ++ platform_set_drvdata(pdev, tz); ++ + return 0; + } + +- + static int bcm2835_thermal_remove(struct platform_device *pdev) + { +- print_debug("IN"); +- +- thermal_zone_device_unregister(bcm2835_data.thermal_dev); +- +- print_debug("OUT"); ++ thermal_zone_device_unregister(platform_get_drvdata(pdev)); + + return 0; + } + +-static struct thermal_zone_device_ops ops = { +- .get_temp = bcm2835_get_temp, +- .get_trip_temp = bcm2835_get_max_temp, +- .get_trip_type = bcm2835_get_trip_type, +- .get_mode = bcm2835_get_mode, +-}; +- + static const struct of_device_id bcm2835_thermal_of_match_table[] = { + { .compatible = "brcm,bcm2835-thermal", }, + {}, +@@ -177,14 +129,13 @@ static struct platform_driver bcm2835_th + .probe = bcm2835_thermal_probe, + .remove = bcm2835_thermal_remove, + .driver = { +- .name = "bcm2835_thermal", +- .owner = THIS_MODULE, +- .of_match_table = bcm2835_thermal_of_match_table, +- }, ++ .name = "bcm2835_thermal", ++ .of_match_table = bcm2835_thermal_of_match_table, ++ }, + }; ++module_platform_driver(bcm2835_thermal_driver); + +-MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Dorian Peake"); ++MODULE_AUTHOR("Noralf Trønnes"); + MODULE_DESCRIPTION("Thermal driver for bcm2835 chip"); +- +-module_platform_driver(bcm2835_thermal_driver); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm2708/patches-4.1/0136-cpufreq-bcm2835-Use-firmware-API.patch b/target/linux/brcm2708/patches-4.1/0136-cpufreq-bcm2835-Use-firmware-API.patch new file mode 100644 index 0000000..0dc3d38 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0136-cpufreq-bcm2835-Use-firmware-API.patch @@ -0,0 +1,186 @@ +From 65ae931012f463feeb8cece70dfc829f2cd2b6b4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Mon, 20 Jul 2015 12:18:36 +0200 +Subject: [PATCH 136/203] cpufreq: bcm2835: Use firmware API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use the new firmware API instead of the legacy mailbox API. + +Signed-off-by: Noralf Trønnes +--- + drivers/cpufreq/bcm2835-cpufreq.c | 117 +++++++++++++++++--------------------- + 1 file changed, 53 insertions(+), 64 deletions(-) + +--- a/drivers/cpufreq/bcm2835-cpufreq.c ++++ b/drivers/cpufreq/bcm2835-cpufreq.c +@@ -26,7 +26,7 @@ + #include + #include + #include +-#include ++#include + + /* ---------- DEFINES ---------- */ + /*#define CPUFREQ_DEBUG_ENABLE*/ /* enable debugging */ +@@ -43,23 +43,6 @@ + #define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) + #define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__) + +-/* tag part of the message */ +-struct vc_msg_tag { +- uint32_t tag_id; /* the message id */ +- uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */ +- uint32_t data_size; /* amount of data being sent or received */ +- uint32_t dev_id; /* the ID of the clock/voltage to get or set */ +- uint32_t val; /* the value (e.g. rate (in Hz)) to set */ +-}; +- +-/* message structure to be sent to videocore */ +-struct vc_msg { +- uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ +- uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ +- struct vc_msg_tag tag; /* the tag structure above to make */ +- uint32_t end_tag; /* an end identifier, should be set to NULL */ +-}; +- + /* ---------- GLOBALS ---------- */ + static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */ + +@@ -74,62 +57,63 @@ static struct cpufreq_frequency_table bc + clk_rate either gets or sets the clock rates. + =============================================== + */ +-static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate) ++ ++static int bcm2835_cpufreq_clock_property(u32 tag, u32 id, u32 *val) + { +- int s, actual_rate=0; +- struct vc_msg msg; ++ struct rpi_firmware *fw = rpi_firmware_get(NULL); ++ struct { ++ u32 id; ++ u32 val; ++ } packet; ++ int ret; ++ ++ packet.id = id; ++ packet.val = *val; ++ ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet)); ++ if (ret) ++ return ret; + +- /* wipe all previous message data */ +- memset(&msg, 0, sizeof msg); ++ *val = packet.val; + +- msg.msg_size = sizeof msg; ++ return 0; ++} + +- msg.tag.tag_id = VCMSG_SET_CLOCK_RATE; +- msg.tag.buffer_size = 8; +- msg.tag.data_size = 8; /* we're sending the clock ID and the new rates which is a total of 2 words */ +- msg.tag.dev_id = VCMSG_ID_ARM_CLOCK; +- msg.tag.val = arm_rate * 1000; ++static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate) ++{ ++ u32 rate = arm_rate * 1000; ++ int ret; + +- /* send the message */ +- s = bcm_mailbox_property(&msg, sizeof msg); ++ ret = bcm2835_cpufreq_clock_property(RPI_FIRMWARE_SET_CLOCK_RATE, VCMSG_ID_ARM_CLOCK, &rate); ++ if (ret) { ++ print_err("Failed to set clock: %d (%d)\n", arm_rate, ret); ++ return 0; ++ } + +- /* check if it was all ok and return the rate in KHz */ +- if (s == 0 && (msg.request_code & 0x80000000)) +- actual_rate = msg.tag.val/1000; ++ rate /= 1000; ++ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, rate); + +- print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, actual_rate); +- return actual_rate; ++ return rate; + } + + static uint32_t bcm2835_cpufreq_get_clock(int tag) + { +- int s; +- int arm_rate = 0; +- struct vc_msg msg; +- +- /* wipe all previous message data */ +- memset(&msg, 0, sizeof msg); +- +- msg.msg_size = sizeof msg; +- msg.tag.tag_id = tag; +- msg.tag.buffer_size = 8; +- msg.tag.data_size = 4; /* we're just sending the clock ID which is one word long */ +- msg.tag.dev_id = VCMSG_ID_ARM_CLOCK; +- +- /* send the message */ +- s = bcm_mailbox_property(&msg, sizeof msg); +- +- /* check if it was all ok and return the rate in KHz */ +- if (s == 0 && (msg.request_code & 0x80000000)) +- arm_rate = msg.tag.val/1000; +- +- print_debug("%s frequency = %d\n", +- tag == VCMSG_GET_CLOCK_RATE ? "Current": +- tag == VCMSG_GET_MIN_CLOCK ? "Min": +- tag == VCMSG_GET_MAX_CLOCK ? "Max": +- "Unexpected", arm_rate); ++ u32 rate; ++ int ret; ++ ++ ret = bcm2835_cpufreq_clock_property(tag, VCMSG_ID_ARM_CLOCK, &rate); ++ if (ret) { ++ print_err("Failed to get clock (%d)\n", ret); ++ return 0; ++ } ++ ++ rate /= 1000; ++ print_debug("%s frequency = %u\n", ++ tag == RPI_FIRMWARE_GET_CLOCK_RATE ? "Current": ++ tag == RPI_FIRMWARE_GET_MIN_CLOCK_RATE ? "Min": ++ tag == RPI_FIRMWARE_GET_MAX_CLOCK_RATE ? "Max": ++ "Unexpected", rate); + +- return arm_rate; ++ return rate; + } + + /* +@@ -165,9 +149,14 @@ static int bcm2835_cpufreq_driver_init(s + /* measured value of how long it takes to change frequency */ + const unsigned int transition_latency = 355000; /* ns */ + ++ if (!rpi_firmware_get(NULL)) { ++ print_err("Firmware is not available\n"); ++ return -ENODEV; ++ } ++ + /* now find out what the maximum and minimum frequencies are */ +- bcm2835_freq_table[0].frequency = bcm2835_cpufreq_get_clock(VCMSG_GET_MIN_CLOCK); +- bcm2835_freq_table[1].frequency = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK); ++ bcm2835_freq_table[0].frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MIN_CLOCK_RATE); ++ bcm2835_freq_table[1].frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MAX_CLOCK_RATE); + + print_info("min=%d max=%d\n", bcm2835_freq_table[0].frequency, bcm2835_freq_table[1].frequency); + return cpufreq_generic_init(policy, bcm2835_freq_table, transition_latency); +@@ -201,8 +190,8 @@ static int bcm2835_cpufreq_driver_target + + static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) + { +- unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); +- print_debug("%d: freq=%d\n", cpu, actual_rate); ++ unsigned int actual_rate = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_CLOCK_RATE); ++ print_debug("cpu%d: freq=%d\n", cpu, actual_rate); + return actual_rate <= bcm2835_freq_table[0].frequency ? bcm2835_freq_table[0].frequency : bcm2835_freq_table[1].frequency; + } + diff --git a/target/linux/brcm2708/patches-4.1/0137-fbdev-bcm2708-Use-firmware-API.patch b/target/linux/brcm2708/patches-4.1/0137-fbdev-bcm2708-Use-firmware-API.patch new file mode 100644 index 0000000..c5ba70b --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0137-fbdev-bcm2708-Use-firmware-API.patch @@ -0,0 +1,413 @@ +From 23f7babfd87a6be47db1e16e1177f5743ddb4ea5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Mon, 20 Jul 2015 12:20:59 +0200 +Subject: [PATCH 137/203] fbdev: bcm2708: Use firmware API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Use the new firmware API instead of the legacy mailbox API. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 1 + + drivers/video/fbdev/bcm2708_fb.c | 273 +++++++++++++++++++--------------- + 2 files changed, 152 insertions(+), 122 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -217,6 +217,7 @@ + + fb: fb { + compatible = "brcm,bcm2708-fb"; ++ firmware = <&firmware>; + status = "disabled"; + }; + +--- a/drivers/video/fbdev/bcm2708_fb.c ++++ b/drivers/video/fbdev/bcm2708_fb.c +@@ -25,7 +25,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -34,6 +33,7 @@ + #include + #include + #include ++#include + + //#define BCM2708_FB_DEBUG + #define MODULE_NAME "bcm2708_fb" +@@ -58,15 +58,19 @@ static u32 dma_busy_wait_threshold = 1<< + module_param(dma_busy_wait_threshold, int, 0644); + MODULE_PARM_DESC(dma_busy_wait_threshold, "Busy-wait for DMA completion below this area"); + +-/* this data structure describes each frame buffer device we find */ +- +-struct fbinfo_s { +- u32 xres, yres, xres_virtual, yres_virtual; +- u32 pitch, bpp; ++struct fb_alloc_tags { ++ struct rpi_firmware_property_tag_header tag1; ++ u32 xres, yres; ++ struct rpi_firmware_property_tag_header tag2; ++ u32 xres_virtual, yres_virtual; ++ struct rpi_firmware_property_tag_header tag3; ++ u32 bpp; ++ struct rpi_firmware_property_tag_header tag4; + u32 xoffset, yoffset; +- u32 base; +- u32 screen_size; +- u16 cmap[256]; ++ struct rpi_firmware_property_tag_header tag5; ++ u32 base, screen_size; ++ struct rpi_firmware_property_tag_header tag6; ++ u32 pitch; + }; + + struct bcm2708_fb_stats { +@@ -78,9 +82,9 @@ struct bcm2708_fb_stats { + struct bcm2708_fb { + struct fb_info fb; + struct platform_device *dev; +- struct fbinfo_s *info; +- dma_addr_t dma; ++ struct rpi_firmware *fw; + u32 cmap[16]; ++ u32 gpu_cmap[256]; + int dma_chan; + int dma_irq; + void __iomem *dma_chan_base; +@@ -270,69 +274,71 @@ static int bcm2708_fb_check_var(struct f + + static int bcm2708_fb_set_par(struct fb_info *info) + { +- uint32_t val = 0; + struct bcm2708_fb *fb = to_bcm2708(info); +- volatile struct fbinfo_s *fbinfo = fb->info; +- fbinfo->xres = info->var.xres; +- fbinfo->yres = info->var.yres; +- fbinfo->xres_virtual = info->var.xres_virtual; +- fbinfo->yres_virtual = info->var.yres_virtual; +- fbinfo->bpp = info->var.bits_per_pixel; +- fbinfo->xoffset = info->var.xoffset; +- fbinfo->yoffset = info->var.yoffset; +- fbinfo->base = 0; /* filled in by VC */ +- fbinfo->pitch = 0; /* filled in by VC */ ++ struct fb_alloc_tags fbinfo = { ++ .tag1 = { RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT, ++ 8, 0, }, ++ .xres = info->var.xres, ++ .yres = info->var.yres, ++ .tag2 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT, ++ 8, 0, }, ++ .xres_virtual = info->var.xres_virtual, ++ .yres_virtual = info->var.yres_virtual, ++ .tag3 = { RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH, 4, 0 }, ++ .bpp = info->var.bits_per_pixel, ++ .tag4 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET, 8, 0 }, ++ .xoffset = info->var.xoffset, ++ .yoffset = info->var.yoffset, ++ .tag5 = { RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE, 8, 0 }, ++ .base = 0, ++ .screen_size = 0, ++ .tag6 = { RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH, 4, 0 }, ++ .pitch = 0, ++ }; ++ int ret; + + print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, + info->var.xres, info->var.yres, info->var.xres_virtual, + info->var.yres_virtual, (int)info->screen_size, + info->var.bits_per_pixel); + +- /* ensure last write to fbinfo is visible to GPU */ +- wmb(); +- +- /* inform vc about new framebuffer */ +- bcm_mailbox_write(MBOX_CHAN_FB, fb->dma); ++ ret = rpi_firmware_property_list(fb->fw, &fbinfo, sizeof(fbinfo)); ++ if (ret) { ++ dev_err(info->device, ++ "Failed to allocate GPU framebuffer (%d)\n", ret); ++ return ret; ++ } + +- /* TODO: replace fb driver with vchiq version */ +- /* wait for response */ +- bcm_mailbox_read(MBOX_CHAN_FB, &val); +- +- /* ensure GPU writes are visible to us */ +- rmb(); +- +- if (val == 0) { +- fb->fb.fix.line_length = fbinfo->pitch; +- +- if (info->var.bits_per_pixel <= 8) +- fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; +- else +- fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; +- +- fb->fb_bus_address = fbinfo->base; +- fbinfo->base &= ~0xc0000000; +- fb->fb.fix.smem_start = fbinfo->base; +- fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual; +- fb->fb.screen_size = fbinfo->screen_size; +- if (fb->fb.screen_base) +- iounmap(fb->fb.screen_base); +- fb->fb.screen_base = +- (void *)ioremap_wc(fbinfo->base, fb->fb.screen_size); +- if (!fb->fb.screen_base) { +- /* the console may currently be locked */ +- console_trylock(); +- console_unlock(); +- pr_err("bcm2708_fb_set_par: Failed to set screen_base\n"); +- return -EIO; +- } ++ if (info->var.bits_per_pixel <= 8) ++ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ else ++ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ ++ fb->fb.fix.line_length = fbinfo.pitch; ++ fbinfo.base |= 0x40000000; ++ fb->fb_bus_address = fbinfo.base; ++ fbinfo.base &= ~0xc0000000; ++ fb->fb.fix.smem_start = fbinfo.base; ++ fb->fb.fix.smem_len = fbinfo.pitch * fbinfo.yres_virtual; ++ fb->fb.screen_size = fbinfo.screen_size; ++ if (fb->fb.screen_base) ++ iounmap(fb->fb.screen_base); ++ fb->fb.screen_base = ioremap_wc(fbinfo.base, fb->fb.screen_size); ++ if (!fb->fb.screen_base) { ++ /* the console may currently be locked */ ++ console_trylock(); ++ console_unlock(); ++ dev_err(info->device, "Failed to set screen_base\n"); ++ return -ENOMEM; + } ++ + print_debug +- ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d success=%d\n", ++ ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d\n", + (void *)fb->fb.screen_base, (void *)fb->fb_bus_address, +- fbinfo->xres, fbinfo->yres, fbinfo->bpp, +- fbinfo->pitch, (int)fb->fb.screen_size, val); ++ fbinfo.xres, fbinfo.yres, fbinfo.bpp, ++ fbinfo.pitch, (int)fb->fb.screen_size); + +- return val; ++ return 0; + } + + static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) +@@ -352,15 +358,34 @@ static int bcm2708_fb_setcolreg(unsigned + /*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/ + if (fb->fb.var.bits_per_pixel <= 8) { + if (regno < 256) { +- /* blue [0:4], green [5:10], red [11:15] */ +- fb->info->cmap[regno] = ((red >> (16-5)) & 0x1f) << 11 | +- ((green >> (16-6)) & 0x3f) << 5 | +- ((blue >> (16-5)) & 0x1f) << 0; ++ /* blue [23:16], green [15:8], red [7:0] */ ++ fb->gpu_cmap[regno] = ((red >> 8) & 0xff) << 0 | ++ ((green >> 8) & 0xff) << 8 | ++ ((blue >> 8) & 0xff) << 16; + } + /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */ + /* So just call it for what looks like the last colour in a list for now. */ +- if (regno == 15 || regno == 255) +- bcm2708_fb_set_par(info); ++ if (regno == 15 || regno == 255) { ++ struct packet { ++ u32 offset; ++ u32 length; ++ u32 cmap[256]; ++ } *packet; ++ int ret; ++ ++ packet = kmalloc(sizeof(*packet), GFP_KERNEL); ++ if (!packet) ++ return -ENOMEM; ++ packet->offset = 0; ++ packet->length = regno + 1; ++ memcpy(packet->cmap, fb->gpu_cmap, sizeof(packet->cmap)); ++ ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE, ++ packet, (2 + packet->length) * sizeof(u32)); ++ if (ret || packet->offset) ++ dev_err(info->device, "Failed to set palette (%d,%u)\n", ++ ret, packet->offset); ++ kfree(packet); ++ } + } else if (regno < 16) { + fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | + convert_bitfield(blue, &fb->fb.var.blue) | +@@ -372,27 +397,31 @@ static int bcm2708_fb_setcolreg(unsigned + + static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) + { +- s32 result = -1; +- u32 p[7]; +- if ( (blank_mode == FB_BLANK_NORMAL) || +- (blank_mode == FB_BLANK_UNBLANK)) { +- +- p[0] = 28; // size = sizeof u32 * length of p +- p[1] = VCMSG_PROCESS_REQUEST; // process request +- p[2] = VCMSG_SET_BLANK_SCREEN; // (the tag id) +- p[3] = 4; // (size of the response buffer) +- p[4] = 4; // (size of the request data) +- p[5] = blank_mode; +- p[6] = VCMSG_PROPERTY_END; // end tag +- +- bcm_mailbox_property(&p, p[0]); +- +- if ( p[1] == VCMSG_REQUEST_SUCCESSFUL ) +- result = 0; +- else +- pr_err("bcm2708_fb_blank(%d) returns=%d p[1]=0x%x\n", blank_mode, p[5], p[1]); ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ u32 value; ++ int ret; ++ ++ switch (blank_mode) { ++ case FB_BLANK_UNBLANK: ++ value = 0; ++ break; ++ case FB_BLANK_NORMAL: ++ case FB_BLANK_VSYNC_SUSPEND: ++ case FB_BLANK_HSYNC_SUSPEND: ++ case FB_BLANK_POWERDOWN: ++ value = 1; ++ break; ++ default: ++ return -EINVAL; + } +- return result; ++ ++ ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK, ++ &value, sizeof(value)); ++ if (ret) ++ dev_err(info->device, "bcm2708_fb_blank(%d) failed: %d\n", ++ blank_mode, ret); ++ ++ return ret; + } + + static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) +@@ -408,25 +437,25 @@ static int bcm2708_fb_pan_display(struct + + static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) + { +- s32 result = -1; +- u32 p[7]; +- if (cmd == FBIO_WAITFORVSYNC) { +- p[0] = 28; // size = sizeof u32 * length of p +- p[1] = VCMSG_PROCESS_REQUEST; // process request +- p[2] = VCMSG_SET_VSYNC; // (the tag id) +- p[3] = 4; // (size of the response buffer) +- p[4] = 4; // (size of the request data) +- p[5] = 0; // dummy +- p[6] = VCMSG_PROPERTY_END; // end tag +- +- bcm_mailbox_property(&p, p[0]); +- +- if ( p[1] == VCMSG_REQUEST_SUCCESSFUL ) +- result = 0; +- else +- pr_err("bcm2708_fb_ioctl %x,%lx returns=%d p[1]=0x%x\n", cmd, arg, p[5], p[1]); ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ u32 dummy = 0; ++ int ret; ++ ++ switch (cmd) { ++ case FBIO_WAITFORVSYNC: ++ ret = rpi_firmware_property(fb->fw, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC, ++ &dummy, sizeof(dummy)); ++ break; ++ default: ++ dev_err(info->device, "Unknown ioctl 0x%x\n", cmd); ++ return -EINVAL; + } +- return result; ++ ++ if (ret) ++ dev_err(info->device, "ioctl 0x%x failed (%d)\n", cmd, ret); ++ ++ return ret; + } + static void bcm2708_fb_fillrect(struct fb_info *info, + const struct fb_fillrect *rect) +@@ -621,20 +650,7 @@ static struct fb_ops bcm2708_fb_ops = { + static int bcm2708_fb_register(struct bcm2708_fb *fb) + { + int ret; +- dma_addr_t dma; +- void *mem; + +- mem = +- dma_alloc_coherent(&fb->dev->dev, PAGE_ALIGN(sizeof(*fb->info)), &dma, +- GFP_KERNEL); +- +- if (NULL == mem) { +- pr_err(": unable to allocate fbinfo buffer\n"); +- ret = -ENOMEM; +- } else { +- fb->info = (struct fbinfo_s *)mem; +- fb->dma = dma; +- } + fb->fb.fbops = &bcm2708_fb_ops; + fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA; + fb->fb.pseudo_palette = fb->cmap; +@@ -693,9 +709,22 @@ out: + + static int bcm2708_fb_probe(struct platform_device *dev) + { ++ struct device_node *fw_np; ++ struct rpi_firmware *fw; + struct bcm2708_fb *fb; + int ret; + ++ fw_np = of_parse_phandle(dev->dev.of_node, "firmware", 0); ++/* Remove comment when booting without Device Tree is no longer supported ++ if (!fw_np) { ++ dev_err(&dev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++*/ ++ fw = rpi_firmware_get(fw_np); ++ if (!fw) ++ return -EPROBE_DEFER; ++ + fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL); + if (!fb) { + dev_err(&dev->dev, +@@ -704,6 +733,7 @@ static int bcm2708_fb_probe(struct platf + goto free_region; + } + ++ fb->fw = fw; + bcm2708_fb_debugfs_init(fb); + + fb->cb_base = dma_alloc_writecombine(&dev->dev, SZ_64K, +@@ -737,6 +767,7 @@ static int bcm2708_fb_probe(struct platf + fb->dma_chan, fb->dma_chan_base); + + fb->dev = dev; ++ fb->fb.device = &dev->dev; + + ret = bcm2708_fb_register(fb); + if (ret == 0) { +@@ -769,8 +800,6 @@ static int bcm2708_fb_remove(struct plat + dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle); + bcm_dma_chan_free(fb->dma_chan); + +- dma_free_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), (void *)fb->info, +- fb->dma); + bcm2708_fb_debugfs_deinit(fb); + + free_irq(fb->dma_irq, fb); diff --git a/target/linux/brcm2708/patches-4.1/0138-bcm2835-Add-firmware-property-to-affected-devices.patch b/target/linux/brcm2708/patches-4.1/0138-bcm2835-Add-firmware-property-to-affected-devices.patch new file mode 100644 index 0000000..1292386 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0138-bcm2835-Add-firmware-property-to-affected-devices.patch @@ -0,0 +1,79 @@ +From 128cfa5445d62b5289ed332c82781ad016aca741 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Mon, 20 Jul 2015 12:27:17 +0200 +Subject: [PATCH 138/203] bcm2835: Add firmware property to affected devices +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Also move firmware depending devices to the rpi dtsi file since +they depend on the Pi specific firmware. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/bcm2835-rpi.dtsi | 22 ++++++++++++++++++---- + arch/arm/boot/dts/bcm2835.dtsi | 15 --------------- + 2 files changed, 18 insertions(+), 19 deletions(-) + +--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi ++++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi +@@ -32,6 +32,24 @@ + compatible = "raspberrypi,bcm2835-firmware"; + mboxes = <&mailbox>; + }; ++ ++ fb: fb { ++ compatible = "brcm,bcm2708-fb"; ++ firmware = <&firmware>; ++ }; ++ ++ thermal: thermal { ++ compatible = "brcm,bcm2835-thermal"; ++ firmware = <&firmware>; ++ }; ++ ++ vchiq: vchiq { ++ compatible = "brcm,bcm2835-vchiq"; ++ reg = <0x7e00b840 0xf>; ++ interrupts = <0 2>; ++ cache-line-size = <32>; ++ firmware = <&firmware>; ++ }; + }; + + /* Onboard audio */ +@@ -101,10 +119,6 @@ + bus-width = <4>; + }; + +-&fb { +- status = "okay"; +-}; +- + / { + __overrides__ { + i2s = <&i2s>,"status"; +--- a/arch/arm/boot/dts/bcm2835.dtsi ++++ b/arch/arm/boot/dts/bcm2835.dtsi +@@ -160,21 +160,6 @@ + arm-pmu { + compatible = "arm,arm1176-pmu"; + }; +- +- fb: fb { +- compatible = "brcm,bcm2708-fb"; +- status = "disabled"; +- }; +- +- vchiq: vchiq { +- compatible = "brcm,bcm2835-vchiq"; +- reg = <0x7e00b840 0xf>; +- interrupts = <0 2>; +- }; +- +- thermal: thermal { +- compatible = "brcm,bcm2835-thermal"; +- }; + }; + + clocks { diff --git a/target/linux/brcm2708/patches-4.1/0139-rpi-ft5406-Use-firmware-API.patch b/target/linux/brcm2708/patches-4.1/0139-rpi-ft5406-Use-firmware-API.patch new file mode 100644 index 0000000..6914910 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0139-rpi-ft5406-Use-firmware-API.patch @@ -0,0 +1,138 @@ +From 9be811d63aab0b9840ebfc3a27e59c0a50404b1d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Tue, 21 Jul 2015 19:09:39 +0200 +Subject: [PATCH 139/203] rpi-ft5406: Use firmware API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts | 1 + + drivers/input/touchscreen/rpi-ft5406.c | 74 ++++++++++------------- + 2 files changed, 32 insertions(+), 43 deletions(-) + +--- a/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts ++++ b/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts +@@ -9,6 +9,7 @@ + __overlay__ { + rpi_ft5406: rpi_ft5406 { + compatible = "rpi,rpi-ft5406"; ++ firmware = <&firmware>; + status = "okay"; + }; + }; +--- a/drivers/input/touchscreen/rpi-ft5406.c ++++ b/drivers/input/touchscreen/rpi-ft5406.c +@@ -21,7 +21,7 @@ + #include + #include + #include +-#include ++#include + + #define MAXIMUM_SUPPORTED_POINTS 10 + struct ft5406_regs { +@@ -49,23 +49,6 @@ struct ft5406 { + struct task_struct * thread; + }; + +- +-/* tag part of the message */ +-struct vc_msg_tag { +- uint32_t tag_id; /* the message id */ +- uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */ +- uint32_t data_size; /* amount of data being sent or received */ +- uint32_t val; /* data buffer */ +-}; +- +-/* message structure to be sent to videocore */ +-struct vc_msg { +- uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ +- uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ +- struct vc_msg_tag tag; /* the tag structure above to make */ +- uint32_t end_tag; /* an end identifier, should be set to NULL */ +-}; +- + /* Thread to poll for touchscreen events + * + * This thread polls the memory based register copy of the ft5406 registers +@@ -136,11 +119,37 @@ static int ft5406_probe(struct platform_ + { + int ret; + struct input_dev * input_dev = input_allocate_device(); +- struct vc_msg request; + struct ft5406 * ts; ++ struct device_node *fw_node; ++ struct rpi_firmware *fw; ++ u32 touchbuf; + + dev_info(&pdev->dev, "Probing device\n"); + ++ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); ++ if (!fw_node) { ++ dev_err(&pdev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++ ++ fw = rpi_firmware_get(fw_node); ++ if (!fw) ++ return -EPROBE_DEFER; ++ ++ ret = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF, ++ &touchbuf, sizeof(touchbuf)); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to get touch buffer\n"); ++ return ret; ++ } ++ ++ if (!touchbuf) { ++ dev_err(&pdev->dev, "Touchscreen not detected\n"); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&pdev->dev, "Got TS buffer 0x%x\n", touchbuf); ++ + ts = kzalloc(sizeof(struct ft5406), GFP_KERNEL); + + if (!ts || !input_dev) { +@@ -174,36 +183,15 @@ static int ft5406_probe(struct platform_ + return ret; + } + +- memset(&request, 0, sizeof request); +- +- request.msg_size = sizeof request; +- request.request_code = VCMSG_PROCESS_REQUEST; +- request.tag.tag_id = VCMSG_GET_TOUCHBUF; +- request.tag.buffer_size = 4; +- request.tag.data_size = 4; +- +- bcm_mailbox_property(&request, sizeof(request)); +- +- if(request.request_code == VCMSG_REQUEST_SUCCESSFUL && request.tag.val != 0) +- { +- dev_dbg(&pdev->dev, "Got TS buffer 0x%x\n", request.tag.val); +- } +- else +- { +- input_unregister_device(input_dev); +- kzfree(ts); +- return -1; +- } +- + // mmap the physical memory +- request.tag.val &= ~0xc0000000; +- ts->ts_base = ioremap(request.tag.val, sizeof(*ts->regs)); ++ touchbuf &= ~0xc0000000; ++ ts->ts_base = ioremap(touchbuf, sizeof(*ts->regs)); + if(ts->ts_base == NULL) + { + dev_err(&pdev->dev, "Failed to map physical address\n"); + input_unregister_device(input_dev); + kzfree(ts); +- return -1; ++ return -ENOMEM; + } + + ts->regs = (struct ft5406_regs *) ts->ts_base; diff --git a/target/linux/brcm2708/patches-4.1/0140-irqchip-bcm2835-Add-FIQ-support.patch b/target/linux/brcm2708/patches-4.1/0140-irqchip-bcm2835-Add-FIQ-support.patch new file mode 100644 index 0000000..89dde5b --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0140-irqchip-bcm2835-Add-FIQ-support.patch @@ -0,0 +1,130 @@ +From 0b5b35852a737361a08e7f6e0a3e6157a15948d9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 12 Jun 2015 19:01:05 +0200 +Subject: [PATCH 140/203] irqchip: bcm2835: Add FIQ support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add a duplicate irq range with an offset on the hwirq's so the +driver can detect that enable_fiq() is used. +Tested with downstream dwc_otg USB controller driver. + +Signed-off-by: Noralf Trønnes +Reviewed-by: Eric Anholt +Acked-by: Stephen Warren +--- + arch/arm/mach-bcm/Kconfig | 1 + + drivers/irqchip/irq-bcm2835.c | 53 ++++++++++++++++++++++++++++++++++++++----- + 2 files changed, 48 insertions(+), 6 deletions(-) + +--- a/arch/arm/mach-bcm/Kconfig ++++ b/arch/arm/mach-bcm/Kconfig +@@ -114,6 +114,7 @@ config ARCH_BCM2835 + select ARM_ERRATA_411920 + select ARM_TIMER_SP804 + select CLKSRC_OF ++ select FIQ + select PINCTRL + select PINCTRL_BCM2835 + help +--- a/drivers/irqchip/irq-bcm2835.c ++++ b/drivers/irqchip/irq-bcm2835.c +@@ -56,7 +56,7 @@ + #include "irqchip.h" + + /* Put the bank and irq (32 bits) into the hwirq */ +-#define MAKE_HWIRQ(b, n) ((b << 5) | (n)) ++#define MAKE_HWIRQ(b, n) (((b) << 5) | (n)) + #define HWIRQ_BANK(i) (i >> 5) + #define HWIRQ_BIT(i) BIT(i & 0x1f) + +@@ -72,9 +72,13 @@ + | SHORTCUT1_MASK | SHORTCUT2_MASK) + + #define REG_FIQ_CONTROL 0x0c ++#define REG_FIQ_ENABLE 0x80 ++#define REG_FIQ_DISABLE 0 + + #define NR_BANKS 3 + #define IRQS_PER_BANK 32 ++#define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0) ++#define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0)) + + static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 }; + static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 }; +@@ -98,14 +102,38 @@ static struct armctrl_ic intc __read_mos + static void __exception_irq_entry bcm2835_handle_irq( + struct pt_regs *regs); + ++static inline unsigned int hwirq_to_fiq(unsigned long hwirq) ++{ ++ hwirq -= NUMBER_IRQS; ++ /* ++ * The hwirq numbering used in this driver is: ++ * BASE (0-7) GPU1 (32-63) GPU2 (64-95). ++ * This differ from the one used in the FIQ register: ++ * GPU1 (0-31) GPU2 (32-63) BASE (64-71) ++ */ ++ if (hwirq >= 32) ++ return hwirq - 32; ++ ++ return hwirq + 64; ++} ++ + static void armctrl_mask_irq(struct irq_data *d) + { +- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); ++ if (d->hwirq >= NUMBER_IRQS) ++ writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL); ++ else ++ writel_relaxed(HWIRQ_BIT(d->hwirq), ++ intc.disable[HWIRQ_BANK(d->hwirq)]); + } + + static void armctrl_unmask_irq(struct irq_data *d) + { +- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); ++ if (d->hwirq >= NUMBER_IRQS) ++ writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), ++ intc.base + REG_FIQ_CONTROL); ++ else ++ writel_relaxed(HWIRQ_BIT(d->hwirq), ++ intc.enable[HWIRQ_BANK(d->hwirq)]); + } + + static struct irq_chip armctrl_chip = { +@@ -150,8 +178,9 @@ static int __init armctrl_of_init(struct + panic("%s: unable to map IC registers\n", + node->full_name); + +- intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0), +- &armctrl_ops, NULL); ++ intc.base = base; ++ intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2, ++ &armctrl_ops, NULL); + if (!intc.domain) + panic("%s: unable to create IRQ domain\n", node->full_name); + +@@ -168,8 +197,20 @@ static int __init armctrl_of_init(struct + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + } +- + set_handle_irq(bcm2835_handle_irq); ++ ++ /* Make a duplicate irq range which is used to enable FIQ */ ++ for (b = 0; b < NR_BANKS; b++) { ++ for (i = 0; i < bank_irqs[b]; i++) { ++ irq = irq_create_mapping(intc.domain, ++ MAKE_HWIRQ(b, i) + NUMBER_IRQS); ++ BUG_ON(irq <= 0); ++ irq_set_chip(irq, &armctrl_chip); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ } ++ init_FIQ(FIQ_START); ++ + return 0; + } + diff --git a/target/linux/brcm2708/patches-4.1/0141-dwc_otg-Add-ARCH_BCM2835-support.patch b/target/linux/brcm2708/patches-4.1/0141-dwc_otg-Add-ARCH_BCM2835-support.patch new file mode 100644 index 0000000..795cbcf --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0141-dwc_otg-Add-ARCH_BCM2835-support.patch @@ -0,0 +1,49 @@ +From 738dc17aab1f5b18d94533b189e00c5960a0def6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 24 Jul 2015 15:50:04 +0200 +Subject: [PATCH 141/203] dwc_otg: Add ARCH_BCM2835 support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Noralf Trønnes +--- + drivers/usb/host/dwc_otg/dwc_otg_driver.c | 1 + + drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 1 - + drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 4 ++++ + 3 files changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c +@@ -723,6 +723,7 @@ static int dwc_otg_driver_probe( + + memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); + dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF; ++ dwc_otg_device->os_dep.platformdev = _dev; + + /* + * Map the DWC_otg Core memory into virtual address space. +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +@@ -36,7 +36,6 @@ + #include "dwc_otg_regs.h" + + #include +-#include + #include + + +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +@@ -445,7 +445,11 @@ static void hcd_init_fiq(void *cookie) + DWC_WARN("MPHI periph has NOT been enabled"); + #endif + // Enable FIQ interrupt from USB peripheral ++#ifdef CONFIG_ARCH_BCM2835 ++ enable_fiq(platform_get_irq(otg_dev->os_dep.platformdev, 1)); ++#else + enable_fiq(INTERRUPT_VC_USB); ++#endif + local_fiq_enable(); + } + diff --git a/target/linux/brcm2708/patches-4.1/0142-bcm2835-Use-DWC_OTG.patch b/target/linux/brcm2708/patches-4.1/0142-bcm2835-Use-DWC_OTG.patch new file mode 100644 index 0000000..80e904a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0142-bcm2835-Use-DWC_OTG.patch @@ -0,0 +1,41 @@ +From b7eae04326d84f4b51ccfee02b5fb39500656fa9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 24 Jul 2015 15:50:24 +0200 +Subject: [PATCH 142/203] bcm2835: Use DWC_OTG +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/bcm2835.dtsi | 8 +++++--- + arch/arm/configs/bcm2835_defconfig | 1 + + 2 files changed, 6 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/bcm2835.dtsi ++++ b/arch/arm/boot/dts/bcm2835.dtsi +@@ -152,9 +152,11 @@ + }; + + usb: usb@7e980000 { +- compatible = "brcm,bcm2835-usb"; +- reg = <0x7e980000 0x10000>; +- interrupts = <1 9>; ++ compatible = "brcm,bcm2708-usb"; ++ reg = <0x7e980000 0x10000>, ++ <0x7e006000 0x1000>; ++ interrupts = <2 0>, ++ <1 9>; + }; + + arm-pmu { +--- a/arch/arm/configs/bcm2835_defconfig ++++ b/arch/arm/configs/bcm2835_defconfig +@@ -869,6 +869,7 @@ CONFIG_USB_HIDDEV=y + CONFIG_USB=y + CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + CONFIG_USB_MON=m ++CONFIG_USB_DWCOTG=y + CONFIG_USB_PRINTER=m + CONFIG_USB_STORAGE=y + CONFIG_USB_STORAGE_REALTEK=m diff --git a/target/linux/brcm2708/patches-4.1/0143-Fix-RASPBERRYPI_FIRMWARE-dependents.patch b/target/linux/brcm2708/patches-4.1/0143-Fix-RASPBERRYPI_FIRMWARE-dependents.patch new file mode 100644 index 0000000..b5aa74c --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0143-Fix-RASPBERRYPI_FIRMWARE-dependents.patch @@ -0,0 +1,73 @@ +From fb25dfd5b7543d9b777239e76ea12f2b64eb2437 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 24 Jul 2015 19:33:16 +0200 +Subject: [PATCH 143/203] Fix RASPBERRYPI_FIRMWARE dependents +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +If forgot this when converting the drivers. + +Signed-off-by: Noralf Trønnes +--- + drivers/cpufreq/Kconfig.arm | 2 +- + drivers/input/touchscreen/Kconfig | 2 +- + drivers/misc/vc04_services/Kconfig | 2 +- + drivers/thermal/Kconfig | 2 +- + drivers/video/fbdev/Kconfig | 2 +- + 5 files changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -259,7 +259,7 @@ config ARM_SPEAR_CPUFREQ + This adds the CPUFreq driver support for SPEAr SOCs. + + config ARM_BCM2835_CPUFREQ +- depends on BCM2708_MBOX ++ depends on RASPBERRYPI_FIRMWARE + bool "BCM2835 Driver" + default y + help +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -585,7 +585,7 @@ config TOUCHSCREEN_EDT_FT5X06 + + config TOUCHSCREEN_RPI_FT5406 + tristate "Raspberry Pi FT5406 driver" +- depends on ARCH_BCM2708 || ARCH_BCM2709 ++ depends on RASPBERRYPI_FIRMWARE + help + Say Y here to enable the Raspberry Pi memory based FT5406 device + +--- a/drivers/misc/vc04_services/Kconfig ++++ b/drivers/misc/vc04_services/Kconfig +@@ -1,6 +1,6 @@ + config BCM2708_VCHIQ + tristate "Videocore VCHIQ" +- depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2708_MBOX ++ depends on RASPBERRYPI_FIRMWARE + default y + help + Kernel to VideoCore communication interface for the +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -239,7 +239,7 @@ config INTEL_POWERCLAMP + user interface is exposed via generic thermal framework. + + config THERMAL_BCM2835 +- depends on BCM2708_MBOX ++ depends on RASPBERRYPI_FIRMWARE + tristate "BCM2835 Thermal Driver" + help + This will enable temperature monitoring for the Broadcom BCM2835 +--- a/drivers/video/fbdev/Kconfig ++++ b/drivers/video/fbdev/Kconfig +@@ -226,7 +226,7 @@ comment "Frame buffer hardware drivers" + + config FB_BCM2708 + tristate "BCM2708 framebuffer support" +- depends on FB && ARM && BCM2708_MBOX ++ depends on FB && RASPBERRYPI_FIRMWARE + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT diff --git a/target/linux/brcm2708/patches-4.1/0144-vc_mem-Remove-unnecessary-include.patch b/target/linux/brcm2708/patches-4.1/0144-vc_mem-Remove-unnecessary-include.patch new file mode 100644 index 0000000..78a8e72 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0144-vc_mem-Remove-unnecessary-include.patch @@ -0,0 +1,23 @@ +From 6c53947855b434549697719a85be14a738a4826d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 24 Jul 2015 19:33:46 +0200 +Subject: [PATCH 144/203] vc_mem: Remove unnecessary include +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Noralf Trønnes +--- + drivers/char/broadcom/vc_mem.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/char/broadcom/vc_mem.c ++++ b/drivers/char/broadcom/vc_mem.c +@@ -22,7 +22,6 @@ + #include + #include + #include +-#include + #include + + #define DRIVER_NAME "vc-mem" diff --git a/target/linux/brcm2708/patches-4.1/0145-configs-Remove-BCM2708_MBOX.patch b/target/linux/brcm2708/patches-4.1/0145-configs-Remove-BCM2708_MBOX.patch new file mode 100644 index 0000000..e907bd4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0145-configs-Remove-BCM2708_MBOX.patch @@ -0,0 +1,45 @@ +From e04d908da0cea4af59fe4c67fd1684e60efa7c90 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 24 Jul 2015 19:34:06 +0200 +Subject: [PATCH 145/203] configs: Remove BCM2708_MBOX +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Noralf Trønnes +--- + arch/arm/configs/bcm2709_defconfig | 1 - + arch/arm/configs/bcm2835_defconfig | 1 - + arch/arm/configs/bcmrpi_defconfig | 1 - + 3 files changed, 3 deletions(-) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -1078,7 +1078,6 @@ CONFIG_FB_TFT_WATTEROTT=m + CONFIG_FB_FLEX=m + CONFIG_FB_TFT_FBTFT_DEVICE=m + CONFIG_MAILBOX=y +-CONFIG_BCM2708_MBOX=y + CONFIG_BCM2835_MBOX=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXTCON=m +--- a/arch/arm/configs/bcm2835_defconfig ++++ b/arch/arm/configs/bcm2835_defconfig +@@ -1065,7 +1065,6 @@ CONFIG_FB_TFT_WATTEROTT=m + CONFIG_FB_FLEX=m + CONFIG_FB_TFT_FBTFT_DEVICE=m + CONFIG_MAILBOX=y +-CONFIG_BCM2708_MBOX=y + CONFIG_BCM2835_MBOX=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXTCON=m +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -1071,7 +1071,6 @@ CONFIG_FB_TFT_WATTEROTT=m + CONFIG_FB_FLEX=m + CONFIG_FB_TFT_FBTFT_DEVICE=m + CONFIG_MAILBOX=y +-CONFIG_BCM2708_MBOX=y + CONFIG_BCM2835_MBOX=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXTCON=m diff --git a/target/linux/brcm2708/patches-4.1/0146-bcm2708-vcio-Remove-module.patch b/target/linux/brcm2708/patches-4.1/0146-bcm2708-vcio-Remove-module.patch new file mode 100644 index 0000000..0fc2cca --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0146-bcm2708-vcio-Remove-module.patch @@ -0,0 +1,266 @@ +From a9b8c66f63005e9d3f4cbd6591874e618492898c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 24 Jul 2015 19:34:31 +0200 +Subject: [PATCH 146/203] bcm2708-vcio: Remove module +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +All drivers have been converted to the new firmware API, so this +module is not needed anymore. + +Signed-off-by: Noralf Trønnes +--- + drivers/mailbox/Kconfig | 6 -- + drivers/mailbox/Makefile | 2 - + drivers/mailbox/bcm2708-vcio.c | 86 ----------------- + include/linux/platform_data/mailbox-bcm2708.h | 127 -------------------------- + 4 files changed, 221 deletions(-) + delete mode 100644 drivers/mailbox/bcm2708-vcio.c + delete mode 100644 include/linux/platform_data/mailbox-bcm2708.h + +--- a/drivers/mailbox/Kconfig ++++ b/drivers/mailbox/Kconfig +@@ -7,12 +7,6 @@ menuconfig MAILBOX + + if MAILBOX + +-config BCM2708_MBOX +- bool "Broadcom BCM2708 Mailbox (vcio)" +- depends on BCM2835_MBOX +- help +- Broadcom BCM2708 Mailbox (vcio) +- + config ARM_MHU + tristate "ARM MHU Mailbox" + depends on ARM_AMBA +--- a/drivers/mailbox/Makefile ++++ b/drivers/mailbox/Makefile +@@ -2,8 +2,6 @@ + + obj-$(CONFIG_MAILBOX) += mailbox.o + +-obj-$(CONFIG_BCM2708_MBOX) += bcm2708-vcio.o +- + obj-$(CONFIG_ARM_MHU) += arm_mhu.o + + obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o +--- a/drivers/mailbox/bcm2708-vcio.c ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright (C) 2010 Broadcom +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License version 2 as +- * published by the Free Software Foundation. +- * +- * This device provides a shared mechanism for writing to the mailboxes, +- * semaphores, doorbells etc. that are shared between the ARM and the +- * VideoCore processor +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#define DRIVER_NAME "bcm2708_vcio" +- +-extern int bcm_mailbox_write(unsigned chan, uint32_t data28) +-{ +- struct rpi_firmware *fw = rpi_firmware_get(NULL); +- +- if (!fw) +- return -ENODEV; +- +- return rpi_firmware_transaction(fw, chan, data28); +-} +-EXPORT_SYMBOL_GPL(bcm_mailbox_write); +- +-extern int bcm_mailbox_read(unsigned chan, uint32_t *data28) +-{ +- struct rpi_firmware *fw = rpi_firmware_get(NULL); +- +- if (!fw) +- return -ENODEV; +- +- *data28 = rpi_firmware_transaction_received(fw); +- +- return 0; +-} +-EXPORT_SYMBOL_GPL(bcm_mailbox_read); +- +-static DEFINE_MUTEX(mailbox_lock); +-extern int bcm_mailbox_property(void *data, int size) +-{ +- uint32_t success; +- dma_addr_t mem_bus; /* the memory address accessed from videocore */ +- void *mem_kern; /* the memory address accessed from driver */ +- int s = 0; +- +- mutex_lock(&mailbox_lock); +- /* allocate some memory for the messages communicating with GPU */ +- mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, +- GFP_KERNEL); +- if (mem_kern) { +- /* create the message */ +- memcpy(mem_kern, data, size); +- +- /* send the message */ +- wmb(); +- s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus); +- if (s == 0) +- s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success); +- if (s == 0) { +- /* copy the response */ +- rmb(); +- memcpy(data, mem_kern, size); +- } +- dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus); +- } else { +- s = -ENOMEM; +- } +- if (s != 0) +- pr_err(DRIVER_NAME ": %s failed (%d)\n", __func__, s); +- +- mutex_unlock(&mailbox_lock); +- return s; +-} +-EXPORT_SYMBOL_GPL(bcm_mailbox_property); +- +-MODULE_AUTHOR("Gray Girling"); +-MODULE_DESCRIPTION("ARM I/O to VideoCore processor"); +-MODULE_LICENSE("GPL"); +--- a/include/linux/platform_data/mailbox-bcm2708.h ++++ /dev/null +@@ -1,127 +0,0 @@ +-/* +- * Copyright (C) 2010 Broadcom +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +-#ifndef _PLAT_MAILBOX_BCM2708_H +-#define _PLAT_MAILBOX_BCM2708_H +- +-/* Routines to handle I/O via the VideoCore "ARM control" registers +- * (semaphores, doorbells, mailboxes) +- */ +- +-/* Constants shared with the ARM identifying separate mailbox channels */ +-#define MBOX_CHAN_POWER 0 /* for use by the power management interface */ +-#define MBOX_CHAN_FB 1 /* for use by the frame buffer */ +-#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */ +-#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */ +-#define MBOX_CHAN_COUNT 9 +- +-enum { +- VCMSG_PROCESS_REQUEST = 0x00000000 +-}; +- +-enum { +- VCMSG_REQUEST_SUCCESSFUL = 0x80000000, +- VCMSG_REQUEST_FAILED = 0x80000001 +-}; +- +-/* Mailbox property tags */ +-enum { +- VCMSG_PROPERTY_END = 0x00000000, +- VCMSG_GET_FIRMWARE_REVISION = 0x00000001, +- VCMSG_GET_BOARD_MODEL = 0x00010001, +- VCMSG_GET_BOARD_REVISION = 0x00010002, +- VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003, +- VCMSG_GET_BOARD_SERIAL = 0x00010004, +- VCMSG_GET_ARM_MEMORY = 0x00010005, +- VCMSG_GET_VC_MEMORY = 0x00010006, +- VCMSG_GET_CLOCKS = 0x00010007, +- VCMSG_GET_COMMAND_LINE = 0x00050001, +- VCMSG_GET_DMA_CHANNELS = 0x00060001, +- VCMSG_GET_POWER_STATE = 0x00020001, +- VCMSG_GET_TIMING = 0x00020002, +- VCMSG_SET_POWER_STATE = 0x00028001, +- VCMSG_GET_CLOCK_STATE = 0x00030001, +- VCMSG_SET_CLOCK_STATE = 0x00038001, +- VCMSG_GET_CLOCK_RATE = 0x00030002, +- VCMSG_SET_CLOCK_RATE = 0x00038002, +- VCMSG_GET_VOLTAGE = 0x00030003, +- VCMSG_SET_VOLTAGE = 0x00038003, +- VCMSG_GET_MAX_CLOCK = 0x00030004, +- VCMSG_GET_MAX_VOLTAGE = 0x00030005, +- VCMSG_GET_TEMPERATURE = 0x00030006, +- VCMSG_GET_MIN_CLOCK = 0x00030007, +- VCMSG_GET_MIN_VOLTAGE = 0x00030008, +- VCMSG_GET_TURBO = 0x00030009, +- VCMSG_GET_MAX_TEMPERATURE = 0x0003000a, +- VCMSG_GET_STC = 0x0003000b, +- VCMSG_SET_TURBO = 0x00038009, +- VCMSG_SET_ALLOCATE_MEM = 0x0003000c, +- VCMSG_SET_LOCK_MEM = 0x0003000d, +- VCMSG_SET_UNLOCK_MEM = 0x0003000e, +- VCMSG_SET_RELEASE_MEM = 0x0003000f, +- VCMSG_SET_EXECUTE_CODE = 0x00030010, +- VCMSG_SET_EXECUTE_QPU = 0x00030011, +- VCMSG_SET_ENABLE_QPU = 0x00030012, +- VCMSG_GET_RESOURCE_HANDLE = 0x00030014, +- VCMSG_GET_EDID_BLOCK = 0x00030020, +- VCMSG_GET_CUSTOMER_OTP = 0x00030021, +- VCMSG_SET_CUSTOMER_OTP = 0x00038021, +- VCMSG_SET_ALLOCATE_BUFFER = 0x00040001, +- VCMSG_SET_RELEASE_BUFFER = 0x00048001, +- VCMSG_SET_BLANK_SCREEN = 0x00040002, +- VCMSG_TST_BLANK_SCREEN = 0x00044002, +- VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003, +- VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003, +- VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003, +- VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004, +- VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004, +- VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004, +- VCMSG_GET_DEPTH = 0x00040005, +- VCMSG_TST_DEPTH = 0x00044005, +- VCMSG_SET_DEPTH = 0x00048005, +- VCMSG_GET_PIXEL_ORDER = 0x00040006, +- VCMSG_TST_PIXEL_ORDER = 0x00044006, +- VCMSG_SET_PIXEL_ORDER = 0x00048006, +- VCMSG_GET_ALPHA_MODE = 0x00040007, +- VCMSG_TST_ALPHA_MODE = 0x00044007, +- VCMSG_SET_ALPHA_MODE = 0x00048007, +- VCMSG_GET_PITCH = 0x00040008, +- VCMSG_TST_PITCH = 0x00044008, +- VCMSG_SET_PITCH = 0x00048008, +- VCMSG_GET_VIRTUAL_OFFSET = 0x00040009, +- VCMSG_TST_VIRTUAL_OFFSET = 0x00044009, +- VCMSG_SET_VIRTUAL_OFFSET = 0x00048009, +- VCMSG_GET_OVERSCAN = 0x0004000a, +- VCMSG_TST_OVERSCAN = 0x0004400a, +- VCMSG_SET_OVERSCAN = 0x0004800a, +- VCMSG_GET_PALETTE = 0x0004000b, +- VCMSG_TST_PALETTE = 0x0004400b, +- VCMSG_SET_PALETTE = 0x0004800b, +- VCMSG_GET_LAYER = 0x0004000c, +- VCMSG_TST_LAYER = 0x0004400c, +- VCMSG_SET_LAYER = 0x0004800c, +- VCMSG_GET_TRANSFORM = 0x0004000d, +- VCMSG_TST_TRANSFORM = 0x0004400d, +- VCMSG_SET_TRANSFORM = 0x0004800d, +- VCMSG_TST_VSYNC = 0x0004400e, +- VCMSG_SET_VSYNC = 0x0004800e, +- VCMSG_GET_TOUCHBUF = 0x0004000f, +- VCMSG_SET_CURSOR_INFO = 0x00008010, +- VCMSG_SET_CURSOR_STATE = 0x00008011, +-}; +- +-int bcm_mailbox_read(unsigned chan, uint32_t *data28); +-int bcm_mailbox_write(unsigned chan, uint32_t data28); +-int bcm_mailbox_property(void *data, int size); +- +-#endif diff --git a/target/linux/brcm2708/patches-4.1/0147-Revert-firmware-bcm2835-Support-legacy-mailbox-API.patch b/target/linux/brcm2708/patches-4.1/0147-Revert-firmware-bcm2835-Support-legacy-mailbox-API.patch new file mode 100644 index 0000000..b44c6d6 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0147-Revert-firmware-bcm2835-Support-legacy-mailbox-API.patch @@ -0,0 +1,89 @@ +From 8892c1d6ce14da3baac8512974e20f129bb9a34e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Fri, 24 Jul 2015 19:34:55 +0200 +Subject: [PATCH 147/203] Revert "firmware: bcm2835: Support legacy mailbox + API" +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This reverts commit 40aa3c4f0c430cd5c574498f4d1d5e9f0bc1cf11. + +The legacy mailbox API has been removed so this is not needed. + +Signed-off-by: Noralf Trønnes +--- + drivers/firmware/raspberrypi.c | 15 ++------------- + include/soc/bcm2835/raspberrypi-firmware.h | 2 -- + 2 files changed, 2 insertions(+), 15 deletions(-) + +--- a/drivers/firmware/raspberrypi.c ++++ b/drivers/firmware/raspberrypi.c +@@ -19,7 +19,6 @@ + #define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf)) + #define MBOX_CHAN(msg) ((msg) & 0xf) + #define MBOX_DATA28(msg) ((msg) & ~0xf) +-#define MBOX_CHAN_VCHIQ 3 + #define MBOX_CHAN_PROPERTY 8 + + struct rpi_firmware { +@@ -27,7 +26,6 @@ struct rpi_firmware { + struct mbox_chan *chan; /* The property channel. */ + struct completion c; + u32 enabled; +- u32 received; + }; + + static struct platform_device *g_pdev; +@@ -37,7 +35,6 @@ static DEFINE_MUTEX(transaction_lock); + static void response_callback(struct mbox_client *cl, void *msg) + { + struct rpi_firmware *fw = container_of(cl, struct rpi_firmware, cl); +- fw->received = *(u32 *)msg; + complete(&fw->c); + } + +@@ -45,7 +42,7 @@ static void response_callback(struct mbo + * Sends a request to the firmware through the BCM2835 mailbox driver, + * and synchronously waits for the reply. + */ +-int ++static int + rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data) + { + u32 message = MBOX_MSG(chan, data); +@@ -57,8 +54,7 @@ rpi_firmware_transaction(struct rpi_firm + reinit_completion(&fw->c); + ret = mbox_send_message(fw->chan, &message); + if (ret >= 0) { +- if (chan != MBOX_CHAN_VCHIQ) +- wait_for_completion(&fw->c); ++ wait_for_completion(&fw->c); + ret = 0; + } else { + dev_err(fw->cl.dev, "mbox_send_message returned %d\n", ret); +@@ -67,13 +63,6 @@ rpi_firmware_transaction(struct rpi_firm + + return ret; + } +-EXPORT_SYMBOL(rpi_firmware_transaction); +- +-u32 rpi_firmware_transaction_received(struct rpi_firmware *fw) +-{ +- return MBOX_DATA28(fw->received); +-} +-EXPORT_SYMBOL(rpi_firmware_transaction_received); + + /** + * rpi_firmware_property_list - Submit firmware property list +--- a/include/soc/bcm2835/raspberrypi-firmware.h ++++ b/include/soc/bcm2835/raspberrypi-firmware.h +@@ -116,8 +116,6 @@ enum rpi_firmware_property_tag { + RPI_FIRMWARE_GET_DMA_CHANNELS = 0x00060001, + }; + +-int rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data); +-u32 rpi_firmware_transaction_received(struct rpi_firmware *fw); + int rpi_firmware_property(struct rpi_firmware *fw, + u32 tag, void *data, size_t len); + int rpi_firmware_property_list(struct rpi_firmware *fw, diff --git a/target/linux/brcm2708/patches-4.1/0148-pinctrl-bcm2835-Clear-the-event-latch-register-when-.patch b/target/linux/brcm2708/patches-4.1/0148-pinctrl-bcm2835-Clear-the-event-latch-register-when-.patch new file mode 100644 index 0000000..d912ba9 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0148-pinctrl-bcm2835-Clear-the-event-latch-register-when-.patch @@ -0,0 +1,37 @@ +From 9dabf31b13de7de5742e3f13c0b38fff460b552b Mon Sep 17 00:00:00 2001 +From: Jonathan Bell +Date: Tue, 30 Jun 2015 12:35:39 +0100 +Subject: [PATCH 148/203] pinctrl: bcm2835: Clear the event latch register when + disabling interrupts + +It's possible to hit a race condition if interrupts are generated on a GPIO +pin when the IRQ line in question is being disabled. + +If the interrupt is freed, bcm2835_gpio_irq_disable() is called which +disables the event generation sources (edge, level). If an event occurred +between the last disabling of hard IRQs and the write to the event +source registers, a bit would be set in the GPIO event detect register +(GPEDSn) which goes unacknowledged by bcm2835_gpio_irq_handler() +so Linux complains loudly. + +There is no per-GPIO mask register, so when disabling GPIO interrupts +write 1 to the relevant bit in GPEDSn to clear out any stale events. + +Signed-off-by: Jonathan Bell +Acked-by: Stephen Warren +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c ++++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c +@@ -503,6 +503,8 @@ static void bcm2835_gpio_irq_disable(str + + spin_lock_irqsave(&pc->irq_lock[bank], flags); + bcm2835_gpio_irq_config(pc, gpio, false); ++ /* Clear events that were latched prior to clearing event sources */ ++ bcm2835_gpio_set_bit(pc, GPEDS0, gpio); + clear_bit(offset, &pc->enabled_irq_map[bank]); + spin_unlock_irqrestore(&pc->irq_lock[bank], flags); + } diff --git a/target/linux/brcm2708/patches-4.1/0149-dwc_otg-fiq_fsm-Make-high-speed-isochronous-strided-.patch b/target/linux/brcm2708/patches-4.1/0149-dwc_otg-fiq_fsm-Make-high-speed-isochronous-strided-.patch new file mode 100644 index 0000000..db72a9f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0149-dwc_otg-fiq_fsm-Make-high-speed-isochronous-strided-.patch @@ -0,0 +1,134 @@ +From c069d755e30358e19c9c5f93f0e3748827a91c9d Mon Sep 17 00:00:00 2001 +From: P33M +Date: Tue, 4 Aug 2015 01:15:20 +0100 +Subject: [PATCH 149/203] dwc_otg: fiq_fsm: Make high-speed isochronous strided + transfers work properly + +Certain low-bandwidth high-speed USB devices (specialist audio devices, +compressed-frame webcams) have packet intervals > 1 microframe. + +Stride these transfers in the FIQ by using the start-of-frame interrupt +to restart the channel at the right time. +--- + drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 17 +++++++++++++---- + drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 5 ++++- + drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 7 ++++++- + drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 6 ++++-- + 4 files changed, 27 insertions(+), 8 deletions(-) + +--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c +@@ -615,8 +615,11 @@ static int notrace noinline fiq_fsm_do_s + break; + + case FIQ_HS_ISOC_SLEEPING: +- state->channel[n].fsm = FIQ_HS_ISOC_TURBO; +- fiq_fsm_restart_channel(state, n, 0); ++ /* Is it time to wake this channel yet? */ ++ if (--state->channel[n].uframe_sleeps == 0) { ++ state->channel[n].fsm = FIQ_HS_ISOC_TURBO; ++ fiq_fsm_restart_channel(state, n, 0); ++ } + break; + + case FIQ_PER_SSPLIT_QUEUED: +@@ -624,7 +627,7 @@ static int notrace noinline fiq_fsm_do_s + break; + if(!fiq_fsm_tt_in_use(state, num_channels, n)) { + if (!fiq_fsm_too_late(state, n)) { +- fiq_print(FIQDBG_INT, st, "SOF GO %01d", n); ++ fiq_print(FIQDBG_INT, state, "SOF GO %01d", n); + fiq_fsm_restart_channel(state, n, 0); + state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; + } else { +@@ -1069,8 +1072,14 @@ static int notrace noinline fiq_fsm_do_h + if (fiq_fsm_update_hs_isoc(state, n, hcint)) { + /* more transactions to come */ + handled = 1; +- restart = 1; + fiq_print(FIQDBG_INT, state, "HSISO M "); ++ /* For strided transfers, put ourselves to sleep */ ++ if (st->hs_isoc_info.stride > 1) { ++ st->uframe_sleeps = st->hs_isoc_info.stride - 1; ++ st->fsm = FIQ_HS_ISOC_SLEEPING; ++ } else { ++ restart = 1; ++ } + } else { + st->fsm = FIQ_HS_ISOC_DONE; + fiq_print(FIQDBG_INT, state, "HSISO F "); +--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h ++++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h +@@ -260,12 +260,13 @@ struct fiq_dma_blob { + * @iso_frame: Pointer to the array of OTG URB iso_frame_descs. + * @nrframes: Total length of iso_frame_desc array + * @index: Current index (FIQ-maintained) +- * ++ * @stride: Interval in uframes between HS isoc transactions + */ + struct fiq_hs_isoc_info { + struct dwc_otg_hcd_iso_packet_desc *iso_desc; + unsigned int nrframes; + unsigned int index; ++ unsigned int stride; + }; + + /** +@@ -296,6 +297,8 @@ struct fiq_channel_state { + /* Hardware bug workaround: sometimes channel halt interrupts are + * delayed until the next SOF. Keep track of when we expected to get interrupted. */ + unsigned int expected_uframe; ++ /* number of uframes remaining (for interval > 1 HS isoc transfers) before next transfer */ ++ unsigned int uframe_sleeps; + /* in/out for communicating number of dma buffers used, or number of ISOC to do */ + unsigned int nrpackets; + struct fiq_dma_info dma_info; +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +@@ -1678,6 +1678,9 @@ int fiq_fsm_queue_isoc_transaction(dwc_o + } + } + ++ st->hs_isoc_info.stride = qh->interval; ++ st->uframe_sleeps = 0; ++ + fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num); + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32); + fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); +@@ -1692,9 +1695,11 @@ int fiq_fsm_queue_isoc_transaction(dwc_o + DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); + if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { + /* Prevent queueing near EOF1. Bad things happen if a periodic +- * split transaction is queued very close to EOF. ++ * split transaction is queued very close to EOF. SOF interrupt handler ++ * will wake this channel at the next interrupt. + */ + st->fsm = FIQ_HS_ISOC_SLEEPING; ++ st->uframe_sleeps = 1; + } else { + st->fsm = FIQ_HS_ISOC_TURBO; + st->hcchar_copy.b.chen = 1; +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +@@ -2297,10 +2297,10 @@ void dwc_otg_fiq_unmangle_isoc(dwc_otg_h + dwc_urb->error_count++; + } + } ++ qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval * (nr_frames - 1)); ++ + //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n", + // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count); +- hcd->fops->complete(hcd, dwc_urb->priv, dwc_urb, 0); +- release_channel(hcd, qh->channel, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); + } + + /** +@@ -2543,6 +2543,8 @@ void dwc_otg_hcd_handle_hc_fsm(dwc_otg_h + * fail. + */ + dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num); ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); + break; + + case FIQ_PER_SPLIT_LS_ABORTED: diff --git a/target/linux/brcm2708/patches-4.1/0150-added-basic-docker-support.patch b/target/linux/brcm2708/patches-4.1/0150-added-basic-docker-support.patch new file mode 100644 index 0000000..b4b5128 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0150-added-basic-docker-support.patch @@ -0,0 +1,62 @@ +From cb0ceb651b94c8d6a01677f9b277c0d7e8862014 Mon Sep 17 00:00:00 2001 +From: Uli Middelberg +Date: Wed, 17 Jun 2015 10:36:56 +0200 +Subject: [PATCH 150/203] added basic docker support + +--- + arch/arm/configs/bcm2709_defconfig | 3 +++ + arch/arm/configs/bcmrpi_defconfig | 3 +++ + 2 files changed, 6 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -17,6 +17,7 @@ CONFIG_IKCONFIG=m + CONFIG_IKCONFIG_PROC=y + CONFIG_CGROUP_FREEZER=y + CONFIG_CGROUP_DEVICE=y ++CONFIG_CPUSETS=y + CONFIG_CGROUP_CPUACCT=y + CONFIG_MEMCG=y + CONFIG_BLK_CGROUP=y +@@ -418,6 +419,7 @@ CONFIG_MD_RAID0=m + CONFIG_BLK_DEV_DM=m + CONFIG_DM_CRYPT=m + CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_THIN_PROVISIONING=m + CONFIG_DM_MIRROR=m + CONFIG_DM_LOG_USERSPACE=m + CONFIG_DM_RAID=m +@@ -1115,6 +1117,7 @@ CONFIG_QFMT_V2=m + CONFIG_AUTOFS4_FS=y + CONFIG_FUSE_FS=m + CONFIG_CUSE=m ++CONFIG_OVERLAY_FS=m + CONFIG_FSCACHE=y + CONFIG_FSCACHE_STATS=y + CONFIG_FSCACHE_HISTOGRAM=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -16,6 +16,7 @@ CONFIG_IKCONFIG=m + CONFIG_IKCONFIG_PROC=y + CONFIG_CGROUP_FREEZER=y + CONFIG_CGROUP_DEVICE=y ++CONFIG_CPUSETS=y + CONFIG_CGROUP_CPUACCT=y + CONFIG_MEMCG=y + CONFIG_BLK_CGROUP=y +@@ -411,6 +412,7 @@ CONFIG_MD_RAID0=m + CONFIG_BLK_DEV_DM=m + CONFIG_DM_CRYPT=m + CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_THIN_PROVISIONING=m + CONFIG_DM_MIRROR=m + CONFIG_DM_LOG_USERSPACE=m + CONFIG_DM_RAID=m +@@ -1108,6 +1110,7 @@ CONFIG_QFMT_V2=m + CONFIG_AUTOFS4_FS=y + CONFIG_FUSE_FS=m + CONFIG_CUSE=m ++CONFIG_OVERLAY_FS=m + CONFIG_FSCACHE=y + CONFIG_FSCACHE_STATS=y + CONFIG_FSCACHE_HISTOGRAM=y diff --git a/target/linux/brcm2708/patches-4.1/0151-bcm2835-camera-planar-packed-stride-length.patch b/target/linux/brcm2708/patches-4.1/0151-bcm2835-camera-planar-packed-stride-length.patch new file mode 100644 index 0000000..2681c34 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0151-bcm2835-camera-planar-packed-stride-length.patch @@ -0,0 +1,170 @@ +From 4e2638fe451b09fc2ba0a98b433f06b5a8986093 Mon Sep 17 00:00:00 2001 +From: Garrett +Date: Thu, 2 Jul 2015 19:32:04 -0500 +Subject: [PATCH 151/203] bcm2835 camera planar/packed stride length + +Added a field to the mmal_fmt struct used to compute the bytes per line +when using a particular format. This results in the correct stride being +calculated even when the format is planar. + +Signed-off-by: Garrett Wilson +--- + drivers/media/platform/bcm2835/bcm2835-camera.c | 26 +++++++++++++++++++------ + drivers/media/platform/bcm2835/mmal-common.h | 1 + + 2 files changed, 21 insertions(+), 6 deletions(-) + +--- a/drivers/media/platform/bcm2835/bcm2835-camera.c ++++ b/drivers/media/platform/bcm2835/bcm2835-camera.c +@@ -88,12 +88,13 @@ static const struct v4l2_fract + /* video formats */ + static struct mmal_fmt formats[] = { + { +- .name = "4:2:0, packed YUV", ++ .name = "4:2:0, planar, YUV", + .fourcc = V4L2_PIX_FMT_YUV420, + .flags = 0, + .mmal = MMAL_ENCODING_I420, + .depth = 12, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 1, + }, + { + .name = "4:2:2, packed, YUYV", +@@ -102,6 +103,7 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_YUYV, + .depth = 16, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 2, + }, + { + .name = "RGB24 (LE)", +@@ -110,6 +112,7 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_BGR24, + .depth = 24, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 3, + }, + { + .name = "JPEG", +@@ -118,6 +121,7 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_JPEG, + .depth = 8, + .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE, ++ .ybbp = 0, + }, + { + .name = "H264", +@@ -126,6 +130,7 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_H264, + .depth = 8, + .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE, ++ .ybbp = 0, + }, + { + .name = "MJPEG", +@@ -134,6 +139,7 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_MJPEG, + .depth = 8, + .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE, ++ .ybbp = 0, + }, + { + .name = "4:2:2, packed, YVYU", +@@ -142,6 +148,7 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_YVYU, + .depth = 16, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 2, + }, + { + .name = "4:2:2, packed, VYUY", +@@ -150,6 +157,7 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_VYUY, + .depth = 16, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 2, + }, + { + .name = "4:2:2, packed, UYVY", +@@ -158,14 +166,16 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_UYVY, + .depth = 16, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 2, + }, + { +- .name = "4:2:0, packed, NV12", ++ .name = "4:2:0, planar, NV12", + .fourcc = V4L2_PIX_FMT_NV12, + .flags = 0, + .mmal = MMAL_ENCODING_NV12, + .depth = 12, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 1, + }, + { + .name = "RGB24 (BE)", +@@ -174,22 +184,25 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_RGB24, + .depth = 24, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 3, + }, + { +- .name = "4:2:0, packed YVU", ++ .name = "4:2:0, planar, YVU", + .fourcc = V4L2_PIX_FMT_YVU420, + .flags = 0, + .mmal = MMAL_ENCODING_YV12, + .depth = 12, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 1, + }, + { +- .name = "4:2:0, packed, NV21", ++ .name = "4:2:0, planar, NV21", + .fourcc = V4L2_PIX_FMT_NV21, + .flags = 0, + .mmal = MMAL_ENCODING_NV21, + .depth = 12, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 1, + }, + { + .name = "RGB32 (BE)", +@@ -198,6 +211,7 @@ static struct mmal_fmt formats[] = { + .mmal = MMAL_ENCODING_BGRA, + .depth = 32, + .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 4, + }, + }; + +@@ -771,7 +785,7 @@ static int vidioc_g_fbuf(struct file *fi + a->fmt.width = preview_port->es.video.width; + a->fmt.height = preview_port->es.video.height; + a->fmt.pixelformat = V4L2_PIX_FMT_YUV420; +- a->fmt.bytesperline = (preview_port->es.video.width * 3)>>1; ++ a->fmt.bytesperline = preview_port->es.video.width; + a->fmt.sizeimage = (preview_port->es.video.width * + preview_port->es.video.height * 3)>>1; + a->fmt.colorspace = V4L2_COLORSPACE_SMPTE170M; +@@ -894,7 +908,7 @@ static int vidioc_try_fmt_vid_cap(struct + + v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 1, + &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 1, 0); +- f->fmt.pix.bytesperline = (f->fmt.pix.width * mfmt->depth)>>3; ++ f->fmt.pix.bytesperline = f->fmt.pix.width * mfmt->ybbp; + + /* Image buffer has to be padded to allow for alignment, even though + * we then remove that padding before delivering the buffer. +--- a/drivers/media/platform/bcm2835/mmal-common.h ++++ b/drivers/media/platform/bcm2835/mmal-common.h +@@ -30,6 +30,7 @@ struct mmal_fmt { + u32 mmal; + int depth; + u32 mmal_component; /* MMAL component index to be used to encode */ ++ u32 ybbp; /* depth of first Y plane for planar formats */ + }; + + /* buffer for one video frame */ diff --git a/target/linux/brcm2708/patches-4.1/0154-BCM270X_DT-Add-pwm-and-pwm-2chan-overlays.patch b/target/linux/brcm2708/patches-4.1/0154-BCM270X_DT-Add-pwm-and-pwm-2chan-overlays.patch new file mode 100644 index 0000000..eec990a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0154-BCM270X_DT-Add-pwm-and-pwm-2chan-overlays.patch @@ -0,0 +1,250 @@ +From 37e5a9206165377033c020ca15caa23b930c6e73 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 17 Aug 2015 10:49:44 +0100 +Subject: [PATCH 154/203] BCM270X_DT: Add pwm and pwm-2chan overlays + +From the README entries: + Legal pin,function combinations for each channel: + PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) + PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) + N.B.: + 1) Pin 18 is the only one available on all platforms, and + it is the one used by the I2S audio interface. + Pins 12 and 13 might be better choices on an A+, B+ or Pi2. + 2) The onboard analogue audio output uses both PWM channels. + 3) So be careful mixing audio and PWM. + 4) Currently the clock must have been enabled and configured + by other means. + +See: https://github.com/raspberrypi/linux/issues/756 +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 16 +++++++++ + arch/arm/boot/dts/overlays/Makefile | 2 ++ + arch/arm/boot/dts/overlays/README | 41 +++++++++++++++++++++ + arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts | 46 ++++++++++++++++++++++++ + arch/arm/boot/dts/overlays/pwm-overlay.dts | 42 ++++++++++++++++++++++ + arch/arm/configs/bcm2709_defconfig | 1 + + arch/arm/configs/bcmrpi_defconfig | 1 + + drivers/pwm/Kconfig | 2 +- + 8 files changed, 150 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/pwm-overlay.dts + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -154,6 +154,14 @@ + status = "disabled"; + }; + ++ pwm: pwm@7e20c000 { ++ compatible = "brcm,bcm2835-pwm"; ++ reg = <0x7e20c000 0x28>; ++ clocks = <&clk_pwm>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ + uart1: uart@7e215040 { + compatible = "brcm,bcm2835-aux-uart", "ns16550"; + reg = <0x7e215040 0x40>; +@@ -279,6 +287,14 @@ + clock-output-names = "apb_pclk"; + clock-frequency = <126000000>; + }; ++ ++ clk_pwm: clock@5 { ++ compatible = "fixed-clock"; ++ reg = <3>; ++ #clock-cells = <0>; ++ clock-output-names = "pwm"; ++ clock-frequency = <100000000>; ++ }; + }; + + __overrides__ { +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -35,6 +35,8 @@ dtb-$(RPI_DT_OVERLAYS) += mz61581-overla + dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += pitft28-resistive-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pwm-2chan-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -410,6 +410,47 @@ Load: dtoverlay=pps-gpio,= + Params: gpiopin Input GPIO (default "18") + + ++Name: pwm ++Info: Configures a single PWM channel ++ Legal pin,function combinations for each channel: ++ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) ++ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) ++ N.B.: ++ 1) Pin 18 is the only one available on all platforms, and ++ it is the one used by the I2S audio interface. ++ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. ++ 2) The onboard analogue audio output uses both PWM channels. ++ 3) So be careful mixing audio and PWM. ++ 4) Currently the clock must have been enabled and configured ++ by other means. ++Load: dtoverlay=pwm-2chan,= ++Load: dtoverlay=pwm,= ++Params: pin Output pin (default 18) - see table ++ func Pin function (default 2 = Alt5) - see above ++ clock PWM clock frequency (informational) ++ ++ ++Name: pwm-2chan ++Info: Configures both PWM channels ++ Legal pin,function combinations for each channel: ++ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) ++ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) ++ N.B.: ++ 1) Pin 18 is the only one available on all platforms, and ++ it is the one used by the I2S audio interface. ++ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. ++ 2) The onboard analogue audio output uses both PWM channels. ++ 3) So be careful mixing audio and PWM. ++ 4) Currently the clock must have been enabled and configured ++ by other means. ++Load: dtoverlay=pwm-2chan,= ++Params: pin Output pin (default 18) - see table ++ pin2 Output pin for other channel (default 19) ++ func Pin function (default 2 = Alt5) - see above ++ func2 Function for pin2 (default 2 = Alt5) ++ clock PWM clock frequency (informational) ++ ++ + Name: rpi-dac + Info: Configures the RPi DAC audio card + Load: dtoverlay=rpi-dac +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts +@@ -0,0 +1,46 @@ ++/dts-v1/; ++/plugin/; ++ ++/* ++This is the 2-channel overlay - only use it if you need both channels. ++ ++Legal pin,function combinations for each channel: ++ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) ++ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) ++ ++N.B.: ++ 1) Pin 18 is the only one available on all platforms, and ++ it is the one used by the I2S audio interface. ++ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. ++ 2) The onboard analogue audio output uses both PWM channels. ++ 3) So be careful mixing audio and PWM. ++*/ ++ ++/ { ++ fragment@0 { ++ target = <&gpio>; ++ __overlay__ { ++ pwm_pins: pwm_pins { ++ brcm,pins = <18 19>; ++ brcm,function = <2 2>; /* Alt5 */ ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ pin = <&pwm_pins>,"brcm,pins:0"; ++ pin2 = <&pwm_pins>,"brcm,pins:4"; ++ func = <&pwm_pins>,"brcm,function:0"; ++ func2 = <&pwm_pins>,"brcm,function:4"; ++ clock = <&clk_pwm>,"clock-frequency:0"; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pwm-overlay.dts +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/* ++Legal pin,function combinations for each channel: ++ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) ++ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) ++ ++N.B.: ++ 1) Pin 18 is the only one available on all platforms, and ++ it is the one used by the I2S audio interface. ++ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. ++ 2) The onboard analogue audio output uses both PWM channels. ++ 3) So be careful mixing audio and PWM. ++*/ ++ ++/ { ++ fragment@0 { ++ target = <&gpio>; ++ __overlay__ { ++ pwm_pins: pwm_pins { ++ brcm,pins = <18>; ++ brcm,function = <2>; /* Alt5 */ ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ pin = <&pwm_pins>,"brcm,pins:0"; ++ func = <&pwm_pins>,"brcm,function:0"; ++ clock = <&clk_pwm>,"clock-frequency:0"; ++ }; ++}; +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -1089,6 +1089,7 @@ CONFIG_IIO_BUFFER=y + CONFIG_IIO_BUFFER_CB=y + CONFIG_IIO_KFIFO_BUF=m + CONFIG_DHT11=m ++CONFIG_PWM_BCM2835=m + CONFIG_RASPBERRYPI_FIRMWARE=y + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -1082,6 +1082,7 @@ CONFIG_IIO_BUFFER=y + CONFIG_IIO_BUFFER_CB=y + CONFIG_IIO_KFIFO_BUF=m + CONFIG_DHT11=m ++CONFIG_PWM_BCM2835=m + CONFIG_RASPBERRYPI_FIRMWARE=y + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -85,7 +85,7 @@ config PWM_BCM_KONA + + config PWM_BCM2835 + tristate "BCM2835 PWM support" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + help + PWM framework driver for BCM2835 controller (Raspberry Pi) + diff --git a/target/linux/brcm2708/patches-4.1/0155-spi-bcm2835-fallback-to-interrupt-for-polling-timeou.patch b/target/linux/brcm2708/patches-4.1/0155-spi-bcm2835-fallback-to-interrupt-for-polling-timeou.patch new file mode 100644 index 0000000..766923e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0155-spi-bcm2835-fallback-to-interrupt-for-polling-timeou.patch @@ -0,0 +1,136 @@ +From 0e646de6b27ee8b6631e5cebf8beffeccad8de63 Mon Sep 17 00:00:00 2001 +From: Martin Sperl +Date: Wed, 22 Apr 2015 07:33:03 +0000 +Subject: [PATCH 155/203] spi: bcm2835: fallback to interrupt for polling + timeouts exceeding 2 jiffies + +The polling mode of the driver is designed for transfers that run +less than 30us - it will only execute under those circumstances. +So it should run comfortably without getting interrupted by the +scheduler. + +But there are situations where the raspberry pi is so overloaded +that it can take up to 80 jiffies until the polling thread gets +rescheduled - this has been observed especially under heavy +IO situations. + +In such a situation we now fall back to the interrupt handler and +log the situation at debug level. + +Signed-off-by: Martin Sperl +Signed-off-by: Mark Brown +(cherry picked from commit a750b124cfd27bae1a12df22318db5a2083dfb12) +--- + drivers/spi/spi-bcm2835.c | 87 +++++++++++++++++++++++++++-------------------- + 1 file changed, 50 insertions(+), 37 deletions(-) + +--- a/drivers/spi/spi-bcm2835.c ++++ b/drivers/spi/spi-bcm2835.c +@@ -69,7 +69,7 @@ + #define BCM2835_SPI_CS_CS_01 0x00000001 + + #define BCM2835_SPI_POLLING_LIMIT_US 30 +-#define BCM2835_SPI_TIMEOUT_MS 30000 ++#define BCM2835_SPI_POLLING_JIFFIES 2 + #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ + | SPI_NO_CS | SPI_3WIRE) + +@@ -157,42 +157,6 @@ static irqreturn_t bcm2835_spi_interrupt + return IRQ_HANDLED; + } + +-static int bcm2835_spi_transfer_one_poll(struct spi_master *master, +- struct spi_device *spi, +- struct spi_transfer *tfr, +- u32 cs, +- unsigned long xfer_time_us) +-{ +- struct bcm2835_spi *bs = spi_master_get_devdata(master); +- /* set timeout to 1 second of maximum polling */ +- unsigned long timeout = jiffies + HZ; +- +- /* enable HW block without interrupts */ +- bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); +- +- /* loop until finished the transfer */ +- while (bs->rx_len) { +- /* read from fifo as much as possible */ +- bcm2835_rd_fifo(bs); +- /* fill in tx fifo as much as possible */ +- bcm2835_wr_fifo(bs); +- /* if we still expect some data after the read, +- * check for a possible timeout +- */ +- if (bs->rx_len && time_after(jiffies, timeout)) { +- /* Transfer complete - reset SPI HW */ +- bcm2835_spi_reset_hw(master); +- /* and return timeout */ +- return -ETIMEDOUT; +- } +- } +- +- /* Transfer complete - reset SPI HW */ +- bcm2835_spi_reset_hw(master); +- /* and return without waiting for completion */ +- return 0; +-} +- + static int bcm2835_spi_transfer_one_irq(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *tfr, +@@ -229,6 +193,55 @@ static int bcm2835_spi_transfer_one_irq( + return 1; + } + ++static int bcm2835_spi_transfer_one_poll(struct spi_master *master, ++ struct spi_device *spi, ++ struct spi_transfer *tfr, ++ u32 cs, ++ unsigned long xfer_time_us) ++{ ++ struct bcm2835_spi *bs = spi_master_get_devdata(master); ++ unsigned long timeout; ++ ++ /* enable HW block without interrupts */ ++ bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); ++ ++ /* fill in the fifo before timeout calculations ++ * if we are interrupted here, then the data is ++ * getting transferred by the HW while we are interrupted ++ */ ++ bcm2835_wr_fifo(bs); ++ ++ /* set the timeout */ ++ timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES; ++ ++ /* loop until finished the transfer */ ++ while (bs->rx_len) { ++ /* fill in tx fifo with remaining data */ ++ bcm2835_wr_fifo(bs); ++ ++ /* read from fifo as much as possible */ ++ bcm2835_rd_fifo(bs); ++ ++ /* if there is still data pending to read ++ * then check the timeout ++ */ ++ if (bs->rx_len && time_after(jiffies, timeout)) { ++ dev_dbg_ratelimited(&spi->dev, ++ "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", ++ jiffies - timeout, ++ bs->tx_len, bs->rx_len); ++ /* fall back to interrupt mode */ ++ return bcm2835_spi_transfer_one_irq(master, spi, ++ tfr, cs); ++ } ++ } ++ ++ /* Transfer complete - reset SPI HW */ ++ bcm2835_spi_reset_hw(master); ++ /* and return without waiting for completion */ ++ return 0; ++} ++ + static int bcm2835_spi_transfer_one(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *tfr) diff --git a/target/linux/brcm2708/patches-4.1/0156-spi-bcm2835-enable-dma-modes-for-transfers-meeting-c.patch b/target/linux/brcm2708/patches-4.1/0156-spi-bcm2835-enable-dma-modes-for-transfers-meeting-c.patch new file mode 100644 index 0000000..bae03ef --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0156-spi-bcm2835-enable-dma-modes-for-transfers-meeting-c.patch @@ -0,0 +1,423 @@ +From 7f4da26c19a10eea74419d92205886516c7f55cb Mon Sep 17 00:00:00 2001 +From: Martin Sperl +Date: Sun, 10 May 2015 20:47:28 +0000 +Subject: [PATCH 156/203] spi: bcm2835: enable dma modes for transfers meeting + certain conditions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Conditions per spi_transfer are: +* transfer.len >= 96 bytes (to avoid mapping overhead costs) +* transfer.len < 65536 bytes (limitaion by spi-hw block - could get extended) +* an individual scatter/gather transfer length must be a multiple of 4 + for anything but the last transfer - spi-hw block limit. + (some shortcut has been taken in can_dma to avoid unnecessary mapping of + pages which, for which there is a chance that there is a split with a + transfer length not a multiple of 4) + +If it becomes a necessity these restrictions can get removed by additional +code. + +Note that this patch requires a patch to dma-bcm2835.c by Noralf to +enable scatter-gather mode inside the dmaengine, which has not been +merged yet. + +That is why no patch to arch/arm/boot/dts/bcm2835.dtsi is included - the +code works as before without dma when tx/rx are not set, but it writes +a message warning about dma not used: +spi-bcm2835 20204000.spi: no tx-dma configuration found - not using dma mode + +To enable dma-mode add the following lines to the device-tree: + dmas = <&dma 6>, <&dma 7>; + dma-names = "tx", "rx"; + +Tested-by: Noralf Trønnes (private communication) +Signed-off-by: Martin Sperl +Signed-off-by: Mark Brown +(cherry picked from commit 3ecd37edaa2a6ba3246e2c35714be9316b1087fe) +--- + drivers/spi/spi-bcm2835.c | 303 +++++++++++++++++++++++++++++++++++++++++++++- + 1 file changed, 301 insertions(+), 2 deletions(-) + +--- a/drivers/spi/spi-bcm2835.c ++++ b/drivers/spi/spi-bcm2835.c +@@ -23,15 +23,18 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include + #include + #include + #include +-#include +-#include ++#include + #include ++#include ++#include + #include + + /* SPI register offsets */ +@@ -70,6 +73,7 @@ + + #define BCM2835_SPI_POLLING_LIMIT_US 30 + #define BCM2835_SPI_POLLING_JIFFIES 2 ++#define BCM2835_SPI_DMA_MIN_LENGTH 96 + #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ + | SPI_NO_CS | SPI_3WIRE) + +@@ -83,6 +87,7 @@ struct bcm2835_spi { + u8 *rx_buf; + int tx_len; + int rx_len; ++ bool dma_pending; + }; + + static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) +@@ -128,12 +133,15 @@ static void bcm2835_spi_reset_hw(struct + /* Disable SPI interrupts and transfer */ + cs &= ~(BCM2835_SPI_CS_INTR | + BCM2835_SPI_CS_INTD | ++ BCM2835_SPI_CS_DMAEN | + BCM2835_SPI_CS_TA); + /* and reset RX/TX FIFOS */ + cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; + + /* and reset the SPI_HW */ + bcm2835_wr(bs, BCM2835_SPI_CS, cs); ++ /* as well as DLEN */ ++ bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); + } + + static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) +@@ -193,6 +201,279 @@ static int bcm2835_spi_transfer_one_irq( + return 1; + } + ++/* ++ * DMA support ++ * ++ * this implementation has currently a few issues in so far as it does ++ * not work arrount limitations of the HW. ++ * ++ * the main one being that DMA transfers are limited to 16 bit ++ * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN ++ * ++ * also we currently assume that the scatter-gather fragments are ++ * all multiple of 4 (except the last) - otherwise we would need ++ * to reset the FIFO before subsequent transfers... ++ * this also means that tx/rx transfers sg's need to be of equal size! ++ * ++ * there may be a few more border-cases we may need to address as well ++ * but unfortunately this would mean splitting up the scatter-gather ++ * list making it slightly unpractical... ++ */ ++static void bcm2835_spi_dma_done(void *data) ++{ ++ struct spi_master *master = data; ++ struct bcm2835_spi *bs = spi_master_get_devdata(master); ++ ++ /* reset fifo and HW */ ++ bcm2835_spi_reset_hw(master); ++ ++ /* and terminate tx-dma as we do not have an irq for it ++ * because when the rx dma will terminate and this callback ++ * is called the tx-dma must have finished - can't get to this ++ * situation otherwise... ++ */ ++ dmaengine_terminate_all(master->dma_tx); ++ ++ /* mark as no longer pending */ ++ bs->dma_pending = 0; ++ ++ /* and mark as completed */; ++ complete(&master->xfer_completion); ++} ++ ++static int bcm2835_spi_prepare_sg(struct spi_master *master, ++ struct spi_transfer *tfr, ++ bool is_tx) ++{ ++ struct dma_chan *chan; ++ struct scatterlist *sgl; ++ unsigned int nents; ++ enum dma_transfer_direction dir; ++ unsigned long flags; ++ ++ struct dma_async_tx_descriptor *desc; ++ dma_cookie_t cookie; ++ ++ if (is_tx) { ++ dir = DMA_MEM_TO_DEV; ++ chan = master->dma_tx; ++ nents = tfr->tx_sg.nents; ++ sgl = tfr->tx_sg.sgl; ++ flags = 0 /* no tx interrupt */; ++ ++ } else { ++ dir = DMA_DEV_TO_MEM; ++ chan = master->dma_rx; ++ nents = tfr->rx_sg.nents; ++ sgl = tfr->rx_sg.sgl; ++ flags = DMA_PREP_INTERRUPT; ++ } ++ /* prepare the channel */ ++ desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); ++ if (!desc) ++ return -EINVAL; ++ ++ /* set callback for rx */ ++ if (!is_tx) { ++ desc->callback = bcm2835_spi_dma_done; ++ desc->callback_param = master; ++ } ++ ++ /* submit it to DMA-engine */ ++ cookie = dmaengine_submit(desc); ++ ++ return dma_submit_error(cookie); ++} ++ ++static inline int bcm2835_check_sg_length(struct sg_table *sgt) ++{ ++ int i; ++ struct scatterlist *sgl; ++ ++ /* check that the sg entries are word-sized (except for last) */ ++ for_each_sg(sgt->sgl, sgl, (int)sgt->nents - 1, i) { ++ if (sg_dma_len(sgl) % 4) ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static int bcm2835_spi_transfer_one_dma(struct spi_master *master, ++ struct spi_device *spi, ++ struct spi_transfer *tfr, ++ u32 cs) ++{ ++ struct bcm2835_spi *bs = spi_master_get_devdata(master); ++ int ret; ++ ++ /* check that the scatter gather segments are all a multiple of 4 */ ++ if (bcm2835_check_sg_length(&tfr->tx_sg) || ++ bcm2835_check_sg_length(&tfr->rx_sg)) { ++ dev_warn_once(&spi->dev, ++ "scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n"); ++ return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); ++ } ++ ++ /* setup tx-DMA */ ++ ret = bcm2835_spi_prepare_sg(master, tfr, true); ++ if (ret) ++ return ret; ++ ++ /* start TX early */ ++ dma_async_issue_pending(master->dma_tx); ++ ++ /* mark as dma pending */ ++ bs->dma_pending = 1; ++ ++ /* set the DMA length */ ++ bcm2835_wr(bs, BCM2835_SPI_DLEN, tfr->len); ++ ++ /* start the HW */ ++ bcm2835_wr(bs, BCM2835_SPI_CS, ++ cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); ++ ++ /* setup rx-DMA late - to run transfers while ++ * mapping of the rx buffers still takes place ++ * this saves 10us or more. ++ */ ++ ret = bcm2835_spi_prepare_sg(master, tfr, false); ++ if (ret) { ++ /* need to reset on errors */ ++ dmaengine_terminate_all(master->dma_tx); ++ bcm2835_spi_reset_hw(master); ++ return ret; ++ } ++ ++ /* start rx dma late */ ++ dma_async_issue_pending(master->dma_rx); ++ ++ /* wait for wakeup in framework */ ++ return 1; ++} ++ ++static bool bcm2835_spi_can_dma(struct spi_master *master, ++ struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ /* only run for gpio_cs */ ++ if (!gpio_is_valid(spi->cs_gpio)) ++ return false; ++ ++ /* we start DMA efforts only on bigger transfers */ ++ if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) ++ return false; ++ ++ /* BCM2835_SPI_DLEN has defined a max transfer size as ++ * 16 bit, so max is 65535 ++ * we can revisit this by using an alternative transfer ++ * method - ideally this would get done without any more ++ * interaction... ++ */ ++ if (tfr->len > 65535) { ++ dev_warn_once(&spi->dev, ++ "transfer size of %d too big for dma-transfer\n", ++ tfr->len); ++ return false; ++ } ++ ++ /* if we run rx/tx_buf with word aligned addresses then we are OK */ ++ if (((u32)tfr->tx_buf % 4 == 0) && ((u32)tfr->tx_buf % 4 == 0)) ++ return true; ++ ++ /* otherwise we only allow transfers within the same page ++ * to avoid wasting time on dma_mapping when it is not practical ++ */ ++ if (((u32)tfr->tx_buf % SZ_4K) + tfr->len > SZ_4K) { ++ dev_warn_once(&spi->dev, ++ "Unaligned spi tx-transfer bridging page\n"); ++ return false; ++ } ++ if (((u32)tfr->rx_buf % SZ_4K) + tfr->len > SZ_4K) { ++ dev_warn_once(&spi->dev, ++ "Unaligned spi tx-transfer bridging page\n"); ++ return false; ++ } ++ ++ /* return OK */ ++ return true; ++} ++ ++void bcm2835_dma_release(struct spi_master *master) ++{ ++ if (master->dma_tx) { ++ dmaengine_terminate_all(master->dma_tx); ++ dma_release_channel(master->dma_tx); ++ master->dma_tx = NULL; ++ } ++ if (master->dma_rx) { ++ dmaengine_terminate_all(master->dma_rx); ++ dma_release_channel(master->dma_rx); ++ master->dma_rx = NULL; ++ } ++} ++ ++void bcm2835_dma_init(struct spi_master *master, struct device *dev) ++{ ++ struct dma_slave_config slave_config; ++ const __be32 *addr; ++ dma_addr_t dma_reg_base; ++ int ret; ++ ++ /* base address in dma-space */ ++ addr = of_get_address(master->dev.of_node, 0, NULL, NULL); ++ if (!addr) { ++ dev_err(dev, "could not get DMA-register address - not using dma mode\n"); ++ goto err; ++ } ++ dma_reg_base = be32_to_cpup(addr); ++ ++ /* get tx/rx dma */ ++ master->dma_tx = dma_request_slave_channel(dev, "tx"); ++ if (!master->dma_tx) { ++ dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); ++ goto err; ++ } ++ master->dma_rx = dma_request_slave_channel(dev, "rx"); ++ if (!master->dma_rx) { ++ dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); ++ goto err_release; ++ } ++ ++ /* configure DMAs */ ++ slave_config.direction = DMA_MEM_TO_DEV; ++ slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); ++ slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ++ ret = dmaengine_slave_config(master->dma_tx, &slave_config); ++ if (ret) ++ goto err_config; ++ ++ slave_config.direction = DMA_DEV_TO_MEM; ++ slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); ++ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ++ ret = dmaengine_slave_config(master->dma_rx, &slave_config); ++ if (ret) ++ goto err_config; ++ ++ /* all went well, so set can_dma */ ++ master->can_dma = bcm2835_spi_can_dma; ++ master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */ ++ /* need to do TX AND RX DMA, so we need dummy buffers */ ++ master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; ++ ++ return; ++ ++err_config: ++ dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", ++ ret); ++err_release: ++ bcm2835_dma_release(master); ++err: ++ return; ++} ++ + static int bcm2835_spi_transfer_one_poll(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *tfr, +@@ -299,6 +580,11 @@ static int bcm2835_spi_transfer_one(stru + return bcm2835_spi_transfer_one_poll(master, spi, tfr, + cs, xfer_time_us); + ++ /* run in dma mode if conditions are right */ ++ if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr)) ++ return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs); ++ ++ /* run in interrupt-mode */ + return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); + } + +@@ -324,6 +610,15 @@ static int bcm2835_spi_prepare_message(s + static void bcm2835_spi_handle_err(struct spi_master *master, + struct spi_message *msg) + { ++ struct bcm2835_spi *bs = spi_master_get_devdata(master); ++ ++ /* if an error occurred and we have an active dma, then terminate */ ++ if (bs->dma_pending) { ++ dmaengine_terminate_all(master->dma_tx); ++ dmaengine_terminate_all(master->dma_rx); ++ bs->dma_pending = 0; ++ } ++ /* and reset */ + bcm2835_spi_reset_hw(master); + } + +@@ -523,6 +818,8 @@ static int bcm2835_spi_probe(struct plat + goto out_clk_disable; + } + ++ bcm2835_dma_init(master, &pdev->dev); ++ + /* initialise the hardware with the default polarities */ + bcm2835_wr(bs, BCM2835_SPI_CS, + BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); +@@ -553,6 +850,8 @@ static int bcm2835_spi_remove(struct pla + + clk_disable_unprepare(bs->clk); + ++ bcm2835_dma_release(master); ++ + return 0; + } + diff --git a/target/linux/brcm2708/patches-4.1/0157-spi-bcm2835-fix-kbuild-compile-warnings-errors-and-a.patch b/target/linux/brcm2708/patches-4.1/0157-spi-bcm2835-fix-kbuild-compile-warnings-errors-and-a.patch new file mode 100644 index 0000000..f51f352 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0157-spi-bcm2835-fix-kbuild-compile-warnings-errors-and-a.patch @@ -0,0 +1,56 @@ +From 3ab28d3476f08708cf2c256dd8a9871583edea00 Mon Sep 17 00:00:00 2001 +From: Martin Sperl +Date: Tue, 12 May 2015 10:32:08 +0000 +Subject: [PATCH 157/203] spi: bcm2835: fix kbuild compile warnings/errors and + a typo + +fixes several warnings/error emmitted by the kbuild system: +* warn: cast from pointer to integer of different size + using size_t instead of u32 +* error: 'SZ_4K' undeclared + moved to PAGE_SIZE and PAGE_MASK instead + +Review showed also a typo in the same code where tx_buff +was checked twice instead of checking both rx and tx_buff. + +Reported by: Stephen Rothwell +Signed-off-by: Martin Sperl +Signed-off-by: Mark Brown +(cherry picked from commit 7e52be0d576e8f7bc99a606f07b9d000c4340f04) +--- + drivers/spi/spi-bcm2835.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/spi/spi-bcm2835.c ++++ b/drivers/spi/spi-bcm2835.c +@@ -20,6 +20,7 @@ + * GNU General Public License for more details. + */ + ++#include + #include + #include + #include +@@ -378,18 +379,19 @@ static bool bcm2835_spi_can_dma(struct s + } + + /* if we run rx/tx_buf with word aligned addresses then we are OK */ +- if (((u32)tfr->tx_buf % 4 == 0) && ((u32)tfr->tx_buf % 4 == 0)) ++ if ((((size_t)tfr->rx_buf & 3) == 0) && ++ (((size_t)tfr->tx_buf & 3) == 0)) + return true; + + /* otherwise we only allow transfers within the same page + * to avoid wasting time on dma_mapping when it is not practical + */ +- if (((u32)tfr->tx_buf % SZ_4K) + tfr->len > SZ_4K) { ++ if (((size_t)tfr->tx_buf & PAGE_MASK) + tfr->len > PAGE_SIZE) { + dev_warn_once(&spi->dev, + "Unaligned spi tx-transfer bridging page\n"); + return false; + } +- if (((u32)tfr->rx_buf % SZ_4K) + tfr->len > SZ_4K) { ++ if (((size_t)tfr->rx_buf & PAGE_MASK) + tfr->len > PAGE_SIZE) { + dev_warn_once(&spi->dev, + "Unaligned spi tx-transfer bridging page\n"); + return false; diff --git a/target/linux/brcm2708/patches-4.1/0158-spi-bcm2835-bcm2835_dma_release-can-be-static.patch b/target/linux/brcm2708/patches-4.1/0158-spi-bcm2835-bcm2835_dma_release-can-be-static.patch new file mode 100644 index 0000000..045ef92 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0158-spi-bcm2835-bcm2835_dma_release-can-be-static.patch @@ -0,0 +1,32 @@ +From 9e0ce86052c88c463ec3f95da35d5633c36894fa Mon Sep 17 00:00:00 2001 +From: kbuild test robot +Date: Tue, 12 May 2015 19:43:59 +0800 +Subject: [PATCH 158/203] spi: bcm2835: bcm2835_dma_release() can be static + +Signed-off-by: Fengguang Wu +Signed-off-by: Mark Brown +(cherry picked from commit 29ad1a7a9e08f1d2b6795c5278a0c0fd23679ded) +--- + drivers/spi/spi-bcm2835.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/spi/spi-bcm2835.c ++++ b/drivers/spi/spi-bcm2835.c +@@ -401,7 +401,7 @@ static bool bcm2835_spi_can_dma(struct s + return true; + } + +-void bcm2835_dma_release(struct spi_master *master) ++static void bcm2835_dma_release(struct spi_master *master) + { + if (master->dma_tx) { + dmaengine_terminate_all(master->dma_tx); +@@ -415,7 +415,7 @@ void bcm2835_dma_release(struct spi_mast + } + } + +-void bcm2835_dma_init(struct spi_master *master, struct device *dev) ++static void bcm2835_dma_init(struct spi_master *master, struct device *dev) + { + struct dma_slave_config slave_config; + const __be32 *addr; diff --git a/target/linux/brcm2708/patches-4.1/0159-dt-overlay-to-enable-dma-for-spi-driver.patch b/target/linux/brcm2708/patches-4.1/0159-dt-overlay-to-enable-dma-for-spi-driver.patch new file mode 100644 index 0000000..25d4d43 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0159-dt-overlay-to-enable-dma-for-spi-driver.patch @@ -0,0 +1,45 @@ +From ff9071764e459f0ae477ca1121cb3d225bbab3f8 Mon Sep 17 00:00:00 2001 +From: Martin Sperl +Date: Wed, 22 Jul 2015 08:34:41 +0000 +Subject: [PATCH 159/203] dt-overlay to enable dma for spi driver + +Signed-off-by: Martin Sperl +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/spi-dma-overlay.dts | 20 ++++++++++++++++++++ + 2 files changed, 21 insertions(+) + create mode 100755 arch/arm/boot/dts/overlays/spi-dma-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -45,6 +45,7 @@ dtb-$(RPI_DT_OVERLAYS) += rpi-sense-over + dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += spi-dma-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += uart1-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += vga666-overlay.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi-dma-overlay.dts +@@ -0,0 +1,20 @@ ++/* ++ * Device tree overlay for spi-bcm2835 to allow dma ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dmas = <&dma 6>, <&dma 7>; ++ dma-names = "tx", "rx"; ++ }; ++ }; ++ }; diff --git a/target/linux/brcm2708/patches-4.1/0160-dt-overlay-added-documentation-of-spi-dma-overlay.patch b/target/linux/brcm2708/patches-4.1/0160-dt-overlay-added-documentation-of-spi-dma-overlay.patch new file mode 100644 index 0000000..a9b6888 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0160-dt-overlay-added-documentation-of-spi-dma-overlay.patch @@ -0,0 +1,25 @@ +From ae4577bd4fcc0e9fb9166550433e2b0ee1ece0e1 Mon Sep 17 00:00:00 2001 +From: Martin Sperl +Date: Wed, 22 Jul 2015 12:41:54 +0000 +Subject: [PATCH 160/203] dt: overlay: added documentation of spi-dma overlay + +Signed-off-by: Martin Sperl +--- + arch/arm/boot/dts/overlays/README | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -515,6 +515,12 @@ Load: dtoverlay=spi-bcm2835 + Params: + + ++Name: spi-dma ++Info: enables dma modes for spi-bcm2835 ++Load: dtoverlay=spi-dma ++Params: ++ ++ + Name: tinylcd35 + Info: 3.5" Color TFT Display by www.tinylcd.com + Options: Touch, RTC, keypad diff --git a/target/linux/brcm2708/patches-4.1/0161-rpisense-fb-add-low-light-mode-and-gamma-control.patch b/target/linux/brcm2708/patches-4.1/0161-rpisense-fb-add-low-light-mode-and-gamma-control.patch new file mode 100644 index 0000000..16ef29c --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0161-rpisense-fb-add-low-light-mode-and-gamma-control.patch @@ -0,0 +1,141 @@ +From 15cf5667c9508d18808e0edf95acbff0313ef954 Mon Sep 17 00:00:00 2001 +From: Serge Schneider +Date: Mon, 17 Aug 2015 18:06:16 +0100 +Subject: [PATCH 161/203] rpisense-fb: add low-light mode and gamma control + +--- + drivers/video/fbdev/rpisense-fb.c | 68 +++++++++++++++++++++++++++++--- + include/linux/mfd/rpisense/framebuffer.h | 6 ++- + 2 files changed, 68 insertions(+), 6 deletions(-) + +--- a/drivers/video/fbdev/rpisense-fb.c ++++ b/drivers/video/fbdev/rpisense-fb.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -26,22 +27,35 @@ + #include + #include + ++static bool lowlight; ++module_param(lowlight, bool, 0); ++MODULE_PARM_DESC(lowlight, "Reduce LED matrix brightness to one third"); ++ + struct rpisense *rpisense; + + struct rpisense_fb_param { + char __iomem *vmem; + u8 *vmem_work; + u32 vmemsize; +- u8 gamma[32]; ++ u8 *gamma; + }; + ++static u8 gamma_default[32] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, ++ 0x02, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0E, 0x0F, 0x11, ++ 0x12, 0x14, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,}; ++ ++static u8 gamma_low[32] = {0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, ++ 0x03, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, ++ 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x0A, 0x0A,}; ++ ++static u8 gamma_user[32]; ++ + static struct rpisense_fb_param rpisense_fb_param = { + .vmem = NULL, + .vmemsize = 128, +- .gamma = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, +- 0x02, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07, +- 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0E, 0x0F, 0x11, +- 0x12, 0x14, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,}, ++ .gamma = gamma_default, + }; + + static struct fb_deferred_io rpisense_fb_defio; +@@ -127,6 +141,46 @@ static struct fb_deferred_io rpisense_fb + .deferred_io = rpisense_fb_deferred_io, + }; + ++static int rpisense_fb_ioctl(struct fb_info *info, unsigned int cmd, ++ unsigned long arg) ++{ ++ switch (cmd) { ++ case SENSEFB_FBIOGET_GAMMA: ++ if (copy_to_user((void __user *) arg, rpisense_fb_param.gamma, ++ sizeof(u8[32]))) ++ return -EFAULT; ++ return 0; ++ case SENSEFB_FBIOSET_GAMMA: ++ if (copy_from_user(gamma_user, (void __user *)arg, ++ sizeof(u8[32]))) ++ return -EFAULT; ++ rpisense_fb_param.gamma = gamma_user; ++ schedule_delayed_work(&info->deferred_work, ++ rpisense_fb_defio.delay); ++ return 0; ++ case SENSEFB_FBIORESET_GAMMA: ++ switch (arg) { ++ case 0: ++ rpisense_fb_param.gamma = gamma_default; ++ break; ++ case 1: ++ rpisense_fb_param.gamma = gamma_low; ++ break; ++ case 2: ++ rpisense_fb_param.gamma = gamma_user; ++ break; ++ default: ++ return -EINVAL; ++ } ++ schedule_delayed_work(&info->deferred_work, ++ rpisense_fb_defio.delay); ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ + static struct fb_ops rpisense_fb_ops = { + .owner = THIS_MODULE, + .fb_read = fb_sys_read, +@@ -134,6 +188,7 @@ static struct fb_ops rpisense_fb_ops = { + .fb_fillrect = rpisense_fb_fillrect, + .fb_copyarea = rpisense_fb_copyarea, + .fb_imageblit = rpisense_fb_imageblit, ++ .fb_ioctl = rpisense_fb_ioctl, + }; + + static int rpisense_fb_probe(struct platform_device *pdev) +@@ -171,6 +226,9 @@ static int rpisense_fb_probe(struct plat + info->screen_base = rpisense_fb_param.vmem; + info->screen_size = rpisense_fb_param.vmemsize; + ++ if (lowlight) ++ rpisense_fb_param.gamma = gamma_low; ++ + fb_deferred_io_init(info); + + ret = register_framebuffer(info); +--- a/include/linux/mfd/rpisense/framebuffer.h ++++ b/include/linux/mfd/rpisense/framebuffer.h +@@ -16,7 +16,11 @@ + #ifndef __LINUX_RPISENSE_FB_H_ + #define __LINUX_RPISENSE_FB_H_ + +-#include ++#define SENSEFB_FBIO_IOC_MAGIC 0xF1 ++ ++#define SENSEFB_FBIOGET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 0) ++#define SENSEFB_FBIOSET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 1) ++#define SENSEFB_FBIORESET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 2) + + struct rpisense; + diff --git a/target/linux/brcm2708/patches-4.1/0162-BCM270X_DT-README-add-note-on-indentation.patch b/target/linux/brcm2708/patches-4.1/0162-BCM270X_DT-README-add-note-on-indentation.patch new file mode 100644 index 0000000..8e0578c --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0162-BCM270X_DT-README-add-note-on-indentation.patch @@ -0,0 +1,22 @@ +From 27932f3c0031925c59b6f6787dbe8c4b379bbb11 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 19 Aug 2015 11:38:10 +0100 +Subject: [PATCH 162/203] BCM270X_DT: README - add note on indentation + +--- + arch/arm/boot/dts/overlays/README | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -74,6 +74,10 @@ behaviour. See the list of overlays belo + The Overlay and Parameter Reference + =================================== + ++N.B. When editing this file, please preserve the indentation levels to make it simple to parse ++programmatically. NO HARD TABS. ++ ++ + Name: + Info: Configures the base Raspberry Pi hardware + Load: diff --git a/target/linux/brcm2708/patches-4.1/0163-bcm2708-dmaengine-Use-more-DMA-channels-but-not-12.patch b/target/linux/brcm2708/patches-4.1/0163-bcm2708-dmaengine-Use-more-DMA-channels-but-not-12.patch new file mode 100644 index 0000000..6e5cf52 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0163-bcm2708-dmaengine-Use-more-DMA-channels-but-not-12.patch @@ -0,0 +1,173 @@ +From a3414b2d51a0fa2b4cea7886168e5e14013904c8 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 20 Aug 2015 13:50:18 +0100 +Subject: [PATCH 163/203] bcm2708-dmaengine: Use more DMA channels (but not 12) + +1) Only the bcm2708_fb drivers uses the legacy DMA API, and +it requires a BULK-capable channel, so all other types +(FAST, NORMAL and LITE) can be made available to the regular +DMA API. + +2) DMA channels 11-14 share an interrupt. The driver can't +handle this, so don't use channels 12-14 (12 was used, probably +because it appears to have an interrupt, but in reality that +interrupt is for activity on ANY channel). This may explain +a lockup encountered when running out of DMA channels. + +The combined effect of this patch is to leave 7 DMA channels +available + channel 0 for bcm2708_fb via the legacy API. + +See: https://github.com/raspberrypi/linux/issues/1110 + https://github.com/raspberrypi/linux/issues/1108 +--- + arch/arm/boot/dts/bcm2708_common.dtsi | 5 ++-- + drivers/dma/bcm2708-dmaengine.c | 43 +++++++++++++++++++++++------------ + 2 files changed, 31 insertions(+), 17 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -59,11 +59,10 @@ + <1 24>, + <1 25>, + <1 26>, +- <1 27>, +- <1 28>; ++ <1 27>; + + #dma-cells = <1>; +- brcm,dma-channel-mask = <0x7f35>; ++ brcm,dma-channel-mask = <0x0f35>; + }; + + intc: interrupt-controller { +--- a/drivers/dma/bcm2708-dmaengine.c ++++ b/drivers/dma/bcm2708-dmaengine.c +@@ -184,7 +184,7 @@ static void vc_dmaman_init(struct vc_dma + } + + static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman, +- unsigned preferred_feature_set) ++ unsigned required_feature_set) + { + u32 chans; + int chan = 0; +@@ -193,10 +193,8 @@ static int vc_dmaman_chan_alloc(struct v + chans = dmaman->chan_available; + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++) + /* select the subset of available channels with the desired +- feature so long as some of the candidate channels have that +- feature */ +- if ((preferred_feature_set & (1 << feature)) && +- (chans & dmaman->has_feature[feature])) ++ features */ ++ if (required_feature_set & (1 << feature)) + chans &= dmaman->has_feature[feature]; + + if (!chans) +@@ -228,7 +226,7 @@ static int vc_dmaman_chan_free(struct vc + + /* DMA Manager Monitor */ + +-extern int bcm_dma_chan_alloc(unsigned preferred_feature_set, ++extern int bcm_dma_chan_alloc(unsigned required_feature_set, + void __iomem **out_dma_base, int *out_dma_irq) + { + struct vc_dmaman *dmaman = g_dmaman; +@@ -240,7 +238,7 @@ extern int bcm_dma_chan_alloc(unsigned p + return -ENODEV; + + mutex_lock(&dmaman->lock); +- chan = vc_dmaman_chan_alloc(dmaman, preferred_feature_set); ++ chan = vc_dmaman_chan_alloc(dmaman, required_feature_set); + if (chan < 0) + goto out; + +@@ -442,6 +440,7 @@ static inline struct bcm2835_desc *to_bc + return container_of(t, struct bcm2835_desc, vd.tx); + } + ++#if 0 + static void dma_dumpregs(struct bcm2835_chan *c) + { + pr_debug("-------------DMA DUMPREGS-------------\n"); +@@ -457,6 +456,7 @@ static void dma_dumpregs(struct bcm2835_ + readl(c->chan_base + BCM2835_DMA_NEXTCB)); + pr_debug("--------------------------------------\n"); + } ++#endif + + static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) + { +@@ -862,6 +862,7 @@ static struct dma_async_tx_descriptor *b + uint32_t len = sg_dma_len(sgent); + + for (j = 0; j < len; j += max_size) { ++ u32 waits; + struct bcm2835_dma_cb *control_block = + &d->control_block_base[i+splitct]; + +@@ -879,7 +880,7 @@ static struct dma_async_tx_descriptor *b + } + + /* Common part */ +- u32 waits = SDHCI_BCM_DMA_WAITS; ++ waits = SDHCI_BCM_DMA_WAITS; + if ((dma_debug >> 0) & 0x1f) + waits = (dma_debug >> 0) & 0x1f; + control_block->info |= BCM2835_DMA_WAITS(waits); +@@ -1074,6 +1075,14 @@ static int bcm2835_dma_probe(struct plat + int rc; + int i; + int irq; ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++ static const u32 wanted_features[] = { ++ BCM_DMA_FEATURE_FAST, ++ BCM_DMA_FEATURE_NORMAL, ++ BCM_DMA_FEATURE_LITE ++ }; ++ int j; ++#endif + + + if (!pdev->dev.dma_mask) +@@ -1120,20 +1129,24 @@ static int bcm2835_dma_probe(struct plat + + platform_set_drvdata(pdev, od); + +- for (i = 0; i < 5; i++) { ++ for (i = 0, j = 0; j < ARRAY_SIZE(wanted_features);) { ++ + void __iomem *chan_base; + int chan_id; + +- chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE, +- &chan_base, +- &irq); +- +- if (chan_id < 0) +- break; ++ chan_id = bcm_dma_chan_alloc(wanted_features[j], ++ &chan_base, ++ &irq); ++ ++ if (chan_id < 0) { ++ j++; ++ continue; ++ } + + rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq); + if (rc) + goto err_no_dma; ++ i++; + } + + if (pdev->dev.of_node) { +@@ -1146,6 +1159,8 @@ static int bcm2835_dma_probe(struct plat + } + } + ++ dev_info(&pdev->dev, "Initialized %i DMA channels (+ 1 legacy)\n", i); ++ + #else + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (rc) diff --git a/target/linux/brcm2708/patches-4.1/0164-staging-fbtft-Add-reset-to-fbtft_init_display_dt.patch b/target/linux/brcm2708/patches-4.1/0164-staging-fbtft-Add-reset-to-fbtft_init_display_dt.patch new file mode 100644 index 0000000..358f4d0 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0164-staging-fbtft-Add-reset-to-fbtft_init_display_dt.patch @@ -0,0 +1,32 @@ +From 82bd9c0d64c76c40bff8c4325df8302c8ffc6945 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Sat, 11 Jul 2015 18:48:10 +0200 +Subject: [PATCH 164/203] staging: fbtft: Add reset to fbtft_init_display_dt() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +When an init sequence is present in the Device Tree, +fbtft_init_display_dt() is used to initialize the display. +Add missing reset function call and activation of +chip select for parallel bus. + +Signed-off-by: Noralf Trønnes +--- + drivers/staging/fbtft/fbtft-core.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/staging/fbtft/fbtft-core.c ++++ b/drivers/staging/fbtft/fbtft-core.c +@@ -1074,6 +1074,11 @@ static int fbtft_init_display_dt(struct + p = of_prop_next_u32(prop, NULL, &val); + if (!p) + return -EINVAL; ++ ++ par->fbtftops.reset(par); ++ if (par->gpio.cs != -1) ++ gpio_set_value(par->gpio.cs, 0); /* Activate chip */ ++ + while (p) { + if (val & FBTFT_OF_INIT_CMD) { + val &= 0xFFFF; diff --git a/target/linux/brcm2708/patches-4.1/0165-BCM270X_DT-mz61581-Revert-to-spi-bcm2708.patch b/target/linux/brcm2708/patches-4.1/0165-BCM270X_DT-mz61581-Revert-to-spi-bcm2708.patch new file mode 100644 index 0000000..d4f1c90 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0165-BCM270X_DT-mz61581-Revert-to-spi-bcm2708.patch @@ -0,0 +1,31 @@ +From 75cf473165850a8e765eb3a081be50fe7620e16e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Sun, 19 Jul 2015 18:57:06 +0200 +Subject: [PATCH 165/203] BCM270X_DT: mz61581: Revert to spi-bcm2708 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The MZ61581 display does not work with spi-bcm2835 and software +chip select. It works before the commit: +spi: bcm2835: transform native-cs to gpio-cs on first spi_setup + +Revert to spi-bcm2708 until the cause has been detected and the +issue resolved. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/overlays/mz61581-overlay.dts | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm/boot/dts/overlays/mz61581-overlay.dts ++++ b/arch/arm/boot/dts/overlays/mz61581-overlay.dts +@@ -12,6 +12,8 @@ + fragment@0 { + target = <&spi0>; + __overlay__ { ++ /* does not work with spi-bcm2835 using software chip selects */ ++ compatible = "brcm,bcm2708-spi"; + status = "okay"; + + spidev@0{ diff --git a/target/linux/brcm2708/patches-4.1/0166-Add-dev-gpiomem-device-for-rootless-user-GPIO-access.patch b/target/linux/brcm2708/patches-4.1/0166-Add-dev-gpiomem-device-for-rootless-user-GPIO-access.patch new file mode 100644 index 0000000..d94f0df --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0166-Add-dev-gpiomem-device-for-rootless-user-GPIO-access.patch @@ -0,0 +1,336 @@ +From c69d4dbfcf290abc926a4499a7583b7514726ad1 Mon Sep 17 00:00:00 2001 +From: Luke Wren +Date: Fri, 21 Aug 2015 23:14:48 +0100 +Subject: [PATCH 166/203] Add /dev/gpiomem device for rootless user GPIO access + +Signed-off-by: Luke Wren +--- + arch/arm/boot/dts/bcm2708.dtsi | 6 + + arch/arm/boot/dts/bcm2709.dtsi | 6 + + drivers/char/broadcom/Kconfig | 9 ++ + drivers/char/broadcom/Makefile | 3 + + drivers/char/broadcom/bcm2835-gpiomem.c | 265 ++++++++++++++++++++++++++++++++ + 5 files changed, 289 insertions(+) + create mode 100644 drivers/char/broadcom/bcm2835-gpiomem.c + +--- a/arch/arm/boot/dts/bcm2708.dtsi ++++ b/arch/arm/boot/dts/bcm2708.dtsi +@@ -15,5 +15,11 @@ + arm-pmu { + compatible = "arm,arm1176-pmu"; + }; ++ ++ gpiomem { ++ compatible = "brcm,bcm2835-gpiomem"; ++ reg = <0x7e200000 0x1000>; ++ status = "okay"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/bcm2709.dtsi ++++ b/arch/arm/boot/dts/bcm2709.dtsi +@@ -16,6 +16,12 @@ + compatible = "arm,cortex-a7-pmu"; + interrupts = <3 9>; + }; ++ ++ gpiomem { ++ compatible = "brcm,bcm2835-gpiomem"; ++ reg = <0x7e200000 0x1000>; ++ status = "okay"; ++ }; + }; + + timer { +--- a/drivers/char/broadcom/Kconfig ++++ b/drivers/char/broadcom/Kconfig +@@ -38,3 +38,12 @@ config BCM_VC_SM + help + Support for the VC shared memory on the Broadcom reference + design. Uses the VCHIQ stack. ++ ++config BCM2835_DEVGPIOMEM ++ tristate "/dev/gpiomem rootless GPIO access via mmap() on the BCM2835" ++ default m ++ help ++ Provides users with root-free access to the GPIO registers ++ on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO ++ register page to the user's pointer. ++ +--- a/drivers/char/broadcom/Makefile ++++ b/drivers/char/broadcom/Makefile +@@ -2,3 +2,6 @@ obj-$(CONFIG_BCM_VC_CMA) += vc_cma/ + obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o + obj-$(CONFIG_BCM_VCIO) += vcio.o + obj-$(CONFIG_BCM_VC_SM) += vc_sm/ ++ ++obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o ++ +--- /dev/null ++++ b/drivers/char/broadcom/bcm2835-gpiomem.c +@@ -0,0 +1,265 @@ ++/** ++ * GPIO memory device driver ++ * ++ * Creates a chardev /dev/gpiomem which will provide user access to ++ * the BCM2835's GPIO registers when it is mmap()'d. ++ * No longer need root for user GPIO access, but without relaxing permissions ++ * on /dev/mem. ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DEVICE_NAME "bcm2835-gpiomem" ++#define DRIVER_NAME "gpiomem-bcm2835" ++#define DEVICE_MINOR 0 ++ ++struct bcm2835_gpiomem_instance { ++ unsigned long gpio_regs_phys; ++ struct device *dev; ++}; ++ ++static struct cdev bcm2835_gpiomem_cdev; ++static dev_t bcm2835_gpiomem_devid; ++static struct class *bcm2835_gpiomem_class; ++static struct device *bcm2835_gpiomem_dev; ++static struct bcm2835_gpiomem_instance *inst; ++ ++ ++/**************************************************************************** ++* ++* GPIO mem chardev file ops ++* ++***************************************************************************/ ++ ++static int bcm2835_gpiomem_open(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ int ret = 0; ++ ++ dev_info(inst->dev, "gpiomem device opened."); ++ ++ if (dev != DEVICE_MINOR) { ++ dev_err(inst->dev, "Unknown minor device: %d", dev); ++ ret = -ENXIO; ++ } ++ return ret; ++} ++ ++static int bcm2835_gpiomem_release(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ int ret = 0; ++ ++ if (dev != DEVICE_MINOR) { ++ dev_err(inst->dev, "Unknown minor device %d", dev); ++ ret = -ENXIO; ++ } ++ return ret; ++} ++ ++static const struct vm_operations_struct bcm2835_gpiomem_vm_ops = { ++#ifdef CONFIG_HAVE_IOREMAP_PROT ++ .access = generic_access_phys ++#endif ++}; ++ ++static int bcm2835_gpiomem_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ /* Ignore what the user says - they're getting the GPIO regs ++ whether they like it or not! */ ++ unsigned long gpio_page = inst->gpio_regs_phys >> PAGE_SHIFT; ++ ++ vma->vm_page_prot = phys_mem_access_prot(file, gpio_page, ++ PAGE_SIZE, ++ vma->vm_page_prot); ++ vma->vm_ops = &bcm2835_gpiomem_vm_ops; ++ if (remap_pfn_range(vma, vma->vm_start, ++ gpio_page, ++ PAGE_SIZE, ++ vma->vm_page_prot)) { ++ return -EAGAIN; ++ } ++ return 0; ++} ++ ++static const struct file_operations ++bcm2835_gpiomem_fops = { ++ .owner = THIS_MODULE, ++ .open = bcm2835_gpiomem_open, ++ .release = bcm2835_gpiomem_release, ++ .mmap = bcm2835_gpiomem_mmap, ++}; ++ ++ ++ /**************************************************************************** ++* ++* Probe and remove functions ++* ++***************************************************************************/ ++ ++ ++static int bcm2835_gpiomem_probe(struct platform_device *pdev) ++{ ++ int err; ++ void *ptr_err; ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct resource *ioresource; ++ ++ /* Allocate buffers and instance data */ ++ ++ inst = kzalloc(sizeof(struct bcm2835_gpiomem_instance), GFP_KERNEL); ++ ++ if (!inst) { ++ err = -ENOMEM; ++ goto failed_inst_alloc; ++ } ++ ++ inst->dev = dev; ++ ++ /* Create character device entries */ ++ ++ err = alloc_chrdev_region(&bcm2835_gpiomem_devid, ++ DEVICE_MINOR, 1, DEVICE_NAME); ++ if (err != 0) { ++ dev_err(inst->dev, "unable to allocate device number"); ++ goto failed_alloc_chrdev; ++ } ++ cdev_init(&bcm2835_gpiomem_cdev, &bcm2835_gpiomem_fops); ++ bcm2835_gpiomem_cdev.owner = THIS_MODULE; ++ err = cdev_add(&bcm2835_gpiomem_cdev, bcm2835_gpiomem_devid, 1); ++ if (err != 0) { ++ dev_err(inst->dev, "unable to register device"); ++ goto failed_cdev_add; ++ } ++ ++ /* Create sysfs entries */ ++ ++ bcm2835_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME); ++ ptr_err = bcm2835_gpiomem_class; ++ if (IS_ERR(ptr_err)) ++ goto failed_class_create; ++ ++ bcm2835_gpiomem_dev = device_create(bcm2835_gpiomem_class, NULL, ++ bcm2835_gpiomem_devid, NULL, ++ "gpiomem"); ++ ptr_err = bcm2835_gpiomem_dev; ++ if (IS_ERR(ptr_err)) ++ goto failed_device_create; ++ ++ /* Get address from device tree if available (*_resource() correctly ++ converts the bus address in device tree to a physical address), ++ or use hardcoded offset + BCM2708_PERI_BASE if not. ++ (In spite of its name 2708 actually seems to have the correct ++ mach-dependent value on 2709 etc, as it is defined in ++ mach-bcm270x/platform.h) */ ++ ++ if (node) { ++ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ inst->gpio_regs_phys = ioresource->start; ++ } else { ++ inst->gpio_regs_phys = GPIO_BASE; ++ } ++ ++ dev_info(inst->dev, "Initialised: Registers at 0x%08lx", ++ inst->gpio_regs_phys); ++ ++ return 0; ++ ++failed_device_create: ++ class_destroy(bcm2835_gpiomem_class); ++failed_class_create: ++ cdev_del(&bcm2835_gpiomem_cdev); ++ err = PTR_ERR(ptr_err); ++failed_cdev_add: ++ unregister_chrdev_region(bcm2835_gpiomem_devid, 1); ++failed_alloc_chrdev: ++ kfree(inst); ++failed_inst_alloc: ++ dev_err(inst->dev, "could not load bcm2835_gpiomem"); ++ return err; ++} ++ ++static int bcm2835_gpiomem_remove(struct platform_device *pdev) ++{ ++ struct device *dev = inst->dev; ++ ++ kfree(inst); ++ device_destroy(bcm2835_gpiomem_class, bcm2835_gpiomem_devid); ++ class_destroy(bcm2835_gpiomem_class); ++ cdev_del(&bcm2835_gpiomem_cdev); ++ unregister_chrdev_region(bcm2835_gpiomem_devid, 1); ++ ++ dev_info(dev, "GPIO mem driver removed - OK"); ++ return 0; ++} ++ ++ /**************************************************************************** ++* ++* Register the driver with device tree ++* ++***************************************************************************/ ++ ++static const struct of_device_id bcm2835_gpiomem_of_match[] = { ++ {.compatible = "brcm,bcm2835-gpiomem",}, ++ { /* sentinel */ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, bcm2835_gpiomem_of_match); ++ ++static struct platform_driver bcm2835_gpiomem_driver = { ++ .probe = bcm2835_gpiomem_probe, ++ .remove = bcm2835_gpiomem_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_gpiomem_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2835_gpiomem_driver); ++ ++MODULE_ALIAS("platform:gpiomem-bcm2835"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("gpiomem driver for accessing GPIO from userspace"); ++MODULE_AUTHOR("Luke Wren "); diff --git a/target/linux/brcm2708/patches-4.1/0167-tpa6130a2-Add-headphone-switch-control.patch b/target/linux/brcm2708/patches-4.1/0167-tpa6130a2-Add-headphone-switch-control.patch new file mode 100644 index 0000000..7e9b1b7 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0167-tpa6130a2-Add-headphone-switch-control.patch @@ -0,0 +1,91 @@ +From 8cbdae16b29ddf95d9eccc74c355d8a37c520bdd Mon Sep 17 00:00:00 2001 +From: Jan Grulich +Date: Mon, 24 Aug 2015 16:02:34 +0100 +Subject: [PATCH 167/203] tpa6130a2: Add headphone switch control + +Signed-off-by: Jan Grulich +--- + sound/soc/codecs/tpa6130a2.c | 29 ++++++++++++++++++++++++++--- + 1 file changed, 26 insertions(+), 3 deletions(-) + +--- a/sound/soc/codecs/tpa6130a2.c ++++ b/sound/soc/codecs/tpa6130a2.c +@@ -4,6 +4,7 @@ + * Copyright (C) Nokia Corporation + * + * Author: Peter Ujfalusi ++ * Modified: Jan Grulich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License +@@ -52,6 +53,8 @@ struct tpa6130a2_data { + enum tpa_model id; + }; + ++static void tpa6130a2_channel_enable(u8 channel, int enable); ++ + static int tpa6130a2_i2c_read(int reg) + { + struct tpa6130a2_data *data; +@@ -189,7 +192,7 @@ exit: + } + + static int tpa6130a2_get_volsw(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_value *ucontrol) ++ struct snd_ctl_elem_value *ucontrol) + { + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; +@@ -218,7 +221,7 @@ static int tpa6130a2_get_volsw(struct sn + } + + static int tpa6130a2_put_volsw(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_value *ucontrol) ++ struct snd_ctl_elem_value *ucontrol) + { + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; +@@ -255,8 +258,22 @@ static int tpa6130a2_put_volsw(struct sn + return 1; + } + ++static int tpa6130a2_put_hp_sw(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int enable = ucontrol->value.integer.value[0]; ++ unsigned int state; ++ ++ state = (tpa6130a2_read(TPA6130A2_REG_VOL_MUTE) & 0x80) == 0; ++ if (state == enable) ++ return 0; /* No change */ ++ ++ tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L, enable); ++ return 1; /* Changed */ ++} ++ + /* +- * TPA6130 volume. From -59.5 to 4 dB with increasing step size when going ++ * TPA6130 volume. From -59.5 to +4.0 dB with increasing step size when going + * down in gain. + */ + static const unsigned int tpa6130_tlv[] = { +@@ -278,6 +295,9 @@ static const struct snd_kcontrol_new tpa + TPA6130A2_REG_VOL_MUTE, 0, 0x3f, 0, + tpa6130a2_get_volsw, tpa6130a2_put_volsw, + tpa6130_tlv), ++ SOC_SINGLE_EXT("TPA6130A2 Headphone Playback Switch", ++ TPA6130A2_REG_VOL_MUTE, 7, 1, 1, ++ tpa6130a2_get_volsw, tpa6130a2_put_hp_sw), + }; + + static const unsigned int tpa6140_tlv[] = { +@@ -292,6 +312,9 @@ static const struct snd_kcontrol_new tpa + TPA6130A2_REG_VOL_MUTE, 1, 0x1f, 0, + tpa6130a2_get_volsw, tpa6130a2_put_volsw, + tpa6140_tlv), ++ SOC_SINGLE_EXT("TPA6140A2 Headphone Playback Switch", ++ TPA6130A2_REG_VOL_MUTE, 7, 1, 1, ++ tpa6130a2_get_volsw, tpa6130a2_put_hp_sw), + }; + + /* diff --git a/target/linux/brcm2708/patches-4.1/0168-RaspiDAC3-support.patch b/target/linux/brcm2708/patches-4.1/0168-RaspiDAC3-support.patch new file mode 100644 index 0000000..dc13aec --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0168-RaspiDAC3-support.patch @@ -0,0 +1,335 @@ +From a382428726be87f1d848772a4c1a619144a33c98 Mon Sep 17 00:00:00 2001 +From: Jan Grulich +Date: Mon, 24 Aug 2015 16:03:47 +0100 +Subject: [PATCH 168/203] RaspiDAC3 support + +Signed-off-by: Jan Grulich +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 6 + + arch/arm/boot/dts/overlays/raspidac3-overlay.dts | 45 ++++++ + arch/arm/configs/bcm2709_defconfig | 1 + + arch/arm/configs/bcmrpi_defconfig | 1 + + sound/soc/bcm/Kconfig | 8 + + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/raspidac3.c | 191 +++++++++++++++++++++++ + 8 files changed, 255 insertions(+) + create mode 100644 arch/arm/boot/dts/overlays/raspidac3-overlay.dts + create mode 100644 sound/soc/bcm/raspidac3.c + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -37,6 +37,7 @@ dtb-$(RPI_DT_OVERLAYS) += pitft28-resist + dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += pwm-2chan-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += raspidac3-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -455,6 +455,12 @@ Params: pin Output + clock PWM clock frequency (informational) + + ++Name: raspidac3 ++Info: Configures the RaspiDAV Rev.3x audio card ++Load: dtoverlay=raspidac3 ++Params: ++ ++ + Name: rpi-dac + Info: Configures the RPi DAC audio card + Load: dtoverlay=rpi-dac +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/raspidac3-overlay.dts +@@ -0,0 +1,45 @@ ++// Definitions for RaspiDACv3 ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "jg,raspidacv3"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4c { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4c>; ++ status = "okay"; ++ }; ++ ++ tpa6130a2: tpa6130a2@60 { ++ compatible = "ti,tpa6130a2"; ++ reg = <0x60>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -830,6 +830,7 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m + CONFIG_SND_BCM2708_SOC_RPI_DAC=m + CONFIG_SND_BCM2708_SOC_RPI_PROTO=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_BCM2708_SOC_RASPIDAC3=m + CONFIG_SND_SOC_WM8804_I2C=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -823,6 +823,7 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m + CONFIG_SND_BCM2708_SOC_RPI_DAC=m + CONFIG_SND_BCM2708_SOC_RPI_PROTO=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_BCM2708_SOC_RASPIDAC3=m + CONFIG_SND_SOC_WM8804_I2C=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -67,3 +67,11 @@ config SND_BCM2708_SOC_IQAUDIO_DAC + select SND_SOC_PCM512x_I2C + help + Say Y or M if you want to add support for IQaudIO-DAC. ++ ++config SND_BCM2708_SOC_RASPIDAC3 ++ tristate "Support for RaspiDAC Rev.3x" ++ depends on SND_BCM2708_SOC_I2S ++ select SND_SOC_PCM512x_I2C ++ select SND_SOC_TPA6130A2 ++ help ++ Say Y or M if you want to add support for RaspiDAC Rev.3x. +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -16,6 +16,7 @@ snd-soc-hifiberry-amp-objs := hifiberry_ + snd-soc-rpi-dac-objs := rpi-dac.o + snd-soc-rpi-proto-objs := rpi-proto.o + snd-soc-iqaudio-dac-objs := iqaudio-dac.o ++snd-soc-raspidac3-objs := raspidac3.o + + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o +@@ -24,3 +25,4 @@ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_A + obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o + obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o + obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o +--- /dev/null ++++ b/sound/soc/bcm/raspidac3.c +@@ -0,0 +1,191 @@ ++/* ++ * ASoC Driver for RaspiDAC v3 ++ * ++ * Author: Jan Grulich ++ * Copyright 2015 ++ * based on code by Daniel Matuschek ++ * based on code by Florian Meier ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/pcm512x.h" ++#include "../codecs/tpa6130a2.h" ++ ++/* sound card init */ ++static int snd_rpi_raspidac3_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ int ret; ++ struct snd_soc_card *card = rtd->card; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02); ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); ++ ++ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); ++ if (ret < 0) ++ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); ++ else { ++ struct snd_kcontrol *kctl; ++ ++ ret = tpa6130a2_add_controls(codec); ++ if (ret < 0) ++ dev_warn(card->dev, "Failed to add TPA6130A2 controls: %d\n", ++ ret); ++ ret = snd_soc_limit_volume(codec, ++ "TPA6130A2 Headphone Playback Volume", ++ 54); ++ if (ret < 0) ++ dev_warn(card->dev, "Failed to set TPA6130A2 volume limit: %d\n", ++ ret); ++ kctl = snd_soc_card_get_kcontrol(card, ++ "TPA6130A2 Headphone Playback Volume"); ++ if (kctl) { ++ strcpy(kctl->id.name, "Headphones Playback Volume"); ++ /* disable the volume dB scale so alsamixer works */ ++ kctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE; ++ } ++ ++ kctl = snd_soc_card_get_kcontrol(card, ++ "TPA6130A2 Headphone Playback Switch"); ++ if (kctl) ++ strcpy(kctl->id.name, "Headphones Playback Switch"); ++ } ++ ++ return 0; ++} ++ ++/* set hw parameters */ ++static int snd_rpi_raspidac3_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ unsigned int sample_bits = ++ snd_pcm_format_physical_width(params_format(params)); ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); ++} ++ ++/* startup */ ++static int snd_rpi_raspidac3_startup(struct snd_pcm_substream *substream) { ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08); ++ tpa6130a2_stereo_enable(codec, 1); ++ return 0; ++} ++ ++/* shutdown */ ++static void snd_rpi_raspidac3_shutdown(struct snd_pcm_substream *substream) { ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); ++ tpa6130a2_stereo_enable(codec, 0); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_raspidac3_ops = { ++ .hw_params = snd_rpi_raspidac3_hw_params, ++ .startup = snd_rpi_raspidac3_startup, ++ .shutdown = snd_rpi_raspidac3_shutdown, ++}; ++ ++/* interface setup */ ++static struct snd_soc_dai_link snd_rpi_raspidac3_dai[] = { ++{ ++ .name = "RaspiDAC Rev.3x", ++ .stream_name = "RaspiDAC HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm512x-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm512x.1-004c", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_raspidac3_ops, ++ .init = snd_rpi_raspidac3_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_raspidac3 = { ++ .name = "RaspiDAC Rev.3x HiFi Audio Card", ++ .dai_link = snd_rpi_raspidac3_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_raspidac3_dai), ++}; ++ ++/* sound card test */ ++static int snd_rpi_raspidac3_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_raspidac3.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_raspidac3_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_raspidac3); ++ if (ret) ++ dev_err(&pdev->dev, ++ "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++/* sound card disconnect */ ++static int snd_rpi_raspidac3_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_raspidac3); ++} ++ ++static const struct of_device_id raspidac3_of_match[] = { ++ { .compatible = "jg,raspidacv3", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, raspidac3_of_match); ++ ++/* sound card platform driver */ ++static struct platform_driver snd_rpi_raspidac3_driver = { ++ .driver = { ++ .name = "snd-rpi-raspidac3", ++ .owner = THIS_MODULE, ++ .of_match_table = raspidac3_of_match, ++ }, ++ .probe = snd_rpi_raspidac3_probe, ++ .remove = snd_rpi_raspidac3_remove, ++}; ++ ++module_platform_driver(snd_rpi_raspidac3_driver); ++ ++MODULE_AUTHOR("Jan Grulich "); ++MODULE_DESCRIPTION("ASoC Driver for RaspiDAC Rev.3x"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/brcm2708/patches-4.1/0169-config-Add-SND_SOC_ADAU1701-module.patch b/target/linux/brcm2708/patches-4.1/0169-config-Add-SND_SOC_ADAU1701-module.patch new file mode 100644 index 0000000..e13e50b --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0169-config-Add-SND_SOC_ADAU1701-module.patch @@ -0,0 +1,30 @@ +From 67ab743eaa1c6fc4c82aa7238eb82d0e779869fa Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Tue, 14 Jul 2015 16:55:02 +0100 +Subject: [PATCH 169/203] config: Add SND_SOC_ADAU1701 module + +--- + arch/arm/configs/bcm2709_defconfig | 1 + + arch/arm/configs/bcmrpi_defconfig | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -831,6 +831,7 @@ CONFIG_SND_BCM2708_SOC_RPI_DAC=m + CONFIG_SND_BCM2708_SOC_RPI_PROTO=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m + CONFIG_SND_BCM2708_SOC_RASPIDAC3=m ++CONFIG_SND_SOC_ADAU1701=m + CONFIG_SND_SOC_WM8804_I2C=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -824,6 +824,7 @@ CONFIG_SND_BCM2708_SOC_RPI_DAC=m + CONFIG_SND_BCM2708_SOC_RPI_PROTO=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m + CONFIG_SND_BCM2708_SOC_RASPIDAC3=m ++CONFIG_SND_SOC_ADAU1701=m + CONFIG_SND_SOC_WM8804_I2C=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m diff --git a/target/linux/brcm2708/patches-4.1/0170-vchiq-fix-NULL-pointer-dereference-when-closing-driv.patch b/target/linux/brcm2708/patches-4.1/0170-vchiq-fix-NULL-pointer-dereference-when-closing-driv.patch new file mode 100644 index 0000000..165f276 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0170-vchiq-fix-NULL-pointer-dereference-when-closing-driv.patch @@ -0,0 +1,98 @@ +From d3f5bff6c861a3addea60da69196172f2e6d360c Mon Sep 17 00:00:00 2001 +From: Colin Ian King +Date: Tue, 1 Sep 2015 16:52:34 +0000 +Subject: [PATCH 170/203] vchiq: fix NULL pointer dereference when closing + driver + +The following code run as root will cause a null pointer dereference oops: + + int fd = open("/dev/vc-cma", O_RDONLY); + if (fd < 0) + err(1, "open failed"); + (void)close(fd); + +[ 1704.877721] Unable to handle kernel NULL pointer dereference at virtual address 00000000 +[ 1704.877725] pgd = b899c000 +[ 1704.877736] [00000000] *pgd=37fab831, *pte=00000000, *ppte=00000000 +[ 1704.877748] Internal error: Oops: 817 [#1] PREEMPT SMP ARM +[ 1704.877765] Modules linked in: evdev i2c_bcm2708 uio_pdrv_genirq uio +[ 1704.877774] CPU: 2 PID: 3656 Comm: stress-ng-fstat Not tainted 3.19.1-12-generic-bcm2709 #12-Ubuntu +[ 1704.877777] Hardware name: BCM2709 +[ 1704.877783] task: b8ab9b00 ti: b7e68000 task.ti: b7e68000 +[ 1704.877798] PC is at __down_interruptible+0x50/0xec +[ 1704.877806] LR is at down_interruptible+0x5c/0x68 +[ 1704.877813] pc : [<80630ee8>] lr : [<800704b0>] psr: 60080093 +sp : b7e69e50 ip : b7e69e88 fp : b7e69e84 +[ 1704.877817] r10: b88123c8 r9 : 00000010 r8 : 00000001 +[ 1704.877822] r7 : b8ab9b00 r6 : 7fffffff r5 : 80a1cc34 r4 : 80a1cc34 +[ 1704.877826] r3 : b7e69e50 r2 : 00000000 r1 : 00000000 r0 : 80a1cc34 +[ 1704.877833] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user +[ 1704.877838] Control: 10c5387d Table: 3899c06a DAC: 00000015 +[ 1704.877843] Process do-oops (pid: 3656, stack limit = 0xb7e68238) +[ 1704.877848] Stack: (0xb7e69e50 to 0xb7e6a000) +[ 1704.877856] 9e40: 80a1cc3c 00000000 00000010 b88123c8 +[ 1704.877865] 9e60: b7e69e84 80a1cc34 fff9fee9 ffffffff b7e68000 00000009 b7e69ea4 b7e69e88 +[ 1704.877874] 9e80: 800704b0 80630ea4 fff9fee9 60080013 80a1cc28 fff9fee9 b7e69edc b7e69ea8 +[ 1704.877884] 9ea0: 8040f558 80070460 fff9fee9 ffffffff 00000000 00000000 00000009 80a1cb7c +[ 1704.877893] 9ec0: 00000000 80a1cb7c 00000000 00000010 b7e69ef4 b7e69ee0 803e1ba4 8040f514 +[ 1704.877902] 9ee0: 00000e48 80a1cb7c b7e69f14 b7e69ef8 803e1c9c 803e1b74 b88123c0 b92acb18 +[ 1704.877911] 9f00: b8812790 b8d815d8 b7e69f24 b7e69f18 803e2250 803e1bc8 b7e69f5c b7e69f28 +[ 1704.877921] 9f20: 80167bac 803e222c 00000000 00000000 b7e69f54 b8ab9ffc 00000000 8098c794 +[ 1704.877930] 9f40: b8ab9b00 8000efc4 b7e68000 00000000 b7e69f6c b7e69f60 80167d6c 80167b28 +[ 1704.877939] 9f60: b7e69f8c b7e69f70 80047d38 80167d60 b7e68000 b7e68010 8000efc4 b7e69fb0 +[ 1704.877949] 9f80: b7e69fac b7e69f90 80012820 80047c84 01155490 011549a8 00000001 00000006 +[ 1704.877957] 9fa0: 00000000 b7e69fb0 8000ee5c 80012790 00000000 353d8c0f 7efc4308 00000000 +[ 1704.877966] 9fc0: 01155490 011549a8 00000001 00000006 00000000 00000000 76cf3ba0 00000003 +[ 1704.877975] 9fe0: 00000000 7efc42e4 0002272f 76e2ed66 60080030 00000003 00000000 00000000 +[ 1704.877998] [<80630ee8>] (__down_interruptible) from [<800704b0>] (down_interruptible+0x5c/0x68) +[ 1704.878015] [<800704b0>] (down_interruptible) from [<8040f558>] (vchiu_queue_push+0x50/0xd8) +[ 1704.878032] [<8040f558>] (vchiu_queue_push) from [<803e1ba4>] (send_worker_msg+0x3c/0x54) +[ 1704.878045] [<803e1ba4>] (send_worker_msg) from [<803e1c9c>] (vc_cma_set_reserve+0xe0/0x1c4) +[ 1704.878057] [<803e1c9c>] (vc_cma_set_reserve) from [<803e2250>] (vc_cma_release+0x30/0x38) +[ 1704.878069] [<803e2250>] (vc_cma_release) from [<80167bac>] (__fput+0x90/0x1e0) +[ 1704.878082] [<80167bac>] (__fput) from [<80167d6c>] (____fput+0x18/0x1c) +[ 1704.878094] [<80167d6c>] (____fput) from [<80047d38>] (task_work_run+0xc0/0xf8) +[ 1704.878109] [<80047d38>] (task_work_run) from [<80012820>] (do_work_pending+0x9c/0xc4) +[ 1704.878123] [<80012820>] (do_work_pending) from [<8000ee5c>] (work_pending+0xc/0x20) +[ 1704.878133] Code: e50b1034 e3a01000 e50b2030 e580300c (e5823000) + +..the fix is to ensure that we have actually initialized the queue before we attempt +to push any items onto it. This occurs if we do an open() followed by a close() without +any activity in between. + +Signed-off-by: Colin Ian King +--- + drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c | 4 ++++ + drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h | 1 + + 2 files changed, 5 insertions(+) + +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c +@@ -46,6 +46,7 @@ int vchiu_queue_init(VCHIU_QUEUE_T *queu + queue->size = size; + queue->read = 0; + queue->write = 0; ++ queue->initialized = 1; + + sema_init(&queue->pop, 0); + sema_init(&queue->push, 0); +@@ -76,6 +77,9 @@ int vchiu_queue_is_full(VCHIU_QUEUE_T *q + + void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header) + { ++ if (!queue->initialized) ++ return; ++ + while (queue->write == queue->read + queue->size) { + if (down_interruptible(&queue->pop) != 0) { + flush_signals(current); +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h +@@ -60,6 +60,7 @@ typedef struct { + int size; + int read; + int write; ++ int initialized; + + struct semaphore pop; + struct semaphore push; diff --git a/target/linux/brcm2708/patches-4.1/0171-bcm2708_fb-remove-redundant-code-as-detected-by-stat.patch b/target/linux/brcm2708/patches-4.1/0171-bcm2708_fb-remove-redundant-code-as-detected-by-stat.patch new file mode 100644 index 0000000..ad0f2ec --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0171-bcm2708_fb-remove-redundant-code-as-detected-by-stat.patch @@ -0,0 +1,32 @@ +From 7e5a9f5063a11fcb006c77ee41584b9cc63a79b5 Mon Sep 17 00:00:00 2001 +From: Colin Ian King +Date: Wed, 2 Sep 2015 07:13:17 -0400 +Subject: [PATCH 171/203] bcm2708_fb: remove redundant code as detected by + static analysis + +static analysis with cppcheck detected some redundant code which +should probably be removed: + +[drivers/video/fbdev/bcm2708_fb.c:269]: (style) Variable 'yres' + is assigned a value that is never used. + +Signed-off-by: Colin Ian King +--- + drivers/video/fbdev/bcm2708_fb.c | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/drivers/video/fbdev/bcm2708_fb.c ++++ b/drivers/video/fbdev/bcm2708_fb.c +@@ -263,12 +263,6 @@ static int bcm2708_fb_check_var(struct f + if (var->yoffset > var->yres_virtual - var->yres) + var->yoffset = var->yres_virtual - var->yres - 1; + +- yres = var->yres; +- if (var->vmode & FB_VMODE_DOUBLE) +- yres *= 2; +- else if (var->vmode & FB_VMODE_INTERLACED) +- yres = (yres + 1) / 2; +- + return 0; + } + diff --git a/target/linux/brcm2708/patches-4.1/0172-bcm2708_fb-remove-unnecessary-initialization-of-resu.patch b/target/linux/brcm2708/patches-4.1/0172-bcm2708_fb-remove-unnecessary-initialization-of-resu.patch new file mode 100644 index 0000000..164cbc5 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0172-bcm2708_fb-remove-unnecessary-initialization-of-resu.patch @@ -0,0 +1,29 @@ +From 8a969160370faf8c7b09959ca36456d5f96a64d7 Mon Sep 17 00:00:00 2001 +From: Colin Ian King +Date: Wed, 2 Sep 2015 07:15:38 -0400 +Subject: [PATCH 172/203] bcm2708_fb: remove unnecessary initialization of + result + +static analysis by cppcheck detected an unnecessary initialization +of variable 'result' which is re-assigned almost immediately after +the initialization. Remove the redundant initialization. + +[drivers/video/fbdev/bcm2708_fb.c:406]: (performance) Variable + 'result' is reassigned a value before the old one has been used. + +Signed-off-by: Colin Ian King +--- + drivers/video/fbdev/bcm2708_fb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/video/fbdev/bcm2708_fb.c ++++ b/drivers/video/fbdev/bcm2708_fb.c +@@ -420,7 +420,7 @@ static int bcm2708_fb_blank(int blank_mo + + static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) + { +- s32 result = -1; ++ s32 result; + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + result = bcm2708_fb_set_par(info); diff --git a/target/linux/brcm2708/patches-4.1/0173-vcsm-increment-res_stats-MAP_FAIL-stats-before-we-po.patch b/target/linux/brcm2708/patches-4.1/0173-vcsm-increment-res_stats-MAP_FAIL-stats-before-we-po.patch new file mode 100644 index 0000000..ee09ee4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0173-vcsm-increment-res_stats-MAP_FAIL-stats-before-we-po.patch @@ -0,0 +1,34 @@ +From d3735e837e3102dfee2d2429c8043c9f4c673383 Mon Sep 17 00:00:00 2001 +From: Colin Ian King +Date: Wed, 2 Sep 2015 07:27:36 -0400 +Subject: [PATCH 173/203] vcsm: increment res_stats MAP_FAIL stats before we + potentially release the resource + +resource can be kfree'd when the reference count is zero, so we should +not bump the res_stats of the resource after the vmcs_sm_release_resource +call since the resource may have been kfree'd by this call. Instead, bump +the stats before we call vmcs_sm_release_resource to avoid a potential +NULL pointer derefernce. + +Bug found using cppcheck static analysis: + +[drivers/char/broadcom/vc_sm/vmcs_sm.c:1373]: (error) Dereferencing + 'resource' after it is deallocated / released + +Signed-off-by: Colin Ian King +--- + drivers/char/broadcom/vc_sm/vmcs_sm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/char/broadcom/vc_sm/vmcs_sm.c ++++ b/drivers/char/broadcom/vc_sm/vmcs_sm.c +@@ -1368,8 +1368,8 @@ static int vc_sm_mmap(struct file *file, + return 0; + + error: +- vmcs_sm_release_resource(resource, 0); + resource->res_stats[MAP_FAIL]++; ++ vmcs_sm_release_resource(resource, 0); + return ret; + } + diff --git a/target/linux/brcm2708/patches-4.1/0174-bcm2835-camera-check-for-scene-not-being-found.patch b/target/linux/brcm2708/patches-4.1/0174-bcm2835-camera-check-for-scene-not-being-found.patch new file mode 100644 index 0000000..2365caf --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0174-bcm2835-camera-check-for-scene-not-being-found.patch @@ -0,0 +1,31 @@ +From ebdecd6494e5b67306b5e247180f5d5c4b3d8f27 Mon Sep 17 00:00:00 2001 +From: Colin Ian King +Date: Wed, 2 Sep 2015 07:33:39 -0400 +Subject: [PATCH 174/203] bcm2835: camera: check for scene not being found + +static analysis by cppcheck detected some potential NULL pointer +dereference issues: + +[drivers/media/platform/bcm2835/controls.c:854]: (error) Possible null + pointer dereference: scene + (and lines 858, 859 too) + +it is possible that scene is not found because of an invalue ctrl->val +and is therefore NULL and hence causing a null pointer dereference. + +Signed-off-by: Colin Ian King +--- + drivers/media/platform/bcm2835/controls.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/media/platform/bcm2835/controls.c ++++ b/drivers/media/platform/bcm2835/controls.c +@@ -845,6 +845,8 @@ static int ctrl_set_scene_mode(struct bm + break; + } + } ++ if (!scene) ++ return -EINVAL; + if (i >= ARRAY_SIZE(scene_configs)) + return -EINVAL; + diff --git a/target/linux/brcm2708/patches-4.1/0175-bcm2835-memcpy-port-data-to-m-rather-than-rmsg.patch b/target/linux/brcm2708/patches-4.1/0175-bcm2835-memcpy-port-data-to-m-rather-than-rmsg.patch new file mode 100644 index 0000000..a41d7d8 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0175-bcm2835-memcpy-port-data-to-m-rather-than-rmsg.patch @@ -0,0 +1,25 @@ +From ec31dc882de68b041b6ac36e3de7e17cf256c222 Mon Sep 17 00:00:00 2001 +From: Colin Ian King +Date: Wed, 2 Sep 2015 07:47:51 -0400 +Subject: [PATCH 175/203] bcm2835: memcpy port data to m rather than rmsg + +static analysis by cppcheck detected a memcpy to rmsg which is +not actually initialized at that point. The memcpy should be copying +to variable m instead. + +Signed-off-by: Colin Ian King +--- + drivers/media/platform/bcm2835/mmal-vchiq.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/media/platform/bcm2835/mmal-vchiq.c ++++ b/drivers/media/platform/bcm2835/mmal-vchiq.c +@@ -851,7 +851,7 @@ static int port_info_set(struct vchiq_mm + sizeof(union mmal_es_specific_format)); + + m.u.port_info_set.format.extradata_size = port->format.extradata_size; +- memcpy(rmsg->u.port_info_set.extradata, port->format.extradata, ++ memcpy(&m.u.port_info_set.extradata, port->format.extradata, + port->format.extradata_size); + + ret = send_synchronous_mmal_msg(instance, &m, diff --git a/target/linux/brcm2708/patches-4.1/0176-spi-bcm2835-fix-overflow-in-calculation-of-transfer-.patch b/target/linux/brcm2708/patches-4.1/0176-spi-bcm2835-fix-overflow-in-calculation-of-transfer-.patch new file mode 100644 index 0000000..4e55ba9 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0176-spi-bcm2835-fix-overflow-in-calculation-of-transfer-.patch @@ -0,0 +1,53 @@ +From 6e1447aaad894f45595a45fc52ae5f7dbe072b2e Mon Sep 17 00:00:00 2001 +From: Martin Sperl +Date: Wed, 29 Jul 2015 07:34:10 +0000 +Subject: [PATCH 176/203] spi: bcm2835: fix overflow in calculation of transfer + time + +This resulted in the use of polling mode when other approaches +(dma or interrupts) would have been more appropriate. + +Happened for transfers longer than 477 bytes. + +Reported-by: Noralf Tronnes +Signed-off-by: Martin Sperl +Signed-off-by: Mark Brown +(cherry picked from commit 0122a5183088e3117bb9c8fbe248914efb502f3f) +--- + drivers/spi/spi-bcm2835.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +--- a/drivers/spi/spi-bcm2835.c ++++ b/drivers/spi/spi-bcm2835.c +@@ -480,7 +480,7 @@ static int bcm2835_spi_transfer_one_poll + struct spi_device *spi, + struct spi_transfer *tfr, + u32 cs, +- unsigned long xfer_time_us) ++ unsigned long long xfer_time_us) + { + struct bcm2835_spi *bs = spi_master_get_devdata(master); + unsigned long timeout; +@@ -531,7 +531,8 @@ static int bcm2835_spi_transfer_one(stru + { + struct bcm2835_spi *bs = spi_master_get_devdata(master); + unsigned long spi_hz, clk_hz, cdiv; +- unsigned long spi_used_hz, xfer_time_us; ++ unsigned long spi_used_hz; ++ unsigned long long xfer_time_us; + u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); + + /* set clock */ +@@ -573,9 +574,10 @@ static int bcm2835_spi_transfer_one(stru + bs->rx_len = tfr->len; + + /* calculate the estimated time in us the transfer runs */ +- xfer_time_us = tfr->len ++ xfer_time_us = (unsigned long long)tfr->len + * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ +- * 1000000 / spi_used_hz; ++ * 1000000; ++ do_div(xfer_time_us, spi_used_hz); + + /* for short requests run polling*/ + if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) diff --git a/target/linux/brcm2708/patches-4.1/0177-BCM270X_DT-Add-SDIO-overlay.patch b/target/linux/brcm2708/patches-4.1/0177-BCM270X_DT-Add-SDIO-overlay.patch new file mode 100644 index 0000000..0ffa829 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0177-BCM270X_DT-Add-SDIO-overlay.patch @@ -0,0 +1,80 @@ +From a0adae0d3e1327dfa796986e45bbe20dee335f2c Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 8 Sep 2015 15:14:50 +0100 +Subject: [PATCH 177/203] BCM270X_DT: Add SDIO overlay + +Enable SDIO from MMC interface via GPIOs 22-27. Includes the sdhost +overlay to free up the MMC interface. +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 15 +++++++++++++++ + arch/arm/boot/dts/overlays/sdio-overlay.dts | 29 +++++++++++++++++++++++++++++ + 3 files changed, 45 insertions(+) + create mode 100644 arch/arm/boot/dts/overlays/sdio-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -44,6 +44,7 @@ dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-ove + dtb-$(RPI_DT_OVERLAYS) += rpi-proto-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-sense-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += sdio-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-dma-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -513,6 +513,21 @@ Params: overclock_50 Clock ( + debug Enable debug output (default off) + + ++Name: sdio ++Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock, ++ and enables SDIO via GPIOs 22-27. ++Load: dtoverlay=sdio,= ++Params: overclock_50 Clock (in MHz) to use when the MMC framework ++ requests 50MHz ++ ++ force_pio Disable DMA support (default off) ++ ++ pio_limit Number of blocks above which to use DMA ++ (default 1) ++ ++ debug Enable debug output (default off) ++ ++ + Name: spi-bcm2708 + Info: Selects the bcm2708-spi SPI driver + Load: dtoverlay=spi-bcm2708 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts +@@ -0,0 +1,29 @@ ++/* Enable SDIO from MMC interface via GPIOs 22-27. Includes sdhost overlay. */ ++ ++/include/ "sdhost-overlay.dts" ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@3 { ++ target = <&mmc>; ++ __overlay__ { ++ compatible = "brcm,bcm2835-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio_pins>; ++ non-removable; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&gpio>; ++ __overlay__ { ++ sdio_pins: sdio_pins { ++ brcm,pins = <22 23 24 25 26 27>; ++ brcm,function = <7 7 7 7 7 7>; /* ALT3 = SD1 */ ++ brcm,pull = <0 2 2 2 2 2>; ++ }; ++ }; ++ }; ++}; diff --git a/target/linux/brcm2708/patches-4.1/0178-BCM270X_DT-Use-fixed-factor-clock-for-uart1.patch b/target/linux/brcm2708/patches-4.1/0178-BCM270X_DT-Use-fixed-factor-clock-for-uart1.patch new file mode 100644 index 0000000..54afb54 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0178-BCM270X_DT-Use-fixed-factor-clock-for-uart1.patch @@ -0,0 +1,92 @@ +From 502a751c5b49d0730f25280345d145e26f0b671d Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 11 Sep 2015 09:14:01 +0100 +Subject: [PATCH 178/203] BCM270X_DT: Use fixed-factor-clock for uart1 + +The BCM2835 mini-UART is almost 8250-compatible, but there is +a factor-of-two difference in the clock divider for the baud rate. +The standard 8250 driver can be used unmodified provided we lie to it +about the clock frequency, pretending it is double the actual value. +The mini-UART block shares the core clock, and the current firmware +uses a DT-parameter to update the clock-frequency property. Although it +works, this isn't ideal because it exposes the firmware to a driver +problem. + +This patch uses the fixed-factor-clock module to create a clock that is +always twice the frequency of the core clock. (N.B. These "fixed" clocks +just describe an existing clock, rather than changing any hardware +settings.) +--- + arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 1 - + arch/arm/boot/dts/bcm2708-rpi-b.dts | 1 - + arch/arm/boot/dts/bcm2708-rpi-cm.dts | 1 - + arch/arm/boot/dts/bcm2708_common.dtsi | 10 +++++++++- + arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 1 - + 5 files changed, 9 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +@@ -103,7 +103,6 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; +- uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; +--- a/arch/arm/boot/dts/bcm2708-rpi-b.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts +@@ -97,7 +97,6 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; +- uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; +--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts ++++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +@@ -79,7 +79,6 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; +- uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -165,7 +165,7 @@ + compatible = "brcm,bcm2835-aux-uart", "ns16550"; + reg = <0x7e215040 0x40>; + interrupts = <1 29>; +- clock-frequency = <500000000>; ++ clocks = <&clk_uart1>; + reg-shift = <2>; + no-loopback-test; + status = "disabled"; +@@ -294,6 +294,14 @@ + clock-output-names = "pwm"; + clock-frequency = <100000000>; + }; ++ ++ clk_uart1: clock@6 { ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_core>; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <2>; ++ }; + }; + + __overrides__ { +--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts ++++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +@@ -103,7 +103,6 @@ + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; +- uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; diff --git a/target/linux/brcm2708/patches-4.1/0179-bcm2835-mmc-Don-t-overwrite-MMC-capabilities-from-DT.patch b/target/linux/brcm2708/patches-4.1/0179-bcm2835-mmc-Don-t-overwrite-MMC-capabilities-from-DT.patch new file mode 100644 index 0000000..a32d4e6 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0179-bcm2835-mmc-Don-t-overwrite-MMC-capabilities-from-DT.patch @@ -0,0 +1,23 @@ +From 1e348feeabfbf0b2628162c2b67a89eeebf8ff7d Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 11 Sep 2015 12:10:15 +0100 +Subject: [PATCH 179/203] bcm2835-mmc: Don't overwrite MMC capabilities from DT + +--- + drivers/mmc/host/bcm2835-mmc.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/mmc/host/bcm2835-mmc.c ++++ b/drivers/mmc/host/bcm2835-mmc.c +@@ -1327,8 +1327,9 @@ static int bcm2835_mmc_add_host(struct b + mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; + #endif + /* host controller capabilities */ +- mmc->caps = MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ | +- MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; ++ mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | ++ MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED | ++ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; + + host->flags = SDHCI_AUTO_CMD23; + diff --git a/target/linux/brcm2708/patches-4.1/0180-Revert-BCM270X_DT-mz61581-Revert-to-spi-bcm2708.patch b/target/linux/brcm2708/patches-4.1/0180-Revert-BCM270X_DT-mz61581-Revert-to-spi-bcm2708.patch new file mode 100644 index 0000000..76a88ec --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0180-Revert-BCM270X_DT-mz61581-Revert-to-spi-bcm2708.patch @@ -0,0 +1,28 @@ +From 3f2b85d10c701c544516d6a68d36d52dbf967a08 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Sun, 13 Sep 2015 15:54:28 +0200 +Subject: [PATCH 180/203] Revert "BCM270X_DT: mz61581: Revert to spi-bcm2708" +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This reverts commit 1820cd05d93b2d465d1616202772efe5bf0d11fe. + +The spi-bcm2835 driver has been fixed, so now we can use it again. + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/overlays/mz61581-overlay.dts | 2 -- + 1 file changed, 2 deletions(-) + +--- a/arch/arm/boot/dts/overlays/mz61581-overlay.dts ++++ b/arch/arm/boot/dts/overlays/mz61581-overlay.dts +@@ -12,8 +12,6 @@ + fragment@0 { + target = <&spi0>; + __overlay__ { +- /* does not work with spi-bcm2835 using software chip selects */ +- compatible = "brcm,bcm2708-spi"; + status = "okay"; + + spidev@0{ diff --git a/target/linux/brcm2708/patches-4.1/0181-BCM270X_DT-mz61581-Set-txbuflen-to-32k.patch b/target/linux/brcm2708/patches-4.1/0181-BCM270X_DT-mz61581-Set-txbuflen-to-32k.patch new file mode 100644 index 0000000..076c2a5 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0181-BCM270X_DT-mz61581-Set-txbuflen-to-32k.patch @@ -0,0 +1,47 @@ +From d9273547c2d4f0d79a3d22324dfc0e125754e6e0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= +Date: Sun, 13 Sep 2015 17:17:14 +0200 +Subject: [PATCH 181/203] BCM270X_DT: mz61581: Set txbuflen to 32k +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Because of the spi dma mapping/engine overhead with spi-bcm2835, +txbuflen has to be increased from 4096 to 32768 to maximize +throughput (11MB/s at 128MHz). + +Signed-off-by: Noralf Trønnes +--- + arch/arm/boot/dts/overlays/README | 2 ++ + arch/arm/boot/dts/overlays/mz61581-overlay.dts | 2 ++ + 2 files changed, 4 insertions(+) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -368,6 +368,8 @@ Params: speed Display + + fps Delay between frame updates + ++ txbuflen Transmit buffer length (default 32768) ++ + debug Debug output level {0-7} + + xohms Touchpanel sensitivity (X-plate resistance) +--- a/arch/arm/boot/dts/overlays/mz61581-overlay.dts ++++ b/arch/arm/boot/dts/overlays/mz61581-overlay.dts +@@ -57,6 +57,7 @@ + bgr; + fps = <30>; + buswidth = <8>; ++ txbuflen = <32768>; + + reset-gpios = <&gpio 15 0>; + dc-gpios = <&gpio 25 0>; +@@ -103,6 +104,7 @@ + speed = <&mz61581>, "spi-max-frequency:0"; + rotate = <&mz61581>, "rotate:0"; + fps = <&mz61581>, "fps:0"; ++ txbuflen = <&mz61581>, "txbuflen:0"; + debug = <&mz61581>, "debug:0"; + xohms = <&mz61581_ts>,"ti,x-plate-ohms;0"; + }; diff --git a/target/linux/brcm2708/patches-4.1/0182-backport-spi-bcm2835-BUG-fix-wrong-use-of-PAGE_MASK.patch b/target/linux/brcm2708/patches-4.1/0182-backport-spi-bcm2835-BUG-fix-wrong-use-of-PAGE_MASK.patch new file mode 100644 index 0000000..cbe4b29 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0182-backport-spi-bcm2835-BUG-fix-wrong-use-of-PAGE_MASK.patch @@ -0,0 +1,44 @@ +From 6460bf849143979acff90f3664f78bf3907aad0f Mon Sep 17 00:00:00 2001 +From: Martin Sperl +Date: Thu, 10 Sep 2015 09:32:14 +0000 +Subject: [PATCH 182/203] backport: spi: bcm2835: BUG: fix wrong use of + PAGE_MASK + +There is a bug in the alignment checking of transfers, +that results in DMA not being used for un-aligned +transfers that do not cross page-boundries, which is valid. + +This is due to a missconception of the meaning PAGE_MASK +when implementing that check originally - (PAGE_SIZE - 1) +should have been used instead. + +Also fixes a copy/paste error. + +Reported-by: +Signed-off-by: Martin Sperl +Signed-off-by: Mark Brown +Cc: stable@vger.kernel.org +--- + drivers/spi/spi-bcm2835.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/spi/spi-bcm2835.c ++++ b/drivers/spi/spi-bcm2835.c +@@ -386,14 +386,14 @@ static bool bcm2835_spi_can_dma(struct s + /* otherwise we only allow transfers within the same page + * to avoid wasting time on dma_mapping when it is not practical + */ +- if (((size_t)tfr->tx_buf & PAGE_MASK) + tfr->len > PAGE_SIZE) { ++ if (((size_t)tfr->tx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { + dev_warn_once(&spi->dev, + "Unaligned spi tx-transfer bridging page\n"); + return false; + } +- if (((size_t)tfr->rx_buf & PAGE_MASK) + tfr->len > PAGE_SIZE) { ++ if (((size_t)tfr->rx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { + dev_warn_once(&spi->dev, +- "Unaligned spi tx-transfer bridging page\n"); ++ "Unaligned spi rx-transfer bridging page\n"); + return false; + } + diff --git a/target/linux/brcm2708/patches-4.1/0183-Use-dts-dirs-feature-for-overlays.patch b/target/linux/brcm2708/patches-4.1/0183-Use-dts-dirs-feature-for-overlays.patch new file mode 100644 index 0000000..7fb5603 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0183-Use-dts-dirs-feature-for-overlays.patch @@ -0,0 +1,37 @@ +From a025837fe723648981d68e23e53d3c4d7f270c21 Mon Sep 17 00:00:00 2001 +From: David Lechner +Date: Mon, 14 Sep 2015 19:08:36 -0500 +Subject: [PATCH 183/203] Use dts-dirs feature for overlays. + +The kernel makefiles have a dts-dirs target that is for vendor subdirectories. + +Using this fixes the install_dtbs target, which previously did not install the overlays. +--- + arch/arm/boot/dts/Makefile | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -15,6 +15,9 @@ endif + ifeq ($(CONFIG_ARCH_BCM2835),y) + RPI_DT_OVERLAYS=y + endif ++ifeq ($(RPI_DT_OVERLAYS),y) ++ dts-dirs += overlays ++endif + + dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb +@@ -683,11 +686,10 @@ targets += $(dtb-y) + endif + + always := $(dtb-y) ++subdir-y := $(dts-dirs) + clean-files := *.dtb + + # Enable fixups to support overlays on BCM2708 platforms + ifeq ($(RPI_DT_OVERLAYS),y) + DTC_FLAGS ?= -@ + endif +- +-subdir-y += overlays diff --git a/target/linux/brcm2708/patches-4.1/0188-config-Add-CIFS_DFS_UPCALL-CIFS_ACL-CIFS_SMB2-CIFS_F.patch b/target/linux/brcm2708/patches-4.1/0188-config-Add-CIFS_DFS_UPCALL-CIFS_ACL-CIFS_SMB2-CIFS_F.patch new file mode 100644 index 0000000..90d6b12 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0188-config-Add-CIFS_DFS_UPCALL-CIFS_ACL-CIFS_SMB2-CIFS_F.patch @@ -0,0 +1,37 @@ +From 4d8738a3f5befd5487930f5bbe62eb58cf943823 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Tue, 15 Sep 2015 15:16:24 +0100 +Subject: [PATCH 188/203] config: Add CIFS_DFS_UPCALL, CIFS_ACL, CIFS_SMB2, + CIFS_FSCACHE + +--- + arch/arm/configs/bcm2709_defconfig | 4 ++++ + arch/arm/configs/bcmrpi_defconfig | 4 ++++ + 2 files changed, 8 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -1158,6 +1158,10 @@ CONFIG_CIFS_WEAK_PW_HASH=y + CONFIG_CIFS_UPCALL=y + CONFIG_CIFS_XATTR=y + CONFIG_CIFS_POSIX=y ++CONFIG_CIFS_ACL=y ++CONFIG_CIFS_DFS_UPCALL=y ++CONFIG_CIFS_SMB2=y ++CONFIG_CIFS_FSCACHE=y + CONFIG_9P_FS=m + CONFIG_9P_FS_POSIX_ACL=y + CONFIG_NLS_DEFAULT="utf8" +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -1151,6 +1151,10 @@ CONFIG_CIFS_WEAK_PW_HASH=y + CONFIG_CIFS_UPCALL=y + CONFIG_CIFS_XATTR=y + CONFIG_CIFS_POSIX=y ++CONFIG_CIFS_ACL=y ++CONFIG_CIFS_DFS_UPCALL=y ++CONFIG_CIFS_SMB2=y ++CONFIG_CIFS_FSCACHE=y + CONFIG_9P_FS=m + CONFIG_9P_FS_POSIX_ACL=y + CONFIG_NLS_DEFAULT="utf8" diff --git a/target/linux/brcm2708/patches-4.1/0189-Add-SMI-driver.patch b/target/linux/brcm2708/patches-4.1/0189-Add-SMI-driver.patch new file mode 100644 index 0000000..8678f9a --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0189-Add-SMI-driver.patch @@ -0,0 +1,2028 @@ +From d0576255447f0e2af80396e105f77e4a6fc981e2 Mon Sep 17 00:00:00 2001 +From: Luke Wren +Date: Sat, 5 Sep 2015 01:14:45 +0100 +Subject: [PATCH 189/203] Add SMI driver + +Signed-off-by: Luke Wren +--- + .../bindings/misc/brcm,bcm2835-smi-dev.txt | 17 + + .../devicetree/bindings/misc/brcm,bcm2835-smi.txt | 48 + + arch/arm/boot/dts/bcm2708_common.dtsi | 11 + + arch/arm/boot/dts/overlays/Makefile | 2 + + arch/arm/boot/dts/overlays/smi-dev-overlay.dts | 18 + + arch/arm/boot/dts/overlays/smi-overlay.dts | 37 + + drivers/char/broadcom/Kconfig | 8 + + drivers/char/broadcom/Makefile | 2 +- + drivers/char/broadcom/bcm2835_smi_dev.c | 402 +++++++++ + drivers/misc/Kconfig | 8 + + drivers/misc/Makefile | 1 + + drivers/misc/bcm2835_smi.c | 985 +++++++++++++++++++++ + include/linux/broadcom/bcm2835_smi.h | 391 ++++++++ + 13 files changed, 1929 insertions(+), 1 deletion(-) + create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt + create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt + create mode 100644 arch/arm/boot/dts/overlays/smi-dev-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/smi-overlay.dts + create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c + create mode 100644 drivers/misc/bcm2835_smi.c + create mode 100644 include/linux/broadcom/bcm2835_smi.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt +@@ -0,0 +1,17 @@ ++* Broadcom BCM2835 SMI character device driver. ++ ++SMI or secondary memory interface is a peripheral specific to certain Broadcom ++SOCs, and is helpful for talking to things like parallel-interface displays ++and NAND flashes (in fact, most things with a parallel register interface). ++ ++This driver adds a character device which provides a user-space interface to ++an instance of the SMI driver. ++ ++Required properties: ++- compatible: "brcm,bcm2835-smi-dev" ++- smi_handle: a phandle to the smi node. ++ ++Optional properties: ++- None. ++ ++ +--- /dev/null ++++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt +@@ -0,0 +1,48 @@ ++* Broadcom BCM2835 SMI driver. ++ ++SMI or secondary memory interface is a peripheral specific to certain Broadcom ++SOCs, and is helpful for talking to things like parallel-interface displays ++and NAND flashes (in fact, most things with a parallel register interface). ++ ++Required properties: ++- compatible: "brcm,bcm2835-smi" ++- reg: Should contain location and length of SMI registers and SMI clkman regs ++- interrupts: *the* SMI interrupt. ++- pinctrl-names: should be "default". ++- pinctrl-0: the phandle of the gpio pin node. ++- brcm,smi-clock-source: the clock source for clkman ++- brcm,smi-clock-divisor: the integer clock divisor for clkman ++- dmas: the dma controller phandle and the DREQ number (4 on a 2835) ++- dma-names: the name used by the driver to request its channel. ++ Should be "rx-tx". ++ ++Optional properties: ++- None. ++ ++Examples: ++ ++8 data pin configuration: ++ ++smi: smi@7e600000 { ++ compatible = "brcm,bcm2835-smi"; ++ reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>; ++ interrupts = <2 16>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&smi_pins>; ++ brcm,smi-clock-source = <6>; ++ brcm,smi-clock-divisor = <4>; ++ dmas = <&dma 4>; ++ dma-names = "rx-tx"; ++ ++ status = "okay"; ++}; ++ ++smi_pins: smi_pins { ++ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>; ++ /* Alt 1: SMI */ ++ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>; ++ /* /CS, /WE and /OE are pulled high, as they are ++ generally active low signals */ ++ brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>; ++}; ++ +--- a/arch/arm/boot/dts/bcm2708_common.dtsi ++++ b/arch/arm/boot/dts/bcm2708_common.dtsi +@@ -205,6 +205,17 @@ + status = "disabled"; + }; + ++ smi: smi@7e600000 { ++ compatible = "brcm,bcm2835-smi"; ++ reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>; ++ interrupts = <2 16>; ++ brcm,smi-clock-source = <6>; ++ brcm,smi-clock-divisor = <4>; ++ dmas = <&dma 4>; ++ dma-names = "rx-tx"; ++ status = "disabled"; ++ }; ++ + usb: usb@7e980000 { + compatible = "brcm,bcm2708-usb"; + reg = <0x7e980000 0x10000>, +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -13,6 +13,8 @@ ifeq ($(CONFIG_ARCH_BCM2835),y) + endif + + dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-dev-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/smi-dev-overlay.dts +@@ -0,0 +1,18 @@ ++// Description: Overlay to enable character device interface for SMI. ++// Author: Luke Wren ++ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ fragment@0 { ++ target = <&soc>; ++ __overlay__ { ++ smi_dev { ++ compatible = "brcm,bcm2835-smi-dev"; ++ smi_handle = <&smi>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/smi-overlay.dts +@@ -0,0 +1,37 @@ ++// Description: Overlay to enable the secondary memory interface peripheral ++// Author: Luke Wren ++ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&smi>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&smi_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ smi_pins: smi_pins { ++ /* Don't configure the top two address bits, as ++ these are already used as ID_SD and ID_SC */ ++ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 ++ 16 17 18 19 20 21 22 23 24 25>; ++ /* Alt 0: SMI */ ++ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 ++ 5 5 5 5 5 5 5 5 5>; ++ /* /CS, /WE and /OE are pulled high, as they are ++ generally active low signals */ ++ brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0>; ++ }; ++ }; ++ }; ++}; +--- a/drivers/char/broadcom/Kconfig ++++ b/drivers/char/broadcom/Kconfig +@@ -47,3 +47,11 @@ config BCM2835_DEVGPIOMEM + on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO + register page to the user's pointer. + ++config BCM2835_SMI_DEV ++ tristate "Character device driver for BCM2835 Secondary Memory Interface" ++ depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2835_SMI ++ default m ++ help ++ This driver provides a character device interface (ioctl + read/write) to ++ Broadcom's Secondary Memory interface. The low-level functionality is provided ++ by the SMI driver itself. +--- a/drivers/char/broadcom/Makefile ++++ b/drivers/char/broadcom/Makefile +@@ -4,4 +4,4 @@ obj-$(CONFIG_BCM_VCIO) += vcio.o + obj-$(CONFIG_BCM_VC_SM) += vc_sm/ + + obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o +- ++obj-$(CONFIG_BCM2835_SMI_DEV) += bcm2835_smi_dev.o +--- /dev/null ++++ b/drivers/char/broadcom/bcm2835_smi_dev.c +@@ -0,0 +1,402 @@ ++/** ++ * Character device driver for Broadcom Secondary Memory Interface ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DEVICE_NAME "bcm2835-smi-dev" ++#define DRIVER_NAME "smi-dev-bcm2835" ++#define DEVICE_MINOR 0 ++ ++static struct cdev bcm2835_smi_cdev; ++static dev_t bcm2835_smi_devid; ++static struct class *bcm2835_smi_class; ++static struct device *bcm2835_smi_dev; ++ ++struct bcm2835_smi_dev_instance { ++ struct device *dev; ++}; ++ ++static struct bcm2835_smi_instance *smi_inst; ++static struct bcm2835_smi_dev_instance *inst; ++ ++static const char *const ioctl_names[] = { ++ "READ_SETTINGS", ++ "WRITE_SETTINGS", ++ "ADDRESS" ++}; ++ ++/**************************************************************************** ++* ++* SMI chardev file ops ++* ++***************************************************************************/ ++static long ++bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ long ret = 0; ++ ++ dev_info(inst->dev, "serving ioctl..."); ++ ++ switch (cmd) { ++ case BCM2835_SMI_IOC_GET_SETTINGS:{ ++ struct smi_settings *settings; ++ ++ dev_info(inst->dev, "Reading SMI settings to user."); ++ settings = bcm2835_smi_get_settings_from_regs(smi_inst); ++ if (copy_to_user((void *)arg, settings, ++ sizeof(struct smi_settings))) ++ dev_err(inst->dev, "settings copy failed."); ++ break; ++ } ++ case BCM2835_SMI_IOC_WRITE_SETTINGS:{ ++ struct smi_settings *settings; ++ ++ dev_info(inst->dev, "Setting user's SMI settings."); ++ settings = bcm2835_smi_get_settings_from_regs(smi_inst); ++ if (copy_from_user(settings, (void *)arg, ++ sizeof(struct smi_settings))) ++ dev_err(inst->dev, "settings copy failed."); ++ else ++ bcm2835_smi_set_regs_from_settings(smi_inst); ++ break; ++ } ++ case BCM2835_SMI_IOC_ADDRESS: ++ dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg); ++ bcm2835_smi_set_address(smi_inst, arg); ++ break; ++ default: ++ dev_err(inst->dev, "invalid ioctl cmd: %d", cmd); ++ ret = -ENOTTY; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int bcm2835_smi_open(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ ++ dev_dbg(inst->dev, "SMI device opened."); ++ ++ if (dev != DEVICE_MINOR) { ++ dev_err(inst->dev, ++ "bcm2835_smi_release: Unknown minor device: %d", ++ dev); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static int bcm2835_smi_release(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ ++ if (dev != DEVICE_MINOR) { ++ dev_err(inst->dev, ++ "bcm2835_smi_release: Unknown minor device %d", dev); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static ssize_t dma_bounce_user( ++ enum dma_transfer_direction dma_dir, ++ char __user *user_ptr, ++ size_t count, ++ struct bcm2835_smi_bounce_info *bounce) ++{ ++ int chunk_size; ++ int chunk_no = 0; ++ int count_left = count; ++ ++ while (count_left) { ++ int rv; ++ void *buf; ++ ++ /* Wait for current chunk to complete: */ ++ if (down_timeout(&bounce->callback_sem, ++ msecs_to_jiffies(1000))) { ++ dev_err(inst->dev, "DMA bounce timed out"); ++ count -= (count_left); ++ break; ++ } ++ ++ if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1) ++ dev_err(inst->dev, "WARNING: Ring buffer overflow"); ++ chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? ++ DMA_BOUNCE_BUFFER_SIZE : count_left; ++ buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; ++ if (dma_dir == DMA_DEV_TO_MEM) ++ rv = copy_to_user(user_ptr, buf, chunk_size); ++ else ++ rv = copy_from_user(buf, user_ptr, chunk_size); ++ if (rv) ++ dev_err(inst->dev, "copy_*_user() failed!: %d", rv); ++ user_ptr += chunk_size; ++ count_left -= chunk_size; ++ chunk_no++; ++ } ++ return count; ++} ++ ++static ssize_t ++bcm2835_read_file(struct file *f, char __user *user_ptr, ++ size_t count, loff_t *offs) ++{ ++ int odd_bytes; ++ ++ dev_dbg(inst->dev, "User reading %d bytes from SMI.", count); ++ /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */ ++ if (count > DMA_THRESHOLD_BYTES) ++ odd_bytes = count & 0x3; ++ else ++ odd_bytes = count; ++ count -= odd_bytes; ++ if (count) { ++ struct bcm2835_smi_bounce_info *bounce; ++ ++ count = bcm2835_smi_user_dma(smi_inst, ++ DMA_DEV_TO_MEM, user_ptr, count, ++ &bounce); ++ if (count) ++ count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr, ++ count, bounce); ++ } ++ if (odd_bytes) { ++ /* Read from FIFO directly if not using DMA */ ++ uint8_t buf[DMA_THRESHOLD_BYTES]; ++ ++ bcm2835_smi_read_buf(smi_inst, buf, odd_bytes); ++ if (copy_to_user(user_ptr, buf, odd_bytes)) ++ dev_err(inst->dev, "copy_to_user() failed."); ++ count += odd_bytes; ++ ++ } ++ return count; ++} ++ ++static ssize_t ++bcm2835_write_file(struct file *f, const char __user *user_ptr, ++ size_t count, loff_t *offs) ++{ ++ int odd_bytes; ++ ++ dev_dbg(inst->dev, "User writing %d bytes to SMI.", count); ++ if (count > DMA_THRESHOLD_BYTES) ++ odd_bytes = count & 0x3; ++ else ++ odd_bytes = count; ++ count -= odd_bytes; ++ if (count) { ++ struct bcm2835_smi_bounce_info *bounce; ++ ++ count = bcm2835_smi_user_dma(smi_inst, ++ DMA_MEM_TO_DEV, (char __user *)user_ptr, count, ++ &bounce); ++ if (count) ++ count = dma_bounce_user(DMA_MEM_TO_DEV, ++ (char __user *)user_ptr, ++ count, bounce); ++ } ++ if (odd_bytes) { ++ uint8_t buf[DMA_THRESHOLD_BYTES]; ++ ++ if (copy_from_user(buf, user_ptr, odd_bytes)) ++ dev_err(inst->dev, "copy_from_user() failed."); ++ else ++ bcm2835_smi_write_buf(smi_inst, buf, odd_bytes); ++ count += odd_bytes; ++ } ++ return count; ++} ++ ++static const struct file_operations ++bcm2835_smi_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = bcm2835_smi_ioctl, ++ .open = bcm2835_smi_open, ++ .release = bcm2835_smi_release, ++ .read = bcm2835_read_file, ++ .write = bcm2835_write_file, ++}; ++ ++ ++/**************************************************************************** ++* ++* bcm2835_smi_probe - called when the driver is loaded. ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_dev_probe(struct platform_device *pdev) ++{ ++ int err; ++ void *ptr_err; ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node, *smi_node; ++ ++ if (!node) { ++ dev_err(dev, "No device tree node supplied!"); ++ return -EINVAL; ++ } ++ ++ smi_node = of_parse_phandle(node, "smi_handle", 0); ++ ++ if (!smi_node) { ++ dev_err(dev, "No such property: smi_handle"); ++ return -ENXIO; ++ } ++ ++ smi_inst = bcm2835_smi_get(smi_node); ++ ++ if (!smi_inst) ++ return -EPROBE_DEFER; ++ ++ /* Allocate buffers and instance data */ ++ ++ inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); ++ ++ if (!inst) ++ return -ENOMEM; ++ ++ inst->dev = dev; ++ ++ /* Create character device entries */ ++ ++ err = alloc_chrdev_region(&bcm2835_smi_devid, ++ DEVICE_MINOR, 1, DEVICE_NAME); ++ if (err != 0) { ++ dev_err(inst->dev, "unable to allocate device number"); ++ return -ENOMEM; ++ } ++ cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops); ++ bcm2835_smi_cdev.owner = THIS_MODULE; ++ err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1); ++ if (err != 0) { ++ dev_err(inst->dev, "unable to register device"); ++ err = -ENOMEM; ++ goto failed_cdev_add; ++ } ++ ++ /* Create sysfs entries */ ++ ++ bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME); ++ ptr_err = bcm2835_smi_class; ++ if (IS_ERR(ptr_err)) ++ goto failed_class_create; ++ ++ bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL, ++ bcm2835_smi_devid, NULL, ++ "smi"); ++ ptr_err = bcm2835_smi_dev; ++ if (IS_ERR(ptr_err)) ++ goto failed_device_create; ++ ++ dev_info(inst->dev, "initialised"); ++ ++ return 0; ++ ++failed_device_create: ++ class_destroy(bcm2835_smi_class); ++failed_class_create: ++ cdev_del(&bcm2835_smi_cdev); ++ err = PTR_ERR(ptr_err); ++failed_cdev_add: ++ unregister_chrdev_region(bcm2835_smi_devid, 1); ++ dev_err(dev, "could not load bcm2835_smi_dev"); ++ return err; ++} ++ ++/**************************************************************************** ++* ++* bcm2835_smi_remove - called when the driver is unloaded. ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_dev_remove(struct platform_device *pdev) ++{ ++ device_destroy(bcm2835_smi_class, bcm2835_smi_devid); ++ class_destroy(bcm2835_smi_class); ++ cdev_del(&bcm2835_smi_cdev); ++ unregister_chrdev_region(bcm2835_smi_devid, 1); ++ ++ dev_info(inst->dev, "SMI character dev removed - OK"); ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* Register the driver with device tree ++* ++***************************************************************************/ ++ ++static const struct of_device_id bcm2835_smi_dev_of_match[] = { ++ {.compatible = "brcm,bcm2835-smi-dev",}, ++ { /* sentinel */ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match); ++ ++static struct platform_driver bcm2835_smi_dev_driver = { ++ .probe = bcm2835_smi_dev_probe, ++ .remove = bcm2835_smi_dev_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_smi_dev_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2835_smi_dev_driver); ++ ++MODULE_ALIAS("platform:smi-dev-bcm2835"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION( ++ "Character device driver for BCM2835's secondary memory interface"); ++MODULE_AUTHOR("Luke Wren "); +--- a/drivers/misc/Kconfig ++++ b/drivers/misc/Kconfig +@@ -10,6 +10,14 @@ config SENSORS_LIS3LV02D + select INPUT_POLLDEV + default n + ++config BCM2835_SMI ++ tristate "Broadcom 283x Secondary Memory Interface driver" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ default m ++ help ++ Driver for enabling and using Broadcom's Secondary/Slow Memory Interface. ++ Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h ++ + config AD525X_DPOT + tristate "Analog Devices Digital Potentiometers" + depends on (I2C || SPI) && SYSFS +--- a/drivers/misc/Makefile ++++ b/drivers/misc/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_AD525X_DPOT_SPI) += ad525x_ + obj-$(CONFIG_INTEL_MID_PTI) += pti.o + obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o + obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o ++obj-$(CONFIG_BCM2835_SMI) += bcm2835_smi.o + obj-$(CONFIG_BMP085) += bmp085.o + obj-$(CONFIG_BMP085_I2C) += bmp085-i2c.o + obj-$(CONFIG_BMP085_SPI) += bmp085-spi.o +--- /dev/null ++++ b/drivers/misc/bcm2835_smi.c +@@ -0,0 +1,985 @@ ++/** ++ * Broadcom Secondary Memory Interface driver ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BCM2835_SMI_IMPLEMENTATION ++#include ++ ++#define DRIVER_NAME "smi-bcm2835" ++ ++#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE) ++ ++#define DMA_WRITE_TO_MEM true ++#define DMA_READ_FROM_MEM false ++ ++struct bcm2835_smi_instance { ++ struct device *dev; ++ struct smi_settings settings; ++ __iomem void *smi_regs_ptr, *cm_smi_regs_ptr; ++ dma_addr_t smi_regs_busaddr; ++ ++ struct dma_chan *dma_chan; ++ struct dma_slave_config dma_config; ++ ++ struct bcm2835_smi_bounce_info bounce; ++ ++ struct scatterlist buffer_sgl; ++ ++ int clock_source; ++ int clock_divisor; ++ ++ /* Sometimes we are called into in an atomic context (e.g. by ++ JFFS2 + MTD) so we can't use a mutex */ ++ spinlock_t transaction_lock; ++}; ++ ++/**************************************************************************** ++* ++* SMI clock manager setup ++* ++***************************************************************************/ ++ ++static inline void write_smi_cm_reg(struct bcm2835_smi_instance *inst, ++ u32 val, unsigned reg) ++{ ++ writel(CM_PWD | val, inst->cm_smi_regs_ptr + reg); ++} ++ ++static inline u32 read_smi_cm_reg(struct bcm2835_smi_instance *inst, ++ unsigned reg) ++{ ++ return readl(inst->cm_smi_regs_ptr + reg); ++} ++ ++static void smi_setup_clock(struct bcm2835_smi_instance *inst) ++{ ++ dev_dbg(inst->dev, "Setting up clock..."); ++ /* Disable SMI clock and wait for it to stop. */ ++ write_smi_cm_reg(inst, 0, CM_SMI_CTL); ++ while (read_smi_cm_reg(inst, CM_SMI_CTL) & CM_SMI_CTL_BUSY) ++ ; ++ ++ write_smi_cm_reg(inst, (inst->clock_divisor << CM_SMI_DIV_DIVI_OFFS), ++ CM_SMI_DIV); ++ write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS), ++ CM_SMI_CTL); ++ ++ /* Enable the clock */ ++ write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS) | ++ CM_SMI_CTL_ENAB, CM_SMI_CTL); ++} ++ ++/**************************************************************************** ++* ++* SMI peripheral setup ++* ++***************************************************************************/ ++ ++static inline void write_smi_reg(struct bcm2835_smi_instance *inst, ++ u32 val, unsigned reg) ++{ ++ writel(val, inst->smi_regs_ptr + reg); ++} ++ ++static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg) ++{ ++ return readl(inst->smi_regs_ptr + reg); ++} ++ ++/* Token-paste macro for e.g SMIDSR_RSTROBE -> value of SMIDSR_RSTROBE_MASK */ ++#define _CONCAT(x, y) x##y ++#define CONCAT(x, y) _CONCAT(x, y) ++ ++#define SET_BIT_FIELD(dest, field, bits) ((dest) = \ ++ ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \ ++ CONCAT(field, _MASK))) ++#define GET_BIT_FIELD(src, field) (((src) & \ ++ CONCAT(field, _MASK)) >> CONCAT(field, _OFFS)) ++ ++static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst, ++ const char *label) ++{ ++ dev_err(inst->dev, "SMI context dump: %s", label); ++ dev_err(inst->dev, "SMICS: 0x%08x", read_smi_reg(inst, SMICS)); ++ dev_err(inst->dev, "SMIL: 0x%08x", read_smi_reg(inst, SMIL)); ++ dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0)); ++ dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0)); ++ dev_err(inst->dev, "SMIDC: 0x%08x", read_smi_reg(inst, SMIDC)); ++ dev_err(inst->dev, "SMIFD: 0x%08x", read_smi_reg(inst, SMIFD)); ++ dev_err(inst->dev, " "); ++} ++ ++static inline void smi_dump_context(struct bcm2835_smi_instance *inst) ++{ ++ smi_dump_context_labelled(inst, ""); ++} ++ ++static void smi_get_default_settings(struct bcm2835_smi_instance *inst) ++{ ++ struct smi_settings *settings = &inst->settings; ++ ++ settings->data_width = SMI_WIDTH_16BIT; ++ settings->pack_data = true; ++ ++ settings->read_setup_time = 1; ++ settings->read_hold_time = 1; ++ settings->read_pace_time = 1; ++ settings->read_strobe_time = 3; ++ ++ settings->write_setup_time = settings->read_setup_time; ++ settings->write_hold_time = settings->read_hold_time; ++ settings->write_pace_time = settings->read_pace_time; ++ settings->write_strobe_time = settings->read_strobe_time; ++ ++ settings->dma_enable = true; ++ settings->dma_passthrough_enable = false; ++ settings->dma_read_thresh = 0x01; ++ settings->dma_write_thresh = 0x3f; ++ settings->dma_panic_read_thresh = 0x20; ++ settings->dma_panic_write_thresh = 0x20; ++} ++ ++void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst) ++{ ++ struct smi_settings *settings = &inst->settings; ++ int smidsr_temp = 0, smidsw_temp = 0, smics_temp, ++ smidcs_temp, smidc_temp = 0; ++ ++ spin_lock(&inst->transaction_lock); ++ ++ /* temporarily disable the peripheral: */ ++ smics_temp = read_smi_reg(inst, SMICS); ++ write_smi_reg(inst, 0, SMICS); ++ smidcs_temp = read_smi_reg(inst, SMIDCS); ++ write_smi_reg(inst, 0, SMIDCS); ++ ++ if (settings->pack_data) ++ smics_temp |= SMICS_PXLDAT; ++ else ++ smics_temp &= ~SMICS_PXLDAT; ++ ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width); ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time); ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time); ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time); ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time); ++ write_smi_reg(inst, smidsr_temp, SMIDSR0); ++ ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width); ++ if (settings->data_width == SMI_WIDTH_8BIT) ++ smidsw_temp |= SMIDSW_WSWAP; ++ else ++ smidsw_temp &= ~SMIDSW_WSWAP; ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time); ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time); ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time); ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE, ++ settings->write_strobe_time); ++ write_smi_reg(inst, smidsw_temp, SMIDSW0); ++ ++ SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh); ++ SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh); ++ SET_BIT_FIELD(smidc_temp, SMIDC_PANICR, ++ settings->dma_panic_read_thresh); ++ SET_BIT_FIELD(smidc_temp, SMIDC_PANICW, ++ settings->dma_panic_write_thresh); ++ if (settings->dma_passthrough_enable) { ++ smidc_temp |= SMIDC_DMAP; ++ smidsr_temp |= SMIDSR_RDREQ; ++ write_smi_reg(inst, smidsr_temp, SMIDSR0); ++ smidsw_temp |= SMIDSW_WDREQ; ++ write_smi_reg(inst, smidsw_temp, SMIDSW0); ++ } else ++ smidc_temp &= ~SMIDC_DMAP; ++ if (settings->dma_enable) ++ smidc_temp |= SMIDC_DMAEN; ++ else ++ smidc_temp &= ~SMIDC_DMAEN; ++ ++ write_smi_reg(inst, smidc_temp, SMIDC); ++ ++ /* re-enable (if was previously enabled) */ ++ write_smi_reg(inst, smics_temp, SMICS); ++ write_smi_reg(inst, smidcs_temp, SMIDCS); ++ ++ spin_unlock(&inst->transaction_lock); ++} ++EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings); ++ ++struct smi_settings *bcm2835_smi_get_settings_from_regs ++ (struct bcm2835_smi_instance *inst) ++{ ++ struct smi_settings *settings = &inst->settings; ++ int smidsr, smidsw, smidc; ++ ++ spin_lock(&inst->transaction_lock); ++ ++ smidsr = read_smi_reg(inst, SMIDSR0); ++ smidsw = read_smi_reg(inst, SMIDSW0); ++ smidc = read_smi_reg(inst, SMIDC); ++ ++ settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ? ++ true : false; ++ ++ settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH); ++ settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP); ++ settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD); ++ settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE); ++ settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE); ++ ++ settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP); ++ settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD); ++ settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE); ++ settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE); ++ ++ settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR); ++ settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW); ++ settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR); ++ settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW); ++ settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false; ++ settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false; ++ ++ spin_unlock(&inst->transaction_lock); ++ ++ return settings; ++} ++EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs); ++ ++static inline void smi_set_address(struct bcm2835_smi_instance *inst, ++ unsigned int address) ++{ ++ int smia_temp = 0, smida_temp = 0; ++ ++ SET_BIT_FIELD(smia_temp, SMIA_ADDR, address); ++ SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address); ++ ++ /* Write to both address registers - user doesn't care whether we're ++ doing programmed or direct transfers. */ ++ write_smi_reg(inst, smia_temp, SMIA); ++ write_smi_reg(inst, smida_temp, SMIDA); ++} ++ ++static void smi_setup_regs(struct bcm2835_smi_instance *inst) ++{ ++ ++ dev_dbg(inst->dev, "Initialising SMI registers..."); ++ /* Disable the peripheral if already enabled */ ++ write_smi_reg(inst, 0, SMICS); ++ write_smi_reg(inst, 0, SMIDCS); ++ ++ smi_get_default_settings(inst); ++ bcm2835_smi_set_regs_from_settings(inst); ++ smi_set_address(inst, 0); ++ ++ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS); ++ write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE, ++ SMIDCS); ++} ++ ++/**************************************************************************** ++* ++* Low-level SMI access functions ++* Other modules should use the exported higher-level functions e.g. ++* bcm2835_smi_write_buf() unless they have a good reason to use these ++* ++***************************************************************************/ ++ ++static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst) ++{ ++ int timeout = 0; ++ ++ write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS); ++ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS); ++ /* Make sure things happen in the right order...*/ ++ mb(); ++ while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && ++ ++timeout < 10000) ++ ; ++ if (timeout < 10000) ++ return read_smi_reg(inst, SMIDD); ++ ++ dev_err(inst->dev, ++ "SMI direct read timed out (is the clock set up correctly?)"); ++ return 0; ++} ++ ++static inline void smi_write_single_word(struct bcm2835_smi_instance *inst, ++ uint32_t data) ++{ ++ int timeout = 0; ++ ++ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS); ++ write_smi_reg(inst, data, SMIDD); ++ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START, ++ SMIDCS); ++ ++ while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && ++ ++timeout < 10000) ++ ; ++ if (timeout >= 10000) ++ dev_err(inst->dev, ++ "SMI direct write timed out (is the clock set up correctly?)"); ++} ++ ++/* Initiates a programmed read into the read FIFO. It is up to the caller to ++ * read data from the FIFO - either via paced DMA transfer, ++ * or polling SMICS_RXD to check whether data is available. ++ * SMICS_ACTIVE will go low upon completion. */ ++static void smi_init_programmed_read(struct bcm2835_smi_instance *inst, ++ int num_transfers) ++{ ++ int smics_temp; ++ ++ /* Disable the peripheral: */ ++ smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE); ++ write_smi_reg(inst, smics_temp, SMICS); ++ while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) ++ ; ++ ++ /* Program the transfer count: */ ++ write_smi_reg(inst, num_transfers, SMIL); ++ ++ /* re-enable and start: */ ++ smics_temp |= SMICS_ENABLE; ++ write_smi_reg(inst, smics_temp, SMICS); ++ smics_temp |= SMICS_CLEAR; ++ /* Just to be certain: */ ++ mb(); ++ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) ++ ; ++ write_smi_reg(inst, smics_temp, SMICS); ++ smics_temp |= SMICS_START; ++ write_smi_reg(inst, smics_temp, SMICS); ++} ++ ++/* Initiates a programmed write sequence, using data from the write FIFO. ++ * It is up to the caller to initiate a DMA transfer before calling, ++ * or use another method to keep the write FIFO topped up. ++ * SMICS_ACTIVE will go low upon completion. ++ */ ++static void smi_init_programmed_write(struct bcm2835_smi_instance *inst, ++ int num_transfers) ++{ ++ int smics_temp; ++ ++ /* Disable the peripheral: */ ++ smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; ++ write_smi_reg(inst, smics_temp, SMICS); ++ while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) ++ ; ++ ++ /* Program the transfer count: */ ++ write_smi_reg(inst, num_transfers, SMIL); ++ ++ /* setup, re-enable and start: */ ++ smics_temp |= SMICS_WRITE | SMICS_ENABLE; ++ write_smi_reg(inst, smics_temp, SMICS); ++ smics_temp |= SMICS_START; ++ write_smi_reg(inst, smics_temp, SMICS); ++} ++ ++/* Initiate a read and then poll FIFO for data, reading out as it appears. */ ++static void smi_read_fifo(struct bcm2835_smi_instance *inst, ++ uint32_t *dest, int n_bytes) ++{ ++ if (read_smi_reg(inst, SMICS) & SMICS_RXD) { ++ smi_dump_context_labelled(inst, ++ "WARNING: read FIFO not empty at start of read call."); ++ while (read_smi_reg(inst, SMICS)) ++ ; ++ } ++ ++ /* Dispatch the read: */ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ smi_init_programmed_read(inst, n_bytes); ++ else if (inst->settings.data_width == SMI_WIDTH_16BIT) ++ smi_init_programmed_read(inst, n_bytes / 2); ++ else { ++ dev_err(inst->dev, "Unsupported data width for read."); ++ return; ++ } ++ ++ /* Poll FIFO to keep it empty */ ++ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) ++ if (read_smi_reg(inst, SMICS) & SMICS_RXD) ++ *dest++ = read_smi_reg(inst, SMID); ++ ++ /* Ensure that the FIFO is emptied */ ++ if (read_smi_reg(inst, SMICS) & SMICS_RXD) { ++ int fifo_count; ++ ++ fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD), ++ SMIFD_FCNT); ++ while (fifo_count--) ++ *dest++ = read_smi_reg(inst, SMID); ++ } ++ ++ if (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) ++ smi_dump_context_labelled(inst, ++ "WARNING: transaction finished but done bit not set."); ++ ++ if (read_smi_reg(inst, SMICS) & SMICS_RXD) ++ smi_dump_context_labelled(inst, ++ "WARNING: read FIFO not empty at end of read call."); ++ ++} ++ ++/* Initiate a write, and then keep the FIFO topped up. */ ++static void smi_write_fifo(struct bcm2835_smi_instance *inst, ++ uint32_t *src, int n_bytes) ++{ ++ int i, timeout = 0; ++ ++ /* Empty FIFOs if not already so */ ++ if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) { ++ smi_dump_context_labelled(inst, ++ "WARNING: write fifo not empty at start of write call."); ++ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR, ++ SMICS); ++ } ++ ++ /* Initiate the transfer */ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ smi_init_programmed_write(inst, n_bytes); ++ else if (inst->settings.data_width == SMI_WIDTH_16BIT) ++ smi_init_programmed_write(inst, n_bytes / 2); ++ else { ++ dev_err(inst->dev, "Unsupported data width for write."); ++ return; ++ } ++ /* Fill the FIFO: */ ++ for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) { ++ while (!(read_smi_reg(inst, SMICS) & SMICS_TXD)) ++ ; ++ write_smi_reg(inst, *src++, SMID); ++ } ++ /* Busy wait... */ ++ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout < ++ 1000000) ++ ; ++ if (timeout >= 1000000) ++ smi_dump_context_labelled(inst, ++ "Timed out on write operation!"); ++ if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) ++ smi_dump_context_labelled(inst, ++ "WARNING: FIFO not empty at end of write operation."); ++} ++ ++/**************************************************************************** ++* ++* SMI DMA operations ++* ++***************************************************************************/ ++ ++/* Disable SMI and put it into the correct direction before doing DMA setup. ++ Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */ ++static void smi_disable(struct bcm2835_smi_instance *inst, ++ enum dma_transfer_direction direction) ++{ ++ int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; ++ ++ if (direction == DMA_DEV_TO_MEM) ++ smics_temp &= ~SMICS_WRITE; ++ else ++ smics_temp |= SMICS_WRITE; ++ write_smi_reg(inst, smics_temp, SMICS); ++ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) ++ ; ++} ++ ++static struct scatterlist *smi_scatterlist_from_buffer( ++ struct bcm2835_smi_instance *inst, ++ dma_addr_t buf, ++ size_t len, ++ struct scatterlist *sg) ++{ ++ sg_init_table(sg, 1); ++ sg_dma_address(sg) = buf; ++ sg_dma_len(sg) = len; ++ return sg; ++} ++ ++static void smi_dma_callback_user_copy(void *param) ++{ ++ /* Notify the bottom half that a chunk is ready for user copy */ ++ struct bcm2835_smi_instance *inst = ++ (struct bcm2835_smi_instance *)param; ++ ++ up(&inst->bounce.callback_sem); ++} ++ ++/* Creates a descriptor, assigns the given callback, and submits the ++ descriptor to dmaengine. Does not block - can queue up multiple ++ descriptors and then wait for them all to complete. ++ sg_len is the number of control blocks, NOT the number of bytes. ++ dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM. ++ callback can be NULL - in this case it is not called. */ ++static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl( ++ struct bcm2835_smi_instance *inst, ++ struct scatterlist *sgl, ++ size_t sg_len, ++ enum dma_transfer_direction dir, ++ dma_async_tx_callback callback) ++{ ++ struct dma_async_tx_descriptor *desc; ++ ++ desc = dmaengine_prep_slave_sg(inst->dma_chan, ++ sgl, ++ sg_len, ++ dir, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK | ++ DMA_PREP_FENCE); ++ if (!desc) { ++ dev_err(inst->dev, "read_sgl: dma slave preparation failed!"); ++ write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE, ++ SMICS); ++ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) ++ cpu_relax(); ++ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE, ++ SMICS); ++ return NULL; ++ } ++ desc->callback = callback; ++ desc->callback_param = inst; ++ if (dmaengine_submit(desc) < 0) ++ return NULL; ++ return desc; ++} ++ ++/* NB this function blocks until the transfer is complete */ ++static void ++smi_dma_read_sgl(struct bcm2835_smi_instance *inst, ++ struct scatterlist *sgl, size_t sg_len, size_t n_bytes) ++{ ++ struct dma_async_tx_descriptor *desc; ++ ++ /* Disable SMI and set to read before dispatching DMA - if SMI is in ++ * write mode and TX fifo is empty, it will generate a DREQ which may ++ * cause the read DMA to complete before the SMI read command is even ++ * dispatched! We want to dispatch DMA before SMI read so that reading ++ * is gapless, for logic analyser. ++ */ ++ ++ smi_disable(inst, DMA_DEV_TO_MEM); ++ ++ desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL); ++ dma_async_issue_pending(inst->dma_chan); ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ smi_init_programmed_read(inst, n_bytes); ++ else ++ smi_init_programmed_read(inst, n_bytes / 2); ++ ++ if (dma_wait_for_async_tx(desc) == DMA_ERROR) ++ smi_dump_context_labelled(inst, "DMA timeout!"); ++} ++ ++static void ++smi_dma_write_sgl(struct bcm2835_smi_instance *inst, ++ struct scatterlist *sgl, size_t sg_len, size_t n_bytes) ++{ ++ struct dma_async_tx_descriptor *desc; ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ smi_init_programmed_write(inst, n_bytes); ++ else ++ smi_init_programmed_write(inst, n_bytes / 2); ++ ++ desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL); ++ dma_async_issue_pending(inst->dma_chan); ++ ++ if (dma_wait_for_async_tx(desc) == DMA_ERROR) ++ smi_dump_context_labelled(inst, "DMA timeout!"); ++ else ++ /* Wait for SMI to finish our writes */ ++ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) ++ cpu_relax(); ++} ++ ++ssize_t bcm2835_smi_user_dma( ++ struct bcm2835_smi_instance *inst, ++ enum dma_transfer_direction dma_dir, ++ char __user *user_ptr, size_t count, ++ struct bcm2835_smi_bounce_info **bounce) ++{ ++ int chunk_no = 0, chunk_size, count_left = count; ++ struct scatterlist *sgl; ++ void (*init_trans_func)(struct bcm2835_smi_instance *, int); ++ ++ spin_lock(&inst->transaction_lock); ++ ++ if (dma_dir == DMA_DEV_TO_MEM) ++ init_trans_func = smi_init_programmed_read; ++ else ++ init_trans_func = smi_init_programmed_write; ++ ++ smi_disable(inst, dma_dir); ++ ++ sema_init(&inst->bounce.callback_sem, 0); ++ if (bounce) ++ *bounce = &inst->bounce; ++ while (count_left) { ++ chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? ++ DMA_BOUNCE_BUFFER_SIZE : count_left; ++ if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) { ++ sgl = ++ &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; ++ } else { ++ sgl = smi_scatterlist_from_buffer( ++ inst, ++ inst->bounce.phys[ ++ chunk_no % DMA_BOUNCE_BUFFER_COUNT], ++ chunk_size, ++ &inst->buffer_sgl); ++ } ++ ++ if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir, ++ smi_dma_callback_user_copy ++ )) { ++ dev_err(inst->dev, "sgl submit failed"); ++ count = 0; ++ goto out; ++ } ++ count_left -= chunk_size; ++ chunk_no++; ++ } ++ dma_async_issue_pending(inst->dma_chan); ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ init_trans_func(inst, count); ++ else if (inst->settings.data_width == SMI_WIDTH_16BIT) ++ init_trans_func(inst, count / 2); ++out: ++ spin_unlock(&inst->transaction_lock); ++ return count; ++} ++EXPORT_SYMBOL(bcm2835_smi_user_dma); ++ ++ ++/**************************************************************************** ++* ++* High level buffer transfer functions - for use by other drivers ++* ++***************************************************************************/ ++ ++/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */ ++void bcm2835_smi_write_buf( ++ struct bcm2835_smi_instance *inst, ++ const void *buf, size_t n_bytes) ++{ ++ int odd_bytes = n_bytes & 0x3; ++ ++ n_bytes -= odd_bytes; ++ ++ spin_lock(&inst->transaction_lock); ++ ++ if (n_bytes > DMA_THRESHOLD_BYTES) { ++ dma_addr_t phy_addr = dma_map_single( ++ inst->dev, ++ (void *)buf, ++ n_bytes, ++ DMA_MEM_TO_DEV); ++ struct scatterlist *sgl = ++ smi_scatterlist_from_buffer(inst, phy_addr, n_bytes, ++ &inst->buffer_sgl); ++ ++ if (!sgl) { ++ smi_dump_context_labelled(inst, ++ "Error: could not create scatterlist for write!"); ++ goto out; ++ } ++ smi_dma_write_sgl(inst, sgl, 1, n_bytes); ++ ++ dma_unmap_single ++ (inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV); ++ } else if (n_bytes) { ++ smi_write_fifo(inst, (uint32_t *) buf, n_bytes); ++ } ++ buf += n_bytes; ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) { ++ while (odd_bytes--) ++ smi_write_single_word(inst, *(uint8_t *) (buf++)); ++ } else { ++ while (odd_bytes >= 2) { ++ smi_write_single_word(inst, *(uint16_t *)buf); ++ buf += 2; ++ odd_bytes -= 2; ++ } ++ if (odd_bytes) { ++ /* Reading an odd number of bytes on a 16 bit bus is ++ a user bug. It's kinder to fail early and tell them ++ than to e.g. transparently give them the bottom byte ++ of a 16 bit transfer. */ ++ dev_err(inst->dev, ++ "WARNING: odd number of bytes specified for wide transfer."); ++ dev_err(inst->dev, ++ "At least one byte dropped as a result."); ++ dump_stack(); ++ } ++ } ++out: ++ spin_unlock(&inst->transaction_lock); ++} ++EXPORT_SYMBOL(bcm2835_smi_write_buf); ++ ++void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst, ++ void *buf, size_t n_bytes) ++{ ++ ++ /* SMI is inherently 32-bit, which causes surprising amounts of mess ++ for bytes % 4 != 0. Easiest to avoid this mess altogether ++ by handling remainder separately. */ ++ int odd_bytes = n_bytes & 0x3; ++ ++ spin_lock(&inst->transaction_lock); ++ n_bytes -= odd_bytes; ++ if (n_bytes > DMA_THRESHOLD_BYTES) { ++ dma_addr_t phy_addr = dma_map_single(inst->dev, ++ buf, n_bytes, ++ DMA_DEV_TO_MEM); ++ struct scatterlist *sgl = smi_scatterlist_from_buffer( ++ inst, phy_addr, n_bytes, ++ &inst->buffer_sgl); ++ if (!sgl) { ++ smi_dump_context_labelled(inst, ++ "Error: could not create scatterlist for read!"); ++ goto out; ++ } ++ smi_dma_read_sgl(inst, sgl, 1, n_bytes); ++ dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM); ++ } else if (n_bytes) { ++ smi_read_fifo(inst, (uint32_t *)buf, n_bytes); ++ } ++ buf += n_bytes; ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) { ++ while (odd_bytes--) ++ *((uint8_t *) (buf++)) = smi_read_single_word(inst); ++ } else { ++ while (odd_bytes >= 2) { ++ *(uint16_t *) buf = smi_read_single_word(inst); ++ buf += 2; ++ odd_bytes -= 2; ++ } ++ if (odd_bytes) { ++ dev_err(inst->dev, ++ "WARNING: odd number of bytes specified for wide transfer."); ++ dev_err(inst->dev, ++ "At least one byte dropped as a result."); ++ dump_stack(); ++ } ++ } ++out: ++ spin_unlock(&inst->transaction_lock); ++} ++EXPORT_SYMBOL(bcm2835_smi_read_buf); ++ ++void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst, ++ unsigned int address) ++{ ++ spin_lock(&inst->transaction_lock); ++ smi_set_address(inst, address); ++ spin_unlock(&inst->transaction_lock); ++} ++EXPORT_SYMBOL(bcm2835_smi_set_address); ++ ++struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node) ++{ ++ struct platform_device *pdev; ++ ++ if (!node) ++ return NULL; ++ ++ pdev = of_find_device_by_node(node); ++ if (!pdev) ++ return NULL; ++ ++ return platform_get_drvdata(pdev); ++} ++EXPORT_SYMBOL(bcm2835_smi_get); ++ ++/**************************************************************************** ++* ++* bcm2835_smi_probe - called when the driver is loaded. ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst) ++{ ++ int i, rv = 0; ++ ++ inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx"); ++ ++ inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID; ++ inst->dma_config.dst_addr = inst->dma_config.src_addr; ++ /* Direction unimportant - always overridden by prep_slave_sg */ ++ inst->dma_config.direction = DMA_DEV_TO_MEM; ++ dmaengine_slave_config(inst->dma_chan, &inst->dma_config); ++ /* Alloc and map bounce buffers */ ++ for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) { ++ inst->bounce.buffer[i] = ++ dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE, ++ &inst->bounce.phys[i], ++ GFP_KERNEL); ++ if (!inst->bounce.buffer[i]) { ++ dev_err(inst->dev, "Could not allocate buffer!"); ++ rv = -ENOMEM; ++ break; ++ } ++ smi_scatterlist_from_buffer( ++ inst, ++ inst->bounce.phys[i], ++ DMA_BOUNCE_BUFFER_SIZE, ++ &inst->bounce.sgl[i] ++ ); ++ } ++ ++ return rv; ++} ++ ++static int bcm2835_smi_probe(struct platform_device *pdev) ++{ ++ int err; ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct resource *ioresource; ++ struct bcm2835_smi_instance *inst; ++ ++ /* Allocate buffers and instance data */ ++ ++ inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance), ++ GFP_KERNEL); ++ ++ if (!inst) ++ return -ENOMEM; ++ ++ inst->dev = dev; ++ spin_lock_init(&inst->transaction_lock); ++ ++ /* We require device tree support */ ++ if (!node) ++ return -EINVAL; ++ ++ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource); ++ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ inst->cm_smi_regs_ptr = devm_ioremap_resource(dev, ioresource); ++ inst->smi_regs_busaddr = be32_to_cpu( ++ *of_get_address(node, 0, NULL, NULL)); ++ of_property_read_u32(node, ++ "brcm,smi-clock-source", ++ &inst->clock_source); ++ of_property_read_u32(node, ++ "brcm,smi-clock-divisor", ++ &inst->clock_divisor); ++ ++ err = bcm2835_smi_dma_setup(inst); ++ if (err) ++ return err; ++ ++ /* Finally, do peripheral setup */ ++ ++ smi_setup_clock(inst); ++ smi_setup_regs(inst); ++ ++ platform_set_drvdata(pdev, inst); ++ ++ dev_info(inst->dev, "initialised"); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* bcm2835_smi_remove - called when the driver is unloaded. ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev); ++ struct device *dev = inst->dev; ++ ++ dev_info(dev, "SMI device removed - OK"); ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* Register the driver with device tree ++* ++***************************************************************************/ ++ ++static const struct of_device_id bcm2835_smi_of_match[] = { ++ {.compatible = "brcm,bcm2835-smi",}, ++ { /* sentinel */ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match); ++ ++static struct platform_driver bcm2835_smi_driver = { ++ .probe = bcm2835_smi_probe, ++ .remove = bcm2835_smi_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_smi_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2835_smi_driver); ++ ++MODULE_ALIAS("platform:smi-bcm2835"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface"); ++MODULE_AUTHOR("Luke Wren "); +--- /dev/null ++++ b/include/linux/broadcom/bcm2835_smi.h +@@ -0,0 +1,391 @@ ++/** ++ * Declarations and definitions for Broadcom's Secondary Memory Interface ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef BCM2835_SMI_H ++#define BCM2835_SMI_H ++ ++#include ++ ++#ifndef __KERNEL__ ++#include ++#include ++#endif ++ ++#define BCM2835_SMI_IOC_MAGIC 0x1 ++#define BCM2835_SMI_INVALID_HANDLE (~0) ++ ++/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */ ++#define BCM2835_SMI_IOC_GET_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 0) ++#define BCM2835_SMI_IOC_WRITE_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 1) ++#define BCM2835_SMI_IOC_ADDRESS _IO(BCM2835_SMI_IOC_MAGIC, 2) ++#define BCM2835_SMI_IOC_MAX 2 ++ ++#define SMI_WIDTH_8BIT 0 ++#define SMI_WIDTH_16BIT 1 ++#define SMI_WIDTH_9BIT 2 ++#define SMI_WIDTH_18BIT 3 ++ ++/* max number of bytes where DMA will not be used */ ++#define DMA_THRESHOLD_BYTES 128 ++#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2) ++#define DMA_BOUNCE_BUFFER_COUNT 3 ++ ++ ++struct smi_settings { ++ int data_width; ++ /* Whether or not to pack multiple SMI transfers into a ++ single 32 bit FIFO word */ ++ bool pack_data; ++ ++ /* Timing for reads (writes the same but for WE) ++ * ++ * OE ----------+ +-------------------- ++ * | | ++ * +----------+ ++ * SD -<==============================>----------- ++ * SA -<=========================================>- ++ * <-setup-> <-strobe -> <-hold -> <- pace -> ++ */ ++ ++ int read_setup_time; ++ int read_hold_time; ++ int read_pace_time; ++ int read_strobe_time; ++ ++ int write_setup_time; ++ int write_hold_time; ++ int write_pace_time; ++ int write_strobe_time; ++ ++ bool dma_enable; /* DREQs */ ++ bool dma_passthrough_enable; /* External DREQs */ ++ int dma_read_thresh; ++ int dma_write_thresh; ++ int dma_panic_read_thresh; ++ int dma_panic_write_thresh; ++}; ++ ++/**************************************************************************** ++* ++* Declare exported SMI functions ++* ++***************************************************************************/ ++ ++#ifdef __KERNEL__ ++ ++#include /* for enum dma_transfer_direction */ ++#include ++#include ++ ++struct bcm2835_smi_instance; ++ ++struct bcm2835_smi_bounce_info { ++ struct semaphore callback_sem; ++ void *buffer[DMA_BOUNCE_BUFFER_COUNT]; ++ dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT]; ++ struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT]; ++}; ++ ++ ++void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *); ++ ++struct smi_settings *bcm2835_smi_get_settings_from_regs( ++ struct bcm2835_smi_instance *inst); ++ ++void bcm2835_smi_write_buf( ++ struct bcm2835_smi_instance *inst, ++ const void *buf, ++ size_t n_bytes); ++ ++void bcm2835_smi_read_buf( ++ struct bcm2835_smi_instance *inst, ++ void *buf, ++ size_t n_bytes); ++ ++void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst, ++ unsigned int address); ++ ++ssize_t bcm2835_smi_user_dma( ++ struct bcm2835_smi_instance *inst, ++ enum dma_transfer_direction dma_dir, ++ char __user *user_ptr, ++ size_t count, ++ struct bcm2835_smi_bounce_info **bounce); ++ ++struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node); ++ ++#endif /* __KERNEL__ */ ++ ++/**************************************************************** ++* ++* Implementation-only declarations ++* ++****************************************************************/ ++ ++#ifdef BCM2835_SMI_IMPLEMENTATION ++ ++/* Clock manager registers for SMI clock: */ ++#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0) ++/* Clock manager "password" to protect registers from spurious writes */ ++#define CM_PWD (0x5a << 24) ++ ++#define CM_SMI_CTL 0x00 ++#define CM_SMI_DIV 0x04 ++ ++#define CM_SMI_CTL_FLIP (1 << 8) ++#define CM_SMI_CTL_BUSY (1 << 7) ++#define CM_SMI_CTL_KILL (1 << 5) ++#define CM_SMI_CTL_ENAB (1 << 4) ++#define CM_SMI_CTL_SRC_MASK (0xf) ++#define CM_SMI_CTL_SRC_OFFS (0) ++ ++#define CM_SMI_DIV_DIVI_MASK (0xf << 12) ++#define CM_SMI_DIV_DIVI_OFFS (12) ++#define CM_SMI_DIV_DIVF_MASK (0xff << 4) ++#define CM_SMI_DIV_DIVF_OFFS (4) ++ ++/* SMI register mapping:*/ ++#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000) ++ ++#define SMICS 0x00 /* control + status register */ ++#define SMIL 0x04 /* length/count (n external txfers) */ ++#define SMIA 0x08 /* address register */ ++#define SMID 0x0c /* data register */ ++#define SMIDSR0 0x10 /* device 0 read settings */ ++#define SMIDSW0 0x14 /* device 0 write settings */ ++#define SMIDSR1 0x18 /* device 1 read settings */ ++#define SMIDSW1 0x1c /* device 1 write settings */ ++#define SMIDSR2 0x20 /* device 2 read settings */ ++#define SMIDSW2 0x24 /* device 2 write settings */ ++#define SMIDSR3 0x28 /* device 3 read settings */ ++#define SMIDSW3 0x2c /* device 3 write settings */ ++#define SMIDC 0x30 /* DMA control registers */ ++#define SMIDCS 0x34 /* direct control/status register */ ++#define SMIDA 0x38 /* direct address register */ ++#define SMIDD 0x3c /* direct data registers */ ++#define SMIFD 0x40 /* FIFO debug register */ ++ ++ ++ ++/* Control and Status register bits: ++ * SMICS_RXF : RX fifo full: 1 when RX fifo is full ++ * SMICS_TXE : TX fifo empty: 1 when empty. ++ * SMICS_RXD : RX fifo contains data: 1 when there is data. ++ * SMICS_TXD : TX fifo can accept data: 1 when true. ++ * SMICS_RXR : RX fifo needs reading: 1 when fifo more than 3/4 full, or ++ * when "DONE" and fifo not emptied. ++ * SMICS_TXW : TX fifo needs writing: 1 when less than 1/4 full. ++ * SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written ++ * when full. Write 1 to clear. ++ * SMICS_EDREQ : 1 when external DREQ received. ++ * SMICS_PXLDAT : Pixel data: write 1 to enable pixel transfer modes. ++ * SMICS_SETERR : 1 if there was an error writing to setup regs (e.g. ++ * tx was in progress). Write 1 to clear. ++ * SMICS_PVMODE : Set to 1 to enable pixel valve mode. ++ * SMICS_INTR : Set to 1 to enable interrupt on RX. ++ * SMICS_INTT : Set to 1 to enable interrupt on TX. ++ * SMICS_INTD : Set to 1 to enable interrupt on DONE condition. ++ * SMICS_TEEN : Tear effect mode enabled: Programmed transfers will wait ++ * for a TE trigger before writing. ++ * SMICS_PAD1 : Padding settings for external transfers. For writes: the ++ * number of bytes initially written to the TX fifo that ++ * SMICS_PAD0 : should be ignored. For reads: the number of bytes that will ++ * be read before the data, and should be dropped. ++ * SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read ++ * SMICS_CLEAR : Write 1 to clear the FIFOs. ++ * SMICS_START : Write 1 to start the programmed transfer. ++ * SMICS_ACTIVE : Reads as 1 when a programmed transfer is underway. ++ * SMICS_DONE : Reads as 1 when transfer finished. For RX, not set until ++ * FIFO emptied. ++ * SMICS_ENABLE : Set to 1 to enable the SMI peripheral, 0 to disable. ++ */ ++ ++#define SMICS_RXF (1 << 31) ++#define SMICS_TXE (1 << 30) ++#define SMICS_RXD (1 << 29) ++#define SMICS_TXD (1 << 28) ++#define SMICS_RXR (1 << 27) ++#define SMICS_TXW (1 << 26) ++#define SMICS_AFERR (1 << 25) ++#define SMICS_EDREQ (1 << 15) ++#define SMICS_PXLDAT (1 << 14) ++#define SMICS_SETERR (1 << 13) ++#define SMICS_PVMODE (1 << 12) ++#define SMICS_INTR (1 << 11) ++#define SMICS_INTT (1 << 10) ++#define SMICS_INTD (1 << 9) ++#define SMICS_TEEN (1 << 8) ++#define SMICS_PAD1 (1 << 7) ++#define SMICS_PAD0 (1 << 6) ++#define SMICS_WRITE (1 << 5) ++#define SMICS_CLEAR (1 << 4) ++#define SMICS_START (1 << 3) ++#define SMICS_ACTIVE (1 << 2) ++#define SMICS_DONE (1 << 1) ++#define SMICS_ENABLE (1 << 0) ++ ++/* Address register bits: */ ++ ++#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8)) ++#define SMIA_DEVICE_OFFS (8) ++#define SMIA_ADDR_MASK (0x3f) /* bits 5 -> 0 */ ++#define SMIA_ADDR_OFFS (0) ++ ++/* DMA control register bits: ++ * SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued. ++ * SMIDC_DMAP : DMA passthrough: when set to 0, top two data pins are used by ++ * SMI as usual. When set to 1, the top two pins are used for ++ * external DREQs: pin 16 read request, 17 write. ++ * SMIDC_PANIC* : Threshold at which DMA will panic during read/write. ++ * SMIDC_REQ* : Threshold at which DMA will generate a DREQ. ++ */ ++ ++#define SMIDC_DMAEN (1 << 28) ++#define SMIDC_DMAP (1 << 24) ++#define SMIDC_PANICR_MASK (0x3f << 18) ++#define SMIDC_PANICR_OFFS (18) ++#define SMIDC_PANICW_MASK (0x3f << 12) ++#define SMIDC_PANICW_OFFS (12) ++#define SMIDC_REQR_MASK (0x3f << 6) ++#define SMIDC_REQR_OFFS (6) ++#define SMIDC_REQW_MASK (0x3f) ++#define SMIDC_REQW_OFFS (0) ++ ++/* Device settings register bits: same for all 4 (or 3?) device register sets. ++ * Device read settings: ++ * SMIDSR_RWIDTH : Read transfer width. 00 = 8bit, 01 = 16bit, ++ * 10 = 18bit, 11 = 9bit. ++ * SMIDSR_RSETUP : Read setup time: number of core cycles between chip ++ * select/address and read strobe. Min 1, max 64. ++ * SMIDSR_MODE68 : 1 for System 68 mode (i.e. enable + direction pins, ++ * rather than OE + WE pin) ++ * SMIDSR_FSETUP : If set to 1, setup time only applies to first ++ * transfer after address change. ++ * SMIDSR_RHOLD : Number of core cycles between read strobe going ++ * inactive and CS/address going inactive. Min 1, max 64 ++ * SMIDSR_RPACEALL : When set to 1, this device's RPACE value will always ++ * be used for the next transaction, even if it is not ++ * to this device. ++ * SMIDSR_RPACE : Number of core cycles spent waiting between CS ++ * deassert and start of next transfer. Min 1, max 128 ++ * SMIDSR_RDREQ : 1 = use external DMA request on SD16 to pace reads ++ * from device. Must also set DMAP in SMICS. ++ * SMIDSR_RSTROBE : Number of cycles to assert the read strobe. ++ * min 1, max 128. ++ */ ++#define SMIDSR_RWIDTH_MASK ((1<<31)|(1<<30)) ++#define SMIDSR_RWIDTH_OFFS (30) ++#define SMIDSR_RSETUP_MASK (0x3f << 24) ++#define SMIDSR_RSETUP_OFFS (24) ++#define SMIDSR_MODE68 (1 << 23) ++#define SMIDSR_FSETUP (1 << 22) ++#define SMIDSR_RHOLD_MASK (0x3f << 16) ++#define SMIDSR_RHOLD_OFFS (16) ++#define SMIDSR_RPACEALL (1 << 15) ++#define SMIDSR_RPACE_MASK (0x7f << 8) ++#define SMIDSR_RPACE_OFFS (8) ++#define SMIDSR_RDREQ (1 << 7) ++#define SMIDSR_RSTROBE_MASK (0x7f) ++#define SMIDSR_RSTROBE_OFFS (0) ++ ++/* Device write settings: ++ * SMIDSW_WWIDTH : Write transfer width. 00 = 8bit, 01 = 16bit, ++ * 10= 18bit, 11 = 9bit. ++ * SMIDSW_WSETUP : Number of cycles between CS assert and write strobe. ++ * Min 1, max 64. ++ * SMIDSW_WFORMAT : Pixel format of input. 0 = 16bit RGB 565, ++ * 1 = 32bit RGBA 8888 ++ * SMIDSW_WSWAP : 1 = swap pixel data bits. (Use with SMICS_PXLDAT) ++ * SMIDSW_WHOLD : Time between WE deassert and CS deassert. 1 to 64 ++ * SMIDSW_WPACEALL : 1: this device's WPACE will be used for the next ++ * transfer, regardless of that transfer's device. ++ * SMIDSW_WPACE : Cycles between CS deassert and next CS assert. ++ * Min 1, max 128 ++ * SMIDSW_WDREQ : Use external DREQ on pin 17 to pace writes. DMAP must ++ * be set in SMICS. ++ * SMIDSW_WSTROBE : Number of cycles to assert the write strobe. ++ * Min 1, max 128 ++ */ ++#define SMIDSW_WWIDTH_MASK ((1<<31)|(1<<30)) ++#define SMIDSW_WWIDTH_OFFS (30) ++#define SMIDSW_WSETUP_MASK (0x3f << 24) ++#define SMIDSW_WSETUP_OFFS (24) ++#define SMIDSW_WFORMAT (1 << 23) ++#define SMIDSW_WSWAP (1 << 22) ++#define SMIDSW_WHOLD_MASK (0x3f << 16) ++#define SMIDSW_WHOLD_OFFS (16) ++#define SMIDSW_WPACEALL (1 << 15) ++#define SMIDSW_WPACE_MASK (0x7f << 8) ++#define SMIDSW_WPACE_OFFS (8) ++#define SMIDSW_WDREQ (1 << 7) ++#define SMIDSW_WSTROBE_MASK (0x7f) ++#define SMIDSW_WSTROBE_OFFS (0) ++ ++/* Direct transfer control + status register ++ * SMIDCS_WRITE : Direction of transfer: 1 -> write, 0 -> read ++ * SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear. ++ * SMIDCS_START : Write 1 to start a transfer, if one is not already underway. ++ * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode. ++ */ ++ ++#define SMIDCS_WRITE (1 << 3) ++#define SMIDCS_DONE (1 << 2) ++#define SMIDCS_START (1 << 1) ++#define SMIDCS_ENABLE (1 << 0) ++ ++/* Direct transfer address register ++ * SMIDA_DEVICE : Indicates which of the device settings banks should be used. ++ * SMIDA_ADDR : The value to be asserted on the address pins. ++ */ ++ ++#define SMIDA_DEVICE_MASK ((1<<9)|(1<<8)) ++#define SMIDA_DEVICE_OFFS (8) ++#define SMIDA_ADDR_MASK (0x3f) ++#define SMIDA_ADDR_OFFS (0) ++ ++/* FIFO debug register ++ * SMIFD_FLVL : The high-tide mark of FIFO count during the most recent txfer ++ * SMIFD_FCNT : The current FIFO count. ++ */ ++#define SMIFD_FLVL_MASK (0x3f << 8) ++#define SMIFD_FLVL_OFFS (8) ++#define SMIFD_FCNT_MASK (0x3f) ++#define SMIFD_FCNT_OFFS (0) ++ ++#endif /* BCM2835_SMI_IMPLEMENTATION */ ++ ++#endif /* BCM2835_SMI_H */ diff --git a/target/linux/brcm2708/patches-4.1/0190-Add-SMI-NAND-driver.patch b/target/linux/brcm2708/patches-4.1/0190-Add-SMI-NAND-driver.patch new file mode 100644 index 0000000..c6b40aa --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0190-Add-SMI-NAND-driver.patch @@ -0,0 +1,491 @@ +From 3103b6c1b1a881e55421b7463fb76ad7bdf3974a Mon Sep 17 00:00:00 2001 +From: Luke Wren +Date: Sat, 5 Sep 2015 01:16:10 +0100 +Subject: [PATCH 190/203] Add SMI NAND driver + +Signed-off-by: Luke Wren +--- + .../bindings/mtd/brcm,bcm2835-smi-nand.txt | 42 ++++ + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/smi-nand-overlay.dts | 69 ++++++ + arch/arm/configs/bcm2709_defconfig | 7 + + arch/arm/configs/bcmrpi_defconfig | 7 + + drivers/mtd/nand/Kconfig | 7 + + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/bcm2835_smi_nand.c | 268 +++++++++++++++++++++ + 8 files changed, 402 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt + create mode 100644 arch/arm/boot/dts/overlays/smi-nand-overlay.dts + create mode 100644 drivers/mtd/nand/bcm2835_smi_nand.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt +@@ -0,0 +1,42 @@ ++* BCM2835 SMI NAND flash ++ ++This driver is a shim between the BCM2835 SMI driver (SMI is a peripheral for ++talking to parallel register interfaces) and Linux's MTD layer. ++ ++Required properties: ++- compatible: "brcm,bcm2835-smi-nand" ++- status: "okay" ++ ++Optional properties: ++- partition@n, where n is an integer from a consecutive sequence starting at 0 ++ - Difficult to store partition table on NAND device - normally put it ++ in the source code, kernel bootparams, or device tree (the best way!) ++ - Sub-properties: ++ - label: the partition name, as shown by mtdinfo /dev/mtd* ++ - reg: the size and offset of this partition. ++ - (optional) read-only: an empty property flagging as read only ++ ++Example: ++ ++nand: flash@0 { ++ compatible = "brcm,bcm2835-smi-nand"; ++ status = "okay"; ++ ++ partition@0 { ++ label = "stage2"; ++ // 128k ++ reg = <0 0x20000>; ++ read-only; ++ }; ++ partition@1 { ++ label = "firmware"; ++ // 16M ++ reg = <0x20000 0x1000000>; ++ read-only; ++ }; ++ partition@2 { ++ label = "root"; ++ // 2G ++ reg = <0x1020000 0x80000000>; ++ }; ++}; +\ No newline at end of file +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -15,6 +15,7 @@ endif + dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += smi-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += smi-dev-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-nand-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/smi-nand-overlay.dts +@@ -0,0 +1,69 @@ ++// Description: Overlay to enable NAND flash through ++// the secondary memory interface ++// Author: Luke Wren ++ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&smi>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&smi_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&soc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ nand: flash@0 { ++ compatible = "brcm,bcm2835-smi-nand"; ++ smi_handle = <&smi>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ status = "okay"; ++ ++ partition@0 { ++ label = "stage2"; ++ // 128k ++ reg = <0 0x20000>; ++ read-only; ++ }; ++ partition@1 { ++ label = "firmware"; ++ // 16M ++ reg = <0x20000 0x1000000>; ++ read-only; ++ }; ++ partition@2 { ++ label = "root"; ++ // 2G (will need to use 64 bit for >=4G) ++ reg = <0x1020000 0x80000000>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ smi_pins: smi_pins { ++ brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 ++ 12 13 14 15>; ++ /* Alt 1: SMI */ ++ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 ++ 5 5 5 5 5>; ++ /* /CS, /WE and /OE are pulled high, as they are ++ generally active low signals */ ++ brcm,pull = <2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0>; ++ }; ++ }; ++ }; ++}; +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -392,6 +392,10 @@ CONFIG_DEVTMPFS=y + CONFIG_DEVTMPFS_MOUNT=y + CONFIG_DMA_CMA=y + CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_MTD=m ++CONFIG_MTD_BLOCK=m ++CONFIG_MTD_NAND=m ++CONFIG_MTD_UBI=m + CONFIG_ZRAM=m + CONFIG_ZRAM_LZ4_COMPRESS=y + CONFIG_BLK_DEV_LOOP=y +@@ -1140,6 +1144,9 @@ CONFIG_CONFIGFS_FS=y + CONFIG_ECRYPT_FS=m + CONFIG_HFS_FS=m + CONFIG_HFSPLUS_FS=m ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_SUMMARY=y ++CONFIG_UBIFS_FS=m + CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -385,6 +385,10 @@ CONFIG_DEVTMPFS=y + CONFIG_DEVTMPFS_MOUNT=y + CONFIG_DMA_CMA=y + CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_MTD=m ++CONFIG_MTD_BLOCK=m ++CONFIG_MTD_NAND=m ++CONFIG_MTD_UBI=m + CONFIG_ZRAM=m + CONFIG_ZRAM_LZ4_COMPRESS=y + CONFIG_BLK_DEV_LOOP=y +@@ -1133,6 +1137,9 @@ CONFIG_CONFIGFS_FS=y + CONFIG_ECRYPT_FS=m + CONFIG_HFS_FS=m + CONFIG_HFSPLUS_FS=m ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_SUMMARY=y ++CONFIG_UBIFS_FS=m + CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -41,6 +41,13 @@ config MTD_SM_COMMON + tristate + default n + ++config MTD_NAND_BCM2835_SMI ++ tristate "Use Broadcom's Secondary Memory Interface as a NAND controller (BCM283x)" ++ depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2835_SMI && MTD_NAND ++ default m ++ help ++ Uses the BCM2835's SMI peripheral as a NAND controller. ++ + config MTD_NAND_DENALI + tristate "Support Denali NAND controller" + depends on HAS_DMA +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_NAND_DENALI) += denali + obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o + obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o + obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o ++obj-$(CONFIG_MTD_NAND_BCM2835_SMI) += bcm2835_smi_nand.o + obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o + obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o + obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o +--- /dev/null ++++ b/drivers/mtd/nand/bcm2835_smi_nand.c +@@ -0,0 +1,268 @@ ++/** ++ * NAND flash driver for Broadcom Secondary Memory Interface ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DEVICE_NAME "bcm2835-smi-nand" ++#define DRIVER_NAME "smi-nand-bcm2835" ++ ++struct bcm2835_smi_nand_host { ++ struct bcm2835_smi_instance *smi_inst; ++ struct nand_chip nand_chip; ++ struct mtd_info mtd; ++ struct device *dev; ++}; ++ ++/**************************************************************************** ++* ++* NAND functionality implementation ++* ++****************************************************************************/ ++ ++#define SMI_NAND_CLE_PIN 0x01 ++#define SMI_NAND_ALE_PIN 0x02 ++ ++static inline void bcm2835_smi_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, ++ unsigned int ctrl) ++{ ++ uint32_t cmd32 = cmd; ++ uint32_t addr = ~(SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN); ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ if (ctrl & NAND_CLE) ++ addr |= SMI_NAND_CLE_PIN; ++ if (ctrl & NAND_ALE) ++ addr |= SMI_NAND_ALE_PIN; ++ /* Lower ALL the CS pins! */ ++ if (ctrl & NAND_NCE) ++ addr &= (SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN); ++ ++ bcm2835_smi_set_address(inst, addr); ++ ++ if (cmd != NAND_CMD_NONE) ++ bcm2835_smi_write_buf(inst, &cmd32, 1); ++} ++ ++static inline uint8_t bcm2835_smi_nand_read_byte(struct mtd_info *mtd) ++{ ++ uint8_t byte; ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ bcm2835_smi_read_buf(inst, &byte, 1); ++ return byte; ++} ++ ++static inline void bcm2835_smi_nand_write_byte(struct mtd_info *mtd, ++ uint8_t byte) ++{ ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ bcm2835_smi_write_buf(inst, &byte, 1); ++} ++ ++static inline void bcm2835_smi_nand_write_buf(struct mtd_info *mtd, ++ const uint8_t *buf, int len) ++{ ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ bcm2835_smi_write_buf(inst, buf, len); ++} ++ ++static inline void bcm2835_smi_nand_read_buf(struct mtd_info *mtd, ++ uint8_t *buf, int len) ++{ ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ bcm2835_smi_read_buf(inst, buf, len); ++} ++ ++/**************************************************************************** ++* ++* Probe and remove functions ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_nand_probe(struct platform_device *pdev) ++{ ++ struct bcm2835_smi_nand_host *host; ++ struct nand_chip *this; ++ struct mtd_info *mtd; ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node, *smi_node; ++ struct mtd_part_parser_data ppdata; ++ struct smi_settings *smi_settings; ++ struct bcm2835_smi_instance *smi_inst; ++ int ret = -ENXIO; ++ ++ if (!node) { ++ dev_err(dev, "No device tree node supplied!"); ++ return -EINVAL; ++ } ++ ++ smi_node = of_parse_phandle(node, "smi_handle", 0); ++ ++ /* Request use of SMI peripheral: */ ++ smi_inst = bcm2835_smi_get(smi_node); ++ ++ if (!smi_inst) { ++ dev_err(dev, "Could not register with SMI."); ++ return -EPROBE_DEFER; ++ } ++ ++ /* Set SMI timing and bus width */ ++ ++ smi_settings = bcm2835_smi_get_settings_from_regs(smi_inst); ++ ++ smi_settings->data_width = SMI_WIDTH_8BIT; ++ smi_settings->read_setup_time = 2; ++ smi_settings->read_hold_time = 1; ++ smi_settings->read_pace_time = 1; ++ smi_settings->read_strobe_time = 3; ++ ++ smi_settings->write_setup_time = 2; ++ smi_settings->write_hold_time = 1; ++ smi_settings->write_pace_time = 1; ++ smi_settings->write_strobe_time = 3; ++ ++ bcm2835_smi_set_regs_from_settings(smi_inst); ++ ++ host = devm_kzalloc(dev, sizeof(struct bcm2835_smi_nand_host), ++ GFP_KERNEL); ++ if (!host) ++ return -ENOMEM; ++ ++ host->dev = dev; ++ host->smi_inst = smi_inst; ++ ++ platform_set_drvdata(pdev, host); ++ ++ /* Link the structures together */ ++ ++ this = &host->nand_chip; ++ mtd = &host->mtd; ++ mtd->priv = this; ++ mtd->owner = THIS_MODULE; ++ mtd->dev.parent = dev; ++ mtd->name = DRIVER_NAME; ++ ppdata.of_node = node; ++ ++ /* 20 us command delay time... */ ++ this->chip_delay = 20; ++ ++ this->priv = host; ++ this->cmd_ctrl = bcm2835_smi_nand_cmd_ctrl; ++ this->read_byte = bcm2835_smi_nand_read_byte; ++ this->write_byte = bcm2835_smi_nand_write_byte; ++ this->write_buf = bcm2835_smi_nand_write_buf; ++ this->read_buf = bcm2835_smi_nand_read_buf; ++ ++ this->ecc.mode = NAND_ECC_SOFT; ++ ++ /* Should never be accessed directly: */ ++ ++ this->IO_ADDR_R = (void *)0xdeadbeef; ++ this->IO_ADDR_W = (void *)0xdeadbeef; ++ ++ /* First scan to find the device and get the page size */ ++ ++ if (nand_scan_ident(mtd, 1, NULL)) ++ return -ENXIO; ++ ++ /* Second phase scan */ ++ ++ if (nand_scan_tail(mtd)) ++ return -ENXIO; ++ ++ ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); ++ if (!ret) ++ return 0; ++ ++ nand_release(mtd); ++ return -EINVAL; ++} ++ ++static int bcm2835_smi_nand_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_smi_nand_host *host = platform_get_drvdata(pdev); ++ ++ nand_release(&host->mtd); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* Register the driver with device tree ++* ++***************************************************************************/ ++ ++static const struct of_device_id bcm2835_smi_nand_of_match[] = { ++ {.compatible = "brcm,bcm2835-smi-nand",}, ++ { /* sentinel */ } ++}; ++ ++MODULE_DEVICE_TABLE(of, bcm2835_smi_nand_of_match); ++ ++static struct platform_driver bcm2835_smi_nand_driver = { ++ .probe = bcm2835_smi_nand_probe, ++ .remove = bcm2835_smi_nand_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_smi_nand_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2835_smi_nand_driver); ++ ++MODULE_ALIAS("platform:smi-nand-bcm2835"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION ++ ("Driver for NAND chips using Broadcom Secondary Memory Interface"); ++MODULE_AUTHOR("Luke Wren "); diff --git a/target/linux/brcm2708/patches-4.1/0191-BCM270X_DT-Document-SMI-overlay.patch b/target/linux/brcm2708/patches-4.1/0191-BCM270X_DT-Document-SMI-overlay.patch new file mode 100644 index 0000000..56d364e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0191-BCM270X_DT-Document-SMI-overlay.patch @@ -0,0 +1,59 @@ +From 31c23a1d9ad93cf6795d1fc72f9a254d5bcfc81b Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 16 Sep 2015 17:28:41 +0100 +Subject: [PATCH 191/203] BCM270X_DT: Document SMI overlay + +--- + arch/arm/boot/dts/overlays/Makefile | 6 +++--- + arch/arm/boot/dts/overlays/README | 18 ++++++++++++++++++ + 2 files changed, 21 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -13,9 +13,6 @@ ifeq ($(CONFIG_ARCH_BCM2835),y) + endif + + dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb +-dtb-$(RPI_DT_OVERLAYS) += smi-overlay.dtb +-dtb-$(RPI_DT_OVERLAYS) += smi-dev-overlay.dtb +-dtb-$(RPI_DT_OVERLAYS) += smi-nand-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb +@@ -48,6 +45,9 @@ dtb-$(RPI_DT_OVERLAYS) += rpi-proto-over + dtb-$(RPI_DT_OVERLAYS) += rpi-sense-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += sdio-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-dev-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-nand-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += spi-dma-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -530,6 +530,24 @@ Params: overclock_50 Clock ( + debug Enable debug output (default off) + + ++Name: smi ++Info: Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25! ++Load: dtoverlay=smi ++Params: ++ ++ ++Name: smi-dev ++Info: Enables the userspace interface for the SMI driver ++Load: dtoverlay=smi-dev ++Params: ++ ++ ++Name: smi-nand ++Info: Enables access to NAND flash via the SMI interface ++Load: dtoverlay=smi-nand ++Params: ++ ++ + Name: spi-bcm2708 + Info: Selects the bcm2708-spi SPI driver + Load: dtoverlay=spi-bcm2708 diff --git a/target/linux/brcm2708/patches-4.1/0192-dwc_otg-Force-host-mode-to-fix-incorrect-compute-mod.patch b/target/linux/brcm2708/patches-4.1/0192-dwc_otg-Force-host-mode-to-fix-incorrect-compute-mod.patch new file mode 100644 index 0000000..2e67974 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0192-dwc_otg-Force-host-mode-to-fix-incorrect-compute-mod.patch @@ -0,0 +1,21 @@ +From 140e8eab017a65e70d93dbb651045d0b8a70ff37 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Thu, 17 Sep 2015 17:13:42 +0100 +Subject: [PATCH 192/203] dwc_otg: Force host mode to fix incorrect compute + module boards + +--- + drivers/usb/host/dwc_otg/dwc_otg_cil.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/usb/host/dwc_otg/dwc_otg_cil.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c +@@ -192,7 +192,7 @@ dwc_otg_core_if_t *dwc_otg_cil_init(cons + core_if->hptxfsiz.d32 = + DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); + gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); +- gusbcfg.b.force_host_mode = 0; ++ gusbcfg.b.force_host_mode = 1; + DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); + dwc_mdelay(100); + } diff --git a/target/linux/brcm2708/patches-4.1/0193-config-Add-CONFIG_UHID.patch b/target/linux/brcm2708/patches-4.1/0193-config-Add-CONFIG_UHID.patch new file mode 100644 index 0000000..07808c4 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0193-config-Add-CONFIG_UHID.patch @@ -0,0 +1,30 @@ +From eaa0186f759c047121b38bf43d0ccfeb36fb23da Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Thu, 1 Oct 2015 11:49:11 +0100 +Subject: [PATCH 193/203] config: Add CONFIG_UHID + +--- + arch/arm/configs/bcm2709_defconfig | 1 + + arch/arm/configs/bcmrpi_defconfig | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -840,6 +840,7 @@ CONFIG_SND_SOC_WM8804_I2C=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m + CONFIG_HIDRAW=y ++CONFIG_UHID=m + CONFIG_HID_A4TECH=m + CONFIG_HID_ACRUX=m + CONFIG_HID_APPLE=m +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -833,6 +833,7 @@ CONFIG_SND_SOC_WM8804_I2C=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m + CONFIG_HIDRAW=y ++CONFIG_UHID=m + CONFIG_HID_A4TECH=m + CONFIG_HID_ACRUX=m + CONFIG_HID_APPLE=m diff --git a/target/linux/brcm2708/patches-4.1/0194-Add-support-for-the-HiFiBerry-DAC-Pro.patch b/target/linux/brcm2708/patches-4.1/0194-Add-support-for-the-HiFiBerry-DAC-Pro.patch new file mode 100644 index 0000000..f168f06 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0194-Add-support-for-the-HiFiBerry-DAC-Pro.patch @@ -0,0 +1,539 @@ +From d20be432374b0912dfbed90e4235411a44cc8fc0 Mon Sep 17 00:00:00 2001 +From: Stuart MacLean +Date: Fri, 2 Oct 2015 15:12:59 +0100 +Subject: [PATCH 194/203] Add support for the HiFiBerry DAC+ Pro. + +The HiFiBerry DAC+ and DAC+ Pro products both use the existing bcm sound driver with the DAC+ Pro having a special clock device driver representing the two high precision oscillators. + +An addition bug fix is included for the PCM512x codec where by the physical size of the sample frame is used in the calculation of the LRCK divisor as it was found to be wrong when using 24-bit depth sample contained in a little endian 4-byte sample frame. +--- + .../dts/overlays/hifiberry-dacplus-overlay.dts | 15 +- + drivers/clk/Makefile | 1 + + drivers/clk/clk-hifiberry-dacpro.c | 160 ++++++++++++++ + sound/soc/bcm/hifiberry_dacplus.c | 244 +++++++++++++++++++-- + sound/soc/codecs/pcm512x.c | 3 +- + 5 files changed, 396 insertions(+), 27 deletions(-) + create mode 100644 drivers/clk/clk-hifiberry-dacpro.c + +--- a/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts ++++ b/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts +@@ -6,6 +6,16 @@ + compatible = "brcm,bcm2708"; + + fragment@0 { ++ target-path = "/clocks"; ++ __overlay__ { ++ dacpro_osc: dacpro_osc { ++ compatible = "hifiberry,dacpro-clk"; ++ #clock-cells = <0>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-dacplus"; +@@ -14,14 +24,14 @@ + }; + }; + +- fragment@1 { ++ fragment@2 { + target = <&i2s>; + __overlay__ { + status = "okay"; + }; + }; + +- fragment@2 { ++ fragment@3 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; +@@ -32,6 +42,7 @@ + #sound-dai-cells = <0>; + compatible = "ti,pcm5122"; + reg = <0x4d>; ++ clocks = <&dacpro_osc>; + status = "okay"; + }; + }; +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk- + obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o + obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o + obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += clk-hifiberry-dacpro.o + obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o + obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o + obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o +--- /dev/null ++++ b/drivers/clk/clk-hifiberry-dacpro.c +@@ -0,0 +1,160 @@ ++/* ++ * Clock Driver for HiFiBerry DAC Pro ++ * ++ * Author: Stuart MacLean ++ * Copyright 2015 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Clock rate of CLK44EN attached to GPIO6 pin */ ++#define CLK_44EN_RATE 22579200UL ++/* Clock rate of CLK48EN attached to GPIO3 pin */ ++#define CLK_48EN_RATE 24576000UL ++ ++/** ++ * struct hifiberry_dacpro_clk - Common struct to the HiFiBerry DAC Pro ++ * @hw: clk_hw for the common clk framework ++ * @mode: 0 => CLK44EN, 1 => CLK48EN ++ */ ++struct clk_hifiberry_hw { ++ struct clk_hw hw; ++ uint8_t mode; ++}; ++ ++#define to_hifiberry_clk(_hw) container_of(_hw, struct clk_hifiberry_hw, hw) ++ ++static const struct of_device_id clk_hifiberry_dacpro_dt_ids[] = { ++ { .compatible = "hifiberry,dacpro-clk",}, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, clk_hifiberry_dacpro_dt_ids); ++ ++static unsigned long clk_hifiberry_dacpro_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ return (to_hifiberry_clk(hw)->mode == 0) ? CLK_44EN_RATE : ++ CLK_48EN_RATE; ++} ++ ++static long clk_hifiberry_dacpro_round_rate(struct clk_hw *hw, ++ unsigned long rate, unsigned long *parent_rate) ++{ ++ long actual_rate; ++ ++ if (rate <= CLK_44EN_RATE) { ++ actual_rate = (long)CLK_44EN_RATE; ++ } else if (rate >= CLK_48EN_RATE) { ++ actual_rate = (long)CLK_48EN_RATE; ++ } else { ++ long diff44Rate = (long)(rate - CLK_44EN_RATE); ++ long diff48Rate = (long)(CLK_48EN_RATE - rate); ++ ++ if (diff44Rate < diff48Rate) ++ actual_rate = (long)CLK_44EN_RATE; ++ else ++ actual_rate = (long)CLK_48EN_RATE; ++ } ++ return actual_rate; ++} ++ ++ ++static int clk_hifiberry_dacpro_set_rate(struct clk_hw *hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ unsigned long actual_rate; ++ struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); ++ ++ actual_rate = (unsigned long)clk_hifiberry_dacpro_round_rate(hw, rate, ++ &parent_rate); ++ clk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1; ++ return 0; ++} ++ ++ ++const struct clk_ops clk_hifiberry_dacpro_rate_ops = { ++ .recalc_rate = clk_hifiberry_dacpro_recalc_rate, ++ .round_rate = clk_hifiberry_dacpro_round_rate, ++ .set_rate = clk_hifiberry_dacpro_set_rate, ++}; ++ ++static int clk_hifiberry_dacpro_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct clk_hifiberry_hw *proclk; ++ struct clk *clk; ++ struct device *dev; ++ struct clk_init_data init; ++ ++ dev = &pdev->dev; ++ ++ proclk = kzalloc(sizeof(struct clk_hifiberry_hw), GFP_KERNEL); ++ if (!proclk) ++ return -ENOMEM; ++ ++ init.name = "clk-hifiberry-dacpro"; ++ init.ops = &clk_hifiberry_dacpro_rate_ops; ++ init.flags = CLK_IS_ROOT | CLK_IS_BASIC; ++ init.parent_names = NULL; ++ init.num_parents = 0; ++ ++ proclk->mode = 0; ++ proclk->hw.init = &init; ++ ++ clk = devm_clk_register(dev, &proclk->hw); ++ if (!IS_ERR(clk)) { ++ ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, ++ clk); ++ } else { ++ dev_err(dev, "Fail to register clock driver\n"); ++ kfree(proclk); ++ ret = PTR_ERR(clk); ++ } ++ return ret; ++} ++ ++static int clk_hifiberry_dacpro_remove(struct platform_device *pdev) ++{ ++ of_clk_del_provider(pdev->dev.of_node); ++ return 0; ++} ++ ++static struct platform_driver clk_hifiberry_dacpro_driver = { ++ .probe = clk_hifiberry_dacpro_probe, ++ .remove = clk_hifiberry_dacpro_remove, ++ .driver = { ++ .name = "clk-hifiberry-dacpro", ++ .of_match_table = clk_hifiberry_dacpro_dt_ids, ++ }, ++}; ++ ++static int __init clk_hifiberry_dacpro_init(void) ++{ ++ return platform_driver_register(&clk_hifiberry_dacpro_driver); ++} ++core_initcall(clk_hifiberry_dacpro_init); ++ ++static void __exit clk_hifiberry_dacpro_exit(void) ++{ ++ platform_driver_unregister(&clk_hifiberry_dacpro_driver); ++} ++module_exit(clk_hifiberry_dacpro_exit); ++ ++MODULE_DESCRIPTION("HiFiBerry DAC Pro clock driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:clk-hifiberry-dacpro"); +--- a/sound/soc/bcm/hifiberry_dacplus.c ++++ b/sound/soc/bcm/hifiberry_dacplus.c +@@ -1,8 +1,8 @@ + /* +- * ASoC Driver for HiFiBerry DAC+ ++ * ASoC Driver for HiFiBerry DAC+ / DAC Pro + * +- * Author: Daniel Matuschek +- * Copyright 2014 ++ * Author: Daniel Matuschek, Stuart MacLean ++ * Copyright 2014-2015 + * based on code by Florian Meier + * + * This program is free software; you can redistribute it and/or +@@ -17,6 +17,13 @@ + + #include + #include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + + #include + #include +@@ -26,34 +33,222 @@ + + #include "../codecs/pcm512x.h" + ++#define HIFIBERRY_DACPRO_NOCLOCK 0 ++#define HIFIBERRY_DACPRO_CLK44EN 1 ++#define HIFIBERRY_DACPRO_CLK48EN 2 ++ ++struct pcm512x_priv { ++ struct regmap *regmap; ++ struct clk *sclk; ++}; ++ ++/* Clock rate of CLK44EN attached to GPIO6 pin */ ++#define CLK_44EN_RATE 22579200UL ++/* Clock rate of CLK48EN attached to GPIO3 pin */ ++#define CLK_48EN_RATE 24576000UL ++ ++static bool snd_rpi_hifiberry_is_dacpro; ++ ++static void snd_rpi_hifiberry_dacplus_select_clk(struct snd_soc_codec *codec, ++ int clk_id) ++{ ++ switch (clk_id) { ++ case HIFIBERRY_DACPRO_NOCLOCK: ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x00); ++ break; ++ case HIFIBERRY_DACPRO_CLK44EN: ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x20); ++ break; ++ case HIFIBERRY_DACPRO_CLK48EN: ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x04); ++ break; ++ } ++} ++ ++static void snd_rpi_hifiberry_dacplus_clk_gpio(struct snd_soc_codec *codec) ++{ ++ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x24, 0x24); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02); ++} ++ ++static bool snd_rpi_hifiberry_dacplus_is_sclk(struct snd_soc_codec *codec) ++{ ++ int sck; ++ ++ sck = snd_soc_read(codec, PCM512x_RATE_DET_4); ++ return (!(sck & 0x40)); ++} ++ ++static bool snd_rpi_hifiberry_dacplus_is_sclk_sleep( ++ struct snd_soc_codec *codec) ++{ ++ msleep(2); ++ return snd_rpi_hifiberry_dacplus_is_sclk(codec); ++} ++ ++static bool snd_rpi_hifiberry_dacplus_is_pro_card(struct snd_soc_codec *codec) ++{ ++ bool isClk44EN, isClk48En, isNoClk; ++ ++ snd_rpi_hifiberry_dacplus_clk_gpio(codec); ++ ++ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_CLK44EN); ++ isClk44EN = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); ++ ++ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_NOCLOCK); ++ isNoClk = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); ++ ++ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_CLK48EN); ++ isClk48En = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); ++ ++ return (isClk44EN && isClk48En && !isNoClk); ++} ++ ++static int snd_rpi_hifiberry_dacplus_clk_for_rate(int sample_rate) ++{ ++ int type; ++ ++ switch (sample_rate) { ++ case 11025: ++ case 22050: ++ case 44100: ++ case 88200: ++ case 176400: ++ type = HIFIBERRY_DACPRO_CLK44EN; ++ break; ++ default: ++ type = HIFIBERRY_DACPRO_CLK48EN; ++ break; ++ } ++ return type; ++} ++ ++static void snd_rpi_hifiberry_dacplus_set_sclk(struct snd_soc_codec *codec, ++ int sample_rate) ++{ ++ struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); ++ ++ if (!IS_ERR(pcm512x->sclk)) { ++ int ctype; ++ ++ ctype = snd_rpi_hifiberry_dacplus_clk_for_rate(sample_rate); ++ clk_set_rate(pcm512x->sclk, (ctype == HIFIBERRY_DACPRO_CLK44EN) ++ ? CLK_44EN_RATE : CLK_48EN_RATE); ++ snd_rpi_hifiberry_dacplus_select_clk(codec, ctype); ++ } ++} ++ + static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd) + { + struct snd_soc_codec *codec = rtd->codec; ++ struct pcm512x_priv *priv; ++ ++ snd_rpi_hifiberry_is_dacpro ++ = snd_rpi_hifiberry_dacplus_is_pro_card(codec); ++ ++ if (snd_rpi_hifiberry_is_dacpro) { ++ struct snd_soc_dai_link *dai = rtd->dai_link; ++ ++ dai->name = "HiFiBerry DAC+ Pro"; ++ dai->stream_name = "HiFiBerry DAC+ Pro HiFi"; ++ dai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF ++ | SND_SOC_DAIFMT_CBM_CFM; ++ ++ snd_soc_update_bits(codec, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11); ++ snd_soc_update_bits(codec, PCM512x_MASTER_MODE, 0x03, 0x03); ++ snd_soc_update_bits(codec, PCM512x_MASTER_CLKDIV_2, 0x7f, 63); ++ } else { ++ priv = snd_soc_codec_get_drvdata(codec); ++ priv->sclk = ERR_PTR(-ENOENT); ++ } ++ + snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08); +- snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02); +- snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02); ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08); ++ ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_dacplus_update_rate_den( ++ struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); ++ struct snd_ratnum *rats_no_pll; ++ unsigned int num = 0, den = 0; ++ int err; ++ ++ rats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL); ++ if (!rats_no_pll) ++ return -ENOMEM; ++ ++ rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; ++ rats_no_pll->den_min = 1; ++ rats_no_pll->den_max = 128; ++ rats_no_pll->den_step = 1; ++ ++ err = snd_interval_ratnum(hw_param_interval(params, ++ SNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den); ++ if (err >= 0 && den) { ++ params->rate_num = num; ++ params->rate_den = den; ++ } ++ ++ devm_kfree(rtd->dev, rats_no_pll); + return 0; + } + +-static int snd_rpi_hifiberry_dacplus_hw_params(struct snd_pcm_substream *substream, +- struct snd_pcm_hw_params *params) ++static int snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro( ++ struct snd_soc_dai *cpu_dai, struct snd_pcm_hw_params *params) ++{ ++ int bratio = snd_pcm_format_physical_width(params_format(params)) ++ * params_channels(params); ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, bratio); ++} ++ ++static int snd_rpi_hifiberry_dacplus_hw_params( ++ struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) + { ++ int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; +- return snd_soc_dai_set_bclk_ratio(cpu_dai, 64); ++ ++ if (snd_rpi_hifiberry_is_dacpro) { ++ struct snd_soc_codec *codec = rtd->codec; ++ ++ snd_rpi_hifiberry_dacplus_set_sclk(codec, ++ params_rate(params)); ++ ++ ret = snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro(cpu_dai, ++ params); ++ if (!ret) ++ ret = snd_rpi_hifiberry_dacplus_update_rate_den( ++ substream, params); ++ } else { ++ ret = snd_soc_dai_set_bclk_ratio(cpu_dai, 64); ++ } ++ return ret; + } + +-static int snd_rpi_hifiberry_dacplus_startup(struct snd_pcm_substream *substream) { ++static int snd_rpi_hifiberry_dacplus_startup( ++ struct snd_pcm_substream *substream) ++{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec *codec = rtd->codec; +- snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08); ++ ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08); + return 0; + } + +-static void snd_rpi_hifiberry_dacplus_shutdown(struct snd_pcm_substream *substream) { ++static void snd_rpi_hifiberry_dacplus_shutdown( ++ struct snd_pcm_substream *substream) ++{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec *codec = rtd->codec; +- snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); ++ ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x00); + } + + /* machine stream operations */ +@@ -90,19 +285,20 @@ static int snd_rpi_hifiberry_dacplus_pro + int ret = 0; + + snd_rpi_hifiberry_dacplus.dev = &pdev->dev; +- + if (pdev->dev.of_node) { +- struct device_node *i2s_node; +- struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dacplus_dai[0]; +- i2s_node = of_parse_phandle(pdev->dev.of_node, +- "i2s-controller", 0); +- +- if (i2s_node) { +- dai->cpu_dai_name = NULL; +- dai->cpu_of_node = i2s_node; +- dai->platform_name = NULL; +- dai->platform_of_node = i2s_node; +- } ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai; ++ ++ dai = &snd_rpi_hifiberry_dacplus_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } + } + + ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); +--- a/sound/soc/codecs/pcm512x.c ++++ b/sound/soc/codecs/pcm512x.c +@@ -856,7 +856,8 @@ static int pcm512x_set_dividers(struct s + int fssp; + int gpio; + +- lrclk_div = snd_soc_params_to_frame_size(params); ++ lrclk_div = snd_pcm_format_physical_width(params_format(params)) ++ * params_channels(params); + if (lrclk_div == 0) { + dev_err(dev, "No LRCLK?\n"); + return -EINVAL; diff --git a/target/linux/brcm2708/patches-4.1/0195-config-Add-CONFIG_CRYPTO_USER_API_SKCIPHER.patch b/target/linux/brcm2708/patches-4.1/0195-config-Add-CONFIG_CRYPTO_USER_API_SKCIPHER.patch new file mode 100644 index 0000000..a0c9759 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0195-config-Add-CONFIG_CRYPTO_USER_API_SKCIPHER.patch @@ -0,0 +1,30 @@ +From 1e0886a25891d714ffa99cbdd2f68f7e2015a804 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Sun, 4 Oct 2015 12:30:01 +0100 +Subject: [PATCH 195/203] config: Add CONFIG_CRYPTO_USER_API_SKCIPHER + +--- + arch/arm/configs/bcm2709_defconfig | 1 + + arch/arm/configs/bcmrpi_defconfig | 1 + + 2 files changed, 2 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -1236,6 +1236,7 @@ CONFIG_CRYPTO_WP512=m + CONFIG_CRYPTO_CAST5=m + CONFIG_CRYPTO_DES=y + # CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_USER_API_SKCIPHER=m + # CONFIG_CRYPTO_HW is not set + CONFIG_ARM_CRYPTO=y + CONFIG_CRYPTO_SHA1_ARM_NEON=m +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -1232,6 +1232,7 @@ CONFIG_CRYPTO_WP512=m + CONFIG_CRYPTO_CAST5=m + CONFIG_CRYPTO_DES=y + # CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_USER_API_SKCIPHER=m + # CONFIG_CRYPTO_HW is not set + CONFIG_ARM_CRYPTO=y + CONFIG_CRYPTO_SHA1_ARM=m diff --git a/target/linux/brcm2708/patches-4.1/0196-config-Add-options-for-supporting-openlabs-802.15.4-.patch b/target/linux/brcm2708/patches-4.1/0196-config-Add-options-for-supporting-openlabs-802.15.4-.patch new file mode 100644 index 0000000..ea9be1f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0196-config-Add-options-for-supporting-openlabs-802.15.4-.patch @@ -0,0 +1,55 @@ +From 59a7fec4b1798a00025438b88e782ec6b36d5a53 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Sun, 4 Oct 2015 12:36:44 +0100 +Subject: [PATCH 196/203] config: Add options for supporting openlabs 802.15.4 + radio + +--- + arch/arm/configs/bcm2709_defconfig | 6 ++++++ + arch/arm/configs/bcmrpi_defconfig | 6 ++++++ + 2 files changed, 12 insertions(+) + +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -283,6 +283,9 @@ CONFIG_VLAN_8021Q=m + CONFIG_VLAN_8021Q_GVRP=y + CONFIG_ATALK=m + CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m + CONFIG_NET_SCHED=y + CONFIG_NET_SCH_CBQ=m + CONFIG_NET_SCH_HTB=m +@@ -527,6 +530,9 @@ CONFIG_ZD1211RW=m + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -276,6 +276,9 @@ CONFIG_VLAN_8021Q=m + CONFIG_VLAN_8021Q_GVRP=y + CONFIG_ATALK=m + CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m + CONFIG_NET_SCHED=y + CONFIG_NET_SCH_CBQ=m + CONFIG_NET_SCH_HTB=m +@@ -520,6 +523,9 @@ CONFIG_ZD1211RW=m + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m diff --git a/target/linux/brcm2708/patches-4.1/0197-BCM270X_DT-Add-at86rf233-overlay.patch b/target/linux/brcm2708/patches-4.1/0197-BCM270X_DT-Add-at86rf233-overlay.patch new file mode 100644 index 0000000..3ede6a5 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0197-BCM270X_DT-Add-at86rf233-overlay.patch @@ -0,0 +1,130 @@ +From 7b82355fa657220c9d5e72f0aa5228f0d76819fa Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 5 Oct 2015 10:47:45 +0100 +Subject: [PATCH 197/203] BCM270X_DT: Add at86rf233 overlay + +Add an overlay to support the Atmel AT86RF233 WPAN transceiver on spi0.0. + +See: https://github.com/raspberrypi/linux/issues/1151 +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 21 +++++++-- + arch/arm/boot/dts/overlays/at86rf233-overlay.dts | 54 ++++++++++++++++++++++++ + 3 files changed, 72 insertions(+), 4 deletions(-) + create mode 100644 arch/arm/boot/dts/overlays/at86rf233-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -13,6 +13,7 @@ ifeq ($(CONFIG_ARCH_BCM2835),y) + endif + + dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += at86rf233-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -69,13 +69,14 @@ DT parameters: + + Parameters always have default values, although in some cases (e.g. "w1-gpio") + it is necessary to provided multiple overlays in order to get the desired +-behaviour. See the list of overlays below for a description of the parameters and their defaults. ++behaviour. See the list of overlays below for a description of the parameters ++and their defaults. + + The Overlay and Parameter Reference + =================================== + +-N.B. When editing this file, please preserve the indentation levels to make it simple to parse +-programmatically. NO HARD TABS. ++N.B. When editing this file, please preserve the indentation levels to make it ++simple to parse programmatically. NO HARD TABS. + + + Name: +@@ -149,7 +150,7 @@ Name: ads7846 + Info: ADS7846 Touch controller + Load: dtoverlay=ads7846,= + Params: cs SPI bus Chip Select (default 1) +- speed SPI bus speed (default 2Mhz, max 3.25MHz) ++ speed SPI bus speed (default 2MHz, max 3.25MHz) + penirq GPIO used for PENIRQ. REQUIRED + penirq_pull Set GPIO pull (default 0=none, 2=pullup) + swapxy Swap x and y axis +@@ -170,6 +171,18 @@ Params: cs SPI bus + www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt + + ++Name: at86rf233 ++Info: Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver, ++ connected to spi0.0 ++Load: dtoverlay=at86rf233,= ++Params: interrupt GPIO used for INT (default 23) ++ reset GPIO used for Reset (default 24) ++ sleep GPIO used for Sleep (default 25) ++ speed SPI bus speed in Hz (default 750000) ++ trim Fine tuning of the internal capacitance ++ arrays (0=+0pF, 15=+4.5pF, default 15) ++ ++ + Name: bmp085_i2c-sensor + Info: Configures the BMP085/BMP180 digital barometric pressure and temperature + sensors from Bosch Sensortec +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/at86rf233-overlay.dts +@@ -0,0 +1,54 @@ ++/dts-v1/; ++/plugin/; ++ ++/* Overlay for Atmel AT86RF233 IEEE 802.15.4 WPAN transceiver on spi0.0 */ ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ lowpan0: at86rf233@0 { ++ compatible = "atmel,at86rf233"; ++ reg = <0>; ++ interrupt-parent = <&gpio>; ++ interrupts = <23 4>; /* active high */ ++ reset-gpio = <&gpio 24 1>; ++ sleep-gpio = <&gpio 25 1>; ++ spi-max-frequency = <7500000>; ++ xtal-trim = /bits/ 8 <0xf>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ lowpan0_pins: lowpan0_pins { ++ brcm,pins = <23 24 25>; ++ brcm,function = <0 1 1>; /* in out out */ ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ interrupt = <&lowpan0>, "interrupts:0", ++ <&lowpan0_pins>, "brcm,pins:0"; ++ reset = <&lowpan0>, "reset-gpio:4", ++ <&lowpan0_pins>, "brcm,pins:4"; ++ sleep = <&lowpan0>, "sleep-gpio:4", ++ <&lowpan0_pins>, "brcm,pins:8"; ++ speed = <&lowpan0>, "spi-max-frequency:0"; ++ trim = <&lowpan0>, "xtal-trim.0"; ++ }; ++}; diff --git a/target/linux/brcm2708/patches-4.1/0198-bcm2835-gpiomem-Fix-for-ARCH_BCM2835-builds.patch b/target/linux/brcm2708/patches-4.1/0198-bcm2835-gpiomem-Fix-for-ARCH_BCM2835-builds.patch new file mode 100644 index 0000000..643ed2c --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0198-bcm2835-gpiomem-Fix-for-ARCH_BCM2835-builds.patch @@ -0,0 +1,67 @@ +From 6413adc1fbf4c3e9a2bcd707dd7776f419988d7c Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Tue, 6 Oct 2015 10:16:58 +0100 +Subject: [PATCH 198/203] bcm2835-gpiomem: Fix for ARCH_BCM2835 builds + +Build on ARCH_BCM2835, and fail to probe if no IO resource. + +See: https://github.com/raspberrypi/linux/issues/1154 +--- + drivers/char/broadcom/bcm2835-gpiomem.c | 25 ++++++++++--------------- + 1 file changed, 10 insertions(+), 15 deletions(-) + +--- a/drivers/char/broadcom/bcm2835-gpiomem.c ++++ b/drivers/char/broadcom/bcm2835-gpiomem.c +@@ -143,7 +143,6 @@ static int bcm2835_gpiomem_probe(struct + int err; + void *ptr_err; + struct device *dev = &pdev->dev; +- struct device_node *node = dev->of_node; + struct resource *ioresource; + + /* Allocate buffers and instance data */ +@@ -157,6 +156,15 @@ static int bcm2835_gpiomem_probe(struct + + inst->dev = dev; + ++ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (ioresource) { ++ inst->gpio_regs_phys = ioresource->start; ++ } else { ++ dev_err(inst->dev, "failed to get IO resource"); ++ err = -ENOENT; ++ goto failed_get_resource; ++ } ++ + /* Create character device entries */ + + err = alloc_chrdev_region(&bcm2835_gpiomem_devid, +@@ -187,20 +195,6 @@ static int bcm2835_gpiomem_probe(struct + if (IS_ERR(ptr_err)) + goto failed_device_create; + +- /* Get address from device tree if available (*_resource() correctly +- converts the bus address in device tree to a physical address), +- or use hardcoded offset + BCM2708_PERI_BASE if not. +- (In spite of its name 2708 actually seems to have the correct +- mach-dependent value on 2709 etc, as it is defined in +- mach-bcm270x/platform.h) */ +- +- if (node) { +- ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- inst->gpio_regs_phys = ioresource->start; +- } else { +- inst->gpio_regs_phys = GPIO_BASE; +- } +- + dev_info(inst->dev, "Initialised: Registers at 0x%08lx", + inst->gpio_regs_phys); + +@@ -214,6 +208,7 @@ failed_class_create: + failed_cdev_add: + unregister_chrdev_region(bcm2835_gpiomem_devid, 1); + failed_alloc_chrdev: ++failed_get_resource: + kfree(inst); + failed_inst_alloc: + dev_err(inst->dev, "could not load bcm2835_gpiomem"); diff --git a/target/linux/brcm2708/patches-4.1/0199-scripts-mkknlimg-Improve-ARCH_BCM2835-detection.patch b/target/linux/brcm2708/patches-4.1/0199-scripts-mkknlimg-Improve-ARCH_BCM2835-detection.patch new file mode 100644 index 0000000..ccd115f --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0199-scripts-mkknlimg-Improve-ARCH_BCM2835-detection.patch @@ -0,0 +1,90 @@ +From f578216ec77548da230336549ed488dbdf4a42f3 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 8 Oct 2015 13:33:28 +0100 +Subject: [PATCH 199/203] scripts/mkknlimg: Improve ARCH_BCM2835 detection + +The board support code contains sufficient strings to be able to +distinguish 2708 vs. 2835 builds, so remove the check for +bcm2835-pm-wdt which could exist in either. + +Also, since the canned configuration is no longer built in (it's +a module), remove the config string checking. + +See: https://github.com/raspberrypi/linux/issues/1157 +--- + scripts/mkknlimg | 41 +++++------------------------------------ + 1 file changed, 5 insertions(+), 36 deletions(-) + +--- a/scripts/mkknlimg ++++ b/scripts/mkknlimg +@@ -50,12 +50,6 @@ if (! -r $kernel_file) + usage(); + } + +-my @wanted_config_lines = +-( +- 'CONFIG_BCM2708_DT', +- 'CONFIG_ARCH_BCM2835' +-); +- + my @wanted_strings = + ( + 'bcm2708_fb', +@@ -63,7 +57,8 @@ my @wanted_strings = + 'brcm,bcm2835-sdhost', + 'brcm,bcm2708-pinctrl', + 'brcm,bcm2835-gpio', +- 'brcm,bcm2835-pm-wdt' ++ 'brcm,bcm2835', ++ 'brcm,bcm2836' + ); + + my $res = try_extract($kernel_file, $tmpfile1); +@@ -98,12 +93,11 @@ if ($res) + config_bool($res, 'brcm,bcm2835-mmc') || + config_bool($res, 'brcm,bcm2835-sdhost')) + { +- $dtok ||= config_bool($res, 'CONFIG_BCM2708_DT'); +- $dtok ||= config_bool($res, 'CONFIG_ARCH_BCM2835'); + $dtok ||= config_bool($res, 'brcm,bcm2708-pinctrl'); + $dtok ||= config_bool($res, 'brcm,bcm2835-gpio'); +- $is_283x ||= config_bool($res, 'CONFIG_ARCH_BCM2835'); +- $is_283x ||= config_bool($res, 'brcm,bcm2835-pm-wdt'); ++ $is_283x ||= config_bool($res, 'brcm,bcm2835'); ++ $is_283x ||= config_bool($res, 'brcm,bcm2836'); ++ $dtok ||= $is_283x; + $append_trailer = 1; + } + else +@@ -205,31 +199,6 @@ sub try_extract + $res->{$match} = 1; + } + +- my $config_pattern = '^('.join('|', @wanted_config_lines).')=(.*)$'; +- my $cf1 = 'IKCFG_ST\037\213\010'; +- my $cf2 = '0123456789'; +- +- my $pos = `tr "$cf1\n$cf2" "\n$cf2=" < "$knl" | grep -abo "^$cf2"`; +- if ($pos) +- { +- $pos =~ s/:.*[\r\n]*$//s; +- $pos += 8; +- my $err = (system("tail -c+$pos \"$knl\" | zcat > $tmp 2> /dev/null") >> 8); +- if (($err == 0) || ($err == 2)) +- { +- if (open(my $fh, '<', $tmp)) +- { +- while (my $line = <$fh>) +- { +- chomp($line); +- $res->{$1} = $2 if ($line =~ /$config_pattern/); +- } +- +- close($fh); +- } +- } +- } +- + return $res; + } + diff --git a/target/linux/brcm2708/patches-4.1/0200-BCM270X_DT-Make-mmc-overlay-compatible-with-current-.patch b/target/linux/brcm2708/patches-4.1/0200-BCM270X_DT-Make-mmc-overlay-compatible-with-current-.patch new file mode 100644 index 0000000..da0a9bc --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0200-BCM270X_DT-Make-mmc-overlay-compatible-with-current-.patch @@ -0,0 +1,39 @@ +From f6c213fbd75a2efeb2e8ef0034be7376a306f7fd Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Fri, 9 Oct 2015 10:49:00 +0100 +Subject: [PATCH 200/203] BCM270X_DT: Make mmc overlay compatible with current + firmware + +The original DT overlay logic followed a merge-then-patch procedure, +i.e. parameters are applied to the loaded overlay before the overlay +is merged into the base DTB. This sequence has been changed to +patch-then-merge, in order to support parameterised node names, and +to protect against bad overlays. As a result, overrides (parameters) +must only target labels in the overlay, but the overlay can obviously target nodes in the base DTB. + +mmc-overlay.dts (that switches back to the original mmc sdcard +driver) is the only overlay violating that rule, and this patch +fixes it. +--- + arch/arm/boot/dts/overlays/mmc-overlay.dts | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm/boot/dts/overlays/mmc-overlay.dts ++++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts +@@ -7,13 +7,13 @@ + fragment@0 { + target = <&mmc>; + +- __overlay__ { ++ frag0: __overlay__ { + brcm,overclock-50 = <0>; + }; + }; + + __overrides__ { +- overclock_50 = <&mmc>,"brcm,overclock-50:0"; +- force_pio = <&mmc>,"brcm,force-pio?"; ++ overclock_50 = <&frag0>,"brcm,overclock-50:0"; ++ force_pio = <&frag0>,"brcm,force-pio?"; + }; + }; diff --git a/target/linux/brcm2708/patches-4.1/0201-BCM270X_DT-Reduce-default-at86rf233-SPI-frequency.patch b/target/linux/brcm2708/patches-4.1/0201-BCM270X_DT-Reduce-default-at86rf233-SPI-frequency.patch new file mode 100644 index 0000000..af1c54e --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0201-BCM270X_DT-Reduce-default-at86rf233-SPI-frequency.patch @@ -0,0 +1,36 @@ +From a78ad9a34f11fecfdcd08675396bf2bf163a3f4d Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 12 Oct 2015 08:52:00 +0100 +Subject: [PATCH 201/203] BCM270X_DT: Reduce default at86rf233 SPI frequency + +The AT86RF233 has been found to be unreliable on a 7.5MHz SPI bus, +so reduce the default frequency to 6MHz. + +See: https://github.com/raspberrypi/linux/issues/1151 +--- + arch/arm/boot/dts/overlays/README | 2 +- + arch/arm/boot/dts/overlays/at86rf233-overlay.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -178,7 +178,7 @@ Load: dtoverlay=at86rf233,=; /* active high */ + reset-gpio = <&gpio 24 1>; + sleep-gpio = <&gpio 25 1>; +- spi-max-frequency = <7500000>; ++ spi-max-frequency = <6000000>; + xtal-trim = /bits/ 8 <0xf>; + }; + }; diff --git a/target/linux/brcm2708/patches-4.1/0202-New-overlay-for-PiScreen2r.patch b/target/linux/brcm2708/patches-4.1/0202-New-overlay-for-PiScreen2r.patch new file mode 100644 index 0000000..cf98bef --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0202-New-overlay-for-PiScreen2r.patch @@ -0,0 +1,148 @@ +From 688316bb306e42d224d4922b26cd44d5ff0e64b3 Mon Sep 17 00:00:00 2001 +From: mwilliams03 +Date: Sun, 18 Oct 2015 17:07:24 -0700 +Subject: [PATCH 202/203] New overlay for PiScreen2r + +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 14 +++ + arch/arm/boot/dts/overlays/piscreen2r-overlay.dts | 100 ++++++++++++++++++++++ + 3 files changed, 115 insertions(+) + create mode 100644 arch/arm/boot/dts/overlays/piscreen2r-overlay.dts + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -34,6 +34,7 @@ dtb-$(RPI_DT_OVERLAYS) += mcp2515-can1-o + dtb-$(RPI_DT_OVERLAYS) += mmc-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += mz61581-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += piscreen2r-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += pitft28-resistive-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -411,6 +411,20 @@ Params: speed Display + xohms Touchpanel sensitivity (X-plate resistance) + + ++Name: piscreen2r ++Info: PiScreen 2 with resistive TP display by OzzMaker.com ++Load: dtoverlay=piscreen,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ + Name: pitft28-resistive + Info: Adafruit PiTFT 2.8" resistive touch screen + Load: dtoverlay=pitft28-resistive,= +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts +@@ -0,0 +1,100 @@ ++ /* ++ * Device Tree overlay for PiScreen2 3.5" TFT with resistive touch by Ozzmaker.com ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ piscreen2_pins: piscreen2_pins { ++ brcm,pins = <17 25 24 22>; ++ brcm,function = <0 1 1 1>; /* in out out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ piscreen2: piscreen2@0{ ++ compatible = "ilitek,ili9486"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&piscreen2_pins>; ++ bgr; ++ spi-max-frequency = <64000000>; ++ rotate = <90>; ++ fps = <30>; ++ buswidth = <8>; ++ regwidth = <16>; ++ txbuflen = <32768>; ++ reset-gpios = <&gpio 25 0>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 22 1>; ++ debug = <0>; ++ ++ init = <0x10000b0 0x00 ++ 0x1000011 ++ 0x20000ff ++ 0x100003a 0x55 ++ 0x1000036 0x28 ++ 0x10000c0 0x11 0x09 ++ 0x10000c1 0x41 ++ 0x10000c5 0x00 0x00 0x00 0x00 ++ 0x10000b6 0x00 0x02 ++ 0x10000f7 0xa9 0x51 0x2c 0x2 ++ 0x10000be 0x00 0x04 ++ 0x10000e9 0x00 ++ 0x1000011 ++ 0x1000029>; ++ ++ }; ++ ++ piscreen2_ts: piscreen2-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <17 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 17 0>; ++ ti,swap-xy; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&piscreen2>,"spi-max-frequency:0"; ++ rotate = <&piscreen2>,"rotate:0"; ++ fps = <&piscreen2>,"fps:0"; ++ debug = <&piscreen2>,"debug:0"; ++ xohms = <&piscreen2_ts>,"ti,x-plate-ohms;0"; ++ }; ++}; ++ diff --git a/target/linux/brcm2708/patches-4.1/0203-rpi_display-add-backlight-driver-and-overlay.patch b/target/linux/brcm2708/patches-4.1/0203-rpi_display-add-backlight-driver-and-overlay.patch new file mode 100644 index 0000000..e52d499 --- /dev/null +++ b/target/linux/brcm2708/patches-4.1/0203-rpi_display-add-backlight-driver-and-overlay.patch @@ -0,0 +1,250 @@ +From 7d9db46fa0eb27c0d6df7a3a6ae20da515a20e58 Mon Sep 17 00:00:00 2001 +From: P33M +Date: Wed, 21 Oct 2015 14:55:21 +0100 +Subject: [PATCH 203/203] rpi_display: add backlight driver and overlay + +Add a mailbox-driven backlight controller for the Raspberry Pi DSI +touchscreen display. Requires updated GPU firmware to recognise the +mailbox request. + +Signed-off-by: Gordon Hollingworth +--- + arch/arm/boot/dts/overlays/Makefile | 1 + + arch/arm/boot/dts/overlays/README | 6 ++ + .../boot/dts/overlays/rpi-backlight-overlay.dts | 21 ++++ + arch/arm/configs/bcm2709_defconfig | 1 + + arch/arm/configs/bcmrpi_defconfig | 1 + + drivers/video/backlight/Kconfig | 6 ++ + drivers/video/backlight/Makefile | 1 + + drivers/video/backlight/rpi_backlight.c | 119 +++++++++++++++++++++ + include/soc/bcm2835/raspberrypi-firmware.h | 1 + + 9 files changed, 157 insertions(+) + create mode 100644 arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts + create mode 100644 drivers/video/backlight/rpi_backlight.c + +--- a/arch/arm/boot/dts/overlays/Makefile ++++ b/arch/arm/boot/dts/overlays/Makefile +@@ -40,6 +40,7 @@ dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overl + dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += pwm-2chan-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += raspidac3-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-backlight-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb + dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb +--- a/arch/arm/boot/dts/overlays/README ++++ b/arch/arm/boot/dts/overlays/README +@@ -490,6 +490,12 @@ Load: dtoverlay=raspidac3 + Params: + + ++Name: rpi-backlight ++Info: Raspberry Pi official display backlight driver ++Load: dtoverlay=rpi-backlight ++Params: ++ ++ + Name: rpi-dac + Info: Configures the RPi DAC audio card + Load: dtoverlay=rpi-dac +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts +@@ -0,0 +1,21 @@ ++/* ++ * Devicetree overlay for mailbox-driven Raspberry Pi DSI Display ++ * backlight controller ++ */ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ rpi_backlight: rpi_backlight { ++ compatible = "raspberrypi,rpi-backlight"; ++ firmware = <&firmware>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +--- a/arch/arm/configs/bcm2709_defconfig ++++ b/arch/arm/configs/bcm2709_defconfig +@@ -806,6 +806,7 @@ CONFIG_FB_BCM2708=y + CONFIG_FB_SSD1307=m + CONFIG_FB_RPISENSE=m + # CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_RPI=m + CONFIG_BACKLIGHT_GPIO=m + CONFIG_FRAMEBUFFER_CONSOLE=y + CONFIG_LOGO=y +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -799,6 +799,7 @@ CONFIG_FB_BCM2708=y + CONFIG_FB_SSD1307=m + CONFIG_FB_RPISENSE=m + # CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_RPI=m + CONFIG_BACKLIGHT_GPIO=m + CONFIG_FRAMEBUFFER_CONSOLE=y + CONFIG_LOGO=y +--- a/drivers/video/backlight/Kconfig ++++ b/drivers/video/backlight/Kconfig +@@ -263,6 +263,12 @@ config BACKLIGHT_PWM + If you have a LCD backlight adjustable by PWM, say Y to enable + this driver. + ++config BACKLIGHT_RPI ++ tristate "Raspberry Pi display firmware driven backlight" ++ help ++ If you have the Raspberry Pi DSI touchscreen display, say Y to ++ enable the mailbox-controlled backlight driver. ++ + config BACKLIGHT_DA903X + tristate "Backlight Driver for DA9030/DA9034 using WLED" + depends on PMIC_DA903X +--- a/drivers/video/backlight/Makefile ++++ b/drivers/video/backlight/Makefile +@@ -49,6 +49,7 @@ obj-$(CONFIG_BACKLIGHT_OT200) += ot200_ + obj-$(CONFIG_BACKLIGHT_PANDORA) += pandora_bl.o + obj-$(CONFIG_BACKLIGHT_PCF50633) += pcf50633-backlight.o + obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o ++obj-$(CONFIG_BACKLIGHT_RPI) += rpi_backlight.o + obj-$(CONFIG_BACKLIGHT_SAHARA) += kb3886_bl.o + obj-$(CONFIG_BACKLIGHT_SKY81452) += sky81452-backlight.o + obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o +--- /dev/null ++++ b/drivers/video/backlight/rpi_backlight.c +@@ -0,0 +1,119 @@ ++/* ++ * rpi_bl.c - Backlight controller through VPU ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct rpi_backlight { ++ struct device *dev; ++ struct device *fbdev; ++ struct rpi_firmware *fw; ++}; ++ ++static int rpi_backlight_update_status(struct backlight_device *bl) ++{ ++ struct rpi_backlight *gbl = bl_get_data(bl); ++ int brightness = bl->props.brightness; ++ int ret; ++ ++ if (bl->props.power != FB_BLANK_UNBLANK || ++ bl->props.fb_blank != FB_BLANK_UNBLANK || ++ bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK)) ++ brightness = 0; ++ ++ ret = rpi_firmware_property(gbl->fw, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT, ++ &brightness, sizeof(brightness)); ++ if (ret) { ++ dev_err(gbl->dev, "Failed to set brightness\n"); ++ return ret; ++ } ++ ++ if (brightness < 0) { ++ dev_err(gbl->dev, "Backlight change failed\n"); ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++static const struct backlight_ops rpi_backlight_ops = { ++ .options = BL_CORE_SUSPENDRESUME, ++ .update_status = rpi_backlight_update_status, ++}; ++ ++static int rpi_backlight_probe(struct platform_device *pdev) ++{ ++ struct backlight_properties props; ++ struct backlight_device *bl; ++ struct rpi_backlight *gbl; ++ struct device_node *fw_node; ++ ++ gbl = devm_kzalloc(&pdev->dev, sizeof(*gbl), GFP_KERNEL); ++ if (gbl == NULL) ++ return -ENOMEM; ++ ++ gbl->dev = &pdev->dev; ++ ++ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); ++ if (!fw_node) { ++ dev_err(&pdev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++ ++ gbl->fw = rpi_firmware_get(fw_node); ++ if (!gbl->fw) ++ return -EPROBE_DEFER; ++ ++ memset(&props, 0, sizeof(props)); ++ props.type = BACKLIGHT_RAW; ++ props.max_brightness = 255; ++ bl = devm_backlight_device_register(&pdev->dev, dev_name(&pdev->dev), ++ &pdev->dev, gbl, &rpi_backlight_ops, ++ &props); ++ if (IS_ERR(bl)) { ++ dev_err(&pdev->dev, "failed to register backlight\n"); ++ return PTR_ERR(bl); ++ } ++ ++ bl->props.brightness = 255; ++ backlight_update_status(bl); ++ ++ platform_set_drvdata(pdev, bl); ++ return 0; ++} ++ ++static const struct of_device_id rpi_backlight_of_match[] = { ++ { .compatible = "raspberrypi,rpi-backlight" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, rpi_backlight_of_match); ++ ++static struct platform_driver rpi_backlight_driver = { ++ .driver = { ++ .name = "rpi-backlight", ++ .of_match_table = of_match_ptr(rpi_backlight_of_match), ++ }, ++ .probe = rpi_backlight_probe, ++}; ++ ++module_platform_driver(rpi_backlight_driver); ++ ++MODULE_AUTHOR("Gordon Hollingworth "); ++MODULE_DESCRIPTION("Raspberry Pi mailbox based Backlight Driver"); ++MODULE_LICENSE("GPL"); +--- a/include/soc/bcm2835/raspberrypi-firmware.h ++++ b/include/soc/bcm2835/raspberrypi-firmware.h +@@ -109,6 +109,7 @@ enum rpi_firmware_property_tag { + RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a, + RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 0x0004800b, + RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC = 0x0004800e, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT = 0x0004800f, + + RPI_FIRMWARE_VCHIQ_INIT = 0x00048010, + diff --git a/target/linux/brcm47xx/Makefile b/target/linux/brcm47xx/Makefile new file mode 100644 index 0000000..e0c44c8 --- /dev/null +++ b/target/linux/brcm47xx/Makefile @@ -0,0 +1,29 @@ +# +# Copyright (C) 2006-2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mipsel +BOARD:=brcm47xx +BOARDNAME:=Broadcom BCM47xx/53xx (MIPS) +FEATURES:=squashfs usb +SUBTARGETS:=generic mips74k legacy +MAINTAINER:=Hauke Mehrtens + +KERNEL_PATCHVER:=4.1 + +include $(INCLUDE_DIR)/target.mk + + +define Target/Description + Build firmware images for Broadcom based BCM47xx/53xx routers with MIPS CPU, *not* ARM. +endef + +DEFAULT_PACKAGES += swconfig wpad-mini nvram otrx \ + kmod-leds-gpio kmod-gpio-button-hotplug \ + kmod-ledtrig-default-on kmod-ledtrig-timer kmod-ledtrig-netdev + +$(eval $(call BuildTarget)) diff --git a/target/linux/brcm47xx/base-files.mk b/target/linux/brcm47xx/base-files.mk new file mode 100644 index 0000000..d6682bd --- /dev/null +++ b/target/linux/brcm47xx/base-files.mk @@ -0,0 +1,5 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef + + diff --git a/target/linux/brcm47xx/base-files/etc/diag.sh b/target/linux/brcm47xx/base-files/etc/diag.sh new file mode 100644 index 0000000..67453e6 --- /dev/null +++ b/target/linux/brcm47xx/base-files/etc/diag.sh @@ -0,0 +1,41 @@ +#!/bin/sh +# Copyright (C) 2006 OpenWrt.org + +. /lib/functions/leds.sh + +get_status_led() { + status_led_file=$(find /sys/class/leds/ -name "*power*" |head -n1) + if [ ! -f $status_led_file ]; then + status_led=$(basename $status_led_file) + return + fi; + status_led_file=$(find /sys/class/leds/ -name "*diag*" |head -n1) + if [ ! -f $status_led_file ]; then + status_led=$(basename $status_led_file) + return + fi; + status_led_file=$(find /sys/class/leds/ -name "*wps*" |head -n1) + if [ ! -f $status_led_file ]; then + status_led=$(basename $status_led_file) + return + fi; +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/brcm47xx/base-files/etc/init.d/netconfig b/target/linux/brcm47xx/base-files/etc/init.d/netconfig new file mode 100755 index 0000000..1890cd0 --- /dev/null +++ b/target/linux/brcm47xx/base-files/etc/init.d/netconfig @@ -0,0 +1,238 @@ +#!/bin/sh /etc/rc.common +# Copyright (C) 2006 OpenWrt.org + +START=05 + +start() { + [ -e /etc/config/network ] && { + local batch + + config_cb() { + case "$1" in + switch) + option_cb() { + case "$1" in + vlan[0-9]|vlan1[0-5]) + local id="${1#vlan}" + local ports="${2%\*}" + append batch "delete network.eth0.${1}${N}" + append batch "set network.eth0_${id}=switch_vlan${N}" + append batch "set network.eth0_${id}.device=eth0${N}" + append batch "set network.eth0_${id}.vlan=${id}${N}" + append batch "set network.eth0_${id}.ports='${ports}'${N}" + ;; + esac + } + ;; + switch_vlan) + option_cb() { :; } + batch="" + ;; + esac + } + + config_load network + + [ -n "$batch" ] && { + logger -t netconfig "migrating switch config to new format ..." + echo "$batch${N}commit network" | uci batch + } + + exit 0 + } + + mkdir -p /etc/config + + local cpuport=5 + [ -e /sbin/swconfig ] && cpuport=$(swconfig dev switch0 help 2>/dev/null | sed -ne "s|.*cpu @ \([0-9]*\).*|\1|p") + local switchname=eth0 + [ -e /sbin/swconfig ] && switchname=$(swconfig dev switch0 help 2>/dev/null | sed -ne "s|switch0: \([^\\\\(]*\).*|\1|p") + local model=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /machine/ {print $2}' /proc/cpuinfo) + + local network_defs=`( + if grep -E 'mtd0: 000(6|a)0000' /proc/mtd 2>&- >&-; then + # WGT634u + echo boardtype=wgt634u + else + strings "$(find_mtd_part nvram)" + fi + ) | awk -v cpuport="$cpuport" -v model="$model" ' + function macinc(mac, maca, i, result) { + split(mac, maca, ":") + for (i = 1; i <= 6; i++) maca[i] = "0x" maca[i] + if (++maca[6] > 0xff) { + maca[5]++ + maca[6] = 0 + } + for (i = 1; i <= 6; i++) { + if (i != 1) result = result ":" + result = result sprintf("%02x", maca[i]) + } + return result + } + + BEGIN { + FS="=" + c["lan_ifname"]="eth0.1" + c["wan_ifname"]="eth0.2" + c["vlan1ports"]="1 2 3 4 5t" + c["vlan2ports"]="0 5t" + for (i = 0; i < 6; i++) { + if (mac_check != "") mac_check = mac_check ":" + mac_check = mac_check "[0-9a-fA-F][0-9a-fA-F]" + } + if (cpuport == "8") { + c["vlan1ports"]="1 2 3 4 8t" + c["vlan2ports"]="0 8t" + } + } + + ($1 == "boardnum") || ($1 == "boardtype") || ($1 == "boardflags") || ($1 ~ /macaddr/) || \ + ($1 ~ /^vlan[0-9]{1,2}ports$/) { + nvram[$1] = $2 + } + + END { + if (((nvram["vlan0ports"] ~ /^0 1 2 3 8/ ) && (nvram["vlan1ports"] ~ /^4 8/ && (cpuport == "8"))) || \ + ((nvram["vlan1ports"] ~ /^0 1 2 3 8/ ) && (nvram["vlan2ports"] ~ /^4 8/ && (cpuport == "8"))) || \ + ((nvram["vlan2ports"] ~ /^0 1 2 3 8/ ) && (nvram["vlan1ports"] ~ /^4 8/ && (cpuport == "8")))) { + c["vlan1ports"] = "0 1 2 3 8t" + c["vlan2ports"] = "4 8t" + } + if (((nvram["vlan0ports"] ~ /^0 1 2 3 5/ ) && (nvram["vlan1ports"] ~ /^4 5/ && (cpuport == "5"))) || \ + ((nvram["vlan1ports"] ~ /^0 1 2 3 5/ ) && (nvram["vlan2ports"] ~ /^4 5/ && (cpuport == "5"))) || \ + ((nvram["vlan2ports"] ~ /^0 1 2 3 5/ ) && (nvram["vlan1ports"] ~ /^4 5/ && (cpuport == "5")))) { + c["vlan1ports"] = "0 1 2 3 5t" + c["vlan2ports"] = "4 5t" + } + if ((model == "Asus WLHDD") || (model == "Asus WL300G")) { + c["wan_ifname"] = "" + c["lan_ifname"] = "eth1" + } + if (model == "Asus WL330GE") { + c["wan_ifname"] = "" + c["lan_ifname"] = "eth0.1" + c["vlan1ports"] = "4 5t" + c["vlan2ports"] = "" + } + if ((model == "Asus WL500G") || (model == "Microsoft MN-700")) { + c["wan_ifname"] = "eth1" + c["lan_ifname"] = "eth0" + } + if ((model == "Asus WL500GP V2") || (model == "Buffalo WHR-G125")) { + c["vlan1ports"] = "0 1 2 3 5t" + c["vlan2ports"] = "4 5t" + } + if (model == "Dell TrueMobile 2300") { + c["lan_ifname"] = "eth0" + c["wan_ifname"] = "eth1" + c["vlan1ports"] = "0 1 2 3 4 5" + c["vlan2ports"] = "" + } + if (nvram["boardtype"] == "bcm94710r4") { + # Toshiba WRC-1000 + c["lan_ifname"] = "eth0" + c["wan_ifname"] = "eth1" + } + if ((nvram["boardtype"] == "wgt634u") || (nvram["boardtype"] == "0x0467")) { + c["vlan1ports"] = "0 1 2 3 5t" + c["vlan2ports"] = "4 5t" + } + if ((nvram["boardtype"] == "0x042f") || (nvram["boardtype"] == "0x0472")) { + if (nvram["boardnum"] == "45") { + # WL-500gP + c["vlan1ports"] = "1 2 3 4 5t" + c["vlan2ports"] = "0 5t" + } else { + # Generic BCM94704 + c["vlan1ports"] = "0 1 2 3 4 5" + c["vlan2ports"] = "" + c["lan_ifname"] = "eth0" + c["wan_ifname"] = "eth1" + + # MAC addresses on 4704 tend to be screwed up. Add a workaround here + if (nvram["et0macaddr"] ~ mac_check) { + c["lan_macaddr"] = nvram["et0macaddr"] + c["wan_macaddr"] = macinc(c["lan_macaddr"]) + } + } + } + # Buffalo WBR-B11 and Buffalo WBR-G54 + if (nvram["boardtype"] == "bcm94710ap") { + c["vlan1ports"] = "0 1 2 3 4 5" + c["vlan2ports"] = "" + c["lan_ifname"] = "eth0" + c["wan_ifname"] = "eth1" + } + + # WAP54G + if ((nvram["boardnum"] == "2") || \ + (nvram["boardnum"] == "1024")) { + c["lan_ifname"]="eth0" + c["wan_ifname"]="" + } + + # Sitecom WL-105b + if ((nvram["boardum"] == "2") && \ + (nvram["GemtekPmonVer"] == "1")) { + c["lan_ifname"]="eth0" + c["wan_ifname"]="" + } + + # ASUS WL-700gE + # These are actually same as defaults above. For some reason this script applies + # Generic BCM94704 settings instead so we revert to proper settings here. + # Hopefully someone will fix this properly soon. + if (model == "Asus WL700") { + c["lan_ifname"]="eth0.1" + c["wan_ifname"]="eth0.2" + c["vlan1ports"]="1 2 3 4 5t" + c["vlan2ports"]="0 5t" + } + if ((model == "Motorola WR850G") || (model == "Siemens SE505 V2")) { + c["vlan1ports"]="0 1 2 3 5t" + c["vlan2ports"]="4 5t" + } + if (model == "Asus WL500W") { + c["lan_ifname"] = "eth0" + c["wan_ifname"] = "eth1" + c["vlan1ports"] = "0 1 2 3 4 5" + c["vlan2ports"] = "" + } + print "local vlan1ports=\"" c["vlan1ports"] "\";" + print "local vlan2ports=\"" c["vlan2ports"] "\";" + print "local lan_ifname=\"" c["lan_ifname"] "\";" + print "local lan_macaddr=\"" c["lan_macaddr"] "\";" + print "local wan_ifname=\"" c["wan_ifname"] "\";" + print "local wan_macaddr=\"" c["wan_macaddr"] "\";" + }'` + + . /lib/functions/uci-defaults.sh + + touch /etc/config/network + + eval "$network_defs" + + [ -n "$vlan1ports" -o -n "$vlan2ports" ] && { + local cfg=`ucidef_add_switch "$switchname" 1 1` + [ -n "$cfg" ] && uci rename network.$cfg=eth0 + [ -n "$vlan1ports" ] && { + cfg=`ucidef_add_switch_vlan "$switchname" 1 "$vlan1ports"` + } + [ -n "$vlan2ports" ] && { + cfg=`ucidef_add_switch_vlan "$switchname" 2 "$vlan2ports"` + } + } + + ucidef_set_interface_loopback + + ucidef_set_interface_lan "$lan_ifname" + [ -n "$lan_macaddr" ] && ucidef_set_interface_macaddr lan "$lan_macaddr" + + [ -n "$wan_ifname" ] && { + ucidef_set_interface_wan "$wan_ifname" + [ -n "$wan_macaddr" ] && ucidef_set_interface_macaddr wan "$wan_macaddr" + } + + uci commit network +} diff --git a/target/linux/brcm47xx/base-files/etc/init.d/wmacfixup b/target/linux/brcm47xx/base-files/etc/init.d/wmacfixup new file mode 100755 index 0000000..ee1b752 --- /dev/null +++ b/target/linux/brcm47xx/base-files/etc/init.d/wmacfixup @@ -0,0 +1,33 @@ +#!/bin/sh /etc/rc.common +# Copyright (C) 2010 OpenWrt.org + +START=41 + +boot() { + [ -d /sys/class/ieee80211 ] || exit + + commit=0 + + fixup_wmac() { + local cfg="$1" + local cfmac + + config_get cfmac "$cfg" macaddr + + [ "$cfmac" != "00:90:4c:5f:00:2a" ] || { + local nvmac="$(nvram get il0macaddr 2>/dev/null)" + [ -n "$nvmac" ] && [ "$nvmac != "$cfmac ] && { + uci set wireless.$cfg.macaddr="$nvmac" + commit=1 + } + } + } + + config_load wireless + config_foreach fixup_wmac wifi-device + + [ "$commit" = 1 ] && uci commit wireless +} + +start() { :; } +stop() { :; } diff --git a/target/linux/brcm47xx/base-files/etc/uci-defaults/03_network_migration b/target/linux/brcm47xx/base-files/etc/uci-defaults/03_network_migration new file mode 100644 index 0000000..cef5add --- /dev/null +++ b/target/linux/brcm47xx/base-files/etc/uci-defaults/03_network_migration @@ -0,0 +1,29 @@ +#!/bin/sh +# +# Copyright (C) 2014 OpenWrt.org +# + +uci show network | grep "\.vlan=0" +[ $? -ne 0 ] && exit 0 + +logger -t network "network config is invalid, creating new one" + +local lan_proto="$(uci -q get network.lan.proto)" +local lan_ipaddr="$(uci -q get network.lan.ipaddr)" +local lan_netmask="$(uci -q get network.lan.netmask)" +local wan_proto="$(uci -q get network.wan.proto)" +local wan_ipaddr="$(uci -q get network.wan.ipaddr)" +local wan_netmask="$(uci -q get network.wan.netmask)" + +rm /etc/config/network +/etc/init.d/netconfig start + +uci set network.lan.proto=$lan_proto +uci set network.lan.ipaddr=$lan_ipaddr +uci set network.lan.netmask=$lan_netmask +uci set network.wan.proto=$wan_proto +uci set network.wan.ipaddr=$wan_ipaddr +uci set network.wan.netmask=$wan_netmask +uci commit network + +exit 0 diff --git a/target/linux/brcm47xx/base-files/etc/uci-defaults/09_fix_crc b/target/linux/brcm47xx/base-files/etc/uci-defaults/09_fix_crc new file mode 100644 index 0000000..346a532 --- /dev/null +++ b/target/linux/brcm47xx/base-files/etc/uci-defaults/09_fix_crc @@ -0,0 +1,7 @@ +#!/bin/sh +# +# Copyright (C) 2007 OpenWrt.org +# +# + +mtd fixtrx firmware diff --git a/target/linux/brcm47xx/base-files/lib/preinit/05_init_interfaces_brcm b/target/linux/brcm47xx/base-files/lib/preinit/05_init_interfaces_brcm new file mode 100644 index 0000000..4b0d0eb --- /dev/null +++ b/target/linux/brcm47xx/base-files/lib/preinit/05_init_interfaces_brcm @@ -0,0 +1,16 @@ +#!/bin/sh + +preinit_iface() { + ifname=eth0 + + # hardware specific overrides + case "$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /machine/ {print $2}' /proc/cpuinfo)" in + "Asus WLHDD") ifname=eth1;; + "Asus WL300G") ifname=eth1;; + esac + + local try=0; + while [ $((try++)) -le 5 ] && [ ! -f /sys/class/net/$ifname/operstate ]; do sleep 1; done +} + +boot_hook_add preinit_main preinit_iface diff --git a/target/linux/brcm47xx/base-files/lib/preinit/15_set_preinit_interface_brcm b/target/linux/brcm47xx/base-files/lib/preinit/15_set_preinit_interface_brcm new file mode 100644 index 0000000..f40e160 --- /dev/null +++ b/target/linux/brcm47xx/base-files/lib/preinit/15_set_preinit_interface_brcm @@ -0,0 +1,16 @@ +#!/bin/sh + +preinit_ip() { + # if the preinit interface isn't specified and ifname is set in + # preinit.arch use that interface + if [ -z "$pi_ifname" ]; then + pi_ifname=$ifname + fi + + [ -n "$pi_ifname" ] && grep -q "$pi_ifname" /proc/net/dev && { + ifconfig $pi_ifname $pi_ip netmask $pi_netmask broadcast $pi_broadcast up + + local try=0; + while [ $((try++)) -le 5 ] && [ ! "$(cat /sys/class/net/$pi_ifname/operstate)" = "up" ]; do sleep 1; done + } +} diff --git a/target/linux/brcm47xx/base-files/lib/upgrade/platform.sh b/target/linux/brcm47xx/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..cbadefb --- /dev/null +++ b/target/linux/brcm47xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,157 @@ +PART_NAME=firmware + +# $(1): file to read magic from +# $(2): offset in bytes +get_magic_long_at() { + dd if="$1" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +platform_machine() { + grep "machine" /proc/cpuinfo | sed "s/.*:[ \t]*//" +} + +platform_expected_image() { + local machine=$(platform_machine) + + case "$machine" in + "Netgear WGR614 V8") echo "chk U12H072T00_NETGEAR"; return;; + "Netgear WGR614 V9") echo "chk U12H094T00_NETGEAR"; return;; + "Netgear WGR614 V10") echo "chk U12H139T01_NETGEAR"; return;; + "Netgear WNDR3300") echo "chk U12H093T00_NETGEAR"; return;; + "Netgear WNDR3400 V1") echo "chk U12H155T00_NETGEAR"; return;; + "Netgear WNDR3400 V2") echo "chk U12H187T00_NETGEAR"; return;; + "Netgear WNDR3400 V3") echo "chk U12H208T00_NETGEAR"; return;; + "Netgear WNDR3400 Vcna") echo "chk U12H155T01_NETGEAR"; return;; + "Netgear WNDR3700 V3") echo "chk U12H194T00_NETGEAR"; return;; + "Netgear WNDR4000") echo "chk U12H181T00_NETGEAR"; return;; + "Netgear WNDR4500 V1") echo "chk U12H189T00_NETGEAR"; return;; + "Netgear WNDR4500 V2") echo "chk U12H224T00_NETGEAR"; return;; + "Netgear WNR2000 V2") echo "chk U12H114T00_NETGEAR"; return;; + "Netgear WNR3500L") echo "chk U12H136T99_NETGEAR"; return;; + "Netgear WNR3500U") echo "chk U12H136T00_NETGEAR"; return;; + "Netgear WNR3500 V2") echo "chk U12H127T00_NETGEAR"; return;; + "Netgear WNR3500 V2vc") echo "chk U12H127T70_NETGEAR"; return;; + "Netgear WNR834B V2") echo "chk U12H081T00_NETGEAR"; return;; + "Linksys E900 V1") echo "cybertan E900"; return;; + "Linksys E1000 V1") echo "cybertan E100"; return;; + "Linksys E1000 V2") echo "cybertan E100"; return;; + "Linksys E1000 V2.1") echo "cybertan E100"; return;; + "Linksys E1200 V2") echo "cybertan E122"; return;; + "Linksys E2000 V1") echo "cybertan 32XN"; return;; + "Linksys E3000 V1") echo "cybertan 61XN"; return;; + "Linksys E3200 V1") echo "cybertan 3200"; return;; + "Linksys E4200 V1") echo "cybertan 4200"; return;; + "Linksys WRT150N V1.1") echo "cybertan N150"; return;; + "Linksys WRT150N V1") echo "cybertan N150"; return;; + "Linksys WRT160N V1") echo "cybertan N150"; return;; + "Linksys WRT160N V3") echo "cybertan N150"; return;; + "Linksys WRT300N V1") echo "cybertan EWCB"; return;; + "Linksys WRT300N V1.1") echo "cybertan EWC2"; return;; + "Linksys WRT310N V1") echo "cybertan 310N"; return;; + "Linksys WRT310N V2") echo "cybertan 310N"; return;; + "Linksys WRT610N V1") echo "cybertan 610N"; return;; + "Linksys WRT610N V2") echo "cybertan 610N"; return;; + esac +} + +brcm47xx_identify() { + local magic + + magic=$(get_magic_long "$1") + case "$magic" in + "48445230") + echo "trx" + return + ;; + "2a23245e") + echo "chk" + return + ;; + esac + + magic=$(get_magic_long_at "$1" 14) + [ "$magic" = "55324e44" ] && { + echo "cybertan" + return + } + + echo "unknown" +} + +platform_check_image() { + [ "$#" -gt 1 ] && return 1 + + local file_type=$(brcm47xx_identify "$1") + local magic + local error=0 + + case "$file_type" in + "chk") + local header_len=$((0x$(get_magic_long_at "$1" 4))) + local board_id_len=$(($header_len - 40)) + local board_id=$(dd if="$1" skip=40 bs=1 count=$board_id_len 2>/dev/null | hexdump -v -e '1/1 "%c"') + local dev_board_id=$(platform_expected_image) + echo "Found CHK image with device board_id $board_id" + + [ -n "$dev_board_id" -a "chk $board_id" != "$dev_board_id" ] && { + echo "Firmware board_id doesn't match device board_id ($dev_board_id)" + error=1 + } + + if ! otrx check "$1" -o "$header_len"; then + echo "No valid TRX firmware in the CHK image" + error=1 + fi + ;; + "cybertan") + local pattern=$(dd if="$1" bs=1 count=4 2>/dev/null | hexdump -v -e '1/1 "%c"') + local dev_pattern=$(platform_expected_image) + echo "Found CyberTAN image with device pattern: $pattern" + + [ -n "$dev_pattern" -a "cybertan $pattern" != "$dev_pattern" ] && { + echo "Firmware pattern doesn't match device pattern ($dev_pattern)" + error=1 + } + + if ! otrx check "$1" -o 32; then + echo "No valid TRX firmware in the CyberTAN image" + error=1 + fi + ;; + "trx") + if ! otrx check "$1"; then + echo "Invalid (corrupted?) TRX firmware" + error=1 + fi + ;; + *) + echo "Invalid image type. Please use only .trx files" + error=1 + ;; + esac + + return $error +} + +platform_trx_from_chk_cmd() { + local header_len=$((0x$(get_magic_long_at "$1" 4))) + + echo -n dd bs=$header_len skip=1 +} + +platform_trx_from_cybertan_cmd() { + echo -n dd bs=32 skip=1 +} + +platform_do_upgrade() { + local file_type=$(brcm47xx_identify "$1") + local trx="$1" + local cmd="" + + case "$file_type" in + "chk") cmd=$(platform_trx_from_chk_cmd "$trx");; + "cybertan") cmd=$(platform_trx_from_cybertan_cmd "$trx");; + esac + + default_do_upgrade "$trx" "$cmd" +} diff --git a/target/linux/brcm47xx/config-4.1 b/target/linux/brcm47xx/config-4.1 new file mode 100644 index 0000000..bae7013 --- /dev/null +++ b/target/linux/brcm47xx/config-4.1 @@ -0,0 +1,184 @@ +CONFIG_ADM6996_PHY=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_B53=y +# CONFIG_B53_MMAP_DRIVER is not set +CONFIG_B53_PHY_DRIVER=y +CONFIG_B53_PHY_FIXUP=y +# CONFIG_B53_SRAB_DRIVER is not set +CONFIG_BCM47XX=y +CONFIG_BCM47XX_BCMA=y +CONFIG_BCM47XX_SSB=y +CONFIG_BCM47XX_WDT=y +CONFIG_BCMA=y +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_DEBUG=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_MIPS=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_NFLASH=y +CONFIG_BCMA_SFLASH=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +# CONFIG_CPU_BMIPS is not set +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +# CONFIG_EARLY_PRINTK is not set +CONFIG_FIXED_PHY=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_WDT=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_GPIO_REGISTER=y +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_BCM47XXSFLASH=y +CONFIG_MTD_BCM47XX_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_BCM47XXNFLASH=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_PHYSMAP=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SRCU=y +CONFIG_SSB=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_DEBUG=y +CONFIG_SSB_DRIVER_EXTIF=y +CONFIG_SSB_DRIVER_GIGE=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_SSB_DRIVER_MIPS=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_EMBEDDED=y +CONFIG_SSB_PCICORE_HOSTMODE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_SERIAL=y +CONFIG_SSB_SFLASH=y +CONFIG_SSB_SPROM=y +CONFIG_SWCONFIG=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_BMIPS=y +CONFIG_SYS_HAS_CPU_BMIPS32_3300=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y +CONFIG_WATCHDOG_CORE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/brcm47xx/generic/profiles/100-Broadcom-b43.mk b/target/linux/brcm47xx/generic/profiles/100-Broadcom-b43.mk new file mode 100644 index 0000000..4c420fb --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/100-Broadcom-b43.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2007-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-b43 + NAME:=Broadcom SoC, all Ethernet, BCM43xx WiFi (b43, default) + PACKAGES:=kmod-b44 kmod-tg3 kmod-bgmac kmod-b43 kmod-b43legacy +endef + +define Profile/Broadcom-b43/Description + Package set compatible with hardware any Broadcom BCM47xx or BCM535x + SoC with Broadcom BCM43xx Wifi cards using the mac80211, b43 and + b43legacy drivers and b44, tg3 or bgmac Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-b43)) + diff --git a/target/linux/brcm47xx/generic/profiles/101-Broadcom-wl.mk b/target/linux/brcm47xx/generic/profiles/101-Broadcom-wl.mk new file mode 100644 index 0000000..21265da --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/101-Broadcom-wl.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2010-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-wl + NAME:=Broadcom SoC, all Ethernet, BCM43xx WiFi (wl, proprietary) + PACKAGES:=-wpad-mini kmod-b44 kmod-tg3 kmod-bgmac kmod-brcm-wl wlc nas +endef + +define Profile/Broadcom-wl/Description + Package set compatible with hardware any Broadcom BCM47xx or BCM535x + SoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom + wireless "wl" driver and b44, tg3 or bgmac Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-wl)) + diff --git a/target/linux/brcm47xx/generic/profiles/104-Broadcom-ath5k.mk b/target/linux/brcm47xx/generic/profiles/104-Broadcom-ath5k.mk new file mode 100644 index 0000000..ca5295f --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/104-Broadcom-ath5k.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-ath5k + NAME:=Broadcom SoC, all Ethernet, Atheros WiFi (ath5k) + PACKAGES:=kmod-b44 kmod-tg3 kmod-bgmac kmod-ath5k +endef + +define Profile/Broadcom-ath5k/Description + Package set compatible with hardware any Broadcom BCM47xx or BCM535x + SoC with Atheros Wifi cards using the mac80211 and ath5k drivers and + b44, tg3 or bgmac Ethernet driver. +endef +$(eval $(call Profile,Broadcom-ath5k)) + diff --git a/target/linux/brcm47xx/generic/profiles/105-Broadcom-none.mk b/target/linux/brcm47xx/generic/profiles/105-Broadcom-none.mk new file mode 100644 index 0000000..301d02a --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/105-Broadcom-none.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-none + NAME:=Broadcom SoC, all Ethernet, No WiFi + PACKAGES:=-wpad-mini kmod-b44 kmod-tg3 kmod-bgmac +endef + +define Profile/Broadcom-none/Description + Package set compatible with hardware any Broadcom BCM47xx or BCM535x + SoC without any Wifi cards and b44, tg3 or bgmac Ethernet driver. +endef +$(eval $(call Profile,Broadcom-none)) + diff --git a/target/linux/brcm47xx/generic/profiles/200-Broadcom-b44-b43.mk b/target/linux/brcm47xx/generic/profiles/200-Broadcom-b44-b43.mk new file mode 100644 index 0000000..662a7c8 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/200-Broadcom-b44-b43.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2007-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-b44-b43 + NAME:=Broadcom SoC, b44 Ethernet, BCM43xx WiFi (b43, default) + PACKAGES:=kmod-b44 kmod-b43 kmod-b43legacy +endef + +define Profile/Broadcom-b44-b43/Description + Package set compatible with hardware older Broadcom BCM47xx or BCM535x + SoC with Broadcom BCM43xx Wifi cards using the mac80211, b43 and + b43legacy drivers and b44 Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-b44-b43)) + diff --git a/target/linux/brcm47xx/generic/profiles/201-Broadcom-b44-wl.mk b/target/linux/brcm47xx/generic/profiles/201-Broadcom-b44-wl.mk new file mode 100644 index 0000000..f974c00 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/201-Broadcom-b44-wl.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2010-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-b44-wl + NAME:=Broadcom SoC, b44 Ethernet, BCM43xx WiFi (wl, proprietary) + PACKAGES:=-wpad-mini kmod-b44 kmod-brcm-wl wlc nas +endef + +define Profile/Broadcom-b44-wl/Description + Package set compatible with hardware older Broadcom BCM47xx or BCM535x + SoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom + wireless "wl" driver and b44 Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-b44-wl)) + diff --git a/target/linux/brcm47xx/generic/profiles/204-Broadcom-b44-ath5k.mk b/target/linux/brcm47xx/generic/profiles/204-Broadcom-b44-ath5k.mk new file mode 100644 index 0000000..e9dda49 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/204-Broadcom-b44-ath5k.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-b44-ath5k + NAME:=Broadcom SoC, b44 Ethernet, Atheros WiFi (ath5k) + PACKAGES:=kmod-b44 kmod-ath5k +endef + +define Profile/Broadcom-b44-ath5k/Description + Package set compatible with hardware older Broadcom BCM47xx or BCM535x + SoC with Atheros Wifi cards using the mac80211 and ath5k drivers and + b44 Ethernet driver. +endef +$(eval $(call Profile,Broadcom-b44-ath5k)) + diff --git a/target/linux/brcm47xx/generic/profiles/205-Broadcom-b44-none.mk b/target/linux/brcm47xx/generic/profiles/205-Broadcom-b44-none.mk new file mode 100644 index 0000000..a936bba --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/205-Broadcom-b44-none.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-b44-none + NAME:=Broadcom SoC, b44 Ethernet, No WiFi + PACKAGES:=-wpad-mini kmod-b44 +endef + +define Profile/Broadcom-b44-none/Description + Package set compatible with hardware older Broadcom BCM47xx or BCM535x + SoC without any Wifi cards and b44 Ethernet driver. +endef +$(eval $(call Profile,Broadcom-b44-none)) + diff --git a/target/linux/brcm47xx/generic/profiles/210-Broadcom-tg3-b43.mk b/target/linux/brcm47xx/generic/profiles/210-Broadcom-tg3-b43.mk new file mode 100644 index 0000000..a0bece9 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/210-Broadcom-tg3-b43.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2007-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-tg3-b43 + NAME:=Broadcom SoC, tg3 Ethernet, BCM43xx WiFi (b43) + PACKAGES:=kmod-b43 kmod-tg3 +endef + +define Profile/Broadcom-tg3-b43/Description + Package set compatible with hardware Broadcom BCM4705/BCM4785 + SoCs with Broadcom BCM43xx Wifi cards using the mac80211 and b43 + driver and tg3 Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-tg3-b43)) + diff --git a/target/linux/brcm47xx/generic/profiles/211-Broadcom-tg3-wl.mk b/target/linux/brcm47xx/generic/profiles/211-Broadcom-tg3-wl.mk new file mode 100644 index 0000000..24ac234 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/211-Broadcom-tg3-wl.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2010-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-tg3-wl + NAME:=Broadcom SoC, tg3 Ethernet, BCM43xx WiFi (wl, proprietary) + PACKAGES:=-wpad-mini kmod-brcm-wl wlc nas kmod-tg3 +endef + +define Profile/Broadcom-tg3-wl/Description + Package set compatible with hardware Broadcom BCM4705/BCM4785 + SoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom + wireless "wl" driver and tg3 Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-tg3-wl)) + diff --git a/target/linux/brcm47xx/generic/profiles/215-Broadcom-tg3-none.mk b/target/linux/brcm47xx/generic/profiles/215-Broadcom-tg3-none.mk new file mode 100644 index 0000000..2d13ca8 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/215-Broadcom-tg3-none.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-tg3-none + NAME:=Broadcom SoC, tg3 Ethernet, no WiFi + PACKAGES:=-wpad-mini kmod-tg3 +endef + +define Profile/Broadcom-tg3-none/Description + Package set compatible with hardware Broadcom BCM4705/BCM4785 + SoC without any Wifi cards and tg3 Ethernet driver. +endef +$(eval $(call Profile,Broadcom-tg3-none)) + diff --git a/target/linux/brcm47xx/generic/profiles/220-Broadcom-bgmac-b43.mk b/target/linux/brcm47xx/generic/profiles/220-Broadcom-bgmac-b43.mk new file mode 100644 index 0000000..6ef0691 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/220-Broadcom-bgmac-b43.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2007-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-bgmac-b43 + NAME:=Broadcom SoC, bgmac Ethernet, BCM43xx WiFi (b43) + PACKAGES:=kmod-bgmac kmod-b43 +endef + +define Profile/Broadcom-bgmac-b43/Description + Package set compatible with hardware newer Broadcom BCM47xx or BCM535x + SoC with Broadcom BCM43xx Wifi cards using the mac80211 and b43 + drivers and bgmac Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-bgmac-b43)) + diff --git a/target/linux/brcm47xx/generic/profiles/221-Broadcom-bgmac-wl.mk b/target/linux/brcm47xx/generic/profiles/221-Broadcom-bgmac-wl.mk new file mode 100644 index 0000000..f671cd9 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/221-Broadcom-bgmac-wl.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2010-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-bgmac-wl + NAME:=Broadcom SoC, bgmac Ethernet, BCM43xx WiFi (wl, proprietary) + PACKAGES:=-wpad-mini kmod-bgmac kmod-brcm-wl wlc nas +endef + +define Profile/Broadcom-bgmac-wl/Description + Package set compatible with hardware newer Broadcom BCM47xx or BCM535x + SoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom + wireless "wl" driver and bgmac Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-bgmac-wl)) + diff --git a/target/linux/brcm47xx/generic/profiles/225-Broadcom-bgmac-none.mk b/target/linux/brcm47xx/generic/profiles/225-Broadcom-bgmac-none.mk new file mode 100644 index 0000000..0512119 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/225-Broadcom-bgmac-none.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2006-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-bgmac-none + NAME:=Broadcom SoC, bgmac Ethernet, No WiFi + PACKAGES:=-wpad-mini kmod-bgmac +endef + +define Profile/Broadcom-bgmac-none/Description + Package set compatible with hardware newer Broadcom BCM47xx or BCM535x + SoC without any Wifi cards and bgmac Ethernet driver. +endef +$(eval $(call Profile,Broadcom-bgmac-none)) + diff --git a/target/linux/brcm47xx/generic/profiles/226-Broadcom-bgmac-brcsmac.mk b/target/linux/brcm47xx/generic/profiles/226-Broadcom-bgmac-brcsmac.mk new file mode 100644 index 0000000..d9dc9e7 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/226-Broadcom-bgmac-brcsmac.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2007-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-bgmac-brcmsmac + NAME:=Broadcom SoC, bgmac Ethernet, BCM43xx WiFi (brcmsmac) + PACKAGES:=kmod-bgmac kmod-brcmsmac +endef + +define Profile/Broadcom-bgmac-brcmsmac/Description + Package set compatable with newer gigabit + N based bcm47xx SoCs with + Broadcom BCM43xx Wifi cards using the mac80211 brcmsmac driver and + bgmac Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-bgmac-brcmsmac)) + diff --git a/target/linux/brcm47xx/generic/profiles/PS-1208MFG.mk b/target/linux/brcm47xx/generic/profiles/PS-1208MFG.mk new file mode 100644 index 0000000..e68c9a2 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/PS-1208MFG.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2007-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Ps1208mfg + NAME:=Edimax PS-1208MFG + PACKAGES:=-firewall -dropbear -dnsmasq -mtd -ppp -wpad-mini kmod-b44 block-mount kmod-usb-storage kmod-usb2 kmod-usb-ohci -iptables -swconfig kmod-fs-ext4 +endef + +define Profile/Ps1208mfg/Description + Package set optimize for edimax PS-1208MFG printserver +endef + +$(eval $(call Profile,Ps1208mfg)) + diff --git a/target/linux/brcm47xx/generic/profiles/WGT634U.mk b/target/linux/brcm47xx/generic/profiles/WGT634U.mk new file mode 100644 index 0000000..16c8d9d --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/WGT634U.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WGT634U + NAME:=Netgear WGT634U + PACKAGES:=kmod-b44 kmod-ath5k kmod-usb-core kmod-usb2 kmod-ocf-ubsec-ssb +endef + +define Profile/WGT634U/Description + Package set compatible with the Netgear WGT634U. Contains USB support +endef +$(eval $(call Profile,WGT634U)) + diff --git a/target/linux/brcm47xx/generic/profiles/WL500GPv1-ATH.mk b/target/linux/brcm47xx/generic/profiles/WL500GPv1-ATH.mk new file mode 100644 index 0000000..3cdd8a0 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/WL500GPv1-ATH.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WL500GPv1 + NAME:=ASUS WL-500g Premium v1 (Atheros WiFi using ath5k) + PACKAGES:=kmod-b44 kmod-ath5k kmod-usb-core kmod-usb-uhci kmod-usb2 +endef + +define Profile/WL500GPv1/Description + Package set optimized for the WL-500g Premium v1 with USB and Atheros WiFi card support +endef +$(eval $(call Profile,WL500GPv1)) diff --git a/target/linux/brcm47xx/generic/profiles/WRT350Nv1.mk b/target/linux/brcm47xx/generic/profiles/WRT350Nv1.mk new file mode 100644 index 0000000..c861615 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/WRT350Nv1.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WRT350Nv1 + NAME:=Linksys WRT350Nv1 + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-tg3 kmod-ocf-ubsec-ssb +endef + +define Profile/WRT350Nv1/Description + Package set compatible with the Linksys WRT350Nv1. Contains USB support +endef +$(eval $(call Profile,WRT350Nv1)) diff --git a/target/linux/brcm47xx/generic/profiles/WRTSL54GS.mk b/target/linux/brcm47xx/generic/profiles/WRTSL54GS.mk new file mode 100644 index 0000000..e5bb908 --- /dev/null +++ b/target/linux/brcm47xx/generic/profiles/WRTSL54GS.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WRTSL54GS + NAME:=Linksys WRTSL54GS + PACKAGES:=kmod-b44 kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-usb-storage kmod-scsi-core kmod-fs-ext4 e2fsprogs kmod-b43 +endef + +define Profile/WRTSL54GS/Description + Package set compatible with the Linksys WRTSL54GS. Contains USB support +endef +$(eval $(call Profile,WRTSL54GS)) + diff --git a/target/linux/brcm47xx/generic/target.mk b/target/linux/brcm47xx/generic/target.mk new file mode 100644 index 0000000..71fde52 --- /dev/null +++ b/target/linux/brcm47xx/generic/target.mk @@ -0,0 +1,7 @@ +BOARDNAME:=Generic +FEATURES+=pcmcia + +define Target/Description + Build generic firmware for all Broadcom BCM47xx and BCM53xx MIPS + devices. It runs on both architectures BMIPS3300 and MIPS 74K. +endef diff --git a/target/linux/brcm47xx/image/Makefile b/target/linux/brcm47xx/image/Makefile new file mode 100644 index 0000000..8063de0 --- /dev/null +++ b/target/linux/brcm47xx/image/Makefile @@ -0,0 +1,383 @@ +# +# Copyright (C) 2006-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Build/Clean + $(MAKE) -C lzma-loader clean +endef + +define Image/Prepare + # Optimized LZMA compression (with dictionary), handled by lzma-loader. + cat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma + + # Less optimal LZMA compression (no dictionary), handled by CFE. + $(STAGING_DIR_HOST)/bin/lzma e -so -d16 $(KDIR)/vmlinux > $(KDIR)/vmlinux-nodictionary.lzma + + gzip -nc9 $(KDIR)/vmlinux > $(KDIR)/vmlinux.gz +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + cat $(KDIR)/vmlinux-initramfs | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux-initramfs.lzma + $(STAGING_DIR_HOST)/bin/lzma e -so -d16 $(KDIR)/vmlinux-initramfs > $(KDIR)/vmlinux-initramfs-nodictionary.lzma +endif + rm -f $(KDIR)/loader.gz + $(MAKE) -C lzma-loader \ + BUILD_DIR="$(KDIR)" \ + TARGET="$(KDIR)" \ + clean install + echo -ne "\\x00" >> $(KDIR)/loader.gz + rm -f $(KDIR)/fs_mark + echo -ne '\xde\xad\xc0\xde' > $(KDIR)/fs_mark + $(call prepare_generic_squashfs,$(KDIR)/fs_mark) +endef + +define Image/Build/wgt634u + dd if=$(KDIR)/loader.elf of=$(BIN_DIR)/$(IMG_PREFIX)-wgt634u-$(2).bin bs=131072 conv=sync + cat $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx >> $(BIN_DIR)/$(IMG_PREFIX)-wgt634u-$(2).bin +endef + +define Image/Build/dwl3150 + cp $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx $(BIN_DIR)/$(IMG_PREFIX)-dwl3150-$(2).bin + echo "BCM-5352-2050-0000000-01" >> $(BIN_DIR)/$(IMG_PREFIX)-dwl3150-$(2).bin +endef + +# $(1): filesystem type. +# $(2): device model (used for output file). +# $(3): pattern (device specific magic). +# $(4): version. +# $(5): simplified filesystem type (without block size). +define Image/Build/CyberTAN + $(STAGING_DIR_HOST)/bin/addpattern -4 -p $(3) -v v$(4) -i $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(5).bin $(if $(6),-s $(6)) +endef +define Image/Build/CyberTAN2 + $(STAGING_DIR_HOST)/bin/addpattern -4 -p $(3) -v v$(4) -i $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(5).noheader.bin -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(5).bin $(if $(6),-s $(6)) +endef +define Image/Build/CyberTANHead + $(STAGING_DIR_HOST)/bin/addpattern -5 -p $(3) -v v$(4) -i /dev/null -o $(KDIR)/$(IMG_PREFIX)-$(2)-header.bin $(if $(6),-s $(6)) +endef + +define Image/Build/Motorola + $(STAGING_DIR_HOST)/bin/motorola-bin -$(3) $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(4).bin +endef + +define Image/Build/USR + $(STAGING_DIR_HOST)/bin/trx2usr $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(3).bin +endef + +define Image/Build/Edi + $(STAGING_DIR_HOST)/bin/trx2edips $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(3).bin +endef + +define Image/Build/Huawei + dd if=/dev/zero of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(3)-gz.bin bs=92 count=1 + echo -ne 'HDR0\x08\x00\x00\x00' >> $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(3)-gz.bin + cat $(BIN_DIR)/$(IMG_PREFIX)-$(1)-gz.trx >> $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(3)-gz.bin +endef + +# $(1): filesystem type. +# $(2): device model (used for output file). +# $(3): board_id (device specific magic). +# $(4): region. +# $(5): simplified filesystem type (without block size). +define Image/Build/Chk + $(STAGING_DIR_HOST)/bin/mkchkimg -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(5).chk -k $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx -b $(3) -r $(4) +endef + +define trxalign/jffs2-128k +-a 0x20000 -f $(KDIR)/root.$(1) +endef +define trxalign/jffs2-64k +-a 0x10000 -f $(KDIR)/root.$(1) +endef +define trxalign/squashfs +-a 1024 -f $(KDIR)/root.$(1) $(if $(2),-f $(2)) -a 0x10000 -A $(KDIR)/fs_mark +endef + +define Image/Build/trxV2 + $(call Image/Build/CyberTANHead,$(1),$(2),$(3),$(4),$(5),$(if $(6),$(6))) + $(STAGING_DIR_HOST)/bin/trx \ + -m 33554432 \ + -2 \ + -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(5).noheader.bin \ + -f $(KDIR)/loader.gz \ + -f $(KDIR)/vmlinux.lzma \ + $(call trxalign/$(1),$(1),$(KDIR)/$(IMG_PREFIX)-$(2)-header.bin) + $(call Image/Build/CyberTAN2,$(1),$(2),$(3),$(4),$(5),$(if $(6),$(6))) +endef + +################################################# +# Images +################################################# + +define Build/trx-with-loader + $(STAGING_DIR_HOST)/bin/trx \ + -m 33554432 \ + -o $@ \ + -f $(KDIR)/loader.gz \ + -f $(word 1,$^) \ + $(call trxalign/$(FILESYSTEM),$(FILESYSTEM)) +endef + +define Build/asus-trx + $(STAGING_DIR_HOST)/bin/asustrx -p "$(PRODUCTID)" -i $@ -o $@.new + mv $@.new $@ +endef + +define Build/linksys-bin + $(STAGING_DIR_HOST)/bin/addpattern -4 -p $(DEVICE_ID) -v v$(VERSION) -i $@ -o $@.new + mv $@.new $@ +endef + +################################################# +# Devices +################################################# + +DEVICE_VARS += PRODUCTID +DEVICE_VARS += DEVICE_ID VERSION +DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_REGION + +define Device/Default + KERNEL := kernel-bin + IMAGE_NAME = $$(IMAGE_PREFIX)-$$(1).$$(2) + KERNEL_NAME = vmlinux.lzma + FILESYSTEMS := $(FS_64K) + IMAGES := trx + IMAGE/trx := trx-with-loader +endef + +define Device/asus + IMAGES := trx + IMAGE/trx := trx-with-loader | asus-trx +endef + +define AsusDevice + define Device/asus-$(1) + $$(Device/asus) + PRODUCTID := $(2) + endef + TARGET_DEVICES += asus-$(1) +endef + +define Device/linksys + IMAGES := bin + IMAGE/bin := trx-with-loader | linksys-bin +endef + +define LinksysDevice + define Device/linksys-$(1) + $$(Device/linksys) + DEVICE_ID := $(2) + VERSION := $(3) + endef + TARGET_DEVICES += linksys-$(1) +endef + +define Device/netgear + IMAGES := chk + IMAGE/chk := trx-with-loader | netgear-chk +endef + +define NetgearDevice + define Device/netgear-$(1) + $$(Device/netgear) + NETGEAR_BOARD_ID := $(2) + NETGEAR_REGION := $(3) + endef + TARGET_DEVICES += netgear-$(1) +endef + +################################################# +# Subtarget generic +################################################# + +ifeq ($(SUBTARGET),generic) + # BCM4705 with tg3 + $(eval $(call LinksysDevice,wrt300n-v1.1,EWC2,1.51.2)) + $(eval $(call LinksysDevice,wrt310n-v1,310N,1.0.10)) + $(eval $(call LinksysDevice,wrt350n-v1,EWCG,1.04.1)) + $(eval $(call LinksysDevice,wrt610n-v1,610N,1.0.1)) + + # BCMA SoC with SSB WiFi + $(eval $(call LinksysDevice,wrt610n-v2,610N,2.0.0)) + $(eval $(call LinksysDevice,e3000-v1,61XN,1.0.3)) +endif + +################################################# +# Subtarget legacy +################################################# + +# $(1): filesystem type. +define Image/Build/legacy/devices-with-128k-blocks + $(call Image/Build/trxV2,$(1),wrt54g3gv2-vf,3G2V,3.00.24,$(patsubst jffs2-%,jffs2,$(1)),6) + $(call Image/Build/wgt634u,$(1),$(patsubst jffs2-%,jffs2,$(1))) +endef + +# $(1): filesystem type. +define Image/Build/legacy/devices-with-64k-blocks + $(call Image/Build/dwl3150,$(1),$(patsubst jffs2-%,jffs2,$(1))) + $(call Image/Build/Edi,$(1),ps1208mfg,$(patsubst jffs2-%,jffs2,$(1))) + $(call Image/Build/Huawei,$(1),e970,$(1)) + $(call Image/Build/Motorola,$(1),wa840g,2,$(patsubst jffs2-%,jffs2,$(1))) + $(call Image/Build/Motorola,$(1),we800g,3,$(patsubst jffs2-%,jffs2,$(1))) + $(call Image/Build/Motorola,$(1),wr850g,1,$(1)) + $(call Image/Build/USR,$(1),usr5461,$(1)) +endef + +# $(1): filesystem type. +define Image/Build/legacy/jffs2-64k + $(call Image/Build/legacy/devices-with-64k-blocks,$(1)) +endef + +# $(1): filesystem type. +define Image/Build/legacy/jffs2-128k + $(call Image/Build/legacy/devices-with-128k-blocks,$(1)) +endef + +# $(1): filesystem type. +define Image/Build/legacy/squashfs + $(call Image/Build/legacy/devices-with-64k-blocks,$(1)) + $(call Image/Build/legacy/devices-with-128k-blocks,$(1)) +endef + +define Device/linksys-wrt54gs + $(Device/linksys) + FILESYSTEMS := $(FS_128K) + DEVICE_ID := W54S + VERSION := 4.80.1 +endef + +define Device/linksys-wrtsl54gs + $(Device/linksys) + FILESYSTEMS := $(FS_128K) + DEVICE_ID := W54U + VERSION := 2.08.1 +endef + +ifeq ($(SUBTARGET),legacy) + TARGET_DEVICES += \ + linksys-wrt54gs \ + linksys-wrtsl54gs + + $(eval $(call AsusDevice,wl-300g,WL300g )) + $(eval $(call AsusDevice,wl-320gp,WL320gP )) + $(eval $(call AsusDevice,wl-330ge,WL-330gE )) + $(eval $(call AsusDevice,wl-500gp-v1,WL500gp )) + $(eval $(call AsusDevice,wl-500gp-v2,WL500gpv2 )) + $(eval $(call AsusDevice,wl-500w,WL500W )) + $(eval $(call AsusDevice,wl-520gu,WL520gu )) + $(eval $(call AsusDevice,wl-550ge,WL550gE )) + $(eval $(call AsusDevice,wl-hdd25,WLHDD )) + $(eval $(call LinksysDevice,wrt54g3g,W54F,2.20.1)) + $(eval $(call LinksysDevice,wrt54g3g-em,W3GN,2.20.1)) + $(eval $(call LinksysDevice,wrt54g,W54G,4.71.1)) + $(eval $(call LinksysDevice,wrt54gs-v4,W54s,1.09.1)) + $(eval $(call LinksysDevice,wrt150n,N150,1.51.3)) + $(eval $(call LinksysDevice,wrt160n-v1,N150,1.50.1)) + $(eval $(call LinksysDevice,wrt300n-v1,EWCB,1.03.6)) + $(eval $(call NetgearDevice,wgr614-v8,U12H072T00_NETGEAR,2)) + $(eval $(call NetgearDevice,wndr3300-v1,U12H093T00_NETGEAR,2)) + $(eval $(call NetgearDevice,wnr834b-v2,U12H081T00_NETGEAR,2)) +endif + +################################################# +# Subtarget mips74k +################################################# + +ifeq ($(SUBTARGET),mips74k) + $(eval $(call AsusDevice,rt-ac53u,RT-AC53U)) +# $(eval $(call AsusDevice,rt-ac66u,RT-AC66U)) + $(eval $(call AsusDevice,rt-n10,RT-N10 )) + $(eval $(call AsusDevice,rt-n10p,RT-N10P)) + $(eval $(call AsusDevice,rt-n10p-v2,RT-N10PV2)) + $(eval $(call AsusDevice,rt-n10u,RT-N10U)) + $(eval $(call AsusDevice,rt-n10u-b,RT-N10U)) + $(eval $(call AsusDevice,rt-n12,RT-N12 )) + $(eval $(call AsusDevice,rt-n12-b1,RT-N12B1)) + $(eval $(call AsusDevice,rt-n12-c1,RT-N12C1)) + $(eval $(call AsusDevice,rt-n12-d1,RT-N12D1)) + $(eval $(call AsusDevice,rt-n12hp,RT-N12HP)) + $(eval $(call AsusDevice,rt-n14uhp,RT-N14UHP)) + $(eval $(call AsusDevice,rt-n15u,RT-N15U)) + $(eval $(call AsusDevice,rt-n16,RT-N16)) + $(eval $(call AsusDevice,rt-n53,RT-N53)) + $(eval $(call AsusDevice,rt-n66u,RT-N66U)) + $(eval $(call AsusDevice,rt-n66w,RT-N66U)) + $(eval $(call LinksysDevice,wrt160n-v3,N150,3.0.3)) + $(eval $(call LinksysDevice,wrt310n-v2,310N,2.0.1)) + $(eval $(call LinksysDevice,wrt320n-v1,320N,1.0.5)) + $(eval $(call LinksysDevice,e900-v1,E900,1.0.4)) + $(eval $(call LinksysDevice,e1000-v1-v2-v2.1,E100,1.1.3)) + $(eval $(call LinksysDevice,e1200-v1,E120,1.0.3)) + $(eval $(call LinksysDevice,e1200-v2,E122,1.0.4)) + $(eval $(call LinksysDevice,e1500-v1,E150,1.0.5)) + $(eval $(call LinksysDevice,e1550-v1,1550,1.0.3)) + $(eval $(call LinksysDevice,e2000-v1,32XN,1.0.4)) + $(eval $(call LinksysDevice,e2500-v1,E25X,1.0.7)) + $(eval $(call LinksysDevice,e2500-v2,E25X,2.0.0)) + $(eval $(call LinksysDevice,e2500-v2.1,25RU,2.1.0)) + $(eval $(call LinksysDevice,e2500-v3,25V3,3.0.0)) + $(eval $(call LinksysDevice,e3200-v1,3200,1.0.1)) + $(eval $(call LinksysDevice,e4200-v1,4200,1.0.5)) + $(eval $(call NetgearDevice,wgr614-v10_north-america,U12H139T01_NETGEAR,2)) + $(eval $(call NetgearDevice,wgr614-v10_other-regions,U12H139T01_NETGEAR,1)) + $(eval $(call NetgearDevice,wndr3400-v1,U12H155T00_NETGEAR,2)) + $(eval $(call NetgearDevice,wndr3400-v2,U12H187T00_NETGEAR,2)) + $(eval $(call NetgearDevice,wndr3400-v3,U12H208T00_NETGEAR,1)) + $(eval $(call NetgearDevice,wndr3700-v3,U12H194T00_NETGEAR,2)) + $(eval $(call NetgearDevice,wndr4000,U12H181T00_NETGEAR,2)) + $(eval $(call NetgearDevice,wnr1000-v3,U12H139T00_NETGEAR,2)) + $(eval $(call NetgearDevice,wnr2000v2,U12H114T00_NETGEAR,2)) + $(eval $(call NetgearDevice,wnr3000rp,U12H163T01_NETGEAR,1)) + $(eval $(call NetgearDevice,wnr3500l-v1-north-america,U12H136T99_NETGEAR,2)) + $(eval $(call NetgearDevice,wnr3500l-v1-other-regions,U12H136T99_NETGEAR,1)) + $(eval $(call NetgearDevice,wnr3500l-v2,U12H172T00_NETGEAR,1)) + $(eval $(call NetgearDevice,wnr3500-v2,U12H127T00_NETGEAR,2)) +endif + +################################################# +# Shared BuildImage defines +################################################# + +define Image/Build/Initramfs + $(STAGING_DIR_HOST)/bin/trx \ + -m 33554432 \ + -o $(BIN_DIR)/$(IMG_PREFIX)-initramfs.trx \ + -f $(KDIR)/loader.gz \ + -f $(KDIR)/vmlinux-initramfs.lzma + $(STAGING_DIR_HOST)/bin/trx \ + -m 33554432 \ + -o $(BIN_DIR)/$(IMG_PREFIX)-initramfs-noloader-nodictionary.trx \ + -f $(KDIR)/vmlinux-initramfs-nodictionary.lzma +endef + +# $(1): filesystem type. +define Image/Build + $(STAGING_DIR_HOST)/bin/trx \ + -m 33554432 \ + -o $(BIN_DIR)/$(IMG_PREFIX)-$(1).trx \ + -f $(KDIR)/loader.gz -f $(KDIR)/vmlinux.lzma \ + $(call trxalign/$(1),$(1)) + $(STAGING_DIR_HOST)/bin/trx \ + -m 33554432 \ + -o $(BIN_DIR)/$(IMG_PREFIX)-$(1)-noloader-nodictionary.trx \ + -f $(KDIR)/vmlinux-nodictionary.lzma \ + $(call trxalign/$(1),$(1)) + $(STAGING_DIR_HOST)/bin/trx \ + -m 33554432 \ + -o $(BIN_DIR)/$(IMG_PREFIX)-$(1)-gz.trx \ + -f $(KDIR)/vmlinux.gz \ + $(call trxalign/$(1),$(1)) + $(call Image/Build/$(SUBTARGET)/$(1),$(1)) +# $(call Image/Build/Chk,$(1),wgr614_v9,U12H094T00_NETGEAR,2,$(patsubst jffs2-%,jffs2,$(1))) +# $(call Image/Build/Chk,$(1),wndr3400_vcna,U12H155T01_NETGEAR,2,$(patsubst jffs2-%,jffs2,$(1))) +# $(call Image/Build/Chk,$(1),wnr3500U,U12H136T00_NETGEAR,2,$(patsubst jffs2-%,jffs2,$(1))) +# $(call Image/Build/Chk,$(1),wnr3500v2_VC,U12H127T70_NETGEAR,2,$(patsubst jffs2-%,jffs2,$(1))) +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Initramfs) +endif +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/brcm47xx/image/lzma-loader/Makefile b/target/linux/brcm47xx/image/lzma-loader/Makefile new file mode 100644 index 0000000..5dd6f50 --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/Makefile @@ -0,0 +1,33 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME := lzma-loader +PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME) + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +$(PKG_BUILD_DIR)/loader.gz: $(PKG_BUILD_DIR)/.prepared + $(MAKE) -C $(PKG_BUILD_DIR) CC="$(TARGET_CC)" \ + LD="$(TARGET_CROSS)ld" CROSS_COMPILE="$(TARGET_CROSS)" + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: $(PKG_BUILD_DIR)/loader.gz +install: + +ifneq ($(TARGET),) +install: compile + $(CP) $(PKG_BUILD_DIR)/loader.gz $(PKG_BUILD_DIR)/loader.elf $(TARGET)/ +endif + +clean: + rm -rf $(PKG_BUILD_DIR) diff --git a/target/linux/brcm47xx/image/lzma-loader/src/LzmaDecode.c b/target/linux/brcm47xx/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 0000000..951700b --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,663 @@ +/* + LzmaDecode.c + LZMA Decoder + + LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#ifndef Byte +#define Byte unsigned char +#endif + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +typedef struct _CRangeDecoder +{ + Byte *Buffer; + Byte *BufferLim; + UInt32 Range; + UInt32 Code; + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback; + int Result; + #endif + int ExtraBytes; +} CRangeDecoder; + +Byte RangeDecoderReadByte(CRangeDecoder *rd) +{ + if (rd->Buffer == rd->BufferLim) + { + #ifdef _LZMA_IN_CB + UInt32 size; + rd->Result = rd->InCallback->Read(rd->InCallback, &rd->Buffer, &size); + rd->BufferLim = rd->Buffer + size; + if (size == 0) + #endif + { + rd->ExtraBytes = 1; + return 0xFF; + } + } + return (*rd->Buffer++); +} + +/* #define ReadByte (*rd->Buffer++) */ +#define ReadByte (RangeDecoderReadByte(rd)) + +void RangeDecoderInit(CRangeDecoder *rd, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback + #else + Byte *stream, UInt32 bufferSize + #endif + ) +{ + int i; + #ifdef _LZMA_IN_CB + rd->InCallback = inCallback; + rd->Buffer = rd->BufferLim = 0; + #else + rd->Buffer = stream; + rd->BufferLim = stream + bufferSize; + #endif + rd->ExtraBytes = 0; + rd->Code = 0; + rd->Range = (0xFFFFFFFF); + for(i = 0; i < 5; i++) + rd->Code = (rd->Code << 8) | ReadByte; +} + +#define RC_INIT_VAR UInt32 range = rd->Range; UInt32 code = rd->Code; +#define RC_FLUSH_VAR rd->Range = range; rd->Code = code; +#define RC_NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | ReadByte; } + +UInt32 RangeDecoderDecodeDirectBits(CRangeDecoder *rd, int numTotalBits) +{ + RC_INIT_VAR + UInt32 result = 0; + int i; + for (i = numTotalBits; i > 0; i--) + { + /* UInt32 t; */ + range >>= 1; + + result <<= 1; + if (code >= range) + { + code -= range; + result |= 1; + } + /* + t = (code - range) >> 31; + t &= 1; + code -= range & (t - 1); + result = (result + result) | (1 - t); + */ + RC_NORMALIZE + } + RC_FLUSH_VAR + return result; +} + +int RangeDecoderBitDecode(CProb *prob, CRangeDecoder *rd) +{ + UInt32 bound = (rd->Range >> kNumBitModelTotalBits) * *prob; + if (rd->Code < bound) + { + rd->Range = bound; + *prob += (kBitModelTotal - *prob) >> kNumMoveBits; + if (rd->Range < kTopValue) + { + rd->Code = (rd->Code << 8) | ReadByte; + rd->Range <<= 8; + } + return 0; + } + else + { + rd->Range -= bound; + rd->Code -= bound; + *prob -= (*prob) >> kNumMoveBits; + if (rd->Range < kTopValue) + { + rd->Code = (rd->Code << 8) | ReadByte; + rd->Range <<= 8; + } + return 1; + } +} + +#define RC_GET_BIT2(prob, mi, A0, A1) \ + UInt32 bound = (range >> kNumBitModelTotalBits) * *prob; \ + if (code < bound) \ + { A0; range = bound; *prob += (kBitModelTotal - *prob) >> kNumMoveBits; mi <<= 1; } \ + else \ + { A1; range -= bound; code -= bound; *prob -= (*prob) >> kNumMoveBits; mi = (mi + mi) + 1; } \ + RC_NORMALIZE + +#define RC_GET_BIT(prob, mi) RC_GET_BIT2(prob, mi, ; , ;) + +int RangeDecoderBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd) +{ + int mi = 1; + int i; + #ifdef _LZMA_LOC_OPT + RC_INIT_VAR + #endif + for(i = numLevels; i > 0; i--) + { + #ifdef _LZMA_LOC_OPT + CProb *prob = probs + mi; + RC_GET_BIT(prob, mi) + #else + mi = (mi + mi) + RangeDecoderBitDecode(probs + mi, rd); + #endif + } + #ifdef _LZMA_LOC_OPT + RC_FLUSH_VAR + #endif + return mi - (1 << numLevels); +} + +int RangeDecoderReverseBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd) +{ + int mi = 1; + int i; + int symbol = 0; + #ifdef _LZMA_LOC_OPT + RC_INIT_VAR + #endif + for(i = 0; i < numLevels; i++) + { + #ifdef _LZMA_LOC_OPT + CProb *prob = probs + mi; + RC_GET_BIT2(prob, mi, ; , symbol |= (1 << i)) + #else + int bit = RangeDecoderBitDecode(probs + mi, rd); + mi = mi + mi + bit; + symbol |= (bit << i); + #endif + } + #ifdef _LZMA_LOC_OPT + RC_FLUSH_VAR + #endif + return symbol; +} + +Byte LzmaLiteralDecode(CProb *probs, CRangeDecoder *rd) +{ + int symbol = 1; + #ifdef _LZMA_LOC_OPT + RC_INIT_VAR + #endif + do + { + #ifdef _LZMA_LOC_OPT + CProb *prob = probs + symbol; + RC_GET_BIT(prob, symbol) + #else + symbol = (symbol + symbol) | RangeDecoderBitDecode(probs + symbol, rd); + #endif + } + while (symbol < 0x100); + #ifdef _LZMA_LOC_OPT + RC_FLUSH_VAR + #endif + return symbol; +} + +Byte LzmaLiteralDecodeMatch(CProb *probs, CRangeDecoder *rd, Byte matchByte) +{ + int symbol = 1; + #ifdef _LZMA_LOC_OPT + RC_INIT_VAR + #endif + do + { + int bit; + int matchBit = (matchByte >> 7) & 1; + matchByte <<= 1; + #ifdef _LZMA_LOC_OPT + { + CProb *prob = probs + ((1 + matchBit) << 8) + symbol; + RC_GET_BIT2(prob, symbol, bit = 0, bit = 1) + } + #else + bit = RangeDecoderBitDecode(probs + ((1 + matchBit) << 8) + symbol, rd); + symbol = (symbol << 1) | bit; + #endif + if (matchBit != bit) + { + while (symbol < 0x100) + { + #ifdef _LZMA_LOC_OPT + CProb *prob = probs + symbol; + RC_GET_BIT(prob, symbol) + #else + symbol = (symbol + symbol) | RangeDecoderBitDecode(probs + symbol, rd); + #endif + } + break; + } + } + while (symbol < 0x100); + #ifdef _LZMA_LOC_OPT + RC_FLUSH_VAR + #endif + return symbol; +} + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + +int LzmaLenDecode(CProb *p, CRangeDecoder *rd, int posState) +{ + if(RangeDecoderBitDecode(p + LenChoice, rd) == 0) + return RangeDecoderBitTreeDecode(p + LenLow + + (posState << kLenNumLowBits), kLenNumLowBits, rd); + if(RangeDecoderBitDecode(p + LenChoice2, rd) == 0) + return kLenNumLowSymbols + RangeDecoderBitTreeDecode(p + LenMid + + (posState << kLenNumMidBits), kLenNumMidBits, rd); + return kLenNumLowSymbols + kLenNumMidSymbols + + RangeDecoderBitTreeDecode(p + LenHigh, kLenNumHighBits, rd); +} + +#define kNumStates 12 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +#ifdef _LZMA_OUT_READ + +typedef struct _LzmaVarState +{ + CRangeDecoder RangeDecoder; + Byte *Dictionary; + UInt32 DictionarySize; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 Reps[4]; + int lc; + int lp; + int pb; + int State; + int PreviousIsMatch; + int RemainLen; +} LzmaVarState; + +int LzmaDecoderInit( + unsigned char *buffer, UInt32 bufferSize, + int lc, int lp, int pb, + unsigned char *dictionary, UInt32 dictionarySize, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback + #else + unsigned char *inStream, UInt32 inSize + #endif + ) +{ + LzmaVarState *vs = (LzmaVarState *)buffer; + CProb *p = (CProb *)(buffer + sizeof(LzmaVarState)); + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + lp)); + UInt32 i; + if (bufferSize < numProbs * sizeof(CProb) + sizeof(LzmaVarState)) + return LZMA_RESULT_NOT_ENOUGH_MEM; + vs->Dictionary = dictionary; + vs->DictionarySize = dictionarySize; + vs->DictionaryPos = 0; + vs->GlobalPos = 0; + vs->Reps[0] = vs->Reps[1] = vs->Reps[2] = vs->Reps[3] = 1; + vs->lc = lc; + vs->lp = lp; + vs->pb = pb; + vs->State = 0; + vs->PreviousIsMatch = 0; + vs->RemainLen = 0; + dictionary[dictionarySize - 1] = 0; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + RangeDecoderInit(&vs->RangeDecoder, + #ifdef _LZMA_IN_CB + inCallback + #else + inStream, inSize + #endif + ); + return LZMA_RESULT_OK; +} + +int LzmaDecode(unsigned char *buffer, + unsigned char *outStream, UInt32 outSize, + UInt32 *outSizeProcessed) +{ + LzmaVarState *vs = (LzmaVarState *)buffer; + CProb *p = (CProb *)(buffer + sizeof(LzmaVarState)); + CRangeDecoder rd = vs->RangeDecoder; + int state = vs->State; + int previousIsMatch = vs->PreviousIsMatch; + Byte previousByte; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + UInt32 nowPos = 0; + UInt32 posStateMask = (1 << (vs->pb)) - 1; + UInt32 literalPosMask = (1 << (vs->lp)) - 1; + int lc = vs->lc; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + if (len == -1) + { + *outSizeProcessed = 0; + return LZMA_RESULT_OK; + } + + while(len > 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; +#else + +int LzmaDecode( + Byte *buffer, UInt32 bufferSize, + int lc, int lp, int pb, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + unsigned char *inStream, UInt32 inSize, + #endif + unsigned char *outStream, UInt32 outSize, + UInt32 *outSizeProcessed) +{ + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + lp)); + CProb *p = (CProb *)buffer; + CRangeDecoder rd; + UInt32 i; + int state = 0; + int previousIsMatch = 0; + Byte previousByte = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + UInt32 nowPos = 0; + UInt32 posStateMask = (1 << pb) - 1; + UInt32 literalPosMask = (1 << lp) - 1; + int len = 0; + if (bufferSize < numProbs * sizeof(CProb)) + return LZMA_RESULT_NOT_ENOUGH_MEM; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + RangeDecoderInit(&rd, + #ifdef _LZMA_IN_CB + inCallback + #else + inStream, inSize + #endif + ); +#endif + + *outSizeProcessed = 0; + while(nowPos < outSize) + { + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + #ifdef _LZMA_IN_CB + if (rd.Result != LZMA_RESULT_OK) + return rd.Result; + #endif + if (rd.ExtraBytes != 0) + return LZMA_RESULT_DATA_ERROR; + if (RangeDecoderBitDecode(p + IsMatch + (state << kNumPosBitsMax) + posState, &rd) == 0) + { + CProb *probs = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + if (previousIsMatch) + { + Byte matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + previousByte = LzmaLiteralDecodeMatch(probs, &rd, matchByte); + previousIsMatch = 0; + } + else + previousByte = LzmaLiteralDecode(probs, &rd); + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + } + else + { + previousIsMatch = 1; + if (RangeDecoderBitDecode(p + IsRep + state, &rd) == 1) + { + if (RangeDecoderBitDecode(p + IsRepG0 + state, &rd) == 0) + { + if (RangeDecoderBitDecode(p + IsRep0Long + (state << kNumPosBitsMax) + posState, &rd) == 0) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + if ( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + == 0) + return LZMA_RESULT_DATA_ERROR; + state = state < 7 ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + continue; + } + } + else + { + UInt32 distance; + if(RangeDecoderBitDecode(p + IsRepG1 + state, &rd) == 0) + distance = rep1; + else + { + if(RangeDecoderBitDecode(p + IsRepG2 + state, &rd) == 0) + distance = rep2; + else + { + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + len = LzmaLenDecode(p + RepLenCoder, &rd, posState); + state = state < 7 ? 8 : 11; + } + else + { + int posSlot; + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < 7 ? 7 : 10; + len = LzmaLenDecode(p + LenCoder, &rd, posState); + posSlot = RangeDecoderBitTreeDecode(p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits), kNumPosSlotBits, &rd); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = ((2 | ((UInt32)posSlot & 1)) << numDirectBits); + if (posSlot < kEndPosModelIndex) + { + rep0 += RangeDecoderReverseBitTreeDecode( + p + SpecPos + rep0 - posSlot - 1, numDirectBits, &rd); + } + else + { + rep0 += RangeDecoderDecodeDirectBits(&rd, + numDirectBits - kNumAlignBits) << kNumAlignBits; + rep0 += RangeDecoderReverseBitTreeDecode(p + Align, kNumAlignBits, &rd); + } + } + else + rep0 = posSlot; + rep0++; + } + if (rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = -1; + break; + } + if (rep0 > nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + { + return LZMA_RESULT_DATA_ERROR; + } + len += kMatchMinLen; + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + len--; + } + while(len > 0 && nowPos < outSize); + } + } + + #ifdef _LZMA_OUT_READ + vs->RangeDecoder = rd; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + nowPos; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->PreviousIsMatch = previousIsMatch; + vs->RemainLen = len; + #endif + + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/brcm47xx/image/lzma-loader/src/LzmaDecode.h b/target/linux/brcm47xx/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 0000000..f58944e --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,100 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifndef UInt32 +#ifdef _LZMA_UINT32_IS_ULONG +#define UInt32 unsigned long +#else +#define UInt32 unsigned int +#endif +#endif + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb unsigned short +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 +#define LZMA_RESULT_NOT_ENOUGH_MEM 2 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, unsigned char **buffer, UInt32 *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +/* +bufferSize = (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp)))* sizeof(CProb) +bufferSize += 100 in case of _LZMA_OUT_READ +by default CProb is unsigned short, +but if specify _LZMA_PROB_32, CProb will be UInt32(unsigned int) +*/ + +#ifdef _LZMA_OUT_READ +int LzmaDecoderInit( + unsigned char *buffer, UInt32 bufferSize, + int lc, int lp, int pb, + unsigned char *dictionary, UInt32 dictionarySize, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback + #else + unsigned char *inStream, UInt32 inSize + #endif +); +#endif + +int LzmaDecode( + unsigned char *buffer, + #ifndef _LZMA_OUT_READ + UInt32 bufferSize, + int lc, int lp, int pb, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + unsigned char *inStream, UInt32 inSize, + #endif + #endif + unsigned char *outStream, UInt32 outSize, + UInt32 *outSizeProcessed); + +#endif diff --git a/target/linux/brcm47xx/image/lzma-loader/src/Makefile b/target/linux/brcm47xx/image/lzma-loader/src/Makefile new file mode 100644 index 0000000..3320e56 --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/src/Makefile @@ -0,0 +1,77 @@ +# +# Makefile for Broadcom BCM947XX boards +# +# Copyright 2001-2003, Broadcom Corporation +# All Rights Reserved. +# +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. +# +# Copyright 2004 Manuel Novoa III +# Modified to support bzip'd kernels. +# Of course, it would be better to integrate bunzip capability into CFE. +# +# Copyright 2005 Oleg I. Vdovikin +# Cleaned up, modified for lzma support, removed from kernel +# + +TEXT_START := 0x80001000 +BZ_TEXT_START := 0x80400000 + +OBJCOPY := $(CROSS_COMPILE)objcopy -O binary -R .reginfo -R .note -R .comment -R .mdebug -S + +CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic \ + -ffunction-sections -pipe -mlong-calls -fno-common \ + -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap +CFLAGS += -DLOADADDR=$(TEXT_START) -D_LZMA_IN_CB + +ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ -DBZ_TEXT_START=$(BZ_TEXT_START) + +SEDFLAGS := s/BZ_TEXT_START/$(BZ_TEXT_START)/;s/TEXT_START/$(TEXT_START)/ + +OBJECTS := head.o data.o + +all: loader.gz loader.elf + +# Don't build dependencies, this may die if $(CC) isn't gcc +dep: + +install: + +loader.gz: loader + gzip -nc9 $< > $@ + +loader.elf: loader.o + cp $< $@ + +loader: loader.o + $(OBJCOPY) $< $@ + +loader.o: loader.lds $(OBJECTS) + $(LD) -static --gc-sections -no-warn-mismatch -T loader.lds -o $@ $(OBJECTS) + +loader.lds: loader.lds.in Makefile + @sed "$(SEDFLAGS)" < $< > $@ + +data.o: data.lds decompress.image + $(LD) -no-warn-mismatch -T data.lds -r -o $@ -b binary decompress.image -b elf32-tradlittlemips + +data.lds: + @echo "SECTIONS { .data : { code_start = .; *(.data) code_stop = .; }}" > $@ + +decompress.image: decompress + $(OBJCOPY) $< $@ + +decompress: decompress.lds decompress.o LzmaDecode.o + $(LD) -static --gc-sections -no-warn-mismatch -T decompress.lds -o $@ decompress.o LzmaDecode.o + +decompress.lds: decompress.lds.in Makefile + @sed "$(SEDFLAGS)" < $< > $@ + +mrproper: clean + +clean: + rm -f loader.gz loader decompress *.lds *.o *.image diff --git a/target/linux/brcm47xx/image/lzma-loader/src/README b/target/linux/brcm47xx/image/lzma-loader/src/README new file mode 100644 index 0000000..16649e9 --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/src/README @@ -0,0 +1,55 @@ +/* + * LZMA compressed kernel decompressor for bcm947xx boards + * + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +The code is intended to decompress kernel, being compressed using lzma utility +build using 7zip LZMA SDK. This utility is located in the LZMA_Alone directory + +decompressor code expects that your .trx file consist of three partitions: + +1) decompressor itself (this is gziped code which pmon/cfe will extract and run +on boot-up instead of real kernel) +2) LZMA compressed kernel (both streamed and regular modes are supported now) +3) Root filesystem + +Please be sure to apply the following patch for use this new trx layout (it will +allow using both new and old trx files for root filesystem lookup code) + +--- linuz/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:24:27.503322896 +0300 ++++ linux/arch/mips/brcm-boards/bcm947xx/setup.c 2005-01-23 19:29:05.237100944 +0300 +@@ -221,7 +221,9 @@ + /* Try looking at TRX header for rootfs offset */ + if (le32_to_cpu(trx->magic) == TRX_MAGIC) { + bcm947xx_parts[1].offset = off; +- if (le32_to_cpu(trx->offsets[1]) > off) ++ if (le32_to_cpu(trx->offsets[2]) > off) ++ off = le32_to_cpu(trx->offsets[2]); ++ else if (le32_to_cpu(trx->offsets[1]) > off) + off = le32_to_cpu(trx->offsets[1]); + continue; + } + + +Revision history: + 0.02 Initial release + 0.03 Added Mineharu Takahara patch to pass actual + output size to decoder (stream mode compressed input is not + a requirement anymore) + 0.04 Reordered functions using lds script diff --git a/target/linux/brcm47xx/image/lzma-loader/src/decompress.c b/target/linux/brcm47xx/image/lzma-loader/src/decompress.c new file mode 100644 index 0000000..05681b1 --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/src/decompress.c @@ -0,0 +1,186 @@ +/* + * LZMA compressed kernel decompressor for bcm947xx boards + * + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * Please note, this was code based on the bunzip2 decompressor code + * by Manuel Novoa III (mjn3@codepoet.org), although the only thing left + * is an idea and part of original vendor code + * + * + * 12-Mar-2005 Mineharu Takahara + * pass actual output size to decoder (stream mode + * compressed input is not a requirement anymore) + * + * 24-Apr-2005 Oleg I. Vdovikin + * reordered functions using lds script, removed forward decl + * + */ + +#include "LzmaDecode.h" + +#define BCM4710_FLASH 0x1fc00000 /* Flash */ + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) + +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 + +#define cache_unroll(base,op) \ + __asm__ __volatile__( \ + ".set noreorder;\n" \ + ".set mips3;\n" \ + "cache %1, (%0);\n" \ + ".set mips0;\n" \ + ".set reorder\n" \ + : \ + : "r" (base), \ + "i" (op)); + +static __inline__ void blast_icache(unsigned long size, unsigned long lsize) +{ + unsigned long start = KSEG0; + unsigned long end = (start + size); + + while(start < end) { + cache_unroll(start,Index_Invalidate_I); + start += lsize; + } +} + +static __inline__ void blast_dcache(unsigned long size, unsigned long lsize) +{ + unsigned long start = KSEG0; + unsigned long end = (start + size); + + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_D); + start += lsize; + } +} + +#define TRX_MAGIC 0x30524448 /* "HDR0" */ + +struct trx_header { + unsigned int magic; /* "HDR0" */ + unsigned int len; /* Length of file including header */ + unsigned int crc32; /* 32-bit CRC from flag_version to end of file */ + unsigned int flag_version; /* 0:15 flags, 16:31 version */ + unsigned int offsets[3]; /* Offsets of partitions from start of header */ +}; + +#define EDIMAX_PS_HEADER_MAGIC 0x36315350 /* "PS16" */ +#define EDIMAX_PS_HEADER_LEN 0xc /* 12 bytes long for edimax header */ + +/* beyound the image end, size not known in advance */ +extern unsigned char workspace[]; + +unsigned int offset; +unsigned char *data; + +/* flash access should be aligned, so wrapper is used */ +/* read byte from the flash, all accesses are 32-bit aligned */ +static int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize) +{ + static unsigned int val; + + if (((unsigned int)offset % 4) == 0) { + val = *(unsigned int *)data; + data += 4; + } + + *bufferSize = 1; + *buffer = ((unsigned char *)&val) + (offset++ & 3); + + return LZMA_RESULT_OK; +} + +static __inline__ unsigned char get_byte(void) +{ + unsigned char *buffer; + UInt32 fake; + + return read_byte(0, &buffer, &fake), *buffer; +} + +/* should be the first function */ +void entry(unsigned long icache_size, unsigned long icache_lsize, + unsigned long dcache_size, unsigned long dcache_lsize, + unsigned long fw_arg0, unsigned long fw_arg1, + unsigned long fw_arg2, unsigned long fw_arg3) +{ + unsigned int i; /* temp value */ + unsigned int lc; /* literal context bits */ + unsigned int lp; /* literal pos state bits */ + unsigned int pb; /* pos state bits */ + unsigned int osize; /* uncompressed size */ + + ILzmaInCallback callback; + callback.Read = read_byte; + + /* look for trx header, 32-bit data access */ + for (data = ((unsigned char *) KSEG1ADDR(BCM4710_FLASH)); + ((struct trx_header *)data)->magic != TRX_MAGIC && + ((struct trx_header *)data)->magic != EDIMAX_PS_HEADER_MAGIC; + data += 65536); + + if (((struct trx_header *)data)->magic == EDIMAX_PS_HEADER_MAGIC) + data += EDIMAX_PS_HEADER_LEN; + /* compressed kernel is in the partition 0 or 1 */ + if (((struct trx_header *)data)->offsets[1] > 65536) + data += ((struct trx_header *)data)->offsets[0]; + else + data += ((struct trx_header *)data)->offsets[1]; + + offset = 0; + + /* lzma args */ + i = get_byte(); + lc = i % 9, i = i / 9; + lp = i % 5, pb = i / 5; + + /* skip rest of the LZMA coder property */ + for (i = 0; i < 4; i++) + get_byte(); + + /* read the lower half of uncompressed size in the header */ + osize = ((unsigned int)get_byte()) + + ((unsigned int)get_byte() << 8) + + ((unsigned int)get_byte() << 16) + + ((unsigned int)get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + for (i = 0; i < 4; i++) + get_byte(); + + /* decompress kernel */ + if (LzmaDecode(workspace, ~0, lc, lp, pb, &callback, + (unsigned char*)LOADADDR, osize, &i) == LZMA_RESULT_OK) + { + blast_dcache(dcache_size, dcache_lsize); + blast_icache(icache_size, icache_lsize); + + /* Jump to load address */ + ((void (*)(unsigned long, unsigned long, unsigned long, + unsigned long)) LOADADDR)(fw_arg0, fw_arg1, fw_arg2, + fw_arg3); + } +} diff --git a/target/linux/brcm47xx/image/lzma-loader/src/decompress.lds.in b/target/linux/brcm47xx/image/lzma-loader/src/decompress.lds.in new file mode 100644 index 0000000..33f56f8 --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/src/decompress.lds.in @@ -0,0 +1,20 @@ +OUTPUT_ARCH(mips) +ENTRY(entry) +SECTIONS { + . = BZ_TEXT_START; + .text : { + *(.text.entry) + *(.text) + *(.rodata) + } + + .data : { + *(.data) + } + + .bss : { + *(.bss) + } + + workspace = .; +} diff --git a/target/linux/brcm47xx/image/lzma-loader/src/head.S b/target/linux/brcm47xx/image/lzma-loader/src/head.S new file mode 100644 index 0000000..3a33e40 --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/src/head.S @@ -0,0 +1,160 @@ +/* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su) */ +/* cache manipulation adapted from Broadcom code */ +/* idea taken from original bunzip2 decompressor code */ +/* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org) */ +/* Licensed under the linux kernel's version of the GPL.*/ + +#include +#include + +#define KSEG0 0x80000000 + +#define C0_CONFIG $16 +#define C0_TAGLO $28 +#define C0_TAGHI $29 + +#define CONF1_DA_SHIFT 7 /* D$ associativity */ +#define CONF1_DA_MASK 0x00000380 +#define CONF1_DA_BASE 1 +#define CONF1_DL_SHIFT 10 /* D$ line size */ +#define CONF1_DL_MASK 0x00001c00 +#define CONF1_DL_BASE 2 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */ +#define CONF1_DS_MASK 0x0000e000 +#define CONF1_DS_BASE 64 +#define CONF1_IA_SHIFT 16 /* I$ associativity */ +#define CONF1_IA_MASK 0x00070000 +#define CONF1_IA_BASE 1 +#define CONF1_IL_SHIFT 19 /* I$ line size */ +#define CONF1_IL_MASK 0x00380000 +#define CONF1_IL_BASE 2 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */ +#define CONF1_IS_MASK 0x01c00000 +#define CONF1_IS_BASE 64 + +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 + + .text + LEAF(startup) + .set noreorder + addi sp, -48 + sw a0, 16(sp) + sw a1, 20(sp) + sw a2, 24(sp) + sw a3, 28(sp) + + /* Copy decompressor code to the right place */ + li t2, BZ_TEXT_START + add a0, t2, 0 + la a1, code_start + la a2, code_stop +$L1: + lw t0, 0(a1) + sw t0, 0(a0) + add a1, 4 + add a0, 4 + blt a1, a2, $L1 + nop + + /* At this point we need to invalidate dcache and */ + /* icache before jumping to new code */ + +1: /* Get cache sizes */ + .set mips32 + mfc0 s0,C0_CONFIG,1 + .set mips0 + + li s1,CONF1_DL_MASK + and s1,s0 + beq s1,zero,nodc + nop + + srl s1,CONF1_DL_SHIFT + li t0,CONF1_DL_BASE + sll s1,t0,s1 /* s1 has D$ cache line size */ + + li s2,CONF1_DA_MASK + and s2,s0 + srl s2,CONF1_DA_SHIFT + addiu s2,CONF1_DA_BASE /* s2 now has D$ associativity */ + + li t0,CONF1_DS_MASK + and t0,s0 + srl t0,CONF1_DS_SHIFT + li s3,CONF1_DS_BASE + sll s3,s3,t0 /* s3 has D$ sets per way */ + + multu s2,s3 /* sets/way * associativity */ + mflo t0 /* total cache lines */ + + multu s1,t0 /* D$ linesize * lines */ + mflo s2 /* s2 is now D$ size in bytes */ + + /* Initilize the D$: */ + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + li t0,KSEG0 /* Just an address for the first $ line */ + addu t1,t0,s2 /* + size of cache == end */ + + .set mips3 +1: cache Index_Writeback_Inv_D,0(t0) + .set mips0 + bne t0,t1,1b + addu t0,s1 + +nodc: + /* Now we get to do it all again for the I$ */ + + move s3,zero /* just in case there is no icache */ + move s4,zero + + li t0,CONF1_IL_MASK + and t0,s0 + beq t0,zero,noic + nop + + srl t0,CONF1_IL_SHIFT + li s3,CONF1_IL_BASE + sll s3,t0 /* s3 has I$ cache line size */ + + li t0,CONF1_IA_MASK + and t0,s0 + srl t0,CONF1_IA_SHIFT + addiu s4,t0,CONF1_IA_BASE /* s4 now has I$ associativity */ + + li t0,CONF1_IS_MASK + and t0,s0 + srl t0,CONF1_IS_SHIFT + li s5,CONF1_IS_BASE + sll s5,t0 /* s5 has I$ sets per way */ + + multu s4,s5 /* sets/way * associativity */ + mflo t0 /* s4 is now total cache lines */ + + multu s3,t0 /* I$ linesize * lines */ + mflo s4 /* s4 is cache size in bytes */ + + /* Initilize the I$: */ + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + li t0,KSEG0 /* Just an address for the first $ line */ + addu t1,t0,s4 /* + size of cache == end */ + + .set mips3 +1: cache Index_Invalidate_I,0(t0) + .set mips0 + bne t0,t1,1b + addu t0,s3 + +noic: + move a0,s3 /* icache line size */ + move a1,s4 /* icache size */ + move a2,s1 /* dcache line size */ + jal t2 + move a3,s2 /* dcache size */ + + .set reorder + END(startup) diff --git a/target/linux/brcm47xx/image/lzma-loader/src/loader.lds.in b/target/linux/brcm47xx/image/lzma-loader/src/loader.lds.in new file mode 100644 index 0000000..20f2ea9 --- /dev/null +++ b/target/linux/brcm47xx/image/lzma-loader/src/loader.lds.in @@ -0,0 +1,17 @@ +OUTPUT_ARCH(mips) +ENTRY(startup) +SECTIONS { + . = TEXT_START; + .text : { + *(.text) + *(.rodata) + } + + .data : { + *(.data) + } + + .bss : { + *(.bss) + } +} diff --git a/target/linux/brcm47xx/legacy/config-default b/target/linux/brcm47xx/legacy/config-default new file mode 100644 index 0000000..8a52e47 --- /dev/null +++ b/target/linux/brcm47xx/legacy/config-default @@ -0,0 +1,8 @@ +CONFIG_B44=y +CONFIG_B44_PCI=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI_AUTOSELECT=y +# CONFIG_BCM47XX_BCMA is not set +# CONFIG_BCMA is not set +# CONFIG_MTD_NAND is not set +# CONFIG_SSB_DRIVER_GIGE is not set diff --git a/target/linux/brcm47xx/legacy/profiles/100-Broadcom-b43.mk b/target/linux/brcm47xx/legacy/profiles/100-Broadcom-b43.mk new file mode 100644 index 0000000..50d7770 --- /dev/null +++ b/target/linux/brcm47xx/legacy/profiles/100-Broadcom-b43.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2007-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-b43 + NAME:=Broadcom SoC, all Ethernet, BCM43xx WiFi (b43, default) + PACKAGES:=kmod-b43 kmod-b43legacy +endef + +define Profile/Broadcom-b43/Description + Package set compatible with hardware any Broadcom BCM47xx or BCM535x + SoC with Broadcom BCM43xx Wifi cards using the mac80211, b43 and + b43legacy drivers and b44, tg3 or bgmac Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-b43)) + diff --git a/target/linux/brcm47xx/legacy/profiles/101-Broadcom-wl.mk b/target/linux/brcm47xx/legacy/profiles/101-Broadcom-wl.mk new file mode 100644 index 0000000..6a4c5b0 --- /dev/null +++ b/target/linux/brcm47xx/legacy/profiles/101-Broadcom-wl.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2010-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-wl + NAME:=Broadcom SoC, all Ethernet, BCM43xx WiFi (wl, proprietary) + PACKAGES:=-wpad-mini kmod-brcm-wl-mini wlc nas +endef + +define Profile/Broadcom-wl/Description + Package set compatible with hardware any Broadcom BCM47xx or BCM535x + SoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom + wireless "wl" driver and b44, tg3 or bgmac Ethernet driver. +endef + +$(eval $(call Profile,Broadcom-wl)) + diff --git a/target/linux/brcm47xx/legacy/profiles/WGT634U.mk b/target/linux/brcm47xx/legacy/profiles/WGT634U.mk new file mode 100644 index 0000000..ebe5e23 --- /dev/null +++ b/target/linux/brcm47xx/legacy/profiles/WGT634U.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WGT634U + NAME:=Netgear WGT634U + PACKAGES:=kmod-ath5k kmod-usb-core kmod-usb2 kmod-ocf-ubsec-ssb +endef + +define Profile/WGT634U/Description + Package set compatible with the Netgear WGT634U. Contains USB support +endef +$(eval $(call Profile,WGT634U)) + diff --git a/target/linux/brcm47xx/legacy/profiles/WRTSL54GS.mk b/target/linux/brcm47xx/legacy/profiles/WRTSL54GS.mk new file mode 100644 index 0000000..8c48483 --- /dev/null +++ b/target/linux/brcm47xx/legacy/profiles/WRTSL54GS.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/WRTSL54GS + NAME:=Linksys WRTSL54GS + PACKAGES:=kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-usb-storage kmod-scsi-core kmod-fs-ext4 e2fsprogs kmod-b43 +endef + +define Profile/WRTSL54GS/Description + Package set compatible with the Linksys WRTSL54GS. Contains USB support +endef +$(eval $(call Profile,WRTSL54GS)) + diff --git a/target/linux/brcm47xx/legacy/target.mk b/target/linux/brcm47xx/legacy/target.mk new file mode 100644 index 0000000..7310896 --- /dev/null +++ b/target/linux/brcm47xx/legacy/target.mk @@ -0,0 +1,8 @@ +FEATURES += low_mem pcmcia +BOARDNAME:=Legacy (BMIPS3300) + +define Target/Description + Build firmware for Broadcom BCM47xx and BCM53xx devices with + BMIPS3300 CPU except for BCM4705 SoC. + Supported SoCs: BCM5352E, BCM5354, BCM5365?, BCM4712, BCM4704. +endef diff --git a/target/linux/brcm47xx/mips74k/config-default b/target/linux/brcm47xx/mips74k/config-default new file mode 100644 index 0000000..09ff5a9 --- /dev/null +++ b/target/linux/brcm47xx/mips74k/config-default @@ -0,0 +1,19 @@ +# CONFIG_ADM6996_PHY is not set +# CONFIG_BCM47XX_SSB is not set +CONFIG_BGMAC=y +CONFIG_BOUNCE=y +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPSR1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +# CONFIG_FIXED_PHY is not set +# CONFIG_GPIO_WDT is not set +CONFIG_HIGHMEM=y +# CONFIG_SSB is not set +# CONFIG_SSB_DRIVER_EXTIF is not set +# CONFIG_SSB_DRIVER_GIGE is not set +# CONFIG_SSB_DRIVER_MIPS is not set +# CONFIG_SSB_EMBEDDED is not set +# CONFIG_SSB_PCICORE_HOSTMODE is not set +# CONFIG_SSB_SERIAL is not set +# CONFIG_SSB_SFLASH is not set diff --git a/target/linux/brcm47xx/mips74k/profiles/100-Broadcom-b43.mk b/target/linux/brcm47xx/mips74k/profiles/100-Broadcom-b43.mk new file mode 100644 index 0000000..bd3b010 --- /dev/null +++ b/target/linux/brcm47xx/mips74k/profiles/100-Broadcom-b43.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-mips74k-b43 + NAME:=Broadcom SoC, BCM43xx WiFi (b43) + PACKAGES:=kmod-b43 +endef + +define Profile/Broadcom-mips74k-b43/Description + Package set for devices with BCM43xx WiFi including mac80211 and b43 + driver. +endef + +$(eval $(call Profile,Broadcom-mips74k-b43)) + diff --git a/target/linux/brcm47xx/mips74k/profiles/101-Broadcom-brcsmac.mk b/target/linux/brcm47xx/mips74k/profiles/101-Broadcom-brcsmac.mk new file mode 100644 index 0000000..a138ef9 --- /dev/null +++ b/target/linux/brcm47xx/mips74k/profiles/101-Broadcom-brcsmac.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-mips74k-brcmsmac + NAME:=Broadcom SoC, BCM43xx WiFi (brcmsmac) + PACKAGES:=kmod-brcmsmac +endef + +define Profile/Broadcom-mips74k-brcmsmac/Description + Package set for devices with BCM43xx WiFi including mac80211 and + brcmsmac driver. +endef + +$(eval $(call Profile,Broadcom-mips74k-brcmsmac)) + diff --git a/target/linux/brcm47xx/mips74k/profiles/102-Broadcom-wl.mk b/target/linux/brcm47xx/mips74k/profiles/102-Broadcom-wl.mk new file mode 100644 index 0000000..502fff4 --- /dev/null +++ b/target/linux/brcm47xx/mips74k/profiles/102-Broadcom-wl.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-mips74k-wl + NAME:=Broadcom SoC, BCM43xx WiFi (proprietary wl) + PACKAGES:=-wpad-mini kmod-brcm-wl wlc nas +endef + +define Profile/Broadcom-mips74k-wl/Description + Package set for devices with BCM43xx WiFi including proprietary (and + closed source) driver "wl". +endef + +$(eval $(call Profile,Broadcom-mips74k-wl)) + diff --git a/target/linux/brcm47xx/mips74k/profiles/103-Broadcom-none.mk b/target/linux/brcm47xx/mips74k/profiles/103-Broadcom-none.mk new file mode 100644 index 0000000..5790527 --- /dev/null +++ b/target/linux/brcm47xx/mips74k/profiles/103-Broadcom-none.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Broadcom-mips74k-none + NAME:=Broadcom SoC, No WiFi + PACKAGES:=-wpad-mini +endef + +define Profile/Broadcom-mips74k-none/Description + Package set for devices without a WiFi. +endef + +$(eval $(call Profile,Broadcom-mips74k-none)) + diff --git a/target/linux/brcm47xx/mips74k/target.mk b/target/linux/brcm47xx/mips74k/target.mk new file mode 100644 index 0000000..ccefa21 --- /dev/null +++ b/target/linux/brcm47xx/mips74k/target.mk @@ -0,0 +1,9 @@ +BOARDNAME:=MIPS 74K +CPU_TYPE:=74kc +CPU_SUBTYPE:=dsp2 +FEATURES+=mips16 + +define Target/Description + Build firmware for Broadcom BCM47xx and BCM53xx devices with + MIPS 74K CPU. +endef diff --git a/target/linux/brcm47xx/modules.mk b/target/linux/brcm47xx/modules.mk new file mode 100644 index 0000000..305643f --- /dev/null +++ b/target/linux/brcm47xx/modules.mk @@ -0,0 +1,36 @@ +# +# Copyright (C) 2006-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/ocf-ubsec-ssb + TITLE:=BCM5365P IPSec Core driver + DEPENDS:=@TARGET_brcm47xx @!TARGET_brcm47xx_mips74k +kmod-crypto-ocf + KCONFIG:=CONFIG_OCF_UBSEC_SSB + FILES:=$(LINUX_DIR)/crypto/ocf/ubsec_ssb/ubsec_ssb.ko + AUTOLOAD:=$(call AutoLoad,10,ubsec_ssb) + $(call AddDepends/crypto) +endef + +define KernelPackage/ocf-ubsec-ssb/description + This package contains the OCF driver for the BCM5365p IPSec Core +endef + +$(eval $(call KernelPackage,ocf-ubsec-ssb)) + +define KernelPackage/bgmac + TITLE:=Broadcom bgmac driver + KCONFIG:=CONFIG_BGMAC + DEPENDS:=@TARGET_brcm47xx @!TARGET_brcm47xx_legacy + SUBMENU:=$(NETWORK_DEVICES_MENU) + FILES:=$(LINUX_DIR)/drivers/net/ethernet/broadcom/bgmac.ko + AUTOLOAD:=$(call AutoLoad,19,bgmac,1) +endef + +define KernelPackage/bgmac/description + Kernel modules for Broadcom bgmac Ethernet adapters. +endef + +$(eval $(call KernelPackage,bgmac)) diff --git a/target/linux/brcm47xx/patches-4.1/031-01-MIPS-BCM47XX-Make-sure-NVRAM-buffer-ends-with-0.patch b/target/linux/brcm47xx/patches-4.1/031-01-MIPS-BCM47XX-Make-sure-NVRAM-buffer-ends-with-0.patch new file mode 100644 index 0000000..7577da1 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-01-MIPS-BCM47XX-Make-sure-NVRAM-buffer-ends-with-0.patch @@ -0,0 +1,54 @@ +From 4ddb225376a2802a4e20e16f71c6d37b679e3169 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 12 May 2015 18:46:11 +0200 +Subject: [PATCH] MIPS: BCM47XX: Make sure NVRAM buffer ends with \0 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This will simplify reading its contents. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Cc: linux-mips@linux-mips.org +Cc: Hauke Mehrtens +Cc: Hante Meuleman +Cc: Ian Kent +Patchwork: https://patchwork.linux-mips.org/patch/10031/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/nvram.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -98,7 +98,7 @@ found: + pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n"); + if (header->len > NVRAM_SPACE) + pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", +- header->len, NVRAM_SPACE); ++ header->len, NVRAM_SPACE - 1); + + src = (u32 *)header; + dst = (u32 *)nvram_buf; +@@ -106,6 +106,7 @@ found: + *dst++ = __raw_readl(src++); + for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4) + *dst++ = readl(src++); ++ nvram_buf[NVRAM_SPACE - 1] = '\0'; + + return 0; + } +@@ -150,10 +151,10 @@ static int nvram_init(void) + u8 *dst = (uint8_t *)nvram_buf; + size_t len = header.len; + +- if (header.len > NVRAM_SPACE) { ++ if (len >= NVRAM_SPACE) { ++ len = NVRAM_SPACE - 1; + pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", +- header.len, NVRAM_SPACE); +- len = NVRAM_SPACE; ++ header.len, len); + } + + err = mtd_read(mtd, 0, len, &bytes_read, dst); diff --git a/target/linux/brcm47xx/patches-4.1/031-02-MIPS-BCM47XX-Simplify-function-looking-for-NVRAM-ent.patch b/target/linux/brcm47xx/patches-4.1/031-02-MIPS-BCM47XX-Simplify-function-looking-for-NVRAM-ent.patch new file mode 100644 index 0000000..7a3ddc3 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-02-MIPS-BCM47XX-Simplify-function-looking-for-NVRAM-ent.patch @@ -0,0 +1,59 @@ +From f6f895644230b13618f14f7108f9b23a21a87bfa Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 12 May 2015 18:46:12 +0200 +Subject: [PATCH] MIPS: BCM47XX: Simplify function looking for NVRAM entry +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +First of all it shouldn't modify copied NVRAM just to make sure it can +loop over all entries. It's enough to just compare current position +pointer with the end of buffer address. +Secondly buffer is guaranteed to be \0 ended, so we don't need strnchr. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Cc: linux-mips@linux-mips.org +Cc: Hauke Mehrtens +Cc: Hante Meuleman +Cc: Ian Kent +Patchwork: https://patchwork.linux-mips.org/patch/10032/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/nvram.c | 13 +++++-------- + 1 file changed, 5 insertions(+), 8 deletions(-) + +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -171,7 +171,7 @@ static int nvram_init(void) + int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len) + { + char *var, *value, *end, *eq; +- int data_left, err; ++ int err; + + if (!name) + return -EINVAL; +@@ -184,19 +184,16 @@ int bcm47xx_nvram_getenv(const char *nam + + /* Look for name=value and return value */ + var = &nvram_buf[sizeof(struct nvram_header)]; +- end = nvram_buf + sizeof(nvram_buf) - 2; +- end[0] = '\0'; +- end[1] = '\0'; +- for (; *var; var = value + strlen(value) + 1) { +- data_left = end - var; +- +- eq = strnchr(var, data_left, '='); ++ end = nvram_buf + sizeof(nvram_buf); ++ while (var < end && *var) { ++ eq = strchr(var, '='); + if (!eq) + break; + value = eq + 1; + if (eq - var == strlen(name) && + strncmp(var, name, eq - var) == 0) + return snprintf(val, val_len, "%s", value); ++ var = value + strlen(value) + 1; + } + return -ENOENT; + } diff --git a/target/linux/brcm47xx/patches-4.1/031-03-MIPS-BCM47xx-Extract-all-boardflags-to-new-u32-field.patch b/target/linux/brcm47xx/patches-4.1/031-03-MIPS-BCM47xx-Extract-all-boardflags-to-new-u32-field.patch new file mode 100644 index 0000000..7a5babc --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-03-MIPS-BCM47xx-Extract-all-boardflags-to-new-u32-field.patch @@ -0,0 +1,35 @@ +From ecd06daee04bae00f3dfd0a3cd46f28142f18191 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 12 May 2015 11:31:02 +0200 +Subject: [PATCH] MIPS: BCM47xx: Extract all boardflags to new u32 fields +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +For years we planned to get rid of old u16 fields, let's start doing it +with MIPS code. This process will take some time, it requires doing the +same in ssb/bcma and then switching all drivers to new fields. This will +be handled in separated patches submitted to appropriate trees. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Cc: linux-mips@linux-mips.org +Cc: Hauke Mehrtens +Patchwork: https://patchwork.linux-mips.org/patch/10026/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/sprom.c | 3 +++ + include/linux/ssb/ssb.h | 5 ++++- + 2 files changed, 7 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm47xx/sprom.c ++++ b/arch/mips/bcm47xx/sprom.c +@@ -201,6 +201,9 @@ static void bcm47xx_sprom_fill_auto(stru + bool fb = fallback; + + ENTRY(0xfffffffe, u16, pre, "boardrev", board_rev, 0, true); ++ ENTRY(0xfffffffe, u32, pre, "boardflags", boardflags, 0, fb); ++ ENTRY(0xfffffff0, u32, pre, "boardflags2", boardflags2, 0, fb); ++ ENTRY(0xfffff800, u32, pre, "boardflags3", boardflags3, 0, fb); + ENTRY(0x00000002, u16, pre, "boardflags", boardflags_lo, 0, fb); + ENTRY(0xfffffffc, u16, pre, "boardtype", board_type, 0, true); + ENTRY(0xfffffffe, u16, pre, "boardnum", board_num, 0, fb); diff --git a/target/linux/brcm47xx/patches-4.1/031-04-MIPS-BCM47xx-Extract-info-about-et2-interface.patch b/target/linux/brcm47xx/patches-4.1/031-04-MIPS-BCM47xx-Extract-info-about-et2-interface.patch new file mode 100644 index 0000000..957bb68 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-04-MIPS-BCM47xx-Extract-info-about-et2-interface.patch @@ -0,0 +1,45 @@ +From c58ec43eaca5f970911770c17cb3a29ac102656d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 12 May 2015 11:54:48 +0200 +Subject: [PATCH] MIPS: BCM47xx: Extract info about et2 interface +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +New devices may have more than 1 Ethernet core (device). We should +extract info about them to make it available to Ethernet drivers. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Cc: linux-mips@linux-mips.org +Cc: Hauke Mehrtens +Cc: Hante Meuleman +Cc: Ian Kent +Patchwork: https://patchwork.linux-mips.org/patch/10027/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/sprom.c | 6 ++++++ + include/linux/ssb/ssb.h | 3 +++ + 2 files changed, 9 insertions(+) + +--- a/arch/mips/bcm47xx/sprom.c ++++ b/arch/mips/bcm47xx/sprom.c +@@ -531,6 +531,8 @@ static int mac_addr_used = 2; + static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, + const char *prefix, bool fallback) + { ++ bool fb = fallback; ++ + nvram_read_macaddr(prefix, "et0macaddr", sprom->et0mac, fallback); + nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0, + fallback); +@@ -543,6 +545,10 @@ static void bcm47xx_fill_sprom_ethernet( + nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0, + fallback); + ++ nvram_read_macaddr(prefix, "et2macaddr", sprom->et2mac, fb); ++ nvram_read_u8(prefix, NULL, "et2mdcport", &sprom->et2mdcport, 0, fb); ++ nvram_read_u8(prefix, NULL, "et2phyaddr", &sprom->et2phyaddr, 0, fb); ++ + nvram_read_macaddr(prefix, "macaddr", sprom->il0mac, fallback); + nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback); + diff --git a/target/linux/brcm47xx/patches-4.1/031-05-MIPS-BCM47xx-Read-board-info-for-all-bcma-buses.patch b/target/linux/brcm47xx/patches-4.1/031-05-MIPS-BCM47xx-Read-board-info-for-all-bcma-buses.patch new file mode 100644 index 0000000..314a6c4 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-05-MIPS-BCM47xx-Read-board-info-for-all-bcma-buses.patch @@ -0,0 +1,132 @@ +From 12e1ab54dcd414c3579cfd26be9d9c9e1cab92ad Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 12 May 2015 13:05:18 +0200 +Subject: [PATCH] MIPS: BCM47xx: Read board info for all bcma buses +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Extra bcma buses may be totally different models, see following dump: +boardtype=0x0646 +pci/1/1/boardtype=0x0545 +pci/2/1/boardtype=0x62b +We need to detect them properly to allow drivers apply some board +specific hacks. + +[ralf@linux-mips.org: folded in Rafal's fix.] + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Cc: linux-mips@linux-mips.org +Cc: Hauke Mehrtens +Patchwork: https://patchwork.linux-mips.org/patch/10028/ +Patchwork: https://patchwork.linux-mips.org/patch/10048/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/setup.c | 3 -- + arch/mips/bcm47xx/sprom.c | 44 ++++++++++++++-------------- + arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 4 --- + 3 files changed, 22 insertions(+), 29 deletions(-) + +--- a/arch/mips/bcm47xx/setup.c ++++ b/arch/mips/bcm47xx/setup.c +@@ -206,9 +206,6 @@ void __init bcm47xx_bus_setup(void) + err = bcma_host_soc_init(&bcm47xx_bus.bcma); + if (err) + panic("Failed to initialize BCMA bus (err %d)", err); +- +- bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, +- NULL); + } + #endif + +--- a/arch/mips/bcm47xx/sprom.c ++++ b/arch/mips/bcm47xx/sprom.c +@@ -640,19 +640,6 @@ void bcm47xx_fill_ssb_boardinfo(struct s + } + #endif + +-#ifdef CONFIG_BCM47XX_BCMA +-void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo, +- const char *prefix) +-{ +- nvram_read_u16(prefix, NULL, "boardvendor", &boardinfo->vendor, 0, +- true); +- if (!boardinfo->vendor) +- boardinfo->vendor = SSB_BOARDVENDOR_BCM; +- +- nvram_read_u16(prefix, NULL, "boardtype", &boardinfo->type, 0, true); +-} +-#endif +- + #if defined(CONFIG_BCM47XX_SSB) + static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out) + { +@@ -707,33 +694,46 @@ static void bcm47xx_sprom_apply_prefix_a + + static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out) + { +- char prefix[10]; ++ struct bcma_boardinfo *binfo = &bus->boardinfo; + struct bcma_device *core; ++ char buf[10]; ++ char *prefix; ++ bool fallback = false; + + switch (bus->hosttype) { + case BCMA_HOSTTYPE_PCI: + memset(out, 0, sizeof(struct ssb_sprom)); +- snprintf(prefix, sizeof(prefix), "pci/%u/%u/", ++ snprintf(buf, sizeof(buf), "pci/%u/%u/", + bus->host_pci->bus->number + 1, + PCI_SLOT(bus->host_pci->devfn)); +- bcm47xx_sprom_apply_prefix_alias(prefix, sizeof(prefix)); +- bcm47xx_fill_sprom(out, prefix, false); +- return 0; ++ bcm47xx_sprom_apply_prefix_alias(buf, sizeof(buf)); ++ prefix = buf; ++ break; + case BCMA_HOSTTYPE_SOC: + memset(out, 0, sizeof(struct ssb_sprom)); + core = bcma_find_core(bus, BCMA_CORE_80211); + if (core) { +- snprintf(prefix, sizeof(prefix), "sb/%u/", ++ snprintf(buf, sizeof(buf), "sb/%u/", + core->core_index); +- bcm47xx_fill_sprom(out, prefix, true); ++ prefix = buf; ++ fallback = true; + } else { +- bcm47xx_fill_sprom(out, NULL, false); ++ prefix = NULL; + } +- return 0; ++ break; + default: + pr_warn("Unable to fill SPROM for given bustype.\n"); + return -EINVAL; + } ++ ++ nvram_read_u16(prefix, NULL, "boardvendor", &binfo->vendor, 0, true); ++ if (!binfo->vendor) ++ binfo->vendor = SSB_BOARDVENDOR_BCM; ++ nvram_read_u16(prefix, NULL, "boardtype", &binfo->type, 0, true); ++ ++ bcm47xx_fill_sprom(out, prefix, fallback); ++ ++ return 0; + } + #endif + +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h +@@ -52,10 +52,6 @@ void bcm47xx_fill_sprom(struct ssb_sprom + void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo, + const char *prefix); + #endif +-#ifdef CONFIG_BCM47XX_BCMA +-void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo, +- const char *prefix); +-#endif + + void bcm47xx_set_system_type(u16 chip_id); + diff --git a/target/linux/brcm47xx/patches-4.1/031-06-MIPS-BCM77xx-Remove-legacy-__cpuinit-data-sections-t.patch b/target/linux/brcm47xx/patches-4.1/031-06-MIPS-BCM77xx-Remove-legacy-__cpuinit-data-sections-t.patch new file mode 100644 index 0000000..e81f695 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-06-MIPS-BCM77xx-Remove-legacy-__cpuinit-data-sections-t.patch @@ -0,0 +1,60 @@ +From 50d68dfef385127a1da2957813272c610c691157 Mon Sep 17 00:00:00 2001 +From: Paul Gortmaker +Date: Mon, 27 Apr 2015 18:47:56 -0400 +Subject: [PATCH] MIPS: BCM77xx: Remove legacy __cpuinit{,data} sections that + crept in +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +We removed __cpuinit support (leaving no-op stubs) quite some time ago. +However a few more crept in as of commit 6ee1d93455384cef8a0426effe85da2 +("MIPS: BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)") + +Since we want to clobber the stubs soon, get this removed now. + +Signed-off-by: Paul Gortmaker +Cc: RafaÅ‚ MiÅ‚ecki +Cc: linux-mips@linux-mips.org +Cc: linux-kernel@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/9892/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/prom.c | 2 +- + arch/mips/include/asm/pgtable-32.h | 2 +- + arch/mips/mm/tlb-r4k.c | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/mips/bcm47xx/prom.c ++++ b/arch/mips/bcm47xx/prom.c +@@ -126,7 +126,7 @@ void __init prom_free_prom_memory(void) + /* Stripped version of tlb_init, with the call to build_tlb_refill_handler + * dropped. Calling it at this stage causes a hang. + */ +-void __cpuinit early_tlb_init(void) ++void early_tlb_init(void) + { + write_c0_pagemask(PM_DEFAULT_MASK); + write_c0_wired(0); +--- a/arch/mips/include/asm/pgtable-32.h ++++ b/arch/mips/include/asm/pgtable-32.h +@@ -18,7 +18,7 @@ + + #include + +-extern int temp_tlb_entry __cpuinitdata; ++extern int temp_tlb_entry; + + /* + * - add_temporary_entry() add a temporary TLB entry. We use TLB entries +--- a/arch/mips/mm/tlb-r4k.c ++++ b/arch/mips/mm/tlb-r4k.c +@@ -423,7 +423,7 @@ int __init has_transparent_hugepage(void + * lifetime of the system + */ + +-int temp_tlb_entry __cpuinitdata; ++int temp_tlb_entry; + + __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) diff --git a/target/linux/brcm47xx/patches-4.1/031-07-MIPS-BCM47XX-Support-Luxul-XWR-1750-board.patch b/target/linux/brcm47xx/patches-4.1/031-07-MIPS-BCM47XX-Support-Luxul-XWR-1750-board.patch new file mode 100644 index 0000000..73f0662 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-07-MIPS-BCM47XX-Support-Luxul-XWR-1750-board.patch @@ -0,0 +1,100 @@ +From 981de3c2f27af27fa4c5c952d122b35ee573ab7a Mon Sep 17 00:00:00 2001 +From: Dan Haab +Date: Wed, 22 Apr 2015 13:58:33 -0600 +Subject: [PATCH] MIPS: BCM47XX: Support Luxul XWR-1750 board +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Dan Haab +Acked-by: RafaÅ‚ MiÅ‚ecki +Cc: linux-mips@linux-mips.org +Cc: Hauke Mehrtens +Cc: Dan Haab +Patchwork: https://patchwork.linux-mips.org/patch/9831/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/board.c | 1 + + arch/mips/bcm47xx/buttons.c | 11 +++++++++++ + arch/mips/bcm47xx/leds.c | 14 ++++++++++++++ + arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 2 ++ + 4 files changed, 28 insertions(+) + +--- a/arch/mips/bcm47xx/board.c ++++ b/arch/mips/bcm47xx/board.c +@@ -149,6 +149,7 @@ struct bcm47xx_board_type_list2 bcm47xx_ + /* board_id */ + static const + struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = { ++ {{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"}, + {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"}, +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -299,6 +299,13 @@ bcm47xx_buttons_linksys_wrtsl54gs[] __in + BCM47XX_GPIO_KEY(6, KEY_RESTART), + }; + ++/* Luxul */ ++ ++static const struct gpio_keys_button ++bcm47xx_buttons_luxul_xwr_1750_v1[] = { ++ BCM47XX_GPIO_KEY(14, BTN_TASK), ++}; ++ + /* Microsoft */ + + static const struct gpio_keys_button +@@ -555,6 +562,10 @@ int __init bcm47xx_buttons_register(void + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrtsl54gs); + break; + ++ case BCM47XX_BOARD_LUXUL_XWR_1750_V1: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xwr_1750_v1); ++ break; ++ + case BCM47XX_BOARD_MICROSOFT_MN700: + err = bcm47xx_copy_bdata(bcm47xx_buttons_microsoft_nm700); + break; +--- a/arch/mips/bcm47xx/leds.c ++++ b/arch/mips/bcm47xx/leds.c +@@ -370,6 +370,16 @@ bcm47xx_leds_linksys_wrtsl54gs[] __initc + BCM47XX_GPIO_LED(7, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), + }; + ++/* Luxul */ ++ ++static const struct gpio_led ++bcm47xx_leds_luxul_xwr_1750_v1[] __initconst = { ++ BCM47XX_GPIO_LED(5, "green", "5ghz", 0, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED_TRIGGER(13, "green", "status", 0, "timer"), ++ BCM47XX_GPIO_LED(15, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), ++}; ++ + /* Microsoft */ + + static const struct gpio_led +@@ -623,6 +633,10 @@ void __init bcm47xx_leds_register(void) + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrtsl54gs); + break; + ++ case BCM47XX_BOARD_LUXUL_XWR_1750_V1: ++ bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_1750_v1); ++ break; ++ + case BCM47XX_BOARD_MICROSOFT_MN700: + bcm47xx_set_pdata(bcm47xx_leds_microsoft_nm700); + break; +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +@@ -80,6 +80,8 @@ enum bcm47xx_board { + BCM47XX_BOARD_LINKSYS_WRT610NV2, + BCM47XX_BOARD_LINKSYS_WRTSL54GS, + ++ BCM47XX_BOARD_LUXUL_XWR_1750_V1, ++ + BCM47XX_BOARD_MICROSOFT_MN700, + + BCM47XX_BOARD_MOTOROLA_WE800G, diff --git a/target/linux/brcm47xx/patches-4.1/031-08-mips-bcm47xx-allow-retrieval-of-complete-nvram-conte.patch b/target/linux/brcm47xx/patches-4.1/031-08-mips-bcm47xx-allow-retrieval-of-complete-nvram-conte.patch new file mode 100644 index 0000000..105c651 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-08-mips-bcm47xx-allow-retrieval-of-complete-nvram-conte.patch @@ -0,0 +1,157 @@ +From 2536295c2aeafc769215a6b2883126fa94c90b9a Mon Sep 17 00:00:00 2001 +From: Hante Meuleman +Date: Thu, 21 May 2015 15:27:23 +0200 +Subject: [PATCH] mips: bcm47xx: allow retrieval of complete nvram contents + +Host platforms such as routers supported by OpenWrt can +support NVRAM reading directly from internal NVRAM store. +The brcmfmac for one requires the complete nvram contents +to select what needs to be sent to wireless device. + +Signed-off-by: Arend van Spriel +Signed-off-by: Hante Meuleman +Reviewed-by: Arend Van Spriel +Reviewed-by: Franky (Zhenhui) Lin +Reviewed-by: Pieter-Paul Giesberts +Reviewed-by: Daniel (Deognyoun) Kim +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/10093/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/nvram.c | 60 ++++++++++++++++++++++++++++++++----------- + include/linux/bcm47xx_nvram.h | 15 +++++++++++ + 2 files changed, 60 insertions(+), 15 deletions(-) + +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -94,17 +94,22 @@ static int nvram_find_and_copy(void __io + return -ENXIO; + + found: +- if (header->len > size) +- pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n"); +- if (header->len > NVRAM_SPACE) +- pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", +- header->len, NVRAM_SPACE - 1); +- + src = (u32 *)header; + dst = (u32 *)nvram_buf; + for (i = 0; i < sizeof(struct nvram_header); i += 4) + *dst++ = __raw_readl(src++); +- for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4) ++ header = (struct nvram_header *)nvram_buf; ++ if (header->len > size) { ++ pr_err("The nvram size according to the header seems to be bigger than the partition on flash\n"); ++ header->len = size; ++ } ++ if (header->len >= NVRAM_SPACE) { ++ pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", ++ header->len, NVRAM_SPACE - 1); ++ header->len = NVRAM_SPACE - 1; ++ } ++ /* proceed reading data after header */ ++ for (; i < header->len; i += 4) + *dst++ = readl(src++); + nvram_buf[NVRAM_SPACE - 1] = '\0'; + +@@ -139,6 +144,7 @@ static int nvram_init(void) + #ifdef CONFIG_MTD + struct mtd_info *mtd; + struct nvram_header header; ++ struct nvram_header *pheader; + size_t bytes_read; + int err; + +@@ -147,20 +153,21 @@ static int nvram_init(void) + return -ENODEV; + + err = mtd_read(mtd, 0, sizeof(header), &bytes_read, (uint8_t *)&header); +- if (!err && header.magic == NVRAM_MAGIC) { +- u8 *dst = (uint8_t *)nvram_buf; +- size_t len = header.len; +- +- if (len >= NVRAM_SPACE) { +- len = NVRAM_SPACE - 1; ++ if (!err && header.magic == NVRAM_MAGIC && ++ header.len > sizeof(header)) { ++ if (header.len >= NVRAM_SPACE) { + pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", +- header.len, len); ++ header.len, NVRAM_SPACE); ++ header.len = NVRAM_SPACE - 1; + } + +- err = mtd_read(mtd, 0, len, &bytes_read, dst); ++ err = mtd_read(mtd, 0, header.len, &bytes_read, ++ (u8 *)nvram_buf); + if (err) + return err; + ++ pheader = (struct nvram_header *)nvram_buf; ++ pheader->len = header.len; + return 0; + } + #endif +@@ -219,3 +226,26 @@ int bcm47xx_nvram_gpio_pin(const char *n + return -ENOENT; + } + EXPORT_SYMBOL(bcm47xx_nvram_gpio_pin); ++ ++char *bcm47xx_nvram_get_contents(size_t *nvram_size) ++{ ++ int err; ++ char *nvram; ++ struct nvram_header *header; ++ ++ if (!nvram_buf[0]) { ++ err = nvram_init(); ++ if (err) ++ return NULL; ++ } ++ ++ header = (struct nvram_header *)nvram_buf; ++ *nvram_size = header->len - sizeof(struct nvram_header); ++ nvram = vmalloc(*nvram_size); ++ if (!nvram) ++ return NULL; ++ memcpy(nvram, &nvram_buf[sizeof(struct nvram_header)], *nvram_size); ++ ++ return nvram; ++} ++EXPORT_SYMBOL(bcm47xx_nvram_get_contents); +--- a/include/linux/bcm47xx_nvram.h ++++ b/include/linux/bcm47xx_nvram.h +@@ -10,11 +10,17 @@ + + #include + #include ++#include + + #ifdef CONFIG_BCM47XX + int bcm47xx_nvram_init_from_mem(u32 base, u32 lim); + int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len); + int bcm47xx_nvram_gpio_pin(const char *name); ++char *bcm47xx_nvram_get_contents(size_t *val_len); ++static inline void bcm47xx_nvram_release_contents(char *nvram) ++{ ++ vfree(nvram); ++}; + #else + static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) + { +@@ -29,6 +35,15 @@ static inline int bcm47xx_nvram_gpio_pin + { + return -ENOTSUPP; + }; ++ ++static inline char *bcm47xx_nvram_get_contents(size_t *val_len) ++{ ++ return NULL; ++}; ++ ++static inline void bcm47xx_nvram_release_contents(char *nvram) ++{ ++}; + #endif + + #endif /* __BCM47XX_NVRAM_H */ diff --git a/target/linux/brcm47xx/patches-4.1/031-09-MIPS-BCM47xx-Add-helper-variable-for-storing-NVRAM-l.patch b/target/linux/brcm47xx/patches-4.1/031-09-MIPS-BCM47xx-Add-helper-variable-for-storing-NVRAM-l.patch new file mode 100644 index 0000000..053144a --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-09-MIPS-BCM47xx-Add-helper-variable-for-storing-NVRAM-l.patch @@ -0,0 +1,131 @@ +From f229d75f1472c4cd30f464e4a0f94f410046bd80 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sat, 6 Jun 2015 23:16:23 +0200 +Subject: [PATCH] MIPS: BCM47xx: Add helper variable for storing NVRAM length +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This simplifies code just a bit (also maybe makes it a bit more +intuitive?) and will allow us to stop storing header. Right now we copy +whole NVRAM including its header to the internal buffer. It is not +needed to store a header as we don't access all these details like CRC, +flags, etc. The next improvement that should follow is copying only the +real contents. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Acked-by: Hauke Mehrtens +Cc: linux-mips@linux-mips.org +Cc: Arend van Spriel +Cc: Hante Meuleman +Patchwork: https://patchwork.linux-mips.org/patch/10535/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/nvram.c | 37 ++++++++++++++++--------------------- + 1 file changed, 16 insertions(+), 21 deletions(-) + +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -35,6 +35,7 @@ struct nvram_header { + }; + + static char nvram_buf[NVRAM_SPACE]; ++static size_t nvram_len; + static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000}; + + static u32 find_nvram_size(void __iomem *end) +@@ -60,7 +61,7 @@ static int nvram_find_and_copy(void __io + u32 *src, *dst; + u32 size; + +- if (nvram_buf[0]) { ++ if (nvram_len) { + pr_warn("nvram already initialized\n"); + return -EEXIST; + } +@@ -99,17 +100,18 @@ found: + for (i = 0; i < sizeof(struct nvram_header); i += 4) + *dst++ = __raw_readl(src++); + header = (struct nvram_header *)nvram_buf; +- if (header->len > size) { ++ nvram_len = header->len; ++ if (nvram_len > size) { + pr_err("The nvram size according to the header seems to be bigger than the partition on flash\n"); +- header->len = size; ++ nvram_len = size; + } +- if (header->len >= NVRAM_SPACE) { ++ if (nvram_len >= NVRAM_SPACE) { + pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", + header->len, NVRAM_SPACE - 1); +- header->len = NVRAM_SPACE - 1; ++ nvram_len = NVRAM_SPACE - 1; + } + /* proceed reading data after header */ +- for (; i < header->len; i += 4) ++ for (; i < nvram_len; i += 4) + *dst++ = readl(src++); + nvram_buf[NVRAM_SPACE - 1] = '\0'; + +@@ -144,7 +146,6 @@ static int nvram_init(void) + #ifdef CONFIG_MTD + struct mtd_info *mtd; + struct nvram_header header; +- struct nvram_header *pheader; + size_t bytes_read; + int err; + +@@ -155,20 +156,16 @@ static int nvram_init(void) + err = mtd_read(mtd, 0, sizeof(header), &bytes_read, (uint8_t *)&header); + if (!err && header.magic == NVRAM_MAGIC && + header.len > sizeof(header)) { +- if (header.len >= NVRAM_SPACE) { ++ nvram_len = header.len; ++ if (nvram_len >= NVRAM_SPACE) { + pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", + header.len, NVRAM_SPACE); +- header.len = NVRAM_SPACE - 1; ++ nvram_len = NVRAM_SPACE - 1; + } + +- err = mtd_read(mtd, 0, header.len, &bytes_read, ++ err = mtd_read(mtd, 0, nvram_len, &nvram_len, + (u8 *)nvram_buf); +- if (err) +- return err; +- +- pheader = (struct nvram_header *)nvram_buf; +- pheader->len = header.len; +- return 0; ++ return err; + } + #endif + +@@ -183,7 +180,7 @@ int bcm47xx_nvram_getenv(const char *nam + if (!name) + return -EINVAL; + +- if (!nvram_buf[0]) { ++ if (!nvram_len) { + err = nvram_init(); + if (err) + return err; +@@ -231,16 +228,14 @@ char *bcm47xx_nvram_get_contents(size_t + { + int err; + char *nvram; +- struct nvram_header *header; + +- if (!nvram_buf[0]) { ++ if (!nvram_len) { + err = nvram_init(); + if (err) + return NULL; + } + +- header = (struct nvram_header *)nvram_buf; +- *nvram_size = header->len - sizeof(struct nvram_header); ++ *nvram_size = nvram_len - sizeof(struct nvram_header); + nvram = vmalloc(*nvram_size); + if (!nvram) + return NULL; diff --git a/target/linux/brcm47xx/patches-4.1/031-10-MIPS-BCM47xx-Don-t-select-BCMA_HOST_PCI.patch b/target/linux/brcm47xx/patches-4.1/031-10-MIPS-BCM47xx-Don-t-select-BCMA_HOST_PCI.patch new file mode 100644 index 0000000..5bcbaa5 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/031-10-MIPS-BCM47xx-Don-t-select-BCMA_HOST_PCI.patch @@ -0,0 +1,30 @@ +From 5521bb0c510ed5c1881636524badfb9bc951f6ac Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Sun, 7 Jun 2015 13:26:44 +0200 +Subject: [PATCH] MIPS: BCM47xx: Don't select BCMA_HOST_PCI +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +SoC may have non-Broadcom PCI device attached or one may want to use +totally different PCI driver. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +Cc: linux-mips@linux-mips.org +Cc: Hauke Mehrtens +Patchwork: https://patchwork.linux-mips.org/patch/10537/ +Signed-off-by: Ralf Baechle +--- + arch/mips/bcm47xx/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/mips/bcm47xx/Kconfig ++++ b/arch/mips/bcm47xx/Kconfig +@@ -25,7 +25,6 @@ config BCM47XX_BCMA + select BCMA + select BCMA_HOST_SOC + select BCMA_DRIVER_MIPS +- select BCMA_HOST_PCI if PCI + select BCMA_DRIVER_PCI_HOSTMODE if PCI + select BCMA_DRIVER_GPIO + default y diff --git a/target/linux/brcm47xx/patches-4.1/159-cpu_fixes.patch b/target/linux/brcm47xx/patches-4.1/159-cpu_fixes.patch new file mode 100644 index 0000000..11d90ec --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/159-cpu_fixes.patch @@ -0,0 +1,391 @@ +--- a/arch/mips/include/asm/r4kcache.h ++++ b/arch/mips/include/asm/r4kcache.h +@@ -25,6 +25,20 @@ + extern void (*r4k_blast_dcache)(void); + extern void (*r4k_blast_icache)(void); + ++#ifdef CONFIG_BCM47XX ++#include ++#include ++#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE))) ++ ++#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr)) ++#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); }) ++#else ++#define BCM4710_DUMMY_RREG() ++ ++#define BCM4710_FILL_TLB(addr) ++#define BCM4710_PROTECTED_FILL_TLB(addr) ++#endif ++ + /* + * This macro return a properly sign-extended address suitable as base address + * for indexed cache operations. Two issues here: +@@ -98,6 +112,7 @@ static inline void flush_icache_line_ind + static inline void flush_dcache_line_indexed(unsigned long addr) + { + __dflush_prologue ++ BCM4710_DUMMY_RREG(); + cache_op(Index_Writeback_Inv_D, addr); + __dflush_epilogue + } +@@ -125,6 +140,7 @@ static inline void flush_icache_line(uns + static inline void flush_dcache_line(unsigned long addr) + { + __dflush_prologue ++ BCM4710_DUMMY_RREG(); + cache_op(Hit_Writeback_Inv_D, addr); + __dflush_epilogue + } +@@ -132,6 +148,7 @@ static inline void flush_dcache_line(uns + static inline void invalidate_dcache_line(unsigned long addr) + { + __dflush_prologue ++ BCM4710_DUMMY_RREG(); + cache_op(Hit_Invalidate_D, addr); + __dflush_epilogue + } +@@ -187,6 +204,7 @@ static inline void protected_flush_icach + #ifdef CONFIG_EVA + protected_cachee_op(Hit_Invalidate_I, addr); + #else ++ BCM4710_DUMMY_RREG(); + protected_cache_op(Hit_Invalidate_I, addr); + #endif + break; +@@ -201,6 +219,7 @@ static inline void protected_flush_icach + */ + static inline void protected_writeback_dcache_line(unsigned long addr) + { ++ BCM4710_DUMMY_RREG(); + #ifdef CONFIG_EVA + protected_cachee_op(Hit_Writeback_Inv_D, addr); + #else +@@ -554,8 +573,51 @@ static inline void invalidate_tcache_pag + : "r" (base), \ + "i" (op)); + ++static inline void blast_dcache(void) ++{ ++ unsigned long start = KSEG0; ++ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways; ++ unsigned long end = (start + dcache_size); ++ ++ do { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Index_Writeback_Inv_D, start); ++ start += current_cpu_data.dcache.linesz; ++ } while(start < end); ++} ++ ++static inline void blast_dcache_page(unsigned long page) ++{ ++ unsigned long start = page; ++ unsigned long end = start + PAGE_SIZE; ++ ++ BCM4710_FILL_TLB(start); ++ do { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Hit_Writeback_Inv_D, start); ++ start += current_cpu_data.dcache.linesz; ++ } while(start < end); ++} ++ ++static inline void blast_dcache_page_indexed(unsigned long page) ++{ ++ unsigned long start = page; ++ unsigned long end = start + PAGE_SIZE; ++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; ++ unsigned long ws_end = current_cpu_data.dcache.ways << ++ current_cpu_data.dcache.waybit; ++ unsigned long ws, addr; ++ for (ws = 0; ws < ws_end; ws += ws_inc) { ++ start = page + ws; ++ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) { ++ BCM4710_DUMMY_RREG(); ++ cache_op(Index_Writeback_Inv_D, addr); ++ } ++ } ++} ++ + /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ +-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \ ++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \ + static inline void extra##blast_##pfx##cache##lsize(void) \ + { \ + unsigned long start = INDEX_BASE; \ +@@ -567,6 +629,7 @@ static inline void extra##blast_##pfx##c + \ + __##pfx##flush_prologue \ + \ ++ war \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache##lsize##_unroll32(addr|ws, indexop); \ +@@ -581,6 +644,7 @@ static inline void extra##blast_##pfx##c + \ + __##pfx##flush_prologue \ + \ ++ war \ + do { \ + cache##lsize##_unroll32(start, hitop); \ + start += lsize * 32; \ +@@ -599,6 +663,8 @@ static inline void extra##blast_##pfx##c + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ ++ war \ ++ \ + __##pfx##flush_prologue \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ +@@ -608,26 +674,26 @@ static inline void extra##blast_##pfx##c + __##pfx##flush_epilogue \ + } + +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, ) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, ) +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, ) +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, ) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, ) +-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, ) +-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, ) +-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, ) +- +-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) +-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, ) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, ) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, ) +-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , ) ++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , ) ++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , ) ++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , ) ++ ++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , ) ++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , ) ++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , ) + + #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \ + static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ +@@ -656,17 +722,19 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde + __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) + + /* build blast_xxx_range, protected_blast_xxx_range */ +-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ ++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \ + static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ + unsigned long end) \ + { \ + unsigned long lsize = cpu_##desc##_line_size(); \ + unsigned long addr = start & ~(lsize - 1); \ + unsigned long aend = (end - 1) & ~(lsize - 1); \ ++ war \ + \ + __##pfx##flush_prologue \ + \ + while (1) { \ ++ war2 \ + prot##cache_op(hitop, addr); \ + if (addr == aend) \ + break; \ +@@ -678,8 +746,8 @@ static inline void prot##extra##blast_## + + #ifndef CONFIG_EVA + +-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) +-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , ) + + #else + +@@ -716,14 +784,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache + __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I) + + #endif +-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , ) + __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ +- protected_, loongson2_) +-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) +-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) +-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) ++ protected_, loongson2_, , ) ++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , ) ++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , ) + /* blast_inv_dcache_range */ +-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) +-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) ++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();) ++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , ) + + #endif /* _ASM_R4KCACHE_H */ +--- a/arch/mips/include/asm/stackframe.h ++++ b/arch/mips/include/asm/stackframe.h +@@ -358,6 +358,10 @@ + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) + .set arch=r4000 ++#ifdef CONFIG_BCM47XX ++ nop ++ nop ++#endif + eret + .set mips0 + .endm +--- a/arch/mips/kernel/genex.S ++++ b/arch/mips/kernel/genex.S +@@ -32,6 +32,10 @@ + NESTED(except_vec3_generic, 0, sp) + .set push + .set noat ++#ifdef CONFIG_BCM47XX ++ nop ++ nop ++#endif + #if R5432_CP0_INTERRUPT_WAR + mfc0 k0, CP0_INDEX + #endif +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -39,6 +39,9 @@ + #include + #include + ++/* For enabling BCM4710 cache workarounds */ ++int bcm4710 = 0; ++ + /* + * Special Variant of smp_call_function for use by cache functions: + * +@@ -157,6 +160,9 @@ static void r4k_blast_dcache_user_page_s + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache_page = blast_dcache_page; ++ else + if (dc_lsize == 0) + r4k_blast_dcache_user_page = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -175,6 +181,9 @@ static void r4k_blast_dcache_page_indexe + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed; ++ else + if (dc_lsize == 0) + r4k_blast_dcache_page_indexed = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -194,6 +203,9 @@ static void r4k_blast_dcache_setup(void) + { + unsigned long dc_lsize = cpu_dcache_line_size(); + ++ if (bcm4710) ++ r4k_blast_dcache = blast_dcache; ++ else + if (dc_lsize == 0) + r4k_blast_dcache = (void *)cache_noop; + else if (dc_lsize == 16) +@@ -793,6 +805,8 @@ static void local_r4k_flush_cache_sigtra + unsigned long addr = (unsigned long) arg; + + R4600_HIT_CACHEOP_WAR_IMPL; ++ BCM4710_PROTECTED_FILL_TLB(addr); ++ BCM4710_PROTECTED_FILL_TLB(addr + 4); + if (dc_lsize) + protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); + if (!cpu_icache_snoops_remote_store && scache_size) +@@ -1599,6 +1613,17 @@ static void coherency_setup(void) + * silly idea of putting something else there ... + */ + switch (current_cpu_type()) { ++ case CPU_BMIPS3300: ++ { ++ u32 cm; ++ cm = read_c0_diag(); ++ /* Enable icache */ ++ cm |= (1 << 31); ++ /* Enable dcache */ ++ cm |= (1 << 30); ++ write_c0_diag(cm); ++ } ++ break; + case CPU_R4000PC: + case CPU_R4000SC: + case CPU_R4000MC: +@@ -1645,6 +1670,15 @@ void r4k_cache_init(void) + extern void build_copy_page(void); + struct cpuinfo_mips *c = ¤t_cpu_data; + ++ /* Check if special workarounds are required */ ++#ifdef CONFIG_BCM47XX ++ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) { ++ printk("Enabling BCM4710A0 cache workarounds.\n"); ++ bcm4710 = 1; ++ } else ++#endif ++ bcm4710 = 0; ++ + probe_pcache(); + setup_scache(); + +@@ -1714,7 +1748,15 @@ void r4k_cache_init(void) + */ + local_r4k___flush_cache_all(NULL); + ++#ifdef CONFIG_BCM47XX ++ { ++ static void (*_coherency_setup)(void); ++ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup); ++ _coherency_setup(); ++ } ++#else + coherency_setup(); ++#endif + board_cache_error_setup = r4k_cache_error_setup; + + /* +--- a/arch/mips/mm/tlbex.c ++++ b/arch/mips/mm/tlbex.c +@@ -1296,6 +1296,9 @@ static void build_r4000_tlb_refill_handl + /* No need for uasm_i_nop */ + } + ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(&p); ++#endif + #ifdef CONFIG_64BIT + build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ + #else +@@ -1868,6 +1871,9 @@ build_r4000_tlbchange_handler_head(u32 * + { + struct work_registers wr = build_get_work_registers(p); + ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(p); ++#endif + #ifdef CONFIG_64BIT + build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ + #else diff --git a/target/linux/brcm47xx/patches-4.1/160-kmap_coherent.patch b/target/linux/brcm47xx/patches-4.1/160-kmap_coherent.patch new file mode 100644 index 0000000..f66e759 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/160-kmap_coherent.patch @@ -0,0 +1,78 @@ +From: Jeff Hansen +Subject: [PATCH] kmap_coherent + +On ASUS WL-500gP there are some "Data bus error"s when executing simple +commands liks "ps" or "cat /proc/1/cmdline". + +This fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485 +--- +--- a/arch/mips/include/asm/cpu-features.h ++++ b/arch/mips/include/asm/cpu-features.h +@@ -158,6 +158,9 @@ + #ifndef cpu_has_local_ebase + #define cpu_has_local_ebase 1 + #endif ++#ifndef cpu_use_kmap_coherent ++#define cpu_use_kmap_coherent 1 ++#endif + + /* + * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors +--- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h ++++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h +@@ -79,4 +79,6 @@ + #define cpu_scache_line_size() 0 + #define cpu_has_vz 0 + ++#define cpu_use_kmap_coherent 0 ++ + #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */ +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -600,7 +600,7 @@ static inline void local_r4k_flush_cache + */ + map_coherent = (cpu_has_dc_aliases && + page_mapped(page) && !Page_dcache_dirty(page)); +- if (map_coherent) ++ if (map_coherent && cpu_use_kmap_coherent) + vaddr = kmap_coherent(page, addr); + else + vaddr = kmap_atomic(page); +@@ -625,7 +625,7 @@ static inline void local_r4k_flush_cache + } + + if (vaddr) { +- if (map_coherent) ++ if (map_coherent && cpu_use_kmap_coherent) + kunmap_coherent(); + else + kunmap_atomic(vaddr); +--- a/arch/mips/mm/init.c ++++ b/arch/mips/mm/init.c +@@ -160,7 +160,7 @@ void copy_user_highpage(struct page *to, + void *vfrom, *vto; + + vto = kmap_atomic(to); +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapped(from) && !Page_dcache_dirty(from)) { + vfrom = kmap_coherent(from, vaddr); + copy_page(vto, vfrom); +@@ -182,7 +182,7 @@ void copy_to_user_page(struct vm_area_st + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) + { +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapped(page) && !Page_dcache_dirty(page)) { + void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(vto, src, len); +@@ -200,7 +200,7 @@ void copy_from_user_page(struct vm_area_ + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) + { +- if (cpu_has_dc_aliases && ++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && + page_mapped(page) && !Page_dcache_dirty(page)) { + void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); + memcpy(dst, vfrom, len); diff --git a/target/linux/brcm47xx/patches-4.1/209-b44-register-adm-switch.patch b/target/linux/brcm47xx/patches-4.1/209-b44-register-adm-switch.patch new file mode 100644 index 0000000..777744c --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/209-b44-register-adm-switch.patch @@ -0,0 +1,122 @@ +From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sat, 9 Nov 2013 17:03:59 +0100 +Subject: [PATCH 210/210] b44: register adm switch + +--- + drivers/net/ethernet/broadcom/b44.c | 57 +++++++++++++++++++++++++++++++++++ + drivers/net/ethernet/broadcom/b44.h | 3 ++ + 2 files changed, 60 insertions(+) + +--- a/drivers/net/ethernet/broadcom/b44.c ++++ b/drivers/net/ethernet/broadcom/b44.c +@@ -31,6 +31,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -2240,6 +2242,70 @@ static void b44_adjust_link(struct net_d + } + } + ++#ifdef CONFIG_BCM47XX ++static int b44_register_adm_switch(struct b44 *bp) ++{ ++ int gpio; ++ struct platform_device *pdev; ++ struct adm6996_gpio_platform_data adm_data = {0}; ++ struct platform_device_info info = {0}; ++ ++ adm_data.model = ADM6996L; ++ gpio = bcm47xx_nvram_gpio_pin("adm_eecs"); ++ if (gpio >= 0) ++ adm_data.eecs = gpio; ++ else ++ adm_data.eecs = 2; ++ ++ gpio = bcm47xx_nvram_gpio_pin("adm_eesk"); ++ if (gpio >= 0) ++ adm_data.eesk = gpio; ++ else ++ adm_data.eesk = 3; ++ ++ gpio = bcm47xx_nvram_gpio_pin("adm_eedi"); ++ if (gpio >= 0) ++ adm_data.eedi = gpio; ++ else ++ adm_data.eedi = 4; ++ ++ gpio = bcm47xx_nvram_gpio_pin("adm_rc"); ++ if (gpio >= 0) ++ adm_data.eerc = gpio; ++ else ++ adm_data.eerc = 5; ++ ++ info.parent = bp->sdev->dev; ++ info.name = "adm6996_gpio"; ++ info.id = -1; ++ info.data = &adm_data; ++ info.size_data = sizeof(adm_data); ++ ++ if (!bp->adm_switch) { ++ pdev = platform_device_register_full(&info); ++ if (IS_ERR(pdev)) ++ return PTR_ERR(pdev); ++ ++ bp->adm_switch = pdev; ++ } ++ return 0; ++} ++static void b44_unregister_adm_switch(struct b44 *bp) ++{ ++ if (bp->adm_switch) ++ platform_device_unregister(bp->adm_switch); ++} ++#else ++static int b44_register_adm_switch(struct b44 *bp) ++{ ++ return 0; ++} ++static void b44_unregister_adm_switch(struct b44 *bp) ++{ ++ ++} ++#endif /* CONFIG_BCM47XX */ ++ + static int b44_register_phy_one(struct b44 *bp) + { + struct mii_bus *mii_bus; +@@ -2283,6 +2349,9 @@ static int b44_register_phy_one(struct b + if (!bp->mii_bus->phy_map[bp->phy_addr] && + (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) { + ++ if (sprom->boardflags_lo & B44_BOARDFLAG_ADM) ++ b44_register_adm_switch(bp); ++ + dev_info(sdev->dev, + "could not find PHY at %i, use fixed one\n", + bp->phy_addr); +@@ -2479,6 +2548,7 @@ static void b44_remove_one(struct ssb_de + unregister_netdev(dev); + if (bp->flags & B44_FLAG_EXTERNAL_PHY) + b44_unregister_phy_one(bp); ++ b44_unregister_adm_switch(bp); + ssb_device_disable(sdev, 0); + ssb_bus_may_powerdown(sdev->bus); + netif_napi_del(&bp->napi); +--- a/drivers/net/ethernet/broadcom/b44.h ++++ b/drivers/net/ethernet/broadcom/b44.h +@@ -404,6 +404,9 @@ struct b44 { + struct mii_bus *mii_bus; + int old_link; + struct mii_if_info mii_if; ++ ++ /* platform device for associated switch */ ++ struct platform_device *adm_switch; + }; + + #endif /* _B44_H */ diff --git a/target/linux/brcm47xx/patches-4.1/210-b44_phy_fix.patch b/target/linux/brcm47xx/patches-4.1/210-b44_phy_fix.patch new file mode 100644 index 0000000..04f6832 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/210-b44_phy_fix.patch @@ -0,0 +1,54 @@ +--- a/drivers/net/ethernet/broadcom/b44.c ++++ b/drivers/net/ethernet/broadcom/b44.c +@@ -431,10 +431,34 @@ static void b44_wap54g10_workaround(stru + error: + pr_warn("PHY: cannot reset MII transceiver isolate bit\n"); + } ++ ++static void b44_bcm47xx_workarounds(struct b44 *bp) ++{ ++ char buf[20]; ++ struct ssb_device *sdev = bp->sdev; ++ ++ /* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */ ++ if (sdev->bus->sprom.board_num == 100) { ++ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY; ++ } else { ++ /* WL-HDD */ ++ if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 && ++ !strncmp(buf, "WL300-", strlen("WL300-"))) { ++ if (sdev->bus->sprom.et0phyaddr == 0 && ++ sdev->bus->sprom.et1phyaddr == 1) ++ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY; ++ } ++ } ++ return; ++} + #else + static inline void b44_wap54g10_workaround(struct b44 *bp) + { + } ++ ++static inline void b44_bcm47xx_workarounds(struct b44 *bp) ++{ ++} + #endif + + static int b44_setup_phy(struct b44 *bp) +@@ -443,6 +467,7 @@ static int b44_setup_phy(struct b44 *bp) + int err; + + b44_wap54g10_workaround(bp); ++ b44_bcm47xx_workarounds(bp); + + if (bp->flags & B44_FLAG_EXTERNAL_PHY) + return 0; +@@ -2170,6 +2195,8 @@ static int b44_get_invariants(struct b44 + * valid PHY address. */ + bp->phy_addr &= 0x1F; + ++ b44_bcm47xx_workarounds(bp); ++ + memcpy(bp->dev->dev_addr, addr, ETH_ALEN); + + if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){ diff --git a/target/linux/brcm47xx/patches-4.1/280-activate_ssb_support_in_usb.patch b/target/linux/brcm47xx/patches-4.1/280-activate_ssb_support_in_usb.patch new file mode 100644 index 0000000..33fefdd --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/280-activate_ssb_support_in_usb.patch @@ -0,0 +1,25 @@ +This prevents the options from being delete with make kernel_oldconfig. +--- + drivers/ssb/Kconfig | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -33,6 +33,7 @@ config BCMA_HOST_PCI + config BCMA_HOST_SOC + bool "Support for BCMA in a SoC" + depends on BCMA ++ select USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD + help + Host interface for a Broadcom AIX bus directly mapped into + the memory. This only works with the Broadcom SoCs from the +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -147,6 +147,7 @@ config SSB_SFLASH + config SSB_EMBEDDED + bool + depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE ++ select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD + default y + + config SSB_DRIVER_EXTIF diff --git a/target/linux/brcm47xx/patches-4.1/300-fork_cacheflush.patch b/target/linux/brcm47xx/patches-4.1/300-fork_cacheflush.patch new file mode 100644 index 0000000..daa2c1a --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/300-fork_cacheflush.patch @@ -0,0 +1,21 @@ +From: Wolfram Joost +Subject: [PATCH] fork_cacheflush + +On ASUS WL-500gP there are many unexpected "Segmentation fault"s that +seem to be caused by a kernel. They can be avoided by: +1) Disabling highpage +2) Using flush_cache_mm in flush_cache_dup_mm + +For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035 +--- +--- a/arch/mips/include/asm/cacheflush.h ++++ b/arch/mips/include/asm/cacheflush.h +@@ -46,7 +46,7 @@ + extern void (*flush_cache_all)(void); + extern void (*__flush_cache_all)(void); + extern void (*flush_cache_mm)(struct mm_struct *mm); +-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0) ++#define flush_cache_dup_mm(mm) flush_cache_mm(mm) + extern void (*flush_cache_range)(struct vm_area_struct *vma, + unsigned long start, unsigned long end); + extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); diff --git a/target/linux/brcm47xx/patches-4.1/310-no_highpage.patch b/target/linux/brcm47xx/patches-4.1/310-no_highpage.patch new file mode 100644 index 0000000..91b6ab5 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/310-no_highpage.patch @@ -0,0 +1,74 @@ +From: Jeff Hansen +Subject: [PATCH] no highpage + +On ASUS WL-500gP there are many unexpected "Segmentation fault"s that +seem to be caused by a kernel. They can be avoided by: +1) Disabling highpage +2) Using flush_cache_mm in flush_cache_dup_mm + +For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035 +--- +--- a/arch/mips/include/asm/page.h ++++ b/arch/mips/include/asm/page.h +@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl + #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ + + #include ++#include + + extern void build_clear_page(void); + extern void build_copy_page(void); +@@ -105,11 +106,16 @@ static inline void clear_user_page(void + flush_data_cache_page((unsigned long)addr); + } + +-struct vm_area_struct; +-extern void copy_user_highpage(struct page *to, struct page *from, +- unsigned long vaddr, struct vm_area_struct *vma); ++static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, ++ struct page *to) ++{ ++ extern void (*flush_data_cache_page)(unsigned long addr); + +-#define __HAVE_ARCH_COPY_USER_HIGHPAGE ++ copy_page(vto, vfrom); ++ if (!cpu_has_ic_fills_f_dc || ++ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) ++ flush_data_cache_page((unsigned long)vto); ++} + + /* + * These are used to make use of C type-checking.. +--- a/arch/mips/mm/init.c ++++ b/arch/mips/mm/init.c +@@ -154,30 +154,6 @@ void kunmap_coherent(void) + pagefault_enable(); + } + +-void copy_user_highpage(struct page *to, struct page *from, +- unsigned long vaddr, struct vm_area_struct *vma) +-{ +- void *vfrom, *vto; +- +- vto = kmap_atomic(to); +- if (cpu_has_dc_aliases && cpu_use_kmap_coherent && +- page_mapped(from) && !Page_dcache_dirty(from)) { +- vfrom = kmap_coherent(from, vaddr); +- copy_page(vto, vfrom); +- kunmap_coherent(); +- } else { +- vfrom = kmap_atomic(from); +- copy_page(vto, vfrom); +- kunmap_atomic(vfrom); +- } +- if ((!cpu_has_ic_fills_f_dc) || +- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) +- flush_data_cache_page((unsigned long)vto); +- kunmap_atomic(vto); +- /* Make sure this page is cleared on other CPU's too before using it */ +- smp_wmb(); +-} +- + void copy_to_user_page(struct vm_area_struct *vma, + struct page *page, unsigned long vaddr, void *dst, const void *src, + unsigned long len) diff --git a/target/linux/brcm47xx/patches-4.1/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch b/target/linux/brcm47xx/patches-4.1/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch new file mode 100644 index 0000000..e19a458 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch @@ -0,0 +1,204 @@ +--- a/arch/mips/bcm47xx/board.c ++++ b/arch/mips/bcm47xx/board.c +@@ -140,6 +140,7 @@ struct bcm47xx_board_type_list2 bcm47xx_ + {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"}, + {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"}, ++ {{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, + {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, +@@ -150,6 +151,7 @@ struct bcm47xx_board_type_list2 bcm47xx_ + static const + struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = { + {{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"}, ++ {{BCM47XX_BOARD_NETGEAR_R6300_V1, "Netgear R6300 V1"}, "U12H218T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"}, +@@ -162,6 +164,7 @@ struct bcm47xx_board_type_list1 bcm47xx_ + {{BCM47XX_BOARD_NETGEAR_WNDR4000, "Netgear WNDR4000"}, "U12H181T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR4500V1, "Netgear WNDR4500 V1"}, "U12H189T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNDR4500V2, "Netgear WNDR4500 V2"}, "U12H224T00_NETGEAR"}, ++ {{BCM47XX_BOARD_NETGEAR_WNR1000_V3, "Netgear WNR1000 V3"}, "U12H139T50_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"}, + {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"}, +--- a/arch/mips/bcm47xx/buttons.c ++++ b/arch/mips/bcm47xx/buttons.c +@@ -20,6 +20,12 @@ + /* Asus */ + + static const struct gpio_keys_button ++bcm47xx_buttons_asus_rtn10u[] __initconst = { ++ BCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON), ++ BCM47XX_GPIO_KEY(21, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_asus_rtn12[] __initconst = { + BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), + BCM47XX_GPIO_KEY(1, KEY_RESTART), +@@ -270,6 +276,18 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in + }; + + static const struct gpio_keys_button ++bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = { ++ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), ++ BCM47XX_GPIO_KEY(6, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button ++bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = { ++ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), ++ BCM47XX_GPIO_KEY(8, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = { + BCM47XX_GPIO_KEY(5, KEY_WIMAX), + BCM47XX_GPIO_KEY(6, KEY_RESTART), +@@ -333,6 +351,11 @@ bcm47xx_buttons_motorola_wr850gv2v3[] __ + /* Netgear */ + + static const struct gpio_keys_button ++bcm47xx_buttons_netgear_r6300_v1[] __initconst = { ++ BCM47XX_GPIO_KEY(6, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_netgear_wndr3400v1[] __initconst = { + BCM47XX_GPIO_KEY(4, KEY_RESTART), + BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), +@@ -360,6 +383,11 @@ bcm47xx_buttons_netgear_wndr4500v1[] __i + }; + + static const struct gpio_keys_button ++bcm47xx_buttons_netgear_wnr1000_v3[] __initconst = { ++ BCM47XX_GPIO_KEY(3, KEY_RESTART), ++}; ++ ++static const struct gpio_keys_button + bcm47xx_buttons_netgear_wnr3500lv1[] __initconst = { + BCM47XX_GPIO_KEY(4, KEY_RESTART), + BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), +@@ -414,6 +442,9 @@ int __init bcm47xx_buttons_register(void + int err; + + switch (board) { ++ case BCM47XX_BOARD_ASUS_RTN10U: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u); ++ break; + case BCM47XX_BOARD_ASUS_RTN12: + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12); + break; +@@ -544,6 +575,12 @@ int __init bcm47xx_buttons_register(void + case BCM47XX_BOARD_LINKSYS_WRT310NV1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1); + break; ++ case BCM47XX_BOARD_LINKSYS_WRT310NV2: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2); ++ break; ++ case BCM47XX_BOARD_LINKSYS_WRT320N_V1: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1); ++ break; + case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2); + break; +@@ -580,6 +617,9 @@ int __init bcm47xx_buttons_register(void + err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_wr850gv2v3); + break; + ++ case BCM47XX_BOARD_NETGEAR_R6300_V1: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1); ++ break; + case BCM47XX_BOARD_NETGEAR_WNDR3400V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1); + break; +@@ -592,6 +632,9 @@ int __init bcm47xx_buttons_register(void + case BCM47XX_BOARD_NETGEAR_WNDR4500V1: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr4500v1); + break; ++ case BCM47XX_BOARD_NETGEAR_WNR1000_V3: ++ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr1000_v3); ++ break; + case BCM47XX_BOARD_NETGEAR_WNR3500L: + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv1); + break; +--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h ++++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +@@ -71,6 +71,7 @@ enum bcm47xx_board { + BCM47XX_BOARD_LINKSYS_WRT300NV11, + BCM47XX_BOARD_LINKSYS_WRT310NV1, + BCM47XX_BOARD_LINKSYS_WRT310NV2, ++ BCM47XX_BOARD_LINKSYS_WRT320N_V1, + BCM47XX_BOARD_LINKSYS_WRT54G3GV2, + BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, + BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, +@@ -88,6 +89,7 @@ enum bcm47xx_board { + BCM47XX_BOARD_MOTOROLA_WR850GP, + BCM47XX_BOARD_MOTOROLA_WR850GV2V3, + ++ BCM47XX_BOARD_NETGEAR_R6300_V1, + BCM47XX_BOARD_NETGEAR_WGR614V8, + BCM47XX_BOARD_NETGEAR_WGR614V9, + BCM47XX_BOARD_NETGEAR_WGR614_V10, +@@ -100,6 +102,7 @@ enum bcm47xx_board { + BCM47XX_BOARD_NETGEAR_WNDR4000, + BCM47XX_BOARD_NETGEAR_WNDR4500V1, + BCM47XX_BOARD_NETGEAR_WNDR4500V2, ++ BCM47XX_BOARD_NETGEAR_WNR1000_V3, + BCM47XX_BOARD_NETGEAR_WNR2000, + BCM47XX_BOARD_NETGEAR_WNR3500L, + BCM47XX_BOARD_NETGEAR_WNR3500U, +--- a/arch/mips/bcm47xx/leds.c ++++ b/arch/mips/bcm47xx/leds.c +@@ -29,6 +29,14 @@ + /* Asus */ + + static const struct gpio_led ++bcm47xx_leds_asus_rtn10u[] __initconst = { ++ BCM47XX_GPIO_LED(5, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(6, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON), ++ BCM47XX_GPIO_LED(7, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(8, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF), ++}; ++ ++static const struct gpio_led + bcm47xx_leds_asus_rtn12[] __initconst = { + BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), + BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), +@@ -313,6 +321,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc + }; + + static const struct gpio_led ++bcm47xx_leds_linksys_wrt320n_v1[] __initconst = { ++ BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), ++ BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON), ++ BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), ++}; ++ ++static const struct gpio_led + bcm47xx_leds_linksys_wrt54g_generic[] __initconst = { + BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF), + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), +@@ -478,6 +493,9 @@ void __init bcm47xx_leds_register(void) + enum bcm47xx_board board = bcm47xx_board_get(); + + switch (board) { ++ case BCM47XX_BOARD_ASUS_RTN10U: ++ bcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u); ++ break; + case BCM47XX_BOARD_ASUS_RTN12: + bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12); + break; +@@ -611,6 +629,9 @@ void __init bcm47xx_leds_register(void) + case BCM47XX_BOARD_LINKSYS_WRT310NV1: + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1); + break; ++ case BCM47XX_BOARD_LINKSYS_WRT320N_V1: ++ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1); ++ break; + case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2); + break; diff --git a/target/linux/brcm47xx/patches-4.1/400-mtd-bcm47xxpart-get-nvram.patch b/target/linux/brcm47xx/patches-4.1/400-mtd-bcm47xxpart-get-nvram.patch new file mode 100644 index 0000000..df51191 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/400-mtd-bcm47xxpart-get-nvram.patch @@ -0,0 +1,34 @@ +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -97,6 +97,7 @@ static int bcm47xxpart_parse(struct mtd_ + int trx_part = -1; + int last_trx_part = -1; + int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, }; ++ bool found_nvram = false; + + /* + * Some really old flashes (like AT45DB*) had smaller erasesize-s, but +@@ -300,12 +301,23 @@ static int bcm47xxpart_parse(struct mtd_ + if (buf[0] == NVRAM_HEADER) { + bcm47xxpart_add_part(&parts[curr_part++], "nvram", + master->size - blocksize, 0); ++ found_nvram = true; + break; + } + } + + kfree(buf); + ++ if (!found_nvram) { ++ pr_err("can not find a nvram partition reserve last block\n"); ++ bcm47xxpart_add_part(&parts[curr_part++], "nvram_guess", ++ master->size - blocksize * 2, MTD_WRITEABLE); ++ for (i = 0; i < curr_part; i++) { ++ if (parts[i].size + parts[i].offset == master->size) ++ parts[i].offset -= blocksize * 2; ++ } ++ } ++ + /* + * Assume that partitions end at the beginning of the one they are + * followed by. diff --git a/target/linux/brcm47xx/patches-4.1/610-pci_ide_fix.patch b/target/linux/brcm47xx/patches-4.1/610-pci_ide_fix.patch new file mode 100644 index 0000000..b68b9c2 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/610-pci_ide_fix.patch @@ -0,0 +1,41 @@ +From: b.sander +Subject: [PATCH] pci: IDE fix + +These are standard probing messages when using pdc202xx_old: +pdc202xx_old 0000:00:01.0: IDE controller (0x105a:0x0d30 rev 0x02) +PCI: Enabling device 0000:00:01.0 (0004 -> 0007) +PCI: Fixing up device 0000:00:01.0 +0000:00:01.0: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode. +0000:00:01.0: FORCING BURST BIT 0x00->0x01 ACTIVE +pdc202xx_old 0000:00:01.0: 100% native mode on irq 6 + +With the default MAX_HWIFS value after above we get: + ide2: BM-DMA at 0x0400-0x0407 + ide3: BM-DMA at 0x0408-0x040f +Probing IDE interface ide2... +hde: CF500, CFA DISK drive + +As you can see it's ide2 + ide3 and hde. + +With this patch applied we get: + ide0: BM-DMA at 0x0400-0x0407 + ide1: BM-DMA at 0x0408-0x040f +Probing IDE interface ide0... +hda: CF500, CFA DISK drive + +This fixes OpenWrt ticket #7061: https://dev.openwrt.org/ticket/7061 +--- +--- a/include/linux/ide.h ++++ b/include/linux/ide.h +@@ -191,7 +191,11 @@ static inline void ide_std_init_ports(st + hw->io_ports.ctl_addr = ctl_addr; + } + ++#if defined CONFIG_BCM47XX ++# define MAX_HWIFS 2 ++#else + #define MAX_HWIFS 10 ++#endif + + /* + * Now for the data we need to maintain per-drive: ide_drive_t diff --git a/target/linux/brcm47xx/patches-4.1/791-tg3-no-pci-sleep.patch b/target/linux/brcm47xx/patches-4.1/791-tg3-no-pci-sleep.patch new file mode 100644 index 0000000..35a816d --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/791-tg3-no-pci-sleep.patch @@ -0,0 +1,17 @@ +When the Ethernet controller is powered down and someone wants to +access the mdio bus like the witch driver (b53) the system crashed if +PCI_D3hot was set before. This patch deactivates this power sawing mode +when a switch driver is in use. + +--- a/drivers/net/ethernet/broadcom/tg3.c ++++ b/drivers/net/ethernet/broadcom/tg3.c +@@ -4263,7 +4263,8 @@ static int tg3_power_down_prepare(struct + static void tg3_power_down(struct tg3 *tp) + { + pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); +- pci_set_power_state(tp->pdev, PCI_D3hot); ++ if (!tg3_flag(tp, ROBOSWITCH)) ++ pci_set_power_state(tp->pdev, PCI_D3hot); + } + + static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) diff --git a/target/linux/brcm47xx/patches-4.1/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch b/target/linux/brcm47xx/patches-4.1/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch new file mode 100644 index 0000000..99d909b --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch @@ -0,0 +1,73 @@ +From 597715c61ae75a05ab3310a34ff3857a006f0f63 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 20 Nov 2014 21:32:42 +0100 +Subject: [PATCH] bcma: add table of serial flashes with smaller blocks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/bcma/driver_chipcommon_sflash.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/drivers/bcma/driver_chipcommon_sflash.c ++++ b/drivers/bcma/driver_chipcommon_sflash.c +@@ -9,6 +9,7 @@ + + #include + #include ++#include + + static struct resource bcma_sflash_resource = { + .name = "bcma_sflash", +@@ -41,6 +42,13 @@ static const struct bcma_sflash_tbl_e bc + { NULL }, + }; + ++/* Some devices use smaller blocks (and have more of them) */ ++static const struct bcma_sflash_tbl_e bcma_sflash_st_shrink_tbl[] = { ++ { "M25P16", 0x14, 0x1000, 512, }, ++ { "M25P32", 0x15, 0x1000, 1024, }, ++ { NULL }, ++}; ++ + static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = { + { "SST25WF512", 1, 0x1000, 16, }, + { "SST25VF512", 0x48, 0x1000, 16, }, +@@ -84,6 +92,24 @@ static void bcma_sflash_cmd(struct bcma_ + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n"); + } + ++const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id) ++{ ++ enum bcm47xx_board board = bcm47xx_board_get(); ++ const struct bcma_sflash_tbl_e *e; ++ ++ switch (board) { ++ case BCM47XX_BOARD_NETGEAR_WGR614_V10: ++ case BCM47XX_BOARD_NETGEAR_WNR1000_V3: ++ for (e = bcma_sflash_st_shrink_tbl; e->name; e++) { ++ if (e->id == id) ++ return e; ++ } ++ return NULL; ++ default: ++ return NULL; ++ } ++} ++ + /* Initialize serial flash access */ + int bcma_sflash_init(struct bcma_drv_cc *cc) + { +@@ -114,6 +140,10 @@ int bcma_sflash_init(struct bcma_drv_cc + case 0x13: + return -ENOTSUPP; + default: ++ e = bcma_sflash_shrink_flash(id); ++ if (e) ++ break; ++ + for (e = bcma_sflash_st_tbl; e->name; e++) { + if (e->id == id) + break; diff --git a/target/linux/brcm47xx/patches-4.1/820-wgt634u-nvram-fix.patch b/target/linux/brcm47xx/patches-4.1/820-wgt634u-nvram-fix.patch new file mode 100644 index 0000000..4738c22 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/820-wgt634u-nvram-fix.patch @@ -0,0 +1,295 @@ +The Netgear wgt634u uses a different format for storing the +configuration. This patch is needed to read out the correct +configuration. The cfe_env.c file uses a different method way to read +out the configuration than the in kernel cfe config reader. + +--- a/arch/mips/bcm47xx/Makefile ++++ b/arch/mips/bcm47xx/Makefile +@@ -5,3 +5,4 @@ + + obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o + obj-y += board.o buttons.o leds.o workarounds.o ++obj-y += cfe_env.o +--- /dev/null ++++ b/arch/mips/bcm47xx/cfe_env.c +@@ -0,0 +1,228 @@ ++/* ++ * CFE environment variable access ++ * ++ * Copyright 2001-2003, Broadcom Corporation ++ * Copyright 2006, Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define NVRAM_SIZE (0x1ff0) ++static char _nvdata[NVRAM_SIZE]; ++static char _valuestr[256]; ++ ++/* ++ * TLV types. These codes are used in the "type-length-value" ++ * encoding of the items stored in the NVRAM device (flash or EEPROM) ++ * ++ * The layout of the flash/nvram is as follows: ++ * ++ * ++ * ++ * The type code of "ENV_TLV_TYPE_END" marks the end of the list. ++ * The "length" field marks the length of the data section, not ++ * including the type and length fields. ++ * ++ * Environment variables are stored as follows: ++ * ++ * = ++ * ++ * If bit 0 (low bit) is set, the length is an 8-bit value. ++ * If bit 0 (low bit) is clear, the length is a 16-bit value ++ * ++ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still ++ * indicates the size of the length field. ++ * ++ * Flags are from the constants below: ++ * ++ */ ++#define ENV_LENGTH_16BITS 0x00 /* for low bit */ ++#define ENV_LENGTH_8BITS 0x01 ++ ++#define ENV_TYPE_USER 0x80 ++ ++#define ENV_CODE_SYS(n,l) (((n)<<1)|(l)) ++#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER) ++ ++/* ++ * The actual TLV types we support ++ */ ++ ++#define ENV_TLV_TYPE_END 0x00 ++#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS) ++ ++/* ++ * Environment variable flags ++ */ ++ ++#define ENV_FLG_NORMAL 0x00 /* normal read/write */ ++#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */ ++#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */ ++ ++#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */ ++#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */ ++ ++ ++/* ********************************************************************* ++ * _nvram_read(buffer,offset,length) ++ * ++ * Read data from the NVRAM device ++ * ++ * Input parameters: ++ * buffer - destination buffer ++ * offset - offset of data to read ++ * length - number of bytes to read ++ * ++ * Return value: ++ * number of bytes read, or <0 if error occured ++ ********************************************************************* */ ++static int ++_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length) ++{ ++ int i; ++ if (offset > NVRAM_SIZE) ++ return -1; ++ ++ for ( i = 0; i < length; i++) { ++ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i]; ++ } ++ return length; ++} ++ ++ ++static char* ++_strnchr(const char *dest,int c,size_t cnt) ++{ ++ while (*dest && (cnt > 0)) { ++ if (*dest == c) return (char *) dest; ++ dest++; ++ cnt--; ++ } ++ return NULL; ++} ++ ++ ++ ++/* ++ * Core support API: Externally visible. ++ */ ++ ++/* ++ * Get the value of an NVRAM variable ++ * @param name name of variable to get ++ * @return value of variable or NULL if undefined ++ */ ++ ++char *cfe_env_get(unsigned char *nv_buf, const char *name) ++{ ++ int size; ++ unsigned char *buffer; ++ unsigned char *ptr; ++ unsigned char *envval; ++ unsigned int reclen; ++ unsigned int rectype; ++ int offset; ++ int flg; ++ ++ if (!strcmp(name, "nvram_type")) ++ return "cfe"; ++ ++ size = NVRAM_SIZE; ++ buffer = &_nvdata[0]; ++ ++ ptr = buffer; ++ offset = 0; ++ ++ /* Read the record type and length */ ++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) { ++ goto error; ++ } ++ ++ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) { ++ ++ /* Adjust pointer for TLV type */ ++ rectype = *(ptr); ++ offset++; ++ size--; ++ ++ /* ++ * Read the length. It can be either 1 or 2 bytes ++ * depending on the code ++ */ ++ if (rectype & ENV_LENGTH_8BITS) { ++ /* Read the record type and length - 8 bits */ ++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) { ++ goto error; ++ } ++ reclen = *(ptr); ++ size--; ++ offset++; ++ } ++ else { ++ /* Read the record type and length - 16 bits, MSB first */ ++ if (_nvram_read(nv_buf, ptr,offset,2) != 2) { ++ goto error; ++ } ++ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1); ++ size -= 2; ++ offset += 2; ++ } ++ ++ if (reclen > size) ++ break; /* should not happen, bad NVRAM */ ++ ++ switch (rectype) { ++ case ENV_TLV_TYPE_ENV: ++ /* Read the TLV data */ ++ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen) ++ goto error; ++ flg = *ptr++; ++ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1)); ++ if (envval) { ++ *envval++ = '\0'; ++ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr)); ++ _valuestr[(reclen-1)-(envval-ptr)] = '\0'; ++#if 0 ++ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr); ++#endif ++ if(!strcmp(ptr, name)){ ++ return _valuestr; ++ } ++ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name)) ++ return _valuestr; ++ } ++ break; ++ ++ default: ++ /* Unknown TLV type, skip it. */ ++ break; ++ } ++ ++ /* ++ * Advance to next TLV ++ */ ++ ++ size -= (int)reclen; ++ offset += reclen; ++ ++ /* Read the next record type */ ++ ptr = buffer; ++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) ++ goto error; ++ } ++ ++error: ++ return NULL; ++ ++} ++ +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -37,6 +37,8 @@ struct nvram_header { + static char nvram_buf[NVRAM_SPACE]; + static size_t nvram_len; + static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000}; ++static int cfe_env; ++extern char *cfe_env_get(char *nv_buf, const char *name); + + static u32 find_nvram_size(void __iomem *end) + { +@@ -66,6 +68,26 @@ static int nvram_find_and_copy(void __io + return -EEXIST; + } + ++ cfe_env = 0; ++ ++ /* XXX: hack for supporting the CFE environment stuff on WGT634U */ ++ if (lim >= 8 * 1024 * 1024) { ++ src = (u32 *)(iobase + 8 * 1024 * 1024 - 0x2000); ++ dst = (u32 *)nvram_buf; ++ ++ if ((*src & 0xff00ff) == 0x000001) { ++ printk("early_nvram_init: WGT634U NVRAM found.\n"); ++ ++ for (i = 0; i < 0x1ff0; i++) { ++ if (*src == 0xFFFFFFFF) ++ break; ++ *dst++ = *src++; ++ } ++ cfe_env = 1; ++ return 0; ++ } ++ } ++ + /* TODO: when nvram is on nand flash check for bad blocks first. */ + off = FLASH_MIN; + while (off <= lim) { +@@ -180,6 +202,13 @@ int bcm47xx_nvram_getenv(const char *nam + if (!name) + return -EINVAL; + ++ if (cfe_env) { ++ value = cfe_env_get(nvram_buf, name); ++ if (!value) ++ return -ENOENT; ++ return snprintf(val, val_len, "%s", value); ++ } ++ + if (!nvram_len) { + err = nvram_init(); + if (err) diff --git a/target/linux/brcm47xx/patches-4.1/830-huawei_e970_support.patch b/target/linux/brcm47xx/patches-4.1/830-huawei_e970_support.patch new file mode 100644 index 0000000..fdb6c19 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/830-huawei_e970_support.patch @@ -0,0 +1,101 @@ +--- a/arch/mips/bcm47xx/setup.c ++++ b/arch/mips/bcm47xx/setup.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -245,6 +246,33 @@ static struct fixed_phy_status bcm47xx_f + .duplex = DUPLEX_FULL, + }; + ++static struct gpio_wdt_platform_data gpio_wdt_data; ++ ++static struct platform_device gpio_wdt_device = { ++ .name = "gpio-wdt", ++ .id = 0, ++ .dev = { ++ .platform_data = &gpio_wdt_data, ++ }, ++}; ++ ++static int __init bcm47xx_register_gpio_watchdog(void) ++{ ++ enum bcm47xx_board board = bcm47xx_board_get(); ++ ++ switch (board) { ++ case BCM47XX_BOARD_HUAWEI_E970: ++ pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n"); ++ gpio_wdt_data.gpio = 7; ++ gpio_wdt_data.interval = HZ; ++ gpio_wdt_data.first_interval = HZ / 5; ++ return platform_device_register(&gpio_wdt_device); ++ default: ++ /* Nothing to do */ ++ return 0; ++ } ++} ++ + static int __init bcm47xx_register_bus_complete(void) + { + switch (bcm47xx_bus_type) { +@@ -264,6 +292,7 @@ static int __init bcm47xx_register_bus_c + bcm47xx_workarounds(); + + fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status); ++ bcm47xx_register_gpio_watchdog(); + return 0; + } + device_initcall(bcm47xx_register_bus_complete); +--- a/arch/mips/configs/bcm47xx_defconfig ++++ b/arch/mips/configs/bcm47xx_defconfig +@@ -67,6 +67,7 @@ CONFIG_HW_RANDOM=y + CONFIG_GPIO_SYSFS=y + CONFIG_WATCHDOG=y + CONFIG_BCM47XX_WDT=y ++CONFIG_GPIO_WDT=y + CONFIG_SSB_DEBUG=y + CONFIG_SSB_DRIVER_GIGE=y + CONFIG_BCMA_DRIVER_GMAC_CMN=y +--- a/drivers/ssb/embedded.c ++++ b/drivers/ssb/embedded.c +@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu + } + EXPORT_SYMBOL(ssb_watchdog_timer_set); + ++#ifdef CONFIG_BCM47XX ++#include ++ ++static bool ssb_watchdog_supported(void) ++{ ++ enum bcm47xx_board board = bcm47xx_board_get(); ++ ++ /* The Huawei E970 has a hardware watchdog using a GPIO */ ++ switch (board) { ++ case BCM47XX_BOARD_HUAWEI_E970: ++ return false; ++ default: ++ return true; ++ } ++} ++#else ++static bool ssb_watchdog_supported(void) ++{ ++ return true; ++} ++#endif ++ + int ssb_watchdog_register(struct ssb_bus *bus) + { + struct bcm47xx_wdt wdt = {}; + struct platform_device *pdev; + ++ if (!ssb_watchdog_supported()) ++ return 0; ++ + if (ssb_chipco_available(&bus->chipco)) { + wdt.driver_data = &bus->chipco; + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt; diff --git a/target/linux/brcm47xx/patches-4.1/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch b/target/linux/brcm47xx/patches-4.1/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch new file mode 100644 index 0000000..d7d2d7e --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch @@ -0,0 +1,30 @@ +From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 8 Apr 2015 06:58:11 +0200 +Subject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +If SoC has a CardBus we can set resources of device at slot 1 only. It's +impossigle to set bridge resources as it simply overwrites device 1 +configuration and usually results in Data bus error-s. + +Signed-off-by: RafaÅ‚ MiÅ‚ecki +--- + drivers/ssb/driver_pcicore.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -164,6 +164,10 @@ static int ssb_extpci_write_config(struc + SSB_WARN_ON(!pc->hostmode); + if (unlikely(len != 1 && len != 2 && len != 4)) + goto out; ++ /* CardBus SoCs allow configuring dev 1 resources only */ ++ if (extpci_core->cardbusmode && dev != 1 && ++ off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5) ++ goto out; + addr = get_cfgspace_addr(pc, bus, dev, func, off); + if (unlikely(!addr)) + goto out; diff --git a/target/linux/brcm47xx/patches-4.1/920-cache-wround.patch b/target/linux/brcm47xx/patches-4.1/920-cache-wround.patch new file mode 100644 index 0000000..e26d98a --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/920-cache-wround.patch @@ -0,0 +1,138 @@ +--- a/arch/mips/include/asm/r4kcache.h ++++ b/arch/mips/include/asm/r4kcache.h +@@ -28,10 +28,28 @@ extern void (*r4k_blast_icache)(void); + #ifdef CONFIG_BCM47XX + #include + #include +-#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE))) ++#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg() ++ ++static inline unsigned long bcm4710_dummy_rreg(void) ++{ ++ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE)); ++} ++ ++#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr)) ++ ++static inline unsigned long bcm4710_fill_tlb(void *addr) ++{ ++ return *(unsigned long *)addr; ++} ++ ++#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr)) ++ ++static inline void bcm4710_protected_fill_tlb(void *addr) ++{ ++ unsigned long x; ++ get_dbe(x, (unsigned long *)addr);; ++} + +-#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr)) +-#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); }) + #else + #define BCM4710_DUMMY_RREG() + +--- a/arch/mips/mm/tlbex.c ++++ b/arch/mips/mm/tlbex.c +@@ -936,6 +936,9 @@ build_get_pgde32(u32 **p, unsigned int t + uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); + uasm_i_addu(p, ptr, tmp, ptr); + #else ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(p); ++#endif + UASM_i_LA_mostly(p, ptr, pgdc); + #endif + uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ +@@ -1296,12 +1299,12 @@ static void build_r4000_tlb_refill_handl + /* No need for uasm_i_nop */ + } + +-#ifdef CONFIG_BCM47XX +- uasm_i_nop(&p); +-#endif + #ifdef CONFIG_64BIT + build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ + #else ++# ifdef CONFIG_BCM47XX ++ uasm_i_nop(&p); ++# endif + build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ + #endif + +@@ -1313,6 +1316,9 @@ static void build_r4000_tlb_refill_handl + build_update_entries(&p, K0, K1); + build_tlb_write_entry(&p, &l, &r, tlb_random); + uasm_l_leave(&l, p); ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(&p); ++#endif + uasm_i_eret(&p); /* return from trap */ + } + #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT +@@ -1871,12 +1877,12 @@ build_r4000_tlbchange_handler_head(u32 * + { + struct work_registers wr = build_get_work_registers(p); + +-#ifdef CONFIG_BCM47XX +- uasm_i_nop(p); +-#endif + #ifdef CONFIG_64BIT + build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ + #else ++# ifdef CONFIG_BCM47XX ++ uasm_i_nop(p); ++# endif + build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ + #endif + +@@ -1923,6 +1929,9 @@ build_r4000_tlbchange_handler_tail(u32 * + build_tlb_write_entry(p, l, r, tlb_indexed); + uasm_l_leave(l, *p); + build_restore_work_registers(p); ++#ifdef CONFIG_BCM47XX ++ uasm_i_nop(p); ++#endif + uasm_i_eret(p); /* return from trap */ + + #ifdef CONFIG_64BIT +--- a/arch/mips/kernel/genex.S ++++ b/arch/mips/kernel/genex.S +@@ -21,6 +21,19 @@ + #include + #include + ++#ifdef CONFIG_BCM47XX ++# ifdef eret ++# undef eret ++# endif ++# define eret \ ++ .set push; \ ++ .set noreorder; \ ++ nop; \ ++ nop; \ ++ eret; \ ++ .set pop; ++#endif ++ + __INIT + + /* +@@ -34,7 +47,6 @@ NESTED(except_vec3_generic, 0, sp) + .set noat + #ifdef CONFIG_BCM47XX + nop +- nop + #endif + #if R5432_CP0_INTERRUPT_WAR + mfc0 k0, CP0_INDEX +@@ -59,6 +71,9 @@ NESTED(except_vec3_r4000, 0, sp) + .set push + .set arch=r4000 + .set noat ++#ifdef CONFIG_BCM47XX ++ nop ++#endif + mfc0 k1, CP0_CAUSE + li k0, 31<<2 + andi k1, k1, 0x7c diff --git a/target/linux/brcm47xx/patches-4.1/940-bcm47xx-yenta.patch b/target/linux/brcm47xx/patches-4.1/940-bcm47xx-yenta.patch new file mode 100644 index 0000000..77c10fc --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/940-bcm47xx-yenta.patch @@ -0,0 +1,46 @@ +--- a/drivers/pcmcia/yenta_socket.c ++++ b/drivers/pcmcia/yenta_socket.c +@@ -920,6 +920,8 @@ static unsigned int yenta_probe_irq(stru + * Probe for usable interrupts using the force + * register to generate bogus card status events. + */ ++#ifndef CONFIG_BCM47XX ++ /* WRT54G3G does not like this */ + cb_writel(socket, CB_SOCKET_EVENT, -1); + cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK); + reg = exca_readb(socket, I365_CSCINT); +@@ -935,6 +937,7 @@ static unsigned int yenta_probe_irq(stru + } + cb_writel(socket, CB_SOCKET_MASK, 0); + exca_writeb(socket, I365_CSCINT, reg); ++#endif + + mask = probe_irq_mask(val) & 0xffff; + +@@ -1019,6 +1022,10 @@ static void yenta_get_socket_capabilitie + else + socket->socket.irq_mask = 0; + ++ /* irq mask probing is broken for the WRT54G3G */ ++ if (socket->socket.irq_mask == 0) ++ socket->socket.irq_mask = 0x6f8; ++ + dev_printk(KERN_INFO, &socket->dev->dev, + "ISA IRQ mask 0x%04x, PCI irq %d\n", + socket->socket.irq_mask, socket->cb_irq); +@@ -1255,6 +1262,15 @@ static int yenta_probe(struct pci_dev *d + dev_printk(KERN_INFO, &dev->dev, + "Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE)); + ++ /* Generate an interrupt on card insert/remove */ ++ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK); ++ ++ /* Set up Multifunction Routing Status Register */ ++ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */); ++ ++ /* Switch interrupts to parallelized */ ++ config_writeb(socket, 0x92, 0x64); ++ + yenta_fixup_parent_bridge(dev->subordinate); + + /* Register it with the pcmcia layer.. */ diff --git a/target/linux/brcm47xx/patches-4.1/976-ssb_increase_pci_delay.patch b/target/linux/brcm47xx/patches-4.1/976-ssb_increase_pci_delay.patch new file mode 100644 index 0000000..90bda51 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/976-ssb_increase_pci_delay.patch @@ -0,0 +1,11 @@ +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -389,7 +389,7 @@ static void ssb_pcicore_init_hostmode(st + set_io_port_base(ssb_pcicore_controller.io_map_base); + /* Give some time to the PCI controller to configure itself with the new + * values. Not waiting at this point causes crashes of the machine. */ +- mdelay(10); ++ mdelay(300); + register_pci_controller(&ssb_pcicore_controller); + } + diff --git a/target/linux/brcm47xx/patches-4.1/999-wl_exports.patch b/target/linux/brcm47xx/patches-4.1/999-wl_exports.patch new file mode 100644 index 0000000..be14a09 --- /dev/null +++ b/target/linux/brcm47xx/patches-4.1/999-wl_exports.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/bcm47xx/nvram.c ++++ b/arch/mips/bcm47xx/nvram.c +@@ -34,7 +34,8 @@ struct nvram_header { + u32 config_ncdl; /* ncdl values for memc */ + }; + +-static char nvram_buf[NVRAM_SPACE]; ++char nvram_buf[NVRAM_SPACE]; ++EXPORT_SYMBOL(nvram_buf); + static size_t nvram_len; + static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000}; + static int cfe_env; +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -59,6 +59,7 @@ void (*_dma_cache_wback)(unsigned long s + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + + EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_inv); + + #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ + diff --git a/target/linux/brcm63xx/Makefile b/target/linux/brcm63xx/Makefile new file mode 100644 index 0000000..f96897c --- /dev/null +++ b/target/linux/brcm63xx/Makefile @@ -0,0 +1,27 @@ +# +# Copyright (C) 2006-2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips +BOARD:=brcm63xx +BOARDNAME:=Broadcom BCM63xx +SUBTARGETS:=generic smp +FEATURES:=squashfs usb atm pci pcmcia usbgadget +KERNEL_PATCHVER:=4.1 +MAINTAINER:=Jonas Gorski + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += swconfig kmod-gpio-button-hotplug + +define Target/Description + Build firmware images for Broadcom based xDSL/routers + currently supports BCM6338, BCM6348 and BCM6358 based devices. + (e.g. Inventel Livebox, Siemens SE515, Neufbox 4) +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/brcm63xx/base-files.mk b/target/linux/brcm63xx/base-files.mk new file mode 100644 index 0000000..d6682bd --- /dev/null +++ b/target/linux/brcm63xx/base-files.mk @@ -0,0 +1,5 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef + + diff --git a/target/linux/brcm63xx/base-files/etc/diag.sh b/target/linux/brcm63xx/base-files/etc/diag.sh new file mode 100644 index 0000000..7826fad --- /dev/null +++ b/target/linux/brcm63xx/base-files/etc/diag.sh @@ -0,0 +1,137 @@ +#!/bin/sh +# Copyright (C) 2007-2013 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/brcm63xx.sh + +set_state() { + case "$(brcm63xx_board_name)" in + a4001n1) + status_led="A4001N1:green:power" + ;; + a4001n) + status_led="A4001N:green:power" + ;; + ar-5381u) + status_led="AR-5381u:green:power" + ;; + ar-5387un) + status_led="AR-5387un:green:power" + ;; + bcm96348gw) + status_led="96348GW:green:power" + ;; + bcm963281tan) + status_led="963281TAN::power" + ;; + bcm96328avng) + status_led="96328avng::power" + ;; + bcm96348gw-11) + status_led="96348GW-11:green:power" + ;; + spw303v) + status_led="spw303v:green:power+adsl" + ;; + vr-3025un) + status_led="VR-3025un:green:power" + ;; + vr-3025u) + status_led="VR-3025u:green:power" + ;; + vr-3026e) + status_led="VR-3026e:green:power" + ;; + wap-5813n) + status_led="WAP-5813n:green:power" + ;; + ar1004g) + status_led="AR1004G:green:power" + ;; + dsl-274xb-c|\ + dsl-274xb-f) + status_led="dsl-274xb:green:power" + ;; + dsl-275xb-d) + status_led="dsl-275xb:green:power" + ;; + cpva642) + status_led="CPVA642:green:power:" + ;; + ct536_ct5621) + status_led="CT536_CT5621:green:power" + ;; + cvg834g) + status_led="CVG834G:green:power" + ;; + dsl-2640b-b) + status_led="D-4P-W:green:power" + ;; + dgnd3700v1_dgnd3800b) + status_led="DGND3700v1_3800B:green:power" + ;; + fast2504n) + status_led="fast2504n:green:ok" + ;; + fast2704n) + status_led2="F@ST2704N:red:power" + ;; + fast2704v2) + status_led="F@ST2704V2:green:power" + ;; + homehub2a) + status_led="HOMEHUB2A:green:upgrading" + status_led2="HOMEHUB2A:blue:upgrading" + ;; + gw6200) + status_led="GW6200:green:line1" + status_led2="GW6200:green:tel" + ;; + hg553) + status_led="HW553:blue:power" + ;; + hg556a_*) + status_led="HW556:red:power" + ;; + hg520) + status_led="HW520:green:net" + ;; + hg655b) + status_led="HW65x:green:power" + ;; + p870hw-51a_v2) + status_led="P870HW-51a:green:power" + ;; + rta770bw) + status_led="RTA770BW:green:diag" + ;; + rta770w) + status_led="RTA770W:green:diag" + ;; + spw500v) + status_led="SPW500V:green:power" + ;; + v2110) + status_led="V2110:power:green" + ;; + esac + + case "$1" in + preinit) + status_led_set_timer 200 200 + ;; + failsafe) + status_led_set_timer 50 50 + ;; + preinit_regular) + status_led_set_timer 500 500 + ;; + done) + if [ "${status_led/power}" != "$status_led" ]; then + status_led_on + else + status_led_off + fi + ;; + esac +} diff --git a/target/linux/brcm63xx/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom b/target/linux/brcm63xx/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom new file mode 100644 index 0000000..4347485 --- /dev/null +++ b/target/linux/brcm63xx/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom @@ -0,0 +1,45 @@ +#!/bin/sh +# Based on gabors ralink wisoc implementation. + +rt2x00_eeprom_die() { + echo "rt2x00 eeprom: " "$*" + exit 1 +} + +rt2x00_eeprom_extract() { + local part=$1 + local offset=$2 + local count=$3 + local mtd + + . /lib/functions.sh + + mtd=$(find_mtd_part $part) + [ -n "$mtd" ] || \ + rt2x00_eeprom_die "no mtd device found for partition $part" + + dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count || \ + rt2x00_eeprom_die "failed to extract from $mtd" +} + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/brcm63xx.sh + +board=$(brcm63xx_board_name) + +case "$FIRMWARE" in +"rt2x00.eeprom" ) + case $board in + hg556a_c) + rt2x00_eeprom_extract "cal_data" 130560 512 + ;; + hg655b) + rt2x00_eeprom_extract "cal_data" 0 512 + ;; + *) + rt2x00_eeprom_die "board $board is not supported yet" + ;; + esac + ;; +esac diff --git a/target/linux/brcm63xx/base-files/etc/uci-defaults/01_leds b/target/linux/brcm63xx/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..bdb3dad --- /dev/null +++ b/target/linux/brcm63xx/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,53 @@ +#!/bin/sh +# +# Copyright (C) 2013-2014 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/brcm63xx.sh + +case "$(brcm63xx_board_name)" in +a4001n1) + ucidef_set_led_netdev "lan" "LAN" "A4001N1:green:eth" "eth0" + ucidef_set_led_usbdev "usb" "USB" "A4001N1:green:3g" "1-1" + ;; +a4001n) + ucidef_set_led_usbdev "usb" "USB" "A4001N:green:usb" "1-1" + ;; +dgnd3700v1_dgnd3800b) + ucidef_set_led_netdev "lan" "LAN" "DGND3700v1_3800B:green:lan" "eth0.1" + ucidef_set_led_netdev "wan" "WAN" "DGND3700v1_3800B:green:inet" "eth0.2" + ucidef_set_led_netdev "wlan0" "WIFI2G" "DGND3700v1_3800B:green:wifi2g" "wlan0" + ucidef_set_led_netdev "wlan1" "WIFI5G" "DGND3700v1_3800B:blue:wifi5g" "wlan1" + ucidef_set_led_usbdev "usb1" "USB1" "DGND3700v1_3800B:green:usb-back" "1-1" + ucidef_set_led_usbdev "usb2" "USB2" "DGND3700v1_3800B:green:usb-front" "1-2" + ;; +fast2704n) + ucidef_set_led_netdev "wan" "WAN" "F@ST2704N:green:inet" "eth0.2" + ;; +fast2704v2) + ucidef_set_led_usbdev "usb" "USB" "F@ST2704V2:green:usb" "1-1" + ;; +hg553) + ucidef_set_led_netdev "lan" "LAN" "HW553:blue:lan" "eth0" + ucidef_set_led_usbdev "usb1" "USB1" "HW553:red:hspa" "1-1" + ucidef_set_led_usbdev "usb2" "USB2" "HW553:blue:hspa" "1-2" + ;; +hg556a_*) + ucidef_set_led_netdev "lan" "LAN" "HW556:red:dsl" "eth0" + ucidef_set_led_usbdev "usb" "USB" "HW556:red:hspa" "1-2" + ;; +hg655b) + ucidef_set_led_usbdev "usb" "USB" "HW65x:green:usb" "1-2" + ;; +homehub2a) + ucidef_set_led_netdev "lan" "LAN" "HOMEHUB2A:blue:broadband" "eth0.1" + ucidef_set_led_netdev "wlan0" "WIFI" "HOMEHUB2A:green:wireless" "wlan0" + ucidef_set_led_usbdev "usb1" "USB1" "HOMEHUB2A:blue:phone" "1-1" + ucidef_set_led_usbdev "usb2" "USB2" "HOMEHUB2A:green:phone" "2-1" + ;; +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/brcm63xx/base-files/etc/uci-defaults/02_network b/target/linux/brcm63xx/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..129514b --- /dev/null +++ b/target/linux/brcm63xx/base-files/etc/uci-defaults/02_network @@ -0,0 +1,154 @@ +#!/bin/sh +# +# Copyright (C) 2012 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/brcm63xx.sh + +ucidef_set_interface_loopback + +case "$(brcm63xx_board_name)" in + +cvg834g |\ +rta770bw |\ +rta770w |\ +spw303v |\ +spw500v) + ucidef_set_interface_lan "eth0" + ;; + +ar1004g |\ +bcm96338gw |\ +bcm96338w |\ +cpva642 |\ +ct-5365 |\ +ct-536p_5621t |\ +ct-6373 |\ +dg834g_v4 |\ +dsl-2640b-b |\ +dsl-2640u |\ +fast2604 |\ +rta1320 |\ +v2110) + ucidef_set_interface_lan "eth0" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0 1 2 3 4 5" + ;; + +agpf-s0 |\ +bcm96348gw |\ +bcm96348gw-10 |\ +bcm96348gw-11 |\ +bcm96358vw |\ +bcm96358vw2 |\ +cpva502p |\ +dg834gt |\ +dmv-s0 |\ +dsl-2650u |\ +dv-201amr |\ +f5d7633 |\ +fast2404 |\ +magic |\ +rg100a |\ +rta1025W |\ +td-w8900gb |\ +usr9108 |\ +v2500v_bb) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "eth1" "1" "1" + ucidef_add_switch_vlan "eth1" "1" "0 1 2 3 4 5" + ;; + +dsl-274xb-c |\ +hg553 |\ +hg556a_* |\ +homehub2a) + ucidef_set_interface_lan "eth0.1" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0 1 2 3 4 5t" + ;; + +dva-g3810bn |\ +hg520 |\ +neufbox4) + ucidef_set_interfaces_lan_wan "eth1.1" "eth0" + ucidef_add_switch "eth1" "1" "1" + ucidef_add_switch_vlan "eth1" "1" "0 1 2 3 4 5t" + ;; + +a4001n1 |\ +a4001n |\ +ar-5381u |\ +ar-5387un |\ +bcm963281tan |\ +bcm96328avng |\ +bcm96368mvngr |\ +dsl-274xb-f |\ +dsl-275xb-d |\ +fast2504n |\ +fast2704v2 |\ +hg655b |\ +p870hw-51a_v2 |\ +vr-3025un |\ +vr-3025u |\ +vr-3026e) + ucidef_set_interface_lan "eth0.1" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0 1 2 3 8t" + ;; + +bcm96368mvwg) + ucidef_set_interface_lan "eth0.1" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "1 2 4 5 8t" + ;; + +wap-5813n) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "0 1 2 3 5t" + ucidef_add_switch_vlan "eth0" "2" "4 5t" + ;; + +fast2704n |\ +dgnd3700v1_dgnd3800b) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "eth0" "1" "1" + ucidef_add_switch_vlan "eth0" "1" "1 2 3 4 8t" + ucidef_add_switch_vlan "eth0" "2" "0 8t" + ;; + +neufbox6) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "1 2 3 4 9t" + ucidef_add_switch_vlan "switch0" "2" "0 9t" + ;; + +vg50) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 8t" + ucidef_add_switch_vlan "switch0" "2" "4 8t" + ;; + +bcm963268bu_p300) + ucidef_set_interface_lan "eth0.1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 3 4 5 6 7 8t" + ;; + +*) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; + +esac + +uci commit network + +exit 0 diff --git a/target/linux/brcm63xx/base-files/etc/uci-defaults/09_fix_crc b/target/linux/brcm63xx/base-files/etc/uci-defaults/09_fix_crc new file mode 100644 index 0000000..f307a4c --- /dev/null +++ b/target/linux/brcm63xx/base-files/etc/uci-defaults/09_fix_crc @@ -0,0 +1,38 @@ +#!/bin/sh +# +# Copyright (C) 2007 OpenWrt.org +# +# + +. /lib/brcm63xx.sh + +do_fixcrc() { + mtd fixtrx linux +} + +case "$(brcm63xx_board_name)" in + a4001n |\ + a4001n1 |\ + ar-5381u |\ + ar-5387un |\ + bcm96328avng |\ + bcm963281tan |\ + cpva502p |\ + cpva642 |\ + ct-6373 |\ + dsl-274xb-f |\ + magic |\ + p870hw-51a_v2 |\ + rta770bw |\ + rta770w |\ + spw303v |\ + v2110 |\ + v2500v_bb |\ + vr-3025u |\ + vr-3025un |\ + vr-3026e |\ + wap-5813n) + do_fixcrc + ;; +esac + diff --git a/target/linux/brcm63xx/base-files/lib/brcm63xx.sh b/target/linux/brcm63xx/base-files/lib/brcm63xx.sh new file mode 100755 index 0000000..1a97c86 --- /dev/null +++ b/target/linux/brcm63xx/base-files/lib/brcm63xx.sh @@ -0,0 +1,292 @@ +#!/bin/sh +# +# Copyright (C) 2007 OpenWrt.org +# +# + +board_id="" +sys_mtd_part="" +ifname="" + +brcm63xx_dt_detect() { + local board_name + + case "$1" in + "ADB P.DG A4001N") + board_name="a4001n" + ;; + "ADB P.DG A4001N1") + board_name="a4001n1" + ;; + "Alcatel RG100A") + board_name="rg100a" + ;; + "ASMAX AR 1004g") + board_name="ar100g" + ;; + "Belkin F5D7633") + board_name="f5d7633" + ;; + "Broadcom 96348R reference board") + board_name="bcm96348r" + ;; + "Broadcom BCM96318REF reference board") + board_name="bcm96318ref" + ;; + "Broadcom BCM96318REF_P300 reference board") + board_name="bcm96318ref_p300" + ;; + "Broadcom BCM963268BU_P300 reference board") + board_name="bcm963268bu_p300" + ;; + "Broadcom BCM963269BHR reference board") + board_name="bcm963269bhr" + ;; + "Broadcom bcm963281TAN reference board") + board_name="bcm963281tan" + ;; + "Broadcom BCM96328avng reference board") + board_name="bcm96328avng" + ;; + "Broadcom BCM96345GW2 reference board") + board_name="bcm96345gw2" + ;; + "Broadcom BCM96348GW-10 reference board") + board_name="bcm96348gw-10" + ;; + "Broadcom BCM96348GW-11 reference board") + board_name="bcm96348gw-11" + ;; + "Broadcom BCM96348GW reference board") + board_name="bcm96358gw" + ;; + "Broadcom BCM96358VW reference board") + board_name="bcm96358vw" + ;; + "Broadcom BCM96358VW2 reference board") + board_name="bcm96358vw2" + ;; + "Broadcom BCM96368MVNgr reference board") + board_name="bcm96368mvngr" + ;; + "Broadcom BCM96368MVWG reference board") + board_name="bcm96368mvwg" + ;; + "BT Home Hub 2.0 Type A") + board_name="homehub2a" + ;; + "BT Voyager 2110") + board_name="v2110" + ;; + "BT Voyager V2500V") + board_name="v2500v_bb" + ;; + "Comtrend AR-5381u") + board_name="ar-5381u" + ;; + "Comtrend AR-5387un") + board_name="ar-5387un" + ;; + "Comtrend CT-5365") + board_name="ct-5365" + ;; + "Comtrend CT-536+/CT-5621T") + board_name="ct-536p_5621t" + ;; + "Comtrend CT-6373") + board_name="ct-6373" + ;; + "Comtrend VR-3025u") + board_name="vr-3025u" + ;; + "Comtrend VR-3025un") + board_name="vr-3025un" + ;; + "Comtrend VR-3026e") + board_name="vr-3026e" + ;; + "Comtrend WAP-5813n") + board_name="wap-5813n" + ;; + "Davolink DV-201AMR") + board_name="dv-201amr" + ;; + "D-Link DSL-2640B rev B2") + board_name="dsl-2640b-b" + ;; + "D-Link DSL-2640U/BRU/C") + board_name="dsl-2640u" + ;; + "D-Link DSL-2650U") + board_name="dsl-2650u" + ;; + "D-Link DSL-2740B/DSL-2741B rev C2/3") + board_name="dsl-274xb-c" + ;; + "D-Link DSL-2740B/DSL-2741B rev F1") + board_name="dsl-274xb-f" + ;; + "D-Link DSL-2750B/DSL-2751 rev D1") + board_name="dsl-275xb-d" + ;; + "D-Link DVA-G3810BN/TL") + board_name="dva-g3810bn" + ;; + "Dynalink RTA770BW") + board_name="rta770bw" + ;; + "Dynalink RTA770W") + board_name="rta770w" + ;; + "Dynalink RTA1025W") + board_name="rta1025w" + ;; + "Dynalink RTA1320") + board_name="rta1320" + ;; + "Huawei EchoLife HG520v") + board_name="hg520v" + ;; + "Huawei EchoLife HG553") + board_name="hg553" + ;; + "Huawei EchoLife HG556a (version A)") + board_name="hg556a_a" + ;; + "Huawei EchoLife HG556a (version B)") + board_name="hg556a_b" + ;; + "Huawei EchoLife HG556a (version C)") + board_name="hg556a_c" + ;; + "Huawei HG655b") + board_name="hg655b" + ;; + "Inteno VG50") + board_name="vg50" + ;; + "Inventel Livebox 1") + board_name="livebox1" + ;; + "Netgear CVG834G") + board_name="cvg834g" + ;; + "Netgear DG834GT/PN") + board_name="dg834gt" + ;; + "Netgear DG834G v4") + board_name="dg834g_v4" + ;; + "Netgear DGND3700v1/DGND3800B") + board_name="dgnd3700v1_dgnd3800b" + ;; + "Pirelli A226G") + board_name="a226g" + ;; + "Pirelli A226M") + board_name="a226m" + ;; + "Pirelli A226M-FWB") + board_name="a226m-fwb" + ;; + "Pirelli Alice Gate AGPF-S0") + board_name="agpf-s0" + ;; + "Sagem F@ST2404") + board_name="fast2404" + ;; + "Sagem F@ST2504n") + board_name="fast2504n" + ;; + "Sagem F@ST2604") + board_name="fast2604" + ;; + "Sagem F@ST2704N") + board_name="fast2704n" + ;; + "Sagem F@ST2704V2") + board_name="fast2704v2" + ;; + "SFR Neuf Box 4"*) + board_name="neufbox4" + ;; + "SFR neufbox 6 (Sercomm)") + board_name="neufbox6" + ;; + "T-Com Speedport W303 V") + board_name="spw303v" + ;; + "T-Com Speedport W500 V") + board_name="spw500v" + ;; + "TECOM GW6000") + board_name="g6000" + ;; + "TECOM GW6200") + board_name="g6200" + ;; + "Telsey CVPA502+") + board_name="cpva502p" + ;; + "Telsey CPVA642-type (CPA-ZNTE60T)") + board_name="cpva642" + ;; + "Telsey MAGIC") + board_name="magic" + ;; + "TP-Link TD-W8900GB") + board_name="td-w8900gb" + ;; + "USRobotics 9108") + board_name="usr9108" + ;; + "Zyxel P870HW-51a v2") + board_name="p870hw-51a_v2" + ;; + *) + board_name="unknown" + ;; + esac + + echo "$board_name" +} + +brcm63xx_legacy_detect() { + local board_name + + case "$1" in + *) + board_name="unknown" + ;; + esac + + echo "$board_name" +} + +brcm63xx_detect() { + local board_name model + + board_id=$(awk 'BEGIN{FS="[ \t:/]+"} /system type/ {print $4}' /proc/cpuinfo) + + if [ -e /proc/device-tree ]; then + model=$(cat /proc/device-tree/model) + board_name=$(brcm63xx_dt_detect "$model") + else + model="Unknown bcm63xx board" + board_name=$(brcm63xx_legacy_detect "$board_id") + fi + + [ -e "/tmp/sysinfo" ] || mkdir -p "/tmp/sysinfo" + + echo "$board_name" > /tmp/sysinfo/board_name + echo "$model" > /tmp/sysinfo/model +} + +brcm63xx_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -n "$name" ] || name="unknown" + + echo $name +} diff --git a/target/linux/brcm63xx/base-files/lib/preinit/03_do_brcm63xx.sh b/target/linux/brcm63xx/base-files/lib/preinit/03_do_brcm63xx.sh new file mode 100644 index 0000000..4179695 --- /dev/null +++ b/target/linux/brcm63xx/base-files/lib/preinit/03_do_brcm63xx.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_brcm63xx() { + . /lib/brcm63xx.sh + + brcm63xx_detect +} + +boot_hook_add preinit_main do_brcm63xx diff --git a/target/linux/brcm63xx/base-files/lib/preinit/05_failsafe_config_switch_brcm63xx b/target/linux/brcm63xx/base-files/lib/preinit/05_failsafe_config_switch_brcm63xx new file mode 100644 index 0000000..e1653e3 --- /dev/null +++ b/target/linux/brcm63xx/base-files/lib/preinit/05_failsafe_config_switch_brcm63xx @@ -0,0 +1,10 @@ +#!/bin/sh + +failsafe_ip() { + [ -n "$pi_ifname" ] && grep -q "$pi_ifname" /proc/net/dev && { + ifconfig $pi_ifname $pi_ip netmask $pi_netmask broadcast $pi_broadcast up + } +} + +boot_hook_add failsafe failsafe_ip + diff --git a/target/linux/brcm63xx/base-files/lib/preinit/05_init_interfaces_brcm63xx b/target/linux/brcm63xx/base-files/lib/preinit/05_init_interfaces_brcm63xx new file mode 100644 index 0000000..abf5b89 --- /dev/null +++ b/target/linux/brcm63xx/base-files/lib/preinit/05_init_interfaces_brcm63xx @@ -0,0 +1,48 @@ +#!/bin/sh + +. /lib/brcm63xx.sh + +set_preinit_iface() { + case "$(brcm63xx_board_name)" in + a4001n |\ + a4001n1 |\ + ar-5381u |\ + ar-5387un |\ + bcm963281tan |\ + bcm96328avng |\ + cpva642 |\ + ct536_ct5621 |\ + cvg834g |\ + dgnd3700v1_dgnd3800b |\ + dsl-2640b-b |\ + dsl-274xb-c |\ + dsl-274xb-f |\ + dsl-275xb-d |\ + fast2504n |\ + fast2704v2 |\ + hg553 |\ + hg556a_* |\ + hg520 |\ + neufbox6 |\ + p870hw-51a_v2 |\ + rta770bw |\ + rta770w |\ + spw303v |\ + spw500v |\ + v2110 |\ + vr-3025un |\ + vr-3025u |\ + vr-3026e |\ + wap-5813n) + ifname=eth0 + ;; + bcm96348gw |\ + bcm96348gw-11 |\ + gw6000 |\ + gw6200) + ifname=eth1 + ;; + esac +} + +boot_hook_add preinit_main set_preinit_iface diff --git a/target/linux/brcm63xx/base-files/lib/preinit/15_set_preinit_interface_brcm63xx b/target/linux/brcm63xx/base-files/lib/preinit/15_set_preinit_interface_brcm63xx new file mode 100644 index 0000000..7655fb7 --- /dev/null +++ b/target/linux/brcm63xx/base-files/lib/preinit/15_set_preinit_interface_brcm63xx @@ -0,0 +1,27 @@ +#!/bin/sh + +port_net_echo() { + [ -n "$pi_ifname" ] && grep -q "$pi_ifname" /proc/net/dev && { + if [ "$pi_preinit_net_messages" = "y" ] || [ "$pi_failsafe_net_message" = "true" ] && [ "$pi_preinit_no_failsafe_netmsg" != "y" ]; then + netmsg $pi_broadcast "$1" + fi + } +} + +preinit_ip_deconfig() { + if [ -z "$pi_ifname" ]; then + ifconfig $ifname 0.0.0.0 down + else + grep -q "$pi_ifname" /proc/net/dev && { + ifconfig $pi_ifname 0.0.0.0 down + } + fi +} + +preinit_net_echo() { + preinit_ip + + port_net_echo $1 +} + + diff --git a/target/linux/brcm63xx/base-files/lib/preinit/20_failsafe_net_echo_brcm63xx b/target/linux/brcm63xx/base-files/lib/preinit/20_failsafe_net_echo_brcm63xx new file mode 100644 index 0000000..f030cb2 --- /dev/null +++ b/target/linux/brcm63xx/base-files/lib/preinit/20_failsafe_net_echo_brcm63xx @@ -0,0 +1,12 @@ +#!/bin/sh + +indicate_failsafe() { + preinit_net_echo() { + port_net_echo $1 + } + echo "- failsafe -" + preinit_net_echo "Entering Failsafe!\n" + indicate_failsafe_led +} + + diff --git a/target/linux/brcm63xx/base-files/lib/upgrade/platform.sh b/target/linux/brcm63xx/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..5c9e2c2 --- /dev/null +++ b/target/linux/brcm63xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,16 @@ +PART_NAME=linux +platform_check_image() { + [ "$#" -gt 1 ] && return 1 + case "$(get_magic_word "$1")" in + 3600|3700|3800) + # 6348GW-11 boards use openwrt-96348GW-11-squashfs-cfe.bin files + return 0 + ;; + *) + echo "Invalid image type. Please use only .bin files" + return 1 + ;; + esac +} + +# use default for platform_do_upgrade() diff --git a/target/linux/brcm63xx/config-3.18 b/target/linux/brcm63xx/config-3.18 new file mode 100644 index 0000000..b72080b --- /dev/null +++ b/target/linux/brcm63xx/config-3.18 @@ -0,0 +1,229 @@ +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_B53=y +CONFIG_B53_MMAP_DRIVER=y +CONFIG_B53_PHY_DRIVER=y +CONFIG_B53_PHY_FIXUP=y +CONFIG_B53_SPI_DRIVER=y +# CONFIG_B53_SRAB_DRIVER is not set +CONFIG_BCM6345_EXT_IRQ=y +CONFIG_BCM6345_PERIPH_IRQ=y +CONFIG_BCM63XX=y +CONFIG_BCM63XX_CPU_3368=y +CONFIG_BCM63XX_CPU_6318=y +CONFIG_BCM63XX_CPU_63268=y +CONFIG_BCM63XX_CPU_6328=y +CONFIG_BCM63XX_CPU_6338=y +CONFIG_BCM63XX_CPU_6345=y +CONFIG_BCM63XX_CPU_6348=y +CONFIG_BCM63XX_CPU_6358=y +CONFIG_BCM63XX_CPU_6362=y +CONFIG_BCM63XX_CPU_6368=y +CONFIG_BCM63XX_EHCI=y +CONFIG_BCM63XX_ENET=y +CONFIG_BCM63XX_OHCI=y +CONFIG_BCM63XX_PHY=y +CONFIG_BCM63XX_WDT=y +CONFIG_BCMA=y +CONFIG_BCMA_BLOCKIO=y +# CONFIG_BCMA_DEBUG is not set +# CONFIG_BCMA_DRIVER_GMAC_CMN is not set +# CONFIG_BCMA_DRIVER_MIPS is not set +# CONFIG_BCMA_DRIVER_PCI_HOSTMODE is not set +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BOARD_BCM63XX_DT=y +CONFIG_BOARD_BCM963XX=y +CONFIG_BOARD_LIVEBOX=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_BMIPS=y +CONFIG_CPU_BMIPS32_3300=y +CONFIG_CPU_BMIPS4350=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_74X164=y +CONFIG_GPIO_BCM63XX=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_SYSFS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_BCM63XX=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KEXEC=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +CONFIG_MIPS_APPENDED_DTB=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=4 +CONFIG_MIPS_L1_CACHE_SHIFT_4=y +# CONFIG_MIPS_MACHINE is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_BCM63XX_PARTS=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_BE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +# CONFIG_MTD_CFI_NOSWAP is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y +CONFIG_MTD_SPI_NOR=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RELAY=y +CONFIG_RTL8366_SMI=y +CONFIG_RTL8367_PHY=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_BCM63XX=y +CONFIG_SERIAL_BCM63XX_CONSOLE=y +CONFIG_SPI=y +CONFIG_SPI_BCM63XX=y +CONFIG_SPI_BCM63XX_HSSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_SSB=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_BLOCKIO=y +# CONFIG_SSB_DRIVER_MIPS is not set +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_SPROM=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWCONFIG=y +CONFIG_SYNC_R4K=y +CONFIG_SYS_HAS_CPU_BMIPS=y +CONFIG_SYS_HAS_CPU_BMIPS32_3300=y +CONFIG_SYS_HAS_CPU_BMIPS4350=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_WEAK_ORDERING=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/brcm63xx/config-4.1 b/target/linux/brcm63xx/config-4.1 new file mode 100644 index 0000000..d61b6e6 --- /dev/null +++ b/target/linux/brcm63xx/config-4.1 @@ -0,0 +1,241 @@ +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_B53=y +CONFIG_B53_MMAP_DRIVER=y +CONFIG_B53_PHY_DRIVER=y +CONFIG_B53_PHY_FIXUP=y +CONFIG_B53_SPI_DRIVER=y +# CONFIG_B53_SRAB_DRIVER is not set +CONFIG_BCM6345_EXT_IRQ=y +CONFIG_BCM6345_PERIPH_IRQ=y +CONFIG_BCM63XX=y +CONFIG_BCM63XX_CPU_3368=y +CONFIG_BCM63XX_CPU_6318=y +CONFIG_BCM63XX_CPU_63268=y +CONFIG_BCM63XX_CPU_6328=y +CONFIG_BCM63XX_CPU_6338=y +CONFIG_BCM63XX_CPU_6345=y +CONFIG_BCM63XX_CPU_6348=y +CONFIG_BCM63XX_CPU_6358=y +CONFIG_BCM63XX_CPU_6362=y +CONFIG_BCM63XX_CPU_6368=y +CONFIG_BCM63XX_EHCI=y +CONFIG_BCM63XX_ENET=y +CONFIG_BCM63XX_OHCI=y +CONFIG_BCM63XX_PHY=y +CONFIG_BCM63XX_WDT=y +CONFIG_BCMA=y +CONFIG_BCMA_BLOCKIO=y +# CONFIG_BCMA_DEBUG is not set +# CONFIG_BCMA_DRIVER_GMAC_CMN is not set +# CONFIG_BCMA_DRIVER_MIPS is not set +CONFIG_BCMA_DRIVER_PCI=y +# CONFIG_BCMA_DRIVER_PCI_HOSTMODE is not set +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BOARD_BCM63XX_DT=y +CONFIG_BOARD_BCM963XX=y +CONFIG_BOARD_LIVEBOX=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CMDLINE_OVERRIDE is not set +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_BMIPS=y +CONFIG_CPU_BMIPS32_3300=y +CONFIG_CPU_BMIPS4350=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_74X164=y +CONFIG_GPIO_BCM63XX=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_SYSFS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_BCM63XX=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KEXEC=y +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=4 +CONFIG_MIPS_L1_CACHE_SHIFT_4=y +# CONFIG_MIPS_MACHINE is not set +# CONFIG_MIPS_NO_APPENDED_DTB is not set +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_BCM63XX_PARTS=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_BE_BYTE_SWAP=y +# CONFIG_MTD_CFI_GEOMETRY is not set +# CONFIG_MTD_CFI_NOSWAP is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y +CONFIG_MTD_SPI_NOR=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +# CONFIG_PCIEAER is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RELAY=y +CONFIG_RTL8366_SMI=y +CONFIG_RTL8367_PHY=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_BCM63XX=y +CONFIG_SERIAL_BCM63XX_CONSOLE=y +CONFIG_SPI=y +CONFIG_SPI_BCM63XX=y +CONFIG_SPI_BCM63XX_HSSPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_SRCU=y +CONFIG_SSB=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_BLOCKIO=y +# CONFIG_SSB_DRIVER_MIPS is not set +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_SPROM=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWCONFIG=y +CONFIG_SYNC_R4K=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYS_HAS_CPU_BMIPS=y +CONFIG_SYS_HAS_CPU_BMIPS32_3300=y +CONFIG_SYS_HAS_CPU_BMIPS4350=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_WEAK_ORDERING=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/brcm63xx/dts/a226g.dts b/target/linux/brcm63xx/dts/a226g.dts new file mode 100644 index 0000000..b62c68f --- /dev/null +++ b/target/linux/brcm63xx/dts/a226g.dts @@ -0,0 +1,109 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Pirelli A226G"; + compatible = "pirelli,a226g", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wps { + label = "wps"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + voip_red { + label = "DWV-S0:red:VoIP"; + gpios = <&gpio0 0 1>; + }; + eth_red { + label = "DWV-S0:red:ethernet"; + gpios = <&gpio0 1 1>; + }; + dsl_green { + label = "DWV-S0:green:ADSL"; + gpios = <&gpio0 2 1>; + }; + usb_green { + label = "DWV-S0:green:USB"; + gpios = <&gpio0 3 1>; + }; + power_green { + label = "DWV-S0:green:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + power_red { + label = "DWV-S0:red:power"; + gpios = <&gpio0 5 1>; + }; + inet_red { + label = "DWV-S0:red:internet"; + gpios = <&gpio0 6 1>; + }; + inet_green { + label = "DWV-S0:green:internet"; + gpios = <&gpio0 7 1>; + }; + eth_green { + label = "DWV-S0:green:ethernet"; + gpios = <&gpio0 8 1>; + }; + voip_green { + label = "DWV-S0:green:VoIP"; + gpios = <&gpio0 9 1>; + }; + wifi_red { + label = "DWV-S0:red:wifi"; + gpios = <&gpio0 10 1>; + }; + usb_red { + label = "DWV-S0:red:USB"; + gpios = <&gpio0 11 1>; + }; + dsl_red { + label = "DWV-S0:red:ADSL"; + gpios = <&gpio0 12 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/a226m-fwb.dts b/target/linux/brcm63xx/dts/a226m-fwb.dts new file mode 100644 index 0000000..d91fffe --- /dev/null +++ b/target/linux/brcm63xx/dts/a226m-fwb.dts @@ -0,0 +1,109 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Pirelli A226M-FWB"; + compatible = "pirelli,a226m-fwb", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wps { + label = "wps"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + voip_red { + label = "DWV-S0:red:VoIP"; + gpios = <&gpio0 0 1>; + }; + eth_red { + label = "DWV-S0:red:ethernet"; + gpios = <&gpio0 1 1>; + }; + dsl_green { + label = "DWV-S0:green:ADSL"; + gpios = <&gpio0 2 1>; + }; + usb_green { + label = "DWV-S0:green:USB"; + gpios = <&gpio0 3 1>; + }; + power_green { + label = "DWV-S0:green:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + power_red { + label = "DWV-S0:red:power"; + gpios = <&gpio0 5 1>; + }; + inet_red { + label = "DWV-S0:red:internet"; + gpios = <&gpio0 6 1>; + }; + inet_green { + label = "DWV-S0:green:internet"; + gpios = <&gpio0 7 1>; + }; + eth_green { + label = "DWV-S0:green:ethernet"; + gpios = <&gpio0 8 1>; + }; + voip_green { + label = "DWV-S0:green:VoIP"; + gpios = <&gpio0 9 1>; + }; + wifi_red { + label = "DWV-S0:red:wifi"; + gpios = <&gpio0 10 1>; + }; + usb_red { + label = "DWV-S0:red:USB"; + gpios = <&gpio0 11 1>; + }; + dsl_red { + label = "DWV-S0:red:ADSL"; + gpios = <&gpio0 12 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0xfc0000>; + }; + + nvram@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/a226m.dts b/target/linux/brcm63xx/dts/a226m.dts new file mode 100644 index 0000000..d3f628d --- /dev/null +++ b/target/linux/brcm63xx/dts/a226m.dts @@ -0,0 +1,109 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Pirelli A226M"; + compatible = "pirelli,a226m", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wps { + label = "wps"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + voip_red { + label = "DWV-S0:red:VoIP"; + gpios = <&gpio0 0 1>; + }; + eth_red { + label = "DWV-S0:red:ethernet"; + gpios = <&gpio0 1 1>; + }; + dsl_green { + label = "DWV-S0:green:ADSL"; + gpios = <&gpio0 2 1>; + }; + usb_green { + label = "DWV-S0:green:USB"; + gpios = <&gpio0 3 1>; + }; + power_green { + label = "DWV-S0:green:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + power_red { + label = "DWV-S0:red:power"; + gpios = <&gpio0 5 1>; + }; + inet_red { + label = "DWV-S0:red:internet"; + gpios = <&gpio0 6 1>; + }; + inet_green { + label = "DWV-S0:green:internet"; + gpios = <&gpio0 7 1>; + }; + eth_green { + label = "DWV-S0:green:ethernet"; + gpios = <&gpio0 8 1>; + }; + voip_green { + label = "DWV-S0:green:VoIP"; + gpios = <&gpio0 9 1>; + }; + wifi_red { + label = "DWV-S0:red:wifi"; + gpios = <&gpio0 10 1>; + }; + usb_red { + label = "DWV-S0:red:USB"; + gpios = <&gpio0 11 1>; + }; + dsl_red { + label = "DWV-S0:red:ADSL"; + gpios = <&gpio0 12 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/a4001n.dts b/target/linux/brcm63xx/dts/a4001n.dts new file mode 100644 index 0000000..13c5e50 --- /dev/null +++ b/target/linux/brcm63xx/dts/a4001n.dts @@ -0,0 +1,55 @@ +/dts-v1/; + +#include "bcm6328.dtsi" + +#include + +/ { + model = "ADB P.DG A4001N"; + compatible = "adb,a4001n", "brcm,bcm6328"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 23 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio0 24 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_red { + label = "A4001N:red:inet"; + gpios = <&gpio0 1 0>; + }; + power_red { + label = "A4001N:red:power"; + gpios = <&gpio0 4 0>; + }; + power_green { + label = "A4001N:green:power"; + gpios = <&gpio0 8 0>; + default-state = "on"; + }; + usb_green { + label = "A4001N:green:usb"; + gpios = <&gpio0 10 1>; + }; + dsl_green { + label = "A4001N:green:dsl"; + gpios = <&gpio0 11 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/a4001n1.dts b/target/linux/brcm63xx/dts/a4001n1.dts new file mode 100644 index 0000000..e30d6d0 --- /dev/null +++ b/target/linux/brcm63xx/dts/a4001n1.dts @@ -0,0 +1,83 @@ +/dts-v1/; + +#include "bcm6328.dtsi" + +#include + +/ { + model = "ADB P.DG A4001N1"; + compatible = "adb,a4001n1", "brcm,bcm6328"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 23 1>; + linux,code = ; + }; + wps { + label = "wlan"; + gpios = <&gpio0 24 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_red { + label = "A4001N1:red:inet"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "A4001N1:green:ppp"; + gpios = <&gpio0 3 1>; + }; + power_green { + label = "A4001N1:green:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + ppp_red { + label = "A4001N1:red:ppp"; + gpios = <&gpio0 5 1>; + }; + usb_green { + label = "A4001N1:green:3g"; + gpios = <&gpio0 6 1>; + }; + usb_red { + label = "A4001N1:red:3g"; + gpios = <&gpio0 7 1>; + }; + power_red { + label = "A4001N1:red:power"; + gpios = <&gpio0 8 1>; + }; + wlan_green { + label = "A4001N1:green:wlan"; + gpios = <&gpio0 9 1>; + }; + wlan_red { + label = "A4001N1:red:wlan"; + gpios = <&gpio0 10 1>; + }; + inet_green { + label = "A4001N1:green:inet"; + gpios = <&gpio0 11 1>; + }; + eth_red { + label = "A4001N1:red:eth"; + gpios = <&gpio0 20 1>; + }; + eth_green { + label = "A4001N1:green:eth"; + gpios = <&gpio0 31 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/agpf-s0.dts b/target/linux/brcm63xx/dts/agpf-s0.dts new file mode 100644 index 0000000..4662b2d --- /dev/null +++ b/target/linux/brcm63xx/dts/agpf-s0.dts @@ -0,0 +1,113 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Pirelli Alice Gate AGPF-S0"; + compatible = "pirelli,agpf-s0", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wps { + label = "wps"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "AGPF-S0:green:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + power_red { + label = "AGPF-S0:red:power"; + gpios = <&gpio0 5 1>; + }; + service_green { + label = "AGPF-S0:green:service"; + gpios = <&gpio0 6 1>; + }; + service_red { + label = "AGPF-S0:red:service"; + gpios = <&gpio0 7 1>; + }; + dsl_green { + label = "AGPF-S0:green:adsl"; + gpios = <&gpio0 9 1>; + }; + dsl_red { + label = "AGPF-S0:red:adsl"; + gpios = <&gpio0 10 1>; + }; + wifi_green { + label = "AGPF-S0:green:wifi"; + gpios = <&gpio0 22 1>; + }; + wifi_red { + label = "AGPF-S0:red:wifi"; + gpios = <&gpio0 23 1>; + }; + inet_red { + label = "AGPF-S0:red:internet"; + gpios = <&gpio0 24 1>; + }; + inet_green { + label = "AGPF-S0:green:internet"; + gpios = <&gpio0 25 1>; + }; + usr1_green { + label = "AGPF-S0:green:usr1"; + gpios = <&gpio0 26 1>; + }; + usr1_red { + label = "AGPF-S0:red:usr1"; + gpios = <&gpio0 27 1>; + }; + usr2_green { + label = "AGPF-S0:green:usr2"; + gpios = <&gpio0 29 1>; + }; + usr2_red { + label = "AGPF-S0:red:usr2"; + gpios = <&gpio0 30 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0xfc0000>; + }; + + nvram@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/ar-5381u.dts b/target/linux/brcm63xx/dts/ar-5381u.dts new file mode 100644 index 0000000..a148ec4 --- /dev/null +++ b/target/linux/brcm63xx/dts/ar-5381u.dts @@ -0,0 +1,42 @@ +/dts-v1/; + +#include "bcm6328.dtsi" + +#include + +/ { + model = "Comtrend AR-5381u"; + compatible = "comtrend,ar-5381u", "brcm,bcm6328"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 23 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + alarm_red { + label = "AR-5381u:red:alarm"; + gpios = <&gpio0 2 1>; + }; + inet_green { + label = "AR-5381u:green:inet"; + gpios = <&gpio0 3 1>; + }; + power_green { + label = "AR-5381u:green:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/ar-5387un.dts b/target/linux/brcm63xx/dts/ar-5387un.dts new file mode 100644 index 0000000..c30da06 --- /dev/null +++ b/target/linux/brcm63xx/dts/ar-5387un.dts @@ -0,0 +1,50 @@ +/dts-v1/; + +#include "bcm6328.dtsi" + +#include + +/ { + model = "Comtrend AR-5387un"; + compatible = "comtrend,ar-5387un", "brcm,bcm6328"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 23 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_red { + label = "AR-5387un:red:inet"; + gpios = <&gpio0 1 0>; + }; + power_red { + label = "AR-5387un:red:power"; + gpios = <&gpio0 4 0>; + }; + inet_green { + label = "AR-5387un:green:inet"; + gpios = <&gpio0 7 0>; + }; + power_green { + label = "AR-5387un:green:power"; + gpios = <&gpio0 8 0>; + default-state = "on"; + }; + dsl_green { + label = "AR-5387un:green:dsl"; + gpios = <&gpio0 11 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/ar1004g.dts b/target/linux/brcm63xx/dts/ar1004g.dts new file mode 100644 index 0000000..0740799 --- /dev/null +++ b/target/linux/brcm63xx/dts/ar1004g.dts @@ -0,0 +1,42 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "ASMAX AR 1004g"; + compatible = "asmax,ar1004g", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "AR1004G:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + inet_green { + label = "AR1004G:green:inet"; + gpios = <&gpio0 3 1>; + }; + power_red { + label = "AR1004G:red:power"; + gpios = <&gpio0 6 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm3368.dtsi b/target/linux/brcm63xx/dts/bcm3368.dtsi new file mode 100644 index 0000000..5be5c6a --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm3368.dtsi @@ -0,0 +1,95 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm3368"; + + aliases { + pflash = &pflash; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + pflash: nor@1e000000 { + compatible = "cfi-flash"; + reg = <0x1e000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus@fff00000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + periph_intc: interrupt-controller@fff8c00c { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0xfffe000c 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + ext_intc0: interrupt-controller@fff8c014 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <25>, <26>, <27>, <28>; + }; + + gpio1: gpio-controller@fff8c080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfff8c080 4>, <0xfff8c088 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <8>; + }; + + gpio0: gpio-controller@fff8c084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfff8c084 4>, <0xfff8c08c 4>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm6318.dtsi b/target/linux/brcm63xx/dts/bcm6318.dtsi new file mode 100644 index 0000000..f851a9c --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm6318.dtsi @@ -0,0 +1,78 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6318"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips3300", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + ubus@10000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <24>, <25>, <26>, <27>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0x10000020 0x20>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 4>, <0x10000088 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <18>; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 4>, <0x1000008c 4>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm63268.dtsi b/target/linux/brcm63xx/dts/bcm63268.dtsi new file mode 100644 index 0000000..0a1f8b1 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm63268.dtsi @@ -0,0 +1,85 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm63268"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + ubus@10000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <44>, <45>, <46>, <47>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0x10000020 0x20>, + <0x10000040 0x20>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + gpio1: gpio-controller@100000c0 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c0 4>, <0x100000c8 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <20>; + }; + + gpio0: gpio-controller@100000c4 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x100000c4 4>, <0x100000cc 4>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm6328.dtsi b/target/linux/brcm63xx/dts/bcm6328.dtsi new file mode 100644 index 0000000..a0b1316 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm6328.dtsi @@ -0,0 +1,67 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6328"; + + aliases { + gpio0 = &gpio0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + ubus@10000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <24>, <25>, <26>, <27>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0x10000020 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 4>, <0x1000008c 4>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm6338.dtsi b/target/linux/brcm63xx/dts/bcm6338.dtsi new file mode 100644 index 0000000..d578a5b --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm6338.dtsi @@ -0,0 +1,80 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6338"; + + aliases { + pflash = &pflash; + gpio0 = &gpio0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips3300", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + pflash: nor@1fc00000 { + compatible = "cfi-flash"; + reg = <0x1fc00000 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus@fff00000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0xfffe000c 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + ext_intc: interrupt-controller@fffe0014 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpu_intc>; + interrupts = <3>, <4>, <5>, <6>; + }; + + gpio0: gpio-controller@fffe0404 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0404 4>, <0xfffe040c 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <8>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm6345.dtsi b/target/linux/brcm63xx/dts/bcm6345.dtsi new file mode 100644 index 0000000..f702468 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm6345.dtsi @@ -0,0 +1,80 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6345"; + + aliases { + pflash = &pflash; + gpio0 = &gpio0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips32", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + pflash: nor@1fc00000 { + compatible = "cfi-flash"; + reg = <0x1fc00000 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus@fff00000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0xfffe000c 0x9>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + ext_intc: interrupt-controller@fffe0014 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpu_intc>; + interrupts = <3>, <4>, <5>, <6>; + }; + + gpio0: gpio-controller@fffe0404 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0404 4>, <0xfffe0408 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <16>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm6348.dtsi b/target/linux/brcm63xx/dts/bcm6348.dtsi new file mode 100644 index 0000000..81e99ed --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm6348.dtsi @@ -0,0 +1,91 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6348"; + + aliases { + pflash = &pflash; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips3300", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + pflash: nor@1fc00000 { + compatible = "cfi-flash"; + reg = <0x1fc00000 0x400000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus@fff00000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0xfffe000c 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>; + }; + + ext_intc: interrupt-controller@fffe0014 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpu_intc>; + interrupts = <3>, <4>, <5>, <6>; + + brcm,field-width = <5>; + }; + + gpio1: gpio-controller@fffe0400 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0400 4>, <0xfffe0408 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <5>; + }; + + gpio0: gpio-controller@fffe0404 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0404 4>, <0xfffe040c 4>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm6358.dtsi b/target/linux/brcm63xx/dts/bcm6358.dtsi new file mode 100644 index 0000000..bc3784a --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm6358.dtsi @@ -0,0 +1,107 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6358"; + + aliases { + pflash = &pflash; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + pflash: nor@1e000000 { + compatible = "cfi-flash"; + reg = <0x1e000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + }; + + ubus@fff00000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0xfffe000c 0x8>, + <0xfffe0038 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + ext_intc0: interrupt-controller@fffe0014 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe0014 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <25>, <26>, <27>, <28>; + }; + + ext_intc1: interrupt-controller@fffe001c { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0xfffe001c 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <20>, <21>; + }; + + gpio1: gpio-controller@fffe0080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0080 4>, <0xfffe0088 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <8>; + }; + + gpio0: gpio-controller@fffe0084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0xfffe0084 4>, <0xfffe008c 4>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm6362.dtsi b/target/linux/brcm63xx/dts/bcm6362.dtsi new file mode 100644 index 0000000..6604f5c --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm6362.dtsi @@ -0,0 +1,85 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6362"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + ubus@10000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <40>, <41>, <42>, <43>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 4>, <0x10000088 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <16>; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 4>, <0x1000008c 4>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm6368.dtsi b/target/linux/brcm63xx/dts/bcm6368.dtsi new file mode 100644 index 0000000..7dbe9ec --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm6368.dtsi @@ -0,0 +1,106 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6368"; + + aliases { + pflash = &pflash; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + }; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + memory { device_type = "memory"; reg = <0 0>; }; + + ubus@10000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + ext_intc0: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x10000018 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <20>, <21>, <22>, <23>; + }; + + ext_intc1: interrupt-controller@1000001c { + compatible = "brcm,bcm6345-ext-intc"; + reg = <0x1000001c 0x4>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&periph_intc>; + interrupts = <24>, <25>; + }; + + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-periph-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 4>, <0x10000088 4>; + + gpio-controller; + #gpio-cells = <2>; + + ngpios = <6>; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 4>, <0x1000008c 4>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + + pflash: nor@18000000 { + compatible = "cfi-flash"; + reg = <0x18000000 0x2000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96318ref.dts b/target/linux/brcm63xx/dts/bcm96318ref.dts new file mode 100644 index 0000000..79137db --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96318ref.dts @@ -0,0 +1,49 @@ +/dts-v1/; + +#include "bcm6318.dtsi" + +#include + +/ { + model = "Broadcom BCM96318REF reference board"; + compatible = "brcm,bcm96318ref", "brcm,bcm6318"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wps { + label = "wps"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet { + label = "96318REF:green:inet"; + gpios = <&gpio0 8 1>; + }; + + inet_fail { + label = "96318REF:red:inet-fail"; + gpios = <&gpio0 9 1>; + }; + + post_failed { + label = "96318REF:red:post-failed"; + gpios = <&gpio0 11 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96318ref_p300.dts b/target/linux/brcm63xx/dts/bcm96318ref_p300.dts new file mode 100644 index 0000000..be1db5a --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96318ref_p300.dts @@ -0,0 +1,55 @@ +/dts-v1/; + +#include "bcm6318.dtsi" + +#include + +/ { + model = "Broadcom BCM96318REF_P300 reference board"; + compatible = "brcm,bcm96318ref_p300", "brcm,bcm6318"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wps { + label = "wps"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet { + label = "96318REF_P300:green:inet"; + gpios = <&gpio0 8 1>; + }; + + inet_fail { + label = "96318REF_P300:red:inet-fail"; + gpios = <&gpio0 9 1>; + }; + + post_failed { + label = "96318REF_P300:red:post-failed"; + gpios = <&gpio0 11 1>; + }; + + usb_pwron { + label = "96318REF_P300::usb-pwron"; + gpios = <&gpio0 13 1>; + default-state = "on"; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm963268bu_p300.dts b/target/linux/brcm63xx/dts/bcm963268bu_p300.dts new file mode 100644 index 0000000..f659b39 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm963268bu_p300.dts @@ -0,0 +1,30 @@ +/dts-v1/; + +#include "bcm63268.dtsi" + +#include + +/ { + model = "Broadcom BCM963268BU_P300 reference board"; + compatible = "brcm,bcm963268bu_p300", "brcm,bcm63268"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 0 0>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&gpio1 1 0>; + linux,code = ; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm963269bhr.dts b/target/linux/brcm63xx/dts/bcm963269bhr.dts new file mode 100644 index 0000000..01a7680 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm963269bhr.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +#include "bcm63268.dtsi" + +#include + +/ { + model = "Broadcom BCM963269BHR reference board"; + compatible = "brcm,bcm963269bhr", "brcm,bcm63268"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 0 0>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + usb1 { + label = "963269BHR:green:usb1"; + gpios = <&gpio0 9 1>; + }; + + usb2 { + label = "963269BHR:green:usb2"; + gpios = <&gpio0 10 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm963281TAN.dts b/target/linux/brcm63xx/dts/bcm963281TAN.dts new file mode 100644 index 0000000..21b329a --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm963281TAN.dts @@ -0,0 +1,40 @@ +/dts-v1/; + +#include "bcm6328.dtsi" + +#include + +/ { + model = "Broadcom bcm963281TAN reference board"; + compatible = "brcm,bcm963281TAN", "brcm,bcm6328"; + + gpio-leds { + compatible = "gpio-leds"; + + inet { + label = "963281TAN::internet"; + gpios = <&gpio0 1 1>; + }; + power { + label = "963281TAN::power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + inet_fail { + label = "963281TAN::internet-fail"; + gpios = <&gpio0 7 1>; + }; + power_fail { + label = "963281TAN::power-fail"; + gpios = <&gpio0 8 1>; + }; + wps { + label = "963281TAN::wps"; + gpios = <&gpio0 9 1>; + }; + dsl { + label = "963281TAN::dsl"; + gpios = <&gpio0 11 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96328avng.dts b/target/linux/brcm63xx/dts/bcm96328avng.dts new file mode 100644 index 0000000..3ed4b22 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96328avng.dts @@ -0,0 +1,40 @@ +/dts-v1/; + +#include "bcm6328.dtsi" + +#include + +/ { + model = "Broadcom BCM96328avng reference board"; + compatible = "brcm,bcm96328avng", "brcm,bcm6328"; + + gpio-leds { + compatible = "gpio-leds"; + + inet_fail { + label = "96328avng::internet-fail"; + gpios = <&gpio0 2 1>; + }; + dsl { + label = "96328avng::dsl"; + gpios = <&gpio0 3 1>; + }; + power { + label = "96328avng::power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + power_fail { + label = "96328avng::power-fail"; + gpios = <&gpio0 8 1>; + }; + wps { + label = "96328avng::wps"; + gpios = <&gpio0 9 1>; + }; + inet { + label = "96328avng::internet"; + gpios = <&gpio0 11 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96338GW.dts b/target/linux/brcm63xx/dts/bcm96338GW.dts new file mode 100644 index 0000000..d7af9ef --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96338GW.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +#include "bcm6338.dtsi" + +#include + +/ { + model = "Broadcom BCM96338GW reference board"; + compatible = "brcm,bcm96338gw", "brcm,bcm6338"; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96338GW:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96338GW:green:stop"; + gpios = <&gpio0 1 1>; + }; + dsl_green { + label = "96338GW:green:adsl"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96338GW:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + ses_green { + label = "96338GW:green:ses"; + gpios = <&gpio0 5 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96338W.dts b/target/linux/brcm63xx/dts/bcm96338W.dts new file mode 100644 index 0000000..4904073 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96338W.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +#include "bcm6338.dtsi" + +#include + +/ { + model = "Broadcom BCM96338W reference board"; + compatible = "brcm,bcm96338w", "brcm,bcm6338"; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96338W:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96338W:green:stop"; + gpios = <&gpio0 1 1>; + }; + dsl_green { + label = "96338W:green:adsl"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96338W:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + ses_green { + label = "96338W:green:ses"; + gpios = <&gpio0 5 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96345GW2.dts b/target/linux/brcm63xx/dts/bcm96345GW2.dts new file mode 100644 index 0000000..7214185 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96345GW2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "bcm6345.dtsi" + +#include + +/ { + model = "Broadcom BCM96345GW2 reference board"; + compatible = "brcm,bcm96345gw2", "brcm,bcm6345"; +}; diff --git a/target/linux/brcm63xx/dts/bcm96348GW-10.dts b/target/linux/brcm63xx/dts/bcm96348GW-10.dts new file mode 100644 index 0000000..5f60d36 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96348GW-10.dts @@ -0,0 +1,50 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Broadcom BCM96348GW-10 reference board"; + compatible = "brcm,bcm96348gw-10", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 6 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348GW-10:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96348GW-10:green:stop"; + gpios = <&gpio0 1 1>; + }; + adsl_fail_green { + label = "96348GW-10:green:adsl-fail"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "96348GW-10:green:ppp"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96348GW-10:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96348GW-11.dts b/target/linux/brcm63xx/dts/bcm96348GW-11.dts new file mode 100644 index 0000000..efd3e91 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96348GW-11.dts @@ -0,0 +1,50 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Broadcom BCM96348GW-11 reference board"; + compatible = "brcm,bcm96348gw-11", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348GW-11:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96348GW-11:green:stop"; + gpios = <&gpio0 1 1>; + }; + adsl_fail_green { + label = "96348GW-11:green:adsl-fail"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "96348GW-11:green:ppp"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96348GW-11:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96348GW.dts b/target/linux/brcm63xx/dts/bcm96348GW.dts new file mode 100644 index 0000000..cf40e52 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96348GW.dts @@ -0,0 +1,50 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Broadcom BCM96348GW reference board"; + compatible = "brcm,bcm96348gw", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 4 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348GW:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96348GW:green:stop"; + gpios = <&gpio0 1 1>; + }; + adsl_fail_green { + label = "96348GW:green:adsl-fail"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "96348GW:green:ppp"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96348GW:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96348R.dts b/target/linux/brcm63xx/dts/bcm96348R.dts new file mode 100644 index 0000000..d7df2a9 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96348R.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Broadcom 96348R reference board"; + compatible = "brcm,bcm96348r", "brcm,bcm6348"; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348R:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96348R:green:stop"; + gpios = <&gpio0 1 1>; + }; + adsl_fail_green { + label = "96348R:green:adsl-fail"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "96348R:green:ppp"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96348R:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96358VW.dts b/target/linux/brcm63xx/dts/bcm96358VW.dts new file mode 100644 index 0000000..ff92499 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96358VW.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Broadcom BCM96358VW reference board"; + compatible = "brcm,bcm96358vw", "brcm,bcm6358"; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96358VW:green:power"; + gpios = <&gpio0 4 0>; + default-state = "on"; + }; + stop_green { + label = "96358VW:green:stop"; + gpios = <&gpio0 5 0>; + }; + adsl_fail_green { + label = "96358VW:green:adsl-fail"; + gpios = <&gpio0 15 1>; + }; + ppp_green { + label = "96358VW:green:ppp"; + gpios = <&gpio0 22 1>; + }; + ppp_fail_green { + label = "96358VW:green:ppp-fail"; + gpios = <&gpio0 23 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96358VW2.dts b/target/linux/brcm63xx/dts/bcm96358VW2.dts new file mode 100644 index 0000000..8f7070a --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96358VW2.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Broadcom BCM96358VW2 reference board"; + compatible = "brcm,bcm96358vw2", "brcm,bcm6358"; + + gpio-leds { + compatible = "gpio-leds"; + + stop_green { + label = "96358VW2:green:stop"; + gpios = <&gpio0 4 1>; + }; + power_green { + label = "96358VW2:green:power"; + gpios = <&gpio0 5 1>; + default-state = "on"; + }; + adsl_green { + label = "96358VW2:green:adsl"; + gpios = <&gpio0 22 1>; + }; + ppp_fail_green { + label = "96358VW2:green:ppp-fail"; + gpios = <&gpio0 23 0>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96368MVNgr.dts b/target/linux/brcm63xx/dts/bcm96368MVNgr.dts new file mode 100644 index 0000000..21f1395 --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96368MVNgr.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Broadcom BCM96368MVNgr reference board"; + compatible = "brcm,bcm96368mvngr", "brcm,bcm6368"; + + gpio-leds { + compatible = "gpio-leds"; + + dsl_green { + label = "96368MVNgr:green:adsl"; + gpios = <&gpio0 2 1>; + }; + inet_fail_green { + label = "96368MVNgr:green:inet-fail"; + gpios = <&gpio0 3 0>; + }; + inet_green { + label = "96368MVNgr:green:inet"; + gpios = <&gpio0 5 0>; + }; + power_green { + label = "96368MVNgr:green:power"; + gpios = <&gpio0 22 0>; + default-state = "on"; + }; + wps_green { + label = "96368MVNgr:green:wps"; + gpios = <&gpio0 23 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/bcm96368MVWG.dts b/target/linux/brcm63xx/dts/bcm96368MVWG.dts new file mode 100644 index 0000000..04442ab --- /dev/null +++ b/target/linux/brcm63xx/dts/bcm96368MVWG.dts @@ -0,0 +1,36 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Broadcom BCM96368MVWG reference board"; + compatible = "brcm,bcm96368mvwg", "brcm,bcm6368"; + + gpio-leds { + compatible = "gpio-leds"; + + dsl_green { + label = "96368MVWG:green:adsl"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "96368MVWG:green:ppp"; + gpios = <&gpio0 5 0>; + }; + power_green { + label = "96368MVWG:green:power"; + gpios = <&gpio0 22 0>; + default-state = "on"; + }; + wps_green { + label = "96368MVWG:green:wps"; + gpios = <&gpio0 23 1>; + }; + ppp_fail_red { + label = "96368MVWG:red:ppp-fail"; + gpios = <&gpio0 31 0>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/cpva502plus.dts b/target/linux/brcm63xx/dts/cpva502plus.dts new file mode 100644 index 0000000..f00d73e --- /dev/null +++ b/target/linux/brcm63xx/dts/cpva502plus.dts @@ -0,0 +1,46 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Telsey CPVA502+"; + compatible = "telsey,cpva502+", "brcm,bcm6348"; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "CPVA502+:green:phone"; + gpios = <&gpio0 0 1>; + }; + + status { + label = "CPVA502+:amber:link"; + gpios = <&gpio0 1 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/cpva642.dts b/target/linux/brcm63xx/dts/cpva642.dts new file mode 100644 index 0000000..8d72e02 --- /dev/null +++ b/target/linux/brcm63xx/dts/cpva642.dts @@ -0,0 +1,97 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Telsey CPVA642-type (CPA-ZNTE60T)"; + compatible = "telsey,cpva642", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 4 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio1 5 0>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + eth_green { + label = "CPVA642:green:ether"; + gpios = <&gpio0 1 1>; + }; + phone2_green { + label = "CPVA642:green:phone2"; + gpios = <&gpio0 2 1>; + }; + usb_green { + label = "CPVA642:green:usb"; + gpios = <&gpio0 3 1>; + }; + phone1_green { + label = "CPVA642:green:phone1"; + gpios = <&gpio0 4 1>; + }; + wifi_red { + label = "CPVA642:red:wifi"; + gpios = <&gpio0 6 1>; + }; + link_red { + label = "CPVA642:red:link"; + gpios = <&gpio0 9 1>; + }; + link_green { + label = "CPVA642:green:link"; + gpios = <&gpio0 10 1>; + }; + power_green { + label = "CPVA642:green:power"; + gpios = <&gpio0 11 1>; + default-state = "on"; + }; + power_red { + label = "CPVA642:red:power"; + gpios = <&gpio0 14 1>; + }; + wifi_green { + label = "CPVA642:green:wifi"; + gpios = <&gpio0 28 0>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/ct-5365.dts b/target/linux/brcm63xx/dts/ct-5365.dts new file mode 100644 index 0000000..6f452fe --- /dev/null +++ b/target/linux/brcm63xx/dts/ct-5365.dts @@ -0,0 +1,74 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Comtrend CT-5365"; + compatible = "comtrend,ct-5365", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + wlan { + label = "wlan"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio1 3 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348A-122:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + alarm_red { + label = "96348A-122:red:alarm"; + gpios = <&gpio0 2 1>; + }; + wps_green { + label = "96348A-122:green:wps"; + gpios = <&gpio0 6 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/ct-6373.dts b/target/linux/brcm63xx/dts/ct-6373.dts new file mode 100644 index 0000000..d6f0f8b --- /dev/null +++ b/target/linux/brcm63xx/dts/ct-6373.dts @@ -0,0 +1,100 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Comtrend CT-6373"; + compatible = "comtrend,ct-6373", "brcm,bcm6358"; + + spi-gpio { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-gpio"; + + gpio-mosi = <&gpio0 7 0>; + gpio-sck = <&gpio0 6 0>; + num-chipselects = <0>; + + hc595: gpio-spi-controller@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 3 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "CT6373-1:green:power"; + gpios = <&gpio0 0 0>; + default-state = "on"; + }; + usb_green { + label = "CT6373-1:green:usb"; + gpios = <&gpio0 3 1>; + }; + wlan_green { + label = "CT6373-1:green:wlan"; + gpios = <&gpio0 9 1>; + }; + dsl_green { + label = "CT6373-1:green:adsl"; + gpios = <&hc595 0 1>; + }; + line_green { + label = "CT6373-1:green:line"; + gpios = <&hc595 1 1>; + }; + fxs1_green { + label = "CT6373-1:green:fxs1"; + gpios = <&hc595 2 1>; + }; + fxs2_green { + label = "CT6373-1:green:fxs2"; + gpios = <&hc595 3 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/ct536plus.dts b/target/linux/brcm63xx/dts/ct536plus.dts new file mode 100644 index 0000000..c05068a --- /dev/null +++ b/target/linux/brcm63xx/dts/ct536plus.dts @@ -0,0 +1,38 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Comtrend CT-536+/CT-5621T"; + compatible = "comtrend,ct536+", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "CT536_CT5621:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + adsl_fail_green { + label = "CT536_CT5621:green:adsl-fail"; + gpios = <&gpio0 2 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/cvg834g.dts b/target/linux/brcm63xx/dts/cvg834g.dts new file mode 100644 index 0000000..b61a07c --- /dev/null +++ b/target/linux/brcm63xx/dts/cvg834g.dts @@ -0,0 +1,42 @@ +/dts-v1/; + +#include "bcm3368.dtsi" + +#include + +/ { + model = "Netgear CVG834G"; + compatible = "netgear,cvg834g", "brcm,bcm6348"; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "CVG834G:green:power"; + gpios = <&gpio1 5 0>; + default-state = "on"; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dg834g_v4.dts b/target/linux/brcm63xx/dts/dg834g_v4.dts new file mode 100644 index 0000000..1485300 --- /dev/null +++ b/target/linux/brcm63xx/dts/dg834g_v4.dts @@ -0,0 +1,68 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Netgear DG834G v4"; + compatible = "netgear,dg834g-v4", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 6 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348W3:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + status { + label = "96348W3:red:power"; + gpios = <&gpio0 1 1>; + }; + inet_green { + label = "96348W3::adsl"; + gpios = <&gpio0 2 1>; + }; + inet_red { + label = "96348W3::internet"; + gpios = <&gpio0 3 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dg834gtpn.dts b/target/linux/brcm63xx/dts/dg834gtpn.dts new file mode 100644 index 0000000..8894358 --- /dev/null +++ b/target/linux/brcm63xx/dts/dg834gtpn.dts @@ -0,0 +1,72 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Netgear DG834GT/PN"; + compatible = "netgear,dg834gtpn", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 6 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348GW-10:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96348GW-10:green:stop"; + gpios = <&gpio0 1 1>; + }; + adsl_fail_green { + label = "96348GW-10:green:adsl-fail"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "96348GW-10:green:ppp"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96348GW-10:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dgnd3700v1.dts b/target/linux/brcm63xx/dts/dgnd3700v1.dts new file mode 100644 index 0000000..8c8c0bf --- /dev/null +++ b/target/linux/brcm63xx/dts/dgnd3700v1.dts @@ -0,0 +1,112 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Netgear DGND3700v1/DGND3800B"; + compatible = "netgear,dgnd3700v1", "brcm,bcm6368"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wlan { + label = "wlan"; + gpios = <&gpio0 10 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio0 12 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio1 3 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + dsl_green { + label = "DGND3700v1_3800B:green:dsl"; + gpios = <&gpio0 2 1>; + }; + inet_red { + label = "DGND3700v1_3800B:red:inet"; + gpios = <&gpio0 4 1>; + }; + inet_green { + label = "DGND3700v1_3800B:green:inet"; + gpios = <&gpio0 5 1>; + }; + wps_green { + label = "DGND3700v1_3800B:green:wps"; + gpios = <&gpio0 11 1>; + }; + usbfront_green { + label = "DGND3700v1_3800B:green:usb-front"; + gpios = <&gpio0 13 1>; + }; + usbback_green { + label = "DGND3700v1_3800B:green:usb-back"; + gpios = <&gpio0 14 1>; + }; + power_red { + label = "DGND3700v1_3800B:red:power"; + gpios = <&gpio0 22 1>; + }; + lan_green { + label = "DGND3700v1_3800B:green:lan"; + gpios = <&gpio0 23 1>; + }; + power_green { + label = "DGND3700v1_3800B:green:power"; + gpios = <&gpio0 24 1>; + default-state = "on"; + }; + wifi2g_green { + label = "DGND3700v1_3800B:green:wifi2g"; + gpios = <&gpio0 26 1>; + }; + wifi5g_blue { + label = "DGND3700v1_3800B:blue:wifi5g"; + gpios = <&gpio0 27 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0x1e20000>; + }; + + board_data@1e40000 { + label = "board_data"; + reg = <0x1e40000 0x1a0000>; + read-only; + }; + + nvram@1fe0000 { + label = "nvram"; + reg = <0x1fe0000 0x20000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dsl-2640b-b.dts b/target/linux/brcm63xx/dts/dsl-2640b-b.dts new file mode 100644 index 0000000..83b36a5 --- /dev/null +++ b/target/linux/brcm63xx/dts/dsl-2640b-b.dts @@ -0,0 +1,68 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "D-Link DSL-2640B rev B2"; + compatible = "d-link,dsl-2640b-b", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 7 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "D-4P-W:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + status { + label = "D-4P-W::status"; + gpios = <&gpio0 3 1>; + }; + inet_green { + label = "D-4P-W:green:internet"; + gpios = <&gpio0 4 1>; + }; + inet_red { + label = "D-4P-W:red:internet"; + gpios = <&gpio0 5 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dsl-2640u.dts b/target/linux/brcm63xx/dts/dsl-2640u.dts new file mode 100644 index 0000000..d3d2772 --- /dev/null +++ b/target/linux/brcm63xx/dts/dsl-2640u.dts @@ -0,0 +1,52 @@ +/dts-v1/; + +#include "bcm6338.dtsi" + +#include + +/ { + model = "D-Link DSL-2640U/BRU/C"; + compatible = "d-link,dsl-2640u", "brcm,bcm6338"; + + gpio-leds { + compatible = "gpio-leds"; + + green_power { + label = "96338W2_E7T:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + + green_stop { + label = "96338W2_E7T:green:ppp"; + gpios = <&gpio0 4 1>; + }; + + green_adsl { + label = "96338W2_E7T:green:ppp-fail"; + gpios = <&gpio0 5 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dsl-2650u.dts b/target/linux/brcm63xx/dts/dsl-2650u.dts new file mode 100644 index 0000000..2847c18 --- /dev/null +++ b/target/linux/brcm63xx/dts/dsl-2650u.dts @@ -0,0 +1,54 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "D-Link DSL-2650U"; + compatible = "d-link,dsl-2650u", "brcm,bcm6358"; + + gpio-leds { + compatible = "gpio-leds"; + + stop_green { + label = "96358VW2:green:stop"; + gpios = <&gpio0 4 1>; + }; + power_green { + label = "96358VW2:green:power"; + gpios = <&gpio0 5 1>; + default-state = "on"; + }; + adsl_green { + label = "96358VW2:green:adsl"; + gpios = <&gpio0 22 1>; + }; + ppp_fail_green { + label = "96358VW2:green:ppp-fail"; + gpios = <&gpio0 23 0>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dsl-274xb-c.dts b/target/linux/brcm63xx/dts/dsl-274xb-c.dts new file mode 100644 index 0000000..29ae125 --- /dev/null +++ b/target/linux/brcm63xx/dts/dsl-274xb-c.dts @@ -0,0 +1,72 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "D-Link DSL-2740B/DSL-2741B rev C2/3"; + compatible = "d-link,dsl-274xb-c2", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "dsl-274xb:green:internet"; + gpios = <&gpio0 2 0>; + }; + power_red { + label = "dsl-274xb:red:power"; + gpios = <&gpio0 4 1>; + }; + power_green { + label = "dsl-274xb:green:power"; + gpios = <&gpio0 5 1>; + default-state = "on"; + }; + dsl_green { + label = "dsl-274xb:green:adsl"; + gpios = <&gpio0 9 1>; + }; + inet_red { + label = "dsl-274xb:red:internet"; + gpios = <&gpio0 10 0>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dsl-274xb-f.dts b/target/linux/brcm63xx/dts/dsl-274xb-f.dts new file mode 100644 index 0000000..fb1ded7 --- /dev/null +++ b/target/linux/brcm63xx/dts/dsl-274xb-f.dts @@ -0,0 +1,64 @@ +/dts-v1/; + +#include "bcm6328.dtsi" + +#include + +/ { + model = "D-Link DSL-2740B/DSL-2741B rev F1"; + compatible = "d-link,dsl-274xb-f", "brcm,bcm6328"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wifi { + label = "wifi"; + gpios = <&gpio0 10 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio0 23 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio0 24 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_red { + label = "dsl-274xb:red:internet"; + gpios = <&gpio0 2 1>; + }; + dsl_green { + label = "dsl-274xb:green:dsl"; + gpios = <&gpio0 3 1>; + }; + power_green { + label = "dsl-274xb:green:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + power_red { + label = "dsl-274xb:red:power"; + gpios = <&gpio0 8 1>; + }; + wps_blue { + label = "dsl-274xb:blue:wps"; + gpios = <&gpio0 9 1>; + }; + inet_green { + label = "dsl-274xb:green:internet"; + gpios = <&gpio0 11 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/dsl-275xb-d.dts b/target/linux/brcm63xx/dts/dsl-275xb-d.dts new file mode 100644 index 0000000..dd00e2c --- /dev/null +++ b/target/linux/brcm63xx/dts/dsl-275xb-d.dts @@ -0,0 +1,77 @@ +/dts-v1/; + +#include "bcm6318.dtsi" + +#include + +/ { + model = "D-Link DSL-2750B/DSL-2751 rev D1"; + compatible = "d-link,dsl-275xb-d", "brcm,bcm6318"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wifi { + label = "wifi"; + gpios = <&gpio0 2 1>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "dsl-275xb:green:power"; + gpios = <&gpio0 3 1>; + default-state = "on"; + }; + + inet_green { + label = "dsl-275xb:green:inet"; + gpios = <&gpio0 8 1>; + }; + + inet_red { + label = "dsl-275xb:red:inet-fail"; + gpios = <&gpio0 9 1>; + }; + + power_red { + label = "dsl-275xb:red:post-failed"; + gpios = <&gpio0 11 1>; + }; + + wps_blue { + label = "dsl-275xb:blue:wps"; + gpios = <&gpio0 16 1>; + }; + + dsl_green { + label = "dsl-275xb:green:dsl"; + gpios = <&gpio0 17 1>; + }; + + usb_green { + /* not user controllable? */ + label = "dsl-275xb:green:usb"; + gpios = <&gpio1 17 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/dv-201amr.dts b/target/linux/brcm63xx/dts/dv-201amr.dts new file mode 100644 index 0000000..f792ac2 --- /dev/null +++ b/target/linux/brcm63xx/dts/dv-201amr.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Davolink DV-201AMR"; + compatible = "davolink,dv-201amr", "brcm,bcm6348"; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + backup@0 { + label = "backup"; + reg = <0x000000 0x400000>; + }; + + cfe@400000 { + label = "cfe"; + reg = <0x400000 0x010000>; + read-only; + }; + + linux@410000 { + label = "linux"; + reg = <0x410000 0x3f0000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/dva-g3810bn_tl.dts b/target/linux/brcm63xx/dts/dva-g3810bn_tl.dts new file mode 100644 index 0000000..2009825 --- /dev/null +++ b/target/linux/brcm63xx/dts/dva-g3810bn_tl.dts @@ -0,0 +1,50 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "D-Link DVA-G3810BN/TL"; + compatible = "d-link,dva-g3810bn/tl", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + voip { + label = "DVAG3810BN::voip"; + gpios = <&gpio0 1 0>; + }; + power { + label = "DVAG3810BN::power"; + gpios = <&gpio0 4 0>; + default-state = "on"; + }; + stop { + label = "DVAG3810BN::stop"; + gpios = <&gpio0 5 0>; + }; + dsl { + label = "DVAG3810BN::dsl"; + gpios = <&gpio0 22 1>; + }; + inet { + label = "DVAG3810BN::internet"; + gpios = <&gpio0 23 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/f5d7633.dts b/target/linux/brcm63xx/dts/f5d7633.dts new file mode 100644 index 0000000..519df1e --- /dev/null +++ b/target/linux/brcm63xx/dts/f5d7633.dts @@ -0,0 +1,72 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Belkin F5D7633"; + compatible = "belkin,f5d7633", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 6 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348GW-10:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96348GW-10:green:stop"; + gpios = <&gpio0 1 1>; + }; + adsl_fail_green { + label = "96348GW-10:green:adsl-fail"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "96348GW-10:green:ppp"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96348GW-10:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0x3c0000>; + }; + + nvram@3e0000 { + label = "nvram"; + reg = <0x3e0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/fast2404.dts b/target/linux/brcm63xx/dts/fast2404.dts new file mode 100644 index 0000000..5309703 --- /dev/null +++ b/target/linux/brcm63xx/dts/fast2404.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Sagem F@ST2404"; + compatible = "sagem,f@st2404", "brcm,bcm6348"; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/fast2504n.dts b/target/linux/brcm63xx/dts/fast2504n.dts new file mode 100644 index 0000000..cf453af --- /dev/null +++ b/target/linux/brcm63xx/dts/fast2504n.dts @@ -0,0 +1,59 @@ +/dts-v1/; + +#include "bcm6362.dtsi" + +#include + +/ { + model = "Sagem F@ST2504n"; + compatible = "sagem,f@st2504n", "brcm,bcm6362"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 24 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio0 25 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_orange { + label = "fast2504n:orange:power"; + gpios = <&gpio0 2 1>; + }; + power_green { + label = "fast2504n:green:power"; + gpios = <&gpio0 10 1>; + default-state = "on"; + }; + inet_red { + label = "fast2504n:red:internet"; + gpios = <&gpio0 26 1>; + }; + ok_green { + label = "fast2504n:green:ok"; + gpios = <&gpio0 28 1>; + }; + ok_orange { + label = "fast2504n:orange:ok"; + gpios = <&gpio0 29 1>; + }; + wlan_orangee { + label = "fast2504n:orange:wlan"; + gpios = <&gpio0 30 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/fast2604.dts b/target/linux/brcm63xx/dts/fast2604.dts new file mode 100644 index 0000000..c6b71d1 --- /dev/null +++ b/target/linux/brcm63xx/dts/fast2604.dts @@ -0,0 +1,68 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Sagem F@ST2604"; + compatible = "sagem,f@st2604", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "F@ST2604:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + power_red { + label = "F@ST2604:red:power"; + gpios = <&gpio0 1 1>; + }; + inet_red { + label = "F@ST2604:red:inet"; + gpios = <&gpio0 4 1>; + }; + wps_green { + label = "F@ST2604:green:wps"; + gpios = <&gpio0 5 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/fast2704n.dts b/target/linux/brcm63xx/dts/fast2704n.dts new file mode 100644 index 0000000..232d4d1 --- /dev/null +++ b/target/linux/brcm63xx/dts/fast2704n.dts @@ -0,0 +1,84 @@ +/dts-v1/; + +#include "bcm6318.dtsi" + +#include + +/ { + model = "Sagem F@ST2704N"; + compatible = "sagem,f@st2704n", "brcm,bcm6318"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wlan { + label = "wlan"; + gpios = <&gpio0 1 0>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wps_green { + label = "F@ST2704N:green:wps"; + gpios = <&gpio0 2 1>; + }; + lan1_green { + label = "F@ST2704N:green:lan1"; + gpios = <&gpio0 4 1>; + }; + lan2_green { + label = "F@ST2704N:green:lan2"; + gpios = <&gpio0 5 1>; + }; + lan3_green { + label = "F@ST2704N:green:lan3"; + gpios = <&gpio0 6 1>; + }; + lan4_green { + label = "F@ST2704N:green:lan4"; + gpios = <&gpio0 7 1>; + }; + inet_green { + label = "F@ST2704N:green:inet"; + gpios = <&gpio0 8 1>; + }; + inet_red { + label = "F@ST2704N:red:inet"; + gpios = <&gpio0 9 1>; + }; + dsl_green { + label = "F@ST2704N:green:dsl"; + gpios = <&gpio0 10 1>; + }; + power_red { + label = "F@ST2704N:red:power"; + gpios = <&gpio0 11 1>; + }; + power_green { + label = "F@ST2704N:green:power"; + gpios = <&gpio1 15 1>; + default-state = "on"; + }; + usb_green { + label = "F@ST2704N:green:usb"; + gpios = <&gpio1 17 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/fast2704v2.dts b/target/linux/brcm63xx/dts/fast2704v2.dts new file mode 100644 index 0000000..3f56827 --- /dev/null +++ b/target/linux/brcm63xx/dts/fast2704v2.dts @@ -0,0 +1,68 @@ +/dts-v1/; + +#include "bcm6328.dtsi" + +#include + +/ { + model = "Sagem F@ST2704V2"; + compatible = "sagem,f@st2704v2", "brcm,bcm6328"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + rfkill { + label = "rfkill"; + gpios = <&gpio0 15 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio0 23 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio0 24 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + usb_green { + label = "F@ST2704V2:green:usb"; + gpios = <&gpio0 1 1>; + }; + inet_red { + label = "F@ST2704V2:red:inet"; + gpios = <&gpio0 2 1>; + }; + dsl_green { + label = "F@ST2704V2:green:dsl"; + gpios = <&gpio0 3 1>; + }; + power_green { + label = "F@ST2704V2:green:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + power_red { + label = "F@ST2704V2:red:power"; + gpios = <&gpio0 5 1>; + }; + wps_green { + label = "F@ST2704V2:green:wps"; + gpios = <&gpio0 10 1>; + }; + inet_green { + label = "F@ST2704V2:green:inet"; + gpios = <&gpio0 11 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/gw6000.dts b/target/linux/brcm63xx/dts/gw6000.dts new file mode 100644 index 0000000..69424e0 --- /dev/null +++ b/target/linux/brcm63xx/dts/gw6000.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "TECOM GW6000"; + compatible = "tecom,gw6000", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 4 1>; + linux,code = ; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/gw6200.dts b/target/linux/brcm63xx/dts/gw6200.dts new file mode 100644 index 0000000..2bd4381 --- /dev/null +++ b/target/linux/brcm63xx/dts/gw6200.dts @@ -0,0 +1,45 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "TECOM GW6200"; + compatible = "tecom,gw6200", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 4 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + line1_green { + label = "GW6200:green:line1"; + gpios = <&gpio0 4 1>; + }; + line2_green { + label = "GW6200:green:line2"; + gpios = <&gpio0 5 1>; + }; + line3_green { + label = "GW6200:green:line3"; + gpios = <&gpio0 6 1>; + }; + tel_green { + label = "GW6200:green:tel"; + gpios = <&gpio0 7 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/hg520v.dts b/target/linux/brcm63xx/dts/hg520v.dts new file mode 100644 index 0000000..7b6b36f --- /dev/null +++ b/target/linux/brcm63xx/dts/hg520v.dts @@ -0,0 +1,55 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Huawei EchoLife HG520v"; + compatible = "huawei,hg520v", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "HW520:green:net"; + gpios = <&gpio1 0 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/hg553.dts b/target/linux/brcm63xx/dts/hg553.dts new file mode 100644 index 0000000..b23ceaa --- /dev/null +++ b/target/linux/brcm63xx/dts/hg553.dts @@ -0,0 +1,94 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Huawei EchoLife HG553"; + compatible = "huawei,hg553", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + rfkill { + label = "rfkill"; + gpios = <&gpio0 9 1>; + linux,code = ; + }; + + reset { + label = "reset"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "HW553:blue:power"; + gpios = <&gpio0 4 1>; + default-state = "on"; + }; + power_red { + label = "HW553:red:power"; + gpios = <&gpio0 5 1>; + }; + hspa_red { + label = "HW553:red:hspa"; + gpios = <&gpio0 12 1>; + }; + hspa_blue { + label = "HW553:blue:hspa"; + gpios = <&gpio0 13 1>; + }; + lan_red { + label = "HW553:red:lan"; + gpios = <&gpio0 22 1>; + }; + lan_blue { + label = "HW553:blue:lan"; + gpios = <&gpio0 23 1>; + }; + wifi_red { + label = "HW553:red:wifi"; + gpios = <&gpio0 25 1>; + }; + dsl_red { + label = "HW553:red:adsl"; + gpios = <&gpio1 2 1>; + }; + dsl_blue { + label = "HW553:blue:adsl"; + gpios = <&gpio1 3 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0xfc0000>; + }; + + nvram@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/hg556a-a.dts b/target/linux/brcm63xx/dts/hg556a-a.dts new file mode 100644 index 0000000..98e0a83 --- /dev/null +++ b/target/linux/brcm63xx/dts/hg556a-a.dts @@ -0,0 +1,126 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Huawei EchoLife HG556a (version A)"; + compatible = "huawei,hg556a-a", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + help { + label = "help"; + gpios = <&gpio0 8 1>; + linux,code = ; + }; + wlan { + label = "wlan"; + gpios = <&gpio0 9 1>; + linux,code = ; + }; + restart { + label = "restart"; + gpios = <&gpio0 10 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio0 11 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + message_red { + label = "HW556:red:message"; + gpios = <&gpio0 0 1>; + }; + hspa_red { + label = "HW556:red:hspa"; + gpios = <&gpio0 1 1>; + }; + dsl_red { + label = "HW556:red:dsl"; + gpios = <&gpio0 2 1>; + }; + power_red { + label = "HW556:red:power"; + gpios = <&gpio0 3 1>; + default-state = "on"; + }; + all_red { + label = "HW556:red:all"; + gpios = <&gpio0 6 1>; + default-state = "on"; + }; + lan1_green { + label = "HW556:green:lan1"; + gpios = <&gpio0 12 1>; + }; + lan1_red { + label = "HW556:red:lan1"; + gpios = <&gpio0 13 1>; + }; + lan2_green { + label = "HW556:green:lan2"; + gpios = <&gpio0 15 1>; + }; + lan2_red { + label = "HW556:red:lan2"; + gpios = <&gpio0 22 1>; + }; + lan3_green { + label = "HW556:green:lan3"; + gpios = <&gpio0 23 1>; + }; + lan3_red { + label = "HW556:red:lan3"; + gpios = <&gpio0 26 1>; + }; + lan4_green { + label = "HW556:green:lan4"; + gpios = <&gpio0 27 1>; + }; + lan4_red { + label = "HW556:red:lan4"; + gpios = <&gpio0 28 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0xec0000>; + }; + + cal_data@ee0000 { + label = "cal_data"; + reg = <0xee0000 0x100000>; + read-only; + }; + + nvram@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/hg556a-b.dts b/target/linux/brcm63xx/dts/hg556a-b.dts new file mode 100644 index 0000000..8a19856 --- /dev/null +++ b/target/linux/brcm63xx/dts/hg556a-b.dts @@ -0,0 +1,126 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Huawei EchoLife HG556a (version B)"; + compatible = "huawei,hg556a-b", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + help { + label = "help"; + gpios = <&gpio0 8 1>; + linux,code = ; + }; + wlan { + label = "wlan"; + gpios = <&gpio0 9 1>; + linux,code = ; + }; + restart { + label = "restart"; + gpios = <&gpio0 10 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio0 11 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + message_red { + label = "HW556:red:message"; + gpios = <&gpio0 0 1>; + }; + hspa_red { + label = "HW556:red:hspa"; + gpios = <&gpio0 1 1>; + }; + dsl_red { + label = "HW556:red:dsl"; + gpios = <&gpio0 2 1>; + }; + power_red { + label = "HW556:red:power"; + gpios = <&gpio0 3 1>; + default-state = "on"; + }; + all_red { + label = "HW556:red:all"; + gpios = <&gpio0 6 1>; + default-state = "on"; + }; + lan1_green { + label = "HW556:green:lan1"; + gpios = <&gpio0 12 1>; + }; + lan1_red { + label = "HW556:red:lan1"; + gpios = <&gpio0 13 1>; + }; + lan2_green { + label = "HW556:green:lan2"; + gpios = <&gpio0 15 1>; + }; + lan2_red { + label = "HW556:red:lan2"; + gpios = <&gpio0 22 1>; + }; + lan3_green { + label = "HW556:green:lan3"; + gpios = <&gpio0 23 1>; + }; + lan3_red { + label = "HW556:red:lan3"; + gpios = <&gpio0 26 1>; + }; + lan4_green { + label = "HW556:green:lan4"; + gpios = <&gpio0 27 1>; + }; + lan4_red { + label = "HW556:red:lan4"; + gpios = <&gpio0 28 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0xec0000>; + }; + + cal_data@ee0000 { + label = "cal_data"; + reg = <0xee0000 0x100000>; + read-only; + }; + + nvram@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/hg556a-c.dts b/target/linux/brcm63xx/dts/hg556a-c.dts new file mode 100644 index 0000000..9798091 --- /dev/null +++ b/target/linux/brcm63xx/dts/hg556a-c.dts @@ -0,0 +1,121 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Huawei EchoLife HG556a (version C)"; + compatible = "huawei,hg556a-c", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + help { + label = "help"; + gpios = <&gpio0 8 1>; + linux,code = ; + }; + wlan { + label = "wlan"; + gpios = <&gpio0 9 1>; + linux,code = ; + }; + restart { + label = "restart"; + gpios = <&gpio0 10 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio0 11 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + lan1_green { + label = "HW556:green:lan1"; + gpios = <&gpio0 0 1>; + }; + lan2_green { + label = "HW556:green:lan2"; + gpios = <&gpio0 1 1>; + }; + dsl_red { + label = "HW556:red:dsl"; + gpios = <&gpio0 2 1>; + }; + power_red { + label = "HW556:red:power"; + gpios = <&gpio0 3 1>; + default-state = "on"; + }; + message_red { + label = "HW556:red:message"; + gpios = <&gpio0 12 1>; + }; + lan1_red { + label = "HW556:red:lan1"; + gpios = <&gpio0 13 1>; + }; + hspa_red { + label = "HW556:red:hspa"; + gpios = <&gpio0 15 1>; + }; + lan2_red { + label = "HW556:red:lan2"; + gpios = <&gpio0 22 1>; + }; + lan3_green { + label = "HW556:green:lan3"; + gpios = <&gpio0 23 1>; + }; + lan3_red { + label = "HW556:red:lan3"; + gpios = <&gpio0 26 1>; + }; + lan4_green { + label = "HW556:green:lan4"; + gpios = <&gpio0 27 1>; + }; + lan4_red { + label = "HW556:red:lan4"; + gpios = <&gpio0 28 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0xec0000>; + }; + + cal_data@ee0000 { + label = "cal_data"; + reg = <0xee0000 0x100000>; + read-only; + }; + + nvram@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/hg655b.dts b/target/linux/brcm63xx/dts/hg655b.dts new file mode 100644 index 0000000..b7722df --- /dev/null +++ b/target/linux/brcm63xx/dts/hg655b.dts @@ -0,0 +1,112 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Huawei HG655b"; + compatible = "huawei,hg655b", "brcm,bcm6368"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wps { + label = "wps"; + gpios = <&gpio0 12 1>; + linux,code = ; + }; + wlan { + label = "wlan"; + gpios = <&gpio0 23 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + dsl_green { + label = "HW65x:green:dsl"; + gpios = <&gpio0 2 1>; + }; + internet_green { + label = "HW65x:green:internet"; + gpios = <&gpio0 5 1>; + }; + lan1_green { + label = "HW65x:green:lan1"; + gpios = <&gpio0 6 1>; + }; + lan2_green { + label = "HW65x:green:lan2"; + gpios = <&gpio0 7 1>; + }; + lan3_green { + label = "HW65x:green:lan3"; + gpios = <&gpio0 8 1>; + }; + lan4_green { + label = "HW65x:green:lan4"; + gpios = <&gpio0 9 1>; + }; + usb_green { + label = "HW65x:green:usb"; + gpios = <&gpio0 14 1>; + }; + power_green { + label = "HW65x:green:power"; + gpios = <&gpio0 22 1>; + default-state = "on"; + }; + voip_green { + label = "HW65x:green:voip"; + gpios = <&gpio0 25 1>; + }; + wps_green { + label = "HW65x:green:wps"; + gpios = <&gpio0 27 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0x770000>; + }; + + board_data@790000 { + label = "board_data"; + reg = <0x790000 0x030000>; + }; + + cal_data@7c0000 { + label = "cal_data"; + reg = <0x7c0000 0x020000>; + read-only; + }; + + nvram@7d0000 { + label = "nvram"; + reg = <0x7e0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/homehub2a.dts b/target/linux/brcm63xx/dts/homehub2a.dts new file mode 100644 index 0000000..9e7ce2f --- /dev/null +++ b/target/linux/brcm63xx/dts/homehub2a.dts @@ -0,0 +1,142 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "BT Home Hub 2.0 Type A"; + compatible = "thomson,homehub2a", "brcm,bcm6358"; + + spi-gpio { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-gpio"; + + gpio-mosi = <&gpio0 7 0>; + gpio-sck = <&gpio0 6 0>; + cs-gpios = <&gpio0 5 0>; + num-chipselects = <1>; + + hc595: gpio-spi-controller@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <2>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + phone { + label = "phone"; + gpios = <&gpio0 1 1>; + linux,code = <169>; + }; + reset { + label = "reset"; + gpios = <&gpio0 9 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio0 11 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_red { + label = "HOMEHUB2A:red:power"; + gpios = <&hc595 0 1>; + }; + power_green { + label = "HOMEHUB2A:green:power"; + gpios = <&hc595 1 1>; + default-state = "on"; + }; + power_blue { + label = "HOMEHUB2A:blue:power"; + gpios = <&hc595 2 1>; + }; + broadband_red { + label = "HOMEHUB2A:red:broadband"; + gpios = <&hc595 3 1>; + }; + broadband_green { + label = "HOMEHUB2A:green:broadband"; + gpios = <&hc595 4 1>; + }; + broadband_blue { + label = "HOMEHUB2A:blue:broadband"; + gpios = <&hc595 5 1>; + }; + wireless_red { + label = "HOMEHUB2A:red:wireless"; + gpios = <&hc595 6 1>; + }; + wireless_green { + label = "HOMEHUB2A:green:wireless"; + gpios = <&hc595 7 1>; + }; + wireless_blue { + label = "HOMEHUB2A:blue:wireless"; + gpios = <&hc595 8 1>; + }; + phone_red { + label = "HOMEHUB2A:red:phone"; + gpios = <&hc595 9 1>; + }; + phone_green { + label = "HOMEHUB2A:green:phone"; + gpios = <&hc595 10 1>; + }; + phone_blue { + label = "HOMEHUB2A:blue:phone"; + gpios = <&hc595 11 1>; + }; + upgrading_red { + label = "HOMEHUB2A:red:upgrading"; + gpios = <&hc595 12 1>; + }; + upgrading_green { + label = "HOMEHUB2A:green:upgrading"; + gpios = <&hc595 13 1>; + }; + upgrading_blue { + label = "HOMEHUB2A:blue:upgrading"; + gpios = <&hc595 14 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0xfc0000>; + }; + + nvram@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/livebox-blue-5g.dts b/target/linux/brcm63xx/dts/livebox-blue-5g.dts new file mode 100644 index 0000000..bc3d403 --- /dev/null +++ b/target/linux/brcm63xx/dts/livebox-blue-5g.dts @@ -0,0 +1,68 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Inventel Livebox 1"; + compatible = "inventel,livebox-blue-5g", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + + poll-interval = <20>; + debounce-interval = <60>; + + button1 { + label = "BTN_1"; + gpios = <&gpio1 4 1>; + linux,code = ; + }; + + button2 { + label = "BTN_2"; + gpios = <&gpio0 7 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red_adsl_fail { + label = "Livebox-blue-5g:red:adsl-fail"; + gpios = <&gpio0 0 0>; + default-state = "on"; + }; + + red_adsl { + label = "Livebox-blue-5g:red:adsl-fail"; + gpios = <&gpio0 1 0>; + }; + + red_traffic { + label = "Livebox-blue-5g:red:adsl-fail"; + gpios = <&gpio0 2 0>; + }; + + red_phone { + label = "Livebox-blue-5g:red:adsl-fail"; + gpios = <&gpio0 3 0>; + }; + + red_wifi { + label = "Livebox-blue-5g:red:adsl-fail"; + gpios = <&gpio0 4 0>; + }; + }; +}; + +&pflash { + reg = <0x1e400000 0x800000>; + status = "ok"; + + linux,part-probe = "redboot"; +}; diff --git a/target/linux/brcm63xx/dts/magic.dts b/target/linux/brcm63xx/dts/magic.dts new file mode 100644 index 0000000..b923ee8 --- /dev/null +++ b/target/linux/brcm63xx/dts/magic.dts @@ -0,0 +1,72 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Alice W-Gate"; + compatible = "telsey,magic", "brcm,bcm6348"; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "MAGIC:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + + stop { + label = "MAGIC:green:stop"; + gpios = <&gpio0 1 1>; + }; + + hpna { + label = "MAGIC:green:hpna"; + gpios = <&gpio0 4 1>; + }; + + status { + label = "MAGIC:green:adsl"; + gpios = <&gpio0 5 1>; + }; + + voip { + label = "MAGIC:green:voip"; + gpios = <&gpio0 22 1>; + }; + + wifi { + label = "MAGIC:green:wifi"; + gpios = <&gpio0 28 0>; + }; + + usb { + label = "MAGIC:green:usb"; + gpios = <&gpio1 3 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/nb4-fxc-r1.dts b/target/linux/brcm63xx/dts/nb4-fxc-r1.dts new file mode 100644 index 0000000..65f26c7 --- /dev/null +++ b/target/linux/brcm63xx/dts/nb4-fxc-r1.dts @@ -0,0 +1,100 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "SFR Neuf Box 4 (Foxconn)"; + compatible = "sfr,nb4-fxc-r1", "brcm,bcm6358"; + + spi-gpio { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-gpio"; + + gpio-mosi = <&gpio0 7 0>; + gpio-sck = <&gpio0 6 0>; + num-chipselects = <0>; + + hc595: gpio-spi-controller@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + service { + label = "service"; + gpios = <&gpio0 27 1>; + linux,code = ; + }; + clip { + label = "clip"; + gpios = <&gpio0 31 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + traffic_white { + label = "NB4-FXC-r1:white:traffic"; + gpios = <&gpio0 2 0>; + }; + service_blue { + label = "NB4-FXC-r1:blue:service"; + gpios = <&gpio0 4 0>; + }; + wifi_white { + label = "NB4-FXC-r1:white:wifi"; + gpios = <&gpio0 15 0>; + }; + service_red { + label = "NB4-FXC-r1:red:service"; + gpios = <&gpio0 29 0>; + }; + service_green { + label = "NB4-FXC-r1:green:service"; + gpios = <&gpio0 30 0>; + }; + alarm_white { + label = "NB4-FXC-r1:white:alarm"; + gpios = <&hc595 0 1>; + }; + tv_white { + label = "NB4-FXC-r1:white:tv"; + gpios = <&hc595 2 1>; + }; + tel_white { + label = "NB4-FXC-r1:white:tel"; + gpios = <&hc595 3 1>; + }; + adsl_white { + label = "NB4-FXC-r0:white:adsl"; + gpios = <&hc595 4 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/nb4-ser-r0.dts b/target/linux/brcm63xx/dts/nb4-ser-r0.dts new file mode 100644 index 0000000..1a48b72 --- /dev/null +++ b/target/linux/brcm63xx/dts/nb4-ser-r0.dts @@ -0,0 +1,100 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "SFR Neuf Box 4 (Sercomm)"; + compatible = "sfr,nb4-ser-r0", "brcm,bcm6358"; + + spi-gpio { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-gpio"; + + gpio-mosi = <&gpio0 7 0>; + gpio-sck = <&gpio0 6 0>; + num-chipselects = <0>; + + hc595: gpio-spi-controller@0 { + compatible = "fairchild,74hc595"; + reg = <0>; + registers-number = <1>; + spi-max-frequency = <100000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + service { + label = "service"; + gpios = <&gpio0 27 1>; + linux,code = ; + }; + clip { + label = "clip"; + gpios = <&gpio0 31 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + traffic_white { + label = "NB4-SER-r0:white:traffic"; + gpios = <&gpio0 2 1>; + }; + service_blue { + label = "NB4-SER-r0:blue:service"; + gpios = <&gpio0 4 1>; + }; + wifi_white { + label = "NB4-SER-r0:white:wifi"; + gpios = <&gpio0 15 1>; + }; + service_red { + label = "NB4-SER-r0:red:service"; + gpios = <&gpio0 29 1>; + }; + service_green { + label = "NB4-SER-r0:green:service"; + gpios = <&gpio0 30 1>; + }; + alarm_white { + label = "NB4-SER-r0:white:alarm"; + gpios = <&hc595 0 1>; + }; + tv_white { + label = "NB4-SER-r0:white:tv"; + gpios = <&hc595 2 1>; + }; + tel_white { + label = "NB4-SER-r0:white:tel"; + gpios = <&hc595 3 1>; + }; + adsl_white { + label = "NB4-SER-r0:white:adsl"; + gpios = <&hc595 4 1>; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/nb6-ser-r0.dts b/target/linux/brcm63xx/dts/nb6-ser-r0.dts new file mode 100644 index 0000000..c23ff90 --- /dev/null +++ b/target/linux/brcm63xx/dts/nb6-ser-r0.dts @@ -0,0 +1,39 @@ +/dts-v1/; + +#include "bcm6362.dtsi" + +#include + +/ { + model = "SFR neufbox 6 (Sercomm)"; + compatible = "sfr,nb6-ser-r0", "brcm,bcm6362"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + service { + label = "service"; + gpios = <&gpio0 10 1>; + linux,code = ; + }; + wlan { + label = "wlan"; + gpios = <&gpio0 12 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio0 24 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio0 25 1>; + linux,code = ; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/p870hw-51a-v2.dts b/target/linux/brcm63xx/dts/p870hw-51a-v2.dts new file mode 100644 index 0000000..606b896 --- /dev/null +++ b/target/linux/brcm63xx/dts/p870hw-51a-v2.dts @@ -0,0 +1,77 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Zyxel P870HW-51a v2"; + compatible = "zyxel,p870hw-51a-v2", "brcm,bcm6368"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio1 3 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "P870HW-51a:green:power"; + gpios = <&gpio0 0 0>; + default-state = "on"; + }; + dsl_green { + label = "P870HW-51a:green:dsl"; + gpios = <&gpio0 2 1>; + }; + inet_green { + label = "P870HW-51a:green:inet"; + gpios = <&gpio0 22 1>; + }; + wps_orange { + label = "P870HW-51a:orange:wps"; + gpios = <&gpio0 24 1>; + }; + inet_red { + label = "P870HW-51a:red:inet"; + gpios = <&gpio1 1 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/rg100a.dts b/target/linux/brcm63xx/dts/rg100a.dts new file mode 100644 index 0000000..503ae57 --- /dev/null +++ b/target/linux/brcm63xx/dts/rg100a.dts @@ -0,0 +1,54 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "Alcatel RG100A"; + compatible = "alcatel,rg100a", "brcm,bcm6358"; + + gpio-leds { + compatible = "gpio-leds"; + + stop_green { + label = "96358VW2:green:stop"; + gpios = <&gpio0 4 1>; + }; + power_green { + label = "96358VW2:green:power"; + gpios = <&gpio0 5 1>; + default-state = "on"; + }; + adsl_green { + label = "96358VW2:green:adsl"; + gpios = <&gpio0 22 1>; + }; + ppp_fail_green { + label = "96358VW2:green:ppp-fail"; + gpios = <&gpio0 23 0>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0xfc0000>; + }; + + nvram@fe0000 { + label = "nvram"; + reg = <0xfe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/rta1025w.dts b/target/linux/brcm63xx/dts/rta1025w.dts new file mode 100644 index 0000000..5d0dce0 --- /dev/null +++ b/target/linux/brcm63xx/dts/rta1025w.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "Dynalink RTA1025W"; + compatible = "dynalink,rta1025w", "brcm,bcm6348"; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/rta1320.dts b/target/linux/brcm63xx/dts/rta1320.dts new file mode 100644 index 0000000..c8c2827 --- /dev/null +++ b/target/linux/brcm63xx/dts/rta1320.dts @@ -0,0 +1,54 @@ +/dts-v1/; + +#include "bcm6338.dtsi" + +#include + +/ { + model = "Dynalink RTA1320"; + compatible = "dynalink,rta1320", "brcm,bcm6338"; + + gpio-leds { + compatible = "gpio-leds"; + + green_power { + label = "RTA1320_16M:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + green_stop { + label = "RTA1320_16M:green:stop"; + gpios = <&gpio0 1 1>; + }; + green_adsl { + label = "RTA1320_16M:green:adsl"; + gpios = <&gpio0 3 1>; + }; + green_ppp { + label = "RTA1320_16M:green:ppp"; + gpios = <&gpio0 4 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/rta770bw.dts b/target/linux/brcm63xx/dts/rta770bw.dts new file mode 100644 index 0000000..d24334e --- /dev/null +++ b/target/linux/brcm63xx/dts/rta770bw.dts @@ -0,0 +1,70 @@ +/dts-v1/; + +#include "bcm6345.dtsi" + +#include + +/ { + model = "Siemens Gigaset SE515"; + compatible = "dynalink,rta770bw", "brcm,bcm6345"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 13 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + usb { + label = "RTA770BW:green:usb"; + gpios = <&gpio0 7 1>; + }; + + adsl { + label = "RTA770BW:green:adsl"; + gpios = <&gpio0 8 0>; + }; + + diag { + label = "RTA770BW:green:diag"; + gpios = <&gpio0 10 1>; + }; + + wlan { + label = "RTA770BW:green:wlan"; + gpios = <&gpio0 11 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/rta770w.dts b/target/linux/brcm63xx/dts/rta770w.dts new file mode 100644 index 0000000..2c2d6fb --- /dev/null +++ b/target/linux/brcm63xx/dts/rta770w.dts @@ -0,0 +1,70 @@ +/dts-v1/; + +#include "bcm6345.dtsi" + +#include + +/ { + model = "Dynalink RTA770W"; + compatible = "dynalink,rta770w", "brcm,bcm6345"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 13 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + usb { + label = "RTA770W:green:usb"; + gpios = <&gpio0 7 1>; + }; + + adsl { + label = "RTA770W:green:adsl"; + gpios = <&gpio0 8 0>; + }; + + diag { + label = "RTA770W:green:diag"; + gpios = <&gpio0 10 1>; + }; + + wlan { + label = "RTA770W:green:wlan"; + gpios = <&gpio0 11 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/spw303v.dts b/target/linux/brcm63xx/dts/spw303v.dts new file mode 100644 index 0000000..2dcf752 --- /dev/null +++ b/target/linux/brcm63xx/dts/spw303v.dts @@ -0,0 +1,81 @@ +/dts-v1/; + +#include "bcm6358.dtsi" + +#include + +/ { + model = "T-Com Speedport W303 V"; + compatible = "t-com,spw303v", "brcm,bcm6358"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 11 0>; + linux,code = ; + }; + ses { + label = "ses"; + gpios = <&gpio1 5 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + ses_green { + label = "spw303v:green:ses"; + gpios = <&gpio0 0 1>; + }; + power_adsl_red { + label = "spw303v:red:power+adsl"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "spw303v:green:ppp"; + gpios = <&gpio0 5 1>; + }; + power_adsl_green { + label = "spw303v:green:power+adsl"; + gpios = <&gpio0 22 1>; + default-state = "on"; + }; + voip_green { + label = "spw303v:green:voip"; + gpios = <&gpio0 27 1>; + }; + pots_green { + label = "spw303v:green:pots"; + gpios = <&gpio0 31 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/spw500v.dts b/target/linux/brcm63xx/dts/spw500v.dts new file mode 100644 index 0000000..2fcf958 --- /dev/null +++ b/target/linux/brcm63xx/dts/spw500v.dts @@ -0,0 +1,72 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "T-Com Speedport W500 V"; + compatible = "t-com,spw500v", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "SPW500V:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + power_red { + label = "SPW500V:red:power"; + gpios = <&gpio0 1 1>; + }; + ppp_green { + label = "SPW500V:green:ppp"; + gpios = <&gpio0 3 1>; + }; + pstn_green { + label = "SPW500V:green:pstn"; + gpios = <&gpio0 28 1>; + }; + voip_green { + label = "SPW500V:green:voip"; + gpios = <&gpio1 0 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/td-w8900gb.dts b/target/linux/brcm63xx/dts/td-w8900gb.dts new file mode 100644 index 0000000..a1480f6 --- /dev/null +++ b/target/linux/brcm63xx/dts/td-w8900gb.dts @@ -0,0 +1,72 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "TP-Link TD-W8900GB"; + compatible = "tp-link,td-w8900gb", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "96348GW-11:green:power"; + gpios = <&gpio0 0 1>; + default-state = "on"; + }; + stop_green { + label = "96348GW-11:green:stop"; + gpios = <&gpio0 1 1>; + }; + adsl_fail_green { + label = "96348GW-11:green:adsl-fail"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "96348GW-11:green:ppp"; + gpios = <&gpio0 3 1>; + }; + ppp_fail_green { + label = "96348GW-11:green:ppp-fail"; + gpios = <&gpio0 4 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x020000 0x3d0000>; + }; + + nvram@3e0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/usr9108.dts b/target/linux/brcm63xx/dts/usr9108.dts new file mode 100644 index 0000000..64a5ab3 --- /dev/null +++ b/target/linux/brcm63xx/dts/usr9108.dts @@ -0,0 +1,45 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "USRobotics 9108"; + compatible = "usr,9108", "brcm,bcm6348"; + + gpio-leds { + compatible = "gpio-leds"; + + usb { + label = "96348GW-A::usb"; + gpios = <&gpio0 0 1>; + }; + dsl { + label = "96348GW-A::adsl"; + gpios = <&gpio0 3 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/v2110.dts b/target/linux/brcm63xx/dts/v2110.dts new file mode 100644 index 0000000..2605339 --- /dev/null +++ b/target/linux/brcm63xx/dts/v2110.dts @@ -0,0 +1,71 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "BT Voyager 2110"; + compatible = "bt,v2110", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 1 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "V2110:green:power"; + gpios = <&gpio0 0 1>; + }; + power_red { + label = "V2110:red:power"; + gpios = <&gpio0 1 1>; + }; + adsl_green { + label = "V2110:green:adsl"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "V2110:green:ppp"; + gpios = <&gpio0 3 1>; + }; + wireless_green { + label = "V2110:green:wireless"; + gpios = <&gpio0 6 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/v2500v-bb.dts b/target/linux/brcm63xx/dts/v2500v-bb.dts new file mode 100644 index 0000000..5a9223f --- /dev/null +++ b/target/linux/brcm63xx/dts/v2500v-bb.dts @@ -0,0 +1,71 @@ +/dts-v1/; + +#include "bcm6348.dtsi" + +#include + +/ { + model = "BT Voyager V2500V"; + compatible = "bt,v2500v-bb", "brcm,bcm6348"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio0 31 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_green { + label = "V2500V_BB:green:power"; + gpios = <&gpio0 0 1>; + }; + power_red { + label = "V2500V_BB:red:power"; + gpios = <&gpio0 1 1>; + }; + adsl_green { + label = "V2500V_BB:green:adsl"; + gpios = <&gpio0 2 1>; + }; + ppp_green { + label = "V2500V_BB:green:ppp"; + gpios = <&gpio0 3 1>; + }; + wireless_green { + label = "V2500V_BB:green:wireless"; + gpios = <&gpio0 6 1>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x3e0000>; + }; + + nvram@3f0000 { + label = "nvram"; + reg = <0x3f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/vg50.dts b/target/linux/brcm63xx/dts/vg50.dts new file mode 100644 index 0000000..f95fa95 --- /dev/null +++ b/target/linux/brcm63xx/dts/vg50.dts @@ -0,0 +1,30 @@ +/dts-v1/; + +#include "bcm63268.dtsi" + +#include + +/ { + model = "Inteno VG50"; + compatible = "inteno,vg50", "brcm,bcm63268"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 0 0>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&gpio1 2 0>; + linux,code = ; + }; + }; +}; diff --git a/target/linux/brcm63xx/dts/vr-3025u.dts b/target/linux/brcm63xx/dts/vr-3025u.dts new file mode 100644 index 0000000..b24b590 --- /dev/null +++ b/target/linux/brcm63xx/dts/vr-3025u.dts @@ -0,0 +1,88 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Comtrend VR-3025u"; + compatible = "comtrend,vr-3025u", "brcm,bcm6368"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + dsl_green { + label = "VR-3025u:green:dsl"; + gpios = <&gpio0 2 1>; + }; + inet_green { + label = "VR-3025u:green:inet"; + gpios = <&gpio0 5 0>; + }; + lan1_green { + label = "VR-3025u:green:lan1"; + gpios = <&gpio0 6 1>; + }; + lan2_green { + label = "VR-3025u:green:lan2"; + gpios = <&gpio0 7 1>; + }; + lan3_green { + label = "VR-3025u:green:lan3"; + gpios = <&gpio0 8 1>; + }; + lan4_green { + label = "VR-3025u:green:lan4"; + gpios = <&gpio0 9 1>; + }; + power_green { + label = "VR-3025u:green:power"; + gpios = <&gpio0 22 0>; + default-state = "on"; + }; + power_red { + label = "VR-3025u:red:power"; + gpios = <&gpio0 24 0>; + }; + inet_red { + label = "VR-3025u:red:inet"; + gpios = <&gpio0 31 0>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x0000000 0x0020000>; + read-only; + }; + + linux@20000 { + label = "linux"; + reg = <0x0020000 0x1fc0000>; + }; + + nvram@1fe0000 { + label = "nvram"; + reg = <0x1fe0000 0x020000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/vr-3025un.dts b/target/linux/brcm63xx/dts/vr-3025un.dts new file mode 100644 index 0000000..124045f --- /dev/null +++ b/target/linux/brcm63xx/dts/vr-3025un.dts @@ -0,0 +1,88 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Comtrend VR-3025un"; + compatible = "comtrend,vr-3025un", "brcm,bcm6368"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + dsl_green { + label = "VR-3025un:green:dsl"; + gpios = <&gpio0 2 1>; + }; + inet_green { + label = "VR-3025un:green:inet"; + gpios = <&gpio0 5 0>; + }; + lan1_green { + label = "VR-3025un:green:lan1"; + gpios = <&gpio0 6 1>; + }; + lan2_green { + label = "VR-3025un:green:lan2"; + gpios = <&gpio0 7 1>; + }; + lan3_green { + label = "VR-3025un:green:lan3"; + gpios = <&gpio0 8 1>; + }; + iptv_green { + label = "VR-3025un:green:iptv"; + gpios = <&gpio0 9 1>; + }; + power_green { + label = "VR-3025un:green:power"; + gpios = <&gpio0 22 0>; + default-state = "on"; + }; + power_red { + label = "VR-3025un:red:power"; + gpios = <&gpio0 24 0>; + }; + inet_red { + label = "VR-3025un:red:inet"; + gpios = <&gpio0 31 0>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/vr-3026e.dts b/target/linux/brcm63xx/dts/vr-3026e.dts new file mode 100644 index 0000000..49790e2 --- /dev/null +++ b/target/linux/brcm63xx/dts/vr-3026e.dts @@ -0,0 +1,88 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Comtrend VR-3026e"; + compatible = "comtrend,vr-3026e", "brcm,bcm6368"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + dsl_green { + label = "VR-3026e:green:dsl"; + gpios = <&gpio0 2 1>; + }; + inet_green { + label = "VR-3026e:green:inet"; + gpios = <&gpio0 5 0>; + }; + lan1_green { + label = "VR-3026e:green:lan1"; + gpios = <&gpio0 6 1>; + }; + lan2_green { + label = "VR-3026e:green:lan2"; + gpios = <&gpio0 7 1>; + }; + lan3_green { + label = "VR-3026e:green:lan3"; + gpios = <&gpio0 8 1>; + }; + lan4_green { + label = "VR-3026e:green:lan4"; + gpios = <&gpio0 9 1>; + }; + power_green { + label = "VR-3026e:green:power"; + gpios = <&gpio0 22 0>; + default-state = "on"; + }; + power_red { + label = "VR-3026e:red:power"; + gpios = <&gpio0 24 0>; + }; + inet_red { + label = "VR-3026e:red:inet"; + gpios = <&gpio0 31 0>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/dts/wap-5813n.dts b/target/linux/brcm63xx/dts/wap-5813n.dts new file mode 100644 index 0000000..1c31c57 --- /dev/null +++ b/target/linux/brcm63xx/dts/wap-5813n.dts @@ -0,0 +1,82 @@ +/dts-v1/; + +#include "bcm6368.dtsi" + +#include + +/ { + model = "Comtrend WAP-5813n"; + compatible = "comtrend,wap-5813n", "brcm,bcm6368"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + debounce-interval = <60>; + + wlan { + label = "wlan"; + gpios = <&gpio1 0 1>; + linux,code = ; + }; + reset { + label = "reset"; + gpios = <&gpio1 2 1>; + linux,code = ; + }; + wps { + label = "wps"; + gpios = <&gpio1 3 1>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "WAP-5813n:green:inet"; + gpios = <&gpio0 5 0>; + }; + power_green { + label = "WAP-5813n:green:power"; + gpios = <&gpio0 22 0>; + default-state = "on"; + }; + wps_green { + label = "WAP-5813n:green:wps"; + gpios = <&gpio0 23 1>; + }; + power_red { + label = "WAP-5813n:red:power"; + gpios = <&gpio0 24 0>; + }; + inet_red { + label = "WAP-5813n:red:inet"; + gpios = <&gpio0 31 0>; + }; + }; +}; + +&pflash { + status = "ok"; + + linux,part-probe = "bcm63xxpart"; + + cfe@0 { + label = "CFE"; + reg = <0x000000 0x010000>; + read-only; + }; + + linux@10000 { + label = "linux"; + reg = <0x010000 0x7e0000>; + }; + + nvram@7f0000 { + label = "nvram"; + reg = <0x7f0000 0x010000>; + }; +}; diff --git a/target/linux/brcm63xx/generic/target.mk b/target/linux/brcm63xx/generic/target.mk new file mode 100644 index 0000000..d43a37c --- /dev/null +++ b/target/linux/brcm63xx/generic/target.mk @@ -0,0 +1,7 @@ +BOARDNAME:=generic + +define Target/Description + Build firmware images for BCM63XX boards without SMP support. +endef + + diff --git a/target/linux/brcm63xx/image/Makefile b/target/linux/brcm63xx/image/Makefile new file mode 100644 index 0000000..9581116 --- /dev/null +++ b/target/linux/brcm63xx/image/Makefile @@ -0,0 +1,636 @@ +# +# Copyright (C) 2006-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +LOADADDR = 0x80010000 # RAM start + 64K +KERNEL_ENTRY = $(LOADADDR) # Newer kernels add a jmp to the kernel_entry at the start of the binary +LOADER_ENTRY = 0x80a00000 # RAM start + 10M, for relocate +RAMSIZE = 0x02000000 # 32MB +LZMA_TEXT_START = 0x81800000 # 32MB - 8MB + +LOADER_MAKEOPTS= \ + KDIR=$(KDIR) \ + LOADADDR=$(LOADADDR) \ + KERNEL_ENTRY=$(KERNEL_ENTRY) \ + RAMSIZE=$(RAMSIZE) \ + LZMA_TEXT_START=$(LZMA_TEXT_START) \ + +RELOCATE_MAKEOPTS= \ + CACHELINE_SIZE=16 \ + KERNEL_ADDR=$(KERNEL_ENTRY) \ + CROSS_COMPILE=$(TARGET_CROSS) \ + LZMA_TEXT_START=$(LOADER_ENTRY) + +define Build/Compile + rm -rf $(KDIR)/relocate + $(CP) ../../generic/image/relocate $(KDIR) + $(MAKE) -C $(KDIR)/relocate $(RELOCATE_MAKEOPTS) +endef + +### Kernel scripts ### +define Build/append-dtb + $(call Image/BuildDTB,../dts/$(DEVICE_DTS).dts,$@.dtb) + cat $@.dtb >> $@ +endef + +define Build/hcs-initramfs + $(STAGING_DIR_HOST)/bin/hcsmakeimage --magic_bytes=$(HCS_MAGIC_BYTES) \ + --rev_maj=$(HCS_REV_MAJ) --rev_min=$(HCS_REV_MIN) --input_file=$@ \ + --output_file=$@.hcs --ldaddress=$(LOADADDR) + mv $@.hcs $@ +endef + +define Build/loader-lzma + rm -rf $@.src + $(MAKE) -C lzma-loader \ + $(LOADER_MAKEOPTS) \ + PKG_BUILD_DIR="$@.src" \ + TARGET_DIR="$(dir $@)" \ + LOADER_DATA="$@" \ + LOADER_NAME="$(notdir $@)" \ + compile loader.$(1) + mv "$@.$(1)" "$@" + rm -rf $@.src +endef + +define Build/lzma + # CFE is a LZMA nazi! It took me hours to find out the parameters! + # Also I think lzma has a bug cause it generates different output depending on + # if you use stdin / stdout or not. Use files instead of stdio here, cause + # otherwise CFE will complain and not boot the image. + $(STAGING_DIR_HOST)/bin/lzma e $@ -d22 -fb64 -a1 $@.lzma + mv $@.lzma $@ +endef + +define Build/lzma-cfe + # Strip out the length, CFE doesn't like this + dd if=$@ of=$@.lzma.cfe bs=5 count=1 + dd if=$@ of=$@.lzma.cfe ibs=13 obs=5 skip=1 seek=1 conv=notrunc + mv $@.lzma.cfe $@ +endef + +define Build/relocate-kernel + # CFE only allows ~4 MiB for the uncompressed kernels, but uncompressed + # kernel might get larger than that, so let CFE unpack and load at a + # higher address and make the kernel relocate itself to the expected + # location. + ( \ + dd if=$(KDIR)/relocate/loader.bin bs=32 conv=sync && \ + perl -e '@s = stat("$@"); print pack("N", @s[7])' && \ + cat $@ \ + ) > $@.relocate + mv $@.relocate $@ +endef + +### Image scripts ### +define rootfspad/jffs2-128k +--align-rootfs +endef +define rootfspad/jffs2-64k +--align-rootfs +endef +define rootfspad/squashfs +endef + +define Image/LimitName16 +$(shell expr substr "$(1)" 1 16) +endef + +define Image/FileSystemStrip +$(subst root.,,$(notdir $(1))) +endef + +define Build/cfe-bin + $(STAGING_DIR_HOST)/bin/imagetag -i $(word 1,$^) -f $(word 2,$^) \ + --output $@ --boardid $(CFE_BOARD_ID) --chipid $(CFE_CHIP_ID) \ + --entry $(LOADER_ENTRY) --load-addr $(LOADER_ENTRY) \ + --info1 "$(call Image/LimitName16,$(DEVICE_NAME))" \ + --info2 "$(call Image/FileSystemStrip,$(word 2,$^))" \ + $(call rootfspad/$(call Image/FileSystemStrip,$(word 2,$^))) \ + $(CFE_EXTRAS) $(1) +endef + +define Build/cfe-old-bin + $(TOPDIR)/scripts/brcmImage.pl -t -p \ + -o $@ -b $(CFE_BOARD_ID) -c $(CFE_CHIP_ID) \ + -e $(LOADER_ENTRY) -a $(LOADER_ENTRY) \ + -k $(word 1,$^) -r $(word 2,$^) \ + $(CFE_EXTRAS) +endef + +define Build/cfe-spw303v-bin + $(STAGING_DIR_HOST)/bin/imagetag -i $(word 1,$^) -f $(word 2,$^) \ + --output $@ --boardid $(CFE_BOARD_ID) --chipid $(CFE_CHIP_ID) \ + --entry $(LOADER_ENTRY) --load-addr $(LOADER_ENTRY) \ + $(call rootfspad/$(call Image/FileSystemStrip,$(word 2,$^))) \ + $(CFE_EXTRAS) +endef + +define Build/spw303v-bin + $(STAGING_DIR_HOST)/bin/spw303v -i $@ -o $@.spw303v + mv $@.spw303v $@ +endef + +define Build/xor-image + $(STAGING_DIR_HOST)/bin/xorimage -i $@ -o $@.xor + mv $@.xor $@ +endef + +define Build/zyxel-bin + $(STAGING_DIR_HOST)/bin/zyxbcm -i $@ -o $@.zyxel + mv $@.zyxel $@ +endef + +define Build/redboot-bin + # Prepare kernel and rootfs + dd if=$(word 1,$^) of=$(BIN_DIR)/$(REDBOOT_PREFIX)-vmlinux.gz bs=65536 conv=sync + dd if=$(word 2,$^) of=$(BIN_DIR)/$(REDBOOT_PREFIX)-$(notdir $(word 2,$^)) bs=64k conv=sync + echo -ne \\xDE\\xAD\\xC0\\xDE >> $(BIN_DIR)/$(REDBOOT_PREFIX)-$(notdir $(word 2,$^)) + # Generate the scripted image + $(TOPDIR)/scripts/redboot-script.pl \ + -k $(BIN_DIR)/$(REDBOOT_PREFIX)-vmlinux.gz \ + -r $(BIN_DIR)/$(REDBOOT_PREFIX)-$(notdir $(word 2,$^)) \ + -a $(strip $(LOADADDR)) -f 0xbe430000 -l 0x7c0000 \ + -s 0x1000 -t 20 -o $@.redbootscript + dd if="$@.redbootscript" of="$@.redbootscript.padded" bs=4096 conv=sync + cat \ + "$@.redbootscript.padded" \ + "$(BIN_DIR)/$(REDBOOT_PREFIX)-vmlinux.gz" \ + "$(BIN_DIR)/$(REDBOOT_PREFIX)-$(notdir $(word 2,$^))" \ + > "$@" +endef + +# Shared device definition: applies to every defined device +define Device/Default + PROFILES = Default $$(DEVICE_PROFILE) + KERNEL_INITRAMFS_IMAGE = $$(KERNEL_INITRAMFS_PREFIX).elf + DEVICE_PROFILE := + DEVICE_DTS := +endef +DEVICE_VARS += DEVICE_PROFILE DEVICE_DTS + +# BCM33xx HCS devices: only generates ramdisks (unsupported bin images) +define Device/bcm33xxHcsRamdisk + KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma bin | hcs-initramfs + IMAGES := + HCS_MAGIC_BYTES := + HCS_REV_MIN := + HCS_REV_MAJ := +endef +DEVICE_VARS += HCS_MAGIC_BYTES HCS_REV_MIN HCS_REV_MAJ + +# Shared BCM63xx CFE device definitios +define Device/bcm63xxCfeCommon + FILESYSTEMS := squashfs jffs2-64k jffs2-128k + KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma | lzma-cfe + KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf +endef + +# BCM63xx CFE devices: only generates ramdisks (unsupported bin images) +define Device/bcm63xxCfeRamdisk + $(Device/bcm63xxCfeCommon) + IMAGES := +endef + +# BCM63xx CFE devices: both ramdisks and parallel/spi bin images +# New versions of CFE bootloader compatible with imagetag +define Device/bcm63xxCfe + $(Device/bcm63xxCfeCommon) + IMAGES := cfe.bin + IMAGE/cfe.bin := cfe-bin + CFE_BOARD_ID := + CFE_CHIP_ID := + CFE_EXTRAS := +endef +DEVICE_VARS += CFE_BOARD_ID CFE_CHIP_ID CFE_EXTRAS + +# BCM63xx CFE BC221 devices: both ramdisks and parallel/spi bin images +# Generates a generic image and a layout version 5 image +define Device/bcm63xxCfeBc221 + $(Device/bcm63xxCfeCommon) + IMAGES := cfe.bin cfe-bc221.bin + IMAGE/cfe.bin := cfe-bin + IMAGE/cfe-bc221.bin := cfe-bin --layoutver 5 + CFE_BOARD_ID := + CFE_CHIP_ID := + CFE_EXTRAS := +endef + +# BCM63xx CFE MultiFlash devices: both ramdisks and parallel/spi bin images +# Generates generic images padded for 4M/8M/16M flashes +define Device/bcm63xxCfeMultiFlash + $(Device/bcm63xxCfeCommon) + IMAGES := cfe-4M.bin cfe-8M.bin cfe-16M.bin + IMAGE/cfe-4M.bin := cfe-bin --pad 2 + IMAGE/cfe-8M.bin := cfe-bin --pad 4 + IMAGE/cfe-16M.bin := cfe-bin --pad 8 + CFE_BOARD_ID := + CFE_CHIP_ID := + CFE_EXTRAS := +endef + +# BCM63xx CFE NETGEAR devices: both ramdisks and parallel/spi bin images +# factory.chk: netgear images for bootloader/original firmware upgrades +# sysupgrade.bin: openwrt images for sysupgrades +define Device/bcm63xxCfeNetgear + $(Device/bcm63xxCfeCommon) + IMAGES := factory.chk sysupgrade.bin + IMAGE/factory.chk := cfe-bin | netgear-chk + IMAGE/sysupgrade.bin := cfe-bin + CFE_BOARD_ID := + CFE_CHIP_ID := + CFE_EXTRAS := + NETGEAR_BOARD_ID := + NETGEAR_REGION := +endef +DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_REGION + +# BCM63xx Old CFE devices: both ramdisks and parallel/spi bin images +# Old versions of CFE bootloader not compatible with imagetag +define Device/bcm63xxCfeOld + $(Device/bcm63xxCfeCommon) + IMAGES := cfe-old.bin + IMAGE/cfe-old.bin := cfe-old-bin + CFE_BOARD_ID := + CFE_CHIP_ID := + CFE_EXTRAS := +endef + +# BCM63xx CFE SPW303V devices: both ramdisks and parallel/spi bin images +# factory.bin: SPW303V images for bootloader/original firmware upgrades +# sysupgrade.bin: openwrt images for sysupgrades +define Device/bcm63xxCfeSpw303v + $(Device/bcm63xxCfeCommon) + IMAGES := factory.bin sysupgrade.bin + IMAGE/factory.bin := cfe-spw303v-bin | spw303v-bin | xor-image + IMAGE/sysupgrade.bin := cfe-spw303v-bin | spw303v-bin + CFE_BOARD_ID := + CFE_CHIP_ID := + CFE_EXTRAS := +endef + +# BCM63xx CFE ZyXEL devices: both ramdisks and parallel/spi bin images +# factory.bin: ZyXEL specific CFE images (sysupgrade compatible) +define Device/bcm63xxCfeZyxel + $(Device/bcm63xxCfeCommon) + IMAGES := factory.bin + IMAGE/factory.bin := cfe-bin | zyxel-bin + CFE_BOARD_ID := + CFE_CHIP_ID := + CFE_EXTRAS := +endef + +# BCM63xx RedBoot devices: both ramdisks and parallel/spi bin images +# Generates images compatible with RedBoot bootloader +define Device/bcm63xxRedBoot + FILESYSTEMS := squashfs + KERNEL := kernel-bin | append-dtb | gzip + IMAGES := redboot.bin + IMAGE/redboot.bin := redboot-bin + REDBOOT_PREFIX := $$(IMAGE_PREFIX) +endef +DEVICE_VARS += REDBOOT_PREFIX + +### Device macros ### +# $(1) = profile +# $(2) = image name +# $(3) = dts +# $(4) = hcs magic bytes +# $(5) = hcs rev min +# $(6) = hcs rev major +define bcm33xxHcsRamdisk + define Device/$(2) + $$(Device/bcm33xxHcsRamdisk) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + HCS_MAGIC_BYTES := $(4) + HCS_REV_MIN := $(5) + HCS_REV_MAJ := $(6) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +define bcm63xxCfeRamdisk + define Device/$(2) + $$(Device/bcm63xxCfeRamdisk) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +# $(4) = cfe board name +# $(5) = cfe chip id +# $(6) = cfe additional options +define bcm63xxCfe + define Device/$(2) + $$(Device/bcm63xxCfe) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + CFE_BOARD_ID := $(4) + CFE_CHIP_ID := $(5) + CFE_EXTRAS := $(6) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +# $(4) = cfe board name +# $(5) = cfe chip id +# $(6) = cfe additional options +define bcm63xxCfeMultiFlash + define Device/$(2) + $$(Device/bcm63xxCfeMultiFlash) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + CFE_BOARD_ID := $(4) + CFE_CHIP_ID := $(5) + CFE_EXTRAS := $(6) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +# $(4) = cfe board name +# $(5) = cfe chip id +# $(6) = cfe additional options +define bcm63xxCfeBc221 + define Device/$(2) + $$(Device/bcm63xxCfeBc221) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + CFE_BOARD_ID := $(4) + CFE_CHIP_ID := $(5) + CFE_EXTRAS := $(6) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +# $(4) = cfe board name +# $(5) = cfe chip id +# $(6) = cfe additional options +# $(7) = netgear id +# $(8) = netgear region +define bcm63xxCfeNetgear + define Device/$(2) + $$(Device/bcm63xxCfeNetgear) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + CFE_BOARD_ID := $(4) + CFE_CHIP_ID := $(5) + CFE_EXTRAS := $(6) + NETGEAR_BOARD_ID := $(7) + NETGEAR_REGION := $(8) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +# $(4) = cfe board name +# $(5) = cfe chip id +# $(6) = cfe additional options +define bcm63xxCfeOld + define Device/$(2) + $$(Device/bcm63xxCfeOld) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + CFE_BOARD_ID := $(4) + CFE_CHIP_ID := $(5) + CFE_EXTRAS := $(6) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +# $(4) = cfe board name +# $(5) = cfe chip id +# $(6) = cfe additional options +define bcm63xxCfeSpw303v + define Device/$(2) + $$(Device/bcm63xxCfeSpw303v) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + CFE_BOARD_ID := $(4) + CFE_CHIP_ID := $(5) + CFE_EXTRAS := $(6) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +# $(4) = cfe board name +# $(5) = cfe chip id +# $(6) = cfe additional options +define bcm63xxCfeZyxel + define Device/$(2) + $$(Device/bcm63xxCfeZyxel) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + CFE_BOARD_ID := $(4) + CFE_CHIP_ID := $(5) + CFE_EXTRAS := $(6) + endef + TARGET_DEVICES += $(2) +endef + +# $(1) = profile +# $(2) = image name +# $(3) = dts +define bcm63xxRedBoot + define Device/$(2) + $$(Device/bcm63xxRedBoot) + DEVICE_PROFILE := $(1) + DEVICE_DTS := $(3) + endef + TARGET_DEVICES += $(2) +endef + +### Devices ### +# Generic 963281TAN +$(eval $(call bcm63xxCfeMultiFlash,963281TAN,963281TAN-generic,bcm963281TAN,963281TAN,6328)) +# Generic 96328avng +$(eval $(call bcm63xxCfeMultiFlash,96328avng,96328avng-generic,bcm96328avng,96328avng,6328)) +# Generic 96338GW +$(eval $(call bcm63xxCfe,96338GW,96338GW-generic,bcm96338GW,6338GW,6338)) +# Generic 96338W +$(eval $(call bcm63xxCfe,96338W,96338W-generic,bcm96338W,6338W,6338)) +# Generic 96345GW2 +$(eval $(call bcm63xxCfeBc221,96345GW2,96345GW2-generic,bcm96345GW2,96345GW2,6345)) +# Generic 96348GW +$(eval $(call bcm63xxCfeBc221,96348GW,96348GW-generic,bcm96348GW,96348GW,6348)) +# Generic 96348GW-10 +$(eval $(call bcm63xxCfe,96348GW_10,96348GW-10-generic,bcm96348GW-10,96348GW-10,6348)) +# Generic 96348GW-11 +$(eval $(call bcm63xxCfe,96348GW_11,96348GW-11-generic,bcm96348GW-11,96348GW-11,6348)) +# Generic 96348R +$(eval $(call bcm63xxCfe,96348R,96348R-generic,bcm96348R,96348R,6348)) +# Generic 96358VW +$(eval $(call bcm63xxCfe,96358VW,96358VW-generic,bcm96358VW,96358VW,6358)) +# Generic 96358VW2 +$(eval $(call bcm63xxCfe,96358VW2,96358VW2-generic,bcm96358VW2,96358VW2,6358)) +# Generic 96368MVNgr +$(eval $(call bcm63xxCfe,96368MVNgr,96368MVNgr-generic,bcm96368MVNgr,96368MVNgr,6368)) +# Generic 96368MVWG +$(eval $(call bcm63xxCfe,96368MVWG,96368MVWG-generic,bcm96368MVWG,96368MVWG,6368)) + +# ADB P.DG A4001N +$(eval $(call bcm63xxCfe,A4001N,A4001N,a4001n,96328dg2x2,6328,--pad 4)) +# ADB P.DG A4001N1 +$(eval $(call bcm63xxCfe,A4001N1,A4001N1,a4001n1,963281T_TEF,6328,--pad 8)) +# Alcatel RG100A +$(eval $(call bcm63xxCfe,RG100A,RG100A,rg100a,96358VW2,6358,--block-size 0x20000 --image-offset 0x20000)) +# Asmax AR 1004g +$(eval $(call bcm63xxCfe,AR1004G,AR1004G,ar1004g,96348GW-10,6348)) +# Belkin F5D7633 +$(eval $(call bcm63xxCfe,F5D7633,F5D7633,f5d7633,96348GW-10,6348,--block-size 0x20000 --image-offset 0x20000)) +# Broadcom BCM96318REF +$(eval $(call bcm63xxCfeRamdisk,BCM96318REF,BCM96318REF,bcm96318ref,96318REF,6318)) +# Broadcom BCM96318REF_P300 +$(eval $(call bcm63xxCfeRamdisk,BCM96318REF_P300,BCM96318ref_P300,bcm96318ref_p300,96318REF_P300,6318)) +# Broadcom BCM963268BU_P300 +$(eval $(call bcm63xxCfeRamdisk,BCM963268BU_P300,BCM963268BU_P300,bcm963268bu_p300,963268BU_P300,63268)) +# Broadcom BCM963269BHR +$(eval $(call bcm63xxCfeRamdisk,BCM963269BHR,BCM963269BHR,bcm963269bhr,963269BHR,63268)) +# BT Home Hub 2.0 A +$(eval $(call bcm63xxCfe,BTHOMEHUB2A,HomeHub2A,homehub2a,HOMEHUB2A,6358,--image-offset 0x20000 --block-size 0x20000)) +# BT Voyager V2110, V2110_AA, V2110_ROI +$(eval $(call bcm63xxCfe,BTV2110,BTV2110,v2110,V2110,6348,--layoutver 5)) +# BT Voyager V2500V, V2500V_SIP_CLUB, V2500V_AA +$(eval $(call bcm63xxCfe,BTV2500V,BTV2500V,v2500v-bb,V2500V_BB,6348,--layoutver 5)) +# Comtrend AR-5381u +$(eval $(call bcm63xxCfe,AR5381u,AR-5381u,ar-5381u,96328A-1241N,6328,--pad 8)) +# Comtrend AR-5387un +$(eval $(call bcm63xxCfe,AR5387un,AR-5387un,ar-5387un,96328A-1441N1,6328,--pad 8)) +# Comtrend 536, 5621 +$(eval $(call bcm63xxCfe,CT536_CT5621,CT536_CT5621,ct536plus,96348GW-11,6348)) +# Comtrend CT-5365 +$(eval $(call bcm63xxCfe,CT5365,CT-5365,ct-5365,96348A-122,6348)) +# Comtrend CT-6373 +$(eval $(call bcm63xxCfe,CT6373,CT-6373,ct-6373,CT6373-1,6358)) +# Comtrend VR-3025u +$(eval $(call bcm63xxCfe,VR3025u,VR-3025u,vr-3025u,96368M-1541N,6368,--pad 16 --image-offset 0x20000 --block-size 0x20000)) +# Comtrend VR-3025un +$(eval $(call bcm63xxCfe,VR3025un,VR-3025un,vr-3025un,96368M-1341N,6368,--pad 4)) +# Comtrend VR-3026e +$(eval $(call bcm63xxCfe,VR3026e,VR-3026e,vr-3026e,96368MT-1341N1,6368,--pad 4)) +# Comtrend WAP-5813n +$(eval $(call bcm63xxCfe,WAP5813n,WAP-5813n,wap-5813n,96369R-1231N,6368,--pad 4)) +# D-Link DSL-2640B, rev B2 +$(eval $(call bcm63xxCfe,DSL2640B-B2,DSL2640B_B,dsl-2640b-b,D-4P-W,6348)) +# D-Link DSL-2640U, rev C1 +$(eval $(call bcm63xxCfe,DSL2640U,DSL2640U,dsl-2640u,96338W2_E7T,6338)) +# D-Link DSL-2650U +$(eval $(call bcm63xxCfe,DSL2650U,DSL2650U,dsl-2650u,96358VW2,6358)) +# D-Link DSL-2740B/DSL-2741B, rev C2 +$(eval $(call bcm63xxCfe,DSL274XB_C,DSL274XB-C2,dsl-274xb-c,96358GW,6358)) +# D-Link DSL-2740B/DSL-2741B, rev C3 +$(eval $(call bcm63xxCfe,DSL274XB_C,DSL274XB-C3,dsl-274xb-c,AW4139,6358)) +# D-Link DSL-2740B/DSL-2741B, rev F1 +$(eval $(call bcm63xxCfe,DSL274XB_F,DSL274XB-F1-EU,dsl-274xb-f,AW4339U,6328,--signature2 "4.06.01.EUF1" --pad 4)) +$(eval $(call bcm63xxCfe,DSL274XB_F,DSL274XB-F1-AU,dsl-274xb-f,AW4339U,6328,--signature2 "4.06.01.AUF1" --pad 4)) +# D-Link DSL-2750B/DSL-2751, rev D1 +$(eval $(call bcm63xxCfe,DSL275XB_D,DSL275XB-D1,dsl-275xb-d,AW5200B,6318,--pad 4)) +# D-Link DVA-G3810BN/TL +$(eval $(call bcm63xxCfe,DVAG3810BN,DVAG3810BN,dva-g3810bn_tl,96358VW,6358)) +# Davolink DV-201AMR +$(eval $(call bcm63xxCfeOld,DV201AMR,DV-201AMR,dv-201amr,DV201AMR,6348)) +# Dynalink RTA770BW (Siemens SE515) +$(eval $(call bcm63xxCfeRamdisk,RTA770BW,RTA770BW,rta770bw,RTA770BW,6345,--layoutver 5)) +# Dynalink RTA770W +$(eval $(call bcm63xxCfeRamdisk,RTA770W,RTA770W,rta770w,RTA770W,6345,--layoutver 5)) +# Dynalink RTA1025W (numerous routers) +$(eval $(call bcm63xxCfe,RTA1025W,RTA1025W_16,rta1025w,RTA1025W_16,6348,--layoutver 5)) +# Dynalink RTA1320 (numerous routers) +$(eval $(call bcm63xxCfe,RTA1320,RTA1320_16M,rta1320,RTA1320_16M,6338,--layoutver 5)) +# Huawei HG520v +$(eval $(call bcm63xxCfe,HG520v,HG520v,hg520v,HW6358GW_B,6358,--rsa-signature "EchoLife_HG520v")) +# Huawei HG553 +$(eval $(call bcm63xxCfe,HG553,HG553,hg553,HW553,6358,--rsa-signature "EchoLife_HG553" --image-offset 0x20000 --block-size 0x20000 --tag-version 7)) +# Huawei HG556a +$(eval $(call bcm63xxCfe,HG556a_AB,HG556a_A,hg556a-a,HW556,6358,--rsa-signature "EchoLife_HG556a" --image-offset 0x20000 --block-size 0x10000 --tag-version 8)) +$(eval $(call bcm63xxCfe,HG556a_AB,HG556a_B,hg556a-b,HW556,6358,--rsa-signature "EchoLife_HG556a" --image-offset 0x20000 --block-size 0x20000 --tag-version 8)) +$(eval $(call bcm63xxCfe,HG556a_C,HG556a_C,hg556a-c,HW556,6358,--rsa-signature "EchoLife_HG556a" --image-offset 0x20000 --block-size 0x20000 --tag-version 8)) +# Huawei HG655b +$(eval $(call bcm63xxCfe,HG655b,HG655b,hg655b,HW65x,6368,--image-offset 0x20000 --tag-version 7 --pad 4)) +# Inteno VG50 +$(eval $(call bcm63xxCfeRamdisk,VG50,vg50,vg50,VW6339GU,63268)) +# Inventel Livebox 1 +$(eval $(call bcm63xxRedBoot,Livebox,livebox,livebox-blue-5g)) +# Netgear CVG834G +$(eval $(call bcm33xxHcsRamdisk,CVG834G,cvg834g,cvg834g,0xa020,0001,0022)) +# Netgear DG834GT/PN +$(eval $(call bcm63xxCfe,DG834GTPN,DG834GT_PN,dg834gtpn,96348GW-10,6348)) +# Netgear DG834G v4 +$(eval $(call bcm63xxCfeRamdisk,DG834GV4,DG834GTv4,dg834g_v4,96348W3,6348)) +# Netgear DGND3700 v1 +$(eval $(call bcm63xxCfeNetgear,DGND3700v1_3800B,DGND3700v1,dgnd3700v1,96368MVWG,6368,--image-offset 0x20000 --block-size 0x20000,U12L144T01_NETGEAR_NEWLED,1)) +# Netgear DGND3800B +$(eval $(call bcm63xxCfeNetgear,DGND3700v1_3800B,DGND3800B,dgnd3700v1,96368MVWG,6368,--image-offset 0x20000 --block-size 0x20000,U12L144T11_NETGEAR_NEWLED,1)) +# Pirelli Alice Gate VoIP 2 Plus Wi-Fi AGPF-S0 +$(eval $(call bcm63xxCfe,AGPF_S0,AGV2+W,agpf-s0,AGPF-S0,6358,--block-size 0x20000 --image-offset 0x20000 --signature2 IMAGE --tag-version 8)) +# Pirelli A226G +$(eval $(call bcm63xxCfe,A226G,A226G,a226g,DWV-S0,6358,--signature2 IMAGE --tag-version 8)) +# Pirelli A226M/A226M-FWB +$(eval $(call bcm63xxCfe,A226M,A226M,a226m,DWV-S0,6358,--signature2 IMAGE --tag-version 8)) +$(eval $(call bcm63xxCfe,A226M,A226M-FWB,a226m-fwb,DWV-S0,6358,--block-size 0x20000 --image-offset 0x20000 --signature2 IMAGE --tag-version 8)) +# Sagem F@ST2404 +$(eval $(call bcm63xxCfe,FAST2404,F@ST2404,fast2404,F@ST2404,6348)) +# Sagem F@ST2504n +$(eval $(call bcm63xxCfe,FAST2504n,F@ST2504n,fast2504n,F@ST2504n,6362)) +# Sagem F@ST2604 +$(eval $(call bcm63xxCfe,FAST2604,F@ST2604,fast2604,F@ST2604,6348)) +# Sagem F@ST2704N V1 / Plusnet F@ST2704N V1 +$(eval $(call bcm63xxCfe,FAST2704N,FAST2704N,fast2704n,F@ST2704N,6318,--pad 4)) +# Sagem F@ST2704V2 +$(eval $(call bcm63xxCfe,FAST2704V2,F@ST2704V2,fast2704v2,F@ST2704V2,6328)) +# SFR Neufbox 4 +$(eval $(call bcm63xxCfe,Neufbox4,NEUFBOX4-SER,nb4-ser-r0,96358VW,6358,--rsa-signature "OpenWRT-$(REVISION)")) +$(eval $(call bcm63xxCfe,Neufbox4,NEUFBOX4-FXC,nb4-fxc-r1,96358VW,6358,--rsa-signature "OpenWRT-$(REVISION)")) +# SFR Neufbox 6 +$(eval $(call bcm63xxCfe,Neufbox6,NEUFBOX6,nb6-ser-r0,NB6-SER-r0,6362,--rsa-signature "OpenWRT-$(REVISION)")) +# T-Com Speedport W 303V Typ B +$(eval $(call bcm63xxCfeSpw303v,SPW303V,SPW303V,spw303v,96358-502V,6358,--pad 4)) +# T-Com Speedport W 500V +$(eval $(call bcm63xxCfe,SPW500V,SPW500V,spw500v,96348GW,6348)) +# Tecom GW6000 +$(eval $(call bcm63xxCfe,GW6000,GW6000,gw6000,96348GW,6348)) +# Tecom GW6200 +$(eval $(call bcm63xxCfe,GW6200,GW6200,gw6200,96348GW,6348,--rsa-signature "$(shell printf '\x99')")) +# Telsey CPVA502+ +$(eval $(call bcm63xxCfeRamdisk,CPVA502PLUS,CVPA502PLUS,cpva502plus,CPVA502+,6348,--signature "Telsey Tlc" --signature2 "99.99.999" --second-image-flag "0")) +# Telsey CPVA642-type (e.g. CPA-ZNTE60T) +$(eval $(call bcm63xxCfe,CPVA642,CPA-ZNTE60T,cpva642,CPVA642,6358,--signature "Telsey Tlc" --signature2 "99.99.999" --second-image-flag "0" --pad 4)) +# Telsey MAGIC (Alice W-Gate) +$(eval $(call bcm63xxCfeRamdisk,MAGIC,MAGIC,magic,MAGIC,6348)) +# TP-Link TD-W8900GB +$(eval $(call bcm63xxCfe,TDW8900GB,TD-W8900GB,td-w8900gb,96348GW-11,6348,--rsa-signature "$(shell printf 'PRID\x89\x10\x00\x02')" --image-offset 0x20000)) +# USRobotics 9108 +$(eval $(call bcm63xxCfe,USR9108,USR9108,usr9108,96348GW-A,6348)) +# ZyXEL P870HW-51a v2 +$(eval $(call bcm63xxCfeZyxel,P870HW_51a_v2,P870HW-51a_v2,p870hw-51a-v2,96368VVW,6368,--rsa-signature "ZyXEL" --signature "ZyXEL_0001")) + +$(eval $(call BuildImage)) diff --git a/target/linux/brcm63xx/image/README.images-bcm63xx b/target/linux/brcm63xx/image/README.images-bcm63xx new file mode 100644 index 0000000..91b6d01 --- /dev/null +++ b/target/linux/brcm63xx/image/README.images-bcm63xx @@ -0,0 +1,127 @@ +The image neede to flash onto a Broadcom 63xx-series board depends on the +board, method you are using to flash, and, for web-based flash, on the version +of the Broadcom code your router uses. + +There are two major revisions of the Broadcom code as far as imagetags are +concerned, before 3.08 and after 3.08, however there are some variations +within in that, either due to vendor differences or due to changes at +Broadcom (it's not clear yet which is the case). In addtion Pirelli modified +the Broadcom code, so Alice Gate models use a different imagetag than any +other vendor. + +The imagetag format for flashing via CFE is the same for almost all the +boards, and is the same for all images generated by the imagetag utility. +Images flashable using cfe are labelled openwrt---cfe.bin + +The imagetags for tftp/ftp flashing is based on Broadcom 3.00-3.04 imagetags +and is known to be correct as the source code GPL and is available for reading. + +Broadcom code 2.21 is based on the BT Voyager firmware image I looked at. It +may in fact be BT Voyager-specific. 2.21 is actually more difficult to deal +with the imagetag from 3.00 as it has three different CRC calculations in +addtition to the header CRC. + +Broadcom 3.00-3.02 flashing has been tested on Comtrend CT-5261, CT-536 and +Tecom GW6000, and is the version of the flashing that was present before the +imagetags were split by broadcom code version (early June 2009) + +3.04 is guessed to be the same as 3.00-3.02 based on available information + +Broadom 3.06 is thought to be the same as 3.00-3.02, however the only 3.06 +this author (Daniel Dickinson) has seen is the Alice Gate (Pirelli) firmware +which is known to be different due to vendor (Pirelli) modifications to the +Broadcom code. + +Broadcom 3.10 uses an imagetag that is believed to apply to all 3.10 and 3.12 +versions, and has been tested on the Tecom GW6200. This version introdec changes to +the imagetag to deal with TR69 (a remote rouer management system developed by the +DSL forum). There is a field for vendor-specific information, that at least in some +cases is not optional. It is based on the hexedit of a neufbox4 firmware image, the +information in https://dev.openwrt.org/ticket/4987, and the hexedit of a Tecom +GW6200 image. + +Some boards share the same tag format, but require vendor-specific fields in +the board. In that case the tagid is shared, but the filename of the generated +image reflects the router for which the image was created. + +router |method | codever |filename ++-------------+-------------+---------+--------------------------------------- +|any |cfe+most web | any |openwrt---cfe.bin +|AGVoIP2+WiFi |cfe |alice3.06|openwrt-AGV2+W-cfe--cfe.bin +|AGVoIP2+WiFi |web |alice3.06|openwrt-AGV2+W-cfe--cfe.bin +|CT536 |web |3.02 |openwrt-CT536_CT5621--cfe.bin +|CT5621 |web |3.02 |openwrt-CT536_CT5621--cfe.bin +|DG834GT |web |3.02 |openwrt-DG834GT_DG834PN--cfe.bin +|DG834PN |web |3.02 |openwrt-DG834GT_DG834PN--cfe.bin +|DSL-2640B |web |3.10 |openwrt-DSL2640B--cfe.bin +|DSL-2740B |web |3.10 |openwrt-DSL2670B--cfe.bin +|F5D7633 |web |3.10 |openwrt-F5D7633--cfe.bin +|F@ST2404 |web |3.0X? |openwrt-F@ST2404-cfe--cfe.bin +|F@ST2404 |web |3.1X? |openwrt-F@ST2404--cfe.bin +|GW6000 |web |3.00 |openwrt-GW6000--cfe.bin +|GW6200 |web |3.10 |openwrt-GW6200--cfe.bin +|Neufbox4 |web |3.12 |openwrt-NEUFBOX4--cfe.bin +|TD8810A |web |3.06 |openwrt-TD8810--cfe.bin +|TD8810B |web |3.06 |openwrt-TD8810--cfe.bin +|TD8811A |web |3.06 |openwrt-TD8811--cfe.bin +|TD8811B |web |3.06 |openwrt-TD881--cfe.bin +|TD8900GB |web |3.06 |openwrt-TD8900DB-cfe.bin +|USR9108 |web |3.0X? |openwrt-USR9108--cfe.bin +|V2091_BTR |web |2.21 |openwrt-V2091_BTR--cfe.bin +|V2091_ROI |web |2.21 |openwrt-V2091--cfe.bin +|V2091_WB |web |2.21 |openwrt-V2091--cfe.bin +|V210_BTR |web |2.21 |openwrt-V210_BTR--cfe.bin +|V210_ROI |web |2.21 |openwrt-V210-ROI_WB-cfe.bin +|V210_WB |web |2.21 |openwrt-V210-ROI_WB-cfe.bin +|V2110 |web |2.21 |openwrt-V2110--cfe.bin +|V2110_AA |web |2.21 |openwrt-V2110--cfe.bin +|V2110_ROI |web |2.21 |openwrt-V2110--cfe.bin +|V2500V |web |2.21 |openwrt-V2500V-cfe.bin +|V2500V_AA |web |2.21 |openwrt-V2500V--cfe.bin +|V2500V_SIP_CLUB |web |2.21 |openwrt-V2500V--cfe.bin + +Old imagetag routers +-------------------- +Davolink DV201AMR + +Redboot routers +--------------- +Inventel Livebox + +Known router->code versions +--------------------------- + +Vendor |Model |Code Ver +---------------------------+------------------------------------------+-------- +Belkin |F5D7633 |3.10 +British Telecom (BT) |Voyager V2091_BTR |2.21 +British Telecom (BT) |Voyager V2091_ROI |2.21 +British Telecom (BT) |Voyager V2091_WB |2.21 +British Telecom (BT) |Voyager V210_BTR |2.21 +British Telecom (BT) |Voyager V210_ROI |2.21 +British Telecom (BT) |Voyager V210_WB |2.21 +British Telecom (BT) |Voyager V2110 |2.21 +British Telecom (BT) |Voyager V2110_AA |2.21 +British Telecom (BT) |Voyager V2110_ROI |2.21 +British Telecom (BT) |Voyager V220V |2.21 +British Telecom (BT) |Voyager V2500V |2.21 +British Telecom (BT) |Voyager V2500V_AA |2.21 +British Telecom (BT) |Voyager V2500V_SIP_CLUB |2.21 +Comtrend |CT-5261 |3.02 +Comtrend |CT-536 |3.02 +D-Link |DSL-2640B |3.10 +D-Link |DSL-2670B |3.10 +NetGear |DG834GT |3.02 +NetGear |DG834PN |3.02 +Neuf Cegetel |Neufbox 4 |3.12 +Pirelli |Alice Gate Wi-Fi (+VoIP models?) |ag 3.06 +Sagem |F@ST2404 |? +TP-Link |TD-8810A |3.06 +TP-Link |TD-8810B |3.06 +TP-Link |TD-8811A |3.06 +TP-Link |TD-8811B |3.06 +TP-Link |TD-W8900GB |3.06 +Tecom |GW6000 |3.00 +Tecom |GW6200 |3.10 +USR |9108 |? + diff --git a/target/linux/brcm63xx/image/lzma-loader/Makefile b/target/linux/brcm63xx/image/lzma-loader/Makefile new file mode 100644 index 0000000..8d36691 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/Makefile @@ -0,0 +1,62 @@ +# +# Copyright (C) 2011 OpenWrt.org +# Copyright (C) 2011 Gabor Juhos +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +LZMA_TEXT_START := 0x80a00000 +LOADER := loader.bin +LOADER_NAME := $(basename $(notdir $(LOADER))) +LOADER_DATA := +TARGET_DIR := +FLASH_OFFS := +FLASH_MAX := + +ifeq ($(TARGET_DIR),) +TARGET_DIR := $(KDIR) +endif + +LOADER_BIN := $(TARGET_DIR)/$(LOADER_NAME).bin +LOADER_GZ := $(TARGET_DIR)/$(LOADER_NAME).gz +LOADER_ELF := $(TARGET_DIR)/$(LOADER_NAME).elf + +PKG_NAME := lzma-loader +PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME) + +.PHONY : loader-compile loader.bin loader.elf loader.gz + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +loader-compile: $(PKG_BUILD_DIR)/.prepared + $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \ + LZMA_TEXT_START=$(LZMA_TEXT_START) \ + LOADER_DATA=$(LOADER_DATA) \ + FLASH_OFFS=$(FLASH_OFFS) \ + FLASH_MAX=$(FLASH_MAX) \ + clean all + +loader.gz: $(PKG_BUILD_DIR)/loader.bin + gzip -nc9 $< > $(LOADER_GZ) + +loader.elf: $(PKG_BUILD_DIR)/loader.elf + $(CP) $< $(LOADER_ELF) + +loader.bin: $(PKG_BUILD_DIR)/loader.bin + $(CP) $< $(LOADER_BIN) + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: loader-compile + +install: + +clean: + rm -rf $(PKG_BUILD_DIR) + diff --git a/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.c b/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 0000000..cb83453 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,584 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \ + BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + return LZMA_RESULT_DATA_ERROR; + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.h b/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 0000000..2870eeb --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,113 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +#include "LzmaTypes.h" + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb UInt16 +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/target/linux/brcm63xx/image/lzma-loader/src/LzmaTypes.h b/target/linux/brcm63xx/image/lzma-loader/src/LzmaTypes.h new file mode 100644 index 0000000..9c27290 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/LzmaTypes.h @@ -0,0 +1,45 @@ +/* +LzmaTypes.h + +Types for LZMA Decoder + +This file written and distributed to public domain by Igor Pavlov. +This file is part of LZMA SDK 4.40 (2006-05-01) +*/ + +#ifndef __LZMATYPES_H +#define __LZMATYPES_H + +#ifndef _7ZIP_BYTE_DEFINED +#define _7ZIP_BYTE_DEFINED +typedef unsigned char Byte; +#endif + +#ifndef _7ZIP_UINT16_DEFINED +#define _7ZIP_UINT16_DEFINED +typedef unsigned short UInt16; +#endif + +#ifndef _7ZIP_UINT32_DEFINED +#define _7ZIP_UINT32_DEFINED +#ifdef _LZMA_UINT32_IS_ULONG +typedef unsigned long UInt32; +#else +typedef unsigned int UInt32; +#endif +#endif + +/* #define _LZMA_NO_SYSTEM_SIZE_T */ +/* You can use it, if you don't want */ + +#ifndef _7ZIP_SIZET_DEFINED +#define _7ZIP_SIZET_DEFINED +#ifdef _LZMA_NO_SYSTEM_SIZE_T +typedef UInt32 SizeT; +#else +#include +typedef size_t SizeT; +#endif +#endif + +#endif diff --git a/target/linux/brcm63xx/image/lzma-loader/src/Makefile b/target/linux/brcm63xx/image/lzma-loader/src/Makefile new file mode 100644 index 0000000..50c22d8 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/Makefile @@ -0,0 +1,86 @@ +# +# Makefile for the LZMA compressed kernel loader for +# Atheros AR7XXX/AR9XXX based boards +# +# Copyright (C) 2011 Gabor Juhos +# +# Some parts of this file was based on the OpenWrt specific lzma-loader +# for the BCM47xx and ADM5120 based boards: +# Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) +# Copyright (C) 2005 Mineharu Takahara +# Copyright (C) 2005 by Oleg I. Vdovikin +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. +# + +LOADADDR := +LZMA_TEXT_START := 0x80a00000 +LOADER_DATA := + +CC := $(CROSS_COMPILE)gcc +LD := $(CROSS_COMPILE)ld +OBJCOPY := $(CROSS_COMPILE)objcopy +OBJDUMP := $(CROSS_COMPILE)objdump + +BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug -S + +CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \ + -mno-abicalls -fno-pic -ffunction-sections -pipe \ + -ffreestanding -fhonour-copts \ + -mabi=32 -march=mips32 \ + -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap +CFLAGS += -D_LZMA_PROB32 + +ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +LDFLAGS = -static --gc-sections -no-warn-mismatch +LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START) + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +OBJECTS := head.o loader.o cache.o board.o printf.o LzmaDecode.o + +ifneq ($(strip $(LOADER_DATA)),) +OBJECTS += data.o +CFLAGS += -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR) +endif + + +all: loader.elf + +# Don't build dependencies, this may die if $(CC) isn't gcc +dep: + +install: + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $< + +%.o : %.S + $(CC) $(ASFLAGS) -c -o $@ $< + +data.o: $(LOADER_DATA) + $(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $< + +loader: $(OBJECTS) + $(LD) $(LDFLAGS) -o $@ $(OBJECTS) + +loader.bin: loader + $(OBJCOPY) $(BIN_FLAGS) $< $@ + +loader2.o: loader.bin + $(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $< + +loader.elf: loader2.o + $(LD) -e startup -T loader2.lds -Ttext $(LOADADDR) -o $@ $< + +mrproper: clean + +clean: + rm -f loader *.elf *.bin *.o + + + diff --git a/target/linux/brcm63xx/image/lzma-loader/src/board.c b/target/linux/brcm63xx/image/lzma-loader/src/board.c new file mode 100644 index 0000000..28b9c53 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/board.c @@ -0,0 +1,111 @@ +/* + * BCM63XX specific implementation parts + * + * Copyright (C) 2014 Jonas Gorski + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include "config.h" +#include "cp0regdef.h" + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +#define UART_IR_REG 0x10 +#define UART_FIFO_REG 0x14 + +unsigned long uart_base; + +static void wait_xfered(void) +{ + unsigned int val; + + do { + val = READREG(uart_base + UART_IR_REG); + if (val & (1 << 5)) + break; + } while (1); +} + +void board_putc(int ch) +{ + if (!uart_base) + return; + + wait_xfered(); + WRITEREG(uart_base + UART_FIFO_REG, ch); + wait_xfered(); +} + +#define PRID_IMP_BMIPS32_REV4 0x4000 +#define PRID_IMP_BMIPS32_REV8 0x8000 +#define PRID_IMP_BMIPS3300 0x9000 +#define PRID_IMP_BMIPS3300_ALT 0x9100 +#define PRID_IMP_BMIPS3300_BUG 0x0000 +#define PRID_IMP_BMIPS43XX 0xa000 + +void board_init(void) +{ + unsigned long prid, chipid, chipid_reg; + + prid = read_32bit_c0_register($15, 0); + + switch (prid & 0xff00) { + case PRID_IMP_BMIPS32_REV4: + case PRID_IMP_BMIPS32_REV8: + case PRID_IMP_BMIPS3300_ALT: + case PRID_IMP_BMIPS3300_BUG: + chipid_reg = 0xfffe0000; + break; + case PRID_IMP_BMIPS3300: + if ((prid & 0xff) >= 0x33) + chipid_reg = 0xb0000000; + else + chipid_reg = 0xfffe0000; + break; + case PRID_IMP_BMIPS43XX: + if ((prid & 0xff) == 0x04) + chipid_reg = 0xfff8c000; + else if ((prid & 0xff) == 0x70) + chipid_reg = 0xb4e00000; + else if ((prid & 0xff) >= 0x30) + chipid_reg = 0xb0000000; + else + chipid_reg = 0xfffe0000; + break; + default: + return; + } + + chipid = READREG(chipid_reg); + + switch (chipid >> 16) { + case 0x3368: + case 0x6318: + case 0x6328: + case 0x6358: + case 0x6362: + case 0x6368: + case 0x6369: + uart_base = chipid_reg + 0x100; + break; + case 0x6316: + case 0x6326: + uart_base = chipid_reg + 0x180; + break; + case 0x3380: + uart_base = chipid_reg + 0x200; + break; + case 0x6338: + case 0x6345: + case 0x6348: + uart_base = chipid_reg + 0x300; + break; + default: + return; + } +} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/cache.c b/target/linux/brcm63xx/image/lzma-loader/src/cache.c new file mode 100644 index 0000000..93751c3 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/cache.c @@ -0,0 +1,46 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * The cache manipulation routine has been taken from the U-Boot project. + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cache.h" +#include "cacheops.h" +#include "config.h" +#include "printf.h" + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size + (lsize - 1)) & ~(lsize - 1); + + printf("blasting from 0x%08x to 0x%08x (0x%08x - 0x%08x)\n", start_addr, size, addr, aend); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/cache.h b/target/linux/brcm63xx/image/lzma-loader/src/cache.h new file mode 100644 index 0000000..506a235 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/cache.h @@ -0,0 +1,17 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __CACHE_H +#define __CACHE_H + +void flush_cache(unsigned long start_addr, unsigned long size); + +#endif /* __CACHE_H */ diff --git a/target/linux/brcm63xx/image/lzma-loader/src/cacheops.h b/target/linux/brcm63xx/image/lzma-loader/src/cacheops.h new file mode 100644 index 0000000..70bcad7 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/cacheops.h @@ -0,0 +1,85 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 + +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +#endif /* __ASM_CACHEOPS_H */ diff --git a/target/linux/brcm63xx/image/lzma-loader/src/config.h b/target/linux/brcm63xx/image/lzma-loader/src/config.h new file mode 100644 index 0000000..ce391f8 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/config.h @@ -0,0 +1,31 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#define CONFIG_ICACHE_SIZE (32 * 1024) +#define CONFIG_DCACHE_SIZE (32 * 1024) +#define CONFIG_CACHELINE_SIZE 16 + +#ifndef CONFIG_FLASH_OFFS +#define CONFIG_FLASH_OFFS 0 +#endif + +#ifndef CONFIG_FLASH_MAX +#define CONFIG_FLASH_MAX 0 +#endif + +#ifndef CONFIG_FLASH_STEP +#define CONFIG_FLASH_STEP 0x1000 +#endif + +#endif /* _CONFIG_H_ */ diff --git a/target/linux/brcm63xx/image/lzma-loader/src/cp0regdef.h b/target/linux/brcm63xx/image/lzma-loader/src/cp0regdef.h new file mode 100644 index 0000000..0d824f4 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/cp0regdef.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * + * Copyright (C) 2001, Monta Vista Software + * Author: jsun@mvista.com or jsun@junsun.net + */ +#ifndef _cp0regdef_h_ +#define _cp0regdef_h_ + +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 + +#define read_32bit_c0_register(reg,sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #reg "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #reg ", " #sel "\n\t" \ + ".set mips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#endif diff --git a/target/linux/brcm63xx/image/lzma-loader/src/head.S b/target/linux/brcm63xx/image/lzma-loader/src/head.S new file mode 100644 index 0000000..543996a --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/head.S @@ -0,0 +1,118 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "cp0regdef.h" +#include "cacheops.h" +#include "config.h" + +#define KSEG0 0x80000000 + + .macro ehb + sll zero, 3 + .endm + + .text + +LEAF(startup) + .set noreorder + .set mips32 + + mtc0 zero, CP0_WATCHLO # clear watch registers + mtc0 zero, CP0_WATCHHI + mtc0 zero, CP0_CAUSE # clear before writing status register + + mfc0 t0, CP0_STATUS + li t1, 0x1000001f + or t0, t1 + xori t0, 0x1f + mtc0 t0, CP0_STATUS + ehb + + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + ehb + + la t0, __reloc_label # get linked address of label + bal __reloc_label # branch and link to label to + nop # get actual address +__reloc_label: + subu t0, ra, t0 # get reloc_delta + + beqz t0, __reloc_done # if delta is 0 we are in the right place + nop + + /* Copy our code to the right place */ + la t1, _code_start # get linked address of _code_start + la t2, _code_end # get linked address of _code_end + addu t0, t0, t1 # calculate actual address of _code_start + +__reloc_copy: + lw t3, 0(t0) + sw t3, 0(t1) + add t1, 4 + blt t1, t2, __reloc_copy + add t0, 4 + + /* flush cache */ + la t0, _code_start + la t1, _code_end + + li t2, ~(CONFIG_CACHELINE_SIZE - 1) + and t0, t2 + and t1, t2 + li t2, CONFIG_CACHELINE_SIZE + + b __flush_check + nop + +__flush_line: + cache Hit_Writeback_Inv_D, 0(t0) + cache Hit_Invalidate_I, 0(t0) + add t0, t2 + +__flush_check: + bne t0, t1, __flush_line + nop + + sync + +__reloc_done: + + /* clear bss */ + la t0, _bss_start + la t1, _bss_end + b __bss_check + nop + +__bss_fill: + sw zero, 0(t0) + addi t0, 4 + +__bss_check: + bne t0, t1, __bss_fill + nop + + /* Setup new "C" stack */ + la sp, _stack + + /* jump to the decompressor routine */ + la t0, loader_main + jr t0 + nop + + .set reorder +END(startup) diff --git a/target/linux/brcm63xx/image/lzma-loader/src/loader.c b/target/linux/brcm63xx/image/lzma-loader/src/loader.c new file mode 100644 index 0000000..0848ce6 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/loader.c @@ -0,0 +1,175 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 Mineharu Takahara + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * The image_header structure has been taken from the U-Boot project. + * (C) Copyright 2008 Semihalf + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "config.h" +#include "cache.h" +#include "printf.h" +#include "LzmaDecode.h" + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) + +#undef LZMA_DEBUG + +#ifdef LZMA_DEBUG +# define DBG(f, a...) printf(f, ## a) +#else +# define DBG(f, a...) do {} while (0) +#endif + +/* beyond the image end, size not known in advance */ +extern unsigned char workspace[]; + + +extern void board_init(void); + +static CLzmaDecoderState lzma_state; +static unsigned char *lzma_data; +static unsigned long lzma_datasize; +static unsigned long lzma_outsize; +static unsigned long kernel_la; + +static void halt(void) +{ + printf("\nSystem halted!\n"); + for(;;); +} + +static __inline__ unsigned char lzma_get_byte(void) +{ + unsigned char c; + + lzma_datasize--; + c = *lzma_data++; + + return c; +} + +static int lzma_init_props(void) +{ + unsigned char props[LZMA_PROPERTIES_SIZE]; + int res; + int i; + + /* read lzma properties */ + for (i = 0; i < LZMA_PROPERTIES_SIZE; i++) + props[i] = lzma_get_byte(); + + /* read the lower half of uncompressed size in the header */ + lzma_outsize = ((SizeT) lzma_get_byte()) + + ((SizeT) lzma_get_byte() << 8) + + ((SizeT) lzma_get_byte() << 16) + + ((SizeT) lzma_get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + for (i = 0; i < 4; i++) + lzma_get_byte(); + + res = LzmaDecodeProperties(&lzma_state.Properties, props, + LZMA_PROPERTIES_SIZE); + return res; +} + +static int lzma_decompress(unsigned char *outStream) +{ + SizeT ip, op; + int ret; + + lzma_state.Probs = (CProb *) workspace; + + ret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream, + lzma_outsize, &op); + + if (ret != LZMA_RESULT_OK) { + int i; + + DBG("LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\n", + ret, lzma_data + ip, lzma_outsize, ip, op); + + for (i = 0; i < 16; i++) + DBG("%02x ", lzma_data[ip + i]); + + DBG("\n"); + } + + return ret; +} + +static void lzma_init_data(void) +{ + extern unsigned char _lzma_data_start[]; + extern unsigned char _lzma_data_end[]; + + kernel_la = LOADADDR; + lzma_data = _lzma_data_start; + lzma_datasize = _lzma_data_end - _lzma_data_start; +} + +void loader_main(unsigned long reg_a0, unsigned long reg_a1, + unsigned long reg_a2, unsigned long reg_a3) +{ + void (*kernel_entry) (unsigned long, unsigned long, unsigned long, + unsigned long); + int res; + + board_init(); + + printf("\n\nOpenWrt kernel loader for BCM63XX\n"); + printf("Copyright (C) 2011 Gabor Juhos \n"); + printf("Copyright (C) 2014 Jonas Gorski \n"); + + lzma_init_data(); + + res = lzma_init_props(); + if (res != LZMA_RESULT_OK) { + printf("Incorrect LZMA stream properties!\n"); + halt(); + } + + printf("Decompressing kernel... "); + + res = lzma_decompress((unsigned char *) kernel_la); + if (res != LZMA_RESULT_OK) { + printf("failed, "); + switch (res) { + case LZMA_RESULT_DATA_ERROR: + printf("data error!\n"); + break; + default: + printf("unknown error %d!\n", res); + } + halt(); + } else { + printf("done!\n"); + } + + flush_cache(kernel_la, lzma_outsize); + + printf("Starting kernel at %08x...\n\n", kernel_la); + + kernel_entry = (void *) kernel_la; + kernel_entry(reg_a0, reg_a1, reg_a2, reg_a3); +} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/loader.lds b/target/linux/brcm63xx/image/lzma-loader/src/loader.lds new file mode 100644 index 0000000..01ff852 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/loader.lds @@ -0,0 +1,34 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + _code_start = .; + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.data.lzma) + } + + . = ALIGN(32); + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(32); + _code_end = .; + + _bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + } + + . = ALIGN(32); + _bss_end = .; + + . = . + 8192; + _stack = .; + + workspace = .; +} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/loader2.lds b/target/linux/brcm63xx/image/lzma-loader/src/loader2.lds new file mode 100644 index 0000000..db0bb46 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/loader2.lds @@ -0,0 +1,10 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + startup = .; + *(.text) + *(.text.*) + *(.data) + *(.data.*) + } +} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/lzma-data.lds b/target/linux/brcm63xx/image/lzma-loader/src/lzma-data.lds new file mode 100644 index 0000000..abf756b --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/lzma-data.lds @@ -0,0 +1,8 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .data.lzma : { + _lzma_data_start = .; + *(.data) + _lzma_data_end = .; + } +} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/printf.c b/target/linux/brcm63xx/image/lzma-loader/src/printf.c new file mode 100644 index 0000000..7bb5a86 --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/printf.c @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "printf.h" + +extern void board_putc(int ch); + +/* this is the maximum width for a variable */ +#define LP_MAX_BUF 256 + +/* macros */ +#define IsDigit(x) ( ((x) >= '0') && ((x) <= '9') ) +#define Ctod(x) ( (x) - '0') + +/* forward declaration */ +static int PrintChar(char *, char, int, int); +static int PrintString(char *, char *, int, int); +static int PrintNum(char *, unsigned long, int, int, int, int, char, int); + +/* private variable */ +static const char theFatalMsg[] = "fatal error in lp_Print!"; + +/* -*- + * A low level printf() function. + */ +static void +lp_Print(void (*output)(void *, char *, int), + void * arg, + char *fmt, + va_list ap) +{ + +#define OUTPUT(arg, s, l) \ + { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \ + (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \ + } else { \ + (*output)(arg, s, l); \ + } \ + } + + char buf[LP_MAX_BUF]; + + char c; + char *s; + long int num; + + int longFlag; + int negFlag; + int width; + int prec; + int ladjust; + char padc; + + int length; + + for(;;) { + { + /* scan for the next '%' */ + char *fmtStart = fmt; + while ( (*fmt != '\0') && (*fmt != '%')) { + fmt ++; + } + + /* flush the string found so far */ + OUTPUT(arg, fmtStart, fmt-fmtStart); + + /* are we hitting the end? */ + if (*fmt == '\0') break; + } + + /* we found a '%' */ + fmt ++; + + /* check for long */ + if (*fmt == 'l') { + longFlag = 1; + fmt ++; + } else { + longFlag = 0; + } + + /* check for other prefixes */ + width = 0; + prec = -1; + ladjust = 0; + padc = ' '; + + if (*fmt == '-') { + ladjust = 1; + fmt ++; + } + + if (*fmt == '0') { + padc = '0'; + fmt++; + } + + if (IsDigit(*fmt)) { + while (IsDigit(*fmt)) { + width = 10 * width + Ctod(*fmt++); + } + } + + if (*fmt == '.') { + fmt ++; + if (IsDigit(*fmt)) { + prec = 0; + while (IsDigit(*fmt)) { + prec = prec*10 + Ctod(*fmt++); + } + } + } + + + /* check format flag */ + negFlag = 0; + switch (*fmt) { + case 'b': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'd': + case 'D': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + if (num < 0) { + num = - num; + negFlag = 1; + } + length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'o': + case 'O': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'u': + case 'U': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'x': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'X': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1); + OUTPUT(arg, buf, length); + break; + + case 'c': + c = (char)va_arg(ap, int); + length = PrintChar(buf, c, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case 's': + s = (char*)va_arg(ap, char *); + length = PrintString(buf, s, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case '\0': + fmt --; + break; + + default: + /* output this char as it is */ + OUTPUT(arg, fmt, 1); + } /* switch (*fmt) */ + + fmt ++; + } /* for(;;) */ + + /* special termination call */ + OUTPUT(arg, "\0", 1); +} + + +/* --------------- local help functions --------------------- */ +static int +PrintChar(char * buf, char c, int length, int ladjust) +{ + int i; + + if (length < 1) length = 1; + if (ladjust) { + *buf = c; + for (i=1; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-1; i++) buf[i] = ' '; + buf[length - 1] = c; + } + return length; +} + +static int +PrintString(char * buf, char* s, int length, int ladjust) +{ + int i; + int len=0; + char* s1 = s; + while (*s1++) len++; + if (length < len) length = len; + + if (ladjust) { + for (i=0; i< len; i++) buf[i] = s[i]; + for (i=len; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-len; i++) buf[i] = ' '; + for (i=length-len; i < length; i++) buf[i] = s[i-length+len]; + } + return length; +} + +static int +PrintNum(char * buf, unsigned long u, int base, int negFlag, + int length, int ladjust, char padc, int upcase) +{ + /* algorithm : + * 1. prints the number from left to right in reverse form. + * 2. fill the remaining spaces with padc if length is longer than + * the actual length + * TRICKY : if left adjusted, no "0" padding. + * if negtive, insert "0" padding between "0" and number. + * 3. if (!ladjust) we reverse the whole string including paddings + * 4. otherwise we only reverse the actual string representing the num. + */ + + int actualLength =0; + char *p = buf; + int i; + + do { + int tmp = u %base; + if (tmp <= 9) { + *p++ = '0' + tmp; + } else if (upcase) { + *p++ = 'A' + tmp - 10; + } else { + *p++ = 'a' + tmp - 10; + } + u /= base; + } while (u != 0); + + if (negFlag) { + *p++ = '-'; + } + + /* figure out actual length and adjust the maximum length */ + actualLength = p - buf; + if (length < actualLength) length = actualLength; + + /* add padding */ + if (ladjust) { + padc = ' '; + } + if (negFlag && !ladjust && (padc == '0')) { + for (i = actualLength-1; i< length-1; i++) buf[i] = padc; + buf[length -1] = '-'; + } else { + for (i = actualLength; i< length; i++) buf[i] = padc; + } + + + /* prepare to reverse the string */ + { + int begin = 0; + int end; + if (ladjust) { + end = actualLength - 1; + } else { + end = length -1; + } + + while (end > begin) { + char tmp = buf[begin]; + buf[begin] = buf[end]; + buf[end] = tmp; + begin ++; + end --; + } + } + + /* adjust the string pointer */ + return length; +} + +static void printf_output(void *arg, char *s, int l) +{ + int i; + + // special termination call + if ((l==1) && (s[0] == '\0')) return; + + for (i=0; i< l; i++) { + board_putc(s[i]); + if (s[i] == '\n') board_putc('\r'); + } +} + +void printf(char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + lp_Print(printf_output, 0, fmt, ap); + va_end(ap); +} diff --git a/target/linux/brcm63xx/image/lzma-loader/src/printf.h b/target/linux/brcm63xx/image/lzma-loader/src/printf.h new file mode 100644 index 0000000..9b1c1df --- /dev/null +++ b/target/linux/brcm63xx/image/lzma-loader/src/printf.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _printf_h_ +#define _printf_h_ + +#include +void printf(char *fmt, ...); + +#endif /* _printf_h_ */ diff --git a/target/linux/brcm63xx/modules.mk b/target/linux/brcm63xx/modules.mk new file mode 100644 index 0000000..6f6aa38 --- /dev/null +++ b/target/linux/brcm63xx/modules.mk @@ -0,0 +1,38 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/pcmcia-bcm63xx + SUBMENU:=$(PCMCIA_MENU) + TITLE:=Broadcom BCM63xx PCMCIA support + DEPENDS:=@TARGET_brcm63xx +kmod-pcmcia-rsrc + KCONFIG:=CONFIG_PCMCIA_BCM63XX + FILES:=$(LINUX_DIR)/drivers/pcmcia/bcm63xx_pcmcia.ko + AUTOLOAD:=$(call AutoLoad,41,bcm63xx_pcmcia) +endef + +define KernelPackage/pcmcia-bcm63xx/description + Kernel support for PCMCIA/CardBus controller on the BCM63xx SoC +endef + +$(eval $(call KernelPackage,pcmcia-bcm63xx)) + +define KernelPackage/bcm63xx-udc + SUBMENU:=$(USB_MENU) + TITLE:=Broadcom BCM63xx UDC support + DEPENDS:=@TARGET_brcm63xx +kmod-usb-gadget + KCONFIG:=CONFIG_USB_BCM63XX_UDC + FILES:= \ + $(LINUX_DIR)/drivers/usb/gadget/udc/bcm63xx_udc.ko + AUTOLOAD:=$(call AutoLoad,51,bcm63xx_udc) + $(call AddDepends/usb) +endef + +define KernelPackage/bcm63xx-udc/description + Kernel support for the USB gadget (device) controller on the BCM63xx SoC +endef + +$(eval $(call KernelPackage,bcm63xx-udc)) diff --git a/target/linux/brcm63xx/patches-3.18/001-spi-spi-gpio-Add-dt-support-for-a-single-device-with.patch b/target/linux/brcm63xx/patches-3.18/001-spi-spi-gpio-Add-dt-support-for-a-single-device-with.patch new file mode 100644 index 0000000..437448f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/001-spi-spi-gpio-Add-dt-support-for-a-single-device-with.patch @@ -0,0 +1,91 @@ +From d1d81802522ade84128a2c66c0d500e372474dca Mon Sep 17 00:00:00 2001 +From: Torsten Fleischer +Date: Mon, 3 Nov 2014 17:17:55 +0100 +Subject: [PATCH] spi: spi-gpio: Add dt support for a single device with no + chip select + +In order to describe a single slave device that has no chip select line +the 'num-chipselects' property has to be <0> and the 'cs-gpios' property +doesn't need to be set. + +Signed-off-by: Torsten Fleischer +Signed-off-by: Mark Brown +--- + Documentation/devicetree/bindings/spi/spi-gpio.txt | 6 ++++-- + drivers/spi/spi-gpio.c | 21 +++++++++++++++------ + 2 files changed, 19 insertions(+), 8 deletions(-) + +--- a/Documentation/devicetree/bindings/spi/spi-gpio.txt ++++ b/Documentation/devicetree/bindings/spi/spi-gpio.txt +@@ -8,8 +8,10 @@ Required properties: + - gpio-sck: GPIO spec for the SCK line to use + - gpio-miso: GPIO spec for the MISO line to use + - gpio-mosi: GPIO spec for the MOSI line to use +- - cs-gpios: GPIOs to use for chipselect lines +- - num-chipselects: number of chipselect lines ++ - cs-gpios: GPIOs to use for chipselect lines. ++ Not needed if num-chipselects = <0>. ++ - num-chipselects: Number of chipselect lines. Should be <0> if a single device ++ with no chip select is connected. + + Example: + +--- a/drivers/spi/spi-gpio.c ++++ b/drivers/spi/spi-gpio.c +@@ -424,6 +424,7 @@ static int spi_gpio_probe(struct platfor + struct spi_gpio_platform_data *pdata; + u16 master_flags = 0; + bool use_of = 0; ++ int num_devices; + + status = spi_gpio_probe_dt(pdev); + if (status < 0) +@@ -433,16 +434,21 @@ static int spi_gpio_probe(struct platfor + + pdata = dev_get_platdata(&pdev->dev); + #ifdef GENERIC_BITBANG +- if (!pdata || !pdata->num_chipselect) ++ if (!pdata || (!use_of && !pdata->num_chipselect)) + return -ENODEV; + #endif + ++ if (use_of && !SPI_N_CHIPSEL) ++ num_devices = 1; ++ else ++ num_devices = SPI_N_CHIPSEL; ++ + status = spi_gpio_request(pdata, dev_name(&pdev->dev), &master_flags); + if (status < 0) + return status; + + master = spi_alloc_master(&pdev->dev, sizeof(*spi_gpio) + +- (sizeof(int) * SPI_N_CHIPSEL)); ++ (sizeof(int) * num_devices)); + if (!master) { + status = -ENOMEM; + goto gpio_free; +@@ -457,7 +463,7 @@ static int spi_gpio_probe(struct platfor + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); + master->flags = master_flags; + master->bus_num = pdev->id; +- master->num_chipselect = SPI_N_CHIPSEL; ++ master->num_chipselect = num_devices; + master->setup = spi_gpio_setup; + master->cleanup = spi_gpio_cleanup; + #ifdef CONFIG_OF +@@ -472,9 +478,12 @@ static int spi_gpio_probe(struct platfor + * property of the node. + */ + +- for (i = 0; i < SPI_N_CHIPSEL; i++) +- spi_gpio->cs_gpios[i] = +- of_get_named_gpio(np, "cs-gpios", i); ++ if (!SPI_N_CHIPSEL) ++ spi_gpio->cs_gpios[0] = SPI_GPIO_NO_CHIPSELECT; ++ else ++ for (i = 0; i < SPI_N_CHIPSEL; i++) ++ spi_gpio->cs_gpios[i] = ++ of_get_named_gpio(np, "cs-gpios", i); + } + #endif + diff --git a/target/linux/brcm63xx/patches-3.18/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch b/target/linux/brcm63xx/patches-3.18/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch new file mode 100644 index 0000000..cfa7298 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch @@ -0,0 +1,98 @@ +From 0f84c305351c993e4307e1e8c128d44760314e31 Mon Sep 17 00:00:00 2001 +From: Andrew Bresticker +Date: Thu, 18 Sep 2014 14:47:07 -0700 +Subject: [PATCH 1/3] MIPS: Always use IRQ domains for CPU IRQs + +Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases. + +Signed-off-by: Andrew Bresticker +Reviewed-by: Qais Yousef +Tested-by: Qais Yousef +Cc: Thomas Gleixner +Cc: Jason Cooper +Cc: Andrew Bresticker +Cc: Jeffrey Deans +Cc: Markos Chandras +Cc: Paul Burton +Cc: Qais Yousef +Cc: Jonas Gorski +Cc: John Crispin +Cc: David Daney +Cc: linux-mips@linux-mips.org +Cc: linux-kernel@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/7799/ +Signed-off-by: Ralf Baechle +--- + arch/mips/Kconfig | 1 + + arch/mips/kernel/irq_cpu.c | 36 +++++++++++------------------------- + 2 files changed, 12 insertions(+), 25 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1056,6 +1056,7 @@ config MIPS_HUGE_TLB_SUPPORT + + config IRQ_CPU + bool ++ select IRQ_DOMAIN + + config IRQ_CPU_RM7K + bool +--- a/arch/mips/kernel/irq_cpu.c ++++ b/arch/mips/kernel/irq_cpu.c +@@ -98,28 +98,6 @@ static struct irq_chip mips_mt_cpu_irq_c + .irq_enable = unmask_mips_irq, + }; + +-void __init mips_cpu_irq_init(void) +-{ +- int irq_base = MIPS_CPU_IRQ_BASE; +- int i; +- +- /* Mask interrupts. */ +- clear_c0_status(ST0_IM); +- clear_c0_cause(CAUSEF_IP); +- +- /* Software interrupts are used for MT/CMT IPI */ +- for (i = irq_base; i < irq_base + 2; i++) +- irq_set_chip_and_handler(i, cpu_has_mipsmt ? +- &mips_mt_cpu_irq_controller : +- &mips_cpu_irq_controller, +- handle_percpu_irq); +- +- for (i = irq_base + 2; i < irq_base + 8; i++) +- irq_set_chip_and_handler(i, &mips_cpu_irq_controller, +- handle_percpu_irq); +-} +- +-#ifdef CONFIG_IRQ_DOMAIN + static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) + { +@@ -142,8 +120,7 @@ static const struct irq_domain_ops mips_ + .xlate = irq_domain_xlate_onecell, + }; + +-int __init mips_cpu_intc_init(struct device_node *of_node, +- struct device_node *parent) ++static void __init __mips_cpu_irq_init(struct device_node *of_node) + { + struct irq_domain *domain; + +@@ -155,7 +132,16 @@ int __init mips_cpu_intc_init(struct dev + &mips_cpu_intc_irq_domain_ops, NULL); + if (!domain) + panic("Failed to add irqdomain for MIPS CPU"); ++} + ++void __init mips_cpu_irq_init(void) ++{ ++ __mips_cpu_irq_init(NULL); ++} ++ ++int __init mips_cpu_intc_init(struct device_node *of_node, ++ struct device_node *parent) ++{ ++ __mips_cpu_irq_init(of_node); + return 0; + } +-#endif /* CONFIG_IRQ_DOMAIN */ diff --git a/target/linux/brcm63xx/patches-3.18/031-MIPS-Rename-mips_cpu_intc_init-mips_cpu_irq_of_init.patch b/target/linux/brcm63xx/patches-3.18/031-MIPS-Rename-mips_cpu_intc_init-mips_cpu_irq_of_init.patch new file mode 100644 index 0000000..141644f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/031-MIPS-Rename-mips_cpu_intc_init-mips_cpu_irq_of_init.patch @@ -0,0 +1,89 @@ +From afe8dc254711b72ba8144295f4a8fcc66d30572d Mon Sep 17 00:00:00 2001 +From: Andrew Bresticker +Date: Thu, 18 Sep 2014 14:47:08 -0700 +Subject: [PATCH 2/3] MIPS: Rename mips_cpu_intc_init() -> + mips_cpu_irq_of_init() + +mips_cpu_intc_init() is used for DT-based initialization of the CPU +IRQ domain. Give it a more appropriate name. + +Signed-off-by: Andrew Bresticker +Reviewed-by: Qais Yousef +Tested-by: Qais Yousef +Cc: Thomas Gleixner +Cc: Jason Cooper +Cc: Andrew Bresticker +Cc: Jeffrey Deans +Cc: Markos Chandras +Cc: Paul Burton +Cc: Qais Yousef +Cc: Jonas Gorski +Cc: John Crispin +Cc: David Daney +Cc: linux-mips@linux-mips.org +Cc: linux-kernel@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/7800/ +Signed-off-by: Ralf Baechle +--- + Documentation/devicetree/bindings/mips/cpu_irq.txt | 4 ++-- + arch/mips/include/asm/irq_cpu.h | 4 ++-- + arch/mips/kernel/irq_cpu.c | 4 ++-- + arch/mips/ralink/irq.c | 2 +- + 4 files changed, 7 insertions(+), 7 deletions(-) + +--- a/Documentation/devicetree/bindings/mips/cpu_irq.txt ++++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt +@@ -1,6 +1,6 @@ + MIPS CPU interrupt controller + +-On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU ++On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU + IRQs from a devicetree file and create a irq_domain for IRQ controller. + + With the irq_domain in place we can describe how the 8 IRQs are wired to the +@@ -36,7 +36,7 @@ Example devicetree: + + Example platform irq.c: + static struct of_device_id __initdata of_irq_ids[] = { +- { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init }, ++ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, + { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, + {}, + }; +--- a/arch/mips/include/asm/irq_cpu.h ++++ b/arch/mips/include/asm/irq_cpu.h +@@ -19,8 +19,8 @@ extern void rm9k_cpu_irq_init(void); + + #ifdef CONFIG_IRQ_DOMAIN + struct device_node; +-extern int mips_cpu_intc_init(struct device_node *of_node, +- struct device_node *parent); ++extern int mips_cpu_irq_of_init(struct device_node *of_node, ++ struct device_node *parent); + #endif + + #endif /* _ASM_IRQ_CPU_H */ +--- a/arch/mips/kernel/irq_cpu.c ++++ b/arch/mips/kernel/irq_cpu.c +@@ -139,8 +139,8 @@ void __init mips_cpu_irq_init(void) + __mips_cpu_irq_init(NULL); + } + +-int __init mips_cpu_intc_init(struct device_node *of_node, +- struct device_node *parent) ++int __init mips_cpu_irq_of_init(struct device_node *of_node, ++ struct device_node *parent) + { + __mips_cpu_irq_init(of_node); + return 0; +--- a/arch/mips/ralink/irq.c ++++ b/arch/mips/ralink/irq.c +@@ -173,7 +173,7 @@ static int __init intc_of_init(struct de + } + + static struct of_device_id __initdata of_irq_ids[] = { +- { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init }, ++ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, + { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, + {}, + }; diff --git a/target/linux/brcm63xx/patches-3.18/032-MIPS-Provide-a-generic-plat_irq_dispatch.patch b/target/linux/brcm63xx/patches-3.18/032-MIPS-Provide-a-generic-plat_irq_dispatch.patch new file mode 100644 index 0000000..8f5bd31 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/032-MIPS-Provide-a-generic-plat_irq_dispatch.patch @@ -0,0 +1,58 @@ +From 85f7cdacbb81db8c4cc8e474837eab1f0e4ff77b Mon Sep 17 00:00:00 2001 +From: Andrew Bresticker +Date: Thu, 18 Sep 2014 14:47:09 -0700 +Subject: [PATCH 3/3] MIPS: Provide a generic plat_irq_dispatch + +For platforms which boot with device-tree or have correctly chained +all external interrupt controllers, a generic plat_irq_dispatch() can +be used. Implement a plat_irq_dispatch() which simply handles all the +pending interrupts as reported by C0_Cause. + +Signed-off-by: Andrew Bresticker +Reviewed-by: Qais Yousef +Tested-by: Qais Yousef +Cc: Thomas Gleixner +Cc: Jason Cooper +Cc: Andrew Bresticker +Cc: Jeffrey Deans +Cc: Markos Chandras +Cc: Paul Burton +Cc: Qais Yousef +Cc: Jonas Gorski +Cc: John Crispin +Cc: David Daney +Cc: linux-mips@linux-mips.org +Cc: linux-kernel@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/7801/ +Signed-off-by: Ralf Baechle +--- + arch/mips/kernel/irq_cpu.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/mips/kernel/irq_cpu.c ++++ b/arch/mips/kernel/irq_cpu.c +@@ -98,6 +98,24 @@ static struct irq_chip mips_mt_cpu_irq_c + .irq_enable = unmask_mips_irq, + }; + ++asmlinkage void __weak plat_irq_dispatch(void) ++{ ++ unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM; ++ int irq; ++ ++ if (!pending) { ++ spurious_interrupt(); ++ return; ++ } ++ ++ pending >>= CAUSEB_IP; ++ while (pending) { ++ irq = fls(pending) - 1; ++ do_IRQ(MIPS_CPU_IRQ_BASE + irq); ++ pending &= ~BIT(irq); ++ } ++} ++ + static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) + { diff --git a/target/linux/brcm63xx/patches-3.18/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch b/target/linux/brcm63xx/patches-3.18/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch new file mode 100644 index 0000000..63d385b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch @@ -0,0 +1,28 @@ +From 80a2f983e9f44dbc3e01ae31c62d877846a7f791 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:19 +0100 +Subject: [PATCH 01/11] MIPS: BCM63XX: add USB host clock enable delay + +Knowledge of the clock setup delay should remain at the clock level (so +it can be clock specific and CPU specific). Add the 100 milliseconds +required clock delay for the USB host clock when it gets enabled. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/clk.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -177,6 +177,11 @@ static void usbh_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); ++ else ++ return; ++ ++ if (enable) ++ msleep(100); + } + + static struct clk clk_usbh = { diff --git a/target/linux/brcm63xx/patches-3.18/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch b/target/linux/brcm63xx/patches-3.18/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch new file mode 100644 index 0000000..5b2c03f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch @@ -0,0 +1,41 @@ +From 8e9bf528a122741f0171b89c297b63041116d704 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:20 +0100 +Subject: [PATCH 02/11] MIPS: BCM63XX: add USB device clock enable delay to + clock code + +This patch adds the required 10 micro seconds delay to the USB device +clock enable operation. Put this where the correct clock knowledege is, +which is in the clock code, and remove this delay from the bcm63xx_udc +gadget driver where it was before. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/clk.c | 5 +++++ + drivers/usb/gadget/bcm63xx_udc.c | 1 - + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -199,6 +199,11 @@ static void usbd_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); ++ else ++ return; ++ ++ if (enable) ++ udelay(10); + } + + static struct clk clk_usbd = { +--- a/drivers/usb/gadget/udc/bcm63xx_udc.c ++++ b/drivers/usb/gadget/udc/bcm63xx_udc.c +@@ -391,7 +391,6 @@ static inline void set_clocks(struct bcm + if (is_enabled) { + clk_enable(udc->usbh_clk); + clk_enable(udc->usbd_clk); +- udelay(10); + } else { + clk_disable(udc->usbd_clk); + clk_disable(udc->usbh_clk); diff --git a/target/linux/brcm63xx/patches-3.18/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch b/target/linux/brcm63xx/patches-3.18/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch new file mode 100644 index 0000000..5d106f8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch @@ -0,0 +1,151 @@ +From ac9b0b574d54be28b300bf99ffe092a2c589484f Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:21 +0100 +Subject: [PATCH 03/11] MIPS: BCM63XX: move code touching the USB private + register + +This patch moves the code touching the USB private register in the +bcm63xx USB gadget driver to arch/mips/bcm63xx/usb-common.c in +preparation for adding support for OHCI and EHCI host controllers which +will also touch the USB private register. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/usb-common.c | 53 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h | 9 ++++ + drivers/usb/gadget/bcm63xx_udc.c | 27 ++-------- + 4 files changed, 67 insertions(+), 24 deletions(-) + create mode 100644 arch/mips/bcm63xx/usb-common.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,7 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-usbd.o ++ dev-wdt.o dev-usb-usbd.o usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -0,0 +1,53 @@ ++/* ++ * Broadcom BCM63xx common USB device configuration code ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2012 Kevin Cernekee ++ * Copyright (C) 2012 Broadcom Corporation ++ * ++ */ ++#include ++ ++#include ++#include ++#include ++#include ++ ++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device) ++{ ++ u32 val; ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); ++ if (is_device) { ++ val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); ++ val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ } else { ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ } ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ if (is_device) ++ val |= USBH_PRIV_SWAP_USBD_MASK; ++ else ++ val &= ~USBH_PRIV_SWAP_USBD_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++} ++EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode); ++ ++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on) ++{ ++ u32 val; ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); ++ if (is_on) ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ else ++ val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++} ++EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup); +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h +@@ -0,0 +1,9 @@ ++#ifndef BCM63XX_USB_PRIV_H_ ++#define BCM63XX_USB_PRIV_H_ ++ ++#include ++ ++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device); ++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on); ++ ++#endif /* BCM63XX_USB_PRIV_H_ */ +--- a/drivers/usb/gadget/udc/bcm63xx_udc.c ++++ b/drivers/usb/gadget/udc/bcm63xx_udc.c +@@ -40,6 +40,7 @@ + #include + #include + #include ++#include + + #define DRV_MODULE_NAME "bcm63xx_udc" + +@@ -868,22 +869,7 @@ static void bcm63xx_select_phy_mode(stru + bcm_gpio_writel(val, GPIO_PINMUX_OTHR_REG); + } + +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); +- if (is_device) { +- val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); +- val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- } else { +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- } +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); +- +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); +- if (is_device) +- val |= USBH_PRIV_SWAP_USBD_MASK; +- else +- val &= ~USBH_PRIV_SWAP_USBD_MASK; +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++ bcm63xx_usb_priv_select_phy_mode(portmask, is_device); + } + + /** +@@ -897,14 +883,9 @@ static void bcm63xx_select_phy_mode(stru + */ + static void bcm63xx_select_pullup(struct bcm63xx_udc *udc, bool is_on) + { +- u32 val, portmask = BIT(udc->pd->port_no); ++ u32 portmask = BIT(udc->pd->port_no); + +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); +- if (is_on) +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- else +- val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ bcm63xx_usb_priv_select_pullup(portmask, is_on); + } + + /** diff --git a/target/linux/brcm63xx/patches-3.18/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch b/target/linux/brcm63xx/patches-3.18/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch new file mode 100644 index 0000000..40bbe08 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch @@ -0,0 +1,169 @@ +From 28758a9da77954ed323f86123ef448c6a563c037 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:22 +0100 +Subject: [PATCH 04/11] MIPS: BCM63XX: add OHCI/EHCI configuration bits to + common USB code + +This patch updates the common USB code touching the USB private +registers with the specific bits to properly enable OHCI and EHCI +controllers on BCM63xx SoCs. As a result we now need to protect access +to Read Modify Write sequences using a spinlock because we cannot +guarantee that any of the exposed helper will not be called +concurrently. + +Signed-off-by: Maxime Bizon +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/usb-common.c | 97 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h | 2 + + 2 files changed, 99 insertions(+) + +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -5,10 +5,12 @@ + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * ++ * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2012 Kevin Cernekee + * Copyright (C) 2012 Broadcom Corporation + * + */ ++#include + #include + + #include +@@ -16,9 +18,14 @@ + #include + #include + ++static DEFINE_SPINLOCK(usb_priv_reg_lock); ++ + void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device) + { + u32 val; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); + + val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); + if (is_device) { +@@ -36,12 +43,17 @@ void bcm63xx_usb_priv_select_phy_mode(u3 + else + val &= ~USBH_PRIV_SWAP_USBD_MASK; + bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); + } + EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode); + + void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on) + { + u32 val; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); + + val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); + if (is_on) +@@ -49,5 +61,90 @@ void bcm63xx_usb_priv_select_pullup(u32 + else + val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); + bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); + } + EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup); ++ ++/* The following array represents the meaning of the DESC/DATA ++ * endian swapping with respect to the CPU configured endianness ++ * ++ * DATA ENDN mmio descriptor ++ * 0 0 BE invalid ++ * 0 1 BE LE ++ * 1 0 BE BE ++ * 1 1 BE invalid ++ * ++ * Since BCM63XX SoCs are configured to be in big-endian mode ++ * we want configuration at line 3. ++ */ ++void bcm63xx_usb_priv_ohci_cfg_set(void) ++{ ++ u32 reg; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); ++ ++ if (BCMCPU_IS_6348()) ++ bcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG); ++ else if (BCMCPU_IS_6358()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG); ++ /* ++ * The magic value comes for the original vendor BSP ++ * and is needed for USB to work. Datasheet does not ++ * help, so the magic value is used as-is. ++ */ ++ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, ++ USBH_PRIV_TEST_6358_REG); ++ ++ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); ++} ++ ++void bcm63xx_usb_priv_ehci_cfg_set(void) ++{ ++ u32 reg; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); ++ ++ if (BCMCPU_IS_6358()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG); ++ ++ /* ++ * The magic value comes for the original vendor BSP ++ * and is needed for USB to work. Datasheet does not ++ * help, so the magic value is used as-is. ++ */ ++ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, ++ USBH_PRIV_TEST_6358_REG); ++ ++ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); ++} +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h +@@ -5,5 +5,7 @@ + + void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device); + void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on); ++void bcm63xx_usb_priv_ohci_cfg_set(void); ++void bcm63xx_usb_priv_ehci_cfg_set(void); + + #endif /* BCM63XX_USB_PRIV_H_ */ diff --git a/target/linux/brcm63xx/patches-3.18/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch b/target/linux/brcm63xx/patches-3.18/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch new file mode 100644 index 0000000..768dcca --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch @@ -0,0 +1,62 @@ +From 94ec618bd1a6b07fafbbfc9bcc54e7f9360ff9a0 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:23 +0100 +Subject: [PATCH 05/11] MIPS: BCM63XX: introduce BCM63XX_OHCI configuration + symbol + +This configuration symbol can be used by CPUs supporting the on-chip +OHCI controller, and ensures that all relevant OHCI-related +configuration options are correctly selected. So far, OHCI support is +available for the 6328, 6348, 6358 and 6358 SoCs. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Kconfig | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -6,10 +6,17 @@ config BCM63XX_CPU_3368 + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + ++config BCM63XX_OHCI ++ bool ++ select USB_ARCH_HAS_OHCI ++ select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD ++ select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6338 + bool "support 6338 CPU" +@@ -24,21 +31,25 @@ config BCM63XX_CPU_6348 + bool "support 6348 CPU" + select SYS_HAS_CPU_BMIPS32_3300 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6358 + bool "support 6358 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6362 + bool "support 6362 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6368 + bool "support 6368 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" diff --git a/target/linux/brcm63xx/patches-3.18/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch b/target/linux/brcm63xx/patches-3.18/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch new file mode 100644 index 0000000..111d481 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch @@ -0,0 +1,138 @@ +From 30d22baef255c99a12c4858ce4ab0d45f0d8c9ae Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:24 +0100 +Subject: [PATCH 06/11] MIPS: BCM63XX: add support for the on-chip OHCI + controller + +Broadcom BCM63XX SoCs include an on-chip OHCI controller which can be +driven by the ohci-platform generic driver by using specific power +on/off/suspend callback to manage clocks and hardware specific +configuration. + +Signed-off-by: Maxime Bizon +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/dev-usb-ohci.c | 94 ++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h | 6 ++ + 3 files changed, 101 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/dev-usb-ohci.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,7 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-usbd.o usb-common.o ++ dev-wdt.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/dev-usb-ohci.c +@@ -0,0 +1,94 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2013 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static struct resource ohci_resources[] = { ++ { ++ .start = -1, /* filled at runtime */ ++ .end = -1, /* filled at runtime */ ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = -1, /* filled at runtime */ ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ohci_dmamask = DMA_BIT_MASK(32); ++ ++static struct clk *usb_host_clock; ++ ++static int bcm63xx_ohci_power_on(struct platform_device *pdev) ++{ ++ usb_host_clock = clk_get(&pdev->dev, "usbh"); ++ if (IS_ERR_OR_NULL(usb_host_clock)) ++ return -ENODEV; ++ ++ clk_prepare_enable(usb_host_clock); ++ ++ bcm63xx_usb_priv_ohci_cfg_set(); ++ ++ return 0; ++} ++ ++static void bcm63xx_ohci_power_off(struct platform_device *pdev) ++{ ++ if (!IS_ERR_OR_NULL(usb_host_clock)) { ++ clk_disable_unprepare(usb_host_clock); ++ clk_put(usb_host_clock); ++ } ++} ++ ++static struct usb_ohci_pdata bcm63xx_ohci_pdata = { ++ .big_endian_desc = 1, ++ .big_endian_mmio = 1, ++ .no_big_frame_no = 1, ++ .num_ports = 1, ++ .power_on = bcm63xx_ohci_power_on, ++ .power_off = bcm63xx_ohci_power_off, ++ .power_suspend = bcm63xx_ohci_power_off, ++}; ++ ++static struct platform_device bcm63xx_ohci_device = { ++ .name = "ohci-platform", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(ohci_resources), ++ .resource = ohci_resources, ++ .dev = { ++ .platform_data = &bcm63xx_ohci_pdata, ++ .dma_mask = &ohci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++int __init bcm63xx_ohci_register(void) ++{ ++ if (BCMCPU_IS_6345() || BCMCPU_IS_6338()) ++ return -ENODEV; ++ ++ ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0); ++ ohci_resources[0].end = ohci_resources[0].start; ++ ohci_resources[0].end += RSET_OHCI_SIZE - 1; ++ ohci_resources[1].start = bcm63xx_get_irq_number(IRQ_OHCI0); ++ ++ return platform_device_register(&bcm63xx_ohci_device); ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h +@@ -0,0 +1,6 @@ ++#ifndef BCM63XX_DEV_USB_OHCI_H_ ++#define BCM63XX_DEV_USB_OHCI_H_ ++ ++int bcm63xx_ohci_register(void); ++ ++#endif /* BCM63XX_DEV_USB_OHCI_H_ */ diff --git a/target/linux/brcm63xx/patches-3.18/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch b/target/linux/brcm63xx/patches-3.18/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch new file mode 100644 index 0000000..2c26482 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch @@ -0,0 +1,36 @@ +From 33ef960aed15f9a98a2c51d8d794cd72418e0be4 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:25 +0100 +Subject: [PATCH 07/11] MIPS: BCM63XX: register OHCI controller if board + enables it + +BCM63XX-based boards can control the registration of the OHCI controller +by setting their has_ohci0 flag to 1. Handle this in the generic +code dealing with board registration and call the actual helper to +register the OHCI controller. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -898,6 +899,9 @@ int __init board_register_devices(void) + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + ++ if (board.has_ohci0) ++ bcm63xx_ohci_register(); ++ + if (board.has_dsp) + bcm63xx_dsp_register(&board.dsp); + diff --git a/target/linux/brcm63xx/patches-3.18/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch b/target/linux/brcm63xx/patches-3.18/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch new file mode 100644 index 0000000..bce91e3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch @@ -0,0 +1,62 @@ +From 00da1683364e58c6430a4577123d01037f8faddc Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:26 +0100 +Subject: [PATCH 08/11] MIPS: BCM63XX: introduce BCM63XX_EHCI configuration + symbol + +This configuration symbol can be used by CPUs supporting the on-chip +EHCI controller, and ensures that all relevant EHCI-related +configuration options are selected. So far BCM6328, BCM6358 and BCM6368 +have an EHCI controller and do select this symbol. Update +drivers/usb/host/Kconfig with BCM63XX to update direct unmet +dependencies. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Kconfig | 9 +++++++++ + drivers/usb/host/Kconfig | 5 +++-- + 2 files changed, 12 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -12,11 +12,18 @@ config BCM63XX_OHCI + select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD + select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD + ++config BCM63XX_EHCI ++ bool ++ select USB_ARCH_HAS_EHCI ++ select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD ++ select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6338 + bool "support 6338 CPU" +@@ -38,18 +45,21 @@ config BCM63XX_CPU_6358 + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6362 + bool "support 6362 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6368 + bool "support 6368 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" diff --git a/target/linux/brcm63xx/patches-3.18/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch b/target/linux/brcm63xx/patches-3.18/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch new file mode 100644 index 0000000..8b1f8d2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch @@ -0,0 +1,137 @@ +From e38f13bd6408769c0b565bb1079024f496eee121 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:27 +0100 +Subject: [PATCH 09/11] MIPS: BCM63XX: add support for the on-chip EHCI + controller + +Broadcom BCM63XX SoCs include an on-chip EHCI controller which can be +driven by the generic ehci-platform driver by using specific power +on/off/suspend callbacks to manage clocks and hardware specific +configuration. + +Signed-off-by: Maxime Bizon +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/dev-usb-ehci.c | 92 ++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h | 6 ++ + 3 files changed, 99 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/dev-usb-ehci.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,8 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o ++ dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ ++ usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -0,0 +1,92 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2013 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static struct resource ehci_resources[] = { ++ { ++ .start = -1, /* filled at runtime */ ++ .end = -1, /* filled at runtime */ ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = -1, /* filled at runtime */ ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ehci_dmamask = DMA_BIT_MASK(32); ++ ++static struct clk *usb_host_clock; ++ ++static int bcm63xx_ehci_power_on(struct platform_device *pdev) ++{ ++ usb_host_clock = clk_get(&pdev->dev, "usbh"); ++ if (IS_ERR_OR_NULL(usb_host_clock)) ++ return -ENODEV; ++ ++ clk_prepare_enable(usb_host_clock); ++ ++ bcm63xx_usb_priv_ehci_cfg_set(); ++ ++ return 0; ++} ++ ++static void bcm63xx_ehci_power_off(struct platform_device *pdev) ++{ ++ if (!IS_ERR_OR_NULL(usb_host_clock)) { ++ clk_disable_unprepare(usb_host_clock); ++ clk_put(usb_host_clock); ++ } ++} ++ ++static struct usb_ehci_pdata bcm63xx_ehci_pdata = { ++ .big_endian_desc = 1, ++ .big_endian_mmio = 1, ++ .power_on = bcm63xx_ehci_power_on, ++ .power_off = bcm63xx_ehci_power_off, ++ .power_suspend = bcm63xx_ehci_power_off, ++}; ++ ++static struct platform_device bcm63xx_ehci_device = { ++ .name = "ehci-platform", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(ehci_resources), ++ .resource = ehci_resources, ++ .dev = { ++ .platform_data = &bcm63xx_ehci_pdata, ++ .dma_mask = &ehci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++int __init bcm63xx_ehci_register(void) ++{ ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ return 0; ++ ++ ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); ++ ehci_resources[0].end = ehci_resources[0].start; ++ ehci_resources[0].end += RSET_EHCI_SIZE - 1; ++ ehci_resources[1].start = bcm63xx_get_irq_number(IRQ_EHCI0); ++ ++ return platform_device_register(&bcm63xx_ehci_device); ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h +@@ -0,0 +1,6 @@ ++#ifndef BCM63XX_DEV_USB_EHCI_H_ ++#define BCM63XX_DEV_USB_EHCI_H_ ++ ++int bcm63xx_ehci_register(void); ++ ++#endif /* BCM63XX_DEV_USB_EHCI_H_ */ diff --git a/target/linux/brcm63xx/patches-3.18/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch b/target/linux/brcm63xx/patches-3.18/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch new file mode 100644 index 0000000..641a57c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch @@ -0,0 +1,36 @@ +From 709ef2034f5ba06da35f89856ad7baf2b7a41287 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:28 +0100 +Subject: [PATCH 10/11] MIPS: BCM63XX: register EHCI controller if board + enables it + +BCM63XX-based board can control the registration of the EHCI controller +by setting their has_ehci0 flag to 1. Handle this in the generic +code dealing with board registration and call the actual helper to register +the EHCI controller. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -899,6 +900,9 @@ int __init board_register_devices(void) + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + ++ if (board.has_ehci0) ++ bcm63xx_ehci_register(); ++ + if (board.has_ohci0) + bcm63xx_ohci_register(); + diff --git a/target/linux/brcm63xx/patches-3.18/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch b/target/linux/brcm63xx/patches-3.18/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch new file mode 100644 index 0000000..6d91129 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch @@ -0,0 +1,24 @@ +From 111bbd770441ab34f9da5bb1d85767a9b75227b4 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:30 +0100 +Subject: [PATCH 12/12] MIPS: BCM63XX: EHCI controller does not support + overcurrent + +This patch sets the ignore_oc flag for the BCM63XX EHCI controller as it +does not support proper overcurrent reporting. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/dev-usb-ehci.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -61,6 +61,7 @@ static void bcm63xx_ehci_power_off(struc + static struct usb_ehci_pdata bcm63xx_ehci_pdata = { + .big_endian_desc = 1, + .big_endian_mmio = 1, ++ .ignore_oc = 1, + .power_on = bcm63xx_ehci_power_on, + .power_off = bcm63xx_ehci_power_off, + .power_suspend = bcm63xx_ehci_power_off, diff --git a/target/linux/brcm63xx/patches-3.18/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch b/target/linux/brcm63xx/patches-3.18/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch new file mode 100644 index 0000000..00dc9c9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch @@ -0,0 +1,38 @@ +From 3f650fc30aa0badf9d02842ce396cea3eef2eeaa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 1 Jul 2011 23:16:47 +0200 +Subject: [PATCH 49/79] SPI: Allow specifying the parsers for SPI flash + +Signed-off-by: Jonas Gorski +--- + include/linux/spi/flash.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -2,7 +2,7 @@ + #define LINUX_SPI_FLASH_H + + struct mtd_partition; +- ++struct mtd_part_parser_data; + /** + * struct flash_platform_data: board-specific flash data + * @name: optional flash device name (eg, as used with mtdparts=) +@@ -10,6 +10,8 @@ struct mtd_partition; + * @nr_parts: number of mtd_partitions for static partitoning + * @type: optional flash device type (e.g. m25p80 vs m25p64), for use + * with chips that can't be queried for JEDEC or other IDs ++ * @part_probe_types: optional list of MTD parser names to use for ++ * partitioning + * + * Board init code (in arch/.../mach-xxx/board-yyy.c files) can + * provide information about SPI flash parts (such as DataFlash) to +@@ -25,6 +27,7 @@ struct flash_platform_data { + + char *type; + ++ const char **part_probe_types; + /* we'll likely add more ... use JEDEC IDs, etc */ + }; + diff --git a/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch b/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch new file mode 100644 index 0000000..b949694 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch @@ -0,0 +1,23 @@ +From c7c3c338cb25d7f55ddb3f6bfbf3572758ca3896 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 10 Nov 2011 16:53:08 +0100 +Subject: [PATCH 50/79] MTD: DEVICES: m25p80: use parsers if provided in flash + platform data + +Signed-off-by: Jonas Gorski +--- + drivers/mtd/devices/m25p80.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -246,7 +246,8 @@ static int m25p_probe(struct spi_device + + ppdata.of_node = spi->dev.of_node; + +- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, ++ return mtd_device_parse_register(&flash->mtd, ++ data ? data->part_probe_types : NULL, &ppdata, + data ? data->parts : NULL, + data ? data->nr_parts : 0); + } diff --git a/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch b/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch new file mode 100644 index 0000000..740fb2d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch @@ -0,0 +1,90 @@ +From 5fb4e8d7287ac8fcb33aae8b1e9e22c5a3c392bd Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 10 Nov 2011 17:33:40 +0100 +Subject: [PATCH 51/79] MTD: DEVICES: m25p80: add support for limiting reads + +Signed-off-by: Jonas Gorski +--- + drivers/mtd/devices/m25p80.c | 29 +++++++++++++++++++++++++++-- + include/linux/spi/flash.h | 4 ++++ + 2 files changed, 31 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -32,6 +32,7 @@ struct m25p { + struct spi_device *spi; + struct spi_nor spi_nor; + struct mtd_info mtd; ++ int max_transfer_len; + u8 command[MAX_CMD_SIZE]; + }; + +@@ -121,7 +122,7 @@ static inline unsigned int m25p80_rx_nbi + * Read an address range from the nor chip. The address range + * may be any size provided it is within the physical boundaries. + */ +-static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, ++static int __m25p80_read(struct spi_nor *nor, loff_t from, size_t len, + size_t *retlen, u_char *buf) + { + struct m25p *flash = nor->priv; +@@ -157,6 +158,29 @@ static int m25p80_read(struct spi_nor *n + return 0; + } + ++static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct m25p *flash = nor->priv; ++ size_t off; ++ size_t read_len = flash->max_transfer_len; ++ size_t part_len; ++ int ret = 0; ++ ++ if (!read_len) ++ return __m25p80_read(nor, from, len, retlen, buf); ++ ++ *retlen = 0; ++ ++ for (off = 0; off < len && !ret; off += read_len) { ++ ret = __m25p80_read(nor, from + off, min(len - off, read_len), ++ &part_len, buf + off); ++ *retlen += part_len; ++ } ++ ++ return ret; ++} ++ + static int m25p80_erase(struct spi_nor *nor, loff_t offset) + { + struct m25p *flash = nor->priv; +@@ -240,6 +264,9 @@ static int m25p_probe(struct spi_device + else + flash_name = spi->modalias; + ++ if (data) ++ flash->max_transfer_len = data->max_transfer_len; ++ + ret = spi_nor_scan(nor, flash_name, mode); + if (ret) + return ret; +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -13,6 +13,8 @@ struct mtd_part_parser_data; + * @part_probe_types: optional list of MTD parser names to use for + * partitioning + * ++ * @max_transfer_len: option maximum read/write length limitation for ++ * SPI controllers not able to transfer any length commands. + * Board init code (in arch/.../mach-xxx/board-yyy.c files) can + * provide information about SPI flash parts (such as DataFlash) to + * help set up the device and its appropriate default partitioning. +@@ -28,6 +30,8 @@ struct flash_platform_data { + char *type; + + const char **part_probe_types; ++ ++ unsigned int max_transfer_len; + /* we'll likely add more ... use JEDEC IDs, etc */ + }; + diff --git a/target/linux/brcm63xx/patches-3.18/204-USB-OHCI-allow-other-arches-to-use-the-BE-frame-numb.patch b/target/linux/brcm63xx/patches-3.18/204-USB-OHCI-allow-other-arches-to-use-the-BE-frame-numb.patch new file mode 100644 index 0000000..4b3d44a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/204-USB-OHCI-allow-other-arches-to-use-the-BE-frame-numb.patch @@ -0,0 +1,31 @@ +From b2f399dcd674a692a64bb3b300b77b78ae57b530 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 12 Jan 2014 16:47:35 +0100 +Subject: [PATCH] USB: OHCI: allow other arches to use the BE frame number + quirk + +Intead of guarding it with a certain PPC SoC and expanding the list +for each SoC requiring it, just guard it with USB_OHCI_BIG_ENDIAN_DESC. + +This makes it less suprising that passing no_big_frame_no = 1 for the +platform data does not do what expected (or + +Checking it for all big endian descriptor setups should not impact +performance much as USB1.1 is rather slow anyway. + +Signed-off-by: Jonas Gorski +--- + drivers/usb/host/ohci.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/usb/host/ohci.h ++++ b/drivers/usb/host/ohci.h +@@ -652,7 +652,7 @@ static inline u32 hc32_to_cpup (const st + * some big-endian SOC implementations. Same thing happens with PSW access. + */ + +-#ifdef CONFIG_PPC_MPC52xx ++#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_DESC + #define big_endian_frame_no_quirk(ohci) (ohci->flags & OHCI_QUIRK_FRAME_NO) + #else + #define big_endian_frame_no_quirk(ohci) 0 diff --git a/target/linux/brcm63xx/patches-3.18/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch b/target/linux/brcm63xx/patches-3.18/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch new file mode 100644 index 0000000..404bea9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch @@ -0,0 +1,66 @@ +From 6ac09efa8f0e189ffe7dd7b0889289de56ee44cc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 19 Jan 2014 12:18:03 +0100 +Subject: [PATCH] USB: EHCI: allow limiting ports for ehci-platform + +In the same way as the ohci platform driver allows limiting ports, +enable the same for ehci. This prevents a mismatch in the available +ports between ehci/ohci on USB 2.0 controllers. + +This is needed if the USB host controller always reports the maximum +number of ports regardless of the number of available ports (because +one might be set to be usb device). + +Signed-off-by: Jonas Gorski +--- + drivers/usb/host/ehci-hcd.c | 4 ++++ + drivers/usb/host/ehci-platform.c | 2 ++ + drivers/usb/host/ehci.h | 1 + + include/linux/usb/ehci_pdriver.h | 1 + + 4 files changed, 8 insertions(+) + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -660,6 +660,10 @@ int ehci_setup(struct usb_hcd *hcd) + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ++ if (ehci->num_ports) { ++ ehci->hcs_params &= ~0xf; /* bits 3:0, ports on HC */ ++ ehci->hcs_params |= ehci->num_ports; ++ } + + ehci->sbrn = HCD_USB2; + +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -58,6 +58,9 @@ static int ehci_platform_reset(struct us + hcd->has_tt = pdata->has_tt; + ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug; + ++ if (pdata->num_ports && pdata->num_ports <= 15) ++ ehci->num_ports = pdata->num_ports; ++ + if (pdata->pre_setup) { + retval = pdata->pre_setup(hcd); + if (retval < 0) +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -213,6 +213,7 @@ struct ehci_hcd { /* one per controlle + u32 command; + + /* SILICON QUIRKS */ ++ unsigned int num_ports; + unsigned no_selective_suspend:1; + unsigned has_fsl_port_bug:1; /* FreeScale */ + unsigned big_endian_mmio:1; +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -40,6 +40,7 @@ struct usb_hcd; + */ + struct usb_ehci_pdata { + int caps_offset; ++ unsigned int num_ports; + unsigned has_tt:1; + unsigned has_synopsys_hc_bug:1; + unsigned big_endian_desc:1; diff --git a/target/linux/brcm63xx/patches-3.18/207-MIPS-BCM63XX-move-device-registration-code-into-its-.patch b/target/linux/brcm63xx/patches-3.18/207-MIPS-BCM63XX-move-device-registration-code-into-its-.patch new file mode 100644 index 0000000..4e5e611 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/207-MIPS-BCM63XX-move-device-registration-code-into-its-.patch @@ -0,0 +1,493 @@ +From 5a50cb0d53344a2429831b00925d6183d4d332e1 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Mar 2014 03:54:05 +0100 +Subject: [PATCH 40/44] MIPS: BCM63XX: move device registration code into its + own file + +Move device registration code into its own file to allow sharing it +between board implementations. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/Makefile | 1 + + arch/mips/bcm63xx/boards/board_bcm963xx.c | 188 +------------------------- + arch/mips/bcm63xx/boards/board_common.c | 215 ++++++++++++++++++++++++++++++ + arch/mips/bcm63xx/boards/board_common.h | 8 ++ + 4 files changed, 223 insertions(+), 183 deletions(-) + create mode 100644 arch/mips/bcm63xx/boards/board_common.c + create mode 100644 arch/mips/bcm63xx/boards/board_common.h + +--- a/arch/mips/bcm63xx/boards/Makefile ++++ b/arch/mips/bcm63xx/boards/Makefile +@@ -1 +1,2 @@ ++obj-y += board_common.o + obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -10,35 +10,22 @@ + #include + #include + #include +-#include +-#include + #include + #include + #include +-#include + #include + #include + #include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include + #include + ++#include "board_common.h" ++ + #include + + #define PFX "board_bcm963xx: " + + #define HCS_OFFSET_128K 0x20000 + +-static struct board_info board; +- + /* + * known 3368 boards + */ +@@ -711,52 +698,6 @@ static const struct board_info __initcon + }; + + /* +- * Register a sane SPROMv2 to make the on-board +- * bcm4318 WLAN work +- */ +-#ifdef CONFIG_SSB_PCIHOST +-static struct ssb_sprom bcm63xx_sprom = { +- .revision = 0x02, +- .board_rev = 0x17, +- .country_code = 0x0, +- .ant_available_bg = 0x3, +- .pa0b0 = 0x15ae, +- .pa0b1 = 0xfa85, +- .pa0b2 = 0xfe8d, +- .pa1b0 = 0xffff, +- .pa1b1 = 0xffff, +- .pa1b2 = 0xffff, +- .gpio0 = 0xff, +- .gpio1 = 0xff, +- .gpio2 = 0xff, +- .gpio3 = 0xff, +- .maxpwr_bg = 0x004c, +- .itssi_bg = 0x00, +- .boardflags_lo = 0x2848, +- .boardflags_hi = 0x0000, +-}; +- +-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +-{ +- if (bus->bustype == SSB_BUSTYPE_PCI) { +- memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); +- return 0; +- } else { +- printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); +- return -EINVAL; +- } +-} +-#endif +- +-/* +- * return board name for /proc/cpuinfo +- */ +-const char *board_get_name(void) +-{ +- return board.name; +-} +- +-/* + * early init callback, read nvram data from flash and checksum it + */ + void __init board_prom_init(void) +@@ -801,141 +742,16 @@ void __init board_prom_init(void) + if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) + continue; + /* copy, board desc array is marked initdata */ +- memcpy(&board, bcm963xx_boards[i], sizeof(board)); ++ board_early_setup(bcm963xx_boards[i]); + break; + } + +- /* bail out if board is not found, will complain later */ +- if (!board.name[0]) { ++ /* warn if board is not found, will complain later */ ++ if (i == ARRAY_SIZE(bcm963xx_boards)) { + char name[17]; + memcpy(name, board_name, 16); + name[16] = 0; + printk(KERN_ERR PFX "unknown bcm963xx board: %s\n", + name); +- return; +- } +- +- /* setup pin multiplexing depending on board enabled device, +- * this has to be done this early since PCI init is done +- * inside arch_initcall */ +- val = 0; +- +-#ifdef CONFIG_PCI +- if (board.has_pci) { +- bcm63xx_pci_enabled = 1; +- if (BCMCPU_IS_6348()) +- val |= GPIO_MODE_6348_G2_PCI; +- } +-#endif +- +- if (board.has_pccard) { +- if (BCMCPU_IS_6348()) +- val |= GPIO_MODE_6348_G1_MII_PCCARD; +- } +- +- if (board.has_enet0 && !board.enet0.use_internal_phy) { +- if (BCMCPU_IS_6348()) +- val |= GPIO_MODE_6348_G3_EXT_MII | +- GPIO_MODE_6348_G0_EXT_MII; +- } +- +- if (board.has_enet1 && !board.enet1.use_internal_phy) { +- if (BCMCPU_IS_6348()) +- val |= GPIO_MODE_6348_G3_EXT_MII | +- GPIO_MODE_6348_G0_EXT_MII; +- } +- +- bcm_gpio_writel(val, GPIO_MODE_REG); +-} +- +-/* +- * second stage init callback, good time to panic if we couldn't +- * identify on which board we're running since early printk is working +- */ +-void __init board_setup(void) +-{ +- if (!board.name[0]) +- panic("unable to detect bcm963xx board"); +- printk(KERN_INFO PFX "board name: %s\n", board.name); +- +- /* make sure we're running on expected cpu */ +- if (bcm63xx_get_cpu_id() != board.expected_cpu_id) +- panic("unexpected CPU for bcm963xx board"); +-} +- +-static struct gpio_led_platform_data bcm63xx_led_data; +- +-static struct platform_device bcm63xx_gpio_leds = { +- .name = "leds-gpio", +- .id = 0, +- .dev.platform_data = &bcm63xx_led_data, +-}; +- +-/* +- * third stage init callback, register all board devices. +- */ +-int __init board_register_devices(void) +-{ +- if (board.has_uart0) +- bcm63xx_uart_register(0); +- +- if (board.has_uart1) +- bcm63xx_uart_register(1); +- +- if (board.has_pccard) +- bcm63xx_pcmcia_register(); +- +- if (board.has_enet0 && +- !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr)) +- bcm63xx_enet_register(0, &board.enet0); +- +- if (board.has_enet1 && +- !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr)) +- bcm63xx_enet_register(1, &board.enet1); +- +- if (board.has_enetsw && +- !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr)) +- bcm63xx_enetsw_register(&board.enetsw); +- +- if (board.has_usbd) +- bcm63xx_usbd_register(&board.usbd); +- +- if (board.has_ehci0) +- bcm63xx_ehci_register(); +- +- if (board.has_ohci0) +- bcm63xx_ohci_register(); +- +- if (board.has_dsp) +- bcm63xx_dsp_register(&board.dsp); +- +- /* Generate MAC address for WLAN and register our SPROM, +- * do this after registering enet devices +- */ +-#ifdef CONFIG_SSB_PCIHOST +- if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) { +- memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); +- memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); +- if (ssb_arch_register_fallback_sprom( +- &bcm63xx_get_fallback_sprom) < 0) +- pr_err(PFX "failed to register fallback SPROM\n"); + } +-#endif +- +- bcm63xx_spi_register(); +- +- bcm63xx_hsspi_register(); +- +- bcm63xx_flash_register(); +- +- bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); +- bcm63xx_led_data.leds = board.leds; +- +- platform_device_register(&bcm63xx_gpio_leds); +- +- if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) +- gpio_request_one(board.ephy_reset_gpio, +- board.ephy_reset_gpio_flags, "ephy-reset"); +- +- return 0; + } +--- /dev/null ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -0,0 +1,217 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2008 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFX "board: " ++ ++static struct board_info board; ++ ++/* ++ * Register a sane SPROMv2 to make the on-board ++ * bcm4318 WLAN work ++ */ ++#ifdef CONFIG_SSB_PCIHOST ++static struct ssb_sprom bcm63xx_sprom = { ++ .revision = 0x02, ++ .board_rev = 0x17, ++ .country_code = 0x0, ++ .ant_available_bg = 0x3, ++ .pa0b0 = 0x15ae, ++ .pa0b1 = 0xfa85, ++ .pa0b2 = 0xfe8d, ++ .pa1b0 = 0xffff, ++ .pa1b1 = 0xffff, ++ .pa1b2 = 0xffff, ++ .gpio0 = 0xff, ++ .gpio1 = 0xff, ++ .gpio2 = 0xff, ++ .gpio3 = 0xff, ++ .maxpwr_bg = 0x004c, ++ .itssi_bg = 0x00, ++ .boardflags_lo = 0x2848, ++ .boardflags_hi = 0x0000, ++}; ++ ++int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) ++{ ++ if (bus->bustype == SSB_BUSTYPE_PCI) { ++ memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ return 0; ++ } else { ++ printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); ++ return -EINVAL; ++ } ++} ++#endif ++ ++/* ++ * return board name for /proc/cpuinfo ++ */ ++const char *board_get_name(void) ++{ ++ return board.name; ++} ++ ++/* ++ * setup board for device registration ++ */ ++void __init board_early_setup(const struct board_info *target) ++{ ++ u32 val; ++ ++ memcpy(&board, target, sizeof(board)); ++ ++ /* setup pin multiplexing depending on board enabled device, ++ * this has to be done this early since PCI init is done ++ * inside arch_initcall */ ++ val = 0; ++ ++#ifdef CONFIG_PCI ++ if (board.has_pci) { ++ bcm63xx_pci_enabled = 1; ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G2_PCI; ++ } ++#endif ++ ++ if (board.has_pccard) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G1_MII_PCCARD; ++ } ++ ++ if (board.has_enet0 && !board.enet0.use_internal_phy) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G3_EXT_MII | ++ GPIO_MODE_6348_G0_EXT_MII; ++ } ++ ++ if (board.has_enet1 && !board.enet1.use_internal_phy) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G3_EXT_MII | ++ GPIO_MODE_6348_G0_EXT_MII; ++ } ++ ++ bcm_gpio_writel(val, GPIO_MODE_REG); ++} ++ ++ ++/* ++ * second stage init callback, good time to panic if we couldn't ++ * identify on which board we're running since early printk is working ++ */ ++void __init board_setup(void) ++{ ++ if (!board.name[0]) ++ panic("unable to detect bcm963xx board"); ++ printk(KERN_INFO PFX "board name: %s\n", board.name); ++ ++ /* make sure we're running on expected cpu */ ++ if (bcm63xx_get_cpu_id() != board.expected_cpu_id) ++ panic("unexpected CPU for bcm963xx board"); ++} ++ ++static struct gpio_led_platform_data bcm63xx_led_data; ++ ++static struct platform_device bcm63xx_gpio_leds = { ++ .name = "leds-gpio", ++ .id = 0, ++ .dev.platform_data = &bcm63xx_led_data, ++}; ++ ++/* ++ * third stage init callback, register all board devices. ++ */ ++int __init board_register_devices(void) ++{ ++ if (board.has_uart0) ++ bcm63xx_uart_register(0); ++ ++ if (board.has_uart1) ++ bcm63xx_uart_register(1); ++ ++ if (board.has_pccard) ++ bcm63xx_pcmcia_register(); ++ ++ if (board.has_enet0 && ++ !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr)) ++ bcm63xx_enet_register(0, &board.enet0); ++ ++ if (board.has_enet1 && ++ !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr)) ++ bcm63xx_enet_register(1, &board.enet1); ++ ++ if (board.has_enetsw && ++ !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr)) ++ bcm63xx_enetsw_register(&board.enetsw); ++ ++ if (board.has_usbd) ++ bcm63xx_usbd_register(&board.usbd); ++ ++ if (board.has_ehci0) ++ bcm63xx_ehci_register(); ++ ++ if (board.has_ohci0) ++ bcm63xx_ohci_register(); ++ ++ if (board.has_dsp) ++ bcm63xx_dsp_register(&board.dsp); ++ ++ /* Generate MAC address for WLAN and register our SPROM, ++ * do this after registering enet devices ++ */ ++#ifdef CONFIG_SSB_PCIHOST ++ if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) { ++ memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); ++ if (ssb_arch_register_fallback_sprom( ++ &bcm63xx_get_fallback_sprom) < 0) ++ pr_err(PFX "failed to register fallback SPROM\n"); ++ } ++#endif ++ ++ bcm63xx_spi_register(); ++ ++ bcm63xx_hsspi_register(); ++ ++ bcm63xx_flash_register(); ++ ++ bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); ++ bcm63xx_led_data.leds = board.leds; ++ ++ platform_device_register(&bcm63xx_gpio_leds); ++ ++ if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) ++ gpio_request_one(board.ephy_reset_gpio, ++ board.ephy_reset_gpio_flags, "ephy-reset"); ++ ++ return 0; ++} +--- /dev/null ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -0,0 +1,8 @@ ++#ifndef __BOARD_COMMON_H ++#define __BOARD_COMMON_H ++ ++#include ++ ++void board_early_setup(const struct board_info *board); ++ ++#endif /* __BOARD_COMMON_H */ diff --git a/target/linux/brcm63xx/patches-3.18/208-MIPS-BCM63XX-pass-a-mac-addresss-allocator-to-board-.patch b/target/linux/brcm63xx/patches-3.18/208-MIPS-BCM63XX-pass-a-mac-addresss-allocator-to-board-.patch new file mode 100644 index 0000000..877030f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/208-MIPS-BCM63XX-pass-a-mac-addresss-allocator-to-board-.patch @@ -0,0 +1,100 @@ +From 4e9c34a37bd3442b286ba55441bfe22c1ac5b65f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Mar 2014 04:08:06 +0100 +Subject: [PATCH 41/44] MIPS: BCM63XX: pass a mac addresss allocator to board + setup + +Pass a mac address allocator to board setup code to allow board +implementations to work with third party bootloaders not using nvram +for configuration storage. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 3 ++- + arch/mips/bcm63xx/boards/board_common.c | 16 ++++++++++------ + arch/mips/bcm63xx/boards/board_common.h | 3 ++- + 3 files changed, 14 insertions(+), 8 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -742,7 +742,8 @@ void __init board_prom_init(void) + if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) + continue; + /* copy, board desc array is marked initdata */ +- board_early_setup(bcm963xx_boards[i]); ++ board_early_setup(bcm963xx_boards[i], ++ bcm63xx_nvram_get_mac_address); + break; + } + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -18,7 +18,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -81,15 +80,20 @@ const char *board_get_name(void) + return board.name; + } + ++static int (*board_get_mac_address)(u8 mac[ETH_ALEN]); ++ + /* + * setup board for device registration + */ +-void __init board_early_setup(const struct board_info *target) ++void __init board_early_setup(const struct board_info *target, ++ int (*get_mac_address)(u8 mac[ETH_ALEN])) + { + u32 val; + + memcpy(&board, target, sizeof(board)); + ++ board_get_mac_address = get_mac_address; ++ + /* setup pin multiplexing depending on board enabled device, + * this has to be done this early since PCI init is done + * inside arch_initcall */ +@@ -162,15 +166,15 @@ int __init board_register_devices(void) + bcm63xx_pcmcia_register(); + + if (board.has_enet0 && +- !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr)) ++ !board_get_mac_address(board.enet0.mac_addr)) + bcm63xx_enet_register(0, &board.enet0); + + if (board.has_enet1 && +- !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr)) ++ !board_get_mac_address(board.enet1.mac_addr)) + bcm63xx_enet_register(1, &board.enet1); + + if (board.has_enetsw && +- !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr)) ++ !board_get_mac_address(board.enetsw.mac_addr)) + bcm63xx_enetsw_register(&board.enetsw); + + if (board.has_usbd) +@@ -189,7 +193,7 @@ int __init board_register_devices(void) + * do this after registering enet devices + */ + #ifdef CONFIG_SSB_PCIHOST +- if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) { ++ if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { + memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); + if (ssb_arch_register_fallback_sprom( +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -3,6 +3,7 @@ + + #include + +-void board_early_setup(const struct board_info *board); ++void board_early_setup(const struct board_info *board, ++ int (*get_mac_address)(u8 mac[ETH_ALEN])); + + #endif /* __BOARD_COMMON_H */ diff --git a/target/linux/brcm63xx/patches-3.18/300-reset_buttons.patch b/target/linux/brcm63xx/patches-3.18/300-reset_buttons.patch new file mode 100644 index 0000000..2263b49 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/300-reset_buttons.patch @@ -0,0 +1,101 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -10,6 +10,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -26,6 +28,9 @@ + + #define HCS_OFFSET_128K 0x20000 + ++#define BCM963XX_KEYS_POLL_INTERVAL 20 ++#define BCM963XX_KEYS_DEBOUNCE_INTERVAL (BCM963XX_KEYS_POLL_INTERVAL * 3) ++ + /* + * known 3368 boards + */ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -32,6 +33,8 @@ + + #define PFX "board: " + ++#define BCM963XX_KEYS_POLL_INTERVAL 20 ++ + static struct board_info board; + + /* +@@ -151,11 +154,23 @@ static struct platform_device bcm63xx_gp + .dev.platform_data = &bcm63xx_led_data, + }; + ++static struct gpio_keys_platform_data bcm63xx_gpio_keys_data = { ++ .poll_interval = BCM963XX_KEYS_POLL_INTERVAL, ++}; ++ ++static struct platform_device bcm63xx_gpio_keys_device = { ++ .name = "gpio-keys-polled", ++ .id = 0, ++ .dev.platform_data = &bcm63xx_gpio_keys_data, ++}; ++ + /* + * third stage init callback, register all board devices. + */ + int __init board_register_devices(void) + { ++ int button_count = 0; ++ + if (board.has_uart0) + bcm63xx_uart_register(0); + +@@ -217,5 +232,16 @@ int __init board_register_devices(void) + gpio_request_one(board.ephy_reset_gpio, + board.ephy_reset_gpio_flags, "ephy-reset"); + ++ /* count number of BUTTONs defined by this device */ ++ while (button_count < ARRAY_SIZE(board.buttons) && board.buttons[button_count].desc) ++ button_count++; ++ ++ if (button_count) { ++ bcm63xx_gpio_keys_data.nbuttons = button_count; ++ bcm63xx_gpio_keys_data.buttons = board.buttons; ++ ++ platform_device_register(&bcm63xx_gpio_keys_device); ++ } ++ + return 0; + } +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -3,6 +3,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -48,6 +49,9 @@ struct board_info { + /* GPIO LEDs */ + struct gpio_led leds[5]; + ++ /* Buttons */ ++ struct gpio_keys_button buttons[4]; ++ + /* External PHY reset GPIO */ + unsigned int ephy_reset_gpio; + diff --git a/target/linux/brcm63xx/patches-3.18/301-led_count.patch b/target/linux/brcm63xx/patches-3.18/301-led_count.patch new file mode 100644 index 0000000..49a1825 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/301-led_count.patch @@ -0,0 +1,41 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -170,6 +170,7 @@ static struct platform_device bcm63xx_gp + int __init board_register_devices(void) + { + int button_count = 0; ++ int led_count = 0; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -223,10 +224,16 @@ int __init board_register_devices(void) + + bcm63xx_flash_register(); + +- bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); +- bcm63xx_led_data.leds = board.leds; ++ /* count number of LEDs defined by this device */ ++ while (led_count < ARRAY_SIZE(board.leds) && board.leds[led_count].name) ++ led_count++; ++ ++ if (led_count) { ++ bcm63xx_led_data.num_leds = led_count; ++ bcm63xx_led_data.leds = board.leds; + +- platform_device_register(&bcm63xx_gpio_leds); ++ platform_device_register(&bcm63xx_gpio_leds); ++ } + + if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) + gpio_request_one(board.ephy_reset_gpio, +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -47,7 +47,7 @@ struct board_info { + struct bcm63xx_dsp_platform_data dsp; + + /* GPIO LEDs */ +- struct gpio_led leds[5]; ++ struct gpio_led leds[14]; + + /* Buttons */ + struct gpio_keys_button buttons[4]; diff --git a/target/linux/brcm63xx/patches-3.18/302-extended-platform-devices.patch b/target/linux/brcm63xx/patches-3.18/302-extended-platform-devices.patch new file mode 100644 index 0000000..cc61cee --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/302-extended-platform-devices.patch @@ -0,0 +1,25 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -222,6 +222,9 @@ int __init board_register_devices(void) + + bcm63xx_hsspi_register(); + ++ if (board.num_devs) ++ platform_add_devices(board.devs, board.num_devs); ++ + bcm63xx_flash_register(); + + /* count number of LEDs defined by this device */ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -57,6 +57,10 @@ struct board_info { + + /* External PHY reset GPIO flags from gpio.h */ + unsigned long ephy_reset_gpio_flags; ++ ++ /* Additional platform devices */ ++ struct platform_device **devs; ++ unsigned int num_devs; + }; + + #endif /* ! BOARD_BCM963XX_H_ */ diff --git a/target/linux/brcm63xx/patches-3.18/303-spi-board-info.patch b/target/linux/brcm63xx/patches-3.18/303-spi-board-info.patch new file mode 100644 index 0000000..878e626 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/303-spi-board-info.patch @@ -0,0 +1,33 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -225,6 +226,9 @@ int __init board_register_devices(void) + if (board.num_devs) + platform_add_devices(board.devs, board.num_devs); + ++ if (board.num_spis) ++ spi_register_board_info(board.spis, board.num_spis); ++ + bcm63xx_flash_register(); + + /* count number of LEDs defined by this device */ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -61,6 +61,10 @@ struct board_info { + /* Additional platform devices */ + struct platform_device **devs; + unsigned int num_devs; ++ ++ /* Additional platform devices */ ++ struct spi_board_info *spis; ++ unsigned int num_spis; + }; + + #endif /* ! BOARD_BCM963XX_H_ */ diff --git a/target/linux/brcm63xx/patches-3.18/309-cfe_version_mod.patch b/target/linux/brcm63xx/patches-3.18/309-cfe_version_mod.patch new file mode 100644 index 0000000..42af6ae --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/309-cfe_version_mod.patch @@ -0,0 +1,27 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -727,10 +727,20 @@ void __init board_prom_init(void) + + /* dump cfe version */ + cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; +- if (!memcmp(cfe, "cfe-v", 5)) +- snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", +- cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); +- else ++ if (strstarts(cfe, "cfe-")) { ++ if(cfe[4] == 'v') { ++ if(cfe[5] == 'd') ++ snprintf(cfe_version, 11, "%s", (char *) &cfe[5]); ++ else if (cfe[10] > 0) ++ snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u-%u", ++ cfe[5], cfe[6], cfe[7], cfe[8], cfe[9], cfe[10]); ++ else ++ snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", ++ cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); ++ } else { ++ snprintf(cfe_version, 12, "%s", (char *) &cfe[4]); ++ } ++ } else + strcpy(cfe_version, "unknown"); + printk(KERN_INFO PFX "CFE version: %s\n", cfe_version); + diff --git a/target/linux/brcm63xx/patches-3.18/310-cfe_simplify_detection.patch b/target/linux/brcm63xx/patches-3.18/310-cfe_simplify_detection.patch new file mode 100644 index 0000000..e05c91d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/310-cfe_simplify_detection.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h +@@ -1,6 +1,8 @@ + #ifndef BCM63XX_BOARD_H_ + #define BCM63XX_BOARD_H_ + ++#include ++ + const char *board_get_name(void); + + void board_prom_init(void); +@@ -9,4 +11,8 @@ void board_setup(void); + + int board_register_devices(void); + ++static inline bool bcm63xx_is_cfe_present(void) { ++ return fw_arg3 == 0x43464531; ++} ++ + #endif /* ! BCM63XX_BOARD_H_ */ diff --git a/target/linux/brcm63xx/patches-3.18/311-bcm63xxpart_use_cfedetection.patch b/target/linux/brcm63xx/patches-3.18/311-bcm63xxpart_use_cfedetection.patch new file mode 100644 index 0000000..46d9b47 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/311-bcm63xxpart_use_cfedetection.patch @@ -0,0 +1,51 @@ +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -35,7 +35,7 @@ + + #include + #include +-#include ++#include + + #define BCM63XX_EXTENDED_SIZE 0xBFC00000 /* Extended flash address */ + +@@ -43,30 +43,6 @@ + + #define BCM63XX_CFE_MAGIC_OFFSET 0x4e0 + +-static int bcm63xx_detect_cfe(struct mtd_info *master) +-{ +- char buf[9]; +- int ret; +- size_t retlen; +- +- ret = mtd_read(master, BCM963XX_CFE_VERSION_OFFSET, 5, &retlen, +- (void *)buf); +- buf[retlen] = 0; +- +- if (ret) +- return ret; +- +- if (strncmp("cfe-v", buf, 5) == 0) +- return 0; +- +- /* very old CFE's do not have the cfe-v string, so check for magic */ +- ret = mtd_read(master, BCM63XX_CFE_MAGIC_OFFSET, 8, &retlen, +- (void *)buf); +- buf[retlen] = 0; +- +- return strncmp("CFE1CFE1", buf, 8); +-} +- + static int bcm63xx_parse_cfe_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -85,7 +61,7 @@ static int bcm63xx_parse_cfe_partitions( + u32 computed_crc; + bool rootfs_first = false; + +- if (bcm63xx_detect_cfe(master)) ++ if (!bcm63xx_is_cfe_present()) + return -EINVAL; + + cfe_erasesize = max_t(uint32_t, master->erasesize, diff --git a/target/linux/brcm63xx/patches-3.18/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch b/target/linux/brcm63xx/patches-3.18/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch new file mode 100644 index 0000000..11eedf9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch @@ -0,0 +1,455 @@ +From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Nov 2014 14:53:12 +0100 +Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq + controller + +Signed-off-by: Jonas Gorski +--- + .../brcm,bcm6345-periph-intc.txt | 50 +++ + drivers/irqchip/Kconfig | 4 + + drivers/irqchip/Makefile | 1 + + drivers/irqchip/irq-bcm6345-periph.c | 339 ++++++++++++++++++++ + include/linux/irqchip/irq-bcm6345-periph.h | 16 + + 5 files changed, 410 insertions(+) + create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt + create mode 100644 drivers/irqchip/irq-bcm6345-periph.c + create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt +@@ -0,0 +1,50 @@ ++Broadcom BCM6345 Level 1 periphery interrupt controller ++ ++This block is a interrupt controller that is typically connected directly ++to one of the HW INT lines on each CPU. Every BCM63XX xDSL chip since ++BCM6345 has contained this hardware. ++ ++Key elements of the hardware design include: ++ ++- 32, 64, or 128 incoming level IRQ lines ++ ++- All onchip peripherals are wired directly to an L2 input ++ ++- A separate instance of the register set for each CPU, allowing individual ++ peripheral IRQs to be routed to any CPU ++ ++- No atomic mask/unmask operations ++ ++- No polarity/level/edge settings ++ ++- No FIFO or priority encoder logic; software is expected to read all ++ 1-4 status words to determine which IRQs are pending ++ ++Required properties: ++ ++- compatible: Should be "brcm,bcm6345-periph-intc". ++- reg: Specifies the base physical address and size of the registers. ++ Multiple register addresses may be specified, and must match the amount of ++ parent interrupts. ++- interrupt-controller: Identifies the node as an interrupt controller. ++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt ++ source, should be 1. ++- interrupt-parent: Specifies the phandle to the parent interrupt controller ++ this one is cascaded from. ++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller ++ node, valid values depend on the type of parent interrupt controller. ++ Multiple lines are used to route interrupts to different cpus, with the first ++ assumed to be for the boot CPU. ++ ++Example: ++ ++periph_intc: interrupt-controller@f0406800 { ++ compatible = "brcm,bcm6345-periph-intc"; ++ reg = <0x10000020 0x10>, <0x10000030 0x10>; ++ ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ ++ interrupt-parent = <&cpu_intc>; ++ interrupts = <2>, <3>; ++}; +--- a/drivers/irqchip/Kconfig ++++ b/drivers/irqchip/Kconfig +@@ -54,6 +54,10 @@ config BRCMSTB_L2_IRQ + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + ++config BCM6345_PERIPH_IRQ ++ bool ++ select IRQ_DOMAIN ++ + config DW_APB_ICTL + bool + select IRQ_DOMAIN +--- a/drivers/irqchip/Makefile ++++ b/drivers/irqchip/Makefile +@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o + obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o + obj-$(CONFIG_ARCH_MXS) += irq-mxs.o + obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o ++obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o + obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o + obj-$(CONFIG_METAG) += irq-metag-ext.o + obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o +--- /dev/null ++++ b/drivers/irqchip/irq-bcm6345-periph.c +@@ -0,0 +1,339 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2014 Jonas Gorski ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_BCM63XX ++#include ++ ++#define VIRQ_BASE IRQ_INTERNAL_BASE ++#else ++#define VIRQ_BASE 0 ++#endif ++ ++#include "irqchip.h" ++ ++#define MAX_WORDS 4 ++#define MAX_PARENT_IRQS 2 ++#define IRQS_PER_WORD 32 ++ ++struct intc_block { ++ int parent_irq; ++ void __iomem *base; ++ void __iomem *en_reg[MAX_WORDS]; ++ void __iomem *status_reg[MAX_WORDS]; ++ u32 mask_cache[MAX_WORDS]; ++}; ++ ++struct intc_data { ++ struct irq_chip chip; ++ struct intc_block block[MAX_PARENT_IRQS]; ++ ++ int num_words; ++ ++ struct irq_domain *domain; ++ raw_spinlock_t lock; ++}; ++ ++static void bcm6345_periph_irq_handle(unsigned int irq, struct irq_desc *desc) ++{ ++ struct intc_data *data = irq_desc_get_handler_data(desc); ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct intc_block *block; ++ unsigned int idx; ++ ++ chained_irq_enter(chip, desc); ++ ++ for (idx = 0; idx < MAX_PARENT_IRQS; idx++) ++ if (irq == data->block[idx].parent_irq) ++ block = &data->block[idx]; ++ ++ for (idx = 0; idx < data->num_words; idx++) { ++ int base = idx * IRQS_PER_WORD; ++ unsigned long pending; ++ int hw_irq; ++ ++ raw_spin_lock(&data->lock); ++ pending = __raw_readl(block->en_reg[idx]) & ++ __raw_readl(block->status_reg[idx]); ++ raw_spin_unlock(&data->lock); ++ ++ for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) { ++ int virq; ++ ++ virq = irq_find_mapping(data->domain, base + hw_irq); ++ generic_handle_irq(virq); ++ } ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit, ++ bool enable) ++{ ++ u32 val; ++ ++ val = __raw_readl(block->en_reg[reg]); ++ if (enable) ++ val |= BIT(bit); ++ else ++ val &= ~BIT(bit); ++ __raw_writel(val, block->en_reg[reg]); ++} ++ ++static void bcm6345_periph_irq_mask(struct irq_data *data) ++{ ++ unsigned int i, reg, bit; ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ ++ reg = hwirq / IRQS_PER_WORD; ++ bit = hwirq % IRQS_PER_WORD; ++ ++ raw_spin_lock(&priv->lock); ++ for (i = 0; i < MAX_PARENT_IRQS; i++) { ++ struct intc_block *block = &priv->block[i]; ++ ++ if (!block->parent_irq) ++ break; ++ ++ __bcm6345_periph_enable(block, reg, bit, false); ++ } ++ raw_spin_unlock(&priv->lock); ++} ++ ++static void bcm6345_periph_irq_unmask(struct irq_data *data) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ unsigned int i, reg, bit; ++ ++ reg = hwirq / IRQS_PER_WORD; ++ bit = hwirq % IRQS_PER_WORD; ++ ++ raw_spin_lock(&priv->lock); ++ for (i = 0; i < MAX_PARENT_IRQS; i++) { ++ struct intc_block *block = &priv->block[i]; ++ ++ if (!block->parent_irq) ++ break; ++ ++ if (block->mask_cache[reg] & BIT(bit)) ++ __bcm6345_periph_enable(block, reg, bit, true); ++ else ++ __bcm6345_periph_enable(block, reg, bit, false); ++ } ++ raw_spin_unlock(&priv->lock); ++} ++ ++#ifdef CONFIG_SMP ++static int bcm6345_periph_set_affinity(struct irq_data *data, ++ const struct cpumask *mask, bool force) ++{ ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ struct intc_data *priv = data->domain->host_data; ++ unsigned int i, reg, bit; ++ unsigned long flags; ++ bool enabled; ++ int cpu; ++ ++ reg = hwirq / IRQS_PER_WORD; ++ bit = hwirq % IRQS_PER_WORD; ++ ++ /* we could route to more than one cpu, but performance ++ suffers, so fix it to one. ++ */ ++ cpu = cpumask_any_and(mask, cpu_online_mask); ++ if (cpu >= nr_cpu_ids) ++ return -EINVAL; ++ ++ if (cpu >= MAX_PARENT_IRQS) ++ return -EINVAL; ++ ++ if (!priv->block[cpu].parent_irq) ++ return -EINVAL; ++ ++ raw_spin_lock_irqsave(&priv->lock, flags); ++ enabled = !irqd_irq_masked(data); ++ for (i = 0; i < MAX_PARENT_IRQS; i++) { ++ struct intc_block *block = &priv->block[i]; ++ ++ if (!block->parent_irq) ++ break; ++ ++ if (i == cpu) { ++ block->mask_cache[reg] |= BIT(bit); ++ __bcm6345_periph_enable(block, reg, bit, enabled); ++ } else { ++ block->mask_cache[reg] &= ~BIT(bit); ++ __bcm6345_periph_enable(block, reg, bit, false); ++ } ++ } ++ raw_spin_unlock_irqrestore(&priv->lock, flags); ++ ++ return 0; ++} ++#endif ++ ++static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq, ++ irq_hw_number_t hw) ++{ ++ struct intc_data *priv = d->host_data; ++ ++ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops bcm6345_periph_domain_ops = { ++ .xlate = irq_domain_xlate_onecell, ++ .map = bcm6345_periph_map, ++}; ++ ++static int __init __bcm6345_periph_intc_init(struct device_node *node, ++ int num_blocks, int *irq, ++ void __iomem **base, int num_words) ++{ ++ struct intc_data *data; ++ unsigned int i, w, status_offset; ++ ++ data = kzalloc(sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ raw_spin_lock_init(&data->lock); ++ ++ status_offset = num_words * sizeof(u32); ++ ++ for (i = 0; i < num_blocks; i++) { ++ struct intc_block *block = &data->block[i]; ++ ++ block->parent_irq = irq[i]; ++ block->base = base[i]; ++ ++ for (w = 0; w < num_words; w++) { ++ int word_offset = sizeof(u32) * ((num_words - w) - 1); ++ ++ block->en_reg[w] = base[i] + word_offset; ++ block->status_reg[w] = base[i] + status_offset; ++ block->status_reg[w] += word_offset; ++ ++ /* route all interrupts to line 0 by default */ ++ if (i == 0) ++ block->mask_cache[w] = 0xffffffff; ++ } ++ ++ irq_set_handler_data(block->parent_irq, data); ++ irq_set_chained_handler(block->parent_irq, ++ bcm6345_periph_irq_handle); ++ } ++ ++ data->num_words = num_words; ++ ++ data->chip.name = "bcm6345-periph-intc"; ++ data->chip.irq_mask = bcm6345_periph_irq_mask; ++ data->chip.irq_unmask = bcm6345_periph_irq_unmask; ++ ++#ifdef CONFIG_SMP ++ if (num_blocks > 1) ++ data->chip.irq_set_affinity = bcm6345_periph_set_affinity; ++#endif ++ ++ data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words, ++ VIRQ_BASE, ++ &bcm6345_periph_domain_ops, data); ++ if (!data->domain) { ++ kfree(data); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++void __init bcm6345_periph_intc_init(int num_blocks, int *irq, ++ void __iomem **base, int num_words) ++{ ++ __bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words); ++} ++ ++#ifdef CONFIG_OF ++static int __init bcm6345_periph_of_init(struct device_node *node, ++ struct device_node *parent) ++{ ++ struct resource res; ++ int num_irqs, ret = -EINVAL; ++ int irqs[MAX_PARENT_IRQS] = { 0 }; ++ void __iomem *bases[MAX_PARENT_IRQS] = { NULL }; ++ int words = 0; ++ int i; ++ ++ num_irqs = of_irq_count(node); ++ ++ if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS) ++ return -EINVAL; ++ ++ for (i = 0; i < num_irqs; i++) { ++ resource_size_t size; ++ ++ irqs[i] = irq_of_parse_and_map(node, i); ++ if (!irqs[i]) ++ goto out_unmap; ++ ++ if (of_address_to_resource(node, i, &res)) ++ goto out_unmap; ++ ++ size = resource_size(&res); ++ switch (size) { ++ case 8: ++ case 16: ++ case 32: ++ size = size / 8; ++ break; ++ default: ++ goto out_unmap; ++ } ++ ++ if (words && words != size) { ++ ret = -EINVAL; ++ goto out_unmap; ++ } ++ words = size; ++ ++ bases[i] = of_iomap(node, i); ++ if (!bases[i]) { ++ ret = -ENOMEM; ++ goto out_unmap; ++ } ++ } ++ ++ ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words); ++ if (!ret) ++ return 0; ++ ++out_unmap: ++ for (i = 0; i < num_irqs; i++) { ++ iounmap(bases[i]); ++ irq_dispose_mapping(irqs[i]); ++ } ++ ++ return ret; ++} ++ ++IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-periph-intc", ++ bcm6345_periph_of_init); ++#endif +--- /dev/null ++++ b/include/linux/irqchip/irq-bcm6345-periph.h +@@ -0,0 +1,16 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2008 Nicolas Schichan ++ */ ++ ++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H ++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H ++ ++void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base, ++ int num_words); ++ ++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */ diff --git a/target/linux/brcm63xx/patches-3.18/321-irqchip-add-support-for-bcm6345-style-external-inter.patch b/target/linux/brcm63xx/patches-3.18/321-irqchip-add-support-for-bcm6345-style-external-inter.patch new file mode 100644 index 0000000..fa2b2f3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/321-irqchip-add-support-for-bcm6345-style-external-inter.patch @@ -0,0 +1,381 @@ +From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Nov 2014 14:54:27 +0100 +Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external + interrupt controller + +Signed-off-by: Jonas Gorski +--- + .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 29 ++ + drivers/irqchip/Kconfig | 4 + + drivers/irqchip/Makefile | 1 + + drivers/irqchip/irq-bcm6345-ext.c | 287 ++++++++++++++++++++ + include/linux/irqchip/irq-bcm6345-ext.h | 14 + + 5 files changed, 335 insertions(+) + create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt + create mode 100644 drivers/irqchip/irq-bcm6345-ext.c + create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt +@@ -0,0 +1,29 @@ ++Broadcom BCM6345-style external interrupt controller ++ ++Required properties: ++ ++- compatible: Should be "brcm,bcm6345-ext-intc". ++- reg: Specifies the base physical addresses and size of the registers. ++- interrupt-controller: identifies the node as an interrupt controller. ++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt ++ source, Should be 2. ++- interrupt-parent: Specifies the phandle to the parent interrupt controller ++ this one is cascaded from. ++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller ++ node, valid values depend on the type of parent interrupt controller. ++ ++Optional properties: ++ ++- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the ++ register. Defaults to 4. ++ ++Example: ++ ++ext_intc: interrupt-controller@10000018 { ++ compatible = "brcm,bcm6345-ext-intc"; ++ interrupt-parent = <&periph_intc>; ++ #interrupt-cells = <2>; ++ reg = <0x10000018 0x4>; ++ interrupt-controller; ++ interrupts = <24>, <25>, <26>, <27>; ++}; +--- a/drivers/irqchip/Kconfig ++++ b/drivers/irqchip/Kconfig +@@ -54,6 +54,10 @@ config BRCMSTB_L2_IRQ + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + ++config BCM6345_EXT_IRQ ++ bool ++ select IRQ_DOMAIN ++ + config BCM6345_PERIPH_IRQ + bool + select IRQ_DOMAIN +--- a/drivers/irqchip/Makefile ++++ b/drivers/irqchip/Makefile +@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o + obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o + obj-$(CONFIG_ARCH_MXS) += irq-mxs.o + obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o ++obj-$(CONFIG_BCM6345_EXT_IRQ) += irq-bcm6345-ext.o + obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o + obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o + obj-$(CONFIG_METAG) += irq-metag-ext.o +--- /dev/null ++++ b/drivers/irqchip/irq-bcm6345-ext.c +@@ -0,0 +1,288 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2014 Jonas Gorski ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "irqchip.h" ++ ++#ifdef CONFIG_BCM63XX ++#include ++ ++#define VIRQ_BASE IRQ_EXTERNAL_BASE ++#else ++#define VIRQ_BASE 0 ++#endif ++ ++#define MAX_IRQS 4 ++ ++#define EXTIRQ_CFG_SENSE 0 ++#define EXTIRQ_CFG_STAT 1 ++#define EXTIRQ_CFG_CLEAR 2 ++#define EXTIRQ_CFG_MASK 3 ++#define EXTIRQ_CFG_BOTHEDGE 4 ++#define EXTIRQ_CFG_LEVELSENSE 5 ++ ++struct intc_data { ++ struct irq_chip chip; ++ struct irq_domain *domain; ++ raw_spinlock_t lock; ++ ++ int parent_irq[MAX_IRQS]; ++ void __iomem *reg; ++ int shift; ++}; ++ ++static void bcm6345_ext_intc_irq_handle(unsigned int irq, struct irq_desc *desc) ++{ ++ struct intc_data *data = irq_desc_get_handler_data(desc); ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ unsigned int idx; ++ ++ chained_irq_enter(chip, desc); ++ ++ for (idx = 0; idx < MAX_IRQS; idx++) { ++ if (data->parent_irq[idx] != irq) ++ continue; ++ ++ generic_handle_irq(irq_find_mapping(data->domain, idx)); ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static void bcm6345_ext_intc_irq_ack(struct irq_data *data) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ u32 reg; ++ ++ raw_spin_lock(&priv->lock); ++ reg = __raw_readl(priv->reg); ++ reg |= hwirq << (EXTIRQ_CFG_CLEAR * priv->shift); ++ __raw_writel(reg, priv->reg); ++ raw_spin_unlock(&priv->lock); ++} ++ ++static void bcm6345_ext_intc_irq_mask(struct irq_data *data) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ u32 reg; ++ ++ raw_spin_lock(&priv->lock); ++ reg = __raw_readl(priv->reg); ++ reg &= ~(hwirq << (EXTIRQ_CFG_MASK * priv->shift)); ++ __raw_writel(reg, priv->reg); ++ raw_spin_unlock(&priv->lock); ++} ++ ++static void bcm6345_ext_intc_irq_unmask(struct irq_data *data) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ u32 reg; ++ ++ raw_spin_lock(&priv->lock); ++ reg = __raw_readl(priv->reg); ++ reg |= hwirq << (EXTIRQ_CFG_MASK * priv->shift); ++ __raw_writel(reg, priv->reg); ++ raw_spin_unlock(&priv->lock); ++} ++ ++static int bcm6345_ext_intc_set_type(struct irq_data *data, ++ unsigned int flow_type) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ bool levelsense = 0, sense = 0, bothedge = 0; ++ u32 reg; ++ ++ flow_type &= IRQ_TYPE_SENSE_MASK; ++ ++ if (flow_type == IRQ_TYPE_NONE) ++ flow_type = IRQ_TYPE_LEVEL_LOW; ++ ++ switch (flow_type) { ++ case IRQ_TYPE_EDGE_BOTH: ++ bothedge = 1; ++ break; ++ ++ case IRQ_TYPE_EDGE_RISING: ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ sense = 1; ++ break; ++ ++ case IRQ_TYPE_LEVEL_HIGH: ++ levelsense = 1; ++ sense = 1; ++ break; ++ ++ case IRQ_TYPE_LEVEL_LOW: ++ levelsense = 1; ++ break; ++ ++ default: ++ pr_err("bogus flow type combination given!\n"); ++ return -EINVAL; ++ } ++ ++ raw_spin_lock(&priv->lock); ++ reg = __raw_readl(priv->reg); ++ ++ if (levelsense) ++ reg |= hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift); ++ else ++ reg &= ~(hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift)); ++ if (sense) ++ reg |= hwirq << (EXTIRQ_CFG_SENSE * priv->shift); ++ else ++ reg &= ~(hwirq << (EXTIRQ_CFG_SENSE * priv->shift)); ++ if (bothedge) ++ reg |= hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift); ++ else ++ reg &= ~(hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift)); ++ ++ __raw_writel(reg, priv->reg); ++ raw_spin_unlock(&priv->lock); ++ ++ irqd_set_trigger_type(data, flow_type); ++ if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) ++ __irq_set_handler_locked(data->irq, handle_level_irq); ++ else ++ __irq_set_handler_locked(data->irq, handle_edge_irq); ++ ++ return 0; ++} ++ ++static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq, ++ irq_hw_number_t hw) ++{ ++ struct intc_data *priv = d->host_data; ++ ++ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops bcm6345_ext_domain_ops = { ++ .xlate = irq_domain_xlate_twocell, ++ .map = bcm6345_ext_intc_map, ++}; ++ ++static int __init __bcm6345_ext_intc_init(struct device_node *node, ++ int num_irqs, int *irqs, ++ void __iomem *reg, int shift) ++{ ++ struct intc_data *data; ++ unsigned int i; ++ int start = VIRQ_BASE; ++ ++ data = kzalloc(sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ raw_spin_lock_init(&data->lock); ++ ++ for (i = 0; i < num_irqs; i++) { ++ data->parent_irq[i] = irqs[i]; ++ ++ irq_set_handler_data(irqs[i], data); ++ irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle); ++ } ++ ++ data->reg = reg; ++ data->shift = shift; ++ ++ data->chip.name = "bcm6345-ext-intc"; ++ data->chip.irq_ack = bcm6345_ext_intc_irq_ack; ++ data->chip.irq_mask = bcm6345_ext_intc_irq_mask; ++ data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask; ++ data->chip.irq_set_type = bcm6345_ext_intc_set_type; ++ ++ /* ++ * If we have less than 4 irqs, this is the second controller on ++ * bcm63xx. So increase the VIRQ start to not overlap with the first ++ * one, but only do so if we actually use a non-zero start. ++ * ++ * This can be removed when bcm63xx has no legacy users anymore. ++ */ ++ if (start && num_irqs < 4) ++ start += 4; ++ ++ data->domain = irq_domain_add_simple(node, num_irqs, start, ++ &bcm6345_ext_domain_ops, data); ++ if (!data->domain) { ++ kfree(data); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg, ++ int shift) ++{ ++ __bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift); ++} ++ ++#ifdef CONFIG_OF ++static int __init bcm6345_ext_intc_of_init(struct device_node *node, ++ struct device_node *parent) ++{ ++ int num_irqs, ret = -EINVAL; ++ unsigned i; ++ void __iomem *base; ++ int irqs[MAX_IRQS] = { 0 }; ++ u32 shift; ++ ++ num_irqs = of_irq_count(node); ++ ++ if (!num_irqs || num_irqs > MAX_IRQS) ++ return -EINVAL; ++ ++ if (of_property_read_u32(node, "brcm,field-width", &shift)) ++ shift = 4; ++ ++ for (i = 0; i < num_irqs; i++) { ++ irqs[i] = irq_of_parse_and_map(node, i); ++ if (!irqs[i]) { ++ ret = -ENOMEM; ++ goto out_unmap; ++ } ++ } ++ ++ base = of_iomap(node, 0); ++ if (!base) ++ goto out_unmap; ++ ++ ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift); ++ if (!ret) ++ return 0; ++out_unmap: ++ iounmap(base); ++ ++ for (i = 0; i < num_irqs; i++) ++ irq_dispose_mapping(irqs[i]); ++ ++ return ret; ++} ++ ++IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc", ++ bcm6345_ext_intc_of_init); ++#endif +--- /dev/null ++++ b/include/linux/irqchip/irq-bcm6345-ext.h +@@ -0,0 +1,14 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2014 Jonas Gorski ++ */ ++ ++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H ++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H ++ ++void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift); ++ ++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */ diff --git a/target/linux/brcm63xx/patches-3.18/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch b/target/linux/brcm63xx/patches-3.18/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch new file mode 100644 index 0000000..54d9094 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch @@ -0,0 +1,695 @@ +From cfe7647c2a4decf874dff8abb60704e9917f76fe Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Nov 2014 14:55:02 +0100 +Subject: [PATCH 3/5] MIPS: BCM63XX: switch to IRQ_DOMAIN + +Now that we have working IRQ_DOMAIN drivers for both interrupt controllers, +switch to using them. + +Signed-off-by: Jonas Gorski +--- + arch/mips/Kconfig | 3 + + arch/mips/bcm63xx/irq.c | 609 +++++++++-------------------------------------- + 2 files changed, 109 insertions(+), 503 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -144,6 +144,9 @@ config BCM63XX + select SYNC_R4K + select DMA_NONCOHERENT + select IRQ_CPU ++ select BCM6345_EXT_IRQ ++ select BCM6345_PERIPH_IRQ ++ select IRQ_DOMAIN + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_HAS_EARLY_PRINTK +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -12,7 +12,9 @@ + #include + #include + #include +-#include ++#include ++#include ++#include + #include + #include + #include +@@ -20,544 +22,145 @@ + #include + #include + +- +-static DEFINE_SPINLOCK(ipic_lock); +-static DEFINE_SPINLOCK(epic_lock); +- +-static u32 irq_stat_addr[2]; +-static u32 irq_mask_addr[2]; +-static void (*dispatch_internal)(int cpu); +-static int is_ext_irq_cascaded; +-static unsigned int ext_irq_count; +-static unsigned int ext_irq_start, ext_irq_end; +-static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; +-static void (*internal_irq_mask)(struct irq_data *d); +-static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m); +- +- +-static inline u32 get_ext_irq_perf_reg(int irq) +-{ +- if (irq < 4) +- return ext_irq_cfg_reg1; +- return ext_irq_cfg_reg2; +-} +- +-static inline void handle_internal(int intbit) +-{ +- if (is_ext_irq_cascaded && +- intbit >= ext_irq_start && intbit <= ext_irq_end) +- do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE); +- else +- do_IRQ(intbit + IRQ_INTERNAL_BASE); +-} +- +-static inline int enable_irq_for_cpu(int cpu, struct irq_data *d, +- const struct cpumask *m) +-{ +- bool enable = cpu_online(cpu); +- +-#ifdef CONFIG_SMP +- if (m) +- enable &= cpu_isset(cpu, *m); +- else if (irqd_affinity_was_set(d)) +- enable &= cpu_isset(cpu, *d->affinity); +-#endif +- return enable; +-} +- +-/* +- * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not +- * prioritize any interrupt relatively to another. the static counter +- * will resume the loop where it ended the last time we left this +- * function. +- */ +- +-#define BUILD_IPIC_INTERNAL(width) \ +-void __dispatch_internal_##width(int cpu) \ +-{ \ +- u32 pending[width / 32]; \ +- unsigned int src, tgt; \ +- bool irqs_pending = false; \ +- static unsigned int i[2]; \ +- unsigned int *next = &i[cpu]; \ +- unsigned long flags; \ +- \ +- /* read registers in reverse order */ \ +- spin_lock_irqsave(&ipic_lock, flags); \ +- for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ +- u32 val; \ +- \ +- val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \ +- val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \ +- pending[--tgt] = val; \ +- \ +- if (val) \ +- irqs_pending = true; \ +- } \ +- spin_unlock_irqrestore(&ipic_lock, flags); \ +- \ +- if (!irqs_pending) \ +- return; \ +- \ +- while (1) { \ +- unsigned int to_call = *next; \ +- \ +- *next = (*next + 1) & (width - 1); \ +- if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ +- handle_internal(to_call); \ +- break; \ +- } \ +- } \ +-} \ +- \ +-static void __internal_irq_mask_##width(struct irq_data *d) \ +-{ \ +- u32 val; \ +- unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ +- unsigned reg = (irq / 32) ^ (width/32 - 1); \ +- unsigned bit = irq & 0x1f; \ +- unsigned long flags; \ +- int cpu; \ +- \ +- spin_lock_irqsave(&ipic_lock, flags); \ +- for_each_present_cpu(cpu) { \ +- if (!irq_mask_addr[cpu]) \ +- break; \ +- \ +- val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ +- val &= ~(1 << bit); \ +- bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ +- } \ +- spin_unlock_irqrestore(&ipic_lock, flags); \ +-} \ +- \ +-static void __internal_irq_unmask_##width(struct irq_data *d, \ +- const struct cpumask *m) \ +-{ \ +- u32 val; \ +- unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ +- unsigned reg = (irq / 32) ^ (width/32 - 1); \ +- unsigned bit = irq & 0x1f; \ +- unsigned long flags; \ +- int cpu; \ +- \ +- spin_lock_irqsave(&ipic_lock, flags); \ +- for_each_present_cpu(cpu) { \ +- if (!irq_mask_addr[cpu]) \ +- break; \ +- \ +- val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ +- if (enable_irq_for_cpu(cpu, d, m)) \ +- val |= (1 << bit); \ +- else \ +- val &= ~(1 << bit); \ +- bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ +- } \ +- spin_unlock_irqrestore(&ipic_lock, flags); \ +-} +- +-BUILD_IPIC_INTERNAL(32); +-BUILD_IPIC_INTERNAL(64); +- +-asmlinkage void plat_irq_dispatch(void) +-{ +- u32 cause; +- +- do { +- cause = read_c0_cause() & read_c0_status() & ST0_IM; +- +- if (!cause) +- break; +- +- if (cause & CAUSEF_IP7) +- do_IRQ(7); +- if (cause & CAUSEF_IP0) +- do_IRQ(0); +- if (cause & CAUSEF_IP1) +- do_IRQ(1); +- if (cause & CAUSEF_IP2) +- dispatch_internal(0); +- if (is_ext_irq_cascaded) { +- if (cause & CAUSEF_IP3) +- dispatch_internal(1); +- } else { +- if (cause & CAUSEF_IP3) +- do_IRQ(IRQ_EXT_0); +- if (cause & CAUSEF_IP4) +- do_IRQ(IRQ_EXT_1); +- if (cause & CAUSEF_IP5) +- do_IRQ(IRQ_EXT_2); +- if (cause & CAUSEF_IP6) +- do_IRQ(IRQ_EXT_3); +- } +- } while (1); +-} +- +-/* +- * internal IRQs operations: only mask/unmask on PERF irq mask +- * register. +- */ +-static void bcm63xx_internal_irq_mask(struct irq_data *d) +-{ +- internal_irq_mask(d); +-} +- +-static void bcm63xx_internal_irq_unmask(struct irq_data *d) +-{ +- internal_irq_unmask(d, NULL); +-} +- +-/* +- * external IRQs operations: mask/unmask and clear on PERF external +- * irq control register. +- */ +-static void bcm63xx_external_irq_mask(struct irq_data *d) +-{ +- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; +- u32 reg, regaddr; +- unsigned long flags; +- +- regaddr = get_ext_irq_perf_reg(irq); +- spin_lock_irqsave(&epic_lock, flags); +- reg = bcm_perf_readl(regaddr); +- +- if (BCMCPU_IS_6348()) +- reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); +- else +- reg &= ~EXTIRQ_CFG_MASK(irq % 4); +- +- bcm_perf_writel(reg, regaddr); +- spin_unlock_irqrestore(&epic_lock, flags); +- +- if (is_ext_irq_cascaded) +- internal_irq_mask(irq_get_irq_data(irq + ext_irq_start)); +-} +- +-static void bcm63xx_external_irq_unmask(struct irq_data *d) +-{ +- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; +- u32 reg, regaddr; +- unsigned long flags; +- +- regaddr = get_ext_irq_perf_reg(irq); +- spin_lock_irqsave(&epic_lock, flags); +- reg = bcm_perf_readl(regaddr); +- +- if (BCMCPU_IS_6348()) +- reg |= EXTIRQ_CFG_MASK_6348(irq % 4); +- else +- reg |= EXTIRQ_CFG_MASK(irq % 4); +- +- bcm_perf_writel(reg, regaddr); +- spin_unlock_irqrestore(&epic_lock, flags); +- +- if (is_ext_irq_cascaded) +- internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start), +- NULL); +-} +- +-static void bcm63xx_external_irq_clear(struct irq_data *d) +-{ +- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; +- u32 reg, regaddr; +- unsigned long flags; +- +- regaddr = get_ext_irq_perf_reg(irq); +- spin_lock_irqsave(&epic_lock, flags); +- reg = bcm_perf_readl(regaddr); +- +- if (BCMCPU_IS_6348()) +- reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); +- else +- reg |= EXTIRQ_CFG_CLEAR(irq % 4); +- +- bcm_perf_writel(reg, regaddr); +- spin_unlock_irqrestore(&epic_lock, flags); +-} +- +-static int bcm63xx_external_irq_set_type(struct irq_data *d, +- unsigned int flow_type) +-{ +- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; +- u32 reg, regaddr; +- int levelsense, sense, bothedge; +- unsigned long flags; +- +- flow_type &= IRQ_TYPE_SENSE_MASK; +- +- if (flow_type == IRQ_TYPE_NONE) +- flow_type = IRQ_TYPE_LEVEL_LOW; +- +- levelsense = sense = bothedge = 0; +- switch (flow_type) { +- case IRQ_TYPE_EDGE_BOTH: +- bothedge = 1; +- break; +- +- case IRQ_TYPE_EDGE_RISING: +- sense = 1; +- break; +- +- case IRQ_TYPE_EDGE_FALLING: +- break; +- +- case IRQ_TYPE_LEVEL_HIGH: +- levelsense = 1; +- sense = 1; +- break; +- +- case IRQ_TYPE_LEVEL_LOW: +- levelsense = 1; +- break; +- +- default: +- printk(KERN_ERR "bogus flow type combination given !\n"); +- return -EINVAL; +- } +- +- regaddr = get_ext_irq_perf_reg(irq); +- spin_lock_irqsave(&epic_lock, flags); +- reg = bcm_perf_readl(regaddr); +- irq %= 4; +- +- switch (bcm63xx_get_cpu_id()) { +- case BCM6348_CPU_ID: +- if (levelsense) +- reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); +- else +- reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq); +- if (sense) +- reg |= EXTIRQ_CFG_SENSE_6348(irq); +- else +- reg &= ~EXTIRQ_CFG_SENSE_6348(irq); +- if (bothedge) +- reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); +- else +- reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); +- break; +- +- case BCM3368_CPU_ID: +- case BCM6328_CPU_ID: +- case BCM6338_CPU_ID: +- case BCM6345_CPU_ID: +- case BCM6358_CPU_ID: +- case BCM6362_CPU_ID: +- case BCM6368_CPU_ID: +- if (levelsense) +- reg |= EXTIRQ_CFG_LEVELSENSE(irq); +- else +- reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); +- if (sense) +- reg |= EXTIRQ_CFG_SENSE(irq); +- else +- reg &= ~EXTIRQ_CFG_SENSE(irq); +- if (bothedge) +- reg |= EXTIRQ_CFG_BOTHEDGE(irq); +- else +- reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); +- break; +- default: +- BUG(); +- } +- +- bcm_perf_writel(reg, regaddr); +- spin_unlock_irqrestore(&epic_lock, flags); +- +- irqd_set_trigger_type(d, flow_type); +- if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) +- __irq_set_handler_locked(d->irq, handle_level_irq); +- else +- __irq_set_handler_locked(d->irq, handle_edge_irq); +- +- return IRQ_SET_MASK_OK_NOCOPY; +-} +- +-#ifdef CONFIG_SMP +-static int bcm63xx_internal_set_affinity(struct irq_data *data, +- const struct cpumask *dest, +- bool force) +-{ +- if (!irqd_irq_disabled(data)) +- internal_irq_unmask(data, dest); +- +- return 0; +-} +-#endif +- +-static struct irq_chip bcm63xx_internal_irq_chip = { +- .name = "bcm63xx_ipic", +- .irq_mask = bcm63xx_internal_irq_mask, +- .irq_unmask = bcm63xx_internal_irq_unmask, +-}; +- +-static struct irq_chip bcm63xx_external_irq_chip = { +- .name = "bcm63xx_epic", +- .irq_ack = bcm63xx_external_irq_clear, +- +- .irq_mask = bcm63xx_external_irq_mask, +- .irq_unmask = bcm63xx_external_irq_unmask, +- +- .irq_set_type = bcm63xx_external_irq_set_type, +-}; +- +-static struct irqaction cpu_ip2_cascade_action = { +- .handler = no_action, +- .name = "cascade_ip2", +- .flags = IRQF_NO_THREAD, +-}; +- +-#ifdef CONFIG_SMP +-static struct irqaction cpu_ip3_cascade_action = { +- .handler = no_action, +- .name = "cascade_ip3", +- .flags = IRQF_NO_THREAD, +-}; +-#endif +- +-static struct irqaction cpu_ext_cascade_action = { +- .handler = no_action, +- .name = "cascade_extirq", +- .flags = IRQF_NO_THREAD, +-}; +- + static void bcm63xx_init_irq(void) + { +- int irq_bits; +- +- irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); +- irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); +- irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF); +- irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF); ++ void __iomem *periph_bases[2]; ++ void __iomem *ext_intc_bases[2]; ++ int periph_irq_count, periph_width, ext_irq_count, ext_shift; ++ int periph_irqs[2] = { 2, 3 }; ++ int ext_irqs[6]; ++ ++ periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); ++ periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); ++ ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); ++ ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); + + switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; +- irq_mask_addr[0] += PERF_IRQMASK_3368_REG; +- irq_stat_addr[1] = 0; +- irq_mask_addr[1] = 0; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; ++ periph_bases[0] += PERF_IRQMASK_3368_REG; ++ periph_irq_count = 1; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_3368_EXT_IRQ0; ++ ext_irqs[1] = BCM_3368_EXT_IRQ1; ++ ext_irqs[2] = BCM_3368_EXT_IRQ2; ++ ext_irqs[3] = BCM_3368_EXT_IRQ3; ++ ext_shift = 4; + break; + case BCM6328_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); +- irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); +- irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1); +- irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1); +- irq_bits = 64; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; ++ periph_bases[0] += PERF_IRQMASK_6328_REG(0); ++ periph_bases[1] += PERF_IRQMASK_6328_REG(1); ++ periph_irq_count = 2; ++ periph_width = 2; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_6328_EXT_IRQ0; ++ ext_irqs[1] = BCM_6328_EXT_IRQ1; ++ ext_irqs[2] = BCM_6328_EXT_IRQ2; ++ ext_irqs[3] = BCM_6328_EXT_IRQ3; ++ ext_shift = 4; + break; + case BCM6338_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; +- irq_mask_addr[0] += PERF_IRQMASK_6338_REG; +- irq_stat_addr[1] = 0; +- irq_mask_addr[1] = 0; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; ++ periph_bases[0] += PERF_IRQMASK_6338_REG; ++ periph_irq_count = 1; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338; ++ ext_irq_count = 4; ++ ext_irqs[0] = 3; ++ ext_irqs[1] = 4; ++ ext_irqs[2] = 5; ++ ext_irqs[3] = 6; ++ ext_shift = 4; + break; + case BCM6345_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; +- irq_mask_addr[0] += PERF_IRQMASK_6345_REG; +- irq_stat_addr[1] = 0; +- irq_mask_addr[1] = 0; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; ++ periph_bases[0] += PERF_IRQMASK_6345_REG; ++ periph_irq_count = 1; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345; ++ ext_irq_count = 4; ++ ext_irqs[0] = 3; ++ ext_irqs[1] = 4; ++ ext_irqs[2] = 5; ++ ext_irqs[3] = 6; ++ ext_shift = 4; + break; + case BCM6348_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; +- irq_mask_addr[0] += PERF_IRQMASK_6348_REG; +- irq_stat_addr[1] = 0; +- irq_mask_addr[1] = 0; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; ++ periph_bases[0] += PERF_IRQMASK_6348_REG; ++ periph_irq_count = 1; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348; ++ ext_irq_count = 4; ++ ext_irqs[0] = 3; ++ ext_irqs[1] = 4; ++ ext_irqs[2] = 5; ++ ext_irqs[3] = 6; ++ ext_shift = 5; + break; + case BCM6358_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); +- irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); +- irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1); +- irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1); +- irq_bits = 32; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; ++ periph_bases[0] += PERF_IRQMASK_6358_REG(0); ++ periph_bases[1] += PERF_IRQMASK_6358_REG(1); ++ periph_irq_count = 2; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_6358_EXT_IRQ0; ++ ext_irqs[1] = BCM_6358_EXT_IRQ1; ++ ext_irqs[2] = BCM_6358_EXT_IRQ2; ++ ext_irqs[3] = BCM_6358_EXT_IRQ3; ++ ext_shift = 4; + break; + case BCM6362_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); +- irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); +- irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1); +- irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1); +- irq_bits = 64; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; ++ periph_bases[0] += PERF_IRQMASK_6362_REG(0); ++ periph_bases[1] += PERF_IRQMASK_6362_REG(1); ++ periph_irq_count = 2; ++ periph_width = 2; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_6362_EXT_IRQ0; ++ ext_irqs[1] = BCM_6362_EXT_IRQ1; ++ ext_irqs[2] = BCM_6362_EXT_IRQ2; ++ ext_irqs[3] = BCM_6362_EXT_IRQ3; ++ ext_shift = 4; + break; + case BCM6368_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); +- irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); +- irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1); +- irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1); +- irq_bits = 64; ++ periph_bases[0] += PERF_IRQMASK_6368_REG(0); ++ periph_bases[1] += PERF_IRQMASK_6368_REG(1); ++ periph_irq_count = 2; ++ periph_width = 2; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368; ++ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368; + ext_irq_count = 6; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; +- ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; ++ ext_irqs[0] = BCM_6368_EXT_IRQ0; ++ ext_irqs[1] = BCM_6368_EXT_IRQ1; ++ ext_irqs[2] = BCM_6368_EXT_IRQ2; ++ ext_irqs[3] = BCM_6368_EXT_IRQ3; ++ ext_irqs[4] = BCM_6368_EXT_IRQ4; ++ ext_irqs[5] = BCM_6368_EXT_IRQ5; ++ ext_shift = 4; + break; + default: + BUG(); + } + +- if (irq_bits == 32) { +- dispatch_internal = __dispatch_internal_32; +- internal_irq_mask = __internal_irq_mask_32; +- internal_irq_unmask = __internal_irq_unmask_32; +- } else { +- dispatch_internal = __dispatch_internal_64; +- internal_irq_mask = __internal_irq_mask_64; +- internal_irq_unmask = __internal_irq_unmask_64; +- } ++ mips_cpu_irq_init(); ++ bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases, ++ periph_width); ++ bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift); ++ if (ext_irq_count > 4) ++ bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1], ++ ext_shift); + } + + void __init arch_init_irq(void) + { +- int i; +- + bcm63xx_init_irq(); +- mips_cpu_irq_init(); +- for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) +- irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, +- handle_level_irq); +- +- for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i) +- irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, +- handle_edge_irq); +- +- if (!is_ext_irq_cascaded) { +- for (i = 3; i < 3 + ext_irq_count; ++i) +- setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); +- } +- +- setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); +-#ifdef CONFIG_SMP +- if (is_ext_irq_cascaded) { +- setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); +- bcm63xx_internal_irq_chip.irq_set_affinity = +- bcm63xx_internal_set_affinity; +- +- cpumask_clear(irq_default_affinity); +- cpumask_set_cpu(smp_processor_id(), irq_default_affinity); +- } +-#endif + } diff --git a/target/linux/brcm63xx/patches-3.18/323-MIPS-BCM63XX-wire-up-BCM6358-s-external-interrupts-4.patch b/target/linux/brcm63xx/patches-3.18/323-MIPS-BCM63XX-wire-up-BCM6358-s-external-interrupts-4.patch new file mode 100644 index 0000000..a2ee1b6 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/323-MIPS-BCM63XX-wire-up-BCM6358-s-external-interrupts-4.patch @@ -0,0 +1,57 @@ +From 4fd286c3e5a5bebab0391cf1937695b3ed6721a3 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Nov 2014 20:20:30 +0100 +Subject: [PATCH 4/5] MIPS: BCM63XX: wire up BCM6358's external interrupts 4 + and 5 + +Due to the external interrupts being non consecutive, the previous +implementation did not support them. Now that we treat both registers +as separate irq controllers, there is no such limitation anymore and +we can expose them for drivers to use. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/irq.c | 5 ++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 ++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 1 + + 3 files changed, 7 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -109,11 +109,14 @@ static void bcm63xx_init_irq(void) + periph_width = 1; + + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358; +- ext_irq_count = 4; ++ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6358; ++ ext_irq_count = 6; + ext_irqs[0] = BCM_6358_EXT_IRQ0; + ext_irqs[1] = BCM_6358_EXT_IRQ1; + ext_irqs[2] = BCM_6358_EXT_IRQ2; + ext_irqs[3] = BCM_6358_EXT_IRQ3; ++ ext_irqs[4] = BCM_6358_EXT_IRQ4; ++ ext_irqs[5] = BCM_6358_EXT_IRQ5; + ext_shift = 4; + break; + case BCM6362_CPU_ID: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -895,6 +895,8 @@ enum bcm63xx_irq { + #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) + #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) + #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) ++#define BCM_6358_EXT_IRQ4 (IRQ_INTERNAL_BASE + 20) ++#define BCM_6358_EXT_IRQ5 (IRQ_INTERNAL_BASE + 21) + + /* + * 6362 irqs +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -243,6 +243,7 @@ + #define PERF_EXTIRQ_CFG_REG_6362 0x18 + #define PERF_EXTIRQ_CFG_REG_6368 0x18 + ++#define PERF_EXTIRQ_CFG_REG2_6358 0x1c + #define PERF_EXTIRQ_CFG_REG2_6368 0x1c + + /* for 6348 only */ diff --git a/target/linux/brcm63xx/patches-3.18/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch b/target/linux/brcm63xx/patches-3.18/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch new file mode 100644 index 0000000..661abf6 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch @@ -0,0 +1,77 @@ +From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:08:36 +0100 +Subject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper + +--- + arch/mips/bcm63xx/cpu.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++ + 2 files changed, 28 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs); + u16 bcm63xx_cpu_id __read_mostly; + EXPORT_SYMBOL(bcm63xx_cpu_id); + ++static u32 bcm63xx_cpu_variant __read_mostly; ++ + static u8 bcm63xx_cpu_rev; + static unsigned int bcm63xx_cpu_freq; + static unsigned int bcm63xx_memory_size; +@@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = { + + }; + ++u32 bcm63xx_get_cpu_variant(void) ++{ ++ return bcm63xx_cpu_variant; ++} ++ ++EXPORT_SYMBOL(bcm63xx_get_cpu_variant); ++ + u8 bcm63xx_get_cpu_rev(void) + { + return bcm63xx_cpu_rev; +@@ -333,6 +342,7 @@ void __init bcm63xx_cpu_init(void) + /* read out CPU type */ + tmp = bcm_readl(chipid_reg); + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; ++ bcm63xx_cpu_variant = bcm63xx_cpu_id; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; + + switch (bcm63xx_cpu_id) { +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -19,6 +19,7 @@ + #define BCM6368_CPU_ID 0x6368 + + void __init bcm63xx_cpu_init(void); ++u32 bcm63xx_get_cpu_variant(void); + u8 bcm63xx_get_cpu_rev(void); + unsigned int bcm63xx_get_cpu_freq(void); + +@@ -82,6 +83,23 @@ static inline u16 __pure bcm63xx_get_cpu + #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) + #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) + ++#define BCMCPU_VARIANT_IS_3368() \ ++ (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6328() \ ++ (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) ++#define BCMCPU_VARIANT_IS_6338() \ ++ (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) ++#define BCMCPU_VARIANT_IS_6345() \ ++ (bcm63xx_get_cpu_variant() == BCM6345_CPU_ID) ++#define BCMCPU_VARIANT_IS_6348() \ ++ (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID) ++#define BCMCPU_VARIANT_IS_6358() \ ++ (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID) ++#define BCMCPU_VARIANT_IS_6362() \ ++ (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) ++#define BCMCPU_VARIANT_IS_6368() \ ++ (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) ++ + /* + * While registers sets are (mostly) the same across 63xx CPU, base + * address of these sets do change. diff --git a/target/linux/brcm63xx/patches-3.18/331-MIPS-BCM63XX-define-variant-id-field.patch b/target/linux/brcm63xx/patches-3.18/331-MIPS-BCM63XX-define-variant-id-field.patch new file mode 100644 index 0000000..2e21c65 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/331-MIPS-BCM63XX-define-variant-id-field.patch @@ -0,0 +1,23 @@ +From 3bd8e2535265f06f79ed9c0ad788405441e091dc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:22:41 +0100 +Subject: [PATCH 21/45] MIPS: BCM63XX: define variant id field + +Some SoC have a variant id field in the chip id register. + +Signed-off-by: Jonas Gorski +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -9,6 +9,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_VARID_SHIFT 12 ++#define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 + #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) + diff --git a/target/linux/brcm63xx/patches-3.18/332-MIPS-BCM63XX-detect-BCM6328-variants.patch b/target/linux/brcm63xx/patches-3.18/332-MIPS-BCM63XX-detect-BCM6328-variants.patch new file mode 100644 index 0000000..faa002e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/332-MIPS-BCM63XX-detect-BCM6328-variants.patch @@ -0,0 +1,68 @@ +From d59120f23279ef62a48d9f94847254b061d0a8b6 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:30:59 +0100 +Subject: [PATCH 22/45] MIPS: BCM63XX: detect BCM6328 variants + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/cpu.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++++-- + 2 files changed, 16 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -305,6 +305,7 @@ void __init bcm63xx_cpu_init(void) + unsigned int tmp; + unsigned int cpu = smp_processor_id(); + u32 chipid_reg; ++ u8 __maybe_unused varid = 0; + + /* soc registers location depends on cpu type */ + chipid_reg = 0; +@@ -344,6 +345,7 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; + bcm63xx_cpu_variant = bcm63xx_cpu_id; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; ++ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; + + switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: +@@ -353,6 +355,14 @@ void __init bcm63xx_cpu_init(void) + case BCM6328_CPU_ID: + bcm63xx_regs_base = bcm6328_regs_base; + bcm63xx_irqs = bcm6328_irqs; ++ ++ if (varid == 1) ++ bcm63xx_cpu_variant = BCM63281_CPU_ID; ++ else if (varid == 3) ++ bcm63xx_cpu_variant = BCM63283_CPU_ID; ++ else ++ pr_warn("unknown BCM6328 variant: %x\n", varid); ++ + break; + case BCM6338_CPU_ID: + bcm63xx_regs_base = bcm6338_regs_base; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -11,6 +11,8 @@ + */ + #define BCM3368_CPU_ID 0x3368 + #define BCM6328_CPU_ID 0x6328 ++#define BCM63281_CPU_ID 0x63281 ++#define BCM63283_CPU_ID 0x63283 + #define BCM6338_CPU_ID 0x6338 + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 +@@ -85,8 +87,10 @@ static inline u16 __pure bcm63xx_get_cpu + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) +-#define BCMCPU_VARIANT_IS_6328() \ +- (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) ++#define BCMCPU_VARIANT_IS_63281() \ ++ (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) ++#define BCMCPU_VARIANT_IS_63283() \ ++ (bcm63xx_get_cpu_variant() == BCM63283_CPU_ID) + #define BCMCPU_VARIANT_IS_6338() \ + (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) + #define BCMCPU_VARIANT_IS_6345() \ diff --git a/target/linux/brcm63xx/patches-3.18/333-MIPS-BCM63XX-detect-BCM6362-variants.patch b/target/linux/brcm63xx/patches-3.18/333-MIPS-BCM63XX-detect-BCM6362-variants.patch new file mode 100644 index 0000000..62ce12e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/333-MIPS-BCM63XX-detect-BCM6362-variants.patch @@ -0,0 +1,46 @@ +From 04458c3db8eb79da21ecde40ab36a1dde52bef06 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:33:28 +0100 +Subject: [PATCH 23/45] MIPS: BCM63XX: detect BCM6362 variants + +--- + arch/mips/bcm63xx/cpu.c | 8 ++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++ + 2 files changed, 11 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -383,6 +383,14 @@ void __init bcm63xx_cpu_init(void) + case BCM6362_CPU_ID: + bcm63xx_regs_base = bcm6362_regs_base; + bcm63xx_irqs = bcm6362_irqs; ++ ++ if (varid == 1) ++ bcm63xx_cpu_variant = BCM6362_CPU_ID; ++ else if (varid == 2) ++ bcm63xx_cpu_variant = BCM6361_CPU_ID; ++ else ++ pr_warn("unknown BCM6362 variant: %x\n", varid); ++ + break; + case BCM6368_CPU_ID: + bcm63xx_regs_base = bcm6368_regs_base; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -17,6 +17,7 @@ + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 + #define BCM6358_CPU_ID 0x6358 ++#define BCM6361_CPU_ID 0x6361 + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 + +@@ -99,6 +100,8 @@ static inline u16 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID) + #define BCMCPU_VARIANT_IS_6358() \ + (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID) ++#define BCMCPU_VARIANT_IS_6361() \ ++ (bcm63xx_get_cpu_variant() == BCM6361_CPU_ID) + #define BCMCPU_VARIANT_IS_6362() \ + (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) + #define BCMCPU_VARIANT_IS_6368() \ diff --git a/target/linux/brcm63xx/patches-3.18/334-MIPS-BCM63XX-detect-BCM6368-variants.patch b/target/linux/brcm63xx/patches-3.18/334-MIPS-BCM63XX-detect-BCM6368-variants.patch new file mode 100644 index 0000000..a993e23 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/334-MIPS-BCM63XX-detect-BCM6368-variants.patch @@ -0,0 +1,48 @@ +From 825cc67e56b5e624a05f6850a86d91508b786848 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:36:56 +0100 +Subject: [PATCH 24/44] MIPS: BCM63XX: detect BCM6368 variants + +The DSL-less BCM6368 variant BCM6367 uses a different chip id. Apart +from missing DSL, there is no difference to BCM6368, so treat it such. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/cpu.c | 4 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++ + 2 files changed, 7 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -393,8 +393,12 @@ void __init bcm63xx_cpu_init(void) + + break; + case BCM6368_CPU_ID: ++ case BCM6369_CPU_ID: + bcm63xx_regs_base = bcm6368_regs_base; + bcm63xx_irqs = bcm6368_irqs; ++ ++ /* BCM6369 is a BCM6368 without xDSL, so treat it the same */ ++ bcm63xx_cpu_id = BCM6368_CPU_ID; + break; + default: + panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -20,6 +20,7 @@ + #define BCM6361_CPU_ID 0x6361 + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 ++#define BCM6369_CPU_ID 0x6369 + + void __init bcm63xx_cpu_init(void); + u32 bcm63xx_get_cpu_variant(void); +@@ -106,6 +107,8 @@ static inline u16 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) + #define BCMCPU_VARIANT_IS_6368() \ + (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6369() \ ++ (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID) + + /* + * While registers sets are (mostly) the same across 63xx CPU, base diff --git a/target/linux/brcm63xx/patches-3.18/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch b/target/linux/brcm63xx/patches-3.18/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch new file mode 100644 index 0000000..3230add --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch @@ -0,0 +1,20 @@ +From f67f8134b4537c8bbafe7e1975edfe808b813997 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 03:05:54 +0100 +Subject: [PATCH 45/53] MIPS: BCM63XX: fix PCIe memory window size + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -41,7 +41,7 @@ + BCM_CB_MEM_SIZE - 1) + + #define BCM_PCIE_MEM_BASE_PA 0x10f00000 +-#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define BCM_PCIE_MEM_SIZE (1 * 1024 * 1024) + #define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ + BCM_PCIE_MEM_SIZE - 1) + diff --git a/target/linux/brcm63xx/patches-3.18/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch b/target/linux/brcm63xx/patches-3.18/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch new file mode 100644 index 0000000..d6eb54d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch @@ -0,0 +1,70 @@ +From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 03:13:06 +0100 +Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows + +Different SoCs use different memory windows (and sizes), so don't +hardcode it. +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 8 ++++---- + arch/mips/pci/pci-bcm63xx.c | 15 ++++++++++----- + 2 files changed, 14 insertions(+), 9 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -40,10 +40,10 @@ + #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ + BCM_CB_MEM_SIZE - 1) + +-#define BCM_PCIE_MEM_BASE_PA 0x10f00000 +-#define BCM_PCIE_MEM_SIZE (1 * 1024 * 1024) +-#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ +- BCM_PCIE_MEM_SIZE - 1) ++#define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000 ++#define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ ++ BCM_PCIE_MEM_SIZE_6328 - 1) + + /* + * Internal registers are accessed through KSEG3 +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control + + static struct resource bcm_pcie_mem_resource = { + .name = "bcm63xx PCIe memory space", +- .start = BCM_PCIE_MEM_BASE_PA, +- .end = BCM_PCIE_MEM_END_PA, ++ .start = 0, ++ .end = 0, + .flags = IORESOURCE_MEM, + }; + +@@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie( + bcm_pcie_writel(val, PCIE_CONFIG2_REG); + + /* set bar0 to little endian */ +- val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; +- val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; ++ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; ++ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; + val |= BASEMASK_REMAP_EN; + bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); + +- val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; ++ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; + bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); + + register_pci_controller(&bcm63xx_pcie_controller); +@@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void) + if (!bcm63xx_pci_enabled) + return -ENODEV; + ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; ++ } ++ + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: diff --git a/target/linux/brcm63xx/patches-3.18/337-MIPS-BCM63XX-widen-cpuid-field.patch b/target/linux/brcm63xx/patches-3.18/337-MIPS-BCM63XX-widen-cpuid-field.patch new file mode 100644 index 0000000..0ead82e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/337-MIPS-BCM63XX-widen-cpuid-field.patch @@ -0,0 +1,56 @@ +From f1477f6e3551fd6beecfee5368fed1325dcd421f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:54:51 +0100 +Subject: [PATCH 47/53] MIPS: BCM63XX: widen cpuid field + +--- + arch/mips/bcm63xx/cpu.c | 2 +- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -24,7 +24,7 @@ EXPORT_SYMBOL(bcm63xx_regs_base); + const int *bcm63xx_irqs; + EXPORT_SYMBOL(bcm63xx_irqs); + +-u16 bcm63xx_cpu_id __read_mostly; ++u32 bcm63xx_cpu_id __read_mostly; + EXPORT_SYMBOL(bcm63xx_cpu_id); + + static u32 bcm63xx_cpu_variant __read_mostly; +@@ -127,7 +127,7 @@ unsigned int bcm63xx_get_memory_size(voi + + static unsigned int detect_cpu_clock(void) + { +- u16 cpu_id = bcm63xx_get_cpu_id(); ++ u32 cpu_id = bcm63xx_get_cpu_id(); + + switch (cpu_id) { + case BCM3368_CPU_ID: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -27,7 +27,7 @@ u32 bcm63xx_get_cpu_variant(void); + u8 bcm63xx_get_cpu_rev(void); + unsigned int bcm63xx_get_cpu_freq(void); + +-static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id) ++static inline u32 __pure __bcm63xx_get_cpu_id(const u32 cpu_id) + { + switch (cpu_id) { + #ifdef CONFIG_BCM63XX_CPU_3368 +@@ -69,11 +69,11 @@ static inline u16 __pure __bcm63xx_get_c + return cpu_id; + } + +-extern u16 bcm63xx_cpu_id; ++extern u32 bcm63xx_cpu_id; + +-static inline u16 __pure bcm63xx_get_cpu_id(void) ++static inline u32 __pure bcm63xx_get_cpu_id(void) + { +- const u16 cpu_id = bcm63xx_cpu_id; ++ const u32 cpu_id = bcm63xx_cpu_id; + + return __bcm63xx_get_cpu_id(cpu_id); + } diff --git a/target/linux/brcm63xx/patches-3.18/338-MIPS-BCM63XX-increase-number-of-IRQs.patch b/target/linux/brcm63xx/patches-3.18/338-MIPS-BCM63XX-increase-number-of-IRQs.patch new file mode 100644 index 0000000..9132e42 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/338-MIPS-BCM63XX-increase-number-of-IRQs.patch @@ -0,0 +1,39 @@ +From 6f5658c845cf1f79213b1d20423a04967259fdaa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 15 Dec 2013 20:46:26 +0100 +Subject: [PATCH 48/53] MIPS: BCM63XX: increase number of IRQs + +Newer SoCs have 128 bit wide irq registers, thus 128 available internal +interupts. +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h | 4 +++- + arch/mips/include/asm/mach-bcm63xx/irq.h | 2 +- + 2 files changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h +@@ -1,10 +1,12 @@ + #ifndef BCM63XX_IRQ_H_ + #define BCM63XX_IRQ_H_ + ++#include + #include + + #define IRQ_INTERNAL_BASE 8 +-#define IRQ_EXTERNAL_BASE 100 ++#define NR_INTERNAL_IRQS 128 ++#define IRQ_EXTERNAL_BASE (IRQ_INTERNAL_BASE + NR_INTERNAL_IRQS) + #define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0) + #define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1) + #define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2) +--- a/arch/mips/include/asm/mach-bcm63xx/irq.h ++++ b/arch/mips/include/asm/mach-bcm63xx/irq.h +@@ -1,7 +1,7 @@ + #ifndef __ASM_MACH_BCM63XX_IRQ_H + #define __ASM_MACH_BCM63XX_IRQ_H + +-#define NR_IRQS 128 ++#define NR_IRQS 256 + #define MIPS_CPU_IRQ_BASE 0 + + #endif diff --git a/target/linux/brcm63xx/patches-3.18/339-MIPS-BCM63XX-add-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.18/339-MIPS-BCM63XX-add-support-for-BCM63268.patch new file mode 100644 index 0000000..1f8a37a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/339-MIPS-BCM63XX-add-support-for-BCM63268.patch @@ -0,0 +1,735 @@ +From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 17:14:17 +0100 +Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268 + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/Kconfig | 5 + + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/clk.c | 25 ++++- + arch/mips/bcm63xx/cpu.c | 59 +++++++++- + arch/mips/bcm63xx/dev-flash.c | 6 + + arch/mips/bcm63xx/dev-spi.c | 4 +- + arch/mips/bcm63xx/irq.c | 20 +++- + arch/mips/bcm63xx/reset.c | 21 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 + + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++ + arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + + 12 files changed, 342 insertions(+), 12 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -60,6 +60,11 @@ config BCM63XX_CPU_6368 + select HW_HAS_PCI + select BCM63XX_OHCI + select BCM63XX_EHCI ++ ++config BCM63XX_CPU_63268 ++ bool "support 63268 CPU" ++ select SYS_HAS_CPU_BMIPS4350 ++ select HW_HAS_PCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -717,7 +717,7 @@ void __init board_prom_init(void) + /* read base address of boot chip select (0) + * 6328/6362 do not have MPI but boot from a fixed address + */ +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { + val = 0x18000000; + } else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -133,6 +133,8 @@ static void enetsw_set(struct clk *clk, + CKCTL_6368_SWPKT_USB_EN | + CKCTL_6368_SWPKT_SAR_EN, + enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable); + else + return; + +@@ -177,6 +179,8 @@ static void usbh_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); + else + return; + +@@ -199,6 +203,8 @@ static void usbd_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_USBD_EN, enable); + else + return; + +@@ -225,9 +231,13 @@ static void spi_set(struct clk *clk, int + mask = CKCTL_6358_SPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_SPI_EN; +- else +- /* BCMCPU_IS_6368 */ ++ else if (BCMCPU_IS_6368()) + mask = CKCTL_6368_SPI_EN; ++ else if (BCMCPU_IS_63268()) ++ mask = CKCTL_63268_SPI_EN; ++ else ++ return; ++ + bcm_hwclock_set(mask, enable); + } + +@@ -246,6 +256,8 @@ static void hsspi_set(struct clk *clk, i + mask = CKCTL_6328_HSSPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_HSSPI_EN; ++ else if (BCMCPU_IS_63268()) ++ mask = CKCTL_63268_HSSPI_EN; + else + return; + +@@ -307,6 +319,8 @@ static void pcie_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); + else if (BCMCPU_IS_6362()) + bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable); + } + + static struct clk clk_pcie = { +@@ -386,9 +400,11 @@ struct clk *clk_get(struct device *dev, + return &clk_periph; + if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm")) + return &clk_pcm; +- if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) ++ if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) && ++ !strcmp(id, "ipsec")) + return &clk_ipsec; +- if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie")) ++ if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && ++ !strcmp(id, "pcie")) + return &clk_pcie; + return ERR_PTR(-ENOENT); + } +@@ -411,6 +427,7 @@ static int __init bcm63xx_clk_init(void) + clk_hsspi.rate = HSSPI_PLL_HZ_6328; + break; + case BCM6362_CPU_ID: ++ case BCM63268_CPU_ID: + clk_hsspi.rate = HSSPI_PLL_HZ_6362; + break; + } +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = { + + }; + ++static const unsigned long bcm63268_regs_base[] = { ++ __GEN_CPU_REGS_TABLE(63268) ++}; ++ ++static const int bcm63268_irqs[] = { ++ __GEN_CPU_IRQ_TABLE(63268) ++ ++}; ++ + u32 bcm63xx_get_cpu_variant(void) + { + return bcm63xx_cpu_variant; +@@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi + + return (((64 * 1000000) / p1) * p2 * ndiv) / m1; + } ++ case BCM63268_CPU_ID: ++ { ++ unsigned int tmp, mips_pll_fcvo; ++ ++ tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >> ++ STRAPBUS_63268_FCVO_SHIFT; ++ switch (mips_pll_fcvo) { ++ case 0x3: ++ case 0xe: ++ return 320000000; ++ case 0xa: ++ return 333000000; ++ case 0x2: ++ case 0xb: ++ case 0xf: ++ return 400000000; ++ default: ++ return 0; ++ } ++ } + + default: + panic("Failed to detect clock for CPU with id=%04X\n", cpu_id); +@@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) + return bcm_ddr_readl(DDR_CSEND_REG) << 24; + + if (BCMCPU_IS_6345()) { +@@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void) + unsigned int tmp; + unsigned int cpu = smp_processor_id(); + u32 chipid_reg; ++ bool long_chipid = false; + u8 __maybe_unused varid = 0; + + /* soc registers location depends on cpu type */ +@@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void) + case 0x10: + chipid_reg = BCM_6345_PERF_BASE; + break; ++ case 0x80: ++ long_chipid = true; ++ /* fall-through */ + default: + chipid_reg = BCM_6368_PERF_BASE; + break; +@@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void) + break; + } + ++ + /* + * really early to panic, but delaying panic would not help since we + * will never get any working console +@@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void) + + /* read out CPU type */ + tmp = bcm_readl(chipid_reg); +- bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; +- bcm63xx_cpu_variant = bcm63xx_cpu_id; ++ ++ if (long_chipid) { ++ bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK; ++ bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT; ++ } else { ++ bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; ++ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; ++ } ++ + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; +- varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; ++ bcm63xx_cpu_variant = bcm63xx_cpu_id; + + switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: +@@ -400,6 +442,15 @@ void __init bcm63xx_cpu_init(void) + /* BCM6369 is a BCM6368 without xDSL, so treat it the same */ + bcm63xx_cpu_id = BCM6368_CPU_ID; + break; ++ case BCM63168_CPU_ID: ++ case BCM63169_CPU_ID: ++ case BCM63268_CPU_ID: ++ case BCM63269_CPU_ID: ++ bcm63xx_regs_base = bcm63268_regs_base; ++ bcm63xx_irqs = bcm63268_irqs; ++ ++ bcm63xx_cpu_id = BCM63268_CPU_ID; ++ break; + default: + panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); + break; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -94,6 +94,12 @@ static int __init bcm63xx_detect_flash_t + case STRAPBUS_6368_BOOT_SEL_PARALLEL: + return BCM63XX_FLASH_TYPE_PARALLEL; + } ++ case BCM63268_CPU_ID: ++ val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) ++ return BCM63XX_FLASH_TYPE_SERIAL; ++ else ++ return BCM63XX_FLASH_TYPE_NAND; + default: + return -EINVAL; + } +--- a/arch/mips/bcm63xx/dev-spi.c ++++ b/arch/mips/bcm63xx/dev-spi.c +@@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init + if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) + bcm63xx_regs_spi = bcm6348_regs_spi; + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || +- BCMCPU_IS_6362() || BCMCPU_IS_6368()) ++ BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) + bcm63xx_regs_spi = bcm6358_regs_spi; + } + +@@ -85,7 +85,7 @@ int __init bcm63xx_spi_register(void) + } + + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || +- BCMCPU_IS_6368()) { ++ BCMCPU_IS_6368() || BCMCPU_IS_63268()) { + spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; + spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; + spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT; +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -150,6 +150,20 @@ static void bcm63xx_init_irq(void) + ext_irqs[5] = BCM_6368_EXT_IRQ5; + ext_shift = 4; + break; ++ case BCM63268_CPU_ID: ++ periph_bases[0] += PERF_IRQMASK_63268_REG(0); ++ periph_bases[1] += PERF_IRQMASK_63268_REG(1); ++ periph_irq_count = 2; ++ periph_width = 4; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_63268_EXT_IRQ0; ++ ext_irqs[1] = BCM_63268_EXT_IRQ1; ++ ext_irqs[2] = BCM_63268_EXT_IRQ2; ++ ext_irqs[3] = BCM_63268_EXT_IRQ3; ++ ext_shift = 4; ++ break; + default: + BUG(); + } +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -125,6 +125,20 @@ + #define BCM6368_RESET_PCIE 0 + #define BCM6368_RESET_PCIE_EXT 0 + ++#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK ++#define BCM63268_RESET_ENET 0 ++#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK ++#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK ++#define BCM63268_RESET_DSL 0 ++#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK ++#define BCM63268_RESET_EPHY 0 ++#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK ++#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK ++#define BCM63268_RESET_MPI 0 ++#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ ++ SOFTRESET_63268_PCIE_CORE_MASK) ++#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK ++ + /* + * core reset bits + */ +@@ -156,6 +170,10 @@ static const u32 bcm6368_reset_bits[] = + __GEN_RESET_BITS_TABLE(6368) + }; + ++static const u32 bcm63268_reset_bits[] = { ++ __GEN_RESET_BITS_TABLE(63268) ++}; ++ + const u32 *bcm63xx_reset_bits; + static int reset_reg; + +@@ -182,6 +200,9 @@ static int __init bcm63xx_reset_bits_ini + } else if (BCMCPU_IS_6368()) { + reset_reg = PERF_SOFTRESET_6368_REG; + bcm63xx_reset_bits = bcm6368_reset_bits; ++ } else if (BCMCPU_IS_63268()) { ++ reset_reg = PERF_SOFTRESET_63268_REG; ++ bcm63xx_reset_bits = bcm63268_reset_bits; + } + + return 0; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -21,6 +21,10 @@ + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 + #define BCM6369_CPU_ID 0x6369 ++#define BCM63168_CPU_ID 0x63168 ++#define BCM63169_CPU_ID 0x63169 ++#define BCM63268_CPU_ID 0x63268 ++#define BCM63269_CPU_ID 0x63269 + + void __init bcm63xx_cpu_init(void); + u32 bcm63xx_get_cpu_variant(void); +@@ -61,6 +65,10 @@ static inline u32 __pure __bcm63xx_get_c + #ifdef CONFIG_BCM63XX_CPU_6368 + case BCM6368_CPU_ID: + #endif ++ ++#ifdef CONFIG_BCM63XX_CPU_63268 ++ case BCM63268_CPU_ID: ++#endif + break; + default: + unreachable(); +@@ -86,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu + #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) + #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) + #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) ++#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID) + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) +@@ -109,6 +118,14 @@ static inline u32 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) + #define BCMCPU_VARIANT_IS_6369() \ + (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID) ++#define BCMCPU_VARIANT_IS_63168() \ ++ (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID) ++#define BCMCPU_VARIANT_IS_63169() \ ++ (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID) ++#define BCMCPU_VARIANT_IS_63268() \ ++ (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID) ++#define BCMCPU_VARIANT_IS_63269() \ ++ (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID) + + /* + * While registers sets are (mostly) the same across 63xx CPU, base +@@ -573,6 +590,52 @@ enum bcm63xx_regs_set { + #define BCM_6368_RNG_BASE (0xb0004180) + #define BCM_6368_MISC_BASE (0xdeadbeef) + ++/* ++ * 63268 register sets base address ++ */ ++#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef) ++#define BCM_63268_PERF_BASE (0xb0000000) ++#define BCM_63268_TIMER_BASE (0xb0000080) ++#define BCM_63268_WDT_BASE (0xb000009c) ++#define BCM_63268_UART0_BASE (0xb0000180) ++#define BCM_63268_UART1_BASE (0xb00001a0) ++#define BCM_63268_GPIO_BASE (0xb00000c0) ++#define BCM_63268_SPI_BASE (0xb0000800) ++#define BCM_63268_HSSPI_BASE (0xb0001000) ++#define BCM_63268_UDC0_BASE (0xdeadbeef) ++#define BCM_63268_USBDMA_BASE (0xb000c800) ++#define BCM_63268_OHCI0_BASE (0xb0002600) ++#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef) ++#define BCM_63268_USBH_PRIV_BASE (0xb0002700) ++#define BCM_63268_USBD_BASE (0xb0002400) ++#define BCM_63268_MPI_BASE (0xdeadbeef) ++#define BCM_63268_PCMCIA_BASE (0xdeadbeef) ++#define BCM_63268_PCIE_BASE (0xb06e0000) ++#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef) ++#define BCM_63268_DSL_BASE (0xdeadbeef) ++#define BCM_63268_UBUS_BASE (0xdeadbeef) ++#define BCM_63268_ENET0_BASE (0xdeadbeef) ++#define BCM_63268_ENET1_BASE (0xdeadbeef) ++#define BCM_63268_ENETDMA_BASE (0xb000d800) ++#define BCM_63268_ENETDMAC_BASE (0xb000da00) ++#define BCM_63268_ENETDMAS_BASE (0xb000dc00) ++#define BCM_63268_ENETSW_BASE (0xb0700000) ++#define BCM_63268_EHCI0_BASE (0xb0002500) ++#define BCM_63268_SDRAM_BASE (0xdeadbeef) ++#define BCM_63268_MEMC_BASE (0xdeadbeef) ++#define BCM_63268_DDR_BASE (0xb0003000) ++#define BCM_63268_M2M_BASE (0xdeadbeef) ++#define BCM_63268_ATM_BASE (0xdeadbeef) ++#define BCM_63268_XTM_BASE (0xb0007000) ++#define BCM_63268_XTMDMA_BASE (0xb000b800) ++#define BCM_63268_XTMDMAC_BASE (0xdeadbeef) ++#define BCM_63268_XTMDMAS_BASE (0xdeadbeef) ++#define BCM_63268_PCM_BASE (0xb000b000) ++#define BCM_63268_PCMDMA_BASE (0xb000b800) ++#define BCM_63268_PCMDMAC_BASE (0xdeadbeef) ++#define BCM_63268_PCMDMAS_BASE (0xdeadbeef) ++#define BCM_63268_RNG_BASE (0xdeadbeef) ++#define BCM_63268_MISC_BASE (0xb0001800) + + extern const unsigned long *bcm63xx_regs_base; + +@@ -1041,6 +1104,73 @@ enum bcm63xx_irq { + #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) + #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) + ++/* ++ * 63268 irqs ++ */ ++#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) ++#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32) ++ ++#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) ++#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16) ++#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5) ++#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2) ++#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23) ++#define BCM_63268_UDC0_IRQ 0 ++#define BCM_63268_ENET0_IRQ 0 ++#define BCM_63268_ENET1_IRQ 0 ++#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13) ++#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6) ++#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) ++#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11) ++#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19) ++#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4) ++#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20) ++#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5) ++#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21) ++#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6) ++#define BCM_63268_PCMCIA_IRQ 0 ++#define BCM_63268_ENET0_RXDMA_IRQ 0 ++#define BCM_63268_ENET0_TXDMA_IRQ 0 ++#define BCM_63268_ENET1_RXDMA_IRQ 0 ++#define BCM_63268_ENET1_TXDMA_IRQ 0 ++#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8) ++#define BCM_63268_ATM_IRQ 0 ++#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1) ++#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2) ++#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3) ++#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4) ++#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0) ++#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1) ++#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2) ++#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3) ++#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17) ++#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) ++ ++#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20) ++#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3) ++#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) ++#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) ++#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18) ++#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13) ++#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15) ++#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) ++#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) ++#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) ++#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) ++#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22) ++#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7) ++#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24) ++#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25) ++#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10) ++#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11) ++#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0) ++#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1) ++#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12) ++#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13) ++#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14) ++#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15) ++ + extern const int *bcm63xx_irqs; + + #define __GEN_CPU_IRQ_TABLE(__cpu) \ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -22,6 +22,8 @@ static inline unsigned long bcm63xx_gpio + return 48; + case BCM6368_CPU_ID: + return 38; ++ case BCM63268_CPU_ID: ++ return 52; + case BCM6348_CPU_ID: + default: + return 37; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -9,6 +9,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_LONG_CHIPID_SHIFT 12 ++#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) + #define REV_VARID_SHIFT 12 + #define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 +@@ -211,6 +213,52 @@ + CKCTL_6368_NAND_EN | \ + CKCTL_6368_IPSEC_EN) + ++#define CKCTL_63268_DISABLE_GLESS (1 << 0) ++#define CKCTL_63268_VDSL_QPROC_EN (1 << 1) ++#define CKCTL_63268_VDSL_AFE_EN (1 << 2) ++#define CKCTL_63268_VDSL_EN (1 << 3) ++#define CKCTL_63268_MIPS_EN (1 << 4) ++#define CKCTL_63268_WLAN_OCP_EN (1 << 5) ++#define CKCTL_63268_DECT_EN (1 << 6) ++#define CKCTL_63268_FAP0_EN (1 << 7) ++#define CKCTL_63268_FAP1_EN (1 << 8) ++#define CKCTL_63268_SAR_EN (1 << 9) ++#define CKCTL_63268_ROBOSW_EN (1 << 10) ++#define CKCTL_63268_PCM_EN (1 << 11) ++#define CKCTL_63268_USBD_EN (1 << 12) ++#define CKCTL_63268_USBH_EN (1 << 13) ++#define CKCTL_63268_IPSEC_EN (1 << 14) ++#define CKCTL_63268_SPI_EN (1 << 15) ++#define CKCTL_63268_HSSPI_EN (1 << 16) ++#define CKCTL_63268_PCIE_EN (1 << 17) ++#define CKCTL_63268_PHYMIPS_EN (1 << 18) ++#define CKCTL_63268_GMAC_EN (1 << 19) ++#define CKCTL_63268_NAND_EN (1 << 20) ++#define CKCTL_63268_TBUS_EN (1 << 27) ++#define CKCTL_63268_ROBOSW250_EN (1 << 31) ++ ++#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \ ++ CKCTL_63268_VDSL_AFE_EN | \ ++ CKCTL_63268_VDSL_EN | \ ++ CKCTL_63268_WLAN_OCP_EN | \ ++ CKCTL_63268_DECT_EN | \ ++ CKCTL_63268_FAP0_EN | \ ++ CKCTL_63268_FAP1_EN | \ ++ CKCTL_63268_SAR_EN | \ ++ CKCTL_63268_ROBOSW_EN | \ ++ CKCTL_63268_PCM_EN | \ ++ CKCTL_63268_USBD_EN | \ ++ CKCTL_63268_USBH_EN | \ ++ CKCTL_63268_IPSEC_EN | \ ++ CKCTL_63268_SPI_EN | \ ++ CKCTL_63268_HSSPI_EN | \ ++ CKCTL_63268_PCIE_EN | \ ++ CKCTL_63268_PHYMIPS_EN | \ ++ CKCTL_63268_GMAC_EN | \ ++ CKCTL_63268_NAND_EN | \ ++ CKCTL_63268_TBUS_EN | \ ++ CKCTL_63268_ROBOSW250_EN) ++ + /* System PLL Control register */ + #define PERF_SYS_PLL_CTL_REG 0x8 + #define SYS_PLL_SOFT_RESET 0x1 +@@ -224,6 +272,7 @@ + #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c) + #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10) + #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10) ++#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20) + + /* Interrupt Status register */ + #define PERF_IRQSTAT_3368_REG 0x10 +@@ -234,6 +283,7 @@ + #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c) + #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10) + #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10) ++#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20) + + /* External Interrupt Configuration register */ + #define PERF_EXTIRQ_CFG_REG_3368 0x14 +@@ -244,6 +294,7 @@ + #define PERF_EXTIRQ_CFG_REG_6358 0x14 + #define PERF_EXTIRQ_CFG_REG_6362 0x18 + #define PERF_EXTIRQ_CFG_REG_6368 0x18 ++#define PERF_EXTIRQ_CFG_REG_63268 0x18 + + #define PERF_EXTIRQ_CFG_REG2_6358 0x1c + #define PERF_EXTIRQ_CFG_REG2_6368 0x1c +@@ -274,6 +325,7 @@ + #define PERF_SOFTRESET_6358_REG 0x34 + #define PERF_SOFTRESET_6362_REG 0x10 + #define PERF_SOFTRESET_6368_REG 0x10 ++#define PERF_SOFTRESET_63268_REG 0x10 + + #define SOFTRESET_3368_SPI_MASK (1 << 0) + #define SOFTRESET_3368_ENET_MASK (1 << 2) +@@ -367,6 +419,26 @@ + #define SOFTRESET_6368_USBH_MASK (1 << 12) + #define SOFTRESET_6368_PCM_MASK (1 << 13) + ++#define SOFTRESET_63268_SPI_MASK (1 << 0) ++#define SOFTRESET_63268_IPSEC_MASK (1 << 1) ++#define SOFTRESET_63268_EPHY_MASK (1 << 2) ++#define SOFTRESET_63268_SAR_MASK (1 << 3) ++#define SOFTRESET_63268_ENETSW_MASK (1 << 4) ++#define SOFTRESET_63268_USBS_MASK (1 << 5) ++#define SOFTRESET_63268_USBH_MASK (1 << 6) ++#define SOFTRESET_63268_PCM_MASK (1 << 7) ++#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8) ++#define SOFTRESET_63268_PCIE_MASK (1 << 9) ++#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10) ++#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11) ++#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12) ++#define SOFTRESET_63268_FAP0_MASK (1 << 13) ++#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14) ++#define SOFTRESET_63268_DECT_MASK (1 << 15) ++#define SOFTRESET_63268_FAP1_MASK (1 << 16) ++#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17) ++#define SOFTRESET_63268_GPHY_MASK (1 << 18) ++ + /* MIPS PLL control register */ + #define PERF_MIPSPLLCTL_REG 0x34 + #define MIPSPLLCTL_N1_SHIFT 20 +@@ -1380,6 +1452,13 @@ + #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) + #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) + ++#define MISC_STRAPBUS_63268_REG 0x14 ++#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9) ++#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11) ++#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11) ++#define STRAPBUS_63268_FCVO_SHIFT 21 ++#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) ++ + #define MISC_STRAPBUS_6328_REG 0x240 + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) +--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h ++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h +@@ -25,6 +25,7 @@ static inline int is_bcm63xx_internal_re + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM6368_CPU_ID: ++ case BCM63268_CPU_ID: + if (offset >= 0xb0000000 && offset < 0xb1000000) + return 1; + break; +--- a/arch/mips/bcm63xx/dev-hsspi.c ++++ b/arch/mips/bcm63xx/dev-hsspi.c +@@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs + + int __init bcm63xx_hsspi_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362()) ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); +--- a/arch/mips/bcm63xx/dev-enet.c ++++ b/arch/mips/bcm63xx/dev-enet.c +@@ -176,7 +176,8 @@ static int __init register_shared(void) + else + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || ++ BCMCPU_IS_63268()) + chan_count = 32; + else if (BCMCPU_IS_6345()) + chan_count = 8; +@@ -276,7 +277,8 @@ bcm63xx_enetsw_register(const struct bcm + { + int ret; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && ++ !BCMCPU_IS_63268()) + return -ENODEV; + + ret = register_shared(); +@@ -297,6 +299,8 @@ bcm63xx_enetsw_register(const struct bcm + enetsw_pd.num_ports = ENETSW_PORTS_6328; + else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) + enetsw_pd.num_ports = ENETSW_PORTS_6368; ++ else if (BCMCPU_IS_63268()) ++ enetsw_pd.num_ports = ENETSW_PORTS_63268; + + enetsw_pd.dma_has_sram = true; + enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h +@@ -62,6 +62,7 @@ struct bcm63xx_enet_platform_data { + #define ENETSW_MAX_PORT 8 + #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */ + #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */ ++#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */ + + #define ENETSW_RGMII_PORT0 4 + diff --git a/target/linux/brcm63xx/patches-3.18/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-3.18/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch new file mode 100644 index 0000000..4e8a090 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch @@ -0,0 +1,55 @@ +From 5c290c81dbdb4433600593fe80c88eb4af86e791 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 03:22:40 +0100 +Subject: [PATCH 50/53] MIPS: BCM63XX: add pcie support for BCM63268 + +--- + arch/mips/bcm63xx/reset.c | 3 ++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 5 +++++ + arch/mips/pci/pci-bcm63xx.c | 4 ++++ + 3 files changed, 11 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -136,7 +136,8 @@ + #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK + #define BCM63268_RESET_MPI 0 + #define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ +- SOFTRESET_63268_PCIE_CORE_MASK) ++ SOFTRESET_63268_PCIE_CORE_MASK | \ ++ SOFTRESET_63268_PCIE_HARD_MASK) + #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK + + /* +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -45,6 +45,11 @@ + #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ + BCM_PCIE_MEM_SIZE_6328 - 1) + ++#define BCM_PCIE_MEM_BASE_PA_63268 0x11000000 ++#define BCM_PCIE_MEM_SIZE_63268 (15 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_63268 (BCM_PCIE_MEM_BASE_PA_63268 + \ ++ BCM_PCIE_MEM_SIZE_63268 - 1) ++ + /* + * Internal registers are accessed through KSEG3 + */ +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -337,11 +337,15 @@ static int __init bcm63xx_pci_init(void) + if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { + bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; + bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; ++ } else if (BCMCPU_IS_63268()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_63268; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_63268; + } + + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: ++ case BCM63268_CPU_ID: + return bcm63xx_register_pcie(); + case BCM3368_CPU_ID: + case BCM6348_CPU_ID: diff --git a/target/linux/brcm63xx/patches-3.18/341-MIPS-BCM63XX-add-support-for-BCM6318.patch b/target/linux/brcm63xx/patches-3.18/341-MIPS-BCM63XX-add-support-for-BCM6318.patch new file mode 100644 index 0000000..f3f4c6a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/341-MIPS-BCM63XX-add-support-for-BCM6318.patch @@ -0,0 +1,675 @@ +From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 01:24:09 +0100 +Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318 + +--- + arch/mips/bcm63xx/Kconfig | 5 + + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/clk.c | 8 +- + arch/mips/bcm63xx/cpu.c | 53 +++++++++++ + arch/mips/bcm63xx/dev-flash.c | 3 + + arch/mips/bcm63xx/dev-spi.c | 2 +- + arch/mips/bcm63xx/irq.c | 10 ++ + arch/mips/bcm63xx/prom.c | 2 +- + arch/mips/bcm63xx/reset.c | 24 +++++ + arch/mips/bcm63xx/setup.c | 5 +- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 107 ++++++++++++++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 75 ++++++++++++++- + arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + + 13 files changed, 291 insertions(+), 6 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -18,6 +18,11 @@ config BCM63XX_EHCI + select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD + select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD + ++config BCM63XX_CPU_6318 ++ bool "support 6318 CPU" ++ select SYS_HAS_CPU_BMIPS32_3300 ++ select HW_HAS_PCI ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -717,7 +717,7 @@ void __init board_prom_init(void) + /* read base address of boot chip select (0) + * 6328/6362 do not have MPI but boot from a fixed address + */ +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { + val = 0x18000000; + } else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -252,7 +252,9 @@ static void hsspi_set(struct clk *clk, i + { + u32 mask; + +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) ++ mask = CKCTL_6318_HSSPI_EN; ++ else if (BCMCPU_IS_6328()) + mask = CKCTL_6328_HSSPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_HSSPI_EN; +@@ -417,12 +419,16 @@ void clk_put(struct clk *clk) + + EXPORT_SYMBOL(clk_put); + ++#define HSSPI_PLL_HZ_6318 250000000 + #define HSSPI_PLL_HZ_6328 133333333 + #define HSSPI_PLL_HZ_6362 400000000 + + static int __init bcm63xx_clk_init(void) + { + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ clk_hsspi.rate = HSSPI_PLL_HZ_6318; ++ break; + case BCM6328_CPU_ID: + clk_hsspi.rate = HSSPI_PLL_HZ_6328; + break; +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = { + __GEN_CPU_IRQ_TABLE(3368) + }; + ++static const unsigned long bcm6318_regs_base[] = { ++ __GEN_CPU_REGS_TABLE(6318) ++}; ++ ++static const int bcm6318_irqs[] = { ++ __GEN_CPU_IRQ_TABLE(6318) ++}; ++ + static const unsigned long bcm6328_regs_base[] = { + __GEN_CPU_REGS_TABLE(6328) + }; +@@ -134,6 +142,10 @@ unsigned int bcm63xx_get_memory_size(voi + return bcm63xx_memory_size; + } + ++#define STRAP_OVERRIDE_BUS_REG 0x0 ++#define OVERRIDE_BUS_MIPS_FREQ_SHIFT 23 ++#define OVERRIDE_BUS_MIPS_FREQ_MASK (0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT) ++ + static unsigned int detect_cpu_clock(void) + { + u32 cpu_id = bcm63xx_get_cpu_id(); +@@ -142,6 +154,28 @@ static unsigned int detect_cpu_clock(voi + case BCM3368_CPU_ID: + return 300000000; + ++ case BCM6318_CPU_ID: ++ { ++ unsigned int tmp, mips_pll_fcvo; ++ ++ tmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG); ++ ++ pr_info("strap_override_bus = %08x\n", tmp); ++ ++ mips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK) ++ >> OVERRIDE_BUS_MIPS_FREQ_SHIFT; ++ ++ switch (mips_pll_fcvo) { ++ case 0: ++ return 166000000; ++ case 1: ++ return 400000000; ++ case 2: ++ return 250000000; ++ case 3: ++ return 333000000; ++ }; ++ } + case BCM6328_CPU_ID: + { + unsigned int tmp, mips_pll_fcvo; +@@ -297,6 +331,13 @@ static unsigned int detect_memory_size(v + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + ++ if (BCMCPU_IS_6318()) { ++ val = bcm_sdram_readl(SDRAM_CFG_REG); ++ val = val & SDRAM_CFG_6318_SPACE_MASK; ++ val >>= SDRAM_CFG_6318_SPACE_SHIFT; ++ return 1 << (val + 20); ++ } ++ + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) + return bcm_ddr_readl(DDR_CSEND_REG) << 24; + +@@ -343,6 +384,12 @@ void __init bcm63xx_cpu_init(void) + + switch (current_cpu_type()) { + case CPU_BMIPS3300: ++ if ((read_c0_prid() & 0xff) >= 0x33) { ++ /* BCM6318 */ ++ chipid_reg = BCM_6368_PERF_BASE; ++ break; ++ } ++ + if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT) + __cpu_name[cpu] = "Broadcom BCM6338"; + /* fall-through */ +@@ -390,6 +437,10 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_cpu_variant = bcm63xx_cpu_id; + + switch (bcm63xx_cpu_id) { ++ case BCM6318_CPU_ID: ++ bcm63xx_regs_base = bcm6318_regs_base; ++ bcm63xx_irqs = bcm6318_irqs; ++ break; + case BCM3368_CPU_ID: + bcm63xx_regs_base = bcm3368_regs_base; + bcm63xx_irqs = bcm3368_irqs; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t + u32 val; + + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ /* only support serial flash */ ++ return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6328_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); + if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) +--- a/arch/mips/bcm63xx/dev-spi.c ++++ b/arch/mips/bcm63xx/dev-spi.c +@@ -70,7 +70,7 @@ static struct platform_device bcm63xx_sp + + int __init bcm63xx_spi_register(void) + { +- if (BCMCPU_IS_6328() || BCMCPU_IS_6345()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI); +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -49,6 +49,19 @@ static void bcm63xx_init_irq(void) + ext_irqs[3] = BCM_3368_EXT_IRQ3; + ext_shift = 4; + break; ++ case BCM6318_CPU_ID: ++ periph_bases[0] += PERF_IRQMASK_6318_REG; ++ periph_irq_count = 1; ++ periph_width = 4; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_6318_EXT_IRQ0; ++ ext_irqs[1] = BCM_6318_EXT_IRQ0; ++ ext_irqs[2] = BCM_6318_EXT_IRQ0; ++ ext_irqs[3] = BCM_6318_EXT_IRQ0; ++ ext_shift = 4; ++ break; + case BCM6328_CPU_ID: + periph_bases[0] += PERF_IRQMASK_6328_REG(0); + periph_bases[1] += PERF_IRQMASK_6328_REG(1); +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -68,7 +68,7 @@ void __init prom_init(void) + + if (reg & OTP_6328_REG3_TP1_DISABLED) + bmips_smp_enabled = 0; +- } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { ++ } else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) { + bmips_smp_enabled = 0; + } + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -43,6 +43,23 @@ + #define BCM3368_RESET_PCIE 0 + #define BCM3368_RESET_PCIE_EXT 0 + ++ ++#define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK ++#define BCM6318_RESET_ENET 0 ++#define BCM6318_RESET_USBH SOFTRESET_6318_USBH_MASK ++#define BCM6318_RESET_USBD SOFTRESET_6318_USBS_MASK ++#define BCM6318_RESET_DSL 0 ++#define BCM6318_RESET_SAR SOFTRESET_6318_SAR_MASK ++#define BCM6318_RESET_EPHY SOFTRESET_6318_EPHY_MASK ++#define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK ++#define BCM6318_RESET_PCM 0 ++#define BCM6318_RESET_MPI 0 ++#define BCM6318_RESET_PCIE \ ++ (SOFTRESET_6318_PCIE_MASK | \ ++ SOFTRESET_6318_PCIE_CORE_MASK | \ ++ SOFTRESET_6318_PCIE_HARD_MASK) ++#define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK ++ + #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK + #define BCM6328_RESET_ENET 0 + #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK +@@ -147,6 +164,10 @@ static const u32 bcm3368_reset_bits[] = + __GEN_RESET_BITS_TABLE(3368) + }; + ++static const u32 bcm6318_reset_bits[] = { ++ __GEN_RESET_BITS_TABLE(6318) ++}; ++ + static const u32 bcm6328_reset_bits[] = { + __GEN_RESET_BITS_TABLE(6328) + }; +@@ -183,6 +204,9 @@ static int __init bcm63xx_reset_bits_ini + if (BCMCPU_IS_3368()) { + reset_reg = PERF_SOFTRESET_6358_REG; + bcm63xx_reset_bits = bcm3368_reset_bits; ++ } else if (BCMCPU_IS_6318()) { ++ reset_reg = PERF_SOFTRESET_6318_REG; ++ bcm63xx_reset_bits = bcm6318_reset_bits; + } else if (BCMCPU_IS_6328()) { + reset_reg = PERF_SOFTRESET_6328_REG; + bcm63xx_reset_bits = bcm6328_reset_bits; +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -72,6 +72,9 @@ void bcm63xx_machine_reboot(void) + case BCM3368_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368; + break; ++ case BCM6318_CPU_ID: ++ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6318; ++ break; + case BCM6328_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; + break; +@@ -111,7 +114,7 @@ void bcm63xx_machine_reboot(void) + bcm6348_a1_reboot(); + + printk(KERN_INFO "triggering watchdog soft-reset...\n"); +- if (BCMCPU_IS_6328()) { ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) { + bcm_wdt_writel(1, WDT_SOFTRESET_REG); + } else { + reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -10,6 +10,7 @@ + * arm mach-types) + */ + #define BCM3368_CPU_ID 0x3368 ++#define BCM6318_CPU_ID 0x6318 + #define BCM6328_CPU_ID 0x6328 + #define BCM63281_CPU_ID 0x63281 + #define BCM63283_CPU_ID 0x63283 +@@ -38,6 +39,10 @@ static inline u32 __pure __bcm63xx_get_c + case BCM3368_CPU_ID: + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6318 ++ case BCM6318_CPU_ID: ++#endif ++ + #ifdef CONFIG_BCM63XX_CPU_6328 + case BCM6328_CPU_ID: + #endif +@@ -87,6 +92,7 @@ static inline u32 __pure bcm63xx_get_cpu + } + + #define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) ++#define BCMCPU_IS_6318() (bcm63xx_get_cpu_id() == BCM6318_CPU_ID) + #define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) + #define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) + #define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) +@@ -98,6 +104,8 @@ static inline u32 __pure bcm63xx_get_cpu + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6318() \ ++ (bcm63xx_get_cpu_variant() == BCM6318_CPU_ID) + #define BCMCPU_VARIANT_IS_63281() \ + (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) + #define BCMCPU_VARIANT_IS_63283() \ +@@ -252,6 +260,56 @@ enum bcm63xx_regs_set { + #define BCM_3368_MISC_BASE (0xdeadbeef) + + /* ++ * 6318 register sets base address ++ */ ++#define BCM_6318_DSL_LMEM_BASE (0xdeadbeef) ++#define BCM_6318_PERF_BASE (0xb0000000) ++#define BCM_6318_TIMER_BASE (0xb0000040) ++#define BCM_6318_WDT_BASE (0xb0000068) ++#define BCM_6318_UART0_BASE (0xb0000100) ++#define BCM_6318_UART1_BASE (0xdeadbeef) ++#define BCM_6318_GPIO_BASE (0xb0000080) ++#define BCM_6318_SPI_BASE (0xdeadbeef) ++#define BCM_6318_HSSPI_BASE (0xb0003000) ++#define BCM_6318_UDC0_BASE (0xdeadbeef) ++#define BCM_6318_USBDMA_BASE (0xb0006800) ++#define BCM_6318_OHCI0_BASE (0xb0005100) ++#define BCM_6318_OHCI_PRIV_BASE (0xdeadbeef) ++#define BCM_6318_USBH_PRIV_BASE (0xb0005200) ++#define BCM_6318_USBD_BASE (0xb0006000) ++#define BCM_6318_MPI_BASE (0xdeadbeef) ++#define BCM_6318_PCMCIA_BASE (0xdeadbeef) ++#define BCM_6318_PCIE_BASE (0xb0010000) ++#define BCM_6318_SDRAM_REGS_BASE (0xdeadbeef) ++#define BCM_6318_DSL_BASE (0xdeadbeef) ++#define BCM_6318_UBUS_BASE (0xdeadbeef) ++#define BCM_6318_ENET0_BASE (0xdeadbeef) ++#define BCM_6318_ENET1_BASE (0xdeadbeef) ++#define BCM_6318_ENETDMA_BASE (0xb0088000) ++#define BCM_6318_ENETDMAC_BASE (0xb0088200) ++#define BCM_6318_ENETDMAS_BASE (0xb0088400) ++#define BCM_6318_ENETSW_BASE (0xb0080000) ++#define BCM_6318_EHCI0_BASE (0xb0005000) ++#define BCM_6318_SDRAM_BASE (0xb0004000) ++#define BCM_6318_MEMC_BASE (0xdeadbeef) ++#define BCM_6318_DDR_BASE (0xdeadbeef) ++#define BCM_6318_M2M_BASE (0xdeadbeef) ++#define BCM_6318_ATM_BASE (0xdeadbeef) ++#define BCM_6318_XTM_BASE (0xdeadbeef) ++#define BCM_6318_XTMDMA_BASE (0xb000c000) ++#define BCM_6318_XTMDMAC_BASE (0xdeadbeef) ++#define BCM_6318_XTMDMAS_BASE (0xdeadbeef) ++#define BCM_6318_PCM_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMA_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMAC_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMAS_BASE (0xdeadbeef) ++#define BCM_6318_RNG_BASE (0xdeadbeef) ++#define BCM_6318_MISC_BASE (0xb0000280) ++#define BCM_6318_OTP_BASE (0xdeadbeef) ++ ++#define BCM_6318_STRAP_BASE (0xb0000900) ++ ++/* + * 6328 register sets base address + */ + #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) +@@ -774,6 +832,55 @@ enum bcm63xx_irq { + #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) + #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) + ++/* ++ * 6318 irqs ++ */ ++#define BCM_6318_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) ++#define BCM_6318_VERY_HIGH_IRQ_BASE (BCM_6318_HIGH_IRQ_BASE + 32) ++ ++#define BCM_6318_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) ++#define BCM_6318_SPI_IRQ 0 ++#define BCM_6318_UART0_IRQ (IRQ_INTERNAL_BASE + 28) ++#define BCM_6318_UART1_IRQ 0 ++#define BCM_6318_DSL_IRQ (IRQ_INTERNAL_BASE + 21) ++#define BCM_6318_UDC0_IRQ 0 ++#define BCM_6318_ENET0_IRQ 0 ++#define BCM_6318_ENET1_IRQ 0 ++#define BCM_6318_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) ++#define BCM_6318_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) ++#define BCM_6318_OHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 9) ++#define BCM_6318_EHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 10) ++#define BCM_6318_USBD_IRQ (IRQ_INTERNAL_BASE + 4) ++#define BCM_6318_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) ++#define BCM_6318_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) ++#define BCM_6318_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) ++#define BCM_6318_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) ++#define BCM_6318_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_6318_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) ++#define BCM_6318_PCMCIA_IRQ 0 ++#define BCM_6318_ENET0_RXDMA_IRQ 0 ++#define BCM_6318_ENET0_TXDMA_IRQ 0 ++#define BCM_6318_ENET1_RXDMA_IRQ 0 ++#define BCM_6318_ENET1_TXDMA_IRQ 0 ++#define BCM_6318_PCI_IRQ (IRQ_INTERNAL_BASE + 23) ++#define BCM_6318_ATM_IRQ 0 ++#define BCM_6318_ENETSW_RXDMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 0) ++#define BCM_6318_ENETSW_RXDMA1_IRQ (BCM_6318_HIGH_IRQ_BASE + 1) ++#define BCM_6318_ENETSW_RXDMA2_IRQ (BCM_6318_HIGH_IRQ_BASE + 2) ++#define BCM_6318_ENETSW_RXDMA3_IRQ (BCM_6318_HIGH_IRQ_BASE + 3) ++#define BCM_6318_ENETSW_TXDMA0_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 10) ++#define BCM_6318_ENETSW_TXDMA1_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 11) ++#define BCM_6318_ENETSW_TXDMA2_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 12) ++#define BCM_6318_ENETSW_TXDMA3_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 13) ++#define BCM_6318_XTM_IRQ (BCM_6318_HIGH_IRQ_BASE + 31) ++#define BCM_6318_XTM_DMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 11) ++ ++#define BCM_6318_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) ++#define BCM_6318_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) ++#define BCM_6318_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) ++#define BCM_6318_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) ++#define BCM_6318_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) ++#define BCM_6318_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) + + /* + * 6328 irqs +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -52,6 +52,39 @@ + CKCTL_3368_EMUSB_EN | \ + CKCTL_3368_USBU_EN) + ++#define CKCTL_6318_ADSL_ASB_EN (1 << 0) ++#define CKCTL_6318_USB_ASB_EN (1 << 1) ++#define CKCTL_6318_MIPS_ASB_EN (1 << 2) ++#define CKCTL_6318_PCIE_ASB_EN (1 << 3) ++#define CKCTL_6318_PHYMIPS_ASB_EN (1 << 4) ++#define CKCTL_6318_ROBOSW_ASB_EN (1 << 5) ++#define CKCTL_6318_SAR_ASB_EN (1 << 6) ++#define CKCTL_6318_SDR_ASB_EN (1 << 7) ++#define CKCTL_6318_SWREG_ASB_EN (1 << 8) ++#define CKCTL_6318_PERIPH_ASB_EN (1 << 9) ++#define CKCTL_6318_CPUBUS160_EN (1 << 10) ++#define CKCTL_6318_ADSL_EN (1 << 11) ++#define CKCTL_6318_SAR125_EN (1 << 12) ++#define CKCTL_6318_MIPS_EN (1 << 13) ++#define CKCTL_6318_PCIE_EN (1 << 14) ++#define CKCTL_6318_ROBOSW250_EN (1 << 16) ++#define CKCTL_6318_ROBOSW025_EN (1 << 17) ++#define CKCTL_6318_SDR_EN (1 << 19) ++#define CKCTL_6318_USB_EN (1 << 20) /* both device and host */ ++#define CKCTL_6318_HSSPI_EN (1 << 25) ++#define CKCTL_6318_PCIE25_EN (1 << 27) ++#define CKCTL_6318_PHYMIPS_EN (1 << 28) ++#define CKCTL_6318_ADSL_AFE_EN (1 << 29) ++#define CKCTL_6318_ADSL_QPROC_EN (1 << 30) ++ ++#define CKCTL_6318_ALL_SAFE_EN (CKCTL_6318_PHYMIPS_EN | \ ++ CKCTL_6318_ADSL_QPROC_EN | \ ++ CKCTL_6318_ADSL_AFE_EN | \ ++ CKCTL_6318_ADSL_EN | \ ++ CKCTL_6318_SAR_EN | \ ++ CKCTL_6318_USB_EN | \ ++ CKCTL_6318_PCIE_EN) ++ + #define CKCTL_6328_PHYMIPS_EN (1 << 0) + #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) + #define CKCTL_6328_ADSL_AFE_EN (1 << 2) +@@ -259,12 +292,27 @@ + CKCTL_63268_TBUS_EN | \ + CKCTL_63268_ROBOSW250_EN) + ++/* UBUS Clock Control register */ ++#define PERF_UB_CKCTL_REG 0x10 ++ ++#define UB_CKCTL_6318_ADSL_EN (1 << 0) ++#define UB_CKCTL_6318_ARB_EN (1 << 1) ++#define UB_CKCTL_6318_MIPS_EN (1 << 2) ++#define UB_CKCTL_6318_PCIE_EN (1 << 3) ++#define UB_CKCTL_6318_PERIPH_EN (1 << 4) ++#define UB_CKCTL_6318_PHYMIPS_EN (1 << 5) ++#define UB_CKCTL_6318_ROBOSW_EN (1 << 6) ++#define UB_CKCTL_6318_SAR_EN (1 << 7) ++#define UB_CKCTL_6318_SDR_EN (1 << 8) ++#define UB_CKCTL_6318_USB_EN (1 << 9) ++ + /* System PLL Control register */ + #define PERF_SYS_PLL_CTL_REG 0x8 + #define SYS_PLL_SOFT_RESET 0x1 + + /* Interrupt Mask register */ + #define PERF_IRQMASK_3368_REG 0xc ++#define PERF_IRQMASK_6318_REG 0x20 + #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10) + #define PERF_IRQMASK_6338_REG 0xc + #define PERF_IRQMASK_6345_REG 0xc +@@ -276,6 +324,7 @@ + + /* Interrupt Status register */ + #define PERF_IRQSTAT_3368_REG 0x10 ++#define PERF_IRQSTAT_6318_REG 0x30 + #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10) + #define PERF_IRQSTAT_6338_REG 0x10 + #define PERF_IRQSTAT_6345_REG 0x10 +@@ -287,6 +336,7 @@ + + /* External Interrupt Configuration register */ + #define PERF_EXTIRQ_CFG_REG_3368 0x14 ++#define PERF_EXTIRQ_CFG_REG_6318 0x18 + #define PERF_EXTIRQ_CFG_REG_6328 0x18 + #define PERF_EXTIRQ_CFG_REG_6338 0x14 + #define PERF_EXTIRQ_CFG_REG_6345 0x14 +@@ -321,6 +371,7 @@ + + /* Soft Reset register */ + #define PERF_SOFTRESET_REG 0x28 ++#define PERF_SOFTRESET_6318_REG 0x10 + #define PERF_SOFTRESET_6328_REG 0x10 + #define PERF_SOFTRESET_6358_REG 0x34 + #define PERF_SOFTRESET_6362_REG 0x10 +@@ -334,6 +385,18 @@ + #define SOFTRESET_3368_USBS_MASK (1 << 11) + #define SOFTRESET_3368_PCM_MASK (1 << 13) + ++#define SOFTRESET_6318_SPI_MASK (1 << 0) ++#define SOFTRESET_6318_EPHY_MASK (1 << 1) ++#define SOFTRESET_6318_SAR_MASK (1 << 2) ++#define SOFTRESET_6318_ENETSW_MASK (1 << 3) ++#define SOFTRESET_6318_USBS_MASK (1 << 4) ++#define SOFTRESET_6318_USBH_MASK (1 << 5) ++#define SOFTRESET_6318_PCIE_CORE_MASK (1 << 6) ++#define SOFTRESET_6318_PCIE_MASK (1 << 7) ++#define SOFTRESET_6318_PCIE_EXT_MASK (1 << 8) ++#define SOFTRESET_6318_PCIE_HARD_MASK (1 << 9) ++#define SOFTRESET_6318_ADSL_MASK (1 << 10) ++ + #define SOFTRESET_6328_SPI_MASK (1 << 0) + #define SOFTRESET_6328_EPHY_MASK (1 << 1) + #define SOFTRESET_6328_SAR_MASK (1 << 2) +@@ -505,8 +568,17 @@ + #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) + #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) + ++#define TIMER_IRQMASK_6318_REG 0x0 ++#define TIMER_IRQSTAT_6318_REG 0x4 ++#define IRQSTATMASK_TIMER0 (1 << 0) ++#define IRQSTATMASK_TIMER1 (1 << 1) ++#define IRQSTATMASK_TIMER2 (1 << 2) ++#define IRQSTATMASK_TIMER3 (1 << 3) ++#define IRQSTATMASK_WDT (1 << 4) ++ + /* Timer control register */ + #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) ++#define TIMER_CTRx_6318_REG(x) (0x8 + (x * 4)) + #define TIMER_CTL0_REG 0x4 + #define TIMER_CTL1_REG 0x8 + #define TIMER_CTL2_REG 0xC +@@ -1253,6 +1325,8 @@ + #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) + #define SDRAM_CFG_BANK_SHIFT 13 + #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) ++#define SDRAM_CFG_6318_SPACE_SHIFT 4 ++#define SDRAM_CFG_6318_SPACE_MASK (0xf << SDRAM_CFG_6318_SPACE_SHIFT) + + #define SDRAM_MBASE_REG 0xc + +--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h ++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h +@@ -22,6 +22,7 @@ static inline int is_bcm63xx_internal_re + if (offset >= 0xfff00000) + return 1; + break; ++ case BCM6318_CPU_ID: + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM6368_CPU_ID: +--- a/arch/mips/bcm63xx/dev-hsspi.c ++++ b/arch/mips/bcm63xx/dev-hsspi.c +@@ -35,7 +35,8 @@ static struct platform_device bcm63xx_hs + + int __init bcm63xx_hsspi_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() && ++ !BCMCPU_IS_63268()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); +--- a/arch/mips/bcm63xx/dev-usb-usbd.c ++++ b/arch/mips/bcm63xx/dev-usb-usbd.c +@@ -41,7 +41,7 @@ int __init bcm63xx_usbd_register(const s + IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 }; + int i; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6368()) + return 0; + + usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD); +--- a/arch/mips/bcm63xx/dev-enet.c ++++ b/arch/mips/bcm63xx/dev-enet.c +@@ -176,8 +176,8 @@ static int __init register_shared(void) + else + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || +- BCMCPU_IS_63268()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_6368() || BCMCPU_IS_63268()) + chan_count = 32; + else if (BCMCPU_IS_6345()) + chan_count = 8; +@@ -277,8 +277,8 @@ bcm63xx_enetsw_register(const struct bcm + { + int ret; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && +- !BCMCPU_IS_63268()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() && ++ !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return -ENODEV; + + ret = register_shared(); +@@ -295,7 +295,7 @@ bcm63xx_enetsw_register(const struct bcm + + memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd)); + +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) + enetsw_pd.num_ports = ENETSW_PORTS_6328; + else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) + enetsw_pd.num_ports = ENETSW_PORTS_6368; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void); + static inline unsigned long bcm63xx_gpio_count(void) + { + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ return 50; + case BCM6328_CPU_ID: + return 32; + case BCM3368_CPU_ID: +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -81,7 +81,8 @@ static struct platform_device bcm63xx_eh + + int __init bcm63xx_ehci_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && ++ !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) + return 0; + + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); diff --git a/target/linux/brcm63xx/patches-3.18/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch b/target/linux/brcm63xx/patches-3.18/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch new file mode 100644 index 0000000..71044f8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch @@ -0,0 +1,156 @@ +From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 14:17:50 +0100 +Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals + +--- + arch/mips/bcm63xx/reset.c | 39 ++++++++++++++-------- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 2 ++ + arch/mips/pci/pci-bcm63xx.c | 7 ++++ + 3 files changed, 34 insertions(+), 14 deletions(-) + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -28,7 +28,9 @@ + [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \ + [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \ + [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ +- [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, ++ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, \ ++ [BCM63XX_RESET_PCIE_CORE] = BCM## __cpu ##_RESET_PCIE_CORE, \ ++ [BCM63XX_RESET_PCIE_HARD] = BCM## __cpu ##_RESET_PCIE_HARD, + + #define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK + #define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK +@@ -42,6 +44,8 @@ + #define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK + #define BCM3368_RESET_PCIE 0 + #define BCM3368_RESET_PCIE_EXT 0 ++#define BCM3368_RESET_PCIE_CORE 0 ++#define BCM3368_RESET_PCIE_HARD 0 + + + #define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK +@@ -54,11 +58,10 @@ + #define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK + #define BCM6318_RESET_PCM 0 + #define BCM6318_RESET_MPI 0 +-#define BCM6318_RESET_PCIE \ +- (SOFTRESET_6318_PCIE_MASK | \ +- SOFTRESET_6318_PCIE_CORE_MASK | \ +- SOFTRESET_6318_PCIE_HARD_MASK) ++#define BCM6318_RESET_PCIE SOFTRESET_6318_PCIE_MASK + #define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK ++#define BCM6318_RESET_PCIE_CORE SOFTRESET_6318_PCIE_CORE_MASK ++#define BCM6318_RESET_PCIE_HARD SOFTRESET_6318_PCIE_HARD_MASK + + #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK + #define BCM6328_RESET_ENET 0 +@@ -70,11 +73,10 @@ + #define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK + #define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK + #define BCM6328_RESET_MPI 0 +-#define BCM6328_RESET_PCIE \ +- (SOFTRESET_6328_PCIE_MASK | \ +- SOFTRESET_6328_PCIE_CORE_MASK | \ +- SOFTRESET_6328_PCIE_HARD_MASK) ++#define BCM6328_RESET_PCIE SOFTRESET_6328_PCIE_MASK + #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK ++#define BCM6328_RESET_PCIE_CORE SOFTRESET_6328_PCIE_CORE_MASK ++#define BCM6328_RESET_PCIE_HARD SOFTRESET_6328_PCIE_HARD_MASK + + #define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK + #define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK +@@ -88,6 +90,8 @@ + #define BCM6338_RESET_MPI 0 + #define BCM6338_RESET_PCIE 0 + #define BCM6338_RESET_PCIE_EXT 0 ++#define BCM6338_RESET_PCIE_CORE 0 ++#define BCM6338_RESET_PCIE_HARD 0 + + #define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK + #define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK +@@ -101,6 +105,8 @@ + #define BCM6348_RESET_MPI 0 + #define BCM6348_RESET_PCIE 0 + #define BCM6348_RESET_PCIE_EXT 0 ++#define BCM6348_RESET_PCIE_CORE 0 ++#define BCM6348_RESET_PCIE_HARD 0 + + #define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK + #define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK +@@ -114,6 +120,8 @@ + #define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK + #define BCM6358_RESET_PCIE 0 + #define BCM6358_RESET_PCIE_EXT 0 ++#define BCM6358_RESET_PCIE_CORE 0 ++#define BCM6358_RESET_PCIE_HARD 0 + + #define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK + #define BCM6362_RESET_ENET 0 +@@ -125,9 +133,10 @@ + #define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK + #define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK + #define BCM6362_RESET_MPI 0 +-#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \ +- SOFTRESET_6362_PCIE_CORE_MASK) ++#define BCM6362_RESET_PCIE SOFTRESET_6362_PCIE_MASK + #define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK ++#define BCM6362_RESET_PCIE_CORE SOFTRESET_6362_PCIE_CORE_MASK ++#define BCM6362_RESET_PCIE_HARD 0 + + #define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK + #define BCM6368_RESET_ENET 0 +@@ -141,6 +150,8 @@ + #define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK + #define BCM6368_RESET_PCIE 0 + #define BCM6368_RESET_PCIE_EXT 0 ++#define BCM6368_RESET_PCIE_CORE 0 ++#define BCM6368_RESET_PCIE_HARD 0 + + #define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK + #define BCM63268_RESET_ENET 0 +@@ -152,10 +163,10 @@ + #define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK + #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK + #define BCM63268_RESET_MPI 0 +-#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ +- SOFTRESET_63268_PCIE_CORE_MASK | \ +- SOFTRESET_63268_PCIE_HARD_MASK) ++#define BCM63268_RESET_PCIE SOFTRESET_63268_PCIE_MASK + #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK ++#define BCM63268_RESET_PCIE_CORE SOFTRESET_63268_PCIE_CORE_MASK ++#define BCM63268_RESET_PCIE_HARD SOFTRESET_63268_PCIE_HARD_MASK + + /* + * core reset bits +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h +@@ -14,6 +14,8 @@ enum bcm63xx_core_reset { + BCM63XX_RESET_MPI, + BCM63XX_RESET_PCIE, + BCM63XX_RESET_PCIE_EXT, ++ BCM63XX_RESET_PCIE_CORE, ++ BCM63XX_RESET_PCIE_HARD, + }; + + void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset); +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo + + /* reset the PCIe core */ + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1); + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); ++ if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) { ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0); ++ } + mdelay(10); + ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0); + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); + mdelay(10); + diff --git a/target/linux/brcm63xx/patches-3.18/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch b/target/linux/brcm63xx/patches-3.18/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch new file mode 100644 index 0000000..3ac08b4 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch @@ -0,0 +1,342 @@ +From 11a8ab8dac4ef5d0d70199843043927edce1d4db Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 15 Dec 2013 20:47:34 +0100 +Subject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318 + +--- + arch/mips/bcm63xx/clk.c | 25 ++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 ++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 60 +++++++++++- + arch/mips/pci/ops-bcm63xx.c | 16 +++- + arch/mips/pci/pci-bcm63xx.c | 106 ++++++++++++++++++---- + 5 files changed, 184 insertions(+), 29 deletions(-) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -50,6 +50,18 @@ static void bcm_hwclock_set(u32 mask, in + bcm_perf_writel(reg, PERF_CKCTL_REG); + } + ++static void bcm_ub_hwclock_set(u32 mask, int enable) ++{ ++ u32 reg; ++ ++ reg = bcm_perf_readl(PERF_UB_CKCTL_REG); ++ if (enable) ++ reg |= mask; ++ else ++ reg &= ~mask; ++ bcm_perf_writel(reg, PERF_UB_CKCTL_REG); ++} ++ + /* + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 + */ +@@ -317,12 +329,17 @@ static struct clk clk_ipsec = { + + static void pcie_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_PCIE_EN, enable); ++ bcm_hwclock_set(CKCTL_6318_PCIE25_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_PCIE_EN, enable); ++ } else if (BCMCPU_IS_6328()) { + bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); +- else if (BCMCPU_IS_6362()) ++ } else if (BCMCPU_IS_6362()) { + bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); +- else if (BCMCPU_IS_63268()) ++ } else if (BCMCPU_IS_63268()) { + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable); ++ } + } + + static struct clk clk_pcie = { +@@ -405,7 +422,7 @@ struct clk *clk_get(struct device *dev, + if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) && + !strcmp(id, "ipsec")) + return &clk_ipsec; +- if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && ++ if ((BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && + !strcmp(id, "pcie")) + return &clk_pcie; + return ERR_PTR(-ENOENT); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -40,6 +40,12 @@ + #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ + BCM_CB_MEM_SIZE - 1) + ++#define BCM_PCIE_MEM_BASE_PA_6318 0x10200000 ++#define BCM_PCIE_MEM_SIZE_6318 (1 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_6318 (BCM_PCIE_MEM_BASE_PA_6318 + \ ++ BCM_PCIE_MEM_SIZE_6318 - 1) ++ ++ + #define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000 + #define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024) + #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -1543,6 +1543,17 @@ + * _REG relative to RSET_PCIE + *************************************************************************/ + ++#define PCIE_SPECIFIC_REG 0x188 ++#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT 0 ++#define SPECIFIC_ENDIAN_MODE_BAR1_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT 2 ++#define SPECIFIC_ENDIAN_MODE_BAR2_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT 4 ++#define SPECIFIC_ENDIAN_MODE_BAR3_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN 0 ++#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1 ++#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN 2 ++ + #define PCIE_CONFIG2_REG 0x408 + #define CONFIG2_BAR1_SIZE_EN 1 + #define CONFIG2_BAR1_SIZE_MASK 0xf +@@ -1588,7 +1599,54 @@ + #define PCIE_RC_INT_C (1 << 2) + #define PCIE_RC_INT_D (1 << 3) + +-#define PCIE_DEVICE_OFFSET 0x8000 ++#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG 0x400c ++#define C2P_MEM_WIN_ENDIAN_MODE_MASK 0x3 ++#define C2P_MEM_WIN_ENDIAN_NO_SWAP 0 ++#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1 ++#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2 ++#define C2P_MEM_WIN_BASE_ADDR_SHIFT 20 ++#define C2P_MEM_WIN_BASE_ADDR_MASK (0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT) ++ ++#define PCIE_RC_BAR1_CONFIG_LO_REG 0x402c ++#define RC_BAR_CFG_LO_SIZE_256MB 0xd ++#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT 20 ++#define RC_BAR_CFG_LO_MATCH_ADDR_MASK (0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT) ++ ++#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070 ++#define C2P_BASELIMIT_LIMIT_SHIFT 20 ++#define C2P_BASELIMIT_LIMIT_MASK (0xfff << C2P_BASELIMIT_LIMIT_SHIFT) ++#define C2P_BASELIMIT_BASE_SHIFT 4 ++#define C2P_BASELIMIT_BASE_MASK (0xfff << C2P_BASELIMIT_BASE_SHIFT) ++ ++#define PCIE_UBUS_BAR1_CFG_REMAP_REG 0x4088 ++#define BAR1_CFG_REMAP_OFFSET_SHIFT 20 ++#define BAR1_CFG_REMAP_OFFSET_MASK (0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT) ++#define BAR1_CFG_REMAP_ACCESS_EN 1 ++ ++#define PCIE_HARD_DEBUG_REG 0x4204 ++#define HARD_DEBUG_SERDES_IDDQ (1 << 23) ++ ++#define PCIE_CPU_INT1_MASK_CLEAR_REG 0x830c ++#define CPU_INT_PCIE_ERR_ATTN_CPU (1 << 0) ++#define CPU_INT_PCIE_INTA (1 << 1) ++#define CPU_INT_PCIE_INTB (1 << 2) ++#define CPU_INT_PCIE_INTC (1 << 3) ++#define CPU_INT_PCIE_INTD (1 << 4) ++#define CPU_INT_PCIE_INTR (1 << 5) ++#define CPU_INT_PCIE_NMI (1 << 6) ++#define CPU_INT_PCIE_UBUS (1 << 7) ++#define CPU_INT_IPI (1 << 8) ++ ++#define PCIE_EXT_CFG_INDEX_REG 0x8400 ++#define EXT_CFG_FUNC_NUM_SHIFT 12 ++#define EXT_CFG_FUNC_NUM_MASK (0x7 << EXT_CFG_FUNC_NUM_SHIFT) ++#define EXT_CFG_DEV_NUM_SHIFT 15 ++#define EXT_CFG_DEV_NUM_MASK (0xf << EXT_CFG_DEV_NUM_SHIFT) ++#define EXT_CFG_BUS_NUM_SHIFT 20 ++#define EXT_CFG_BUS_NUM_MASK (0xff << EXT_CFG_BUS_NUM_SHIFT) ++ ++#define PCIE_DEVICE_OFFSET_6318 0x9000 ++#define PCIE_DEVICE_OFFSET_6328 0x8000 + + /************************************************************************* + * _REG relative to RSET_OTP +--- a/arch/mips/pci/ops-bcm63xx.c ++++ b/arch/mips/pci/ops-bcm63xx.c +@@ -488,8 +488,12 @@ static int bcm63xx_pcie_read(struct pci_ + if (!bcm63xx_pcie_can_access(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (bus->number == PCIE_BUS_DEVICE) +- reg += PCIE_DEVICE_OFFSET; ++ if (bus->number == PCIE_BUS_DEVICE) { ++ if (BCMCPU_IS_6318()) ++ reg += PCIE_DEVICE_OFFSET_6318; ++ else ++ reg += PCIE_DEVICE_OFFSET_6328; ++ } + + data = bcm_pcie_readl(reg); + +@@ -508,8 +512,12 @@ static int bcm63xx_pcie_write(struct pci + if (!bcm63xx_pcie_can_access(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (bus->number == PCIE_BUS_DEVICE) +- reg += PCIE_DEVICE_OFFSET; ++ if (bus->number == PCIE_BUS_DEVICE) { ++ if (BCMCPU_IS_6318()) ++ reg += PCIE_DEVICE_OFFSET_6318; ++ else ++ reg += PCIE_DEVICE_OFFSET_6328; ++ } + + + data = bcm_pcie_readl(reg); +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -118,7 +118,7 @@ static void bcm63xx_int_cfg_writel(u32 v + + void __iomem *pci_iospace_start; + +-static void __init bcm63xx_reset_pcie(void) ++static void __init bcm63xx_reset_pcie_gen1(void) + { + u32 val; + u32 reg; +@@ -152,20 +152,32 @@ static void __init bcm63xx_reset_pcie(vo + mdelay(200); + } + +-static struct clk *pcie_clk; +- +-static int __init bcm63xx_register_pcie(void) ++static void __init bcm63xx_reset_pcie_gen2(void) + { + u32 val; + +- /* enable clock */ +- pcie_clk = clk_get(NULL, "pcie"); +- if (IS_ERR_OR_NULL(pcie_clk)) +- return -ENODEV; ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0); + +- clk_prepare_enable(pcie_clk); ++ /* reset the PCIe core */ ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); ++ mdelay(10); ++ val = bcm_pcie_readl(PCIE_HARD_DEBUG_REG); ++ val &= ~HARD_DEBUG_SERDES_IDDQ; ++ bcm_pcie_writel(val, PCIE_HARD_DEBUG_REG); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0); ++ mdelay(200); ++} + +- bcm63xx_reset_pcie(); ++static void __init bcm63xx_init_pcie_gen1(void) ++{ ++ u32 val; + + /* configure the PCIe bridge */ + val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); +@@ -190,6 +202,65 @@ static int __init bcm63xx_register_pcie( + val |= OPT2_CFG_TYPE1_BD_SEL; + bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); + ++ /* set bar0 to little endian */ ++ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; ++ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; ++ val |= BASEMASK_REMAP_EN; ++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); ++ ++ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; ++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); ++} ++ ++static void __init bcm63xx_init_pcie_gen2(void) ++{ ++ u32 val; ++ ++ bcm_pcie_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB | ++ CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD, ++ PCIE_CPU_INT1_MASK_CLEAR_REG); ++ ++ val = bcm_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK; ++ val |= (bcm_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT) << ++ C2P_BASELIMIT_BASE_SHIFT; ++ ++ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG); ++ ++ /* set bar0 to little endian */ ++ val = bcm_pcie_readl(PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG); ++ val |= bcm_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK; ++ val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP; ++ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG); ++ ++ bcm_pcie_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN, PCIE_SPECIFIC_REG); ++ bcm_pcie_writel(RC_BAR_CFG_LO_SIZE_256MB, PCIE_RC_BAR1_CONFIG_LO_REG); ++ bcm_pcie_writel(BAR1_CFG_REMAP_ACCESS_EN, PCIE_UBUS_BAR1_CFG_REMAP_REG); ++ ++ bcm_pcie_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT, ++ PCIE_EXT_CFG_INDEX_REG); ++} ++ ++static struct clk *pcie_clk; ++ ++static int __init bcm63xx_register_pcie(void) ++{ ++ u32 val; ++ ++ /* enable clock */ ++ pcie_clk = clk_get(NULL, "pcie"); ++ if (IS_ERR_OR_NULL(pcie_clk)) ++ return -ENODEV; ++ ++ clk_prepare_enable(pcie_clk); ++ ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { ++ bcm63xx_reset_pcie_gen1(); ++ bcm63xx_init_pcie_gen1(); ++ } else { ++ bcm63xx_reset_pcie_gen2(); ++ bcm63xx_init_pcie_gen2(); ++ } ++ + /* setup class code as bridge */ + val = bcm_pcie_readl(PCIE_IDVAL3_REG); + val &= ~IDVAL3_CLASS_CODE_MASK; +@@ -201,15 +272,6 @@ static int __init bcm63xx_register_pcie( + val &= ~CONFIG2_BAR1_SIZE_MASK; + bcm_pcie_writel(val, PCIE_CONFIG2_REG); + +- /* set bar0 to little endian */ +- val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; +- val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; +- val |= BASEMASK_REMAP_EN; +- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); +- +- val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; +- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); +- + register_pci_controller(&bcm63xx_pcie_controller); + + return 0; +@@ -341,7 +403,10 @@ static int __init bcm63xx_pci_init(void) + if (!bcm63xx_pci_enabled) + return -ENODEV; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ if (BCMCPU_IS_6318()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6318; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6318; ++ } if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { + bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; + bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; + } else if (BCMCPU_IS_63268()) { +@@ -350,6 +415,7 @@ static int __init bcm63xx_pci_init(void) + } + + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM63268_CPU_ID: diff --git a/target/linux/brcm63xx/patches-3.18/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch b/target/linux/brcm63xx/patches-3.18/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch new file mode 100644 index 0000000..f5b0e77 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch @@ -0,0 +1,74 @@ +From 9a97177b907330971aa7bf41855fafc2602e1c18 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 22 Dec 2013 12:26:57 +0100 +Subject: [PATCH 51/56] MIPS: BCM63XX: detect flash type early and store the + result + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 10 +++++++--- + arch/mips/bcm63xx/prom.c | 4 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++ + 3 files changed, 13 insertions(+), 3 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -22,6 +22,8 @@ + #include + #include + ++static int flash_type; ++ + static struct mtd_partition mtd_partitions[] = { + { + .name = "cfe", +@@ -108,13 +110,15 @@ static int __init bcm63xx_detect_flash_t + } + } + ++void __init bcm63xx_flash_detect(void) ++{ ++ flash_type = bcm63xx_detect_flash_type(); ++} ++ + int __init bcm63xx_flash_register(void) + { +- int flash_type; + u32 val; + +- flash_type = bcm63xx_detect_flash_type(); +- + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: + /* read base address of boot chip select (0) */ +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + void __init prom_init(void) + { +@@ -52,6 +53,9 @@ void __init prom_init(void) + reg &= ~mask; + bcm_perf_writel(reg, PERF_CKCTL_REG); + ++ /* detect and setup flash access */ ++ bcm63xx_flash_detect(); ++ + /* do low level board init */ + board_prom_init(); + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -7,6 +7,8 @@ enum { + BCM63XX_FLASH_TYPE_NAND, + }; + ++void bcm63xx_flash_detect(void); ++ + int __init bcm63xx_flash_register(void); + + #endif /* __BCM63XX_FLASH_H */ diff --git a/target/linux/brcm63xx/patches-3.18/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch b/target/linux/brcm63xx/patches-3.18/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch new file mode 100644 index 0000000..c8bef13 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch @@ -0,0 +1,84 @@ +From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 22 Dec 2013 13:25:25 +0100 +Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot + +Some bootloaders leave the flash access in an invalid state with dual +read enabled; fix it by disabling it and falling back to simple fast +reads. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 51 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 51 insertions(+) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -110,9 +111,59 @@ static int __init bcm63xx_detect_flash_t + } + } + ++#define HSSPI_FLASH_CTRL_REG 0x14 ++#define FLASH_CTRL_READ_OPCODE_MASK 0xff ++#define FLASH_CTRL_ADDR_BYTES_MASK (0x3 << 8) ++#define FLASH_CTRL_ADDR_BYTES_2 (0 << 8) ++#define FLASH_CTRL_ADDR_BYTES_3 (1 << 8) ++#define FLASH_CTRL_ADDR_BYTES_4 (2 << 8) ++#define FLASH_CTRL_DUMMY_BYTES_SHIFT 10 ++#define FLASH_CTRL_DUMMY_BYTES_MASK (0x3 << FLASH_CTRL_DUMMY_BYTES_SHIFT) ++#define FLASH_CTRL_MB_EN (1 << 23) ++ + void __init bcm63xx_flash_detect(void) + { + flash_type = bcm63xx_detect_flash_type(); ++ ++ /* ensure flash mapping has sane values */ ++ if (flash_type == BCM63XX_FLASH_TYPE_SERIAL && ++ (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_63268())) { ++ u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG); ++ ++ if (val & FLASH_CTRL_MB_EN) { ++ /* cfe might configure non working dual-io mode */ ++ val &= ~FLASH_CTRL_MB_EN; ++ val &= ~FLASH_CTRL_READ_OPCODE_MASK; ++ val &= ~FLASH_CTRL_DUMMY_BYTES_MASK; ++ val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT; ++ ++ switch (val & FLASH_CTRL_ADDR_BYTES_MASK) { ++ case FLASH_CTRL_ADDR_BYTES_3: ++ val |= SPINOR_OP_READ_FAST; ++ break; ++ case FLASH_CTRL_ADDR_BYTES_4: ++ val |= SPINOR_OP_READ4_FAST; ++ break; ++ case FLASH_CTRL_ADDR_BYTES_2: ++ default: ++ pr_warn("unsupported address byte mode (%x), not fixing up\n", ++ val & FLASH_CTRL_ADDR_BYTES_MASK); ++ return; ++ } ++ } else { ++ /* ensure dummy bytes is set to 1 for _FAST reads */ ++ u8 cmd = val & FLASH_CTRL_READ_OPCODE_MASK; ++ ++ if (cmd != SPINOR_OP_READ_FAST && cmd != SPINOR_OP_READ4_FAST) ++ return; ++ ++ val &= ~FLASH_CTRL_DUMMY_BYTES_MASK; ++ val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT; ++ } ++ ++ bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG); ++ } + } + + int __init bcm63xx_flash_register(void) diff --git a/target/linux/brcm63xx/patches-3.18/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch b/target/linux/brcm63xx/patches-3.18/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch new file mode 100644 index 0000000..384702c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -136,7 +136,11 @@ static struct clk clk_ephy = { + */ + static void enetsw_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_ROBOSW250_EN | ++ CKCTL_6318_ROBOSW025_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_ROBOSW_EN, enable); ++ } else if (BCMCPU_IS_6328()) + bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable); + else if (BCMCPU_IS_6362()) + bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable); +@@ -183,18 +187,22 @@ static struct clk clk_pcm = { + */ + static void usbh_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_USB_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_USB_EN, enable); ++ } else if (BCMCPU_IS_6328()) { + bcm_hwclock_set(CKCTL_6328_USBH_EN, enable); +- else if (BCMCPU_IS_6348()) ++ } else if (BCMCPU_IS_6348()) { + bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); +- else if (BCMCPU_IS_6362()) ++ } else if (BCMCPU_IS_6362()) { + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); +- else if (BCMCPU_IS_6368()) ++ } else if (BCMCPU_IS_6368()) { + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); +- else if (BCMCPU_IS_63268()) ++ } else if (BCMCPU_IS_63268()) { + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); +- else ++ } else { + return; ++ } + + if (enable) + msleep(100); +@@ -405,9 +413,9 @@ struct clk *clk_get(struct device *dev, + return &clk_enetsw; + if (!strcmp(id, "ephy")) + return &clk_ephy; +- if (!strcmp(id, "usbh")) ++ if (!strcmp(id, "usbh") || (BCMCPU_IS_6318() && !strcmp(id, "usbd"))) + return &clk_usbh; +- if (!strcmp(id, "usbd")) ++ if (!strcmp(id, "usbd") && !BCMCPU_IS_6318()) + return &clk_usbd; + if (!strcmp(id, "spi")) + return &clk_spi; diff --git a/target/linux/brcm63xx/patches-3.18/347-MIPS-BCM6318-USB-support.patch b/target/linux/brcm63xx/patches-3.18/347-MIPS-BCM6318-USB-support.patch new file mode 100644 index 0000000..904d0b7 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/347-MIPS-BCM6318-USB-support.patch @@ -0,0 +1,124 @@ +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_6318()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); ++ reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG); + } + + spin_unlock_irqrestore(&usb_priv_reg_lock, flags); +@@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_6318()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); ++ reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG); + } + + spin_unlock_irqrestore(&usb_priv_reg_lock, flags); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -681,6 +681,12 @@ + #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) + #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) + ++#define GPIO_PINMUX_SEL0_6318 0x1c ++#define GPIO_PINMUX_SEL0_GPIO13_SHIFT 26 ++#define GPIO_PINMUX_SEL0_GPIO13_MASK (0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_PWRON (1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_LED (2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_GPIO (3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) + + #define GPIO_PINMUX_OTHR_REG 0x24 + #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 +@@ -999,6 +1005,7 @@ + + #define USBH_PRIV_SWAP_6358_REG 0x0 + #define USBH_PRIV_SWAP_6368_REG 0x1c ++#define USBH_PRIV_SWAP_6318_REG 0x0c + + #define USBH_PRIV_SWAP_USBD_SHIFT 6 + #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) +@@ -1024,6 +1031,13 @@ + #define USBH_PRIV_SETUP_IOC_SHIFT 4 + #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) + ++#define USBH_PRIV_SETUP_6318_REG 0x00 ++#define USBH_PRIV_PLL_CTRL1_6318_REG 0x04 ++#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27) ++#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31) ++#define USBH_PRIV_SIM_CTRL_6318_REG 0x20 ++#define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5) ++ + + /************************************************************************* + * _REG relative to RSET_USBD +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -129,6 +129,15 @@ void __init board_early_setup(const stru + } + + bcm_gpio_writel(val, GPIO_MODE_REG); ++ ++#if IS_ENABLED(CONFIG_USB) ++ if (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) { ++ val = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318); ++ val &= ~GPIO_PINMUX_SEL0_GPIO13_MASK; ++ val |= GPIO_PINMUX_SEL0_GPIO13_PWRON; ++ bcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318); ++ } ++#endif + } + + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -22,6 +22,8 @@ config BCM63XX_CPU_6318 + bool "support 6318 CPU" + select SYS_HAS_CPU_BMIPS32_3300 + select HW_HAS_PCI ++ select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6328 + bool "support 6328 CPU" diff --git a/target/linux/brcm63xx/patches-3.18/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch b/target/linux/brcm63xx/patches-3.18/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch new file mode 100644 index 0000000..c758163 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch @@ -0,0 +1,71 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -586,6 +586,9 @@ + #define TIMER_CTL_MONOTONIC_MASK (1 << 30) + #define TIMER_CTL_ENABLE_MASK (1 << 31) + ++/* Clock reset control (63268 only) */ ++#define TIMER_CLK_RST_CTL_REG 0x2c ++#define CLK_RST_CTL_USB_REF_CLK_EN (1 << 18) + + /************************************************************************* + * _REG relative to RSET_WDT +@@ -1547,6 +1550,11 @@ + #define STRAPBUS_63268_FCVO_SHIFT 21 + #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) + ++#define MISC_IDDQ_CTRL_6328_REG 0x48 ++#define MISC_IDDQ_CTRL_63268_REG 0x4c ++ ++#define IDDQ_CTRL_63268_USBH (1 << 4) ++ + #define MISC_STRAPBUS_6328_REG 0x240 + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -62,6 +62,26 @@ static void bcm_ub_hwclock_set(u32 mask, + bcm_perf_writel(reg, PERF_UB_CKCTL_REG); + } + ++static void bcm_misc_iddq_set(u32 mask, int enable) ++{ ++ u32 offset; ++ u32 reg; ++ ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) ++ offset = MISC_IDDQ_CTRL_6328_REG; ++ else if (BCMCPU_IS_63268()) ++ offset = MISC_IDDQ_CTRL_63268_REG; ++ else ++ return; ++ ++ reg = bcm_misc_readl(offset); ++ if (enable) ++ reg &= ~mask; ++ else ++ reg |= mask; ++ bcm_misc_writel(reg, offset); ++} ++ + /* + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 + */ +@@ -199,7 +219,17 @@ static void usbh_set(struct clk *clk, in + } else if (BCMCPU_IS_6368()) { + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); + } else if (BCMCPU_IS_63268()) { ++ u32 reg; ++ + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); ++ bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable); ++ bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable); ++ reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG); ++ if (enable) ++ reg |= CLK_RST_CTL_USB_REF_CLK_EN; ++ else ++ reg &= ~CLK_RST_CTL_USB_REF_CLK_EN; ++ bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG); + } else { + return; + } diff --git a/target/linux/brcm63xx/patches-3.18/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch b/target/linux/brcm63xx/patches-3.18/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch new file mode 100644 index 0000000..0b70991 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch @@ -0,0 +1,117 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -1033,11 +1033,18 @@ + #define USBH_PRIV_SETUP_6368_REG 0x28 + #define USBH_PRIV_SETUP_IOC_SHIFT 4 + #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) ++#define USBH_PRIV_SETUP_IPP_SHIFT 5 ++#define USBH_PRIV_SETUP_IPP_MASK (1 << USBH_PRIV_SETUP_IPP_SHIFT) + + #define USBH_PRIV_SETUP_6318_REG 0x00 ++#define USBH_PRIV_PLL_CTRL1_6368_REG 0x18 + #define USBH_PRIV_PLL_CTRL1_6318_REG 0x04 +-#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27) +-#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31) ++ ++#define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN (1 << 27) ++#define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN (1 << 31) ++#define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN (1 << 9) ++#define USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY (1 << 10) ++ + #define USBH_PRIV_SIM_CTRL_6318_REG 0x20 + #define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -72,6 +72,8 @@ config BCM63XX_CPU_63268 + bool "support 63268 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI ++ select BCM63XX_EHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -82,7 +82,7 @@ static struct platform_device bcm63xx_eh + int __init bcm63xx_ehci_register(void) + { + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && +- !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return 0; + + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -109,9 +109,24 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_63268()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ reg &= ~USBH_PRIV_SETUP_IPP_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG); ++ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN | ++ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY); ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG); + } else if (BCMCPU_IS_6318()) { + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); +@@ -124,7 +139,7 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); +@@ -165,9 +180,24 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_63268()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ reg &= ~USBH_PRIV_SETUP_IPP_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG); ++ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN | ++ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY); ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG); + } else if (BCMCPU_IS_6318()) { + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); +@@ -180,7 +210,7 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); diff --git a/target/linux/brcm63xx/patches-3.18/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch b/target/linux/brcm63xx/patches-3.18/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch new file mode 100644 index 0000000..41747da --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch @@ -0,0 +1,107 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -42,6 +42,7 @@ struct board_info { + + /* USB config */ + struct bcm63xx_usbd_platform_data usbd; ++ unsigned int num_usbh_ports:2; + + /* DSP config */ + struct bcm63xx_dsp_platform_data dsp; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h +@@ -1,6 +1,6 @@ + #ifndef BCM63XX_DEV_USB_EHCI_H_ + #define BCM63XX_DEV_USB_EHCI_H_ + +-int bcm63xx_ehci_register(void); ++int bcm63xx_ehci_register(unsigned int num_ports); + + #endif /* BCM63XX_DEV_USB_EHCI_H_ */ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h +@@ -1,6 +1,6 @@ + #ifndef BCM63XX_DEV_USB_OHCI_H_ + #define BCM63XX_DEV_USB_OHCI_H_ + +-int bcm63xx_ohci_register(void); ++int bcm63xx_ohci_register(unsigned int num_ports); + + #endif /* BCM63XX_DEV_USB_OHCI_H_ */ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -181,6 +181,7 @@ int __init board_register_devices(void) + { + int button_count = 0; + int led_count = 0; ++ int usbh_ports = 0; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -203,14 +204,21 @@ int __init board_register_devices(void) + !board_get_mac_address(board.enetsw.mac_addr)) + bcm63xx_enetsw_register(&board.enetsw); + ++ if ((board.has_ohci0 || board.has_ehci0)) { ++ usbh_ports = board.num_usbh_ports; ++ ++ if (!usbh_ports || WARN_ON(usbh_ports > 1 && board.has_usbd)) ++ usbh_ports = 1; ++ } ++ + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + + if (board.has_ehci0) +- bcm63xx_ehci_register(); ++ bcm63xx_ehci_register(usbh_ports); + + if (board.has_ohci0) +- bcm63xx_ohci_register(); ++ bcm63xx_ohci_register(usbh_ports); + + if (board.has_dsp) + bcm63xx_dsp_register(&board.dsp); +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -79,12 +79,14 @@ static struct platform_device bcm63xx_eh + }, + }; + +-int __init bcm63xx_ehci_register(void) ++int __init bcm63xx_ehci_register(unsigned int num_ports) + { + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && + !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return 0; + ++ bcm63xx_ehci_pdata.num_ports = num_ports; ++ + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); + ehci_resources[0].end = ehci_resources[0].start; + ehci_resources[0].end += RSET_EHCI_SIZE - 1; +--- a/arch/mips/bcm63xx/dev-usb-ohci.c ++++ b/arch/mips/bcm63xx/dev-usb-ohci.c +@@ -62,7 +62,6 @@ static struct usb_ohci_pdata bcm63xx_ohc + .big_endian_desc = 1, + .big_endian_mmio = 1, + .no_big_frame_no = 1, +- .num_ports = 1, + .power_on = bcm63xx_ohci_power_on, + .power_off = bcm63xx_ohci_power_off, + .power_suspend = bcm63xx_ohci_power_off, +@@ -80,11 +79,13 @@ static struct platform_device bcm63xx_oh + }, + }; + +-int __init bcm63xx_ohci_register(void) ++int __init bcm63xx_ohci_register(unsigned int num_ports) + { + if (BCMCPU_IS_6345() || BCMCPU_IS_6338()) + return -ENODEV; + ++ bcm63xx_ohci_pdata.num_ports = num_ports; ++ + ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0); + ohci_resources[0].end = ohci_resources[0].start; + ohci_resources[0].end += RSET_OHCI_SIZE - 1; diff --git a/target/linux/brcm63xx/patches-3.18/351-set-board-usbh-ports.patch b/target/linux/brcm63xx/patches-3.18/351-set-board-usbh-ports.patch new file mode 100644 index 0000000..285aa40 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/351-set-board-usbh-ports.patch @@ -0,0 +1,10 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -596,6 +596,7 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, ++ .num_usbh_ports = 2, + + .leds = { + { diff --git a/target/linux/brcm63xx/patches-3.18/354-MIPS-BCM63XX-allow-building-support-for-more-than-on.patch b/target/linux/brcm63xx/patches-3.18/354-MIPS-BCM63XX-allow-building-support-for-more-than-on.patch new file mode 100644 index 0000000..c60f939 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/354-MIPS-BCM63XX-allow-building-support-for-more-than-on.patch @@ -0,0 +1,95 @@ +From 0daf361ea799fba0af5a232036d0f06cea85ad24 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Jun 2014 12:47:49 +0200 +Subject: [PATCH 42/44] MIPS: BCM63XX: allow building support for more than one + board type + +Use the arguments passed to the kernel to detect being booted with +CFE as the indicator for bcm963xx board support, allowing the +non presence of CFE_EPTSEAL to assume a different board type. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/Kconfig | 7 +++---- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/boards/board_common.c | 13 +++++++++++++ + arch/mips/bcm63xx/boards/board_common.h | 6 ++++++ + 4 files changed, 23 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -1,11 +1,10 @@ +-choice +- prompt "Board support" ++menu "Board support" + depends on BCM63XX +- default BOARD_BCM963XX + + config BOARD_BCM963XX + bool "Generic Broadcom 963xx boards" + select SSB ++ default y + help + +-endchoice ++endmenu +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -706,7 +706,7 @@ static const struct board_info __initcon + /* + * early init callback, read nvram data from flash and checksum it + */ +-void __init board_prom_init(void) ++void __init board_bcm963xx_init(void) + { + unsigned int i; + u8 *boot_addr, *cfe; +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -15,6 +15,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -32,6 +34,8 @@ + #include + #include + ++#include "board_common.h" ++ + #define PFX "board: " + + #define BCM963XX_KEYS_POLL_INTERVAL 20 +@@ -84,6 +88,15 @@ const char *board_get_name(void) + return board.name; + } + ++void __init board_prom_init(void) ++{ ++ /* detect bootloader */ ++ if (fw_arg3 == CFE_EPTSEAL) ++ board_bcm963xx_init(); ++ else ++ panic("unsupported bootloader detected"); ++} ++ + static int (*board_get_mac_address)(u8 mac[ETH_ALEN]); + + /* +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -6,4 +6,10 @@ + void board_early_setup(const struct board_info *board, + int (*get_mac_address)(u8 mac[ETH_ALEN])); + ++#if defined(CONFIG_BOARD_BCM963XX) ++void board_bcm963xx_init(void); ++#else ++static inline void board_bcm963xx_init(void) { } ++#endif ++ + #endif /* __BOARD_COMMON_H */ diff --git a/target/linux/brcm63xx/patches-3.18/355-MIPS-BCM63XX-allow-board-implementations-to-force-fl.patch b/target/linux/brcm63xx/patches-3.18/355-MIPS-BCM63XX-allow-board-implementations-to-force-fl.patch new file mode 100644 index 0000000..bdbba03 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/355-MIPS-BCM63XX-allow-board-implementations-to-force-fl.patch @@ -0,0 +1,61 @@ +From 8a30097a899b975709f728666d5ad20c8b832d21 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Mar 2014 04:28:14 +0100 +Subject: [PATCH 43/44] MIPS: BCM63XX: allow board implementations to force + flash address + +Allow board implementations to force the physmap address. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 19 ++++++++++++++----- + .../mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++ + 2 files changed, 16 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -58,6 +58,12 @@ static struct platform_device mtd_dev = + }, + }; + ++void __init bcm63xx_flash_force_phys_base_address(u32 start, u32 end) ++{ ++ mtd_resources[0].start = start; ++ mtd_resources[0].end = end; ++} ++ + static int __init bcm63xx_detect_flash_type(void) + { + u32 val; +@@ -172,12 +178,15 @@ int __init bcm63xx_flash_register(void) + + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: +- /* read base address of boot chip select (0) */ +- val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +- val &= MPI_CSBASE_BASE_MASK; + +- mtd_resources[0].start = val; +- mtd_resources[0].end = 0x1FFFFFFF; ++ if (!mtd_resources[0].start) { ++ /* read base address of boot chip select (0) */ ++ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); ++ val &= MPI_CSBASE_BASE_MASK; ++ ++ mtd_resources[0].start = val; ++ mtd_resources[0].end = 0x1FFFFFFF; ++ } + + return platform_device_register(&mtd_dev); + case BCM63XX_FLASH_TYPE_SERIAL: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -9,6 +9,8 @@ enum { + + void bcm63xx_flash_detect(void); + ++void bcm63xx_flash_force_phys_base_address(u32 start, u32 end); ++ + int __init bcm63xx_flash_register(void); + + #endif /* __BCM63XX_FLASH_H */ diff --git a/target/linux/brcm63xx/patches-3.18/356-MIPS-BCM63XX-move-fallback-sprom-support-into-its-ow.patch b/target/linux/brcm63xx/patches-3.18/356-MIPS-BCM63XX-move-fallback-sprom-support-into-its-ow.patch new file mode 100644 index 0000000..450bc1d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/356-MIPS-BCM63XX-move-fallback-sprom-support-into-its-ow.patch @@ -0,0 +1,188 @@ +From cc025e749a1fece61a6cc0d64bbe7b12472259cc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 21:31:12 +0200 +Subject: [PATCH 01/10] MIPS: BCM63XX: move fallback sprom support into its own + unit + +In preparation for enhancing it, move it into its own file. Require a +mac address to be passed as the argument to always "reserve" the mac +regardless of the inclusion state of SSB. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/boards/board_common.c | 53 ++-------------- + arch/mips/bcm63xx/sprom.c | 70 ++++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 6 ++ + 4 files changed, 83 insertions(+), 48 deletions(-) + create mode 100644 arch/mips/bcm63xx/sprom.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ + dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ +- usb-common.o ++ usb-common.o sprom.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -43,44 +43,6 @@ + static struct board_info board; + + /* +- * Register a sane SPROMv2 to make the on-board +- * bcm4318 WLAN work +- */ +-#ifdef CONFIG_SSB_PCIHOST +-static struct ssb_sprom bcm63xx_sprom = { +- .revision = 0x02, +- .board_rev = 0x17, +- .country_code = 0x0, +- .ant_available_bg = 0x3, +- .pa0b0 = 0x15ae, +- .pa0b1 = 0xfa85, +- .pa0b2 = 0xfe8d, +- .pa1b0 = 0xffff, +- .pa1b1 = 0xffff, +- .pa1b2 = 0xffff, +- .gpio0 = 0xff, +- .gpio1 = 0xff, +- .gpio2 = 0xff, +- .gpio3 = 0xff, +- .maxpwr_bg = 0x004c, +- .itssi_bg = 0x00, +- .boardflags_lo = 0x2848, +- .boardflags_hi = 0x0000, +-}; +- +-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +-{ +- if (bus->bustype == SSB_BUSTYPE_PCI) { +- memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); +- return 0; +- } else { +- printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); +- return -EINVAL; +- } +-} +-#endif +- +-/* + * return board name for /proc/cpuinfo + */ + const char *board_get_name(void) +@@ -195,6 +157,7 @@ int __init board_register_devices(void) + int button_count = 0; + int led_count = 0; + int usbh_ports = 0; ++ u8 mac[ETH_ALEN]; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -239,15 +202,10 @@ int __init board_register_devices(void) + /* Generate MAC address for WLAN and register our SPROM, + * do this after registering enet devices + */ +-#ifdef CONFIG_SSB_PCIHOST +- if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { +- memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); +- memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); +- if (ssb_arch_register_fallback_sprom( +- &bcm63xx_get_fallback_sprom) < 0) +- pr_err(PFX "failed to register fallback SPROM\n"); +- } +-#endif ++ ++ if (board_get_mac_address(mac) || ++ bcm63xx_register_fallback_sprom(mac)) ++ pr_err(PFX "failed to register fallback SPROM\n"); + + bcm63xx_spi_register(); + +--- /dev/null ++++ b/arch/mips/bcm63xx/sprom.c +@@ -0,0 +1,70 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2008 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFX "sprom: " ++ ++/* ++ * Register a sane SPROMv2 to make the on-board ++ * bcm4318 WLAN work ++ */ ++#ifdef CONFIG_SSB_PCIHOST ++static struct ssb_sprom bcm63xx_sprom = { ++ .revision = 0x02, ++ .board_rev = 0x17, ++ .country_code = 0x0, ++ .ant_available_bg = 0x3, ++ .pa0b0 = 0x15ae, ++ .pa0b1 = 0xfa85, ++ .pa0b2 = 0xfe8d, ++ .pa1b0 = 0xffff, ++ .pa1b1 = 0xffff, ++ .pa1b2 = 0xffff, ++ .gpio0 = 0xff, ++ .gpio1 = 0xff, ++ .gpio2 = 0xff, ++ .gpio3 = 0xff, ++ .maxpwr_bg = 0x004c, ++ .itssi_bg = 0x00, ++ .boardflags_lo = 0x2848, ++ .boardflags_hi = 0x0000, ++}; ++ ++int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) ++{ ++ if (bus->bustype == SSB_BUSTYPE_PCI) { ++ memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ return 0; ++ } else { ++ printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); ++ return -EINVAL; ++ } ++} ++#endif ++ ++int __init bcm63xx_register_fallback_sprom(u8 *mac) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_SSB_PCIHOST ++ memcpy(bcm63xx_sprom.il0mac, mac, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et0mac, mac, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et1mac, mac, ETH_ALEN); ++ ++ ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom); ++#endif ++ return ret; ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -0,0 +1,6 @@ ++#ifndef __BCM63XX_FALLBACK_SPROM ++#define __BCM63XX_FALLBACK_SPROM ++ ++int bcm63xx_register_fallback_sprom(u8 *mac); ++ ++#endif diff --git a/target/linux/brcm63xx/patches-3.18/357-MIPS-BCM63XX-use-platform-data-for-the-sprom.patch b/target/linux/brcm63xx/patches-3.18/357-MIPS-BCM63XX-use-platform-data-for-the-sprom.patch new file mode 100644 index 0000000..bc35c25 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/357-MIPS-BCM63XX-use-platform-data-for-the-sprom.patch @@ -0,0 +1,95 @@ +From 9912a8b3c240a9b0af01ff496b7e8ed9e4cc5b82 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 21:43:49 +0200 +Subject: [PATCH 02/10] MIPS: BCM63XX: use platform data for the sprom + +Similar to ethernet setup, use a platform data struct for passing +the mac. This eliminates the requirement to allocate an array on +stack for the mac passed. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_common.c | 6 ++---- + arch/mips/bcm63xx/sprom.c | 8 ++++---- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 8 +++++++- + arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 4 ++++ + 4 files changed, 17 insertions(+), 9 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -157,7 +157,6 @@ int __init board_register_devices(void) + int button_count = 0; + int led_count = 0; + int usbh_ports = 0; +- u8 mac[ETH_ALEN]; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -203,8 +202,8 @@ int __init board_register_devices(void) + * do this after registering enet devices + */ + +- if (board_get_mac_address(mac) || +- bcm63xx_register_fallback_sprom(mac)) ++ if (board_get_mac_address(board.fallback_sprom.mac_addr) || ++ bcm63xx_register_fallback_sprom(&board.fallback_sprom)) + pr_err(PFX "failed to register fallback SPROM\n"); + + bcm63xx_spi_register(); +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -55,14 +55,14 @@ int bcm63xx_get_fallback_sprom(struct ss + } + #endif + +-int __init bcm63xx_register_fallback_sprom(u8 *mac) ++int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data) + { + int ret = 0; + + #ifdef CONFIG_SSB_PCIHOST +- memcpy(bcm63xx_sprom.il0mac, mac, ETH_ALEN); +- memcpy(bcm63xx_sprom.et0mac, mac, ETH_ALEN); +- memcpy(bcm63xx_sprom.et1mac, mac, ETH_ALEN); ++ memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); + + ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom); + #endif +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -1,6 +1,12 @@ + #ifndef __BCM63XX_FALLBACK_SPROM + #define __BCM63XX_FALLBACK_SPROM + +-int bcm63xx_register_fallback_sprom(u8 *mac); ++#include ++ ++struct fallback_sprom_data { ++ u8 mac_addr[ETH_ALEN]; ++}; ++ ++int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data); + + #endif +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + + /* + * flash mapping +@@ -59,6 +60,9 @@ struct board_info { + /* External PHY reset GPIO flags from gpio.h */ + unsigned long ephy_reset_gpio_flags; + ++ /* fallback sprom config */ ++ struct fallback_sprom_data fallback_sprom; ++ + /* Additional platform devices */ + struct platform_device **devs; + unsigned int num_devs; diff --git a/target/linux/brcm63xx/patches-3.18/358-MIPS-BCM63XX-make-fallback-sprom-optional.patch b/target/linux/brcm63xx/patches-3.18/358-MIPS-BCM63XX-make-fallback-sprom-optional.patch new file mode 100644 index 0000000..d7250d5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/358-MIPS-BCM63XX-make-fallback-sprom-optional.patch @@ -0,0 +1,140 @@ +From 83131acbfb59760a19f3711c09526e191c8aad54 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 21:52:56 +0200 +Subject: [PATCH 03/10] MIPS: BCM63XX: make fallback sprom optional + +Some devices do not provide enough mac addresses to populate wifi in +addition to ethernet. + +Use having pci enabled as a rough heuristic which boards should have it +enabled. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 12 ++++++++++++ + arch/mips/bcm63xx/boards/board_common.c | 5 +++-- + arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 1 + + 3 files changed, 16 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -74,6 +74,7 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_pci = 1, + .has_usbd = 0, ++ .use_fallback_sprom = 1, + + .usbd = { + .use_fullspeed = 0, +@@ -223,6 +224,7 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_enet0 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -268,6 +270,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -328,6 +331,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -382,6 +386,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -440,6 +445,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -463,6 +469,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -481,6 +488,7 @@ static struct board_info __initdata boar + + .has_uart0 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + .has_ohci0 = 1, + + .has_enet0 = 1, +@@ -503,6 +511,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -529,6 +538,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -581,6 +591,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -652,6 +663,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -202,8 +202,9 @@ int __init board_register_devices(void) + * do this after registering enet devices + */ + +- if (board_get_mac_address(board.fallback_sprom.mac_addr) || +- bcm63xx_register_fallback_sprom(&board.fallback_sprom)) ++ if (board.use_fallback_sprom && ++ (board_get_mac_address(board.fallback_sprom.mac_addr) || ++ bcm63xx_register_fallback_sprom(&board.fallback_sprom))) + pr_err(PFX "failed to register fallback SPROM\n"); + + bcm63xx_spi_register(); +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -35,6 +35,7 @@ struct board_info { + unsigned int has_dsp:1; + unsigned int has_uart0:1; + unsigned int has_uart1:1; ++ unsigned int use_fallback_sprom:1; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; diff --git a/target/linux/brcm63xx/patches-3.18/359-MIPS-BCM63XX-allow-different-types-of-sprom.patch b/target/linux/brcm63xx/patches-3.18/359-MIPS-BCM63XX-allow-different-types-of-sprom.patch new file mode 100644 index 0000000..0c4a9be --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/359-MIPS-BCM63XX-allow-different-types-of-sprom.patch @@ -0,0 +1,66 @@ +From 1cece9f7aca1f0c193edce201f77a87008c5a405 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 21:58:38 +0200 +Subject: [PATCH 04/10] MIPS: BCM63XX: allow different types of sprom + +Different chips require different sprom contents, so prepare for +supplying the appropriate sprom type. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 13 ++++++++++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 5 +++++ + 2 files changed, 17 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -22,7 +22,7 @@ + * bcm4318 WLAN work + */ + #ifdef CONFIG_SSB_PCIHOST +-static struct ssb_sprom bcm63xx_sprom = { ++static __initconst struct ssb_sprom bcm63xx_default_sprom = { + .revision = 0x02, + .board_rev = 0x17, + .country_code = 0x0, +@@ -43,6 +43,8 @@ static struct ssb_sprom bcm63xx_sprom = + .boardflags_hi = 0x0000, + }; + ++static struct ssb_sprom bcm63xx_sprom; ++ + int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) + { + if (bus->bustype == SSB_BUSTYPE_PCI) { +@@ -60,6 +62,15 @@ int __init bcm63xx_register_fallback_spr + int ret = 0; + + #ifdef CONFIG_SSB_PCIHOST ++ switch (data->type) { ++ case SPROM_DEFAULT: ++ memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, ++ sizeof(bcm63xx_sprom)); ++ break; ++ default: ++ return -EINVAL; ++ } ++ + memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -3,8 +3,13 @@ + + #include + ++enum sprom_type { ++ SPROM_DEFAULT, /* default fallback sprom */ ++}; ++ + struct fallback_sprom_data { + u8 mac_addr[ETH_ALEN]; ++ enum sprom_type type; + }; + + int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data); diff --git a/target/linux/brcm63xx/patches-3.18/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch b/target/linux/brcm63xx/patches-3.18/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch new file mode 100644 index 0000000..42502eb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch @@ -0,0 +1,517 @@ +From cedee63bc73f8b7d45b8c0cba1236986812c1f83 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 22:16:36 +0200 +Subject: [PATCH 05/10] MIPS: BCM63XX: add support for "raw" sproms + +Allow using raw sprom content as templates. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 482 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 482 insertions(+) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -55,13 +55,492 @@ int bcm63xx_get_fallback_sprom(struct ss + return -EINVAL; + } + } ++ ++/* FIXME: use lib_sprom after submission upstream */ ++ ++/* Get the word-offset for a SSB_SPROM_XXX define. */ ++#define SPOFF(offset) ((offset) / sizeof(u16)) ++/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */ ++#define SPEX16(_outvar, _offset, _mask, _shift) \ ++ out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) ++#define SPEX32(_outvar, _offset, _mask, _shift) \ ++ out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \ ++ in[SPOFF(_offset)]) & (_mask)) >> (_shift)) ++#define SPEX(_outvar, _offset, _mask, _shift) \ ++ SPEX16(_outvar, _offset, _mask, _shift) ++ ++#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ ++ do { \ ++ SPEX(_field[0], _offset + 0, _mask, _shift); \ ++ SPEX(_field[1], _offset + 2, _mask, _shift); \ ++ SPEX(_field[2], _offset + 4, _mask, _shift); \ ++ SPEX(_field[3], _offset + 6, _mask, _shift); \ ++ SPEX(_field[4], _offset + 8, _mask, _shift); \ ++ SPEX(_field[5], _offset + 10, _mask, _shift); \ ++ SPEX(_field[6], _offset + 12, _mask, _shift); \ ++ SPEX(_field[7], _offset + 14, _mask, _shift); \ ++ } while (0) ++ ++ ++static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in, ++ u16 mask, u16 shift) ++{ ++ u16 v; ++ u8 gain; ++ ++ v = in[SPOFF(SSB_SPROM1_AGAIN)]; ++ gain = (v & mask) >> shift; ++ if (gain == 0xFF) ++ gain = 2; /* If unset use 2dBm */ ++ if (sprom_revision == 1) { ++ /* Convert to Q5.2 */ ++ gain <<= 2; ++ } else { ++ /* Q5.2 Fractional part is stored in 0xC0 */ ++ gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2); ++ } ++ ++ return (s8)gain; ++} ++ ++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); ++ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); ++ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); ++ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, ++ SSB_SPROM2_MAXP_A_LO_SHIFT); ++} ++ ++static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) ++{ ++ u16 loc[3]; ++ ++ if (out->revision == 3) /* rev 3 moved MAC */ ++ loc[0] = SSB_SPROM3_IL0MAC; ++ else { ++ loc[0] = SSB_SPROM1_IL0MAC; ++ loc[1] = SSB_SPROM1_ET0MAC; ++ loc[2] = SSB_SPROM1_ET1MAC; ++ } ++ ++ SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0); ++ SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A, ++ SSB_SPROM1_ETHPHY_ET1A_SHIFT); ++ SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14); ++ SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15); ++ SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); ++ if (out->revision == 1) ++ SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE, ++ SSB_SPROM1_BINF_CCODE_SHIFT); ++ SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA, ++ SSB_SPROM1_BINF_ANTA_SHIFT); ++ SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG, ++ SSB_SPROM1_BINF_ANTBG_SHIFT); ++ SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0); ++ SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0); ++ SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0); ++ SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0); ++ SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0); ++ SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0); ++ SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1, ++ SSB_SPROM1_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3, ++ SSB_SPROM1_GPIOB_P3_SHIFT); ++ SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A, ++ SSB_SPROM1_MAXPWR_A_SHIFT); ++ SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0); ++ SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A, ++ SSB_SPROM1_ITSSI_A_SHIFT); ++ SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); ++ SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); ++ ++ SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); ++ ++ /* Extract the antenna gain values. */ ++ out->antenna_gain.a0 = r123_extract_antgain(out->revision, in, ++ SSB_SPROM1_AGAIN_BG, ++ SSB_SPROM1_AGAIN_BG_SHIFT); ++ out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, ++ SSB_SPROM1_AGAIN_A, ++ SSB_SPROM1_AGAIN_A_SHIFT); ++ if (out->revision >= 2) ++ sprom_extract_r23(out, in); ++} ++ ++/* Revs 4 5 and 8 have partially shared layout */ ++static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, ++ SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT); ++ SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, ++ SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT); ++ SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, ++ SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT); ++ SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, ++ SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT); ++ ++ SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, ++ SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT); ++ SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, ++ SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT); ++ SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, ++ SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT); ++ SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, ++ SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT); ++ ++ SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, ++ SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT); ++ SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, ++ SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT); ++ SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, ++ SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT); ++ SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, ++ SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT); ++ ++ SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, ++ SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT); ++ SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, ++ SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT); ++ SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, ++ SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT); ++ SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, ++ SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT); ++} ++ ++static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) ++{ ++ u16 il0mac_offset; ++ ++ if (out->revision == 4) ++ il0mac_offset = SSB_SPROM4_IL0MAC; ++ else ++ il0mac_offset = SSB_SPROM5_IL0MAC; ++ ++ SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0); ++ SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A, ++ SSB_SPROM4_ETHPHY_ET1A_SHIFT); ++ SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); ++ if (out->revision == 4) { ++ SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0); ++ SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0); ++ SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0); ++ SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0); ++ SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0); ++ } else { ++ SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0); ++ SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0); ++ SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0); ++ SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0); ++ SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0); ++ } ++ SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A, ++ SSB_SPROM4_ANTAVAIL_A_SHIFT); ++ SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG, ++ SSB_SPROM4_ANTAVAIL_BG_SHIFT); ++ SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0); ++ SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG, ++ SSB_SPROM4_ITSSI_BG_SHIFT); ++ SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0); ++ SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A, ++ SSB_SPROM4_ITSSI_A_SHIFT); ++ if (out->revision == 4) { ++ SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1, ++ SSB_SPROM4_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3, ++ SSB_SPROM4_GPIOB_P3_SHIFT); ++ } else { ++ SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1, ++ SSB_SPROM5_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3, ++ SSB_SPROM5_GPIOB_P3_SHIFT); ++ } ++ ++ /* Extract the antenna gain values. */ ++ SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01, ++ SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT); ++ SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01, ++ SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT); ++ SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23, ++ SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT); ++ SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23, ++ SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT); ++ ++ sprom_extract_r458(out, in); ++ ++ /* TODO - get remaining rev 4 stuff needed */ ++} ++ ++static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) ++{ ++ int i; ++ u16 o; ++ u16 pwr_info_offset[] = { ++ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1, ++ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3 ++ }; ++ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) != ++ ARRAY_SIZE(out->core_pwr_info)); ++ ++ SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); ++ SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0); ++ SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0); ++ SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0); ++ SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0); ++ SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0); ++ SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A, ++ SSB_SPROM8_ANTAVAIL_A_SHIFT); ++ SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG, ++ SSB_SPROM8_ANTAVAIL_BG_SHIFT); ++ SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0); ++ SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG, ++ SSB_SPROM8_ITSSI_BG_SHIFT); ++ SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0); ++ SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A, ++ SSB_SPROM8_ITSSI_A_SHIFT); ++ SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0); ++ SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK, ++ SSB_SPROM8_MAXP_AL_SHIFT); ++ SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1, ++ SSB_SPROM8_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3, ++ SSB_SPROM8_GPIOB_P3_SHIFT); ++ SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0); ++ SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G, ++ SSB_SPROM8_TRI5G_SHIFT); ++ SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0); ++ SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH, ++ SSB_SPROM8_TRI5GH_SHIFT); ++ SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0); ++ SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G, ++ SSB_SPROM8_RXPO5G_SHIFT); ++ SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0); ++ SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G, ++ SSB_SPROM8_RSSISMC2G_SHIFT); ++ SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G, ++ SSB_SPROM8_RSSISAV2G_SHIFT); ++ SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G, ++ SSB_SPROM8_BXA2G_SHIFT); ++ SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0); ++ SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G, ++ SSB_SPROM8_RSSISMC5G_SHIFT); ++ SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G, ++ SSB_SPROM8_RSSISAV5G_SHIFT); ++ SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G, ++ SSB_SPROM8_BXA5G_SHIFT); ++ SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0); ++ SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0); ++ SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0); ++ SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0); ++ SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0); ++ SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0); ++ SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0); ++ SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0); ++ SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0); ++ SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0); ++ SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0); ++ SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0); ++ ++ /* Extract the antenna gain values. */ ++ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01, ++ SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT); ++ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01, ++ SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT); ++ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23, ++ SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT); ++ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23, ++ SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT); ++ ++ /* Extract cores power info info */ ++ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) { ++ o = pwr_info_offset[i]; ++ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI, ++ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT); ++ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI, ++ SSB_SPROM8_2G_MAXP, 0); ++ ++ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0); ++ ++ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI, ++ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT); ++ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI, ++ SSB_SPROM8_5G_MAXP, 0); ++ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP, ++ SSB_SPROM8_5GH_MAXP, 0); ++ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP, ++ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT); ++ ++ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0); ++ } ++ ++ /* Extract FEM info */ ++ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON, ++ SSB_SPROM8_LEDDC_ON_SHIFT); ++ SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF, ++ SSB_SPROM8_LEDDC_OFF_SHIFT); ++ ++ SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN, ++ SSB_SPROM8_TXRXC_TXCHAIN_SHIFT); ++ SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN, ++ SSB_SPROM8_TXRXC_RXCHAIN_SHIFT); ++ SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH, ++ SSB_SPROM8_TXRXC_SWITCH_SHIFT); ++ ++ SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0); ++ ++ SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0); ++ ++ SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP, ++ SSB_SPROM8_RAWTS_RAWTEMP_SHIFT); ++ SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER, ++ SSB_SPROM8_RAWTS_MEASPOWER_SHIFT); ++ SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX, ++ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE, ++ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT); ++ SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX, ++ SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT); ++ SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX, ++ SSB_SPROM8_OPT_CORRX_TEMP_OPTION, ++ SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT); ++ SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP, ++ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR, ++ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT); ++ SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP, ++ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP, ++ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT); ++ SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL, ++ SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT); ++ ++ SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0); ++ SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0); ++ SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0); ++ SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0); ++ ++ SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH, ++ SSB_SPROM8_THERMAL_TRESH_SHIFT); ++ SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET, ++ SSB_SPROM8_THERMAL_OFFSET_SHIFT); ++ SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA, ++ SSB_SPROM8_TEMPDELTA_PHYCAL, ++ SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT); ++ SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD, ++ SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT); ++ SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA, ++ SSB_SPROM8_TEMPDELTA_HYSTERESIS, ++ SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT); ++ sprom_extract_r458(out, in); ++ ++ /* TODO - get remaining rev 8 stuff needed */ ++} ++ ++static int sprom_extract(struct ssb_sprom *out, const u16 *in, u16 size) ++{ ++ memset(out, 0, sizeof(*out)); ++ ++ out->revision = in[size - 1] & 0x00FF; ++ memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ ++ memset(out->et1mac, 0xFF, 6); ++ ++ switch (out->revision) { ++ case 1: ++ case 2: ++ case 3: ++ sprom_extract_r123(out, in); ++ break; ++ case 4: ++ case 5: ++ sprom_extract_r45(out, in); ++ break; ++ case 8: ++ sprom_extract_r8(out, in); ++ break; ++ default: ++ pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n", ++ out->revision); ++ out->revision = 1; ++ sprom_extract_r123(out, in); ++ } ++ ++ if (out->boardflags_lo == 0xFFFF) ++ out->boardflags_lo = 0; /* per specs */ ++ if (out->boardflags_hi == 0xFFFF) ++ out->boardflags_hi = 0; /* per specs */ ++ ++ return 0; ++} ++ ++static __initdata u16 template_sprom[220]; + #endif + ++ + int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data) + { + int ret = 0; + + #ifdef CONFIG_SSB_PCIHOST ++ u16 size = 0; ++ + switch (data->type) { + case SPROM_DEFAULT: + memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, +@@ -71,6 +550,9 @@ int __init bcm63xx_register_fallback_spr + return -EINVAL; + } + ++ if (size > 0) ++ sprom_extract(&bcm63xx_sprom, template_sprom, size); ++ + memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); diff --git a/target/linux/brcm63xx/patches-3.18/361-MIPS-BCM63XX-add-raw-fallback-sproms-for-most-common.patch b/target/linux/brcm63xx/patches-3.18/361-MIPS-BCM63XX-add-raw-fallback-sproms-for-most-common.patch new file mode 100644 index 0000000..65c00b5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/361-MIPS-BCM63XX-add-raw-fallback-sproms-for-most-common.patch @@ -0,0 +1,181 @@ +From 7be5bb46003295c9e04fd4e795593b2deaacd783 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 22:33:38 +0200 +Subject: [PATCH 06/10] MIPS: BCM63XX: add raw fallback sproms for most common + ssb cards + +Add template sproms for BCM4306, BCM4318, BCM4321, BCM4322, and BCM43222. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 136 +++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 6 + + 2 files changed, 142 insertions(+) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -43,6 +43,122 @@ static __initconst struct ssb_sprom bcm6 + .boardflags_hi = 0x0000, + }; + ++ ++static __initconst u16 bcm4306_sprom[] = { ++ 0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002, ++ 0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3034, 0x14d4, ++ 0xfa91, 0xfe60, 0xffff, 0xffff, 0x004c, 0xffff, 0xffff, 0xffff, ++ 0x003e, 0x0a49, 0xff02, 0x0000, 0xff10, 0xffff, 0xffff, 0x0002, ++}; ++ ++static __initconst u16 bcm4318_sprom[] = { ++ 0x2001, 0x0000, 0x0449, 0x14e4, 0x4318, 0x8000, 0x0002, 0x0000, ++ 0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3046, 0x15a7, ++ 0xfab0, 0xfe97, 0xffff, 0xffff, 0x0048, 0xffff, 0xffff, 0xffff, ++ 0x003e, 0xea49, 0xff02, 0x0000, 0xff08, 0xffff, 0xffff, 0x0002, ++}; ++ ++static __initconst u16 bcm4321_sprom[] = { ++ 0x3001, 0x0000, 0x046c, 0x14e4, 0x4328, 0x8000, 0x0002, 0x0000, ++ 0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x0032, 0x4a01, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x2728, 0x5b5b, 0x222b, 0x5b5b, 0x1927, 0x5b5b, 0x1e36, ++ 0x5b5b, 0x303c, 0x3030, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x3e4c, 0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0x3e4c, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0008, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0004, ++}; ++ ++static __initconst u16 bcm4322_sprom[] = { ++ 0x3001, 0x0000, 0x04bc, 0x14e4, 0x432c, 0x8000, 0x0002, 0x0000, ++ 0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x1209, 0x0200, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0301, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x2048, 0xfe9a, 0x1571, 0xfabd, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x2048, 0xfeb9, 0x159f, 0xfadd, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x3333, 0x5555, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ ++static __initconst u16 bcm43222_sprom[] = { ++ 0x2001, 0x0000, 0x04d4, 0x14e4, 0x4351, 0x8000, 0x0002, 0x0000, ++ 0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x2305, 0x0200, 0x0000, 0x2400, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x204c, 0xfea6, 0x1717, 0xfa6d, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x204c, 0xfeb8, 0x167c, 0xfa9e, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x3333, 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, ++ 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ + static struct ssb_sprom bcm63xx_sprom; + + int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +@@ -542,6 +658,26 @@ int __init bcm63xx_register_fallback_spr + u16 size = 0; + + switch (data->type) { ++ case SPROM_BCM4306: ++ memcpy(&template_sprom, &bcm4306_sprom, sizeof(bcm4306_sprom)); ++ size = ARRAY_SIZE(bcm4306_sprom); ++ break; ++ case SPROM_BCM4318: ++ memcpy(&template_sprom, &bcm4318_sprom, sizeof(bcm4318_sprom)); ++ size = ARRAY_SIZE(bcm4318_sprom); ++ break; ++ case SPROM_BCM4321: ++ memcpy(&template_sprom, &bcm4321_sprom, sizeof(bcm4321_sprom)); ++ size = ARRAY_SIZE(bcm4321_sprom); ++ break; ++ case SPROM_BCM4322: ++ memcpy(&template_sprom, &bcm4322_sprom, sizeof(bcm4322_sprom)); ++ size = ARRAY_SIZE(bcm4322_sprom); ++ break; ++ case SPROM_BCM43222: ++ memcpy(&template_sprom, &bcm43222_sprom, sizeof(bcm43222_sprom)); ++ size = ARRAY_SIZE(bcm43222_sprom); ++ break; + case SPROM_DEFAULT: + memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, + sizeof(bcm63xx_sprom)); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -5,6 +5,12 @@ + + enum sprom_type { + SPROM_DEFAULT, /* default fallback sprom */ ++ /* SSB based */ ++ SPROM_BCM4306, ++ SPROM_BCM4318, ++ SPROM_BCM4321, ++ SPROM_BCM4322, ++ SPROM_BCM43222, + }; + + struct fallback_sprom_data { diff --git a/target/linux/brcm63xx/patches-3.18/362-MIPS-BCM63XX-also-register-a-fallback-sprom-for-bcma.patch b/target/linux/brcm63xx/patches-3.18/362-MIPS-BCM63XX-also-register-a-fallback-sprom-for-bcma.patch new file mode 100644 index 0000000..6475f9f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/362-MIPS-BCM63XX-also-register-a-fallback-sprom-for-bcma.patch @@ -0,0 +1,128 @@ +From 03feb9db77fba3eef3d83e17a87a56979659b248 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 22:48:26 +0200 +Subject: [PATCH 07/10] MIPS: BCM63XX: also register a fallback sprom for bcma + +Similar to SSB, register a fallback sprom handler for BCMA. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/Kconfig | 1 + + arch/mips/bcm63xx/sprom.c | 40 +++++++++++++++++++++++++++++++++++----- + 2 files changed, 36 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -4,6 +4,7 @@ menu "Board support" + config BOARD_BCM963XX + bool "Generic Broadcom 963xx boards" + select SSB ++ select BCMA + default y + help + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -21,7 +22,7 @@ + * Register a sane SPROMv2 to make the on-board + * bcm4318 WLAN work + */ +-#ifdef CONFIG_SSB_PCIHOST ++#if defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) + static __initconst struct ssb_sprom bcm63xx_default_sprom = { + .revision = 0x02, + .board_rev = 0x17, +@@ -43,7 +44,7 @@ static __initconst struct ssb_sprom bcm6 + .boardflags_hi = 0x0000, + }; + +- ++#if defined (CONFIG_SSB_PCIHOST) + static __initconst u16 bcm4306_sprom[] = { + 0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002, + 0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, +@@ -158,10 +159,12 @@ static __initconst u16 bcm43222_sprom[] + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0x0008, + }; ++#endif /* CONFIG_SSB_PCIHOST */ + + static struct ssb_sprom bcm63xx_sprom; + +-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) ++#if defined(CONFIG_SSB_PCIHOST) ++int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out) + { + if (bus->bustype == SSB_BUSTYPE_PCI) { + memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); +@@ -171,6 +174,20 @@ int bcm63xx_get_fallback_sprom(struct ss + return -EINVAL; + } + } ++#endif ++ ++#if defined(CONFIG_BCMA_HOST_PCI) ++int bcm63xx_get_fallback_bcma_sprom(struct bcma_bus *bus, struct ssb_sprom *out) ++{ ++ if (bus->hosttype == BCMA_HOSTTYPE_PCI) { ++ memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ return 0; ++ } else { ++ printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); ++ return -EINVAL; ++ } ++} ++#endif + + /* FIXME: use lib_sprom after submission upstream */ + +@@ -654,10 +671,11 @@ int __init bcm63xx_register_fallback_spr + { + int ret = 0; + +-#ifdef CONFIG_SSB_PCIHOST ++#if defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) + u16 size = 0; + + switch (data->type) { ++#if defined(CONFIG_SSB_PCIHOST) + case SPROM_BCM4306: + memcpy(&template_sprom, &bcm4306_sprom, sizeof(bcm4306_sprom)); + size = ARRAY_SIZE(bcm4306_sprom); +@@ -678,6 +696,7 @@ int __init bcm63xx_register_fallback_spr + memcpy(&template_sprom, &bcm43222_sprom, sizeof(bcm43222_sprom)); + size = ARRAY_SIZE(bcm43222_sprom); + break; ++#endif + case SPROM_DEFAULT: + memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, + sizeof(bcm63xx_sprom)); +@@ -692,8 +711,19 @@ int __init bcm63xx_register_fallback_spr + memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); ++#endif /* defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) */ ++ ++#if defined(CONFIG_SSB_PCIHOST) ++ ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_ssb_sprom); ++ if (ret) ++ return ret; ++ ++#endif + +- ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom); ++#if defined(CONFIG_BCMA_HOST_PCI) ++ ret = bcma_arch_register_fallback_sprom(bcm63xx_get_fallback_bcma_sprom); ++ if (ret) ++ return ret; + #endif + return ret; + } diff --git a/target/linux/brcm63xx/patches-3.18/363-MIPS-BCM63XX-add-BCMA-based-sprom-templates.patch b/target/linux/brcm63xx/patches-3.18/363-MIPS-BCM63XX-add-BCMA-based-sprom-templates.patch new file mode 100644 index 0000000..5c0abb9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/363-MIPS-BCM63XX-add-BCMA-based-sprom-templates.patch @@ -0,0 +1,303 @@ +From 27bf70e3fe797691b17df07ecbfaf9f5a4419f49 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Wed, 30 Jul 2014 23:14:27 +0200 +Subject: [PATCH 08/10] MIPS: BCM63XX: add BCMA based sprom templates + +Add fallback sproms for BCM4313, BCM43131, BCM43217, BCM43225, BCM43227, +BCM43228, and BCM4331. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 256 +++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 8 + + 2 files changed, 264 insertions(+) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -161,6 +161,226 @@ static __initconst u16 bcm43222_sprom[] + }; + #endif /* CONFIG_SSB_PCIHOST */ + ++#if defined(CONFIG_BCMA_HOST_PCI) ++static __initconst u16 bcm4313_sprom[] = { ++ 0x2801, 0x0000, 0x0510, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x4727, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1215, 0x2a00, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202, ++ 0xffff, 0x0011, 0x007a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0201, ++ 0x0000, 0x7800, 0x7c0a, 0x0398, 0x0008, 0x0000, 0x0000, 0x0000, ++ 0x0044, 0x1684, 0xfd0d, 0xff35, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0048, 0xfed2, 0x15d9, 0xfac6, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0008, ++}; ++ ++static __initconst u16 bcm43131_sprom[] = { ++ 0x2801, 0x0000, 0x05f7, 0x14e4, 0x0070, 0xedbe, 0x1c00, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x43aa, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1280, 0x0200, 0x0000, 0x8800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0002, 0x0202, ++ 0xffff, 0x0022, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415, ++ 0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666, ++ 0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ ++static __initconst u16 bcm43217_sprom[] = { ++ 0x2801, 0x0000, 0x05e9, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x43a9, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1252, 0x0200, 0x0000, 0x9800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202, ++ 0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415, ++ 0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666, ++ 0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x7a08, ++}; ++ ++static __initconst u16 bcm43225_sprom[] = { ++ 0x2801, 0x0000, 0x04da, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0x1008, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x4357, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x1200, 0x0200, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x88ff, 0xffff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325, ++ 0xffff, 0x7800, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x204e, 0xfead, 0x1611, 0xfa9a, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x204e, 0xfec1, 0x1674, 0xfab2, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x5555, 0x5555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555, ++ 0x7555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0002, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ ++static __initconst u16 bcm43227_sprom[] = { ++ 0x2801, 0x0000, 0x0543, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x4358, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1402, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202, ++ 0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415, ++ 0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xff36, 0x16d2, 0xfaae, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfeca, 0x159b, 0xfa80, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666, ++ 0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ ++static __initconst u16 bcm43228_sprom[] = { ++ 0x2801, 0x0000, 0x0011, 0x1028, 0x0070, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x4359, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1203, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0215, ++ 0x0215, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xff73, 0x1762, 0xfaa4, 0x3e34, 0x3434, 0xfea1, 0x154c, ++ 0xfad0, 0xfea1, 0x144c, 0xfafb, 0xfe7b, 0x13fe, 0xfafc, 0x0000, ++ 0x204c, 0xff41, 0x16a3, 0xfa8f, 0x3e34, 0x3434, 0xfe97, 0x1446, ++ 0xfb05, 0xfe97, 0x1346, 0xfb32, 0xfeb9, 0x1516, 0xfaee, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x8888, 0x8888, 0x8888, ++ 0x8888, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333, ++ 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333, ++ 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333, ++ 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xf008, ++}; ++ ++static __initconst u16 bcm4331_sprom[] = { ++ 0x2801, 0x0000, 0x0525, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0x1010, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x4331, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x1104, 0x0200, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0x88ff, 0xffff, 0x0707, 0x0202, ++ 0xff02, 0x0077, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325, ++ 0x0325, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x2048, 0xfe56, 0x16f2, 0xfa44, 0x3e3c, 0x3c3c, 0xfe77, 0x1657, ++ 0xfa75, 0xffff, 0xffff, 0xffff, 0xfe76, 0x15da, 0xfa85, 0x0000, ++ 0x2048, 0xfe5c, 0x16b5, 0xfa56, 0x3e3c, 0x3c3c, 0xfe7c, 0x169d, ++ 0xfa6b, 0xffff, 0xffff, 0xffff, 0xfe7a, 0x1597, 0xfa97, 0x0000, ++ 0x2048, 0xfe68, 0x1734, 0xfa46, 0x3e3c, 0x3c3c, 0xfe7f, 0x15e4, ++ 0xfa94, 0xffff, 0xffff, 0xffff, 0xfe7d, 0x1582, 0xfa9f, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0009, ++}; ++ ++#endif /* CONFIG_BCMA_HOST_PCI */ ++ + static struct ssb_sprom bcm63xx_sprom; + + #if defined(CONFIG_SSB_PCIHOST) +@@ -697,6 +917,42 @@ int __init bcm63xx_register_fallback_spr + size = ARRAY_SIZE(bcm43222_sprom); + break; + #endif ++#if defined(CONFIG_BCMA_HOST_PCI) ++ case SPROM_BCM4313: ++ memcpy(&template_sprom, &bcm4313_sprom, ++ sizeof(bcm4313_sprom)); ++ size = ARRAY_SIZE(bcm4313_sprom); ++ break; ++ case SPROM_BCM43131: ++ memcpy(&template_sprom, &bcm43131_sprom, ++ sizeof(bcm43131_sprom)); ++ size = ARRAY_SIZE(bcm43131_sprom); ++ break; ++ case SPROM_BCM43217: ++ memcpy(&template_sprom, &bcm43217_sprom, ++ sizeof(bcm43217_sprom)); ++ size = ARRAY_SIZE(bcm43217_sprom); ++ break; ++ case SPROM_BCM43225: ++ memcpy(&template_sprom, &bcm43225_sprom, ++ sizeof(bcm43225_sprom)); ++ size = ARRAY_SIZE(bcm43225_sprom); ++ break; ++ case SPROM_BCM43227: ++ memcpy(&template_sprom, &bcm43227_sprom, ++ sizeof(bcm43227_sprom)); ++ size = ARRAY_SIZE(bcm43227_sprom); ++ break; ++ case SPROM_BCM43228: ++ memcpy(&template_sprom, &bcm43228_sprom, ++ sizeof(bcm43228_sprom)); ++ size = ARRAY_SIZE(bcm43228_sprom); ++ break; ++ case SPROM_BCM4331: ++ memcpy(&template_sprom, &bcm4331_sprom, sizeof(&bcm4331_sprom)); ++ size = ARRAY_SIZE(bcm4331_sprom); ++ break; ++#endif + case SPROM_DEFAULT: + memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, + sizeof(bcm63xx_sprom)); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -11,6 +11,14 @@ enum sprom_type { + SPROM_BCM4321, + SPROM_BCM4322, + SPROM_BCM43222, ++ /* BCMA based */ ++ SPROM_BCM4313, ++ SPROM_BCM43131, ++ SPROM_BCM43217, ++ SPROM_BCM43225, ++ SPROM_BCM43227, ++ SPROM_BCM43228, ++ SPROM_BCM4331, + }; + + struct fallback_sprom_data { diff --git a/target/linux/brcm63xx/patches-3.18/364-MIPS-BCM63XX-allow-board-files-to-provide-sprom-fixu.patch b/target/linux/brcm63xx/patches-3.18/364-MIPS-BCM63XX-allow-board-files-to-provide-sprom-fixu.patch new file mode 100644 index 0000000..74c2846 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/364-MIPS-BCM63XX-allow-board-files-to-provide-sprom-fixu.patch @@ -0,0 +1,67 @@ +From 8575548b08e33c9ff4fd540abec09dd177e33682 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 31 Jul 2014 19:12:33 +0200 +Subject: [PATCH 09/10] MIPS: BCM63XX: allow board files to provide sprom + fixups + +Allow board_info files to supply fixups for the base sproms to adapt +them to the actual used sprom contents in case they do not use the +default ones. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 14 +++++++++++++- + .../mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 8 ++++++++ + 2 files changed, 21 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -883,6 +883,14 @@ static int sprom_extract(struct ssb_spro + return 0; + } + ++void sprom_apply_fixups(u16 *sprom, struct sprom_fixup *fixups, int n) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < n; i++) ++ sprom[fixups[i].offset] = fixups[i].value; ++} ++ + static __initdata u16 template_sprom[220]; + #endif + +@@ -961,8 +969,12 @@ int __init bcm63xx_register_fallback_spr + return -EINVAL; + } + +- if (size > 0) ++ if (size > 0) { ++ sprom_apply_fixups(template_sprom, data->board_fixups, ++ data->num_board_fixups); ++ + sprom_extract(&bcm63xx_sprom, template_sprom, size); ++ } + + memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -21,9 +21,17 @@ enum sprom_type { + SPROM_BCM4331, + }; + ++struct sprom_fixup { ++ u16 offset; ++ u16 value; ++}; ++ + struct fallback_sprom_data { + u8 mac_addr[ETH_ALEN]; + enum sprom_type type; ++ ++ struct sprom_fixup *board_fixups; ++ unsigned int num_board_fixups; + }; + + int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data); diff --git a/target/linux/brcm63xx/patches-3.18/365-MIPS-BCM63XX-allow-setting-a-pci-bus-device-for-fall.patch b/target/linux/brcm63xx/patches-3.18/365-MIPS-BCM63XX-allow-setting-a-pci-bus-device-for-fall.patch new file mode 100644 index 0000000..40591e5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/365-MIPS-BCM63XX-allow-setting-a-pci-bus-device-for-fall.patch @@ -0,0 +1,102 @@ +From f393eaacf178e7e8a61eb11a96edd7dfb35cb49d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 31 Jul 2014 20:39:44 +0200 +Subject: [PATCH 10/10] MIPS: BCM63XX: allow setting a pci bus/device for + fallback sprom + +Warn if the set pci bus/slot does not match the actual request. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 31 ++++++++++++++++++---- + .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 3 +++ + 2 files changed, 29 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -381,13 +381,25 @@ static __initconst u16 bcm4331_sprom[] = + + #endif /* CONFIG_BCMA_HOST_PCI */ + +-static struct ssb_sprom bcm63xx_sprom; ++struct fallback_sprom_match { ++ u8 pci_bus; ++ u8 pci_dev; ++ struct ssb_sprom sprom; ++}; ++ ++static struct fallback_sprom_match fallback_sprom; + + #if defined(CONFIG_SSB_PCIHOST) + int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out) + { + if (bus->bustype == SSB_BUSTYPE_PCI) { +- memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ if (bus->host_pci->bus->number != fallback_sprom.pci_bus || ++ PCI_SLOT(bus->host_pci->devfn) != fallback_sprom.pci_dev) ++ pr_warn("ssb_fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\n", ++ fallback_sprom.pci_bus, fallback_sprom.pci_dev, ++ bus->host_pci->bus->number, ++ PCI_SLOT(bus->host_pci->devfn)); ++ memcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom)); + return 0; + } else { + printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); +@@ -400,7 +412,13 @@ int bcm63xx_get_fallback_ssb_sprom(struc + int bcm63xx_get_fallback_bcma_sprom(struct bcma_bus *bus, struct ssb_sprom *out) + { + if (bus->hosttype == BCMA_HOSTTYPE_PCI) { +- memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ if (bus->host_pci->bus->number != fallback_sprom.pci_bus || ++ PCI_SLOT(bus->host_pci->devfn) != fallback_sprom.pci_dev) ++ pr_warn("bcma_fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\n", ++ fallback_sprom.pci_bus, fallback_sprom.pci_dev, ++ bus->host_pci->bus->number, ++ PCI_SLOT(bus->host_pci->devfn)); ++ memcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom)); + return 0; + } else { + printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); +@@ -962,8 +980,8 @@ int __init bcm63xx_register_fallback_spr + break; + #endif + case SPROM_DEFAULT: +- memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, +- sizeof(bcm63xx_sprom)); ++ memcpy(&fallback_sprom.sprom, &bcm63xx_default_sprom, ++ sizeof(bcm63xx_default_sprom)); + break; + default: + return -EINVAL; +@@ -973,12 +991,15 @@ int __init bcm63xx_register_fallback_spr + sprom_apply_fixups(template_sprom, data->board_fixups, + data->num_board_fixups); + +- sprom_extract(&bcm63xx_sprom, template_sprom, size); ++ sprom_extract(&fallback_sprom.sprom, template_sprom, size); + } + +- memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); +- memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); +- memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); ++ memcpy(fallback_sprom.sprom.il0mac, data->mac_addr, ETH_ALEN); ++ memcpy(fallback_sprom.sprom.et0mac, data->mac_addr, ETH_ALEN); ++ memcpy(fallback_sprom.sprom.et1mac, data->mac_addr, ETH_ALEN); ++ ++ fallback_sprom.pci_bus = data->pci_bus; ++ fallback_sprom.pci_dev = data->pci_dev; + #endif /* defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) */ + + #if defined(CONFIG_SSB_PCIHOST) +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -30,6 +30,9 @@ struct fallback_sprom_data { + u8 mac_addr[ETH_ALEN]; + enum sprom_type type; + ++ u8 pci_bus; ++ u8 pci_dev; ++ + struct sprom_fixup *board_fixups; + unsigned int num_board_fixups; + }; diff --git a/target/linux/brcm63xx/patches-3.18/366-MIPS-add-support-for-vmlinux.bin-appended-DTB.patch b/target/linux/brcm63xx/patches-3.18/366-MIPS-add-support-for-vmlinux.bin-appended-DTB.patch new file mode 100644 index 0000000..ff455dd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/366-MIPS-add-support-for-vmlinux.bin-appended-DTB.patch @@ -0,0 +1,124 @@ +From 318c1fce4aeef298cbb6153416c499c94ad7cda0 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 24 Jun 2014 10:53:15 +0200 +Subject: [PATCH RFC v3] MIPS: add support for vmlinux.bin appended DTB + +Add support for populating initial_boot_params through a dtb +blob appended to raw vmlinux.bin. + +Signed-off-by: Jonas Gorski +--- +Changes RFC v2 -> v3 + +* fixed !smp kernels (TODO: move it to its own patch + +Changes RFC v1 -> v2 + +* changed all occurences of vmlinux to vmlinux.bin +* clarified this applies to the raw vmlinux.bin without decompressor +* s/initial_device_params/initial_boot_params/ + +Initial comments by me still valid: + +Mostly adapted from how ARM is doing it. + +Sent as an RFC PATCH because I am not sure if this is the right way to +it, and whether storing the pointer in initial_boot_params is a good +idea, or a new variable should be introduced. + +The reasoning for initial_boot_params is that there is no common +MIPS interface yet, so the next best thing was using that. This also +has the advantage of keeping the original fw_args intact. + +This patch works for me on bcm63xx, where the bootloader expects +an lzma compressed kernel, so I didn't want to double compress using +the in-kernel compressed kernel support. + +Completely untested on anything except MIPS32 / big endian. + + arch/mips/Kconfig | 18 ++++++++++++++++++ + arch/mips/kernel/head.S | 19 +++++++++++++++++++ + arch/mips/kernel/vmlinux.lds.S | 7 +++++++ + 3 files changed, 43 insertions(+) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2655,6 +2655,24 @@ config RAPIDIO + + source "drivers/rapidio/Kconfig" + ++config MIPS_APPENDED_DTB ++ bool "Use appended device tree blob to vmlinux.bin (EXPERIMENTAL)" ++ depends on OF ++ help ++ With this option, the boot code will look for a device tree binary ++ DTB) appended to raw vmlinux.bin (without decompressor). ++ (e.g. cat vmlinux.bin .dtb > vmlinux_w_dtb). ++ ++ This is meant as a backward compatibility convenience for those ++ systems with a bootloader that can't be upgraded to accommodate ++ the documented boot protocol using a device tree. ++ ++ Beware that there is very little in terms of protection against ++ this option being confused by leftover garbage in memory that might ++ look like a DTB header after a reboot if no actual DTB is appended ++ to vmlinux.bin. Do not leave this option active in a production kernel ++ if you don't intend to always append a DTB. ++ + endmenu + + menu "Executable file formats" +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -100,6 +100,22 @@ NESTED(kernel_entry, 16, sp) # kernel + jr t0 + 0: + ++#ifdef CONFIG_MIPS_APPENDED_DTB ++ PTR_LA t0, __appended_dtb ++ PTR_LI t3, 0 ++ ++#ifdef CONFIG_CPU_BIG_ENDIAN ++ PTR_LI t1, 0xd00dfeed ++#else ++ PTR_LI t1, 0xedfe0dd0 ++#endif ++ LONG_L t2, (t0) ++ bne t1, t2, not_found ++ ++ PTR_LA t3, __appended_dtb ++ ++not_found: ++#endif + PTR_LA t0, __bss_start # clear .bss + LONG_S zero, (t0) + PTR_LA t1, __bss_stop - LONGSIZE +@@ -113,6 +129,10 @@ NESTED(kernel_entry, 16, sp) # kernel + LONG_S a2, fw_arg2 + LONG_S a3, fw_arg3 + ++#ifdef CONFIG_MIPS_APPENDED_DTB ++ LONG_S t3, initial_boot_params ++#endif ++ + MTC0 zero, CP0_CONTEXT # clear context register + PTR_LA $28, init_thread_union + /* Set the SP after an empty pt_regs. */ +--- a/arch/mips/kernel/vmlinux.lds.S ++++ b/arch/mips/kernel/vmlinux.lds.S +@@ -125,8 +125,14 @@ SECTIONS + .exit.data : { + EXIT_DATA + } +- ++#ifdef CONFIG_SMP + PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT) ++#endif ++#ifdef CONFIG_MIPS_APPENDED_DTB ++ __appended_dtb = .; ++ /* leave space for appended DTB */ ++ . = . + 0x100000; ++#endif + /* + * Align to 64K in attempt to eliminate holes before the + * .bss..swapper_pg_dir section at the start of .bss. This diff --git a/target/linux/brcm63xx/patches-3.18/367-MIPS-BCM63XX-add-support-for-loading-DTB.patch b/target/linux/brcm63xx/patches-3.18/367-MIPS-BCM63XX-add-support-for-loading-DTB.patch new file mode 100644 index 0000000..577df55 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/367-MIPS-BCM63XX-add-support-for-loading-DTB.patch @@ -0,0 +1,96 @@ +From db896341299cbcb703821228574ba9b79b6a3565 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 24 Jun 2014 10:57:51 +0200 +Subject: [PATCH 45/48] MIPS: BCM63XX: add support for loading DTB + +--- + arch/mips/bcm63xx/boards/Kconfig | 4 ++++ + arch/mips/bcm63xx/boards/board_common.c | 34 +++++++++++++++++++++++++++++++++ + 2 files changed, 38 insertions(+) + +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -1,6 +1,10 @@ + menu "Board support" + depends on BCM63XX + ++config BOARD_BCM63XX_DT ++ bool "Device Tree boards (experimential)" ++ select USE_OF ++ + config BOARD_BCM963XX + bool "Generic Broadcom 963xx boards" + select SSB +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -10,6 +10,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -17,6 +19,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -129,8 +132,23 @@ void __init board_setup(void) + /* make sure we're running on expected cpu */ + if (bcm63xx_get_cpu_id() != board.expected_cpu_id) + panic("unexpected CPU for bcm963xx board"); ++ ++#if CONFIG_OF ++ if (initial_boot_params) ++ __dt_setup_arch(initial_boot_params); ++#endif + } + ++#if CONFIG_OF ++void __init device_tree_init(void) ++{ ++ if (!initial_boot_params) ++ return; ++ ++ unflatten_and_copy_device_tree(); ++} ++#endif ++ + static struct gpio_led_platform_data bcm63xx_led_data; + + static struct platform_device bcm63xx_gpio_leds = { +@@ -149,6 +167,13 @@ static struct platform_device bcm63xx_gp + .dev.platform_data = &bcm63xx_gpio_keys_data, + }; + ++#if CONFIG_OF ++static struct of_device_id of_ids[] = { ++ { /* filled at runtime */ }, ++ { .compatible = "simple-bus" }, ++ { }, ++}; ++#endif + /* + * third stage init callback, register all board devices. + */ +@@ -158,6 +183,15 @@ int __init board_register_devices(void) + int led_count = 0; + int usbh_ports = 0; + ++#if CONFIG_OF ++ if (of_have_populated_dt()) { ++ snprintf(of_ids[0].compatible, sizeof(of_ids[0].compatible), ++ "brcm,bcm%x", bcm63xx_get_cpu_id()); ++ ++ of_platform_populate(NULL, of_ids, NULL, NULL); ++ } ++#endif ++ + if (board.has_uart0) + bcm63xx_uart_register(0); + diff --git a/target/linux/brcm63xx/patches-3.18/368-MIPS-BCM63XX-add-support-for-matching-the-board_info.patch b/target/linux/brcm63xx/patches-3.18/368-MIPS-BCM63XX-add-support-for-matching-the-board_info.patch new file mode 100644 index 0000000..58ffe5e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/368-MIPS-BCM63XX-add-support-for-matching-the-board_info.patch @@ -0,0 +1,95 @@ +From 25bf2b5836c892f091651d8a3384c9c57ce1b400 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 26 Jun 2014 12:51:00 +0200 +Subject: [PATCH 46/48] MIPS: BCM63XX: add support for matching the board_info + by dtb + +Allow using the passed dtb's compatible property to match board_info +structs instead of nvram's boardname field, which is not unique anyway. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 15 +++++++++++++++ + arch/mips/bcm63xx/boards/board_common.c | 18 ++++++++++++++++++ + arch/mips/bcm63xx/boards/board_common.h | 3 +++ + 3 files changed, 36 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -715,6 +715,10 @@ static const struct board_info __initcon + #endif + }; + ++static struct of_device_id const bcm963xx_boards_dt[] = { ++ { }, ++}; ++ + /* + * early init callback, read nvram data from flash and checksum it + */ +@@ -726,6 +730,7 @@ void __init board_bcm963xx_init(void) + char *board_name = NULL; + u32 val; + struct bcm_hcs *hcs; ++ const struct of_device_id *board_match; + + /* read base address of boot chip select (0) + * 6328/6362 do not have MPI but boot from a fixed address +@@ -765,6 +770,16 @@ void __init board_bcm963xx_init(void) + } else { + board_name = bcm63xx_nvram_get_name(); + } ++ ++ /* find board by compat */ ++ board_match = bcm63xx_match_board(bcm963xx_boards_dt); ++ if (board_match) { ++ board_early_setup(board_match->data, ++ bcm63xx_nvram_get_mac_address); ++ ++ return; ++ } ++ + /* find board by name */ + for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) { + if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -281,3 +281,21 @@ int __init board_register_devices(void) + + return 0; + } ++ ++const struct of_device_id * __init bcm63xx_match_board(const struct of_device_id *m) ++{ ++ const struct of_device_id *match; ++ unsigned long dt_root; ++ ++ if (!IS_ENABLED(CONFIG_OF) || !initial_boot_params) ++ return NULL; ++ ++ dt_root = of_get_flat_dt_root(); ++ ++ for (match = m; match->compatible[0]; match++) { ++ if (of_flat_dt_is_compatible(dt_root, match->compatible)) ++ return match; ++ } ++ ++ return NULL; ++} +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -1,11 +1,14 @@ + #ifndef __BOARD_COMMON_H + #define __BOARD_COMMON_H + ++#include + #include + + void board_early_setup(const struct board_info *board, + int (*get_mac_address)(u8 mac[ETH_ALEN])); + ++const struct of_device_id *bcm63xx_match_board(const struct of_device_id *); ++ + #if defined(CONFIG_BOARD_BCM963XX) + void board_bcm963xx_init(void); + #else diff --git a/target/linux/brcm63xx/patches-3.18/369-MIPS-BCM63XX-populate-the-compatible-to-board_info-l.patch b/target/linux/brcm63xx/patches-3.18/369-MIPS-BCM63XX-populate-the-compatible-to-board_info-l.patch new file mode 100644 index 0000000..9c5688c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/369-MIPS-BCM63XX-populate-the-compatible-to-board_info-l.patch @@ -0,0 +1,65 @@ +From e71eea9953c774dfadb754258824fb1888c279f4 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 21 Nov 2014 16:54:06 +0100 +Subject: [PATCH 47/48] MIPS: BCM63XX: populate the compatible to board_info + list + +Populate the compatible to board_info list to allow dtbs to be used +for known boards. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 34 +++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -716,6 +716,48 @@ static const struct board_info __initcon + }; + + static struct of_device_id const bcm963xx_boards_dt[] = { ++#ifdef CONFIG_OF ++#ifdef CONFIG_BCM63XX_CPU_3368 ++ { .compatible = "netgear,cvg834g", .data = &board_cvg834g, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6328 ++ { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6338 ++ { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, ++ { .compatible = "brcm,bcm96338w", .data = &board_96338w, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6345 ++ { .compatible = "brcm,bcm96345gw2", .data = &board_96345gw2, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6348 ++ { .compatible = "belkin,f5d7633", .data = &board_96348gw_10, }, ++ { .compatible = "brcm,bcm96348r", .data = &board_96348r, }, ++ { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, ++ { .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, }, ++ { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, ++ { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, ++ { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, ++ { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, ++ { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, ++ { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, ++ { .compatible = "usr,9108", .data = &board_96348gw_a, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6358 ++ { .compatible = "alcatel,rg100a", .data = &board_96358vw2, }, ++ { .compatible = "brcm,bcm96358vw", .data = &board_96358vw, }, ++ { .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, }, ++ { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, ++ { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, ++ { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, ++ { .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, }, ++ { .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6368 ++#endif ++#ifdef CONFIG_BCM63XX_CPU_63268 ++#endif ++#endif /* CONFIG_OF */ + { }, + }; + diff --git a/target/linux/brcm63xx/patches-3.18/371_add_of_node_available_by_alias.patch b/target/linux/brcm63xx/patches-3.18/371_add_of_node_available_by_alias.patch new file mode 100644 index 0000000..99d778d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/371_add_of_node_available_by_alias.patch @@ -0,0 +1,37 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -147,6 +147,18 @@ void __init device_tree_init(void) + + unflatten_and_copy_device_tree(); + } ++ ++int board_of_device_present(const char *alias) ++{ ++ bool present; ++ struct device_node *np; ++ ++ np = of_find_node_by_path(alias); ++ present = of_device_is_available(np); ++ of_node_put(np); ++ ++ return present; ++} + #endif + + static struct gpio_led_platform_data bcm63xx_led_data; +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -15,4 +15,13 @@ void board_bcm963xx_init(void); + static inline void board_bcm963xx_init(void) { } + #endif + ++#if defined(CONFIG_OF) ++int board_of_device_present(const char *alias); ++#else ++static inline void board_of_device_present(const char *alias) ++{ ++ return 0; ++} ++#endif ++ + #endif /* __BOARD_COMMON_H */ diff --git a/target/linux/brcm63xx/patches-3.18/372_dont_register_pflash_when_available_in_dtb.patch b/target/linux/brcm63xx/patches-3.18/372_dont_register_pflash_when_available_in_dtb.patch new file mode 100644 index 0000000..25384eb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/372_dont_register_pflash_when_available_in_dtb.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -23,6 +23,8 @@ + #include + #include + ++#include "boards/board_common.h" ++ + static int flash_type; + + static struct mtd_partition mtd_partitions[] = { +@@ -178,6 +180,9 @@ int __init bcm63xx_flash_register(void) + + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: ++ /* don't register when already registered through from dtb */ ++ if (board_of_device_present("pflash")) ++ return 0; + + if (!mtd_resources[0].start) { + /* read base address of boot chip select (0) */ diff --git a/target/linux/brcm63xx/patches-3.18/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch b/target/linux/brcm63xx/patches-3.18/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch new file mode 100644 index 0000000..edc05d9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch @@ -0,0 +1,38 @@ +From 8a0803979163c647736cb234ee1620c049c4915c Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 1 Dec 2014 00:20:07 +0100 +Subject: [PATCH 5/5] MIPS: BCM63XX: register interrupt controllers through DT + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/irq.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -15,6 +15,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -190,7 +192,15 @@ static void bcm63xx_init_irq(void) + ext_shift); + } + ++OF_DECLARE_2(irqchip, mips_cpu_intc, "mti,cpu-interrupt-controller", ++ mips_cpu_irq_of_init); ++ + void __init arch_init_irq(void) + { +- bcm63xx_init_irq(); ++#ifdef CONFIG_OF ++ if (initial_boot_params) ++ irqchip_init(); ++ else ++#endif ++ bcm63xx_init_irq(); + } diff --git a/target/linux/brcm63xx/patches-3.18/374-gpio-add-a-simple-GPIO-driver-for-bcm63xx.patch b/target/linux/brcm63xx/patches-3.18/374-gpio-add-a-simple-GPIO-driver-for-bcm63xx.patch new file mode 100644 index 0000000..3e53c80 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/374-gpio-add-a-simple-GPIO-driver-for-bcm63xx.patch @@ -0,0 +1,166 @@ +From dbe94a8daaa63ef81b7414f2a17bca8e36dd6daa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 20 Feb 2015 19:55:32 +0100 +Subject: [PATCH 1/6] gpio: add a simple GPIO driver for bcm63xx + + +Signed-off-by: Jonas Gorski +--- + drivers/gpio/Kconfig | 8 +++ + drivers/gpio/Makefile | 1 + + drivers/gpio/gpio-bcm63xx.c | 122 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 131 insertions(+) + create mode 100644 drivers/gpio/gpio-bcm63xx.c + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -892,6 +892,14 @@ config GPIO_BCM_KONA + help + Turn on GPIO support for Broadcom "Kona" chips. + ++config GPIO_BCM63XX ++ bool "Broadcom BCM63XX GPIO" ++ depends on MIPS || COMPILE_TEST ++ select GPIO_GENERIC ++ help ++ Turn on GPIO support for Broadcom BCM63XX xDSL chips. ++ ++ + comment "USB GPIO expanders:" + + config GPIO_VIPERBOARD +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_GPIO_ADP5588) += gpio-adp55 + obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o + obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o + obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o ++obj-$(CONFIG_GPIO_BCM63XX) += gpio-bcm63xx.o + obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o + obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o + obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o +--- /dev/null ++++ b/drivers/gpio/gpio-bcm63xx.c +@@ -0,0 +1,122 @@ ++/* ++ * Driver for BCM63XX memory-mapped GPIO controllers, based on ++ * Generic driver for memory-mapped GPIO controllers. ++ * ++ * Copyright 2008 MontaVista Software, Inc. ++ * Copyright 2008,2010 Anton Vorontsov ++ * Copyright 2015 Jonas Gorski ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int bcm63xx_gpio_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct resource *dat_r, *dirout_r; ++ void __iomem *dat; ++ void __iomem *dirout; ++ unsigned long sz; ++ int err; ++ struct bgpio_chip *bgc; ++ struct bgpio_pdata *pdata = dev_get_platdata(dev); ++ ++ dirout_r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dat_r = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!dat_r || !dirout_r) ++ return -EINVAL; ++ ++ if (resource_size(dat_r) != resource_size(dirout_r)) ++ return -EINVAL; ++ ++ sz = resource_size(dat_r); ++ ++ dat = devm_ioremap_resource(dev, dat_r); ++ if (IS_ERR(dat)) ++ return PTR_ERR(dat); ++ ++ dirout = devm_ioremap_resource(dev, dirout_r); ++ if (IS_ERR(dirout)) ++ return PTR_ERR(dirout); ++ ++ bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL); ++ if (!bgc) ++ return -ENOMEM; ++ ++ err = bgpio_init(bgc, dev, sz, dat, NULL, NULL, dirout, NULL, ++ BGPIOF_BIG_ENDIAN_BYTE_ORDER); ++ if (err) ++ return err; ++ ++ platform_set_drvdata(pdev, bgc); ++ ++ if (dev->of_node) { ++ int id = of_alias_get_id(dev->of_node, "gpio"); ++ u32 ngpios; ++ ++ if (id >= 0) ++ bgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, ++ "bcm63xx-gpio.%d", id); ++ ++ if (!of_property_read_u32(dev->of_node, "ngpios", &ngpios)) ++ bgc->gc.ngpio = ngpios; ++ ++ } else if (pdata) { ++ bgc->gc.base = pdata->base; ++ if (pdata->ngpio > 0) ++ bgc->gc.ngpio = pdata->ngpio; ++ } ++ ++ return gpiochip_add(&bgc->gc); ++} ++ ++static int bcm63xx_gpio_remove(struct platform_device *pdev) ++{ ++ struct bgpio_chip *bgc = platform_get_drvdata(pdev); ++ ++ return bgpio_remove(bgc); ++} ++ ++#ifdef CONFIG_OF ++static struct of_device_id bcm63xx_gpio_of_match[] = { ++ { .compatible = "brcm,bcm6345-gpio" }, ++ { }, ++}; ++#endif ++ ++static struct platform_driver bcm63xx_gpio_driver = { ++ .probe = bcm63xx_gpio_probe, ++ .remove = bcm63xx_gpio_remove, ++ .driver = { ++ .name = "bcm63xx-gpio", ++ .of_match_table = of_match_ptr(bcm63xx_gpio_of_match), ++ }, ++}; ++ ++module_platform_driver(bcm63xx_gpio_driver); ++ ++MODULE_DESCRIPTION("Driver for BCM63XX memory-mapped GPIO controllers"); ++MODULE_AUTHOR("Jonas Gorski "); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm63xx/patches-3.18/375-MIPS-BCM63XX-switch-to-new-gpio-driver.patch b/target/linux/brcm63xx/patches-3.18/375-MIPS-BCM63XX-switch-to-new-gpio-driver.patch new file mode 100644 index 0000000..baf97b2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/375-MIPS-BCM63XX-switch-to-new-gpio-driver.patch @@ -0,0 +1,216 @@ +From cc99dca188bb63ba390008e2f7fa62d0300233e0 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 20 Feb 2015 23:58:54 +0100 +Subject: [PATCH 2/6] MIPS: BCM63XX: switch to new gpio driver + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_common.c | 2 + + arch/mips/bcm63xx/gpio.c | 147 +++++++------------------------ + arch/mips/bcm63xx/setup.c | 3 - + 3 files changed, 33 insertions(+), 119 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -204,6 +204,8 @@ int __init board_register_devices(void) + } + #endif + ++ bcm63xx_gpio_init(); ++ + if (board.has_uart0) + bcm63xx_uart_register(0); + +--- a/arch/mips/bcm63xx/gpio.c ++++ b/arch/mips/bcm63xx/gpio.c +@@ -5,147 +5,62 @@ + * + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2008-2011 Florian Fainelli ++ * Copyright (C) Jonas Gorski + */ + + #include +-#include +-#include + #include ++#include + #include + + #include + #include +-#include + #include + +-static u32 gpio_out_low_reg; +- +-static void bcm63xx_gpio_out_low_reg_init(void) ++static void __init bcm63xx_gpio_init_one(int id, int dir, int data, int ngpio) + { +- switch (bcm63xx_get_cpu_id()) { +- case BCM6345_CPU_ID: +- gpio_out_low_reg = GPIO_DATA_LO_REG_6345; +- break; +- default: +- gpio_out_low_reg = GPIO_DATA_LO_REG; +- break; +- } +-} +- +-static DEFINE_SPINLOCK(bcm63xx_gpio_lock); +-static u32 gpio_out_low, gpio_out_high; ++ struct resource res[2]; ++ struct bgpio_pdata pdata; + +-static void bcm63xx_gpio_set(struct gpio_chip *chip, +- unsigned gpio, int val) +-{ +- u32 reg; +- u32 mask; +- u32 *v; +- unsigned long flags; +- +- if (gpio >= chip->ngpio) +- BUG(); +- +- if (gpio < 32) { +- reg = gpio_out_low_reg; +- mask = 1 << gpio; +- v = &gpio_out_low; +- } else { +- reg = GPIO_DATA_HI_REG; +- mask = 1 << (gpio - 32); +- v = &gpio_out_high; +- } +- +- spin_lock_irqsave(&bcm63xx_gpio_lock, flags); +- if (val) +- *v |= mask; +- else +- *v &= ~mask; +- bcm_gpio_writel(*v, reg); +- spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags); +-} ++ memset(res, 0, sizeof(res)); ++ memset(&pdata, 0, sizeof(pdata)); + +-static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio) +-{ +- u32 reg; +- u32 mask; ++ res[0].flags = IORESOURCE_MEM; ++ res[0].start = bcm63xx_regset_address(RSET_GPIO); ++ res[0].start += dir; + +- if (gpio >= chip->ngpio) +- BUG(); ++ res[0].end = res[0].start + 3; + +- if (gpio < 32) { +- reg = gpio_out_low_reg; +- mask = 1 << gpio; +- } else { +- reg = GPIO_DATA_HI_REG; +- mask = 1 << (gpio - 32); +- } ++ res[1].flags = IORESOURCE_MEM; ++ res[1].start = bcm63xx_regset_address(RSET_GPIO); ++ res[1].start += data; + +- return !!(bcm_gpio_readl(reg) & mask); +-} ++ res[1].end = res[1].start + 3; + +-static int bcm63xx_gpio_set_direction(struct gpio_chip *chip, +- unsigned gpio, int dir) +-{ +- u32 reg; +- u32 mask; +- u32 tmp; +- unsigned long flags; +- +- if (gpio >= chip->ngpio) +- BUG(); +- +- if (gpio < 32) { +- reg = GPIO_CTL_LO_REG; +- mask = 1 << gpio; +- } else { +- reg = GPIO_CTL_HI_REG; +- mask = 1 << (gpio - 32); +- } +- +- spin_lock_irqsave(&bcm63xx_gpio_lock, flags); +- tmp = bcm_gpio_readl(reg); +- if (dir == BCM63XX_GPIO_DIR_IN) +- tmp &= ~mask; +- else +- tmp |= mask; +- bcm_gpio_writel(tmp, reg); +- spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags); ++ pdata.base = id * 32; ++ pdata.ngpio = ngpio; + +- return 0; ++ platform_device_register_resndata(NULL, "bcm63xx-gpio", id, res, 2, ++ &pdata, sizeof(pdata)); + } + +-static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) ++int __init bcm63xx_gpio_init(void) + { +- return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_IN); +-} ++ int ngpio = bcm63xx_gpio_count(); ++ int data_low_reg; + +-static int bcm63xx_gpio_direction_output(struct gpio_chip *chip, +- unsigned gpio, int value) +-{ +- bcm63xx_gpio_set(chip, gpio, value); +- return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_OUT); +-} ++ if (BCMCPU_IS_6345()) ++ data_low_reg = GPIO_DATA_LO_REG_6345; ++ else ++ data_low_reg = GPIO_DATA_LO_REG; + ++ bcm63xx_gpio_init_one(0, GPIO_CTL_LO_REG, data_low_reg, min(ngpio, 32)); + +-static struct gpio_chip bcm63xx_gpio_chip = { +- .label = "bcm63xx-gpio", +- .direction_input = bcm63xx_gpio_direction_input, +- .direction_output = bcm63xx_gpio_direction_output, +- .get = bcm63xx_gpio_get, +- .set = bcm63xx_gpio_set, +- .base = 0, +-}; ++ if (ngpio <= 32) ++ return 0; + +-int __init bcm63xx_gpio_init(void) +-{ +- bcm63xx_gpio_out_low_reg_init(); ++ bcm63xx_gpio_init_one(1, GPIO_CTL_HI_REG, GPIO_DATA_HI_REG, ngpio - 32); + +- gpio_out_low = bcm_gpio_readl(gpio_out_low_reg); +- if (!BCMCPU_IS_6345()) +- gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG); +- bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count(); +- pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio); ++ return 0; + +- return gpiochip_add(&bcm63xx_gpio_chip); + } +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -164,9 +164,6 @@ void __init plat_mem_setup(void) + + int __init bcm63xx_register_devices(void) + { +- /* register gpiochip */ +- bcm63xx_gpio_init(); +- + return board_register_devices(); + } + diff --git a/target/linux/brcm63xx/patches-3.18/376-net-bcm63xx_enet-use-named-gpio-for-ephy-reset-gpio.patch b/target/linux/brcm63xx/patches-3.18/376-net-bcm63xx_enet-use-named-gpio-for-ephy-reset-gpio.patch new file mode 100644 index 0000000..6d19cc0 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/376-net-bcm63xx_enet-use-named-gpio-for-ephy-reset-gpio.patch @@ -0,0 +1,46 @@ +From ec905f2ea78ec40602a685ede31c5e4f9893d196 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Feb 2015 16:35:07 +0100 +Subject: [PATCH 3/6] net: bcm63xx_enet: use named gpio for ephy reset gpio + +Allow using a named optional gpio for ephy reset gpio registration. +--- + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + #include "bcm63xx_enet.h" +@@ -2848,10 +2849,15 @@ static int bcm_enet_shared_probe(struct + { + struct resource *res; + void __iomem *p[3]; ++ struct gpio_desc *ephy_reset; + unsigned int i; + + memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base)); + ++ ephy_reset = devm_gpiod_get_optional(&pdev->dev, "ephy-reset"); ++ if (IS_ERR(ephy_reset)) ++ return PTR_ERR(ephy_reset); ++ + for (i = 0; i < 3; i++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + p[i] = devm_ioremap_resource(&pdev->dev, res); +@@ -2861,6 +2867,9 @@ static int bcm_enet_shared_probe(struct + + memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base)); + ++ if (ephy_reset) ++ gpiod_direction_output(ephy_reset, 0); ++ + return 0; + } + diff --git a/target/linux/brcm63xx/patches-3.18/377-MIPS-BCM63XX-register-lookup-for-ephy-reset-gpio.patch b/target/linux/brcm63xx/patches-3.18/377-MIPS-BCM63XX-register-lookup-for-ephy-reset-gpio.patch new file mode 100644 index 0000000..30f6ba5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/377-MIPS-BCM63XX-register-lookup-for-ephy-reset-gpio.patch @@ -0,0 +1,138 @@ +From d13bdf92ec885105cf107183f8464c40e5f3b93b Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Feb 2015 17:21:59 +0100 +Subject: [PATCH 4/6] MIPS: BCM63XX: register lookup for ephy-reset gpio + + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/boards/board_common.c | 7 +++-- + arch/mips/bcm63xx/gpio.c | 32 ++++++++++++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 ++ + .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 5 +-- + 5 files changed, 42 insertions(+), 6 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -59,7 +59,7 @@ static struct board_info __initdata boar + }, + + .ephy_reset_gpio = 36, +- .ephy_reset_gpio_flags = GPIOF_INIT_HIGH, ++ .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, + }; + #endif + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -278,9 +278,10 @@ int __init board_register_devices(void) + platform_device_register(&bcm63xx_gpio_leds); + } + +- if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) +- gpio_request_one(board.ephy_reset_gpio, +- board.ephy_reset_gpio_flags, "ephy-reset"); ++ if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) { ++ bcm63xx_gpio_ephy_reset(board.ephy_reset_gpio, ++ board.ephy_reset_gpio_flags); ++ } + + /* count number of BUTTONs defined by this device */ + while (button_count < ARRAY_SIZE(board.buttons) && board.buttons[button_count].desc) +--- a/arch/mips/bcm63xx/gpio.c ++++ b/arch/mips/bcm63xx/gpio.c +@@ -8,15 +8,24 @@ + * Copyright (C) Jonas Gorski + */ + ++#include ++ + #include + #include + #include + #include ++#include + + #include + #include + #include + ++/* for registering lookups; make them large enough to hold OF names */ ++static char *gpio_chip_labels[] = { ++ "xxxxxxxx.gpio-controller", ++ "xxxxxxxx.gpio-controller", ++}; ++ + static void __init bcm63xx_gpio_init_one(int id, int dir, int data, int ngpio) + { + struct resource res[2]; +@@ -40,6 +49,7 @@ static void __init bcm63xx_gpio_init_one + pdata.base = id * 32; + pdata.ngpio = ngpio; + ++ sprintf(gpio_chip_labels[id], "bcm63xx-gpio.%d", id); + platform_device_register_resndata(NULL, "bcm63xx-gpio", id, res, 2, + &pdata, sizeof(pdata)); + } +@@ -64,3 +74,25 @@ int __init bcm63xx_gpio_init(void) + return 0; + + } ++ ++static struct gpiod_lookup_table ephy_reset = { ++ .dev_id = "bcm63xx_enet_shared.0", ++ .table = { ++ { /* filled at runtime */ }, ++ { }, ++ }, ++}; ++ ++ ++void bcm63xx_gpio_ephy_reset(int hw_gpio, enum gpio_lookup_flags flags) ++{ ++ if (ephy_reset.table[0].chip_label) ++ return; ++ ++ ephy_reset.table[0].chip_label = gpio_chip_labels[hw_gpio / 32]; ++ ephy_reset.table[0].chip_hwnum = hw_gpio % 32; ++ ephy_reset.table[0].con_id = "ephy-reset"; ++ ephy_reset.table[0].flags = flags; ++ ++ gpiod_add_lookup_table(&ephy_reset); ++} +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -2,9 +2,11 @@ + #define BCM63XX_GPIO_H + + #include ++#include + #include + + int __init bcm63xx_gpio_init(void); ++void bcm63xx_gpio_ephy_reset(int hw_gpio, enum gpio_lookup_flags flags); + + static inline unsigned long bcm63xx_gpio_count(void) + { +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -4,6 +4,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -58,8 +59,8 @@ struct board_info { + /* External PHY reset GPIO */ + unsigned int ephy_reset_gpio; + +- /* External PHY reset GPIO flags from gpio.h */ +- unsigned long ephy_reset_gpio_flags; ++ /* External PHY reset GPIO flags from gpio/machine.h */ ++ enum gpio_lookup_flags ephy_reset_gpio_flags; + + /* fallback sprom config */ + struct fallback_sprom_data fallback_sprom; diff --git a/target/linux/brcm63xx/patches-3.18/378-MIPS-BCM63XX-do-not-register-gpio-controller-if-pres.patch b/target/linux/brcm63xx/patches-3.18/378-MIPS-BCM63XX-do-not-register-gpio-controller-if-pres.patch new file mode 100644 index 0000000..2faf0de --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/378-MIPS-BCM63XX-do-not-register-gpio-controller-if-pres.patch @@ -0,0 +1,34 @@ +From e55892aac9d5508a000647ca66f0e678e02be3bb Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Feb 2015 17:26:50 +0100 +Subject: [PATCH 5/6] MIPS: BCM63XX: do not register gpio-controller if +present in dtb + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/gpio.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/gpio.c ++++ b/arch/mips/bcm63xx/gpio.c +@@ -20,6 +20,8 @@ + #include + #include + ++#include "boards/board_common.h" ++ + /* for registering lookups; make them large enough to hold OF names */ + static char *gpio_chip_labels[] = { + "xxxxxxxx.gpio-controller", +@@ -50,8 +52,9 @@ static void __init bcm63xx_gpio_init_one + pdata.ngpio = ngpio; + + sprintf(gpio_chip_labels[id], "bcm63xx-gpio.%d", id); +- platform_device_register_resndata(NULL, "bcm63xx-gpio", id, res, 2, +- &pdata, sizeof(pdata)); ++ if (!board_of_device_present("gpio0")) ++ platform_device_register_resndata(NULL, "bcm63xx-gpio", id, res, ++ 2, &pdata, sizeof(pdata)); + } + + int __init bcm63xx_gpio_init(void) diff --git a/target/linux/brcm63xx/patches-3.18/379-MIPS-BCM63XX-provide-a-gpio-lookup-for-the-pcmcia-re.patch b/target/linux/brcm63xx/patches-3.18/379-MIPS-BCM63XX-provide-a-gpio-lookup-for-the-pcmcia-re.patch new file mode 100644 index 0000000..b571999 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/379-MIPS-BCM63XX-provide-a-gpio-lookup-for-the-pcmcia-re.patch @@ -0,0 +1,59 @@ +From 1647cccc871bf43876c3df9852869680880d054c Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Wed, 25 Mar 2015 13:52:02 +0100 +Subject: [PATCH 1/2] MIPS: BCM63XX: provide a gpio lookup for the pcmcia + ready gpio + +To prepare for a time when gpiobases don't need to be fixed anymore. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-pcmcia.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/mips/bcm63xx/dev-pcmcia.c ++++ b/arch/mips/bcm63xx/dev-pcmcia.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -101,6 +102,14 @@ static const struct { + }, + }; + ++static struct gpiod_lookup_table pcmcia_gpios_table = { ++ .dev_id = "bcm63xx_pcmcia.0", ++ .table = { ++ GPIO_LOOKUP("bcm63xx-gpio.0", 0, "ready", GPIO_ACTIVE_HIGH), ++ { }, ++ }, ++}; ++ + int __init bcm63xx_pcmcia_register(void) + { + int ret, i; +@@ -112,16 +121,20 @@ int __init bcm63xx_pcmcia_register(void) + switch (bcm63xx_get_cpu_id()) { + case BCM6348_CPU_ID: + pd.ready_gpio = 22; ++ pcmcia_gpios_table.table[0].chip_hwnum = 22; + break; + + case BCM6358_CPU_ID: + pd.ready_gpio = 18; ++ pcmcia_gpios_table.table[0].chip_hwnum = 18; + break; + + default: + return -ENODEV; + } + ++ gpiod_add_lookup_table(&pcmcia_gpios_table); ++ + pcmcia_resources[0].start = bcm63xx_regset_address(RSET_PCMCIA); + pcmcia_resources[0].end = pcmcia_resources[0].start + + RSET_PCMCIA_SIZE - 1; diff --git a/target/linux/brcm63xx/patches-3.18/380-pcmcia-bcm63xx_pmcia-use-the-new-named-gpio.patch b/target/linux/brcm63xx/patches-3.18/380-pcmcia-bcm63xx_pmcia-use-the-new-named-gpio.patch new file mode 100644 index 0000000..524ca1a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/380-pcmcia-bcm63xx_pmcia-use-the-new-named-gpio.patch @@ -0,0 +1,59 @@ +From c4e04f1c54928a49b227a5420d38b18226838775 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Wed, 25 Mar 2015 13:54:56 +0100 +Subject: [PATCH 2/2] pcmcia: bcm63xx_pmcia: use the new named gpio + +Use the new named gpio instead of relying on the hardware gpio numbers +matching the virtual gpio numbers. + +Signed-off-by: Jonas Gorski +--- + drivers/pcmcia/bcm63xx_pcmcia.c | 9 ++++++++- + drivers/pcmcia/bcm63xx_pcmcia.h | 4 ++++ + 2 files changed, 12 insertions(+), 1 deletion(-) + +--- a/drivers/pcmcia/bcm63xx_pcmcia.c ++++ b/drivers/pcmcia/bcm63xx_pcmcia.c +@@ -237,7 +237,7 @@ static unsigned int __get_socket_status( + stat |= SS_XVCARD; + stat |= SS_POWERON; + +- if (gpio_get_value(skt->pd->ready_gpio)) ++ if (gpiod_get_value(skt->ready_gpio)) + stat |= SS_READY; + + return stat; +@@ -373,6 +373,13 @@ static int bcm63xx_drv_pcmcia_probe(stru + goto err; + } + ++ /* get ready gpio */ ++ skt->ready_gpio = devm_gpiod_get(&pdev->dev, "ready", GPIOD_IN); ++ if (IS_ERR(skt->ready_gpio)) { ++ ret = PTR_ERR(skt->ready_gpio); ++ goto err; ++ } ++ + /* resources are static */ + sock->resource_ops = &pccard_static_ops; + sock->ops = &bcm63xx_pcmcia_operations; +--- a/drivers/pcmcia/bcm63xx_pcmcia.h ++++ b/drivers/pcmcia/bcm63xx_pcmcia.h +@@ -3,6 +3,7 @@ + + #include + #include ++#include + #include + #include + +@@ -55,6 +56,9 @@ struct bcm63xx_pcmcia_socket { + + /* base address of io memory */ + void __iomem *io_base; ++ ++ /* ready gpio */ ++ struct gpio_desc *ready_gpio; + }; + + #endif /* BCM63XX_PCMCIA_H_ */ diff --git a/target/linux/brcm63xx/patches-3.18/400-bcm963xx_flashmap.patch b/target/linux/brcm63xx/patches-3.18/400-bcm963xx_flashmap.patch new file mode 100644 index 0000000..c693ace --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/400-bcm963xx_flashmap.patch @@ -0,0 +1,65 @@ +From a4d005c91d403d9f3d0272db6cc46202c06ec774 Mon Sep 17 00:00:00 2001 +From: Axel Gembe +Date: Mon, 12 May 2008 18:54:09 +0200 +Subject: [PATCH] bcm963xx: flashmap support + +Signed-off-by: Axel Gembe +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 19 +---------------- + drivers/mtd/maps/bcm963xx-flash.c | 32 ++++++++++++++++++++++++---- + drivers/mtd/redboot.c | 13 +++++++++-- + 3 files changed, 38 insertions(+), 26 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -35,7 +35,7 @@ static struct mtd_partition mtd_partitio + } + }; + +-static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL }; ++static const char *bcm63xx_part_types[] = { "bcm63xxpart", "RedBoot", NULL }; + + static struct physmap_flash_data flash_data = { + .width = 2, +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -72,6 +72,7 @@ static int parse_redboot_partitions(stru + int nulllen = 0; + int numslots; + unsigned long offset; ++ unsigned long fis_origin = 0; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif +@@ -176,6 +177,16 @@ static int parse_redboot_partitions(stru + goto out; + } + ++ if (data && data->origin) { ++ fis_origin = data->origin; ++ } else { ++ for (i = 0; i < numslots; i++) { ++ if (!strncmp(buf[i].name, "RedBoot", 8)) { ++ fis_origin = (buf[i].flash_base & (master->size << 1) - 1); ++ } ++ } ++ } ++ + for (i = 0; i < numslots; i++) { + struct fis_list *new_fl, **prev; + +@@ -196,10 +207,10 @@ static int parse_redboot_partitions(stru + goto out; + } + new_fl->img = &buf[i]; +- if (data && data->origin) +- buf[i].flash_base -= data->origin; +- else +- buf[i].flash_base &= master->size-1; ++ if (fis_origin) ++ buf[i].flash_base -= fis_origin; ++ ++ buf[i].flash_base &= (master->size << 1) - 1; + + /* I'm sure the JFFS2 code has done me permanent damage. + * I now think the following is _normal_ diff --git a/target/linux/brcm63xx/patches-3.18/401-bcm963xx_real_rootfs_length.patch b/target/linux/brcm63xx/patches-3.18/401-bcm963xx_real_rootfs_length.patch new file mode 100644 index 0000000..92c264b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/401-bcm963xx_real_rootfs_length.patch @@ -0,0 +1,27 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h +@@ -85,8 +85,10 @@ struct bcm_tag { + __u32 rootfs_crc; + /* 224-227: CRC32 of kernel partition */ + __u32 kernel_crc; +- /* 228-235: Unused at present */ +- char reserved1[8]; ++ /* 228-231: Image sequence number */ ++ char image_sequence[4]; ++ /* 222-235: Openwrt: real rootfs length */ ++ __u32 real_rootfs_length; + /* 236-239: CRC32 of header excluding last 20 bytes */ + __u32 header_crc; + /* 240-255: Unused at present */ +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -110,7 +110,8 @@ static int bcm63xx_parse_cfe_partitions( + } else { + /* OpenWrt layout */ + rootfsaddr = kerneladdr + kernellen; +- rootfslen = spareaddr - rootfsaddr; ++ rootfslen = buf->real_rootfs_length; ++ spareaddr = rootfsaddr + rootfslen; + } + } else { + pr_warn("CFE boot tag CRC invalid (expected %08x, actual %08x)\n", diff --git a/target/linux/brcm63xx/patches-3.18/402_bcm63xx_enet_vlan_incoming_fixed.patch b/target/linux/brcm63xx/patches-3.18/402_bcm63xx_enet_vlan_incoming_fixed.patch new file mode 100644 index 0000000..fc2e8ab --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/402_bcm63xx_enet_vlan_incoming_fixed.patch @@ -0,0 +1,11 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -1633,7 +1633,7 @@ static int compute_hw_mtu(struct bcm_ene + actual_mtu = mtu; + + /* add ethernet header + vlan tag size */ +- actual_mtu += VLAN_ETH_HLEN; ++ actual_mtu += VLAN_ETH_HLEN + VLAN_HLEN; + + if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU) + return -EINVAL; diff --git a/target/linux/brcm63xx/patches-3.18/403-6358-enet1-external-mii-clk.patch b/target/linux/brcm63xx/patches-3.18/403-6358-enet1-external-mii-clk.patch new file mode 100644 index 0000000..0745c3c --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/403-6358-enet1-external-mii-clk.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -104,6 +104,8 @@ void __init board_early_setup(const stru + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G3_EXT_MII | + GPIO_MODE_6348_G0_EXT_MII; ++ else if (BCMCPU_IS_6358()) ++ val |= GPIO_MODE_6358_ENET1_MII_CLK_INV; + } + + bcm_gpio_writel(val, GPIO_MODE_REG); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -651,6 +651,8 @@ + #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) + #define GPIO_MODE_6358_SERIAL_LED (1 << 10) + #define GPIO_MODE_6358_UTOPIA (1 << 12) ++#define GPIO_MODE_6358_ENET1_MII_CLK_INV (1 << 30) ++#define GPIO_MODE_6358_ENET0_MII_CLK_INV (1 << 31) + + #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) + #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) diff --git a/target/linux/brcm63xx/patches-3.18/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch b/target/linux/brcm63xx/patches-3.18/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch new file mode 100644 index 0000000..6036d2f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch @@ -0,0 +1,169 @@ +From b11218c750ab92cfab4408a0328f1b36ceec3f33 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 6 Jan 2012 12:24:18 +0100 +Subject: [PATCH 19/63] NET: bcm63xx_enet: move phy_(dis)connect into probe/remove + +Only connect/disconnect the phy during probe and remove, not during any +open/close. The phy seldom changes during the runtime, and disconnecting +the phy during close will prevent it from keeping any configuration over +a down/up cycle. + +Signed-off-by: Jonas Gorski +--- + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 84 +++++++++++++------------- + 1 files changed, 41 insertions(+), 43 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -871,10 +871,8 @@ static int bcm_enet_open(struct net_devi + struct bcm_enet_priv *priv; + struct sockaddr addr; + struct device *kdev; +- struct phy_device *phydev; + int i, ret; + unsigned int size; +- char phy_id[MII_BUS_ID_SIZE + 3]; + void *p; + u32 val; + +@@ -882,40 +880,10 @@ static int bcm_enet_open(struct net_devi + kdev = &priv->pdev->dev; + + if (priv->has_phy) { +- /* connect to PHY */ +- snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, +- priv->mii_bus->id, priv->phy_id); +- +- phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, +- PHY_INTERFACE_MODE_MII); +- +- if (IS_ERR(phydev)) { +- dev_err(kdev, "could not attach to PHY\n"); +- return PTR_ERR(phydev); +- } +- +- /* mask with MAC supported features */ +- phydev->supported &= (SUPPORTED_10baseT_Half | +- SUPPORTED_10baseT_Full | +- SUPPORTED_100baseT_Half | +- SUPPORTED_100baseT_Full | +- SUPPORTED_Autoneg | +- SUPPORTED_Pause | +- SUPPORTED_MII); +- phydev->advertising = phydev->supported; +- +- if (priv->pause_auto && priv->pause_rx && priv->pause_tx) +- phydev->advertising |= SUPPORTED_Pause; +- else +- phydev->advertising &= ~SUPPORTED_Pause; +- +- dev_info(kdev, "attached PHY at address %d [%s]\n", +- phydev->addr, phydev->drv->name); +- ++ /* Reset state */ + priv->old_link = 0; + priv->old_duplex = -1; + priv->old_pause = -1; +- priv->phydev = phydev; + } + + /* mask all interrupts and request them */ +@@ -925,7 +893,7 @@ static int bcm_enet_open(struct net_devi + + ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); + if (ret) +- goto out_phy_disconnect; ++ return ret; + + ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0, + dev->name, dev); +@@ -1128,9 +1096,6 @@ out_freeirq_rx: + out_freeirq: + free_irq(dev->irq, dev); + +-out_phy_disconnect: +- phy_disconnect(priv->phydev); +- + return ret; + } + +@@ -1235,12 +1200,6 @@ static int bcm_enet_stop(struct net_devi + free_irq(priv->irq_rx, dev); + free_irq(dev->irq, dev); + +- /* release phy */ +- if (priv->has_phy) { +- phy_disconnect(priv->phydev); +- priv->phydev = NULL; +- } +- + return 0; + } + +@@ -1831,6 +1790,8 @@ static int bcm_enet_probe(struct platfor + + /* MII bus registration */ + if (priv->has_phy) { ++ struct phy_device *phydev; ++ char phy_id[MII_BUS_ID_SIZE + 3]; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { +@@ -1868,6 +1829,38 @@ static int bcm_enet_probe(struct platfor + dev_err(&pdev->dev, "unable to register mdio bus\n"); + goto out_free_mdio; + } ++ ++ /* connect to PHY */ ++ snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, ++ priv->mii_bus->id, priv->phy_id); ++ ++ phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, ++ PHY_INTERFACE_MODE_MII); ++ ++ if (IS_ERR(phydev)) { ++ dev_err(&pdev->dev, "could not attach to PHY\n"); ++ goto out_unregister_mdio; ++ } ++ ++ /* mask with MAC supported features */ ++ phydev->supported &= (SUPPORTED_10baseT_Half | ++ SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | ++ SUPPORTED_100baseT_Full | ++ SUPPORTED_Autoneg | ++ SUPPORTED_Pause | ++ SUPPORTED_MII); ++ phydev->advertising = phydev->supported; ++ ++ if (priv->pause_auto && priv->pause_rx && priv->pause_tx) ++ phydev->advertising |= SUPPORTED_Pause; ++ else ++ phydev->advertising &= ~SUPPORTED_Pause; ++ ++ dev_info(&pdev->dev, "attached PHY at address %d [%s]\n", ++ phydev->addr, phydev->drv->name); ++ ++ priv->phydev = phydev; + } else { + + /* run platform code to initialize PHY device */ +@@ -1913,6 +1906,9 @@ static int bcm_enet_probe(struct platfor + return 0; + + out_unregister_mdio: ++ if (priv->phydev) ++ phy_disconnect(priv->phydev); ++ + if (priv->mii_bus) + mdiobus_unregister(priv->mii_bus); + +@@ -1954,6 +1950,8 @@ static int bcm_enet_remove(struct platfo + enet_writel(priv, 0, ENET_MIISC_REG); + + if (priv->has_phy) { ++ phy_disconnect(priv->phydev); ++ priv->phydev = NULL; + mdiobus_unregister(priv->mii_bus); + mdiobus_free(priv->mii_bus); + } else { diff --git a/target/linux/brcm63xx/patches-3.18/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch b/target/linux/brcm63xx/patches-3.18/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch new file mode 100644 index 0000000..2f2eecf --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch @@ -0,0 +1,53 @@ +From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 15 Jul 2012 20:08:57 +0200 +Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 13 +++++++++++++ + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 12 ++++++++++++ + 2 files changed, 25 insertions(+), 0 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -967,6 +967,19 @@ + #define ENETSW_PORTOV_FDX_MASK (1 << 1) + #define ENETSW_PORTOV_LINKUP_MASK (1 << 0) + ++/* Port RGMII control register */ ++#define ENETSW_RGMII_CTRL_REG(x) (0x60 + (x)) ++#define ENETSW_RGMII_CTRL_GMII_CLK_EN (1 << 7) ++#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6) ++#define ENETSW_RGMII_CTRL_MII_MODE_MASK (3 << 4) ++#define ENETSW_RGMII_CTRL_RGMII_MODE (0 << 4) ++#define ENETSW_RGMII_CTRL_MII_MODE (1 << 4) ++#define ENETSW_RGMII_CTRL_RVMII_MODE (2 << 4) ++#define ENETSW_RGMII_CTRL_TIMING_SEL_EN (1 << 0) ++ ++/* Port RGMII timing register */ ++#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x)) ++ + /* MDIO control register */ + #define ENETSW_MDIOC_REG (0xb0) + #define ENETSW_MDIOC_EXT_MASK (1 << 16) +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2225,6 +2225,18 @@ static int bcm_enetsw_open(struct net_de + priv->sw_port_link[i] = 0; + } + ++ /* enable external ports */ ++ for (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) { ++ u8 rgmii_ctrl; ++ ++ if (!priv->used_ports[i].used) ++ continue; ++ ++ rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i)); ++ rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN; ++ enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); ++ } ++ + /* reset mib */ + val = enetsw_readb(priv, ENETSW_GMCR_REG); + val |= ENETSW_GMCR_RST_MIB_MASK; diff --git a/target/linux/brcm63xx/patches-3.18/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch b/target/linux/brcm63xx/patches-3.18/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch new file mode 100644 index 0000000..23b3b83 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch @@ -0,0 +1,133 @@ +From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 3 Jul 2011 15:00:38 +0200 +Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 33 +++++++++++++++++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 + + 2 files changed, 33 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -17,9 +17,12 @@ + #include + #include + #include ++#include ++#include + + #include + #include ++#include + #include + #include + +@@ -66,6 +69,21 @@ void __init bcm63xx_flash_force_phys_bas + mtd_resources[0].end = end; + } + ++static struct flash_platform_data bcm63xx_flash_data = { ++ .part_probe_types = bcm63xx_part_types, ++}; ++ ++static struct spi_board_info bcm63xx_spi_flash_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .mode = 0, ++ .max_speed_hz = 781000, ++ .modalias = "m25p80", ++ .platform_data = &bcm63xx_flash_data, ++ }, ++}; ++ + static int __init bcm63xx_detect_flash_type(void) + { + u32 val; +@@ -73,9 +91,15 @@ static int __init bcm63xx_detect_flash_t + switch (bcm63xx_get_cpu_id()) { + case BCM6318_CPU_ID: + /* only support serial flash */ ++ bcm63xx_spi_flash_info[0].max_speed_hz = 62500000; + return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6328_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); ++ if (val & STRAPBUS_6328_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 33333334; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 16666667; ++ + if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else +@@ -94,12 +118,20 @@ static int __init bcm63xx_detect_flash_t + return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6362_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); ++ if (val & STRAPBUS_6362_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else + return BCM63XX_FLASH_TYPE_NAND; + case BCM6368_CPU_ID: + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); ++ if (val & STRAPBUS_6368_SPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { + case STRAPBUS_6368_BOOT_SEL_NAND: + return BCM63XX_FLASH_TYPE_NAND; +@@ -110,6 +142,11 @@ static int __init bcm63xx_detect_flash_t + } + case BCM63268_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ if (val & STRAPBUS_63268_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else +@@ -195,8 +232,15 @@ int __init bcm63xx_flash_register(void) + + return platform_device_register(&mtd_dev); + case BCM63XX_FLASH_TYPE_SERIAL: +- pr_warn("unsupported serial flash detected\n"); +- return -ENODEV; ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_63268()) ++ bcm63xx_spi_flash_info[0].bus_num = 1; ++ ++ if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) ++ bcm63xx_flash_data.max_transfer_len = SPI_6358_MSG_DATA_SIZE; ++ ++ return spi_register_board_info(bcm63xx_spi_flash_info, ++ ARRAY_SIZE(bcm63xx_spi_flash_info)); + case BCM63XX_FLASH_TYPE_NAND: + pr_warn("unsupported NAND flash detected\n"); + return -ENODEV; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -708,6 +708,7 @@ + #define GPIO_STRAPBUS_REG 0x40 + #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) + #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) ++#define STRAPBUS_6368_SPI_CLK_FAST (1 << 6) + #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 + #define STRAPBUS_6368_BOOT_SEL_NAND 0 + #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 +@@ -1578,6 +1579,7 @@ + #define IDDQ_CTRL_63268_USBH (1 << 4) + + #define MISC_STRAPBUS_6328_REG 0x240 ++#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4) + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) + #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) diff --git a/target/linux/brcm63xx/patches-3.18/412-MTD-physmap-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-3.18/412-MTD-physmap-allow-passing-pp_data.patch new file mode 100644 index 0000000..3511120 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/412-MTD-physmap-allow-passing-pp_data.patch @@ -0,0 +1,41 @@ +From 266c506f4b262bd6aba0776a03d82c98e65d9906 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 1 May 2012 17:32:36 +0200 +Subject: [PATCH 63/79] MTD: physmap: allow passing pp_data + +--- + drivers/mtd/maps/physmap.c | 4 +++- + include/linux/mtd/physmap.h | 1 + + 2 files changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/physmap.c ++++ b/drivers/mtd/maps/physmap.c +@@ -96,6 +96,7 @@ static int physmap_flash_probe(struct pl + { + struct physmap_flash_data *physmap_data; + struct physmap_flash_info *info; ++ struct mtd_part_parser_data *pp_data; + const char * const *probe_type; + const char * const *part_types; + int err = 0; +@@ -187,8 +188,9 @@ static int physmap_flash_probe(struct pl + spin_lock_init(&info->vpp_lock); + + part_types = physmap_data->part_probe_types ? : part_probe_types; ++ pp_data = physmap_data->pp_data ? physmap_data->pp_data : NULL; + +- mtd_device_parse_register(info->cmtd, part_types, NULL, ++ mtd_device_parse_register(info->cmtd, part_types, pp_data, + physmap_data->parts, physmap_data->nr_parts); + return 0; + +--- a/include/linux/mtd/physmap.h ++++ b/include/linux/mtd/physmap.h +@@ -31,6 +31,7 @@ struct physmap_flash_data { + char *probe_type; + struct mtd_partition *parts; + const char * const *part_probe_types; ++ struct mtd_part_parser_data *pp_data; + }; + + #endif /* __LINUX_MTD_PHYSMAP__ */ diff --git a/target/linux/brcm63xx/patches-3.18/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch b/target/linux/brcm63xx/patches-3.18/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch new file mode 100644 index 0000000..0960005 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch @@ -0,0 +1,72 @@ +From 8879e209111192c5e9752d7bd203cf7582693328 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 3 May 2012 14:40:03 +0200 +Subject: [PATCH 58/72] BCM63XX: allow providing fixup data in board data + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 9 ++++++++- + arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 10 ++++++++++ + 2 files changed, 18 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + #include "board_common.h" + +@@ -196,6 +197,7 @@ int __init board_register_devices(void) + int button_count = 0; + int led_count = 0; + int usbh_ports = 0; ++ int i; + + #if CONFIG_OF + if (of_have_populated_dt()) { +@@ -296,6 +298,10 @@ int __init board_register_devices(void) + platform_device_register(&bcm63xx_gpio_keys_device); + } + ++ /* register any fixups */ ++ for (i = 0; i < board.has_caldata; i++) ++ pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset); ++ + return 0; + } + +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + /* + * flash mapping +@@ -17,6 +18,11 @@ + #define BCM963XX_CFE_VERSION_OFFSET 0x570 + #define BCM963XX_NVRAM_OFFSET 0x580 + ++struct ath9k_caldata { ++ unsigned int slot; ++ u32 caldata_offset; ++}; ++ + /* + * board definition + */ +@@ -37,6 +43,10 @@ struct board_info { + unsigned int has_uart0:1; + unsigned int has_uart1:1; + unsigned int use_fallback_sprom:1; ++ unsigned int has_caldata:2; ++ ++ /* wifi calibration data config */ ++ struct ath9k_caldata caldata[2]; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; diff --git a/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch new file mode 100644 index 0000000..b7bf57f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch @@ -0,0 +1,40 @@ +From 7f17dfe9009beb07a3de0e380932a725293829df Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 1 May 2012 17:33:03 +0200 +Subject: [PATCH 64/79] MTD: m25p80: allow passing pp_data + +--- + drivers/mtd/devices/m25p80.c | 3 +++ + include/linux/spi/flash.h | 2 ++ + 2 files changed, 5 insertions(+) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -267,6 +267,9 @@ static int m25p_probe(struct spi_device + if (data) + flash->max_transfer_len = data->max_transfer_len; + ++ if (data && data->pp_data) ++ memcpy(&ppdata, data->pp_data, sizeof(ppdata)); ++ + ret = spi_nor_scan(nor, flash_name, mode); + if (ret) + return ret; +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -12,6 +12,7 @@ struct mtd_part_parser_data; + * with chips that can't be queried for JEDEC or other IDs + * @part_probe_types: optional list of MTD parser names to use for + * partitioning ++ * @pp_data: optional partition parser data. + * + * @max_transfer_len: option maximum read/write length limitation for + * SPI controllers not able to transfer any length commands. +@@ -30,6 +31,7 @@ struct flash_platform_data { + char *type; + + const char **part_probe_types; ++ struct mtd_part_parser_data *pp_data; + + unsigned int max_transfer_len; + /* we'll likely add more ... use JEDEC IDs, etc */ diff --git a/target/linux/brcm63xx/patches-3.18/415-MIPS-BCM63XX-export-the-attached-flash-type.patch b/target/linux/brcm63xx/patches-3.18/415-MIPS-BCM63XX-export-the-attached-flash-type.patch new file mode 100644 index 0000000..44763bb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/415-MIPS-BCM63XX-export-the-attached-flash-type.patch @@ -0,0 +1,31 @@ +From 066f1e37742ee434496d32a41a9284458de96742 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 13 Jan 2014 12:12:30 +0100 +Subject: [PATCH] MIPS: BCM63XX: export the attached flash type + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 5 +++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++ + 2 files changed, 7 insertions(+) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -250,3 +250,8 @@ int __init bcm63xx_flash_register(void) + return -ENODEV; + } + } ++ ++int bcm63xx_flash_get_type(void) ++{ ++ return flash_type; ++} +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -13,4 +13,6 @@ void bcm63xx_flash_force_phys_base_addre + + int __init bcm63xx_flash_register(void); + ++int bcm63xx_flash_get_type(void); ++ + #endif /* __BCM63XX_FLASH_H */ diff --git a/target/linux/brcm63xx/patches-3.18/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch b/target/linux/brcm63xx/patches-3.18/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch new file mode 100644 index 0000000..7a7c825 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch @@ -0,0 +1,236 @@ +From bbebbf735a02b6d044ed928978ab4bd5f1833364 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 3 May 2012 14:36:11 +0200 +Subject: [PATCH 61/72] BCM63XX: add a fixup for ath9k devices + +--- + arch/mips/bcm63xx/Makefile | 3 +- + arch/mips/bcm63xx/pci-ath9k-fixup.c | 190 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/pci_ath9k_fixup.h | 7 + + 3 files changed, 199 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/pci-ath9k-fixup.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ + dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ +- usb-common.o sprom.o ++ pci-ath9k-fixup.o usb-common.o sprom.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -0,0 +1,199 @@ ++/* ++ * Broadcom BCM63XX Ath9k EEPROM fixup helper. ++ * ++ * Copytight (C) 2012 Jonas Gorski ++ * ++ * Based on ++ * ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define bcm_hsspi_writel(v, o) bcm_rset_writel(RSET_HSSPI, (v), (o)) ++ ++struct ath9k_fixup { ++ unsigned slot; ++ u8 mac[ETH_ALEN]; ++ struct ath9k_platform_data pdata; ++}; ++ ++static int ath9k_num_fixups; ++static struct ath9k_fixup ath9k_fixups[2] = { ++ { ++ .slot = 255, ++ .pdata = { ++ .led_pin = -1, ++ }, ++ }, ++ { ++ .slot = 255, ++ .pdata = { ++ .led_pin = -1, ++ }, ++ }, ++}; ++ ++static u16 *bcm63xx_read_eeprom(u16 *eeprom, u32 offset) ++{ ++ u32 addr; ++ ++ if (BCMCPU_IS_6328()) { ++ addr = 0x18000000; ++ } else { ++ addr = bcm_mpi_readl(MPI_CSBASE_REG(0)); ++ addr &= MPI_CSBASE_BASE_MASK; ++ } ++ ++ switch (bcm63xx_flash_get_type()) { ++ case BCM63XX_FLASH_TYPE_PARALLEL: ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ return eeprom; ++ case BCM63XX_FLASH_TYPE_SERIAL: ++ /* the first megabyte is memory mapped */ ++ if (offset < 0x100000) { ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ return eeprom; ++ } ++ ++ if (BCMCPU_IS_6328()) { ++ /* we can change the memory mapped megabyte */ ++ bcm_hsspi_writel(offset & 0xf00000, 0x18); ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + (offset & 0xfffff)), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ bcm_hsspi_writel(0, 0x18); ++ return eeprom; ++ } ++ /* can't do anything here without talking to the SPI controller. */ ++ case BCM63XX_FLASH_TYPE_NAND: ++ default: ++ return NULL; ++ } ++} ++ ++static void ath9k_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ struct ath9k_platform_data *pdata = NULL; ++ struct pci_dev *bridge = pci_upstream_bridge(dev); ++ u16 *cal_data = NULL; ++ u16 cmd; ++ u32 bar0; ++ u32 val; ++ unsigned i; ++ ++ for (i = 0; i < ath9k_num_fixups; i++) { ++ if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ cal_data = ath9k_fixups[i].pdata.eeprom_data; ++ pdata = &ath9k_fixups[i].pdata; ++ break; ++ } ++ ++ if (cal_data == NULL) ++ return; ++ ++ if (*cal_data != 0xa55a) { ++ pr_err("pci %s: invalid calibration data\n", pci_name(dev)); ++ return; ++ } ++ ++ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); ++ ++ switch (bcm63xx_get_cpu_id()) { ++ case BCM6328_CPU_ID: ++ val = BCM_PCIE_MEM_BASE_PA_6328; ++ break; ++ case BCM6348_CPU_ID: ++ case BCM6358_CPU_ID: ++ case BCM6368_CPU_ID: ++ val = BCM_PCI_MEM_BASE_PA; ++ break; ++ default: ++ BUG(); ++ } ++ ++ mem = ioremap(val, 0x10000); ++ if (!mem) { ++ pr_err("pci %s: ioremap error\n", pci_name(dev)); ++ return; ++ } ++ ++ if (bridge) ++ pci_enable_device(bridge); ++ ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, val); ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ /* set offset to first reg address */ ++ cal_data += 3; ++ while(*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; ++ ++ writel(val, mem + reg); ++ udelay(100); ++ } ++ ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; ++ ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); ++ ++ if (bridge) ++ pci_disable_device(bridge); ++ ++ iounmap(mem); ++ ++ dev->dev.platform_data = pdata; ++} ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); ++ ++void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset) ++{ ++ if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) ++ return; ++ ++ ath9k_fixups[ath9k_num_fixups].slot = slot; ++ ++ if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) ++ return; ++ ++ if (bcm63xx_nvram_get_mac_address(ath9k_fixups[ath9k_num_fixups].mac)) ++ return; ++ ++ ath9k_fixups[ath9k_num_fixups].pdata.macaddr = ath9k_fixups[ath9k_num_fixups].mac; ++ ath9k_num_fixups++; ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -0,0 +1,7 @@ ++#ifndef _PCI_ATH9K_FIXUP ++#define _PCI_ATH9K_FIXUP ++ ++ ++void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init; ++ ++#endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/brcm63xx/patches-3.18/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch b/target/linux/brcm63xx/patches-3.18/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch new file mode 100644 index 0000000..3b02c07 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch @@ -0,0 +1,120 @@ +Allow bcm63xxpart to receive a caldata offset if calibration data is +contained in flash. +--- + drivers/mtd/bcm63xxpart.c | 51 ++++++++++++++++++++++++++++++++++++--- + include/linux/mtd/partitions.h | 2 + + 2 files changed, 49 insertions(+), 4 deletions(-) + +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -53,10 +53,12 @@ static int bcm63xx_parse_cfe_partitions( + struct mtd_partition *parts; + int ret; + size_t retlen; +- unsigned int rootfsaddr, kerneladdr, spareaddr; ++ unsigned int rootfsaddr, kerneladdr, spareaddr, nvramaddr; + unsigned int rootfslen, kernellen, sparelen, totallen; + unsigned int cfelen, nvramlen; + unsigned int cfe_erasesize; ++ unsigned int caldatalen1 = 0, caldataaddr1 = 0; ++ unsigned int caldatalen2 = 0, caldataaddr2 = 0; + int i; + u32 computed_crc; + bool rootfs_first = false; +@@ -70,6 +72,24 @@ static int bcm63xx_parse_cfe_partitions( + cfelen = cfe_erasesize; + nvramlen = bcm63xx_nvram_get_psi_size() * SZ_1K; + nvramlen = roundup(nvramlen, cfe_erasesize); ++ nvramaddr = master->size - nvramlen; ++ ++ if (data) { ++ if (data->caldata[0]) { ++ caldatalen1 = cfe_erasesize; ++ caldataaddr1 = rounddown(data->caldata[0], ++ cfe_erasesize); ++ } ++ if (data->caldata[1]) { ++ caldatalen2 = cfe_erasesize; ++ caldataaddr2 = rounddown(data->caldata[1], ++ cfe_erasesize); ++ } ++ if (caldataaddr1 == caldataaddr2) { ++ caldataaddr2 = 0; ++ caldatalen2 = 0; ++ } ++ } + + /* Allocate memory for buffer */ + buf = vmalloc(sizeof(struct bcm_tag)); +@@ -121,7 +141,7 @@ static int bcm63xx_parse_cfe_partitions( + rootfsaddr = 0; + spareaddr = cfelen; + } +- sparelen = master->size - spareaddr - nvramlen; ++ sparelen = min_not_zero(nvramaddr, caldataaddr1) - spareaddr; + + /* Determine number of partitions */ + if (rootfslen > 0) +@@ -130,6 +150,12 @@ static int bcm63xx_parse_cfe_partitions( + if (kernellen > 0) + nrparts++; + ++ if (caldatalen1 > 0) ++ nrparts++; ++ ++ if (caldatalen2 > 0) ++ nrparts++; ++ + /* Ask kernel for more memory */ + parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL); + if (!parts) { +@@ -167,15 +193,32 @@ static int bcm63xx_parse_cfe_partitions( + curpart++; + } + ++ if (caldatalen1 > 0) { ++ if (caldatalen2 > 0) ++ parts[curpart].name = "cal_data1"; ++ else ++ parts[curpart].name = "cal_data"; ++ parts[curpart].offset = caldataaddr1; ++ parts[curpart].size = caldatalen1; ++ curpart++; ++ } ++ ++ if (caldatalen2 > 0) { ++ parts[curpart].name = "cal_data2"; ++ parts[curpart].offset = caldataaddr2; ++ parts[curpart].size = caldatalen2; ++ curpart++; ++ } ++ + parts[curpart].name = "nvram"; +- parts[curpart].offset = master->size - nvramlen; ++ parts[curpart].offset = nvramaddr; + parts[curpart].size = nvramlen; + curpart++; + + /* Global partition "linux" to make easy firmware upgrade */ + parts[curpart].name = "linux"; + parts[curpart].offset = cfelen; +- parts[curpart].size = master->size - cfelen - nvramlen; ++ parts[curpart].size = min_not_zero(nvramaddr, caldataaddr1) - cfelen; + + for (i = 0; i < nrparts; i++) + pr_info("Partition %d is %s offset %llx and length %llx\n", i, +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -56,10 +56,12 @@ struct device_node; + /** + * struct mtd_part_parser_data - used to pass data to MTD partition parsers. + * @origin: for RedBoot, start address of MTD device ++ * @caldata: for CFE, start address of wifi calibration data + * @of_node: for OF parsers, device node containing partitioning information + */ + struct mtd_part_parser_data { + unsigned long origin; ++ unsigned long caldata[2]; + struct device_node *of_node; + }; + diff --git a/target/linux/brcm63xx/patches-3.18/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch b/target/linux/brcm63xx/patches-3.18/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch new file mode 100644 index 0000000..484e1fd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch @@ -0,0 +1,83 @@ +From 977f8a30103b9c4992cab8f49357fe0d4274004f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 3 May 2012 14:55:26 +0200 +Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash + +--- + arch/mips/bcm63xx/boards/board_common.c | 2 +- + arch/mips/bcm63xx/dev-flash.c | 9 ++++++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 4 +++- + 3 files changed, 12 insertions(+), 3 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -269,7 +269,7 @@ int __init board_register_devices(void) + if (board.num_spis) + spi_register_board_info(board.spis, board.num_spis); + +- bcm63xx_flash_register(); ++ bcm63xx_flash_register(board.has_caldata, board.caldata); + + /* count number of LEDs defined by this device */ + while (led_count < ARRAY_SIZE(board.leds) && board.leds[led_count].name) +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -38,12 +38,15 @@ static struct mtd_partition mtd_partitio + } + }; + ++static struct mtd_part_parser_data bcm63xx_parser_data; ++ + static const char *bcm63xx_part_types[] = { "bcm63xxpart", "RedBoot", NULL }; + + static struct physmap_flash_data flash_data = { + .width = 2, + .parts = mtd_partitions, + .part_probe_types = bcm63xx_part_types, ++ .pp_data = &bcm63xx_parser_data, + }; + + static struct resource mtd_resources[] = { +@@ -71,6 +74,7 @@ void __init bcm63xx_flash_force_phys_bas + + static struct flash_platform_data bcm63xx_flash_data = { + .part_probe_types = bcm63xx_part_types, ++ .pp_data = &bcm63xx_parser_data, + }; + + static struct spi_board_info bcm63xx_spi_flash_info[] = { +@@ -211,9 +215,13 @@ void __init bcm63xx_flash_detect(void) + } + } + +-int __init bcm63xx_flash_register(void) ++int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata) + { + u32 val; ++ unsigned int i; ++ ++ for (i = 0; i < num_caldata; i++) ++ bcm63xx_parser_data.caldata[i] = caldata[i].caldata_offset; + + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -1,6 +1,8 @@ + #ifndef __BCM63XX_FLASH_H + #define __BCM63XX_FLASH_H + ++#include ++ + enum { + BCM63XX_FLASH_TYPE_PARALLEL, + BCM63XX_FLASH_TYPE_SERIAL, +@@ -11,7 +13,7 @@ void bcm63xx_flash_detect(void); + + void bcm63xx_flash_force_phys_base_address(u32 start, u32 end); + +-int __init bcm63xx_flash_register(void); ++int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata); + + int bcm63xx_flash_get_type(void); + diff --git a/target/linux/brcm63xx/patches-3.18/420-BCM63XX-add-endian-check-for-ath9k.patch b/target/linux/brcm63xx/patches-3.18/420-BCM63XX-add-endian-check-for-ath9k.patch new file mode 100644 index 0000000..5398c3d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/420-BCM63XX-add-endian-check-for-ath9k.patch @@ -0,0 +1,51 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -2,6 +2,7 @@ + #define _PCI_ATH9K_FIXUP + + +-void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init; ++void pci_enable_ath9k_fixup(unsigned slot, u32 offset, ++ unsigned endian_check) __init; + + #endif /* _PCI_ATH9K_FIXUP */ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -21,6 +21,7 @@ + struct ath9k_caldata { + unsigned int slot; + u32 caldata_offset; ++ unsigned int endian_check:1; + }; + + /* +--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -181,12 +181,14 @@ static void ath9k_pci_fixup(struct pci_d + } + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + +-void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset) ++void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset, ++ unsigned endian_check) + { + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; ++ ath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check; + + if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) + return; +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -300,7 +300,8 @@ int __init board_register_devices(void) + + /* register any fixups */ + for (i = 0; i < board.has_caldata; i++) +- pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset); ++ pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, ++ board.caldata[i].endian_check); + + return 0; + } diff --git a/target/linux/brcm63xx/patches-3.18/421-BCM63XX-add-led-pin-for-ath9k.patch b/target/linux/brcm63xx/patches-3.18/421-BCM63XX-add-led-pin-for-ath9k.patch new file mode 100644 index 0000000..1310136 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/421-BCM63XX-add-led-pin-for-ath9k.patch @@ -0,0 +1,49 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -301,7 +301,7 @@ int __init board_register_devices(void) + /* register any fixups */ + for (i = 0; i < board.has_caldata; i++) + pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, +- board.caldata[i].endian_check); ++ board.caldata[i].endian_check, board.caldata[i].led_pin); + + return 0; + } +--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -182,13 +182,14 @@ static void ath9k_pci_fixup(struct pci_d + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + + void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset, +- unsigned endian_check) ++ unsigned endian_check, int led_pin) + { + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; + ath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check; ++ ath9k_fixups[ath9k_num_fixups].pdata.led_pin = led_pin; + + if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) + return; +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -22,6 +22,7 @@ struct ath9k_caldata { + unsigned int slot; + u32 caldata_offset; + unsigned int endian_check:1; ++ int led_pin; + }; + + /* +--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -3,6 +3,6 @@ + + + void pci_enable_ath9k_fixup(unsigned slot, u32 offset, +- unsigned endian_check) __init; ++ unsigned endian_check, int led_pin) __init; + + #endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/brcm63xx/patches-3.18/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch b/target/linux/brcm63xx/patches-3.18/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch new file mode 100644 index 0000000..4a0a7b0 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch @@ -0,0 +1,206 @@ +From 5ed5b5e9614fa5b02da699ab565af76c7e63d64d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 7 Jan 2013 17:45:39 +0100 +Subject: [PATCH 72/72] 446-BCM63XX-add-a-fixup-for-rt2x00-devices + +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 17 ++++- + arch/mips/bcm63xx/dev-flash.c | 2 +- + arch/mips/bcm63xx/pci-rt2x00-fixup.c | 71 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 +- + .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 9 ++- + .../include/asm/mach-bcm63xx/pci_rt2x00_fixup.h | 9 +++ + 7 files changed, 104 insertions(+), 8 deletions(-) + create mode 100644 arch/mips/bcm63xx/pci-rt2x00-fixup.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_rt2x00_fixup.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ + dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ +- pci-ath9k-fixup.o usb-common.o sprom.o ++ pci-ath9k-fixup.o pci-rt2x00-fixup.o usb-common.o sprom.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + + #include "board_common.h" + +@@ -299,9 +300,19 @@ int __init board_register_devices(void) + } + + /* register any fixups */ +- for (i = 0; i < board.has_caldata; i++) +- pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, +- board.caldata[i].endian_check, board.caldata[i].led_pin); ++ for (i = 0; i < board.has_caldata; i++) { ++ switch (board.caldata[i].vendor) { ++ case PCI_VENDOR_ID_ATHEROS: ++ pci_enable_ath9k_fixup(board.caldata[i].slot, ++ board.caldata[i].caldata_offset, board.caldata[i].endian_check, ++ board.caldata[i].led_pin); ++ break; ++ case PCI_VENDOR_ID_RALINK: ++ pci_enable_rt2x00_fixup(board.caldata[i].slot, ++ board.caldata[i].eeprom); ++ break; ++ } ++ } + + return 0; + } +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -215,7 +215,7 @@ void __init bcm63xx_flash_detect(void) + } + } + +-int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata) ++int __init bcm63xx_flash_register(int num_caldata, struct bcm63xx_caldata *caldata) + { + u32 val; + unsigned int i; +--- /dev/null ++++ b/arch/mips/bcm63xx/pci-rt2x00-fixup.c +@@ -0,0 +1,72 @@ ++/* ++ * Broadcom BCM63XX RT2x00 EEPROM fixup helper. ++ * ++ * Copyright (C) 2012 Ãlvaro Fernández Rojas ++ * ++ * Based on ++ * ++ * Broadcom BCM63XX Ath9k EEPROM fixup helper. ++ * ++ * Copyright (C) 2012 Jonas Gorski ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct rt2x00_fixup { ++ unsigned slot; ++ u8 mac[ETH_ALEN]; ++ struct rt2x00_platform_data pdata; ++}; ++ ++static int rt2x00_num_fixups; ++static struct rt2x00_fixup rt2x00_fixups[2] = { ++ { ++ .slot = 255, ++ }, ++ { ++ .slot = 255, ++ }, ++}; ++ ++static void rt2x00_pci_fixup(struct pci_dev *dev) ++{ ++ unsigned i; ++ struct rt2x00_platform_data *pdata = NULL; ++ ++ for (i = 0; i < rt2x00_num_fixups; i++) { ++ if (rt2x00_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ pdata = &rt2x00_fixups[i].pdata; ++ break; ++ } ++ ++ dev->dev.platform_data = pdata; ++} ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RALINK, PCI_ANY_ID, rt2x00_pci_fixup); ++ ++void __init pci_enable_rt2x00_fixup(unsigned slot, char* eeprom) ++{ ++ if (rt2x00_num_fixups >= ARRAY_SIZE(rt2x00_fixups)) ++ return; ++ ++ rt2x00_fixups[rt2x00_num_fixups].slot = slot; ++ rt2x00_fixups[rt2x00_num_fixups].pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL); ++ ++ if (bcm63xx_nvram_get_mac_address(rt2x00_fixups[rt2x00_num_fixups].mac)) ++ return; ++ ++ rt2x00_fixups[rt2x00_num_fixups].pdata.mac_address = rt2x00_fixups[rt2x00_num_fixups].mac; ++ rt2x00_num_fixups++; ++} ++ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -13,7 +13,7 @@ void bcm63xx_flash_detect(void); + + void bcm63xx_flash_force_phys_base_address(u32 start, u32 end); + +-int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata); ++int __init bcm63xx_flash_register(int num_caldata, struct bcm63xx_caldata *caldata); + + int bcm63xx_flash_get_type(void); + +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + + /* + * flash mapping +@@ -18,11 +19,15 @@ + #define BCM963XX_CFE_VERSION_OFFSET 0x570 + #define BCM963XX_NVRAM_OFFSET 0x580 + +-struct ath9k_caldata { ++struct bcm63xx_caldata { ++ unsigned int vendor; + unsigned int slot; + u32 caldata_offset; ++ /* Atheros */ + unsigned int endian_check:1; + int led_pin; ++ /* Ralink */ ++ char* eeprom; + }; + + /* +@@ -48,7 +53,7 @@ struct board_info { + unsigned int has_caldata:2; + + /* wifi calibration data config */ +- struct ath9k_caldata caldata[2]; ++ struct bcm63xx_caldata caldata[2]; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_rt2x00_fixup.h +@@ -0,0 +1,9 @@ ++#ifndef _PCI_RT2X00_FIXUP ++#define _PCI_RT2X00_FIXUP ++ ++#define PCI_VENDOR_ID_RALINK 0x1814 ++ ++void pci_enable_rt2x00_fixup(unsigned slot, char* eeprom) __init; ++ ++#endif /* _PCI_RT2X00_FIXUP */ ++ diff --git a/target/linux/brcm63xx/patches-3.18/423-bcm63xx_enet_add_b53_support.patch b/target/linux/brcm63xx/patches-3.18/423-bcm63xx_enet_add_b53_support.patch new file mode 100644 index 0000000..f7697e1 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/423-bcm63xx_enet_add_b53_support.patch @@ -0,0 +1,169 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h +@@ -336,6 +336,9 @@ struct bcm_enet_priv { + struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT]; + int sw_port_link[ENETSW_MAX_PORT]; + ++ /* platform device for associated switch */ ++ struct platform_device *b53_device; ++ + /* used to poll switch port state */ + struct timer_list swphy_poll; + spinlock_t enetsw_mdio_lock; +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + + #include + #include "bcm63xx_enet.h" +@@ -1975,7 +1976,8 @@ static int bcm_enet_remove(struct platfo + return 0; + } + +-struct platform_driver bcm63xx_enet_driver = { ++ ++static struct platform_driver bcm63xx_enet_driver = { + .probe = bcm_enet_probe, + .remove = bcm_enet_remove, + .driver = { +@@ -1984,6 +1986,42 @@ struct platform_driver bcm63xx_enet_driv + }, + }; + ++struct b53_platform_data bcm63xx_b53_pdata = { ++ .chip_id = 0x6300, ++ .big_endian = 1, ++}; ++ ++struct platform_device bcm63xx_b53_dev = { ++ .name = "b53-switch", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm63xx_b53_pdata, ++ }, ++}; ++ ++static int bcmenet_switch_register(struct bcm_enet_priv *priv, u16 port_mask) ++{ ++ int ret; ++ ++ bcm63xx_b53_pdata.regs = priv->base; ++ bcm63xx_b53_pdata.enabled_ports = port_mask; ++ bcm63xx_b53_pdata.alias = priv->net_dev->name; ++ ++ ret = platform_device_register(&bcm63xx_b53_dev); ++ if (!ret) ++ priv->b53_device = &bcm63xx_b53_dev; ++ ++ return ret; ++} ++ ++static void bcmenet_switch_unregister(struct bcm_enet_priv *priv) ++{ ++ if (priv->b53_device) ++ platform_device_unregister(&bcm63xx_b53_dev); ++ ++ priv->b53_device = NULL; ++} ++ + /* + * switch mii access callbacks + */ +@@ -2237,29 +2275,6 @@ static int bcm_enetsw_open(struct net_de + enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); + } + +- /* reset mib */ +- val = enetsw_readb(priv, ENETSW_GMCR_REG); +- val |= ENETSW_GMCR_RST_MIB_MASK; +- enetsw_writeb(priv, val, ENETSW_GMCR_REG); +- mdelay(1); +- val &= ~ENETSW_GMCR_RST_MIB_MASK; +- enetsw_writeb(priv, val, ENETSW_GMCR_REG); +- mdelay(1); +- +- /* force CPU port state */ +- val = enetsw_readb(priv, ENETSW_IMPOV_REG); +- val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; +- enetsw_writeb(priv, val, ENETSW_IMPOV_REG); +- +- /* enable switch forward engine */ +- val = enetsw_readb(priv, ENETSW_SWMODE_REG); +- val |= ENETSW_SWMODE_FWD_EN_MASK; +- enetsw_writeb(priv, val, ENETSW_SWMODE_REG); +- +- /* enable jumbo on all ports */ +- enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); +- enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); +- + /* initialize flow control buffer allocation */ + enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, + ENETDMA_BUFALLOC_REG(priv->rx_chan)); +@@ -2719,6 +2734,9 @@ static int bcm_enetsw_probe(struct platf + struct bcm63xx_enetsw_platform_data *pd; + struct resource *res_mem; + int ret, irq_rx, irq_tx; ++ unsigned i, num_ports = 0; ++ u16 port_mask = BIT(8); ++ u8 val; + + /* stop if shared driver failed, assume driver->probe will be + * called in the same order we register devices (correct ?) +@@ -2808,6 +2826,43 @@ static int bcm_enetsw_probe(struct platf + priv->pdev = pdev; + priv->net_dev = dev; + ++ /* reset mib */ ++ val = enetsw_readb(priv, ENETSW_GMCR_REG); ++ val |= ENETSW_GMCR_RST_MIB_MASK; ++ enetsw_writeb(priv, val, ENETSW_GMCR_REG); ++ mdelay(1); ++ val &= ~ENETSW_GMCR_RST_MIB_MASK; ++ enetsw_writeb(priv, val, ENETSW_GMCR_REG); ++ mdelay(1); ++ ++ /* force CPU port state */ ++ val = enetsw_readb(priv, ENETSW_IMPOV_REG); ++ val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; ++ enetsw_writeb(priv, val, ENETSW_IMPOV_REG); ++ ++ /* enable switch forward engine */ ++ val = enetsw_readb(priv, ENETSW_SWMODE_REG); ++ val |= ENETSW_SWMODE_FWD_EN_MASK; ++ enetsw_writeb(priv, val, ENETSW_SWMODE_REG); ++ ++ /* enable jumbo on all ports */ ++ enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); ++ enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); ++ ++ for (i = 0; i < priv->num_ports; i++) { ++ struct bcm63xx_enetsw_port *port = &priv->used_ports[i]; ++ ++ if (!port->used) ++ continue; ++ ++ num_ports++; ++ port_mask |= BIT(i); ++ } ++ ++ /* only register if there is more than one external port */ ++ if (num_ports > 1) ++ bcmenet_switch_register(priv, port_mask); ++ + return 0; + + out_put_clk: +@@ -2836,6 +2891,9 @@ static int bcm_enetsw_remove(struct plat + priv = netdev_priv(dev); + unregister_netdev(dev); + ++ /* remove switch */ ++ bcmenet_switch_unregister(priv); ++ + /* release device resources */ + iounmap(priv->base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/brcm63xx/patches-3.18/424-bcm63xx_enet_no_request_mem_region.patch b/target/linux/brcm63xx/patches-3.18/424-bcm63xx_enet_no_request_mem_region.patch new file mode 100644 index 0000000..a087308 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/424-bcm63xx_enet_no_request_mem_region.patch @@ -0,0 +1,15 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2781,12 +2781,6 @@ static int bcm_enetsw_probe(struct platf + if (ret) + goto out; + +- if (!request_mem_region(res_mem->start, resource_size(res_mem), +- "bcm63xx_enetsw")) { +- ret = -EBUSY; +- goto out; +- } +- + priv->base = ioremap(res_mem->start, resource_size(res_mem)); + if (priv->base == NULL) { + ret = -ENOMEM; diff --git a/target/linux/brcm63xx/patches-3.18/425-bcm63xxpart_parse_paritions_from_dt.patch b/target/linux/brcm63xx/patches-3.18/425-bcm63xxpart_parse_paritions_from_dt.patch new file mode 100644 index 0000000..53fc4c5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/425-bcm63xxpart_parse_paritions_from_dt.patch @@ -0,0 +1,357 @@ +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -43,66 +44,35 @@ + + #define BCM63XX_CFE_MAGIC_OFFSET 0x4e0 + +-static int bcm63xx_parse_cfe_partitions(struct mtd_info *master, +- struct mtd_partition **pparts, +- struct mtd_part_parser_data *data) ++static bool node_has_compatible(struct device_node *pp) ++{ ++ return of_get_property(pp, "compatible", NULL); ++} ++ ++static int parse_bcmtag(struct mtd_info *master, struct mtd_partition *pparts, ++ int next_part, size_t offset, size_t size) + { +- /* CFE, NVRAM and global Linux are always present */ +- int nrparts = 3, curpart = 0; + struct bcm_tag *buf; +- struct mtd_partition *parts; ++ u32 computed_crc; + int ret; + size_t retlen; +- unsigned int rootfsaddr, kerneladdr, spareaddr, nvramaddr; +- unsigned int rootfslen, kernellen, sparelen, totallen; +- unsigned int cfelen, nvramlen; +- unsigned int cfe_erasesize; +- unsigned int caldatalen1 = 0, caldataaddr1 = 0; +- unsigned int caldatalen2 = 0, caldataaddr2 = 0; +- int i; +- u32 computed_crc; ++ unsigned int rootfsaddr, kerneladdr; ++ unsigned int rootfslen, kernellen, totallen; + bool rootfs_first = false; +- +- if (!bcm63xx_is_cfe_present()) +- return -EINVAL; +- +- cfe_erasesize = max_t(uint32_t, master->erasesize, +- BCM63XX_CFE_BLOCK_SIZE); +- +- cfelen = cfe_erasesize; +- nvramlen = bcm63xx_nvram_get_psi_size() * SZ_1K; +- nvramlen = roundup(nvramlen, cfe_erasesize); +- nvramaddr = master->size - nvramlen; +- +- if (data) { +- if (data->caldata[0]) { +- caldatalen1 = cfe_erasesize; +- caldataaddr1 = rounddown(data->caldata[0], +- cfe_erasesize); +- } +- if (data->caldata[1]) { +- caldatalen2 = cfe_erasesize; +- caldataaddr2 = rounddown(data->caldata[1], +- cfe_erasesize); +- } +- if (caldataaddr1 == caldataaddr2) { +- caldataaddr2 = 0; +- caldatalen2 = 0; +- } +- } ++ int curr_part = next_part; + + /* Allocate memory for buffer */ +- buf = vmalloc(sizeof(struct bcm_tag)); ++ buf = vmalloc(sizeof(*buf)); + if (!buf) + return -ENOMEM; + + /* Get the tag */ +- ret = mtd_read(master, cfelen, sizeof(struct bcm_tag), &retlen, ++ ret = mtd_read(master, offset, sizeof(*buf), &retlen, + (void *)buf); + +- if (retlen != sizeof(struct bcm_tag)) { ++ if (retlen != sizeof(*buf)) { + vfree(buf); +- return -EIO; ++ return 0; + } + + computed_crc = crc32_le(IMAGETAG_CRC_START, (u8 *)buf, +@@ -121,7 +91,6 @@ static int bcm63xx_parse_cfe_partitions( + + kerneladdr = kerneladdr - BCM63XX_EXTENDED_SIZE; + rootfsaddr = rootfsaddr - BCM63XX_EXTENDED_SIZE; +- spareaddr = roundup(totallen, master->erasesize) + cfelen; + + if (rootfsaddr < kerneladdr) { + /* default Broadcom layout */ +@@ -130,8 +99,8 @@ static int bcm63xx_parse_cfe_partitions( + } else { + /* OpenWrt layout */ + rootfsaddr = kerneladdr + kernellen; +- rootfslen = buf->real_rootfs_length; +- spareaddr = rootfsaddr + rootfslen; ++ rootfslen = size - kernellen - ++ sizeof(*buf); + } + } else { + pr_warn("CFE boot tag CRC invalid (expected %08x, actual %08x)\n", +@@ -139,16 +108,153 @@ static int bcm63xx_parse_cfe_partitions( + kernellen = 0; + rootfslen = 0; + rootfsaddr = 0; +- spareaddr = cfelen; + } +- sparelen = min_not_zero(nvramaddr, caldataaddr1) - spareaddr; + +- /* Determine number of partitions */ +- if (rootfslen > 0) +- nrparts++; ++ if (kernellen > 0) { ++ int kernelpart = curr_part; + +- if (kernellen > 0) +- nrparts++; ++ if (rootfslen > 0 && rootfs_first) ++ kernelpart++; ++ pparts[kernelpart].name = "kernel"; ++ pparts[kernelpart].offset = kerneladdr; ++ pparts[kernelpart].size = kernellen; ++ curr_part++; ++ } ++ ++ if (rootfslen > 0) { ++ int rootfspart = curr_part; ++ ++ if (kernellen > 0 && rootfs_first) ++ rootfspart--; ++ pparts[rootfspart].name = "rootfs"; ++ pparts[rootfspart].offset = rootfsaddr; ++ pparts[rootfspart].size = rootfslen; ++ ++ curr_part++; ++ } ++ ++ vfree(buf); ++ ++ return curr_part - next_part; ++} ++ ++ ++static int bcm63xx_parse_cfe_partitions_of(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct device_node *dp = data->of_node; ++ struct device_node *pp; ++ int i, nr_parts = 0; ++ const char *partname; ++ int len; ++ ++ for_each_child_of_node(dp, pp) { ++ if (node_has_compatible(pp)) ++ continue; ++ ++ if (!of_get_property(pp, "reg", &len)) ++ continue; ++ ++ partname = of_get_property(pp, "label", &len); ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ ++ if (!strcmp(partname, "linux")) ++ nr_parts += 2; ++ ++ nr_parts++; ++ } ++ ++ *pparts = kzalloc(nr_parts * sizeof(**pparts), GFP_KERNEL); ++ if (!*pparts) ++ return -ENOMEM; ++ ++ i = 0; ++ for_each_child_of_node(dp, pp) { ++ const __be32 *reg; ++ int a_cells, s_cells; ++ size_t size, offset; ++ ++ if (node_has_compatible(pp)) ++ continue; ++ ++ reg = of_get_property(pp, "reg", &len); ++ if (!reg) ++ continue; ++ ++ a_cells = of_n_addr_cells(pp); ++ s_cells = of_n_size_cells(pp); ++ offset = of_read_number(reg, a_cells); ++ size = of_read_number(reg + a_cells, s_cells); ++ partname = of_get_property(pp, "label", &len); ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ ++ if (!strcmp(partname, "linux")) ++ i += parse_bcmtag(master, *pparts, i, offset, size); ++ ++ if (of_get_property(pp, "read-only", &len)) ++ (*pparts)[i].mask_flags |= MTD_WRITEABLE; ++ ++ if (of_get_property(pp, "lock", &len)) ++ (*pparts)[i].mask_flags |= MTD_POWERUP_LOCK; ++ ++ (*pparts)[i].offset = offset; ++ (*pparts)[i].size = size; ++ (*pparts)[i].name = partname; ++ ++ i++; ++ } ++ ++ return i; ++} ++ ++static int bcm63xx_parse_cfe_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ /* CFE, NVRAM and global Linux are always present */ ++ int nrparts = 5, curpart = 0; ++ struct mtd_partition *parts; ++ unsigned int nvramaddr; ++ unsigned int cfelen, nvramlen; ++ unsigned int cfe_erasesize; ++ unsigned int caldatalen1 = 0, caldataaddr1 = 0; ++ unsigned int caldatalen2 = 0, caldataaddr2 = 0; ++ unsigned int imageaddr, imagelen; ++ int i; ++ ++ if (!bcm63xx_is_cfe_present()) ++ return -EINVAL; ++ ++ cfe_erasesize = max_t(uint32_t, master->erasesize, ++ BCM63XX_CFE_BLOCK_SIZE); ++ ++ cfelen = cfe_erasesize; ++ nvramlen = bcm63xx_nvram_get_psi_size() * SZ_1K; ++ nvramlen = roundup(nvramlen, cfe_erasesize); ++ nvramaddr = master->size - nvramlen; ++ ++ if (data) { ++ if (data->caldata[0]) { ++ caldatalen1 = cfe_erasesize; ++ caldataaddr1 = rounddown(data->caldata[0], ++ cfe_erasesize); ++ } ++ if (data->caldata[1]) { ++ caldatalen2 = cfe_erasesize; ++ caldataaddr2 = rounddown(data->caldata[1], ++ cfe_erasesize); ++ } ++ if (caldataaddr1 == caldataaddr2) { ++ caldataaddr2 = 0; ++ caldatalen2 = 0; ++ } ++ } ++ ++ imageaddr = cfelen; ++ imagelen = min_not_zero(nvramaddr, caldataaddr1) - imageaddr; + + if (caldatalen1 > 0) + nrparts++; +@@ -158,10 +264,8 @@ static int bcm63xx_parse_cfe_partitions( + + /* Ask kernel for more memory */ + parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL); +- if (!parts) { +- vfree(buf); ++ if (!parts) + return -ENOMEM; +- } + + /* Start building partition list */ + parts[curpart].name = "CFE"; +@@ -169,29 +273,7 @@ static int bcm63xx_parse_cfe_partitions( + parts[curpart].size = cfelen; + curpart++; + +- if (kernellen > 0) { +- int kernelpart = curpart; +- +- if (rootfslen > 0 && rootfs_first) +- kernelpart++; +- parts[kernelpart].name = "kernel"; +- parts[kernelpart].offset = kerneladdr; +- parts[kernelpart].size = kernellen; +- curpart++; +- } +- +- if (rootfslen > 0) { +- int rootfspart = curpart; +- +- if (kernellen > 0 && rootfs_first) +- rootfspart--; +- parts[rootfspart].name = "rootfs"; +- parts[rootfspart].offset = rootfsaddr; +- parts[rootfspart].size = rootfslen; +- if (sparelen > 0 && !rootfs_first) +- parts[rootfspart].size += sparelen; +- curpart++; +- } ++ curpart += parse_bcmtag(master, parts, curpart, imageaddr, imagelen); + + if (caldatalen1 > 0) { + if (caldatalen2 > 0) +@@ -217,25 +299,33 @@ static int bcm63xx_parse_cfe_partitions( + + /* Global partition "linux" to make easy firmware upgrade */ + parts[curpart].name = "linux"; +- parts[curpart].offset = cfelen; +- parts[curpart].size = min_not_zero(nvramaddr, caldataaddr1) - cfelen; ++ parts[curpart].offset = imageaddr; ++ parts[curpart].size = imagelen; ++ curpart++; + +- for (i = 0; i < nrparts; i++) ++ for (i = 0; i < curpart; i++) + pr_info("Partition %d is %s offset %llx and length %llx\n", i, + parts[i].name, parts[i].offset, parts[i].size); + +- pr_info("Spare partition is offset %x and length %x\n", spareaddr, +- sparelen); +- + *pparts = parts; +- vfree(buf); + + return nrparts; + }; + ++ ++static int bcm63xx_parse_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ if (data && data->of_node) ++ return bcm63xx_parse_cfe_partitions_of(master, pparts, data); ++ else ++ return bcm63xx_parse_cfe_partitions(master, pparts, data); ++} ++ + static struct mtd_part_parser bcm63xx_cfe_parser = { + .owner = THIS_MODULE, +- .parse_fn = bcm63xx_parse_cfe_partitions, ++ .parse_fn = bcm63xx_parse_partitions, + .name = "bcm63xxpart", + }; + diff --git a/target/linux/brcm63xx/patches-3.18/426-bcm63xx_enet-fix-napi-poll-return-value.patch b/target/linux/brcm63xx/patches-3.18/426-bcm63xx_enet-fix-napi-poll-return-value.patch new file mode 100644 index 0000000..af34c23 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/426-bcm63xx_enet-fix-napi-poll-return-value.patch @@ -0,0 +1,27 @@ +From d150ac8f353cb1ab59288829db006300120c9daf Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 28 Feb 2015 20:23:13 +0100 +Subject: [PATCH] bcm63xx_enet: fix napi poll return value + +Commit d75b1ade567ffab ("net: less interrupt masking in NAPI") changed +the way how napi treated a returnvalue < budget, which causes hangs when +there there was tx_work_done, but rx_work_done is less than budget. + +To fix this, return budget instead of rx_done to ensure repolling. + +Signed-off-by: Jonas Gorski +--- + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -508,7 +508,7 @@ static int bcm_enet_poll(struct napi_str + + if (rx_work_done >= budget || tx_work_done > 0) { + /* rx/tx queue is not yet empty/clean */ +- return rx_work_done; ++ return budget; + } + + /* no more packet in rx/tx queue, remove device from poll diff --git a/target/linux/brcm63xx/patches-3.18/427-boards_probe_switch.patch b/target/linux/brcm63xx/patches-3.18/427-boards_probe_switch.patch new file mode 100644 index 0000000..b813d09 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/427-boards_probe_switch.patch @@ -0,0 +1,119 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -123,6 +123,8 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_enet0 = 1, + .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -166,6 +168,8 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_enet0 = 1, + .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -277,6 +281,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -339,6 +345,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -393,6 +401,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -453,6 +463,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -476,6 +488,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -495,6 +509,8 @@ static struct board_info __initdata boar + .has_enet1 = 1, + .enet0 = { + .has_phy = 1, ++ .phy_id = 0, ++ .has_phy = 1, + .use_internal_phy = 1, + }, + .enet1 = { +@@ -518,6 +534,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -546,6 +564,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -599,6 +619,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -648,6 +670,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -671,6 +695,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, diff --git a/target/linux/brcm63xx/patches-3.18/499-allow_better_context_for_board_patches.patch b/target/linux/brcm63xx/patches-3.18/499-allow_better_context_for_board_patches.patch new file mode 100644 index 0000000..bf51de0 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/499-allow_better_context_for_board_patches.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -61,7 +61,7 @@ static struct board_info __initdata boar + .ephy_reset_gpio = 36, + .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_3368 */ + + /* + * known 6328 boards +@@ -110,7 +110,7 @@ static struct board_info __initdata boar + }, + }, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6328 */ + + /* + * known 6338 boards +@@ -203,7 +203,7 @@ static struct board_info __initdata boar + }, + }, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6338 */ + + /* + * known 6345 boards +@@ -215,7 +215,7 @@ static struct board_info __initdata boar + + .has_uart0 = 1, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6345 */ + + /* + * known 6348 boards +@@ -542,7 +542,7 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* + * known 6358 boards +@@ -703,7 +703,7 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* + * all boards diff --git a/target/linux/brcm63xx/patches-3.18/500-board-D4PW.patch b/target/linux/brcm63xx/patches-3.18/500-board-D4PW.patch new file mode 100644 index 0000000..5a1a785 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/500-board-D4PW.patch @@ -0,0 +1,41 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -542,6 +542,22 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; ++ ++static struct board_info __initdata board_96348_D4PW = { ++ .name = "D-4P-W", ++ .expected_cpu_id = 0x6348, ++ ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .has_uart0 = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* +@@ -731,6 +747,7 @@ static const struct board_info __initcon + &board_DV201AMR, + &board_96348gw_a, + &board_rta1025w_16, ++ &board_96348_D4PW, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -762,6 +779,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, + { .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, }, + { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, ++ { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, diff --git a/target/linux/brcm63xx/patches-3.18/501-board-NB4.patch b/target/linux/brcm63xx/patches-3.18/501-board-NB4.patch new file mode 100644 index 0000000..79d638e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/501-board-NB4.patch @@ -0,0 +1,83 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -719,6 +719,62 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; ++ ++static struct board_info __initdata board_nb4_ser_r0 = { ++ .name = "NB4-SER-r0", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++}; ++ ++static struct board_info __initdata board_nb4_fxc_r1 = { ++ .name = "NB4-FXC-r1", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++}; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* +@@ -755,6 +811,8 @@ static const struct board_info __initcon + &board_96358vw2, + &board_AGPFS0, + &board_DWVS0, ++ &board_nb4_ser_r0, ++ &board_nb4_fxc_r1, + #endif + }; + +@@ -796,6 +854,8 @@ static struct of_device_id const bcm963x + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, }, + { .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, }, ++ { .compatible = "sfr,nb4-ser-r0", .data = &board_nb4_ser_r0, }, ++ { .compatible = "sfr,nb4-fxc-r1", .data = &board_nb4_fxc_r1, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 + #endif diff --git a/target/linux/brcm63xx/patches-3.18/502-board-96338W2_E7T.patch b/target/linux/brcm63xx/patches-3.18/502-board-96338W2_E7T.patch new file mode 100644 index 0000000..f35b76a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/502-board-96338W2_E7T.patch @@ -0,0 +1,39 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -203,6 +203,20 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_96338w2_e7t = { ++ .name = "96338W2_E7T", ++ .expected_cpu_id = 0x6338, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6338 */ + + /* +@@ -790,6 +804,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, + &board_96338w, ++ &board_96338w2_e7t, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, +@@ -827,6 +842,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6338 + { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, + { .compatible = "brcm,bcm96338w", .data = &board_96338w, }, ++ { .compatible = "d-link,dsl-2640u", .data = &board_96338w2_e7t, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + { .compatible = "brcm,bcm96345gw2", .data = &board_96345gw2, }, diff --git a/target/linux/brcm63xx/patches-3.18/503-board-CPVA642.patch b/target/linux/brcm63xx/patches-3.18/503-board-CPVA642.patch new file mode 100644 index 0000000..a102380 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/503-board-CPVA642.patch @@ -0,0 +1,45 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -685,6 +685,26 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_CPVA642 = { ++ .name = "CPVA642", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++}; ++ ++ + static struct board_info __initdata board_AGPFS0 = { + .name = "AGPF-S0", + .expected_cpu_id = 0x6358, +@@ -825,6 +845,7 @@ static const struct board_info __initcon + &board_96358vw, + &board_96358vw2, + &board_AGPFS0, ++ &board_CPVA642, + &board_DWVS0, + &board_nb4_ser_r0, + &board_nb4_fxc_r1, +@@ -872,6 +893,7 @@ static struct of_device_id const bcm963x + { .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, }, + { .compatible = "sfr,nb4-ser-r0", .data = &board_nb4_ser_r0, }, + { .compatible = "sfr,nb4-fxc-r1", .data = &board_nb4_fxc_r1, }, ++ { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 + #endif diff --git a/target/linux/brcm63xx/patches-3.18/504-board_dsl_274xb_rev_c.patch b/target/linux/brcm63xx/patches-3.18/504-board_dsl_274xb_rev_c.patch new file mode 100644 index 0000000..2cc7266 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/504-board_dsl_274xb_rev_c.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -754,6 +754,23 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + }; + ++/* D-Link DSL-274xB revison C2/C3 */ ++static struct board_info __initdata board_dsl_274xb_rev_c = { ++ .name = "AW4139", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ + static struct board_info __initdata board_nb4_ser_r0 = { + .name = "NB4-SER-r0", + .expected_cpu_id = 0x6358, +@@ -847,6 +864,7 @@ static const struct board_info __initcon + &board_AGPFS0, + &board_CPVA642, + &board_DWVS0, ++ &board_dsl_274xb_rev_c, + &board_nb4_ser_r0, + &board_nb4_fxc_r1, + #endif +@@ -886,6 +904,7 @@ static struct of_device_id const bcm963x + { .compatible = "alcatel,rg100a", .data = &board_96358vw2, }, + { .compatible = "brcm,bcm96358vw", .data = &board_96358vw, }, + { .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, }, ++ { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, + { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, diff --git a/target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch b/target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch new file mode 100644 index 0000000..bbc7f64 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/505-board_spw500v.patch @@ -0,0 +1,64 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -572,6 +572,45 @@ static struct board_info __initdata boar + .force_duplex_full = 1, + }, + }; ++ ++static struct sprom_fixup __initdata spw500v_fixups[] = { ++ { .offset = 46, .value = 0x3046 }, ++ { .offset = 47, .value = 0x15a7 }, ++ { .offset = 48, .value = 0xfa89 }, ++ { .offset = 49, .value = 0xfe79 }, ++ { .offset = 57, .value = 0x6a49 }, ++}; ++ ++static struct board_info __initdata board_spw500v = { ++ .name = "SPW500V", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 6, ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = spw500v_fixups, ++ .num_board_fixups = ARRAY_SIZE(spw500v_fixups), ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* +@@ -856,6 +895,7 @@ static const struct board_info __initcon + &board_96348gw_a, + &board_rta1025w_16, + &board_96348_D4PW, ++ &board_spw500v, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -897,6 +937,7 @@ static struct of_device_id const bcm963x + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, + { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, ++ { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, + { .compatible = "usr,9108", .data = &board_96348gw_a, }, + #endif diff --git a/target/linux/brcm63xx/patches-3.18/506-board_gw6200_gw6000.patch b/target/linux/brcm63xx/patches-3.18/506-board_gw6200_gw6000.patch new file mode 100644 index 0000000..6fc29df --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/506-board_gw6200_gw6000.patch @@ -0,0 +1,87 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -461,6 +461,66 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_gw6200 = { ++ .name = "GW6200", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 8, /* FIXME: What is real GPIO here? */ ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++}; ++ ++static struct board_info __initdata board_gw6000 = { ++ .name = "GW6000", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 6, ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++}; ++ ++ ++ + static struct board_info __initdata board_FAST2404 = { + .name = "F@ST2404", + .expected_cpu_id = 0x6348, +@@ -888,6 +948,8 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, + &board_96348gw, ++ &board_gw6000, ++ &board_gw6200, + &board_96348gw_10, + &board_96348gw_11, + &board_FAST2404, +@@ -938,6 +1000,8 @@ static struct of_device_id const bcm963x + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, + { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, ++ { .compatible = "tecom,gw6000", .data = &board_gw6000, }, ++ { .compatible = "tecom,gw6200", .data = &board_gw6200, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, + { .compatible = "usr,9108", .data = &board_96348gw_a, }, + #endif diff --git a/target/linux/brcm63xx/patches-3.18/507-board-MAGIC.patch b/target/linux/brcm63xx/patches-3.18/507-board-MAGIC.patch new file mode 100644 index 0000000..cc4f6c2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/507-board-MAGIC.patch @@ -0,0 +1,59 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -671,6 +671,40 @@ static struct board_info __initdata boar + .num_board_fixups = ARRAY_SIZE(spw500v_fixups), + }, + }; ++ ++static struct board_info __initdata board_96348sv = { ++ .name = "MAGIC", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ /* it has BP_ENET_EXTERNAL_PHY */ ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 25, ++ .gpio_int = 34, ++ .cs = 2, ++ .ext_irq = 2, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* +@@ -958,6 +992,7 @@ static const struct board_info __initcon + &board_rta1025w_16, + &board_96348_D4PW, + &board_spw500v, ++ &board_96348sv, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1002,6 +1037,7 @@ static struct of_device_id const bcm963x + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tecom,gw6000", .data = &board_gw6000, }, + { .compatible = "tecom,gw6200", .data = &board_gw6200, }, ++ { .compatible = "telsey,magic", .data = &board_96348sv, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, + { .compatible = "usr,9108", .data = &board_96348gw_a, }, + #endif diff --git a/target/linux/brcm63xx/patches-3.18/508-board_hw553.patch b/target/linux/brcm63xx/patches-3.18/508-board_hw553.patch new file mode 100644 index 0000000..2d71bab --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/508-board_hw553.patch @@ -0,0 +1,53 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -959,6 +959,34 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + .num_usbh_ports = 2, + }; ++ ++static struct board_info __initdata board_HW553 = { ++ .name = "HW553", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* +@@ -1004,6 +1032,7 @@ static const struct board_info __initcon + &board_dsl_274xb_rev_c, + &board_nb4_ser_r0, + &board_nb4_fxc_r1, ++ &board_HW553, + #endif + }; + +@@ -1047,6 +1076,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, }, + { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, ++ { .compatible = "huawei,hg553", .data = &board_HW553, }, + { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, }, diff --git a/target/linux/brcm63xx/patches-3.18/509-board_rta1320_16m.patch b/target/linux/brcm63xx/patches-3.18/509-board_rta1320_16m.patch new file mode 100644 index 0000000..ced00bd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/509-board_rta1320_16m.patch @@ -0,0 +1,40 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -217,6 +217,21 @@ static struct board_info __initdata boar + .force_duplex_full = 1, + }, + }; ++ ++static struct board_info __initdata board_rta1320_16m = { ++ .name = "RTA1320_16M", ++ .expected_cpu_id = 0x6338, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6338 */ + + /* +@@ -1003,6 +1018,7 @@ static const struct board_info __initcon + &board_96338gw, + &board_96338w, + &board_96338w2_e7t, ++ &board_rta1320_16m, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, +@@ -1047,6 +1063,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6338 + { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, + { .compatible = "brcm,bcm96338w", .data = &board_96338w, }, ++ { .compatible = "dynalink,rta1320", .data = &board_rta1320_16m, }, + { .compatible = "d-link,dsl-2640u", .data = &board_96338w2_e7t, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 diff --git a/target/linux/brcm63xx/patches-3.18/510-board_spw303v.patch b/target/linux/brcm63xx/patches-3.18/510-board_spw303v.patch new file mode 100644 index 0000000..f903bfc --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/510-board_spw303v.patch @@ -0,0 +1,40 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1002,6 +1002,21 @@ static struct board_info __initdata boar + .pci_dev = 1, + }, + }; ++ ++ /* T-Home Speedport W 303V Typ B */ ++static struct board_info __initdata board_spw303v = { ++ .name = "96358-502V", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* +@@ -1049,6 +1064,7 @@ static const struct board_info __initcon + &board_nb4_ser_r0, + &board_nb4_fxc_r1, + &board_HW553, ++ &board_spw303v, + #endif + }; + +@@ -1100,6 +1116,7 @@ static struct of_device_id const bcm963x + { .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, }, + { .compatible = "sfr,nb4-ser-r0", .data = &board_nb4_ser_r0, }, + { .compatible = "sfr,nb4-fxc-r1", .data = &board_nb4_fxc_r1, }, ++ { .compatible = "t-com,spw303v", .data = &board_spw303v, }, + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 diff --git a/target/linux/brcm63xx/patches-3.18/511-board_V2500V.patch b/target/linux/brcm63xx/patches-3.18/511-board_V2500V.patch new file mode 100644 index 0000000..5b7c789 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/511-board_V2500V.patch @@ -0,0 +1,93 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -720,6 +720,27 @@ static struct board_info __initdata boar + .ext_irq = 2, + }, + }; ++ ++static struct board_info __initdata board_V2500V_BB = { ++ .name = "V2500V_BB", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* +@@ -1052,6 +1073,7 @@ static const struct board_info __initcon + &board_96348_D4PW, + &board_spw500v, + &board_96348sv, ++ &board_V2500V_BB, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1091,6 +1113,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, + { .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, }, + { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, ++ { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, }, + { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, +@@ -1150,6 +1173,22 @@ void __init board_bcm963xx_init(void) + val &= MPI_CSBASE_BASE_MASK; + } + boot_addr = (u8 *)KSEG1ADDR(val); ++ printk(KERN_INFO PFX "Boot address 0x%08x\n",(unsigned int)boot_addr); ++ ++ /* BT Voyager 2500V (RTA1046VW PCB) has 8 Meg flash used as two */ ++ /* banks of 4 Meg. The byte at 0xBF800000 identifies the back to use.*/ ++ /* Loading firmware from the CFE Prompt always loads to Bank 0 */ ++ /* Do an early check of CFE and then select bank 0 */ ++ ++ if (boot_addr == (u8 *)0xbf800000) { ++ u8 *tmp_boot_addr = (u8*)0xbfc00000; ++ ++ bcm63xx_nvram_init(tmp_boot_addr + BCM963XX_NVRAM_OFFSET); ++ if (!strcmp(bcm63xx_nvram_get_name(), "V2500V_BB")) { ++ printk(KERN_INFO PFX "V2500V: nvram bank 0\n"); ++ boot_addr = tmp_boot_addr; ++ } ++ } + + /* dump cfe version */ + cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -20,6 +20,7 @@ + #include + #include + ++#include + #include + #include + #include +@@ -234,6 +235,13 @@ int __init bcm63xx_flash_register(int nu + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + ++ /* BT Voyager 2500V has 8 Meg flash in two 4 Meg banks */ ++ /* Loading from CFE always uses Bank 0 */ ++ if (!strcmp(board_get_name(), "V2500V_BB")) { ++ pr_info("V2500V: Start in Bank 0\n"); ++ val = val + 0x400000; // Select Bank 0 start address ++ } ++ + mtd_resources[0].start = val; + mtd_resources[0].end = 0x1FFFFFFF; + } diff --git a/target/linux/brcm63xx/patches-3.18/512-board_BTV2110.patch b/target/linux/brcm63xx/patches-3.18/512-board_BTV2110.patch new file mode 100644 index 0000000..1e1e856 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/512-board_BTV2110.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -415,6 +415,25 @@ static struct board_info __initdata boar + }, + }; + ++ ++/* BT Voyager 2110 */ ++static struct board_info __initdata board_V2110 = { ++ .name = "V2110", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -1074,6 +1093,7 @@ static const struct board_info __initcon + &board_spw500v, + &board_96348sv, + &board_V2500V_BB, ++ &board_V2110, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1113,6 +1133,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, + { .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, }, + { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, ++ { .compatible = "bt,v2110", .data = &board_V2110, }, + { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, }, + { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, diff --git a/target/linux/brcm63xx/patches-3.18/513-MIPS-BCM63XX-add-inventel-Livebox-support.patch b/target/linux/brcm63xx/patches-3.18/513-MIPS-BCM63XX-add-inventel-Livebox-support.patch new file mode 100644 index 0000000..3842f7b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/513-MIPS-BCM63XX-add-inventel-Livebox-support.patch @@ -0,0 +1,224 @@ +From e796582b499f0ba6acaa1ac3a10c09cceaab7702 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Mar 2014 04:55:52 +0100 +Subject: [PATCH] MIPS: BCM63XX: add inventel Livebox support + +--- + arch/mips/bcm63xx/boards/Kconfig | 6 + + arch/mips/bcm63xx/boards/Makefile | 1 + + arch/mips/bcm63xx/boards/board_common.c | 2 +- + arch/mips/bcm63xx/boards/board_common.h | 6 + + arch/mips/bcm63xx/boards/board_livebox.c | 215 ++++++++++++++++++++++++++++++ + 5 files changed, 229 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/boards/board_livebox.c + +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -12,4 +12,10 @@ config BOARD_BCM963XX + default y + help + ++config BOARD_LIVEBOX ++ bool "Inventel Livebox(es) boards" ++ select SSB ++ help ++ Inventel Livebox boards using the RedBoot bootloader. ++ + endmenu +--- a/arch/mips/bcm63xx/boards/Makefile ++++ b/arch/mips/bcm63xx/boards/Makefile +@@ -1,2 +1,3 @@ + obj-y += board_common.o + obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o ++obj-$(CONFIG_BOARD_LIVEBOX) += board_livebox.o +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -61,7 +61,7 @@ void __init board_prom_init(void) + if (fw_arg3 == CFE_EPTSEAL) + board_bcm963xx_init(); + else +- panic("unsupported bootloader detected"); ++ board_livebox_init(); + } + + static int (*board_get_mac_address)(u8 mac[ETH_ALEN]); +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -24,4 +24,10 @@ static inline void board_of_device_prese + } + #endif + ++#if defined(CONFIG_BOARD_LIVEBOX) ++void board_livebox_init(void); ++#else ++static inline void board_livebox_init(void) { } ++#endif ++ + #endif /* __BOARD_COMMON_H */ +--- /dev/null ++++ b/arch/mips/bcm63xx/boards/board_livebox.c +@@ -0,0 +1,164 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "board_common.h" ++ ++#define PFX "board_livebox: " ++ ++static unsigned int mac_addr_used = 0; ++ ++/* ++ * known 6348 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6348 ++static struct board_info __initdata board_livebox_blue5g = { ++ .name = "Livebox-blue-5g", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 31, ++ }, ++ ++ .ephy_reset_gpio = 6, ++ .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ ++ .has_dsp = 0, /*TODO some Liveboxes have dsp*/ ++ .dsp = { ++ .gpio_rst = 6, ++ .gpio_int = 35, ++ .cs = 2, ++ .ext_irq = 2, ++ }, ++}; ++#endif ++ ++/* ++ * all boards ++ */ ++static const struct board_info __initdata *bcm963xx_boards[] = { ++#ifdef CONFIG_BCM63XX_CPU_6348 ++ &board_livebox_blue5g ++#endif ++}; ++ ++static struct of_device_id const livebox_boards_dt[] = { ++ { .compatible = "inventel,livebox-blue-5g", .data = &board_livebox_blue5g, }, ++ { } ++}; ++ ++/* ++ * register & return a new board mac address ++ */ ++static int livebox_get_mac_address(u8 *mac) ++{ ++ u8 *p; ++ int count; ++ ++ memcpy(mac, (u8 *)0xBEBFF377, ETH_ALEN); ++ ++ p = mac + ETH_ALEN - 1; ++ count = mac_addr_used; ++ ++ while (count--) { ++ do { ++ (*p)++; ++ if (*p != 0) ++ break; ++ p--; ++ } while (p != mac); ++ } ++ ++ if (p == mac) { ++ printk(KERN_ERR PFX "unable to fetch mac address\n"); ++ return -ENODEV; ++ } ++ mac_addr_used++; ++ ++ return 0; ++} ++ ++/* ++ * early init callback ++ */ ++#define LIVEBOX_GPIO_DETECT_MASK 0x000000ff ++#define LIVEBOX_BOOT_ADDR 0x1e400000 ++ ++#define LIVEBOX_HW_BLUE5G_9 0x90 ++ ++void __init board_livebox_init(void) ++{ ++ u32 val; ++ u8 hw_version; ++ const struct board_info *board; ++ const struct of_device_id *board_match; ++ ++ /* find board by compat */ ++ board_match = bcm63xx_match_board(livebox_boards_dt); ++ if (board_match) { ++ board = board_match->data; ++ } else { ++ /* Get hardware version */ ++ val = bcm_gpio_readl(GPIO_CTL_LO_REG); ++ val &= ~LIVEBOX_GPIO_DETECT_MASK; ++ bcm_gpio_writel(val, GPIO_CTL_LO_REG); ++ ++ hw_version = bcm_gpio_readl(GPIO_DATA_LO_REG); ++ hw_version &= LIVEBOX_GPIO_DETECT_MASK; ++ ++ switch (hw_version) { ++ case LIVEBOX_HW_BLUE5G_9: ++ printk(KERN_INFO PFX "Livebox BLUE5G.9\n"); ++ board = bcm963xx_boards[0]; ++ break; ++ default: ++ printk(KERN_INFO PFX "Unknown livebox version: %02x\n", ++ hw_version); ++ /* use default livebox configuration */ ++ board = bcm963xx_boards[0]; ++ break; ++ } ++ } ++ ++ /* use default livebox configuration */ ++ board_early_setup(board, livebox_get_mac_address); ++ ++ /* read base address of boot chip select (0) */ ++ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); ++ val &= MPI_CSBASE_BASE_MASK; ++ if (val != LIVEBOX_BOOT_ADDR) { ++ printk(KERN_NOTICE PFX "flash address is: 0x%08x, forcing to: 0x%08x\n", ++ val, LIVEBOX_BOOT_ADDR); ++ bcm63xx_flash_force_phys_base_address(LIVEBOX_BOOT_ADDR, 0x1ebfffff); ++ } ++} diff --git a/target/linux/brcm63xx/patches-3.18/514-board_ct536_ct5621.patch b/target/linux/brcm63xx/patches-3.18/514-board_ct536_ct5621.patch new file mode 100644 index 0000000..45c71ae --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/514-board_ct536_ct5621.patch @@ -0,0 +1,54 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -434,6 +434,34 @@ static struct board_info __initdata boar + }; + + ++static struct board_info __initdata board_ct536_ct5621 = { ++ .name = "CT536_CT5621", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 0, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -1094,6 +1122,7 @@ static const struct board_info __initcon + &board_96348sv, + &board_V2500V_BB, + &board_V2110, ++ &board_ct536_ct5621, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1135,6 +1164,8 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, + { .compatible = "bt,v2110", .data = &board_V2110, }, + { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, }, ++ { .compatible = "comtrend,ct-536+", .data = &board_ct536_ct5621, }, ++ { .compatible = "comtrend,ct-5621", .data = &board_ct536_ct5621, }, + { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, diff --git a/target/linux/brcm63xx/patches-3.18/515-board_DWV-S0_fixes.patch b/target/linux/brcm63xx/patches-3.18/515-board_DWV-S0_fixes.patch new file mode 100644 index 0000000..9ed5eab --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/515-board_DWV-S0_fixes.patch @@ -0,0 +1,19 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -950,6 +950,8 @@ static struct board_info __initdata boar + .name = "DWV-S0", + .expected_cpu_id = 0x6358, + ++ .has_uart0 = 1, ++ + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, +@@ -968,6 +970,7 @@ static struct board_info __initdata boar + }, + + .has_ohci0 = 1, ++ .has_ehci0 = 1, + }; + + /* D-Link DSL-274xB revison C2/C3 */ diff --git a/target/linux/brcm63xx/patches-3.18/516-board_96348A-122.patch b/target/linux/brcm63xx/patches-3.18/516-board_96348A-122.patch new file mode 100644 index 0000000..0df9bbb --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/516-board_96348A-122.patch @@ -0,0 +1,50 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -462,6 +462,31 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_96348A_122 = { ++ .name = "96348A-122", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -1126,6 +1151,7 @@ static const struct board_info __initcon + &board_V2500V_BB, + &board_V2110, + &board_ct536_ct5621, ++ &board_96348A_122, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1168,6 +1194,7 @@ static struct of_device_id const bcm963x + { .compatible = "bt,v2110", .data = &board_V2110, }, + { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, }, + { .compatible = "comtrend,ct-536+", .data = &board_ct536_ct5621, }, ++ { .compatible = "comtrend,ct-5365", .data = &board_96348A_122, }, + { .compatible = "comtrend,ct-5621", .data = &board_ct536_ct5621, }, + { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, diff --git a/target/linux/brcm63xx/patches-3.18/517-RTA1205W_16_uart_fixes.patch b/target/linux/brcm63xx/patches-3.18/517-RTA1205W_16_uart_fixes.patch new file mode 100644 index 0000000..5233fae --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/517-RTA1205W_16_uart_fixes.patch @@ -0,0 +1,10 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -639,6 +639,7 @@ static struct board_info __initdata boar + .name = "RTA1025W_16", + .expected_cpu_id = 0x6348, + ++ .has_uart0 = 1, + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, diff --git a/target/linux/brcm63xx/patches-3.18/519_board_CPVA502plus.patch b/target/linux/brcm63xx/patches-3.18/519_board_CPVA502plus.patch new file mode 100644 index 0000000..f2e4324 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/519_board_CPVA502plus.patch @@ -0,0 +1,46 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -433,6 +433,27 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_CPVA502plus = { ++ .name = "CPVA502+", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ }, ++ ++ .ephy_reset_gpio = 4, ++ .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, ++}; + + static struct board_info __initdata board_ct536_ct5621 = { + .name = "CT536_CT5621", +@@ -1153,6 +1174,7 @@ static const struct board_info __initcon + &board_V2110, + &board_ct536_ct5621, + &board_96348A_122, ++ &board_CPVA502plus, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1205,6 +1227,7 @@ static struct of_device_id const bcm963x + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tecom,gw6000", .data = &board_gw6000, }, + { .compatible = "tecom,gw6200", .data = &board_gw6200, }, ++ { .compatible = "telsey,cpva502+", .data = &board_CPVA502plus, }, + { .compatible = "telsey,magic", .data = &board_96348sv, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, + { .compatible = "usr,9108", .data = &board_96348gw_a, }, diff --git a/target/linux/brcm63xx/patches-3.18/520-bcm63xx-add-support-for-96368MVWG-board.patch b/target/linux/brcm63xx/patches-3.18/520-bcm63xx-add-support-for-96368MVWG-board.patch new file mode 100644 index 0000000..d7543fc --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/520-bcm63xx-add-support-for-96368MVWG-board.patch @@ -0,0 +1,119 @@ +From eeacc2529942051504bc957726aa178671344421 Mon Sep 17 00:00:00 2001 +From: Maxime Bizon +Date: Wed, 20 Jan 2010 16:21:30 +0100 +Subject: [PATCH 32/63] bcm63xx: add support for 96368MVWG board. + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 95 ++++++++++++++++++++ + .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 2 + + 2 files changed, 97 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1138,6 +1138,59 @@ static struct board_info __initdata boar + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* ++ * known 6368 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6368 ++static struct board_info __initdata board_96368mvwg = { ++ .name = "96368MVWG", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port1", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port2", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 0x12, ++ .name = "port0", ++ }, ++ ++ [5] = { ++ .used = 1, ++ .phy_id = 0x11, ++ .name = "port3", ++ }, ++ }, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++}; ++#endif /* CONFIG_BCM63XX_CPU_6368 */ ++ ++/* + * all boards + */ + static const struct board_info __initconst *bcm963xx_boards[] = { +@@ -1189,6 +1242,10 @@ static const struct board_info __initcon + &board_HW553, + &board_spw303v, + #endif ++ ++#ifdef CONFIG_BCM63XX_CPU_6368 ++ &board_96368mvwg, ++#endif + }; + + static struct of_device_id const bcm963xx_boards_dt[] = { +@@ -1249,6 +1306,7 @@ static struct of_device_id const bcm963x + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 ++ { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + #endif +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -88,12 +88,25 @@ void __init board_early_setup(const stru + bcm63xx_pci_enabled = 1; + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G2_PCI; ++ ++ if (BCMCPU_IS_6368()) ++ val |= GPIO_MODE_6368_PCI_REQ1 | ++ GPIO_MODE_6368_PCI_GNT1 | ++ GPIO_MODE_6368_PCI_INTB | ++ GPIO_MODE_6368_PCI_REQ0 | ++ GPIO_MODE_6368_PCI_GNT0; + } + #endif + + if (board.has_pccard) { + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G1_MII_PCCARD; ++ ++ if (BCMCPU_IS_6368()) ++ val |= GPIO_MODE_6368_PCMCIA_CD1 | ++ GPIO_MODE_6368_PCMCIA_CD2 | ++ GPIO_MODE_6368_PCMCIA_VS1 | ++ GPIO_MODE_6368_PCMCIA_VS2; + } + + if (board.has_enet0 && !board.enet0.use_internal_phy) { diff --git a/target/linux/brcm63xx/patches-3.18/521-bcm63xx-add-support-for-96368MVNgr-board.patch b/target/linux/brcm63xx/patches-3.18/521-bcm63xx-add-support-for-96368MVNgr-board.patch new file mode 100644 index 0000000..6ec6cf3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/521-bcm63xx-add-support-for-96368MVNgr-board.patch @@ -0,0 +1,74 @@ +From f457fc2eb9bb915b5a4d251c7c68d4694cf07b01 Mon Sep 17 00:00:00 2001 +From: Maxime Bizon +Date: Fri, 4 Nov 2011 12:33:48 +0100 +Subject: [PATCH 33/63] bcm63xx: add support for 96368MVNgr board. + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 67 +++++++++++++++++++++++++++++ + 1 files changed, 67 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1188,6 +1188,46 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_ehci0 = 1, + }; ++ ++static struct board_info __initdata board_96368mvngr = { ++ .name = "96368MVNgr", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++}; + #endif /* CONFIG_BCM63XX_CPU_6368 */ + + /* +@@ -1245,6 +1285,7 @@ static const struct board_info __initcon + + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, ++ &board_96368mvngr, + #endif + }; + +@@ -1306,6 +1347,7 @@ static struct of_device_id const bcm963x + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 ++ { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 diff --git a/target/linux/brcm63xx/patches-3.18/522-MIPS-BCM63XX-add-96328avng-reference-board.patch b/target/linux/brcm63xx/patches-3.18/522-MIPS-BCM63XX-add-96328avng-reference-board.patch new file mode 100644 index 0000000..5ca3954 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/522-MIPS-BCM63XX-add-96328avng-reference-board.patch @@ -0,0 +1,45 @@ +From c93c2bbf0cc96da5a47d77f01daf6c983cfe4216 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 May 2012 10:52:25 +0200 +Subject: [PATCH] MIPS: BCM63XX: add 96328avng reference board + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 77 +++++++++++++++++++++++++++++ + 1 files changed, 77 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -109,6 +109,33 @@ static struct board_info __initdata boar + .active_low = 1, + }, + }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, + }; + #endif /* CONFIG_BCM63XX_CPU_6328 */ + diff --git a/target/linux/brcm63xx/patches-3.18/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch b/target/linux/brcm63xx/patches-3.18/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch new file mode 100644 index 0000000..b01a0d4 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch @@ -0,0 +1,69 @@ +From f0649f7b7c672cf452a1796a1422bf615e1973f8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 May 2012 11:01:12 +0200 +Subject: [PATCH] MIPS: BCM63XX: add 963281TAN reference board + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 71 +++++++++++++++++++++++++++++ + 1 files changed, 71 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -137,6 +137,41 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_963281TAN = { ++ .name = "963281TAN", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6328 */ + + /* +@@ -1266,6 +1301,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_963281TAN, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, +@@ -1322,6 +1358,7 @@ static struct of_device_id const bcm963x + { .compatible = "netgear,cvg834g", .data = &board_cvg834g, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 ++ { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 diff --git a/target/linux/brcm63xx/patches-3.18/524-board_dsl_274xb_rev_f.patch b/target/linux/brcm63xx/patches-3.18/524-board_dsl_274xb_rev_f.patch new file mode 100644 index 0000000..0d61f97 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/524-board_dsl_274xb_rev_f.patch @@ -0,0 +1,80 @@ +From 66808f706b3dcd83a9f5157997ff478a880a2906 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 30 Apr 2012 09:10:51 +0200 +Subject: [PATCH 70/79] MIPS: BCM63XX: Add board definition for D-Link + DSL-274xB rev F1 + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 104 +++++++++++++++++++++++++++++ + 1 files changed, 104 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -172,6 +172,51 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_dsl_274xb_f1 = { ++ .name = "AW4339U", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0x7d1000, ++ .slot = 0, ++ .led_pin = -1, ++ }, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 4", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 3", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 2", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 1", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6328 */ + + /* +@@ -1302,6 +1347,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_963281TAN, ++ &board_dsl_274xb_f1, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, +@@ -1360,6 +1406,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, ++ { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, diff --git a/target/linux/brcm63xx/patches-3.18/525-board_96348w3.patch b/target/linux/brcm63xx/patches-3.18/525-board_96348w3.patch new file mode 100644 index 0000000..8c83433 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/525-board_96348w3.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -833,6 +833,25 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + }; + ++/* NetGear DG834G v4 */ ++static struct board_info __initdata board_96348W3 = { ++ .name = "96348W3", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++}; ++ + static struct board_info __initdata board_96348_D4PW = { + .name = "D-4P-W", + .expected_cpu_id = 0x6348, +@@ -1377,6 +1396,7 @@ static const struct board_info __initcon + &board_ct536_ct5621, + &board_96348A_122, + &board_CPVA502plus, ++ &board_96348W3, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1432,6 +1452,7 @@ static struct of_device_id const bcm963x + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, ++ { .compatible = "netgear,dg834g-v4", .data = &board_96348W3, }, + { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tecom,gw6000", .data = &board_gw6000, }, diff --git a/target/linux/brcm63xx/patches-3.18/526-board_CT6373-1.patch b/target/linux/brcm63xx/patches-3.18/526-board_CT6373-1.patch new file mode 100644 index 0000000..3bd7eca --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/526-board_CT6373-1.patch @@ -0,0 +1,50 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1219,6 +1219,31 @@ static struct board_info __initdata boar + .num_usbh_ports = 2, + }; + ++static struct board_info __initdata board_ct6373_1 = { ++ .name = "CT6373-1", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_HW553 = { + .name = "HW553", + .expected_cpu_id = 0x6358, +@@ -1408,6 +1433,7 @@ static const struct board_info __initcon + &board_dsl_274xb_rev_c, + &board_nb4_ser_r0, + &board_nb4_fxc_r1, ++ &board_ct6373_1, + &board_HW553, + &board_spw303v, + #endif +@@ -1466,6 +1492,7 @@ static struct of_device_id const bcm963x + { .compatible = "alcatel,rg100a", .data = &board_96358vw2, }, + { .compatible = "brcm,bcm96358vw", .data = &board_96358vw, }, + { .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, }, ++ { .compatible = "comtrend,ct-6373", .data = &board_ct6373_1, }, + { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, + { .compatible = "huawei,hg553", .data = &board_HW553, }, diff --git a/target/linux/brcm63xx/patches-3.18/527-board_dva-g3810bn-tl-1.patch b/target/linux/brcm63xx/patches-3.18/527-board_dva-g3810bn-tl-1.patch new file mode 100644 index 0000000..792f504 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/527-board_dva-g3810bn-tl-1.patch @@ -0,0 +1,55 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1286,6 +1286,36 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + }; ++ ++/* D-Link DVA-G3810BN/TL */ ++static struct board_info __initdata board_DVAG3810BN = { ++ .name = "DVAG3810BN", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 0, ++ .use_internal_phy = 1, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++}; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* +@@ -1436,6 +1466,7 @@ static const struct board_info __initcon + &board_ct6373_1, + &board_HW553, + &board_spw303v, ++ &board_DVAG3810BN, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6368 +@@ -1495,6 +1526,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,ct-6373", .data = &board_ct6373_1, }, + { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, ++ { .compatible = "d-link,dva-g3810bn/tl", .data = &board_DVAG3810BN, }, + { .compatible = "huawei,hg553", .data = &board_HW553, }, + { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, diff --git a/target/linux/brcm63xx/patches-3.18/528-board_nb6.patch b/target/linux/brcm63xx/patches-3.18/528-board_nb6.patch new file mode 100644 index 0000000..173c2d2 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/528-board_nb6.patch @@ -0,0 +1,112 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -12,6 +12,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -31,6 +33,9 @@ + #define BCM963XX_KEYS_POLL_INTERVAL 20 + #define BCM963XX_KEYS_DEBOUNCE_INTERVAL (BCM963XX_KEYS_POLL_INTERVAL * 3) + ++#define NB6_GPIO_RTL8367_SDA 18 ++#define NB6_GPIO_RTL8367_SCK 20 ++ + /* + * known 3368 boards + */ +@@ -1318,6 +1323,69 @@ static struct board_info __initdata boar + }; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++static struct rtl8367_extif_config nb6_rtl8367_extif0_cfg = { ++ .mode = RTL8367_EXTIF_MODE_RGMII, ++ .txdelay = 1, ++ .rxdelay = 5, ++ .ability = { ++ .force_mode = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ .link = 1, ++ .duplex = 1, ++ .speed = RTL8367_PORT_SPEED_1000, ++ }, ++}; ++ ++static struct rtl8367_platform_data nb6_rtl8367_data = { ++ .gpio_sda = NB6_GPIO_RTL8367_SDA, ++ .gpio_sck = NB6_GPIO_RTL8367_SCK, ++ .extif0_cfg = &nb6_rtl8367_extif0_cfg, ++}; ++ ++static struct platform_device nb6_rtl8367_device = { ++ .name = RTL8367_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &nb6_rtl8367_data, ++ } ++}; ++ ++static struct platform_device * __initdata nb6_devices[] = { ++ &nb6_rtl8367_device, ++}; ++ ++static struct board_info __initdata board_nb6 = { ++ .name = "NB6", ++ .expected_cpu_id = 0x6362, ++ ++ .has_uart0 = 1, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [4] = { ++ .used = 1, ++ .phy_id = 0xff, ++ .bypass_link = 1, ++ .force_speed = 1000, ++ .force_duplex_full = 1, ++ .name = "RGMII", ++ }, ++ }, ++ }, ++ ++ .devs = nb6_devices, ++ .num_devs = ARRAY_SIZE(nb6_devices), ++}; ++#endif /* CONFIG_BCM63XX_CPU_6362 */ ++ + /* + * known 6368 boards + */ +@@ -1469,6 +1537,10 @@ static const struct board_info __initcon + &board_DVAG3810BN, + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++ &board_nb6, ++#endif ++ + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, +@@ -1537,6 +1609,9 @@ static struct of_device_id const bcm963x + { .compatible = "t-com,spw303v", .data = &board_spw303v, }, + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif ++#ifdef CONFIG_BCM63XX_CPU_6362 ++ { .compatible = "sfr,nb6-ser-r0", .data = &board_nb6, }, ++#endif + #ifdef CONFIG_BCM63XX_CPU_6368 + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, diff --git a/target/linux/brcm63xx/patches-3.18/529-board_fast2604.patch b/target/linux/brcm63xx/patches-3.18/529-board_fast2604.patch new file mode 100644 index 0000000..dc31325 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/529-board_fast2604.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -768,6 +768,23 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct board_info __initdata board_FAST2604 = { ++ .name = "F@ST2604", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ + static struct board_info __initdata board_rta1025w_16 = { + .name = "RTA1025W_16", + .expected_cpu_id = 0x6348, +@@ -1508,6 +1525,7 @@ static const struct board_info __initcon + &board_96348gw_10, + &board_96348gw_11, + &board_FAST2404, ++ &board_FAST2604, + &board_DV201AMR, + &board_96348gw_a, + &board_rta1025w_16, +@@ -1583,6 +1601,7 @@ static struct of_device_id const bcm963x + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, + { .compatible = "netgear,dg834g-v4", .data = &board_96348W3, }, + { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, ++ { .compatible = "sagem,f@st2604", .data = &board_FAST2604, }, + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tecom,gw6000", .data = &board_gw6000, }, + { .compatible = "tecom,gw6200", .data = &board_gw6200, }, diff --git a/target/linux/brcm63xx/patches-3.18/530-board_A4001N1.patch b/target/linux/brcm63xx/patches-3.18/530-board_A4001N1.patch new file mode 100644 index 0000000..6ce8573 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/530-board_A4001N1.patch @@ -0,0 +1,69 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -178,6 +178,50 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_A4001N1 = { ++ .name = "963281T_TEF", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43225, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ }, ++}; ++ + static struct board_info __initdata board_dsl_274xb_f1 = { + .name = "AW4339U", + .expected_cpu_id = 0x6328, +@@ -1506,6 +1550,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_963281TAN, ++ &board_A4001N1, + &board_dsl_274xb_f1, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 +@@ -1571,6 +1616,7 @@ static struct of_device_id const bcm963x + { .compatible = "netgear,cvg834g", .data = &board_cvg834g, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 ++ { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, + { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, diff --git a/target/linux/brcm63xx/patches-3.18/531-board_AR-5387un.patch b/target/linux/brcm63xx/patches-3.18/531-board_AR-5387un.patch new file mode 100644 index 0000000..000794a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/531-board_AR-5387un.patch @@ -0,0 +1,98 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -143,6 +143,79 @@ static struct board_info __initdata boar + }, + }; + ++static struct sprom_fixup __initdata ar5387un_fixups[] = { ++ { .offset = 2, .value = 0x05bb }, ++ { .offset = 65, .value = 0x1204 }, ++ { .offset = 78, .value = 0x0303 }, ++ { .offset = 79, .value = 0x0202 }, ++ { .offset = 80, .value = 0xff02 }, ++ { .offset = 87, .value = 0x0315 }, ++ { .offset = 88, .value = 0x0315 }, ++ { .offset = 96, .value = 0x2048 }, ++ { .offset = 97, .value = 0xff11 }, ++ { .offset = 98, .value = 0x1567 }, ++ { .offset = 99, .value = 0xfb24 }, ++ { .offset = 100, .value = 0x3e3c }, ++ { .offset = 101, .value = 0x4038 }, ++ { .offset = 102, .value = 0xfe7f }, ++ { .offset = 103, .value = 0x1279 }, ++ { .offset = 112, .value = 0x2048 }, ++ { .offset = 113, .value = 0xff03 }, ++ { .offset = 114, .value = 0x154c }, ++ { .offset = 115, .value = 0xfb27 }, ++ { .offset = 116, .value = 0x3e3c }, ++ { .offset = 117, .value = 0x4038 }, ++ { .offset = 118, .value = 0xfe87 }, ++ { .offset = 119, .value = 0x1233 }, ++ { .offset = 203, .value = 0x2226 }, ++}; ++ ++static struct board_info __initdata board_AR5387un = { ++ .name = "96328A-1441N1", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43225, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ .board_fixups = ar5387un_fixups, ++ .num_board_fixups = ARRAY_SIZE(ar5387un_fixups), ++ }, ++}; ++ + static struct board_info __initdata board_963281TAN = { + .name = "963281TAN", + .expected_cpu_id = 0x6328, +@@ -1549,6 +1622,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_AR5387un, + &board_963281TAN, + &board_A4001N1, + &board_dsl_274xb_f1, +@@ -1619,6 +1693,7 @@ static struct of_device_id const bcm963x + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, ++ { .compatible = "comtrend,ar-5387un", .data = &board_AR5387un, }, + { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 diff --git a/target/linux/brcm63xx/patches-3.18/532-board_AR-5381u.patch b/target/linux/brcm63xx/patches-3.18/532-board_AR-5381u.patch new file mode 100644 index 0000000..3b79f0f --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/532-board_AR-5381u.patch @@ -0,0 +1,80 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -143,6 +143,61 @@ static struct board_info __initdata boar + }, + }; + ++static struct sprom_fixup __initdata ar5381u_fixups[] = { ++ { .offset = 97, .value = 0xfee5 }, ++ { .offset = 98, .value = 0x157c }, ++ { .offset = 99, .value = 0xfae7 }, ++ { .offset = 113, .value = 0xfefa }, ++ { .offset = 114, .value = 0x15d6 }, ++ { .offset = 115, .value = 0xfaf8 }, ++}; ++ ++static struct board_info __initdata board_AR5381u = { ++ .name = "96328A-1241N", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43225, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ .board_fixups = ar5381u_fixups, ++ .num_board_fixups = ARRAY_SIZE(ar5381u_fixups), ++ }, ++}; ++ + static struct sprom_fixup __initdata ar5387un_fixups[] = { + { .offset = 2, .value = 0x05bb }, + { .offset = 65, .value = 0x1204 }, +@@ -1622,6 +1677,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_AR5381u, + &board_AR5387un, + &board_963281TAN, + &board_A4001N1, +@@ -1693,6 +1749,7 @@ static struct of_device_id const bcm963x + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, ++ { .compatible = "comtrend,ar-5381u", .data = &board_AR5381u, }, + { .compatible = "comtrend,ar-5387un", .data = &board_AR5387un, }, + { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, + #endif diff --git a/target/linux/brcm63xx/patches-3.18/533-board_rta770bw.patch b/target/linux/brcm63xx/patches-3.18/533-board_rta770bw.patch new file mode 100644 index 0000000..cbff51e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/533-board_rta770bw.patch @@ -0,0 +1,41 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -528,6 +528,22 @@ static struct board_info __initdata boar + + .has_uart0 = 1, + }; ++ ++static struct board_info __initdata board_rta770bw = { ++ .name = "RTA770BW", ++ .expected_cpu_id = 0x6345, ++ ++ .has_uart0 = 1, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6345 */ + + /* +@@ -1691,6 +1707,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, ++ &board_rta770bw, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, +@@ -1761,6 +1778,7 @@ static struct of_device_id const bcm963x + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + { .compatible = "brcm,bcm96345gw2", .data = &board_96345gw2, }, ++ { .compatible = "dynalink,rta770bw", .data = &board_rta770bw, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + { .compatible = "belkin,f5d7633", .data = &board_96348gw_10, }, diff --git a/target/linux/brcm63xx/patches-3.18/534-board_hw556.patch b/target/linux/brcm63xx/patches-3.18/534-board_hw556.patch new file mode 100644 index 0000000..85f2c3e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/534-board_hw556.patch @@ -0,0 +1,124 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1482,6 +1483,93 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_HW556_C = { ++ .name = "HW556_C", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_RALINK, ++ .caldata_offset = 0xeffe00, ++ .slot = 1, ++ .eeprom = "rt2x00.eeprom", ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++static struct board_info __initdata board_HW556_A = { ++ .name = "HW556_A", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0xf7e000, ++ .slot = 1, ++ .endian_check = 1, ++ .led_pin = 2, ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++static struct board_info __initdata board_HW556_B = { ++ .name = "HW556_B", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0xefe000, ++ .slot = 1, ++ .endian_check = 1, ++ .led_pin = 2, ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ + /* T-Home Speedport W 303V Typ B */ + static struct board_info __initdata board_spw303v = { + .name = "96358-502V", +@@ -1743,6 +1831,9 @@ static const struct board_info __initcon + &board_nb4_fxc_r1, + &board_ct6373_1, + &board_HW553, ++ &board_HW556_A, ++ &board_HW556_B, ++ &board_HW556_C, + &board_spw303v, + &board_DVAG3810BN, + #endif +@@ -1815,6 +1906,9 @@ static struct of_device_id const bcm963x + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, + { .compatible = "d-link,dva-g3810bn/tl", .data = &board_DVAG3810BN, }, + { .compatible = "huawei,hg553", .data = &board_HW553, }, ++ { .compatible = "huawei,hg556a-a", .data = &board_HW556_A, }, ++ { .compatible = "huawei,hg556a-b", .data = &board_HW556_B, }, ++ { .compatible = "huawei,hg556a-c", .data = &board_HW556_C, }, + { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, }, diff --git a/target/linux/brcm63xx/patches-3.18/535-board_rta770w.patch b/target/linux/brcm63xx/patches-3.18/535-board_rta770w.patch new file mode 100644 index 0000000..0697299 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/535-board_rta770w.patch @@ -0,0 +1,46 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -545,6 +545,27 @@ static struct board_info __initdata boar + .force_duplex_full = 1, + }, + }; ++ ++// Actually this board is the very same as the rta770bw, ++// where the additional 'b' within the name just ++// just indicates 'Annex B'. The ADSL Modem itself is able ++// to handle both Annex A as well as Annex B - ++// the loaded firmware makes the only difference ++static struct board_info __initdata board_rta770w = { ++ .name = "RTA770W", ++ .expected_cpu_id = 0x6345, ++ ++ .has_uart0 = 1, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6345 */ + + /* +@@ -1796,6 +1817,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, + &board_rta770bw, ++ &board_rta770w, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, +@@ -1870,6 +1892,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6345 + { .compatible = "brcm,bcm96345gw2", .data = &board_96345gw2, }, + { .compatible = "dynalink,rta770bw", .data = &board_rta770bw, }, ++ { .compatible = "dynalink,rta770w", .data = &board_rta770w, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + { .compatible = "belkin,f5d7633", .data = &board_96348gw_10, }, diff --git a/target/linux/brcm63xx/patches-3.18/536-board_fast2704.patch b/target/linux/brcm63xx/patches-3.18/536-board_fast2704.patch new file mode 100644 index 0000000..6546e5d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/536-board_fast2704.patch @@ -0,0 +1,75 @@ +From: Marcin Jurkowski +Date: Thu, 31 Oct 2013 22:33:10 +0000 +Subject: [PATCH] bcm63xx: Add kernel support for Sagemcom F@ST2704V2 ADSL + router + +This adds kernel support support for Sagemcom F@st 2704 wireless ADSL +router. +It's a BCM6328-based 802.11n wireless router with USB port and ADSL2+ +modem equipped with 64 MiB RAM and 8 MiB flash. + +Signed-off-by: Marcin Jurkowski +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -395,6 +395,44 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_FAST2704V2 = { ++ .name = "F@ST2704V2", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .has_usbd = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6328 */ + + /* +@@ -1807,6 +1845,7 @@ static const struct board_info __initcon + &board_963281TAN, + &board_A4001N1, + &board_dsl_274xb_f1, ++ &board_FAST2704V2, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, +@@ -1882,6 +1921,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,ar-5381u", .data = &board_AR5381u, }, + { .compatible = "comtrend,ar-5387un", .data = &board_AR5387un, }, + { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, ++ { .compatible = "sagem,f@st2704v2", .data = &board_FAST2704V2, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, diff --git a/target/linux/brcm63xx/patches-3.18/537-board_fast2504n.patch b/target/linux/brcm63xx/patches-3.18/537-board_fast2504n.patch new file mode 100644 index 0000000..b423df3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/537-board_fast2504n.patch @@ -0,0 +1,68 @@ +From: Max Staudt +Date: Wed, 15 Jan 2014 18:51:13 +0000 +Subject: [PATCH] brcm63xx: F@ST2504n board support (Linux-3.10.26) + +Signed-off-by: Max Staudt +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1736,6 +1736,43 @@ static struct board_info __initdata boar + .devs = nb6_devices, + .num_devs = ARRAY_SIZE(nb6_devices), + }; ++ ++static struct board_info __initdata board_fast2504n = { ++ .name = "F@ST2504n", ++ .expected_cpu_id = 0x6362, ++ ++ .has_uart0 = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6362 */ + + /* +@@ -1901,6 +1938,7 @@ static const struct board_info __initcon + + #ifdef CONFIG_BCM63XX_CPU_6362 + &board_nb6, ++ &board_fast2504n, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6368 +@@ -1982,6 +2020,7 @@ static struct of_device_id const bcm963x + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6362 ++ { .compatible = "sagem,f@st2504n", .data = &board_fast2504n, }, + { .compatible = "sfr,nb6-ser-r0", .data = &board_nb6, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 diff --git a/target/linux/brcm63xx/patches-3.18/550-MIPS-BCM63XX-remove-leds-and-buttons.patch b/target/linux/brcm63xx/patches-3.18/550-MIPS-BCM63XX-remove-leds-and-buttons.patch new file mode 100644 index 0000000..4bd3695 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/550-MIPS-BCM63XX-remove-leds-and-buttons.patch @@ -0,0 +1,343 @@ +From 997f53b174c63153335508c22dc4493e8e5808d6 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 22 Feb 2015 17:52:32 +0100 +Subject: [PATCH] MIPS: BCM63XX: remove leds and buttons + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 262 ----------------------------- + 1 file changed, 262 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -56,14 +56,6 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + +- .leds = { +- { +- .name = "CVG834G:green:power", +- .gpio = 37, +- .default_trigger= "default-on", +- }, +- }, +- + .ephy_reset_gpio = 36, + .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, + }; +@@ -87,35 +79,6 @@ static struct board_info __initdata boar + .port_no = 0, + }, + +- .leds = { +- { +- .name = "96328avng::ppp-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "96328avng::power", +- .gpio = 4, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "96328avng::power-fail", +- .gpio = 8, +- .active_low = 1, +- }, +- { +- .name = "96328avng::wps", +- .gpio = 9, +- .active_low = 1, +- }, +- { +- .name = "96328avng::ppp", +- .gpio = 11, +- .active_low = 1, +- }, +- }, +- + .has_enetsw = 1, + + .enetsw = { +@@ -453,35 +416,6 @@ static struct board_info __initdata boar + }, + + .has_ohci0 = 1, +- +- .leds = { +- { +- .name = "adsl", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ses", +- .gpio = 5, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- } +- }, + }; + + static struct board_info __initdata board_96338w = { +@@ -496,35 +430,6 @@ static struct board_info __initdata boar + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +- +- .leds = { +- { +- .name = "adsl", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ses", +- .gpio = 5, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_96338w2_e7t = { +@@ -623,36 +528,6 @@ static struct board_info __initdata boar + .has_phy = 1, + .use_internal_phy = 1, + }, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_96348gw_10 = { +@@ -687,35 +562,6 @@ static struct board_info __initdata boar + .cs = 2, + .ext_irq = 2, + }, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_96348gw_11 = { +@@ -744,35 +590,6 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + +@@ -898,35 +715,6 @@ static struct board_info __initdata boar + .ext_irq = 2, + .cs = 2, + }, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_gw6200 = { +@@ -1263,33 +1051,6 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 15, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 22, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 23, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 4, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 5, +- }, +- }, + }; + + static struct board_info __initdata board_96358vw2 = { +@@ -1319,29 +1080,6 @@ static struct board_info __initdata boar + .has_pccard = 1, + .has_ehci0 = 1, + .num_usbh_ports = 2, +- +- .leds = { +- { +- .name = "adsl", +- .gpio = 22, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 23, +- }, +- { +- .name = "power", +- .gpio = 5, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 4, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_CPVA642 = { diff --git a/target/linux/brcm63xx/patches-3.18/555-board_96318ref.patch b/target/linux/brcm63xx/patches-3.18/555-board_96318ref.patch new file mode 100644 index 0000000..595ac07 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/555-board_96318ref.patch @@ -0,0 +1,79 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -62,6 +62,56 @@ static struct board_info __initdata boar + #endif /* CONFIG_BCM63XX_CPU_3368 */ + + /* ++ * known 6318 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6318 ++static struct board_info __initdata board_96318ref = { ++ .name = "96318REF", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; ++#endif /* CONFIG_BCM63XX_CPU_6318 */ ++ ++/* + * known 6328 boards + */ + #ifdef CONFIG_BCM63XX_CPU_6328 +@@ -1613,6 +1663,9 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_3368 + &board_cvg834g, + #endif ++#ifdef CONFIG_BCM63XX_CPU_6318 ++ &board_96318ref, ++#endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_AR5381u, +@@ -1690,6 +1743,9 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_3368 + { .compatible = "netgear,cvg834g", .data = &board_cvg834g, }, + #endif ++#ifdef CONFIG_BCM63XX_CPU_6318 ++ { .compatible = "brcm,bcm96318ref", .data = &board_96318ref, }, ++#endif + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, diff --git a/target/linux/brcm63xx/patches-3.18/556-board_96318ref_p300.patch b/target/linux/brcm63xx/patches-3.18/556-board_96318ref_p300.patch new file mode 100644 index 0000000..81493fd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/556-board_96318ref_p300.patch @@ -0,0 +1,70 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -109,6 +109,51 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_96318ref_p300 = { ++ .name = "96318REF_P300", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6318 */ + + /* +@@ -1665,6 +1710,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6318 + &board_96318ref, ++ &board_96318ref_p300, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, +@@ -1745,6 +1791,7 @@ static struct of_device_id const bcm963x + #endif + #ifdef CONFIG_BCM63XX_CPU_6318 + { .compatible = "brcm,bcm96318ref", .data = &board_96318ref, }, ++ { .compatible = "brcm,bcm96318ref_p300", .data = &board_96318ref_p300, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, diff --git a/target/linux/brcm63xx/patches-3.18/557-board_bcm963269bhr.patch b/target/linux/brcm63xx/patches-3.18/557-board_bcm963269bhr.patch new file mode 100644 index 0000000..1dcfea8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/557-board_bcm963269bhr.patch @@ -0,0 +1,73 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1702,6 +1702,52 @@ static struct board_info __initdata boar + #endif /* CONFIG_BCM63XX_CPU_6368 */ + + /* ++ * known 63268/63269 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_63268 ++static struct board_info __initdata board_963269bhr = { ++ .name = "963269BHR", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_pci = 1, ++ ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++}; ++#endif /* CONFIG_BCM63XX_CPU_63268 */ ++ ++/* + * all boards + */ + static const struct board_info __initconst *bcm963xx_boards[] = { +@@ -1782,6 +1828,9 @@ static const struct board_info __initcon + &board_96368mvwg, + &board_96368mvngr, + #endif ++#ifdef CONFIG_BCM63XX_CPU_63268 ++ &board_963269bhr, ++#endif + }; + + static struct of_device_id const bcm963xx_boards_dt[] = { +@@ -1869,6 +1918,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 ++ { .compatible = "brcm,bcm963269bhr", .data = &board_963269bhr, }, + #endif + #endif /* CONFIG_OF */ + { }, diff --git a/target/linux/brcm63xx/patches-3.18/558-board_AR1004G.patch b/target/linux/brcm63xx/patches-3.18/558-board_AR1004G.patch new file mode 100644 index 0000000..29d5783 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/558-board_AR1004G.patch @@ -0,0 +1,49 @@ +From: "mexit@o2.pl" +Date: Sun, 24 Nov 2013 21:33:38 +0000 +Subject: [PATCH 4/5] brcm63xx: add support for Asmax AR 1004g router + +Support for Asmax AR 1004g router + +Signed-off-by: Adrian Feliks +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -687,6 +687,22 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct board_info __initdata board_96348gw_10_AR1004G = { ++ .name = "AR1004G", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ + + /* BT Voyager 2110 */ + static struct board_info __initdata board_V2110 = { +@@ -1799,6 +1815,7 @@ static const struct board_info __initcon + &board_96348A_122, + &board_CPVA502plus, + &board_96348W3, ++ &board_96348gw_10_AR1004G, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1863,6 +1880,7 @@ static struct of_device_id const bcm963x + { .compatible = "dynalink,rta770w", .data = &board_rta770w, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 ++ { .compatible = "asmax,ar1004g", .data = &board_96348gw_10_AR1004G, }, + { .compatible = "belkin,f5d7633", .data = &board_96348gw_10, }, + { .compatible = "brcm,bcm96348r", .data = &board_96348r, }, + { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, diff --git a/target/linux/brcm63xx/patches-3.18/559-board_vw6339gu.patch b/target/linux/brcm63xx/patches-3.18/559-board_vw6339gu.patch new file mode 100644 index 0000000..3a38540 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/559-board_vw6339gu.patch @@ -0,0 +1,72 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1761,6 +1761,53 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_vw6339gu = { ++ .name = "VW6339GU", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_ehci0 = 1, ++ .has_ohci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "LAN2", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "LAN3", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "LAN4", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "LAN1", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 7, ++ .name = "WAN", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_63268 */ + + /* +@@ -1847,6 +1894,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + &board_963269bhr, ++ &board_vw6339gu, + #endif + }; + +@@ -1937,6 +1985,7 @@ static struct of_device_id const bcm963x + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + { .compatible = "brcm,bcm963269bhr", .data = &board_963269bhr, }, ++ { .compatible = "inteno,vg50", .data = &board_vw6339gu, }, + #endif + #endif /* CONFIG_OF */ + { }, diff --git a/target/linux/brcm63xx/patches-3.18/560-board_963268gu_p300.patch b/target/linux/brcm63xx/patches-3.18/560-board_963268gu_p300.patch new file mode 100644 index 0000000..494328b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/560-board_963268gu_p300.patch @@ -0,0 +1,85 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1721,6 +1721,66 @@ static struct board_info __initdata boar + * known 63268/63269 boards + */ + #ifdef CONFIG_BCM63XX_CPU_63268 ++static struct board_info __initdata board_963268bu_p300 = { ++ .name = "963268BU_P300", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_ehci0 = 1, ++ .has_ohci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 17, ++ .name = "FE1", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "GbE2", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 0, ++ .name = "GbE3", ++ }, ++ ++ [5] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "GbE1", ++ }, ++ ++ [6] = { ++ .used = 1, ++ .phy_id = 24, ++ .name = "GbE4", ++ }, ++ ++ [7] = { ++ .used = 1, ++ .phy_id = 25, ++ .name = "GbE5", ++ }, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_963269bhr = { + .name = "963269BHR", + .expected_cpu_id = 0x63268, +@@ -1893,6 +1953,7 @@ static const struct board_info __initcon + &board_96368mvngr, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 ++ &board_963268bu_p300, + &board_963269bhr, + &board_vw6339gu, + #endif +@@ -1984,6 +2045,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 ++ { .compatible = "brcm,bcm963268bu_p300", .data = &board_963268bu_p300, }, + { .compatible = "brcm,bcm963269bhr", .data = &board_963269bhr, }, + { .compatible = "inteno,vg50", .data = &board_vw6339gu, }, + #endif diff --git a/target/linux/brcm63xx/patches-3.18/561-board_WAP-5813n.patch b/target/linux/brcm63xx/patches-3.18/561-board_WAP-5813n.patch new file mode 100644 index 0000000..b695b2b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/561-board_WAP-5813n.patch @@ -0,0 +1,94 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -14,7 +14,9 @@ + #include + #include + #include ++#include + #include ++#include + #include + #include + #include +@@ -1715,6 +1717,65 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_ehci0 = 1, + }; ++ ++static struct b53_platform_data WAP5813n_b53_pdata = { ++ .alias = "eth0", ++}; ++ ++static struct spi_board_info WAP5813n_spi_devices[] = { ++ { ++ .modalias = "b53-switch", ++ .max_speed_hz = 781000, ++ .bus_num = 0, ++ .chip_select = 0, ++ .platform_data = &WAP5813n_b53_pdata, ++ } ++}; ++ ++static struct sprom_fixup __initdata wap5813n_fixups[] = { ++ { .offset = 97, .value = 0xfeed }, ++ { .offset = 98, .value = 0x15d1 }, ++ { .offset = 99, .value = 0xfb0d }, ++ { .offset = 113, .value = 0xfef7 }, ++ { .offset = 114, .value = 0x15f7 }, ++ { .offset = 115, .value = 0xfb1a }, ++}; ++ ++static struct board_info __initdata board_WAP5813n = { ++ .name = "96369R-1231N", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [4] = { ++ .used = 1, ++ .phy_id = 0xff, ++ .bypass_link = 1, ++ .force_speed = 1000, ++ .force_duplex_full = 1, ++ .name = "RGMII", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43222, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = wap5813n_fixups, ++ .num_board_fixups = ARRAY_SIZE(wap5813n_fixups), ++ }, ++ ++ .spis = WAP5813n_spi_devices, ++ .num_spis = ARRAY_SIZE(WAP5813n_spi_devices), ++}; + #endif /* CONFIG_BCM63XX_CPU_6368 */ + + /* +@@ -1951,6 +2012,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, ++ &board_WAP5813n, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + &board_963268bu_p300, +@@ -2043,6 +2105,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6368 + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, ++ { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + { .compatible = "brcm,bcm963268bu_p300", .data = &board_963268bu_p300, }, diff --git a/target/linux/brcm63xx/patches-3.18/562-board_VR-3025u.patch b/target/linux/brcm63xx/patches-3.18/562-board_VR-3025u.patch new file mode 100644 index 0000000..13a2dc9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/562-board_VR-3025u.patch @@ -0,0 +1,79 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1718,6 +1718,60 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct sprom_fixup __initdata vr3025u_fixups[] = { ++ { .offset = 97, .value = 0xfeb3 }, ++ { .offset = 98, .value = 0x1618 }, ++ { .offset = 99, .value = 0xfab0 }, ++ { .offset = 113, .value = 0xfed1 }, ++ { .offset = 114, .value = 0x1609 }, ++ { .offset = 115, .value = 0xfad9 }, ++}; ++ ++static struct board_info __initdata board_VR3025u = { ++ .name = "96368M-1541N", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43222, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = vr3025u_fixups, ++ .num_board_fixups = ARRAY_SIZE(vr3025u_fixups), ++ }, ++}; ++ + static struct b53_platform_data WAP5813n_b53_pdata = { + .alias = "eth0", + }; +@@ -2012,6 +2066,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, ++ &board_VR3025u, + &board_WAP5813n, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 +@@ -2105,6 +2160,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6368 + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, ++ { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 diff --git a/target/linux/brcm63xx/patches-3.18/563-board_VR-3025un.patch b/target/linux/brcm63xx/patches-3.18/563-board_VR-3025un.patch new file mode 100644 index 0000000..f194a88 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/563-board_VR-3025un.patch @@ -0,0 +1,79 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1772,6 +1772,60 @@ static struct board_info __initdata boar + }, + }; + ++static struct sprom_fixup __initdata vr3025un_fixups[] = { ++ { .offset = 97, .value = 0xfeb3 }, ++ { .offset = 98, .value = 0x1618 }, ++ { .offset = 99, .value = 0xfab0 }, ++ { .offset = 113, .value = 0xfed1 }, ++ { .offset = 114, .value = 0x1609 }, ++ { .offset = 115, .value = 0xfad9 }, ++}; ++ ++static struct board_info __initdata board_VR3025un = { ++ .name = "96368M-1341N", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43222, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = vr3025un_fixups, ++ .num_board_fixups = ARRAY_SIZE(vr3025un_fixups), ++ }, ++}; ++ + static struct b53_platform_data WAP5813n_b53_pdata = { + .alias = "eth0", + }; +@@ -2067,6 +2121,7 @@ static const struct board_info __initcon + &board_96368mvwg, + &board_96368mvngr, + &board_VR3025u, ++ &board_VR3025un, + &board_WAP5813n, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 +@@ -2161,6 +2216,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, ++ { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 diff --git a/target/linux/brcm63xx/patches-3.18/564-board_P870HW-51a_v2.patch b/target/linux/brcm63xx/patches-3.18/564-board_P870HW-51a_v2.patch new file mode 100644 index 0000000..8ccba3a --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/564-board_P870HW-51a_v2.patch @@ -0,0 +1,68 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1727,6 +1727,49 @@ static struct sprom_fixup __initdata vr3 + { .offset = 115, .value = 0xfad9 }, + }; + ++static struct board_info __initdata board_P870HW51A_V2 = { ++ .name = "P870HW-51a_v2", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_VR3025u = { + .name = "96368M-1541N", + .expected_cpu_id = 0x6368, +@@ -2120,6 +2163,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, ++ &board_P870HW51A_V2, + &board_VR3025u, + &board_VR3025un, + &board_WAP5813n, +@@ -2218,6 +2262,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, ++ { .compatible = "zyxel,p870hw-51a-v2", .data = &board_P870HW51A_V2, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + { .compatible = "brcm,bcm963268bu_p300", .data = &board_963268bu_p300, }, diff --git a/target/linux/brcm63xx/patches-3.18/565-board_hw520.patch b/target/linux/brcm63xx/patches-3.18/565-board_hw520.patch new file mode 100644 index 0000000..8f40612 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/565-board_hw520.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1365,6 +1365,37 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_HW520 = { ++ .name = "HW6358GW_B", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enet0 = 1, ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_HW553 = { + .name = "HW553", + .expected_cpu_id = 0x6358, +@@ -2147,6 +2178,7 @@ static const struct board_info __initcon + &board_nb4_ser_r0, + &board_nb4_fxc_r1, + &board_ct6373_1, ++ &board_HW520, + &board_HW553, + &board_HW556_A, + &board_HW556_B, +@@ -2239,6 +2271,7 @@ static struct of_device_id const bcm963x + { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, + { .compatible = "d-link,dva-g3810bn/tl", .data = &board_DVAG3810BN, }, ++ { .compatible = "huawei,hg520v", .data = &board_HW520, }, + { .compatible = "huawei,hg553", .data = &board_HW553, }, + { .compatible = "huawei,hg556a-a", .data = &board_HW556_A, }, + { .compatible = "huawei,hg556a-b", .data = &board_HW556_B, }, diff --git a/target/linux/brcm63xx/patches-3.18/566-board_A4001N.patch b/target/linux/brcm63xx/patches-3.18/566-board_A4001N.patch new file mode 100644 index 0000000..f8a95e5 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/566-board_A4001N.patch @@ -0,0 +1,69 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -367,6 +367,50 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_A4001N = { ++ .name = "96328dg2x2", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43225, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ }, ++}; ++ + static struct board_info __initdata board_A4001N1 = { + .name = "963281T_TEF", + .expected_cpu_id = 0x6328, +@@ -2129,6 +2173,7 @@ static const struct board_info __initcon + &board_AR5381u, + &board_AR5387un, + &board_963281TAN, ++ &board_A4001N, + &board_A4001N1, + &board_dsl_274xb_f1, + &board_FAST2704V2, +@@ -2217,6 +2262,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96318ref_p300", .data = &board_96318ref_p300, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 ++ { .compatible = "adb,a4001n", .data = &board_A4001N, }, + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, diff --git a/target/linux/brcm63xx/patches-3.18/567-board_dsl-2751b_e1.patch b/target/linux/brcm63xx/patches-3.18/567-board_dsl-2751b_e1.patch new file mode 100644 index 0000000..af22c2b --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/567-board_dsl-2751b_e1.patch @@ -0,0 +1,94 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -156,6 +156,75 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct sprom_fixup __initdata dsl2751b_e1_fixups[] = { ++ { .offset = 96, .value = 0x2046 }, ++ { .offset = 97, .value = 0xfe9d }, ++ { .offset = 98, .value = 0x1854 }, ++ { .offset = 99, .value = 0xfa59 }, ++ { .offset = 112, .value = 0x2046 }, ++ { .offset = 113, .value = 0xfe79 }, ++ { .offset = 114, .value = 0x17f5 }, ++ { .offset = 115, .value = 0xfa47 }, ++ { .offset = 161, .value = 0x2222 }, ++ { .offset = 162, .value = 0x2222 }, ++ { .offset = 169, .value = 0x2222 }, ++ { .offset = 170, .value = 0x2222 }, ++ { .offset = 171, .value = 0x5555 }, ++ { .offset = 172, .value = 0x5555 }, ++ { .offset = 173, .value = 0x4444 }, ++ { .offset = 174, .value = 0x4444 }, ++ { .offset = 175, .value = 0x5555 }, ++ { .offset = 176, .value = 0x5555 }, ++}; ++ ++static struct board_info __initdata board_dsl_2751b_d1 = { ++ .name = "AW5200B", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .has_enetsw = 1, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43217, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ .board_fixups = dsl2751b_e1_fixups, ++ .num_board_fixups = ARRAY_SIZE(dsl2751b_e1_fixups), ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6318 */ + + /* +@@ -2167,6 +2236,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6318 + &board_96318ref, + &board_96318ref_p300, ++ &board_dsl_2751b_d1, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, +@@ -2260,6 +2330,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6318 + { .compatible = "brcm,bcm96318ref", .data = &board_96318ref, }, + { .compatible = "brcm,bcm96318ref_p300", .data = &board_96318ref_p300, }, ++ { .compatible = "d-link,dsl-275xb-d", .data = &board_dsl_2751b_d1, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "adb,a4001n", .data = &board_A4001N, }, diff --git a/target/linux/brcm63xx/patches-3.18/568-board_DGND3700v1_3800B.patch b/target/linux/brcm63xx/patches-3.18/568-board_DGND3700v1_3800B.patch new file mode 100644 index 0000000..97e65d3 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/568-board_DGND3700v1_3800B.patch @@ -0,0 +1,67 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1862,6 +1862,48 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct b53_platform_data DGND3700v1_3800B_b53_pdata = { ++ .alias = "eth0", ++}; ++ ++static struct spi_board_info DGND3700v1_3800B_spi_devices[] = { ++ { ++ .modalias = "b53-switch", ++ .max_speed_hz = 781000, ++ .bus_num = 0, ++ .chip_select = 1, ++ .platform_data = &DGND3700v1_3800B_b53_pdata, ++ } ++}; ++ ++static struct board_info __initdata board_DGND3700v1_3800B = { ++ .name = "DGND3700v1_3800B", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [5] = { ++ .used = 1, ++ .phy_id = 0xff, ++ .bypass_link = 1, ++ .force_speed = 1000, ++ .force_duplex_full = 1, ++ .name = "RGMII", ++ }, ++ }, ++ }, ++ ++ .spis = DGND3700v1_3800B_spi_devices, ++ .num_spis = ARRAY_SIZE(DGND3700v1_3800B_spi_devices), ++}; ++ + static struct sprom_fixup __initdata vr3025u_fixups[] = { + { .offset = 97, .value = 0xfeb3 }, + { .offset = 98, .value = 0x1618 }, +@@ -2310,6 +2352,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, ++ &board_DGND3700v1_3800B, + &board_P870HW51A_V2, + &board_VR3025u, + &board_VR3025un, +@@ -2412,6 +2455,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, ++ { .compatible = "netgear,dgnd3700v1", .data = &board_DGND3700v1_3800B, }, + { .compatible = "zyxel,p870hw-51a-v2", .data = &board_P870HW51A_V2, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 diff --git a/target/linux/brcm63xx/patches-3.18/569-board_homehub2a.patch b/target/linux/brcm63xx/patches-3.18/569-board_homehub2a.patch new file mode 100644 index 0000000..e7678a9 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/569-board_homehub2a.patch @@ -0,0 +1,51 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1478,6 +1478,32 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_homehub2a = { ++ .name = "HOMEHUB2A", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4322, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_HW520 = { + .name = "HW6358GW_B", + .expected_cpu_id = 0x6358, +@@ -2335,6 +2361,7 @@ static const struct board_info __initcon + &board_nb4_ser_r0, + &board_nb4_fxc_r1, + &board_ct6373_1, ++ &board_homehub2a, + &board_HW520, + &board_HW553, + &board_HW556_A, +@@ -2444,6 +2471,7 @@ static struct of_device_id const bcm963x + { .compatible = "sfr,nb4-fxc-r1", .data = &board_nb4_fxc_r1, }, + { .compatible = "t-com,spw303v", .data = &board_spw303v, }, + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, ++ { .compatible = "thomson,homehub2a", .data = &board_homehub2a, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6362 + { .compatible = "sagem,f@st2504n", .data = &board_fast2504n, }, diff --git a/target/linux/brcm63xx/patches-3.18/570-board_HG655b.patch b/target/linux/brcm63xx/patches-3.18/570-board_HG655b.patch new file mode 100644 index 0000000..7c667bf --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/570-board_HG655b.patch @@ -0,0 +1,72 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1930,6 +1930,53 @@ static struct board_info __initdata boar + .num_spis = ARRAY_SIZE(DGND3700v1_3800B_spi_devices), + }; + ++static struct board_info __initdata board_HG655b = { ++ .name = "HW65x", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_RALINK, ++ .caldata_offset = 0x7c0000, ++ .slot = 1, ++ .eeprom = "rt2x00.eeprom", ++ }, ++ }, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++}; ++ + static struct sprom_fixup __initdata vr3025u_fixups[] = { + { .offset = 97, .value = 0xfeb3 }, + { .offset = 98, .value = 0x1618 }, +@@ -2380,6 +2427,7 @@ static const struct board_info __initcon + &board_96368mvwg, + &board_96368mvngr, + &board_DGND3700v1_3800B, ++ &board_HG655b, + &board_P870HW51A_V2, + &board_VR3025u, + &board_VR3025un, +@@ -2483,6 +2531,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, ++ { .compatible = "huawei,hg655b", .data = &board_HG655b, }, + { .compatible = "netgear,dgnd3700v1", .data = &board_DGND3700v1_3800B, }, + { .compatible = "zyxel,p870hw-51a-v2", .data = &board_P870HW51A_V2, }, + #endif diff --git a/target/linux/brcm63xx/patches-3.18/571-board_fast2704n.patch b/target/linux/brcm63xx/patches-3.18/571-board_fast2704n.patch new file mode 100644 index 0000000..f4e0fbf --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/571-board_fast2704n.patch @@ -0,0 +1,65 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -225,6 +225,46 @@ static struct board_info __initdata boar + .num_board_fixups = ARRAY_SIZE(dsl2751b_e1_fixups), + }, + }; ++ ++static struct board_info __initdata board_FAST2704N = { ++ .name = "F@ST2704N", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .has_enetsw = 1, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6318 */ + + /* +@@ -2352,6 +2392,7 @@ static const struct board_info __initcon + &board_96318ref, + &board_96318ref_p300, + &board_dsl_2751b_d1, ++ &board_FAST2704N, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, +@@ -2449,6 +2490,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96318ref", .data = &board_96318ref, }, + { .compatible = "brcm,bcm96318ref_p300", .data = &board_96318ref_p300, }, + { .compatible = "d-link,dsl-275xb-d", .data = &board_dsl_2751b_d1, }, ++ { .compatible = "sagem,f@st2704n", .data = &board_FAST2704N, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "adb,a4001n", .data = &board_A4001N, }, diff --git a/target/linux/brcm63xx/patches-3.18/572-board_VR-3026e.patch b/target/linux/brcm63xx/patches-3.18/572-board_VR-3026e.patch new file mode 100644 index 0000000..4358afd --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/572-board_VR-3026e.patch @@ -0,0 +1,79 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2168,6 +2168,60 @@ static struct board_info __initdata boar + }, + }; + ++static struct sprom_fixup __initdata vr3026e_fixups[] = { ++ { .offset = 97, .value = 0xfeb3 }, ++ { .offset = 98, .value = 0x1618 }, ++ { .offset = 99, .value = 0xfab0 }, ++ { .offset = 113, .value = 0xfed1 }, ++ { .offset = 114, .value = 0x1609 }, ++ { .offset = 115, .value = 0xfad9 }, ++}; ++ ++static struct board_info __initdata board_VR3026e = { ++ .name = "96368MT-1341N1", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43222, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = vr3026e_fixups, ++ .num_board_fixups = ARRAY_SIZE(vr3026e_fixups), ++ }, ++}; ++ + static struct b53_platform_data WAP5813n_b53_pdata = { + .alias = "eth0", + }; +@@ -2472,6 +2526,7 @@ static const struct board_info __initcon + &board_P870HW51A_V2, + &board_VR3025u, + &board_VR3025un, ++ &board_VR3026e, + &board_WAP5813n, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 +@@ -2572,6 +2627,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, ++ { .compatible = "comtrend,vr-3026e", .data = &board_VR3026e, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, + { .compatible = "huawei,hg655b", .data = &board_HG655b, }, + { .compatible = "netgear,dgnd3700v1", .data = &board_DGND3700v1_3800B, }, diff --git a/target/linux/brcm63xx/patches-3.18/800-wl_exports.patch b/target/linux/brcm63xx/patches-3.18/800-wl_exports.patch new file mode 100644 index 0000000..68d37c7 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/800-wl_exports.patch @@ -0,0 +1,25 @@ +--- a/arch/mips/bcm63xx/nvram.c ++++ b/arch/mips/bcm63xx/nvram.c +@@ -40,6 +40,12 @@ struct bcm963xx_nvram { + static struct bcm963xx_nvram nvram; + static int mac_addr_used; + ++/* ++ * Required export for WL ++ */ ++u32 nvram_buf[5] = { 0, cpu_to_le32(20), 0, 0, 0 }; ++EXPORT_SYMBOL(nvram_buf); ++ + void __init bcm63xx_nvram_init(void *addr) + { + unsigned int check_len; +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -59,6 +59,7 @@ void (*_dma_cache_wback)(unsigned long s + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + + EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_inv); + + #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ + diff --git a/target/linux/brcm63xx/patches-3.18/801-ssb_export_fallback_sprom.patch b/target/linux/brcm63xx/patches-3.18/801-ssb_export_fallback_sprom.patch new file mode 100644 index 0000000..11a8353 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/801-ssb_export_fallback_sprom.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -8,6 +8,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -387,7 +388,19 @@ struct fallback_sprom_match { + struct ssb_sprom sprom; + }; + +-static struct fallback_sprom_match fallback_sprom; ++struct fallback_sprom_match fallback_sprom; ++ ++int bcm63xx_get_fallback_sprom(uint pci_bus, uint pci_slot, struct ssb_sprom *out) ++{ ++ if (pci_bus != fallback_sprom.pci_bus || ++ pci_slot != fallback_sprom.pci_dev) ++ pr_warn("fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\n", ++ fallback_sprom.pci_bus, fallback_sprom.pci_dev, ++ pci_bus, pci_slot); ++ memcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom)); ++ return 0; ++} ++EXPORT_SYMBOL(bcm63xx_get_fallback_sprom); + + #if defined(CONFIG_SSB_PCIHOST) + int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out) diff --git a/target/linux/brcm63xx/patches-3.18/802-rtl8367r_fix_RGMII_support.patch b/target/linux/brcm63xx/patches-3.18/802-rtl8367r_fix_RGMII_support.patch new file mode 100644 index 0000000..9037d89 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/802-rtl8367r_fix_RGMII_support.patch @@ -0,0 +1,30 @@ +From e3208e6087642b95a5bab3101fc9c6e34892c861 Mon Sep 17 00:00:00 2001 +From: Miguel GAIO +Date: Fri, 6 Jul 2012 14:12:33 +0200 +Subject: [PATCH 6/8] * [rtl8367r] Fix RGMII support + +--- + drivers/net/phy/rtl8367.c | 5 +++++ + 1 files changed, 5 insertions(+), 0 deletions(-) + +--- a/drivers/net/phy/rtl8367.c ++++ b/drivers/net/phy/rtl8367.c +@@ -146,6 +146,10 @@ + #define RTL8367_EXT_RGMXF_TXDELAY_MASK 1 + #define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7 + ++#define RTL8367_PHY_AD_REG 0x130f ++#define RTL8370_PHY_AD_DUMMY_1_OFFSET 5 ++#define RTL8370_PHY_AD_DUMMY_1_MASK 0xe0 ++ + #define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x)) + #define RTL8367_DI_FORCE_MODE BIT(12) + #define RTL8367_DI_FORCE_NWAY BIT(7) +@@ -894,6 +898,7 @@ static int rtl8367_extif_set_mode(struct + case RTL8367_EXTIF_MODE_RGMII_33V: + REG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367); + REG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777); ++ REG_RMW(smi, RTL8367_PHY_AD_REG, BIT(5), 0); + break; + + case RTL8367_EXTIF_MODE_TMII_MAC: diff --git a/target/linux/brcm63xx/patches-3.18/803-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch b/target/linux/brcm63xx/patches-3.18/803-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch new file mode 100644 index 0000000..8b603e8 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/803-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch @@ -0,0 +1,26 @@ +From ff3409ab17d56450943364ba49a16960e3cdda9b Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 6 Apr 2014 22:33:16 +0200 +Subject: [RFC] jffs2: work around unaligned accesses failing on bcm63xx/smp + +Unligned memcpy_fromio randomly fails with an unaligned dst. Work around +it by ensuring we are always doing aligned copies. + +Should fix filename corruption in jffs2 with SMP. + +Signed-off-by: Jonas Gorski +--- + fs/jffs2/nodelist.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/fs/jffs2/nodelist.h ++++ b/fs/jffs2/nodelist.h +@@ -255,7 +255,7 @@ struct jffs2_full_dirent + uint32_t ino; /* == zero for unlink */ + unsigned int nhash; + unsigned char type; +- unsigned char name[0]; ++ unsigned char name[0] __attribute__((aligned((sizeof(long))))); + }; + + /* diff --git a/target/linux/brcm63xx/patches-3.18/804-bcm63xx_enet_63268_rgmii_ports.patch b/target/linux/brcm63xx/patches-3.18/804-bcm63xx_enet_63268_rgmii_ports.patch new file mode 100644 index 0000000..770f39e --- /dev/null +++ b/target/linux/brcm63xx/patches-3.18/804-bcm63xx_enet_63268_rgmii_ports.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2272,6 +2272,10 @@ static int bcm_enetsw_open(struct net_de + + rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i)); + rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN; ++ if (BCMCPU_IS_63268()) { ++ rgmii_ctrl |= ENETSW_RGMII_CTRL_TIMING_SEL_EN; ++ rgmii_ctrl |= ENETSW_RGMII_CTRL_MII_OVERRIDE_EN; ++ } + enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); + } + diff --git a/target/linux/brcm63xx/patches-4.1/001-4.2-MIPS-Add-support-for-vmlinux.bin-appended-dtb.patch b/target/linux/brcm63xx/patches-4.1/001-4.2-MIPS-Add-support-for-vmlinux.bin-appended-dtb.patch new file mode 100644 index 0000000..fa7732b --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/001-4.2-MIPS-Add-support-for-vmlinux.bin-appended-dtb.patch @@ -0,0 +1,112 @@ +From 1da8f1798e307fb8422753984339beb00025f97d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 12 Apr 2015 12:24:58 +0200 +Subject: [PATCH] MIPS: Add support for vmlinux.bin appended dtb + +Add support for detecting a vmlinux.bin appended dtb and overriding +the boot arguments to match the UHI interface. + +Due to the PERCPU section being empty for !SMP, but still modifying +the current address by aligning it to the page size, do not define +it for !SMP builds to allow __appended_dtb to still point to +the actual end of the data. + +Signed-off-by: Jonas Gorski +Cc: linux-mips@linux-mips.org +Cc: devicetree@vger.kernel.org +Cc: John Crispin +Cc: Kevin Cernekee +Cc: Florian Fainelli +Cc: Aaro Koskinen +Cc: Markos Chandras +Cc: Andrew Bresticker +Cc: Daniel Schwierzeck +Cc: Paul Burton +Cc: James Hartley +Patchwork: https://patchwork.linux-mips.org/patch/9739/ +Signed-off-by: Ralf Baechle +--- + arch/mips/Kconfig | 27 +++++++++++++++++++++++++++ + arch/mips/kernel/head.S | 16 ++++++++++++++++ + arch/mips/kernel/vmlinux.lds.S | 8 +++++++- + 3 files changed, 50 insertions(+), 1 deletion(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2703,6 +2703,33 @@ config BOOT_RAW + + + ++choice ++ prompt "Kernel appended dtb support" if OF ++ default MIPS_NO_APPENDED_DTB ++ ++ config MIPS_NO_APPENDED_DTB ++ bool "None" ++ help ++ Do not enable appended dtb support. ++ ++ config MIPS_RAW_APPENDED_DTB ++ bool "vmlinux.bin" ++ help ++ With this option, the boot code will look for a device tree binary ++ DTB) appended to raw vmlinux.bin (without decompressor). ++ (e.g. cat vmlinux.bin .dtb > vmlinux_w_dtb). ++ ++ This is meant as a backward compatibility convenience for those ++ systems with a bootloader that can't be upgraded to accommodate ++ the documented boot protocol using a device tree. ++ ++ Beware that there is very little in terms of protection against ++ this option being confused by leftover garbage in memory that might ++ look like a DTB header after a reboot if no actual DTB is appended ++ to vmlinux.bin. Do not leave this option active in a production kernel ++ if you don't intend to always append a DTB. ++endchoice ++ + endmenu + + config LOCKDEP_SUPPORT +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -100,6 +100,22 @@ NESTED(kernel_entry, 16, sp) # kernel + jr t0 + 0: + ++#ifdef CONFIG_MIPS_RAW_APPENDED_DTB ++ PTR_LA t0, __appended_dtb ++ ++#ifdef CONFIG_CPU_BIG_ENDIAN ++ li t1, 0xd00dfeed ++#else ++ li t1, 0xedfe0dd0 ++#endif ++ lw t2, (t0) ++ bne t1, t2, not_found ++ nop ++ ++ move a1, t0 ++ PTR_LI a0, -2 ++not_found: ++#endif + PTR_LA t0, __bss_start # clear .bss + LONG_S zero, (t0) + PTR_LA t1, __bss_stop - LONGSIZE +--- a/arch/mips/kernel/vmlinux.lds.S ++++ b/arch/mips/kernel/vmlinux.lds.S +@@ -125,8 +125,14 @@ SECTIONS + .exit.data : { + EXIT_DATA + } +- ++#ifdef CONFIG_SMP + PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT) ++#endif ++#ifdef CONFIG_MIPS_RAW_APPENDED_DTB ++ __appended_dtb = .; ++ /* leave space for appended DTB */ ++ . += 0x100000; ++#endif + /* + * Align to 64K in attempt to eliminate holes before the + * .bss..swapper_pg_dir section at the start of .bss. This diff --git a/target/linux/brcm63xx/patches-4.1/002-4.2-irqchip-Move-IRQCHIP_DECLARE-macro-to-include-linux-.patch b/target/linux/brcm63xx/patches-4.1/002-4.2-irqchip-Move-IRQCHIP_DECLARE-macro-to-include-linux-.patch new file mode 100644 index 0000000..83c07e6 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/002-4.2-irqchip-Move-IRQCHIP_DECLARE-macro-to-include-linux-.patch @@ -0,0 +1,79 @@ +From 91e20b5040c67c51aad88cf87db4305c5bd7f79d Mon Sep 17 00:00:00 2001 +From: Joel Porquet +Date: Thu, 2 Jul 2015 15:32:00 -0400 +Subject: [PATCH] irqchip: Move IRQCHIP_DECLARE macro to + include/linux/irqchip.h + +At the moment the IRQCHIP_DECLARE macro is only declared locally in +drivers/irqchip/irqchip.h. It prevents from using it directly in arch/* +directories whenever irqchip drivers only exist there, which happens in a few +cases (e.g. arc, arm, microblaze and mips). + +This patch makes the macro to be globally defined, i.e. in +include/linux/irqchip.h, and thus usable for arch-specific declarations of +irqchip drivers. In this way, it is very similar to what clocksource does (ie +CLOCKSOURCE_OF_DECLARE is defined in include/linux/clocksource.h). + +For now, this patch only moves the declaration of the macro +IRQCHIP_DECLARE to the global header 'include/linux/irqchip.h' and make +'drivers/irqchip/irqchip.h' include 'include/linux/irqchip.h'. Later, other +patches will get rid of 'drivers/irqchip/irqchip.h' and modify all the impacted +irqchip drivers. + +Signed-off-by: Joel Porquet +Cc: Jason Cooper +Link: http://lkml.kernel.org/r/1435865565-14114-1-git-send-email-joel@porquet.org +Signed-off-by: Thomas Gleixner +--- + drivers/irqchip/irqchip.h | 19 +------------------ + include/linux/irqchip.h | 14 ++++++++++++++ + 2 files changed, 15 insertions(+), 18 deletions(-) + +--- a/drivers/irqchip/irqchip.h ++++ b/drivers/irqchip/irqchip.h +@@ -8,21 +8,4 @@ + * warranty of any kind, whether express or implied. + */ + +-#ifndef _IRQCHIP_H +-#define _IRQCHIP_H +- +-#include +- +-/* +- * This macro must be used by the different irqchip drivers to declare +- * the association between their DT compatible string and their +- * initialization function. +- * +- * @name: name that must be unique accross all IRQCHIP_DECLARE of the +- * same file. +- * @compstr: compatible string of the irqchip driver +- * @fn: initialization function +- */ +-#define IRQCHIP_DECLARE(name, compat, fn) OF_DECLARE_2(irqchip, name, compat, fn) +- +-#endif ++#include +--- a/include/linux/irqchip.h ++++ b/include/linux/irqchip.h +@@ -11,6 +11,20 @@ + #ifndef _LINUX_IRQCHIP_H + #define _LINUX_IRQCHIP_H + ++#include ++ ++/* ++ * This macro must be used by the different irqchip drivers to declare ++ * the association between their DT compatible string and their ++ * initialization function. ++ * ++ * @name: name that must be unique accross all IRQCHIP_DECLARE of the ++ * same file. ++ * @compstr: compatible string of the irqchip driver ++ * @fn: initialization function ++ */ ++#define IRQCHIP_DECLARE(name, compat, fn) OF_DECLARE_2(irqchip, name, compat, fn) ++ + #ifdef CONFIG_IRQCHIP + void irqchip_init(void); + #else diff --git a/target/linux/brcm63xx/patches-4.1/010-4.3-01-spi-bcm63xx-hsspi-add-support-for-dual-spi-read-writ.patch b/target/linux/brcm63xx/patches-4.1/010-4.3-01-spi-bcm63xx-hsspi-add-support-for-dual-spi-read-writ.patch new file mode 100644 index 0000000..1be40eb --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/010-4.3-01-spi-bcm63xx-hsspi-add-support-for-dual-spi-read-writ.patch @@ -0,0 +1,68 @@ +From 61dc388f577b6f984797949f32c30021d9ea73dc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 23 Aug 2015 12:16:02 +0200 +Subject: [PATCH V2] spi/bcm63xx-hsspi: add support for dual spi read/write + +Add support for dual read/writes on spi-bcm63xx-hsspi. This has been +tested with a s25fl129p1 dual read capable spi flash, with a nice speed +improvement: + +serial read: + +root@OpenWrt:/# time dd if=/dev/mtd4 of=/dev/null bs=8192 +2032+0 records in +2032+0 records out +real 0m 4.39s +user 0m 0.00s +sys 0m 1.55s + +dual read: + +root@OpenWrt:/# time dd if=/dev/mtd4 of=/dev/null bs=8192 +2032+0 records in +2032+0 records out +real 0m 3.09s +user 0m 0.00s +sys 0m 1.56s + +Signed-off-by: Jonas Gorski +--- + drivers/spi/spi-bcm63xx-hsspi.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +--- a/drivers/spi/spi-bcm63xx-hsspi.c ++++ b/drivers/spi/spi-bcm63xx-hsspi.c +@@ -76,6 +76,7 @@ + #define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200) + + ++#define HSSPI_OP_MULTIBIT BIT(11) + #define HSSPI_OP_CODE_SHIFT 13 + #define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT) + #define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT) +@@ -171,9 +172,12 @@ static int bcm63xx_hsspi_do_txrx(struct + if (opcode != HSSPI_OP_READ) + step_size -= HSSPI_OPCODE_LEN; + +- __raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT | +- 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT | +- 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff, ++ if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || ++ (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) ++ opcode |= HSSPI_OP_MULTIBIT; ++ ++ __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT | ++ 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff, + bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); + + while (pending > 0) { +@@ -374,7 +378,8 @@ static int bcm63xx_hsspi_probe(struct pl + master->num_chipselect = 8; + master->setup = bcm63xx_hsspi_setup; + master->transfer_one_message = bcm63xx_hsspi_transfer_one; +- master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; ++ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | ++ SPI_RX_DUAL | SPI_TX_DUAL; + master->bits_per_word_mask = SPI_BPW_MASK(8); + master->auto_runtime_pm = true; + diff --git a/target/linux/brcm63xx/patches-4.1/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch b/target/linux/brcm63xx/patches-4.1/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch new file mode 100644 index 0000000..63d385b --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch @@ -0,0 +1,28 @@ +From 80a2f983e9f44dbc3e01ae31c62d877846a7f791 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:19 +0100 +Subject: [PATCH 01/11] MIPS: BCM63XX: add USB host clock enable delay + +Knowledge of the clock setup delay should remain at the clock level (so +it can be clock specific and CPU specific). Add the 100 milliseconds +required clock delay for the USB host clock when it gets enabled. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/clk.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -177,6 +177,11 @@ static void usbh_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); ++ else ++ return; ++ ++ if (enable) ++ msleep(100); + } + + static struct clk clk_usbh = { diff --git a/target/linux/brcm63xx/patches-4.1/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch b/target/linux/brcm63xx/patches-4.1/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch new file mode 100644 index 0000000..5b2c03f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch @@ -0,0 +1,41 @@ +From 8e9bf528a122741f0171b89c297b63041116d704 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:20 +0100 +Subject: [PATCH 02/11] MIPS: BCM63XX: add USB device clock enable delay to + clock code + +This patch adds the required 10 micro seconds delay to the USB device +clock enable operation. Put this where the correct clock knowledege is, +which is in the clock code, and remove this delay from the bcm63xx_udc +gadget driver where it was before. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/clk.c | 5 +++++ + drivers/usb/gadget/bcm63xx_udc.c | 1 - + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -199,6 +199,11 @@ static void usbd_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); ++ else ++ return; ++ ++ if (enable) ++ udelay(10); + } + + static struct clk clk_usbd = { +--- a/drivers/usb/gadget/udc/bcm63xx_udc.c ++++ b/drivers/usb/gadget/udc/bcm63xx_udc.c +@@ -391,7 +391,6 @@ static inline void set_clocks(struct bcm + if (is_enabled) { + clk_enable(udc->usbh_clk); + clk_enable(udc->usbd_clk); +- udelay(10); + } else { + clk_disable(udc->usbd_clk); + clk_disable(udc->usbh_clk); diff --git a/target/linux/brcm63xx/patches-4.1/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch b/target/linux/brcm63xx/patches-4.1/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch new file mode 100644 index 0000000..5d106f8 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch @@ -0,0 +1,151 @@ +From ac9b0b574d54be28b300bf99ffe092a2c589484f Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:21 +0100 +Subject: [PATCH 03/11] MIPS: BCM63XX: move code touching the USB private + register + +This patch moves the code touching the USB private register in the +bcm63xx USB gadget driver to arch/mips/bcm63xx/usb-common.c in +preparation for adding support for OHCI and EHCI host controllers which +will also touch the USB private register. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/usb-common.c | 53 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h | 9 ++++ + drivers/usb/gadget/bcm63xx_udc.c | 27 ++-------- + 4 files changed, 67 insertions(+), 24 deletions(-) + create mode 100644 arch/mips/bcm63xx/usb-common.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,7 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-usbd.o ++ dev-wdt.o dev-usb-usbd.o usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -0,0 +1,53 @@ ++/* ++ * Broadcom BCM63xx common USB device configuration code ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2012 Kevin Cernekee ++ * Copyright (C) 2012 Broadcom Corporation ++ * ++ */ ++#include ++ ++#include ++#include ++#include ++#include ++ ++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device) ++{ ++ u32 val; ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); ++ if (is_device) { ++ val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); ++ val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ } else { ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ } ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ if (is_device) ++ val |= USBH_PRIV_SWAP_USBD_MASK; ++ else ++ val &= ~USBH_PRIV_SWAP_USBD_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++} ++EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode); ++ ++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on) ++{ ++ u32 val; ++ ++ val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); ++ if (is_on) ++ val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ else ++ val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); ++ bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++} ++EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup); +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h +@@ -0,0 +1,9 @@ ++#ifndef BCM63XX_USB_PRIV_H_ ++#define BCM63XX_USB_PRIV_H_ ++ ++#include ++ ++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device); ++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on); ++ ++#endif /* BCM63XX_USB_PRIV_H_ */ +--- a/drivers/usb/gadget/udc/bcm63xx_udc.c ++++ b/drivers/usb/gadget/udc/bcm63xx_udc.c +@@ -40,6 +40,7 @@ + #include + #include + #include ++#include + + #define DRV_MODULE_NAME "bcm63xx_udc" + +@@ -868,22 +869,7 @@ static void bcm63xx_select_phy_mode(stru + bcm_gpio_writel(val, GPIO_PINMUX_OTHR_REG); + } + +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); +- if (is_device) { +- val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); +- val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- } else { +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT); +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- } +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); +- +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); +- if (is_device) +- val |= USBH_PRIV_SWAP_USBD_MASK; +- else +- val &= ~USBH_PRIV_SWAP_USBD_MASK; +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++ bcm63xx_usb_priv_select_phy_mode(portmask, is_device); + } + + /** +@@ -897,14 +883,9 @@ static void bcm63xx_select_phy_mode(stru + */ + static void bcm63xx_select_pullup(struct bcm63xx_udc *udc, bool is_on) + { +- u32 val, portmask = BIT(udc->pd->port_no); ++ u32 portmask = BIT(udc->pd->port_no); + +- val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); +- if (is_on) +- val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- else +- val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); +- bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ bcm63xx_usb_priv_select_pullup(portmask, is_on); + } + + /** diff --git a/target/linux/brcm63xx/patches-4.1/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch b/target/linux/brcm63xx/patches-4.1/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch new file mode 100644 index 0000000..40bbe08 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch @@ -0,0 +1,169 @@ +From 28758a9da77954ed323f86123ef448c6a563c037 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:22 +0100 +Subject: [PATCH 04/11] MIPS: BCM63XX: add OHCI/EHCI configuration bits to + common USB code + +This patch updates the common USB code touching the USB private +registers with the specific bits to properly enable OHCI and EHCI +controllers on BCM63xx SoCs. As a result we now need to protect access +to Read Modify Write sequences using a spinlock because we cannot +guarantee that any of the exposed helper will not be called +concurrently. + +Signed-off-by: Maxime Bizon +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/usb-common.c | 97 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h | 2 + + 2 files changed, 99 insertions(+) + +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -5,10 +5,12 @@ + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * ++ * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2012 Kevin Cernekee + * Copyright (C) 2012 Broadcom Corporation + * + */ ++#include + #include + + #include +@@ -16,9 +18,14 @@ + #include + #include + ++static DEFINE_SPINLOCK(usb_priv_reg_lock); ++ + void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device) + { + u32 val; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); + + val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); + if (is_device) { +@@ -36,12 +43,17 @@ void bcm63xx_usb_priv_select_phy_mode(u3 + else + val &= ~USBH_PRIV_SWAP_USBD_MASK; + bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG); ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); + } + EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode); + + void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on) + { + u32 val; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); + + val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG); + if (is_on) +@@ -49,5 +61,90 @@ void bcm63xx_usb_priv_select_pullup(u32 + else + val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT); + bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG); ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); + } + EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup); ++ ++/* The following array represents the meaning of the DESC/DATA ++ * endian swapping with respect to the CPU configured endianness ++ * ++ * DATA ENDN mmio descriptor ++ * 0 0 BE invalid ++ * 0 1 BE LE ++ * 1 0 BE BE ++ * 1 1 BE invalid ++ * ++ * Since BCM63XX SoCs are configured to be in big-endian mode ++ * we want configuration at line 3. ++ */ ++void bcm63xx_usb_priv_ohci_cfg_set(void) ++{ ++ u32 reg; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); ++ ++ if (BCMCPU_IS_6348()) ++ bcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG); ++ else if (BCMCPU_IS_6358()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG); ++ /* ++ * The magic value comes for the original vendor BSP ++ * and is needed for USB to work. Datasheet does not ++ * help, so the magic value is used as-is. ++ */ ++ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, ++ USBH_PRIV_TEST_6358_REG); ++ ++ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); ++} ++ ++void bcm63xx_usb_priv_ehci_cfg_set(void) ++{ ++ u32 reg; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&usb_priv_reg_lock, flags); ++ ++ if (BCMCPU_IS_6358()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG); ++ ++ /* ++ * The magic value comes for the original vendor BSP ++ * and is needed for USB to work. Datasheet does not ++ * help, so the magic value is used as-is. ++ */ ++ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, ++ USBH_PRIV_TEST_6358_REG); ++ ++ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } ++ ++ spin_unlock_irqrestore(&usb_priv_reg_lock, flags); ++} +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h +@@ -5,5 +5,7 @@ + + void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device); + void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on); ++void bcm63xx_usb_priv_ohci_cfg_set(void); ++void bcm63xx_usb_priv_ehci_cfg_set(void); + + #endif /* BCM63XX_USB_PRIV_H_ */ diff --git a/target/linux/brcm63xx/patches-4.1/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch b/target/linux/brcm63xx/patches-4.1/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch new file mode 100644 index 0000000..768dcca --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch @@ -0,0 +1,62 @@ +From 94ec618bd1a6b07fafbbfc9bcc54e7f9360ff9a0 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:23 +0100 +Subject: [PATCH 05/11] MIPS: BCM63XX: introduce BCM63XX_OHCI configuration + symbol + +This configuration symbol can be used by CPUs supporting the on-chip +OHCI controller, and ensures that all relevant OHCI-related +configuration options are correctly selected. So far, OHCI support is +available for the 6328, 6348, 6358 and 6358 SoCs. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Kconfig | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -6,10 +6,17 @@ config BCM63XX_CPU_3368 + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + ++config BCM63XX_OHCI ++ bool ++ select USB_ARCH_HAS_OHCI ++ select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD ++ select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6338 + bool "support 6338 CPU" +@@ -24,21 +31,25 @@ config BCM63XX_CPU_6348 + bool "support 6348 CPU" + select SYS_HAS_CPU_BMIPS32_3300 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6358 + bool "support 6358 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6362 + bool "support 6362 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + + config BCM63XX_CPU_6368 + bool "support 6368 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" diff --git a/target/linux/brcm63xx/patches-4.1/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch b/target/linux/brcm63xx/patches-4.1/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch new file mode 100644 index 0000000..111d481 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch @@ -0,0 +1,138 @@ +From 30d22baef255c99a12c4858ce4ab0d45f0d8c9ae Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:24 +0100 +Subject: [PATCH 06/11] MIPS: BCM63XX: add support for the on-chip OHCI + controller + +Broadcom BCM63XX SoCs include an on-chip OHCI controller which can be +driven by the ohci-platform generic driver by using specific power +on/off/suspend callback to manage clocks and hardware specific +configuration. + +Signed-off-by: Maxime Bizon +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/dev-usb-ohci.c | 94 ++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h | 6 ++ + 3 files changed, 101 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/dev-usb-ohci.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,7 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-usbd.o usb-common.o ++ dev-wdt.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/dev-usb-ohci.c +@@ -0,0 +1,94 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2013 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static struct resource ohci_resources[] = { ++ { ++ .start = -1, /* filled at runtime */ ++ .end = -1, /* filled at runtime */ ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = -1, /* filled at runtime */ ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ohci_dmamask = DMA_BIT_MASK(32); ++ ++static struct clk *usb_host_clock; ++ ++static int bcm63xx_ohci_power_on(struct platform_device *pdev) ++{ ++ usb_host_clock = clk_get(&pdev->dev, "usbh"); ++ if (IS_ERR_OR_NULL(usb_host_clock)) ++ return -ENODEV; ++ ++ clk_prepare_enable(usb_host_clock); ++ ++ bcm63xx_usb_priv_ohci_cfg_set(); ++ ++ return 0; ++} ++ ++static void bcm63xx_ohci_power_off(struct platform_device *pdev) ++{ ++ if (!IS_ERR_OR_NULL(usb_host_clock)) { ++ clk_disable_unprepare(usb_host_clock); ++ clk_put(usb_host_clock); ++ } ++} ++ ++static struct usb_ohci_pdata bcm63xx_ohci_pdata = { ++ .big_endian_desc = 1, ++ .big_endian_mmio = 1, ++ .no_big_frame_no = 1, ++ .num_ports = 1, ++ .power_on = bcm63xx_ohci_power_on, ++ .power_off = bcm63xx_ohci_power_off, ++ .power_suspend = bcm63xx_ohci_power_off, ++}; ++ ++static struct platform_device bcm63xx_ohci_device = { ++ .name = "ohci-platform", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(ohci_resources), ++ .resource = ohci_resources, ++ .dev = { ++ .platform_data = &bcm63xx_ohci_pdata, ++ .dma_mask = &ohci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++int __init bcm63xx_ohci_register(void) ++{ ++ if (BCMCPU_IS_6345() || BCMCPU_IS_6338()) ++ return -ENODEV; ++ ++ ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0); ++ ohci_resources[0].end = ohci_resources[0].start; ++ ohci_resources[0].end += RSET_OHCI_SIZE - 1; ++ ohci_resources[1].start = bcm63xx_get_irq_number(IRQ_OHCI0); ++ ++ return platform_device_register(&bcm63xx_ohci_device); ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h +@@ -0,0 +1,6 @@ ++#ifndef BCM63XX_DEV_USB_OHCI_H_ ++#define BCM63XX_DEV_USB_OHCI_H_ ++ ++int bcm63xx_ohci_register(void); ++ ++#endif /* BCM63XX_DEV_USB_OHCI_H_ */ diff --git a/target/linux/brcm63xx/patches-4.1/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch b/target/linux/brcm63xx/patches-4.1/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch new file mode 100644 index 0000000..2c26482 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch @@ -0,0 +1,36 @@ +From 33ef960aed15f9a98a2c51d8d794cd72418e0be4 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:25 +0100 +Subject: [PATCH 07/11] MIPS: BCM63XX: register OHCI controller if board + enables it + +BCM63XX-based boards can control the registration of the OHCI controller +by setting their has_ohci0 flag to 1. Handle this in the generic +code dealing with board registration and call the actual helper to +register the OHCI controller. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -898,6 +899,9 @@ int __init board_register_devices(void) + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + ++ if (board.has_ohci0) ++ bcm63xx_ohci_register(); ++ + if (board.has_dsp) + bcm63xx_dsp_register(&board.dsp); + diff --git a/target/linux/brcm63xx/patches-4.1/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch b/target/linux/brcm63xx/patches-4.1/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch new file mode 100644 index 0000000..bce91e3 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch @@ -0,0 +1,62 @@ +From 00da1683364e58c6430a4577123d01037f8faddc Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:26 +0100 +Subject: [PATCH 08/11] MIPS: BCM63XX: introduce BCM63XX_EHCI configuration + symbol + +This configuration symbol can be used by CPUs supporting the on-chip +EHCI controller, and ensures that all relevant EHCI-related +configuration options are selected. So far BCM6328, BCM6358 and BCM6368 +have an EHCI controller and do select this symbol. Update +drivers/usb/host/Kconfig with BCM63XX to update direct unmet +dependencies. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Kconfig | 9 +++++++++ + drivers/usb/host/Kconfig | 5 +++-- + 2 files changed, 12 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -12,11 +12,18 @@ config BCM63XX_OHCI + select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD + select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD + ++config BCM63XX_EHCI ++ bool ++ select USB_ARCH_HAS_EHCI ++ select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD ++ select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6338 + bool "support 6338 CPU" +@@ -38,18 +45,21 @@ config BCM63XX_CPU_6358 + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6362 + bool "support 6362 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6368 + bool "support 6368 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI + select BCM63XX_OHCI ++ select BCM63XX_EHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" diff --git a/target/linux/brcm63xx/patches-4.1/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch b/target/linux/brcm63xx/patches-4.1/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch new file mode 100644 index 0000000..8b1f8d2 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch @@ -0,0 +1,137 @@ +From e38f13bd6408769c0b565bb1079024f496eee121 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:27 +0100 +Subject: [PATCH 09/11] MIPS: BCM63XX: add support for the on-chip EHCI + controller + +Broadcom BCM63XX SoCs include an on-chip EHCI controller which can be +driven by the generic ehci-platform driver by using specific power +on/off/suspend callbacks to manage clocks and hardware specific +configuration. + +Signed-off-by: Maxime Bizon +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/dev-usb-ehci.c | 92 ++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h | 6 ++ + 3 files changed, 99 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/dev-usb-ehci.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -1,7 +1,8 @@ + obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ +- dev-wdt.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o ++ dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ ++ usb-common.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -0,0 +1,92 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2013 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static struct resource ehci_resources[] = { ++ { ++ .start = -1, /* filled at runtime */ ++ .end = -1, /* filled at runtime */ ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = -1, /* filled at runtime */ ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ehci_dmamask = DMA_BIT_MASK(32); ++ ++static struct clk *usb_host_clock; ++ ++static int bcm63xx_ehci_power_on(struct platform_device *pdev) ++{ ++ usb_host_clock = clk_get(&pdev->dev, "usbh"); ++ if (IS_ERR_OR_NULL(usb_host_clock)) ++ return -ENODEV; ++ ++ clk_prepare_enable(usb_host_clock); ++ ++ bcm63xx_usb_priv_ehci_cfg_set(); ++ ++ return 0; ++} ++ ++static void bcm63xx_ehci_power_off(struct platform_device *pdev) ++{ ++ if (!IS_ERR_OR_NULL(usb_host_clock)) { ++ clk_disable_unprepare(usb_host_clock); ++ clk_put(usb_host_clock); ++ } ++} ++ ++static struct usb_ehci_pdata bcm63xx_ehci_pdata = { ++ .big_endian_desc = 1, ++ .big_endian_mmio = 1, ++ .power_on = bcm63xx_ehci_power_on, ++ .power_off = bcm63xx_ehci_power_off, ++ .power_suspend = bcm63xx_ehci_power_off, ++}; ++ ++static struct platform_device bcm63xx_ehci_device = { ++ .name = "ehci-platform", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(ehci_resources), ++ .resource = ehci_resources, ++ .dev = { ++ .platform_data = &bcm63xx_ehci_pdata, ++ .dma_mask = &ehci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++int __init bcm63xx_ehci_register(void) ++{ ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ return 0; ++ ++ ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); ++ ehci_resources[0].end = ehci_resources[0].start; ++ ehci_resources[0].end += RSET_EHCI_SIZE - 1; ++ ehci_resources[1].start = bcm63xx_get_irq_number(IRQ_EHCI0); ++ ++ return platform_device_register(&bcm63xx_ehci_device); ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h +@@ -0,0 +1,6 @@ ++#ifndef BCM63XX_DEV_USB_EHCI_H_ ++#define BCM63XX_DEV_USB_EHCI_H_ ++ ++int bcm63xx_ehci_register(void); ++ ++#endif /* BCM63XX_DEV_USB_EHCI_H_ */ diff --git a/target/linux/brcm63xx/patches-4.1/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch b/target/linux/brcm63xx/patches-4.1/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch new file mode 100644 index 0000000..641a57c --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch @@ -0,0 +1,36 @@ +From 709ef2034f5ba06da35f89856ad7baf2b7a41287 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:28 +0100 +Subject: [PATCH 10/11] MIPS: BCM63XX: register EHCI controller if board + enables it + +BCM63XX-based board can control the registration of the EHCI controller +by setting their has_ehci0 flag to 1. Handle this in the generic +code dealing with board registration and call the actual helper to register +the EHCI controller. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -899,6 +900,9 @@ int __init board_register_devices(void) + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + ++ if (board.has_ehci0) ++ bcm63xx_ehci_register(); ++ + if (board.has_ohci0) + bcm63xx_ohci_register(); + diff --git a/target/linux/brcm63xx/patches-4.1/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch b/target/linux/brcm63xx/patches-4.1/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch new file mode 100644 index 0000000..6d91129 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch @@ -0,0 +1,24 @@ +From 111bbd770441ab34f9da5bb1d85767a9b75227b4 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:30 +0100 +Subject: [PATCH 12/12] MIPS: BCM63XX: EHCI controller does not support + overcurrent + +This patch sets the ignore_oc flag for the BCM63XX EHCI controller as it +does not support proper overcurrent reporting. + +Signed-off-by: Florian Fainelli +--- + arch/mips/bcm63xx/dev-usb-ehci.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -61,6 +61,7 @@ static void bcm63xx_ehci_power_off(struc + static struct usb_ehci_pdata bcm63xx_ehci_pdata = { + .big_endian_desc = 1, + .big_endian_mmio = 1, ++ .ignore_oc = 1, + .power_on = bcm63xx_ehci_power_on, + .power_off = bcm63xx_ehci_power_off, + .power_suspend = bcm63xx_ehci_power_off, diff --git a/target/linux/brcm63xx/patches-4.1/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch b/target/linux/brcm63xx/patches-4.1/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch new file mode 100644 index 0000000..00dc9c9 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch @@ -0,0 +1,38 @@ +From 3f650fc30aa0badf9d02842ce396cea3eef2eeaa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 1 Jul 2011 23:16:47 +0200 +Subject: [PATCH 49/79] SPI: Allow specifying the parsers for SPI flash + +Signed-off-by: Jonas Gorski +--- + include/linux/spi/flash.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -2,7 +2,7 @@ + #define LINUX_SPI_FLASH_H + + struct mtd_partition; +- ++struct mtd_part_parser_data; + /** + * struct flash_platform_data: board-specific flash data + * @name: optional flash device name (eg, as used with mtdparts=) +@@ -10,6 +10,8 @@ struct mtd_partition; + * @nr_parts: number of mtd_partitions for static partitoning + * @type: optional flash device type (e.g. m25p80 vs m25p64), for use + * with chips that can't be queried for JEDEC or other IDs ++ * @part_probe_types: optional list of MTD parser names to use for ++ * partitioning + * + * Board init code (in arch/.../mach-xxx/board-yyy.c files) can + * provide information about SPI flash parts (such as DataFlash) to +@@ -25,6 +27,7 @@ struct flash_platform_data { + + char *type; + ++ const char **part_probe_types; + /* we'll likely add more ... use JEDEC IDs, etc */ + }; + diff --git a/target/linux/brcm63xx/patches-4.1/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch b/target/linux/brcm63xx/patches-4.1/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch new file mode 100644 index 0000000..e58cd59 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch @@ -0,0 +1,23 @@ +From c7c3c338cb25d7f55ddb3f6bfbf3572758ca3896 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 10 Nov 2011 16:53:08 +0100 +Subject: [PATCH 50/79] MTD: DEVICES: m25p80: use parsers if provided in flash + platform data + +Signed-off-by: Jonas Gorski +--- + drivers/mtd/devices/m25p80.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -234,7 +234,8 @@ static int m25p_probe(struct spi_device + + ppdata.of_node = spi->dev.of_node; + +- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, ++ return mtd_device_parse_register(&flash->mtd, ++ data ? data->part_probe_types : NULL, &ppdata, + data ? data->parts : NULL, + data ? data->nr_parts : 0); + } diff --git a/target/linux/brcm63xx/patches-4.1/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch b/target/linux/brcm63xx/patches-4.1/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch new file mode 100644 index 0000000..fb064b8 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch @@ -0,0 +1,90 @@ +From 5fb4e8d7287ac8fcb33aae8b1e9e22c5a3c392bd Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 10 Nov 2011 17:33:40 +0100 +Subject: [PATCH 51/79] MTD: DEVICES: m25p80: add support for limiting reads + +Signed-off-by: Jonas Gorski +--- + drivers/mtd/devices/m25p80.c | 29 +++++++++++++++++++++++++++-- + include/linux/spi/flash.h | 4 ++++ + 2 files changed, 31 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -32,6 +32,7 @@ struct m25p { + struct spi_device *spi; + struct spi_nor spi_nor; + struct mtd_info mtd; ++ int max_transfer_len; + u8 command[MAX_CMD_SIZE]; + }; + +@@ -121,7 +122,7 @@ static inline unsigned int m25p80_rx_nbi + * Read an address range from the nor chip. The address range + * may be any size provided it is within the physical boundaries. + */ +-static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, ++static int __m25p80_read(struct spi_nor *nor, loff_t from, size_t len, + size_t *retlen, u_char *buf) + { + struct m25p *flash = nor->priv; +@@ -154,6 +155,29 @@ static int m25p80_read(struct spi_nor *n + return 0; + } + ++static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct m25p *flash = nor->priv; ++ size_t off; ++ size_t read_len = flash->max_transfer_len; ++ size_t part_len; ++ int ret = 0; ++ ++ if (!read_len) ++ return __m25p80_read(nor, from, len, retlen, buf); ++ ++ *retlen = 0; ++ ++ for (off = 0; off < len && !ret; off += read_len) { ++ ret = __m25p80_read(nor, from + off, min(len - off, read_len), ++ &part_len, buf + off); ++ *retlen += part_len; ++ } ++ ++ return ret; ++} ++ + static int m25p80_erase(struct spi_nor *nor, loff_t offset) + { + struct m25p *flash = nor->priv; +@@ -228,6 +252,9 @@ static int m25p_probe(struct spi_device + else + flash_name = spi->modalias; + ++ if (data) ++ flash->max_transfer_len = data->max_transfer_len; ++ + ret = spi_nor_scan(nor, flash_name, mode); + if (ret) + return ret; +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -13,6 +13,8 @@ struct mtd_part_parser_data; + * @part_probe_types: optional list of MTD parser names to use for + * partitioning + * ++ * @max_transfer_len: option maximum read/write length limitation for ++ * SPI controllers not able to transfer any length commands. + * Board init code (in arch/.../mach-xxx/board-yyy.c files) can + * provide information about SPI flash parts (such as DataFlash) to + * help set up the device and its appropriate default partitioning. +@@ -28,6 +30,8 @@ struct flash_platform_data { + char *type; + + const char **part_probe_types; ++ ++ unsigned int max_transfer_len; + /* we'll likely add more ... use JEDEC IDs, etc */ + }; + diff --git a/target/linux/brcm63xx/patches-4.1/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch b/target/linux/brcm63xx/patches-4.1/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch new file mode 100644 index 0000000..f615deb --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch @@ -0,0 +1,66 @@ +From 6ac09efa8f0e189ffe7dd7b0889289de56ee44cc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 19 Jan 2014 12:18:03 +0100 +Subject: [PATCH] USB: EHCI: allow limiting ports for ehci-platform + +In the same way as the ohci platform driver allows limiting ports, +enable the same for ehci. This prevents a mismatch in the available +ports between ehci/ohci on USB 2.0 controllers. + +This is needed if the USB host controller always reports the maximum +number of ports regardless of the number of available ports (because +one might be set to be usb device). + +Signed-off-by: Jonas Gorski +--- + drivers/usb/host/ehci-hcd.c | 4 ++++ + drivers/usb/host/ehci-platform.c | 2 ++ + drivers/usb/host/ehci.h | 1 + + include/linux/usb/ehci_pdriver.h | 1 + + 4 files changed, 8 insertions(+) + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -665,6 +665,10 @@ int ehci_setup(struct usb_hcd *hcd) + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ++ if (ehci->num_ports) { ++ ehci->hcs_params &= ~0xf; /* bits 3:0, ports on HC */ ++ ehci->hcs_params |= ehci->num_ports; ++ } + + ehci->sbrn = HCD_USB2; + +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -59,6 +59,9 @@ static int ehci_platform_reset(struct us + hcd->has_tt = pdata->has_tt; + ehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug; + ++ if (pdata->num_ports && pdata->num_ports <= 15) ++ ehci->num_ports = pdata->num_ports; ++ + if (pdata->pre_setup) { + retval = pdata->pre_setup(hcd); + if (retval < 0) +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -213,6 +213,7 @@ struct ehci_hcd { /* one per controlle + u32 command; + + /* SILICON QUIRKS */ ++ unsigned int num_ports; + unsigned no_selective_suspend:1; + unsigned has_fsl_port_bug:1; /* FreeScale */ + unsigned big_endian_mmio:1; +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -42,6 +42,7 @@ struct usb_hcd; + */ + struct usb_ehci_pdata { + int caps_offset; ++ unsigned int num_ports; + unsigned has_tt:1; + unsigned has_synopsys_hc_bug:1; + unsigned big_endian_desc:1; diff --git a/target/linux/brcm63xx/patches-4.1/207-MIPS-BCM63XX-move-device-registration-code-into-its-.patch b/target/linux/brcm63xx/patches-4.1/207-MIPS-BCM63XX-move-device-registration-code-into-its-.patch new file mode 100644 index 0000000..4e5e611 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/207-MIPS-BCM63XX-move-device-registration-code-into-its-.patch @@ -0,0 +1,493 @@ +From 5a50cb0d53344a2429831b00925d6183d4d332e1 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Mar 2014 03:54:05 +0100 +Subject: [PATCH 40/44] MIPS: BCM63XX: move device registration code into its + own file + +Move device registration code into its own file to allow sharing it +between board implementations. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/Makefile | 1 + + arch/mips/bcm63xx/boards/board_bcm963xx.c | 188 +------------------------- + arch/mips/bcm63xx/boards/board_common.c | 215 ++++++++++++++++++++++++++++++ + arch/mips/bcm63xx/boards/board_common.h | 8 ++ + 4 files changed, 223 insertions(+), 183 deletions(-) + create mode 100644 arch/mips/bcm63xx/boards/board_common.c + create mode 100644 arch/mips/bcm63xx/boards/board_common.h + +--- a/arch/mips/bcm63xx/boards/Makefile ++++ b/arch/mips/bcm63xx/boards/Makefile +@@ -1 +1,2 @@ ++obj-y += board_common.o + obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -10,35 +10,22 @@ + #include + #include + #include +-#include +-#include + #include + #include + #include +-#include + #include + #include + #include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include + #include + ++#include "board_common.h" ++ + #include + + #define PFX "board_bcm963xx: " + + #define HCS_OFFSET_128K 0x20000 + +-static struct board_info board; +- + /* + * known 3368 boards + */ +@@ -711,52 +698,6 @@ static const struct board_info __initcon + }; + + /* +- * Register a sane SPROMv2 to make the on-board +- * bcm4318 WLAN work +- */ +-#ifdef CONFIG_SSB_PCIHOST +-static struct ssb_sprom bcm63xx_sprom = { +- .revision = 0x02, +- .board_rev = 0x17, +- .country_code = 0x0, +- .ant_available_bg = 0x3, +- .pa0b0 = 0x15ae, +- .pa0b1 = 0xfa85, +- .pa0b2 = 0xfe8d, +- .pa1b0 = 0xffff, +- .pa1b1 = 0xffff, +- .pa1b2 = 0xffff, +- .gpio0 = 0xff, +- .gpio1 = 0xff, +- .gpio2 = 0xff, +- .gpio3 = 0xff, +- .maxpwr_bg = 0x004c, +- .itssi_bg = 0x00, +- .boardflags_lo = 0x2848, +- .boardflags_hi = 0x0000, +-}; +- +-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +-{ +- if (bus->bustype == SSB_BUSTYPE_PCI) { +- memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); +- return 0; +- } else { +- printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); +- return -EINVAL; +- } +-} +-#endif +- +-/* +- * return board name for /proc/cpuinfo +- */ +-const char *board_get_name(void) +-{ +- return board.name; +-} +- +-/* + * early init callback, read nvram data from flash and checksum it + */ + void __init board_prom_init(void) +@@ -801,141 +742,16 @@ void __init board_prom_init(void) + if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) + continue; + /* copy, board desc array is marked initdata */ +- memcpy(&board, bcm963xx_boards[i], sizeof(board)); ++ board_early_setup(bcm963xx_boards[i]); + break; + } + +- /* bail out if board is not found, will complain later */ +- if (!board.name[0]) { ++ /* warn if board is not found, will complain later */ ++ if (i == ARRAY_SIZE(bcm963xx_boards)) { + char name[17]; + memcpy(name, board_name, 16); + name[16] = 0; + printk(KERN_ERR PFX "unknown bcm963xx board: %s\n", + name); +- return; +- } +- +- /* setup pin multiplexing depending on board enabled device, +- * this has to be done this early since PCI init is done +- * inside arch_initcall */ +- val = 0; +- +-#ifdef CONFIG_PCI +- if (board.has_pci) { +- bcm63xx_pci_enabled = 1; +- if (BCMCPU_IS_6348()) +- val |= GPIO_MODE_6348_G2_PCI; +- } +-#endif +- +- if (board.has_pccard) { +- if (BCMCPU_IS_6348()) +- val |= GPIO_MODE_6348_G1_MII_PCCARD; +- } +- +- if (board.has_enet0 && !board.enet0.use_internal_phy) { +- if (BCMCPU_IS_6348()) +- val |= GPIO_MODE_6348_G3_EXT_MII | +- GPIO_MODE_6348_G0_EXT_MII; +- } +- +- if (board.has_enet1 && !board.enet1.use_internal_phy) { +- if (BCMCPU_IS_6348()) +- val |= GPIO_MODE_6348_G3_EXT_MII | +- GPIO_MODE_6348_G0_EXT_MII; +- } +- +- bcm_gpio_writel(val, GPIO_MODE_REG); +-} +- +-/* +- * second stage init callback, good time to panic if we couldn't +- * identify on which board we're running since early printk is working +- */ +-void __init board_setup(void) +-{ +- if (!board.name[0]) +- panic("unable to detect bcm963xx board"); +- printk(KERN_INFO PFX "board name: %s\n", board.name); +- +- /* make sure we're running on expected cpu */ +- if (bcm63xx_get_cpu_id() != board.expected_cpu_id) +- panic("unexpected CPU for bcm963xx board"); +-} +- +-static struct gpio_led_platform_data bcm63xx_led_data; +- +-static struct platform_device bcm63xx_gpio_leds = { +- .name = "leds-gpio", +- .id = 0, +- .dev.platform_data = &bcm63xx_led_data, +-}; +- +-/* +- * third stage init callback, register all board devices. +- */ +-int __init board_register_devices(void) +-{ +- if (board.has_uart0) +- bcm63xx_uart_register(0); +- +- if (board.has_uart1) +- bcm63xx_uart_register(1); +- +- if (board.has_pccard) +- bcm63xx_pcmcia_register(); +- +- if (board.has_enet0 && +- !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr)) +- bcm63xx_enet_register(0, &board.enet0); +- +- if (board.has_enet1 && +- !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr)) +- bcm63xx_enet_register(1, &board.enet1); +- +- if (board.has_enetsw && +- !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr)) +- bcm63xx_enetsw_register(&board.enetsw); +- +- if (board.has_usbd) +- bcm63xx_usbd_register(&board.usbd); +- +- if (board.has_ehci0) +- bcm63xx_ehci_register(); +- +- if (board.has_ohci0) +- bcm63xx_ohci_register(); +- +- if (board.has_dsp) +- bcm63xx_dsp_register(&board.dsp); +- +- /* Generate MAC address for WLAN and register our SPROM, +- * do this after registering enet devices +- */ +-#ifdef CONFIG_SSB_PCIHOST +- if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) { +- memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); +- memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); +- if (ssb_arch_register_fallback_sprom( +- &bcm63xx_get_fallback_sprom) < 0) +- pr_err(PFX "failed to register fallback SPROM\n"); + } +-#endif +- +- bcm63xx_spi_register(); +- +- bcm63xx_hsspi_register(); +- +- bcm63xx_flash_register(); +- +- bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); +- bcm63xx_led_data.leds = board.leds; +- +- platform_device_register(&bcm63xx_gpio_leds); +- +- if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) +- gpio_request_one(board.ephy_reset_gpio, +- board.ephy_reset_gpio_flags, "ephy-reset"); +- +- return 0; + } +--- /dev/null ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -0,0 +1,217 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2008 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFX "board: " ++ ++static struct board_info board; ++ ++/* ++ * Register a sane SPROMv2 to make the on-board ++ * bcm4318 WLAN work ++ */ ++#ifdef CONFIG_SSB_PCIHOST ++static struct ssb_sprom bcm63xx_sprom = { ++ .revision = 0x02, ++ .board_rev = 0x17, ++ .country_code = 0x0, ++ .ant_available_bg = 0x3, ++ .pa0b0 = 0x15ae, ++ .pa0b1 = 0xfa85, ++ .pa0b2 = 0xfe8d, ++ .pa1b0 = 0xffff, ++ .pa1b1 = 0xffff, ++ .pa1b2 = 0xffff, ++ .gpio0 = 0xff, ++ .gpio1 = 0xff, ++ .gpio2 = 0xff, ++ .gpio3 = 0xff, ++ .maxpwr_bg = 0x004c, ++ .itssi_bg = 0x00, ++ .boardflags_lo = 0x2848, ++ .boardflags_hi = 0x0000, ++}; ++ ++int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) ++{ ++ if (bus->bustype == SSB_BUSTYPE_PCI) { ++ memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ return 0; ++ } else { ++ printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); ++ return -EINVAL; ++ } ++} ++#endif ++ ++/* ++ * return board name for /proc/cpuinfo ++ */ ++const char *board_get_name(void) ++{ ++ return board.name; ++} ++ ++/* ++ * setup board for device registration ++ */ ++void __init board_early_setup(const struct board_info *target) ++{ ++ u32 val; ++ ++ memcpy(&board, target, sizeof(board)); ++ ++ /* setup pin multiplexing depending on board enabled device, ++ * this has to be done this early since PCI init is done ++ * inside arch_initcall */ ++ val = 0; ++ ++#ifdef CONFIG_PCI ++ if (board.has_pci) { ++ bcm63xx_pci_enabled = 1; ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G2_PCI; ++ } ++#endif ++ ++ if (board.has_pccard) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G1_MII_PCCARD; ++ } ++ ++ if (board.has_enet0 && !board.enet0.use_internal_phy) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G3_EXT_MII | ++ GPIO_MODE_6348_G0_EXT_MII; ++ } ++ ++ if (board.has_enet1 && !board.enet1.use_internal_phy) { ++ if (BCMCPU_IS_6348()) ++ val |= GPIO_MODE_6348_G3_EXT_MII | ++ GPIO_MODE_6348_G0_EXT_MII; ++ } ++ ++ bcm_gpio_writel(val, GPIO_MODE_REG); ++} ++ ++ ++/* ++ * second stage init callback, good time to panic if we couldn't ++ * identify on which board we're running since early printk is working ++ */ ++void __init board_setup(void) ++{ ++ if (!board.name[0]) ++ panic("unable to detect bcm963xx board"); ++ printk(KERN_INFO PFX "board name: %s\n", board.name); ++ ++ /* make sure we're running on expected cpu */ ++ if (bcm63xx_get_cpu_id() != board.expected_cpu_id) ++ panic("unexpected CPU for bcm963xx board"); ++} ++ ++static struct gpio_led_platform_data bcm63xx_led_data; ++ ++static struct platform_device bcm63xx_gpio_leds = { ++ .name = "leds-gpio", ++ .id = 0, ++ .dev.platform_data = &bcm63xx_led_data, ++}; ++ ++/* ++ * third stage init callback, register all board devices. ++ */ ++int __init board_register_devices(void) ++{ ++ if (board.has_uart0) ++ bcm63xx_uart_register(0); ++ ++ if (board.has_uart1) ++ bcm63xx_uart_register(1); ++ ++ if (board.has_pccard) ++ bcm63xx_pcmcia_register(); ++ ++ if (board.has_enet0 && ++ !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr)) ++ bcm63xx_enet_register(0, &board.enet0); ++ ++ if (board.has_enet1 && ++ !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr)) ++ bcm63xx_enet_register(1, &board.enet1); ++ ++ if (board.has_enetsw && ++ !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr)) ++ bcm63xx_enetsw_register(&board.enetsw); ++ ++ if (board.has_usbd) ++ bcm63xx_usbd_register(&board.usbd); ++ ++ if (board.has_ehci0) ++ bcm63xx_ehci_register(); ++ ++ if (board.has_ohci0) ++ bcm63xx_ohci_register(); ++ ++ if (board.has_dsp) ++ bcm63xx_dsp_register(&board.dsp); ++ ++ /* Generate MAC address for WLAN and register our SPROM, ++ * do this after registering enet devices ++ */ ++#ifdef CONFIG_SSB_PCIHOST ++ if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) { ++ memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); ++ if (ssb_arch_register_fallback_sprom( ++ &bcm63xx_get_fallback_sprom) < 0) ++ pr_err(PFX "failed to register fallback SPROM\n"); ++ } ++#endif ++ ++ bcm63xx_spi_register(); ++ ++ bcm63xx_hsspi_register(); ++ ++ bcm63xx_flash_register(); ++ ++ bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); ++ bcm63xx_led_data.leds = board.leds; ++ ++ platform_device_register(&bcm63xx_gpio_leds); ++ ++ if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) ++ gpio_request_one(board.ephy_reset_gpio, ++ board.ephy_reset_gpio_flags, "ephy-reset"); ++ ++ return 0; ++} +--- /dev/null ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -0,0 +1,8 @@ ++#ifndef __BOARD_COMMON_H ++#define __BOARD_COMMON_H ++ ++#include ++ ++void board_early_setup(const struct board_info *board); ++ ++#endif /* __BOARD_COMMON_H */ diff --git a/target/linux/brcm63xx/patches-4.1/208-MIPS-BCM63XX-pass-a-mac-addresss-allocator-to-board-.patch b/target/linux/brcm63xx/patches-4.1/208-MIPS-BCM63XX-pass-a-mac-addresss-allocator-to-board-.patch new file mode 100644 index 0000000..877030f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/208-MIPS-BCM63XX-pass-a-mac-addresss-allocator-to-board-.patch @@ -0,0 +1,100 @@ +From 4e9c34a37bd3442b286ba55441bfe22c1ac5b65f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Mar 2014 04:08:06 +0100 +Subject: [PATCH 41/44] MIPS: BCM63XX: pass a mac addresss allocator to board + setup + +Pass a mac address allocator to board setup code to allow board +implementations to work with third party bootloaders not using nvram +for configuration storage. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 3 ++- + arch/mips/bcm63xx/boards/board_common.c | 16 ++++++++++------ + arch/mips/bcm63xx/boards/board_common.h | 3 ++- + 3 files changed, 14 insertions(+), 8 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -742,7 +742,8 @@ void __init board_prom_init(void) + if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) + continue; + /* copy, board desc array is marked initdata */ +- board_early_setup(bcm963xx_boards[i]); ++ board_early_setup(bcm963xx_boards[i], ++ bcm63xx_nvram_get_mac_address); + break; + } + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -18,7 +18,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -81,15 +80,20 @@ const char *board_get_name(void) + return board.name; + } + ++static int (*board_get_mac_address)(u8 mac[ETH_ALEN]); ++ + /* + * setup board for device registration + */ +-void __init board_early_setup(const struct board_info *target) ++void __init board_early_setup(const struct board_info *target, ++ int (*get_mac_address)(u8 mac[ETH_ALEN])) + { + u32 val; + + memcpy(&board, target, sizeof(board)); + ++ board_get_mac_address = get_mac_address; ++ + /* setup pin multiplexing depending on board enabled device, + * this has to be done this early since PCI init is done + * inside arch_initcall */ +@@ -162,15 +166,15 @@ int __init board_register_devices(void) + bcm63xx_pcmcia_register(); + + if (board.has_enet0 && +- !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr)) ++ !board_get_mac_address(board.enet0.mac_addr)) + bcm63xx_enet_register(0, &board.enet0); + + if (board.has_enet1 && +- !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr)) ++ !board_get_mac_address(board.enet1.mac_addr)) + bcm63xx_enet_register(1, &board.enet1); + + if (board.has_enetsw && +- !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr)) ++ !board_get_mac_address(board.enetsw.mac_addr)) + bcm63xx_enetsw_register(&board.enetsw); + + if (board.has_usbd) +@@ -189,7 +193,7 @@ int __init board_register_devices(void) + * do this after registering enet devices + */ + #ifdef CONFIG_SSB_PCIHOST +- if (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) { ++ if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { + memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); + if (ssb_arch_register_fallback_sprom( +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -3,6 +3,7 @@ + + #include + +-void board_early_setup(const struct board_info *board); ++void board_early_setup(const struct board_info *board, ++ int (*get_mac_address)(u8 mac[ETH_ALEN])); + + #endif /* __BOARD_COMMON_H */ diff --git a/target/linux/brcm63xx/patches-4.1/302-extended-platform-devices.patch b/target/linux/brcm63xx/patches-4.1/302-extended-platform-devices.patch new file mode 100644 index 0000000..3f5cfc6 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/302-extended-platform-devices.patch @@ -0,0 +1,25 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -206,6 +206,9 @@ int __init board_register_devices(void) + + bcm63xx_hsspi_register(); + ++ if (board.num_devs) ++ platform_add_devices(board.devs, board.num_devs); ++ + bcm63xx_flash_register(); + + bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -53,6 +53,10 @@ struct board_info { + + /* External PHY reset GPIO flags from gpio.h */ + unsigned long ephy_reset_gpio_flags; ++ ++ /* Additional platform devices */ ++ struct platform_device **devs; ++ unsigned int num_devs; + }; + + #endif /* ! BOARD_BCM963XX_H_ */ diff --git a/target/linux/brcm63xx/patches-4.1/303-spi-board-info.patch b/target/linux/brcm63xx/patches-4.1/303-spi-board-info.patch new file mode 100644 index 0000000..ece8691 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/303-spi-board-info.patch @@ -0,0 +1,33 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -209,6 +210,9 @@ int __init board_register_devices(void) + if (board.num_devs) + platform_add_devices(board.devs, board.num_devs); + ++ if (board.num_spis) ++ spi_register_board_info(board.spis, board.num_spis); ++ + bcm63xx_flash_register(); + + bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -57,6 +57,10 @@ struct board_info { + /* Additional platform devices */ + struct platform_device **devs; + unsigned int num_devs; ++ ++ /* Additional platform devices */ ++ struct spi_board_info *spis; ++ unsigned int num_spis; + }; + + #endif /* ! BOARD_BCM963XX_H_ */ diff --git a/target/linux/brcm63xx/patches-4.1/309-cfe_version_mod.patch b/target/linux/brcm63xx/patches-4.1/309-cfe_version_mod.patch new file mode 100644 index 0000000..9a8c106 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/309-cfe_version_mod.patch @@ -0,0 +1,27 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -722,10 +722,20 @@ void __init board_prom_init(void) + + /* dump cfe version */ + cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; +- if (!memcmp(cfe, "cfe-v", 5)) +- snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", +- cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); +- else ++ if (strstarts(cfe, "cfe-")) { ++ if(cfe[4] == 'v') { ++ if(cfe[5] == 'd') ++ snprintf(cfe_version, 11, "%s", (char *) &cfe[5]); ++ else if (cfe[10] > 0) ++ snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u-%u", ++ cfe[5], cfe[6], cfe[7], cfe[8], cfe[9], cfe[10]); ++ else ++ snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", ++ cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); ++ } else { ++ snprintf(cfe_version, 12, "%s", (char *) &cfe[4]); ++ } ++ } else + strcpy(cfe_version, "unknown"); + printk(KERN_INFO PFX "CFE version: %s\n", cfe_version); + diff --git a/target/linux/brcm63xx/patches-4.1/310-cfe_simplify_detection.patch b/target/linux/brcm63xx/patches-4.1/310-cfe_simplify_detection.patch new file mode 100644 index 0000000..e05c91d --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/310-cfe_simplify_detection.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h +@@ -1,6 +1,8 @@ + #ifndef BCM63XX_BOARD_H_ + #define BCM63XX_BOARD_H_ + ++#include ++ + const char *board_get_name(void); + + void board_prom_init(void); +@@ -9,4 +11,8 @@ void board_setup(void); + + int board_register_devices(void); + ++static inline bool bcm63xx_is_cfe_present(void) { ++ return fw_arg3 == 0x43464531; ++} ++ + #endif /* ! BCM63XX_BOARD_H_ */ diff --git a/target/linux/brcm63xx/patches-4.1/311-bcm63xxpart_use_cfedetection.patch b/target/linux/brcm63xx/patches-4.1/311-bcm63xxpart_use_cfedetection.patch new file mode 100644 index 0000000..46d9b47 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/311-bcm63xxpart_use_cfedetection.patch @@ -0,0 +1,51 @@ +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -35,7 +35,7 @@ + + #include + #include +-#include ++#include + + #define BCM63XX_EXTENDED_SIZE 0xBFC00000 /* Extended flash address */ + +@@ -43,30 +43,6 @@ + + #define BCM63XX_CFE_MAGIC_OFFSET 0x4e0 + +-static int bcm63xx_detect_cfe(struct mtd_info *master) +-{ +- char buf[9]; +- int ret; +- size_t retlen; +- +- ret = mtd_read(master, BCM963XX_CFE_VERSION_OFFSET, 5, &retlen, +- (void *)buf); +- buf[retlen] = 0; +- +- if (ret) +- return ret; +- +- if (strncmp("cfe-v", buf, 5) == 0) +- return 0; +- +- /* very old CFE's do not have the cfe-v string, so check for magic */ +- ret = mtd_read(master, BCM63XX_CFE_MAGIC_OFFSET, 8, &retlen, +- (void *)buf); +- buf[retlen] = 0; +- +- return strncmp("CFE1CFE1", buf, 8); +-} +- + static int bcm63xx_parse_cfe_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -85,7 +61,7 @@ static int bcm63xx_parse_cfe_partitions( + u32 computed_crc; + bool rootfs_first = false; + +- if (bcm63xx_detect_cfe(master)) ++ if (!bcm63xx_is_cfe_present()) + return -EINVAL; + + cfe_erasesize = max_t(uint32_t, master->erasesize, diff --git a/target/linux/brcm63xx/patches-4.1/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch b/target/linux/brcm63xx/patches-4.1/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch new file mode 100644 index 0000000..4a5b629 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch @@ -0,0 +1,455 @@ +From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Nov 2014 14:53:12 +0100 +Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq + controller + +Signed-off-by: Jonas Gorski +--- + .../brcm,bcm6345-periph-intc.txt | 50 +++ + drivers/irqchip/Kconfig | 4 + + drivers/irqchip/Makefile | 1 + + drivers/irqchip/irq-bcm6345-periph.c | 339 ++++++++++++++++++++ + include/linux/irqchip/irq-bcm6345-periph.h | 16 + + 5 files changed, 410 insertions(+) + create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt + create mode 100644 drivers/irqchip/irq-bcm6345-periph.c + create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt +@@ -0,0 +1,50 @@ ++Broadcom BCM6345 Level 1 periphery interrupt controller ++ ++This block is a interrupt controller that is typically connected directly ++to one of the HW INT lines on each CPU. Every BCM63XX xDSL chip since ++BCM6345 has contained this hardware. ++ ++Key elements of the hardware design include: ++ ++- 32, 64, or 128 incoming level IRQ lines ++ ++- All onchip peripherals are wired directly to an L2 input ++ ++- A separate instance of the register set for each CPU, allowing individual ++ peripheral IRQs to be routed to any CPU ++ ++- No atomic mask/unmask operations ++ ++- No polarity/level/edge settings ++ ++- No FIFO or priority encoder logic; software is expected to read all ++ 1-4 status words to determine which IRQs are pending ++ ++Required properties: ++ ++- compatible: Should be "brcm,bcm6345-periph-intc". ++- reg: Specifies the base physical address and size of the registers. ++ Multiple register addresses may be specified, and must match the amount of ++ parent interrupts. ++- interrupt-controller: Identifies the node as an interrupt controller. ++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt ++ source, should be 1. ++- interrupt-parent: Specifies the phandle to the parent interrupt controller ++ this one is cascaded from. ++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller ++ node, valid values depend on the type of parent interrupt controller. ++ Multiple lines are used to route interrupts to different cpus, with the first ++ assumed to be for the boot CPU. ++ ++Example: ++ ++periph_intc: interrupt-controller@f0406800 { ++ compatible = "brcm,bcm6345-periph-intc"; ++ reg = <0x10000020 0x10>, <0x10000030 0x10>; ++ ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ ++ interrupt-parent = <&cpu_intc>; ++ interrupts = <2>, <3>; ++}; +--- a/drivers/irqchip/Kconfig ++++ b/drivers/irqchip/Kconfig +@@ -75,6 +75,10 @@ config BRCMSTB_L2_IRQ + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + ++config BCM6345_PERIPH_IRQ ++ bool ++ select IRQ_DOMAIN ++ + config DW_APB_ICTL + bool + select GENERIC_IRQ_CHIP +--- a/drivers/irqchip/Makefile ++++ b/drivers/irqchip/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_MVEBU) += irq-armada- + obj-$(CONFIG_ARCH_MXS) += irq-mxs.o + obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o + obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o ++obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o + obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o + obj-$(CONFIG_METAG) += irq-metag-ext.o + obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o +--- /dev/null ++++ b/drivers/irqchip/irq-bcm6345-periph.c +@@ -0,0 +1,339 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2014 Jonas Gorski ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_BCM63XX ++#include ++ ++#define VIRQ_BASE IRQ_INTERNAL_BASE ++#else ++#define VIRQ_BASE 0 ++#endif ++ ++#include "irqchip.h" ++ ++#define MAX_WORDS 4 ++#define MAX_PARENT_IRQS 2 ++#define IRQS_PER_WORD 32 ++ ++struct intc_block { ++ int parent_irq; ++ void __iomem *base; ++ void __iomem *en_reg[MAX_WORDS]; ++ void __iomem *status_reg[MAX_WORDS]; ++ u32 mask_cache[MAX_WORDS]; ++}; ++ ++struct intc_data { ++ struct irq_chip chip; ++ struct intc_block block[MAX_PARENT_IRQS]; ++ ++ int num_words; ++ ++ struct irq_domain *domain; ++ raw_spinlock_t lock; ++}; ++ ++static void bcm6345_periph_irq_handle(unsigned int irq, struct irq_desc *desc) ++{ ++ struct intc_data *data = irq_desc_get_handler_data(desc); ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct intc_block *block; ++ unsigned int idx; ++ ++ chained_irq_enter(chip, desc); ++ ++ for (idx = 0; idx < MAX_PARENT_IRQS; idx++) ++ if (irq == data->block[idx].parent_irq) ++ block = &data->block[idx]; ++ ++ for (idx = 0; idx < data->num_words; idx++) { ++ int base = idx * IRQS_PER_WORD; ++ unsigned long pending; ++ int hw_irq; ++ ++ raw_spin_lock(&data->lock); ++ pending = __raw_readl(block->en_reg[idx]) & ++ __raw_readl(block->status_reg[idx]); ++ raw_spin_unlock(&data->lock); ++ ++ for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) { ++ int virq; ++ ++ virq = irq_find_mapping(data->domain, base + hw_irq); ++ generic_handle_irq(virq); ++ } ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit, ++ bool enable) ++{ ++ u32 val; ++ ++ val = __raw_readl(block->en_reg[reg]); ++ if (enable) ++ val |= BIT(bit); ++ else ++ val &= ~BIT(bit); ++ __raw_writel(val, block->en_reg[reg]); ++} ++ ++static void bcm6345_periph_irq_mask(struct irq_data *data) ++{ ++ unsigned int i, reg, bit; ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ ++ reg = hwirq / IRQS_PER_WORD; ++ bit = hwirq % IRQS_PER_WORD; ++ ++ raw_spin_lock(&priv->lock); ++ for (i = 0; i < MAX_PARENT_IRQS; i++) { ++ struct intc_block *block = &priv->block[i]; ++ ++ if (!block->parent_irq) ++ break; ++ ++ __bcm6345_periph_enable(block, reg, bit, false); ++ } ++ raw_spin_unlock(&priv->lock); ++} ++ ++static void bcm6345_periph_irq_unmask(struct irq_data *data) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ unsigned int i, reg, bit; ++ ++ reg = hwirq / IRQS_PER_WORD; ++ bit = hwirq % IRQS_PER_WORD; ++ ++ raw_spin_lock(&priv->lock); ++ for (i = 0; i < MAX_PARENT_IRQS; i++) { ++ struct intc_block *block = &priv->block[i]; ++ ++ if (!block->parent_irq) ++ break; ++ ++ if (block->mask_cache[reg] & BIT(bit)) ++ __bcm6345_periph_enable(block, reg, bit, true); ++ else ++ __bcm6345_periph_enable(block, reg, bit, false); ++ } ++ raw_spin_unlock(&priv->lock); ++} ++ ++#ifdef CONFIG_SMP ++static int bcm6345_periph_set_affinity(struct irq_data *data, ++ const struct cpumask *mask, bool force) ++{ ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ struct intc_data *priv = data->domain->host_data; ++ unsigned int i, reg, bit; ++ unsigned long flags; ++ bool enabled; ++ int cpu; ++ ++ reg = hwirq / IRQS_PER_WORD; ++ bit = hwirq % IRQS_PER_WORD; ++ ++ /* we could route to more than one cpu, but performance ++ suffers, so fix it to one. ++ */ ++ cpu = cpumask_any_and(mask, cpu_online_mask); ++ if (cpu >= nr_cpu_ids) ++ return -EINVAL; ++ ++ if (cpu >= MAX_PARENT_IRQS) ++ return -EINVAL; ++ ++ if (!priv->block[cpu].parent_irq) ++ return -EINVAL; ++ ++ raw_spin_lock_irqsave(&priv->lock, flags); ++ enabled = !irqd_irq_masked(data); ++ for (i = 0; i < MAX_PARENT_IRQS; i++) { ++ struct intc_block *block = &priv->block[i]; ++ ++ if (!block->parent_irq) ++ break; ++ ++ if (i == cpu) { ++ block->mask_cache[reg] |= BIT(bit); ++ __bcm6345_periph_enable(block, reg, bit, enabled); ++ } else { ++ block->mask_cache[reg] &= ~BIT(bit); ++ __bcm6345_periph_enable(block, reg, bit, false); ++ } ++ } ++ raw_spin_unlock_irqrestore(&priv->lock, flags); ++ ++ return 0; ++} ++#endif ++ ++static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq, ++ irq_hw_number_t hw) ++{ ++ struct intc_data *priv = d->host_data; ++ ++ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops bcm6345_periph_domain_ops = { ++ .xlate = irq_domain_xlate_onecell, ++ .map = bcm6345_periph_map, ++}; ++ ++static int __init __bcm6345_periph_intc_init(struct device_node *node, ++ int num_blocks, int *irq, ++ void __iomem **base, int num_words) ++{ ++ struct intc_data *data; ++ unsigned int i, w, status_offset; ++ ++ data = kzalloc(sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ raw_spin_lock_init(&data->lock); ++ ++ status_offset = num_words * sizeof(u32); ++ ++ for (i = 0; i < num_blocks; i++) { ++ struct intc_block *block = &data->block[i]; ++ ++ block->parent_irq = irq[i]; ++ block->base = base[i]; ++ ++ for (w = 0; w < num_words; w++) { ++ int word_offset = sizeof(u32) * ((num_words - w) - 1); ++ ++ block->en_reg[w] = base[i] + word_offset; ++ block->status_reg[w] = base[i] + status_offset; ++ block->status_reg[w] += word_offset; ++ ++ /* route all interrupts to line 0 by default */ ++ if (i == 0) ++ block->mask_cache[w] = 0xffffffff; ++ } ++ ++ irq_set_handler_data(block->parent_irq, data); ++ irq_set_chained_handler(block->parent_irq, ++ bcm6345_periph_irq_handle); ++ } ++ ++ data->num_words = num_words; ++ ++ data->chip.name = "bcm6345-periph-intc"; ++ data->chip.irq_mask = bcm6345_periph_irq_mask; ++ data->chip.irq_unmask = bcm6345_periph_irq_unmask; ++ ++#ifdef CONFIG_SMP ++ if (num_blocks > 1) ++ data->chip.irq_set_affinity = bcm6345_periph_set_affinity; ++#endif ++ ++ data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words, ++ VIRQ_BASE, ++ &bcm6345_periph_domain_ops, data); ++ if (!data->domain) { ++ kfree(data); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++void __init bcm6345_periph_intc_init(int num_blocks, int *irq, ++ void __iomem **base, int num_words) ++{ ++ __bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words); ++} ++ ++#ifdef CONFIG_OF ++static int __init bcm6345_periph_of_init(struct device_node *node, ++ struct device_node *parent) ++{ ++ struct resource res; ++ int num_irqs, ret = -EINVAL; ++ int irqs[MAX_PARENT_IRQS] = { 0 }; ++ void __iomem *bases[MAX_PARENT_IRQS] = { NULL }; ++ int words = 0; ++ int i; ++ ++ num_irqs = of_irq_count(node); ++ ++ if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS) ++ return -EINVAL; ++ ++ for (i = 0; i < num_irqs; i++) { ++ resource_size_t size; ++ ++ irqs[i] = irq_of_parse_and_map(node, i); ++ if (!irqs[i]) ++ goto out_unmap; ++ ++ if (of_address_to_resource(node, i, &res)) ++ goto out_unmap; ++ ++ size = resource_size(&res); ++ switch (size) { ++ case 8: ++ case 16: ++ case 32: ++ size = size / 8; ++ break; ++ default: ++ goto out_unmap; ++ } ++ ++ if (words && words != size) { ++ ret = -EINVAL; ++ goto out_unmap; ++ } ++ words = size; ++ ++ bases[i] = of_iomap(node, i); ++ if (!bases[i]) { ++ ret = -ENOMEM; ++ goto out_unmap; ++ } ++ } ++ ++ ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words); ++ if (!ret) ++ return 0; ++ ++out_unmap: ++ for (i = 0; i < num_irqs; i++) { ++ iounmap(bases[i]); ++ irq_dispose_mapping(irqs[i]); ++ } ++ ++ return ret; ++} ++ ++IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-periph-intc", ++ bcm6345_periph_of_init); ++#endif +--- /dev/null ++++ b/include/linux/irqchip/irq-bcm6345-periph.h +@@ -0,0 +1,16 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2008 Nicolas Schichan ++ */ ++ ++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H ++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H ++ ++void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base, ++ int num_words); ++ ++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */ diff --git a/target/linux/brcm63xx/patches-4.1/321-irqchip-add-support-for-bcm6345-style-external-inter.patch b/target/linux/brcm63xx/patches-4.1/321-irqchip-add-support-for-bcm6345-style-external-inter.patch new file mode 100644 index 0000000..5ee5ee2 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/321-irqchip-add-support-for-bcm6345-style-external-inter.patch @@ -0,0 +1,381 @@ +From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Nov 2014 14:54:27 +0100 +Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external + interrupt controller + +Signed-off-by: Jonas Gorski +--- + .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 29 ++ + drivers/irqchip/Kconfig | 4 + + drivers/irqchip/Makefile | 1 + + drivers/irqchip/irq-bcm6345-ext.c | 287 ++++++++++++++++++++ + include/linux/irqchip/irq-bcm6345-ext.h | 14 + + 5 files changed, 335 insertions(+) + create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt + create mode 100644 drivers/irqchip/irq-bcm6345-ext.c + create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt +@@ -0,0 +1,29 @@ ++Broadcom BCM6345-style external interrupt controller ++ ++Required properties: ++ ++- compatible: Should be "brcm,bcm6345-ext-intc". ++- reg: Specifies the base physical addresses and size of the registers. ++- interrupt-controller: identifies the node as an interrupt controller. ++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt ++ source, Should be 2. ++- interrupt-parent: Specifies the phandle to the parent interrupt controller ++ this one is cascaded from. ++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller ++ node, valid values depend on the type of parent interrupt controller. ++ ++Optional properties: ++ ++- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the ++ register. Defaults to 4. ++ ++Example: ++ ++ext_intc: interrupt-controller@10000018 { ++ compatible = "brcm,bcm6345-ext-intc"; ++ interrupt-parent = <&periph_intc>; ++ #interrupt-cells = <2>; ++ reg = <0x10000018 0x4>; ++ interrupt-controller; ++ interrupts = <24>, <25>, <26>, <27>; ++}; +--- a/drivers/irqchip/Kconfig ++++ b/drivers/irqchip/Kconfig +@@ -75,6 +75,10 @@ config BRCMSTB_L2_IRQ + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + ++config BCM6345_EXT_IRQ ++ bool ++ select IRQ_DOMAIN ++ + config BCM6345_PERIPH_IRQ + bool + select IRQ_DOMAIN +--- a/drivers/irqchip/Makefile ++++ b/drivers/irqchip/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_MVEBU) += irq-armada- + obj-$(CONFIG_ARCH_MXS) += irq-mxs.o + obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o + obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o ++obj-$(CONFIG_BCM6345_EXT_IRQ) += irq-bcm6345-ext.o + obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o + obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o + obj-$(CONFIG_METAG) += irq-metag-ext.o +--- /dev/null ++++ b/drivers/irqchip/irq-bcm6345-ext.c +@@ -0,0 +1,288 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2014 Jonas Gorski ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "irqchip.h" ++ ++#ifdef CONFIG_BCM63XX ++#include ++ ++#define VIRQ_BASE IRQ_EXTERNAL_BASE ++#else ++#define VIRQ_BASE 0 ++#endif ++ ++#define MAX_IRQS 4 ++ ++#define EXTIRQ_CFG_SENSE 0 ++#define EXTIRQ_CFG_STAT 1 ++#define EXTIRQ_CFG_CLEAR 2 ++#define EXTIRQ_CFG_MASK 3 ++#define EXTIRQ_CFG_BOTHEDGE 4 ++#define EXTIRQ_CFG_LEVELSENSE 5 ++ ++struct intc_data { ++ struct irq_chip chip; ++ struct irq_domain *domain; ++ raw_spinlock_t lock; ++ ++ int parent_irq[MAX_IRQS]; ++ void __iomem *reg; ++ int shift; ++}; ++ ++static void bcm6345_ext_intc_irq_handle(unsigned int irq, struct irq_desc *desc) ++{ ++ struct intc_data *data = irq_desc_get_handler_data(desc); ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ unsigned int idx; ++ ++ chained_irq_enter(chip, desc); ++ ++ for (idx = 0; idx < MAX_IRQS; idx++) { ++ if (data->parent_irq[idx] != irq) ++ continue; ++ ++ generic_handle_irq(irq_find_mapping(data->domain, idx)); ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static void bcm6345_ext_intc_irq_ack(struct irq_data *data) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ u32 reg; ++ ++ raw_spin_lock(&priv->lock); ++ reg = __raw_readl(priv->reg); ++ reg |= hwirq << (EXTIRQ_CFG_CLEAR * priv->shift); ++ __raw_writel(reg, priv->reg); ++ raw_spin_unlock(&priv->lock); ++} ++ ++static void bcm6345_ext_intc_irq_mask(struct irq_data *data) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ u32 reg; ++ ++ raw_spin_lock(&priv->lock); ++ reg = __raw_readl(priv->reg); ++ reg &= ~(hwirq << (EXTIRQ_CFG_MASK * priv->shift)); ++ __raw_writel(reg, priv->reg); ++ raw_spin_unlock(&priv->lock); ++} ++ ++static void bcm6345_ext_intc_irq_unmask(struct irq_data *data) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ u32 reg; ++ ++ raw_spin_lock(&priv->lock); ++ reg = __raw_readl(priv->reg); ++ reg |= hwirq << (EXTIRQ_CFG_MASK * priv->shift); ++ __raw_writel(reg, priv->reg); ++ raw_spin_unlock(&priv->lock); ++} ++ ++static int bcm6345_ext_intc_set_type(struct irq_data *data, ++ unsigned int flow_type) ++{ ++ struct intc_data *priv = data->domain->host_data; ++ irq_hw_number_t hwirq = irqd_to_hwirq(data); ++ bool levelsense = 0, sense = 0, bothedge = 0; ++ u32 reg; ++ ++ flow_type &= IRQ_TYPE_SENSE_MASK; ++ ++ if (flow_type == IRQ_TYPE_NONE) ++ flow_type = IRQ_TYPE_LEVEL_LOW; ++ ++ switch (flow_type) { ++ case IRQ_TYPE_EDGE_BOTH: ++ bothedge = 1; ++ break; ++ ++ case IRQ_TYPE_EDGE_RISING: ++ break; ++ ++ case IRQ_TYPE_EDGE_FALLING: ++ sense = 1; ++ break; ++ ++ case IRQ_TYPE_LEVEL_HIGH: ++ levelsense = 1; ++ sense = 1; ++ break; ++ ++ case IRQ_TYPE_LEVEL_LOW: ++ levelsense = 1; ++ break; ++ ++ default: ++ pr_err("bogus flow type combination given!\n"); ++ return -EINVAL; ++ } ++ ++ raw_spin_lock(&priv->lock); ++ reg = __raw_readl(priv->reg); ++ ++ if (levelsense) ++ reg |= hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift); ++ else ++ reg &= ~(hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift)); ++ if (sense) ++ reg |= hwirq << (EXTIRQ_CFG_SENSE * priv->shift); ++ else ++ reg &= ~(hwirq << (EXTIRQ_CFG_SENSE * priv->shift)); ++ if (bothedge) ++ reg |= hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift); ++ else ++ reg &= ~(hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift)); ++ ++ __raw_writel(reg, priv->reg); ++ raw_spin_unlock(&priv->lock); ++ ++ irqd_set_trigger_type(data, flow_type); ++ if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) ++ __irq_set_handler_locked(data->irq, handle_level_irq); ++ else ++ __irq_set_handler_locked(data->irq, handle_edge_irq); ++ ++ return 0; ++} ++ ++static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq, ++ irq_hw_number_t hw) ++{ ++ struct intc_data *priv = d->host_data; ++ ++ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops bcm6345_ext_domain_ops = { ++ .xlate = irq_domain_xlate_twocell, ++ .map = bcm6345_ext_intc_map, ++}; ++ ++static int __init __bcm6345_ext_intc_init(struct device_node *node, ++ int num_irqs, int *irqs, ++ void __iomem *reg, int shift) ++{ ++ struct intc_data *data; ++ unsigned int i; ++ int start = VIRQ_BASE; ++ ++ data = kzalloc(sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ raw_spin_lock_init(&data->lock); ++ ++ for (i = 0; i < num_irqs; i++) { ++ data->parent_irq[i] = irqs[i]; ++ ++ irq_set_handler_data(irqs[i], data); ++ irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle); ++ } ++ ++ data->reg = reg; ++ data->shift = shift; ++ ++ data->chip.name = "bcm6345-ext-intc"; ++ data->chip.irq_ack = bcm6345_ext_intc_irq_ack; ++ data->chip.irq_mask = bcm6345_ext_intc_irq_mask; ++ data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask; ++ data->chip.irq_set_type = bcm6345_ext_intc_set_type; ++ ++ /* ++ * If we have less than 4 irqs, this is the second controller on ++ * bcm63xx. So increase the VIRQ start to not overlap with the first ++ * one, but only do so if we actually use a non-zero start. ++ * ++ * This can be removed when bcm63xx has no legacy users anymore. ++ */ ++ if (start && num_irqs < 4) ++ start += 4; ++ ++ data->domain = irq_domain_add_simple(node, num_irqs, start, ++ &bcm6345_ext_domain_ops, data); ++ if (!data->domain) { ++ kfree(data); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg, ++ int shift) ++{ ++ __bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift); ++} ++ ++#ifdef CONFIG_OF ++static int __init bcm6345_ext_intc_of_init(struct device_node *node, ++ struct device_node *parent) ++{ ++ int num_irqs, ret = -EINVAL; ++ unsigned i; ++ void __iomem *base; ++ int irqs[MAX_IRQS] = { 0 }; ++ u32 shift; ++ ++ num_irqs = of_irq_count(node); ++ ++ if (!num_irqs || num_irqs > MAX_IRQS) ++ return -EINVAL; ++ ++ if (of_property_read_u32(node, "brcm,field-width", &shift)) ++ shift = 4; ++ ++ for (i = 0; i < num_irqs; i++) { ++ irqs[i] = irq_of_parse_and_map(node, i); ++ if (!irqs[i]) { ++ ret = -ENOMEM; ++ goto out_unmap; ++ } ++ } ++ ++ base = of_iomap(node, 0); ++ if (!base) ++ goto out_unmap; ++ ++ ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift); ++ if (!ret) ++ return 0; ++out_unmap: ++ iounmap(base); ++ ++ for (i = 0; i < num_irqs; i++) ++ irq_dispose_mapping(irqs[i]); ++ ++ return ret; ++} ++ ++IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc", ++ bcm6345_ext_intc_of_init); ++#endif +--- /dev/null ++++ b/include/linux/irqchip/irq-bcm6345-ext.h +@@ -0,0 +1,14 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2014 Jonas Gorski ++ */ ++ ++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H ++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H ++ ++void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift); ++ ++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */ diff --git a/target/linux/brcm63xx/patches-4.1/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch b/target/linux/brcm63xx/patches-4.1/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch new file mode 100644 index 0000000..e45ada6 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch @@ -0,0 +1,695 @@ +From 86c5d808d660a6aa72cc41d584776fbc8b2736fe Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Nov 2014 14:55:02 +0100 +Subject: [PATCH 5/8] MIPS: BCM63XX: switch to IRQ_DOMAIN + +Now that we have working IRQ_DOMAIN drivers for both interrupt controllers, +switch to using them. + +Signed-off-by: Jonas Gorski +--- + arch/mips/Kconfig | 3 + + arch/mips/bcm63xx/irq.c | 612 ++++++++--------------------------------------- + 2 files changed, 108 insertions(+), 507 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -197,6 +197,9 @@ config BCM63XX + select SYNC_R4K + select DMA_NONCOHERENT + select IRQ_CPU ++ select BCM6345_EXT_IRQ ++ select BCM6345_PERIPH_IRQ ++ select IRQ_DOMAIN + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_HAS_EARLY_PRINTK +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -12,7 +12,9 @@ + #include + #include + #include +-#include ++#include ++#include ++#include + #include + #include + #include +@@ -20,544 +22,140 @@ + #include + #include + +- +-static DEFINE_SPINLOCK(ipic_lock); +-static DEFINE_SPINLOCK(epic_lock); +- +-static u32 irq_stat_addr[2]; +-static u32 irq_mask_addr[2]; +-static void (*dispatch_internal)(int cpu); +-static int is_ext_irq_cascaded; +-static unsigned int ext_irq_count; +-static unsigned int ext_irq_start, ext_irq_end; +-static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; +-static void (*internal_irq_mask)(struct irq_data *d); +-static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m); +- +- +-static inline u32 get_ext_irq_perf_reg(int irq) +-{ +- if (irq < 4) +- return ext_irq_cfg_reg1; +- return ext_irq_cfg_reg2; +-} +- +-static inline void handle_internal(int intbit) +-{ +- if (is_ext_irq_cascaded && +- intbit >= ext_irq_start && intbit <= ext_irq_end) +- do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE); +- else +- do_IRQ(intbit + IRQ_INTERNAL_BASE); +-} +- +-static inline int enable_irq_for_cpu(int cpu, struct irq_data *d, +- const struct cpumask *m) +-{ +- bool enable = cpu_online(cpu); +- +-#ifdef CONFIG_SMP +- if (m) +- enable &= cpumask_test_cpu(cpu, m); +- else if (irqd_affinity_was_set(d)) +- enable &= cpumask_test_cpu(cpu, d->affinity); +-#endif +- return enable; +-} +- +-/* +- * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not +- * prioritize any interrupt relatively to another. the static counter +- * will resume the loop where it ended the last time we left this +- * function. +- */ +- +-#define BUILD_IPIC_INTERNAL(width) \ +-void __dispatch_internal_##width(int cpu) \ +-{ \ +- u32 pending[width / 32]; \ +- unsigned int src, tgt; \ +- bool irqs_pending = false; \ +- static unsigned int i[2]; \ +- unsigned int *next = &i[cpu]; \ +- unsigned long flags; \ +- \ +- /* read registers in reverse order */ \ +- spin_lock_irqsave(&ipic_lock, flags); \ +- for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ +- u32 val; \ +- \ +- val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \ +- val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \ +- pending[--tgt] = val; \ +- \ +- if (val) \ +- irqs_pending = true; \ +- } \ +- spin_unlock_irqrestore(&ipic_lock, flags); \ +- \ +- if (!irqs_pending) \ +- return; \ +- \ +- while (1) { \ +- unsigned int to_call = *next; \ +- \ +- *next = (*next + 1) & (width - 1); \ +- if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ +- handle_internal(to_call); \ +- break; \ +- } \ +- } \ +-} \ +- \ +-static void __internal_irq_mask_##width(struct irq_data *d) \ +-{ \ +- u32 val; \ +- unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ +- unsigned reg = (irq / 32) ^ (width/32 - 1); \ +- unsigned bit = irq & 0x1f; \ +- unsigned long flags; \ +- int cpu; \ +- \ +- spin_lock_irqsave(&ipic_lock, flags); \ +- for_each_present_cpu(cpu) { \ +- if (!irq_mask_addr[cpu]) \ +- break; \ +- \ +- val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ +- val &= ~(1 << bit); \ +- bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ +- } \ +- spin_unlock_irqrestore(&ipic_lock, flags); \ +-} \ +- \ +-static void __internal_irq_unmask_##width(struct irq_data *d, \ +- const struct cpumask *m) \ +-{ \ +- u32 val; \ +- unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ +- unsigned reg = (irq / 32) ^ (width/32 - 1); \ +- unsigned bit = irq & 0x1f; \ +- unsigned long flags; \ +- int cpu; \ +- \ +- spin_lock_irqsave(&ipic_lock, flags); \ +- for_each_present_cpu(cpu) { \ +- if (!irq_mask_addr[cpu]) \ +- break; \ +- \ +- val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ +- if (enable_irq_for_cpu(cpu, d, m)) \ +- val |= (1 << bit); \ +- else \ +- val &= ~(1 << bit); \ +- bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ +- } \ +- spin_unlock_irqrestore(&ipic_lock, flags); \ +-} +- +-BUILD_IPIC_INTERNAL(32); +-BUILD_IPIC_INTERNAL(64); +- +-asmlinkage void plat_irq_dispatch(void) +-{ +- u32 cause; +- +- do { +- cause = read_c0_cause() & read_c0_status() & ST0_IM; +- +- if (!cause) +- break; +- +- if (cause & CAUSEF_IP7) +- do_IRQ(7); +- if (cause & CAUSEF_IP0) +- do_IRQ(0); +- if (cause & CAUSEF_IP1) +- do_IRQ(1); +- if (cause & CAUSEF_IP2) +- dispatch_internal(0); +- if (is_ext_irq_cascaded) { +- if (cause & CAUSEF_IP3) +- dispatch_internal(1); +- } else { +- if (cause & CAUSEF_IP3) +- do_IRQ(IRQ_EXT_0); +- if (cause & CAUSEF_IP4) +- do_IRQ(IRQ_EXT_1); +- if (cause & CAUSEF_IP5) +- do_IRQ(IRQ_EXT_2); +- if (cause & CAUSEF_IP6) +- do_IRQ(IRQ_EXT_3); +- } +- } while (1); +-} +- +-/* +- * internal IRQs operations: only mask/unmask on PERF irq mask +- * register. +- */ +-static void bcm63xx_internal_irq_mask(struct irq_data *d) +-{ +- internal_irq_mask(d); +-} +- +-static void bcm63xx_internal_irq_unmask(struct irq_data *d) +-{ +- internal_irq_unmask(d, NULL); +-} +- +-/* +- * external IRQs operations: mask/unmask and clear on PERF external +- * irq control register. +- */ +-static void bcm63xx_external_irq_mask(struct irq_data *d) +-{ +- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; +- u32 reg, regaddr; +- unsigned long flags; +- +- regaddr = get_ext_irq_perf_reg(irq); +- spin_lock_irqsave(&epic_lock, flags); +- reg = bcm_perf_readl(regaddr); +- +- if (BCMCPU_IS_6348()) +- reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); +- else +- reg &= ~EXTIRQ_CFG_MASK(irq % 4); +- +- bcm_perf_writel(reg, regaddr); +- spin_unlock_irqrestore(&epic_lock, flags); +- +- if (is_ext_irq_cascaded) +- internal_irq_mask(irq_get_irq_data(irq + ext_irq_start)); +-} +- +-static void bcm63xx_external_irq_unmask(struct irq_data *d) +-{ +- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; +- u32 reg, regaddr; +- unsigned long flags; +- +- regaddr = get_ext_irq_perf_reg(irq); +- spin_lock_irqsave(&epic_lock, flags); +- reg = bcm_perf_readl(regaddr); +- +- if (BCMCPU_IS_6348()) +- reg |= EXTIRQ_CFG_MASK_6348(irq % 4); +- else +- reg |= EXTIRQ_CFG_MASK(irq % 4); +- +- bcm_perf_writel(reg, regaddr); +- spin_unlock_irqrestore(&epic_lock, flags); +- +- if (is_ext_irq_cascaded) +- internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start), +- NULL); +-} +- +-static void bcm63xx_external_irq_clear(struct irq_data *d) +-{ +- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; +- u32 reg, regaddr; +- unsigned long flags; +- +- regaddr = get_ext_irq_perf_reg(irq); +- spin_lock_irqsave(&epic_lock, flags); +- reg = bcm_perf_readl(regaddr); +- +- if (BCMCPU_IS_6348()) +- reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); +- else +- reg |= EXTIRQ_CFG_CLEAR(irq % 4); +- +- bcm_perf_writel(reg, regaddr); +- spin_unlock_irqrestore(&epic_lock, flags); +-} +- +-static int bcm63xx_external_irq_set_type(struct irq_data *d, +- unsigned int flow_type) +-{ +- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; +- u32 reg, regaddr; +- int levelsense, sense, bothedge; +- unsigned long flags; +- +- flow_type &= IRQ_TYPE_SENSE_MASK; +- +- if (flow_type == IRQ_TYPE_NONE) +- flow_type = IRQ_TYPE_LEVEL_LOW; +- +- levelsense = sense = bothedge = 0; +- switch (flow_type) { +- case IRQ_TYPE_EDGE_BOTH: +- bothedge = 1; +- break; +- +- case IRQ_TYPE_EDGE_RISING: +- sense = 1; +- break; +- +- case IRQ_TYPE_EDGE_FALLING: +- break; +- +- case IRQ_TYPE_LEVEL_HIGH: +- levelsense = 1; +- sense = 1; +- break; +- +- case IRQ_TYPE_LEVEL_LOW: +- levelsense = 1; +- break; +- +- default: +- printk(KERN_ERR "bogus flow type combination given !\n"); +- return -EINVAL; +- } +- +- regaddr = get_ext_irq_perf_reg(irq); +- spin_lock_irqsave(&epic_lock, flags); +- reg = bcm_perf_readl(regaddr); +- irq %= 4; +- +- switch (bcm63xx_get_cpu_id()) { +- case BCM6348_CPU_ID: +- if (levelsense) +- reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); +- else +- reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq); +- if (sense) +- reg |= EXTIRQ_CFG_SENSE_6348(irq); +- else +- reg &= ~EXTIRQ_CFG_SENSE_6348(irq); +- if (bothedge) +- reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); +- else +- reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); +- break; +- +- case BCM3368_CPU_ID: +- case BCM6328_CPU_ID: +- case BCM6338_CPU_ID: +- case BCM6345_CPU_ID: +- case BCM6358_CPU_ID: +- case BCM6362_CPU_ID: +- case BCM6368_CPU_ID: +- if (levelsense) +- reg |= EXTIRQ_CFG_LEVELSENSE(irq); +- else +- reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); +- if (sense) +- reg |= EXTIRQ_CFG_SENSE(irq); +- else +- reg &= ~EXTIRQ_CFG_SENSE(irq); +- if (bothedge) +- reg |= EXTIRQ_CFG_BOTHEDGE(irq); +- else +- reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); +- break; +- default: +- BUG(); +- } +- +- bcm_perf_writel(reg, regaddr); +- spin_unlock_irqrestore(&epic_lock, flags); +- +- irqd_set_trigger_type(d, flow_type); +- if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) +- __irq_set_handler_locked(d->irq, handle_level_irq); +- else +- __irq_set_handler_locked(d->irq, handle_edge_irq); +- +- return IRQ_SET_MASK_OK_NOCOPY; +-} +- +-#ifdef CONFIG_SMP +-static int bcm63xx_internal_set_affinity(struct irq_data *data, +- const struct cpumask *dest, +- bool force) +-{ +- if (!irqd_irq_disabled(data)) +- internal_irq_unmask(data, dest); +- +- return 0; +-} +-#endif +- +-static struct irq_chip bcm63xx_internal_irq_chip = { +- .name = "bcm63xx_ipic", +- .irq_mask = bcm63xx_internal_irq_mask, +- .irq_unmask = bcm63xx_internal_irq_unmask, +-}; +- +-static struct irq_chip bcm63xx_external_irq_chip = { +- .name = "bcm63xx_epic", +- .irq_ack = bcm63xx_external_irq_clear, +- +- .irq_mask = bcm63xx_external_irq_mask, +- .irq_unmask = bcm63xx_external_irq_unmask, +- +- .irq_set_type = bcm63xx_external_irq_set_type, +-}; +- +-static struct irqaction cpu_ip2_cascade_action = { +- .handler = no_action, +- .name = "cascade_ip2", +- .flags = IRQF_NO_THREAD, +-}; +- +-#ifdef CONFIG_SMP +-static struct irqaction cpu_ip3_cascade_action = { +- .handler = no_action, +- .name = "cascade_ip3", +- .flags = IRQF_NO_THREAD, +-}; +-#endif +- +-static struct irqaction cpu_ext_cascade_action = { +- .handler = no_action, +- .name = "cascade_extirq", +- .flags = IRQF_NO_THREAD, +-}; +- +-static void bcm63xx_init_irq(void) ++void __init arch_init_irq(void) + { +- int irq_bits; +- +- irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); +- irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); +- irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF); +- irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF); ++ void __iomem *periph_bases[2]; ++ void __iomem *ext_intc_bases[2]; ++ int periph_irq_count, periph_width, ext_irq_count, ext_shift; ++ int periph_irqs[2] = { 2, 3 }; ++ int ext_irqs[6]; ++ ++ periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); ++ periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); ++ ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); ++ ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); + + switch (bcm63xx_get_cpu_id()) { + case BCM3368_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; +- irq_mask_addr[0] += PERF_IRQMASK_3368_REG; +- irq_stat_addr[1] = 0; +- irq_mask_addr[1] = 0; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; ++ periph_bases[0] += PERF_IRQMASK_3368_REG; ++ periph_irq_count = 1; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_3368_EXT_IRQ0; ++ ext_irqs[1] = BCM_3368_EXT_IRQ1; ++ ext_irqs[2] = BCM_3368_EXT_IRQ2; ++ ext_irqs[3] = BCM_3368_EXT_IRQ3; ++ ext_shift = 4; + break; + case BCM6328_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); +- irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); +- irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1); +- irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1); +- irq_bits = 64; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; ++ periph_bases[0] += PERF_IRQMASK_6328_REG(0); ++ periph_bases[1] += PERF_IRQMASK_6328_REG(1); ++ periph_irq_count = 2; ++ periph_width = 2; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_6328_EXT_IRQ0; ++ ext_irqs[1] = BCM_6328_EXT_IRQ1; ++ ext_irqs[2] = BCM_6328_EXT_IRQ2; ++ ext_irqs[3] = BCM_6328_EXT_IRQ3; ++ ext_shift = 4; + break; + case BCM6338_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; +- irq_mask_addr[0] += PERF_IRQMASK_6338_REG; +- irq_stat_addr[1] = 0; +- irq_mask_addr[1] = 0; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; ++ periph_bases[0] += PERF_IRQMASK_6338_REG; ++ periph_irq_count = 1; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338; ++ ext_irq_count = 4; ++ ext_irqs[0] = 3; ++ ext_irqs[1] = 4; ++ ext_irqs[2] = 5; ++ ext_irqs[3] = 6; ++ ext_shift = 4; + break; + case BCM6345_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; +- irq_mask_addr[0] += PERF_IRQMASK_6345_REG; +- irq_stat_addr[1] = 0; +- irq_mask_addr[1] = 0; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; ++ periph_bases[0] += PERF_IRQMASK_6345_REG; ++ periph_irq_count = 1; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345; ++ ext_irq_count = 4; ++ ext_irqs[0] = 3; ++ ext_irqs[1] = 4; ++ ext_irqs[2] = 5; ++ ext_irqs[3] = 6; ++ ext_shift = 4; + break; + case BCM6348_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; +- irq_mask_addr[0] += PERF_IRQMASK_6348_REG; +- irq_stat_addr[1] = 0; +- irq_mask_addr[1] = 0; +- irq_bits = 32; +- ext_irq_count = 4; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; ++ periph_bases[0] += PERF_IRQMASK_6348_REG; ++ periph_irq_count = 1; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348; ++ ext_irq_count = 4; ++ ext_irqs[0] = 3; ++ ext_irqs[1] = 4; ++ ext_irqs[2] = 5; ++ ext_irqs[3] = 6; ++ ext_shift = 5; + break; + case BCM6358_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); +- irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); +- irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1); +- irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1); +- irq_bits = 32; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; ++ periph_bases[0] += PERF_IRQMASK_6358_REG(0); ++ periph_bases[1] += PERF_IRQMASK_6358_REG(1); ++ periph_irq_count = 2; ++ periph_width = 1; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_6358_EXT_IRQ0; ++ ext_irqs[1] = BCM_6358_EXT_IRQ1; ++ ext_irqs[2] = BCM_6358_EXT_IRQ2; ++ ext_irqs[3] = BCM_6358_EXT_IRQ3; ++ ext_shift = 4; + break; + case BCM6362_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); +- irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); +- irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1); +- irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1); +- irq_bits = 64; +- ext_irq_count = 4; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; ++ periph_bases[0] += PERF_IRQMASK_6362_REG(0); ++ periph_bases[1] += PERF_IRQMASK_6362_REG(1); ++ periph_irq_count = 2; ++ periph_width = 2; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_6362_EXT_IRQ0; ++ ext_irqs[1] = BCM_6362_EXT_IRQ1; ++ ext_irqs[2] = BCM_6362_EXT_IRQ2; ++ ext_irqs[3] = BCM_6362_EXT_IRQ3; ++ ext_shift = 4; + break; + case BCM6368_CPU_ID: +- irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); +- irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); +- irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1); +- irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1); +- irq_bits = 64; ++ periph_bases[0] += PERF_IRQMASK_6368_REG(0); ++ periph_bases[1] += PERF_IRQMASK_6368_REG(1); ++ periph_irq_count = 2; ++ periph_width = 2; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368; ++ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368; + ext_irq_count = 6; +- is_ext_irq_cascaded = 1; +- ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; +- ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; +- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; +- ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; ++ ext_irqs[0] = BCM_6368_EXT_IRQ0; ++ ext_irqs[1] = BCM_6368_EXT_IRQ1; ++ ext_irqs[2] = BCM_6368_EXT_IRQ2; ++ ext_irqs[3] = BCM_6368_EXT_IRQ3; ++ ext_irqs[4] = BCM_6368_EXT_IRQ4; ++ ext_irqs[5] = BCM_6368_EXT_IRQ5; ++ ext_shift = 4; + break; + default: + BUG(); + } + +- if (irq_bits == 32) { +- dispatch_internal = __dispatch_internal_32; +- internal_irq_mask = __internal_irq_mask_32; +- internal_irq_unmask = __internal_irq_unmask_32; +- } else { +- dispatch_internal = __dispatch_internal_64; +- internal_irq_mask = __internal_irq_mask_64; +- internal_irq_unmask = __internal_irq_unmask_64; +- } +-} +- +-void __init arch_init_irq(void) +-{ +- int i; +- +- bcm63xx_init_irq(); + mips_cpu_irq_init(); +- for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) +- irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, +- handle_level_irq); +- +- for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i) +- irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, +- handle_edge_irq); +- +- if (!is_ext_irq_cascaded) { +- for (i = 3; i < 3 + ext_irq_count; ++i) +- setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); +- } +- +- setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); +-#ifdef CONFIG_SMP +- if (is_ext_irq_cascaded) { +- setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); +- bcm63xx_internal_irq_chip.irq_set_affinity = +- bcm63xx_internal_set_affinity; +- +- cpumask_clear(irq_default_affinity); +- cpumask_set_cpu(smp_processor_id(), irq_default_affinity); +- } +-#endif ++ bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases, ++ periph_width); ++ bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift); ++ if (ext_irq_count > 4) ++ bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1], ++ ext_shift); + } diff --git a/target/linux/brcm63xx/patches-4.1/323-MIPS-BCM63XX-wire-up-BCM6358-s-external-interrupts-4.patch b/target/linux/brcm63xx/patches-4.1/323-MIPS-BCM63XX-wire-up-BCM6358-s-external-interrupts-4.patch new file mode 100644 index 0000000..0796bb5 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/323-MIPS-BCM63XX-wire-up-BCM6358-s-external-interrupts-4.patch @@ -0,0 +1,57 @@ +From 4fd286c3e5a5bebab0391cf1937695b3ed6721a3 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Nov 2014 20:20:30 +0100 +Subject: [PATCH 4/5] MIPS: BCM63XX: wire up BCM6358's external interrupts 4 + and 5 + +Due to the external interrupts being non consecutive, the previous +implementation did not support them. Now that we treat both registers +as separate irq controllers, there is no such limitation anymore and +we can expose them for drivers to use. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/irq.c | 5 ++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 ++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 1 + + 3 files changed, 7 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -109,11 +109,14 @@ void __init arch_init_irq(void) + periph_width = 1; + + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358; +- ext_irq_count = 4; ++ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6358; ++ ext_irq_count = 6; + ext_irqs[0] = BCM_6358_EXT_IRQ0; + ext_irqs[1] = BCM_6358_EXT_IRQ1; + ext_irqs[2] = BCM_6358_EXT_IRQ2; + ext_irqs[3] = BCM_6358_EXT_IRQ3; ++ ext_irqs[4] = BCM_6358_EXT_IRQ4; ++ ext_irqs[5] = BCM_6358_EXT_IRQ5; + ext_shift = 4; + break; + case BCM6362_CPU_ID: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -895,6 +895,8 @@ enum bcm63xx_irq { + #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) + #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) + #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) ++#define BCM_6358_EXT_IRQ4 (IRQ_INTERNAL_BASE + 20) ++#define BCM_6358_EXT_IRQ5 (IRQ_INTERNAL_BASE + 21) + + /* + * 6362 irqs +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -243,6 +243,7 @@ + #define PERF_EXTIRQ_CFG_REG_6362 0x18 + #define PERF_EXTIRQ_CFG_REG_6368 0x18 + ++#define PERF_EXTIRQ_CFG_REG2_6358 0x1c + #define PERF_EXTIRQ_CFG_REG2_6368 0x1c + + /* for 6348 only */ diff --git a/target/linux/brcm63xx/patches-4.1/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch b/target/linux/brcm63xx/patches-4.1/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch new file mode 100644 index 0000000..661abf6 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch @@ -0,0 +1,77 @@ +From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:08:36 +0100 +Subject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper + +--- + arch/mips/bcm63xx/cpu.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++ + 2 files changed, 28 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs); + u16 bcm63xx_cpu_id __read_mostly; + EXPORT_SYMBOL(bcm63xx_cpu_id); + ++static u32 bcm63xx_cpu_variant __read_mostly; ++ + static u8 bcm63xx_cpu_rev; + static unsigned int bcm63xx_cpu_freq; + static unsigned int bcm63xx_memory_size; +@@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = { + + }; + ++u32 bcm63xx_get_cpu_variant(void) ++{ ++ return bcm63xx_cpu_variant; ++} ++ ++EXPORT_SYMBOL(bcm63xx_get_cpu_variant); ++ + u8 bcm63xx_get_cpu_rev(void) + { + return bcm63xx_cpu_rev; +@@ -333,6 +342,7 @@ void __init bcm63xx_cpu_init(void) + /* read out CPU type */ + tmp = bcm_readl(chipid_reg); + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; ++ bcm63xx_cpu_variant = bcm63xx_cpu_id; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; + + switch (bcm63xx_cpu_id) { +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -19,6 +19,7 @@ + #define BCM6368_CPU_ID 0x6368 + + void __init bcm63xx_cpu_init(void); ++u32 bcm63xx_get_cpu_variant(void); + u8 bcm63xx_get_cpu_rev(void); + unsigned int bcm63xx_get_cpu_freq(void); + +@@ -82,6 +83,23 @@ static inline u16 __pure bcm63xx_get_cpu + #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) + #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) + ++#define BCMCPU_VARIANT_IS_3368() \ ++ (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6328() \ ++ (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) ++#define BCMCPU_VARIANT_IS_6338() \ ++ (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) ++#define BCMCPU_VARIANT_IS_6345() \ ++ (bcm63xx_get_cpu_variant() == BCM6345_CPU_ID) ++#define BCMCPU_VARIANT_IS_6348() \ ++ (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID) ++#define BCMCPU_VARIANT_IS_6358() \ ++ (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID) ++#define BCMCPU_VARIANT_IS_6362() \ ++ (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) ++#define BCMCPU_VARIANT_IS_6368() \ ++ (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) ++ + /* + * While registers sets are (mostly) the same across 63xx CPU, base + * address of these sets do change. diff --git a/target/linux/brcm63xx/patches-4.1/331-MIPS-BCM63XX-define-variant-id-field.patch b/target/linux/brcm63xx/patches-4.1/331-MIPS-BCM63XX-define-variant-id-field.patch new file mode 100644 index 0000000..2e21c65 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/331-MIPS-BCM63XX-define-variant-id-field.patch @@ -0,0 +1,23 @@ +From 3bd8e2535265f06f79ed9c0ad788405441e091dc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:22:41 +0100 +Subject: [PATCH 21/45] MIPS: BCM63XX: define variant id field + +Some SoC have a variant id field in the chip id register. + +Signed-off-by: Jonas Gorski +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -9,6 +9,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_VARID_SHIFT 12 ++#define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 + #define REV_REVID_MASK (0xff << REV_REVID_SHIFT) + diff --git a/target/linux/brcm63xx/patches-4.1/332-MIPS-BCM63XX-detect-BCM6328-variants.patch b/target/linux/brcm63xx/patches-4.1/332-MIPS-BCM63XX-detect-BCM6328-variants.patch new file mode 100644 index 0000000..faa002e --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/332-MIPS-BCM63XX-detect-BCM6328-variants.patch @@ -0,0 +1,68 @@ +From d59120f23279ef62a48d9f94847254b061d0a8b6 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:30:59 +0100 +Subject: [PATCH 22/45] MIPS: BCM63XX: detect BCM6328 variants + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/cpu.c | 10 ++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++++-- + 2 files changed, 16 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -305,6 +305,7 @@ void __init bcm63xx_cpu_init(void) + unsigned int tmp; + unsigned int cpu = smp_processor_id(); + u32 chipid_reg; ++ u8 __maybe_unused varid = 0; + + /* soc registers location depends on cpu type */ + chipid_reg = 0; +@@ -344,6 +345,7 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; + bcm63xx_cpu_variant = bcm63xx_cpu_id; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; ++ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; + + switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: +@@ -353,6 +355,14 @@ void __init bcm63xx_cpu_init(void) + case BCM6328_CPU_ID: + bcm63xx_regs_base = bcm6328_regs_base; + bcm63xx_irqs = bcm6328_irqs; ++ ++ if (varid == 1) ++ bcm63xx_cpu_variant = BCM63281_CPU_ID; ++ else if (varid == 3) ++ bcm63xx_cpu_variant = BCM63283_CPU_ID; ++ else ++ pr_warn("unknown BCM6328 variant: %x\n", varid); ++ + break; + case BCM6338_CPU_ID: + bcm63xx_regs_base = bcm6338_regs_base; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -11,6 +11,8 @@ + */ + #define BCM3368_CPU_ID 0x3368 + #define BCM6328_CPU_ID 0x6328 ++#define BCM63281_CPU_ID 0x63281 ++#define BCM63283_CPU_ID 0x63283 + #define BCM6338_CPU_ID 0x6338 + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 +@@ -85,8 +87,10 @@ static inline u16 __pure bcm63xx_get_cpu + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) +-#define BCMCPU_VARIANT_IS_6328() \ +- (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID) ++#define BCMCPU_VARIANT_IS_63281() \ ++ (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) ++#define BCMCPU_VARIANT_IS_63283() \ ++ (bcm63xx_get_cpu_variant() == BCM63283_CPU_ID) + #define BCMCPU_VARIANT_IS_6338() \ + (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID) + #define BCMCPU_VARIANT_IS_6345() \ diff --git a/target/linux/brcm63xx/patches-4.1/333-MIPS-BCM63XX-detect-BCM6362-variants.patch b/target/linux/brcm63xx/patches-4.1/333-MIPS-BCM63XX-detect-BCM6362-variants.patch new file mode 100644 index 0000000..62ce12e --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/333-MIPS-BCM63XX-detect-BCM6362-variants.patch @@ -0,0 +1,46 @@ +From 04458c3db8eb79da21ecde40ab36a1dde52bef06 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:33:28 +0100 +Subject: [PATCH 23/45] MIPS: BCM63XX: detect BCM6362 variants + +--- + arch/mips/bcm63xx/cpu.c | 8 ++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++ + 2 files changed, 11 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -383,6 +383,14 @@ void __init bcm63xx_cpu_init(void) + case BCM6362_CPU_ID: + bcm63xx_regs_base = bcm6362_regs_base; + bcm63xx_irqs = bcm6362_irqs; ++ ++ if (varid == 1) ++ bcm63xx_cpu_variant = BCM6362_CPU_ID; ++ else if (varid == 2) ++ bcm63xx_cpu_variant = BCM6361_CPU_ID; ++ else ++ pr_warn("unknown BCM6362 variant: %x\n", varid); ++ + break; + case BCM6368_CPU_ID: + bcm63xx_regs_base = bcm6368_regs_base; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -17,6 +17,7 @@ + #define BCM6345_CPU_ID 0x6345 + #define BCM6348_CPU_ID 0x6348 + #define BCM6358_CPU_ID 0x6358 ++#define BCM6361_CPU_ID 0x6361 + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 + +@@ -99,6 +100,8 @@ static inline u16 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID) + #define BCMCPU_VARIANT_IS_6358() \ + (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID) ++#define BCMCPU_VARIANT_IS_6361() \ ++ (bcm63xx_get_cpu_variant() == BCM6361_CPU_ID) + #define BCMCPU_VARIANT_IS_6362() \ + (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) + #define BCMCPU_VARIANT_IS_6368() \ diff --git a/target/linux/brcm63xx/patches-4.1/334-MIPS-BCM63XX-detect-BCM6368-variants.patch b/target/linux/brcm63xx/patches-4.1/334-MIPS-BCM63XX-detect-BCM6368-variants.patch new file mode 100644 index 0000000..a993e23 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/334-MIPS-BCM63XX-detect-BCM6368-variants.patch @@ -0,0 +1,48 @@ +From 825cc67e56b5e624a05f6850a86d91508b786848 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:36:56 +0100 +Subject: [PATCH 24/44] MIPS: BCM63XX: detect BCM6368 variants + +The DSL-less BCM6368 variant BCM6367 uses a different chip id. Apart +from missing DSL, there is no difference to BCM6368, so treat it such. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/cpu.c | 4 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++ + 2 files changed, 7 insertions(+) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -393,8 +393,12 @@ void __init bcm63xx_cpu_init(void) + + break; + case BCM6368_CPU_ID: ++ case BCM6369_CPU_ID: + bcm63xx_regs_base = bcm6368_regs_base; + bcm63xx_irqs = bcm6368_irqs; ++ ++ /* BCM6369 is a BCM6368 without xDSL, so treat it the same */ ++ bcm63xx_cpu_id = BCM6368_CPU_ID; + break; + default: + panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -20,6 +20,7 @@ + #define BCM6361_CPU_ID 0x6361 + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 ++#define BCM6369_CPU_ID 0x6369 + + void __init bcm63xx_cpu_init(void); + u32 bcm63xx_get_cpu_variant(void); +@@ -106,6 +107,8 @@ static inline u16 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID) + #define BCMCPU_VARIANT_IS_6368() \ + (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6369() \ ++ (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID) + + /* + * While registers sets are (mostly) the same across 63xx CPU, base diff --git a/target/linux/brcm63xx/patches-4.1/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch b/target/linux/brcm63xx/patches-4.1/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch new file mode 100644 index 0000000..3230add --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch @@ -0,0 +1,20 @@ +From f67f8134b4537c8bbafe7e1975edfe808b813997 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 03:05:54 +0100 +Subject: [PATCH 45/53] MIPS: BCM63XX: fix PCIe memory window size + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -41,7 +41,7 @@ + BCM_CB_MEM_SIZE - 1) + + #define BCM_PCIE_MEM_BASE_PA 0x10f00000 +-#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define BCM_PCIE_MEM_SIZE (1 * 1024 * 1024) + #define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ + BCM_PCIE_MEM_SIZE - 1) + diff --git a/target/linux/brcm63xx/patches-4.1/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch b/target/linux/brcm63xx/patches-4.1/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch new file mode 100644 index 0000000..d6eb54d --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch @@ -0,0 +1,70 @@ +From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 03:13:06 +0100 +Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows + +Different SoCs use different memory windows (and sizes), so don't +hardcode it. +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 8 ++++---- + arch/mips/pci/pci-bcm63xx.c | 15 ++++++++++----- + 2 files changed, 14 insertions(+), 9 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -40,10 +40,10 @@ + #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ + BCM_CB_MEM_SIZE - 1) + +-#define BCM_PCIE_MEM_BASE_PA 0x10f00000 +-#define BCM_PCIE_MEM_SIZE (1 * 1024 * 1024) +-#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ +- BCM_PCIE_MEM_SIZE - 1) ++#define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000 ++#define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ ++ BCM_PCIE_MEM_SIZE_6328 - 1) + + /* + * Internal registers are accessed through KSEG3 +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control + + static struct resource bcm_pcie_mem_resource = { + .name = "bcm63xx PCIe memory space", +- .start = BCM_PCIE_MEM_BASE_PA, +- .end = BCM_PCIE_MEM_END_PA, ++ .start = 0, ++ .end = 0, + .flags = IORESOURCE_MEM, + }; + +@@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie( + bcm_pcie_writel(val, PCIE_CONFIG2_REG); + + /* set bar0 to little endian */ +- val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; +- val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; ++ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; ++ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; + val |= BASEMASK_REMAP_EN; + bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); + +- val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; ++ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; + bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); + + register_pci_controller(&bcm63xx_pcie_controller); +@@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void) + if (!bcm63xx_pci_enabled) + return -ENODEV; + ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; ++ } ++ + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: diff --git a/target/linux/brcm63xx/patches-4.1/337-MIPS-BCM63XX-widen-cpuid-field.patch b/target/linux/brcm63xx/patches-4.1/337-MIPS-BCM63XX-widen-cpuid-field.patch new file mode 100644 index 0000000..0ead82e --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/337-MIPS-BCM63XX-widen-cpuid-field.patch @@ -0,0 +1,56 @@ +From f1477f6e3551fd6beecfee5368fed1325dcd421f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 14:54:51 +0100 +Subject: [PATCH 47/53] MIPS: BCM63XX: widen cpuid field + +--- + arch/mips/bcm63xx/cpu.c | 2 +- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -24,7 +24,7 @@ EXPORT_SYMBOL(bcm63xx_regs_base); + const int *bcm63xx_irqs; + EXPORT_SYMBOL(bcm63xx_irqs); + +-u16 bcm63xx_cpu_id __read_mostly; ++u32 bcm63xx_cpu_id __read_mostly; + EXPORT_SYMBOL(bcm63xx_cpu_id); + + static u32 bcm63xx_cpu_variant __read_mostly; +@@ -127,7 +127,7 @@ unsigned int bcm63xx_get_memory_size(voi + + static unsigned int detect_cpu_clock(void) + { +- u16 cpu_id = bcm63xx_get_cpu_id(); ++ u32 cpu_id = bcm63xx_get_cpu_id(); + + switch (cpu_id) { + case BCM3368_CPU_ID: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -27,7 +27,7 @@ u32 bcm63xx_get_cpu_variant(void); + u8 bcm63xx_get_cpu_rev(void); + unsigned int bcm63xx_get_cpu_freq(void); + +-static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id) ++static inline u32 __pure __bcm63xx_get_cpu_id(const u32 cpu_id) + { + switch (cpu_id) { + #ifdef CONFIG_BCM63XX_CPU_3368 +@@ -69,11 +69,11 @@ static inline u16 __pure __bcm63xx_get_c + return cpu_id; + } + +-extern u16 bcm63xx_cpu_id; ++extern u32 bcm63xx_cpu_id; + +-static inline u16 __pure bcm63xx_get_cpu_id(void) ++static inline u32 __pure bcm63xx_get_cpu_id(void) + { +- const u16 cpu_id = bcm63xx_cpu_id; ++ const u32 cpu_id = bcm63xx_cpu_id; + + return __bcm63xx_get_cpu_id(cpu_id); + } diff --git a/target/linux/brcm63xx/patches-4.1/338-MIPS-BCM63XX-increase-number-of-IRQs.patch b/target/linux/brcm63xx/patches-4.1/338-MIPS-BCM63XX-increase-number-of-IRQs.patch new file mode 100644 index 0000000..9132e42 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/338-MIPS-BCM63XX-increase-number-of-IRQs.patch @@ -0,0 +1,39 @@ +From 6f5658c845cf1f79213b1d20423a04967259fdaa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 15 Dec 2013 20:46:26 +0100 +Subject: [PATCH 48/53] MIPS: BCM63XX: increase number of IRQs + +Newer SoCs have 128 bit wide irq registers, thus 128 available internal +interupts. +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h | 4 +++- + arch/mips/include/asm/mach-bcm63xx/irq.h | 2 +- + 2 files changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h +@@ -1,10 +1,12 @@ + #ifndef BCM63XX_IRQ_H_ + #define BCM63XX_IRQ_H_ + ++#include + #include + + #define IRQ_INTERNAL_BASE 8 +-#define IRQ_EXTERNAL_BASE 100 ++#define NR_INTERNAL_IRQS 128 ++#define IRQ_EXTERNAL_BASE (IRQ_INTERNAL_BASE + NR_INTERNAL_IRQS) + #define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0) + #define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1) + #define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2) +--- a/arch/mips/include/asm/mach-bcm63xx/irq.h ++++ b/arch/mips/include/asm/mach-bcm63xx/irq.h +@@ -1,7 +1,7 @@ + #ifndef __ASM_MACH_BCM63XX_IRQ_H + #define __ASM_MACH_BCM63XX_IRQ_H + +-#define NR_IRQS 128 ++#define NR_IRQS 256 + #define MIPS_CPU_IRQ_BASE 0 + + #endif diff --git a/target/linux/brcm63xx/patches-4.1/339-MIPS-BCM63XX-add-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-4.1/339-MIPS-BCM63XX-add-support-for-BCM63268.patch new file mode 100644 index 0000000..277aa70 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/339-MIPS-BCM63XX-add-support-for-BCM63268.patch @@ -0,0 +1,735 @@ +From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 7 Dec 2013 17:14:17 +0100 +Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268 + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/Kconfig | 5 + + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/clk.c | 25 ++++- + arch/mips/bcm63xx/cpu.c | 59 +++++++++- + arch/mips/bcm63xx/dev-flash.c | 6 + + arch/mips/bcm63xx/dev-spi.c | 4 +- + arch/mips/bcm63xx/irq.c | 20 +++- + arch/mips/bcm63xx/reset.c | 21 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 + + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++ + arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + + 12 files changed, 342 insertions(+), 12 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -60,6 +60,11 @@ config BCM63XX_CPU_6368 + select HW_HAS_PCI + select BCM63XX_OHCI + select BCM63XX_EHCI ++ ++config BCM63XX_CPU_63268 ++ bool "support 63268 CPU" ++ select SYS_HAS_CPU_BMIPS4350 ++ select HW_HAS_PCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -712,7 +712,7 @@ void __init board_prom_init(void) + /* read base address of boot chip select (0) + * 6328/6362 do not have MPI but boot from a fixed address + */ +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { + val = 0x18000000; + } else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -133,6 +133,8 @@ static void enetsw_set(struct clk *clk, + CKCTL_6368_SWPKT_USB_EN | + CKCTL_6368_SWPKT_SAR_EN, + enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable); + else + return; + +@@ -177,6 +179,8 @@ static void usbh_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); + else + return; + +@@ -199,6 +203,8 @@ static void usbd_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); + else if (BCMCPU_IS_6368()) + bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_USBD_EN, enable); + else + return; + +@@ -225,9 +231,13 @@ static void spi_set(struct clk *clk, int + mask = CKCTL_6358_SPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_SPI_EN; +- else +- /* BCMCPU_IS_6368 */ ++ else if (BCMCPU_IS_6368()) + mask = CKCTL_6368_SPI_EN; ++ else if (BCMCPU_IS_63268()) ++ mask = CKCTL_63268_SPI_EN; ++ else ++ return; ++ + bcm_hwclock_set(mask, enable); + } + +@@ -246,6 +256,8 @@ static void hsspi_set(struct clk *clk, i + mask = CKCTL_6328_HSSPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_HSSPI_EN; ++ else if (BCMCPU_IS_63268()) ++ mask = CKCTL_63268_HSSPI_EN; + else + return; + +@@ -307,6 +319,8 @@ static void pcie_set(struct clk *clk, in + bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); + else if (BCMCPU_IS_6362()) + bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); ++ else if (BCMCPU_IS_63268()) ++ bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable); + } + + static struct clk clk_pcie = { +@@ -386,9 +400,11 @@ struct clk *clk_get(struct device *dev, + return &clk_periph; + if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm")) + return &clk_pcm; +- if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) ++ if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) && ++ !strcmp(id, "ipsec")) + return &clk_ipsec; +- if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie")) ++ if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && ++ !strcmp(id, "pcie")) + return &clk_pcie; + return ERR_PTR(-ENOENT); + } +@@ -411,6 +427,7 @@ static int __init bcm63xx_clk_init(void) + clk_hsspi.rate = HSSPI_PLL_HZ_6328; + break; + case BCM6362_CPU_ID: ++ case BCM63268_CPU_ID: + clk_hsspi.rate = HSSPI_PLL_HZ_6362; + break; + } +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = { + + }; + ++static const unsigned long bcm63268_regs_base[] = { ++ __GEN_CPU_REGS_TABLE(63268) ++}; ++ ++static const int bcm63268_irqs[] = { ++ __GEN_CPU_IRQ_TABLE(63268) ++ ++}; ++ + u32 bcm63xx_get_cpu_variant(void) + { + return bcm63xx_cpu_variant; +@@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi + + return (((64 * 1000000) / p1) * p2 * ndiv) / m1; + } ++ case BCM63268_CPU_ID: ++ { ++ unsigned int tmp, mips_pll_fcvo; ++ ++ tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >> ++ STRAPBUS_63268_FCVO_SHIFT; ++ switch (mips_pll_fcvo) { ++ case 0x3: ++ case 0xe: ++ return 320000000; ++ case 0xa: ++ return 333000000; ++ case 0x2: ++ case 0xb: ++ case 0xf: ++ return 400000000; ++ default: ++ return 0; ++ } ++ } + + default: + panic("Failed to detect clock for CPU with id=%04X\n", cpu_id); +@@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) + return bcm_ddr_readl(DDR_CSEND_REG) << 24; + + if (BCMCPU_IS_6345()) { +@@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void) + unsigned int tmp; + unsigned int cpu = smp_processor_id(); + u32 chipid_reg; ++ bool long_chipid = false; + u8 __maybe_unused varid = 0; + + /* soc registers location depends on cpu type */ +@@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void) + case 0x10: + chipid_reg = BCM_6345_PERF_BASE; + break; ++ case 0x80: ++ long_chipid = true; ++ /* fall-through */ + default: + chipid_reg = BCM_6368_PERF_BASE; + break; +@@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void) + break; + } + ++ + /* + * really early to panic, but delaying panic would not help since we + * will never get any working console +@@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void) + + /* read out CPU type */ + tmp = bcm_readl(chipid_reg); +- bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; +- bcm63xx_cpu_variant = bcm63xx_cpu_id; ++ ++ if (long_chipid) { ++ bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK; ++ bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT; ++ } else { ++ bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; ++ varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; ++ } ++ + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; +- varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; ++ bcm63xx_cpu_variant = bcm63xx_cpu_id; + + switch (bcm63xx_cpu_id) { + case BCM3368_CPU_ID: +@@ -400,6 +442,15 @@ void __init bcm63xx_cpu_init(void) + /* BCM6369 is a BCM6368 without xDSL, so treat it the same */ + bcm63xx_cpu_id = BCM6368_CPU_ID; + break; ++ case BCM63168_CPU_ID: ++ case BCM63169_CPU_ID: ++ case BCM63268_CPU_ID: ++ case BCM63269_CPU_ID: ++ bcm63xx_regs_base = bcm63268_regs_base; ++ bcm63xx_irqs = bcm63268_irqs; ++ ++ bcm63xx_cpu_id = BCM63268_CPU_ID; ++ break; + default: + panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); + break; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -94,6 +94,12 @@ static int __init bcm63xx_detect_flash_t + case STRAPBUS_6368_BOOT_SEL_PARALLEL: + return BCM63XX_FLASH_TYPE_PARALLEL; + } ++ case BCM63268_CPU_ID: ++ val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) ++ return BCM63XX_FLASH_TYPE_SERIAL; ++ else ++ return BCM63XX_FLASH_TYPE_NAND; + default: + return -EINVAL; + } +--- a/arch/mips/bcm63xx/dev-spi.c ++++ b/arch/mips/bcm63xx/dev-spi.c +@@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init + if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) + bcm63xx_regs_spi = bcm6348_regs_spi; + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || +- BCMCPU_IS_6362() || BCMCPU_IS_6368()) ++ BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) + bcm63xx_regs_spi = bcm6358_regs_spi; + } + +@@ -85,7 +85,7 @@ int __init bcm63xx_spi_register(void) + } + + if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || +- BCMCPU_IS_6368()) { ++ BCMCPU_IS_6368() || BCMCPU_IS_63268()) { + spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; + spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; + spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT; +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -150,6 +150,20 @@ void __init arch_init_irq(void) + ext_irqs[5] = BCM_6368_EXT_IRQ5; + ext_shift = 4; + break; ++ case BCM63268_CPU_ID: ++ periph_bases[0] += PERF_IRQMASK_63268_REG(0); ++ periph_bases[1] += PERF_IRQMASK_63268_REG(1); ++ periph_irq_count = 2; ++ periph_width = 4; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_63268_EXT_IRQ0; ++ ext_irqs[1] = BCM_63268_EXT_IRQ1; ++ ext_irqs[2] = BCM_63268_EXT_IRQ2; ++ ext_irqs[3] = BCM_63268_EXT_IRQ3; ++ ext_shift = 4; ++ break; + default: + BUG(); + } +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -125,6 +125,20 @@ + #define BCM6368_RESET_PCIE 0 + #define BCM6368_RESET_PCIE_EXT 0 + ++#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK ++#define BCM63268_RESET_ENET 0 ++#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK ++#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK ++#define BCM63268_RESET_DSL 0 ++#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK ++#define BCM63268_RESET_EPHY 0 ++#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK ++#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK ++#define BCM63268_RESET_MPI 0 ++#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ ++ SOFTRESET_63268_PCIE_CORE_MASK) ++#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK ++ + /* + * core reset bits + */ +@@ -156,6 +170,10 @@ static const u32 bcm6368_reset_bits[] = + __GEN_RESET_BITS_TABLE(6368) + }; + ++static const u32 bcm63268_reset_bits[] = { ++ __GEN_RESET_BITS_TABLE(63268) ++}; ++ + const u32 *bcm63xx_reset_bits; + static int reset_reg; + +@@ -182,6 +200,9 @@ static int __init bcm63xx_reset_bits_ini + } else if (BCMCPU_IS_6368()) { + reset_reg = PERF_SOFTRESET_6368_REG; + bcm63xx_reset_bits = bcm6368_reset_bits; ++ } else if (BCMCPU_IS_63268()) { ++ reset_reg = PERF_SOFTRESET_63268_REG; ++ bcm63xx_reset_bits = bcm63268_reset_bits; + } + + return 0; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -21,6 +21,10 @@ + #define BCM6362_CPU_ID 0x6362 + #define BCM6368_CPU_ID 0x6368 + #define BCM6369_CPU_ID 0x6369 ++#define BCM63168_CPU_ID 0x63168 ++#define BCM63169_CPU_ID 0x63169 ++#define BCM63268_CPU_ID 0x63268 ++#define BCM63269_CPU_ID 0x63269 + + void __init bcm63xx_cpu_init(void); + u32 bcm63xx_get_cpu_variant(void); +@@ -61,6 +65,10 @@ static inline u32 __pure __bcm63xx_get_c + #ifdef CONFIG_BCM63XX_CPU_6368 + case BCM6368_CPU_ID: + #endif ++ ++#ifdef CONFIG_BCM63XX_CPU_63268 ++ case BCM63268_CPU_ID: ++#endif + break; + default: + unreachable(); +@@ -86,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu + #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) + #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) + #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) ++#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID) + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) +@@ -109,6 +118,14 @@ static inline u32 __pure bcm63xx_get_cpu + (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) + #define BCMCPU_VARIANT_IS_6369() \ + (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID) ++#define BCMCPU_VARIANT_IS_63168() \ ++ (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID) ++#define BCMCPU_VARIANT_IS_63169() \ ++ (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID) ++#define BCMCPU_VARIANT_IS_63268() \ ++ (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID) ++#define BCMCPU_VARIANT_IS_63269() \ ++ (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID) + + /* + * While registers sets are (mostly) the same across 63xx CPU, base +@@ -573,6 +590,52 @@ enum bcm63xx_regs_set { + #define BCM_6368_RNG_BASE (0xb0004180) + #define BCM_6368_MISC_BASE (0xdeadbeef) + ++/* ++ * 63268 register sets base address ++ */ ++#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef) ++#define BCM_63268_PERF_BASE (0xb0000000) ++#define BCM_63268_TIMER_BASE (0xb0000080) ++#define BCM_63268_WDT_BASE (0xb000009c) ++#define BCM_63268_UART0_BASE (0xb0000180) ++#define BCM_63268_UART1_BASE (0xb00001a0) ++#define BCM_63268_GPIO_BASE (0xb00000c0) ++#define BCM_63268_SPI_BASE (0xb0000800) ++#define BCM_63268_HSSPI_BASE (0xb0001000) ++#define BCM_63268_UDC0_BASE (0xdeadbeef) ++#define BCM_63268_USBDMA_BASE (0xb000c800) ++#define BCM_63268_OHCI0_BASE (0xb0002600) ++#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef) ++#define BCM_63268_USBH_PRIV_BASE (0xb0002700) ++#define BCM_63268_USBD_BASE (0xb0002400) ++#define BCM_63268_MPI_BASE (0xdeadbeef) ++#define BCM_63268_PCMCIA_BASE (0xdeadbeef) ++#define BCM_63268_PCIE_BASE (0xb06e0000) ++#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef) ++#define BCM_63268_DSL_BASE (0xdeadbeef) ++#define BCM_63268_UBUS_BASE (0xdeadbeef) ++#define BCM_63268_ENET0_BASE (0xdeadbeef) ++#define BCM_63268_ENET1_BASE (0xdeadbeef) ++#define BCM_63268_ENETDMA_BASE (0xb000d800) ++#define BCM_63268_ENETDMAC_BASE (0xb000da00) ++#define BCM_63268_ENETDMAS_BASE (0xb000dc00) ++#define BCM_63268_ENETSW_BASE (0xb0700000) ++#define BCM_63268_EHCI0_BASE (0xb0002500) ++#define BCM_63268_SDRAM_BASE (0xdeadbeef) ++#define BCM_63268_MEMC_BASE (0xdeadbeef) ++#define BCM_63268_DDR_BASE (0xb0003000) ++#define BCM_63268_M2M_BASE (0xdeadbeef) ++#define BCM_63268_ATM_BASE (0xdeadbeef) ++#define BCM_63268_XTM_BASE (0xb0007000) ++#define BCM_63268_XTMDMA_BASE (0xb000b800) ++#define BCM_63268_XTMDMAC_BASE (0xdeadbeef) ++#define BCM_63268_XTMDMAS_BASE (0xdeadbeef) ++#define BCM_63268_PCM_BASE (0xb000b000) ++#define BCM_63268_PCMDMA_BASE (0xb000b800) ++#define BCM_63268_PCMDMAC_BASE (0xdeadbeef) ++#define BCM_63268_PCMDMAS_BASE (0xdeadbeef) ++#define BCM_63268_RNG_BASE (0xdeadbeef) ++#define BCM_63268_MISC_BASE (0xb0001800) + + extern const unsigned long *bcm63xx_regs_base; + +@@ -1041,6 +1104,73 @@ enum bcm63xx_irq { + #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) + #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) + ++/* ++ * 63268 irqs ++ */ ++#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) ++#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32) ++ ++#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) ++#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16) ++#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5) ++#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2) ++#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23) ++#define BCM_63268_UDC0_IRQ 0 ++#define BCM_63268_ENET0_IRQ 0 ++#define BCM_63268_ENET1_IRQ 0 ++#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13) ++#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6) ++#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) ++#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11) ++#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19) ++#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4) ++#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20) ++#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5) ++#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21) ++#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6) ++#define BCM_63268_PCMCIA_IRQ 0 ++#define BCM_63268_ENET0_RXDMA_IRQ 0 ++#define BCM_63268_ENET0_TXDMA_IRQ 0 ++#define BCM_63268_ENET1_RXDMA_IRQ 0 ++#define BCM_63268_ENET1_TXDMA_IRQ 0 ++#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8) ++#define BCM_63268_ATM_IRQ 0 ++#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1) ++#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2) ++#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3) ++#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4) ++#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0) ++#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1) ++#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2) ++#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3) ++#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17) ++#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) ++ ++#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20) ++#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3) ++#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) ++#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) ++#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18) ++#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13) ++#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15) ++#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) ++#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) ++#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) ++#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) ++#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22) ++#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7) ++#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24) ++#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25) ++#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10) ++#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11) ++#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0) ++#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1) ++#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12) ++#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13) ++#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14) ++#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15) ++ + extern const int *bcm63xx_irqs; + + #define __GEN_CPU_IRQ_TABLE(__cpu) \ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -22,6 +22,8 @@ static inline unsigned long bcm63xx_gpio + return 48; + case BCM6368_CPU_ID: + return 38; ++ case BCM63268_CPU_ID: ++ return 52; + case BCM6348_CPU_ID: + default: + return 37; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -9,6 +9,8 @@ + #define PERF_REV_REG 0x0 + #define REV_CHIPID_SHIFT 16 + #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) ++#define REV_LONG_CHIPID_SHIFT 12 ++#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) + #define REV_VARID_SHIFT 12 + #define REV_VARID_MASK (0xf << REV_VARID_SHIFT) + #define REV_REVID_SHIFT 0 +@@ -211,6 +213,52 @@ + CKCTL_6368_NAND_EN | \ + CKCTL_6368_IPSEC_EN) + ++#define CKCTL_63268_DISABLE_GLESS (1 << 0) ++#define CKCTL_63268_VDSL_QPROC_EN (1 << 1) ++#define CKCTL_63268_VDSL_AFE_EN (1 << 2) ++#define CKCTL_63268_VDSL_EN (1 << 3) ++#define CKCTL_63268_MIPS_EN (1 << 4) ++#define CKCTL_63268_WLAN_OCP_EN (1 << 5) ++#define CKCTL_63268_DECT_EN (1 << 6) ++#define CKCTL_63268_FAP0_EN (1 << 7) ++#define CKCTL_63268_FAP1_EN (1 << 8) ++#define CKCTL_63268_SAR_EN (1 << 9) ++#define CKCTL_63268_ROBOSW_EN (1 << 10) ++#define CKCTL_63268_PCM_EN (1 << 11) ++#define CKCTL_63268_USBD_EN (1 << 12) ++#define CKCTL_63268_USBH_EN (1 << 13) ++#define CKCTL_63268_IPSEC_EN (1 << 14) ++#define CKCTL_63268_SPI_EN (1 << 15) ++#define CKCTL_63268_HSSPI_EN (1 << 16) ++#define CKCTL_63268_PCIE_EN (1 << 17) ++#define CKCTL_63268_PHYMIPS_EN (1 << 18) ++#define CKCTL_63268_GMAC_EN (1 << 19) ++#define CKCTL_63268_NAND_EN (1 << 20) ++#define CKCTL_63268_TBUS_EN (1 << 27) ++#define CKCTL_63268_ROBOSW250_EN (1 << 31) ++ ++#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \ ++ CKCTL_63268_VDSL_AFE_EN | \ ++ CKCTL_63268_VDSL_EN | \ ++ CKCTL_63268_WLAN_OCP_EN | \ ++ CKCTL_63268_DECT_EN | \ ++ CKCTL_63268_FAP0_EN | \ ++ CKCTL_63268_FAP1_EN | \ ++ CKCTL_63268_SAR_EN | \ ++ CKCTL_63268_ROBOSW_EN | \ ++ CKCTL_63268_PCM_EN | \ ++ CKCTL_63268_USBD_EN | \ ++ CKCTL_63268_USBH_EN | \ ++ CKCTL_63268_IPSEC_EN | \ ++ CKCTL_63268_SPI_EN | \ ++ CKCTL_63268_HSSPI_EN | \ ++ CKCTL_63268_PCIE_EN | \ ++ CKCTL_63268_PHYMIPS_EN | \ ++ CKCTL_63268_GMAC_EN | \ ++ CKCTL_63268_NAND_EN | \ ++ CKCTL_63268_TBUS_EN | \ ++ CKCTL_63268_ROBOSW250_EN) ++ + /* System PLL Control register */ + #define PERF_SYS_PLL_CTL_REG 0x8 + #define SYS_PLL_SOFT_RESET 0x1 +@@ -224,6 +272,7 @@ + #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c) + #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10) + #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10) ++#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20) + + /* Interrupt Status register */ + #define PERF_IRQSTAT_3368_REG 0x10 +@@ -234,6 +283,7 @@ + #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c) + #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10) + #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10) ++#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20) + + /* External Interrupt Configuration register */ + #define PERF_EXTIRQ_CFG_REG_3368 0x14 +@@ -244,6 +294,7 @@ + #define PERF_EXTIRQ_CFG_REG_6358 0x14 + #define PERF_EXTIRQ_CFG_REG_6362 0x18 + #define PERF_EXTIRQ_CFG_REG_6368 0x18 ++#define PERF_EXTIRQ_CFG_REG_63268 0x18 + + #define PERF_EXTIRQ_CFG_REG2_6358 0x1c + #define PERF_EXTIRQ_CFG_REG2_6368 0x1c +@@ -274,6 +325,7 @@ + #define PERF_SOFTRESET_6358_REG 0x34 + #define PERF_SOFTRESET_6362_REG 0x10 + #define PERF_SOFTRESET_6368_REG 0x10 ++#define PERF_SOFTRESET_63268_REG 0x10 + + #define SOFTRESET_3368_SPI_MASK (1 << 0) + #define SOFTRESET_3368_ENET_MASK (1 << 2) +@@ -367,6 +419,26 @@ + #define SOFTRESET_6368_USBH_MASK (1 << 12) + #define SOFTRESET_6368_PCM_MASK (1 << 13) + ++#define SOFTRESET_63268_SPI_MASK (1 << 0) ++#define SOFTRESET_63268_IPSEC_MASK (1 << 1) ++#define SOFTRESET_63268_EPHY_MASK (1 << 2) ++#define SOFTRESET_63268_SAR_MASK (1 << 3) ++#define SOFTRESET_63268_ENETSW_MASK (1 << 4) ++#define SOFTRESET_63268_USBS_MASK (1 << 5) ++#define SOFTRESET_63268_USBH_MASK (1 << 6) ++#define SOFTRESET_63268_PCM_MASK (1 << 7) ++#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8) ++#define SOFTRESET_63268_PCIE_MASK (1 << 9) ++#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10) ++#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11) ++#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12) ++#define SOFTRESET_63268_FAP0_MASK (1 << 13) ++#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14) ++#define SOFTRESET_63268_DECT_MASK (1 << 15) ++#define SOFTRESET_63268_FAP1_MASK (1 << 16) ++#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17) ++#define SOFTRESET_63268_GPHY_MASK (1 << 18) ++ + /* MIPS PLL control register */ + #define PERF_MIPSPLLCTL_REG 0x34 + #define MIPSPLLCTL_N1_SHIFT 20 +@@ -1366,6 +1438,13 @@ + #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) + #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) + ++#define MISC_STRAPBUS_63268_REG 0x14 ++#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9) ++#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11) ++#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11) ++#define STRAPBUS_63268_FCVO_SHIFT 21 ++#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) ++ + #define MISC_STRAPBUS_6328_REG 0x240 + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) +--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h ++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h +@@ -25,6 +25,7 @@ static inline int is_bcm63xx_internal_re + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM6368_CPU_ID: ++ case BCM63268_CPU_ID: + if (offset >= 0xb0000000 && offset < 0xb1000000) + return 1; + break; +--- a/arch/mips/bcm63xx/dev-hsspi.c ++++ b/arch/mips/bcm63xx/dev-hsspi.c +@@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs + + int __init bcm63xx_hsspi_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362()) ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); +--- a/arch/mips/bcm63xx/dev-enet.c ++++ b/arch/mips/bcm63xx/dev-enet.c +@@ -176,7 +176,8 @@ static int __init register_shared(void) + else + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || ++ BCMCPU_IS_63268()) + chan_count = 32; + else if (BCMCPU_IS_6345()) + chan_count = 8; +@@ -276,7 +277,8 @@ bcm63xx_enetsw_register(const struct bcm + { + int ret; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && ++ !BCMCPU_IS_63268()) + return -ENODEV; + + ret = register_shared(); +@@ -297,6 +299,8 @@ bcm63xx_enetsw_register(const struct bcm + enetsw_pd.num_ports = ENETSW_PORTS_6328; + else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) + enetsw_pd.num_ports = ENETSW_PORTS_6368; ++ else if (BCMCPU_IS_63268()) ++ enetsw_pd.num_ports = ENETSW_PORTS_63268; + + enetsw_pd.dma_has_sram = true; + enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h +@@ -62,6 +62,7 @@ struct bcm63xx_enet_platform_data { + #define ENETSW_MAX_PORT 8 + #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */ + #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */ ++#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */ + + #define ENETSW_RGMII_PORT0 4 + diff --git a/target/linux/brcm63xx/patches-4.1/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch b/target/linux/brcm63xx/patches-4.1/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch new file mode 100644 index 0000000..4e8a090 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch @@ -0,0 +1,55 @@ +From 5c290c81dbdb4433600593fe80c88eb4af86e791 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 03:22:40 +0100 +Subject: [PATCH 50/53] MIPS: BCM63XX: add pcie support for BCM63268 + +--- + arch/mips/bcm63xx/reset.c | 3 ++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 5 +++++ + arch/mips/pci/pci-bcm63xx.c | 4 ++++ + 3 files changed, 11 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -136,7 +136,8 @@ + #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK + #define BCM63268_RESET_MPI 0 + #define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ +- SOFTRESET_63268_PCIE_CORE_MASK) ++ SOFTRESET_63268_PCIE_CORE_MASK | \ ++ SOFTRESET_63268_PCIE_HARD_MASK) + #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK + + /* +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -45,6 +45,11 @@ + #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ + BCM_PCIE_MEM_SIZE_6328 - 1) + ++#define BCM_PCIE_MEM_BASE_PA_63268 0x11000000 ++#define BCM_PCIE_MEM_SIZE_63268 (15 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_63268 (BCM_PCIE_MEM_BASE_PA_63268 + \ ++ BCM_PCIE_MEM_SIZE_63268 - 1) ++ + /* + * Internal registers are accessed through KSEG3 + */ +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -337,11 +337,15 @@ static int __init bcm63xx_pci_init(void) + if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { + bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; + bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; ++ } else if (BCMCPU_IS_63268()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_63268; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_63268; + } + + switch (bcm63xx_get_cpu_id()) { + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: ++ case BCM63268_CPU_ID: + return bcm63xx_register_pcie(); + case BCM3368_CPU_ID: + case BCM6348_CPU_ID: diff --git a/target/linux/brcm63xx/patches-4.1/341-MIPS-BCM63XX-add-support-for-BCM6318.patch b/target/linux/brcm63xx/patches-4.1/341-MIPS-BCM63XX-add-support-for-BCM6318.patch new file mode 100644 index 0000000..1bcaae2 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/341-MIPS-BCM63XX-add-support-for-BCM6318.patch @@ -0,0 +1,675 @@ +From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 01:24:09 +0100 +Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318 + +--- + arch/mips/bcm63xx/Kconfig | 5 + + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/clk.c | 8 +- + arch/mips/bcm63xx/cpu.c | 53 +++++++++++ + arch/mips/bcm63xx/dev-flash.c | 3 + + arch/mips/bcm63xx/dev-spi.c | 2 +- + arch/mips/bcm63xx/irq.c | 10 ++ + arch/mips/bcm63xx/prom.c | 2 +- + arch/mips/bcm63xx/reset.c | 24 +++++ + arch/mips/bcm63xx/setup.c | 5 +- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 107 ++++++++++++++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 75 ++++++++++++++- + arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + + 13 files changed, 291 insertions(+), 6 deletions(-) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -18,6 +18,11 @@ config BCM63XX_EHCI + select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD + select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD + ++config BCM63XX_CPU_6318 ++ bool "support 6318 CPU" ++ select SYS_HAS_CPU_BMIPS32_3300 ++ select HW_HAS_PCI ++ + config BCM63XX_CPU_6328 + bool "support 6328 CPU" + select SYS_HAS_CPU_BMIPS4350 +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -712,7 +712,7 @@ void __init board_prom_init(void) + /* read base address of boot chip select (0) + * 6328/6362 do not have MPI but boot from a fixed address + */ +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { + val = 0x18000000; + } else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -252,7 +252,9 @@ static void hsspi_set(struct clk *clk, i + { + u32 mask; + +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) ++ mask = CKCTL_6318_HSSPI_EN; ++ else if (BCMCPU_IS_6328()) + mask = CKCTL_6328_HSSPI_EN; + else if (BCMCPU_IS_6362()) + mask = CKCTL_6362_HSSPI_EN; +@@ -417,12 +419,16 @@ void clk_put(struct clk *clk) + + EXPORT_SYMBOL(clk_put); + ++#define HSSPI_PLL_HZ_6318 250000000 + #define HSSPI_PLL_HZ_6328 133333333 + #define HSSPI_PLL_HZ_6362 400000000 + + static int __init bcm63xx_clk_init(void) + { + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ clk_hsspi.rate = HSSPI_PLL_HZ_6318; ++ break; + case BCM6328_CPU_ID: + clk_hsspi.rate = HSSPI_PLL_HZ_6328; + break; +--- a/arch/mips/bcm63xx/cpu.c ++++ b/arch/mips/bcm63xx/cpu.c +@@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = { + __GEN_CPU_IRQ_TABLE(3368) + }; + ++static const unsigned long bcm6318_regs_base[] = { ++ __GEN_CPU_REGS_TABLE(6318) ++}; ++ ++static const int bcm6318_irqs[] = { ++ __GEN_CPU_IRQ_TABLE(6318) ++}; ++ + static const unsigned long bcm6328_regs_base[] = { + __GEN_CPU_REGS_TABLE(6328) + }; +@@ -134,6 +142,10 @@ unsigned int bcm63xx_get_memory_size(voi + return bcm63xx_memory_size; + } + ++#define STRAP_OVERRIDE_BUS_REG 0x0 ++#define OVERRIDE_BUS_MIPS_FREQ_SHIFT 23 ++#define OVERRIDE_BUS_MIPS_FREQ_MASK (0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT) ++ + static unsigned int detect_cpu_clock(void) + { + u32 cpu_id = bcm63xx_get_cpu_id(); +@@ -142,6 +154,28 @@ static unsigned int detect_cpu_clock(voi + case BCM3368_CPU_ID: + return 300000000; + ++ case BCM6318_CPU_ID: ++ { ++ unsigned int tmp, mips_pll_fcvo; ++ ++ tmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG); ++ ++ pr_info("strap_override_bus = %08x\n", tmp); ++ ++ mips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK) ++ >> OVERRIDE_BUS_MIPS_FREQ_SHIFT; ++ ++ switch (mips_pll_fcvo) { ++ case 0: ++ return 166000000; ++ case 1: ++ return 400000000; ++ case 2: ++ return 250000000; ++ case 3: ++ return 333000000; ++ }; ++ } + case BCM6328_CPU_ID: + { + unsigned int tmp, mips_pll_fcvo; +@@ -297,6 +331,13 @@ static unsigned int detect_memory_size(v + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + ++ if (BCMCPU_IS_6318()) { ++ val = bcm_sdram_readl(SDRAM_CFG_REG); ++ val = val & SDRAM_CFG_6318_SPACE_MASK; ++ val >>= SDRAM_CFG_6318_SPACE_SHIFT; ++ return 1 << (val + 20); ++ } ++ + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) + return bcm_ddr_readl(DDR_CSEND_REG) << 24; + +@@ -343,6 +384,12 @@ void __init bcm63xx_cpu_init(void) + + switch (current_cpu_type()) { + case CPU_BMIPS3300: ++ if ((read_c0_prid() & 0xff) >= 0x33) { ++ /* BCM6318 */ ++ chipid_reg = BCM_6368_PERF_BASE; ++ break; ++ } ++ + if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT) + __cpu_name[cpu] = "Broadcom BCM6338"; + /* fall-through */ +@@ -390,6 +437,10 @@ void __init bcm63xx_cpu_init(void) + bcm63xx_cpu_variant = bcm63xx_cpu_id; + + switch (bcm63xx_cpu_id) { ++ case BCM6318_CPU_ID: ++ bcm63xx_regs_base = bcm6318_regs_base; ++ bcm63xx_irqs = bcm6318_irqs; ++ break; + case BCM3368_CPU_ID: + bcm63xx_regs_base = bcm3368_regs_base; + bcm63xx_irqs = bcm3368_irqs; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t + u32 val; + + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ /* only support serial flash */ ++ return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6328_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); + if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) +--- a/arch/mips/bcm63xx/dev-spi.c ++++ b/arch/mips/bcm63xx/dev-spi.c +@@ -70,7 +70,7 @@ static struct platform_device bcm63xx_sp + + int __init bcm63xx_spi_register(void) + { +- if (BCMCPU_IS_6328() || BCMCPU_IS_6345()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI); +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -49,6 +49,19 @@ void __init arch_init_irq(void) + ext_irqs[3] = BCM_3368_EXT_IRQ3; + ext_shift = 4; + break; ++ case BCM6318_CPU_ID: ++ periph_bases[0] += PERF_IRQMASK_6318_REG; ++ periph_irq_count = 1; ++ periph_width = 4; ++ ++ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318; ++ ext_irq_count = 4; ++ ext_irqs[0] = BCM_6318_EXT_IRQ0; ++ ext_irqs[1] = BCM_6318_EXT_IRQ0; ++ ext_irqs[2] = BCM_6318_EXT_IRQ0; ++ ext_irqs[3] = BCM_6318_EXT_IRQ0; ++ ext_shift = 4; ++ break; + case BCM6328_CPU_ID: + periph_bases[0] += PERF_IRQMASK_6328_REG(0); + periph_bases[1] += PERF_IRQMASK_6328_REG(1); +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -68,7 +68,7 @@ void __init prom_init(void) + + if (reg & OTP_6328_REG3_TP1_DISABLED) + bmips_smp_enabled = 0; +- } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { ++ } else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) { + bmips_smp_enabled = 0; + } + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -43,6 +43,23 @@ + #define BCM3368_RESET_PCIE 0 + #define BCM3368_RESET_PCIE_EXT 0 + ++ ++#define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK ++#define BCM6318_RESET_ENET 0 ++#define BCM6318_RESET_USBH SOFTRESET_6318_USBH_MASK ++#define BCM6318_RESET_USBD SOFTRESET_6318_USBS_MASK ++#define BCM6318_RESET_DSL 0 ++#define BCM6318_RESET_SAR SOFTRESET_6318_SAR_MASK ++#define BCM6318_RESET_EPHY SOFTRESET_6318_EPHY_MASK ++#define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK ++#define BCM6318_RESET_PCM 0 ++#define BCM6318_RESET_MPI 0 ++#define BCM6318_RESET_PCIE \ ++ (SOFTRESET_6318_PCIE_MASK | \ ++ SOFTRESET_6318_PCIE_CORE_MASK | \ ++ SOFTRESET_6318_PCIE_HARD_MASK) ++#define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK ++ + #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK + #define BCM6328_RESET_ENET 0 + #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK +@@ -147,6 +164,10 @@ static const u32 bcm3368_reset_bits[] = + __GEN_RESET_BITS_TABLE(3368) + }; + ++static const u32 bcm6318_reset_bits[] = { ++ __GEN_RESET_BITS_TABLE(6318) ++}; ++ + static const u32 bcm6328_reset_bits[] = { + __GEN_RESET_BITS_TABLE(6328) + }; +@@ -183,6 +204,9 @@ static int __init bcm63xx_reset_bits_ini + if (BCMCPU_IS_3368()) { + reset_reg = PERF_SOFTRESET_6358_REG; + bcm63xx_reset_bits = bcm3368_reset_bits; ++ } else if (BCMCPU_IS_6318()) { ++ reset_reg = PERF_SOFTRESET_6318_REG; ++ bcm63xx_reset_bits = bcm6318_reset_bits; + } else if (BCMCPU_IS_6328()) { + reset_reg = PERF_SOFTRESET_6328_REG; + bcm63xx_reset_bits = bcm6328_reset_bits; +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -72,6 +72,9 @@ void bcm63xx_machine_reboot(void) + case BCM3368_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368; + break; ++ case BCM6318_CPU_ID: ++ perf_regs[0] = PERF_EXTIRQ_CFG_REG_6318; ++ break; + case BCM6328_CPU_ID: + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; + break; +@@ -111,7 +114,7 @@ void bcm63xx_machine_reboot(void) + bcm6348_a1_reboot(); + + printk(KERN_INFO "triggering watchdog soft-reset...\n"); +- if (BCMCPU_IS_6328()) { ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) { + bcm_wdt_writel(1, WDT_SOFTRESET_REG); + } else { + reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +@@ -10,6 +10,7 @@ + * arm mach-types) + */ + #define BCM3368_CPU_ID 0x3368 ++#define BCM6318_CPU_ID 0x6318 + #define BCM6328_CPU_ID 0x6328 + #define BCM63281_CPU_ID 0x63281 + #define BCM63283_CPU_ID 0x63283 +@@ -38,6 +39,10 @@ static inline u32 __pure __bcm63xx_get_c + case BCM3368_CPU_ID: + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6318 ++ case BCM6318_CPU_ID: ++#endif ++ + #ifdef CONFIG_BCM63XX_CPU_6328 + case BCM6328_CPU_ID: + #endif +@@ -87,6 +92,7 @@ static inline u32 __pure bcm63xx_get_cpu + } + + #define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) ++#define BCMCPU_IS_6318() (bcm63xx_get_cpu_id() == BCM6318_CPU_ID) + #define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) + #define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) + #define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) +@@ -98,6 +104,8 @@ static inline u32 __pure bcm63xx_get_cpu + + #define BCMCPU_VARIANT_IS_3368() \ + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) ++#define BCMCPU_VARIANT_IS_6318() \ ++ (bcm63xx_get_cpu_variant() == BCM6318_CPU_ID) + #define BCMCPU_VARIANT_IS_63281() \ + (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) + #define BCMCPU_VARIANT_IS_63283() \ +@@ -252,6 +260,56 @@ enum bcm63xx_regs_set { + #define BCM_3368_MISC_BASE (0xdeadbeef) + + /* ++ * 6318 register sets base address ++ */ ++#define BCM_6318_DSL_LMEM_BASE (0xdeadbeef) ++#define BCM_6318_PERF_BASE (0xb0000000) ++#define BCM_6318_TIMER_BASE (0xb0000040) ++#define BCM_6318_WDT_BASE (0xb0000068) ++#define BCM_6318_UART0_BASE (0xb0000100) ++#define BCM_6318_UART1_BASE (0xdeadbeef) ++#define BCM_6318_GPIO_BASE (0xb0000080) ++#define BCM_6318_SPI_BASE (0xdeadbeef) ++#define BCM_6318_HSSPI_BASE (0xb0003000) ++#define BCM_6318_UDC0_BASE (0xdeadbeef) ++#define BCM_6318_USBDMA_BASE (0xb0006800) ++#define BCM_6318_OHCI0_BASE (0xb0005100) ++#define BCM_6318_OHCI_PRIV_BASE (0xdeadbeef) ++#define BCM_6318_USBH_PRIV_BASE (0xb0005200) ++#define BCM_6318_USBD_BASE (0xb0006000) ++#define BCM_6318_MPI_BASE (0xdeadbeef) ++#define BCM_6318_PCMCIA_BASE (0xdeadbeef) ++#define BCM_6318_PCIE_BASE (0xb0010000) ++#define BCM_6318_SDRAM_REGS_BASE (0xdeadbeef) ++#define BCM_6318_DSL_BASE (0xdeadbeef) ++#define BCM_6318_UBUS_BASE (0xdeadbeef) ++#define BCM_6318_ENET0_BASE (0xdeadbeef) ++#define BCM_6318_ENET1_BASE (0xdeadbeef) ++#define BCM_6318_ENETDMA_BASE (0xb0088000) ++#define BCM_6318_ENETDMAC_BASE (0xb0088200) ++#define BCM_6318_ENETDMAS_BASE (0xb0088400) ++#define BCM_6318_ENETSW_BASE (0xb0080000) ++#define BCM_6318_EHCI0_BASE (0xb0005000) ++#define BCM_6318_SDRAM_BASE (0xb0004000) ++#define BCM_6318_MEMC_BASE (0xdeadbeef) ++#define BCM_6318_DDR_BASE (0xdeadbeef) ++#define BCM_6318_M2M_BASE (0xdeadbeef) ++#define BCM_6318_ATM_BASE (0xdeadbeef) ++#define BCM_6318_XTM_BASE (0xdeadbeef) ++#define BCM_6318_XTMDMA_BASE (0xb000c000) ++#define BCM_6318_XTMDMAC_BASE (0xdeadbeef) ++#define BCM_6318_XTMDMAS_BASE (0xdeadbeef) ++#define BCM_6318_PCM_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMA_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMAC_BASE (0xdeadbeef) ++#define BCM_6318_PCMDMAS_BASE (0xdeadbeef) ++#define BCM_6318_RNG_BASE (0xdeadbeef) ++#define BCM_6318_MISC_BASE (0xb0000280) ++#define BCM_6318_OTP_BASE (0xdeadbeef) ++ ++#define BCM_6318_STRAP_BASE (0xb0000900) ++ ++/* + * 6328 register sets base address + */ + #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) +@@ -774,6 +832,55 @@ enum bcm63xx_irq { + #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) + #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) + ++/* ++ * 6318 irqs ++ */ ++#define BCM_6318_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) ++#define BCM_6318_VERY_HIGH_IRQ_BASE (BCM_6318_HIGH_IRQ_BASE + 32) ++ ++#define BCM_6318_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) ++#define BCM_6318_SPI_IRQ 0 ++#define BCM_6318_UART0_IRQ (IRQ_INTERNAL_BASE + 28) ++#define BCM_6318_UART1_IRQ 0 ++#define BCM_6318_DSL_IRQ (IRQ_INTERNAL_BASE + 21) ++#define BCM_6318_UDC0_IRQ 0 ++#define BCM_6318_ENET0_IRQ 0 ++#define BCM_6318_ENET1_IRQ 0 ++#define BCM_6318_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) ++#define BCM_6318_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) ++#define BCM_6318_OHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 9) ++#define BCM_6318_EHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 10) ++#define BCM_6318_USBD_IRQ (IRQ_INTERNAL_BASE + 4) ++#define BCM_6318_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) ++#define BCM_6318_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) ++#define BCM_6318_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) ++#define BCM_6318_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) ++#define BCM_6318_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) ++#define BCM_6318_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) ++#define BCM_6318_PCMCIA_IRQ 0 ++#define BCM_6318_ENET0_RXDMA_IRQ 0 ++#define BCM_6318_ENET0_TXDMA_IRQ 0 ++#define BCM_6318_ENET1_RXDMA_IRQ 0 ++#define BCM_6318_ENET1_TXDMA_IRQ 0 ++#define BCM_6318_PCI_IRQ (IRQ_INTERNAL_BASE + 23) ++#define BCM_6318_ATM_IRQ 0 ++#define BCM_6318_ENETSW_RXDMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 0) ++#define BCM_6318_ENETSW_RXDMA1_IRQ (BCM_6318_HIGH_IRQ_BASE + 1) ++#define BCM_6318_ENETSW_RXDMA2_IRQ (BCM_6318_HIGH_IRQ_BASE + 2) ++#define BCM_6318_ENETSW_RXDMA3_IRQ (BCM_6318_HIGH_IRQ_BASE + 3) ++#define BCM_6318_ENETSW_TXDMA0_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 10) ++#define BCM_6318_ENETSW_TXDMA1_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 11) ++#define BCM_6318_ENETSW_TXDMA2_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 12) ++#define BCM_6318_ENETSW_TXDMA3_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 13) ++#define BCM_6318_XTM_IRQ (BCM_6318_HIGH_IRQ_BASE + 31) ++#define BCM_6318_XTM_DMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 11) ++ ++#define BCM_6318_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) ++#define BCM_6318_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) ++#define BCM_6318_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) ++#define BCM_6318_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) ++#define BCM_6318_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) ++#define BCM_6318_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) + + /* + * 6328 irqs +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -52,6 +52,39 @@ + CKCTL_3368_EMUSB_EN | \ + CKCTL_3368_USBU_EN) + ++#define CKCTL_6318_ADSL_ASB_EN (1 << 0) ++#define CKCTL_6318_USB_ASB_EN (1 << 1) ++#define CKCTL_6318_MIPS_ASB_EN (1 << 2) ++#define CKCTL_6318_PCIE_ASB_EN (1 << 3) ++#define CKCTL_6318_PHYMIPS_ASB_EN (1 << 4) ++#define CKCTL_6318_ROBOSW_ASB_EN (1 << 5) ++#define CKCTL_6318_SAR_ASB_EN (1 << 6) ++#define CKCTL_6318_SDR_ASB_EN (1 << 7) ++#define CKCTL_6318_SWREG_ASB_EN (1 << 8) ++#define CKCTL_6318_PERIPH_ASB_EN (1 << 9) ++#define CKCTL_6318_CPUBUS160_EN (1 << 10) ++#define CKCTL_6318_ADSL_EN (1 << 11) ++#define CKCTL_6318_SAR125_EN (1 << 12) ++#define CKCTL_6318_MIPS_EN (1 << 13) ++#define CKCTL_6318_PCIE_EN (1 << 14) ++#define CKCTL_6318_ROBOSW250_EN (1 << 16) ++#define CKCTL_6318_ROBOSW025_EN (1 << 17) ++#define CKCTL_6318_SDR_EN (1 << 19) ++#define CKCTL_6318_USB_EN (1 << 20) /* both device and host */ ++#define CKCTL_6318_HSSPI_EN (1 << 25) ++#define CKCTL_6318_PCIE25_EN (1 << 27) ++#define CKCTL_6318_PHYMIPS_EN (1 << 28) ++#define CKCTL_6318_ADSL_AFE_EN (1 << 29) ++#define CKCTL_6318_ADSL_QPROC_EN (1 << 30) ++ ++#define CKCTL_6318_ALL_SAFE_EN (CKCTL_6318_PHYMIPS_EN | \ ++ CKCTL_6318_ADSL_QPROC_EN | \ ++ CKCTL_6318_ADSL_AFE_EN | \ ++ CKCTL_6318_ADSL_EN | \ ++ CKCTL_6318_SAR_EN | \ ++ CKCTL_6318_USB_EN | \ ++ CKCTL_6318_PCIE_EN) ++ + #define CKCTL_6328_PHYMIPS_EN (1 << 0) + #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) + #define CKCTL_6328_ADSL_AFE_EN (1 << 2) +@@ -259,12 +292,27 @@ + CKCTL_63268_TBUS_EN | \ + CKCTL_63268_ROBOSW250_EN) + ++/* UBUS Clock Control register */ ++#define PERF_UB_CKCTL_REG 0x10 ++ ++#define UB_CKCTL_6318_ADSL_EN (1 << 0) ++#define UB_CKCTL_6318_ARB_EN (1 << 1) ++#define UB_CKCTL_6318_MIPS_EN (1 << 2) ++#define UB_CKCTL_6318_PCIE_EN (1 << 3) ++#define UB_CKCTL_6318_PERIPH_EN (1 << 4) ++#define UB_CKCTL_6318_PHYMIPS_EN (1 << 5) ++#define UB_CKCTL_6318_ROBOSW_EN (1 << 6) ++#define UB_CKCTL_6318_SAR_EN (1 << 7) ++#define UB_CKCTL_6318_SDR_EN (1 << 8) ++#define UB_CKCTL_6318_USB_EN (1 << 9) ++ + /* System PLL Control register */ + #define PERF_SYS_PLL_CTL_REG 0x8 + #define SYS_PLL_SOFT_RESET 0x1 + + /* Interrupt Mask register */ + #define PERF_IRQMASK_3368_REG 0xc ++#define PERF_IRQMASK_6318_REG 0x20 + #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10) + #define PERF_IRQMASK_6338_REG 0xc + #define PERF_IRQMASK_6345_REG 0xc +@@ -276,6 +324,7 @@ + + /* Interrupt Status register */ + #define PERF_IRQSTAT_3368_REG 0x10 ++#define PERF_IRQSTAT_6318_REG 0x30 + #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10) + #define PERF_IRQSTAT_6338_REG 0x10 + #define PERF_IRQSTAT_6345_REG 0x10 +@@ -287,6 +336,7 @@ + + /* External Interrupt Configuration register */ + #define PERF_EXTIRQ_CFG_REG_3368 0x14 ++#define PERF_EXTIRQ_CFG_REG_6318 0x18 + #define PERF_EXTIRQ_CFG_REG_6328 0x18 + #define PERF_EXTIRQ_CFG_REG_6338 0x14 + #define PERF_EXTIRQ_CFG_REG_6345 0x14 +@@ -321,6 +371,7 @@ + + /* Soft Reset register */ + #define PERF_SOFTRESET_REG 0x28 ++#define PERF_SOFTRESET_6318_REG 0x10 + #define PERF_SOFTRESET_6328_REG 0x10 + #define PERF_SOFTRESET_6358_REG 0x34 + #define PERF_SOFTRESET_6362_REG 0x10 +@@ -334,6 +385,18 @@ + #define SOFTRESET_3368_USBS_MASK (1 << 11) + #define SOFTRESET_3368_PCM_MASK (1 << 13) + ++#define SOFTRESET_6318_SPI_MASK (1 << 0) ++#define SOFTRESET_6318_EPHY_MASK (1 << 1) ++#define SOFTRESET_6318_SAR_MASK (1 << 2) ++#define SOFTRESET_6318_ENETSW_MASK (1 << 3) ++#define SOFTRESET_6318_USBS_MASK (1 << 4) ++#define SOFTRESET_6318_USBH_MASK (1 << 5) ++#define SOFTRESET_6318_PCIE_CORE_MASK (1 << 6) ++#define SOFTRESET_6318_PCIE_MASK (1 << 7) ++#define SOFTRESET_6318_PCIE_EXT_MASK (1 << 8) ++#define SOFTRESET_6318_PCIE_HARD_MASK (1 << 9) ++#define SOFTRESET_6318_ADSL_MASK (1 << 10) ++ + #define SOFTRESET_6328_SPI_MASK (1 << 0) + #define SOFTRESET_6328_EPHY_MASK (1 << 1) + #define SOFTRESET_6328_SAR_MASK (1 << 2) +@@ -505,8 +568,17 @@ + #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) + #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) + ++#define TIMER_IRQMASK_6318_REG 0x0 ++#define TIMER_IRQSTAT_6318_REG 0x4 ++#define IRQSTATMASK_TIMER0 (1 << 0) ++#define IRQSTATMASK_TIMER1 (1 << 1) ++#define IRQSTATMASK_TIMER2 (1 << 2) ++#define IRQSTATMASK_TIMER3 (1 << 3) ++#define IRQSTATMASK_WDT (1 << 4) ++ + /* Timer control register */ + #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) ++#define TIMER_CTRx_6318_REG(x) (0x8 + (x * 4)) + #define TIMER_CTL0_REG 0x4 + #define TIMER_CTL1_REG 0x8 + #define TIMER_CTL2_REG 0xC +@@ -1253,6 +1325,8 @@ + #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) + #define SDRAM_CFG_BANK_SHIFT 13 + #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) ++#define SDRAM_CFG_6318_SPACE_SHIFT 4 ++#define SDRAM_CFG_6318_SPACE_MASK (0xf << SDRAM_CFG_6318_SPACE_SHIFT) + + #define SDRAM_MBASE_REG 0xc + +--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h ++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h +@@ -22,6 +22,7 @@ static inline int is_bcm63xx_internal_re + if (offset >= 0xfff00000) + return 1; + break; ++ case BCM6318_CPU_ID: + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM6368_CPU_ID: +--- a/arch/mips/bcm63xx/dev-hsspi.c ++++ b/arch/mips/bcm63xx/dev-hsspi.c +@@ -35,7 +35,8 @@ static struct platform_device bcm63xx_hs + + int __init bcm63xx_hsspi_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() && ++ !BCMCPU_IS_63268()) + return -ENODEV; + + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); +--- a/arch/mips/bcm63xx/dev-usb-usbd.c ++++ b/arch/mips/bcm63xx/dev-usb-usbd.c +@@ -41,7 +41,7 @@ int __init bcm63xx_usbd_register(const s + IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 }; + int i; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6368()) + return 0; + + usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD); +--- a/arch/mips/bcm63xx/dev-enet.c ++++ b/arch/mips/bcm63xx/dev-enet.c +@@ -176,8 +176,8 @@ static int __init register_shared(void) + else + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || +- BCMCPU_IS_63268()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_6368() || BCMCPU_IS_63268()) + chan_count = 32; + else if (BCMCPU_IS_6345()) + chan_count = 8; +@@ -277,8 +277,8 @@ bcm63xx_enetsw_register(const struct bcm + { + int ret; + +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && +- !BCMCPU_IS_63268()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() && ++ !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return -ENODEV; + + ret = register_shared(); +@@ -295,7 +295,7 @@ bcm63xx_enetsw_register(const struct bcm + + memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd)); + +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) + enetsw_pd.num_ports = ENETSW_PORTS_6328; + else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) + enetsw_pd.num_ports = ENETSW_PORTS_6368; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void); + static inline unsigned long bcm63xx_gpio_count(void) + { + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: ++ return 50; + case BCM6328_CPU_ID: + return 32; + case BCM3368_CPU_ID: +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -81,7 +81,8 @@ static struct platform_device bcm63xx_eh + + int __init bcm63xx_ehci_register(void) + { +- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && ++ !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) + return 0; + + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); diff --git a/target/linux/brcm63xx/patches-4.1/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch b/target/linux/brcm63xx/patches-4.1/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch new file mode 100644 index 0000000..71044f8 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch @@ -0,0 +1,156 @@ +From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 8 Dec 2013 14:17:50 +0100 +Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals + +--- + arch/mips/bcm63xx/reset.c | 39 ++++++++++++++-------- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 2 ++ + arch/mips/pci/pci-bcm63xx.c | 7 ++++ + 3 files changed, 34 insertions(+), 14 deletions(-) + +--- a/arch/mips/bcm63xx/reset.c ++++ b/arch/mips/bcm63xx/reset.c +@@ -28,7 +28,9 @@ + [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \ + [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \ + [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ +- [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, ++ [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, \ ++ [BCM63XX_RESET_PCIE_CORE] = BCM## __cpu ##_RESET_PCIE_CORE, \ ++ [BCM63XX_RESET_PCIE_HARD] = BCM## __cpu ##_RESET_PCIE_HARD, + + #define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK + #define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK +@@ -42,6 +44,8 @@ + #define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK + #define BCM3368_RESET_PCIE 0 + #define BCM3368_RESET_PCIE_EXT 0 ++#define BCM3368_RESET_PCIE_CORE 0 ++#define BCM3368_RESET_PCIE_HARD 0 + + + #define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK +@@ -54,11 +58,10 @@ + #define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK + #define BCM6318_RESET_PCM 0 + #define BCM6318_RESET_MPI 0 +-#define BCM6318_RESET_PCIE \ +- (SOFTRESET_6318_PCIE_MASK | \ +- SOFTRESET_6318_PCIE_CORE_MASK | \ +- SOFTRESET_6318_PCIE_HARD_MASK) ++#define BCM6318_RESET_PCIE SOFTRESET_6318_PCIE_MASK + #define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK ++#define BCM6318_RESET_PCIE_CORE SOFTRESET_6318_PCIE_CORE_MASK ++#define BCM6318_RESET_PCIE_HARD SOFTRESET_6318_PCIE_HARD_MASK + + #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK + #define BCM6328_RESET_ENET 0 +@@ -70,11 +73,10 @@ + #define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK + #define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK + #define BCM6328_RESET_MPI 0 +-#define BCM6328_RESET_PCIE \ +- (SOFTRESET_6328_PCIE_MASK | \ +- SOFTRESET_6328_PCIE_CORE_MASK | \ +- SOFTRESET_6328_PCIE_HARD_MASK) ++#define BCM6328_RESET_PCIE SOFTRESET_6328_PCIE_MASK + #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK ++#define BCM6328_RESET_PCIE_CORE SOFTRESET_6328_PCIE_CORE_MASK ++#define BCM6328_RESET_PCIE_HARD SOFTRESET_6328_PCIE_HARD_MASK + + #define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK + #define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK +@@ -88,6 +90,8 @@ + #define BCM6338_RESET_MPI 0 + #define BCM6338_RESET_PCIE 0 + #define BCM6338_RESET_PCIE_EXT 0 ++#define BCM6338_RESET_PCIE_CORE 0 ++#define BCM6338_RESET_PCIE_HARD 0 + + #define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK + #define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK +@@ -101,6 +105,8 @@ + #define BCM6348_RESET_MPI 0 + #define BCM6348_RESET_PCIE 0 + #define BCM6348_RESET_PCIE_EXT 0 ++#define BCM6348_RESET_PCIE_CORE 0 ++#define BCM6348_RESET_PCIE_HARD 0 + + #define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK + #define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK +@@ -114,6 +120,8 @@ + #define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK + #define BCM6358_RESET_PCIE 0 + #define BCM6358_RESET_PCIE_EXT 0 ++#define BCM6358_RESET_PCIE_CORE 0 ++#define BCM6358_RESET_PCIE_HARD 0 + + #define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK + #define BCM6362_RESET_ENET 0 +@@ -125,9 +133,10 @@ + #define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK + #define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK + #define BCM6362_RESET_MPI 0 +-#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \ +- SOFTRESET_6362_PCIE_CORE_MASK) ++#define BCM6362_RESET_PCIE SOFTRESET_6362_PCIE_MASK + #define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK ++#define BCM6362_RESET_PCIE_CORE SOFTRESET_6362_PCIE_CORE_MASK ++#define BCM6362_RESET_PCIE_HARD 0 + + #define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK + #define BCM6368_RESET_ENET 0 +@@ -141,6 +150,8 @@ + #define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK + #define BCM6368_RESET_PCIE 0 + #define BCM6368_RESET_PCIE_EXT 0 ++#define BCM6368_RESET_PCIE_CORE 0 ++#define BCM6368_RESET_PCIE_HARD 0 + + #define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK + #define BCM63268_RESET_ENET 0 +@@ -152,10 +163,10 @@ + #define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK + #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK + #define BCM63268_RESET_MPI 0 +-#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ +- SOFTRESET_63268_PCIE_CORE_MASK | \ +- SOFTRESET_63268_PCIE_HARD_MASK) ++#define BCM63268_RESET_PCIE SOFTRESET_63268_PCIE_MASK + #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK ++#define BCM63268_RESET_PCIE_CORE SOFTRESET_63268_PCIE_CORE_MASK ++#define BCM63268_RESET_PCIE_HARD SOFTRESET_63268_PCIE_HARD_MASK + + /* + * core reset bits +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h +@@ -14,6 +14,8 @@ enum bcm63xx_core_reset { + BCM63XX_RESET_MPI, + BCM63XX_RESET_PCIE, + BCM63XX_RESET_PCIE_EXT, ++ BCM63XX_RESET_PCIE_CORE, ++ BCM63XX_RESET_PCIE_HARD, + }; + + void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset); +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo + + /* reset the PCIe core */ + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1); + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); ++ if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) { ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0); ++ } + mdelay(10); + ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0); + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); + mdelay(10); + diff --git a/target/linux/brcm63xx/patches-4.1/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch b/target/linux/brcm63xx/patches-4.1/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch new file mode 100644 index 0000000..4ffeac9 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch @@ -0,0 +1,342 @@ +From 11a8ab8dac4ef5d0d70199843043927edce1d4db Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 15 Dec 2013 20:47:34 +0100 +Subject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318 + +--- + arch/mips/bcm63xx/clk.c | 25 ++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 6 ++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 60 +++++++++++- + arch/mips/pci/ops-bcm63xx.c | 16 +++- + arch/mips/pci/pci-bcm63xx.c | 106 ++++++++++++++++++---- + 5 files changed, 184 insertions(+), 29 deletions(-) + +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -50,6 +50,18 @@ static void bcm_hwclock_set(u32 mask, in + bcm_perf_writel(reg, PERF_CKCTL_REG); + } + ++static void bcm_ub_hwclock_set(u32 mask, int enable) ++{ ++ u32 reg; ++ ++ reg = bcm_perf_readl(PERF_UB_CKCTL_REG); ++ if (enable) ++ reg |= mask; ++ else ++ reg &= ~mask; ++ bcm_perf_writel(reg, PERF_UB_CKCTL_REG); ++} ++ + /* + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 + */ +@@ -317,12 +329,17 @@ static struct clk clk_ipsec = { + + static void pcie_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_PCIE_EN, enable); ++ bcm_hwclock_set(CKCTL_6318_PCIE25_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_PCIE_EN, enable); ++ } else if (BCMCPU_IS_6328()) { + bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); +- else if (BCMCPU_IS_6362()) ++ } else if (BCMCPU_IS_6362()) { + bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); +- else if (BCMCPU_IS_63268()) ++ } else if (BCMCPU_IS_63268()) { + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable); ++ } + } + + static struct clk clk_pcie = { +@@ -405,7 +422,7 @@ struct clk *clk_get(struct device *dev, + if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) && + !strcmp(id, "ipsec")) + return &clk_ipsec; +- if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && ++ if ((BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) && + !strcmp(id, "pcie")) + return &clk_pcie; + return ERR_PTR(-ENOENT); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +@@ -40,6 +40,12 @@ + #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ + BCM_CB_MEM_SIZE - 1) + ++#define BCM_PCIE_MEM_BASE_PA_6318 0x10200000 ++#define BCM_PCIE_MEM_SIZE_6318 (1 * 1024 * 1024) ++#define BCM_PCIE_MEM_END_PA_6318 (BCM_PCIE_MEM_BASE_PA_6318 + \ ++ BCM_PCIE_MEM_SIZE_6318 - 1) ++ ++ + #define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000 + #define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024) + #define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -1529,6 +1529,17 @@ + * _REG relative to RSET_PCIE + *************************************************************************/ + ++#define PCIE_SPECIFIC_REG 0x188 ++#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT 0 ++#define SPECIFIC_ENDIAN_MODE_BAR1_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT 2 ++#define SPECIFIC_ENDIAN_MODE_BAR2_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT 4 ++#define SPECIFIC_ENDIAN_MODE_BAR3_MASK (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT) ++#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN 0 ++#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1 ++#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN 2 ++ + #define PCIE_CONFIG2_REG 0x408 + #define CONFIG2_BAR1_SIZE_EN 1 + #define CONFIG2_BAR1_SIZE_MASK 0xf +@@ -1574,7 +1585,54 @@ + #define PCIE_RC_INT_C (1 << 2) + #define PCIE_RC_INT_D (1 << 3) + +-#define PCIE_DEVICE_OFFSET 0x8000 ++#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG 0x400c ++#define C2P_MEM_WIN_ENDIAN_MODE_MASK 0x3 ++#define C2P_MEM_WIN_ENDIAN_NO_SWAP 0 ++#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1 ++#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2 ++#define C2P_MEM_WIN_BASE_ADDR_SHIFT 20 ++#define C2P_MEM_WIN_BASE_ADDR_MASK (0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT) ++ ++#define PCIE_RC_BAR1_CONFIG_LO_REG 0x402c ++#define RC_BAR_CFG_LO_SIZE_256MB 0xd ++#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT 20 ++#define RC_BAR_CFG_LO_MATCH_ADDR_MASK (0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT) ++ ++#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070 ++#define C2P_BASELIMIT_LIMIT_SHIFT 20 ++#define C2P_BASELIMIT_LIMIT_MASK (0xfff << C2P_BASELIMIT_LIMIT_SHIFT) ++#define C2P_BASELIMIT_BASE_SHIFT 4 ++#define C2P_BASELIMIT_BASE_MASK (0xfff << C2P_BASELIMIT_BASE_SHIFT) ++ ++#define PCIE_UBUS_BAR1_CFG_REMAP_REG 0x4088 ++#define BAR1_CFG_REMAP_OFFSET_SHIFT 20 ++#define BAR1_CFG_REMAP_OFFSET_MASK (0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT) ++#define BAR1_CFG_REMAP_ACCESS_EN 1 ++ ++#define PCIE_HARD_DEBUG_REG 0x4204 ++#define HARD_DEBUG_SERDES_IDDQ (1 << 23) ++ ++#define PCIE_CPU_INT1_MASK_CLEAR_REG 0x830c ++#define CPU_INT_PCIE_ERR_ATTN_CPU (1 << 0) ++#define CPU_INT_PCIE_INTA (1 << 1) ++#define CPU_INT_PCIE_INTB (1 << 2) ++#define CPU_INT_PCIE_INTC (1 << 3) ++#define CPU_INT_PCIE_INTD (1 << 4) ++#define CPU_INT_PCIE_INTR (1 << 5) ++#define CPU_INT_PCIE_NMI (1 << 6) ++#define CPU_INT_PCIE_UBUS (1 << 7) ++#define CPU_INT_IPI (1 << 8) ++ ++#define PCIE_EXT_CFG_INDEX_REG 0x8400 ++#define EXT_CFG_FUNC_NUM_SHIFT 12 ++#define EXT_CFG_FUNC_NUM_MASK (0x7 << EXT_CFG_FUNC_NUM_SHIFT) ++#define EXT_CFG_DEV_NUM_SHIFT 15 ++#define EXT_CFG_DEV_NUM_MASK (0xf << EXT_CFG_DEV_NUM_SHIFT) ++#define EXT_CFG_BUS_NUM_SHIFT 20 ++#define EXT_CFG_BUS_NUM_MASK (0xff << EXT_CFG_BUS_NUM_SHIFT) ++ ++#define PCIE_DEVICE_OFFSET_6318 0x9000 ++#define PCIE_DEVICE_OFFSET_6328 0x8000 + + /************************************************************************* + * _REG relative to RSET_OTP +--- a/arch/mips/pci/ops-bcm63xx.c ++++ b/arch/mips/pci/ops-bcm63xx.c +@@ -488,8 +488,12 @@ static int bcm63xx_pcie_read(struct pci_ + if (!bcm63xx_pcie_can_access(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (bus->number == PCIE_BUS_DEVICE) +- reg += PCIE_DEVICE_OFFSET; ++ if (bus->number == PCIE_BUS_DEVICE) { ++ if (BCMCPU_IS_6318()) ++ reg += PCIE_DEVICE_OFFSET_6318; ++ else ++ reg += PCIE_DEVICE_OFFSET_6328; ++ } + + data = bcm_pcie_readl(reg); + +@@ -508,8 +512,12 @@ static int bcm63xx_pcie_write(struct pci + if (!bcm63xx_pcie_can_access(bus, devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + +- if (bus->number == PCIE_BUS_DEVICE) +- reg += PCIE_DEVICE_OFFSET; ++ if (bus->number == PCIE_BUS_DEVICE) { ++ if (BCMCPU_IS_6318()) ++ reg += PCIE_DEVICE_OFFSET_6318; ++ else ++ reg += PCIE_DEVICE_OFFSET_6328; ++ } + + + data = bcm_pcie_readl(reg); +--- a/arch/mips/pci/pci-bcm63xx.c ++++ b/arch/mips/pci/pci-bcm63xx.c +@@ -118,7 +118,7 @@ static void bcm63xx_int_cfg_writel(u32 v + + void __iomem *pci_iospace_start; + +-static void __init bcm63xx_reset_pcie(void) ++static void __init bcm63xx_reset_pcie_gen1(void) + { + u32 val; + u32 reg; +@@ -152,20 +152,32 @@ static void __init bcm63xx_reset_pcie(vo + mdelay(200); + } + +-static struct clk *pcie_clk; +- +-static int __init bcm63xx_register_pcie(void) ++static void __init bcm63xx_reset_pcie_gen2(void) + { + u32 val; + +- /* enable clock */ +- pcie_clk = clk_get(NULL, "pcie"); +- if (IS_ERR_OR_NULL(pcie_clk)) +- return -ENODEV; ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0); + +- clk_prepare_enable(pcie_clk); ++ /* reset the PCIe core */ ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); ++ mdelay(10); ++ val = bcm_pcie_readl(PCIE_HARD_DEBUG_REG); ++ val &= ~HARD_DEBUG_SERDES_IDDQ; ++ bcm_pcie_writel(val, PCIE_HARD_DEBUG_REG); ++ mdelay(10); ++ bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0); ++ mdelay(200); ++} + +- bcm63xx_reset_pcie(); ++static void __init bcm63xx_init_pcie_gen1(void) ++{ ++ u32 val; + + /* configure the PCIe bridge */ + val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); +@@ -190,6 +202,65 @@ static int __init bcm63xx_register_pcie( + val |= OPT2_CFG_TYPE1_BD_SEL; + bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); + ++ /* set bar0 to little endian */ ++ val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; ++ val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; ++ val |= BASEMASK_REMAP_EN; ++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); ++ ++ val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; ++ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); ++} ++ ++static void __init bcm63xx_init_pcie_gen2(void) ++{ ++ u32 val; ++ ++ bcm_pcie_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB | ++ CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD, ++ PCIE_CPU_INT1_MASK_CLEAR_REG); ++ ++ val = bcm_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK; ++ val |= (bcm_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT) << ++ C2P_BASELIMIT_BASE_SHIFT; ++ ++ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG); ++ ++ /* set bar0 to little endian */ ++ val = bcm_pcie_readl(PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG); ++ val |= bcm_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK; ++ val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP; ++ bcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG); ++ ++ bcm_pcie_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN, PCIE_SPECIFIC_REG); ++ bcm_pcie_writel(RC_BAR_CFG_LO_SIZE_256MB, PCIE_RC_BAR1_CONFIG_LO_REG); ++ bcm_pcie_writel(BAR1_CFG_REMAP_ACCESS_EN, PCIE_UBUS_BAR1_CFG_REMAP_REG); ++ ++ bcm_pcie_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT, ++ PCIE_EXT_CFG_INDEX_REG); ++} ++ ++static struct clk *pcie_clk; ++ ++static int __init bcm63xx_register_pcie(void) ++{ ++ u32 val; ++ ++ /* enable clock */ ++ pcie_clk = clk_get(NULL, "pcie"); ++ if (IS_ERR_OR_NULL(pcie_clk)) ++ return -ENODEV; ++ ++ clk_prepare_enable(pcie_clk); ++ ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { ++ bcm63xx_reset_pcie_gen1(); ++ bcm63xx_init_pcie_gen1(); ++ } else { ++ bcm63xx_reset_pcie_gen2(); ++ bcm63xx_init_pcie_gen2(); ++ } ++ + /* setup class code as bridge */ + val = bcm_pcie_readl(PCIE_IDVAL3_REG); + val &= ~IDVAL3_CLASS_CODE_MASK; +@@ -201,15 +272,6 @@ static int __init bcm63xx_register_pcie( + val &= ~CONFIG2_BAR1_SIZE_MASK; + bcm_pcie_writel(val, PCIE_CONFIG2_REG); + +- /* set bar0 to little endian */ +- val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; +- val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; +- val |= BASEMASK_REMAP_EN; +- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); +- +- val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; +- bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); +- + register_pci_controller(&bcm63xx_pcie_controller); + + return 0; +@@ -341,7 +403,10 @@ static int __init bcm63xx_pci_init(void) + if (!bcm63xx_pci_enabled) + return -ENODEV; + +- if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { ++ if (BCMCPU_IS_6318()) { ++ bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6318; ++ bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6318; ++ } if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { + bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; + bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; + } else if (BCMCPU_IS_63268()) { +@@ -350,6 +415,7 @@ static int __init bcm63xx_pci_init(void) + } + + switch (bcm63xx_get_cpu_id()) { ++ case BCM6318_CPU_ID: + case BCM6328_CPU_ID: + case BCM6362_CPU_ID: + case BCM63268_CPU_ID: diff --git a/target/linux/brcm63xx/patches-4.1/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch b/target/linux/brcm63xx/patches-4.1/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch new file mode 100644 index 0000000..f5b0e77 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch @@ -0,0 +1,74 @@ +From 9a97177b907330971aa7bf41855fafc2602e1c18 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 22 Dec 2013 12:26:57 +0100 +Subject: [PATCH 51/56] MIPS: BCM63XX: detect flash type early and store the + result + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 10 +++++++--- + arch/mips/bcm63xx/prom.c | 4 ++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++ + 3 files changed, 13 insertions(+), 3 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -22,6 +22,8 @@ + #include + #include + ++static int flash_type; ++ + static struct mtd_partition mtd_partitions[] = { + { + .name = "cfe", +@@ -108,13 +110,15 @@ static int __init bcm63xx_detect_flash_t + } + } + ++void __init bcm63xx_flash_detect(void) ++{ ++ flash_type = bcm63xx_detect_flash_type(); ++} ++ + int __init bcm63xx_flash_register(void) + { +- int flash_type; + u32 val; + +- flash_type = bcm63xx_detect_flash_type(); +- + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: + /* read base address of boot chip select (0) */ +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + void __init prom_init(void) + { +@@ -52,6 +53,9 @@ void __init prom_init(void) + reg &= ~mask; + bcm_perf_writel(reg, PERF_CKCTL_REG); + ++ /* detect and setup flash access */ ++ bcm63xx_flash_detect(); ++ + /* do low level board init */ + board_prom_init(); + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -7,6 +7,8 @@ enum { + BCM63XX_FLASH_TYPE_NAND, + }; + ++void bcm63xx_flash_detect(void); ++ + int __init bcm63xx_flash_register(void); + + #endif /* __BCM63XX_FLASH_H */ diff --git a/target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch b/target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch new file mode 100644 index 0000000..c8bef13 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch @@ -0,0 +1,84 @@ +From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 22 Dec 2013 13:25:25 +0100 +Subject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot + +Some bootloaders leave the flash access in an invalid state with dual +read enabled; fix it by disabling it and falling back to simple fast +reads. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 51 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 51 insertions(+) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -110,9 +111,59 @@ static int __init bcm63xx_detect_flash_t + } + } + ++#define HSSPI_FLASH_CTRL_REG 0x14 ++#define FLASH_CTRL_READ_OPCODE_MASK 0xff ++#define FLASH_CTRL_ADDR_BYTES_MASK (0x3 << 8) ++#define FLASH_CTRL_ADDR_BYTES_2 (0 << 8) ++#define FLASH_CTRL_ADDR_BYTES_3 (1 << 8) ++#define FLASH_CTRL_ADDR_BYTES_4 (2 << 8) ++#define FLASH_CTRL_DUMMY_BYTES_SHIFT 10 ++#define FLASH_CTRL_DUMMY_BYTES_MASK (0x3 << FLASH_CTRL_DUMMY_BYTES_SHIFT) ++#define FLASH_CTRL_MB_EN (1 << 23) ++ + void __init bcm63xx_flash_detect(void) + { + flash_type = bcm63xx_detect_flash_type(); ++ ++ /* ensure flash mapping has sane values */ ++ if (flash_type == BCM63XX_FLASH_TYPE_SERIAL && ++ (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_63268())) { ++ u32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG); ++ ++ if (val & FLASH_CTRL_MB_EN) { ++ /* cfe might configure non working dual-io mode */ ++ val &= ~FLASH_CTRL_MB_EN; ++ val &= ~FLASH_CTRL_READ_OPCODE_MASK; ++ val &= ~FLASH_CTRL_DUMMY_BYTES_MASK; ++ val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT; ++ ++ switch (val & FLASH_CTRL_ADDR_BYTES_MASK) { ++ case FLASH_CTRL_ADDR_BYTES_3: ++ val |= SPINOR_OP_READ_FAST; ++ break; ++ case FLASH_CTRL_ADDR_BYTES_4: ++ val |= SPINOR_OP_READ4_FAST; ++ break; ++ case FLASH_CTRL_ADDR_BYTES_2: ++ default: ++ pr_warn("unsupported address byte mode (%x), not fixing up\n", ++ val & FLASH_CTRL_ADDR_BYTES_MASK); ++ return; ++ } ++ } else { ++ /* ensure dummy bytes is set to 1 for _FAST reads */ ++ u8 cmd = val & FLASH_CTRL_READ_OPCODE_MASK; ++ ++ if (cmd != SPINOR_OP_READ_FAST && cmd != SPINOR_OP_READ4_FAST) ++ return; ++ ++ val &= ~FLASH_CTRL_DUMMY_BYTES_MASK; ++ val |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT; ++ } ++ ++ bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG); ++ } + } + + int __init bcm63xx_flash_register(void) diff --git a/target/linux/brcm63xx/patches-4.1/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch b/target/linux/brcm63xx/patches-4.1/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch new file mode 100644 index 0000000..384702c --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -136,7 +136,11 @@ static struct clk clk_ephy = { + */ + static void enetsw_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_ROBOSW250_EN | ++ CKCTL_6318_ROBOSW025_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_ROBOSW_EN, enable); ++ } else if (BCMCPU_IS_6328()) + bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable); + else if (BCMCPU_IS_6362()) + bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable); +@@ -183,18 +187,22 @@ static struct clk clk_pcm = { + */ + static void usbh_set(struct clk *clk, int enable) + { +- if (BCMCPU_IS_6328()) ++ if (BCMCPU_IS_6318()) { ++ bcm_hwclock_set(CKCTL_6318_USB_EN, enable); ++ bcm_ub_hwclock_set(UB_CKCTL_6318_USB_EN, enable); ++ } else if (BCMCPU_IS_6328()) { + bcm_hwclock_set(CKCTL_6328_USBH_EN, enable); +- else if (BCMCPU_IS_6348()) ++ } else if (BCMCPU_IS_6348()) { + bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); +- else if (BCMCPU_IS_6362()) ++ } else if (BCMCPU_IS_6362()) { + bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); +- else if (BCMCPU_IS_6368()) ++ } else if (BCMCPU_IS_6368()) { + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); +- else if (BCMCPU_IS_63268()) ++ } else if (BCMCPU_IS_63268()) { + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); +- else ++ } else { + return; ++ } + + if (enable) + msleep(100); +@@ -405,9 +413,9 @@ struct clk *clk_get(struct device *dev, + return &clk_enetsw; + if (!strcmp(id, "ephy")) + return &clk_ephy; +- if (!strcmp(id, "usbh")) ++ if (!strcmp(id, "usbh") || (BCMCPU_IS_6318() && !strcmp(id, "usbd"))) + return &clk_usbh; +- if (!strcmp(id, "usbd")) ++ if (!strcmp(id, "usbd") && !BCMCPU_IS_6318()) + return &clk_usbd; + if (!strcmp(id, "spi")) + return &clk_spi; diff --git a/target/linux/brcm63xx/patches-4.1/347-MIPS-BCM6318-USB-support.patch b/target/linux/brcm63xx/patches-4.1/347-MIPS-BCM6318-USB-support.patch new file mode 100644 index 0000000..db489f8 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/347-MIPS-BCM6318-USB-support.patch @@ -0,0 +1,124 @@ +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_6318()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); ++ reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG); + } + + spin_unlock_irqrestore(&usb_priv_reg_lock, flags); +@@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_6318()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); ++ reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); ++ reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG); + } + + spin_unlock_irqrestore(&usb_priv_reg_lock, flags); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -681,6 +681,12 @@ + #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) + #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) + ++#define GPIO_PINMUX_SEL0_6318 0x1c ++#define GPIO_PINMUX_SEL0_GPIO13_SHIFT 26 ++#define GPIO_PINMUX_SEL0_GPIO13_MASK (0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_PWRON (1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_LED (2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) ++#define GPIO_PINMUX_SEL0_GPIO13_GPIO (3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) + + #define GPIO_PINMUX_OTHR_REG 0x24 + #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 +@@ -999,6 +1005,7 @@ + + #define USBH_PRIV_SWAP_6358_REG 0x0 + #define USBH_PRIV_SWAP_6368_REG 0x1c ++#define USBH_PRIV_SWAP_6318_REG 0x0c + + #define USBH_PRIV_SWAP_USBD_SHIFT 6 + #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) +@@ -1024,6 +1031,13 @@ + #define USBH_PRIV_SETUP_IOC_SHIFT 4 + #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) + ++#define USBH_PRIV_SETUP_6318_REG 0x00 ++#define USBH_PRIV_PLL_CTRL1_6318_REG 0x04 ++#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27) ++#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31) ++#define USBH_PRIV_SIM_CTRL_6318_REG 0x20 ++#define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5) ++ + + /************************************************************************* + * _REG relative to RSET_USBD +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -126,6 +126,15 @@ void __init board_early_setup(const stru + } + + bcm_gpio_writel(val, GPIO_MODE_REG); ++ ++#if IS_ENABLED(CONFIG_USB) ++ if (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) { ++ val = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318); ++ val &= ~GPIO_PINMUX_SEL0_GPIO13_MASK; ++ val |= GPIO_PINMUX_SEL0_GPIO13_PWRON; ++ bcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318); ++ } ++#endif + } + + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -22,6 +22,8 @@ config BCM63XX_CPU_6318 + bool "support 6318 CPU" + select SYS_HAS_CPU_BMIPS32_3300 + select HW_HAS_PCI ++ select BCM63XX_OHCI ++ select BCM63XX_EHCI + + config BCM63XX_CPU_6328 + bool "support 6328 CPU" diff --git a/target/linux/brcm63xx/patches-4.1/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch b/target/linux/brcm63xx/patches-4.1/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch new file mode 100644 index 0000000..10edbc4 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch @@ -0,0 +1,71 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -586,6 +586,9 @@ + #define TIMER_CTL_MONOTONIC_MASK (1 << 30) + #define TIMER_CTL_ENABLE_MASK (1 << 31) + ++/* Clock reset control (63268 only) */ ++#define TIMER_CLK_RST_CTL_REG 0x2c ++#define CLK_RST_CTL_USB_REF_CLK_EN (1 << 18) + + /************************************************************************* + * _REG relative to RSET_WDT +@@ -1533,6 +1536,11 @@ + #define STRAPBUS_63268_FCVO_SHIFT 21 + #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) + ++#define MISC_IDDQ_CTRL_6328_REG 0x48 ++#define MISC_IDDQ_CTRL_63268_REG 0x4c ++ ++#define IDDQ_CTRL_63268_USBH (1 << 4) ++ + #define MISC_STRAPBUS_6328_REG 0x240 + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) +--- a/arch/mips/bcm63xx/clk.c ++++ b/arch/mips/bcm63xx/clk.c +@@ -62,6 +62,26 @@ static void bcm_ub_hwclock_set(u32 mask, + bcm_perf_writel(reg, PERF_UB_CKCTL_REG); + } + ++static void bcm_misc_iddq_set(u32 mask, int enable) ++{ ++ u32 offset; ++ u32 reg; ++ ++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) ++ offset = MISC_IDDQ_CTRL_6328_REG; ++ else if (BCMCPU_IS_63268()) ++ offset = MISC_IDDQ_CTRL_63268_REG; ++ else ++ return; ++ ++ reg = bcm_misc_readl(offset); ++ if (enable) ++ reg &= ~mask; ++ else ++ reg |= mask; ++ bcm_misc_writel(reg, offset); ++} ++ + /* + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 + */ +@@ -199,7 +219,17 @@ static void usbh_set(struct clk *clk, in + } else if (BCMCPU_IS_6368()) { + bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); + } else if (BCMCPU_IS_63268()) { ++ u32 reg; ++ + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); ++ bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable); ++ bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable); ++ reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG); ++ if (enable) ++ reg |= CLK_RST_CTL_USB_REF_CLK_EN; ++ else ++ reg &= ~CLK_RST_CTL_USB_REF_CLK_EN; ++ bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG); + } else { + return; + } diff --git a/target/linux/brcm63xx/patches-4.1/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch b/target/linux/brcm63xx/patches-4.1/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch new file mode 100644 index 0000000..0b70991 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch @@ -0,0 +1,117 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -1033,11 +1033,18 @@ + #define USBH_PRIV_SETUP_6368_REG 0x28 + #define USBH_PRIV_SETUP_IOC_SHIFT 4 + #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) ++#define USBH_PRIV_SETUP_IPP_SHIFT 5 ++#define USBH_PRIV_SETUP_IPP_MASK (1 << USBH_PRIV_SETUP_IPP_SHIFT) + + #define USBH_PRIV_SETUP_6318_REG 0x00 ++#define USBH_PRIV_PLL_CTRL1_6368_REG 0x18 + #define USBH_PRIV_PLL_CTRL1_6318_REG 0x04 +-#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27) +-#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31) ++ ++#define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN (1 << 27) ++#define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN (1 << 31) ++#define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN (1 << 9) ++#define USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY (1 << 10) ++ + #define USBH_PRIV_SIM_CTRL_6318_REG 0x20 + #define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5) + +--- a/arch/mips/bcm63xx/Kconfig ++++ b/arch/mips/bcm63xx/Kconfig +@@ -72,6 +72,8 @@ config BCM63XX_CPU_63268 + bool "support 63268 CPU" + select SYS_HAS_CPU_BMIPS4350 + select HW_HAS_PCI ++ select BCM63XX_OHCI ++ select BCM63XX_EHCI + endmenu + + source "arch/mips/bcm63xx/boards/Kconfig" +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -82,7 +82,7 @@ static struct platform_device bcm63xx_eh + int __init bcm63xx_ehci_register(void) + { + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && +- !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) ++ !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return 0; + + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); +--- a/arch/mips/bcm63xx/usb-common.c ++++ b/arch/mips/bcm63xx/usb-common.c +@@ -109,9 +109,24 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_63268()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ reg &= ~USBH_PRIV_SETUP_IPP_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG); ++ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN | ++ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY); ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG); + } else if (BCMCPU_IS_6318()) { + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); +@@ -124,7 +139,7 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); +@@ -165,9 +180,24 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); + reg |= USBH_PRIV_SETUP_IOC_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ } else if (BCMCPU_IS_63268()) { ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); ++ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; ++ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); ++ reg |= USBH_PRIV_SETUP_IOC_MASK; ++ reg &= ~USBH_PRIV_SETUP_IPP_MASK; ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); ++ ++ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG); ++ reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN | ++ USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY); ++ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG); + } else if (BCMCPU_IS_6318()) { + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; ++ reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); +@@ -180,7 +210,7 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); +- reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; ++ reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); diff --git a/target/linux/brcm63xx/patches-4.1/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch b/target/linux/brcm63xx/patches-4.1/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch new file mode 100644 index 0000000..974c67f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch @@ -0,0 +1,108 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -41,6 +41,7 @@ struct board_info { + + /* USB config */ + struct bcm63xx_usbd_platform_data usbd; ++ unsigned int num_usbh_ports:2; + + /* DSP config */ + struct bcm63xx_dsp_platform_data dsp; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h +@@ -1,6 +1,6 @@ + #ifndef BCM63XX_DEV_USB_EHCI_H_ + #define BCM63XX_DEV_USB_EHCI_H_ + +-int bcm63xx_ehci_register(void); ++int bcm63xx_ehci_register(unsigned int num_ports); + + #endif /* BCM63XX_DEV_USB_EHCI_H_ */ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h +@@ -1,6 +1,6 @@ + #ifndef BCM63XX_DEV_USB_OHCI_H_ + #define BCM63XX_DEV_USB_OHCI_H_ + +-int bcm63xx_ohci_register(void); ++int bcm63xx_ohci_register(unsigned int num_ports); + + #endif /* BCM63XX_DEV_USB_OHCI_H_ */ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -166,6 +166,8 @@ static struct platform_device bcm63xx_gp + */ + int __init board_register_devices(void) + { ++ int usbh_ports = 0; ++ + if (board.has_uart0) + bcm63xx_uart_register(0); + +@@ -187,14 +189,21 @@ int __init board_register_devices(void) + !board_get_mac_address(board.enetsw.mac_addr)) + bcm63xx_enetsw_register(&board.enetsw); + ++ if ((board.has_ohci0 || board.has_ehci0)) { ++ usbh_ports = board.num_usbh_ports; ++ ++ if (!usbh_ports || WARN_ON(usbh_ports > 1 && board.has_usbd)) ++ usbh_ports = 1; ++ } ++ + if (board.has_usbd) + bcm63xx_usbd_register(&board.usbd); + + if (board.has_ehci0) +- bcm63xx_ehci_register(); ++ bcm63xx_ehci_register(usbh_ports); + + if (board.has_ohci0) +- bcm63xx_ohci_register(); ++ bcm63xx_ohci_register(usbh_ports); + + if (board.has_dsp) + bcm63xx_dsp_register(&board.dsp); +--- a/arch/mips/bcm63xx/dev-usb-ehci.c ++++ b/arch/mips/bcm63xx/dev-usb-ehci.c +@@ -79,12 +79,14 @@ static struct platform_device bcm63xx_eh + }, + }; + +-int __init bcm63xx_ehci_register(void) ++int __init bcm63xx_ehci_register(unsigned int num_ports) + { + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && + !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) + return 0; + ++ bcm63xx_ehci_pdata.num_ports = num_ports; ++ + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); + ehci_resources[0].end = ehci_resources[0].start; + ehci_resources[0].end += RSET_EHCI_SIZE - 1; +--- a/arch/mips/bcm63xx/dev-usb-ohci.c ++++ b/arch/mips/bcm63xx/dev-usb-ohci.c +@@ -62,7 +62,6 @@ static struct usb_ohci_pdata bcm63xx_ohc + .big_endian_desc = 1, + .big_endian_mmio = 1, + .no_big_frame_no = 1, +- .num_ports = 1, + .power_on = bcm63xx_ohci_power_on, + .power_off = bcm63xx_ohci_power_off, + .power_suspend = bcm63xx_ohci_power_off, +@@ -80,11 +79,13 @@ static struct platform_device bcm63xx_oh + }, + }; + +-int __init bcm63xx_ohci_register(void) ++int __init bcm63xx_ohci_register(unsigned int num_ports) + { + if (BCMCPU_IS_6345() || BCMCPU_IS_6338()) + return -ENODEV; + ++ bcm63xx_ohci_pdata.num_ports = num_ports; ++ + ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0); + ohci_resources[0].end = ohci_resources[0].start; + ohci_resources[0].end += RSET_OHCI_SIZE - 1; diff --git a/target/linux/brcm63xx/patches-4.1/351-set-board-usbh-ports.patch b/target/linux/brcm63xx/patches-4.1/351-set-board-usbh-ports.patch new file mode 100644 index 0000000..51cb29d --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/351-set-board-usbh-ports.patch @@ -0,0 +1,10 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -591,6 +591,7 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, ++ .num_usbh_ports = 2, + + .leds = { + { diff --git a/target/linux/brcm63xx/patches-4.1/354-MIPS-BCM63XX-allow-building-support-for-more-than-on.patch b/target/linux/brcm63xx/patches-4.1/354-MIPS-BCM63XX-allow-building-support-for-more-than-on.patch new file mode 100644 index 0000000..125ac83 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/354-MIPS-BCM63XX-allow-building-support-for-more-than-on.patch @@ -0,0 +1,95 @@ +From 0daf361ea799fba0af5a232036d0f06cea85ad24 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Jun 2014 12:47:49 +0200 +Subject: [PATCH 42/44] MIPS: BCM63XX: allow building support for more than one + board type + +Use the arguments passed to the kernel to detect being booted with +CFE as the indicator for bcm963xx board support, allowing the +non presence of CFE_EPTSEAL to assume a different board type. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/Kconfig | 7 +++---- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/boards/board_common.c | 13 +++++++++++++ + arch/mips/bcm63xx/boards/board_common.h | 6 ++++++ + 4 files changed, 23 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -1,11 +1,10 @@ +-choice +- prompt "Board support" ++menu "Board support" + depends on BCM63XX +- default BOARD_BCM963XX + + config BOARD_BCM963XX + bool "Generic Broadcom 963xx boards" + select SSB ++ default y + help + +-endchoice ++endmenu +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -701,7 +701,7 @@ static const struct board_info __initcon + /* + * early init callback, read nvram data from flash and checksum it + */ +-void __init board_prom_init(void) ++void __init board_bcm963xx_init(void) + { + unsigned int i; + u8 *boot_addr, *cfe; +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -14,6 +14,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -31,6 +33,8 @@ + #include + #include + ++#include "board_common.h" ++ + #define PFX "board: " + + static struct board_info board; +@@ -81,6 +85,15 @@ const char *board_get_name(void) + return board.name; + } + ++void __init board_prom_init(void) ++{ ++ /* detect bootloader */ ++ if (fw_arg3 == CFE_EPTSEAL) ++ board_bcm963xx_init(); ++ else ++ panic("unsupported bootloader detected"); ++} ++ + static int (*board_get_mac_address)(u8 mac[ETH_ALEN]); + + /* +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -6,4 +6,10 @@ + void board_early_setup(const struct board_info *board, + int (*get_mac_address)(u8 mac[ETH_ALEN])); + ++#if defined(CONFIG_BOARD_BCM963XX) ++void board_bcm963xx_init(void); ++#else ++static inline void board_bcm963xx_init(void) { } ++#endif ++ + #endif /* __BOARD_COMMON_H */ diff --git a/target/linux/brcm63xx/patches-4.1/355-MIPS-BCM63XX-allow-board-implementations-to-force-fl.patch b/target/linux/brcm63xx/patches-4.1/355-MIPS-BCM63XX-allow-board-implementations-to-force-fl.patch new file mode 100644 index 0000000..bdbba03 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/355-MIPS-BCM63XX-allow-board-implementations-to-force-fl.patch @@ -0,0 +1,61 @@ +From 8a30097a899b975709f728666d5ad20c8b832d21 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Mar 2014 04:28:14 +0100 +Subject: [PATCH 43/44] MIPS: BCM63XX: allow board implementations to force + flash address + +Allow board implementations to force the physmap address. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 19 ++++++++++++++----- + .../mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++ + 2 files changed, 16 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -58,6 +58,12 @@ static struct platform_device mtd_dev = + }, + }; + ++void __init bcm63xx_flash_force_phys_base_address(u32 start, u32 end) ++{ ++ mtd_resources[0].start = start; ++ mtd_resources[0].end = end; ++} ++ + static int __init bcm63xx_detect_flash_type(void) + { + u32 val; +@@ -172,12 +178,15 @@ int __init bcm63xx_flash_register(void) + + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: +- /* read base address of boot chip select (0) */ +- val = bcm_mpi_readl(MPI_CSBASE_REG(0)); +- val &= MPI_CSBASE_BASE_MASK; + +- mtd_resources[0].start = val; +- mtd_resources[0].end = 0x1FFFFFFF; ++ if (!mtd_resources[0].start) { ++ /* read base address of boot chip select (0) */ ++ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); ++ val &= MPI_CSBASE_BASE_MASK; ++ ++ mtd_resources[0].start = val; ++ mtd_resources[0].end = 0x1FFFFFFF; ++ } + + return platform_device_register(&mtd_dev); + case BCM63XX_FLASH_TYPE_SERIAL: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -9,6 +9,8 @@ enum { + + void bcm63xx_flash_detect(void); + ++void bcm63xx_flash_force_phys_base_address(u32 start, u32 end); ++ + int __init bcm63xx_flash_register(void); + + #endif /* __BCM63XX_FLASH_H */ diff --git a/target/linux/brcm63xx/patches-4.1/356-MIPS-BCM63XX-move-fallback-sprom-support-into-its-ow.patch b/target/linux/brcm63xx/patches-4.1/356-MIPS-BCM63XX-move-fallback-sprom-support-into-its-ow.patch new file mode 100644 index 0000000..cec6c7e --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/356-MIPS-BCM63XX-move-fallback-sprom-support-into-its-ow.patch @@ -0,0 +1,188 @@ +From cc025e749a1fece61a6cc0d64bbe7b12472259cc Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 21:31:12 +0200 +Subject: [PATCH 01/10] MIPS: BCM63XX: move fallback sprom support into its own + unit + +In preparation for enhancing it, move it into its own file. Require a +mac address to be passed as the argument to always "reserve" the mac +regardless of the inclusion state of SSB. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/boards/board_common.c | 53 ++-------------- + arch/mips/bcm63xx/sprom.c | 70 ++++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 6 ++ + 4 files changed, 83 insertions(+), 48 deletions(-) + create mode 100644 arch/mips/bcm63xx/sprom.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ + dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ +- usb-common.o ++ usb-common.o sprom.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -40,44 +40,6 @@ + static struct board_info board; + + /* +- * Register a sane SPROMv2 to make the on-board +- * bcm4318 WLAN work +- */ +-#ifdef CONFIG_SSB_PCIHOST +-static struct ssb_sprom bcm63xx_sprom = { +- .revision = 0x02, +- .board_rev = 0x17, +- .country_code = 0x0, +- .ant_available_bg = 0x3, +- .pa0b0 = 0x15ae, +- .pa0b1 = 0xfa85, +- .pa0b2 = 0xfe8d, +- .pa1b0 = 0xffff, +- .pa1b1 = 0xffff, +- .pa1b2 = 0xffff, +- .gpio0 = 0xff, +- .gpio1 = 0xff, +- .gpio2 = 0xff, +- .gpio3 = 0xff, +- .maxpwr_bg = 0x004c, +- .itssi_bg = 0x00, +- .boardflags_lo = 0x2848, +- .boardflags_hi = 0x0000, +-}; +- +-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +-{ +- if (bus->bustype == SSB_BUSTYPE_PCI) { +- memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); +- return 0; +- } else { +- printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); +- return -EINVAL; +- } +-} +-#endif +- +-/* + * return board name for /proc/cpuinfo + */ + const char *board_get_name(void) +@@ -180,6 +142,7 @@ static struct platform_device bcm63xx_gp + int __init board_register_devices(void) + { + int usbh_ports = 0; ++ u8 mac[ETH_ALEN]; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -224,15 +187,10 @@ int __init board_register_devices(void) + /* Generate MAC address for WLAN and register our SPROM, + * do this after registering enet devices + */ +-#ifdef CONFIG_SSB_PCIHOST +- if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { +- memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); +- memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); +- if (ssb_arch_register_fallback_sprom( +- &bcm63xx_get_fallback_sprom) < 0) +- pr_err(PFX "failed to register fallback SPROM\n"); +- } +-#endif ++ ++ if (board_get_mac_address(mac) || ++ bcm63xx_register_fallback_sprom(mac)) ++ pr_err(PFX "failed to register fallback SPROM\n"); + + bcm63xx_spi_register(); + +--- /dev/null ++++ b/arch/mips/bcm63xx/sprom.c +@@ -0,0 +1,70 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Maxime Bizon ++ * Copyright (C) 2008 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PFX "sprom: " ++ ++/* ++ * Register a sane SPROMv2 to make the on-board ++ * bcm4318 WLAN work ++ */ ++#ifdef CONFIG_SSB_PCIHOST ++static struct ssb_sprom bcm63xx_sprom = { ++ .revision = 0x02, ++ .board_rev = 0x17, ++ .country_code = 0x0, ++ .ant_available_bg = 0x3, ++ .pa0b0 = 0x15ae, ++ .pa0b1 = 0xfa85, ++ .pa0b2 = 0xfe8d, ++ .pa1b0 = 0xffff, ++ .pa1b1 = 0xffff, ++ .pa1b2 = 0xffff, ++ .gpio0 = 0xff, ++ .gpio1 = 0xff, ++ .gpio2 = 0xff, ++ .gpio3 = 0xff, ++ .maxpwr_bg = 0x004c, ++ .itssi_bg = 0x00, ++ .boardflags_lo = 0x2848, ++ .boardflags_hi = 0x0000, ++}; ++ ++int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) ++{ ++ if (bus->bustype == SSB_BUSTYPE_PCI) { ++ memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ return 0; ++ } else { ++ printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); ++ return -EINVAL; ++ } ++} ++#endif ++ ++int __init bcm63xx_register_fallback_sprom(u8 *mac) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_SSB_PCIHOST ++ memcpy(bcm63xx_sprom.il0mac, mac, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et0mac, mac, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et1mac, mac, ETH_ALEN); ++ ++ ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom); ++#endif ++ return ret; ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -0,0 +1,6 @@ ++#ifndef __BCM63XX_FALLBACK_SPROM ++#define __BCM63XX_FALLBACK_SPROM ++ ++int bcm63xx_register_fallback_sprom(u8 *mac); ++ ++#endif diff --git a/target/linux/brcm63xx/patches-4.1/357-MIPS-BCM63XX-use-platform-data-for-the-sprom.patch b/target/linux/brcm63xx/patches-4.1/357-MIPS-BCM63XX-use-platform-data-for-the-sprom.patch new file mode 100644 index 0000000..cdee70c --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/357-MIPS-BCM63XX-use-platform-data-for-the-sprom.patch @@ -0,0 +1,95 @@ +From 9912a8b3c240a9b0af01ff496b7e8ed9e4cc5b82 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 21:43:49 +0200 +Subject: [PATCH 02/10] MIPS: BCM63XX: use platform data for the sprom + +Similar to ethernet setup, use a platform data struct for passing +the mac. This eliminates the requirement to allocate an array on +stack for the mac passed. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_common.c | 6 ++---- + arch/mips/bcm63xx/sprom.c | 8 ++++---- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 8 +++++++- + arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 4 ++++ + 4 files changed, 17 insertions(+), 9 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -142,7 +142,6 @@ static struct platform_device bcm63xx_gp + int __init board_register_devices(void) + { + int usbh_ports = 0; +- u8 mac[ETH_ALEN]; + + if (board.has_uart0) + bcm63xx_uart_register(0); +@@ -188,8 +187,8 @@ int __init board_register_devices(void) + * do this after registering enet devices + */ + +- if (board_get_mac_address(mac) || +- bcm63xx_register_fallback_sprom(mac)) ++ if (board_get_mac_address(board.fallback_sprom.mac_addr) || ++ bcm63xx_register_fallback_sprom(&board.fallback_sprom)) + pr_err(PFX "failed to register fallback SPROM\n"); + + bcm63xx_spi_register(); +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -55,14 +55,14 @@ int bcm63xx_get_fallback_sprom(struct ss + } + #endif + +-int __init bcm63xx_register_fallback_sprom(u8 *mac) ++int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data) + { + int ret = 0; + + #ifdef CONFIG_SSB_PCIHOST +- memcpy(bcm63xx_sprom.il0mac, mac, ETH_ALEN); +- memcpy(bcm63xx_sprom.et0mac, mac, ETH_ALEN); +- memcpy(bcm63xx_sprom.et1mac, mac, ETH_ALEN); ++ memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); ++ memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); + + ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom); + #endif +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -1,6 +1,12 @@ + #ifndef __BCM63XX_FALLBACK_SPROM + #define __BCM63XX_FALLBACK_SPROM + +-int bcm63xx_register_fallback_sprom(u8 *mac); ++#include ++ ++struct fallback_sprom_data { ++ u8 mac_addr[ETH_ALEN]; ++}; ++ ++int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data); + + #endif +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + + /* + * flash mapping +@@ -55,6 +56,9 @@ struct board_info { + /* External PHY reset GPIO flags from gpio.h */ + unsigned long ephy_reset_gpio_flags; + ++ /* fallback sprom config */ ++ struct fallback_sprom_data fallback_sprom; ++ + /* Additional platform devices */ + struct platform_device **devs; + unsigned int num_devs; diff --git a/target/linux/brcm63xx/patches-4.1/358-MIPS-BCM63XX-make-fallback-sprom-optional.patch b/target/linux/brcm63xx/patches-4.1/358-MIPS-BCM63XX-make-fallback-sprom-optional.patch new file mode 100644 index 0000000..a890ab5 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/358-MIPS-BCM63XX-make-fallback-sprom-optional.patch @@ -0,0 +1,140 @@ +From 83131acbfb59760a19f3711c09526e191c8aad54 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 21:52:56 +0200 +Subject: [PATCH 03/10] MIPS: BCM63XX: make fallback sprom optional + +Some devices do not provide enough mac addresses to populate wifi in +addition to ethernet. + +Use having pci enabled as a rough heuristic which boards should have it +enabled. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 12 ++++++++++++ + arch/mips/bcm63xx/boards/board_common.c | 5 +++-- + arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 1 + + 3 files changed, 16 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -69,6 +69,7 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_pci = 1, + .has_usbd = 0, ++ .use_fallback_sprom = 1, + + .usbd = { + .use_fullspeed = 0, +@@ -218,6 +219,7 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_enet0 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -263,6 +265,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -323,6 +326,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -377,6 +381,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -435,6 +440,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -458,6 +464,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -476,6 +483,7 @@ static struct board_info __initdata boar + + .has_uart0 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + .has_ohci0 = 1, + + .has_enet0 = 1, +@@ -498,6 +506,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -524,6 +533,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -576,6 +586,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +@@ -647,6 +658,7 @@ static struct board_info __initdata boar + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, ++ .use_fallback_sprom = 1, + + .enet0 = { + .has_phy = 1, +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -187,8 +187,9 @@ int __init board_register_devices(void) + * do this after registering enet devices + */ + +- if (board_get_mac_address(board.fallback_sprom.mac_addr) || +- bcm63xx_register_fallback_sprom(&board.fallback_sprom)) ++ if (board.use_fallback_sprom && ++ (board_get_mac_address(board.fallback_sprom.mac_addr) || ++ bcm63xx_register_fallback_sprom(&board.fallback_sprom))) + pr_err(PFX "failed to register fallback SPROM\n"); + + bcm63xx_spi_register(); +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -34,6 +34,7 @@ struct board_info { + unsigned int has_dsp:1; + unsigned int has_uart0:1; + unsigned int has_uart1:1; ++ unsigned int use_fallback_sprom:1; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; diff --git a/target/linux/brcm63xx/patches-4.1/359-MIPS-BCM63XX-allow-different-types-of-sprom.patch b/target/linux/brcm63xx/patches-4.1/359-MIPS-BCM63XX-allow-different-types-of-sprom.patch new file mode 100644 index 0000000..0c4a9be --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/359-MIPS-BCM63XX-allow-different-types-of-sprom.patch @@ -0,0 +1,66 @@ +From 1cece9f7aca1f0c193edce201f77a87008c5a405 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 21:58:38 +0200 +Subject: [PATCH 04/10] MIPS: BCM63XX: allow different types of sprom + +Different chips require different sprom contents, so prepare for +supplying the appropriate sprom type. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 13 ++++++++++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 5 +++++ + 2 files changed, 17 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -22,7 +22,7 @@ + * bcm4318 WLAN work + */ + #ifdef CONFIG_SSB_PCIHOST +-static struct ssb_sprom bcm63xx_sprom = { ++static __initconst struct ssb_sprom bcm63xx_default_sprom = { + .revision = 0x02, + .board_rev = 0x17, + .country_code = 0x0, +@@ -43,6 +43,8 @@ static struct ssb_sprom bcm63xx_sprom = + .boardflags_hi = 0x0000, + }; + ++static struct ssb_sprom bcm63xx_sprom; ++ + int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) + { + if (bus->bustype == SSB_BUSTYPE_PCI) { +@@ -60,6 +62,15 @@ int __init bcm63xx_register_fallback_spr + int ret = 0; + + #ifdef CONFIG_SSB_PCIHOST ++ switch (data->type) { ++ case SPROM_DEFAULT: ++ memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, ++ sizeof(bcm63xx_sprom)); ++ break; ++ default: ++ return -EINVAL; ++ } ++ + memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -3,8 +3,13 @@ + + #include + ++enum sprom_type { ++ SPROM_DEFAULT, /* default fallback sprom */ ++}; ++ + struct fallback_sprom_data { + u8 mac_addr[ETH_ALEN]; ++ enum sprom_type type; + }; + + int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data); diff --git a/target/linux/brcm63xx/patches-4.1/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch b/target/linux/brcm63xx/patches-4.1/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch new file mode 100644 index 0000000..42502eb --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch @@ -0,0 +1,517 @@ +From cedee63bc73f8b7d45b8c0cba1236986812c1f83 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 22:16:36 +0200 +Subject: [PATCH 05/10] MIPS: BCM63XX: add support for "raw" sproms + +Allow using raw sprom content as templates. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 482 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 482 insertions(+) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -55,13 +55,492 @@ int bcm63xx_get_fallback_sprom(struct ss + return -EINVAL; + } + } ++ ++/* FIXME: use lib_sprom after submission upstream */ ++ ++/* Get the word-offset for a SSB_SPROM_XXX define. */ ++#define SPOFF(offset) ((offset) / sizeof(u16)) ++/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */ ++#define SPEX16(_outvar, _offset, _mask, _shift) \ ++ out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) ++#define SPEX32(_outvar, _offset, _mask, _shift) \ ++ out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \ ++ in[SPOFF(_offset)]) & (_mask)) >> (_shift)) ++#define SPEX(_outvar, _offset, _mask, _shift) \ ++ SPEX16(_outvar, _offset, _mask, _shift) ++ ++#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ ++ do { \ ++ SPEX(_field[0], _offset + 0, _mask, _shift); \ ++ SPEX(_field[1], _offset + 2, _mask, _shift); \ ++ SPEX(_field[2], _offset + 4, _mask, _shift); \ ++ SPEX(_field[3], _offset + 6, _mask, _shift); \ ++ SPEX(_field[4], _offset + 8, _mask, _shift); \ ++ SPEX(_field[5], _offset + 10, _mask, _shift); \ ++ SPEX(_field[6], _offset + 12, _mask, _shift); \ ++ SPEX(_field[7], _offset + 14, _mask, _shift); \ ++ } while (0) ++ ++ ++static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in, ++ u16 mask, u16 shift) ++{ ++ u16 v; ++ u8 gain; ++ ++ v = in[SPOFF(SSB_SPROM1_AGAIN)]; ++ gain = (v & mask) >> shift; ++ if (gain == 0xFF) ++ gain = 2; /* If unset use 2dBm */ ++ if (sprom_revision == 1) { ++ /* Convert to Q5.2 */ ++ gain <<= 2; ++ } else { ++ /* Q5.2 Fractional part is stored in 0xC0 */ ++ gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2); ++ } ++ ++ return (s8)gain; ++} ++ ++static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0); ++ SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0); ++ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0); ++ SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0); ++ SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO, ++ SSB_SPROM2_MAXP_A_LO_SHIFT); ++} ++ ++static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in) ++{ ++ u16 loc[3]; ++ ++ if (out->revision == 3) /* rev 3 moved MAC */ ++ loc[0] = SSB_SPROM3_IL0MAC; ++ else { ++ loc[0] = SSB_SPROM1_IL0MAC; ++ loc[1] = SSB_SPROM1_ET0MAC; ++ loc[2] = SSB_SPROM1_ET1MAC; ++ } ++ ++ SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0); ++ SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A, ++ SSB_SPROM1_ETHPHY_ET1A_SHIFT); ++ SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14); ++ SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15); ++ SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); ++ if (out->revision == 1) ++ SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE, ++ SSB_SPROM1_BINF_CCODE_SHIFT); ++ SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA, ++ SSB_SPROM1_BINF_ANTA_SHIFT); ++ SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG, ++ SSB_SPROM1_BINF_ANTBG_SHIFT); ++ SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0); ++ SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0); ++ SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0); ++ SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0); ++ SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0); ++ SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0); ++ SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1, ++ SSB_SPROM1_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3, ++ SSB_SPROM1_GPIOB_P3_SHIFT); ++ SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A, ++ SSB_SPROM1_MAXPWR_A_SHIFT); ++ SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0); ++ SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A, ++ SSB_SPROM1_ITSSI_A_SHIFT); ++ SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0); ++ SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0); ++ ++ SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0); ++ ++ /* Extract the antenna gain values. */ ++ out->antenna_gain.a0 = r123_extract_antgain(out->revision, in, ++ SSB_SPROM1_AGAIN_BG, ++ SSB_SPROM1_AGAIN_BG_SHIFT); ++ out->antenna_gain.a1 = r123_extract_antgain(out->revision, in, ++ SSB_SPROM1_AGAIN_A, ++ SSB_SPROM1_AGAIN_A_SHIFT); ++ if (out->revision >= 2) ++ sprom_extract_r23(out, in); ++} ++ ++/* Revs 4 5 and 8 have partially shared layout */ ++static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in) ++{ ++ SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, ++ SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT); ++ SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, ++ SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT); ++ SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, ++ SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT); ++ SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, ++ SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT); ++ ++ SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, ++ SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT); ++ SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, ++ SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT); ++ SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, ++ SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT); ++ SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, ++ SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT); ++ ++ SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, ++ SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT); ++ SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, ++ SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT); ++ SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, ++ SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT); ++ SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, ++ SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT); ++ ++ SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, ++ SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT); ++ SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, ++ SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT); ++ SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, ++ SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT); ++ SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, ++ SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT); ++} ++ ++static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in) ++{ ++ u16 il0mac_offset; ++ ++ if (out->revision == 4) ++ il0mac_offset = SSB_SPROM4_IL0MAC; ++ else ++ il0mac_offset = SSB_SPROM5_IL0MAC; ++ ++ SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0); ++ SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A, ++ SSB_SPROM4_ETHPHY_ET1A_SHIFT); ++ SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); ++ if (out->revision == 4) { ++ SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0); ++ SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0); ++ SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0); ++ SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0); ++ SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0); ++ } else { ++ SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0); ++ SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0); ++ SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0); ++ SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0); ++ SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0); ++ } ++ SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A, ++ SSB_SPROM4_ANTAVAIL_A_SHIFT); ++ SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG, ++ SSB_SPROM4_ANTAVAIL_BG_SHIFT); ++ SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0); ++ SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG, ++ SSB_SPROM4_ITSSI_BG_SHIFT); ++ SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0); ++ SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A, ++ SSB_SPROM4_ITSSI_A_SHIFT); ++ if (out->revision == 4) { ++ SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1, ++ SSB_SPROM4_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3, ++ SSB_SPROM4_GPIOB_P3_SHIFT); ++ } else { ++ SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1, ++ SSB_SPROM5_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3, ++ SSB_SPROM5_GPIOB_P3_SHIFT); ++ } ++ ++ /* Extract the antenna gain values. */ ++ SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01, ++ SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT); ++ SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01, ++ SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT); ++ SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23, ++ SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT); ++ SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23, ++ SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT); ++ ++ sprom_extract_r458(out, in); ++ ++ /* TODO - get remaining rev 4 stuff needed */ ++} ++ ++static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in) ++{ ++ int i; ++ u16 o; ++ u16 pwr_info_offset[] = { ++ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1, ++ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3 ++ }; ++ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) != ++ ARRAY_SIZE(out->core_pwr_info)); ++ ++ SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0); ++ SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0); ++ SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8); ++ SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0); ++ SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0); ++ SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0); ++ SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0); ++ SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0); ++ SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A, ++ SSB_SPROM8_ANTAVAIL_A_SHIFT); ++ SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG, ++ SSB_SPROM8_ANTAVAIL_BG_SHIFT); ++ SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0); ++ SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG, ++ SSB_SPROM8_ITSSI_BG_SHIFT); ++ SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0); ++ SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A, ++ SSB_SPROM8_ITSSI_A_SHIFT); ++ SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0); ++ SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK, ++ SSB_SPROM8_MAXP_AL_SHIFT); ++ SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0); ++ SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1, ++ SSB_SPROM8_GPIOA_P1_SHIFT); ++ SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0); ++ SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3, ++ SSB_SPROM8_GPIOB_P3_SHIFT); ++ SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0); ++ SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G, ++ SSB_SPROM8_TRI5G_SHIFT); ++ SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0); ++ SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH, ++ SSB_SPROM8_TRI5GH_SHIFT); ++ SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0); ++ SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G, ++ SSB_SPROM8_RXPO5G_SHIFT); ++ SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0); ++ SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G, ++ SSB_SPROM8_RSSISMC2G_SHIFT); ++ SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G, ++ SSB_SPROM8_RSSISAV2G_SHIFT); ++ SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G, ++ SSB_SPROM8_BXA2G_SHIFT); ++ SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0); ++ SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G, ++ SSB_SPROM8_RSSISMC5G_SHIFT); ++ SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G, ++ SSB_SPROM8_RSSISAV5G_SHIFT); ++ SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G, ++ SSB_SPROM8_BXA5G_SHIFT); ++ SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0); ++ SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0); ++ SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0); ++ SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0); ++ SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0); ++ SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0); ++ SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0); ++ SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0); ++ SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0); ++ SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0); ++ SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0); ++ SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0); ++ SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0); ++ SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0); ++ SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0); ++ SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0); ++ SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0); ++ ++ /* Extract the antenna gain values. */ ++ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01, ++ SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT); ++ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01, ++ SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT); ++ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23, ++ SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT); ++ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23, ++ SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT); ++ ++ /* Extract cores power info info */ ++ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) { ++ o = pwr_info_offset[i]; ++ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI, ++ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT); ++ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI, ++ SSB_SPROM8_2G_MAXP, 0); ++ ++ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0); ++ ++ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI, ++ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT); ++ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI, ++ SSB_SPROM8_5G_MAXP, 0); ++ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP, ++ SSB_SPROM8_5GH_MAXP, 0); ++ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP, ++ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT); ++ ++ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0); ++ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0); ++ } ++ ++ /* Extract FEM info */ ++ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT); ++ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT); ++ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT); ++ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT); ++ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, ++ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT); ++ ++ SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON, ++ SSB_SPROM8_LEDDC_ON_SHIFT); ++ SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF, ++ SSB_SPROM8_LEDDC_OFF_SHIFT); ++ ++ SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN, ++ SSB_SPROM8_TXRXC_TXCHAIN_SHIFT); ++ SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN, ++ SSB_SPROM8_TXRXC_RXCHAIN_SHIFT); ++ SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH, ++ SSB_SPROM8_TXRXC_SWITCH_SHIFT); ++ ++ SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0); ++ ++ SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0); ++ SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0); ++ ++ SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP, ++ SSB_SPROM8_RAWTS_RAWTEMP_SHIFT); ++ SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER, ++ SSB_SPROM8_RAWTS_MEASPOWER_SHIFT); ++ SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX, ++ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE, ++ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT); ++ SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX, ++ SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT); ++ SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX, ++ SSB_SPROM8_OPT_CORRX_TEMP_OPTION, ++ SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT); ++ SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP, ++ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR, ++ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT); ++ SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP, ++ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP, ++ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT); ++ SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL, ++ SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT); ++ ++ SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0); ++ SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0); ++ SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0); ++ SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0); ++ ++ SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH, ++ SSB_SPROM8_THERMAL_TRESH_SHIFT); ++ SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET, ++ SSB_SPROM8_THERMAL_OFFSET_SHIFT); ++ SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA, ++ SSB_SPROM8_TEMPDELTA_PHYCAL, ++ SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT); ++ SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD, ++ SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT); ++ SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA, ++ SSB_SPROM8_TEMPDELTA_HYSTERESIS, ++ SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT); ++ sprom_extract_r458(out, in); ++ ++ /* TODO - get remaining rev 8 stuff needed */ ++} ++ ++static int sprom_extract(struct ssb_sprom *out, const u16 *in, u16 size) ++{ ++ memset(out, 0, sizeof(*out)); ++ ++ out->revision = in[size - 1] & 0x00FF; ++ memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */ ++ memset(out->et1mac, 0xFF, 6); ++ ++ switch (out->revision) { ++ case 1: ++ case 2: ++ case 3: ++ sprom_extract_r123(out, in); ++ break; ++ case 4: ++ case 5: ++ sprom_extract_r45(out, in); ++ break; ++ case 8: ++ sprom_extract_r8(out, in); ++ break; ++ default: ++ pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n", ++ out->revision); ++ out->revision = 1; ++ sprom_extract_r123(out, in); ++ } ++ ++ if (out->boardflags_lo == 0xFFFF) ++ out->boardflags_lo = 0; /* per specs */ ++ if (out->boardflags_hi == 0xFFFF) ++ out->boardflags_hi = 0; /* per specs */ ++ ++ return 0; ++} ++ ++static __initdata u16 template_sprom[220]; + #endif + ++ + int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data) + { + int ret = 0; + + #ifdef CONFIG_SSB_PCIHOST ++ u16 size = 0; ++ + switch (data->type) { + case SPROM_DEFAULT: + memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, +@@ -71,6 +550,9 @@ int __init bcm63xx_register_fallback_spr + return -EINVAL; + } + ++ if (size > 0) ++ sprom_extract(&bcm63xx_sprom, template_sprom, size); ++ + memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); diff --git a/target/linux/brcm63xx/patches-4.1/361-MIPS-BCM63XX-add-raw-fallback-sproms-for-most-common.patch b/target/linux/brcm63xx/patches-4.1/361-MIPS-BCM63XX-add-raw-fallback-sproms-for-most-common.patch new file mode 100644 index 0000000..65c00b5 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/361-MIPS-BCM63XX-add-raw-fallback-sproms-for-most-common.patch @@ -0,0 +1,181 @@ +From 7be5bb46003295c9e04fd4e795593b2deaacd783 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 22:33:38 +0200 +Subject: [PATCH 06/10] MIPS: BCM63XX: add raw fallback sproms for most common + ssb cards + +Add template sproms for BCM4306, BCM4318, BCM4321, BCM4322, and BCM43222. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 136 +++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 6 + + 2 files changed, 142 insertions(+) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -43,6 +43,122 @@ static __initconst struct ssb_sprom bcm6 + .boardflags_hi = 0x0000, + }; + ++ ++static __initconst u16 bcm4306_sprom[] = { ++ 0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002, ++ 0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3034, 0x14d4, ++ 0xfa91, 0xfe60, 0xffff, 0xffff, 0x004c, 0xffff, 0xffff, 0xffff, ++ 0x003e, 0x0a49, 0xff02, 0x0000, 0xff10, 0xffff, 0xffff, 0x0002, ++}; ++ ++static __initconst u16 bcm4318_sprom[] = { ++ 0x2001, 0x0000, 0x0449, 0x14e4, 0x4318, 0x8000, 0x0002, 0x0000, ++ 0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3046, 0x15a7, ++ 0xfab0, 0xfe97, 0xffff, 0xffff, 0x0048, 0xffff, 0xffff, 0xffff, ++ 0x003e, 0xea49, 0xff02, 0x0000, 0xff08, 0xffff, 0xffff, 0x0002, ++}; ++ ++static __initconst u16 bcm4321_sprom[] = { ++ 0x3001, 0x0000, 0x046c, 0x14e4, 0x4328, 0x8000, 0x0002, 0x0000, ++ 0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x0032, 0x4a01, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x2728, 0x5b5b, 0x222b, 0x5b5b, 0x1927, 0x5b5b, 0x1e36, ++ 0x5b5b, 0x303c, 0x3030, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x3e4c, 0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0x3e4c, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0x0008, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0004, ++}; ++ ++static __initconst u16 bcm4322_sprom[] = { ++ 0x3001, 0x0000, 0x04bc, 0x14e4, 0x432c, 0x8000, 0x0002, 0x0000, ++ 0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x1209, 0x0200, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0301, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x2048, 0xfe9a, 0x1571, 0xfabd, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x2048, 0xfeb9, 0x159f, 0xfadd, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x3333, 0x5555, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ ++static __initconst u16 bcm43222_sprom[] = { ++ 0x2001, 0x0000, 0x04d4, 0x14e4, 0x4351, 0x8000, 0x0002, 0x0000, ++ 0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x2305, 0x0200, 0x0000, 0x2400, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x204c, 0xfea6, 0x1717, 0xfa6d, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x204c, 0xfeb8, 0x167c, 0xfa9e, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x3333, 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, ++ 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ + static struct ssb_sprom bcm63xx_sprom; + + int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) +@@ -542,6 +658,26 @@ int __init bcm63xx_register_fallback_spr + u16 size = 0; + + switch (data->type) { ++ case SPROM_BCM4306: ++ memcpy(&template_sprom, &bcm4306_sprom, sizeof(bcm4306_sprom)); ++ size = ARRAY_SIZE(bcm4306_sprom); ++ break; ++ case SPROM_BCM4318: ++ memcpy(&template_sprom, &bcm4318_sprom, sizeof(bcm4318_sprom)); ++ size = ARRAY_SIZE(bcm4318_sprom); ++ break; ++ case SPROM_BCM4321: ++ memcpy(&template_sprom, &bcm4321_sprom, sizeof(bcm4321_sprom)); ++ size = ARRAY_SIZE(bcm4321_sprom); ++ break; ++ case SPROM_BCM4322: ++ memcpy(&template_sprom, &bcm4322_sprom, sizeof(bcm4322_sprom)); ++ size = ARRAY_SIZE(bcm4322_sprom); ++ break; ++ case SPROM_BCM43222: ++ memcpy(&template_sprom, &bcm43222_sprom, sizeof(bcm43222_sprom)); ++ size = ARRAY_SIZE(bcm43222_sprom); ++ break; + case SPROM_DEFAULT: + memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, + sizeof(bcm63xx_sprom)); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -5,6 +5,12 @@ + + enum sprom_type { + SPROM_DEFAULT, /* default fallback sprom */ ++ /* SSB based */ ++ SPROM_BCM4306, ++ SPROM_BCM4318, ++ SPROM_BCM4321, ++ SPROM_BCM4322, ++ SPROM_BCM43222, + }; + + struct fallback_sprom_data { diff --git a/target/linux/brcm63xx/patches-4.1/362-MIPS-BCM63XX-also-register-a-fallback-sprom-for-bcma.patch b/target/linux/brcm63xx/patches-4.1/362-MIPS-BCM63XX-also-register-a-fallback-sprom-for-bcma.patch new file mode 100644 index 0000000..6475f9f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/362-MIPS-BCM63XX-also-register-a-fallback-sprom-for-bcma.patch @@ -0,0 +1,128 @@ +From 03feb9db77fba3eef3d83e17a87a56979659b248 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 Jul 2014 22:48:26 +0200 +Subject: [PATCH 07/10] MIPS: BCM63XX: also register a fallback sprom for bcma + +Similar to SSB, register a fallback sprom handler for BCMA. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/Kconfig | 1 + + arch/mips/bcm63xx/sprom.c | 40 +++++++++++++++++++++++++++++++++++----- + 2 files changed, 36 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -4,6 +4,7 @@ menu "Board support" + config BOARD_BCM963XX + bool "Generic Broadcom 963xx boards" + select SSB ++ select BCMA + default y + help + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -21,7 +22,7 @@ + * Register a sane SPROMv2 to make the on-board + * bcm4318 WLAN work + */ +-#ifdef CONFIG_SSB_PCIHOST ++#if defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) + static __initconst struct ssb_sprom bcm63xx_default_sprom = { + .revision = 0x02, + .board_rev = 0x17, +@@ -43,7 +44,7 @@ static __initconst struct ssb_sprom bcm6 + .boardflags_hi = 0x0000, + }; + +- ++#if defined (CONFIG_SSB_PCIHOST) + static __initconst u16 bcm4306_sprom[] = { + 0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002, + 0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, +@@ -158,10 +159,12 @@ static __initconst u16 bcm43222_sprom[] + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0x0008, + }; ++#endif /* CONFIG_SSB_PCIHOST */ + + static struct ssb_sprom bcm63xx_sprom; + +-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out) ++#if defined(CONFIG_SSB_PCIHOST) ++int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out) + { + if (bus->bustype == SSB_BUSTYPE_PCI) { + memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); +@@ -171,6 +174,20 @@ int bcm63xx_get_fallback_sprom(struct ss + return -EINVAL; + } + } ++#endif ++ ++#if defined(CONFIG_BCMA_HOST_PCI) ++int bcm63xx_get_fallback_bcma_sprom(struct bcma_bus *bus, struct ssb_sprom *out) ++{ ++ if (bus->hosttype == BCMA_HOSTTYPE_PCI) { ++ memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ return 0; ++ } else { ++ printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); ++ return -EINVAL; ++ } ++} ++#endif + + /* FIXME: use lib_sprom after submission upstream */ + +@@ -654,10 +671,11 @@ int __init bcm63xx_register_fallback_spr + { + int ret = 0; + +-#ifdef CONFIG_SSB_PCIHOST ++#if defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) + u16 size = 0; + + switch (data->type) { ++#if defined(CONFIG_SSB_PCIHOST) + case SPROM_BCM4306: + memcpy(&template_sprom, &bcm4306_sprom, sizeof(bcm4306_sprom)); + size = ARRAY_SIZE(bcm4306_sprom); +@@ -678,6 +696,7 @@ int __init bcm63xx_register_fallback_spr + memcpy(&template_sprom, &bcm43222_sprom, sizeof(bcm43222_sprom)); + size = ARRAY_SIZE(bcm43222_sprom); + break; ++#endif + case SPROM_DEFAULT: + memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, + sizeof(bcm63xx_sprom)); +@@ -692,8 +711,19 @@ int __init bcm63xx_register_fallback_spr + memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); ++#endif /* defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) */ ++ ++#if defined(CONFIG_SSB_PCIHOST) ++ ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_ssb_sprom); ++ if (ret) ++ return ret; ++ ++#endif + +- ret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom); ++#if defined(CONFIG_BCMA_HOST_PCI) ++ ret = bcma_arch_register_fallback_sprom(bcm63xx_get_fallback_bcma_sprom); ++ if (ret) ++ return ret; + #endif + return ret; + } diff --git a/target/linux/brcm63xx/patches-4.1/363-MIPS-BCM63XX-add-BCMA-based-sprom-templates.patch b/target/linux/brcm63xx/patches-4.1/363-MIPS-BCM63XX-add-BCMA-based-sprom-templates.patch new file mode 100644 index 0000000..5c0abb9 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/363-MIPS-BCM63XX-add-BCMA-based-sprom-templates.patch @@ -0,0 +1,303 @@ +From 27bf70e3fe797691b17df07ecbfaf9f5a4419f49 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Wed, 30 Jul 2014 23:14:27 +0200 +Subject: [PATCH 08/10] MIPS: BCM63XX: add BCMA based sprom templates + +Add fallback sproms for BCM4313, BCM43131, BCM43217, BCM43225, BCM43227, +BCM43228, and BCM4331. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 256 +++++++++++++++++++++ + .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 8 + + 2 files changed, 264 insertions(+) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -161,6 +161,226 @@ static __initconst u16 bcm43222_sprom[] + }; + #endif /* CONFIG_SSB_PCIHOST */ + ++#if defined(CONFIG_BCMA_HOST_PCI) ++static __initconst u16 bcm4313_sprom[] = { ++ 0x2801, 0x0000, 0x0510, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x4727, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1215, 0x2a00, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202, ++ 0xffff, 0x0011, 0x007a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0201, ++ 0x0000, 0x7800, 0x7c0a, 0x0398, 0x0008, 0x0000, 0x0000, 0x0000, ++ 0x0044, 0x1684, 0xfd0d, 0xff35, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0048, 0xfed2, 0x15d9, 0xfac6, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0008, ++}; ++ ++static __initconst u16 bcm43131_sprom[] = { ++ 0x2801, 0x0000, 0x05f7, 0x14e4, 0x0070, 0xedbe, 0x1c00, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x43aa, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1280, 0x0200, 0x0000, 0x8800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0002, 0x0202, ++ 0xffff, 0x0022, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415, ++ 0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666, ++ 0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ ++static __initconst u16 bcm43217_sprom[] = { ++ 0x2801, 0x0000, 0x05e9, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x43a9, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1252, 0x0200, 0x0000, 0x9800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202, ++ 0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415, ++ 0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666, ++ 0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x7a08, ++}; ++ ++static __initconst u16 bcm43225_sprom[] = { ++ 0x2801, 0x0000, 0x04da, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0x1008, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x4357, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x1200, 0x0200, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x88ff, 0xffff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325, ++ 0xffff, 0x7800, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x204e, 0xfead, 0x1611, 0xfa9a, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x204e, 0xfec1, 0x1674, 0xfab2, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x5555, 0x5555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555, ++ 0x7555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0002, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ ++static __initconst u16 bcm43227_sprom[] = { ++ 0x2801, 0x0000, 0x0543, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x4358, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1402, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202, ++ 0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415, ++ 0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xff36, 0x16d2, 0xfaae, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xfeca, 0x159b, 0xfa80, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666, ++ 0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0008, ++}; ++ ++static __initconst u16 bcm43228_sprom[] = { ++ 0x2801, 0x0000, 0x0011, 0x1028, 0x0070, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x4359, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x5372, 0x1203, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0303, 0x0202, ++ 0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0215, ++ 0x0215, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x204c, 0xff73, 0x1762, 0xfaa4, 0x3e34, 0x3434, 0xfea1, 0x154c, ++ 0xfad0, 0xfea1, 0x144c, 0xfafb, 0xfe7b, 0x13fe, 0xfafc, 0x0000, ++ 0x204c, 0xff41, 0x16a3, 0xfa8f, 0x3e34, 0x3434, 0xfe97, 0x1446, ++ 0xfb05, 0xfe97, 0x1346, 0xfb32, 0xfeb9, 0x1516, 0xfaee, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x8888, 0x8888, 0x8888, ++ 0x8888, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333, ++ 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333, ++ 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333, ++ 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xf008, ++}; ++ ++static __initconst u16 bcm4331_sprom[] = { ++ 0x2801, 0x0000, 0x0525, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4, ++ 0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820, ++ 0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100, ++ 0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0x1010, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x4331, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x5372, 0x1104, 0x0200, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0xffff, 0x88ff, 0xffff, 0x0707, 0x0202, ++ 0xff02, 0x0077, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325, ++ 0x0325, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x2048, 0xfe56, 0x16f2, 0xfa44, 0x3e3c, 0x3c3c, 0xfe77, 0x1657, ++ 0xfa75, 0xffff, 0xffff, 0xffff, 0xfe76, 0x15da, 0xfa85, 0x0000, ++ 0x2048, 0xfe5c, 0x16b5, 0xfa56, 0x3e3c, 0x3c3c, 0xfe7c, 0x169d, ++ 0xfa6b, 0xffff, 0xffff, 0xffff, 0xfe7a, 0x1597, 0xfa97, 0x0000, ++ 0x2048, 0xfe68, 0x1734, 0xfa46, 0x3e3c, 0x3c3c, 0xfe7f, 0x15e4, ++ 0xfa94, 0xffff, 0xffff, 0xffff, 0xfe7d, 0x1582, 0xfa9f, 0x0000, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, ++ 0xffff, 0xffff, 0xffff, 0x0009, ++}; ++ ++#endif /* CONFIG_BCMA_HOST_PCI */ ++ + static struct ssb_sprom bcm63xx_sprom; + + #if defined(CONFIG_SSB_PCIHOST) +@@ -697,6 +917,42 @@ int __init bcm63xx_register_fallback_spr + size = ARRAY_SIZE(bcm43222_sprom); + break; + #endif ++#if defined(CONFIG_BCMA_HOST_PCI) ++ case SPROM_BCM4313: ++ memcpy(&template_sprom, &bcm4313_sprom, ++ sizeof(bcm4313_sprom)); ++ size = ARRAY_SIZE(bcm4313_sprom); ++ break; ++ case SPROM_BCM43131: ++ memcpy(&template_sprom, &bcm43131_sprom, ++ sizeof(bcm43131_sprom)); ++ size = ARRAY_SIZE(bcm43131_sprom); ++ break; ++ case SPROM_BCM43217: ++ memcpy(&template_sprom, &bcm43217_sprom, ++ sizeof(bcm43217_sprom)); ++ size = ARRAY_SIZE(bcm43217_sprom); ++ break; ++ case SPROM_BCM43225: ++ memcpy(&template_sprom, &bcm43225_sprom, ++ sizeof(bcm43225_sprom)); ++ size = ARRAY_SIZE(bcm43225_sprom); ++ break; ++ case SPROM_BCM43227: ++ memcpy(&template_sprom, &bcm43227_sprom, ++ sizeof(bcm43227_sprom)); ++ size = ARRAY_SIZE(bcm43227_sprom); ++ break; ++ case SPROM_BCM43228: ++ memcpy(&template_sprom, &bcm43228_sprom, ++ sizeof(bcm43228_sprom)); ++ size = ARRAY_SIZE(bcm43228_sprom); ++ break; ++ case SPROM_BCM4331: ++ memcpy(&template_sprom, &bcm4331_sprom, sizeof(&bcm4331_sprom)); ++ size = ARRAY_SIZE(bcm4331_sprom); ++ break; ++#endif + case SPROM_DEFAULT: + memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, + sizeof(bcm63xx_sprom)); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -11,6 +11,14 @@ enum sprom_type { + SPROM_BCM4321, + SPROM_BCM4322, + SPROM_BCM43222, ++ /* BCMA based */ ++ SPROM_BCM4313, ++ SPROM_BCM43131, ++ SPROM_BCM43217, ++ SPROM_BCM43225, ++ SPROM_BCM43227, ++ SPROM_BCM43228, ++ SPROM_BCM4331, + }; + + struct fallback_sprom_data { diff --git a/target/linux/brcm63xx/patches-4.1/364-MIPS-BCM63XX-allow-board-files-to-provide-sprom-fixu.patch b/target/linux/brcm63xx/patches-4.1/364-MIPS-BCM63XX-allow-board-files-to-provide-sprom-fixu.patch new file mode 100644 index 0000000..74c2846 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/364-MIPS-BCM63XX-allow-board-files-to-provide-sprom-fixu.patch @@ -0,0 +1,67 @@ +From 8575548b08e33c9ff4fd540abec09dd177e33682 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 31 Jul 2014 19:12:33 +0200 +Subject: [PATCH 09/10] MIPS: BCM63XX: allow board files to provide sprom + fixups + +Allow board_info files to supply fixups for the base sproms to adapt +them to the actual used sprom contents in case they do not use the +default ones. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 14 +++++++++++++- + .../mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 8 ++++++++ + 2 files changed, 21 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -883,6 +883,14 @@ static int sprom_extract(struct ssb_spro + return 0; + } + ++void sprom_apply_fixups(u16 *sprom, struct sprom_fixup *fixups, int n) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < n; i++) ++ sprom[fixups[i].offset] = fixups[i].value; ++} ++ + static __initdata u16 template_sprom[220]; + #endif + +@@ -961,8 +969,12 @@ int __init bcm63xx_register_fallback_spr + return -EINVAL; + } + +- if (size > 0) ++ if (size > 0) { ++ sprom_apply_fixups(template_sprom, data->board_fixups, ++ data->num_board_fixups); ++ + sprom_extract(&bcm63xx_sprom, template_sprom, size); ++ } + + memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); + memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -21,9 +21,17 @@ enum sprom_type { + SPROM_BCM4331, + }; + ++struct sprom_fixup { ++ u16 offset; ++ u16 value; ++}; ++ + struct fallback_sprom_data { + u8 mac_addr[ETH_ALEN]; + enum sprom_type type; ++ ++ struct sprom_fixup *board_fixups; ++ unsigned int num_board_fixups; + }; + + int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data); diff --git a/target/linux/brcm63xx/patches-4.1/365-MIPS-BCM63XX-allow-setting-a-pci-bus-device-for-fall.patch b/target/linux/brcm63xx/patches-4.1/365-MIPS-BCM63XX-allow-setting-a-pci-bus-device-for-fall.patch new file mode 100644 index 0000000..40591e5 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/365-MIPS-BCM63XX-allow-setting-a-pci-bus-device-for-fall.patch @@ -0,0 +1,102 @@ +From f393eaacf178e7e8a61eb11a96edd7dfb35cb49d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 31 Jul 2014 20:39:44 +0200 +Subject: [PATCH 10/10] MIPS: BCM63XX: allow setting a pci bus/device for + fallback sprom + +Warn if the set pci bus/slot does not match the actual request. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/sprom.c | 31 ++++++++++++++++++---- + .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 3 +++ + 2 files changed, 29 insertions(+), 5 deletions(-) + +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -381,13 +381,25 @@ static __initconst u16 bcm4331_sprom[] = + + #endif /* CONFIG_BCMA_HOST_PCI */ + +-static struct ssb_sprom bcm63xx_sprom; ++struct fallback_sprom_match { ++ u8 pci_bus; ++ u8 pci_dev; ++ struct ssb_sprom sprom; ++}; ++ ++static struct fallback_sprom_match fallback_sprom; + + #if defined(CONFIG_SSB_PCIHOST) + int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out) + { + if (bus->bustype == SSB_BUSTYPE_PCI) { +- memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ if (bus->host_pci->bus->number != fallback_sprom.pci_bus || ++ PCI_SLOT(bus->host_pci->devfn) != fallback_sprom.pci_dev) ++ pr_warn("ssb_fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\n", ++ fallback_sprom.pci_bus, fallback_sprom.pci_dev, ++ bus->host_pci->bus->number, ++ PCI_SLOT(bus->host_pci->devfn)); ++ memcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom)); + return 0; + } else { + printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); +@@ -400,7 +412,13 @@ int bcm63xx_get_fallback_ssb_sprom(struc + int bcm63xx_get_fallback_bcma_sprom(struct bcma_bus *bus, struct ssb_sprom *out) + { + if (bus->hosttype == BCMA_HOSTTYPE_PCI) { +- memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom)); ++ if (bus->host_pci->bus->number != fallback_sprom.pci_bus || ++ PCI_SLOT(bus->host_pci->devfn) != fallback_sprom.pci_dev) ++ pr_warn("bcma_fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\n", ++ fallback_sprom.pci_bus, fallback_sprom.pci_dev, ++ bus->host_pci->bus->number, ++ PCI_SLOT(bus->host_pci->devfn)); ++ memcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom)); + return 0; + } else { + printk(KERN_ERR PFX "unable to fill SPROM for given bustype.\n"); +@@ -962,8 +980,8 @@ int __init bcm63xx_register_fallback_spr + break; + #endif + case SPROM_DEFAULT: +- memcpy(&bcm63xx_sprom, &bcm63xx_default_sprom, +- sizeof(bcm63xx_sprom)); ++ memcpy(&fallback_sprom.sprom, &bcm63xx_default_sprom, ++ sizeof(bcm63xx_default_sprom)); + break; + default: + return -EINVAL; +@@ -973,12 +991,15 @@ int __init bcm63xx_register_fallback_spr + sprom_apply_fixups(template_sprom, data->board_fixups, + data->num_board_fixups); + +- sprom_extract(&bcm63xx_sprom, template_sprom, size); ++ sprom_extract(&fallback_sprom.sprom, template_sprom, size); + } + +- memcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN); +- memcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN); +- memcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN); ++ memcpy(fallback_sprom.sprom.il0mac, data->mac_addr, ETH_ALEN); ++ memcpy(fallback_sprom.sprom.et0mac, data->mac_addr, ETH_ALEN); ++ memcpy(fallback_sprom.sprom.et1mac, data->mac_addr, ETH_ALEN); ++ ++ fallback_sprom.pci_bus = data->pci_bus; ++ fallback_sprom.pci_dev = data->pci_dev; + #endif /* defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) */ + + #if defined(CONFIG_SSB_PCIHOST) +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h +@@ -30,6 +30,9 @@ struct fallback_sprom_data { + u8 mac_addr[ETH_ALEN]; + enum sprom_type type; + ++ u8 pci_bus; ++ u8 pci_dev; ++ + struct sprom_fixup *board_fixups; + unsigned int num_board_fixups; + }; diff --git a/target/linux/brcm63xx/patches-4.1/367-MIPS-BCM63XX-add-support-for-loading-DTB.patch b/target/linux/brcm63xx/patches-4.1/367-MIPS-BCM63XX-add-support-for-loading-DTB.patch new file mode 100644 index 0000000..5ab76e4 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/367-MIPS-BCM63XX-add-support-for-loading-DTB.patch @@ -0,0 +1,119 @@ +From 26546e5499d98616322fb3472b977e2e86603f3a Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 24 Jun 2014 10:57:51 +0200 +Subject: [PATCH 45/48] MIPS: BCM63XX: add support for loading DTB + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/Kconfig | 4 ++++ + arch/mips/bcm63xx/boards/board_common.c | 34 +++++++++++++++++++++++++++++++ + arch/mips/bcm63xx/prom.c | 6 ++++++ + 3 files changed, 44 insertions(+) + +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -1,6 +1,10 @@ + menu "Board support" + depends on BCM63XX + ++config BOARD_BCM63XX_DT ++ bool "Device Tree boards (experimential)" ++ select USE_OF ++ + config BOARD_BCM963XX + bool "Generic Broadcom 963xx boards" + select SSB +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -10,12 +10,15 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include + #include + #include + #include ++#include + #include + #include + #include +@@ -126,8 +129,23 @@ void __init board_setup(void) + /* make sure we're running on expected cpu */ + if (bcm63xx_get_cpu_id() != board.expected_cpu_id) + panic("unexpected CPU for bcm963xx board"); ++ ++#if CONFIG_OF ++ if (initial_boot_params) ++ __dt_setup_arch(initial_boot_params); ++#endif + } + ++#if CONFIG_OF ++void __init device_tree_init(void) ++{ ++ if (!initial_boot_params) ++ return; ++ ++ unflatten_and_copy_device_tree(); ++} ++#endif ++ + static struct gpio_led_platform_data bcm63xx_led_data; + + static struct platform_device bcm63xx_gpio_leds = { +@@ -136,6 +154,13 @@ static struct platform_device bcm63xx_gp + .dev.platform_data = &bcm63xx_led_data, + }; + ++#if CONFIG_OF ++static struct of_device_id of_ids[] = { ++ { /* filled at runtime */ }, ++ { .compatible = "simple-bus" }, ++ { }, ++}; ++#endif + /* + * third stage init callback, register all board devices. + */ +@@ -143,6 +168,15 @@ int __init board_register_devices(void) + { + int usbh_ports = 0; + ++#if CONFIG_OF ++ if (of_have_populated_dt()) { ++ snprintf(of_ids[0].compatible, sizeof(of_ids[0].compatible), ++ "brcm,bcm%x", bcm63xx_get_cpu_id()); ++ ++ of_platform_populate(NULL, of_ids, NULL, NULL); ++ } ++#endif ++ + if (board.has_uart0) + bcm63xx_uart_register(0); + +--- a/arch/mips/bcm63xx/prom.c ++++ b/arch/mips/bcm63xx/prom.c +@@ -8,6 +8,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -23,6 +24,11 @@ void __init prom_init(void) + { + u32 reg, mask; + ++#if CONFIG_OF ++ if (fw_arg0 == -2) ++ early_init_dt_verify((void *)fw_arg1); ++#endif ++ + bcm63xx_cpu_init(); + + /* stop any running watchdog */ diff --git a/target/linux/brcm63xx/patches-4.1/368-MIPS-BCM63XX-add-support-for-matching-the-board_info.patch b/target/linux/brcm63xx/patches-4.1/368-MIPS-BCM63XX-add-support-for-matching-the-board_info.patch new file mode 100644 index 0000000..fd280d8 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/368-MIPS-BCM63XX-add-support-for-matching-the-board_info.patch @@ -0,0 +1,95 @@ +From 25bf2b5836c892f091651d8a3384c9c57ce1b400 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 26 Jun 2014 12:51:00 +0200 +Subject: [PATCH 46/48] MIPS: BCM63XX: add support for matching the board_info + by dtb + +Allow using the passed dtb's compatible property to match board_info +structs instead of nvram's boardname field, which is not unique anyway. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 15 +++++++++++++++ + arch/mips/bcm63xx/boards/board_common.c | 18 ++++++++++++++++++ + arch/mips/bcm63xx/boards/board_common.h | 3 +++ + 3 files changed, 36 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -710,6 +710,10 @@ static const struct board_info __initcon + #endif + }; + ++static struct of_device_id const bcm963xx_boards_dt[] = { ++ { }, ++}; ++ + /* + * early init callback, read nvram data from flash and checksum it + */ +@@ -721,6 +725,7 @@ void __init board_bcm963xx_init(void) + char *board_name = NULL; + u32 val; + struct bcm_hcs *hcs; ++ const struct of_device_id *board_match; + + /* read base address of boot chip select (0) + * 6328/6362 do not have MPI but boot from a fixed address +@@ -760,6 +765,16 @@ void __init board_bcm963xx_init(void) + } else { + board_name = bcm63xx_nvram_get_name(); + } ++ ++ /* find board by compat */ ++ board_match = bcm63xx_match_board(bcm963xx_boards_dt); ++ if (board_match) { ++ board_early_setup(board_match->data, ++ bcm63xx_nvram_get_mac_address); ++ ++ return; ++ } ++ + /* find board by name */ + for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) { + if (strncmp(board_name, bcm963xx_boards[i]->name, 16)) +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -249,3 +249,21 @@ int __init board_register_devices(void) + + return 0; + } ++ ++const struct of_device_id * __init bcm63xx_match_board(const struct of_device_id *m) ++{ ++ const struct of_device_id *match; ++ unsigned long dt_root; ++ ++ if (!IS_ENABLED(CONFIG_OF) || !initial_boot_params) ++ return NULL; ++ ++ dt_root = of_get_flat_dt_root(); ++ ++ for (match = m; match->compatible[0]; match++) { ++ if (of_flat_dt_is_compatible(dt_root, match->compatible)) ++ return match; ++ } ++ ++ return NULL; ++} +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -1,11 +1,14 @@ + #ifndef __BOARD_COMMON_H + #define __BOARD_COMMON_H + ++#include + #include + + void board_early_setup(const struct board_info *board, + int (*get_mac_address)(u8 mac[ETH_ALEN])); + ++const struct of_device_id *bcm63xx_match_board(const struct of_device_id *); ++ + #if defined(CONFIG_BOARD_BCM963XX) + void board_bcm963xx_init(void); + #else diff --git a/target/linux/brcm63xx/patches-4.1/369-MIPS-BCM63XX-populate-the-compatible-to-board_info-l.patch b/target/linux/brcm63xx/patches-4.1/369-MIPS-BCM63XX-populate-the-compatible-to-board_info-l.patch new file mode 100644 index 0000000..653f9fd --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/369-MIPS-BCM63XX-populate-the-compatible-to-board_info-l.patch @@ -0,0 +1,65 @@ +From e71eea9953c774dfadb754258824fb1888c279f4 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 21 Nov 2014 16:54:06 +0100 +Subject: [PATCH 47/48] MIPS: BCM63XX: populate the compatible to board_info + list + +Populate the compatible to board_info list to allow dtbs to be used +for known boards. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 34 +++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -711,6 +711,48 @@ static const struct board_info __initcon + }; + + static struct of_device_id const bcm963xx_boards_dt[] = { ++#ifdef CONFIG_OF ++#ifdef CONFIG_BCM63XX_CPU_3368 ++ { .compatible = "netgear,cvg834g", .data = &board_cvg834g, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6328 ++ { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6338 ++ { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, ++ { .compatible = "brcm,bcm96338w", .data = &board_96338w, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6345 ++ { .compatible = "brcm,bcm96345gw2", .data = &board_96345gw2, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6348 ++ { .compatible = "belkin,f5d7633", .data = &board_96348gw_10, }, ++ { .compatible = "brcm,bcm96348r", .data = &board_96348r, }, ++ { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, ++ { .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, }, ++ { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, ++ { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, ++ { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, ++ { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, ++ { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, ++ { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, ++ { .compatible = "usr,9108", .data = &board_96348gw_a, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6358 ++ { .compatible = "alcatel,rg100a", .data = &board_96358vw2, }, ++ { .compatible = "brcm,bcm96358vw", .data = &board_96358vw, }, ++ { .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, }, ++ { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, ++ { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, ++ { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, ++ { .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, }, ++ { .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, }, ++#endif ++#ifdef CONFIG_BCM63XX_CPU_6368 ++#endif ++#ifdef CONFIG_BCM63XX_CPU_63268 ++#endif ++#endif /* CONFIG_OF */ + { }, + }; + diff --git a/target/linux/brcm63xx/patches-4.1/371_add_of_node_available_by_alias.patch b/target/linux/brcm63xx/patches-4.1/371_add_of_node_available_by_alias.patch new file mode 100644 index 0000000..dbe1a41 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/371_add_of_node_available_by_alias.patch @@ -0,0 +1,37 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -144,6 +144,18 @@ void __init device_tree_init(void) + + unflatten_and_copy_device_tree(); + } ++ ++int board_of_device_present(const char *alias) ++{ ++ bool present; ++ struct device_node *np; ++ ++ np = of_find_node_by_path(alias); ++ present = of_device_is_available(np); ++ of_node_put(np); ++ ++ return present; ++} + #endif + + static struct gpio_led_platform_data bcm63xx_led_data; +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -15,4 +15,13 @@ void board_bcm963xx_init(void); + static inline void board_bcm963xx_init(void) { } + #endif + ++#if defined(CONFIG_OF) ++int board_of_device_present(const char *alias); ++#else ++static inline void board_of_device_present(const char *alias) ++{ ++ return 0; ++} ++#endif ++ + #endif /* __BOARD_COMMON_H */ diff --git a/target/linux/brcm63xx/patches-4.1/372_dont_register_pflash_when_available_in_dtb.patch b/target/linux/brcm63xx/patches-4.1/372_dont_register_pflash_when_available_in_dtb.patch new file mode 100644 index 0000000..25384eb --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/372_dont_register_pflash_when_available_in_dtb.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -23,6 +23,8 @@ + #include + #include + ++#include "boards/board_common.h" ++ + static int flash_type; + + static struct mtd_partition mtd_partitions[] = { +@@ -178,6 +180,9 @@ int __init bcm63xx_flash_register(void) + + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: ++ /* don't register when already registered through from dtb */ ++ if (board_of_device_present("pflash")) ++ return 0; + + if (!mtd_resources[0].start) { + /* read base address of boot chip select (0) */ diff --git a/target/linux/brcm63xx/patches-4.1/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch b/target/linux/brcm63xx/patches-4.1/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch new file mode 100644 index 0000000..555352e --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch @@ -0,0 +1,45 @@ +From 8a0803979163c647736cb234ee1620c049c4915c Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 1 Dec 2014 00:20:07 +0100 +Subject: [PATCH 5/5] MIPS: BCM63XX: register interrupt controllers through DT + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/irq.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -15,6 +15,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -22,6 +24,9 @@ + #include + #include + ++IRQCHIP_DECLARE(mips_cpu_intc, "mti,cpu-interrupt-controller", ++ mips_cpu_irq_of_init); ++ + void __init arch_init_irq(void) + { + void __iomem *periph_bases[2]; +@@ -30,6 +35,13 @@ void __init arch_init_irq(void) + int periph_irqs[2] = { 2, 3 }; + int ext_irqs[6]; + ++#ifdef CONFIG_OF ++ if (initial_boot_params) { ++ irqchip_init(); ++ return; ++ } ++#endif ++ + periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); + periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); + ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); diff --git a/target/linux/brcm63xx/patches-4.1/374-gpio-add-a-simple-GPIO-driver-for-bcm63xx.patch b/target/linux/brcm63xx/patches-4.1/374-gpio-add-a-simple-GPIO-driver-for-bcm63xx.patch new file mode 100644 index 0000000..f80818d --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/374-gpio-add-a-simple-GPIO-driver-for-bcm63xx.patch @@ -0,0 +1,165 @@ +From dbe94a8daaa63ef81b7414f2a17bca8e36dd6daa Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 20 Feb 2015 19:55:32 +0100 +Subject: [PATCH 1/6] gpio: add a simple GPIO driver for bcm63xx + + +Signed-off-by: Jonas Gorski +--- + drivers/gpio/Kconfig | 8 +++ + drivers/gpio/Makefile | 1 + + drivers/gpio/gpio-bcm63xx.c | 122 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 131 insertions(+) + create mode 100644 drivers/gpio/gpio-bcm63xx.c + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -126,6 +126,13 @@ config GPIO_BCM_KONA + help + Turn on GPIO support for Broadcom "Kona" chips. + ++config GPIO_BCM63XX ++ bool "Broadcom BCM63XX GPIO" ++ depends on MIPS || COMPILE_TEST ++ select GPIO_GENERIC ++ help ++ Turn on GPIO support for Broadcom BCM63XX xDSL chips. ++ + config GPIO_CLPS711X + tristate "CLPS711X GPIO support" + depends on ARCH_CLPS711X || COMPILE_TEST +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -21,6 +21,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alte + obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o + obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o + obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o ++obj-$(CONFIG_GPIO_BCM63XX) += gpio-bcm63xx.o + obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o + obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o + obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o +--- /dev/null ++++ b/drivers/gpio/gpio-bcm63xx.c +@@ -0,0 +1,122 @@ ++/* ++ * Driver for BCM63XX memory-mapped GPIO controllers, based on ++ * Generic driver for memory-mapped GPIO controllers. ++ * ++ * Copyright 2008 MontaVista Software, Inc. ++ * Copyright 2008,2010 Anton Vorontsov ++ * Copyright 2015 Jonas Gorski ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int bcm63xx_gpio_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct resource *dat_r, *dirout_r; ++ void __iomem *dat; ++ void __iomem *dirout; ++ unsigned long sz; ++ int err; ++ struct bgpio_chip *bgc; ++ struct bgpio_pdata *pdata = dev_get_platdata(dev); ++ ++ dirout_r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dat_r = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!dat_r || !dirout_r) ++ return -EINVAL; ++ ++ if (resource_size(dat_r) != resource_size(dirout_r)) ++ return -EINVAL; ++ ++ sz = resource_size(dat_r); ++ ++ dat = devm_ioremap_resource(dev, dat_r); ++ if (IS_ERR(dat)) ++ return PTR_ERR(dat); ++ ++ dirout = devm_ioremap_resource(dev, dirout_r); ++ if (IS_ERR(dirout)) ++ return PTR_ERR(dirout); ++ ++ bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL); ++ if (!bgc) ++ return -ENOMEM; ++ ++ err = bgpio_init(bgc, dev, sz, dat, NULL, NULL, dirout, NULL, ++ BGPIOF_BIG_ENDIAN_BYTE_ORDER); ++ if (err) ++ return err; ++ ++ platform_set_drvdata(pdev, bgc); ++ ++ if (dev->of_node) { ++ int id = of_alias_get_id(dev->of_node, "gpio"); ++ u32 ngpios; ++ ++ if (id >= 0) ++ bgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, ++ "bcm63xx-gpio.%d", id); ++ ++ if (!of_property_read_u32(dev->of_node, "ngpios", &ngpios)) ++ bgc->gc.ngpio = ngpios; ++ ++ } else if (pdata) { ++ bgc->gc.base = pdata->base; ++ if (pdata->ngpio > 0) ++ bgc->gc.ngpio = pdata->ngpio; ++ } ++ ++ return gpiochip_add(&bgc->gc); ++} ++ ++static int bcm63xx_gpio_remove(struct platform_device *pdev) ++{ ++ struct bgpio_chip *bgc = platform_get_drvdata(pdev); ++ ++ return bgpio_remove(bgc); ++} ++ ++#ifdef CONFIG_OF ++static struct of_device_id bcm63xx_gpio_of_match[] = { ++ { .compatible = "brcm,bcm6345-gpio" }, ++ { }, ++}; ++#endif ++ ++static struct platform_driver bcm63xx_gpio_driver = { ++ .probe = bcm63xx_gpio_probe, ++ .remove = bcm63xx_gpio_remove, ++ .driver = { ++ .name = "bcm63xx-gpio", ++ .of_match_table = of_match_ptr(bcm63xx_gpio_of_match), ++ }, ++}; ++ ++module_platform_driver(bcm63xx_gpio_driver); ++ ++MODULE_DESCRIPTION("Driver for BCM63XX memory-mapped GPIO controllers"); ++MODULE_AUTHOR("Jonas Gorski "); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/brcm63xx/patches-4.1/375-MIPS-BCM63XX-switch-to-new-gpio-driver.patch b/target/linux/brcm63xx/patches-4.1/375-MIPS-BCM63XX-switch-to-new-gpio-driver.patch new file mode 100644 index 0000000..ce32f64 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/375-MIPS-BCM63XX-switch-to-new-gpio-driver.patch @@ -0,0 +1,216 @@ +From cc99dca188bb63ba390008e2f7fa62d0300233e0 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 20 Feb 2015 23:58:54 +0100 +Subject: [PATCH 2/6] MIPS: BCM63XX: switch to new gpio driver + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_common.c | 2 + + arch/mips/bcm63xx/gpio.c | 147 +++++++------------------------ + arch/mips/bcm63xx/setup.c | 3 - + 3 files changed, 33 insertions(+), 119 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -189,6 +189,8 @@ int __init board_register_devices(void) + } + #endif + ++ bcm63xx_gpio_init(); ++ + if (board.has_uart0) + bcm63xx_uart_register(0); + +--- a/arch/mips/bcm63xx/gpio.c ++++ b/arch/mips/bcm63xx/gpio.c +@@ -5,147 +5,62 @@ + * + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2008-2011 Florian Fainelli ++ * Copyright (C) Jonas Gorski + */ + + #include +-#include +-#include + #include ++#include + #include + + #include + #include +-#include + #include + +-static u32 gpio_out_low_reg; +- +-static void bcm63xx_gpio_out_low_reg_init(void) ++static void __init bcm63xx_gpio_init_one(int id, int dir, int data, int ngpio) + { +- switch (bcm63xx_get_cpu_id()) { +- case BCM6345_CPU_ID: +- gpio_out_low_reg = GPIO_DATA_LO_REG_6345; +- break; +- default: +- gpio_out_low_reg = GPIO_DATA_LO_REG; +- break; +- } +-} +- +-static DEFINE_SPINLOCK(bcm63xx_gpio_lock); +-static u32 gpio_out_low, gpio_out_high; ++ struct resource res[2]; ++ struct bgpio_pdata pdata; + +-static void bcm63xx_gpio_set(struct gpio_chip *chip, +- unsigned gpio, int val) +-{ +- u32 reg; +- u32 mask; +- u32 *v; +- unsigned long flags; +- +- if (gpio >= chip->ngpio) +- BUG(); +- +- if (gpio < 32) { +- reg = gpio_out_low_reg; +- mask = 1 << gpio; +- v = &gpio_out_low; +- } else { +- reg = GPIO_DATA_HI_REG; +- mask = 1 << (gpio - 32); +- v = &gpio_out_high; +- } +- +- spin_lock_irqsave(&bcm63xx_gpio_lock, flags); +- if (val) +- *v |= mask; +- else +- *v &= ~mask; +- bcm_gpio_writel(*v, reg); +- spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags); +-} ++ memset(res, 0, sizeof(res)); ++ memset(&pdata, 0, sizeof(pdata)); + +-static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio) +-{ +- u32 reg; +- u32 mask; ++ res[0].flags = IORESOURCE_MEM; ++ res[0].start = bcm63xx_regset_address(RSET_GPIO); ++ res[0].start += dir; + +- if (gpio >= chip->ngpio) +- BUG(); ++ res[0].end = res[0].start + 3; + +- if (gpio < 32) { +- reg = gpio_out_low_reg; +- mask = 1 << gpio; +- } else { +- reg = GPIO_DATA_HI_REG; +- mask = 1 << (gpio - 32); +- } ++ res[1].flags = IORESOURCE_MEM; ++ res[1].start = bcm63xx_regset_address(RSET_GPIO); ++ res[1].start += data; + +- return !!(bcm_gpio_readl(reg) & mask); +-} ++ res[1].end = res[1].start + 3; + +-static int bcm63xx_gpio_set_direction(struct gpio_chip *chip, +- unsigned gpio, int dir) +-{ +- u32 reg; +- u32 mask; +- u32 tmp; +- unsigned long flags; +- +- if (gpio >= chip->ngpio) +- BUG(); +- +- if (gpio < 32) { +- reg = GPIO_CTL_LO_REG; +- mask = 1 << gpio; +- } else { +- reg = GPIO_CTL_HI_REG; +- mask = 1 << (gpio - 32); +- } +- +- spin_lock_irqsave(&bcm63xx_gpio_lock, flags); +- tmp = bcm_gpio_readl(reg); +- if (dir == BCM63XX_GPIO_DIR_IN) +- tmp &= ~mask; +- else +- tmp |= mask; +- bcm_gpio_writel(tmp, reg); +- spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags); ++ pdata.base = id * 32; ++ pdata.ngpio = ngpio; + +- return 0; ++ platform_device_register_resndata(NULL, "bcm63xx-gpio", id, res, 2, ++ &pdata, sizeof(pdata)); + } + +-static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) ++int __init bcm63xx_gpio_init(void) + { +- return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_IN); +-} ++ int ngpio = bcm63xx_gpio_count(); ++ int data_low_reg; + +-static int bcm63xx_gpio_direction_output(struct gpio_chip *chip, +- unsigned gpio, int value) +-{ +- bcm63xx_gpio_set(chip, gpio, value); +- return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_OUT); +-} ++ if (BCMCPU_IS_6345()) ++ data_low_reg = GPIO_DATA_LO_REG_6345; ++ else ++ data_low_reg = GPIO_DATA_LO_REG; + ++ bcm63xx_gpio_init_one(0, GPIO_CTL_LO_REG, data_low_reg, min(ngpio, 32)); + +-static struct gpio_chip bcm63xx_gpio_chip = { +- .label = "bcm63xx-gpio", +- .direction_input = bcm63xx_gpio_direction_input, +- .direction_output = bcm63xx_gpio_direction_output, +- .get = bcm63xx_gpio_get, +- .set = bcm63xx_gpio_set, +- .base = 0, +-}; ++ if (ngpio <= 32) ++ return 0; + +-int __init bcm63xx_gpio_init(void) +-{ +- bcm63xx_gpio_out_low_reg_init(); ++ bcm63xx_gpio_init_one(1, GPIO_CTL_HI_REG, GPIO_DATA_HI_REG, ngpio - 32); + +- gpio_out_low = bcm_gpio_readl(gpio_out_low_reg); +- if (!BCMCPU_IS_6345()) +- gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG); +- bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count(); +- pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio); ++ return 0; + +- return gpiochip_add(&bcm63xx_gpio_chip); + } +--- a/arch/mips/bcm63xx/setup.c ++++ b/arch/mips/bcm63xx/setup.c +@@ -164,9 +164,6 @@ void __init plat_mem_setup(void) + + int __init bcm63xx_register_devices(void) + { +- /* register gpiochip */ +- bcm63xx_gpio_init(); +- + return board_register_devices(); + } + diff --git a/target/linux/brcm63xx/patches-4.1/376-net-bcm63xx_enet-use-named-gpio-for-ephy-reset-gpio.patch b/target/linux/brcm63xx/patches-4.1/376-net-bcm63xx_enet-use-named-gpio-for-ephy-reset-gpio.patch new file mode 100644 index 0000000..6d19cc0 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/376-net-bcm63xx_enet-use-named-gpio-for-ephy-reset-gpio.patch @@ -0,0 +1,46 @@ +From ec905f2ea78ec40602a685ede31c5e4f9893d196 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Feb 2015 16:35:07 +0100 +Subject: [PATCH 3/6] net: bcm63xx_enet: use named gpio for ephy reset gpio + +Allow using a named optional gpio for ephy reset gpio registration. +--- + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + #include "bcm63xx_enet.h" +@@ -2848,10 +2849,15 @@ static int bcm_enet_shared_probe(struct + { + struct resource *res; + void __iomem *p[3]; ++ struct gpio_desc *ephy_reset; + unsigned int i; + + memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base)); + ++ ephy_reset = devm_gpiod_get_optional(&pdev->dev, "ephy-reset"); ++ if (IS_ERR(ephy_reset)) ++ return PTR_ERR(ephy_reset); ++ + for (i = 0; i < 3; i++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + p[i] = devm_ioremap_resource(&pdev->dev, res); +@@ -2861,6 +2867,9 @@ static int bcm_enet_shared_probe(struct + + memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base)); + ++ if (ephy_reset) ++ gpiod_direction_output(ephy_reset, 0); ++ + return 0; + } + diff --git a/target/linux/brcm63xx/patches-4.1/377-MIPS-BCM63XX-register-lookup-for-ephy-reset-gpio.patch b/target/linux/brcm63xx/patches-4.1/377-MIPS-BCM63XX-register-lookup-for-ephy-reset-gpio.patch new file mode 100644 index 0000000..0cbb4f5 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/377-MIPS-BCM63XX-register-lookup-for-ephy-reset-gpio.patch @@ -0,0 +1,138 @@ +From d13bdf92ec885105cf107183f8464c40e5f3b93b Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Feb 2015 17:21:59 +0100 +Subject: [PATCH 4/6] MIPS: BCM63XX: register lookup for ephy-reset gpio + + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- + arch/mips/bcm63xx/boards/board_common.c | 7 +++-- + arch/mips/bcm63xx/gpio.c | 32 ++++++++++++++++++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 ++ + .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 5 +-- + 5 files changed, 42 insertions(+), 6 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -54,7 +54,7 @@ static struct board_info __initdata boar + }, + + .ephy_reset_gpio = 36, +- .ephy_reset_gpio_flags = GPIOF_INIT_HIGH, ++ .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, + }; + #endif + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -257,9 +257,10 @@ int __init board_register_devices(void) + + platform_device_register(&bcm63xx_gpio_leds); + +- if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) +- gpio_request_one(board.ephy_reset_gpio, +- board.ephy_reset_gpio_flags, "ephy-reset"); ++ if (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) { ++ bcm63xx_gpio_ephy_reset(board.ephy_reset_gpio, ++ board.ephy_reset_gpio_flags); ++ } + + return 0; + } +--- a/arch/mips/bcm63xx/gpio.c ++++ b/arch/mips/bcm63xx/gpio.c +@@ -8,15 +8,24 @@ + * Copyright (C) Jonas Gorski + */ + ++#include ++ + #include + #include + #include + #include ++#include + + #include + #include + #include + ++/* for registering lookups; make them large enough to hold OF names */ ++static char *gpio_chip_labels[] = { ++ "xxxxxxxx.gpio-controller", ++ "xxxxxxxx.gpio-controller", ++}; ++ + static void __init bcm63xx_gpio_init_one(int id, int dir, int data, int ngpio) + { + struct resource res[2]; +@@ -40,6 +49,7 @@ static void __init bcm63xx_gpio_init_one + pdata.base = id * 32; + pdata.ngpio = ngpio; + ++ sprintf(gpio_chip_labels[id], "bcm63xx-gpio.%d", id); + platform_device_register_resndata(NULL, "bcm63xx-gpio", id, res, 2, + &pdata, sizeof(pdata)); + } +@@ -64,3 +74,25 @@ int __init bcm63xx_gpio_init(void) + return 0; + + } ++ ++static struct gpiod_lookup_table ephy_reset = { ++ .dev_id = "bcm63xx_enet_shared.0", ++ .table = { ++ { /* filled at runtime */ }, ++ { }, ++ }, ++}; ++ ++ ++void bcm63xx_gpio_ephy_reset(int hw_gpio, enum gpio_lookup_flags flags) ++{ ++ if (ephy_reset.table[0].chip_label) ++ return; ++ ++ ephy_reset.table[0].chip_label = gpio_chip_labels[hw_gpio / 32]; ++ ephy_reset.table[0].chip_hwnum = hw_gpio % 32; ++ ephy_reset.table[0].con_id = "ephy-reset"; ++ ephy_reset.table[0].flags = flags; ++ ++ gpiod_add_lookup_table(&ephy_reset); ++} +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +@@ -2,9 +2,11 @@ + #define BCM63XX_GPIO_H + + #include ++#include + #include + + int __init bcm63xx_gpio_init(void); ++void bcm63xx_gpio_ephy_reset(int hw_gpio, enum gpio_lookup_flags flags); + + static inline unsigned long bcm63xx_gpio_count(void) + { +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -3,6 +3,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -54,8 +55,8 @@ struct board_info { + /* External PHY reset GPIO */ + unsigned int ephy_reset_gpio; + +- /* External PHY reset GPIO flags from gpio.h */ +- unsigned long ephy_reset_gpio_flags; ++ /* External PHY reset GPIO flags from gpio/machine.h */ ++ enum gpio_lookup_flags ephy_reset_gpio_flags; + + /* fallback sprom config */ + struct fallback_sprom_data fallback_sprom; diff --git a/target/linux/brcm63xx/patches-4.1/378-MIPS-BCM63XX-do-not-register-gpio-controller-if-pres.patch b/target/linux/brcm63xx/patches-4.1/378-MIPS-BCM63XX-do-not-register-gpio-controller-if-pres.patch new file mode 100644 index 0000000..2faf0de --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/378-MIPS-BCM63XX-do-not-register-gpio-controller-if-pres.patch @@ -0,0 +1,34 @@ +From e55892aac9d5508a000647ca66f0e678e02be3bb Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Feb 2015 17:26:50 +0100 +Subject: [PATCH 5/6] MIPS: BCM63XX: do not register gpio-controller if +present in dtb + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/gpio.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/gpio.c ++++ b/arch/mips/bcm63xx/gpio.c +@@ -20,6 +20,8 @@ + #include + #include + ++#include "boards/board_common.h" ++ + /* for registering lookups; make them large enough to hold OF names */ + static char *gpio_chip_labels[] = { + "xxxxxxxx.gpio-controller", +@@ -50,8 +52,9 @@ static void __init bcm63xx_gpio_init_one + pdata.ngpio = ngpio; + + sprintf(gpio_chip_labels[id], "bcm63xx-gpio.%d", id); +- platform_device_register_resndata(NULL, "bcm63xx-gpio", id, res, 2, +- &pdata, sizeof(pdata)); ++ if (!board_of_device_present("gpio0")) ++ platform_device_register_resndata(NULL, "bcm63xx-gpio", id, res, ++ 2, &pdata, sizeof(pdata)); + } + + int __init bcm63xx_gpio_init(void) diff --git a/target/linux/brcm63xx/patches-4.1/379-MIPS-BCM63XX-provide-a-gpio-lookup-for-the-pcmcia-re.patch b/target/linux/brcm63xx/patches-4.1/379-MIPS-BCM63XX-provide-a-gpio-lookup-for-the-pcmcia-re.patch new file mode 100644 index 0000000..b571999 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/379-MIPS-BCM63XX-provide-a-gpio-lookup-for-the-pcmcia-re.patch @@ -0,0 +1,59 @@ +From 1647cccc871bf43876c3df9852869680880d054c Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Wed, 25 Mar 2015 13:52:02 +0100 +Subject: [PATCH 1/2] MIPS: BCM63XX: provide a gpio lookup for the pcmcia + ready gpio + +To prepare for a time when gpiobases don't need to be fixed anymore. + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-pcmcia.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/mips/bcm63xx/dev-pcmcia.c ++++ b/arch/mips/bcm63xx/dev-pcmcia.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -101,6 +102,14 @@ static const struct { + }, + }; + ++static struct gpiod_lookup_table pcmcia_gpios_table = { ++ .dev_id = "bcm63xx_pcmcia.0", ++ .table = { ++ GPIO_LOOKUP("bcm63xx-gpio.0", 0, "ready", GPIO_ACTIVE_HIGH), ++ { }, ++ }, ++}; ++ + int __init bcm63xx_pcmcia_register(void) + { + int ret, i; +@@ -112,16 +121,20 @@ int __init bcm63xx_pcmcia_register(void) + switch (bcm63xx_get_cpu_id()) { + case BCM6348_CPU_ID: + pd.ready_gpio = 22; ++ pcmcia_gpios_table.table[0].chip_hwnum = 22; + break; + + case BCM6358_CPU_ID: + pd.ready_gpio = 18; ++ pcmcia_gpios_table.table[0].chip_hwnum = 18; + break; + + default: + return -ENODEV; + } + ++ gpiod_add_lookup_table(&pcmcia_gpios_table); ++ + pcmcia_resources[0].start = bcm63xx_regset_address(RSET_PCMCIA); + pcmcia_resources[0].end = pcmcia_resources[0].start + + RSET_PCMCIA_SIZE - 1; diff --git a/target/linux/brcm63xx/patches-4.1/380-pcmcia-bcm63xx_pmcia-use-the-new-named-gpio.patch b/target/linux/brcm63xx/patches-4.1/380-pcmcia-bcm63xx_pmcia-use-the-new-named-gpio.patch new file mode 100644 index 0000000..524ca1a --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/380-pcmcia-bcm63xx_pmcia-use-the-new-named-gpio.patch @@ -0,0 +1,59 @@ +From c4e04f1c54928a49b227a5420d38b18226838775 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Wed, 25 Mar 2015 13:54:56 +0100 +Subject: [PATCH 2/2] pcmcia: bcm63xx_pmcia: use the new named gpio + +Use the new named gpio instead of relying on the hardware gpio numbers +matching the virtual gpio numbers. + +Signed-off-by: Jonas Gorski +--- + drivers/pcmcia/bcm63xx_pcmcia.c | 9 ++++++++- + drivers/pcmcia/bcm63xx_pcmcia.h | 4 ++++ + 2 files changed, 12 insertions(+), 1 deletion(-) + +--- a/drivers/pcmcia/bcm63xx_pcmcia.c ++++ b/drivers/pcmcia/bcm63xx_pcmcia.c +@@ -237,7 +237,7 @@ static unsigned int __get_socket_status( + stat |= SS_XVCARD; + stat |= SS_POWERON; + +- if (gpio_get_value(skt->pd->ready_gpio)) ++ if (gpiod_get_value(skt->ready_gpio)) + stat |= SS_READY; + + return stat; +@@ -373,6 +373,13 @@ static int bcm63xx_drv_pcmcia_probe(stru + goto err; + } + ++ /* get ready gpio */ ++ skt->ready_gpio = devm_gpiod_get(&pdev->dev, "ready", GPIOD_IN); ++ if (IS_ERR(skt->ready_gpio)) { ++ ret = PTR_ERR(skt->ready_gpio); ++ goto err; ++ } ++ + /* resources are static */ + sock->resource_ops = &pccard_static_ops; + sock->ops = &bcm63xx_pcmcia_operations; +--- a/drivers/pcmcia/bcm63xx_pcmcia.h ++++ b/drivers/pcmcia/bcm63xx_pcmcia.h +@@ -3,6 +3,7 @@ + + #include + #include ++#include + #include + #include + +@@ -55,6 +56,9 @@ struct bcm63xx_pcmcia_socket { + + /* base address of io memory */ + void __iomem *io_base; ++ ++ /* ready gpio */ ++ struct gpio_desc *ready_gpio; + }; + + #endif /* BCM63XX_PCMCIA_H_ */ diff --git a/target/linux/brcm63xx/patches-4.1/400-bcm963xx_flashmap.patch b/target/linux/brcm63xx/patches-4.1/400-bcm963xx_flashmap.patch new file mode 100644 index 0000000..c693ace --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/400-bcm963xx_flashmap.patch @@ -0,0 +1,65 @@ +From a4d005c91d403d9f3d0272db6cc46202c06ec774 Mon Sep 17 00:00:00 2001 +From: Axel Gembe +Date: Mon, 12 May 2008 18:54:09 +0200 +Subject: [PATCH] bcm963xx: flashmap support + +Signed-off-by: Axel Gembe +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 19 +---------------- + drivers/mtd/maps/bcm963xx-flash.c | 32 ++++++++++++++++++++++++---- + drivers/mtd/redboot.c | 13 +++++++++-- + 3 files changed, 38 insertions(+), 26 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -35,7 +35,7 @@ static struct mtd_partition mtd_partitio + } + }; + +-static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL }; ++static const char *bcm63xx_part_types[] = { "bcm63xxpart", "RedBoot", NULL }; + + static struct physmap_flash_data flash_data = { + .width = 2, +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -72,6 +72,7 @@ static int parse_redboot_partitions(stru + int nulllen = 0; + int numslots; + unsigned long offset; ++ unsigned long fis_origin = 0; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif +@@ -176,6 +177,16 @@ static int parse_redboot_partitions(stru + goto out; + } + ++ if (data && data->origin) { ++ fis_origin = data->origin; ++ } else { ++ for (i = 0; i < numslots; i++) { ++ if (!strncmp(buf[i].name, "RedBoot", 8)) { ++ fis_origin = (buf[i].flash_base & (master->size << 1) - 1); ++ } ++ } ++ } ++ + for (i = 0; i < numslots; i++) { + struct fis_list *new_fl, **prev; + +@@ -196,10 +207,10 @@ static int parse_redboot_partitions(stru + goto out; + } + new_fl->img = &buf[i]; +- if (data && data->origin) +- buf[i].flash_base -= data->origin; +- else +- buf[i].flash_base &= master->size-1; ++ if (fis_origin) ++ buf[i].flash_base -= fis_origin; ++ ++ buf[i].flash_base &= (master->size << 1) - 1; + + /* I'm sure the JFFS2 code has done me permanent damage. + * I now think the following is _normal_ diff --git a/target/linux/brcm63xx/patches-4.1/401-bcm963xx_real_rootfs_length.patch b/target/linux/brcm63xx/patches-4.1/401-bcm963xx_real_rootfs_length.patch new file mode 100644 index 0000000..92c264b --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/401-bcm963xx_real_rootfs_length.patch @@ -0,0 +1,27 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h +@@ -85,8 +85,10 @@ struct bcm_tag { + __u32 rootfs_crc; + /* 224-227: CRC32 of kernel partition */ + __u32 kernel_crc; +- /* 228-235: Unused at present */ +- char reserved1[8]; ++ /* 228-231: Image sequence number */ ++ char image_sequence[4]; ++ /* 222-235: Openwrt: real rootfs length */ ++ __u32 real_rootfs_length; + /* 236-239: CRC32 of header excluding last 20 bytes */ + __u32 header_crc; + /* 240-255: Unused at present */ +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -110,7 +110,8 @@ static int bcm63xx_parse_cfe_partitions( + } else { + /* OpenWrt layout */ + rootfsaddr = kerneladdr + kernellen; +- rootfslen = spareaddr - rootfsaddr; ++ rootfslen = buf->real_rootfs_length; ++ spareaddr = rootfsaddr + rootfslen; + } + } else { + pr_warn("CFE boot tag CRC invalid (expected %08x, actual %08x)\n", diff --git a/target/linux/brcm63xx/patches-4.1/402_bcm63xx_enet_vlan_incoming_fixed.patch b/target/linux/brcm63xx/patches-4.1/402_bcm63xx_enet_vlan_incoming_fixed.patch new file mode 100644 index 0000000..fc2e8ab --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/402_bcm63xx_enet_vlan_incoming_fixed.patch @@ -0,0 +1,11 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -1633,7 +1633,7 @@ static int compute_hw_mtu(struct bcm_ene + actual_mtu = mtu; + + /* add ethernet header + vlan tag size */ +- actual_mtu += VLAN_ETH_HLEN; ++ actual_mtu += VLAN_ETH_HLEN + VLAN_HLEN; + + if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU) + return -EINVAL; diff --git a/target/linux/brcm63xx/patches-4.1/403-6358-enet1-external-mii-clk.patch b/target/linux/brcm63xx/patches-4.1/403-6358-enet1-external-mii-clk.patch new file mode 100644 index 0000000..2733e05 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/403-6358-enet1-external-mii-clk.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -101,6 +101,8 @@ void __init board_early_setup(const stru + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G3_EXT_MII | + GPIO_MODE_6348_G0_EXT_MII; ++ else if (BCMCPU_IS_6358()) ++ val |= GPIO_MODE_6358_ENET1_MII_CLK_INV; + } + + bcm_gpio_writel(val, GPIO_MODE_REG); +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -651,6 +651,8 @@ + #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) + #define GPIO_MODE_6358_SERIAL_LED (1 << 10) + #define GPIO_MODE_6358_UTOPIA (1 << 12) ++#define GPIO_MODE_6358_ENET1_MII_CLK_INV (1 << 30) ++#define GPIO_MODE_6358_ENET0_MII_CLK_INV (1 << 31) + + #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0) + #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1) diff --git a/target/linux/brcm63xx/patches-4.1/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch b/target/linux/brcm63xx/patches-4.1/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch new file mode 100644 index 0000000..6036d2f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch @@ -0,0 +1,169 @@ +From b11218c750ab92cfab4408a0328f1b36ceec3f33 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 6 Jan 2012 12:24:18 +0100 +Subject: [PATCH 19/63] NET: bcm63xx_enet: move phy_(dis)connect into probe/remove + +Only connect/disconnect the phy during probe and remove, not during any +open/close. The phy seldom changes during the runtime, and disconnecting +the phy during close will prevent it from keeping any configuration over +a down/up cycle. + +Signed-off-by: Jonas Gorski +--- + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 84 +++++++++++++------------- + 1 files changed, 41 insertions(+), 43 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -871,10 +871,8 @@ static int bcm_enet_open(struct net_devi + struct bcm_enet_priv *priv; + struct sockaddr addr; + struct device *kdev; +- struct phy_device *phydev; + int i, ret; + unsigned int size; +- char phy_id[MII_BUS_ID_SIZE + 3]; + void *p; + u32 val; + +@@ -882,40 +880,10 @@ static int bcm_enet_open(struct net_devi + kdev = &priv->pdev->dev; + + if (priv->has_phy) { +- /* connect to PHY */ +- snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, +- priv->mii_bus->id, priv->phy_id); +- +- phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, +- PHY_INTERFACE_MODE_MII); +- +- if (IS_ERR(phydev)) { +- dev_err(kdev, "could not attach to PHY\n"); +- return PTR_ERR(phydev); +- } +- +- /* mask with MAC supported features */ +- phydev->supported &= (SUPPORTED_10baseT_Half | +- SUPPORTED_10baseT_Full | +- SUPPORTED_100baseT_Half | +- SUPPORTED_100baseT_Full | +- SUPPORTED_Autoneg | +- SUPPORTED_Pause | +- SUPPORTED_MII); +- phydev->advertising = phydev->supported; +- +- if (priv->pause_auto && priv->pause_rx && priv->pause_tx) +- phydev->advertising |= SUPPORTED_Pause; +- else +- phydev->advertising &= ~SUPPORTED_Pause; +- +- dev_info(kdev, "attached PHY at address %d [%s]\n", +- phydev->addr, phydev->drv->name); +- ++ /* Reset state */ + priv->old_link = 0; + priv->old_duplex = -1; + priv->old_pause = -1; +- priv->phydev = phydev; + } + + /* mask all interrupts and request them */ +@@ -925,7 +893,7 @@ static int bcm_enet_open(struct net_devi + + ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); + if (ret) +- goto out_phy_disconnect; ++ return ret; + + ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0, + dev->name, dev); +@@ -1128,9 +1096,6 @@ out_freeirq_rx: + out_freeirq: + free_irq(dev->irq, dev); + +-out_phy_disconnect: +- phy_disconnect(priv->phydev); +- + return ret; + } + +@@ -1235,12 +1200,6 @@ static int bcm_enet_stop(struct net_devi + free_irq(priv->irq_rx, dev); + free_irq(dev->irq, dev); + +- /* release phy */ +- if (priv->has_phy) { +- phy_disconnect(priv->phydev); +- priv->phydev = NULL; +- } +- + return 0; + } + +@@ -1831,6 +1790,8 @@ static int bcm_enet_probe(struct platfor + + /* MII bus registration */ + if (priv->has_phy) { ++ struct phy_device *phydev; ++ char phy_id[MII_BUS_ID_SIZE + 3]; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { +@@ -1868,6 +1829,38 @@ static int bcm_enet_probe(struct platfor + dev_err(&pdev->dev, "unable to register mdio bus\n"); + goto out_free_mdio; + } ++ ++ /* connect to PHY */ ++ snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, ++ priv->mii_bus->id, priv->phy_id); ++ ++ phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link, ++ PHY_INTERFACE_MODE_MII); ++ ++ if (IS_ERR(phydev)) { ++ dev_err(&pdev->dev, "could not attach to PHY\n"); ++ goto out_unregister_mdio; ++ } ++ ++ /* mask with MAC supported features */ ++ phydev->supported &= (SUPPORTED_10baseT_Half | ++ SUPPORTED_10baseT_Full | ++ SUPPORTED_100baseT_Half | ++ SUPPORTED_100baseT_Full | ++ SUPPORTED_Autoneg | ++ SUPPORTED_Pause | ++ SUPPORTED_MII); ++ phydev->advertising = phydev->supported; ++ ++ if (priv->pause_auto && priv->pause_rx && priv->pause_tx) ++ phydev->advertising |= SUPPORTED_Pause; ++ else ++ phydev->advertising &= ~SUPPORTED_Pause; ++ ++ dev_info(&pdev->dev, "attached PHY at address %d [%s]\n", ++ phydev->addr, phydev->drv->name); ++ ++ priv->phydev = phydev; + } else { + + /* run platform code to initialize PHY device */ +@@ -1913,6 +1906,9 @@ static int bcm_enet_probe(struct platfor + return 0; + + out_unregister_mdio: ++ if (priv->phydev) ++ phy_disconnect(priv->phydev); ++ + if (priv->mii_bus) + mdiobus_unregister(priv->mii_bus); + +@@ -1954,6 +1950,8 @@ static int bcm_enet_remove(struct platfo + enet_writel(priv, 0, ENET_MIISC_REG); + + if (priv->has_phy) { ++ phy_disconnect(priv->phydev); ++ priv->phydev = NULL; + mdiobus_unregister(priv->mii_bus); + mdiobus_free(priv->mii_bus); + } else { diff --git a/target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch b/target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch new file mode 100644 index 0000000..2f2eecf --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch @@ -0,0 +1,53 @@ +From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 15 Jul 2012 20:08:57 +0200 +Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports + +--- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 13 +++++++++++++ + drivers/net/ethernet/broadcom/bcm63xx_enet.c | 12 ++++++++++++ + 2 files changed, 25 insertions(+), 0 deletions(-) + +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -967,6 +967,19 @@ + #define ENETSW_PORTOV_FDX_MASK (1 << 1) + #define ENETSW_PORTOV_LINKUP_MASK (1 << 0) + ++/* Port RGMII control register */ ++#define ENETSW_RGMII_CTRL_REG(x) (0x60 + (x)) ++#define ENETSW_RGMII_CTRL_GMII_CLK_EN (1 << 7) ++#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6) ++#define ENETSW_RGMII_CTRL_MII_MODE_MASK (3 << 4) ++#define ENETSW_RGMII_CTRL_RGMII_MODE (0 << 4) ++#define ENETSW_RGMII_CTRL_MII_MODE (1 << 4) ++#define ENETSW_RGMII_CTRL_RVMII_MODE (2 << 4) ++#define ENETSW_RGMII_CTRL_TIMING_SEL_EN (1 << 0) ++ ++/* Port RGMII timing register */ ++#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x)) ++ + /* MDIO control register */ + #define ENETSW_MDIOC_REG (0xb0) + #define ENETSW_MDIOC_EXT_MASK (1 << 16) +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2225,6 +2225,18 @@ static int bcm_enetsw_open(struct net_de + priv->sw_port_link[i] = 0; + } + ++ /* enable external ports */ ++ for (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) { ++ u8 rgmii_ctrl; ++ ++ if (!priv->used_ports[i].used) ++ continue; ++ ++ rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i)); ++ rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN; ++ enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); ++ } ++ + /* reset mib */ + val = enetsw_readb(priv, ENETSW_GMCR_REG); + val |= ENETSW_GMCR_RST_MIB_MASK; diff --git a/target/linux/brcm63xx/patches-4.1/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch b/target/linux/brcm63xx/patches-4.1/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch new file mode 100644 index 0000000..0c317cb --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch @@ -0,0 +1,135 @@ +From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 3 Jul 2011 15:00:38 +0200 +Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 35 +++++++++++++++++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 + + 2 files changed, 33 insertions(+), 2 deletions(-) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -17,9 +17,12 @@ + #include + #include + #include ++#include ++#include + + #include + #include ++#include + #include + #include + +@@ -66,6 +69,21 @@ void __init bcm63xx_flash_force_phys_bas + mtd_resources[0].end = end; + } + ++static struct flash_platform_data bcm63xx_flash_data = { ++ .part_probe_types = bcm63xx_part_types, ++}; ++ ++static struct spi_board_info bcm63xx_spi_flash_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .mode = 0, ++ .max_speed_hz = 781000, ++ .modalias = "m25p80", ++ .platform_data = &bcm63xx_flash_data, ++ }, ++}; ++ + static int __init bcm63xx_detect_flash_type(void) + { + u32 val; +@@ -73,9 +91,15 @@ static int __init bcm63xx_detect_flash_t + switch (bcm63xx_get_cpu_id()) { + case BCM6318_CPU_ID: + /* only support serial flash */ ++ bcm63xx_spi_flash_info[0].max_speed_hz = 62500000; + return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6328_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); ++ if (val & STRAPBUS_6328_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 33333334; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 16666667; ++ + if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else +@@ -94,12 +118,20 @@ static int __init bcm63xx_detect_flash_t + return BCM63XX_FLASH_TYPE_SERIAL; + case BCM6362_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); ++ if (val & STRAPBUS_6362_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else + return BCM63XX_FLASH_TYPE_NAND; + case BCM6368_CPU_ID: + val = bcm_gpio_readl(GPIO_STRAPBUS_REG); ++ if (val & STRAPBUS_6368_SPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { + case STRAPBUS_6368_BOOT_SEL_NAND: + return BCM63XX_FLASH_TYPE_NAND; +@@ -110,6 +142,11 @@ static int __init bcm63xx_detect_flash_t + } + case BCM63268_CPU_ID: + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); ++ if (val & STRAPBUS_63268_HSSPI_CLK_FAST) ++ bcm63xx_spi_flash_info[0].max_speed_hz = 50000000; ++ else ++ bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; ++ + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) + return BCM63XX_FLASH_TYPE_SERIAL; + else +@@ -195,8 +232,17 @@ int __init bcm63xx_flash_register(void) + + return platform_device_register(&mtd_dev); + case BCM63XX_FLASH_TYPE_SERIAL: +- pr_warn("unsupported serial flash detected\n"); +- return -ENODEV; ++ if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || ++ BCMCPU_IS_63268()) { ++ bcm63xx_spi_flash_info[0].bus_num = 1; ++ bcm63xx_spi_flash_info[0].mode = SPI_RX_DUAL; ++ } ++ ++ if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) ++ bcm63xx_flash_data.max_transfer_len = SPI_6358_MSG_DATA_SIZE; ++ ++ return spi_register_board_info(bcm63xx_spi_flash_info, ++ ARRAY_SIZE(bcm63xx_spi_flash_info)); + case BCM63XX_FLASH_TYPE_NAND: + pr_warn("unsupported NAND flash detected\n"); + return -ENODEV; +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +@@ -708,6 +708,7 @@ + #define GPIO_STRAPBUS_REG 0x40 + #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) + #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) ++#define STRAPBUS_6368_SPI_CLK_FAST (1 << 6) + #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 + #define STRAPBUS_6368_BOOT_SEL_NAND 0 + #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 +@@ -1564,6 +1565,7 @@ + #define IDDQ_CTRL_63268_USBH (1 << 4) + + #define MISC_STRAPBUS_6328_REG 0x240 ++#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4) + #define STRAPBUS_6328_FCVO_SHIFT 7 + #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) + #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) diff --git a/target/linux/brcm63xx/patches-4.1/412-MTD-physmap-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-4.1/412-MTD-physmap-allow-passing-pp_data.patch new file mode 100644 index 0000000..3511120 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/412-MTD-physmap-allow-passing-pp_data.patch @@ -0,0 +1,41 @@ +From 266c506f4b262bd6aba0776a03d82c98e65d9906 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 1 May 2012 17:32:36 +0200 +Subject: [PATCH 63/79] MTD: physmap: allow passing pp_data + +--- + drivers/mtd/maps/physmap.c | 4 +++- + include/linux/mtd/physmap.h | 1 + + 2 files changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/physmap.c ++++ b/drivers/mtd/maps/physmap.c +@@ -96,6 +96,7 @@ static int physmap_flash_probe(struct pl + { + struct physmap_flash_data *physmap_data; + struct physmap_flash_info *info; ++ struct mtd_part_parser_data *pp_data; + const char * const *probe_type; + const char * const *part_types; + int err = 0; +@@ -187,8 +188,9 @@ static int physmap_flash_probe(struct pl + spin_lock_init(&info->vpp_lock); + + part_types = physmap_data->part_probe_types ? : part_probe_types; ++ pp_data = physmap_data->pp_data ? physmap_data->pp_data : NULL; + +- mtd_device_parse_register(info->cmtd, part_types, NULL, ++ mtd_device_parse_register(info->cmtd, part_types, pp_data, + physmap_data->parts, physmap_data->nr_parts); + return 0; + +--- a/include/linux/mtd/physmap.h ++++ b/include/linux/mtd/physmap.h +@@ -31,6 +31,7 @@ struct physmap_flash_data { + char *probe_type; + struct mtd_partition *parts; + const char * const *part_probe_types; ++ struct mtd_part_parser_data *pp_data; + }; + + #endif /* __LINUX_MTD_PHYSMAP__ */ diff --git a/target/linux/brcm63xx/patches-4.1/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch b/target/linux/brcm63xx/patches-4.1/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch new file mode 100644 index 0000000..5f830dd --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch @@ -0,0 +1,72 @@ +From 8879e209111192c5e9752d7bd203cf7582693328 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 3 May 2012 14:40:03 +0200 +Subject: [PATCH 58/72] BCM63XX: allow providing fixup data in board data + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 9 ++++++++- + arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 10 ++++++++++ + 2 files changed, 18 insertions(+), 1 deletion(-) + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -35,6 +35,7 @@ + #include + #include + #include ++#include + + #include "board_common.h" + +@@ -181,6 +182,7 @@ static struct of_device_id of_ids[] = { + int __init board_register_devices(void) + { + int usbh_ports = 0; ++ int i; + + #if CONFIG_OF + if (of_have_populated_dt()) { +@@ -264,6 +266,10 @@ int __init board_register_devices(void) + board.ephy_reset_gpio_flags); + } + ++ /* register any fixups */ ++ for (i = 0; i < board.has_caldata; i++) ++ pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset); ++ + return 0; + } + +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + + /* + * flash mapping +@@ -16,6 +17,11 @@ + #define BCM963XX_CFE_VERSION_OFFSET 0x570 + #define BCM963XX_NVRAM_OFFSET 0x580 + ++struct ath9k_caldata { ++ unsigned int slot; ++ u32 caldata_offset; ++}; ++ + /* + * board definition + */ +@@ -36,6 +42,10 @@ struct board_info { + unsigned int has_uart0:1; + unsigned int has_uart1:1; + unsigned int use_fallback_sprom:1; ++ unsigned int has_caldata:2; ++ ++ /* wifi calibration data config */ ++ struct ath9k_caldata caldata[2]; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; diff --git a/target/linux/brcm63xx/patches-4.1/414-MTD-m25p80-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-4.1/414-MTD-m25p80-allow-passing-pp_data.patch new file mode 100644 index 0000000..9a8cdf5 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/414-MTD-m25p80-allow-passing-pp_data.patch @@ -0,0 +1,40 @@ +From 7f17dfe9009beb07a3de0e380932a725293829df Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 1 May 2012 17:33:03 +0200 +Subject: [PATCH 64/79] MTD: m25p80: allow passing pp_data + +--- + drivers/mtd/devices/m25p80.c | 3 +++ + include/linux/spi/flash.h | 2 ++ + 2 files changed, 5 insertions(+) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -255,6 +255,9 @@ static int m25p_probe(struct spi_device + if (data) + flash->max_transfer_len = data->max_transfer_len; + ++ if (data && data->pp_data) ++ memcpy(&ppdata, data->pp_data, sizeof(ppdata)); ++ + ret = spi_nor_scan(nor, flash_name, mode); + if (ret) + return ret; +--- a/include/linux/spi/flash.h ++++ b/include/linux/spi/flash.h +@@ -12,6 +12,7 @@ struct mtd_part_parser_data; + * with chips that can't be queried for JEDEC or other IDs + * @part_probe_types: optional list of MTD parser names to use for + * partitioning ++ * @pp_data: optional partition parser data. + * + * @max_transfer_len: option maximum read/write length limitation for + * SPI controllers not able to transfer any length commands. +@@ -30,6 +31,7 @@ struct flash_platform_data { + char *type; + + const char **part_probe_types; ++ struct mtd_part_parser_data *pp_data; + + unsigned int max_transfer_len; + /* we'll likely add more ... use JEDEC IDs, etc */ diff --git a/target/linux/brcm63xx/patches-4.1/415-MIPS-BCM63XX-export-the-attached-flash-type.patch b/target/linux/brcm63xx/patches-4.1/415-MIPS-BCM63XX-export-the-attached-flash-type.patch new file mode 100644 index 0000000..d874059 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/415-MIPS-BCM63XX-export-the-attached-flash-type.patch @@ -0,0 +1,31 @@ +From 066f1e37742ee434496d32a41a9284458de96742 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 13 Jan 2014 12:12:30 +0100 +Subject: [PATCH] MIPS: BCM63XX: export the attached flash type + +Signed-off-by: Jonas Gorski +--- + arch/mips/bcm63xx/dev-flash.c | 5 +++++ + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++ + 2 files changed, 7 insertions(+) + +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -252,3 +252,8 @@ int __init bcm63xx_flash_register(void) + return -ENODEV; + } + } ++ ++int bcm63xx_flash_get_type(void) ++{ ++ return flash_type; ++} +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -13,4 +13,6 @@ void bcm63xx_flash_force_phys_base_addre + + int __init bcm63xx_flash_register(void); + ++int bcm63xx_flash_get_type(void); ++ + #endif /* __BCM63XX_FLASH_H */ diff --git a/target/linux/brcm63xx/patches-4.1/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch b/target/linux/brcm63xx/patches-4.1/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch new file mode 100644 index 0000000..7a7c825 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch @@ -0,0 +1,236 @@ +From bbebbf735a02b6d044ed928978ab4bd5f1833364 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 3 May 2012 14:36:11 +0200 +Subject: [PATCH 61/72] BCM63XX: add a fixup for ath9k devices + +--- + arch/mips/bcm63xx/Makefile | 3 +- + arch/mips/bcm63xx/pci-ath9k-fixup.c | 190 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/pci_ath9k_fixup.h | 7 + + 3 files changed, 199 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/pci-ath9k-fixup.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ + dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ +- usb-common.o sprom.o ++ pci-ath9k-fixup.o usb-common.o sprom.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- /dev/null ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -0,0 +1,199 @@ ++/* ++ * Broadcom BCM63XX Ath9k EEPROM fixup helper. ++ * ++ * Copytight (C) 2012 Jonas Gorski ++ * ++ * Based on ++ * ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define bcm_hsspi_writel(v, o) bcm_rset_writel(RSET_HSSPI, (v), (o)) ++ ++struct ath9k_fixup { ++ unsigned slot; ++ u8 mac[ETH_ALEN]; ++ struct ath9k_platform_data pdata; ++}; ++ ++static int ath9k_num_fixups; ++static struct ath9k_fixup ath9k_fixups[2] = { ++ { ++ .slot = 255, ++ .pdata = { ++ .led_pin = -1, ++ }, ++ }, ++ { ++ .slot = 255, ++ .pdata = { ++ .led_pin = -1, ++ }, ++ }, ++}; ++ ++static u16 *bcm63xx_read_eeprom(u16 *eeprom, u32 offset) ++{ ++ u32 addr; ++ ++ if (BCMCPU_IS_6328()) { ++ addr = 0x18000000; ++ } else { ++ addr = bcm_mpi_readl(MPI_CSBASE_REG(0)); ++ addr &= MPI_CSBASE_BASE_MASK; ++ } ++ ++ switch (bcm63xx_flash_get_type()) { ++ case BCM63XX_FLASH_TYPE_PARALLEL: ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ return eeprom; ++ case BCM63XX_FLASH_TYPE_SERIAL: ++ /* the first megabyte is memory mapped */ ++ if (offset < 0x100000) { ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ return eeprom; ++ } ++ ++ if (BCMCPU_IS_6328()) { ++ /* we can change the memory mapped megabyte */ ++ bcm_hsspi_writel(offset & 0xf00000, 0x18); ++ memcpy(eeprom, (void *)KSEG1ADDR(addr + (offset & 0xfffff)), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); ++ bcm_hsspi_writel(0, 0x18); ++ return eeprom; ++ } ++ /* can't do anything here without talking to the SPI controller. */ ++ case BCM63XX_FLASH_TYPE_NAND: ++ default: ++ return NULL; ++ } ++} ++ ++static void ath9k_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ struct ath9k_platform_data *pdata = NULL; ++ struct pci_dev *bridge = pci_upstream_bridge(dev); ++ u16 *cal_data = NULL; ++ u16 cmd; ++ u32 bar0; ++ u32 val; ++ unsigned i; ++ ++ for (i = 0; i < ath9k_num_fixups; i++) { ++ if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ cal_data = ath9k_fixups[i].pdata.eeprom_data; ++ pdata = &ath9k_fixups[i].pdata; ++ break; ++ } ++ ++ if (cal_data == NULL) ++ return; ++ ++ if (*cal_data != 0xa55a) { ++ pr_err("pci %s: invalid calibration data\n", pci_name(dev)); ++ return; ++ } ++ ++ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); ++ ++ switch (bcm63xx_get_cpu_id()) { ++ case BCM6328_CPU_ID: ++ val = BCM_PCIE_MEM_BASE_PA_6328; ++ break; ++ case BCM6348_CPU_ID: ++ case BCM6358_CPU_ID: ++ case BCM6368_CPU_ID: ++ val = BCM_PCI_MEM_BASE_PA; ++ break; ++ default: ++ BUG(); ++ } ++ ++ mem = ioremap(val, 0x10000); ++ if (!mem) { ++ pr_err("pci %s: ioremap error\n", pci_name(dev)); ++ return; ++ } ++ ++ if (bridge) ++ pci_enable_device(bridge); ++ ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, val); ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ /* set offset to first reg address */ ++ cal_data += 3; ++ while(*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; ++ ++ writel(val, mem + reg); ++ udelay(100); ++ } ++ ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; ++ ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); ++ ++ if (bridge) ++ pci_disable_device(bridge); ++ ++ iounmap(mem); ++ ++ dev->dev.platform_data = pdata; ++} ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); ++ ++void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset) ++{ ++ if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) ++ return; ++ ++ ath9k_fixups[ath9k_num_fixups].slot = slot; ++ ++ if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) ++ return; ++ ++ if (bcm63xx_nvram_get_mac_address(ath9k_fixups[ath9k_num_fixups].mac)) ++ return; ++ ++ ath9k_fixups[ath9k_num_fixups].pdata.macaddr = ath9k_fixups[ath9k_num_fixups].mac; ++ ath9k_num_fixups++; ++} +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -0,0 +1,7 @@ ++#ifndef _PCI_ATH9K_FIXUP ++#define _PCI_ATH9K_FIXUP ++ ++ ++void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init; ++ ++#endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/brcm63xx/patches-4.1/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch b/target/linux/brcm63xx/patches-4.1/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch new file mode 100644 index 0000000..3b02c07 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch @@ -0,0 +1,120 @@ +Allow bcm63xxpart to receive a caldata offset if calibration data is +contained in flash. +--- + drivers/mtd/bcm63xxpart.c | 51 ++++++++++++++++++++++++++++++++++++--- + include/linux/mtd/partitions.h | 2 + + 2 files changed, 49 insertions(+), 4 deletions(-) + +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -53,10 +53,12 @@ static int bcm63xx_parse_cfe_partitions( + struct mtd_partition *parts; + int ret; + size_t retlen; +- unsigned int rootfsaddr, kerneladdr, spareaddr; ++ unsigned int rootfsaddr, kerneladdr, spareaddr, nvramaddr; + unsigned int rootfslen, kernellen, sparelen, totallen; + unsigned int cfelen, nvramlen; + unsigned int cfe_erasesize; ++ unsigned int caldatalen1 = 0, caldataaddr1 = 0; ++ unsigned int caldatalen2 = 0, caldataaddr2 = 0; + int i; + u32 computed_crc; + bool rootfs_first = false; +@@ -70,6 +72,24 @@ static int bcm63xx_parse_cfe_partitions( + cfelen = cfe_erasesize; + nvramlen = bcm63xx_nvram_get_psi_size() * SZ_1K; + nvramlen = roundup(nvramlen, cfe_erasesize); ++ nvramaddr = master->size - nvramlen; ++ ++ if (data) { ++ if (data->caldata[0]) { ++ caldatalen1 = cfe_erasesize; ++ caldataaddr1 = rounddown(data->caldata[0], ++ cfe_erasesize); ++ } ++ if (data->caldata[1]) { ++ caldatalen2 = cfe_erasesize; ++ caldataaddr2 = rounddown(data->caldata[1], ++ cfe_erasesize); ++ } ++ if (caldataaddr1 == caldataaddr2) { ++ caldataaddr2 = 0; ++ caldatalen2 = 0; ++ } ++ } + + /* Allocate memory for buffer */ + buf = vmalloc(sizeof(struct bcm_tag)); +@@ -121,7 +141,7 @@ static int bcm63xx_parse_cfe_partitions( + rootfsaddr = 0; + spareaddr = cfelen; + } +- sparelen = master->size - spareaddr - nvramlen; ++ sparelen = min_not_zero(nvramaddr, caldataaddr1) - spareaddr; + + /* Determine number of partitions */ + if (rootfslen > 0) +@@ -130,6 +150,12 @@ static int bcm63xx_parse_cfe_partitions( + if (kernellen > 0) + nrparts++; + ++ if (caldatalen1 > 0) ++ nrparts++; ++ ++ if (caldatalen2 > 0) ++ nrparts++; ++ + /* Ask kernel for more memory */ + parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL); + if (!parts) { +@@ -167,15 +193,32 @@ static int bcm63xx_parse_cfe_partitions( + curpart++; + } + ++ if (caldatalen1 > 0) { ++ if (caldatalen2 > 0) ++ parts[curpart].name = "cal_data1"; ++ else ++ parts[curpart].name = "cal_data"; ++ parts[curpart].offset = caldataaddr1; ++ parts[curpart].size = caldatalen1; ++ curpart++; ++ } ++ ++ if (caldatalen2 > 0) { ++ parts[curpart].name = "cal_data2"; ++ parts[curpart].offset = caldataaddr2; ++ parts[curpart].size = caldatalen2; ++ curpart++; ++ } ++ + parts[curpart].name = "nvram"; +- parts[curpart].offset = master->size - nvramlen; ++ parts[curpart].offset = nvramaddr; + parts[curpart].size = nvramlen; + curpart++; + + /* Global partition "linux" to make easy firmware upgrade */ + parts[curpart].name = "linux"; + parts[curpart].offset = cfelen; +- parts[curpart].size = master->size - cfelen - nvramlen; ++ parts[curpart].size = min_not_zero(nvramaddr, caldataaddr1) - cfelen; + + for (i = 0; i < nrparts; i++) + pr_info("Partition %d is %s offset %llx and length %llx\n", i, +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -56,10 +56,12 @@ struct device_node; + /** + * struct mtd_part_parser_data - used to pass data to MTD partition parsers. + * @origin: for RedBoot, start address of MTD device ++ * @caldata: for CFE, start address of wifi calibration data + * @of_node: for OF parsers, device node containing partitioning information + */ + struct mtd_part_parser_data { + unsigned long origin; ++ unsigned long caldata[2]; + struct device_node *of_node; + }; + diff --git a/target/linux/brcm63xx/patches-4.1/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch b/target/linux/brcm63xx/patches-4.1/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch new file mode 100644 index 0000000..374604f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch @@ -0,0 +1,83 @@ +From 977f8a30103b9c4992cab8f49357fe0d4274004f Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Thu, 3 May 2012 14:55:26 +0200 +Subject: [PATCH 69/80] MIPS: BCM63XX: pass caldata info to flash + +--- + arch/mips/bcm63xx/boards/board_common.c | 2 +- + arch/mips/bcm63xx/dev-flash.c | 9 ++++++++- + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 4 +++- + 3 files changed, 12 insertions(+), 3 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -254,7 +254,7 @@ int __init board_register_devices(void) + if (board.num_spis) + spi_register_board_info(board.spis, board.num_spis); + +- bcm63xx_flash_register(); ++ bcm63xx_flash_register(board.has_caldata, board.caldata); + + bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); + bcm63xx_led_data.leds = board.leds; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -38,12 +38,15 @@ static struct mtd_partition mtd_partitio + } + }; + ++static struct mtd_part_parser_data bcm63xx_parser_data; ++ + static const char *bcm63xx_part_types[] = { "bcm63xxpart", "RedBoot", NULL }; + + static struct physmap_flash_data flash_data = { + .width = 2, + .parts = mtd_partitions, + .part_probe_types = bcm63xx_part_types, ++ .pp_data = &bcm63xx_parser_data, + }; + + static struct resource mtd_resources[] = { +@@ -71,6 +74,7 @@ void __init bcm63xx_flash_force_phys_bas + + static struct flash_platform_data bcm63xx_flash_data = { + .part_probe_types = bcm63xx_part_types, ++ .pp_data = &bcm63xx_parser_data, + }; + + static struct spi_board_info bcm63xx_spi_flash_info[] = { +@@ -211,9 +215,13 @@ void __init bcm63xx_flash_detect(void) + } + } + +-int __init bcm63xx_flash_register(void) ++int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata) + { + u32 val; ++ unsigned int i; ++ ++ for (i = 0; i < num_caldata; i++) ++ bcm63xx_parser_data.caldata[i] = caldata[i].caldata_offset; + + switch (flash_type) { + case BCM63XX_FLASH_TYPE_PARALLEL: +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -1,6 +1,8 @@ + #ifndef __BCM63XX_FLASH_H + #define __BCM63XX_FLASH_H + ++#include ++ + enum { + BCM63XX_FLASH_TYPE_PARALLEL, + BCM63XX_FLASH_TYPE_SERIAL, +@@ -11,7 +13,7 @@ void bcm63xx_flash_detect(void); + + void bcm63xx_flash_force_phys_base_address(u32 start, u32 end); + +-int __init bcm63xx_flash_register(void); ++int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata); + + int bcm63xx_flash_get_type(void); + diff --git a/target/linux/brcm63xx/patches-4.1/420-BCM63XX-add-endian-check-for-ath9k.patch b/target/linux/brcm63xx/patches-4.1/420-BCM63XX-add-endian-check-for-ath9k.patch new file mode 100644 index 0000000..9d75f3a --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/420-BCM63XX-add-endian-check-for-ath9k.patch @@ -0,0 +1,51 @@ +--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -2,6 +2,7 @@ + #define _PCI_ATH9K_FIXUP + + +-void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init; ++void pci_enable_ath9k_fixup(unsigned slot, u32 offset, ++ unsigned endian_check) __init; + + #endif /* _PCI_ATH9K_FIXUP */ +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -20,6 +20,7 @@ + struct ath9k_caldata { + unsigned int slot; + u32 caldata_offset; ++ unsigned int endian_check:1; + }; + + /* +--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -181,12 +181,14 @@ static void ath9k_pci_fixup(struct pci_d + } + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + +-void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset) ++void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset, ++ unsigned endian_check) + { + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; ++ ath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check; + + if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) + return; +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -268,7 +268,8 @@ int __init board_register_devices(void) + + /* register any fixups */ + for (i = 0; i < board.has_caldata; i++) +- pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset); ++ pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, ++ board.caldata[i].endian_check); + + return 0; + } diff --git a/target/linux/brcm63xx/patches-4.1/421-BCM63XX-add-led-pin-for-ath9k.patch b/target/linux/brcm63xx/patches-4.1/421-BCM63XX-add-led-pin-for-ath9k.patch new file mode 100644 index 0000000..84a26be --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/421-BCM63XX-add-led-pin-for-ath9k.patch @@ -0,0 +1,49 @@ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -269,7 +269,7 @@ int __init board_register_devices(void) + /* register any fixups */ + for (i = 0; i < board.has_caldata; i++) + pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, +- board.caldata[i].endian_check); ++ board.caldata[i].endian_check, board.caldata[i].led_pin); + + return 0; + } +--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c ++++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c +@@ -182,13 +182,14 @@ static void ath9k_pci_fixup(struct pci_d + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); + + void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset, +- unsigned endian_check) ++ unsigned endian_check, int led_pin) + { + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) + return; + + ath9k_fixups[ath9k_num_fixups].slot = slot; + ath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check; ++ ath9k_fixups[ath9k_num_fixups].pdata.led_pin = led_pin; + + if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) + return; +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -21,6 +21,7 @@ struct ath9k_caldata { + unsigned int slot; + u32 caldata_offset; + unsigned int endian_check:1; ++ int led_pin; + }; + + /* +--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h +@@ -3,6 +3,6 @@ + + + void pci_enable_ath9k_fixup(unsigned slot, u32 offset, +- unsigned endian_check) __init; ++ unsigned endian_check, int led_pin) __init; + + #endif /* _PCI_ATH9K_FIXUP */ diff --git a/target/linux/brcm63xx/patches-4.1/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch b/target/linux/brcm63xx/patches-4.1/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch new file mode 100644 index 0000000..47273b8 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch @@ -0,0 +1,206 @@ +From 5ed5b5e9614fa5b02da699ab565af76c7e63d64d Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 7 Jan 2013 17:45:39 +0100 +Subject: [PATCH 72/72] 446-BCM63XX-add-a-fixup-for-rt2x00-devices + +--- + arch/mips/bcm63xx/Makefile | 2 +- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 17 ++++- + arch/mips/bcm63xx/dev-flash.c | 2 +- + arch/mips/bcm63xx/pci-rt2x00-fixup.c | 71 ++++++++++++++++++++ + .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 +- + .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 9 ++- + .../include/asm/mach-bcm63xx/pci_rt2x00_fixup.h | 9 +++ + 7 files changed, 104 insertions(+), 8 deletions(-) + create mode 100644 arch/mips/bcm63xx/pci-rt2x00-fixup.c + create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_rt2x00_fixup.h + +--- a/arch/mips/bcm63xx/Makefile ++++ b/arch/mips/bcm63xx/Makefile +@@ -2,7 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o + setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ + dev-wdt.o dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o \ +- pci-ath9k-fixup.o usb-common.o sprom.o ++ pci-ath9k-fixup.o pci-rt2x00-fixup.o usb-common.o sprom.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-y += boards/ +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + #include "board_common.h" + +@@ -267,9 +268,19 @@ int __init board_register_devices(void) + } + + /* register any fixups */ +- for (i = 0; i < board.has_caldata; i++) +- pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset, +- board.caldata[i].endian_check, board.caldata[i].led_pin); ++ for (i = 0; i < board.has_caldata; i++) { ++ switch (board.caldata[i].vendor) { ++ case PCI_VENDOR_ID_ATHEROS: ++ pci_enable_ath9k_fixup(board.caldata[i].slot, ++ board.caldata[i].caldata_offset, board.caldata[i].endian_check, ++ board.caldata[i].led_pin); ++ break; ++ case PCI_VENDOR_ID_RALINK: ++ pci_enable_rt2x00_fixup(board.caldata[i].slot, ++ board.caldata[i].eeprom); ++ break; ++ } ++ } + + return 0; + } +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -215,7 +215,7 @@ void __init bcm63xx_flash_detect(void) + } + } + +-int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata) ++int __init bcm63xx_flash_register(int num_caldata, struct bcm63xx_caldata *caldata) + { + u32 val; + unsigned int i; +--- /dev/null ++++ b/arch/mips/bcm63xx/pci-rt2x00-fixup.c +@@ -0,0 +1,72 @@ ++/* ++ * Broadcom BCM63XX RT2x00 EEPROM fixup helper. ++ * ++ * Copyright (C) 2012 Ãlvaro Fernández Rojas ++ * ++ * Based on ++ * ++ * Broadcom BCM63XX Ath9k EEPROM fixup helper. ++ * ++ * Copyright (C) 2012 Jonas Gorski ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct rt2x00_fixup { ++ unsigned slot; ++ u8 mac[ETH_ALEN]; ++ struct rt2x00_platform_data pdata; ++}; ++ ++static int rt2x00_num_fixups; ++static struct rt2x00_fixup rt2x00_fixups[2] = { ++ { ++ .slot = 255, ++ }, ++ { ++ .slot = 255, ++ }, ++}; ++ ++static void rt2x00_pci_fixup(struct pci_dev *dev) ++{ ++ unsigned i; ++ struct rt2x00_platform_data *pdata = NULL; ++ ++ for (i = 0; i < rt2x00_num_fixups; i++) { ++ if (rt2x00_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ pdata = &rt2x00_fixups[i].pdata; ++ break; ++ } ++ ++ dev->dev.platform_data = pdata; ++} ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RALINK, PCI_ANY_ID, rt2x00_pci_fixup); ++ ++void __init pci_enable_rt2x00_fixup(unsigned slot, char* eeprom) ++{ ++ if (rt2x00_num_fixups >= ARRAY_SIZE(rt2x00_fixups)) ++ return; ++ ++ rt2x00_fixups[rt2x00_num_fixups].slot = slot; ++ rt2x00_fixups[rt2x00_num_fixups].pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL); ++ ++ if (bcm63xx_nvram_get_mac_address(rt2x00_fixups[rt2x00_num_fixups].mac)) ++ return; ++ ++ rt2x00_fixups[rt2x00_num_fixups].pdata.mac_address = rt2x00_fixups[rt2x00_num_fixups].mac; ++ rt2x00_num_fixups++; ++} ++ +--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h ++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +@@ -13,7 +13,7 @@ void bcm63xx_flash_detect(void); + + void bcm63xx_flash_force_phys_base_address(u32 start, u32 end); + +-int __init bcm63xx_flash_register(int num_caldata, struct ath9k_caldata *caldata); ++int __init bcm63xx_flash_register(int num_caldata, struct bcm63xx_caldata *caldata); + + int bcm63xx_flash_get_type(void); + +--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h ++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + /* + * flash mapping +@@ -17,11 +18,15 @@ + #define BCM963XX_CFE_VERSION_OFFSET 0x570 + #define BCM963XX_NVRAM_OFFSET 0x580 + +-struct ath9k_caldata { ++struct bcm63xx_caldata { ++ unsigned int vendor; + unsigned int slot; + u32 caldata_offset; ++ /* Atheros */ + unsigned int endian_check:1; + int led_pin; ++ /* Ralink */ ++ char* eeprom; + }; + + /* +@@ -47,7 +52,7 @@ struct board_info { + unsigned int has_caldata:2; + + /* wifi calibration data config */ +- struct ath9k_caldata caldata[2]; ++ struct bcm63xx_caldata caldata[2]; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; +--- /dev/null ++++ b/arch/mips/include/asm/mach-bcm63xx/pci_rt2x00_fixup.h +@@ -0,0 +1,9 @@ ++#ifndef _PCI_RT2X00_FIXUP ++#define _PCI_RT2X00_FIXUP ++ ++#define PCI_VENDOR_ID_RALINK 0x1814 ++ ++void pci_enable_rt2x00_fixup(unsigned slot, char* eeprom) __init; ++ ++#endif /* _PCI_RT2X00_FIXUP */ ++ diff --git a/target/linux/brcm63xx/patches-4.1/423-bcm63xx_enet_add_b53_support.patch b/target/linux/brcm63xx/patches-4.1/423-bcm63xx_enet_add_b53_support.patch new file mode 100644 index 0000000..f7697e1 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/423-bcm63xx_enet_add_b53_support.patch @@ -0,0 +1,169 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h +@@ -336,6 +336,9 @@ struct bcm_enet_priv { + struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT]; + int sw_port_link[ENETSW_MAX_PORT]; + ++ /* platform device for associated switch */ ++ struct platform_device *b53_device; ++ + /* used to poll switch port state */ + struct timer_list swphy_poll; + spinlock_t enetsw_mdio_lock; +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + + #include + #include "bcm63xx_enet.h" +@@ -1975,7 +1976,8 @@ static int bcm_enet_remove(struct platfo + return 0; + } + +-struct platform_driver bcm63xx_enet_driver = { ++ ++static struct platform_driver bcm63xx_enet_driver = { + .probe = bcm_enet_probe, + .remove = bcm_enet_remove, + .driver = { +@@ -1984,6 +1986,42 @@ struct platform_driver bcm63xx_enet_driv + }, + }; + ++struct b53_platform_data bcm63xx_b53_pdata = { ++ .chip_id = 0x6300, ++ .big_endian = 1, ++}; ++ ++struct platform_device bcm63xx_b53_dev = { ++ .name = "b53-switch", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm63xx_b53_pdata, ++ }, ++}; ++ ++static int bcmenet_switch_register(struct bcm_enet_priv *priv, u16 port_mask) ++{ ++ int ret; ++ ++ bcm63xx_b53_pdata.regs = priv->base; ++ bcm63xx_b53_pdata.enabled_ports = port_mask; ++ bcm63xx_b53_pdata.alias = priv->net_dev->name; ++ ++ ret = platform_device_register(&bcm63xx_b53_dev); ++ if (!ret) ++ priv->b53_device = &bcm63xx_b53_dev; ++ ++ return ret; ++} ++ ++static void bcmenet_switch_unregister(struct bcm_enet_priv *priv) ++{ ++ if (priv->b53_device) ++ platform_device_unregister(&bcm63xx_b53_dev); ++ ++ priv->b53_device = NULL; ++} ++ + /* + * switch mii access callbacks + */ +@@ -2237,29 +2275,6 @@ static int bcm_enetsw_open(struct net_de + enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); + } + +- /* reset mib */ +- val = enetsw_readb(priv, ENETSW_GMCR_REG); +- val |= ENETSW_GMCR_RST_MIB_MASK; +- enetsw_writeb(priv, val, ENETSW_GMCR_REG); +- mdelay(1); +- val &= ~ENETSW_GMCR_RST_MIB_MASK; +- enetsw_writeb(priv, val, ENETSW_GMCR_REG); +- mdelay(1); +- +- /* force CPU port state */ +- val = enetsw_readb(priv, ENETSW_IMPOV_REG); +- val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; +- enetsw_writeb(priv, val, ENETSW_IMPOV_REG); +- +- /* enable switch forward engine */ +- val = enetsw_readb(priv, ENETSW_SWMODE_REG); +- val |= ENETSW_SWMODE_FWD_EN_MASK; +- enetsw_writeb(priv, val, ENETSW_SWMODE_REG); +- +- /* enable jumbo on all ports */ +- enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); +- enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); +- + /* initialize flow control buffer allocation */ + enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, + ENETDMA_BUFALLOC_REG(priv->rx_chan)); +@@ -2719,6 +2734,9 @@ static int bcm_enetsw_probe(struct platf + struct bcm63xx_enetsw_platform_data *pd; + struct resource *res_mem; + int ret, irq_rx, irq_tx; ++ unsigned i, num_ports = 0; ++ u16 port_mask = BIT(8); ++ u8 val; + + /* stop if shared driver failed, assume driver->probe will be + * called in the same order we register devices (correct ?) +@@ -2808,6 +2826,43 @@ static int bcm_enetsw_probe(struct platf + priv->pdev = pdev; + priv->net_dev = dev; + ++ /* reset mib */ ++ val = enetsw_readb(priv, ENETSW_GMCR_REG); ++ val |= ENETSW_GMCR_RST_MIB_MASK; ++ enetsw_writeb(priv, val, ENETSW_GMCR_REG); ++ mdelay(1); ++ val &= ~ENETSW_GMCR_RST_MIB_MASK; ++ enetsw_writeb(priv, val, ENETSW_GMCR_REG); ++ mdelay(1); ++ ++ /* force CPU port state */ ++ val = enetsw_readb(priv, ENETSW_IMPOV_REG); ++ val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK; ++ enetsw_writeb(priv, val, ENETSW_IMPOV_REG); ++ ++ /* enable switch forward engine */ ++ val = enetsw_readb(priv, ENETSW_SWMODE_REG); ++ val |= ENETSW_SWMODE_FWD_EN_MASK; ++ enetsw_writeb(priv, val, ENETSW_SWMODE_REG); ++ ++ /* enable jumbo on all ports */ ++ enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG); ++ enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG); ++ ++ for (i = 0; i < priv->num_ports; i++) { ++ struct bcm63xx_enetsw_port *port = &priv->used_ports[i]; ++ ++ if (!port->used) ++ continue; ++ ++ num_ports++; ++ port_mask |= BIT(i); ++ } ++ ++ /* only register if there is more than one external port */ ++ if (num_ports > 1) ++ bcmenet_switch_register(priv, port_mask); ++ + return 0; + + out_put_clk: +@@ -2836,6 +2891,9 @@ static int bcm_enetsw_remove(struct plat + priv = netdev_priv(dev); + unregister_netdev(dev); + ++ /* remove switch */ ++ bcmenet_switch_unregister(priv); ++ + /* release device resources */ + iounmap(priv->base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/brcm63xx/patches-4.1/424-bcm63xx_enet_no_request_mem_region.patch b/target/linux/brcm63xx/patches-4.1/424-bcm63xx_enet_no_request_mem_region.patch new file mode 100644 index 0000000..a087308 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/424-bcm63xx_enet_no_request_mem_region.patch @@ -0,0 +1,15 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2781,12 +2781,6 @@ static int bcm_enetsw_probe(struct platf + if (ret) + goto out; + +- if (!request_mem_region(res_mem->start, resource_size(res_mem), +- "bcm63xx_enetsw")) { +- ret = -EBUSY; +- goto out; +- } +- + priv->base = ioremap(res_mem->start, resource_size(res_mem)); + if (priv->base == NULL) { + ret = -ENOMEM; diff --git a/target/linux/brcm63xx/patches-4.1/425-bcm63xxpart_parse_paritions_from_dt.patch b/target/linux/brcm63xx/patches-4.1/425-bcm63xxpart_parse_paritions_from_dt.patch new file mode 100644 index 0000000..53fc4c5 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/425-bcm63xxpart_parse_paritions_from_dt.patch @@ -0,0 +1,357 @@ +--- a/drivers/mtd/bcm63xxpart.c ++++ b/drivers/mtd/bcm63xxpart.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -43,66 +44,35 @@ + + #define BCM63XX_CFE_MAGIC_OFFSET 0x4e0 + +-static int bcm63xx_parse_cfe_partitions(struct mtd_info *master, +- struct mtd_partition **pparts, +- struct mtd_part_parser_data *data) ++static bool node_has_compatible(struct device_node *pp) ++{ ++ return of_get_property(pp, "compatible", NULL); ++} ++ ++static int parse_bcmtag(struct mtd_info *master, struct mtd_partition *pparts, ++ int next_part, size_t offset, size_t size) + { +- /* CFE, NVRAM and global Linux are always present */ +- int nrparts = 3, curpart = 0; + struct bcm_tag *buf; +- struct mtd_partition *parts; ++ u32 computed_crc; + int ret; + size_t retlen; +- unsigned int rootfsaddr, kerneladdr, spareaddr, nvramaddr; +- unsigned int rootfslen, kernellen, sparelen, totallen; +- unsigned int cfelen, nvramlen; +- unsigned int cfe_erasesize; +- unsigned int caldatalen1 = 0, caldataaddr1 = 0; +- unsigned int caldatalen2 = 0, caldataaddr2 = 0; +- int i; +- u32 computed_crc; ++ unsigned int rootfsaddr, kerneladdr; ++ unsigned int rootfslen, kernellen, totallen; + bool rootfs_first = false; +- +- if (!bcm63xx_is_cfe_present()) +- return -EINVAL; +- +- cfe_erasesize = max_t(uint32_t, master->erasesize, +- BCM63XX_CFE_BLOCK_SIZE); +- +- cfelen = cfe_erasesize; +- nvramlen = bcm63xx_nvram_get_psi_size() * SZ_1K; +- nvramlen = roundup(nvramlen, cfe_erasesize); +- nvramaddr = master->size - nvramlen; +- +- if (data) { +- if (data->caldata[0]) { +- caldatalen1 = cfe_erasesize; +- caldataaddr1 = rounddown(data->caldata[0], +- cfe_erasesize); +- } +- if (data->caldata[1]) { +- caldatalen2 = cfe_erasesize; +- caldataaddr2 = rounddown(data->caldata[1], +- cfe_erasesize); +- } +- if (caldataaddr1 == caldataaddr2) { +- caldataaddr2 = 0; +- caldatalen2 = 0; +- } +- } ++ int curr_part = next_part; + + /* Allocate memory for buffer */ +- buf = vmalloc(sizeof(struct bcm_tag)); ++ buf = vmalloc(sizeof(*buf)); + if (!buf) + return -ENOMEM; + + /* Get the tag */ +- ret = mtd_read(master, cfelen, sizeof(struct bcm_tag), &retlen, ++ ret = mtd_read(master, offset, sizeof(*buf), &retlen, + (void *)buf); + +- if (retlen != sizeof(struct bcm_tag)) { ++ if (retlen != sizeof(*buf)) { + vfree(buf); +- return -EIO; ++ return 0; + } + + computed_crc = crc32_le(IMAGETAG_CRC_START, (u8 *)buf, +@@ -121,7 +91,6 @@ static int bcm63xx_parse_cfe_partitions( + + kerneladdr = kerneladdr - BCM63XX_EXTENDED_SIZE; + rootfsaddr = rootfsaddr - BCM63XX_EXTENDED_SIZE; +- spareaddr = roundup(totallen, master->erasesize) + cfelen; + + if (rootfsaddr < kerneladdr) { + /* default Broadcom layout */ +@@ -130,8 +99,8 @@ static int bcm63xx_parse_cfe_partitions( + } else { + /* OpenWrt layout */ + rootfsaddr = kerneladdr + kernellen; +- rootfslen = buf->real_rootfs_length; +- spareaddr = rootfsaddr + rootfslen; ++ rootfslen = size - kernellen - ++ sizeof(*buf); + } + } else { + pr_warn("CFE boot tag CRC invalid (expected %08x, actual %08x)\n", +@@ -139,16 +108,153 @@ static int bcm63xx_parse_cfe_partitions( + kernellen = 0; + rootfslen = 0; + rootfsaddr = 0; +- spareaddr = cfelen; + } +- sparelen = min_not_zero(nvramaddr, caldataaddr1) - spareaddr; + +- /* Determine number of partitions */ +- if (rootfslen > 0) +- nrparts++; ++ if (kernellen > 0) { ++ int kernelpart = curr_part; + +- if (kernellen > 0) +- nrparts++; ++ if (rootfslen > 0 && rootfs_first) ++ kernelpart++; ++ pparts[kernelpart].name = "kernel"; ++ pparts[kernelpart].offset = kerneladdr; ++ pparts[kernelpart].size = kernellen; ++ curr_part++; ++ } ++ ++ if (rootfslen > 0) { ++ int rootfspart = curr_part; ++ ++ if (kernellen > 0 && rootfs_first) ++ rootfspart--; ++ pparts[rootfspart].name = "rootfs"; ++ pparts[rootfspart].offset = rootfsaddr; ++ pparts[rootfspart].size = rootfslen; ++ ++ curr_part++; ++ } ++ ++ vfree(buf); ++ ++ return curr_part - next_part; ++} ++ ++ ++static int bcm63xx_parse_cfe_partitions_of(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct device_node *dp = data->of_node; ++ struct device_node *pp; ++ int i, nr_parts = 0; ++ const char *partname; ++ int len; ++ ++ for_each_child_of_node(dp, pp) { ++ if (node_has_compatible(pp)) ++ continue; ++ ++ if (!of_get_property(pp, "reg", &len)) ++ continue; ++ ++ partname = of_get_property(pp, "label", &len); ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ ++ if (!strcmp(partname, "linux")) ++ nr_parts += 2; ++ ++ nr_parts++; ++ } ++ ++ *pparts = kzalloc(nr_parts * sizeof(**pparts), GFP_KERNEL); ++ if (!*pparts) ++ return -ENOMEM; ++ ++ i = 0; ++ for_each_child_of_node(dp, pp) { ++ const __be32 *reg; ++ int a_cells, s_cells; ++ size_t size, offset; ++ ++ if (node_has_compatible(pp)) ++ continue; ++ ++ reg = of_get_property(pp, "reg", &len); ++ if (!reg) ++ continue; ++ ++ a_cells = of_n_addr_cells(pp); ++ s_cells = of_n_size_cells(pp); ++ offset = of_read_number(reg, a_cells); ++ size = of_read_number(reg + a_cells, s_cells); ++ partname = of_get_property(pp, "label", &len); ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ ++ if (!strcmp(partname, "linux")) ++ i += parse_bcmtag(master, *pparts, i, offset, size); ++ ++ if (of_get_property(pp, "read-only", &len)) ++ (*pparts)[i].mask_flags |= MTD_WRITEABLE; ++ ++ if (of_get_property(pp, "lock", &len)) ++ (*pparts)[i].mask_flags |= MTD_POWERUP_LOCK; ++ ++ (*pparts)[i].offset = offset; ++ (*pparts)[i].size = size; ++ (*pparts)[i].name = partname; ++ ++ i++; ++ } ++ ++ return i; ++} ++ ++static int bcm63xx_parse_cfe_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ /* CFE, NVRAM and global Linux are always present */ ++ int nrparts = 5, curpart = 0; ++ struct mtd_partition *parts; ++ unsigned int nvramaddr; ++ unsigned int cfelen, nvramlen; ++ unsigned int cfe_erasesize; ++ unsigned int caldatalen1 = 0, caldataaddr1 = 0; ++ unsigned int caldatalen2 = 0, caldataaddr2 = 0; ++ unsigned int imageaddr, imagelen; ++ int i; ++ ++ if (!bcm63xx_is_cfe_present()) ++ return -EINVAL; ++ ++ cfe_erasesize = max_t(uint32_t, master->erasesize, ++ BCM63XX_CFE_BLOCK_SIZE); ++ ++ cfelen = cfe_erasesize; ++ nvramlen = bcm63xx_nvram_get_psi_size() * SZ_1K; ++ nvramlen = roundup(nvramlen, cfe_erasesize); ++ nvramaddr = master->size - nvramlen; ++ ++ if (data) { ++ if (data->caldata[0]) { ++ caldatalen1 = cfe_erasesize; ++ caldataaddr1 = rounddown(data->caldata[0], ++ cfe_erasesize); ++ } ++ if (data->caldata[1]) { ++ caldatalen2 = cfe_erasesize; ++ caldataaddr2 = rounddown(data->caldata[1], ++ cfe_erasesize); ++ } ++ if (caldataaddr1 == caldataaddr2) { ++ caldataaddr2 = 0; ++ caldatalen2 = 0; ++ } ++ } ++ ++ imageaddr = cfelen; ++ imagelen = min_not_zero(nvramaddr, caldataaddr1) - imageaddr; + + if (caldatalen1 > 0) + nrparts++; +@@ -158,10 +264,8 @@ static int bcm63xx_parse_cfe_partitions( + + /* Ask kernel for more memory */ + parts = kzalloc(sizeof(*parts) * nrparts + 10 * nrparts, GFP_KERNEL); +- if (!parts) { +- vfree(buf); ++ if (!parts) + return -ENOMEM; +- } + + /* Start building partition list */ + parts[curpart].name = "CFE"; +@@ -169,29 +273,7 @@ static int bcm63xx_parse_cfe_partitions( + parts[curpart].size = cfelen; + curpart++; + +- if (kernellen > 0) { +- int kernelpart = curpart; +- +- if (rootfslen > 0 && rootfs_first) +- kernelpart++; +- parts[kernelpart].name = "kernel"; +- parts[kernelpart].offset = kerneladdr; +- parts[kernelpart].size = kernellen; +- curpart++; +- } +- +- if (rootfslen > 0) { +- int rootfspart = curpart; +- +- if (kernellen > 0 && rootfs_first) +- rootfspart--; +- parts[rootfspart].name = "rootfs"; +- parts[rootfspart].offset = rootfsaddr; +- parts[rootfspart].size = rootfslen; +- if (sparelen > 0 && !rootfs_first) +- parts[rootfspart].size += sparelen; +- curpart++; +- } ++ curpart += parse_bcmtag(master, parts, curpart, imageaddr, imagelen); + + if (caldatalen1 > 0) { + if (caldatalen2 > 0) +@@ -217,25 +299,33 @@ static int bcm63xx_parse_cfe_partitions( + + /* Global partition "linux" to make easy firmware upgrade */ + parts[curpart].name = "linux"; +- parts[curpart].offset = cfelen; +- parts[curpart].size = min_not_zero(nvramaddr, caldataaddr1) - cfelen; ++ parts[curpart].offset = imageaddr; ++ parts[curpart].size = imagelen; ++ curpart++; + +- for (i = 0; i < nrparts; i++) ++ for (i = 0; i < curpart; i++) + pr_info("Partition %d is %s offset %llx and length %llx\n", i, + parts[i].name, parts[i].offset, parts[i].size); + +- pr_info("Spare partition is offset %x and length %x\n", spareaddr, +- sparelen); +- + *pparts = parts; +- vfree(buf); + + return nrparts; + }; + ++ ++static int bcm63xx_parse_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ if (data && data->of_node) ++ return bcm63xx_parse_cfe_partitions_of(master, pparts, data); ++ else ++ return bcm63xx_parse_cfe_partitions(master, pparts, data); ++} ++ + static struct mtd_part_parser bcm63xx_cfe_parser = { + .owner = THIS_MODULE, +- .parse_fn = bcm63xx_parse_cfe_partitions, ++ .parse_fn = bcm63xx_parse_partitions, + .name = "bcm63xxpart", + }; + diff --git a/target/linux/brcm63xx/patches-4.1/427-boards_probe_switch.patch b/target/linux/brcm63xx/patches-4.1/427-boards_probe_switch.patch new file mode 100644 index 0000000..127d1ef --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/427-boards_probe_switch.patch @@ -0,0 +1,119 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -118,6 +118,8 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_enet0 = 1, + .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -161,6 +163,8 @@ static struct board_info __initdata boar + .has_uart0 = 1, + .has_enet0 = 1, + .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -272,6 +276,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -334,6 +340,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -388,6 +396,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -448,6 +458,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -471,6 +483,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -490,6 +504,8 @@ static struct board_info __initdata boar + .has_enet1 = 1, + .enet0 = { + .has_phy = 1, ++ .phy_id = 0, ++ .has_phy = 1, + .use_internal_phy = 1, + }, + .enet1 = { +@@ -513,6 +529,8 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -541,6 +559,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -594,6 +614,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -643,6 +665,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +@@ -666,6 +690,8 @@ static struct board_info __initdata boar + }, + + .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, + .force_speed_100 = 1, + .force_duplex_full = 1, + }, diff --git a/target/linux/brcm63xx/patches-4.1/499-allow_better_context_for_board_patches.patch b/target/linux/brcm63xx/patches-4.1/499-allow_better_context_for_board_patches.patch new file mode 100644 index 0000000..18a1cd4 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/499-allow_better_context_for_board_patches.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -56,7 +56,7 @@ static struct board_info __initdata boar + .ephy_reset_gpio = 36, + .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_3368 */ + + /* + * known 6328 boards +@@ -105,7 +105,7 @@ static struct board_info __initdata boar + }, + }, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6328 */ + + /* + * known 6338 boards +@@ -198,7 +198,7 @@ static struct board_info __initdata boar + }, + }, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6338 */ + + /* + * known 6345 boards +@@ -210,7 +210,7 @@ static struct board_info __initdata boar + + .has_uart0 = 1, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6345 */ + + /* + * known 6348 boards +@@ -537,7 +537,7 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* + * known 6358 boards +@@ -698,7 +698,7 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; +-#endif ++#endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* + * all boards diff --git a/target/linux/brcm63xx/patches-4.1/500-board-D4PW.patch b/target/linux/brcm63xx/patches-4.1/500-board-D4PW.patch new file mode 100644 index 0000000..b0d93b0 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/500-board-D4PW.patch @@ -0,0 +1,41 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -537,6 +537,22 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; ++ ++static struct board_info __initdata board_96348_D4PW = { ++ .name = "D-4P-W", ++ .expected_cpu_id = 0x6348, ++ ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .has_uart0 = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* +@@ -726,6 +742,7 @@ static const struct board_info __initcon + &board_DV201AMR, + &board_96348gw_a, + &board_rta1025w_16, ++ &board_96348_D4PW, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -757,6 +774,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, + { .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, }, + { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, ++ { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, diff --git a/target/linux/brcm63xx/patches-4.1/501-board-NB4.patch b/target/linux/brcm63xx/patches-4.1/501-board-NB4.patch new file mode 100644 index 0000000..35335fc --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/501-board-NB4.patch @@ -0,0 +1,83 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -714,6 +714,62 @@ static struct board_info __initdata boar + + .has_ohci0 = 1, + }; ++ ++static struct board_info __initdata board_nb4_ser_r0 = { ++ .name = "NB4-SER-r0", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++}; ++ ++static struct board_info __initdata board_nb4_fxc_r1 = { ++ .name = "NB4-FXC-r1", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++}; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* +@@ -750,6 +806,8 @@ static const struct board_info __initcon + &board_96358vw2, + &board_AGPFS0, + &board_DWVS0, ++ &board_nb4_ser_r0, ++ &board_nb4_fxc_r1, + #endif + }; + +@@ -791,6 +849,8 @@ static struct of_device_id const bcm963x + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, }, + { .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, }, ++ { .compatible = "sfr,nb4-ser-r0", .data = &board_nb4_ser_r0, }, ++ { .compatible = "sfr,nb4-fxc-r1", .data = &board_nb4_fxc_r1, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 + #endif diff --git a/target/linux/brcm63xx/patches-4.1/502-board-96338W2_E7T.patch b/target/linux/brcm63xx/patches-4.1/502-board-96338W2_E7T.patch new file mode 100644 index 0000000..4bf4fd7 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/502-board-96338W2_E7T.patch @@ -0,0 +1,39 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -198,6 +198,20 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_96338w2_e7t = { ++ .name = "96338W2_E7T", ++ .expected_cpu_id = 0x6338, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6338 */ + + /* +@@ -785,6 +799,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, + &board_96338w, ++ &board_96338w2_e7t, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, +@@ -822,6 +837,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6338 + { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, + { .compatible = "brcm,bcm96338w", .data = &board_96338w, }, ++ { .compatible = "d-link,dsl-2640u", .data = &board_96338w2_e7t, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + { .compatible = "brcm,bcm96345gw2", .data = &board_96345gw2, }, diff --git a/target/linux/brcm63xx/patches-4.1/503-board-CPVA642.patch b/target/linux/brcm63xx/patches-4.1/503-board-CPVA642.patch new file mode 100644 index 0000000..8bdcdd0 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/503-board-CPVA642.patch @@ -0,0 +1,45 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -680,6 +680,26 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_CPVA642 = { ++ .name = "CPVA642", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++}; ++ ++ + static struct board_info __initdata board_AGPFS0 = { + .name = "AGPF-S0", + .expected_cpu_id = 0x6358, +@@ -820,6 +840,7 @@ static const struct board_info __initcon + &board_96358vw, + &board_96358vw2, + &board_AGPFS0, ++ &board_CPVA642, + &board_DWVS0, + &board_nb4_ser_r0, + &board_nb4_fxc_r1, +@@ -867,6 +888,7 @@ static struct of_device_id const bcm963x + { .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, }, + { .compatible = "sfr,nb4-ser-r0", .data = &board_nb4_ser_r0, }, + { .compatible = "sfr,nb4-fxc-r1", .data = &board_nb4_fxc_r1, }, ++ { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 + #endif diff --git a/target/linux/brcm63xx/patches-4.1/504-board_dsl_274xb_rev_c.patch b/target/linux/brcm63xx/patches-4.1/504-board_dsl_274xb_rev_c.patch new file mode 100644 index 0000000..0b89b42 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/504-board_dsl_274xb_rev_c.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -749,6 +749,23 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + }; + ++/* D-Link DSL-274xB revison C2/C3 */ ++static struct board_info __initdata board_dsl_274xb_rev_c = { ++ .name = "AW4139", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ + static struct board_info __initdata board_nb4_ser_r0 = { + .name = "NB4-SER-r0", + .expected_cpu_id = 0x6358, +@@ -842,6 +859,7 @@ static const struct board_info __initcon + &board_AGPFS0, + &board_CPVA642, + &board_DWVS0, ++ &board_dsl_274xb_rev_c, + &board_nb4_ser_r0, + &board_nb4_fxc_r1, + #endif +@@ -881,6 +899,7 @@ static struct of_device_id const bcm963x + { .compatible = "alcatel,rg100a", .data = &board_96358vw2, }, + { .compatible = "brcm,bcm96358vw", .data = &board_96358vw, }, + { .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, }, ++ { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, + { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, diff --git a/target/linux/brcm63xx/patches-4.1/505-board_spw500v.patch b/target/linux/brcm63xx/patches-4.1/505-board_spw500v.patch new file mode 100644 index 0000000..6391c89 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/505-board_spw500v.patch @@ -0,0 +1,64 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -567,6 +567,45 @@ static struct board_info __initdata boar + .force_duplex_full = 1, + }, + }; ++ ++static struct sprom_fixup __initdata spw500v_fixups[] = { ++ { .offset = 46, .value = 0x3046 }, ++ { .offset = 47, .value = 0x15a7 }, ++ { .offset = 48, .value = 0xfa89 }, ++ { .offset = 49, .value = 0xfe79 }, ++ { .offset = 57, .value = 0x6a49 }, ++}; ++ ++static struct board_info __initdata board_spw500v = { ++ .name = "SPW500V", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 6, ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = spw500v_fixups, ++ .num_board_fixups = ARRAY_SIZE(spw500v_fixups), ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* +@@ -851,6 +890,7 @@ static const struct board_info __initcon + &board_96348gw_a, + &board_rta1025w_16, + &board_96348_D4PW, ++ &board_spw500v, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -892,6 +932,7 @@ static struct of_device_id const bcm963x + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, + { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, ++ { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, + { .compatible = "usr,9108", .data = &board_96348gw_a, }, + #endif diff --git a/target/linux/brcm63xx/patches-4.1/506-board_gw6200_gw6000.patch b/target/linux/brcm63xx/patches-4.1/506-board_gw6200_gw6000.patch new file mode 100644 index 0000000..f25f451 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/506-board_gw6200_gw6000.patch @@ -0,0 +1,87 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -456,6 +456,66 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_gw6200 = { ++ .name = "GW6200", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 8, /* FIXME: What is real GPIO here? */ ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++}; ++ ++static struct board_info __initdata board_gw6000 = { ++ .name = "GW6000", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 6, ++ .gpio_int = 34, ++ .ext_irq = 2, ++ .cs = 2, ++ }, ++}; ++ ++ ++ + static struct board_info __initdata board_FAST2404 = { + .name = "F@ST2404", + .expected_cpu_id = 0x6348, +@@ -883,6 +943,8 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, + &board_96348gw, ++ &board_gw6000, ++ &board_gw6200, + &board_96348gw_10, + &board_96348gw_11, + &board_FAST2404, +@@ -933,6 +995,8 @@ static struct of_device_id const bcm963x + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, + { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, ++ { .compatible = "tecom,gw6000", .data = &board_gw6000, }, ++ { .compatible = "tecom,gw6200", .data = &board_gw6200, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, + { .compatible = "usr,9108", .data = &board_96348gw_a, }, + #endif diff --git a/target/linux/brcm63xx/patches-4.1/507-board-MAGIC.patch b/target/linux/brcm63xx/patches-4.1/507-board-MAGIC.patch new file mode 100644 index 0000000..d2d2416 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/507-board-MAGIC.patch @@ -0,0 +1,59 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -666,6 +666,40 @@ static struct board_info __initdata boar + .num_board_fixups = ARRAY_SIZE(spw500v_fixups), + }, + }; ++ ++static struct board_info __initdata board_96348sv = { ++ .name = "MAGIC", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ /* it has BP_ENET_EXTERNAL_PHY */ ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ ++ .has_dsp = 1, ++ .dsp = { ++ .gpio_rst = 25, ++ .gpio_int = 34, ++ .cs = 2, ++ .ext_irq = 2, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* +@@ -953,6 +987,7 @@ static const struct board_info __initcon + &board_rta1025w_16, + &board_96348_D4PW, + &board_spw500v, ++ &board_96348sv, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -997,6 +1032,7 @@ static struct of_device_id const bcm963x + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tecom,gw6000", .data = &board_gw6000, }, + { .compatible = "tecom,gw6200", .data = &board_gw6200, }, ++ { .compatible = "telsey,magic", .data = &board_96348sv, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, + { .compatible = "usr,9108", .data = &board_96348gw_a, }, + #endif diff --git a/target/linux/brcm63xx/patches-4.1/508-board_hw553.patch b/target/linux/brcm63xx/patches-4.1/508-board_hw553.patch new file mode 100644 index 0000000..8cc14fb --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/508-board_hw553.patch @@ -0,0 +1,53 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -954,6 +954,34 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + .num_usbh_ports = 2, + }; ++ ++static struct board_info __initdata board_HW553 = { ++ .name = "HW553", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* +@@ -999,6 +1027,7 @@ static const struct board_info __initcon + &board_dsl_274xb_rev_c, + &board_nb4_ser_r0, + &board_nb4_fxc_r1, ++ &board_HW553, + #endif + }; + +@@ -1042,6 +1071,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, }, + { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, ++ { .compatible = "huawei,hg553", .data = &board_HW553, }, + { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, }, diff --git a/target/linux/brcm63xx/patches-4.1/509-board_rta1320_16m.patch b/target/linux/brcm63xx/patches-4.1/509-board_rta1320_16m.patch new file mode 100644 index 0000000..0b0d970 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/509-board_rta1320_16m.patch @@ -0,0 +1,40 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -212,6 +212,21 @@ static struct board_info __initdata boar + .force_duplex_full = 1, + }, + }; ++ ++static struct board_info __initdata board_rta1320_16m = { ++ .name = "RTA1320_16M", ++ .expected_cpu_id = 0x6338, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6338 */ + + /* +@@ -998,6 +1013,7 @@ static const struct board_info __initcon + &board_96338gw, + &board_96338w, + &board_96338w2_e7t, ++ &board_rta1320_16m, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, +@@ -1042,6 +1058,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6338 + { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, + { .compatible = "brcm,bcm96338w", .data = &board_96338w, }, ++ { .compatible = "dynalink,rta1320", .data = &board_rta1320_16m, }, + { .compatible = "d-link,dsl-2640u", .data = &board_96338w2_e7t, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 diff --git a/target/linux/brcm63xx/patches-4.1/510-board_spw303v.patch b/target/linux/brcm63xx/patches-4.1/510-board_spw303v.patch new file mode 100644 index 0000000..c251e76 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/510-board_spw303v.patch @@ -0,0 +1,40 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -997,6 +997,21 @@ static struct board_info __initdata boar + .pci_dev = 1, + }, + }; ++ ++ /* T-Home Speedport W 303V Typ B */ ++static struct board_info __initdata board_spw303v = { ++ .name = "96358-502V", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* +@@ -1044,6 +1059,7 @@ static const struct board_info __initcon + &board_nb4_ser_r0, + &board_nb4_fxc_r1, + &board_HW553, ++ &board_spw303v, + #endif + }; + +@@ -1095,6 +1111,7 @@ static struct of_device_id const bcm963x + { .compatible = "pirelli,agpf-s0", .data = &board_AGPFS0, }, + { .compatible = "sfr,nb4-ser-r0", .data = &board_nb4_ser_r0, }, + { .compatible = "sfr,nb4-fxc-r1", .data = &board_nb4_fxc_r1, }, ++ { .compatible = "t-com,spw303v", .data = &board_spw303v, }, + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 diff --git a/target/linux/brcm63xx/patches-4.1/511-board_V2500V.patch b/target/linux/brcm63xx/patches-4.1/511-board_V2500V.patch new file mode 100644 index 0000000..82c9883 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/511-board_V2500V.patch @@ -0,0 +1,93 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -715,6 +715,27 @@ static struct board_info __initdata boar + .ext_irq = 2, + }, + }; ++ ++static struct board_info __initdata board_V2500V_BB = { ++ .name = "V2500V_BB", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6348 */ + + /* +@@ -1047,6 +1068,7 @@ static const struct board_info __initcon + &board_96348_D4PW, + &board_spw500v, + &board_96348sv, ++ &board_V2500V_BB, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1086,6 +1108,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, + { .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, }, + { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, ++ { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, }, + { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, +@@ -1145,6 +1168,22 @@ void __init board_bcm963xx_init(void) + val &= MPI_CSBASE_BASE_MASK; + } + boot_addr = (u8 *)KSEG1ADDR(val); ++ printk(KERN_INFO PFX "Boot address 0x%08x\n",(unsigned int)boot_addr); ++ ++ /* BT Voyager 2500V (RTA1046VW PCB) has 8 Meg flash used as two */ ++ /* banks of 4 Meg. The byte at 0xBF800000 identifies the back to use.*/ ++ /* Loading firmware from the CFE Prompt always loads to Bank 0 */ ++ /* Do an early check of CFE and then select bank 0 */ ++ ++ if (boot_addr == (u8 *)0xbf800000) { ++ u8 *tmp_boot_addr = (u8*)0xbfc00000; ++ ++ bcm63xx_nvram_init(tmp_boot_addr + BCM963XX_NVRAM_OFFSET); ++ if (!strcmp(bcm63xx_nvram_get_name(), "V2500V_BB")) { ++ printk(KERN_INFO PFX "V2500V: nvram bank 0\n"); ++ boot_addr = tmp_boot_addr; ++ } ++ } + + /* dump cfe version */ + cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; +--- a/arch/mips/bcm63xx/dev-flash.c ++++ b/arch/mips/bcm63xx/dev-flash.c +@@ -20,6 +20,7 @@ + #include + #include + ++#include + #include + #include + #include +@@ -234,6 +235,13 @@ int __init bcm63xx_flash_register(int nu + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + ++ /* BT Voyager 2500V has 8 Meg flash in two 4 Meg banks */ ++ /* Loading from CFE always uses Bank 0 */ ++ if (!strcmp(board_get_name(), "V2500V_BB")) { ++ pr_info("V2500V: Start in Bank 0\n"); ++ val = val + 0x400000; // Select Bank 0 start address ++ } ++ + mtd_resources[0].start = val; + mtd_resources[0].end = 0x1FFFFFFF; + } diff --git a/target/linux/brcm63xx/patches-4.1/512-board_BTV2110.patch b/target/linux/brcm63xx/patches-4.1/512-board_BTV2110.patch new file mode 100644 index 0000000..ba0a530 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/512-board_BTV2110.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -410,6 +410,25 @@ static struct board_info __initdata boar + }, + }; + ++ ++/* BT Voyager 2110 */ ++static struct board_info __initdata board_V2110 = { ++ .name = "V2110", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -1069,6 +1088,7 @@ static const struct board_info __initcon + &board_spw500v, + &board_96348sv, + &board_V2500V_BB, ++ &board_V2110, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1108,6 +1128,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, + { .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, }, + { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, ++ { .compatible = "bt,v2110", .data = &board_V2110, }, + { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, }, + { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, diff --git a/target/linux/brcm63xx/patches-4.1/513-MIPS-BCM63XX-add-inventel-Livebox-support.patch b/target/linux/brcm63xx/patches-4.1/513-MIPS-BCM63XX-add-inventel-Livebox-support.patch new file mode 100644 index 0000000..962f040 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/513-MIPS-BCM63XX-add-inventel-Livebox-support.patch @@ -0,0 +1,224 @@ +From e796582b499f0ba6acaa1ac3a10c09cceaab7702 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Mar 2014 04:55:52 +0100 +Subject: [PATCH] MIPS: BCM63XX: add inventel Livebox support + +--- + arch/mips/bcm63xx/boards/Kconfig | 6 + + arch/mips/bcm63xx/boards/Makefile | 1 + + arch/mips/bcm63xx/boards/board_common.c | 2 +- + arch/mips/bcm63xx/boards/board_common.h | 6 + + arch/mips/bcm63xx/boards/board_livebox.c | 215 ++++++++++++++++++++++++++++++ + 5 files changed, 229 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/bcm63xx/boards/board_livebox.c + +--- a/arch/mips/bcm63xx/boards/Kconfig ++++ b/arch/mips/bcm63xx/boards/Kconfig +@@ -12,4 +12,10 @@ config BOARD_BCM963XX + default y + help + ++config BOARD_LIVEBOX ++ bool "Inventel Livebox(es) boards" ++ select SSB ++ help ++ Inventel Livebox boards using the RedBoot bootloader. ++ + endmenu +--- a/arch/mips/bcm63xx/boards/Makefile ++++ b/arch/mips/bcm63xx/boards/Makefile +@@ -1,2 +1,3 @@ + obj-y += board_common.o + obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o ++obj-$(CONFIG_BOARD_LIVEBOX) += board_livebox.o +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -58,7 +58,7 @@ void __init board_prom_init(void) + if (fw_arg3 == CFE_EPTSEAL) + board_bcm963xx_init(); + else +- panic("unsupported bootloader detected"); ++ board_livebox_init(); + } + + static int (*board_get_mac_address)(u8 mac[ETH_ALEN]); +--- a/arch/mips/bcm63xx/boards/board_common.h ++++ b/arch/mips/bcm63xx/boards/board_common.h +@@ -24,4 +24,10 @@ static inline void board_of_device_prese + } + #endif + ++#if defined(CONFIG_BOARD_LIVEBOX) ++void board_livebox_init(void); ++#else ++static inline void board_livebox_init(void) { } ++#endif ++ + #endif /* __BOARD_COMMON_H */ +--- /dev/null ++++ b/arch/mips/bcm63xx/boards/board_livebox.c +@@ -0,0 +1,164 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Florian Fainelli ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "board_common.h" ++ ++#define PFX "board_livebox: " ++ ++static unsigned int mac_addr_used = 0; ++ ++/* ++ * known 6348 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6348 ++static struct board_info __initdata board_livebox_blue5g = { ++ .name = "Livebox-blue-5g", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 31, ++ }, ++ ++ .ephy_reset_gpio = 6, ++ .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ ++ .has_dsp = 0, /*TODO some Liveboxes have dsp*/ ++ .dsp = { ++ .gpio_rst = 6, ++ .gpio_int = 35, ++ .cs = 2, ++ .ext_irq = 2, ++ }, ++}; ++#endif ++ ++/* ++ * all boards ++ */ ++static const struct board_info __initdata *bcm963xx_boards[] = { ++#ifdef CONFIG_BCM63XX_CPU_6348 ++ &board_livebox_blue5g ++#endif ++}; ++ ++static struct of_device_id const livebox_boards_dt[] = { ++ { .compatible = "inventel,livebox-blue-5g", .data = &board_livebox_blue5g, }, ++ { } ++}; ++ ++/* ++ * register & return a new board mac address ++ */ ++static int livebox_get_mac_address(u8 *mac) ++{ ++ u8 *p; ++ int count; ++ ++ memcpy(mac, (u8 *)0xBEBFF377, ETH_ALEN); ++ ++ p = mac + ETH_ALEN - 1; ++ count = mac_addr_used; ++ ++ while (count--) { ++ do { ++ (*p)++; ++ if (*p != 0) ++ break; ++ p--; ++ } while (p != mac); ++ } ++ ++ if (p == mac) { ++ printk(KERN_ERR PFX "unable to fetch mac address\n"); ++ return -ENODEV; ++ } ++ mac_addr_used++; ++ ++ return 0; ++} ++ ++/* ++ * early init callback ++ */ ++#define LIVEBOX_GPIO_DETECT_MASK 0x000000ff ++#define LIVEBOX_BOOT_ADDR 0x1e400000 ++ ++#define LIVEBOX_HW_BLUE5G_9 0x90 ++ ++void __init board_livebox_init(void) ++{ ++ u32 val; ++ u8 hw_version; ++ const struct board_info *board; ++ const struct of_device_id *board_match; ++ ++ /* find board by compat */ ++ board_match = bcm63xx_match_board(livebox_boards_dt); ++ if (board_match) { ++ board = board_match->data; ++ } else { ++ /* Get hardware version */ ++ val = bcm_gpio_readl(GPIO_CTL_LO_REG); ++ val &= ~LIVEBOX_GPIO_DETECT_MASK; ++ bcm_gpio_writel(val, GPIO_CTL_LO_REG); ++ ++ hw_version = bcm_gpio_readl(GPIO_DATA_LO_REG); ++ hw_version &= LIVEBOX_GPIO_DETECT_MASK; ++ ++ switch (hw_version) { ++ case LIVEBOX_HW_BLUE5G_9: ++ printk(KERN_INFO PFX "Livebox BLUE5G.9\n"); ++ board = bcm963xx_boards[0]; ++ break; ++ default: ++ printk(KERN_INFO PFX "Unknown livebox version: %02x\n", ++ hw_version); ++ /* use default livebox configuration */ ++ board = bcm963xx_boards[0]; ++ break; ++ } ++ } ++ ++ /* use default livebox configuration */ ++ board_early_setup(board, livebox_get_mac_address); ++ ++ /* read base address of boot chip select (0) */ ++ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); ++ val &= MPI_CSBASE_BASE_MASK; ++ if (val != LIVEBOX_BOOT_ADDR) { ++ printk(KERN_NOTICE PFX "flash address is: 0x%08x, forcing to: 0x%08x\n", ++ val, LIVEBOX_BOOT_ADDR); ++ bcm63xx_flash_force_phys_base_address(LIVEBOX_BOOT_ADDR, 0x1ebfffff); ++ } ++} diff --git a/target/linux/brcm63xx/patches-4.1/514-board_ct536_ct5621.patch b/target/linux/brcm63xx/patches-4.1/514-board_ct536_ct5621.patch new file mode 100644 index 0000000..cf3701f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/514-board_ct536_ct5621.patch @@ -0,0 +1,54 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -429,6 +429,34 @@ static struct board_info __initdata boar + }; + + ++static struct board_info __initdata board_ct536_ct5621 = { ++ .name = "CT536_CT5621", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 0, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -1089,6 +1117,7 @@ static const struct board_info __initcon + &board_96348sv, + &board_V2500V_BB, + &board_V2110, ++ &board_ct536_ct5621, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1130,6 +1159,8 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, }, + { .compatible = "bt,v2110", .data = &board_V2110, }, + { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, }, ++ { .compatible = "comtrend,ct-536+", .data = &board_ct536_ct5621, }, ++ { .compatible = "comtrend,ct-5621", .data = &board_ct536_ct5621, }, + { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, diff --git a/target/linux/brcm63xx/patches-4.1/515-board_DWV-S0_fixes.patch b/target/linux/brcm63xx/patches-4.1/515-board_DWV-S0_fixes.patch new file mode 100644 index 0000000..03a124c --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/515-board_DWV-S0_fixes.patch @@ -0,0 +1,19 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -945,6 +945,8 @@ static struct board_info __initdata boar + .name = "DWV-S0", + .expected_cpu_id = 0x6358, + ++ .has_uart0 = 1, ++ + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, +@@ -963,6 +965,7 @@ static struct board_info __initdata boar + }, + + .has_ohci0 = 1, ++ .has_ehci0 = 1, + }; + + /* D-Link DSL-274xB revison C2/C3 */ diff --git a/target/linux/brcm63xx/patches-4.1/516-board_96348A-122.patch b/target/linux/brcm63xx/patches-4.1/516-board_96348A-122.patch new file mode 100644 index 0000000..a192986 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/516-board_96348A-122.patch @@ -0,0 +1,50 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -457,6 +457,31 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_96348A_122 = { ++ .name = "96348A-122", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, +@@ -1121,6 +1146,7 @@ static const struct board_info __initcon + &board_V2500V_BB, + &board_V2110, + &board_ct536_ct5621, ++ &board_96348A_122, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1163,6 +1189,7 @@ static struct of_device_id const bcm963x + { .compatible = "bt,v2110", .data = &board_V2110, }, + { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, }, + { .compatible = "comtrend,ct-536+", .data = &board_ct536_ct5621, }, ++ { .compatible = "comtrend,ct-5365", .data = &board_96348A_122, }, + { .compatible = "comtrend,ct-5621", .data = &board_ct536_ct5621, }, + { .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, }, + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, diff --git a/target/linux/brcm63xx/patches-4.1/517-RTA1205W_16_uart_fixes.patch b/target/linux/brcm63xx/patches-4.1/517-RTA1205W_16_uart_fixes.patch new file mode 100644 index 0000000..ba5a7f9 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/517-RTA1205W_16_uart_fixes.patch @@ -0,0 +1,10 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -634,6 +634,7 @@ static struct board_info __initdata boar + .name = "RTA1025W_16", + .expected_cpu_id = 0x6348, + ++ .has_uart0 = 1, + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, diff --git a/target/linux/brcm63xx/patches-4.1/519_board_CPVA502plus.patch b/target/linux/brcm63xx/patches-4.1/519_board_CPVA502plus.patch new file mode 100644 index 0000000..c1757dc --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/519_board_CPVA502plus.patch @@ -0,0 +1,46 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -428,6 +428,27 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_CPVA502plus = { ++ .name = "CPVA502+", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ }, ++ ++ .ephy_reset_gpio = 4, ++ .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, ++}; + + static struct board_info __initdata board_ct536_ct5621 = { + .name = "CT536_CT5621", +@@ -1148,6 +1169,7 @@ static const struct board_info __initcon + &board_V2110, + &board_ct536_ct5621, + &board_96348A_122, ++ &board_CPVA502plus, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1200,6 +1222,7 @@ static struct of_device_id const bcm963x + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tecom,gw6000", .data = &board_gw6000, }, + { .compatible = "tecom,gw6200", .data = &board_gw6200, }, ++ { .compatible = "telsey,cpva502+", .data = &board_CPVA502plus, }, + { .compatible = "telsey,magic", .data = &board_96348sv, }, + { .compatible = "tp-link,td-w8900gb", .data = &board_96348gw_11, }, + { .compatible = "usr,9108", .data = &board_96348gw_a, }, diff --git a/target/linux/brcm63xx/patches-4.1/520-bcm63xx-add-support-for-96368MVWG-board.patch b/target/linux/brcm63xx/patches-4.1/520-bcm63xx-add-support-for-96368MVWG-board.patch new file mode 100644 index 0000000..11b60ff --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/520-bcm63xx-add-support-for-96368MVWG-board.patch @@ -0,0 +1,119 @@ +From eeacc2529942051504bc957726aa178671344421 Mon Sep 17 00:00:00 2001 +From: Maxime Bizon +Date: Wed, 20 Jan 2010 16:21:30 +0100 +Subject: [PATCH 32/63] bcm63xx: add support for 96368MVWG board. + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 95 ++++++++++++++++++++ + .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 2 + + 2 files changed, 97 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1133,6 +1133,59 @@ static struct board_info __initdata boar + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* ++ * known 6368 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6368 ++static struct board_info __initdata board_96368mvwg = { ++ .name = "96368MVWG", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port1", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port2", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 0x12, ++ .name = "port0", ++ }, ++ ++ [5] = { ++ .used = 1, ++ .phy_id = 0x11, ++ .name = "port3", ++ }, ++ }, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++}; ++#endif /* CONFIG_BCM63XX_CPU_6368 */ ++ ++/* + * all boards + */ + static const struct board_info __initconst *bcm963xx_boards[] = { +@@ -1184,6 +1237,10 @@ static const struct board_info __initcon + &board_HW553, + &board_spw303v, + #endif ++ ++#ifdef CONFIG_BCM63XX_CPU_6368 ++ &board_96368mvwg, ++#endif + }; + + static struct of_device_id const bcm963xx_boards_dt[] = { +@@ -1244,6 +1301,7 @@ static struct of_device_id const bcm963x + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 ++ { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + #endif +--- a/arch/mips/bcm63xx/boards/board_common.c ++++ b/arch/mips/bcm63xx/boards/board_common.c +@@ -85,12 +85,25 @@ void __init board_early_setup(const stru + bcm63xx_pci_enabled = 1; + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G2_PCI; ++ ++ if (BCMCPU_IS_6368()) ++ val |= GPIO_MODE_6368_PCI_REQ1 | ++ GPIO_MODE_6368_PCI_GNT1 | ++ GPIO_MODE_6368_PCI_INTB | ++ GPIO_MODE_6368_PCI_REQ0 | ++ GPIO_MODE_6368_PCI_GNT0; + } + #endif + + if (board.has_pccard) { + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G1_MII_PCCARD; ++ ++ if (BCMCPU_IS_6368()) ++ val |= GPIO_MODE_6368_PCMCIA_CD1 | ++ GPIO_MODE_6368_PCMCIA_CD2 | ++ GPIO_MODE_6368_PCMCIA_VS1 | ++ GPIO_MODE_6368_PCMCIA_VS2; + } + + if (board.has_enet0 && !board.enet0.use_internal_phy) { diff --git a/target/linux/brcm63xx/patches-4.1/521-bcm63xx-add-support-for-96368MVNgr-board.patch b/target/linux/brcm63xx/patches-4.1/521-bcm63xx-add-support-for-96368MVNgr-board.patch new file mode 100644 index 0000000..1464cdc --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/521-bcm63xx-add-support-for-96368MVNgr-board.patch @@ -0,0 +1,74 @@ +From f457fc2eb9bb915b5a4d251c7c68d4694cf07b01 Mon Sep 17 00:00:00 2001 +From: Maxime Bizon +Date: Fri, 4 Nov 2011 12:33:48 +0100 +Subject: [PATCH 33/63] bcm63xx: add support for 96368MVNgr board. + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 67 +++++++++++++++++++++++++++++ + 1 files changed, 67 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1183,6 +1183,46 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_ehci0 = 1, + }; ++ ++static struct board_info __initdata board_96368mvngr = { ++ .name = "96368MVNgr", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++}; + #endif /* CONFIG_BCM63XX_CPU_6368 */ + + /* +@@ -1240,6 +1280,7 @@ static const struct board_info __initcon + + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, ++ &board_96368mvngr, + #endif + }; + +@@ -1301,6 +1342,7 @@ static struct of_device_id const bcm963x + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 ++ { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 diff --git a/target/linux/brcm63xx/patches-4.1/522-MIPS-BCM63XX-add-96328avng-reference-board.patch b/target/linux/brcm63xx/patches-4.1/522-MIPS-BCM63XX-add-96328avng-reference-board.patch new file mode 100644 index 0000000..1b54fa9 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/522-MIPS-BCM63XX-add-96328avng-reference-board.patch @@ -0,0 +1,45 @@ +From c93c2bbf0cc96da5a47d77f01daf6c983cfe4216 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 May 2012 10:52:25 +0200 +Subject: [PATCH] MIPS: BCM63XX: add 96328avng reference board + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 77 +++++++++++++++++++++++++++++ + 1 files changed, 77 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -104,6 +104,33 @@ static struct board_info __initdata boar + .active_low = 1, + }, + }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, + }; + #endif /* CONFIG_BCM63XX_CPU_6328 */ + diff --git a/target/linux/brcm63xx/patches-4.1/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch b/target/linux/brcm63xx/patches-4.1/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch new file mode 100644 index 0000000..e778676 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch @@ -0,0 +1,69 @@ +From f0649f7b7c672cf452a1796a1422bf615e1973f8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 29 May 2012 11:01:12 +0200 +Subject: [PATCH] MIPS: BCM63XX: add 963281TAN reference board + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 71 +++++++++++++++++++++++++++++ + 1 files changed, 71 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -132,6 +132,41 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_963281TAN = { ++ .name = "963281TAN", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6328 */ + + /* +@@ -1261,6 +1296,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_963281TAN, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, +@@ -1317,6 +1353,7 @@ static struct of_device_id const bcm963x + { .compatible = "netgear,cvg834g", .data = &board_cvg834g, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 ++ { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 diff --git a/target/linux/brcm63xx/patches-4.1/524-board_dsl_274xb_rev_f.patch b/target/linux/brcm63xx/patches-4.1/524-board_dsl_274xb_rev_f.patch new file mode 100644 index 0000000..2b32cd0 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/524-board_dsl_274xb_rev_f.patch @@ -0,0 +1,80 @@ +From 66808f706b3dcd83a9f5157997ff478a880a2906 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 30 Apr 2012 09:10:51 +0200 +Subject: [PATCH 70/79] MIPS: BCM63XX: Add board definition for D-Link + DSL-274xB rev F1 + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 104 +++++++++++++++++++++++++++++ + 1 files changed, 104 insertions(+), 0 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -167,6 +167,51 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_dsl_274xb_f1 = { ++ .name = "AW4339U", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0x7d1000, ++ .slot = 0, ++ .led_pin = -1, ++ }, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 4", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 3", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 2", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 1", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6328 */ + + /* +@@ -1297,6 +1342,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_963281TAN, ++ &board_dsl_274xb_f1, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, +@@ -1355,6 +1401,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, ++ { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, diff --git a/target/linux/brcm63xx/patches-4.1/525-board_96348w3.patch b/target/linux/brcm63xx/patches-4.1/525-board_96348w3.patch new file mode 100644 index 0000000..daac5b5 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/525-board_96348w3.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -828,6 +828,25 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + }; + ++/* NetGear DG834G v4 */ ++static struct board_info __initdata board_96348W3 = { ++ .name = "96348W3", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++}; ++ + static struct board_info __initdata board_96348_D4PW = { + .name = "D-4P-W", + .expected_cpu_id = 0x6348, +@@ -1372,6 +1391,7 @@ static const struct board_info __initcon + &board_ct536_ct5621, + &board_96348A_122, + &board_CPVA502plus, ++ &board_96348W3, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1427,6 +1447,7 @@ static struct of_device_id const bcm963x + { .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, }, + { .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, }, + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, ++ { .compatible = "netgear,dg834g-v4", .data = &board_96348W3, }, + { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tecom,gw6000", .data = &board_gw6000, }, diff --git a/target/linux/brcm63xx/patches-4.1/526-board_CT6373-1.patch b/target/linux/brcm63xx/patches-4.1/526-board_CT6373-1.patch new file mode 100644 index 0000000..4422348 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/526-board_CT6373-1.patch @@ -0,0 +1,50 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1214,6 +1214,31 @@ static struct board_info __initdata boar + .num_usbh_ports = 2, + }; + ++static struct board_info __initdata board_ct6373_1 = { ++ .name = "CT6373-1", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_HW553 = { + .name = "HW553", + .expected_cpu_id = 0x6358, +@@ -1403,6 +1428,7 @@ static const struct board_info __initcon + &board_dsl_274xb_rev_c, + &board_nb4_ser_r0, + &board_nb4_fxc_r1, ++ &board_ct6373_1, + &board_HW553, + &board_spw303v, + #endif +@@ -1461,6 +1487,7 @@ static struct of_device_id const bcm963x + { .compatible = "alcatel,rg100a", .data = &board_96358vw2, }, + { .compatible = "brcm,bcm96358vw", .data = &board_96358vw, }, + { .compatible = "brcm,bcm96358vw2", .data = &board_96358vw2, }, ++ { .compatible = "comtrend,ct-6373", .data = &board_ct6373_1, }, + { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, + { .compatible = "huawei,hg553", .data = &board_HW553, }, diff --git a/target/linux/brcm63xx/patches-4.1/527-board_dva-g3810bn-tl-1.patch b/target/linux/brcm63xx/patches-4.1/527-board_dva-g3810bn-tl-1.patch new file mode 100644 index 0000000..a093ba1 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/527-board_dva-g3810bn-tl-1.patch @@ -0,0 +1,55 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1281,6 +1281,36 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + }; ++ ++/* D-Link DVA-G3810BN/TL */ ++static struct board_info __initdata board_DVAG3810BN = { ++ .name = "DVAG3810BN", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet0 = { ++ .has_phy = 0, ++ .use_internal_phy = 1, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ ++ .has_ohci0 = 1, ++ .has_pccard = 1, ++ .has_ehci0 = 1, ++}; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + + /* +@@ -1431,6 +1461,7 @@ static const struct board_info __initcon + &board_ct6373_1, + &board_HW553, + &board_spw303v, ++ &board_DVAG3810BN, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6368 +@@ -1490,6 +1521,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,ct-6373", .data = &board_ct6373_1, }, + { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, ++ { .compatible = "d-link,dva-g3810bn/tl", .data = &board_DVAG3810BN, }, + { .compatible = "huawei,hg553", .data = &board_HW553, }, + { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, diff --git a/target/linux/brcm63xx/patches-4.1/528-board_nb6.patch b/target/linux/brcm63xx/patches-4.1/528-board_nb6.patch new file mode 100644 index 0000000..8b49108 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/528-board_nb6.patch @@ -0,0 +1,112 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -10,6 +10,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -26,6 +28,9 @@ + + #define HCS_OFFSET_128K 0x20000 + ++#define NB6_GPIO_RTL8367_SDA 18 ++#define NB6_GPIO_RTL8367_SCK 20 ++ + /* + * known 3368 boards + */ +@@ -1313,6 +1318,69 @@ static struct board_info __initdata boar + }; + #endif /* CONFIG_BCM63XX_CPU_6358 */ + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++static struct rtl8367_extif_config nb6_rtl8367_extif0_cfg = { ++ .mode = RTL8367_EXTIF_MODE_RGMII, ++ .txdelay = 1, ++ .rxdelay = 5, ++ .ability = { ++ .force_mode = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ .link = 1, ++ .duplex = 1, ++ .speed = RTL8367_PORT_SPEED_1000, ++ }, ++}; ++ ++static struct rtl8367_platform_data nb6_rtl8367_data = { ++ .gpio_sda = NB6_GPIO_RTL8367_SDA, ++ .gpio_sck = NB6_GPIO_RTL8367_SCK, ++ .extif0_cfg = &nb6_rtl8367_extif0_cfg, ++}; ++ ++static struct platform_device nb6_rtl8367_device = { ++ .name = RTL8367_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &nb6_rtl8367_data, ++ } ++}; ++ ++static struct platform_device * __initdata nb6_devices[] = { ++ &nb6_rtl8367_device, ++}; ++ ++static struct board_info __initdata board_nb6 = { ++ .name = "NB6", ++ .expected_cpu_id = 0x6362, ++ ++ .has_uart0 = 1, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [4] = { ++ .used = 1, ++ .phy_id = 0xff, ++ .bypass_link = 1, ++ .force_speed = 1000, ++ .force_duplex_full = 1, ++ .name = "RGMII", ++ }, ++ }, ++ }, ++ ++ .devs = nb6_devices, ++ .num_devs = ARRAY_SIZE(nb6_devices), ++}; ++#endif /* CONFIG_BCM63XX_CPU_6362 */ ++ + /* + * known 6368 boards + */ +@@ -1464,6 +1532,10 @@ static const struct board_info __initcon + &board_DVAG3810BN, + #endif + ++#ifdef CONFIG_BCM63XX_CPU_6362 ++ &board_nb6, ++#endif ++ + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, +@@ -1532,6 +1604,9 @@ static struct of_device_id const bcm963x + { .compatible = "t-com,spw303v", .data = &board_spw303v, }, + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif ++#ifdef CONFIG_BCM63XX_CPU_6362 ++ { .compatible = "sfr,nb6-ser-r0", .data = &board_nb6, }, ++#endif + #ifdef CONFIG_BCM63XX_CPU_6368 + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, diff --git a/target/linux/brcm63xx/patches-4.1/529-board_fast2604.patch b/target/linux/brcm63xx/patches-4.1/529-board_fast2604.patch new file mode 100644 index 0000000..f82cfb7 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/529-board_fast2604.patch @@ -0,0 +1,42 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -763,6 +763,23 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct board_info __initdata board_FAST2604 = { ++ .name = "F@ST2604", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ + static struct board_info __initdata board_rta1025w_16 = { + .name = "RTA1025W_16", + .expected_cpu_id = 0x6348, +@@ -1503,6 +1520,7 @@ static const struct board_info __initcon + &board_96348gw_10, + &board_96348gw_11, + &board_FAST2404, ++ &board_FAST2604, + &board_DV201AMR, + &board_96348gw_a, + &board_rta1025w_16, +@@ -1578,6 +1596,7 @@ static struct of_device_id const bcm963x + { .compatible = "netgear,dg834gtpn", .data = &board_96348gw_10, }, + { .compatible = "netgear,dg834g-v4", .data = &board_96348W3, }, + { .compatible = "sagem,f@st2404", .data = &board_FAST2404, }, ++ { .compatible = "sagem,f@st2604", .data = &board_FAST2604, }, + { .compatible = "t-com,spw500v", .data = &board_spw500v, }, + { .compatible = "tecom,gw6000", .data = &board_gw6000, }, + { .compatible = "tecom,gw6200", .data = &board_gw6200, }, diff --git a/target/linux/brcm63xx/patches-4.1/530-board_A4001N1.patch b/target/linux/brcm63xx/patches-4.1/530-board_A4001N1.patch new file mode 100644 index 0000000..fa164ee --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/530-board_A4001N1.patch @@ -0,0 +1,69 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -173,6 +173,50 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_A4001N1 = { ++ .name = "963281T_TEF", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43225, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ }, ++}; ++ + static struct board_info __initdata board_dsl_274xb_f1 = { + .name = "AW4339U", + .expected_cpu_id = 0x6328, +@@ -1501,6 +1545,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_963281TAN, ++ &board_A4001N1, + &board_dsl_274xb_f1, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 +@@ -1566,6 +1611,7 @@ static struct of_device_id const bcm963x + { .compatible = "netgear,cvg834g", .data = &board_cvg834g, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 ++ { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, + { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, diff --git a/target/linux/brcm63xx/patches-4.1/531-board_AR-5387un.patch b/target/linux/brcm63xx/patches-4.1/531-board_AR-5387un.patch new file mode 100644 index 0000000..32808ed --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/531-board_AR-5387un.patch @@ -0,0 +1,98 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -138,6 +138,79 @@ static struct board_info __initdata boar + }, + }; + ++static struct sprom_fixup __initdata ar5387un_fixups[] = { ++ { .offset = 2, .value = 0x05bb }, ++ { .offset = 65, .value = 0x1204 }, ++ { .offset = 78, .value = 0x0303 }, ++ { .offset = 79, .value = 0x0202 }, ++ { .offset = 80, .value = 0xff02 }, ++ { .offset = 87, .value = 0x0315 }, ++ { .offset = 88, .value = 0x0315 }, ++ { .offset = 96, .value = 0x2048 }, ++ { .offset = 97, .value = 0xff11 }, ++ { .offset = 98, .value = 0x1567 }, ++ { .offset = 99, .value = 0xfb24 }, ++ { .offset = 100, .value = 0x3e3c }, ++ { .offset = 101, .value = 0x4038 }, ++ { .offset = 102, .value = 0xfe7f }, ++ { .offset = 103, .value = 0x1279 }, ++ { .offset = 112, .value = 0x2048 }, ++ { .offset = 113, .value = 0xff03 }, ++ { .offset = 114, .value = 0x154c }, ++ { .offset = 115, .value = 0xfb27 }, ++ { .offset = 116, .value = 0x3e3c }, ++ { .offset = 117, .value = 0x4038 }, ++ { .offset = 118, .value = 0xfe87 }, ++ { .offset = 119, .value = 0x1233 }, ++ { .offset = 203, .value = 0x2226 }, ++}; ++ ++static struct board_info __initdata board_AR5387un = { ++ .name = "96328A-1441N1", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43225, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ .board_fixups = ar5387un_fixups, ++ .num_board_fixups = ARRAY_SIZE(ar5387un_fixups), ++ }, ++}; ++ + static struct board_info __initdata board_963281TAN = { + .name = "963281TAN", + .expected_cpu_id = 0x6328, +@@ -1544,6 +1617,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_AR5387un, + &board_963281TAN, + &board_A4001N1, + &board_dsl_274xb_f1, +@@ -1614,6 +1688,7 @@ static struct of_device_id const bcm963x + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, ++ { .compatible = "comtrend,ar-5387un", .data = &board_AR5387un, }, + { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 diff --git a/target/linux/brcm63xx/patches-4.1/532-board_AR-5381u.patch b/target/linux/brcm63xx/patches-4.1/532-board_AR-5381u.patch new file mode 100644 index 0000000..a071558 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/532-board_AR-5381u.patch @@ -0,0 +1,80 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -138,6 +138,61 @@ static struct board_info __initdata boar + }, + }; + ++static struct sprom_fixup __initdata ar5381u_fixups[] = { ++ { .offset = 97, .value = 0xfee5 }, ++ { .offset = 98, .value = 0x157c }, ++ { .offset = 99, .value = 0xfae7 }, ++ { .offset = 113, .value = 0xfefa }, ++ { .offset = 114, .value = 0x15d6 }, ++ { .offset = 115, .value = 0xfaf8 }, ++}; ++ ++static struct board_info __initdata board_AR5381u = { ++ .name = "96328A-1241N", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43225, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ .board_fixups = ar5381u_fixups, ++ .num_board_fixups = ARRAY_SIZE(ar5381u_fixups), ++ }, ++}; ++ + static struct sprom_fixup __initdata ar5387un_fixups[] = { + { .offset = 2, .value = 0x05bb }, + { .offset = 65, .value = 0x1204 }, +@@ -1617,6 +1672,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, ++ &board_AR5381u, + &board_AR5387un, + &board_963281TAN, + &board_A4001N1, +@@ -1688,6 +1744,7 @@ static struct of_device_id const bcm963x + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, ++ { .compatible = "comtrend,ar-5381u", .data = &board_AR5381u, }, + { .compatible = "comtrend,ar-5387un", .data = &board_AR5387un, }, + { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, + #endif diff --git a/target/linux/brcm63xx/patches-4.1/533-board_rta770bw.patch b/target/linux/brcm63xx/patches-4.1/533-board_rta770bw.patch new file mode 100644 index 0000000..277f7af --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/533-board_rta770bw.patch @@ -0,0 +1,41 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -523,6 +523,22 @@ static struct board_info __initdata boar + + .has_uart0 = 1, + }; ++ ++static struct board_info __initdata board_rta770bw = { ++ .name = "RTA770BW", ++ .expected_cpu_id = 0x6345, ++ ++ .has_uart0 = 1, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6345 */ + + /* +@@ -1686,6 +1702,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, ++ &board_rta770bw, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, +@@ -1756,6 +1773,7 @@ static struct of_device_id const bcm963x + #endif + #ifdef CONFIG_BCM63XX_CPU_6345 + { .compatible = "brcm,bcm96345gw2", .data = &board_96345gw2, }, ++ { .compatible = "dynalink,rta770bw", .data = &board_rta770bw, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + { .compatible = "belkin,f5d7633", .data = &board_96348gw_10, }, diff --git a/target/linux/brcm63xx/patches-4.1/534-board_hw556.patch b/target/linux/brcm63xx/patches-4.1/534-board_hw556.patch new file mode 100644 index 0000000..4a01493 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/534-board_hw556.patch @@ -0,0 +1,124 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1477,6 +1478,93 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_HW556_C = { ++ .name = "HW556_C", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_RALINK, ++ .caldata_offset = 0xeffe00, ++ .slot = 1, ++ .eeprom = "rt2x00.eeprom", ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++static struct board_info __initdata board_HW556_A = { ++ .name = "HW556_A", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0xf7e000, ++ .slot = 1, ++ .endian_check = 1, ++ .led_pin = 2, ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++static struct board_info __initdata board_HW556_B = { ++ .name = "HW556_B", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_ATHEROS, ++ .caldata_offset = 0xefe000, ++ .slot = 1, ++ .endian_check = 1, ++ .led_pin = 2, ++ }, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ + /* T-Home Speedport W 303V Typ B */ + static struct board_info __initdata board_spw303v = { + .name = "96358-502V", +@@ -1738,6 +1826,9 @@ static const struct board_info __initcon + &board_nb4_fxc_r1, + &board_ct6373_1, + &board_HW553, ++ &board_HW556_A, ++ &board_HW556_B, ++ &board_HW556_C, + &board_spw303v, + &board_DVAG3810BN, + #endif +@@ -1810,6 +1901,9 @@ static struct of_device_id const bcm963x + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, + { .compatible = "d-link,dva-g3810bn/tl", .data = &board_DVAG3810BN, }, + { .compatible = "huawei,hg553", .data = &board_HW553, }, ++ { .compatible = "huawei,hg556a-a", .data = &board_HW556_A, }, ++ { .compatible = "huawei,hg556a-b", .data = &board_HW556_B, }, ++ { .compatible = "huawei,hg556a-c", .data = &board_HW556_C, }, + { .compatible = "pirelli,a226g", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m", .data = &board_DWVS0, }, + { .compatible = "pirelli,a226m-fwb", .data = &board_DWVS0, }, diff --git a/target/linux/brcm63xx/patches-4.1/535-board_rta770w.patch b/target/linux/brcm63xx/patches-4.1/535-board_rta770w.patch new file mode 100644 index 0000000..99623e7 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/535-board_rta770w.patch @@ -0,0 +1,46 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -540,6 +540,27 @@ static struct board_info __initdata boar + .force_duplex_full = 1, + }, + }; ++ ++// Actually this board is the very same as the rta770bw, ++// where the additional 'b' within the name just ++// just indicates 'Annex B'. The ADSL Modem itself is able ++// to handle both Annex A as well as Annex B - ++// the loaded firmware makes the only difference ++static struct board_info __initdata board_rta770w = { ++ .name = "RTA770W", ++ .expected_cpu_id = 0x6345, ++ ++ .has_uart0 = 1, ++ ++ .has_enet0 = 1, ++ ++ .enet0 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6345 */ + + /* +@@ -1791,6 +1812,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, + &board_rta770bw, ++ &board_rta770w, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, +@@ -1865,6 +1887,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6345 + { .compatible = "brcm,bcm96345gw2", .data = &board_96345gw2, }, + { .compatible = "dynalink,rta770bw", .data = &board_rta770bw, }, ++ { .compatible = "dynalink,rta770w", .data = &board_rta770w, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 + { .compatible = "belkin,f5d7633", .data = &board_96348gw_10, }, diff --git a/target/linux/brcm63xx/patches-4.1/536-board_fast2704.patch b/target/linux/brcm63xx/patches-4.1/536-board_fast2704.patch new file mode 100644 index 0000000..e1a128c --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/536-board_fast2704.patch @@ -0,0 +1,75 @@ +From: Marcin Jurkowski +Date: Thu, 31 Oct 2013 22:33:10 +0000 +Subject: [PATCH] bcm63xx: Add kernel support for Sagemcom F@ST2704V2 ADSL + router + +This adds kernel support support for Sagemcom F@st 2704 wireless ADSL +router. +It's a BCM6328-based 802.11n wireless router with USB port and ADSL2+ +modem equipped with 64 MiB RAM and 8 MiB flash. + +Signed-off-by: Marcin Jurkowski +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -390,6 +390,44 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_FAST2704V2 = { ++ .name = "F@ST2704V2", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .has_usbd = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6328 */ + + /* +@@ -1802,6 +1840,7 @@ static const struct board_info __initcon + &board_963281TAN, + &board_A4001N1, + &board_dsl_274xb_f1, ++ &board_FAST2704V2, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, +@@ -1877,6 +1916,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,ar-5381u", .data = &board_AR5381u, }, + { .compatible = "comtrend,ar-5387un", .data = &board_AR5387un, }, + { .compatible = "d-link,dsl-274xb-f", .data = &board_dsl_274xb_f1, }, ++ { .compatible = "sagem,f@st2704v2", .data = &board_FAST2704V2, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6338 + { .compatible = "brcm,bcm96338gw", .data = &board_96338gw, }, diff --git a/target/linux/brcm63xx/patches-4.1/537-board_fast2504n.patch b/target/linux/brcm63xx/patches-4.1/537-board_fast2504n.patch new file mode 100644 index 0000000..bfc68df --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/537-board_fast2504n.patch @@ -0,0 +1,68 @@ +From: Max Staudt +Date: Wed, 15 Jan 2014 18:51:13 +0000 +Subject: [PATCH] brcm63xx: F@ST2504n board support (Linux-3.10.26) + +Signed-off-by: Max Staudt +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1731,6 +1731,43 @@ static struct board_info __initdata boar + .devs = nb6_devices, + .num_devs = ARRAY_SIZE(nb6_devices), + }; ++ ++static struct board_info __initdata board_fast2504n = { ++ .name = "F@ST2504n", ++ .expected_cpu_id = 0x6362, ++ ++ .has_uart0 = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6362 */ + + /* +@@ -1896,6 +1933,7 @@ static const struct board_info __initcon + + #ifdef CONFIG_BCM63XX_CPU_6362 + &board_nb6, ++ &board_fast2504n, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6368 +@@ -1977,6 +2015,7 @@ static struct of_device_id const bcm963x + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6362 ++ { .compatible = "sagem,f@st2504n", .data = &board_fast2504n, }, + { .compatible = "sfr,nb6-ser-r0", .data = &board_nb6, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6368 diff --git a/target/linux/brcm63xx/patches-4.1/550-MIPS-BCM63XX-remove-leds-and-buttons.patch b/target/linux/brcm63xx/patches-4.1/550-MIPS-BCM63XX-remove-leds-and-buttons.patch new file mode 100644 index 0000000..fe55401 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/550-MIPS-BCM63XX-remove-leds-and-buttons.patch @@ -0,0 +1,343 @@ +From 997f53b174c63153335508c22dc4493e8e5808d6 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 22 Feb 2015 17:52:32 +0100 +Subject: [PATCH] MIPS: BCM63XX: remove leds and buttons + +--- + arch/mips/bcm63xx/boards/board_bcm963xx.c | 262 ----------------------------- + 1 file changed, 262 deletions(-) + +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -51,14 +51,6 @@ static struct board_info __initdata boar + .use_internal_phy = 1, + }, + +- .leds = { +- { +- .name = "CVG834G:green:power", +- .gpio = 37, +- .default_trigger= "default-on", +- }, +- }, +- + .ephy_reset_gpio = 36, + .ephy_reset_gpio_flags = GPIO_ACTIVE_LOW, + }; +@@ -82,35 +74,6 @@ static struct board_info __initdata boar + .port_no = 0, + }, + +- .leds = { +- { +- .name = "96328avng::ppp-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "96328avng::power", +- .gpio = 4, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "96328avng::power-fail", +- .gpio = 8, +- .active_low = 1, +- }, +- { +- .name = "96328avng::wps", +- .gpio = 9, +- .active_low = 1, +- }, +- { +- .name = "96328avng::ppp", +- .gpio = 11, +- .active_low = 1, +- }, +- }, +- + .has_enetsw = 1, + + .enetsw = { +@@ -448,35 +411,6 @@ static struct board_info __initdata boar + }, + + .has_ohci0 = 1, +- +- .leds = { +- { +- .name = "adsl", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ses", +- .gpio = 5, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- } +- }, + }; + + static struct board_info __initdata board_96338w = { +@@ -491,35 +425,6 @@ static struct board_info __initdata boar + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +- +- .leds = { +- { +- .name = "adsl", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ses", +- .gpio = 5, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_96338w2_e7t = { +@@ -618,36 +523,6 @@ static struct board_info __initdata boar + .has_phy = 1, + .use_internal_phy = 1, + }, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_96348gw_10 = { +@@ -682,35 +557,6 @@ static struct board_info __initdata boar + .cs = 2, + .ext_irq = 2, + }, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_96348gw_11 = { +@@ -739,35 +585,6 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + +@@ -893,35 +710,6 @@ static struct board_info __initdata boar + .ext_irq = 2, + .cs = 2, + }, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 2, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 3, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 4, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 0, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 1, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_gw6200 = { +@@ -1258,33 +1046,6 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +- +- .leds = { +- { +- .name = "adsl-fail", +- .gpio = 15, +- .active_low = 1, +- }, +- { +- .name = "ppp", +- .gpio = 22, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 23, +- .active_low = 1, +- }, +- { +- .name = "power", +- .gpio = 4, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 5, +- }, +- }, + }; + + static struct board_info __initdata board_96358vw2 = { +@@ -1314,29 +1075,6 @@ static struct board_info __initdata boar + .has_pccard = 1, + .has_ehci0 = 1, + .num_usbh_ports = 2, +- +- .leds = { +- { +- .name = "adsl", +- .gpio = 22, +- .active_low = 1, +- }, +- { +- .name = "ppp-fail", +- .gpio = 23, +- }, +- { +- .name = "power", +- .gpio = 5, +- .active_low = 1, +- .default_trigger = "default-on", +- }, +- { +- .name = "stop", +- .gpio = 4, +- .active_low = 1, +- }, +- }, + }; + + static struct board_info __initdata board_CPVA642 = { diff --git a/target/linux/brcm63xx/patches-4.1/555-board_96318ref.patch b/target/linux/brcm63xx/patches-4.1/555-board_96318ref.patch new file mode 100644 index 0000000..252fd3f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/555-board_96318ref.patch @@ -0,0 +1,79 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -57,6 +57,56 @@ static struct board_info __initdata boar + #endif /* CONFIG_BCM63XX_CPU_3368 */ + + /* ++ * known 6318 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_6318 ++static struct board_info __initdata board_96318ref = { ++ .name = "96318REF", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; ++#endif /* CONFIG_BCM63XX_CPU_6318 */ ++ ++/* + * known 6328 boards + */ + #ifdef CONFIG_BCM63XX_CPU_6328 +@@ -1608,6 +1658,9 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_3368 + &board_cvg834g, + #endif ++#ifdef CONFIG_BCM63XX_CPU_6318 ++ &board_96318ref, ++#endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, + &board_AR5381u, +@@ -1685,6 +1738,9 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_3368 + { .compatible = "netgear,cvg834g", .data = &board_cvg834g, }, + #endif ++#ifdef CONFIG_BCM63XX_CPU_6318 ++ { .compatible = "brcm,bcm96318ref", .data = &board_96318ref, }, ++#endif + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, diff --git a/target/linux/brcm63xx/patches-4.1/556-board_96318ref_p300.patch b/target/linux/brcm63xx/patches-4.1/556-board_96318ref_p300.patch new file mode 100644 index 0000000..18d0f07 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/556-board_96318ref_p300.patch @@ -0,0 +1,70 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -104,6 +104,51 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_96318ref_p300 = { ++ .name = "96318REF_P300", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6318 */ + + /* +@@ -1660,6 +1705,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_6318 + &board_96318ref, ++ &board_96318ref_p300, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, +@@ -1740,6 +1786,7 @@ static struct of_device_id const bcm963x + #endif + #ifdef CONFIG_BCM63XX_CPU_6318 + { .compatible = "brcm,bcm96318ref", .data = &board_96318ref, }, ++ { .compatible = "brcm,bcm96318ref_p300", .data = &board_96318ref_p300, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, diff --git a/target/linux/brcm63xx/patches-4.1/557-board_bcm963269bhr.patch b/target/linux/brcm63xx/patches-4.1/557-board_bcm963269bhr.patch new file mode 100644 index 0000000..89a2a4f --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/557-board_bcm963269bhr.patch @@ -0,0 +1,73 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1697,6 +1697,52 @@ static struct board_info __initdata boar + #endif /* CONFIG_BCM63XX_CPU_6368 */ + + /* ++ * known 63268/63269 boards ++ */ ++#ifdef CONFIG_BCM63XX_CPU_63268 ++static struct board_info __initdata board_963269bhr = { ++ .name = "963269BHR", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_pci = 1, ++ ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++}; ++#endif /* CONFIG_BCM63XX_CPU_63268 */ ++ ++/* + * all boards + */ + static const struct board_info __initconst *bcm963xx_boards[] = { +@@ -1777,6 +1823,9 @@ static const struct board_info __initcon + &board_96368mvwg, + &board_96368mvngr, + #endif ++#ifdef CONFIG_BCM63XX_CPU_63268 ++ &board_963269bhr, ++#endif + }; + + static struct of_device_id const bcm963xx_boards_dt[] = { +@@ -1864,6 +1913,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 ++ { .compatible = "brcm,bcm963269bhr", .data = &board_963269bhr, }, + #endif + #endif /* CONFIG_OF */ + { }, diff --git a/target/linux/brcm63xx/patches-4.1/558-board_AR1004G.patch b/target/linux/brcm63xx/patches-4.1/558-board_AR1004G.patch new file mode 100644 index 0000000..74aad59 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/558-board_AR1004G.patch @@ -0,0 +1,49 @@ +From: "mexit@o2.pl" +Date: Sun, 24 Nov 2013 21:33:38 +0000 +Subject: [PATCH 4/5] brcm63xx: add support for Asmax AR 1004g router + +Support for Asmax AR 1004g router + +Signed-off-by: Adrian Feliks +--- +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -682,6 +682,22 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct board_info __initdata board_96348gw_10_AR1004G = { ++ .name = "AR1004G", ++ .expected_cpu_id = 0x6348, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++}; ++ + + /* BT Voyager 2110 */ + static struct board_info __initdata board_V2110 = { +@@ -1794,6 +1810,7 @@ static const struct board_info __initcon + &board_96348A_122, + &board_CPVA502plus, + &board_96348W3, ++ &board_96348gw_10_AR1004G, + #endif + + #ifdef CONFIG_BCM63XX_CPU_6358 +@@ -1858,6 +1875,7 @@ static struct of_device_id const bcm963x + { .compatible = "dynalink,rta770w", .data = &board_rta770w, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6348 ++ { .compatible = "asmax,ar1004g", .data = &board_96348gw_10_AR1004G, }, + { .compatible = "belkin,f5d7633", .data = &board_96348gw_10, }, + { .compatible = "brcm,bcm96348r", .data = &board_96348r, }, + { .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, }, diff --git a/target/linux/brcm63xx/patches-4.1/559-board_vw6339gu.patch b/target/linux/brcm63xx/patches-4.1/559-board_vw6339gu.patch new file mode 100644 index 0000000..2e647c9 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/559-board_vw6339gu.patch @@ -0,0 +1,72 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1756,6 +1756,53 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct board_info __initdata board_vw6339gu = { ++ .name = "VW6339GU", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_ehci0 = 1, ++ .has_ohci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "LAN2", ++ }, ++ ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "LAN3", ++ }, ++ ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "LAN4", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "LAN1", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 7, ++ .name = "WAN", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_63268 */ + + /* +@@ -1842,6 +1889,7 @@ static const struct board_info __initcon + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + &board_963269bhr, ++ &board_vw6339gu, + #endif + }; + +@@ -1932,6 +1980,7 @@ static struct of_device_id const bcm963x + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + { .compatible = "brcm,bcm963269bhr", .data = &board_963269bhr, }, ++ { .compatible = "inteno,vg50", .data = &board_vw6339gu, }, + #endif + #endif /* CONFIG_OF */ + { }, diff --git a/target/linux/brcm63xx/patches-4.1/560-board_963268gu_p300.patch b/target/linux/brcm63xx/patches-4.1/560-board_963268gu_p300.patch new file mode 100644 index 0000000..5e51d80 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/560-board_963268gu_p300.patch @@ -0,0 +1,85 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1716,6 +1716,66 @@ static struct board_info __initdata boar + * known 63268/63269 boards + */ + #ifdef CONFIG_BCM63XX_CPU_63268 ++static struct board_info __initdata board_963268bu_p300 = { ++ .name = "963268BU_P300", ++ .expected_cpu_id = 0x63268, ++ ++ .has_uart0 = 1, ++ ++ .has_ehci0 = 1, ++ .has_ohci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .has_usbd = 1, ++ ++ .usbd = { ++ .use_fullspeed = 0, ++ .port_no = 0, ++ }, ++ ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 17, ++ .name = "FE1", ++ }, ++ ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "GbE2", ++ }, ++ ++ [4] = { ++ .used = 1, ++ .phy_id = 0, ++ .name = "GbE3", ++ }, ++ ++ [5] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "GbE1", ++ }, ++ ++ [6] = { ++ .used = 1, ++ .phy_id = 24, ++ .name = "GbE4", ++ }, ++ ++ [7] = { ++ .used = 1, ++ .phy_id = 25, ++ .name = "GbE5", ++ }, ++ }, ++ }, ++}; ++ + static struct board_info __initdata board_963269bhr = { + .name = "963269BHR", + .expected_cpu_id = 0x63268, +@@ -1888,6 +1948,7 @@ static const struct board_info __initcon + &board_96368mvngr, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 ++ &board_963268bu_p300, + &board_963269bhr, + &board_vw6339gu, + #endif +@@ -1979,6 +2040,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 ++ { .compatible = "brcm,bcm963268bu_p300", .data = &board_963268bu_p300, }, + { .compatible = "brcm,bcm963269bhr", .data = &board_963269bhr, }, + { .compatible = "inteno,vg50", .data = &board_vw6339gu, }, + #endif diff --git a/target/linux/brcm63xx/patches-4.1/561-board_WAP-5813n.patch b/target/linux/brcm63xx/patches-4.1/561-board_WAP-5813n.patch new file mode 100644 index 0000000..5d0f914 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/561-board_WAP-5813n.patch @@ -0,0 +1,94 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -12,7 +12,9 @@ + #include + #include + #include ++#include + #include ++#include + #include + #include + #include +@@ -1710,6 +1712,65 @@ static struct board_info __initdata boar + .has_ohci0 = 1, + .has_ehci0 = 1, + }; ++ ++static struct b53_platform_data WAP5813n_b53_pdata = { ++ .alias = "eth0", ++}; ++ ++static struct spi_board_info WAP5813n_spi_devices[] = { ++ { ++ .modalias = "b53-switch", ++ .max_speed_hz = 781000, ++ .bus_num = 0, ++ .chip_select = 0, ++ .platform_data = &WAP5813n_b53_pdata, ++ } ++}; ++ ++static struct sprom_fixup __initdata wap5813n_fixups[] = { ++ { .offset = 97, .value = 0xfeed }, ++ { .offset = 98, .value = 0x15d1 }, ++ { .offset = 99, .value = 0xfb0d }, ++ { .offset = 113, .value = 0xfef7 }, ++ { .offset = 114, .value = 0x15f7 }, ++ { .offset = 115, .value = 0xfb1a }, ++}; ++ ++static struct board_info __initdata board_WAP5813n = { ++ .name = "96369R-1231N", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [4] = { ++ .used = 1, ++ .phy_id = 0xff, ++ .bypass_link = 1, ++ .force_speed = 1000, ++ .force_duplex_full = 1, ++ .name = "RGMII", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43222, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = wap5813n_fixups, ++ .num_board_fixups = ARRAY_SIZE(wap5813n_fixups), ++ }, ++ ++ .spis = WAP5813n_spi_devices, ++ .num_spis = ARRAY_SIZE(WAP5813n_spi_devices), ++}; + #endif /* CONFIG_BCM63XX_CPU_6368 */ + + /* +@@ -1946,6 +2007,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, ++ &board_WAP5813n, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + &board_963268bu_p300, +@@ -2038,6 +2100,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6368 + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, ++ { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + { .compatible = "brcm,bcm963268bu_p300", .data = &board_963268bu_p300, }, diff --git a/target/linux/brcm63xx/patches-4.1/562-board_VR-3025u.patch b/target/linux/brcm63xx/patches-4.1/562-board_VR-3025u.patch new file mode 100644 index 0000000..fc17426 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/562-board_VR-3025u.patch @@ -0,0 +1,79 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1713,6 +1713,60 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct sprom_fixup __initdata vr3025u_fixups[] = { ++ { .offset = 97, .value = 0xfeb3 }, ++ { .offset = 98, .value = 0x1618 }, ++ { .offset = 99, .value = 0xfab0 }, ++ { .offset = 113, .value = 0xfed1 }, ++ { .offset = 114, .value = 0x1609 }, ++ { .offset = 115, .value = 0xfad9 }, ++}; ++ ++static struct board_info __initdata board_VR3025u = { ++ .name = "96368M-1541N", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43222, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = vr3025u_fixups, ++ .num_board_fixups = ARRAY_SIZE(vr3025u_fixups), ++ }, ++}; ++ + static struct b53_platform_data WAP5813n_b53_pdata = { + .alias = "eth0", + }; +@@ -2007,6 +2061,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, ++ &board_VR3025u, + &board_WAP5813n, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 +@@ -2100,6 +2155,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6368 + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, ++ { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 diff --git a/target/linux/brcm63xx/patches-4.1/563-board_VR-3025un.patch b/target/linux/brcm63xx/patches-4.1/563-board_VR-3025un.patch new file mode 100644 index 0000000..5dc5e8b --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/563-board_VR-3025un.patch @@ -0,0 +1,79 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1767,6 +1767,60 @@ static struct board_info __initdata boar + }, + }; + ++static struct sprom_fixup __initdata vr3025un_fixups[] = { ++ { .offset = 97, .value = 0xfeb3 }, ++ { .offset = 98, .value = 0x1618 }, ++ { .offset = 99, .value = 0xfab0 }, ++ { .offset = 113, .value = 0xfed1 }, ++ { .offset = 114, .value = 0x1609 }, ++ { .offset = 115, .value = 0xfad9 }, ++}; ++ ++static struct board_info __initdata board_VR3025un = { ++ .name = "96368M-1341N", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43222, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = vr3025un_fixups, ++ .num_board_fixups = ARRAY_SIZE(vr3025un_fixups), ++ }, ++}; ++ + static struct b53_platform_data WAP5813n_b53_pdata = { + .alias = "eth0", + }; +@@ -2062,6 +2116,7 @@ static const struct board_info __initcon + &board_96368mvwg, + &board_96368mvngr, + &board_VR3025u, ++ &board_VR3025un, + &board_WAP5813n, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 +@@ -2156,6 +2211,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, }, + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, ++ { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 diff --git a/target/linux/brcm63xx/patches-4.1/564-board_P870HW-51a_v2.patch b/target/linux/brcm63xx/patches-4.1/564-board_P870HW-51a_v2.patch new file mode 100644 index 0000000..af62746 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/564-board_P870HW-51a_v2.patch @@ -0,0 +1,68 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1722,6 +1722,49 @@ static struct sprom_fixup __initdata vr3 + { .offset = 115, .value = 0xfad9 }, + }; + ++static struct board_info __initdata board_P870HW51A_V2 = { ++ .name = "P870HW-51a_v2", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_VR3025u = { + .name = "96368M-1541N", + .expected_cpu_id = 0x6368, +@@ -2115,6 +2158,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, ++ &board_P870HW51A_V2, + &board_VR3025u, + &board_VR3025un, + &board_WAP5813n, +@@ -2213,6 +2257,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, ++ { .compatible = "zyxel,p870hw-51a-v2", .data = &board_P870HW51A_V2, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 + { .compatible = "brcm,bcm963268bu_p300", .data = &board_963268bu_p300, }, diff --git a/target/linux/brcm63xx/patches-4.1/565-board_hw520.patch b/target/linux/brcm63xx/patches-4.1/565-board_hw520.patch new file mode 100644 index 0000000..56371f3 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/565-board_hw520.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1360,6 +1360,37 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_HW520 = { ++ .name = "HW6358GW_B", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enet0 = 1, ++ .enet0 = { ++ .has_phy = 1, ++ .use_internal_phy = 1, ++ }, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4318, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_HW553 = { + .name = "HW553", + .expected_cpu_id = 0x6358, +@@ -2142,6 +2173,7 @@ static const struct board_info __initcon + &board_nb4_ser_r0, + &board_nb4_fxc_r1, + &board_ct6373_1, ++ &board_HW520, + &board_HW553, + &board_HW556_A, + &board_HW556_B, +@@ -2234,6 +2266,7 @@ static struct of_device_id const bcm963x + { .compatible = "d-link,dsl-274xb-c2", .data = &board_dsl_274xb_rev_c, }, + { .compatible = "d-link,dsl-2650u", .data = &board_96358vw2, }, + { .compatible = "d-link,dva-g3810bn/tl", .data = &board_DVAG3810BN, }, ++ { .compatible = "huawei,hg520v", .data = &board_HW520, }, + { .compatible = "huawei,hg553", .data = &board_HW553, }, + { .compatible = "huawei,hg556a-a", .data = &board_HW556_A, }, + { .compatible = "huawei,hg556a-b", .data = &board_HW556_B, }, diff --git a/target/linux/brcm63xx/patches-4.1/566-board_A4001N.patch b/target/linux/brcm63xx/patches-4.1/566-board_A4001N.patch new file mode 100644 index 0000000..4647e81 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/566-board_A4001N.patch @@ -0,0 +1,69 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -362,6 +362,50 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_A4001N = { ++ .name = "96328dg2x2", ++ .expected_cpu_id = 0x6328, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ .has_enetsw = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43225, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ }, ++}; ++ + static struct board_info __initdata board_A4001N1 = { + .name = "963281T_TEF", + .expected_cpu_id = 0x6328, +@@ -2124,6 +2168,7 @@ static const struct board_info __initcon + &board_AR5381u, + &board_AR5387un, + &board_963281TAN, ++ &board_A4001N, + &board_A4001N1, + &board_dsl_274xb_f1, + &board_FAST2704V2, +@@ -2212,6 +2257,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96318ref_p300", .data = &board_96318ref_p300, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 ++ { .compatible = "adb,a4001n", .data = &board_A4001N, }, + { .compatible = "adb,a4001n1", .data = &board_A4001N1, }, + { .compatible = "brcm,bcm963281TAN", .data = &board_963281TAN, }, + { .compatible = "brcm,bcm96328avng", .data = &board_96328avng, }, diff --git a/target/linux/brcm63xx/patches-4.1/567-board_dsl-2751b_e1.patch b/target/linux/brcm63xx/patches-4.1/567-board_dsl-2751b_e1.patch new file mode 100644 index 0000000..4d5b294 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/567-board_dsl-2751b_e1.patch @@ -0,0 +1,94 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -151,6 +151,75 @@ static struct board_info __initdata boar + }, + }, + }; ++ ++static struct sprom_fixup __initdata dsl2751b_e1_fixups[] = { ++ { .offset = 96, .value = 0x2046 }, ++ { .offset = 97, .value = 0xfe9d }, ++ { .offset = 98, .value = 0x1854 }, ++ { .offset = 99, .value = 0xfa59 }, ++ { .offset = 112, .value = 0x2046 }, ++ { .offset = 113, .value = 0xfe79 }, ++ { .offset = 114, .value = 0x17f5 }, ++ { .offset = 115, .value = 0xfa47 }, ++ { .offset = 161, .value = 0x2222 }, ++ { .offset = 162, .value = 0x2222 }, ++ { .offset = 169, .value = 0x2222 }, ++ { .offset = 170, .value = 0x2222 }, ++ { .offset = 171, .value = 0x5555 }, ++ { .offset = 172, .value = 0x5555 }, ++ { .offset = 173, .value = 0x4444 }, ++ { .offset = 174, .value = 0x4444 }, ++ { .offset = 175, .value = 0x5555 }, ++ { .offset = 176, .value = 0x5555 }, ++}; ++ ++static struct board_info __initdata board_dsl_2751b_d1 = { ++ .name = "AW5200B", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .has_enetsw = 1, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43217, ++ .pci_bus = 1, ++ .pci_dev = 0, ++ .board_fixups = dsl2751b_e1_fixups, ++ .num_board_fixups = ARRAY_SIZE(dsl2751b_e1_fixups), ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6318 */ + + /* +@@ -2162,6 +2231,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6318 + &board_96318ref, + &board_96318ref_p300, ++ &board_dsl_2751b_d1, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, +@@ -2255,6 +2325,7 @@ static struct of_device_id const bcm963x + #ifdef CONFIG_BCM63XX_CPU_6318 + { .compatible = "brcm,bcm96318ref", .data = &board_96318ref, }, + { .compatible = "brcm,bcm96318ref_p300", .data = &board_96318ref_p300, }, ++ { .compatible = "d-link,dsl-275xb-d", .data = &board_dsl_2751b_d1, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "adb,a4001n", .data = &board_A4001N, }, diff --git a/target/linux/brcm63xx/patches-4.1/568-board_DGND3700v1_3800B.patch b/target/linux/brcm63xx/patches-4.1/568-board_DGND3700v1_3800B.patch new file mode 100644 index 0000000..9f722ee --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/568-board_DGND3700v1_3800B.patch @@ -0,0 +1,67 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1857,6 +1857,48 @@ static struct board_info __initdata boar + .has_ehci0 = 1, + }; + ++static struct b53_platform_data DGND3700v1_3800B_b53_pdata = { ++ .alias = "eth0", ++}; ++ ++static struct spi_board_info DGND3700v1_3800B_spi_devices[] = { ++ { ++ .modalias = "b53-switch", ++ .max_speed_hz = 781000, ++ .bus_num = 0, ++ .chip_select = 1, ++ .platform_data = &DGND3700v1_3800B_b53_pdata, ++ } ++}; ++ ++static struct board_info __initdata board_DGND3700v1_3800B = { ++ .name = "DGND3700v1_3800B", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [5] = { ++ .used = 1, ++ .phy_id = 0xff, ++ .bypass_link = 1, ++ .force_speed = 1000, ++ .force_duplex_full = 1, ++ .name = "RGMII", ++ }, ++ }, ++ }, ++ ++ .spis = DGND3700v1_3800B_spi_devices, ++ .num_spis = ARRAY_SIZE(DGND3700v1_3800B_spi_devices), ++}; ++ + static struct sprom_fixup __initdata vr3025u_fixups[] = { + { .offset = 97, .value = 0xfeb3 }, + { .offset = 98, .value = 0x1618 }, +@@ -2305,6 +2347,7 @@ static const struct board_info __initcon + #ifdef CONFIG_BCM63XX_CPU_6368 + &board_96368mvwg, + &board_96368mvngr, ++ &board_DGND3700v1_3800B, + &board_P870HW51A_V2, + &board_VR3025u, + &board_VR3025un, +@@ -2407,6 +2450,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, ++ { .compatible = "netgear,dgnd3700v1", .data = &board_DGND3700v1_3800B, }, + { .compatible = "zyxel,p870hw-51a-v2", .data = &board_P870HW51A_V2, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 diff --git a/target/linux/brcm63xx/patches-4.1/569-board_homehub2a.patch b/target/linux/brcm63xx/patches-4.1/569-board_homehub2a.patch new file mode 100644 index 0000000..6897cef --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/569-board_homehub2a.patch @@ -0,0 +1,51 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1473,6 +1473,32 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_homehub2a = { ++ .name = "HOMEHUB2A", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_enet1 = 1, ++ .enet1 = { ++ .has_phy = 1, ++ .phy_id = 0, ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM4322, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ }, ++}; ++ + static struct board_info __initdata board_HW520 = { + .name = "HW6358GW_B", + .expected_cpu_id = 0x6358, +@@ -2330,6 +2356,7 @@ static const struct board_info __initcon + &board_nb4_ser_r0, + &board_nb4_fxc_r1, + &board_ct6373_1, ++ &board_homehub2a, + &board_HW520, + &board_HW553, + &board_HW556_A, +@@ -2439,6 +2466,7 @@ static struct of_device_id const bcm963x + { .compatible = "sfr,nb4-fxc-r1", .data = &board_nb4_fxc_r1, }, + { .compatible = "t-com,spw303v", .data = &board_spw303v, }, + { .compatible = "telsey,cpva642", .data = &board_CPVA642, }, ++ { .compatible = "thomson,homehub2a", .data = &board_homehub2a, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6362 + { .compatible = "sagem,f@st2504n", .data = &board_fast2504n, }, diff --git a/target/linux/brcm63xx/patches-4.1/570-board_HG655b.patch b/target/linux/brcm63xx/patches-4.1/570-board_HG655b.patch new file mode 100644 index 0000000..fad8209 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/570-board_HG655b.patch @@ -0,0 +1,72 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -1925,6 +1925,53 @@ static struct board_info __initdata boar + .num_spis = ARRAY_SIZE(DGND3700v1_3800B_spi_devices), + }; + ++static struct board_info __initdata board_HG655b = { ++ .name = "HW65x", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 2, ++ ++ .has_caldata = 1, ++ .caldata = { ++ { ++ .vendor = PCI_VENDOR_ID_RALINK, ++ .caldata_offset = 0x7c0000, ++ .slot = 1, ++ .eeprom = "rt2x00.eeprom", ++ }, ++ }, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++}; ++ + static struct sprom_fixup __initdata vr3025u_fixups[] = { + { .offset = 97, .value = 0xfeb3 }, + { .offset = 98, .value = 0x1618 }, +@@ -2375,6 +2422,7 @@ static const struct board_info __initcon + &board_96368mvwg, + &board_96368mvngr, + &board_DGND3700v1_3800B, ++ &board_HG655b, + &board_P870HW51A_V2, + &board_VR3025u, + &board_VR3025un, +@@ -2478,6 +2526,7 @@ static struct of_device_id const bcm963x + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, ++ { .compatible = "huawei,hg655b", .data = &board_HG655b, }, + { .compatible = "netgear,dgnd3700v1", .data = &board_DGND3700v1_3800B, }, + { .compatible = "zyxel,p870hw-51a-v2", .data = &board_P870HW51A_V2, }, + #endif diff --git a/target/linux/brcm63xx/patches-4.1/571-board_fast2704n.patch b/target/linux/brcm63xx/patches-4.1/571-board_fast2704n.patch new file mode 100644 index 0000000..664a120 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/571-board_fast2704n.patch @@ -0,0 +1,65 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -220,6 +220,46 @@ static struct board_info __initdata boar + .num_board_fixups = ARRAY_SIZE(dsl2751b_e1_fixups), + }, + }; ++ ++static struct board_info __initdata board_FAST2704N = { ++ .name = "F@ST2704N", ++ .expected_cpu_id = 0x6318, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ ++ .has_enetsw = 1, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ .num_usbh_ports = 1, ++ ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "Port 1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "Port 2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "Port 3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "Port 4", ++ }, ++ }, ++ }, ++}; + #endif /* CONFIG_BCM63XX_CPU_6318 */ + + /* +@@ -2347,6 +2387,7 @@ static const struct board_info __initcon + &board_96318ref, + &board_96318ref_p300, + &board_dsl_2751b_d1, ++ &board_FAST2704N, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + &board_96328avng, +@@ -2444,6 +2485,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96318ref", .data = &board_96318ref, }, + { .compatible = "brcm,bcm96318ref_p300", .data = &board_96318ref_p300, }, + { .compatible = "d-link,dsl-275xb-d", .data = &board_dsl_2751b_d1, }, ++ { .compatible = "sagem,f@st2704n", .data = &board_FAST2704N, }, + #endif + #ifdef CONFIG_BCM63XX_CPU_6328 + { .compatible = "adb,a4001n", .data = &board_A4001N, }, diff --git a/target/linux/brcm63xx/patches-4.1/572-board_VR-3026e.patch b/target/linux/brcm63xx/patches-4.1/572-board_VR-3026e.patch new file mode 100644 index 0000000..c19c4f8 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/572-board_VR-3026e.patch @@ -0,0 +1,79 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -2163,6 +2163,60 @@ static struct board_info __initdata boar + }, + }; + ++static struct sprom_fixup __initdata vr3026e_fixups[] = { ++ { .offset = 97, .value = 0xfeb3 }, ++ { .offset = 98, .value = 0x1618 }, ++ { .offset = 99, .value = 0xfab0 }, ++ { .offset = 113, .value = 0xfed1 }, ++ { .offset = 114, .value = 0x1609 }, ++ { .offset = 115, .value = 0xfad9 }, ++}; ++ ++static struct board_info __initdata board_VR3026e = { ++ .name = "96368MT-1341N1", ++ .expected_cpu_id = 0x6368, ++ ++ .has_uart0 = 1, ++ .has_pci = 1, ++ .use_fallback_sprom = 1, ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ .has_enetsw = 1, ++ .enetsw = { ++ .used_ports = { ++ [0] = { ++ .used = 1, ++ .phy_id = 1, ++ .name = "port1", ++ }, ++ [1] = { ++ .used = 1, ++ .phy_id = 2, ++ .name = "port2", ++ }, ++ [2] = { ++ .used = 1, ++ .phy_id = 3, ++ .name = "port3", ++ }, ++ [3] = { ++ .used = 1, ++ .phy_id = 4, ++ .name = "port4", ++ }, ++ }, ++ }, ++ ++ .fallback_sprom = { ++ .type = SPROM_BCM43222, ++ .pci_bus = 0, ++ .pci_dev = 1, ++ .board_fixups = vr3026e_fixups, ++ .num_board_fixups = ARRAY_SIZE(vr3026e_fixups), ++ }, ++}; ++ + static struct b53_platform_data WAP5813n_b53_pdata = { + .alias = "eth0", + }; +@@ -2467,6 +2521,7 @@ static const struct board_info __initcon + &board_P870HW51A_V2, + &board_VR3025u, + &board_VR3025un, ++ &board_VR3026e, + &board_WAP5813n, + #endif + #ifdef CONFIG_BCM63XX_CPU_63268 +@@ -2567,6 +2622,7 @@ static struct of_device_id const bcm963x + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, }, + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, }, + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, }, ++ { .compatible = "comtrend,vr-3026e", .data = &board_VR3026e, }, + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, }, + { .compatible = "huawei,hg655b", .data = &board_HG655b, }, + { .compatible = "netgear,dgnd3700v1", .data = &board_DGND3700v1_3800B, }, diff --git a/target/linux/brcm63xx/patches-4.1/800-wl_exports.patch b/target/linux/brcm63xx/patches-4.1/800-wl_exports.patch new file mode 100644 index 0000000..68d37c7 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/800-wl_exports.patch @@ -0,0 +1,25 @@ +--- a/arch/mips/bcm63xx/nvram.c ++++ b/arch/mips/bcm63xx/nvram.c +@@ -40,6 +40,12 @@ struct bcm963xx_nvram { + static struct bcm963xx_nvram nvram; + static int mac_addr_used; + ++/* ++ * Required export for WL ++ */ ++u32 nvram_buf[5] = { 0, cpu_to_le32(20), 0, 0, 0 }; ++EXPORT_SYMBOL(nvram_buf); ++ + void __init bcm63xx_nvram_init(void *addr) + { + unsigned int check_len; +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -59,6 +59,7 @@ void (*_dma_cache_wback)(unsigned long s + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + + EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_inv); + + #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ + diff --git a/target/linux/brcm63xx/patches-4.1/801-ssb_export_fallback_sprom.patch b/target/linux/brcm63xx/patches-4.1/801-ssb_export_fallback_sprom.patch new file mode 100644 index 0000000..11a8353 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/801-ssb_export_fallback_sprom.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/bcm63xx/sprom.c ++++ b/arch/mips/bcm63xx/sprom.c +@@ -8,6 +8,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -387,7 +388,19 @@ struct fallback_sprom_match { + struct ssb_sprom sprom; + }; + +-static struct fallback_sprom_match fallback_sprom; ++struct fallback_sprom_match fallback_sprom; ++ ++int bcm63xx_get_fallback_sprom(uint pci_bus, uint pci_slot, struct ssb_sprom *out) ++{ ++ if (pci_bus != fallback_sprom.pci_bus || ++ pci_slot != fallback_sprom.pci_dev) ++ pr_warn("fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\n", ++ fallback_sprom.pci_bus, fallback_sprom.pci_dev, ++ pci_bus, pci_slot); ++ memcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom)); ++ return 0; ++} ++EXPORT_SYMBOL(bcm63xx_get_fallback_sprom); + + #if defined(CONFIG_SSB_PCIHOST) + int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out) diff --git a/target/linux/brcm63xx/patches-4.1/802-rtl8367r_fix_RGMII_support.patch b/target/linux/brcm63xx/patches-4.1/802-rtl8367r_fix_RGMII_support.patch new file mode 100644 index 0000000..9037d89 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/802-rtl8367r_fix_RGMII_support.patch @@ -0,0 +1,30 @@ +From e3208e6087642b95a5bab3101fc9c6e34892c861 Mon Sep 17 00:00:00 2001 +From: Miguel GAIO +Date: Fri, 6 Jul 2012 14:12:33 +0200 +Subject: [PATCH 6/8] * [rtl8367r] Fix RGMII support + +--- + drivers/net/phy/rtl8367.c | 5 +++++ + 1 files changed, 5 insertions(+), 0 deletions(-) + +--- a/drivers/net/phy/rtl8367.c ++++ b/drivers/net/phy/rtl8367.c +@@ -146,6 +146,10 @@ + #define RTL8367_EXT_RGMXF_TXDELAY_MASK 1 + #define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7 + ++#define RTL8367_PHY_AD_REG 0x130f ++#define RTL8370_PHY_AD_DUMMY_1_OFFSET 5 ++#define RTL8370_PHY_AD_DUMMY_1_MASK 0xe0 ++ + #define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x)) + #define RTL8367_DI_FORCE_MODE BIT(12) + #define RTL8367_DI_FORCE_NWAY BIT(7) +@@ -894,6 +898,7 @@ static int rtl8367_extif_set_mode(struct + case RTL8367_EXTIF_MODE_RGMII_33V: + REG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367); + REG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777); ++ REG_RMW(smi, RTL8367_PHY_AD_REG, BIT(5), 0); + break; + + case RTL8367_EXTIF_MODE_TMII_MAC: diff --git a/target/linux/brcm63xx/patches-4.1/803-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch b/target/linux/brcm63xx/patches-4.1/803-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch new file mode 100644 index 0000000..8b603e8 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/803-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch @@ -0,0 +1,26 @@ +From ff3409ab17d56450943364ba49a16960e3cdda9b Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 6 Apr 2014 22:33:16 +0200 +Subject: [RFC] jffs2: work around unaligned accesses failing on bcm63xx/smp + +Unligned memcpy_fromio randomly fails with an unaligned dst. Work around +it by ensuring we are always doing aligned copies. + +Should fix filename corruption in jffs2 with SMP. + +Signed-off-by: Jonas Gorski +--- + fs/jffs2/nodelist.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/fs/jffs2/nodelist.h ++++ b/fs/jffs2/nodelist.h +@@ -255,7 +255,7 @@ struct jffs2_full_dirent + uint32_t ino; /* == zero for unlink */ + unsigned int nhash; + unsigned char type; +- unsigned char name[0]; ++ unsigned char name[0] __attribute__((aligned((sizeof(long))))); + }; + + /* diff --git a/target/linux/brcm63xx/patches-4.1/804-bcm63xx_enet_63268_rgmii_ports.patch b/target/linux/brcm63xx/patches-4.1/804-bcm63xx_enet_63268_rgmii_ports.patch new file mode 100644 index 0000000..770f39e --- /dev/null +++ b/target/linux/brcm63xx/patches-4.1/804-bcm63xx_enet_63268_rgmii_ports.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2272,6 +2272,10 @@ static int bcm_enetsw_open(struct net_de + + rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i)); + rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN; ++ if (BCMCPU_IS_63268()) { ++ rgmii_ctrl |= ENETSW_RGMII_CTRL_TIMING_SEL_EN; ++ rgmii_ctrl |= ENETSW_RGMII_CTRL_MII_OVERRIDE_EN; ++ } + enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); + } + diff --git a/target/linux/brcm63xx/profiles/00-default.mk b/target/linux/brcm63xx/profiles/00-default.mk new file mode 100644 index 0000000..a25be92 --- /dev/null +++ b/target/linux/brcm63xx/profiles/00-default.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/Default/description + Package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/brcm63xx/profiles/01-generic.mk b/target/linux/brcm63xx/profiles/01-generic.mk new file mode 100644 index 0000000..2a9eb15 --- /dev/null +++ b/target/linux/brcm63xx/profiles/01-generic.mk @@ -0,0 +1,123 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/963281TAN + NAME:=Generic 963281TAN + PACKAGES:= +endef +define Profile/963281TAN/Description + Package set optimized for 963281TAN. +endef +$(eval $(call Profile,963281TAN)) + +define Profile/96328avng + NAME:=Generic 96328avng + PACKAGES:= +endef +define Profile/96328avng/Description + Package set optimized for 96328avng. +endef +$(eval $(call Profile,96328avng)) + +define Profile/96338GW + NAME:=Generic 96338GW + PACKAGES:= +endef +define Profile/96338GW/Description + Package set optimized for 96338GW. +endef +$(eval $(call Profile,96338GW)) + +define Profile/96338W + NAME:=Generic 96338W + PACKAGES:= +endef +define Profile/96338W/Description + Package set optimized for 96338W. +endef +$(eval $(call Profile,96338W)) + +define Profile/96345GW2 + NAME:=Generic 96345GW2 + PACKAGES:= +endef +define Profile/96345GW2/Description + Package set optimized for 96345GW2. +endef +$(eval $(call Profile,96345GW2)) + +define Profile/96348GW + NAME:=Generic 96348GW + PACKAGES:= +endef +define Profile/96348GW/Description + Package set optimized for 96348GW. +endef +$(eval $(call Profile,96348GW)) + +define Profile/96348GW_10 + NAME:=Generic 96348GW-10 + PACKAGES:= +endef +define Profile/96348GW_10/Description + Package set optimized for 96348GW-10. +endef +$(eval $(call Profile,96348GW_10)) + +define Profile/96348GW_11 + NAME:=Generic 96348GW-11 + PACKAGES:= +endef +define Profile/96348GW_11/Description + Package set optimized for 96348GW-11. +endef +$(eval $(call Profile,96348GW_11)) + +define Profile/96348R + NAME:=Generic 96348R + PACKAGES:= +endef +define Profile/96348R/Description + Package set optimized for 96348R. +endef +$(eval $(call Profile,96348R)) + +define Profile/96358VW + NAME:=Generic 96358VW + PACKAGES:= +endef +define Profile/96358VW/Description + Package set optimized for 96358VW. +endef +$(eval $(call Profile,96358VW)) + +define Profile/96358VW2 + NAME:=Generic 96358VW2 + PACKAGES:= +endef +define Profile/96358VW2/Description + Package set optimized for 96358VW2. +endef +$(eval $(call Profile,96358VW2)) + +define Profile/96368MVNgr + NAME:=Generic 96368MVNgr + PACKAGES:= +endef +define Profile/96368MVNgr/Description + Package set optimized for 96368MVNgr. +endef +$(eval $(call Profile,96368MVNgr)) + +define Profile/96368MVWG + NAME:=Generic 96368MVWG + PACKAGES:= +endef +define Profile/96368MVWG/Description + Package set optimized for 96368MVWG. +endef +$(eval $(call Profile,96368MVWG)) diff --git a/target/linux/brcm63xx/profiles/adb.mk b/target/linux/brcm63xx/profiles/adb.mk new file mode 100644 index 0000000..13c7524 --- /dev/null +++ b/target/linux/brcm63xx/profiles/adb.mk @@ -0,0 +1,26 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/A4001N + NAME:=ADB P.DG A4001N + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/A4001N/Description + Package set optimized for A4001N. +endef +$(eval $(call Profile,A4001N)) + +define Profile/A4001N1 + NAME:=ADB P.DG A4001N1 + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/A4001N1/Description + Package set optimized for A4001N1. +endef +$(eval $(call Profile,A4001N1)) diff --git a/target/linux/brcm63xx/profiles/alcatel.mk b/target/linux/brcm63xx/profiles/alcatel.mk new file mode 100644 index 0000000..ec93a19 --- /dev/null +++ b/target/linux/brcm63xx/profiles/alcatel.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RG100A + NAME:=Alcatel RG100A + PACKAGES:=kmod-b43 wpad-mini\ + kmod-usb2 kmod-usb-ohci +endef +define Profile/RG100A/Description + Package set optimized for RG100A. +endef +$(eval $(call Profile,RG100A)) diff --git a/target/linux/brcm63xx/profiles/asmax.mk b/target/linux/brcm63xx/profiles/asmax.mk new file mode 100644 index 0000000..c8f0072 --- /dev/null +++ b/target/linux/brcm63xx/profiles/asmax.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/AR1004G + NAME:=Asmax AR 1004G + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/AR1004G/Description + Package set optimized for AR 1004G. +endef +$(eval $(call Profile,AR1004G)) diff --git a/target/linux/brcm63xx/profiles/belkin.mk b/target/linux/brcm63xx/profiles/belkin.mk new file mode 100644 index 0000000..4bd50b0 --- /dev/null +++ b/target/linux/brcm63xx/profiles/belkin.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/F5D7633 + NAME:=Belkin F5D7633 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/F5D7633/Description + Package set optimized for F5D7633. +endef +$(eval $(call Profile,F5D7633)) diff --git a/target/linux/brcm63xx/profiles/broadcom.mk b/target/linux/brcm63xx/profiles/broadcom.mk new file mode 100644 index 0000000..520a676 --- /dev/null +++ b/target/linux/brcm63xx/profiles/broadcom.mk @@ -0,0 +1,42 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/BCM96318REF + NAME:=Broadcom BCM9618REF reference board + PACKAGES:= kmod-b43 wpad-mini kmod-usb-ohci kmod-usb2 kmod-bcm63xx-udc +endef +define Profile/BCM96318REF/Description + Package set optimized for the Broadcom BCM96318REF reference board. +endef +$(eval $(call Profile,BCM96318REF)) + +define Profile/BCM96318REF_P300 + NAME:=Broadcom BCM96318REF_P300 reference board + PACKAGES:= kmod-b43 wpad-mini kmod-usb-ohci kmod-usb2 kmod-bcm63xx-udc +endef +define Profile/BCM96318REF_P300/Description + Package set optimized for the Broadcom BCM96318REF_P300 reference board. +endef +$(eval $(call Profile,BCM96318REF_P300)) + +define Profile/BCM963268BU_P300 + NAME:=Broadcom BCM963268BU_P300 reference board + PACKAGES:= kmod-usb-ohci kmod-usb2 kmod-bcm63xx-udc +endef +define Profile/BCM963268BU_P300/Description + Package set optimized for the Broadcom BCM963268BU_P300 reference board. +endef +$(eval $(call Profile,BCM963268BU_P300)) + +define Profile/BCM963269BHR + NAME:=Broadcom BCM963269BHR reference board + PACKAGES:= kmod-usb-ohci kmod-usb2 kmod-bcm63xx-udc +endef +define Profile/BCM963269BHR/Description + Package set optimized for the Broadcom BCM963269BHR reference board. +endef +$(eval $(call Profile,BCM963269BHR)) diff --git a/target/linux/brcm63xx/profiles/bt.mk b/target/linux/brcm63xx/profiles/bt.mk new file mode 100644 index 0000000..f76ac5c --- /dev/null +++ b/target/linux/brcm63xx/profiles/bt.mk @@ -0,0 +1,34 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/BTHOMEHUB2A + NAME:=BT Home Hub 2A + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci kmod-ledtrig-usbdev +endef +define Profile/BTHOMEHUB2A/Description + Package set optimized for BTHOMEHUB2A. +endef +$(eval $(call Profile,BTHOMEHUB2A)) + +define Profile/BTV2110 + NAME:=BT Voyager V2110 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/BTV2500V/Description + Package set optimized for BTV2110. +endef +$(eval $(call Profile,BTV2110)) + +define Profile/BTV2500V + NAME:=BT Voyager V2500V + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/BTV2500V/Description + Package set optimized for BTV2500V. +endef +$(eval $(call Profile,BTV2500V)) diff --git a/target/linux/brcm63xx/profiles/comtrend.mk b/target/linux/brcm63xx/profiles/comtrend.mk new file mode 100644 index 0000000..99fec4a --- /dev/null +++ b/target/linux/brcm63xx/profiles/comtrend.mk @@ -0,0 +1,93 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/AR5381u + NAME:=Comtrend AR-5381u + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/AR5381u/Description + Package set optimized for AR-5381u. +endef +$(eval $(call Profile,AR5381u)) + +define Profile/AR5387un + NAME:=Comtrend AR-5387un + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/AR5387un/Description + Package set optimized for AR-5387un. +endef +$(eval $(call Profile,AR5387un)) + +define Profile/CT536_CT5621 + NAME:=Comtrend CT-536+/CT-5621 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/CT536_CT5621/Description + Package set optimized for CT-536+/CT-5621. +endef +$(eval $(call Profile,CT536_CT5621)) + +define Profile/CT5365 + NAME:=Comtrend CT-5365 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/CT5365/Description + Package set optimized for CT-5365. +endef +$(eval $(call Profile,CT5365)) + +define Profile/CT6373 + NAME:=Comtrend CT-6373 + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/CT6373/Description + Package set optimized for CT-6373. +endef +$(eval $(call Profile,CT6373)) + +define Profile/VR3025u + NAME:=Comtrend VR-3025u + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/VR3025u/Description + Package set optimized for VR-3025u. +endef +$(eval $(call Profile,VR3025u)) + +define Profile/VR3025un + NAME:=Comtrend VR-3025un + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/VR3025un/Description + Package set optimized for VR-3025un. +endef +$(eval $(call Profile,VR3025un)) + +define Profile/VR3026e + NAME:=Comtrend VR-3026e + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/VR3026e/Description + Package set optimized for VR-3026e. +endef +$(eval $(call Profile,VR3026e)) + +define Profile/WAP5813n + NAME:=Comtrend WAP-5813n + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/WAP5813n/Description + Package set optimized for WAP-5813n. +endef +$(eval $(call Profile,WAP5813n)) diff --git a/target/linux/brcm63xx/profiles/d-link.mk b/target/linux/brcm63xx/profiles/d-link.mk new file mode 100644 index 0000000..1bd5fc8 --- /dev/null +++ b/target/linux/brcm63xx/profiles/d-link.mk @@ -0,0 +1,71 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DSL2640B_B + NAME:=D-Link DSL-2640B rev B2 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/DSL2640B_B/Description + Package set optimized for DSL-2640B rev B2. +endef +$(eval $(call Profile,DSL2640B_B)) + +define Profile/DSL2640U + NAME:=D-Link DSL-2640U/BRU/C + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/DSL2640U/Description + Package set optimized for DSL-2640U +endef +$(eval $(call Profile,DSL2640U)) + +define Profile/DSL2650U + NAME:=D-Link DSL-2650U + PACKAGES:=kmod-b43 wpad-mini\ + kmod-usb2 kmod-usb-ohci +endef +define Profile/DSL2650U/Description + Package set optimized for DSL-2650U. +endef +$(eval $(call Profile,DSL2650U)) + +define Profile/DSL274XB_C + NAME:=D-Link DSL-2740B/DSL-2741B rev C2/C3 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/DSL274XB_C/Description + Package set optimized for DSL-2740B/DSL-2741B rev C2/C3. +endef +$(eval $(call Profile,DSL274XB_C)) + +define Profile/DSL274XB_F + NAME:=D-Link DSL-2740B/DSL-2741B rev F1 + PACKAGES:=kmod-ath9k wpad-mini +endef +define Profile/DSL274XB_F/Description + Package set optimized for DSL-2740B/DSL-2741B rev F1. +endef +$(eval $(call Profile,DSL274XB_F)) + +define Profile/DSL275XB_D + NAME:=D-Link DSL-2750B/DSL-2751 rev D1 + PACKAGES:=kmod-b43 wpad-mini kmod-usb-ohci kmod-usb2 +endef +define Profile/DSL275XB_D/Description + Package set optimized for DSL-2750B/DSL-2751 rev D1. +endef +$(eval $(call Profile,DSL275XB_D)) + +define Profile/DVAG3810BN + NAME:=D-Link DVA-G3810BN/TL + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/DVAG3810BN/Description + Package set optimized for DVA-G3810BN/TL. +endef +$(eval $(call Profile,DVAG3810BN)) diff --git a/target/linux/brcm63xx/profiles/davolink.mk b/target/linux/brcm63xx/profiles/davolink.mk new file mode 100644 index 0000000..0097a80 --- /dev/null +++ b/target/linux/brcm63xx/profiles/davolink.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DV201AMR + NAME:=Davolink DV-201AMR + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/DV201AMR/Description + Package set optimized for DV-201AMR. +endef +$(eval $(call Profile,DV201AMR)) diff --git a/target/linux/brcm63xx/profiles/dynalink.mk b/target/linux/brcm63xx/profiles/dynalink.mk new file mode 100644 index 0000000..f15699f --- /dev/null +++ b/target/linux/brcm63xx/profiles/dynalink.mk @@ -0,0 +1,42 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/RTA770BW + NAME:=Dynalink RTA770BW (Siemens SE 515) + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/RTA770BW/Description + Package set optimized for RTA770BW. +endef +$(eval $(call Profile,RTA770BW)) + +define Profile/RTA770W + NAME:=Dynalink RTA770W + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/RTA770W/Description + Package set optimized for RTA770W. +endef +$(eval $(call Profile,RTA770W)) + +define Profile/RTA1025W + NAME:=Dynalink RTA1025W + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/RTA1025W/Description + Package set optimized for RTA1025W. +endef +$(eval $(call Profile,RTA1025W)) + +define Profile/RTA1320 + NAME:=Dynalink RTA1320 + PACKAGES:= +endef +define Profile/RTA1320/Description + Package set optimized for RTA1320. +endef +$(eval $(call Profile,RTA1320)) diff --git a/target/linux/brcm63xx/profiles/huawei.mk b/target/linux/brcm63xx/profiles/huawei.mk new file mode 100644 index 0000000..a6764b7 --- /dev/null +++ b/target/linux/brcm63xx/profiles/huawei.mk @@ -0,0 +1,55 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/HG520v + NAME:=Huawei EchoLife HG520v + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/HG520v/Description + Package set optimized for Huawei HG520v. +endef +$(eval $(call Profile,HG520v)) + +define Profile/HG553 + NAME:=Huawei EchoLife HG553 + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci kmod-ledtrig-usbdev +endef +define Profile/HG553/Description + Package set optimized for Huawei HG553. +endef +$(eval $(call Profile,HG553)) + +define Profile/HG556a_AB + NAME:=Huawei EchoLife HG556a (version A/B - Atheros) + PACKAGES:=kmod-ath9k wpad-mini \ + kmod-usb2 kmod-usb-ohci kmod-ledtrig-usbdev +endef +define Profile/HG556a_AB/Description + Package set optimized for Huawei HG556a version A/B (Atheros). +endef +$(eval $(call Profile,HG556a_AB)) + +define Profile/HG556a_C + NAME:=Huawei EchoLife HG556a (version C - Ralink) + PACKAGES:=kmod-rt2800-pci wpad-mini \ + kmod-usb2 kmod-usb-ohci kmod-ledtrig-usbdev +endef +define Profile/HG556a_C/Description + Package set optimized for Huawei HG556a version C (Ralink). +endef +$(eval $(call Profile,HG556a_C)) + +define Profile/HG655b + NAME:=Huawei HG655b + PACKAGES:=kmod-rt2800-pci wpad-mini \ + kmod-usb2 kmod-usb-ohci kmod-ledtrig-usbdev +endef +define Profile/HG655b/Description + Package set optimized for Huawei HG655b, HG655d. +endef +$(eval $(call Profile,HG655b)) diff --git a/target/linux/brcm63xx/profiles/inteno.mk b/target/linux/brcm63xx/profiles/inteno.mk new file mode 100644 index 0000000..a8043c9 --- /dev/null +++ b/target/linux/brcm63xx/profiles/inteno.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/VG50 + NAME:=Inteno VG50 Multi-WAN CPE + PACKAGES:= kmod-usb-ohci kmod-usb2 +endef +define Profile/VG50/Description + Package set optimized for the Inteno VG50 Multi-WAN CPE. +endef +$(eval $(call Profile,VG50)) diff --git a/target/linux/brcm63xx/profiles/inventel.mk b/target/linux/brcm63xx/profiles/inventel.mk new file mode 100644 index 0000000..a6733fc --- /dev/null +++ b/target/linux/brcm63xx/profiles/inventel.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Livebox + NAME:=Inventel Livebox 1 + PACKAGES:=kmod-b43 wpad-mini kmod-usb-ohci +endef +define Profile/Livebox/Description + Package set optimized for Inventel Livebox 1. +endef +$(eval $(call Profile,Livebox)) diff --git a/target/linux/brcm63xx/profiles/netgear.mk b/target/linux/brcm63xx/profiles/netgear.mk new file mode 100644 index 0000000..bc345bb --- /dev/null +++ b/target/linux/brcm63xx/profiles/netgear.mk @@ -0,0 +1,43 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CVG834G + NAME:=Netgear CVG834G + PACKAGES:= +endef +define Profile/CVG834G/Description + Package set optimized for CVG834G. +endef +$(eval $(call Profile,CVG834G)) + +define Profile/DG834GTPN + NAME:=Netgear DG834GT/PN + PACKAGES:=kmod-ath5k wpad-mini +endef +define Profile/DG834GTPN/Description + Package set optimized for DG834GT/PN. +endef +$(eval $(call Profile,DG834GTPN)) + +define Profile/DG834GV4 + NAME:=Netgear DG834G v4 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/DG834GTPN/Description + Package set optimized for DG834G v4. +endef +$(eval $(call Profile,DG834GV4)) + +define Profile/DGND3700v1_3800B + NAME:=Netgear DGND3700 v1 / DGND3800B + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci kmod-ledtrig-usbdev +endef +define Profile/DGND3700v1_3800B/Description + Package set optimized for DGND3700 v1 / DGND3800B. +endef +$(eval $(call Profile,DGND3700v1_3800B)) diff --git a/target/linux/brcm63xx/profiles/pirelli.mk b/target/linux/brcm63xx/profiles/pirelli.mk new file mode 100644 index 0000000..5861719 --- /dev/null +++ b/target/linux/brcm63xx/profiles/pirelli.mk @@ -0,0 +1,35 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/A226G + NAME:=Pirelli A226G + PACKAGES:=kmod-b43 wpad-mini\ + kmod-usb2 kmod-usb-ohci +endef +define Profile/A226G/Description + Package set optimized for A226G. +endef +$(eval $(call Profile,A226G)) + +define Profile/A226M + NAME:=Pirelli A226M/A226M-FWB + PACKAGES:=kmod-usb2 kmod-usb-ohci +endef +define Profile/A226M/Description + Package set optimized for A226M/A226M-FWB. +endef +$(eval $(call Profile,A226M)) + +define Profile/AGPF_S0 + NAME:=Pirelli Alice Gate VoIP 2 Plus Wi-Fi AGPF-S0 + PACKAGES:=kmod-b43 wpad-mini\ + kmod-usb2 kmod-usb-ohci +endef +define Profile/AGPF_S0/Description + Package set optimized for AGPF-S0. +endef +$(eval $(call Profile,AGPF_S0)) diff --git a/target/linux/brcm63xx/profiles/sagem.mk b/target/linux/brcm63xx/profiles/sagem.mk new file mode 100644 index 0000000..7d9a160 --- /dev/null +++ b/target/linux/brcm63xx/profiles/sagem.mk @@ -0,0 +1,53 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/FAST2404 + NAME:=Sagem F@ST2404 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/FAST2404/Description + Package set optimized for F@ST2404. +endef +$(eval $(call Profile,FAST2404)) + +define Profile/FAST2504n + NAME:=Sagem F@ST2504n + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/FAST2504n/Description + Package set optimized for F@ST2504n. +endef +$(eval $(call Profile,FAST2504n)) + +define Profile/FAST2604 + NAME:=Sagem F@ST2604 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/FAST2604/Description + Package set optimized for F@ST2604. +endef +$(eval $(call Profile,FAST2604)) + +define Profile/FAST2704N + NAME:=Sagem F@ST2704N + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/FAST2704N/Description + Package set optimized for F@ST2704N. +endef +$(eval $(call Profile,FAST2704N)) + +define Profile/FAST2704V2 + NAME:=Sagem F@ST2704V2 + PACKAGES:=kmod-b43 wpad-mini\ + kmod-usb2 kmod-usb-ohci +endef +define Profile/FAST2704V2/Description + Package set optimized for F@ST2704V2. +endef +$(eval $(call Profile,FAST2704V2)) diff --git a/target/linux/brcm63xx/profiles/sfr.mk b/target/linux/brcm63xx/profiles/sfr.mk new file mode 100644 index 0000000..8b0dd44 --- /dev/null +++ b/target/linux/brcm63xx/profiles/sfr.mk @@ -0,0 +1,26 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Neufbox4 + NAME:=SFR Neufbox4 + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/Neufbox4/Description + Package set optimized for Neufbox4. +endef +$(eval $(call Profile,Neufbox4)) + +define Profile/Neufbox6 + NAME:=SFR Neufbox6 + PACKAGES:=kmod-b43 wpad-mini \ + kmod-usb2 kmod-usb-ohci +endef +define Profile/Neufbox6/Description + Package set optimized for Neufbox6. +endef +$(eval $(call Profile,Neufbox6)) diff --git a/target/linux/brcm63xx/profiles/t-com.mk b/target/linux/brcm63xx/profiles/t-com.mk new file mode 100644 index 0000000..f1eaf0a --- /dev/null +++ b/target/linux/brcm63xx/profiles/t-com.mk @@ -0,0 +1,25 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/SPW303V + NAME:=T-Com Speedport W 303V + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/SPW303V/Description + Package set optimized for SPW303V. +endef +$(eval $(call Profile,SPW303V)) + + +define Profile/SPW500V + NAME:=T-Com Speedport W 500V + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/SPW500V/Description + Package set optimized for SPW500V. +endef +$(eval $(call Profile,SPW500V)) diff --git a/target/linux/brcm63xx/profiles/tecom.mk b/target/linux/brcm63xx/profiles/tecom.mk new file mode 100644 index 0000000..038ef5e --- /dev/null +++ b/target/linux/brcm63xx/profiles/tecom.mk @@ -0,0 +1,28 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/GW6000 + NAME:=Tecom GW6000 + PACKAGES:=kmod-brcm-wl kmod-usb-ohci kmod-usb-storage \ + kmod-fs-ext4 kmod-nls-cp437 kmod-nls-iso8859-1 e2fsprogs \ + kmod-ipt-nathelper-extra wlc +endef +define Profile/GW6000/Description + Package set optimized for GW6000. +endef +$(eval $(call Profile,GW6000)) + +define Profile/GW6200 + NAME:=Tecom GW6200 + PACKAGES:=kmod-brcm-wl kmod-usb-ohci kmod-usb-storage \ + kmod-fs-ext4 kmod-nls-cp437 kmod-nls-iso8859-1 e2fsprogs \ + kmod-ipt-nathelper-extra wlc +endef +define Profile/GW6200/Description + Package set optimized for GW6200. +endef +$(eval $(call Profile,GW6200)) diff --git a/target/linux/brcm63xx/profiles/telsey.mk b/target/linux/brcm63xx/profiles/telsey.mk new file mode 100644 index 0000000..759a273 --- /dev/null +++ b/target/linux/brcm63xx/profiles/telsey.mk @@ -0,0 +1,34 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/CPVA502PLUS + NAME:=Telsey CPVA502+ + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/CPVA502PLUS/Description + Package set optimized for CPVA502+. +endef +$(eval $(call Profile,CPVA502PLUS)) + +define Profile/CPVA642 + NAME:=Telsey CPVA642-type (CPA-ZNTE60T) + PACKAGES:=kmod-rt61-pci wpad-mini\ + kmod-usb2 kmod-usb-ohci +endef +define Profile/CPVA642/Description + Package set optimized for CPVA642-type. +endef +$(eval $(call Profile,CPVA642)) + +define Profile/MAGIC + NAME:=Telsey MAGIC (Alice W-Gate) + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/MAGIC/Description + Package set optimized for Telsey MAGIC (Alice W-Gate) +endef +$(eval $(call Profile,CPVA502PLUS)) diff --git a/target/linux/brcm63xx/profiles/tp-link.mk b/target/linux/brcm63xx/profiles/tp-link.mk new file mode 100644 index 0000000..a7e7f26 --- /dev/null +++ b/target/linux/brcm63xx/profiles/tp-link.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/TDW8900GB + NAME:=TP-Link TD-W8900GB + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/TDW8900GB/Description + Package set optimized for TD-W8900GB. +endef +$(eval $(call Profile,TDW8900GB)) diff --git a/target/linux/brcm63xx/profiles/usrobotics.mk b/target/linux/brcm63xx/profiles/usrobotics.mk new file mode 100644 index 0000000..76b5e12 --- /dev/null +++ b/target/linux/brcm63xx/profiles/usrobotics.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/USR9108 + NAME:=USRobotics 9108 + PACKAGES:=kmod-b43 wpad-mini\ + kmod-usb-ohci +endef +define Profile/USR9108/Description + Package set optimized for USR9108. +endef +$(eval $(call Profile,USR9108)) diff --git a/target/linux/brcm63xx/profiles/zyxel.mk b/target/linux/brcm63xx/profiles/zyxel.mk new file mode 100644 index 0000000..3aca094 --- /dev/null +++ b/target/linux/brcm63xx/profiles/zyxel.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/P870HW_51a_v2 + NAME:=ZyXEL P870HW-51a v2 + PACKAGES:=kmod-b43 wpad-mini +endef +define Profile/P870HW_51a_v2/Description + Package set optimized for P870HW-51a v2. +endef +$(eval $(call Profile,P870HW_51a_v2)) diff --git a/target/linux/brcm63xx/smp/config-default b/target/linux/brcm63xx/smp/config-default new file mode 100644 index 0000000..8afdf5e --- /dev/null +++ b/target/linux/brcm63xx/smp/config-default @@ -0,0 +1,13 @@ +CONFIG_CPU_RMAP=y +# CONFIG_KEXEC is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NR_CPUS=2 +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_STOP_MACHINE=y +CONFIG_TREE_RCU=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_XPS=y diff --git a/target/linux/brcm63xx/smp/target.mk b/target/linux/brcm63xx/smp/target.mk new file mode 100644 index 0000000..b0ccf97 --- /dev/null +++ b/target/linux/brcm63xx/smp/target.mk @@ -0,0 +1,8 @@ +BOARDNAME:=smp + +define Target/Description + Build firmware images for BCM63XX boards with SMP support. + Currently only BCM6362 and BCM6368 supported. +endef + + diff --git a/target/linux/cns3xxx/Makefile b/target/linux/cns3xxx/Makefile new file mode 100644 index 0000000..0b4432a --- /dev/null +++ b/target/linux/cns3xxx/Makefile @@ -0,0 +1,30 @@ +# +# Copyright (C) 2010-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=cns3xxx +BOARDNAME:=Cavium Networks Econa CNS3xxx +FEATURES:=squashfs fpu gpio pcie usb usbgadget +CPU_TYPE:=mpcore +CPU_SUBTYPE:=vfp +MAINTAINER:=Felix Fietkau + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +define Target/Description + Build images for Cavium Networks Econa CNS3xxx based boards, + eg. the Gateworks Laguna family +endef + +KERNELNAME:=zImage + +DEFAULT_PACKAGES += kmod-ath9k kmod-usb2 wpad-mini + +$(eval $(call BuildTarget)) diff --git a/target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu b/target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu new file mode 100755 index 0000000..3a2a57b --- /dev/null +++ b/target/linux/cns3xxx/base-files/etc/init.d/netdev-cpu @@ -0,0 +1,21 @@ +#!/bin/sh /etc/rc.common + +START=99 + +get_irq() { + local name="$1" + grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,' +} + +set_irq_affinity() { + local name="$1" + local val="$2" + local irq="$(get_irq "$name")" + [ -n "$irq" ] || return + echo "$val" > "/proc/irq/$irq/smp_affinity" +} + +start() { + set_irq_affinity gig_switch 2 + set_irq_affinity gig_stat 2 +} diff --git a/target/linux/cns3xxx/base-files/lib/cns3xxx.sh b/target/linux/cns3xxx/base-files/lib/cns3xxx.sh new file mode 100644 index 0000000..476f9be --- /dev/null +++ b/target/linux/cns3xxx/base-files/lib/cns3xxx.sh @@ -0,0 +1,22 @@ +#!/bin/sh +# +# Copyright (C) 2012 OpenWrt.org +# + +cns3xxx_board_name() { + local machine + local name + + machine=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /Hardware/ {print $2}' /proc/cpuinfo) + + case "$machine" in + "Gateworks Corporation Laguna"*) + name="laguna" + ;; + *) + name="generic"; + ;; + esac + + echo $name +} diff --git a/target/linux/cns3xxx/base-files/lib/upgrade/platform.sh b/target/linux/cns3xxx/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..6d94a53 --- /dev/null +++ b/target/linux/cns3xxx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,122 @@ +. /lib/cns3xxx.sh + +RAMFS_COPY_DATA="/lib/cns3xxx.sh" + +CI_BLKSZ=65536 + +platform_find_partitions() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + vmlinux.bin.l7|kernel|linux|rootfs) + if [ -z "$first" ]; then + first="$name" + else + echo "$erasesize:$first:$name" + break + fi + ;; + esac + done < /proc/mtd +} + +platform_find_kernelpart() { + local part + for part in "${1%:*}" "${1#*:}"; do + case "$part" in + vmlinux.bin.l7|kernel|linux) + echo "$part" + break + ;; + esac + done +} + +platform_do_upgrade_combined() { + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}" + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local kern_blocks=$(($kern_length / $CI_BLKSZ)) + local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ)) + + v "platform_do_upgrade_combined" + v "partitions=$partitions" + v "kernelpart=$kernelpart" + v "erase_size=$erase_size" + v "kern_blocks=$kern_blocks" + v "root_blocks=$root_blocks" + + if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \ + [ ${kern_blocks:-0} -gt 0 ] && \ + [ ${root_blocks:-0} -gt 0 ] && \ + [ ${erase_size:-0} -gt 0 ]; + then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null | mtd write - kernel + dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null | \ + mtd -r $append write - rootfs + else + echo "invalid image" + fi +} + +platform_check_image() { + local board=$(cns3xxx_board_name) + local magic="$(get_magic_word "$1")" + local magic_long="$(get_magic_long "$1")" + + [ "$#" -gt 1 ] && return 1 + + case "$board" in + laguna) + [ "$magic" != "4349" ] && { + echo "Invalid image. Use *-sysupgrade.bin files on this board" + return 1 + } + + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + + if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then + return 0 + else + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + return 0 + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_do_upgrade() { + local board=$(cns3xxx_board_name) + + v "board=$board" + case "$board" in + laguna) + platform_do_upgrade_combined "$ARGV" + ;; + *) + default_do_upgrade "$ARGV" + ;; + esac +} + +disable_watchdog() { + v "killing watchdog" + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +# CONFIG_WATCHDOG_NOWAYOUT=y - can't kill watchdog unless kernel cmdline has a mpcore_wdt.nowayout=0 +#append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/cns3xxx/config-3.18 b/target/linux/cns3xxx/config-3.18 new file mode 100644 index 0000000..6614b38 --- /dev/null +++ b/target/linux/cns3xxx/config-3.18 @@ -0,0 +1,286 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_CNS3XXX=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +# CONFIG_ARCH_WM8750 is not set +CONFIG_ARM=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ATA=y +CONFIG_ATAGS=y +# CONFIG_ATA_SFF is not set +CONFIG_ATA_VERBOSE_ERROR=y +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +CONFIG_AUTO_ZRELADDR=y +CONFIG_BLK_DEV_SD=y +CONFIG_BROADCOM_PHY=y +CONFIG_CACHE_L2X0=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CNS3XXX_ETH=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_PXA is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_ABRT_EV6=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_V6K=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_UART_BCM63XX is not set +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DMA_CACHE_FIQ_BROADCAST=y +CONFIG_DTC=y +CONFIG_EEPROM_AT24=y +CONFIG_FIQ=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HWMON=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_CNS3XXX=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INTEL_SOC_PMIC is not set +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_TRIGGER_NETDEV is not set +CONFIG_LIBFDT=y +# CONFIG_MACH_CNS3420VB is not set +CONFIG_MACH_GW2388=y +CONFIG_MDIO_BOARDINFO=y +# CONFIG_MFD_AXP20X is not set +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_CNS3XXX=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_OF_PARTS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_NR_CPUS=2 +CONFIG_NTP_PPS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +# CONFIG_PHY_SAMSUNG_USB2 is not set +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_753970=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_PPS=y +CONFIG_PPS_CLIENT_GPIO=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_PROC_STRIPPED is not set +CONFIG_RAID_ATTRS=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1672=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SCHED_HRTICK=y +CONFIG_SCSI=y +CONFIG_SENSORS_AD7418=y +CONFIG_SENSORS_GSC=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SERIAL_EARLYCON=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_CNS3XXX=y +CONFIG_SPI_MASTER=y +# CONFIG_STAGING is not set +CONFIG_STOP_MACHINE=y +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_CNS3XXX_EHCI=y +CONFIG_USB_CNS3XXX_OHCI=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC2=y +# CONFIG_USB_DWC2_DEBUG is not set +CONFIG_USB_DWC2_HOST=y +# CONFIG_USB_DWC2_PCI is not set +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_PLATFORM=y +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_ETH is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_XILINX is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S new file mode 100644 index 0000000..b1155ef --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/cns3xxx_fiq.S @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2012 Gateworks Corporation + * Chris Lang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include + +#define D_CACHE_LINE_SIZE 32 + + .text + +/* + * R8 - DMA Start Address + * R9 - DMA Length + * R10 - DMA Direction + * R11 - DMA type + * R12 - fiq_buffer Address +*/ + + .global cns3xxx_fiq_end +ENTRY(cns3xxx_fiq_start) + str r8, [r13] + + ldmia r12, {r8, r9, r10} + and r11, r10, #0x3000000 + and r10, r10, #0xff + + teq r11, #0x1000000 + beq cns3xxx_dma_map_area + teq r11, #0x2000000 + beq cns3xxx_dma_unmap_area + /* fall through */ +cns3xxx_dma_flush_range: + bic r8, r8, #D_CACHE_LINE_SIZE - 1 +1: + mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line + add r8, r8, #D_CACHE_LINE_SIZE + cmp r8, r9 + blo 1b + /* fall through */ +cns3xxx_fiq_exit: + mov r8, #0 + str r8, [r12, #8] + mcr p15, 0, r8, c7, c10, 4 @ drain write buffer + subs pc, lr, #4 + +cns3xxx_dma_map_area: + add r9, r9, r8 + teq r10, #DMA_FROM_DEVICE + beq cns3xxx_dma_inv_range + teq r10, #DMA_TO_DEVICE + bne cns3xxx_dma_flush_range + /* fall through */ +cns3xxx_dma_clean_range: + bic r8, r8, #D_CACHE_LINE_SIZE - 1 +1: + mcr p15, 0, r8, c7, c10, 1 @ clean D line + add r8, r8, #D_CACHE_LINE_SIZE + cmp r8, r9 + blo 1b + b cns3xxx_fiq_exit + +cns3xxx_dma_unmap_area: + add r9, r9, r8 + teq r10, #DMA_TO_DEVICE + beq cns3xxx_fiq_exit + /* fall through */ +cns3xxx_dma_inv_range: + tst r8, #D_CACHE_LINE_SIZE - 1 + bic r8, r8, #D_CACHE_LINE_SIZE - 1 + mcrne p15, 0, r8, c7, c10, 1 @ clean D line + tst r9, #D_CACHE_LINE_SIZE - 1 + bic r9, r9, #D_CACHE_LINE_SIZE - 1 + mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line +1: + mcr p15, 0, r8, c7, c6, 1 @ invalidate D line + add r8, r8, #D_CACHE_LINE_SIZE + cmp r8, r9 + blo 1b + b cns3xxx_fiq_exit + +cns3xxx_fiq_end: diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c new file mode 100644 index 0000000..b6e4061 --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c @@ -0,0 +1,292 @@ +/* + * Copyright 2012 Gateworks Corporation + * Chris Lang + * Tim Harvey + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Registers + */ +#define GPIO_INPUT 0x04 +#define GPIO_DIR 0x08 +#define GPIO_SET 0x10 +#define GPIO_CLEAR 0x14 +#define GPIO_INTERRUPT_ENABLE 0x20 +#define GPIO_INTERRUPT_RAW_STATUS 0x24 +#define GPIO_INTERRUPT_MASKED_STATUS 0x28 +#define GPIO_INTERRUPT_MASK 0x2C +#define GPIO_INTERRUPT_CLEAR 0x30 +#define GPIO_INTERRUPT_TRIGGER_METHOD 0x34 +#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES 0x38 +#define GPIO_INTERRUPT_TRIGGER_TYPE 0x3C + +#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE 0 +#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1 +#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE 0 +#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH 1 +#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING 0 +#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1 +#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH 0 +#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW 1 + +struct cns3xxx_gpio_chip { + struct gpio_chip chip; + struct irq_domain *domain; + spinlock_t lock; + void __iomem *base; +}; + +static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2]; +static int cns3xxx_gpio_chip_count; + +static inline void +__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input) +{ + u32 reg; + + reg = __raw_readl(cchip->base + GPIO_DIR); + if (input) + reg &= ~(1 << pin); + else + reg |= (1 << pin); + __raw_writel(reg, cchip->base + GPIO_DIR); +} + +/* + * GENERIC_GPIO primatives + */ +static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin) +{ + struct cns3xxx_gpio_chip *cchip = + container_of(chip, struct cns3xxx_gpio_chip, chip); + unsigned long flags; + + spin_lock_irqsave(&cchip->lock, flags); + __set_direction(cchip, pin, 1); + spin_unlock_irqrestore(&cchip->lock, flags); + + return 0; +} + +static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin) +{ + struct cns3xxx_gpio_chip *cchip = + container_of(chip, struct cns3xxx_gpio_chip, chip); + int val; + + val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1); + + return val; +} + +static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level) +{ + struct cns3xxx_gpio_chip *cchip = + container_of(chip, struct cns3xxx_gpio_chip, chip); + unsigned long flags; + + spin_lock_irqsave(&cchip->lock, flags); + if (level) + __raw_writel(1 << pin, cchip->base + GPIO_SET); + else + __raw_writel(1 << pin, cchip->base + GPIO_CLEAR); + __set_direction(cchip, pin, 0); + spin_unlock_irqrestore(&cchip->lock, flags); + + return 0; +} + +static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin, + int level) +{ + struct cns3xxx_gpio_chip *cchip = + container_of(chip, struct cns3xxx_gpio_chip, chip); + + if (level) + __raw_writel(1 << pin, cchip->base + GPIO_SET); + else + __raw_writel(1 << pin, cchip->base + GPIO_CLEAR); +} + +static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin) +{ + struct cns3xxx_gpio_chip *cchip = + container_of(chip, struct cns3xxx_gpio_chip, chip); + + return irq_find_mapping(cchip->domain, pin); +} + + +/* + * IRQ support + */ + +/* one interrupt per GPIO controller (GPIOA/GPIOB) + * this is called in task context, with IRQs enabled + */ +static void cns3xxx_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct cns3xxx_gpio_chip *cchip = irq_get_handler_data(irq); + struct irq_chip *chip = irq_get_chip(irq); + u16 i; + u32 reg; + + chained_irq_enter(chip, desc); /* mask and ack the base interrupt */ + + /* see which pin(s) triggered the interrupt */ + reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS); + for (i = 0; i < 32; i++) { + if (reg & (1 << i)) { + /* let the generic IRQ layer handle an interrupt */ + generic_handle_irq(irq_find_mapping(cchip->domain, i)); + } + } + + chained_irq_exit(chip, desc); /* unmask the base interrupt */ +} + +static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + struct cns3xxx_gpio_chip *cchip = gc->private; + u32 gpio = d->hwirq; + unsigned long flags; + u32 method, edges, type; + + spin_lock_irqsave(&cchip->lock, flags); + method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD); + edges = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES); + type = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE); + method &= ~(1 << gpio); + edges &= ~(1 << gpio); + type &= ~(1 << gpio); + + switch(irqtype) { + case IRQ_TYPE_EDGE_RISING: + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio); + edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio); + type |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio); + break; + case IRQ_TYPE_EDGE_FALLING: + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio); + edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio); + type |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio); + break; + case IRQ_TYPE_EDGE_BOTH: + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio); + edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio); + break; + case IRQ_TYPE_LEVEL_LOW: + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio); + type |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio); + break; + case IRQ_TYPE_LEVEL_HIGH: + method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio); + type |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio); + break; + default: + printk(KERN_WARNING "No irq type\n"); + spin_unlock_irqrestore(&cchip->lock, flags); + return -EINVAL; + } + + __raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD); + __raw_writel(edges, cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES); + __raw_writel(type, cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE); + spin_unlock_irqrestore(&cchip->lock, flags); + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + __irq_set_handler_locked(d->irq, handle_level_irq); + else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + __irq_set_handler_locked(d->irq, handle_edge_irq); + + return 0; +} + +void __init cns3xxx_gpio_init(int gpio_base, int ngpio, + u32 base, int irq, int secondary_irq_base) +{ + struct cns3xxx_gpio_chip *cchip; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + char gc_label[16]; + int irq_base; + + if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips)) + return; + + snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d", + cns3xxx_gpio_chip_count); + + cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count; + cchip->chip.label = kstrdup(gc_label, GFP_KERNEL); + cchip->chip.direction_input = cns3xxx_gpio_direction_input; + cchip->chip.get = cns3xxx_gpio_get; + cchip->chip.direction_output = cns3xxx_gpio_direction_output; + cchip->chip.set = cns3xxx_gpio_set; + cchip->chip.to_irq = cns3xxx_gpio_to_irq; + cchip->chip.base = gpio_base; + cchip->chip.ngpio = ngpio; + cchip->chip.can_sleep = 0; + spin_lock_init(&cchip->lock); + cchip->base = (void __iomem *)base; + + BUG_ON(gpiochip_add(&cchip->chip) < 0); + cns3xxx_gpio_chip_count++; + + /* clear GPIO interrupts */ + __raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR); + + irq_base = irq_alloc_descs(-1, secondary_irq_base, ngpio, + numa_node_id()); + if (irq_base < 0) + goto out_irqdesc_free; + + cchip->domain = irq_domain_add_legacy(NULL, ngpio, irq_base, 0, + &irq_domain_simple_ops, NULL); + if (!cchip->domain) + goto out_irqdesc_free; + + /* + * IRQ chip init + */ + gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, irq_base, + cchip->base, handle_edge_irq); + + gc->private = cchip; + + ct = gc->chip_types; + ct->type = IRQ_TYPE_EDGE_FALLING; + ct->regs.ack = GPIO_INTERRUPT_CLEAR; + ct->regs.enable = GPIO_INTERRUPT_ENABLE; + ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_enable = irq_gc_unmask_enable_reg; + ct->chip.irq_disable = irq_gc_mask_disable_reg; + ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type; + ct->handler = handle_edge_irq; + + irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST, 0); + irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler); + irq_set_handler_data(irq, cchip); + + return; + +out_irqdesc_free: + irq_free_descs(irq_base, ngpio); +} diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S new file mode 100644 index 0000000..3b46bdc --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S @@ -0,0 +1,42 @@ +/* + * linux/arch/arm/mach-cns3xxx/headsmp.S + * + * Cloned from linux/arch/arm/plat-versatile/headsmp.S + * + * Copyright (c) 2003 ARM Limited + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include + + __CPUINIT + +/* + * CNS3XXX specific entry point for secondary CPUs. This provides + * a "holding pen" into which all secondary cores are held until we're + * ready for them to initialise. + */ +ENTRY(cns3xxx_secondary_startup) + mrc p15, 0, r0, c0, c0, 5 + and r0, r0, #15 + adr r4, 1f + ldmia r4, {r5, r6} + sub r4, r4, r5 + add r6, r6, r4 +pen: ldr r7, [r6] + cmp r7, r0 + bne pen + + /* + * we've been released from the holding pen: secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup + + .align +1: .long . + .long pen_release diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c new file mode 100644 index 0000000..be0d499 --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/hotplug.c @@ -0,0 +1,130 @@ +/* linux arch/arm/mach-cns3xxx/hotplug.c + * + * Cloned from linux/arch/arm/mach-realview/hotplug.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include + +#include + +extern volatile int pen_release; + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + asm volatile( + " mcr p15, 0, %1, c7, c5, 0\n" + " mcr p15, 0, %1, c7, c10, 4\n" + /* + * Turn off coherency + */ + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, %3\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0), "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + +static inline void platform_do_lowpower(unsigned int cpu, int *spurious) +{ + /* + * there is no power-control hardware on this platform, so all + * we can do is put the core into WFI; this is safe as the calling + * code will have already disabled interrupts + */ + for (;;) { + /* + * here's the WFI + */ + asm(".word 0xe320f003\n" + : + : + : "memory", "cc"); + + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + + /* + * Getting here, means that we have come out of WFI without + * having been woken up - this shouldn't happen + * + * Just note it happening - when we're woken, we can report + * its occurrence. + */ + (*spurious)++; + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return 1; +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ + int spurious = 0; + + /* + * we're ready for shutdown now, so do it + */ + cpu_enter_lowpower(); + platform_do_lowpower(cpu, &spurious); + + /* + * bring this CPU back into the world of cache + * coherency, and then restore interrupts + */ + cpu_leave_lowpower(); + + if (spurious) + pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h new file mode 100644 index 0000000..8c66748 --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/gpio.h @@ -0,0 +1,17 @@ +/* + * arch/arm/mach-cns3xxx/include/mach/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + */ +#ifndef __ASM_ARCH_CNS3XXX_GPIO_H +#define __ASM_ARCH_CNS3XXX_GPIO_H + +#include + +extern void __init cns3xxx_gpio_init(int gpio_base, int ngpio, + u32 base, int irq, int secondary_irq_base); + +#endif diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h new file mode 100644 index 0000000..e5bc568 --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/include/mach/smp.h @@ -0,0 +1,8 @@ +#ifndef __MACH_SMP_H +#define __MACH_SMP_H + +extern void smp_dma_map_area(const void *, size_t, int); +extern void smp_dma_unmap_area(const void *, size_t, int); +extern void smp_dma_flush_range(const void *, const void *); + +#endif diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c new file mode 100644 index 0000000..99c4108 --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/laguna.c @@ -0,0 +1,1079 @@ +/* + * Gateworks Corporation Laguna Platform + * + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2008 ARM Limited + * Copyright 2008 Cavium Networks + * Scott Shu + * Copyright 2010 MontaVista Software, LLC. + * Anton Vorontsov + * Copyright 2011 Gateworks Corporation + * Chris Lang + * Copyright 2012-2013 Gateworks Corporation + * Tim Harvey + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" +#include "devices.h" +#include "cns3xxx.h" +#include "pm.h" + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + +// Config 1 Bitmap +#define ETH0_LOAD BIT(0) +#define ETH1_LOAD BIT(1) +#define ETH2_LOAD BIT(2) +#define SATA0_LOAD BIT(3) +#define SATA1_LOAD BIT(4) +#define PCM_LOAD BIT(5) +#define I2S_LOAD BIT(6) +#define SPI0_LOAD BIT(7) +#define SPI1_LOAD BIT(8) +#define PCIE0_LOAD BIT(9) +#define PCIE1_LOAD BIT(10) +#define USB0_LOAD BIT(11) +#define USB1_LOAD BIT(12) +#define USB1_ROUTE BIT(13) +#define SD_LOAD BIT(14) +#define UART0_LOAD BIT(15) +#define UART1_LOAD BIT(16) +#define UART2_LOAD BIT(17) +#define MPCI0_LOAD BIT(18) +#define MPCI1_LOAD BIT(19) +#define MPCI2_LOAD BIT(20) +#define MPCI3_LOAD BIT(21) +#define FP_BUT_LOAD BIT(22) +#define FP_BUT_HEADER_LOAD BIT(23) +#define FP_LED_LOAD BIT(24) +#define FP_LED_HEADER_LOAD BIT(25) +#define FP_TAMPER_LOAD BIT(26) +#define HEADER_33V_LOAD BIT(27) +#define SATA_POWER_LOAD BIT(28) +#define FP_POWER_LOAD BIT(29) +#define GPIO_HEADER_LOAD BIT(30) +#define GSP_BAT_LOAD BIT(31) + +// Config 2 Bitmap +#define FAN_LOAD BIT(0) +#define SPI_FLASH_LOAD BIT(1) +#define NOR_FLASH_LOAD BIT(2) +#define GPS_LOAD BIT(3) +#define SUPPLY_5V_LOAD BIT(6) +#define SUPPLY_33V_LOAD BIT(7) + +struct laguna_board_info { + char model[16]; + u32 config_bitmap; + u32 config2_bitmap; + u8 nor_flash_size; + u8 spi_flash_size; +}; + +static struct laguna_board_info laguna_info __initdata; + +/* + * NOR Flash + */ +static struct mtd_partition laguna_nor_partitions[] = { + { + .name = "uboot", + .size = SZ_256K, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "params", + .size = SZ_128K, + .offset = SZ_256K, + }, { + .name = "kernel", + .size = SZ_2M, + .offset = SZ_256K + SZ_128K, + }, { + .name = "rootfs", + .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M, + .offset = SZ_256K + SZ_128K + SZ_2M, + }, +}; + +static struct physmap_flash_data laguna_nor_pdata = { + .width = 2, + .parts = laguna_nor_partitions, + .nr_parts = ARRAY_SIZE(laguna_nor_partitions), +}; + +static struct resource laguna_nor_res = { + .start = CNS3XXX_FLASH_BASE, + .end = CNS3XXX_FLASH_BASE + SZ_128M - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, +}; + +static struct platform_device laguna_nor_pdev = { + .name = "physmap-flash", + .id = 0, + .resource = &laguna_nor_res, + .num_resources = 1, + .dev = { + .platform_data = &laguna_nor_pdata, + }, +}; + +/* + * SPI + */ +static struct mtd_partition laguna_spi_partitions[] = { + { + .name = "uboot", + .size = SZ_256K, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "params", + .size = SZ_256K, + .offset = SZ_256K, + }, { + .name = "kernel", + .size = SZ_1M + SZ_512K, + .offset = SZ_512K, + }, { + .name = "rootfs", + .size = SZ_16M - SZ_2M, + .offset = SZ_2M, + }, +}; + +static struct flash_platform_data laguna_spi_pdata = { + .parts = laguna_spi_partitions, + .nr_parts = ARRAY_SIZE(laguna_spi_partitions), +}; + +static struct spi_board_info __initdata laguna_spi_devices[] = { + { + .modalias = "m25p80", + .platform_data = &laguna_spi_pdata, + .max_speed_hz = 50000000, + .bus_num = 1, + .chip_select = 0, + }, +}; + +static struct resource laguna_spi_resource = { + .start = CNS3XXX_SSP_BASE + 0x40, + .end = CNS3XXX_SSP_BASE + 0x6f, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device laguna_spi_controller = { + .name = "cns3xxx_spi", + .resource = &laguna_spi_resource, + .num_resources = 1, +}; + +/* + * LED's + */ +static struct gpio_led laguna_gpio_leds[] = { + { + .name = "user1", /* Green Led */ + .gpio = 115, + .active_low = 1, + },{ + .name = "user2", /* Red Led */ + .gpio = 114, + .active_low = 1, + },{ + .name = "pwr1", /* Green Led */ + .gpio = 116, + .active_low = 1, + },{ + .name = "pwr2", /* Yellow Led */ + .gpio = 117, + .active_low = 1, + },{ + .name = "txd1", /* Green Led */ + .gpio = 118, + .active_low = 1, + },{ + .name = "txd2", /* Yellow Led */ + .gpio = 119, + .active_low = 1, + },{ + .name = "rxd1", /* Green Led */ + .gpio = 120, + .active_low = 1, + },{ + .name = "rxd2", /* Yellow Led */ + .gpio = 121, + .active_low = 1, + },{ + .name = "ser1", /* Green Led */ + .gpio = 122, + .active_low = 1, + },{ + .name = "ser2", /* Yellow Led */ + .gpio = 123, + .active_low = 1, + },{ + .name = "enet1", /* Green Led */ + .gpio = 124, + .active_low = 1, + },{ + .name = "enet2", /* Yellow Led */ + .gpio = 125, + .active_low = 1, + },{ + .name = "sig1_1", /* Green Led */ + .gpio = 126, + .active_low = 1, + },{ + .name = "sig1_2", /* Yellow Led */ + .gpio = 127, + .active_low = 1, + },{ + .name = "sig2_1", /* Green Led */ + .gpio = 128, + .active_low = 1, + },{ + .name = "sig2_2", /* Yellow Led */ + .gpio = 129, + .active_low = 1, + },{ + .name = "sig3_1", /* Green Led */ + .gpio = 130, + .active_low = 1, + },{ + .name = "sig3_2", /* Yellow Led */ + .gpio = 131, + .active_low = 1, + },{ + .name = "net1", /*Green Led */ + .gpio = 109, + .active_low = 1, + },{ + .name = "net2", /* Red Led */ + .gpio = 110, + .active_low = 1, + },{ + .name = "mod1", /* Green Led */ + .gpio = 111, + .active_low = 1, + },{ + .name = "mod2", /* Red Led */ + .gpio = 112, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data laguna_gpio_leds_data = { + .num_leds = 22, + .leds = laguna_gpio_leds, +}; + +static struct platform_device laguna_gpio_leds_device = { + .name = "leds-gpio", + .id = -1, + .dev.platform_data = &laguna_gpio_leds_data, +}; + +/* + * Ethernet + */ +static struct cns3xxx_plat_info laguna_net_data = { + .ports = 0, + .phy = { + 0, + 1, + 2, + }, +}; + +static struct resource laguna_net_resource[] = { + { + .name = "eth0_mem", + .start = CNS3XXX_SWITCH_BASE, + .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM + }, { + .name = "eth_rx", + .start = IRQ_CNS3XXX_SW_R0RXC, + .end = IRQ_CNS3XXX_SW_R0RXC, + .flags = IORESOURCE_IRQ + }, { + .name = "eth_stat", + .start = IRQ_CNS3XXX_SW_STATUS, + .end = IRQ_CNS3XXX_SW_STATUS, + .flags = IORESOURCE_IRQ + } +}; + +static u64 laguna_net_dmamask = DMA_BIT_MASK(32); +static struct platform_device laguna_net_device = { + .name = "cns3xxx_eth", + .id = 0, + .resource = laguna_net_resource, + .num_resources = ARRAY_SIZE(laguna_net_resource), + .dev = { + .dma_mask = &laguna_net_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &laguna_net_data, + } +}; + +/* + * UART + */ +static void __init laguna_early_serial_setup(void) +{ +#ifdef CONFIG_SERIAL_8250_CONSOLE + static struct uart_port laguna_serial_port = { + .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, + .mapbase = CNS3XXX_UART0_BASE, + .irq = IRQ_CNS3XXX_UART0, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, + .regshift = 2, + .uartclk = 24000000, + .line = 0, + .type = PORT_16550A, + .fifosize = 16, + }; + + early_serial_setup(&laguna_serial_port); +#endif +} + +static struct resource laguna_uart_resources[] = { + { + .start = CNS3XXX_UART0_BASE, + .end = CNS3XXX_UART0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM + },{ + .start = CNS3XXX_UART2_BASE, + .end = CNS3XXX_UART2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM + },{ + .start = CNS3XXX_UART2_BASE, + .end = CNS3XXX_UART2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM + }, +}; + +static struct plat_serial8250_port laguna_uart_data[] = { + { + .mapbase = (CNS3XXX_UART0_BASE), + .irq = IRQ_CNS3XXX_UART0, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP, + .regshift = 2, + .uartclk = 24000000, + .type = PORT_16550A, + },{ + .mapbase = (CNS3XXX_UART1_BASE), + .irq = IRQ_CNS3XXX_UART1, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP, + .regshift = 2, + .uartclk = 24000000, + .type = PORT_16550A, + },{ + .mapbase = (CNS3XXX_UART2_BASE), + .irq = IRQ_CNS3XXX_UART2, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST | UPF_IOREMAP, + .regshift = 2, + .uartclk = 24000000, + .type = PORT_16550A, + }, + { }, +}; + +static struct platform_device laguna_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = laguna_uart_data, + .num_resources = 3, + .resource = laguna_uart_resources +}; + +/* + * USB + */ +static struct resource cns3xxx_usb_ehci_resources[] = { + [0] = { + .start = CNS3XXX_USB_BASE, + .end = CNS3XXX_USB_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CNS3XXX_USB_EHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); + +static int csn3xxx_usb_power_on(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + * + * Set USB AHB INCR length to 16 + */ + if (atomic_inc_return(&usb_pwr_ref) == 1) { + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); + cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); + __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), + MISC_CHIP_CONFIG_REG); + } + + return 0; +} + +static void csn3xxx_usb_power_off(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + */ + if (atomic_dec_return(&usb_pwr_ref) == 0) + cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); +} + +static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct platform_device cns3xxx_usb_ehci_device = { + .name = "ehci-platform", + .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), + .resource = cns3xxx_usb_ehci_resources, + .dev = { + .dma_mask = &cns3xxx_usb_ehci_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &cns3xxx_usb_ehci_pdata, + }, +}; + +static struct resource cns3xxx_usb_ohci_resources[] = { + [0] = { + .start = CNS3XXX_USB_OHCI_BASE, + .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CNS3XXX_USB_OHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); + +static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { + .num_ports = 1, + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct platform_device cns3xxx_usb_ohci_device = { + .name = "ohci-platform", + .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), + .resource = cns3xxx_usb_ohci_resources, + .dev = { + .dma_mask = &cns3xxx_usb_ohci_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &cns3xxx_usb_ohci_pdata, + }, +}; + +static struct resource cns3xxx_usb_otg_resources[] = { + [0] = { + .start = CNS3XXX_USBOTG_BASE, + .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_CNS3XXX_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device cns3xxx_usb_otg_device = { + .name = "dwc2", + .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources), + .resource = cns3xxx_usb_otg_resources, + .dev = { + .dma_mask = &cns3xxx_usb_otg_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +/* + * I2C + */ +static struct resource laguna_i2c_resource[] = { + { + .start = CNS3XXX_SSP_BASE + 0x20, + .end = CNS3XXX_SSP_BASE + 0x3f, + .flags = IORESOURCE_MEM, + },{ + .start = IRQ_CNS3XXX_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device laguna_i2c_controller = { + .name = "cns3xxx-i2c", + .num_resources = 2, + .resource = laguna_i2c_resource, +}; + +static struct memory_accessor *at24_mem_acc; + +static void at24_setup(struct memory_accessor *mem_acc, void *context) +{ + char buf[16]; + + at24_mem_acc = mem_acc; + + /* Read MAC addresses */ + if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6) + memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN); + if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6) + memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN); + if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6) + memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN); + if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6) + memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN); + + /* Read out Model Information */ + if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16) + memcpy(&laguna_info.model, buf, 16); + if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1) + memcpy(&laguna_info.nor_flash_size, buf, 1); + if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1) + memcpy(&laguna_info.spi_flash_size, buf, 1); + if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4) + memcpy(&laguna_info.config_bitmap, buf, 4); + if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4) + memcpy(&laguna_info.config2_bitmap, buf, 4); +}; + +static struct at24_platform_data laguna_eeprom_info = { + .byte_len = 1024, + .page_size = 16, + .flags = AT24_FLAG_READONLY, + .setup = at24_setup, +}; + +static struct pca953x_platform_data laguna_pca_data = { + .gpio_base = 100, + .irq_base = -1, +}; + +static struct pca953x_platform_data laguna_pca2_data = { + .gpio_base = 116, + .irq_base = -1, +}; + +static struct i2c_board_info __initdata laguna_i2c_devices[] = { + { + I2C_BOARD_INFO("pca9555", 0x23), + .platform_data = &laguna_pca_data, + },{ + I2C_BOARD_INFO("pca9555", 0x27), + .platform_data = &laguna_pca2_data, + },{ + I2C_BOARD_INFO("gsp", 0x29), + },{ + I2C_BOARD_INFO ("24c08",0x50), + .platform_data = &laguna_eeprom_info, + },{ + I2C_BOARD_INFO("ds1672", 0x68), + }, +}; + +/* + * Watchdog + */ + +static struct resource laguna_watchdog_resources[] = { + [0] = { + .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog + .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device laguna_watchdog = { + .name = "mpcore_wdt", + .id = -1, + .num_resources = ARRAY_SIZE(laguna_watchdog_resources), + .resource = laguna_watchdog_resources, +}; + +/* + * GPS PPS + */ +static struct pps_gpio_platform_data laguna_pps_data = { + .gpio_pin = 0, + .gpio_label = "GPS_PPS", + .assert_falling_edge = 0, + .capture_clear = 0, +}; + +static struct platform_device laguna_pps_device = { + .name = "pps-gpio", + .id = -1, + .dev.platform_data = &laguna_pps_data, +}; + +/* + * GPIO + */ + +static struct gpio laguna_gpio_gw2391[] = { + { 0, GPIOF_IN , "*GPS_PPS" }, + { 1, GPIOF_IN , "*GSC_IRQ#" }, + { 2, GPIOF_IN , "*USB_FAULT#" }, + { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" }, + { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, + { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" }, + { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" }, + { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" }, + { 100, GPIOF_IN , "*USER_PB#" }, + { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" }, + { 108, GPIOF_IN , "DIO0" }, + { 109, GPIOF_IN , "DIO1" }, + { 110, GPIOF_IN , "DIO2" }, + { 111, GPIOF_IN , "DIO3" }, + { 112, GPIOF_IN , "DIO4" }, +}; + +static struct gpio laguna_gpio_gw2388[] = { + { 0, GPIOF_IN , "*GPS_PPS" }, + { 1, GPIOF_IN , "*GSC_IRQ#" }, + { 3, GPIOF_IN , "*USB_FAULT#" }, + { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, + { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, + { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, + { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, + { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" }, + { 108, GPIOF_IN , "DIO0" }, + { 109, GPIOF_IN , "DIO1" }, + { 110, GPIOF_IN , "DIO2" }, + { 111, GPIOF_IN , "DIO3" }, + { 112, GPIOF_IN , "DIO4" }, +}; + +static struct gpio laguna_gpio_gw2387[] = { + { 0, GPIOF_IN , "*GPS_PPS" }, + { 1, GPIOF_IN , "*GSC_IRQ#" }, + { 2, GPIOF_IN , "*USB_FAULT#" }, + { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" }, + { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, + { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, + { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, + { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, + { 100, GPIOF_IN , "*USER_PB#" }, + { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" }, + { 108, GPIOF_IN , "DIO0" }, + { 109, GPIOF_IN , "DIO1" }, + { 110, GPIOF_IN , "DIO2" }, + { 111, GPIOF_IN , "DIO3" }, + { 112, GPIOF_IN , "DIO4" }, + { 113, GPIOF_IN , "DIO5" }, +}; + +static struct gpio laguna_gpio_gw2385[] = { + { 0, GPIOF_IN , "*GSC_IRQ#" }, + { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" }, + { 2, GPIOF_IN , "*USB_HST_FAULT#" }, + { 5, GPIOF_IN , "*USB_OTG_FAULT#" }, + { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" }, + { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, + { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, + { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" }, + { 10, GPIOF_IN, "*USER_PB#" }, + { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" }, + { 100, GPIOF_IN , "*USER_PB#" }, + { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" }, +}; + +static struct gpio laguna_gpio_gw2384[] = { + { 0, GPIOF_IN , "*GSC_IRQ#" }, + { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" }, + { 2, GPIOF_IN , "*USB_HST_FAULT#" }, + { 5, GPIOF_IN , "*USB_OTG_FAULT#" }, + { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" }, + { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, + { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, + { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, + { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" }, + { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" }, + { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" }, + { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" }, + { 100, GPIOF_IN , "*USER_PB#" }, + { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" }, + { 108, GPIOF_IN , "J9_DIOGSC0" }, +}; + +static struct gpio laguna_gpio_gw2383[] = { + { 0, GPIOF_IN , "*GPS_PPS" }, + { 1, GPIOF_IN , "*GSC_IRQ#" }, + { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" }, + { 3, GPIOF_IN , "GPIO0" }, + { 8, GPIOF_IN , "GPIO1" }, + { 100, GPIOF_IN , "DIO0" }, + { 101, GPIOF_IN , "DIO1" }, + { 108, GPIOF_IN , "*USER_PB#" }, +}; + +static struct gpio laguna_gpio_gw2382[] = { + { 0, GPIOF_IN , "*GPS_PPS" }, + { 1, GPIOF_IN , "*GSC_IRQ#" }, + { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" }, + { 3, GPIOF_IN , "GPIO0" }, + { 4, GPIOF_IN , "GPIO1" }, + { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, + { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" }, + { 100, GPIOF_IN , "DIO0" }, + { 101, GPIOF_IN , "DIO1" }, + { 108, GPIOF_IN , "*USER_PB#" }, +}; + +static struct gpio laguna_gpio_gw2380[] = { + { 0, GPIOF_IN , "*GPS_PPS" }, + { 1, GPIOF_IN , "*GSC_IRQ#" }, + { 3, GPIOF_IN , "GPIO0" }, + { 8, GPIOF_IN , "GPIO1" }, + { 100, GPIOF_IN , "DIO0" }, + { 101, GPIOF_IN , "DIO1" }, + { 102, GPIOF_IN , "DIO2" }, + { 103, GPIOF_IN , "DIO3" }, + { 108, GPIOF_IN , "*USER_PB#" }, +}; + +/* + * Initialization + */ +static void __init laguna_init(void) +{ + struct clk *clk; + u32 __iomem *reg; + + clk = clk_register_fixed_rate(NULL, "cpu", NULL, + CLK_IS_ROOT | CLK_IGNORE_UNUSED, + cns3xxx_cpu_clock() * (1000000 / 8)); + clk_register_clkdev(clk, "cpu", NULL); + + platform_device_register(&laguna_watchdog); + + platform_device_register(&laguna_i2c_controller); + + /* Set ext_int 0-3 drive strength to 21 mA */ + reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B; + *reg |= 0x300; + + /* Enable SCL/SDA for I2C */ + reg = MISC_GPIOB_PIN_ENABLE_REG; + *reg |= BIT(12) | BIT(13); + + /* Enable MMC/SD pins */ + *reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11); + + cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); + cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); + cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C)); + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C)); + + i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices)); + + pm_power_off = cns3xxx_power_off; +} + +static struct map_desc laguna_io_desc[] __initdata = { + { + .virtual = CNS3XXX_UART0_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +static void __init laguna_map_io(void) +{ + cns3xxx_map_io(); + cns3xxx_pcie_iotable_init(); + iotable_init(ARRAY_AND_SIZE(laguna_io_desc)); + laguna_early_serial_setup(); +} + +static int laguna_register_gpio(struct gpio *array, size_t num) +{ + int i, err, ret; + + ret = 0; + for (i = 0; i < num; i++, array++) { + const char *label = array->label; + if (label[0] == '*') + label++; + err = gpio_request_one(array->gpio, array->flags, label); + if (err) + ret = err; + else { + err = gpio_export(array->gpio, array->label[0] != '*'); + } + } + return ret; +} + +static int __init laguna_pcie_init(void) +{ + if (!machine_is_gw2388()) + return 0; + + return cns3xxx_pcie_init(); +} +subsys_initcall(laguna_pcie_init); + +static int __init laguna_model_setup(void) +{ + u32 __iomem *mem; + u32 reg; + + if (!machine_is_gw2388()) + return 0; + + printk("Running on Gateworks Laguna %s\n", laguna_info.model); + cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, + NR_IRQS_CNS3XXX); + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, + NR_IRQS_CNS3XXX + 32); + + if (strncmp(laguna_info.model, "GW", 2) == 0) { + if (laguna_info.config_bitmap & ETH0_LOAD) + laguna_net_data.ports |= BIT(0); + if (laguna_info.config_bitmap & ETH1_LOAD) + laguna_net_data.ports |= BIT(1); + if (laguna_info.config_bitmap & ETH2_LOAD) + laguna_net_data.ports |= BIT(2); + if (laguna_net_data.ports) + platform_device_register(&laguna_net_device); + + if ((laguna_info.config_bitmap & SATA0_LOAD) || + (laguna_info.config_bitmap & SATA1_LOAD)) + cns3xxx_ahci_init(); + + if (laguna_info.config_bitmap & (USB0_LOAD)) { + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); + + /* DRVVBUS pins share with GPIOA */ + mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014); + reg = __raw_readl(mem); + reg |= 0x8; + __raw_writel(reg, mem); + + /* Enable OTG */ + mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808); + reg = __raw_readl(mem); + reg &= ~(1 << 10); + __raw_writel(reg, mem); + + platform_device_register(&cns3xxx_usb_otg_device); + } + + if (laguna_info.config_bitmap & (USB1_LOAD)) { + platform_device_register(&cns3xxx_usb_ehci_device); + platform_device_register(&cns3xxx_usb_ohci_device); + } + + if (laguna_info.config_bitmap & (SD_LOAD)) + cns3xxx_sdhci_init(); + + if (laguna_info.config_bitmap & (UART0_LOAD)) + laguna_uart.num_resources = 1; + if (laguna_info.config_bitmap & (UART1_LOAD)) + laguna_uart.num_resources = 2; + if (laguna_info.config_bitmap & (UART2_LOAD)) + laguna_uart.num_resources = 3; + platform_device_register(&laguna_uart); + + if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) { + switch (laguna_info.nor_flash_size) { + case 1: + laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M; + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1; + break; + case 2: + laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M; + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1; + break; + case 3: + laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M; + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1; + break; + case 4: + laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M; + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1; + break; + case 5: + laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M; + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1; + break; + } + platform_device_register(&laguna_nor_pdev); + } + + if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) { + switch (laguna_info.spi_flash_size) { + case 1: + laguna_spi_partitions[3].size = SZ_4M - SZ_2M; + break; + case 2: + laguna_spi_partitions[3].size = SZ_8M - SZ_2M; + break; + case 3: + laguna_spi_partitions[3].size = SZ_16M - SZ_2M; + break; + case 4: + laguna_spi_partitions[3].size = SZ_32M - SZ_2M; + break; + case 5: + laguna_spi_partitions[3].size = SZ_64M - SZ_2M; + break; + } + spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices)); + } + + if ((laguna_info.config_bitmap & SPI0_LOAD) || + (laguna_info.config_bitmap & SPI1_LOAD)) + platform_device_register(&laguna_spi_controller); + + if (laguna_info.config2_bitmap & GPS_LOAD) + platform_device_register(&laguna_pps_device); + + /* + * Do any model specific setup not known by the bitmap by matching + * the first 6 characters of the model name + */ + + if ( (strncmp(laguna_info.model, "GW2388", 6) == 0) + || (strncmp(laguna_info.model, "GW2389", 6) == 0) ) + { + // configure GPIO's + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388)); + // configure LED's + laguna_gpio_leds_data.num_leds = 2; + } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) { + // configure GPIO's + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387)); + // configure LED's + laguna_gpio_leds_data.num_leds = 2; + } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) { + // configure GPIO's + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385)); + // configure LED's + laguna_gpio_leds[0].gpio = 115; + laguna_gpio_leds[1].gpio = 12; + laguna_gpio_leds[1].name = "red"; + laguna_gpio_leds[1].active_low = 0, + laguna_gpio_leds[2].gpio = 14; + laguna_gpio_leds[2].name = "green"; + laguna_gpio_leds[2].active_low = 0, + laguna_gpio_leds[3].gpio = 15; + laguna_gpio_leds[3].name = "blue"; + laguna_gpio_leds[3].active_low = 0, + laguna_gpio_leds_data.num_leds = 4; + } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) { + // configure GPIO's + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384)); + // configure LED's + laguna_gpio_leds_data.num_leds = 1; + } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) { + // configure GPIO's + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383)); + // configure LED's + laguna_gpio_leds[0].gpio = 107; + laguna_gpio_leds_data.num_leds = 1; + } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) { + // configure GPIO's + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382)); + // configure LED's + laguna_gpio_leds[0].gpio = 107; + laguna_gpio_leds_data.num_leds = 1; + } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) { + // configure GPIO's + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380)); + // configure LED's + laguna_gpio_leds[0].gpio = 107; + laguna_gpio_leds[1].gpio = 106; + laguna_gpio_leds_data.num_leds = 2; + } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) { + // configure GPIO's + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391)); + // configure LED's + laguna_gpio_leds_data.num_leds = 2; + } + platform_device_register(&laguna_gpio_leds_device); + } else { + // Do some defaults here, not sure what yet + } + return 0; +} +late_initcall(laguna_model_setup); + +MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform") + .smp = smp_ops(cns3xxx_smp_ops), + .atag_offset = 0x100, + .map_io = laguna_map_io, + .init_irq = cns3xxx_init_irq, + .init_time = cns3xxx_timer_init, + .init_machine = laguna_init, + .restart = cns3xxx_restart, +MACHINE_END diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/localtimer.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/localtimer.c new file mode 100644 index 0000000..5e1111c --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/localtimer.c @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-cns3xxx/localtimer.c + * + * Cloned from linux/arch/arm/mach-realview/localtimer.c + * + * Copyright (C) 2002 ARM Ltd. + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + +#include +#include + +/* + * Setup the local clock events for a CPU. + */ +int __cpuinit local_timer_setup(struct clock_event_device *evt) +{ + evt->irq = IRQ_LOCALTIMER; + twd_timer_setup(evt); + return 0; +} diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c new file mode 100644 index 0000000..5359885 --- /dev/null +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c @@ -0,0 +1,337 @@ +/* + * linux/arch/arm/mach-cns3xxx/platsmp.c + * + * Copyright (C) 2002 ARM Ltd. + * Copyright 2012 Gateworks Corporation + * Chris Lang + * Tim Harvey + * + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include "cns3xxx.h" + +static struct fiq_handler fh = { + .name = "cns3xxx-fiq" +}; + +struct fiq_req { + union { + struct { + const void *addr; + size_t size; + } map; + struct { + const void *addr; + size_t size; + } unmap; + struct { + const void *start; + const void *end; + } flush; + }; + volatile uint flags; + void __iomem *reg; +} ____cacheline_aligned; + +extern unsigned int fiq_number[2]; + +DEFINE_PER_CPU(struct fiq_req, fiq_data); + +#define FIQ_ENABLED 0x80000000 +#define FIQ_GENERATE 0x00010000 +#define CNS3XXX_MAP_AREA 0x01000000 +#define CNS3XXX_UNMAP_AREA 0x02000000 +#define CNS3XXX_FLUSH_RANGE 0x03000000 + +extern void cns3xxx_secondary_startup(void); +extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end; + +#define SCU_CPU_STATUS 0x08 +static void __iomem *scu_base; + +static inline void __cpuinit cns3xxx_set_fiq_regs(unsigned int cpu) +{ + struct pt_regs FIQ_regs; + struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu); + + FIQ_regs.ARM_r8 = 0; + FIQ_regs.ARM_ip = (unsigned int)fiq_req; + FIQ_regs.ARM_sp = (int) MISC_FIQ_CPU(!cpu); + fiq_req->reg = MISC_FIQ_CPU(!cpu); + + set_fiq_regs(&FIQ_regs); +} + +static void __init cns3xxx_init_fiq(void) +{ + void *fiqhandler_start; + unsigned int fiqhandler_length; + int ret; + + fiqhandler_start = &cns3xxx_fiq_start; + fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start; + + ret = claim_fiq(&fh); + if (ret) + return; + + set_fiq_handler(fiqhandler_start, fiqhandler_length); +} + + +/* + * Write pen_release in a way that is guaranteed to be visible to all + * observers, irrespective of whether they're taking part in coherency + * or not. This is necessary for the hotplug code to work reliably. + */ +static void __cpuinit write_pen_release(int val) +{ + pen_release = val; + smp_wmb(); + __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); + outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); +} + +static DEFINE_SPINLOCK(boot_lock); + +static void __cpuinit cns3xxx_secondary_init(unsigned int cpu) +{ + /* + * Setup Secondary Core FIQ regs + */ + cns3xxx_set_fiq_regs(1); + + /* + * let the primary processor know we're out of the + * pen, then head off into the C entry point + */ + write_pen_release(-1); + + /* + * Synchronise with the boot thread. + */ + spin_lock(&boot_lock); + spin_unlock(&boot_lock); +} + +static int __cpuinit cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + unsigned long timeout; + + /* + * Set synchronisation state between this boot processor + * and the secondary one + */ + spin_lock(&boot_lock); + + /* + * The secondary processor is waiting to be released from + * the holding pen - release it, then wait for it to flag + * that it has been released by resetting pen_release. + * + * Note that "pen_release" is the hardware CPU ID, whereas + * "cpu" is Linux's internal ID. + */ + write_pen_release(cpu); + + /* + * Send the secondary CPU a soft interrupt, thereby causing + * the boot monitor to read the system wide flags register, + * and branch to the address found there. + */ + arch_send_wakeup_ipi_mask(cpumask_of(cpu));; + + timeout = jiffies + (1 * HZ); + while (time_before(jiffies, timeout)) { + smp_rmb(); + if (pen_release == -1) + break; + + udelay(10); + } + + /* + * now the secondary core is starting up let it run its + * calibrations, then wait for it to finish + */ + spin_unlock(&boot_lock); + + return pen_release != -1 ? -ENOSYS : 0; +} + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +static void __init cns3xxx_smp_init_cpus(void) +{ + unsigned int i, ncores; + unsigned int status; + + scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT; + + /* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION + * used in scu_get_core_count + */ + status = __raw_readl(scu_base + SCU_CPU_STATUS); + for (i = 0; i < NR_CPUS+1; i++) { + if (((status >> (i*2)) & 0x3) == 0) + set_cpu_possible(i, true); + else + break; + } + ncores = i; +} + +static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus) +{ + int i; + + /* + * Initialise the present map, which describes the set of CPUs + * actually populated at the present time. + */ + for (i = 0; i < max_cpus; i++) { + set_cpu_present(i, true); + } + + /* + * enable SCU + */ + scu_enable(scu_base); + + /* + * Write the address of secondary startup into the + * system-wide flags register. The boot monitor waits + * until it receives a soft interrupt, and then the + * secondary CPU branches to this address. + */ + __raw_writel(virt_to_phys(cns3xxx_secondary_startup), + (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600)); + + /* + * Setup FIQ's for main cpu + */ + cns3xxx_init_fiq(); + cns3xxx_set_fiq_regs(0); +} + +extern void v6_dma_map_area(const void *, size_t, int); +extern void v6_dma_unmap_area(const void *, size_t, int); +extern void v6_dma_flush_range(const void *, const void *); +extern void v6_flush_kern_dcache_area(void *, size_t); + +void fiq_dma_map_area(const void *addr, size_t size, int dir) +{ + unsigned long flags; + struct fiq_req *req; + + raw_local_irq_save(flags); + /* currently, not possible to take cpu0 down, so only check cpu1 */ + if (!cpu_online(1)) { + raw_local_irq_restore(flags); + v6_dma_map_area(addr, size, dir); + return; + } + + req = this_cpu_ptr(&fiq_data); + req->map.addr = addr; + req->map.size = size; + req->flags = dir | CNS3XXX_MAP_AREA; + smp_mb(); + + writel_relaxed(FIQ_GENERATE, req->reg); + + v6_dma_map_area(addr, size, dir); + while (req->flags) + barrier(); + + raw_local_irq_restore(flags); +} + +void fiq_dma_unmap_area(const void *addr, size_t size, int dir) +{ + unsigned long flags; + struct fiq_req *req; + + raw_local_irq_save(flags); + /* currently, not possible to take cpu0 down, so only check cpu1 */ + if (!cpu_online(1)) { + raw_local_irq_restore(flags); + v6_dma_unmap_area(addr, size, dir); + return; + } + + req = this_cpu_ptr(&fiq_data); + req->unmap.addr = addr; + req->unmap.size = size; + req->flags = dir | CNS3XXX_UNMAP_AREA; + smp_mb(); + + writel_relaxed(FIQ_GENERATE, req->reg); + + v6_dma_unmap_area(addr, size, dir); + while (req->flags) + barrier(); + + raw_local_irq_restore(flags); +} + +void fiq_dma_flush_range(const void *start, const void *end) +{ + unsigned long flags; + struct fiq_req *req; + + raw_local_irq_save(flags); + /* currently, not possible to take cpu0 down, so only check cpu1 */ + if (!cpu_online(1)) { + raw_local_irq_restore(flags); + v6_dma_flush_range(start, end); + return; + } + + req = this_cpu_ptr(&fiq_data); + + req->flush.start = start; + req->flush.end = end; + req->flags = CNS3XXX_FLUSH_RANGE; + smp_mb(); + + writel_relaxed(FIQ_GENERATE, req->reg); + + v6_dma_flush_range(start, end); + + while (req->flags) + barrier(); + + raw_local_irq_restore(flags); +} + +void fiq_flush_kern_dcache_area(void *addr, size_t size) +{ + fiq_dma_flush_range(addr, addr + size); +} + +struct smp_operations cns3xxx_smp_ops __initdata = { + .smp_init_cpus = cns3xxx_smp_init_cpus, + .smp_prepare_cpus = cns3xxx_smp_prepare_cpus, + .smp_secondary_init = cns3xxx_secondary_init, + .smp_boot_secondary = cns3xxx_boot_secondary, +}; diff --git a/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c b/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c new file mode 100644 index 0000000..7acff37 --- /dev/null +++ b/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c @@ -0,0 +1,374 @@ +/* + * Cavium CNS3xxx I2C Host Controller + * + * Copyright 2010 Cavium Network + * Copyright 2012 Gateworks Corporation + * Chris Lang + * Tim Harvey + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * We need the memory map + */ + +#define I2C_MEM_MAP_ADDR(x) (i2c->base + x) +#define I2C_MEM_MAP_VALUE(x) (*((unsigned int volatile*)I2C_MEM_MAP_ADDR(x))) + +#define I2C_CONTROLLER_REG I2C_MEM_MAP_VALUE(0x00) +#define I2C_TIME_OUT_REG I2C_MEM_MAP_VALUE(0x04) +#define I2C_SLAVE_ADDRESS_REG I2C_MEM_MAP_VALUE(0x08) +#define I2C_WRITE_DATA_REG I2C_MEM_MAP_VALUE(0x0C) +#define I2C_READ_DATA_REG I2C_MEM_MAP_VALUE(0x10) +#define I2C_INTERRUPT_STATUS_REG I2C_MEM_MAP_VALUE(0x14) +#define I2C_INTERRUPT_ENABLE_REG I2C_MEM_MAP_VALUE(0x18) +#define I2C_TWI_OUT_DLY_REG I2C_MEM_MAP_VALUE(0x1C) + +#define I2C_BUS_ERROR_FLAG (0x1) +#define I2C_ACTION_DONE_FLAG (0x2) + +#define CNS3xxx_I2C_ENABLE() (I2C_CONTROLLER_REG) |= ((unsigned int)0x1 << 31) +#define CNS3xxx_I2C_DISABLE() (I2C_CONTROLLER_REG) &= ~((unsigned int)0x1 << 31) +#define CNS3xxx_I2C_ENABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) |= 0x03 +#define CNS3xxx_I2C_DISABLE_INTR() (I2C_INTERRUPT_ENABLE_REG) &= 0xfc + +#define TWI_TIMEOUT (10*HZ) +#define I2C_100KHZ 100000 +#define I2C_200KHZ 200000 +#define I2C_300KHZ 300000 +#define I2C_400KHZ 400000 + +#define CNS3xxx_I2C_CLK I2C_100KHZ + +#define STATE_DONE 1 +#define STATE_ERROR 2 + +struct cns3xxx_i2c { + struct device *dev; + void __iomem *base; /* virtual */ + wait_queue_head_t wait; + struct i2c_adapter adap; + struct i2c_msg *msg; + u8 state; /* see STATE_ */ + u8 error; /* see TWI_STATUS register */ + int rd_wr_len; + u8 *buf; +}; + +static u32 cns3xxx_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static int +cns3xxx_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg) +{ + struct cns3xxx_i2c *i2c = i2c_get_adapdata(adap); + int i, j; + u8 buf[1] = { 0 }; + + if (msg->len == 0) { + /* + * We are probably doing a probe for a device here, + * so set the length to one, and data to 0 + */ + msg->len = 1; + i2c->buf = buf; + } else { + i2c->buf = msg->buf; + } + + if (msg->flags & I2C_M_TEN) { + printk + ("%s:%d: Presently the driver does not handle extended addressing\n", + __FUNCTION__, __LINE__); + return -EINVAL; + } + i2c->msg = msg; + + for (i = 0; i < msg->len; i++) { + if (msg->len - i >= 4) + i2c->rd_wr_len = 3; + else + i2c->rd_wr_len = msg->len - i - 1; + + // Set Data Width and TWI_EN + I2C_CONTROLLER_REG = 0x80000000 | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len); + + // Clear Write Reg + I2C_WRITE_DATA_REG = 0; + + // Set the slave address + I2C_SLAVE_ADDRESS_REG = (msg->addr << 1); + + // Are we Writing + if (!(msg->flags & I2C_M_RD)) { + I2C_CONTROLLER_REG |= (1 << 4); + if (i != 0) { + /* + * We need to set the address in the first byte. + * The base address is going to be in buf[0] and then + * it needs to be incremented by i - 1. + */ + i2c->buf--; + *i2c->buf = buf[0] + i - 1; + + if (i2c->rd_wr_len < 3) { + i += i2c->rd_wr_len; + i2c->rd_wr_len++; + I2C_CONTROLLER_REG = 0x80000000 | (1 << 4) | (i2c->rd_wr_len << 2) | (i2c->rd_wr_len); + } else { + i += i2c->rd_wr_len - 1; + } + } else { + i += i2c->rd_wr_len; + buf[0] = *i2c->buf; + } + for (j = 0; j <= i2c->rd_wr_len; j++) { + I2C_WRITE_DATA_REG |= ((*i2c->buf++) << (8 * j)); + } + } else { + i += i2c->rd_wr_len; + } + + // Start the Transfer + i2c->state = 0; // Clear out the State + i2c->error = 0; + I2C_CONTROLLER_REG |= (1 << 6); + + if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || + (i2c->state == STATE_DONE), TWI_TIMEOUT)) { + if (i2c->state == STATE_ERROR) { + dev_dbg(i2c->dev, "controller error: 0x%2x", i2c->error); + return -EAGAIN; // try again + } + } else { + dev_err(i2c->dev, "controller timed out " + "waiting for start condition to finish\n"); + return -ETIMEDOUT; + } + } + return 0; +} + +static int +cns3xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + int i; + int ret; + for (i = 0; i < num; i++) + { + ret = cns3xxx_i2c_xfer_msg(adap, &msgs[i]); + if (ret < 0) { + return ret; + } + } + return num; +} + + +static struct i2c_algorithm cns3xxx_i2c_algo = { + .master_xfer = cns3xxx_i2c_xfer, + .functionality = cns3xxx_i2c_func, +}; + +static struct i2c_adapter cns3xxx_i2c_adapter = { + .owner = THIS_MODULE, + .algo = &cns3xxx_i2c_algo, + .algo_data = NULL, + .nr = 0, + .name = "CNS3xxx I2C 0", + .retries = 5, +}; + +static void cns3xxx_i2c_adapter_init(struct cns3xxx_i2c *i2c) +{ + struct clk *clk; + + clk = devm_clk_get(i2c->dev, "cpu"); + if (WARN_ON(!clk)) + return; + + /* Disable the I2C */ + I2C_CONTROLLER_REG = 0; /* Disabled the I2C */ + + /* Check the Reg Dump when testing */ + I2C_TIME_OUT_REG = + (((((clk_get_rate(clk) / (2 * CNS3xxx_I2C_CLK)) - + 1) & 0x3FF) << 8) | (1 << 7) | 0x7F); + I2C_TWI_OUT_DLY_REG |= 0x3; + + /* Enable The Interrupt */ + CNS3xxx_I2C_ENABLE_INTR(); + + /* Clear Interrupt Status (0x2 | 0x1) */ + I2C_INTERRUPT_STATUS_REG |= (I2C_ACTION_DONE_FLAG | I2C_BUS_ERROR_FLAG); + + /* Enable the I2C Controller */ + CNS3xxx_I2C_ENABLE(); +} + +static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id) +{ + struct cns3xxx_i2c *i2c = dev_id; + int i; + uint32_t stat = I2C_INTERRUPT_STATUS_REG; + + /* Clear Interrupt */ + I2C_INTERRUPT_STATUS_REG |= 0x1; + + if (stat & I2C_BUS_ERROR_FLAG) { + i2c->state = STATE_ERROR; + i2c->error = (I2C_INTERRUPT_STATUS_REG & 0xff00)>>8; + } else { + if (i2c->msg->flags & I2C_M_RD) { + for (i = 0; i <= i2c->rd_wr_len; i++) + { + *i2c->buf++ = ((I2C_READ_DATA_REG >> (8 * i)) & 0xff); + } + } + i2c->state = STATE_DONE; + } + wake_up(&i2c->wait); + return IRQ_HANDLED; +} + +static int cns3xxx_i2c_probe(struct platform_device *pdev) +{ + struct cns3xxx_i2c *i2c; + struct resource *res, *res2; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + printk("%s: IORESOURCE_MEM not defined \n", __FUNCTION__); + return -ENODEV; + } + + res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res2) { + printk("%s: IORESOURCE_IRQ not defined \n", __FUNCTION__); + return -ENODEV; + } + + i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + if (!request_mem_region(res->start, res->end - res->start + 1, + pdev->name)) { + dev_err(&pdev->dev, "Memory region busy\n"); + ret = -EBUSY; + goto request_mem_failed; + } + + i2c->dev = &pdev->dev; + i2c->base = ioremap(res->start, res->end - res->start + 1); + if (!i2c->base) { + dev_err(&pdev->dev, "Unable to map registers\n"); + ret = -EIO; + goto map_failed; + } + + cns3xxx_i2c_adapter_init(i2c); + + init_waitqueue_head(&i2c->wait); + ret = request_irq(res2->start, cns3xxx_i2c_isr, 0, pdev->name, i2c); + if (ret) { + dev_err(&pdev->dev, "Cannot claim IRQ\n"); + goto request_irq_failed; + } + + platform_set_drvdata(pdev, i2c); + i2c->adap = cns3xxx_i2c_adapter; + i2c_set_adapdata(&i2c->adap, i2c); + i2c->adap.dev.parent = &pdev->dev; + + /* add i2c adapter to i2c tree */ + ret = i2c_add_numbered_adapter(&i2c->adap); + if (ret) { + dev_err(&pdev->dev, "Failed to add adapter\n"); + goto add_adapter_failed; + } + + return 0; + + add_adapter_failed: + free_irq(res2->start, i2c); + request_irq_failed: + iounmap(i2c->base); + map_failed: + release_mem_region(res->start, res->end - res->start + 1); + request_mem_failed: + kfree(i2c); + + return ret; +} + +static int cns3xxx_i2c_remove(struct platform_device *pdev) +{ + struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev); + struct resource *res; + + /* disable i2c logic */ + CNS3xxx_I2C_DISABLE_INTR(); + CNS3xxx_I2C_DISABLE(); + /* remove adapter & data */ + i2c_del_adapter(&i2c->adap); + platform_set_drvdata(pdev, NULL); + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res) + free_irq(res->start, i2c); + + iounmap(i2c->base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res) + release_mem_region(res->start, res->end - res->start + 1); + + kfree(i2c); + + return 0; +} + +static struct platform_driver cns3xxx_i2c_driver = { + .probe = cns3xxx_i2c_probe, + .remove = cns3xxx_i2c_remove, + .driver = { + .owner = THIS_MODULE, + .name = "cns3xxx-i2c", + }, +}; + +static int __init cns3xxx_i2c_init(void) +{ + return platform_driver_register(&cns3xxx_i2c_driver); +} + +static void __exit cns3xxx_i2c_exit(void) +{ + platform_driver_unregister(&cns3xxx_i2c_driver); +} + +module_init(cns3xxx_i2c_init); +module_exit(cns3xxx_i2c_exit); + +MODULE_AUTHOR("Cavium Networks"); +MODULE_DESCRIPTION("Cavium CNS3XXX I2C Controller"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig new file mode 100644 index 0000000..79eebe2 --- /dev/null +++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Kconfig @@ -0,0 +1,24 @@ +config NET_VENDOR_CAVIUM + bool "Cavium devices" + default y + depends on ARCH_CNS3XXX + ---help--- + If you have a network (Ethernet) chipset belonging to this class, + say Y. + + Note that the answer to this question does not directly affect + the kernel: saying N will just case the configurator to skip all + the questions regarding AMD chipsets. If you say Y, you will be asked + for your specific chipset/driver in the following questions. + +if NET_VENDOR_CAVIUM + +config CNS3XXX_ETH + tristate "Cavium CNS3xxx Ethernet support" + depends on ARCH_CNS3XXX + select PHYLIB + help + Say Y here if you want to use built-in Ethernet ports + on CNS3XXX processor. + +endif diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile new file mode 100644 index 0000000..badd240 --- /dev/null +++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the Cavium ethernet device drivers. +# + +obj-$(CONFIG_CNS3XXX_ETH) += cns3xxx_eth.o diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c new file mode 100644 index 0000000..e2db636 --- /dev/null +++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c @@ -0,0 +1,1358 @@ +/* + * Cavium CNS3xxx Gigabit driver for Linux + * + * Copyright 2011 Gateworks Corporation + * Chris Lang + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "cns3xxx_eth" + +#define RX_DESCS 256 +#define TX_DESCS 128 +#define TX_DESC_RESERVE 20 + +#define RX_POOL_ALLOC_SIZE (sizeof(struct rx_desc) * RX_DESCS) +#define TX_POOL_ALLOC_SIZE (sizeof(struct tx_desc) * TX_DESCS) +#define REGS_SIZE 336 + +#define RX_BUFFER_ALIGN 64 +#define RX_BUFFER_ALIGN_MASK (~(RX_BUFFER_ALIGN - 1)) + +#define SKB_HEAD_ALIGN (((PAGE_SIZE - NET_SKB_PAD) % RX_BUFFER_ALIGN) + NET_SKB_PAD + NET_IP_ALIGN) +#define RX_SEGMENT_ALLOC_SIZE 2048 +#define RX_SEGMENT_BUFSIZE (SKB_WITH_OVERHEAD(RX_SEGMENT_ALLOC_SIZE)) +#define RX_SEGMENT_MRU (((RX_SEGMENT_BUFSIZE - SKB_HEAD_ALIGN) & RX_BUFFER_ALIGN_MASK) - NET_IP_ALIGN) +#define MAX_MTU 9500 + +#define NAPI_WEIGHT 64 + +/* MDIO Defines */ +#define MDIO_CMD_COMPLETE 0x00008000 +#define MDIO_WRITE_COMMAND 0x00002000 +#define MDIO_READ_COMMAND 0x00004000 +#define MDIO_REG_OFFSET 8 +#define MDIO_VALUE_OFFSET 16 + +/* Descritor Defines */ +#define END_OF_RING 0x40000000 +#define FIRST_SEGMENT 0x20000000 +#define LAST_SEGMENT 0x10000000 +#define FORCE_ROUTE 0x04000000 +#define IP_CHECKSUM 0x00040000 +#define UDP_CHECKSUM 0x00020000 +#define TCP_CHECKSUM 0x00010000 + +/* Port Config Defines */ +#define PORT_BP_ENABLE 0x00020000 +#define PORT_DISABLE 0x00040000 +#define PORT_LEARN_DIS 0x00080000 +#define PORT_BLOCK_STATE 0x00100000 +#define PORT_BLOCK_MODE 0x00200000 + +#define PROMISC_OFFSET 29 + +/* Global Config Defines */ +#define UNKNOWN_VLAN_TO_CPU 0x02000000 +#define ACCEPT_CRC_PACKET 0x00200000 +#define CRC_STRIPPING 0x00100000 + +/* VLAN Config Defines */ +#define NIC_MODE 0x00008000 +#define VLAN_UNAWARE 0x00000001 + +/* DMA AUTO Poll Defines */ +#define TS_POLL_EN 0x00000020 +#define TS_SUSPEND 0x00000010 +#define FS_POLL_EN 0x00000002 +#define FS_SUSPEND 0x00000001 + +/* DMA Ring Control Defines */ +#define QUEUE_THRESHOLD 0x000000f0 +#define CLR_FS_STATE 0x80000000 + +/* Interrupt Status Defines */ +#define MAC0_STATUS_CHANGE 0x00004000 +#define MAC1_STATUS_CHANGE 0x00008000 +#define MAC2_STATUS_CHANGE 0x00010000 +#define MAC0_RX_ERROR 0x00100000 +#define MAC1_RX_ERROR 0x00200000 +#define MAC2_RX_ERROR 0x00400000 + +struct tx_desc +{ + u32 sdp; /* segment data pointer */ + + union { + struct { + u32 sdl:16; /* segment data length */ + u32 tco:1; + u32 uco:1; + u32 ico:1; + u32 rsv_1:3; /* reserve */ + u32 pri:3; + u32 fp:1; /* force priority */ + u32 fr:1; + u32 interrupt:1; + u32 lsd:1; + u32 fsd:1; + u32 eor:1; + u32 cown:1; + }; + u32 config0; + }; + + union { + struct { + u32 ctv:1; + u32 stv:1; + u32 sid:4; + u32 inss:1; + u32 dels:1; + u32 rsv_2:9; + u32 pmap:5; + u32 mark:3; + u32 ewan:1; + u32 fewan:1; + u32 rsv_3:5; + }; + u32 config1; + }; + + union { + struct { + u32 c_vid:12; + u32 c_cfs:1; + u32 c_pri:3; + u32 s_vid:12; + u32 s_dei:1; + u32 s_pri:3; + }; + u32 config2; + }; + + u8 alignment[16]; /* for 32 byte */ +}; + +struct rx_desc +{ + u32 sdp; /* segment data pointer */ + + union { + struct { + u32 sdl:16; /* segment data length */ + u32 l4f:1; + u32 ipf:1; + u32 prot:4; + u32 hr:6; + u32 lsd:1; + u32 fsd:1; + u32 eor:1; + u32 cown:1; + }; + u32 config0; + }; + + union { + struct { + u32 ctv:1; + u32 stv:1; + u32 unv:1; + u32 iwan:1; + u32 exdv:1; + u32 e_wan:1; + u32 rsv_1:2; + u32 sp:3; + u32 crc_err:1; + u32 un_eth:1; + u32 tc:2; + u32 rsv_2:1; + u32 ip_offset:5; + u32 rsv_3:11; + }; + u32 config1; + }; + + union { + struct { + u32 c_vid:12; + u32 c_cfs:1; + u32 c_pri:3; + u32 s_vid:12; + u32 s_dei:1; + u32 s_pri:3; + }; + u32 config2; + }; + + u8 alignment[16]; /* for 32 byte alignment */ +}; + + +struct switch_regs { + u32 phy_control; + u32 phy_auto_addr; + u32 mac_glob_cfg; + u32 mac_cfg[4]; + u32 mac_pri_ctrl[5], __res; + u32 etype[2]; + u32 udp_range[4]; + u32 prio_etype_udp; + u32 prio_ipdscp[8]; + u32 tc_ctrl; + u32 rate_ctrl; + u32 fc_glob_thrs; + u32 fc_port_thrs; + u32 mc_fc_glob_thrs; + u32 dc_glob_thrs; + u32 arl_vlan_cmd; + u32 arl_ctrl[3]; + u32 vlan_cfg; + u32 pvid[2]; + u32 vlan_ctrl[3]; + u32 session_id[8]; + u32 intr_stat; + u32 intr_mask; + u32 sram_test; + u32 mem_queue; + u32 farl_ctrl; + u32 fc_input_thrs, __res1[2]; + u32 clk_skew_ctrl; + u32 mac_glob_cfg_ext, __res2[2]; + u32 dma_ring_ctrl; + u32 dma_auto_poll_cfg; + u32 delay_intr_cfg, __res3; + u32 ts_dma_ctrl0; + u32 ts_desc_ptr0; + u32 ts_desc_base_addr0, __res4; + u32 fs_dma_ctrl0; + u32 fs_desc_ptr0; + u32 fs_desc_base_addr0, __res5; + u32 ts_dma_ctrl1; + u32 ts_desc_ptr1; + u32 ts_desc_base_addr1, __res6; + u32 fs_dma_ctrl1; + u32 fs_desc_ptr1; + u32 fs_desc_base_addr1; + u32 __res7[109]; + u32 mac_counter0[13]; +}; + +struct _tx_ring { + struct tx_desc *desc; + dma_addr_t phys_addr; + struct tx_desc *cur_addr; + struct sk_buff *buff_tab[TX_DESCS]; + unsigned int phys_tab[TX_DESCS]; + u32 free_index; + u32 count_index; + u32 cur_index; + int num_used; + int num_count; + bool stopped; +}; + +struct _rx_ring { + struct rx_desc *desc; + dma_addr_t phys_addr; + struct rx_desc *cur_addr; + void *buff_tab[RX_DESCS]; + unsigned int phys_tab[RX_DESCS]; + u32 cur_index; + u32 alloc_index; + int alloc_count; +}; + +struct sw { + struct switch_regs __iomem *regs; + struct napi_struct napi; + struct cns3xxx_plat_info *plat; + struct _tx_ring tx_ring; + struct _rx_ring rx_ring; + struct sk_buff *frag_first; + struct sk_buff *frag_last; + struct device *dev; + int rx_irq; + int stat_irq; +}; + +struct port { + struct net_device *netdev; + struct phy_device *phydev; + struct sw *sw; + int id; /* logical port ID */ + int speed, duplex; +}; + +static spinlock_t mdio_lock; +static DEFINE_SPINLOCK(tx_lock); +static struct switch_regs __iomem *mdio_regs; /* mdio command and status only */ +struct mii_bus *mdio_bus; +static int ports_open; +static struct port *switch_port_tab[4]; +static struct dma_pool *rx_dma_pool; +static struct dma_pool *tx_dma_pool; +struct net_device *napi_dev; + +static int cns3xxx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, + int write, u16 cmd) +{ + int cycles = 0; + u32 temp = 0; + + temp = __raw_readl(&mdio_regs->phy_control); + temp |= MDIO_CMD_COMPLETE; + __raw_writel(temp, &mdio_regs->phy_control); + udelay(10); + + if (write) { + temp = (cmd << MDIO_VALUE_OFFSET); + temp |= MDIO_WRITE_COMMAND; + } else { + temp = MDIO_READ_COMMAND; + } + temp |= ((location & 0x1f) << MDIO_REG_OFFSET); + temp |= (phy_id & 0x1f); + + __raw_writel(temp, &mdio_regs->phy_control); + + while (((__raw_readl(&mdio_regs->phy_control) & MDIO_CMD_COMPLETE) == 0) + && cycles < 5000) { + udelay(1); + cycles++; + } + + if (cycles == 5000) { + printk(KERN_ERR "%s #%i: MII transaction failed\n", bus->name, + phy_id); + return -1; + } + + temp = __raw_readl(&mdio_regs->phy_control); + temp |= MDIO_CMD_COMPLETE; + __raw_writel(temp, &mdio_regs->phy_control); + + if (write) + return 0; + + return ((temp >> MDIO_VALUE_OFFSET) & 0xFFFF); +} + +static int cns3xxx_mdio_read(struct mii_bus *bus, int phy_id, int location) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&mdio_lock, flags); + ret = cns3xxx_mdio_cmd(bus, phy_id, location, 0, 0); + spin_unlock_irqrestore(&mdio_lock, flags); + return ret; +} + +static int cns3xxx_mdio_write(struct mii_bus *bus, int phy_id, int location, + u16 val) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&mdio_lock, flags); + ret = cns3xxx_mdio_cmd(bus, phy_id, location, 1, val); + spin_unlock_irqrestore(&mdio_lock, flags); + return ret; +} + +static int cns3xxx_mdio_register(void __iomem *base) +{ + int err; + + if (!(mdio_bus = mdiobus_alloc())) + return -ENOMEM; + + mdio_regs = base; + + spin_lock_init(&mdio_lock); + mdio_bus->name = "CNS3xxx MII Bus"; + mdio_bus->read = &cns3xxx_mdio_read; + mdio_bus->write = &cns3xxx_mdio_write; + strcpy(mdio_bus->id, "0"); + + if ((err = mdiobus_register(mdio_bus))) + mdiobus_free(mdio_bus); + return err; +} + +static void cns3xxx_mdio_remove(void) +{ + mdiobus_unregister(mdio_bus); + mdiobus_free(mdio_bus); +} + +static void enable_tx_dma(struct sw *sw) +{ + __raw_writel(0x1, &sw->regs->ts_dma_ctrl0); +} + +static void enable_rx_dma(struct sw *sw) +{ + __raw_writel(0x1, &sw->regs->fs_dma_ctrl0); +} + +static void cns3xxx_adjust_link(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + struct phy_device *phydev = port->phydev; + + if (!phydev->link) { + if (port->speed) { + port->speed = 0; + printk(KERN_INFO "%s: link down\n", dev->name); + } + return; + } + + if (port->speed == phydev->speed && port->duplex == phydev->duplex) + return; + + port->speed = phydev->speed; + port->duplex = phydev->duplex; + + printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n", + dev->name, port->speed, port->duplex ? "full" : "half"); +} + +static void eth_schedule_poll(struct sw *sw) +{ + if (unlikely(!napi_schedule_prep(&sw->napi))) + return; + + disable_irq_nosync(sw->rx_irq); + __napi_schedule(&sw->napi); +} + +irqreturn_t eth_rx_irq(int irq, void *pdev) +{ + struct net_device *dev = pdev; + struct sw *sw = netdev_priv(dev); + eth_schedule_poll(sw); + return (IRQ_HANDLED); +} + +irqreturn_t eth_stat_irq(int irq, void *pdev) +{ + struct net_device *dev = pdev; + struct sw *sw = netdev_priv(dev); + u32 cfg; + u32 stat = __raw_readl(&sw->regs->intr_stat); + __raw_writel(0xffffffff, &sw->regs->intr_stat); + + if (stat & MAC2_RX_ERROR) + switch_port_tab[3]->netdev->stats.rx_dropped++; + if (stat & MAC1_RX_ERROR) + switch_port_tab[1]->netdev->stats.rx_dropped++; + if (stat & MAC0_RX_ERROR) + switch_port_tab[0]->netdev->stats.rx_dropped++; + + if (stat & MAC0_STATUS_CHANGE) { + cfg = __raw_readl(&sw->regs->mac_cfg[0]); + switch_port_tab[0]->phydev->link = (cfg & 0x1); + switch_port_tab[0]->phydev->duplex = ((cfg >> 4) & 0x1); + if (((cfg >> 2) & 0x3) == 2) + switch_port_tab[0]->phydev->speed = 1000; + else if (((cfg >> 2) & 0x3) == 1) + switch_port_tab[0]->phydev->speed = 100; + else + switch_port_tab[0]->phydev->speed = 10; + cns3xxx_adjust_link(switch_port_tab[0]->netdev); + } + + if (stat & MAC1_STATUS_CHANGE) { + cfg = __raw_readl(&sw->regs->mac_cfg[1]); + switch_port_tab[1]->phydev->link = (cfg & 0x1); + switch_port_tab[1]->phydev->duplex = ((cfg >> 4) & 0x1); + if (((cfg >> 2) & 0x3) == 2) + switch_port_tab[1]->phydev->speed = 1000; + else if (((cfg >> 2) & 0x3) == 1) + switch_port_tab[1]->phydev->speed = 100; + else + switch_port_tab[1]->phydev->speed = 10; + cns3xxx_adjust_link(switch_port_tab[1]->netdev); + } + + if (stat & MAC2_STATUS_CHANGE) { + cfg = __raw_readl(&sw->regs->mac_cfg[3]); + switch_port_tab[3]->phydev->link = (cfg & 0x1); + switch_port_tab[3]->phydev->duplex = ((cfg >> 4) & 0x1); + if (((cfg >> 2) & 0x3) == 2) + switch_port_tab[3]->phydev->speed = 1000; + else if (((cfg >> 2) & 0x3) == 1) + switch_port_tab[3]->phydev->speed = 100; + else + switch_port_tab[3]->phydev->speed = 10; + cns3xxx_adjust_link(switch_port_tab[3]->netdev); + } + + return (IRQ_HANDLED); +} + + +static void cns3xxx_alloc_rx_buf(struct sw *sw, int received) +{ + struct _rx_ring *rx_ring = &sw->rx_ring; + unsigned int i = rx_ring->alloc_index; + struct rx_desc *desc = &(rx_ring)->desc[i]; + void *buf; + unsigned int phys; + + for (received += rx_ring->alloc_count; received > 0; received--) { + buf = kmalloc(RX_SEGMENT_ALLOC_SIZE, GFP_ATOMIC); + if (!buf) + break; + + phys = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN, + RX_SEGMENT_MRU, DMA_FROM_DEVICE); + if (dma_mapping_error(sw->dev, phys)) { + kfree(buf); + break; + } + + desc->sdl = RX_SEGMENT_MRU; + desc->sdp = phys; + + wmb(); + + /* put the new buffer on RX-free queue */ + rx_ring->buff_tab[i] = buf; + rx_ring->phys_tab[i] = phys; + if (i == RX_DESCS - 1) { + i = 0; + desc->config0 = END_OF_RING | FIRST_SEGMENT | + LAST_SEGMENT | RX_SEGMENT_MRU; + desc = &(rx_ring)->desc[i]; + } else { + desc->config0 = FIRST_SEGMENT | LAST_SEGMENT | + RX_SEGMENT_MRU; + i++; + desc++; + } + } + + rx_ring->alloc_count = received; + rx_ring->alloc_index = i; +} + +static void eth_check_num_used(struct _tx_ring *tx_ring) +{ + bool stop = false; + int i; + + if (tx_ring->num_used >= TX_DESCS - TX_DESC_RESERVE) + stop = true; + + if (tx_ring->stopped == stop) + return; + + tx_ring->stopped = stop; + for (i = 0; i < 4; i++) { + struct port *port = switch_port_tab[i]; + struct net_device *dev; + + if (!port) + continue; + + dev = port->netdev; + if (stop) + netif_stop_queue(dev); + else + netif_wake_queue(dev); + } +} + +static void eth_complete_tx(struct sw *sw) +{ + struct _tx_ring *tx_ring = &sw->tx_ring; + struct tx_desc *desc; + int i; + int index; + int num_used = tx_ring->num_used; + struct sk_buff *skb; + + index = tx_ring->free_index; + desc = &(tx_ring)->desc[index]; + for (i = 0; i < num_used; i++) { + if (desc->cown) { + skb = tx_ring->buff_tab[index]; + tx_ring->buff_tab[index] = 0; + if (skb) + dev_kfree_skb_any(skb); + dma_unmap_single(sw->dev, tx_ring->phys_tab[index], + desc->sdl, DMA_TO_DEVICE); + if (++index == TX_DESCS) { + index = 0; + desc = &(tx_ring)->desc[index]; + } else { + desc++; + } + } else { + break; + } + } + tx_ring->free_index = index; + tx_ring->num_used -= i; + eth_check_num_used(tx_ring); +} + +static int eth_poll(struct napi_struct *napi, int budget) +{ + struct sw *sw = container_of(napi, struct sw, napi); + struct _rx_ring *rx_ring = &sw->rx_ring; + int received = 0; + unsigned int length; + unsigned int i = rx_ring->cur_index; + struct rx_desc *desc = &(rx_ring)->desc[i]; + unsigned int alloc_count = rx_ring->alloc_count; + + while (desc->cown && alloc_count + received < RX_DESCS - 1) { + struct sk_buff *skb; + int reserve = SKB_HEAD_ALIGN; + + if (received >= budget) + break; + + /* process received frame */ + dma_unmap_single(sw->dev, rx_ring->phys_tab[i], + RX_SEGMENT_MRU, DMA_FROM_DEVICE); + + skb = build_skb(rx_ring->buff_tab[i], 0); + if (!skb) + break; + + skb->dev = switch_port_tab[desc->sp]->netdev; + + length = desc->sdl; + if (desc->fsd && !desc->lsd) + length = RX_SEGMENT_MRU; + + if (!desc->fsd) { + reserve -= NET_IP_ALIGN; + if (!desc->lsd) + length += NET_IP_ALIGN; + } + + skb_reserve(skb, reserve); + skb_put(skb, length); + + if (!sw->frag_first) + sw->frag_first = skb; + else { + if (sw->frag_first == sw->frag_last) + skb_frag_add_head(sw->frag_first, skb); + else + sw->frag_last->next = skb; + sw->frag_first->len += skb->len; + sw->frag_first->data_len += skb->len; + sw->frag_first->truesize += skb->truesize; + } + sw->frag_last = skb; + + if (desc->lsd) { + struct net_device *dev; + + skb = sw->frag_first; + dev = skb->dev; + skb->protocol = eth_type_trans(skb, dev); + + dev->stats.rx_packets++; + dev->stats.rx_bytes += skb->len; + + /* RX Hardware checksum offload */ + skb->ip_summed = CHECKSUM_NONE; + switch (desc->prot) { + case 1: + case 2: + case 5: + case 6: + case 13: + case 14: + if (!desc->l4f) { + skb->ip_summed = CHECKSUM_UNNECESSARY; + napi_gro_receive(napi, skb); + break; + } + /* fall through */ + default: + netif_receive_skb(skb); + break; + } + + sw->frag_first = NULL; + sw->frag_last = NULL; + } + + received++; + if (++i == RX_DESCS) { + i = 0; + desc = &(rx_ring)->desc[i]; + } else { + desc++; + } + } + + rx_ring->cur_index = i; + if (!received) { + napi_complete(napi); + enable_irq(sw->rx_irq); + + /* if rx descriptors are full schedule another poll */ + if (rx_ring->desc[(i-1) & (RX_DESCS-1)].cown) + eth_schedule_poll(sw); + } + + spin_lock_bh(&tx_lock); + eth_complete_tx(sw); + spin_unlock_bh(&tx_lock); + + cns3xxx_alloc_rx_buf(sw, received); + + wmb(); + enable_rx_dma(sw); + + return received; +} + +static void eth_set_desc(struct sw *sw, struct _tx_ring *tx_ring, int index, + int index_last, void *data, int len, u32 config0, + u32 pmap) +{ + struct tx_desc *tx_desc = &(tx_ring)->desc[index]; + unsigned int phys; + + phys = dma_map_single(sw->dev, data, len, DMA_TO_DEVICE); + tx_desc->sdp = phys; + tx_desc->pmap = pmap; + tx_ring->phys_tab[index] = phys; + + config0 |= len; + if (index == TX_DESCS - 1) + config0 |= END_OF_RING; + if (index == index_last) + config0 |= LAST_SEGMENT; + + wmb(); + tx_desc->config0 = config0; +} + +static int eth_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + struct sw *sw = port->sw; + struct _tx_ring *tx_ring = &sw->tx_ring; + struct sk_buff *skb1; + char pmap = (1 << port->id); + int nr_frags = skb_shinfo(skb)->nr_frags; + int nr_desc = nr_frags; + int index0, index, index_last; + int len0; + unsigned int i; + u32 config0; + + if (pmap == 8) + pmap = (1 << 4); + + skb_walk_frags(skb, skb1) + nr_desc++; + + eth_schedule_poll(sw); + spin_lock_bh(&tx_lock); + if ((tx_ring->num_used + nr_desc + 1) >= TX_DESCS) { + spin_unlock_bh(&tx_lock); + return NETDEV_TX_BUSY; + } + + index = index0 = tx_ring->cur_index; + index_last = (index0 + nr_desc) % TX_DESCS; + tx_ring->cur_index = (index_last + 1) % TX_DESCS; + + spin_unlock_bh(&tx_lock); + + config0 = FORCE_ROUTE; + if (skb->ip_summed == CHECKSUM_PARTIAL) + config0 |= UDP_CHECKSUM | TCP_CHECKSUM; + + len0 = skb->len; + + /* fragments */ + for (i = 0; i < nr_frags; i++) { + struct skb_frag_struct *frag; + void *addr; + + index = (index + 1) % TX_DESCS; + + frag = &skb_shinfo(skb)->frags[i]; + addr = page_address(skb_frag_page(frag)) + frag->page_offset; + + eth_set_desc(sw, tx_ring, index, index_last, addr, frag->size, + config0, pmap); + } + + if (nr_frags) + len0 = skb->len - skb->data_len; + + skb_walk_frags(skb, skb1) { + index = (index + 1) % TX_DESCS; + len0 -= skb1->len; + + eth_set_desc(sw, tx_ring, index, index_last, skb1->data, + skb1->len, config0, pmap); + } + + tx_ring->buff_tab[index0] = skb; + eth_set_desc(sw, tx_ring, index0, index_last, skb->data, len0, + config0 | FIRST_SEGMENT, pmap); + + wmb(); + + spin_lock(&tx_lock); + tx_ring->num_used += nr_desc + 1; + spin_unlock(&tx_lock); + + dev->stats.tx_packets++; + dev->stats.tx_bytes += skb->len; + + enable_tx_dma(sw); + + return NETDEV_TX_OK; +} + +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) +{ + struct port *port = netdev_priv(dev); + + if (!netif_running(dev)) + return -EINVAL; + return phy_mii_ioctl(port->phydev, req, cmd); +} + +/* ethtool support */ + +static void cns3xxx_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + strcpy(info->driver, DRV_NAME); + strcpy(info->bus_info, "internal"); +} + +static int cns3xxx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct port *port = netdev_priv(dev); + return phy_ethtool_gset(port->phydev, cmd); +} + +static int cns3xxx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct port *port = netdev_priv(dev); + return phy_ethtool_sset(port->phydev, cmd); +} + +static int cns3xxx_nway_reset(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + return phy_start_aneg(port->phydev); +} + +static struct ethtool_ops cns3xxx_ethtool_ops = { + .get_drvinfo = cns3xxx_get_drvinfo, + .get_settings = cns3xxx_get_settings, + .set_settings = cns3xxx_set_settings, + .nway_reset = cns3xxx_nway_reset, + .get_link = ethtool_op_get_link, +}; + + +static int init_rings(struct sw *sw) +{ + int i; + struct _rx_ring *rx_ring = &sw->rx_ring; + struct _tx_ring *tx_ring = &sw->tx_ring; + + __raw_writel(0, &sw->regs->fs_dma_ctrl0); + __raw_writel(TS_SUSPEND | FS_SUSPEND, &sw->regs->dma_auto_poll_cfg); + __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl); + __raw_writel(CLR_FS_STATE | QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl); + + __raw_writel(QUEUE_THRESHOLD, &sw->regs->dma_ring_ctrl); + + if (!(rx_dma_pool = dma_pool_create(DRV_NAME, sw->dev, + RX_POOL_ALLOC_SIZE, 32, 0))) + return -ENOMEM; + + if (!(rx_ring->desc = dma_pool_alloc(rx_dma_pool, GFP_KERNEL, + &rx_ring->phys_addr))) + return -ENOMEM; + memset(rx_ring->desc, 0, RX_POOL_ALLOC_SIZE); + + /* Setup RX buffers */ + for (i = 0; i < RX_DESCS; i++) { + struct rx_desc *desc = &(rx_ring)->desc[i]; + void *buf; + + buf = kzalloc(RX_SEGMENT_ALLOC_SIZE, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + desc->sdl = RX_SEGMENT_MRU; + if (i == (RX_DESCS - 1)) + desc->eor = 1; + desc->fsd = 1; + desc->lsd = 1; + + desc->sdp = dma_map_single(sw->dev, buf + SKB_HEAD_ALIGN, + RX_SEGMENT_MRU, DMA_FROM_DEVICE); + if (dma_mapping_error(sw->dev, desc->sdp)) + return -EIO; + + rx_ring->buff_tab[i] = buf; + rx_ring->phys_tab[i] = desc->sdp; + desc->cown = 0; + } + __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_ptr0); + __raw_writel(rx_ring->phys_addr, &sw->regs->fs_desc_base_addr0); + + if (!(tx_dma_pool = dma_pool_create(DRV_NAME, sw->dev, + TX_POOL_ALLOC_SIZE, 32, 0))) + return -ENOMEM; + + if (!(tx_ring->desc = dma_pool_alloc(tx_dma_pool, GFP_KERNEL, + &tx_ring->phys_addr))) + return -ENOMEM; + memset(tx_ring->desc, 0, TX_POOL_ALLOC_SIZE); + + /* Setup TX buffers */ + for (i = 0; i < TX_DESCS; i++) { + struct tx_desc *desc = &(tx_ring)->desc[i]; + tx_ring->buff_tab[i] = 0; + + if (i == (TX_DESCS - 1)) + desc->eor = 1; + desc->cown = 1; + } + __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_ptr0); + __raw_writel(tx_ring->phys_addr, &sw->regs->ts_desc_base_addr0); + + return 0; +} + +static void destroy_rings(struct sw *sw) +{ + int i; + if (sw->rx_ring.desc) { + for (i = 0; i < RX_DESCS; i++) { + struct _rx_ring *rx_ring = &sw->rx_ring; + struct rx_desc *desc = &(rx_ring)->desc[i]; + struct sk_buff *skb = sw->rx_ring.buff_tab[i]; + + if (!skb) + continue; + + dma_unmap_single(sw->dev, desc->sdp, RX_SEGMENT_MRU, + DMA_FROM_DEVICE); + dev_kfree_skb(skb); + } + dma_pool_free(rx_dma_pool, sw->rx_ring.desc, sw->rx_ring.phys_addr); + dma_pool_destroy(rx_dma_pool); + rx_dma_pool = 0; + sw->rx_ring.desc = 0; + } + if (sw->tx_ring.desc) { + for (i = 0; i < TX_DESCS; i++) { + struct _tx_ring *tx_ring = &sw->tx_ring; + struct tx_desc *desc = &(tx_ring)->desc[i]; + struct sk_buff *skb = sw->tx_ring.buff_tab[i]; + if (skb) { + dma_unmap_single(sw->dev, desc->sdp, + skb->len, DMA_TO_DEVICE); + dev_kfree_skb(skb); + } + } + dma_pool_free(tx_dma_pool, sw->tx_ring.desc, sw->tx_ring.phys_addr); + dma_pool_destroy(tx_dma_pool); + tx_dma_pool = 0; + sw->tx_ring.desc = 0; + } +} + +static int eth_open(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + struct sw *sw = port->sw; + u32 temp; + + port->speed = 0; /* force "link up" message */ + phy_start(port->phydev); + + netif_start_queue(dev); + + if (!ports_open) { + request_irq(sw->rx_irq, eth_rx_irq, IRQF_SHARED, "gig_switch", napi_dev); + request_irq(sw->stat_irq, eth_stat_irq, IRQF_SHARED, "gig_stat", napi_dev); + napi_enable(&sw->napi); + netif_start_queue(napi_dev); + + __raw_writel(~(MAC0_STATUS_CHANGE | MAC1_STATUS_CHANGE | MAC2_STATUS_CHANGE | + MAC0_RX_ERROR | MAC1_RX_ERROR | MAC2_RX_ERROR), &sw->regs->intr_mask); + + temp = __raw_readl(&sw->regs->mac_cfg[2]); + temp &= ~(PORT_DISABLE); + __raw_writel(temp, &sw->regs->mac_cfg[2]); + + temp = __raw_readl(&sw->regs->dma_auto_poll_cfg); + temp &= ~(TS_SUSPEND | FS_SUSPEND); + __raw_writel(temp, &sw->regs->dma_auto_poll_cfg); + + enable_rx_dma(sw); + } + temp = __raw_readl(&sw->regs->mac_cfg[port->id]); + temp &= ~(PORT_DISABLE); + __raw_writel(temp, &sw->regs->mac_cfg[port->id]); + + ports_open++; + netif_carrier_on(dev); + + return 0; +} + +static int eth_close(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + struct sw *sw = port->sw; + u32 temp; + + ports_open--; + + temp = __raw_readl(&sw->regs->mac_cfg[port->id]); + temp |= (PORT_DISABLE); + __raw_writel(temp, &sw->regs->mac_cfg[port->id]); + + netif_stop_queue(dev); + + phy_stop(port->phydev); + + if (!ports_open) { + disable_irq(sw->rx_irq); + free_irq(sw->rx_irq, napi_dev); + disable_irq(sw->stat_irq); + free_irq(sw->stat_irq, napi_dev); + napi_disable(&sw->napi); + netif_stop_queue(napi_dev); + temp = __raw_readl(&sw->regs->mac_cfg[2]); + temp |= (PORT_DISABLE); + __raw_writel(temp, &sw->regs->mac_cfg[2]); + + __raw_writel(TS_SUSPEND | FS_SUSPEND, + &sw->regs->dma_auto_poll_cfg); + } + + netif_carrier_off(dev); + return 0; +} + +static void eth_rx_mode(struct net_device *dev) +{ + struct port *port = netdev_priv(dev); + struct sw *sw = port->sw; + u32 temp; + + temp = __raw_readl(&sw->regs->mac_glob_cfg); + + if (dev->flags & IFF_PROMISC) { + if (port->id == 3) + temp |= ((1 << 2) << PROMISC_OFFSET); + else + temp |= ((1 << port->id) << PROMISC_OFFSET); + } else { + if (port->id == 3) + temp &= ~((1 << 2) << PROMISC_OFFSET); + else + temp &= ~((1 << port->id) << PROMISC_OFFSET); + } + __raw_writel(temp, &sw->regs->mac_glob_cfg); +} + +static int eth_set_mac(struct net_device *netdev, void *p) +{ + struct port *port = netdev_priv(netdev); + struct sw *sw = port->sw; + struct sockaddr *addr = p; + u32 cycles = 0; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EADDRNOTAVAIL; + + /* Invalidate old ARL Entry */ + if (port->id == 3) + __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]); + else + __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]); + __raw_writel( ((netdev->dev_addr[0] << 24) | (netdev->dev_addr[1] << 16) | + (netdev->dev_addr[2] << 8) | (netdev->dev_addr[3])), + &sw->regs->arl_ctrl[1]); + + __raw_writel( ((netdev->dev_addr[4] << 24) | (netdev->dev_addr[5] << 16) | + (1 << 1)), + &sw->regs->arl_ctrl[2]); + __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd); + + while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0) + && cycles < 5000) { + udelay(1); + cycles++; + } + + cycles = 0; + memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); + + if (port->id == 3) + __raw_writel((port->id << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]); + else + __raw_writel(((port->id + 1) << 16) | (0x4 << 9), &sw->regs->arl_ctrl[0]); + __raw_writel( ((addr->sa_data[0] << 24) | (addr->sa_data[1] << 16) | + (addr->sa_data[2] << 8) | (addr->sa_data[3])), + &sw->regs->arl_ctrl[1]); + + __raw_writel( ((addr->sa_data[4] << 24) | (addr->sa_data[5] << 16) | + (7 << 4) | (1 << 1)), &sw->regs->arl_ctrl[2]); + __raw_writel((1 << 19), &sw->regs->arl_vlan_cmd); + + while (((__raw_readl(&sw->regs->arl_vlan_cmd) & (1 << 21)) == 0) + && cycles < 5000) { + udelay(1); + cycles++; + } + return 0; +} + +static int cns3xxx_change_mtu(struct net_device *dev, int new_mtu) +{ + if (new_mtu > MAX_MTU) + return -EINVAL; + + dev->mtu = new_mtu; + return 0; +} + +static const struct net_device_ops cns3xxx_netdev_ops = { + .ndo_open = eth_open, + .ndo_stop = eth_close, + .ndo_start_xmit = eth_xmit, + .ndo_set_rx_mode = eth_rx_mode, + .ndo_do_ioctl = eth_ioctl, + .ndo_change_mtu = cns3xxx_change_mtu, + .ndo_set_mac_address = eth_set_mac, + .ndo_validate_addr = eth_validate_addr, +}; + +static int eth_init_one(struct platform_device *pdev) +{ + int i; + struct port *port; + struct sw *sw; + struct net_device *dev; + struct cns3xxx_plat_info *plat = pdev->dev.platform_data; + char phy_id[MII_BUS_ID_SIZE + 3]; + int err; + u32 temp; + struct resource *res; + void __iomem *regs; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + err = cns3xxx_mdio_register(regs); + if (err) + return err; + + if (!(napi_dev = alloc_etherdev(sizeof(struct sw)))) { + err = -ENOMEM; + goto err_remove_mdio; + } + + strcpy(napi_dev->name, "switch%d"); + napi_dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST; + + SET_NETDEV_DEV(napi_dev, &pdev->dev); + sw = netdev_priv(napi_dev); + memset(sw, 0, sizeof(struct sw)); + sw->regs = regs; + sw->dev = &pdev->dev; + + sw->rx_irq = platform_get_irq_byname(pdev, "eth_rx"); + sw->stat_irq = platform_get_irq_byname(pdev, "eth_stat"); + + temp = __raw_readl(&sw->regs->phy_auto_addr); + temp |= (3 << 30); /* maximum frame length: 9600 bytes */ + __raw_writel(temp, &sw->regs->phy_auto_addr); + + for (i = 0; i < 4; i++) { + temp = __raw_readl(&sw->regs->mac_cfg[i]); + temp |= (PORT_DISABLE); + __raw_writel(temp, &sw->regs->mac_cfg[i]); + } + + temp = PORT_DISABLE; + __raw_writel(temp, &sw->regs->mac_cfg[2]); + + temp = __raw_readl(&sw->regs->vlan_cfg); + temp |= NIC_MODE | VLAN_UNAWARE; + __raw_writel(temp, &sw->regs->vlan_cfg); + + __raw_writel(UNKNOWN_VLAN_TO_CPU | + CRC_STRIPPING, &sw->regs->mac_glob_cfg); + + if ((err = init_rings(sw)) != 0) { + destroy_rings(sw); + err = -ENOMEM; + goto err_free; + } + platform_set_drvdata(pdev, napi_dev); + + netif_napi_add(napi_dev, &sw->napi, eth_poll, NAPI_WEIGHT); + + for (i = 0; i < 3; i++) { + if (!(plat->ports & (1 << i))) { + continue; + } + + if (!(dev = alloc_etherdev(sizeof(struct port)))) { + goto free_ports; + } + + port = netdev_priv(dev); + port->netdev = dev; + if (i == 2) + port->id = 3; + else + port->id = i; + port->sw = sw; + + temp = __raw_readl(&sw->regs->mac_cfg[port->id]); + temp |= (PORT_DISABLE | PORT_BLOCK_STATE | PORT_LEARN_DIS); + __raw_writel(temp, &sw->regs->mac_cfg[port->id]); + + SET_NETDEV_DEV(dev, &pdev->dev); + dev->netdev_ops = &cns3xxx_netdev_ops; + dev->ethtool_ops = &cns3xxx_ethtool_ops; + dev->tx_queue_len = 1000; + dev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST; + + switch_port_tab[port->id] = port; + memcpy(dev->dev_addr, &plat->hwaddr[i], ETH_ALEN); + + snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy[i]); + port->phydev = phy_connect(dev, phy_id, &cns3xxx_adjust_link, + PHY_INTERFACE_MODE_RGMII); + if ((err = IS_ERR(port->phydev))) { + switch_port_tab[port->id] = 0; + free_netdev(dev); + goto free_ports; + } + + port->phydev->irq = PHY_IGNORE_INTERRUPT; + + if ((err = register_netdev(dev))) { + phy_disconnect(port->phydev); + switch_port_tab[port->id] = 0; + free_netdev(dev); + goto free_ports; + } + + printk(KERN_INFO "%s: RGMII PHY %i on cns3xxx Switch\n", dev->name, plat->phy[i]); + netif_carrier_off(dev); + dev = 0; + } + + return 0; + +free_ports: + err = -ENOMEM; + for (--i; i >= 0; i--) { + if (switch_port_tab[i]) { + port = switch_port_tab[i]; + dev = port->netdev; + unregister_netdev(dev); + phy_disconnect(port->phydev); + switch_port_tab[i] = 0; + free_netdev(dev); + } + } +err_free: + free_netdev(napi_dev); +err_remove_mdio: + cns3xxx_mdio_remove(); + return err; +} + +static int eth_remove_one(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct sw *sw = netdev_priv(dev); + int i; + destroy_rings(sw); + + for (i = 3; i >= 0; i--) { + if (switch_port_tab[i]) { + struct port *port = switch_port_tab[i]; + struct net_device *dev = port->netdev; + unregister_netdev(dev); + phy_disconnect(port->phydev); + switch_port_tab[i] = 0; + free_netdev(dev); + } + } + + free_netdev(napi_dev); + cns3xxx_mdio_remove(); + + return 0; +} + +static struct platform_driver cns3xxx_eth_driver = { + .driver.name = DRV_NAME, + .probe = eth_init_one, + .remove = eth_remove_one, +}; + +static int __init eth_init_module(void) +{ + return platform_driver_register(&cns3xxx_eth_driver); +} + +static void __exit eth_cleanup_module(void) +{ + platform_driver_unregister(&cns3xxx_eth_driver); +} + +module_init(eth_init_module); +module_exit(eth_cleanup_module); + +MODULE_AUTHOR("Chris Lang"); +MODULE_DESCRIPTION("Cavium CNS3xxx Ethernet driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:cns3xxx_eth"); diff --git a/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c b/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c new file mode 100644 index 0000000..6301986 --- /dev/null +++ b/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c @@ -0,0 +1,448 @@ +/******************************************************************************* + * + * CNS3XXX SPI controller driver (master mode only) + * + * Copyright (c) 2008 Cavium Networks + * Copyright 2011 Gateworks Corporation + * Chris Lang + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or + * visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + * + ******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +/* + * define access macros + */ +#define SPI_MEM_MAP_VALUE(reg_offset) (*((u32 volatile *)(hw->base + reg_offset))) + +#define SPI_CONFIGURATION_REG SPI_MEM_MAP_VALUE(0x00) +#define SPI_SERVICE_STATUS_REG SPI_MEM_MAP_VALUE(0x04) +#define SPI_BIT_RATE_CONTROL_REG SPI_MEM_MAP_VALUE(0x08) +#define SPI_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x0C) +#define SPI_TRANSMIT_BUFFER_REG SPI_MEM_MAP_VALUE(0x10) +#define SPI_RECEIVE_CONTROL_REG SPI_MEM_MAP_VALUE(0x14) +#define SPI_RECEIVE_BUFFER_REG SPI_MEM_MAP_VALUE(0x18) +#define SPI_FIFO_TRANSMIT_CONFIG_REG SPI_MEM_MAP_VALUE(0x1C) +#define SPI_FIFO_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x20) +#define SPI_FIFO_RECEIVE_CONFIG_REG SPI_MEM_MAP_VALUE(0x24) +#define SPI_INTERRUPT_STATUS_REG SPI_MEM_MAP_VALUE(0x28) +#define SPI_INTERRUPT_ENABLE_REG SPI_MEM_MAP_VALUE(0x2C) + +#define SPI_TRANSMIT_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x10) +#define SPI_RECEIVE_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x18) + +/* Structure for SPI controller of CNS3XXX SOCs */ +struct cns3xxx_spi { + /* bitbang has to be first */ + struct spi_bitbang bitbang; + struct completion done; + wait_queue_head_t wait; + + int len; + int count; + int last_in_message_list; + + /* data buffers */ + const unsigned char *tx; + unsigned char *rx; + + void __iomem *base; + struct spi_master *master; + struct platform_device *pdev; + struct device *dev; +}; + +static inline u8 cns3xxx_spi_bus_idle(struct cns3xxx_spi *hw) +{ + return ((SPI_SERVICE_STATUS_REG & 0x1) ? 0 : 1); +} + +static inline u8 cns3xxx_spi_tx_buffer_empty(struct cns3xxx_spi *hw) +{ + return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 3)) ? 1 : 0); +} + +static inline u8 cns3xxx_spi_rx_buffer_full(struct cns3xxx_spi *hw) +{ + return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 2)) ? 1 : 0); +} + +u8 cns3xxx_spi_tx_rx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof, + u32 tx_data, u32 * rx_data) +{ + u8 rx_channel; + u8 rx_eof; + + while (!cns3xxx_spi_bus_idle(hw)) ; // do nothing + + while (!cns3xxx_spi_tx_buffer_empty(hw)) ; // do nothing + + SPI_TRANSMIT_CONTROL_REG &= ~(0x7); + SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2); + + SPI_TRANSMIT_BUFFER_REG = tx_data; + + while (!cns3xxx_spi_rx_buffer_full(hw)) ; // do nothing + + rx_channel = SPI_RECEIVE_CONTROL_REG & 0x3; + rx_eof = (SPI_RECEIVE_CONTROL_REG & (0x1 << 2)) ? 1 : 0; + + *rx_data = SPI_RECEIVE_BUFFER_REG; + + if ((tx_channel != rx_channel) || (tx_eof != rx_eof)) { + return 0; + } else { + return 1; + } +} + +u8 cns3xxx_spi_tx(struct cns3xxx_spi *hw, u8 tx_channel, u8 tx_eof, u32 tx_data) +{ + + while (!cns3xxx_spi_bus_idle(hw)) ; // do nothing + + while (!cns3xxx_spi_tx_buffer_empty(hw)) ; // do nothing + + SPI_TRANSMIT_CONTROL_REG &= ~(0x7); + SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2); + + SPI_TRANSMIT_BUFFER_REG = tx_data; + + return 1; +} + +static inline struct cns3xxx_spi *to_hw(struct spi_device *sdev) +{ + return spi_master_get_devdata(sdev->master); +} + +static int cns3xxx_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) +{ + return 0; +} + +static void cns3xxx_spi_chipselect(struct spi_device *spi, int value) +{ + struct cns3xxx_spi *hw = to_hw(spi); + unsigned int spi_config; + + switch (value) { + case BITBANG_CS_INACTIVE: + break; + + case BITBANG_CS_ACTIVE: + spi_config = SPI_CONFIGURATION_REG; + + if (spi->mode & SPI_CPHA) + spi_config |= (0x1 << 13); + else + spi_config &= ~(0x1 << 13); + + if (spi->mode & SPI_CPOL) + spi_config |= (0x1 << 14); + else + spi_config &= ~(0x1 << 14); + + /* write new configration */ + SPI_CONFIGURATION_REG = spi_config; + + SPI_TRANSMIT_CONTROL_REG &= ~(0x7); + SPI_TRANSMIT_CONTROL_REG |= (spi->chip_select & 0x3); + + break; + } +} + +static int cns3xxx_spi_setup(struct spi_device *spi) +{ + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + return 0; +} + +static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) +{ + struct cns3xxx_spi *hw = to_hw(spi); + + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", t->tx_buf, t->rx_buf, + t->len); + + hw->tx = t->tx_buf; + hw->rx = t->rx_buf; + hw->len = t->len; + hw->count = 0; + hw->last_in_message_list = t->last_in_message_list; + + init_completion(&hw->done); + + if (hw->tx) { + int i; + u32 rx_data; + for (i = 0; i < (hw->len - 1); i++) { + dev_dbg(&spi->dev, + "[SPI_CNS3XXX_DEBUG] hw->tx[%02d]: 0x%02x\n", i, + hw->tx[i]); + cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i], + &rx_data); + if (hw->rx) { + hw->rx[i] = rx_data; + dev_dbg(&spi->dev, + "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", + i, hw->rx[i]); + } + } + + if (t->last_in_message_list) { + cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, hw->tx[i], + &rx_data); + if (hw->rx) { + hw->rx[i] = rx_data; + dev_dbg(&spi->dev, + "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", + i, hw->rx[i]); + } + } else { + cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, hw->tx[i], + &rx_data); + } + goto done; + } + + if (hw->rx) { + int i; + u32 rx_data; + for (i = 0; i < (hw->len - 1); i++) { + cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data); + hw->rx[i] = rx_data; + dev_dbg(&spi->dev, + "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", i, + hw->rx[i]); + } + + if (t->last_in_message_list) { + cns3xxx_spi_tx_rx(hw, spi->chip_select, 1, 0xff, &rx_data); + } else { + cns3xxx_spi_tx_rx(hw, spi->chip_select, 0, 0xff, &rx_data); + } + hw->rx[i] = rx_data; + dev_dbg(&spi->dev, "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", + i, hw->rx[i]); + } +done: + return hw->len; +} + +static void __init cns3xxx_spi_initial(struct cns3xxx_spi *hw) +{ + SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) | /* 8bits shift length */ + (0x0 << 9) | /* SPI mode */ + (0x0 << 10) | /* disable FIFO */ + (0x1 << 11) | /* SPI master mode */ + (0x0 << 12) | /* disable SPI loopback mode */ + (0x1 << 13) | /* clock phase */ + (0x1 << 14) | /* clock polarity */ + (0x0 << 24) | /* disable - SPI data swap */ + (0x1 << 29) | /* enable - 2IO Read mode */ + (0x0 << 30) | /* disable - SPI high speed read for system boot up */ + (0x0 << 31)); /* disable - SPI */ + + /* Set SPI bit rate PCLK/2 */ + SPI_BIT_RATE_CONTROL_REG = 0x1; + + /* Set SPI Tx channel 0 */ + SPI_TRANSMIT_CONTROL_REG = 0x0; + + /* Set Tx FIFO Threshold, Tx FIFO has 2 words */ + SPI_FIFO_TRANSMIT_CONFIG_REG &= ~(0x03 << 4); + SPI_FIFO_TRANSMIT_CONFIG_REG |= ((0x0 & 0x03) << 4); + + /* Set Rx FIFO Threshold, Rx FIFO has 2 words */ + SPI_FIFO_RECEIVE_CONFIG_REG &= ~(0x03 << 4); + SPI_FIFO_RECEIVE_CONFIG_REG |= ((0x0 & 0x03) << 4); + + /* Disable all interrupt */ + SPI_INTERRUPT_ENABLE_REG = 0x0; + + /* Clear spurious interrupt sources */ + SPI_INTERRUPT_STATUS_REG = (0x0F << 4); + + /* Enable SPI */ + SPI_CONFIGURATION_REG |= (0x1 << 31); + + return; +} + +static int cns3xxx_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct cns3xxx_spi *hw; + struct resource *res; + int err = 0; + + printk("%s: setup CNS3XXX SPI Controller\n", __FUNCTION__); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + /* Allocate master with space for cns3xxx_spi */ + master = spi_alloc_master(&pdev->dev, sizeof(struct cns3xxx_spi)); + if (master == NULL) { + dev_err(&pdev->dev, "No memory for spi_master\n"); + err = -ENOMEM; + goto err_nomem; + } + + hw = spi_master_get_devdata(master); + memset(hw, 0, sizeof(struct cns3xxx_spi)); + + hw->master = spi_master_get(master); + hw->dev = &pdev->dev; + + hw->base = devm_ioremap_resource(hw->dev, res); + if (IS_ERR(hw->base)) { + dev_err(hw->dev, "Unable to map registers\n"); + err = PTR_ERR(hw->base); + goto err_register; + } + + platform_set_drvdata(pdev, hw); + init_completion(&hw->done); + + /* setup the master state. */ + + master->num_chipselect = 4; + master->bus_num = 1; + + /* setup the state for the bitbang driver */ + + hw->bitbang.master = hw->master; + hw->bitbang.setup_transfer = cns3xxx_spi_setup_transfer; + hw->bitbang.chipselect = cns3xxx_spi_chipselect; + hw->bitbang.txrx_bufs = cns3xxx_spi_txrx; + hw->bitbang.master->setup = cns3xxx_spi_setup; + + dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); + + /* SPI controller initializations */ + cns3xxx_spi_initial(hw); + + /* register SPI controller */ + + err = spi_bitbang_start(&hw->bitbang); + if (err) { + dev_err(&pdev->dev, "Failed to register SPI master\n"); + goto err_register; + } + + return 0; + +err_register: + spi_master_put(hw->master);; + +err_nomem: + return err; +} + +static int cns3xxx_spi_remove(struct platform_device *dev) +{ + struct cns3xxx_spi *hw = platform_get_drvdata(dev); + + platform_set_drvdata(dev, NULL); + + spi_unregister_master(hw->master); + + spi_master_put(hw->master); + return 0; +} + +#ifdef CONFIG_PM + +static int cns3xxx_spi_suspend(struct platform_device *pdev, pm_message_t msg) +{ + struct cns3xxx_spi *hw = platform_get_drvdata(pdev); + + return 0; +} + +static int cns3xxx_spi_resume(struct platform_device *pdev) +{ + struct cns3xxx_spi *hw = platform_get_drvdata(pdev); + + return 0; +} + +#else +#define cns3xxx_spi_suspend NULL +#define cns3xxx_spi_resume NULL +#endif + +static struct platform_driver cns3xxx_spi_driver = { + .probe = cns3xxx_spi_probe, + .remove = cns3xxx_spi_remove, + .suspend = cns3xxx_spi_suspend, + .resume = cns3xxx_spi_resume, + .driver = { + .name = "cns3xxx_spi", + .owner = THIS_MODULE, + }, +}; + +static int __init cns3xxx_spi_init(void) +{ + return platform_driver_register(&cns3xxx_spi_driver); +} + +static void __exit cns3xxx_spi_exit(void) +{ + platform_driver_unregister(&cns3xxx_spi_driver); +} + +module_init(cns3xxx_spi_init); +module_exit(cns3xxx_spi_exit); + +MODULE_AUTHOR("Cavium Networks"); +MODULE_DESCRIPTION("CNS3XXX SPI Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:cns3xxx_spi"); + +EXPORT_SYMBOL_GPL(cns3xxx_spi_tx_rx); diff --git a/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h b/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h new file mode 100644 index 0000000..f286d0d --- /dev/null +++ b/target/linux/cns3xxx/files/include/linux/platform_data/cns3xxx.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-cns3xxx/include/mach/platform.h + * + * Copyright 2011 Gateworks Corporation + * Chris Lang $(BIN_DIR)/$(IMG_PREFIX)-$(1).bin +endef + +define Image/Build/jffs2-128k + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync + ( \ + dd if=$(KDIR)/uImage bs=2048k conv=sync; \ + dd if=$(KDIR)/root.$(1) bs=128k conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).bin +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync + ( \ + dd if=$(KDIR)/uImage bs=2048k conv=sync; \ + dd if=$(KDIR)/root.$(1) bs=128k conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-$(1)_laguna_nor.bin + ( \ + dd if=$(KDIR)/uImage bs=1536k conv=sync; \ + dd if=$(KDIR)/root.$(1) bs=256k conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-$(1)_laguna_spi.bin +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/cns3xxx/patches-3.18/000-cns3xxx_arch_include.patch b/target/linux/cns3xxx/patches-3.18/000-cns3xxx_arch_include.patch new file mode 100644 index 0000000..f98fe0c --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/000-cns3xxx_arch_include.patch @@ -0,0 +1,8 @@ +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,3 +1,5 @@ ++ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include ++ + obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o + cns3xxx-y += core.o pm.o + cns3xxx-$(CONFIG_ATAGS) += devices.o diff --git a/target/linux/cns3xxx/patches-3.18/001-cns3xxx_section_fix.patch b/target/linux/cns3xxx/patches-3.18/001-cns3xxx_section_fix.patch new file mode 100644 index 0000000..ba0e725 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/001-cns3xxx_section_fix.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -339,7 +339,7 @@ static struct usb_ohci_pdata cns3xxx_usb + .power_off = csn3xxx_usb_power_off, + }; + +-static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { ++static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { + { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, + { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, + { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, diff --git a/target/linux/cns3xxx/patches-3.18/010-arm_introduce-dma-fiq-irq-broadcast.patch b/target/linux/cns3xxx/patches-3.18/010-arm_introduce-dma-fiq-irq-broadcast.patch new file mode 100644 index 0000000..dd02323 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/010-arm_introduce-dma-fiq-irq-broadcast.patch @@ -0,0 +1,64 @@ +--- a/arch/arm/include/asm/glue-cache.h ++++ b/arch/arm/include/asm/glue-cache.h +@@ -156,11 +156,19 @@ static inline void nop_dma_unmap_area(co + #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) + #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) + #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) ++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST + #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) + + #define dmac_map_area __glue(_CACHE,_dma_map_area) + #define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) + #define dmac_flush_range __glue(_CACHE,_dma_flush_range) ++#else ++#define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area) ++ ++#define dmac_map_area __glue(fiq,_dma_map_area) ++#define dmac_unmap_area __glue(fiq,_dma_unmap_area) ++#define dmac_flush_range __glue(fiq,_dma_flush_range) ++#endif /* CONFIG_DMA_CACHE_FIQ_BROADCAST */ + #endif + + #endif +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -844,6 +844,17 @@ config DMA_CACHE_RWFO + in hardware, other workarounds are needed (e.g. cache + maintenance broadcasting in software via FIQ). + ++config DMA_CACHE_FIQ_BROADCAST ++ bool "Enable fiq broadcast DMA cache maintenance" ++ depends on CPU_V6K && SMP ++ select FIQ ++ help ++ The Snoop Control Unit on ARM11MPCore does not detect the ++ cache maintenance operations and the dma_{map,unmap}_area() ++ functions may leave stale cache entries on other CPUs. By ++ enabling this option, fiq broadcast in the ARMv6 ++ DMA cache maintenance functions is performed. ++ + config OUTER_CACHE + bool + +--- a/arch/arm/mm/flush.c ++++ b/arch/arm/mm/flush.c +@@ -304,6 +304,7 @@ void __sync_icache_dcache(pte_t pteval) + void flush_dcache_page(struct page *page) + { + struct address_space *mapping; ++ bool skip_broadcast = true; + + /* + * The zero page is never written to, so never has any dirty +@@ -314,7 +315,10 @@ void flush_dcache_page(struct page *page + + mapping = page_mapping(page); + +- if (!cache_ops_need_broadcast() && ++#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST ++ skip_broadcast = !cache_ops_need_broadcast(); ++#endif ++ if (skip_broadcast && + mapping && !page_mapped(page)) + clear_bit(PG_dcache_clean, &page->flags); + else { diff --git a/target/linux/cns3xxx/patches-3.18/020-watchdog_support.patch b/target/linux/cns3xxx/patches-3.18/020-watchdog_support.patch new file mode 100644 index 0000000..74ffcc3 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/020-watchdog_support.patch @@ -0,0 +1,59 @@ +1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog + since the CNS3xxx SOCs have ARM11 MPcore CPU. +2. Enable mpcore_watchdog option as module to default configuration at + arch/arm/configs/cns3420vb_defconfig. + +Signed-off-by: Tommy Lin + +--- +arch/arm/Kconfig | 1 + + arch/arm/configs/cns3420vb_defconfig | 2 ++ + arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++ + 3 files changed, 25 insertions(+), 0 deletions(-) + +--- a/arch/arm/configs/cns3420vb_defconfig ++++ b/arch/arm/configs/cns3420vb_defconfig +@@ -56,6 +56,8 @@ CONFIG_LEGACY_PTY_COUNT=16 + # CONFIG_HW_RANDOM is not set + # CONFIG_HWMON is not set + # CONFIG_VGA_CONSOLE is not set ++CONFIG_WATCHDOG=y ++CONFIG_MPCORE_WATCHDOG=m + # CONFIG_HID_SUPPORT is not set + # CONFIG_USB_SUPPORT is not set + CONFIG_MMC=y +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -206,10 +206,32 @@ static struct platform_device cns3xxx_us + }, + }; + ++/* Watchdog */ ++static struct resource cns3xxx_watchdog_resources[] = { ++ [0] = { ++ .start = CNS3XXX_TC11MP_TWD_BASE, ++ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_LOCALWDOG, ++ .end = IRQ_LOCALWDOG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device cns3xxx_watchdog_device = { ++ .name = "mpcore_wdt", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources), ++ .resource = cns3xxx_watchdog_resources, ++}; ++ + /* + * Initialization + */ + static struct platform_device *cns3420_pdevs[] __initdata = { ++ &cns3xxx_watchdog_device, + &cns3420_nor_pdev, + &cns3xxx_usb_ehci_device, + &cns3xxx_usb_ohci_device, diff --git a/target/linux/cns3xxx/patches-3.18/025-smp_support.patch b/target/linux/cns3xxx/patches-3.18/025-smp_support.patch new file mode 100644 index 0000000..418c065 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/025-smp_support.patch @@ -0,0 +1,30 @@ +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -5,3 +5,5 @@ cns3xxx-y += core.o pm.o + cns3xxx-$(CONFIG_ATAGS) += devices.o + cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o ++cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o ++cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -2,6 +2,9 @@ menuconfig ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6 + select ARM_GIC + select PCI_DOMAINS if PCI ++ select HAVE_ARM_SCU if SMP ++ select HAVE_ARM_TWD if LOCAL_TIMERS ++ select HAVE_SMP + help + Support for Cavium Networks CNS3XXX platform. + +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -13,6 +13,7 @@ + + #include + ++extern struct smp_operations cns3xxx_smp_ops; + extern void cns3xxx_timer_init(void); + + #ifdef CONFIG_CACHE_L2X0 diff --git a/target/linux/cns3xxx/patches-3.18/030-pcie_clock.patch b/target/linux/cns3xxx/patches-3.18/030-pcie_clock.patch new file mode 100644 index 0000000..45c73cb --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/030-pcie_clock.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -331,8 +331,6 @@ void __init cns3xxx_pcie_init_late(void) + "imprecise external abort"); + + for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { +- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); +- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); + cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); + cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); + pci_common_init(&cns3xxx_pcie[i].hw_pci); diff --git a/target/linux/cns3xxx/patches-3.18/031-pcie_init.patch b/target/linux/cns3xxx/patches-3.18/031-pcie_init.patch new file mode 100644 index 0000000..3c739c5 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/031-pcie_init.patch @@ -0,0 +1,33 @@ +--- a/arch/arm/mach-cns3xxx/laguna.c ++++ b/arch/arm/mach-cns3xxx/laguna.c +@@ -849,7 +849,6 @@ static struct map_desc laguna_io_desc[] + static void __init laguna_map_io(void) + { + cns3xxx_map_io(); +- cns3xxx_pcie_iotable_init(); + iotable_init(ARRAY_AND_SIZE(laguna_io_desc)); + laguna_early_serial_setup(); + } +@@ -873,15 +872,6 @@ static int laguna_register_gpio(struct g + return ret; + } + +-static int __init laguna_pcie_init(void) +-{ +- if (!machine_is_gw2388()) +- return 0; +- +- return cns3xxx_pcie_init(); +-} +-subsys_initcall(laguna_pcie_init); +- + static int __init laguna_model_setup(void) + { + u32 __iomem *mem; +@@ -1075,5 +1065,6 @@ MACHINE_START(GW2388, "Gateworks Corpora + .init_irq = cns3xxx_init_irq, + .init_time = cns3xxx_timer_init, + .init_machine = laguna_init, ++ .init_late = cns3xxx_pcie_init_late, + .restart = cns3xxx_restart, + MACHINE_END diff --git a/target/linux/cns3xxx/patches-3.18/040-fiq_support.patch b/target/linux/cns3xxx/patches-3.18/040-fiq_support.patch new file mode 100644 index 0000000..4f09a36 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/040-fiq_support.patch @@ -0,0 +1,40 @@ +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -5,6 +5,7 @@ menuconfig ARCH_CNS3XXX + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_SMP ++ select FIQ + help + Support for Cavium Networks CNS3XXX platform. + +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -5,5 +5,5 @@ cns3xxx-y += core.o pm.o + cns3xxx-$(CONFIG_ATAGS) += devices.o + cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +-cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o ++cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o + cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o +--- a/arch/arm/mach-cns3xxx/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/cns3xxx.h +@@ -267,6 +267,7 @@ + #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) + #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) + ++#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4) + /* + * Power management and clock control + */ +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -827,7 +827,7 @@ config KUSER_HELPERS + + config DMA_CACHE_RWFO + bool "Enable read/write for ownership DMA cache maintenance" +- depends on CPU_V6K && SMP ++ depends on CPU_V6K && SMP && !ARCH_CNS3XXX + default y + help + The Snoop Control Unit on ARM11MPCore does not detect the diff --git a/target/linux/cns3xxx/patches-3.18/045-twd_base.patch b/target/linux/cns3xxx/patches-3.18/045-twd_base.patch new file mode 100644 index 0000000..f61b8ed --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/045-twd_base.patch @@ -0,0 +1,45 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -26,6 +27,8 @@ + #include "core.h" + #include "pm.h" + ++#define IRQ_LOCALTIMER 29 ++ + static struct map_desc cns3xxx_io_desc[] __initdata = { + { + .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, +@@ -191,6 +194,17 @@ static struct irqaction cns3xxx_timer_ir + .handler = cns3xxx_timer_interrupt, + }; + ++static void __init cns3xxx_init_twd(void) ++{ ++#ifdef CONFIG_LOCAL_TIMERS ++ static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer, ++ CNS3XXX_TC11MP_TWD_BASE, ++ IRQ_LOCALTIMER); ++ ++ twd_local_timer_register(&cns3xx_twd_local_timer); ++#endif ++} ++ + /* + * Set up the clock source and clock events devices + */ +@@ -244,6 +258,7 @@ static void __init __cns3xxx_timer_init( + setup_irq(timer_irq, &cns3xxx_timer_irq); + + cns3xxx_clockevents_init(timer_irq); ++ cns3xxx_init_twd(); + } + + void __init cns3xxx_timer_init(void) diff --git a/target/linux/cns3xxx/patches-3.18/055-pcie_io.patch b/target/linux/cns3xxx/patches-3.18/055-pcie_io.patch new file mode 100644 index 0000000..4680853 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/055-pcie_io.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -81,6 +81,16 @@ static struct map_desc cns3xxx_io_desc[] + .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), + .length = SZ_16M, + .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE), ++ .length = SZ_16M, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE), ++ .length = SZ_16M, ++ .type = MT_DEVICE, + #endif + }, + }; diff --git a/target/linux/cns3xxx/patches-3.18/060-pcie_abort.patch b/target/linux/cns3xxx/patches-3.18/060-pcie_abort.patch new file mode 100644 index 0000000..d72629f --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/060-pcie_abort.patch @@ -0,0 +1,129 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -88,6 +88,79 @@ static void __iomem *cns3xxx_pci_cfg_bas + return base + (where & 0xffc) + (devfn << 12); + } + ++static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where) ++{ ++ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); ++ ++ /* check PCI-compatible status register after access */ ++ if (cnspci->linked) { ++ void __iomem *host_base; ++ u32 sreg, ereg; ++ ++ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual; ++ sreg = __raw_readw(host_base + 0x6) & 0xF900; ++ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg ++ ++ if (sreg | ereg) { ++ /* SREG: ++ * BIT15 - Detected Parity Error ++ * BIT14 - Signaled System Error ++ * BIT13 - Received Master Abort ++ * BIT12 - Received Target Abort ++ * BIT11 - Signaled Target Abort ++ * BIT08 - Master Data Parity Error ++ * ++ * EREG: ++ * BIT20 - Unsupported Request ++ * BIT19 - ECRC ++ * BIT18 - Malformed TLP ++ * BIT17 - Receiver Overflow ++ * BIT16 - Unexpected Completion ++ * BIT15 - Completer Abort ++ * BIT14 - Completion Timeout ++ * BIT13 - Flow Control Protocol Error ++ * BIT12 - Poisoned TLP ++ * BIT04 - Data Link Protocol Error ++ * ++ * TODO: see Documentation/pci-error-recovery.txt ++ * implement error_detected handler ++ */ ++/* ++ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg); ++ if (sreg & BIT(15)) printk(" SERR"); ++ if (sreg & BIT(13)) printk(" TABRT"); ++ if (sreg & BIT( 8)) printk(" MPERR"); ++ ++ if (ereg & BIT(20)) printk(" Unsup"); ++ if (ereg & BIT(19)) printk(" ECRC"); ++ if (ereg & BIT(18)) printk(" MTLP"); ++ if (ereg & BIT(17)) printk(" OFLOW"); ++ if (ereg & BIT(16)) printk(" Unex"); ++ if (ereg & BIT(15)) printk(" ABRT"); ++ if (ereg & BIT(14)) printk(" COMPTO"); ++ if (ereg & BIT(13)) printk(" FLOW"); ++ if (ereg & BIT(12)) printk(" PTLP"); ++ if (ereg & BIT( 4)) printk(" DLINK"); ++ printk("\n"); ++*/ ++ pr_debug("%s failed port%d sreg=0x%04x\n", __func__, ++ cnspci->hw_pci.domain, sreg); ++ ++ /* make sure the status bits are reset */ ++ __raw_writew(sreg, host_base + 6); ++ __raw_writel(ereg, host_base + 0x104); ++ return 1; ++ } ++ } ++ else ++ return 1; ++ ++ return 0; ++} ++ + static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) + { +@@ -104,6 +177,11 @@ static int cns3xxx_pci_read_config(struc + + v = __raw_readl(base); + ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ + if (bus->number == 0 && devfn == 0 && + (where & 0xffc) == PCI_CLASS_REVISION) { + /* +@@ -133,11 +211,19 @@ static int cns3xxx_pci_write_config(stru + return PCIBIOS_SUCCESSFUL; + + v = __raw_readl(base); ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } + + v &= ~(mask << shift); + v |= (val & mask) << shift; + + __raw_writel(v, base); ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on write\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } + + return PCIBIOS_SUCCESSFUL; + } +@@ -315,8 +401,14 @@ static void __init cns3xxx_pcie_hw_init( + static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) + { ++#if 0 ++/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE ++ * ignore imprecise aborts and use PCI-compatible Status register to ++ * determine errors instead ++ */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; ++#endif + return 0; + } + diff --git a/target/linux/cns3xxx/patches-3.18/065-pcie_skip_inactive.patch b/target/linux/cns3xxx/patches-3.18/065-pcie_skip_inactive.patch new file mode 100644 index 0000000..837fc87 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/065-pcie_skip_inactive.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -424,6 +424,8 @@ void __init cns3xxx_pcie_init_late(void) + + for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { + cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); ++ if (!cns3xxx_pcie[i].linked) ++ continue; + cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); + pci_common_init(&cns3xxx_pcie[i].hw_pci); + } diff --git a/target/linux/cns3xxx/patches-3.18/070-i2c_support.patch b/target/linux/cns3xxx/patches-3.18/070-i2c_support.patch new file mode 100644 index 0000000..ff6be6a --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/070-i2c_support.patch @@ -0,0 +1,31 @@ +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -417,6 +417,18 @@ config I2C_CBUS_GPIO + This driver can also be built as a module. If so, the module + will be called i2c-cbus-gpio. + ++config I2C_CNS3XXX ++ tristate "Cavium CNS3xxx I2C driver" ++ depends on ARCH_CNS3XXX ++ help ++ Support for Cavium CNS3xxx I2C controller driver. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-cns3xxx. ++ ++ Please note that this driver might be needed to bring up other ++ devices such as Cavium CNS3xxx Ethernet. ++ + config I2C_CPM + tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)" + depends on CPM1 || CPM2 +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c- + obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o + obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o + obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o ++obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o + obj-$(CONFIG_SCx200_ACB) += scx200_acb.o + + ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG diff --git a/target/linux/cns3xxx/patches-3.18/075-spi_support.patch b/target/linux/cns3xxx/patches-3.18/075-spi_support.patch new file mode 100644 index 0000000..da6dcd4 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/075-spi_support.patch @@ -0,0 +1,55 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -171,6 +171,13 @@ config SPI_CLPS711X + This enables dedicated general purpose SPI/Microwire1-compatible + master mode interface (SSI1) for CLPS711X-based CPUs. + ++config SPI_CNS3XXX ++ tristate "CNS3XXX SPI controller" ++ depends on ARCH_CNS3XXX && SPI_MASTER ++ select SPI_BITBANG ++ help ++ This enables using the CNS3XXX SPI controller in master mode. ++ + config SPI_COLDFIRE_QSPI + tristate "Freescale Coldfire QSPI controller" + depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x) +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi-bitban + obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o + obj-$(CONFIG_SPI_CADENCE) += spi-cadence.o + obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o ++obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o + obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o + obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o + obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o +--- a/drivers/spi/spi-bitbang.c ++++ b/drivers/spi/spi-bitbang.c +@@ -335,6 +335,10 @@ static int spi_bitbang_transfer_one(stru + */ + if (!m->is_dma_mapped) + t->rx_dma = t->tx_dma = 0; ++ ++ t->last_in_message_list = ++ list_is_last(&t->transfer_list, &m->transfers); ++ + status = bitbang->txrx_bufs(spi, t); + } + if (status > 0) +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -630,6 +630,13 @@ struct spi_transfer { + u32 speed_hz; + + struct list_head transfer_list; ++ ++#ifdef CONFIG_ARCH_CNS3XXX ++ unsigned last_in_message_list; ++#ifdef CONFIG_SPI_CNS3XXX_2IOREAD ++ u8 dio_read; ++#endif ++#endif + }; + + /** diff --git a/target/linux/cns3xxx/patches-3.18/080-sata_support.patch b/target/linux/cns3xxx/patches-3.18/080-sata_support.patch new file mode 100644 index 0000000..c619787 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/080-sata_support.patch @@ -0,0 +1,26 @@ +--- a/drivers/ata/ahci_platform.c ++++ b/drivers/ata/ahci_platform.c +@@ -29,12 +29,23 @@ static const struct ata_port_info ahci_p + .port_ops = &ahci_platform_ops, + }; + ++static const struct ata_port_info cns3xxx_port_info = { ++ .flags = AHCI_FLAG_COMMON, ++ .pio_mask = ATA_PIO4, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &ahci_pmp_retry_srst_ops, ++}; ++ + static int ahci_probe(struct platform_device *pdev) + { + struct device *dev = &pdev->dev; + struct ahci_host_priv *hpriv; ++ const struct ata_port_info *info = &ahci_port_info; + int rc; + ++ if (IS_ENABLED(CONFIG_ARCH_CNS3XXX)) ++ info = &cns3xxx_port_info; ++ + hpriv = ahci_platform_get_resources(pdev); + if (IS_ERR(hpriv)) + return PTR_ERR(hpriv); diff --git a/target/linux/cns3xxx/patches-3.18/085-ethernet_support.patch b/target/linux/cns3xxx/patches-3.18/085-ethernet_support.patch new file mode 100644 index 0000000..258423a --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/085-ethernet_support.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -34,6 +34,7 @@ source "drivers/net/ethernet/adi/Kconfig + source "drivers/net/ethernet/broadcom/Kconfig" + source "drivers/net/ethernet/brocade/Kconfig" + source "drivers/net/ethernet/calxeda/Kconfig" ++source "drivers/net/ethernet/cavium/Kconfig" + source "drivers/net/ethernet/chelsio/Kconfig" + source "drivers/net/ethernet/cirrus/Kconfig" + source "drivers/net/ethernet/cisco/Kconfig" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_NET_BFIN) += adi/ + obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/ + obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/ + obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/ ++obj-$(CONFIG_NET_VENDOR_CAVIUM) += cavium/ + obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/ + obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/ + obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/ diff --git a/target/linux/cns3xxx/patches-3.18/090-timers.patch b/target/linux/cns3xxx/patches-3.18/090-timers.patch new file mode 100644 index 0000000..a884021 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/090-timers.patch @@ -0,0 +1,104 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -135,12 +135,13 @@ static void cns3xxx_timer_set_mode(enum + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: +- reload = pclk * 20 / (3 * HZ) * 0x25000; ++ reload = pclk * 1000000 / HZ; + writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + ctrl |= (1 << 0) | (1 << 2) | (1 << 9); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ ++ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + ctrl |= (1 << 2) | (1 << 9); + break; + case CLOCK_EVT_MODE_UNUSED: +@@ -168,7 +169,7 @@ static struct clock_event_device cns3xxx + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = cns3xxx_timer_set_mode, + .set_next_event = cns3xxx_timer_set_next_event, +- .rating = 350, ++ .rating = 300, + .cpumask = cpu_all_mask, + }; + +@@ -215,6 +216,35 @@ static void __init cns3xxx_init_twd(void + #endif + } + ++static cycle_t cns3xxx_get_cycles(struct clocksource *cs) ++{ ++ u64 val; ++ ++ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); ++ val &= 0xffff; ++ ++ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET)); ++} ++ ++static struct clocksource clocksource_cns3xxx = { ++ .name = "freerun", ++ .rating = 200, ++ .read = cns3xxx_get_cycles, ++ .mask = CLOCKSOURCE_MASK(48), ++ .shift = 16, ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++static void __init cns3xxx_clocksource_init(void) ++{ ++ /* Reset the FreeRunning counter */ ++ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); ++ ++ clocksource_cns3xxx.mult = ++ clocksource_khz2mult(100, clocksource_cns3xxx.shift); ++ clocksource_register(&clocksource_cns3xxx); ++} ++ + /* + * Set up the clock source and clock events devices + */ +@@ -232,13 +262,12 @@ static void __init __cns3xxx_timer_init( + /* stop free running timer3 */ + writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); + +- /* timer1 */ +- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); +- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); +- + writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); + writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); + ++ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ; ++ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); ++ + /* mask irq, non-mask timer1 overflow */ + irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); + irq_mask &= ~(1 << 2); +@@ -250,23 +279,9 @@ static void __init __cns3xxx_timer_init( + val |= (1 << 9); + writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + +- /* timer2 */ +- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); +- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); +- +- /* mask irq */ +- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); +- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); +- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); +- +- /* down counter */ +- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); +- val |= (1 << 10); +- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); +- +- /* Make irqs happen for the system timer */ + setup_irq(timer_irq, &cns3xxx_timer_irq); + ++ cns3xxx_clocksource_init(); + cns3xxx_clockevents_init(timer_irq); + cns3xxx_init_twd(); + } diff --git a/target/linux/cns3xxx/patches-3.18/095-gpio_support.patch b/target/linux/cns3xxx/patches-3.18/095-gpio_support.patch new file mode 100644 index 0000000..a6ce177 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/095-gpio_support.patch @@ -0,0 +1,67 @@ +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -245,6 +245,10 @@ static void __init cns3420_init(void) + + cns3xxx_ahci_init(); + cns3xxx_sdhci_init(); ++ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, ++ NR_IRQS_CNS3XXX); ++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, ++ NR_IRQS_CNS3XXX + 32); + + pm_power_off = cns3xxx_power_off; + } +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -1,6 +1,8 @@ + menuconfig ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6 + select ARM_GIC ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_IRQ_CHIP + select PCI_DOMAINS if PCI + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD if LOCAL_TIMERS +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,7 +1,7 @@ + ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include + + obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o +-cns3xxx-y += core.o pm.o ++cns3xxx-y += core.o pm.o gpio.o + cns3xxx-$(CONFIG_ATAGS) += devices.o + cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +--- a/arch/arm/mach-cns3xxx/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/cns3xxx.h +@@ -68,8 +68,10 @@ + #define SMC_PCELL_ID_3_OFFSET 0xFFC + + #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ ++#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000 + + #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ ++#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000 + + #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ + +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[] + .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), + .length = SZ_4K, + .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_GPIOA_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_GPIOB_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE, + #ifdef CONFIG_PCI + }, { + .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, diff --git a/target/linux/cns3xxx/patches-3.18/097-l2x0_cmdline_disable.patch b/target/linux/cns3xxx/patches-3.18/097-l2x0_cmdline_disable.patch new file mode 100644 index 0000000..f575348 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/097-l2x0_cmdline_disable.patch @@ -0,0 +1,69 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -305,13 +305,26 @@ void __init cns3xxx_timer_init(void) + + #ifdef CONFIG_CACHE_L2X0 + +-void __init cns3xxx_l2x0_init(void) ++static int cns3xxx_l2x0_enable = 1; ++ ++static int __init cns3xxx_l2x0_disable(char *s) ++{ ++ cns3xxx_l2x0_enable = 0; ++ return 1; ++} ++__setup("nol2x0", cns3xxx_l2x0_disable); ++ ++static int __init cns3xxx_l2x0_init(void) + { +- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); ++ void __iomem *base; + u32 val; + ++ if (!cns3xxx_l2x0_enable) ++ return 0; ++ ++ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); + if (WARN_ON(!base)) +- return; ++ return 0; + + /* + * Tag RAM Control register +@@ -341,7 +354,10 @@ void __init cns3xxx_l2x0_init(void) + + /* 32 KiB, 8-way, parity disable */ + l2x0_init(base, 0x00500000, 0xfe0f0fff); ++ ++ return 0; + } ++arch_initcall(cns3xxx_l2x0_init); + + #endif /* CONFIG_CACHE_L2X0 */ + +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -239,8 +239,6 @@ static struct platform_device *cns3420_p + + static void __init cns3420_init(void) + { +- cns3xxx_l2x0_init(); +- + platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); + + cns3xxx_ahci_init(); +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -16,12 +16,6 @@ + extern struct smp_operations cns3xxx_smp_ops; + extern void cns3xxx_timer_init(void); + +-#ifdef CONFIG_CACHE_L2X0 +-void __init cns3xxx_l2x0_init(void); +-#else +-static inline void cns3xxx_l2x0_init(void) {} +-#endif /* CONFIG_CACHE_L2X0 */ +- + #ifdef CONFIG_PCI + extern void __init cns3xxx_pcie_init_late(void); + #else diff --git a/target/linux/cns3xxx/patches-3.18/100-laguna_support.patch b/target/linux/cns3xxx/patches-3.18/100-laguna_support.patch new file mode 100644 index 0000000..3c0bba4 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/100-laguna_support.patch @@ -0,0 +1,46 @@ +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -22,4 +22,12 @@ config MACH_CNS3420VB + This is a platform with an on-board ARM11 MPCore and has support + for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. + ++config MACH_GW2388 ++ bool "Support for Gateworks Laguna Platform" ++ help ++ Include support for the Gateworks Laguna Platform ++ ++ This is a platform with an on-board ARM11 MPCore and has support ++ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc. ++ + endif +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -7,3 +7,5 @@ cns3xxx-$(CONFIG_PCI) += pcie.o + cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o + cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o + cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o ++cns3xxx-$(CONFIG_MACH_GW2388) += laguna.o ++ +--- a/arch/arm/mach-cns3xxx/devices.c ++++ b/arch/arm/mach-cns3xxx/devices.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include "cns3xxx.h" + #include "pm.h" + #include "core.h" +@@ -101,7 +102,11 @@ void __init cns3xxx_sdhci_init(void) + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ +- gpioa_pins |= 0x1fff0004; ++ if (machine_is_gw2388()) { ++ gpioa_pins |= 0x1fff0000; ++ } else { ++ gpioa_pins |= 0x1fff0004; ++ } + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); diff --git a/target/linux/cns3xxx/patches-3.18/101-laguna_sdhci_card_detect.patch b/target/linux/cns3xxx/patches-3.18/101-laguna_sdhci_card_detect.patch new file mode 100644 index 0000000..72648a5 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/101-laguna_sdhci_card_detect.patch @@ -0,0 +1,14 @@ +--- a/drivers/mmc/host/sdhci-cns3xxx.c ++++ b/drivers/mmc/host/sdhci-cns3xxx.c +@@ -88,9 +88,9 @@ static const struct sdhci_pltfm_data sdh + .ops = &sdhci_cns3xxx_ops, + .quirks = SDHCI_QUIRK_BROKEN_DMA | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | +- SDHCI_QUIRK_INVERTED_WRITE_PROTECT | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | +- SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | ++ SDHCI_QUIRK_BROKEN_CARD_DETECTION, + }; + + static int sdhci_cns3xxx_probe(struct platform_device *pdev) diff --git a/target/linux/cns3xxx/patches-3.18/110-pci_isolated_interrupts.patch b/target/linux/cns3xxx/patches-3.18/110-pci_isolated_interrupts.patch new file mode 100644 index 0000000..b7e07ff --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/110-pci_isolated_interrupts.patch @@ -0,0 +1,188 @@ +--- a/arch/arm/mach-cns3xxx/laguna.c ++++ b/arch/arm/mach-cns3xxx/laguna.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -872,6 +873,47 @@ static int laguna_register_gpio(struct g + return ret; + } + ++/* allow disabling of external isolated PCIe IRQs */ ++static int cns3xxx_pciextirq = 1; ++static int __init cns3xxx_pciextirq_disable(char *s) ++{ ++ cns3xxx_pciextirq = 0; ++ return 1; ++} ++__setup("noextirq", cns3xxx_pciextirq_disable); ++ ++static int __init laguna_pcie_init_irq(void) ++{ ++ u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004); ++ u32 reg = (__raw_readl(mem) >> 26) & 0xf; ++ int irqs[] = { ++ IRQ_CNS3XXX_EXTERNAL_PIN0, ++ IRQ_CNS3XXX_EXTERNAL_PIN1, ++ IRQ_CNS3XXX_EXTERNAL_PIN2, ++ 154, ++ }; ++ ++ if (!machine_is_gw2388()) ++ return 0; ++ ++ /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */ ++ if (cns3xxx_pciextirq && reg != 1) ++ cns3xxx_pciextirq = 0; ++ ++ if (cns3xxx_pciextirq) { ++ printk("laguna: using isolated PCI interrupts:" ++ " irq%d/irq%d/irq%d/irq%d\n", ++ irqs[0], irqs[1], irqs[2], irqs[3]); ++ cns3xxx_pcie_set_irqs(0, irqs); ++ } else { ++ printk("laguna: using shared PCI interrupts: irq%d\n", ++ IRQ_CNS3XXX_PCIE0_DEVICE); ++ } ++ ++ return 0; ++} ++subsys_initcall(laguna_pcie_init_irq); ++ + static int __init laguna_model_setup(void) + { + u32 __iomem *mem; +@@ -883,8 +925,33 @@ static int __init laguna_model_setup(voi + printk("Running on Gateworks Laguna %s\n", laguna_info.model); + cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, + NR_IRQS_CNS3XXX); +- cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, +- NR_IRQS_CNS3XXX + 32); ++ ++ /* ++ * If pcie external interrupts are supported and desired ++ * configure IRQ types and configure pin function. ++ * Note that cns3xxx_pciextirq is enabled by default, but can be ++ * unset via the 'noextirq' kernel param or by laguna_pcie_init() if ++ * the baseboard model does not support this hardware feature. ++ */ ++ if (cns3xxx_pciextirq) { ++ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018); ++ reg = __raw_readl(mem); ++ /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */ ++ reg &= ~0x3c000000; ++ reg |= 0x38000000; ++ __raw_writel(reg, mem); ++ ++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, ++ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); ++ ++ irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH); ++ irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH); ++ irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH); ++ } else { ++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, ++ IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); ++ } + + if (strncmp(laguna_info.model, "GW", 2) == 0) { + if (laguna_info.config_bitmap & ETH0_LOAD) +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + #include + #include + #include "cns3xxx.h" +@@ -27,7 +28,7 @@ struct cns3xxx_pcie { + void __iomem *host_regs; /* PCI config registers for host bridge */ + void __iomem *cfg0_regs; /* PCI Type 0 config registers */ + void __iomem *cfg1_regs; /* PCI Type 1 config registers */ +- unsigned int irqs[2]; ++ unsigned int irqs[5]; + struct resource res_io; + struct resource res_mem; + struct hw_pci hw_pci; +@@ -97,7 +98,7 @@ static inline int check_master_abort(str + void __iomem *host_base; + u32 sreg, ereg; + +- host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual; ++ host_base = (void __iomem *) cnspci->host_regs; + sreg = __raw_readw(host_base + 0x6) & 0xF900; + ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg + +@@ -251,7 +252,7 @@ static struct pci_ops cns3xxx_pcie_ops = + static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { + struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); +- int irq = cnspci->irqs[!!dev->bus->number]; ++ int irq = cnspci->irqs[!!dev->bus->number + pin - 1]; + + pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", + pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), +@@ -277,7 +278,12 @@ static struct cns3xxx_pcie cns3xxx_pcie[ + .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */ + .flags = IORESOURCE_MEM, + }, +- .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, ++ .irqs = { IRQ_CNS3XXX_PCIE0_RC, ++ IRQ_CNS3XXX_PCIE0_DEVICE, ++ IRQ_CNS3XXX_PCIE0_DEVICE, ++ IRQ_CNS3XXX_PCIE0_DEVICE, ++ IRQ_CNS3XXX_PCIE0_DEVICE, ++ }, + .hw_pci = { + .domain = 0, + .nr_controllers = 1, +@@ -302,7 +308,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[ + .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */ + .flags = IORESOURCE_MEM, + }, +- .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, ++ .irqs = { ++ IRQ_CNS3XXX_PCIE1_RC, ++ IRQ_CNS3XXX_PCIE1_DEVICE, ++ IRQ_CNS3XXX_PCIE1_DEVICE, ++ IRQ_CNS3XXX_PCIE1_DEVICE, ++ IRQ_CNS3XXX_PCIE1_DEVICE, ++ }, + .hw_pci = { + .domain = 1, + .nr_controllers = 1, +@@ -412,6 +424,14 @@ static int cns3xxx_pcie_abort_handler(un + return 0; + } + ++void __init cns3xxx_pcie_set_irqs(int bus, int *irqs) ++{ ++ int i; ++ ++ for (i = 0; i < 4; i++) ++ cns3xxx_pcie[bus].irqs[i + 1] = irqs[i]; ++} ++ + void __init cns3xxx_pcie_init_late(void) + { + int i; +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void); + + #ifdef CONFIG_PCI + extern void __init cns3xxx_pcie_init_late(void); ++extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs); + #else + static inline void __init cns3xxx_pcie_init_late(void) {} ++static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {} + #endif + + void __init cns3xxx_map_io(void); diff --git a/target/linux/cns3xxx/patches-3.18/200-broadcom_phy_reinit.patch b/target/linux/cns3xxx/patches-3.18/200-broadcom_phy_reinit.patch new file mode 100644 index 0000000..e4cc278 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/200-broadcom_phy_reinit.patch @@ -0,0 +1,14 @@ +--- a/drivers/net/phy/broadcom.c ++++ b/drivers/net/phy/broadcom.c +@@ -393,6 +393,11 @@ static int bcm5481_config_aneg(struct ph + /* Write bits 14:0. */ + reg |= (1 << 15); + phy_write(phydev, 0x18, reg); ++ } else { ++ phy_write(phydev, 0x18, 0xf1e7); ++ phy_write(phydev, 0x1c, 0x8e00); ++ ++ phy_write(phydev, 0x1c, 0xa41f); + } + + return ret; diff --git a/target/linux/cns3xxx/patches-3.18/210-dwc2_defaults.patch b/target/linux/cns3xxx/patches-3.18/210-dwc2_defaults.patch new file mode 100644 index 0000000..e9c71a1 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.18/210-dwc2_defaults.patch @@ -0,0 +1,47 @@ +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -105,6 +105,34 @@ static const struct dwc2_core_params par + .uframe_sched = -1, + }; + ++static const struct dwc2_core_params params_cns3xxx = { ++ .otg_cap = 2, /* non-HNP/non-SRP capable */ ++ .otg_ver = 0, /* 1.3 */ ++ .dma_enable = 1, ++ .dma_desc_enable = 0, ++ .speed = 0, /* High Speed */ ++ .enable_dynamic_fifo = 1, ++ .en_multiple_tx_fifo = 1, ++ .host_rx_fifo_size = 658, /* 774 DWORDs */ ++ .host_nperio_tx_fifo_size = 128, /* 256 DWORDs */ ++ .host_perio_tx_fifo_size = 658, /* 512 DWORDs */ ++ .max_transfer_size = 65535, ++ .max_packet_count = 511, ++ .host_channels = 16, ++ .phy_type = 1, /* UTMI */ ++ .phy_utmi_width = 16, /* 8 bits */ ++ .phy_ulpi_ddr = 0, /* Single */ ++ .phy_ulpi_ext_vbus = 0, ++ .i2c_enable = 0, ++ .ulpi_fs_ls = 0, ++ .host_support_fs_ls_low_power = 0, ++ .host_ls_low_power_phy_clk = 0, /* 48 MHz */ ++ .ts_dline = 0, ++ .reload_ctl = 0, ++ .ahbcfg = 0x10, ++ .uframe_sched = 0, ++}; ++ + /** + * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the + * DWC_otg driver +@@ -165,6 +193,9 @@ static int dwc2_driver_probe(struct plat + /* Default all params to autodetect */ + dwc2_set_all_params(&defparams, -1); + params = &defparams; ++#ifdef CONFIG_ARCH_CNS3XXX ++ params = ¶ms_cns3xxx; ++#endif + + /* + * Disable descriptor dma mode by default as the HW can support diff --git a/target/linux/gemini/Makefile b/target/linux/gemini/Makefile new file mode 100644 index 0000000..42f8c1e --- /dev/null +++ b/target/linux/gemini/Makefile @@ -0,0 +1,23 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=gemini +BOARDNAME:=Cortina Systems CS351x +SUBTARGETS:=raidsonic wiligear +FEATURES:=squashfs pci rtc +CPU_TYPE:=fa526 +MAINTAINER:=Roman Yeryomin + +KERNEL_PATCHVER:=4.1 + +KERNELNAME:=zImage + +include $(INCLUDE_DIR)/target.mk + +$(eval $(call BuildTarget)) diff --git a/target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini b/target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini new file mode 100644 index 0000000..4996081 --- /dev/null +++ b/target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini @@ -0,0 +1,13 @@ +#!/bin/sh + +set_ether_mac() { + CONFIG_PARTITION="$(grep "VCTL" /proc/mtd | cut -d: -f1)" + MAC1="$(strings /dev/$CONFIG_PARTITION |grep MAC|cut -d: -f2|cut -c3-14|sed -e 's,\(..\),:\1,g' -e 's,^:,,')" + MAC2="$(strings /dev/$CONFIG_PARTITION |grep MAC|cut -d: -f8|cut -c3-14|sed -e 's,\(..\),:\1,g' -e 's,^:,,')" + + ifconfig eth0 hw ether $MAC1 2>/dev/null + ifconfig eth1 hw ether $MAC2 2>/dev/null +} + +boot_hook_add preinit_main set_ether_mac + diff --git a/target/linux/gemini/config-3.18 b/target/linux/gemini/config-3.18 new file mode 100644 index 0000000..0591001 --- /dev/null +++ b/target/linux/gemini/config-3.18 @@ -0,0 +1,163 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_GEMINI=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_NR_BANKS=8 +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARPD is not set +CONFIG_ATA=y +CONFIG_ATAGS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=32M" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CPU_32v4=y +CONFIG_CPU_ABRT_EV4=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_FA=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FA=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +CONFIG_CPU_FA526=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_TLB_FA=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_UART_PHYS=0x42000000 +CONFIG_DEBUG_UART_VIRT=0xf4200000 +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +# CONFIG_DLCI is not set +CONFIG_DMADEVICES=y +CONFIG_DNOTIFY=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_FRAME_POINTER=y +CONFIG_GEMINI_MEM_SWAP=y +CONFIG_GEMINI_SL351X=y +CONFIG_GEMINI_WATCHDOG=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQ_WORK=y +CONFIG_KTIME_SCALAR=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_MACH_NAS4220B is not set +# CONFIG_MACH_RUT100 is not set +CONFIG_MACH_WBD111=y +CONFIG_MACH_WBD222=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MDIO_GPIO=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_PHYSMAP=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_MACH_GPIO_H=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_VENDOR_GEMINI=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PATA_GEMINI=y +CONFIG_PCI=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GEMINI=y +# CONFIG_SCHED_HRTICK is not set +# CONFIG_SCSI_DMA is not set +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UID16=y +CONFIG_UIDGID_CONVERTED=y +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_SUPPORT=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WAN=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/gemini/config-4.1 b/target/linux/gemini/config-4.1 new file mode 100644 index 0000000..b2ef7d7 --- /dev/null +++ b/target/linux/gemini/config-4.1 @@ -0,0 +1,164 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_GEMINI=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_NR_BANKS=8 +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARPD is not set +CONFIG_ATA=y +CONFIG_ATAGS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=32M" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CPU_32v4=y +CONFIG_CPU_ABRT_EV4=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_FA=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FA=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +CONFIG_CPU_FA526=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_TLB_FA=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_UART_PHYS=0x42000000 +CONFIG_DEBUG_UART_VIRT=0xf4200000 +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +# CONFIG_DLCI is not set +CONFIG_DMADEVICES=y +CONFIG_DNOTIFY=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_FRAME_POINTER=y +CONFIG_GEMINI_MEM_SWAP=y +CONFIG_GEMINI_SL351X=y +CONFIG_GEMINI_WATCHDOG=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +# CONFIG_HSU_DMA_PCI is not set +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQ_WORK=y +CONFIG_KTIME_SCALAR=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_MACH_NAS4220B is not set +# CONFIG_MACH_RUT100 is not set +CONFIG_MACH_WBD111=y +CONFIG_MACH_WBD222=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MDIO_GPIO=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_PHYSMAP=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_MACH_GPIO_H=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_VENDOR_GEMINI=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PATA_GEMINI=y +CONFIG_PCI=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GEMINI=y +# CONFIG_SCHED_HRTICK is not set +# CONFIG_SCSI_DMA is not set +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UID16=y +CONFIG_UIDGID_CONVERTED=y +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_SUPPORT=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WAN=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/gemini/files/drivers/ata/pata_gemini.c b/target/linux/gemini/files/drivers/ata/pata_gemini.c new file mode 100644 index 0000000..707e870 --- /dev/null +++ b/target/linux/gemini/files/drivers/ata/pata_gemini.c @@ -0,0 +1,234 @@ +/* + * Support for Gemini PATA + * + * Copyright (C) 2009 Janos Laube + * Copyright (C) 2010 Frederic Pecourt + * Copyright (C) 2011 Tobias Waldvogel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* Values of IOMUX + * 26:24 bits is "IDE IO Select" + * 111:100 - Reserved + * 011 - ata0 <-> sata0, sata1; bring out ata1 + * 010 - ata1 <-> sata1, sata0; bring out ata0 + * 001 - ata0 <-> sata0, ata1 <-> sata1; bring out ata1 + * 000 - ata0 <-> sata0, ata1 <-> sata1; bring out ata0 + * + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define DRV_NAME "pata-gemini" + +#define PATA_GEMINI_PORTS 1 + +#define PIO_TIMING_REG 0x10 +#define MDMA_TIMING_REG 0x11 +#define UDMA_TIMING0_REG 0x12 +#define UDMA_TIMING1_REG 0x13 +#define CLK_MOD_REG 0x14 + +#define CLK_MOD_66M_DEV0_BIT 0 +#define CLK_MOD_66M_DEV1_BIT 1 +#define CLK_MOD_UDMA_DEV0_BIT 4 +#define CLK_MOD_UDMA_DEV1_BIT 5 + +#define CLK_MOD_66M_DEV0 (1 << CLK_MOD_66M_DEV0_BIT) +#define CLK_MOD_66M_DEV1 (1 << CLK_MOD_66M_DEV1_BIT) +#define CLK_MOD_UDMA_DEV0 (1 << CLK_MOD_UDMA_DEV0_BIT) +#define CLK_MOD_UDMA_DEV1 (1 << CLK_MOD_UDMA_DEV1_BIT) + +#define SATA_ENABLE_PDEV_MASK 0x01 +#define SATA_ENABLE_PDEV_PM 0x02 +#define SATA_ENABLE_PDEV_ADDED 0x04 +#define SATA_ENABLE_PDEV_REMOVED 0x08 +#define SATA_ENABLE_SDEV_MASK 0x10 +#define SATA_ENABLE_SDEV_PM 0x20 +#define SATA_ENABLE_SDEV_ADDED 0x40 +#define SATA_ENABLE_SDEV_REMOVED 0x80 + +MODULE_AUTHOR("Janos Laube "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRV_NAME); + +static unsigned char PIO_TIMING[5] = { + 0xaa, 0xa3, 0xa1, 0x33, 0x31 +}; + +static unsigned char TIMING_MW_DMA[4][2] = { + { 0x44, 1 }, // 480 4.2 + { 0x42, 1 }, // 150 13.3 + { 0x31, 1 }, // 120 16.7 + { 0x21, 1 }, // 100 20 +}; + +static unsigned char TIMING_UDMA[7][2] = { + { 0x33, 0 }, //240 16.7 + { 0x31, 0 }, //160 25 + { 0x21, 0 }, //120 33.3 + { 0x21, 1 }, //90 44.4 + { 0x11, 1 }, //60 66.7 + { 0x11 | 0x80, 0 }, //40 100 + { 0x11 | 0x80, 1 }, //30 133 +}; + +static struct scsi_host_template pata_gemini_sht = { + ATA_NCQ_SHT(DRV_NAME), + .can_queue = 1, + .sg_tablesize = 128, + .dma_boundary = 0xffffU, +}; + +static void gemini_set_dmamode(struct ata_port *ap, struct ata_device *adev) +{ + void __iomem *clk_reg = ap->ioaddr.bmdma_addr + CLK_MOD_REG; + void __iomem *tim_reg = ap->ioaddr.bmdma_addr + UDMA_TIMING0_REG; + unsigned short udma = adev->dma_mode; + unsigned short speed = udma; + unsigned short devno = adev->devno & 1; + unsigned short i; + u8 mod_udma_mask = 1 << (CLK_MOD_UDMA_DEV0_BIT + devno); + u8 mod_66m_mask = 1 << (CLK_MOD_66M_DEV0_BIT + devno); + u8 clk_mod; + u8 timing; + + clk_mod = ioread8(clk_reg); + clk_mod &= ~mod_udma_mask; + + if (speed & XFER_UDMA_0) { + i = speed & ~XFER_UDMA_0; + timing = TIMING_UDMA[i][0]; + clk_mod |= mod_udma_mask; + if (TIMING_UDMA[i][1]) + clk_mod |= mod_66m_mask; + } else { + i = speed & ~XFER_MW_DMA_0; + timing = TIMING_MW_DMA[i][0]; + clk_mod |= mod_udma_mask; + if (TIMING_MW_DMA[i][1]) + clk_mod |= mod_66m_mask; + } + + iowrite8(clk_mod, clk_reg); + iowrite8(timing, tim_reg + devno); + return; +} + +static void gemini_set_piomode(struct ata_port *ap, struct ata_device *adev) +{ + void __iomem *pio_reg = ap->ioaddr.bmdma_addr + PIO_TIMING_REG; + unsigned int pio = adev->pio_mode - XFER_PIO_0; + + iowrite8(PIO_TIMING[pio], pio_reg); +} + +unsigned int gemini_qc_issue(struct ata_queued_cmd *qc) +{ + ledtrig_ide_activity(); + return ata_bmdma_qc_issue(qc); +} + +static struct ata_port_operations pata_gemini_port_ops = { + .inherits = &ata_bmdma_port_ops, + .set_dmamode = gemini_set_dmamode, + .set_piomode = gemini_set_piomode, + .qc_issue = gemini_qc_issue, +}; + +static struct ata_port_info pata_gemini_portinfo = { + .flags = 0, + .udma_mask = ATA_UDMA6, + .pio_mask = ATA_PIO4, + .port_ops = &pata_gemini_port_ops, +}; + +static const struct ata_port_info *pata_gemini_ports = &pata_gemini_portinfo; + +static int pata_gemini_probe(struct platform_device *pdev) +{ + struct ata_host *host; + struct resource *res; + unsigned int irq, i; + void __iomem *mmio_base; + + /* standard bdma init */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + pr_info(DRV_NAME ": irq %d, io base 0x%08x\n", irq, res->start); + + mmio_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + + host = ata_host_alloc_pinfo(&pdev->dev, &pata_gemini_ports, 1); + if (!host) + return -ENOMEM; + + for (i = 0; i < host->n_ports; i++) { + struct ata_port *ap = host->ports[i]; + struct ata_ioports *ioaddr = &ap->ioaddr; + + ioaddr->bmdma_addr = mmio_base; + ioaddr->cmd_addr = mmio_base + 0x20; + ioaddr->ctl_addr = mmio_base + 0x36; + ioaddr->altstatus_addr = ioaddr->ctl_addr; + ata_sff_std_ports(ioaddr); + host->ports[i]->cbl = ATA_CBL_SATA; + } + + return ata_host_activate(host, irq, ata_bmdma_interrupt, + IRQF_SHARED, &pata_gemini_sht); +} + +static int pata_gemini_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ata_host *host = dev_get_drvdata(dev); + ata_host_detach(host); + return 0; +} + +static struct platform_driver pata_gemini_driver = { + .probe = pata_gemini_probe, + .remove = pata_gemini_remove, + .driver.owner = THIS_MODULE, + .driver.name = DRV_NAME, +}; + +static int __init pata_gemini_module_init(void) +{ + return platform_driver_probe(&pata_gemini_driver, pata_gemini_probe); +} + +static void __exit pata_gemini_module_exit(void) +{ + platform_driver_unregister(&pata_gemini_driver); +} + +module_init(pata_gemini_module_init); +module_exit(pata_gemini_module_exit); diff --git a/target/linux/gemini/files/drivers/rtc/rtc-gemini.c b/target/linux/gemini/files/drivers/rtc/rtc-gemini.c new file mode 100644 index 0000000..587d812 --- /dev/null +++ b/target/linux/gemini/files/drivers/rtc/rtc-gemini.c @@ -0,0 +1,220 @@ +/* + * Gemini OnChip RTC + * + * Copyright (C) 2009 Janos Laube + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Original code for older kernel 2.6.15 are form Stormlinksemi + * first update from Janos Laube for > 2.6.29 kernels + * + * checkpatch fixes and usage off rtc-lib code + * Hans Ulli Kroll + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_NAME "rtc-gemini" + +MODULE_DESCRIPTION("RTC driver for Gemini SoC"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_AUTHOR("Hans Ulli Kroll "); +MODULE_LICENSE("GPL"); + +struct gemini_rtc { + struct rtc_device *dev; + void __iomem *base; + int irq; +}; + +enum gemini_rtc_offsets { + GEMINI_RTC_SECOND = 0x00, + GEMINI_RTC_MINUTE = 0x04, + GEMINI_RTC_HOUR = 0x08, + GEMINI_RTC_DAYS = 0x0C, + GEMINI_RTC_ALARM_SECOND = 0x10, + GEMINI_RTC_ALARM_MINUTE = 0x14, + GEMINI_RTC_ALARM_HOUR = 0x18, + GEMINI_RTC_RECORD = 0x1C, + GEMINI_RTC_CR = 0x20 +}; + +static irqreturn_t gemini_rtc_interrupt(int irq, void *dev) +{ + return IRQ_HANDLED; +} + +/* + * Looks like the RTC in the Gemini SoC is (totaly) broken + * We can't read/write directly the time from RTC registers. + * We must do some "offset" calculation to get the real time + * + * The register "day" seams to be fixed, and the register "hour" + * has his own mind. + * + * Maybe we can write directly the hour and days since EPOCH + * but in this case the RTC will recalucate to some (other) strange values. + * If you write time to the registers you will not read the same values. + * + * This FIX works pretty fine and Stormlinksemi aka Cortina-Networks does + * the same thing, without the rtc-lib.c calls. + */ + +static int gemini_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct gemini_rtc *rtc = dev_get_drvdata(dev); + + unsigned int days, hour, min, sec; + unsigned long offset, time; + + sec = readl(rtc->base + GEMINI_RTC_SECOND); + min = readl(rtc->base + GEMINI_RTC_MINUTE); + hour = readl(rtc->base + GEMINI_RTC_HOUR); + days = readl(rtc->base + GEMINI_RTC_DAYS); + offset = readl(rtc->base + GEMINI_RTC_RECORD); + + time = offset + days * 86400 + hour * 3600 + min * 60 + sec; + + rtc_time_to_tm(time, tm); + return 0; +} + +/* + * Maybe there is some hidden register to care ? + * looks like register GEMINI_RTC_DAY can count + * 365 days * 179 years >= 65535 (uint16) + */ + +static int gemini_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct gemini_rtc *rtc = dev_get_drvdata(dev); + unsigned int sec, min, hour, day; + unsigned long offset, time; + + if (tm->tm_year >= 2148) /* EPOCH Year + 179 */ + return -EINVAL; + + rtc_tm_to_time(tm , &time); + + sec = readl(rtc->base + GEMINI_RTC_SECOND); + min = readl(rtc->base + GEMINI_RTC_MINUTE); + hour = readl(rtc->base + GEMINI_RTC_HOUR); + day = readl(rtc->base + GEMINI_RTC_DAYS); + + offset = time - (day*86400 + hour*3600 + min*60 + sec); + + writel(offset, rtc->base + GEMINI_RTC_RECORD); + writel(0x01, rtc->base + GEMINI_RTC_CR); + return 0; +} + +static struct rtc_class_ops gemini_rtc_ops = { + .read_time = gemini_rtc_read_time, + .set_time = gemini_rtc_set_time, +}; + +static int gemini_rtc_probe(struct platform_device *pdev) +{ + struct gemini_rtc *rtc; + struct device *dev = &pdev->dev; + struct resource *res; + int ret; + + rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); + if (unlikely(!rtc)) + return -ENOMEM; + platform_set_drvdata(pdev, rtc); + + rtc->irq = platform_get_irq(pdev, 0); + if (rtc->irq < 0) { + ret = -rtc->irq; + goto err_mem; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENODEV; + goto err_mem; + } + rtc->base = devm_ioremap(&pdev->dev, res->start, + res->end - res->start + 1); + + ret = request_irq(rtc->irq, gemini_rtc_interrupt, + IRQF_SHARED, pdev->name, dev); + if (unlikely(ret)) + goto err_mem; + + rtc->dev = rtc_device_register(pdev->name, dev, + &gemini_rtc_ops, THIS_MODULE); + if (unlikely(IS_ERR(rtc->dev))) { + ret = PTR_ERR(rtc->dev); + goto err_irq; + } + return 0; + +err_irq: + free_irq(rtc->irq, dev); + +err_mem: + kfree(rtc); + return ret; +} + +static int gemini_rtc_remove(struct platform_device *pdev) +{ + struct gemini_rtc *rtc = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + + free_irq(rtc->irq, dev); + rtc_device_unregister(rtc->dev); + platform_set_drvdata(pdev, NULL); + kfree(rtc); + + return 0; +} + +static struct platform_driver gemini_rtc_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, + .probe = gemini_rtc_probe, + .remove = gemini_rtc_remove, +}; + +static int __init gemini_rtc_init(void) +{ + int retval; + + retval = platform_driver_register(&gemini_rtc_driver); + if (retval == 0) + pr_info(DRV_NAME ": registered successfully"); + return retval; +} + +static void __exit gemini_rtc_exit(void) +{ + platform_driver_unregister(&gemini_rtc_driver); +} + +module_init(gemini_rtc_init); +module_exit(gemini_rtc_exit); diff --git a/target/linux/gemini/files/drivers/usb/host/ehci-fotg2.c b/target/linux/gemini/files/drivers/usb/host/ehci-fotg2.c new file mode 100644 index 0000000..0717abc --- /dev/null +++ b/target/linux/gemini/files/drivers/usb/host/ehci-fotg2.c @@ -0,0 +1,258 @@ +/* + * Gemini EHCI Host Controller driver + * + * Copyright (C) 2014 Roman Yeryomin + * Copyright (C) 2012 Tobias Waldvogel + * based on GPLd code from Sony Computer Entertainment Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "ehci.h" + +#define DRV_NAME "ehci-fotg2" + +#define HCD_MISC 0x40 + +#define OTGC_SCR 0x80 +#define OTGC_INT_STS 0x84 +#define OTGC_INT_EN 0x88 + +#define GLOBAL_ISR 0xC0 +#define GLOBAL_ICR 0xC4 + +#define GLOBAL_INT_POLARITY (1 << 3) +#define GLOBAL_INT_MASK_HC (1 << 2) +#define GLOBAL_INT_MASK_OTG (1 << 1) +#define GLOBAL_INT_MASK_DEV (1 << 0) + +#define OTGC_SCR_ID (1 << 21) +#define OTGC_SCR_CROLE (1 << 20) +#define OTGC_SCR_VBUS_VLD (1 << 19) +#define OTGC_SCR_A_SRP_RESP_TYPE (1 << 8) +#define OTGC_SCR_A_SRP_DET_EN (1 << 7) +#define OTGC_SCR_A_SET_B_HNP_EN (1 << 6) +#define OTGC_SCR_A_BUS_DROP (1 << 5) +#define OTGC_SCR_A_BUS_REQ (1 << 4) + +#define OTGC_INT_APLGRMV (1 << 12) +#define OTGC_INT_BPLGRMV (1 << 11) +#define OTGC_INT_OVC (1 << 10) +#define OTGC_INT_IDCHG (1 << 9) +#define OTGC_INT_RLCHG (1 << 8) +#define OTGC_INT_AVBUSERR (1 << 5) +#define OTGC_INT_ASRPDET (1 << 4) +#define OTGC_INT_BSRPDN (1 << 0) + +#define OTGC_INT_A_TYPE ( \ + OTGC_INT_ASRPDET | \ + OTGC_INT_AVBUSERR | \ + OTGC_INT_OVC | \ + OTGC_INT_RLCHG | \ + OTGC_INT_IDCHG | \ + OTGC_INT_APLGRMV \ + ) +#define OTGC_INT_B_TYPE ( \ + OTGC_INT_AVBUSERR | \ + OTGC_INT_OVC | \ + OTGC_INT_RLCHG | \ + OTGC_INT_IDCHG \ + ) + + +static void fotg2_otg_init(struct usb_hcd *hcd) +{ + u32 val; + + writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC | + GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV, + hcd->regs + GLOBAL_ICR); + + val = readl(hcd->regs + OTGC_SCR); + val &= ~(OTGC_SCR_A_SRP_RESP_TYPE | OTGC_SCR_A_SRP_DET_EN | + OTGC_SCR_A_BUS_DROP | OTGC_SCR_A_SET_B_HNP_EN); + val |= OTGC_SCR_A_BUS_REQ; + writel(val, hcd->regs + OTGC_SCR); + + writel(OTGC_INT_A_TYPE, hcd->regs + OTGC_INT_EN); + + /* setup MISC register, fixes timing problems */ + val = readl(hcd->regs + HCD_MISC); + val |= 0xD; + writel(val, hcd->regs + HCD_MISC); + + writel(~0, hcd->regs + GLOBAL_ISR); + writel(~0, hcd->regs + OTGC_INT_STS); +} + +static int fotg2_ehci_reset(struct usb_hcd *hcd) +{ + int retval; + + retval = ehci_setup(hcd); + if (retval) + return retval; + + writel(GLOBAL_INT_POLARITY, hcd->regs + GLOBAL_ICR); + return 0; +} + +static const struct hc_driver fotg2_ehci_hc_driver = { + .description = hcd_name, + .product_desc = "FOTG2 EHCI Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + .reset = fotg2_ehci_reset, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .endpoint_reset = ehci_endpoint_reset, + .get_frame_number = ehci_get_frame, + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#if defined(CONFIG_PM) + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static irqreturn_t fotg2_ehci_irq(int irq, void *data) +{ + struct usb_hcd *hcd = data; + u32 icr, sts; + irqreturn_t retval; + + icr = readl(hcd->regs + GLOBAL_ICR); + writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC | + GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV, + hcd->regs + GLOBAL_ICR); + + retval = IRQ_NONE; + + sts = ~icr; + sts &= GLOBAL_INT_MASK_HC | GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV; + sts &= readl(hcd->regs + GLOBAL_ISR); + writel(sts, hcd->regs + GLOBAL_ISR); + + if (unlikely(sts & GLOBAL_INT_MASK_DEV)) { + ehci_warn(hcd_to_ehci(hcd), + "Received unexpected irq for device role\n"); + retval = IRQ_HANDLED; + } + + if (unlikely(sts & GLOBAL_INT_MASK_OTG)) { + u32 otg_sts; + + otg_sts = readl(hcd->regs + OTGC_INT_STS); + writel(otg_sts, hcd->regs + OTGC_INT_STS); + + ehci_warn(hcd_to_ehci(hcd), + "Received unexpected irq for OTG management\n"); + retval = IRQ_HANDLED; + } + + if (sts & GLOBAL_INT_MASK_HC) { + retval = IRQ_NONE; + } + + writel(icr, hcd->regs + GLOBAL_ICR); + return retval; +} + +static int fotg2_ehci_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct resource *res; + int irq , err; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + pr_err("no irq provided"); + return irq; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + pr_err("no memory resource provided"); + return -ENXIO; + } + + hcd = usb_create_hcd(&fotg2_ehci_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = res->start; + hcd->rsrc_len = resource_size(res); + + hcd->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(hcd->regs)) { + err = -ENOMEM; + goto err_put_hcd; + } + + hcd->has_tt = 1; + hcd_to_ehci(hcd)->caps = hcd->regs; + + fotg2_otg_init(hcd); + + err = request_irq(irq, &fotg2_ehci_irq, IRQF_SHARED, "fotg2", hcd); + if (err) + goto err_put_hcd; + + err = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (err) + goto err_put_hcd; + + platform_set_drvdata(pdev, hcd); + return 0; + +err_put_hcd: + usb_put_hcd(hcd); + return err; +} + +static int fotg2_ehci_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + writel(GLOBAL_INT_POLARITY | GLOBAL_INT_MASK_HC | + GLOBAL_INT_MASK_OTG | GLOBAL_INT_MASK_DEV, + hcd->regs + GLOBAL_ICR); + + free_irq(hcd->irq, hcd); + usb_remove_hcd(hcd); + usb_put_hcd(hcd); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +MODULE_ALIAS("platform:" DRV_NAME); + +static struct platform_driver ehci_fotg2_driver = { + .probe = fotg2_ehci_probe, + .remove = fotg2_ehci_remove, + .driver.name = DRV_NAME, +}; diff --git a/target/linux/gemini/image/ImageInfo-ib4220 b/target/linux/gemini/image/ImageInfo-ib4220 new file mode 100644 index 0000000..68fca5b --- /dev/null +++ b/target/linux/gemini/image/ImageInfo-ib4220 @@ -0,0 +1,19 @@ +Distribution="OpenWrt" +Layout="Compact" +UpgradeImages="zImage rd.gz hddapp.tgz" +productName="IB-NAS4220-B" +hardwareName="MP-LNU23SL" +productVendor=" " +VendorID="macpower" +ProductID="pddlan" +UpgradeVersion="300" +ExtraVersion="" +manufacturerURL=" " +Description="IB-NAS4220-B" +hostname="IB-NAS4220-B" +softwareVersion="3.0" +TSS="enabled" +DIRECT_MODE="disabled" +Raid_Support="raid0_raid1_raid5_linear" +RaidTestDiskSize="0" +Raid_Show_Disk="2" diff --git a/target/linux/gemini/image/Makefile b/target/linux/gemini/image/Makefile new file mode 100644 index 0000000..1c51b62 --- /dev/null +++ b/target/linux/gemini/image/Makefile @@ -0,0 +1,87 @@ +# +# Copyright (C) 2009-2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +ifeq ($(SUBTARGET),wiligear) +define Image/Prepare +# WBD111: mach id 1690 (0x69a) + echo -en "\x06\x1c\xa0\xe3\x9a\x10\x81\xe3" > $(KDIR)/$(IMG_PREFIX)-wbd111-zImage + cat $(KDIR)/zImage >> $(KDIR)/$(IMG_PREFIX)-wbd111-zImage +# WBD222: mach id 2753 (0xAC1) + echo -en "\x0a\x1c\xa0\xe3\xc1\x10\x81\xe3" > $(KDIR)/$(IMG_PREFIX)-wbd222-zImage + cat $(KDIR)/zImage >> $(KDIR)/$(IMG_PREFIX)-wbd222-zImage +endef +endif + +ifeq ($(SUBTARGET),raidsonic) +define Image/Prepare +# NAS4220: mach id 2038 (0x7F6) + echo -en "\x07\x1c\xa0\xe3\xf6\x10\x81\xe3" > $(KDIR)/$(IMG_PREFIX)-nas4220-zImage + cat $(KDIR)/zImage >> $(KDIR)/$(IMG_PREFIX)-nas4220-zImage +endef +endif + +ifeq ($(SUBTARGET),wiligear) +define Image/BuildKernel +# workaround the bootloader's bug with extra nops + echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage + cat $(KDIR)/$(IMG_PREFIX)-wbd111-zImage >> $(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage + echo -en "\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1\x00\x00\xa0\xe1" > $(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage + cat $(KDIR)/$(IMG_PREFIX)-wbd222-zImage >> $(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage +endef +endif + +define Image/Build/jffs2-64k + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=64k conv=sync +endef + +define Image/Build/jffs2-128k + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=128k conv=sync +endef + +ifeq ($(SUBTARGET),wiligear) +define Image/Build + $(call Image/Build/$(1),$(1)) + -$(STAGING_DIR_HOST)/bin/mkfwimage2 \ + -m GEOS -f 0x30000000 -z \ + -v WILI-S.WILIBOARD.v5.00.SL3512.OpenWrt.00000.000000.000000 \ + -o $(BIN_DIR)/$(IMG_PREFIX)-wbd111-$(1).bin \ + -p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-wbd111-zImage \ + -p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img + + -$(STAGING_DIR_HOST)/bin/mkfwimage2 \ + -m GEOS -f 0x30000000 -z \ + -v WILI-S.WBD222.v5.00.SL3512.OpenWrt.00000.000000.000000 \ + -o $(BIN_DIR)/$(IMG_PREFIX)-wbd222-$(1).bin \ + -p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-wbd222-zImage \ + -p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img +endef +endif + +ifeq ($(SUBTARGET),raidsonic) +define Image/Build + $(call Image/Build/$(1),$(1)) + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img of=$(BIN_DIR)/rd.gz bs=6144k count=1 +# dd if=/dev/zero of=$(BIN_DIR)/hddapp.tgz bs=6144k count=1 + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img of=$(BIN_DIR)/hddapp.tgz bs=6144k count=1 seek=1 + cp $(KDIR)/$(IMG_PREFIX)-nas4220-zImage $(BIN_DIR)/ + cp $(BIN_DIR)/$(IMG_PREFIX)-nas4220-zImage $(BIN_DIR)/zImage + cp ./ImageInfo-ib4220 $(BIN_DIR)/ImageInfo + (cd $(BIN_DIR); tar -czf $(IMG_PREFIX)-sysupgrade-ib4220.tar.gz ImageInfo zImage rd.gz hddapp.tgz) + mv $(BIN_DIR)/rd.gz $(BIN_DIR)/$(IMG_PREFIX)-nas4220-rd.gz + mv $(BIN_DIR)/hddapp.tgz $(BIN_DIR)/$(IMG_PREFIX)-nas4220-hddapp.tgz + rm -f $(BIN_DIR)/zImage $(BIN_DIR)/ImageInfo +endef +endif + +$(eval $(call BuildImage)) diff --git a/target/linux/gemini/patches-3.18/002-gemini-rtc.patch b/target/linux/gemini/patches-3.18/002-gemini-rtc.patch new file mode 100644 index 0000000..f16e6a3 --- /dev/null +++ b/target/linux/gemini/patches-3.18/002-gemini-rtc.patch @@ -0,0 +1,51 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1182,6 +1182,15 @@ config RTC_DRV_BFIN + This driver can also be built as a module. If so, the module + will be called rtc-bfin. + ++config RTC_DRV_GEMINI ++ tristate "Gemini SoC RTC" ++ help ++ If you say Y here you will get support for the ++ RTC found on Gemini SoC's. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-gemini. ++ + config RTC_DRV_RS5C313 + tristate "Ricoh RS5C313" + depends on SH_LANDISK +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -60,6 +60,7 @@ obj-$(CONFIG_RTC_DRV_EFI) += rtc-efi.o + obj-$(CONFIG_RTC_DRV_EM3027) += rtc-em3027.o + obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o + obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o ++obj-$(CONFIG_RTC_DRV_GEMINI) += rtc-gemini.o + obj-$(CONFIG_RTC_DRV_GENERIC) += rtc-generic.o + obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o + obj-$(CONFIG_RTC_DRV_HYM8563) += rtc-hym8563.o +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -18,9 +18,9 @@ extern void gemini_map_io(void); + extern void gemini_init_irq(void); + extern void gemini_timer_init(void); + extern void gemini_gpio_init(void); +-extern void platform_register_rtc(void); + + /* Common platform devices registration functions */ ++extern int platform_register_rtc(void); + extern int platform_register_uart(void); + extern int platform_register_pflash(unsigned int size, + struct mtd_partition *parts, +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include "common.h" + + static struct plat_serial8250_port serial_platform_data[] = { + { diff --git a/target/linux/gemini/patches-3.18/021-reset-parameters.patch b/target/linux/gemini/patches-3.18/021-reset-parameters.patch new file mode 100644 index 0000000..644e513 --- /dev/null +++ b/target/linux/gemini/patches-3.18/021-reset-parameters.patch @@ -0,0 +1,25 @@ +--- a/arch/arm/mach-gemini/reset.c ++++ b/arch/arm/mach-gemini/reset.c +@@ -11,10 +11,11 @@ + #define __MACH_SYSTEM_H + + #include ++#include + #include + #include + +-void gemini_restart(char mode, const char *cmd) ++void gemini_restart(enum reboot_mode mode, const char *cmd) + { + __raw_writel(RESET_GLOBAL | RESET_CPU1, + IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET); +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -26,6 +26,6 @@ extern int platform_register_pflash(unsi + struct mtd_partition *parts, + unsigned int nr_parts); + +-extern void gemini_restart(char mode, const char *cmd); ++extern void gemini_restart(enum reboot_mode mode, const char *cmd); + + #endif /* __GEMINI_COMMON_H__ */ diff --git a/target/linux/gemini/patches-3.18/050-gpio-to-irq.patch b/target/linux/gemini/patches-3.18/050-gpio-to-irq.patch new file mode 100644 index 0000000..7572849 --- /dev/null +++ b/target/linux/gemini/patches-3.18/050-gpio-to-irq.patch @@ -0,0 +1,21 @@ +--- a/arch/arm/mach-gemini/gpio.c ++++ b/arch/arm/mach-gemini/gpio.c +@@ -196,12 +196,18 @@ static int gemini_gpio_direction_output( + return 0; + } + ++static int gemini_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) ++{ ++ return gpio + GPIO_IRQ_BASE; ++} ++ + static struct gpio_chip gemini_gpio_chip = { + .label = "Gemini", + .direction_input = gemini_gpio_direction_input, + .get = gemini_gpio_get, + .direction_output = gemini_gpio_direction_output, + .set = gemini_gpio_set, ++ .to_irq = gemini_gpio_to_irq, + .base = 0, + .ngpio = GPIO_PORT_NUM * 32, + }; diff --git a/target/linux/gemini/patches-3.18/060-cache-fa.diff b/target/linux/gemini/patches-3.18/060-cache-fa.diff new file mode 100644 index 0000000..fc74c0a --- /dev/null +++ b/target/linux/gemini/patches-3.18/060-cache-fa.diff @@ -0,0 +1,41 @@ +--- a/arch/arm/mm/cache-fa.S ++++ b/arch/arm/mm/cache-fa.S +@@ -24,7 +24,8 @@ + /* + * The size of one data cache line. + */ +-#define CACHE_DLINESIZE 16 ++#define CACHE_DLINESIZE 16 ++#define CACHE_DLINESHIFT 4 + + /* + * The total size of the data cache. +@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area) + * - start - virtual start address + * - end - virtual end address + */ ++__flush_whole_dcache: ++ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer ++ mov pc, lr ++ + fa_dma_inv_range: ++ sub r3, r1, r0 @ calculate total size ++ cmp r3, #CACHE_DLIMIT @ total size >= limit? ++ bhs __flush_whole_dcache @ flush whole D cache ++ + tst r0, #CACHE_DLINESIZE - 1 + bic r0, r0, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry +@@ -193,6 +204,10 @@ fa_dma_inv_range: + * - end - virtual end address + */ + fa_dma_clean_range: ++ sub r3, r1, r0 @ calculate total size ++ cmp r3, #CACHE_DLIMIT @ total size >= limit? ++ bhs __flush_whole_dcache @ flush whole D cache ++ + bic r0, r0, #CACHE_DLINESIZE - 1 + 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHE_DLINESIZE diff --git a/target/linux/gemini/patches-3.18/110-watchdog-add-gemini_wdt-driver.patch b/target/linux/gemini/patches-3.18/110-watchdog-add-gemini_wdt-driver.patch new file mode 100644 index 0000000..003a562 --- /dev/null +++ b/target/linux/gemini/patches-3.18/110-watchdog-add-gemini_wdt-driver.patch @@ -0,0 +1,410 @@ +--- /dev/null ++++ b/drivers/watchdog/gemini_wdt.c +@@ -0,0 +1,378 @@ ++/* ++ * Watchdog driver for Cortina Systems Gemini SoC ++ * ++ * Copyright (C) 2009 Paulius Zaleckas ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define GEMINI_WDCOUNTER 0x0 ++#define GEMINI_WDLOAD 0x4 ++#define GEMINI_WDRESTART 0x8 ++ ++#define WDRESTART_MAGIC 0x5AB9 ++ ++#define GEMINI_WDCR 0xC ++ ++#define WDCR_CLOCK_5MHZ (1 << 4) ++#define WDCR_SYS_RST (1 << 1) ++#define WDCR_ENABLE (1 << 0) ++ ++#define WDT_CLOCK 5000000 /* 5 MHz */ ++#define WDT_DEFAULT_TIMEOUT 13 ++#define WDT_MAX_TIMEOUT (0xFFFFFFFF / WDT_CLOCK) ++ ++/* status bits */ ++#define WDT_ACTIVE 0 ++#define WDT_OK_TO_CLOSE 1 ++ ++static unsigned int timeout = WDT_DEFAULT_TIMEOUT; ++static int nowayout = WATCHDOG_NOWAYOUT; ++ ++static DEFINE_SPINLOCK(gemini_wdt_lock); ++ ++static struct platform_device *gemini_wdt_dev; ++ ++struct gemini_wdt_struct { ++ struct resource *res; ++ struct device *dev; ++ void __iomem *base; ++ unsigned long status; ++}; ++ ++static struct watchdog_info gemini_wdt_info = { ++ .identity = "Gemini watchdog", ++ .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | ++ WDIOF_SETTIMEOUT, ++}; ++ ++/* Disable the watchdog. */ ++static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt) ++{ ++ spin_lock(&gemini_wdt_lock); ++ ++ __raw_writel(0, gemini_wdt->base + GEMINI_WDCR); ++ ++ clear_bit(WDT_ACTIVE, &gemini_wdt->status); ++ ++ spin_unlock(&gemini_wdt_lock); ++} ++ ++/* Service the watchdog */ ++static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt) ++{ ++ __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART); ++} ++ ++/* Enable and reset the watchdog. */ ++static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt) ++{ ++ spin_lock(&gemini_wdt_lock); ++ ++ __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD); ++ ++ gemini_wdt_service(gemini_wdt); ++ ++ /* set clock before enabling */ ++ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST, ++ gemini_wdt->base + GEMINI_WDCR); ++ ++ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE, ++ gemini_wdt->base + GEMINI_WDCR); ++ ++ set_bit(WDT_ACTIVE, &gemini_wdt->status); ++ ++ spin_unlock(&gemini_wdt_lock); ++} ++ ++/* Watchdog device is opened, and watchdog starts running. */ ++static int gemini_wdt_open(struct inode *inode, struct file *file) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev); ++ ++ if (test_bit(WDT_ACTIVE, &gemini_wdt->status)) ++ return -EBUSY; ++ ++ file->private_data = gemini_wdt; ++ ++ gemini_wdt_start(gemini_wdt); ++ ++ return nonseekable_open(inode, file); ++} ++ ++/* Close the watchdog device. */ ++static int gemini_wdt_close(struct inode *inode, struct file *file) ++{ ++ struct gemini_wdt_struct *gemini_wdt = file->private_data; ++ ++ /* Disable the watchdog if possible */ ++ if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status)) ++ gemini_wdt_stop(gemini_wdt); ++ else ++ dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n"); ++ ++ return 0; ++} ++ ++/* Handle commands from user-space. */ ++static long gemini_wdt_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ struct gemini_wdt_struct *gemini_wdt = file->private_data; ++ ++ int value; ++ ++ switch (cmd) { ++ case WDIOC_KEEPALIVE: ++ gemini_wdt_service(gemini_wdt); ++ return 0; ++ ++ case WDIOC_GETSUPPORT: ++ return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info, ++ sizeof(gemini_wdt_info)) ? -EFAULT : 0; ++ ++ case WDIOC_SETTIMEOUT: ++ if (get_user(value, (int *)arg)) ++ return -EFAULT; ++ ++ if ((value < 1) || (value > WDT_MAX_TIMEOUT)) ++ return -EINVAL; ++ ++ timeout = value; ++ ++ /* restart wdt to use new timeout */ ++ gemini_wdt_stop(gemini_wdt); ++ gemini_wdt_start(gemini_wdt); ++ ++ /* Fall through */ ++ case WDIOC_GETTIMEOUT: ++ return put_user(timeout, (int *)arg); ++ ++ case WDIOC_GETTIMELEFT: ++ value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER); ++ return put_user(value / WDT_CLOCK, (int *)arg); ++ ++ default: ++ return -ENOTTY; ++ } ++} ++ ++/* Refresh the watchdog whenever device is written to. */ ++static ssize_t gemini_wdt_write(struct file *file, const char *data, ++ size_t len, loff_t *ppos) ++{ ++ struct gemini_wdt_struct *gemini_wdt = file->private_data; ++ ++ if (len) { ++ if (!nowayout) { ++ size_t i; ++ ++ clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status); ++ for (i = 0; i != len; i++) { ++ char c; ++ ++ if (get_user(c, data + i)) ++ return -EFAULT; ++ if (c == 'V') ++ set_bit(WDT_OK_TO_CLOSE, ++ &gemini_wdt->status); ++ } ++ } ++ gemini_wdt_service(gemini_wdt); ++ } ++ ++ return len; ++} ++ ++static const struct file_operations gemini_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .unlocked_ioctl = gemini_wdt_ioctl, ++ .open = gemini_wdt_open, ++ .release = gemini_wdt_close, ++ .write = gemini_wdt_write, ++}; ++ ++static struct miscdevice gemini_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &gemini_wdt_fops, ++}; ++ ++static void gemini_wdt_shutdown(struct platform_device *pdev) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev); ++ ++ gemini_wdt_stop(gemini_wdt); ++} ++ ++static int gemini_wdt_probe(struct platform_device *pdev) ++{ ++ int ret; ++ int res_size; ++ struct resource *res; ++ void __iomem *base; ++ struct gemini_wdt_struct *gemini_wdt; ++ unsigned int reg; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "can't get device resources\n"); ++ return -ENODEV; ++ } ++ ++ res_size = resource_size(res); ++ if (!request_mem_region(res->start, res_size, res->name)) { ++ dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n", ++ res_size, res->start); ++ return -ENOMEM; ++ } ++ ++ base = ioremap(res->start, res_size); ++ if (!base) { ++ dev_err(&pdev->dev, "ioremap failed\n"); ++ ret = -EIO; ++ goto fail0; ++ } ++ ++ gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL); ++ if (!gemini_wdt) { ++ dev_err(&pdev->dev, "can't allocate interface\n"); ++ ret = -ENOMEM; ++ goto fail1; ++ } ++ ++ /* Setup gemini_wdt driver structure */ ++ gemini_wdt->base = base; ++ gemini_wdt->res = res; ++ ++ /* Set up platform driver data */ ++ platform_set_drvdata(pdev, gemini_wdt); ++ gemini_wdt_dev = pdev; ++ ++ if (gemini_wdt_miscdev.parent) { ++ ret = -EBUSY; ++ goto fail2; ++ } ++ ++ gemini_wdt_miscdev.parent = &pdev->dev; ++ ++ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR); ++ if (reg & WDCR_ENABLE) { ++ /* Watchdog was enabled by the bootloader, disable it. */ ++ reg &= ~(WDCR_ENABLE); ++ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR); ++ } ++ ++ ret = misc_register(&gemini_wdt_miscdev); ++ if (ret) ++ goto fail2; ++ ++ return 0; ++ ++fail2: ++ platform_set_drvdata(pdev, NULL); ++ kfree(gemini_wdt); ++fail1: ++ iounmap(base); ++fail0: ++ release_mem_region(res->start, res_size); ++ ++ return ret; ++} ++ ++static int gemini_wdt_remove(struct platform_device *pdev) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev); ++ ++ platform_set_drvdata(pdev, NULL); ++ misc_deregister(&gemini_wdt_miscdev); ++ gemini_wdt_dev = NULL; ++ iounmap(gemini_wdt->base); ++ release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res)); ++ ++ kfree(gemini_wdt); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev); ++ unsigned int reg; ++ ++ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR); ++ reg &= ~(WDCR_WDENABLE); ++ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR); ++ ++ return 0; ++} ++ ++static int gemini_wdt_resume(struct platform_device *pdev) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev); ++ unsigned int reg; ++ ++ if (gemini_wdt->status) { ++ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR); ++ reg |= WDCR_WDENABLE; ++ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR); ++ } ++ ++ return 0; ++} ++#else ++#define gemini_wdt_suspend NULL ++#define gemini_wdt_resume NULL ++#endif ++ ++static struct platform_driver gemini_wdt_driver = { ++ .probe = gemini_wdt_probe, ++ .remove = gemini_wdt_remove, ++ .shutdown = gemini_wdt_shutdown, ++ .suspend = gemini_wdt_suspend, ++ .resume = gemini_wdt_resume, ++ .driver = { ++ .name = "gemini-wdt", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init gemini_wdt_init(void) ++{ ++ return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe); ++} ++ ++static void __exit gemini_wdt_exit(void) ++{ ++ platform_driver_unregister(&gemini_wdt_driver); ++} ++ ++module_init(gemini_wdt_init); ++module_exit(gemini_wdt_exit); ++ ++module_param(timeout, uint, 0); ++MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds"); ++ ++module_param(nowayout, int, 0); ++MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); ++ ++MODULE_AUTHOR("Paulius Zaleckas"); ++MODULE_DESCRIPTION("Watchdog driver for Gemini"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:gemini-wdt"); +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -199,6 +199,16 @@ config 977_WATCHDOG + + Not sure? It's safe to say N. + ++config GEMINI_WATCHDOG ++ tristate "Gemini watchdog" ++ depends on ARCH_GEMINI ++ help ++ Say Y here if to include support for the watchdog timer ++ embedded in the Cortina Systems Gemini family of devices. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called gemini_wdt. ++ + config IXP4XX_WATCHDOG + tristate "IXP4xx Watchdog" + depends on ARCH_IXP4XX +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -37,6 +37,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt. + obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o + obj-$(CONFIG_21285_WATCHDOG) += wdt285.o + obj-$(CONFIG_977_WATCHDOG) += wdt977.o ++obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o + obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o + obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o + obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o diff --git a/target/linux/gemini/patches-3.18/111-arm-gemini-add-watchdog-device.patch b/target/linux/gemini/patches-3.18/111-arm-gemini-add-watchdog-device.patch new file mode 100644 index 0000000..3f1f40d --- /dev/null +++ b/target/linux/gemini/patches-3.18/111-arm-gemini-add-watchdog-device.patch @@ -0,0 +1,33 @@ +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -117,3 +117,20 @@ int __init platform_register_rtc(void) + return platform_device_register(&gemini_rtc_device); + } + ++static struct resource wdt_resource = { ++ .start = GEMINI_WAQTCHDOG_BASE, ++ .end = GEMINI_WAQTCHDOG_BASE + 0x18, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device wdt_device = { ++ .name = "gemini-wdt", ++ .id = 0, ++ .resource = &wdt_resource, ++ .num_resources = 1, ++}; ++ ++int __init platform_register_watchdog(void) ++{ ++ return platform_device_register(&wdt_device); ++} +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -25,6 +25,7 @@ extern int platform_register_uart(void); + extern int platform_register_pflash(unsigned int size, + struct mtd_partition *parts, + unsigned int nr_parts); ++extern int platform_register_watchdog(void); + + extern void gemini_restart(enum reboot_mode mode, const char *cmd); + diff --git a/target/linux/gemini/patches-3.18/112-arm-gemini-register-watchdog-devices.patch b/target/linux/gemini/patches-3.18/112-arm-gemini-register-watchdog-devices.patch new file mode 100644 index 0000000..74564b1 --- /dev/null +++ b/target/linux/gemini/patches-3.18/112-arm-gemini-register-watchdog-devices.patch @@ -0,0 +1,40 @@ +--- a/arch/arm/mach-gemini/board-nas4220b.c ++++ b/arch/arm/mach-gemini/board-nas4220b.c +@@ -95,6 +95,7 @@ static void __init ib4220b_init(void) + platform_device_register(&ib4220b_led_device); + platform_device_register(&ib4220b_key_device); + platform_register_rtc(); ++ platform_register_watchdog(); + } + + MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") +--- a/arch/arm/mach-gemini/board-wbd111.c ++++ b/arch/arm/mach-gemini/board-wbd111.c +@@ -122,6 +122,7 @@ static void __init wbd111_init(void) + platform_device_register(&wbd111_leds_device); + platform_device_register(&wbd111_keys_device); + platform_register_rtc(); ++ platform_register_watchdog(); + } + + MACHINE_START(WBD111, "Wiliboard WBD-111") +--- a/arch/arm/mach-gemini/board-wbd222.c ++++ b/arch/arm/mach-gemini/board-wbd222.c +@@ -122,6 +122,7 @@ static void __init wbd222_init(void) + platform_device_register(&wbd222_leds_device); + platform_device_register(&wbd222_keys_device); + platform_register_rtc(); ++ platform_register_watchdog(); + } + + MACHINE_START(WBD222, "Wiliboard WBD-222") +--- a/arch/arm/mach-gemini/board-rut1xx.c ++++ b/arch/arm/mach-gemini/board-rut1xx.c +@@ -80,6 +80,7 @@ static void __init rut1xx_init(void) + platform_device_register(&rut1xx_leds); + platform_device_register(&rut1xx_keys_device); + platform_register_rtc(); ++ platform_register_watchdog(); + } + + MACHINE_START(RUT100, "Teltonika RUT100") diff --git a/target/linux/gemini/patches-3.18/120-net-add-gemini-gmac-driver.patch b/target/linux/gemini/patches-3.18/120-net-add-gemini-gmac-driver.patch new file mode 100644 index 0000000..5f916ab --- /dev/null +++ b/target/linux/gemini/patches-3.18/120-net-add-gemini-gmac-driver.patch @@ -0,0 +1,3953 @@ +--- /dev/null ++++ b/arch/arm/mach-gemini/include/mach/gmac.h +@@ -0,0 +1,21 @@ ++/* ++ * Gemini GMAC specific defines ++ * ++ * Copyright (C) 2008, Paulius Zaleckas ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#ifndef __NET_GEMINI_PLATFORM_H__ ++#define __NET_GEMINI_PLATFORM_H__ ++ ++#include ++ ++struct gemini_gmac_platform_data { ++ char *bus_id[2]; /* NULL means that this port is not used */ ++ phy_interface_t interface[2]; ++}; ++ ++#endif /* __NET_GEMINI_PLATFORM_H__ */ +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -13,6 +13,7 @@ + #define __GEMINI_COMMON_H__ + + struct mtd_partition; ++struct gemini_gmac_platform_data; + + extern void gemini_map_io(void); + extern void gemini_init_irq(void); +@@ -26,6 +27,7 @@ extern int platform_register_pflash(unsi + struct mtd_partition *parts, + unsigned int nr_parts); + extern int platform_register_watchdog(void); ++extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata); + + extern void gemini_restart(enum reboot_mode mode, const char *cmd); + +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include "common.h" + + static struct plat_serial8250_port serial_platform_data[] = { +@@ -134,3 +135,56 @@ int __init platform_register_watchdog(vo + { + return platform_device_register(&wdt_device); + } ++ ++static struct resource gmac_resources[] = { ++ { ++ .start = GEMINI_TOE_BASE, ++ .end = GEMINI_TOE_BASE + 0xffff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IRQ_GMAC0, ++ .end = IRQ_GMAC0, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .start = IRQ_GMAC1, ++ .end = IRQ_GMAC1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 gmac_dmamask = 0xffffffffUL; ++ ++static struct platform_device ethernet_device = { ++ .name = "gmac-gemini", ++ .id = 0, ++ .dev = { ++ .dma_mask = &gmac_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(gmac_resources), ++ .resource = gmac_resources, ++}; ++ ++int platform_register_ethernet(struct gemini_gmac_platform_data *pdata) ++{ ++ unsigned int reg; ++ ++ reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ ++ reg &= ~(GMAC_GMII | GMAC_1_ENABLE); ++ ++ if (pdata->bus_id[1]) ++ reg |= GMAC_1_ENABLE; ++ else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII) ++ reg |= GMAC_GMII; ++ ++ writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ ++ ethernet_device.dev.platform_data = pdata; ++ ++ return platform_device_register(ðernet_device); ++} +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -70,6 +70,7 @@ source "drivers/net/ethernet/neterion/Kc + source "drivers/net/ethernet/faraday/Kconfig" + source "drivers/net/ethernet/freescale/Kconfig" + source "drivers/net/ethernet/fujitsu/Kconfig" ++source "drivers/net/ethernet/gemini/Kconfig" + source "drivers/net/ethernet/hisilicon/Kconfig" + source "drivers/net/ethernet/hp/Kconfig" + source "drivers/net/ethernet/ibm/Kconfig" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_NET_VENDOR_EXAR) += neterio + obj-$(CONFIG_NET_VENDOR_FARADAY) += faraday/ + obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/ + obj-$(CONFIG_NET_VENDOR_FUJITSU) += fujitsu/ ++obj-$(CONFIG_NET_VENDOR_GEMINI) += gemini/ + obj-$(CONFIG_NET_VENDOR_HISILICON) += hisilicon/ + obj-$(CONFIG_NET_VENDOR_HP) += hp/ + obj-$(CONFIG_NET_VENDOR_IBM) += ibm/ +--- /dev/null ++++ b/drivers/net/ethernet/gemini/Kconfig +@@ -0,0 +1,31 @@ ++# ++# Gemini device configuration ++# ++ ++config NET_VENDOR_GEMINI ++ bool "Cortina Gemini devices" ++ default y ++ depends on ARCH_GEMINI ++ ---help--- ++ If you have a network (Ethernet) card belonging to this class, say Y ++ and read the Ethernet-HOWTO, available from ++ . ++ ++ Note that the answer to this question doesn't directly affect the ++ kernel: saying N will just cause the configurator to skip all ++ the questions about D-Link devices. If you say Y, you will be asked for ++ your specific card in the following questions. ++ ++if NET_VENDOR_GEMINI ++ ++config GEMINI_SL351X ++ tristate "StorLink SL351x Gigabit Ethernet support" ++ depends on ARCH_GEMINI ++ select PHYLIB ++ select MDIO_BITBANG ++ select MDIO_GPIO ++ select CRC32 ++ ---help--- ++ This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet. ++ ++endif # NET_VENDOR_GEMINI +--- /dev/null ++++ b/drivers/net/ethernet/gemini/Makefile +@@ -0,0 +1,5 @@ ++# ++# Makefile for the Cortina Gemini network device drivers. ++# ++ ++obj-$(CONFIG_GEMINI_SL351X) += sl351x.o +--- /dev/null ++++ b/drivers/net/ethernet/gemini/sl351x.c +@@ -0,0 +1,2340 @@ ++/* ++ * Ethernet device driver for Gemini SoC (SL351x GMAC). ++ * ++ * Copyright (C) 2011, Tobias Waldvogel ++ * ++ * Based on work by MichaÅ‚ MirosÅ‚aw and ++ * Paulius Zaleckas and ++ * Giuseppe De Robertis and ++ * GPLd spaghetti code from Raidsonic and other Gemini-based NAS vendors. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include "sl351x_hw.h" ++ ++#define DRV_NAME "gmac-gemini" ++#define DRV_VERSION "1.0" ++ ++#define HSIZE_8 0b00 ++#define HSIZE_16 0b01 ++#define HSIZE_32 0b10 ++ ++#define HBURST_SINGLE 0b00 ++#define HBURST_INCR 0b01 ++#define HBURST_INCR4 0b10 ++#define HBURST_INCR8 0b11 ++ ++#define HPROT_DATA_CACHE BIT(0) ++#define HPROT_PRIVILIGED BIT(1) ++#define HPROT_BUFFERABLE BIT(2) ++#define HPROT_CACHABLE BIT(3) ++ ++#define DEFAULT_RX_COALESCE_NSECS 0 ++#define DEFAULT_GMAC_RXQ_ORDER 9 ++#define DEFAULT_GMAC_TXQ_ORDER 8 ++#define DEFAULT_RX_BUF_ORDER 11 ++#define DEFAULT_NAPI_WEIGHT 64 ++#define TX_MAX_FRAGS 16 ++#define TX_QUEUE_NUM 1 /* max: 6 */ ++#define RX_MAX_ALLOC_ORDER 2 ++ ++#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT|GMAC0_TXPERR_INT_BIT| \ ++ GMAC0_RXDERR_INT_BIT|GMAC0_RXPERR_INT_BIT) ++#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT| \ ++ GMAC0_SWTQ00_FIN_INT_BIT) ++#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT|GMAC0_RX_OVERRUN_INT_BIT) ++ ++#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \ ++ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \ ++ NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) ++ ++MODULE_AUTHOR("Tobias Waldvogel"); ++MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" DRV_NAME); ++ ++struct toe_private { ++ void __iomem *iomem; ++ spinlock_t irq_lock; ++ ++ struct net_device *netdev[2]; ++ __le32 mac_addr[2][3]; ++ ++ struct device *dev; ++ int irq; ++ ++ unsigned int freeq_order; ++ unsigned int freeq_frag_order; ++ GMAC_RXDESC_T *freeq_ring; ++ dma_addr_t freeq_dma_base; ++ struct page **freeq_page_tab; ++ spinlock_t freeq_lock; ++}; ++ ++struct gmac_txq { ++ GMAC_TXDESC_T *ring; ++ struct sk_buff **skb; ++ unsigned int cptr; ++ unsigned int noirq_packets; ++}; ++ ++struct gmac_private { ++ unsigned int num; ++ struct toe_private *toe; ++ void __iomem *ctl_iomem; ++ void __iomem *dma_iomem; ++ ++ void __iomem *rxq_rwptr; ++ GMAC_RXDESC_T *rxq_ring; ++ unsigned int rxq_order; ++ ++ struct napi_struct napi; ++ struct hrtimer rx_coalesce_timer; ++ unsigned int rx_coalesce_nsecs; ++ unsigned int freeq_refill; ++ struct gmac_txq txq[TX_QUEUE_NUM]; ++ unsigned int txq_order; ++ unsigned int irq_every_tx_packets; ++ ++ dma_addr_t rxq_dma_base; ++ dma_addr_t txq_dma_base; ++ ++ unsigned int msg_enable; ++ spinlock_t config_lock; ++ ++ struct u64_stats_sync tx_stats_syncp; ++ struct u64_stats_sync rx_stats_syncp; ++ struct u64_stats_sync ir_stats_syncp; ++ ++ struct rtnl_link_stats64 stats; ++ u64 hw_stats[RX_STATS_NUM]; ++ u64 rx_stats[RX_STATUS_NUM]; ++ u64 rx_csum_stats[RX_CHKSUM_NUM]; ++ u64 rx_napi_exits; ++ u64 tx_frag_stats[TX_MAX_FRAGS]; ++ u64 tx_frags_linearized; ++ u64 tx_hw_csummed; ++}; ++ ++#define GMAC_STATS_NUM ( \ ++ RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \ ++ TX_MAX_FRAGS + 2) ++ ++static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = { ++ "GMAC_IN_DISCARDS", ++ "GMAC_IN_ERRORS", ++ "GMAC_IN_MCAST", ++ "GMAC_IN_BCAST", ++ "GMAC_IN_MAC1", ++ "GMAC_IN_MAC2", ++ "RX_STATUS_GOOD_FRAME", ++ "RX_STATUS_TOO_LONG_GOOD_CRC", ++ "RX_STATUS_RUNT_FRAME", ++ "RX_STATUS_SFD_NOT_FOUND", ++ "RX_STATUS_CRC_ERROR", ++ "RX_STATUS_TOO_LONG_BAD_CRC", ++ "RX_STATUS_ALIGNMENT_ERROR", ++ "RX_STATUS_TOO_LONG_BAD_ALIGN", ++ "RX_STATUS_RX_ERR", ++ "RX_STATUS_DA_FILTERED", ++ "RX_STATUS_BUFFER_FULL", ++ "RX_STATUS_11", ++ "RX_STATUS_12", ++ "RX_STATUS_13", ++ "RX_STATUS_14", ++ "RX_STATUS_15", ++ "RX_CHKSUM_IP_UDP_TCP_OK", ++ "RX_CHKSUM_IP_OK_ONLY", ++ "RX_CHKSUM_NONE", ++ "RX_CHKSUM_3", ++ "RX_CHKSUM_IP_ERR_UNKNOWN", ++ "RX_CHKSUM_IP_ERR", ++ "RX_CHKSUM_TCP_UDP_ERR", ++ "RX_CHKSUM_7", ++ "RX_NAPI_EXITS", ++ "TX_FRAGS[1]", ++ "TX_FRAGS[2]", ++ "TX_FRAGS[3]", ++ "TX_FRAGS[4]", ++ "TX_FRAGS[5]", ++ "TX_FRAGS[6]", ++ "TX_FRAGS[7]", ++ "TX_FRAGS[8]", ++ "TX_FRAGS[9]", ++ "TX_FRAGS[10]", ++ "TX_FRAGS[11]", ++ "TX_FRAGS[12]", ++ "TX_FRAGS[13]", ++ "TX_FRAGS[14]", ++ "TX_FRAGS[15]", ++ "TX_FRAGS[16+]", ++ "TX_FRAGS_LINEARIZED", ++ "TX_HW_CSUMMED", ++}; ++ ++static void gmac_dump_dma_state(struct net_device *dev); ++ ++static void gmac_update_config0_reg(struct net_device *dev, u32 val, u32 vmask) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ reg = (reg & ~vmask) | val; ++ writel(reg, gmac->ctl_iomem + GMAC_CONFIG0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++} ++ ++static void gmac_enable_tx_rx(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0; ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(config0); ++ reg &= ~CONFIG0_TX_RX_DISABLE; ++ writel(reg, config0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++} ++ ++static void gmac_disable_tx_rx(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0; ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(config0); ++ reg |= CONFIG0_TX_RX_DISABLE; ++ writel(reg, config0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++ ++ mdelay(10); /* let GMAC consume packet */ ++} ++ ++static void gmac_set_flow_control(struct net_device *dev, bool tx, bool rx) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0; ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(config0); ++ reg &= ~CONFIG0_FLOW_CTL; ++ if (tx) ++ reg |= CONFIG0_FLOW_TX; ++ if (rx) ++ reg |= CONFIG0_FLOW_RX; ++ writel(reg, config0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++} ++ ++static void gmac_update_link_state(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ void __iomem *status_reg = gmac->ctl_iomem + GMAC_STATUS; ++ struct phy_device *phydev = dev->phydev; ++ GMAC_STATUS_T status, old_status; ++ int pause_tx=0, pause_rx=0; ++ ++ old_status.bits32 = status.bits32 = readl(status_reg); ++ ++ status.bits.link = phydev->link; ++ status.bits.duplex = phydev->duplex; ++ ++ switch (phydev->speed) { ++ case 1000: ++ status.bits.speed = GMAC_SPEED_1000; ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) ++ status.bits.mii_rmii = GMAC_PHY_RGMII_1000; ++ break; ++ case 100: ++ status.bits.speed = GMAC_SPEED_100; ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) ++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; ++ break; ++ case 10: ++ status.bits.speed = GMAC_SPEED_10; ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) ++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; ++ break; ++ default: ++ netdev_warn(dev, "Not supported PHY speed (%d)\n", ++ phydev->speed); ++ } ++ ++ if (phydev->duplex == DUPLEX_FULL) { ++ u16 lcladv = phy_read(phydev, MII_ADVERTISE); ++ u16 rmtadv = phy_read(phydev, MII_LPA); ++ u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); ++ ++ if (cap & FLOW_CTRL_RX) ++ pause_rx=1; ++ if (cap & FLOW_CTRL_TX) ++ pause_tx=1; ++ } ++ ++ gmac_set_flow_control(dev, pause_tx, pause_rx); ++ ++ if (old_status.bits32 == status.bits32) ++ return; ++ ++ if (netif_msg_link(gmac)) { ++ phy_print_status(phydev); ++ netdev_info(dev, "link flow control: %s\n", ++ phydev->pause ++ ? (phydev->asym_pause ? "tx" : "both") ++ : (phydev->asym_pause ? "rx" : "none") ++ ); ++ } ++ ++ gmac_disable_tx_rx(dev); ++ writel(status.bits32, status_reg); ++ gmac_enable_tx_rx(dev); ++} ++ ++static int gmac_setup_phy(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ struct gemini_gmac_platform_data *pdata = toe->dev->platform_data; ++ GMAC_STATUS_T status = { .bits32 = 0 }; ++ int num = dev->dev_id; ++ ++ dev->phydev = phy_connect(dev, pdata->bus_id[num], ++ &gmac_update_link_state, pdata->interface[num]); ++ ++ if (IS_ERR(dev->phydev)) { ++ int err = PTR_ERR(dev->phydev); ++ dev->phydev = NULL; ++ return err; ++ } ++ ++ dev->phydev->supported &= PHY_GBIT_FEATURES; ++ dev->phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; ++ dev->phydev->advertising = dev->phydev->supported; ++ ++ /* set PHY interface type */ ++ switch (dev->phydev->interface) { ++ case PHY_INTERFACE_MODE_MII: ++ status.bits.mii_rmii = GMAC_PHY_MII; ++ break; ++ case PHY_INTERFACE_MODE_GMII: ++ status.bits.mii_rmii = GMAC_PHY_GMII; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; ++ break; ++ default: ++ netdev_err(dev, "Unsupported MII interface\n"); ++ phy_disconnect(dev->phydev); ++ dev->phydev = NULL; ++ return -EINVAL; ++ } ++ writel(status.bits32, gmac->ctl_iomem + GMAC_STATUS); ++ ++ return 0; ++} ++ ++static int gmac_pick_rx_max_len(int max_l3_len) ++{ ++ /* index = CONFIG_MAXLEN_XXX values */ ++ static const int max_len[8] = { ++ 1536, 1518, 1522, 1542, ++ 9212, 10236, 1518, 1518 ++ }; ++ int i, n = 5; ++ ++ max_l3_len += ETH_HLEN + VLAN_HLEN; ++ ++ if (max_l3_len > max_len[n]) ++ return -1; ++ ++ for (i = 0; i < 5; ++i) { ++ if (max_len[i] >= max_l3_len && max_len[i] < max_len[n]) ++ n = i; ++ } ++ ++ return n; ++} ++ ++static int gmac_init(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ u32 val; ++ ++ GMAC_CONFIG0_T config0 = { .bits = { ++ .dis_tx = 1, ++ .dis_rx = 1, ++ .ipv4_rx_chksum = 1, ++ .ipv6_rx_chksum = 1, ++ .rx_err_detect = 1, ++ .rgmm_edge = 1, ++ .port0_chk_hwq = 1, ++ .port1_chk_hwq = 1, ++ .port0_chk_toeq = 1, ++ .port1_chk_toeq = 1, ++ .port0_chk_classq = 1, ++ .port1_chk_classq = 1, ++ } }; ++ GMAC_AHB_WEIGHT_T ahb_weight = { .bits = { ++ .rx_weight = 1, ++ .tx_weight = 1, ++ .hash_weight = 1, ++ .pre_req = 0x1f, ++ .tqDV_threshold = 0, ++ } }; ++ GMAC_TX_WCR0_T hw_weigh = { .bits = { ++ .hw_tq3 = 1, ++ .hw_tq2 = 1, ++ .hw_tq1 = 1, ++ .hw_tq0 = 1, ++ } }; ++ GMAC_TX_WCR1_T sw_weigh = { .bits = { ++ .sw_tq5 = 1, ++ .sw_tq4 = 1, ++ .sw_tq3 = 1, ++ .sw_tq2 = 1, ++ .sw_tq1 = 1, ++ .sw_tq0 = 1, ++ } }; ++ GMAC_CONFIG1_T config1 = { .bits = { ++ .set_threshold = 16, ++ .rel_threshold = 24, ++ } }; ++ GMAC_CONFIG2_T config2 = { .bits = { ++ .set_threshold = 16, ++ .rel_threshold = 32, ++ } }; ++ GMAC_CONFIG3_T config3 = { .bits = { ++ .set_threshold = 0, ++ .rel_threshold = 0, ++ } }; ++ ++ config0.bits.max_len = gmac_pick_rx_max_len(dev->mtu); ++ ++ val = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ config0.bits.reserved = ((GMAC_CONFIG0_T)val).bits.reserved; ++ writel(config0.bits32, gmac->ctl_iomem + GMAC_CONFIG0); ++ writel(config1.bits32, gmac->ctl_iomem + GMAC_CONFIG1); ++ writel(config2.bits32, gmac->ctl_iomem + GMAC_CONFIG2); ++ writel(config3.bits32, gmac->ctl_iomem + GMAC_CONFIG3); ++ ++ val = readl(gmac->dma_iomem + GMAC_AHB_WEIGHT_REG); ++ writel(ahb_weight.bits32, gmac->dma_iomem + GMAC_AHB_WEIGHT_REG); ++ ++ writel(hw_weigh.bits32, ++ gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_0_REG); ++ writel(sw_weigh.bits32, ++ gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_1_REG); ++ ++ gmac->rxq_order = DEFAULT_GMAC_RXQ_ORDER; ++ gmac->txq_order = DEFAULT_GMAC_TXQ_ORDER; ++ gmac->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS; ++ ++ /* Mark every quarter of the queue a packet for interrupt ++ in order to be able to wake up the queue if it was stopped */ ++ gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2); ++ ++ return 0; ++} ++ ++static void gmac_uninit(struct net_device *dev) ++{ ++ if (dev->phydev) ++ phy_disconnect(dev->phydev); ++} ++ ++static int gmac_setup_txqs(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG; ++ void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG; ++ ++ unsigned int n_txq = dev->num_tx_queues; ++ size_t entries = 1 <txq_order; ++ size_t len = n_txq * entries; ++ struct gmac_txq *txq = gmac->txq; ++ GMAC_TXDESC_T *desc_ring; ++ struct sk_buff **skb_tab; ++ unsigned int r; ++ int i; ++ ++ skb_tab = kzalloc(len * sizeof(*skb_tab), GFP_KERNEL); ++ if (!skb_tab) ++ return -ENOMEM; ++ ++ desc_ring = dma_alloc_coherent(toe->dev, len * sizeof(*desc_ring), ++ &gmac->txq_dma_base, GFP_KERNEL); ++ ++ if (!desc_ring) { ++ kfree(skb_tab); ++ return -ENOMEM; ++ } ++ ++ BUG_ON(gmac->txq_dma_base & ~DMA_Q_BASE_MASK); ++ ++ writel(gmac->txq_dma_base | gmac->txq_order, base_reg); ++ ++ for (i = 0; i < n_txq; i++) { ++ txq->ring = desc_ring; ++ txq->skb = skb_tab; ++ txq->noirq_packets = 0; ++ ++ r = readw(rwptr_reg); ++ rwptr_reg += 2; ++ writew(r, rwptr_reg); ++ rwptr_reg +=2; ++ txq->cptr = r; ++ ++ txq++; ++ desc_ring += entries; ++ skb_tab += entries; ++ } ++ ++ return 0; ++} ++ ++static void gmac_clean_txq(struct net_device *dev, struct gmac_txq *txq, ++ unsigned int r) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned int errs = 0; ++ unsigned int pkts = 0; ++ unsigned int hwchksum = 0; ++ unsigned long bytes = 0; ++ unsigned int m = (1 << gmac->txq_order) - 1; ++ unsigned int c = txq->cptr; ++ GMAC_TXDESC_0_T word0; ++ GMAC_TXDESC_1_T word1; ++ unsigned int word3; ++ dma_addr_t mapping; ++ GMAC_TXDESC_T *txd; ++ unsigned short nfrags; ++ ++ if (unlikely(c == r)) ++ return; ++ ++ rmb(); ++ while (c != r) { ++ txd = txq->ring + c; ++ word0 = txd->word0; ++ word1 = txd->word1; ++ mapping = txd->word2.buf_adr; ++ word3 = txd->word3.bits32; ++ ++ dma_unmap_single(toe->dev, mapping, word0.bits.buffer_size, DMA_TO_DEVICE); ++ ++ if (word3 & EOF_BIT) ++ dev_kfree_skb(txq->skb[c]); ++ ++ c++; ++ c &= m; ++ ++ if (!(word3 & SOF_BIT)) ++ continue; ++ ++ if (!word0.bits.status_tx_ok) { ++ errs++; ++ continue; ++ } ++ ++ pkts++; ++ bytes += txd->word1.bits.byte_count; ++ ++ if (word1.bits32 & TSS_CHECKUM_ENABLE) ++ hwchksum++; ++ ++ nfrags = word0.bits.desc_count - 1; ++ if (nfrags) { ++ if (nfrags >= TX_MAX_FRAGS) ++ nfrags = TX_MAX_FRAGS - 1; ++ ++ u64_stats_update_begin(&gmac->tx_stats_syncp); ++ gmac->tx_frag_stats[nfrags]++; ++ u64_stats_update_end(&gmac->ir_stats_syncp); ++ } ++ } ++ ++ u64_stats_update_begin(&gmac->ir_stats_syncp); ++ gmac->stats.tx_errors += errs; ++ gmac->stats.tx_packets += pkts; ++ gmac->stats.tx_bytes += bytes; ++ gmac->tx_hw_csummed += hwchksum; ++ u64_stats_update_end(&gmac->ir_stats_syncp); ++ ++ txq->cptr = c; ++} ++ ++static void gmac_cleanup_txqs(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG; ++ void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG; ++ ++ unsigned n_txq = dev->num_tx_queues; ++ unsigned int r, i; ++ ++ for (i = 0; i < n_txq; i++) { ++ r = readw(rwptr_reg); ++ rwptr_reg += 2; ++ writew(r, rwptr_reg); ++ rwptr_reg += 2; ++ ++ gmac_clean_txq(dev, gmac->txq + i, r); ++ } ++ writel(0, base_reg); ++ ++ kfree(gmac->txq->skb); ++ dma_free_coherent(toe->dev, ++ n_txq * sizeof(*gmac->txq->ring) << gmac->txq_order, ++ gmac->txq->ring, gmac->txq_dma_base); ++} ++ ++static int gmac_setup_rxq(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id); ++ ++ gmac->rxq_rwptr = &qhdr->word1; ++ gmac->rxq_ring = dma_alloc_coherent(toe->dev, ++ sizeof(*gmac->rxq_ring) << gmac->rxq_order, ++ &gmac->rxq_dma_base, GFP_KERNEL); ++ if (!gmac->rxq_ring) ++ return -ENOMEM; ++ ++ BUG_ON(gmac->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK); ++ ++ writel(gmac->rxq_dma_base | gmac->rxq_order, &qhdr->word0); ++ writel(0, gmac->rxq_rwptr); ++ return 0; ++} ++ ++static void gmac_cleanup_rxq(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ ++ NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id); ++ void __iomem *dma_reg = &qhdr->word0; ++ void __iomem *ptr_reg = &qhdr->word1; ++ GMAC_RXDESC_T *rxd = gmac->rxq_ring; ++ DMA_RWPTR_T rw; ++ unsigned int r, w; ++ unsigned int m = (1 <rxq_order) - 1; ++ struct page *page; ++ dma_addr_t mapping; ++ ++ rw.bits32 = readl(ptr_reg); ++ r = rw.bits.rptr; ++ w = rw.bits.wptr; ++ writew(r, ptr_reg + 2); ++ ++ writel(0, dma_reg); ++ ++ rmb(); ++ while (r != w) { ++ mapping = rxd[r].word2.buf_adr; ++ r++; ++ r &= m; ++ ++ if (!mapping) ++ continue; ++ ++ page = pfn_to_page(dma_to_pfn(toe->dev, mapping)); ++ put_page(page); ++ } ++ ++ dma_free_coherent(toe->dev, sizeof(*gmac->rxq_ring) << gmac->rxq_order, ++ gmac->rxq_ring, gmac->rxq_dma_base); ++} ++ ++static struct page *toe_freeq_alloc_map_page(struct toe_private *toe, int pn) ++{ ++ unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order; ++ unsigned int frag_len = 1 << toe->freeq_frag_order; ++ GMAC_RXDESC_T *freeq_entry; ++ dma_addr_t mapping; ++ struct page *page; ++ int i; ++ ++ page = alloc_page(__GFP_COLD | GFP_ATOMIC); ++ if (!page) ++ return NULL; ++ ++ mapping = dma_map_single(toe->dev, page_address(page), ++ PAGE_SIZE, DMA_FROM_DEVICE); ++ ++ if (unlikely(dma_mapping_error(toe->dev, mapping) || !mapping)) { ++ put_page(page); ++ return NULL; ++ } ++ ++ freeq_entry = toe->freeq_ring + (pn << fpp_order); ++ for (i = 1 << fpp_order; i > 0; --i) { ++ freeq_entry->word2.buf_adr = mapping; ++ freeq_entry++; ++ mapping += frag_len; ++ } ++ ++ if (toe->freeq_page_tab[pn]) { ++ mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr; ++ dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE); ++ put_page(toe->freeq_page_tab[pn]); ++ } ++ ++ toe->freeq_page_tab[pn] = page; ++ return page; ++} ++ ++static unsigned int toe_fill_freeq(struct toe_private *toe, int reset) ++{ ++ void __iomem *rwptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG; ++ ++ DMA_RWPTR_T rw; ++ unsigned int pn, epn; ++ unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order; ++ unsigned int m_pn = (1 << (toe->freeq_order - fpp_order)) - 1; ++ struct page *page; ++ unsigned int count = 0; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&toe->freeq_lock, flags); ++ ++ rw.bits32 = readl(rwptr_reg); ++ pn = (reset ? rw.bits.rptr : rw.bits.wptr) >> fpp_order; ++ epn = (rw.bits.rptr >> fpp_order) - 1; ++ epn &= m_pn; ++ ++ while (pn != epn) { ++ page = toe->freeq_page_tab[pn]; ++ ++ if (atomic_read(&page->_count) > 1) { ++ unsigned int fl = (pn -epn) & m_pn; ++ ++ if (fl > 64 >> fpp_order) ++ break; ++ ++ page = toe_freeq_alloc_map_page(toe, pn); ++ if (!page) ++ break; ++ } ++ ++ atomic_add(1 << fpp_order, &page->_count); ++ count += 1 << fpp_order; ++ pn++; ++ pn &= m_pn; ++ } ++ ++ wmb(); ++ writew(pn << fpp_order, rwptr_reg+2); ++ ++ spin_unlock_irqrestore(&toe->freeq_lock, flags); ++ return count; ++} ++ ++static int toe_setup_freeq(struct toe_private *toe) ++{ ++ void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG; ++ QUEUE_THRESHOLD_T qt; ++ DMA_SKB_SIZE_T skbsz; ++ unsigned int filled; ++ unsigned int frag_len = 1 << toe->freeq_frag_order; ++ unsigned int len = 1 << toe->freeq_order; ++ unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order; ++ unsigned int pages = len >> fpp_order; ++ dma_addr_t mapping; ++ unsigned int pn; ++ ++ toe->freeq_ring = dma_alloc_coherent(toe->dev, ++ sizeof(*toe->freeq_ring) << toe->freeq_order, ++ &toe->freeq_dma_base, GFP_KERNEL); ++ if (!toe->freeq_ring) ++ return -ENOMEM; ++ ++ BUG_ON(toe->freeq_dma_base & ~DMA_Q_BASE_MASK); ++ ++ toe->freeq_page_tab = kzalloc(pages * sizeof(*toe->freeq_page_tab), ++ GFP_KERNEL); ++ if (!toe->freeq_page_tab) ++ goto err_freeq; ++ ++ for (pn = 0; pn < pages; pn++) ++ if (!toe_freeq_alloc_map_page(toe, pn)) ++ goto err_freeq_alloc; ++ ++ filled = toe_fill_freeq(toe, 1); ++ if (!filled) ++ goto err_freeq_alloc; ++ ++ qt.bits32 = readl(toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG); ++ qt.bits.swfq_empty = 32; ++ writel(qt.bits32, toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG); ++ ++ skbsz.bits.sw_skb_size = 1 << toe->freeq_frag_order; ++ writel(skbsz.bits32, toe->iomem + GLOBAL_DMA_SKB_SIZE_REG); ++ writel(toe->freeq_dma_base | toe->freeq_order, dma_reg); ++ ++ return 0; ++ ++err_freeq_alloc: ++ while (pn > 0) { ++ --pn; ++ mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr; ++ dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE); ++ put_page(toe->freeq_page_tab[pn]); ++ } ++ ++err_freeq: ++ dma_free_coherent(toe->dev, ++ sizeof(*toe->freeq_ring) << toe->freeq_order, ++ toe->freeq_ring, toe->freeq_dma_base); ++ toe->freeq_ring = NULL; ++ return -ENOMEM; ++} ++ ++static void toe_cleanup_freeq(struct toe_private *toe) ++{ ++ void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG; ++ void __iomem *ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG; ++ ++ unsigned int frag_len = 1 << toe->freeq_frag_order; ++ unsigned int len = 1 << toe->freeq_order; ++ unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order; ++ unsigned int pages = len >> fpp_order; ++ struct page *page; ++ dma_addr_t mapping; ++ unsigned int pn; ++ ++ writew(readw(ptr_reg), ptr_reg + 2); ++ writel(0, dma_reg); ++ ++ for (pn = 0; pn < pages; pn++) { ++ mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr; ++ dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE); ++ ++ page = toe->freeq_page_tab[pn]; ++ while (atomic_read(&page->_count) > 0) ++ put_page(page); ++ } ++ ++ kfree(toe->freeq_page_tab); ++ ++ dma_free_coherent(toe->dev, ++ sizeof(*toe->freeq_ring) << toe->freeq_order, ++ toe->freeq_ring, toe->freeq_dma_base); ++} ++ ++static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id) ++{ ++ void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG; ++ struct gmac_private *gmac; ++ struct net_device *other = toe->netdev[1 - changing_dev_id]; ++ unsigned new_size = 0; ++ unsigned new_order; ++ int err; ++ unsigned long flags; ++ unsigned en; ++ ++ if (other && netif_running(other)) ++ return -EBUSY; ++ ++ if (toe->netdev[0]) { ++ gmac = netdev_priv(toe->netdev[0]); ++ new_size = 1 << (gmac->rxq_order + 1); ++ } ++ ++ if (toe->netdev[1]) { ++ gmac = netdev_priv(toe->netdev[1]); ++ new_size += 1 << (gmac->rxq_order + 1); ++ } ++ ++ new_order = min(15, ilog2(new_size - 1) + 1); ++ if (toe->freeq_order == new_order) ++ return 0; ++ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ en = readl(irqen_reg); ++ en &= ~SWFQ_EMPTY_INT_BIT; ++ writel(en, irqen_reg); ++ ++ if (toe->freeq_ring) ++ toe_cleanup_freeq(toe); ++ ++ toe->freeq_order = new_order; ++ err = toe_setup_freeq(toe); ++ ++ en |= SWFQ_EMPTY_INT_BIT; ++ writel(en, irqen_reg); ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++ ++ return err; ++} ++ ++static void gmac_tx_irq_enable(struct net_device *dev, unsigned txq, int en) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned val, mask; ++ ++ mask = GMAC0_IRQ0_TXQ0_INTS << (6 * dev->dev_id + txq); ++ ++ if (en) ++ writel(mask, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG); ++ ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ val = en ? val | mask : val & ~mask; ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++} ++ ++ ++static void gmac_tx_irq(struct net_device *dev, unsigned txq_num) ++{ ++ struct netdev_queue *ntxq = netdev_get_tx_queue(dev, txq_num); ++ ++ gmac_tx_irq_enable(dev, txq_num, 0); ++ netif_tx_wake_queue(ntxq); ++} ++ ++static int gmac_map_tx_bufs(struct net_device *dev, struct sk_buff *skb, ++ struct gmac_txq *txq, unsigned short *desc) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ struct skb_shared_info *skb_si = skb_shinfo(skb); ++ skb_frag_t *skb_frag; ++ short frag, last_frag = skb_si->nr_frags - 1; ++ unsigned short m = (1 << gmac->txq_order) -1; ++ unsigned short w = *desc; ++ unsigned word1, word3, buflen; ++ dma_addr_t mapping; ++ void *buffer; ++ unsigned short mtu; ++ GMAC_TXDESC_T *txd; ++ ++ mtu = ETH_HLEN; ++ mtu += dev->mtu; ++ if (skb->protocol == htons(ETH_P_8021Q)) ++ mtu += VLAN_HLEN; ++ ++ word1 = skb->len; ++ word3 = SOF_BIT; ++ ++ if (word1 > mtu) { ++ word1 |= TSS_MTU_ENABLE_BIT; ++ word3 += mtu; ++ } ++ ++ if (skb->ip_summed != CHECKSUM_NONE) { ++ int tcp = 0; ++ if (skb->protocol == htons(ETH_P_IP)) { ++ word1 |= TSS_IP_CHKSUM_BIT; ++ tcp = ip_hdr(skb)->protocol == IPPROTO_TCP; ++ } else { /* IPv6 */ ++ word1 |= TSS_IPV6_ENABLE_BIT; ++ tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP; ++ } ++ ++ word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT; ++ } ++ ++ frag = -1; ++ while (frag <= last_frag) { ++ if (frag == -1) { ++ buffer = skb->data; ++ buflen = skb_headlen(skb); ++ } else { ++ skb_frag = skb_si->frags + frag; ++ buffer = page_address(skb_frag_page(skb_frag)) + ++ skb_frag->page_offset; ++ buflen = skb_frag->size; ++ } ++ ++ if (frag == last_frag) { ++ word3 |= EOF_BIT; ++ txq->skb[w] = skb; ++ } ++ ++ mapping = dma_map_single(toe->dev, buffer, buflen, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(toe->dev, mapping) || ++ !(mapping & PAGE_MASK)) ++ goto map_error; ++ ++ txd = txq->ring + w; ++ txd->word0.bits32 = buflen; ++ txd->word1.bits32 = word1; ++ txd->word2.buf_adr = mapping; ++ txd->word3.bits32 = word3; ++ ++ word3 &= MTU_SIZE_BIT_MASK; ++ w++; ++ w &= m; ++ frag++; ++ } ++ ++ *desc = w; ++ return 0; ++ ++map_error: ++ while (w != *desc) { ++ w--; ++ w &= m; ++ ++ dma_unmap_page(toe->dev, txq->ring[w].word2.buf_adr, ++ txq->ring[w].word0.bits.buffer_size, DMA_TO_DEVICE); ++ } ++ return ENOMEM; ++} ++ ++static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ void __iomem *ptr_reg; ++ struct gmac_txq *txq; ++ struct netdev_queue *ntxq; ++ int txq_num, nfrags; ++ DMA_RWPTR_T rw; ++ unsigned short r, w, d; ++ unsigned short m = (1 << gmac->txq_order) - 1; ++ ++ SKB_FRAG_ASSERT(skb); ++ ++ if (unlikely(skb->len >= 0x10000)) ++ goto out_drop_free; ++ ++ txq_num = skb_get_queue_mapping(skb); ++ ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_PTR_REG(txq_num); ++ txq = &gmac->txq[txq_num]; ++ ntxq = netdev_get_tx_queue(dev, txq_num); ++ nfrags = skb_shinfo(skb)->nr_frags; ++ ++ rw.bits32 = readl(ptr_reg); ++ r = rw.bits.rptr; ++ w = rw.bits.wptr; ++ ++ d = txq->cptr - w - 1; ++ d &= m; ++ ++ if (unlikely(d < nfrags+2)) ++ { ++ gmac_clean_txq(dev, txq, r); ++ d = txq->cptr - w - 1; ++ d &= m; ++ ++ if (unlikely(d < nfrags+2)) { ++ netif_tx_stop_queue(ntxq); ++ ++ d = txq->cptr + nfrags + 16; ++ d &= m; ++ txq->ring[d].word3.bits.eofie = 1; ++ gmac_tx_irq_enable(dev, txq_num, 1); ++ ++ u64_stats_update_begin(&gmac->tx_stats_syncp); ++ dev->stats.tx_fifo_errors++; ++ u64_stats_update_end(&gmac->tx_stats_syncp); ++ return NETDEV_TX_BUSY; ++ } ++ } ++ ++ if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w))) { ++ if (skb_linearize(skb)) ++ goto out_drop; ++ ++ if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w))) ++ goto out_drop_free; ++ ++ u64_stats_update_begin(&gmac->tx_stats_syncp); ++ gmac->tx_frags_linearized++; ++ u64_stats_update_end(&gmac->tx_stats_syncp); ++ } ++ ++ writew(w, ptr_reg+2); ++ ++ gmac_clean_txq(dev, txq, r); ++ return NETDEV_TX_OK; ++ ++out_drop_free: ++ dev_kfree_skb(skb); ++out_drop: ++ u64_stats_update_begin(&gmac->tx_stats_syncp); ++ gmac->stats.tx_dropped++; ++ u64_stats_update_end(&gmac->tx_stats_syncp); ++ return NETDEV_TX_OK; ++} ++ ++static void gmac_tx_timeout(struct net_device *dev) ++{ ++ netdev_err(dev, "Tx timeout\n"); ++ gmac_dump_dma_state(dev); ++} ++ ++static void gmac_enable_irq(struct net_device *dev, int enable) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned long flags; ++ unsigned val, mask; ++ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ ++ mask = GMAC0_IRQ0_2 << (dev->dev_id * 2); ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ val = enable ? (val | mask) : (val & ~mask); ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ ++ mask = DEFAULT_Q0_INT_BIT << dev->dev_id; ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ val = enable ? (val | mask) : (val & ~mask); ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ ++ mask = GMAC0_IRQ4_8 << (dev->dev_id * 8); ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG); ++ val = enable ? (val | mask) : (val & ~mask); ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG); ++ ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++} ++ ++static void gmac_enable_rx_irq(struct net_device *dev, int enable) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned long flags; ++ unsigned val, mask; ++ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ mask = DEFAULT_Q0_INT_BIT << dev->dev_id; ++ ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ val = enable ? (val | mask) : (val & ~mask); ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++} ++ ++static struct sk_buff *gmac_skb_if_good_frame(struct gmac_private *gmac, ++ GMAC_RXDESC_0_T word0, unsigned frame_len) ++{ ++ struct sk_buff *skb = NULL; ++ unsigned rx_status = word0.bits.status; ++ unsigned rx_csum = word0.bits.chksum_status; ++ ++ gmac->rx_stats[rx_status]++; ++ gmac->rx_csum_stats[rx_csum]++; ++ ++ if (word0.bits.derr || word0.bits.perr || ++ rx_status || frame_len < ETH_ZLEN || ++ rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) { ++ gmac->stats.rx_errors++; ++ ++ if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status)) ++ gmac->stats.rx_length_errors++; ++ if (RX_ERROR_OVER(rx_status)) ++ gmac->stats.rx_over_errors++; ++ if (RX_ERROR_CRC(rx_status)) ++ gmac->stats.rx_crc_errors++; ++ if (RX_ERROR_FRAME(rx_status)) ++ gmac->stats.rx_frame_errors++; ++ ++ return NULL; ++ } ++ ++ skb = napi_get_frags(&gmac->napi); ++ if (!skb) ++ return NULL; ++ ++ if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK) ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ ++ gmac->stats.rx_bytes += frame_len; ++ gmac->stats.rx_packets++; ++ return skb; ++} ++ ++static unsigned gmac_rx(struct net_device *dev, unsigned budget) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *ptr_reg = gmac->rxq_rwptr; ++ ++ static struct sk_buff *skb; ++ ++ DMA_RWPTR_T rw; ++ unsigned short r, w; ++ unsigned short m = (1 << gmac->rxq_order) -1; ++ GMAC_RXDESC_T *rx = NULL; ++ struct page* page = NULL; ++ unsigned page_offs; ++ unsigned int frame_len, frag_len; ++ int frag_nr = 0; ++ ++ GMAC_RXDESC_0_T word0; ++ GMAC_RXDESC_1_T word1; ++ dma_addr_t mapping; ++ GMAC_RXDESC_3_T word3; ++ ++ rw.bits32 = readl(ptr_reg); ++ /* Reset interrupt as all packages until here are taken into account */ ++ writel(DEFAULT_Q0_INT_BIT << dev->dev_id, ++ toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG); ++ r = rw.bits.rptr; ++ w = rw.bits.wptr; ++ ++ while (budget && w != r) { ++ rx = gmac->rxq_ring + r; ++ word0 = rx->word0; ++ word1 = rx->word1; ++ mapping = rx->word2.buf_adr; ++ word3 = rx->word3; ++ ++ r++; ++ r &= m; ++ ++ frag_len = word0.bits.buffer_size; ++ frame_len =word1.bits.byte_count; ++ page_offs = mapping & ~PAGE_MASK; ++ ++ if (unlikely(!mapping)) { ++ netdev_err(dev, "rxq[%u]: HW BUG: zero DMA desc\n", r); ++ goto err_drop; ++ } ++ ++ page = pfn_to_page(dma_to_pfn(toe->dev, mapping)); ++ ++ if (word3.bits32 & SOF_BIT) { ++ if (unlikely(skb)) { ++ napi_free_frags(&gmac->napi); ++ gmac->stats.rx_dropped++; ++ } ++ ++ skb = gmac_skb_if_good_frame(gmac, word0, frame_len); ++ if (unlikely(!skb)) ++ goto err_drop; ++ ++ page_offs += NET_IP_ALIGN; ++ frag_len -= NET_IP_ALIGN; ++ frag_nr = 0; ++ ++ } else if (!skb) { ++ put_page(page); ++ continue; ++ } ++ ++ if (word3.bits32 & EOF_BIT) ++ frag_len = frame_len - skb->len; ++ ++ /* append page frag to skb */ ++ if (unlikely(frag_nr == MAX_SKB_FRAGS)) ++ goto err_drop; ++ ++ if (frag_len == 0) ++ netdev_err(dev, "Received fragment with len = 0\n"); ++ ++ skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len); ++ skb->len += frag_len; ++ skb->data_len += frag_len; ++ skb->truesize += frag_len; ++ frag_nr++; ++ ++ if (word3.bits32 & EOF_BIT) { ++ napi_gro_frags(&gmac->napi); ++ skb = NULL; ++ --budget; ++ } ++ continue; ++ ++err_drop: ++ if (skb) { ++ napi_free_frags(&gmac->napi); ++ skb = NULL; ++ } ++ ++ if (mapping) ++ put_page(page); ++ ++ gmac->stats.rx_dropped++; ++ } ++ ++ writew(r, ptr_reg); ++ return budget; ++} ++ ++static int gmac_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct gmac_private *gmac = netdev_priv(napi->dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned rx; ++ unsigned freeq_threshold = 1 << (toe->freeq_order - 1); ++ ++ u64_stats_update_begin(&gmac->rx_stats_syncp); ++ ++ rx = budget - gmac_rx(napi->dev, budget); ++ ++ if (rx == 0) { ++ napi_gro_flush(napi, false); ++ __napi_complete(napi); ++ gmac_enable_rx_irq(napi->dev, 1); ++ ++gmac->rx_napi_exits; ++ } ++ ++ gmac->freeq_refill += rx; ++ if (gmac->freeq_refill > freeq_threshold) { ++ gmac->freeq_refill -= freeq_threshold; ++ toe_fill_freeq(toe, 0); ++ } ++ ++ u64_stats_update_end(&gmac->rx_stats_syncp); ++ return rx; ++} ++ ++static void gmac_dump_dma_state(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *ptr_reg; ++ unsigned reg[5]; ++ ++ /* Interrupt status */ ++ reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG); ++ reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG); ++ reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG); ++ reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG); ++ reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG); ++ netdev_err(dev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ reg[0], reg[1], reg[2], reg[3], reg[4]); ++ ++ /* Interrupt enable */ ++ reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG); ++ reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG); ++ reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG); ++ netdev_err(dev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ reg[0], reg[1], reg[2], reg[3], reg[4]); ++ ++ /* RX DMA status */ ++ reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_FIRST_DESC_REG); ++ reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_CURR_DESC_REG); ++ reg[2] = GET_RPTR(gmac->rxq_rwptr); ++ reg[3] = GET_WPTR(gmac->rxq_rwptr); ++ netdev_err(dev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ ++ reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD0_REG); ++ reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD1_REG); ++ reg[2] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD2_REG); ++ reg[3] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD3_REG); ++ netdev_err(dev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ ++ /* TX DMA status */ ++ ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG; ++ ++ reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_FIRST_DESC_REG); ++ reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_CURR_DESC_REG); ++ reg[2] = GET_RPTR(ptr_reg); ++ reg[3] = GET_WPTR(ptr_reg); ++ netdev_err(dev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ ++ reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD0_REG); ++ reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD1_REG); ++ reg[2] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD2_REG); ++ reg[3] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD3_REG); ++ netdev_err(dev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ ++ /* FREE queues status */ ++ ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG; ++ ++ reg[0] = GET_RPTR(ptr_reg); ++ reg[1] = GET_WPTR(ptr_reg); ++ ++ ptr_reg = toe->iomem + GLOBAL_HWFQ_RWPTR_REG; ++ ++ reg[2] = GET_RPTR(ptr_reg); ++ reg[3] = GET_WPTR(ptr_reg); ++ netdev_err(dev, "FQ SW ptr: %u %u, HW ptr: %u %u\n", ++ reg[0], reg[1], reg[2], reg[3]); ++} ++ ++static void gmac_update_hw_stats(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned long flags; ++ unsigned int rx_discards, rx_mcast, rx_bcast; ++ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ u64_stats_update_begin(&gmac->ir_stats_syncp); ++ ++ gmac->hw_stats[0] += rx_discards = readl(gmac->ctl_iomem + GMAC_IN_DISCARDS); ++ gmac->hw_stats[1] += readl(gmac->ctl_iomem + GMAC_IN_ERRORS); ++ gmac->hw_stats[2] += rx_mcast = readl(gmac->ctl_iomem + GMAC_IN_MCAST); ++ gmac->hw_stats[3] += rx_bcast = readl(gmac->ctl_iomem + GMAC_IN_BCAST); ++ gmac->hw_stats[4] += readl(gmac->ctl_iomem + GMAC_IN_MAC1); ++ gmac->hw_stats[5] += readl(gmac->ctl_iomem + GMAC_IN_MAC2); ++ ++ gmac->stats.rx_missed_errors += rx_discards; ++ gmac->stats.multicast += rx_mcast; ++ gmac->stats.multicast += rx_bcast; ++ ++ writel(GMAC0_MIB_INT_BIT << (dev->dev_id * 8), ++ toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG); ++ ++ u64_stats_update_end(&gmac->ir_stats_syncp); ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++} ++ ++static inline unsigned gmac_get_intr_flags(struct net_device *dev, int i) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *irqif_reg, *irqen_reg; ++ unsigned offs, val; ++ ++ offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - GLOBAL_INTERRUPT_STATUS_0_REG); ++ ++ irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG + offs; ++ irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG + offs; ++ ++ val = readl(irqif_reg) & readl(irqen_reg); ++ return val; ++} ++ ++enum hrtimer_restart gmac_coalesce_delay_expired( struct hrtimer *timer ) ++{ ++ struct gmac_private *gmac = container_of(timer, struct gmac_private, rx_coalesce_timer); ++ ++ napi_schedule(&gmac->napi); ++ return HRTIMER_NORESTART; ++} ++ ++static irqreturn_t gmac_irq(int irq, void *data) ++{ ++ struct net_device *dev = data; ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned val, orr = 0; ++ ++ orr |= val = gmac_get_intr_flags(dev, 0); ++ ++ if (unlikely(val & (GMAC0_IRQ0_2 << (dev->dev_id * 2)))) { ++ /* oh, crap. */ ++ netdev_err(dev, "hw failure/sw bug\n"); ++ gmac_dump_dma_state(dev); ++ ++ /* don't know how to recover, just reduce losses */ ++ gmac_enable_irq(dev, 0); ++ return IRQ_HANDLED; ++ } ++ ++ if (val & (GMAC0_IRQ0_TXQ0_INTS << (dev->dev_id * 6))) ++ gmac_tx_irq(dev, 0); ++ ++ orr |= val = gmac_get_intr_flags(dev, 1); ++ ++ if (val & (DEFAULT_Q0_INT_BIT << dev->dev_id)) { ++ ++ gmac_enable_rx_irq(dev, 0); ++ ++ if (!gmac->rx_coalesce_nsecs) ++ napi_schedule(&gmac->napi); ++ else { ++ ktime_t ktime; ++ ktime = ktime_set(0, gmac->rx_coalesce_nsecs); ++ hrtimer_start(&gmac->rx_coalesce_timer, ktime, HRTIMER_MODE_REL); ++ } ++ } ++ ++ orr |= val = gmac_get_intr_flags(dev, 4); ++ ++ if (unlikely(val & (GMAC0_MIB_INT_BIT << (dev->dev_id * 8)))) ++ gmac_update_hw_stats(dev); ++ ++ if (unlikely(val & (GMAC0_RX_OVERRUN_INT_BIT << (dev->dev_id * 8)))) { ++ writel(GMAC0_RXDERR_INT_BIT << (dev->dev_id * 8), ++ toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG); ++ ++ spin_lock(&toe->irq_lock); ++ u64_stats_update_begin(&gmac->ir_stats_syncp); ++ ++gmac->stats.rx_fifo_errors; ++ u64_stats_update_end(&gmac->ir_stats_syncp); ++ spin_unlock(&toe->irq_lock); ++ } ++ ++ return orr ? IRQ_HANDLED : IRQ_NONE; ++} ++ ++static void gmac_start_dma(struct gmac_private *gmac) ++{ ++ void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG; ++ GMAC_DMA_CTRL_T dma_ctrl; ++ ++ dma_ctrl.bits32 = readl(dma_ctrl_reg); ++ dma_ctrl.bits.rd_enable = 1; ++ dma_ctrl.bits.td_enable = 1; ++ dma_ctrl.bits.loopback = 0; ++ dma_ctrl.bits.drop_small_ack = 0; ++ dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN; ++ dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED; ++ dma_ctrl.bits.rd_burst_size = HBURST_INCR8; ++ dma_ctrl.bits.rd_bus = HSIZE_8; ++ dma_ctrl.bits.td_prot = HPROT_DATA_CACHE; ++ dma_ctrl.bits.td_burst_size = HBURST_INCR8; ++ dma_ctrl.bits.td_bus = HSIZE_8; ++ ++ writel(dma_ctrl.bits32, dma_ctrl_reg); ++} ++ ++static void gmac_stop_dma(struct gmac_private *gmac) ++{ ++ void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG; ++ GMAC_DMA_CTRL_T dma_ctrl; ++ ++ dma_ctrl.bits32 = readl(dma_ctrl_reg); ++ dma_ctrl.bits.rd_enable = 0; ++ dma_ctrl.bits.td_enable = 0; ++ writel(dma_ctrl.bits32, dma_ctrl_reg); ++} ++ ++static int gmac_open(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ int err; ++ ++ if (!dev->phydev) { ++ err = gmac_setup_phy(dev); ++ if (err) { ++ netif_err(gmac, ifup, dev, ++ "PHY init failed: %d\n", err); ++ return err; ++ } ++ } ++ ++ err = request_irq(dev->irq, gmac_irq, ++ IRQF_SHARED, dev->name, dev); ++ if (unlikely(err)) ++ return err; ++ ++ netif_carrier_off(dev); ++ phy_start(dev->phydev); ++ ++ err = toe_resize_freeq(gmac->toe, dev->dev_id); ++ if (unlikely(err)) ++ goto err_stop_phy; ++ ++ err = gmac_setup_rxq(dev); ++ if (unlikely(err)) ++ goto err_stop_phy; ++ ++ err = gmac_setup_txqs(dev); ++ if (unlikely(err)) { ++ gmac_cleanup_rxq(dev); ++ goto err_stop_phy; ++ } ++ ++ napi_enable(&gmac->napi); ++ ++ gmac_start_dma(gmac); ++ gmac_enable_irq(dev, 1); ++ gmac_enable_tx_rx(dev); ++ netif_tx_start_all_queues(dev); ++ ++ hrtimer_init(&gmac->rx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); ++ gmac->rx_coalesce_timer.function = &gmac_coalesce_delay_expired; ++ return 0; ++ ++err_stop_phy: ++ phy_stop(dev->phydev); ++ free_irq(dev->irq, dev); ++ return err; ++} ++ ++static int gmac_stop(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ hrtimer_cancel(&gmac->rx_coalesce_timer); ++ netif_tx_stop_all_queues(dev); ++ gmac_disable_tx_rx(dev); ++ gmac_stop_dma(gmac); ++ napi_disable(&gmac->napi); ++ ++ gmac_enable_irq(dev, 0); ++ gmac_cleanup_rxq(dev); ++ gmac_cleanup_txqs(dev); ++ ++ phy_stop(dev->phydev); ++ free_irq(dev->irq, dev); ++ ++ gmac_update_hw_stats(dev); ++ return 0; ++} ++ ++static void gmac_set_rx_mode(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct netdev_hw_addr *ha; ++ __u32 mc_filter[2]; ++ unsigned bit_nr; ++ GMAC_RX_FLTR_T filter = { .bits = { ++ .broadcast = 1, ++ .multicast = 1, ++ .unicast = 1, ++ } }; ++ ++ mc_filter[1] = mc_filter[0] = 0; ++ ++ if (dev->flags & IFF_PROMISC) { ++ filter.bits.error = 1; ++ filter.bits.promiscuous = 1; ++ } else if (!(dev->flags & IFF_ALLMULTI)) { ++ mc_filter[1] = mc_filter[0] = 0; ++ netdev_for_each_mc_addr(ha, dev) { ++ bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f; ++ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f); ++ } ++ } ++ ++ writel(mc_filter[0], gmac->ctl_iomem + GMAC_MCAST_FIL0); ++ writel(mc_filter[1], gmac->ctl_iomem + GMAC_MCAST_FIL1); ++ writel(filter.bits32, gmac->ctl_iomem + GMAC_RX_FLTR); ++} ++ ++static void __gmac_set_mac_address(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ __le32 addr[3]; ++ ++ memset(addr, 0, sizeof(addr)); ++ memcpy(addr, dev->dev_addr, ETH_ALEN); ++ ++ writel(le32_to_cpu(addr[0]), gmac->ctl_iomem + GMAC_STA_ADD0); ++ writel(le32_to_cpu(addr[1]), gmac->ctl_iomem + GMAC_STA_ADD1); ++ writel(le32_to_cpu(addr[2]), gmac->ctl_iomem + GMAC_STA_ADD2); ++} ++ ++static int gmac_set_mac_address(struct net_device *dev, void *addr) ++{ ++ struct sockaddr *sa = addr; ++ ++ memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); ++ __gmac_set_mac_address(dev); ++ ++ return 0; ++} ++ ++static void gmac_clear_hw_stats(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ readl(gmac->ctl_iomem + GMAC_IN_DISCARDS); ++ readl(gmac->ctl_iomem + GMAC_IN_ERRORS); ++ readl(gmac->ctl_iomem + GMAC_IN_MCAST); ++ readl(gmac->ctl_iomem + GMAC_IN_BCAST); ++ readl(gmac->ctl_iomem + GMAC_IN_MAC1); ++ readl(gmac->ctl_iomem + GMAC_IN_MAC2); ++} ++ ++static struct rtnl_link_stats64 *gmac_get_stats64(struct net_device *dev, ++ struct rtnl_link_stats64 *storage) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ unsigned int start; ++ ++ gmac_update_hw_stats(dev); ++ ++ /* racing with RX NAPI */ ++ do { ++ start = u64_stats_fetch_begin(&gmac->rx_stats_syncp); ++ ++ storage->rx_packets = gmac->stats.rx_packets; ++ storage->rx_bytes = gmac->stats.rx_bytes; ++ storage->rx_errors = gmac->stats.rx_errors; ++ storage->rx_dropped = gmac->stats.rx_dropped; ++ ++ storage->rx_length_errors = gmac->stats.rx_length_errors; ++ storage->rx_over_errors = gmac->stats.rx_over_errors; ++ storage->rx_crc_errors = gmac->stats.rx_crc_errors; ++ storage->rx_frame_errors = gmac->stats.rx_frame_errors; ++ ++ } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start)); ++ ++ /* racing with MIB and TX completion interrupts */ ++ do { ++ start = u64_stats_fetch_begin(&gmac->ir_stats_syncp); ++ ++ storage->tx_errors = gmac->stats.tx_errors; ++ storage->tx_packets = gmac->stats.tx_packets; ++ storage->tx_bytes = gmac->stats.tx_bytes; ++ ++ storage->multicast = gmac->stats.multicast; ++ storage->rx_missed_errors = gmac->stats.rx_missed_errors; ++ storage->rx_fifo_errors = gmac->stats.rx_fifo_errors; ++ ++ } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start)); ++ ++ /* racing with hard_start_xmit */ ++ do { ++ start = u64_stats_fetch_begin(&gmac->tx_stats_syncp); ++ ++ storage->tx_dropped = gmac->stats.tx_dropped; ++ ++ } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start)); ++ ++ storage->rx_dropped += storage->rx_missed_errors; ++ ++ return storage; ++} ++ ++static int gmac_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ int max_len = gmac_pick_rx_max_len(new_mtu); ++ ++ if (max_len < 0) ++ return -EINVAL; ++ ++ gmac_disable_tx_rx(dev); ++ ++ dev->mtu = new_mtu; ++ gmac_update_config0_reg(dev, ++ max_len << CONFIG0_MAXLEN_SHIFT, ++ CONFIG0_MAXLEN_MASK); ++ ++ netdev_update_features(dev); ++ ++ gmac_enable_tx_rx(dev); ++ ++ return 0; ++} ++ ++static netdev_features_t gmac_fix_features(struct net_device *dev, netdev_features_t features) ++{ ++ if (dev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK) ++ features &= ~GMAC_OFFLOAD_FEATURES; ++ ++ return features; ++} ++ ++static int gmac_set_features(struct net_device *dev, netdev_features_t features) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ int enable = features & NETIF_F_RXCSUM; ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM; ++ writel(reg, gmac->ctl_iomem + GMAC_CONFIG0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++ return 0; ++} ++ ++static int gmac_get_sset_count(struct net_device *dev, int sset) ++{ ++ return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0; ++} ++ ++static void gmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) ++{ ++ if (stringset != ETH_SS_STATS) ++ return; ++ ++ memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings)); ++} ++ ++static void gmac_get_ethtool_stats(struct net_device *dev, ++ struct ethtool_stats *estats, u64 *values) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ unsigned int start; ++ u64 *p; ++ int i; ++ ++ gmac_update_hw_stats(dev); ++ ++ /* racing with MIB interrupt */ ++ do { ++ p = values; ++ start = u64_stats_fetch_begin(&gmac->ir_stats_syncp); ++ ++ for (i = 0; i < RX_STATS_NUM; ++i) ++ *p++ = gmac->hw_stats[i]; ++ ++ } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start)); ++ values = p; ++ ++ /* racing with RX NAPI */ ++ do { ++ p = values; ++ start = u64_stats_fetch_begin(&gmac->rx_stats_syncp); ++ ++ for (i = 0; i < RX_STATUS_NUM; ++i) ++ *p++ = gmac->rx_stats[i]; ++ for (i = 0; i < RX_CHKSUM_NUM; ++i) ++ *p++ = gmac->rx_csum_stats[i]; ++ *p++ = gmac->rx_napi_exits; ++ ++ } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start)); ++ values = p; ++ ++ /* racing with TX start_xmit */ ++ do { ++ p = values; ++ start = u64_stats_fetch_begin(&gmac->tx_stats_syncp); ++ ++ for (i = 0; i < TX_MAX_FRAGS; ++i) { ++ *values++ = gmac->tx_frag_stats[i]; ++ gmac->tx_frag_stats[i] = 0; ++ } ++ *values++ = gmac->tx_frags_linearized; ++ *values++ = gmac->tx_hw_csummed; ++ ++ } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start)); ++} ++ ++static int gmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ if (!dev->phydev) ++ return -ENXIO; ++ return phy_ethtool_gset(dev->phydev, cmd); ++} ++ ++static int gmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ if (!dev->phydev) ++ return -ENXIO; ++ return phy_ethtool_sset(dev->phydev, cmd); ++} ++ ++static int gmac_nway_reset(struct net_device *dev) ++{ ++ if (!dev->phydev) ++ return -ENXIO; ++ return phy_start_aneg(dev->phydev); ++} ++ ++static void gmac_get_pauseparam(struct net_device *dev, ++ struct ethtool_pauseparam *pparam) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ GMAC_CONFIG0_T config0; ++ ++ config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ ++ pparam->rx_pause = config0.bits.rx_fc_en; ++ pparam->tx_pause = config0.bits.tx_fc_en; ++ pparam->autoneg = true; ++} ++ ++static void gmac_get_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *rp) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ GMAC_CONFIG0_T config0; ++ ++ config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ ++ rp->rx_max_pending = 1 << 15; ++ rp->rx_mini_max_pending = 0; ++ rp->rx_jumbo_max_pending = 0; ++ rp->tx_max_pending = 1 << 15; ++ ++ rp->rx_pending = 1 << gmac->rxq_order; ++ rp->rx_mini_pending = 0; ++ rp->rx_jumbo_pending = 0; ++ rp->tx_pending = 1 << gmac->txq_order; ++} ++ ++static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id); ++ ++static int gmac_set_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *rp) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ int err = 0; ++ ++ if (netif_running(dev)) ++ return -EBUSY; ++ ++ if (rp->rx_pending) { ++ gmac->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1); ++ err = toe_resize_freeq(toe, dev->dev_id); ++ } ++ ++ if (rp->tx_pending) ++ { ++ gmac->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1); ++ gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2); ++ } ++ ++ return err; ++} ++ ++static int gmac_get_coalesce(struct net_device *dev, ++ struct ethtool_coalesce *ecmd) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ ecmd->rx_max_coalesced_frames = 1; ++ ecmd->tx_max_coalesced_frames = gmac->irq_every_tx_packets; ++ ecmd->rx_coalesce_usecs = gmac->rx_coalesce_nsecs/1000; ++ ++ return 0; ++} ++ ++static int gmac_set_coalesce(struct net_device *dev, ++ struct ethtool_coalesce *ecmd) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ if (ecmd->tx_max_coalesced_frames < 1) ++ return -EINVAL; ++ if (ecmd->tx_max_coalesced_frames >= 1 << gmac->txq_order) ++ return -EINVAL; ++ ++ gmac->irq_every_tx_packets = ecmd->tx_max_coalesced_frames; ++ gmac->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000; ++ ++ return 0; ++} ++ ++static u32 gmac_get_msglevel(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ return gmac->msg_enable; ++} ++ ++static void gmac_set_msglevel(struct net_device *dev, u32 level) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ gmac->msg_enable = level; ++} ++ ++static void gmac_get_drvinfo(struct net_device *dev, ++ struct ethtool_drvinfo *info) ++{ ++ strcpy(info->driver, DRV_NAME); ++ strcpy(info->version, DRV_VERSION); ++ strcpy(info->bus_info, dev->dev_id ? "1" : "0"); ++} ++ ++static const struct net_device_ops gmac_351x_ops = { ++ .ndo_init = gmac_init, ++ .ndo_uninit = gmac_uninit, ++ .ndo_open = gmac_open, ++ .ndo_stop = gmac_stop, ++ .ndo_start_xmit = gmac_start_xmit, ++ .ndo_tx_timeout = gmac_tx_timeout, ++ .ndo_set_rx_mode = gmac_set_rx_mode, ++ .ndo_set_mac_address = gmac_set_mac_address, ++ .ndo_get_stats64 = gmac_get_stats64, ++ .ndo_change_mtu = gmac_change_mtu, ++ .ndo_fix_features = gmac_fix_features, ++ .ndo_set_features = gmac_set_features, ++}; ++ ++static const struct ethtool_ops gmac_351x_ethtool_ops = { ++ .get_sset_count = gmac_get_sset_count, ++ .get_strings = gmac_get_strings, ++ .get_ethtool_stats = gmac_get_ethtool_stats, ++ .get_settings = gmac_get_settings, ++ .set_settings = gmac_set_settings, ++ .get_link = ethtool_op_get_link, ++ .nway_reset = gmac_nway_reset, ++ .get_pauseparam = gmac_get_pauseparam, ++ .get_ringparam = gmac_get_ringparam, ++ .set_ringparam = gmac_set_ringparam, ++ .get_coalesce = gmac_get_coalesce, ++ .set_coalesce = gmac_set_coalesce, ++ .get_msglevel = gmac_get_msglevel, ++ .set_msglevel = gmac_set_msglevel, ++ .get_drvinfo = gmac_get_drvinfo, ++}; ++ ++static int gmac_init_netdev(struct toe_private *toe, int num, ++ struct platform_device *pdev) ++{ ++ struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data; ++ struct gmac_private *gmac; ++ struct net_device *dev; ++ int irq, err; ++ ++ if (!pdata->bus_id[num]) ++ return 0; ++ ++ irq = platform_get_irq(pdev, num); ++ if (irq < 0) { ++ dev_err(toe->dev, "No IRQ for ethernet device #%d\n", num); ++ return irq; ++ } ++ ++ dev = alloc_etherdev_mq(sizeof(*gmac), TX_QUEUE_NUM); ++ if (!dev) { ++ dev_err(toe->dev, "Can't allocate ethernet device #%d\n", num); ++ return -ENOMEM; ++ } ++ ++ gmac = netdev_priv(dev); ++ gmac->num = num; ++ gmac->toe = toe; ++ SET_NETDEV_DEV(dev, toe->dev); ++ ++ toe->netdev[num] = dev; ++ dev->dev_id = num; ++ ++ gmac->ctl_iomem = toe->iomem + TOE_GMAC_BASE(num); ++ gmac->dma_iomem = toe->iomem + TOE_GMAC_DMA_BASE(num); ++ dev->irq = irq; ++ ++ dev->netdev_ops = &gmac_351x_ops; ++ dev->ethtool_ops = &gmac_351x_ethtool_ops; ++ ++ spin_lock_init(&gmac->config_lock); ++ gmac_clear_hw_stats(dev); ++ ++ dev->hw_features = GMAC_OFFLOAD_FEATURES; ++ dev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO; ++ ++ gmac->freeq_refill = 0; ++ netif_napi_add(dev, &gmac->napi, gmac_napi_poll, DEFAULT_NAPI_WEIGHT); ++ ++ if (is_valid_ether_addr((void *)toe->mac_addr[num])) ++ memcpy(dev->dev_addr, toe->mac_addr[num], ETH_ALEN); ++ else ++ random_ether_addr(dev->dev_addr); ++ __gmac_set_mac_address(dev); ++ ++ err = gmac_setup_phy(dev); ++ if (err) ++ netif_warn(gmac, probe, dev, ++ "PHY init failed: %d, deferring to ifup time\n", err); ++ ++ err = register_netdev(dev); ++ if (!err) ++ { ++ pr_info(DRV_NAME " %s: irq %d, dma base 0x%p, io base 0x%p\n", ++ dev->name, irq, gmac->dma_iomem, gmac->ctl_iomem); ++ return 0; ++ } ++ ++ toe->netdev[num] = NULL; ++ free_netdev(dev); ++ return err; ++} ++ ++static irqreturn_t toe_irq_thread(int irq, void *data) ++{ ++ struct toe_private *toe = data; ++ void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG; ++ void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG; ++ unsigned long irqmask = SWFQ_EMPTY_INT_BIT; ++ unsigned long flags; ++ ++ toe_fill_freeq(toe, 0); ++ ++ /* Ack and enable interrupt */ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ writel(irqmask, irqif_reg); ++ irqmask |= readl(irqen_reg); ++ writel(irqmask, irqen_reg); ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t toe_irq(int irq, void *data) ++{ ++ struct toe_private *toe = data; ++ void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG; ++ void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG; ++ unsigned long val, en; ++ irqreturn_t ret = IRQ_NONE; ++ ++ spin_lock(&toe->irq_lock); ++ ++ val = readl(irqif_reg); ++ en = readl(irqen_reg); ++ ++ if (val & en & SWFQ_EMPTY_INT_BIT) { ++ en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT ++ | GMAC1_RX_OVERRUN_INT_BIT); ++ writel(en, irqen_reg); ++ ret = IRQ_WAKE_THREAD; ++ } ++ ++ spin_unlock(&toe->irq_lock); ++ return ret; ++} ++ ++static int toe_init(struct toe_private *toe, ++ struct platform_device *pdev) ++{ ++ int err; ++ ++ writel(0, toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG); ++ writel(0, toe->iomem + GLOBAL_HW_FREEQ_BASE_SIZE_REG); ++ writel(0, toe->iomem + GLOBAL_SWFQ_RWPTR_REG); ++ writel(0, toe->iomem + GLOBAL_HWFQ_RWPTR_REG); ++ ++ toe->freeq_frag_order = DEFAULT_RX_BUF_ORDER; ++ toe->freeq_order = ~0; ++ ++ err = request_threaded_irq(toe->irq, toe_irq, ++ toe_irq_thread, IRQF_SHARED, DRV_NAME " toe", toe); ++ if (err) ++ goto err_freeq; ++ ++ return 0; ++ ++err_freeq: ++ toe_cleanup_freeq(toe); ++ return err; ++} ++ ++static void toe_deinit(struct toe_private *toe) ++{ ++ free_irq(toe->irq, toe); ++ toe_cleanup_freeq(toe); ++} ++ ++static int toe_reset(struct toe_private *toe) ++{ ++ unsigned int reg = 0, retry = 5; ++ ++ reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_RESET)); ++ reg |= RESET_GMAC1 | RESET_GMAC0; ++ writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_RESET)); ++ ++ do { ++ udelay(2); ++ reg = readl((void __iomem*)(toe->iomem + ++ GLOBAL_TOE_VERSION_REG)); ++ barrier(); ++ } while (!reg && --retry); ++ ++ return reg ? 0 : -EIO; ++} ++ ++/* ++ * Interrupt config: ++ * ++ * GMAC0 intr bits ------> int0 ----> eth0 ++ * GMAC1 intr bits ------> int1 ----> eth1 ++ * TOE intr -------------> int1 ----> eth1 ++ * Classification Intr --> int0 ----> eth0 ++ * Default Q0 -----------> int0 ----> eth0 ++ * Default Q1 -----------> int1 ----> eth1 ++ * FreeQ intr -----------> int1 ----> eth1 ++ */ ++static void toe_init_irq(struct toe_private *toe) ++{ ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG); ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG); ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG); ++ ++ writel(0xCCFC0FC0, toe->iomem + GLOBAL_INTERRUPT_SELECT_0_REG); ++ writel(0x00F00002, toe->iomem + GLOBAL_INTERRUPT_SELECT_1_REG); ++ writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_2_REG); ++ writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_3_REG); ++ writel(0xFF000003, toe->iomem + GLOBAL_INTERRUPT_SELECT_4_REG); ++ ++ /* edge-triggered interrupts packed to level-triggered one... */ ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG); ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG); ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG); ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG); ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG); ++} ++ ++static void toe_save_mac_addr(struct toe_private *toe, ++ struct platform_device *pdev) ++{ ++ struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data; ++ void __iomem *ctl; ++ int i; ++ ++ for (i = 0; i < 2; i++) { ++ if (pdata->bus_id[i]) { ++ ctl = toe->iomem + TOE_GMAC_BASE(i); ++ toe->mac_addr[i][0] = cpu_to_le32(readl(ctl + GMAC_STA_ADD0)); ++ toe->mac_addr[i][1] = cpu_to_le32(readl(ctl + GMAC_STA_ADD1)); ++ toe->mac_addr[i][2] = cpu_to_le32(readl(ctl + GMAC_STA_ADD2)); ++ } ++ } ++} ++ ++static int gemini_gmac_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct toe_private *toe; ++ int irq, retval; ++ ++ if (!pdev->dev.platform_data) ++ return -EINVAL; ++ ++ irq = platform_get_irq(pdev, 1); ++ if (irq < 0) ++ return irq; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "can't get device resources\n"); ++ return -ENODEV; ++ } ++ ++ toe = kzalloc(sizeof(*toe), GFP_KERNEL); ++ if (!toe) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, toe); ++ toe->dev = &pdev->dev; ++ toe->irq = irq; ++ ++ toe->iomem = ioremap(res->start, resource_size(res)); ++ if (!toe->iomem) { ++ dev_err(toe->dev, "ioremap failed\n"); ++ retval = -EIO; ++ goto err_data; ++ } ++ ++ toe_save_mac_addr(toe, pdev); ++ ++ retval = toe_reset(toe); ++ if (retval < 0) ++ goto err_unmap; ++ ++ pr_info(DRV_NAME " toe: irq %d, io base 0x%08x, version %d\n", ++ irq, res->start, retval); ++ ++ spin_lock_init(&toe->irq_lock); ++ spin_lock_init(&toe->freeq_lock); ++ ++ toe_init_irq(toe); ++ ++ retval = toe_init(toe, pdev); ++ if (retval) ++ goto err_unmap; ++ ++ retval = gmac_init_netdev(toe, 0, pdev); ++ if (retval) ++ goto err_uninit; ++ ++ retval = gmac_init_netdev(toe, 1, pdev); ++ if (retval) ++ goto err_uninit; ++ ++ return 0; ++ ++err_uninit: ++ if (toe->netdev[0]) ++ unregister_netdev(toe->netdev[0]); ++ toe_deinit(toe); ++err_unmap: ++ iounmap(toe->iomem); ++err_data: ++ kfree(toe); ++ return retval; ++} ++ ++static int gemini_gmac_remove(struct platform_device *pdev) ++{ ++ struct toe_private *toe = platform_get_drvdata(pdev); ++ int i; ++ ++ for (i = 0; i < 2; i++) ++ if (toe->netdev[i]) ++ unregister_netdev(toe->netdev[i]); ++ ++ toe_init_irq(toe); ++ toe_deinit(toe); ++ ++ iounmap(toe->iomem); ++ kfree(toe); ++ ++ return 0; ++} ++ ++static struct platform_driver gemini_gmac_driver = { ++ .probe = gemini_gmac_probe, ++ .remove = gemini_gmac_remove, ++ .driver.name = DRV_NAME, ++ .driver.owner = THIS_MODULE, ++}; ++ ++static int __init gemini_gmac_init(void) ++{ ++#ifdef CONFIG_MDIO_GPIO_MODULE ++ request_module("mdio-gpio"); ++#endif ++ return platform_driver_register(&gemini_gmac_driver); ++} ++ ++static void __exit gemini_gmac_exit(void) ++{ ++ platform_driver_unregister(&gemini_gmac_driver); ++} ++ ++module_init(gemini_gmac_init); ++module_exit(gemini_gmac_exit); +--- /dev/null ++++ b/drivers/net/ethernet/gemini/sl351x_hw.h +@@ -0,0 +1,1436 @@ ++/* ++ * Register definitions for Gemini LEPUS GMAC Ethernet device driver. ++ * ++ * Copyright (C) 2006, Storlink, Corp. ++ * Copyright (C) 2008-2009, Paulius Zaleckas ++ * Copyright (C) 2010, MichaÅ‚ MirosÅ‚aw ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#ifndef _GMAC_HW_H ++#define _GMAC_HW_H ++ ++#include ++ ++/* ++ * Base Registers ++ */ ++#define TOE_NONTOE_QUE_HDR_BASE 0x2000 ++#define TOE_TOE_QUE_HDR_BASE 0x3000 ++#define TOE_V_BIT_BASE 0x4000 ++#define TOE_A_BIT_BASE 0x6000 ++#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x)) ++#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x)) ++ ++/* ++ * Queue ID ++ */ ++#define TOE_SW_FREE_QID 0x00 ++#define TOE_HW_FREE_QID 0x01 ++#define TOE_GMAC0_SW_TXQ0_QID 0x02 ++#define TOE_GMAC0_SW_TXQ1_QID 0x03 ++#define TOE_GMAC0_SW_TXQ2_QID 0x04 ++#define TOE_GMAC0_SW_TXQ3_QID 0x05 ++#define TOE_GMAC0_SW_TXQ4_QID 0x06 ++#define TOE_GMAC0_SW_TXQ5_QID 0x07 ++#define TOE_GMAC0_HW_TXQ0_QID 0x08 ++#define TOE_GMAC0_HW_TXQ1_QID 0x09 ++#define TOE_GMAC0_HW_TXQ2_QID 0x0A ++#define TOE_GMAC0_HW_TXQ3_QID 0x0B ++#define TOE_GMAC1_SW_TXQ0_QID 0x12 ++#define TOE_GMAC1_SW_TXQ1_QID 0x13 ++#define TOE_GMAC1_SW_TXQ2_QID 0x14 ++#define TOE_GMAC1_SW_TXQ3_QID 0x15 ++#define TOE_GMAC1_SW_TXQ4_QID 0x16 ++#define TOE_GMAC1_SW_TXQ5_QID 0x17 ++#define TOE_GMAC1_HW_TXQ0_QID 0x18 ++#define TOE_GMAC1_HW_TXQ1_QID 0x19 ++#define TOE_GMAC1_HW_TXQ2_QID 0x1A ++#define TOE_GMAC1_HW_TXQ3_QID 0x1B ++#define TOE_GMAC0_DEFAULT_QID 0x20 ++#define TOE_GMAC1_DEFAULT_QID 0x21 ++#define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */ ++#define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */ ++ ++/* ++ * old info: ++ * TOE DMA Queue Size should be 2^n, n = 6...12 ++ * TOE DMA Queues are the following queue types: ++ * SW Free Queue, HW Free Queue, ++ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5 ++ * The base address and descriptor number are configured at ++ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004) ++ */ ++ ++#define GET_WPTR(addr) __raw_readw((addr) + 2) ++#define GET_RPTR(addr) __raw_readw((addr)) ++#define SET_WPTR(addr, data) __raw_writew((data), (addr) + 2) ++#define SET_RPTR(addr, data) __raw_writew((data), (addr)) ++#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask)) ++#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask)) ++#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask)) ++#define __RWPTR_MASK(order) ((1 << (order)) - 1) ++#define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order))) ++#define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order))) ++#define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \ ++ __RWPTR_MASK((order))) ++ ++/* ++ * Global registers ++ * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000) ++ * Base 0x60000000 ++ */ ++#define GLOBAL_TOE_VERSION_REG 0x0000 ++#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004 ++#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008 ++#define GLOBAL_DMA_SKB_SIZE_REG 0x0010 ++#define GLOBAL_SWFQ_RWPTR_REG 0x0014 ++#define GLOBAL_HWFQ_RWPTR_REG 0x0018 ++#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020 ++#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024 ++#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028 ++#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030 ++#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034 ++#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038 ++#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040 ++#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044 ++#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048 ++#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050 ++#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054 ++#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058 ++#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060 ++#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064 ++#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068 ++#define GLOBAL_HASH_TABLE_BASE_REG 0x006C ++#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070 ++ ++/* ++ * GMAC 0/1 DMA/TOE register ++ * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000) ++ * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000) ++ * Base 0x60008000 or 0x6000C000 ++ */ ++#define GMAC_DMA_CTRL_REG 0x0000 ++#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004 ++#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008 ++#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C ++#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010 ++#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014 ++#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018 ++#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C ++#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020 ++#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i)) ++#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024 ++#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028 ++#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C ++#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030 ++#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i)) ++#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038 ++#define GMAC_DMA_TX_CURR_DESC_REG 0x003C ++#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040 ++#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044 ++#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048 ++#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C ++#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050 ++#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054 ++#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058 ++#define GMAC_DMA_RX_CURR_DESC_REG 0x005C ++#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060 ++#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064 ++#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068 ++#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C ++#define GMAC_HASH_ENGINE_REG0 0x0070 ++#define GMAC_HASH_ENGINE_REG1 0x0074 ++/* matching rule 0 Control register 0 */ ++#define GMAC_MR0CR0 0x0078 ++#define GMAC_MR0CR1 0x007C ++#define GMAC_MR0CR2 0x0080 ++#define GMAC_MR1CR0 0x0084 ++#define GMAC_MR1CR1 0x0088 ++#define GMAC_MR1CR2 0x008C ++#define GMAC_MR2CR0 0x0090 ++#define GMAC_MR2CR1 0x0094 ++#define GMAC_MR2CR2 0x0098 ++#define GMAC_MR3CR0 0x009C ++#define GMAC_MR3CR1 0x00A0 ++#define GMAC_MR3CR2 0x00A4 ++/* Support Protocol Regsister 0 */ ++#define GMAC_SPR0 0x00A8 ++#define GMAC_SPR1 0x00AC ++#define GMAC_SPR2 0x00B0 ++#define GMAC_SPR3 0x00B4 ++#define GMAC_SPR4 0x00B8 ++#define GMAC_SPR5 0x00BC ++#define GMAC_SPR6 0x00C0 ++#define GMAC_SPR7 0x00C4 ++/* GMAC Hash/Rx/Tx AHB Weighting register */ ++#define GMAC_AHB_WEIGHT_REG 0x00C8 ++ ++/* ++ * TOE GMAC 0/1 register ++ * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000) ++ * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000) ++ * Base 0x6000A000 or 0x6000E000 ++ */ ++enum GMAC_REGISTER { ++ GMAC_STA_ADD0 = 0x0000, ++ GMAC_STA_ADD1 = 0x0004, ++ GMAC_STA_ADD2 = 0x0008, ++ GMAC_RX_FLTR = 0x000c, ++ GMAC_MCAST_FIL0 = 0x0010, ++ GMAC_MCAST_FIL1 = 0x0014, ++ GMAC_CONFIG0 = 0x0018, ++ GMAC_CONFIG1 = 0x001c, ++ GMAC_CONFIG2 = 0x0020, ++ GMAC_CONFIG3 = 0x0024, ++ GMAC_RESERVED = 0x0028, ++ GMAC_STATUS = 0x002c, ++ GMAC_IN_DISCARDS= 0x0030, ++ GMAC_IN_ERRORS = 0x0034, ++ GMAC_IN_MCAST = 0x0038, ++ GMAC_IN_BCAST = 0x003c, ++ GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */ ++ GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */ ++}; ++ ++#define RX_STATS_NUM 6 ++ ++/* ++ * DMA Queues description Ring Base Address/Size Register (offset 0x0004) ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int base_size; ++} DMA_Q_BASE_SIZE_T; ++#define DMA_Q_BASE_MASK (~0x0f) ++ ++/* ++ * DMA SKB Buffer register (offset 0x0008) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0008 { ++ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */ ++ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */ ++ } bits; ++} DMA_SKB_SIZE_T; ++ ++/* ++ * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_000c { ++ unsigned int rptr : 16; /* Read Ptr, RO */ ++ unsigned int wptr : 16; /* Write Ptr, RW */ ++ } bits; ++} DMA_RWPTR_T; ++ ++/* ++ * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010) ++ * see DMA_RWPTR_T structure ++ */ ++ ++/* ++ * Interrupt Status Register 0 (offset 0x0020) ++ * Interrupt Mask Register 0 (offset 0x0024) ++ * Interrupt Select Register 0 (offset 0x0028) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0020 { ++ /* GMAC0 SW Tx Queue 0 EOF Interrupt */ ++ unsigned int swtq00_eof : 1; ++ unsigned int swtq01_eof : 1; ++ unsigned int swtq02_eof : 1; ++ unsigned int swtq03_eof : 1; ++ unsigned int swtq04_eof : 1; ++ unsigned int swtq05_eof : 1; ++ /* GMAC1 SW Tx Queue 0 EOF Interrupt */ ++ unsigned int swtq10_eof : 1; ++ unsigned int swtq11_eof : 1; ++ unsigned int swtq12_eof : 1; ++ unsigned int swtq13_eof : 1; ++ unsigned int swtq14_eof : 1; ++ unsigned int swtq15_eof : 1; ++ /* GMAC0 SW Tx Queue 0 Finish Interrupt */ ++ unsigned int swtq00_fin : 1; ++ unsigned int swtq01_fin : 1; ++ unsigned int swtq02_fin : 1; ++ unsigned int swtq03_fin : 1; ++ unsigned int swtq04_fin : 1; ++ unsigned int swtq05_fin : 1; ++ /* GMAC1 SW Tx Queue 0 Finish Interrupt */ ++ unsigned int swtq10_fin : 1; ++ unsigned int swtq11_fin : 1; ++ unsigned int swtq12_fin : 1; ++ unsigned int swtq13_fin : 1; ++ unsigned int swtq14_fin : 1; ++ unsigned int swtq15_fin : 1; ++ /* GMAC0 Rx Descriptor Protocol Error */ ++ unsigned int rxPerr0 : 1; ++ /* GMAC0 AHB Bus Error while Rx */ ++ unsigned int rxDerr0 : 1; ++ /* GMAC1 Rx Descriptor Protocol Error */ ++ unsigned int rxPerr1 : 1; ++ /* GMAC1 AHB Bus Error while Rx */ ++ unsigned int rxDerr1 : 1; ++ /* GMAC0 Tx Descriptor Protocol Error */ ++ unsigned int txPerr0 : 1; ++ /* GMAC0 AHB Bus Error while Tx */ ++ unsigned int txDerr0 : 1; ++ /* GMAC1 Tx Descriptor Protocol Error */ ++ unsigned int txPerr1 : 1; ++ /* GMAC1 AHB Bus Error while Tx */ ++ unsigned int txDerr1 : 1; ++ } bits; ++} INTR_REG0_T; ++ ++#define GMAC1_TXDERR_INT_BIT BIT(31) ++#define GMAC1_TXPERR_INT_BIT BIT(30) ++#define GMAC0_TXDERR_INT_BIT BIT(29) ++#define GMAC0_TXPERR_INT_BIT BIT(28) ++#define GMAC1_RXDERR_INT_BIT BIT(27) ++#define GMAC1_RXPERR_INT_BIT BIT(26) ++#define GMAC0_RXDERR_INT_BIT BIT(25) ++#define GMAC0_RXPERR_INT_BIT BIT(24) ++#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23) ++#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22) ++#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21) ++#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20) ++#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19) ++#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18) ++#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17) ++#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16) ++#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15) ++#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14) ++#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13) ++#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12) ++#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11) ++#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10) ++#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9) ++#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8) ++#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7) ++#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6) ++#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5) ++#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4) ++#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3) ++#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2) ++#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1) ++#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0) ++ ++/* ++ * Interrupt Status Register 1 (offset 0x0030) ++ * Interrupt Mask Register 1 (offset 0x0034) ++ * Interrupt Select Register 1 (offset 0x0038) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0030 { ++ unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */ ++ unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */ ++ unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */ ++ unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */ ++ unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */ ++ unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */ ++ unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */ ++ unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */ ++ unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */ ++ unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */ ++ unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */ ++ unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */ ++ unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */ ++ unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */ ++ unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */ ++ unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */ ++ unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */ ++ unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */ ++ unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */ ++ } bits; ++} INTR_REG1_T; ++ ++#define TOE_IQ3_FULL_INT_BIT BIT(31) ++#define TOE_IQ2_FULL_INT_BIT BIT(30) ++#define TOE_IQ1_FULL_INT_BIT BIT(29) ++#define TOE_IQ0_FULL_INT_BIT BIT(28) ++#define TOE_IQ3_INT_BIT BIT(27) ++#define TOE_IQ2_INT_BIT BIT(26) ++#define TOE_IQ1_INT_BIT BIT(25) ++#define TOE_IQ0_INT_BIT BIT(24) ++#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23) ++#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22) ++#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21) ++#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20) ++#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19) ++#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18) ++#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17) ++#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16) ++#define CLASS_RX_INT_BIT(x) BIT((x + 2)) ++#define DEFAULT_Q1_INT_BIT BIT(1) ++#define DEFAULT_Q0_INT_BIT BIT(0) ++ ++#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \ ++ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT) ++#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \ ++ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT) ++#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS) ++#define TOE_CLASS_RX_INT_BITS 0xfffc ++ ++/* ++ * Interrupt Status Register 2 (offset 0x0040) ++ * Interrupt Mask Register 2 (offset 0x0044) ++ * Interrupt Select Register 2 (offset 0x0048) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0040 { ++ unsigned int toe_q0_full : 1; /* bit 0 TOE Queue 0 Full Interrupt */ ++ unsigned int toe_q1_full : 1; /* bit 1 TOE Queue 1 Full Interrupt */ ++ unsigned int toe_q2_full : 1; /* bit 2 TOE Queue 2 Full Interrupt */ ++ unsigned int toe_q3_full : 1; /* bit 3 TOE Queue 3 Full Interrupt */ ++ unsigned int toe_q4_full : 1; /* bit 4 TOE Queue 4 Full Interrupt */ ++ unsigned int toe_q5_full : 1; /* bit 5 TOE Queue 5 Full Interrupt */ ++ unsigned int toe_q6_full : 1; /* bit 6 TOE Queue 6 Full Interrupt */ ++ unsigned int toe_q7_full : 1; /* bit 7 TOE Queue 7 Full Interrupt */ ++ unsigned int toe_q8_full : 1; /* bit 8 TOE Queue 8 Full Interrupt */ ++ unsigned int toe_q9_full : 1; /* bit 9 TOE Queue 9 Full Interrupt */ ++ unsigned int toe_q10_full : 1; /* bit 10 TOE Queue 10 Full Interrupt */ ++ unsigned int toe_q11_full : 1; /* bit 11 TOE Queue 11 Full Interrupt */ ++ unsigned int toe_q12_full : 1; /* bit 12 TOE Queue 12 Full Interrupt */ ++ unsigned int toe_q13_full : 1; /* bit 13 TOE Queue 13 Full Interrupt */ ++ unsigned int toe_q14_full : 1; /* bit 14 TOE Queue 14 Full Interrupt */ ++ unsigned int toe_q15_full : 1; /* bit 15 TOE Queue 15 Full Interrupt */ ++ unsigned int toe_q16_full : 1; /* bit 16 TOE Queue 16 Full Interrupt */ ++ unsigned int toe_q17_full : 1; /* bit 17 TOE Queue 17 Full Interrupt */ ++ unsigned int toe_q18_full : 1; /* bit 18 TOE Queue 18 Full Interrupt */ ++ unsigned int toe_q19_full : 1; /* bit 19 TOE Queue 19 Full Interrupt */ ++ unsigned int toe_q20_full : 1; /* bit 20 TOE Queue 20 Full Interrupt */ ++ unsigned int toe_q21_full : 1; /* bit 21 TOE Queue 21 Full Interrupt */ ++ unsigned int toe_q22_full : 1; /* bit 22 TOE Queue 22 Full Interrupt */ ++ unsigned int toe_q23_full : 1; /* bit 23 TOE Queue 23 Full Interrupt */ ++ unsigned int toe_q24_full : 1; /* bit 24 TOE Queue 24 Full Interrupt */ ++ unsigned int toe_q25_full : 1; /* bit 25 TOE Queue 25 Full Interrupt */ ++ unsigned int toe_q26_full : 1; /* bit 26 TOE Queue 26 Full Interrupt */ ++ unsigned int toe_q27_full : 1; /* bit 27 TOE Queue 27 Full Interrupt */ ++ unsigned int toe_q28_full : 1; /* bit 28 TOE Queue 28 Full Interrupt */ ++ unsigned int toe_q29_full : 1; /* bit 29 TOE Queue 29 Full Interrupt */ ++ unsigned int toe_q30_full : 1; /* bit 30 TOE Queue 30 Full Interrupt */ ++ unsigned int toe_q31_full : 1; /* bit 31 TOE Queue 31 Full Interrupt */ ++ } bits; ++} INTR_REG2_T; ++ ++#define TOE_QL_FULL_INT_BIT(x) BIT(x) ++ ++/* ++ * Interrupt Status Register 3 (offset 0x0050) ++ * Interrupt Mask Register 3 (offset 0x0054) ++ * Interrupt Select Register 3 (offset 0x0058) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0050 { ++ unsigned int toe_q32_full : 1; /* bit 32 TOE Queue 32 Full Interrupt */ ++ unsigned int toe_q33_full : 1; /* bit 33 TOE Queue 33 Full Interrupt */ ++ unsigned int toe_q34_full : 1; /* bit 34 TOE Queue 34 Full Interrupt */ ++ unsigned int toe_q35_full : 1; /* bit 35 TOE Queue 35 Full Interrupt */ ++ unsigned int toe_q36_full : 1; /* bit 36 TOE Queue 36 Full Interrupt */ ++ unsigned int toe_q37_full : 1; /* bit 37 TOE Queue 37 Full Interrupt */ ++ unsigned int toe_q38_full : 1; /* bit 38 TOE Queue 38 Full Interrupt */ ++ unsigned int toe_q39_full : 1; /* bit 39 TOE Queue 39 Full Interrupt */ ++ unsigned int toe_q40_full : 1; /* bit 40 TOE Queue 40 Full Interrupt */ ++ unsigned int toe_q41_full : 1; /* bit 41 TOE Queue 41 Full Interrupt */ ++ unsigned int toe_q42_full : 1; /* bit 42 TOE Queue 42 Full Interrupt */ ++ unsigned int toe_q43_full : 1; /* bit 43 TOE Queue 43 Full Interrupt */ ++ unsigned int toe_q44_full : 1; /* bit 44 TOE Queue 44 Full Interrupt */ ++ unsigned int toe_q45_full : 1; /* bit 45 TOE Queue 45 Full Interrupt */ ++ unsigned int toe_q46_full : 1; /* bit 46 TOE Queue 46 Full Interrupt */ ++ unsigned int toe_q47_full : 1; /* bit 47 TOE Queue 47 Full Interrupt */ ++ unsigned int toe_q48_full : 1; /* bit 48 TOE Queue 48 Full Interrupt */ ++ unsigned int toe_q49_full : 1; /* bit 49 TOE Queue 49 Full Interrupt */ ++ unsigned int toe_q50_full : 1; /* bit 50 TOE Queue 50 Full Interrupt */ ++ unsigned int toe_q51_full : 1; /* bit 51 TOE Queue 51 Full Interrupt */ ++ unsigned int toe_q52_full : 1; /* bit 52 TOE Queue 52 Full Interrupt */ ++ unsigned int toe_q53_full : 1; /* bit 53 TOE Queue 53 Full Interrupt */ ++ unsigned int toe_q54_full : 1; /* bit 54 TOE Queue 54 Full Interrupt */ ++ unsigned int toe_q55_full : 1; /* bit 55 TOE Queue 55 Full Interrupt */ ++ unsigned int toe_q56_full : 1; /* bit 56 TOE Queue 56 Full Interrupt */ ++ unsigned int toe_q57_full : 1; /* bit 57 TOE Queue 57 Full Interrupt */ ++ unsigned int toe_q58_full : 1; /* bit 58 TOE Queue 58 Full Interrupt */ ++ unsigned int toe_q59_full : 1; /* bit 59 TOE Queue 59 Full Interrupt */ ++ unsigned int toe_q60_full : 1; /* bit 60 TOE Queue 60 Full Interrupt */ ++ unsigned int toe_q61_full : 1; /* bit 61 TOE Queue 61 Full Interrupt */ ++ unsigned int toe_q62_full : 1; /* bit 62 TOE Queue 62 Full Interrupt */ ++ unsigned int toe_q63_full : 1; /* bit 63 TOE Queue 63 Full Interrupt */ ++ } bits; ++} INTR_REG3_T; ++ ++#define TOE_QH_FULL_INT_BIT(x) BIT(x-32) ++ ++/* ++ * Interrupt Status Register 4 (offset 0x0060) ++ * Interrupt Mask Register 4 (offset 0x0064) ++ * Interrupt Select Register 4 (offset 0x0068) ++ */ ++typedef union { ++ unsigned char byte; ++ struct bit_0060 { ++ unsigned char status_changed : 1; /* Status Changed Intr for RGMII Mode */ ++ unsigned char rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */ ++ unsigned char tx_pause_off : 1; /* received pause off frame interrupt */ ++ unsigned char rx_pause_off : 1; /* received pause off frame interrupt */ ++ unsigned char tx_pause_on : 1; /* transmit pause on frame interrupt */ ++ unsigned char rx_pause_on : 1; /* received pause on frame interrupt */ ++ unsigned char cnt_full : 1; /* MIB counters half full interrupt */ ++ unsigned char reserved : 1; /* */ ++ } __packed bits; ++} __packed GMAC_INTR_T; ++ ++typedef union { ++ unsigned int bits32; ++ struct bit_0060_2 { ++ unsigned int swfq_empty : 1; /* bit 0 Software Free Queue Empty Intr. */ ++ unsigned int hwfq_empty : 1; /* bit 1 Hardware Free Queue Empty Intr. */ ++ unsigned int class_qf_int : 14; /* bit 15:2 Classification Rx Queue13-0 Full Intr. */ ++ GMAC_INTR_T gmac0; ++ GMAC_INTR_T gmac1; ++ } bits; ++} INTR_REG4_T; ++ ++#define GMAC1_RESERVED_INT_BIT BIT(31) ++#define GMAC1_MIB_INT_BIT BIT(30) ++#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29) ++#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28) ++#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27) ++#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26) ++#define GMAC1_RX_OVERRUN_INT_BIT BIT(25) ++#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24) ++#define GMAC0_RESERVED_INT_BIT BIT(23) ++#define GMAC0_MIB_INT_BIT BIT(22) ++#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21) ++#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20) ++#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19) ++#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18) ++#define GMAC0_RX_OVERRUN_INT_BIT BIT(17) ++#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16) ++#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2)) ++#define HWFQ_EMPTY_INT_BIT BIT(1) ++#define SWFQ_EMPTY_INT_BIT BIT(0) ++ ++#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \ ++ GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \ ++ GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \ ++ GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT) ++#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \ ++ GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \ ++ GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \ ++ GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT) ++ ++#define CLASS_RX_FULL_INT_BITS 0xfffc ++ ++/* ++ * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0070_2 { ++ unsigned int swfq_empty : 8; /* 7:0 Software Free Queue Empty Threshold */ ++ unsigned int hwfq_empty : 8; /* 15:8 Hardware Free Queue Empty Threshold */ ++ unsigned int intrq : 8; /* 23:16 */ ++ unsigned int toe_class : 8; /* 31:24 */ ++ } bits; ++} QUEUE_THRESHOLD_T; ++ ++ ++/* ++ * GMAC DMA Control Register ++ * GMAC0 offset 0x8000 ++ * GMAC1 offset 0xC000 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8000 { ++ unsigned int td_bus : 2; /* bit 1:0 Peripheral Bus Width */ ++ unsigned int td_burst_size : 2; /* bit 3:2 TxDMA max burst size for every AHB request */ ++ unsigned int td_prot : 4; /* bit 7:4 TxDMA protection control */ ++ unsigned int rd_bus : 2; /* bit 9:8 Peripheral Bus Width */ ++ unsigned int rd_burst_size : 2; /* bit 11:10 DMA max burst size for every AHB request */ ++ unsigned int rd_prot : 4; /* bit 15:12 DMA Protection Control */ ++ unsigned int rd_insert_bytes : 2; /* bit 17:16 */ ++ unsigned int reserved : 10; /* bit 27:18 */ ++ unsigned int drop_small_ack : 1; /* bit 28 1: Drop, 0: Accept */ ++ unsigned int loopback : 1; /* bit 29 Loopback TxDMA to RxDMA */ ++ unsigned int td_enable : 1; /* bit 30 Tx DMA Enable */ ++ unsigned int rd_enable : 1; /* bit 31 Rx DMA Enable */ ++ } bits; ++} GMAC_DMA_CTRL_T; ++ ++/* ++ * GMAC Tx Weighting Control Register 0 ++ * GMAC0 offset 0x8004 ++ * GMAC1 offset 0xC004 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8004 { ++ unsigned int hw_tq0 : 6; /* bit 5:0 HW TX Queue 3 */ ++ unsigned int hw_tq1 : 6; /* bit 11:6 HW TX Queue 2 */ ++ unsigned int hw_tq2 : 6; /* bit 17:12 HW TX Queue 1 */ ++ unsigned int hw_tq3 : 6; /* bit 23:18 HW TX Queue 0 */ ++ unsigned int reserved : 8; /* bit 31:24 */ ++ } bits; ++} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */ ++ ++/* ++ * GMAC Tx Weighting Control Register 1 ++ * GMAC0 offset 0x8008 ++ * GMAC1 offset 0xC008 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8008 { ++ unsigned int sw_tq0 : 5; /* bit 4:0 SW TX Queue 0 */ ++ unsigned int sw_tq1 : 5; /* bit 9:5 SW TX Queue 1 */ ++ unsigned int sw_tq2 : 5; /* bit 14:10 SW TX Queue 2 */ ++ unsigned int sw_tq3 : 5; /* bit 19:15 SW TX Queue 3 */ ++ unsigned int sw_tq4 : 5; /* bit 24:20 SW TX Queue 4 */ ++ unsigned int sw_tq5 : 5; /* bit 29:25 SW TX Queue 5 */ ++ unsigned int reserved : 2; /* bit 31:30 */ ++ } bits; ++} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */ ++ ++/* ++ * Queue Read/Write Pointer ++ * GMAC SW TX Queue 0~5 Read/Write Pointer register ++ * GMAC0 offset 0x800C ~ 0x8020 ++ * GMAC1 offset 0xC00C ~ 0xC020 ++ * GMAC HW TX Queue 0~3 Read/Write Pointer register ++ * GMAC0 offset 0x8024 ~ 0x8030 ++ * GMAC1 offset 0xC024 ~ 0xC030 ++ * ++ * see DMA_RWPTR_T structure ++ */ ++ ++/* ++ * GMAC DMA Tx First Description Address Register ++ * GMAC0 offset 0x8038 ++ * GMAC1 offset 0xC038 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8038 { ++ unsigned int reserved : 3; ++ unsigned int td_busy : 1; /* bit 3 1: TxDMA busy; 0: TxDMA idle */ ++ unsigned int td_first_des_ptr : 28; /* bit 31:4 first descriptor address */ ++ } bits; ++} GMAC_TXDMA_FIRST_DESC_T; ++ ++/* ++ * GMAC DMA Tx Current Description Address Register ++ * GMAC0 offset 0x803C ++ * GMAC1 offset 0xC03C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_803C { ++ unsigned int reserved : 4; ++ unsigned int td_curr_desc_ptr : 28; /* bit 31:4 current descriptor address */ ++ } bits; ++} GMAC_TXDMA_CURR_DESC_T; ++ ++/* ++ * GMAC DMA Tx Description Word 0 Register ++ * GMAC0 offset 0x8040 ++ * GMAC1 offset 0xC040 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8040 { ++ unsigned int buffer_size : 16; /* bit 15:0 Transfer size */ ++ unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */ ++ unsigned int status_tx_ok : 1; /* bit 22 Tx Status, 1: Successful 0: Failed */ ++ unsigned int status_rvd : 6; /* bit 28:23 Tx Status, Reserved bits */ ++ unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */ ++ unsigned int derr : 1; /* bit 30 data error during processing this descriptor */ ++ unsigned int reserved : 1; /* bit 31 */ ++ } bits; ++} GMAC_TXDESC_0_T; ++ ++/* ++ * GMAC DMA Tx Description Word 1 Register ++ * GMAC0 offset 0x8044 ++ * GMAC1 offset 0xC044 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct txdesc_word1 { ++ unsigned int byte_count : 16; /* bit 15: 0 Tx Frame Byte Count */ ++ unsigned int mtu_enable : 1; /* bit 16 TSS segmentation use MTU setting */ ++ unsigned int ip_chksum : 1; /* bit 17 IPV4 Header Checksum Enable */ ++ unsigned int ipv6_enable : 1; /* bit 18 IPV6 Tx Enable */ ++ unsigned int tcp_chksum : 1; /* bit 19 TCP Checksum Enable */ ++ unsigned int udp_chksum : 1; /* bit 20 UDP Checksum Enable */ ++ unsigned int bypass_tss : 1; /* bit 21 Bypass HW offload engine */ ++ unsigned int ip_fixed_len : 1; /* bit 22 Don't update IP length field */ ++ unsigned int reserved : 9; /* bit 31:23 Tx Flag, Reserved */ ++ } bits; ++} GMAC_TXDESC_1_T; ++ ++#define TSS_IP_FIXED_LEN_BIT BIT(22) ++#define TSS_BYPASS_BIT BIT(21) ++#define TSS_UDP_CHKSUM_BIT BIT(20) ++#define TSS_TCP_CHKSUM_BIT BIT(19) ++#define TSS_IPV6_ENABLE_BIT BIT(18) ++#define TSS_IP_CHKSUM_BIT BIT(17) ++#define TSS_MTU_ENABLE_BIT BIT(16) ++ ++#define TSS_CHECKUM_ENABLE \ ++ (TSS_IP_CHKSUM_BIT|TSS_IPV6_ENABLE_BIT| \ ++ TSS_TCP_CHKSUM_BIT|TSS_UDP_CHKSUM_BIT) ++ ++/* ++ * GMAC DMA Tx Description Word 2 Register ++ * GMAC0 offset 0x8048 ++ * GMAC1 offset 0xC048 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int buf_adr; ++} GMAC_TXDESC_2_T; ++ ++/* ++ * GMAC DMA Tx Description Word 3 Register ++ * GMAC0 offset 0x804C ++ * GMAC1 offset 0xC04C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct txdesc_word3 { ++ unsigned int mtu_size : 13; /* bit 12: 0 Tx Frame Byte Count */ ++ unsigned int reserved : 16; /* bit 28:13 */ ++ unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */ ++ unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */ ++ } bits; ++} GMAC_TXDESC_3_T; ++#define SOF_EOF_BIT_MASK 0x3fffffff ++#define SOF_BIT 0x80000000 ++#define EOF_BIT 0x40000000 ++#define EOFIE_BIT BIT(29) ++#define MTU_SIZE_BIT_MASK 0x1fff ++ ++/* ++ * GMAC Tx Descriptor ++ */ ++typedef struct { ++ GMAC_TXDESC_0_T word0; ++ GMAC_TXDESC_1_T word1; ++ GMAC_TXDESC_2_T word2; ++ GMAC_TXDESC_3_T word3; ++} GMAC_TXDESC_T; ++ ++/* ++ * GMAC DMA Rx First Description Address Register ++ * GMAC0 offset 0x8058 ++ * GMAC1 offset 0xC058 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8058 { ++ unsigned int reserved : 3; /* bit 2:0 */ ++ unsigned int rd_busy : 1; /* bit 3 1-RxDMA busy; 0-RxDMA idle */ ++ unsigned int rd_first_des_ptr : 28; /* bit 31:4 first descriptor address */ ++ } bits; ++} GMAC_RXDMA_FIRST_DESC_T; ++ ++/* ++ * GMAC DMA Rx Current Description Address Register ++ * GMAC0 offset 0x805C ++ * GMAC1 offset 0xC05C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_805C { ++ unsigned int reserved : 4; /* bit 3:0 */ ++ unsigned int rd_curr_des_ptr : 28; /* bit 31:4 current descriptor address */ ++ } bits; ++} GMAC_RXDMA_CURR_DESC_T; ++ ++/* ++ * GMAC DMA Rx Description Word 0 Register ++ * GMAC0 offset 0x8060 ++ * GMAC1 offset 0xC060 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8060 { ++ unsigned int buffer_size : 16; /* bit 15:0 number of descriptors used for the current frame */ ++ unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */ ++ unsigned int status : 4; /* bit 24:22 Status of rx frame */ ++ unsigned int chksum_status : 3; /* bit 28:26 Check Sum Status */ ++ unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */ ++ unsigned int derr : 1; /* bit 30 data error during processing this descriptor */ ++ unsigned int drop : 1; /* bit 31 TOE/CIS Queue Full dropped packet to default queue */ ++ } bits; ++} GMAC_RXDESC_0_T; ++ ++#define GMAC_RXDESC_0_T_derr BIT(30) ++#define GMAC_RXDESC_0_T_perr BIT(29) ++#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26)) ++#define GMAC_RXDESC_0_T_status(x) BIT((x+22)) ++#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16)) ++ ++#define RX_CHKSUM_IP_UDP_TCP_OK 0 ++#define RX_CHKSUM_IP_OK_ONLY 1 ++#define RX_CHKSUM_NONE 2 ++#define RX_CHKSUM_IP_ERR_UNKNOWN 4 ++#define RX_CHKSUM_IP_ERR 5 ++#define RX_CHKSUM_TCP_UDP_ERR 6 ++#define RX_CHKSUM_NUM 8 ++ ++#define RX_STATUS_GOOD_FRAME 0 ++#define RX_STATUS_TOO_LONG_GOOD_CRC 1 ++#define RX_STATUS_RUNT_FRAME 2 ++#define RX_STATUS_SFD_NOT_FOUND 3 ++#define RX_STATUS_CRC_ERROR 4 ++#define RX_STATUS_TOO_LONG_BAD_CRC 5 ++#define RX_STATUS_ALIGNMENT_ERROR 6 ++#define RX_STATUS_TOO_LONG_BAD_ALIGN 7 ++#define RX_STATUS_RX_ERR 8 ++#define RX_STATUS_DA_FILTERED 9 ++#define RX_STATUS_BUFFER_FULL 10 ++#define RX_STATUS_NUM 16 ++ ++#define RX_ERROR_LENGTH(s) \ ++ ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \ ++ (s) == RX_STATUS_TOO_LONG_BAD_CRC || \ ++ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN) ++#define RX_ERROR_OVER(s) \ ++ ((s) == RX_STATUS_BUFFER_FULL) ++#define RX_ERROR_CRC(s) \ ++ ((s) == RX_STATUS_CRC_ERROR || \ ++ (s) == RX_STATUS_TOO_LONG_BAD_CRC) ++#define RX_ERROR_FRAME(s) \ ++ ((s) == RX_STATUS_ALIGNMENT_ERROR || \ ++ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN) ++#define RX_ERROR_FIFO(s) \ ++ (0) ++ ++/* ++ * GMAC DMA Rx Description Word 1 Register ++ * GMAC0 offset 0x8064 ++ * GMAC1 offset 0xC064 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct rxdesc_word1 { ++ unsigned int byte_count : 16; /* bit 15: 0 Rx Frame Byte Count */ ++ unsigned int sw_id : 16; /* bit 31:16 Software ID */ ++ } bits; ++} GMAC_RXDESC_1_T; ++ ++/* ++ * GMAC DMA Rx Description Word 2 Register ++ * GMAC0 offset 0x8068 ++ * GMAC1 offset 0xC068 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int buf_adr; ++} GMAC_RXDESC_2_T; ++ ++#define RX_INSERT_NONE 0 ++#define RX_INSERT_1_BYTE 1 ++#define RX_INSERT_2_BYTE 2 ++#define RX_INSERT_3_BYTE 3 ++ ++/* ++ * GMAC DMA Rx Description Word 3 Register ++ * GMAC0 offset 0x806C ++ * GMAC1 offset 0xC06C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct rxdesc_word3 { ++ unsigned int l3_offset : 8; /* bit 7: 0 L3 data offset */ ++ unsigned int l4_offset : 8; /* bit 15: 8 L4 data offset */ ++ unsigned int l7_offset : 8; /* bit 23: 16 L7 data offset */ ++ unsigned int dup_ack : 1; /* bit 24 Duplicated ACK detected */ ++ unsigned int abnormal : 1; /* bit 25 abnormal case found */ ++ unsigned int option : 1; /* bit 26 IPV4 option or IPV6 extension header */ ++ unsigned int out_of_seq : 1; /* bit 27 Out of Sequence packet */ ++ unsigned int ctrl_flag : 1; /* bit 28 Control Flag is present */ ++ unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */ ++ unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */ ++ } bits; ++} GMAC_RXDESC_3_T; ++ ++/* ++ * GMAC Rx Descriptor ++ */ ++typedef struct { ++ GMAC_RXDESC_0_T word0; ++ GMAC_RXDESC_1_T word1; ++ GMAC_RXDESC_2_T word2; ++ GMAC_RXDESC_3_T word3; ++} GMAC_RXDESC_T; ++ ++/* ++ * GMAC Hash Engine Enable/Action Register 0 Offset Register ++ * GMAC0 offset 0x8070 ++ * GMAC1 offset 0xC070 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8070 { ++ unsigned int mr0hel : 6; /* bit 5:0 match rule 0 hash entry size */ ++ unsigned int mr0_action : 5; /* bit 10:6 Matching Rule 0 action offset */ ++ unsigned int reserved0 : 4; /* bit 14:11 */ ++ unsigned int mr0en : 1; /* bit 15 Enable Matching Rule 0 */ ++ unsigned int mr1hel : 6; /* bit 21:16 match rule 1 hash entry size */ ++ unsigned int mr1_action : 5; /* bit 26:22 Matching Rule 1 action offset */ ++ unsigned int timing : 3; /* bit 29:27 */ ++ unsigned int reserved1 : 1; /* bit 30 */ ++ unsigned int mr1en : 1; /* bit 31 Enable Matching Rule 1 */ ++ } bits; ++} GMAC_HASH_ENABLE_REG0_T; ++ ++/* ++ * GMAC Hash Engine Enable/Action Register 1 Offset Register ++ * GMAC0 offset 0x8074 ++ * GMAC1 offset 0xC074 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8074 { ++ unsigned int mr2hel : 6; /* bit 5:0 match rule 2 hash entry size */ ++ unsigned int mr2_action : 5; /* bit 10:6 Matching Rule 2 action offset */ ++ unsigned int reserved2 : 4; /* bit 14:11 */ ++ unsigned int mr2en : 1; /* bit 15 Enable Matching Rule 2 */ ++ unsigned int mr3hel : 6; /* bit 21:16 match rule 3 hash entry size */ ++ unsigned int mr3_action : 5; /* bit 26:22 Matching Rule 3 action offset */ ++ unsigned int reserved1 : 4; /* bit 30:27 */ ++ unsigned int mr3en : 1; /* bit 31 Enable Matching Rule 3 */ ++ } bits; ++} GMAC_HASH_ENABLE_REG1_T; ++ ++/* ++ * GMAC Matching Rule Control Register 0 ++ * GMAC0 offset 0x8078 ++ * GMAC1 offset 0xC078 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8078 { ++ unsigned int sprx : 8; /* bit 7:0 Support Protocol Register 7:0 */ ++ unsigned int reserved2 : 4; /* bit 11:8 */ ++ unsigned int tos_traffic : 1; /* bit 12 IPV4 TOS or IPV6 Traffice Class */ ++ unsigned int flow_lable : 1; /* bit 13 IPV6 Flow label */ ++ unsigned int ip_hdr_len : 1; /* bit 14 IPV4 Header length */ ++ unsigned int ip_version : 1; /* bit 15 0: IPV4, 1: IPV6 */ ++ unsigned int reserved1 : 3; /* bit 18:16 */ ++ unsigned int pppoe : 1; /* bit 19 PPPoE Session ID enable */ ++ unsigned int vlan : 1; /* bit 20 VLAN ID enable */ ++ unsigned int ether_type : 1; /* bit 21 Ethernet type enable */ ++ unsigned int sa : 1; /* bit 22 MAC SA enable */ ++ unsigned int da : 1; /* bit 23 MAC DA enable */ ++ unsigned int priority : 3; /* bit 26:24 priority if multi-rules matched */ ++ unsigned int port : 1; /* bit 27 PORT ID matching enable */ ++ unsigned int l7 : 1; /* bit 28 L7 matching enable */ ++ unsigned int l4 : 1; /* bit 29 L4 matching enable */ ++ unsigned int l3 : 1; /* bit 30 L3 matching enable */ ++ unsigned int l2 : 1; /* bit 31 L2 matching enable */ ++ } bits; ++} GMAC_MRxCR0_T; ++ ++#define MR_L2_BIT BIT(31) ++#define MR_L3_BIT BIT(30) ++#define MR_L4_BIT BIT(29) ++#define MR_L7_BIT BIT(28) ++#define MR_PORT_BIT BIT(27) ++#define MR_PRIORITY_BIT BIT(26) ++#define MR_DA_BIT BIT(23) ++#define MR_SA_BIT BIT(22) ++#define MR_ETHER_TYPE_BIT BIT(21) ++#define MR_VLAN_BIT BIT(20) ++#define MR_PPPOE_BIT BIT(19) ++#define MR_IP_VER_BIT BIT(15) ++#define MR_IP_HDR_LEN_BIT BIT(14) ++#define MR_FLOW_LABLE_BIT BIT(13) ++#define MR_TOS_TRAFFIC_BIT BIT(12) ++#define MR_SPR_BIT(x) BIT(x) ++#define MR_SPR_BITS 0xff ++ ++/* ++ * GMAC Matching Rule Control Register 1 ++ * GMAC0 offset 0x807C ++ * GMAC1 offset 0xC07C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_807C { ++ unsigned int l4_byte0_15 : 16; /* bit 15: 0 */ ++ unsigned int dip_netmask : 7; /* bit 22:16 Dest IP net mask, number of mask bits */ ++ unsigned int dip : 1; /* bit 23 Dest IP */ ++ unsigned int sip_netmask : 7; /* bit 30:24 Srce IP net mask, number of mask bits */ ++ unsigned int sip : 1; /* bit 31 Srce IP */ ++ } bits; ++} GMAC_MRxCR1_T; ++ ++/* ++ * GMAC Matching Rule Control Register 2 ++ * GMAC0 offset 0x8080 ++ * GMAC1 offset 0xC080 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8080 { ++ unsigned int l7_byte0_23 : 24; /* bit 23:0 */ ++ unsigned int l4_byte16_24 : 8; /* bit 31: 24 */ ++ } bits; ++} GMAC_MRxCR2_T; ++ ++/* ++ * GMAC Support registers ++ * GMAC0 offset 0x80A8 ++ * GMAC1 offset 0xC0A8 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_80A8 { ++ unsigned int protocol : 8; /* bit 7:0 Supported protocol */ ++ unsigned int swap : 3; /* bit 10:8 Swap */ ++ unsigned int reserved : 21; /* bit 31:11 */ ++ } bits; ++} GMAC_SPR_T; ++ ++/* ++ * GMAC_AHB_WEIGHT registers ++ * GMAC0 offset 0x80C8 ++ * GMAC1 offset 0xC0C8 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_80C8 { ++ unsigned int hash_weight : 5; /* 4:0 */ ++ unsigned int rx_weight : 5; /* 9:5 */ ++ unsigned int tx_weight : 5; /* 14:10 */ ++ unsigned int pre_req : 5; /* 19:15 Rx Data Pre Request FIFO Threshold */ ++ unsigned int tqDV_threshold : 5; /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */ ++ unsigned int reserved : 7; /* 31:25 */ ++ } bits; ++} GMAC_AHB_WEIGHT_T; ++ ++/* ++ * the register structure of GMAC ++ */ ++ ++/* ++ * GMAC RX FLTR ++ * GMAC0 Offset 0xA00C ++ * GMAC1 Offset 0xE00C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_000c { ++ unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */ ++ unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */ ++ unsigned int broadcast : 1; /* enable receive of broadcast frames */ ++ unsigned int promiscuous : 1; /* enable receive of all frames */ ++ unsigned int error : 1; /* enable receive of all error frames */ ++ unsigned int : 27; ++ } bits; ++} GMAC_RX_FLTR_T; ++ ++/* ++ * GMAC Configuration 0 ++ * GMAC0 Offset 0xA018 ++ * GMAC1 Offset 0xE018 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_0018 { ++ unsigned int dis_tx : 1; /* 0: disable transmit */ ++ unsigned int dis_rx : 1; /* 1: disable receive */ ++ unsigned int loop_back : 1; /* 2: transmit data loopback enable */ ++ unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */ ++ unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */ ++ unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */ ++ unsigned int dis_bkoff : 1; /* 11: disable back-off function */ ++ unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */ ++ unsigned int sim_test : 1; /* 13: speed up timers in simulation */ ++ unsigned int rx_fc_en : 1; /* 14: RX flow control enable */ ++ unsigned int tx_fc_en : 1; /* 15: TX flow control enable */ ++ unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */ ++ unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */ ++ unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */ ++ unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */ ++ unsigned int rgmm_edge : 1; /* 20 */ ++ unsigned int rxc_inv : 1; /* 21 */ ++ unsigned int ipv6_exthdr_order : 1; /* 22 */ ++ unsigned int rx_err_detect : 1; /* 23 */ ++ unsigned int port0_chk_hwq : 1; /* 24 */ ++ unsigned int port1_chk_hwq : 1; /* 25 */ ++ unsigned int port0_chk_toeq : 1; /* 26 */ ++ unsigned int port1_chk_toeq : 1; /* 27 */ ++ unsigned int port0_chk_classq : 1; /* 28 */ ++ unsigned int port1_chk_classq : 1; /* 29 */ ++ unsigned int reserved : 2; /* 31 */ ++ } bits; ++} GMAC_CONFIG0_T; ++ ++#define CONFIG0_TX_RX_DISABLE (BIT(1)|BIT(0)) ++#define CONFIG0_RX_CHKSUM (BIT(18)|BIT(17)) ++#define CONFIG0_FLOW_RX (BIT(14)) ++#define CONFIG0_FLOW_TX (BIT(15)) ++#define CONFIG0_FLOW_TX_RX (BIT(14)|BIT(15)) ++#define CONFIG0_FLOW_CTL (BIT(14)|BIT(15)) ++ ++#define CONFIG0_MAXLEN_SHIFT 8 ++#define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT) ++#define CONFIG0_MAXLEN_1536 0 ++#define CONFIG0_MAXLEN_1518 1 ++#define CONFIG0_MAXLEN_1522 2 ++#define CONFIG0_MAXLEN_1542 3 ++#define CONFIG0_MAXLEN_9k 4 /* 9212 */ ++#define CONFIG0_MAXLEN_10k 5 /* 10236 */ ++#define CONFIG0_MAXLEN_1518__6 6 ++#define CONFIG0_MAXLEN_1518__7 7 ++ ++/* ++ * GMAC Configuration 1 ++ * GMAC0 Offset 0xA01C ++ * GMAC1 Offset 0xE01C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_001c { ++ unsigned int set_threshold : 8; /* flow control set threshold */ ++ unsigned int rel_threshold : 8; /* flow control release threshold */ ++ unsigned int reserved : 16; ++ } bits; ++} GMAC_CONFIG1_T; ++ ++#define GMAC_FLOWCTRL_SET_MAX 32 ++#define GMAC_FLOWCTRL_SET_MIN 0 ++#define GMAC_FLOWCTRL_RELEASE_MAX 32 ++#define GMAC_FLOWCTRL_RELEASE_MIN 0 ++ ++/* ++ * GMAC Configuration 2 ++ * GMAC0 Offset 0xA020 ++ * GMAC1 Offset 0xE020 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_0020 { ++ unsigned int set_threshold : 16; /* flow control set threshold */ ++ unsigned int rel_threshold : 16; /* flow control release threshold */ ++ } bits; ++} GMAC_CONFIG2_T; ++ ++/* ++ * GMAC Configuration 3 ++ * GMAC0 Offset 0xA024 ++ * GMAC1 Offset 0xE024 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_0024 { ++ unsigned int set_threshold : 16; /* flow control set threshold */ ++ unsigned int rel_threshold : 16; /* flow control release threshold */ ++ } bits; ++} GMAC_CONFIG3_T; ++ ++ ++/* ++ * GMAC STATUS ++ * GMAC0 Offset 0xA02C ++ * GMAC1 Offset 0xE02C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_002c { ++ unsigned int link : 1; /* link status */ ++ unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */ ++ unsigned int duplex : 1; /* duplex mode */ ++ unsigned int reserved : 1; ++ unsigned int mii_rmii : 2; /* PHY interface type */ ++ unsigned int : 25; ++ } bits; ++} GMAC_STATUS_T; ++ ++#define GMAC_SPEED_10 0 ++#define GMAC_SPEED_100 1 ++#define GMAC_SPEED_1000 2 ++ ++#define GMAC_PHY_MII 0 ++#define GMAC_PHY_GMII 1 ++#define GMAC_PHY_RGMII_100_10 2 ++#define GMAC_PHY_RGMII_1000 3 ++ ++/* ++ * Queue Header ++ * (1) TOE Queue Header ++ * (2) Non-TOE Queue Header ++ * (3) Interrupt Queue Header ++ * ++ * memory Layout ++ * TOE Queue Header ++ * 0x60003000 +---------------------------+ 0x0000 ++ * | TOE Queue 0 Header | ++ * | 8 * 4 Bytes | ++ * +---------------------------+ 0x0020 ++ * | TOE Queue 1 Header | ++ * | 8 * 4 Bytes | ++ * +---------------------------+ 0x0040 ++ * | ...... | ++ * | | ++ * +---------------------------+ ++ * ++ * Non TOE Queue Header ++ * 0x60002000 +---------------------------+ 0x0000 ++ * | Default Queue 0 Header | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ 0x0008 ++ * | Default Queue 1 Header | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ 0x0010 ++ * | Classification Queue 0 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * | Classification Queue 1 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ (n * 8 + 0x10) ++ * | ... | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ (13 * 8 + 0x10) ++ * | Classification Queue 13 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ 0x80 ++ * | Interrupt Queue 0 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * | Interrupt Queue 1 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * | Interrupt Queue 2 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * | Interrupt Queue 3 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * ++ */ ++#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32) ++#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1)) ++#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x)) ++#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10) ++#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80) ++#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8) ++#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1)) ++/* ++ * TOE Queue Header Word 0 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int base_size; ++} TOE_QHDR0_T; ++ ++#define TOE_QHDR0_BASE_MASK (~0x0f) ++ ++/* ++ * TOE Queue Header Word 1 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr1 { ++ unsigned int rptr : 16; /* bit 15:0 */ ++ unsigned int wptr : 16; /* bit 31:16 */ ++ } bits; ++} TOE_QHDR1_T; ++ ++/* ++ * TOE Queue Header Word 2 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr2 { ++ unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */ ++ unsigned int reserved : 7; /* bit 23:17 */ ++ unsigned int dack : 1; /* bit 24 1: Duplicated ACK */ ++ unsigned int abn : 1; /* bit 25 1: Abnormal case Found */ ++ unsigned int tcp_opt : 1; /* bit 26 1: Have TCP option */ ++ unsigned int ip_opt : 1; /* bit 27 1: have IPV4 option or IPV6 Extension header */ ++ unsigned int sat : 1; /* bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */ ++ unsigned int osq : 1; /* bit 29 1: out of sequence */ ++ unsigned int ctl : 1; /* bit 30 1: have control flag bits (except ack) */ ++ unsigned int usd : 1; /* bit 31 0: if no data assembled yet */ ++ } bits; ++} TOE_QHDR2_T; ++ ++/* ++ * TOE Queue Header Word 3 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int seq_num; ++} TOE_QHDR3_T; ++ ++/* ++ * TOE Queue Header Word 4 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int ack_num; ++} TOE_QHDR4_T; ++ ++/* ++ * TOE Queue Header Word 5 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr5 { ++ unsigned int AckCnt : 16; /* bit 15:0 */ ++ unsigned int SeqCnt : 16; /* bit 31:16 */ ++ } bits; ++} TOE_QHDR5_T; ++ ++/* ++ * TOE Queue Header Word 6 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr6 { ++ unsigned int WinSize : 16; /* bit 15:0 */ ++ unsigned int iq_num : 2; /* bit 17:16 */ ++ unsigned int MaxPktSize : 14; /* bit 31:18 */ ++ } bits; ++} TOE_QHDR6_T; ++ ++/* ++ * TOE Queue Header Word 7 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr7 { ++ unsigned int AckThreshold : 16; /* bit 15:0 */ ++ unsigned int SeqThreshold : 16; /* bit 31:16 */ ++ } bits; ++} TOE_QHDR7_T; ++ ++/* ++ * TOE Queue Header ++ */ ++typedef struct { ++ TOE_QHDR0_T word0; ++ TOE_QHDR1_T word1; ++ TOE_QHDR2_T word2; ++ TOE_QHDR3_T word3; ++ TOE_QHDR4_T word4; ++ TOE_QHDR5_T word5; ++ TOE_QHDR6_T word6; ++ TOE_QHDR7_T word7; ++} TOE_QHDR_T; ++ ++/* ++ * NONTOE Queue Header Word 0 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int base_size; ++} NONTOE_QHDR0_T; ++ ++#define NONTOE_QHDR0_BASE_MASK (~0x0f) ++ ++/* ++ * NONTOE Queue Header Word 1 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_nonqhdr1 { ++ unsigned int rptr : 16; /* bit 15:0 */ ++ unsigned int wptr : 16; /* bit 31:16 */ ++ } bits; ++} NONTOE_QHDR1_T; ++ ++/* ++ * Non-TOE Queue Header ++ */ ++typedef struct { ++ NONTOE_QHDR0_T word0; ++ NONTOE_QHDR1_T word1; ++} NONTOE_QHDR_T; ++ ++/* ++ * Interrupt Queue Header Word 0 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_intrqhdr0 { ++ unsigned int win_size : 16; /* bit 15:0 Descriptor Ring Size */ ++ unsigned int wptr : 16; /* bit 31:16 Write Pointer where hw stopped */ ++ } bits; ++} INTR_QHDR0_T; ++ ++/* ++ * Interrupt Queue Header Word 1 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_intrqhdr1 { ++ unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */ ++ unsigned int tcp_qid : 8; /* bit 24:17 TCP Queue ID */ ++ unsigned int dack : 1; /* bit 25 1: Duplicated ACK */ ++ unsigned int abn : 1; /* bit 26 1: Abnormal case Found */ ++ unsigned int tcp_opt : 1; /* bit 27 1: Have TCP option */ ++ unsigned int ip_opt : 1; /* bit 28 1: have IPV4 option or IPV6 Extension header */ ++ unsigned int sat : 1; /* bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */ ++ unsigned int osq : 1; /* bit 30 1: out of sequence */ ++ unsigned int ctl : 1; /* bit 31 1: have control flag bits (except ack) */ ++ } bits; ++} INTR_QHDR1_T; ++ ++/* ++ * Interrupt Queue Header Word 2 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int seq_num; ++} INTR_QHDR2_T; ++ ++/* ++ * Interrupt Queue Header Word 3 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int ack_num; ++} INTR_QHDR3_T; ++ ++/* ++ * Interrupt Queue Header Word 4 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_intrqhdr4 { ++ unsigned int AckCnt : 16; /* bit 15:0 Ack# change since last ack# intr. */ ++ unsigned int SeqCnt : 16; /* bit 31:16 Seq# change since last seq# intr. */ ++ } bits; ++} INTR_QHDR4_T; ++ ++/* ++ * Interrupt Queue Header ++ */ ++typedef struct { ++ INTR_QHDR0_T word0; ++ INTR_QHDR1_T word1; ++ INTR_QHDR2_T word2; ++ INTR_QHDR3_T word3; ++ INTR_QHDR4_T word4; ++ unsigned int word5; ++ unsigned int word6; ++ unsigned int word7; ++} INTR_QHDR_T; ++ ++#endif /* _GMAC_SL351x_H */ diff --git a/target/linux/gemini/patches-3.18/121-arm-gemini-register-ethernet.patch b/target/linux/gemini/patches-3.18/121-arm-gemini-register-ethernet.patch new file mode 100644 index 0000000..5ae896c --- /dev/null +++ b/target/linux/gemini/patches-3.18/121-arm-gemini-register-ethernet.patch @@ -0,0 +1,209 @@ +--- a/arch/arm/mach-gemini/board-nas4220b.c ++++ b/arch/arm/mach-gemini/board-nas4220b.c +@@ -28,9 +28,27 @@ + + #include + #include ++#include + + #include "common.h" + ++static struct mdio_gpio_platform_data ib4220b_mdio = { ++ .mdc = 22, ++ .mdio = 21, ++ .phy_mask = ~(1 << 1), ++}; ++ ++static struct platform_device ib4220b_phy_device = { ++ .name = "mdio-gpio", ++ .id = 0, ++ .dev = { .platform_data = &ib4220b_mdio, }, ++}; ++ ++static struct gemini_gmac_platform_data ib4220b_gmac_data = { ++ .bus_id[0] = "gpio-0:01", ++ .interface[0] = PHY_INTERFACE_MODE_RGMII, ++}; ++ + static struct gpio_led ib4220b_leds[] = { + { + .name = "nas4220b:orange:hdd", +@@ -87,15 +105,47 @@ static struct platform_device ib4220b_ke + }, + }; + ++static void __init ib4220b_gmac_init(void) ++{ ++ unsigned int val; ++ ++ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_IO_DRIVING_CTRL)); ++ val |= (0x3 << GMAC0_PADS_SHIFT) | (0x3 << GMAC1_PADS_SHIFT); ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_IO_DRIVING_CTRL)); ++ ++ val = (0x0 << GMAC0_RXDV_SKEW_SHIFT) | (0xf << GMAC0_RXC_SKEW_SHIFT) | ++ (0x7 << GMAC0_TXEN_SKEW_SHIFT) | (0xb << GMAC0_TXC_SKEW_SHIFT) | ++ (0x0 << GMAC1_RXDV_SKEW_SHIFT) | (0xf << GMAC1_RXC_SKEW_SHIFT) | ++ (0x7 << GMAC1_TXEN_SKEW_SHIFT) | (0xa << GMAC1_TXC_SKEW_SHIFT); ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_GMAC_CTRL_SKEW_CTRL)); ++ ++ writel(0x77777777, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_GMAC0_DATA_SKEW_CTRL)); ++ writel(0x77777777, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_GMAC1_DATA_SKEW_CTRL)); ++ ++ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_ARBITRATION1_CTRL)) & ~BURST_LENGTH_MASK; ++ val |= (0x20 << BURST_LENGTH_SHIFT) | GMAC0_HIGH_PRIO | GMAC1_HIGH_PRIO; ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_ARBITRATION1_CTRL)); ++} ++ + static void __init ib4220b_init(void) + { + gemini_gpio_init(); ++ ib4220b_gmac_init(); + platform_register_uart(); + platform_register_pflash(SZ_16M, NULL, 0); + platform_device_register(&ib4220b_led_device); + platform_device_register(&ib4220b_key_device); + platform_register_rtc(); + platform_register_watchdog(); ++ platform_device_register(&ib4220b_phy_device); ++ platform_register_ethernet(&ib4220b_gmac_data); + } + + MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") +--- a/arch/arm/mach-gemini/board-wbd111.c ++++ b/arch/arm/mach-gemini/board-wbd111.c +@@ -22,9 +22,29 @@ + #include + #include + ++#include + + #include "common.h" + ++static struct mdio_gpio_platform_data wbd111_mdio = { ++ .mdc = 22, ++ .mdio = 21, ++ .phy_mask = ~(1 << 1), ++}; ++ ++static struct platform_device wbd111_phy_device = { ++ .name = "mdio-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &wbd111_mdio, ++ }, ++}; ++ ++static struct gemini_gmac_platform_data gmac_data = { ++ .bus_id[0] = "gpio-0:01", ++ .interface[0] = PHY_INTERFACE_MODE_MII, ++}; ++ + static struct gpio_keys_button wbd111_keys[] = { + { + .code = KEY_SETUP, +@@ -123,6 +143,8 @@ static void __init wbd111_init(void) + platform_device_register(&wbd111_keys_device); + platform_register_rtc(); + platform_register_watchdog(); ++ platform_device_register(&wbd111_phy_device); ++ platform_register_ethernet(&gmac_data); + } + + MACHINE_START(WBD111, "Wiliboard WBD-111") +--- a/arch/arm/mach-gemini/board-wbd222.c ++++ b/arch/arm/mach-gemini/board-wbd222.c +@@ -22,9 +22,31 @@ + #include + #include + ++#include + + #include "common.h" + ++static struct mdio_gpio_platform_data wbd222_mdio = { ++ .mdc = 22, ++ .mdio = 21, ++ .phy_mask = ~((1 << 1) | (1 << 3)), ++}; ++ ++static struct platform_device wbd222_phy_device = { ++ .name = "mdio-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &wbd222_mdio, ++ }, ++}; ++ ++static struct gemini_gmac_platform_data gmac_data = { ++ .bus_id[0] = "gpio-0:01", ++ .interface[0] = PHY_INTERFACE_MODE_MII, ++ .bus_id[1] = "gpio-0:03", ++ .interface[1] = PHY_INTERFACE_MODE_MII, ++}; ++ + static struct gpio_keys_button wbd222_keys[] = { + { + .code = KEY_SETUP, +@@ -123,6 +145,8 @@ static void __init wbd222_init(void) + platform_device_register(&wbd222_keys_device); + platform_register_rtc(); + platform_register_watchdog(); ++ platform_device_register(&wbd222_phy_device); ++ platform_register_ethernet(&gmac_data); + } + + MACHINE_START(WBD222, "Wiliboard WBD-222") +--- a/arch/arm/mach-gemini/board-rut1xx.c ++++ b/arch/arm/mach-gemini/board-rut1xx.c +@@ -15,13 +15,35 @@ + #include + #include + #include ++#include + + #include + #include + #include + ++#include ++ + #include "common.h" + ++static struct mdio_gpio_platform_data rut1xx_mdio = { ++ .mdc = 22, ++ .mdio = 21, ++ .phy_mask = ~(1 << 1), ++}; ++ ++static struct platform_device rut1xx_phy_device = { ++ .name = "mdio-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &rut1xx_mdio, ++ }, ++}; ++ ++static struct gemini_gmac_platform_data gmac_data = { ++ .bus_id[0] = "gpio-0:01", ++ .interface[0] = PHY_INTERFACE_MODE_MII, ++}; ++ + static struct gpio_keys_button rut1xx_keys[] = { + { + .code = KEY_SETUP, +@@ -81,6 +103,8 @@ static void __init rut1xx_init(void) + platform_device_register(&rut1xx_keys_device); + platform_register_rtc(); + platform_register_watchdog(); ++ platform_device_register(&rut1xx_phy_device); ++ platform_register_ethernet(&gmac_data); + } + + MACHINE_START(RUT100, "Teltonika RUT100") diff --git a/target/linux/gemini/patches-3.18/130-usb-ehci-fot2g.patch b/target/linux/gemini/patches-3.18/130-usb-ehci-fot2g.patch new file mode 100644 index 0000000..d13554e --- /dev/null +++ b/target/linux/gemini/patches-3.18/130-usb-ehci-fot2g.patch @@ -0,0 +1,210 @@ +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -188,3 +188,64 @@ int platform_register_ethernet(struct ge + + return platform_device_register(ðernet_device); + } ++ ++static struct resource usb0_resources[] = { ++ { ++ .start = GEMINI_USB0_BASE, ++ .end = GEMINI_USB0_BASE + 0xfff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IRQ_USB0, ++ .end = IRQ_USB0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource usb1_resources[] = { ++ { ++ .start = GEMINI_USB1_BASE, ++ .end = GEMINI_USB1_BASE + 0xfff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IRQ_USB1, ++ .end = IRQ_USB1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 usb0_dmamask = 0xffffffffUL; ++static u64 usb1_dmamask = 0xffffffffUL; ++ ++static struct platform_device usb_device[] = { ++ { ++ .name = "ehci-fotg2", ++ .id = 0, ++ .dev = { ++ .dma_mask = &usb0_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(usb0_resources), ++ .resource = usb0_resources, ++ }, ++ { ++ .name = "ehci-fotg2", ++ .id = 1, ++ .dev = { ++ .dma_mask = &usb1_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(usb1_resources), ++ .resource = usb1_resources, ++ }, ++}; ++ ++int __init platform_register_usb(unsigned int id) ++{ ++ if (id > 1) ++ return -EINVAL; ++ ++ return platform_device_register(&usb_device[id]); ++} ++ +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -28,6 +28,7 @@ extern int platform_register_pflash(unsi + unsigned int nr_parts); + extern int platform_register_watchdog(void); + extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata); ++extern int platform_register_usb(unsigned int id); + + extern void gemini_restart(enum reboot_mode mode, const char *cmd); + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -346,11 +346,13 @@ static void ehci_silence_controller(stru + ehci->rh_state = EHCI_RH_HALTED; + ehci_turn_off_all_ports(ehci); + ++#ifndef CONFIG_ARCH_GEMINI + /* make BIOS/etc use companion controller during reboot */ + ehci_writel(ehci, 0, &ehci->regs->configured_flag); + + /* unblock posted writes */ + ehci_readl(ehci, &ehci->regs->configured_flag); ++#endif + spin_unlock_irq(&ehci->lock); + } + +@@ -602,7 +604,9 @@ static int ehci_run (struct usb_hcd *hcd + // Philips, Intel, and maybe others need CMD_RUN before the + // root hub will detect new devices (why?); NEC doesn't + ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); ++#ifndef CONFIG_ARCH_GEMINI + ehci->command |= CMD_RUN; ++#endif + ehci_writel(ehci, ehci->command, &ehci->regs->command); + dbg_cmd (ehci, "init", ehci->command); + +@@ -622,9 +626,11 @@ static int ehci_run (struct usb_hcd *hcd + */ + down_write(&ehci_cf_port_reset_rwsem); + ehci->rh_state = EHCI_RH_RUNNING; ++#ifndef CONFIG_ARCH_GEMINI + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ + msleep(5); ++#endif + up_write(&ehci_cf_port_reset_rwsem); + ehci->last_periodic_enable = ktime_get_real(); + +@@ -762,9 +768,10 @@ static irqreturn_t ehci_irq (struct usb_ + pcd_status = status; + + /* resume root hub? */ ++#ifndef CONFIG_ARCH_GEMINI + if (ehci->rh_state == EHCI_RH_SUSPENDED) + usb_hcd_resume_root_hub(hcd); +- ++#endif + /* get per-port change detect bits */ + if (ehci->has_ppcd) + ppcd = status >> 16; +@@ -1243,6 +1250,11 @@ MODULE_DESCRIPTION(DRIVER_DESC); + MODULE_AUTHOR (DRIVER_AUTHOR); + MODULE_LICENSE ("GPL"); + ++#ifdef CONFIG_ARCH_GEMINI ++#include "ehci-fotg2.c" ++#define PLATFORM_DRIVER ehci_fotg2_driver ++#endif ++ + #ifdef CONFIG_USB_EHCI_FSL + #include "ehci-fsl.c" + #define PLATFORM_DRIVER ehci_fsl_driver +--- a/drivers/usb/host/ehci-timer.c ++++ b/drivers/usb/host/ehci-timer.c +@@ -208,7 +208,9 @@ static void ehci_handle_controller_death + + /* Clean up the mess */ + ehci->rh_state = EHCI_RH_HALTED; ++#ifndef CONFIG_ARCH_GEMINI + ehci_writel(ehci, 0, &ehci->regs->configured_flag); ++#endif + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + ehci_work(ehci); + end_unlink_async(ehci); +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -656,7 +656,12 @@ static inline unsigned int + ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) + { + if (ehci_is_TDI(ehci)) { +- switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { ++#ifdef CONFIG_ARCH_GEMINI ++ portsc = readl(ehci_to_hcd(ehci)->regs + 0x80); ++ switch ((portsc>>22)&3) { ++#else ++ switch ((portsc>>26)&3) { ++#endif + case 0: + return 0; + case 1: +--- a/drivers/usb/host/ehci-hub.c ++++ b/drivers/usb/host/ehci-hub.c +@@ -1075,6 +1075,11 @@ int ehci_hub_control( + /* see what we found out */ + temp = check_reset_complete (ehci, wIndex, status_reg, + ehci_readl(ehci, status_reg)); ++#ifdef CONFIG_ARCH_GEMINI ++ /* restart schedule */ ++ ehci->command |= CMD_RUN; ++ ehci_writel(ehci, ehci->command, &ehci->regs->command); ++#endif + } + + /* transfer dedicated ports to the companion hc */ +--- a/include/linux/usb/ehci_def.h ++++ b/include/linux/usb/ehci_def.h +@@ -110,8 +110,13 @@ struct ehci_regs { + u32 frame_list; /* points to periodic list */ + /* ASYNCLISTADDR: offset 0x18 */ + u32 async_next; /* address of next async queue head */ +- ++#ifndef CONFIG_ARCH_GEMINI + u32 reserved1[2]; ++#else ++ u32 reserved1; ++ /* PORTSC: offset 0x20 for Faraday OTG */ ++ u32 port_status[1]; ++#endif + + /* TXFILLTUNING: offset 0x24 */ + u32 txfill_tuning; /* TX FIFO Tuning register */ +@@ -123,8 +128,11 @@ struct ehci_regs { + u32 configured_flag; + #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ + ++#ifndef CONFIG_ARCH_GEMINI + /* PORTSC: offset 0x44 */ + u32 port_status[0]; /* up to N_PORTS */ ++#endif ++ + /* EHCI 1.1 addendum */ + #define PORTSC_SUSPEND_STS_ACK 0 + #define PORTSC_SUSPEND_STS_NYET 1 diff --git a/target/linux/gemini/patches-3.18/132-arm-gemini-register-usb.patch b/target/linux/gemini/patches-3.18/132-arm-gemini-register-usb.patch new file mode 100644 index 0000000..2a61d82 --- /dev/null +++ b/target/linux/gemini/patches-3.18/132-arm-gemini-register-usb.patch @@ -0,0 +1,65 @@ +--- a/arch/arm/mach-gemini/board-wbd111.c ++++ b/arch/arm/mach-gemini/board-wbd111.c +@@ -145,6 +145,7 @@ static void __init wbd111_init(void) + platform_register_watchdog(); + platform_device_register(&wbd111_phy_device); + platform_register_ethernet(&gmac_data); ++ platform_register_usb(0); + } + + MACHINE_START(WBD111, "Wiliboard WBD-111") +--- a/arch/arm/mach-gemini/board-wbd222.c ++++ b/arch/arm/mach-gemini/board-wbd222.c +@@ -147,6 +147,7 @@ static void __init wbd222_init(void) + platform_register_watchdog(); + platform_device_register(&wbd222_phy_device); + platform_register_ethernet(&gmac_data); ++ platform_register_usb(0); + } + + MACHINE_START(WBD222, "Wiliboard WBD-222") +--- a/arch/arm/mach-gemini/board-rut1xx.c ++++ b/arch/arm/mach-gemini/board-rut1xx.c +@@ -105,6 +105,7 @@ static void __init rut1xx_init(void) + platform_register_watchdog(); + platform_device_register(&rut1xx_phy_device); + platform_register_ethernet(&gmac_data); ++ platform_register_usb(0); + } + + MACHINE_START(RUT100, "Teltonika RUT100") +--- a/arch/arm/mach-gemini/board-nas4220b.c ++++ b/arch/arm/mach-gemini/board-nas4220b.c +@@ -134,10 +134,23 @@ static void __init ib4220b_gmac_init(voi + GLOBAL_ARBITRATION1_CTRL)); + } + ++static void __init usb_ib4220b_init(void) ++{ ++ unsigned int val; ++ ++ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ val &= ~(USB0_PLUG_MINIB | USB1_PLUG_MINIB); ++ val |= USB0_VBUS_ON | USB1_VBUS_ON; ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++} ++ + static void __init ib4220b_init(void) + { + gemini_gpio_init(); + ib4220b_gmac_init(); ++ usb_ib4220b_init(); + platform_register_uart(); + platform_register_pflash(SZ_16M, NULL, 0); + platform_device_register(&ib4220b_led_device); +@@ -146,6 +159,8 @@ static void __init ib4220b_init(void) + platform_register_watchdog(); + platform_device_register(&ib4220b_phy_device); + platform_register_ethernet(&ib4220b_gmac_data); ++ platform_register_usb(0); ++ platform_register_usb(1); + } + + MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") diff --git a/target/linux/gemini/patches-3.18/140-arm-gemini-add-pci-support.patch b/target/linux/gemini/patches-3.18/140-arm-gemini-add-pci-support.patch new file mode 100644 index 0000000..f662a29 --- /dev/null +++ b/target/linux/gemini/patches-3.18/140-arm-gemini-add-pci-support.patch @@ -0,0 +1,389 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -400,6 +400,7 @@ config ARCH_GEMINI + select CLKSRC_MMIO + select CPU_FA526 + select GENERIC_CLOCKEVENTS ++ select MIGHT_HAVE_PCI + help + Support for the Cortina Systems Gemini family SoCs + +--- a/arch/arm/mach-gemini/include/mach/hardware.h ++++ b/arch/arm/mach-gemini/include/mach/hardware.h +@@ -71,4 +71,9 @@ + */ + #define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000) + ++/* ++ * PCI subsystem macros ++ */ ++#define pcibios_assign_all_busses() 1 ++ + #endif +--- a/arch/arm/mach-gemini/include/mach/irqs.h ++++ b/arch/arm/mach-gemini/include/mach/irqs.h +@@ -43,11 +43,14 @@ + + #define NORMAL_IRQ_NUM 32 + +-#define GPIO_IRQ_BASE NORMAL_IRQ_NUM ++#define PCI_IRQ_BASE NORMAL_IRQ_NUM ++#define PCI_IRQ_NUM 4 ++ ++#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM) + #define GPIO_IRQ_NUM (3 * 32) + + #define ARCH_TIMER_IRQ IRQ_TIMER2 + +-#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM) ++#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM) + + #endif /* __MACH_IRQS_H__ */ +--- a/arch/arm/mach-gemini/Makefile ++++ b/arch/arm/mach-gemini/Makefile +@@ -6,6 +6,8 @@ + + obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o + ++obj-$(CONFIG_PCI) += pci.o ++ + # Board-specific support + obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o + obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o +--- a/arch/arm/mach-gemini/mm.c ++++ b/arch/arm/mach-gemini/mm.c +@@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[] + .length = SZ_512K, + .type = MT_DEVICE, + }, { ++ .virtual = (unsigned long)IO_ADDRESS(GEMINI_PCI_IO_BASE), ++ .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE), ++ .length = SZ_512K, ++ .type = MT_DEVICE, ++ }, { + .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE), + .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE), + .length = SZ_512K, +--- /dev/null ++++ b/arch/arm/mach-gemini/pci.c +@@ -0,0 +1,320 @@ ++/* ++ * Support for Gemini PCI Controller ++ * ++ * Copyright (C) 2009 Janos Laube ++ * Copyright (C) 2009 Paulius Zaleckas ++ * ++ * based on SL2312 PCI controller code ++ * Storlink (C) 2003 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#define GEMINI_PCI_IOSIZE_1M 0x0000 ++ ++#define GEMINI_PCI_PMC 0x40 ++#define GEMINI_PCI_PMCSR 0x44 ++#define GEMINI_PCI_CTRL1 0x48 ++#define GEMINI_PCI_CTRL2 0x4C ++#define GEMINI_PCI_MEM1_BASE_SIZE 0x50 ++#define GEMINI_PCI_MEM2_BASE_SIZE 0x54 ++#define GEMINI_PCI_MEM3_BASE_SIZE 0x58 ++ ++#define PCI_CTRL2_INTSTS_OFFSET 28 ++#define PCI_CTRL2_INTMASK_OFFSET 22 ++ ++#define GEMINI_PCI_DMA_MASK 0xFFF00000 ++#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000 ++#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000 ++#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000 ++#define GEMINI_PCI_DMA_MEM1_SIZE 7 ++#define GEMINI_PCI_DMA_MEM2_SIZE 6 ++#define GEMINI_PCI_DMA_MEM3_SIZE 6 ++ ++#define PCI_CONF_ENABLE (1 << 31) ++#define PCI_CONF_WHERE(r) ((r) & 0xFC) ++#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16) ++#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11) ++#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8) ++ ++#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE)) ++#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04) ++#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08) ++#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10) ++#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28) ++#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C) ++ ++ ++static DEFINE_SPINLOCK(gemini_pci_lock); ++ ++static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn, ++ int config, int size, u32* value) ++{ ++ unsigned long irq_flags; ++ ++ spin_lock_irqsave(&gemini_pci_lock, irq_flags); ++ ++ __raw_writel(PCI_CONF_BUS(bus->number) | ++ PCI_CONF_DEVICE(PCI_SLOT(fn)) | ++ PCI_CONF_FUNCTION(PCI_FUNC(fn)) | ++ PCI_CONF_WHERE(config) | ++ PCI_CONF_ENABLE, ++ PCI_CONFIG_REG); ++ ++ *value = __raw_readl(PCI_DATA_REG); ++ ++ if (size == 1) ++ *value = (*value >> (8 * (config & 3))) & 0xFF; ++ else if (size == 2) ++ *value = (*value >> (8 * (config & 3))) & 0xFFFF; ++ ++ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags); ++ ++ dev_dbg(&bus->dev, ++ "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", ++ PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn, ++ int config, int size, u32 value) ++{ ++ unsigned long irq_flags = 0; ++ int ret = PCIBIOS_SUCCESSFUL; ++ ++ dev_dbg(&bus->dev, ++ "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", ++ PCI_SLOT(fn), PCI_FUNC(fn), config, size, value); ++ ++ spin_lock_irqsave(&gemini_pci_lock, irq_flags); ++ ++ __raw_writel(PCI_CONF_BUS(bus->number) | ++ PCI_CONF_DEVICE(PCI_SLOT(fn)) | ++ PCI_CONF_FUNCTION(PCI_FUNC(fn)) | ++ PCI_CONF_WHERE(config) | ++ PCI_CONF_ENABLE, ++ PCI_CONFIG_REG); ++ ++ switch(size) { ++ case 4: ++ __raw_writel(value, PCI_DATA_REG); ++ break; ++ case 2: ++ __raw_writew(value, PCI_DATA_REG + (config & 3)); ++ break; ++ case 1: ++ __raw_writeb(value, PCI_DATA_REG + (config & 3)); ++ break; ++ default: ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ } ++ ++ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags); ++ ++ return ret; ++} ++ ++static struct pci_ops gemini_pci_ops = { ++ .read = gemini_pci_read_config, ++ .write = gemini_pci_write_config, ++}; ++ ++static struct resource gemini_pci_resource_io = { ++ .name = "PCI I/O Space", ++ .start = GEMINI_PCI_IO_BASE, ++ .end = GEMINI_PCI_IO_BASE + SZ_1M - 1, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource gemini_pci_resource_mem = { ++ .name = "PCI Memory Space", ++ .start = GEMINI_PCI_MEM_BASE, ++ .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static int __init gemini_pci_request_resources(struct pci_sys_data *sys) ++{ ++ if (request_resource(&ioport_resource, &gemini_pci_resource_io)) ++ goto bad_resources; ++ if (request_resource(&iomem_resource, &gemini_pci_resource_mem)) ++ goto bad_resources; ++ ++ pci_add_resource(&sys->resources, &gemini_pci_resource_io); ++ pci_add_resource(&sys->resources, &gemini_pci_resource_mem); ++ ++ return 0; ++ ++bad_resources: ++ pr_err("Gemini PCI: request_resource() failed. " ++ "Abort PCI bus enumeration.\n"); ++ return -1; ++} ++ ++static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys) ++{ ++ unsigned int cmd; ++ ++ pcibios_min_io = 0x100; ++ pcibios_min_mem = 0; ++ ++ if ((nr > 0) || gemini_pci_request_resources(sys)) ++ return 0; ++ ++ /* setup I/O space to 1MB size */ ++ __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG); ++ ++ /* setup hostbridge */ ++ cmd = __raw_readl(PCI_CTRL_REG); ++ cmd |= PCI_COMMAND_IO; ++ cmd |= PCI_COMMAND_MEMORY; ++ cmd |= PCI_COMMAND_MASTER; ++ __raw_writel(cmd, PCI_CTRL_REG); ++ ++ return 1; ++} ++ ++static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys) ++{ ++ unsigned int reg = 0; ++ struct pci_bus* bus = 0; ++ ++ bus = pci_scan_bus(nr, &gemini_pci_ops, sys); ++ if (bus) { ++ dev_dbg(&bus->dev, "setting up PCI DMA\n"); ++ reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK) ++ | (GEMINI_PCI_DMA_MEM1_SIZE << 16); ++ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg); ++ reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK) ++ | (GEMINI_PCI_DMA_MEM2_SIZE << 16); ++ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg); ++ reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK) ++ | (GEMINI_PCI_DMA_MEM3_SIZE << 16); ++ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg); ++ } ++ ++ return bus; ++} ++ ++/* Should work with all boards based on original Storlink EVB */ ++static int __init gemini_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot < 9 || slot > 12) ++ return -1; ++ ++ return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3); ++} ++ ++static struct hw_pci gemini_hw_pci __initdata = { ++ .nr_controllers = 1, ++ .setup = gemini_pci_setup, ++ .scan = gemini_pci_scan_bus, ++ .map_irq = gemini_pci_map_irq, ++}; ++ ++/* we need this for muxed PCI interrupts handling */ ++static struct pci_bus bogus_pci_bus; ++ ++static void gemini_pci_ack_irq(struct irq_data *d) ++{ ++ unsigned int irq = d->irq; ++ unsigned int reg; ++ ++ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®); ++ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET); ++ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET); ++ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg); ++} ++ ++static void gemini_pci_mask_irq(struct irq_data *d) ++{ ++ unsigned int irq = d->irq; ++ unsigned int reg; ++ ++ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®); ++ reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET) ++ | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET))); ++ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg); ++} ++ ++static void gemini_pci_unmask_irq(struct irq_data *d) ++{ ++ unsigned int irq = d->irq; ++ unsigned int reg; ++ ++ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®); ++ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET); ++ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET); ++ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg); ++} ++ ++static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ unsigned int pci_irq_no, irq_stat, reg, i; ++ ++ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®); ++ irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET; ++ ++ for (i = 0; i < 4; i++) { ++ ++ if ((irq_stat & (1 << i)) == 0) ++ continue; ++ ++ pci_irq_no = PCI_IRQ_BASE + i; ++ ++ BUG_ON(!(irq_desc[pci_irq_no].handle_irq)); ++ irq_desc[pci_irq_no].handle_irq(pci_irq_no, ++ &irq_desc[pci_irq_no]); ++ } ++} ++ ++static struct irq_chip gemini_pci_irq_chip = { ++ .name = "PCI", ++ .irq_ack = gemini_pci_ack_irq, ++ .irq_mask = gemini_pci_mask_irq, ++ .irq_unmask = gemini_pci_unmask_irq, ++}; ++ ++static int __init gemini_pci_init(void) ++{ ++ int i; ++ ++ for (i = 72; i <= 95; i++) ++ gpio_request(i, "PCI"); ++ ++ /* initialize our bogus bus */ ++ dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler"); ++ bogus_pci_bus.number = 0; ++ ++ /* mask and clear all interrupts */ ++ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2, ++ 0xF000); ++ ++ for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) { ++ irq_set_chip_and_handler(i, &gemini_pci_irq_chip, ++ handle_level_irq); ++ set_irq_flags(i, IRQF_VALID); ++ } ++ ++ irq_set_chained_handler(IRQ_PCI, gemini_pci_irq_handler); ++ ++ pci_common_init(&gemini_hw_pci); ++ ++ return 0; ++} ++ ++subsys_initcall(gemini_pci_init); diff --git a/target/linux/gemini/patches-3.18/150-gemini-pata.patch b/target/linux/gemini/patches-3.18/150-gemini-pata.patch new file mode 100644 index 0000000..62a71de --- /dev/null +++ b/target/linux/gemini/patches-3.18/150-gemini-pata.patch @@ -0,0 +1,192 @@ +--- a/arch/arm/mach-gemini/include/mach/global_reg.h ++++ b/arch/arm/mach-gemini/include/mach/global_reg.h +@@ -227,7 +227,13 @@ + #define USB0_PLUG_MINIB (1 << 29) + #define GMAC_GMII (1 << 28) + #define GMAC_1_ENABLE (1 << 27) +-/* TODO: define ATA/SATA bits */ ++/* 011 - ata0 <-> sata0, sata1; bring out ata1 ++ * 010 - ata1 <-> sata1, sata0; bring out ata0 ++ * 001 - ata0 <-> sata0, ata1 <-> sata1; bring out ata1 ++ * 000 - ata0 <-> sata0, ata1 <-> sata1; bring out ata0 */ ++#define IDE_IOMUX_MASK (7 << 24) ++#define IDE_IOMUX_SATA1_SATA0 (2 << 24) ++#define IDE_IOMUX_SATA0_SATA1 (3 << 24) + #define USB1_VBUS_ON (1 << 23) + #define USB0_VBUS_ON (1 << 22) + #define APB_CLKOUT_ENABLE (1 << 21) +--- a/arch/arm/mach-gemini/irq.c ++++ b/arch/arm/mach-gemini/irq.c +@@ -89,6 +89,9 @@ void __init gemini_init_irq(void) + irq_set_handler(i, handle_edge_irq); + mode |= 1 << i; + level |= 1 << i; ++ } else if (i >= IRQ_IDE0 && i <= IRQ_IDE1) { ++ irq_set_handler(i, handle_edge_irq); ++ mode |= 1 << i; + } else { + irq_set_handler(i, handle_level_irq); + } +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -29,6 +29,7 @@ extern int platform_register_pflash(unsi + extern int platform_register_watchdog(void); + extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata); + extern int platform_register_usb(unsigned int id); ++extern int platform_register_pata(unsigned int id); + + extern void gemini_restart(enum reboot_mode mode, const char *cmd); + +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -249,3 +249,67 @@ int __init platform_register_usb(unsigne + return platform_device_register(&usb_device[id]); + } + ++static u64 pata_gemini_dmamask0 = 0xffffffffUL; ++static u64 pata_gemini_dmamask1 = 0xffffffffUL; ++ ++static struct resource pata_gemini_resources0[] = ++{ ++ [0] = { ++ .start = GEMINI_IDE0_BASE, ++ .end = GEMINI_IDE0_BASE + 0x40, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_IDE0, ++ .end = IRQ_IDE0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource pata_gemini_resources1[] = ++{ ++ [0] = { ++ .start = GEMINI_IDE1_BASE, ++ .end = GEMINI_IDE1_BASE + 0x40, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_IDE1, ++ .end = IRQ_IDE1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device pata_gemini_devices[] = ++{ ++ { ++ .name = "pata-gemini", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &pata_gemini_dmamask0, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(pata_gemini_resources0), ++ .resource = pata_gemini_resources0, ++ }, ++ { ++ .name = "pata-gemini", ++ .id = 1, ++ .dev = ++ { ++ .dma_mask = &pata_gemini_dmamask1, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(pata_gemini_resources1), ++ .resource = pata_gemini_resources1, ++ }, ++}; ++ ++int __init platform_register_pata(unsigned int id) ++{ ++ if (id > 1) ++ return -EINVAL; ++ ++ return platform_device_register(&pata_gemini_devices[id]); ++} +--- a/arch/arm/mach-gemini/mm.c ++++ b/arch/arm/mach-gemini/mm.c +@@ -24,6 +24,11 @@ static struct map_desc gemini_io_desc[] + .length = SZ_512K, + .type = MT_DEVICE, + }, { ++ .virtual = (unsigned long)IO_ADDRESS(GEMINI_SATA_BASE), ++ .pfn = __phys_to_pfn(GEMINI_SATA_BASE), ++ .length = SZ_512K, ++ .type = MT_DEVICE, ++ }, { + .virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE), + .pfn = __phys_to_pfn(GEMINI_UART_BASE), + .length = SZ_512K, +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -536,6 +536,16 @@ config PATA_EP93XX + + If unsure, say N. + ++config PATA_GEMINI ++ tristate "Gemini PATA support (Experimental)" ++ depends on ARCH_GEMINI ++ help ++ This option enables support for the Gemini PATA-Controller. ++ Note that the Gemini SoC has no native SATA-Controller but an ++ onboard PATA-SATA bridge. ++ ++ If unsure, say N. ++ + config PATA_HPT366 + tristate "HPT 366/368 PATA support" + depends on PCI +--- a/drivers/ata/Makefile ++++ b/drivers/ata/Makefile +@@ -53,6 +53,7 @@ obj-$(CONFIG_PATA_CS5536) += pata_cs5536 + obj-$(CONFIG_PATA_CYPRESS) += pata_cypress.o + obj-$(CONFIG_PATA_EFAR) += pata_efar.o + obj-$(CONFIG_PATA_EP93XX) += pata_ep93xx.o ++obj-$(CONFIG_PATA_GEMINI) += pata_gemini.o + obj-$(CONFIG_PATA_HPT366) += pata_hpt366.o + obj-$(CONFIG_PATA_HPT37X) += pata_hpt37x.o + obj-$(CONFIG_PATA_HPT3X2N) += pata_hpt3x2n.o +--- a/arch/arm/mach-gemini/board-nas4220b.c ++++ b/arch/arm/mach-gemini/board-nas4220b.c +@@ -146,11 +146,28 @@ static void __init usb_ib4220b_init(void + GLOBAL_MISC_CTRL)); + } + ++static void __init sata_ib4220b_init(void) ++{ ++ unsigned val; ++ ++ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ val &= ~(IDE_IOMUX_MASK | PFLASH_PADS_DISABLE); ++ val |= IDE_PADS_ENABLE; ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ ++ /* enabling ports for presence detection, master only */ ++ writel(0x00000001, (void __iomem*)(IO_ADDRESS(GEMINI_SATA_BASE) + 0x18)); ++ writel(0x00000001, (void __iomem*)(IO_ADDRESS(GEMINI_SATA_BASE) + 0x1c)); ++} ++ + static void __init ib4220b_init(void) + { + gemini_gpio_init(); + ib4220b_gmac_init(); + usb_ib4220b_init(); ++ sata_ib4220b_init(); + platform_register_uart(); + platform_register_pflash(SZ_16M, NULL, 0); + platform_device_register(&ib4220b_led_device); +@@ -161,6 +178,8 @@ static void __init ib4220b_init(void) + platform_register_ethernet(&ib4220b_gmac_data); + platform_register_usb(0); + platform_register_usb(1); ++ platform_register_pata(0); ++ platform_register_pata(1); + } + + MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") diff --git a/target/linux/gemini/patches-3.18/160-gemini-timers.patch b/target/linux/gemini/patches-3.18/160-gemini-timers.patch new file mode 100644 index 0000000..4b0edb4 --- /dev/null +++ b/target/linux/gemini/patches-3.18/160-gemini-timers.patch @@ -0,0 +1,243 @@ +--- a/arch/arm/mach-gemini/time.c ++++ b/arch/arm/mach-gemini/time.c +@@ -15,15 +15,18 @@ + #include + #include + #include ++#include + + /* + * Register definitions for the timers + */ +-#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00) +-#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04) +-#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08) +-#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C) +-#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30) ++#define TIMER_COUNT(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x00) ++#define TIMER_LOAD(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x04) ++#define TIMER_MATCH1(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x08) ++#define TIMER_MATCH2(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x0C) ++#define TIMER_CR(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x30) ++#define TIMER_INTR_STATE(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x34) ++#define TIMER_INTR_MASK(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x38) + + #define TIMER_1_CR_ENABLE (1 << 0) + #define TIMER_1_CR_CLOCK (1 << 1) +@@ -34,27 +37,38 @@ + #define TIMER_3_CR_ENABLE (1 << 6) + #define TIMER_3_CR_CLOCK (1 << 7) + #define TIMER_3_CR_INT (1 << 8) ++#define TIMER_1_CR_UPDOWN (1 << 9) ++#define TIMER_2_CR_UPDOWN (1 << 10) ++#define TIMER_3_CR_UPDOWN (1 << 11) ++ ++#define TIMER_1_INT_MATCH1 (1 << 0) ++#define TIMER_1_INT_MATCH2 (1 << 1) ++#define TIMER_1_INT_OVERFLOW (1 << 2) ++#define TIMER_2_INT_MATCH1 (1 << 3) ++#define TIMER_2_INT_MATCH2 (1 << 4) ++#define TIMER_2_INT_OVERFLOW (1 << 5) ++#define TIMER_3_INT_MATCH1 (1 << 6) ++#define TIMER_3_INT_MATCH2 (1 << 7) ++#define TIMER_3_INT_OVERFLOW (1 << 8) ++#define TIMER_INT_ALL_MASK 0x1ff + + static unsigned int tick_rate; + ++static u64 notrace gemini_read_sched_clock(void) ++{ ++ return readl(TIMER_COUNT(GEMINI_TIMER3_BASE)); ++} ++ + static int gemini_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) + { + u32 cr; + +- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- +- /* This may be overdoing it, feel free to test without this */ +- cr &= ~TIMER_2_CR_ENABLE; +- cr &= ~TIMER_2_CR_INT; +- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- +- /* Set next event */ +- writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); +- writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); +- cr |= TIMER_2_CR_ENABLE; +- cr |= TIMER_2_CR_INT; +- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); ++ /* Setup the match register */ ++ cr = readl(TIMER_COUNT(GEMINI_TIMER1_BASE)); ++ writel(cr + cycles, TIMER_MATCH1(GEMINI_TIMER1_BASE)); ++ if (readl(TIMER_COUNT(GEMINI_TIMER1_BASE)) - cr > cycles) ++ return -ETIME; + + return 0; + } +@@ -66,48 +80,68 @@ static void gemini_timer_set_mode(enum c + u32 cr; + + switch (mode) { +- case CLOCK_EVT_MODE_PERIODIC: +- /* Start the timer */ +- writel(period, +- TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); +- writel(period, +- TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); +- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- cr |= TIMER_2_CR_ENABLE; +- cr |= TIMER_2_CR_INT; +- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); ++ case CLOCK_EVT_MODE_PERIODIC: ++ /* Stop timer and interrupt. */ ++ cr = readl(TIMER_CR(GEMINI_TIMER_BASE)); ++ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); ++ writel(cr, TIMER_CR(GEMINI_TIMER_BASE)); ++ ++ /* Setup timer to fire at 1/HZ intervals. */ ++ cr = 0xffffffff - (period - 1); ++ writel(cr, TIMER_COUNT(GEMINI_TIMER1_BASE)); ++ writel(cr, TIMER_LOAD(GEMINI_TIMER1_BASE)); ++ ++ /* enable interrupt on overflaw */ ++ cr = readl(TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); ++ cr |= TIMER_1_INT_OVERFLOW; ++ writel(cr, TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ ++ /* start the timer */ ++ cr = readl(TIMER_CR(GEMINI_TIMER_BASE)); ++ cr |= TIMER_1_CR_ENABLE | TIMER_1_CR_INT; ++ writel(cr, TIMER_CR(GEMINI_TIMER_BASE)); + break; ++ + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: +- case CLOCK_EVT_MODE_SHUTDOWN: ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ /* Stop timer and interrupt. */ ++ cr = readl(TIMER_CR(GEMINI_TIMER_BASE)); ++ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); ++ writel(cr, TIMER_CR(GEMINI_TIMER_BASE)); ++ ++ /* Setup counter start from 0 */ ++ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE)); ++ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE)); ++ ++ /* enable interrupt */ ++ cr = readl(TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); ++ cr |= TIMER_1_INT_MATCH1; ++ writel(cr, TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ ++ /* start the timer */ ++ cr = readl(TIMER_CR(GEMINI_TIMER_BASE)); ++ cr |= TIMER_1_CR_ENABLE; ++ writel(cr, TIMER_CR(GEMINI_TIMER_BASE)); ++ break; ++ + case CLOCK_EVT_MODE_RESUME: +- /* +- * Disable also for oneshot: the set_next() call will +- * arm the timer instead. +- */ +- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- cr &= ~TIMER_2_CR_ENABLE; +- cr &= ~TIMER_2_CR_INT; +- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + break; +- default: +- break; + } + } + +-/* Use TIMER2 as clock event */ + static struct clock_event_device gemini_clockevent = { +- .name = "TIMER2", +- .rating = 300, /* Reasonably fast and accurate clock event */ +- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, +- .set_next_event = gemini_timer_set_next_event, +- .set_mode = gemini_timer_set_mode, ++ .name = "gemini_timer_1", ++ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, ++ .shift = 32, ++ .rating = 300, ++ .set_next_event = gemini_timer_set_next_event, ++ .set_mode = gemini_timer_set_mode, + }; + +-/* +- * IRQ handler for the timer +- */ +-static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id) ++static irqreturn_t gemini_timer_intr(int irq, void *dev_id) + { + struct clock_event_device *evt = &gemini_clockevent; + +@@ -116,14 +150,11 @@ static irqreturn_t gemini_timer_interrup + } + + static struct irqaction gemini_timer_irq = { +- .name = "Gemini Timer Tick", +- .flags = IRQF_TIMER, +- .handler = gemini_timer_interrupt, ++ .name = "gemini timer 1", ++ .flags = IRQF_DISABLED | IRQF_TIMER, ++ .handler = gemini_timer_intr, + }; + +-/* +- * Set up timer interrupt, and return the current time in seconds. +- */ + void __init gemini_timer_init(void) + { + u32 reg_v; +@@ -151,20 +182,35 @@ void __init gemini_timer_init(void) + } + + /* +- * Make irqs happen for the system timer ++ * Reset the interrupt mask and status + */ +- setup_irq(IRQ_TIMER2, &gemini_timer_irq); ++ writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ writel(0, TIMER_INTR_STATE(GEMINI_TIMER_BASE)); ++ writel(TIMER_1_CR_UPDOWN | TIMER_3_CR_ENABLE | TIMER_3_CR_UPDOWN, ++ TIMER_CR(GEMINI_TIMER_BASE)); + +- /* Enable and use TIMER1 as clock source */ +- writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); +- writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); +- writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)), +- "TIMER1", tick_rate, 300, 32, +- clocksource_mmio_readl_up)) +- pr_err("timer: failed to initialize gemini clock source\n"); ++ /* ++ * Setup free-running clocksource timer (interrupts ++ * disabled.) ++ */ ++ writel(0, TIMER_COUNT(GEMINI_TIMER3_BASE)); ++ writel(0, TIMER_LOAD(GEMINI_TIMER3_BASE)); ++ writel(0, TIMER_MATCH1(GEMINI_TIMER3_BASE)); ++ writel(0, TIMER_MATCH2(GEMINI_TIMER3_BASE)); ++ clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER3_BASE), ++ "gemini_clocksource", tick_rate, ++ 300, 32, clocksource_mmio_readl_up); ++ sched_clock_register(gemini_read_sched_clock, 32, tick_rate); + +- /* Configure and register the clockevent */ ++ /* ++ * Setup clockevent timer (interrupt-driven.) ++ */ ++ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE)); ++ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE)); ++ writel(0, TIMER_MATCH1(GEMINI_TIMER1_BASE)); ++ writel(0, TIMER_MATCH2(GEMINI_TIMER1_BASE)); ++ setup_irq(IRQ_TIMER1, &gemini_timer_irq); ++ gemini_clockevent.cpumask = cpumask_of(0); + clockevents_config_and_register(&gemini_clockevent, tick_rate, + 1, 0xffffffff); + } diff --git a/target/linux/gemini/patches-4.1/002-gemini-rtc.patch b/target/linux/gemini/patches-4.1/002-gemini-rtc.patch new file mode 100644 index 0000000..c795569 --- /dev/null +++ b/target/linux/gemini/patches-4.1/002-gemini-rtc.patch @@ -0,0 +1,51 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1300,6 +1300,15 @@ config RTC_DRV_BFIN + This driver can also be built as a module. If so, the module + will be called rtc-bfin. + ++config RTC_DRV_GEMINI ++ tristate "Gemini SoC RTC" ++ help ++ If you say Y here you will get support for the ++ RTC found on Gemini SoC's. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-gemini. ++ + config RTC_DRV_RS5C313 + tristate "Ricoh RS5C313" + depends on SH_LANDISK +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -65,6 +65,7 @@ obj-$(CONFIG_RTC_DRV_EFI) += rtc-efi.o + obj-$(CONFIG_RTC_DRV_EM3027) += rtc-em3027.o + obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o + obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o ++obj-$(CONFIG_RTC_DRV_GEMINI) += rtc-gemini.o + obj-$(CONFIG_RTC_DRV_GENERIC) += rtc-generic.o + obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o + obj-$(CONFIG_RTC_DRV_HYM8563) += rtc-hym8563.o +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -20,9 +20,9 @@ extern void gemini_map_io(void); + extern void gemini_init_irq(void); + extern void gemini_timer_init(void); + extern void gemini_gpio_init(void); +-extern void platform_register_rtc(void); + + /* Common platform devices registration functions */ ++extern int platform_register_rtc(void); + extern int platform_register_uart(void); + extern int platform_register_pflash(unsigned int size, + struct mtd_partition *parts, +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include "common.h" + + static struct plat_serial8250_port serial_platform_data[] = { + { diff --git a/target/linux/gemini/patches-4.1/050-gpio-to-irq.patch b/target/linux/gemini/patches-4.1/050-gpio-to-irq.patch new file mode 100644 index 0000000..7572849 --- /dev/null +++ b/target/linux/gemini/patches-4.1/050-gpio-to-irq.patch @@ -0,0 +1,21 @@ +--- a/arch/arm/mach-gemini/gpio.c ++++ b/arch/arm/mach-gemini/gpio.c +@@ -196,12 +196,18 @@ static int gemini_gpio_direction_output( + return 0; + } + ++static int gemini_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) ++{ ++ return gpio + GPIO_IRQ_BASE; ++} ++ + static struct gpio_chip gemini_gpio_chip = { + .label = "Gemini", + .direction_input = gemini_gpio_direction_input, + .get = gemini_gpio_get, + .direction_output = gemini_gpio_direction_output, + .set = gemini_gpio_set, ++ .to_irq = gemini_gpio_to_irq, + .base = 0, + .ngpio = GPIO_PORT_NUM * 32, + }; diff --git a/target/linux/gemini/patches-4.1/060-cache-fa.diff b/target/linux/gemini/patches-4.1/060-cache-fa.diff new file mode 100644 index 0000000..fc74c0a --- /dev/null +++ b/target/linux/gemini/patches-4.1/060-cache-fa.diff @@ -0,0 +1,41 @@ +--- a/arch/arm/mm/cache-fa.S ++++ b/arch/arm/mm/cache-fa.S +@@ -24,7 +24,8 @@ + /* + * The size of one data cache line. + */ +-#define CACHE_DLINESIZE 16 ++#define CACHE_DLINESIZE 16 ++#define CACHE_DLINESHIFT 4 + + /* + * The total size of the data cache. +@@ -169,7 +170,17 @@ ENTRY(fa_flush_kern_dcache_area) + * - start - virtual start address + * - end - virtual end address + */ ++__flush_whole_dcache: ++ mcr p15, 0, r0, c7, c14, 0 @ clean/invalidate D cache ++ mov r0, #0 ++ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer ++ mov pc, lr ++ + fa_dma_inv_range: ++ sub r3, r1, r0 @ calculate total size ++ cmp r3, #CACHE_DLIMIT @ total size >= limit? ++ bhs __flush_whole_dcache @ flush whole D cache ++ + tst r0, #CACHE_DLINESIZE - 1 + bic r0, r0, #CACHE_DLINESIZE - 1 + mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry +@@ -193,6 +204,10 @@ fa_dma_inv_range: + * - end - virtual end address + */ + fa_dma_clean_range: ++ sub r3, r1, r0 @ calculate total size ++ cmp r3, #CACHE_DLIMIT @ total size >= limit? ++ bhs __flush_whole_dcache @ flush whole D cache ++ + bic r0, r0, #CACHE_DLINESIZE - 1 + 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHE_DLINESIZE diff --git a/target/linux/gemini/patches-4.1/110-watchdog-add-gemini_wdt-driver.patch b/target/linux/gemini/patches-4.1/110-watchdog-add-gemini_wdt-driver.patch new file mode 100644 index 0000000..3b767ae --- /dev/null +++ b/target/linux/gemini/patches-4.1/110-watchdog-add-gemini_wdt-driver.patch @@ -0,0 +1,410 @@ +--- /dev/null ++++ b/drivers/watchdog/gemini_wdt.c +@@ -0,0 +1,378 @@ ++/* ++ * Watchdog driver for Cortina Systems Gemini SoC ++ * ++ * Copyright (C) 2009 Paulius Zaleckas ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define GEMINI_WDCOUNTER 0x0 ++#define GEMINI_WDLOAD 0x4 ++#define GEMINI_WDRESTART 0x8 ++ ++#define WDRESTART_MAGIC 0x5AB9 ++ ++#define GEMINI_WDCR 0xC ++ ++#define WDCR_CLOCK_5MHZ (1 << 4) ++#define WDCR_SYS_RST (1 << 1) ++#define WDCR_ENABLE (1 << 0) ++ ++#define WDT_CLOCK 5000000 /* 5 MHz */ ++#define WDT_DEFAULT_TIMEOUT 13 ++#define WDT_MAX_TIMEOUT (0xFFFFFFFF / WDT_CLOCK) ++ ++/* status bits */ ++#define WDT_ACTIVE 0 ++#define WDT_OK_TO_CLOSE 1 ++ ++static unsigned int timeout = WDT_DEFAULT_TIMEOUT; ++static int nowayout = WATCHDOG_NOWAYOUT; ++ ++static DEFINE_SPINLOCK(gemini_wdt_lock); ++ ++static struct platform_device *gemini_wdt_dev; ++ ++struct gemini_wdt_struct { ++ struct resource *res; ++ struct device *dev; ++ void __iomem *base; ++ unsigned long status; ++}; ++ ++static struct watchdog_info gemini_wdt_info = { ++ .identity = "Gemini watchdog", ++ .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | ++ WDIOF_SETTIMEOUT, ++}; ++ ++/* Disable the watchdog. */ ++static void gemini_wdt_stop(struct gemini_wdt_struct *gemini_wdt) ++{ ++ spin_lock(&gemini_wdt_lock); ++ ++ __raw_writel(0, gemini_wdt->base + GEMINI_WDCR); ++ ++ clear_bit(WDT_ACTIVE, &gemini_wdt->status); ++ ++ spin_unlock(&gemini_wdt_lock); ++} ++ ++/* Service the watchdog */ ++static void gemini_wdt_service(struct gemini_wdt_struct *gemini_wdt) ++{ ++ __raw_writel(WDRESTART_MAGIC, gemini_wdt->base + GEMINI_WDRESTART); ++} ++ ++/* Enable and reset the watchdog. */ ++static void gemini_wdt_start(struct gemini_wdt_struct *gemini_wdt) ++{ ++ spin_lock(&gemini_wdt_lock); ++ ++ __raw_writel(timeout * WDT_CLOCK, gemini_wdt->base + GEMINI_WDLOAD); ++ ++ gemini_wdt_service(gemini_wdt); ++ ++ /* set clock before enabling */ ++ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST, ++ gemini_wdt->base + GEMINI_WDCR); ++ ++ __raw_writel(WDCR_CLOCK_5MHZ | WDCR_SYS_RST | WDCR_ENABLE, ++ gemini_wdt->base + GEMINI_WDCR); ++ ++ set_bit(WDT_ACTIVE, &gemini_wdt->status); ++ ++ spin_unlock(&gemini_wdt_lock); ++} ++ ++/* Watchdog device is opened, and watchdog starts running. */ ++static int gemini_wdt_open(struct inode *inode, struct file *file) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(gemini_wdt_dev); ++ ++ if (test_bit(WDT_ACTIVE, &gemini_wdt->status)) ++ return -EBUSY; ++ ++ file->private_data = gemini_wdt; ++ ++ gemini_wdt_start(gemini_wdt); ++ ++ return nonseekable_open(inode, file); ++} ++ ++/* Close the watchdog device. */ ++static int gemini_wdt_close(struct inode *inode, struct file *file) ++{ ++ struct gemini_wdt_struct *gemini_wdt = file->private_data; ++ ++ /* Disable the watchdog if possible */ ++ if (test_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status)) ++ gemini_wdt_stop(gemini_wdt); ++ else ++ dev_warn(gemini_wdt->dev, "Device closed unexpectedly - timer will not stop\n"); ++ ++ return 0; ++} ++ ++/* Handle commands from user-space. */ ++static long gemini_wdt_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ struct gemini_wdt_struct *gemini_wdt = file->private_data; ++ ++ int value; ++ ++ switch (cmd) { ++ case WDIOC_KEEPALIVE: ++ gemini_wdt_service(gemini_wdt); ++ return 0; ++ ++ case WDIOC_GETSUPPORT: ++ return copy_to_user((struct watchdog_info *)arg, &gemini_wdt_info, ++ sizeof(gemini_wdt_info)) ? -EFAULT : 0; ++ ++ case WDIOC_SETTIMEOUT: ++ if (get_user(value, (int *)arg)) ++ return -EFAULT; ++ ++ if ((value < 1) || (value > WDT_MAX_TIMEOUT)) ++ return -EINVAL; ++ ++ timeout = value; ++ ++ /* restart wdt to use new timeout */ ++ gemini_wdt_stop(gemini_wdt); ++ gemini_wdt_start(gemini_wdt); ++ ++ /* Fall through */ ++ case WDIOC_GETTIMEOUT: ++ return put_user(timeout, (int *)arg); ++ ++ case WDIOC_GETTIMELEFT: ++ value = __raw_readl(gemini_wdt->base + GEMINI_WDCOUNTER); ++ return put_user(value / WDT_CLOCK, (int *)arg); ++ ++ default: ++ return -ENOTTY; ++ } ++} ++ ++/* Refresh the watchdog whenever device is written to. */ ++static ssize_t gemini_wdt_write(struct file *file, const char *data, ++ size_t len, loff_t *ppos) ++{ ++ struct gemini_wdt_struct *gemini_wdt = file->private_data; ++ ++ if (len) { ++ if (!nowayout) { ++ size_t i; ++ ++ clear_bit(WDT_OK_TO_CLOSE, &gemini_wdt->status); ++ for (i = 0; i != len; i++) { ++ char c; ++ ++ if (get_user(c, data + i)) ++ return -EFAULT; ++ if (c == 'V') ++ set_bit(WDT_OK_TO_CLOSE, ++ &gemini_wdt->status); ++ } ++ } ++ gemini_wdt_service(gemini_wdt); ++ } ++ ++ return len; ++} ++ ++static const struct file_operations gemini_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .unlocked_ioctl = gemini_wdt_ioctl, ++ .open = gemini_wdt_open, ++ .release = gemini_wdt_close, ++ .write = gemini_wdt_write, ++}; ++ ++static struct miscdevice gemini_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &gemini_wdt_fops, ++}; ++ ++static void gemini_wdt_shutdown(struct platform_device *pdev) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev); ++ ++ gemini_wdt_stop(gemini_wdt); ++} ++ ++static int gemini_wdt_probe(struct platform_device *pdev) ++{ ++ int ret; ++ int res_size; ++ struct resource *res; ++ void __iomem *base; ++ struct gemini_wdt_struct *gemini_wdt; ++ unsigned int reg; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "can't get device resources\n"); ++ return -ENODEV; ++ } ++ ++ res_size = resource_size(res); ++ if (!request_mem_region(res->start, res_size, res->name)) { ++ dev_err(&pdev->dev, "can't allocate %d bytes at %d address\n", ++ res_size, res->start); ++ return -ENOMEM; ++ } ++ ++ base = ioremap(res->start, res_size); ++ if (!base) { ++ dev_err(&pdev->dev, "ioremap failed\n"); ++ ret = -EIO; ++ goto fail0; ++ } ++ ++ gemini_wdt = kzalloc(sizeof(struct gemini_wdt_struct), GFP_KERNEL); ++ if (!gemini_wdt) { ++ dev_err(&pdev->dev, "can't allocate interface\n"); ++ ret = -ENOMEM; ++ goto fail1; ++ } ++ ++ /* Setup gemini_wdt driver structure */ ++ gemini_wdt->base = base; ++ gemini_wdt->res = res; ++ ++ /* Set up platform driver data */ ++ platform_set_drvdata(pdev, gemini_wdt); ++ gemini_wdt_dev = pdev; ++ ++ if (gemini_wdt_miscdev.parent) { ++ ret = -EBUSY; ++ goto fail2; ++ } ++ ++ gemini_wdt_miscdev.parent = &pdev->dev; ++ ++ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR); ++ if (reg & WDCR_ENABLE) { ++ /* Watchdog was enabled by the bootloader, disable it. */ ++ reg &= ~(WDCR_ENABLE); ++ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR); ++ } ++ ++ ret = misc_register(&gemini_wdt_miscdev); ++ if (ret) ++ goto fail2; ++ ++ return 0; ++ ++fail2: ++ platform_set_drvdata(pdev, NULL); ++ kfree(gemini_wdt); ++fail1: ++ iounmap(base); ++fail0: ++ release_mem_region(res->start, res_size); ++ ++ return ret; ++} ++ ++static int gemini_wdt_remove(struct platform_device *pdev) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev); ++ ++ platform_set_drvdata(pdev, NULL); ++ misc_deregister(&gemini_wdt_miscdev); ++ gemini_wdt_dev = NULL; ++ iounmap(gemini_wdt->base); ++ release_mem_region(gemini_wdt->res->start, resource_size(gemini_wdt->res)); ++ ++ kfree(gemini_wdt); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int gemini_wdt_suspend(struct platform_device *pdev, pm_message_t message) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev); ++ unsigned int reg; ++ ++ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR); ++ reg &= ~(WDCR_WDENABLE); ++ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR); ++ ++ return 0; ++} ++ ++static int gemini_wdt_resume(struct platform_device *pdev) ++{ ++ struct gemini_wdt_struct *gemini_wdt = platform_get_drvdata(pdev); ++ unsigned int reg; ++ ++ if (gemini_wdt->status) { ++ reg = __raw_readw(gemini_wdt->base + GEMINI_WDCR); ++ reg |= WDCR_WDENABLE; ++ __raw_writel(reg, gemini_wdt->base + GEMINI_WDCR); ++ } ++ ++ return 0; ++} ++#else ++#define gemini_wdt_suspend NULL ++#define gemini_wdt_resume NULL ++#endif ++ ++static struct platform_driver gemini_wdt_driver = { ++ .probe = gemini_wdt_probe, ++ .remove = gemini_wdt_remove, ++ .shutdown = gemini_wdt_shutdown, ++ .suspend = gemini_wdt_suspend, ++ .resume = gemini_wdt_resume, ++ .driver = { ++ .name = "gemini-wdt", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init gemini_wdt_init(void) ++{ ++ return platform_driver_probe(&gemini_wdt_driver, gemini_wdt_probe); ++} ++ ++static void __exit gemini_wdt_exit(void) ++{ ++ platform_driver_unregister(&gemini_wdt_driver); ++} ++ ++module_init(gemini_wdt_init); ++module_exit(gemini_wdt_exit); ++ ++module_param(timeout, uint, 0); ++MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds"); ++ ++module_param(nowayout, int, 0); ++MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); ++ ++MODULE_AUTHOR("Paulius Zaleckas"); ++MODULE_DESCRIPTION("Watchdog driver for Gemini"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:gemini-wdt"); +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -198,6 +198,16 @@ config 977_WATCHDOG + + Not sure? It's safe to say N. + ++config GEMINI_WATCHDOG ++ tristate "Gemini watchdog" ++ depends on ARCH_GEMINI ++ help ++ Say Y here if to include support for the watchdog timer ++ embedded in the Cortina Systems Gemini family of devices. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called gemini_wdt. ++ + config IXP4XX_WATCHDOG + tristate "IXP4xx Watchdog" + depends on ARCH_IXP4XX +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -37,6 +37,7 @@ obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt. + obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o + obj-$(CONFIG_21285_WATCHDOG) += wdt285.o + obj-$(CONFIG_977_WATCHDOG) += wdt977.o ++obj-$(CONFIG_GEMINI_WATCHDOG) += gemini_wdt.o + obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o + obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o + obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o diff --git a/target/linux/gemini/patches-4.1/111-arm-gemini-add-watchdog-device.patch b/target/linux/gemini/patches-4.1/111-arm-gemini-add-watchdog-device.patch new file mode 100644 index 0000000..a0435d3 --- /dev/null +++ b/target/linux/gemini/patches-4.1/111-arm-gemini-add-watchdog-device.patch @@ -0,0 +1,33 @@ +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -117,3 +117,20 @@ int __init platform_register_rtc(void) + return platform_device_register(&gemini_rtc_device); + } + ++static struct resource wdt_resource = { ++ .start = GEMINI_WAQTCHDOG_BASE, ++ .end = GEMINI_WAQTCHDOG_BASE + 0x18, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device wdt_device = { ++ .name = "gemini-wdt", ++ .id = 0, ++ .resource = &wdt_resource, ++ .num_resources = 1, ++}; ++ ++int __init platform_register_watchdog(void) ++{ ++ return platform_device_register(&wdt_device); ++} +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -27,6 +27,7 @@ extern int platform_register_uart(void); + extern int platform_register_pflash(unsigned int size, + struct mtd_partition *parts, + unsigned int nr_parts); ++extern int platform_register_watchdog(void); + + extern void gemini_restart(enum reboot_mode mode, const char *cmd); + diff --git a/target/linux/gemini/patches-4.1/112-arm-gemini-register-watchdog-devices.patch b/target/linux/gemini/patches-4.1/112-arm-gemini-register-watchdog-devices.patch new file mode 100644 index 0000000..74564b1 --- /dev/null +++ b/target/linux/gemini/patches-4.1/112-arm-gemini-register-watchdog-devices.patch @@ -0,0 +1,40 @@ +--- a/arch/arm/mach-gemini/board-nas4220b.c ++++ b/arch/arm/mach-gemini/board-nas4220b.c +@@ -95,6 +95,7 @@ static void __init ib4220b_init(void) + platform_device_register(&ib4220b_led_device); + platform_device_register(&ib4220b_key_device); + platform_register_rtc(); ++ platform_register_watchdog(); + } + + MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") +--- a/arch/arm/mach-gemini/board-wbd111.c ++++ b/arch/arm/mach-gemini/board-wbd111.c +@@ -122,6 +122,7 @@ static void __init wbd111_init(void) + platform_device_register(&wbd111_leds_device); + platform_device_register(&wbd111_keys_device); + platform_register_rtc(); ++ platform_register_watchdog(); + } + + MACHINE_START(WBD111, "Wiliboard WBD-111") +--- a/arch/arm/mach-gemini/board-wbd222.c ++++ b/arch/arm/mach-gemini/board-wbd222.c +@@ -122,6 +122,7 @@ static void __init wbd222_init(void) + platform_device_register(&wbd222_leds_device); + platform_device_register(&wbd222_keys_device); + platform_register_rtc(); ++ platform_register_watchdog(); + } + + MACHINE_START(WBD222, "Wiliboard WBD-222") +--- a/arch/arm/mach-gemini/board-rut1xx.c ++++ b/arch/arm/mach-gemini/board-rut1xx.c +@@ -80,6 +80,7 @@ static void __init rut1xx_init(void) + platform_device_register(&rut1xx_leds); + platform_device_register(&rut1xx_keys_device); + platform_register_rtc(); ++ platform_register_watchdog(); + } + + MACHINE_START(RUT100, "Teltonika RUT100") diff --git a/target/linux/gemini/patches-4.1/120-net-add-gemini-gmac-driver.patch b/target/linux/gemini/patches-4.1/120-net-add-gemini-gmac-driver.patch new file mode 100644 index 0000000..fd5045c --- /dev/null +++ b/target/linux/gemini/patches-4.1/120-net-add-gemini-gmac-driver.patch @@ -0,0 +1,3953 @@ +--- /dev/null ++++ b/arch/arm/mach-gemini/include/mach/gmac.h +@@ -0,0 +1,21 @@ ++/* ++ * Gemini GMAC specific defines ++ * ++ * Copyright (C) 2008, Paulius Zaleckas ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#ifndef __NET_GEMINI_PLATFORM_H__ ++#define __NET_GEMINI_PLATFORM_H__ ++ ++#include ++ ++struct gemini_gmac_platform_data { ++ char *bus_id[2]; /* NULL means that this port is not used */ ++ phy_interface_t interface[2]; ++}; ++ ++#endif /* __NET_GEMINI_PLATFORM_H__ */ +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -15,6 +15,7 @@ + #include + + struct mtd_partition; ++struct gemini_gmac_platform_data; + + extern void gemini_map_io(void); + extern void gemini_init_irq(void); +@@ -28,6 +29,7 @@ extern int platform_register_pflash(unsi + struct mtd_partition *parts, + unsigned int nr_parts); + extern int platform_register_watchdog(void); ++extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata); + + extern void gemini_restart(enum reboot_mode mode, const char *cmd); + +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include "common.h" + + static struct plat_serial8250_port serial_platform_data[] = { +@@ -134,3 +135,56 @@ int __init platform_register_watchdog(vo + { + return platform_device_register(&wdt_device); + } ++ ++static struct resource gmac_resources[] = { ++ { ++ .start = GEMINI_TOE_BASE, ++ .end = GEMINI_TOE_BASE + 0xffff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IRQ_GMAC0, ++ .end = IRQ_GMAC0, ++ .flags = IORESOURCE_IRQ, ++ }, ++ { ++ .start = IRQ_GMAC1, ++ .end = IRQ_GMAC1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 gmac_dmamask = 0xffffffffUL; ++ ++static struct platform_device ethernet_device = { ++ .name = "gmac-gemini", ++ .id = 0, ++ .dev = { ++ .dma_mask = &gmac_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(gmac_resources), ++ .resource = gmac_resources, ++}; ++ ++int platform_register_ethernet(struct gemini_gmac_platform_data *pdata) ++{ ++ unsigned int reg; ++ ++ reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ ++ reg &= ~(GMAC_GMII | GMAC_1_ENABLE); ++ ++ if (pdata->bus_id[1]) ++ reg |= GMAC_1_ENABLE; ++ else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII) ++ reg |= GMAC_GMII; ++ ++ writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ ++ ethernet_device.dev.platform_data = pdata; ++ ++ return platform_device_register(ðernet_device); ++} +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -70,6 +70,7 @@ source "drivers/net/ethernet/neterion/Kc + source "drivers/net/ethernet/faraday/Kconfig" + source "drivers/net/ethernet/freescale/Kconfig" + source "drivers/net/ethernet/fujitsu/Kconfig" ++source "drivers/net/ethernet/gemini/Kconfig" + source "drivers/net/ethernet/hisilicon/Kconfig" + source "drivers/net/ethernet/hp/Kconfig" + source "drivers/net/ethernet/ibm/Kconfig" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_NET_VENDOR_EXAR) += neterio + obj-$(CONFIG_NET_VENDOR_FARADAY) += faraday/ + obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/ + obj-$(CONFIG_NET_VENDOR_FUJITSU) += fujitsu/ ++obj-$(CONFIG_NET_VENDOR_GEMINI) += gemini/ + obj-$(CONFIG_NET_VENDOR_HISILICON) += hisilicon/ + obj-$(CONFIG_NET_VENDOR_HP) += hp/ + obj-$(CONFIG_NET_VENDOR_IBM) += ibm/ +--- /dev/null ++++ b/drivers/net/ethernet/gemini/Kconfig +@@ -0,0 +1,31 @@ ++# ++# Gemini device configuration ++# ++ ++config NET_VENDOR_GEMINI ++ bool "Cortina Gemini devices" ++ default y ++ depends on ARCH_GEMINI ++ ---help--- ++ If you have a network (Ethernet) card belonging to this class, say Y ++ and read the Ethernet-HOWTO, available from ++ . ++ ++ Note that the answer to this question doesn't directly affect the ++ kernel: saying N will just cause the configurator to skip all ++ the questions about D-Link devices. If you say Y, you will be asked for ++ your specific card in the following questions. ++ ++if NET_VENDOR_GEMINI ++ ++config GEMINI_SL351X ++ tristate "StorLink SL351x Gigabit Ethernet support" ++ depends on ARCH_GEMINI ++ select PHYLIB ++ select MDIO_BITBANG ++ select MDIO_GPIO ++ select CRC32 ++ ---help--- ++ This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet. ++ ++endif # NET_VENDOR_GEMINI +--- /dev/null ++++ b/drivers/net/ethernet/gemini/Makefile +@@ -0,0 +1,5 @@ ++# ++# Makefile for the Cortina Gemini network device drivers. ++# ++ ++obj-$(CONFIG_GEMINI_SL351X) += sl351x.o +--- /dev/null ++++ b/drivers/net/ethernet/gemini/sl351x.c +@@ -0,0 +1,2340 @@ ++/* ++ * Ethernet device driver for Gemini SoC (SL351x GMAC). ++ * ++ * Copyright (C) 2011, Tobias Waldvogel ++ * ++ * Based on work by MichaÅ‚ MirosÅ‚aw and ++ * Paulius Zaleckas and ++ * Giuseppe De Robertis and ++ * GPLd spaghetti code from Raidsonic and other Gemini-based NAS vendors. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include "sl351x_hw.h" ++ ++#define DRV_NAME "gmac-gemini" ++#define DRV_VERSION "1.0" ++ ++#define HSIZE_8 0b00 ++#define HSIZE_16 0b01 ++#define HSIZE_32 0b10 ++ ++#define HBURST_SINGLE 0b00 ++#define HBURST_INCR 0b01 ++#define HBURST_INCR4 0b10 ++#define HBURST_INCR8 0b11 ++ ++#define HPROT_DATA_CACHE BIT(0) ++#define HPROT_PRIVILIGED BIT(1) ++#define HPROT_BUFFERABLE BIT(2) ++#define HPROT_CACHABLE BIT(3) ++ ++#define DEFAULT_RX_COALESCE_NSECS 0 ++#define DEFAULT_GMAC_RXQ_ORDER 9 ++#define DEFAULT_GMAC_TXQ_ORDER 8 ++#define DEFAULT_RX_BUF_ORDER 11 ++#define DEFAULT_NAPI_WEIGHT 64 ++#define TX_MAX_FRAGS 16 ++#define TX_QUEUE_NUM 1 /* max: 6 */ ++#define RX_MAX_ALLOC_ORDER 2 ++ ++#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT|GMAC0_TXPERR_INT_BIT| \ ++ GMAC0_RXDERR_INT_BIT|GMAC0_RXPERR_INT_BIT) ++#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT| \ ++ GMAC0_SWTQ00_FIN_INT_BIT) ++#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT|GMAC0_RX_OVERRUN_INT_BIT) ++ ++#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \ ++ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \ ++ NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) ++ ++MODULE_AUTHOR("Tobias Waldvogel"); ++MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" DRV_NAME); ++ ++struct toe_private { ++ void __iomem *iomem; ++ spinlock_t irq_lock; ++ ++ struct net_device *netdev[2]; ++ __le32 mac_addr[2][3]; ++ ++ struct device *dev; ++ int irq; ++ ++ unsigned int freeq_order; ++ unsigned int freeq_frag_order; ++ GMAC_RXDESC_T *freeq_ring; ++ dma_addr_t freeq_dma_base; ++ struct page **freeq_page_tab; ++ spinlock_t freeq_lock; ++}; ++ ++struct gmac_txq { ++ GMAC_TXDESC_T *ring; ++ struct sk_buff **skb; ++ unsigned int cptr; ++ unsigned int noirq_packets; ++}; ++ ++struct gmac_private { ++ unsigned int num; ++ struct toe_private *toe; ++ void __iomem *ctl_iomem; ++ void __iomem *dma_iomem; ++ ++ void __iomem *rxq_rwptr; ++ GMAC_RXDESC_T *rxq_ring; ++ unsigned int rxq_order; ++ ++ struct napi_struct napi; ++ struct hrtimer rx_coalesce_timer; ++ unsigned int rx_coalesce_nsecs; ++ unsigned int freeq_refill; ++ struct gmac_txq txq[TX_QUEUE_NUM]; ++ unsigned int txq_order; ++ unsigned int irq_every_tx_packets; ++ ++ dma_addr_t rxq_dma_base; ++ dma_addr_t txq_dma_base; ++ ++ unsigned int msg_enable; ++ spinlock_t config_lock; ++ ++ struct u64_stats_sync tx_stats_syncp; ++ struct u64_stats_sync rx_stats_syncp; ++ struct u64_stats_sync ir_stats_syncp; ++ ++ struct rtnl_link_stats64 stats; ++ u64 hw_stats[RX_STATS_NUM]; ++ u64 rx_stats[RX_STATUS_NUM]; ++ u64 rx_csum_stats[RX_CHKSUM_NUM]; ++ u64 rx_napi_exits; ++ u64 tx_frag_stats[TX_MAX_FRAGS]; ++ u64 tx_frags_linearized; ++ u64 tx_hw_csummed; ++}; ++ ++#define GMAC_STATS_NUM ( \ ++ RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \ ++ TX_MAX_FRAGS + 2) ++ ++static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = { ++ "GMAC_IN_DISCARDS", ++ "GMAC_IN_ERRORS", ++ "GMAC_IN_MCAST", ++ "GMAC_IN_BCAST", ++ "GMAC_IN_MAC1", ++ "GMAC_IN_MAC2", ++ "RX_STATUS_GOOD_FRAME", ++ "RX_STATUS_TOO_LONG_GOOD_CRC", ++ "RX_STATUS_RUNT_FRAME", ++ "RX_STATUS_SFD_NOT_FOUND", ++ "RX_STATUS_CRC_ERROR", ++ "RX_STATUS_TOO_LONG_BAD_CRC", ++ "RX_STATUS_ALIGNMENT_ERROR", ++ "RX_STATUS_TOO_LONG_BAD_ALIGN", ++ "RX_STATUS_RX_ERR", ++ "RX_STATUS_DA_FILTERED", ++ "RX_STATUS_BUFFER_FULL", ++ "RX_STATUS_11", ++ "RX_STATUS_12", ++ "RX_STATUS_13", ++ "RX_STATUS_14", ++ "RX_STATUS_15", ++ "RX_CHKSUM_IP_UDP_TCP_OK", ++ "RX_CHKSUM_IP_OK_ONLY", ++ "RX_CHKSUM_NONE", ++ "RX_CHKSUM_3", ++ "RX_CHKSUM_IP_ERR_UNKNOWN", ++ "RX_CHKSUM_IP_ERR", ++ "RX_CHKSUM_TCP_UDP_ERR", ++ "RX_CHKSUM_7", ++ "RX_NAPI_EXITS", ++ "TX_FRAGS[1]", ++ "TX_FRAGS[2]", ++ "TX_FRAGS[3]", ++ "TX_FRAGS[4]", ++ "TX_FRAGS[5]", ++ "TX_FRAGS[6]", ++ "TX_FRAGS[7]", ++ "TX_FRAGS[8]", ++ "TX_FRAGS[9]", ++ "TX_FRAGS[10]", ++ "TX_FRAGS[11]", ++ "TX_FRAGS[12]", ++ "TX_FRAGS[13]", ++ "TX_FRAGS[14]", ++ "TX_FRAGS[15]", ++ "TX_FRAGS[16+]", ++ "TX_FRAGS_LINEARIZED", ++ "TX_HW_CSUMMED", ++}; ++ ++static void gmac_dump_dma_state(struct net_device *dev); ++ ++static void gmac_update_config0_reg(struct net_device *dev, u32 val, u32 vmask) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ reg = (reg & ~vmask) | val; ++ writel(reg, gmac->ctl_iomem + GMAC_CONFIG0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++} ++ ++static void gmac_enable_tx_rx(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0; ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(config0); ++ reg &= ~CONFIG0_TX_RX_DISABLE; ++ writel(reg, config0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++} ++ ++static void gmac_disable_tx_rx(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0; ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(config0); ++ reg |= CONFIG0_TX_RX_DISABLE; ++ writel(reg, config0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++ ++ mdelay(10); /* let GMAC consume packet */ ++} ++ ++static void gmac_set_flow_control(struct net_device *dev, bool tx, bool rx) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ void __iomem *config0 = gmac->ctl_iomem + GMAC_CONFIG0; ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(config0); ++ reg &= ~CONFIG0_FLOW_CTL; ++ if (tx) ++ reg |= CONFIG0_FLOW_TX; ++ if (rx) ++ reg |= CONFIG0_FLOW_RX; ++ writel(reg, config0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++} ++ ++static void gmac_update_link_state(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ void __iomem *status_reg = gmac->ctl_iomem + GMAC_STATUS; ++ struct phy_device *phydev = dev->phydev; ++ GMAC_STATUS_T status, old_status; ++ int pause_tx=0, pause_rx=0; ++ ++ old_status.bits32 = status.bits32 = readl(status_reg); ++ ++ status.bits.link = phydev->link; ++ status.bits.duplex = phydev->duplex; ++ ++ switch (phydev->speed) { ++ case 1000: ++ status.bits.speed = GMAC_SPEED_1000; ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) ++ status.bits.mii_rmii = GMAC_PHY_RGMII_1000; ++ break; ++ case 100: ++ status.bits.speed = GMAC_SPEED_100; ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) ++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; ++ break; ++ case 10: ++ status.bits.speed = GMAC_SPEED_10; ++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) ++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; ++ break; ++ default: ++ netdev_warn(dev, "Not supported PHY speed (%d)\n", ++ phydev->speed); ++ } ++ ++ if (phydev->duplex == DUPLEX_FULL) { ++ u16 lcladv = phy_read(phydev, MII_ADVERTISE); ++ u16 rmtadv = phy_read(phydev, MII_LPA); ++ u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); ++ ++ if (cap & FLOW_CTRL_RX) ++ pause_rx=1; ++ if (cap & FLOW_CTRL_TX) ++ pause_tx=1; ++ } ++ ++ gmac_set_flow_control(dev, pause_tx, pause_rx); ++ ++ if (old_status.bits32 == status.bits32) ++ return; ++ ++ if (netif_msg_link(gmac)) { ++ phy_print_status(phydev); ++ netdev_info(dev, "link flow control: %s\n", ++ phydev->pause ++ ? (phydev->asym_pause ? "tx" : "both") ++ : (phydev->asym_pause ? "rx" : "none") ++ ); ++ } ++ ++ gmac_disable_tx_rx(dev); ++ writel(status.bits32, status_reg); ++ gmac_enable_tx_rx(dev); ++} ++ ++static int gmac_setup_phy(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ struct gemini_gmac_platform_data *pdata = toe->dev->platform_data; ++ GMAC_STATUS_T status = { .bits32 = 0 }; ++ int num = dev->dev_id; ++ ++ dev->phydev = phy_connect(dev, pdata->bus_id[num], ++ &gmac_update_link_state, pdata->interface[num]); ++ ++ if (IS_ERR(dev->phydev)) { ++ int err = PTR_ERR(dev->phydev); ++ dev->phydev = NULL; ++ return err; ++ } ++ ++ dev->phydev->supported &= PHY_GBIT_FEATURES; ++ dev->phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; ++ dev->phydev->advertising = dev->phydev->supported; ++ ++ /* set PHY interface type */ ++ switch (dev->phydev->interface) { ++ case PHY_INTERFACE_MODE_MII: ++ status.bits.mii_rmii = GMAC_PHY_MII; ++ break; ++ case PHY_INTERFACE_MODE_GMII: ++ status.bits.mii_rmii = GMAC_PHY_GMII; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10; ++ break; ++ default: ++ netdev_err(dev, "Unsupported MII interface\n"); ++ phy_disconnect(dev->phydev); ++ dev->phydev = NULL; ++ return -EINVAL; ++ } ++ writel(status.bits32, gmac->ctl_iomem + GMAC_STATUS); ++ ++ return 0; ++} ++ ++static int gmac_pick_rx_max_len(int max_l3_len) ++{ ++ /* index = CONFIG_MAXLEN_XXX values */ ++ static const int max_len[8] = { ++ 1536, 1518, 1522, 1542, ++ 9212, 10236, 1518, 1518 ++ }; ++ int i, n = 5; ++ ++ max_l3_len += ETH_HLEN + VLAN_HLEN; ++ ++ if (max_l3_len > max_len[n]) ++ return -1; ++ ++ for (i = 0; i < 5; ++i) { ++ if (max_len[i] >= max_l3_len && max_len[i] < max_len[n]) ++ n = i; ++ } ++ ++ return n; ++} ++ ++static int gmac_init(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ u32 val; ++ ++ GMAC_CONFIG0_T config0 = { .bits = { ++ .dis_tx = 1, ++ .dis_rx = 1, ++ .ipv4_rx_chksum = 1, ++ .ipv6_rx_chksum = 1, ++ .rx_err_detect = 1, ++ .rgmm_edge = 1, ++ .port0_chk_hwq = 1, ++ .port1_chk_hwq = 1, ++ .port0_chk_toeq = 1, ++ .port1_chk_toeq = 1, ++ .port0_chk_classq = 1, ++ .port1_chk_classq = 1, ++ } }; ++ GMAC_AHB_WEIGHT_T ahb_weight = { .bits = { ++ .rx_weight = 1, ++ .tx_weight = 1, ++ .hash_weight = 1, ++ .pre_req = 0x1f, ++ .tqDV_threshold = 0, ++ } }; ++ GMAC_TX_WCR0_T hw_weigh = { .bits = { ++ .hw_tq3 = 1, ++ .hw_tq2 = 1, ++ .hw_tq1 = 1, ++ .hw_tq0 = 1, ++ } }; ++ GMAC_TX_WCR1_T sw_weigh = { .bits = { ++ .sw_tq5 = 1, ++ .sw_tq4 = 1, ++ .sw_tq3 = 1, ++ .sw_tq2 = 1, ++ .sw_tq1 = 1, ++ .sw_tq0 = 1, ++ } }; ++ GMAC_CONFIG1_T config1 = { .bits = { ++ .set_threshold = 16, ++ .rel_threshold = 24, ++ } }; ++ GMAC_CONFIG2_T config2 = { .bits = { ++ .set_threshold = 16, ++ .rel_threshold = 32, ++ } }; ++ GMAC_CONFIG3_T config3 = { .bits = { ++ .set_threshold = 0, ++ .rel_threshold = 0, ++ } }; ++ ++ config0.bits.max_len = gmac_pick_rx_max_len(dev->mtu); ++ ++ val = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ config0.bits.reserved = ((GMAC_CONFIG0_T)val).bits.reserved; ++ writel(config0.bits32, gmac->ctl_iomem + GMAC_CONFIG0); ++ writel(config1.bits32, gmac->ctl_iomem + GMAC_CONFIG1); ++ writel(config2.bits32, gmac->ctl_iomem + GMAC_CONFIG2); ++ writel(config3.bits32, gmac->ctl_iomem + GMAC_CONFIG3); ++ ++ val = readl(gmac->dma_iomem + GMAC_AHB_WEIGHT_REG); ++ writel(ahb_weight.bits32, gmac->dma_iomem + GMAC_AHB_WEIGHT_REG); ++ ++ writel(hw_weigh.bits32, ++ gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_0_REG); ++ writel(sw_weigh.bits32, ++ gmac->dma_iomem + GMAC_TX_WEIGHTING_CTRL_1_REG); ++ ++ gmac->rxq_order = DEFAULT_GMAC_RXQ_ORDER; ++ gmac->txq_order = DEFAULT_GMAC_TXQ_ORDER; ++ gmac->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS; ++ ++ /* Mark every quarter of the queue a packet for interrupt ++ in order to be able to wake up the queue if it was stopped */ ++ gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2); ++ ++ return 0; ++} ++ ++static void gmac_uninit(struct net_device *dev) ++{ ++ if (dev->phydev) ++ phy_disconnect(dev->phydev); ++} ++ ++static int gmac_setup_txqs(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG; ++ void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG; ++ ++ unsigned int n_txq = dev->num_tx_queues; ++ size_t entries = 1 <txq_order; ++ size_t len = n_txq * entries; ++ struct gmac_txq *txq = gmac->txq; ++ GMAC_TXDESC_T *desc_ring; ++ struct sk_buff **skb_tab; ++ unsigned int r; ++ int i; ++ ++ skb_tab = kzalloc(len * sizeof(*skb_tab), GFP_KERNEL); ++ if (!skb_tab) ++ return -ENOMEM; ++ ++ desc_ring = dma_alloc_coherent(toe->dev, len * sizeof(*desc_ring), ++ &gmac->txq_dma_base, GFP_KERNEL); ++ ++ if (!desc_ring) { ++ kfree(skb_tab); ++ return -ENOMEM; ++ } ++ ++ BUG_ON(gmac->txq_dma_base & ~DMA_Q_BASE_MASK); ++ ++ writel(gmac->txq_dma_base | gmac->txq_order, base_reg); ++ ++ for (i = 0; i < n_txq; i++) { ++ txq->ring = desc_ring; ++ txq->skb = skb_tab; ++ txq->noirq_packets = 0; ++ ++ r = readw(rwptr_reg); ++ rwptr_reg += 2; ++ writew(r, rwptr_reg); ++ rwptr_reg +=2; ++ txq->cptr = r; ++ ++ txq++; ++ desc_ring += entries; ++ skb_tab += entries; ++ } ++ ++ return 0; ++} ++ ++static void gmac_clean_txq(struct net_device *dev, struct gmac_txq *txq, ++ unsigned int r) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned int errs = 0; ++ unsigned int pkts = 0; ++ unsigned int hwchksum = 0; ++ unsigned long bytes = 0; ++ unsigned int m = (1 << gmac->txq_order) - 1; ++ unsigned int c = txq->cptr; ++ GMAC_TXDESC_0_T word0; ++ GMAC_TXDESC_1_T word1; ++ unsigned int word3; ++ dma_addr_t mapping; ++ GMAC_TXDESC_T *txd; ++ unsigned short nfrags; ++ ++ if (unlikely(c == r)) ++ return; ++ ++ rmb(); ++ while (c != r) { ++ txd = txq->ring + c; ++ word0 = txd->word0; ++ word1 = txd->word1; ++ mapping = txd->word2.buf_adr; ++ word3 = txd->word3.bits32; ++ ++ dma_unmap_single(toe->dev, mapping, word0.bits.buffer_size, DMA_TO_DEVICE); ++ ++ if (word3 & EOF_BIT) ++ dev_kfree_skb(txq->skb[c]); ++ ++ c++; ++ c &= m; ++ ++ if (!(word3 & SOF_BIT)) ++ continue; ++ ++ if (!word0.bits.status_tx_ok) { ++ errs++; ++ continue; ++ } ++ ++ pkts++; ++ bytes += txd->word1.bits.byte_count; ++ ++ if (word1.bits32 & TSS_CHECKUM_ENABLE) ++ hwchksum++; ++ ++ nfrags = word0.bits.desc_count - 1; ++ if (nfrags) { ++ if (nfrags >= TX_MAX_FRAGS) ++ nfrags = TX_MAX_FRAGS - 1; ++ ++ u64_stats_update_begin(&gmac->tx_stats_syncp); ++ gmac->tx_frag_stats[nfrags]++; ++ u64_stats_update_end(&gmac->ir_stats_syncp); ++ } ++ } ++ ++ u64_stats_update_begin(&gmac->ir_stats_syncp); ++ gmac->stats.tx_errors += errs; ++ gmac->stats.tx_packets += pkts; ++ gmac->stats.tx_bytes += bytes; ++ gmac->tx_hw_csummed += hwchksum; ++ u64_stats_update_end(&gmac->ir_stats_syncp); ++ ++ txq->cptr = c; ++} ++ ++static void gmac_cleanup_txqs(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *rwptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG; ++ void __iomem *base_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_BASE_REG; ++ ++ unsigned n_txq = dev->num_tx_queues; ++ unsigned int r, i; ++ ++ for (i = 0; i < n_txq; i++) { ++ r = readw(rwptr_reg); ++ rwptr_reg += 2; ++ writew(r, rwptr_reg); ++ rwptr_reg += 2; ++ ++ gmac_clean_txq(dev, gmac->txq + i, r); ++ } ++ writel(0, base_reg); ++ ++ kfree(gmac->txq->skb); ++ dma_free_coherent(toe->dev, ++ n_txq * sizeof(*gmac->txq->ring) << gmac->txq_order, ++ gmac->txq->ring, gmac->txq_dma_base); ++} ++ ++static int gmac_setup_rxq(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id); ++ ++ gmac->rxq_rwptr = &qhdr->word1; ++ gmac->rxq_ring = dma_alloc_coherent(toe->dev, ++ sizeof(*gmac->rxq_ring) << gmac->rxq_order, ++ &gmac->rxq_dma_base, GFP_KERNEL); ++ if (!gmac->rxq_ring) ++ return -ENOMEM; ++ ++ BUG_ON(gmac->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK); ++ ++ writel(gmac->rxq_dma_base | gmac->rxq_order, &qhdr->word0); ++ writel(0, gmac->rxq_rwptr); ++ return 0; ++} ++ ++static void gmac_cleanup_rxq(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ ++ NONTOE_QHDR_T __iomem *qhdr = toe->iomem + TOE_DEFAULT_Q_HDR_BASE(dev->dev_id); ++ void __iomem *dma_reg = &qhdr->word0; ++ void __iomem *ptr_reg = &qhdr->word1; ++ GMAC_RXDESC_T *rxd = gmac->rxq_ring; ++ DMA_RWPTR_T rw; ++ unsigned int r, w; ++ unsigned int m = (1 <rxq_order) - 1; ++ struct page *page; ++ dma_addr_t mapping; ++ ++ rw.bits32 = readl(ptr_reg); ++ r = rw.bits.rptr; ++ w = rw.bits.wptr; ++ writew(r, ptr_reg + 2); ++ ++ writel(0, dma_reg); ++ ++ rmb(); ++ while (r != w) { ++ mapping = rxd[r].word2.buf_adr; ++ r++; ++ r &= m; ++ ++ if (!mapping) ++ continue; ++ ++ page = pfn_to_page(dma_to_pfn(toe->dev, mapping)); ++ put_page(page); ++ } ++ ++ dma_free_coherent(toe->dev, sizeof(*gmac->rxq_ring) << gmac->rxq_order, ++ gmac->rxq_ring, gmac->rxq_dma_base); ++} ++ ++static struct page *toe_freeq_alloc_map_page(struct toe_private *toe, int pn) ++{ ++ unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order; ++ unsigned int frag_len = 1 << toe->freeq_frag_order; ++ GMAC_RXDESC_T *freeq_entry; ++ dma_addr_t mapping; ++ struct page *page; ++ int i; ++ ++ page = alloc_page(__GFP_COLD | GFP_ATOMIC); ++ if (!page) ++ return NULL; ++ ++ mapping = dma_map_single(toe->dev, page_address(page), ++ PAGE_SIZE, DMA_FROM_DEVICE); ++ ++ if (unlikely(dma_mapping_error(toe->dev, mapping) || !mapping)) { ++ put_page(page); ++ return NULL; ++ } ++ ++ freeq_entry = toe->freeq_ring + (pn << fpp_order); ++ for (i = 1 << fpp_order; i > 0; --i) { ++ freeq_entry->word2.buf_adr = mapping; ++ freeq_entry++; ++ mapping += frag_len; ++ } ++ ++ if (toe->freeq_page_tab[pn]) { ++ mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr; ++ dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE); ++ put_page(toe->freeq_page_tab[pn]); ++ } ++ ++ toe->freeq_page_tab[pn] = page; ++ return page; ++} ++ ++static unsigned int toe_fill_freeq(struct toe_private *toe, int reset) ++{ ++ void __iomem *rwptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG; ++ ++ DMA_RWPTR_T rw; ++ unsigned int pn, epn; ++ unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order; ++ unsigned int m_pn = (1 << (toe->freeq_order - fpp_order)) - 1; ++ struct page *page; ++ unsigned int count = 0; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&toe->freeq_lock, flags); ++ ++ rw.bits32 = readl(rwptr_reg); ++ pn = (reset ? rw.bits.rptr : rw.bits.wptr) >> fpp_order; ++ epn = (rw.bits.rptr >> fpp_order) - 1; ++ epn &= m_pn; ++ ++ while (pn != epn) { ++ page = toe->freeq_page_tab[pn]; ++ ++ if (atomic_read(&page->_count) > 1) { ++ unsigned int fl = (pn -epn) & m_pn; ++ ++ if (fl > 64 >> fpp_order) ++ break; ++ ++ page = toe_freeq_alloc_map_page(toe, pn); ++ if (!page) ++ break; ++ } ++ ++ atomic_add(1 << fpp_order, &page->_count); ++ count += 1 << fpp_order; ++ pn++; ++ pn &= m_pn; ++ } ++ ++ wmb(); ++ writew(pn << fpp_order, rwptr_reg+2); ++ ++ spin_unlock_irqrestore(&toe->freeq_lock, flags); ++ return count; ++} ++ ++static int toe_setup_freeq(struct toe_private *toe) ++{ ++ void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG; ++ QUEUE_THRESHOLD_T qt; ++ DMA_SKB_SIZE_T skbsz; ++ unsigned int filled; ++ unsigned int frag_len = 1 << toe->freeq_frag_order; ++ unsigned int len = 1 << toe->freeq_order; ++ unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order; ++ unsigned int pages = len >> fpp_order; ++ dma_addr_t mapping; ++ unsigned int pn; ++ ++ toe->freeq_ring = dma_alloc_coherent(toe->dev, ++ sizeof(*toe->freeq_ring) << toe->freeq_order, ++ &toe->freeq_dma_base, GFP_KERNEL); ++ if (!toe->freeq_ring) ++ return -ENOMEM; ++ ++ BUG_ON(toe->freeq_dma_base & ~DMA_Q_BASE_MASK); ++ ++ toe->freeq_page_tab = kzalloc(pages * sizeof(*toe->freeq_page_tab), ++ GFP_KERNEL); ++ if (!toe->freeq_page_tab) ++ goto err_freeq; ++ ++ for (pn = 0; pn < pages; pn++) ++ if (!toe_freeq_alloc_map_page(toe, pn)) ++ goto err_freeq_alloc; ++ ++ filled = toe_fill_freeq(toe, 1); ++ if (!filled) ++ goto err_freeq_alloc; ++ ++ qt.bits32 = readl(toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG); ++ qt.bits.swfq_empty = 32; ++ writel(qt.bits32, toe->iomem + GLOBAL_QUEUE_THRESHOLD_REG); ++ ++ skbsz.bits.sw_skb_size = 1 << toe->freeq_frag_order; ++ writel(skbsz.bits32, toe->iomem + GLOBAL_DMA_SKB_SIZE_REG); ++ writel(toe->freeq_dma_base | toe->freeq_order, dma_reg); ++ ++ return 0; ++ ++err_freeq_alloc: ++ while (pn > 0) { ++ --pn; ++ mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr; ++ dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE); ++ put_page(toe->freeq_page_tab[pn]); ++ } ++ ++err_freeq: ++ dma_free_coherent(toe->dev, ++ sizeof(*toe->freeq_ring) << toe->freeq_order, ++ toe->freeq_ring, toe->freeq_dma_base); ++ toe->freeq_ring = NULL; ++ return -ENOMEM; ++} ++ ++static void toe_cleanup_freeq(struct toe_private *toe) ++{ ++ void __iomem *dma_reg = toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG; ++ void __iomem *ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG; ++ ++ unsigned int frag_len = 1 << toe->freeq_frag_order; ++ unsigned int len = 1 << toe->freeq_order; ++ unsigned int fpp_order = PAGE_SHIFT - toe->freeq_frag_order; ++ unsigned int pages = len >> fpp_order; ++ struct page *page; ++ dma_addr_t mapping; ++ unsigned int pn; ++ ++ writew(readw(ptr_reg), ptr_reg + 2); ++ writel(0, dma_reg); ++ ++ for (pn = 0; pn < pages; pn++) { ++ mapping = toe->freeq_ring[pn << fpp_order].word2.buf_adr; ++ dma_unmap_single(toe->dev, mapping, frag_len, DMA_FROM_DEVICE); ++ ++ page = toe->freeq_page_tab[pn]; ++ while (atomic_read(&page->_count) > 0) ++ put_page(page); ++ } ++ ++ kfree(toe->freeq_page_tab); ++ ++ dma_free_coherent(toe->dev, ++ sizeof(*toe->freeq_ring) << toe->freeq_order, ++ toe->freeq_ring, toe->freeq_dma_base); ++} ++ ++static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id) ++{ ++ void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG; ++ struct gmac_private *gmac; ++ struct net_device *other = toe->netdev[1 - changing_dev_id]; ++ unsigned new_size = 0; ++ unsigned new_order; ++ int err; ++ unsigned long flags; ++ unsigned en; ++ ++ if (other && netif_running(other)) ++ return -EBUSY; ++ ++ if (toe->netdev[0]) { ++ gmac = netdev_priv(toe->netdev[0]); ++ new_size = 1 << (gmac->rxq_order + 1); ++ } ++ ++ if (toe->netdev[1]) { ++ gmac = netdev_priv(toe->netdev[1]); ++ new_size += 1 << (gmac->rxq_order + 1); ++ } ++ ++ new_order = min(15, ilog2(new_size - 1) + 1); ++ if (toe->freeq_order == new_order) ++ return 0; ++ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ en = readl(irqen_reg); ++ en &= ~SWFQ_EMPTY_INT_BIT; ++ writel(en, irqen_reg); ++ ++ if (toe->freeq_ring) ++ toe_cleanup_freeq(toe); ++ ++ toe->freeq_order = new_order; ++ err = toe_setup_freeq(toe); ++ ++ en |= SWFQ_EMPTY_INT_BIT; ++ writel(en, irqen_reg); ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++ ++ return err; ++} ++ ++static void gmac_tx_irq_enable(struct net_device *dev, unsigned txq, int en) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned val, mask; ++ ++ mask = GMAC0_IRQ0_TXQ0_INTS << (6 * dev->dev_id + txq); ++ ++ if (en) ++ writel(mask, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG); ++ ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ val = en ? val | mask : val & ~mask; ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++} ++ ++ ++static void gmac_tx_irq(struct net_device *dev, unsigned txq_num) ++{ ++ struct netdev_queue *ntxq = netdev_get_tx_queue(dev, txq_num); ++ ++ gmac_tx_irq_enable(dev, txq_num, 0); ++ netif_tx_wake_queue(ntxq); ++} ++ ++static int gmac_map_tx_bufs(struct net_device *dev, struct sk_buff *skb, ++ struct gmac_txq *txq, unsigned short *desc) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ struct skb_shared_info *skb_si = skb_shinfo(skb); ++ skb_frag_t *skb_frag; ++ short frag, last_frag = skb_si->nr_frags - 1; ++ unsigned short m = (1 << gmac->txq_order) -1; ++ unsigned short w = *desc; ++ unsigned word1, word3, buflen; ++ dma_addr_t mapping; ++ void *buffer; ++ unsigned short mtu; ++ GMAC_TXDESC_T *txd; ++ ++ mtu = ETH_HLEN; ++ mtu += dev->mtu; ++ if (skb->protocol == htons(ETH_P_8021Q)) ++ mtu += VLAN_HLEN; ++ ++ word1 = skb->len; ++ word3 = SOF_BIT; ++ ++ if (word1 > mtu) { ++ word1 |= TSS_MTU_ENABLE_BIT; ++ word3 += mtu; ++ } ++ ++ if (skb->ip_summed != CHECKSUM_NONE) { ++ int tcp = 0; ++ if (skb->protocol == htons(ETH_P_IP)) { ++ word1 |= TSS_IP_CHKSUM_BIT; ++ tcp = ip_hdr(skb)->protocol == IPPROTO_TCP; ++ } else { /* IPv6 */ ++ word1 |= TSS_IPV6_ENABLE_BIT; ++ tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP; ++ } ++ ++ word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT; ++ } ++ ++ frag = -1; ++ while (frag <= last_frag) { ++ if (frag == -1) { ++ buffer = skb->data; ++ buflen = skb_headlen(skb); ++ } else { ++ skb_frag = skb_si->frags + frag; ++ buffer = page_address(skb_frag_page(skb_frag)) + ++ skb_frag->page_offset; ++ buflen = skb_frag->size; ++ } ++ ++ if (frag == last_frag) { ++ word3 |= EOF_BIT; ++ txq->skb[w] = skb; ++ } ++ ++ mapping = dma_map_single(toe->dev, buffer, buflen, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(toe->dev, mapping) || ++ !(mapping & PAGE_MASK)) ++ goto map_error; ++ ++ txd = txq->ring + w; ++ txd->word0.bits32 = buflen; ++ txd->word1.bits32 = word1; ++ txd->word2.buf_adr = mapping; ++ txd->word3.bits32 = word3; ++ ++ word3 &= MTU_SIZE_BIT_MASK; ++ w++; ++ w &= m; ++ frag++; ++ } ++ ++ *desc = w; ++ return 0; ++ ++map_error: ++ while (w != *desc) { ++ w--; ++ w &= m; ++ ++ dma_unmap_page(toe->dev, txq->ring[w].word2.buf_adr, ++ txq->ring[w].word0.bits.buffer_size, DMA_TO_DEVICE); ++ } ++ return ENOMEM; ++} ++ ++static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ void __iomem *ptr_reg; ++ struct gmac_txq *txq; ++ struct netdev_queue *ntxq; ++ int txq_num, nfrags; ++ DMA_RWPTR_T rw; ++ unsigned short r, w, d; ++ unsigned short m = (1 << gmac->txq_order) - 1; ++ ++ SKB_FRAG_ASSERT(skb); ++ ++ if (unlikely(skb->len >= 0x10000)) ++ goto out_drop_free; ++ ++ txq_num = skb_get_queue_mapping(skb); ++ ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE_PTR_REG(txq_num); ++ txq = &gmac->txq[txq_num]; ++ ntxq = netdev_get_tx_queue(dev, txq_num); ++ nfrags = skb_shinfo(skb)->nr_frags; ++ ++ rw.bits32 = readl(ptr_reg); ++ r = rw.bits.rptr; ++ w = rw.bits.wptr; ++ ++ d = txq->cptr - w - 1; ++ d &= m; ++ ++ if (unlikely(d < nfrags+2)) ++ { ++ gmac_clean_txq(dev, txq, r); ++ d = txq->cptr - w - 1; ++ d &= m; ++ ++ if (unlikely(d < nfrags+2)) { ++ netif_tx_stop_queue(ntxq); ++ ++ d = txq->cptr + nfrags + 16; ++ d &= m; ++ txq->ring[d].word3.bits.eofie = 1; ++ gmac_tx_irq_enable(dev, txq_num, 1); ++ ++ u64_stats_update_begin(&gmac->tx_stats_syncp); ++ dev->stats.tx_fifo_errors++; ++ u64_stats_update_end(&gmac->tx_stats_syncp); ++ return NETDEV_TX_BUSY; ++ } ++ } ++ ++ if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w))) { ++ if (skb_linearize(skb)) ++ goto out_drop; ++ ++ if (unlikely(gmac_map_tx_bufs(dev, skb, txq, &w))) ++ goto out_drop_free; ++ ++ u64_stats_update_begin(&gmac->tx_stats_syncp); ++ gmac->tx_frags_linearized++; ++ u64_stats_update_end(&gmac->tx_stats_syncp); ++ } ++ ++ writew(w, ptr_reg+2); ++ ++ gmac_clean_txq(dev, txq, r); ++ return NETDEV_TX_OK; ++ ++out_drop_free: ++ dev_kfree_skb(skb); ++out_drop: ++ u64_stats_update_begin(&gmac->tx_stats_syncp); ++ gmac->stats.tx_dropped++; ++ u64_stats_update_end(&gmac->tx_stats_syncp); ++ return NETDEV_TX_OK; ++} ++ ++static void gmac_tx_timeout(struct net_device *dev) ++{ ++ netdev_err(dev, "Tx timeout\n"); ++ gmac_dump_dma_state(dev); ++} ++ ++static void gmac_enable_irq(struct net_device *dev, int enable) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned long flags; ++ unsigned val, mask; ++ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ ++ mask = GMAC0_IRQ0_2 << (dev->dev_id * 2); ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ val = enable ? (val | mask) : (val & ~mask); ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ ++ mask = DEFAULT_Q0_INT_BIT << dev->dev_id; ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ val = enable ? (val | mask) : (val & ~mask); ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ ++ mask = GMAC0_IRQ4_8 << (dev->dev_id * 8); ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG); ++ val = enable ? (val | mask) : (val & ~mask); ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG); ++ ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++} ++ ++static void gmac_enable_rx_irq(struct net_device *dev, int enable) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned long flags; ++ unsigned val, mask; ++ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ mask = DEFAULT_Q0_INT_BIT << dev->dev_id; ++ ++ val = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ val = enable ? (val | mask) : (val & ~mask); ++ writel(val, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++} ++ ++static struct sk_buff *gmac_skb_if_good_frame(struct gmac_private *gmac, ++ GMAC_RXDESC_0_T word0, unsigned frame_len) ++{ ++ struct sk_buff *skb = NULL; ++ unsigned rx_status = word0.bits.status; ++ unsigned rx_csum = word0.bits.chksum_status; ++ ++ gmac->rx_stats[rx_status]++; ++ gmac->rx_csum_stats[rx_csum]++; ++ ++ if (word0.bits.derr || word0.bits.perr || ++ rx_status || frame_len < ETH_ZLEN || ++ rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) { ++ gmac->stats.rx_errors++; ++ ++ if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status)) ++ gmac->stats.rx_length_errors++; ++ if (RX_ERROR_OVER(rx_status)) ++ gmac->stats.rx_over_errors++; ++ if (RX_ERROR_CRC(rx_status)) ++ gmac->stats.rx_crc_errors++; ++ if (RX_ERROR_FRAME(rx_status)) ++ gmac->stats.rx_frame_errors++; ++ ++ return NULL; ++ } ++ ++ skb = napi_get_frags(&gmac->napi); ++ if (!skb) ++ return NULL; ++ ++ if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK) ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ ++ gmac->stats.rx_bytes += frame_len; ++ gmac->stats.rx_packets++; ++ return skb; ++} ++ ++static unsigned gmac_rx(struct net_device *dev, unsigned budget) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *ptr_reg = gmac->rxq_rwptr; ++ ++ static struct sk_buff *skb; ++ ++ DMA_RWPTR_T rw; ++ unsigned short r, w; ++ unsigned short m = (1 << gmac->rxq_order) -1; ++ GMAC_RXDESC_T *rx = NULL; ++ struct page* page = NULL; ++ unsigned page_offs; ++ unsigned int frame_len, frag_len; ++ int frag_nr = 0; ++ ++ GMAC_RXDESC_0_T word0; ++ GMAC_RXDESC_1_T word1; ++ dma_addr_t mapping; ++ GMAC_RXDESC_3_T word3; ++ ++ rw.bits32 = readl(ptr_reg); ++ /* Reset interrupt as all packages until here are taken into account */ ++ writel(DEFAULT_Q0_INT_BIT << dev->dev_id, ++ toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG); ++ r = rw.bits.rptr; ++ w = rw.bits.wptr; ++ ++ while (budget && w != r) { ++ rx = gmac->rxq_ring + r; ++ word0 = rx->word0; ++ word1 = rx->word1; ++ mapping = rx->word2.buf_adr; ++ word3 = rx->word3; ++ ++ r++; ++ r &= m; ++ ++ frag_len = word0.bits.buffer_size; ++ frame_len =word1.bits.byte_count; ++ page_offs = mapping & ~PAGE_MASK; ++ ++ if (unlikely(!mapping)) { ++ netdev_err(dev, "rxq[%u]: HW BUG: zero DMA desc\n", r); ++ goto err_drop; ++ } ++ ++ page = pfn_to_page(dma_to_pfn(toe->dev, mapping)); ++ ++ if (word3.bits32 & SOF_BIT) { ++ if (unlikely(skb)) { ++ napi_free_frags(&gmac->napi); ++ gmac->stats.rx_dropped++; ++ } ++ ++ skb = gmac_skb_if_good_frame(gmac, word0, frame_len); ++ if (unlikely(!skb)) ++ goto err_drop; ++ ++ page_offs += NET_IP_ALIGN; ++ frag_len -= NET_IP_ALIGN; ++ frag_nr = 0; ++ ++ } else if (!skb) { ++ put_page(page); ++ continue; ++ } ++ ++ if (word3.bits32 & EOF_BIT) ++ frag_len = frame_len - skb->len; ++ ++ /* append page frag to skb */ ++ if (unlikely(frag_nr == MAX_SKB_FRAGS)) ++ goto err_drop; ++ ++ if (frag_len == 0) ++ netdev_err(dev, "Received fragment with len = 0\n"); ++ ++ skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len); ++ skb->len += frag_len; ++ skb->data_len += frag_len; ++ skb->truesize += frag_len; ++ frag_nr++; ++ ++ if (word3.bits32 & EOF_BIT) { ++ napi_gro_frags(&gmac->napi); ++ skb = NULL; ++ --budget; ++ } ++ continue; ++ ++err_drop: ++ if (skb) { ++ napi_free_frags(&gmac->napi); ++ skb = NULL; ++ } ++ ++ if (mapping) ++ put_page(page); ++ ++ gmac->stats.rx_dropped++; ++ } ++ ++ writew(r, ptr_reg); ++ return budget; ++} ++ ++static int gmac_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct gmac_private *gmac = netdev_priv(napi->dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned rx; ++ unsigned freeq_threshold = 1 << (toe->freeq_order - 1); ++ ++ u64_stats_update_begin(&gmac->rx_stats_syncp); ++ ++ rx = budget - gmac_rx(napi->dev, budget); ++ ++ if (rx == 0) { ++ napi_gro_flush(napi, false); ++ __napi_complete(napi); ++ gmac_enable_rx_irq(napi->dev, 1); ++ ++gmac->rx_napi_exits; ++ } ++ ++ gmac->freeq_refill += rx; ++ if (gmac->freeq_refill > freeq_threshold) { ++ gmac->freeq_refill -= freeq_threshold; ++ toe_fill_freeq(toe, 0); ++ } ++ ++ u64_stats_update_end(&gmac->rx_stats_syncp); ++ return budget; ++} ++ ++static void gmac_dump_dma_state(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *ptr_reg; ++ unsigned reg[5]; ++ ++ /* Interrupt status */ ++ reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG); ++ reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG); ++ reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG); ++ reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG); ++ reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG); ++ netdev_err(dev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ reg[0], reg[1], reg[2], reg[3], reg[4]); ++ ++ /* Interrupt enable */ ++ reg[0] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ reg[1] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ reg[2] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG); ++ reg[3] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG); ++ reg[4] = readl(toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG); ++ netdev_err(dev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ reg[0], reg[1], reg[2], reg[3], reg[4]); ++ ++ /* RX DMA status */ ++ reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_FIRST_DESC_REG); ++ reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_CURR_DESC_REG); ++ reg[2] = GET_RPTR(gmac->rxq_rwptr); ++ reg[3] = GET_WPTR(gmac->rxq_rwptr); ++ netdev_err(dev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ ++ reg[0] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD0_REG); ++ reg[1] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD1_REG); ++ reg[2] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD2_REG); ++ reg[3] = readl(gmac->dma_iomem + GMAC_DMA_RX_DESC_WORD3_REG); ++ netdev_err(dev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ ++ /* TX DMA status */ ++ ptr_reg = gmac->dma_iomem + GMAC_SW_TX_QUEUE0_PTR_REG; ++ ++ reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_FIRST_DESC_REG); ++ reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_CURR_DESC_REG); ++ reg[2] = GET_RPTR(ptr_reg); ++ reg[3] = GET_WPTR(ptr_reg); ++ netdev_err(dev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ ++ reg[0] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD0_REG); ++ reg[1] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD1_REG); ++ reg[2] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD2_REG); ++ reg[3] = readl(gmac->dma_iomem + GMAC_DMA_TX_DESC_WORD3_REG); ++ netdev_err(dev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ ++ /* FREE queues status */ ++ ptr_reg = toe->iomem + GLOBAL_SWFQ_RWPTR_REG; ++ ++ reg[0] = GET_RPTR(ptr_reg); ++ reg[1] = GET_WPTR(ptr_reg); ++ ++ ptr_reg = toe->iomem + GLOBAL_HWFQ_RWPTR_REG; ++ ++ reg[2] = GET_RPTR(ptr_reg); ++ reg[3] = GET_WPTR(ptr_reg); ++ netdev_err(dev, "FQ SW ptr: %u %u, HW ptr: %u %u\n", ++ reg[0], reg[1], reg[2], reg[3]); ++} ++ ++static void gmac_update_hw_stats(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned long flags; ++ unsigned int rx_discards, rx_mcast, rx_bcast; ++ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ u64_stats_update_begin(&gmac->ir_stats_syncp); ++ ++ gmac->hw_stats[0] += rx_discards = readl(gmac->ctl_iomem + GMAC_IN_DISCARDS); ++ gmac->hw_stats[1] += readl(gmac->ctl_iomem + GMAC_IN_ERRORS); ++ gmac->hw_stats[2] += rx_mcast = readl(gmac->ctl_iomem + GMAC_IN_MCAST); ++ gmac->hw_stats[3] += rx_bcast = readl(gmac->ctl_iomem + GMAC_IN_BCAST); ++ gmac->hw_stats[4] += readl(gmac->ctl_iomem + GMAC_IN_MAC1); ++ gmac->hw_stats[5] += readl(gmac->ctl_iomem + GMAC_IN_MAC2); ++ ++ gmac->stats.rx_missed_errors += rx_discards; ++ gmac->stats.multicast += rx_mcast; ++ gmac->stats.multicast += rx_bcast; ++ ++ writel(GMAC0_MIB_INT_BIT << (dev->dev_id * 8), ++ toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG); ++ ++ u64_stats_update_end(&gmac->ir_stats_syncp); ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++} ++ ++static inline unsigned gmac_get_intr_flags(struct net_device *dev, int i) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ void __iomem *irqif_reg, *irqen_reg; ++ unsigned offs, val; ++ ++ offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG - GLOBAL_INTERRUPT_STATUS_0_REG); ++ ++ irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG + offs; ++ irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG + offs; ++ ++ val = readl(irqif_reg) & readl(irqen_reg); ++ return val; ++} ++ ++enum hrtimer_restart gmac_coalesce_delay_expired( struct hrtimer *timer ) ++{ ++ struct gmac_private *gmac = container_of(timer, struct gmac_private, rx_coalesce_timer); ++ ++ napi_schedule(&gmac->napi); ++ return HRTIMER_NORESTART; ++} ++ ++static irqreturn_t gmac_irq(int irq, void *data) ++{ ++ struct net_device *dev = data; ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ unsigned val, orr = 0; ++ ++ orr |= val = gmac_get_intr_flags(dev, 0); ++ ++ if (unlikely(val & (GMAC0_IRQ0_2 << (dev->dev_id * 2)))) { ++ /* oh, crap. */ ++ netdev_err(dev, "hw failure/sw bug\n"); ++ gmac_dump_dma_state(dev); ++ ++ /* don't know how to recover, just reduce losses */ ++ gmac_enable_irq(dev, 0); ++ return IRQ_HANDLED; ++ } ++ ++ if (val & (GMAC0_IRQ0_TXQ0_INTS << (dev->dev_id * 6))) ++ gmac_tx_irq(dev, 0); ++ ++ orr |= val = gmac_get_intr_flags(dev, 1); ++ ++ if (val & (DEFAULT_Q0_INT_BIT << dev->dev_id)) { ++ ++ gmac_enable_rx_irq(dev, 0); ++ ++ if (!gmac->rx_coalesce_nsecs) ++ napi_schedule(&gmac->napi); ++ else { ++ ktime_t ktime; ++ ktime = ktime_set(0, gmac->rx_coalesce_nsecs); ++ hrtimer_start(&gmac->rx_coalesce_timer, ktime, HRTIMER_MODE_REL); ++ } ++ } ++ ++ orr |= val = gmac_get_intr_flags(dev, 4); ++ ++ if (unlikely(val & (GMAC0_MIB_INT_BIT << (dev->dev_id * 8)))) ++ gmac_update_hw_stats(dev); ++ ++ if (unlikely(val & (GMAC0_RX_OVERRUN_INT_BIT << (dev->dev_id * 8)))) { ++ writel(GMAC0_RXDERR_INT_BIT << (dev->dev_id * 8), ++ toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG); ++ ++ spin_lock(&toe->irq_lock); ++ u64_stats_update_begin(&gmac->ir_stats_syncp); ++ ++gmac->stats.rx_fifo_errors; ++ u64_stats_update_end(&gmac->ir_stats_syncp); ++ spin_unlock(&toe->irq_lock); ++ } ++ ++ return orr ? IRQ_HANDLED : IRQ_NONE; ++} ++ ++static void gmac_start_dma(struct gmac_private *gmac) ++{ ++ void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG; ++ GMAC_DMA_CTRL_T dma_ctrl; ++ ++ dma_ctrl.bits32 = readl(dma_ctrl_reg); ++ dma_ctrl.bits.rd_enable = 1; ++ dma_ctrl.bits.td_enable = 1; ++ dma_ctrl.bits.loopback = 0; ++ dma_ctrl.bits.drop_small_ack = 0; ++ dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN; ++ dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED; ++ dma_ctrl.bits.rd_burst_size = HBURST_INCR8; ++ dma_ctrl.bits.rd_bus = HSIZE_8; ++ dma_ctrl.bits.td_prot = HPROT_DATA_CACHE; ++ dma_ctrl.bits.td_burst_size = HBURST_INCR8; ++ dma_ctrl.bits.td_bus = HSIZE_8; ++ ++ writel(dma_ctrl.bits32, dma_ctrl_reg); ++} ++ ++static void gmac_stop_dma(struct gmac_private *gmac) ++{ ++ void __iomem *dma_ctrl_reg = gmac->dma_iomem + GMAC_DMA_CTRL_REG; ++ GMAC_DMA_CTRL_T dma_ctrl; ++ ++ dma_ctrl.bits32 = readl(dma_ctrl_reg); ++ dma_ctrl.bits.rd_enable = 0; ++ dma_ctrl.bits.td_enable = 0; ++ writel(dma_ctrl.bits32, dma_ctrl_reg); ++} ++ ++static int gmac_open(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ int err; ++ ++ if (!dev->phydev) { ++ err = gmac_setup_phy(dev); ++ if (err) { ++ netif_err(gmac, ifup, dev, ++ "PHY init failed: %d\n", err); ++ return err; ++ } ++ } ++ ++ err = request_irq(dev->irq, gmac_irq, ++ IRQF_SHARED, dev->name, dev); ++ if (unlikely(err)) ++ return err; ++ ++ netif_carrier_off(dev); ++ phy_start(dev->phydev); ++ ++ err = toe_resize_freeq(gmac->toe, dev->dev_id); ++ if (unlikely(err)) ++ goto err_stop_phy; ++ ++ err = gmac_setup_rxq(dev); ++ if (unlikely(err)) ++ goto err_stop_phy; ++ ++ err = gmac_setup_txqs(dev); ++ if (unlikely(err)) { ++ gmac_cleanup_rxq(dev); ++ goto err_stop_phy; ++ } ++ ++ napi_enable(&gmac->napi); ++ ++ gmac_start_dma(gmac); ++ gmac_enable_irq(dev, 1); ++ gmac_enable_tx_rx(dev); ++ netif_tx_start_all_queues(dev); ++ ++ hrtimer_init(&gmac->rx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); ++ gmac->rx_coalesce_timer.function = &gmac_coalesce_delay_expired; ++ return 0; ++ ++err_stop_phy: ++ phy_stop(dev->phydev); ++ free_irq(dev->irq, dev); ++ return err; ++} ++ ++static int gmac_stop(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ hrtimer_cancel(&gmac->rx_coalesce_timer); ++ netif_tx_stop_all_queues(dev); ++ gmac_disable_tx_rx(dev); ++ gmac_stop_dma(gmac); ++ napi_disable(&gmac->napi); ++ ++ gmac_enable_irq(dev, 0); ++ gmac_cleanup_rxq(dev); ++ gmac_cleanup_txqs(dev); ++ ++ phy_stop(dev->phydev); ++ free_irq(dev->irq, dev); ++ ++ gmac_update_hw_stats(dev); ++ return 0; ++} ++ ++static void gmac_set_rx_mode(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct netdev_hw_addr *ha; ++ __u32 mc_filter[2]; ++ unsigned bit_nr; ++ GMAC_RX_FLTR_T filter = { .bits = { ++ .broadcast = 1, ++ .multicast = 1, ++ .unicast = 1, ++ } }; ++ ++ mc_filter[1] = mc_filter[0] = 0; ++ ++ if (dev->flags & IFF_PROMISC) { ++ filter.bits.error = 1; ++ filter.bits.promiscuous = 1; ++ } else if (!(dev->flags & IFF_ALLMULTI)) { ++ mc_filter[1] = mc_filter[0] = 0; ++ netdev_for_each_mc_addr(ha, dev) { ++ bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f; ++ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f); ++ } ++ } ++ ++ writel(mc_filter[0], gmac->ctl_iomem + GMAC_MCAST_FIL0); ++ writel(mc_filter[1], gmac->ctl_iomem + GMAC_MCAST_FIL1); ++ writel(filter.bits32, gmac->ctl_iomem + GMAC_RX_FLTR); ++} ++ ++static void __gmac_set_mac_address(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ __le32 addr[3]; ++ ++ memset(addr, 0, sizeof(addr)); ++ memcpy(addr, dev->dev_addr, ETH_ALEN); ++ ++ writel(le32_to_cpu(addr[0]), gmac->ctl_iomem + GMAC_STA_ADD0); ++ writel(le32_to_cpu(addr[1]), gmac->ctl_iomem + GMAC_STA_ADD1); ++ writel(le32_to_cpu(addr[2]), gmac->ctl_iomem + GMAC_STA_ADD2); ++} ++ ++static int gmac_set_mac_address(struct net_device *dev, void *addr) ++{ ++ struct sockaddr *sa = addr; ++ ++ memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); ++ __gmac_set_mac_address(dev); ++ ++ return 0; ++} ++ ++static void gmac_clear_hw_stats(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ readl(gmac->ctl_iomem + GMAC_IN_DISCARDS); ++ readl(gmac->ctl_iomem + GMAC_IN_ERRORS); ++ readl(gmac->ctl_iomem + GMAC_IN_MCAST); ++ readl(gmac->ctl_iomem + GMAC_IN_BCAST); ++ readl(gmac->ctl_iomem + GMAC_IN_MAC1); ++ readl(gmac->ctl_iomem + GMAC_IN_MAC2); ++} ++ ++static struct rtnl_link_stats64 *gmac_get_stats64(struct net_device *dev, ++ struct rtnl_link_stats64 *storage) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ unsigned int start; ++ ++ gmac_update_hw_stats(dev); ++ ++ /* racing with RX NAPI */ ++ do { ++ start = u64_stats_fetch_begin(&gmac->rx_stats_syncp); ++ ++ storage->rx_packets = gmac->stats.rx_packets; ++ storage->rx_bytes = gmac->stats.rx_bytes; ++ storage->rx_errors = gmac->stats.rx_errors; ++ storage->rx_dropped = gmac->stats.rx_dropped; ++ ++ storage->rx_length_errors = gmac->stats.rx_length_errors; ++ storage->rx_over_errors = gmac->stats.rx_over_errors; ++ storage->rx_crc_errors = gmac->stats.rx_crc_errors; ++ storage->rx_frame_errors = gmac->stats.rx_frame_errors; ++ ++ } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start)); ++ ++ /* racing with MIB and TX completion interrupts */ ++ do { ++ start = u64_stats_fetch_begin(&gmac->ir_stats_syncp); ++ ++ storage->tx_errors = gmac->stats.tx_errors; ++ storage->tx_packets = gmac->stats.tx_packets; ++ storage->tx_bytes = gmac->stats.tx_bytes; ++ ++ storage->multicast = gmac->stats.multicast; ++ storage->rx_missed_errors = gmac->stats.rx_missed_errors; ++ storage->rx_fifo_errors = gmac->stats.rx_fifo_errors; ++ ++ } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start)); ++ ++ /* racing with hard_start_xmit */ ++ do { ++ start = u64_stats_fetch_begin(&gmac->tx_stats_syncp); ++ ++ storage->tx_dropped = gmac->stats.tx_dropped; ++ ++ } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start)); ++ ++ storage->rx_dropped += storage->rx_missed_errors; ++ ++ return storage; ++} ++ ++static int gmac_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ int max_len = gmac_pick_rx_max_len(new_mtu); ++ ++ if (max_len < 0) ++ return -EINVAL; ++ ++ gmac_disable_tx_rx(dev); ++ ++ dev->mtu = new_mtu; ++ gmac_update_config0_reg(dev, ++ max_len << CONFIG0_MAXLEN_SHIFT, ++ CONFIG0_MAXLEN_MASK); ++ ++ netdev_update_features(dev); ++ ++ gmac_enable_tx_rx(dev); ++ ++ return 0; ++} ++ ++static netdev_features_t gmac_fix_features(struct net_device *dev, netdev_features_t features) ++{ ++ if (dev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK) ++ features &= ~GMAC_OFFLOAD_FEATURES; ++ ++ return features; ++} ++ ++static int gmac_set_features(struct net_device *dev, netdev_features_t features) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ int enable = features & NETIF_F_RXCSUM; ++ unsigned long flags; ++ u32 reg; ++ ++ spin_lock_irqsave(&gmac->config_lock, flags); ++ ++ reg = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM; ++ writel(reg, gmac->ctl_iomem + GMAC_CONFIG0); ++ ++ spin_unlock_irqrestore(&gmac->config_lock, flags); ++ return 0; ++} ++ ++static int gmac_get_sset_count(struct net_device *dev, int sset) ++{ ++ return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0; ++} ++ ++static void gmac_get_strings(struct net_device *dev, u32 stringset, u8 *data) ++{ ++ if (stringset != ETH_SS_STATS) ++ return; ++ ++ memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings)); ++} ++ ++static void gmac_get_ethtool_stats(struct net_device *dev, ++ struct ethtool_stats *estats, u64 *values) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ unsigned int start; ++ u64 *p; ++ int i; ++ ++ gmac_update_hw_stats(dev); ++ ++ /* racing with MIB interrupt */ ++ do { ++ p = values; ++ start = u64_stats_fetch_begin(&gmac->ir_stats_syncp); ++ ++ for (i = 0; i < RX_STATS_NUM; ++i) ++ *p++ = gmac->hw_stats[i]; ++ ++ } while (u64_stats_fetch_retry(&gmac->ir_stats_syncp, start)); ++ values = p; ++ ++ /* racing with RX NAPI */ ++ do { ++ p = values; ++ start = u64_stats_fetch_begin(&gmac->rx_stats_syncp); ++ ++ for (i = 0; i < RX_STATUS_NUM; ++i) ++ *p++ = gmac->rx_stats[i]; ++ for (i = 0; i < RX_CHKSUM_NUM; ++i) ++ *p++ = gmac->rx_csum_stats[i]; ++ *p++ = gmac->rx_napi_exits; ++ ++ } while (u64_stats_fetch_retry(&gmac->rx_stats_syncp, start)); ++ values = p; ++ ++ /* racing with TX start_xmit */ ++ do { ++ p = values; ++ start = u64_stats_fetch_begin(&gmac->tx_stats_syncp); ++ ++ for (i = 0; i < TX_MAX_FRAGS; ++i) { ++ *values++ = gmac->tx_frag_stats[i]; ++ gmac->tx_frag_stats[i] = 0; ++ } ++ *values++ = gmac->tx_frags_linearized; ++ *values++ = gmac->tx_hw_csummed; ++ ++ } while (u64_stats_fetch_retry(&gmac->tx_stats_syncp, start)); ++} ++ ++static int gmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ if (!dev->phydev) ++ return -ENXIO; ++ return phy_ethtool_gset(dev->phydev, cmd); ++} ++ ++static int gmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ if (!dev->phydev) ++ return -ENXIO; ++ return phy_ethtool_sset(dev->phydev, cmd); ++} ++ ++static int gmac_nway_reset(struct net_device *dev) ++{ ++ if (!dev->phydev) ++ return -ENXIO; ++ return phy_start_aneg(dev->phydev); ++} ++ ++static void gmac_get_pauseparam(struct net_device *dev, ++ struct ethtool_pauseparam *pparam) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ GMAC_CONFIG0_T config0; ++ ++ config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ ++ pparam->rx_pause = config0.bits.rx_fc_en; ++ pparam->tx_pause = config0.bits.tx_fc_en; ++ pparam->autoneg = true; ++} ++ ++static void gmac_get_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *rp) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ GMAC_CONFIG0_T config0; ++ ++ config0.bits32 = readl(gmac->ctl_iomem + GMAC_CONFIG0); ++ ++ rp->rx_max_pending = 1 << 15; ++ rp->rx_mini_max_pending = 0; ++ rp->rx_jumbo_max_pending = 0; ++ rp->tx_max_pending = 1 << 15; ++ ++ rp->rx_pending = 1 << gmac->rxq_order; ++ rp->rx_mini_pending = 0; ++ rp->rx_jumbo_pending = 0; ++ rp->tx_pending = 1 << gmac->txq_order; ++} ++ ++static int toe_resize_freeq(struct toe_private *toe, int changing_dev_id); ++ ++static int gmac_set_ringparam(struct net_device *dev, ++ struct ethtool_ringparam *rp) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ struct toe_private *toe = gmac->toe; ++ int err = 0; ++ ++ if (netif_running(dev)) ++ return -EBUSY; ++ ++ if (rp->rx_pending) { ++ gmac->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1); ++ err = toe_resize_freeq(toe, dev->dev_id); ++ } ++ ++ if (rp->tx_pending) ++ { ++ gmac->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1); ++ gmac->irq_every_tx_packets = 1 << (gmac->txq_order - 2); ++ } ++ ++ return err; ++} ++ ++static int gmac_get_coalesce(struct net_device *dev, ++ struct ethtool_coalesce *ecmd) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ ecmd->rx_max_coalesced_frames = 1; ++ ecmd->tx_max_coalesced_frames = gmac->irq_every_tx_packets; ++ ecmd->rx_coalesce_usecs = gmac->rx_coalesce_nsecs/1000; ++ ++ return 0; ++} ++ ++static int gmac_set_coalesce(struct net_device *dev, ++ struct ethtool_coalesce *ecmd) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ ++ if (ecmd->tx_max_coalesced_frames < 1) ++ return -EINVAL; ++ if (ecmd->tx_max_coalesced_frames >= 1 << gmac->txq_order) ++ return -EINVAL; ++ ++ gmac->irq_every_tx_packets = ecmd->tx_max_coalesced_frames; ++ gmac->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000; ++ ++ return 0; ++} ++ ++static u32 gmac_get_msglevel(struct net_device *dev) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ return gmac->msg_enable; ++} ++ ++static void gmac_set_msglevel(struct net_device *dev, u32 level) ++{ ++ struct gmac_private *gmac = netdev_priv(dev); ++ gmac->msg_enable = level; ++} ++ ++static void gmac_get_drvinfo(struct net_device *dev, ++ struct ethtool_drvinfo *info) ++{ ++ strcpy(info->driver, DRV_NAME); ++ strcpy(info->version, DRV_VERSION); ++ strcpy(info->bus_info, dev->dev_id ? "1" : "0"); ++} ++ ++static const struct net_device_ops gmac_351x_ops = { ++ .ndo_init = gmac_init, ++ .ndo_uninit = gmac_uninit, ++ .ndo_open = gmac_open, ++ .ndo_stop = gmac_stop, ++ .ndo_start_xmit = gmac_start_xmit, ++ .ndo_tx_timeout = gmac_tx_timeout, ++ .ndo_set_rx_mode = gmac_set_rx_mode, ++ .ndo_set_mac_address = gmac_set_mac_address, ++ .ndo_get_stats64 = gmac_get_stats64, ++ .ndo_change_mtu = gmac_change_mtu, ++ .ndo_fix_features = gmac_fix_features, ++ .ndo_set_features = gmac_set_features, ++}; ++ ++static const struct ethtool_ops gmac_351x_ethtool_ops = { ++ .get_sset_count = gmac_get_sset_count, ++ .get_strings = gmac_get_strings, ++ .get_ethtool_stats = gmac_get_ethtool_stats, ++ .get_settings = gmac_get_settings, ++ .set_settings = gmac_set_settings, ++ .get_link = ethtool_op_get_link, ++ .nway_reset = gmac_nway_reset, ++ .get_pauseparam = gmac_get_pauseparam, ++ .get_ringparam = gmac_get_ringparam, ++ .set_ringparam = gmac_set_ringparam, ++ .get_coalesce = gmac_get_coalesce, ++ .set_coalesce = gmac_set_coalesce, ++ .get_msglevel = gmac_get_msglevel, ++ .set_msglevel = gmac_set_msglevel, ++ .get_drvinfo = gmac_get_drvinfo, ++}; ++ ++static int gmac_init_netdev(struct toe_private *toe, int num, ++ struct platform_device *pdev) ++{ ++ struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data; ++ struct gmac_private *gmac; ++ struct net_device *dev; ++ int irq, err; ++ ++ if (!pdata->bus_id[num]) ++ return 0; ++ ++ irq = platform_get_irq(pdev, num); ++ if (irq < 0) { ++ dev_err(toe->dev, "No IRQ for ethernet device #%d\n", num); ++ return irq; ++ } ++ ++ dev = alloc_etherdev_mq(sizeof(*gmac), TX_QUEUE_NUM); ++ if (!dev) { ++ dev_err(toe->dev, "Can't allocate ethernet device #%d\n", num); ++ return -ENOMEM; ++ } ++ ++ gmac = netdev_priv(dev); ++ gmac->num = num; ++ gmac->toe = toe; ++ SET_NETDEV_DEV(dev, toe->dev); ++ ++ toe->netdev[num] = dev; ++ dev->dev_id = num; ++ ++ gmac->ctl_iomem = toe->iomem + TOE_GMAC_BASE(num); ++ gmac->dma_iomem = toe->iomem + TOE_GMAC_DMA_BASE(num); ++ dev->irq = irq; ++ ++ dev->netdev_ops = &gmac_351x_ops; ++ dev->ethtool_ops = &gmac_351x_ethtool_ops; ++ ++ spin_lock_init(&gmac->config_lock); ++ gmac_clear_hw_stats(dev); ++ ++ dev->hw_features = GMAC_OFFLOAD_FEATURES; ++ dev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO; ++ ++ gmac->freeq_refill = 0; ++ netif_napi_add(dev, &gmac->napi, gmac_napi_poll, DEFAULT_NAPI_WEIGHT); ++ ++ if (is_valid_ether_addr((void *)toe->mac_addr[num])) ++ memcpy(dev->dev_addr, toe->mac_addr[num], ETH_ALEN); ++ else ++ random_ether_addr(dev->dev_addr); ++ __gmac_set_mac_address(dev); ++ ++ err = gmac_setup_phy(dev); ++ if (err) ++ netif_warn(gmac, probe, dev, ++ "PHY init failed: %d, deferring to ifup time\n", err); ++ ++ err = register_netdev(dev); ++ if (!err) ++ { ++ pr_info(DRV_NAME " %s: irq %d, dma base 0x%p, io base 0x%p\n", ++ dev->name, irq, gmac->dma_iomem, gmac->ctl_iomem); ++ return 0; ++ } ++ ++ toe->netdev[num] = NULL; ++ free_netdev(dev); ++ return err; ++} ++ ++static irqreturn_t toe_irq_thread(int irq, void *data) ++{ ++ struct toe_private *toe = data; ++ void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG; ++ void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG; ++ unsigned long irqmask = SWFQ_EMPTY_INT_BIT; ++ unsigned long flags; ++ ++ toe_fill_freeq(toe, 0); ++ ++ /* Ack and enable interrupt */ ++ spin_lock_irqsave(&toe->irq_lock, flags); ++ writel(irqmask, irqif_reg); ++ irqmask |= readl(irqen_reg); ++ writel(irqmask, irqen_reg); ++ spin_unlock_irqrestore(&toe->irq_lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t toe_irq(int irq, void *data) ++{ ++ struct toe_private *toe = data; ++ void __iomem *irqif_reg = toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG; ++ void __iomem *irqen_reg = toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG; ++ unsigned long val, en; ++ irqreturn_t ret = IRQ_NONE; ++ ++ spin_lock(&toe->irq_lock); ++ ++ val = readl(irqif_reg); ++ en = readl(irqen_reg); ++ ++ if (val & en & SWFQ_EMPTY_INT_BIT) { ++ en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT ++ | GMAC1_RX_OVERRUN_INT_BIT); ++ writel(en, irqen_reg); ++ ret = IRQ_WAKE_THREAD; ++ } ++ ++ spin_unlock(&toe->irq_lock); ++ return ret; ++} ++ ++static int toe_init(struct toe_private *toe, ++ struct platform_device *pdev) ++{ ++ int err; ++ ++ writel(0, toe->iomem + GLOBAL_SW_FREEQ_BASE_SIZE_REG); ++ writel(0, toe->iomem + GLOBAL_HW_FREEQ_BASE_SIZE_REG); ++ writel(0, toe->iomem + GLOBAL_SWFQ_RWPTR_REG); ++ writel(0, toe->iomem + GLOBAL_HWFQ_RWPTR_REG); ++ ++ toe->freeq_frag_order = DEFAULT_RX_BUF_ORDER; ++ toe->freeq_order = ~0; ++ ++ err = request_threaded_irq(toe->irq, toe_irq, ++ toe_irq_thread, IRQF_SHARED, DRV_NAME " toe", toe); ++ if (err) ++ goto err_freeq; ++ ++ return 0; ++ ++err_freeq: ++ toe_cleanup_freeq(toe); ++ return err; ++} ++ ++static void toe_deinit(struct toe_private *toe) ++{ ++ free_irq(toe->irq, toe); ++ toe_cleanup_freeq(toe); ++} ++ ++static int toe_reset(struct toe_private *toe) ++{ ++ unsigned int reg = 0, retry = 5; ++ ++ reg = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_RESET)); ++ reg |= RESET_GMAC1 | RESET_GMAC0; ++ writel(reg, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_RESET)); ++ ++ do { ++ udelay(2); ++ reg = readl((void __iomem*)(toe->iomem + ++ GLOBAL_TOE_VERSION_REG)); ++ barrier(); ++ } while (!reg && --retry); ++ ++ return reg ? 0 : -EIO; ++} ++ ++/* ++ * Interrupt config: ++ * ++ * GMAC0 intr bits ------> int0 ----> eth0 ++ * GMAC1 intr bits ------> int1 ----> eth1 ++ * TOE intr -------------> int1 ----> eth1 ++ * Classification Intr --> int0 ----> eth0 ++ * Default Q0 -----------> int0 ----> eth0 ++ * Default Q1 -----------> int1 ----> eth1 ++ * FreeQ intr -----------> int1 ----> eth1 ++ */ ++static void toe_init_irq(struct toe_private *toe) ++{ ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_0_REG); ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_1_REG); ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_2_REG); ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_3_REG); ++ writel(0, toe->iomem + GLOBAL_INTERRUPT_ENABLE_4_REG); ++ ++ writel(0xCCFC0FC0, toe->iomem + GLOBAL_INTERRUPT_SELECT_0_REG); ++ writel(0x00F00002, toe->iomem + GLOBAL_INTERRUPT_SELECT_1_REG); ++ writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_2_REG); ++ writel(0xFFFFFFFF, toe->iomem + GLOBAL_INTERRUPT_SELECT_3_REG); ++ writel(0xFF000003, toe->iomem + GLOBAL_INTERRUPT_SELECT_4_REG); ++ ++ /* edge-triggered interrupts packed to level-triggered one... */ ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_0_REG); ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_1_REG); ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_2_REG); ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_3_REG); ++ writel(~0, toe->iomem + GLOBAL_INTERRUPT_STATUS_4_REG); ++} ++ ++static void toe_save_mac_addr(struct toe_private *toe, ++ struct platform_device *pdev) ++{ ++ struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data; ++ void __iomem *ctl; ++ int i; ++ ++ for (i = 0; i < 2; i++) { ++ if (pdata->bus_id[i]) { ++ ctl = toe->iomem + TOE_GMAC_BASE(i); ++ toe->mac_addr[i][0] = cpu_to_le32(readl(ctl + GMAC_STA_ADD0)); ++ toe->mac_addr[i][1] = cpu_to_le32(readl(ctl + GMAC_STA_ADD1)); ++ toe->mac_addr[i][2] = cpu_to_le32(readl(ctl + GMAC_STA_ADD2)); ++ } ++ } ++} ++ ++static int gemini_gmac_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct toe_private *toe; ++ int irq, retval; ++ ++ if (!pdev->dev.platform_data) ++ return -EINVAL; ++ ++ irq = platform_get_irq(pdev, 1); ++ if (irq < 0) ++ return irq; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "can't get device resources\n"); ++ return -ENODEV; ++ } ++ ++ toe = kzalloc(sizeof(*toe), GFP_KERNEL); ++ if (!toe) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, toe); ++ toe->dev = &pdev->dev; ++ toe->irq = irq; ++ ++ toe->iomem = ioremap(res->start, resource_size(res)); ++ if (!toe->iomem) { ++ dev_err(toe->dev, "ioremap failed\n"); ++ retval = -EIO; ++ goto err_data; ++ } ++ ++ toe_save_mac_addr(toe, pdev); ++ ++ retval = toe_reset(toe); ++ if (retval < 0) ++ goto err_unmap; ++ ++ pr_info(DRV_NAME " toe: irq %d, io base 0x%08x, version %d\n", ++ irq, res->start, retval); ++ ++ spin_lock_init(&toe->irq_lock); ++ spin_lock_init(&toe->freeq_lock); ++ ++ toe_init_irq(toe); ++ ++ retval = toe_init(toe, pdev); ++ if (retval) ++ goto err_unmap; ++ ++ retval = gmac_init_netdev(toe, 0, pdev); ++ if (retval) ++ goto err_uninit; ++ ++ retval = gmac_init_netdev(toe, 1, pdev); ++ if (retval) ++ goto err_uninit; ++ ++ return 0; ++ ++err_uninit: ++ if (toe->netdev[0]) ++ unregister_netdev(toe->netdev[0]); ++ toe_deinit(toe); ++err_unmap: ++ iounmap(toe->iomem); ++err_data: ++ kfree(toe); ++ return retval; ++} ++ ++static int gemini_gmac_remove(struct platform_device *pdev) ++{ ++ struct toe_private *toe = platform_get_drvdata(pdev); ++ int i; ++ ++ for (i = 0; i < 2; i++) ++ if (toe->netdev[i]) ++ unregister_netdev(toe->netdev[i]); ++ ++ toe_init_irq(toe); ++ toe_deinit(toe); ++ ++ iounmap(toe->iomem); ++ kfree(toe); ++ ++ return 0; ++} ++ ++static struct platform_driver gemini_gmac_driver = { ++ .probe = gemini_gmac_probe, ++ .remove = gemini_gmac_remove, ++ .driver.name = DRV_NAME, ++ .driver.owner = THIS_MODULE, ++}; ++ ++static int __init gemini_gmac_init(void) ++{ ++#ifdef CONFIG_MDIO_GPIO_MODULE ++ request_module("mdio-gpio"); ++#endif ++ return platform_driver_register(&gemini_gmac_driver); ++} ++ ++static void __exit gemini_gmac_exit(void) ++{ ++ platform_driver_unregister(&gemini_gmac_driver); ++} ++ ++module_init(gemini_gmac_init); ++module_exit(gemini_gmac_exit); +--- /dev/null ++++ b/drivers/net/ethernet/gemini/sl351x_hw.h +@@ -0,0 +1,1436 @@ ++/* ++ * Register definitions for Gemini LEPUS GMAC Ethernet device driver. ++ * ++ * Copyright (C) 2006, Storlink, Corp. ++ * Copyright (C) 2008-2009, Paulius Zaleckas ++ * Copyright (C) 2010, MichaÅ‚ MirosÅ‚aw ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#ifndef _GMAC_HW_H ++#define _GMAC_HW_H ++ ++#include ++ ++/* ++ * Base Registers ++ */ ++#define TOE_NONTOE_QUE_HDR_BASE 0x2000 ++#define TOE_TOE_QUE_HDR_BASE 0x3000 ++#define TOE_V_BIT_BASE 0x4000 ++#define TOE_A_BIT_BASE 0x6000 ++#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x)) ++#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x)) ++ ++/* ++ * Queue ID ++ */ ++#define TOE_SW_FREE_QID 0x00 ++#define TOE_HW_FREE_QID 0x01 ++#define TOE_GMAC0_SW_TXQ0_QID 0x02 ++#define TOE_GMAC0_SW_TXQ1_QID 0x03 ++#define TOE_GMAC0_SW_TXQ2_QID 0x04 ++#define TOE_GMAC0_SW_TXQ3_QID 0x05 ++#define TOE_GMAC0_SW_TXQ4_QID 0x06 ++#define TOE_GMAC0_SW_TXQ5_QID 0x07 ++#define TOE_GMAC0_HW_TXQ0_QID 0x08 ++#define TOE_GMAC0_HW_TXQ1_QID 0x09 ++#define TOE_GMAC0_HW_TXQ2_QID 0x0A ++#define TOE_GMAC0_HW_TXQ3_QID 0x0B ++#define TOE_GMAC1_SW_TXQ0_QID 0x12 ++#define TOE_GMAC1_SW_TXQ1_QID 0x13 ++#define TOE_GMAC1_SW_TXQ2_QID 0x14 ++#define TOE_GMAC1_SW_TXQ3_QID 0x15 ++#define TOE_GMAC1_SW_TXQ4_QID 0x16 ++#define TOE_GMAC1_SW_TXQ5_QID 0x17 ++#define TOE_GMAC1_HW_TXQ0_QID 0x18 ++#define TOE_GMAC1_HW_TXQ1_QID 0x19 ++#define TOE_GMAC1_HW_TXQ2_QID 0x1A ++#define TOE_GMAC1_HW_TXQ3_QID 0x1B ++#define TOE_GMAC0_DEFAULT_QID 0x20 ++#define TOE_GMAC1_DEFAULT_QID 0x21 ++#define TOE_CLASSIFICATION_QID(x) (0x22 + x) /* 0x22 ~ 0x2F */ ++#define TOE_TOE_QID(x) (0x40 + x) /* 0x40 ~ 0x7F */ ++ ++/* ++ * old info: ++ * TOE DMA Queue Size should be 2^n, n = 6...12 ++ * TOE DMA Queues are the following queue types: ++ * SW Free Queue, HW Free Queue, ++ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5 ++ * The base address and descriptor number are configured at ++ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004) ++ */ ++ ++#define GET_WPTR(addr) __raw_readw((addr) + 2) ++#define GET_RPTR(addr) __raw_readw((addr)) ++#define SET_WPTR(addr, data) __raw_writew((data), (addr) + 2) ++#define SET_RPTR(addr, data) __raw_writew((data), (addr)) ++#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask)) ++#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask)) ++#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask)) ++#define __RWPTR_MASK(order) ((1 << (order)) - 1) ++#define RWPTR_NEXT(x, order) __RWPTR_NEXT((x), __RWPTR_MASK((order))) ++#define RWPTR_PREV(x, order) __RWPTR_PREV((x), __RWPTR_MASK((order))) ++#define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \ ++ __RWPTR_MASK((order))) ++ ++/* ++ * Global registers ++ * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000) ++ * Base 0x60000000 ++ */ ++#define GLOBAL_TOE_VERSION_REG 0x0000 ++#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004 ++#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008 ++#define GLOBAL_DMA_SKB_SIZE_REG 0x0010 ++#define GLOBAL_SWFQ_RWPTR_REG 0x0014 ++#define GLOBAL_HWFQ_RWPTR_REG 0x0018 ++#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020 ++#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024 ++#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028 ++#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030 ++#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034 ++#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038 ++#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040 ++#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044 ++#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048 ++#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050 ++#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054 ++#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058 ++#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060 ++#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064 ++#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068 ++#define GLOBAL_HASH_TABLE_BASE_REG 0x006C ++#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070 ++ ++/* ++ * GMAC 0/1 DMA/TOE register ++ * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000) ++ * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000) ++ * Base 0x60008000 or 0x6000C000 ++ */ ++#define GMAC_DMA_CTRL_REG 0x0000 ++#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004 ++#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008 ++#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C ++#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010 ++#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014 ++#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018 ++#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C ++#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020 ++#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i)) ++#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024 ++#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028 ++#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C ++#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030 ++#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i)) ++#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038 ++#define GMAC_DMA_TX_CURR_DESC_REG 0x003C ++#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040 ++#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044 ++#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048 ++#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C ++#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050 ++#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054 ++#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058 ++#define GMAC_DMA_RX_CURR_DESC_REG 0x005C ++#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060 ++#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064 ++#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068 ++#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C ++#define GMAC_HASH_ENGINE_REG0 0x0070 ++#define GMAC_HASH_ENGINE_REG1 0x0074 ++/* matching rule 0 Control register 0 */ ++#define GMAC_MR0CR0 0x0078 ++#define GMAC_MR0CR1 0x007C ++#define GMAC_MR0CR2 0x0080 ++#define GMAC_MR1CR0 0x0084 ++#define GMAC_MR1CR1 0x0088 ++#define GMAC_MR1CR2 0x008C ++#define GMAC_MR2CR0 0x0090 ++#define GMAC_MR2CR1 0x0094 ++#define GMAC_MR2CR2 0x0098 ++#define GMAC_MR3CR0 0x009C ++#define GMAC_MR3CR1 0x00A0 ++#define GMAC_MR3CR2 0x00A4 ++/* Support Protocol Regsister 0 */ ++#define GMAC_SPR0 0x00A8 ++#define GMAC_SPR1 0x00AC ++#define GMAC_SPR2 0x00B0 ++#define GMAC_SPR3 0x00B4 ++#define GMAC_SPR4 0x00B8 ++#define GMAC_SPR5 0x00BC ++#define GMAC_SPR6 0x00C0 ++#define GMAC_SPR7 0x00C4 ++/* GMAC Hash/Rx/Tx AHB Weighting register */ ++#define GMAC_AHB_WEIGHT_REG 0x00C8 ++ ++/* ++ * TOE GMAC 0/1 register ++ * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000) ++ * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000) ++ * Base 0x6000A000 or 0x6000E000 ++ */ ++enum GMAC_REGISTER { ++ GMAC_STA_ADD0 = 0x0000, ++ GMAC_STA_ADD1 = 0x0004, ++ GMAC_STA_ADD2 = 0x0008, ++ GMAC_RX_FLTR = 0x000c, ++ GMAC_MCAST_FIL0 = 0x0010, ++ GMAC_MCAST_FIL1 = 0x0014, ++ GMAC_CONFIG0 = 0x0018, ++ GMAC_CONFIG1 = 0x001c, ++ GMAC_CONFIG2 = 0x0020, ++ GMAC_CONFIG3 = 0x0024, ++ GMAC_RESERVED = 0x0028, ++ GMAC_STATUS = 0x002c, ++ GMAC_IN_DISCARDS= 0x0030, ++ GMAC_IN_ERRORS = 0x0034, ++ GMAC_IN_MCAST = 0x0038, ++ GMAC_IN_BCAST = 0x003c, ++ GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */ ++ GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */ ++}; ++ ++#define RX_STATS_NUM 6 ++ ++/* ++ * DMA Queues description Ring Base Address/Size Register (offset 0x0004) ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int base_size; ++} DMA_Q_BASE_SIZE_T; ++#define DMA_Q_BASE_MASK (~0x0f) ++ ++/* ++ * DMA SKB Buffer register (offset 0x0008) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0008 { ++ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */ ++ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */ ++ } bits; ++} DMA_SKB_SIZE_T; ++ ++/* ++ * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_000c { ++ unsigned int rptr : 16; /* Read Ptr, RO */ ++ unsigned int wptr : 16; /* Write Ptr, RW */ ++ } bits; ++} DMA_RWPTR_T; ++ ++/* ++ * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010) ++ * see DMA_RWPTR_T structure ++ */ ++ ++/* ++ * Interrupt Status Register 0 (offset 0x0020) ++ * Interrupt Mask Register 0 (offset 0x0024) ++ * Interrupt Select Register 0 (offset 0x0028) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0020 { ++ /* GMAC0 SW Tx Queue 0 EOF Interrupt */ ++ unsigned int swtq00_eof : 1; ++ unsigned int swtq01_eof : 1; ++ unsigned int swtq02_eof : 1; ++ unsigned int swtq03_eof : 1; ++ unsigned int swtq04_eof : 1; ++ unsigned int swtq05_eof : 1; ++ /* GMAC1 SW Tx Queue 0 EOF Interrupt */ ++ unsigned int swtq10_eof : 1; ++ unsigned int swtq11_eof : 1; ++ unsigned int swtq12_eof : 1; ++ unsigned int swtq13_eof : 1; ++ unsigned int swtq14_eof : 1; ++ unsigned int swtq15_eof : 1; ++ /* GMAC0 SW Tx Queue 0 Finish Interrupt */ ++ unsigned int swtq00_fin : 1; ++ unsigned int swtq01_fin : 1; ++ unsigned int swtq02_fin : 1; ++ unsigned int swtq03_fin : 1; ++ unsigned int swtq04_fin : 1; ++ unsigned int swtq05_fin : 1; ++ /* GMAC1 SW Tx Queue 0 Finish Interrupt */ ++ unsigned int swtq10_fin : 1; ++ unsigned int swtq11_fin : 1; ++ unsigned int swtq12_fin : 1; ++ unsigned int swtq13_fin : 1; ++ unsigned int swtq14_fin : 1; ++ unsigned int swtq15_fin : 1; ++ /* GMAC0 Rx Descriptor Protocol Error */ ++ unsigned int rxPerr0 : 1; ++ /* GMAC0 AHB Bus Error while Rx */ ++ unsigned int rxDerr0 : 1; ++ /* GMAC1 Rx Descriptor Protocol Error */ ++ unsigned int rxPerr1 : 1; ++ /* GMAC1 AHB Bus Error while Rx */ ++ unsigned int rxDerr1 : 1; ++ /* GMAC0 Tx Descriptor Protocol Error */ ++ unsigned int txPerr0 : 1; ++ /* GMAC0 AHB Bus Error while Tx */ ++ unsigned int txDerr0 : 1; ++ /* GMAC1 Tx Descriptor Protocol Error */ ++ unsigned int txPerr1 : 1; ++ /* GMAC1 AHB Bus Error while Tx */ ++ unsigned int txDerr1 : 1; ++ } bits; ++} INTR_REG0_T; ++ ++#define GMAC1_TXDERR_INT_BIT BIT(31) ++#define GMAC1_TXPERR_INT_BIT BIT(30) ++#define GMAC0_TXDERR_INT_BIT BIT(29) ++#define GMAC0_TXPERR_INT_BIT BIT(28) ++#define GMAC1_RXDERR_INT_BIT BIT(27) ++#define GMAC1_RXPERR_INT_BIT BIT(26) ++#define GMAC0_RXDERR_INT_BIT BIT(25) ++#define GMAC0_RXPERR_INT_BIT BIT(24) ++#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23) ++#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22) ++#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21) ++#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20) ++#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19) ++#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18) ++#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17) ++#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16) ++#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15) ++#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14) ++#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13) ++#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12) ++#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11) ++#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10) ++#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9) ++#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8) ++#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7) ++#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6) ++#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5) ++#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4) ++#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3) ++#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2) ++#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1) ++#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0) ++ ++/* ++ * Interrupt Status Register 1 (offset 0x0030) ++ * Interrupt Mask Register 1 (offset 0x0034) ++ * Interrupt Select Register 1 (offset 0x0038) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0030 { ++ unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */ ++ unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */ ++ unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */ ++ unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */ ++ unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */ ++ unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */ ++ unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */ ++ unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */ ++ unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */ ++ unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */ ++ unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */ ++ unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */ ++ unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */ ++ unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */ ++ unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */ ++ unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */ ++ unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */ ++ unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */ ++ unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */ ++ } bits; ++} INTR_REG1_T; ++ ++#define TOE_IQ3_FULL_INT_BIT BIT(31) ++#define TOE_IQ2_FULL_INT_BIT BIT(30) ++#define TOE_IQ1_FULL_INT_BIT BIT(29) ++#define TOE_IQ0_FULL_INT_BIT BIT(28) ++#define TOE_IQ3_INT_BIT BIT(27) ++#define TOE_IQ2_INT_BIT BIT(26) ++#define TOE_IQ1_INT_BIT BIT(25) ++#define TOE_IQ0_INT_BIT BIT(24) ++#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23) ++#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22) ++#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21) ++#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20) ++#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19) ++#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18) ++#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17) ++#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16) ++#define CLASS_RX_INT_BIT(x) BIT((x + 2)) ++#define DEFAULT_Q1_INT_BIT BIT(1) ++#define DEFAULT_Q0_INT_BIT BIT(0) ++ ++#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \ ++ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT) ++#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \ ++ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT) ++#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS) ++#define TOE_CLASS_RX_INT_BITS 0xfffc ++ ++/* ++ * Interrupt Status Register 2 (offset 0x0040) ++ * Interrupt Mask Register 2 (offset 0x0044) ++ * Interrupt Select Register 2 (offset 0x0048) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0040 { ++ unsigned int toe_q0_full : 1; /* bit 0 TOE Queue 0 Full Interrupt */ ++ unsigned int toe_q1_full : 1; /* bit 1 TOE Queue 1 Full Interrupt */ ++ unsigned int toe_q2_full : 1; /* bit 2 TOE Queue 2 Full Interrupt */ ++ unsigned int toe_q3_full : 1; /* bit 3 TOE Queue 3 Full Interrupt */ ++ unsigned int toe_q4_full : 1; /* bit 4 TOE Queue 4 Full Interrupt */ ++ unsigned int toe_q5_full : 1; /* bit 5 TOE Queue 5 Full Interrupt */ ++ unsigned int toe_q6_full : 1; /* bit 6 TOE Queue 6 Full Interrupt */ ++ unsigned int toe_q7_full : 1; /* bit 7 TOE Queue 7 Full Interrupt */ ++ unsigned int toe_q8_full : 1; /* bit 8 TOE Queue 8 Full Interrupt */ ++ unsigned int toe_q9_full : 1; /* bit 9 TOE Queue 9 Full Interrupt */ ++ unsigned int toe_q10_full : 1; /* bit 10 TOE Queue 10 Full Interrupt */ ++ unsigned int toe_q11_full : 1; /* bit 11 TOE Queue 11 Full Interrupt */ ++ unsigned int toe_q12_full : 1; /* bit 12 TOE Queue 12 Full Interrupt */ ++ unsigned int toe_q13_full : 1; /* bit 13 TOE Queue 13 Full Interrupt */ ++ unsigned int toe_q14_full : 1; /* bit 14 TOE Queue 14 Full Interrupt */ ++ unsigned int toe_q15_full : 1; /* bit 15 TOE Queue 15 Full Interrupt */ ++ unsigned int toe_q16_full : 1; /* bit 16 TOE Queue 16 Full Interrupt */ ++ unsigned int toe_q17_full : 1; /* bit 17 TOE Queue 17 Full Interrupt */ ++ unsigned int toe_q18_full : 1; /* bit 18 TOE Queue 18 Full Interrupt */ ++ unsigned int toe_q19_full : 1; /* bit 19 TOE Queue 19 Full Interrupt */ ++ unsigned int toe_q20_full : 1; /* bit 20 TOE Queue 20 Full Interrupt */ ++ unsigned int toe_q21_full : 1; /* bit 21 TOE Queue 21 Full Interrupt */ ++ unsigned int toe_q22_full : 1; /* bit 22 TOE Queue 22 Full Interrupt */ ++ unsigned int toe_q23_full : 1; /* bit 23 TOE Queue 23 Full Interrupt */ ++ unsigned int toe_q24_full : 1; /* bit 24 TOE Queue 24 Full Interrupt */ ++ unsigned int toe_q25_full : 1; /* bit 25 TOE Queue 25 Full Interrupt */ ++ unsigned int toe_q26_full : 1; /* bit 26 TOE Queue 26 Full Interrupt */ ++ unsigned int toe_q27_full : 1; /* bit 27 TOE Queue 27 Full Interrupt */ ++ unsigned int toe_q28_full : 1; /* bit 28 TOE Queue 28 Full Interrupt */ ++ unsigned int toe_q29_full : 1; /* bit 29 TOE Queue 29 Full Interrupt */ ++ unsigned int toe_q30_full : 1; /* bit 30 TOE Queue 30 Full Interrupt */ ++ unsigned int toe_q31_full : 1; /* bit 31 TOE Queue 31 Full Interrupt */ ++ } bits; ++} INTR_REG2_T; ++ ++#define TOE_QL_FULL_INT_BIT(x) BIT(x) ++ ++/* ++ * Interrupt Status Register 3 (offset 0x0050) ++ * Interrupt Mask Register 3 (offset 0x0054) ++ * Interrupt Select Register 3 (offset 0x0058) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0050 { ++ unsigned int toe_q32_full : 1; /* bit 32 TOE Queue 32 Full Interrupt */ ++ unsigned int toe_q33_full : 1; /* bit 33 TOE Queue 33 Full Interrupt */ ++ unsigned int toe_q34_full : 1; /* bit 34 TOE Queue 34 Full Interrupt */ ++ unsigned int toe_q35_full : 1; /* bit 35 TOE Queue 35 Full Interrupt */ ++ unsigned int toe_q36_full : 1; /* bit 36 TOE Queue 36 Full Interrupt */ ++ unsigned int toe_q37_full : 1; /* bit 37 TOE Queue 37 Full Interrupt */ ++ unsigned int toe_q38_full : 1; /* bit 38 TOE Queue 38 Full Interrupt */ ++ unsigned int toe_q39_full : 1; /* bit 39 TOE Queue 39 Full Interrupt */ ++ unsigned int toe_q40_full : 1; /* bit 40 TOE Queue 40 Full Interrupt */ ++ unsigned int toe_q41_full : 1; /* bit 41 TOE Queue 41 Full Interrupt */ ++ unsigned int toe_q42_full : 1; /* bit 42 TOE Queue 42 Full Interrupt */ ++ unsigned int toe_q43_full : 1; /* bit 43 TOE Queue 43 Full Interrupt */ ++ unsigned int toe_q44_full : 1; /* bit 44 TOE Queue 44 Full Interrupt */ ++ unsigned int toe_q45_full : 1; /* bit 45 TOE Queue 45 Full Interrupt */ ++ unsigned int toe_q46_full : 1; /* bit 46 TOE Queue 46 Full Interrupt */ ++ unsigned int toe_q47_full : 1; /* bit 47 TOE Queue 47 Full Interrupt */ ++ unsigned int toe_q48_full : 1; /* bit 48 TOE Queue 48 Full Interrupt */ ++ unsigned int toe_q49_full : 1; /* bit 49 TOE Queue 49 Full Interrupt */ ++ unsigned int toe_q50_full : 1; /* bit 50 TOE Queue 50 Full Interrupt */ ++ unsigned int toe_q51_full : 1; /* bit 51 TOE Queue 51 Full Interrupt */ ++ unsigned int toe_q52_full : 1; /* bit 52 TOE Queue 52 Full Interrupt */ ++ unsigned int toe_q53_full : 1; /* bit 53 TOE Queue 53 Full Interrupt */ ++ unsigned int toe_q54_full : 1; /* bit 54 TOE Queue 54 Full Interrupt */ ++ unsigned int toe_q55_full : 1; /* bit 55 TOE Queue 55 Full Interrupt */ ++ unsigned int toe_q56_full : 1; /* bit 56 TOE Queue 56 Full Interrupt */ ++ unsigned int toe_q57_full : 1; /* bit 57 TOE Queue 57 Full Interrupt */ ++ unsigned int toe_q58_full : 1; /* bit 58 TOE Queue 58 Full Interrupt */ ++ unsigned int toe_q59_full : 1; /* bit 59 TOE Queue 59 Full Interrupt */ ++ unsigned int toe_q60_full : 1; /* bit 60 TOE Queue 60 Full Interrupt */ ++ unsigned int toe_q61_full : 1; /* bit 61 TOE Queue 61 Full Interrupt */ ++ unsigned int toe_q62_full : 1; /* bit 62 TOE Queue 62 Full Interrupt */ ++ unsigned int toe_q63_full : 1; /* bit 63 TOE Queue 63 Full Interrupt */ ++ } bits; ++} INTR_REG3_T; ++ ++#define TOE_QH_FULL_INT_BIT(x) BIT(x-32) ++ ++/* ++ * Interrupt Status Register 4 (offset 0x0060) ++ * Interrupt Mask Register 4 (offset 0x0064) ++ * Interrupt Select Register 4 (offset 0x0068) ++ */ ++typedef union { ++ unsigned char byte; ++ struct bit_0060 { ++ unsigned char status_changed : 1; /* Status Changed Intr for RGMII Mode */ ++ unsigned char rx_overrun : 1; /* GMAC Rx FIFO overrun interrupt */ ++ unsigned char tx_pause_off : 1; /* received pause off frame interrupt */ ++ unsigned char rx_pause_off : 1; /* received pause off frame interrupt */ ++ unsigned char tx_pause_on : 1; /* transmit pause on frame interrupt */ ++ unsigned char rx_pause_on : 1; /* received pause on frame interrupt */ ++ unsigned char cnt_full : 1; /* MIB counters half full interrupt */ ++ unsigned char reserved : 1; /* */ ++ } __packed bits; ++} __packed GMAC_INTR_T; ++ ++typedef union { ++ unsigned int bits32; ++ struct bit_0060_2 { ++ unsigned int swfq_empty : 1; /* bit 0 Software Free Queue Empty Intr. */ ++ unsigned int hwfq_empty : 1; /* bit 1 Hardware Free Queue Empty Intr. */ ++ unsigned int class_qf_int : 14; /* bit 15:2 Classification Rx Queue13-0 Full Intr. */ ++ GMAC_INTR_T gmac0; ++ GMAC_INTR_T gmac1; ++ } bits; ++} INTR_REG4_T; ++ ++#define GMAC1_RESERVED_INT_BIT BIT(31) ++#define GMAC1_MIB_INT_BIT BIT(30) ++#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29) ++#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28) ++#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27) ++#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26) ++#define GMAC1_RX_OVERRUN_INT_BIT BIT(25) ++#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24) ++#define GMAC0_RESERVED_INT_BIT BIT(23) ++#define GMAC0_MIB_INT_BIT BIT(22) ++#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21) ++#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20) ++#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19) ++#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18) ++#define GMAC0_RX_OVERRUN_INT_BIT BIT(17) ++#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16) ++#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2)) ++#define HWFQ_EMPTY_INT_BIT BIT(1) ++#define SWFQ_EMPTY_INT_BIT BIT(0) ++ ++#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \ ++ GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \ ++ GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \ ++ GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT) ++#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \ ++ GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \ ++ GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \ ++ GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT) ++ ++#define CLASS_RX_FULL_INT_BITS 0xfffc ++ ++/* ++ * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070) ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_0070_2 { ++ unsigned int swfq_empty : 8; /* 7:0 Software Free Queue Empty Threshold */ ++ unsigned int hwfq_empty : 8; /* 15:8 Hardware Free Queue Empty Threshold */ ++ unsigned int intrq : 8; /* 23:16 */ ++ unsigned int toe_class : 8; /* 31:24 */ ++ } bits; ++} QUEUE_THRESHOLD_T; ++ ++ ++/* ++ * GMAC DMA Control Register ++ * GMAC0 offset 0x8000 ++ * GMAC1 offset 0xC000 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8000 { ++ unsigned int td_bus : 2; /* bit 1:0 Peripheral Bus Width */ ++ unsigned int td_burst_size : 2; /* bit 3:2 TxDMA max burst size for every AHB request */ ++ unsigned int td_prot : 4; /* bit 7:4 TxDMA protection control */ ++ unsigned int rd_bus : 2; /* bit 9:8 Peripheral Bus Width */ ++ unsigned int rd_burst_size : 2; /* bit 11:10 DMA max burst size for every AHB request */ ++ unsigned int rd_prot : 4; /* bit 15:12 DMA Protection Control */ ++ unsigned int rd_insert_bytes : 2; /* bit 17:16 */ ++ unsigned int reserved : 10; /* bit 27:18 */ ++ unsigned int drop_small_ack : 1; /* bit 28 1: Drop, 0: Accept */ ++ unsigned int loopback : 1; /* bit 29 Loopback TxDMA to RxDMA */ ++ unsigned int td_enable : 1; /* bit 30 Tx DMA Enable */ ++ unsigned int rd_enable : 1; /* bit 31 Rx DMA Enable */ ++ } bits; ++} GMAC_DMA_CTRL_T; ++ ++/* ++ * GMAC Tx Weighting Control Register 0 ++ * GMAC0 offset 0x8004 ++ * GMAC1 offset 0xC004 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8004 { ++ unsigned int hw_tq0 : 6; /* bit 5:0 HW TX Queue 3 */ ++ unsigned int hw_tq1 : 6; /* bit 11:6 HW TX Queue 2 */ ++ unsigned int hw_tq2 : 6; /* bit 17:12 HW TX Queue 1 */ ++ unsigned int hw_tq3 : 6; /* bit 23:18 HW TX Queue 0 */ ++ unsigned int reserved : 8; /* bit 31:24 */ ++ } bits; ++} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */ ++ ++/* ++ * GMAC Tx Weighting Control Register 1 ++ * GMAC0 offset 0x8008 ++ * GMAC1 offset 0xC008 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8008 { ++ unsigned int sw_tq0 : 5; /* bit 4:0 SW TX Queue 0 */ ++ unsigned int sw_tq1 : 5; /* bit 9:5 SW TX Queue 1 */ ++ unsigned int sw_tq2 : 5; /* bit 14:10 SW TX Queue 2 */ ++ unsigned int sw_tq3 : 5; /* bit 19:15 SW TX Queue 3 */ ++ unsigned int sw_tq4 : 5; /* bit 24:20 SW TX Queue 4 */ ++ unsigned int sw_tq5 : 5; /* bit 29:25 SW TX Queue 5 */ ++ unsigned int reserved : 2; /* bit 31:30 */ ++ } bits; ++} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */ ++ ++/* ++ * Queue Read/Write Pointer ++ * GMAC SW TX Queue 0~5 Read/Write Pointer register ++ * GMAC0 offset 0x800C ~ 0x8020 ++ * GMAC1 offset 0xC00C ~ 0xC020 ++ * GMAC HW TX Queue 0~3 Read/Write Pointer register ++ * GMAC0 offset 0x8024 ~ 0x8030 ++ * GMAC1 offset 0xC024 ~ 0xC030 ++ * ++ * see DMA_RWPTR_T structure ++ */ ++ ++/* ++ * GMAC DMA Tx First Description Address Register ++ * GMAC0 offset 0x8038 ++ * GMAC1 offset 0xC038 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8038 { ++ unsigned int reserved : 3; ++ unsigned int td_busy : 1; /* bit 3 1: TxDMA busy; 0: TxDMA idle */ ++ unsigned int td_first_des_ptr : 28; /* bit 31:4 first descriptor address */ ++ } bits; ++} GMAC_TXDMA_FIRST_DESC_T; ++ ++/* ++ * GMAC DMA Tx Current Description Address Register ++ * GMAC0 offset 0x803C ++ * GMAC1 offset 0xC03C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_803C { ++ unsigned int reserved : 4; ++ unsigned int td_curr_desc_ptr : 28; /* bit 31:4 current descriptor address */ ++ } bits; ++} GMAC_TXDMA_CURR_DESC_T; ++ ++/* ++ * GMAC DMA Tx Description Word 0 Register ++ * GMAC0 offset 0x8040 ++ * GMAC1 offset 0xC040 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8040 { ++ unsigned int buffer_size : 16; /* bit 15:0 Transfer size */ ++ unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */ ++ unsigned int status_tx_ok : 1; /* bit 22 Tx Status, 1: Successful 0: Failed */ ++ unsigned int status_rvd : 6; /* bit 28:23 Tx Status, Reserved bits */ ++ unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */ ++ unsigned int derr : 1; /* bit 30 data error during processing this descriptor */ ++ unsigned int reserved : 1; /* bit 31 */ ++ } bits; ++} GMAC_TXDESC_0_T; ++ ++/* ++ * GMAC DMA Tx Description Word 1 Register ++ * GMAC0 offset 0x8044 ++ * GMAC1 offset 0xC044 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct txdesc_word1 { ++ unsigned int byte_count : 16; /* bit 15: 0 Tx Frame Byte Count */ ++ unsigned int mtu_enable : 1; /* bit 16 TSS segmentation use MTU setting */ ++ unsigned int ip_chksum : 1; /* bit 17 IPV4 Header Checksum Enable */ ++ unsigned int ipv6_enable : 1; /* bit 18 IPV6 Tx Enable */ ++ unsigned int tcp_chksum : 1; /* bit 19 TCP Checksum Enable */ ++ unsigned int udp_chksum : 1; /* bit 20 UDP Checksum Enable */ ++ unsigned int bypass_tss : 1; /* bit 21 Bypass HW offload engine */ ++ unsigned int ip_fixed_len : 1; /* bit 22 Don't update IP length field */ ++ unsigned int reserved : 9; /* bit 31:23 Tx Flag, Reserved */ ++ } bits; ++} GMAC_TXDESC_1_T; ++ ++#define TSS_IP_FIXED_LEN_BIT BIT(22) ++#define TSS_BYPASS_BIT BIT(21) ++#define TSS_UDP_CHKSUM_BIT BIT(20) ++#define TSS_TCP_CHKSUM_BIT BIT(19) ++#define TSS_IPV6_ENABLE_BIT BIT(18) ++#define TSS_IP_CHKSUM_BIT BIT(17) ++#define TSS_MTU_ENABLE_BIT BIT(16) ++ ++#define TSS_CHECKUM_ENABLE \ ++ (TSS_IP_CHKSUM_BIT|TSS_IPV6_ENABLE_BIT| \ ++ TSS_TCP_CHKSUM_BIT|TSS_UDP_CHKSUM_BIT) ++ ++/* ++ * GMAC DMA Tx Description Word 2 Register ++ * GMAC0 offset 0x8048 ++ * GMAC1 offset 0xC048 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int buf_adr; ++} GMAC_TXDESC_2_T; ++ ++/* ++ * GMAC DMA Tx Description Word 3 Register ++ * GMAC0 offset 0x804C ++ * GMAC1 offset 0xC04C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct txdesc_word3 { ++ unsigned int mtu_size : 13; /* bit 12: 0 Tx Frame Byte Count */ ++ unsigned int reserved : 16; /* bit 28:13 */ ++ unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */ ++ unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */ ++ } bits; ++} GMAC_TXDESC_3_T; ++#define SOF_EOF_BIT_MASK 0x3fffffff ++#define SOF_BIT 0x80000000 ++#define EOF_BIT 0x40000000 ++#define EOFIE_BIT BIT(29) ++#define MTU_SIZE_BIT_MASK 0x1fff ++ ++/* ++ * GMAC Tx Descriptor ++ */ ++typedef struct { ++ GMAC_TXDESC_0_T word0; ++ GMAC_TXDESC_1_T word1; ++ GMAC_TXDESC_2_T word2; ++ GMAC_TXDESC_3_T word3; ++} GMAC_TXDESC_T; ++ ++/* ++ * GMAC DMA Rx First Description Address Register ++ * GMAC0 offset 0x8058 ++ * GMAC1 offset 0xC058 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8058 { ++ unsigned int reserved : 3; /* bit 2:0 */ ++ unsigned int rd_busy : 1; /* bit 3 1-RxDMA busy; 0-RxDMA idle */ ++ unsigned int rd_first_des_ptr : 28; /* bit 31:4 first descriptor address */ ++ } bits; ++} GMAC_RXDMA_FIRST_DESC_T; ++ ++/* ++ * GMAC DMA Rx Current Description Address Register ++ * GMAC0 offset 0x805C ++ * GMAC1 offset 0xC05C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_805C { ++ unsigned int reserved : 4; /* bit 3:0 */ ++ unsigned int rd_curr_des_ptr : 28; /* bit 31:4 current descriptor address */ ++ } bits; ++} GMAC_RXDMA_CURR_DESC_T; ++ ++/* ++ * GMAC DMA Rx Description Word 0 Register ++ * GMAC0 offset 0x8060 ++ * GMAC1 offset 0xC060 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8060 { ++ unsigned int buffer_size : 16; /* bit 15:0 number of descriptors used for the current frame */ ++ unsigned int desc_count : 6; /* bit 21:16 number of descriptors used for the current frame */ ++ unsigned int status : 4; /* bit 24:22 Status of rx frame */ ++ unsigned int chksum_status : 3; /* bit 28:26 Check Sum Status */ ++ unsigned int perr : 1; /* bit 29 protocol error during processing this descriptor */ ++ unsigned int derr : 1; /* bit 30 data error during processing this descriptor */ ++ unsigned int drop : 1; /* bit 31 TOE/CIS Queue Full dropped packet to default queue */ ++ } bits; ++} GMAC_RXDESC_0_T; ++ ++#define GMAC_RXDESC_0_T_derr BIT(30) ++#define GMAC_RXDESC_0_T_perr BIT(29) ++#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26)) ++#define GMAC_RXDESC_0_T_status(x) BIT((x+22)) ++#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16)) ++ ++#define RX_CHKSUM_IP_UDP_TCP_OK 0 ++#define RX_CHKSUM_IP_OK_ONLY 1 ++#define RX_CHKSUM_NONE 2 ++#define RX_CHKSUM_IP_ERR_UNKNOWN 4 ++#define RX_CHKSUM_IP_ERR 5 ++#define RX_CHKSUM_TCP_UDP_ERR 6 ++#define RX_CHKSUM_NUM 8 ++ ++#define RX_STATUS_GOOD_FRAME 0 ++#define RX_STATUS_TOO_LONG_GOOD_CRC 1 ++#define RX_STATUS_RUNT_FRAME 2 ++#define RX_STATUS_SFD_NOT_FOUND 3 ++#define RX_STATUS_CRC_ERROR 4 ++#define RX_STATUS_TOO_LONG_BAD_CRC 5 ++#define RX_STATUS_ALIGNMENT_ERROR 6 ++#define RX_STATUS_TOO_LONG_BAD_ALIGN 7 ++#define RX_STATUS_RX_ERR 8 ++#define RX_STATUS_DA_FILTERED 9 ++#define RX_STATUS_BUFFER_FULL 10 ++#define RX_STATUS_NUM 16 ++ ++#define RX_ERROR_LENGTH(s) \ ++ ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \ ++ (s) == RX_STATUS_TOO_LONG_BAD_CRC || \ ++ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN) ++#define RX_ERROR_OVER(s) \ ++ ((s) == RX_STATUS_BUFFER_FULL) ++#define RX_ERROR_CRC(s) \ ++ ((s) == RX_STATUS_CRC_ERROR || \ ++ (s) == RX_STATUS_TOO_LONG_BAD_CRC) ++#define RX_ERROR_FRAME(s) \ ++ ((s) == RX_STATUS_ALIGNMENT_ERROR || \ ++ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN) ++#define RX_ERROR_FIFO(s) \ ++ (0) ++ ++/* ++ * GMAC DMA Rx Description Word 1 Register ++ * GMAC0 offset 0x8064 ++ * GMAC1 offset 0xC064 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct rxdesc_word1 { ++ unsigned int byte_count : 16; /* bit 15: 0 Rx Frame Byte Count */ ++ unsigned int sw_id : 16; /* bit 31:16 Software ID */ ++ } bits; ++} GMAC_RXDESC_1_T; ++ ++/* ++ * GMAC DMA Rx Description Word 2 Register ++ * GMAC0 offset 0x8068 ++ * GMAC1 offset 0xC068 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int buf_adr; ++} GMAC_RXDESC_2_T; ++ ++#define RX_INSERT_NONE 0 ++#define RX_INSERT_1_BYTE 1 ++#define RX_INSERT_2_BYTE 2 ++#define RX_INSERT_3_BYTE 3 ++ ++/* ++ * GMAC DMA Rx Description Word 3 Register ++ * GMAC0 offset 0x806C ++ * GMAC1 offset 0xC06C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct rxdesc_word3 { ++ unsigned int l3_offset : 8; /* bit 7: 0 L3 data offset */ ++ unsigned int l4_offset : 8; /* bit 15: 8 L4 data offset */ ++ unsigned int l7_offset : 8; /* bit 23: 16 L7 data offset */ ++ unsigned int dup_ack : 1; /* bit 24 Duplicated ACK detected */ ++ unsigned int abnormal : 1; /* bit 25 abnormal case found */ ++ unsigned int option : 1; /* bit 26 IPV4 option or IPV6 extension header */ ++ unsigned int out_of_seq : 1; /* bit 27 Out of Sequence packet */ ++ unsigned int ctrl_flag : 1; /* bit 28 Control Flag is present */ ++ unsigned int eofie : 1; /* bit 29 End of frame interrupt enable */ ++ unsigned int sof_eof : 2; /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */ ++ } bits; ++} GMAC_RXDESC_3_T; ++ ++/* ++ * GMAC Rx Descriptor ++ */ ++typedef struct { ++ GMAC_RXDESC_0_T word0; ++ GMAC_RXDESC_1_T word1; ++ GMAC_RXDESC_2_T word2; ++ GMAC_RXDESC_3_T word3; ++} GMAC_RXDESC_T; ++ ++/* ++ * GMAC Hash Engine Enable/Action Register 0 Offset Register ++ * GMAC0 offset 0x8070 ++ * GMAC1 offset 0xC070 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8070 { ++ unsigned int mr0hel : 6; /* bit 5:0 match rule 0 hash entry size */ ++ unsigned int mr0_action : 5; /* bit 10:6 Matching Rule 0 action offset */ ++ unsigned int reserved0 : 4; /* bit 14:11 */ ++ unsigned int mr0en : 1; /* bit 15 Enable Matching Rule 0 */ ++ unsigned int mr1hel : 6; /* bit 21:16 match rule 1 hash entry size */ ++ unsigned int mr1_action : 5; /* bit 26:22 Matching Rule 1 action offset */ ++ unsigned int timing : 3; /* bit 29:27 */ ++ unsigned int reserved1 : 1; /* bit 30 */ ++ unsigned int mr1en : 1; /* bit 31 Enable Matching Rule 1 */ ++ } bits; ++} GMAC_HASH_ENABLE_REG0_T; ++ ++/* ++ * GMAC Hash Engine Enable/Action Register 1 Offset Register ++ * GMAC0 offset 0x8074 ++ * GMAC1 offset 0xC074 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8074 { ++ unsigned int mr2hel : 6; /* bit 5:0 match rule 2 hash entry size */ ++ unsigned int mr2_action : 5; /* bit 10:6 Matching Rule 2 action offset */ ++ unsigned int reserved2 : 4; /* bit 14:11 */ ++ unsigned int mr2en : 1; /* bit 15 Enable Matching Rule 2 */ ++ unsigned int mr3hel : 6; /* bit 21:16 match rule 3 hash entry size */ ++ unsigned int mr3_action : 5; /* bit 26:22 Matching Rule 3 action offset */ ++ unsigned int reserved1 : 4; /* bit 30:27 */ ++ unsigned int mr3en : 1; /* bit 31 Enable Matching Rule 3 */ ++ } bits; ++} GMAC_HASH_ENABLE_REG1_T; ++ ++/* ++ * GMAC Matching Rule Control Register 0 ++ * GMAC0 offset 0x8078 ++ * GMAC1 offset 0xC078 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8078 { ++ unsigned int sprx : 8; /* bit 7:0 Support Protocol Register 7:0 */ ++ unsigned int reserved2 : 4; /* bit 11:8 */ ++ unsigned int tos_traffic : 1; /* bit 12 IPV4 TOS or IPV6 Traffice Class */ ++ unsigned int flow_lable : 1; /* bit 13 IPV6 Flow label */ ++ unsigned int ip_hdr_len : 1; /* bit 14 IPV4 Header length */ ++ unsigned int ip_version : 1; /* bit 15 0: IPV4, 1: IPV6 */ ++ unsigned int reserved1 : 3; /* bit 18:16 */ ++ unsigned int pppoe : 1; /* bit 19 PPPoE Session ID enable */ ++ unsigned int vlan : 1; /* bit 20 VLAN ID enable */ ++ unsigned int ether_type : 1; /* bit 21 Ethernet type enable */ ++ unsigned int sa : 1; /* bit 22 MAC SA enable */ ++ unsigned int da : 1; /* bit 23 MAC DA enable */ ++ unsigned int priority : 3; /* bit 26:24 priority if multi-rules matched */ ++ unsigned int port : 1; /* bit 27 PORT ID matching enable */ ++ unsigned int l7 : 1; /* bit 28 L7 matching enable */ ++ unsigned int l4 : 1; /* bit 29 L4 matching enable */ ++ unsigned int l3 : 1; /* bit 30 L3 matching enable */ ++ unsigned int l2 : 1; /* bit 31 L2 matching enable */ ++ } bits; ++} GMAC_MRxCR0_T; ++ ++#define MR_L2_BIT BIT(31) ++#define MR_L3_BIT BIT(30) ++#define MR_L4_BIT BIT(29) ++#define MR_L7_BIT BIT(28) ++#define MR_PORT_BIT BIT(27) ++#define MR_PRIORITY_BIT BIT(26) ++#define MR_DA_BIT BIT(23) ++#define MR_SA_BIT BIT(22) ++#define MR_ETHER_TYPE_BIT BIT(21) ++#define MR_VLAN_BIT BIT(20) ++#define MR_PPPOE_BIT BIT(19) ++#define MR_IP_VER_BIT BIT(15) ++#define MR_IP_HDR_LEN_BIT BIT(14) ++#define MR_FLOW_LABLE_BIT BIT(13) ++#define MR_TOS_TRAFFIC_BIT BIT(12) ++#define MR_SPR_BIT(x) BIT(x) ++#define MR_SPR_BITS 0xff ++ ++/* ++ * GMAC Matching Rule Control Register 1 ++ * GMAC0 offset 0x807C ++ * GMAC1 offset 0xC07C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_807C { ++ unsigned int l4_byte0_15 : 16; /* bit 15: 0 */ ++ unsigned int dip_netmask : 7; /* bit 22:16 Dest IP net mask, number of mask bits */ ++ unsigned int dip : 1; /* bit 23 Dest IP */ ++ unsigned int sip_netmask : 7; /* bit 30:24 Srce IP net mask, number of mask bits */ ++ unsigned int sip : 1; /* bit 31 Srce IP */ ++ } bits; ++} GMAC_MRxCR1_T; ++ ++/* ++ * GMAC Matching Rule Control Register 2 ++ * GMAC0 offset 0x8080 ++ * GMAC1 offset 0xC080 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_8080 { ++ unsigned int l7_byte0_23 : 24; /* bit 23:0 */ ++ unsigned int l4_byte16_24 : 8; /* bit 31: 24 */ ++ } bits; ++} GMAC_MRxCR2_T; ++ ++/* ++ * GMAC Support registers ++ * GMAC0 offset 0x80A8 ++ * GMAC1 offset 0xC0A8 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_80A8 { ++ unsigned int protocol : 8; /* bit 7:0 Supported protocol */ ++ unsigned int swap : 3; /* bit 10:8 Swap */ ++ unsigned int reserved : 21; /* bit 31:11 */ ++ } bits; ++} GMAC_SPR_T; ++ ++/* ++ * GMAC_AHB_WEIGHT registers ++ * GMAC0 offset 0x80C8 ++ * GMAC1 offset 0xC0C8 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_80C8 { ++ unsigned int hash_weight : 5; /* 4:0 */ ++ unsigned int rx_weight : 5; /* 9:5 */ ++ unsigned int tx_weight : 5; /* 14:10 */ ++ unsigned int pre_req : 5; /* 19:15 Rx Data Pre Request FIFO Threshold */ ++ unsigned int tqDV_threshold : 5; /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */ ++ unsigned int reserved : 7; /* 31:25 */ ++ } bits; ++} GMAC_AHB_WEIGHT_T; ++ ++/* ++ * the register structure of GMAC ++ */ ++ ++/* ++ * GMAC RX FLTR ++ * GMAC0 Offset 0xA00C ++ * GMAC1 Offset 0xE00C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_000c { ++ unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */ ++ unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */ ++ unsigned int broadcast : 1; /* enable receive of broadcast frames */ ++ unsigned int promiscuous : 1; /* enable receive of all frames */ ++ unsigned int error : 1; /* enable receive of all error frames */ ++ unsigned int : 27; ++ } bits; ++} GMAC_RX_FLTR_T; ++ ++/* ++ * GMAC Configuration 0 ++ * GMAC0 Offset 0xA018 ++ * GMAC1 Offset 0xE018 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_0018 { ++ unsigned int dis_tx : 1; /* 0: disable transmit */ ++ unsigned int dis_rx : 1; /* 1: disable receive */ ++ unsigned int loop_back : 1; /* 2: transmit data loopback enable */ ++ unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */ ++ unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */ ++ unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */ ++ unsigned int dis_bkoff : 1; /* 11: disable back-off function */ ++ unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */ ++ unsigned int sim_test : 1; /* 13: speed up timers in simulation */ ++ unsigned int rx_fc_en : 1; /* 14: RX flow control enable */ ++ unsigned int tx_fc_en : 1; /* 15: TX flow control enable */ ++ unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */ ++ unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */ ++ unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */ ++ unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */ ++ unsigned int rgmm_edge : 1; /* 20 */ ++ unsigned int rxc_inv : 1; /* 21 */ ++ unsigned int ipv6_exthdr_order : 1; /* 22 */ ++ unsigned int rx_err_detect : 1; /* 23 */ ++ unsigned int port0_chk_hwq : 1; /* 24 */ ++ unsigned int port1_chk_hwq : 1; /* 25 */ ++ unsigned int port0_chk_toeq : 1; /* 26 */ ++ unsigned int port1_chk_toeq : 1; /* 27 */ ++ unsigned int port0_chk_classq : 1; /* 28 */ ++ unsigned int port1_chk_classq : 1; /* 29 */ ++ unsigned int reserved : 2; /* 31 */ ++ } bits; ++} GMAC_CONFIG0_T; ++ ++#define CONFIG0_TX_RX_DISABLE (BIT(1)|BIT(0)) ++#define CONFIG0_RX_CHKSUM (BIT(18)|BIT(17)) ++#define CONFIG0_FLOW_RX (BIT(14)) ++#define CONFIG0_FLOW_TX (BIT(15)) ++#define CONFIG0_FLOW_TX_RX (BIT(14)|BIT(15)) ++#define CONFIG0_FLOW_CTL (BIT(14)|BIT(15)) ++ ++#define CONFIG0_MAXLEN_SHIFT 8 ++#define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT) ++#define CONFIG0_MAXLEN_1536 0 ++#define CONFIG0_MAXLEN_1518 1 ++#define CONFIG0_MAXLEN_1522 2 ++#define CONFIG0_MAXLEN_1542 3 ++#define CONFIG0_MAXLEN_9k 4 /* 9212 */ ++#define CONFIG0_MAXLEN_10k 5 /* 10236 */ ++#define CONFIG0_MAXLEN_1518__6 6 ++#define CONFIG0_MAXLEN_1518__7 7 ++ ++/* ++ * GMAC Configuration 1 ++ * GMAC0 Offset 0xA01C ++ * GMAC1 Offset 0xE01C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_001c { ++ unsigned int set_threshold : 8; /* flow control set threshold */ ++ unsigned int rel_threshold : 8; /* flow control release threshold */ ++ unsigned int reserved : 16; ++ } bits; ++} GMAC_CONFIG1_T; ++ ++#define GMAC_FLOWCTRL_SET_MAX 32 ++#define GMAC_FLOWCTRL_SET_MIN 0 ++#define GMAC_FLOWCTRL_RELEASE_MAX 32 ++#define GMAC_FLOWCTRL_RELEASE_MIN 0 ++ ++/* ++ * GMAC Configuration 2 ++ * GMAC0 Offset 0xA020 ++ * GMAC1 Offset 0xE020 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_0020 { ++ unsigned int set_threshold : 16; /* flow control set threshold */ ++ unsigned int rel_threshold : 16; /* flow control release threshold */ ++ } bits; ++} GMAC_CONFIG2_T; ++ ++/* ++ * GMAC Configuration 3 ++ * GMAC0 Offset 0xA024 ++ * GMAC1 Offset 0xE024 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_0024 { ++ unsigned int set_threshold : 16; /* flow control set threshold */ ++ unsigned int rel_threshold : 16; /* flow control release threshold */ ++ } bits; ++} GMAC_CONFIG3_T; ++ ++ ++/* ++ * GMAC STATUS ++ * GMAC0 Offset 0xA02C ++ * GMAC1 Offset 0xE02C ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit1_002c { ++ unsigned int link : 1; /* link status */ ++ unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */ ++ unsigned int duplex : 1; /* duplex mode */ ++ unsigned int reserved : 1; ++ unsigned int mii_rmii : 2; /* PHY interface type */ ++ unsigned int : 25; ++ } bits; ++} GMAC_STATUS_T; ++ ++#define GMAC_SPEED_10 0 ++#define GMAC_SPEED_100 1 ++#define GMAC_SPEED_1000 2 ++ ++#define GMAC_PHY_MII 0 ++#define GMAC_PHY_GMII 1 ++#define GMAC_PHY_RGMII_100_10 2 ++#define GMAC_PHY_RGMII_1000 3 ++ ++/* ++ * Queue Header ++ * (1) TOE Queue Header ++ * (2) Non-TOE Queue Header ++ * (3) Interrupt Queue Header ++ * ++ * memory Layout ++ * TOE Queue Header ++ * 0x60003000 +---------------------------+ 0x0000 ++ * | TOE Queue 0 Header | ++ * | 8 * 4 Bytes | ++ * +---------------------------+ 0x0020 ++ * | TOE Queue 1 Header | ++ * | 8 * 4 Bytes | ++ * +---------------------------+ 0x0040 ++ * | ...... | ++ * | | ++ * +---------------------------+ ++ * ++ * Non TOE Queue Header ++ * 0x60002000 +---------------------------+ 0x0000 ++ * | Default Queue 0 Header | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ 0x0008 ++ * | Default Queue 1 Header | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ 0x0010 ++ * | Classification Queue 0 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * | Classification Queue 1 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ (n * 8 + 0x10) ++ * | ... | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ (13 * 8 + 0x10) ++ * | Classification Queue 13 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ 0x80 ++ * | Interrupt Queue 0 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * | Interrupt Queue 1 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * | Interrupt Queue 2 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * | Interrupt Queue 3 | ++ * | 2 * 4 Bytes | ++ * +---------------------------+ ++ * ++ */ ++#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32) ++#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1)) ++#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x)) ++#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10) ++#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80) ++#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8) ++#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1)) ++/* ++ * TOE Queue Header Word 0 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int base_size; ++} TOE_QHDR0_T; ++ ++#define TOE_QHDR0_BASE_MASK (~0x0f) ++ ++/* ++ * TOE Queue Header Word 1 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr1 { ++ unsigned int rptr : 16; /* bit 15:0 */ ++ unsigned int wptr : 16; /* bit 31:16 */ ++ } bits; ++} TOE_QHDR1_T; ++ ++/* ++ * TOE Queue Header Word 2 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr2 { ++ unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */ ++ unsigned int reserved : 7; /* bit 23:17 */ ++ unsigned int dack : 1; /* bit 24 1: Duplicated ACK */ ++ unsigned int abn : 1; /* bit 25 1: Abnormal case Found */ ++ unsigned int tcp_opt : 1; /* bit 26 1: Have TCP option */ ++ unsigned int ip_opt : 1; /* bit 27 1: have IPV4 option or IPV6 Extension header */ ++ unsigned int sat : 1; /* bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */ ++ unsigned int osq : 1; /* bit 29 1: out of sequence */ ++ unsigned int ctl : 1; /* bit 30 1: have control flag bits (except ack) */ ++ unsigned int usd : 1; /* bit 31 0: if no data assembled yet */ ++ } bits; ++} TOE_QHDR2_T; ++ ++/* ++ * TOE Queue Header Word 3 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int seq_num; ++} TOE_QHDR3_T; ++ ++/* ++ * TOE Queue Header Word 4 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int ack_num; ++} TOE_QHDR4_T; ++ ++/* ++ * TOE Queue Header Word 5 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr5 { ++ unsigned int AckCnt : 16; /* bit 15:0 */ ++ unsigned int SeqCnt : 16; /* bit 31:16 */ ++ } bits; ++} TOE_QHDR5_T; ++ ++/* ++ * TOE Queue Header Word 6 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr6 { ++ unsigned int WinSize : 16; /* bit 15:0 */ ++ unsigned int iq_num : 2; /* bit 17:16 */ ++ unsigned int MaxPktSize : 14; /* bit 31:18 */ ++ } bits; ++} TOE_QHDR6_T; ++ ++/* ++ * TOE Queue Header Word 7 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_qhdr7 { ++ unsigned int AckThreshold : 16; /* bit 15:0 */ ++ unsigned int SeqThreshold : 16; /* bit 31:16 */ ++ } bits; ++} TOE_QHDR7_T; ++ ++/* ++ * TOE Queue Header ++ */ ++typedef struct { ++ TOE_QHDR0_T word0; ++ TOE_QHDR1_T word1; ++ TOE_QHDR2_T word2; ++ TOE_QHDR3_T word3; ++ TOE_QHDR4_T word4; ++ TOE_QHDR5_T word5; ++ TOE_QHDR6_T word6; ++ TOE_QHDR7_T word7; ++} TOE_QHDR_T; ++ ++/* ++ * NONTOE Queue Header Word 0 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int base_size; ++} NONTOE_QHDR0_T; ++ ++#define NONTOE_QHDR0_BASE_MASK (~0x0f) ++ ++/* ++ * NONTOE Queue Header Word 1 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_nonqhdr1 { ++ unsigned int rptr : 16; /* bit 15:0 */ ++ unsigned int wptr : 16; /* bit 31:16 */ ++ } bits; ++} NONTOE_QHDR1_T; ++ ++/* ++ * Non-TOE Queue Header ++ */ ++typedef struct { ++ NONTOE_QHDR0_T word0; ++ NONTOE_QHDR1_T word1; ++} NONTOE_QHDR_T; ++ ++/* ++ * Interrupt Queue Header Word 0 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_intrqhdr0 { ++ unsigned int win_size : 16; /* bit 15:0 Descriptor Ring Size */ ++ unsigned int wptr : 16; /* bit 31:16 Write Pointer where hw stopped */ ++ } bits; ++} INTR_QHDR0_T; ++ ++/* ++ * Interrupt Queue Header Word 1 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_intrqhdr1 { ++ unsigned int TotalPktSize : 17; /* bit 16: 0 Total packet size */ ++ unsigned int tcp_qid : 8; /* bit 24:17 TCP Queue ID */ ++ unsigned int dack : 1; /* bit 25 1: Duplicated ACK */ ++ unsigned int abn : 1; /* bit 26 1: Abnormal case Found */ ++ unsigned int tcp_opt : 1; /* bit 27 1: Have TCP option */ ++ unsigned int ip_opt : 1; /* bit 28 1: have IPV4 option or IPV6 Extension header */ ++ unsigned int sat : 1; /* bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold */ ++ unsigned int osq : 1; /* bit 30 1: out of sequence */ ++ unsigned int ctl : 1; /* bit 31 1: have control flag bits (except ack) */ ++ } bits; ++} INTR_QHDR1_T; ++ ++/* ++ * Interrupt Queue Header Word 2 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int seq_num; ++} INTR_QHDR2_T; ++ ++/* ++ * Interrupt Queue Header Word 3 ++ */ ++typedef union { ++ unsigned int bits32; ++ unsigned int ack_num; ++} INTR_QHDR3_T; ++ ++/* ++ * Interrupt Queue Header Word 4 ++ */ ++typedef union { ++ unsigned int bits32; ++ struct bit_intrqhdr4 { ++ unsigned int AckCnt : 16; /* bit 15:0 Ack# change since last ack# intr. */ ++ unsigned int SeqCnt : 16; /* bit 31:16 Seq# change since last seq# intr. */ ++ } bits; ++} INTR_QHDR4_T; ++ ++/* ++ * Interrupt Queue Header ++ */ ++typedef struct { ++ INTR_QHDR0_T word0; ++ INTR_QHDR1_T word1; ++ INTR_QHDR2_T word2; ++ INTR_QHDR3_T word3; ++ INTR_QHDR4_T word4; ++ unsigned int word5; ++ unsigned int word6; ++ unsigned int word7; ++} INTR_QHDR_T; ++ ++#endif /* _GMAC_SL351x_H */ diff --git a/target/linux/gemini/patches-4.1/121-arm-gemini-register-ethernet.patch b/target/linux/gemini/patches-4.1/121-arm-gemini-register-ethernet.patch new file mode 100644 index 0000000..5ae896c --- /dev/null +++ b/target/linux/gemini/patches-4.1/121-arm-gemini-register-ethernet.patch @@ -0,0 +1,209 @@ +--- a/arch/arm/mach-gemini/board-nas4220b.c ++++ b/arch/arm/mach-gemini/board-nas4220b.c +@@ -28,9 +28,27 @@ + + #include + #include ++#include + + #include "common.h" + ++static struct mdio_gpio_platform_data ib4220b_mdio = { ++ .mdc = 22, ++ .mdio = 21, ++ .phy_mask = ~(1 << 1), ++}; ++ ++static struct platform_device ib4220b_phy_device = { ++ .name = "mdio-gpio", ++ .id = 0, ++ .dev = { .platform_data = &ib4220b_mdio, }, ++}; ++ ++static struct gemini_gmac_platform_data ib4220b_gmac_data = { ++ .bus_id[0] = "gpio-0:01", ++ .interface[0] = PHY_INTERFACE_MODE_RGMII, ++}; ++ + static struct gpio_led ib4220b_leds[] = { + { + .name = "nas4220b:orange:hdd", +@@ -87,15 +105,47 @@ static struct platform_device ib4220b_ke + }, + }; + ++static void __init ib4220b_gmac_init(void) ++{ ++ unsigned int val; ++ ++ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_IO_DRIVING_CTRL)); ++ val |= (0x3 << GMAC0_PADS_SHIFT) | (0x3 << GMAC1_PADS_SHIFT); ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_IO_DRIVING_CTRL)); ++ ++ val = (0x0 << GMAC0_RXDV_SKEW_SHIFT) | (0xf << GMAC0_RXC_SKEW_SHIFT) | ++ (0x7 << GMAC0_TXEN_SKEW_SHIFT) | (0xb << GMAC0_TXC_SKEW_SHIFT) | ++ (0x0 << GMAC1_RXDV_SKEW_SHIFT) | (0xf << GMAC1_RXC_SKEW_SHIFT) | ++ (0x7 << GMAC1_TXEN_SKEW_SHIFT) | (0xa << GMAC1_TXC_SKEW_SHIFT); ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_GMAC_CTRL_SKEW_CTRL)); ++ ++ writel(0x77777777, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_GMAC0_DATA_SKEW_CTRL)); ++ writel(0x77777777, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_GMAC1_DATA_SKEW_CTRL)); ++ ++ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_ARBITRATION1_CTRL)) & ~BURST_LENGTH_MASK; ++ val |= (0x20 << BURST_LENGTH_SHIFT) | GMAC0_HIGH_PRIO | GMAC1_HIGH_PRIO; ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_ARBITRATION1_CTRL)); ++} ++ + static void __init ib4220b_init(void) + { + gemini_gpio_init(); ++ ib4220b_gmac_init(); + platform_register_uart(); + platform_register_pflash(SZ_16M, NULL, 0); + platform_device_register(&ib4220b_led_device); + platform_device_register(&ib4220b_key_device); + platform_register_rtc(); + platform_register_watchdog(); ++ platform_device_register(&ib4220b_phy_device); ++ platform_register_ethernet(&ib4220b_gmac_data); + } + + MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") +--- a/arch/arm/mach-gemini/board-wbd111.c ++++ b/arch/arm/mach-gemini/board-wbd111.c +@@ -22,9 +22,29 @@ + #include + #include + ++#include + + #include "common.h" + ++static struct mdio_gpio_platform_data wbd111_mdio = { ++ .mdc = 22, ++ .mdio = 21, ++ .phy_mask = ~(1 << 1), ++}; ++ ++static struct platform_device wbd111_phy_device = { ++ .name = "mdio-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &wbd111_mdio, ++ }, ++}; ++ ++static struct gemini_gmac_platform_data gmac_data = { ++ .bus_id[0] = "gpio-0:01", ++ .interface[0] = PHY_INTERFACE_MODE_MII, ++}; ++ + static struct gpio_keys_button wbd111_keys[] = { + { + .code = KEY_SETUP, +@@ -123,6 +143,8 @@ static void __init wbd111_init(void) + platform_device_register(&wbd111_keys_device); + platform_register_rtc(); + platform_register_watchdog(); ++ platform_device_register(&wbd111_phy_device); ++ platform_register_ethernet(&gmac_data); + } + + MACHINE_START(WBD111, "Wiliboard WBD-111") +--- a/arch/arm/mach-gemini/board-wbd222.c ++++ b/arch/arm/mach-gemini/board-wbd222.c +@@ -22,9 +22,31 @@ + #include + #include + ++#include + + #include "common.h" + ++static struct mdio_gpio_platform_data wbd222_mdio = { ++ .mdc = 22, ++ .mdio = 21, ++ .phy_mask = ~((1 << 1) | (1 << 3)), ++}; ++ ++static struct platform_device wbd222_phy_device = { ++ .name = "mdio-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &wbd222_mdio, ++ }, ++}; ++ ++static struct gemini_gmac_platform_data gmac_data = { ++ .bus_id[0] = "gpio-0:01", ++ .interface[0] = PHY_INTERFACE_MODE_MII, ++ .bus_id[1] = "gpio-0:03", ++ .interface[1] = PHY_INTERFACE_MODE_MII, ++}; ++ + static struct gpio_keys_button wbd222_keys[] = { + { + .code = KEY_SETUP, +@@ -123,6 +145,8 @@ static void __init wbd222_init(void) + platform_device_register(&wbd222_keys_device); + platform_register_rtc(); + platform_register_watchdog(); ++ platform_device_register(&wbd222_phy_device); ++ platform_register_ethernet(&gmac_data); + } + + MACHINE_START(WBD222, "Wiliboard WBD-222") +--- a/arch/arm/mach-gemini/board-rut1xx.c ++++ b/arch/arm/mach-gemini/board-rut1xx.c +@@ -15,13 +15,35 @@ + #include + #include + #include ++#include + + #include + #include + #include + ++#include ++ + #include "common.h" + ++static struct mdio_gpio_platform_data rut1xx_mdio = { ++ .mdc = 22, ++ .mdio = 21, ++ .phy_mask = ~(1 << 1), ++}; ++ ++static struct platform_device rut1xx_phy_device = { ++ .name = "mdio-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &rut1xx_mdio, ++ }, ++}; ++ ++static struct gemini_gmac_platform_data gmac_data = { ++ .bus_id[0] = "gpio-0:01", ++ .interface[0] = PHY_INTERFACE_MODE_MII, ++}; ++ + static struct gpio_keys_button rut1xx_keys[] = { + { + .code = KEY_SETUP, +@@ -81,6 +103,8 @@ static void __init rut1xx_init(void) + platform_device_register(&rut1xx_keys_device); + platform_register_rtc(); + platform_register_watchdog(); ++ platform_device_register(&rut1xx_phy_device); ++ platform_register_ethernet(&gmac_data); + } + + MACHINE_START(RUT100, "Teltonika RUT100") diff --git a/target/linux/gemini/patches-4.1/130-usb-ehci-fot2g.patch b/target/linux/gemini/patches-4.1/130-usb-ehci-fot2g.patch new file mode 100644 index 0000000..5f6eecc --- /dev/null +++ b/target/linux/gemini/patches-4.1/130-usb-ehci-fot2g.patch @@ -0,0 +1,210 @@ +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -188,3 +188,64 @@ int platform_register_ethernet(struct ge + + return platform_device_register(ðernet_device); + } ++ ++static struct resource usb0_resources[] = { ++ { ++ .start = GEMINI_USB0_BASE, ++ .end = GEMINI_USB0_BASE + 0xfff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IRQ_USB0, ++ .end = IRQ_USB0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource usb1_resources[] = { ++ { ++ .start = GEMINI_USB1_BASE, ++ .end = GEMINI_USB1_BASE + 0xfff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IRQ_USB1, ++ .end = IRQ_USB1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 usb0_dmamask = 0xffffffffUL; ++static u64 usb1_dmamask = 0xffffffffUL; ++ ++static struct platform_device usb_device[] = { ++ { ++ .name = "ehci-fotg2", ++ .id = 0, ++ .dev = { ++ .dma_mask = &usb0_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(usb0_resources), ++ .resource = usb0_resources, ++ }, ++ { ++ .name = "ehci-fotg2", ++ .id = 1, ++ .dev = { ++ .dma_mask = &usb1_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(usb1_resources), ++ .resource = usb1_resources, ++ }, ++}; ++ ++int __init platform_register_usb(unsigned int id) ++{ ++ if (id > 1) ++ return -EINVAL; ++ ++ return platform_device_register(&usb_device[id]); ++} ++ +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -30,6 +30,7 @@ extern int platform_register_pflash(unsi + unsigned int nr_parts); + extern int platform_register_watchdog(void); + extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata); ++extern int platform_register_usb(unsigned int id); + + extern void gemini_restart(enum reboot_mode mode, const char *cmd); + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -351,11 +351,13 @@ static void ehci_silence_controller(stru + ehci->rh_state = EHCI_RH_HALTED; + ehci_turn_off_all_ports(ehci); + ++#ifndef CONFIG_ARCH_GEMINI + /* make BIOS/etc use companion controller during reboot */ + ehci_writel(ehci, 0, &ehci->regs->configured_flag); + + /* unblock posted writes */ + ehci_readl(ehci, &ehci->regs->configured_flag); ++#endif + spin_unlock_irq(&ehci->lock); + } + +@@ -607,7 +609,9 @@ static int ehci_run (struct usb_hcd *hcd + // Philips, Intel, and maybe others need CMD_RUN before the + // root hub will detect new devices (why?); NEC doesn't + ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); ++#ifndef CONFIG_ARCH_GEMINI + ehci->command |= CMD_RUN; ++#endif + ehci_writel(ehci, ehci->command, &ehci->regs->command); + dbg_cmd (ehci, "init", ehci->command); + +@@ -627,9 +631,11 @@ static int ehci_run (struct usb_hcd *hcd + */ + down_write(&ehci_cf_port_reset_rwsem); + ehci->rh_state = EHCI_RH_RUNNING; ++#ifndef CONFIG_ARCH_GEMINI + ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); + ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ + msleep(5); ++#endif + up_write(&ehci_cf_port_reset_rwsem); + ehci->last_periodic_enable = ktime_get_real(); + +@@ -767,9 +773,10 @@ static irqreturn_t ehci_irq (struct usb_ + pcd_status = status; + + /* resume root hub? */ ++#ifndef CONFIG_ARCH_GEMINI + if (ehci->rh_state == EHCI_RH_SUSPENDED) + usb_hcd_resume_root_hub(hcd); +- ++#endif + /* get per-port change detect bits */ + if (ehci->has_ppcd) + ppcd = status >> 16; +@@ -1250,6 +1257,11 @@ MODULE_DESCRIPTION(DRIVER_DESC); + MODULE_AUTHOR (DRIVER_AUTHOR); + MODULE_LICENSE ("GPL"); + ++#ifdef CONFIG_ARCH_GEMINI ++#include "ehci-fotg2.c" ++#define PLATFORM_DRIVER ehci_fotg2_driver ++#endif ++ + #ifdef CONFIG_USB_EHCI_FSL + #include "ehci-fsl.c" + #define PLATFORM_DRIVER ehci_fsl_driver +--- a/drivers/usb/host/ehci-timer.c ++++ b/drivers/usb/host/ehci-timer.c +@@ -208,7 +208,9 @@ static void ehci_handle_controller_death + + /* Clean up the mess */ + ehci->rh_state = EHCI_RH_HALTED; ++#ifndef CONFIG_ARCH_GEMINI + ehci_writel(ehci, 0, &ehci->regs->configured_flag); ++#endif + ehci_writel(ehci, 0, &ehci->regs->intr_enable); + ehci_work(ehci); + end_unlink_async(ehci); +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -656,7 +656,12 @@ static inline unsigned int + ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) + { + if (ehci_is_TDI(ehci)) { +- switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { ++#ifdef CONFIG_ARCH_GEMINI ++ portsc = readl(ehci_to_hcd(ehci)->regs + 0x80); ++ switch ((portsc>>22)&3) { ++#else ++ switch ((portsc>>26)&3) { ++#endif + case 0: + return 0; + case 1: +--- a/drivers/usb/host/ehci-hub.c ++++ b/drivers/usb/host/ehci-hub.c +@@ -1075,6 +1075,11 @@ int ehci_hub_control( + /* see what we found out */ + temp = check_reset_complete (ehci, wIndex, status_reg, + ehci_readl(ehci, status_reg)); ++#ifdef CONFIG_ARCH_GEMINI ++ /* restart schedule */ ++ ehci->command |= CMD_RUN; ++ ehci_writel(ehci, ehci->command, &ehci->regs->command); ++#endif + } + + /* transfer dedicated ports to the companion hc */ +--- a/include/linux/usb/ehci_def.h ++++ b/include/linux/usb/ehci_def.h +@@ -112,8 +112,13 @@ struct ehci_regs { + u32 frame_list; /* points to periodic list */ + /* ASYNCLISTADDR: offset 0x18 */ + u32 async_next; /* address of next async queue head */ +- ++#ifndef CONFIG_ARCH_GEMINI + u32 reserved1[2]; ++#else ++ u32 reserved1; ++ /* PORTSC: offset 0x20 for Faraday OTG */ ++ u32 port_status[1]; ++#endif + + /* TXFILLTUNING: offset 0x24 */ + u32 txfill_tuning; /* TX FIFO Tuning register */ +@@ -125,8 +130,11 @@ struct ehci_regs { + u32 configured_flag; + #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ + ++#ifndef CONFIG_ARCH_GEMINI + /* PORTSC: offset 0x44 */ + u32 port_status[0]; /* up to N_PORTS */ ++#endif ++ + /* EHCI 1.1 addendum */ + #define PORTSC_SUSPEND_STS_ACK 0 + #define PORTSC_SUSPEND_STS_NYET 1 diff --git a/target/linux/gemini/patches-4.1/132-arm-gemini-register-usb.patch b/target/linux/gemini/patches-4.1/132-arm-gemini-register-usb.patch new file mode 100644 index 0000000..2a61d82 --- /dev/null +++ b/target/linux/gemini/patches-4.1/132-arm-gemini-register-usb.patch @@ -0,0 +1,65 @@ +--- a/arch/arm/mach-gemini/board-wbd111.c ++++ b/arch/arm/mach-gemini/board-wbd111.c +@@ -145,6 +145,7 @@ static void __init wbd111_init(void) + platform_register_watchdog(); + platform_device_register(&wbd111_phy_device); + platform_register_ethernet(&gmac_data); ++ platform_register_usb(0); + } + + MACHINE_START(WBD111, "Wiliboard WBD-111") +--- a/arch/arm/mach-gemini/board-wbd222.c ++++ b/arch/arm/mach-gemini/board-wbd222.c +@@ -147,6 +147,7 @@ static void __init wbd222_init(void) + platform_register_watchdog(); + platform_device_register(&wbd222_phy_device); + platform_register_ethernet(&gmac_data); ++ platform_register_usb(0); + } + + MACHINE_START(WBD222, "Wiliboard WBD-222") +--- a/arch/arm/mach-gemini/board-rut1xx.c ++++ b/arch/arm/mach-gemini/board-rut1xx.c +@@ -105,6 +105,7 @@ static void __init rut1xx_init(void) + platform_register_watchdog(); + platform_device_register(&rut1xx_phy_device); + platform_register_ethernet(&gmac_data); ++ platform_register_usb(0); + } + + MACHINE_START(RUT100, "Teltonika RUT100") +--- a/arch/arm/mach-gemini/board-nas4220b.c ++++ b/arch/arm/mach-gemini/board-nas4220b.c +@@ -134,10 +134,23 @@ static void __init ib4220b_gmac_init(voi + GLOBAL_ARBITRATION1_CTRL)); + } + ++static void __init usb_ib4220b_init(void) ++{ ++ unsigned int val; ++ ++ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ val &= ~(USB0_PLUG_MINIB | USB1_PLUG_MINIB); ++ val |= USB0_VBUS_ON | USB1_VBUS_ON; ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++} ++ + static void __init ib4220b_init(void) + { + gemini_gpio_init(); + ib4220b_gmac_init(); ++ usb_ib4220b_init(); + platform_register_uart(); + platform_register_pflash(SZ_16M, NULL, 0); + platform_device_register(&ib4220b_led_device); +@@ -146,6 +159,8 @@ static void __init ib4220b_init(void) + platform_register_watchdog(); + platform_device_register(&ib4220b_phy_device); + platform_register_ethernet(&ib4220b_gmac_data); ++ platform_register_usb(0); ++ platform_register_usb(1); + } + + MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") diff --git a/target/linux/gemini/patches-4.1/140-arm-gemini-add-pci-support.patch b/target/linux/gemini/patches-4.1/140-arm-gemini-add-pci-support.patch new file mode 100644 index 0000000..141799b --- /dev/null +++ b/target/linux/gemini/patches-4.1/140-arm-gemini-add-pci-support.patch @@ -0,0 +1,389 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -381,6 +381,7 @@ config ARCH_GEMINI + select CLKSRC_MMIO + select CPU_FA526 + select GENERIC_CLOCKEVENTS ++ select MIGHT_HAVE_PCI + help + Support for the Cortina Systems Gemini family SoCs + +--- a/arch/arm/mach-gemini/include/mach/hardware.h ++++ b/arch/arm/mach-gemini/include/mach/hardware.h +@@ -71,4 +71,9 @@ + */ + #define IO_ADDRESS(x) IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000) + ++/* ++ * PCI subsystem macros ++ */ ++#define pcibios_assign_all_busses() 1 ++ + #endif +--- a/arch/arm/mach-gemini/include/mach/irqs.h ++++ b/arch/arm/mach-gemini/include/mach/irqs.h +@@ -43,11 +43,14 @@ + + #define NORMAL_IRQ_NUM 32 + +-#define GPIO_IRQ_BASE NORMAL_IRQ_NUM ++#define PCI_IRQ_BASE NORMAL_IRQ_NUM ++#define PCI_IRQ_NUM 4 ++ ++#define GPIO_IRQ_BASE (NORMAL_IRQ_NUM + PCI_IRQ_NUM) + #define GPIO_IRQ_NUM (3 * 32) + + #define ARCH_TIMER_IRQ IRQ_TIMER2 + +-#define NR_IRQS (NORMAL_IRQ_NUM + GPIO_IRQ_NUM) ++#define NR_IRQS (NORMAL_IRQ_NUM + PCI_IRQ_NUM + GPIO_IRQ_NUM) + + #endif /* __MACH_IRQS_H__ */ +--- a/arch/arm/mach-gemini/Makefile ++++ b/arch/arm/mach-gemini/Makefile +@@ -6,6 +6,8 @@ + + obj-y := irq.o mm.o time.o devices.o gpio.o idle.o reset.o + ++obj-$(CONFIG_PCI) += pci.o ++ + # Board-specific support + obj-$(CONFIG_MACH_NAS4220B) += board-nas4220b.o + obj-$(CONFIG_MACH_RUT100) += board-rut1xx.o +--- a/arch/arm/mach-gemini/mm.c ++++ b/arch/arm/mach-gemini/mm.c +@@ -59,6 +59,11 @@ static struct map_desc gemini_io_desc[] + .length = SZ_512K, + .type = MT_DEVICE, + }, { ++ .virtual = (unsigned long)IO_ADDRESS(GEMINI_PCI_IO_BASE), ++ .pfn = __phys_to_pfn(GEMINI_PCI_IO_BASE), ++ .length = SZ_512K, ++ .type = MT_DEVICE, ++ }, { + .virtual = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE), + .pfn = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE), + .length = SZ_512K, +--- /dev/null ++++ b/arch/arm/mach-gemini/pci.c +@@ -0,0 +1,320 @@ ++/* ++ * Support for Gemini PCI Controller ++ * ++ * Copyright (C) 2009 Janos Laube ++ * Copyright (C) 2009 Paulius Zaleckas ++ * ++ * based on SL2312 PCI controller code ++ * Storlink (C) 2003 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#define GEMINI_PCI_IOSIZE_1M 0x0000 ++ ++#define GEMINI_PCI_PMC 0x40 ++#define GEMINI_PCI_PMCSR 0x44 ++#define GEMINI_PCI_CTRL1 0x48 ++#define GEMINI_PCI_CTRL2 0x4C ++#define GEMINI_PCI_MEM1_BASE_SIZE 0x50 ++#define GEMINI_PCI_MEM2_BASE_SIZE 0x54 ++#define GEMINI_PCI_MEM3_BASE_SIZE 0x58 ++ ++#define PCI_CTRL2_INTSTS_OFFSET 28 ++#define PCI_CTRL2_INTMASK_OFFSET 22 ++ ++#define GEMINI_PCI_DMA_MASK 0xFFF00000 ++#define GEMINI_PCI_DMA_MEM1_BASE 0x00000000 ++#define GEMINI_PCI_DMA_MEM2_BASE 0x00000000 ++#define GEMINI_PCI_DMA_MEM3_BASE 0x00000000 ++#define GEMINI_PCI_DMA_MEM1_SIZE 7 ++#define GEMINI_PCI_DMA_MEM2_SIZE 6 ++#define GEMINI_PCI_DMA_MEM3_SIZE 6 ++ ++#define PCI_CONF_ENABLE (1 << 31) ++#define PCI_CONF_WHERE(r) ((r) & 0xFC) ++#define PCI_CONF_BUS(b) (((b) & 0xFF) << 16) ++#define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11) ++#define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8) ++ ++#define PCI_IOSIZE_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE)) ++#define PCI_PROT_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x04) ++#define PCI_CTRL_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x08) ++#define PCI_SOFTRST_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x10) ++#define PCI_CONFIG_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x28) ++#define PCI_DATA_REG (IO_ADDRESS(GEMINI_PCI_IO_BASE) + 0x2C) ++ ++ ++static DEFINE_SPINLOCK(gemini_pci_lock); ++ ++static int gemini_pci_read_config(struct pci_bus* bus, unsigned int fn, ++ int config, int size, u32* value) ++{ ++ unsigned long irq_flags; ++ ++ spin_lock_irqsave(&gemini_pci_lock, irq_flags); ++ ++ __raw_writel(PCI_CONF_BUS(bus->number) | ++ PCI_CONF_DEVICE(PCI_SLOT(fn)) | ++ PCI_CONF_FUNCTION(PCI_FUNC(fn)) | ++ PCI_CONF_WHERE(config) | ++ PCI_CONF_ENABLE, ++ PCI_CONFIG_REG); ++ ++ *value = __raw_readl(PCI_DATA_REG); ++ ++ if (size == 1) ++ *value = (*value >> (8 * (config & 3))) & 0xFF; ++ else if (size == 2) ++ *value = (*value >> (8 * (config & 3))) & 0xFFFF; ++ ++ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags); ++ ++ dev_dbg(&bus->dev, ++ "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", ++ PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int gemini_pci_write_config(struct pci_bus* bus, unsigned int fn, ++ int config, int size, u32 value) ++{ ++ unsigned long irq_flags = 0; ++ int ret = PCIBIOS_SUCCESSFUL; ++ ++ dev_dbg(&bus->dev, ++ "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n", ++ PCI_SLOT(fn), PCI_FUNC(fn), config, size, value); ++ ++ spin_lock_irqsave(&gemini_pci_lock, irq_flags); ++ ++ __raw_writel(PCI_CONF_BUS(bus->number) | ++ PCI_CONF_DEVICE(PCI_SLOT(fn)) | ++ PCI_CONF_FUNCTION(PCI_FUNC(fn)) | ++ PCI_CONF_WHERE(config) | ++ PCI_CONF_ENABLE, ++ PCI_CONFIG_REG); ++ ++ switch(size) { ++ case 4: ++ __raw_writel(value, PCI_DATA_REG); ++ break; ++ case 2: ++ __raw_writew(value, PCI_DATA_REG + (config & 3)); ++ break; ++ case 1: ++ __raw_writeb(value, PCI_DATA_REG + (config & 3)); ++ break; ++ default: ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ } ++ ++ spin_unlock_irqrestore(&gemini_pci_lock, irq_flags); ++ ++ return ret; ++} ++ ++static struct pci_ops gemini_pci_ops = { ++ .read = gemini_pci_read_config, ++ .write = gemini_pci_write_config, ++}; ++ ++static struct resource gemini_pci_resource_io = { ++ .name = "PCI I/O Space", ++ .start = GEMINI_PCI_IO_BASE, ++ .end = GEMINI_PCI_IO_BASE + SZ_1M - 1, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource gemini_pci_resource_mem = { ++ .name = "PCI Memory Space", ++ .start = GEMINI_PCI_MEM_BASE, ++ .end = GEMINI_PCI_MEM_BASE + SZ_128M - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static int __init gemini_pci_request_resources(struct pci_sys_data *sys) ++{ ++ if (request_resource(&ioport_resource, &gemini_pci_resource_io)) ++ goto bad_resources; ++ if (request_resource(&iomem_resource, &gemini_pci_resource_mem)) ++ goto bad_resources; ++ ++ pci_add_resource(&sys->resources, &gemini_pci_resource_io); ++ pci_add_resource(&sys->resources, &gemini_pci_resource_mem); ++ ++ return 0; ++ ++bad_resources: ++ pr_err("Gemini PCI: request_resource() failed. " ++ "Abort PCI bus enumeration.\n"); ++ return -1; ++} ++ ++static int __init gemini_pci_setup(int nr, struct pci_sys_data *sys) ++{ ++ unsigned int cmd; ++ ++ pcibios_min_io = 0x100; ++ pcibios_min_mem = 0; ++ ++ if ((nr > 0) || gemini_pci_request_resources(sys)) ++ return 0; ++ ++ /* setup I/O space to 1MB size */ ++ __raw_writel(GEMINI_PCI_IOSIZE_1M, PCI_IOSIZE_REG); ++ ++ /* setup hostbridge */ ++ cmd = __raw_readl(PCI_CTRL_REG); ++ cmd |= PCI_COMMAND_IO; ++ cmd |= PCI_COMMAND_MEMORY; ++ cmd |= PCI_COMMAND_MASTER; ++ __raw_writel(cmd, PCI_CTRL_REG); ++ ++ return 1; ++} ++ ++static struct pci_bus* __init gemini_pci_scan_bus(int nr, struct pci_sys_data* sys) ++{ ++ unsigned int reg = 0; ++ struct pci_bus* bus = 0; ++ ++ bus = pci_scan_bus(nr, &gemini_pci_ops, sys); ++ if (bus) { ++ dev_dbg(&bus->dev, "setting up PCI DMA\n"); ++ reg = (GEMINI_PCI_DMA_MEM1_BASE & GEMINI_PCI_DMA_MASK) ++ | (GEMINI_PCI_DMA_MEM1_SIZE << 16); ++ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM1_BASE_SIZE, 4, reg); ++ reg = (GEMINI_PCI_DMA_MEM2_BASE & GEMINI_PCI_DMA_MASK) ++ | (GEMINI_PCI_DMA_MEM2_SIZE << 16); ++ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM2_BASE_SIZE, 4, reg); ++ reg = (GEMINI_PCI_DMA_MEM3_BASE & GEMINI_PCI_DMA_MASK) ++ | (GEMINI_PCI_DMA_MEM3_SIZE << 16); ++ gemini_pci_write_config(bus, 0, GEMINI_PCI_MEM3_BASE_SIZE, 4, reg); ++ } ++ ++ return bus; ++} ++ ++/* Should work with all boards based on original Storlink EVB */ ++static int __init gemini_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot < 9 || slot > 12) ++ return -1; ++ ++ return PCI_IRQ_BASE + (((slot - 9) + (pin - 1)) & 0x3); ++} ++ ++static struct hw_pci gemini_hw_pci __initdata = { ++ .nr_controllers = 1, ++ .setup = gemini_pci_setup, ++ .scan = gemini_pci_scan_bus, ++ .map_irq = gemini_pci_map_irq, ++}; ++ ++/* we need this for muxed PCI interrupts handling */ ++static struct pci_bus bogus_pci_bus; ++ ++static void gemini_pci_ack_irq(struct irq_data *d) ++{ ++ unsigned int irq = d->irq; ++ unsigned int reg; ++ ++ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®); ++ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET); ++ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTSTS_OFFSET); ++ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg); ++} ++ ++static void gemini_pci_mask_irq(struct irq_data *d) ++{ ++ unsigned int irq = d->irq; ++ unsigned int reg; ++ ++ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®); ++ reg &= ~((0xF << PCI_CTRL2_INTSTS_OFFSET) ++ | (1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET))); ++ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg); ++} ++ ++static void gemini_pci_unmask_irq(struct irq_data *d) ++{ ++ unsigned int irq = d->irq; ++ unsigned int reg; ++ ++ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®); ++ reg &= ~(0xF << PCI_CTRL2_INTSTS_OFFSET); ++ reg |= 1 << (irq - PCI_IRQ_BASE + PCI_CTRL2_INTMASK_OFFSET); ++ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, reg); ++} ++ ++static void gemini_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ unsigned int pci_irq_no, irq_stat, reg, i; ++ ++ gemini_pci_read_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2, 4, ®); ++ irq_stat = reg >> PCI_CTRL2_INTSTS_OFFSET; ++ ++ for (i = 0; i < 4; i++) { ++ ++ if ((irq_stat & (1 << i)) == 0) ++ continue; ++ ++ pci_irq_no = PCI_IRQ_BASE + i; ++ ++ BUG_ON(!(irq_desc[pci_irq_no].handle_irq)); ++ irq_desc[pci_irq_no].handle_irq(pci_irq_no, ++ &irq_desc[pci_irq_no]); ++ } ++} ++ ++static struct irq_chip gemini_pci_irq_chip = { ++ .name = "PCI", ++ .irq_ack = gemini_pci_ack_irq, ++ .irq_mask = gemini_pci_mask_irq, ++ .irq_unmask = gemini_pci_unmask_irq, ++}; ++ ++static int __init gemini_pci_init(void) ++{ ++ int i; ++ ++ for (i = 72; i <= 95; i++) ++ gpio_request(i, "PCI"); ++ ++ /* initialize our bogus bus */ ++ dev_set_name(&bogus_pci_bus.dev, "PCI IRQ handler"); ++ bogus_pci_bus.number = 0; ++ ++ /* mask and clear all interrupts */ ++ gemini_pci_write_config(&bogus_pci_bus, 0, GEMINI_PCI_CTRL2 + 2, 2, ++ 0xF000); ++ ++ for (i = PCI_IRQ_BASE; i < PCI_IRQ_BASE + 4; i++) { ++ irq_set_chip_and_handler(i, &gemini_pci_irq_chip, ++ handle_level_irq); ++ set_irq_flags(i, IRQF_VALID); ++ } ++ ++ irq_set_chained_handler(IRQ_PCI, gemini_pci_irq_handler); ++ ++ pci_common_init(&gemini_hw_pci); ++ ++ return 0; ++} ++ ++subsys_initcall(gemini_pci_init); diff --git a/target/linux/gemini/patches-4.1/150-gemini-pata.patch b/target/linux/gemini/patches-4.1/150-gemini-pata.patch new file mode 100644 index 0000000..b3e0237 --- /dev/null +++ b/target/linux/gemini/patches-4.1/150-gemini-pata.patch @@ -0,0 +1,192 @@ +--- a/arch/arm/mach-gemini/include/mach/global_reg.h ++++ b/arch/arm/mach-gemini/include/mach/global_reg.h +@@ -227,7 +227,13 @@ + #define USB0_PLUG_MINIB (1 << 29) + #define GMAC_GMII (1 << 28) + #define GMAC_1_ENABLE (1 << 27) +-/* TODO: define ATA/SATA bits */ ++/* 011 - ata0 <-> sata0, sata1; bring out ata1 ++ * 010 - ata1 <-> sata1, sata0; bring out ata0 ++ * 001 - ata0 <-> sata0, ata1 <-> sata1; bring out ata1 ++ * 000 - ata0 <-> sata0, ata1 <-> sata1; bring out ata0 */ ++#define IDE_IOMUX_MASK (7 << 24) ++#define IDE_IOMUX_SATA1_SATA0 (2 << 24) ++#define IDE_IOMUX_SATA0_SATA1 (3 << 24) + #define USB1_VBUS_ON (1 << 23) + #define USB0_VBUS_ON (1 << 22) + #define APB_CLKOUT_ENABLE (1 << 21) +--- a/arch/arm/mach-gemini/irq.c ++++ b/arch/arm/mach-gemini/irq.c +@@ -89,6 +89,9 @@ void __init gemini_init_irq(void) + irq_set_handler(i, handle_edge_irq); + mode |= 1 << i; + level |= 1 << i; ++ } else if (i >= IRQ_IDE0 && i <= IRQ_IDE1) { ++ irq_set_handler(i, handle_edge_irq); ++ mode |= 1 << i; + } else { + irq_set_handler(i, handle_level_irq); + } +--- a/arch/arm/mach-gemini/common.h ++++ b/arch/arm/mach-gemini/common.h +@@ -31,6 +31,7 @@ extern int platform_register_pflash(unsi + extern int platform_register_watchdog(void); + extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata); + extern int platform_register_usb(unsigned int id); ++extern int platform_register_pata(unsigned int id); + + extern void gemini_restart(enum reboot_mode mode, const char *cmd); + +--- a/arch/arm/mach-gemini/devices.c ++++ b/arch/arm/mach-gemini/devices.c +@@ -249,3 +249,67 @@ int __init platform_register_usb(unsigne + return platform_device_register(&usb_device[id]); + } + ++static u64 pata_gemini_dmamask0 = 0xffffffffUL; ++static u64 pata_gemini_dmamask1 = 0xffffffffUL; ++ ++static struct resource pata_gemini_resources0[] = ++{ ++ [0] = { ++ .start = GEMINI_IDE0_BASE, ++ .end = GEMINI_IDE0_BASE + 0x40, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_IDE0, ++ .end = IRQ_IDE0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource pata_gemini_resources1[] = ++{ ++ [0] = { ++ .start = GEMINI_IDE1_BASE, ++ .end = GEMINI_IDE1_BASE + 0x40, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_IDE1, ++ .end = IRQ_IDE1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct platform_device pata_gemini_devices[] = ++{ ++ { ++ .name = "pata-gemini", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &pata_gemini_dmamask0, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(pata_gemini_resources0), ++ .resource = pata_gemini_resources0, ++ }, ++ { ++ .name = "pata-gemini", ++ .id = 1, ++ .dev = ++ { ++ .dma_mask = &pata_gemini_dmamask1, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(pata_gemini_resources1), ++ .resource = pata_gemini_resources1, ++ }, ++}; ++ ++int __init platform_register_pata(unsigned int id) ++{ ++ if (id > 1) ++ return -EINVAL; ++ ++ return platform_device_register(&pata_gemini_devices[id]); ++} +--- a/arch/arm/mach-gemini/mm.c ++++ b/arch/arm/mach-gemini/mm.c +@@ -24,6 +24,11 @@ static struct map_desc gemini_io_desc[] + .length = SZ_512K, + .type = MT_DEVICE, + }, { ++ .virtual = (unsigned long)IO_ADDRESS(GEMINI_SATA_BASE), ++ .pfn = __phys_to_pfn(GEMINI_SATA_BASE), ++ .length = SZ_512K, ++ .type = MT_DEVICE, ++ }, { + .virtual = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE), + .pfn = __phys_to_pfn(GEMINI_UART_BASE), + .length = SZ_512K, +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -537,6 +537,16 @@ config PATA_EP93XX + + If unsure, say N. + ++config PATA_GEMINI ++ tristate "Gemini PATA support (Experimental)" ++ depends on ARCH_GEMINI ++ help ++ This option enables support for the Gemini PATA-Controller. ++ Note that the Gemini SoC has no native SATA-Controller but an ++ onboard PATA-SATA bridge. ++ ++ If unsure, say N. ++ + config PATA_HPT366 + tristate "HPT 366/368 PATA support" + depends on PCI +--- a/drivers/ata/Makefile ++++ b/drivers/ata/Makefile +@@ -53,6 +53,7 @@ obj-$(CONFIG_PATA_CS5536) += pata_cs5536 + obj-$(CONFIG_PATA_CYPRESS) += pata_cypress.o + obj-$(CONFIG_PATA_EFAR) += pata_efar.o + obj-$(CONFIG_PATA_EP93XX) += pata_ep93xx.o ++obj-$(CONFIG_PATA_GEMINI) += pata_gemini.o + obj-$(CONFIG_PATA_HPT366) += pata_hpt366.o + obj-$(CONFIG_PATA_HPT37X) += pata_hpt37x.o + obj-$(CONFIG_PATA_HPT3X2N) += pata_hpt3x2n.o +--- a/arch/arm/mach-gemini/board-nas4220b.c ++++ b/arch/arm/mach-gemini/board-nas4220b.c +@@ -146,11 +146,28 @@ static void __init usb_ib4220b_init(void + GLOBAL_MISC_CTRL)); + } + ++static void __init sata_ib4220b_init(void) ++{ ++ unsigned val; ++ ++ val = readl((void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ val &= ~(IDE_IOMUX_MASK | PFLASH_PADS_DISABLE); ++ val |= IDE_PADS_ENABLE; ++ writel(val, (void __iomem*)(IO_ADDRESS(GEMINI_GLOBAL_BASE) + ++ GLOBAL_MISC_CTRL)); ++ ++ /* enabling ports for presence detection, master only */ ++ writel(0x00000001, (void __iomem*)(IO_ADDRESS(GEMINI_SATA_BASE) + 0x18)); ++ writel(0x00000001, (void __iomem*)(IO_ADDRESS(GEMINI_SATA_BASE) + 0x1c)); ++} ++ + static void __init ib4220b_init(void) + { + gemini_gpio_init(); + ib4220b_gmac_init(); + usb_ib4220b_init(); ++ sata_ib4220b_init(); + platform_register_uart(); + platform_register_pflash(SZ_16M, NULL, 0); + platform_device_register(&ib4220b_led_device); +@@ -161,6 +178,8 @@ static void __init ib4220b_init(void) + platform_register_ethernet(&ib4220b_gmac_data); + platform_register_usb(0); + platform_register_usb(1); ++ platform_register_pata(0); ++ platform_register_pata(1); + } + + MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") diff --git a/target/linux/gemini/patches-4.1/160-gemini-timers.patch b/target/linux/gemini/patches-4.1/160-gemini-timers.patch new file mode 100644 index 0000000..d7c8f86 --- /dev/null +++ b/target/linux/gemini/patches-4.1/160-gemini-timers.patch @@ -0,0 +1,242 @@ +--- a/arch/arm/mach-gemini/time.c ++++ b/arch/arm/mach-gemini/time.c +@@ -15,15 +15,18 @@ + #include + #include + #include ++#include + + /* + * Register definitions for the timers + */ +-#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00) +-#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04) +-#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08) +-#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C) +-#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30) ++#define TIMER_COUNT(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x00) ++#define TIMER_LOAD(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x04) ++#define TIMER_MATCH1(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x08) ++#define TIMER_MATCH2(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x0C) ++#define TIMER_CR(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x30) ++#define TIMER_INTR_STATE(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x34) ++#define TIMER_INTR_MASK(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x38) + + #define TIMER_1_CR_ENABLE (1 << 0) + #define TIMER_1_CR_CLOCK (1 << 1) +@@ -34,27 +37,38 @@ + #define TIMER_3_CR_ENABLE (1 << 6) + #define TIMER_3_CR_CLOCK (1 << 7) + #define TIMER_3_CR_INT (1 << 8) ++#define TIMER_1_CR_UPDOWN (1 << 9) ++#define TIMER_2_CR_UPDOWN (1 << 10) ++#define TIMER_3_CR_UPDOWN (1 << 11) ++ ++#define TIMER_1_INT_MATCH1 (1 << 0) ++#define TIMER_1_INT_MATCH2 (1 << 1) ++#define TIMER_1_INT_OVERFLOW (1 << 2) ++#define TIMER_2_INT_MATCH1 (1 << 3) ++#define TIMER_2_INT_MATCH2 (1 << 4) ++#define TIMER_2_INT_OVERFLOW (1 << 5) ++#define TIMER_3_INT_MATCH1 (1 << 6) ++#define TIMER_3_INT_MATCH2 (1 << 7) ++#define TIMER_3_INT_OVERFLOW (1 << 8) ++#define TIMER_INT_ALL_MASK 0x1ff + + static unsigned int tick_rate; + ++static u64 notrace gemini_read_sched_clock(void) ++{ ++ return readl(TIMER_COUNT(GEMINI_TIMER3_BASE)); ++} ++ + static int gemini_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) + { + u32 cr; + +- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- +- /* This may be overdoing it, feel free to test without this */ +- cr &= ~TIMER_2_CR_ENABLE; +- cr &= ~TIMER_2_CR_INT; +- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- +- /* Set next event */ +- writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); +- writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); +- cr |= TIMER_2_CR_ENABLE; +- cr |= TIMER_2_CR_INT; +- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); ++ /* Setup the match register */ ++ cr = readl(TIMER_COUNT(GEMINI_TIMER1_BASE)); ++ writel(cr + cycles, TIMER_MATCH1(GEMINI_TIMER1_BASE)); ++ if (readl(TIMER_COUNT(GEMINI_TIMER1_BASE)) - cr > cycles) ++ return -ETIME; + + return 0; + } +@@ -66,48 +80,68 @@ static void gemini_timer_set_mode(enum c + u32 cr; + + switch (mode) { +- case CLOCK_EVT_MODE_PERIODIC: +- /* Start the timer */ +- writel(period, +- TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); +- writel(period, +- TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); +- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- cr |= TIMER_2_CR_ENABLE; +- cr |= TIMER_2_CR_INT; +- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); ++ case CLOCK_EVT_MODE_PERIODIC: ++ /* Stop timer and interrupt. */ ++ cr = readl(TIMER_CR(GEMINI_TIMER_BASE)); ++ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); ++ writel(cr, TIMER_CR(GEMINI_TIMER_BASE)); ++ ++ /* Setup timer to fire at 1/HZ intervals. */ ++ cr = 0xffffffff - (period - 1); ++ writel(cr, TIMER_COUNT(GEMINI_TIMER1_BASE)); ++ writel(cr, TIMER_LOAD(GEMINI_TIMER1_BASE)); ++ ++ /* enable interrupt on overflaw */ ++ cr = readl(TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); ++ cr |= TIMER_1_INT_OVERFLOW; ++ writel(cr, TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ ++ /* start the timer */ ++ cr = readl(TIMER_CR(GEMINI_TIMER_BASE)); ++ cr |= TIMER_1_CR_ENABLE | TIMER_1_CR_INT; ++ writel(cr, TIMER_CR(GEMINI_TIMER_BASE)); + break; ++ + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: +- case CLOCK_EVT_MODE_SHUTDOWN: ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ /* Stop timer and interrupt. */ ++ cr = readl(TIMER_CR(GEMINI_TIMER_BASE)); ++ cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); ++ writel(cr, TIMER_CR(GEMINI_TIMER_BASE)); ++ ++ /* Setup counter start from 0 */ ++ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE)); ++ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE)); ++ ++ /* enable interrupt */ ++ cr = readl(TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); ++ cr |= TIMER_1_INT_MATCH1; ++ writel(cr, TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ ++ /* start the timer */ ++ cr = readl(TIMER_CR(GEMINI_TIMER_BASE)); ++ cr |= TIMER_1_CR_ENABLE; ++ writel(cr, TIMER_CR(GEMINI_TIMER_BASE)); ++ break; ++ + case CLOCK_EVT_MODE_RESUME: +- /* +- * Disable also for oneshot: the set_next() call will +- * arm the timer instead. +- */ +- cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- cr &= ~TIMER_2_CR_ENABLE; +- cr &= ~TIMER_2_CR_INT; +- writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); + break; +- default: +- break; + } + } + +-/* Use TIMER2 as clock event */ + static struct clock_event_device gemini_clockevent = { +- .name = "TIMER2", +- .rating = 300, /* Reasonably fast and accurate clock event */ +- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, +- .set_next_event = gemini_timer_set_next_event, +- .set_mode = gemini_timer_set_mode, ++ .name = "gemini_timer_1", ++ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, ++ .shift = 32, ++ .rating = 300, ++ .set_next_event = gemini_timer_set_next_event, ++ .set_mode = gemini_timer_set_mode, + }; + +-/* +- * IRQ handler for the timer +- */ +-static irqreturn_t gemini_timer_interrupt(int irq, void *dev_id) ++static irqreturn_t gemini_timer_intr(int irq, void *dev_id) + { + struct clock_event_device *evt = &gemini_clockevent; + +@@ -116,14 +150,11 @@ static irqreturn_t gemini_timer_interrup + } + + static struct irqaction gemini_timer_irq = { +- .name = "Gemini Timer Tick", ++ .name = "gemini timer 1", + .flags = IRQF_TIMER, +- .handler = gemini_timer_interrupt, ++ .handler = gemini_timer_intr, + }; + +-/* +- * Set up timer interrupt, and return the current time in seconds. +- */ + void __init gemini_timer_init(void) + { + u32 reg_v; +@@ -151,20 +182,35 @@ void __init gemini_timer_init(void) + } + + /* +- * Make irqs happen for the system timer ++ * Reset the interrupt mask and status + */ +- setup_irq(IRQ_TIMER2, &gemini_timer_irq); ++ writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK(GEMINI_TIMER_BASE)); ++ writel(0, TIMER_INTR_STATE(GEMINI_TIMER_BASE)); ++ writel(TIMER_1_CR_UPDOWN | TIMER_3_CR_ENABLE | TIMER_3_CR_UPDOWN, ++ TIMER_CR(GEMINI_TIMER_BASE)); + +- /* Enable and use TIMER1 as clock source */ +- writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE))); +- writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE))); +- writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); +- if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)), +- "TIMER1", tick_rate, 300, 32, +- clocksource_mmio_readl_up)) +- pr_err("timer: failed to initialize gemini clock source\n"); ++ /* ++ * Setup free-running clocksource timer (interrupts ++ * disabled.) ++ */ ++ writel(0, TIMER_COUNT(GEMINI_TIMER3_BASE)); ++ writel(0, TIMER_LOAD(GEMINI_TIMER3_BASE)); ++ writel(0, TIMER_MATCH1(GEMINI_TIMER3_BASE)); ++ writel(0, TIMER_MATCH2(GEMINI_TIMER3_BASE)); ++ clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER3_BASE), ++ "gemini_clocksource", tick_rate, ++ 300, 32, clocksource_mmio_readl_up); ++ sched_clock_register(gemini_read_sched_clock, 32, tick_rate); + +- /* Configure and register the clockevent */ ++ /* ++ * Setup clockevent timer (interrupt-driven.) ++ */ ++ writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE)); ++ writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE)); ++ writel(0, TIMER_MATCH1(GEMINI_TIMER1_BASE)); ++ writel(0, TIMER_MATCH2(GEMINI_TIMER1_BASE)); ++ setup_irq(IRQ_TIMER1, &gemini_timer_irq); ++ gemini_clockevent.cpumask = cpumask_of(0); + clockevents_config_and_register(&gemini_clockevent, tick_rate, + 1, 0xffffffff); + } diff --git a/target/linux/gemini/raidsonic/config-3.18 b/target/linux/gemini/raidsonic/config-3.18 new file mode 100644 index 0000000..9160523 --- /dev/null +++ b/target/linux/gemini/raidsonic/config-3.18 @@ -0,0 +1,5 @@ +CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=128M mtdparts=physmap-flash.0:128k(BOOT),3072k(Kern),6144k(Ramdisk),6144k(Application),128k(VCTL),640k(CurConf),128k(FIS-directory),12288k@0x320000(rootfs),15360k@0x20000(firmware) root=/dev/mtdblock7" +CONFIG_MACH_NAS4220B=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_SPLIT_FIRMWARE=y diff --git a/target/linux/gemini/raidsonic/config-4.1 b/target/linux/gemini/raidsonic/config-4.1 new file mode 100644 index 0000000..9160523 --- /dev/null +++ b/target/linux/gemini/raidsonic/config-4.1 @@ -0,0 +1,5 @@ +CONFIG_CMDLINE="rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=128M mtdparts=physmap-flash.0:128k(BOOT),3072k(Kern),6144k(Ramdisk),6144k(Application),128k(VCTL),640k(CurConf),128k(FIS-directory),12288k@0x320000(rootfs),15360k@0x20000(firmware) root=/dev/mtdblock7" +CONFIG_MACH_NAS4220B=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_SPLIT_FIRMWARE=y diff --git a/target/linux/gemini/raidsonic/target.mk b/target/linux/gemini/raidsonic/target.mk new file mode 100644 index 0000000..d158090 --- /dev/null +++ b/target/linux/gemini/raidsonic/target.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2014 OpenWrt.org +# + +SUBTARGET:=raidsonic +BOARDNAME:=Raidsonic NAS42x0 +FEATURES+=usb +DEFAULT_PACKAGES+=kmod-usb2 kmod-md-mod kmod-md-linear kmod-md-multipath \ + kmod-md-raid0 kmod-md-raid1 kmod-md-raid10 kmod-md-raid456 \ + kmod-fs-btrfs kmod-fs-cifs kmod-fs-ext4 kmod-fs-nfs \ + kmod-fs-nfsd kmod-fs-ntfs kmod-fs-reiserfs kmod-fs-vfat \ + kmod-nls-utf8 kmod-usb-storage-extras \ + samba36-server mdadm cfdisk fdisk e2fsprogs badblocks + +define Target/Description + Build firmware images for Raidsonic NAS4220. +endef diff --git a/target/linux/gemini/wiligear/target.mk b/target/linux/gemini/wiligear/target.mk new file mode 100644 index 0000000..97cab18 --- /dev/null +++ b/target/linux/gemini/wiligear/target.mk @@ -0,0 +1,10 @@ +# +# Copyright (C) 2014 OpenWrt.org +# + +SUBTARGET:=wiligear +BOARDNAME:=Wiligear WBD-222/111 + +define Target/Description + Build firmware images for Wiligear WBD-222 and WBD-111 boards. +endef diff --git a/target/linux/generic/PATCHES b/target/linux/generic/PATCHES new file mode 100644 index 0000000..86ced46 --- /dev/null +++ b/target/linux/generic/PATCHES @@ -0,0 +1,20 @@ +The patches-* subdirectories contain the kernel patches applied for every +OpenWrt target. All patches should be named 'NNN-lowercase_shortname.patch' +and sorted into the following categories: + +0xx - upstream backports +1xx - code awaiting upstream merge +2xx - kernel build / config / header patches +3xx - architecture specific patches +4xx - mtd related patches (subsystem and drivers) +5xx - filesystem related patches +6xx - generic network patches +7xx - network / phy driver patches +8xx - other drivers +9xx - uncategorized other patches + +ALL patches must be in a way that they are potentially upstreamable, meaning: + +- they must contain a proper subject +- they must contain a proper commit message explaining what they change +- they must contain a valid Signed-off-by line diff --git a/target/linux/generic/base-files/init b/target/linux/generic/base-files/init new file mode 100755 index 0000000..514be57 --- /dev/null +++ b/target/linux/generic/base-files/init @@ -0,0 +1,4 @@ +#!/bin/sh +# Copyright (C) 2006 OpenWrt.org +export INITRAMFS=1 +exec /sbin/init diff --git a/target/linux/generic/config-3.18 b/target/linux/generic/config-3.18 new file mode 100644 index 0000000..8649b8e --- /dev/null +++ b/target/linux/generic/config-3.18 @@ -0,0 +1,4647 @@ +CONFIG_32BIT=y +# CONFIG_6LOWPAN is not set +# CONFIG_6PACK is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_9P_FS is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_AB8500_CORE is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_ACENIC is not set +# CONFIG_ACERHDF is not set +# CONFIG_ACORN_PARTITION is not set +# CONFIG_ACPI_APEI is not set +# CONFIG_ACPI_CUSTOM_METHOD is not set +# CONFIG_ACPI_EXTLOG is not set +# CONFIG_ACPI_HED is not set +# CONFIG_ACPI_INT3403_THERMAL is not set +# CONFIG_ACPI_POWER_METER is not set +# CONFIG_ACPI_QUICKSTART is not set +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +# CONFIG_AD5064 is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686 is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5930 is not set +# CONFIG_AD5933 is not set +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD7746 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD799X is not set +# CONFIG_AD8366 is not set +# CONFIG_AD9523 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16255 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_ADM6996_PHY is not set +# CONFIG_ADM8211 is not set +# CONFIG_ADT7316 is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_ADXRS450 is not set +CONFIG_AEABI=y +# CONFIG_AFFS_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AGP is not set +# CONFIG_AHCI_MVEBU is not set +CONFIG_AIO=y +# CONFIG_AIRO is not set +# CONFIG_AIRO_CS is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_AK09911 is not set +# CONFIG_AK8975 is not set +# CONFIG_AL3320A is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_ALIM7101_WDT is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_ALTERA_STAPL is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_ALX is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_AMD_XGBE is not set +# CONFIG_AMD_XGBE_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_AMILO_RFKILL is not set +# CONFIG_ANDROID is not set +CONFIG_ANON_INODES=y +# CONFIG_APDS9300 is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_APM8018X is not set +# CONFIG_APPLICOM is not set +# CONFIG_AR5523 is not set +# CONFIG_AR7 is not set +# CONFIG_AR8216_PHY is not set +# CONFIG_AR8216_PHY_LEDS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_EXYNOS is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +# CONFIG_ARCH_HI3xxx is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_MSM_DT is not set +# CONFIG_ARCH_MSM_NODT is not set +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_MULTI_V6 is not set +# CONFIG_ARCH_MULTI_V7 is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_NSPIRE is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2PLUS is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_SHMOBILE_LEGACY is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_WM8505 is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCNET is not set +# CONFIG_ARC_EMAC is not set +# CONFIG_ARM_APPENDED_DTB is not set +# CONFIG_ARM_ARCH_TIMER is not set +# CONFIG_ARM_AT91_ETHER is not set +# CONFIG_ARM_CCI is not set +# CONFIG_ARM_CCN is not set +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_ARM_ERRATA_326103 is not set +# CONFIG_ARM_ERRATA_364296 is not set +# CONFIG_ARM_ERRATA_411920 is not set +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_643719 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_KPROBES_TEST is not set +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +# CONFIG_ARM_PSCI is not set +# CONFIG_ARM_PTDUMP is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_ARM_VIRT_EXT is not set +CONFIG_ARPD=y +# CONFIG_ARTHUR is not set +# CONFIG_AS3935 is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set +# CONFIG_ASYNC_RAID6_TEST is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_ATA is not set +# CONFIG_ATAGS is not set +CONFIG_ATAGS_PROC=y +# CONFIG_ATALK is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_ATA_ACPI is not set +CONFIG_ATA_BMDMA=y +# CONFIG_ATA_GENERIC is not set +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_ATA_PIIX is not set +CONFIG_ATA_SFF=y +# CONFIG_ATA_VERBOSE_ERROR is not set +# CONFIG_ATH10K is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH6KL is not set +# CONFIG_ATH6K_LEGACY is not set +# CONFIG_ATH79 is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_ATH_CARDS is not set +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1C is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL2 is not set +# CONFIG_ATM is not set +# CONFIG_ATMEL is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ATM_AMBASSADOR is not set +# CONFIG_ATM_BR2684 is not set +CONFIG_ATM_BR2684_IPFILTER=y +# CONFIG_ATM_CLIP is not set +CONFIG_ATM_CLIP_NO_ICMP=y +# CONFIG_ATM_DRIVERS is not set +# CONFIG_ATM_DUMMY is not set +# CONFIG_ATM_ENI is not set +# CONFIG_ATM_FIRESTREAM is not set +# CONFIG_ATM_FORE200E is not set +# CONFIG_ATM_HE is not set +# CONFIG_ATM_HORIZON is not set +# CONFIG_ATM_IA is not set +# CONFIG_ATM_IDT77252 is not set +# CONFIG_ATM_LANAI is not set +# CONFIG_ATM_LANE is not set +# CONFIG_ATM_MPOA is not set +# CONFIG_ATM_NICSTAR is not set +# CONFIG_ATM_SOLOS is not set +# CONFIG_ATM_TCP is not set +# CONFIG_ATM_ZATM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ATP is not set +# CONFIG_AUDIT is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTO_ZRELADDR is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_AVERAGE is not set +# CONFIG_AX25 is not set +# CONFIG_AX25_DAMA_SLAVE is not set +# CONFIG_AX88796 is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_B44 is not set +# CONFIG_B53 is not set +# CONFIG_B53_SPI_DRIVER is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_BACKLIGHT_LM3630 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_PANDORA is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +CONFIG_BASE_FULL=y +CONFIG_BASE_SMALL=0 +# CONFIG_BATMAN_ADV is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BAYCOM_EPP is not set +# CONFIG_BAYCOM_PAR is not set +# CONFIG_BAYCOM_SER_FDX is not set +# CONFIG_BAYCOM_SER_HDX is not set +# CONFIG_BCACHE is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_BCM63XX_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BCMA is not set +# CONFIG_BCMA_DRIVER_GPIO is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMGENET is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BE2NET is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_BGMAC is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_BIG_LITTLE is not set +# CONFIG_BINARY_PRINTF is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_CPQ_DA is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_ATIIXP is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_CS5535 is not set +# CONFIG_BLK_DEV_CS5536 is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_DELKIN is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_IDEACPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDECS is not set +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_BLK_DEV_IDEPNP is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDE_AU1XXX is not set +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RZ1000 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_SD is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SIS5513 is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SL82C105 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_BLK_DEV_THROTTLING is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_UMC8672 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLOCK=y +# CONFIG_BMA180 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_BMG160 is not set +# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_BNA is not set +# CONFIG_BNX2 is not set +# CONFIG_BNX2X is not set +# CONFIG_BONDING is not set +# CONFIG_BOOKE_WDT is not set +CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_BOOT_RAW=y +# CONFIG_BPCTL is not set +CONFIG_BPF=y +# CONFIG_BPF_JIT is not set +CONFIG_BPF_SYSCALL=y +# CONFIG_BPQETHER is not set +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_BRCMFMAC is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMSTB_GISB_ARB is not set +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_EBT_802_3 is not set +# CONFIG_BRIDGE_EBT_AMONG is not set +# CONFIG_BRIDGE_EBT_ARP is not set +# CONFIG_BRIDGE_EBT_ARPREPLY is not set +# CONFIG_BRIDGE_EBT_BROUTE is not set +# CONFIG_BRIDGE_EBT_DNAT is not set +# CONFIG_BRIDGE_EBT_IP is not set +# CONFIG_BRIDGE_EBT_IP6 is not set +# CONFIG_BRIDGE_EBT_LIMIT is not set +# CONFIG_BRIDGE_EBT_LOG is not set +# CONFIG_BRIDGE_EBT_MARK is not set +# CONFIG_BRIDGE_EBT_MARK_T is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_BRIDGE_EBT_PKTTYPE is not set +# CONFIG_BRIDGE_EBT_REDIRECT is not set +# CONFIG_BRIDGE_EBT_SNAT is not set +# CONFIG_BRIDGE_EBT_STP is not set +# CONFIG_BRIDGE_EBT_T_FILTER is not set +# CONFIG_BRIDGE_EBT_T_NAT is not set +# CONFIG_BRIDGE_EBT_ULOG is not set +# CONFIG_BRIDGE_EBT_VLAN is not set +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_NETFILTER is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BROADCOM_PHY is not set +CONFIG_BROKEN_ON_SMP=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_BT is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BT_ATH3K is not set +# CONFIG_BT_BNEP is not set +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +# CONFIG_BT_CMTP is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIBLUECARD is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBT3C is not set +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIBTUART is not set +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIDTL1 is not set +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIUART_3WIRE is not set +# CONFIG_BT_HCIUART_ATH3K is not set +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_HIDP is not set +CONFIG_BT_L2CAP=y +# CONFIG_BT_MRVL is not set +# CONFIG_BT_RFCOMM is not set +# CONFIG_BUILD_BIN2C is not set +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_SCO=y +CONFIG_BUG=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +# CONFIG_C2PORT is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_CAIF is not set +# CONFIG_CAN is not set +# CONFIG_CAN_GS_USB is not set +# CONFIG_CAN_M_CAN is not set +# CONFIG_CAN_RCAR is not set +# CONFIG_CAPI_AVM is not set +# CONFIG_CAPI_EICON is not set +# CONFIG_CAPI_TRACE is not set +CONFIG_CARDBUS=y +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_CARL9170 is not set +# CONFIG_CARMA_FPGA is not set +# CONFIG_CARMA_FPGA_PROGRAM is not set +# CONFIG_CASSINI is not set +CONFIG_CAVIUM_OCTEON_HELPER=y +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_SOC is not set +# CONFIG_CB710_CORE is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_CED1401 is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_CFG80211 is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_WEXT is not set +# CONFIG_CGROUPS is not set +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_CHARGER_TWL4030 is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CIFS is not set +# CONFIG_CIFS_ACL is not set +# CONFIG_CIFS_DEBUG is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_NFSD_EXPORT is not set +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB2 is not set +CONFIG_CIFS_STATS=y +# CONFIG_CIFS_STATS2 is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CLEANCACHE is not set +# CONFIG_CLKSRC_VERSATILE is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CM32181 is not set +# CONFIG_CM36651 is not set +# CONFIG_CMA is not set +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_CMDLINE_FROM_BOOTLOADER is not set +# CONFIG_CMDLINE_PARTITION is not set +# CONFIG_CNIC is not set +# CONFIG_CODA_FS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_COMEDI is not set +# CONFIG_COMMON_CLK_DEBUG is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_QCOM is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMPACTION is not set +# CONFIG_COMPAL_LAPTOP is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPILE_TEST is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_CONNECTOR is not set +CONFIG_CONSTRUCTORS=y +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_COPS is not set +# CONFIG_CORDIC is not set +# CONFIG_COREDUMP is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set +# CONFIG_CPU_IDLE_GOV_MENU is not set +# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set +# CONFIG_CRAMFS is not set +CONFIG_CRASHLOG=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_CRC32_BIT is not set +CONFIG_CRC32_SARWATE=y +# CONFIG_CRC32_SELFTEST is not set +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SLICEBY8 is not set +# CONFIG_CRC7 is not set +# CONFIG_CRC8 is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CROSS_COMPILE="" +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_AEAD is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_586 is not set +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_AES_ARM_BS is not set +# CONFIG_CRYPTO_AES_NI_INTEL is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32C_INTEL is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_DEV_ATMEL_AES is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set +# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM is not set +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO_DEV_MV_CESA is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QCE is not set +# CONFIG_CRYPTO_DEV_SAHARA is not set +# CONFIG_CRYPTO_DEV_TALITOS is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set +# CONFIG_CRYPTO_HASH is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_PCOMP is not set +# CONFIG_CRYPTO_PCOMP2 is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_RNG is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SALSA20_586 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_TWOFISH_586 is not set +# CONFIG_CRYPTO_TWOFISH_COMMON is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_XZ is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYSTALHD is not set +# CONFIG_CS5535_MFGPT is not set +# CONFIG_CS89x0 is not set +# CONFIG_CUSE is not set +# CONFIG_CW1200 is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXT1E1 is not set +# CONFIG_CYPRESS_FIRMWARE is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DCB is not set +# CONFIG_DDR is not set +# CONFIG_DE600 is not set +# CONFIG_DE620 is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +CONFIG_DEBUG_INFO_REDUCED=y +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +# CONFIG_DEBUG_LOCKDEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_NX_TEST is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set +# CONFIG_DEBUG_UART_BCM63XX is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_ZBOOT is not set +# CONFIG_DECNET is not set +CONFIG_DEFAULT_CUBIC=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_DEFAULT_NOOP is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_SECURITY="" +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +# CONFIG_DELL_SMO8800 is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_DEVKMEM is not set +CONFIG_DEVPORT=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_DEVTMPFS is not set +# CONFIG_DEVTMPFS_MOUNT is not set +# CONFIG_DGAP is not set +# CONFIG_DGNC is not set +# CONFIG_DGRP is not set +# CONFIG_DHT11 is not set +# CONFIG_DIRECT_IO is not set +CONFIG_DISABLE_DEV_COREDUMP=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set +# CONFIG_DISPLAY_CONNECTOR_DVI is not set +# CONFIG_DISPLAY_CONNECTOR_HDMI is not set +# CONFIG_DISPLAY_ENCODER_TFP410 is not set +# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set +# CONFIG_DISPLAY_PANEL_DPI is not set +# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set +# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_DL2K is not set +# CONFIG_DLM is not set +# CONFIG_DM9000 is not set +# CONFIG_DMADEVICES is not set +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMASCC is not set +# CONFIG_DMATEST is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_ENGINE is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_LOG_USERSPACE is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DNET is not set +# CONFIG_DNOTIFY is not set +# CONFIG_DNS_RESOLVER is not set +CONFIG_DOUBLEFAULT=y +CONFIG_DQL=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_DRM is not set +# CONFIG_DS1682 is not set +# CONFIG_DTLK is not set +# CONFIG_DUMMY is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_DWC3_HOST_USB3_LPM_ENABLE is not set +# CONFIG_DX_SEP is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_E2100 is not set +# CONFIG_EARLY_PRINTK_8250 is not set +# CONFIG_EASYCAP is not set +# CONFIG_ECHO is not set +# CONFIG_ECONET is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_EDAC is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_DIGSY_MTC_CFG is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEXPRESS is not set +# CONFIG_EEXPRESS_PRO is not set +CONFIG_EFI_PARTITION=y +# CONFIG_EFS_FS is not set +# CONFIG_ELF_CORE is not set +# CONFIG_EMAC_ROCKCHIP is not set +CONFIG_EMBEDDED=y +# CONFIG_EM_TIMER_STI is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENC28J60 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_ENIC is not set +# CONFIG_EPAPR_PARAVIRT is not set +# CONFIG_EPIC100 is not set +CONFIG_EPOLL=y +# CONFIG_EQUALIZER is not set +# CONFIG_ET131X is not set +# CONFIG_GATEWORKS_GW16083 is not set +# CONFIG_GLOB_SELFTEST is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_ETH16I is not set +CONFIG_ETHERNET=y +# CONFIG_ETHOC is not set +CONFIG_EVENTFD=y +# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set +# CONFIG_EWRK3 is not set +CONFIG_EXPERIMENTAL=y +CONFIG_EXPERT=y +# CONFIG_EXPORTFS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_DEBUG is not set +# CONFIG_EXT4_FS is not set +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_USE_FOR_EXT23=y +# CONFIG_EXTCON is not set +CONFIG_EXTRA_FIRMWARE="" +CONFIG_EXTRA_TARGETS="" +# CONFIG_EXYNOS_ADC is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FAIR_GROUP_SCHED is not set +# CONFIG_FANOTIFY is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_FS is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_FB is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_DA8XX is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GEODE is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_N411 is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_PS3 is not set +# CONFIG_FB_PXA is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_XGI is not set +# CONFIG_FCOE is not set +# CONFIG_FCOE_FNIC is not set +# CONFIG_FDDI is not set +# CONFIG_FEALNX is not set +# CONFIG_FENCE_TRACE is not set +# CONFIG_FHANDLE is not set +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIREWIRE_SERIAL is not set +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FIXED_PHY is not set +CONFIG_FLATMEM=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_FM10K is not set +# CONFIG_FMC is not set +# CONFIG_FORCEDETH is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_FRAME_POINTER is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_FREEZER is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_FSCACHE is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_XGMAC_MDIO is not set +CONFIG_FSNOTIFY=y +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_FT1000 is not set +# CONFIG_FTGMAC100 is not set +# CONFIG_FTL is not set +# CONFIG_FTMAC100 is not set +# CONFIG_FTRACE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_FUJITSU_TABLET is not set +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_FUSE_FS is not set +# CONFIG_FUSION is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set +# CONFIG_FUSION_SPI is not set +CONFIG_FUTEX=y +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_GACT_PROB=y +# CONFIG_GADGET_UAC1 is not set +# CONFIG_GAMEPORT is not set +# CONFIG_GCOV is not set +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GENEVE is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_GENERIC_CALIBRATE_DELAY=y +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_GENERIC_PHY is not set +CONFIG_GENERIC_TIME=y +# CONFIG_GENWQE is not set +# CONFIG_GFS2_FS is not set +# CONFIG_GIGASET_CAPI is not set +# CONFIG_GIGASET_DEBUG is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_GPIOLIB is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_BCM_KONA is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_ICH is not set +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_RDC321X is not set +# CONFIG_GPIO_SCH is not set +# CONFIG_GPIO_SCH311X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_SYSFS is not set +# CONFIG_GPIO_TS5500 is not set +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_GPIO_WDT is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HAMACHI is not set +# CONFIG_HAMRADIO is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HCALL_STATS is not set +# CONFIG_HDLC is not set +# CONFIG_HDLC_CISCO is not set +# CONFIG_HDLC_FR is not set +# CONFIG_HDLC_PPP is not set +# CONFIG_HDLC_RAW is not set +# CONFIG_HDLC_RAW_ETH is not set +# CONFIG_HDQ_MASTER_OMAP is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_HERMES is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_HFSPLUS_FS_POSIX_ACL is not set +# CONFIG_HFS_FS is not set +# CONFIG_HIBERNATION is not set +# CONFIG_HID is not set +# CONFIG_HIDRAW is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_ACRUX_FF is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_LOGITECH_DJ is not set +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PID is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PS3REMOTE is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_ARVO is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_ROCCAT_KONEPLUS is not set +# CONFIG_HID_ROCCAT_KOVAPLUS is not set +# CONFIG_HID_ROCCAT_PYRA is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HIGHMEM is not set +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIPPI is not set +# CONFIG_HIX5HD2_GMAC is not set +# CONFIG_HMC6352 is not set +# CONFIG_HOSTAP is not set +# CONFIG_HOSTAP_CS is not set +# CONFIG_HOSTAP_PCI is not set +# CONFIG_HOSTAP_PLX is not set +CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HP100 is not set +CONFIG_HPET_MMAP_DEFAULT=y +# CONFIG_HPFS_FS is not set +# CONFIG_HPLAN is not set +# CONFIG_HPLAN_PLUS is not set +# CONFIG_HP_ILO is not set +# CONFIG_HP_WIRELESS is not set +# CONFIG_HSI is not set +# CONFIG_HSR is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_HVC_DCC is not set +# CONFIG_HVC_UDBG is not set +# CONFIG_HWMON is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_HWMON_VID is not set +# CONFIG_HWSPINLOCK_OMAP is not set +CONFIG_HW_PERF_EVENTS=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set +# CONFIG_HW_RANDOM_GEODE is not set +# CONFIG_HW_RANDOM_INTEL is not set +# CONFIG_HW_RANDOM_OMAP3_ROM is not set +# CONFIG_HW_RANDOM_PPC4XX is not set +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_VIA is not set +# CONFIG_HYPERV is not set +# CONFIG_HYSDN is not set +CONFIG_HZ=100 +CONFIG_HZ_100=y +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_48 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_PERIODIC is not set +# CONFIG_I2C is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCA is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_AU1550 is not set +# CONFIG_I2C_BCM2835 is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_ELEKTOR is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_HID is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_IBM_IIC is not set +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +# CONFIG_I2C_MPC is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MV64XXX is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_OCTEON is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PCA_ISA is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_SCMI is not set +# CONFIG_I2C_SH_MOBILE is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_SMBUS is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VERSATILE is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2O is not set +# CONFIG_I40E is not set +# CONFIG_I40EVF is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_I82092 is not set +# CONFIG_I82365 is not set +# CONFIG_IBM_ASM is not set +# CONFIG_IBM_EMAC_DEBUG is not set +# CONFIG_IBM_EMAC_EMAC4 is not set +# CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_EMAC_MAL_COMMON_ERR is not set +# CONFIG_IBM_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_EMAC_RGMII is not set +# CONFIG_IBM_EMAC_TAH is not set +# CONFIG_IBM_EMAC_ZMII is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_ICS932S401 is not set +# CONFIG_IDE is not set +# CONFIG_IDEAPAD_LAPTOP is not set +# CONFIG_IDE_GD is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IEEE802154 is not set +# CONFIG_IEEE802154_FAKEHARD is not set +# CONFIG_IFB is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IIO is not set +# CONFIG_IIO_BUFFER_CB is not set +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_GPIO_TRIGGER is not set +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +# CONFIG_IKCONFIG is not set +# CONFIG_IKCONFIG_PROC is not set +# CONFIG_IMAGE_CMDLINE_HACK is not set +# CONFIG_IMX_IPUV3_CORE is not set +CONFIG_INET=y +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_DIAG is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_TCP_DIAG is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INFINIBAND is not set +# CONFIG_INFTL is not set +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_INITRAMFS_COMPRESSION_NONE=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_INOTIFY_USER=y +# CONFIG_INPUT is not set +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_APANEL is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATLAS_BTNS is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PCSPKR is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_WISTRON_BTNS is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INT340X_THERMAL is not set +# CONFIG_INTEL_IDLE is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_INTEL_MEI_ME is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_INTEL_MIC_CARD is not set +# CONFIG_INTEL_MIC_HOST is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_INTEL_OAKTRAIL is not set +# CONFIG_INTEL_RST is not set +# CONFIG_INTEL_SMARTCONNECT is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_INV_MPU6050_IIO is not set +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_NOOP=y +# CONFIG_IP1000 is not set +# CONFIG_IP17XX_PHY is not set +# CONFIG_IP6_NF_FILTER is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP6_NF_MANGLE is not set +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_NAT is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_TARGET_LOG is not set +# CONFIG_IP6_NF_TARGET_REJECT is not set +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +# CONFIG_IPACK_BUS is not set +# CONFIG_IPC_NS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPV6 is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_ROUTE_INFO is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_SIT_6RD is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_VTI is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2100_DEBUG is not set +CONFIG_IPW2100_MONITOR=y +# CONFIG_IPW2200 is not set +# CONFIG_IPW2200_DEBUG is not set +CONFIG_IPW2200_MONITOR=y +# CONFIG_IPW2200_PROMISCUOUS is not set +# CONFIG_IPW2200_QOS is not set +# CONFIG_IPW2200_RADIOTAP is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_IPX is not set +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_DCCP is not set +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_NF_ARPFILTER is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARP_MANGLE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_SECURITY is not set +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_MASQUERADE is not set +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_REDIRECT is not set +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +# CONFIG_IP_PNP is not set +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_SCTP is not set +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set +# CONFIG_IRDA is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_IRQ_ALL_CPUS is not set +# CONFIG_IRQ_DOMAIN_DEBUG is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_IR_HIX5HD2 is not set +# CONFIG_IR_IGUANA is not set +# CONFIG_IR_IMG is not set +# CONFIG_IR_IMON is not set +# CONFIG_IR_JVC_DECODER is not set +# CONFIG_IR_LIRC_CODEC is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_NEC_DECODER is not set +# CONFIG_IR_RC5_DECODER is not set +# CONFIG_IR_RC5_SZ_DECODER is not set +# CONFIG_IR_RC6_DECODER is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_SONY_DECODER is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_IR_TTUSBIR is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_ISCSI_TCP is not set +CONFIG_ISDN=y +# CONFIG_ISDN_AUDIO is not set +# CONFIG_ISDN_CAPI is not set +# CONFIG_ISDN_CAPI_CAPIDRV is not set +# CONFIG_ISDN_DIVERSION is not set +# CONFIG_ISDN_DRV_ACT2000 is not set +# CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON is not set +# CONFIG_ISDN_DRV_GIGASET is not set +# CONFIG_ISDN_DRV_HISAX is not set +# CONFIG_ISDN_DRV_ICN is not set +# CONFIG_ISDN_DRV_LOOP is not set +# CONFIG_ISDN_DRV_PCBIT is not set +# CONFIG_ISDN_DRV_SC is not set +# CONFIG_ISDN_I4L is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_ISL29125 is not set +# CONFIG_ISO9660_FS is not set +# CONFIG_ISS4xx is not set +# CONFIG_ITG3200 is not set +# CONFIG_IWL3945 is not set +# CONFIG_IWLAGN is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWMC3200TOP is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_JBD is not set +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_POSIX_ACL is not set +# CONFIG_JFFS2_FS_SECURITY is not set +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_LZMA=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_ZLIB is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_JME is not set +CONFIG_JOLIET=y +# CONFIG_JUMP_LABEL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_UNCOMPRESSED is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_MODE_NEON=y +CONFIG_KERNEL_XZ=y +CONFIG_KERNFS=y +# CONFIG_KEXEC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_CAP1106 is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PXA27x is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_SH_KEYSC is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_KGDB is not set +# CONFIG_KMEMCHECK is not set +# CONFIG_KPROBES is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_KSM is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_KVM_GUEST is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_KXSD9 is not set +# CONFIG_L2TP is not set +# CONFIG_L2TP_ETH is not set +# CONFIG_L2TP_IP is not set +# CONFIG_L2TP_V3 is not set +# CONFIG_LANMEDIA is not set +# CONFIG_LANTIQ is not set +# CONFIG_LAPB is not set +# CONFIG_LASAT is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_LBDAF=y +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_LEDS_ATMEL_PWM is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_BLINKM is not set +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_GPIO_OF=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_INTEL_SS4200 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3556 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_NET5501 is not set +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA9685 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_TCA6507 is not set +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +# CONFIG_LEDS_TRIGGER_MORSE is not set +CONFIG_LEDS_TRIGGER_NETDEV=y +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +CONFIG_LEDS_TRIGGER_TIMER=y +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_USBDEV is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LIB80211 is not set +# CONFIG_LIB80211_CRYPT_CCMP is not set +# CONFIG_LIB80211_CRYPT_TKIP is not set +# CONFIG_LIB80211_CRYPT_WEP is not set +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_LIBERTAS_USB is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_LIBIPW_DEBUG is not set +# CONFIG_LINE6_USB is not set +# CONFIG_LIRC_STAGING is not set +# CONFIG_LIS3L02DQ is not set +# CONFIG_LKDTM is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_LOCKD is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_LOGFS is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_LOGO is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +# CONFIG_LOONGSON_MC146818 is not set +# CONFIG_LP486E is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_LP_CONSOLE is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_LTR501 is not set +# CONFIG_LTPC is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_LXT_PHY is not set +CONFIG_LZMA_COMPRESS=y +CONFIG_LZMA_DECOMPRESS=y +# CONFIG_LZO_COMPRESS is not set +# CONFIG_LZO_DECOMPRESS is not set +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +# CONFIG_LZ4HC_COMPRESS is not set +# CONFIG_M25PXX_PREFER_SMALL_SECTOR_ERASE is not set +# CONFIG_MAC80211 is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MACB is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set +# CONFIG_MACH_NO_WESTBRIDGE is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_MACINTOSH_DRIVERS is not set +# CONFIG_MACVLAN is not set +# CONFIG_MACVTAP is not set +# CONFIG_MAC_EMUMOUSEBTN is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MAG3110 is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +# CONFIG_MAILBOX is not set +# CONFIG_MANGLE_BOOTARGS is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MCB is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_MCPM is not set +# CONFIG_MD is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_ATTACH is not set +# CONFIG_MEDIA_CAMERA_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_PARPORT_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_MEMORY is not set +# CONFIG_MEMORY_FAILURE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_CS5535 is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_OMAP_USB_HOST is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MG_DISK is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MIGRATION is not set +CONFIG_MII=y +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MIPS_FPU_EMULATOR is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_O32_FP64_SUPPORT is not set +# CONFIG_MIPS_PARAVIRT is not set +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_MIPS_SIM is not set +CONFIG_MISC_DEVICES=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_MISDN is not set +# CONFIG_MISDN_AVMFRITZ is not set +# CONFIG_MISDN_HFCPCI is not set +# CONFIG_MISDN_HFCUSB is not set +# CONFIG_MISDN_INFINEON is not set +# CONFIG_MISDN_NETJET is not set +# CONFIG_MISDN_SPEEDFAX is not set +# CONFIG_MISDN_W6692 is not set +# CONFIG_MKISS is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMC is not set +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_AU1X is not set +# CONFIG_MMC_BLOCK is not set +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_MVSDIO is not set +# CONFIG_MMC_S3C is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_ACPI is not set +# CONFIG_MMC_SDHCI_BCM_KONA is not set +# CONFIG_MMC_SDHCI_MSM is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ESDHC is not set +# CONFIG_MMC_SDHCI_OF_HLWD is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDRICOH_CS is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMIOTRACE is not set +CONFIG_MMU=y +CONFIG_MODULES=y +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULE_STRIPPED=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_INPORT is not set +# CONFIG_MOUSE_LOGIBM is not set +# CONFIG_MOUSE_PC110PAD is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_MPL115 is not set +# CONFIG_MPL3115 is not set +# CONFIG_MSDOS_FS is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_MSI_LAPTOP is not set +CONFIG_MTD=y +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_BLOCK2MTD is not set +CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_CHAR=y +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LATCH_ADDR is not set +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +# CONFIG_MTD_M25P80 is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_MYLOADER_PARTS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_NAND_AMS_DELTA is not set +# CONFIG_MTD_NAND_AR934X is not set +# CONFIG_MTD_NAND_AR934X_HW_ECC is not set +# CONFIG_MTD_NAND_ATMEL is not set +# CONFIG_MTD_NAND_AU1550 is not set +# CONFIG_MTD_NAND_AUTCPU12 is not set +# CONFIG_MTD_NAND_BCH is not set +# CONFIG_MTD_NAND_BCM_UMI is not set +# CONFIG_MTD_NAND_BF5XX is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_CM_X270 is not set +# CONFIG_MTD_NAND_CS553X is not set +# CONFIG_MTD_NAND_DAVINCI is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018 +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_ECC is not set +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_NAND_FSL_IFC is not set +# CONFIG_MTD_NAND_FSL_UPM is not set +# CONFIG_MTD_NAND_FSMC is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_GPMI_NAND is not set +# CONFIG_MTD_NAND_H1900 is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_JZ4740 is not set +# CONFIG_MTD_NAND_MPC5121_NFC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_MXC is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_NOMADIK is not set +# CONFIG_MTD_NAND_NUC900 is not set +# CONFIG_MTD_NAND_OMAP2 is not set +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set +# CONFIG_MTD_NAND_ORION is not set +# CONFIG_MTD_NAND_PASEMI is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_NAND_PPCHAMELEONEVB is not set +# CONFIG_MTD_NAND_PXA3xx is not set +# CONFIG_MTD_NAND_RB4XX is not set +# CONFIG_MTD_NAND_RB750 is not set +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_RTC_FROM4 is not set +# CONFIG_MTD_NAND_S3C2410 is not set +# CONFIG_MTD_NAND_SHARPSL is not set +# CONFIG_MTD_NAND_SH_FLCTL is not set +# CONFIG_MTD_NAND_SOCRATES is not set +# CONFIG_MTD_NAND_SPIA is not set +# CONFIG_MTD_NAND_TMIO is not set +# CONFIG_MTD_NAND_TXX9NDFMC is not set +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_PCMCIA is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_ROM is not set +CONFIG_MTD_ROOTFS_ROOT_DEV=y +CONFIG_MTD_ROOTFS_SPLIT=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SPI_NOR is not set +# CONFIG_MTD_SPINAND_MT29F is not set +CONFIG_MTD_SPLIT=y +# CONFIG_MTD_SPLIT_FIRMWARE is not set +CONFIG_MTD_SPLIT_FIRMWARE_NAME="firmware" +# CONFIG_MTD_SPLIT_FIT_FW is not set +# CONFIG_MTD_SPLIT_LZMA_FW is not set +# CONFIG_MTD_SPLIT_SEAMA_FW is not set +CONFIG_MTD_SPLIT_SQUASHFS_ROOT=y +CONFIG_MTD_SPLIT_SUPPORT=y +# CONFIG_MTD_SPLIT_TRX_FW is not set +# CONFIG_MTD_SPLIT_TPLINK_FW is not set +# CONFIG_MTD_SPLIT_UIMAGE_FW is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_UBI is not set +# CONFIG_MTD_UIMAGE_SPLIT is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_MVMDIO is not set +# CONFIG_MVSW61XX_PHY is not set +# CONFIG_MVSW6171_PHY is not set +# CONFIG_MVSWITCH_PHY is not set +# CONFIG_MWAVE is not set +# CONFIG_MWIFIEX is not set +# CONFIG_MWL8K is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NATSEMI is not set +# CONFIG_NAU7802 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_NCP_FS is not set +# CONFIG_NE2000 is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NEC_MARKEINS is not set +CONFIG_NET=y +# CONFIG_NETCONSOLE is not set +CONFIG_NETDEVICES=y +CONFIG_NETDEV_1000=y +# CONFIG_NETDEV_10000 is not set +# CONFIG_NETFILTER is not set +# CONFIG_NETFILTER_ADVANCED is not set +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_QUEUE_CT is not set +# CONFIG_NETFILTER_TPROXY is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LAYER7 is not set +# CONFIG_NETFILTER_XT_MATCH_LAYER7_DEBUG is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NETROM is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NET_9P is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +CONFIG_NET_CADENCE=y +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_ACT is not set +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_IND=y +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_U32 is not set +CONFIG_NET_CORE=y +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_NET_DSA is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6171 is not set +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_NBYTE is not set +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_TEXT is not set +# CONFIG_NET_EMATCH_U32 is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_FC is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_IPGRE is not set +CONFIG_NET_IPGRE_BROADCAST=y +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_IP_TUNNEL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_KEY is not set +# CONFIG_NET_KEY_MIGRATE is not set +# CONFIG_NET_MPLS_GSO is not set +# CONFIG_NET_PACKET_ENGINE is not set +CONFIG_NET_PCI=y +# CONFIG_NET_PCMCIA is not set +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_POCKET is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_NET_PTP_CLASSIFY is not set +CONFIG_NET_RX_BUSY_POLL=y +# CONFIG_NET_SB1000 is not set +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_ATM is not set +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_ESFQ is not set +CONFIG_NET_SCH_ESFQ_NFCT=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_NET_SCH_FQ is not set +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCTPPROBE is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_TEAM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_NET_UDP_TUNNEL is not set +CONFIG_NET_VENDOR_3COM=y +CONFIG_NET_VENDOR_8390=y +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_NET_VENDOR_AGERE=y +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CIRRUS=y +CONFIG_NET_VENDOR_CISCO=y +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_VENDOR_DLINK=y +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_NET_VENDOR_EXAR=y +CONFIG_NET_VENDOR_FARADAY=y +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HP=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_IBM=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_MICREL=y +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_NET_VENDOR_OKI=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_NET_VENDOR_RDC=y +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_NET_VENDOR_SILICOM=y +CONFIG_NET_VENDOR_SIS=y +CONFIG_NET_VENDOR_SMSC=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_NET_VENDOR_SUN=y +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_NET_VENDOR_TI=y +CONFIG_NET_VENDOR_TOSHIBA=y +CONFIG_NET_VENDOR_VIA=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +CONFIG_NET_VENDOR_XIRCOM=y +# CONFIG_NET_XGENE is not set +CONFIG_NEW_LEDS=y +# CONFIG_NFC is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_DEPRECATED is not set +# CONFIG_NFSD_V2_ACL is not set +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +# CONFIG_NFS_ACL_SUPPORT is not set +CONFIG_NFS_COMMON=y +# CONFIG_NFS_FS is not set +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_V4_1 is not set +# CONFIG_NFTL is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IPV4 is not set +# CONFIG_NF_CONNTRACK_IPV6 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set +# CONFIG_NF_CONNTRACK_RTSP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_GRE is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +# CONFIG_NF_NAT is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_FTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_IPV6 is not set +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set +# CONFIG_NF_NAT_MASQUERADE_IPV6 is not set +# CONFIG_NF_NAT_NEEDED is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_PROTO_GRE is not set +# CONFIG_NF_NAT_RTSP is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_REJECT_IPV4 is not set +# CONFIG_NF_TABLES is not set +# CONFIG_NI52 is not set +# CONFIG_NI65 is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NIU is not set +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLATTR=y +# CONFIG_NLMON is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLS is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NORTEL_HERMES is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_NOZOMI is not set +# CONFIG_NO_BOOTMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_NS83820 is not set +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_NTP_PPS is not set +# CONFIG_NVRAM is not set +# CONFIG_NV_TCO is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_N_GSM is not set +# CONFIG_OABI_COMPAT is not set +# CONFIG_OBS600 is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_OCF_BENCH is not set +# CONFIG_OCF_C7108 is not set +# CONFIG_OCF_CRYPTOCTEON is not set +# CONFIG_OCF_EP80579 is not set +# CONFIG_OCF_HIFN is not set +# CONFIG_OCF_HIFNHIPP is not set +# CONFIG_OCF_IXP4XX is not set +# CONFIG_OCF_KIRKWOOD is not set +# CONFIG_OCF_OCF is not set +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_SAFE is not set +# CONFIG_OCF_TALITOS is not set +# CONFIG_OCF_UBSEC_SSB is not set +# CONFIG_OC_ETM is not set +# CONFIG_OF_SELFTEST is not set +# CONFIG_OMAP2_DSS_DEBUG is not set +# CONFIG_OMAP2_DSS_DEBUGFS is not set +# CONFIG_OMAP2_DSS_SDI is not set +# CONFIG_OMAP_CONTROL_USB is not set +# CONFIG_OMAP_OCP2SCP is not set +# CONFIG_OMAP_USB2 is not set +# CONFIG_OMAP_USB3 is not set +# CONFIG_OMFS_FS is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_OPROFILE is not set +# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set +# CONFIG_ORION_WATCHDOG is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_OVERLAY_FS=y +# CONFIG_P54_COMMON is not set +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PANEL is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PANTHERLORD_FF is not set +# CONFIG_PARPORT is not set +# CONFIG_PARPORT_1284 is not set +# CONFIG_PARPORT_AX88796 is not set +# CONFIG_PARPORT_PC is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARASAN_CF is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CS5535 is not set +# CONFIG_PATA_CS5536 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_ISAPNP is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OCTEON_CF is not set +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PCMCIA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_QDI is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_WINBOND_VLB is not set +# CONFIG_PC300TOO is not set +# CONFIG_PCCARD is not set +# CONFIG_PCH_GBE is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_PCI200SYN is not set +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIEASPM is not set +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_PCI_ATMEL is not set +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set +# CONFIG_PCI_HERMES is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_PCI_PRI is not set +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +CONFIG_PCI_SYSCALL=y +# CONFIG_PCMCIA is not set +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_3C589 is not set +# CONFIG_PCMCIA_AHA152X is not set +# CONFIG_PCMCIA_ATMEL is not set +# CONFIG_PCMCIA_AXNET is not set +# CONFIG_PCMCIA_DEBUG is not set +# CONFIG_PCMCIA_FDOMAIN is not set +# CONFIG_PCMCIA_FMVJ18X is not set +# CONFIG_PCMCIA_HERMES is not set +# CONFIG_PCMCIA_LOAD_CIS is not set +# CONFIG_PCMCIA_NINJA_SCSI is not set +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_PCNET is not set +# CONFIG_PCMCIA_QLOGIC is not set +# CONFIG_PCMCIA_RAYCS is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_SPECTRUM is not set +# CONFIG_PCMCIA_SYM53C500 is not set +# CONFIG_PCMCIA_WL3501 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_XIRCOM is not set +# CONFIG_PCNET32 is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_PD6729 is not set +# CONFIG_PDA_POWER is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_PHANTOM is not set +# CONFIG_PHONE is not set +# CONFIG_PHONET is not set +# CONFIG_PHYLIB is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_PHY_EXYNOS_DP_VIDEO is not set +# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set +# CONFIG_PHY_QCOM_DWC3 is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_PID_NS is not set +CONFIG_PINCONF=y +# CONFIG_PINCTRL is not set +# CONFIG_PINCTRL_CAPRI is not set +# CONFIG_PINCTRL_EXYNOS is not set +# CONFIG_PINCTRL_EXYNOS5440 is not set +# CONFIG_PINCTRL_MSM8X74 is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINMUX=y +# CONFIG_PLAT_SPEAR is not set +# CONFIG_PLIP is not set +# CONFIG_PLX_HERMES is not set +# CONFIG_PM is not set +# CONFIG_PMBUS is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_PM_RUNTIME is not set +# CONFIG_PM_WAKELOCKS is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_POHMELFS is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_POWERCAP is not set +# CONFIG_POWERTV is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_VERSATILE is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_DISABLE_WERROR is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_PPC_EPAPR_HV_BYTECHAN is not set +# CONFIG_PPP is not set +# CONFIG_PPPOATM is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +CONFIG_PPP_FILTER=y +# CONFIG_PPP_MPPE is not set +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPS is not set +# CONFIG_PPS_CLIENT_GPIO is not set +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_DEBUG is not set +# CONFIG_PPTP is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_PRINTK=y +# CONFIG_PRINTK_TIME is not set +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_PRISM2_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_PROBE_INITRD_HEADER is not set +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_PROC_STRIPPED=y +CONFIG_PROC_SYSCTL=y +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILING is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_PROVE_RCU is not set +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_PSB6970_PHY is not set +# CONFIG_PSTORE is not set +# CONFIG_PTP_1588_CLOCK is not set +# CONFIG_PTP_1588_CLOCK_IXP46X is not set +# CONFIG_PTP_1588_CLOCK_PCH is not set +# CONFIG_PWM is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_QCA7000 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_R3964 is not set +# CONFIG_R6040 is not set +# CONFIG_R8169 is not set +# CONFIG_R8187SE is not set +# CONFIG_R8188EU is not set +# CONFIG_R8712U is not set +# CONFIG_R8723AU is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_RADIO_AZTECH is not set +# CONFIG_RADIO_CADET is not set +# CONFIG_RADIO_GEMTEK is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_RTRACK is not set +# CONFIG_RADIO_RTRACK2 is not set +# CONFIG_RADIO_SF16FMI is not set +# CONFIG_RADIO_SF16FMR2 is not set +# CONFIG_RADIO_TERRATEC is not set +# CONFIG_RADIO_TRUST is not set +# CONFIG_RADIO_TYPHOON is not set +# CONFIG_RADIO_ZOLTRIX is not set +# CONFIG_RAID_ATTRS is not set +# CONFIG_RALINK is not set +# CONFIG_RAMOOPS is not set +# CONFIG_RANDOM32_SELFTEST is not set +# CONFIG_RAPIDIO is not set +# CONFIG_RAR_REGISTER is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_RCU_NOCB_CPU is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_USER_QS is not set +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_RC_CORE is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_LOOPBACK is not set +# CONFIG_RC_MAP is not set +# CONFIG_RDS is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_XZ is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_REDWOOD is not set +# CONFIG_REGMAP is not set +# CONFIG_REGMAP_I2C is not set +# CONFIG_REGMAP_MMIO is not set +# CONFIG_REGMAP_SPI is not set +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ANATOP is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_TI_ABB is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_FS_POSIX_ACL is not set +# CONFIG_REISERFS_FS_SECURITY is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_RELAY is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_RFD_FTL is not set +# CONFIG_RFKILL is not set +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_ROSE is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RT2X00 is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_RTC_DEBUG is not set +# CONFIG_RTC_DRV_AU1XXX is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_BQ4802 is not set +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_EP93XX is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_GENERIC is not set +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12057 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_MOXART is not set +# CONFIG_RTC_DRV_MPC5121 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_OMAP is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_PS3 is not set +# CONFIG_RTC_DRV_PT7C4338 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_RTC7301 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_SUN6I is not set +# CONFIG_RTC_DRV_TEST is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_XGENE is not set +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_SYSTOHC=y +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_RTL8192E is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTL8306_PHY is not set +# CONFIG_RTL8366RB_PHY is not set +# CONFIG_RTL8366S_PHY is not set +# CONFIG_RTL8366_SMI is not set +# CONFIG_RTL8366_SMI_DEBUG_FS is not set +# CONFIG_RTL8367B_PHY is not set +# CONFIG_RTL8367_PHY is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_RTS5139 is not set +# CONFIG_RTS5208 is not set +# CONFIG_RTS_PSTOR is not set +CONFIG_RT_MUTEXES=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_RUNTIME_DEBUG is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_S2IO is not set +# CONFIG_SAMPLES is not set +# CONFIG_SAMSUNG_LAPTOP is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_FSL is not set +# CONFIG_SATA_HIGHBANK is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_SATA_PMP is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_RCAR is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SBC_FITPC2_WATCHDOG is not set +# CONFIG_SBE_2T3E3 is not set +# CONFIG_SBYPASS is not set +# CONFIG_SC92031 is not set +# CONFIG_SCA3000 is not set +# CONFIG_SCC is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHED_MC is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y +# CONFIG_SCHED_SMT is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_7000FASST is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_AHA152X is not set +# CONFIG_SCSI_AHA1542 is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_DTC3280 is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_GENERIC_NCR5380 is not set +# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_IN2000 is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_ISCI is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_LPFC is not set +CONFIG_SCSI_MOD=y +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVSAS_DEBUG is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_NCR53C406A is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_SCSI_PAS16 is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PROC_FS=y +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLOGIC_FAS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_T128 is not set +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_ULTRASTOR is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCx200_ACB is not set +# CONFIG_SDIO_UART is not set +# CONFIG_SECCOMP is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SEEQ8005 is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_ACPI_POWER is not set +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATK0110 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_GSC is not set +# CONFIG_SENSORS_HDAPS is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HMC5843 is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_K10TEMP is not set +# CONFIG_SENSORS_K8TEMP is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VIA_CPUTEMP is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_ACCENT is not set +# CONFIG_SERIAL_8250_BOCA is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DMA=y +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_EM is not set +# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_FOURPORT is not set +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_8250_HUB6 is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_NR_UARTS=2 +# CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_SYSRQ is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_ARC is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_SERIAL_OF_PLATFORM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SH_SCI is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIO is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SFC is not set +# CONFIG_SFI is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_SHMEM=y +# CONFIG_SH_ETH is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_SI7005 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIGMA is not set +CONFIG_SIGNALFD=y +# CONFIG_SIMPLE_GPIO is not set +# CONFIG_SIS190 is not set +# CONFIG_SIS900 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SKY2_DEBUG is not set +CONFIG_SLAB=y +CONFIG_SLABINFO=y +# CONFIG_SLHC is not set +# CONFIG_SLICOSS is not set +# CONFIG_SLIP is not set +# CONFIG_SLOB is not set +# CONFIG_SLUB is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SMARTJOYPLUS_FF is not set +# CONFIG_SMC911X is not set +# CONFIG_SMC9194 is not set +# CONFIG_SMC91X is not set +# CONFIG_SMP is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_SM_FTL is not set +# CONFIG_SND is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +# CONFIG_SND_AD1816A is not set +# CONFIG_SND_AD1848 is not set +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ADLIB is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_ALS100 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALS4000 is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_ASIHPI is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_ATMEL_AC97C is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT2320 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMI8330 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4231 is not set +# CONFIG_SND_CS4236 is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5530 is not set +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1688 is not set +# CONFIG_SND_ES18XX is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FIREWIRE is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_GUSCLASSIC is not set +# CONFIG_SND_GUSEXTREME is not set +# CONFIG_SND_GUSMAX is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_HWDEP is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_INTERWAVE is not set +# CONFIG_SND_INTERWAVE_STB is not set +# CONFIG_SND_ISA is not set +# CONFIG_SND_KIRKWOOD_SOC is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_MIRO is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MPC52xx_SOC_EFIKA is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_MTS64 is not set +# CONFIG_SND_MXS_SOC is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_OPL3SA2 is not set +# CONFIG_SND_OPTI92X_AD1848 is not set +# CONFIG_SND_OPTI92X_CS4231 is not set +# CONFIG_SND_OPTI93X is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_OXYGEN is not set +CONFIG_SND_PCI=y +# CONFIG_SND_PCM is not set +# CONFIG_SND_PCMCIA is not set +# CONFIG_SND_PCM_OSS is not set +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_PDAUDIOCF is not set +# CONFIG_SND_PORTMAN2X4 is not set +# CONFIG_SND_POWERPC_SOC is not set +# CONFIG_SND_PPC is not set +# CONFIG_SND_RAWMIDI is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_RTCTIMER is not set +# CONFIG_SND_SB16 is not set +# CONFIG_SND_SB8 is not set +# CONFIG_SND_SBAWE is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SND_SIS7019 is not set +# CONFIG_SND_SOC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AU1XAUDIO is not set +# CONFIG_SND_SOC_AU1XPSC is not set +# CONFIG_SND_SOC_CACHE_LZO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271 is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_ES8328 is not set +# CONFIG_SND_SOC_EUKREA_TLV320 is not set +# CONFIG_SND_SOC_FSL_ASOC_CARD is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_HDMI_CODEC is not set +# CONFIG_SND_SOC_IMX_ES8328 is not set +# CONFIG_SND_SOC_IMX_SPDIF is not set +# CONFIG_SND_SOC_IMX_WM8962 is not set +# CONFIG_SND_SOC_INTEL_SST is not set +# CONFIG_SND_SOC_MPC5200_AC97 is not set +# CONFIG_SND_SOC_MPC5200_I2S is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1792A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8804 is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_SSCAPE is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_TIMER is not set +# CONFIG_SND_TRIDENT is not set +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_US122L is not set +# CONFIG_SND_USB_USX2Y is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_WAVEFRONT is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SNI_RM is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_SOC_DRA7XX is not set +# CONFIG_SOC_HAS_OMAP2_SDRC is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_TI is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_SOLO6X10 is not set +# CONFIG_SONYPI is not set +# CONFIG_SONY_LAPTOP is not set +# CONFIG_SOUND is not set +# CONFIG_SOUND_PRIME is not set +# CONFIG_SP5100_TCO is not set +# CONFIG_SPARSEMEM_MANUAL is not set +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +# CONFIG_SPARSE_IRQ is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_SPEAKUP is not set +# CONFIG_SPI is not set +# CONFIG_SPINLOCK_TEST is not set +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AU1550 is not set +# CONFIG_SPI_BCM2835 is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_BUTTERFLY is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_FSL_ESPI is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_GPIO_OLD is not set +# CONFIG_SPI_LM70_LLP is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_SPI_MPC52xx is not set +# CONFIG_SPI_MPC52xx_PSC is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_OCTEON is not set +# CONFIG_SPI_ORION is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PPC4xx is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_RAMIPS is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TI_QSPI is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_XWAY is not set +# CONFIG_SPMI is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XATTR is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SRAM is not set +# CONFIG_SSB is not set +# CONFIG_SSBI is not set +# CONFIG_SSB_DEBUG is not set +# CONFIG_SSB_DRIVER_GPIO is not set +# CONFIG_SSB_PCMCIAHOST is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSFDC is not set +CONFIG_STACKTRACE_SUPPORT=y +# CONFIG_STACKTRACE is not set +# CONFIG_STACK_TRACER is not set +CONFIG_STAGING=y +# CONFIG_STAGING_MEDIA is not set +CONFIG_STANDALONE=y +CONFIG_STDBINUTILS=y +# CONFIG_STE10XP is not set +# CONFIG_STE_MODEM_RPROC is not set +# CONFIG_STMMAC_ETH is not set +# CONFIG_STMMAC_PLATFORM is not set +# CONFIG_STMMAC_PCI is not set +CONFIG_STP=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_STUB_POULSBO is not set +# CONFIG_SUNDANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_SUNRPC is not set +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SUSPEND is not set +CONFIG_SWAP=y +# CONFIG_SWCONFIG is not set +# CONFIG_SWCONFIG_LEDS is not set +# CONFIG_SXGBE_ETH is not set +# CONFIG_SYNCLINK_CS is not set +CONFIG_SYN_COOKIES=y +CONFIG_SYSCTL=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_SYSFS=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_SYSV_FS is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_T5403 is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_TASKS_RCU is not set +# CONFIG_TC35815 is not set +# CONFIG_TCG_TPM is not set +# CONFIG_TCIC is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_MD5SIG is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_TEHUTI is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_MODULE is not set +# CONFIG_TEST_POWER is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_USER_COPY is not set +CONFIG_TEXTSEARCH=y +# CONFIG_TEXTSEARCH_BM is not set +# CONFIG_TEXTSEARCH_FSM is not set +# CONFIG_TEXTSEARCH_KMP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_THUNDERBOLT is not set +# CONFIG_TICK_CPU_ACCOUNTING is not set +CONFIG_TICK_ONESHOT=y +# CONFIG_TIFM_CORE is not set +# CONFIG_TIGON3 is not set +# CONFIG_TIMB_DMA is not set +CONFIG_TIMERFD=y +# CONFIG_TIMER_STATS is not set +CONFIG_TINY_RCU=y +# CONFIG_TIPC is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_AM335X_ADC is not set +# CONFIG_TI_CPSW is not set +# CONFIG_TI_CPTS is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_TI_DAVINCI_CPDMA is not set +# CONFIG_TI_DAVINCI_MDIO is not set +# CONFIG_TI_ST is not set +# CONFIG_TLAN is not set +# CONFIG_TWL4030_MADC is not set +# CONFIG_TMD_HERMES is not set +# CONFIG_TMP006 is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +CONFIG_TMPFS_XATTR=y +# CONFIG_TORTURE_TEST is not set +# CONFIG_TOSHIBA_HAPS is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_S3C2410 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TR is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_TRACER_SNAPSHOT is not set +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_TRACE_SINK is not set +CONFIG_TRACING_SUPPORT=y +CONFIG_TRAD_SIGNALS=y +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_TRANZPORT is not set +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TREE_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set +# CONFIG_TSL4531 is not set +CONFIG_TTY=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_TUN is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6030_GPADC is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_TYPHOON is not set +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_UDF_FS is not set +CONFIG_UDF_NLS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_UFS_FS is not set +# CONFIG_UHID is not set +CONFIG_UIDGID_STRICT_TYPE_CHECKS=y +# CONFIG_UIO is not set +# CONFIG_ULTRA is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_UNIX_DIAG is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_UPROBE_EVENT is not set +# CONFIG_UPROBES is not set +# CONFIG_USB is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_ADUTUX is not set +CONFIG_USB_ALI_M5632=y +# CONFIG_USB_AMD5536UDC is not set +CONFIG_USB_AN2720=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_ATM is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_BTMTK is not set +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_CONFIGFS is not set +# CONFIG_USB_CXACRU is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_DEBUG is not set +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_DWC2_DUAL_ROLE is not set +# CONFIG_USB_DWC2_HOST is not set +# CONFIG_USB_DWC2_PERIPHERAL is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC3_EXYNOS is not set +# CONFIG_USB_DWC3_QCOM is not set +# CONFIG_USB_DWC3_PCI is not set +# CONFIG_USB_DWC3_KEYSTONE is not set +# CONFIG_USB_DWC_OTG_LPM is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_EHCI_HCD_AT91 is not set +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_EHCI_MSM is not set +# CONFIG_USB_EHCI_MV is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_ET61X251 is not set +CONFIG_USB_EZUSB=y +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_FSL_USB2 is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_VBUS_DRAW=2 +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STK1135 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_HID is not set +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_INPUT_IMS_PCU is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_KBD is not set +# CONFIG_USB_KC2190 is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LIBUSUAL is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_M5602 is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_MSM_OTG is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_NET_AX88179_178A is not set +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_CDC_NCM is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_OHCI_HCD_PCI is not set +# CONFIG_USB_OHCI_HCD_PPC_OF is not set +# CONFIG_USB_OHCI_HCD_PPC_OF_BE is not set +# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set +# CONFIG_USB_OHCI_HCD_PPC_SOC is not set +# CONFIG_USB_OHCI_HCD_SSB is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_FSM is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_PHY is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_PWC_INPUT_EVDEV is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RCAR_PHY is not set +# CONFIG_USB_RENESAS_USBHS is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_S2255 is not set +# CONFIG_USB_S3C_HSOTG is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_DEBUG is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_GARMIN is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +CONFIG_USB_SERIAL_KEYSPAN_MPR=y +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +CONFIG_USB_SERIAL_KEYSPAN_USA18X=y +CONFIG_USB_SERIAL_KEYSPAN_USA19=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y +CONFIG_USB_SERIAL_KEYSPAN_USA19W=y +CONFIG_USB_SERIAL_KEYSPAN_USA28=y +CONFIG_USB_SERIAL_KEYSPAN_USA28X=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +CONFIG_USB_SERIAL_KEYSPAN_USA49W=y +CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_SERIAL_QUATECH_USB2 is not set +# CONFIG_USB_SERIAL_SAFE is not set +CONFIG_USB_SERIAL_SAFE_PADDED=y +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_ZTE is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_SPEEDTOUCH is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_TMC is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_UEAGLEATM is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_USS720 is not set +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +# CONFIG_USB_VL600 is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_XUSBATM is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USELIB is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_USE_OF is not set +# CONFIG_UTS_NS is not set +# CONFIG_UWB is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VETH is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_VF610_ADC is not set +# CONFIG_VFAT_FS is not set +# CONFIG_VGASTATE is not set +# CONFIG_VGA_ARB is not set +# CONFIG_VGA_SWITCHEROO is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT848 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_BWQCAM is not set +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_CAPTURE_DRIVERS is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CQCAM is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_CX2341X is not set +# CONFIG_VIDEO_CX25840 is not set +# CONFIG_VIDEO_CX88 is not set +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_DM6446_CCDC is not set +# CONFIG_VIDEO_DT3155 is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +# CONFIG_VIDEO_HEXIUM_GEMINI is not set +# CONFIG_VIDEO_HEXIUM_ORION is not set +# CONFIG_VIDEO_IR_I2C is not set +# CONFIG_VIDEO_IVTV is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_MEDIA is not set +# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MXB is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_OMAP2_VOUT is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_SAA6588 is not set +# CONFIG_VIDEO_SAA6752HS is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7134 is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TM6000 is not set +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_USBTV is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_VIDEO_V4L2 is not set +# CONFIG_VIDEO_V4L2_COMMON is not set +# CONFIG_VIDEO_V4L2_INT_DEVICE is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTUALIZATION is not set +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRT_TO_BUS=y +# CONFIG_VITESSE_PHY is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_VME_BUS is not set +# CONFIG_VMSPLIT_1G is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_2G_OPT is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMWARE_PVSCSI is not set +# CONFIG_VMXNET3 is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_VORTEX is not set +# CONFIG_VSOCKETS is not set +# CONFIG_VT is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_VXFS_FS is not set +# CONFIG_VXGE is not set +# CONFIG_VXLAN is not set +# CONFIG_W1 is not set +# CONFIG_W1_CON is not set +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_GPIO is not set +# CONFIG_W1_MASTER_MATROX is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +# CONFIG_W1_SLAVE_DS2406 is not set +# CONFIG_W1_SLAVE_DS2408 is not set +# CONFIG_W1_SLAVE_DS2413 is not set +# CONFIG_W1_SLAVE_DS2423 is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_DS2780 is not set +# CONFIG_W1_SLAVE_DS2781 is not set +# CONFIG_W1_SLAVE_DS28E04 is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W35UND is not set +# CONFIG_W83627HF_WDT is not set +# CONFIG_W83697HF_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_W83977F_WDT is not set +# CONFIG_WAN is not set +# CONFIG_WANXL is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WD80x3 is not set +# CONFIG_WDTPCI is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PRIV=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WILINK_PLATFORM_DATA=y +# CONFIG_WIMAX is not set +# CONFIG_WIMAX_GDM72XX is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +# CONFIG_WIRELESS_EXT_SYSFS is not set +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLAGS49_H2 is not set +# CONFIG_WLAGS49_H25 is not set +CONFIG_WLAN=y +# CONFIG_WLCORE is not set +CONFIG_WL_TI=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_WR_PPMC is not set +# CONFIG_X25 is not set +# CONFIG_X86_DEBUG_STATIC_CPU_HAS is not set +# CONFIG_X86_PKG_TEMP_THERMAL is not set +CONFIG_X86_SYSFB=y +# CONFIG_XEN is not set +CONFIG_XFRM=y +# CONFIG_XFRM_IPCOMP is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_USER is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_XFS_FS is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_EMACLITE is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_XMON is not set +# CONFIG_XVMALLOC is not set +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_BCJ is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_TEST is not set +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_YAM is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_YENTA is not set +# CONFIG_YENTA_O2 is not set +# CONFIG_YENTA_RICOH is not set +# CONFIG_YENTA_TI is not set +# CONFIG_YENTA_TOSHIBA is not set +# CONFIG_ZBUD is not set +# CONFIG_ZD1211RW is not set +# CONFIG_ZD1211RW_DEBUG is not set +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_ZISOFS is not set +# CONFIG_ZLIB_DEFLATE is not set +# CONFIG_ZLIB_INFLATE is not set +# CONFIG_ZNET is not set +# CONFIG_ZPOOL is not set +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_ZRAM is not set +# CONFIG_ZRAM_LZ4_COMPRESS is not set +# CONFIG_ZSMALLOC is not set diff --git a/target/linux/generic/config-4.0 b/target/linux/generic/config-4.0 new file mode 100644 index 0000000..4d42fae --- /dev/null +++ b/target/linux/generic/config-4.0 @@ -0,0 +1,4731 @@ +CONFIG_32BIT=y +# CONFIG_6LOWPAN is not set +# CONFIG_6PACK is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_9P_FS is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_AB8500_CORE is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_ACENIC is not set +# CONFIG_ACERHDF is not set +# CONFIG_ACORN_PARTITION is not set +# CONFIG_ACPI_APEI is not set +# CONFIG_ACPI_CUSTOM_METHOD is not set +# CONFIG_ACPI_EXTLOG is not set +# CONFIG_ACPI_HED is not set +# CONFIG_ACPI_INT3403_THERMAL is not set +# CONFIG_ACPI_POWER_METER is not set +# CONFIG_ACPI_QUICKSTART is not set +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +# CONFIG_AD5064 is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686 is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5930 is not set +# CONFIG_AD5933 is not set +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD7746 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD799X is not set +# CONFIG_AD8366 is not set +# CONFIG_AD9523 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16255 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_ADM6996_PHY is not set +# CONFIG_ADM8211 is not set +# CONFIG_ADT7316 is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_ADXRS450 is not set +CONFIG_AEABI=y +# CONFIG_AFFS_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AGP is not set +# CONFIG_AHCI_MVEBU is not set +CONFIG_AIO=y +# CONFIG_AIRO is not set +# CONFIG_AIRO_CS is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_AK09911 is not set +# CONFIG_AK8975 is not set +# CONFIG_AL3320A is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_ALIM7101_WDT is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_ALTERA_STAPL is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_ALX is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_AMD_XGBE is not set +# CONFIG_AMD_XGBE_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_AMILO_RFKILL is not set +# CONFIG_ANDROID is not set +CONFIG_ANON_INODES=y +# CONFIG_APDS9300 is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_APM8018X is not set +# CONFIG_APPLICOM is not set +# CONFIG_AR5523 is not set +# CONFIG_AR7 is not set +# CONFIG_AR8216_PHY is not set +# CONFIG_AR8216_PHY_LEDS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_EXYNOS is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +# CONFIG_ARCH_HI3xxx is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_MSM_DT is not set +# CONFIG_ARCH_MSM_NODT is not set +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_MULTI_V6 is not set +# CONFIG_ARCH_MULTI_V7 is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_NSPIRE is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2PLUS is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_SHMOBILE_LEGACY is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_WM8505 is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCNET is not set +# CONFIG_ARC_EMAC is not set +# CONFIG_ARM_APPENDED_DTB is not set +# CONFIG_ARM_ARCH_TIMER is not set +# CONFIG_ARM_AT91_ETHER is not set +# CONFIG_ARM_CCI is not set +# CONFIG_ARM_CCN is not set +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_ARM_ERRATA_326103 is not set +# CONFIG_ARM_ERRATA_364296 is not set +# CONFIG_ARM_ERRATA_411920 is not set +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_643719 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_KERNMEM_PERMS is not set +# CONFIG_ARM_KPROBES_TEST is not set +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +# CONFIG_ARM_PSCI is not set +# CONFIG_ARM_PTDUMP is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_ARM_VIRT_EXT is not set +CONFIG_ARPD=y +# CONFIG_ARTHUR is not set +# CONFIG_AS3935 is not set +# CONFIG_ASM9260_TIMER is not set +# CONFIG_ASUS_LAPTOP is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set +# CONFIG_ASYNC_RAID6_TEST is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_ATA is not set +# CONFIG_ATAGS is not set +CONFIG_ATAGS_PROC=y +# CONFIG_ATALK is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_ATA_ACPI is not set +CONFIG_ATA_BMDMA=y +# CONFIG_ATA_GENERIC is not set +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_ATA_PIIX is not set +CONFIG_ATA_SFF=y +# CONFIG_ATA_VERBOSE_ERROR is not set +# CONFIG_ATH10K is not set +# CONFIG_ATH25 is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH6KL is not set +# CONFIG_ATH6K_LEGACY is not set +# CONFIG_ATH79 is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1C is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL2 is not set +# CONFIG_ATM is not set +# CONFIG_ATMEL is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ATM_AMBASSADOR is not set +# CONFIG_ATM_BR2684 is not set +CONFIG_ATM_BR2684_IPFILTER=y +# CONFIG_ATM_CLIP is not set +CONFIG_ATM_CLIP_NO_ICMP=y +# CONFIG_ATM_DRIVERS is not set +# CONFIG_ATM_DUMMY is not set +# CONFIG_ATM_ENI is not set +# CONFIG_ATM_FIRESTREAM is not set +# CONFIG_ATM_FORE200E is not set +# CONFIG_ATM_HE is not set +# CONFIG_ATM_HORIZON is not set +# CONFIG_ATM_IA is not set +# CONFIG_ATM_IDT77252 is not set +# CONFIG_ATM_LANAI is not set +# CONFIG_ATM_LANE is not set +# CONFIG_ATM_MPOA is not set +# CONFIG_ATM_NICSTAR is not set +# CONFIG_ATM_SOLOS is not set +# CONFIG_ATM_TCP is not set +# CONFIG_ATM_ZATM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ATP is not set +# CONFIG_AUDIT is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTO_ZRELADDR is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_AVERAGE is not set +# CONFIG_AX25 is not set +# CONFIG_AX25_DAMA_SLAVE is not set +# CONFIG_AX88796 is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_B44 is not set +# CONFIG_B53 is not set +# CONFIG_B53_SPI_DRIVER is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_BACKLIGHT_LM3630 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_PANDORA is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +CONFIG_BASE_FULL=y +CONFIG_BASE_SMALL=0 +# CONFIG_BATMAN_ADV is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BAYCOM_EPP is not set +# CONFIG_BAYCOM_PAR is not set +# CONFIG_BAYCOM_SER_FDX is not set +# CONFIG_BAYCOM_SER_HDX is not set +# CONFIG_BCACHE is not set +# CONFIG_BCM3384 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_BCM63XX_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BCMA is not set +# CONFIG_BCMA_DRIVER_GPIO is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMGENET is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BE2NET is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_BGMAC is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_BIG_LITTLE is not set +# CONFIG_BINARY_PRINTF is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_CPQ_DA is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_ATIIXP is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_CS5535 is not set +# CONFIG_BLK_DEV_CS5536 is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_DELKIN is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_IDEACPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDECS is not set +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_BLK_DEV_IDEPNP is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDE_AU1XXX is not set +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RZ1000 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_SD is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SIS5513 is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SL82C105 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_BLK_DEV_THROTTLING is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_UMC8672 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLOCK=y +# CONFIG_BMA180 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_BMG160 is not set +# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_BMP280 is not set +# CONFIG_BNA is not set +# CONFIG_BNX2 is not set +# CONFIG_BNX2X is not set +# CONFIG_BONDING is not set +# CONFIG_BOOKE_WDT is not set +CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_BOOT_RAW=y +# CONFIG_BPCTL is not set +CONFIG_BPF=y +# CONFIG_BPF_JIT is not set +CONFIG_BPF_SYSCALL=y +# CONFIG_BPQETHER is not set +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_BRCMFMAC is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMSTB_GISB_ARB is not set +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_EBT_802_3 is not set +# CONFIG_BRIDGE_EBT_AMONG is not set +# CONFIG_BRIDGE_EBT_ARP is not set +# CONFIG_BRIDGE_EBT_ARPREPLY is not set +# CONFIG_BRIDGE_EBT_BROUTE is not set +# CONFIG_BRIDGE_EBT_DNAT is not set +# CONFIG_BRIDGE_EBT_IP is not set +# CONFIG_BRIDGE_EBT_IP6 is not set +# CONFIG_BRIDGE_EBT_LIMIT is not set +# CONFIG_BRIDGE_EBT_LOG is not set +# CONFIG_BRIDGE_EBT_MARK is not set +# CONFIG_BRIDGE_EBT_MARK_T is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_BRIDGE_EBT_PKTTYPE is not set +# CONFIG_BRIDGE_EBT_REDIRECT is not set +# CONFIG_BRIDGE_EBT_SNAT is not set +# CONFIG_BRIDGE_EBT_STP is not set +# CONFIG_BRIDGE_EBT_T_FILTER is not set +# CONFIG_BRIDGE_EBT_T_NAT is not set +# CONFIG_BRIDGE_EBT_ULOG is not set +# CONFIG_BRIDGE_EBT_VLAN is not set +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_NETFILTER is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BROADCOM_PHY is not set +CONFIG_BROKEN_ON_SMP=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_BT is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BT_ATH3K is not set +# CONFIG_BT_BNEP is not set +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +# CONFIG_BT_BREDR is not set +# CONFIG_BT_CMTP is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIBLUECARD is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBT3C is not set +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIBTUART is not set +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIDTL1 is not set +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIUART_3WIRE is not set +# CONFIG_BT_HCIUART_ATH3K is not set +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_HIDP is not set +CONFIG_BT_L2CAP=y +# CONFIG_BT_LE is not set +# CONFIG_BT_MRVL is not set +# CONFIG_BT_RFCOMM is not set +# CONFIG_BUILD_BIN2C is not set +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_SCO=y +# CONFIG_BT_SELFTEST is not set +CONFIG_BUG=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +# CONFIG_C2PORT is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_CAIF is not set +# CONFIG_CAN is not set +# CONFIG_CAN_GS_USB is not set +# CONFIG_CAN_M_CAN is not set +# CONFIG_CAN_RCAR is not set +# CONFIG_CAPI_AVM is not set +# CONFIG_CAPI_EICON is not set +# CONFIG_CAPI_TRACE is not set +CONFIG_CARDBUS=y +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_CARL9170 is not set +# CONFIG_CARMA_FPGA is not set +# CONFIG_CARMA_FPGA_PROGRAM is not set +# CONFIG_CASSINI is not set +CONFIG_CAVIUM_OCTEON_HELPER=y +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_SOC is not set +# CONFIG_CB710_CORE is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_CED1401 is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_CFG80211 is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CGROUPS is not set +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_CHARGER_TWL4030 is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CIFS is not set +# CONFIG_CIFS_ACL is not set +# CONFIG_CIFS_DEBUG is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_NFSD_EXPORT is not set +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB2 is not set +CONFIG_CIFS_STATS=y +# CONFIG_CIFS_STATS2 is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CLEANCACHE is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_CLKSRC_VERSATILE is not set +# CONFIG_CLOCK_THERMAL is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM36651 is not set +# CONFIG_CMA is not set +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_CMDLINE_FROM_BOOTLOADER is not set +# CONFIG_CMDLINE_PARTITION is not set +# CONFIG_CNIC is not set +# CONFIG_CODA_FS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_COMEDI is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_DEBUG is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_QCOM is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_COMPACTION is not set +# CONFIG_COMPAL_LAPTOP is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPILE_TEST is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_CONNECTOR is not set +CONFIG_CONSTRUCTORS=y +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_COPS is not set +# CONFIG_CORDIC is not set +# CONFIG_COREDUMP is not set +# CONFIG_CORESIGHT is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set +# CONFIG_CPU_IDLE_GOV_MENU is not set +# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set +# CONFIG_CRAMFS is not set +CONFIG_CRASHLOG=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_CRC32_BIT is not set +CONFIG_CRC32_SARWATE=y +# CONFIG_CRC32_SELFTEST is not set +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SLICEBY8 is not set +# CONFIG_CRC7 is not set +# CONFIG_CRC8 is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CROSS_COMPILE="" +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_AEAD is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_586 is not set +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_AES_ARM_BS is not set +# CONFIG_CRYPTO_AES_NI_INTEL is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32C_INTEL is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_DEV_ATMEL_AES is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set +# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM is not set +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO_DEV_MV_CESA is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QCE is not set +# CONFIG_CRYPTO_DEV_SAHARA is not set +# CONFIG_CRYPTO_DEV_TALITOS is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set +# CONFIG_CRYPTO_HASH is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_PCOMP is not set +# CONFIG_CRYPTO_PCOMP2 is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_RNG is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SALSA20_586 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_TWOFISH_586 is not set +# CONFIG_CRYPTO_TWOFISH_COMMON is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_XZ is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYSTALHD is not set +# CONFIG_CS5535_MFGPT is not set +# CONFIG_CS89x0 is not set +# CONFIG_CUSE is not set +# CONFIG_CW1200 is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXT1E1 is not set +# CONFIG_CYPRESS_FIRMWARE is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DCB is not set +# CONFIG_DDR is not set +# CONFIG_DE600 is not set +# CONFIG_DE620 is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +CONFIG_DEBUG_INFO_REDUCED=y +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +# CONFIG_DEBUG_LOCKDEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_NX_TEST is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set +# CONFIG_DEBUG_UART_BCM63XX is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_ZBOOT is not set +# CONFIG_DECNET is not set +CONFIG_DEFAULT_CUBIC=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_DEFAULT_NOOP is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_SECURITY="" +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +# CONFIG_DELL_SMO8800 is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_DEVKMEM is not set +# CONFIG_DEVMEM is not set +CONFIG_DEVPORT=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_DEVTMPFS is not set +# CONFIG_DEVTMPFS_MOUNT is not set +# CONFIG_DGAP is not set +# CONFIG_DGNC is not set +# CONFIG_DGRP is not set +# CONFIG_DHT11 is not set +# CONFIG_DIRECT_IO is not set +CONFIG_DISABLE_DEV_COREDUMP=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set +# CONFIG_DISPLAY_CONNECTOR_DVI is not set +# CONFIG_DISPLAY_CONNECTOR_HDMI is not set +# CONFIG_DISPLAY_ENCODER_TFP410 is not set +# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set +# CONFIG_DISPLAY_PANEL_DPI is not set +# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set +# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_DL2K is not set +# CONFIG_DLM is not set +# CONFIG_DM9000 is not set +# CONFIG_DMADEVICES is not set +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMASCC is not set +# CONFIG_DMATEST is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_ENGINE is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_LOG_USERSPACE is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DNET is not set +# CONFIG_DNOTIFY is not set +# CONFIG_DNS_RESOLVER is not set +CONFIG_DOUBLEFAULT=y +CONFIG_DQL=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_DRM is not set +# CONFIG_DS1682 is not set +# CONFIG_DTLK is not set +# CONFIG_DUMMY is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_DWC3_HOST_USB3_LPM_ENABLE is not set +# CONFIG_DX_SEP is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_E2100 is not set +# CONFIG_EARLY_PRINTK_8250 is not set +# CONFIG_EASYCAP is not set +# CONFIG_ECHO is not set +# CONFIG_ECONET is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_EDAC is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_DIGSY_MTC_CFG is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEXPRESS is not set +# CONFIG_EEXPRESS_PRO is not set +CONFIG_EFI_PARTITION=y +# CONFIG_EFS_FS is not set +# CONFIG_ELF_CORE is not set +# CONFIG_EMAC_ROCKCHIP is not set +CONFIG_EMBEDDED=y +# CONFIG_EM_TIMER_STI is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENC28J60 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_ENIC is not set +# CONFIG_EPAPR_PARAVIRT is not set +# CONFIG_EPIC100 is not set +CONFIG_EPOLL=y +# CONFIG_EQUALIZER is not set +# CONFIG_ET131X is not set +# CONFIG_GATEWORKS_GW16083 is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_GLOB_SELFTEST is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_ETH16I is not set +CONFIG_ETHERNET=y +# CONFIG_ETHOC is not set +CONFIG_EVENTFD=y +# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set +# CONFIG_EWRK3 is not set +CONFIG_EXPERIMENTAL=y +CONFIG_EXPERT=y +# CONFIG_EXPORTFS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_DEBUG is not set +# CONFIG_EXT4_FS is not set +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_USE_FOR_EXT23=y +# CONFIG_EXTCON is not set +CONFIG_EXTRA_FIRMWARE="" +CONFIG_EXTRA_TARGETS="" +# CONFIG_EXYNOS_ADC is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FAIR_GROUP_SCHED is not set +# CONFIG_FANOTIFY is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_FS is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_FB is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_DA8XX is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GEODE is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_N411 is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_PS3 is not set +# CONFIG_FB_PXA is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_XGI is not set +# CONFIG_FCOE is not set +# CONFIG_FCOE_FNIC is not set +# CONFIG_FDDI is not set +# CONFIG_FEALNX is not set +# CONFIG_FENCE_TRACE is not set +# CONFIG_FHANDLE is not set +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIREWIRE_SERIAL is not set +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FIXED_PHY is not set +CONFIG_FLATMEM=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_FM10K is not set +# CONFIG_FMC is not set +# CONFIG_FORCEDETH is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_FRAME_POINTER is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_FREEZER is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_FSCACHE is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_XGMAC_MDIO is not set +CONFIG_FSNOTIFY=y +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_FT1000 is not set +# CONFIG_FTGMAC100 is not set +# CONFIG_FTL is not set +# CONFIG_FTMAC100 is not set +# CONFIG_FTRACE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_FUJITSU_TABLET is not set +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_FUSE_FS is not set +# CONFIG_FUSION is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set +# CONFIG_FUSION_SPI is not set +CONFIG_FUTEX=y +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_GACT_PROB=y +# CONFIG_GADGET_UAC1 is not set +# CONFIG_GAMEPORT is not set +# CONFIG_GCOV is not set +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GENEVE is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_GENERIC_CALIBRATE_DELAY=y +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_GENERIC_PHY is not set +CONFIG_GENERIC_TIME=y +# CONFIG_GENWQE is not set +# CONFIG_GFS2_FS is not set +# CONFIG_GIGASET_CAPI is not set +# CONFIG_GIGASET_DEBUG is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_GPIOLIB is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_BCM_KONA is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_ICH is not set +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_RDC321X is not set +# CONFIG_GPIO_SCH is not set +# CONFIG_GPIO_SCH311X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_SYSFS is not set +# CONFIG_GPIO_TS5500 is not set +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_GPIO_WDT is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HAMACHI is not set +# CONFIG_HAMRADIO is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HCALL_STATS is not set +# CONFIG_HDLC is not set +# CONFIG_HDLC_CISCO is not set +# CONFIG_HDLC_FR is not set +# CONFIG_HDLC_PPP is not set +# CONFIG_HDLC_RAW is not set +# CONFIG_HDLC_RAW_ETH is not set +# CONFIG_HDQ_MASTER_OMAP is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_HERMES is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_HFSPLUS_FS_POSIX_ACL is not set +# CONFIG_HFS_FS is not set +# CONFIG_HIBERNATION is not set +# CONFIG_HID is not set +# CONFIG_HIDRAW is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_ACRUX_FF is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_LOGITECH_DJ is not set +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PID is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PS3REMOTE is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_ARVO is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_ROCCAT_KONEPLUS is not set +# CONFIG_HID_ROCCAT_KOVAPLUS is not set +# CONFIG_HID_ROCCAT_PYRA is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HIGHMEM is not set +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIP04_ETH is not set +# CONFIG_HIPPI is not set +# CONFIG_HIX5HD2_GMAC is not set +# CONFIG_HMC6352 is not set +# CONFIG_HOSTAP is not set +# CONFIG_HOSTAP_CS is not set +# CONFIG_HOSTAP_PCI is not set +# CONFIG_HOSTAP_PLX is not set +CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HP100 is not set +CONFIG_HPET_MMAP_DEFAULT=y +# CONFIG_HPFS_FS is not set +# CONFIG_HPLAN is not set +# CONFIG_HPLAN_PLUS is not set +# CONFIG_HP_ILO is not set +# CONFIG_HP_WIRELESS is not set +# CONFIG_HSI is not set +# CONFIG_HSR is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_HVC_DCC is not set +# CONFIG_HVC_UDBG is not set +# CONFIG_HWMON is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_HWMON_VID is not set +# CONFIG_HWSPINLOCK_OMAP is not set +CONFIG_HW_PERF_EVENTS=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set +# CONFIG_HW_RANDOM_GEODE is not set +# CONFIG_HW_RANDOM_INTEL is not set +# CONFIG_HW_RANDOM_OMAP3_ROM is not set +# CONFIG_HW_RANDOM_PPC4XX is not set +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_VIA is not set +# CONFIG_HYPERV is not set +# CONFIG_HYSDN is not set +CONFIG_HZ=100 +CONFIG_HZ_100=y +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_48 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_PERIODIC is not set +# CONFIG_I2C is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCA is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_AU1550 is not set +# CONFIG_I2C_BCM2835 is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_ELEKTOR is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_HID is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_IBM_IIC is not set +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +# CONFIG_I2C_MPC is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MV64XXX is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_OCTEON is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PCA_ISA is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_SCMI is not set +# CONFIG_I2C_SH_MOBILE is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_SMBUS is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VERSATILE is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2O is not set +# CONFIG_I40E is not set +# CONFIG_I40EVF is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_I82092 is not set +# CONFIG_I82365 is not set +# CONFIG_IBM_ASM is not set +# CONFIG_IBM_EMAC_DEBUG is not set +# CONFIG_IBM_EMAC_EMAC4 is not set +# CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_EMAC_MAL_COMMON_ERR is not set +# CONFIG_IBM_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_EMAC_RGMII is not set +# CONFIG_IBM_EMAC_TAH is not set +# CONFIG_IBM_EMAC_ZMII is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_ICS932S401 is not set +# CONFIG_IDE is not set +# CONFIG_IDEAPAD_LAPTOP is not set +# CONFIG_IDE_GD is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IEEE802154 is not set +# CONFIG_IFB is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IIO is not set +# CONFIG_IIO_BUFFER_CB is not set +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_GPIO_TRIGGER is not set +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_IIO_SSP_SENSORHUB is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +# CONFIG_IKCONFIG is not set +# CONFIG_IKCONFIG_PROC is not set +# CONFIG_IMAGE_CMDLINE_HACK is not set +# CONFIG_IMGPDC_WDT is not set +# CONFIG_IMX_IPUV3_CORE is not set +CONFIG_INET=y +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_DIAG is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_TCP_DIAG is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INFINIBAND is not set +# CONFIG_INFTL is not set +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_INITRAMFS_COMPRESSION_NONE=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_INIT_FALLBACK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_INOTIFY_USER=y +# CONFIG_INPUT is not set +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_APANEL is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATLAS_BTNS is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PCSPKR is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_WISTRON_BTNS is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INT340X_THERMAL is not set +# CONFIG_INTEL_IDLE is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_INTEL_MEI_ME is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_INTEL_MIC_CARD is not set +# CONFIG_INTEL_MIC_HOST is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_INTEL_OAKTRAIL is not set +# CONFIG_INTEL_RST is not set +# CONFIG_INTEL_SMARTCONNECT is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_INV_MPU6050_IIO is not set +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_NOOP=y +# CONFIG_IP1000 is not set +# CONFIG_IP17XX_PHY is not set +# CONFIG_IP6_NF_FILTER is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP6_NF_MANGLE is not set +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_NAT is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_TARGET_LOG is not set +# CONFIG_IP6_NF_TARGET_REJECT is not set +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +# CONFIG_IPACK_BUS is not set +# CONFIG_IPC_NS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPV6 is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_ROUTE_INFO is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_SIT_6RD is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_VTI is not set +# CONFIG_IPVLAN is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2100_DEBUG is not set +CONFIG_IPW2100_MONITOR=y +# CONFIG_IPW2200 is not set +# CONFIG_IPW2200_DEBUG is not set +CONFIG_IPW2200_MONITOR=y +# CONFIG_IPW2200_PROMISCUOUS is not set +# CONFIG_IPW2200_QOS is not set +# CONFIG_IPW2200_RADIOTAP is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_IPX is not set +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_DCCP is not set +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_NF_ARPFILTER is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARP_MANGLE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_SECURITY is not set +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_MASQUERADE is not set +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_REDIRECT is not set +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +# CONFIG_IP_PNP is not set +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_SCTP is not set +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set +# CONFIG_IRDA is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_IRQ_ALL_CPUS is not set +# CONFIG_IRQ_DOMAIN_DEBUG is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_IR_HIX5HD2 is not set +# CONFIG_IR_IGUANA is not set +# CONFIG_IR_IMG is not set +# CONFIG_IR_IMON is not set +# CONFIG_IR_JVC_DECODER is not set +# CONFIG_IR_LIRC_CODEC is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_NEC_DECODER is not set +# CONFIG_IR_RC5_DECODER is not set +# CONFIG_IR_RC5_SZ_DECODER is not set +# CONFIG_IR_RC6_DECODER is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_SONY_DECODER is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_IR_TTUSBIR is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_ISCSI_TCP is not set +CONFIG_ISDN=y +# CONFIG_ISDN_AUDIO is not set +# CONFIG_ISDN_CAPI is not set +# CONFIG_ISDN_CAPI_CAPIDRV is not set +# CONFIG_ISDN_DIVERSION is not set +# CONFIG_ISDN_DRV_ACT2000 is not set +# CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON is not set +# CONFIG_ISDN_DRV_GIGASET is not set +# CONFIG_ISDN_DRV_HISAX is not set +# CONFIG_ISDN_DRV_ICN is not set +# CONFIG_ISDN_DRV_LOOP is not set +# CONFIG_ISDN_DRV_PCBIT is not set +# CONFIG_ISDN_DRV_SC is not set +# CONFIG_ISDN_I4L is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_ISL29125 is not set +# CONFIG_ISO9660_FS is not set +# CONFIG_ISS4xx is not set +# CONFIG_ITG3200 is not set +# CONFIG_IWL3945 is not set +# CONFIG_IWLAGN is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWMC3200TOP is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_JBD is not set +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_POSIX_ACL is not set +# CONFIG_JFFS2_FS_SECURITY is not set +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_LZMA=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_ZLIB is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_JME is not set +CONFIG_JOLIET=y +# CONFIG_JSA1212 is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_UNCOMPRESSED is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_MODE_NEON=y +CONFIG_KERNEL_XZ=y +CONFIG_KERNFS=y +# CONFIG_KEXEC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_CAP1106 is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PXA27x is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_SH_KEYSC is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_KGDB is not set +# CONFIG_KMEMCHECK is not set +# CONFIG_KMX61 is not set +# CONFIG_KPROBES is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_KSM is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_KVM_GUEST is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_KXSD9 is not set +# CONFIG_L2TP is not set +# CONFIG_L2TP_ETH is not set +# CONFIG_L2TP_IP is not set +# CONFIG_L2TP_V3 is not set +# CONFIG_LANMEDIA is not set +# CONFIG_LANTIQ is not set +# CONFIG_LAPB is not set +# CONFIG_LASAT is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_LBDAF=y +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_LEDS_ATMEL_PWM is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_BLINKM is not set +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_GPIO_OF=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_INTEL_SS4200 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3556 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_NET5501 is not set +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA9685 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_TCA6507 is not set +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +# CONFIG_LEDS_TRIGGER_MORSE is not set +CONFIG_LEDS_TRIGGER_NETDEV=y +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +CONFIG_LEDS_TRIGGER_TIMER=y +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_USBDEV is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LIB80211 is not set +# CONFIG_LIB80211_CRYPT_CCMP is not set +# CONFIG_LIB80211_CRYPT_TKIP is not set +# CONFIG_LIB80211_CRYPT_WEP is not set +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_LIBERTAS_USB is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_LIBIPW_DEBUG is not set +# CONFIG_LINE6_USB is not set +# CONFIG_LIRC_STAGING is not set +# CONFIG_LIS3L02DQ is not set +# CONFIG_LKDTM is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_LOCKD is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_LOGFS is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_LOGO is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +# CONFIG_LOONGSON_MC146818 is not set +# CONFIG_LP486E is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_LP_CONSOLE is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_LTR501 is not set +# CONFIG_LTPC is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_LXT_PHY is not set +# CONFIG_LZ4HC_COMPRESS is not set +CONFIG_LZMA_COMPRESS=y +CONFIG_LZMA_DECOMPRESS=y +# CONFIG_LZO_COMPRESS is not set +# CONFIG_LZO_DECOMPRESS is not set +# CONFIG_M25PXX_PREFER_SMALL_SECTOR_ERASE is not set +# CONFIG_MAC80211 is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MACB is not set +# CONFIG_MACH_ASM9260 is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set +# CONFIG_MACH_NO_WESTBRIDGE is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_MACINTOSH_DRIVERS is not set +# CONFIG_MACVLAN is not set +# CONFIG_MACVTAP is not set +# CONFIG_MAC_EMUMOUSEBTN is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MAG3110 is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +# CONFIG_MAILBOX is not set +# CONFIG_MANGLE_BOOTARGS is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MCB is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_MCPM is not set +# CONFIG_MD is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_ATTACH is not set +# CONFIG_MEDIA_CAMERA_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_PARPORT_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_MEMORY is not set +# CONFIG_MEMORY_FAILURE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_CS5535 is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_OMAP_USB_HOST is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MG_DISK is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MIGRATION is not set +CONFIG_MII=y +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MIPS_FPU_EMULATOR is not set +# CONFIG_MIPS_O32_FP64_SUPPORT is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_PARAVIRT is not set +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_MIPS_SIM is not set +CONFIG_MISC_DEVICES=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_MISDN is not set +# CONFIG_MISDN_AVMFRITZ is not set +# CONFIG_MISDN_HFCPCI is not set +# CONFIG_MISDN_HFCUSB is not set +# CONFIG_MISDN_INFINEON is not set +# CONFIG_MISDN_NETJET is not set +# CONFIG_MISDN_SPEEDFAX is not set +# CONFIG_MISDN_W6692 is not set +# CONFIG_MKISS is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MMC is not set +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_AU1X is not set +# CONFIG_MMC_BLOCK is not set +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_MVSDIO is not set +# CONFIG_MMC_S3C is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_ACPI is not set +# CONFIG_MMC_SDHCI_BCM_KONA is not set +# CONFIG_MMC_SDHCI_MSM is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ESDHC is not set +# CONFIG_MMC_SDHCI_OF_HLWD is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDRICOH_CS is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMIOTRACE is not set +CONFIG_MMU=y +CONFIG_MODULES=y +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULE_STRIPPED=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_INPORT is not set +# CONFIG_MOUSE_LOGIBM is not set +# CONFIG_MOUSE_PC110PAD is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_MPL115 is not set +# CONFIG_MPL3115 is not set +# CONFIG_MSDOS_FS is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_MSI_LAPTOP is not set +CONFIG_MTD=y +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_BLOCK2MTD is not set +CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_CHAR=y +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LATCH_ADDR is not set +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +# CONFIG_MTD_M25P80 is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_MYLOADER_PARTS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_NAND_AMS_DELTA is not set +# CONFIG_MTD_NAND_AR934X is not set +# CONFIG_MTD_NAND_AR934X_HW_ECC is not set +# CONFIG_MTD_NAND_ATMEL is not set +# CONFIG_MTD_NAND_AU1550 is not set +# CONFIG_MTD_NAND_AUTCPU12 is not set +# CONFIG_MTD_NAND_BCH is not set +# CONFIG_MTD_NAND_BCM_UMI is not set +# CONFIG_MTD_NAND_BF5XX is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_CM_X270 is not set +# CONFIG_MTD_NAND_CS553X is not set +# CONFIG_MTD_NAND_DAVINCI is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018 +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_ECC is not set +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_NAND_FSL_IFC is not set +# CONFIG_MTD_NAND_FSL_UPM is not set +# CONFIG_MTD_NAND_FSMC is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_GPMI_NAND is not set +# CONFIG_MTD_NAND_H1900 is not set +# CONFIG_MTD_NAND_HISI504 is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_JZ4740 is not set +# CONFIG_MTD_NAND_MPC5121_NFC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_MXC is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_NOMADIK is not set +# CONFIG_MTD_NAND_NUC900 is not set +# CONFIG_MTD_NAND_OMAP2 is not set +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set +# CONFIG_MTD_NAND_ORION is not set +# CONFIG_MTD_NAND_PASEMI is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_NAND_PPCHAMELEONEVB is not set +# CONFIG_MTD_NAND_PXA3xx is not set +# CONFIG_MTD_NAND_RB4XX is not set +# CONFIG_MTD_NAND_RB750 is not set +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_RTC_FROM4 is not set +# CONFIG_MTD_NAND_S3C2410 is not set +# CONFIG_MTD_NAND_SHARPSL is not set +# CONFIG_MTD_NAND_SH_FLCTL is not set +# CONFIG_MTD_NAND_SOCRATES is not set +# CONFIG_MTD_NAND_SPIA is not set +# CONFIG_MTD_NAND_TMIO is not set +# CONFIG_MTD_NAND_TXX9NDFMC is not set +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_PCMCIA is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_ROM is not set +CONFIG_MTD_ROOTFS_ROOT_DEV=y +CONFIG_MTD_ROOTFS_SPLIT=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SPI_NOR is not set +# CONFIG_MTD_SPINAND_MT29F is not set +CONFIG_MTD_SPLIT=y +# CONFIG_MTD_SPLIT_FIRMWARE is not set +CONFIG_MTD_SPLIT_FIRMWARE_NAME="firmware" +# CONFIG_MTD_SPLIT_FIT_FW is not set +# CONFIG_MTD_SPLIT_LZMA_FW is not set +# CONFIG_MTD_SPLIT_SEAMA_FW is not set +CONFIG_MTD_SPLIT_SQUASHFS_ROOT=y +CONFIG_MTD_SPLIT_SUPPORT=y +# CONFIG_MTD_SPLIT_TRX_FW is not set +# CONFIG_MTD_SPLIT_TPLINK_FW is not set +# CONFIG_MTD_SPLIT_UIMAGE_FW is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_UBI is not set +# CONFIG_MTD_UIMAGE_SPLIT is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_MVMDIO is not set +# CONFIG_MVSW61XX_PHY is not set +# CONFIG_MVSW6171_PHY is not set +# CONFIG_MVSWITCH_PHY is not set +# CONFIG_MWAVE is not set +# CONFIG_MWL8K is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NATSEMI is not set +# CONFIG_NAU7802 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_NCP_FS is not set +# CONFIG_NE2000 is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NEC_MARKEINS is not set +CONFIG_NET=y +# CONFIG_NETCONSOLE is not set +CONFIG_NETDEVICES=y +CONFIG_NETDEV_1000=y +# CONFIG_NETDEV_10000 is not set +# CONFIG_NETFILTER is not set +# CONFIG_NETFILTER_ADVANCED is not set +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_QUEUE_CT is not set +# CONFIG_NETFILTER_TPROXY is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LAYER7 is not set +# CONFIG_NETFILTER_XT_MATCH_LAYER7_DEBUG is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NETROM is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NET_9P is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_VLAN is not set +CONFIG_NET_CADENCE=y +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_ACT is not set +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_IND=y +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_U32 is not set +CONFIG_NET_CORE=y +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_NET_DSA is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6171 is not set +# CONFIG_NET_DSA_MV88E6352 is not set +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_NBYTE is not set +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_TEXT is not set +# CONFIG_NET_EMATCH_U32 is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_FC is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_NET_IPGRE is not set +CONFIG_NET_IPGRE_BROADCAST=y +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_IP_TUNNEL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_KEY is not set +# CONFIG_NET_KEY_MIGRATE is not set +# CONFIG_NET_MPLS_GSO is not set +# CONFIG_NET_PACKET_ENGINE is not set +CONFIG_NET_PCI=y +# CONFIG_NET_PCMCIA is not set +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_POCKET is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_NET_PTP_CLASSIFY is not set +CONFIG_NET_RX_BUSY_POLL=y +# CONFIG_NET_SB1000 is not set +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_ATM is not set +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_ESFQ is not set +CONFIG_NET_SCH_ESFQ_NFCT=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_NET_SCH_FQ is not set +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCTPPROBE is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_TEAM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_NET_UDP_TUNNEL is not set +CONFIG_NET_VENDOR_3COM=y +CONFIG_NET_VENDOR_8390=y +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_NET_VENDOR_AGERE=y +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CIRRUS=y +CONFIG_NET_VENDOR_CISCO=y +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_VENDOR_DLINK=y +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_NET_VENDOR_EXAR=y +CONFIG_NET_VENDOR_FARADAY=y +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HP=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_IBM=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_MICREL=y +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_NET_VENDOR_OKI=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_NET_VENDOR_RDC=y +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_NET_VENDOR_SILICOM=y +CONFIG_NET_VENDOR_SIS=y +CONFIG_NET_VENDOR_SMSC=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_NET_VENDOR_SUN=y +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_NET_VENDOR_TI=y +CONFIG_NET_VENDOR_TOSHIBA=y +CONFIG_NET_VENDOR_VIA=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +CONFIG_NET_VENDOR_XIRCOM=y +# CONFIG_NET_XGENE is not set +CONFIG_NEW_LEDS=y +# CONFIG_NFC is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_DEPRECATED is not set +# CONFIG_NFSD_V2_ACL is not set +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +# CONFIG_NFS_ACL_SUPPORT is not set +CONFIG_NFS_COMMON=y +# CONFIG_NFS_FS is not set +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_V4_1 is not set +# CONFIG_NFTL is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IPV4 is not set +# CONFIG_NF_CONNTRACK_IPV6 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set +# CONFIG_NF_CONNTRACK_RTSP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_GRE is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +# CONFIG_NF_NAT is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_FTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_IPV6 is not set +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set +# CONFIG_NF_NAT_MASQUERADE_IPV6 is not set +# CONFIG_NF_NAT_NEEDED is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_PROTO_GRE is not set +# CONFIG_NF_NAT_RTSP is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_REJECT_IPV4 is not set +# CONFIG_NF_TABLES is not set +# CONFIG_NI52 is not set +# CONFIG_NI65 is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NIU is not set +CONFIG_NLATTR=y +# CONFIG_NLMON is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLS is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NORTEL_HERMES is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_NOZOMI is not set +# CONFIG_NO_BOOTMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_NS83820 is not set +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_NTP_PPS is not set +# CONFIG_NVRAM is not set +# CONFIG_NV_TCO is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_N_GSM is not set +# CONFIG_OABI_COMPAT is not set +# CONFIG_OBS600 is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_OCF_BENCH is not set +# CONFIG_OCF_C7108 is not set +# CONFIG_OCF_CRYPTOCTEON is not set +# CONFIG_OCF_EP80579 is not set +# CONFIG_OCF_HIFN is not set +# CONFIG_OCF_HIFNHIPP is not set +# CONFIG_OCF_IXP4XX is not set +# CONFIG_OCF_KIRKWOOD is not set +# CONFIG_OCF_OCF is not set +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_SAFE is not set +# CONFIG_OCF_TALITOS is not set +# CONFIG_OCF_UBSEC_SSB is not set +# CONFIG_OC_ETM is not set +# CONFIG_OF_OVERLAY is not set +# CONFIG_OF_SELFTEST is not set +# CONFIG_OF_UNITTEST is not set +# CONFIG_OMAP2_DSS_DEBUG is not set +# CONFIG_OMAP2_DSS_DEBUGFS is not set +# CONFIG_OMAP2_DSS_SDI is not set +# CONFIG_OMAP_CONTROL_USB is not set +# CONFIG_OMAP_OCP2SCP is not set +# CONFIG_OMAP_USB2 is not set +# CONFIG_OMAP_USB3 is not set +# CONFIG_OMFS_FS is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_OPROFILE is not set +# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set +# CONFIG_ORION_WATCHDOG is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_OVERLAY_FS=y +# CONFIG_P54_COMMON is not set +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PANEL is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PANTHERLORD_FF is not set +# CONFIG_PARPORT is not set +# CONFIG_PARPORT_1284 is not set +# CONFIG_PARPORT_AX88796 is not set +# CONFIG_PARPORT_PC is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARASAN_CF is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CS5535 is not set +# CONFIG_PATA_CS5536 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_ISAPNP is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OCTEON_CF is not set +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PCMCIA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_QDI is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_WINBOND_VLB is not set +# CONFIG_PC300TOO is not set +# CONFIG_PCCARD is not set +# CONFIG_PCH_GBE is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_PCI200SYN is not set +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIEASPM is not set +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_PCI_ATMEL is not set +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set +# CONFIG_PCI_HERMES is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_LAYERSCAPE is not set +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_PCI_PRI is not set +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +CONFIG_PCI_SYSCALL=y +# CONFIG_PCMCIA is not set +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_3C589 is not set +# CONFIG_PCMCIA_AHA152X is not set +# CONFIG_PCMCIA_ATMEL is not set +# CONFIG_PCMCIA_AXNET is not set +# CONFIG_PCMCIA_DEBUG is not set +# CONFIG_PCMCIA_FDOMAIN is not set +# CONFIG_PCMCIA_FMVJ18X is not set +# CONFIG_PCMCIA_HERMES is not set +# CONFIG_PCMCIA_LOAD_CIS is not set +# CONFIG_PCMCIA_NINJA_SCSI is not set +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_PCNET is not set +# CONFIG_PCMCIA_QLOGIC is not set +# CONFIG_PCMCIA_RAYCS is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_SPECTRUM is not set +# CONFIG_PCMCIA_SYM53C500 is not set +# CONFIG_PCMCIA_WL3501 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_XIRCOM is not set +# CONFIG_PCNET32 is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_PD6729 is not set +# CONFIG_PDA_POWER is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_PHANTOM is not set +# CONFIG_PHONE is not set +# CONFIG_PHONET is not set +# CONFIG_PHYLIB is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_PHY_EXYNOS_DP_VIDEO is not set +# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHY_QCOM_DWC3 is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_PID_NS is not set +CONFIG_PINCONF=y +# CONFIG_PINCTRL is not set +# CONFIG_PINCTRL_CAPRI is not set +# CONFIG_PINCTRL_EXYNOS is not set +# CONFIG_PINCTRL_EXYNOS5440 is not set +# CONFIG_PINCTRL_MSM8X74 is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINMUX=y +# CONFIG_PLAT_SPEAR is not set +# CONFIG_PLIP is not set +# CONFIG_PLX_HERMES is not set +# CONFIG_PM is not set +# CONFIG_PMBUS is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_PM_RUNTIME is not set +# CONFIG_PM_WAKELOCKS is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_POHMELFS is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_POWERCAP is not set +# CONFIG_POWERTV is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_VERSATILE is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_DISABLE_WERROR is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_PPC_EPAPR_HV_BYTECHAN is not set +# CONFIG_PPP is not set +# CONFIG_PPPOATM is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +CONFIG_PPP_FILTER=y +# CONFIG_PPP_MPPE is not set +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPS is not set +# CONFIG_PPS_CLIENT_GPIO is not set +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_DEBUG is not set +# CONFIG_PPTP is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_PRINTK=y +# CONFIG_PRINTK_TIME is not set +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_PRISM2_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_PROBE_INITRD_HEADER is not set +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_PROC_STRIPPED=y +CONFIG_PROC_SYSCTL=y +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILING is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_PROVE_RCU is not set +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_PSB6970_PHY is not set +# CONFIG_PSTORE is not set +# CONFIG_PTP_1588_CLOCK is not set +# CONFIG_PTP_1588_CLOCK_IXP46X is not set +# CONFIG_PTP_1588_CLOCK_PCH is not set +# CONFIG_PWM is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_QCA7000 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_R3964 is not set +# CONFIG_R6040 is not set +# CONFIG_R8169 is not set +# CONFIG_R8187SE is not set +# CONFIG_R8188EU is not set +# CONFIG_R8712U is not set +# CONFIG_R8723AU is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_RADIO_AZTECH is not set +# CONFIG_RADIO_CADET is not set +# CONFIG_RADIO_GEMTEK is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_RTRACK is not set +# CONFIG_RADIO_RTRACK2 is not set +# CONFIG_RADIO_SF16FMI is not set +# CONFIG_RADIO_SF16FMR2 is not set +# CONFIG_RADIO_TERRATEC is not set +# CONFIG_RADIO_TRUST is not set +# CONFIG_RADIO_TYPHOON is not set +# CONFIG_RADIO_ZOLTRIX is not set +# CONFIG_RAID_ATTRS is not set +# CONFIG_RALINK is not set +# CONFIG_RAMOOPS is not set +# CONFIG_RANDOM32_SELFTEST is not set +# CONFIG_RAPIDIO is not set +# CONFIG_RAR_REGISTER is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FAST_NO_HZ is not set +CONFIG_RCU_KTHREAD_PRIO=0 +# CONFIG_RCU_NOCB_CPU is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_USER_QS is not set +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_RC_CORE is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_LOOPBACK is not set +# CONFIG_RC_MAP is not set +# CONFIG_RDS is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_XZ is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_REDWOOD is not set +# CONFIG_REGMAP is not set +# CONFIG_REGMAP_I2C is not set +# CONFIG_REGMAP_MMIO is not set +# CONFIG_REGMAP_SPI is not set +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ANATOP is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_TI_ABB is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_FS_POSIX_ACL is not set +# CONFIG_REISERFS_FS_SECURITY is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_RELAY is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_RFD_FTL is not set +# CONFIG_RFKILL is not set +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_ROCKER is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_ROSE is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RT2X00 is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_RTC_DEBUG is not set +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ARMADA38X is not set +# CONFIG_RTC_DRV_AU1XXX is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_BQ4802 is not set +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_EP93XX is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_GENERIC is not set +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12057 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_MOXART is not set +# CONFIG_RTC_DRV_MPC5121 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_OMAP is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_PS3 is not set +# CONFIG_RTC_DRV_PT7C4338 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_RTC7301 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_SUN6I is not set +# CONFIG_RTC_DRV_TEST is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_XGENE is not set +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_SYSTOHC=y +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_RTL8192E is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTL8306_PHY is not set +# CONFIG_RTL8366RB_PHY is not set +# CONFIG_RTL8366S_PHY is not set +# CONFIG_RTL8366_SMI is not set +# CONFIG_RTL8366_SMI_DEBUG_FS is not set +# CONFIG_RTL8367B_PHY is not set +# CONFIG_RTL8367_PHY is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_RTS5139 is not set +# CONFIG_RTS5208 is not set +# CONFIG_RTS_PSTOR is not set +CONFIG_RT_MUTEXES=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_RUNTIME_DEBUG is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_S2IO is not set +# CONFIG_SAMPLES is not set +# CONFIG_SAMSUNG_LAPTOP is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_FSL is not set +# CONFIG_SATA_HIGHBANK is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_SATA_PMP is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_RCAR is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SBC_FITPC2_WATCHDOG is not set +# CONFIG_SBE_2T3E3 is not set +# CONFIG_SBYPASS is not set +# CONFIG_SC92031 is not set +# CONFIG_SCA3000 is not set +# CONFIG_SCC is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHED_MC is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y +# CONFIG_SCHED_SMT is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_7000FASST is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_AHA152X is not set +# CONFIG_SCSI_AHA1542 is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_DTC3280 is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_GENERIC_NCR5380 is not set +# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_IN2000 is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_ISCI is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_LPFC is not set +CONFIG_SCSI_MOD=y +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVSAS_DEBUG is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_NCR53C406A is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_SCSI_PAS16 is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PROC_FS=y +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLOGIC_FAS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_T128 is not set +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_ULTRASTOR is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCx200_ACB is not set +# CONFIG_SDIO_UART is not set +# CONFIG_SECCOMP is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SEEQ8005 is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_ACPI_POWER is not set +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATK0110 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_GSC is not set +# CONFIG_SENSORS_HDAPS is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HMC5843 is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_K10TEMP is not set +# CONFIG_SENSORS_K8TEMP is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VIA_CPUTEMP is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_ACCENT is not set +# CONFIG_SERIAL_8250_BOCA is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DMA=y +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_EM is not set +# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_8250_FOURPORT is not set +# CONFIG_SERIAL_8250_HUB6 is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_NR_UARTS=2 +# CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_SYSRQ is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_SERIAL_OF_PLATFORM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SH_SCI is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIO is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SFC is not set +# CONFIG_SFI is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_SHMEM=y +# CONFIG_SH_ETH is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIGMA is not set +CONFIG_SIGNALFD=y +# CONFIG_SIMPLE_GPIO is not set +# CONFIG_SIS190 is not set +# CONFIG_SIS900 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SKY2_DEBUG is not set +CONFIG_SLAB=y +CONFIG_SLABINFO=y +# CONFIG_SLHC is not set +# CONFIG_SLICOSS is not set +# CONFIG_SLIP is not set +# CONFIG_SLOB is not set +# CONFIG_SLUB is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SMARTJOYPLUS_FF is not set +# CONFIG_SMC911X is not set +# CONFIG_SMC9194 is not set +# CONFIG_SMC91X is not set +# CONFIG_SMP is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_SM_FTL is not set +# CONFIG_SND is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +# CONFIG_SND_AD1816A is not set +# CONFIG_SND_AD1848 is not set +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ADLIB is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_ALS100 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALS4000 is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_ASIHPI is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_ATMEL_AC97C is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT2320 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMI8330 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4231 is not set +# CONFIG_SND_CS4236 is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5530 is not set +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1688 is not set +# CONFIG_SND_ES18XX is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FIREWIRE is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_GUSCLASSIC is not set +# CONFIG_SND_GUSEXTREME is not set +# CONFIG_SND_GUSMAX is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_HWDEP is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_INTERWAVE is not set +# CONFIG_SND_INTERWAVE_STB is not set +# CONFIG_SND_ISA is not set +# CONFIG_SND_KIRKWOOD_SOC is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_MIRO is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MPC52xx_SOC_EFIKA is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_MTS64 is not set +# CONFIG_SND_MXS_SOC is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_OPL3SA2 is not set +# CONFIG_SND_OPTI92X_AD1848 is not set +# CONFIG_SND_OPTI92X_CS4231 is not set +# CONFIG_SND_OPTI93X is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_OXYGEN is not set +CONFIG_SND_PCI=y +# CONFIG_SND_PCM is not set +# CONFIG_SND_PCMCIA is not set +# CONFIG_SND_PCM_OSS is not set +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_PDAUDIOCF is not set +# CONFIG_SND_PORTMAN2X4 is not set +# CONFIG_SND_POWERPC_SOC is not set +# CONFIG_SND_PPC is not set +# CONFIG_SND_RAWMIDI is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_RTCTIMER is not set +# CONFIG_SND_SB16 is not set +# CONFIG_SND_SB8 is not set +# CONFIG_SND_SBAWE is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SND_SIS7019 is not set +# CONFIG_SND_SOC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AU1XAUDIO is not set +# CONFIG_SND_SOC_AU1XPSC is not set +# CONFIG_SND_SOC_CACHE_LZO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SND is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_ES8328 is not set +# CONFIG_SND_SOC_EUKREA_TLV320 is not set +# CONFIG_SND_SOC_FSL_ASOC_CARD is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_HDMI_CODEC is not set +# CONFIG_SND_SOC_IMX_ES8328 is not set +# CONFIG_SND_SOC_IMX_SPDIF is not set +# CONFIG_SND_SOC_IMX_WM8962 is not set +# CONFIG_SND_SOC_INTEL_SST is not set +# CONFIG_SND_SOC_MPC5200_AC97 is not set +# CONFIG_SND_SOC_MPC5200_I2S is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1792A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8804 is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_SSCAPE is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_TIMER is not set +# CONFIG_SND_TRIDENT is not set +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_US122L is not set +# CONFIG_SND_USB_USX2Y is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_WAVEFRONT is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SNI_RM is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_SOC_DRA7XX is not set +# CONFIG_SOC_HAS_OMAP2_SDRC is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_TI is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_SOLO6X10 is not set +# CONFIG_SONYPI is not set +# CONFIG_SONY_LAPTOP is not set +# CONFIG_SOUND is not set +# CONFIG_SOUND_PRIME is not set +# CONFIG_SP5100_TCO is not set +# CONFIG_SPARSEMEM_MANUAL is not set +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +# CONFIG_SPARSE_IRQ is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_SPEAKUP is not set +# CONFIG_SPI is not set +# CONFIG_SPINLOCK_TEST is not set +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AU1550 is not set +# CONFIG_SPI_BCM2835 is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_BUTTERFLY is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_FSL_ESPI is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_GPIO_OLD is not set +# CONFIG_SPI_IMG_SPFI is not set +# CONFIG_SPI_LM70_LLP is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_SPI_MPC52xx is not set +# CONFIG_SPI_MPC52xx_PSC is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_OCTEON is not set +# CONFIG_SPI_ORION is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PPC4xx is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_RAMIPS is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TI_QSPI is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_XWAY is not set +# CONFIG_SPMI is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XATTR is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SRAM is not set +# CONFIG_SSB is not set +# CONFIG_SSBI is not set +# CONFIG_SSB_DEBUG is not set +# CONFIG_SSB_DRIVER_GPIO is not set +# CONFIG_SSB_PCMCIAHOST is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSFDC is not set +CONFIG_STACKTRACE_SUPPORT=y +# CONFIG_STACKTRACE is not set +# CONFIG_STACK_TRACER is not set +CONFIG_STAGING=y +# CONFIG_STAGING_MEDIA is not set +CONFIG_STANDALONE=y +CONFIG_STDBINUTILS=y +# CONFIG_STE10XP is not set +# CONFIG_STE_MODEM_RPROC is not set +# CONFIG_STMMAC_ETH is not set +# CONFIG_STMMAC_PLATFORM is not set +# CONFIG_STMMAC_PCI is not set +CONFIG_STP=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_STUB_POULSBO is not set +# CONFIG_SUNDANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_SUNRPC is not set +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SUSPEND is not set +CONFIG_SWAP=y +# CONFIG_SWCONFIG is not set +# CONFIG_SWCONFIG_LEDS is not set +# CONFIG_SX9500 is not set +# CONFIG_SXGBE_ETH is not set +# CONFIG_SYNCLINK_CS is not set +CONFIG_SYN_COOKIES=y +CONFIG_SYSCTL=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_SYSFS=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_SYSV_FS is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_T5403 is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_TASKS_RCU is not set +# CONFIG_TC35815 is not set +# CONFIG_TCG_TPM is not set +# CONFIG_TCIC is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_MD5SIG is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_TEGRA_AHB is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_TEHUTI is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_MODULE is not set +# CONFIG_TEST_POWER is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_USER_COPY is not set +CONFIG_TEXTSEARCH=y +# CONFIG_TEXTSEARCH_BM is not set +# CONFIG_TEXTSEARCH_FSM is not set +# CONFIG_TEXTSEARCH_KMP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_THINKPAD_ACPI is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_THUNDERBOLT is not set +# CONFIG_TICK_CPU_ACCOUNTING is not set +CONFIG_TICK_ONESHOT=y +# CONFIG_TIFM_CORE is not set +# CONFIG_TIGON3 is not set +# CONFIG_TIMB_DMA is not set +CONFIG_TIMERFD=y +# CONFIG_TIMER_STATS is not set +CONFIG_TINY_RCU=y +# CONFIG_TIPC is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_AM335X_ADC is not set +# CONFIG_TI_CPSW is not set +# CONFIG_TI_CPSW_ALE is not set +# CONFIG_TI_CPTS is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_TI_DAVINCI_CPDMA is not set +# CONFIG_TI_DAVINCI_MDIO is not set +# CONFIG_TI_ST is not set +# CONFIG_TLAN is not set +# CONFIG_TMD_HERMES is not set +# CONFIG_TMP006 is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +CONFIG_TMPFS_XATTR=y +# CONFIG_TOPSTAR_LAPTOP is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_TOSHIBA_HAPS is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_S3C2410 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TR is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_TRACER_SNAPSHOT is not set +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_TRACE_SINK is not set +CONFIG_TRACING_SUPPORT=y +CONFIG_TRAD_SIGNALS=y +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_TRANZPORT is not set +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TREE_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set +# CONFIG_TSL4531 is not set +CONFIG_TTY=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_TUN is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6030_GPADC is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_TYPHOON is not set +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_UDF_FS is not set +CONFIG_UDF_NLS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_UFS_FS is not set +# CONFIG_UHID is not set +CONFIG_UIDGID_STRICT_TYPE_CHECKS=y +# CONFIG_UIO is not set +# CONFIG_ULTRA is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_UNIX_DIAG is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_UPROBE_EVENT is not set +# CONFIG_UPROBES is not set +# CONFIG_USB is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_ADUTUX is not set +CONFIG_USB_ALI_M5632=y +# CONFIG_USB_AMD5536UDC is not set +CONFIG_USB_AN2720=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_ATM is not set +# CONFIG_USB_BDC_UDC is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_BTMTK is not set +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_CONFIGFS is not set +# CONFIG_USB_CXACRU is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_DEBUG is not set +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_DWC2_DUAL_ROLE is not set +# CONFIG_USB_DWC2_HOST is not set +# CONFIG_USB_DWC2_PERIPHERAL is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC3_EXYNOS is not set +# CONFIG_USB_DWC3_QCOM is not set +# CONFIG_USB_DWC3_PCI is not set +# CONFIG_USB_DWC3_KEYSTONE is not set +# CONFIG_USB_DWC_OTG_LPM is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_EHCI_HCD_AT91 is not set +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_EHCI_MSM is not set +# CONFIG_USB_EHCI_MV is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_ET61X251 is not set +CONFIG_USB_EZUSB=y +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_FSL_USB2 is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_VBUS_DRAW=2 +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STK1135 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_HID is not set +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_INPUT_IMS_PCU is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_ISP1760 is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_KBD is not set +# CONFIG_USB_KC2190 is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LIBUSUAL is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_M5602 is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_MSM_OTG is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_NET_AX88179_178A is not set +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_CDC_NCM is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_OHCI_HCD_PCI is not set +# CONFIG_USB_OHCI_HCD_PPC_OF is not set +# CONFIG_USB_OHCI_HCD_PPC_OF_BE is not set +# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set +# CONFIG_USB_OHCI_HCD_PPC_SOC is not set +# CONFIG_USB_OHCI_HCD_SSB is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_FSM is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_PHY is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_PWC_INPUT_EVDEV is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RCAR_PHY is not set +# CONFIG_USB_RENESAS_USBHS is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_S2255 is not set +# CONFIG_USB_S3C_HSOTG is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_DEBUG is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_GARMIN is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +CONFIG_USB_SERIAL_KEYSPAN_MPR=y +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +CONFIG_USB_SERIAL_KEYSPAN_USA18X=y +CONFIG_USB_SERIAL_KEYSPAN_USA19=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y +CONFIG_USB_SERIAL_KEYSPAN_USA19W=y +CONFIG_USB_SERIAL_KEYSPAN_USA28=y +CONFIG_USB_SERIAL_KEYSPAN_USA28X=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +CONFIG_USB_SERIAL_KEYSPAN_USA49W=y +CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_SERIAL_QUATECH_USB2 is not set +# CONFIG_USB_SERIAL_SAFE is not set +CONFIG_USB_SERIAL_SAFE_PADDED=y +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_ZTE is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_SPEEDTOUCH is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_TMC is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_UEAGLEATM is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_USS720 is not set +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +# CONFIG_USB_VL600 is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_XUSBATM is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USELIB is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_USE_OF is not set +# CONFIG_UTS_NS is not set +# CONFIG_UWB is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VETH is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_VF610_ADC is not set +# CONFIG_VFAT_FS is not set +# CONFIG_VGASTATE is not set +# CONFIG_VGA_ARB is not set +# CONFIG_VGA_SWITCHEROO is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT848 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_BWQCAM is not set +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_CAPTURE_DRIVERS is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CQCAM is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_CX2341X is not set +# CONFIG_VIDEO_CX25840 is not set +# CONFIG_VIDEO_CX88 is not set +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_DM6446_CCDC is not set +# CONFIG_VIDEO_DT3155 is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +# CONFIG_VIDEO_HEXIUM_GEMINI is not set +# CONFIG_VIDEO_HEXIUM_ORION is not set +# CONFIG_VIDEO_IR_I2C is not set +# CONFIG_VIDEO_IVTV is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_MEDIA is not set +# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MXB is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_OMAP2_VOUT is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_SAA6588 is not set +# CONFIG_VIDEO_SAA6752HS is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7134 is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TM6000 is not set +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_USBTV is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_VIDEO_V4L2 is not set +# CONFIG_VIDEO_V4L2_COMMON is not set +# CONFIG_VIDEO_V4L2_INT_DEVICE is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTUALIZATION is not set +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRT_TO_BUS=y +# CONFIG_VITESSE_PHY is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_VME_BUS is not set +# CONFIG_VMSPLIT_1G is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_2G_OPT is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMWARE_PVSCSI is not set +# CONFIG_VMXNET3 is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_VORTEX is not set +# CONFIG_VSOCKETS is not set +# CONFIG_VT is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_VXFS_FS is not set +# CONFIG_VXGE is not set +# CONFIG_VXLAN is not set +# CONFIG_W1 is not set +# CONFIG_W1_CON is not set +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_GPIO is not set +# CONFIG_W1_MASTER_MATROX is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +# CONFIG_W1_SLAVE_DS2406 is not set +# CONFIG_W1_SLAVE_DS2408 is not set +# CONFIG_W1_SLAVE_DS2413 is not set +# CONFIG_W1_SLAVE_DS2423 is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_DS2780 is not set +# CONFIG_W1_SLAVE_DS2781 is not set +# CONFIG_W1_SLAVE_DS28E04 is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W35UND is not set +# CONFIG_W83627HF_WDT is not set +# CONFIG_W83697HF_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_W83977F_WDT is not set +# CONFIG_WAN is not set +# CONFIG_WANXL is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WD80x3 is not set +# CONFIG_WDTPCI is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PRIV=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WILINK_PLATFORM_DATA=y +# CONFIG_WIMAX is not set +# CONFIG_WIMAX_GDM72XX is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +# CONFIG_WIRELESS_EXT_SYSFS is not set +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLAGS49_H2 is not set +# CONFIG_WLAGS49_H25 is not set +CONFIG_WLAN=y +# CONFIG_WLCORE is not set +CONFIG_WL_TI=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_WR_PPMC is not set +# CONFIG_X25 is not set +# CONFIG_X86_DEBUG_STATIC_CPU_HAS is not set +# CONFIG_X86_PKG_TEMP_THERMAL is not set +CONFIG_X86_SYSFB=y +# CONFIG_XEN is not set +CONFIG_XFRM=y +# CONFIG_XFRM_IPCOMP is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_USER is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_XFS_FS is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_EMACLITE is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_XMON is not set +# CONFIG_XVMALLOC is not set +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_BCJ is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_TEST is not set +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_YAM is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_YENTA is not set +# CONFIG_YENTA_O2 is not set +# CONFIG_YENTA_RICOH is not set +# CONFIG_YENTA_TI is not set +# CONFIG_YENTA_TOSHIBA is not set +# CONFIG_ZBUD is not set +# CONFIG_ZD1211RW is not set +# CONFIG_ZD1211RW_DEBUG is not set +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_ZISOFS is not set +# CONFIG_ZLIB_DEFLATE is not set +# CONFIG_ZLIB_INFLATE is not set +# CONFIG_ZNET is not set +# CONFIG_ZPOOL is not set +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_ZRAM is not set +# CONFIG_ZSMALLOC is not set diff --git a/target/linux/generic/config-4.1 b/target/linux/generic/config-4.1 new file mode 100644 index 0000000..d5e21ab --- /dev/null +++ b/target/linux/generic/config-4.1 @@ -0,0 +1,4814 @@ +CONFIG_32BIT=y +# CONFIG_6LOWPAN is not set +# CONFIG_6PACK is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_9P_FS is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_AB8500_CORE is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_ACENIC is not set +# CONFIG_ACERHDF is not set +# CONFIG_ACORN_PARTITION is not set +# CONFIG_ACPI_APEI is not set +# CONFIG_ACPI_CUSTOM_METHOD is not set +# CONFIG_ACPI_EXTLOG is not set +# CONFIG_ACPI_HED is not set +# CONFIG_ACPI_INT3403_THERMAL is not set +# CONFIG_ACPI_POWER_METER is not set +# CONFIG_ACPI_QUICKSTART is not set +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +# CONFIG_AD5064 is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686 is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5930 is not set +# CONFIG_AD5933 is not set +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD7746 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD799X is not set +# CONFIG_AD8366 is not set +# CONFIG_AD9523 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16255 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_ADM6996_PHY is not set +# CONFIG_ADM8211 is not set +# CONFIG_ADT7316 is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_ADXRS450 is not set +CONFIG_AEABI=y +# CONFIG_AFFS_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AGP is not set +# CONFIG_AHCI_MVEBU is not set +CONFIG_AIO=y +# CONFIG_AIRO is not set +# CONFIG_AIRO_CS is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_AK09911 is not set +# CONFIG_AK8975 is not set +# CONFIG_AL3320A is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_ALIM7101_WDT is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_ALTERA_MBOX is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_ALX is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_AMD_XGBE is not set +# CONFIG_AMD_XGBE_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_AMILO_RFKILL is not set +# CONFIG_ANDROID is not set +CONFIG_ANON_INODES=y +# CONFIG_APDS9300 is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_APM8018X is not set +# CONFIG_APPLICOM is not set +# CONFIG_AR5523 is not set +# CONFIG_AR7 is not set +# CONFIG_AR8216_PHY is not set +# CONFIG_AR8216_PHY_LEDS is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_EXYNOS is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +# CONFIG_ARCH_HI3xxx is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_MSM_DT is not set +# CONFIG_ARCH_MSM_NODT is not set +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_MULTI_V6 is not set +# CONFIG_ARCH_MULTI_V7 is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_NSPIRE is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2PLUS is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_SHMOBILE_LEGACY is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_WM8505 is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCNET is not set +# CONFIG_ARC_EMAC is not set +# CONFIG_ARM_APPENDED_DTB is not set +# CONFIG_ARM_ARCH_TIMER is not set +# CONFIG_ARM_AT91_ETHER is not set +# CONFIG_ARM_CCI is not set +# CONFIG_ARM_CCI400_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_ARM_CRYPTO is not set +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_ARM_ERRATA_326103 is not set +# CONFIG_ARM_ERRATA_364296 is not set +# CONFIG_ARM_ERRATA_411920 is not set +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_643719 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_KERNMEM_PERMS is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +# CONFIG_ARM_KPROBES_TEST is not set +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +# CONFIG_ARM_PSCI is not set +# CONFIG_ARM_PTDUMP is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_ARM_VIRT_EXT is not set +CONFIG_ARPD=y +# CONFIG_ARTHUR is not set +# CONFIG_AS3935 is not set +# CONFIG_ASM9260_TIMER is not set +# CONFIG_ASUS_LAPTOP is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set +# CONFIG_ASYNC_RAID6_TEST is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_ATA is not set +# CONFIG_ATAGS is not set +CONFIG_ATAGS_PROC=y +# CONFIG_ATALK is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_ATA_ACPI is not set +CONFIG_ATA_BMDMA=y +# CONFIG_ATA_GENERIC is not set +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_ATA_PIIX is not set +CONFIG_ATA_SFF=y +# CONFIG_ATA_VERBOSE_ERROR is not set +# CONFIG_ATH10K is not set +# CONFIG_ATH25 is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH6KL is not set +# CONFIG_ATH6K_LEGACY is not set +# CONFIG_ATH79 is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1C is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL2 is not set +# CONFIG_ATM is not set +# CONFIG_ATMEL is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ATM_AMBASSADOR is not set +# CONFIG_ATM_BR2684 is not set +CONFIG_ATM_BR2684_IPFILTER=y +# CONFIG_ATM_CLIP is not set +CONFIG_ATM_CLIP_NO_ICMP=y +# CONFIG_ATM_DRIVERS is not set +# CONFIG_ATM_DUMMY is not set +# CONFIG_ATM_ENI is not set +# CONFIG_ATM_FIRESTREAM is not set +# CONFIG_ATM_FORE200E is not set +# CONFIG_ATM_HE is not set +# CONFIG_ATM_HORIZON is not set +# CONFIG_ATM_IA is not set +# CONFIG_ATM_IDT77252 is not set +# CONFIG_ATM_LANAI is not set +# CONFIG_ATM_LANE is not set +# CONFIG_ATM_MPOA is not set +# CONFIG_ATM_NICSTAR is not set +# CONFIG_ATM_SOLOS is not set +# CONFIG_ATM_TCP is not set +# CONFIG_ATM_ZATM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ATP is not set +# CONFIG_AUDIT is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTO_ZRELADDR is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_AVERAGE is not set +# CONFIG_AX25 is not set +# CONFIG_AX25_DAMA_SLAVE is not set +# CONFIG_AX88796 is not set +# CONFIG_AXP288_ADC is not set +# CONFIG_AXP288_FUEL_GAUGE is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_B44 is not set +# CONFIG_B53 is not set +# CONFIG_B53_SPI_DRIVER is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_BACKLIGHT_LM3630 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_PANDORA is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +CONFIG_BASE_FULL=y +CONFIG_BASE_SMALL=0 +# CONFIG_BATMAN_ADV is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BAYCOM_EPP is not set +# CONFIG_BAYCOM_PAR is not set +# CONFIG_BAYCOM_SER_FDX is not set +# CONFIG_BAYCOM_SER_HDX is not set +# CONFIG_BCACHE is not set +# CONFIG_BCM3384 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_BCM63XX_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BCMA is not set +# CONFIG_BCMA_DRIVER_GPIO is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMGENET is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BE2NET is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_BGMAC is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_BIG_LITTLE is not set +# CONFIG_BINARY_PRINTF is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_CPQ_DA is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_ATIIXP is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_CS5535 is not set +# CONFIG_BLK_DEV_CS5536 is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_DELKIN is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_IDEACPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDECS is not set +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_BLK_DEV_IDEPNP is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDE_AU1XXX is not set +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_PMEM is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RZ1000 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_SD is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SIS5513 is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SL82C105 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_BLK_DEV_THROTTLING is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_UMC8672 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLOCK=y +# CONFIG_BMA180 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_BMG160 is not set +# CONFIG_BMIPS_GENERIC is not set +# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_BMP280 is not set +# CONFIG_BNA is not set +# CONFIG_BNX2 is not set +# CONFIG_BNX2X is not set +# CONFIG_BONDING is not set +# CONFIG_BOOKE_WDT is not set +CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_BOOT_RAW=y +# CONFIG_BPCTL is not set +CONFIG_BPF=y +# CONFIG_BPF_JIT is not set +CONFIG_BPF_SYSCALL=y +# CONFIG_BPQETHER is not set +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_BRCMFMAC is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMSTB_GISB_ARB is not set +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_EBT_802_3 is not set +# CONFIG_BRIDGE_EBT_AMONG is not set +# CONFIG_BRIDGE_EBT_ARP is not set +# CONFIG_BRIDGE_EBT_ARPREPLY is not set +# CONFIG_BRIDGE_EBT_BROUTE is not set +# CONFIG_BRIDGE_EBT_DNAT is not set +# CONFIG_BRIDGE_EBT_IP is not set +# CONFIG_BRIDGE_EBT_IP6 is not set +# CONFIG_BRIDGE_EBT_LIMIT is not set +# CONFIG_BRIDGE_EBT_LOG is not set +# CONFIG_BRIDGE_EBT_MARK is not set +# CONFIG_BRIDGE_EBT_MARK_T is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_BRIDGE_EBT_PKTTYPE is not set +# CONFIG_BRIDGE_EBT_REDIRECT is not set +# CONFIG_BRIDGE_EBT_SNAT is not set +# CONFIG_BRIDGE_EBT_STP is not set +# CONFIG_BRIDGE_EBT_T_FILTER is not set +# CONFIG_BRIDGE_EBT_T_NAT is not set +# CONFIG_BRIDGE_EBT_ULOG is not set +# CONFIG_BRIDGE_EBT_VLAN is not set +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_NETFILTER is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BROADCOM_PHY is not set +CONFIG_BROKEN_ON_SMP=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_BT is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BT_ATH3K is not set +# CONFIG_BT_BNEP is not set +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +# CONFIG_BT_BREDR is not set +# CONFIG_BT_CMTP is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIBLUECARD is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBT3C is not set +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIBTUART is not set +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIDTL1 is not set +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIUART_3WIRE is not set +# CONFIG_BT_HCIUART_ATH3K is not set +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_HIDP is not set +CONFIG_BT_L2CAP=y +# CONFIG_BT_LE is not set +# CONFIG_BT_MRVL is not set +# CONFIG_BT_RFCOMM is not set +# CONFIG_BUILD_BIN2C is not set +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_SCO=y +# CONFIG_BT_SELFTEST is not set +CONFIG_BUG=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +# CONFIG_C2PORT is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_CAIF is not set +# CONFIG_CAN is not set +# CONFIG_CAN_GS_USB is not set +# CONFIG_CAN_M_CAN is not set +# CONFIG_CAN_RCAR is not set +# CONFIG_CAPI_AVM is not set +# CONFIG_CAPI_EICON is not set +# CONFIG_CAPI_TRACE is not set +CONFIG_CARDBUS=y +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_CARL9170 is not set +# CONFIG_CARMA_FPGA is not set +# CONFIG_CARMA_FPGA_PROGRAM is not set +# CONFIG_CASSINI is not set +CONFIG_CAVIUM_OCTEON_HELPER=y +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_SOC is not set +# CONFIG_CB710_CORE is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_CED1401 is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_CFG80211 is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CGROUPS is not set +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_CHARGER_TWL4030 is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CIFS is not set +# CONFIG_CIFS_ACL is not set +# CONFIG_CIFS_DEBUG is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_NFSD_EXPORT is not set +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB2 is not set +CONFIG_CIFS_STATS=y +# CONFIG_CIFS_STATS2 is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CLEANCACHE is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_CLKSRC_VERSATILE is not set +# CONFIG_CLOCK_THERMAL is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM36651 is not set +# CONFIG_CMA is not set +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_CMDLINE_FROM_BOOTLOADER is not set +# CONFIG_CMDLINE_PARTITION is not set +# CONFIG_CNIC is not set +# CONFIG_CODA_FS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_COMEDI is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_DEBUG is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_QCOM is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_COMPACTION is not set +# CONFIG_COMPAL_LAPTOP is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPILE_TEST is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_CONNECTOR is not set +CONFIG_CONSTRUCTORS=y +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_COPS is not set +# CONFIG_CORDIC is not set +# CONFIG_COREDUMP is not set +# CONFIG_CORESIGHT is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set +# CONFIG_CPU_IDLE_GOV_MENU is not set +# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set +# CONFIG_CRAMFS is not set +CONFIG_CRASHLOG=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_CRC32_BIT is not set +CONFIG_CRC32_SARWATE=y +# CONFIG_CRC32_SELFTEST is not set +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SLICEBY8 is not set +# CONFIG_CRC7 is not set +# CONFIG_CRC8 is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CROSS_COMPILE="" +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_AEAD is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_586 is not set +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_AES_ARM_BS is not set +# CONFIG_CRYPTO_AES_NI_INTEL is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32C_INTEL is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_DEV_ATMEL_AES is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set +# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM is not set +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set +# CONFIG_CRYPTO_DEV_MV_CESA is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QCE is not set +# CONFIG_CRYPTO_DEV_SAHARA is not set +# CONFIG_CRYPTO_DEV_TALITOS is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set +# CONFIG_CRYPTO_HASH is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_PCOMP is not set +# CONFIG_CRYPTO_PCOMP2 is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_RNG is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SALSA20_586 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_TWOFISH_586 is not set +# CONFIG_CRYPTO_TWOFISH_COMMON is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_XZ is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYSTALHD is not set +# CONFIG_CS5535_MFGPT is not set +# CONFIG_CS89x0 is not set +# CONFIG_CUSE is not set +# CONFIG_CW1200 is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXT1E1 is not set +# CONFIG_CYPRESS_FIRMWARE is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DCB is not set +# CONFIG_DDR is not set +# CONFIG_DE600 is not set +# CONFIG_DE620 is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +CONFIG_DEBUG_INFO_REDUCED=y +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +# CONFIG_DEBUG_LOCKDEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_NX_TEST is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_UART_BCM63XX is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_ZBOOT is not set +# CONFIG_DECNET is not set +CONFIG_DEFAULT_CUBIC=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_DEFAULT_NOOP is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_SECURITY="" +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +# CONFIG_DELL_SMO8800 is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_DEVKMEM is not set +# CONFIG_DEVMEM is not set +CONFIG_DEVPORT=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_DEVTMPFS is not set +# CONFIG_DEVTMPFS_MOUNT is not set +# CONFIG_DGAP is not set +# CONFIG_DGNC is not set +# CONFIG_DGRP is not set +# CONFIG_DHT11 is not set +# CONFIG_DIRECT_IO is not set +CONFIG_DISABLE_DEV_COREDUMP=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set +# CONFIG_DISPLAY_CONNECTOR_DVI is not set +# CONFIG_DISPLAY_CONNECTOR_HDMI is not set +# CONFIG_DISPLAY_ENCODER_TFP410 is not set +# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set +# CONFIG_DISPLAY_PANEL_DPI is not set +# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set +# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_DL2K is not set +# CONFIG_DLM is not set +# CONFIG_DM9000 is not set +# CONFIG_DMADEVICES is not set +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMASCC is not set +# CONFIG_DMATEST is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_ENGINE is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_LOG_USERSPACE is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DNET is not set +# CONFIG_DNOTIFY is not set +# CONFIG_DNS_RESOLVER is not set +CONFIG_DOUBLEFAULT=y +CONFIG_DQL=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_DRM is not set +# CONFIG_DS1682 is not set +# CONFIG_DTLK is not set +# CONFIG_DUMMY is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_DWC3_HOST_USB3_LPM_ENABLE is not set +# CONFIG_DX_SEP is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_E2100 is not set +# CONFIG_EARLY_PRINTK_8250 is not set +# CONFIG_EASYCAP is not set +# CONFIG_ECHO is not set +# CONFIG_ECONET is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_EDAC is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_DIGSY_MTC_CFG is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEXPRESS is not set +# CONFIG_EEXPRESS_PRO is not set +CONFIG_EFI_PARTITION=y +# CONFIG_EFS_FS is not set +# CONFIG_ELF_CORE is not set +# CONFIG_EMAC_ROCKCHIP is not set +CONFIG_EMBEDDED=y +# CONFIG_EM_TIMER_STI is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENC28J60 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_ENIC is not set +# CONFIG_EPAPR_PARAVIRT is not set +# CONFIG_EPIC100 is not set +CONFIG_EPOLL=y +# CONFIG_EQUALIZER is not set +# CONFIG_ET131X is not set +# CONFIG_GATEWORKS_GW16083 is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_GLOB_SELFTEST is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_ETH16I is not set +CONFIG_ETHERNET=y +# CONFIG_ETHOC is not set +CONFIG_EVENTFD=y +# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set +# CONFIG_EWRK3 is not set +CONFIG_EXPERIMENTAL=y +CONFIG_EXPERT=y +# CONFIG_EXPORTFS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_DEBUG is not set +# CONFIG_EXT4_ENCRYPTION is not set +# CONFIG_EXT4_FS is not set +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_USE_FOR_EXT23=y +# CONFIG_EXTCON is not set +CONFIG_EXTRA_FIRMWARE="" +CONFIG_EXTRA_TARGETS="" +# CONFIG_EXYNOS_ADC is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_FS is not set +# CONFIG_F2FS_IO_TRACE is not set +# CONFIG_FAIR_GROUP_SCHED is not set +# CONFIG_FANOTIFY is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_FS is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_FB is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_DA8XX is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GEODE is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_N411 is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_PS3 is not set +# CONFIG_FB_PXA is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_TFT is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_XGI is not set +# CONFIG_FCOE is not set +# CONFIG_FCOE_FNIC is not set +# CONFIG_FDDI is not set +# CONFIG_FEALNX is not set +# CONFIG_FENCE_TRACE is not set +# CONFIG_FHANDLE is not set +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIREWIRE_SERIAL is not set +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FIXED_PHY is not set +CONFIG_FLATMEM=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_FM10K is not set +# CONFIG_FMC is not set +# CONFIG_FORCEDETH is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_FRAME_POINTER is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_FREEZER is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_FSCACHE is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_XGMAC_MDIO is not set +CONFIG_FSNOTIFY=y +# CONFIG_FS_DAX is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_FT1000 is not set +# CONFIG_FTGMAC100 is not set +# CONFIG_FTL is not set +# CONFIG_FTMAC100 is not set +# CONFIG_FTRACE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_FUJITSU_TABLET is not set +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_FUSE_FS is not set +# CONFIG_FUSION is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set +# CONFIG_FUSION_SPI is not set +CONFIG_FUTEX=y +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_GACT_PROB=y +# CONFIG_GADGET_UAC1 is not set +# CONFIG_GAMEPORT is not set +# CONFIG_GCOV is not set +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GENEVE is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_GENERIC_CALIBRATE_DELAY=y +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_GENERIC_PHY is not set +CONFIG_GENERIC_TIME=y +# CONFIG_GENWQE is not set +# CONFIG_GFS2_FS is not set +# CONFIG_GIGASET_CAPI is not set +# CONFIG_GIGASET_DEBUG is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_GPIOLIB is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_BCM_KONA is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_ICH is not set +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_RDC321X is not set +# CONFIG_GPIO_SCH is not set +# CONFIG_GPIO_SCH311X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_SYSFS is not set +# CONFIG_GPIO_TS5500 is not set +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_GPIO_WDT is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HAMACHI is not set +# CONFIG_HAMRADIO is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HCALL_STATS is not set +# CONFIG_HDLC is not set +# CONFIG_HDLC_CISCO is not set +# CONFIG_HDLC_FR is not set +# CONFIG_HDLC_PPP is not set +# CONFIG_HDLC_RAW is not set +# CONFIG_HDLC_RAW_ETH is not set +# CONFIG_HDQ_MASTER_OMAP is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_HERMES is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_HFSPLUS_FS_POSIX_ACL is not set +# CONFIG_HFS_FS is not set +# CONFIG_HIBERNATION is not set +# CONFIG_HID is not set +# CONFIG_HIDRAW is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_ACRUX_FF is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_LOGITECH_DJ is not set +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PID is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PS3REMOTE is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_ARVO is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_ROCCAT_KONEPLUS is not set +# CONFIG_HID_ROCCAT_KOVAPLUS is not set +# CONFIG_HID_ROCCAT_PYRA is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HIGHMEM is not set +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIP04_ETH is not set +# CONFIG_HIPPI is not set +# CONFIG_HIX5HD2_GMAC is not set +# CONFIG_HMC6352 is not set +# CONFIG_HOSTAP is not set +# CONFIG_HOSTAP_CS is not set +# CONFIG_HOSTAP_PCI is not set +# CONFIG_HOSTAP_PLX is not set +CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HP100 is not set +CONFIG_HPET_MMAP_DEFAULT=y +# CONFIG_HPFS_FS is not set +# CONFIG_HPLAN is not set +# CONFIG_HPLAN_PLUS is not set +# CONFIG_HP_ILO is not set +# CONFIG_HP_WIRELESS is not set +# CONFIG_HSI is not set +# CONFIG_HSR is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_HVC_DCC is not set +# CONFIG_HVC_UDBG is not set +# CONFIG_HWMON is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_HWMON_VID is not set +# CONFIG_HWSPINLOCK_OMAP is not set +CONFIG_HW_PERF_EVENTS=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set +# CONFIG_HW_RANDOM_GEODE is not set +# CONFIG_HW_RANDOM_INTEL is not set +# CONFIG_HW_RANDOM_IPROC_RNG200 is not set +# CONFIG_HW_RANDOM_OMAP3_ROM is not set +# CONFIG_HW_RANDOM_PPC4XX is not set +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_VIA is not set +# CONFIG_HYPERV is not set +# CONFIG_HYSDN is not set +CONFIG_HZ=100 +CONFIG_HZ_100=y +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_48 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_PERIODIC is not set +# CONFIG_I2C is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCA is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_AU1550 is not set +# CONFIG_I2C_BCM2835 is not set +# CONFIG_I2C_BCM_IPROC is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_ELEKTOR is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_HID is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_IBM_IIC is not set +# CONFIG_I2C_IMG is not set +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +# CONFIG_I2C_MPC is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MV64XXX is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_OCTEON is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PCA_ISA is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_SCMI is not set +# CONFIG_I2C_SH_MOBILE is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_SMBUS is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VERSATILE is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2O is not set +# CONFIG_I40E is not set +# CONFIG_I40EVF is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_I82092 is not set +# CONFIG_I82365 is not set +# CONFIG_IBM_ASM is not set +# CONFIG_IBM_EMAC_DEBUG is not set +# CONFIG_IBM_EMAC_EMAC4 is not set +# CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_EMAC_MAL_COMMON_ERR is not set +# CONFIG_IBM_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_EMAC_RGMII is not set +# CONFIG_IBM_EMAC_TAH is not set +# CONFIG_IBM_EMAC_ZMII is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_ICS932S401 is not set +# CONFIG_IDE is not set +# CONFIG_IDEAPAD_LAPTOP is not set +# CONFIG_IDE_GD is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IEEE802154 is not set +# CONFIG_IFB is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IIO is not set +# CONFIG_IIO_BUFFER_CB is not set +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_GPIO_TRIGGER is not set +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_IIO_SSP_SENSORHUB is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +# CONFIG_IKCONFIG is not set +# CONFIG_IKCONFIG_PROC is not set +# CONFIG_IMAGE_CMDLINE_HACK is not set +# CONFIG_IMGPDC_WDT is not set +# CONFIG_IMX_IPUV3_CORE is not set +CONFIG_INET=y +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_DIAG is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_TCP_DIAG is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INFINIBAND is not set +# CONFIG_INFTL is not set +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_INITRAMFS_COMPRESSION_NONE=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_INIT_FALLBACK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_INOTIFY_USER=y +# CONFIG_INPUT is not set +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_APANEL is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATLAS_BTNS is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PCSPKR is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_WISTRON_BTNS is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INT340X_THERMAL is not set +# CONFIG_INTEL_IDLE is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_INTEL_MEI_ME is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_INTEL_MIC_CARD is not set +# CONFIG_INTEL_MIC_HOST is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_INTEL_OAKTRAIL is not set +# CONFIG_INTEL_RST is not set +# CONFIG_INTEL_SMARTCONNECT is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_INV_MPU6050_IIO is not set +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_NOOP=y +# CONFIG_IP1000 is not set +# CONFIG_IP17XX_PHY is not set +# CONFIG_IP6_NF_FILTER is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP6_NF_MANGLE is not set +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_NAT is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_TARGET_LOG is not set +# CONFIG_IP6_NF_TARGET_REJECT is not set +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +# CONFIG_IPACK_BUS is not set +# CONFIG_IPC_NS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPV6 is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_ROUTE_INFO is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_SIT_6RD is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_VTI is not set +# CONFIG_IPVLAN is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2100_DEBUG is not set +CONFIG_IPW2100_MONITOR=y +# CONFIG_IPW2200 is not set +# CONFIG_IPW2200_DEBUG is not set +CONFIG_IPW2200_MONITOR=y +# CONFIG_IPW2200_PROMISCUOUS is not set +# CONFIG_IPW2200_QOS is not set +# CONFIG_IPW2200_RADIOTAP is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_IPX is not set +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_DCCP is not set +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_NF_ARPFILTER is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARP_MANGLE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_SECURITY is not set +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_MASQUERADE is not set +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_REDIRECT is not set +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +# CONFIG_IP_PNP is not set +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_SCTP is not set +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set +# CONFIG_IRDA is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_IRQ_ALL_CPUS is not set +# CONFIG_IRQ_DOMAIN_DEBUG is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_IR_HIX5HD2 is not set +# CONFIG_IR_IGORPLUGUSB is not set +# CONFIG_IR_IGUANA is not set +# CONFIG_IR_IMG is not set +# CONFIG_IR_IMON is not set +# CONFIG_IR_JVC_DECODER is not set +# CONFIG_IR_LIRC_CODEC is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_NEC_DECODER is not set +# CONFIG_IR_RC5_DECODER is not set +# CONFIG_IR_RC5_SZ_DECODER is not set +# CONFIG_IR_RC6_DECODER is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_SONY_DECODER is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_IR_TTUSBIR is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_ISCSI_TCP is not set +CONFIG_ISDN=y +# CONFIG_ISDN_AUDIO is not set +# CONFIG_ISDN_CAPI is not set +# CONFIG_ISDN_CAPI_CAPIDRV is not set +# CONFIG_ISDN_DIVERSION is not set +# CONFIG_ISDN_DRV_ACT2000 is not set +# CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON is not set +# CONFIG_ISDN_DRV_GIGASET is not set +# CONFIG_ISDN_DRV_HISAX is not set +# CONFIG_ISDN_DRV_ICN is not set +# CONFIG_ISDN_DRV_LOOP is not set +# CONFIG_ISDN_DRV_PCBIT is not set +# CONFIG_ISDN_DRV_SC is not set +# CONFIG_ISDN_I4L is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_ISL29125 is not set +# CONFIG_ISO9660_FS is not set +# CONFIG_ISS4xx is not set +# CONFIG_ITG3200 is not set +# CONFIG_IWL3945 is not set +# CONFIG_IWLAGN is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWMC3200TOP is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_JBD is not set +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_POSIX_ACL is not set +# CONFIG_JFFS2_FS_SECURITY is not set +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_LZMA=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_ZLIB is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_JME is not set +CONFIG_JOLIET=y +# CONFIG_JSA1212 is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_UNCOMPRESSED is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_MODE_NEON=y +CONFIG_KERNEL_XZ=y +CONFIG_KERNFS=y +# CONFIG_KEXEC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP1106 is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PXA27x is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_SH_KEYSC is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_KGDB is not set +# CONFIG_KMEMCHECK is not set +# CONFIG_KMX61 is not set +# CONFIG_KPROBES is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_KSM is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_KVM_GUEST is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_KXSD9 is not set +# CONFIG_L2TP is not set +# CONFIG_L2TP_ETH is not set +# CONFIG_L2TP_IP is not set +# CONFIG_L2TP_V3 is not set +# CONFIG_LANMEDIA is not set +# CONFIG_LANTIQ is not set +# CONFIG_LAPB is not set +# CONFIG_LASAT is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_LBDAF=y +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_LEDS_ATMEL_PWM is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_BLINKM is not set +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_GPIO_OF=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_INTEL_SS4200 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3556 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_NET5501 is not set +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA9685 is not set +# CONFIG_LEDS_PM8941_WLED is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_TCA6507 is not set +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +# CONFIG_LEDS_TRIGGER_MORSE is not set +CONFIG_LEDS_TRIGGER_NETDEV=y +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +CONFIG_LEDS_TRIGGER_TIMER=y +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_USBDEV is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LIB80211 is not set +# CONFIG_LIB80211_CRYPT_CCMP is not set +# CONFIG_LIB80211_CRYPT_TKIP is not set +# CONFIG_LIB80211_CRYPT_WEP is not set +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_LIBERTAS_USB is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_LIBIPW_DEBUG is not set +# CONFIG_LINE6_USB is not set +# CONFIG_LIRC_STAGING is not set +# CONFIG_LIS3L02DQ is not set +# CONFIG_LKDTM is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_LOCKD is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_LOGFS is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_LOGO is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +# CONFIG_LOONGSON_MC146818 is not set +# CONFIG_LP486E is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_LP_CONSOLE is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_LTR501 is not set +# CONFIG_LTPC is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_LXT_PHY is not set +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +# CONFIG_LZ4HC_COMPRESS is not set +CONFIG_LZMA_COMPRESS=y +CONFIG_LZMA_DECOMPRESS=y +# CONFIG_LZO_COMPRESS is not set +# CONFIG_LZO_DECOMPRESS is not set +# CONFIG_M25PXX_PREFER_SMALL_SECTOR_ERASE is not set +# CONFIG_MAC80211 is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MACB is not set +# CONFIG_MACH_ASM9260 is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set +# CONFIG_MACH_NO_WESTBRIDGE is not set +# CONFIG_MACH_PISTACHIO is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_MACINTOSH_DRIVERS is not set +# CONFIG_MACVLAN is not set +# CONFIG_MACVTAP is not set +# CONFIG_MAC_EMUMOUSEBTN is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MAG3110 is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +# CONFIG_MAILBOX is not set +# CONFIG_MANGLE_BOOTARGS is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MCB is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_MCPM is not set +# CONFIG_MD is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_ATTACH is not set +# CONFIG_MEDIA_CAMERA_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_PARPORT_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_MEMORY is not set +# CONFIG_MEMORY_FAILURE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_MEMTEST is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_CS5535 is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_OMAP_USB_HOST is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MG_DISK is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MIGRATION is not set +CONFIG_MII=y +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_MIPS_CDMM is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MIPS_FPU_EMULATOR is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_O32_FP64_SUPPORT is not set +# CONFIG_MIPS_PARAVIRT is not set +# CONFIG_MIPS_PLATFORM_DEVICES is not set +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_MIPS_SIM is not set +CONFIG_MISC_DEVICES=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_MISDN is not set +# CONFIG_MISDN_AVMFRITZ is not set +# CONFIG_MISDN_HFCPCI is not set +# CONFIG_MISDN_HFCUSB is not set +# CONFIG_MISDN_INFINEON is not set +# CONFIG_MISDN_NETJET is not set +# CONFIG_MISDN_SPEEDFAX is not set +# CONFIG_MISDN_W6692 is not set +# CONFIG_MKISS is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MMC is not set +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_AU1X is not set +# CONFIG_MMC_BLOCK is not set +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_MVSDIO is not set +# CONFIG_MMC_S3C is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_ACPI is not set +# CONFIG_MMC_SDHCI_BCM_KONA is not set +# CONFIG_MMC_SDHCI_IPROC is not set +# CONFIG_MMC_SDHCI_MSM is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ESDHC is not set +# CONFIG_MMC_SDHCI_OF_HLWD is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDRICOH_CS is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMIOTRACE is not set +CONFIG_MMU=y +CONFIG_MODULES=y +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULE_STRIPPED=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_INPORT is not set +# CONFIG_MOUSE_LOGIBM is not set +# CONFIG_MOUSE_PC110PAD is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_MPL115 is not set +# CONFIG_MPL3115 is not set +# CONFIG_MPLS is not set +# CONFIG_MS5611 is not set +# CONFIG_MSDOS_FS is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_MSI_LAPTOP is not set +CONFIG_MTD=y +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_BLOCK2MTD is not set +CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_CHAR=y +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LATCH_ADDR is not set +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +# CONFIG_MTD_M25P80 is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_MYLOADER_PARTS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_NAND_AMS_DELTA is not set +# CONFIG_MTD_NAND_AR934X is not set +# CONFIG_MTD_NAND_AR934X_HW_ECC is not set +# CONFIG_MTD_NAND_ATMEL is not set +# CONFIG_MTD_NAND_AU1550 is not set +# CONFIG_MTD_NAND_AUTCPU12 is not set +# CONFIG_MTD_NAND_BCH is not set +# CONFIG_MTD_NAND_BCM_UMI is not set +# CONFIG_MTD_NAND_BF5XX is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_CM_X270 is not set +# CONFIG_MTD_NAND_CS553X is not set +# CONFIG_MTD_NAND_DAVINCI is not set +# CONFIG_MTD_NAND_DENALI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018 +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_ECC is not set +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_NAND_FSL_IFC is not set +# CONFIG_MTD_NAND_FSL_UPM is not set +# CONFIG_MTD_NAND_FSMC is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_GPMI_NAND is not set +# CONFIG_MTD_NAND_H1900 is not set +# CONFIG_MTD_NAND_HISI504 is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_JZ4740 is not set +# CONFIG_MTD_NAND_MPC5121_NFC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_MXC is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_NOMADIK is not set +# CONFIG_MTD_NAND_NUC900 is not set +# CONFIG_MTD_NAND_OMAP2 is not set +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set +# CONFIG_MTD_NAND_ORION is not set +# CONFIG_MTD_NAND_PASEMI is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_NAND_PPCHAMELEONEVB is not set +# CONFIG_MTD_NAND_PXA3xx is not set +# CONFIG_MTD_NAND_RB4XX is not set +# CONFIG_MTD_NAND_RB750 is not set +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_RTC_FROM4 is not set +# CONFIG_MTD_NAND_S3C2410 is not set +# CONFIG_MTD_NAND_SHARPSL is not set +# CONFIG_MTD_NAND_SH_FLCTL is not set +# CONFIG_MTD_NAND_SOCRATES is not set +# CONFIG_MTD_NAND_SPIA is not set +# CONFIG_MTD_NAND_TMIO is not set +# CONFIG_MTD_NAND_TXX9NDFMC is not set +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_PCMCIA is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_ROM is not set +CONFIG_MTD_ROOTFS_ROOT_DEV=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SPI_NOR is not set +# CONFIG_MTD_SPINAND_MT29F is not set +CONFIG_MTD_SPLIT=y +# CONFIG_MTD_SPLIT_FIRMWARE is not set +CONFIG_MTD_SPLIT_FIRMWARE_NAME="firmware" +# CONFIG_MTD_SPLIT_FIT_FW is not set +# CONFIG_MTD_SPLIT_LZMA_FW is not set +# CONFIG_MTD_SPLIT_SEAMA_FW is not set +CONFIG_MTD_SPLIT_SQUASHFS_ROOT=y +CONFIG_MTD_SPLIT_SUPPORT=y +# CONFIG_MTD_SPLIT_TRX_FW is not set +# CONFIG_MTD_SPLIT_TPLINK_FW is not set +# CONFIG_MTD_SPLIT_UIMAGE_FW is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_UBI is not set +# CONFIG_MTD_UIMAGE_SPLIT is not set +CONFIG_MULTIUSER=y +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_MVMDIO is not set +# CONFIG_MVSW61XX_PHY is not set +# CONFIG_MVSW6171_PHY is not set +# CONFIG_MVSWITCH_PHY is not set +# CONFIG_MWAVE is not set +# CONFIG_MWL8K is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NATSEMI is not set +# CONFIG_NAU7802 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_NCP_FS is not set +# CONFIG_NE2000 is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NEC_MARKEINS is not set +CONFIG_NET=y +# CONFIG_NETCONSOLE is not set +CONFIG_NETDEVICES=y +CONFIG_NETDEV_1000=y +# CONFIG_NETDEV_10000 is not set +# CONFIG_NETFILTER is not set +# CONFIG_NETFILTER_ADVANCED is not set +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_QUEUE_CT is not set +# CONFIG_NETFILTER_TPROXY is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LAYER7 is not set +# CONFIG_NETFILTER_XT_MATCH_LAYER7_DEBUG is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NETROM is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NET_9P is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_VLAN is not set +CONFIG_NET_CADENCE=y +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_ACT is not set +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_IND=y +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_U32 is not set +CONFIG_NET_CORE=y +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_NET_DSA is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6171 is not set +# CONFIG_NET_DSA_MV88E6352 is not set +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_NBYTE is not set +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_TEXT is not set +# CONFIG_NET_EMATCH_U32 is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_FC is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_NET_IPGRE is not set +CONFIG_NET_IPGRE_BROADCAST=y +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_IP_TUNNEL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_KEY is not set +# CONFIG_NET_KEY_MIGRATE is not set +# CONFIG_NET_MPLS_GSO is not set +# CONFIG_NET_PACKET_ENGINE is not set +CONFIG_NET_PCI=y +# CONFIG_NET_PCMCIA is not set +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_POCKET is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_NET_PTP_CLASSIFY is not set +CONFIG_NET_RX_BUSY_POLL=y +# CONFIG_NET_SB1000 is not set +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_ATM is not set +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_ESFQ is not set +CONFIG_NET_SCH_ESFQ_NFCT=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_NET_SCH_FQ is not set +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCTPPROBE is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_TEAM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_NET_UDP_TUNNEL is not set +CONFIG_NET_VENDOR_3COM=y +CONFIG_NET_VENDOR_8390=y +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_NET_VENDOR_AGERE=y +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CIRRUS=y +CONFIG_NET_VENDOR_CISCO=y +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_VENDOR_DLINK=y +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_NET_VENDOR_EXAR=y +CONFIG_NET_VENDOR_FARADAY=y +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HP=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_IBM=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_MICREL=y +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_NET_VENDOR_OKI=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_NET_VENDOR_RDC=y +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_NET_VENDOR_SILICOM=y +CONFIG_NET_VENDOR_SIS=y +CONFIG_NET_VENDOR_SMSC=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_NET_VENDOR_SUN=y +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_NET_VENDOR_TI=y +CONFIG_NET_VENDOR_TOSHIBA=y +CONFIG_NET_VENDOR_VIA=y +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_XILINX=y +CONFIG_NET_VENDOR_XIRCOM=y +# CONFIG_NET_XGENE is not set +CONFIG_NEW_LEDS=y +# CONFIG_NFC is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_DEPRECATED is not set +# CONFIG_NFSD_V2_ACL is not set +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +# CONFIG_NFS_ACL_SUPPORT is not set +CONFIG_NFS_COMMON=y +# CONFIG_NFS_FS is not set +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_V4_1 is not set +# CONFIG_NFTL is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IPV4 is not set +# CONFIG_NF_CONNTRACK_IPV6 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set +# CONFIG_NF_CONNTRACK_RTSP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_GRE is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +# CONFIG_NF_NAT is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_FTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_IPV6 is not set +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set +# CONFIG_NF_NAT_MASQUERADE_IPV6 is not set +# CONFIG_NF_NAT_NEEDED is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_PROTO_GRE is not set +# CONFIG_NF_NAT_RTSP is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_REJECT_IPV4 is not set +# CONFIG_NF_TABLES is not set +# CONFIG_NI52 is not set +# CONFIG_NI65 is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NIU is not set +CONFIG_NLATTR=y +# CONFIG_NLMON is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLS is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NORTEL_HERMES is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_NOZOMI is not set +# CONFIG_NO_BOOTMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_NS83820 is not set +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_NTP_PPS is not set +# CONFIG_NVRAM is not set +# CONFIG_NV_TCO is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_N_GSM is not set +# CONFIG_OABI_COMPAT is not set +# CONFIG_OBS600 is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_OCF_BENCH is not set +# CONFIG_OCF_C7108 is not set +# CONFIG_OCF_CRYPTOCTEON is not set +# CONFIG_OCF_EP80579 is not set +# CONFIG_OCF_HIFN is not set +# CONFIG_OCF_HIFNHIPP is not set +# CONFIG_OCF_IXP4XX is not set +# CONFIG_OCF_KIRKWOOD is not set +# CONFIG_OCF_OCF is not set +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_SAFE is not set +# CONFIG_OCF_TALITOS is not set +# CONFIG_OCF_UBSEC_SSB is not set +# CONFIG_OC_ETM is not set +# CONFIG_OF_OVERLAY is not set +# CONFIG_OF_SELFTEST is not set +# CONFIG_OF_UNITTEST is not set +# CONFIG_OMAP2_DSS_DEBUG is not set +# CONFIG_OMAP2_DSS_DEBUGFS is not set +# CONFIG_OMAP2_DSS_SDI is not set +# CONFIG_OMAP_CONTROL_USB is not set +# CONFIG_OMAP_OCP2SCP is not set +# CONFIG_OMAP_USB2 is not set +# CONFIG_OMAP_USB3 is not set +# CONFIG_OMFS_FS is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_OPROFILE is not set +# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set +# CONFIG_ORION_WATCHDOG is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_OVERLAY_FS=y +# CONFIG_P54_COMMON is not set +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PANEL is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PANTHERLORD_FF is not set +# CONFIG_PARPORT is not set +# CONFIG_PARPORT_1284 is not set +# CONFIG_PARPORT_AX88796 is not set +# CONFIG_PARPORT_PC is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARASAN_CF is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CS5535 is not set +# CONFIG_PATA_CS5536 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_ISAPNP is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OCTEON_CF is not set +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PCMCIA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_QDI is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_WINBOND_VLB is not set +# CONFIG_PC300TOO is not set +# CONFIG_PCCARD is not set +# CONFIG_PCH_GBE is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_PCI200SYN is not set +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIEASPM is not set +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_PCI_ATMEL is not set +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set +# CONFIG_PCI_HERMES is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_LAYERSCAPE is not set +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_PCI_PRI is not set +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +CONFIG_PCI_SYSCALL=y +# CONFIG_PCMCIA is not set +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_3C589 is not set +# CONFIG_PCMCIA_AHA152X is not set +# CONFIG_PCMCIA_ATMEL is not set +# CONFIG_PCMCIA_AXNET is not set +# CONFIG_PCMCIA_DEBUG is not set +# CONFIG_PCMCIA_FDOMAIN is not set +# CONFIG_PCMCIA_FMVJ18X is not set +# CONFIG_PCMCIA_HERMES is not set +# CONFIG_PCMCIA_LOAD_CIS is not set +# CONFIG_PCMCIA_NINJA_SCSI is not set +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_PCNET is not set +# CONFIG_PCMCIA_QLOGIC is not set +# CONFIG_PCMCIA_RAYCS is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_SPECTRUM is not set +# CONFIG_PCMCIA_SYM53C500 is not set +# CONFIG_PCMCIA_WL3501 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_XIRCOM is not set +# CONFIG_PCNET32 is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_PD6729 is not set +# CONFIG_PDA_POWER is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_PHANTOM is not set +# CONFIG_PHONE is not set +# CONFIG_PHONET is not set +# CONFIG_PHYLIB is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_PHY_EXYNOS_DP_VIDEO is not set +# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHY_QCOM_DWC3 is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_PID_NS is not set +CONFIG_PINCONF=y +# CONFIG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_CAPRI is not set +# CONFIG_PINCTRL_EXYNOS is not set +# CONFIG_PINCTRL_EXYNOS5440 is not set +# CONFIG_PINCTRL_MSM8X74 is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINMUX=y +# CONFIG_PL320_MBOX is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_PLIP is not set +# CONFIG_PLX_HERMES is not set +# CONFIG_PM is not set +# CONFIG_PMBUS is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_PM_RUNTIME is not set +# CONFIG_PM_WAKELOCKS is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_POHMELFS is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_POWERCAP is not set +# CONFIG_POWERTV is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_RESET_VERSATILE is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_DISABLE_WERROR is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_PPC_EPAPR_HV_BYTECHAN is not set +# CONFIG_PPP is not set +# CONFIG_PPPOATM is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +CONFIG_PPP_FILTER=y +# CONFIG_PPP_MPPE is not set +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPS is not set +# CONFIG_PPS_CLIENT_GPIO is not set +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_DEBUG is not set +# CONFIG_PPTP is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_PRINTK=y +# CONFIG_PRINTK_TIME is not set +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_PRISM2_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_PROBE_INITRD_HEADER is not set +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_PROC_STRIPPED=y +CONFIG_PROC_SYSCTL=y +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILING is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_PROVE_RCU is not set +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_PROVE_RCU_REPEATEDLY is not set +# CONFIG_PSB6970_PHY is not set +# CONFIG_PSTORE is not set +# CONFIG_PTP_1588_CLOCK is not set +# CONFIG_PTP_1588_CLOCK_IXP46X is not set +# CONFIG_PTP_1588_CLOCK_PCH is not set +# CONFIG_PWM is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_QCA7000 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_QORIQ_CPUFREQ is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_R3964 is not set +# CONFIG_R6040 is not set +# CONFIG_R8169 is not set +# CONFIG_R8187SE is not set +# CONFIG_R8188EU is not set +# CONFIG_R8712U is not set +# CONFIG_R8723AU is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_RADIO_AZTECH is not set +# CONFIG_RADIO_CADET is not set +# CONFIG_RADIO_GEMTEK is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_RTRACK is not set +# CONFIG_RADIO_RTRACK2 is not set +# CONFIG_RADIO_SF16FMI is not set +# CONFIG_RADIO_SF16FMR2 is not set +# CONFIG_RADIO_TERRATEC is not set +# CONFIG_RADIO_TRUST is not set +# CONFIG_RADIO_TYPHOON is not set +# CONFIG_RADIO_ZOLTRIX is not set +# CONFIG_RAID_ATTRS is not set +# CONFIG_RALINK is not set +# CONFIG_RAMOOPS is not set +# CONFIG_RANDOM32_SELFTEST is not set +# CONFIG_RAPIDIO is not set +# CONFIG_RAR_REGISTER is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EXPEDITE_BOOT is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FAST_NO_HZ is not set +CONFIG_RCU_KTHREAD_PRIO=0 +# CONFIG_RCU_NOCB_CPU is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_TORTURE_TEST_SLOW_INIT_DELAY=3 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_USER_QS is not set +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_RC_CORE is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_LOOPBACK is not set +# CONFIG_RC_MAP is not set +# CONFIG_RDS is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_XZ is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_REDWOOD is not set +# CONFIG_REGMAP is not set +# CONFIG_REGMAP_I2C is not set +# CONFIG_REGMAP_MMIO is not set +# CONFIG_REGMAP_SPI is not set +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ANATOP is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_TI_ABB is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_FS_POSIX_ACL is not set +# CONFIG_REISERFS_FS_SECURITY is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_RELAY is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_RFD_FTL is not set +# CONFIG_RFKILL is not set +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_ROCKER is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_ROSE is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RT2X00 is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_RTC_DEBUG is not set +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_ARMADA38X is not set +# CONFIG_RTC_DRV_AU1XXX is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_BQ4802 is not set +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_EP93XX is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_GENERIC is not set +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12057 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_MOXART is not set +# CONFIG_RTC_DRV_MPC5121 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_OMAP is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_PS3 is not set +# CONFIG_RTC_DRV_PT7C4338 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_RTC7301 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_SUN6I is not set +# CONFIG_RTC_DRV_TEST is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_XGENE is not set +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_SYSTOHC=y +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_RTL8192E is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTL8306_PHY is not set +# CONFIG_RTL8366RB_PHY is not set +# CONFIG_RTL8366S_PHY is not set +# CONFIG_RTL8366_SMI is not set +# CONFIG_RTL8366_SMI_DEBUG_FS is not set +# CONFIG_RTL8367B_PHY is not set +# CONFIG_RTL8367_PHY is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_RTS5139 is not set +# CONFIG_RTS5208 is not set +# CONFIG_RTS_PSTOR is not set +CONFIG_RT_MUTEXES=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_RUNTIME_DEBUG is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_S2IO is not set +# CONFIG_SAMPLES is not set +# CONFIG_SAMSUNG_LAPTOP is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_FSL is not set +# CONFIG_SATA_HIGHBANK is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_SATA_PMP is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_RCAR is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SBC_FITPC2_WATCHDOG is not set +# CONFIG_SBE_2T3E3 is not set +# CONFIG_SBYPASS is not set +# CONFIG_SC92031 is not set +# CONFIG_SCA3000 is not set +# CONFIG_SCC is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHED_MC is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y +# CONFIG_SCHED_SMT is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_7000FASST is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_AHA152X is not set +# CONFIG_SCSI_AHA1542 is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_DTC3280 is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_GENERIC_NCR5380 is not set +# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_IN2000 is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_ISCI is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_LPFC is not set +CONFIG_SCSI_MOD=y +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVSAS_DEBUG is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_NCR53C406A is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_SCSI_PAS16 is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PROC_FS=y +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLOGIC_FAS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_T128 is not set +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_ULTRASTOR is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCx200_ACB is not set +# CONFIG_SDIO_UART is not set +# CONFIG_SECCOMP is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SEEQ8005 is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_ACPI_POWER is not set +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATK0110 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_GSC is not set +# CONFIG_SENSORS_HDAPS is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HMC5843 is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_K10TEMP is not set +# CONFIG_SENSORS_K8TEMP is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VIA_CPUTEMP is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_ACCENT is not set +# CONFIG_SERIAL_8250_BOCA is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DMA=y +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_EM is not set +# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_8250_FOURPORT is not set +# CONFIG_SERIAL_8250_HUB6 is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_NR_UARTS=2 +# CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_SYSRQ is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_SERIAL_OF_PLATFORM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SH_SCI is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIO is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_SUN4I_PS2 is not set +# CONFIG_SFC is not set +# CONFIG_SFI is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_SHMEM=y +# CONFIG_SH_ETH is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIGMA is not set +CONFIG_SIGNALFD=y +# CONFIG_SIMPLE_GPIO is not set +# CONFIG_SIS190 is not set +# CONFIG_SIS900 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SKY2_DEBUG is not set +CONFIG_SLAB=y +CONFIG_SLABINFO=y +# CONFIG_SLHC is not set +# CONFIG_SLICOSS is not set +# CONFIG_SLIP is not set +# CONFIG_SLOB is not set +# CONFIG_SLUB is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SMARTJOYPLUS_FF is not set +# CONFIG_SMC911X is not set +# CONFIG_SMC9194 is not set +# CONFIG_SMC91X is not set +# CONFIG_SMP is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_SM_FTL is not set +# CONFIG_SND is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +# CONFIG_SND_AD1816A is not set +# CONFIG_SND_AD1848 is not set +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ADLIB is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_ALS100 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALS4000 is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_ASIHPI is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_ATMEL_AC97C is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT2320 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMI8330 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4231 is not set +# CONFIG_SND_CS4236 is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5530 is not set +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1688 is not set +# CONFIG_SND_ES18XX is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FIREWIRE is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_GUSCLASSIC is not set +# CONFIG_SND_GUSEXTREME is not set +# CONFIG_SND_GUSMAX is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_HWDEP is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_INTERWAVE is not set +# CONFIG_SND_INTERWAVE_STB is not set +# CONFIG_SND_ISA is not set +# CONFIG_SND_KIRKWOOD_SOC is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_MIRO is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MPC52xx_SOC_EFIKA is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_MTS64 is not set +# CONFIG_SND_MXS_SOC is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_OPL3SA2 is not set +# CONFIG_SND_OPTI92X_AD1848 is not set +# CONFIG_SND_OPTI92X_CS4231 is not set +# CONFIG_SND_OPTI93X is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_OXYGEN is not set +CONFIG_SND_PCI=y +# CONFIG_SND_PCM is not set +# CONFIG_SND_PCMCIA is not set +# CONFIG_SND_PCM_OSS is not set +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_PDAUDIOCF is not set +# CONFIG_SND_PORTMAN2X4 is not set +# CONFIG_SND_POWERPC_SOC is not set +# CONFIG_SND_PPC is not set +# CONFIG_SND_RAWMIDI is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_RTCTIMER is not set +# CONFIG_SND_SB16 is not set +# CONFIG_SND_SB8 is not set +# CONFIG_SND_SBAWE is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SND_SIS7019 is not set +# CONFIG_SND_SOC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AU1XAUDIO is not set +# CONFIG_SND_SOC_AU1XPSC is not set +# CONFIG_SND_SOC_CACHE_LZO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SND is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_ES8328 is not set +# CONFIG_SND_SOC_EUKREA_TLV320 is not set +# CONFIG_SND_SOC_FSL_ASOC_CARD is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_HDMI_CODEC is not set +# CONFIG_SND_SOC_IMX_ES8328 is not set +# CONFIG_SND_SOC_IMX_SPDIF is not set +# CONFIG_SND_SOC_IMX_WM8962 is not set +# CONFIG_SND_SOC_INTEL_SST is not set +# CONFIG_SND_SOC_MPC5200_AC97 is not set +# CONFIG_SND_SOC_MPC5200_I2S is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1792A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_QCOM is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_SSCAPE is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_TIMER is not set +# CONFIG_SND_TRIDENT is not set +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_US122L is not set +# CONFIG_SND_USB_USX2Y is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_WAVEFRONT is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SNI_RM is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_SOC_DRA7XX is not set +# CONFIG_SOC_HAS_OMAP2_SDRC is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_TI is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_SOLO6X10 is not set +# CONFIG_SONYPI is not set +# CONFIG_SONY_LAPTOP is not set +# CONFIG_SOUND is not set +# CONFIG_SOUND_PRIME is not set +# CONFIG_SP5100_TCO is not set +# CONFIG_SPARSEMEM_MANUAL is not set +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +# CONFIG_SPARSE_IRQ is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_SPEAKUP is not set +# CONFIG_SPI is not set +# CONFIG_SPINLOCK_TEST is not set +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AU1550 is not set +# CONFIG_SPI_BCM2835 is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_BUTTERFLY is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_FSL_ESPI is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_GPIO_OLD is not set +# CONFIG_SPI_IMG_SPFI is not set +# CONFIG_SPI_LM70_LLP is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_SPI_MPC52xx is not set +# CONFIG_SPI_MPC52xx_PSC is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_OCTEON is not set +# CONFIG_SPI_ORION is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PPC4xx is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_RAMIPS is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TI_QSPI is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_XWAY is not set +# CONFIG_SPMI is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XATTR is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SRAM is not set +# CONFIG_SSB is not set +# CONFIG_SSBI is not set +# CONFIG_SSB_DEBUG is not set +# CONFIG_SSB_DRIVER_GPIO is not set +# CONFIG_SSB_PCMCIAHOST is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSFDC is not set +CONFIG_STACKTRACE_SUPPORT=y +# CONFIG_STACKTRACE is not set +# CONFIG_STACK_TRACER is not set +CONFIG_STAGING=y +# CONFIG_STAGING_MEDIA is not set +CONFIG_STANDALONE=y +CONFIG_STDBINUTILS=y +# CONFIG_STE10XP is not set +# CONFIG_STE_MODEM_RPROC is not set +# CONFIG_STMMAC_ETH is not set +# CONFIG_STMMAC_PLATFORM is not set +# CONFIG_STMMAC_PCI is not set +CONFIG_STP=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_STUB_POULSBO is not set +# CONFIG_SUNDANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_SUNRPC is not set +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SUSPEND is not set +CONFIG_SWAP=y +# CONFIG_SWCONFIG is not set +# CONFIG_SWCONFIG_LEDS is not set +# CONFIG_SX9500 is not set +# CONFIG_SXGBE_ETH is not set +# CONFIG_SYNCLINK_CS is not set +CONFIG_SYN_COOKIES=y +CONFIG_SYSCTL=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_SYSFS=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_SYSV_FS is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_T5403 is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_TASKS_RCU is not set +# CONFIG_TC35815 is not set +# CONFIG_TCG_TPM is not set +# CONFIG_TCIC is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_MD5SIG is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_TEGRA_AHB is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_TEHUTI is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_MODULE is not set +# CONFIG_TEST_POWER is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_USER_COPY is not set +CONFIG_TEXTSEARCH=y +# CONFIG_TEXTSEARCH_BM is not set +# CONFIG_TEXTSEARCH_FSM is not set +# CONFIG_TEXTSEARCH_KMP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_THINKPAD_ACPI is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_THUNDERBOLT is not set +# CONFIG_TICK_CPU_ACCOUNTING is not set +CONFIG_TICK_ONESHOT=y +# CONFIG_TIFM_CORE is not set +# CONFIG_TIGON3 is not set +# CONFIG_TIMB_DMA is not set +CONFIG_TIMERFD=y +# CONFIG_TIMER_STATS is not set +CONFIG_TINY_RCU=y +# CONFIG_TIPC is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_AM335X_ADC is not set +# CONFIG_TI_CPSW is not set +# CONFIG_TI_CPSW_ALE is not set +# CONFIG_TI_CPTS is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_TI_DAVINCI_CPDMA is not set +# CONFIG_TI_DAVINCI_MDIO is not set +# CONFIG_TI_ST is not set +# CONFIG_TLAN is not set +# CONFIG_TMD_HERMES is not set +# CONFIG_TMP006 is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +CONFIG_TMPFS_XATTR=y +# CONFIG_TOPSTAR_LAPTOP is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_TOSHIBA_HAPS is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_S3C2410 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TR is not set +# CONFIG_TRACE_ENUM_MAP_FILE is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_TRACER_SNAPSHOT is not set +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_TRACE_ENUM_MAP_FILE is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_TRACE_SINK is not set +CONFIG_TRACING_SUPPORT=y +CONFIG_TRAD_SIGNALS=y +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_TRANZPORT is not set +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TREE_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set +# CONFIG_TSL4531 is not set +CONFIG_TTY=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_TUN is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6030_GPADC is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_TYPHOON is not set +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_UDF_FS is not set +CONFIG_UDF_NLS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_UFS_FS is not set +# CONFIG_UHID is not set +CONFIG_UIDGID_STRICT_TYPE_CHECKS=y +# CONFIG_UIO is not set +# CONFIG_ULTRA is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_UNIX_DIAG is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_UPROBE_EVENT is not set +# CONFIG_UPROBES is not set +# CONFIG_USB is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_ADUTUX is not set +CONFIG_USB_ALI_M5632=y +# CONFIG_USB_AMD5536UDC is not set +CONFIG_USB_AN2720=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_ATM is not set +# CONFIG_USB_BDC_UDC is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_BTMTK is not set +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_CONFIGFS is not set +# CONFIG_USB_CXACRU is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_DEBUG is not set +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_DWC2_DUAL_ROLE is not set +# CONFIG_USB_DWC2_HOST is not set +# CONFIG_USB_DWC2_PERIPHERAL is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC3_EXYNOS is not set +# CONFIG_USB_DWC3_QCOM is not set +# CONFIG_USB_DWC3_PCI is not set +# CONFIG_USB_DWC3_KEYSTONE is not set +# CONFIG_USB_DWC_OTG_LPM is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_EHCI_HCD_AT91 is not set +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_EHCI_MSM is not set +# CONFIG_USB_EHCI_MV is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_ET61X251 is not set +CONFIG_USB_EZUSB=y +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_FSL_USB2 is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_VBUS_DRAW=2 +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STK1135 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_HID is not set +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_INPUT_IMS_PCU is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_ISP1760 is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_KBD is not set +# CONFIG_USB_KC2190 is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LIBUSUAL is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_M5602 is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_MSM_OTG is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_NET_AX88179_178A is not set +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_CDC_NCM is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_OHCI_HCD_PCI is not set +# CONFIG_USB_OHCI_HCD_PPC_OF is not set +# CONFIG_USB_OHCI_HCD_PPC_OF_BE is not set +# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set +# CONFIG_USB_OHCI_HCD_PPC_SOC is not set +# CONFIG_USB_OHCI_HCD_SSB is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_FSM is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_PHY is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_PWC_INPUT_EVDEV is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RCAR_PHY is not set +# CONFIG_USB_RENESAS_USBHS is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_S2255 is not set +# CONFIG_USB_S3C_HSOTG is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_DEBUG is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_GARMIN is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +CONFIG_USB_SERIAL_KEYSPAN_MPR=y +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +CONFIG_USB_SERIAL_KEYSPAN_USA18X=y +CONFIG_USB_SERIAL_KEYSPAN_USA19=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y +CONFIG_USB_SERIAL_KEYSPAN_USA19W=y +CONFIG_USB_SERIAL_KEYSPAN_USA28=y +CONFIG_USB_SERIAL_KEYSPAN_USA28X=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +CONFIG_USB_SERIAL_KEYSPAN_USA49W=y +CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_SERIAL_QUATECH_USB2 is not set +# CONFIG_USB_SERIAL_SAFE is not set +CONFIG_USB_SERIAL_SAFE_PADDED=y +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_ZTE is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_SPEEDTOUCH is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_TMC is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_UEAGLEATM is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_USS720 is not set +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +# CONFIG_USB_VL600 is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_XUSBATM is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USELIB is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_USE_OF is not set +# CONFIG_UTS_NS is not set +# CONFIG_UWB is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VDSO is not set +# CONFIG_VETH is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_VF610_ADC is not set +# CONFIG_VFAT_FS is not set +# CONFIG_VGASTATE is not set +# CONFIG_VGA_ARB is not set +# CONFIG_VGA_SWITCHEROO is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT848 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_BWQCAM is not set +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_CAPTURE_DRIVERS is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CQCAM is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_CX2341X is not set +# CONFIG_VIDEO_CX25840 is not set +# CONFIG_VIDEO_CX88 is not set +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_DM6446_CCDC is not set +# CONFIG_VIDEO_DT3155 is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +# CONFIG_VIDEO_HEXIUM_GEMINI is not set +# CONFIG_VIDEO_HEXIUM_ORION is not set +# CONFIG_VIDEO_IR_I2C is not set +# CONFIG_VIDEO_IVTV is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_MEDIA is not set +# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MXB is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_OMAP2_VOUT is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_SAA6588 is not set +# CONFIG_VIDEO_SAA6752HS is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7134 is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TM6000 is not set +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_USBTV is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_VIDEO_V4L2 is not set +# CONFIG_VIDEO_V4L2_COMMON is not set +# CONFIG_VIDEO_V4L2_INT_DEVICE is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_INPUT is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTUALIZATION is not set +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRT_TO_BUS=y +# CONFIG_VITESSE_PHY is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_VME_BUS is not set +# CONFIG_VMSPLIT_1G is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_2G_OPT is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMWARE_PVSCSI is not set +# CONFIG_VMXNET3 is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_VORTEX is not set +# CONFIG_VSOCKETS is not set +# CONFIG_VT is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_VXFS_FS is not set +# CONFIG_VXGE is not set +# CONFIG_VXLAN is not set +# CONFIG_W1 is not set +# CONFIG_W1_CON is not set +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_GPIO is not set +# CONFIG_W1_MASTER_MATROX is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +# CONFIG_W1_SLAVE_DS2406 is not set +# CONFIG_W1_SLAVE_DS2408 is not set +# CONFIG_W1_SLAVE_DS2413 is not set +# CONFIG_W1_SLAVE_DS2423 is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_DS2780 is not set +# CONFIG_W1_SLAVE_DS2781 is not set +# CONFIG_W1_SLAVE_DS28E04 is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W35UND is not set +# CONFIG_W83627HF_WDT is not set +# CONFIG_W83697HF_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_W83977F_WDT is not set +# CONFIG_WAN is not set +# CONFIG_WANXL is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WD80x3 is not set +# CONFIG_WDTPCI is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PRIV=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WILINK_PLATFORM_DATA=y +# CONFIG_WIMAX is not set +# CONFIG_WIMAX_GDM72XX is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +# CONFIG_WIRELESS_EXT_SYSFS is not set +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLAGS49_H2 is not set +# CONFIG_WLAGS49_H25 is not set +CONFIG_WLAN=y +# CONFIG_WLCORE is not set +CONFIG_WL_TI=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_WR_PPMC is not set +# CONFIG_X25 is not set +# CONFIG_X86_DEBUG_STATIC_CPU_HAS is not set +# CONFIG_X86_PKG_TEMP_THERMAL is not set +CONFIG_X86_SYSFB=y +# CONFIG_XEN is not set +CONFIG_XFRM=y +# CONFIG_XFRM_IPCOMP is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_USER is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_XFS_FS is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_EMACLITE is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_XMON is not set +# CONFIG_XVMALLOC is not set +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_BCJ is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_TEST is not set +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_YAM is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_YENTA is not set +# CONFIG_YENTA_O2 is not set +# CONFIG_YENTA_RICOH is not set +# CONFIG_YENTA_TI is not set +# CONFIG_YENTA_TOSHIBA is not set +# CONFIG_ZBUD is not set +# CONFIG_ZD1211RW is not set +# CONFIG_ZD1211RW_DEBUG is not set +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_ZISOFS is not set +# CONFIG_ZLIB_DEFLATE is not set +# CONFIG_ZLIB_INFLATE is not set +# CONFIG_ZNET is not set +# CONFIG_ZPOOL is not set +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_ZRAM is not set +# CONFIG_ZSMALLOC is not set diff --git a/target/linux/generic/config-4.3 b/target/linux/generic/config-4.3 new file mode 100644 index 0000000..f72c169 --- /dev/null +++ b/target/linux/generic/config-4.3 @@ -0,0 +1,4925 @@ +CONFIG_32BIT=y +# CONFIG_6LOWPAN is not set +# CONFIG_6PACK is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_9P_FS is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_AB8500_CORE is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_ACENIC is not set +# CONFIG_ACERHDF is not set +# CONFIG_ACORN_PARTITION is not set +# CONFIG_ACPI_APEI is not set +# CONFIG_ACPI_CUSTOM_METHOD is not set +# CONFIG_ACPI_EXTLOG is not set +# CONFIG_ACPI_HED is not set +# CONFIG_ACPI_INT3403_THERMAL is not set +# CONFIG_ACPI_POWER_METER is not set +# CONFIG_ACPI_QUICKSTART is not set +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +# CONFIG_AD5064 is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686 is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5930 is not set +# CONFIG_AD5933 is not set +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD7746 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD799X is not set +# CONFIG_AD8366 is not set +# CONFIG_AD9523 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16255 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_ADM6996_PHY is not set +# CONFIG_ADM8211 is not set +# CONFIG_ADT7316 is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_ADXRS450 is not set +CONFIG_AEABI=y +# CONFIG_AFFS_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AGP is not set +# CONFIG_AHCI_CEVA is not set +# CONFIG_AHCI_MVEBU is not set +CONFIG_AIO=y +# CONFIG_AIRO is not set +# CONFIG_AIRO_CS is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_AK09911 is not set +# CONFIG_AK8975 is not set +# CONFIG_AL3320A is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_ALIM7101_WDT is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_ALTERA_MBOX is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_ALX is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_AMD_XGBE is not set +# CONFIG_AMD_XGBE_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_AMILO_RFKILL is not set +# CONFIG_ANDROID is not set +CONFIG_ANON_INODES=y +# CONFIG_APDS9300 is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_APM8018X is not set +# CONFIG_APPLICOM is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AR5523 is not set +# CONFIG_AR7 is not set +# CONFIG_AR8216_PHY is not set +# CONFIG_AR8216_PHY_LEDS is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_EXYNOS is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +# CONFIG_ARCH_HI3xxx is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_MSM_DT is not set +# CONFIG_ARCH_MSM_NODT is not set +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_MULTI_V6 is not set +# CONFIG_ARCH_MULTI_V7 is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_NSPIRE is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2PLUS is not set +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_SHMOBILE_LEGACY is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_WM8505 is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCNET is not set +# CONFIG_ARC_EMAC is not set +# CONFIG_ARM_APPENDED_DTB is not set +# CONFIG_ARM_ARCH_TIMER is not set +# CONFIG_ARM_AT91_ETHER is not set +# CONFIG_ARM_CCI is not set +# CONFIG_ARM_CCI400_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_ARM_CRYPTO is not set +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_ARM_ERRATA_326103 is not set +# CONFIG_ARM_ERRATA_364296 is not set +# CONFIG_ARM_ERRATA_411920 is not set +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_643719 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_KERNMEM_PERMS is not set +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +# CONFIG_ARM_KPROBES_TEST is not set +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MODULE_PLTS is not set +# CONFIG_ARM_PATCH_PHYS_VIRT is not set +# CONFIG_ARM_PSCI is not set +# CONFIG_ARM_PTDUMP is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_ARM_VIRT_EXT is not set +CONFIG_ARPD=y +# CONFIG_ARTHUR is not set +# CONFIG_AS3935 is not set +# CONFIG_ASM9260_TIMER is not set +# CONFIG_ASUS_LAPTOP is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set +# CONFIG_ASYNC_RAID6_TEST is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_ATA is not set +# CONFIG_ATAGS is not set +CONFIG_ATAGS_PROC=y +# CONFIG_ATALK is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_ATA_ACPI is not set +CONFIG_ATA_BMDMA=y +# CONFIG_ATA_GENERIC is not set +# CONFIG_ATA_NONSTANDARD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_ATA_PIIX is not set +CONFIG_ATA_SFF=y +# CONFIG_ATA_VERBOSE_ERROR is not set +# CONFIG_ATH10K is not set +# CONFIG_ATH25 is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH6KL is not set +# CONFIG_ATH6K_LEGACY is not set +# CONFIG_ATH79 is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1C is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL2 is not set +# CONFIG_ATM is not set +# CONFIG_ATMEL is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ATM_AMBASSADOR is not set +# CONFIG_ATM_BR2684 is not set +CONFIG_ATM_BR2684_IPFILTER=y +# CONFIG_ATM_CLIP is not set +CONFIG_ATM_CLIP_NO_ICMP=y +# CONFIG_ATM_DRIVERS is not set +# CONFIG_ATM_DUMMY is not set +# CONFIG_ATM_ENI is not set +# CONFIG_ATM_FIRESTREAM is not set +# CONFIG_ATM_FORE200E is not set +# CONFIG_ATM_HE is not set +# CONFIG_ATM_HORIZON is not set +# CONFIG_ATM_IA is not set +# CONFIG_ATM_IDT77252 is not set +# CONFIG_ATM_LANAI is not set +# CONFIG_ATM_LANE is not set +# CONFIG_ATM_MPOA is not set +# CONFIG_ATM_NICSTAR is not set +# CONFIG_ATM_SOLOS is not set +# CONFIG_ATM_TCP is not set +# CONFIG_ATM_ZATM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ATP is not set +# CONFIG_AUDIT is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTO_ZRELADDR is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_AVERAGE is not set +# CONFIG_AX25 is not set +# CONFIG_AX25_DAMA_SLAVE is not set +# CONFIG_AX88796 is not set +# CONFIG_AXP288_ADC is not set +# CONFIG_AXP288_FUEL_GAUGE is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_B44 is not set +# CONFIG_B53 is not set +# CONFIG_B53_SPI_DRIVER is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_BACKLIGHT_LM3630 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_PANDORA is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +CONFIG_BASE_FULL=y +CONFIG_BASE_SMALL=0 +# CONFIG_BATMAN_ADV is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BAYCOM_EPP is not set +# CONFIG_BAYCOM_PAR is not set +# CONFIG_BAYCOM_SER_FDX is not set +# CONFIG_BAYCOM_SER_HDX is not set +# CONFIG_BCACHE is not set +# CONFIG_BCM3384 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_BCM63XX_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BCMA is not set +# CONFIG_BCMA_DRIVER_GPIO is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMGENET is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_BDI_SWITCH is not set +# CONFIG_BE2ISCSI is not set +# CONFIG_BE2NET is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_BGMAC is not set +# CONFIG_BH1750 is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_BIG_LITTLE is not set +# CONFIG_BINARY_PRINTF is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITREVERSE=y +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_CPQ_DA is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_ATIIXP is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_CS5535 is not set +# CONFIG_BLK_DEV_CS5536 is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_DELKIN is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_IDEACPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDECS is not set +# CONFIG_BLK_DEV_IDEPCI is not set +# CONFIG_BLK_DEV_IDEPNP is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDE_AU1XXX is not set +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_PMEM is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RZ1000 is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_SD is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SIS5513 is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SL82C105 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_TC86C001 is not set +# CONFIG_BLK_DEV_THROTTLING is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_UMC8672 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLOCK=y +# CONFIG_BMA180 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_BMC150_MAGN is not set +# CONFIG_BMG160 is not set +# CONFIG_BMIPS_GENERIC is not set +# CONFIG_BMP085 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_BMP280 is not set +# CONFIG_BNA is not set +# CONFIG_BNX2 is not set +# CONFIG_BNX2X is not set +# CONFIG_BONDING is not set +# CONFIG_BOOKE_WDT is not set +CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_BOOT_RAW=y +# CONFIG_BPCTL is not set +CONFIG_BPF=y +# CONFIG_BPF_JIT is not set +CONFIG_BPF_SYSCALL=y +# CONFIG_BPQETHER is not set +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_BRCMFMAC is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMSTB_GISB_ARB is not set +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_EBT_802_3 is not set +# CONFIG_BRIDGE_EBT_AMONG is not set +# CONFIG_BRIDGE_EBT_ARP is not set +# CONFIG_BRIDGE_EBT_ARPREPLY is not set +# CONFIG_BRIDGE_EBT_BROUTE is not set +# CONFIG_BRIDGE_EBT_DNAT is not set +# CONFIG_BRIDGE_EBT_IP is not set +# CONFIG_BRIDGE_EBT_IP6 is not set +# CONFIG_BRIDGE_EBT_LIMIT is not set +# CONFIG_BRIDGE_EBT_LOG is not set +# CONFIG_BRIDGE_EBT_MARK is not set +# CONFIG_BRIDGE_EBT_MARK_T is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_BRIDGE_EBT_PKTTYPE is not set +# CONFIG_BRIDGE_EBT_REDIRECT is not set +# CONFIG_BRIDGE_EBT_SNAT is not set +# CONFIG_BRIDGE_EBT_STP is not set +# CONFIG_BRIDGE_EBT_T_FILTER is not set +# CONFIG_BRIDGE_EBT_T_NAT is not set +# CONFIG_BRIDGE_EBT_ULOG is not set +# CONFIG_BRIDGE_EBT_VLAN is not set +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_NETFILTER is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BROADCOM_PHY is not set +CONFIG_BROKEN_ON_SMP=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_BT is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BT_ATH3K is not set +# CONFIG_BT_BNEP is not set +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +# CONFIG_BT_BREDR is not set +# CONFIG_BT_CMTP is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIBLUECARD is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBT3C is not set +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIBTUART is not set +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTUSB_RTL is not set +# CONFIG_BT_HCIDTL1 is not set +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIUART_3WIRE is not set +# CONFIG_BT_HCIUART_ATH3K is not set +# CONFIG_BT_HCIUART_QCA is not set +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_HIDP is not set +# CONFIG_BT_HS is not set +CONFIG_BT_L2CAP=y +# CONFIG_BT_LE is not set +# CONFIG_BT_MRVL is not set +# CONFIG_BT_RFCOMM is not set +# CONFIG_BUILD_BIN2C is not set +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_SCO=y +# CONFIG_BT_SELFTEST is not set +CONFIG_BUG=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +# CONFIG_C2PORT is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_CAIF is not set +# CONFIG_CAN is not set +# CONFIG_CAN_GS_USB is not set +# CONFIG_CAN_M_CAN is not set +# CONFIG_CAN_RCAR is not set +# CONFIG_CAPI_AVM is not set +# CONFIG_CAPI_EICON is not set +# CONFIG_CAPI_TRACE is not set +CONFIG_CARDBUS=y +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_CARL9170 is not set +# CONFIG_CARMA_FPGA is not set +# CONFIG_CARMA_FPGA_PROGRAM is not set +# CONFIG_CASSINI is not set +CONFIG_CAVIUM_OCTEON_HELPER=y +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_SOC is not set +# CONFIG_CB710_CORE is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_CED1401 is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_CFG80211 is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CGROUPS is not set +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_CHARGER_TWL4030 is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CIFS is not set +# CONFIG_CIFS_ACL is not set +# CONFIG_CIFS_DEBUG is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_FSCACHE is not set +# CONFIG_CIFS_NFSD_EXPORT is not set +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB2 is not set +CONFIG_CIFS_STATS=y +# CONFIG_CIFS_STATS2 is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CLEANCACHE is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_CLKSRC_VERSATILE is not set +# CONFIG_CLOCK_THERMAL is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM36651 is not set +# CONFIG_CMA is not set +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_BOOL is not set +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_CMDLINE_FROM_BOOTLOADER is not set +# CONFIG_CMDLINE_PARTITION is not set +# CONFIG_CNIC is not set +# CONFIG_CODA_FS is not set +# CONFIG_CODE_PATCHING_SELFTEST is not set +# CONFIG_COMEDI is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_DEBUG is not set +# CONFIG_COMMON_CLK_IPROC is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_QCOM is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_COMPACTION is not set +# CONFIG_COMPAL_LAPTOP is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPILE_TEST is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_CONNECTOR is not set +CONFIG_CONSTRUCTORS=y +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_COPS is not set +# CONFIG_CORDIC is not set +# CONFIG_COREDUMP is not set +# CONFIG_CORESIGHT is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_IDLE is not set +# CONFIG_CPU_IDLE_GOV_MENU is not set +# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +# CONFIG_CRAMFS is not set +CONFIG_CRASHLOG=y +# CONFIG_CRASH_DUMP is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_CRC32_BIT is not set +CONFIG_CRC32_SARWATE=y +# CONFIG_CRC32_SELFTEST is not set +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SLICEBY8 is not set +# CONFIG_CRC7 is not set +# CONFIG_CRC8 is not set +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CROSS_COMPILE="" +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_CRYPTO=y +# CONFIG_CRYPTO_AEAD is not set +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_586 is not set +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_AES_ARM_BS is not set +# CONFIG_CRYPTO_AES_NI_INTEL is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32C_INTEL is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_DEV_ATMEL_AES is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set +# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_FSL_CAAM is not set +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set +# CONFIG_CRYPTO_DEV_MV_CESA is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QCE is not set +# CONFIG_CRYPTO_DEV_SAHARA is not set +# CONFIG_CRYPTO_DEV_TALITOS is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_ECHAINIV is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_FIPS is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set +# CONFIG_CRYPTO_HASH is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_PCOMP is not set +# CONFIG_CRYPTO_PCOMP2 is not set +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_RNG is not set +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SALSA20_586 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_TWOFISH_586 is not set +# CONFIG_CRYPTO_TWOFISH_COMMON is not set +# CONFIG_CRYPTO_USER is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_XZ is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYSTALHD is not set +# CONFIG_CS5535_MFGPT is not set +# CONFIG_CS89x0 is not set +# CONFIG_CUSE is not set +# CONFIG_CW1200 is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_EEH is not set +# CONFIG_CXL_KERNEL_API is not set +# CONFIG_CXT1E1 is not set +# CONFIG_CYPRESS_FIRMWARE is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DCB is not set +# CONFIG_DDR is not set +# CONFIG_DE600 is not set +# CONFIG_DE620 is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +CONFIG_DEBUG_INFO_REDUCED=y +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +# CONFIG_DEBUG_LOCKDEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_NX_TEST is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_UART_BCM63XX is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_ZBOOT is not set +# CONFIG_DECNET is not set +CONFIG_DEFAULT_CUBIC=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_DEFAULT_NOOP is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_SECURITY="" +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +# CONFIG_DELL_SMO8800 is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_DEVKMEM is not set +# CONFIG_DEVMEM is not set +CONFIG_DEVPORT=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_DEVTMPFS is not set +# CONFIG_DEVTMPFS_MOUNT is not set +# CONFIG_DGAP is not set +# CONFIG_DGNC is not set +# CONFIG_DGRP is not set +# CONFIG_DHT11 is not set +# CONFIG_DIRECT_IO is not set +CONFIG_DISABLE_DEV_COREDUMP=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set +# CONFIG_DISPLAY_CONNECTOR_DVI is not set +# CONFIG_DISPLAY_CONNECTOR_HDMI is not set +# CONFIG_DISPLAY_ENCODER_TFP410 is not set +# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set +# CONFIG_DISPLAY_PANEL_DPI is not set +# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set +# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_DL2K is not set +# CONFIG_DLM is not set +# CONFIG_DM9000 is not set +# CONFIG_DMADEVICES is not set +# CONFIG_DMADEVICES_DEBUG is not set +# CONFIG_DMASCC is not set +# CONFIG_DMATEST is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_ENGINE is not set +# CONFIG_DMA_SHARED_BUFFER is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_LOG_USERSPACE is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DNET is not set +# CONFIG_DNOTIFY is not set +# CONFIG_DNS_RESOLVER is not set +CONFIG_DOUBLEFAULT=y +# CONFIG_DP83867_PHY is not set +CONFIG_DQL=y +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_DRM is not set +# CONFIG_DS1682 is not set +# CONFIG_DTLK is not set +# CONFIG_DUMMY is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DVB_DUMMY_FE is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +# CONFIG_DW_DMAC is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_DWC3_HOST_USB3_LPM_ENABLE is not set +# CONFIG_DX_SEP is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_E100 is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_E2100 is not set +# CONFIG_EARLY_PRINTK_8250 is not set +# CONFIG_EASYCAP is not set +# CONFIG_ECHO is not set +# CONFIG_ECONET is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_EDAC is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_DIGSY_MTC_CFG is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEXPRESS is not set +# CONFIG_EEXPRESS_PRO is not set +CONFIG_EFI_PARTITION=y +# CONFIG_EFS_FS is not set +# CONFIG_ELF_CORE is not set +# CONFIG_EMAC_ROCKCHIP is not set +CONFIG_EMBEDDED=y +# CONFIG_EM_TIMER_STI is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENC28J60 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_ENIC is not set +# CONFIG_EPAPR_PARAVIRT is not set +# CONFIG_EPIC100 is not set +CONFIG_EPOLL=y +# CONFIG_EQUALIZER is not set +# CONFIG_ET131X is not set +# CONFIG_GATEWORKS_GW16083 is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_GLOB_SELFTEST is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_ETH16I is not set +CONFIG_ETHERNET=y +# CONFIG_ETHOC is not set +CONFIG_EVENTFD=y +# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set +# CONFIG_EWRK3 is not set +CONFIG_EXPERIMENTAL=y +CONFIG_EXPERT=y +# CONFIG_EXPORTFS is not set +# CONFIG_EXT2_FS is not set +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_DEBUG is not set +# CONFIG_EXT4_ENCRYPTION is not set +# CONFIG_EXT4_FS is not set +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXTCON is not set +CONFIG_EXTRA_FIRMWARE="" +CONFIG_EXTRA_TARGETS="" +# CONFIG_EXYNOS_ADC is not set +# CONFIG_EXYNOS_VIDEO is not set +# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_FS is not set +# CONFIG_F2FS_FS_ENCRYPTION is not set +# CONFIG_F2FS_IO_TRACE is not set +# CONFIG_FAIR_GROUP_SCHED is not set +# CONFIG_FANOTIFY is not set +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_FS is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_FB is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_DA8XX is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GEODE is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_N411 is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_PS3 is not set +# CONFIG_FB_PXA is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM712 is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_TFT is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_XGI is not set +# CONFIG_FCOE is not set +# CONFIG_FCOE_FNIC is not set +# CONFIG_FDDI is not set +# CONFIG_FEALNX is not set +# CONFIG_FENCE_TRACE is not set +# CONFIG_FHANDLE is not set +CONFIG_FIB_RULES=y +CONFIG_FILE_LOCKING=y +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIREWIRE_SERIAL is not set +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FIXED_PHY is not set +CONFIG_FLATMEM=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_FM10K is not set +# CONFIG_FMC is not set +# CONFIG_FORCEDETH is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_FRAME_POINTER is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_FREEZER is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_FSCACHE is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_XGMAC_MDIO is not set +CONFIG_FSNOTIFY=y +# CONFIG_FS_DAX is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_FT1000 is not set +# CONFIG_FTGMAC100 is not set +# CONFIG_FTL is not set +# CONFIG_FTMAC100 is not set +# CONFIG_FTRACE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_FTR_FIXUP_SELFTEST is not set +# CONFIG_FUJITSU_TABLET is not set +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_FUSE_FS is not set +# CONFIG_FUSION is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set +# CONFIG_FUSION_SPI is not set +CONFIG_FUTEX=y +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_GACT_PROB=y +# CONFIG_GADGET_UAC1 is not set +# CONFIG_GAMEPORT is not set +# CONFIG_GCOV is not set +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GENEVE is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_GENERIC_CALIBRATE_DELAY=y +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_GENERIC_PHY is not set +CONFIG_GENERIC_TIME=y +# CONFIG_GENWQE is not set +# CONFIG_GFS2_FS is not set +# CONFIG_GIGASET_CAPI is not set +# CONFIG_GIGASET_DEBUG is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_GPIOLIB is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_BCM_KONA is not set +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_CS5535 is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_ICH is not set +# CONFIG_GPIO_IT8761E is not set +# CONFIG_GPIO_LANGWELL is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_RDC321X is not set +# CONFIG_GPIO_SCH is not set +# CONFIG_GPIO_SCH311X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_SYSFS is not set +# CONFIG_GPIO_TS5500 is not set +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_GPIO_WDT is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_ZX is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HAMACHI is not set +# CONFIG_HAMRADIO is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HCALL_STATS is not set +# CONFIG_HDLC is not set +# CONFIG_HDLC_CISCO is not set +# CONFIG_HDLC_FR is not set +# CONFIG_HDLC_PPP is not set +# CONFIG_HDLC_RAW is not set +# CONFIG_HDLC_RAW_ETH is not set +# CONFIG_HDQ_MASTER_OMAP is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_HERMES is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_HFSPLUS_FS_POSIX_ACL is not set +# CONFIG_HFS_FS is not set +# CONFIG_HIBERNATION is not set +# CONFIG_HID is not set +# CONFIG_HIDRAW is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_ACRUX_FF is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CP2112 is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_HUION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_LOGITECH_DJ is not set +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PID is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_PS3REMOTE is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_ARVO is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_ROCCAT_KONEPLUS is not set +# CONFIG_HID_ROCCAT_KOVAPLUS is not set +# CONFIG_HID_ROCCAT_PYRA is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HIGHMEM is not set +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIP04_ETH is not set +# CONFIG_HIPPI is not set +# CONFIG_HIX5HD2_GMAC is not set +# CONFIG_HMC6352 is not set +# CONFIG_HOSTAP is not set +# CONFIG_HOSTAP_CS is not set +# CONFIG_HOSTAP_PCI is not set +# CONFIG_HOSTAP_PLX is not set +CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HP100 is not set +CONFIG_HPET_MMAP_DEFAULT=y +# CONFIG_HPFS_FS is not set +# CONFIG_HPLAN is not set +# CONFIG_HPLAN_PLUS is not set +# CONFIG_HP_ILO is not set +# CONFIG_HP_WIRELESS is not set +# CONFIG_HSI is not set +# CONFIG_HSR is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_HVC_DCC is not set +# CONFIG_HVC_UDBG is not set +# CONFIG_HWMON is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_HWMON_VID is not set +# CONFIG_HWSPINLOCK_OMAP is not set +CONFIG_HW_PERF_EVENTS=y +# CONFIG_HW_RANDOM is not set +# CONFIG_HW_RANDOM_AMD is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_EXYNOS is not set +# CONFIG_HW_RANDOM_GEODE is not set +# CONFIG_HW_RANDOM_INTEL is not set +# CONFIG_HW_RANDOM_IPROC_RNG200 is not set +# CONFIG_HW_RANDOM_OMAP3_ROM is not set +# CONFIG_HW_RANDOM_PPC4XX is not set +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_VIA is not set +# CONFIG_HYPERV is not set +# CONFIG_HYSDN is not set +CONFIG_HZ=100 +CONFIG_HZ_100=y +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_48 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_PERIODIC is not set +# CONFIG_I2C is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCA is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_AU1550 is not set +# CONFIG_I2C_BCM2835 is not set +# CONFIG_I2C_BCM_IPROC is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_ELEKTOR is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_HID is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_IBM_IIC is not set +# CONFIG_I2C_IMG is not set +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +# CONFIG_I2C_MPC is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_MV64XXX is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_OCTEON is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_PCA_ISA is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RCAR is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_SCMI is not set +# CONFIG_I2C_SH_MOBILE is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_SMBUS is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set +# CONFIG_I2C_VERSATILE is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2O is not set +# CONFIG_I40E is not set +# CONFIG_I40EVF is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_I82092 is not set +# CONFIG_I82365 is not set +# CONFIG_IBM_ASM is not set +# CONFIG_IBM_EMAC_DEBUG is not set +# CONFIG_IBM_EMAC_EMAC4 is not set +# CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_EMAC_MAL_COMMON_ERR is not set +# CONFIG_IBM_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_EMAC_RGMII is not set +# CONFIG_IBM_EMAC_TAH is not set +# CONFIG_IBM_EMAC_ZMII is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_ICS932S401 is not set +# CONFIG_IDE is not set +# CONFIG_IDEAPAD_LAPTOP is not set +# CONFIG_IDE_GD is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_IDE_PROC_FS is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +# CONFIG_IDMA64 is not set +# CONFIG_IEEE802154 is not set +# CONFIG_IEEE802154_ATUSB is not set +# CONFIG_IFB is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_IIO is not set +# CONFIG_IIO_BUFFER_CB is not set +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_GPIO_TRIGGER is not set +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_IIO_SSP_SENSORHUB is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +# CONFIG_IKCONFIG is not set +# CONFIG_IKCONFIG_PROC is not set +# CONFIG_IMAGE_CMDLINE_HACK is not set +# CONFIG_IMGPDC_WDT is not set +# CONFIG_IMX_IPUV3_CORE is not set +CONFIG_INET=y +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_DIAG is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_TCP_DIAG is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INFINIBAND is not set +# CONFIG_INFTL is not set +# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set +# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set +# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set +CONFIG_INITRAMFS_COMPRESSION_NONE=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_INIT_FALLBACK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_INOTIFY_USER=y +# CONFIG_INPUT is not set +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_APANEL is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_ATLAS_BTNS is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_LEDS is not set +# CONFIG_INPUT_MATRIXKMAP is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PCSPKR is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_WISTRON_BTNS is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INT340X_THERMAL is not set +# CONFIG_INTEL_IDLE is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_INTEL_MEI_ME is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_INTEL_MIC_CARD is not set +# CONFIG_INTEL_MIC_HOST is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_INTEL_OAKTRAIL is not set +# CONFIG_INTEL_RST is not set +# CONFIG_INTEL_SMARTCONNECT is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_INV_MPU6050_IIO is not set +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_NOOP=y +# CONFIG_IP1000 is not set +# CONFIG_IP17XX_PHY is not set +# CONFIG_IP6_NF_FILTER is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP6_NF_MANGLE is not set +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_NAT is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_TARGET_LOG is not set +# CONFIG_IP6_NF_TARGET_REJECT is not set +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +# CONFIG_IPACK_BUS is not set +# CONFIG_IPC_NS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPV6 is not set +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_ROUTE_INFO is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_SIT_6RD is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_VTI is not set +# CONFIG_IPVLAN is not set +# CONFIG_IPW2100 is not set +# CONFIG_IPW2100_DEBUG is not set +CONFIG_IPW2100_MONITOR=y +# CONFIG_IPW2200 is not set +# CONFIG_IPW2200_DEBUG is not set +CONFIG_IPW2200_MONITOR=y +# CONFIG_IPW2200_PROMISCUOUS is not set +# CONFIG_IPW2200_QOS is not set +# CONFIG_IPW2200_RADIOTAP is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_IPX is not set +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_DCCP is not set +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_NF_ARPFILTER is not set +# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARP_MANGLE is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_SECURITY is not set +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_MASQUERADE is not set +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_REDIRECT is not set +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +# CONFIG_IP_PNP is not set +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_SCTP is not set +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set +# CONFIG_IRDA is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_IRQ_ALL_CPUS is not set +# CONFIG_IRQ_DOMAIN_DEBUG is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_IR_HIX5HD2 is not set +# CONFIG_IR_IGORPLUGUSB is not set +# CONFIG_IR_IGUANA is not set +# CONFIG_IR_IMG is not set +# CONFIG_IR_IMON is not set +# CONFIG_IR_JVC_DECODER is not set +# CONFIG_IR_LIRC_CODEC is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_NEC_DECODER is not set +# CONFIG_IR_RC5_DECODER is not set +# CONFIG_IR_RC5_SZ_DECODER is not set +# CONFIG_IR_RC6_DECODER is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_SONY_DECODER is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_IR_TTUSBIR is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_ISCSI_TCP is not set +CONFIG_ISDN=y +# CONFIG_ISDN_AUDIO is not set +# CONFIG_ISDN_CAPI is not set +# CONFIG_ISDN_CAPI_CAPIDRV is not set +# CONFIG_ISDN_DIVERSION is not set +# CONFIG_ISDN_DRV_ACT2000 is not set +# CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON is not set +# CONFIG_ISDN_DRV_GIGASET is not set +# CONFIG_ISDN_DRV_HISAX is not set +# CONFIG_ISDN_DRV_ICN is not set +# CONFIG_ISDN_DRV_LOOP is not set +# CONFIG_ISDN_DRV_PCBIT is not set +# CONFIG_ISDN_DRV_SC is not set +# CONFIG_ISDN_I4L is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_ISL29125 is not set +# CONFIG_ISO9660_FS is not set +# CONFIG_ISS4xx is not set +# CONFIG_ITG3200 is not set +# CONFIG_IWL3945 is not set +# CONFIG_IWLAGN is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWMC3200TOP is not set +# CONFIG_IXGB is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGBEVF is not set +# CONFIG_JBD is not set +# CONFIG_JBD2_DEBUG is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_POSIX_ACL is not set +# CONFIG_JFFS2_FS_SECURITY is not set +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_LZMA=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_ZLIB is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_JME is not set +CONFIG_JOLIET=y +# CONFIG_JSA1212 is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_KALLSYMS is not set +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_UNCOMPRESSED is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_KERNEL_MODE_NEON=y +CONFIG_KERNEL_XZ=y +CONFIG_KERNFS=y +# CONFIG_KEXEC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP1106 is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PXA27x is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_SH_KEYSC is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_KGDB is not set +# CONFIG_KMEMCHECK is not set +# CONFIG_KMX61 is not set +# CONFIG_KPROBES is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_KSM is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_KVM_GUEST is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_KXSD9 is not set +# CONFIG_L2TP is not set +# CONFIG_L2TP_ETH is not set +# CONFIG_L2TP_IP is not set +# CONFIG_L2TP_V3 is not set +# CONFIG_LANMEDIA is not set +# CONFIG_LANTIQ is not set +# CONFIG_LAPB is not set +# CONFIG_LASAT is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_LBDAF=y +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_LEDS_ATMEL_PWM is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_BLINKM is not set +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_GPIO_OF=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_INTEL_SS4200 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3556 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_NET5501 is not set +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_PCA9685 is not set +# CONFIG_LEDS_PM8941_WLED is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +# CONFIG_LEDS_TRIGGER_MORSE is not set +CONFIG_LEDS_TRIGGER_NETDEV=y +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +CONFIG_LEDS_TRIGGER_TIMER=y +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_USBDEV is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LIB80211 is not set +# CONFIG_LIB80211_CRYPT_CCMP is not set +# CONFIG_LIB80211_CRYPT_TKIP is not set +# CONFIG_LIB80211_CRYPT_WEP is not set +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_LIBERTAS_USB is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_LIBIPW_DEBUG is not set +# CONFIG_LIBNVDIMM is not set +# CONFIG_LINE6_USB is not set +# CONFIG_LIRC_STAGING is not set +# CONFIG_LIS3L02DQ is not set +# CONFIG_LKDTM is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_LOCKD is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_LOCKD_V4=y +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_LOGFS is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_LOGO is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +# CONFIG_LOONGSON_MC146818 is not set +# CONFIG_LP486E is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_LP_CONSOLE is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_LTR501 is not set +# CONFIG_LTPC is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_LWTUNNEL is not set +# CONFIG_LXT_PHY is not set +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +# CONFIG_LZ4HC_COMPRESS is not set +CONFIG_LZMA_COMPRESS=y +CONFIG_LZMA_DECOMPRESS=y +# CONFIG_LZO_COMPRESS is not set +# CONFIG_LZO_DECOMPRESS is not set +# CONFIG_M25PXX_PREFER_SMALL_SECTOR_ERASE is not set +# CONFIG_M62332 is not set +# CONFIG_MAC80211 is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MACB is not set +# CONFIG_MACH_ASM9260 is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MACH_LOONGSON1 is not set +# CONFIG_MACH_NO_WESTBRIDGE is not set +# CONFIG_MACH_PISTACHIO is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_MACINTOSH_DRIVERS is not set +# CONFIG_MACVLAN is not set +# CONFIG_MACVTAP is not set +# CONFIG_MAC_EMUMOUSEBTN is not set +# CONFIG_MAC_PARTITION is not set +# CONFIG_MAG3110 is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +# CONFIG_MAILBOX is not set +# CONFIG_MANGLE_BOOTARGS is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MCB is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_MCPM is not set +# CONFIG_MD is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_ATTACH is not set +# CONFIG_MEDIA_CAMERA_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_PARPORT_SUPPORT is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +# CONFIG_MEDIA_USB_SUPPORT is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_SAS is not set +CONFIG_MEMBARRIER=y +# CONFIG_MEMORY is not set +# CONFIG_MEMORY_FAILURE is not set +# CONFIG_MEMSTICK is not set +# CONFIG_MEMTEST is not set +# CONFIG_MEN_A21_WDT is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_CS5535 is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_OMAP_USB_HOST is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MG_DISK is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MIGRATION is not set +CONFIG_MII=y +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_MINIX_FS is not set +# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_MIPS_ALCHEMY is not set +# CONFIG_MIPS_CDMM is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MIPS_FPU_EMULATOR is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_O32_FP64_SUPPORT is not set +# CONFIG_MIPS_PARAVIRT is not set +# CONFIG_MIPS_PLATFORM_DEVICES is not set +# CONFIG_MIPS_SEAD3 is not set +# CONFIG_MIPS_SIM is not set +CONFIG_MISC_DEVICES=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_MISDN is not set +# CONFIG_MISDN_AVMFRITZ is not set +# CONFIG_MISDN_HFCPCI is not set +# CONFIG_MISDN_HFCUSB is not set +# CONFIG_MISDN_INFINEON is not set +# CONFIG_MISDN_NETJET is not set +# CONFIG_MISDN_SPEEDFAX is not set +# CONFIG_MISDN_W6692 is not set +# CONFIG_MKISS is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MLXSW_CORE is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MMC is not set +# CONFIG_MMC35240 is not set +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_AU1X is not set +# CONFIG_MMC_BLOCK is not set +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MMC_MVSDIO is not set +# CONFIG_MMC_S3C is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_ACPI is not set +# CONFIG_MMC_SDHCI_BCM_KONA is not set +# CONFIG_MMC_SDHCI_IPROC is not set +# CONFIG_MMC_SDHCI_MSM is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ESDHC is not set +# CONFIG_MMC_SDHCI_OF_HLWD is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDRICOH_CS is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_TEST is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMIOTRACE is not set +CONFIG_MMU=y +CONFIG_MODULES=y +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULE_STRIPPED=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MOST is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_INPORT is not set +# CONFIG_MOUSE_LOGIBM is not set +# CONFIG_MOUSE_PC110PAD is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_MPL115 is not set +# CONFIG_MPL3115 is not set +# CONFIG_MPLS is not set +# CONFIG_MS5611 is not set +# CONFIG_MSDOS_FS is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_MSI_BITMAP_SELFTEST is not set +# CONFIG_MSI_LAPTOP is not set +CONFIG_MTD=y +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_MTD_BLOCK2MTD is not set +CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +CONFIG_MTD_CHAR=y +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_COMPLEX_MAPPINGS=y +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_GPIO_ADDR is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LATCH_ADDR is not set +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +# CONFIG_MTD_M25P80 is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_MYLOADER_PARTS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_NAND_AMS_DELTA is not set +# CONFIG_MTD_NAND_AR934X is not set +# CONFIG_MTD_NAND_AR934X_HW_ECC is not set +# CONFIG_MTD_NAND_ATMEL is not set +# CONFIG_MTD_NAND_AU1550 is not set +# CONFIG_MTD_NAND_AUTCPU12 is not set +# CONFIG_MTD_NAND_BCH is not set +# CONFIG_MTD_NAND_BCM_UMI is not set +# CONFIG_MTD_NAND_BF5XX is not set +# CONFIG_MTD_NAND_BRCMNAND is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_CM_X270 is not set +# CONFIG_MTD_NAND_CS553X is not set +# CONFIG_MTD_NAND_DAVINCI is not set +# CONFIG_MTD_NAND_DENALI is not set +# CONFIG_MTD_NAND_DENALI_DT is not set +# CONFIG_MTD_NAND_DENALI_PCI is not set +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018 +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_ECC is not set +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_FSL_ELBC is not set +# CONFIG_MTD_NAND_FSL_IFC is not set +# CONFIG_MTD_NAND_FSL_UPM is not set +# CONFIG_MTD_NAND_FSMC is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_GPMI_NAND is not set +# CONFIG_MTD_NAND_H1900 is not set +# CONFIG_MTD_NAND_HISI504 is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_JZ4740 is not set +# CONFIG_MTD_NAND_MPC5121_NFC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_MXC is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_NDFC is not set +# CONFIG_MTD_NAND_NOMADIK is not set +# CONFIG_MTD_NAND_NUC900 is not set +# CONFIG_MTD_NAND_OMAP2 is not set +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set +# CONFIG_MTD_NAND_ORION is not set +# CONFIG_MTD_NAND_PASEMI is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_NAND_PPCHAMELEONEVB is not set +# CONFIG_MTD_NAND_PXA3xx is not set +# CONFIG_MTD_NAND_RB4XX is not set +# CONFIG_MTD_NAND_RB750 is not set +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_RTC_FROM4 is not set +# CONFIG_MTD_NAND_S3C2410 is not set +# CONFIG_MTD_NAND_SHARPSL is not set +# CONFIG_MTD_NAND_SH_FLCTL is not set +# CONFIG_MTD_NAND_SOCRATES is not set +# CONFIG_MTD_NAND_SPIA is not set +# CONFIG_MTD_NAND_TMIO is not set +# CONFIG_MTD_NAND_TXX9NDFMC is not set +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_PCMCIA is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_RAM is not set +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_ROM is not set +CONFIG_MTD_ROOTFS_ROOT_DEV=y +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SPI_NOR is not set +# CONFIG_MTD_SPINAND_MT29F is not set +CONFIG_MTD_SPLIT=y +# CONFIG_MTD_SPLIT_FIRMWARE is not set +CONFIG_MTD_SPLIT_FIRMWARE_NAME="firmware" +# CONFIG_MTD_SPLIT_FIT_FW is not set +# CONFIG_MTD_SPLIT_LZMA_FW is not set +# CONFIG_MTD_SPLIT_SEAMA_FW is not set +CONFIG_MTD_SPLIT_SQUASHFS_ROOT=y +CONFIG_MTD_SPLIT_SUPPORT=y +# CONFIG_MTD_SPLIT_TRX_FW is not set +# CONFIG_MTD_SPLIT_TPLINK_FW is not set +# CONFIG_MTD_SPLIT_UIMAGE_FW is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_UBI is not set +# CONFIG_MTD_UIMAGE_SPLIT is not set +CONFIG_MULTIUSER=y +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_MV643XX_ETH is not set +# CONFIG_MVMDIO is not set +# CONFIG_MVSW61XX_PHY is not set +# CONFIG_MVSW6171_PHY is not set +# CONFIG_MVSWITCH_PHY is not set +# CONFIG_MWAVE is not set +# CONFIG_MWL8K is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NATSEMI is not set +# CONFIG_NAU7802 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_NCP_FS is not set +# CONFIG_NE2000 is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NEC_MARKEINS is not set +CONFIG_NET=y +# CONFIG_NETCONSOLE is not set +CONFIG_NETDEVICES=y +CONFIG_NETDEV_1000=y +# CONFIG_NETDEV_10000 is not set +# CONFIG_NETFILTER is not set +# CONFIG_NETFILTER_ADVANCED is not set +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_NETFILTER_INGRESS is not set +# CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_QUEUE_CT is not set +# CONFIG_NETFILTER_TPROXY is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LAYER7 is not set +# CONFIG_NETFILTER_XT_MATCH_LAYER7_DEBUG is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETPOLL is not set +# CONFIG_NETROM is not set +CONFIG_NETWORK_FILESYSTEMS=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NET_9P is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_VLAN is not set +CONFIG_NET_CADENCE=y +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_ACT is not set +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_IND=y +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_U32 is not set +CONFIG_NET_CORE=y +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_NET_DSA is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6171 is not set +# CONFIG_NET_DSA_MV88E6352 is not set +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_NBYTE is not set +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_TEXT is not set +# CONFIG_NET_EMATCH_U32 is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_FC is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_NET_IPGRE is not set +CONFIG_NET_IPGRE_BROADCAST=y +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_IP_TUNNEL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_KEY is not set +# CONFIG_NET_KEY_MIGRATE is not set +# CONFIG_NET_MPLS_GSO is not set +# CONFIG_NET_PACKET_ENGINE is not set +CONFIG_NET_PCI=y +# CONFIG_NET_PCMCIA is not set +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_POCKET is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_NET_PTP_CLASSIFY is not set +CONFIG_NET_RX_BUSY_POLL=y +# CONFIG_NET_SB1000 is not set +CONFIG_NET_SCHED=y +# CONFIG_NET_SCH_ATM is not set +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_ESFQ is not set +CONFIG_NET_SCH_ESFQ_NFCT=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_NET_SCH_FQ is not set +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCTPPROBE is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_TEAM is not set +# CONFIG_NET_TULIP is not set +# CONFIG_NET_UDP_TUNNEL is not set +CONFIG_NET_VENDOR_3COM=y +CONFIG_NET_VENDOR_8390=y +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_NET_VENDOR_AGERE=y +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CIRRUS=y +CONFIG_NET_VENDOR_CISCO=y +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_VENDOR_DLINK=y +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_NET_VENDOR_EXAR=y +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_NET_VENDOR_FARADAY=y +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_NET_VENDOR_HP=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_IBM=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_MICREL=y +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_NET_VENDOR_OKI=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_NET_VENDOR_RDC=y +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_NET_VENDOR_SILICOM=y +CONFIG_NET_VENDOR_SIS=y +CONFIG_NET_VENDOR_SMSC=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_NET_VENDOR_SUN=y +CONFIG_NET_VENDOR_SYNOPSYS=y +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_NET_VENDOR_TI=y +CONFIG_NET_VENDOR_TOSHIBA=y +CONFIG_NET_VENDOR_VIA=y +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NET_VENDOR_XILINX=y +CONFIG_NET_VENDOR_XIRCOM=y +# CONFIG_NET_VRF is not set +# CONFIG_NET_XGENE is not set +CONFIG_NEW_LEDS=y +# CONFIG_NFC is not set +# CONFIG_NFC_DEVICES is not set +# CONFIG_NFSD is not set +# CONFIG_NFSD_DEPRECATED is not set +# CONFIG_NFSD_V2_ACL is not set +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +# CONFIG_NFS_ACL_SUPPORT is not set +CONFIG_NFS_COMMON=y +# CONFIG_NFS_FS is not set +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_V4_1 is not set +# CONFIG_NFTL is not set +# CONFIG_NFT_DUP_IPV4 is not set +# CONFIG_NFT_DUP_IPV6 is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IPV4 is not set +# CONFIG_NF_CONNTRACK_IPV6 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set +# CONFIG_NF_CONNTRACK_RTSP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +# CONFIG_NF_CT_PROTO_DCCP is not set +# CONFIG_NF_CT_PROTO_GRE is not set +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_DUP_IPV6 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +# CONFIG_NF_NAT is not set +# CONFIG_NF_NAT_AMANDA is not set +# CONFIG_NF_NAT_FTP is not set +# CONFIG_NF_NAT_H323 is not set +# CONFIG_NF_NAT_IPV6 is not set +# CONFIG_NF_NAT_IRC is not set +# CONFIG_NF_NAT_MASQUERADE_IPV4 is not set +# CONFIG_NF_NAT_MASQUERADE_IPV6 is not set +# CONFIG_NF_NAT_NEEDED is not set +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_PROTO_GRE is not set +# CONFIG_NF_NAT_RTSP is not set +# CONFIG_NF_NAT_SIP is not set +# CONFIG_NF_NAT_SNMP_BASIC is not set +# CONFIG_NF_NAT_TFTP is not set +# CONFIG_NF_REJECT_IPV4 is not set +# CONFIG_NF_TABLES is not set +# CONFIG_NF_TABLES_NETDEV is not set +# CONFIG_NI52 is not set +# CONFIG_NI65 is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NIU is not set +CONFIG_NLATTR=y +# CONFIG_NLMON is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set +# CONFIG_NLS is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_NORTEL_HERMES is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_NOZOMI is not set +# CONFIG_NO_BOOTMEM is not set +# CONFIG_NO_HZ is not set +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_NS83820 is not set +# CONFIG_NTB is not set +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_NTP_PPS is not set +# CONFIG_NVMEM is not set +# CONFIG_NVRAM is not set +# CONFIG_NV_TCO is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_N_GSM is not set +# CONFIG_OABI_COMPAT is not set +# CONFIG_OBS600 is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_OCF_BENCH is not set +# CONFIG_OCF_C7108 is not set +# CONFIG_OCF_CRYPTOCTEON is not set +# CONFIG_OCF_EP80579 is not set +# CONFIG_OCF_HIFN is not set +# CONFIG_OCF_HIFNHIPP is not set +# CONFIG_OCF_IXP4XX is not set +# CONFIG_OCF_KIRKWOOD is not set +# CONFIG_OCF_OCF is not set +# CONFIG_OCF_OCFNULL is not set +# CONFIG_OCF_SAFE is not set +# CONFIG_OCF_TALITOS is not set +# CONFIG_OCF_UBSEC_SSB is not set +# CONFIG_OC_ETM is not set +# CONFIG_OF_OVERLAY is not set +# CONFIG_OF_SELFTEST is not set +# CONFIG_OF_UNITTEST is not set +# CONFIG_OMAP2_DSS_DEBUG is not set +# CONFIG_OMAP2_DSS_DEBUGFS is not set +# CONFIG_OMAP2_DSS_SDI is not set +# CONFIG_OMAP_CONTROL_USB is not set +# CONFIG_OMAP_OCP2SCP is not set +# CONFIG_OMAP_USB2 is not set +# CONFIG_OMAP_USB3 is not set +# CONFIG_OMFS_FS is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_OPROFILE is not set +# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set +# CONFIG_OPT3001 is not set +# CONFIG_ORION_WATCHDOG is not set +# CONFIG_OSF_PARTITION is not set +CONFIG_OVERLAY_FS=y +# CONFIG_P54_COMMON is not set +# CONFIG_PA12203001 is not set +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_64KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PANEL is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_PANTHERLORD_FF is not set +# CONFIG_PARPORT is not set +# CONFIG_PARPORT_1284 is not set +# CONFIG_PARPORT_AX88796 is not set +# CONFIG_PARPORT_PC is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARASAN_CF is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CS5535 is not set +# CONFIG_PATA_CS5536 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_ISAPNP is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OCTEON_CF is not set +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PCMCIA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_QDI is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_WINBOND_VLB is not set +# CONFIG_PC300TOO is not set +# CONFIG_PCCARD is not set +# CONFIG_PCH_GBE is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_PCI200SYN is not set +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIEASPM is not set +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_PCI_ATMEL is not set +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set +# CONFIG_PCI_HERMES is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_LAYERSCAPE is not set +# CONFIG_PCI_MSI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_PCI_PRI is not set +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +CONFIG_PCI_SYSCALL=y +# CONFIG_PCMCIA is not set +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_3C589 is not set +# CONFIG_PCMCIA_AHA152X is not set +# CONFIG_PCMCIA_ATMEL is not set +# CONFIG_PCMCIA_AXNET is not set +# CONFIG_PCMCIA_DEBUG is not set +# CONFIG_PCMCIA_FDOMAIN is not set +# CONFIG_PCMCIA_FMVJ18X is not set +# CONFIG_PCMCIA_HERMES is not set +# CONFIG_PCMCIA_LOAD_CIS is not set +# CONFIG_PCMCIA_NINJA_SCSI is not set +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_PCNET is not set +# CONFIG_PCMCIA_QLOGIC is not set +# CONFIG_PCMCIA_RAYCS is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_SPECTRUM is not set +# CONFIG_PCMCIA_SYM53C500 is not set +# CONFIG_PCMCIA_WL3501 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_XIRCOM is not set +# CONFIG_PCNET32 is not set +# CONFIG_PCSPKR_PLATFORM is not set +# CONFIG_PD6729 is not set +# CONFIG_PDA_POWER is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_PHANTOM is not set +# CONFIG_PHONE is not set +# CONFIG_PHONET is not set +# CONFIG_PHYLIB is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_PHY_EXYNOS_DP_VIDEO is not set +# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHY_QCOM_DWC3 is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_PID_NS is not set +CONFIG_PINCONF=y +# CONFIG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_CAPRI is not set +# CONFIG_PINCTRL_EXYNOS is not set +# CONFIG_PINCTRL_EXYNOS5440 is not set +# CONFIG_PINCTRL_MSM8X74 is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINMUX=y +# CONFIG_PL320_MBOX is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_PLIP is not set +# CONFIG_PLX_HERMES is not set +# CONFIG_PM is not set +# CONFIG_PMBUS is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_PM_RUNTIME is not set +# CONFIG_PM_WAKELOCKS is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_POHMELFS is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_POWERCAP is not set +# CONFIG_POWERTV is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_RESET_VERSATILE is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PPC4xx_GPIO is not set +# CONFIG_PPC_16K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set +CONFIG_PPC_4K_PAGES=y +# CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_DISABLE_WERROR is not set +# CONFIG_PPC_EMULATED_STATS is not set +# CONFIG_PPC_EPAPR_HV_BYTECHAN is not set +# CONFIG_PPP is not set +# CONFIG_PPPOATM is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +CONFIG_PPP_FILTER=y +# CONFIG_PPP_MPPE is not set +CONFIG_PPP_MULTILINK=y +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_PPS is not set +# CONFIG_PPS_CLIENT_GPIO is not set +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_DEBUG is not set +# CONFIG_PPTP is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_PRINTK=y +# CONFIG_PRINTK_TIME is not set +CONFIG_PRINT_STACK_DEPTH=64 +# CONFIG_PRISM2_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_PROC_CHILDREN is not set +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_PROC_STRIPPED=y +CONFIG_PROC_SYSCTL=y +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILING is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_PROVE_RCU is not set +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_PROVE_RCU_REPEATEDLY is not set +# CONFIG_PSB6970_PHY is not set +# CONFIG_PSTORE is not set +# CONFIG_PTP_1588_CLOCK is not set +# CONFIG_PTP_1588_CLOCK_IXP46X is not set +# CONFIG_PTP_1588_CLOCK_PCH is not set +# CONFIG_PWM is not set +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_QCA7000 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_QORIQ_CPUFREQ is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_R3964 is not set +# CONFIG_R6040 is not set +# CONFIG_R8169 is not set +# CONFIG_R8187SE is not set +# CONFIG_R8188EU is not set +# CONFIG_R8712U is not set +# CONFIG_R8723AU is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_RADIO_AZTECH is not set +# CONFIG_RADIO_CADET is not set +# CONFIG_RADIO_GEMTEK is not set +# CONFIG_RADIO_MAXIRADIO is not set +# CONFIG_RADIO_RTRACK is not set +# CONFIG_RADIO_RTRACK2 is not set +# CONFIG_RADIO_SF16FMI is not set +# CONFIG_RADIO_SF16FMR2 is not set +# CONFIG_RADIO_TERRATEC is not set +# CONFIG_RADIO_TRUST is not set +# CONFIG_RADIO_TYPHOON is not set +# CONFIG_RADIO_ZOLTRIX is not set +# CONFIG_RAID_ATTRS is not set +# CONFIG_RALINK is not set +# CONFIG_RAMOOPS is not set +# CONFIG_RANDOM32_SELFTEST is not set +# CONFIG_RAPIDIO is not set +# CONFIG_RAR_REGISTER is not set +# CONFIG_RAS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +CONFIG_RCU_EXPERT=y +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FAST_NO_HZ is not set +CONFIG_RCU_KTHREAD_PRIO=0 +# CONFIG_RCU_NOCB_CPU is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_TORTURE_TEST_SLOW_INIT_DELAY=3 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_USER_QS is not set +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_RC_CORE is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_LOOPBACK is not set +# CONFIG_RC_MAP is not set +# CONFIG_RDS is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_XZ is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_REDWOOD is not set +# CONFIG_REGMAP is not set +# CONFIG_REGMAP_I2C is not set +# CONFIG_REGMAP_MMIO is not set +# CONFIG_REGMAP_SPI is not set +# CONFIG_REGULATOR is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ANATOP is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_TI_ABB is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_FS_POSIX_ACL is not set +# CONFIG_REISERFS_FS_SECURITY is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_RELAY is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_RFD_FTL is not set +# CONFIG_RFKILL is not set +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_ROCKER is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_ROSE is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPR0521 is not set +# CONFIG_RT2X00 is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_RTC_DEBUG is not set +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_ARMADA38X is not set +# CONFIG_RTC_DRV_AU1XXX is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_BQ4802 is not set +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_EP93XX is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_GENERIC is not set +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12057 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_DRV_MOXART is not set +# CONFIG_RTC_DRV_MPC5121 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_OMAP is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_PS3 is not set +# CONFIG_RTC_DRV_PT7C4338 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_RTC7301 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_SUN6I is not set +# CONFIG_RTC_DRV_TEST is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_XGENE is not set +# CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB=y +CONFIG_RTC_SYSTOHC=y +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_RTL8192E is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTL8306_PHY is not set +# CONFIG_RTL8366RB_PHY is not set +# CONFIG_RTL8366S_PHY is not set +# CONFIG_RTL8366_SMI is not set +# CONFIG_RTL8366_SMI_DEBUG_FS is not set +# CONFIG_RTL8367B_PHY is not set +# CONFIG_RTL8367_PHY is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL_CARDS is not set +# CONFIG_RTS5139 is not set +# CONFIG_RTS5208 is not set +# CONFIG_RTS_PSTOR is not set +CONFIG_RT_MUTEXES=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_RUNTIME_DEBUG is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_S2IO is not set +# CONFIG_SAMPLES is not set +# CONFIG_SAMSUNG_LAPTOP is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_FSL is not set +# CONFIG_SATA_HIGHBANK is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_SATA_PMP is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_RCAR is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIL24 is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SBC_FITPC2_WATCHDOG is not set +# CONFIG_SBE_2T3E3 is not set +# CONFIG_SBYPASS is not set +# CONFIG_SC92031 is not set +# CONFIG_SCA3000 is not set +# CONFIG_SCC is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHED_MC is not set +CONFIG_SCHED_OMIT_FRAME_POINTER=y +# CONFIG_SCHED_SMT is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set +# CONFIG_SCSI_7000FASST is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_ADVANSYS is not set +# CONFIG_SCSI_AHA152X is not set +# CONFIG_SCSI_AHA1542 is not set +# CONFIG_SCSI_AIC79XX is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_AM53C974 is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_SCSI_BFA_FC is not set +# CONFIG_SCSI_BNX2X_FCOE is not set +# CONFIG_SCSI_BNX2_ISCSI is not set +# CONFIG_SCSI_BUSLOGIC is not set +# CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_CXGB3_ISCSI is not set +# CONFIG_SCSI_CXGB4_ISCSI is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_DTC3280 is not set +# CONFIG_SCSI_EATA is not set +# CONFIG_SCSI_ESAS2R is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_GDTH is not set +# CONFIG_SCSI_GENERIC_NCR5380 is not set +# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set +# CONFIG_SCSI_HPSA is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_IN2000 is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_IPR is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_ISCI is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_LPFC is not set +CONFIG_SCSI_MOD=y +# CONFIG_SCSI_MPT2SAS is not set +# CONFIG_SCSI_MPT3SAS is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_MVSAS is not set +# CONFIG_SCSI_MVSAS_DEBUG is not set +# CONFIG_SCSI_MVUMI is not set +# CONFIG_SCSI_NCR53C406A is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_SCSI_PAS16 is not set +# CONFIG_SCSI_PM8001 is not set +# CONFIG_SCSI_PMCRAID is not set +CONFIG_SCSI_PROC_FS=y +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLOGIC_FAS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +# CONFIG_SCSI_SNIC is not set +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C416 is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_T128 is not set +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_U14_34F is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_ULTRASTOR is not set +# CONFIG_SCSI_VIRTIO is not set +# CONFIG_SCSI_WD719X is not set +# CONFIG_SCx200_ACB is not set +# CONFIG_SDIO_UART is not set +# CONFIG_SECCOMP is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SEEQ8005 is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_ACPI_POWER is not set +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATK0110 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_GSC is not set +# CONFIG_SENSORS_HDAPS is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HMC5843 is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_HTU21 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_K10TEMP is not set +# CONFIG_SENSORS_K8TEMP is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VIA_CPUTEMP is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_ACCENT is not set +# CONFIG_SERIAL_8250_BOCA is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DMA=y +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_EM is not set +# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_FINTEK is not set +# CONFIG_SERIAL_8250_FOURPORT is not set +# CONFIG_SERIAL_8250_HUB6 is not set +# CONFIG_SERIAL_8250_INGENIC is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_NR_UARTS=2 +# CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_SYSRQ is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_SERIAL_OF_PLATFORM is not set +# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SH_SCI is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIO is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_SUN4I_PS2 is not set +# CONFIG_SFC is not set +# CONFIG_SFI is not set +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SGI_PARTITION is not set +CONFIG_SHMEM=y +# CONFIG_SH_ETH is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIGMA is not set +CONFIG_SIGNALFD=y +# CONFIG_SIMPLE_GPIO is not set +# CONFIG_SIS190 is not set +# CONFIG_SIS900 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SKY2_DEBUG is not set +CONFIG_SLAB=y +CONFIG_SLABINFO=y +# CONFIG_SLHC is not set +# CONFIG_SLICOSS is not set +# CONFIG_SLIP is not set +# CONFIG_SLOB is not set +# CONFIG_SLUB is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SMARTJOYPLUS_FF is not set +# CONFIG_SMC911X is not set +# CONFIG_SMC9194 is not set +# CONFIG_SMC91X is not set +# CONFIG_SMP is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_SM_FTL is not set +# CONFIG_SND is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +# CONFIG_SND_AD1816A is not set +# CONFIG_SND_AD1848 is not set +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ADLIB is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_ALS100 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALS4000 is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_ASIHPI is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_ATMEL_AC97C is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT2320 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMI8330 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_CS4231 is not set +# CONFIG_SND_CS4236 is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5530 is not set +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1688 is not set +# CONFIG_SND_ES18XX is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FIREWIRE is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_GUSCLASSIC is not set +# CONFIG_SND_GUSEXTREME is not set +# CONFIG_SND_GUSMAX is not set +# CONFIG_SND_HDA_INTEL is not set +CONFIG_SND_HDA_PREALLOC_SIZE=64 +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_HWDEP is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_INTERWAVE is not set +# CONFIG_SND_INTERWAVE_STB is not set +# CONFIG_SND_ISA is not set +# CONFIG_SND_KIRKWOOD_SOC is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_MIRO is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MPC52xx_SOC_EFIKA is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_MTS64 is not set +# CONFIG_SND_MXS_SOC is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_OPL3SA2 is not set +# CONFIG_SND_OPTI92X_AD1848 is not set +# CONFIG_SND_OPTI92X_CS4231 is not set +# CONFIG_SND_OPTI93X is not set +CONFIG_SND_OSSEMUL=y +# CONFIG_SND_OXYGEN is not set +CONFIG_SND_PCI=y +# CONFIG_SND_PCM is not set +# CONFIG_SND_PCMCIA is not set +# CONFIG_SND_PCM_OSS is not set +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_PDAUDIOCF is not set +# CONFIG_SND_PROC_FS is not set +# CONFIG_SND_PORTMAN2X4 is not set +# CONFIG_SND_POWERPC_SOC is not set +# CONFIG_SND_PPC is not set +# CONFIG_SND_RAWMIDI is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SE6X is not set +# CONFIG_SND_RTCTIMER is not set +# CONFIG_SND_SB16 is not set +# CONFIG_SND_SB8 is not set +# CONFIG_SND_SBAWE is not set +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SND_SIS7019 is not set +# CONFIG_SND_SOC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AU1XAUDIO is not set +# CONFIG_SND_SOC_AU1XPSC is not set +# CONFIG_SND_SOC_CACHE_LZO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SND is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_ES8328 is not set +# CONFIG_SND_SOC_EUKREA_TLV320 is not set +# CONFIG_SND_SOC_FSL_ASOC_CARD is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDMI_CODEC is not set +# CONFIG_SND_SOC_IMX_ES8328 is not set +# CONFIG_SND_SOC_IMX_SPDIF is not set +# CONFIG_SND_SOC_IMX_WM8962 is not set +# CONFIG_SND_SOC_INTEL_SST is not set +# CONFIG_SND_SOC_MPC5200_AC97 is not set +# CONFIG_SND_SOC_MPC5200_I2S is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1792A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_QCOM is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_SSCAPE is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_TIMER is not set +# CONFIG_SND_TRIDENT is not set +CONFIG_SND_USB=y +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_US122L is not set +# CONFIG_SND_USB_USX2Y is not set +# CONFIG_SND_USB_VARIAX is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_WAVEFRONT is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SNI_RM is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_CAMERA is not set +# CONFIG_SOC_DRA7XX is not set +# CONFIG_SOC_HAS_OMAP2_SDRC is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_TI is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_SOLO6X10 is not set +# CONFIG_SONYPI is not set +# CONFIG_SONY_LAPTOP is not set +# CONFIG_SOUND is not set +# CONFIG_SOUND_PRIME is not set +# CONFIG_SP5100_TCO is not set +# CONFIG_SPARSEMEM_MANUAL is not set +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +# CONFIG_SPARSE_IRQ is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_SPEAKUP is not set +# CONFIG_SPI is not set +# CONFIG_SPINLOCK_TEST is not set +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AU1550 is not set +# CONFIG_SPI_BCM2835 is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_BUTTERFLY is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_FSL_DSPI is not set +# CONFIG_SPI_FSL_ESPI is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_GPIO_OLD is not set +# CONFIG_SPI_IMG_SPFI is not set +# CONFIG_SPI_LM70_LLP is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_SPI_MPC52xx is not set +# CONFIG_SPI_MPC52xx_PSC is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_OCTEON is not set +# CONFIG_SPI_ORION is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PPC4xx is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_RAMIPS is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TI_QSPI is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_XWAY is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPMI is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XATTR is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SRAM is not set +# CONFIG_SSB is not set +# CONFIG_SSBI is not set +# CONFIG_SSB_DEBUG is not set +# CONFIG_SSB_DRIVER_GPIO is not set +# CONFIG_SSB_PCMCIAHOST is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSFDC is not set +CONFIG_STACKTRACE_SUPPORT=y +# CONFIG_STACKTRACE is not set +# CONFIG_STACK_TRACER is not set +CONFIG_STAGING=y +# CONFIG_STAGING_BOARD is not set +# CONFIG_STAGING_MEDIA is not set +CONFIG_STANDALONE=y +CONFIG_STDBINUTILS=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STE10XP is not set +# CONFIG_STE_MODEM_RPROC is not set +# CONFIG_STK3310 is not set +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set +# CONFIG_STMMAC_ETH is not set +# CONFIG_STMMAC_PLATFORM is not set +# CONFIG_STMMAC_PCI is not set +CONFIG_STP=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_STUB_POULSBO is not set +# CONFIG_SUNDANCE is not set +# CONFIG_SUNGEM is not set +# CONFIG_SUNRPC is not set +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_SUSPEND is not set +CONFIG_SWAP=y +# CONFIG_SWCONFIG is not set +# CONFIG_SWCONFIG_LEDS is not set +# CONFIG_SX9500 is not set +# CONFIG_SXGBE_ETH is not set +# CONFIG_SYNCLINK_CS is not set +# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set +CONFIG_SYN_COOKIES=y +CONFIG_SYSCTL=y +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_SYSFS=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_SYSV_FS is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_T5403 is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_TASKS_RCU is not set +# CONFIG_TC35815 is not set +# CONFIG_TCG_TPM is not set +# CONFIG_TCIC is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_CDG is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_MD5SIG is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_TEGRA_AHB is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_TEHUTI is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_MODULE is not set +# CONFIG_TEST_POWER is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_USER_COPY is not set +CONFIG_TEXTSEARCH=y +# CONFIG_TEXTSEARCH_BM is not set +# CONFIG_TEXTSEARCH_FSM is not set +# CONFIG_TEXTSEARCH_KMP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_THINKPAD_ACPI is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_THUNDERBOLT is not set +# CONFIG_TICK_CPU_ACCOUNTING is not set +CONFIG_TICK_ONESHOT=y +# CONFIG_TIFM_CORE is not set +# CONFIG_TIGON3 is not set +# CONFIG_TIMB_DMA is not set +CONFIG_TIMERFD=y +# CONFIG_TIMER_STATS is not set +CONFIG_TINY_RCU=y +# CONFIG_TIPC is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_AM335X_ADC is not set +# CONFIG_TI_CPSW is not set +# CONFIG_TI_CPSW_ALE is not set +# CONFIG_TI_CPTS is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_TI_DAVINCI_CPDMA is not set +# CONFIG_TI_DAVINCI_MDIO is not set +# CONFIG_TI_ST is not set +# CONFIG_TLAN is not set +# CONFIG_TMD_HERMES is not set +# CONFIG_TMP006 is not set +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +CONFIG_TMPFS_XATTR=y +# CONFIG_TOPSTAR_LAPTOP is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_TOSHIBA_HAPS is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_S3C2410 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_TR is not set +# CONFIG_TRACE_ENUM_MAP_FILE is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_TRACER_SNAPSHOT is not set +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_TRACE_ENUM_MAP_FILE is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_TRACE_SINK is not set +CONFIG_TRACING_SUPPORT=y +CONFIG_TRAD_SIGNALS=y +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_TRANZPORT is not set +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TREE_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set +# CONFIG_TSL4531 is not set +CONFIG_TTY=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6030_GPADC is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_TYPHOON is not set +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_UDF_FS is not set +CONFIG_UDF_NLS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_UFS_FS is not set +# CONFIG_UHID is not set +CONFIG_UIDGID_STRICT_TYPE_CHECKS=y +# CONFIG_UIO is not set +# CONFIG_ULTRA is not set +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_UNIX=y +CONFIG_UNIX98_PTYS=y +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_UNIX_DIAG is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_UPROBE_EVENT is not set +# CONFIG_UPROBES is not set +# CONFIG_USB is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_ADUTUX is not set +CONFIG_USB_ALI_M5632=y +# CONFIG_USB_AMD5536UDC is not set +CONFIG_USB_AN2720=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_APPLEDISPLAY is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_ATM is not set +# CONFIG_USB_BDC_UDC is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_BTMTK is not set +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_CATC is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_CONFIGFS is not set +# CONFIG_USB_CXACRU is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_DEBUG is not set +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_DWC2_DUAL_ROLE is not set +# CONFIG_USB_DWC2_HOST is not set +# CONFIG_USB_DWC2_PERIPHERAL is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC3_EXYNOS is not set +# CONFIG_USB_DWC3_QCOM is not set +# CONFIG_USB_DWC3_PCI is not set +# CONFIG_USB_DWC3_KEYSTONE is not set +# CONFIG_USB_DWC_OTG_LPM is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_EHCI_HCD_AT91 is not set +# CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_EHCI_MSM is not set +# CONFIG_USB_EHCI_MV is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_ET61X251 is not set +CONFIG_USB_EZUSB=y +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_FSL_USB2 is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_VBUS_DRAW=2 +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_GSPCA is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STK1135 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_HID is not set +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_INPUT_IMS_PCU is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_IP_COMMON is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_ISP1760 is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_KBD is not set +# CONFIG_USB_KC2190 is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LIBUSUAL is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_M5602 is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_MSM_OTG is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_NET_AX88179_178A is not set +# CONFIG_USB_NET_AX8817X is not set +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_CDC_NCM is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_DRIVERS is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_OHCI_HCD_PCI is not set +# CONFIG_USB_OHCI_HCD_PPC_OF is not set +# CONFIG_USB_OHCI_HCD_PPC_OF_BE is not set +# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set +# CONFIG_USB_OHCI_HCD_PPC_SOC is not set +# CONFIG_USB_OHCI_HCD_SSB is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_FSM is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_PHY is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_PWC_INPUT_EVDEV is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_RCAR_PHY is not set +# CONFIG_USB_RENESAS_USBHS is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_S2255 is not set +# CONFIG_USB_S3C_HSOTG is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_DEBUG is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_GARMIN is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +CONFIG_USB_SERIAL_KEYSPAN_MPR=y +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +CONFIG_USB_SERIAL_KEYSPAN_USA18X=y +CONFIG_USB_SERIAL_KEYSPAN_USA19=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y +CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y +CONFIG_USB_SERIAL_KEYSPAN_USA19W=y +CONFIG_USB_SERIAL_KEYSPAN_USA28=y +CONFIG_USB_SERIAL_KEYSPAN_USA28X=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y +CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y +CONFIG_USB_SERIAL_KEYSPAN_USA49W=y +CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_USB_SERIAL_QUATECH_USB2 is not set +# CONFIG_USB_SERIAL_SAFE is not set +CONFIG_USB_SERIAL_SAFE_PADDED=y +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_ZTE is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_SPEEDTOUCH is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_TMC is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_UEAGLEATM is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_USS720 is not set +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +# CONFIG_USB_VL600 is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_XUSBATM is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ZR364XX is not set +CONFIG_USERFAULTFD=y +# CONFIG_USELIB is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_USE_OF is not set +# CONFIG_UTS_NS is not set +# CONFIG_UWB is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VDSO is not set +# CONFIG_VETH is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_VF610_ADC is not set +# CONFIG_VFAT_FS is not set +# CONFIG_VGASTATE is not set +# CONFIG_VGA_ARB is not set +# CONFIG_VGA_SWITCHEROO is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT848 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_BWQCAM is not set +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_CAPTURE_DRIVERS is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CQCAM is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_CX231XX is not set +# CONFIG_VIDEO_CX2341X is not set +# CONFIG_VIDEO_CX25840 is not set +# CONFIG_VIDEO_CX88 is not set +# CONFIG_VIDEO_DEV is not set +# CONFIG_VIDEO_DM6446_CCDC is not set +# CONFIG_VIDEO_DT3155 is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_GO7007 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +# CONFIG_VIDEO_HEXIUM_GEMINI is not set +# CONFIG_VIDEO_HEXIUM_ORION is not set +# CONFIG_VIDEO_IR_I2C is not set +# CONFIG_VIDEO_IVTV is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_MEDIA is not set +# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MXB is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_OMAP2_VOUT is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_SAA6588 is not set +# CONFIG_VIDEO_SAA6752HS is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7134 is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TM6000 is not set +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_USBTV is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_VIDEO_V4L2 is not set +# CONFIG_VIDEO_V4L2_COMMON is not set +# CONFIG_VIDEO_V4L2_INT_DEVICE is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_VPX3220 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_VIRQ_DEBUG is not set +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_INPUT is not set +# CONFIG_VIRTIO_MMIO is not set +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTUALIZATION is not set +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRT_TO_BUS=y +# CONFIG_VITESSE_PHY is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_VME_BUS is not set +# CONFIG_VMSPLIT_1G is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_2G_OPT is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMWARE_PVSCSI is not set +# CONFIG_VMXNET3 is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_VORTEX is not set +# CONFIG_VSOCKETS is not set +# CONFIG_VT is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_VXFS_FS is not set +# CONFIG_VXGE is not set +# CONFIG_VXLAN is not set +# CONFIG_W1 is not set +# CONFIG_W1_CON is not set +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_GPIO is not set +# CONFIG_W1_MASTER_MATROX is not set +# CONFIG_W1_SLAVE_BQ27000 is not set +# CONFIG_W1_SLAVE_DS2406 is not set +# CONFIG_W1_SLAVE_DS2408 is not set +# CONFIG_W1_SLAVE_DS2413 is not set +# CONFIG_W1_SLAVE_DS2423 is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +# CONFIG_W1_SLAVE_DS2760 is not set +# CONFIG_W1_SLAVE_DS2780 is not set +# CONFIG_W1_SLAVE_DS2781 is not set +# CONFIG_W1_SLAVE_DS28E04 is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W35UND is not set +# CONFIG_W83627HF_WDT is not set +# CONFIG_W83697HF_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_W83977F_WDT is not set +# CONFIG_WAN is not set +# CONFIG_WANXL is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WD80x3 is not set +# CONFIG_WDTPCI is not set +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PRIV=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WILINK_PLATFORM_DATA=y +# CONFIG_WIMAX is not set +# CONFIG_WIMAX_GDM72XX is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +# CONFIG_WIRELESS_EXT_SYSFS is not set +# CONFIG_WIZNET_W5100 is not set +# CONFIG_WIZNET_W5300 is not set +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLAGS49_H2 is not set +# CONFIG_WLAGS49_H25 is not set +CONFIG_WLAN=y +# CONFIG_WLCORE is not set +# CONFIG_WL_MEDIATEK is not set +CONFIG_WL_TI=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_WR_PPMC is not set +# CONFIG_X25 is not set +# CONFIG_X86_DEBUG_STATIC_CPU_HAS is not set +# CONFIG_X86_PKG_TEMP_THERMAL is not set +CONFIG_X86_SYSFB=y +# CONFIG_XEN is not set +CONFIG_XFRM=y +# CONFIG_XFRM_IPCOMP is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_USER is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_XFS_FS is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_EMACLITE is not set +# CONFIG_XILINX_LL_TEMAC is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_XMON is not set +# CONFIG_XVMALLOC is not set +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_BCJ is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_TEST is not set +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_YAM is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_YENTA is not set +# CONFIG_YENTA_O2 is not set +# CONFIG_YENTA_RICOH is not set +# CONFIG_YENTA_TI is not set +# CONFIG_YENTA_TOSHIBA is not set +# CONFIG_ZBUD is not set +# CONFIG_ZD1211RW is not set +# CONFIG_ZD1211RW_DEBUG is not set +# CONFIG_ZEROPLUS_FF is not set +# CONFIG_ZISOFS is not set +# CONFIG_ZLIB_DEFLATE is not set +# CONFIG_ZLIB_INFLATE is not set +# CONFIG_ZNET is not set +# CONFIG_ZPOOL is not set +CONFIG_ZONE_DMA=y +CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_ZRAM is not set +# CONFIG_ZSMALLOC is not set diff --git a/target/linux/generic/files/Documentation/networking/adm6996.txt b/target/linux/generic/files/Documentation/networking/adm6996.txt new file mode 100644 index 0000000..ab59f1d --- /dev/null +++ b/target/linux/generic/files/Documentation/networking/adm6996.txt @@ -0,0 +1,110 @@ +------- + +ADM6996FC / ADM6996M switch chip driver + + +1. General information + + This driver supports the FC and M models only. The ADM6996F and L are + completely different chips. + + Support for the FC model is extremely limited at the moment. There is no VLAN + support as of yet. The driver will not offer an swconfig interface for the FC + chip. + +1.1 VLAN IDs + + It is possible to define 16 different VLANs. Every VLAN has an identifier, its + VLAN ID. It is easiest if you use at most VLAN IDs 0-15. In that case, the + swconfig based configuration is very straightforward. To define two VLANs with + IDs 4 and 5, you can invoke, for example: + + # swconfig dev ethX vlan 4 set ports '0 1t 2 5t' + # swconfig dev ethX vlan 5 set ports '0t 1t 5t' + + The swconfig framework will automatically invoke 'port Y set pvid Z' for every + port that is an untagged member of VLAN Y, setting its Primary VLAN ID. In + this example, ports 0 and 2 would get "pvid 4". The Primary VLAN ID of a port + is the VLAN ID associated with untagged packets coming in on that port. + + But if you wish to use VLAN IDs outside the range 0-15, this automatic + behaviour of the swconfig framework becomes a problem. The 16 VLANs that + swconfig can configure on the ADM6996 also have a "vid" setting. By default, + this is the same as the number of the VLAN entry, to make the simple behaviour + above possible. To still support a VLAN with a VLAN ID higher than 15 + (presumably because you are in a network where such VLAN IDs are already in + use), you can change the "vid" setting of the VLAN to anything in the range + 0-1023. But suppose you did the following: + + # swconfig dev ethX vlan 0 set vid 998 + # swconfig dev ethX vlan 0 set ports '0 2 5t' + + Now the swconfig framework will issue 'port 0 set pvid 0' and 'port 2 set pvid + 0'. But the "pvid" should be set to 998, so you are responsible for manually + fixing this! + +1.2 VLAN filtering + + The switch is configured to apply source port filtering. This means that + packets are only accepted when the port the packets came in on is a member of + the VLAN the packet should go to. + + Only membership of a VLAN is tested, it does not matter whether it is a tagged + or untagged membership. + + For untagged packets, the destination VLAN is the Primary VLAN ID of the + incoming port. So if the PVID of a port is 0, but that port is not a member of + the VLAN with ID 0, this means that untagged packets on that port are dropped. + This can be used as a roundabout way of dropping untagged packets from a port, + a mode often referred to as "Admit only tagged packets". + +1.3 Reset + + The two supported chip models do not have a sofware-initiated reset. When the + driver is initialised, as well as when the 'reset' swconfig option is invoked, + the driver will set those registers it knows about and supports to the correct + default value. But there are a lot of registers in the chip that the driver + does not support. If something changed those registers, invoking 'reset' or + performing a warm reboot might still leave the chip in a "broken" state. Only + a hardware reset will bring it back in the default state. + +2. Technical details on PHYs and the ADM6996 + + From the viewpoint of the Linux kernel, it is common that an Ethernet adapter + can be seen as a separate MAC entity and a separate PHY entity. The PHY entity + can be queried and set through registers accessible via an MDIO bus. A PHY + normally has a single address on that bus, in the range 0 through 31. + + The ADM6996 has special-purpose registers in the range of PHYs 0 through 10. + Even though all these registers control a single ADM6996 chip, the Linux + kernel treats this as 11 separate PHYs. The driver will bind to these + addresses to prevent a different PHY driver from binding and corrupting these + registers. + + What Linux sees as the PHY on address 0 is meant for the Ethernet MAC + connected to the CPU port of the ADM6996 switch chip (port 5). This is the + Ethernet MAC you will use to send and receive data through the switch. + + The PHYs at addresses 16 through 20 map to the PHYs on ports 0 through 4 of + the switch chip. These can be accessed with the Generic PHY driver, as the + registers have the common layout. + + If a second Ethernet MAC on your board is wired to the port 4 PHY, that MAC + needs to bind to PHY address 20 for the port to work correctly. + + The ADM6996 switch driver will reset the ports 0 through 3 on startup and when + 'reset' is invoked. This could clash with a different PHY driver if the kernel + binds a PHY driver to address 16 through 19. + + If Linux binds a PHY on addresses 1 through 10 to an Ethernet MAC, the ADM6996 + driver will simply always report a connected 100 Mbit/s full-duplex link for + that PHY, and provide no other functionality. This is most likely not what you + want. So if you see a message in your log + + ethX: PHY overlaps ADM6996, providing fixed PHY yy. + + This is most likely an indication that ethX will not work properly, and your + kernel needs to be configured to attach a different PHY to that Ethernet MAC. + + Controlling the mapping between MACs and PHYs is usually done in platform- or + board-specific fixup code. The ADM6996 driver has no influence over this. diff --git a/target/linux/generic/files/arch/mips/fw/myloader/Makefile b/target/linux/generic/files/arch/mips/fw/myloader/Makefile new file mode 100644 index 0000000..34acfd0 --- /dev/null +++ b/target/linux/generic/files/arch/mips/fw/myloader/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the Compex's MyLoader support on MIPS architecture +# + +lib-y += myloader.o diff --git a/target/linux/generic/files/arch/mips/fw/myloader/myloader.c b/target/linux/generic/files/arch/mips/fw/myloader/myloader.c new file mode 100644 index 0000000..a26f9ad --- /dev/null +++ b/target/linux/generic/files/arch/mips/fw/myloader/myloader.c @@ -0,0 +1,63 @@ +/* + * Compex's MyLoader specific prom routines + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include +#include + +#define SYS_PARAMS_ADDR KSEG1ADDR(0x80000800) +#define BOARD_PARAMS_ADDR KSEG1ADDR(0x80000A00) +#define PART_TABLE_ADDR KSEG1ADDR(0x80000C00) +#define BOOT_PARAMS_ADDR KSEG1ADDR(0x80000E00) + +static struct myloader_info myloader_info __initdata; +static int myloader_found __initdata; + +struct myloader_info * __init myloader_get_info(void) +{ + struct mylo_system_params *sysp; + struct mylo_board_params *boardp; + struct mylo_partition_table *parts; + + if (myloader_found) + return &myloader_info; + + sysp = (struct mylo_system_params *)(SYS_PARAMS_ADDR); + boardp = (struct mylo_board_params *)(BOARD_PARAMS_ADDR); + parts = (struct mylo_partition_table *)(PART_TABLE_ADDR); + + printk(KERN_DEBUG "MyLoader: sysp=%08x, boardp=%08x, parts=%08x\n", + sysp->magic, boardp->magic, parts->magic); + + /* Check for some magic numbers */ + if (sysp->magic != MYLO_MAGIC_SYS_PARAMS || + boardp->magic != MYLO_MAGIC_BOARD_PARAMS || + le32_to_cpu(parts->magic) != MYLO_MAGIC_PARTITIONS) + return NULL; + + printk(KERN_DEBUG "MyLoader: id=%04x:%04x, sub_id=%04x:%04x\n", + sysp->vid, sysp->did, sysp->svid, sysp->sdid); + + myloader_info.vid = sysp->vid; + myloader_info.did = sysp->did; + myloader_info.svid = sysp->svid; + myloader_info.sdid = sysp->sdid; + + memcpy(myloader_info.macs, boardp->addr, sizeof(myloader_info.macs)); + + myloader_found = 1; + + return &myloader_info; +} diff --git a/target/linux/generic/files/crypto/ocf/Config.in b/target/linux/generic/files/crypto/ocf/Config.in new file mode 100644 index 0000000..652f76e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/Config.in @@ -0,0 +1,38 @@ +############################################################################# + +mainmenu_option next_comment +comment 'OCF Configuration' +tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF +dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ + CONFIG_OCF_FIPS $CONFIG_OCF_OCF +dep_mbool ' enable harvesting entropy for /dev/random' \ + CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF +dep_tristate ' cryptodev (user space support)' \ + CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF +dep_tristate ' cryptosoft (software crypto engine)' \ + CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF +dep_tristate ' safenet (HW crypto engine)' \ + CONFIG_OCF_SAFE $CONFIG_OCF_OCF +dep_tristate ' IXP4xx (HW crypto engine)' \ + CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF +dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ + CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX +dep_tristate ' hifn (HW crypto engine)' \ + CONFIG_OCF_HIFN $CONFIG_OCF_OCF +dep_tristate ' talitos (HW crypto engine)' \ + CONFIG_OCF_TALITOS $CONFIG_OCF_OCF +dep_tristate ' pasemi (HW crypto engine)' \ + CONFIG_OCF_PASEMI $CONFIG_OCF_OCF +dep_tristate ' ep80579 (HW crypto engine)' \ + CONFIG_OCF_EP80579 $CONFIG_OCF_OCF +dep_tristate ' Micronas c7108 (HW crypto engine)' \ + CONFIG_OCF_C7108 $CONFIG_OCF_OCF +dep_tristate ' uBsec BCM5365 (HW crypto engine)' + CONFIG_OCF_UBSEC_SSB $CONFIG_OCF_OCF +dep_tristate ' ocfnull (does no crypto)' \ + CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF +dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ + CONFIG_OCF_BENCH $CONFIG_OCF_OCF +endmenu + +############################################################################# diff --git a/target/linux/generic/files/crypto/ocf/Kconfig b/target/linux/generic/files/crypto/ocf/Kconfig new file mode 100644 index 0000000..3b3e1d1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/Kconfig @@ -0,0 +1,128 @@ +menu "OCF Configuration" + +config OCF_OCF + tristate "OCF (Open Cryptograhic Framework)" + help + A linux port of the OpenBSD/FreeBSD crypto framework. + +config OCF_RANDOMHARVEST + bool "crypto random --- harvest entropy for /dev/random" + depends on OCF_OCF + help + Includes code to harvest random numbers from devices that support it. + +config OCF_FIPS + bool "enable fips RNG checks" + depends on OCF_OCF && OCF_RANDOMHARVEST + help + Run all RNG provided data through a fips check before + adding it /dev/random's entropy pool. + +config OCF_CRYPTODEV + tristate "cryptodev (user space support)" + depends on OCF_OCF + help + The user space API to access crypto hardware. + +config OCF_CRYPTOSOFT + tristate "cryptosoft (software crypto engine)" + depends on OCF_OCF + select CRYPTO + select CRYPTO_HASH + select CRYPTO_BLKCIPHER + help + A software driver for the OCF framework that uses + the kernel CryptoAPI. + +config OCF_SAFE + tristate "safenet (HW crypto engine)" + depends on OCF_OCF + help + A driver for a number of the safenet Excel crypto accelerators. + Currently tested and working on the 1141 and 1741. + +config OCF_IXP4XX + tristate "IXP4xx (HW crypto engine)" + depends on OCF_OCF + help + XScale IXP4xx crypto accelerator driver. Requires the + Intel Access library. + +config OCF_IXP4XX_SHA1_MD5 + bool "IXP4xx SHA1 and MD5 Hashing" + depends on OCF_IXP4XX + help + Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. + Note: this is MUCH slower than using cryptosoft (software crypto engine). + +config OCF_HIFN + tristate "hifn (HW crypto engine)" + depends on OCF_OCF && PCI + help + OCF driver for various HIFN based crypto accelerators. + (7951, 7955, 7956, 7751, 7811) + +config OCF_HIFNHIPP + tristate "Hifn HIPP (HW packet crypto engine)" + depends on OCF_OCF + help + OCF driver for various HIFN (HIPP) based crypto accelerators + (7855) + +config OCF_TALITOS + tristate "talitos (HW crypto engine)" + depends on OCF_OCF + help + OCF driver for Freescale's security engine (SEC/talitos). + +config OCF_PASEMI + tristate "pasemi (HW crypto engine)" + depends on OCF_OCF && PPC_PASEMI + help + OCF driver for the PA Semi PWRficient DMA Engine + +config OCF_EP80579 + tristate "ep80579 (HW crypto engine)" + depends on OCF_OCF + help + OCF driver for the Intel EP80579 Integrated Processor Product Line. + +config OCF_CRYPTOCTEON + tristate "cryptocteon (HW crypto engine)" + depends on OCF_OCF + help + OCF driver for the Cavium OCTEON Processors. + +config OCF_KIRKWOOD + tristate "kirkwood (HW crypto engine)" + depends on OCF_OCF + help + OCF driver for the Marvell Kirkwood (88F6xxx) Processors. + +config OCF_C7108 + tristate "Micronas 7108 (HW crypto engine)" + depends on OCF_OCF + help + OCF driver for the Microna 7108 Cipher processors. + +config OCF_UBSEC_SSB + tristate "uBsec BCM5365 (HW crypto engine)" + depends on OCF_OCF + help + OCF driver for uBsec BCM5365 hardware crypto accelerator. + +config OCF_OCFNULL + tristate "ocfnull (fake crypto engine)" + depends on OCF_OCF + help + OCF driver for measuring ipsec overheads (does no crypto) + +config OCF_BENCH + tristate "ocf-bench (HW crypto in-kernel benchmark)" + depends on OCF_OCF + help + A very simple encryption test for the in-kernel interface + of OCF. Also includes code to benchmark the IXP Access library + for comparison. + +endmenu diff --git a/target/linux/generic/files/crypto/ocf/Makefile b/target/linux/generic/files/crypto/ocf/Makefile new file mode 100644 index 0000000..78d052c --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/Makefile @@ -0,0 +1,148 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +OCF_OBJS = crypto.o criov.o + +ifdef CONFIG_OCF_RANDOMHARVEST + OCF_OBJS += random.o +endif + +ifdef CONFIG_OCF_FIPS + OCF_OBJS += rndtest.o +endif + +# Add in autoconf.h to get #defines for CONFIG_xxx +AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h +ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) + EXTRA_CFLAGS += -include $(AUTOCONF_H) + export EXTRA_CFLAGS +endif + +ifndef obj + obj ?= . + _obj = subdir + mod-subdirs := safe hifn ixp4xx talitos ocfnull + export-objs += crypto.o criov.o random.o + list-multi += ocf.o + _slash := +else + _obj = obj + _slash := / +endif + +EXTRA_CFLAGS += -I$(obj)/. + +obj-$(CONFIG_OCF_OCF) += ocf.o +obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o +obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o +obj-$(CONFIG_OCF_BENCH) += ocf-bench.o + +$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) +$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) +$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) +$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) +$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) +$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) +$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) +$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) +$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) +$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) +$(_obj)-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb$(_slash) + +ocf-objs := $(OCF_OBJS) + +dummy: + @echo "Please consult the README for how to build OCF." + @echo "If you can't wait then the following should do it:" + @echo "" + @echo " make ocf_modules" + @echo " sudo make ocf_install" + @echo "" + @exit 1 + +$(list-multi) dummy1: $(ocf-objs) + $(LD) -r -o $@ $(ocf-objs) + +.PHONY: +clean: + rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c + rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags + rm -f */modules.order */modules.builtin modules.order modules.builtin + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + +# +# targets to build easily on the current machine +# + +ocf_make: + make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m + make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_CRYPTOSOFT=m + -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_BENCH=m + -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_OCFNULL=m + -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_HIFN=m + +ocf_modules: + $(MAKE) ocf_make OCF_TARGET=modules + +ocf_install: + $(MAKE) ocf_make OCF_TARGET="modules modules_install" + depmod + mkdir -p /usr/include/crypto + cp cryptodev.h /usr/include/crypto/. + +# +# generate full kernel patches for 2.4 and 2.6 kernels to make patching +# your kernel easier +# + +.PHONY: patch +patch: + patchbase=.; \ + [ -d $$patchbase/patches ] || patchbase=..; \ + patch=ocf-linux-base.patch; \ + patch24=ocf-linux-24.patch; \ + patch26=ocf-linux-26.patch; \ + patch3=ocf-linux-3.patch; \ + ( \ + find . -name Makefile; \ + find . -name Config.in; \ + find . -name Kconfig; \ + find . -name README; \ + find . -name '*.[ch]' | grep -v '.mod.c'; \ + ) | while read t; do \ + diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ + done > $$patch; \ + cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ + cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \ + cat $$patchbase/patches/linux-3.2.1-ocf.patch $$patch > $$patch3; \ + + +# +# this target probably does nothing for anyone but me - davidm +# + +.PHONY: release +release: + REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ + CURDIR=`pwd`; \ + rm -rf /tmp/ocf-linux-$$REL*; \ + mkdir -p $$RELDIR/ocf; \ + mkdir -p $$RELDIR/patches; \ + mkdir -p $$RELDIR/crypto-tools; \ + cp README* $$RELDIR/.; \ + cp patches/[!C]* $$RELDIR/patches/.; \ + cp tools/[!C]* $$RELDIR/crypto-tools/.; \ + cp -r [!C]* Config.in $$RELDIR/ocf/.; \ + rm -rf $$RELDIR/ocf/patches $$RELDIR/ocf/tools; \ + rm -f $$RELDIR/ocf/README*; \ + cp $$CURDIR/../../user/crypto-tools/[!C]* $$RELDIR/crypto-tools/.; \ + make -C $$RELDIR/crypto-tools clean; \ + make -C $$RELDIR/ocf clean; \ + find $$RELDIR/ocf -name CVS | xargs rm -rf; \ + cd $$RELDIR/..; \ + tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ + gzip -9n ocf-linux-$$REL.tar + diff --git a/target/linux/generic/files/crypto/ocf/c7108/Makefile b/target/linux/generic/files/crypto/ocf/c7108/Makefile new file mode 100644 index 0000000..e7e634b --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/c7108/Makefile @@ -0,0 +1,12 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_C7108) += aes-7108.o + +obj ?= . +EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/c7108/aes-7108.c b/target/linux/generic/files/crypto/ocf/c7108/aes-7108.c new file mode 100644 index 0000000..f4841f5 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/c7108/aes-7108.c @@ -0,0 +1,841 @@ +/* + * Copyright (C) 2006 Micronas USA + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ + +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include + +/* Runtime mode */ +static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; +//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; + +static int32_t c7108_id = -1; +static struct cipher_7108 **c7108_sessions = NULL; +static u_int32_t c7108_sesnum = 0; +static unsigned long iobar; + +/* Crypto entry points */ +static int c7108_process(void *, struct cryptop *, int); +static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); +static int c7108_freesession(void *, u_int64_t); + +/* Globals */ +static int debug = 0; +static spinlock_t csr_mutex; + +/* Generic controller-based lock */ +#define AES_LOCK()\ + spin_lock(&csr_mutex) +#define AES_UNLOCK()\ + spin_unlock(&csr_mutex) + +/* 7108 AES register access */ +#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) +#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) +#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) +#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) +#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) +#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) + +static int +c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) +{ + int i, nw=0; + nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); + for ( i = 0; i < nw; i++) { + k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | + (k8ptr[i+1] << 8) | k8ptr[i]; + + } + return 0; +} + +static int +c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) +{ + int i, nb=0; + u8* ptr = (u8*)k32ptr; + nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); + for ( i = 0; i < nb; i++) + k8ptr[i] = ptr[i]; + return 0; +} + +static int +c7108_aes_setup_dma(u32 src, u32 dst, u32 len) +{ + if (len < 16) { + printk("len < 16\n"); + return -10; + } + if (len % 16) { + printk("len not multiple of 16\n"); + return -11; + } + c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); + c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); + c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); + c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); + c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); + + return 0; +} + +static int +c7108_aes_set_hw_iv(u8 iv[16]) +{ + c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); + c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); + c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); + c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); + c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); + c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); + c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); + c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); + + return 0; +} + +static void +c7108_aes_read_dkey(u32 * dkey) +{ + dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | + c7108_reg_rd16(C7108_AES_EKEY0_LO); + dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | + c7108_reg_rd16(C7108_AES_EKEY1_LO); + dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | + c7108_reg_rd16(C7108_AES_EKEY2_LO); + dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | + c7108_reg_rd16(C7108_AES_EKEY3_LO); + dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | + c7108_reg_rd16(C7108_AES_EKEY4_LO); + dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | + c7108_reg_rd16(C7108_AES_EKEY5_LO); + dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | + c7108_reg_rd16(C7108_AES_EKEY6_LO); + dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | + c7108_reg_rd16(C7108_AES_EKEY7_LO); +} + +static int +c7108_aes_cipher(int op, + u32 dst, + u32 src, + u32 len, + int klen, + u16 mode, + u32 key[8], + u8 iv[16]) +{ + int rv = 0, cnt=0; + u16 ctrl = 0, stat = 0; + + AES_LOCK(); + + /* Setup key length */ + if (klen == 128) { + ctrl |= C7108_AES_KEY_LEN_128; + } else if (klen == 192) { + ctrl |= C7108_AES_KEY_LEN_192; + } else if (klen == 256) { + ctrl |= C7108_AES_KEY_LEN_256; + } else { + AES_UNLOCK(); + return -3; + } + + /* Check opcode */ + if (C7108_AES_ENCRYPT == op) { + ctrl |= C7108_AES_ENCRYPT; + } else if (C7108_AES_DECRYPT == op) { + ctrl |= C7108_AES_DECRYPT; + } else { + AES_UNLOCK(); + return -4; + } + + /* check mode */ + if ( (mode != C7108_AES_CTRL_MODE_CBC) && + (mode != C7108_AES_CTRL_MODE_CFB) && + (mode != C7108_AES_CTRL_MODE_OFB) && + (mode != C7108_AES_CTRL_MODE_CTR) && + (mode != C7108_AES_CTRL_MODE_ECB) ) { + AES_UNLOCK(); + return -5; + } + + /* Now set mode */ + ctrl |= mode; + + /* For CFB, OFB, and CTR, neither backward key + * expansion nor key inversion is required. + */ + if ( (C7108_AES_DECRYPT == op) && + (C7108_AES_CTRL_MODE_CBC == mode || + C7108_AES_CTRL_MODE_ECB == mode ) ){ + + /* Program Key */ + c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); + c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); + c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); + c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); + c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); + c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); + c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); + c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); + c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); + c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); + c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); + c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); + + + if (192 == klen) { + c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); + c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); + c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); + c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); + + } else if (256 == klen) { + /* 256 */ + c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); + c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); + c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); + c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); + + } + + } else { + /* Program Key */ + c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); + c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); + c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); + c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); + c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); + c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); + c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); + c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); + c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); + c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); + c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); + c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); + c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); + c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); + c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); + c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); + + } + + /* Set IV always */ + c7108_aes_set_hw_iv(iv); + + /* Program DMA addresses */ + if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { + AES_UNLOCK(); + return rv; + } + + + /* Start AES cipher */ + c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); + + //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); + do { + /* TODO: interrupt mode */ + // printk("aes_stat=0x%x\n", stat); + //udelay(100); + } while ((cnt++ < 1000000) && + !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); + + + if ((mode == C7108_AES_CTRL_MODE_ECB)|| + (mode == C7108_AES_CTRL_MODE_CBC)) { + /* Save out key when the lock is held ... */ + c7108_aes_read_dkey(key); + } + + AES_UNLOCK(); + return 0; + +} + +/* + * Generate a new crypto device session. + */ +static int +c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) +{ + struct cipher_7108 **swd; + u_int32_t i; + char *algo; + int mode, xfm_type; + + dprintk("%s()\n", __FUNCTION__); + if (sid == NULL || cri == NULL) { + dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + if (c7108_sessions) { + for (i = 1; i < c7108_sesnum; i++) + if (c7108_sessions[i] == NULL) + break; + } else + i = 1; /* NB: to silence compiler warning */ + + if (c7108_sessions == NULL || i == c7108_sesnum) { + if (c7108_sessions == NULL) { + i = 1; /* We leave c7108_sessions[0] empty */ + c7108_sesnum = CRYPTO_SW_SESSIONS; + } else + c7108_sesnum *= 2; + + swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), + GFP_ATOMIC); + if (swd == NULL) { + /* Reset session number */ + if (c7108_sesnum == CRYPTO_SW_SESSIONS) + c7108_sesnum = 0; + else + c7108_sesnum /= 2; + dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); + return ENOBUFS; + } + memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); + + /* Copy existing sessions */ + if (c7108_sessions) { + memcpy(swd, c7108_sessions, + (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); + kfree(c7108_sessions); + } + + c7108_sessions = swd; + + } + + swd = &c7108_sessions[i]; + *sid = i; + + while (cri) { + *swd = (struct cipher_7108 *) + kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); + if (*swd == NULL) { + c7108_freesession(NULL, i); + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return ENOBUFS; + } + memset(*swd, 0, sizeof(struct cipher_7108)); + + algo = NULL; + mode = 0; + xfm_type = HW_TYPE_CIPHER; + + switch (cri->cri_alg) { + + case CRYPTO_AES_CBC: + algo = "aes"; + mode = CRYPTO_TFM_MODE_CBC; + c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; + break; +#if 0 + case CRYPTO_AES_CTR: + algo = "aes_ctr"; + mode = CRYPTO_TFM_MODE_CBC; + c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; + break; + case CRYPTO_AES_ECB: + algo = "aes_ecb"; + mode = CRYPTO_TFM_MODE_CBC; + c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; + break; + case CRYPTO_AES_OFB: + algo = "aes_ofb"; + mode = CRYPTO_TFM_MODE_CBC; + c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; + break; + case CRYPTO_AES_CFB: + algo = "aes_cfb"; + mode = CRYPTO_TFM_MODE_CBC; + c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; + break; +#endif + default: + printk("unsupported crypto algorithm: %d\n", + cri->cri_alg); + return -EINVAL; + break; + } + + + if (!algo || !*algo) { + printk("cypher_7108_crypto: Unknown algo 0x%x\n", + cri->cri_alg); + c7108_freesession(NULL, i); + return EINVAL; + } + + if (xfm_type == HW_TYPE_CIPHER) { + if (debug) { + dprintk("%s key:", __FUNCTION__); + for (i = 0; i < (cri->cri_klen + 7) / 8; i++) + dprintk("%s0x%02x", (i % 8) ? " " : "\n ", + cri->cri_key[i]); + dprintk("\n"); + } + + } else if (xfm_type == SW_TYPE_HMAC || + xfm_type == SW_TYPE_HASH) { + printk("cypher_7108_crypto: HMAC unsupported!\n"); + return -EINVAL; + c7108_freesession(NULL, i); + } else { + printk("cypher_7108_crypto: " + "Unhandled xfm_type %d\n", xfm_type); + c7108_freesession(NULL, i); + return EINVAL; + } + + (*swd)->cri_alg = cri->cri_alg; + (*swd)->xfm_type = xfm_type; + + cri = cri->cri_next; + swd = &((*swd)->next); + } + return 0; +} + +/* + * Free a session. + */ +static int +c7108_freesession(void *arg, u_int64_t tid) +{ + struct cipher_7108 *swd; + u_int32_t sid = CRYPTO_SESID2LID(tid); + + dprintk("%s()\n", __FUNCTION__); + if (sid > c7108_sesnum || c7108_sessions == NULL || + c7108_sessions[sid] == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return(EINVAL); + } + + /* Silently accept and return */ + if (sid == 0) + return(0); + + while ((swd = c7108_sessions[sid]) != NULL) { + c7108_sessions[sid] = swd->next; + kfree(swd); + } + return 0; +} + +/* + * Process a hardware request. + */ +static int +c7108_process(void *arg, struct cryptop *crp, int hint) +{ + struct cryptodesc *crd; + struct cipher_7108 *sw; + u_int32_t lid; + int type; + u32 hwkey[8]; + +#define SCATTERLIST_MAX 16 + struct scatterlist sg[SCATTERLIST_MAX]; + int sg_num, sg_len, skip; + struct sk_buff *skb = NULL; + struct uio *uiop = NULL; + + dprintk("%s()\n", __FUNCTION__); + /* Sanity check */ + if (crp == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + crp->crp_etype = 0; + + if (crp->crp_desc == NULL || crp->crp_buf == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + crp->crp_etype = EINVAL; + goto done; + } + + lid = crp->crp_sid & 0xffffffff; + if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || + c7108_sessions[lid] == NULL) { + crp->crp_etype = ENOENT; + dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); + goto done; + } + + /* + * do some error checking outside of the loop for SKB and IOV + * processing this leaves us with valid skb or uiop pointers + * for later + */ + if (crp->crp_flags & CRYPTO_F_SKBUF) { + skb = (struct sk_buff *) crp->crp_buf; + if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { + printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", + __FILE__, __LINE__, + skb_shinfo(skb)->nr_frags); + goto done; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + uiop = (struct uio *) crp->crp_buf; + if (uiop->uio_iovcnt > SCATTERLIST_MAX) { + printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", + __FILE__, __LINE__, + uiop->uio_iovcnt); + goto done; + } + } + + /* Go through crypto descriptors, processing as we go */ + for (crd = crp->crp_desc; crd; crd = crd->crd_next) { + /* + * Find the crypto context. + * + * XXX Note that the logic here prevents us from having + * XXX the same algorithm multiple times in a session + * XXX (or rather, we can but it won't give us the right + * XXX results). To do that, we'd need some way of differentiating + * XXX between the various instances of an algorithm (so we can + * XXX locate the correct crypto context). + */ + for (sw = c7108_sessions[lid]; + sw && sw->cri_alg != crd->crd_alg; + sw = sw->next) + ; + + /* No such context ? */ + if (sw == NULL) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + goto done; + } + + skip = crd->crd_skip; + + /* + * setup the SG list skip from the start of the buffer + */ + memset(sg, 0, sizeof(sg)); + if (crp->crp_flags & CRYPTO_F_SKBUF) { + int i, len; + type = CRYPTO_BUF_SKBUF; + + sg_num = 0; + sg_len = 0; + + if (skip < skb_headlen(skb)) { + //sg[sg_num].page = virt_to_page(skb->data + skip); + //sg[sg_num].offset = offset_in_page(skb->data + skip); + len = skb_headlen(skb) - skip; + if (len + sg_len > crd->crd_len) + len = crd->crd_len - sg_len; + //sg[sg_num].length = len; + sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); + sg_len += sg[sg_num].length; + sg_num++; + skip = 0; + } else + skip -= skb_headlen(skb); + + for (i = 0; sg_len < crd->crd_len && + i < skb_shinfo(skb)->nr_frags && + sg_num < SCATTERLIST_MAX; i++) { + if (skip < skb_shinfo(skb)->frags[i].size) { + //sg[sg_num].page = skb_frag_page(&skb_shinfo(skb)->frags[i]); + //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; + len = skb_shinfo(skb)->frags[i].size - skip; + if (len + sg_len > crd->crd_len) + len = crd->crd_len - sg_len; + //sg[sg_num].length = len; + sg_set_page(&sg[sg_num], skb_frag_page(&skb_shinfo(skb)->frags[i]), len, skb_shinfo(skb)->frags[i].page_offset + skip); + sg_len += sg[sg_num].length; + sg_num++; + skip = 0; + } else + skip -= skb_shinfo(skb)->frags[i].size; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + int len; + type = CRYPTO_BUF_IOV; + sg_len = 0; + for (sg_num = 0; sg_len < crd->crd_len && + sg_num < uiop->uio_iovcnt && + sg_num < SCATTERLIST_MAX; sg_num++) { + if (skip < uiop->uio_iov[sg_num].iov_len) { + //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); + //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); + len = uiop->uio_iov[sg_num].iov_len - skip; + if (len + sg_len > crd->crd_len) + len = crd->crd_len - sg_len; + //sg[sg_num].length = len; + sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); + sg_len += sg[sg_num].length; + skip = 0; + } else + skip -= uiop->uio_iov[sg_num].iov_len; + } + } else { + type = CRYPTO_BUF_CONTIG; + //sg[0].page = virt_to_page(crp->crp_buf + skip); + //sg[0].offset = offset_in_page(crp->crp_buf + skip); + sg_len = (crp->crp_ilen - skip); + if (sg_len > crd->crd_len) + sg_len = crd->crd_len; + //sg[0].length = sg_len; + sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); + sg_num = 1; + } + if (sg_num > 0) + sg_mark_end(&sg[sg_num-1]); + + + switch (sw->xfm_type) { + + case HW_TYPE_CIPHER: { + + unsigned char iv[64]; + unsigned char *ivp = iv; + int i; + int ivsize = 16; /* fixed for AES */ + int blocksize = 16; /* fixed for AES */ + + if (sg_len < blocksize) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: EINVAL len %d < %d\n", + __FILE__, __LINE__, + sg_len, + blocksize); + goto done; + } + + if (ivsize > sizeof(iv)) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + goto done; + } + + if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ + + if (crd->crd_flags & CRD_F_IV_EXPLICIT) { + ivp = crd->crd_iv; + } else { + get_random_bytes(ivp, ivsize); + } + /* + * do we have to copy the IV back to the buffer ? + */ + if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { + crypto_copyback(crp->crp_buf, + crd->crd_inject, + ivsize, + (caddr_t)ivp); + } + + c7108_xlate_key(crd->crd_klen, + (u8*)crd->crd_key, (u32*)hwkey); + + /* Encrypt SG list */ + for (i = 0; i < sg_num; i++) { + sg[i].dma_address = + dma_map_single(NULL, + kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); +#if 0 + printk("sg[%d]:0x%08x, off 0x%08x " + "kmap 0x%08x phys 0x%08x\n", + i, sg[i].page, sg[i].offset, + kmap(sg[i].page) + sg[i].offset, + sg[i].dma_address); +#endif + c7108_aes_cipher(C7108_AES_ENCRYPT, + sg[i].dma_address, + sg[i].dma_address, + sg_len, + crd->crd_klen, + c7108_crypto_mode, + hwkey, + ivp); + + if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| + (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { + /* Read back expanded key and cache it in key + * context. + * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) + * where you set the key once. + */ + c7108_cache_key(crd->crd_klen, + (u32*)hwkey, (u8*)crd->crd_key); +#if 0 + printk("%s expanded key:", __FUNCTION__); + for (i = 0; i < (crd->crd_klen + 7) / 8; i++) + printk("%s0x%02x", (i % 8) ? " " : "\n ", + crd->crd_key[i]); + printk("\n"); +#endif + } + } + } + else { /*decrypt */ + + if (crd->crd_flags & CRD_F_IV_EXPLICIT) { + ivp = crd->crd_iv; + } else { + crypto_copydata(crp->crp_buf, crd->crd_inject, + ivsize, (caddr_t)ivp); + } + + c7108_xlate_key(crd->crd_klen, + (u8*)crd->crd_key, (u32*)hwkey); + + /* Decrypt SG list */ + for (i = 0; i < sg_num; i++) { + sg[i].dma_address = + dma_map_single(NULL, + kmap(sg_page(&sg[i])) + sg[i].offset, + sg_len, DMA_BIDIRECTIONAL); + +#if 0 + printk("sg[%d]:0x%08x, off 0x%08x " + "kmap 0x%08x phys 0x%08x\n", + i, sg[i].page, sg[i].offset, + kmap(sg[i].page) + sg[i].offset, + sg[i].dma_address); +#endif + c7108_aes_cipher(C7108_AES_DECRYPT, + sg[i].dma_address, + sg[i].dma_address, + sg_len, + crd->crd_klen, + c7108_crypto_mode, + hwkey, + ivp); + } + } + } break; + case SW_TYPE_HMAC: + case SW_TYPE_HASH: + crp->crp_etype = EINVAL; + goto done; + break; + + case SW_TYPE_COMP: + crp->crp_etype = EINVAL; + goto done; + break; + + default: + /* Unknown/unsupported algorithm */ + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + crp->crp_etype = EINVAL; + goto done; + } + } + +done: + crypto_done(crp); + return 0; +} + +static struct { + softc_device_decl sc_dev; +} a7108dev; + +static device_method_t a7108_methods = { +/* crypto device methods */ + DEVMETHOD(cryptodev_newsession, c7108_newsession), + DEVMETHOD(cryptodev_freesession, c7108_freesession), + DEVMETHOD(cryptodev_process, c7108_process), + DEVMETHOD(cryptodev_kprocess, NULL) +}; + +static int +cypher_7108_crypto_init(void) +{ + dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); + + iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); + printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", + iobar, CCU_AES_REG_BASE, + c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : + c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : + c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : + c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : + c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); + csr_mutex = SPIN_LOCK_UNLOCKED; + + memset(&a7108dev, 0, sizeof(a7108dev)); + softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); + + c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); + if (c7108_id < 0) + panic("7108: crypto device cannot initialize!"); + +// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); + crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); + + return(0); +} + +static void +cypher_7108_crypto_exit(void) +{ + dprintk("%s()\n", __FUNCTION__); + crypto_unregister_all(c7108_id); + c7108_id = -1; +} + +module_init(cypher_7108_crypto_init); +module_exit(cypher_7108_crypto_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); diff --git a/target/linux/generic/files/crypto/ocf/c7108/aes-7108.h b/target/linux/generic/files/crypto/ocf/c7108/aes-7108.h new file mode 100644 index 0000000..0c7bfcb --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/c7108/aes-7108.h @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2006 Micronas USA + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ + +#ifndef __AES_7108_H__ +#define __AES_7108_H__ + +/* Cypher 7108 AES Controller Hardware */ +#define CCU_REG_BASE 0x1b500000 +#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) +#define C7108_AES_KEY0_LO (0x0000) +#define C7108_AES_KEY0_HI (0x0004) +#define C7108_AES_KEY1_LO (0x0008) +#define C7108_AES_KEY1_HI (0x000c) +#define C7108_AES_KEY2_LO (0x0010) +#define C7108_AES_KEY2_HI (0x0014) +#define C7108_AES_KEY3_LO (0x0018) +#define C7108_AES_KEY3_HI (0x001c) +#define C7108_AES_KEY4_LO (0x0020) +#define C7108_AES_KEY4_HI (0x0024) +#define C7108_AES_KEY5_LO (0x0028) +#define C7108_AES_KEY5_HI (0x002c) +#define C7108_AES_KEY6_LO (0x0030) +#define C7108_AES_KEY6_HI (0x0034) +#define C7108_AES_KEY7_LO (0x0038) +#define C7108_AES_KEY7_HI (0x003c) +#define C7108_AES_IV0_LO (0x0040) +#define C7108_AES_IV0_HI (0x0044) +#define C7108_AES_IV1_LO (0x0048) +#define C7108_AES_IV1_HI (0x004c) +#define C7108_AES_IV2_LO (0x0050) +#define C7108_AES_IV2_HI (0x0054) +#define C7108_AES_IV3_LO (0x0058) +#define C7108_AES_IV3_HI (0x005c) + +#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ +#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ +#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ +#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ +#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ + +/* AES/Copy engine control register */ +#define C7108_AES_CTRL (0x007c) /* AES control */ +#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ + +/* AES Cipher mode, controlled by setting Bits 2:0 */ +#define C7108_AES_CTRL_MODE_CBC 0 +#define C7108_AES_CTRL_MODE_CFB (1<<0) +#define C7108_AES_CTRL_MODE_OFB (1<<1) +#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) +#define C7108_AES_CTRL_MODE_ECB (1<<2) + +/* AES Key length , Bits 5:4 */ +#define C7108_AES_KEY_LEN_128 0 /* 00 */ +#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ +#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ + +/* AES Operation (crypt/decrypt), Bit 3 */ +#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ +#define C7108_AES_ENCRYPT 0 +#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ +#define C7108_AES_GO (1<<14) /* Run */ +#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ + + +/* Expanded key registers */ +#define C7108_AES_EKEY0_LO (0x0080) +#define C7108_AES_EKEY0_HI (0x0084) +#define C7108_AES_EKEY1_LO (0x0088) +#define C7108_AES_EKEY1_HI (0x008c) +#define C7108_AES_EKEY2_LO (0x0090) +#define C7108_AES_EKEY2_HI (0x0094) +#define C7108_AES_EKEY3_LO (0x0098) +#define C7108_AES_EKEY3_HI (0x009c) +#define C7108_AES_EKEY4_LO (0x00a0) +#define C7108_AES_EKEY4_HI (0x00a4) +#define C7108_AES_EKEY5_LO (0x00a8) +#define C7108_AES_EKEY5_HI (0x00ac) +#define C7108_AES_EKEY6_LO (0x00b0) +#define C7108_AES_EKEY6_HI (0x00b4) +#define C7108_AES_EKEY7_LO (0x00b8) +#define C7108_AES_EKEY7_HI (0x00bc) +#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ + +#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) + +/* Software session entry */ + +#define HW_TYPE_CIPHER 0 +#define SW_TYPE_HMAC 1 +#define SW_TYPE_AUTH2 2 +#define SW_TYPE_HASH 3 +#define SW_TYPE_COMP 4 + +struct cipher_7108 { + int xfm_type; + int cri_alg; + union { + struct { + char sw_key[HMAC_BLOCK_LEN]; + int sw_klen; + int sw_authlen; + } hmac; + } u; + struct cipher_7108 *next; +}; + + + +#endif /* __C7108_AES_7108_H__ */ diff --git a/target/linux/generic/files/crypto/ocf/criov.c b/target/linux/generic/files/crypto/ocf/criov.c new file mode 100644 index 0000000..a8c1a8c --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/criov.c @@ -0,0 +1,215 @@ +/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ + +/* + * Linux port done by David McCullough + * Copyright (C) 2006-2010 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * The license and original author are listed below. + * + * Copyright (c) 1999 Theo de Raadt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * +__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * This macro is only for avoiding code duplication, as we need to skip + * given number of bytes in the same way in three functions below. + */ +#define CUIO_SKIP() do { \ + KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ + KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ + while (off > 0) { \ + KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ + if (off < iov->iov_len) \ + break; \ + off -= iov->iov_len; \ + iol--; \ + iov++; \ + } \ +} while (0) + +void +cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) +{ + struct iovec *iov = uio->uio_iov; + int iol = uio->uio_iovcnt; + unsigned count; + + CUIO_SKIP(); + while (len > 0) { + KASSERT(iol >= 0, ("%s: empty", __func__)); + count = min((int)(iov->iov_len - off), len); + memcpy(cp, ((caddr_t)iov->iov_base) + off, count); + len -= count; + cp += count; + off = 0; + iol--; + iov++; + } +} + +void +cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) +{ + struct iovec *iov = uio->uio_iov; + int iol = uio->uio_iovcnt; + unsigned count; + + CUIO_SKIP(); + while (len > 0) { + KASSERT(iol >= 0, ("%s: empty", __func__)); + count = min((int)(iov->iov_len - off), len); + memcpy(((caddr_t)iov->iov_base) + off, cp, count); + len -= count; + cp += count; + off = 0; + iol--; + iov++; + } +} + +/* + * Return a pointer to iov/offset of location in iovec list. + */ +struct iovec * +cuio_getptr(struct uio *uio, int loc, int *off) +{ + struct iovec *iov = uio->uio_iov; + int iol = uio->uio_iovcnt; + + while (loc >= 0) { + /* Normal end of search */ + if (loc < iov->iov_len) { + *off = loc; + return (iov); + } + + loc -= iov->iov_len; + if (iol == 0) { + if (loc == 0) { + /* Point at the end of valid data */ + *off = iov->iov_len; + return (iov); + } else + return (NULL); + } else { + iov++, iol--; + } + } + + return (NULL); +} + +EXPORT_SYMBOL(cuio_copyback); +EXPORT_SYMBOL(cuio_copydata); +EXPORT_SYMBOL(cuio_getptr); + +static void +skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) +{ + int i; + if (offset < skb_headlen(skb)) { + memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); + len -= skb_headlen(skb); + cp += skb_headlen(skb); + } + offset -= skb_headlen(skb); + for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { + if (offset < skb_shinfo(skb)->frags[i].size) { + memcpy(page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) + + skb_shinfo(skb)->frags[i].page_offset, + cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); + len -= skb_shinfo(skb)->frags[i].size; + cp += skb_shinfo(skb)->frags[i].size; + } + offset -= skb_shinfo(skb)->frags[i].size; + } +} + +void +crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) +{ + + if ((flags & CRYPTO_F_SKBUF) != 0) + skb_copy_bits_back((struct sk_buff *)buf, off, in, size); + else if ((flags & CRYPTO_F_IOV) != 0) + cuio_copyback((struct uio *)buf, off, size, in); + else + bcopy(in, buf + off, size); +} + +void +crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) +{ + + if ((flags & CRYPTO_F_SKBUF) != 0) + skb_copy_bits((struct sk_buff *)buf, off, out, size); + else if ((flags & CRYPTO_F_IOV) != 0) + cuio_copydata((struct uio *)buf, off, size, out); + else + bcopy(buf + off, out, size); +} + +int +crypto_apply(int flags, caddr_t buf, int off, int len, + int (*f)(void *, void *, u_int), void *arg) +{ +#if 0 + int error; + + if ((flags & CRYPTO_F_SKBUF) != 0) + error = XXXXXX((struct mbuf *)buf, off, len, f, arg); + else if ((flags & CRYPTO_F_IOV) != 0) + error = cuio_apply((struct uio *)buf, off, len, f, arg); + else + error = (*f)(arg, buf + off, len); + return (error); +#else + KASSERT(0, ("crypto_apply not implemented!\n")); +#endif + return 0; +} + +EXPORT_SYMBOL(crypto_copyback); +EXPORT_SYMBOL(crypto_copydata); +EXPORT_SYMBOL(crypto_apply); + diff --git a/target/linux/generic/files/crypto/ocf/crypto.c b/target/linux/generic/files/crypto/ocf/crypto.c new file mode 100644 index 0000000..dab3427 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/crypto.c @@ -0,0 +1,1766 @@ +/*- + * Linux port done by David McCullough + * Copyright (C) 2006-2010 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * The license and original author are listed below. + * + * Redistribution and use in source and binary forms, with or without + * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. + * + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if 0 +#include +__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); +#endif + +/* + * Cryptographic Subsystem. + * + * This code is derived from the Openbsd Cryptographic Framework (OCF) + * that has the copyright shown below. Very little of the original + * code remains. + */ +/*- + * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) + * + * This code was written by Angelos D. Keromytis in Athens, Greece, in + * February 2000. Network Security Technologies Inc. (NSTI) kindly + * supported the development of this code. + * + * Copyright (c) 2000, 2001 Angelos D. Keromytis + * + * Permission to use, copy, and modify this software with or without fee + * is hereby granted, provided that this entire notice is included in + * all source code copies of any software which is or includes a copy or + * modification of this software. + * + * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY + * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE + * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR + * PURPOSE. + * +__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); + */ + + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,4) +#include +#endif +#include + +/* + * keep track of whether or not we have been initialised, a big + * issue if we are linked into the kernel and a driver gets started before + * us + */ +static int crypto_initted = 0; + +/* + * Crypto drivers register themselves by allocating a slot in the + * crypto_drivers table with crypto_get_driverid() and then registering + * each algorithm they support with crypto_register() and crypto_kregister(). + */ + +/* + * lock on driver table + * we track its state as spin_is_locked does not do anything on non-SMP boxes + */ +static spinlock_t crypto_drivers_lock; +static int crypto_drivers_locked; /* for non-SMP boxes */ + +#define CRYPTO_DRIVER_LOCK() \ + ({ \ + spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ + crypto_drivers_locked = 1; \ + dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ + }) +#define CRYPTO_DRIVER_UNLOCK() \ + ({ \ + dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ + crypto_drivers_locked = 0; \ + spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ + }) +#define CRYPTO_DRIVER_ASSERT() \ + ({ \ + if (!crypto_drivers_locked) { \ + dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ + } \ + }) + +/* + * Crypto device/driver capabilities structure. + * + * Synchronization: + * (d) - protected by CRYPTO_DRIVER_LOCK() + * (q) - protected by CRYPTO_Q_LOCK() + * Not tagged fields are read-only. + */ +struct cryptocap { + device_t cc_dev; /* (d) device/driver */ + u_int32_t cc_sessions; /* (d) # of sessions */ + u_int32_t cc_koperations; /* (d) # os asym operations */ + /* + * Largest possible operator length (in bits) for each type of + * encryption algorithm. XXX not used + */ + u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; + u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; + u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; + + int cc_flags; /* (d) flags */ +#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ + int cc_qblocked; /* (q) symmetric q blocked */ + int cc_kqblocked; /* (q) asymmetric q blocked */ + + int cc_unqblocked; /* (q) symmetric q blocked */ + int cc_unkqblocked; /* (q) asymmetric q blocked */ +}; +static struct cryptocap *crypto_drivers = NULL; +static int crypto_drivers_num = 0; + +/* + * There are two queues for crypto requests; one for symmetric (e.g. + * cipher) operations and one for asymmetric (e.g. MOD)operations. + * A single mutex is used to lock access to both queues. We could + * have one per-queue but having one simplifies handling of block/unblock + * operations. + */ +static LIST_HEAD(crp_q); /* crypto request queue */ +static LIST_HEAD(crp_kq); /* asym request queue */ + +static spinlock_t crypto_q_lock; + +int crypto_all_qblocked = 0; /* protect with Q_LOCK */ +module_param(crypto_all_qblocked, int, 0444); +MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); + +int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ +module_param(crypto_all_kqblocked, int, 0444); +MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); + +#define CRYPTO_Q_LOCK() \ + ({ \ + spin_lock_irqsave(&crypto_q_lock, q_flags); \ + dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ + }) +#define CRYPTO_Q_UNLOCK() \ + ({ \ + dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ + spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ + }) + +/* + * There are two queues for processing completed crypto requests; one + * for the symmetric and one for the asymmetric ops. We only need one + * but have two to avoid type futzing (cryptop vs. cryptkop). A single + * mutex is used to lock access to both queues. Note that this lock + * must be separate from the lock on request queues to insure driver + * callbacks don't generate lock order reversals. + */ +static LIST_HEAD(crp_ret_q); /* callback queues */ +static LIST_HEAD(crp_ret_kq); + +static spinlock_t crypto_ret_q_lock; +#define CRYPTO_RETQ_LOCK() \ + ({ \ + spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ + dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ + }) +#define CRYPTO_RETQ_UNLOCK() \ + ({ \ + dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ + spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ + }) +#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static kmem_cache_t *cryptop_zone; +static kmem_cache_t *cryptodesc_zone; +#else +static struct kmem_cache *cryptop_zone; +static struct kmem_cache *cryptodesc_zone; +#endif + +#define debug crypto_debug +int crypto_debug = 0; +module_param(crypto_debug, int, 0644); +MODULE_PARM_DESC(crypto_debug, "Enable debug"); +EXPORT_SYMBOL(crypto_debug); + +/* + * Maximum number of outstanding crypto requests before we start + * failing requests. We need this to prevent DOS when too many + * requests are arriving for us to keep up. Otherwise we will + * run the system out of memory. Since crypto is slow, we are + * usually the bottleneck that needs to say, enough is enough. + * + * We cannot print errors when this condition occurs, we are already too + * slow, printing anything will just kill us + */ + +static int crypto_q_cnt = 0; +module_param(crypto_q_cnt, int, 0444); +MODULE_PARM_DESC(crypto_q_cnt, + "Current number of outstanding crypto requests"); + +static int crypto_q_max = 1000; +module_param(crypto_q_max, int, 0644); +MODULE_PARM_DESC(crypto_q_max, + "Maximum number of outstanding crypto requests"); + +#define bootverbose crypto_verbose +static int crypto_verbose = 0; +module_param(crypto_verbose, int, 0644); +MODULE_PARM_DESC(crypto_verbose, + "Enable verbose crypto startup"); + +int crypto_usercrypto = 1; /* userland may do crypto reqs */ +module_param(crypto_usercrypto, int, 0644); +MODULE_PARM_DESC(crypto_usercrypto, + "Enable/disable user-mode access to crypto support"); + +int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ +module_param(crypto_userasymcrypto, int, 0644); +MODULE_PARM_DESC(crypto_userasymcrypto, + "Enable/disable user-mode access to asymmetric crypto support"); + +int crypto_devallowsoft = 0; /* only use hardware crypto */ +module_param(crypto_devallowsoft, int, 0644); +MODULE_PARM_DESC(crypto_devallowsoft, + "Enable/disable use of software crypto support"); + +/* + * This parameter controls the maximum number of crypto operations to + * do consecutively in the crypto kernel thread before scheduling to allow + * other processes to run. Without it, it is possible to get into a + * situation where the crypto thread never allows any other processes to run. + * Default to 1000 which should be less than one second. + */ +static int crypto_max_loopcount = 1000; +module_param(crypto_max_loopcount, int, 0644); +MODULE_PARM_DESC(crypto_max_loopcount, + "Maximum number of crypto ops to do before yielding to other processes"); + +#ifndef CONFIG_NR_CPUS +#define CONFIG_NR_CPUS 1 +#endif + +static struct task_struct *cryptoproc[CONFIG_NR_CPUS]; +static struct task_struct *cryptoretproc[CONFIG_NR_CPUS]; +static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); +static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); + +static int crypto_proc(void *arg); +static int crypto_ret_proc(void *arg); +static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); +static int crypto_kinvoke(struct cryptkop *krp, int flags); +static void crypto_exit(void); +static int crypto_init(void); + +static struct cryptostats cryptostats; + +static struct cryptocap * +crypto_checkdriver(u_int32_t hid) +{ + if (crypto_drivers == NULL) + return NULL; + return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); +} + +/* + * Compare a driver's list of supported algorithms against another + * list; return non-zero if all algorithms are supported. + */ +static int +driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) +{ + const struct cryptoini *cr; + + /* See if all the algorithms are supported. */ + for (cr = cri; cr; cr = cr->cri_next) + if (cap->cc_alg[cr->cri_alg] == 0) + return 0; + return 1; +} + + +/* + * Select a driver for a new session that supports the specified + * algorithms and, optionally, is constrained according to the flags. + * The algorithm we use here is pretty stupid; just use the + * first driver that supports all the algorithms we need. If there + * are multiple drivers we choose the driver with the fewest active + * sessions. We prefer hardware-backed drivers to software ones. + * + * XXX We need more smarts here (in real life too, but that's + * XXX another story altogether). + */ +static struct cryptocap * +crypto_select_driver(const struct cryptoini *cri, int flags) +{ + struct cryptocap *cap, *best; + int match, hid; + + CRYPTO_DRIVER_ASSERT(); + + /* + * Look first for hardware crypto devices if permitted. + */ + if (flags & CRYPTOCAP_F_HARDWARE) + match = CRYPTOCAP_F_HARDWARE; + else + match = CRYPTOCAP_F_SOFTWARE; + best = NULL; +again: + for (hid = 0; hid < crypto_drivers_num; hid++) { + cap = &crypto_drivers[hid]; + /* + * If it's not initialized, is in the process of + * going away, or is not appropriate (hardware + * or software based on match), then skip. + */ + if (cap->cc_dev == NULL || + (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || + (cap->cc_flags & match) == 0) + continue; + + /* verify all the algorithms are supported. */ + if (driver_suitable(cap, cri)) { + if (best == NULL || + cap->cc_sessions < best->cc_sessions) + best = cap; + } + } + if (best != NULL) + return best; + if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { + /* sort of an Algol 68-style for loop */ + match = CRYPTOCAP_F_SOFTWARE; + goto again; + } + return best; +} + +/* + * Create a new session. The crid argument specifies a crypto + * driver to use or constraints on a driver to select (hardware + * only, software only, either). Whatever driver is selected + * must be capable of the requested crypto algorithms. + */ +int +crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) +{ + struct cryptocap *cap; + u_int32_t hid, lid; + int err; + unsigned long d_flags; + + CRYPTO_DRIVER_LOCK(); + if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { + /* + * Use specified driver; verify it is capable. + */ + cap = crypto_checkdriver(crid); + if (cap != NULL && !driver_suitable(cap, cri)) + cap = NULL; + } else { + /* + * No requested driver; select based on crid flags. + */ + cap = crypto_select_driver(cri, crid); + /* + * if NULL then can't do everything in one session. + * XXX Fix this. We need to inject a "virtual" session + * XXX layer right about here. + */ + } + if (cap != NULL) { + /* Call the driver initialization routine. */ + hid = cap - crypto_drivers; + lid = hid; /* Pass the driver ID. */ + cap->cc_sessions++; + CRYPTO_DRIVER_UNLOCK(); + err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); + CRYPTO_DRIVER_LOCK(); + if (err == 0) { + (*sid) = (cap->cc_flags & 0xff000000) + | (hid & 0x00ffffff); + (*sid) <<= 32; + (*sid) |= (lid & 0xffffffff); + } else + cap->cc_sessions--; + } else + err = EINVAL; + CRYPTO_DRIVER_UNLOCK(); + return err; +} + +static void +crypto_remove(struct cryptocap *cap) +{ + CRYPTO_DRIVER_ASSERT(); + if (cap->cc_sessions == 0 && cap->cc_koperations == 0) + bzero(cap, sizeof(*cap)); +} + +/* + * Delete an existing session (or a reserved session on an unregistered + * driver). + */ +int +crypto_freesession(u_int64_t sid) +{ + struct cryptocap *cap; + u_int32_t hid; + int err = 0; + unsigned long d_flags; + + dprintk("%s()\n", __FUNCTION__); + CRYPTO_DRIVER_LOCK(); + + if (crypto_drivers == NULL) { + err = EINVAL; + goto done; + } + + /* Determine two IDs. */ + hid = CRYPTO_SESID2HID(sid); + + if (hid >= crypto_drivers_num) { + dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); + err = ENOENT; + goto done; + } + cap = &crypto_drivers[hid]; + + if (cap->cc_dev) { + CRYPTO_DRIVER_UNLOCK(); + /* Call the driver cleanup routine, if available, unlocked. */ + err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); + CRYPTO_DRIVER_LOCK(); + } + + if (cap->cc_sessions) + cap->cc_sessions--; + + if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) + crypto_remove(cap); + +done: + CRYPTO_DRIVER_UNLOCK(); + return err; +} + +/* + * Return an unused driver id. Used by drivers prior to registering + * support for the algorithms they handle. + */ +int32_t +crypto_get_driverid(device_t dev, int flags) +{ + struct cryptocap *newdrv; + int i; + unsigned long d_flags; + + if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { + printf("%s: no flags specified when registering driver\n", + device_get_nameunit(dev)); + return -1; + } + + CRYPTO_DRIVER_LOCK(); + + for (i = 0; i < crypto_drivers_num; i++) { + if (crypto_drivers[i].cc_dev == NULL && + (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { + break; + } + } + + /* Out of entries, allocate some more. */ + if (i == crypto_drivers_num) { + /* Be careful about wrap-around. */ + if (2 * crypto_drivers_num <= crypto_drivers_num) { + CRYPTO_DRIVER_UNLOCK(); + printk("crypto: driver count wraparound!\n"); + return -1; + } + + newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), + GFP_KERNEL); + if (newdrv == NULL) { + CRYPTO_DRIVER_UNLOCK(); + printk("crypto: no space to expand driver table!\n"); + return -1; + } + + memcpy(newdrv, crypto_drivers, + crypto_drivers_num * sizeof(struct cryptocap)); + memset(&newdrv[crypto_drivers_num], 0, + crypto_drivers_num * sizeof(struct cryptocap)); + + crypto_drivers_num *= 2; + + kfree(crypto_drivers); + crypto_drivers = newdrv; + } + + /* NB: state is zero'd on free */ + crypto_drivers[i].cc_sessions = 1; /* Mark */ + crypto_drivers[i].cc_dev = dev; + crypto_drivers[i].cc_flags = flags; + if (bootverbose) + printf("crypto: assign %s driver id %u, flags %u\n", + device_get_nameunit(dev), i, flags); + + CRYPTO_DRIVER_UNLOCK(); + + return i; +} + +/* + * Lookup a driver by name. We match against the full device + * name and unit, and against just the name. The latter gives + * us a simple widlcarding by device name. On success return the + * driver/hardware identifier; otherwise return -1. + */ +int +crypto_find_driver(const char *match) +{ + int i, len = strlen(match); + unsigned long d_flags; + + CRYPTO_DRIVER_LOCK(); + for (i = 0; i < crypto_drivers_num; i++) { + device_t dev = crypto_drivers[i].cc_dev; + if (dev == NULL || + (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) + continue; + if (strncmp(match, device_get_nameunit(dev), len) == 0 || + strncmp(match, device_get_name(dev), len) == 0) + break; + } + CRYPTO_DRIVER_UNLOCK(); + return i < crypto_drivers_num ? i : -1; +} + +/* + * Return the device_t for the specified driver or NULL + * if the driver identifier is invalid. + */ +device_t +crypto_find_device_byhid(int hid) +{ + struct cryptocap *cap = crypto_checkdriver(hid); + return cap != NULL ? cap->cc_dev : NULL; +} + +/* + * Return the device/driver capabilities. + */ +int +crypto_getcaps(int hid) +{ + struct cryptocap *cap = crypto_checkdriver(hid); + return cap != NULL ? cap->cc_flags : 0; +} + +/* + * Register support for a key-related algorithm. This routine + * is called once for each algorithm supported a driver. + */ +int +crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) +{ + struct cryptocap *cap; + int err; + unsigned long d_flags; + + dprintk("%s()\n", __FUNCTION__); + CRYPTO_DRIVER_LOCK(); + + cap = crypto_checkdriver(driverid); + if (cap != NULL && + (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { + /* + * XXX Do some performance testing to determine placing. + * XXX We probably need an auxiliary data structure that + * XXX describes relative performances. + */ + + cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; + if (bootverbose) + printf("crypto: %s registers key alg %u flags %u\n" + , device_get_nameunit(cap->cc_dev) + , kalg + , flags + ); + err = 0; + } else + err = EINVAL; + + CRYPTO_DRIVER_UNLOCK(); + return err; +} + +/* + * Register support for a non-key-related algorithm. This routine + * is called once for each such algorithm supported by a driver. + */ +int +crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, + u_int32_t flags) +{ + struct cryptocap *cap; + int err; + unsigned long d_flags; + + dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, + driverid, alg, maxoplen, flags); + + CRYPTO_DRIVER_LOCK(); + + cap = crypto_checkdriver(driverid); + /* NB: algorithms are in the range [1..max] */ + if (cap != NULL && + (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { + /* + * XXX Do some performance testing to determine placing. + * XXX We probably need an auxiliary data structure that + * XXX describes relative performances. + */ + + cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; + cap->cc_max_op_len[alg] = maxoplen; + if (bootverbose) + printf("crypto: %s registers alg %u flags %u maxoplen %u\n" + , device_get_nameunit(cap->cc_dev) + , alg + , flags + , maxoplen + ); + cap->cc_sessions = 0; /* Unmark */ + err = 0; + } else + err = EINVAL; + + CRYPTO_DRIVER_UNLOCK(); + return err; +} + +static void +driver_finis(struct cryptocap *cap) +{ + u_int32_t ses, kops; + + CRYPTO_DRIVER_ASSERT(); + + ses = cap->cc_sessions; + kops = cap->cc_koperations; + bzero(cap, sizeof(*cap)); + if (ses != 0 || kops != 0) { + /* + * If there are pending sessions, + * just mark as invalid. + */ + cap->cc_flags |= CRYPTOCAP_F_CLEANUP; + cap->cc_sessions = ses; + cap->cc_koperations = kops; + } +} + +/* + * Unregister a crypto driver. If there are pending sessions using it, + * leave enough information around so that subsequent calls using those + * sessions will correctly detect the driver has been unregistered and + * reroute requests. + */ +int +crypto_unregister(u_int32_t driverid, int alg) +{ + struct cryptocap *cap; + int i, err; + unsigned long d_flags; + + dprintk("%s()\n", __FUNCTION__); + CRYPTO_DRIVER_LOCK(); + + cap = crypto_checkdriver(driverid); + if (cap != NULL && + (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && + cap->cc_alg[alg] != 0) { + cap->cc_alg[alg] = 0; + cap->cc_max_op_len[alg] = 0; + + /* Was this the last algorithm ? */ + for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) + if (cap->cc_alg[i] != 0) + break; + + if (i == CRYPTO_ALGORITHM_MAX + 1) + driver_finis(cap); + err = 0; + } else + err = EINVAL; + CRYPTO_DRIVER_UNLOCK(); + return err; +} + +/* + * Unregister all algorithms associated with a crypto driver. + * If there are pending sessions using it, leave enough information + * around so that subsequent calls using those sessions will + * correctly detect the driver has been unregistered and reroute + * requests. + */ +int +crypto_unregister_all(u_int32_t driverid) +{ + struct cryptocap *cap; + int err; + unsigned long d_flags; + + dprintk("%s()\n", __FUNCTION__); + CRYPTO_DRIVER_LOCK(); + cap = crypto_checkdriver(driverid); + if (cap != NULL) { + driver_finis(cap); + err = 0; + } else + err = EINVAL; + CRYPTO_DRIVER_UNLOCK(); + + return err; +} + +/* + * Clear blockage on a driver. The what parameter indicates whether + * the driver is now ready for cryptop's and/or cryptokop's. + */ +int +crypto_unblock(u_int32_t driverid, int what) +{ + struct cryptocap *cap; + int err; + unsigned long q_flags; + + CRYPTO_Q_LOCK(); + cap = crypto_checkdriver(driverid); + if (cap != NULL) { + if (what & CRYPTO_SYMQ) { + cap->cc_qblocked = 0; + cap->cc_unqblocked = 0; + crypto_all_qblocked = 0; + } + if (what & CRYPTO_ASYMQ) { + cap->cc_kqblocked = 0; + cap->cc_unkqblocked = 0; + crypto_all_kqblocked = 0; + } + wake_up_interruptible(&cryptoproc_wait); + err = 0; + } else + err = EINVAL; + CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock + + return err; +} + +/* + * Add a crypto request to a queue, to be processed by the kernel thread. + */ +int +crypto_dispatch(struct cryptop *crp) +{ + struct cryptocap *cap; + int result = -1; + unsigned long q_flags; + + dprintk("%s()\n", __FUNCTION__); + + cryptostats.cs_ops++; + + CRYPTO_Q_LOCK(); + if (crypto_q_cnt >= crypto_q_max) { + cryptostats.cs_drops++; + CRYPTO_Q_UNLOCK(); + return ENOMEM; + } + crypto_q_cnt++; + + /* make sure we are starting a fresh run on this crp. */ + crp->crp_flags &= ~CRYPTO_F_DONE; + crp->crp_etype = 0; + + /* + * Caller marked the request to be processed immediately; dispatch + * it directly to the driver unless the driver is currently blocked. + */ + if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { + int hid = CRYPTO_SESID2HID(crp->crp_sid); + cap = crypto_checkdriver(hid); + /* Driver cannot disappear when there is an active session. */ + KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); + if (!cap->cc_qblocked) { + crypto_all_qblocked = 0; + crypto_drivers[hid].cc_unqblocked = 1; + CRYPTO_Q_UNLOCK(); + result = crypto_invoke(cap, crp, 0); + CRYPTO_Q_LOCK(); + if (result == ERESTART) + if (crypto_drivers[hid].cc_unqblocked) + crypto_drivers[hid].cc_qblocked = 1; + crypto_drivers[hid].cc_unqblocked = 0; + } + } + if (result == ERESTART) { + /* + * The driver ran out of resources, mark the + * driver ``blocked'' for cryptop's and put + * the request back in the queue. It would + * best to put the request back where we got + * it but that's hard so for now we put it + * at the front. This should be ok; putting + * it at the end does not work. + */ + list_add(&crp->crp_next, &crp_q); + cryptostats.cs_blocks++; + result = 0; + } else if (result == -1) { + TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); + result = 0; + } + wake_up_interruptible(&cryptoproc_wait); + CRYPTO_Q_UNLOCK(); + return result; +} + +/* + * Add an asymetric crypto request to a queue, + * to be processed by the kernel thread. + */ +int +crypto_kdispatch(struct cryptkop *krp) +{ + int error; + unsigned long q_flags; + + cryptostats.cs_kops++; + + error = crypto_kinvoke(krp, krp->krp_crid); + if (error == ERESTART) { + CRYPTO_Q_LOCK(); + TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); + wake_up_interruptible(&cryptoproc_wait); + CRYPTO_Q_UNLOCK(); + error = 0; + } + return error; +} + +/* + * Verify a driver is suitable for the specified operation. + */ +static __inline int +kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) +{ + return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; +} + +/* + * Select a driver for an asym operation. The driver must + * support the necessary algorithm. The caller can constrain + * which device is selected with the flags parameter. The + * algorithm we use here is pretty stupid; just use the first + * driver that supports the algorithms we need. If there are + * multiple suitable drivers we choose the driver with the + * fewest active operations. We prefer hardware-backed + * drivers to software ones when either may be used. + */ +static struct cryptocap * +crypto_select_kdriver(const struct cryptkop *krp, int flags) +{ + struct cryptocap *cap, *best, *blocked; + int match, hid; + + CRYPTO_DRIVER_ASSERT(); + + /* + * Look first for hardware crypto devices if permitted. + */ + if (flags & CRYPTOCAP_F_HARDWARE) + match = CRYPTOCAP_F_HARDWARE; + else + match = CRYPTOCAP_F_SOFTWARE; + best = NULL; + blocked = NULL; +again: + for (hid = 0; hid < crypto_drivers_num; hid++) { + cap = &crypto_drivers[hid]; + /* + * If it's not initialized, is in the process of + * going away, or is not appropriate (hardware + * or software based on match), then skip. + */ + if (cap->cc_dev == NULL || + (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || + (cap->cc_flags & match) == 0) + continue; + + /* verify all the algorithms are supported. */ + if (kdriver_suitable(cap, krp)) { + if (best == NULL || + cap->cc_koperations < best->cc_koperations) + best = cap; + } + } + if (best != NULL) + return best; + if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { + /* sort of an Algol 68-style for loop */ + match = CRYPTOCAP_F_SOFTWARE; + goto again; + } + return best; +} + +/* + * Dispatch an assymetric crypto request. + */ +static int +crypto_kinvoke(struct cryptkop *krp, int crid) +{ + struct cryptocap *cap = NULL; + int error; + unsigned long d_flags; + + KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); + KASSERT(krp->krp_callback != NULL, + ("%s: krp->crp_callback == NULL", __func__)); + + CRYPTO_DRIVER_LOCK(); + if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { + cap = crypto_checkdriver(crid); + if (cap != NULL) { + /* + * Driver present, it must support the necessary + * algorithm and, if s/w drivers are excluded, + * it must be registered as hardware-backed. + */ + if (!kdriver_suitable(cap, krp) || + (!crypto_devallowsoft && + (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) + cap = NULL; + } + } else { + /* + * No requested driver; select based on crid flags. + */ + if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ + crid &= ~CRYPTOCAP_F_SOFTWARE; + cap = crypto_select_kdriver(krp, crid); + } + if (cap != NULL && !cap->cc_kqblocked) { + krp->krp_hid = cap - crypto_drivers; + cap->cc_koperations++; + CRYPTO_DRIVER_UNLOCK(); + error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); + CRYPTO_DRIVER_LOCK(); + if (error == ERESTART) { + cap->cc_koperations--; + CRYPTO_DRIVER_UNLOCK(); + return (error); + } + /* return the actual device used */ + krp->krp_crid = krp->krp_hid; + } else { + /* + * NB: cap is !NULL if device is blocked; in + * that case return ERESTART so the operation + * is resubmitted if possible. + */ + error = (cap == NULL) ? ENODEV : ERESTART; + } + CRYPTO_DRIVER_UNLOCK(); + + if (error) { + krp->krp_status = error; + crypto_kdone(krp); + } + return 0; +} + + +/* + * Dispatch a crypto request to the appropriate crypto devices. + */ +static int +crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) +{ + KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); + KASSERT(crp->crp_callback != NULL, + ("%s: crp->crp_callback == NULL", __func__)); + KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); + + dprintk("%s()\n", __FUNCTION__); + +#ifdef CRYPTO_TIMING + if (crypto_timing) + crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); +#endif + if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { + struct cryptodesc *crd; + u_int64_t nid; + + /* + * Driver has unregistered; migrate the session and return + * an error to the caller so they'll resubmit the op. + * + * XXX: What if there are more already queued requests for this + * session? + */ + crypto_freesession(crp->crp_sid); + + for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) + crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); + + /* XXX propagate flags from initial session? */ + if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), + CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) + crp->crp_sid = nid; + + crp->crp_etype = EAGAIN; + crypto_done(crp); + return 0; + } else { + /* + * Invoke the driver to process the request. + */ + return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); + } +} + +/* + * Release a set of crypto descriptors. + */ +void +crypto_freereq(struct cryptop *crp) +{ + struct cryptodesc *crd; + + if (crp == NULL) + return; + +#ifdef DIAGNOSTIC + { + struct cryptop *crp2; + unsigned long q_flags; + + CRYPTO_Q_LOCK(); + TAILQ_FOREACH(crp2, &crp_q, crp_next) { + KASSERT(crp2 != crp, + ("Freeing cryptop from the crypto queue (%p).", + crp)); + } + CRYPTO_Q_UNLOCK(); + CRYPTO_RETQ_LOCK(); + TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { + KASSERT(crp2 != crp, + ("Freeing cryptop from the return queue (%p).", + crp)); + } + CRYPTO_RETQ_UNLOCK(); + } +#endif + + while ((crd = crp->crp_desc) != NULL) { + crp->crp_desc = crd->crd_next; + kmem_cache_free(cryptodesc_zone, crd); + } + kmem_cache_free(cryptop_zone, crp); +} + +/* + * Acquire a set of crypto descriptors. + */ +struct cryptop * +crypto_getreq(int num) +{ + struct cryptodesc *crd; + struct cryptop *crp; + + crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); + if (crp != NULL) { + memset(crp, 0, sizeof(*crp)); + INIT_LIST_HEAD(&crp->crp_next); + init_waitqueue_head(&crp->crp_waitq); + while (num--) { + crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); + if (crd == NULL) { + crypto_freereq(crp); + return NULL; + } + memset(crd, 0, sizeof(*crd)); + crd->crd_next = crp->crp_desc; + crp->crp_desc = crd; + } + } + return crp; +} + +/* + * Invoke the callback on behalf of the driver. + */ +void +crypto_done(struct cryptop *crp) +{ + unsigned long q_flags; + + dprintk("%s()\n", __FUNCTION__); + if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { + crp->crp_flags |= CRYPTO_F_DONE; + CRYPTO_Q_LOCK(); + crypto_q_cnt--; + CRYPTO_Q_UNLOCK(); + } else + printk("crypto: crypto_done op already done, flags 0x%x", + crp->crp_flags); + if (crp->crp_etype != 0) + cryptostats.cs_errs++; + /* + * CBIMM means unconditionally do the callback immediately; + * CBIFSYNC means do the callback immediately only if the + * operation was done synchronously. Both are used to avoid + * doing extraneous context switches; the latter is mostly + * used with the software crypto driver. + */ + if ((crp->crp_flags & CRYPTO_F_CBIMM) || + ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && + (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { + /* + * Do the callback directly. This is ok when the + * callback routine does very little (e.g. the + * /dev/crypto callback method just does a wakeup). + */ + crp->crp_callback(crp); + } else { + unsigned long r_flags; + /* + * Normal case; queue the callback for the thread. + */ + CRYPTO_RETQ_LOCK(); + wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ + TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); + CRYPTO_RETQ_UNLOCK(); + } +} + +/* + * Invoke the callback on behalf of the driver. + */ +void +crypto_kdone(struct cryptkop *krp) +{ + struct cryptocap *cap; + unsigned long d_flags; + + if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) + printk("crypto: crypto_kdone op already done, flags 0x%x", + krp->krp_flags); + krp->krp_flags |= CRYPTO_KF_DONE; + if (krp->krp_status != 0) + cryptostats.cs_kerrs++; + + CRYPTO_DRIVER_LOCK(); + /* XXX: What if driver is loaded in the meantime? */ + if (krp->krp_hid < crypto_drivers_num) { + cap = &crypto_drivers[krp->krp_hid]; + cap->cc_koperations--; + KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); + if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) + crypto_remove(cap); + } + CRYPTO_DRIVER_UNLOCK(); + + /* + * CBIMM means unconditionally do the callback immediately; + * This is used to avoid doing extraneous context switches + */ + if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { + /* + * Do the callback directly. This is ok when the + * callback routine does very little (e.g. the + * /dev/crypto callback method just does a wakeup). + */ + krp->krp_callback(krp); + } else { + unsigned long r_flags; + /* + * Normal case; queue the callback for the thread. + */ + CRYPTO_RETQ_LOCK(); + wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ + TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); + CRYPTO_RETQ_UNLOCK(); + } +} + +int +crypto_getfeat(int *featp) +{ + int hid, kalg, feat = 0; + unsigned long d_flags; + + CRYPTO_DRIVER_LOCK(); + for (hid = 0; hid < crypto_drivers_num; hid++) { + const struct cryptocap *cap = &crypto_drivers[hid]; + + if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && + !crypto_devallowsoft) { + continue; + } + for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) + if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) + feat |= 1 << kalg; + } + CRYPTO_DRIVER_UNLOCK(); + *featp = feat; + return (0); +} + +/* + * Crypto thread, dispatches crypto requests. + */ +static int +crypto_proc(void *arg) +{ + struct cryptop *crp, *submit; + struct cryptkop *krp, *krpp; + struct cryptocap *cap; + u_int32_t hid; + int result, hint; + unsigned long q_flags; + int loopcount = 0; + + set_current_state(TASK_INTERRUPTIBLE); + + CRYPTO_Q_LOCK(); + for (;;) { + /* + * we need to make sure we don't get into a busy loop with nothing + * to do, the two crypto_all_*blocked vars help us find out when + * we are all full and can do nothing on any driver or Q. If so we + * wait for an unblock. + */ + crypto_all_qblocked = !list_empty(&crp_q); + + /* + * Find the first element in the queue that can be + * processed and look-ahead to see if multiple ops + * are ready for the same driver. + */ + submit = NULL; + hint = 0; + list_for_each_entry(crp, &crp_q, crp_next) { + hid = CRYPTO_SESID2HID(crp->crp_sid); + cap = crypto_checkdriver(hid); + /* + * Driver cannot disappear when there is an active + * session. + */ + KASSERT(cap != NULL, ("%s:%u Driver disappeared.", + __func__, __LINE__)); + if (cap == NULL || cap->cc_dev == NULL) { + /* Op needs to be migrated, process it. */ + if (submit == NULL) + submit = crp; + break; + } + if (!cap->cc_qblocked) { + if (submit != NULL) { + /* + * We stop on finding another op, + * regardless whether its for the same + * driver or not. We could keep + * searching the queue but it might be + * better to just use a per-driver + * queue instead. + */ + if (CRYPTO_SESID2HID(submit->crp_sid) == hid) + hint = CRYPTO_HINT_MORE; + break; + } else { + submit = crp; + if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) + break; + /* keep scanning for more are q'd */ + } + } + } + if (submit != NULL) { + hid = CRYPTO_SESID2HID(submit->crp_sid); + crypto_all_qblocked = 0; + list_del(&submit->crp_next); + crypto_drivers[hid].cc_unqblocked = 1; + cap = crypto_checkdriver(hid); + CRYPTO_Q_UNLOCK(); + KASSERT(cap != NULL, ("%s:%u Driver disappeared.", + __func__, __LINE__)); + result = crypto_invoke(cap, submit, hint); + CRYPTO_Q_LOCK(); + if (result == ERESTART) { + /* + * The driver ran out of resources, mark the + * driver ``blocked'' for cryptop's and put + * the request back in the queue. It would + * best to put the request back where we got + * it but that's hard so for now we put it + * at the front. This should be ok; putting + * it at the end does not work. + */ + /* XXX validate sid again? */ + list_add(&submit->crp_next, &crp_q); + cryptostats.cs_blocks++; + if (crypto_drivers[hid].cc_unqblocked) + crypto_drivers[hid].cc_qblocked=0; + crypto_drivers[hid].cc_unqblocked=0; + } + crypto_drivers[hid].cc_unqblocked = 0; + } + + crypto_all_kqblocked = !list_empty(&crp_kq); + + /* As above, but for key ops */ + krp = NULL; + list_for_each_entry(krpp, &crp_kq, krp_next) { + cap = crypto_checkdriver(krpp->krp_hid); + if (cap == NULL || cap->cc_dev == NULL) { + /* + * Operation needs to be migrated, invalidate + * the assigned device so it will reselect a + * new one below. Propagate the original + * crid selection flags if supplied. + */ + krp->krp_hid = krp->krp_crid & + (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); + if (krp->krp_hid == 0) + krp->krp_hid = + CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; + break; + } + if (!cap->cc_kqblocked) { + krp = krpp; + break; + } + } + if (krp != NULL) { + crypto_all_kqblocked = 0; + list_del(&krp->krp_next); + crypto_drivers[krp->krp_hid].cc_kqblocked = 1; + CRYPTO_Q_UNLOCK(); + result = crypto_kinvoke(krp, krp->krp_hid); + CRYPTO_Q_LOCK(); + if (result == ERESTART) { + /* + * The driver ran out of resources, mark the + * driver ``blocked'' for cryptkop's and put + * the request back in the queue. It would + * best to put the request back where we got + * it but that's hard so for now we put it + * at the front. This should be ok; putting + * it at the end does not work. + */ + /* XXX validate sid again? */ + list_add(&krp->krp_next, &crp_kq); + cryptostats.cs_kblocks++; + } else + crypto_drivers[krp->krp_hid].cc_kqblocked = 0; + } + + if (submit == NULL && krp == NULL) { + /* + * Nothing more to be processed. Sleep until we're + * woken because there are more ops to process. + * This happens either by submission or by a driver + * becoming unblocked and notifying us through + * crypto_unblock. Note that when we wakeup we + * start processing each queue again from the + * front. It's not clear that it's important to + * preserve this ordering since ops may finish + * out of order if dispatched to different devices + * and some become blocked while others do not. + */ + dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", + __FUNCTION__, + list_empty(&crp_q), crypto_all_qblocked, + list_empty(&crp_kq), crypto_all_kqblocked); + loopcount = 0; + CRYPTO_Q_UNLOCK(); + wait_event_interruptible(cryptoproc_wait, + !(list_empty(&crp_q) || crypto_all_qblocked) || + !(list_empty(&crp_kq) || crypto_all_kqblocked) || + kthread_should_stop()); + if (signal_pending (current)) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + spin_lock_irq(¤t->sigmask_lock); +#endif + flush_signals(current); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + spin_unlock_irq(¤t->sigmask_lock); +#endif + } + CRYPTO_Q_LOCK(); + dprintk("%s - awake\n", __FUNCTION__); + if (kthread_should_stop()) + break; + cryptostats.cs_intrs++; + } else if (loopcount > crypto_max_loopcount) { + /* + * Give other processes a chance to run if we've + * been using the CPU exclusively for a while. + */ + loopcount = 0; + CRYPTO_Q_UNLOCK(); + schedule(); + CRYPTO_Q_LOCK(); + } + loopcount++; + } + CRYPTO_Q_UNLOCK(); + return 0; +} + +/* + * Crypto returns thread, does callbacks for processed crypto requests. + * Callbacks are done here, rather than in the crypto drivers, because + * callbacks typically are expensive and would slow interrupt handling. + */ +static int +crypto_ret_proc(void *arg) +{ + struct cryptop *crpt; + struct cryptkop *krpt; + unsigned long r_flags; + + set_current_state(TASK_INTERRUPTIBLE); + + CRYPTO_RETQ_LOCK(); + for (;;) { + /* Harvest return q's for completed ops */ + crpt = NULL; + if (!list_empty(&crp_ret_q)) + crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); + if (crpt != NULL) + list_del(&crpt->crp_next); + + krpt = NULL; + if (!list_empty(&crp_ret_kq)) + krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); + if (krpt != NULL) + list_del(&krpt->krp_next); + + if (crpt != NULL || krpt != NULL) { + CRYPTO_RETQ_UNLOCK(); + /* + * Run callbacks unlocked. + */ + if (crpt != NULL) + crpt->crp_callback(crpt); + if (krpt != NULL) + krpt->krp_callback(krpt); + CRYPTO_RETQ_LOCK(); + } else { + /* + * Nothing more to be processed. Sleep until we're + * woken because there are more returns to process. + */ + dprintk("%s - sleeping\n", __FUNCTION__); + CRYPTO_RETQ_UNLOCK(); + wait_event_interruptible(cryptoretproc_wait, + !list_empty(&crp_ret_q) || + !list_empty(&crp_ret_kq) || + kthread_should_stop()); + if (signal_pending (current)) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + spin_lock_irq(¤t->sigmask_lock); +#endif + flush_signals(current); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + spin_unlock_irq(¤t->sigmask_lock); +#endif + } + CRYPTO_RETQ_LOCK(); + dprintk("%s - awake\n", __FUNCTION__); + if (kthread_should_stop()) { + dprintk("%s - EXITING!\n", __FUNCTION__); + break; + } + cryptostats.cs_rets++; + } + } + CRYPTO_RETQ_UNLOCK(); + return 0; +} + + +#if 0 /* should put this into /proc or something */ +static void +db_show_drivers(void) +{ + int hid; + + db_printf("%12s %4s %4s %8s %2s %2s\n" + , "Device" + , "Ses" + , "Kops" + , "Flags" + , "QB" + , "KB" + ); + for (hid = 0; hid < crypto_drivers_num; hid++) { + const struct cryptocap *cap = &crypto_drivers[hid]; + if (cap->cc_dev == NULL) + continue; + db_printf("%-12s %4u %4u %08x %2u %2u\n" + , device_get_nameunit(cap->cc_dev) + , cap->cc_sessions + , cap->cc_koperations + , cap->cc_flags + , cap->cc_qblocked + , cap->cc_kqblocked + ); + } +} + +DB_SHOW_COMMAND(crypto, db_show_crypto) +{ + struct cryptop *crp; + + db_show_drivers(); + db_printf("\n"); + + db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", + "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", + "Desc", "Callback"); + TAILQ_FOREACH(crp, &crp_q, crp_next) { + db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" + , (int) CRYPTO_SESID2HID(crp->crp_sid) + , (int) CRYPTO_SESID2CAPS(crp->crp_sid) + , crp->crp_ilen, crp->crp_olen + , crp->crp_etype + , crp->crp_flags + , crp->crp_desc + , crp->crp_callback + ); + } + if (!TAILQ_EMPTY(&crp_ret_q)) { + db_printf("\n%4s %4s %4s %8s\n", + "HID", "Etype", "Flags", "Callback"); + TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { + db_printf("%4u %4u %04x %8p\n" + , (int) CRYPTO_SESID2HID(crp->crp_sid) + , crp->crp_etype + , crp->crp_flags + , crp->crp_callback + ); + } + } +} + +DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) +{ + struct cryptkop *krp; + + db_show_drivers(); + db_printf("\n"); + + db_printf("%4s %5s %4s %4s %8s %4s %8s\n", + "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); + TAILQ_FOREACH(krp, &crp_kq, krp_next) { + db_printf("%4u %5u %4u %4u %08x %4u %8p\n" + , krp->krp_op + , krp->krp_status + , krp->krp_iparams, krp->krp_oparams + , krp->krp_crid, krp->krp_hid + , krp->krp_callback + ); + } + if (!TAILQ_EMPTY(&crp_ret_q)) { + db_printf("%4s %5s %8s %4s %8s\n", + "Op", "Status", "CRID", "HID", "Callback"); + TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { + db_printf("%4u %5u %08x %4u %8p\n" + , krp->krp_op + , krp->krp_status + , krp->krp_crid, krp->krp_hid + , krp->krp_callback + ); + } + } +} +#endif + + +static int +crypto_init(void) +{ + int error; + unsigned long cpu; + + dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); + + if (crypto_initted) + return 0; + crypto_initted = 1; + + spin_lock_init(&crypto_drivers_lock); + spin_lock_init(&crypto_q_lock); + spin_lock_init(&crypto_ret_q_lock); + + cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), + 0, SLAB_HWCACHE_ALIGN, NULL +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) + , NULL +#endif + ); + + cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), + 0, SLAB_HWCACHE_ALIGN, NULL +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) + , NULL +#endif + ); + + if (cryptodesc_zone == NULL || cryptop_zone == NULL) { + printk("crypto: crypto_init cannot setup crypto zones\n"); + error = ENOMEM; + goto bad; + } + + crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; + crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), + GFP_KERNEL); + if (crypto_drivers == NULL) { + printk("crypto: crypto_init cannot setup crypto drivers\n"); + error = ENOMEM; + goto bad; + } + + memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); + + ocf_for_each_cpu(cpu) { + cryptoproc[cpu] = kthread_create(crypto_proc, (void *) cpu, + "ocf_%d", (int) cpu); + if (IS_ERR(cryptoproc[cpu])) { + error = PTR_ERR(cryptoproc[cpu]); + printk("crypto: crypto_init cannot start crypto thread; error %d", + error); + goto bad; + } + kthread_bind(cryptoproc[cpu], cpu); + wake_up_process(cryptoproc[cpu]); + + cryptoretproc[cpu] = kthread_create(crypto_ret_proc, (void *) cpu, + "ocf_ret_%d", (int) cpu); + if (IS_ERR(cryptoretproc[cpu])) { + error = PTR_ERR(cryptoretproc[cpu]); + printk("crypto: crypto_init cannot start cryptoret thread; error %d", + error); + goto bad; + } + kthread_bind(cryptoretproc[cpu], cpu); + wake_up_process(cryptoretproc[cpu]); + } + + return 0; +bad: + crypto_exit(); + return error; +} + + +static void +crypto_exit(void) +{ + int cpu; + + dprintk("%s()\n", __FUNCTION__); + + /* + * Terminate any crypto threads. + */ + ocf_for_each_cpu(cpu) { + kthread_stop(cryptoproc[cpu]); + kthread_stop(cryptoretproc[cpu]); + } + + /* + * Reclaim dynamically allocated resources. + */ + if (crypto_drivers != NULL) + kfree(crypto_drivers); + + if (cryptodesc_zone != NULL) + kmem_cache_destroy(cryptodesc_zone); + if (cryptop_zone != NULL) + kmem_cache_destroy(cryptop_zone); +} + + +EXPORT_SYMBOL(crypto_newsession); +EXPORT_SYMBOL(crypto_freesession); +EXPORT_SYMBOL(crypto_get_driverid); +EXPORT_SYMBOL(crypto_kregister); +EXPORT_SYMBOL(crypto_register); +EXPORT_SYMBOL(crypto_unregister); +EXPORT_SYMBOL(crypto_unregister_all); +EXPORT_SYMBOL(crypto_unblock); +EXPORT_SYMBOL(crypto_dispatch); +EXPORT_SYMBOL(crypto_kdispatch); +EXPORT_SYMBOL(crypto_freereq); +EXPORT_SYMBOL(crypto_getreq); +EXPORT_SYMBOL(crypto_done); +EXPORT_SYMBOL(crypto_kdone); +EXPORT_SYMBOL(crypto_getfeat); +EXPORT_SYMBOL(crypto_userasymcrypto); +EXPORT_SYMBOL(crypto_getcaps); +EXPORT_SYMBOL(crypto_find_driver); +EXPORT_SYMBOL(crypto_find_device_byhid); + +module_init(crypto_init); +module_exit(crypto_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); diff --git a/target/linux/generic/files/crypto/ocf/cryptocteon/Makefile b/target/linux/generic/files/crypto/ocf/cryptocteon/Makefile new file mode 100644 index 0000000..eeed0d6 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/cryptocteon/Makefile @@ -0,0 +1,17 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o + +obj ?= . +EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ + +ifdef CONFIG_OCF_CRYPTOCTEON +# you need the cavium crypto component installed +EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include +endif + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/cryptocteon/README.txt b/target/linux/generic/files/crypto/ocf/cryptocteon/README.txt new file mode 100644 index 0000000..807b2e5 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/cryptocteon/README.txt @@ -0,0 +1,11 @@ + +You will need the CRYPTO package installed to build this driver, and +potentially the ADK. + +cavium_crypto sourced from: + + adk/components/source/cavium_ipsec_kame/cavium_ipsec.c + +and significantly modified to suit use with OCF. All original +copyright/ownership headers retained. + diff --git a/target/linux/generic/files/crypto/ocf/cryptocteon/cavium_crypto.c b/target/linux/generic/files/crypto/ocf/cryptocteon/cavium_crypto.c new file mode 100644 index 0000000..ceaf77c --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/cryptocteon/cavium_crypto.c @@ -0,0 +1,2283 @@ +/* + * Copyright (c) 2009 David McCullough + * + * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Cavium Networks + * 4. Cavium Networks' name may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * This Software, including technical data, may be subject to U.S. export + * control laws, including the U.S. Export Administration Act and its + * associated regulations, and may be subject to export or import regulations + * in other countries. You warrant that You will comply strictly in all + * respects with all such regulations and acknowledge that you have the + * responsibility to obtain licenses to export, re-export or import the + * Software. + * + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND + * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, + * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE + * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR + * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM + * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, + * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF + * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR + * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR + * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. +*/ +/****************************************************************************/ + +#include +#include +#include "octeon-asm.h" + +/****************************************************************************/ + +extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); +extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); + +#define SG_INIT(s, p, i, l) \ + { \ + (i) = 0; \ + (l) = (s)[0].length; \ + (p) = (typeof(p)) sg_virt((s)); \ + CVMX_PREFETCH0((p)); \ + } + +#define SG_CONSUME(s, p, i, l) \ + { \ + (p)++; \ + (l) -= sizeof(*(p)); \ + if ((l) < 0) { \ + dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ + } else if ((l) == 0) { \ + (i)++; \ + (l) = (s)[0].length; \ + (p) = (typeof(p)) sg_virt(s); \ + CVMX_PREFETCH0((p)); \ + } \ + } + +#define ESP_HEADER_LENGTH 8 +#define DES_CBC_IV_LENGTH 8 +#define AES_CBC_IV_LENGTH 16 +#define ESP_HMAC_LEN 12 + +#define ESP_HEADER_LENGTH 8 +#define DES_CBC_IV_LENGTH 8 + +/****************************************************************************/ + +#define CVM_LOAD_SHA_UNIT(dat, next) { \ + if (next == 0) { \ + next = 1; \ + CVMX_MT_HSH_DAT (dat, 0); \ + } else if (next == 1) { \ + next = 2; \ + CVMX_MT_HSH_DAT (dat, 1); \ + } else if (next == 2) { \ + next = 3; \ + CVMX_MT_HSH_DAT (dat, 2); \ + } else if (next == 3) { \ + next = 4; \ + CVMX_MT_HSH_DAT (dat, 3); \ + } else if (next == 4) { \ + next = 5; \ + CVMX_MT_HSH_DAT (dat, 4); \ + } else if (next == 5) { \ + next = 6; \ + CVMX_MT_HSH_DAT (dat, 5); \ + } else if (next == 6) { \ + next = 7; \ + CVMX_MT_HSH_DAT (dat, 6); \ + } else { \ + CVMX_MT_HSH_STARTSHA (dat); \ + next = 0; \ + } \ +} + +#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ + if (next == 0) { \ + CVMX_MT_HSH_DAT (dat1, 0); \ + CVMX_MT_HSH_DAT (dat2, 1); \ + next = 2; \ + } else if (next == 1) { \ + CVMX_MT_HSH_DAT (dat1, 1); \ + CVMX_MT_HSH_DAT (dat2, 2); \ + next = 3; \ + } else if (next == 2) { \ + CVMX_MT_HSH_DAT (dat1, 2); \ + CVMX_MT_HSH_DAT (dat2, 3); \ + next = 4; \ + } else if (next == 3) { \ + CVMX_MT_HSH_DAT (dat1, 3); \ + CVMX_MT_HSH_DAT (dat2, 4); \ + next = 5; \ + } else if (next == 4) { \ + CVMX_MT_HSH_DAT (dat1, 4); \ + CVMX_MT_HSH_DAT (dat2, 5); \ + next = 6; \ + } else if (next == 5) { \ + CVMX_MT_HSH_DAT (dat1, 5); \ + CVMX_MT_HSH_DAT (dat2, 6); \ + next = 7; \ + } else if (next == 6) { \ + CVMX_MT_HSH_DAT (dat1, 6); \ + CVMX_MT_HSH_STARTSHA (dat2); \ + next = 0; \ + } else { \ + CVMX_MT_HSH_STARTSHA (dat1); \ + CVMX_MT_HSH_DAT (dat2, 0); \ + next = 1; \ + } \ +} + +/****************************************************************************/ + +#define CVM_LOAD_MD5_UNIT(dat, next) { \ + if (next == 0) { \ + next = 1; \ + CVMX_MT_HSH_DAT (dat, 0); \ + } else if (next == 1) { \ + next = 2; \ + CVMX_MT_HSH_DAT (dat, 1); \ + } else if (next == 2) { \ + next = 3; \ + CVMX_MT_HSH_DAT (dat, 2); \ + } else if (next == 3) { \ + next = 4; \ + CVMX_MT_HSH_DAT (dat, 3); \ + } else if (next == 4) { \ + next = 5; \ + CVMX_MT_HSH_DAT (dat, 4); \ + } else if (next == 5) { \ + next = 6; \ + CVMX_MT_HSH_DAT (dat, 5); \ + } else if (next == 6) { \ + next = 7; \ + CVMX_MT_HSH_DAT (dat, 6); \ + } else { \ + CVMX_MT_HSH_STARTMD5 (dat); \ + next = 0; \ + } \ +} + +#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ + if (next == 0) { \ + CVMX_MT_HSH_DAT (dat1, 0); \ + CVMX_MT_HSH_DAT (dat2, 1); \ + next = 2; \ + } else if (next == 1) { \ + CVMX_MT_HSH_DAT (dat1, 1); \ + CVMX_MT_HSH_DAT (dat2, 2); \ + next = 3; \ + } else if (next == 2) { \ + CVMX_MT_HSH_DAT (dat1, 2); \ + CVMX_MT_HSH_DAT (dat2, 3); \ + next = 4; \ + } else if (next == 3) { \ + CVMX_MT_HSH_DAT (dat1, 3); \ + CVMX_MT_HSH_DAT (dat2, 4); \ + next = 5; \ + } else if (next == 4) { \ + CVMX_MT_HSH_DAT (dat1, 4); \ + CVMX_MT_HSH_DAT (dat2, 5); \ + next = 6; \ + } else if (next == 5) { \ + CVMX_MT_HSH_DAT (dat1, 5); \ + CVMX_MT_HSH_DAT (dat2, 6); \ + next = 7; \ + } else if (next == 6) { \ + CVMX_MT_HSH_DAT (dat1, 6); \ + CVMX_MT_HSH_STARTMD5 (dat2); \ + next = 0; \ + } else { \ + CVMX_MT_HSH_STARTMD5 (dat1); \ + CVMX_MT_HSH_DAT (dat2, 0); \ + next = 1; \ + } \ +} + +/****************************************************************************/ + +static inline uint64_t +swap64(uint64_t a) +{ + return ((a >> 56) | + (((a >> 48) & 0xfful) << 8) | + (((a >> 40) & 0xfful) << 16) | + (((a >> 32) & 0xfful) << 24) | + (((a >> 24) & 0xfful) << 32) | + (((a >> 16) & 0xfful) << 40) | + (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); +} + +/****************************************************************************/ + +void +octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) +{ + uint8_t hash_key[64]; + uint64_t *key1; + register uint64_t xor1 = 0x3636363636363636ULL; + register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + memset(hash_key, 0, sizeof(hash_key)); + memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); + key1 = (uint64_t *) hash_key; + flags = octeon_crypto_enable(&state); + if (auth) { + CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); + CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); + CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); + } else { + CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); + CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); + } + + CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); + key1++; + if (auth) + CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); + else + CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); + + CVMX_MF_HSH_IV(inner[0], 0); + CVMX_MF_HSH_IV(inner[1], 1); + if (auth) { + inner[2] = 0; + CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); + } + + memset(hash_key, 0, sizeof(hash_key)); + memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); + key1 = (uint64_t *) hash_key; + if (auth) { + CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); + CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); + CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); + } else { + CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); + CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); + } + + CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); + key1++; + CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); + key1++; + if (auth) + CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); + else + CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); + + CVMX_MF_HSH_IV(outer[0], 0); + CVMX_MF_HSH_IV(outer[1], 1); + if (auth) { + outer[2] = 0; + CVMX_MF_HSH_IV(outer[2], 2); + } + octeon_crypto_disable(&state, flags); + return; +} + +/****************************************************************************/ +/* DES functions */ + +int +octo_des_cbc_encrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + uint64_t *data; + int data_i, data_l; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load 3DES Key */ + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + if (od->octo_encklen == 24) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + } else if (od->octo_encklen == 8) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + + CVMX_MT_3DES_IV(* (uint64_t *) ivp); + + while (crypt_off > 0) { + SG_CONSUME(sg, data, data_i, data_l); + crypt_off -= 8; + } + + while (crypt_len > 0) { + CVMX_MT_3DES_ENC_CBC(*data); + CVMX_MF_3DES_RESULT(*data); + SG_CONSUME(sg, data, data_i, data_l); + crypt_len -= 8; + } + + octeon_crypto_disable(&state, flags); + return 0; +} + + +int +octo_des_cbc_decrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + uint64_t *data; + int data_i, data_l; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load 3DES Key */ + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + if (od->octo_encklen == 24) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + } else if (od->octo_encklen == 8) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + + CVMX_MT_3DES_IV(* (uint64_t *) ivp); + + while (crypt_off > 0) { + SG_CONSUME(sg, data, data_i, data_l); + crypt_off -= 8; + } + + while (crypt_len > 0) { + CVMX_MT_3DES_DEC_CBC(*data); + CVMX_MF_3DES_RESULT(*data); + SG_CONSUME(sg, data, data_i, data_l); + crypt_len -= 8; + } + + octeon_crypto_disable(&state, flags); + return 0; +} + +/****************************************************************************/ +/* AES functions */ + +int +octo_aes_cbc_encrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + uint64_t *data, *pdata; + int data_i, data_l; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load AES Key */ + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + + if (od->octo_encklen == 16) { + CVMX_MT_AES_KEY(0x0, 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 24) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 32) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); + + CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); + CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); + + while (crypt_off > 0) { + SG_CONSUME(sg, data, data_i, data_l); + crypt_off -= 8; + } + + while (crypt_len > 0) { + pdata = data; + CVMX_MT_AES_ENC_CBC0(*data); + SG_CONSUME(sg, data, data_i, data_l); + CVMX_MT_AES_ENC_CBC1(*data); + CVMX_MF_AES_RESULT(*pdata, 0); + CVMX_MF_AES_RESULT(*data, 1); + SG_CONSUME(sg, data, data_i, data_l); + crypt_len -= 16; + } + + octeon_crypto_disable(&state, flags); + return 0; +} + + +int +octo_aes_cbc_decrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + uint64_t *data, *pdata; + int data_i, data_l; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load AES Key */ + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + + if (od->octo_encklen == 16) { + CVMX_MT_AES_KEY(0x0, 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 24) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 32) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); + + CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); + CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); + + while (crypt_off > 0) { + SG_CONSUME(sg, data, data_i, data_l); + crypt_off -= 8; + } + + while (crypt_len > 0) { + pdata = data; + CVMX_MT_AES_DEC_CBC0(*data); + SG_CONSUME(sg, data, data_i, data_l); + CVMX_MT_AES_DEC_CBC1(*data); + CVMX_MF_AES_RESULT(*pdata, 0); + CVMX_MF_AES_RESULT(*data, 1); + SG_CONSUME(sg, data, data_i, data_l); + crypt_len -= 16; + } + + octeon_crypto_disable(&state, flags); + return 0; +} + +/****************************************************************************/ +/* MD5 */ + +int +octo_null_md5_encrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + uint64_t *data; + uint64_t tmp1, tmp2; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || + (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data, data_i, data_l); + + flags = octeon_crypto_enable(&state); + + /* Load MD5 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + + while (auth_off > 0) { + SG_CONSUME(sg, data, data_i, data_l); + auth_off -= 8; + } + + while (auth_len > 0) { + CVM_LOAD_MD5_UNIT(*data, next); + auth_len -= 8; + SG_CONSUME(sg, data, data_i, data_l); + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_MD5_UNIT(tmp, next); + } else { + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); + } + CVMX_ES64(tmp1, ((alen + 64) << 3)); + CVM_LOAD_MD5_UNIT(tmp1, next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_ES64(tmp1, ((64 + 16) << 3)); + CVMX_MT_HSH_STARTMD5(tmp1); + + /* save the HMAC */ + SG_INIT(sg, data, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data, data_i, data_l); + icv_off -= 8; + } + CVMX_MF_HSH_IV(*data, 0); + SG_CONSUME(sg, data, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *(uint32_t *)data = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +/****************************************************************************/ +/* SHA1 */ + +int +octo_null_sha1_encrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + uint64_t *data; + uint64_t tmp1, tmp2, tmp3; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || + (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data, data_i, data_l); + + flags = octeon_crypto_enable(&state); + + /* Load SHA1 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + CVMX_MT_HSH_IV(od->octo_hminner[2], 2); + + while (auth_off > 0) { + SG_CONSUME(sg, data, data_i, data_l); + auth_off -= 8; + } + + while (auth_len > 0) { + CVM_LOAD_SHA_UNIT(*data, next); + auth_len -= 8; + SG_CONSUME(sg, data, data_i, data_l); + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_MD5_UNIT(tmp, next); + } else { + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); + } + CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + tmp3 = 0; + CVMX_MF_HSH_IV(tmp3, 2); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + tmp3 |= 0x0000000080000000; + CVMX_MT_HSH_DAT(tmp3, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); + + /* save the HMAC */ + SG_INIT(sg, data, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data, data_i, data_l); + icv_off -= 8; + } + CVMX_MF_HSH_IV(*data, 0); + SG_CONSUME(sg, data, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *(uint32_t *)data = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +/****************************************************************************/ +/* DES MD5 */ + +int +octo_des_cbc_md5_encrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + union { + uint32_t data32[2]; + uint64_t data64[1]; + } mydata; + uint64_t *data = &mydata.data64[0]; + uint32_t *data32; + uint64_t tmp1, tmp2; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || + (crypt_len & 0x7) || + (auth_len & 0x7) || + (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data32, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load 3DES Key */ + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + if (od->octo_encklen == 24) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + } else if (od->octo_encklen == 8) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + + CVMX_MT_3DES_IV(* (uint64_t *) ivp); + + /* Load MD5 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + + while (crypt_off > 0 && auth_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + crypt_off -= 4; + auth_off -= 4; + } + + while (crypt_len > 0 || auth_len > 0) { + uint32_t *first = data32; + mydata.data32[0] = *first; + SG_CONSUME(sg, data32, data_i, data_l); + mydata.data32[1] = *data32; + if (crypt_off <= 0) { + if (crypt_len > 0) { + CVMX_MT_3DES_ENC_CBC(*data); + CVMX_MF_3DES_RESULT(*data); + crypt_len -= 8; + } + } else + crypt_off -= 8; + if (auth_off <= 0) { + if (auth_len > 0) { + CVM_LOAD_MD5_UNIT(*data, next); + auth_len -= 8; + } + } else + auth_off -= 8; + *first = mydata.data32[0]; + *data32 = mydata.data32[1]; + SG_CONSUME(sg, data32, data_i, data_l); + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_MD5_UNIT(tmp, next); + } else { + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); + } + CVMX_ES64(tmp1, ((alen + 64) << 3)); + CVM_LOAD_MD5_UNIT(tmp1, next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_ES64(tmp1, ((64 + 16) << 3)); + CVMX_MT_HSH_STARTMD5(tmp1); + + /* save the HMAC */ + SG_INIT(sg, data32, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + icv_off -= 4; + } + CVMX_MF_HSH_IV(tmp1, 0); + *data32 = (uint32_t) (tmp1 >> 32); + SG_CONSUME(sg, data32, data_i, data_l); + *data32 = (uint32_t) tmp1; + SG_CONSUME(sg, data32, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *data32 = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +int +octo_des_cbc_md5_decrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + union { + uint32_t data32[2]; + uint64_t data64[1]; + } mydata; + uint64_t *data = &mydata.data64[0]; + uint32_t *data32; + uint64_t tmp1, tmp2; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || + (crypt_len & 0x7) || + (auth_len & 0x7) || + (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data32, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load 3DES Key */ + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + if (od->octo_encklen == 24) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + } else if (od->octo_encklen == 8) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + + CVMX_MT_3DES_IV(* (uint64_t *) ivp); + + /* Load MD5 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + + while (crypt_off > 0 && auth_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + crypt_off -= 4; + auth_off -= 4; + } + + while (crypt_len > 0 || auth_len > 0) { + uint32_t *first = data32; + mydata.data32[0] = *first; + SG_CONSUME(sg, data32, data_i, data_l); + mydata.data32[1] = *data32; + if (auth_off <= 0) { + if (auth_len > 0) { + CVM_LOAD_MD5_UNIT(*data, next); + auth_len -= 8; + } + } else + auth_off -= 8; + if (crypt_off <= 0) { + if (crypt_len > 0) { + CVMX_MT_3DES_DEC_CBC(*data); + CVMX_MF_3DES_RESULT(*data); + crypt_len -= 8; + } + } else + crypt_off -= 8; + *first = mydata.data32[0]; + *data32 = mydata.data32[1]; + SG_CONSUME(sg, data32, data_i, data_l); + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_MD5_UNIT(tmp, next); + } else { + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); + } + CVMX_ES64(tmp1, ((alen + 64) << 3)); + CVM_LOAD_MD5_UNIT(tmp1, next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_ES64(tmp1, ((64 + 16) << 3)); + CVMX_MT_HSH_STARTMD5(tmp1); + + /* save the HMAC */ + SG_INIT(sg, data32, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + icv_off -= 4; + } + CVMX_MF_HSH_IV(tmp1, 0); + *data32 = (uint32_t) (tmp1 >> 32); + SG_CONSUME(sg, data32, data_i, data_l); + *data32 = (uint32_t) tmp1; + SG_CONSUME(sg, data32, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *data32 = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +/****************************************************************************/ +/* DES SHA */ + +int +octo_des_cbc_sha1_encrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + union { + uint32_t data32[2]; + uint64_t data64[1]; + } mydata; + uint64_t *data = &mydata.data64[0]; + uint32_t *data32; + uint64_t tmp1, tmp2, tmp3; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || + (crypt_len & 0x7) || + (auth_len & 0x7) || + (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data32, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load 3DES Key */ + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + if (od->octo_encklen == 24) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + } else if (od->octo_encklen == 8) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + + CVMX_MT_3DES_IV(* (uint64_t *) ivp); + + /* Load SHA1 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + CVMX_MT_HSH_IV(od->octo_hminner[2], 2); + + while (crypt_off > 0 && auth_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + crypt_off -= 4; + auth_off -= 4; + } + + while (crypt_len > 0 || auth_len > 0) { + uint32_t *first = data32; + mydata.data32[0] = *first; + SG_CONSUME(sg, data32, data_i, data_l); + mydata.data32[1] = *data32; + if (crypt_off <= 0) { + if (crypt_len > 0) { + CVMX_MT_3DES_ENC_CBC(*data); + CVMX_MF_3DES_RESULT(*data); + crypt_len -= 8; + } + } else + crypt_off -= 8; + if (auth_off <= 0) { + if (auth_len > 0) { + CVM_LOAD_SHA_UNIT(*data, next); + auth_len -= 8; + } + } else + auth_off -= 8; + *first = mydata.data32[0]; + *data32 = mydata.data32[1]; + SG_CONSUME(sg, data32, data_i, data_l); + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_SHA_UNIT(tmp, next); + } else { + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); + } + CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + tmp3 = 0; + CVMX_MF_HSH_IV(tmp3, 2); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + tmp3 |= 0x0000000080000000; + CVMX_MT_HSH_DAT(tmp3, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); + + /* save the HMAC */ + SG_INIT(sg, data32, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + icv_off -= 4; + } + CVMX_MF_HSH_IV(tmp1, 0); + *data32 = (uint32_t) (tmp1 >> 32); + SG_CONSUME(sg, data32, data_i, data_l); + *data32 = (uint32_t) tmp1; + SG_CONSUME(sg, data32, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *data32 = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +int +octo_des_cbc_sha1_decrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + union { + uint32_t data32[2]; + uint64_t data64[1]; + } mydata; + uint64_t *data = &mydata.data64[0]; + uint32_t *data32; + uint64_t tmp1, tmp2, tmp3; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || + (crypt_len & 0x7) || + (auth_len & 0x7) || + (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data32, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load 3DES Key */ + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + if (od->octo_encklen == 24) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + } else if (od->octo_encklen == 8) { + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); + CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + + CVMX_MT_3DES_IV(* (uint64_t *) ivp); + + /* Load SHA1 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + CVMX_MT_HSH_IV(od->octo_hminner[2], 2); + + while (crypt_off > 0 && auth_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + crypt_off -= 4; + auth_off -= 4; + } + + while (crypt_len > 0 || auth_len > 0) { + uint32_t *first = data32; + mydata.data32[0] = *first; + SG_CONSUME(sg, data32, data_i, data_l); + mydata.data32[1] = *data32; + if (auth_off <= 0) { + if (auth_len > 0) { + CVM_LOAD_SHA_UNIT(*data, next); + auth_len -= 8; + } + } else + auth_off -= 8; + if (crypt_off <= 0) { + if (crypt_len > 0) { + CVMX_MT_3DES_DEC_CBC(*data); + CVMX_MF_3DES_RESULT(*data); + crypt_len -= 8; + } + } else + crypt_off -= 8; + *first = mydata.data32[0]; + *data32 = mydata.data32[1]; + SG_CONSUME(sg, data32, data_i, data_l); + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_SHA_UNIT(tmp, next); + } else { + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); + } + CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + tmp3 = 0; + CVMX_MF_HSH_IV(tmp3, 2); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + tmp3 |= 0x0000000080000000; + CVMX_MT_HSH_DAT(tmp3, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); + /* save the HMAC */ + SG_INIT(sg, data32, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + icv_off -= 4; + } + CVMX_MF_HSH_IV(tmp1, 0); + *data32 = (uint32_t) (tmp1 >> 32); + SG_CONSUME(sg, data32, data_i, data_l); + *data32 = (uint32_t) tmp1; + SG_CONSUME(sg, data32, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *data32 = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +/****************************************************************************/ +/* AES MD5 */ + +int +octo_aes_cbc_md5_encrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + union { + uint32_t data32[2]; + uint64_t data64[1]; + } mydata[2]; + uint64_t *pdata = &mydata[0].data64[0]; + uint64_t *data = &mydata[1].data64[0]; + uint32_t *data32; + uint64_t tmp1, tmp2; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || + (crypt_len & 0x7) || + (auth_len & 0x7) || + (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data32, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load AES Key */ + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + + if (od->octo_encklen == 16) { + CVMX_MT_AES_KEY(0x0, 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 24) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 32) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); + + CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); + CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); + + /* Load MD5 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + + while (crypt_off > 0 && auth_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + crypt_off -= 4; + auth_off -= 4; + } + + /* align auth and crypt */ + while (crypt_off > 0 && auth_len > 0) { + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + CVM_LOAD_MD5_UNIT(*pdata, next); + crypt_off -= 8; + auth_len -= 8; + } + + while (crypt_len > 0) { + uint32_t *pdata32[3]; + + pdata32[0] = data32; + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + + pdata32[1] = data32; + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + + pdata32[2] = data32; + mydata[1].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + + mydata[1].data32[1] = *data32; + + CVMX_MT_AES_ENC_CBC0(*pdata); + CVMX_MT_AES_ENC_CBC1(*data); + CVMX_MF_AES_RESULT(*pdata, 0); + CVMX_MF_AES_RESULT(*data, 1); + crypt_len -= 16; + + if (auth_len > 0) { + CVM_LOAD_MD5_UNIT(*pdata, next); + auth_len -= 8; + } + if (auth_len > 0) { + CVM_LOAD_MD5_UNIT(*data, next); + auth_len -= 8; + } + + *pdata32[0] = mydata[0].data32[0]; + *pdata32[1] = mydata[0].data32[1]; + *pdata32[2] = mydata[1].data32[0]; + *data32 = mydata[1].data32[1]; + + SG_CONSUME(sg, data32, data_i, data_l); + } + + /* finish any left over hashing */ + while (auth_len > 0) { + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + CVM_LOAD_MD5_UNIT(*pdata, next); + auth_len -= 8; + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_MD5_UNIT(tmp, next); + } else { + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); + } + CVMX_ES64(tmp1, ((alen + 64) << 3)); + CVM_LOAD_MD5_UNIT(tmp1, next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_ES64(tmp1, ((64 + 16) << 3)); + CVMX_MT_HSH_STARTMD5(tmp1); + + /* save the HMAC */ + SG_INIT(sg, data32, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + icv_off -= 4; + } + CVMX_MF_HSH_IV(tmp1, 0); + *data32 = (uint32_t) (tmp1 >> 32); + SG_CONSUME(sg, data32, data_i, data_l); + *data32 = (uint32_t) tmp1; + SG_CONSUME(sg, data32, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *data32 = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +int +octo_aes_cbc_md5_decrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + union { + uint32_t data32[2]; + uint64_t data64[1]; + } mydata[2]; + uint64_t *pdata = &mydata[0].data64[0]; + uint64_t *data = &mydata[1].data64[0]; + uint32_t *data32; + uint64_t tmp1, tmp2; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || + (crypt_len & 0x7) || + (auth_len & 0x7) || + (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data32, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load AES Key */ + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + + if (od->octo_encklen == 16) { + CVMX_MT_AES_KEY(0x0, 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 24) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 32) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); + + CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); + CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); + + /* Load MD5 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + + while (crypt_off > 0 && auth_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + crypt_off -= 4; + auth_off -= 4; + } + + /* align auth and crypt */ + while (crypt_off > 0 && auth_len > 0) { + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + CVM_LOAD_MD5_UNIT(*pdata, next); + crypt_off -= 8; + auth_len -= 8; + } + + while (crypt_len > 0) { + uint32_t *pdata32[3]; + + pdata32[0] = data32; + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + pdata32[1] = data32; + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + pdata32[2] = data32; + mydata[1].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[1].data32[1] = *data32; + + if (auth_len > 0) { + CVM_LOAD_MD5_UNIT(*pdata, next); + auth_len -= 8; + } + + if (auth_len > 0) { + CVM_LOAD_MD5_UNIT(*data, next); + auth_len -= 8; + } + + CVMX_MT_AES_DEC_CBC0(*pdata); + CVMX_MT_AES_DEC_CBC1(*data); + CVMX_MF_AES_RESULT(*pdata, 0); + CVMX_MF_AES_RESULT(*data, 1); + crypt_len -= 16; + + *pdata32[0] = mydata[0].data32[0]; + *pdata32[1] = mydata[0].data32[1]; + *pdata32[2] = mydata[1].data32[0]; + *data32 = mydata[1].data32[1]; + + SG_CONSUME(sg, data32, data_i, data_l); + } + + /* finish left over hash if any */ + while (auth_len > 0) { + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + CVM_LOAD_MD5_UNIT(*pdata, next); + auth_len -= 8; + } + + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_MD5_UNIT(tmp, next); + } else { + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); + } + CVMX_ES64(tmp1, ((alen + 64) << 3)); + CVM_LOAD_MD5_UNIT(tmp1, next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_ES64(tmp1, ((64 + 16) << 3)); + CVMX_MT_HSH_STARTMD5(tmp1); + + /* save the HMAC */ + SG_INIT(sg, data32, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + icv_off -= 4; + } + CVMX_MF_HSH_IV(tmp1, 0); + *data32 = (uint32_t) (tmp1 >> 32); + SG_CONSUME(sg, data32, data_i, data_l); + *data32 = (uint32_t) tmp1; + SG_CONSUME(sg, data32, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *data32 = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +/****************************************************************************/ +/* AES SHA1 */ + +int +octo_aes_cbc_sha1_encrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + union { + uint32_t data32[2]; + uint64_t data64[1]; + } mydata[2]; + uint64_t *pdata = &mydata[0].data64[0]; + uint64_t *data = &mydata[1].data64[0]; + uint32_t *data32; + uint64_t tmp1, tmp2, tmp3; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", + __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || + (crypt_len & 0x7) || + (auth_len & 0x7) || + (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data32, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load AES Key */ + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + + if (od->octo_encklen == 16) { + CVMX_MT_AES_KEY(0x0, 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 24) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 32) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); + + CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); + CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); + + /* Load SHA IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + CVMX_MT_HSH_IV(od->octo_hminner[2], 2); + + while (crypt_off > 0 && auth_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + crypt_off -= 4; + auth_off -= 4; + } + + /* align auth and crypt */ + while (crypt_off > 0 && auth_len > 0) { + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + CVM_LOAD_SHA_UNIT(*pdata, next); + crypt_off -= 8; + auth_len -= 8; + } + + while (crypt_len > 0) { + uint32_t *pdata32[3]; + + pdata32[0] = data32; + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + pdata32[1] = data32; + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + pdata32[2] = data32; + mydata[1].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[1].data32[1] = *data32; + + CVMX_MT_AES_ENC_CBC0(*pdata); + CVMX_MT_AES_ENC_CBC1(*data); + CVMX_MF_AES_RESULT(*pdata, 0); + CVMX_MF_AES_RESULT(*data, 1); + crypt_len -= 16; + + if (auth_len > 0) { + CVM_LOAD_SHA_UNIT(*pdata, next); + auth_len -= 8; + } + if (auth_len > 0) { + CVM_LOAD_SHA_UNIT(*data, next); + auth_len -= 8; + } + + *pdata32[0] = mydata[0].data32[0]; + *pdata32[1] = mydata[0].data32[1]; + *pdata32[2] = mydata[1].data32[0]; + *data32 = mydata[1].data32[1]; + + SG_CONSUME(sg, data32, data_i, data_l); + } + + /* finish and hashing */ + while (auth_len > 0) { + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + CVM_LOAD_SHA_UNIT(*pdata, next); + auth_len -= 8; + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_SHA_UNIT(tmp, next); + } else { + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); + } + CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + tmp3 = 0; + CVMX_MF_HSH_IV(tmp3, 2); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + tmp3 |= 0x0000000080000000; + CVMX_MT_HSH_DAT(tmp3, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_MD5_UNIT(tmp, next); + } else { + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); +#endif + + /* save the HMAC */ + SG_INIT(sg, data32, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + icv_off -= 4; + } + CVMX_MF_HSH_IV(tmp1, 0); + *data32 = (uint32_t) (tmp1 >> 32); + SG_CONSUME(sg, data32, data_i, data_l); + *data32 = (uint32_t) tmp1; + SG_CONSUME(sg, data32, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *data32 = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +int +octo_aes_cbc_sha1_decrypt( + struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp) +{ + register int next = 0; + union { + uint32_t data32[2]; + uint64_t data64[1]; + } mydata[2]; + uint64_t *pdata = &mydata[0].data64[0]; + uint64_t *data = &mydata[1].data64[0]; + uint32_t *data32; + uint64_t tmp1, tmp2, tmp3; + int data_i, data_l, alen = auth_len; + struct octeon_cop2_state state; + unsigned long flags; + + dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", + __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); + + if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || + (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || + (crypt_len & 0x7) || + (auth_len & 0x7) || + (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { + dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " + "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " + "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + return -EINVAL; + } + + SG_INIT(sg, data32, data_i, data_l); + + CVMX_PREFETCH0(ivp); + CVMX_PREFETCH0(od->octo_enckey); + + flags = octeon_crypto_enable(&state); + + /* load AES Key */ + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); + + if (od->octo_encklen == 16) { + CVMX_MT_AES_KEY(0x0, 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 24) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(0x0, 3); + } else if (od->octo_encklen == 32) { + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); + CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); + } else { + octeon_crypto_disable(&state, flags); + dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); + return -EINVAL; + } + CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); + + CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); + CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); + + /* Load SHA1 IV */ + CVMX_MT_HSH_IV(od->octo_hminner[0], 0); + CVMX_MT_HSH_IV(od->octo_hminner[1], 1); + CVMX_MT_HSH_IV(od->octo_hminner[2], 2); + + while (crypt_off > 0 && auth_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + crypt_off -= 4; + auth_off -= 4; + } + + /* align auth and crypt */ + while (crypt_off > 0 && auth_len > 0) { + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + CVM_LOAD_SHA_UNIT(*pdata, next); + crypt_off -= 8; + auth_len -= 8; + } + + while (crypt_len > 0) { + uint32_t *pdata32[3]; + + pdata32[0] = data32; + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + pdata32[1] = data32; + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + pdata32[2] = data32; + mydata[1].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[1].data32[1] = *data32; + + if (auth_len > 0) { + CVM_LOAD_SHA_UNIT(*pdata, next); + auth_len -= 8; + } + if (auth_len > 0) { + CVM_LOAD_SHA_UNIT(*data, next); + auth_len -= 8; + } + + CVMX_MT_AES_DEC_CBC0(*pdata); + CVMX_MT_AES_DEC_CBC1(*data); + CVMX_MF_AES_RESULT(*pdata, 0); + CVMX_MF_AES_RESULT(*data, 1); + crypt_len -= 16; + + *pdata32[0] = mydata[0].data32[0]; + *pdata32[1] = mydata[0].data32[1]; + *pdata32[2] = mydata[1].data32[0]; + *data32 = mydata[1].data32[1]; + + SG_CONSUME(sg, data32, data_i, data_l); + } + + /* finish and leftover hashing */ + while (auth_len > 0) { + mydata[0].data32[0] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + mydata[0].data32[1] = *data32; + SG_CONSUME(sg, data32, data_i, data_l); + CVM_LOAD_SHA_UNIT(*pdata, next); + auth_len -= 8; + } + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_SHA_UNIT(tmp, next); + } else { + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); +#endif + + /* Finish Inner hash */ + while (next != 7) { + CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); + } + CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); + + /* Get the inner hash of HMAC */ + CVMX_MF_HSH_IV(tmp1, 0); + CVMX_MF_HSH_IV(tmp2, 1); + tmp3 = 0; + CVMX_MF_HSH_IV(tmp3, 2); + + /* Initialize hash unit */ + CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); + CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); + CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); + + CVMX_MT_HSH_DAT(tmp1, 0); + CVMX_MT_HSH_DAT(tmp2, 1); + tmp3 |= 0x0000000080000000; + CVMX_MT_HSH_DAT(tmp3, 2); + CVMX_MT_HSH_DATZ(3); + CVMX_MT_HSH_DATZ(4); + CVMX_MT_HSH_DATZ(5); + CVMX_MT_HSH_DATZ(6); + CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); + + /* finish the hash */ + CVMX_PREFETCH0(od->octo_hmouter); +#if 0 + if (unlikely(inplen)) { + uint64_t tmp = 0; + uint8_t *p = (uint8_t *) & tmp; + p[inplen] = 0x80; + do { + inplen--; + p[inplen] = ((uint8_t *) data)[inplen]; + } while (inplen); + CVM_LOAD_MD5_UNIT(tmp, next); + } else { + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); + } +#else + CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); +#endif + + /* save the HMAC */ + SG_INIT(sg, data32, data_i, data_l); + while (icv_off > 0) { + SG_CONSUME(sg, data32, data_i, data_l); + icv_off -= 4; + } + CVMX_MF_HSH_IV(tmp1, 0); + *data32 = (uint32_t) (tmp1 >> 32); + SG_CONSUME(sg, data32, data_i, data_l); + *data32 = (uint32_t) tmp1; + SG_CONSUME(sg, data32, data_i, data_l); + CVMX_MF_HSH_IV(tmp1, 1); + *data32 = (uint32_t) (tmp1 >> 32); + + octeon_crypto_disable(&state, flags); + return 0; +} + +/****************************************************************************/ diff --git a/target/linux/generic/files/crypto/ocf/cryptocteon/cryptocteon.c b/target/linux/generic/files/crypto/ocf/cryptocteon/cryptocteon.c new file mode 100644 index 0000000..e084c6b --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/cryptocteon/cryptocteon.c @@ -0,0 +1,576 @@ +/* + * Octeon Crypto for OCF + * + * Written by David McCullough + * Copyright (C) 2009-2010 David McCullough + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + * --------------------------------------------------------------------------- + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct { + softc_device_decl sc_dev; +} octo_softc; + +#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) + +struct octo_sess { + int octo_encalg; + #define MAX_CIPHER_KEYLEN 64 + char octo_enckey[MAX_CIPHER_KEYLEN]; + int octo_encklen; + + int octo_macalg; + #define MAX_HASH_KEYLEN 64 + char octo_mackey[MAX_HASH_KEYLEN]; + int octo_macklen; + int octo_mackey_set; + + int octo_mlen; + int octo_ivsize; + + int (*octo_encrypt)(struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp); + int (*octo_decrypt)(struct octo_sess *od, + struct scatterlist *sg, int sg_len, + int auth_off, int auth_len, + int crypt_off, int crypt_len, + int icv_off, uint8_t *ivp); + + uint64_t octo_hminner[3]; + uint64_t octo_hmouter[3]; +}; + +int32_t octo_id = -1; +module_param(octo_id, int, 0444); +MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); + +static struct octo_sess **octo_sessions = NULL; +static u_int32_t octo_sesnum = 0; + +static int octo_process(device_t, struct cryptop *, int); +static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); +static int octo_freesession(device_t, u_int64_t); + +static device_method_t octo_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, octo_newsession), + DEVMETHOD(cryptodev_freesession,octo_freesession), + DEVMETHOD(cryptodev_process, octo_process), +}; + +#define debug octo_debug +int octo_debug = 0; +module_param(octo_debug, int, 0644); +MODULE_PARM_DESC(octo_debug, "Enable debug"); + + +#include "cavium_crypto.c" + + +/* + * Generate a new octo session. We artifically limit it to a single + * hash/cipher or hash-cipher combo just to make it easier, most callers + * do not expect more than this anyway. + */ +static int +octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) +{ + struct cryptoini *c, *encini = NULL, *macini = NULL; + struct octo_sess **ocd; + int i; + + dprintk("%s()\n", __FUNCTION__); + if (sid == NULL || cri == NULL) { + dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + /* + * To keep it simple, we only handle hash, cipher or hash/cipher in a + * session, you cannot currently do multiple ciphers/hashes in one + * session even though it would be possibel to code this driver to + * handle it. + */ + for (i = 0, c = cri; c && i < 2; i++) { + if (c->cri_alg == CRYPTO_MD5_HMAC || + c->cri_alg == CRYPTO_SHA1_HMAC || + c->cri_alg == CRYPTO_NULL_HMAC) { + if (macini) { + break; + } + macini = c; + } + if (c->cri_alg == CRYPTO_DES_CBC || + c->cri_alg == CRYPTO_3DES_CBC || + c->cri_alg == CRYPTO_AES_CBC || + c->cri_alg == CRYPTO_NULL_CBC) { + if (encini) { + break; + } + encini = c; + } + c = c->cri_next; + } + if (!macini && !encini) { + dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", + __FILE__, __LINE__); + return EINVAL; + } + if (c) { + dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", + __FILE__, __LINE__); + return EINVAL; + } + + /* + * So we have something we can do, lets setup the session + */ + + if (octo_sessions) { + for (i = 1; i < octo_sesnum; i++) + if (octo_sessions[i] == NULL) + break; + } else + i = 1; /* NB: to silence compiler warning */ + + if (octo_sessions == NULL || i == octo_sesnum) { + if (octo_sessions == NULL) { + i = 1; /* We leave octo_sessions[0] empty */ + octo_sesnum = CRYPTO_SW_SESSIONS; + } else + octo_sesnum *= 2; + + ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); + if (ocd == NULL) { + /* Reset session number */ + if (octo_sesnum == CRYPTO_SW_SESSIONS) + octo_sesnum = 0; + else + octo_sesnum /= 2; + dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); + return ENOBUFS; + } + memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); + + /* Copy existing sessions */ + if (octo_sessions) { + memcpy(ocd, octo_sessions, + (octo_sesnum / 2) * sizeof(struct octo_sess *)); + kfree(octo_sessions); + } + + octo_sessions = ocd; + } + + ocd = &octo_sessions[i]; + *sid = i; + + + *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); + if (*ocd == NULL) { + octo_freesession(NULL, i); + dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); + return ENOBUFS; + } + memset(*ocd, 0, sizeof(struct octo_sess)); + + if (encini && encini->cri_key) { + (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; + memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); + } + + if (macini && macini->cri_key) { + (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; + memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); + } + + (*ocd)->octo_mlen = 0; + if (encini && encini->cri_mlen) + (*ocd)->octo_mlen = encini->cri_mlen; + else if (macini && macini->cri_mlen) + (*ocd)->octo_mlen = macini->cri_mlen; + else + (*ocd)->octo_mlen = 12; + + /* + * point c at the enc if it exists, otherwise the mac + */ + c = encini ? encini : macini; + + switch (c->cri_alg) { + case CRYPTO_DES_CBC: + case CRYPTO_3DES_CBC: + (*ocd)->octo_ivsize = 8; + switch (macini ? macini->cri_alg : -1) { + case CRYPTO_MD5_HMAC: + (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; + (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; + octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, + (*ocd)->octo_hmouter); + break; + case CRYPTO_SHA1_HMAC: + (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; + (*ocd)->octo_decrypt = octo_des_cbc_sha1_decrypt; + octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, + (*ocd)->octo_hmouter); + break; + case -1: + (*ocd)->octo_encrypt = octo_des_cbc_encrypt; + (*ocd)->octo_decrypt = octo_des_cbc_decrypt; + break; + default: + octo_freesession(NULL, i); + dprintk("%s,%d: EINVALn", __FILE__, __LINE__); + return EINVAL; + } + break; + case CRYPTO_AES_CBC: + (*ocd)->octo_ivsize = 16; + switch (macini ? macini->cri_alg : -1) { + case CRYPTO_MD5_HMAC: + (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; + (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; + octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, + (*ocd)->octo_hmouter); + break; + case CRYPTO_SHA1_HMAC: + (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; + (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; + octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, + (*ocd)->octo_hmouter); + break; + case -1: + (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; + (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; + break; + default: + octo_freesession(NULL, i); + dprintk("%s,%d: EINVALn", __FILE__, __LINE__); + return EINVAL; + } + break; + case CRYPTO_MD5_HMAC: + (*ocd)->octo_encrypt = octo_null_md5_encrypt; + (*ocd)->octo_decrypt = octo_null_md5_encrypt; /* encrypt == decrypt */ + octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, + (*ocd)->octo_hmouter); + break; + case CRYPTO_SHA1_HMAC: + (*ocd)->octo_encrypt = octo_null_sha1_encrypt; + (*ocd)->octo_decrypt = octo_null_sha1_encrypt; /* encrypt == decrypt */ + octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, + (*ocd)->octo_hmouter); + break; + default: + octo_freesession(NULL, i); + dprintk("%s,%d: EINVALn", __FILE__, __LINE__); + return EINVAL; + } + + (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; + (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; + + return 0; +} + +/* + * Free a session. + */ +static int +octo_freesession(device_t dev, u_int64_t tid) +{ + u_int32_t sid = CRYPTO_SESID2LID(tid); + + dprintk("%s()\n", __FUNCTION__); + if (sid > octo_sesnum || octo_sessions == NULL || + octo_sessions[sid] == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return(EINVAL); + } + + /* Silently accept and return */ + if (sid == 0) + return(0); + + if (octo_sessions[sid]) + kfree(octo_sessions[sid]); + octo_sessions[sid] = NULL; + return 0; +} + +/* + * Process a request. + */ +static int +octo_process(device_t dev, struct cryptop *crp, int hint) +{ + struct cryptodesc *crd; + struct octo_sess *od; + u_int32_t lid; +#define SCATTERLIST_MAX 16 + struct scatterlist sg[SCATTERLIST_MAX]; + int sg_num, sg_len; + struct sk_buff *skb = NULL; + struct uio *uiop = NULL; + struct cryptodesc *enccrd = NULL, *maccrd = NULL; + unsigned char *ivp = NULL; + unsigned char iv_data[HASH_MAX_LEN]; + int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; + + dprintk("%s()\n", __FUNCTION__); + /* Sanity check */ + if (crp == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + crp->crp_etype = 0; + + if (crp->crp_desc == NULL || crp->crp_buf == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + crp->crp_etype = EINVAL; + goto done; + } + + lid = crp->crp_sid & 0xffffffff; + if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || + octo_sessions[lid] == NULL) { + crp->crp_etype = ENOENT; + dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); + goto done; + } + od = octo_sessions[lid]; + + /* + * do some error checking outside of the loop for SKB and IOV processing + * this leaves us with valid skb or uiop pointers for later + */ + if (crp->crp_flags & CRYPTO_F_SKBUF) { + skb = (struct sk_buff *) crp->crp_buf; + if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { + printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, + skb_shinfo(skb)->nr_frags); + goto done; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + uiop = (struct uio *) crp->crp_buf; + if (uiop->uio_iovcnt > SCATTERLIST_MAX) { + printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, + uiop->uio_iovcnt); + goto done; + } + } + + /* point our enccrd and maccrd appropriately */ + crd = crp->crp_desc; + if (crd->crd_alg == od->octo_encalg) enccrd = crd; + if (crd->crd_alg == od->octo_macalg) maccrd = crd; + crd = crd->crd_next; + if (crd) { + if (crd->crd_alg == od->octo_encalg) enccrd = crd; + if (crd->crd_alg == od->octo_macalg) maccrd = crd; + crd = crd->crd_next; + } + if (crd) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: ENOENT - descriptors do not match session\n", + __FILE__, __LINE__); + goto done; + } + + if (enccrd) { + if (enccrd->crd_flags & CRD_F_ENCRYPT) { + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) + ivp = enccrd->crd_iv; + else + read_random((ivp = iv_data), od->octo_ivsize); + if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) + crypto_copyback(crp->crp_flags, crp->crp_buf, + enccrd->crd_inject, od->octo_ivsize, ivp); + } else { + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { + ivp = enccrd->crd_iv; + } else { + ivp = iv_data; + crypto_copydata(crp->crp_flags, crp->crp_buf, + enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); + } + } + + if (maccrd) { + auth_off = maccrd->crd_skip; + auth_len = maccrd->crd_len; + icv_off = maccrd->crd_inject; + } + + crypt_off = enccrd->crd_skip; + crypt_len = enccrd->crd_len; + } else { /* if (maccrd) */ + auth_off = maccrd->crd_skip; + auth_len = maccrd->crd_len; + icv_off = maccrd->crd_inject; + } + + + /* + * setup the SG list to cover the buffer + */ + memset(sg, 0, sizeof(sg)); + if (crp->crp_flags & CRYPTO_F_SKBUF) { + int i, len; + + sg_num = 0; + sg_len = 0; + + len = skb_headlen(skb); + sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, + offset_in_page(skb->data)); + sg_len += len; + sg_num++; + + for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; + i++) { + len = skb_shinfo(skb)->frags[i].size; + sg_set_page(&sg[sg_num], skb_frag_page(&skb_shinfo(skb)->frags[i]), + len, skb_shinfo(skb)->frags[i].page_offset); + sg_len += len; + sg_num++; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + int len; + + sg_len = 0; + for (sg_num = 0; sg_len < crp->crp_ilen && + sg_num < uiop->uio_iovcnt && + sg_num < SCATTERLIST_MAX; sg_num++) { + len = uiop->uio_iov[sg_num].iov_len; + sg_set_page(&sg[sg_num], + virt_to_page(uiop->uio_iov[sg_num].iov_base), len, + offset_in_page(uiop->uio_iov[sg_num].iov_base)); + sg_len += len; + } + } else { + sg_len = crp->crp_ilen; + sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, + offset_in_page(crp->crp_buf)); + sg_num = 1; + } + if (sg_num > 0) + sg_mark_end(&sg[sg_num-1]); + + /* + * setup a new explicit key + */ + if (enccrd) { + if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { + od->octo_encklen = (enccrd->crd_klen + 7) / 8; + memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); + } + } + if (maccrd) { + if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { + od->octo_macklen = (maccrd->crd_klen + 7) / 8; + memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); + od->octo_mackey_set = 0; + } + if (!od->octo_mackey_set) { + octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, + maccrd->crd_key, od->octo_hminner, od->octo_hmouter); + od->octo_mackey_set = 1; + } + } + + + if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) + (*od->octo_encrypt)(od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + else + (*od->octo_decrypt)(od, sg, sg_len, + auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); + +done: + crypto_done(crp); + return 0; +} + +static int +cryptocteon_init(void) +{ + dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); + + softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); + + octo_id = crypto_get_driverid(softc_get_device(&octo_softc), + CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); + if (octo_id < 0) { + printk("Cryptocteon device cannot initialize!"); + return -ENODEV; + } + + crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); + crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); + //crypto_register(octo_id, CRYPTO_MD5, 0,0); + //crypto_register(octo_id, CRYPTO_SHA1, 0,0); + crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); + crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); + crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); + + return(0); +} + +static void +cryptocteon_exit(void) +{ + dprintk("%s()\n", __FUNCTION__); + crypto_unregister_all(octo_id); + octo_id = -1; +} + +module_init(cryptocteon_init); +module_exit(cryptocteon_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); diff --git a/target/linux/generic/files/crypto/ocf/cryptodev.c b/target/linux/generic/files/crypto/ocf/cryptodev.c new file mode 100644 index 0000000..9a23f05 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/cryptodev.c @@ -0,0 +1,1069 @@ +/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ + +/*- + * Linux port done by David McCullough + * Copyright (C) 2006-2010 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * The license and original author are listed below. + * + * Copyright (c) 2001 Theo de Raadt + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * +__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +extern asmlinkage long sys_dup(unsigned int fildes); + +#define debug cryptodev_debug +int cryptodev_debug = 0; +module_param(cryptodev_debug, int, 0644); +MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); + +struct csession_info { + u_int16_t blocksize; + u_int16_t minkey, maxkey; + + u_int16_t keysize; + /* u_int16_t hashsize; */ + u_int16_t authsize; + u_int16_t authkey; + /* u_int16_t ctxsize; */ +}; + +struct csession { + struct list_head list; + u_int64_t sid; + u_int32_t ses; + + wait_queue_head_t waitq; + + u_int32_t cipher; + + u_int32_t mac; + + caddr_t key; + int keylen; + u_char tmp_iv[EALG_MAX_BLOCK_LEN]; + + caddr_t mackey; + int mackeylen; + + struct csession_info info; + + struct iovec iovec; + struct uio uio; + int error; +}; + +struct fcrypt { + struct list_head csessions; + int sesn; +}; + +static struct csession *csefind(struct fcrypt *, u_int); +static int csedelete(struct fcrypt *, struct csession *); +static struct csession *cseadd(struct fcrypt *, struct csession *); +static struct csession *csecreate(struct fcrypt *, u_int64_t, + struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); +static int csefree(struct csession *); + +static int cryptodev_op(struct csession *, struct crypt_op *); +static int cryptodev_key(struct crypt_kop *); +static int cryptodev_find(struct crypt_find_op *); + +static int cryptodev_cb(void *); +static int cryptodev_open(struct inode *inode, struct file *filp); + +/* + * Check a crypto identifier to see if it requested + * a valid crid and it's capabilities match. + */ +static int +checkcrid(int crid) +{ + int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); + int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); + int caps = 0; + + /* if the user hasn't selected a driver, then just call newsession */ + if (hid == 0 && typ != 0) + return 0; + + caps = crypto_getcaps(hid); + + /* didn't find anything with capabilities */ + if (caps == 0) { + dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); + return EINVAL; + } + + /* the user didn't specify SW or HW, so the driver is ok */ + if (typ == 0) + return 0; + + /* if the type specified didn't match */ + if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { + dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, + hid, typ, caps); + return EINVAL; + } + + return 0; +} + +static int +cryptodev_op(struct csession *cse, struct crypt_op *cop) +{ + struct cryptop *crp = NULL; + struct cryptodesc *crde = NULL, *crda = NULL; + int error = 0; + + dprintk("%s()\n", __FUNCTION__); + if (cop->len > CRYPTO_MAX_DATA_LEN) { + dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); + return (E2BIG); + } + + if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { + dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, + cop->len); + return (EINVAL); + } + + cse->uio.uio_iov = &cse->iovec; + cse->uio.uio_iovcnt = 1; + cse->uio.uio_offset = 0; +#if 0 + cse->uio.uio_resid = cop->len; + cse->uio.uio_segflg = UIO_SYSSPACE; + cse->uio.uio_rw = UIO_WRITE; + cse->uio.uio_td = td; +#endif + cse->uio.uio_iov[0].iov_len = cop->len; + if (cse->info.authsize) + cse->uio.uio_iov[0].iov_len += cse->info.authsize; + cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, + GFP_KERNEL); + + if (cse->uio.uio_iov[0].iov_base == NULL) { + dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, + (int)cse->uio.uio_iov[0].iov_len); + return (ENOMEM); + } + + crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); + if (crp == NULL) { + dprintk("%s: ENOMEM\n", __FUNCTION__); + error = ENOMEM; + goto bail; + } + + if (cse->info.authsize && cse->info.blocksize) { + if (cop->op == COP_ENCRYPT) { + crde = crp->crp_desc; + crda = crde->crd_next; + } else { + crda = crp->crp_desc; + crde = crda->crd_next; + } + } else if (cse->info.authsize) { + crda = crp->crp_desc; + } else if (cse->info.blocksize) { + crde = crp->crp_desc; + } else { + dprintk("%s: bad request\n", __FUNCTION__); + error = EINVAL; + goto bail; + } + + if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, + cop->len))) { + dprintk("%s: bad copy\n", __FUNCTION__); + goto bail; + } + + if (crda) { + crda->crd_skip = 0; + crda->crd_len = cop->len; + crda->crd_inject = cop->len; + + crda->crd_alg = cse->mac; + crda->crd_key = cse->mackey; + crda->crd_klen = cse->mackeylen * 8; + } + + if (crde) { + if (cop->op == COP_ENCRYPT) + crde->crd_flags |= CRD_F_ENCRYPT; + else + crde->crd_flags &= ~CRD_F_ENCRYPT; + crde->crd_len = cop->len; + crde->crd_inject = 0; + + crde->crd_alg = cse->cipher; + crde->crd_key = cse->key; + crde->crd_klen = cse->keylen * 8; + } + + crp->crp_ilen = cse->uio.uio_iov[0].iov_len; + crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM + | (cop->flags & COP_F_BATCH); + crp->crp_buf = (caddr_t)&cse->uio; + crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; + crp->crp_sid = cse->sid; + crp->crp_opaque = (void *)cse; + + if (cop->iv) { + if (crde == NULL) { + error = EINVAL; + dprintk("%s no crde\n", __FUNCTION__); + goto bail; + } + if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ + error = EINVAL; + dprintk("%s arc4 with IV\n", __FUNCTION__); + goto bail; + } + if ((error = copy_from_user(cse->tmp_iv, cop->iv, + cse->info.blocksize))) { + dprintk("%s bad iv copy\n", __FUNCTION__); + goto bail; + } + memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); + crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; + crde->crd_skip = 0; + } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ + crde->crd_skip = 0; + } else if (crde) { + crde->crd_flags |= CRD_F_IV_PRESENT; + crde->crd_skip = cse->info.blocksize; + crde->crd_len -= cse->info.blocksize; + } + + if (cop->mac && crda == NULL) { + error = EINVAL; + dprintk("%s no crda\n", __FUNCTION__); + goto bail; + } + + /* + * Let the dispatch run unlocked, then, interlock against the + * callback before checking if the operation completed and going + * to sleep. This insures drivers don't inherit our lock which + * results in a lock order reversal between crypto_dispatch forced + * entry and the crypto_done callback into us. + */ + error = crypto_dispatch(crp); + if (error) { + dprintk("%s error in crypto_dispatch\n", __FUNCTION__); + goto bail; + } + + dprintk("%s about to WAIT\n", __FUNCTION__); + /* + * we really need to wait for driver to complete to maintain + * state, luckily interrupts will be remembered + */ + do { + error = wait_event_interruptible(crp->crp_waitq, + ((crp->crp_flags & CRYPTO_F_DONE) != 0)); + /* + * we can't break out of this loop or we will leave behind + * a huge mess, however, staying here means if your driver + * is broken user applications can hang and not be killed. + * The solution, fix your driver :-) + */ + if (error) { + schedule(); + error = 0; + } + } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); + dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); + + if (crp->crp_etype != 0) { + error = crp->crp_etype; + dprintk("%s error in crp processing\n", __FUNCTION__); + goto bail; + } + + if (cse->error) { + error = cse->error; + dprintk("%s error in cse processing\n", __FUNCTION__); + goto bail; + } + + if (cop->dst && (error = copy_to_user(cop->dst, + cse->uio.uio_iov[0].iov_base, cop->len))) { + dprintk("%s bad dst copy\n", __FUNCTION__); + goto bail; + } + + if (cop->mac && + (error=copy_to_user(cop->mac, + (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, + cse->info.authsize))) { + dprintk("%s bad mac copy\n", __FUNCTION__); + goto bail; + } + +bail: + if (crp) + crypto_freereq(crp); + if (cse->uio.uio_iov[0].iov_base) + kfree(cse->uio.uio_iov[0].iov_base); + + return (error); +} + +static int +cryptodev_cb(void *op) +{ + struct cryptop *crp = (struct cryptop *) op; + struct csession *cse = (struct csession *)crp->crp_opaque; + int error; + + dprintk("%s()\n", __FUNCTION__); + error = crp->crp_etype; + if (error == EAGAIN) { + crp->crp_flags &= ~CRYPTO_F_DONE; +#ifdef NOTYET + /* + * DAVIDM I am fairly sure that we should turn this into a batch + * request to stop bad karma/lockup, revisit + */ + crp->crp_flags |= CRYPTO_F_BATCH; +#endif + return crypto_dispatch(crp); + } + if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { + cse->error = error; + wake_up_interruptible(&crp->crp_waitq); + } + return (0); +} + +static int +cryptodevkey_cb(void *op) +{ + struct cryptkop *krp = (struct cryptkop *) op; + dprintk("%s()\n", __FUNCTION__); + wake_up_interruptible(&krp->krp_waitq); + return (0); +} + +static int +cryptodev_key(struct crypt_kop *kop) +{ + struct cryptkop *krp = NULL; + int error = EINVAL; + int in, out, size, i; + + dprintk("%s()\n", __FUNCTION__); + if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { + dprintk("%s params too big\n", __FUNCTION__); + return (EFBIG); + } + + in = kop->crk_iparams; + out = kop->crk_oparams; + switch (kop->crk_op) { + case CRK_MOD_EXP: + if (in == 3 && out == 1) + break; + return (EINVAL); + case CRK_MOD_EXP_CRT: + if (in == 6 && out == 1) + break; + return (EINVAL); + case CRK_DSA_SIGN: + if (in == 5 && out == 2) + break; + return (EINVAL); + case CRK_DSA_VERIFY: + if (in == 7 && out == 0) + break; + return (EINVAL); + case CRK_DH_COMPUTE_KEY: + if (in == 3 && out == 1) + break; + return (EINVAL); + default: + return (EINVAL); + } + + krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); + if (!krp) + return (ENOMEM); + bzero(krp, sizeof *krp); + krp->krp_op = kop->crk_op; + krp->krp_status = kop->crk_status; + krp->krp_iparams = kop->crk_iparams; + krp->krp_oparams = kop->crk_oparams; + krp->krp_crid = kop->crk_crid; + krp->krp_status = 0; + krp->krp_flags = CRYPTO_KF_CBIMM; + krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; + init_waitqueue_head(&krp->krp_waitq); + + for (i = 0; i < CRK_MAXPARAM; i++) + krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; + for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { + size = (krp->krp_param[i].crp_nbits + 7) / 8; + if (size == 0) + continue; + krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); + if (i >= krp->krp_iparams) + continue; + error = copy_from_user(krp->krp_param[i].crp_p, + kop->crk_param[i].crp_p, size); + if (error) + goto fail; + } + + error = crypto_kdispatch(krp); + if (error) + goto fail; + + do { + error = wait_event_interruptible(krp->krp_waitq, + ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); + /* + * we can't break out of this loop or we will leave behind + * a huge mess, however, staying here means if your driver + * is broken user applications can hang and not be killed. + * The solution, fix your driver :-) + */ + if (error) { + schedule(); + error = 0; + } + } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); + + dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); + + kop->crk_crid = krp->krp_crid; /* device that did the work */ + if (krp->krp_status != 0) { + error = krp->krp_status; + goto fail; + } + + for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { + size = (krp->krp_param[i].crp_nbits + 7) / 8; + if (size == 0) + continue; + error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, + size); + if (error) + goto fail; + } + +fail: + if (krp) { + kop->crk_status = krp->krp_status; + for (i = 0; i < CRK_MAXPARAM; i++) { + if (krp->krp_param[i].crp_p) + kfree(krp->krp_param[i].crp_p); + } + kfree(krp); + } + return (error); +} + +static int +cryptodev_find(struct crypt_find_op *find) +{ + device_t dev; + + if (find->crid != -1) { + dev = crypto_find_device_byhid(find->crid); + if (dev == NULL) + return (ENOENT); + strlcpy(find->name, device_get_nameunit(dev), + sizeof(find->name)); + } else { + find->crid = crypto_find_driver(find->name); + if (find->crid == -1) + return (ENOENT); + } + return (0); +} + +static struct csession * +csefind(struct fcrypt *fcr, u_int ses) +{ + struct csession *cse; + + dprintk("%s()\n", __FUNCTION__); + list_for_each_entry(cse, &fcr->csessions, list) + if (cse->ses == ses) + return (cse); + return (NULL); +} + +static int +csedelete(struct fcrypt *fcr, struct csession *cse_del) +{ + struct csession *cse; + + dprintk("%s()\n", __FUNCTION__); + list_for_each_entry(cse, &fcr->csessions, list) { + if (cse == cse_del) { + list_del(&cse->list); + return (1); + } + } + return (0); +} + +static struct csession * +cseadd(struct fcrypt *fcr, struct csession *cse) +{ + dprintk("%s()\n", __FUNCTION__); + list_add_tail(&cse->list, &fcr->csessions); + cse->ses = fcr->sesn++; + return (cse); +} + +static struct csession * +csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, + struct cryptoini *cria, struct csession_info *info) +{ + struct csession *cse; + + dprintk("%s()\n", __FUNCTION__); + cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); + if (cse == NULL) + return NULL; + memset(cse, 0, sizeof(struct csession)); + + INIT_LIST_HEAD(&cse->list); + init_waitqueue_head(&cse->waitq); + + cse->key = crie->cri_key; + cse->keylen = crie->cri_klen/8; + cse->mackey = cria->cri_key; + cse->mackeylen = cria->cri_klen/8; + cse->sid = sid; + cse->cipher = crie->cri_alg; + cse->mac = cria->cri_alg; + cse->info = *info; + cseadd(fcr, cse); + return (cse); +} + +static int +csefree(struct csession *cse) +{ + int error; + + dprintk("%s()\n", __FUNCTION__); + error = crypto_freesession(cse->sid); + if (cse->key) + kfree(cse->key); + if (cse->mackey) + kfree(cse->mackey); + kfree(cse); + return(error); +} + +static int +cryptodev_ioctl( + struct inode *inode, + struct file *filp, + unsigned int cmd, + unsigned long arg) +{ + struct cryptoini cria, crie; + struct fcrypt *fcr = filp->private_data; + struct csession *cse; + struct csession_info info; + struct session2_op sop; + struct crypt_op cop; + struct crypt_kop kop; + struct crypt_find_op fop; + u_int64_t sid; + u_int32_t ses = 0; + int feat, fd, error = 0, crid; + mm_segment_t fs; + + dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); + + switch (cmd) { + + case CRIOGET: { + dprintk("%s(CRIOGET)\n", __FUNCTION__); + fs = get_fs(); + set_fs(get_ds()); + for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) + if (files_fdtable(current->files)->fd[fd] == filp) + break; + fd = sys_dup(fd); + set_fs(fs); + put_user(fd, (int *) arg); + return IS_ERR_VALUE(fd) ? fd : 0; + } + +#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") + case CIOCGSESSION: + case CIOCGSESSION2: + dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); + memset(&crie, 0, sizeof(crie)); + memset(&cria, 0, sizeof(cria)); + memset(&info, 0, sizeof(info)); + memset(&sop, 0, sizeof(sop)); + + if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? + sizeof(struct session_op) : sizeof(sop))) { + dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); + error = EFAULT; + goto bail; + } + + switch (sop.cipher) { + case 0: + dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); + break; + case CRYPTO_NULL_CBC: + info.blocksize = NULL_BLOCK_LEN; + info.minkey = NULL_MIN_KEY_LEN; + info.maxkey = NULL_MAX_KEY_LEN; + break; + case CRYPTO_DES_CBC: + info.blocksize = DES_BLOCK_LEN; + info.minkey = DES_MIN_KEY_LEN; + info.maxkey = DES_MAX_KEY_LEN; + break; + case CRYPTO_3DES_CBC: + info.blocksize = DES3_BLOCK_LEN; + info.minkey = DES3_MIN_KEY_LEN; + info.maxkey = DES3_MAX_KEY_LEN; + break; + case CRYPTO_BLF_CBC: + info.blocksize = BLOWFISH_BLOCK_LEN; + info.minkey = BLOWFISH_MIN_KEY_LEN; + info.maxkey = BLOWFISH_MAX_KEY_LEN; + break; + case CRYPTO_CAST_CBC: + info.blocksize = CAST128_BLOCK_LEN; + info.minkey = CAST128_MIN_KEY_LEN; + info.maxkey = CAST128_MAX_KEY_LEN; + break; + case CRYPTO_SKIPJACK_CBC: + info.blocksize = SKIPJACK_BLOCK_LEN; + info.minkey = SKIPJACK_MIN_KEY_LEN; + info.maxkey = SKIPJACK_MAX_KEY_LEN; + break; + case CRYPTO_AES_CBC: + info.blocksize = AES_BLOCK_LEN; + info.minkey = AES_MIN_KEY_LEN; + info.maxkey = AES_MAX_KEY_LEN; + break; + case CRYPTO_ARC4: + info.blocksize = ARC4_BLOCK_LEN; + info.minkey = ARC4_MIN_KEY_LEN; + info.maxkey = ARC4_MAX_KEY_LEN; + break; + case CRYPTO_CAMELLIA_CBC: + info.blocksize = CAMELLIA_BLOCK_LEN; + info.minkey = CAMELLIA_MIN_KEY_LEN; + info.maxkey = CAMELLIA_MAX_KEY_LEN; + break; + default: + dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); + error = EINVAL; + goto bail; + } + + switch (sop.mac) { + case 0: + dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); + break; + case CRYPTO_NULL_HMAC: + info.authsize = NULL_HASH_LEN; + break; + case CRYPTO_MD5: + info.authsize = MD5_HASH_LEN; + break; + case CRYPTO_SHA1: + info.authsize = SHA1_HASH_LEN; + break; + case CRYPTO_SHA2_256: + info.authsize = SHA2_256_HASH_LEN; + break; + case CRYPTO_SHA2_384: + info.authsize = SHA2_384_HASH_LEN; + break; + case CRYPTO_SHA2_512: + info.authsize = SHA2_512_HASH_LEN; + break; + case CRYPTO_RIPEMD160: + info.authsize = RIPEMD160_HASH_LEN; + break; + case CRYPTO_MD5_HMAC: + info.authsize = MD5_HASH_LEN; + info.authkey = 16; + break; + case CRYPTO_SHA1_HMAC: + info.authsize = SHA1_HASH_LEN; + info.authkey = 20; + break; + case CRYPTO_SHA2_256_HMAC: + info.authsize = SHA2_256_HASH_LEN; + info.authkey = 32; + break; + case CRYPTO_SHA2_384_HMAC: + info.authsize = SHA2_384_HASH_LEN; + info.authkey = 48; + break; + case CRYPTO_SHA2_512_HMAC: + info.authsize = SHA2_512_HASH_LEN; + info.authkey = 64; + break; + case CRYPTO_RIPEMD160_HMAC: + info.authsize = RIPEMD160_HASH_LEN; + info.authkey = 20; + break; + default: + dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); + error = EINVAL; + goto bail; + } + + if (info.blocksize) { + crie.cri_alg = sop.cipher; + crie.cri_klen = sop.keylen * 8; + if ((info.maxkey && sop.keylen > info.maxkey) || + sop.keylen < info.minkey) { + dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); + error = EINVAL; + goto bail; + } + + crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); + if (copy_from_user(crie.cri_key, sop.key, + crie.cri_klen/8)) { + dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); + error = EFAULT; + goto bail; + } + if (info.authsize) + crie.cri_next = &cria; + } + + if (info.authsize) { + cria.cri_alg = sop.mac; + cria.cri_klen = sop.mackeylen * 8; + if (info.authkey && sop.mackeylen != info.authkey) { + dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, + CIOCGSESSSTR, sop.mackeylen, info.authkey); + error = EINVAL; + goto bail; + } + + if (cria.cri_klen) { + cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); + if (copy_from_user(cria.cri_key, sop.mackey, + cria.cri_klen / 8)) { + dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); + error = EFAULT; + goto bail; + } + } + } + + /* NB: CIOGSESSION2 has the crid */ + if (cmd == CIOCGSESSION2) { + crid = sop.crid; + error = checkcrid(crid); + if (error) { + dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, + CIOCGSESSSTR, error); + goto bail; + } + } else { + /* allow either HW or SW to be used */ + crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; + } + error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); + if (error) { + dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); + goto bail; + } + + cse = csecreate(fcr, sid, &crie, &cria, &info); + if (cse == NULL) { + crypto_freesession(sid); + error = EINVAL; + dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); + goto bail; + } + sop.ses = cse->ses; + + if (cmd == CIOCGSESSION2) { + /* return hardware/driver id */ + sop.crid = CRYPTO_SESID2HID(cse->sid); + } + + if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? + sizeof(struct session_op) : sizeof(sop))) { + dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); + error = EFAULT; + } +bail: + if (error) { + dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); + if (crie.cri_key) + kfree(crie.cri_key); + if (cria.cri_key) + kfree(cria.cri_key); + } + break; + case CIOCFSESSION: + dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); + get_user(ses, (uint32_t*)arg); + cse = csefind(fcr, ses); + if (cse == NULL) { + error = EINVAL; + dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); + break; + } + csedelete(fcr, cse); + error = csefree(cse); + break; + case CIOCCRYPT: + dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); + if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { + dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); + error = EFAULT; + goto bail; + } + cse = csefind(fcr, cop.ses); + if (cse == NULL) { + error = EINVAL; + dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); + break; + } + error = cryptodev_op(cse, &cop); + if(copy_to_user((void*)arg, &cop, sizeof(cop))) { + dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); + error = EFAULT; + goto bail; + } + break; + case CIOCKEY: + case CIOCKEY2: + dprintk("%s(CIOCKEY)\n", __FUNCTION__); + if (!crypto_userasymcrypto) + return (EPERM); /* XXX compat? */ + if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { + dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); + error = EFAULT; + goto bail; + } + if (cmd == CIOCKEY) { + /* NB: crypto core enforces s/w driver use */ + kop.crk_crid = + CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; + } + error = cryptodev_key(&kop); + if(copy_to_user((void*)arg, &kop, sizeof(kop))) { + dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); + error = EFAULT; + goto bail; + } + break; + case CIOCASYMFEAT: + dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); + if (!crypto_userasymcrypto) { + /* + * NB: if user asym crypto operations are + * not permitted return "no algorithms" + * so well-behaved applications will just + * fallback to doing them in software. + */ + feat = 0; + } else + error = crypto_getfeat(&feat); + if (!error) { + error = copy_to_user((void*)arg, &feat, sizeof(feat)); + } + break; + case CIOCFINDDEV: + if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { + dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); + error = EFAULT; + goto bail; + } + error = cryptodev_find(&fop); + if (copy_to_user((void*)arg, &fop, sizeof(fop))) { + dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); + error = EFAULT; + goto bail; + } + break; + default: + dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); + error = EINVAL; + break; + } + return(-error); +} + +#ifdef HAVE_UNLOCKED_IOCTL +static long +cryptodev_unlocked_ioctl( + struct file *filp, + unsigned int cmd, + unsigned long arg) +{ + return cryptodev_ioctl(NULL, filp, cmd, arg); +} +#endif + +static int +cryptodev_open(struct inode *inode, struct file *filp) +{ + struct fcrypt *fcr; + + dprintk("%s()\n", __FUNCTION__); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) + /* + * on 2.6.35 private_data points to a miscdevice structure, we override + * it, which is currently safe to do. + */ + if (filp->private_data) { + printk("cryptodev: Private data already exists - %p!\n", filp->private_data); + return(-ENODEV); + } +#endif + + fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); + if (!fcr) { + dprintk("%s() - malloc failed\n", __FUNCTION__); + return(-ENOMEM); + } + memset(fcr, 0, sizeof(*fcr)); + + INIT_LIST_HEAD(&fcr->csessions); + filp->private_data = fcr; + return(0); +} + +static int +cryptodev_release(struct inode *inode, struct file *filp) +{ + struct fcrypt *fcr = filp->private_data; + struct csession *cse, *tmp; + + dprintk("%s()\n", __FUNCTION__); + if (!filp) { + printk("cryptodev: No private data on release\n"); + return(0); + } + + list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { + list_del(&cse->list); + (void)csefree(cse); + } + filp->private_data = NULL; + kfree(fcr); + return(0); +} + +static struct file_operations cryptodev_fops = { + .owner = THIS_MODULE, + .open = cryptodev_open, + .release = cryptodev_release, +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) + .ioctl = cryptodev_ioctl, +#endif +#ifdef HAVE_UNLOCKED_IOCTL + .unlocked_ioctl = cryptodev_unlocked_ioctl, +#endif +}; + +static struct miscdevice cryptodev = { + .minor = CRYPTODEV_MINOR, + .name = "crypto", + .fops = &cryptodev_fops, +}; + +static int __init +cryptodev_init(void) +{ + int rc; + + dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); + rc = misc_register(&cryptodev); + if (rc) { + printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); + return(rc); + } + + return(0); +} + +static void __exit +cryptodev_exit(void) +{ + dprintk("%s()\n", __FUNCTION__); + misc_deregister(&cryptodev); +} + +module_init(cryptodev_init); +module_exit(cryptodev_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); diff --git a/target/linux/generic/files/crypto/ocf/cryptodev.h b/target/linux/generic/files/crypto/ocf/cryptodev.h new file mode 100644 index 0000000..cca0ec8 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/cryptodev.h @@ -0,0 +1,480 @@ +/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ +/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ + +/*- + * Linux port done by David McCullough + * Copyright (C) 2006-2010 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * The license and original author are listed below. + * + * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting + * + * This code was written by Angelos D. Keromytis in Athens, Greece, in + * February 2000. Network Security Technologies Inc. (NSTI) kindly + * supported the development of this code. + * + * Copyright (c) 2000 Angelos D. Keromytis + * + * Permission to use, copy, and modify this software with or without fee + * is hereby granted, provided that this entire notice is included in + * all source code copies of any software which is or includes a copy or + * modification of this software. + * + * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY + * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE + * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR + * PURPOSE. + * + * Copyright (c) 2001 Theo de Raadt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ + +#ifndef _CRYPTO_CRYPTO_H_ +#define _CRYPTO_CRYPTO_H_ + +/* Some initial values */ +#define CRYPTO_DRIVERS_INITIAL 4 +#define CRYPTO_SW_SESSIONS 32 + +/* Hash values */ +#define NULL_HASH_LEN 0 +#define MD5_HASH_LEN 16 +#define SHA1_HASH_LEN 20 +#define RIPEMD160_HASH_LEN 20 +#define SHA2_256_HASH_LEN 32 +#define SHA2_384_HASH_LEN 48 +#define SHA2_512_HASH_LEN 64 +#define MD5_KPDK_HASH_LEN 16 +#define SHA1_KPDK_HASH_LEN 20 +/* Maximum hash algorithm result length */ +#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ + +/* HMAC values */ +#define NULL_HMAC_BLOCK_LEN 1 +#define MD5_HMAC_BLOCK_LEN 64 +#define SHA1_HMAC_BLOCK_LEN 64 +#define RIPEMD160_HMAC_BLOCK_LEN 64 +#define SHA2_256_HMAC_BLOCK_LEN 64 +#define SHA2_384_HMAC_BLOCK_LEN 128 +#define SHA2_512_HMAC_BLOCK_LEN 128 +/* Maximum HMAC block length */ +#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ +#define HMAC_IPAD_VAL 0x36 +#define HMAC_OPAD_VAL 0x5C + +/* Encryption algorithm block sizes */ +#define NULL_BLOCK_LEN 1 +#define DES_BLOCK_LEN 8 +#define DES3_BLOCK_LEN 8 +#define BLOWFISH_BLOCK_LEN 8 +#define SKIPJACK_BLOCK_LEN 8 +#define CAST128_BLOCK_LEN 8 +#define RIJNDAEL128_BLOCK_LEN 16 +#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN +#define CAMELLIA_BLOCK_LEN 16 +#define ARC4_BLOCK_LEN 1 +#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ + +/* Encryption algorithm min and max key sizes */ +#define NULL_MIN_KEY_LEN 0 +#define NULL_MAX_KEY_LEN 0 +#define DES_MIN_KEY_LEN 8 +#define DES_MAX_KEY_LEN 8 +#define DES3_MIN_KEY_LEN 24 +#define DES3_MAX_KEY_LEN 24 +#define BLOWFISH_MIN_KEY_LEN 4 +#define BLOWFISH_MAX_KEY_LEN 56 +#define SKIPJACK_MIN_KEY_LEN 10 +#define SKIPJACK_MAX_KEY_LEN 10 +#define CAST128_MIN_KEY_LEN 5 +#define CAST128_MAX_KEY_LEN 16 +#define RIJNDAEL128_MIN_KEY_LEN 16 +#define RIJNDAEL128_MAX_KEY_LEN 32 +#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN +#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN +#define CAMELLIA_MIN_KEY_LEN 16 +#define CAMELLIA_MAX_KEY_LEN 32 +#define ARC4_MIN_KEY_LEN 1 +#define ARC4_MAX_KEY_LEN 256 + +/* Max size of data that can be processed */ +#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 + +#define CRYPTO_ALGORITHM_MIN 1 +#define CRYPTO_DES_CBC 1 +#define CRYPTO_3DES_CBC 2 +#define CRYPTO_BLF_CBC 3 +#define CRYPTO_CAST_CBC 4 +#define CRYPTO_SKIPJACK_CBC 5 +#define CRYPTO_MD5_HMAC 6 +#define CRYPTO_SHA1_HMAC 7 +#define CRYPTO_RIPEMD160_HMAC 8 +#define CRYPTO_MD5_KPDK 9 +#define CRYPTO_SHA1_KPDK 10 +#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ +#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ +#define CRYPTO_ARC4 12 +#define CRYPTO_MD5 13 +#define CRYPTO_SHA1 14 +#define CRYPTO_NULL_HMAC 15 +#define CRYPTO_NULL_CBC 16 +#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ +#define CRYPTO_SHA2_256_HMAC 18 +#define CRYPTO_SHA2_384_HMAC 19 +#define CRYPTO_SHA2_512_HMAC 20 +#define CRYPTO_CAMELLIA_CBC 21 +#define CRYPTO_SHA2_256 22 +#define CRYPTO_SHA2_384 23 +#define CRYPTO_SHA2_512 24 +#define CRYPTO_RIPEMD160 25 +#define CRYPTO_LZS_COMP 26 +#define CRYPTO_ALGORITHM_MAX 26 /* Keep updated - see above */ + +/* Algorithm flags */ +#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ +#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ +#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ + +/* + * Crypto driver/device flags. They can set in the crid + * parameter when creating a session or submitting a key + * op to affect the device/driver assigned. If neither + * of these are specified then the crid is assumed to hold + * the driver id of an existing (and suitable) device that + * must be used to satisfy the request. + */ +#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ +#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ + +/* NB: deprecated */ +struct session_op { + u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ + u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ + + u_int32_t keylen; /* cipher key */ + caddr_t key; + int mackeylen; /* mac key */ + caddr_t mackey; + + u_int32_t ses; /* returns: session # */ +}; + +struct session2_op { + u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ + u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ + + u_int32_t keylen; /* cipher key */ + caddr_t key; + int mackeylen; /* mac key */ + caddr_t mackey; + + u_int32_t ses; /* returns: session # */ + int crid; /* driver id + flags (rw) */ + int pad[4]; /* for future expansion */ +}; + +struct crypt_op { + u_int32_t ses; + u_int16_t op; /* i.e. COP_ENCRYPT */ +#define COP_NONE 0 +#define COP_ENCRYPT 1 +#define COP_DECRYPT 2 + u_int16_t flags; +#define COP_F_BATCH 0x0008 /* Batch op if possible */ + u_int len; + caddr_t src, dst; /* become iov[] inside kernel */ + caddr_t mac; /* must be big enough for chosen MAC */ + caddr_t iv; +}; + +/* + * Parameters for looking up a crypto driver/device by + * device name or by id. The latter are returned for + * created sessions (crid) and completed key operations. + */ +struct crypt_find_op { + int crid; /* driver id + flags */ + char name[32]; /* device/driver name */ +}; + +/* bignum parameter, in packed bytes, ... */ +struct crparam { + caddr_t crp_p; + u_int crp_nbits; +}; + +#define CRK_MAXPARAM 8 + +struct crypt_kop { + u_int crk_op; /* ie. CRK_MOD_EXP or other */ + u_int crk_status; /* return status */ + u_short crk_iparams; /* # of input parameters */ + u_short crk_oparams; /* # of output parameters */ + u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ + struct crparam crk_param[CRK_MAXPARAM]; +}; +#define CRK_ALGORITM_MIN 0 +#define CRK_MOD_EXP 0 +#define CRK_MOD_EXP_CRT 1 +#define CRK_DSA_SIGN 2 +#define CRK_DSA_VERIFY 3 +#define CRK_DH_COMPUTE_KEY 4 +#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ + +#define CRF_MOD_EXP (1 << CRK_MOD_EXP) +#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) +#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) +#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) +#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) + +/* + * done against open of /dev/crypto, to get a cloned descriptor. + * Please use F_SETFD against the cloned descriptor. + */ +#define CRIOGET _IOWR('c', 100, u_int32_t) +#define CRIOASYMFEAT CIOCASYMFEAT +#define CRIOFINDDEV CIOCFINDDEV + +/* the following are done against the cloned descriptor */ +#define CIOCGSESSION _IOWR('c', 101, struct session_op) +#define CIOCFSESSION _IOW('c', 102, u_int32_t) +#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) +#define CIOCKEY _IOWR('c', 104, struct crypt_kop) +#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) +#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) +#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) +#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) + +struct cryptotstat { + struct timespec acc; /* total accumulated time */ + struct timespec min; /* min time */ + struct timespec max; /* max time */ + u_int32_t count; /* number of observations */ +}; + +struct cryptostats { + u_int32_t cs_ops; /* symmetric crypto ops submitted */ + u_int32_t cs_errs; /* symmetric crypto ops that failed */ + u_int32_t cs_kops; /* asymetric/key ops submitted */ + u_int32_t cs_kerrs; /* asymetric/key ops that failed */ + u_int32_t cs_intrs; /* crypto swi thread activations */ + u_int32_t cs_rets; /* crypto return thread activations */ + u_int32_t cs_blocks; /* symmetric op driver block */ + u_int32_t cs_kblocks; /* symmetric op driver block */ + /* + * When CRYPTO_TIMING is defined at compile time and the + * sysctl debug.crypto is set to 1, the crypto system will + * accumulate statistics about how long it takes to process + * crypto requests at various points during processing. + */ + struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ + struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ + struct cryptotstat cs_cb; /* crypto_done -> callback */ + struct cryptotstat cs_finis; /* callback -> callback return */ + + u_int32_t cs_drops; /* crypto ops dropped due to congestion */ +}; + +#ifdef __KERNEL__ + +/* Standard initialization structure beginning */ +struct cryptoini { + int cri_alg; /* Algorithm to use */ + int cri_klen; /* Key length, in bits */ + int cri_mlen; /* Number of bytes we want from the + entire hash. 0 means all. */ + caddr_t cri_key; /* key to use */ + u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ + struct cryptoini *cri_next; +}; + +/* Describe boundaries of a single crypto operation */ +struct cryptodesc { + int crd_skip; /* How many bytes to ignore from start */ + int crd_len; /* How many bytes to process */ + int crd_inject; /* Where to inject results, if applicable */ + int crd_flags; + +#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ +#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in + place, so don't copy. */ +#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ +#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ +#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ +#define CRD_F_COMP 0x0f /* Set when doing compression */ + + struct cryptoini CRD_INI; /* Initialization/context data */ +#define crd_iv CRD_INI.cri_iv +#define crd_key CRD_INI.cri_key +#define crd_alg CRD_INI.cri_alg +#define crd_klen CRD_INI.cri_klen +#define crd_mlen CRD_INI.cri_mlen + + struct cryptodesc *crd_next; +}; + +/* Structure describing complete operation */ +struct cryptop { + struct list_head crp_next; + wait_queue_head_t crp_waitq; + + u_int64_t crp_sid; /* Session ID */ + int crp_ilen; /* Input data total length */ + int crp_olen; /* Result total length */ + + int crp_etype; /* + * Error type (zero means no error). + * All error codes except EAGAIN + * indicate possible data corruption (as in, + * the data have been touched). On all + * errors, the crp_sid may have changed + * (reset to a new one), so the caller + * should always check and use the new + * value on future requests. + */ + int crp_flags; + +#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ +#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ +#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ +#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ +#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ +#define CRYPTO_F_DONE 0x0020 /* Operation completed */ +#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ + + caddr_t crp_buf; /* Data to be processed */ + caddr_t crp_opaque; /* Opaque pointer, passed along */ + struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ + + int (*crp_callback)(struct cryptop *); /* Callback function */ +}; + +#define CRYPTO_BUF_CONTIG 0x0 +#define CRYPTO_BUF_IOV 0x1 +#define CRYPTO_BUF_SKBUF 0x2 + +#define CRYPTO_OP_DECRYPT 0x0 +#define CRYPTO_OP_ENCRYPT 0x1 + +/* + * Hints passed to process methods. + */ +#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ + +struct cryptkop { + struct list_head krp_next; + wait_queue_head_t krp_waitq; + + int krp_flags; +#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ +#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ + + u_int krp_op; /* ie. CRK_MOD_EXP or other */ + u_int krp_status; /* return status */ + u_short krp_iparams; /* # of input parameters */ + u_short krp_oparams; /* # of output parameters */ + u_int krp_crid; /* desired device, etc. */ + u_int32_t krp_hid; + struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ + int (*krp_callback)(struct cryptkop *); +}; + +#include + +/* + * Session ids are 64 bits. The lower 32 bits contain a "local id" which + * is a driver-private session identifier. The upper 32 bits contain a + * "hardware id" used by the core crypto code to identify the driver and + * a copy of the driver's capabilities that can be used by client code to + * optimize operation. + */ +#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) +#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) +#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) + +extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); +extern int crypto_freesession(u_int64_t sid); +#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE +#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE +#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ +extern int32_t crypto_get_driverid(device_t dev, int flags); +extern int crypto_find_driver(const char *); +extern device_t crypto_find_device_byhid(int hid); +extern int crypto_getcaps(int hid); +extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, + u_int32_t flags); +extern int crypto_kregister(u_int32_t, int, u_int32_t); +extern int crypto_unregister(u_int32_t driverid, int alg); +extern int crypto_unregister_all(u_int32_t driverid); +extern int crypto_dispatch(struct cryptop *crp); +extern int crypto_kdispatch(struct cryptkop *); +#define CRYPTO_SYMQ 0x1 +#define CRYPTO_ASYMQ 0x2 +extern int crypto_unblock(u_int32_t, int); +extern void crypto_done(struct cryptop *crp); +extern void crypto_kdone(struct cryptkop *); +extern int crypto_getfeat(int *); + +extern void crypto_freereq(struct cryptop *crp); +extern struct cryptop *crypto_getreq(int num); + +extern int crypto_usercrypto; /* userland may do crypto requests */ +extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ +extern int crypto_devallowsoft; /* only use hardware crypto */ + +/* + * random number support, crypto_unregister_all will unregister + */ +extern int crypto_rregister(u_int32_t driverid, + int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); +extern int crypto_runregister_all(u_int32_t driverid); + +/* + * Crypto-related utility routines used mainly by drivers. + * + * XXX these don't really belong here; but for now they're + * kept apart from the rest of the system. + */ +struct uio; +extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); +extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); +extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); + +extern void crypto_copyback(int flags, caddr_t buf, int off, int size, + caddr_t in); +extern void crypto_copydata(int flags, caddr_t buf, int off, int size, + caddr_t out); +extern int crypto_apply(int flags, caddr_t buf, int off, int len, + int (*f)(void *, void *, u_int), void *arg); + +#endif /* __KERNEL__ */ +#endif /* _CRYPTO_CRYPTO_H_ */ diff --git a/target/linux/generic/files/crypto/ocf/cryptosoft.c b/target/linux/generic/files/crypto/ocf/cryptosoft.c new file mode 100644 index 0000000..aa2383d --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/cryptosoft.c @@ -0,0 +1,1322 @@ +/* + * An OCF module that uses the linux kernel cryptoapi, based on the + * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) + * but is mostly unrecognisable, + * + * Written by David McCullough + * Copyright (C) 2004-2011 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * ALTERNATIVELY, provided that this notice is retained in full, this product + * may be distributed under the terms of the GNU General Public License (GPL), + * in which case the provisions of the GPL apply INSTEAD OF those given above. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + * --------------------------------------------------------------------------- + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) +#include +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) +#include +#endif + +#include +#include + +struct { + softc_device_decl sc_dev; +} swcr_softc; + +#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) + +#define SW_TYPE_CIPHER 0x01 +#define SW_TYPE_HMAC 0x02 +#define SW_TYPE_HASH 0x04 +#define SW_TYPE_COMP 0x08 +#define SW_TYPE_BLKCIPHER 0x10 +#define SW_TYPE_ALG_MASK 0x1f + +#define SW_TYPE_ASYNC 0x8000 + +#define SW_TYPE_INUSE 0x10000000 + +/* We change some of the above if we have an async interface */ + +#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) + +#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) +#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) +#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) + +#define SCATTERLIST_MAX 16 + +struct swcr_data { + struct work_struct workq; + int sw_type; + int sw_alg; + struct crypto_tfm *sw_tfm; + spinlock_t sw_tfm_lock; + union { + struct { + char *sw_key; + int sw_klen; + int sw_mlen; + } hmac; + void *sw_comp_buf; + } u; + struct swcr_data *sw_next; +}; + +struct swcr_req { + struct swcr_data *sw_head; + struct swcr_data *sw; + struct cryptop *crp; + struct cryptodesc *crd; + struct scatterlist sg[SCATTERLIST_MAX]; + unsigned char iv[EALG_MAX_BLOCK_LEN]; + char result[HASH_MAX_LEN]; + void *crypto_req; +}; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static kmem_cache_t *swcr_req_cache; +#else +static struct kmem_cache *swcr_req_cache; +#endif + +#ifndef CRYPTO_TFM_MODE_CBC +/* + * As of linux-2.6.21 this is no longer defined, and presumably no longer + * needed to be passed into the crypto core code. + */ +#define CRYPTO_TFM_MODE_CBC 0 +#define CRYPTO_TFM_MODE_ECB 0 +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + /* + * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new + * API into old API. + */ + + /* Symmetric/Block Cipher */ + struct blkcipher_desc + { + struct crypto_tfm *tfm; + void *info; + }; + #define ecb(X) #X , CRYPTO_TFM_MODE_ECB + #define cbc(X) #X , CRYPTO_TFM_MODE_CBC + #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) + #define crypto_blkcipher_cast(X) X + #define crypto_blkcipher_tfm(X) X + #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) + #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) + #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) + #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) + #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ + crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) + #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ + crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) + #define crypto_blkcipher_set_flags(x, y) /* nop */ + #define crypto_free_blkcipher(x) crypto_free_tfm(x) + #define crypto_free_comp crypto_free_tfm + #define crypto_free_hash crypto_free_tfm + + /* Hash/HMAC/Digest */ + struct hash_desc + { + struct crypto_tfm *tfm; + }; + #define hmac(X) #X , 0 + #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) + #define crypto_hash_cast(X) X + #define crypto_hash_tfm(X) X + #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) + #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) + #define crypto_hash_digest(W, X, Y, Z) \ + crypto_digest_digest((W)->tfm, X, sg_num, Z) + + /* Asymmetric Cipher */ + #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) + + /* Compression */ + #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) + #define crypto_comp_tfm(X) X + #define crypto_comp_cast(X) X + #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) + #define plain(X) #X , 0 +#else + #define ecb(X) "ecb(" #X ")" , 0 + #define cbc(X) "cbc(" #X ")" , 0 + #define hmac(X) "hmac(" #X ")" , 0 + #define plain(X) #X , 0 +#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) +/* no ablkcipher in older kernels */ +#define crypto_alloc_ablkcipher(a,b,c) (NULL) +#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) +#define crypto_ablkcipher_set_flags(a, b) /* nop */ +#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) +#define crypto_has_ablkcipher(a,b,c) (0) +#else +#define HAVE_ABLKCIPHER +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) +/* no ahash in older kernels */ +#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) +#define crypto_alloc_ahash(a,b,c) (NULL) +#define crypto_ahash_digestsize(x) 0 +#else +#define HAVE_AHASH +#endif + +struct crypto_details { + char *alg_name; + int mode; + int sw_type; +}; + +static struct crypto_details crypto_details[] = { + [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, + [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, + [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, + [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, + [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, + [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, + [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, + [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, + [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, + [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, + [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, + [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, + [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, + [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, + [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, + [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, + [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, + [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, + [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, + [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, + [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, + [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, + [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, + [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, + [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, +}; + +int32_t swcr_id = -1; +module_param(swcr_id, int, 0444); +MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); + +int swcr_fail_if_compression_grows = 1; +module_param(swcr_fail_if_compression_grows, int, 0644); +MODULE_PARM_DESC(swcr_fail_if_compression_grows, + "Treat compression that results in more data as a failure"); + +int swcr_no_ahash = 0; +module_param(swcr_no_ahash, int, 0644); +MODULE_PARM_DESC(swcr_no_ahash, + "Do not use async hash/hmac even if available"); + +int swcr_no_ablk = 0; +module_param(swcr_no_ablk, int, 0644); +MODULE_PARM_DESC(swcr_no_ablk, + "Do not use async blk ciphers even if available"); + +static struct swcr_data **swcr_sessions = NULL; +static u_int32_t swcr_sesnum = 0; + +static int swcr_process(device_t, struct cryptop *, int); +static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); +static int swcr_freesession(device_t, u_int64_t); + +static device_method_t swcr_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, swcr_newsession), + DEVMETHOD(cryptodev_freesession,swcr_freesession), + DEVMETHOD(cryptodev_process, swcr_process), +}; + +#define debug swcr_debug +int swcr_debug = 0; +module_param(swcr_debug, int, 0644); +MODULE_PARM_DESC(swcr_debug, "Enable debug"); + +static void swcr_process_req(struct swcr_req *req); + +/* + * somethings just need to be run with user context no matter whether + * the kernel compression libs use vmalloc/vfree for example. + */ + +typedef struct { + struct work_struct wq; + void (*func)(void *arg); + void *arg; +} execute_later_t; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +static void +doing_it_now(struct work_struct *wq) +{ + execute_later_t *w = container_of(wq, execute_later_t, wq); + (w->func)(w->arg); + kfree(w); +} +#else +static void +doing_it_now(void *arg) +{ + execute_later_t *w = (execute_later_t *) arg; + (w->func)(w->arg); + kfree(w); +} +#endif + +static void +execute_later(void (fn)(void *), void *arg) +{ + execute_later_t *w; + + w = (execute_later_t *) kmalloc(sizeof(execute_later_t), SLAB_ATOMIC); + if (w) { + memset(w, '\0', sizeof(w)); + w->func = fn; + w->arg = arg; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + INIT_WORK(&w->wq, doing_it_now); +#else + INIT_WORK(&w->wq, doing_it_now, w); +#endif + schedule_work(&w->wq); + } +} + +/* + * Generate a new software session. + */ +static int +swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) +{ + struct swcr_data **swd; + u_int32_t i; + int error; + char *algo; + int mode; + + dprintk("%s()\n", __FUNCTION__); + if (sid == NULL || cri == NULL) { + dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + if (swcr_sessions) { + for (i = 1; i < swcr_sesnum; i++) + if (swcr_sessions[i] == NULL) + break; + } else + i = 1; /* NB: to silence compiler warning */ + + if (swcr_sessions == NULL || i == swcr_sesnum) { + if (swcr_sessions == NULL) { + i = 1; /* We leave swcr_sessions[0] empty */ + swcr_sesnum = CRYPTO_SW_SESSIONS; + } else + swcr_sesnum *= 2; + + swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); + if (swd == NULL) { + /* Reset session number */ + if (swcr_sesnum == CRYPTO_SW_SESSIONS) + swcr_sesnum = 0; + else + swcr_sesnum /= 2; + dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); + return ENOBUFS; + } + memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); + + /* Copy existing sessions */ + if (swcr_sessions) { + memcpy(swd, swcr_sessions, + (swcr_sesnum / 2) * sizeof(struct swcr_data *)); + kfree(swcr_sessions); + } + + swcr_sessions = swd; + } + + swd = &swcr_sessions[i]; + *sid = i; + + while (cri) { + *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), + SLAB_ATOMIC); + if (*swd == NULL) { + swcr_freesession(NULL, i); + dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); + return ENOBUFS; + } + memset(*swd, 0, sizeof(struct swcr_data)); + + if (cri->cri_alg < 0 || + cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ + printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); + swcr_freesession(NULL, i); + return EINVAL; + } + + algo = crypto_details[cri->cri_alg].alg_name; + if (!algo || !*algo) { + printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); + swcr_freesession(NULL, i); + return EINVAL; + } + + mode = crypto_details[cri->cri_alg].mode; + (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; + (*swd)->sw_alg = cri->cri_alg; + + spin_lock_init(&(*swd)->sw_tfm_lock); + + /* Algorithm specific configuration */ + switch (cri->cri_alg) { + case CRYPTO_NULL_CBC: + cri->cri_klen = 0; /* make it work with crypto API */ + break; + default: + break; + } + + if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { + dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, + algo, mode); + + /* try async first */ + (*swd)->sw_tfm = swcr_no_ablk ? NULL : + crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); + if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) { + dprintk("%s %s cipher is async\n", __FUNCTION__, algo); + (*swd)->sw_type |= SW_TYPE_ASYNC; + } else { + (*swd)->sw_tfm = crypto_blkcipher_tfm( + crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); + if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) + dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); + } + if (!(*swd)->sw_tfm || IS_ERR((*swd)->sw_tfm)) { + int err; + dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", + algo,mode); + err = IS_ERR((*swd)->sw_tfm) ? -(PTR_ERR((*swd)->sw_tfm)) : EINVAL; + (*swd)->sw_tfm = NULL; /* ensure NULL */ + swcr_freesession(NULL, i); + return err; + } + + if (debug) { + dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", + __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); + for (i = 0; i < (cri->cri_klen + 7) / 8; i++) + dprintk("%s0x%x", (i % 8) ? " " : "\n ", + cri->cri_key[i] & 0xff); + dprintk("\n"); + } + if ((*swd)->sw_type & SW_TYPE_ASYNC) { + /* OCF doesn't enforce keys */ + crypto_ablkcipher_set_flags( + __crypto_ablkcipher_cast((*swd)->sw_tfm), + CRYPTO_TFM_REQ_WEAK_KEY); + error = crypto_ablkcipher_setkey( + __crypto_ablkcipher_cast((*swd)->sw_tfm), + cri->cri_key, (cri->cri_klen + 7) / 8); + } else { + /* OCF doesn't enforce keys */ + crypto_blkcipher_set_flags( + crypto_blkcipher_cast((*swd)->sw_tfm), + CRYPTO_TFM_REQ_WEAK_KEY); + error = crypto_blkcipher_setkey( + crypto_blkcipher_cast((*swd)->sw_tfm), + cri->cri_key, (cri->cri_klen + 7) / 8); + } + if (error) { + printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, + (*swd)->sw_tfm->crt_flags); + swcr_freesession(NULL, i); + return error; + } + } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { + dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, + algo, mode); + + /* try async first */ + (*swd)->sw_tfm = swcr_no_ahash ? NULL : + crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); + if ((*swd)->sw_tfm) { + dprintk("%s %s hash is async\n", __FUNCTION__, algo); + (*swd)->sw_type |= SW_TYPE_ASYNC; + } else { + dprintk("%s %s hash is sync\n", __FUNCTION__, algo); + (*swd)->sw_tfm = crypto_hash_tfm( + crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); + } + + if (!(*swd)->sw_tfm) { + dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", + algo, mode); + swcr_freesession(NULL, i); + return EINVAL; + } + + (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; + (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, + SLAB_ATOMIC); + if ((*swd)->u.hmac.sw_key == NULL) { + swcr_freesession(NULL, i); + dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); + return ENOBUFS; + } + memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); + if (cri->cri_mlen) { + (*swd)->u.hmac.sw_mlen = cri->cri_mlen; + } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { + (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( + __crypto_ahash_cast((*swd)->sw_tfm)); + } else { + (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( + crypto_hash_cast((*swd)->sw_tfm)); + } + } else if ((*swd)->sw_type & SW_TYPE_COMP) { + (*swd)->sw_tfm = crypto_comp_tfm( + crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); + if (!(*swd)->sw_tfm) { + dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", + algo, mode); + swcr_freesession(NULL, i); + return EINVAL; + } + (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); + if ((*swd)->u.sw_comp_buf == NULL) { + swcr_freesession(NULL, i); + dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); + return ENOBUFS; + } + } else { + printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); + swcr_freesession(NULL, i); + return EINVAL; + } + + cri = cri->cri_next; + swd = &((*swd)->sw_next); + } + return 0; +} + +/* + * Free a session. + */ +static int +swcr_freesession(device_t dev, u_int64_t tid) +{ + struct swcr_data *swd; + u_int32_t sid = CRYPTO_SESID2LID(tid); + + dprintk("%s()\n", __FUNCTION__); + if (sid > swcr_sesnum || swcr_sessions == NULL || + swcr_sessions[sid] == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return(EINVAL); + } + + /* Silently accept and return */ + if (sid == 0) + return(0); + + while ((swd = swcr_sessions[sid]) != NULL) { + swcr_sessions[sid] = swd->sw_next; + if (swd->sw_tfm) { + switch (swd->sw_type & SW_TYPE_ALG_AMASK) { +#ifdef HAVE_AHASH + case SW_TYPE_AHMAC: + case SW_TYPE_AHASH: + crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); + break; +#endif +#ifdef HAVE_ABLKCIPHER + case SW_TYPE_ABLKCIPHER: + crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); + break; +#endif + case SW_TYPE_BLKCIPHER: + crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); + break; + case SW_TYPE_HMAC: + case SW_TYPE_HASH: + crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); + break; + case SW_TYPE_COMP: + if (in_interrupt()) + execute_later((void (*)(void *))crypto_free_comp, (void *)crypto_comp_cast(swd->sw_tfm)); + else + crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); + break; + default: + crypto_free_tfm(swd->sw_tfm); + break; + } + swd->sw_tfm = NULL; + } + if (swd->sw_type & SW_TYPE_COMP) { + if (swd->u.sw_comp_buf) + kfree(swd->u.sw_comp_buf); + } else { + if (swd->u.hmac.sw_key) + kfree(swd->u.hmac.sw_key); + } + kfree(swd); + } + return 0; +} + +static void swcr_process_req_complete(struct swcr_req *req) +{ + dprintk("%s()\n", __FUNCTION__); + + if (req->sw->sw_type & SW_TYPE_INUSE) { + unsigned long flags; + spin_lock_irqsave(&req->sw->sw_tfm_lock, flags); + req->sw->sw_type &= ~SW_TYPE_INUSE; + spin_unlock_irqrestore(&req->sw->sw_tfm_lock, flags); + } + + if (req->crp->crp_etype) + goto done; + + switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { +#if defined(HAVE_AHASH) + case SW_TYPE_AHMAC: + case SW_TYPE_AHASH: + crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, + req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); + ahash_request_free(req->crypto_req); + break; +#endif +#if defined(HAVE_ABLKCIPHER) + case SW_TYPE_ABLKCIPHER: + ablkcipher_request_free(req->crypto_req); + break; +#endif + case SW_TYPE_CIPHER: + case SW_TYPE_HMAC: + case SW_TYPE_HASH: + case SW_TYPE_COMP: + case SW_TYPE_BLKCIPHER: + break; + default: + req->crp->crp_etype = EINVAL; + goto done; + } + + req->crd = req->crd->crd_next; + if (req->crd) { + swcr_process_req(req); + return; + } + +done: + dprintk("%s crypto_done %p\n", __FUNCTION__, req); + crypto_done(req->crp); + kmem_cache_free(swcr_req_cache, req); +} + +#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) +static void swcr_process_callback(struct crypto_async_request *creq, int err) +{ + struct swcr_req *req = creq->data; + + dprintk("%s()\n", __FUNCTION__); + if (err) { + if (err == -EINPROGRESS) + return; + dprintk("%s() fail %d\n", __FUNCTION__, -err); + req->crp->crp_etype = -err; + } + + swcr_process_req_complete(req); +} +#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ + + +static void swcr_process_req(struct swcr_req *req) +{ + struct swcr_data *sw; + struct cryptop *crp = req->crp; + struct cryptodesc *crd = req->crd; + struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; + struct uio *uiop = (struct uio *) crp->crp_buf; + int sg_num, sg_len, skip; + + dprintk("%s()\n", __FUNCTION__); + + /* + * Find the crypto context. + * + * XXX Note that the logic here prevents us from having + * XXX the same algorithm multiple times in a session + * XXX (or rather, we can but it won't give us the right + * XXX results). To do that, we'd need some way of differentiating + * XXX between the various instances of an algorithm (so we can + * XXX locate the correct crypto context). + */ + for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) + ; + + /* No such context ? */ + if (sw == NULL) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + goto done; + } + + /* + * for some types we need to ensure only one user as info is stored in + * the tfm during an operation that can get corrupted + */ + switch (sw->sw_type & SW_TYPE_ALG_AMASK) { +#ifdef HAVE_AHASH + case SW_TYPE_AHMAC: + case SW_TYPE_AHASH: +#endif + case SW_TYPE_HMAC: + case SW_TYPE_HASH: { + unsigned long flags; + spin_lock_irqsave(&sw->sw_tfm_lock, flags); + if (sw->sw_type & SW_TYPE_INUSE) { + spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); + execute_later((void (*)(void *))swcr_process_req, (void *)req); + return; + } + sw->sw_type |= SW_TYPE_INUSE; + spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); + } break; + } + + req->sw = sw; + skip = crd->crd_skip; + + /* + * setup the SG list skip from the start of the buffer + */ + memset(req->sg, 0, sizeof(req->sg)); + sg_init_table(req->sg, SCATTERLIST_MAX); + if (crp->crp_flags & CRYPTO_F_SKBUF) { + int i, len; + + sg_num = 0; + sg_len = 0; + + if (skip < skb_headlen(skb)) { + len = skb_headlen(skb) - skip; + if (len + sg_len > crd->crd_len) + len = crd->crd_len - sg_len; + sg_set_page(&req->sg[sg_num], + virt_to_page(skb->data + skip), len, + offset_in_page(skb->data + skip)); + sg_len += len; + sg_num++; + skip = 0; + } else + skip -= skb_headlen(skb); + + for (i = 0; sg_len < crd->crd_len && + i < skb_shinfo(skb)->nr_frags && + sg_num < SCATTERLIST_MAX; i++) { + if (skip < skb_shinfo(skb)->frags[i].size) { + len = skb_shinfo(skb)->frags[i].size - skip; + if (len + sg_len > crd->crd_len) + len = crd->crd_len - sg_len; + sg_set_page(&req->sg[sg_num], + skb_frag_page(&skb_shinfo(skb)->frags[i]), + len, + skb_shinfo(skb)->frags[i].page_offset + skip); + sg_len += len; + sg_num++; + skip = 0; + } else + skip -= skb_shinfo(skb)->frags[i].size; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + int len; + + sg_len = 0; + for (sg_num = 0; sg_len < crd->crd_len && + sg_num < uiop->uio_iovcnt && + sg_num < SCATTERLIST_MAX; sg_num++) { + if (skip <= uiop->uio_iov[sg_num].iov_len) { + len = uiop->uio_iov[sg_num].iov_len - skip; + if (len + sg_len > crd->crd_len) + len = crd->crd_len - sg_len; + sg_set_page(&req->sg[sg_num], + virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), + len, + offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); + sg_len += len; + skip = 0; + } else + skip -= uiop->uio_iov[sg_num].iov_len; + } + } else { + sg_len = (crp->crp_ilen - skip); + if (sg_len > crd->crd_len) + sg_len = crd->crd_len; + sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), + sg_len, offset_in_page(crp->crp_buf + skip)); + sg_num = 1; + } + if (sg_num > 0) + sg_mark_end(&req->sg[sg_num-1]); + + switch (sw->sw_type & SW_TYPE_ALG_AMASK) { + +#ifdef HAVE_AHASH + case SW_TYPE_AHMAC: + case SW_TYPE_AHASH: + { + int ret; + + /* check we have room for the result */ + if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { + dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " + "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, + crd->crd_inject, sw->u.hmac.sw_mlen); + crp->crp_etype = EINVAL; + goto done; + } + + req->crypto_req = + ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_ATOMIC); + if (!req->crypto_req) { + crp->crp_etype = ENOMEM; + dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); + goto done; + } + + ahash_request_set_callback(req->crypto_req, + CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); + + memset(req->result, 0, sizeof(req->result)); + + if (sw->sw_type & SW_TYPE_AHMAC) + crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), + sw->u.hmac.sw_key, sw->u.hmac.sw_klen); + ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); + ret = crypto_ahash_digest(req->crypto_req); + switch (ret) { + case -EINPROGRESS: + case -EBUSY: + return; + default: + case 0: + dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); + crp->crp_etype = ret; + goto done; + } + } break; +#endif /* HAVE_AHASH */ + +#ifdef HAVE_ABLKCIPHER + case SW_TYPE_ABLKCIPHER: { + int ret; + unsigned char *ivp = req->iv; + int ivsize = + crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); + + if (sg_len < crypto_ablkcipher_blocksize( + __crypto_ablkcipher_cast(sw->sw_tfm))) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, + sg_len, crypto_ablkcipher_blocksize( + __crypto_ablkcipher_cast(sw->sw_tfm))); + goto done; + } + + if (ivsize > sizeof(req->iv)) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + goto done; + } + + req->crypto_req = ablkcipher_request_alloc( + __crypto_ablkcipher_cast(sw->sw_tfm), GFP_ATOMIC); + if (!req->crypto_req) { + crp->crp_etype = ENOMEM; + dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", + __FILE__, __LINE__); + goto done; + } + + ablkcipher_request_set_callback(req->crypto_req, + CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); + + if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { + int i, error; + + if (debug) { + dprintk("%s key:", __FUNCTION__); + for (i = 0; i < (crd->crd_klen + 7) / 8; i++) + dprintk("%s0x%x", (i % 8) ? " " : "\n ", + crd->crd_key[i] & 0xff); + dprintk("\n"); + } + /* OCF doesn't enforce keys */ + crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), + CRYPTO_TFM_REQ_WEAK_KEY); + error = crypto_ablkcipher_setkey( + __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, + (crd->crd_klen + 7) / 8); + if (error) { + dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", + error, sw->sw_tfm->crt_flags); + crp->crp_etype = -error; + } + } + + if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ + + if (crd->crd_flags & CRD_F_IV_EXPLICIT) + ivp = crd->crd_iv; + else + get_random_bytes(ivp, ivsize); + /* + * do we have to copy the IV back to the buffer ? + */ + if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { + crypto_copyback(crp->crp_flags, crp->crp_buf, + crd->crd_inject, ivsize, (caddr_t)ivp); + } + ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, + sg_len, ivp); + ret = crypto_ablkcipher_encrypt(req->crypto_req); + + } else { /*decrypt */ + + if (crd->crd_flags & CRD_F_IV_EXPLICIT) + ivp = crd->crd_iv; + else + crypto_copydata(crp->crp_flags, crp->crp_buf, + crd->crd_inject, ivsize, (caddr_t)ivp); + ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, + sg_len, ivp); + ret = crypto_ablkcipher_decrypt(req->crypto_req); + } + + switch (ret) { + case -EINPROGRESS: + case -EBUSY: + return; + default: + case 0: + dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); + crp->crp_etype = ret; + goto done; + } + } break; +#endif /* HAVE_ABLKCIPHER */ + + case SW_TYPE_BLKCIPHER: { + unsigned char iv[EALG_MAX_BLOCK_LEN]; + unsigned char *ivp = iv; + struct blkcipher_desc desc; + int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); + + if (sg_len < crypto_blkcipher_blocksize( + crypto_blkcipher_cast(sw->sw_tfm))) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, + sg_len, crypto_blkcipher_blocksize( + crypto_blkcipher_cast(sw->sw_tfm))); + goto done; + } + + if (ivsize > sizeof(iv)) { + crp->crp_etype = EINVAL; + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + goto done; + } + + if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { + int i, error; + + if (debug) { + dprintk("%s key:", __FUNCTION__); + for (i = 0; i < (crd->crd_klen + 7) / 8; i++) + dprintk("%s0x%x", (i % 8) ? " " : "\n ", + crd->crd_key[i] & 0xff); + dprintk("\n"); + } + /* OCF doesn't enforce keys */ + crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), + CRYPTO_TFM_REQ_WEAK_KEY); + error = crypto_blkcipher_setkey( + crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, + (crd->crd_klen + 7) / 8); + if (error) { + dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", + error, sw->sw_tfm->crt_flags); + crp->crp_etype = -error; + } + } + + memset(&desc, 0, sizeof(desc)); + desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); + + if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ + + if (crd->crd_flags & CRD_F_IV_EXPLICIT) { + ivp = crd->crd_iv; + } else { + get_random_bytes(ivp, ivsize); + } + /* + * do we have to copy the IV back to the buffer ? + */ + if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { + crypto_copyback(crp->crp_flags, crp->crp_buf, + crd->crd_inject, ivsize, (caddr_t)ivp); + } + desc.info = ivp; + crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); + + } else { /*decrypt */ + + if (crd->crd_flags & CRD_F_IV_EXPLICIT) { + ivp = crd->crd_iv; + } else { + crypto_copydata(crp->crp_flags, crp->crp_buf, + crd->crd_inject, ivsize, (caddr_t)ivp); + } + desc.info = ivp; + crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); + } + } break; + + case SW_TYPE_HMAC: + case SW_TYPE_HASH: + { + char result[HASH_MAX_LEN]; + struct hash_desc desc; + + /* check we have room for the result */ + if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { + dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " + "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, + crd->crd_inject, sw->u.hmac.sw_mlen); + crp->crp_etype = EINVAL; + goto done; + } + + memset(&desc, 0, sizeof(desc)); + desc.tfm = crypto_hash_cast(sw->sw_tfm); + + memset(result, 0, sizeof(result)); + + if (sw->sw_type & SW_TYPE_HMAC) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) + crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, + req->sg, sg_num, result); +#else + crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, + sw->u.hmac.sw_klen); + crypto_hash_digest(&desc, req->sg, sg_len, result); +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ + + } else { /* SW_TYPE_HASH */ + crypto_hash_digest(&desc, req->sg, sg_len, result); + } + + crypto_copyback(crp->crp_flags, crp->crp_buf, + crd->crd_inject, sw->u.hmac.sw_mlen, result); + } + break; + + case SW_TYPE_COMP: { + void *ibuf = NULL; + void *obuf = sw->u.sw_comp_buf; + int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; + int ret = 0; + + /* + * we need to use an additional copy if there is more than one + * input chunk since the kernel comp routines do not handle + * SG yet. Otherwise we just use the input buffer as is. + * Rather than allocate another buffer we just split the tmp + * buffer we already have. + * Perhaps we should just use zlib directly ? + */ + if (sg_num > 1) { + int blk; + + ibuf = obuf; + for (blk = 0; blk < sg_num; blk++) { + memcpy(obuf, sg_virt(&req->sg[blk]), + req->sg[blk].length); + obuf += req->sg[blk].length; + } + olen -= sg_len; + } else + ibuf = sg_virt(&req->sg[0]); + + if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ + ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), + ibuf, ilen, obuf, &olen); + if (!ret && olen > crd->crd_len) { + dprintk("cryptosoft: ERANGE compress %d into %d\n", + crd->crd_len, olen); + if (swcr_fail_if_compression_grows) + ret = ERANGE; + } + } else { /* decompress */ + ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), + ibuf, ilen, obuf, &olen); + if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { + dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " + "space for %d,at offset %d\n", + crd->crd_len, olen, crp->crp_olen, crd->crd_inject); + ret = ETOOSMALL; + } + } + if (ret) + dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); + + /* + * on success copy result back, + * linux crpyto API returns -errno, we need to fix that + */ + crp->crp_etype = ret < 0 ? -ret : ret; + if (ret == 0) { + /* copy back the result and return it's size */ + crypto_copyback(crp->crp_flags, crp->crp_buf, + crd->crd_inject, olen, obuf); + crp->crp_olen = olen; + } + } break; + + default: + /* Unknown/unsupported algorithm */ + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + crp->crp_etype = EINVAL; + goto done; + } + +done: + swcr_process_req_complete(req); +} + + +/* + * Process a crypto request. + */ +static int +swcr_process(device_t dev, struct cryptop *crp, int hint) +{ + struct swcr_req *req = NULL; + u_int32_t lid; + + dprintk("%s()\n", __FUNCTION__); + /* Sanity check */ + if (crp == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + crp->crp_etype = 0; + + if (crp->crp_desc == NULL || crp->crp_buf == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + crp->crp_etype = EINVAL; + goto done; + } + + lid = crp->crp_sid & 0xffffffff; + if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || + swcr_sessions[lid] == NULL) { + crp->crp_etype = ENOENT; + dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); + goto done; + } + + /* + * do some error checking outside of the loop for SKB and IOV processing + * this leaves us with valid skb or uiop pointers for later + */ + if (crp->crp_flags & CRYPTO_F_SKBUF) { + struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; + if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { + printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, + skb_shinfo(skb)->nr_frags); + goto done; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + struct uio *uiop = (struct uio *) crp->crp_buf; + if (uiop->uio_iovcnt > SCATTERLIST_MAX) { + printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, + uiop->uio_iovcnt); + goto done; + } + } + + /* + * setup a new request ready for queuing + */ + req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); + if (req == NULL) { + dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); + crp->crp_etype = ENOMEM; + goto done; + } + memset(req, 0, sizeof(*req)); + + req->sw_head = swcr_sessions[lid]; + req->crp = crp; + req->crd = crp->crp_desc; + + swcr_process_req(req); + return 0; + +done: + crypto_done(crp); + if (req) + kmem_cache_free(swcr_req_cache, req); + return 0; +} + + +static int +cryptosoft_init(void) +{ + int i, sw_type, mode; + char *algo; + + dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); + + swcr_req_cache = kmem_cache_create("cryptosoft_req", + sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) + , NULL +#endif + ); + if (!swcr_req_cache) { + printk("cryptosoft: failed to create request cache\n"); + return -ENOENT; + } + + softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); + + swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), + CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); + if (swcr_id < 0) { + printk("cryptosoft: Software crypto device cannot initialize!"); + return -ENODEV; + } + +#define REGISTER(alg) \ + crypto_register(swcr_id, alg, 0,0) + + for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { + int found; + + algo = crypto_details[i].alg_name; + if (!algo || !*algo) { + dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); + continue; + } + + mode = crypto_details[i].mode; + sw_type = crypto_details[i].sw_type; + + found = 0; + switch (sw_type & SW_TYPE_ALG_MASK) { + case SW_TYPE_CIPHER: + found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); + break; + case SW_TYPE_HMAC: + found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); + break; + case SW_TYPE_HASH: + found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); + break; + case SW_TYPE_COMP: + found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); + break; + case SW_TYPE_BLKCIPHER: + found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); + if (!found && !swcr_no_ablk) + found = crypto_has_ablkcipher(algo, 0, 0); + break; + } + if (found) { + REGISTER(i); + } else { + dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", + __FUNCTION__, sw_type, i, algo); + } + } + return 0; +} + +static void +cryptosoft_exit(void) +{ + dprintk("%s()\n", __FUNCTION__); + crypto_unregister_all(swcr_id); + swcr_id = -1; + kmem_cache_destroy(swcr_req_cache); +} + +late_initcall(cryptosoft_init); +module_exit(cryptosoft_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); diff --git a/target/linux/generic/files/crypto/ocf/ep80579/Makefile b/target/linux/generic/files/crypto/ocf/ep80579/Makefile new file mode 100644 index 0000000..9aab295 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ep80579/Makefile @@ -0,0 +1,119 @@ +######################################################################### +# +# Targets supported +# all - builds everything and installs +# install - identical to all +# depend - build dependencies +# clean - clears derived objects except the .depend files +# distclean- clears all derived objects and the .depend file +# +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# version: Security.L.1.0.2-229 +############################################################################ + + +####################Common variables and definitions######################## + +ifndef ICP_ROOT +$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ + "-> setenv ICP_ROOT ") +all fastdep: + : +else + +ifndef KERNEL_SOURCE_ROOT +$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ + "-> setenv KERNEL_SOURCE_ROOT ") +endif + +# Ensure The ENV_DIR environmental var is defined. +ifndef ICP_ENV_DIR +$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ + "-> setenv ICP_ENV_DIR ") +endif + +#Add your project environment Makefile +include ${ICP_ENV_DIR}/environment.mk + +#include the makefile with all the default and common Make variable definitions +include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk + +#Add the name for the executable, Library or Module output definitions +OUTPUT_NAME= icp_ocf + +# List of Source Files to be compiled +SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c + +#common includes between all supported OSes +INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ +-I${ICP_OCF_SRC_DIR} + +# The location of the os level makefile needs to be changed. +include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk + +# On the line directly below list the outputs you wish to build for, +# e.g "lib_static lib_shared exe module" as shown below +install: module + +###################Include rules makefiles######################## +include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk +###################End of Rules inclusion######################### + +endif diff --git a/target/linux/generic/files/crypto/ocf/ep80579/environment.mk b/target/linux/generic/files/crypto/ocf/ep80579/environment.mk new file mode 100644 index 0000000..1a663e5 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ep80579/environment.mk @@ -0,0 +1,78 @@ + ########################################################################### + # +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# version: Security.L.1.0.130 + # + ########################################################################### + + +ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac +ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr +ICP_API_DIR=$(ICP_ROOT)/Acceleration/include +ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/ +ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),) +ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/ +endif + +ICP_OS_LEVEL?=kernel_space + +ICP_OS?=linux_2.6 + +ICP_CORE?=ia + diff --git a/target/linux/generic/files/crypto/ocf/ep80579/icp_asym.c b/target/linux/generic/files/crypto/ocf/ep80579/icp_asym.c new file mode 100644 index 0000000..d2641c5 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ep80579/icp_asym.c @@ -0,0 +1,1334 @@ +/*************************************************************************** + * + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * version: Security.L.1.0.2-229 + * + ***************************************************************************/ + +#include "icp_ocf.h" + +/*The following define values (containing the word 'INDEX') are used to find +the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). +These values were found through analysis of the OCF OpenSSL patch. If the +calling program uses different input buffer positions, these defines will have +to be changed.*/ + +/*DIFFIE HELLMAN buffer index values*/ +#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) +#define ICP_DH_KRP_PARAM_BASE_INDEX (1) +#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) +#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) + +/*MOD EXP buffer index values*/ +#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) +#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) +#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) +#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) + +/*MOD EXP CRT buffer index values*/ +#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) +#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) +#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) +#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) +#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) +#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) +#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) + +/*DSA sign buffer index values*/ +#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) +#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) +#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) +#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) +#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) +#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) +#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) + +/*DSA verify buffer index values*/ +#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) +#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) +#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) +#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) +#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) +#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) +#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) + +/*DSA sign prime Q vs random number K size check values*/ +#define DONT_RUN_LESS_THAN_CHECK (0) +#define FAIL_A_IS_GREATER_THAN_B (1) +#define FAIL_A_IS_EQUAL_TO_B (1) +#define SUCCESS_A_IS_LESS_THAN_B (0) +#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) + +/* We need to set a cryptokp success value just in case it is set or allocated + and not set to zero outside of this module */ +#define CRYPTO_OP_SUCCESS (0) + +/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ +static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); + +/*Function to compute a Modular Exponentiation (Mod Exp)*/ +static int icp_ocfDrvModExp(struct cryptkop *krp); + +/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ +static int icp_ocfDrvModExpCRT(struct cryptkop *krp); + +/*Helper function to compute whether the first big number argument is less than + the second big number argument */ +static int +icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); + +/*Function to sign an input with DSA R and S keys*/ +static int icp_ocfDrvDsaSign(struct cryptkop *krp); + +/*Function to Verify a DSA buffer signature*/ +static int icp_ocfDrvDsaVerify(struct cryptkop *krp); + +/*Callback function for DH operation*/ +static void +icp_ocfDrvDhP1CallBack(void *callbackTag, + CpaStatus status, + void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); + +/*Callback function for ME operation*/ +static void +icp_ocfDrvModExpCallBack(void *callbackTag, + CpaStatus status, + void *pOpData, CpaFlatBuffer * pResult); + +/*Callback function for ME CRT operation*/ +static void +icp_ocfDrvModExpCRTCallBack(void *callbackTag, + CpaStatus status, + void *pOpData, CpaFlatBuffer * pOutputData); + +/*Callback function for DSA sign operation*/ +static void +icp_ocfDrvDsaRSSignCallBack(void *callbackTag, + CpaStatus status, + void *pOpData, + CpaBoolean protocolStatus, + CpaFlatBuffer * pR, CpaFlatBuffer * pS); + +/*Callback function for DSA Verify operation*/ +static void +icp_ocfDrvDsaVerifyCallBack(void *callbackTag, + CpaStatus status, + void *pOpData, CpaBoolean verifyStatus); + +/* Name : icp_ocfDrvPkeProcess + * + * Description : This function will choose which PKE process to follow + * based on the input arguments + */ +int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) +{ + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + + if (NULL == krp) { + DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", + __FUNCTION__, krp); + return EINVAL; + } + + if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { + krp->krp_status = ECANCELED; + return ECANCELED; + } + + switch (krp->krp_op) { + case CRK_DH_COMPUTE_KEY: + DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); + lacStatus = icp_ocfDrvDHComputeKey(krp); + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " + "(%d).\n", __FUNCTION__, lacStatus); + krp->krp_status = ECANCELED; + return ECANCELED; + } + + break; + + case CRK_MOD_EXP: + DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); + lacStatus = icp_ocfDrvModExp(krp); + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", + __FUNCTION__, lacStatus); + krp->krp_status = ECANCELED; + return ECANCELED; + } + + break; + + case CRK_MOD_EXP_CRT: + DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); + lacStatus = icp_ocfDrvModExpCRT(krp); + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): icp_ocfDrvModExpCRT " + "failed (%d).\n", __FUNCTION__, lacStatus); + krp->krp_status = ECANCELED; + return ECANCELED; + } + + break; + + case CRK_DSA_SIGN: + DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); + lacStatus = icp_ocfDrvDsaSign(krp); + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): icp_ocfDrvDsaSign " + "failed (%d).\n", __FUNCTION__, lacStatus); + krp->krp_status = ECANCELED; + return ECANCELED; + } + + break; + + case CRK_DSA_VERIFY: + DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); + lacStatus = icp_ocfDrvDsaVerify(krp); + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): icp_ocfDrvDsaVerify " + "failed (%d).\n", __FUNCTION__, lacStatus); + krp->krp_status = ECANCELED; + return ECANCELED; + } + + break; + + default: + EPRINTK("%s(): Asymettric function not " + "supported (%d).\n", __FUNCTION__, krp->krp_op); + krp->krp_status = EOPNOTSUPP; + return EOPNOTSUPP; + } + + return ICP_OCF_DRV_STATUS_SUCCESS; +} + +/* Name : icp_ocfDrvSwapBytes + * + * Description : This function is used to swap the byte order of a buffer. + * It has been seen that in general we are passed little endian byte order + * buffers, but LAC only accepts big endian byte order buffers. + */ +static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) +{ + + int i; + u_int8_t *end_ptr; + u_int8_t hold_val; + + end_ptr = num + (buff_len_bytes - 1); + buff_len_bytes = buff_len_bytes >> 1; + for (i = 0; i < buff_len_bytes; i++) { + hold_val = *num; + *num = *end_ptr; + num++; + *end_ptr = hold_val; + end_ptr--; + } +} + +/* Name : icp_ocfDrvDHComputeKey + * + * Description : This function will map Diffie Hellman calls from OCF + * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and + * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases + * break down to a modular exponentiation. + */ +static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) +{ + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + void *callbackTag = NULL; + CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; + CpaFlatBuffer *pLocalOctetStringPV = NULL; + uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; + + /* Input checks - check prime is a multiple of 8 bits to allow for + allocation later */ + dh_prime_len_bits = + (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); + + /* LAC can reject prime lengths based on prime key sizes, we just + need to make sure we can allocate space for the base and + exponent buffers correctly */ + if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { + APRINTK("%s(): Warning Prime number buffer size is not a " + "multiple of 8 bits\n", __FUNCTION__); + } + + /* Result storage space should be the same size as the prime as this + value can take up the same amount of storage space */ + if (dh_prime_len_bits != + krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { + DPRINTK("%s(): Return Buffer must be the same size " + "as the Prime buffer\n", __FUNCTION__); + krp->krp_status = EINVAL; + return EINVAL; + } + /* Switch to size in bytes */ + BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); + + callbackTag = krp; + +/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting +called in interrupt context*/ + pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); + if (NULL == pPhase1OpData) { + APRINTK("%s():Failed to get memory for key gen data\n", + __FUNCTION__); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + pLocalOctetStringPV = + icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); + if (NULL == pLocalOctetStringPV) { + APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", + __FUNCTION__); + ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + /* Link parameters */ + pPhase1OpData->primeP.pData = + krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; + + pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; + + icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); + + pPhase1OpData->baseG.pData = + krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; + + BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, + krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); + + icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, + pPhase1OpData->baseG.dataLenInBytes); + + pPhase1OpData->privateValueX.pData = + krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; + + BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, + krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, + pPhase1OpData->privateValueX.dataLenInBytes); + + /* Output parameters */ + pLocalOctetStringPV->pData = + krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; + + BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, + krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); + + lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, + icp_ocfDrvDhP1CallBack, + callbackTag, pPhase1OpData, + pLocalOctetStringPV); + + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", + __FUNCTION__, lacStatus); + icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); + ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); + } + + return lacStatus; +} + +/* Name : icp_ocfDrvModExp + * + * Description : This function will map ordinary Modular Exponentiation calls + * from OCF to the LAC API. + * + */ +static int icp_ocfDrvModExp(struct cryptkop *krp) +{ + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + void *callbackTag = NULL; + CpaCyLnModExpOpData *pModExpOpData = NULL; + CpaFlatBuffer *pResult = NULL; + + if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % + NUM_BITS_IN_BYTE) != 0) { + DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " + "multiple of 8 bits\n", __FUNCTION__, + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. + crp_nbits); + } + + /* Result storage space should be the same size as the prime as this + value can take up the same amount of storage space */ + if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { + APRINTK("%s(): Return Buffer size must be the same or" + " greater than the Modulus buffer\n", __FUNCTION__); + krp->krp_status = EINVAL; + return EINVAL; + } + + callbackTag = krp; + + pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); + if (NULL == pModExpOpData) { + APRINTK("%s():Failed to get memory for key gen data\n", + __FUNCTION__); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); + if (NULL == pResult) { + APRINTK("%s():Failed to get memory for ModExp result\n", + __FUNCTION__); + ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + /* Link parameters */ + pModExpOpData->modulus.pData = + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; + BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, + pModExpOpData->modulus.dataLenInBytes); + + DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> + krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); + pModExpOpData->base.pData = + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; + BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. + crp_nbits); + icp_ocfDrvSwapBytes(pModExpOpData->base.pData, + pModExpOpData->base.dataLenInBytes); + + pModExpOpData->exponent.pData = + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; + BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, + pModExpOpData->exponent.dataLenInBytes); + /* Output parameters */ + pResult->pData = + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, + BITS_TO_BYTES(pResult->dataLenInBytes, + krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. + crp_nbits); + + lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, + icp_ocfDrvModExpCallBack, + callbackTag, pModExpOpData, pResult); + + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): Mod Exp Operation failed (%d).\n", + __FUNCTION__, lacStatus); + krp->krp_status = ECANCELED; + icp_ocfDrvFreeFlatBuffer(pResult); + ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); + } + + return lacStatus; +} + +/* Name : icp_ocfDrvModExpCRT + * + * Description : This function will map ordinary Modular Exponentiation Chinese + * Remainder Theorem implementaion calls from OCF to the LAC API. + * + * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 + * decrypt operation. Therefore P and Q input values must always be prime + * numbers. Although basic primality checks are done in LAC, it is up to the + * user to do any correct prime number checking before passing the inputs. + */ +static int icp_ocfDrvModExpCRT(struct cryptkop *krp) +{ + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; + void *callbackTag = NULL; + CpaFlatBuffer *pOutputData = NULL; + + /*Parameter input checks are all done by LAC, no need to repeat + them here. */ + callbackTag = krp; + + rsaDecryptOpData = + icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); + if (NULL == rsaDecryptOpData) { + APRINTK("%s():Failed to get memory" + " for MOD EXP CRT Op data struct\n", __FUNCTION__); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + rsaDecryptOpData->pRecipientPrivateKey + = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); + if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { + APRINTK("%s():Failed to get memory for MOD EXP CRT" + " private key values struct\n", __FUNCTION__); + ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + rsaDecryptOpData->pRecipientPrivateKey-> + version = CPA_CY_RSA_VERSION_TWO_PRIME; + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; + + pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); + if (NULL == pOutputData) { + APRINTK("%s():Failed to get memory" + " for MOD EXP CRT output data\n", __FUNCTION__); + ICP_CACHE_FREE(drvRSAPrivateKey_zone, + rsaDecryptOpData->pRecipientPrivateKey); + ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + rsaDecryptOpData->pRecipientPrivateKey-> + version = CPA_CY_RSA_VERSION_TWO_PRIME; + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; + + /* Link parameters */ + rsaDecryptOpData->inputData.pData = + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; + BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, + rsaDecryptOpData->inputData.dataLenInBytes); + + rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; + BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. + prime1P.dataLenInBytes, + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.prime1P.pData, + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.prime1P.dataLenInBytes); + + rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; + BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. + prime2Q.dataLenInBytes, + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.prime2Q.pData, + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.prime2Q.dataLenInBytes); + + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.exponent1Dp.pData = + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; + BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. + exponent1Dp.dataLenInBytes, + krp-> + krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.exponent1Dp.pData, + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.exponent1Dp.dataLenInBytes); + + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.exponent2Dq.pData = + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; + BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.exponent2Dq.dataLenInBytes, + krp-> + krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.exponent2Dq.pData, + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.exponent2Dq.dataLenInBytes); + + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.coefficientQInv.pData = + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; + BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.coefficientQInv.dataLenInBytes, + krp-> + krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.coefficientQInv.pData, + rsaDecryptOpData->pRecipientPrivateKey-> + privateKeyRep2.coefficientQInv.dataLenInBytes); + + /* Output Parameter */ + pOutputData->pData = + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; + BITS_TO_BYTES(pOutputData->dataLenInBytes, + krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. + crp_nbits); + + lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, + icp_ocfDrvModExpCRTCallBack, + callbackTag, rsaDecryptOpData, pOutputData); + + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", + __FUNCTION__, lacStatus); + krp->krp_status = ECANCELED; + icp_ocfDrvFreeFlatBuffer(pOutputData); + ICP_CACHE_FREE(drvRSAPrivateKey_zone, + rsaDecryptOpData->pRecipientPrivateKey); + ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); + } + + return lacStatus; +} + +/* Name : icp_ocfDrvCheckALessThanB + * + * Description : This function will check whether the first argument is less + * than the second. It is used to check whether the DSA RS sign Random K + * value is less than the Prime Q value (as defined in the specification) + * + */ +static int +icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) +{ + + uint8_t *MSB_K = pK->pData; + uint8_t *MSB_Q = pQ->pData; + uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; + + if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { + return FAIL_A_IS_GREATER_THAN_B; + } + +/*Check MSBs +if A == B, check next MSB +if A > B, return A_IS_GREATER_THAN_B +if A < B, return A_IS_LESS_THAN_B (success) +*/ + while (*MSB_K == *MSB_Q) { + MSB_K++; + MSB_Q++; + + buffer_lengths_in_bytes--; + if (0 == buffer_lengths_in_bytes) { + DPRINTK("%s() Buffers have equal value!!\n", + __FUNCTION__); + return FAIL_A_IS_EQUAL_TO_B; + } + + } + + if (*MSB_K < *MSB_Q) { + return SUCCESS_A_IS_LESS_THAN_B; + } else { + return FAIL_A_IS_GREATER_THAN_B; + } + +} + +/* Name : icp_ocfDrvDsaSign + * + * Description : This function will map DSA RS Sign from OCF to the LAC API. + * + * NOTE: From looking at OCF patch to OpenSSL and even the number of input + * parameters, OCF expects us to generate the random seed value. This value + * is generated and passed to LAC, however the number is discared in the + * callback and not returned to the user. + */ +static int icp_ocfDrvDsaSign(struct cryptkop *krp) +{ + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; + void *callbackTag = NULL; + CpaCyRandGenOpData randGenOpData; + int primeQSizeInBytes = 0; + int doCheck = 0; + CpaFlatBuffer randData; + CpaBoolean protocolStatus = CPA_FALSE; + CpaFlatBuffer *pR = NULL; + CpaFlatBuffer *pS = NULL; + + callbackTag = krp; + + BITS_TO_BYTES(primeQSizeInBytes, + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. + crp_nbits); + + if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { + APRINTK("%s(): DSA PRIME Q size not equal to the " + "FIPS defined 20bytes, = %d\n", + __FUNCTION__, primeQSizeInBytes); + krp->krp_status = EDOM; + return EDOM; + } + + dsaRsSignOpData = + icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); + if (NULL == dsaRsSignOpData) { + APRINTK("%s():Failed to get memory" + " for DSA RS Sign Op data struct\n", __FUNCTION__); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + dsaRsSignOpData->K.pData = + icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); + + if (NULL == dsaRsSignOpData->K.pData) { + APRINTK("%s():Failed to get memory" + " for DSA RS Sign Op Random value\n", __FUNCTION__); + ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); + if (NULL == pR) { + APRINTK("%s():Failed to get memory" + " for DSA signature R\n", __FUNCTION__); + ICP_CACHE_FREE(drvDSARSSignKValue_zone, + dsaRsSignOpData->K.pData); + ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); + if (NULL == pS) { + APRINTK("%s():Failed to get memory" + " for DSA signature S\n", __FUNCTION__); + icp_ocfDrvFreeFlatBuffer(pR); + ICP_CACHE_FREE(drvDSARSSignKValue_zone, + dsaRsSignOpData->K.pData); + ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + /*link prime number parameter for ease of processing */ + dsaRsSignOpData->P.pData = + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; + BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, + dsaRsSignOpData->P.dataLenInBytes); + + dsaRsSignOpData->Q.pData = + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; + BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. + crp_nbits); + + icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, + dsaRsSignOpData->Q.dataLenInBytes); + + /*generate random number with equal buffer size to Prime value Q, + but value less than Q */ + dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; + + randGenOpData.generateBits = CPA_TRUE; + randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; + + icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, + dsaRsSignOpData->K.dataLenInBytes, + &randData); + + doCheck = 0; + while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), + &(dsaRsSignOpData->Q), &doCheck)) { + + if (CPA_STATUS_SUCCESS + != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, + NULL, NULL, &randGenOpData, &randData)) { + APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" + "value\n", __FUNCTION__); + icp_ocfDrvFreeFlatBuffer(pS); + icp_ocfDrvFreeFlatBuffer(pR); + ICP_CACHE_FREE(drvDSARSSignKValue_zone, + dsaRsSignOpData->K.pData); + ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); + krp->krp_status = EAGAIN; + return EAGAIN; + } + + doCheck++; + if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { + APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " + "value less than Q value\n", __FUNCTION__); + icp_ocfDrvFreeFlatBuffer(pS); + icp_ocfDrvFreeFlatBuffer(pR); + ICP_CACHE_FREE(drvDSARSSignKValue_zone, + dsaRsSignOpData->K.pData); + ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); + krp->krp_status = EAGAIN; + return EAGAIN; + } + + } + /*Rand Data - no need to swap bytes for pK */ + + /* Link parameters */ + dsaRsSignOpData->G.pData = + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; + BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); + + icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, + dsaRsSignOpData->G.dataLenInBytes); + + dsaRsSignOpData->X.pData = + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; + BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); + icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, + dsaRsSignOpData->X.dataLenInBytes); + + /*OpenSSL dgst parameter is left in big endian byte order, + therefore no byte swap is required */ + dsaRsSignOpData->M.pData = + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; + BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. + crp_nbits); + + /* Output Parameters */ + pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; + BITS_TO_BYTES(pS->dataLenInBytes, + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. + crp_nbits); + + pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; + BITS_TO_BYTES(pR->dataLenInBytes, + krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. + crp_nbits); + + lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, + icp_ocfDrvDsaRSSignCallBack, + callbackTag, dsaRsSignOpData, + &protocolStatus, pR, pS); + + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", + __FUNCTION__, lacStatus); + krp->krp_status = ECANCELED; + icp_ocfDrvFreeFlatBuffer(pS); + icp_ocfDrvFreeFlatBuffer(pR); + ICP_CACHE_FREE(drvDSARSSignKValue_zone, + dsaRsSignOpData->K.pData); + ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); + } + + return lacStatus; +} + +/* Name : icp_ocfDrvDsaVerify + * + * Description : This function will map DSA RS Verify from OCF to the LAC API. + * + */ +static int icp_ocfDrvDsaVerify(struct cryptkop *krp) +{ + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; + void *callbackTag = NULL; + CpaBoolean verifyStatus = CPA_FALSE; + + callbackTag = krp; + + dsaVerifyOpData = + icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); + if (NULL == dsaVerifyOpData) { + APRINTK("%s():Failed to get memory" + " for DSA Verify Op data struct\n", __FUNCTION__); + krp->krp_status = ENOMEM; + return ENOMEM; + } + + /* Link parameters */ + dsaVerifyOpData->P.pData = + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; + BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. + crp_nbits); + icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, + dsaVerifyOpData->P.dataLenInBytes); + + dsaVerifyOpData->Q.pData = + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; + BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. + crp_nbits); + icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, + dsaVerifyOpData->Q.dataLenInBytes); + + dsaVerifyOpData->G.pData = + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; + BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. + crp_nbits); + icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, + dsaVerifyOpData->G.dataLenInBytes); + + dsaVerifyOpData->Y.pData = + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; + BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. + crp_nbits); + icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, + dsaVerifyOpData->Y.dataLenInBytes); + + /*OpenSSL dgst parameter is left in big endian byte order, + therefore no byte swap is required */ + dsaVerifyOpData->M.pData = + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; + BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. + crp_nbits); + + dsaVerifyOpData->R.pData = + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; + BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. + crp_nbits); + icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, + dsaVerifyOpData->R.dataLenInBytes); + + dsaVerifyOpData->S.pData = + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; + BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, + krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. + crp_nbits); + icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, + dsaVerifyOpData->S.dataLenInBytes); + + lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, + icp_ocfDrvDsaVerifyCallBack, + callbackTag, dsaVerifyOpData, &verifyStatus); + + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): DSA Verify Operation failed (%d).\n", + __FUNCTION__, lacStatus); + ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); + krp->krp_status = ECANCELED; + } + + return lacStatus; +} + +/* Name : icp_ocfDrvDhP1Callback + * + * Description : When this function returns it signifies that the LAC + * component has completed the DH operation. + */ +static void +icp_ocfDrvDhP1CallBack(void *callbackTag, + CpaStatus status, + void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) +{ + struct cryptkop *krp = NULL; + CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; + + if (NULL == callbackTag) { + DPRINTK("%s(): Invalid input parameters - " + "callbackTag data is NULL\n", __FUNCTION__); + return; + } + krp = (struct cryptkop *)callbackTag; + + if (NULL == pOpData) { + DPRINTK("%s(): Invalid input parameters - " + "Operation Data is NULL\n", __FUNCTION__); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; + + if (NULL == pLocalOctetStringPV) { + DPRINTK("%s(): Invalid input parameters - " + "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); + memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); + ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + + if (CPA_STATUS_SUCCESS == status) { + krp->krp_status = CRYPTO_OP_SUCCESS; + } else { + APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " + "Operation Status = %d\n", __FUNCTION__, status); + krp->krp_status = ECANCELED; + } + + icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, + pLocalOctetStringPV->dataLenInBytes); + + icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); + memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); + ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); + + crypto_kdone(krp); + + return; +} + +/* Name : icp_ocfDrvModExpCallBack + * + * Description : When this function returns it signifies that the LAC + * component has completed the Mod Exp operation. + */ +static void +icp_ocfDrvModExpCallBack(void *callbackTag, + CpaStatus status, + void *pOpdata, CpaFlatBuffer * pResult) +{ + struct cryptkop *krp = NULL; + CpaCyLnModExpOpData *pLnModExpOpData = NULL; + + if (NULL == callbackTag) { + DPRINTK("%s(): Invalid input parameters - " + "callbackTag data is NULL\n", __FUNCTION__); + return; + } + krp = (struct cryptkop *)callbackTag; + + if (NULL == pOpdata) { + DPRINTK("%s(): Invalid Mod Exp input parameters - " + "Operation Data is NULL\n", __FUNCTION__); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; + + if (NULL == pResult) { + DPRINTK("%s(): Invalid input parameters - " + "pResult data is NULL\n", __FUNCTION__); + krp->krp_status = ECANCELED; + memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); + ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); + crypto_kdone(krp); + return; + } + + if (CPA_STATUS_SUCCESS == status) { + krp->krp_status = CRYPTO_OP_SUCCESS; + } else { + APRINTK("%s(): LAC Mod Exp Operation failed - " + "Operation Status = %d\n", __FUNCTION__, status); + krp->krp_status = ECANCELED; + } + + icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); + + /*switch base size value back to original */ + if (pLnModExpOpData->base.pData == + (uint8_t *) & (krp-> + krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. + crp_nbits)) { + *((uint32_t *) pLnModExpOpData->base.pData) = + ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); + } + icp_ocfDrvFreeFlatBuffer(pResult); + memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); + ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); + + crypto_kdone(krp); + + return; + +} + +/* Name : icp_ocfDrvModExpCRTCallBack + * + * Description : When this function returns it signifies that the LAC + * component has completed the Mod Exp CRT operation. + */ +static void +icp_ocfDrvModExpCRTCallBack(void *callbackTag, + CpaStatus status, + void *pOpData, CpaFlatBuffer * pOutputData) +{ + struct cryptkop *krp = NULL; + CpaCyRsaDecryptOpData *pDecryptData = NULL; + + if (NULL == callbackTag) { + DPRINTK("%s(): Invalid input parameters - " + "callbackTag data is NULL\n", __FUNCTION__); + return; + } + + krp = (struct cryptkop *)callbackTag; + + if (NULL == pOpData) { + DPRINTK("%s(): Invalid input parameters - " + "Operation Data is NULL\n", __FUNCTION__); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; + + if (NULL == pOutputData) { + DPRINTK("%s(): Invalid input parameter - " + "pOutputData is NULL\n", __FUNCTION__); + memset(pDecryptData->pRecipientPrivateKey, 0, + sizeof(CpaCyRsaPrivateKey)); + ICP_CACHE_FREE(drvRSAPrivateKey_zone, + pDecryptData->pRecipientPrivateKey); + memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); + ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + + if (CPA_STATUS_SUCCESS == status) { + krp->krp_status = CRYPTO_OP_SUCCESS; + } else { + APRINTK("%s(): LAC Mod Exp CRT operation failed - " + "Operation Status = %d\n", __FUNCTION__, status); + krp->krp_status = ECANCELED; + } + + icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); + + icp_ocfDrvFreeFlatBuffer(pOutputData); + memset(pDecryptData->pRecipientPrivateKey, 0, + sizeof(CpaCyRsaPrivateKey)); + ICP_CACHE_FREE(drvRSAPrivateKey_zone, + pDecryptData->pRecipientPrivateKey); + memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); + ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); + + crypto_kdone(krp); + + return; +} + +/* Name : icp_ocfDrvDsaRSSignCallBack + * + * Description : When this function returns it signifies that the LAC + * component has completed the DSA RS sign operation. + */ +static void +icp_ocfDrvDsaRSSignCallBack(void *callbackTag, + CpaStatus status, + void *pOpData, + CpaBoolean protocolStatus, + CpaFlatBuffer * pR, CpaFlatBuffer * pS) +{ + struct cryptkop *krp = NULL; + CpaCyDsaRSSignOpData *pSignData = NULL; + + if (NULL == callbackTag) { + DPRINTK("%s(): Invalid input parameters - " + "callbackTag data is NULL\n", __FUNCTION__); + return; + } + + krp = (struct cryptkop *)callbackTag; + + if (NULL == pOpData) { + DPRINTK("%s(): Invalid input parameters - " + "Operation Data is NULL\n", __FUNCTION__); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + pSignData = (CpaCyDsaRSSignOpData *) pOpData; + + if (NULL == pR) { + DPRINTK("%s(): Invalid input parameter - " + "pR sign is NULL\n", __FUNCTION__); + icp_ocfDrvFreeFlatBuffer(pS); + ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + + if (NULL == pS) { + DPRINTK("%s(): Invalid input parameter - " + "pS sign is NULL\n", __FUNCTION__); + icp_ocfDrvFreeFlatBuffer(pR); + ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + + if (CPA_STATUS_SUCCESS != status) { + APRINTK("%s(): LAC DSA RS Sign operation failed - " + "Operation Status = %d\n", __FUNCTION__, status); + krp->krp_status = ECANCELED; + } else { + krp->krp_status = CRYPTO_OP_SUCCESS; + + if (CPA_TRUE != protocolStatus) { + DPRINTK("%s(): LAC DSA RS Sign operation failed due " + "to protocol error\n", __FUNCTION__); + krp->krp_status = EIO; + } + } + + /* Swap bytes only when the callback status is successful and + protocolStatus is set to true */ + if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { + icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); + icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); + } + + icp_ocfDrvFreeFlatBuffer(pR); + icp_ocfDrvFreeFlatBuffer(pS); + memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); + ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); + memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); + ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); + crypto_kdone(krp); + + return; +} + +/* Name : icp_ocfDrvDsaVerifyCallback + * + * Description : When this function returns it signifies that the LAC + * component has completed the DSA Verify operation. + */ +static void +icp_ocfDrvDsaVerifyCallBack(void *callbackTag, + CpaStatus status, + void *pOpData, CpaBoolean verifyStatus) +{ + + struct cryptkop *krp = NULL; + CpaCyDsaVerifyOpData *pVerData = NULL; + + if (NULL == callbackTag) { + DPRINTK("%s(): Invalid input parameters - " + "callbackTag data is NULL\n", __FUNCTION__); + return; + } + + krp = (struct cryptkop *)callbackTag; + + if (NULL == pOpData) { + DPRINTK("%s(): Invalid input parameters - " + "Operation Data is NULL\n", __FUNCTION__); + krp->krp_status = ECANCELED; + crypto_kdone(krp); + return; + } + pVerData = (CpaCyDsaVerifyOpData *) pOpData; + + if (CPA_STATUS_SUCCESS != status) { + APRINTK("%s(): LAC DSA Verify operation failed - " + "Operation Status = %d\n", __FUNCTION__, status); + krp->krp_status = ECANCELED; + } else { + krp->krp_status = CRYPTO_OP_SUCCESS; + + if (CPA_TRUE != verifyStatus) { + DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); + krp->krp_status = EIO; + } + } + + /* Swap bytes only when the callback status is successful and + verifyStatus is set to true */ + /*Just swapping back the key values for now. Possibly all + swapped buffers need to be reverted */ + if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { + icp_ocfDrvSwapBytes(pVerData->R.pData, + pVerData->R.dataLenInBytes); + icp_ocfDrvSwapBytes(pVerData->S.pData, + pVerData->S.dataLenInBytes); + } + + memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); + ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); + crypto_kdone(krp); + + return; +} diff --git a/target/linux/generic/files/crypto/ocf/ep80579/icp_common.c b/target/linux/generic/files/crypto/ocf/ep80579/icp_common.c new file mode 100644 index 0000000..5d46c0a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ep80579/icp_common.c @@ -0,0 +1,773 @@ +/************************************************************************* + * + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * version: Security.L.1.0.2-229 + * + ***************************************************************************/ + +/* + * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the + * crypto. + * + * This driver requires the ICP Access Library that is available from Intel in + * order to operate. + */ + +#include "icp_ocf.h" + +#define ICP_OCF_COMP_NAME "ICP_OCF" +#define ICP_OCF_VER_MAIN (2) +#define ICP_OCF_VER_MJR (1) +#define ICP_OCF_VER_MNR (0) + +#define MAX_DEREG_RETRIES (100) +#define DEFAULT_DEREG_RETRIES (10) +#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) + +/* This defines the maximum number of sessions possible between OCF + and the OCF EP80579 Driver. If set to zero, there is no limit. */ +#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) +#define NUM_SUPPORTED_CAPABILITIES (21) + +/*Slab zone names*/ +#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" +#define ICP_OP_DATA_NAME "icp_ocf.OpDat" +#define ICP_DH_NAME "icp_ocf.DH" +#define ICP_MODEXP_NAME "icp_ocf.ModExp" +#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" +#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" +#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" +#define ICP_DSA_VER_NAME "icp_ocf.DSAver" +#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" +#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" + +/*Slabs zones*/ +icp_kmem_cache drvSessionData_zone = NULL; +icp_kmem_cache drvOpData_zone = NULL; +icp_kmem_cache drvDH_zone = NULL; +icp_kmem_cache drvLnModExp_zone = NULL; +icp_kmem_cache drvRSADecrypt_zone = NULL; +icp_kmem_cache drvRSAPrivateKey_zone = NULL; +icp_kmem_cache drvDSARSSign_zone = NULL; +icp_kmem_cache drvDSARSSignKValue_zone = NULL; +icp_kmem_cache drvDSAVerify_zone = NULL; + +/*Slab zones for flatbuffers and bufferlist*/ +icp_kmem_cache drvFlatBuffer_zone = NULL; + +static inline int icp_cache_null_check(void) +{ + return (drvSessionData_zone && drvOpData_zone + && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone + && drvRSAPrivateKey_zone && drvDSARSSign_zone + && drvDSARSSign_zone && drvDSARSSignKValue_zone + && drvDSAVerify_zone && drvFlatBuffer_zone); +} + +/*Function to free all allocated slab caches before exiting the module*/ +static void icp_ocfDrvFreeCaches(void); + +int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; + +/* Module parameter - gives the number of times LAC deregistration shall be + re-tried */ +int num_dereg_retries = DEFAULT_DEREG_RETRIES; + +/* Module parameter - gives the delay time in jiffies before a LAC session + shall be attempted to be deregistered again */ +int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; + +/* Module parameter - gives the maximum number of sessions possible between + OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ +int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; + +/* This is set when the module is removed from the system, no further + processing can take place if this is set */ +icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); + +/* This is used to show how many lac sessions were not deregistered*/ +icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); + +/* This is used to track the number of registered sessions between OCF and + * and the OCF EP80579 driver, when max_session is set to value other than + * zero. This ensures that the max_session set for the OCF and the driver + * is equal to the LAC registered sessions */ +icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); + +/* Head of linked list used to store session data */ +icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; +icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; + +icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; + +/*Below pointer is only used in linux, FreeBSD uses the name to +create its own variable name*/ +icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; +ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); + +struct icp_drvBuffListInfo defBuffListInfo; + +/* Name : icp_ocfDrvInit + * + * Description : This function will register all the symmetric and asymmetric + * functionality that will be accelerated by the hardware. It will also + * get a unique driver ID from the OCF and initialise all slab caches + */ +ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) +{ + int ocfStatus = 0; + + IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, + ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); + + if (MAX_DEREG_RETRIES < num_dereg_retries) { + EPRINTK("Session deregistration retry count set to greater " + "than %d", MAX_DEREG_RETRIES); + icp_module_return_code(EINVAL); + } + + /* Initialize and Start the Cryptographic component */ + if (CPA_STATUS_SUCCESS != + cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { + EPRINTK("Failed to initialize and start the instance " + "of the Cryptographic component.\n"); + return icp_module_return_code(EINVAL); + } + + icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); + + /* Set the default size of BufferList to allocate */ + memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); + if (ICP_OCF_DRV_STATUS_SUCCESS != + icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, + &defBuffListInfo)) { + EPRINTK("Failed to get bufferlist memory info.\n"); + return icp_module_return_code(ENOMEM); + } + + /*Register OCF EP80579 Driver with OCF */ + icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); + + if (icp_ocfDrvDriverId < 0) { + EPRINTK("%s : ICP driver failed to register with OCF!\n", + __FUNCTION__); + return icp_module_return_code(ENODEV); + } + + /*Create all the slab caches used by the OCF EP80579 Driver */ + drvSessionData_zone = + ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); + + /* + * Allocation of the OpData includes the allocation space for meta data. + * The memory after the opData structure is reserved for this meta data. + */ + drvOpData_zone = + icp_kmem_cache_create(ICP_OP_DATA_NAME, + sizeof(struct icp_drvOpData) + + defBuffListInfo.metaSize, + ICP_KERNEL_CACHE_ALIGN, + ICP_KERNEL_CACHE_NOINIT); + + drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); + + drvLnModExp_zone = + ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); + + drvRSADecrypt_zone = + ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); + + drvRSAPrivateKey_zone = + ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); + + drvDSARSSign_zone = + ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); + + /*too awkward to use a macro here */ + drvDSARSSignKValue_zone = + ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, + DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); + + drvDSAVerify_zone = + ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); + + drvFlatBuffer_zone = + ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); + + if (0 == icp_cache_null_check()) { + icp_ocfDrvFreeCaches(); + EPRINTK("%s() line %d: Not enough memory!\n", + __FUNCTION__, __LINE__); + return ENOMEM; + } + + /* Register the ICP symmetric crypto support. */ + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, + ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, + ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); + ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, + ocfStatus); + + /* Register the ICP asymmetric algorithm support */ + ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, + ocfStatus); + ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); + ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); + ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); + ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); + + /* Register the ICP random number generator support */ + ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, + icp_ocfDrvReadRandom, NULL, ocfStatus); + + if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { + DPRINTK("%s: Failed to register any device capabilities\n", + __FUNCTION__); + icp_ocfDrvFreeCaches(); + icp_ocfDrvDriverId = INVALID_DRIVER_ID; + return icp_module_return_code(ECANCELED); + } + + DPRINTK("%s: Registered %d of %d device capabilities\n", + __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); + + /*Session data linked list used during module exit */ + ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); + ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); + + ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); + if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { + EPRINTK("%s: Failed to create single " + "thread workqueue\n", __FUNCTION__); + icp_ocfDrvFreeCaches(); + icp_ocfDrvDriverId = INVALID_DRIVER_ID; + return icp_module_return_code(ENOMEM); + } + + return icp_module_return_code(0); +} + +/* Name : icp_ocfDrvExit + * + * Description : This function will deregister all the symmetric sessions + * registered with the LAC component. It will also deregister all symmetric + * and asymmetric functionality that can be accelerated by the hardware via OCF + * and random number generation if it is enabled. + */ +ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) +{ + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + struct icp_drvSessionData *sessionData = NULL; + struct icp_drvSessionData *tempSessionData = NULL; + int i, remaining_delay_time_in_jiffies = 0; + + /* For FreeBSD the invariant macro below makes function to return */ + /* with EBUSY value in the case of any session which has been regi- */ + /* stered with LAC not being deregistered. */ + /* The Linux implementation is empty since it is purely to compensate */ + /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ + + ICP_MODULE_EXIT_INV(); + + /* There is a possibility of a process or new session command being */ + /* sent before this variable is incremented. The aim of this variable */ + /* is to stop a loop of calls creating a deadlock situation which */ + /* would prevent the driver from exiting. */ + icp_atomic_set(&icp_ocfDrvIsExiting, 1); + + /*Existing sessions will be routed to another driver after these calls */ + crypto_unregister_all(icp_ocfDrvDriverId); + crypto_runregister_all(icp_ocfDrvDriverId); + + if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { + DPRINTK("%s: workqueue already " + "destroyed, therefore module exit " + " function already called. Exiting.\n", __FUNCTION__); + return ICP_MODULE_EXIT_FUNC_RETURN_VAL; + } + /*If any sessions are waiting to be deregistered, do that. This also + flushes the work queue */ + ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); + + /*ENTER CRITICAL SECTION */ + icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); + + ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, + &icp_ocfDrvGlobalSymListHead, listNode) { + for (i = 0; i < num_dereg_retries; i++) { + /*No harm if bad input - LAC will handle error cases */ + if (ICP_SESSION_RUNNING == tempSessionData->inUse) { + lacStatus = + cpaCySymRemoveSession + (CPA_INSTANCE_HANDLE_SINGLE, + tempSessionData->sessHandle); + if (CPA_STATUS_SUCCESS == lacStatus) { + /* Succesfully deregistered */ + break; + } else if (CPA_STATUS_RETRY != lacStatus) { + icp_atomic_inc + (&lac_session_failed_dereg_count); + break; + } + + /*schedule_timout returns the time left for completion if + * this task is set to TASK_INTERRUPTIBLE */ + remaining_delay_time_in_jiffies = + dereg_retry_delay_in_jiffies; + while (0 > remaining_delay_time_in_jiffies) { + remaining_delay_time_in_jiffies = + icp_schedule_timeout + (&icp_ocfDrvSymSessInfoListSpinlock, + remaining_delay_time_in_jiffies); + } + + DPRINTK + ("%s(): Retry %d to deregistrate the session\n", + __FUNCTION__, i); + } + } + + /*remove from current list */ + ICP_LIST_DEL(tempSessionData, listNode); + /*add to free mem linked list */ + ICP_LIST_ADD(tempSessionData, + &icp_ocfDrvGlobalSymListHead_FreeMemList, + listNode); + + } + + /*EXIT CRITICAL SECTION */ + icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); + + /*set back to initial values */ + sessionData = NULL; + /*still have a reference in our list! */ + tempSessionData = NULL; + /*free memory */ + + ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, + &icp_ocfDrvGlobalSymListHead_FreeMemList, + listNode) { + + ICP_LIST_DEL(tempSessionData, listNode); + /* Free allocated CpaCySymSessionCtx */ + if (NULL != tempSessionData->sessHandle) { + icp_kfree(tempSessionData->sessHandle); + } + memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); + ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); + } + + if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { + DPRINTK("%s(): %d LAC sessions were not deregistered " + "correctly. This is not a clean exit! \n", + __FUNCTION__, + icp_atomic_read(&lac_session_failed_dereg_count)); + } + + icp_ocfDrvFreeCaches(); + icp_ocfDrvDriverId = INVALID_DRIVER_ID; + + icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); + + /* Shutdown the Cryptographic component */ + lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); + if (CPA_STATUS_SUCCESS != lacStatus) { + DPRINTK("%s(): Failed to stop instance of the " + "Cryptographic component.(status == %d)\n", + __FUNCTION__, lacStatus); + } + + return ICP_MODULE_EXIT_FUNC_RETURN_VAL; +} + +/* Name : icp_ocfDrvFreeCaches + * + * Description : This function deregisters all slab caches + */ +static void icp_ocfDrvFreeCaches(void) +{ + icp_atomic_set(&icp_ocfDrvIsExiting, 1); + + /*Sym Zones */ + ICP_CACHE_DESTROY(drvSessionData_zone); + ICP_CACHE_DESTROY(drvOpData_zone); + + /*Asym zones */ + ICP_CACHE_DESTROY(drvDH_zone); + ICP_CACHE_DESTROY(drvLnModExp_zone); + ICP_CACHE_DESTROY(drvRSADecrypt_zone); + ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); + ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); + ICP_CACHE_DESTROY(drvDSARSSign_zone); + ICP_CACHE_DESTROY(drvDSAVerify_zone); + + /*FlatBuffer and BufferList Zones */ + ICP_CACHE_DESTROY(drvFlatBuffer_zone); + +} + +/* Name : icp_ocfDrvDeregRetry + * + * Description : This function will try to farm the session deregistration + * off to a work queue. If it fails, nothing more can be done and it + * returns an error + */ +int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) +{ + struct icp_ocfDrvFreeLacSession *workstore = NULL; + + DPRINTK("%s(): Retry - Deregistering session (%p)\n", + __FUNCTION__, sessionToDeregister); + + /*make sure the session is not available to be allocated during this + process */ + icp_atomic_inc(&lac_session_failed_dereg_count); + + /*Farm off to work queue */ + workstore = + icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); + if (NULL == workstore) { + DPRINTK("%s(): unable to free session - no memory available " + "for work queue\n", __FUNCTION__); + return ENOMEM; + } + + workstore->sessionToDeregister = sessionToDeregister; + + icp_init_work(&(workstore->work), + icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); + + ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, + &(workstore->work)); + + return ICP_OCF_DRV_STATUS_SUCCESS; + +} + +/* Name : icp_ocfDrvDeferedFreeLacSessionProcess + * + * Description : This function will retry (module input parameter) + * 'num_dereg_retries' times to deregister any symmetric session that recieves a + * CPA_STATUS_RETRY message from the LAC component. This function is run in + * Thread context because it is called from a worker thread + */ +void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) +{ + struct icp_ocfDrvFreeLacSession *workstore = NULL; + CpaCySymSessionCtx sessionToDeregister = NULL; + int i = 0; + int remaining_delay_time_in_jiffies = 0; + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + + workstore = (struct icp_ocfDrvFreeLacSession *)arg; + if (NULL == workstore) { + DPRINTK("%s() function called with null parameter \n", + __FUNCTION__); + return; + } + + sessionToDeregister = workstore->sessionToDeregister; + icp_kfree(workstore); + + /*if exiting, give deregistration one more blast only */ + if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { + lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, + sessionToDeregister); + + if (lacStatus != CPA_STATUS_SUCCESS) { + DPRINTK("%s() Failed to Dereg LAC session %p " + "during module exit\n", __FUNCTION__, + sessionToDeregister); + return; + } + + icp_atomic_dec(&lac_session_failed_dereg_count); + return; + } + + for (i = 0; i <= num_dereg_retries; i++) { + lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, + sessionToDeregister); + + if (lacStatus == CPA_STATUS_SUCCESS) { + icp_atomic_dec(&lac_session_failed_dereg_count); + return; + } + if (lacStatus != CPA_STATUS_RETRY) { + DPRINTK("%s() Failed to deregister session - lacStatus " + " = %d", __FUNCTION__, lacStatus); + break; + } + + /*schedule_timout returns the time left for completion if this + task is set to TASK_INTERRUPTIBLE */ + remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; + while (0 < remaining_delay_time_in_jiffies) { + remaining_delay_time_in_jiffies = + icp_schedule_timeout(NULL, + remaining_delay_time_in_jiffies); + } + + } + + DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); + DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, + icp_atomic_read(&lac_session_failed_dereg_count)); +} + +/* Name : icp_ocfDrvPtrAndLenToFlatBuffer + * + * Description : This function converts a "pointer and length" buffer + * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. + * + * This function assumes that the data passed in are valid. + */ +inline void +icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, + CpaFlatBuffer * pFlatBuffer) +{ + pFlatBuffer->pData = pData; + pFlatBuffer->dataLenInBytes = len; +} + +/* Name : icp_ocfDrvPtrAndLenToBufferList + * + * Description : This function converts a "pointer and length" buffer + * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. + * + * This function assumes that the data passed in are valid. + */ +inline void +icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, + CpaBufferList * pBufferList) +{ + pBufferList->numBuffers = 1; + pBufferList->pBuffers->pData = pDataIn; + pBufferList->pBuffers->dataLenInBytes = length; +} + +/* Name : icp_ocfDrvBufferListToPtrAndLen + * + * Description : This function converts Fredericksburg Scatter/Gather Buffer + * (CpaBufferList) format to a "pointer and length" buffer structure. + * + * This function assumes that the data passed in are valid. + */ +inline void +icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, + void **ppDataOut, uint32_t * pLength) +{ + *ppDataOut = pBufferList->pBuffers->pData; + *pLength = pBufferList->pBuffers->dataLenInBytes; +} + +/* Name : icp_ocfDrvBufferListMemInfo + * + * Description : This function will set the number of flat buffers in + * bufferlist, the size of memory to allocate for the pPrivateMetaData + * member of the CpaBufferList. + */ +int +icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, + struct icp_drvBuffListInfo *buffListInfo) +{ + buffListInfo->numBuffers = numBuffers; + + if (CPA_STATUS_SUCCESS != + cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, + buffListInfo->numBuffers, + &(buffListInfo->metaSize))) { + EPRINTK("%s() Failed to get buffer list meta size.\n", + __FUNCTION__); + return ICP_OCF_DRV_STATUS_FAIL; + } + + return ICP_OCF_DRV_STATUS_SUCCESS; +} + +/* Name : icp_ocfDrvFreeFlatBuffer + * + * Description : This function will deallocate flat buffer. + */ +inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) +{ + if (pFlatBuffer != NULL) { + memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); + ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); + } +} + +/* Name : icp_ocfDrvAllocMetaData + * + * Description : This function will allocate memory for the + * pPrivateMetaData member of CpaBufferList. + */ +inline int +icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, + struct icp_drvOpData *pOpData) +{ + Cpa32U metaSize = 0; + + if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { + uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; + + if (0 == defBuffListInfo.metaSize) { + pBufferList->pPrivateMetaData = NULL; + return ICP_OCF_DRV_STATUS_SUCCESS; + } + /* + * The meta data allocation has been included as part of the + * op data. It has been pre-allocated in memory just after the + * icp_drvOpData structure. + */ + pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + + sizeof(struct + icp_drvOpData)); + } else { + if (CPA_STATUS_SUCCESS != + cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, + pBufferList->numBuffers, + &metaSize)) { + EPRINTK("%s() Failed to get buffer list meta size.\n", + __FUNCTION__); + return ICP_OCF_DRV_STATUS_FAIL; + } + + if (0 == metaSize) { + pBufferList->pPrivateMetaData = NULL; + return ICP_OCF_DRV_STATUS_SUCCESS; + } + + pBufferList->pPrivateMetaData = + icp_kmalloc(metaSize, ICP_M_NOWAIT); + } + if (NULL == pBufferList->pPrivateMetaData) { + EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", + __FUNCTION__); + return ICP_OCF_DRV_STATUS_FAIL; + } + + return ICP_OCF_DRV_STATUS_SUCCESS; +} + +/* Name : icp_ocfDrvFreeMetaData + * + * Description : This function will deallocate pPrivateMetaData memory. + */ +inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) +{ + if (NULL == pBufferList->pPrivateMetaData) { + return; + } + + /* + * Only free the meta data if the BufferList has more than + * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. + * Otherwise, the meta data shall be freed when the icp_drvOpData is + * freed. + */ + if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { + icp_kfree(pBufferList->pPrivateMetaData); + } +} + +/* Module declaration, init and exit functions */ +ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); +ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); +ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); +ICP_MODULE_LICENSE("Dual BSD/GPL"); +ICP_MODULE_AUTHOR("Intel"); + +/* Module parameters */ +ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, + "Number of times to retry LAC Sym Session Deregistration. " + "Default 10, Max 100"); +ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " + "(added to a schedule() function call) before a LAC Sym " + "Session Dereg is retried. Default 10"); +ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, + "This sets the maximum number of sessions " + "between OCF and this driver. If this value is set to zero," + "max session count checking is disabled. Default is zero(0)"); + +/* Module dependencies */ +#define MODULE_MIN_VER 1 +#define CRYPTO_MAX_VER 3 +#define LAC_MAX_VER 2 + +ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, + CRYPTO_MAX_VER); +ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, + CRYPTO_MAX_VER); +ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, + LAC_MAX_VER); diff --git a/target/linux/generic/files/crypto/ocf/ep80579/icp_ocf.h b/target/linux/generic/files/crypto/ocf/ep80579/icp_ocf.h new file mode 100644 index 0000000..d9dde87 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ep80579/icp_ocf.h @@ -0,0 +1,376 @@ +/*************************************************************************** + * + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * version: Security.L.1.0.2-229 + * + ***************************************************************************/ + +/* + * OCF driver header file for the Intel ICP processor. + */ + +#ifndef ICP_OCF_H_ +#define ICP_OCF_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "icp_os.h" + +#define NUM_BITS_IN_BYTE (8) +#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) +#define INVALID_DRIVER_ID (-1) +#define RETURN_RAND_NUM_GEN_FAILED (-1) + +/*This is the max block cipher initialisation vector*/ +#define MAX_IV_LEN_IN_BYTES (20) +/*This is used to check whether the OCF to this driver session limit has + been disabled*/ +#define NO_OCF_TO_DRV_MAX_SESSIONS (0) + +/*OCF values mapped here*/ +#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) +#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) +#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) +#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) +#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) +#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) + +#define OCF_REGISTRATION_STATUS_SUCCESS (0) +#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) +#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) +#define ICP_OCF_DRV_STATUS_SUCCESS (0) +#define ICP_OCF_DRV_STATUS_FAIL (1) + +/*Turn on/off debug options*/ +#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) +#define ICP_OCF_PRINT_KERN_ALERT (1) +#define ICP_OCF_PRINT_KERN_ERRS (1) + +#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 +#define DPRINTK(args...) \ +{ \ + ICP_IPRINTK(args); \ +} + +#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 + +#define DPRINTK(args...) + +#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 + +#if ICP_OCF_PRINT_KERN_ALERT == 1 +#define APRINTK(args...) \ +{ \ + ICP_APRINTK(args); \ +} + +#else //ICP_OCF_PRINT_KERN_ALERT == 1 + +#define APRINTK(args...) + +#endif //ICP_OCF_PRINT_KERN_ALERT == 1 + +#if ICP_OCF_PRINT_KERN_ERRS == 1 +#define EPRINTK(args...) \ +{ \ + ICP_EPRINTK(args); \ +} + +#else //ICP_OCF_PRINT_KERN_ERRS == 1 + +#define EPRINTK(args...) + +#endif //ICP_OCF_PRINT_KERN_ERRS == 1 + +#define IPRINTK(args...) \ +{ \ + ICP_IPRINTK(args); \ +} + +/*DSA Prime Q size in bytes (as defined in the standard) */ +#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) + +#define BITS_TO_BYTES(bytes, bits) \ + bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE + +typedef enum { + ICP_OCF_DRV_ALG_CIPHER = 0, + ICP_OCF_DRV_ALG_HASH +} icp_ocf_drv_alg_type_t; + +typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, + icp_drvSessionData) icp_drvSessionListHead_t; + +/*Values used to derisk chances of performs being called against +deregistered sessions (for which the slab page has been reclaimed) +This is not a fix - since page frames are reclaimed from a slab, one cannot +rely on that memory not being re-used by another app.*/ +typedef enum { + ICP_SESSION_INITIALISED = 0x5C5C5C, + ICP_SESSION_RUNNING = 0x005C00, + ICP_SESSION_DEREGISTERED = 0xC5C5C5 +} usage_derisk; + +/* This struct is required for deferred session + deregistration as a work queue function can + only have one argument*/ +struct icp_ocfDrvFreeLacSession { + CpaCySymSessionCtx sessionToDeregister; + icp_workstruct work; +}; + +/* +This is the OCF<->OCF_DRV session object: + +1.listNode + The first member is a listNode. These session objects are added to a linked + list in order to make it easier to remove them all at session exit time. + +2.inUse + The second member is used to give the session object state and derisk the + possibility of OCF batch calls executing against a deregistered session (as + described above). + +3.sessHandle + The third member is a LAC<->OCF_DRV session handle (initialised with the first + perform request for that session). + +4.lacSessCtx + The fourth is the LAC session context. All the parameters for this structure + are only known when the first perform request for this session occurs. That is + why the OCF EP80579 Driver only registers a new LAC session at perform time +*/ +struct icp_drvSessionData { + ICP_LIST_ENTRY(icp_drvSessionData) listNode; + usage_derisk inUse; + CpaCySymSessionCtx sessHandle; + CpaCySymSessionSetupData lacSessCtx; +}; + +/* These are all defined in icp_common.c */ +extern icp_atomic_t lac_session_failed_dereg_count; +extern icp_atomic_t icp_ocfDrvIsExiting; +extern icp_atomic_t num_ocf_to_drv_registered_sessions; + +extern int32_t icp_ocfDrvDriverId; + +extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; +extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; +extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; +extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; + +/*Slab zones for symettric functionality, instantiated in icp_common.c*/ +extern icp_kmem_cache drvSessionData_zone; +extern icp_kmem_cache drvOpData_zone; + +/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ +extern icp_kmem_cache drvDH_zone; +extern icp_kmem_cache drvLnModExp_zone; +extern icp_kmem_cache drvRSADecrypt_zone; +extern icp_kmem_cache drvRSAPrivateKey_zone; +extern icp_kmem_cache drvDSARSSign_zone; +extern icp_kmem_cache drvDSARSSignKValue_zone; +extern icp_kmem_cache drvDSAVerify_zone; + +/* Module parameters defined in icp_cpmmon.c*/ + +/* Module parameters - gives the number of times LAC deregistration shall be + re-tried */ +extern int num_dereg_retries; + +/* Module parameter - gives the delay time in jiffies before a LAC session + shall be attempted to be deregistered again */ +extern int dereg_retry_delay_in_jiffies; + +/* Module parameter - gives the maximum number of sessions possible between + OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ +extern int max_sessions; + +/*Slab zones for flatbuffers and bufferlist*/ +extern icp_kmem_cache drvFlatBuffer_zone; + +#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) + +struct icp_drvBuffListInfo { + Cpa16U numBuffers; + Cpa32U metaSize; + Cpa32U metaOffset; + Cpa32U buffListSize; +}; + +extern struct icp_drvBuffListInfo defBuffListInfo; + +/* This struct is used to keep a reference to the relevant node in the list + of sessionData structs, to the buffer type required by OCF and to the OCF + provided crp struct that needs to be returned. All this info is needed in + the callback function.*/ +struct icp_drvOpData { + CpaCySymOpData lacOpData; + uint32_t digestSizeInBytes; + struct cryptop *crp; + uint8_t bufferType; + uint8_t ivData[MAX_IV_LEN_IN_BYTES]; + uint16_t numBufferListArray; + CpaBufferList srcBuffer; + CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; + CpaBoolean verifyResult; +}; + +/* Create a new session between OCF and this driver*/ +int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, + struct cryptoini *cri); + +/* Free a session between this driver and the Quick Assist Framework*/ +int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); + +/* Defer freeing a Quick Assist session*/ +void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); + +/* Process OCF cryptographic request for a symmetric algorithm*/ +int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); + +/* Process OCF cryptographic request for an asymmetric algorithm*/ +int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); + +/* Populate a buffer with random data*/ +int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); + +/* Retry Quick Assist session deregistration*/ +int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); + +/* Convert an OS scatter gather list to a CPA buffer list*/ +int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, + CpaBufferList * bufferList); + +/* Convert a CPA buffer list to an OS scatter gather list*/ +int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, + icp_packet_buffer_t ** pPacketBuffer); + +/* Get the number of buffers in an OS scatter gather list*/ +uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); + +/* Convert a single OS buffer to a CPA Flat Buffer*/ +void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, + CpaFlatBuffer * pFlatBuffer); + +/* Add pointer and length to a CPA Flat Buffer structure*/ +void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, + CpaFlatBuffer * pFlatBuffer); + +/* Convert pointer and length values to a CPA buffer list*/ +void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, + CpaBufferList * pBufferList); + +/* Convert a CPA buffer list to pointer and length values*/ +void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, + void **ppDataOut, uint32_t * pLength); + +/* Set the number of flat buffers in bufferlist and the size of memory + to allocate for the pPrivateMetaData member of the CpaBufferList.*/ +int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, + struct icp_drvBuffListInfo *buffListInfo); + +/* Find pointer position of the digest within an OS scatter gather list*/ +uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData + *drvOpData, + int offsetInBytes, + uint32_t digestSizeInBytes); + +/*This top level function is used to find a pointer to where a digest is + stored/needs to be inserted. */ +uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, + struct cryptodesc *crp_desc); + +/* Free a CPA flat buffer*/ +void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); + +/* This function will allocate memory for the pPrivateMetaData + member of CpaBufferList. */ +int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, + struct icp_drvOpData *pOpData); + +/* Free data allocated for the pPrivateMetaData + member of CpaBufferList.*/ +void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); + +#define ICP_CACHE_CREATE(cache_ID, cache_name) \ + icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ + ICP_KERNEL_CACHE_NOINIT) + +#define ICP_CACHE_FREE(args...) \ + icp_kmem_cache_free (args) + +#define ICP_CACHE_DESTROY(slab_zone)\ +{\ + if(NULL != slab_zone){\ + icp_kmem_cache_destroy(slab_zone);\ + slab_zone = NULL;\ + }\ +} + +#endif +/* ICP_OCF_H_ */ diff --git a/target/linux/generic/files/crypto/ocf/ep80579/icp_sym.c b/target/linux/generic/files/crypto/ocf/ep80579/icp_sym.c new file mode 100644 index 0000000..e1c7148 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ep80579/icp_sym.c @@ -0,0 +1,1153 @@ +/*************************************************************************** + * + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * version: Security.L.1.0.2-229 + * + ***************************************************************************/ +/* + * An OCF module that uses the API for Intel® QuickAssist Technology to do the + * cryptography. + * + * This driver requires the ICP Access Library that is available from Intel in + * order to operate. + */ + +#include "icp_ocf.h" + +/*This is the call back function for all symmetric cryptographic processes. + Its main functionality is to free driver crypto operation structure and to + call back to OCF*/ +static void +icp_ocfDrvSymCallBack(void *callbackTag, + CpaStatus status, + const CpaCySymOp operationType, + void *pOpData, + CpaBufferList * pDstBuffer, CpaBoolean verifyResult); + +/*This function is used to extract crypto processing information from the OCF + inputs, so as that it may be passed onto LAC*/ +static int +icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, + struct cryptodesc *crp_desc); + +/*This function checks whether the crp_desc argument pertains to a digest or a + cipher operation*/ +static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); + +/*This function copies all the passed in session context information and stores + it in a LAC context structure*/ +static int +icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, + CpaCySymSessionSetupData * lacSessCtx); + +/*This function is used to free an OCF->OCF_DRV session object*/ +static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); + +/*max IOV buffs supported in a UIO structure*/ +#define NUM_IOV_SUPPORTED (1) + +/* Name : icp_ocfDrvSymCallBack + * + * Description : When this function returns it signifies that the LAC + * component has completed the relevant symmetric operation. + * + * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory + * object was passed to LAC for the cryptographic processing and contains all + * the relevant information for cleaning up buffer handles etc. so that the + * OCF EP80579 Driver portion of this crypto operation can be fully completed. + */ +static void +icp_ocfDrvSymCallBack(void *callbackTag, + CpaStatus status, + const CpaCySymOp operationType, + void *pOpData, + CpaBufferList * pDstBuffer, CpaBoolean verifyResult) +{ + struct cryptop *crp = NULL; + struct icp_drvOpData *temp_drvOpData = + (struct icp_drvOpData *)callbackTag; + uint64_t *tempBasePtr = NULL; + uint32_t tempLen = 0; + + if (NULL == temp_drvOpData) { + DPRINTK("%s(): The callback from the LAC component" + " has failed due to Null userOpaque data" + "(status == %d).\n", __FUNCTION__, status); + DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); + return; + } + + crp = temp_drvOpData->crp; + crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; + + if (NULL == pOpData) { + DPRINTK("%s(): The callback from the LAC component" + " has failed due to Null Symmetric Op data" + "(status == %d).\n", __FUNCTION__, status); + crp->crp_etype = ECANCELED; + crypto_done(crp); + return; + } + + if (NULL == pDstBuffer) { + DPRINTK("%s(): The callback from the LAC component" + " has failed due to Null Dst Bufferlist data" + "(status == %d).\n", __FUNCTION__, status); + crp->crp_etype = ECANCELED; + crypto_done(crp); + return; + } + + if (CPA_STATUS_SUCCESS == status) { + + if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { + if (ICP_OCF_DRV_STATUS_SUCCESS != + icp_ocfDrvBufferListToPacketBuff(pDstBuffer, + (icp_packet_buffer_t + **) + & (crp->crp_buf))) { + EPRINTK("%s(): BufferList to SkBuff " + "conversion error.\n", __FUNCTION__); + crp->crp_etype = EPERM; + } + } else { + icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, + (void **)&tempBasePtr, + &tempLen); + crp->crp_olen = (int)tempLen; + } + + } else { + DPRINTK("%s(): The callback from the LAC component has failed" + "(status == %d).\n", __FUNCTION__, status); + + crp->crp_etype = ECANCELED; + } + + if (temp_drvOpData->numBufferListArray > + ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { + icp_kfree(pDstBuffer->pBuffers); + } + icp_ocfDrvFreeMetaData(pDstBuffer); + ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); + + /* Invoke the OCF callback function */ + crypto_done(crp); + + return; +} + +/* Name : icp_ocfDrvNewSession + * + * Description : This function will create a new Driver<->OCF session + * + * Notes : LAC session registration happens during the first perform call. + * That is the first time we know all information about a given session. + */ +int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, + struct cryptoini *cri) +{ + struct icp_drvSessionData *sessionData = NULL; + uint32_t delete_session = 0; + + /* The SID passed in should be our driver ID. We can return the */ + /* local ID (LID) which is a unique identifier which we can use */ + /* to differentiate between the encrypt/decrypt LAC session handles */ + if (NULL == sid) { + EPRINTK("%s(): Invalid input parameters - NULL sid.\n", + __FUNCTION__); + return EINVAL; + } + + if (NULL == cri) { + EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", + __FUNCTION__); + return EINVAL; + } + + if (icp_ocfDrvDriverId != *sid) { + EPRINTK("%s(): Invalid input parameters - bad driver ID\n", + __FUNCTION__); + EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); + return EINVAL; + } + + sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); + if (NULL == sessionData) { + DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); + return ENOMEM; + } + + /*ENTER CRITICAL SECTION */ + icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); + /*put this check in the spinlock so no new sessions can be added to the + linked list when we are exiting */ + if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { + delete_session++; + + } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { + if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= + (max_sessions - + icp_atomic_read(&lac_session_failed_dereg_count))) { + delete_session++; + } else { + icp_atomic_inc(&num_ocf_to_drv_registered_sessions); + /* Add to session data linked list */ + ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, + listNode); + } + + } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { + ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, + listNode); + } + + sessionData->inUse = ICP_SESSION_INITIALISED; + + /*EXIT CRITICAL SECTION */ + icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); + + if (delete_session) { + DPRINTK("%s():No Session handles available\n", __FUNCTION__); + ICP_CACHE_FREE(drvSessionData_zone, sessionData); + return EPERM; + } + + if (ICP_OCF_DRV_STATUS_SUCCESS != + icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { + DPRINTK("%s():algorithm not supported\n", __FUNCTION__); + icp_ocfDrvFreeOCFSession(sessionData); + return EINVAL; + } + + if (cri->cri_next) { + if (cri->cri_next->cri_next != NULL) { + DPRINTK("%s():only two chained algorithms supported\n", + __FUNCTION__); + icp_ocfDrvFreeOCFSession(sessionData); + return EPERM; + } + + if (ICP_OCF_DRV_STATUS_SUCCESS != + icp_ocfDrvAlgorithmSetup(cri->cri_next, + &(sessionData->lacSessCtx))) { + DPRINTK("%s():second algorithm not supported\n", + __FUNCTION__); + icp_ocfDrvFreeOCFSession(sessionData); + return EINVAL; + } + + sessionData->lacSessCtx.symOperation = + CPA_CY_SYM_OP_ALGORITHM_CHAINING; + } + + *sid = (uint32_t) sessionData; + + return ICP_OCF_DRV_STATUS_SUCCESS; +} + +/* Name : icp_ocfDrvAlgorithmSetup + * + * Description : This function builds the session context data from the + * information supplied through OCF. Algorithm chain order and whether the + * session is Encrypt/Decrypt can only be found out at perform time however, so + * the session is registered with LAC at that time. + */ +static int +icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, + CpaCySymSessionSetupData * lacSessCtx) +{ + + lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; + + switch (cri->cri_alg) { + + case CRYPTO_NULL_CBC: + DPRINTK("%s(): NULL CBC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; + lacSessCtx->cipherSetupData.cipherAlgorithm = + CPA_CY_SYM_CIPHER_NULL; + lacSessCtx->cipherSetupData.cipherKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; + break; + + case CRYPTO_DES_CBC: + DPRINTK("%s(): DES CBC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; + lacSessCtx->cipherSetupData.cipherAlgorithm = + CPA_CY_SYM_CIPHER_DES_CBC; + lacSessCtx->cipherSetupData.cipherKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; + break; + + case CRYPTO_3DES_CBC: + DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; + lacSessCtx->cipherSetupData.cipherAlgorithm = + CPA_CY_SYM_CIPHER_3DES_CBC; + lacSessCtx->cipherSetupData.cipherKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; + break; + + case CRYPTO_AES_CBC: + DPRINTK("%s(): AES CBC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; + lacSessCtx->cipherSetupData.cipherAlgorithm = + CPA_CY_SYM_CIPHER_AES_CBC; + lacSessCtx->cipherSetupData.cipherKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; + break; + + case CRYPTO_ARC4: + DPRINTK("%s(): ARC4\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; + lacSessCtx->cipherSetupData.cipherAlgorithm = + CPA_CY_SYM_CIPHER_ARC4; + lacSessCtx->cipherSetupData.cipherKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; + break; + + case CRYPTO_SHA1: + DPRINTK("%s(): SHA1\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); + + break; + + case CRYPTO_SHA1_HMAC: + DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); + lacSessCtx->hashSetupData.authModeSetupData.authKey = + cri->cri_key; + lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; + + break; + + case CRYPTO_SHA2_256: + DPRINTK("%s(): SHA256\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = + CPA_CY_SYM_HASH_SHA256; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); + + break; + + case CRYPTO_SHA2_256_HMAC: + DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = + CPA_CY_SYM_HASH_SHA256; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); + lacSessCtx->hashSetupData.authModeSetupData.authKey = + cri->cri_key; + lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; + + break; + + case CRYPTO_SHA2_384: + DPRINTK("%s(): SHA384\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = + CPA_CY_SYM_HASH_SHA384; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); + + break; + + case CRYPTO_SHA2_384_HMAC: + DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = + CPA_CY_SYM_HASH_SHA384; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); + lacSessCtx->hashSetupData.authModeSetupData.authKey = + cri->cri_key; + lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; + + break; + + case CRYPTO_SHA2_512: + DPRINTK("%s(): SHA512\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = + CPA_CY_SYM_HASH_SHA512; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); + + break; + + case CRYPTO_SHA2_512_HMAC: + DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = + CPA_CY_SYM_HASH_SHA512; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); + lacSessCtx->hashSetupData.authModeSetupData.authKey = + cri->cri_key; + lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; + + break; + + case CRYPTO_MD5: + DPRINTK("%s(): MD5\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); + + break; + + case CRYPTO_MD5_HMAC: + DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); + lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; + lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; + lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; + lacSessCtx->hashSetupData.digestResultLenInBytes = + (cri->cri_mlen ? + cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); + lacSessCtx->hashSetupData.authModeSetupData.authKey = + cri->cri_key; + lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = + cri->cri_klen / NUM_BITS_IN_BYTE; + lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; + + break; + + default: + DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); + return ICP_OCF_DRV_STATUS_FAIL; + } + + return ICP_OCF_DRV_STATUS_SUCCESS; +} + +/* Name : icp_ocfDrvFreeOCFSession + * + * Description : This function deletes all existing Session data representing + * the Cryptographic session established between OCF and this driver. This + * also includes freeing the memory allocated for the session context. The + * session object is also removed from the session linked list. + */ +static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) +{ + + sessionData->inUse = ICP_SESSION_DEREGISTERED; + + /*ENTER CRITICAL SECTION */ + icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); + + if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { + /*If the Driver is exiting, allow that process to + handle any deletions */ + /*EXIT CRITICAL SECTION */ + icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); + return; + } + + icp_atomic_dec(&num_ocf_to_drv_registered_sessions); + + ICP_LIST_DEL(sessionData, listNode); + + /*EXIT CRITICAL SECTION */ + icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); + + if (NULL != sessionData->sessHandle) { + icp_kfree(sessionData->sessHandle); + } + ICP_CACHE_FREE(drvSessionData_zone, sessionData); +} + +/* Name : icp_ocfDrvFreeLACSession + * + * Description : This attempts to deregister a LAC session. If it fails, the + * deregistation retry function is called. + */ +int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) +{ + CpaCySymSessionCtx sessionToDeregister = NULL; + struct icp_drvSessionData *sessionData = NULL; + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + int retval = 0; + + sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); + if (NULL == sessionData) { + EPRINTK("%s(): OCF Free session called with Null Session ID.\n", + __FUNCTION__); + return EINVAL; + } + + sessionToDeregister = sessionData->sessHandle; + + if ((ICP_SESSION_INITIALISED != sessionData->inUse) && + (ICP_SESSION_RUNNING != sessionData->inUse) && + (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { + DPRINTK("%s() Session not initialised.\n", __FUNCTION__); + return EINVAL; + } + + if (ICP_SESSION_RUNNING == sessionData->inUse) { + lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, + sessionToDeregister); + if (CPA_STATUS_RETRY == lacStatus) { + if (ICP_OCF_DRV_STATUS_SUCCESS != + icp_ocfDrvDeregRetry(&sessionToDeregister)) { + /* the retry function increments the + dereg failed count */ + DPRINTK("%s(): LAC failed to deregister the " + "session. (localSessionId= %p)\n", + __FUNCTION__, sessionToDeregister); + retval = EPERM; + } + + } else if (CPA_STATUS_SUCCESS != lacStatus) { + DPRINTK("%s(): LAC failed to deregister the session. " + "localSessionId= %p, lacStatus = %d\n", + __FUNCTION__, sessionToDeregister, lacStatus); + icp_atomic_inc(&lac_session_failed_dereg_count); + retval = EPERM; + } + } else { + DPRINTK("%s() Session not registered with LAC.\n", + __FUNCTION__); + } + + icp_ocfDrvFreeOCFSession(sessionData); + return retval; + +} + +/* Name : icp_ocfDrvAlgCheck + * + * Description : This function checks whether the cryptodesc argument pertains + * to a sym or hash function + */ +static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) +{ + + if (crp_desc->crd_alg == CRYPTO_3DES_CBC || + crp_desc->crd_alg == CRYPTO_AES_CBC || + crp_desc->crd_alg == CRYPTO_DES_CBC || + crp_desc->crd_alg == CRYPTO_NULL_CBC || + crp_desc->crd_alg == CRYPTO_ARC4) { + return ICP_OCF_DRV_ALG_CIPHER; + } + + return ICP_OCF_DRV_ALG_HASH; +} + +/* Name : icp_ocfDrvSymProcess + * + * Description : This function will map symmetric functionality calls from OCF + * to the LAC API. It will also allocate memory to store the session context. + * + * Notes: If it is the first perform call for a given session, then a LAC + * session is registered. After the session is registered, no checks as + * to whether session paramaters have changed (e.g. alg chain order) are + * done. + */ +int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) +{ + struct icp_drvSessionData *sessionData = NULL; + struct icp_drvOpData *drvOpData = NULL; + CpaStatus lacStatus = CPA_STATUS_SUCCESS; + Cpa32U sessionCtxSizeInBytes = 0; + + if (NULL == crp) { + DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", + __FUNCTION__); + return EINVAL; + } + + if (NULL == crp->crp_desc) { + DPRINTK("%s(): Invalid input parameters, no crp_desc attached " + "to crp\n", __FUNCTION__); + crp->crp_etype = EINVAL; + return EINVAL; + } + + if (NULL == crp->crp_buf) { + DPRINTK("%s(): Invalid input parameters, no buffer attached " + "to crp\n", __FUNCTION__); + crp->crp_etype = EINVAL; + return EINVAL; + } + + if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { + crp->crp_etype = EFAULT; + return EFAULT; + } + + sessionData = (struct icp_drvSessionData *) + (CRYPTO_SESID2LID(crp->crp_sid)); + if (NULL == sessionData) { + DPRINTK("%s(): Invalid input parameters, Null Session ID \n", + __FUNCTION__); + crp->crp_etype = EINVAL; + return EINVAL; + } + +/*If we get a request against a deregisted session, cancel operation*/ + if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { + DPRINTK("%s(): Session ID %d was deregistered \n", + __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); + crp->crp_etype = EFAULT; + return EFAULT; + } + +/*If none of the session states are set, then the session structure was either + not initialised properly or we are reading from a freed memory area (possible + due to OCF batch mode not removing queued requests against deregistered + sessions*/ + if (ICP_SESSION_INITIALISED != sessionData->inUse && + ICP_SESSION_RUNNING != sessionData->inUse) { + DPRINTK("%s(): Session - ID %d - not properly initialised or " + "memory freed back to the kernel \n", + __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); + crp->crp_etype = EINVAL; + return EINVAL; + } + + /*For the below checks, remember error checking is already done in LAC. + We're not validating inputs subsequent to registration */ + if (sessionData->inUse == ICP_SESSION_INITIALISED) { + DPRINTK("%s(): Initialising session\n", __FUNCTION__); + + if (NULL != crp->crp_desc->crd_next) { + if (ICP_OCF_DRV_ALG_CIPHER == + icp_ocfDrvAlgCheck(crp->crp_desc)) { + + sessionData->lacSessCtx.algChainOrder = + CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; + + if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { + sessionData->lacSessCtx.cipherSetupData. + cipherDirection = + CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; + } else { + sessionData->lacSessCtx.cipherSetupData. + cipherDirection = + CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; + } + } else { + sessionData->lacSessCtx.algChainOrder = + CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; + + if (crp->crp_desc->crd_next->crd_flags & + CRD_F_ENCRYPT) { + sessionData->lacSessCtx.cipherSetupData. + cipherDirection = + CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; + } else { + sessionData->lacSessCtx.cipherSetupData. + cipherDirection = + CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; + } + + } + + } else if (ICP_OCF_DRV_ALG_CIPHER == + icp_ocfDrvAlgCheck(crp->crp_desc)) { + if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { + sessionData->lacSessCtx.cipherSetupData. + cipherDirection = + CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; + } else { + sessionData->lacSessCtx.cipherSetupData. + cipherDirection = + CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; + } + + } + + /*No action required for standalone Auth here */ + + /* Allocate memory for SymSessionCtx before the Session Registration */ + lacStatus = + cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, + &(sessionData->lacSessCtx), + &sessionCtxSizeInBytes); + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", + __FUNCTION__, lacStatus); + crp->crp_etype = EINVAL; + return EINVAL; + } + sessionData->sessHandle = + icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); + if (NULL == sessionData->sessHandle) { + EPRINTK + ("%s(): Failed to get memory for SymSessionCtx\n", + __FUNCTION__); + crp->crp_etype = ENOMEM; + return ENOMEM; + } + + lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, + icp_ocfDrvSymCallBack, + &(sessionData->lacSessCtx), + sessionData->sessHandle); + + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): cpaCySymInitSession failed -%d \n", + __FUNCTION__, lacStatus); + crp->crp_etype = EFAULT; + return EFAULT; + } + + sessionData->inUse = ICP_SESSION_RUNNING; + } + + drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); + if (NULL == drvOpData) { + EPRINTK("%s():Failed to get memory for drvOpData\n", + __FUNCTION__); + crp->crp_etype = ENOMEM; + return ENOMEM; + } + + drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; + drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. + digestResultLenInBytes; + drvOpData->crp = crp; + + /* Set the default buffer list array memory allocation */ + drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; + drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; + + if (ICP_OCF_DRV_STATUS_SUCCESS != + icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { + crp->crp_etype = EINVAL; + goto err; + } + + if (drvOpData->crp->crp_desc->crd_next != NULL) { + if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> + crp_desc->crd_next)) { + crp->crp_etype = EINVAL; + goto err; + } + + } + + /* + * Allocate buffer list array memory if the data fragment is more than + * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not + * calculated already + */ + if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { + if (NULL == drvOpData->lacOpData.pDigestResult) { + drvOpData->numBufferListArray = + icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) + crp->crp_buf); + } + + if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < + drvOpData->numBufferListArray) { + DPRINTK("%s() numBufferListArray more than default\n", + __FUNCTION__); + drvOpData->srcBuffer.pBuffers = NULL; + drvOpData->srcBuffer.pBuffers = + icp_kmalloc(drvOpData->numBufferListArray * + sizeof(CpaFlatBuffer), ICP_M_NOWAIT); + if (NULL == drvOpData->srcBuffer.pBuffers) { + EPRINTK("%s() Failed to get memory for " + "pBuffers\n", __FUNCTION__); + ICP_CACHE_FREE(drvOpData_zone, drvOpData); + crp->crp_etype = ENOMEM; + return ENOMEM; + } + } + } + + /* + * Check the type of buffer structure we got and convert it into + * CpaBufferList format. + */ + if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { + if (ICP_OCF_DRV_STATUS_SUCCESS != + icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) + crp->crp_buf, + &(drvOpData->srcBuffer))) { + EPRINTK("%s():Failed to translate from packet buffer " + "to bufferlist\n", __FUNCTION__); + crp->crp_etype = EINVAL; + goto err; + } + + drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; + } else if (crp->crp_flags & CRYPTO_F_IOV) { + /* OCF only supports IOV of one entry. */ + if (NUM_IOV_SUPPORTED == + ((struct uio *)(crp->crp_buf))->uio_iovcnt) { + + icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> + crp_buf))-> + uio_iov[0].iov_base, + ((struct uio *)(crp-> + crp_buf))-> + uio_iov[0].iov_len, + &(drvOpData-> + srcBuffer)); + + drvOpData->bufferType = CRYPTO_F_IOV; + + } else { + DPRINTK("%s():Unable to handle IOVs with lengths of " + "greater than one!\n", __FUNCTION__); + crp->crp_etype = EINVAL; + goto err; + } + + } else { + icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, + crp->crp_ilen, + &(drvOpData->srcBuffer)); + + drvOpData->bufferType = CRYPTO_BUF_CONTIG; + } + + /* Allocate srcBuffer's private meta data */ + if (ICP_OCF_DRV_STATUS_SUCCESS != + icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { + EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); + memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); + crp->crp_etype = EINVAL; + goto err; + } + + /* Perform "in-place" crypto operation */ + lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, + (void *)drvOpData, + &(drvOpData->lacOpData), + &(drvOpData->srcBuffer), + &(drvOpData->srcBuffer), + &(drvOpData->verifyResult)); + if (CPA_STATUS_RETRY == lacStatus) { + DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", + __FUNCTION__, lacStatus); + memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); + crp->crp_etype = ERESTART; + goto err; + } + if (CPA_STATUS_SUCCESS != lacStatus) { + EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", + __FUNCTION__, lacStatus); + memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); + crp->crp_etype = EINVAL; + goto err; + } + + return 0; //OCF success status value + + err: + if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { + icp_kfree(drvOpData->srcBuffer.pBuffers); + } + icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); + ICP_CACHE_FREE(drvOpData_zone, drvOpData); + + return crp->crp_etype; +} + +/* Name : icp_ocfDrvProcessDataSetup + * + * Description : This function will setup all the cryptographic operation data + * that is required by LAC to execute the operation. + */ +static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, + struct cryptodesc *crp_desc) +{ + CpaCyRandGenOpData randGenOpData; + CpaFlatBuffer randData; + + drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; + + /* Convert from the cryptop to the ICP LAC crypto parameters */ + switch (crp_desc->crd_alg) { + case CRYPTO_NULL_CBC: + drvOpData->lacOpData. + cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; + drvOpData->lacOpData. + messageLenToCipherInBytes = crp_desc->crd_len; + drvOpData->verifyResult = CPA_FALSE; + drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; + break; + case CRYPTO_DES_CBC: + drvOpData->lacOpData. + cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; + drvOpData->lacOpData. + messageLenToCipherInBytes = crp_desc->crd_len; + drvOpData->verifyResult = CPA_FALSE; + drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; + break; + case CRYPTO_3DES_CBC: + drvOpData->lacOpData. + cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; + drvOpData->lacOpData. + messageLenToCipherInBytes = crp_desc->crd_len; + drvOpData->verifyResult = CPA_FALSE; + drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; + break; + case CRYPTO_ARC4: + drvOpData->lacOpData. + cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; + drvOpData->lacOpData. + messageLenToCipherInBytes = crp_desc->crd_len; + drvOpData->verifyResult = CPA_FALSE; + drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; + break; + case CRYPTO_AES_CBC: + drvOpData->lacOpData. + cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; + drvOpData->lacOpData. + messageLenToCipherInBytes = crp_desc->crd_len; + drvOpData->verifyResult = CPA_FALSE; + drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; + break; + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + case CRYPTO_SHA2_256: + case CRYPTO_SHA2_256_HMAC: + case CRYPTO_SHA2_384: + case CRYPTO_SHA2_384_HMAC: + case CRYPTO_SHA2_512: + case CRYPTO_SHA2_512_HMAC: + case CRYPTO_MD5: + case CRYPTO_MD5_HMAC: + drvOpData->lacOpData. + hashStartSrcOffsetInBytes = crp_desc->crd_skip; + drvOpData->lacOpData. + messageLenToHashInBytes = crp_desc->crd_len; + drvOpData->lacOpData. + pDigestResult = + icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); + + if (NULL == drvOpData->lacOpData.pDigestResult) { + DPRINTK("%s(): ERROR - could not calculate " + "Digest Result memory address\n", __FUNCTION__); + return ICP_OCF_DRV_STATUS_FAIL; + } + + drvOpData->lacOpData.digestVerify = CPA_FALSE; + break; + default: + DPRINTK("%s(): Crypto process error - algorithm not " + "found \n", __FUNCTION__); + return ICP_OCF_DRV_STATUS_FAIL; + } + + /* Figure out what the IV is supposed to be */ + if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || + (crp_desc->crd_alg == CRYPTO_3DES_CBC) || + (crp_desc->crd_alg == CRYPTO_AES_CBC)) { + /*ARC4 doesn't use an IV */ + if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { + /* Explicit IV provided to OCF */ + drvOpData->lacOpData.pIv = crp_desc->crd_iv; + } else { + /* IV is not explicitly provided to OCF */ + + /* Point the LAC OP Data IV pointer to our allocated + storage location for this session. */ + drvOpData->lacOpData.pIv = drvOpData->ivData; + + if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && + ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { + + /* Encrypting - need to create IV */ + randGenOpData.generateBits = CPA_TRUE; + randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; + + icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) + drvOpData-> + ivData, + MAX_IV_LEN_IN_BYTES, + &randData); + + if (CPA_STATUS_SUCCESS != + cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, + NULL, NULL, + &randGenOpData, &randData)) { + DPRINTK("%s(): ERROR - Failed to" + " generate" + " Initialisation Vector\n", + __FUNCTION__); + return ICP_OCF_DRV_STATUS_FAIL; + } + + crypto_copyback(drvOpData->crp-> + crp_flags, + drvOpData->crp->crp_buf, + crp_desc->crd_inject, + drvOpData->lacOpData. + ivLenInBytes, + (caddr_t) (drvOpData->lacOpData. + pIv)); + } else { + /* Reading IV from buffer */ + crypto_copydata(drvOpData->crp-> + crp_flags, + drvOpData->crp->crp_buf, + crp_desc->crd_inject, + drvOpData->lacOpData. + ivLenInBytes, + (caddr_t) (drvOpData->lacOpData. + pIv)); + } + + } + + } + + return ICP_OCF_DRV_STATUS_SUCCESS; +} + +/* Name : icp_ocfDrvDigestPointerFind + * + * Description : This function is used to find the memory address of where the + * digest information shall be stored in. Input buffer types are an skbuff, iov + * or flat buffer. The address is found using the buffer data start address and + * an offset. + * + * Note: In the case of a linux skbuff, the digest address may exist within + * a memory space linked to from the start buffer. These linked memory spaces + * must be traversed by the data length offset in order to find the digest start + * address. Whether there is enough space for the digest must also be checked. + */ +uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, + struct cryptodesc * crp_desc) +{ + + int offsetInBytes = crp_desc->crd_inject; + uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; + uint8_t *flat_buffer_base = NULL; + int flat_buffer_length = 0; + + if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { + + return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, + offsetInBytes, + digestSizeInBytes); + + } else { + /* IOV or flat buffer */ + if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { + /*single IOV check has already been done */ + flat_buffer_base = ((struct uio *) + (drvOpData->crp->crp_buf))-> + uio_iov[0].iov_base; + flat_buffer_length = ((struct uio *) + (drvOpData->crp->crp_buf))-> + uio_iov[0].iov_len; + } else { + flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; + flat_buffer_length = drvOpData->crp->crp_ilen; + } + + if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { + DPRINTK("%s() Not enough space for Digest " + "(IOV/Flat Buffer) \n", __FUNCTION__); + return NULL; + } else { + return (uint8_t *) (flat_buffer_base + offsetInBytes); + } + } + DPRINTK("%s() Should not reach this point\n", __FUNCTION__); + return NULL; +} diff --git a/target/linux/generic/files/crypto/ocf/ep80579/linux_2.6_kernel_space.mk b/target/linux/generic/files/crypto/ocf/ep80579/linux_2.6_kernel_space.mk new file mode 100644 index 0000000..96afa9a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ep80579/linux_2.6_kernel_space.mk @@ -0,0 +1,69 @@ +################### +# @par +# This file is provided under a dual BSD/GPLv2 license. When using or +# redistributing this file, you may do so under either license. +# +# GPL LICENSE SUMMARY +# +# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of version 2 of the GNU General Public License as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. +# The full GNU General Public License is included in this distribution +# in the file called LICENSE.GPL. +# +# Contact Information: +# Intel Corporation +# +# BSD LICENSE +# +# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# +# version: Security.L.1.0.130 +################### + +#specific include directories in kernel space +INCLUDES+=#e.g. -I$(OSAL_DIR)/include \ + +#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include +EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall +EXTRA_LDFLAGS +=-whole-archive + diff --git a/target/linux/generic/files/crypto/ocf/hifn/Makefile b/target/linux/generic/files/crypto/ocf/hifn/Makefile new file mode 100644 index 0000000..163fed0 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/hifn/Makefile @@ -0,0 +1,13 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_HIFN) += hifn7751.o +obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o + +obj ?= . +EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/hifn/hifn7751.c b/target/linux/generic/files/crypto/ocf/hifn/hifn7751.c new file mode 100644 index 0000000..3e5cc9b --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/hifn/hifn7751.c @@ -0,0 +1,2954 @@ +/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ + +/*- + * Invertex AEON / Hifn 7751 driver + * Copyright (c) 1999 Invertex Inc. All rights reserved. + * Copyright (c) 1999 Theo de Raadt + * Copyright (c) 2000-2001 Network Security Technologies, Inc. + * http://www.netsec.net + * Copyright (c) 2003 Hifn Inc. + * + * This driver is based on a previous driver by Invertex, for which they + * requested: Please send any comments, feedback, bug-fixes, or feature + * requests to software@invertex.com. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + * +__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); + */ + +/* + * Driver for various Hifn encryption processors. + */ +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#if 1 +#define DPRINTF(a...) if (hifn_debug) { \ + printk("%s: ", sc ? \ + device_get_nameunit(sc->sc_dev) : "hifn"); \ + printk(a); \ + } else +#else +#define DPRINTF(a...) +#endif + +static inline int +pci_get_revid(struct pci_dev *dev) +{ + u8 rid = 0; + pci_read_config_byte(dev, PCI_REVISION_ID, &rid); + return rid; +} + +static struct hifn_stats hifnstats; + +#define debug hifn_debug +int hifn_debug = 0; +module_param(hifn_debug, int, 0644); +MODULE_PARM_DESC(hifn_debug, "Enable debug"); + +int hifn_maxbatch = 1; +module_param(hifn_maxbatch, int, 0644); +MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); + +int hifn_cache_linesize = 0x10; +module_param(hifn_cache_linesize, int, 0444); +MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); + +#ifdef MODULE_PARM +char *hifn_pllconfig = NULL; +MODULE_PARM(hifn_pllconfig, "s"); +#else +char hifn_pllconfig[32]; /* This setting is RO after loading */ +module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); +#endif +MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); + +#ifdef HIFN_VULCANDEV +#include +#include + +static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ +#endif + +/* + * Prototypes and count for the pci_device structure + */ +static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); +static void hifn_remove(struct pci_dev *dev); + +static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); +static int hifn_freesession(device_t, u_int64_t); +static int hifn_process(device_t, struct cryptop *, int); + +static device_method_t hifn_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, hifn_newsession), + DEVMETHOD(cryptodev_freesession,hifn_freesession), + DEVMETHOD(cryptodev_process, hifn_process), +}; + +static void hifn_reset_board(struct hifn_softc *, int); +static void hifn_reset_puc(struct hifn_softc *); +static void hifn_puc_wait(struct hifn_softc *); +static int hifn_enable_crypto(struct hifn_softc *); +static void hifn_set_retry(struct hifn_softc *sc); +static void hifn_init_dma(struct hifn_softc *); +static void hifn_init_pci_registers(struct hifn_softc *); +static int hifn_sramsize(struct hifn_softc *); +static int hifn_dramsize(struct hifn_softc *); +static int hifn_ramtype(struct hifn_softc *); +static void hifn_sessions(struct hifn_softc *); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) +static irqreturn_t hifn_intr(int irq, void *arg); +#else +static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); +#endif +static u_int hifn_write_command(struct hifn_command *, u_int8_t *); +static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); +static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); +static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); +static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); +static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); +static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); +static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); +static int hifn_init_pubrng(struct hifn_softc *); +static void hifn_tick(unsigned long arg); +static void hifn_abort(struct hifn_softc *); +static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); + +static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); +static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); + +#ifdef CONFIG_OCF_RANDOMHARVEST +static int hifn_read_random(void *arg, u_int32_t *buf, int len); +#endif + +#define HIFN_MAX_CHIPS 8 +static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; + +static __inline u_int32_t +READ_REG_0(struct hifn_softc *sc, bus_size_t reg) +{ + u_int32_t v = readl(sc->sc_bar0 + reg); + sc->sc_bar0_lastreg = (bus_size_t) -1; + return (v); +} +#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) + +static __inline u_int32_t +READ_REG_1(struct hifn_softc *sc, bus_size_t reg) +{ + u_int32_t v = readl(sc->sc_bar1 + reg); + sc->sc_bar1_lastreg = (bus_size_t) -1; + return (v); +} +#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) + +/* + * map in a given buffer (great on some arches :-) + */ + +static int +pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) +{ + struct iovec *iov = uio->uio_iov; + + DPRINTF("%s()\n", __FUNCTION__); + + buf->mapsize = 0; + for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { + buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, + iov->iov_base, iov->iov_len, + PCI_DMA_BIDIRECTIONAL); + buf->segs[buf->nsegs].ds_len = iov->iov_len; + buf->mapsize += iov->iov_len; + iov++; + buf->nsegs++; + } + /* identify this buffer by the first segment */ + buf->map = (void *) buf->segs[0].ds_addr; + return(0); +} + +/* + * map in a given sk_buff + */ + +static int +pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) +{ + int i; + + DPRINTF("%s()\n", __FUNCTION__); + + buf->mapsize = 0; + + buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, + skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); + buf->segs[0].ds_len = skb_headlen(skb); + buf->mapsize += buf->segs[0].ds_len; + + buf->nsegs = 1; + + for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { + buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; + buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, + page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) + + skb_shinfo(skb)->frags[i].page_offset, + buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); + buf->mapsize += buf->segs[buf->nsegs].ds_len; + buf->nsegs++; + } + + /* identify this buffer by the first segment */ + buf->map = (void *) buf->segs[0].ds_addr; + return(0); +} + +/* + * map in a given contiguous buffer + */ + +static int +pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) +{ + DPRINTF("%s()\n", __FUNCTION__); + + buf->mapsize = 0; + buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, + b, len, PCI_DMA_BIDIRECTIONAL); + buf->segs[0].ds_len = len; + buf->mapsize += buf->segs[0].ds_len; + buf->nsegs = 1; + + /* identify this buffer by the first segment */ + buf->map = (void *) buf->segs[0].ds_addr; + return(0); +} + +#if 0 /* not needed at this time */ +static void +pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) +{ + int i; + + DPRINTF("%s()\n", __FUNCTION__); + for (i = 0; i < buf->nsegs; i++) + pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, + buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); +} +#endif + +static void +pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) +{ + int i; + DPRINTF("%s()\n", __FUNCTION__); + for (i = 0; i < buf->nsegs; i++) { + pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, + buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); + buf->segs[i].ds_addr = 0; + buf->segs[i].ds_len = 0; + } + buf->nsegs = 0; + buf->mapsize = 0; + buf->map = 0; +} + +static const char* +hifn_partname(struct hifn_softc *sc) +{ + /* XXX sprintf numbers when not decoded */ + switch (pci_get_vendor(sc->sc_pcidev)) { + case PCI_VENDOR_HIFN: + switch (pci_get_device(sc->sc_pcidev)) { + case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; + case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; + case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; + case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; + case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; + case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; + } + return "Hifn unknown-part"; + case PCI_VENDOR_INVERTEX: + switch (pci_get_device(sc->sc_pcidev)) { + case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; + } + return "Invertex unknown-part"; + case PCI_VENDOR_NETSEC: + switch (pci_get_device(sc->sc_pcidev)) { + case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; + } + return "NetSec unknown-part"; + } + return "Unknown-vendor unknown-part"; +} + +static u_int +checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) +{ + struct hifn_softc *sc = pci_get_drvdata(dev); + if (v > max) { + device_printf(sc->sc_dev, "Warning, %s %u out of range, " + "using max %u\n", what, v, max); + v = max; + } else if (v < min) { + device_printf(sc->sc_dev, "Warning, %s %u out of range, " + "using min %u\n", what, v, min); + v = min; + } + return v; +} + +/* + * Select PLL configuration for 795x parts. This is complicated in + * that we cannot determine the optimal parameters without user input. + * The reference clock is derived from an external clock through a + * multiplier. The external clock is either the host bus (i.e. PCI) + * or an external clock generator. When using the PCI bus we assume + * the clock is either 33 or 66 MHz; for an external source we cannot + * tell the speed. + * + * PLL configuration is done with a string: "pci" for PCI bus, or "ext" + * for an external source, followed by the frequency. We calculate + * the appropriate multiplier and PLL register contents accordingly. + * When no configuration is given we default to "pci66" since that + * always will allow the card to work. If a card is using the PCI + * bus clock and in a 33MHz slot then it will be operating at half + * speed until the correct information is provided. + * + * We use a default setting of "ext66" because according to Mike Ham + * of HiFn, almost every board in existence has an external crystal + * populated at 66Mhz. Using PCI can be a problem on modern motherboards, + * because PCI33 can have clocks from 0 to 33Mhz, and some have + * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. + */ +static void +hifn_getpllconfig(struct pci_dev *dev, u_int *pll) +{ + const char *pllspec = hifn_pllconfig; + u_int freq, mul, fl, fh; + u_int32_t pllconfig; + char *nxt; + + if (pllspec == NULL) + pllspec = "ext66"; + fl = 33, fh = 66; + pllconfig = 0; + if (strncmp(pllspec, "ext", 3) == 0) { + pllspec += 3; + pllconfig |= HIFN_PLL_REF_SEL; + switch (pci_get_device(dev)) { + case PCI_PRODUCT_HIFN_7955: + case PCI_PRODUCT_HIFN_7956: + fl = 20, fh = 100; + break; +#ifdef notyet + case PCI_PRODUCT_HIFN_7954: + fl = 20, fh = 66; + break; +#endif + } + } else if (strncmp(pllspec, "pci", 3) == 0) + pllspec += 3; + freq = strtoul(pllspec, &nxt, 10); + if (nxt == pllspec) + freq = 66; + else + freq = checkmaxmin(dev, "frequency", freq, fl, fh); + /* + * Calculate multiplier. We target a Fck of 266 MHz, + * allowing only even values, possibly rounded down. + * Multipliers > 8 must set the charge pump current. + */ + mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); + pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; + if (mul > 8) + pllconfig |= HIFN_PLL_IS; + *pll = pllconfig; +} + +/* + * Attach an interface that successfully probed. + */ +static int +hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) +{ + struct hifn_softc *sc = NULL; + char rbase; + u_int16_t ena, rev; + int rseg, rc; + unsigned long mem_start, mem_len; + static int num_chips = 0; + + DPRINTF("%s()\n", __FUNCTION__); + + if (pci_enable_device(dev) < 0) + return(-ENODEV); + + if (pci_set_mwi(dev)) + return(-ENODEV); + + if (!dev->irq) { + printk("hifn: found device with no IRQ assigned. check BIOS settings!"); + pci_disable_device(dev); + return(-ENODEV); + } + + sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); + if (!sc) + return(-ENOMEM); + memset(sc, 0, sizeof(*sc)); + + softc_device_init(sc, "hifn", num_chips, hifn_methods); + + sc->sc_pcidev = dev; + sc->sc_irq = -1; + sc->sc_cid = -1; + sc->sc_num = num_chips++; + if (sc->sc_num < HIFN_MAX_CHIPS) + hifn_chip_idx[sc->sc_num] = sc; + + pci_set_drvdata(sc->sc_pcidev, sc); + + spin_lock_init(&sc->sc_mtx); + + /* XXX handle power management */ + + /* + * The 7951 and 795x have a random number generator and + * public key support; note this. + */ + if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && + (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || + pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || + pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) + sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; + /* + * The 7811 has a random number generator and + * we also note it's identity 'cuz of some quirks. + */ + if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && + pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) + sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; + + /* + * The 795x parts support AES. + */ + if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && + (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || + pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { + sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; + /* + * Select PLL configuration. This depends on the + * bus and board design and must be manually configured + * if the default setting is unacceptable. + */ + hifn_getpllconfig(dev, &sc->sc_pllconfig); + } + + /* + * Setup PCI resources. Note that we record the bus + * tag and handle for each register mapping, this is + * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, + * and WRITE_REG_1 macros throughout the driver. + */ + mem_start = pci_resource_start(sc->sc_pcidev, 0); + mem_len = pci_resource_len(sc->sc_pcidev, 0); + sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); + if (!sc->sc_bar0) { + device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); + goto fail; + } + sc->sc_bar0_lastreg = (bus_size_t) -1; + + mem_start = pci_resource_start(sc->sc_pcidev, 1); + mem_len = pci_resource_len(sc->sc_pcidev, 1); + sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); + if (!sc->sc_bar1) { + device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); + goto fail; + } + sc->sc_bar1_lastreg = (bus_size_t) -1; + + /* fix up the bus size */ + if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { + device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); + goto fail; + } + if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { + device_printf(sc->sc_dev, + "No usable consistent DMA configuration, aborting.\n"); + goto fail; + } + + hifn_set_retry(sc); + + /* + * Setup the area where the Hifn DMA's descriptors + * and associated data structures. + */ + sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, + sizeof(*sc->sc_dma), + &sc->sc_dma_physaddr); + if (!sc->sc_dma) { + device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); + goto fail; + } + bzero(sc->sc_dma, sizeof(*sc->sc_dma)); + + /* + * Reset the board and do the ``secret handshake'' + * to enable the crypto support. Then complete the + * initialization procedure by setting up the interrupt + * and hooking in to the system crypto support so we'll + * get used for system services like the crypto device, + * IPsec, RNG device, etc. + */ + hifn_reset_board(sc, 0); + + if (hifn_enable_crypto(sc) != 0) { + device_printf(sc->sc_dev, "crypto enabling failed\n"); + goto fail; + } + hifn_reset_puc(sc); + + hifn_init_dma(sc); + hifn_init_pci_registers(sc); + + pci_set_master(sc->sc_pcidev); + + /* XXX can't dynamically determine ram type for 795x; force dram */ + if (sc->sc_flags & HIFN_IS_7956) + sc->sc_drammodel = 1; + else if (hifn_ramtype(sc)) + goto fail; + + if (sc->sc_drammodel == 0) + hifn_sramsize(sc); + else + hifn_dramsize(sc); + + /* + * Workaround for NetSec 7751 rev A: half ram size because two + * of the address lines were left floating + */ + if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && + pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && + pci_get_revid(dev) == 0x61) /*XXX???*/ + sc->sc_ramsize >>= 1; + + /* + * Arrange the interrupt line. + */ + rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); + if (rc) { + device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); + goto fail; + } + sc->sc_irq = dev->irq; + + hifn_sessions(sc); + + /* + * NB: Keep only the low 16 bits; this masks the chip id + * from the 7951. + */ + rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; + + rseg = sc->sc_ramsize / 1024; + rbase = 'K'; + if (sc->sc_ramsize >= (1024 * 1024)) { + rbase = 'M'; + rseg /= 1024; + } + device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", + hifn_partname(sc), rev, + rseg, rbase, sc->sc_drammodel ? 'd' : 's'); + if (sc->sc_flags & HIFN_IS_7956) + printf(", pll=0x%x<%s clk, %ux mult>", + sc->sc_pllconfig, + sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", + 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); + printf("\n"); + + sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); + if (sc->sc_cid < 0) { + device_printf(sc->sc_dev, "could not get crypto driver id\n"); + goto fail; + } + + WRITE_REG_0(sc, HIFN_0_PUCNFG, + READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); + ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; + + switch (ena) { + case HIFN_PUSTAT_ENA_2: + crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); + if (sc->sc_flags & HIFN_HAS_AES) + crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); + /*FALLTHROUGH*/ + case HIFN_PUSTAT_ENA_1: + crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); + break; + } + + if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) + hifn_init_pubrng(sc); + + init_timer(&sc->sc_tickto); + sc->sc_tickto.function = hifn_tick; + sc->sc_tickto.data = (unsigned long) sc->sc_num; + mod_timer(&sc->sc_tickto, jiffies + HZ); + + return (0); + +fail: + if (sc->sc_cid >= 0) + crypto_unregister_all(sc->sc_cid); + if (sc->sc_irq != -1) + free_irq(sc->sc_irq, sc); + if (sc->sc_dma) { + /* Turn off DMA polling */ + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | + HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); + + pci_free_consistent(sc->sc_pcidev, + sizeof(*sc->sc_dma), + sc->sc_dma, sc->sc_dma_physaddr); + } + kfree(sc); + return (-ENXIO); +} + +/* + * Detach an interface that successfully probed. + */ +static void +hifn_remove(struct pci_dev *dev) +{ + struct hifn_softc *sc = pci_get_drvdata(dev); + unsigned long l_flags; + + DPRINTF("%s()\n", __FUNCTION__); + + KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); + + /* disable interrupts */ + HIFN_LOCK(sc); + WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); + HIFN_UNLOCK(sc); + + /*XXX other resources */ + del_timer_sync(&sc->sc_tickto); + + /* Turn off DMA polling */ + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | + HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); + + crypto_unregister_all(sc->sc_cid); + + free_irq(sc->sc_irq, sc); + + pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), + sc->sc_dma, sc->sc_dma_physaddr); +} + + +static int +hifn_init_pubrng(struct hifn_softc *sc) +{ + int i; + + DPRINTF("%s()\n", __FUNCTION__); + + if ((sc->sc_flags & HIFN_IS_7811) == 0) { + /* Reset 7951 public key/rng engine */ + WRITE_REG_1(sc, HIFN_1_PUB_RESET, + READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); + + for (i = 0; i < 100; i++) { + DELAY(1000); + if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & + HIFN_PUBRST_RESET) == 0) + break; + } + + if (i == 100) { + device_printf(sc->sc_dev, "public key init failed\n"); + return (1); + } + } + + /* Enable the rng, if available */ +#ifdef CONFIG_OCF_RANDOMHARVEST + if (sc->sc_flags & HIFN_HAS_RNG) { + if (sc->sc_flags & HIFN_IS_7811) { + u_int32_t r; + r = READ_REG_1(sc, HIFN_1_7811_RNGENA); + if (r & HIFN_7811_RNGENA_ENA) { + r &= ~HIFN_7811_RNGENA_ENA; + WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); + } + WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, + HIFN_7811_RNGCFG_DEFL); + r |= HIFN_7811_RNGENA_ENA; + WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); + } else + WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, + READ_REG_1(sc, HIFN_1_RNG_CONFIG) | + HIFN_RNGCFG_ENA); + + sc->sc_rngfirst = 1; + crypto_rregister(sc->sc_cid, hifn_read_random, sc); + } +#endif + + /* Enable public key engine, if available */ + if (sc->sc_flags & HIFN_HAS_PUBLIC) { + WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); + sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; + WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); +#ifdef HIFN_VULCANDEV + sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, + UID_ROOT, GID_WHEEL, 0666, + "vulcanpk"); + sc->sc_pkdev->si_drv1 = sc; +#endif + } + + return (0); +} + +#ifdef CONFIG_OCF_RANDOMHARVEST +static int +hifn_read_random(void *arg, u_int32_t *buf, int len) +{ + struct hifn_softc *sc = (struct hifn_softc *) arg; + u_int32_t sts; + int i, rc = 0; + + if (len <= 0) + return rc; + + if (sc->sc_flags & HIFN_IS_7811) { + /* ONLY VALID ON 7811!!!! */ + for (i = 0; i < 5; i++) { + sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); + if (sts & HIFN_7811_RNGSTS_UFL) { + device_printf(sc->sc_dev, + "RNG underflow: disabling\n"); + /* DAVIDM perhaps return -1 */ + break; + } + if ((sts & HIFN_7811_RNGSTS_RDY) == 0) + break; + + /* + * There are at least two words in the RNG FIFO + * at this point. + */ + if (rc < len) + buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); + if (rc < len) + buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); + } + } else + buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); + + /* NB: discard first data read */ + if (sc->sc_rngfirst) { + sc->sc_rngfirst = 0; + rc = 0; + } + + return(rc); +} +#endif /* CONFIG_OCF_RANDOMHARVEST */ + +static void +hifn_puc_wait(struct hifn_softc *sc) +{ + int i; + int reg = HIFN_0_PUCTRL; + + if (sc->sc_flags & HIFN_IS_7956) { + reg = HIFN_0_PUCTRL2; + } + + for (i = 5000; i > 0; i--) { + DELAY(1); + if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) + break; + } + if (!i) + device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", + READ_REG_0(sc, HIFN_0_PUCTRL)); +} + +/* + * Reset the processing unit. + */ +static void +hifn_reset_puc(struct hifn_softc *sc) +{ + /* Reset processing unit */ + int reg = HIFN_0_PUCTRL; + + if (sc->sc_flags & HIFN_IS_7956) { + reg = HIFN_0_PUCTRL2; + } + WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); + + hifn_puc_wait(sc); +} + +/* + * Set the Retry and TRDY registers; note that we set them to + * zero because the 7811 locks up when forced to retry (section + * 3.6 of "Specification Update SU-0014-04". Not clear if we + * should do this for all Hifn parts, but it doesn't seem to hurt. + */ +static void +hifn_set_retry(struct hifn_softc *sc) +{ + DPRINTF("%s()\n", __FUNCTION__); + /* NB: RETRY only responds to 8-bit reads/writes */ + pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); + pci_write_config_byte(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); + /* piggy back the cache line setting here */ + pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); +} + +/* + * Resets the board. Values in the regesters are left as is + * from the reset (i.e. initial values are assigned elsewhere). + */ +static void +hifn_reset_board(struct hifn_softc *sc, int full) +{ + u_int32_t reg; + + DPRINTF("%s()\n", __FUNCTION__); + /* + * Set polling in the DMA configuration register to zero. 0x7 avoids + * resetting the board and zeros out the other fields. + */ + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | + HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); + + /* + * Now that polling has been disabled, we have to wait 1 ms + * before resetting the board. + */ + DELAY(1000); + + /* Reset the DMA unit */ + if (full) { + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); + DELAY(1000); + } else { + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, + HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); + hifn_reset_puc(sc); + } + + KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); + bzero(sc->sc_dma, sizeof(*sc->sc_dma)); + + /* Bring dma unit out of reset */ + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | + HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); + + hifn_puc_wait(sc); + hifn_set_retry(sc); + + if (sc->sc_flags & HIFN_IS_7811) { + for (reg = 0; reg < 1000; reg++) { + if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & + HIFN_MIPSRST_CRAMINIT) + break; + DELAY(1000); + } + if (reg == 1000) + device_printf(sc->sc_dev, ": cram init timeout\n"); + } else { + /* set up DMA configuration register #2 */ + /* turn off all PK and BAR0 swaps */ + WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, + (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| + (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| + (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| + (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); + } +} + +static u_int32_t +hifn_next_signature(u_int32_t a, u_int cnt) +{ + int i; + u_int32_t v; + + for (i = 0; i < cnt; i++) { + + /* get the parity */ + v = a & 0x80080125; + v ^= v >> 16; + v ^= v >> 8; + v ^= v >> 4; + v ^= v >> 2; + v ^= v >> 1; + + a = (v & 1) ^ (a << 1); + } + + return a; +} + + +/* + * Checks to see if crypto is already enabled. If crypto isn't enable, + * "hifn_enable_crypto" is called to enable it. The check is important, + * as enabling crypto twice will lock the board. + */ +static int +hifn_enable_crypto(struct hifn_softc *sc) +{ + u_int32_t dmacfg, ramcfg, encl, addr, i; + char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 }; + + DPRINTF("%s()\n", __FUNCTION__); + + ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); + dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); + + /* + * The RAM config register's encrypt level bit needs to be set before + * every read performed on the encryption level register. + */ + WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); + + encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; + + /* + * Make sure we don't re-unlock. Two unlocks kills chip until the + * next reboot. + */ + if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { +#ifdef HIFN_DEBUG + if (hifn_debug) + device_printf(sc->sc_dev, + "Strong crypto already enabled!\n"); +#endif + goto report; + } + + if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { +#ifdef HIFN_DEBUG + if (hifn_debug) + device_printf(sc->sc_dev, + "Unknown encryption level 0x%x\n", encl); +#endif + return 1; + } + + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | + HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); + DELAY(1000); + addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); + DELAY(1000); + WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); + DELAY(1000); + + for (i = 0; i <= 12; i++) { + addr = hifn_next_signature(addr, offtbl[i] + 0x101); + WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); + + DELAY(1000); + } + + WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); + encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; + +#ifdef HIFN_DEBUG + if (hifn_debug) { + if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) + device_printf(sc->sc_dev, "Engine is permanently " + "locked until next system reset!\n"); + else + device_printf(sc->sc_dev, "Engine enabled " + "successfully!\n"); + } +#endif + +report: + WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); + + switch (encl) { + case HIFN_PUSTAT_ENA_1: + case HIFN_PUSTAT_ENA_2: + break; + case HIFN_PUSTAT_ENA_0: + default: + device_printf(sc->sc_dev, "disabled\n"); + break; + } + + return 0; +} + +/* + * Give initial values to the registers listed in the "Register Space" + * section of the HIFN Software Development reference manual. + */ +static void +hifn_init_pci_registers(struct hifn_softc *sc) +{ + DPRINTF("%s()\n", __FUNCTION__); + + /* write fixed values needed by the Initialization registers */ + WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); + WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); + WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); + + /* write all 4 ring address registers */ + WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + + offsetof(struct hifn_dma, cmdr[0])); + WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + + offsetof(struct hifn_dma, srcr[0])); + WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + + offsetof(struct hifn_dma, dstr[0])); + WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + + offsetof(struct hifn_dma, resr[0])); + + DELAY(2000); + + /* write status register */ + WRITE_REG_1(sc, HIFN_1_DMA_CSR, + HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | + HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | + HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | + HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | + HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | + HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | + HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | + HIFN_DMACSR_S_WAIT | + HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | + HIFN_DMACSR_C_WAIT | + HIFN_DMACSR_ENGINE | + ((sc->sc_flags & HIFN_HAS_PUBLIC) ? + HIFN_DMACSR_PUBDONE : 0) | + ((sc->sc_flags & HIFN_IS_7811) ? + HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); + + sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; + sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | + HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | + HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | + ((sc->sc_flags & HIFN_IS_7811) ? + HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); + sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; + WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); + + + if (sc->sc_flags & HIFN_IS_7956) { + u_int32_t pll; + + WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | + HIFN_PUCNFG_TCALLPHASES | + HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); + + /* turn off the clocks and insure bypass is set */ + pll = READ_REG_1(sc, HIFN_1_PLL); + pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) + | HIFN_PLL_BP | HIFN_PLL_MBSET; + WRITE_REG_1(sc, HIFN_1_PLL, pll); + DELAY(10*1000); /* 10ms */ + + /* change configuration */ + pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; + WRITE_REG_1(sc, HIFN_1_PLL, pll); + DELAY(10*1000); /* 10ms */ + + /* disable bypass */ + pll &= ~HIFN_PLL_BP; + WRITE_REG_1(sc, HIFN_1_PLL, pll); + /* enable clocks with new configuration */ + pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; + WRITE_REG_1(sc, HIFN_1_PLL, pll); + } else { + WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | + HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | + HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | + (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); + } + + WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | + HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | + ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | + ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); +} + +/* + * The maximum number of sessions supported by the card + * is dependent on the amount of context ram, which + * encryption algorithms are enabled, and how compression + * is configured. This should be configured before this + * routine is called. + */ +static void +hifn_sessions(struct hifn_softc *sc) +{ + u_int32_t pucnfg; + int ctxsize; + + DPRINTF("%s()\n", __FUNCTION__); + + pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); + + if (pucnfg & HIFN_PUCNFG_COMPSING) { + if (pucnfg & HIFN_PUCNFG_ENCCNFG) + ctxsize = 128; + else + ctxsize = 512; + /* + * 7955/7956 has internal context memory of 32K + */ + if (sc->sc_flags & HIFN_IS_7956) + sc->sc_maxses = 32768 / ctxsize; + else + sc->sc_maxses = 1 + + ((sc->sc_ramsize - 32768) / ctxsize); + } else + sc->sc_maxses = sc->sc_ramsize / 16384; + + if (sc->sc_maxses > 2048) + sc->sc_maxses = 2048; +} + +/* + * Determine ram type (sram or dram). Board should be just out of a reset + * state when this is called. + */ +static int +hifn_ramtype(struct hifn_softc *sc) +{ + u_int8_t data[8], dataexpect[8]; + int i; + + for (i = 0; i < sizeof(data); i++) + data[i] = dataexpect[i] = 0x55; + if (hifn_writeramaddr(sc, 0, data)) + return (-1); + if (hifn_readramaddr(sc, 0, data)) + return (-1); + if (bcmp(data, dataexpect, sizeof(data)) != 0) { + sc->sc_drammodel = 1; + return (0); + } + + for (i = 0; i < sizeof(data); i++) + data[i] = dataexpect[i] = 0xaa; + if (hifn_writeramaddr(sc, 0, data)) + return (-1); + if (hifn_readramaddr(sc, 0, data)) + return (-1); + if (bcmp(data, dataexpect, sizeof(data)) != 0) { + sc->sc_drammodel = 1; + return (0); + } + + return (0); +} + +#define HIFN_SRAM_MAX (32 << 20) +#define HIFN_SRAM_STEP_SIZE 16384 +#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) + +static int +hifn_sramsize(struct hifn_softc *sc) +{ + u_int32_t a; + u_int8_t data[8]; + u_int8_t dataexpect[sizeof(data)]; + int32_t i; + + for (i = 0; i < sizeof(data); i++) + data[i] = dataexpect[i] = i ^ 0x5a; + + for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { + a = i * HIFN_SRAM_STEP_SIZE; + bcopy(&i, data, sizeof(i)); + hifn_writeramaddr(sc, a, data); + } + + for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { + a = i * HIFN_SRAM_STEP_SIZE; + bcopy(&i, dataexpect, sizeof(i)); + if (hifn_readramaddr(sc, a, data) < 0) + return (0); + if (bcmp(data, dataexpect, sizeof(data)) != 0) + return (0); + sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; + } + + return (0); +} + +/* + * XXX For dram boards, one should really try all of the + * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG + * is already set up correctly. + */ +static int +hifn_dramsize(struct hifn_softc *sc) +{ + u_int32_t cnfg; + + if (sc->sc_flags & HIFN_IS_7956) { + /* + * 7955/7956 have a fixed internal ram of only 32K. + */ + sc->sc_ramsize = 32768; + } else { + cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & + HIFN_PUCNFG_DRAMMASK; + sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); + } + return (0); +} + +static void +hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) +{ + struct hifn_dma *dma = sc->sc_dma; + + DPRINTF("%s()\n", __FUNCTION__); + + if (dma->cmdi == HIFN_D_CMD_RSIZE) { + dma->cmdi = 0; + dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); + wmb(); + dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); + HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + } + *cmdp = dma->cmdi++; + dma->cmdk = dma->cmdi; + + if (dma->srci == HIFN_D_SRC_RSIZE) { + dma->srci = 0; + dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); + wmb(); + dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); + HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + } + *srcp = dma->srci++; + dma->srck = dma->srci; + + if (dma->dsti == HIFN_D_DST_RSIZE) { + dma->dsti = 0; + dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); + wmb(); + dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); + HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + } + *dstp = dma->dsti++; + dma->dstk = dma->dsti; + + if (dma->resi == HIFN_D_RES_RSIZE) { + dma->resi = 0; + dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); + wmb(); + dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); + HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + } + *resp = dma->resi++; + dma->resk = dma->resi; +} + +static int +hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) +{ + struct hifn_dma *dma = sc->sc_dma; + hifn_base_command_t wc; + const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; + int r, cmdi, resi, srci, dsti; + + DPRINTF("%s()\n", __FUNCTION__); + + wc.masks = htole16(3 << 13); + wc.session_num = htole16(addr >> 14); + wc.total_source_count = htole16(8); + wc.total_dest_count = htole16(addr & 0x3fff); + + hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); + + WRITE_REG_1(sc, HIFN_1_DMA_CSR, + HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | + HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); + + /* build write command */ + bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); + *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; + bcopy(data, &dma->test_src, sizeof(dma->test_src)); + + dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + + offsetof(struct hifn_dma, test_src)); + dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + + offsetof(struct hifn_dma, test_dst)); + + dma->cmdr[cmdi].l = htole32(16 | masks); + dma->srcr[srci].l = htole32(8 | masks); + dma->dstr[dsti].l = htole32(4 | masks); + dma->resr[resi].l = htole32(4 | masks); + + for (r = 10000; r >= 0; r--) { + DELAY(10); + if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) + break; + } + if (r == 0) { + device_printf(sc->sc_dev, "writeramaddr -- " + "result[%d](addr %d) still valid\n", resi, addr); + r = -1; + return (-1); + } else + r = 0; + + WRITE_REG_1(sc, HIFN_1_DMA_CSR, + HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | + HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); + + return (r); +} + +static int +hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) +{ + struct hifn_dma *dma = sc->sc_dma; + hifn_base_command_t rc; + const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; + int r, cmdi, srci, dsti, resi; + + DPRINTF("%s()\n", __FUNCTION__); + + rc.masks = htole16(2 << 13); + rc.session_num = htole16(addr >> 14); + rc.total_source_count = htole16(addr & 0x3fff); + rc.total_dest_count = htole16(8); + + hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); + + WRITE_REG_1(sc, HIFN_1_DMA_CSR, + HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | + HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); + + bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); + *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; + + dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + + offsetof(struct hifn_dma, test_src)); + dma->test_src = 0; + dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + + offsetof(struct hifn_dma, test_dst)); + dma->test_dst = 0; + dma->cmdr[cmdi].l = htole32(8 | masks); + dma->srcr[srci].l = htole32(8 | masks); + dma->dstr[dsti].l = htole32(8 | masks); + dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); + + for (r = 10000; r >= 0; r--) { + DELAY(10); + if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) + break; + } + if (r == 0) { + device_printf(sc->sc_dev, "readramaddr -- " + "result[%d](addr %d) still valid\n", resi, addr); + r = -1; + } else { + r = 0; + bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); + } + + WRITE_REG_1(sc, HIFN_1_DMA_CSR, + HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | + HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); + + return (r); +} + +/* + * Initialize the descriptor rings. + */ +static void +hifn_init_dma(struct hifn_softc *sc) +{ + struct hifn_dma *dma = sc->sc_dma; + int i; + + DPRINTF("%s()\n", __FUNCTION__); + + hifn_set_retry(sc); + + /* initialize static pointer values */ + for (i = 0; i < HIFN_D_CMD_RSIZE; i++) + dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + + offsetof(struct hifn_dma, command_bufs[i][0])); + for (i = 0; i < HIFN_D_RES_RSIZE; i++) + dma->resr[i].p = htole32(sc->sc_dma_physaddr + + offsetof(struct hifn_dma, result_bufs[i][0])); + + dma->cmdr[HIFN_D_CMD_RSIZE].p = + htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); + dma->srcr[HIFN_D_SRC_RSIZE].p = + htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); + dma->dstr[HIFN_D_DST_RSIZE].p = + htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); + dma->resr[HIFN_D_RES_RSIZE].p = + htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); + + dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; + dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; + dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; +} + +/* + * Writes out the raw command buffer space. Returns the + * command buffer size. + */ +static u_int +hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) +{ + struct hifn_softc *sc = NULL; + u_int8_t *buf_pos; + hifn_base_command_t *base_cmd; + hifn_mac_command_t *mac_cmd; + hifn_crypt_command_t *cry_cmd; + int using_mac, using_crypt, len, ivlen; + u_int32_t dlen, slen; + + DPRINTF("%s()\n", __FUNCTION__); + + buf_pos = buf; + using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; + using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; + + base_cmd = (hifn_base_command_t *)buf_pos; + base_cmd->masks = htole16(cmd->base_masks); + slen = cmd->src_mapsize; + if (cmd->sloplen) + dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); + else + dlen = cmd->dst_mapsize; + base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); + base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); + dlen >>= 16; + slen >>= 16; + base_cmd->session_num = htole16( + ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | + ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); + buf_pos += sizeof(hifn_base_command_t); + + if (using_mac) { + mac_cmd = (hifn_mac_command_t *)buf_pos; + dlen = cmd->maccrd->crd_len; + mac_cmd->source_count = htole16(dlen & 0xffff); + dlen >>= 16; + mac_cmd->masks = htole16(cmd->mac_masks | + ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); + mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); + mac_cmd->reserved = 0; + buf_pos += sizeof(hifn_mac_command_t); + } + + if (using_crypt) { + cry_cmd = (hifn_crypt_command_t *)buf_pos; + dlen = cmd->enccrd->crd_len; + cry_cmd->source_count = htole16(dlen & 0xffff); + dlen >>= 16; + cry_cmd->masks = htole16(cmd->cry_masks | + ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); + cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); + cry_cmd->reserved = 0; + buf_pos += sizeof(hifn_crypt_command_t); + } + + if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { + bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); + buf_pos += HIFN_MAC_KEY_LENGTH; + } + + if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { + switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { + case HIFN_CRYPT_CMD_ALG_3DES: + bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); + buf_pos += HIFN_3DES_KEY_LENGTH; + break; + case HIFN_CRYPT_CMD_ALG_DES: + bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); + buf_pos += HIFN_DES_KEY_LENGTH; + break; + case HIFN_CRYPT_CMD_ALG_RC4: + len = 256; + do { + int clen; + + clen = MIN(cmd->cklen, len); + bcopy(cmd->ck, buf_pos, clen); + len -= clen; + buf_pos += clen; + } while (len > 0); + bzero(buf_pos, 4); + buf_pos += 4; + break; + case HIFN_CRYPT_CMD_ALG_AES: + /* + * AES keys are variable 128, 192 and + * 256 bits (16, 24 and 32 bytes). + */ + bcopy(cmd->ck, buf_pos, cmd->cklen); + buf_pos += cmd->cklen; + break; + } + } + + if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { + switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { + case HIFN_CRYPT_CMD_ALG_AES: + ivlen = HIFN_AES_IV_LENGTH; + break; + default: + ivlen = HIFN_IV_LENGTH; + break; + } + bcopy(cmd->iv, buf_pos, ivlen); + buf_pos += ivlen; + } + + if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { + bzero(buf_pos, 8); + buf_pos += 8; + } + + return (buf_pos - buf); +} + +static int +hifn_dmamap_aligned(struct hifn_operand *op) +{ + struct hifn_softc *sc = NULL; + int i; + + DPRINTF("%s()\n", __FUNCTION__); + + for (i = 0; i < op->nsegs; i++) { + if (op->segs[i].ds_addr & 3) + return (0); + if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) + return (0); + } + return (1); +} + +static __inline int +hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) +{ + struct hifn_dma *dma = sc->sc_dma; + + if (++idx == HIFN_D_DST_RSIZE) { + dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | + HIFN_D_MASKDONEIRQ); + HIFN_DSTR_SYNC(sc, idx, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + idx = 0; + } + return (idx); +} + +static int +hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) +{ + struct hifn_dma *dma = sc->sc_dma; + struct hifn_operand *dst = &cmd->dst; + u_int32_t p, l; + int idx, used = 0, i; + + DPRINTF("%s()\n", __FUNCTION__); + + idx = dma->dsti; + for (i = 0; i < dst->nsegs - 1; i++) { + dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); + dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); + wmb(); + dma->dstr[idx].l |= htole32(HIFN_D_VALID); + HIFN_DSTR_SYNC(sc, idx, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + used++; + + idx = hifn_dmamap_dstwrap(sc, idx); + } + + if (cmd->sloplen == 0) { + p = dst->segs[i].ds_addr; + l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | + dst->segs[i].ds_len; + } else { + p = sc->sc_dma_physaddr + + offsetof(struct hifn_dma, slop[cmd->slopidx]); + l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | + sizeof(u_int32_t); + + if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { + dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); + dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | + (dst->segs[i].ds_len - cmd->sloplen)); + wmb(); + dma->dstr[idx].l |= htole32(HIFN_D_VALID); + HIFN_DSTR_SYNC(sc, idx, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + used++; + + idx = hifn_dmamap_dstwrap(sc, idx); + } + } + dma->dstr[idx].p = htole32(p); + dma->dstr[idx].l = htole32(l); + wmb(); + dma->dstr[idx].l |= htole32(HIFN_D_VALID); + HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + used++; + + idx = hifn_dmamap_dstwrap(sc, idx); + + dma->dsti = idx; + dma->dstu += used; + return (idx); +} + +static __inline int +hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) +{ + struct hifn_dma *dma = sc->sc_dma; + + if (++idx == HIFN_D_SRC_RSIZE) { + dma->srcr[idx].l = htole32(HIFN_D_VALID | + HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); + HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + idx = 0; + } + return (idx); +} + +static int +hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) +{ + struct hifn_dma *dma = sc->sc_dma; + struct hifn_operand *src = &cmd->src; + int idx, i; + u_int32_t last = 0; + + DPRINTF("%s()\n", __FUNCTION__); + + idx = dma->srci; + for (i = 0; i < src->nsegs; i++) { + if (i == src->nsegs - 1) + last = HIFN_D_LAST; + + dma->srcr[idx].p = htole32(src->segs[i].ds_addr); + dma->srcr[idx].l = htole32(src->segs[i].ds_len | + HIFN_D_MASKDONEIRQ | last); + wmb(); + dma->srcr[idx].l |= htole32(HIFN_D_VALID); + HIFN_SRCR_SYNC(sc, idx, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + + idx = hifn_dmamap_srcwrap(sc, idx); + } + dma->srci = idx; + dma->srcu += src->nsegs; + return (idx); +} + + +static int +hifn_crypto( + struct hifn_softc *sc, + struct hifn_command *cmd, + struct cryptop *crp, + int hint) +{ + struct hifn_dma *dma = sc->sc_dma; + u_int32_t cmdlen, csr; + int cmdi, resi, err = 0; + unsigned long l_flags; + + DPRINTF("%s()\n", __FUNCTION__); + + /* + * need 1 cmd, and 1 res + * + * NB: check this first since it's easy. + */ + HIFN_LOCK(sc); + if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || + (dma->resu + 1) > HIFN_D_RES_RSIZE) { +#ifdef HIFN_DEBUG + if (hifn_debug) { + device_printf(sc->sc_dev, + "cmd/result exhaustion, cmdu %u resu %u\n", + dma->cmdu, dma->resu); + } +#endif + hifnstats.hst_nomem_cr++; + sc->sc_needwakeup |= CRYPTO_SYMQ; + HIFN_UNLOCK(sc); + return (ERESTART); + } + + if (crp->crp_flags & CRYPTO_F_SKBUF) { + if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { + hifnstats.hst_nomem_load++; + err = ENOMEM; + goto err_srcmap1; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { + hifnstats.hst_nomem_load++; + err = ENOMEM; + goto err_srcmap1; + } + } else { + if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { + hifnstats.hst_nomem_load++; + err = ENOMEM; + goto err_srcmap1; + } + } + + if (hifn_dmamap_aligned(&cmd->src)) { + cmd->sloplen = cmd->src_mapsize & 3; + cmd->dst = cmd->src; + } else { + if (crp->crp_flags & CRYPTO_F_IOV) { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + err = EINVAL; + goto err_srcmap; + } else if (crp->crp_flags & CRYPTO_F_SKBUF) { +#ifdef NOTYET + int totlen, len; + struct mbuf *m, *m0, *mlast; + + KASSERT(cmd->dst_m == cmd->src_m, + ("hifn_crypto: dst_m initialized improperly")); + hifnstats.hst_unaligned++; + /* + * Source is not aligned on a longword boundary. + * Copy the data to insure alignment. If we fail + * to allocate mbufs or clusters while doing this + * we return ERESTART so the operation is requeued + * at the crypto later, but only if there are + * ops already posted to the hardware; otherwise we + * have no guarantee that we'll be re-entered. + */ + totlen = cmd->src_mapsize; + if (cmd->src_m->m_flags & M_PKTHDR) { + len = MHLEN; + MGETHDR(m0, M_DONTWAIT, MT_DATA); + if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { + m_free(m0); + m0 = NULL; + } + } else { + len = MLEN; + MGET(m0, M_DONTWAIT, MT_DATA); + } + if (m0 == NULL) { + hifnstats.hst_nomem_mbuf++; + err = dma->cmdu ? ERESTART : ENOMEM; + goto err_srcmap; + } + if (totlen >= MINCLSIZE) { + MCLGET(m0, M_DONTWAIT); + if ((m0->m_flags & M_EXT) == 0) { + hifnstats.hst_nomem_mcl++; + err = dma->cmdu ? ERESTART : ENOMEM; + m_freem(m0); + goto err_srcmap; + } + len = MCLBYTES; + } + totlen -= len; + m0->m_pkthdr.len = m0->m_len = len; + mlast = m0; + + while (totlen > 0) { + MGET(m, M_DONTWAIT, MT_DATA); + if (m == NULL) { + hifnstats.hst_nomem_mbuf++; + err = dma->cmdu ? ERESTART : ENOMEM; + m_freem(m0); + goto err_srcmap; + } + len = MLEN; + if (totlen >= MINCLSIZE) { + MCLGET(m, M_DONTWAIT); + if ((m->m_flags & M_EXT) == 0) { + hifnstats.hst_nomem_mcl++; + err = dma->cmdu ? ERESTART : ENOMEM; + mlast->m_next = m; + m_freem(m0); + goto err_srcmap; + } + len = MCLBYTES; + } + + m->m_len = len; + m0->m_pkthdr.len += len; + totlen -= len; + + mlast->m_next = m; + mlast = m; + } + cmd->dst_m = m0; +#else + device_printf(sc->sc_dev, + "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", + __FILE__, __LINE__); + err = EINVAL; + goto err_srcmap; +#endif + } else { + device_printf(sc->sc_dev, + "%s,%d: unaligned contig buffers not implemented\n", + __FILE__, __LINE__); + err = EINVAL; + goto err_srcmap; + } + } + + if (cmd->dst_map == NULL) { + if (crp->crp_flags & CRYPTO_F_SKBUF) { + if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { + hifnstats.hst_nomem_map++; + err = ENOMEM; + goto err_dstmap1; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { + hifnstats.hst_nomem_load++; + err = ENOMEM; + goto err_dstmap1; + } + } else { + if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { + hifnstats.hst_nomem_load++; + err = ENOMEM; + goto err_dstmap1; + } + } + } + +#ifdef HIFN_DEBUG + if (hifn_debug) { + device_printf(sc->sc_dev, + "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", + READ_REG_1(sc, HIFN_1_DMA_CSR), + READ_REG_1(sc, HIFN_1_DMA_IER), + dma->cmdu, dma->srcu, dma->dstu, dma->resu, + cmd->src_nsegs, cmd->dst_nsegs); + } +#endif + +#if 0 + if (cmd->src_map == cmd->dst_map) { + bus_dmamap_sync(sc->sc_dmat, cmd->src_map, + BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); + } else { + bus_dmamap_sync(sc->sc_dmat, cmd->src_map, + BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, + BUS_DMASYNC_PREREAD); + } +#endif + + /* + * need N src, and N dst + */ + if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || + (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { +#ifdef HIFN_DEBUG + if (hifn_debug) { + device_printf(sc->sc_dev, + "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", + dma->srcu, cmd->src_nsegs, + dma->dstu, cmd->dst_nsegs); + } +#endif + hifnstats.hst_nomem_sd++; + err = ERESTART; + goto err_dstmap; + } + + if (dma->cmdi == HIFN_D_CMD_RSIZE) { + dma->cmdi = 0; + dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); + wmb(); + dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); + HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + } + cmdi = dma->cmdi++; + cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); + HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); + + /* .p for command/result already set */ + dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | + HIFN_D_MASKDONEIRQ); + wmb(); + dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); + HIFN_CMDR_SYNC(sc, cmdi, + BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); + dma->cmdu++; + + /* + * We don't worry about missing an interrupt (which a "command wait" + * interrupt salvages us from), unless there is more than one command + * in the queue. + */ + if (dma->cmdu > 1) { + sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; + WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); + } + + hifnstats.hst_ipackets++; + hifnstats.hst_ibytes += cmd->src_mapsize; + + hifn_dmamap_load_src(sc, cmd); + + /* + * Unlike other descriptors, we don't mask done interrupt from + * result descriptor. + */ +#ifdef HIFN_DEBUG + if (hifn_debug) + device_printf(sc->sc_dev, "load res\n"); +#endif + if (dma->resi == HIFN_D_RES_RSIZE) { + dma->resi = 0; + dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); + wmb(); + dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); + HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + resi = dma->resi++; + KASSERT(dma->hifn_commands[resi] == NULL, + ("hifn_crypto: command slot %u busy", resi)); + dma->hifn_commands[resi] = cmd; + HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); + if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { + dma->resr[resi].l = htole32(HIFN_MAX_RESULT | + HIFN_D_LAST | HIFN_D_MASKDONEIRQ); + wmb(); + dma->resr[resi].l |= htole32(HIFN_D_VALID); + sc->sc_curbatch++; + if (sc->sc_curbatch > hifnstats.hst_maxbatch) + hifnstats.hst_maxbatch = sc->sc_curbatch; + hifnstats.hst_totbatch++; + } else { + dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); + wmb(); + dma->resr[resi].l |= htole32(HIFN_D_VALID); + sc->sc_curbatch = 0; + } + HIFN_RESR_SYNC(sc, resi, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + dma->resu++; + + if (cmd->sloplen) + cmd->slopidx = resi; + + hifn_dmamap_load_dst(sc, cmd); + + csr = 0; + if (sc->sc_c_busy == 0) { + csr |= HIFN_DMACSR_C_CTRL_ENA; + sc->sc_c_busy = 1; + } + if (sc->sc_s_busy == 0) { + csr |= HIFN_DMACSR_S_CTRL_ENA; + sc->sc_s_busy = 1; + } + if (sc->sc_r_busy == 0) { + csr |= HIFN_DMACSR_R_CTRL_ENA; + sc->sc_r_busy = 1; + } + if (sc->sc_d_busy == 0) { + csr |= HIFN_DMACSR_D_CTRL_ENA; + sc->sc_d_busy = 1; + } + if (csr) + WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); + +#ifdef HIFN_DEBUG + if (hifn_debug) { + device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", + READ_REG_1(sc, HIFN_1_DMA_CSR), + READ_REG_1(sc, HIFN_1_DMA_IER)); + } +#endif + + sc->sc_active = 5; + HIFN_UNLOCK(sc); + KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); + return (err); /* success */ + +err_dstmap: + if (cmd->src_map != cmd->dst_map) + pci_unmap_buf(sc, &cmd->dst); +err_dstmap1: +err_srcmap: + if (crp->crp_flags & CRYPTO_F_SKBUF) { + if (cmd->src_skb != cmd->dst_skb) +#ifdef NOTYET + m_freem(cmd->dst_m); +#else + device_printf(sc->sc_dev, + "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", + __FILE__, __LINE__); +#endif + } + pci_unmap_buf(sc, &cmd->src); +err_srcmap1: + HIFN_UNLOCK(sc); + return (err); +} + +static void +hifn_tick(unsigned long arg) +{ + struct hifn_softc *sc; + unsigned long l_flags; + + if (arg >= HIFN_MAX_CHIPS) + return; + sc = hifn_chip_idx[arg]; + if (!sc) + return; + + HIFN_LOCK(sc); + if (sc->sc_active == 0) { + struct hifn_dma *dma = sc->sc_dma; + u_int32_t r = 0; + + if (dma->cmdu == 0 && sc->sc_c_busy) { + sc->sc_c_busy = 0; + r |= HIFN_DMACSR_C_CTRL_DIS; + } + if (dma->srcu == 0 && sc->sc_s_busy) { + sc->sc_s_busy = 0; + r |= HIFN_DMACSR_S_CTRL_DIS; + } + if (dma->dstu == 0 && sc->sc_d_busy) { + sc->sc_d_busy = 0; + r |= HIFN_DMACSR_D_CTRL_DIS; + } + if (dma->resu == 0 && sc->sc_r_busy) { + sc->sc_r_busy = 0; + r |= HIFN_DMACSR_R_CTRL_DIS; + } + if (r) + WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); + } else + sc->sc_active--; + HIFN_UNLOCK(sc); + mod_timer(&sc->sc_tickto, jiffies + HZ); +} + +static irqreturn_t +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) +hifn_intr(int irq, void *arg) +#else +hifn_intr(int irq, void *arg, struct pt_regs *regs) +#endif +{ + struct hifn_softc *sc = arg; + struct hifn_dma *dma; + u_int32_t dmacsr, restart; + int i, u; + unsigned long l_flags; + + dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); + + /* Nothing in the DMA unit interrupted */ + if ((dmacsr & sc->sc_dmaier) == 0) + return IRQ_NONE; + + HIFN_LOCK(sc); + + dma = sc->sc_dma; + +#ifdef HIFN_DEBUG + if (hifn_debug) { + device_printf(sc->sc_dev, + "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", + dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, + dma->cmdi, dma->srci, dma->dsti, dma->resi, + dma->cmdk, dma->srck, dma->dstk, dma->resk, + dma->cmdu, dma->srcu, dma->dstu, dma->resu); + } +#endif + + WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); + + if ((sc->sc_flags & HIFN_HAS_PUBLIC) && + (dmacsr & HIFN_DMACSR_PUBDONE)) + WRITE_REG_1(sc, HIFN_1_PUB_STATUS, + READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); + + restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); + if (restart) + device_printf(sc->sc_dev, "overrun %x\n", dmacsr); + + if (sc->sc_flags & HIFN_IS_7811) { + if (dmacsr & HIFN_DMACSR_ILLR) + device_printf(sc->sc_dev, "illegal read\n"); + if (dmacsr & HIFN_DMACSR_ILLW) + device_printf(sc->sc_dev, "illegal write\n"); + } + + restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | + HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); + if (restart) { + device_printf(sc->sc_dev, "abort, resetting.\n"); + hifnstats.hst_abort++; + hifn_abort(sc); + HIFN_UNLOCK(sc); + return IRQ_HANDLED; + } + + if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { + /* + * If no slots to process and we receive a "waiting on + * command" interrupt, we disable the "waiting on command" + * (by clearing it). + */ + sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; + WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); + } + + /* clear the rings */ + i = dma->resk; u = dma->resu; + while (u != 0) { + HIFN_RESR_SYNC(sc, i, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + if (dma->resr[i].l & htole32(HIFN_D_VALID)) { + HIFN_RESR_SYNC(sc, i, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + break; + } + + if (i != HIFN_D_RES_RSIZE) { + struct hifn_command *cmd; + u_int8_t *macbuf = NULL; + + HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); + cmd = dma->hifn_commands[i]; + KASSERT(cmd != NULL, + ("hifn_intr: null command slot %u", i)); + dma->hifn_commands[i] = NULL; + + if (cmd->base_masks & HIFN_BASE_CMD_MAC) { + macbuf = dma->result_bufs[i]; + macbuf += 12; + } + + hifn_callback(sc, cmd, macbuf); + hifnstats.hst_opackets++; + u--; + } + + if (++i == (HIFN_D_RES_RSIZE + 1)) + i = 0; + } + dma->resk = i; dma->resu = u; + + i = dma->srck; u = dma->srcu; + while (u != 0) { + if (i == HIFN_D_SRC_RSIZE) + i = 0; + HIFN_SRCR_SYNC(sc, i, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { + HIFN_SRCR_SYNC(sc, i, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + break; + } + i++, u--; + } + dma->srck = i; dma->srcu = u; + + i = dma->cmdk; u = dma->cmdu; + while (u != 0) { + HIFN_CMDR_SYNC(sc, i, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { + HIFN_CMDR_SYNC(sc, i, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + break; + } + if (i != HIFN_D_CMD_RSIZE) { + u--; + HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); + } + if (++i == (HIFN_D_CMD_RSIZE + 1)) + i = 0; + } + dma->cmdk = i; dma->cmdu = u; + + HIFN_UNLOCK(sc); + + if (sc->sc_needwakeup) { /* XXX check high watermark */ + int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); +#ifdef HIFN_DEBUG + if (hifn_debug) + device_printf(sc->sc_dev, + "wakeup crypto (%x) u %d/%d/%d/%d\n", + sc->sc_needwakeup, + dma->cmdu, dma->srcu, dma->dstu, dma->resu); +#endif + sc->sc_needwakeup &= ~wakeup; + crypto_unblock(sc->sc_cid, wakeup); + } + + return IRQ_HANDLED; +} + +/* + * Allocate a new 'session' and return an encoded session id. 'sidp' + * contains our registration id, and should contain an encoded session + * id on successful allocation. + */ +static int +hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) +{ + struct hifn_softc *sc = device_get_softc(dev); + struct cryptoini *c; + int mac = 0, cry = 0, sesn; + struct hifn_session *ses = NULL; + unsigned long l_flags; + + DPRINTF("%s()\n", __FUNCTION__); + + KASSERT(sc != NULL, ("hifn_newsession: null softc")); + if (sidp == NULL || cri == NULL || sc == NULL) { + DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); + return (EINVAL); + } + + HIFN_LOCK(sc); + if (sc->sc_sessions == NULL) { + ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), + SLAB_ATOMIC); + if (ses == NULL) { + HIFN_UNLOCK(sc); + return (ENOMEM); + } + sesn = 0; + sc->sc_nsessions = 1; + } else { + for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { + if (!sc->sc_sessions[sesn].hs_used) { + ses = &sc->sc_sessions[sesn]; + break; + } + } + + if (ses == NULL) { + sesn = sc->sc_nsessions; + ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), + SLAB_ATOMIC); + if (ses == NULL) { + HIFN_UNLOCK(sc); + return (ENOMEM); + } + bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); + bzero(sc->sc_sessions, sesn * sizeof(*ses)); + kfree(sc->sc_sessions); + sc->sc_sessions = ses; + ses = &sc->sc_sessions[sesn]; + sc->sc_nsessions++; + } + } + HIFN_UNLOCK(sc); + + bzero(ses, sizeof(*ses)); + ses->hs_used = 1; + + for (c = cri; c != NULL; c = c->cri_next) { + switch (c->cri_alg) { + case CRYPTO_MD5: + case CRYPTO_SHA1: + case CRYPTO_MD5_HMAC: + case CRYPTO_SHA1_HMAC: + if (mac) { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + return (EINVAL); + } + mac = 1; + ses->hs_mlen = c->cri_mlen; + if (ses->hs_mlen == 0) { + switch (c->cri_alg) { + case CRYPTO_MD5: + case CRYPTO_MD5_HMAC: + ses->hs_mlen = 16; + break; + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + ses->hs_mlen = 20; + break; + } + } + break; + case CRYPTO_DES_CBC: + case CRYPTO_3DES_CBC: + case CRYPTO_AES_CBC: + case CRYPTO_ARC4: + if (cry) { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + return (EINVAL); + } + cry = 1; + break; + default: + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + return (EINVAL); + } + } + if (mac == 0 && cry == 0) { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + return (EINVAL); + } + + *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); + + return (0); +} + +/* + * Deallocate a session. + * XXX this routine should run a zero'd mac/encrypt key into context ram. + * XXX to blow away any keys already stored there. + */ +static int +hifn_freesession(device_t dev, u_int64_t tid) +{ + struct hifn_softc *sc = device_get_softc(dev); + int session, error; + u_int32_t sid = CRYPTO_SESID2LID(tid); + unsigned long l_flags; + + DPRINTF("%s()\n", __FUNCTION__); + + KASSERT(sc != NULL, ("hifn_freesession: null softc")); + if (sc == NULL) { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + return (EINVAL); + } + + HIFN_LOCK(sc); + session = HIFN_SESSION(sid); + if (session < sc->sc_nsessions) { + bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); + error = 0; + } else { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + error = EINVAL; + } + HIFN_UNLOCK(sc); + + return (error); +} + +static int +hifn_process(device_t dev, struct cryptop *crp, int hint) +{ + struct hifn_softc *sc = device_get_softc(dev); + struct hifn_command *cmd = NULL; + int session, err, ivlen; + struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; + + DPRINTF("%s()\n", __FUNCTION__); + + if (crp == NULL || crp->crp_callback == NULL) { + hifnstats.hst_invalid++; + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + return (EINVAL); + } + session = HIFN_SESSION(crp->crp_sid); + + if (sc == NULL || session >= sc->sc_nsessions) { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + err = EINVAL; + goto errout; + } + + cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); + if (cmd == NULL) { + hifnstats.hst_nomem++; + err = ENOMEM; + goto errout; + } + memset(cmd, 0, sizeof(*cmd)); + + if (crp->crp_flags & CRYPTO_F_SKBUF) { + cmd->src_skb = (struct sk_buff *)crp->crp_buf; + cmd->dst_skb = (struct sk_buff *)crp->crp_buf; + } else if (crp->crp_flags & CRYPTO_F_IOV) { + cmd->src_io = (struct uio *)crp->crp_buf; + cmd->dst_io = (struct uio *)crp->crp_buf; + } else { + cmd->src_buf = crp->crp_buf; + cmd->dst_buf = crp->crp_buf; + } + + crd1 = crp->crp_desc; + if (crd1 == NULL) { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + err = EINVAL; + goto errout; + } + crd2 = crd1->crd_next; + + if (crd2 == NULL) { + if (crd1->crd_alg == CRYPTO_MD5_HMAC || + crd1->crd_alg == CRYPTO_SHA1_HMAC || + crd1->crd_alg == CRYPTO_SHA1 || + crd1->crd_alg == CRYPTO_MD5) { + maccrd = crd1; + enccrd = NULL; + } else if (crd1->crd_alg == CRYPTO_DES_CBC || + crd1->crd_alg == CRYPTO_3DES_CBC || + crd1->crd_alg == CRYPTO_AES_CBC || + crd1->crd_alg == CRYPTO_ARC4) { + if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) + cmd->base_masks |= HIFN_BASE_CMD_DECODE; + maccrd = NULL; + enccrd = crd1; + } else { + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + err = EINVAL; + goto errout; + } + } else { + if ((crd1->crd_alg == CRYPTO_MD5_HMAC || + crd1->crd_alg == CRYPTO_SHA1_HMAC || + crd1->crd_alg == CRYPTO_MD5 || + crd1->crd_alg == CRYPTO_SHA1) && + (crd2->crd_alg == CRYPTO_DES_CBC || + crd2->crd_alg == CRYPTO_3DES_CBC || + crd2->crd_alg == CRYPTO_AES_CBC || + crd2->crd_alg == CRYPTO_ARC4) && + ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { + cmd->base_masks = HIFN_BASE_CMD_DECODE; + maccrd = crd1; + enccrd = crd2; + } else if ((crd1->crd_alg == CRYPTO_DES_CBC || + crd1->crd_alg == CRYPTO_ARC4 || + crd1->crd_alg == CRYPTO_3DES_CBC || + crd1->crd_alg == CRYPTO_AES_CBC) && + (crd2->crd_alg == CRYPTO_MD5_HMAC || + crd2->crd_alg == CRYPTO_SHA1_HMAC || + crd2->crd_alg == CRYPTO_MD5 || + crd2->crd_alg == CRYPTO_SHA1) && + (crd1->crd_flags & CRD_F_ENCRYPT)) { + enccrd = crd1; + maccrd = crd2; + } else { + /* + * We cannot order the 7751 as requested + */ + DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); + err = EINVAL; + goto errout; + } + } + + if (enccrd) { + cmd->enccrd = enccrd; + cmd->base_masks |= HIFN_BASE_CMD_CRYPT; + switch (enccrd->crd_alg) { + case CRYPTO_ARC4: + cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; + break; + case CRYPTO_DES_CBC: + cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | + HIFN_CRYPT_CMD_MODE_CBC | + HIFN_CRYPT_CMD_NEW_IV; + break; + case CRYPTO_3DES_CBC: + cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | + HIFN_CRYPT_CMD_MODE_CBC | + HIFN_CRYPT_CMD_NEW_IV; + break; + case CRYPTO_AES_CBC: + cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | + HIFN_CRYPT_CMD_MODE_CBC | + HIFN_CRYPT_CMD_NEW_IV; + break; + default: + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + err = EINVAL; + goto errout; + } + if (enccrd->crd_alg != CRYPTO_ARC4) { + ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? + HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); + if (enccrd->crd_flags & CRD_F_ENCRYPT) { + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) + bcopy(enccrd->crd_iv, cmd->iv, ivlen); + else + read_random(cmd->iv, ivlen); + + if ((enccrd->crd_flags & CRD_F_IV_PRESENT) + == 0) { + crypto_copyback(crp->crp_flags, + crp->crp_buf, enccrd->crd_inject, + ivlen, cmd->iv); + } + } else { + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) + bcopy(enccrd->crd_iv, cmd->iv, ivlen); + else { + crypto_copydata(crp->crp_flags, + crp->crp_buf, enccrd->crd_inject, + ivlen, cmd->iv); + } + } + } + + if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) + cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; + cmd->ck = enccrd->crd_key; + cmd->cklen = enccrd->crd_klen >> 3; + cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; + + /* + * Need to specify the size for the AES key in the masks. + */ + if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == + HIFN_CRYPT_CMD_ALG_AES) { + switch (cmd->cklen) { + case 16: + cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; + break; + case 24: + cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; + break; + case 32: + cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; + break; + default: + DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); + err = EINVAL; + goto errout; + } + } + } + + if (maccrd) { + cmd->maccrd = maccrd; + cmd->base_masks |= HIFN_BASE_CMD_MAC; + + switch (maccrd->crd_alg) { + case CRYPTO_MD5: + cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | + HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | + HIFN_MAC_CMD_POS_IPSEC; + break; + case CRYPTO_MD5_HMAC: + cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | + HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | + HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; + break; + case CRYPTO_SHA1: + cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | + HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | + HIFN_MAC_CMD_POS_IPSEC; + break; + case CRYPTO_SHA1_HMAC: + cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | + HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | + HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; + break; + } + + if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || + maccrd->crd_alg == CRYPTO_MD5_HMAC) { + cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; + bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); + bzero(cmd->mac + (maccrd->crd_klen >> 3), + HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); + } + } + + cmd->crp = crp; + cmd->session_num = session; + cmd->softc = sc; + + err = hifn_crypto(sc, cmd, crp, hint); + if (!err) { + return 0; + } else if (err == ERESTART) { + /* + * There weren't enough resources to dispatch the request + * to the part. Notify the caller so they'll requeue this + * request and resubmit it again soon. + */ +#ifdef HIFN_DEBUG + if (hifn_debug) + device_printf(sc->sc_dev, "requeue request\n"); +#endif + kfree(cmd); + sc->sc_needwakeup |= CRYPTO_SYMQ; + return (err); + } + +errout: + if (cmd != NULL) + kfree(cmd); + if (err == EINVAL) + hifnstats.hst_invalid++; + else + hifnstats.hst_nomem++; + crp->crp_etype = err; + crypto_done(crp); + return (err); +} + +static void +hifn_abort(struct hifn_softc *sc) +{ + struct hifn_dma *dma = sc->sc_dma; + struct hifn_command *cmd; + struct cryptop *crp; + int i, u; + + DPRINTF("%s()\n", __FUNCTION__); + + i = dma->resk; u = dma->resu; + while (u != 0) { + cmd = dma->hifn_commands[i]; + KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); + dma->hifn_commands[i] = NULL; + crp = cmd->crp; + + if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { + /* Salvage what we can. */ + u_int8_t *macbuf; + + if (cmd->base_masks & HIFN_BASE_CMD_MAC) { + macbuf = dma->result_bufs[i]; + macbuf += 12; + } else + macbuf = NULL; + hifnstats.hst_opackets++; + hifn_callback(sc, cmd, macbuf); + } else { +#if 0 + if (cmd->src_map == cmd->dst_map) { + bus_dmamap_sync(sc->sc_dmat, cmd->src_map, + BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); + } else { + bus_dmamap_sync(sc->sc_dmat, cmd->src_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, + BUS_DMASYNC_POSTREAD); + } +#endif + + if (cmd->src_skb != cmd->dst_skb) { +#ifdef NOTYET + m_freem(cmd->src_m); + crp->crp_buf = (caddr_t)cmd->dst_m; +#else + device_printf(sc->sc_dev, + "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", + __FILE__, __LINE__); +#endif + } + + /* non-shared buffers cannot be restarted */ + if (cmd->src_map != cmd->dst_map) { + /* + * XXX should be EAGAIN, delayed until + * after the reset. + */ + crp->crp_etype = ENOMEM; + pci_unmap_buf(sc, &cmd->dst); + } else + crp->crp_etype = ENOMEM; + + pci_unmap_buf(sc, &cmd->src); + + kfree(cmd); + if (crp->crp_etype != EAGAIN) + crypto_done(crp); + } + + if (++i == HIFN_D_RES_RSIZE) + i = 0; + u--; + } + dma->resk = i; dma->resu = u; + + hifn_reset_board(sc, 1); + hifn_init_dma(sc); + hifn_init_pci_registers(sc); +} + +static void +hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) +{ + struct hifn_dma *dma = sc->sc_dma; + struct cryptop *crp = cmd->crp; + struct cryptodesc *crd; + int i, u; + + DPRINTF("%s()\n", __FUNCTION__); + +#if 0 + if (cmd->src_map == cmd->dst_map) { + bus_dmamap_sync(sc->sc_dmat, cmd->src_map, + BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); + } else { + bus_dmamap_sync(sc->sc_dmat, cmd->src_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, + BUS_DMASYNC_POSTREAD); + } +#endif + + if (crp->crp_flags & CRYPTO_F_SKBUF) { + if (cmd->src_skb != cmd->dst_skb) { +#ifdef NOTYET + crp->crp_buf = (caddr_t)cmd->dst_m; + totlen = cmd->src_mapsize; + for (m = cmd->dst_m; m != NULL; m = m->m_next) { + if (totlen < m->m_len) { + m->m_len = totlen; + totlen = 0; + } else + totlen -= m->m_len; + } + cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; + m_freem(cmd->src_m); +#else + device_printf(sc->sc_dev, + "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", + __FILE__, __LINE__); +#endif + } + } + + if (cmd->sloplen != 0) { + crypto_copyback(crp->crp_flags, crp->crp_buf, + cmd->src_mapsize - cmd->sloplen, cmd->sloplen, + (caddr_t)&dma->slop[cmd->slopidx]); + } + + i = dma->dstk; u = dma->dstu; + while (u != 0) { + if (i == HIFN_D_DST_RSIZE) + i = 0; +#if 0 + bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); +#endif + if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { +#if 0 + bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +#endif + break; + } + i++, u--; + } + dma->dstk = i; dma->dstu = u; + + hifnstats.hst_obytes += cmd->dst_mapsize; + + if (macbuf != NULL) { + for (crd = crp->crp_desc; crd; crd = crd->crd_next) { + int len; + + if (crd->crd_alg != CRYPTO_MD5 && + crd->crd_alg != CRYPTO_SHA1 && + crd->crd_alg != CRYPTO_MD5_HMAC && + crd->crd_alg != CRYPTO_SHA1_HMAC) { + continue; + } + len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; + crypto_copyback(crp->crp_flags, crp->crp_buf, + crd->crd_inject, len, macbuf); + break; + } + } + + if (cmd->src_map != cmd->dst_map) + pci_unmap_buf(sc, &cmd->dst); + pci_unmap_buf(sc, &cmd->src); + kfree(cmd); + crypto_done(crp); +} + +/* + * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 + * and Group 1 registers; avoid conditions that could create + * burst writes by doing a read in between the writes. + * + * NB: The read we interpose is always to the same register; + * we do this because reading from an arbitrary (e.g. last) + * register may not always work. + */ +static void +hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) +{ + if (sc->sc_flags & HIFN_IS_7811) { + if (sc->sc_bar0_lastreg == reg - 4) + readl(sc->sc_bar0 + HIFN_0_PUCNFG); + sc->sc_bar0_lastreg = reg; + } + writel(val, sc->sc_bar0 + reg); +} + +static void +hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) +{ + if (sc->sc_flags & HIFN_IS_7811) { + if (sc->sc_bar1_lastreg == reg - 4) + readl(sc->sc_bar1 + HIFN_1_REVID); + sc->sc_bar1_lastreg = reg; + } + writel(val, sc->sc_bar1 + reg); +} + + +static struct pci_device_id hifn_pci_tbl[] = { + { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + /* + * Other vendors share this PCI ID as well, such as + * http://www.powercrypt.com, and obviously they also + * use the same key. + */ + { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { 0, 0, 0, 0, 0, 0, } +}; +MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); + +static struct pci_driver hifn_driver = { + .name = "hifn", + .id_table = hifn_pci_tbl, + .probe = hifn_probe, + .remove = hifn_remove, + /* add PM stuff here one day */ +}; + +static int __init hifn_init (void) +{ + struct hifn_softc *sc = NULL; + int rc; + + DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); + + rc = pci_register_driver(&hifn_driver); + pci_register_driver_compat(&hifn_driver, rc); + + return rc; +} + +static void __exit hifn_exit (void) +{ + pci_unregister_driver(&hifn_driver); +} + +module_init(hifn_init); +module_exit(hifn_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); diff --git a/target/linux/generic/files/crypto/ocf/hifn/hifn7751reg.h b/target/linux/generic/files/crypto/ocf/hifn/hifn7751reg.h new file mode 100644 index 0000000..ccf54f9 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/hifn/hifn7751reg.h @@ -0,0 +1,540 @@ +/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ +/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ + +/*- + * Invertex AEON / Hifn 7751 driver + * Copyright (c) 1999 Invertex Inc. All rights reserved. + * Copyright (c) 1999 Theo de Raadt + * Copyright (c) 2000-2001 Network Security Technologies, Inc. + * http://www.netsec.net + * + * Please send any comments, feedback, bug-fixes, or feature requests to + * software@invertex.com. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ +#ifndef __HIFN_H__ +#define __HIFN_H__ + +/* + * Some PCI configuration space offset defines. The names were made + * identical to the names used by the Linux kernel. + */ +#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ +#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ +#define HIFN_TRDY_TIMEOUT 0x40 +#define HIFN_RETRY_TIMEOUT 0x41 + +/* + * PCI vendor and device identifiers + * (the names are preserved from their OpenBSD source). + */ +#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ +#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ +#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ +#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ +#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ +#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ +#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ +#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ + +#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ +#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ + +#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ +#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ + +/* + * The values below should multiple of 4 -- and be large enough to handle + * any command the driver implements. + * + * MAX_COMMAND = base command + mac command + encrypt command + + * mac-key + rc4-key + * MAX_RESULT = base result + mac result + mac + encrypt result + * + * + */ +#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) +#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) + +/* + * hifn_desc_t + * + * Holds an individual descriptor for any of the rings. + */ +typedef struct hifn_desc { + volatile u_int32_t l; /* length and status bits */ + volatile u_int32_t p; +} hifn_desc_t; + +/* + * Masks for the "length" field of struct hifn_desc. + */ +#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ +#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ +#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ +#define HIFN_D_OVER 0x08000000 /* overflow */ +#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ +#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ +#define HIFN_D_VALID 0x80000000 /* valid bit */ + + +/* + * Processing Unit Registers (offset from BASEREG0) + */ +#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ +#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ +#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ +#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ +#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ +#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ +#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ +#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ +#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ +#define HIFN_0_MUTE1 0x80 +#define HIFN_0_MUTE2 0x90 +#define HIFN_0_SPACESIZE 0x100 /* Register space size */ + +/* Processing Unit Control Register (HIFN_0_PUCTRL) */ +#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ +#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ +#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ +#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ +#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ + +/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ +#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ +#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ +#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ +#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ +#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ +#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ +#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ +#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ +#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ +#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ + +/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ +#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ +#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ +#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ +#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ +#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ +#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ +#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ +#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ +#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ +#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ +#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ +#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ +#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ +#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ +#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ +#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ +#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ +#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ +#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ +#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ +#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ +#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ +#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ + +/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ +#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ +#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ +#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ +#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ +#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ +#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ +#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ +#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ +#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ +#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ + +/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ +#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ +#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ +#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ +#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ +#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ +#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ +#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ +#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ +#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ +#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ +#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ +#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ +#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ +#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ +#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ +#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ +#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ + +/* FIFO Status Register (HIFN_0_FIFOSTAT) */ +#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ +#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ + +/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ +#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ + +/* + * DMA Interface Registers (offset from BASEREG1) + */ +#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ +#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ +#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ +#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ +#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ +#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ +#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ +#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ +#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ +#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ +#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ +#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ +#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ +#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ +#define HIFN_1_REVID 0x98 /* Revision ID */ + +#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ +#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ +#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ +#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ +#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ +#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ +#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ +#define HIFN_1_RNG_DATA 0x318 /* RNG data */ +#define HIFN_1_PUB_MODE 0x320 /* PK mode */ +#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ +#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ +#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ +#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ + +/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ +#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ +#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ +#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ +#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ +#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ +#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ +#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ +#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ +#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ +#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ +#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ +#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ +#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ +#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ +#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ +#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ +#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ +#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ +#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ +#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ +#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ +#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ +#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ +#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ +#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ +#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ +#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ +#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ +#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ +#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ +#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ +#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ +#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ +#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ +#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ +#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ +#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ +#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ + +/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ +#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ +#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ +#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ +#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ +#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ +#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ +#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ +#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ +#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ +#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ +#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ +#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ +#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ +#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ +#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ +#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ +#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ +#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ +#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ +#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ +#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ +#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ + +/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ +#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ +#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ +#define HIFN_DMACNFG_UNLOCK 0x00000800 +#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ +#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ +#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ +#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ +#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ + +/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ +#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ +#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ +#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ +#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ +#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 +#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 +#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 +#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 + +/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ +#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ + +/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ +#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ +#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ +#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ + +/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ +#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ +#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ + +/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ +#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ +#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ +#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ +#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ +#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ +#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ +#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ +#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ +#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ + +/* Public key reset register (HIFN_1_PUB_RESET) */ +#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ + +/* Public operation register (HIFN_1_PUB_OP) */ +#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ +#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ +#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ +#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ +#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ +#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ +#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ +#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ +#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ +#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ +#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ +#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ +#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ +#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ +#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ +#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ +#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ + +/* Public operand length register (HIFN_1_PUB_OPLEN) */ +#define HIFN_PUBOPLEN_MODLEN 0x0000007f +#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 +#define HIFN_PUBOPLEN_REDLEN 0x003c0000 + +/* Public status register (HIFN_1_PUB_STATUS) */ +#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ +#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ +#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ +#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ +#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ +#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ +#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ + +/* Public interrupt enable register (HIFN_1_PUB_IEN) */ +#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ + +/* Random number generator config register (HIFN_1_RNG_CONFIG) */ +#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ + +/* + * Register offsets in register set 1 + */ + +#define HIFN_UNLOCK_SECRET1 0xf4 +#define HIFN_UNLOCK_SECRET2 0xfc + +/* + * PLL config register + * + * This register is present only on 7954/7955/7956 parts. It must be + * programmed according to the bus interface method used by the h/w. + * Note that the parts require a stable clock. Since the PCI clock + * may vary the reference clock must usually be used. To avoid + * overclocking the core logic, setup must be done carefully, refer + * to the driver for details. The exact multiplier required varies + * by part and system configuration; refer to the Hifn documentation. + */ +#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ +#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ +/* bit 2 reserved */ +#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ +#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ +/* bits 5-9 reserved */ +#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ +#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ +#define HIFN_PLL_ND_SHIFT 11 +#define HIFN_PLL_ND_2 0x00000000 /* 2x */ +#define HIFN_PLL_ND_4 0x00000800 /* 4x */ +#define HIFN_PLL_ND_6 0x00001000 /* 6x */ +#define HIFN_PLL_ND_8 0x00001800 /* 8x */ +#define HIFN_PLL_ND_10 0x00002000 /* 10x */ +#define HIFN_PLL_ND_12 0x00002800 /* 12x */ +/* bits 14-15 reserved */ +#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ +/* bits 17-31 reserved */ + +/* + * Board configuration specifies only these bits. + */ +#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) + +/* + * Public Key Engine Mode Register + */ +#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ +#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ + + +/********************************************************************* + * Structs for board commands + * + *********************************************************************/ + +/* + * Structure to help build up the command data structure. + */ +typedef struct hifn_base_command { + volatile u_int16_t masks; + volatile u_int16_t session_num; + volatile u_int16_t total_source_count; + volatile u_int16_t total_dest_count; +} hifn_base_command_t; + +#define HIFN_BASE_CMD_MAC 0x0400 +#define HIFN_BASE_CMD_CRYPT 0x0800 +#define HIFN_BASE_CMD_DECODE 0x2000 +#define HIFN_BASE_CMD_SRCLEN_M 0xc000 +#define HIFN_BASE_CMD_SRCLEN_S 14 +#define HIFN_BASE_CMD_DSTLEN_M 0x3000 +#define HIFN_BASE_CMD_DSTLEN_S 12 +#define HIFN_BASE_CMD_LENMASK_HI 0x30000 +#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff + +/* + * Structure to help build up the command data structure. + */ +typedef struct hifn_crypt_command { + volatile u_int16_t masks; + volatile u_int16_t header_skip; + volatile u_int16_t source_count; + volatile u_int16_t reserved; +} hifn_crypt_command_t; + +#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ +#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ +#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ +#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ +#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ +#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ +#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ +#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ +#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ +#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ +#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ +#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ +#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ + +#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 +#define HIFN_CRYPT_CMD_SRCLEN_S 14 + +#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ +#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ +#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ +#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ + +/* + * Structure to help build up the command data structure. + */ +typedef struct hifn_mac_command { + volatile u_int16_t masks; + volatile u_int16_t header_skip; + volatile u_int16_t source_count; + volatile u_int16_t reserved; +} hifn_mac_command_t; + +#define HIFN_MAC_CMD_ALG_MASK 0x0001 +#define HIFN_MAC_CMD_ALG_SHA1 0x0000 +#define HIFN_MAC_CMD_ALG_MD5 0x0001 +#define HIFN_MAC_CMD_MODE_MASK 0x000c +#define HIFN_MAC_CMD_MODE_HMAC 0x0000 +#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 +#define HIFN_MAC_CMD_MODE_HASH 0x0008 +#define HIFN_MAC_CMD_MODE_FULL 0x0004 +#define HIFN_MAC_CMD_TRUNC 0x0010 +#define HIFN_MAC_CMD_RESULT 0x0020 +#define HIFN_MAC_CMD_APPEND 0x0040 +#define HIFN_MAC_CMD_SRCLEN_M 0xc000 +#define HIFN_MAC_CMD_SRCLEN_S 14 + +/* + * MAC POS IPsec initiates authentication after encryption on encodes + * and before decryption on decodes. + */ +#define HIFN_MAC_CMD_POS_IPSEC 0x0200 +#define HIFN_MAC_CMD_NEW_KEY 0x0800 + +/* + * The poll frequency and poll scalar defines are unshifted values used + * to set fields in the DMA Configuration Register. + */ +#ifndef HIFN_POLL_FREQUENCY +#define HIFN_POLL_FREQUENCY 0x1 +#endif + +#ifndef HIFN_POLL_SCALAR +#define HIFN_POLL_SCALAR 0x0 +#endif + +#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ +#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ +#endif /* __HIFN_H__ */ diff --git a/target/linux/generic/files/crypto/ocf/hifn/hifn7751var.h b/target/linux/generic/files/crypto/ocf/hifn/hifn7751var.h new file mode 100644 index 0000000..c5d30f9 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/hifn/hifn7751var.h @@ -0,0 +1,368 @@ +/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ +/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ + +/*- + * Invertex AEON / Hifn 7751 driver + * Copyright (c) 1999 Invertex Inc. All rights reserved. + * Copyright (c) 1999 Theo de Raadt + * Copyright (c) 2000-2001 Network Security Technologies, Inc. + * http://www.netsec.net + * + * Please send any comments, feedback, bug-fixes, or feature requests to + * software@invertex.com. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ + +#ifndef __HIFN7751VAR_H__ +#define __HIFN7751VAR_H__ + +#ifdef __KERNEL__ + +/* + * Some configurable values for the driver. By default command+result + * descriptor rings are the same size. The src+dst descriptor rings + * are sized at 3.5x the number of potential commands. Slower parts + * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) + * src+cmd/result descriptors. It's not clear that increasing the size + * of the descriptor rings helps performance significantly as other + * factors tend to come into play (e.g. copying misaligned packets). + */ +#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ +#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ +#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ +#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ + +/* + * Length values for cryptography + */ +#define HIFN_DES_KEY_LENGTH 8 +#define HIFN_3DES_KEY_LENGTH 24 +#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH +#define HIFN_IV_LENGTH 8 +#define HIFN_AES_IV_LENGTH 16 +#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH + +/* + * Length values for authentication + */ +#define HIFN_MAC_KEY_LENGTH 64 +#define HIFN_MD5_LENGTH 16 +#define HIFN_SHA1_LENGTH 20 +#define HIFN_MAC_TRUNC_LENGTH 12 + +#define MAX_SCATTER 64 + +/* + * Data structure to hold all 4 rings and any other ring related data. + */ +struct hifn_dma { + /* + * Descriptor rings. We add +1 to the size to accomidate the + * jump descriptor. + */ + struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; + struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; + struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; + struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; + + struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; + + u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; + u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; + u_int32_t slop[HIFN_D_CMD_RSIZE]; + + u_int64_t test_src, test_dst; + + /* + * Our current positions for insertion and removal from the desriptor + * rings. + */ + int cmdi, srci, dsti, resi; + volatile int cmdu, srcu, dstu, resu; + int cmdk, srck, dstk, resk; +}; + +struct hifn_session { + int hs_used; + int hs_mlen; +}; + +#define HIFN_RING_SYNC(sc, r, i, f) \ + /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ + +#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) +#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) +#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) +#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) + +#define HIFN_CMD_SYNC(sc, i, f) \ + /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ + +#define HIFN_RES_SYNC(sc, i, f) \ + /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ + +typedef int bus_size_t; + +/* + * Holds data specific to a single HIFN board. + */ +struct hifn_softc { + softc_device_decl sc_dev; + + struct pci_dev *sc_pcidev; /* PCI device pointer */ + spinlock_t sc_mtx; /* per-instance lock */ + + int sc_num; /* for multiple devs */ + + ocf_iomem_t sc_bar0; + bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ + ocf_iomem_t sc_bar1; + bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ + + int sc_irq; + + u_int32_t sc_dmaier; + u_int32_t sc_drammodel; /* 1=dram, 0=sram */ + u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ + + struct hifn_dma *sc_dma; + dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ + + int sc_dmansegs; + int32_t sc_cid; + int sc_maxses; + int sc_nsessions; + struct hifn_session *sc_sessions; + int sc_ramsize; + int sc_flags; +#define HIFN_HAS_RNG 0x1 /* includes random number generator */ +#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ +#define HIFN_HAS_AES 0x4 /* includes AES support */ +#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ +#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ + + struct timer_list sc_tickto; /* for managing DMA */ + + int sc_rngfirst; + int sc_rnghz; /* RNG polling frequency */ + + int sc_c_busy; /* command ring busy */ + int sc_s_busy; /* source data ring busy */ + int sc_d_busy; /* destination data ring busy */ + int sc_r_busy; /* result ring busy */ + int sc_active; /* for initial countdown */ + int sc_needwakeup; /* ops q'd wating on resources */ + int sc_curbatch; /* # ops submitted w/o int */ + int sc_suspended; +#ifdef HIFN_VULCANDEV + struct cdev *sc_pkdev; +#endif +}; + +#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) +#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) + +/* + * hifn_command_t + * + * This is the control structure used to pass commands to hifn_encrypt(). + * + * flags + * ----- + * Flags is the bitwise "or" values for command configuration. A single + * encrypt direction needs to be set: + * + * HIFN_ENCODE or HIFN_DECODE + * + * To use cryptography, a single crypto algorithm must be included: + * + * HIFN_CRYPT_3DES or HIFN_CRYPT_DES + * + * To use authentication is used, a single MAC algorithm must be included: + * + * HIFN_MAC_MD5 or HIFN_MAC_SHA1 + * + * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. + * If the value below is set, hash values are truncated or assumed + * truncated to 12 bytes: + * + * HIFN_MAC_TRUNC + * + * Keys for encryption and authentication can be sent as part of a command, + * or the last key value used with a particular session can be retrieved + * and used again if either of these flags are not specified. + * + * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY + * + * session_num + * ----------- + * A number between 0 and 2048 (for DRAM models) or a number between + * 0 and 768 (for SRAM models). Those who don't want to use session + * numbers should leave value at zero and send a new crypt key and/or + * new MAC key on every command. If you use session numbers and + * don't send a key with a command, the last key sent for that same + * session number will be used. + * + * Warning: Using session numbers and multiboard at the same time + * is currently broken. + * + * mbuf + * ---- + * Either fill in the mbuf pointer and npa=0 or + * fill packp[] and packl[] and set npa to > 0 + * + * mac_header_skip + * --------------- + * The number of bytes of the source_buf that are skipped over before + * authentication begins. This must be a number between 0 and 2^16-1 + * and can be used by IPsec implementers to skip over IP headers. + * *** Value ignored if authentication not used *** + * + * crypt_header_skip + * ----------------- + * The number of bytes of the source_buf that are skipped over before + * the cryptographic operation begins. This must be a number between 0 + * and 2^16-1. For IPsec, this number will always be 8 bytes larger + * than the auth_header_skip (to skip over the ESP header). + * *** Value ignored if cryptography not used *** + * + */ +struct hifn_operand { + union { + struct sk_buff *skb; + struct uio *io; + unsigned char *buf; + } u; + void *map; + bus_size_t mapsize; + int nsegs; + struct { + dma_addr_t ds_addr; + int ds_len; + } segs[MAX_SCATTER]; +}; + +struct hifn_command { + u_int16_t session_num; + u_int16_t base_masks, cry_masks, mac_masks; + u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; + int cklen; + int sloplen, slopidx; + + struct hifn_operand src; + struct hifn_operand dst; + + struct hifn_softc *softc; + struct cryptop *crp; + struct cryptodesc *enccrd, *maccrd; +}; + +#define src_skb src.u.skb +#define src_io src.u.io +#define src_map src.map +#define src_mapsize src.mapsize +#define src_segs src.segs +#define src_nsegs src.nsegs +#define src_buf src.u.buf + +#define dst_skb dst.u.skb +#define dst_io dst.u.io +#define dst_map dst.map +#define dst_mapsize dst.mapsize +#define dst_segs dst.segs +#define dst_nsegs dst.nsegs +#define dst_buf dst.u.buf + +/* + * Return values for hifn_crypto() + */ +#define HIFN_CRYPTO_SUCCESS 0 +#define HIFN_CRYPTO_BAD_INPUT (-1) +#define HIFN_CRYPTO_RINGS_FULL (-2) + +/************************************************************************** + * + * Function: hifn_crypto + * + * Purpose: Called by external drivers to begin an encryption on the + * HIFN board. + * + * Blocking/Non-blocking Issues + * ============================ + * The driver cannot block in hifn_crypto (no calls to tsleep) currently. + * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough + * room in any of the rings for the request to proceed. + * + * Return Values + * ============= + * 0 for success, negative values on error + * + * Defines for negative error codes are: + * + * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. + * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking + * behaviour was requested. + * + *************************************************************************/ + +/* + * Convert back and forth from 'sid' to 'card' and 'session' + */ +#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) +#define HIFN_SESSION(sid) ((sid) & 0x000007ff) +#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) + +#endif /* _KERNEL */ + +struct hifn_stats { + u_int64_t hst_ibytes; + u_int64_t hst_obytes; + u_int32_t hst_ipackets; + u_int32_t hst_opackets; + u_int32_t hst_invalid; + u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ + u_int32_t hst_abort; + u_int32_t hst_noirq; /* IRQ for no reason */ + u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ + u_int32_t hst_maxbatch; /* max ops submitted together */ + u_int32_t hst_unaligned; /* unaligned src caused copy */ + /* + * The following divides hst_nomem into more specific buckets. + */ + u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ + u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ + u_int32_t hst_nomem_mbuf; /* MGET* failed */ + u_int32_t hst_nomem_mcl; /* MCLGET* failed */ + u_int32_t hst_nomem_cr; /* out of command/result descriptor */ + u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ +}; + +#endif /* __HIFN7751VAR_H__ */ diff --git a/target/linux/generic/files/crypto/ocf/hifn/hifnHIPP.c b/target/linux/generic/files/crypto/ocf/hifn/hifnHIPP.c new file mode 100644 index 0000000..56b8a5c --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/hifn/hifnHIPP.c @@ -0,0 +1,421 @@ +/*- + * Driver for Hifn HIPP-I/II chipset + * Copyright (c) 2006 Michael Richardson + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored by Hifn Inc. + * + */ + +/* + * Driver for various Hifn encryption processors. + */ +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "hifnHIPPreg.h" +#include "hifnHIPPvar.h" + +#if 1 +#define DPRINTF(a...) if (hipp_debug) { \ + printk("%s: ", sc ? \ + device_get_nameunit(sc->sc_dev) : "hifn"); \ + printk(a); \ + } else +#else +#define DPRINTF(a...) +#endif + +typedef int bus_size_t; + +static inline int +pci_get_revid(struct pci_dev *dev) +{ + u8 rid = 0; + pci_read_config_byte(dev, PCI_REVISION_ID, &rid); + return rid; +} + +#define debug hipp_debug +int hipp_debug = 0; +module_param(hipp_debug, int, 0644); +MODULE_PARM_DESC(hipp_debug, "Enable debug"); + +int hipp_maxbatch = 1; +module_param(hipp_maxbatch, int, 0644); +MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); + +static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); +static void hipp_remove(struct pci_dev *dev); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) +static irqreturn_t hipp_intr(int irq, void *arg); +#else +static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); +#endif + +static int hipp_num_chips = 0; +static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; + +static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); +static int hipp_freesession(device_t, u_int64_t); +static int hipp_process(device_t, struct cryptop *, int); + +static device_method_t hipp_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, hipp_newsession), + DEVMETHOD(cryptodev_freesession,hipp_freesession), + DEVMETHOD(cryptodev_process, hipp_process), +}; + +static __inline u_int32_t +READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) +{ + u_int32_t v = readl(sc->sc_bar[barno] + reg); + //sc->sc_bar0_lastreg = (bus_size_t) -1; + return (v); +} +static __inline void +WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) +{ + writel(val, sc->sc_bar[barno] + reg); +} + +#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) +#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) +#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) +#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) + +static int +hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) +{ + return EINVAL; +} + +static int +hipp_freesession(device_t dev, u_int64_t tid) +{ + return EINVAL; +} + +static int +hipp_process(device_t dev, struct cryptop *crp, int hint) +{ + return EINVAL; +} + +static const char* +hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) +{ + char *n = NULL; + + switch (pci_get_vendor(sc->sc_pcidev)) { + case PCI_VENDOR_HIFN: + switch (pci_get_device(sc->sc_pcidev)) { + case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; + case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; + case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; + } + } + + if(n==NULL) { + snprintf(buf, blen, "VID=%02x,PID=%02x", + pci_get_vendor(sc->sc_pcidev), + pci_get_device(sc->sc_pcidev)); + } else { + buf[0]='\0'; + strncat(buf, n, blen); + } + return buf; +} + +struct hipp_fs_entry { + struct attribute attr; + /* other stuff */ +}; + + +static ssize_t +cryptoid_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct hipp_softc *sc; + + sc = pci_get_drvdata(to_pci_dev (dev)); + return sprintf (buf, "%d\n", sc->sc_cid); +} + +struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); + +/* + * Attach an interface that successfully probed. + */ +static int +hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) +{ + struct hipp_softc *sc = NULL; + int i; + //char rbase; + //u_int16_t ena; + int rev; + //int rseg; + int rc; + + DPRINTF("%s()\n", __FUNCTION__); + + if (pci_enable_device(dev) < 0) + return(-ENODEV); + + if (pci_set_mwi(dev)) + return(-ENODEV); + + if (!dev->irq) { + printk("hifn: found device with no IRQ assigned. check BIOS settings!"); + pci_disable_device(dev); + return(-ENODEV); + } + + sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); + if (!sc) + return(-ENOMEM); + memset(sc, 0, sizeof(*sc)); + + softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); + + sc->sc_pcidev = dev; + sc->sc_irq = -1; + sc->sc_cid = -1; + sc->sc_num = hipp_num_chips++; + + if (sc->sc_num < HIPP_MAX_CHIPS) + hipp_chip_idx[sc->sc_num] = sc; + + pci_set_drvdata(sc->sc_pcidev, sc); + + spin_lock_init(&sc->sc_mtx); + + /* + * Setup PCI resources. + * The READ_REG_0, WRITE_REG_0, READ_REG_1, + * and WRITE_REG_1 macros throughout the driver are used + * to permit better debugging. + */ + for(i=0; i<4; i++) { + unsigned long mem_start, mem_len; + mem_start = pci_resource_start(sc->sc_pcidev, i); + mem_len = pci_resource_len(sc->sc_pcidev, i); + sc->sc_barphy[i] = (caddr_t)mem_start; + sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); + if (!sc->sc_bar[i]) { + device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); + goto fail; + } + } + + //hipp_reset_board(sc, 0); + pci_set_master(sc->sc_pcidev); + + /* + * Arrange the interrupt line. + */ + rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); + if (rc) { + device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); + goto fail; + } + sc->sc_irq = dev->irq; + + rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; + + { + char b[32]; + device_printf(sc->sc_dev, "%s, rev %u", + hipp_partname(sc, b, sizeof(b)), rev); + } + +#if 0 + if (sc->sc_flags & HIFN_IS_7956) + printf(", pll=0x%x<%s clk, %ux mult>", + sc->sc_pllconfig, + sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", + 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); +#endif + printf("\n"); + + sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); + if (sc->sc_cid < 0) { + device_printf(sc->sc_dev, "could not get crypto driver id\n"); + goto fail; + } + +#if 0 /* cannot work with a non-GPL module */ + /* make a sysfs entry to let the world know what entry we got */ + sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); +#endif + +#if 0 + init_timer(&sc->sc_tickto); + sc->sc_tickto.function = hifn_tick; + sc->sc_tickto.data = (unsigned long) sc->sc_num; + mod_timer(&sc->sc_tickto, jiffies + HZ); +#endif + +#if 0 /* no code here yet ?? */ + crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); +#endif + + return (0); + +fail: + if (sc->sc_cid >= 0) + crypto_unregister_all(sc->sc_cid); + if (sc->sc_irq != -1) + free_irq(sc->sc_irq, sc); + +#if 0 + if (sc->sc_dma) { + /* Turn off DMA polling */ + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | + HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); + + pci_free_consistent(sc->sc_pcidev, + sizeof(*sc->sc_dma), + sc->sc_dma, sc->sc_dma_physaddr); + } +#endif + kfree(sc); + return (-ENXIO); +} + +/* + * Detach an interface that successfully probed. + */ +static void +hipp_remove(struct pci_dev *dev) +{ + struct hipp_softc *sc = pci_get_drvdata(dev); + unsigned long l_flags; + + DPRINTF("%s()\n", __FUNCTION__); + + /* disable interrupts */ + HIPP_LOCK(sc); + +#if 0 + WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); + HIFN_UNLOCK(sc); + + /*XXX other resources */ + del_timer_sync(&sc->sc_tickto); + + /* Turn off DMA polling */ + WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | + HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); +#endif + + crypto_unregister_all(sc->sc_cid); + + free_irq(sc->sc_irq, sc); + +#if 0 + pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), + sc->sc_dma, sc->sc_dma_physaddr); +#endif +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) +static irqreturn_t hipp_intr(int irq, void *arg) +#else +static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) +#endif +{ + struct hipp_softc *sc = arg; + + sc = sc; /* shut up compiler */ + + return IRQ_HANDLED; +} + +static struct pci_device_id hipp_pci_tbl[] = { + { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { 0 }, /* terminating entry */ +}; +MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); + +static struct pci_driver hipp_driver = { + .name = "hipp", + .id_table = hipp_pci_tbl, + .probe = hipp_probe, + .remove = hipp_remove, + /* add PM stuff here one day */ +}; + +static int __init hipp_init (void) +{ + struct hipp_softc *sc = NULL; + int rc; + + DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); + + rc = pci_register_driver(&hipp_driver); + pci_register_driver_compat(&hipp_driver, rc); + + return rc; +} + +static void __exit hipp_exit (void) +{ + pci_unregister_driver(&hipp_driver); +} + +module_init(hipp_init); +module_exit(hipp_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("Michael Richardson "); +MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); diff --git a/target/linux/generic/files/crypto/ocf/hifn/hifnHIPPreg.h b/target/linux/generic/files/crypto/ocf/hifn/hifnHIPPreg.h new file mode 100644 index 0000000..8c0e720 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/hifn/hifnHIPPreg.h @@ -0,0 +1,46 @@ +/*- + * Hifn HIPP-I/HIPP-II (7855/8155) driver. + * Copyright (c) 2006 Michael Richardson + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored by Hifn inc. + * + */ + +#ifndef __HIFNHIPP_H__ +#define __HIFNHIPP_H__ + +/* + * PCI vendor and device identifiers + */ +#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ +#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ +#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ +#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ + +#define HIPP_1_REVID 0x01 /* BOGUS */ + +#endif /* __HIPP_H__ */ diff --git a/target/linux/generic/files/crypto/ocf/hifn/hifnHIPPvar.h b/target/linux/generic/files/crypto/ocf/hifn/hifnHIPPvar.h new file mode 100644 index 0000000..61d292f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/hifn/hifnHIPPvar.h @@ -0,0 +1,93 @@ +/* + * Hifn HIPP-I/HIPP-II (7855/8155) driver. + * Copyright (c) 2006 Michael Richardson * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored by Hifn inc. + * + */ + +#ifndef __HIFNHIPPVAR_H__ +#define __HIFNHIPPVAR_H__ + +#define HIPP_MAX_CHIPS 8 + +/* + * Holds data specific to a single Hifn HIPP-I board. + */ +struct hipp_softc { + softc_device_decl sc_dev; + + struct pci_dev *sc_pcidev; /* device backpointer */ + ocf_iomem_t sc_bar[5]; + caddr_t sc_barphy[5]; /* physical address */ + int sc_num; /* for multiple devs */ + spinlock_t sc_mtx; /* per-instance lock */ + int32_t sc_cid; + int sc_irq; + +#if 0 + + u_int32_t sc_dmaier; + u_int32_t sc_drammodel; /* 1=dram, 0=sram */ + u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ + + struct hifn_dma *sc_dma; + dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ + + int sc_dmansegs; + int sc_maxses; + int sc_nsessions; + struct hifn_session *sc_sessions; + int sc_ramsize; + int sc_flags; +#define HIFN_HAS_RNG 0x1 /* includes random number generator */ +#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ +#define HIFN_HAS_AES 0x4 /* includes AES support */ +#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ +#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ + + struct timer_list sc_tickto; /* for managing DMA */ + + int sc_rngfirst; + int sc_rnghz; /* RNG polling frequency */ + + int sc_c_busy; /* command ring busy */ + int sc_s_busy; /* source data ring busy */ + int sc_d_busy; /* destination data ring busy */ + int sc_r_busy; /* result ring busy */ + int sc_active; /* for initial countdown */ + int sc_needwakeup; /* ops q'd wating on resources */ + int sc_curbatch; /* # ops submitted w/o int */ + int sc_suspended; + struct miscdevice sc_miscdev; +#endif +}; + +#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) +#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) + +#endif /* __HIFNHIPPVAR_H__ */ diff --git a/target/linux/generic/files/crypto/ocf/ixp4xx/Makefile b/target/linux/generic/files/crypto/ocf/ixp4xx/Makefile new file mode 100644 index 0000000..d94a3b7 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ixp4xx/Makefile @@ -0,0 +1,104 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +# +# You will need to point this at your Intel ixp425 includes, this portion +# of the Makefile only really works under SGLinux with the appropriate libs +# installed. They can be downloaded from http://www.snapgear.org/ +# +ifeq ($(CONFIG_CPU_IXP46X),y) +IXPLATFORM = ixp46X +else +ifeq ($(CONFIG_CPU_IXP43X),y) +IXPLATFORM = ixp43X +else +IXPLATFORM = ixp42X +endif +endif + +ifdef CONFIG_IXP400_LIB_2_4 +IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw +OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal +endif +ifdef CONFIG_IXP400_LIB_2_1 +IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw +OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal +endif +ifdef CONFIG_IXP400_LIB_2_0 +IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw +OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal +endif +ifdef IX_XSCALE_SW +ifdef CONFIG_IXP400_LIB_2_4 +IXP_CFLAGS = \ + -I$(ROOTDIR)/. \ + -I$(IX_XSCALE_SW)/src/include \ + -I$(OSAL_DIR)/common/include/ \ + -I$(OSAL_DIR)/common/include/modules/ \ + -I$(OSAL_DIR)/common/include/modules/ddk/ \ + -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ + -I$(OSAL_DIR)/common/include/modules/ioMem/ \ + -I$(OSAL_DIR)/common/os/linux/include/ \ + -I$(OSAL_DIR)/common/os/linux/include/core/ \ + -I$(OSAL_DIR)/common/os/linux/include/modules/ \ + -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ + -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ + -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ + -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ + -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ + -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ + -DUSE_IXP4XX_CRYPTO +else +IXP_CFLAGS = \ + -I$(ROOTDIR)/. \ + -I$(IX_XSCALE_SW)/src/include \ + -I$(OSAL_DIR)/ \ + -I$(OSAL_DIR)/os/linux/include/ \ + -I$(OSAL_DIR)/os/linux/include/modules/ \ + -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ + -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ + -I$(OSAL_DIR)/os/linux/include/core/ \ + -I$(OSAL_DIR)/os/linux/include/platforms/ \ + -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ + -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ + -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ + -I$(OSAL_DIR)/os/linux/include/core/ \ + -I$(OSAL_DIR)/include/ \ + -I$(OSAL_DIR)/include/modules/ \ + -I$(OSAL_DIR)/include/modules/bufferMgt/ \ + -I$(OSAL_DIR)/include/modules/ioMem/ \ + -I$(OSAL_DIR)/include/platforms/ \ + -I$(OSAL_DIR)/include/platforms/ixp400/ \ + -DUSE_IXP4XX_CRYPTO +endif +endif +ifdef CONFIG_IXP400_LIB_1_4 +IXP_CFLAGS = \ + -I$(ROOTDIR)/. \ + -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ + -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ + -DUSE_IXP4XX_CRYPTO +endif +ifndef IXPDIR +IXPDIR = ixp-version-is-not-supported +endif + +ifeq ($(CONFIG_CPU_IXP46X),y) +IXP_CFLAGS += -D__ixp46X +else +ifeq ($(CONFIG_CPU_IXP43X),y) +IXP_CFLAGS += -D__ixp43X +else +IXP_CFLAGS += -D__ixp42X +endif +endif + +obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o + +obj ?= . +EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/ixp4xx/ixp4xx.c b/target/linux/generic/files/crypto/ocf/ixp4xx/ixp4xx.c new file mode 100644 index 0000000..ede598f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ixp4xx/ixp4xx.c @@ -0,0 +1,1339 @@ +/* + * An OCF module that uses Intels IXP CryptACC API to do the crypto. + * This driver requires the IXP400 Access Library that is available + * from Intel in order to operate (or compile). + * + * Written by David McCullough + * Copyright (C) 2006-2011 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * ALTERNATIVELY, provided that this notice is retained in full, this product + * may be distributed under the terms of the GNU General Public License (GPL), + * in which case the provisions of the GPL apply INSTEAD OF those given above. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifndef IX_MBUF_PRIV +#define IX_MBUF_PRIV(x) ((x)->priv) +#endif + +struct ixp_data; + +struct ixp_q { + struct list_head ixp_q_list; + struct ixp_data *ixp_q_data; + struct cryptop *ixp_q_crp; + struct cryptodesc *ixp_q_ccrd; + struct cryptodesc *ixp_q_acrd; + IX_MBUF ixp_q_mbuf; + UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ + UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ + unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; + unsigned char *ixp_q_iv; +}; + +struct ixp_data { + int ixp_registered; /* is the context registered */ + int ixp_crd_flags; /* detect direction changes */ + + int ixp_cipher_alg; + int ixp_auth_alg; + + UINT32 ixp_ctx_id; + UINT32 ixp_hash_key_id; /* used when hashing */ + IxCryptoAccCtx ixp_ctx; + IX_MBUF ixp_pri_mbuf; + IX_MBUF ixp_sec_mbuf; + + struct work_struct ixp_pending_work; + struct work_struct ixp_registration_work; + struct list_head ixp_q; /* unprocessed requests */ +}; + +#ifdef __ixp46X + +#define MAX_IOP_SIZE 64 /* words */ +#define MAX_OOP_SIZE 128 + +#define MAX_PARAMS 3 + +struct ixp_pkq { + struct list_head pkq_list; + struct cryptkop *pkq_krp; + + IxCryptoAccPkeEauInOperands pkq_op; + IxCryptoAccPkeEauOpResult pkq_result; + + UINT32 pkq_ibuf0[MAX_IOP_SIZE]; + UINT32 pkq_ibuf1[MAX_IOP_SIZE]; + UINT32 pkq_ibuf2[MAX_IOP_SIZE]; + UINT32 pkq_obuf[MAX_OOP_SIZE]; +}; + +static LIST_HEAD(ixp_pkq); /* current PK wait list */ +static struct ixp_pkq *ixp_pk_cur; +static spinlock_t ixp_pkq_lock; + +#endif /* __ixp46X */ + +static int ixp_blocked = 0; + +static int32_t ixp_id = -1; +static struct ixp_data **ixp_sessions = NULL; +static u_int32_t ixp_sesnum = 0; + +static int ixp_process(device_t, struct cryptop *, int); +static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); +static int ixp_freesession(device_t, u_int64_t); +#ifdef __ixp46X +static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) +static kmem_cache_t *qcache; +#else +static struct kmem_cache *qcache; +#endif + +#define debug ixp_debug +static int ixp_debug = 0; +module_param(ixp_debug, int, 0644); +MODULE_PARM_DESC(ixp_debug, "Enable debug"); + +static int ixp_init_crypto = 1; +module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ +MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); + +static void ixp_process_pending(void *arg); +static void ixp_registration(void *arg); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +static void ixp_process_pending_wq(struct work_struct *work); +static void ixp_registration_wq(struct work_struct *work); +#endif + +/* + * dummy device structure + */ + +static struct { + softc_device_decl sc_dev; +} ixpdev; + +static device_method_t ixp_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, ixp_newsession), + DEVMETHOD(cryptodev_freesession,ixp_freesession), + DEVMETHOD(cryptodev_process, ixp_process), +#ifdef __ixp46X + DEVMETHOD(cryptodev_kprocess, ixp_kprocess), +#endif +}; + +/* + * Generate a new software session. + */ +static int +ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) +{ + struct ixp_data *ixp; + u_int32_t i; +#define AUTH_LEN(cri, def) \ + (cri->cri_mlen ? cri->cri_mlen : (def)) + + dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); + if (sid == NULL || cri == NULL) { + dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + if (ixp_sessions) { + for (i = 1; i < ixp_sesnum; i++) + if (ixp_sessions[i] == NULL) + break; + } else + i = 1; /* NB: to silence compiler warning */ + + if (ixp_sessions == NULL || i == ixp_sesnum) { + struct ixp_data **ixpd; + + if (ixp_sessions == NULL) { + i = 1; /* We leave ixp_sessions[0] empty */ + ixp_sesnum = CRYPTO_SW_SESSIONS; + } else + ixp_sesnum *= 2; + + ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); + if (ixpd == NULL) { + /* Reset session number */ + if (ixp_sesnum == CRYPTO_SW_SESSIONS) + ixp_sesnum = 0; + else + ixp_sesnum /= 2; + dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); + return ENOBUFS; + } + memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); + + /* Copy existing sessions */ + if (ixp_sessions) { + memcpy(ixpd, ixp_sessions, + (ixp_sesnum / 2) * sizeof(struct ixp_data *)); + kfree(ixp_sessions); + } + + ixp_sessions = ixpd; + } + + ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), + SLAB_ATOMIC); + if (ixp_sessions[i] == NULL) { + ixp_freesession(NULL, i); + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return ENOBUFS; + } + + *sid = i; + + ixp = ixp_sessions[i]; + memset(ixp, 0, sizeof(*ixp)); + + ixp->ixp_cipher_alg = -1; + ixp->ixp_auth_alg = -1; + ixp->ixp_ctx_id = -1; + INIT_LIST_HEAD(&ixp->ixp_q); + + ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; + + while (cri) { + switch (cri->cri_alg) { + case CRYPTO_DES_CBC: + ixp->ixp_cipher_alg = cri->cri_alg; + ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; + ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; + ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; + ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; + ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = + IX_CRYPTO_ACC_DES_IV_64; + memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, + cri->cri_key, (cri->cri_klen + 7) / 8); + break; + + case CRYPTO_3DES_CBC: + ixp->ixp_cipher_alg = cri->cri_alg; + ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; + ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; + ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; + ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; + ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = + IX_CRYPTO_ACC_DES_IV_64; + memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, + cri->cri_key, (cri->cri_klen + 7) / 8); + break; + + case CRYPTO_RIJNDAEL128_CBC: + ixp->ixp_cipher_alg = cri->cri_alg; + ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; + ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; + ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; + ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; + ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; + memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, + cri->cri_key, (cri->cri_klen + 7) / 8); + break; + + case CRYPTO_MD5: + case CRYPTO_MD5_HMAC: + ixp->ixp_auth_alg = cri->cri_alg; + ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; + ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); + ixp->ixp_ctx.authCtx.aadLen = 0; + /* Only MD5_HMAC needs a key */ + if (cri->cri_alg == CRYPTO_MD5_HMAC) { + ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; + if (ixp->ixp_ctx.authCtx.authKeyLen > + sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { + printk( + "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", + cri->cri_klen); + ixp_freesession(NULL, i); + return EINVAL; + } + memcpy(ixp->ixp_ctx.authCtx.key.authKey, + cri->cri_key, (cri->cri_klen + 7) / 8); + } + break; + + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + ixp->ixp_auth_alg = cri->cri_alg; + ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; + ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); + ixp->ixp_ctx.authCtx.aadLen = 0; + /* Only SHA1_HMAC needs a key */ + if (cri->cri_alg == CRYPTO_SHA1_HMAC) { + ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; + if (ixp->ixp_ctx.authCtx.authKeyLen > + sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { + printk( + "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", + cri->cri_klen); + ixp_freesession(NULL, i); + return EINVAL; + } + memcpy(ixp->ixp_ctx.authCtx.key.authKey, + cri->cri_key, (cri->cri_klen + 7) / 8); + } + break; + + default: + printk("ixp: unknown algo 0x%x\n", cri->cri_alg); + ixp_freesession(NULL, i); + return EINVAL; + } + cri = cri->cri_next; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); + INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); +#else + INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); + INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); +#endif + + return 0; +} + + +/* + * Free a session. + */ +static int +ixp_freesession(device_t dev, u_int64_t tid) +{ + u_int32_t sid = CRYPTO_SESID2LID(tid); + + dprintk("%s()\n", __FUNCTION__); + if (sid > ixp_sesnum || ixp_sessions == NULL || + ixp_sessions[sid] == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + /* Silently accept and return */ + if (sid == 0) + return 0; + + if (ixp_sessions[sid]) { + if (ixp_sessions[sid]->ixp_ctx_id != -1) { + ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); + ixp_sessions[sid]->ixp_ctx_id = -1; + } + kfree(ixp_sessions[sid]); + } + ixp_sessions[sid] = NULL; + if (ixp_blocked) { + ixp_blocked = 0; + crypto_unblock(ixp_id, CRYPTO_SYMQ); + } + return 0; +} + + +/* + * callback for when hash processing is complete + */ + +static void +ixp_hash_perform_cb( + UINT32 hash_key_id, + IX_MBUF *bufp, + IxCryptoAccStatus status) +{ + struct ixp_q *q; + + dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); + + if (bufp == NULL) { + printk("ixp: NULL buf in %s\n", __FUNCTION__); + return; + } + + q = IX_MBUF_PRIV(bufp); + if (q == NULL) { + printk("ixp: NULL priv in %s\n", __FUNCTION__); + return; + } + + if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { + /* On success, need to copy hash back into original client buffer */ + memcpy(q->ixp_hash_dest, q->ixp_hash_src, + (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? + SHA1_HASH_LEN : MD5_HASH_LEN); + } + else { + printk("ixp: hash perform failed status=%d\n", status); + q->ixp_q_crp->crp_etype = EINVAL; + } + + /* Free internal buffer used for hashing */ + kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); + + crypto_done(q->ixp_q_crp); + kmem_cache_free(qcache, q); +} + +/* + * setup a request and perform it + */ +static void +ixp_q_process(struct ixp_q *q) +{ + IxCryptoAccStatus status; + struct ixp_data *ixp = q->ixp_q_data; + int auth_off = 0; + int auth_len = 0; + int crypt_off = 0; + int crypt_len = 0; + int icv_off = 0; + char *crypt_func; + + dprintk("%s(%p)\n", __FUNCTION__, q); + + if (q->ixp_q_ccrd) { + if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { + if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { + q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; + } else { + q->ixp_q_iv = q->ixp_q_iv_data; + read_random(q->ixp_q_iv, ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen); + } + if ((q->ixp_q_ccrd->crd_flags & CRD_F_IV_PRESENT) == 0) + crypto_copyback(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, + q->ixp_q_ccrd->crd_inject, + ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, + (caddr_t) q->ixp_q_iv); + } else { + if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) + q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; + else { + q->ixp_q_iv = q->ixp_q_iv_data; + crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, + q->ixp_q_ccrd->crd_inject, + ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, + (caddr_t) q->ixp_q_iv); + } + } + + if (q->ixp_q_acrd) { + auth_off = q->ixp_q_acrd->crd_skip; + auth_len = q->ixp_q_acrd->crd_len; + icv_off = q->ixp_q_acrd->crd_inject; + } + + crypt_off = q->ixp_q_ccrd->crd_skip; + crypt_len = q->ixp_q_ccrd->crd_len; + } else { /* if (q->ixp_q_acrd) */ + auth_off = q->ixp_q_acrd->crd_skip; + auth_len = q->ixp_q_acrd->crd_len; + icv_off = q->ixp_q_acrd->crd_inject; + } + + if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { + struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; + if (skb_shinfo(skb)->nr_frags) { + /* + * DAVIDM fix this limitation one day by using + * a buffer pool and chaining, it is not currently + * needed for current user/kernel space acceleration + */ + printk("ixp: Cannot handle fragmented skb's yet !\n"); + q->ixp_q_crp->crp_etype = ENOENT; + goto done; + } + IX_MBUF_MLEN(&q->ixp_q_mbuf) = + IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; + IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; + } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { + struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; + if (uiop->uio_iovcnt != 1) { + /* + * DAVIDM fix this limitation one day by using + * a buffer pool and chaining, it is not currently + * needed for current user/kernel space acceleration + */ + printk("ixp: Cannot handle more than 1 iovec yet !\n"); + q->ixp_q_crp->crp_etype = ENOENT; + goto done; + } + IX_MBUF_MLEN(&q->ixp_q_mbuf) = + IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; + IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; + } else /* contig buffer */ { + IX_MBUF_MLEN(&q->ixp_q_mbuf) = + IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; + IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; + } + + IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; + + if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { + /* + * For SHA1 and MD5 hash, need to create an internal buffer that is big + * enough to hold the original data + the appropriate padding for the + * hash algorithm. + */ + UINT8 *tbuf = NULL; + + IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = + ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; + tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); + + if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { + printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", + IX_MBUF_MLEN(&q->ixp_q_mbuf)); + q->ixp_q_crp->crp_etype = ENOMEM; + goto done; + } + memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); + + /* Set location in client buffer to copy hash into */ + q->ixp_hash_dest = + &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; + + IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; + + /* Set location in internal buffer for where hash starts */ + q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; + + crypt_func = "ixCryptoAccHashPerform"; + status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, + &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, + &ixp->ixp_hash_key_id); + } + else { + crypt_func = "ixCryptoAccAuthCryptPerform"; + status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, + NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, + q->ixp_q_iv); + } + + if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) + return; + + if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { + q->ixp_q_crp->crp_etype = ENOMEM; + goto done; + } + + printk("ixp: %s failed %u\n", crypt_func, status); + q->ixp_q_crp->crp_etype = EINVAL; + +done: + crypto_done(q->ixp_q_crp); + kmem_cache_free(qcache, q); +} + + +/* + * because we cannot process the Q from the Register callback + * we do it here on a task Q. + */ + +static void +ixp_process_pending(void *arg) +{ + struct ixp_data *ixp = arg; + struct ixp_q *q = NULL; + + dprintk("%s(%p)\n", __FUNCTION__, arg); + + if (!ixp) + return; + + while (!list_empty(&ixp->ixp_q)) { + q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); + list_del(&q->ixp_q_list); + ixp_q_process(q); + } +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +static void +ixp_process_pending_wq(struct work_struct *work) +{ + struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); + ixp_process_pending(ixp); +} +#endif + +/* + * callback for when context registration is complete + */ + +static void +ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) +{ + int i; + struct ixp_data *ixp; + struct ixp_q *q; + + dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); + + /* + * free any buffer passed in to this routine + */ + if (bufp) { + IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; + kfree(IX_MBUF_MDATA(bufp)); + IX_MBUF_MDATA(bufp) = NULL; + } + + for (i = 0; i < ixp_sesnum; i++) { + ixp = ixp_sessions[i]; + if (ixp && ixp->ixp_ctx_id == ctx_id) + break; + } + if (i >= ixp_sesnum) { + printk("ixp: invalid context id %d\n", ctx_id); + return; + } + + if (IX_CRYPTO_ACC_STATUS_WAIT == status) { + /* this is normal to free the first of two buffers */ + dprintk("ixp: register not finished yet.\n"); + return; + } + + if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { + printk("ixp: register failed 0x%x\n", status); + while (!list_empty(&ixp->ixp_q)) { + q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); + list_del(&q->ixp_q_list); + q->ixp_q_crp->crp_etype = EINVAL; + crypto_done(q->ixp_q_crp); + kmem_cache_free(qcache, q); + } + return; + } + + /* + * we are now registered, we cannot start processing the Q here + * or we get strange errors with AES (DES/3DES seem to be ok). + */ + ixp->ixp_registered = 1; + schedule_work(&ixp->ixp_pending_work); +} + + +/* + * callback for when data processing is complete + */ + +static void +ixp_perform_cb( + UINT32 ctx_id, + IX_MBUF *sbufp, + IX_MBUF *dbufp, + IxCryptoAccStatus status) +{ + struct ixp_q *q; + + dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, + dbufp, status); + + if (sbufp == NULL) { + printk("ixp: NULL sbuf in ixp_perform_cb\n"); + return; + } + + q = IX_MBUF_PRIV(sbufp); + if (q == NULL) { + printk("ixp: NULL priv in ixp_perform_cb\n"); + return; + } + + if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { + printk("ixp: perform failed status=%d\n", status); + q->ixp_q_crp->crp_etype = EINVAL; + } + + crypto_done(q->ixp_q_crp); + kmem_cache_free(qcache, q); +} + + +/* + * registration is not callable at IRQ time, so we defer + * to a task queue, this routines completes the registration for us + * when the task queue runs + * + * Unfortunately this means we cannot tell OCF that the driver is blocked, + * we do that on the next request. + */ + +static void +ixp_registration(void *arg) +{ + struct ixp_data *ixp = arg; + struct ixp_q *q = NULL; + IX_MBUF *pri = NULL, *sec = NULL; + int status = IX_CRYPTO_ACC_STATUS_SUCCESS; + + if (!ixp) { + printk("ixp: ixp_registration with no arg\n"); + return; + } + + if (ixp->ixp_ctx_id != -1) { + ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); + ixp->ixp_ctx_id = -1; + } + + if (list_empty(&ixp->ixp_q)) { + printk("ixp: ixp_registration with no Q\n"); + return; + } + + /* + * setup the primary and secondary buffers + */ + q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); + if (q->ixp_q_acrd) { + pri = &ixp->ixp_pri_mbuf; + sec = &ixp->ixp_sec_mbuf; + IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; + IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); + IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; + IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); + } + + /* Only need to register if a crypt op or HMAC op */ + if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || + ixp->ixp_auth_alg == CRYPTO_MD5)) { + status = ixCryptoAccCtxRegister( + &ixp->ixp_ctx, + pri, sec, + ixp_register_cb, + ixp_perform_cb, + &ixp->ixp_ctx_id); + } + else { + /* Otherwise we start processing pending q */ + schedule_work(&ixp->ixp_pending_work); + } + + if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) + return; + + if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { + printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); + ixp_blocked = 1; + /* perhaps we should return EGAIN on queued ops ? */ + return; + } + + printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); + ixp->ixp_ctx_id = -1; + + /* + * everything waiting is toasted + */ + while (!list_empty(&ixp->ixp_q)) { + q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); + list_del(&q->ixp_q_list); + q->ixp_q_crp->crp_etype = ENOENT; + crypto_done(q->ixp_q_crp); + kmem_cache_free(qcache, q); + } +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +static void +ixp_registration_wq(struct work_struct *work) +{ + struct ixp_data *ixp = container_of(work, struct ixp_data, + ixp_registration_work); + ixp_registration(ixp); +} +#endif + +/* + * Process a request. + */ +static int +ixp_process(device_t dev, struct cryptop *crp, int hint) +{ + struct ixp_data *ixp; + unsigned int lid; + struct ixp_q *q = NULL; + int status; + + dprintk("%s()\n", __FUNCTION__); + + /* Sanity check */ + if (crp == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + crp->crp_etype = 0; + + if (ixp_blocked) + return ERESTART; + + if (crp->crp_desc == NULL || crp->crp_buf == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + crp->crp_etype = EINVAL; + goto done; + } + + /* + * find the session we are using + */ + + lid = crp->crp_sid & 0xffffffff; + if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || + ixp_sessions[lid] == NULL) { + crp->crp_etype = ENOENT; + dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); + goto done; + } + ixp = ixp_sessions[lid]; + + /* + * setup a new request ready for queuing + */ + q = kmem_cache_alloc(qcache, SLAB_ATOMIC); + if (q == NULL) { + dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); + crp->crp_etype = ENOMEM; + goto done; + } + /* + * save some cycles by only zeroing the important bits + */ + memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); + q->ixp_q_ccrd = NULL; + q->ixp_q_acrd = NULL; + q->ixp_q_crp = crp; + q->ixp_q_data = ixp; + + /* + * point the cipher and auth descriptors appropriately + * check that we have something to do + */ + if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) + q->ixp_q_ccrd = crp->crp_desc; + else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) + q->ixp_q_acrd = crp->crp_desc; + else { + crp->crp_etype = ENOENT; + dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); + goto done; + } + if (crp->crp_desc->crd_next) { + if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) + q->ixp_q_ccrd = crp->crp_desc->crd_next; + else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) + q->ixp_q_acrd = crp->crp_desc->crd_next; + else { + crp->crp_etype = ENOENT; + dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); + goto done; + } + } + + /* + * If there is a direction change for this context then we mark it as + * unregistered and re-register is for the new direction. This is not + * a very expensive operation and currently only tends to happen when + * user-space application are doing benchmarks + * + * DM - we should be checking for pending requests before unregistering. + */ + if (q->ixp_q_ccrd && ixp->ixp_registered && + ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { + dprintk("%s - detected direction change on session\n", __FUNCTION__); + ixp->ixp_registered = 0; + } + + /* + * if we are registered, call straight into the perform code + */ + if (ixp->ixp_registered) { + ixp_q_process(q); + return 0; + } + + /* + * the only part of the context not set in newsession is the direction + * dependent parts + */ + if (q->ixp_q_ccrd) { + ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); + if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { + ixp->ixp_ctx.operation = q->ixp_q_acrd ? + IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; + } else { + ixp->ixp_ctx.operation = q->ixp_q_acrd ? + IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; + } + } else { + /* q->ixp_q_acrd must be set if we are here */ + ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; + } + + status = list_empty(&ixp->ixp_q); + list_add_tail(&q->ixp_q_list, &ixp->ixp_q); + if (status) + schedule_work(&ixp->ixp_registration_work); + return 0; + +done: + if (q) + kmem_cache_free(qcache, q); + crypto_done(crp); + return 0; +} + + +#ifdef __ixp46X +/* + * key processing support for the ixp465 + */ + + +/* + * copy a BN (LE) into a buffer (BE) an fill out the op appropriately + * assume zeroed and only copy bits that are significant + */ + +static int +ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) +{ + unsigned char *src = (unsigned char *) p->crp_p; + unsigned char *dst; + int len, bits = p->crp_nbits; + + dprintk("%s()\n", __FUNCTION__); + + if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { + dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, + bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); + return -1; + } + + len = (bits + 31) / 32; /* the number UINT32's needed */ + + dst = (unsigned char *) &buf[len]; + dst--; + + while (bits > 0) { + *dst-- = *src++; + bits -= 8; + } + +#if 0 /* no need to zero remaining bits as it is done during request alloc */ + while (dst > (unsigned char *) buf) + *dst-- = '\0'; +#endif + + op->pData = buf; + op->dataLen = len; + return 0; +} + +/* + * copy out the result, be as forgiving as we can about small output buffers + */ + +static int +ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) +{ + unsigned char *dst = (unsigned char *) p->crp_p; + unsigned char *src = (unsigned char *) buf; + int len, z, bits = p->crp_nbits; + + dprintk("%s()\n", __FUNCTION__); + + len = op->dataLen * sizeof(UINT32); + + /* skip leading zeroes to be small buffer friendly */ + z = 0; + while (z < len && src[z] == '\0') + z++; + + src += len; + src--; + len -= z; + + while (len > 0 && bits > 0) { + *dst++ = *src--; + len--; + bits -= 8; + } + + while (bits > 0) { + *dst++ = '\0'; + bits -= 8; + } + + if (len > 0) { + dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", + __FUNCTION__, len, z, p->crp_nbits / 8); + return -1; + } + + return 0; +} + + +/* + * the parameter offsets for exp_mod + */ + +#define IXP_PARAM_BASE 0 +#define IXP_PARAM_EXP 1 +#define IXP_PARAM_MOD 2 +#define IXP_PARAM_RES 3 + +/* + * key processing complete callback, is also used to start processing + * by passing a NULL for pResult + */ + +static void +ixp_kperform_cb( + IxCryptoAccPkeEauOperation operation, + IxCryptoAccPkeEauOpResult *pResult, + BOOL carryOrBorrow, + IxCryptoAccStatus status) +{ + struct ixp_pkq *q, *tmp; + unsigned long flags; + + dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, + carryOrBorrow, status); + + /* handle a completed request */ + if (pResult) { + if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { + q = ixp_pk_cur; + if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { + dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); + q->pkq_krp->krp_status = ERANGE; /* could do better */ + } else { + /* copy out the result */ + if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], + &q->pkq_result, q->pkq_obuf)) + q->pkq_krp->krp_status = ERANGE; + } + crypto_kdone(q->pkq_krp); + kfree(q); + ixp_pk_cur = NULL; + } else + printk("%s - callback with invalid result pointer\n", __FUNCTION__); + } + + spin_lock_irqsave(&ixp_pkq_lock, flags); + if (ixp_pk_cur || list_empty(&ixp_pkq)) { + spin_unlock_irqrestore(&ixp_pkq_lock, flags); + return; + } + + list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { + + list_del(&q->pkq_list); + ixp_pk_cur = q; + + spin_unlock_irqrestore(&ixp_pkq_lock, flags); + + status = ixCryptoAccPkeEauPerform( + IX_CRYPTO_ACC_OP_EAU_MOD_EXP, + &q->pkq_op, + ixp_kperform_cb, + &q->pkq_result); + + if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { + dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); + return; /* callback will return here for callback */ + } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { + printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); + } else { + printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", + __FUNCTION__, status); + } + q->pkq_krp->krp_status = ERANGE; /* could do better */ + crypto_kdone(q->pkq_krp); + kfree(q); + spin_lock_irqsave(&ixp_pkq_lock, flags); + } + spin_unlock_irqrestore(&ixp_pkq_lock, flags); +} + + +static int +ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) +{ + struct ixp_pkq *q; + int rc = 0; + unsigned long flags; + + dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, + krp->krp_param[IXP_PARAM_BASE].crp_nbits, + krp->krp_param[IXP_PARAM_EXP].crp_nbits, + krp->krp_param[IXP_PARAM_MOD].crp_nbits, + krp->krp_param[IXP_PARAM_RES].crp_nbits); + + + if (krp->krp_op != CRK_MOD_EXP) { + krp->krp_status = EOPNOTSUPP; + goto err; + } + + q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); + if (q == NULL) { + krp->krp_status = ENOMEM; + goto err; + } + + /* + * The PKE engine does not appear to zero the output buffer + * appropriately, so we need to do it all here. + */ + memset(q, 0, sizeof(*q)); + + q->pkq_krp = krp; + INIT_LIST_HEAD(&q->pkq_list); + + if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, + q->pkq_ibuf0)) + rc = 1; + if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], + &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) + rc = 2; + if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], + &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) + rc = 3; + + if (rc) { + kfree(q); + krp->krp_status = ERANGE; + goto err; + } + + q->pkq_result.pData = q->pkq_obuf; + q->pkq_result.dataLen = + (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; + + spin_lock_irqsave(&ixp_pkq_lock, flags); + list_add_tail(&q->pkq_list, &ixp_pkq); + spin_unlock_irqrestore(&ixp_pkq_lock, flags); + + if (!ixp_pk_cur) + ixp_kperform_cb(0, NULL, 0, 0); + return (0); + +err: + crypto_kdone(krp); + return (0); +} + + + +#ifdef CONFIG_OCF_RANDOMHARVEST +/* + * We run the random number generator output through SHA so that it + * is FIPS compliant. + */ + +static volatile int sha_done = 0; +static unsigned char sha_digest[20]; + +static void +ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) +{ + dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); + if (sha_digest != digest) + printk("digest error\n"); + if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) + sha_done = 1; + else + sha_done = -status; +} + +static int +ixp_read_random(void *arg, u_int32_t *buf, int maxwords) +{ + IxCryptoAccStatus status; + int i, n, rc; + + dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); + memset(buf, 0, maxwords * sizeof(*buf)); + status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); + if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { + dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", + __FUNCTION__, status); + return 0; + } + + /* + * run the random data through SHA to make it look more random + */ + + n = sizeof(sha_digest); /* process digest bytes at a time */ + + rc = 0; + for (i = 0; i < maxwords; i += n / sizeof(*buf)) { + if ((maxwords - i) * sizeof(*buf) < n) + n = (maxwords - i) * sizeof(*buf); + sha_done = 0; + status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, + (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); + if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { + dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); + return -EIO; + } + while (!sha_done) + schedule(); + if (sha_done < 0) { + dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); + return 0; + } + memcpy(&buf[i], sha_digest, n); + rc += n / sizeof(*buf);; + } + + return rc; +} +#endif /* CONFIG_OCF_RANDOMHARVEST */ + +#endif /* __ixp46X */ + + + +/* + * our driver startup and shutdown routines + */ + +static int +ixp_init(void) +{ + dprintk("%s(%p)\n", __FUNCTION__, ixp_init); + + if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) + printk("ixCryptoAccInit failed, assuming already initialised!\n"); + + qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, + SLAB_HWCACHE_ALIGN, NULL +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) + , NULL +#endif + ); + if (!qcache) { + printk("failed to create Qcache\n"); + return -ENOENT; + } + + memset(&ixpdev, 0, sizeof(ixpdev)); + softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); + + ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), + CRYPTOCAP_F_HARDWARE); + if (ixp_id < 0) + panic("IXP/OCF crypto device cannot initialize!"); + +#define REGISTER(alg) \ + crypto_register(ixp_id,alg,0,0) + + REGISTER(CRYPTO_DES_CBC); + REGISTER(CRYPTO_3DES_CBC); + REGISTER(CRYPTO_RIJNDAEL128_CBC); +#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 + REGISTER(CRYPTO_MD5); + REGISTER(CRYPTO_SHA1); +#endif + REGISTER(CRYPTO_MD5_HMAC); + REGISTER(CRYPTO_SHA1_HMAC); +#undef REGISTER + +#ifdef __ixp46X + spin_lock_init(&ixp_pkq_lock); + /* + * we do not enable the go fast options here as they can potentially + * allow timing based attacks + * + * http://www.openssl.org/news/secadv_20030219.txt + */ + ixCryptoAccPkeEauExpConfig(0, 0); + crypto_kregister(ixp_id, CRK_MOD_EXP, 0); +#ifdef CONFIG_OCF_RANDOMHARVEST + crypto_rregister(ixp_id, ixp_read_random, NULL); +#endif +#endif + + return 0; +} + +static void +ixp_exit(void) +{ + dprintk("%s()\n", __FUNCTION__); + crypto_unregister_all(ixp_id); + ixp_id = -1; + kmem_cache_destroy(qcache); + qcache = NULL; +} + +module_init(ixp_init); +module_exit(ixp_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/Makefile b/target/linux/generic/files/crypto/ocf/kirkwood/Makefile new file mode 100644 index 0000000..6dafd00 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/Makefile @@ -0,0 +1,19 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o + +mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o + +# Extra objects required by the CESA driver +mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o + +ifdef src +EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) +endif + +EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAes.h b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAes.h new file mode 100644 index 0000000..07a8601 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAes.h @@ -0,0 +1,62 @@ +/* mvAes.h v2.0 August '99 + * Reference ANSI C code + */ + +/* AES Cipher header file for ANSI C Submissions + Lawrence E. Bassham III + Computer Security Division + National Institute of Standards and Technology + + April 15, 1998 + + This sample is to assist implementers developing to the Cryptographic +API Profile for AES Candidate Algorithm Submissions. Please consult this +document as a cross-reference. + + ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE +MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH +THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT +BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE +IMPLEMENTATION SPECIFIC INFORMATION. +*/ + +/* Includes: + Standard include files +*/ + +#include "mvOs.h" + + +/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ + +/* Key direction is invalid, e.g., unknown value */ +#define AES_BAD_KEY_DIR -1 + +/* Key material not of correct length */ +#define AES_BAD_KEY_MAT -2 + +/* Key passed is not valid */ +#define AES_BAD_KEY_INSTANCE -3 + +/* Params struct passed to cipherInit invalid */ +#define AES_BAD_CIPHER_MODE -4 + +/* Cipher in wrong state (e.g., not initialized) */ +#define AES_BAD_CIPHER_STATE -5 + +#define AES_BAD_CIPHER_INSTANCE -7 + + +/* Function protoypes */ +/* CHANGED: makeKey(): parameter blockLen added + this parameter is absolutely necessary if you want to + setup the round keys in a variable block length setting + cipherInit(): parameter blockLen added (for obvious reasons) + */ +int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); +int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher); +int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, + MV_U32 *plain, int numBlocks, MV_U32 *cipher); + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c new file mode 100644 index 0000000..a65dc28 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c @@ -0,0 +1,317 @@ +/* rijndael-alg-ref.c v2.0 August '99 + * Reference ANSI C code + * authors: Paulo Barreto + * Vincent Rijmen, K.U.Leuven + * + * This code is placed in the public domain. + */ + +#include "mvOs.h" + +#include "mvAesAlg.h" + +#include "mvAesBoxes.dat" + + +MV_U8 mul1(MV_U8 aa, MV_U8 bb); +void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); +void ShiftRow128Enc(MV_U8 a[4][MAXBC]); +void ShiftRow128Dec(MV_U8 a[4][MAXBC]); +void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); +void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); +void InvMixColumn(MV_U8 a[4][MAXBC]); + + +#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) + +MV_U8 mul1(MV_U8 aa, MV_U8 bb) +{ + return mask[bb] & Alogtable[aa + Logtable[bb]]; +} + + +void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) +{ + /* Exor corresponding text input and round key input bytes + */ + ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; + ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; + ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; + ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; + +} + +void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { + /* Row 0 remains unchanged + * The other three rows are shifted a variable amount + */ + MV_U8 tmp[MAXBC]; + + tmp[0] = a[1][1]; + tmp[1] = a[1][2]; + tmp[2] = a[1][3]; + tmp[3] = a[1][0]; + + ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[1][0] = tmp[0]; + a[1][1] = tmp[1]; + a[1][2] = tmp[2]; + a[1][3] = tmp[3]; + */ + tmp[0] = a[2][2]; + tmp[1] = a[2][3]; + tmp[2] = a[2][0]; + tmp[3] = a[2][1]; + + ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[2][0] = tmp[0]; + a[2][1] = tmp[1]; + a[2][2] = tmp[2]; + a[2][3] = tmp[3]; + */ + tmp[0] = a[3][3]; + tmp[1] = a[3][0]; + tmp[2] = a[3][1]; + tmp[3] = a[3][2]; + + ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[3][0] = tmp[0]; + a[3][1] = tmp[1]; + a[3][2] = tmp[2]; + a[3][3] = tmp[3]; + */ +} + +void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { + /* Row 0 remains unchanged + * The other three rows are shifted a variable amount + */ + MV_U8 tmp[MAXBC]; + + tmp[0] = a[1][3]; + tmp[1] = a[1][0]; + tmp[2] = a[1][1]; + tmp[3] = a[1][2]; + + ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[1][0] = tmp[0]; + a[1][1] = tmp[1]; + a[1][2] = tmp[2]; + a[1][3] = tmp[3]; + */ + + tmp[0] = a[2][2]; + tmp[1] = a[2][3]; + tmp[2] = a[2][0]; + tmp[3] = a[2][1]; + + ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[2][0] = tmp[0]; + a[2][1] = tmp[1]; + a[2][2] = tmp[2]; + a[2][3] = tmp[3]; + */ + + tmp[0] = a[3][1]; + tmp[1] = a[3][2]; + tmp[2] = a[3][3]; + tmp[3] = a[3][0]; + + ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; + /* + a[3][0] = tmp[0]; + a[3][1] = tmp[1]; + a[3][2] = tmp[2]; + a[3][3] = tmp[3]; + */ +} + +void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { + /* Replace every byte of the input by the byte at that place + * in the nonlinear S-box + */ + int i, j; + + for(i = 0; i < 4; i++) + for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; +} + +void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { + /* Mix the four bytes of every column in a linear way + */ + MV_U8 b[4][MAXBC]; + int i, j; + + for(j = 0; j < 4; j++){ + b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; + b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; + b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; + b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; + } + for(i = 0; i < 4; i++) + /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ + ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; +} + +void InvMixColumn(MV_U8 a[4][MAXBC]) { + /* Mix the four bytes of every column in a linear way + * This is the opposite operation of Mixcolumn + */ + MV_U8 b[4][MAXBC]; + int i, j; + + for(j = 0; j < 4; j++){ + b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); + b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); + b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); + b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); + } + for(i = 0; i < 4; i++) + /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ + ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; +} + +int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) +{ + /* Calculate the necessary round keys + * The number of calculations depends on keyBits and blockBits + */ + int KC, BC, ROUNDS; + int i, j, t, rconpointer = 0; + MV_U8 tk[4][MAXKC]; + + switch (keyBits) { + case 128: KC = 4; break; + case 192: KC = 6; break; + case 256: KC = 8; break; + default : return (-1); + } + + switch (blockBits) { + case 128: BC = 4; break; + case 192: BC = 6; break; + case 256: BC = 8; break; + default : return (-2); + } + + switch (keyBits >= blockBits ? keyBits : blockBits) { + case 128: ROUNDS = 10; break; + case 192: ROUNDS = 12; break; + case 256: ROUNDS = 14; break; + default : return (-3); /* this cannot happen */ + } + + + for(j = 0; j < KC; j++) + for(i = 0; i < 4; i++) + tk[i][j] = k[i][j]; + t = 0; + /* copy values into round key array */ + for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) + for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; + + while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ + /* calculate new values */ + for(i = 0; i < 4; i++) + tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; + tk[0][0] ^= rcon[rconpointer++]; + + if (KC != 8) + for(j = 1; j < KC; j++) + for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; + else { + for(j = 1; j < KC/2; j++) + for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; + for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; + for(j = KC/2 + 1; j < KC; j++) + for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; + } + /* copy values into round key array */ + for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) + for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; + } + + return 0; +} + + + +int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) +{ + /* Encryption of one block. + */ + int r, BC, ROUNDS; + + BC = 4; + ROUNDS = rounds; + + /* begin with a key addition + */ + + KeyAddition(a,rk[0],BC); + + /* ROUNDS-1 ordinary rounds + */ + for(r = 1; r < ROUNDS; r++) { + Substitution(a,S); + ShiftRow128Enc(a); + MixColumn(a, rk[r]); + /*KeyAddition(a,rk[r],BC);*/ + } + + /* Last round is special: there is no MixColumn + */ + Substitution(a,S); + ShiftRow128Enc(a); + KeyAddition(a,rk[ROUNDS],BC); + + return 0; +} + + +int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) +{ + int r, BC, ROUNDS; + + BC = 4; + ROUNDS = rounds; + + /* To decrypt: apply the inverse operations of the encrypt routine, + * in opposite order + * + * (KeyAddition is an involution: it 's equal to its inverse) + * (the inverse of Substitution with table S is Substitution with the inverse table of S) + * (the inverse of Shiftrow is Shiftrow over a suitable distance) + */ + + /* First the special round: + * without InvMixColumn + * with extra KeyAddition + */ + KeyAddition(a,rk[ROUNDS],BC); + ShiftRow128Dec(a); + Substitution(a,Si); + + /* ROUNDS-1 ordinary rounds + */ + for(r = ROUNDS-1; r > 0; r--) { + KeyAddition(a,rk[r],BC); + InvMixColumn(a); + ShiftRow128Dec(a); + Substitution(a,Si); + + } + + /* End with the extra key addition + */ + + KeyAddition(a,rk[0],BC); + + return 0; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h new file mode 100644 index 0000000..ec81e40 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h @@ -0,0 +1,19 @@ +/* rijndael-alg-ref.h v2.0 August '99 + * Reference ANSI C code + * authors: Paulo Barreto + * Vincent Rijmen, K.U.Leuven + */ +#ifndef __RIJNDAEL_ALG_H +#define __RIJNDAEL_ALG_H + +#define MAXBC (128/32) +#define MAXKC (256/32) +#define MAXROUNDS 14 + + +int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); + +int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); +int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); + +#endif /* __RIJNDAEL_ALG_H */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c new file mode 100644 index 0000000..b432dc6 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c @@ -0,0 +1,312 @@ +/* rijndael-api-ref.c v2.1 April 2000 + * Reference ANSI C code + * authors: v2.0 Paulo Barreto + * Vincent Rijmen, K.U.Leuven + * v2.1 Vincent Rijmen, K.U.Leuven + * + * This code is placed in the public domain. + */ +#include "mvOs.h" + +#include "mvAes.h" +#include "mvAesAlg.h" + + +/* Defines: + Add any additional defines you need +*/ + +#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ +#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ +#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ + + +int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) +{ + MV_U8 W[MAXROUNDS+1][4][MAXBC]; + MV_U8 k[4][MAXKC]; + MV_U8 j; + int i, rounds, KC; + + if (expandedKey == NULL) + { + return AES_BAD_KEY_INSTANCE; + } + + if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) + { + return AES_BAD_KEY_MAT; + } + + if (keyMaterial == NULL) + { + return AES_BAD_KEY_MAT; + } + + /* initialize key schedule: */ + for(i=0; i= 3) +MV_U32 cesaChainLength = 0; +int chainReqNum = 0; +MV_U32 chainIndex = 0; +MV_CESA_REQ* pNextActiveChain = 0; +MV_CESA_REQ* pEndCurrChain = 0; +MV_BOOL isFirstReq = MV_TRUE; +#endif + +static INLINE MV_U8* mvCesaSramAddrGet(void) +{ +#ifdef MV_CESA_NO_SRAM + return (MV_U8*)cesaSramVirtPtr; +#else + return (MV_U8*)cesaCryptEngBase; +#endif /* MV_CESA_NO_SRAM */ +} + +static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) +{ +#ifdef MV_CESA_NO_SRAM + return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); +#else + return (MV_ULONG)pSramVirt; +#endif /* MV_CESA_NO_SRAM */ +} + +/* Internal Function prototypes */ + +static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, + int cryptoOffset, int ivOffset, int cryptoLength, + int macOffset, int digestOffset, int macLength, int macTotalLen, + MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); + +static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); + +static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, + MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush); + +static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, + unsigned char innerIV[], unsigned char outerIV[]); + +static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, + int macDataSize); + +static MV_CESA_COMMAND* mvCesaCtrModeInit(void); + +static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); +static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); +static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); + +static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); +static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); + +static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); +static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); + +static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, + int cryptoOffset, int macOffset, + int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); +static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); + + +/* Go to the next request in the request queue */ +static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) +{ + if(pReq == pCesaReqLast) + return pCesaReqFirst; + + return pReq+1; +} + +#if (MV_CESA_VERSION >= 3) +/* Go to the previous request in the request queue */ +static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) +{ + if(pReq == pCesaReqFirst) + return pCesaReqLast; + + return pReq-1; +} + +#endif + + +static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) +{ + int frag; + +#if (MV_CESA_VERSION >= 3) + pReq->state = MV_CESA_CHAIN; +#else + pReq->state = MV_CESA_PROCESS; +#endif + cesaStats.startCount++; + + if(pReq->fragMode == MV_CESA_FRAG_NONE) + { + frag = 0; + } + else + { + frag = pReq->frags.nextFrag; + pReq->frags.nextFrag++; + } +#if (MV_CESA_VERSION >= 2) + /* Enable TDMA engine */ + MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); + MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, + (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); +#else + /* Enable IDMA engine */ + MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); + MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), + (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); +#endif /* MV_CESA_VERSION >= 2 */ + +#if defined(MV_BRIDGE_SYNC_REORDER) + mvOsBridgeReorderWA(); +#endif + + /* Start Accelerator */ + MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); +} + + +/******************************************************************************* +* mvCesaHalInit - Initialize the CESA driver +* +* DESCRIPTION: +* This function initialize the CESA driver. +* 1) Session database +* 2) Request queue +* 4) DMA descriptor lists - one list per request. Each list +* has MV_CESA_MAX_DMA_DESC descriptors. +* +* INPUT: +* numOfSession - maximum number of supported sessions +* queueDepth - number of elements in the request queue. +* pSramBase - virtual address of Sram +* osHandle - A handle used by the OS to allocate memory for the +* module (Passed to the OS Services layer) +* +* RETURN: +* MV_OK - Success +* MV_NO_RESOURCE - Fail, can't allocate resources: +* Session database, request queue, +* DMA descriptors list, LRU cache database. +* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. +* +*******************************************************************************/ +MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, + void *osHandle) +{ + int i, req; + MV_U32 descOffsetReg, configReg; + MV_CESA_SRAM_SA *pSramSA; + + + mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", + numOfSession, queueDepth, pSramBase); + + cesaOsHandle = osHandle; + /* Create Session database */ + pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); + if(pCesaSAD == NULL) + { + mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", + sizeof(MV_CESA_SA)*numOfSession, numOfSession); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); + cesaMaxSA = numOfSession; + + /* Allocate imag of sramSA in the DRAM */ + cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + + CPU_D_CACHE_LINE_SIZE; + + cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, + &cesaSramSaBuf.bufPhysAddr, + &cesaSramSaBuf.memHandle); + + if(cesaSramSaBuf.bufVirtPtr == NULL) + { + mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", + cesaSramSaBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); + pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + for(i=0; i= 3) + cesaChainLength = MAX_CESA_CHAIN_LENGTH; +#endif + /* pSramBase must be 8 byte aligned */ + if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) + { + mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", + pSramBase); + mvCesaFinish(); + return MV_NOT_ALIGNED; + } + cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; + + cesaCryptEngBase = cryptEngBase; + + /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ + + /* Clear registers */ + MV_REG_WRITE( MV_CESA_CFG_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); + + /* Initialize DMA descriptor lists for all requests in Request queue */ + descOffsetReg = configReg = 0; + for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + + CPU_D_CACHE_LINE_SIZE; + + pReq->cesaDescBuf.bufVirtPtr = + mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, + &pReq->cesaDescBuf.bufPhysAddr, + &pReq->cesaDescBuf.memHandle); + + if(pReq->cesaDescBuf.bufVirtPtr == NULL) + { + mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", + req, pReq->cesaDescBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); + pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + + CPU_D_CACHE_LINE_SIZE; + + pReq->dmaDescBuf.bufVirtPtr = + mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, + &pReq->dmaDescBuf.bufPhysAddr, + &pReq->dmaDescBuf.memHandle); + + if(pReq->dmaDescBuf.bufVirtPtr == NULL) + { + mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", + req, pReq->dmaDescBuf.bufSize); + mvCesaFinish(); + return MV_NO_RESOURCE; + } + memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); + pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + for(frag=0; fragdma[frag]; + + pDma->pDmaFirst = pDmaDesc; + pDma->pDmaLast = NULL; + + for(i=0; ipDmaFirst[i].phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); + } + pDma->pDmaFirst[i].phyNextDescPtr = 0; + mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); + + pDmaDesc += MV_CESA_MAX_DMA_DESC; + } + } + /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ + descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); + MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); + + configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); +#if (MV_CESA_VERSION >= 3) + configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; +#endif + +#if (MV_CESA_VERSION >= 2) + /* Initialize TDMA engine */ + MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); + MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); + MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); +#else + /* Initialize IDMA #0 engine */ + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); + MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); + MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); + MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE +#ifdef MV_CPU_LE + | ICCHR_DESC_BYTE_SWAP_EN +#endif + ); + /* Clear Cause Byte of IDMA channel to be used */ + MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); +#endif /* (MV_CESA_VERSION >= 2) */ + + /* Set CESA configuration registers */ + MV_REG_WRITE( MV_CESA_CFG_REG, configReg); + mvCesaDebugStatsClear(); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaFinish - Shutdown the CESA driver +* +* DESCRIPTION: +* This function shutdown the CESA driver and free all allocted resources. +* +* INPUT: None +* +* RETURN: +* MV_OK - Success +* Other - Fail +* +*******************************************************************************/ +MV_STATUS mvCesaFinish (void) +{ + int req; + MV_CESA_REQ* pReq; + + mvOsPrintf("mvCesaFinish: \n"); + + cesaSramVirtPtr = NULL; + + /* Free all resources: DMA list, etc. */ + for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) + { + mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, + pReq->dmaDescBuf.bufPhysAddr, + pReq->dmaDescBuf.bufVirtPtr, + pReq->dmaDescBuf.memHandle); + } + if(pReq->cesaDescBuf.bufVirtPtr != NULL) + { + mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, + pReq->cesaDescBuf.bufPhysAddr, + pReq->cesaDescBuf.bufVirtPtr, + pReq->cesaDescBuf.memHandle); + } + } +#if (MV_CESA_VERSION < 2) + MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); +#endif /* (MV_CESA_VERSION < 2) */ + + /* Free request queue */ + if(pCesaReqFirst != NULL) + { + mvOsFree(pCesaReqFirst); + pCesaReqFirst = pCesaReqLast = NULL; + pCesaReqEmpty = pCesaReqProcess = NULL; + cesaQueueDepth = cesaReqResources = 0; + } + /* Free SA database */ + if(pCesaSAD != NULL) + { + mvOsFree(pCesaSAD); + pCesaSAD = NULL; + cesaMaxSA = 0; + } + MV_REG_WRITE( MV_CESA_CFG_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode +* +* DESCRIPTION: +* This function set IV value using by Crypto algorithms in CBC mode. +* Each channel has its own IV value. +* This function gets IV value from the caller. If no IV value passed from +* the caller or only part of IV passed, the function will init the rest part +* of IV value (or the whole IV) by random value. +* +* INPUT: +* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL +* the function will generate random IV value. +* int ivSize - size (in bytes) of IV provided by user. If ivSize is +* smaller than maximum IV size, the function will complete +* IV by random value. +* +* RETURN: +* MV_OK - Success +* Other - Fail +* +*******************************************************************************/ +MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) +{ + MV_U8* pSramIV; +#if defined(MV646xx) + mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); +#endif + pSramIV = cesaSramVirtPtr->cryptoIV; + if(ivSize > MV_CESA_MAX_IV_LENGTH) + { + mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); + ivSize = MV_CESA_MAX_IV_LENGTH; + } + if(pIV != NULL) + { + memcpy(pSramIV, pIV, ivSize); + ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; + pSramIV += ivSize; + } + + while(ivSize > 0) + { + int size, mv_random = mvOsRand(); + + size = MV_MIN(ivSize, sizeof(mv_random)); + memcpy(pSramIV, (void*)&mv_random, size); + + pSramIV += size; + ivSize -= size; + } +/* + mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, + MV_CESA_MAX_IV_LENGTH); + mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, + MV_CESA_MAX_IV_LENGTH); +*/ + return MV_OK; +} + +/******************************************************************************* +* mvCesaSessionOpen - Open new uni-directional crypto session +* +* DESCRIPTION: +* This function open new session. +* +* INPUT: +* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters +* +* OUTPUT: +* short *pSid - session ID, should be used for all future +* requests over this session. +* +* RETURN: +* MV_OK - Session opend successfully. +* MV_FULL - All sessions are in use, no free place in +* SA database. +* MV_BAD_PARAM - One of session input parameters is invalid. +* +*******************************************************************************/ +MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) +{ + short sid; + MV_U32 config = 0; + int digestSize; + + cesaStats.openedCount++; + + /* Find free entry in SAD */ + for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) + { + mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", + pSession->operation); + return MV_BAD_PARAM; + } + config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); + + if( (pSession->direction != MV_CESA_DIR_ENCODE) && + (pSession->direction != MV_CESA_DIR_DECODE) ) + { + mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", + pSession->direction); + return MV_BAD_PARAM; + } + config |= (pSession->direction << MV_CESA_DIRECTION_BIT); + /* Clear SA entry */ + /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ + + /* Check AUTH parameters and update SA entry */ + if(pSession->operation != MV_CESA_CRYPTO_ONLY) + { + /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ + if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || + (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) + { + if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) + { + mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", + pSession->macKeyLength); + return MV_BAD_PARAM; + } + mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, + pCesaSAD[sid].pSramSA->macInnerIV, + pCesaSAD[sid].pSramSA->macOuterIV); + pCesaSAD[sid].macKeyLength = pSession->macKeyLength; + } + switch(pSession->macMode) + { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", + pSession->macMode); + return MV_BAD_PARAM; + } + config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); + + /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ + /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ + if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) + { + mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", + pSession->digestSize); + mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); + return MV_BAD_PARAM; + } + pCesaSAD[sid].digestSize = pSession->digestSize; + + if(pCesaSAD[sid].digestSize == 12) + { + /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ + config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); + } + } + + /* Check CRYPTO parameters and update SA entry */ + if(pSession->operation != MV_CESA_MAC_ONLY) + { + switch(pSession->cryptoAlgorithm) + { + case MV_CESA_CRYPTO_DES: + pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; + pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_3DES: + pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; + pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; + /* Only EDE mode is supported */ + config |= (MV_CESA_CRYPTO_3DES_EDE << + MV_CESA_CRYPTO_3DES_MODE_BIT); + break; + + case MV_CESA_CRYPTO_AES: + switch(pSession->cryptoKeyLength) + { + case 16: + pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_128 << + MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + + case 24: + pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_192 << + MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + + case 32: + default: + pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; + config |= (MV_CESA_CRYPTO_AES_KEY_256 << + MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); + break; + } + pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", + pSession->cryptoAlgorithm); + return MV_BAD_PARAM; + } + config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); + + if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) + { + mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", + pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); + return MV_BAD_PARAM; + } + + /* Copy Crypto key */ + if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && + (pSession->direction == MV_CESA_DIR_DECODE)) + { + /* Crypto Key for AES decode is computed from original key material */ + /* and depend on cryptoKeyLength (128/192/256 bits) */ + aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, + pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); + } + else + { + /*panic("mvCesaSessionOpen2");*/ + memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, + pCesaSAD[sid].cryptoKeyLength); + + } + + switch(pSession->cryptoMode) + { + case MV_CESA_CRYPTO_ECB: + pCesaSAD[sid].cryptoIvSize = 0; + break; + + case MV_CESA_CRYPTO_CBC: + pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; + break; + + case MV_CESA_CRYPTO_CTR: + /* Supported only for AES algorithm */ + if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) + { + mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); + return MV_BAD_PARAM; + } + pCesaSAD[sid].cryptoIvSize = 0; + pCesaSAD[sid].ctrMode = 1; + /* Replace to ECB mode for HW */ + pSession->cryptoMode = MV_CESA_CRYPTO_ECB; + break; + + default: + mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", + pSession->cryptoMode); + return MV_BAD_PARAM; + } + + config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); + } + pCesaSAD[sid].config = config; + + mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); + if(pSid != NULL) + *pSid = sid; + + pCesaSAD[sid].valid = 1; + return MV_OK; +} + +/******************************************************************************* +* mvCesaSessionClose - Close active crypto session +* +* DESCRIPTION: +* This function closes existing session +* +* INPUT: +* short sid - Unique identifier of the session to be closed +* +* RETURN: +* MV_OK - Session closed successfully. +* MV_BAD_PARAM - Session identifier is out of valid range. +* MV_NOT_FOUND - There is no active session with such ID. +* +*******************************************************************************/ +MV_STATUS mvCesaSessionClose(short sid) +{ + cesaStats.closedCount++; + + if(sid >= cesaMaxSA) + { + mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); + return MV_BAD_PARAM; + } + if(pCesaSAD[sid].valid == 0) + { + mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); + return MV_NOT_FOUND; + } + if(cesaLastSid == sid) + cesaLastSid = -1; + + pCesaSAD[sid].valid = 0; + return MV_OK; +} + +/******************************************************************************* +* mvCesaAction - Perform crypto operation +* +* DESCRIPTION: +* This function set new CESA request FIFO queue for further HW processing. +* The function checks request parameters before set new request to the queue. +* If one of the CESA channels is ready for processing the request will be +* passed to HW. When request processing is finished the CESA interrupt will +* be generated by HW. The caller should call mvCesaReadyGet() function to +* complete request processing and get result. +* +* INPUT: +* MV_CESA_COMMAND *pCmd - pointer to new CESA request. +* It includes pointers to Source and Destination +* buffers, session identifier get from +* mvCesaSessionOpen() function, pointer to caller +* private data and all needed crypto parameters. +* +* RETURN: +* MV_OK - request successfully added to request queue +* and will be processed. +* MV_NO_MORE - request successfully added to request queue and will +* be processed, but request queue became Full and next +* request will not be accepted. +* MV_NO_RESOURCE - request queue is FULL and the request can not +* be processed. +* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is +* failed. Request can not be processed. +* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed +* as one request and should be splitted for two requests: +* CRYPTO_ONLY and MAC_ONLY. +* MV_BAD_PARAM - One of the request parameters is out of valid range. +* The request can not be processed. +* +*******************************************************************************/ +MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) +{ + MV_STATUS status; + MV_CESA_REQ* pReq = pCesaReqEmpty; + int sid = pCmd->sessionId; + MV_CESA_SA* pSA = &pCesaSAD[sid]; +#if (MV_CESA_VERSION >= 3) + MV_CESA_REQ* pFromReq; + MV_CESA_REQ* pToReq; +#endif + cesaStats.reqCount++; + + /* Check that the request queue is not FULL */ + if(cesaReqResources == 0) + return MV_NO_RESOURCE; + + if( (sid >= cesaMaxSA) || (!pSA->valid) ) + { + mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); + return MV_BAD_PARAM; + } + pSA->count++; + + if(pSA->ctrMode) + { + /* AES in CTR mode can't be mixed with Authentication */ + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); + return MV_NOT_ALLOWED; + } + /* All other request parameters should not be checked because key stream */ + /* (not user data) processed by AES HW engine */ + pReq->pOrgCmd = pCmd; + /* Allocate temporary pCmd structure for Key stream */ + pCmd = mvCesaCtrModeInit(); + if(pCmd == NULL) + return MV_OUT_OF_CPU_MEM; + + /* Prepare Key stream */ + mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); + pReq->fixOffset = 0; + } + else + { + /* Check request parameters and calculae fixOffset */ + status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); + if(status != MV_OK) + { + return status; + } + } + pReq->pCmd = pCmd; + + /* Check if the packet need fragmentation */ + if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) + { + /* request size is smaller than single buffer size */ + pReq->fragMode = MV_CESA_FRAG_NONE; + + /* Prepare NOT fragmented packets */ + status = mvCesaReqProcess(pReq); + if(status != MV_OK) + { + mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", + pReq, status); + } +#if (MV_CESA_VERSION >= 3) + pReq->frags.numFrag = 1; +#endif + } + else + { + MV_U8 frag = 0; + + /* request size is larger than buffer size - needs fragmentation */ + + /* Check restrictions for processing fragmented packets */ + status = mvCesaFragParamCheck(pSA, pCmd); + if(status != MV_OK) + return status; + + pReq->fragMode = MV_CESA_FRAG_FIRST; + pReq->frags.nextFrag = 0; + + /* Prepare Process Fragmented packets */ + while(pReq->fragMode != MV_CESA_FRAG_LAST) + { + if(frag >= MV_CESA_MAX_REQ_FRAGS) + { + mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); + return MV_OUT_OF_CPU_MEM; + } + status = mvCesaFragReqProcess(pReq, frag); + if(status == MV_OK) { +#if (MV_CESA_VERSION >= 3) + if(frag) { + pReq->dma[frag-1].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); + mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); + } +#endif + frag++; + } + } + pReq->frags.numFrag = frag; +#if (MV_CESA_VERSION >= 3) + if(chainReqNum) { + chainReqNum += pReq->frags.numFrag; + if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) + chainReqNum = MAX_CESA_CHAIN_LENGTH; + } +#endif + } + + pReq->state = MV_CESA_PENDING; + + pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); + cesaReqResources -= 1; + +/* #ifdef CESA_DEBUG */ + if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) + cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); +/* #endif CESA_DEBUG */ + + cesaLastSid = sid; + +#if (MV_CESA_VERSION >= 3) + /* Are we within chain bounderies and follows the first request ? */ + if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { + if(chainIndex) { + pFromReq = MV_CESA_REQ_PREV_PTR(pReq); + pToReq = pReq; + pReq->state = MV_CESA_CHAIN; + /* assume concatenating is possible */ + pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); + mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); + + /* align active & next pointers */ + if(pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); + } + else { /* we have only one chain, start new one */ + chainReqNum = 0; + chainIndex++; + /* align active & next pointers */ + if(pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = pReq; + } + } + else { + /* In case we concatenate full chain */ + if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { + chainIndex++; + if(pNextActiveChain->state != MV_CESA_PENDING) + pEndCurrChain = pNextActiveChain = pReq; + chainReqNum = 0; + } + + pReq = pCesaReqProcess; + if(pReq->state == MV_CESA_PENDING) { + pNextActiveChain = pReq; + pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); + /* Start Process new request */ + mvCesaReqProcessStart(pReq); + } + } + + chainReqNum++; + + if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) + cesaStats.maxChainUsage = chainReqNum; + +#else + + /* Check status of CESA channels and process requests if possible */ + pReq = pCesaReqProcess; + if(pReq->state == MV_CESA_PENDING) + { + /* Start Process new request */ + mvCesaReqProcessStart(pReq); + } +#endif + /* If request queue became FULL - return MV_NO_MORE */ + if(cesaReqResources == 0) + return MV_NO_MORE; + + return MV_OK; + +} + +/******************************************************************************* +* mvCesaReadyGet - Get crypto request that processing is finished +* +* DESCRIPTION: +* This function complete request processing and return ready request to +* caller. To don't miss interrupts the caller must call this function +* while MV_OK or MV_TERMINATE values returned. +* +* INPUT: +* MV_U32 chanMap - map of CESA channels finished thier job +* accordingly with CESA Cause register. +* MV_CESA_RESULT* pResult - pointer to structure contains information +* about ready request. It includes pointer to +* user private structure "pReqPrv", session identifier +* for this request "sessionId" and return code. +* Return code set to MV_FAIL if calculated digest value +* on decode direction is different than digest value +* in the packet. +* +* RETURN: +* MV_OK - Success, ready request is returned. +* MV_NOT_READY - Next request is not ready yet. New interrupt will +* be generated for futher request processing. +* MV_EMPTY - There is no more request for processing. +* MV_BUSY - Fragmented request is not ready yet. +* MV_TERMINATE - Call this function once more to complete processing +* of fragmented request. +* +*******************************************************************************/ +MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) +{ + MV_STATUS status, readyStatus = MV_NOT_READY; + MV_U32 statusReg; + MV_CESA_REQ* pReq; + MV_CESA_SA* pSA; + +#if (MV_CESA_VERSION >= 3) + if(isFirstReq == MV_TRUE) { + if(chainIndex == 0) + chainReqNum = 0; + + isFirstReq = MV_FALSE; + + if(pNextActiveChain->state == MV_CESA_PENDING) { + /* Start request Process */ + mvCesaReqProcessStart(pNextActiveChain); + pEndCurrChain = pNextActiveChain; + if(chainIndex > 0) + chainIndex--; + /* Update pNextActiveChain to next chain head */ + while(pNextActiveChain->state == MV_CESA_CHAIN) + pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); + } + } + + /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ + if(pCesaReqProcess == pEndCurrChain) { + isFirstReq = MV_TRUE; + pEndCurrChain = pNextActiveChain; +#else + if(pCesaReqProcess->state != MV_CESA_PROCESS) { +#endif + return MV_EMPTY; + } + +#ifdef CESA_DEBUG + statusReg = MV_REG_READ(MV_CESA_STATUS_REG); + if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) + { + mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); + cesaStats.notReadyCount++; + return MV_NOT_READY; + } +#endif /* CESA_DEBUG */ + + cesaStats.readyCount++; + + pReq = pCesaReqProcess; + pSA = &pCesaSAD[pReq->pCmd->sessionId]; + + pResult->retCode = MV_OK; + if(pReq->fragMode != MV_CESA_FRAG_NONE) + { + MV_U8* pNewDigest; + int frag; +#if (MV_CESA_VERSION >= 3) + pReq->frags.nextFrag = 1; + while(pReq->frags.nextFrag <= pReq->frags.numFrag) { +#endif + frag = (pReq->frags.nextFrag - 1); + + /* Restore DMA descriptor list */ + pReq->dma[frag].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); + pReq->dma[frag].pDmaLast = NULL; + + /* Special processing for finished fragmented request */ + if(pReq->frags.nextFrag >= pReq->frags.numFrag) + { + mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); + + /* Fragmented packet is ready */ + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; + + if(macDataSize != 0) + { + /* Calculate all other blocks by SW */ + mvCesaFragAuthComplete(pReq, pSA, macDataSize); + } + + /* Copy new digest from SRAM to the Destination buffer */ + pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; + status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, + pReq->pCmd->digestOffset, pSA->digestSize); + + /* For decryption: Compare new digest value with original one */ + if((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) + { + if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) + { +/* + mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", + chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); +*/ + /* Signiture verification is failed */ + pResult->retCode = MV_FAIL; + } + } + } + readyStatus = MV_OK; + } +#if (MV_CESA_VERSION >= 3) + pReq->frags.nextFrag++; + } +#endif + } + else + { + mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); + + /* Restore DMA descriptor list */ + pReq->dma[0].pDmaLast->phyNextDescPtr = + MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); + pReq->dma[0].pDmaLast = NULL; + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) + { + /* For AUTH on decode : Check Digest result in Status register */ + statusReg = MV_REG_READ(MV_CESA_STATUS_REG); + if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) + { +/* + mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", + chan, statusReg); +*/ + /* Signiture verification is failed */ + pResult->retCode = MV_FAIL; + } + } + readyStatus = MV_OK; + } + + if(readyStatus == MV_OK) + { + /* If Request is ready - Prepare pResult structure */ + pResult->pReqPrv = pReq->pCmd->pReqPrv; + pResult->sessionId = pReq->pCmd->sessionId; + + pReq->state = MV_CESA_IDLE; + pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); + cesaReqResources++; + + if(pSA->ctrMode) + { + /* For AES CTR mode - complete processing and free allocated resources */ + mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); + mvCesaCtrModeFinish(pReq->pCmd); + pReq->pOrgCmd = NULL; + } + } + +#if (MV_CESA_VERSION < 3) + if(pCesaReqProcess->state == MV_CESA_PROCESS) + { + /* Start request Process */ + mvCesaReqProcessStart(pCesaReqProcess); + if(readyStatus == MV_NOT_READY) + readyStatus = MV_BUSY; + } + else if(pCesaReqProcess != pCesaReqEmpty) + { + /* Start process new request from the queue */ + mvCesaReqProcessStart(pCesaReqProcess); + } +#endif + return readyStatus; +} + +/***************** Functions to work with CESA_MBUF structure ******************/ + +/******************************************************************************* +* mvCesaMbufOffset - Locate offset in the Mbuf structure +* +* DESCRIPTION: +* This function locates offset inside Multi-Bufeer structure. +* It get fragment number and place in the fragment where the offset +* is located. +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure +* int offset - Offset from the beginning of the data presented by +* the Mbuf structure. +* +* OUTPUT: +* int* pBufOffset - Offset from the beginning of the fragment where +* the offset is located. +* +* RETURN: +* int - Number of fragment, where the offset is located\ +* +*******************************************************************************/ +int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) +{ + int frag = 0; + + while(offset > 0) + { + if(frag >= pMbuf->numFrags) + { + mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", + frag, pMbuf->numFrags); + return MV_INVALID; + } + if(offset < pMbuf->pFrags[frag].bufSize) + { + break; + } + offset -= pMbuf->pFrags[frag].bufSize; + frag++; + } + if(pBufOffset != NULL) + *pBufOffset = offset; + + return frag; +} + +/******************************************************************************* +* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer +* +* DESCRIPTION: +* +* +* INPUT: +* MV_U8* pDstBuf - Pointer to continuous buffer, where data is +* copied to. +* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is +* copied from. +* int offset - Offset in the Mbuf structure where located first +* byte of data should be copied. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. +* No data is copied. +* MV_EMPTY - Multi-buffer structure has not enough data to copy +* Data from the offset to end of Mbuf data is copied. +* +*******************************************************************************/ +MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, + int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8* pBuf; + + if(size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); + if(frag == MV_INVALID) + { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while(MV_TRUE) + { + if(size <= bufSize) + { + memcpy(pDstBuf, pBuf, size); + return MV_OK; + } + memcpy(pDstBuf, pBuf, bufSize); + size -= bufSize; + frag++; + pDstBuf += bufSize; + if(frag >= pSrcMbuf->numFrags) + break; + + bufSize = pSrcMbuf->pFrags[frag].bufSize; + pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", + size); + return MV_EMPTY; +} + +/******************************************************************************* +* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure +* +* DESCRIPTION: +* +* +* INPUT: +* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is +* copied from. +* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is +* copied to. +* int offset - Offset in the Mbuf structure where located first +* byte of data should be copied. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. +* No data is copied. +* MV_FULL - Multi-buffer structure has not enough place to copy +* all data. Data from the offset to end of Mbuf data +* is copied. +* +*******************************************************************************/ +MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, + int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8* pBuf; + + if(size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); + if(frag == MV_INVALID) + { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while(MV_TRUE) + { + if(size <= bufSize) + { + memcpy(pBuf, pSrcBuf, size); + return MV_OK; + } + memcpy(pBuf, pSrcBuf, bufSize); + size -= bufSize; + frag++; + pSrcBuf += bufSize; + if(frag >= pDstMbuf->numFrags) + break; + + bufSize = pDstMbuf->pFrags[frag].bufSize; + pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", + size); + return MV_FULL; +} + +/******************************************************************************* +* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure +* +* DESCRIPTION: +* +* +* INPUT: +* +* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is +* copied to. +* int dstMbufOffset - Offset in the dstMbuf structure where first byte +* of data should be copied to. +* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is +* copied from. +* int srcMbufOffset - Offset in the srcMbuf structure where first byte +* of data should be copied from. +* int size - Size of data should be copied +* +* RETURN: +* MV_OK - Success, all data is copied successfully. +* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of +* srcMbuf or dstMbuf structure correspondently. +* No data is copied. +* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy +* all data. Partial data is copied +* +*******************************************************************************/ +MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, + MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) +{ + int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; + int copySize; + MV_U8 *pSrc, *pDst; + + if(size == 0) + return MV_OK; + + srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); + if(srcFrag == MV_INVALID) + { + mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); + return MV_OUT_OF_RANGE; + } + pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; + srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; + + dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); + if(dstFrag == MV_INVALID) + { + mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); + return MV_OUT_OF_RANGE; + } + pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; + dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; + + while(size > 0) + { + copySize = MV_MIN(srcSize, dstSize); + if(size <= copySize) + { + memcpy(pDst, pSrc, size); + return MV_OK; + } + memcpy(pDst, pSrc, copySize); + size -= copySize; + srcSize -= copySize; + dstSize -= copySize; + + if(srcSize == 0) + { + srcFrag++; + if(srcFrag >= pMbufSrc->numFrags) + break; + + pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pMbufSrc->pFrags[srcFrag].bufSize; + } + + if(dstSize == 0) + { + dstFrag++; + if(dstFrag >= pMbufDst->numFrags) + break; + + pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pMbufDst->pFrags[dstFrag].bufSize; + } + } + mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", + size); + + return MV_BAD_SIZE; +} + +static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) +{ + int frag, fragOffset, bufSize; + MV_U8* pBuf; + + if(size == 0) + return MV_OK; + + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if(frag == MV_INVALID) + { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return MV_OUT_OF_RANGE; + } + + bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; + while(MV_TRUE) + { + if(size <= bufSize) + { + mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); + return MV_OK; + } + + mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); + size -= bufSize; + frag++; + if(frag >= pMbuf->numFrags) + break; + + bufSize = pMbuf->pFrags[frag].bufSize; + pBuf = pMbuf->pFrags[frag].bufVirtPtr; + } + mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", + __FUNCTION__, size); + return MV_FULL; +} + + +/*************************************** Local Functions ******************************/ + +/******************************************************************************* +* mvCesaFragReqProcess - Process fragmented request +* +* DESCRIPTION: +* This function processes a fragment of fragmented request (First, Middle or Last) +* +* +* INPUT: +* MV_CESA_REQ* pReq - Pointer to the request in the request queue. +* +* RETURN: +* MV_OK - The fragment is successfully passed to HW for processing. +* MV_TERMINATE - Means, that HW finished its work on this packet and no more +* interrupts will be generated for this request. +* Function mvCesaReadyGet() must be called to complete request +* processing and get request result. +* +*******************************************************************************/ +static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) +{ + int i, copySize, cryptoDataSize, macDataSize, sid; + int cryptoIvOffset, digestOffset; + MV_U32 config; + MV_CESA_COMMAND* pCmd = pReq->pCmd; + MV_CESA_SA* pSA; + MV_CESA_MBUF* pMbuf; + MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; + MV_U8* pSramBuf = cesaSramVirtPtr->buf; + int macTotalLen = 0; + int fixOffset, cryptoOffset, macOffset; + + cesaStats.fragCount++; + + sid = pReq->pCmd->sessionId; + + pSA = &pCesaSAD[sid]; + + cryptoIvOffset = digestOffset = 0; + i = macDataSize = 0; + cryptoDataSize = 0; + + /* First fragment processing */ + if(pReq->fragMode == MV_CESA_FRAG_FIRST) + { + /* pReq->frags monitors processing of fragmented request between fragments */ + pReq->frags.bufOffset = 0; + pReq->frags.cryptoSize = 0; + pReq->frags.macSize = 0; + + config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); + + /* fixOffset can be not equal to zero only for FIRST fragment */ + fixOffset = pReq->fixOffset; + /* For FIRST fragment crypto and mac offsets are taken from pCmd */ + cryptoOffset = pCmd->cryptoOffset; + macOffset = pCmd->macOffset; + + copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; + + /* Find fragment size: Must meet all requirements for CRYPTO and MAC + * cryptoDataSize - size of data will be encrypted/decrypted in this fragment + * macDataSize - size of data will be signed/verified in this fragment + * copySize - size of data will be copied from srcMbuf to SRAM and + * back to dstMbuf for this fragment + */ + mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, + ©Size, &cryptoDataSize, &macDataSize); + + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) + { + /* CryptoIV special processing */ + if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == + (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) + { + /* In CBC mode for encode direction when IV from user */ + if( (pCmd->ivFromUser) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) + { + + /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, + * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place + * in the buffer to SRAM IVPointer + */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + + /* Special processing when IV is not located in the first fragment */ + if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) + { + /* Prepare dummy place for cryptoIV in SRAM */ + cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); + + /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ + if((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) + { + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + else + { + /* For Encryption when IV is NOT from User: */ + /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ + if(pCmd->ivFromUser == 0) + { + /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + } + } + else + { + cryptoIvOffset = pCmd->ivOffset; + } + } + } + + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + /* MAC digest special processing on Decode direction */ + if((pSA->config & MV_CESA_DIRECTION_MASK) == + (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) + { + /* Save digest from pCmd->digestOffset */ + mvCesaCopyFromMbuf(pReq->frags.orgDigest, + pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); + + /* If pCmd->digestOffset is not located on the first */ + if(pCmd->digestOffset > (copySize - pSA->digestSize)) + { + MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; + + /* Set zeros to pCmd->digestOffset (DRAM) */ + memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); + mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); + + /* Prepare dummy place for digest in SRAM */ + digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + } + else + { + digestOffset = pCmd->digestOffset; + } + } + } + /* Update SA in SRAM */ + if(cesaLastSid != sid) + { + mvCesaSramSaUpdate(sid, &pDmaDesc[i]); + i++; + } + + pReq->fragMode = MV_CESA_FRAG_MIDDLE; + } + else + { + /* Continue fragment */ + fixOffset = 0; + cryptoOffset = 0; + macOffset = 0; + if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) + { + /* Last fragment */ + config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); + pReq->fragMode = MV_CESA_FRAG_LAST; + copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; + + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + macDataSize = pCmd->macLength - pReq->frags.macSize; + + /* If pCmd->digestOffset is not located on last fragment */ + if(pCmd->digestOffset < pReq->frags.bufOffset) + { + /* Prepare dummy place for digest in SRAM */ + digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + } + else + { + digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; + } + pReq->frags.newDigestOffset = digestOffset; + macTotalLen = pCmd->macLength; + + /* HW can't calculate the Digest correctly for fragmented packets + * in the following cases: + * - MV88F5182 || + * - MV88F5181L when total macLength more that 16 Kbytes || + * - total macLength more that 64 Kbytes + */ + if( (mvCtrlModelGet() == MV_5182_DEV_ID) || + ( (mvCtrlModelGet() == MV_5181_DEV_ID) && + (mvCtrlRevGet() >= MV_5181L_A0_REV) && + (pCmd->macLength >= (1 << 14)) ) ) + { + return MV_TERMINATE; + } + } + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; + } + + /* cryptoIvOffset - don't care */ + } + else + { + /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ + if( (mvCtrlModelGet() == MV_5182_DEV_ID) && + (((pSA->config & MV_CESA_MAC_MODE_MASK) == + (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || + ((pSA->config & MV_CESA_MAC_MODE_MASK) == + (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) + { + pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); + pReq->fragMode = MV_CESA_FRAG_LAST; + + return MV_TERMINATE; + } + /* Middle fragment */ + config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); + copySize = sizeof(cesaSramVirtPtr->buf); + /* digestOffset and cryptoIvOffset - don't care */ + + /* Find fragment size */ + mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, + ©Size, &cryptoDataSize, &macDataSize); + } + } + /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ + pMbuf = pCmd->pSrc; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); + + /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ + mvCesaSramDescrBuild(config, frag, + cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, + cryptoDataSize, macOffset + fixOffset, + digestOffset + fixOffset, macDataSize, macTotalLen, + pReq, &pDmaDesc[i]); + i++; + + /* Add special descriptor Ownership for CPU */ + pDmaDesc[i].byteCnt = 0; + pDmaDesc[i].phySrcAdd = 0; + pDmaDesc[i].phyDestAdd = 0; + i++; + + /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ + pMbuf = pCmd->pDst; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); + + /* Next field of Last DMA descriptor must be NULL */ + pDmaDesc[i-1].phyNextDescPtr = 0; + pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; + mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, + i*sizeof(MV_DMA_DESC)); + + /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ + + pReq->frags.bufOffset += copySize; + pReq->frags.cryptoSize += cryptoDataSize; + pReq->frags.macSize += macDataSize; + + return MV_OK; +} + + +/******************************************************************************* +* mvCesaReqProcess - Process regular (Non-fragmented) request +* +* DESCRIPTION: +* This function processes the whole (not fragmented) request +* +* INPUT: +* MV_CESA_REQ* pReq - Pointer to the request in the request queue. +* +* RETURN: +* MV_OK - The request is successfully passed to HW for processing. +* Other - Failure. The request will not be processed +* +*******************************************************************************/ +static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) +{ + MV_CESA_MBUF *pMbuf; + MV_DMA_DESC *pDmaDesc; + MV_U8 *pSramBuf; + int sid, i, fixOffset; + MV_CESA_SA *pSA; + MV_CESA_COMMAND *pCmd = pReq->pCmd; + + cesaStats.procCount++; + + sid = pCmd->sessionId; + pSA = &pCesaSAD[sid]; + pDmaDesc = pReq->dma[0].pDmaFirst; + pSramBuf = cesaSramVirtPtr->buf; + fixOffset = pReq->fixOffset; + +/* + mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", + sid, pSA, pDmaDesc, pSramBuf); +*/ + i = 0; + + /* Crypto IV Special processing in CBC mode for Encryption direction */ + if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && + ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && + ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && + (pCmd->ivFromUser) ) + { + /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, + * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place + * in the buffer to SRAM IVPointer + */ + i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], + MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); + } + + /* Update SA in SRAM */ + if(cesaLastSid != sid) + { + mvCesaSramSaUpdate(sid, &pDmaDesc[i]); + i++; + } + + /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ + pMbuf = pCmd->pSrc; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); + + /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ + mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, + pCmd->ivOffset + fixOffset, pCmd->cryptoLength, + pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, + pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); + i++; + + /* Add special descriptor Ownership for CPU */ + pDmaDesc[i].byteCnt = 0; + pDmaDesc[i].phySrcAdd = 0; + pDmaDesc[i].phyDestAdd = 0; + i++; + + /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ + pMbuf = pCmd->pDst; + i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], + MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); + + /* Next field of Last DMA descriptor must be NULL */ + pDmaDesc[i-1].phyNextDescPtr = 0; + pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; + mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); + + return MV_OK; +} + + +/******************************************************************************* +* mvCesaSramDescrBuild - Set CESA descriptor in SRAM +* +* DESCRIPTION: +* This function builds CESA descriptor in SRAM from all Command parameters +* +* +* INPUT: +* int chan - CESA channel uses the descriptor +* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure +* int cryptoOffset - Offset from the beginning of SRAM buffer where +* data for encryption/decription is started. +* int ivOffset - Offset of crypto IV from the SRAM base. Valid only +* for first fragment. +* int cryptoLength - Size (in bytes) of data for encryption/descryption +* operation on this fragment. +* int macOffset - Offset from the beginning of SRAM buffer where +* data for Authentication is started +* int digestOffset - Offset from the beginning of SRAM buffer where +* digest is located. Valid for first and last fragments. +* int macLength - Size (in bytes) of data for Authentication +* operation on this fragment. +* int macTotalLen - Toatl size (in bytes) of data for Authentication +* operation on the whole request (packet). Valid for +* last fragment only. +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaSramDescrBuild(MV_U32 config, int frag, + int cryptoOffset, int ivOffset, int cryptoLength, + int macOffset, int digestOffset, int macLength, + int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) +{ + MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; + MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; + MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); + + pCesaDesc->config = MV_32BIT_LE(config); + + if( (config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + /* word 1 */ + pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); + pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); + /* word 2 */ + pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); + /* word 3 */ + pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - + mvCesaSramAddrGet())); + /* word 4 */ + pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - + mvCesaSramAddrGet())); + pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); + } + + if( (config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + /* word 5 */ + pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); + pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); + + /* word 6 */ + pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); + pCesaDesc->macDataLen = MV_16BIT_LE(macLength); + + /* word 7 */ + pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - + mvCesaSramAddrGet())); + pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - + mvCesaSramAddrGet())); + } + /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ + pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); + pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); + pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); + + /* flush Source buffer */ + mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); +} + +/******************************************************************************* +* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. +* +* DESCRIPTION: +* Copy to SRAM values of the required SA. +* +* +* INPUT: +* short sid - Session ID needs SRAM Cache update +* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to +* copy SA values from DRAM to SRAM. +* +* RETURN: +* MV_OK - Cache entry for this SA copied to SRAM. +* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM +* +*******************************************************************************/ +static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) +{ + MV_CESA_SA *pSA = &pCesaSAD[sid]; + + /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ + pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); + pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); + pDmaDesc->phyDestAdd = + MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); + + /* Source buffer is already flushed during OpenSession*/ + /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ +} + +/******************************************************************************* +* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by +* Mbuf structure from DRAM to SRAM +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request +* data in DRAM +* MV_U8* pSramBuf - pointer to buffer in SRAM where data should +* be copied to. +* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. +* The function set number of DMA descriptors needed +* to copy the copySize bytes from Mbuf. +* MV_BOOL isToMbuf - Copy direction. +* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. +* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. +* int offset - Offset in the Mbuf structure that copy should be +* started from. +* int copySize - Size of data should be copied. +* +* RETURN: +* int - number of DMA descriptors used for the copy. +* +*******************************************************************************/ +#ifndef MV_NETBSD +static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, + MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush) +{ + int bufOffset, bufSize, size, frag, i; + MV_U8* pBuf; + + i = 0; + + /* Calculate start place for copy: fragment number and offset in the fragment */ + frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); + bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; + + /* Size accumulate total copy size */ + size = 0; + + /* Create DMA lists to copy mBuf from pSrc to SRAM */ + while(size < copySize) + { + /* Find copy size for each DMA descriptor */ + bufSize = MV_MIN(bufSize, (copySize - size)); + pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); + if(isToMbuf) + { + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + pDmaDesc[i].phySrcAdd = + MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); + /* invalidate the buffer */ + if(skipFlush == MV_FALSE) + mvOsCacheInvalidate(NULL, pBuf, bufSize); + } + else + { + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + pDmaDesc[i].phyDestAdd = + MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); + /* flush the buffer */ + if(skipFlush == MV_FALSE) + mvOsCacheFlush(NULL, pBuf, bufSize); + } + + /* Count number of used DMA descriptors */ + i++; + size += bufSize; + + /* go to next fragment in the Mbuf */ + frag++; + pBuf = pMbuf->pFrags[frag].bufVirtPtr; + bufSize = pMbuf->pFrags[frag].bufSize; + } + return i; +} +#else /* MV_NETBSD */ +static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, + MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, + int offset, int copySize, MV_BOOL skipFlush) +{ + int bufOffset, bufSize, thisSize, size, frag, i; + MV_ULONG bufPhys, sramPhys; + MV_U8* pBuf; + + /* + * Calculate start place for copy: fragment number and offset in + * the fragment + */ + frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); + + /* + * Get SRAM physical address only once. We can update it in-place + * as we build the descriptor chain. + */ + sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); + + /* + * 'size' accumulates total copy size, 'i' counts desccriptors. + */ + size = i = 0; + + /* Create DMA lists to copy mBuf from pSrc to SRAM */ + while (size < copySize) { + /* + * Calculate # of bytes to copy from the current fragment, + * and the pointer to the start of data + */ + bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; + pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; + bufOffset = 0; /* First frag may be non-zero */ + frag++; + + /* + * As long as there is data in the current fragment... + */ + while (bufSize > 0) { + /* + * Ensure we don't cross an MMU page boundary. + * XXX: This is NetBSD-specific, but it is a + * quick and dirty way to fix the problem. + * A true HAL would rely on the OS-specific + * driver to do this... + */ + thisSize = PAGE_SIZE - + (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); + thisSize = MV_MIN(bufSize, thisSize); + /* + * Make sure we don't copy more than requested + */ + if (thisSize > (copySize - size)) { + thisSize = copySize - size; + bufSize = 0; + } + + /* + * Physicall address of this fragment + */ + bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); + + /* + * Set up the descriptor + */ + pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); + if(isToMbuf) { + pDmaDesc[i].phyDestAdd = bufPhys; + pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); + /* invalidate the buffer */ + if(skipFlush == MV_FALSE) + mvOsCacheInvalidate(NULL, pBuf, thisSize); + } else { + pDmaDesc[i].phySrcAdd = bufPhys; + pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); + /* flush the buffer */ + if(skipFlush == MV_FALSE) + mvOsCacheFlush(NULL, pBuf, thisSize); + } + + pDmaDesc[i].phyNextDescPtr = + MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); + + /* flush the DMA desc */ + mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); + + /* Update state */ + bufSize -= thisSize; + sramPhys += thisSize; + pBuf += thisSize; + size += thisSize; + i++; + } + } + + return i; +} +#endif /* MV_NETBSD */ +/******************************************************************************* +* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key +* +* DESCRIPTION: +* This function calculate Inner and Outer values used for HMAC algorithm. +* This operation allows improve performance fro the whole HMAC processing. +* +* INPUT: +* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. +* unsigned char key[] - Pointer to HMAC key. +* int keyLength - Size of HMAC key (maximum 64 bytes) +* +* OUTPUT: +* unsigned char innerIV[] - HASH(key^inner) +* unsigned char outerIV[] - HASH(key^outter) +* +* RETURN: None +* +*******************************************************************************/ +static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, + unsigned char innerIV[], unsigned char outerIV[]) +{ + unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; + unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; + int i, digestSize = 0; +#if defined(MV_CPU_LE) || defined(MV_PPC) + MV_U32 swapped32, val32, *pVal32; +#endif + for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; + size = pMbuf->pFrags[frag].bufSize - fragOffset; + + /* Complete Inner part */ + while(macLeftSize > 0) + { + if(macLeftSize <= size) + { + mvSHA1Update(&ctx, pData, macLeftSize); + break; + } + mvSHA1Update(&ctx, pData, size); + macLeftSize -= size; + frag++; + pData = pMbuf->pFrags[frag].bufVirtPtr; + size = pMbuf->pFrags[frag].bufSize; + } + mvSHA1Final(pDigest, &ctx); +/* + mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", + pOuterIV, macLeftSize, macTotalSize); + mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); +*/ + + if(pOuterIV != NULL) + { + /* If HMAC - Complete Outer part */ + for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; + size = pMbuf->pFrags[frag].bufSize - fragOffset; + + /* Complete Inner part */ + while(macLeftSize > 0) + { + if(macLeftSize <= size) + { + mvMD5Update(&ctx, pData, macLeftSize); + break; + } + mvMD5Update(&ctx, pData, size); + macLeftSize -= size; + frag++; + pData = pMbuf->pFrags[frag].bufVirtPtr; + size = pMbuf->pFrags[frag].bufSize; + } + mvMD5Final(pDigest, &ctx); + +/* + mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", + pOuterIV, macLeftSize, macTotalSize); + mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); +*/ + if(pOuterIV != NULL) + { + /* Complete Outer part */ + for(i=0; ipCmd; + MV_U8* pDigest; + MV_CESA_MAC_MODE macMode; + MV_U8* pOuterIV = NULL; + + /* Copy data from Source fragment to Destination */ + if(pCmd->pSrc != pCmd->pDst) + { + mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, + pCmd->pSrc, pReq->frags.bufOffset, macDataSize); + } + +/* + mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); + mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); +*/ + pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); + + macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; +/* + mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", + macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); +*/ + switch(macMode) + { + case MV_CESA_MAC_HMAC_MD5: + pOuterIV = pSA->pSramSA->macOuterIV; + + case MV_CESA_MAC_MD5: + mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, + macDataSize, pCmd->macLength, pDigest); + break; + + case MV_CESA_MAC_HMAC_SHA1: + pOuterIV = pSA->pSramSA->macOuterIV; + + case MV_CESA_MAC_SHA1: + mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, + macDataSize, pCmd->macLength, pDigest); + break; + + default: + mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); + return MV_BAD_PARAM; + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeInit - +* +* DESCRIPTION: +* +* +* INPUT: NONE +* +* +* RETURN: +* MV_CESA_COMMAND* +* +*******************************************************************************/ +static MV_CESA_COMMAND* mvCesaCtrModeInit(void) +{ + MV_CESA_MBUF *pMbuf; + MV_U8 *pBuf; + MV_CESA_COMMAND *pCmd; + + pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); + if(pBuf == NULL) + { + mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", + sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); + return NULL; + } + pCmd = (MV_CESA_COMMAND*)pBuf; + pBuf += sizeof(MV_CESA_COMMAND); + + pMbuf = (MV_CESA_MBUF*)pBuf; + pBuf += sizeof(MV_CESA_MBUF); + + pMbuf->pFrags = (MV_BUF_INFO*)pBuf; + + pMbuf->numFrags = 1; + pCmd->pSrc = pMbuf; + pCmd->pDst = pMbuf; +/* + mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", + pCmd, pCmd->pSrc, pCmd->pDst, + pMbuf->pFrags); +*/ + return pCmd; +} + +/******************************************************************************* +* mvCesaCtrModePrepare - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) +{ + MV_CESA_MBUF *pMbuf; + MV_U8 *pBuf, *pIV; + MV_U32 counter, *pCounter; + int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); +/* + mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", + pCmd, pCmd->pSrc, pCmd->pDst, + pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); +*/ + pMbuf = pCtrModeCmd->pSrc; + + /* Allocate buffer for Key stream */ + pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, + &pMbuf->pFrags[0].bufPhysAddr, + &pMbuf->pFrags[0].memHandle); + if(pBuf == NULL) + { + mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); + return MV_OUT_OF_CPU_MEM; + } + memset(pBuf, 0, cryptoSize); + mvOsCacheFlush(NULL, pBuf, cryptoSize); + + pMbuf->pFrags[0].bufVirtPtr = pBuf; + pMbuf->mbufSize = cryptoSize; + pMbuf->pFrags[0].bufSize = cryptoSize; + + pCtrModeCmd->pReqPrv = pCmd->pReqPrv; + pCtrModeCmd->sessionId = pCmd->sessionId; + + /* ivFromUser and ivOffset are don't care */ + pCtrModeCmd->cryptoOffset = 0; + pCtrModeCmd->cryptoLength = cryptoSize; + + /* digestOffset, macOffset and macLength are don't care */ + + mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); + pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); + counter = *pCounter; + counter = MV_32BIT_BE(counter); + pIV = pBuf; + cryptoSize -= MV_CESA_AES_BLOCK_SIZE; + + /* fill key stream */ + while(cryptoSize > 0) + { + pBuf += MV_CESA_AES_BLOCK_SIZE; + memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); + pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); + counter++; + *pCounter = MV_32BIT_BE(counter); + cryptoSize -= MV_CESA_AES_BLOCK_SIZE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeComplete - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) +{ + int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; + int cryptoSize = pCmd->cryptoLength; + MV_U8 *pSrc, *pDst, *pKey; + MV_STATUS status = MV_OK; +/* + mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", + pCmd, pCmd->pSrc, pCmd->pDst, + pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); +*/ + /* XOR source data with key stream to destination data */ + pKey = pCmd->pDst->pFrags[0].bufVirtPtr; + keyOffset = 0; + + if( (pOrgCmd->pSrc != pOrgCmd->pDst) && + (pOrgCmd->cryptoOffset > 0) ) + { + /* Copy Prefix from source buffer to destination buffer */ + + status = mvCesaMbufCopy(pOrgCmd->pDst, 0, + pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); +/* + status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, + 0, pOrgCmd->cryptoOffset); + status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, + 0, pOrgCmd->cryptoOffset); +*/ + } + + srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); + pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; + + dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); + pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; + + while(cryptoSize > 0) + { + pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); + + cryptoSize--; + dstOffset++; + srcOffset++; + keyOffset++; + + if(srcOffset >= srcSize) + { + srcFrag++; + srcOffset = 0; + pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; + srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; + } + + if(dstOffset >= dstSize) + { + dstFrag++; + dstOffset = 0; + pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; + dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; + } + } + + if(pOrgCmd->pSrc != pOrgCmd->pDst) + { + /* Copy Suffix from source buffer to destination buffer */ + srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; + + if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) + { + status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, + pOrgCmd->pSrc, srcOffset, + pOrgCmd->pDst->mbufSize - srcOffset); + } + +/* + status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, + srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); + status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, + srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); +*/ + } + + /* Free buffer used for Key stream */ + mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, + pCmd->pDst->pFrags[0].bufPhysAddr, + pCmd->pDst->pFrags[0].bufVirtPtr, + pCmd->pDst->pFrags[0].memHandle); + + return MV_OK; +} + +/******************************************************************************* +* mvCesaCtrModeFinish - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_COMMAND* pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) +{ + mvOsFree(pCmd); +} + +/******************************************************************************* +* mvCesaParamCheck - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, + MV_U8* pFixOffset) +{ + MV_U8 fixOffset = 0xFF; + + /* Check AUTH operation parameters */ + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) + { + /* MAC offset should be at least 4 byte aligned */ + if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) + { + mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", + pCmd->macOffset); + return MV_BAD_PARAM; + } + /* Digest offset must be 4 byte aligned */ + if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) + { + mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", + pCmd->digestOffset); + return MV_BAD_PARAM; + } + /* In addition all offsets should be the same alignment: 8 or 4 */ + if(fixOffset == 0xFF) + { + fixOffset = (pCmd->macOffset % 8); + } + else + { + if( (pCmd->macOffset % 8) != fixOffset) + { + mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", + pCmd->macOffset, fixOffset); + return MV_BAD_PARAM; + } + } + if( (pCmd->digestOffset % 8) != fixOffset) + { + mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", + pCmd->digestOffset, fixOffset); + return MV_BAD_PARAM; + } + } + /* Check CRYPTO operation parameters */ + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) + { + /* CryptoOffset should be at least 4 byte aligned */ + if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) + { + mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", + pCmd->cryptoOffset); + return MV_BAD_PARAM; + } + /* cryptoLength should be the whole number of blocks */ + if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) + { + mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", + pCmd->cryptoLength, pSA->cryptoBlockSize); + return MV_BAD_PARAM; + } + if(fixOffset == 0xFF) + { + fixOffset = (pCmd->cryptoOffset % 8); + } + else + { + /* In addition all offsets should be the same alignment: 8 or 4 */ + if( (pCmd->cryptoOffset % 8) != fixOffset) + { + mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", + pCmd->cryptoOffset, fixOffset); + return MV_BAD_PARAM; + } + } + + /* check for CBC mode */ + if(pSA->cryptoIvSize > 0) + { + /* cryptoIV must not be part of CryptoLength */ + if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && + (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) + { + mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", + pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); + return MV_BAD_PARAM; + } + + /* ivOffset must be 4 byte aligned */ + if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) + { + mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", + pCmd->ivOffset); + return MV_BAD_PARAM; + } + /* In addition all offsets should be the same alignment: 8 or 4 */ + if( (pCmd->ivOffset % 8) != fixOffset) + { + mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", + pCmd->ivOffset, fixOffset); + return MV_BAD_PARAM; + } + } + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaFragParamCheck - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) +{ + int offset; + + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) + { + /* macOffset must be less that SRAM buffer size */ + if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) + { + mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", + pCmd->macOffset); + return MV_BAD_PARAM; + } + /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ + if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || + ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= + sizeof(cesaSramVirtPtr->buf)) ) + { + mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", + pCmd->macLength, pCmd->pSrc->mbufSize); + return MV_BAD_PARAM; + } + } + + if( ((pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) + { + /* cryptoOffset must be less that SRAM buffer size */ + /* 4 for possible fixOffset */ + if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) + { + mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", + pCmd->cryptoOffset); + return MV_BAD_PARAM; + } + + /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ + if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || + ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= + (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) + { + mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", + pCmd->cryptoLength, pCmd->pSrc->mbufSize); + return MV_BAD_PARAM; + } + } + + /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ + if( ((pSA->config & MV_CESA_OPERATION_MASK) == + (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || + ((pSA->config & MV_CESA_OPERATION_MASK) == + (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) + { + if( (mvCtrlModelGet() == MV_5182_DEV_ID) || + ( (mvCtrlModelGet() == MV_5181_DEV_ID) && + (mvCtrlRevGet() >= MV_5181L_A0_REV) && + (pCmd->macLength >= (1 << 14)) ) ) + { + return MV_NOT_ALLOWED; + } + + /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ + if(pCmd->cryptoOffset > pCmd->macOffset) + { + offset = pCmd->cryptoOffset - pCmd->macOffset; + } + else + { + offset = pCmd->macOffset - pCmd->cryptoOffset; + } + + if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) + { +/* + mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", + pSA->cryptoBlockSize); +*/ + return MV_NOT_ALLOWED; + } + /* Digest must not be part of CryptoLength */ + if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && + (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) + { +/* + mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", + pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); +*/ + return MV_NOT_ALLOWED; + } + } + return MV_OK; +} + +/******************************************************************************* +* mvCesaFragSizeFind - +* +* DESCRIPTION: +* +* +* INPUT: +* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, +* int cryptoOffset, int macOffset, +* +* OUTPUT: +* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize +* +* RETURN: +* MV_STATUS +* +*******************************************************************************/ +static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, + int cryptoOffset, int macOffset, + int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) +{ + MV_CESA_COMMAND *pCmd = pReq->pCmd; + int cryptoDataSize, macDataSize, copySize; + + cryptoDataSize = macDataSize = 0; + copySize = *pCopySize; + + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + cryptoDataSize = MV_MIN( (copySize - cryptoOffset), + (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); + + /* cryptoSize for each fragment must be the whole number of blocksSize */ + if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) + { + cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); + copySize = cryptoOffset + cryptoDataSize; + } + } + if( (pSA->config & MV_CESA_OPERATION_MASK) != + (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) + { + macDataSize = MV_MIN( (copySize - macOffset), + (pCmd->macLength - (pReq->frags.macSize + 1))); + + /* macSize for each fragment (except last) must be the whole number of blocksSize */ + if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) + { + macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); + copySize = macOffset + macDataSize; + } + cryptoDataSize = copySize - cryptoOffset; + } + *pCopySize = copySize; + + if(pCryptoDataSize != NULL) + *pCryptoDataSize = cryptoDataSize; + + if(pMacDataSize != NULL) + *pMacDataSize = macDataSize; +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesa.h b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesa.h new file mode 100644 index 0000000..c0abc9b --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesa.h @@ -0,0 +1,412 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration for +* the Marvell Cryptographic Engines and Security Accelerator. +* +*******************************************************************************/ + +#ifndef __mvCesa_h__ +#define __mvCesa_h__ + +#include "mvOs.h" +#include "mvCommon.h" +#include "mvDebug.h" + +#include "ctrlEnv/mvCtrlEnvSpec.h" + +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" + +#include "cesa/mvCesa.h" +#include "cesa/AES/mvAes.h" +#include "mvSysHwConfig.h" + +#ifdef MV_INCLUDE_IDMA +#include "idma/mvIdma.h" +#include "idma/mvIdmaRegs.h" +#else +/* Redefine MV_DMA_DESC structure */ +typedef struct _mvDmaDesc +{ + MV_U32 byteCnt; /* The total number of bytes to transfer */ + MV_U32 phySrcAdd; /* The physical source address */ + MV_U32 phyDestAdd; /* The physical destination address */ + MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ + /* then this pointer should point to the */ + /* physical address of the next descriptor, */ + /* otherwise it should be NULL. */ +}MV_DMA_DESC; +#endif /* MV_INCLUDE_IDMA */ + +#include "cesa/mvCesaRegs.h" + +#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ + +#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ +#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ + +#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE + +#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ +#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ +#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ +#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ +#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ + +#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH + +#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ +#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ + +#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ + +#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE + +#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ + +typedef struct +{ + MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; + MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; + MV_CESA_OPERATION operation; + MV_CESA_DIRECTION direction; + MV_CESA_CRYPTO_ALG cryptoAlgorithm; + MV_CESA_CRYPTO_MODE cryptoMode; + MV_U8 cryptoKeyLength; + MV_CESA_MAC_MODE macMode; + MV_U8 macKeyLength; + MV_U8 digestSize; + +} MV_CESA_OPEN_SESSION; + +typedef struct +{ + MV_BUF_INFO *pFrags; + MV_U16 numFrags; + MV_U16 mbufSize; + +} MV_CESA_MBUF; + +typedef struct +{ + void* pReqPrv; /* instead of reqId */ + MV_U32 retCode; + MV_16 sessionId; + +} MV_CESA_RESULT; + +typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); + + +typedef struct +{ + void* pReqPrv; /* instead of reqId */ + MV_CESA_MBUF* pSrc; + MV_CESA_MBUF* pDst; + MV_CESA_CALLBACK* pFuncCB; + MV_16 sessionId; + MV_U16 ivFromUser; + MV_U16 ivOffset; + MV_U16 cryptoOffset; + MV_U16 cryptoLength; + MV_U16 digestOffset; + MV_U16 macOffset; + MV_U16 macLength; + MV_BOOL skipFlush; +} MV_CESA_COMMAND; + + + +MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); +MV_STATUS mvCesaFinish (void); +MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); +MV_STATUS mvCesaSessionClose(short sid); +MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); + +MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); + +MV_U32 mvCesaInProcessGet(void); +MV_STATUS mvCesaReadyDispatch(void); +MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); +MV_BOOL mvCesaIsReady(void); + +int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); +MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, + int offset, int size); +MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, + int offset, int size); +MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, + MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); + +/********** Debug functions ********/ + +void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); +void mvCesaDebugSA(short sid, int mode); +void mvCesaDebugStats(void); +void mvCesaDebugStatsClear(void); +void mvCesaDebugRegs(void); +void mvCesaDebugStatus(void); +void mvCesaDebugQueue(int mode); +void mvCesaDebugSram(int mode); +void mvCesaDebugSAD(int mode); + + +/******** CESA Private definitions ********/ +#if (MV_CESA_VERSION >= 2) +#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) +#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ + | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ + | MV_CESA_TDMA_ENABLE_MASK +#else +#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ + | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ + /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ + | MV_CESA_TDMA_ENABLE_MASK + +#endif +#else +#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ + | ICCLR_SRC_BURST_LIM_128BYTE \ + | ICCLR_INT_MODE_MASK \ + | ICCLR_BLOCK_MODE \ + | ICCLR_CHAN_ENABLE \ + | ICCLR_DESC_MODE_16M +#endif /* MV_CESA_VERSION >= 2 */ + +#define MV_CESA_MAX_PKT_SIZE (64 * 1024) +#define MV_CESA_MAX_MBUF_FRAGS 20 + +#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) + +#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) + +#define MAX_CESA_CHAIN_LENGTH 20 + +typedef enum +{ + MV_CESA_IDLE = 0, + MV_CESA_PENDING, + MV_CESA_PROCESS, + MV_CESA_READY, +#if (MV_CESA_VERSION >= 3) + MV_CESA_CHAIN, +#endif +} MV_CESA_STATE; + + +/* Session database */ + +/* Map of Key materials of the session in SRAM. + * Each field must be 8 byte aligned + * Total size: 32 + 24 + 24 = 80 bytes + */ +typedef struct +{ + MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; + MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; + MV_U8 reservedInner[4]; + MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; + MV_U8 reservedOuter[4]; + +} MV_CESA_SRAM_SA; + +typedef struct +{ + MV_CESA_SRAM_SA* pSramSA; + MV_U32 config; + MV_U8 cryptoKeyLength; + MV_U8 cryptoIvSize; + MV_U8 cryptoBlockSize; + MV_U8 digestSize; + MV_U8 macKeyLength; + MV_U8 valid; + MV_U8 ctrMode; + MV_U32 count; + +} MV_CESA_SA; + +/* DMA list management */ +typedef struct +{ + MV_DMA_DESC* pDmaFirst; + MV_DMA_DESC* pDmaLast; + +} MV_CESA_DMA; + + +typedef struct +{ + MV_U8 numFrag; + MV_U8 nextFrag; + int bufOffset; + int cryptoSize; + int macSize; + int newDigestOffset; + MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; + +} MV_CESA_FRAGS; + +/* Request queue */ +typedef struct +{ + MV_U8 state; + MV_U8 fragMode; + MV_U8 fixOffset; + MV_CESA_COMMAND* pCmd; + MV_CESA_COMMAND* pOrgCmd; + MV_BUF_INFO dmaDescBuf; + MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; + MV_BUF_INFO cesaDescBuf; + MV_CESA_DESC* pCesaDesc; + MV_CESA_FRAGS frags; + + +} MV_CESA_REQ; + + +/* SRAM map */ +/* Total SRAM size calculation */ +/* SRAM size = + * MV_CESA_MAX_BUF_SIZE + + * sizeof(MV_CESA_DESC) + + * MV_CESA_MAX_IV_LENGTH + + * MV_CESA_MAX_IV_LENGTH + + * MV_CESA_MAX_DIGEST_SIZE + + * sizeof(MV_CESA_SRAM_SA) + * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes + * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes + */ +typedef struct +{ + MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; + MV_CESA_DESC desc; + MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; + MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; + MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; + MV_CESA_SRAM_SA sramSA; + +} MV_CESA_SRAM_MAP; + + +typedef struct +{ + MV_U32 openedCount; + MV_U32 closedCount; + MV_U32 fragCount; + MV_U32 reqCount; + MV_U32 maxReqCount; + MV_U32 procCount; + MV_U32 readyCount; + MV_U32 notReadyCount; + MV_U32 startCount; +#if (MV_CESA_VERSION >= 3) + MV_U32 maxChainUsage; +#endif + +} MV_CESA_STATS; + + +/* External variables */ + +extern MV_CESA_STATS cesaStats; +extern MV_CESA_FRAGS cesaFrags; + +extern MV_BUF_INFO cesaSramSaBuf; + +extern MV_CESA_SA* pCesaSAD; +extern MV_U16 cesaMaxSA; + +extern MV_CESA_REQ* pCesaReqFirst; +extern MV_CESA_REQ* pCesaReqLast; +extern MV_CESA_REQ* pCesaReqEmpty; +extern MV_CESA_REQ* pCesaReqProcess; +extern int cesaQueueDepth; +extern int cesaReqResources; +#if (MV_CESA_VERSION>= 3) +extern MV_U32 cesaChainLength; +#endif + +extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; +extern MV_U32 cesaSramPhysAddr; + +static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) +{ + return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); +} + +/* Additional DEBUG functions */ +void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); +void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); +void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); + + + +#endif /* __mvCesa_h__ */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaDebug.c b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaDebug.c new file mode 100644 index 0000000..31b78a8 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaDebug.c @@ -0,0 +1,484 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvDebug.h" + +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" + +#include "cesa/mvCesa.h" +#include "cesa/mvCesaRegs.h" +#include "cesa/AES/mvAes.h" + +static const char* mvCesaDebugStateStr(MV_CESA_STATE state) +{ + switch(state) + { + case MV_CESA_IDLE: + return "Idle"; + + case MV_CESA_PENDING: + return "Pend"; + + case MV_CESA_PROCESS: + return "Proc"; + + case MV_CESA_READY: + return "Ready"; + + default: + break; + } + return "Unknown"; +} + +static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) +{ + switch(oper) + { + case MV_CESA_MAC_ONLY: + return "MacOnly"; + + case MV_CESA_CRYPTO_ONLY: + return "CryptoOnly"; + + case MV_CESA_MAC_THEN_CRYPTO: + return "MacCrypto"; + + case MV_CESA_CRYPTO_THEN_MAC: + return "CryptoMac"; + + default: + break; + } + return "Null"; +} + +static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) +{ + switch(cryptoAlg) + { + case MV_CESA_CRYPTO_DES: + return "DES"; + + case MV_CESA_CRYPTO_3DES: + return "3DES"; + + case MV_CESA_CRYPTO_AES: + return "AES"; + + default: + break; + } + return "Null"; +} + +static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) +{ + switch(macMode) + { + case MV_CESA_MAC_MD5: + return "MD5"; + + case MV_CESA_MAC_SHA1: + return "SHA1"; + + case MV_CESA_MAC_HMAC_MD5: + return "HMAC-MD5"; + + case MV_CESA_MAC_HMAC_SHA1: + return "HMAC_SHA1"; + + default: + break; + } + return "Null"; +} + +void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) +{ + mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", + pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, + pCmd->pFuncCB, pCmd->sessionId); + mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", + pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, + pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); +} + +/* no need to use in tool */ +void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) +{ + int frag, len, fragOffset; + + if(str != NULL) + mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", + str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); + + frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); + if(frag == MV_INVALID) + { + mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); + return; + } + + for(; fragnumFrags; frag++) + { + mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", + frag, pMbuf->pFrags[frag].bufVirtPtr, + pMbuf->pFrags[frag].bufSize); + if(size > 0) + { + len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); + mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); + size -= len; + fragOffset = 0; + } + } +} + +void mvCesaDebugRegs(void) +{ + mvOsPrintf("\t CESA Registers:\n"); + + mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", + MV_CESA_CMD_REG, + MV_REG_READ( MV_CESA_CMD_REG ) ); + + mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", + MV_CESA_CHAN_DESC_OFFSET_REG, + MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); + + mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", + MV_CESA_CFG_REG, + MV_REG_READ( MV_CESA_CFG_REG ) ); + + mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", + MV_CESA_STATUS_REG, + MV_REG_READ( MV_CESA_STATUS_REG ) ); + + mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", + MV_CESA_ISR_CAUSE_REG, + MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); + + mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", + MV_CESA_ISR_MASK_REG, + MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); +#if (MV_CESA_VERSION >= 2) + mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_CTRL_REG, + MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_BYTE_COUNT_REG, + MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_SRC_ADDR_REG, + MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_DST_ADDR_REG, + MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_NEXT_DESC_PTR_REG, + MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_CURR_DESC_PTR_REG, + MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_ERROR_CAUSE_REG, + MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); + + mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", + MV_CESA_TDMA_ERROR_MASK_REG, + MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); + +#endif +} + +void mvCesaDebugStatus(void) +{ + mvOsPrintf("\n\t CESA Status\n\n"); + + mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", + pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), + cesaReqResources); +#if (MV_CESA_VERSION >= 3) + mvOsPrintf("chainLength=%u\n",cesaChainLength); +#else + mvOsPrintf("\n"); +#endif + + mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", + pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); + + mvOsPrintf("\n"); + + mvCesaDebugRegs(); + mvCesaDebugStats(); + mvCesaDebugStatsClear(); +} + +void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) +{ + mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", + pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); + + mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", + pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, + pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); + + mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", + pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, + pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); +} + +void mvCesaDebugQueue(int mode) +{ + mvOsPrintf("\n\t CESA Request Queue:\n\n"); + + mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", + pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); + + mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", + pCesaReqEmpty, pCesaReqProcess, + cesaReqResources); + + if(mode != 0) + { + int count = 0; + MV_CESA_REQ* pReq = pCesaReqFirst; + + for(count=0; countstate), + pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); + if(pReq->fragMode != MV_CESA_FRAG_NONE) + { + int frag; + + mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", + &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, + pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); + for(frag=0; fragfrags.numFrag; frag++) + { + mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, + pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); + } + } + if(mode > 1) + { + /* Print out Command */ + mvCesaDebugCmd(pReq->pCmd, mode); + + /* Print out Descriptor */ + mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); + } + pReq++; + } + } +} + + +void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) +{ + if(pSramSA == NULL) + { + mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); + return; + } + mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", + pSramSA, sizeof(MV_CESA_SRAM_SA)); + + if(mode != 0) + { + mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", + pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); + mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); + + mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", + pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); + mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); + + mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", + pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); + mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); + } +} + +void mvCesaDebugSA(short sid, int mode) +{ + MV_CESA_OPERATION oper; + MV_CESA_DIRECTION dir; + MV_CESA_CRYPTO_ALG cryptoAlg; + MV_CESA_CRYPTO_MODE cryptoMode; + MV_CESA_MAC_MODE macMode; + MV_CESA_SA* pSA = &pCesaSAD[sid]; + + if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) + { + mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", + sid, pSA, + pSA->valid ? "Valid" : "Invalid", pSA->count); + + oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; + dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; + mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), + (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); + if(oper != MV_CESA_MAC_ONLY) + { + cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; + cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; + mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), + (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); + } + if(oper != MV_CESA_CRYPTO_ONLY) + { + macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; + mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); + } + mvOsPrintf("\n"); + + if(mode > 0) + { + mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", + pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, + pCesaSAD[sid].digestSize); + + mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); + } + } +} + + +/**/ +void mvCesaDebugSram(int mode) +{ + mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", + sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); + + mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", + MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); + if(mode != 0) + mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); + + mvOsPrintf("\n"); + mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", + sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); + if(mode != 0) + { + mvOsPrintf("\n"); + mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); + } + mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", + MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); + if(mode != 0) + { + mvOsPrintf("\n"); + mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); + } + mvOsPrintf("\n"); + mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); +} + +void mvCesaDebugSAD(int mode) +{ + int sid; + + mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", + pCesaSAD, cesaMaxSA); + + for(sid=0; sid= 3) + mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); +#endif + mvOsPrintf("\n"); + mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", + cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); +} + +void mvCesaDebugStatsClear(void) +{ + memset(&cesaStats, 0, sizeof(cesaStats)); +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaRegs.h new file mode 100644 index 0000000..6b7ce12 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvCesaRegs.h @@ -0,0 +1,357 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvCesaRegs_h__ +#define __mvCesaRegs_h__ + +#include "mvTypes.h" + +typedef struct +{ + /* word 0 */ + MV_U32 config; + /* word 1 */ + MV_U16 cryptoSrcOffset; + MV_U16 cryptoDstOffset; + /* word 2 */ + MV_U16 cryptoDataLen; + MV_U16 reserved1; + /* word 3 */ + MV_U16 cryptoKeyOffset; + MV_U16 reserved2; + /* word 4 */ + MV_U16 cryptoIvOffset; + MV_U16 cryptoIvBufOffset; + /* word 5 */ + MV_U16 macSrcOffset; + MV_U16 macTotalLen; + /* word 6 */ + MV_U16 macDigestOffset; + MV_U16 macDataLen; + /* word 7 */ + MV_U16 macInnerIvOffset; + MV_U16 macOuterIvOffset; + +} MV_CESA_DESC; + +/* operation */ +typedef enum +{ + MV_CESA_MAC_ONLY = 0, + MV_CESA_CRYPTO_ONLY = 1, + MV_CESA_MAC_THEN_CRYPTO = 2, + MV_CESA_CRYPTO_THEN_MAC = 3, + + MV_CESA_MAX_OPERATION + +} MV_CESA_OPERATION; + +#define MV_CESA_OPERATION_OFFSET 0 +#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) + +/* mac algorithm */ +typedef enum +{ + MV_CESA_MAC_NULL = 0, + MV_CESA_MAC_MD5 = 4, + MV_CESA_MAC_SHA1 = 5, + MV_CESA_MAC_HMAC_MD5 = 6, + MV_CESA_MAC_HMAC_SHA1 = 7, + +} MV_CESA_MAC_MODE; + +#define MV_CESA_MAC_MODE_OFFSET 4 +#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) + +typedef enum +{ + MV_CESA_MAC_DIGEST_FULL = 0, + MV_CESA_MAC_DIGEST_96B = 1, + +} MV_CESA_MAC_DIGEST_SIZE; + +#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 +#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) + + +typedef enum +{ + MV_CESA_CRYPTO_NULL = 0, + MV_CESA_CRYPTO_DES = 1, + MV_CESA_CRYPTO_3DES = 2, + MV_CESA_CRYPTO_AES = 3, + +} MV_CESA_CRYPTO_ALG; + +#define MV_CESA_CRYPTO_ALG_OFFSET 8 +#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) + + +/* direction */ +typedef enum +{ + MV_CESA_DIR_ENCODE = 0, + MV_CESA_DIR_DECODE = 1, + +} MV_CESA_DIRECTION; + +#define MV_CESA_DIRECTION_BIT 12 +#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) + +/* crypto IV mode */ +typedef enum +{ + MV_CESA_CRYPTO_ECB = 0, + MV_CESA_CRYPTO_CBC = 1, + + /* NO HW Support */ + MV_CESA_CRYPTO_CTR = 10, + +} MV_CESA_CRYPTO_MODE; + +#define MV_CESA_CRYPTO_MODE_BIT 16 +#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) + +/* 3DES mode */ +typedef enum +{ + MV_CESA_CRYPTO_3DES_EEE = 0, + MV_CESA_CRYPTO_3DES_EDE = 1, + +} MV_CESA_CRYPTO_3DES_MODE; + +#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 +#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) + + +/* AES Key Length */ +typedef enum +{ + MV_CESA_CRYPTO_AES_KEY_128 = 0, + MV_CESA_CRYPTO_AES_KEY_192 = 1, + MV_CESA_CRYPTO_AES_KEY_256 = 2, + +} MV_CESA_CRYPTO_AES_KEY_LEN; + +#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 +#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) + +/* Fragmentation mode */ +typedef enum +{ + MV_CESA_FRAG_NONE = 0, + MV_CESA_FRAG_FIRST = 1, + MV_CESA_FRAG_LAST = 2, + MV_CESA_FRAG_MIDDLE = 3, + +} MV_CESA_FRAG_MODE; + +#define MV_CESA_FRAG_MODE_OFFSET 30 +#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) +/*---------------------------------------------------------------------------*/ + +/********** Security Accelerator Command Register **************/ +#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) + +#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 +#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) + +#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 +#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) + +/********** Security Accelerator Descriptor Pointers Register **********/ +#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) + +/********** Security Accelerator Configuration Register **********/ +#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) + +#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 +#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) + +#define MV_CESA_CFG_WAIT_DMA_BIT 7 +#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) + +#define MV_CESA_CFG_ACT_DMA_BIT 9 +#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) + +#define MV_CESA_CFG_CHAIN_MODE_BIT 11 +#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) + +/********** Security Accelerator Status Register ***********/ +#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) + +#define MV_CESA_STATUS_ACTIVE_BIT 0 +#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) + +#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 +#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) + + +/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ +#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) + +/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ +#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) + +#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) +#define MV_CESA_CAUSE_DES_MASK (1 << 1) +#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) +#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) +#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) + +#define MV_CESA_CAUSE_ACC_BIT 5 +#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) + +#define MV_CESA_CAUSE_ACC_DMA_BIT 7 +#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) +#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) + +#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 +#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) + +#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 +#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) + +#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 +#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) + + +#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) +#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) +#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) + +#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) + +#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) +#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) +#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) + +#define MV_CESA_AUTH_ALGORITHM_BIT 0 +#define MV_CESA_AUTH_ALGORITHM_MD5 (0< +wait_queue_head_t cesaTest_waitq; +spinlock_t cesaLock; + +#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) +#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); + +#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) +#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) +#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) + +#define CESA_TEST_TICK_GET() jiffies +#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) + +#elif defined(MV_NETBSD) + +#include +#include +static int cesaLock; + +#define CESA_TEST_LOCK(flags) flags = splnet() +#define CESA_TEST_UNLOCK(flags) splx(flags) + +#define CESA_TEST_WAIT_INIT() /* nothing */ +#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) +#define CESA_TEST_WAIT(cond, ms) \ +do { \ + while (!(cond)) \ + tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ +} while (/*CONSTCOND*/0) + +#define CESA_TEST_TICK_GET() hardclock_ticks +#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) + +#define request_irq(i,h,t,n,a) \ + !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) + +#else +#error "Only Linux, VxWorks, or NetBSD OS are supported" +#endif + +#include "mvDebug.h" + +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cntmr/mvCntmr.h" +#include "cesa/mvCesa.h" +#include "cesa/mvCesaRegs.h" +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" + +#if defined(CONFIG_MV646xx) +#include "marvell_pic.h" +#endif + +#define MV_CESA_USE_TIMER_ID 0 +#define CESA_DEF_BUF_SIZE 1500 +#define CESA_DEF_BUF_NUM 1 +#define CESA_DEF_SESSION_NUM 32 + +#define CESA_DEF_ITER_NUM 100 + +#define CESA_DEF_REQ_SIZE 256 + + +/* CESA Tests Debug */ +#undef CESA_TEST_DEBUG + +#ifdef CESA_TEST_DEBUG + +# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg +# define CESA_TEST_DEBUG_CODE(code) code + +typedef struct +{ + int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ + MV_U32 timeStamp; + MV_U32 cause; + MV_U32 realCause; + MV_U32 dmaCause; + int resources; + MV_CESA_REQ* pReqReady; + MV_CESA_REQ* pReqEmpty; + MV_CESA_REQ* pReqProcess; +} MV_CESA_TEST_TRACE; + +#define MV_CESA_TEST_TRACE_SIZE 25 + +static int cesaTestTraceIdx = 0; +static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; + +static void cesaTestTraceAdd(int type, MV_U32 cause) +{ + cesaTestTrace[cesaTestTraceIdx].type = type; + cesaTestTrace[cesaTestTraceIdx].cause = cause; + cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); + cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; + cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; + cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; + cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; + cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); + cesaTestTraceIdx++; + if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) + cesaTestTraceIdx = 0; +} + +#else + +# define CESA_TEST_DEBUG_PRINT(msg) +# define CESA_TEST_DEBUG_CODE(code) + +#endif /* CESA_TEST_DEBUG */ + +int cesaExpReqId=0; +int cesaCbIter=0; + +int cesaIdx; +int cesaIteration; +int cesaRateSize; +int cesaReqSize; +unsigned long cesaTaskId; +int cesaBufNum; +int cesaBufSize; +int cesaCheckOffset; +int cesaCheckSize; +int cesaCheckMode; +int cesaTestIdx; +int cesaCaseIdx; + + +MV_U32 cesaTestIsrCount = 0; +MV_U32 cesaTestIsrMissCount = 0; + +MV_U32 cesaCryptoError = 0; +MV_U32 cesaReqIdError = 0; +MV_U32 cesaError = 0; + +char* cesaHexBuffer = NULL; + +char* cesaBinBuffer = NULL; +char* cesaExpBinBuffer = NULL; + +char* cesaInputHexStr = NULL; +char* cesaOutputHexStr = NULL; + +MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; + +MV_CESA_COMMAND* cesaCmdRing; +MV_CESA_RESULT cesaResult; + +int cesaTestFull = 0; + +MV_BOOL cesaIsReady = MV_FALSE; +MV_U32 cesaCycles = 0; +MV_U32 cesaBeginTicks = 0; +MV_U32 cesaEndTicks = 0; +MV_U32 cesaRate = 0; +MV_U32 cesaRateAfterDot = 0; + +void *cesaTestOSHandle = NULL; + +enum +{ + CESA_FAST_CHECK_MODE = 0, + CESA_FULL_CHECK_MODE, + CESA_NULL_CHECK_MODE, + CESA_SHOW_CHECK_MODE, + CESA_SW_SHOW_CHECK_MODE, + CESA_SW_NULL_CHECK_MODE, + + CESA_MAX_CHECK_MODE +}; + +enum +{ + DES_TEST_TYPE = 0, + TRIPLE_DES_TEST_TYPE = 1, + AES_TEST_TYPE = 2, + MD5_TEST_TYPE = 3, + SHA_TEST_TYPE = 4, + COMBINED_TEST_TYPE = 5, + + MAX_TEST_TYPE +}; + +/* Tests data base */ +typedef struct +{ + short sid; + char cryptoAlgorithm; /* DES/3DES/AES */ + char cryptoMode; /* ECB or CBC */ + char macAlgorithm; /* MD5 / SHA1 */ + char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ + char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ + unsigned char* pCryptoKey; + int cryptoKeySize; + unsigned char* pMacKey; + int macKeySize; + const char* name; + +} MV_CESA_TEST_SESSION; + +typedef struct +{ + MV_CESA_TEST_SESSION* pSessions; + int numSessions; + +} MV_CESA_TEST_DB_ENTRY; + +typedef struct +{ + char* plainHexStr; + char* cipherHexStr; + unsigned char* pCryptoIV; + int cryptoLength; + int macLength; + int digestOffset; + +} MV_CESA_TEST_CASE; + +typedef struct +{ + int size; + const char* outputHexStr; + +} MV_CESA_SIZE_TEST; + +static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; + +static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; +static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; + + +static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; + +static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; + +static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; + +static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, + 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; + + +static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, + 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; + +/* Input ASCII string: The quick brown fox jump */ +static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; +static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; + +static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, + 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, + 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; + +static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; + +static char plain3des2[] = "326a494cd33fe756"; + +static char cipher3desCbc2[] = "8e29f75ea77e5475" + "b22b8d66de970692"; + +static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, + 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, + 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; + +static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; + +static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; + +static char cipher3desCbc3[] = "3d1de3cc132e3b65" + "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; + +static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, + 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; + +static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, + 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; + +static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; + +static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; + +static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b}; + +static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + 0xaa, 0xaa, 0xaa, 0xaa}; + +static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; + +static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, + 0x11, 0x12, 0x13, 0x14}; + + +static MV_CESA_TEST_SESSION desTestSessions[] = +{ +/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), + NULL, 0, + "DES ECB encode", + }, +/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), + NULL, 0, + "DES ECB decode", + }, +/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), + NULL, 0, + "DES CBC encode" + }, +/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), + NULL, 0, + "DES CBC decode" + }, +/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, NULL, 0, + "NULL Crypto Algorithm encode" + }, +}; + + +static MV_CESA_TEST_SESSION tripleDesTestSessions[] = +{ +/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + NULL, 0, + "3DES ECB encode", + }, +/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + NULL, 0, + "3DES ECB decode", + }, +/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + NULL, 0, + "3DES CBC encode" + }, +/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + NULL, 0, + "3DES CBC decode" + }, +/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des1, sizeof(key3des1), + NULL, 0, + "3DES ECB encode" + }, +/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des2, sizeof(key3des2), + NULL, 0, + "3DES ECB encode" + }, +/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + key3des3, sizeof(key3des3), + NULL, 0, + "3DES ECB encode" + }, +}; + + +static MV_CESA_TEST_SESSION aesTestSessions[] = +{ +/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), + NULL, 0, + "AES-128 ECB encode" + }, +/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), + NULL, 0, + "AES-128 ECB decode" + }, +/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), + NULL, 0, + "AES-128 CBC encode" + }, +/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), + NULL, 0, + "AES-128 CBC decode" + }, +/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), + NULL, 0, + "AES-192 ECB encode" + }, +/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), + NULL, 0, + "AES-192 ECB decode" + }, +/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), + NULL, 0, + "AES-256 ECB encode" + }, +/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_DECODE, + cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), + NULL, 0, + "AES-256 ECB decode" + }, +/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, + MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, + MV_CESA_DIR_ENCODE, + aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), + NULL, 0, + "AES-128 CTR encode" + }, +}; + + +static MV_CESA_TEST_SESSION md5TestSessions[] = +{ +/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey1, sizeof(mdKey1), + "HMAC-MD5 Generate Signature" + }, +/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + mdKey1, sizeof(mdKey1), + "HMAC-MD5 Verify Signature" + }, +/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey2, sizeof(mdKey2), + "HMAC-MD5 Generate Signature" + }, +/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + mdKey2, sizeof(mdKey2), + "HMAC-MD5 Verify Signature" + }, +/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + mdKey4, sizeof(mdKey4), + "HMAC-MD5 Generate Signature" + }, +/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + NULL, 0, + "HASH-MD5 Generate Signature" + }, +}; + + +static MV_CESA_TEST_SESSION shaTestSessions[] = +{ +/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey1, sizeof(shaKey1), + "HMAC-SHA1 Generate Signature" + }, +/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + shaKey1, sizeof(shaKey1), + "HMAC-SHA1 Verify Signature" + }, +/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey2, sizeof(shaKey2), + "HMAC-SHA1 Generate Signature" + }, +/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_DECODE, + NULL, 0, + shaKey2, sizeof(shaKey2), + "HMAC-SHA1 Verify Signature" + }, +/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + shaKey4, sizeof(shaKey4), + "HMAC-SHA1 Generate Signature" + }, +/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, + MV_CESA_DIR_ENCODE, + NULL, 0, + NULL, 0, + "HASH-SHA1 Generate Signature" + }, +}; + +static MV_CESA_TEST_SESSION combinedTestSessions[] = +{ +/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, MV_CESA_DES_KEY_LENGTH, + mdKey4, sizeof(mdKey4), + "DES + MD5 encode" + }, +/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, MV_CESA_DES_KEY_LENGTH, + shaKey4, sizeof(shaKey4), + "DES + SHA1 encode" + }, +/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "3DES + MD5 encode" + }, +/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + shaKey4, sizeof(shaKey4), + "3DES + SHA1 encode" + }, +/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "3DES CBC + MD5 encode" + }, +/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + shaKey4, sizeof(shaKey4), + "3DES CBC + SHA1 encode" + }, +/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), + mdKey4, sizeof(mdKey4), + "AES-128 CBC + MD5 encode" + }, +/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, + MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, + MV_CESA_DIR_ENCODE, + cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), + shaKey4, sizeof(shaKey4), + "AES-128 CBC + SHA1 encode" + }, +/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, + MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, + MV_CESA_DIR_DECODE, + cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), + mdKey4, sizeof(mdKey4), + "HMAC-MD5 + 3DES decode" + }, +}; + + +static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = +{ + { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, + { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, + { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, + { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, + { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, + { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, + { NULL, 0 } +}; + + +char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; + +char cesaPlainAsciiText[] = "Now is the time for all "; +char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; +char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; +char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; +char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; + +char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; +char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; +char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; +char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; + +char cesaAsciiStr1[] = "Hi There"; +char cesaDataHexStr1[] = "4869205468657265"; +char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; +char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; +char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; +char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; + +char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" + "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" + "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" + "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; + +char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" + "0f3af07a9a31a9c684db207eb0ef8e4e" + "35907aa632c3ffdf868bb7b29d3d46ad" + "83ce9f9a102ee99d49a53e87f4c3da55"; + +char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" + "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" + "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" + "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" + "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; + +char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" + "c30e32ffedc0774e6aff6af0869f71aa" + "0f3af07a9a31a9c684db207eb0ef8e4e" + "35907aa632c3ffdf868bb7b29d3d46ad" + "83ce9f9a102ee99d49a53e87f4c3da55"; + +char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" + "000102030405060708090A0B0C0D0E0F" + "101112131415161718191A1B1C1D1E1F" + "20212223"; + +char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" + "C1CF48A89F2FFDD9CF4652E9EFDB72D7" + "4540A42BDE6D7836D59A5CEAAEF31053" + "25B2072F"; + + + +/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ +char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; +char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; +char cesaDataHexStr3[50*2+1] = ""; +char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; +char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; + +/* Ascii string is "abc" */ +char hashHexStr3[] = "616263"; +char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; +char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; + +char hashHexStr80[] = "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930" + "31323334353637383930"; + +char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; + +char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; +char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; + +char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; +char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; + +char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; +char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; + + +static MV_CESA_TEST_CASE cesaTestCases[] = +{ + /* plainHexStr cipherHexStr IV crypto mac digest */ + /* Length Length Offset */ + /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, + /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, + /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, + /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, + /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, + /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, + /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, + /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, + /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, + /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, +/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, +/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, +/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, +/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, +/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, +/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, +/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, +/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, +/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, +/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, +/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, +/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, +/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, +/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, +/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, +/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, +/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, +/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, +}; + + +/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa + * Input 0xdd repeated "size" times + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = +{ + { 80, "7a031a640c14a4872814930b1ef3a5b2" }, + { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, + { 1000, "d00814f586a8b78a05724239d2531821" }, + { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, + { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, + { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, + { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, + { 1005, "e082790b4857fcfc266e92e59e608814" }, + { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, + { 1336, "e42edcce57d0b75b01aa09d71427948b" }, + { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, + { 1399, "0f44d793e744b24d53f44f295082ee8c" }, + { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, + { 1401, "e913858b484cbe2b384099ea88d8855b" }, + { 1402, "d9848a164af53620e0540c1d7d87629e" }, + { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, + { 1404, "12edd4f609416e3c936170360561b064" }, + { 1405, "7fc912718a05446395345009132bf562" }, + { 1406, "882f17425e579ff0d85a91a59f308aa0" }, + { 1407, "005cae408630a2fb5db82ad9db7e59da" }, + { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, + { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, + { 2048, "67caf64475650732def374ebb8bde3fd" }, + { 2049, "6c84f11f472825f7e6cd125c2981884b" }, + { 2050, "8999586754a73a99efbe4dbad2816d41" }, + { 2051, "ba6946b610e098d286bc81091659dfff" }, + { 2052, "d0afa01c92d4d13def2b024f36faed83" }, + { 3072, "61d8beac61806afa2585d74a9a0e6974" }, + { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, + { 3075, "ea4a6929be67e33e61ff475369248b73" }, + { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, + { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, + { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, + { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, + { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, + { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, + { 6528, "b1d707b027354aca152c45ee559ccd3f" }, + { 8192, "c600ea4429ac47f9941f09182166e51a" }, + {16384, "16e8754bfbeb4c649218422792267a37" }, + {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, + { 0, NULL }, +}; + +/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = +{ + { 80, "a456c4723fee6068530af5a2afa71627" }, + { 512, "f85c2a2344f5de68b432208ad13e5794" }, + { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, + { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, + { 1002, "5664f71800c011cc311cb6943339c1b8" }, + { 1003, "779c723b044c585dc7802b13e8501bdc" }, + { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, + { 1005, "d5f978954f5c38529d1679d2b714f068" }, + { 1006, "cd3efc827ce628b7281b72172693abf9" }, + { 1336, "6f04479910785878ae6335b8d1e87edf" }, + { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, + { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, + { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, + { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, + { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, + { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, + { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, + { 1405, "d1487bd42f6edd9b4dab316631159221" }, + { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, + { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, + { 1408, "a9e13335612c0356f5e2c27086e86c43" }, + { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, + { 2048, "396905c9b961cd0f6152abfb69c4449c" }, + { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, + { 2050, "3a2b4823bc4d0415656550226a63e34a" }, + { 2051, "dec60580d406c782540f398ad0bcc7e0" }, + { 2052, "32f76610a14310309eb748fe025081bf" }, + { 3072, "45edc1a42bf9d708a621076b63b774da" }, + { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, + { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, + { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, + { 4052, "81976bcaeb274223983996c137875cb8" }, + { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, + { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, + { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, + { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, + { 6528, "216f44f23047cfee03a7a64f88f9a995" }, + { 8192, "ac7a993b2cad54879dba1bde63e39097" }, + { 8320, "55ed7be9682d6c0025b3221a62088d08" }, + {16384, "c6c722087653b62007aea668277175e5" }, + {18432, "f1faca8e907872c809e14ffbd85792d6" }, + { 0, NULL }, +}; + +/* HASH-MD5 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * repeated "size" times + */ +static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = +{ + { 80, "57edf4a22be3c955ac49da2e2107b67a" }, + { 512, "c729ae8f0736cc377a9767a660eaa04e" }, + { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, + { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, + { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, + { 1003, "961753017feee04c9b93a8e51658a829" }, + { 1004, "dd68c4338608dcc87807a711636bf2af" }, + { 1005, "e338d567d3ce66bf69ada29658a8759b" }, + { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, + { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, + { 1344, "335a919805f370b9e402a62c6fe01739" }, + { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, + { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, + { 1401, "49590f61298a76719bc93a57a30136f5" }, + { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, + { 1403, "37073a02ab00ecba2645c57c228860db" }, + { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, + { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, + { 1406, "4b6695772a4c66313fa4871017d05f36" }, + { 1407, "d1539b97fbfda1c075624e958de19c5b" }, + { 1408, "b801b9b69920907cd018e8063092ede9" }, + { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, + { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, + { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, + { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, + { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, + { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, + { 3072, "37d158e33b21390822739d13db7b87fe" }, + { 3074, "aef3b209d01d39d0597fe03634bbf441" }, + { 3075, "335ffb428eabf210bada96d74d5a4012" }, + { 4048, "2434c2b43d798d2819487a886261fc64" }, + { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, + { 4058, "856781f85616c341c3533d090c1e1e84" }, + { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, + { 6150, "a09a353be7795fac2401dac5601872e6" }, + { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, + { 6528, "3d47aa193a8540c091e7e02f779e6751" }, + { 8192, "d3164e710c0626f6f395b38f20141cb7" }, + { 8320, "b727589d9183ff4e8491dd24466974a3" }, + {16384, "3f54d970793d2274d5b20d10a69938ac" }, + {18432, "f558511dcf81985b7a1bb57fad970531" }, + { 0, NULL }, +}; + + +/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, + * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa + * 0xaa, 0xaa, 0xaa, 0xaa + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = +{ + { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, + { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, + { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, + { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, + { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, + { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, + { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, + { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, + { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, + { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, + { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, + { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, + { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, + { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, + { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, + { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, + { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, + { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, + { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, + { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, + { 1408, "3987511182b18473a564436003139b808fa46343" }, + { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, + { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, + { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, + { 2050, "8831939904009338de10e7fa670847041387807d" }, + { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, + { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, + { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, + { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, + { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, + { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, + { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, + { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, + { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, + { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, + { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, + { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, + { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, + { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, + {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, + {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, + { 0, NULL }, +}; + +/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = +{ + { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, + { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, + { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, + { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, + { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, + { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, + { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, + { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, + { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, + { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, + { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, + { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, + { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, + { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, + { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, + { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, + { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, + { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, + { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, + { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, + { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, + { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, + { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, + { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, + { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, + { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, + { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, + { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, + { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, + { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, + { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, + { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, + { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, + { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, + { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, + { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, + { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, + { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, + { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, + {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, + {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, + { 0, NULL }, +}; + +/* HASH-SHA1 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * repeated "size" times + */ +static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = +{ + { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, + { 512, "f14516a08948fa27917a974d219741a697ba0087" }, + { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, + { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, + { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, + { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, + { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, + { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, + { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, + { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, + { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, + { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, + { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, + { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, + { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, + { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, + { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, + { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, + { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, + { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, + { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, + { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, + { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, + { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, + { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, + { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, + { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, + { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, + { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, + { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, + { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, + { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, + { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, + { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, + { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, + { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, + { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, + { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, + { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, + {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, + {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, + { 0, NULL }, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = +{ + { 64, "9586962a2aaaef28803dec2e17807a7f" }, + { 80, "b7726a03aad490bd6c5a452a89a1b271" }, + { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, + { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, + { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, + { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, + { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, + { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, + { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, + { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, + { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, + { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, + { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, + { 6400, "44e4613496ba622deb0e7cb768135a2f" }, + { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, + { 8192, "d581780b7163138a0f412be681457d82" }, + {16384, "03b8ac05527faaf1bed03df149c65ccf" }, + {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, + { 0, NULL }, +}; + + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = +{ + { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, + { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, + { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, + { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, + { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, + { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, + { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, + { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, + { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, + { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, + { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, + { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, + { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, + { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, + { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, + { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, + {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, + {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, + { 0, NULL }, +}; + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = +{ + { 64, "8d10e00802460ede0058c139ba48bd2d" }, + { 80, "6f463057e1a90e0e91ae505b527bcec0" }, + { 352, "4938d48bdf86aece2c6851e7c6079788" }, + { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, + { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, + { 1336, "44af60087b74ed07950088efbe3b126a" }, + { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, + { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, + { 1408, "4fb436624b02516fc9d1535466574bf9" }, + { 2048, "c909b0985c423d8d86719f701e9e83db" }, + { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, + { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, + { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, + { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, + { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, + { 8192, "afe101fbe745bb449ae4f50d10801456" }, + {16384, "9741706d0b1c923340c4660ff97cacdf" }, + {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, + { 0, NULL }, +}; + + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to 3DES block size (8 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = +{ + { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, + { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, + { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, + { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, + { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, + { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, + { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, + { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, + { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, + { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, + { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, + { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, + { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, + { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, + { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, + { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, + {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, + {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, + { 0, NULL }, +}; + + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to AES block size (16 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = +{ + { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, + { 64, "7dba7fb988e80da609b1fea7254bced8" }, + { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, + { 352, "a1ceb9c2e3021002400d525187a9f38c" }, + { 512, "596c055c1c55db748379223164075641" }, + { 1008, "f920989c02f3b3603f53c99d89492377" }, + { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, + { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, + { 2048, "a917f0099c69eb94079a8421714b6aad" }, + { 3072, "693cd5033d7f5391d3c958519fa9e934" }, + { 4048, "139dca91bcff65b3c40771749052906b" }, + { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, + { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, + { 6528, "ad876f6297186a7be1f1b907ed860eda" }, + { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, + {16384, "60fda559c74f91df538100c9842f2f15" }, + {18432, "4a3eb1cba1fa45f3981270953f720c42" }, + { 0, NULL }, +}; + + +/* CryptoKey = 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef, + * 0x01234567, 0x89abcdef; + * IV = 0x12345678, 0x90abcdef + * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 + * 0x11, 0x12, 0x13, 0x14 + * InputHexStr = "31323334353637383930" (ASCII = "1234567890") + * Note: only sizes aligned to AES block size (16 bytes) allowed + */ +static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = +{ + { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, + { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, + { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, + { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, + { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, + { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, + { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, + { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, + { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, + { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, + { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, + { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, + { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, + { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, + { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, + {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, + {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, + { 0, NULL }, +}; + + +void cesaTestPrintStatus(void); + + +/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ +MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, + MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); +MV_STATUS testClose(int idx); +MV_STATUS testOpen(int idx); +void close_session(int sid); +void cesaTestCheckReady(const MV_CESA_RESULT *r); +void cesaCheckReady(MV_CESA_RESULT* r); +void printTestResults(int idx, MV_STATUS status, int checkMode); +void cesaLastResult(void); +void cesaTestPrintReq(int req, int offset, int size); + +void cesaTestPrintStatus(void); +void cesaTestPrintSession(int idx); +void sizeTest(int testIdx, int iter, int checkMode); +void multiTest(int iter, int reqSize, int checkMode); +void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); +void multiSizeTest(int idx, int iter, int checkMode, char* inputData); +void cesaTest(int iter, int reqSize, int checkMode); +void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); +void combiTest(int iter, int reqSize, int checkMode); +void shaTest(int iter, int reqSize, int checkMode); +void mdTest(int iter, int reqSize, int checkMode); +void aesTest(int iter, int reqSize, int checkMode); +void tripleDesTest(int iter, int reqSize, int checkMode); +void desTest(int iter, int reqSize, int checkMode); +void cesaTestStop(void); +MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); +void cesaTestStart(int bufNum, int bufSize); + + +static MV_U32 getRate(MV_U32* remainder) +{ + MV_U32 kBits, milliSec, rate; + + milliSec = 0; + if( (cesaEndTicks - cesaBeginTicks) > 0) + { + milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); + } + if(milliSec == 0) + { + if(remainder != NULL) + *remainder = 0; + return 0; + } + + kBits = (cesaIteration*cesaRateSize*8)/1000; + rate = kBits/milliSec; + if(remainder != NULL) + *remainder = ((kBits % milliSec)*10)/milliSec; + + return rate; +} + +static char* extractMbuf(MV_CESA_MBUF *pMbuf, + int offset, int size, char* hexStr) +{ + mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); + mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); + + return hexStr; +} + +static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, + const char* hexString, int offset, + int checkSize) +{ + MV_BOOL isFailed = MV_FALSE; + MV_STATUS status; + int size = strlen(hexString)/2; + int checkedSize = 0; +/* + mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", + pMbuf, offset, checkSize, pMbuf->mbufSize); +*/ + if(pMbuf->mbufSize < (checkSize + offset)) + { + mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", + checkSize, offset, pMbuf->mbufSize); + return MV_TRUE; + } + status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); + if(status != MV_OK) + { + mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", + checkSize, pMbuf, cesaBinBuffer); + return MV_TRUE; + } +/* + mvDebugMemDump(cesaBinBuffer, size, 1); +*/ + mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); + + /* Compare buffers */ + while(checkSize > checkedSize) + { + size = MV_MIN(size, (checkSize - checkedSize)); + if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) + { + mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", + checkSize, size, checkedSize); + mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); + mvDebugMemDump(cesaExpBinBuffer, size, 1); + + isFailed = MV_TRUE; + break; + } + checkedSize += size; + } + + return isFailed; +} + +static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, + const char* hexString, + int offset, int reqSize) +{ + MV_STATUS status = MV_OK; + int copySize, size = strlen(hexString)/2; + + mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); + + copySize = 0; + while(reqSize > copySize) + { + size = MV_MIN(size, (reqSize - copySize)); + + status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); + if(status != MV_OK) + { + mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", + copySize, reqSize); + break; + } + copySize += size; + } + pMbuf->mbufSize = offset+copySize; + return status; +} + +static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) +{ + int testIdx, dbIdx = idx/100; + + if(dbIdx > MAX_TEST_TYPE) + { + mvOsPrintf("Wrong index %d - No such test type\n", idx); + return NULL; + } + testIdx = idx % 100; + + if(testIdx >= cesaTestsDB[dbIdx].numSessions) + { + mvOsPrintf("Wrong index %d - No such test\n", idx); + return NULL; + } + if(pTestIdx != NULL) + *pTestIdx = testIdx; + + return cesaTestsDB[dbIdx].pSessions; +} + +/* Debug */ +void cesaTestPrintReq(int req, int offset, int size) +{ + MV_CESA_MBUF* pMbuf; + + mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", + req, offset, size); + mvDebugMemDump(cesaCmdRing, 128, 4); + + pMbuf = cesaCmdRing[req].pSrc; + mvCesaDebugMbuf("src", pMbuf, offset,size); + pMbuf = cesaCmdRing[req].pDst; + mvCesaDebugMbuf("dst", pMbuf, offset, size); + + cesaTestPrintStatus(); +} + +void cesaLastResult(void) +{ + mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", + (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, + cesaResult.retCode); +} + +void printTestResults(int idx, MV_STATUS status, int checkMode) +{ + int testIdx; + MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); + + if(pTestSessions == NULL) + return; + + mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, + cesaIteration, cesaReqSize); + if( (status == MV_OK) && + (cesaCryptoError == 0) && + (cesaError == 0) && + (cesaReqIdError == 0) ) + { + mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", + cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); + } + else + { + mvOsPrintf("Failed, Status = 0x%x\n", status); + if(cesaCryptoError > 0) + mvOsPrintf("cryptoError : %d\n", cesaCryptoError); + if(cesaReqIdError > 0) + mvOsPrintf("reqIdError : %d\n", cesaReqIdError); + if(cesaError > 0) + mvOsPrintf("cesaError : %d\n", cesaError); + } + if(cesaTestIsrMissCount > 0) + mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); +} + +void cesaCheckReady(MV_CESA_RESULT* r) +{ + int reqId; + MV_CESA_MBUF *pMbuf; + MV_BOOL isFailed; + + cesaResult = *r; + reqId = (int)cesaResult.pReqPrv; + pMbuf = cesaCmdRing[reqId].pDst; + +/* + mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", + reqId, cesaCheckOffset, cesaCheckSize); +*/ + /* Check expected reqId */ + if(reqId != cesaExpReqId) + { + cesaReqIdError++; +/* + mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", + cesaCbIter, cesaIteration, reqId, cesaExpReqId); +*/ + } + else + { + if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || + (cesaCheckMode == CESA_FAST_CHECK_MODE) ) + { + if(cesaResult.retCode != MV_OK) + { + cesaError++; + + mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", + cesaCbIter, cesaIteration, reqId, cesaResult.retCode); + } + else + { + if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) + { + /* Check expected output */ + + isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); + if(isFailed) + { + mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", + cesaCbIter, cesaIteration, reqId); + + CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", + reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); + + CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); + + CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); + + cesaCryptoError++; + } + } + } + } + } + if(cesaCheckMode == CESA_SHOW_CHECK_MODE) + { + extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); + mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); + } + + cesaCbIter++; + if(cesaCbIter >= cesaIteration) + { + cesaCbIter = 0; + cesaExpReqId = 0; + cesaIsReady = MV_TRUE; + + cesaEndTicks = CESA_TEST_TICK_GET(); + cesaRate = getRate(&cesaRateAfterDot); + } + else + { + cesaExpReqId = reqId + 1; + if(cesaExpReqId == CESA_DEF_REQ_SIZE) + cesaExpReqId = 0; + } +} + + +#ifdef MV_NETBSD +static int cesaTestReadyIsr(void *arg) +#else +#ifdef __KERNEL__ +static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) +#endif +#ifdef MV_VXWORKS +void cesaTestReadyIsr(void) +#endif +#endif +{ + MV_U32 cause; + MV_STATUS status; + MV_CESA_RESULT result; + + cesaTestIsrCount++; + /* Clear cause register */ + cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) + { + mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); +#ifdef MV_NETBSD + return 0; +#else +#ifdef __KERNEL__ + return 1; +#else + return; +#endif +#endif + } + + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + + while(MV_TRUE) + { + /* Get Ready requests */ + status = mvCesaReadyGet(&result); + if(status == MV_OK) + cesaCheckReady(&result); + + break; + } + if( (cesaTestFull == 1) && (status != MV_BUSY) ) + { + cesaTestFull = 0; + CESA_TEST_WAKE_UP(); + } + +#ifdef __KERNEL__ + return 1; +#endif +} + +void +cesaTestCheckReady(const MV_CESA_RESULT *r) +{ + MV_CESA_RESULT result = *r; + + cesaCheckReady(&result); + + if (cesaTestFull == 1) { + cesaTestFull = 0; + CESA_TEST_WAKE_UP(); + } +} + +static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) +{ + MV_U16 sid; + MV_STATUS status; + + status = mvCesaSessionOpen(pOs, (short*)&sid); + if(status != MV_OK) + { + mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", + status); + return -1; + } + + return (int)sid; +} + +void close_session(int sid) +{ + MV_STATUS status; + + status = mvCesaSessionClose(sid); + if(status != MV_OK) + { + mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", + sid, status); + } +} + +MV_STATUS testOpen(int idx) +{ + MV_CESA_OPEN_SESSION os; + int sid, i, testIdx; + MV_CESA_TEST_SESSION* pTestSession; + MV_U16 digestSize = 0; + + pTestSession = getTestSessionDb(idx, &testIdx); + if(pTestSession == NULL) + { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + if(pTestSession->sid != -1) + { + mvOsPrintf("Session for test %d already created: sid=%d\n", + idx, pTestSession->sid); + return MV_OK; + } + + os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; + os.macMode = pTestSession->macAlgorithm; + switch(os.macMode) + { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + + case MV_CESA_MAC_NULL: + digestSize = 0; + } + os.cryptoMode = pTestSession->cryptoMode; + os.direction = pTestSession->direction; + os.operation = pTestSession->operation; + + for(i=0; icryptoKeySize; i++) + os.cryptoKey[i] = pTestSession->pCryptoKey[i]; + + os.cryptoKeyLength = pTestSession->cryptoKeySize; + + for(i=0; imacKeySize; i++) + os.macKey[i] = pTestSession->pMacKey[i]; + + os.macKeyLength = pTestSession->macKeySize; + os.digestSize = digestSize; + + sid = open_session(&os); + if(sid == -1) + { + mvOsPrintf("Can't open session for test %d: rc=0x%x\n", + idx, cesaResult.retCode); + return cesaResult.retCode; + } + CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); + pTestSession->sid = sid; + return MV_OK; +} + +MV_STATUS testClose(int idx) +{ + int testIdx; + MV_CESA_TEST_SESSION* pTestSession; + + pTestSession = getTestSessionDb(idx, &testIdx); + if(pTestSession == NULL) + { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + if(pTestSession->sid == -1) + { + mvOsPrintf("Test session %d is not opened\n", idx); + return MV_NO_SUCH; + } + + close_session(pTestSession->sid); + pTestSession->sid = -1; + + return MV_OK; +} + +MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, + MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) +{ + int cmdReqId = 0; + int i; + MV_STATUS rc = MV_OK; + char ivZeroHex[] = "0000"; + + if(iter == 0) + iter = CESA_DEF_ITER_NUM; + + if(pCmd == NULL) + { + mvOsPrintf("testCmd failed: pCmd=NULL\n"); + return MV_BAD_PARAM; + } + pCmd->sessionId = sid; + + cesaCryptoError = 0; + cesaReqIdError = 0; + cesaError = 0; + cesaTestIsrMissCount = 0; + cesaIsReady = MV_FALSE; + cesaIteration = iter; + + if(cesaInputHexStr == NULL) + cesaInputHexStr = cesaPlainHexEbc; + + for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); + if(pIV != NULL) + { + /* If IV from SA - set IV in Source buffer to zeros */ + cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); + cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, + (cesaReqSize - pCmd->cryptoOffset)); + } + else + { + cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); + } + pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); + cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); + + memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); + } + + if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) + { + MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; + + if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) + { + mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); + mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", + cesaReqSize, pCmd->macLength); + mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); + return MV_OK; + } + if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) + { + mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); + mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", + cesaReqSize, pCmd->macLength); + mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); + return MV_OK; + } + } + + cesaBeginTicks = CESA_TEST_TICK_GET(); + CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); + cesaTestTraceIdx = 0; + ); + + if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) + { + volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; + + for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) + { + mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); + } + if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) + { + mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); + } + } + cesaEndTicks = CESA_TEST_TICK_GET(); + cesaRate = getRate(&cesaRateAfterDot); + cesaIsReady = MV_TRUE; + + return MV_OK; + } + + /*cesaTestIsrCount = 0;*/ + /*mvCesaDebugStatsClear();*/ + +#ifndef MV_NETBSD + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); +#endif + + for(i=0; ipReqPrv = (void*)cmdReqId; + + CESA_TEST_LOCK(flags); + + rc = mvCesaAction(pCmd); + if(rc == MV_NO_RESOURCE) + cesaTestFull = 1; + + CESA_TEST_UNLOCK(flags); + + if(rc == MV_NO_RESOURCE) + { + CESA_TEST_LOCK(flags); + CESA_TEST_WAIT( (cesaTestFull == 0), 100); + CESA_TEST_UNLOCK(flags); + if(cesaTestFull == 1) + { + mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", + i, iter, cesaTestFull); + cesaTestFull = 0; + return MV_TIMEOUT; + } + + CESA_TEST_LOCK(flags); + + rc = mvCesaAction(pCmd); + + CESA_TEST_UNLOCK(flags); + } + if( (rc != MV_OK) && (rc != MV_NO_MORE) ) + { + mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); + return rc; + } + + cmdReqId++; + if(cmdReqId >= CESA_DEF_REQ_SIZE) + cmdReqId = 0; + +#ifdef MV_LINUX + /* Reschedule each 16 requests */ + if( (i & 0xF) == 0) + schedule(); +#endif + } + return MV_OK; +} + +void cesaTestStart(int bufNum, int bufSize) +{ + int i, j, idx; + MV_CESA_MBUF *pMbufSrc, *pMbufDst; + MV_BUF_INFO *pFragsSrc, *pFragsDst; + char *pBuf; +#ifndef MV_NETBSD + int numOfSessions, queueDepth; + char *pSram; + MV_STATUS status; + MV_CPU_DEC_WIN addrDecWin; +#endif + + cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); + if(cesaCmdRing == NULL) + { + mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", + sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); + return; + } + memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); + + if(bufNum == 0) + bufNum = CESA_DEF_BUF_NUM; + + if(bufSize == 0) + bufSize = CESA_DEF_BUF_SIZE; + + cesaBufNum = bufNum; + cesaBufSize = bufSize; + mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", + bufNum, bufSize); + + cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); + if(cesaHexBuffer == NULL) + { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", + 2*bufNum*bufSize); + return; + } + memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); + + cesaBinBuffer = mvOsMalloc(bufNum*bufSize); + if(cesaBinBuffer == NULL) + { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", + bufNum*bufSize); + return; + } + memset(cesaBinBuffer, 0, (bufNum*bufSize)); + + cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); + if(cesaExpBinBuffer == NULL) + { + mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", + bufNum*bufSize); + return; + } + memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); + + CESA_TEST_WAIT_INIT(); + + pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || + (pMbufDst == NULL) || (pFragsDst == NULL) ) + { + mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); + /* !!!! Dima cesaTestCleanup();*/ + return; + } + + memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); + memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); + + mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", + pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); + + idx = 0; + for(i=0; ipFrags = &pFragsSrc[idx]; + cesaCmdRing[i].pSrc->numFrags = bufNum; + cesaCmdRing[i].pSrc->mbufSize = 0; + + cesaCmdRing[i].pDst = &pMbufDst[i]; + cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; + cesaCmdRing[i].pDst->numFrags = bufNum; + cesaCmdRing[i].pDst->mbufSize = 0; + + for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; + cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; + pBuf += bufSize; + cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; + cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; + pBuf += bufSize; + } + idx += bufNum; + } + +#ifndef MV_NETBSD + if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) + pSram = (char*)addrDecWin.addrWin.baseLow; + else + { + mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); + return; + } + +#ifdef MV_CESA_NO_SRAM + pSram = mvOsMalloc(4*1024+8); + if(pSram == NULL) + { + mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", + 4*1024+8); + /* !!!! Dima cesaTestCleanup();*/ + return; + } + pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); +#endif /* MV_CESA_NO_SRAM */ + + numOfSessions = CESA_DEF_SESSION_NUM; + queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; + + status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); + if(status != MV_OK) + { + mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); + /* !!!! Dima cesaTestCleanup();*/ + return; + } +#endif /* !MV_NETBSD */ + + /* Prepare data for tests */ + for(i=0; i<50; i++) + strcat((char*)cesaDataHexStr3, "dd"); + + strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); + strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); + + /* Digest must be 8 byte aligned */ + for(; i<56; i++) + { + strcat((char*)cesaDataAndMd5digest3, "00"); + strcat((char*)cesaDataAndSha1digest3, "00"); + } + strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); + strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); + +#ifndef MV_NETBSD + MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); +#endif + +#ifdef MV_VXWORKS + { + MV_STATUS status; + + status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); + if (status != OK) + { + mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", + INT_LVL_CESA, status); + /* !!!! Dima cesaTestCleanup();*/ + return; + } + cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); + if(cesaSemId == NULL) + { + mvOsPrintf("cesaTestStart: Can't create semaphore\n"); + return; + } + intEnable(INT_LVL_CESA); + } +#endif /* MV_VXWORKS */ + +#if !defined(MV_NETBSD) && defined(__KERNEL__) + if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) + { + mvOsPrintf( "cannot assign irq\n" ); + /* !!!! Dima cesaTestCleanup();*/ + return; + } + spin_lock_init( &cesaLock ); +#endif +} + +MV_STATUS testRun(int idx, int caseIdx, int iter, + int reqSize, int checkMode) +{ + int testIdx, count, sid, digestSize; + int blockSize; + MV_CESA_TEST_SESSION* pTestSession; + MV_CESA_COMMAND cmd; + MV_STATUS status; + + memset(&cmd, 0, sizeof(cmd)); + + pTestSession = getTestSessionDb(idx, &testIdx); + if(pTestSession == NULL) + { + mvOsPrintf("Test %d is not exist\n", idx); + return MV_BAD_PARAM; + } + pTestSession = &pTestSession[testIdx]; + + sid = pTestSession->sid; + if(sid == -1) + { + mvOsPrintf("Test %d is not opened\n", idx); + return MV_BAD_STATE; + } + switch(pTestSession->cryptoAlgorithm) + { + case MV_CESA_CRYPTO_DES: + case MV_CESA_CRYPTO_3DES: + blockSize = MV_CESA_DES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_AES: + blockSize = MV_CESA_AES_BLOCK_SIZE; + break; + + case MV_CESA_CRYPTO_NULL: + blockSize = 0; + break; + + default: + mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", + pTestSession->cryptoAlgorithm); + return MV_BAD_PARAM; + } + switch(pTestSession->macAlgorithm) + { + case MV_CESA_MAC_MD5: + case MV_CESA_MAC_HMAC_MD5: + digestSize = MV_CESA_MD5_DIGEST_SIZE; + break; + + case MV_CESA_MAC_SHA1: + case MV_CESA_MAC_HMAC_SHA1: + digestSize = MV_CESA_SHA1_DIGEST_SIZE; + break; + default: + digestSize = 0; + } + + if(iter == 0) + iter = CESA_DEF_ITER_NUM; + + if(pTestSession->direction == MV_CESA_DIR_ENCODE) + { + cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; + cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; + } + else + { + cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; + cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; + } + + cmd.sessionId = sid; + if(checkMode == CESA_FAST_CHECK_MODE) + { + cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; + cmd.macLength = cesaTestCases[caseIdx].macLength; + } + else + { + cmd.cryptoLength = reqSize; + cmd.macLength = reqSize; + } + cesaRateSize = cmd.cryptoLength; + cesaReqSize = cmd.cryptoLength; + cmd.cryptoOffset = 0; + if(pTestSession->operation != MV_CESA_MAC_ONLY) + { + if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || + (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) + { + cmd.ivOffset = 0; + cmd.cryptoOffset = blockSize; + if(cesaTestCases[caseIdx].pCryptoIV == NULL) + { + cmd.ivFromUser = 1; + } + else + { + cmd.ivFromUser = 0; + mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); + } + cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; + } + } + +/* + mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", + cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); +*/ + if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) + { + cmd.macOffset = cmd.cryptoOffset; + + if(cesaTestCases[caseIdx].digestOffset == -1) + { + cmd.digestOffset = cmd.macOffset + cmd.macLength; + cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); + } + else + { + cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; + } + if( (cmd.digestOffset + digestSize) > cesaReqSize) + cesaReqSize = cmd.digestOffset + digestSize; + } + + cesaCheckMode = checkMode; + + if(checkMode == CESA_NULL_CHECK_MODE) + { + cesaCheckSize = 0; + cesaCheckOffset = 0; + } + else + { + if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) + { + cesaCheckOffset = 0; + cesaCheckSize = cmd.cryptoLength; + } + else + { + cesaCheckSize = digestSize; + cesaCheckOffset = cmd.digestOffset; + } + } +/* + mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", + cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); + + mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", + blockSize, cmd.ivOffset, cmd.ivFromUser, + cmd.cryptoOffset, cmd.cryptoLength); + + mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", + cmd.macOffset, cmd.digestOffset, cmd.macLength); +*/ + status = testCmd(sid, iter, &cmd, pTestSession, + cesaTestCases[caseIdx].pCryptoIV, blockSize); + + if(status != MV_OK) + return status; + + /* Wait when all callbacks is received */ + count = 0; + while(cesaIsReady == MV_FALSE) + { + mvOsSleep(10); + count++; + if(count > 100) + { + mvOsPrintf("testRun: Timeout occured\n"); + return MV_TIMEOUT; + } + } + + return MV_OK; +} + + +void cesaTestStop(void) +{ + MV_CESA_MBUF *pMbufSrc, *pMbufDst; + MV_BUF_INFO *pFragsSrc, *pFragsDst; + int i; + + /* Release all allocated memories */ + pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); + pFragsSrc = cesaCmdRing[0].pSrc->pFrags; + + pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); + pFragsDst = cesaCmdRing[0].pDst->pFrags; + + mvOsFree(pMbufSrc); + mvOsFree(pMbufDst); + mvOsFree(pFragsSrc); + mvOsFree(pFragsDst); + + for(i=0; i 0) + cryptoError++; + if(cesaReqIdError > 0) + reqIdError++; + + testClose(idx); + } + } + if(cryptoError > 0) + mvOsPrintf("cryptoError : %d\n", cryptoError); + if(reqIdError > 0) + mvOsPrintf("reqIdError : %d\n", reqIdError); + + if(openErrors > 0) + { + mvOsPrintf("Open Errors = %d\n", openErrors); + for(i=0; i<100; i++) + { + if(openErrDisp[i] != 0) + mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); + } + } +} + + +void loopback_test(int idx, int iter, int size, char* pPlainData) +{ +} + + +#if defined(MV_VXWORKS) +int testMode = 0; +unsigned __TASKCONV cesaTask(void* args) +{ + int reqSize = cesaReqSize; + + if(testMode == 0) + { + cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, + reqSize, cesaCheckMode); + } + else + { + if(testMode == 1) + { + cesaTest(cesaIteration, reqSize, cesaCheckMode); + combiTest(cesaIteration, reqSize, cesaCheckMode); + } + else + { + multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); + } + } + return 0; +} + +void oneTest(int testIdx, int caseIdx, + int iter, int reqSize, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaReqSize = cesaRateSize = reqSize; + cesaCheckMode = checkMode; + testMode = 0; + cesaTestIdx = testIdx; + cesaCaseIdx = caseIdx; + rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + { + mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); + } +} + +void multiTest(int iter, int reqSize, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaCheckMode = checkMode; + cesaReqSize = reqSize; + testMode = 1; + rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + { + mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); + } +} + +void sizeTest(int testIdx, int iter, int checkMode) +{ + long rc; + + cesaIteration = iter; + cesaCheckMode = checkMode; + testMode = 2; + cesaIdx = testIdx; + rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); + if (rc != MV_OK) + { + mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); + } +} + +#endif /* MV_VXWORKS */ + +extern void mvCesaDebugSA(short sid, int mode); +void cesaTestPrintSession(int idx) +{ + int testIdx; + MV_CESA_TEST_SESSION* pTestSession; + + pTestSession = getTestSessionDb(idx, &testIdx); + if(pTestSession == NULL) + { + mvOsPrintf("Test %d is not exist\n", idx); + return; + } + pTestSession = &pTestSession[testIdx]; + + if(pTestSession->sid == -1) + { + mvOsPrintf("Test session %d is not opened\n", idx); + return; + } + + mvCesaDebugSA(pTestSession->sid, 1); +} + +void cesaTestPrintStatus(void) +{ + mvOsPrintf("\n\t Cesa Test Status\n\n"); + + mvOsPrintf("isrCount=%d\n", + cesaTestIsrCount); + +#ifdef CESA_TEST_DEBUG + { + int i, j; + j = cesaTestTraceIdx; + mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); + for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); + if(pLruCache->table == NULL) + { + mvOsFree(pLruCache); + return NULL; + } + memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); + pLruCache->tableSize = numOfEntries; + + for(i=0; itable[i].next = i+1; + pLruCache->table[i].prev = i-1; + } + pLruCache->least = 0; + pLruCache->most = numOfEntries-1; + + return pLruCache; +} + +void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) +{ + mvOsFree(pLruCache->table); + mvOsFree(pLruCache); +} + +/* Update LRU cache database after using cache Index */ +void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) +{ + int prev, next; + + if(cacheIdx == pLruHndl->most) + return; + + next = pLruHndl->table[cacheIdx].next; + if(cacheIdx == pLruHndl->least) + { + pLruHndl->least = next; + } + else + { + prev = pLruHndl->table[cacheIdx].prev; + + pLruHndl->table[next].prev = prev; + pLruHndl->table[prev].next = next; + } + + pLruHndl->table[pLruHndl->most].next = cacheIdx; + pLruHndl->table[cacheIdx].prev = pLruHndl->most; + pLruHndl->most = cacheIdx; +} + +/* Delete LRU cache entry */ +void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) +{ + int prev, next; + + if(cacheIdx == pLruHndl->least) + return; + + prev = pLruHndl->table[cacheIdx].prev; + if(cacheIdx == pLruHndl->most) + { + pLruHndl->most = prev; + } + else + { + next = pLruHndl->table[cacheIdx].next; + + pLruHndl->table[next].prev = prev; + pLruHndl->table[prev].next = next; + } + pLruHndl->table[pLruHndl->least].prev = cacheIdx; + pLruHndl->table[cacheIdx].next = pLruHndl->least; + pLruHndl->least = cacheIdx; +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvLru.h b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvLru.h new file mode 100644 index 0000000..896e7f8 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvLru.h @@ -0,0 +1,112 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/******************************************************************************* +* mvLru.h - Header File for Least Recently Used Cache algorithm +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration for +* the Least Recently Used Cache algorithm. +* +*******************************************************************************/ + +#ifndef __mvLru_h__ +#define __mvLru_h__ + + +typedef struct +{ + int next; + int prev; +} MV_LRU_ENTRY; + +typedef struct +{ + int least; + int most; + MV_LRU_ENTRY* table; + int tableSize; + +}MV_LRU_CACHE; + + +/* Find Cache index for replacement LRU */ +static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) +{ + return pLruHndl->least; +} + +/* Init LRU cache module */ +MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); + +/* Finish LRU cache module */ +void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); + +/* Update LRU cache database after using cache Index */ +void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); + +/* Delete LRU cache entry */ +void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); + + +#endif /* __mvLru_h__ */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvMD5.c b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvMD5.c new file mode 100644 index 0000000..189f629 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvMD5.c @@ -0,0 +1,349 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvMD5.h" + +static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); + +#ifdef MV_CPU_LE +#define mvByteReverse(buf, len) /* Nothing */ +#else +static void mvByteReverse(unsigned char *buf, unsigned longs); + +/* + * Note: this code is harmless on little-endian machines. + */ +static void mvByteReverse(unsigned char *buf, unsigned longs) +{ + MV_U32 t; + + do + { + t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | + ((unsigned) buf[1] << 8 | buf[0]); + *(MV_U32 *) buf = t; + buf += 4; + } while (--longs); +} +#endif + +/* + * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious + * initialization constants. + */ +void mvMD5Init(MV_MD5_CONTEXT *ctx) +{ + ctx->buf[0] = 0x67452301; + ctx->buf[1] = 0xefcdab89; + ctx->buf[2] = 0x98badcfe; + ctx->buf[3] = 0x10325476; + + ctx->bits[0] = 0; + ctx->bits[1] = 0; +} + +/* + * Update context to reflect the concatenation of another buffer full + * of bytes. + */ +void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) +{ + MV_U32 t; + + /* Update bitcount */ + + t = ctx->bits[0]; + if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) + ctx->bits[1]++; /* Carry from low to high */ + ctx->bits[1] += len >> 29; + + t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ + + /* Handle any leading odd-sized chunks */ + + if (t) + { + unsigned char *p = (unsigned char *) ctx->in + t; + + t = 64 - t; + if (len < t) + { + memcpy(p, buf, len); + return; + } + memcpy(p, buf, t); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); + buf += t; + len -= t; + } + /* Process data in 64-byte chunks */ + + while (len >= 64) + { + memcpy(ctx->in, buf, 64); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); + buf += 64; + len -= 64; + } + + /* Handle any remaining bytes of data. */ + + memcpy(ctx->in, buf, len); +} + +/* + * Final wrapup - pad to 64-byte boundary with the bit pattern + * 1 0* (64-bit count of bits processed, MSB-first) + */ +void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) +{ + unsigned count; + unsigned char *p; + + /* Compute number of bytes mod 64 */ + count = (ctx->bits[0] >> 3) & 0x3F; + + /* Set the first char of padding to 0x80. This is safe since there is + always at least one byte free */ + p = ctx->in + count; + *p++ = 0x80; + + /* Bytes of padding needed to make 64 bytes */ + count = 64 - 1 - count; + + /* Pad out to 56 mod 64 */ + if (count < 8) + { + /* Two lots of padding: Pad the first block to 64 bytes */ + memset(p, 0, count); + mvByteReverse(ctx->in, MV_MD5_MAC_LEN); + mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); + + /* Now fill the next block with 56 bytes */ + memset(ctx->in, 0, 56); + } + else + { + /* Pad block to 56 bytes */ + memset(p, 0, count - 8); + } + mvByteReverse(ctx->in, 14); + + /* Append length in bits and transform */ + ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; + ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; + + mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); + mvByteReverse((unsigned char *) ctx->buf, 4); + memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); + memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ +} + +/* The four core functions - F1 is optimized somewhat */ + +/* #define F1(x, y, z) (x & y | ~x & z) */ +#define F1(x, y, z) (z ^ (x & (y ^ z))) +#define F2(x, y, z) F1(z, x, y) +#define F3(x, y, z) (x ^ y ^ z) +#define F4(x, y, z) (y ^ (x | ~z)) + +/* This is the central step in the MD5 algorithm. */ +#define MD5STEP(f, w, x, y, z, data, s) \ + ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) + +/* + * The core of the MD5 algorithm, this alters an existing MD5 hash to + * reflect the addition of 16 longwords of new data. MD5Update blocks + * the data and converts bytes into longwords for this routine. + */ +static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) +{ + register MV_U32 a, b, c, d; + + a = buf[0]; + b = buf[1]; + c = buf[2]; + d = buf[3]; + + MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); + MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); + MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); + MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); + MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); + MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); + MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); + MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); + MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); + MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); + MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); + MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); + MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); + MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); + MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); + MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); + + MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); + MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); + MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); + MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); + MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); + MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); + MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); + MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); + MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); + MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); + MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); + MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); + MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); + MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); + MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); + MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); + + MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); + MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); + MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); + MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); + MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); + MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); + MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); + MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); + MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); + MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); + MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); + MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); + MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); + MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); + MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); + MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); + + MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); + MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); + MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); + MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); + MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); + MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); + MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); + MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); + MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); + MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); + MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); + MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); + MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); + MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); + MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); + MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); + + buf[0] += a; + buf[1] += b; + buf[2] += c; + buf[3] += d; +} + +void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) +{ + MV_MD5_CONTEXT ctx; + + mvMD5Init(&ctx); + mvMD5Update(&ctx, buf, len); + mvMD5Final(digest, &ctx); +} + + +void mvHmacMd5(unsigned char const* text, int text_len, + unsigned char const* key, int key_len, + unsigned char* digest) +{ + int i; + MV_MD5_CONTEXT ctx; + unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ + unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ + + /* start out by storing key in pads */ + memset(k_ipad, 0, 64); + memcpy(k_ipad, key, key_len); + memset(k_opad, 0, 64); + memcpy(k_opad, key, key_len); + + /* XOR key with ipad and opad values */ + for (i=0; i<64; i++) + { + k_ipad[i] ^= 0x36; + k_opad[i] ^= 0x5c; + } + + /* perform inner MD5 */ + mvMD5Init(&ctx); /* init ctx for 1st pass */ + mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ + mvMD5Update(&ctx, text, text_len); /* then text of datagram */ + mvMD5Final(digest, &ctx); /* finish up 1st pass */ + + /* perform outer MD5 */ + mvMD5Init(&ctx); /* init ctx for 2nd pass */ + mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ + mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ + mvMD5Final(digest, &ctx); /* finish up 2nd pass */ +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvMD5.h b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvMD5.h new file mode 100644 index 0000000..d05c6b6 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvMD5.h @@ -0,0 +1,93 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvMD5_h__ +#define __mvMD5_h__ + +#include "mvMD5.h" + +#define MV_MD5_MAC_LEN 16 + + +typedef struct +{ + MV_U32 buf[4]; + MV_U32 bits[2]; + MV_U8 in[64]; + +} MV_MD5_CONTEXT; + +void mvMD5Init(MV_MD5_CONTEXT *context); +void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, + unsigned len); +void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); + +void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); + +void mvHmacMd5(unsigned char const* text, int text_len, + unsigned char const* key, int key_len, + unsigned char* digest); + + +#endif /* __mvMD5_h__ */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvSHA1.c b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvSHA1.c new file mode 100644 index 0000000..0e0786b --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvSHA1.c @@ -0,0 +1,239 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvOs.h" +#include "mvSHA1.h" + +#define SHA1HANDSOFF + +typedef union +{ + MV_U8 c[64]; + MV_U32 l[16]; + +} CHAR64LONG16; + +static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); + +#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) + + +#ifdef MV_CPU_LE +#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ + (rol(block->l[i], 8) & 0x00FF00FF)) +#else +#define blk0(i) block->l[i] +#endif +#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ + block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) + +/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ +#define R0(v,w,x,y,z,i) \ + z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ + w = rol(w, 30); +#define R1(v,w,x,y,z,i) \ + z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ + w = rol(w, 30); +#define R2(v,w,x,y,z,i) \ + z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); +#define R3(v,w,x,y,z,i) \ + z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ + w = rol(w, 30); +#define R4(v,w,x,y,z,i) \ + z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ + w=rol(w, 30); + +/* Hash a single 512-bit block. This is the core of the algorithm. */ +static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) +{ + MV_U32 a, b, c, d, e; + CHAR64LONG16* block; + +#ifdef SHA1HANDSOFF + static MV_U32 workspace[16]; + + block = (CHAR64LONG16 *) workspace; + memcpy(block, buffer, 64); +#else + block = (CHAR64LONG16 *) buffer; +#endif + /* Copy context->state[] to working vars */ + a = state[0]; + b = state[1]; + c = state[2]; + d = state[3]; + e = state[4]; + /* 4 rounds of 20 operations each. Loop unrolled. */ + R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); + R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); + R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); + R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); + R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); + R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); + R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); + R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); + R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); + R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); + R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); + R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); + R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); + R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); + R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); + R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); + R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); + R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); + R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); + R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); + /* Add the working vars back into context.state[] */ + state[0] += a; + state[1] += b; + state[2] += c; + state[3] += d; + state[4] += e; + /* Wipe variables */ + a = b = c = d = e = 0; +} + +void mvSHA1Init(MV_SHA1_CTX* context) +{ + /* SHA1 initialization constants */ + context->state[0] = 0x67452301; + context->state[1] = 0xEFCDAB89; + context->state[2] = 0x98BADCFE; + context->state[3] = 0x10325476; + context->state[4] = 0xC3D2E1F0; + context->count[0] = context->count[1] = 0; +} + + +/* Run your data through this. */ +void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, + unsigned int len) +{ + MV_U32 i, j; + + j = (context->count[0] >> 3) & 63; + if ((context->count[0] += len << 3) < (len << 3)) + context->count[1]++; + context->count[1] += (len >> 29); + if ((j + len) > 63) + { + memcpy(&context->buffer[j], data, (i = 64-j)); + mvSHA1Transform(context->state, context->buffer); + for ( ; i + 63 < len; i += 64) + { + mvSHA1Transform(context->state, &data[i]); + } + j = 0; + } + else + { + i = 0; + } + memcpy(&context->buffer[j], &data[i], len - i); +} + +void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) +{ + MV_U32 i; + MV_U8 finalcount[8]; + + for (i = 0; i < 8; i++) + { + finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> + ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ + } + mvSHA1Update(context, (const unsigned char *) "\200", 1); + while ((context->count[0] & 504) != 448) + { + mvSHA1Update(context, (const unsigned char *) "\0", 1); + } + mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() + */ + for (i = 0; i < 20; i++) + { + digest[i] = (unsigned char) + ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); + } + /* Wipe variables */ + i = 0; + memset(context->buffer, 0, 64); + memset(context->state, 0, 20); + memset(context->count, 0, 8); + memset(finalcount, 0, 8); + +#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ + mvSHA1Transform(context->state, context->buffer); +#endif +} + + +void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) +{ + MV_SHA1_CTX ctx; + + mvSHA1Init(&ctx); + mvSHA1Update(&ctx, buf, len); + mvSHA1Final(digest, &ctx); +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvSHA1.h b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvSHA1.h new file mode 100644 index 0000000..17df9fc --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa/mvSHA1.h @@ -0,0 +1,88 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvSHA1_h__ +#define __mvSHA1_h__ + +#include "mvSHA1.h" + +#define MV_SHA1_MAC_LEN 20 + + +typedef struct +{ + MV_U32 state[5]; + MV_U32 count[2]; + MV_U8 buffer[64]; + +} MV_SHA1_CTX; + +void mvSHA1Init(MV_SHA1_CTX *context); +void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); +void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); + +void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); + + +#endif /* __mvSHA1_h__ */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/cesa_ocf_drv.c b/target/linux/generic/files/crypto/ocf/kirkwood/cesa_ocf_drv.c new file mode 100644 index 0000000..6fb9e09 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/cesa_ocf_drv.c @@ -0,0 +1,1302 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ctrlEnv/sys/mvSysCesa.h" +#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ +#include +#include +#include +#include +#include "mvDebug.h" + +#include "cesa/mvMD5.h" +#include "cesa/mvSHA1.h" + +#include "cesa/mvCesaRegs.h" +#include "cesa/AES/mvAes.h" +#include "cesa/mvLru.h" + +#undef RT_DEBUG +#ifdef RT_DEBUG +static int debug = 1; +module_param(debug, int, 1); +MODULE_PARM_DESC(debug, "Enable debug"); +#undef dprintk +#define dprintk(a...) if (debug) { printk(a); } else +#else +static int debug = 0; +#undef dprintk +#define dprintk(a...) +#endif + + +/* TDMA Regs */ +#define WINDOW_BASE(i) 0xA00 + (i << 3) +#define WINDOW_CTRL(i) 0xA04 + (i << 3) + +/* interrupt handling */ +#undef CESA_OCF_POLLING +#undef CESA_OCF_TASKLET + +#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) +#error "don't use both tasklet and polling mode" +#endif + +extern int cesaReqResources; +/* support for spliting action into 2 actions */ +#define CESA_OCF_SPLIT + +/* general defines */ +#define CESA_OCF_MAX_SES 128 +#define CESA_Q_SIZE 64 + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0) +#define FRAG_PAGE(f) (f).p +#else +#define FRAG_PAGE(f) (f) +#endif + +/* data structures */ +struct cesa_ocf_data { + int cipher_alg; + int auth_alg; + int encrypt_tn_auth; +#define auth_tn_decrypt encrypt_tn_auth + int ivlen; + int digestlen; + short sid_encrypt; + short sid_decrypt; + /* fragment workaround sessions */ + short frag_wa_encrypt; + short frag_wa_decrypt; + short frag_wa_auth; +}; + +/* CESA device data */ +struct cesa_dev { + void __iomem *sram; + void __iomem *reg; + struct mv_cesa_platform_data *plat_data; + int irq; +}; + +#define DIGEST_BUF_SIZE 32 +struct cesa_ocf_process { + MV_CESA_COMMAND cesa_cmd; + MV_CESA_MBUF cesa_mbuf; + MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; + char digest[DIGEST_BUF_SIZE]; + int digest_len; + struct cryptop *crp; + int need_cb; +}; + +/* global variables */ +static int32_t cesa_ocf_id = -1; +static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; +static spinlock_t cesa_lock; +static struct cesa_dev cesa_device; + +/* static APIs */ +static int cesa_ocf_process (device_t, struct cryptop *, int); +static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); +static int cesa_ocf_freesession (device_t, u_int64_t); +static void cesa_callback (unsigned long); +static irqreturn_t cesa_interrupt_handler (int, void *); +#ifdef CESA_OCF_POLLING +static void cesa_interrupt_polling(void); +#endif +#ifdef CESA_OCF_TASKLET +static struct tasklet_struct cesa_ocf_tasklet; +#endif + +static struct timeval tt_start; +static struct timeval tt_end; + +/* + * dummy device structure + */ + +static struct { + softc_device_decl sc_dev; +} mv_cesa_dev; + +static device_method_t mv_cesa_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), + DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), + DEVMETHOD(cryptodev_process, cesa_ocf_process), + DEVMETHOD(cryptodev_kprocess, NULL), +}; + + + +/* Add debug Trace */ +#undef CESA_OCF_TRACE_DEBUG +#ifdef CESA_OCF_TRACE_DEBUG + +#define MV_CESA_USE_TIMER_ID 0 + +typedef struct +{ + int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ + MV_U32 timeStamp; + MV_U32 cause; + MV_U32 realCause; + MV_U32 dmaCause; + int resources; + MV_CESA_REQ* pReqReady; + MV_CESA_REQ* pReqEmpty; + MV_CESA_REQ* pReqProcess; +} MV_CESA_TEST_TRACE; + +#define MV_CESA_TEST_TRACE_SIZE 50 + +static int cesaTestTraceIdx = 0; +static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; + +static void cesaTestTraceAdd(int type) +{ + cesaTestTrace[cesaTestTraceIdx].type = type; + cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); + cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; + cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; + cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; + cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; + cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); + cesaTestTraceIdx++; + if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) + cesaTestTraceIdx = 0; +} + +#else /* CESA_OCF_TRACE_DEBUG */ + +#define cesaTestTraceAdd(x) + +#endif /* CESA_OCF_TRACE_DEBUG */ + +unsigned int +get_usec(unsigned int start) +{ + if(start) { + do_gettimeofday (&tt_start); + return 0; + } + else { + do_gettimeofday (&tt_end); + tt_end.tv_sec -= tt_start.tv_sec; + tt_end.tv_usec -= tt_start.tv_usec; + if (tt_end.tv_usec < 0) { + tt_end.tv_usec += 1000 * 1000; + tt_end.tv_sec -= 1; + } + } + printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); + return (tt_end.tv_usec + tt_end.tv_sec * 1000000); +} + +#ifdef RT_DEBUG +/* + * check that the crp action match the current session + */ +static int +ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { + int count = 0; + int encrypt = 0, decrypt = 0, auth = 0; + struct cryptodesc *crd; + + /* Go through crypto descriptors, processing as we go */ + for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { + if(count > 2) { + printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); + return 1; + } + + /* Encryption /Decryption */ + if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { + /* check that the action is compatible with session */ + if(encrypt || decrypt) { + printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); + return 1; + } + + if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ + if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { + printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); + return 1; + } + encrypt++; + } + else { /* decrypt */ + if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { + printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); + return 1; + } + decrypt++; + } + + } + /* Authentication */ + else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { + /* check that the action is compatible with session */ + if(auth) { + printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); + return 1; + } + if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { + printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); + return 1; + } + if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { + printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); + return 1; + } + auth++; + } + else { + printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); + return 1; + } + } + return 0; + +} +#endif + +/* + * Process a request. + */ +static int +cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) +{ + struct cesa_ocf_process *cesa_ocf_cmd = NULL; + struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; + MV_CESA_COMMAND *cesa_cmd; + struct cryptodesc *crd; + struct cesa_ocf_data *cesa_ocf_cur_ses; + int sid = 0, temp_len = 0, i; + int encrypt = 0, decrypt = 0, auth = 0; + int status; + struct sk_buff *skb = NULL; + struct uio *uiop = NULL; + unsigned char *ivp; + MV_BUF_INFO *p_buf_info; + MV_CESA_MBUF *p_mbuf_info; + unsigned long flags; + + dprintk("%s()\n", __FUNCTION__); + + if( cesaReqResources <= 1 ) { + dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); + return ERESTART; + } + +#ifdef RT_DEBUG + /* Sanity check */ + if (crp == NULL) { + printk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { + printk("%s,%d: EINVAL\n", __FILE__, __LINE__); + crp->crp_etype = EINVAL; + return EINVAL; + } + + sid = crp->crp_sid & 0xffffffff; + if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { + crp->crp_etype = ENOENT; + printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); + return EINVAL; + } +#endif + + sid = crp->crp_sid & 0xffffffff; + crp->crp_etype = 0; + cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; + +#ifdef RT_DEBUG + if(ocf_check_action(crp, cesa_ocf_cur_ses)){ + goto p_error; + } +#endif + + /* malloc a new cesa process */ + cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); + + if (cesa_ocf_cmd == NULL) { + printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); + goto p_error; + } + memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); + + /* init cesa_process */ + cesa_ocf_cmd->crp = crp; + /* always call callback */ + cesa_ocf_cmd->need_cb = 1; + + /* init cesa_cmd for usage of the HALs */ + cesa_cmd = &cesa_ocf_cmd->cesa_cmd; + cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; + cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ + + /* prepare src buffer */ + /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ + /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ + /* from skip to crd_len. */ + p_buf_info = cesa_ocf_cmd->cesa_bufs; + p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; + + p_buf_info += 2; /* save 2 first buffers for IV and digest - + we won't append them to the end since, they + might be places in an unaligned addresses. */ + + p_mbuf_info->pFrags = p_buf_info; + temp_len = 0; + + /* handle SKB */ + if (crp->crp_flags & CRYPTO_F_SKBUF) { + + dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); + skb = (struct sk_buff *) crp->crp_buf; + + if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { + printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); + goto p_error; + } + + p_mbuf_info->mbufSize = skb->len; + temp_len = skb->len; + /* first skb fragment */ + p_buf_info->bufSize = skb_headlen(skb); + p_buf_info->bufVirtPtr = skb->data; + p_buf_info++; + + /* now handle all other skb fragments */ + for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { + skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; + p_buf_info->bufSize = frag->size; + p_buf_info->bufVirtPtr = page_address(FRAG_PAGE(frag->page)) + frag->page_offset; + p_buf_info++; + } + p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; + } + /* handle UIO */ + else if(crp->crp_flags & CRYPTO_F_IOV) { + + dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); + uiop = (struct uio *) crp->crp_buf; + + if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { + printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); + goto p_error; + } + + p_mbuf_info->mbufSize = crp->crp_ilen; + p_mbuf_info->numFrags = uiop->uio_iovcnt; + for(i = 0; i < uiop->uio_iovcnt; i++) { + p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; + p_buf_info->bufSize = uiop->uio_iov[i].iov_len; + temp_len += p_buf_info->bufSize; + dprintk("%s,%d: buf %x-> addr %x, size %x \n" + , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); + p_buf_info++; + } + + } + /* handle CONTIG */ + else { + dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); + p_mbuf_info->numFrags = 1; + p_mbuf_info->mbufSize = crp->crp_ilen; + p_buf_info->bufVirtPtr = crp->crp_buf; + p_buf_info->bufSize = crp->crp_ilen; + temp_len = crp->crp_ilen; + p_buf_info++; + } + + /* Support up to 64K why? cause! */ + if(crp->crp_ilen > 64*1024) { + printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); + goto p_error; + } + + if( temp_len != crp->crp_ilen ) { + printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); + } + + cesa_cmd->pSrc = p_mbuf_info; + cesa_cmd->pDst = p_mbuf_info; + + /* restore p_buf_info to point to first available buf */ + p_buf_info = cesa_ocf_cmd->cesa_bufs; + p_buf_info += 1; + + + /* Go through crypto descriptors, processing as we go */ + for (crd = crp->crp_desc; crd; crd = crd->crd_next) { + + /* Encryption /Decryption */ + if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { + + dprintk("%s,%d: cipher", __FILE__, __LINE__); + + cesa_cmd->cryptoOffset = crd->crd_skip; + cesa_cmd->cryptoLength = crd->crd_len; + + if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ + dprintk(" encrypt \n"); + encrypt++; + + /* handle IV */ + if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ + dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); + cesa_cmd->ivFromUser = 1; + ivp = crd->crd_iv; + + /* + * do we have to copy the IV back to the buffer ? + */ + if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { + dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); + cesa_cmd->ivOffset = crd->crd_inject; + crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, cesa_ocf_cur_ses->ivlen, ivp); + } + else { + dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); + p_mbuf_info->numFrags++; + p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; + p_mbuf_info->pFrags = p_buf_info; + + p_buf_info->bufVirtPtr = ivp; + p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; + p_buf_info--; + + /* offsets */ + cesa_cmd->ivOffset = 0; + cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; + if(auth) { + cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; + cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; + } + } + } + else { /* random IV */ + dprintk("%s,%d: random IV \n", __FILE__, __LINE__); + cesa_cmd->ivFromUser = 0; + + /* + * do we have to copy the IV back to the buffer ? + */ + /* in this mode the HAL will always copy the IV */ + /* given by the session to the ivOffset */ + if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { + cesa_cmd->ivOffset = crd->crd_inject; + } + else { + /* if IV isn't copy, then how will the user know which IV did we use??? */ + printk("%s,%d: EINVAL\n", __FILE__, __LINE__); + goto p_error; + } + } + } + else { /* decrypt */ + dprintk(" decrypt \n"); + decrypt++; + cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; + + /* handle IV */ + if (crd->crd_flags & CRD_F_IV_EXPLICIT) { + dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); + /* append the IV buf to the mbuf */ + cesa_cmd->ivFromUser = 1; + p_mbuf_info->numFrags++; + p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; + p_mbuf_info->pFrags = p_buf_info; + + p_buf_info->bufVirtPtr = crd->crd_iv; + p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; + p_buf_info--; + + /* offsets */ + cesa_cmd->ivOffset = 0; + cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; + if(auth) { + cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; + cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; + } + } + else { + dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); + cesa_cmd->ivFromUser = 0; + cesa_cmd->ivOffset = crd->crd_inject; + } + } + + } + /* Authentication */ + else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { + dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); + auth++; + cesa_cmd->macOffset = crd->crd_skip; + cesa_cmd->macLength = crd->crd_len; + + /* digest + mac */ + cesa_cmd->digestOffset = crd->crd_inject; + } + else { + printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); + goto p_error; + } + } + + dprintk("\n"); + dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); + dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); + dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); + dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); + dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); + if(debug) { + mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); + } + + + /* send action to HAL */ + spin_lock_irqsave(&cesa_lock, flags); + status = mvCesaAction(cesa_cmd); + spin_unlock_irqrestore(&cesa_lock, flags); + + /* action not allowed */ + if(status == MV_NOT_ALLOWED) { +#ifdef CESA_OCF_SPLIT + /* if both encrypt and auth try to split */ + if(auth && (encrypt || decrypt)) { + MV_CESA_COMMAND *cesa_cmd_wa; + + /* malloc a new cesa process and init it */ + cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); + + if (cesa_ocf_cmd_wa == NULL) { + printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); + goto p_error; + } + memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); + cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; + cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; + cesa_ocf_cmd_wa->need_cb = 0; + + /* break requests to two operation, first operation completion won't call callback */ + if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { + cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; + cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; + } + else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { + cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; + cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; + } + else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { + cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; + cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; + } + else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ + cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; + cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; + } + else { + printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); + goto p_error; + } + + /* send the 2 actions to the HAL */ + spin_lock_irqsave(&cesa_lock, flags); + status = mvCesaAction(cesa_cmd_wa); + spin_unlock_irqrestore(&cesa_lock, flags); + + if((status != MV_NO_MORE) && (status != MV_OK)) { + printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); + goto p_error; + } + spin_lock_irqsave(&cesa_lock, flags); + status = mvCesaAction(cesa_cmd); + spin_unlock_irqrestore(&cesa_lock, flags); + + } + /* action not allowed and can't split */ + else +#endif + { + goto p_error; + } + } + + /* Hal Q is full, send again. This should never happen */ + if(status == MV_NO_RESOURCE) { + printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); + if(cesa_ocf_cmd) + kfree(cesa_ocf_cmd); + if(cesa_ocf_cmd_wa) + kfree(cesa_ocf_cmd_wa); + return ERESTART; + } + else if((status != MV_NO_MORE) && (status != MV_OK)) { + printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); + goto p_error; + } + + +#ifdef CESA_OCF_POLLING + cesa_interrupt_polling(); +#endif + cesaTestTraceAdd(5); + + return 0; +p_error: + crp->crp_etype = EINVAL; + if(cesa_ocf_cmd) + kfree(cesa_ocf_cmd); + if(cesa_ocf_cmd_wa) + kfree(cesa_ocf_cmd_wa); + return EINVAL; +} + +/* + * cesa callback. + */ +static void +cesa_callback(unsigned long dummy) +{ + struct cesa_ocf_process *cesa_ocf_cmd = NULL; + struct cryptop *crp = NULL; + MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; + int res_idx = 0,i; + MV_STATUS status; + + dprintk("%s()\n", __FUNCTION__); + +#ifdef CESA_OCF_TASKLET + disable_irq(cesa_device.irq); +#endif + while(MV_TRUE) { + + /* Get Ready requests */ + spin_lock(&cesa_lock); + status = mvCesaReadyGet(&result[res_idx]); + spin_unlock(&cesa_lock); + + cesaTestTraceAdd(2); + + if(status != MV_OK) { +#ifdef CESA_OCF_POLLING + if(status == MV_BUSY) { /* Fragment */ + cesa_interrupt_polling(); + return; + } +#endif + break; + } + res_idx++; + break; + } + + for(i = 0; i < res_idx; i++) { + + if(!result[i].pReqPrv) { + printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); + break; + } + + cesa_ocf_cmd = result[i].pReqPrv; + crp = cesa_ocf_cmd->crp; + + // ignore HMAC error. + //if(result->retCode) + // crp->crp_etype = EIO; + +#if defined(CESA_OCF_POLLING) + if(!cesa_ocf_cmd->need_cb){ + cesa_interrupt_polling(); + } +#endif + if(cesa_ocf_cmd->need_cb) { + if(debug) { + mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); + } + crypto_done(crp); + } + kfree(cesa_ocf_cmd); + } +#ifdef CESA_OCF_TASKLET + enable_irq(cesa_device.irq); +#endif + + cesaTestTraceAdd(3); + + return; +} + +#ifdef CESA_OCF_POLLING +static void +cesa_interrupt_polling(void) +{ + u32 cause; + + dprintk("%s()\n", __FUNCTION__); + + /* Read cause register */ + do { + cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; + + } while (cause == 0); + + /* clear interrupts */ + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + + cesa_callback(0); + + return; +} + +#endif + +/* + * cesa Interrupt polling routine. + */ +static irqreturn_t +cesa_interrupt_handler(int irq, void *arg) +{ + u32 cause; + + dprintk("%s()\n", __FUNCTION__); + + cesaTestTraceAdd(0); + + /* Read cause register */ + cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); + + if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) + { + /* Empty interrupt */ + dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); + return IRQ_HANDLED; + } + + /* clear interrupts */ + MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); + + cesaTestTraceAdd(1); +#ifdef CESA_OCF_TASKLET + tasklet_hi_schedule(&cesa_ocf_tasklet); +#else + cesa_callback(0); +#endif + return IRQ_HANDLED; +} + +/* + * Open a session. + */ +static int +/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ +cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) +{ + u32 status = 0, i; + u32 count = 0, auth = 0, encrypt =0; + struct cesa_ocf_data *cesa_ocf_cur_ses; + MV_CESA_OPEN_SESSION cesa_session; + MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; + + + dprintk("%s()\n", __FUNCTION__); + if (sid == NULL || cri == NULL) { + printk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + /* leave first empty like in other implementations */ + for (i = 1; i < CESA_OCF_MAX_SES; i++) { + if (cesa_ocf_sessions[i] == NULL) + break; + } + + if(i >= CESA_OCF_MAX_SES) { + printk("%s,%d: no more sessions \n", __FILE__, __LINE__); + return EINVAL; + } + + cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); + if (cesa_ocf_sessions[i] == NULL) { + cesa_ocf_freesession(NULL, i); + printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); + return ENOBUFS; + } + dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); + + *sid = i; + cesa_ocf_cur_ses = cesa_ocf_sessions[i]; + memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); + cesa_ocf_cur_ses->sid_encrypt = -1; + cesa_ocf_cur_ses->sid_decrypt = -1; + cesa_ocf_cur_ses->frag_wa_encrypt = -1; + cesa_ocf_cur_ses->frag_wa_decrypt = -1; + cesa_ocf_cur_ses->frag_wa_auth = -1; + + /* init the session */ + memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); + count = 1; + while (cri) { + if(count > 2) { + printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); + goto error; + } + switch (cri->cri_alg) { + case CRYPTO_AES_CBC: + dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); + cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; + cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; + cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; + cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; + if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { + printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); + goto error; + } + memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); + dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); + cesa_ses->cryptoKeyLength = cri->cri_klen/8; + encrypt += count; + break; + case CRYPTO_3DES_CBC: + dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); + cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; + cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; + cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; + cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; + if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { + printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); + goto error; + } + memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); + cesa_ses->cryptoKeyLength = cri->cri_klen/8; + encrypt += count; + break; + case CRYPTO_DES_CBC: + dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); + cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; + cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; + cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; + cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; + if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { + printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); + goto error; + } + memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); + cesa_ses->cryptoKeyLength = cri->cri_klen/8; + encrypt += count; + break; + case CRYPTO_MD5: + case CRYPTO_MD5_HMAC: + dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); + cesa_ocf_cur_ses->auth_alg = cri->cri_alg; + cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; + cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; + if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { + printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); + goto error; + } + cesa_ses->macKeyLength = cri->cri_klen/8; + memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); + cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; + auth += count; + break; + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); + cesa_ocf_cur_ses->auth_alg = cri->cri_alg; + cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; + cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; + if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { + printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); + goto error; + } + cesa_ses->macKeyLength = cri->cri_klen/8; + memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); + cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; + auth += count; + break; + default: + printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); + goto error; + } + cri = cri->cri_next; + count++; + } + + if((encrypt > 2) || (auth > 2)) { + printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); + goto error; + } + /* create new sessions in HAL */ + if(encrypt) { + cesa_ses->operation = MV_CESA_CRYPTO_ONLY; + /* encrypt session */ + if(auth == 1) { + cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; + } + else if(auth == 2) { + cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; + cesa_ocf_cur_ses->encrypt_tn_auth = 1; + } + else { + cesa_ses->operation = MV_CESA_CRYPTO_ONLY; + } + cesa_ses->direction = MV_CESA_DIR_ENCODE; + status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); + if(status != MV_OK) { + printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); + goto error; + } + /* decrypt session */ + if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { + cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; + } + else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { + cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; + } + cesa_ses->direction = MV_CESA_DIR_DECODE; + status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); + if(status != MV_OK) { + printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); + goto error; + } + + /* preapre one action sessions for case we will need to split an action */ +#ifdef CESA_OCF_SPLIT + if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || + ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { + /* open one session for encode and one for decode */ + cesa_ses->operation = MV_CESA_CRYPTO_ONLY; + cesa_ses->direction = MV_CESA_DIR_ENCODE; + status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); + if(status != MV_OK) { + printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); + goto error; + } + + cesa_ses->direction = MV_CESA_DIR_DECODE; + status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); + if(status != MV_OK) { + printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); + goto error; + } + /* open one session for auth */ + cesa_ses->operation = MV_CESA_MAC_ONLY; + cesa_ses->direction = MV_CESA_DIR_ENCODE; + status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); + if(status != MV_OK) { + printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); + goto error; + } + } +#endif + } + else { /* only auth */ + cesa_ses->operation = MV_CESA_MAC_ONLY; + cesa_ses->direction = MV_CESA_DIR_ENCODE; + status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); + if(status != MV_OK) { + printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); + goto error; + } + } + + return 0; +error: + cesa_ocf_freesession(NULL, *sid); + return EINVAL; + +} + + +/* + * Free a session. + */ +static int +cesa_ocf_freesession(device_t dev, u_int64_t tid) +{ + struct cesa_ocf_data *cesa_ocf_cur_ses; + u_int32_t sid = CRYPTO_SESID2LID(tid); + //unsigned long flags; + + dprintk("%s() %d \n", __FUNCTION__, sid); + if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { + printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); + return(EINVAL); + } + + /* Silently accept and return */ + if (sid == 0) + return(0); + + /* release session from HAL */ + cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; + if (cesa_ocf_cur_ses->sid_encrypt != -1) { + mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); + } + if (cesa_ocf_cur_ses->sid_decrypt != -1) { + mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); + } + if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { + mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); + } + if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { + mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); + } + if (cesa_ocf_cur_ses->frag_wa_auth != -1) { + mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); + } + + kfree(cesa_ocf_cur_ses); + cesa_ocf_sessions[sid] = NULL; + + return 0; +} + + +/* TDMA Window setup */ + +static void __init +setup_tdma_mbus_windows(struct cesa_dev *dev) +{ + int i; + + for (i = 0; i < 4; i++) { + writel(0, dev->reg + WINDOW_BASE(i)); + writel(0, dev->reg + WINDOW_CTRL(i)); + } + + for (i = 0; i < dev->plat_data->dram->num_cs; i++) { + struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; + writel( + ((cs->size - 1) & 0xffff0000) | + (cs->mbus_attr << 8) | + (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, + dev->reg + WINDOW_CTRL(i) + ); + writel(cs->base, dev->reg + WINDOW_BASE(i)); + } +} + +/* + * our driver startup and shutdown routines + */ +static int +mv_cesa_ocf_init(struct platform_device *pdev) +{ +#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) + if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) + { + dprintk("CESA is not mapped to this CPU\n"); + return -ENODEV; + } +#endif + + dprintk("%s\n", __FUNCTION__); + memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); + softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); + cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); + + if (cesa_ocf_id < 0) + panic("MV CESA crypto device cannot initialize!"); + + dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); + + /* CESA unit is auto power on off */ +#if 0 + if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) + { + printk("\nWarning CESA %d is Powered Off\n",0); + return EINVAL; + } +#endif + + memset(&cesa_device, 0, sizeof(struct cesa_dev)); + /* Get the IRQ, and crypto memory regions */ + { + struct resource *res; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); + + if (!res) + return -ENXIO; + + cesa_device.sram = ioremap(res->start, res->end - res->start + 1); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); + + if (!res) { + iounmap(cesa_device.sram); + return -ENXIO; + } + cesa_device.reg = ioremap(res->start, res->end - res->start + 1); + cesa_device.irq = platform_get_irq(pdev, 0); + cesa_device.plat_data = pdev->dev.platform_data; + setup_tdma_mbus_windows(&cesa_device); + + } + + + if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, + NULL) ) { + printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); + return EINVAL; + } + + /* clear and unmask Int */ + MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); +#ifndef CESA_OCF_POLLING + MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); +#endif +#ifdef CESA_OCF_TASKLET + tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); +#endif + /* register interrupt */ + if( request_irq( cesa_device.irq, cesa_interrupt_handler, + 0, "cesa", &cesa_ocf_id) < 0) { + printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); + return EINVAL; + } + + + memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); + +#define REGISTER(alg) \ + crypto_register(cesa_ocf_id, alg, 0,0) + REGISTER(CRYPTO_AES_CBC); + REGISTER(CRYPTO_DES_CBC); + REGISTER(CRYPTO_3DES_CBC); + REGISTER(CRYPTO_MD5); + REGISTER(CRYPTO_MD5_HMAC); + REGISTER(CRYPTO_SHA1); + REGISTER(CRYPTO_SHA1_HMAC); +#undef REGISTER + + return 0; +} + +static void +mv_cesa_ocf_exit(struct platform_device *pdev) +{ + dprintk("%s()\n", __FUNCTION__); + + crypto_unregister_all(cesa_ocf_id); + cesa_ocf_id = -1; + iounmap(cesa_device.reg); + iounmap(cesa_device.sram); + free_irq(cesa_device.irq, NULL); + + /* mask and clear Int */ + MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); + MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); + + + if( MV_OK != mvCesaFinish() ) { + printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); + return; + } +} + + +void cesa_ocf_debug(void) +{ + +#ifdef CESA_OCF_TRACE_DEBUG + { + int i, j; + j = cesaTestTraceIdx; + mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); + for(i=0; i= _1G) + { + mvOsOutput("%3dGB ", size / _1G); + size %= _1G; + if(size) + mvOsOutput("+"); + } + if(size >= _1M ) + { + mvOsOutput("%3dMB ", size / _1M); + size %= _1M; + if(size) + mvOsOutput("+"); + } + if(size >= _1K) + { + mvOsOutput("%3dKB ", size / _1K); + size %= _1K; + if(size) + mvOsOutput("+"); + } + if(size > 0) + { + mvOsOutput("%3dB ", size); + } +} + +/******************************************************************************* +* mvHexToBin - Convert hex to binary +* +* DESCRIPTION: +* This function Convert hex to binary. +* +* INPUT: +* pHexStr - hex buffer pointer. +* size - Size to convert. +* +* OUTPUT: +* pBin - Binary buffer pointer. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) +{ + int j, i; + char tmp[3]; + MV_U8 byte; + + for(j=0, i=0; j> 1; + result++; + } + return result; +} + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h new file mode 100644 index 0000000..c8e9ce1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCommon.h @@ -0,0 +1,308 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + +#ifndef __INCmvCommonh +#define __INCmvCommonh + +#include "mvTypes.h" + +/* Swap tool */ + +/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ +#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4)) + +/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ +#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ + ((X&0xf0) >> 4) | \ + ((X&0xf00) << 4) | \ + ((X&0xf000) >> 4) | \ + ((X&0xf0000) << 4) | \ + ((X&0xf00000) >> 4) | \ + ((X&0xf000000) << 4) | \ + ((X&0xf0000000) >> 4)) + +/* 16bit byte swap. For example 0x1122 -> 0x2211 */ +#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) + +/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ +#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ + (((X)&0xff00)<<8) | \ + (((X)&0xff0000)>>8) | \ + (((X)&0xff000000)>>24)) + +/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ +#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ + (((X)&0xff00ULL)<<40) | \ + (((X)&0xff0000ULL)<<24) | \ + (((X)&0xff000000ULL)<<8) | \ + (((X)&0xff00000000ULL)>>8) | \ + (((X)&0xff0000000000ULL)>>24) | \ + (((X)&0xff000000000000ULL)>>40) | \ + (((X)&0xff00000000000000ULL)>>56))) + +/* Endianess macros. */ +#if defined(MV_CPU_LE) + #define MV_16BIT_LE(X) (X) + #define MV_32BIT_LE(X) (X) + #define MV_64BIT_LE(X) (X) + #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) + #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) +#elif defined(MV_CPU_BE) + #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) + #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) + #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) + #define MV_16BIT_BE(X) (X) + #define MV_32BIT_BE(X) (X) + #define MV_64BIT_BE(X) (X) +#else + #error "CPU endianess isn't defined!\n" +#endif + + +/* Bit field definitions */ +#define NO_BIT 0x00000000 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +/* Handy sizes */ +#define _1K 0x00000400 +#define _2K 0x00000800 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +/* Tclock and Sys clock define */ +#define _100MHz 100000000 +#define _125MHz 125000000 +#define _133MHz 133333334 +#define _150MHz 150000000 +#define _160MHz 160000000 +#define _166MHz 166666667 +#define _175MHz 175000000 +#define _178MHz 178000000 +#define _183MHz 183333334 +#define _187MHz 187000000 +#define _192MHz 192000000 +#define _194MHz 194000000 +#define _200MHz 200000000 +#define _233MHz 233333334 +#define _250MHz 250000000 +#define _266MHz 266666667 +#define _300MHz 300000000 + +/* For better address window table readability */ +#define EN MV_TRUE +#define DIS MV_FALSE +#define N_A -1 /* Not applicable */ + +/* Cache configuration options for memory (DRAM, SRAM, ... ) */ + +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + + +/* Macro for testing aligment. Positive if number is NOT aligned */ +#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) + +/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ +#define MV_ALIGN_UP(number, align) \ +(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) + +/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ +#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) + +/* This macro returns absolute value */ +#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) + + +/* Bit fields manipulation macros */ + +/* An integer word which its 'x' bit is set */ +#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) + +/* Checks wheter bit 'x' in integer word is set */ +#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) + +/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ +#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) + +/* Set bit 'x' in integer word (RMW) */ +#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) + +/* Invert bit 'x' in integer word (RMW) */ +#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) + +/* Get the min between 'a' or 'b' */ +#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) + +/* Get the max between 'a' or 'b' */ +#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) + +/* Temporary */ +#define mvOsDivide(num, div) \ +({ \ + int i=0, rem=(num); \ + \ + while(rem >= (div)) \ + { \ + rem -= (div); \ + i++; \ + } \ + (i); \ +}) + +/* Temporary */ +#define mvOsReminder(num, div) \ +({ \ + int rem = (num); \ + \ + while(rem >= (div)) \ + rem -= (div); \ + (rem); \ +}) + +#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ + ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) + +#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) + +#ifndef MV_ASMLANGUAGE +/* mvCommon API list */ + +MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); +void mvAsciiToHex(const char* asciiStr, char* hexStr); +void mvBinToHex(const MV_U8* bin, char* hexStr, int size); +void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); + +MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); +MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); +void mvSizePrint(MV_U32); + +MV_U32 mvLog2(MV_U32 num); + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __INCmvCommonh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt new file mode 100644 index 0000000..38a9264 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.4 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.c new file mode 100644 index 0000000..087f36d --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.c @@ -0,0 +1,326 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + +/* includes */ +#include "mvOs.h" +#include "mv802_3.h" +#include "mvCommon.h" +#include "mvDebug.h" + +/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros + * mvDebug - map of bits (one for each module) bit=1 means enable + * debug code and messages for this module + * mvModuleDebug - array of 32 bits varables one for each module + */ +MV_U32 mvDebug = 0; +MV_U32 mvDebugModules[MV_MODULE_MAX]; + +/* Init mvModuleDebug array to default values */ +void mvDebugInit(void) +{ + int bit; + + mvDebug = 0; + for(bit=0; bit 0) + { + mvOsPrintf("%08x: ", memAddr); + i = 0; + /* 32 bytes in the line */ + while(i < 32) + { + if(memAddr >= (MV_U32)addr) + { + switch(access) + { + case 1: + if( memAddr == CPU_PHY_MEM(memAddr) ) + { + mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); + } + else + { + mvOsPrintf("%02x ", *((MV_U8*)memAddr)); + } + break; + + case 2: + if( memAddr == CPU_PHY_MEM(memAddr) ) + { + mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); + } + else + { + mvOsPrintf("%04x ", *((MV_U16*)memAddr)); + } + break; + + case 4: + if( memAddr == CPU_PHY_MEM(memAddr) ) + { + mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); + } + else + { + mvOsPrintf("%08x ", *((MV_U32*)memAddr)); + } + break; + } + } + else + { + for(j=0; j<(access*2+1); j++) + mvOsPrintf(" "); + } + i += access; + memAddr += access; + size -= access; + if(size <= 0) + break; + } + mvOsPrintf("\n"); + } +} + +void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) +{ + if(pBufInfo == NULL) + { + mvOsPrintf("\n!!! pBufInfo = NULL\n"); + return; + } + mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", + (unsigned int)pBufInfo, + (unsigned int)pBufInfo->cmdSts, + (unsigned int)pBufInfo->pBuff, + (unsigned int)pBufInfo->bufSize); + mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", + (unsigned int)pBufInfo->pData, + (unsigned int)pBufInfo->byteCnt, + (unsigned int)pBufInfo->pNextBufInfo, + (unsigned int)pBufInfo->userInfo1, + (unsigned int)pBufInfo->userInfo2); + if(pBufInfo->pData != NULL) + { + if(size > pBufInfo->byteCnt) + size = pBufInfo->byteCnt; + mvDebugMemDump(pBufInfo->pData, size, access); + } +} + +void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) +{ + int frag, len; + + if(pPktInfo == NULL) + { + mvOsPrintf("\n!!! pPktInfo = NULL\n"); + return; + } + mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", + pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, + pPktInfo->pFrags, pPktInfo->osInfo); + + for(frag=0; fragnumFrags; frag++) + { + mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", + frag, pPktInfo->pFrags[frag].bufVirtPtr, + pPktInfo->pFrags[frag].bufSize); + if(size > 0) + { + len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); + mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); + size -= len; + } + } + +} + +void mvDebugPrintIpAddr(MV_U32 ipAddr) +{ + mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), + ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); +} + +void mvDebugPrintMacAddr(const MV_U8* pMacAddr) +{ + int i; + + mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); + for(i=1; ibegin = 0; + pTimeEntry->count = count; + pTimeEntry->end = 0; + pTimeEntry->left = pTimeEntry->count; + pTimeEntry->total = 0; + pTimeEntry->min = 0xFFFFFFFF; + pTimeEntry->max = 0x0; + strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); + pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; +} + +/* Print out MV_DEBUG_TIMES entry */ +void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) +{ + int num; + + if(isTitle == MV_TRUE) + mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); + + num = pTimeEntry->count-pTimeEntry->left; + if(num > 0) + { + mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", + pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, + pTimeEntry->min, pTimeEntry->max); + } +} + +/* Update MV_DEBUG_TIMES entry */ +void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) +{ + MV_U32 delta; + + if(pTimeEntry->left > 0) + { + if(pTimeEntry->end <= pTimeEntry->begin) + { + delta = pTimeEntry->begin - pTimeEntry->end; + } + else + { + delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; + } + pTimeEntry->total += delta; + + if(delta < pTimeEntry->min) + pTimeEntry->min = delta; + + if(delta > pTimeEntry->max) + pTimeEntry->max = delta; + + pTimeEntry->left--; + } +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.h new file mode 100644 index 0000000..e4975be --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDebug.h @@ -0,0 +1,178 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + + +#ifndef __INCmvDebugh +#define __INCmvDebugh + +/* includes */ +#include "mvTypes.h" + +typedef enum +{ + MV_MODULE_INVALID = -1, + MV_MODULE_ETH = 0, + MV_MODULE_IDMA, + MV_MODULE_XOR, + MV_MODULE_TWASI, + MV_MODULE_MGI, + MV_MODULE_USB, + MV_MODULE_CESA, + + MV_MODULE_MAX +}MV_MODULE_ID; + +/* Define generic flags useful for most of modules */ +#define MV_DEBUG_FLAG_ALL (0) +#define MV_DEBUG_FLAG_INIT (1 << 0) +#define MV_DEBUG_FLAG_RX (1 << 1) +#define MV_DEBUG_FLAG_TX (1 << 2) +#define MV_DEBUG_FLAG_ERR (1 << 3) +#define MV_DEBUG_FLAG_TRACE (1 << 4) +#define MV_DEBUG_FLAG_DUMP (1 << 5) +#define MV_DEBUG_FLAG_CACHE (1 << 6) +#define MV_DEBUG_FLAG_IOCTL (1 << 7) +#define MV_DEBUG_FLAG_STATS (1 << 8) + +extern MV_U32 mvDebug; +extern MV_U32 mvDebugModules[MV_MODULE_MAX]; + +#ifdef MV_DEBUG +# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg +# define MV_DEBUG_CODE(module, flags, code) code +#elif defined(MV_RT_DEBUG) +# define MV_DEBUG_PRINT(module, flags, msg) \ + if( (mvDebug & (1<<(module))) && \ + ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ + mvOsPrintf msg +# define MV_DEBUG_CODE(module, flags, code) \ + if( (mvDebug & (1<<(module))) && \ + ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ + code +#else +# define MV_DEBUG_PRINT(module, flags, msg) +# define MV_DEBUG_CODE(module, flags, code) +#endif + + + +/* typedefs */ + +/* time measurement structure used to check how much time pass between + * two points + */ +typedef struct { + char name[20]; /* name of the entry */ + unsigned long begin; /* time measured on begin point */ + unsigned long end; /* time measured on end point */ + unsigned long total; /* Accumulated time */ + unsigned long left; /* The rest measurement actions */ + unsigned long count; /* Maximum measurement actions */ + unsigned long min; /* Minimum time from begin to end */ + unsigned long max; /* Maximum time from begin to end */ +} MV_DEBUG_TIMES; + + +/* mvDebug.h API list */ + +/****** Error Recording ******/ + +/* Dump memory in specific format: + * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 + */ +void mvDebugMemDump(void* addr, int size, int access); + +void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); + +void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); + +void mvDebugPrintIpAddr(MV_U32 ipAddr); + +void mvDebugPrintMacAddr(const MV_U8* pMacAddr); + +/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ + +/* Reset MV_DEBUG_TIMES entry */ +void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); + +/* Update MV_DEBUG_TIMES entry */ +void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); + +/* Print out MV_DEBUG_TIMES entry */ +void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); + + +/******** General ***********/ + +/* Change value of mvDebugPrint global variable */ + +void mvDebugInit(void); +void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); +void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); +void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); + + +#endif /* __INCmvDebug.h */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h new file mode 100644 index 0000000..4782094 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h @@ -0,0 +1,225 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceIdh +#define __INCmvDeviceIdh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +#define MARVELL_VEN_ID 0x11ab + +/* Disco-3 */ +#define MV64460_DEV_ID 0x6480 +#define MV64460B_DEV_ID 0x6485 +#define MV64430_DEV_ID 0x6420 + +/* Disco-5 */ +#define MV64560_DEV_ID 0x6450 + +/* Disco-6 */ +#define MV64660_DEV_ID 0x6460 + +/* Orion */ +#define MV_1181_DEV_ID 0x1181 +#define MV_5181_DEV_ID 0x5181 +#define MV_5281_DEV_ID 0x5281 +#define MV_5182_DEV_ID 0x5182 +#define MV_8660_DEV_ID 0x8660 +#define MV_5180_DEV_ID 0x5180 +#define MV_5082_DEV_ID 0x5082 +#define MV_1281_DEV_ID 0x1281 +#define MV_6082_DEV_ID 0x6082 +#define MV_6183_DEV_ID 0x6183 +#define MV_6183L_DEV_ID 0x6083 + +#define MV_5281_D0_REV 0x4 +#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) +#define MV_5281_D0_NAME "88F5281 D0" + +#define MV_5281_D1_REV 0x5 +#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) +#define MV_5281_D1_NAME "88F5281 D1" + +#define MV_5281_D2_REV 0x6 +#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) +#define MV_5281_D2_NAME "88F5281 D2" + + +#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ +#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ +#define MV_5181_B0_REV 0x2 +#define MV_5181_B1_REV 0x3 +#define MV_5182_A1_REV 0x1 +#define MV_5180N_B1_REV 0x3 +#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) + + + +/* kw */ +#define MV_6281_DEV_ID 0x6281 +#define MV_6192_DEV_ID 0x6192 +#define MV_6190_DEV_ID 0x6190 +#define MV_6180_DEV_ID 0x6180 + +#define MV_6281_A0_REV 0x2 +#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) +#define MV_6281_A0_NAME "88F6281 A0" + +#define MV_6192_A0_REV 0x2 +#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) +#define MV_6192_A0_NAME "88F6192 A0" + +#define MV_6190_A0_REV 0x2 +#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) +#define MV_6190_A0_NAME "88F6190 A0" + +#define MV_6180_A0_REV 0x2 +#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) +#define MV_6180_A0_NAME "88F6180 A0" + +#define MV_6281_A1_REV 0x3 +#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) +#define MV_6281_A1_NAME "88F6281 A1" + +#define MV_6192_A1_REV 0x3 +#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) +#define MV_6192_A1_NAME "88F6192 A1" + +#define MV_6190_A1_REV 0x3 +#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) +#define MV_6190_A1_NAME "88F6190 A1" + +#define MV_6180_A1_REV 0x3 +#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) +#define MV_6180_A1_NAME "88F6180 A1" + +#define MV_88F6XXX_A0_REV 0x2 +#define MV_88F6XXX_A1_REV 0x3 +/* Disco-Duo */ +#define MV_78XX0_ZY_DEV_ID 0x6381 +#define MV_78XX0_ZY_NAME "MV78X00" + +#define MV_78XX0_Z0_REV 0x1 +#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) +#define MV_78XX0_Z0_NAME "78X00 Z0" + +#define MV_78XX0_Y0_REV 0x2 +#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) +#define MV_78XX0_Y0_NAME "78X00 Y0" + +#define MV_78XX0_DEV_ID 0x7800 +#define MV_78XX0_NAME "MV78X00" + +#define MV_76100_DEV_ID 0x7610 +#define MV_78200_DEV_ID 0x7820 +#define MV_78100_DEV_ID 0x7810 +#define MV_78XX0_A0_REV 0x1 +#define MV_78XX0_A1_REV 0x2 + +#define MV_76100_NAME "MV76100" +#define MV_78100_NAME "MV78100" +#define MV_78200_NAME "MV78200" + +#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) +#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) +#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) + +#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) +#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) +#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) + +#define MV_76100_A0_NAME "MV76100 A0" +#define MV_78100_A0_NAME "MV78100 A0" +#define MV_78200_A0_NAME "MV78200 A0" +#define MV_78XX0_A0_NAME "MV78XX0 A0" + +#define MV_76100_A1_NAME "MV76100 A1" +#define MV_78100_A1_NAME "MV78100 A1" +#define MV_78200_A1_NAME "MV78200 A1" +#define MV_78XX0_A1_NAME "MV78XX0 A1" + +/*MV88F632X family*/ +#define MV_6321_DEV_ID 0x6321 +#define MV_6322_DEV_ID 0x6322 +#define MV_6323_DEV_ID 0x6323 + +#define MV_6321_NAME "88F6321" +#define MV_6322_NAME "88F6322" +#define MV_6323_NAME "88F6323" + +#define MV_632X_A1_REV 0x2 + +#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) +#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) +#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) + +#define MV_6321_A1_NAME "88F6321 A1" +#define MV_6322_A1_NAME "88F6322 A1" +#define MV_6323_A1_NAME "88F6323 A1" + + +#endif /* __INCmvDeviceIdh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h new file mode 100644 index 0000000..3bfcfe1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h @@ -0,0 +1,73 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvHalVerh +#define __INCmvHalVerh + +/* Defines */ +#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" +#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" + +#endif /* __INCmvHalVerh */ \ No newline at end of file diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.c new file mode 100644 index 0000000..41ca7ce --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvQueue.c +* +* FILENAME: $Workfile: mvStack.c $ +* REVISION: $Revision: 1.1 $ +* LAST UPDATE: $Modtime: $ +* +* DESCRIPTION: +* This file implements simple Stack LIFO functionality. +*******************************************************************************/ + +/* includes */ +#include "mvOs.h" +#include "mvTypes.h" +#include "mvDebug.h" +#include "mvStack.h" + +/* defines */ + + +/* Public functions */ + + +/* Purpose: Create new stack + * Inputs: + * - MV_U32 noOfElements - maximum number of elements in the stack. + * Each element 4 bytes size + * Return: void* - pointer to created stack. + */ +void* mvStackCreate(int numOfElements) +{ + MV_STACK* pStack; + MV_U32* pStackElements; + + pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); + pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); + if( (pStack == NULL) || (pStackElements == NULL) ) + { + mvOsPrintf("mvStack: Can't create new stack\n"); + return NULL; + } + memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); + pStack->numOfElements = numOfElements; + pStack->stackIdx = 0; + pStack->stackElements = pStackElements; + + return pStack; +} + +/* Purpose: Delete existing stack + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function + * + * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. + * MV_OK - Success. + */ +MV_STATUS mvStackDelete(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + if( (pStack == NULL) || (pStack->stackElements == NULL) ) + return MV_NOT_FOUND; + + mvOsFree(pStack->stackElements); + mvOsFree(pStack); + + return MV_OK; +} + + +/* PrintOut status of the stack */ +void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) +{ + int i; + MV_STACK* pStack = (MV_STACK*)stackHndl; + + mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", + stackHndl, pStack->stackElements, pStack->numOfElements, + pStack->stackIdx); + if(isPrintElements == MV_TRUE) + { + for(i=0; istackIdx; i++) + { + mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); + } + } +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.h new file mode 100644 index 0000000..e247e61 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvStack.h @@ -0,0 +1,140 @@ +/******************************************************************************* +* Copyright 2003, Marvell Semiconductor Israel LTD. * +* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * +* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * +* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * +* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * +* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * +* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * +* * +* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * +* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * +* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * +* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * +******************************************************************************** +* mvStack.h - Header File for : +* +* FILENAME: $Workfile: mvStack.h $ +* REVISION: $Revision: 1.1 $ +* LAST UPDATE: $Modtime: $ +* +* DESCRIPTION: +* This file defines simple Stack (LIFO) functionality. +* +*******************************************************************************/ + +#ifndef __mvStack_h__ +#define __mvStack_h__ + + +/* includes */ +#include "mvTypes.h" + + +/* defines */ + + +/* typedefs */ +/* Data structure describes general purpose Stack */ +typedef struct +{ + int stackIdx; + int numOfElements; + MV_U32* stackElements; +} MV_STACK; + +static INLINE MV_BOOL mvStackIsFull(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + if(pStack->stackIdx == pStack->numOfElements) + return MV_TRUE; + + return MV_FALSE; +} + +static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + if(pStack->stackIdx == 0) + return MV_TRUE; + + return MV_FALSE; +} +/* Purpose: Push new element to stack + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. + * - MV_U32 value - New element. + * + * Return: MV_STATUS MV_FULL - Failure. Stack is full. + * MV_OK - Success. Element is put to stack. + */ +static INLINE void mvStackPush(void* stackHndl, MV_U32 value) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + +#ifdef MV_RT_DEBUG + if(pStack->stackIdx == pStack->numOfElements) + { + mvOsPrintf("mvStackPush: Stack is FULL\n"); + return; + } +#endif /* MV_RT_DEBUG */ + + pStack->stackElements[pStack->stackIdx] = value; + pStack->stackIdx++; +} + +/* Purpose: Pop element from the top of stack and copy it to "pValue" + * Inputs: + * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. + * - MV_U32 value - Element in the top of stack. + * + * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. + * MV_OK - Success. Element is removed from the stack and + * copied to pValue argument + */ +static INLINE MV_U32 mvStackPop(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + +#ifdef MV_RT_DEBUG + if(pStack->stackIdx == 0) + { + mvOsPrintf("mvStackPop: Stack is EMPTY\n"); + return 0; + } +#endif /* MV_RT_DEBUG */ + + pStack->stackIdx--; + return pStack->stackElements[pStack->stackIdx]; +} + +static INLINE int mvStackIndex(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + return pStack->stackIdx; +} + +static INLINE int mvStackFreeElements(void* stackHndl) +{ + MV_STACK* pStack = (MV_STACK*)stackHndl; + + return (pStack->numOfElements - pStack->stackIdx); +} + +/* mvStack.h API list */ + +/* Create new Stack */ +void* mvStackCreate(int numOfElements); + +/* Delete existing stack */ +MV_STATUS mvStackDelete(void* stackHndl); + +/* Print status of the stack */ +void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); + +#endif /* __mvStack_h__ */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvTypes.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvTypes.h new file mode 100644 index 0000000..de212a1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/mvTypes.h @@ -0,0 +1,245 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvTypesh +#define __INCmvTypesh + +/* Defines */ + +/* The following is a list of Marvell status */ +#define MV_ERROR (-1) +#define MV_OK (0x00) /* Operation succeeded */ +#define MV_FAIL (0x01) /* Operation failed */ +#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ +#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ +#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ +#define MV_BAD_PTR (0x05) /* Illegal pointer value */ +#define MV_BAD_SIZE (0x06) /* Illegal size */ +#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ +#define MV_SET_ERROR (0x08) /* Set operation failed */ +#define MV_GET_ERROR (0x09) /* Get operation failed */ +#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ +#define MV_NOT_FOUND (0x0B) /* Item not found */ +#define MV_NO_MORE (0x0C) /* No more items found */ +#define MV_NO_SUCH (0x0D) /* No such item */ +#define MV_TIMEOUT (0x0E) /* Time Out */ +#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ +#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ +#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ +#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ +#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ +#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ +#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ +#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ +#define MV_HW_ERROR (0x17) /* Hardware error */ +#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ +#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ +#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ +#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ +#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ +#define MV_NOT_STARTED (0x1D) /* Not started yet */ +#define MV_BUSY (0x1E) /* Item is busy. */ +#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ +#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ +#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ +#define MV_WRITE_PROTECT (0x22) /* Write protected */ + + +#define MV_INVALID (int)(-1) + +#define MV_FALSE 0 +#define MV_TRUE (!(MV_FALSE)) + + +#ifndef NULL +#define NULL ((void*)0) +#endif + + +#ifndef MV_ASMLANGUAGE +/* typedefs */ + +typedef char MV_8; +typedef unsigned char MV_U8; + +typedef int MV_32; +typedef unsigned int MV_U32; + +typedef short MV_16; +typedef unsigned short MV_U16; + +#ifdef MV_PPC64 +typedef long MV_64; +typedef unsigned long MV_U64; +#else +typedef long long MV_64; +typedef unsigned long long MV_U64; +#endif + +typedef long MV_LONG; /* 32/64 */ +typedef unsigned long MV_ULONG; /* 32/64 */ + +typedef int MV_STATUS; +typedef int MV_BOOL; +typedef void MV_VOID; +typedef float MV_FLOAT; + +typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ +typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ +typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ +typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ + +typedef MV_U32 MV_KHZ; +typedef MV_U32 MV_MHZ; +typedef MV_U32 MV_HZ; + + +/* This enumerator describes the set of commands that can be applied on */ +/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ +/* status (see MV_STATE enumerator) */ +/* Start can be applied only when status is IDLE */ +/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ +/* Pause can be applied only when status is ACTIVE */ +/* Restart can be applied only when status is PAUSED */ +typedef enum _mvCommand +{ + MV_START, /* Start */ + MV_STOP, /* Stop */ + MV_PAUSE, /* Pause */ + MV_RESTART /* Restart */ +} MV_COMMAND; + +/* This enumerator describes the set of state conditions. */ +/* Moving from one state to other is stricted. */ +typedef enum _mvState +{ + MV_IDLE, + MV_ACTIVE, + MV_PAUSED, + MV_UNDEFINED_STATE +} MV_STATE; + + +/* This structure describes address space window. Window base can be */ +/* 64 bit, window size up to 4GB */ +typedef struct _mvAddrWin +{ + MV_U32 baseLow; /* 32bit base low */ + MV_U32 baseHigh; /* 32bit base high */ + MV_U32 size; /* 32bit size */ +}MV_ADDR_WIN; + +/* This binary enumerator describes protection attribute status */ +typedef enum _mvProtRight +{ + ALLOWED, /* Protection attribute allowed */ + FORBIDDEN /* Protection attribute forbidden */ +}MV_PROT_RIGHT; + +/* Unified struct for Rx and Tx packet operations. The user is required to */ +/* be familier only with Tx/Rx descriptor command status. */ +typedef struct _bufInfo +{ + MV_U32 cmdSts; /* Tx/Rx command status */ + MV_U16 byteCnt; /* Size of valid data in the buffer */ + MV_U16 bufSize; /* Total size of the buffer */ + MV_U8 *pBuff; /* Pointer to Buffer */ + MV_U8 *pData; /* Pointer to data in the Buffer */ + MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ + MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ + struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ +} BUF_INFO; + +/* This structure contains information describing one of buffers + * (fragments) they are built Ethernet packet. + */ +typedef struct +{ + MV_U8* bufVirtPtr; + MV_ULONG bufPhysAddr; + MV_U32 bufSize; + MV_U32 dataSize; + MV_U32 memHandle; + MV_32 bufAddrShift; +} MV_BUF_INFO; + +/* This structure contains information describing Ethernet packet. + * The packet can be divided for few buffers (fragments) + */ +typedef struct +{ + MV_ULONG osInfo; + MV_BUF_INFO *pFrags; + MV_U32 status; + MV_U16 pktSize; + MV_U16 numFrags; + MV_U32 ownerId; + MV_U32 fragIP; +} MV_PKT_INFO; + +#endif /* MV_ASMLANGUAGE */ + +#endif /* __INCmvTypesh */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.c new file mode 100644 index 0000000..644fd02 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.c @@ -0,0 +1,110 @@ +#include +#include +#include +#include "dbg-trace.h" + +#define TRACE_ARR_LEN 800 +#define STR_LEN 128 +struct trace { + struct timeval tv; + char str[STR_LEN]; + unsigned int callback_val1; + unsigned int callback_val2; + char valid; +}; +static unsigned int (*trc_callback1) (unsigned char) = NULL; +static unsigned int (*trc_callback2) (unsigned char) = NULL; +static unsigned char trc_param1 = 0; +static unsigned char trc_param2 = 0; +struct trace *trc_arr; +static int trc_index; +static int trc_active = 0; + +void TRC_START() +{ + trc_active = 1; +} + +void TRC_STOP() +{ + trc_active = 0; +} + +void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) +{ + printk("Marvell debug tracing is on\n"); + trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); + if(trc_arr == NULL) + { + printk("Can't allocate Debug Trace buffer\n"); + return; + } + memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); + trc_index = 0; + trc_callback1 = callback1; + trc_callback2 = callback2; + trc_param1 = callback1_param; + trc_param2 = callback2_param; +} +void TRC_REC(char *fmt,...) +{ + va_list args; + struct trace *trc = &trc_arr[trc_index]; + + if(trc_active == 0) + return; + + do_gettimeofday(&trc->tv); + if(trc_callback1) + trc->callback_val1 = trc_callback1(trc_param1); + if(trc_callback2) + trc->callback_val2 = trc_callback2(trc_param2); + va_start(args, fmt); + vsprintf(trc->str,fmt,args); + va_end(args); + trc->valid = 1; + if((++trc_index) == TRACE_ARR_LEN) { + trc_index = 0; + } +} +void TRC_OUTPUT(void) +{ + int i,j; + struct trace *p; + printk("\n\nTrace %d items\n",TRACE_ARR_LEN); + for(i=0,j=trc_index; ivalid) { + unsigned long uoffs; + struct trace *plast; + if(p == &trc_arr[0]) + plast = &trc_arr[TRACE_ARR_LEN-1]; + else + plast = p-1; + if(p->tv.tv_sec == ((plast)->tv.tv_sec)) + uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); + else + uoffs = (1000000 - ((plast)->tv.tv_usec)) + + ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + + p->tv.tv_usec; + printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); + if(trc_callback1) + printk("[%u]",p->callback_val1); + if(trc_callback2) + printk("[%u]",p->callback_val2); + printk(": %s",p->str); + } + p->valid = 0; + } + memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); + trc_index = 0; +} +void TRC_RELEASE(void) +{ + kfree(trc_arr); + trc_index = 0; +} + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h new file mode 100644 index 0000000..a5aac26 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/dbg-trace.h @@ -0,0 +1,24 @@ + +#ifndef _MV_DBG_TRCE_H_ +#define _MV_DBG_TRCE_H_ + +#ifdef CONFIG_MV_DBG_TRACE +void TRC_INIT(void *callback1, void *callback2, + unsigned char callback1_param, unsigned char callback2_param); +void TRC_REC(char *fmt,...); +void TRC_OUTPUT(void); +void TRC_RELEASE(void); +void TRC_START(void); +void TRC_STOP(void); + +#else +#define TRC_INIT(x1,x2,x3,x4) +#define TRC_REC(X...) +#define TRC_OUTPUT() +#define TRC_RELEASE() +#define TRC_START() +#define TRC_STOP() +#endif + + +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c new file mode 100644 index 0000000..5f62784 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c @@ -0,0 +1,2513 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "cpu/mvCpu.h" +#include "cntmr/mvCntmr.h" +#include "gpp/mvGpp.h" +#include "twsi/mvTwsi.h" +#include "pex/mvPex.h" +#include "device/mvDevice.h" +#include "eth/gbe/mvEthRegs.h" + +/* defines */ +/* #define MV_DEBUG */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; + +#define CODE_IN_ROM MV_FALSE +#define CODE_IN_RAM MV_TRUE + +extern MV_BOARD_INFO* boardInfoTbl[]; +#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] + +/* Locals */ +static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +MV_U32 tClkRate = -1; + + +/******************************************************************************* +* mvBoardEnvInit - Init board +* +* DESCRIPTION: +* In this function the board environment take care of device bank +* initialization. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardEnvInit(MV_VOID) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); + return; + + } + + /* Set GPP Out value */ + MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); + MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); + + /* set GPP polarity */ + mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); + mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); + + /* Workaround for Erratum FE-MISC-70*/ + if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) + { + BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; + BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; + } /*End of WA*/ + + /* Set GPP Out Enable*/ + mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); + mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); + + /* Nand CE */ + MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); +} + +/******************************************************************************* +* mvBoardModelGet - Get Board model +* +* DESCRIPTION: +* This function returns 16bit describing board model. +* Board model is constructed of one byte major and minor numbers in the +* following manner: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardModelGet(MV_VOID) +{ + return (mvBoardIdGet() >> 16); +} + +/******************************************************************************* +* mbBoardRevlGet - Get Board revision +* +* DESCRIPTION: +* This function returns a 32bit describing the board revision. +* Board revision is constructed of 4bytes. 2bytes describes major number +* and the other 2bytes describes minor munber. +* For example for board revision 3.4 the function will return +* 0x00030004. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* String describing board model. +* +*******************************************************************************/ +MV_U16 mvBoardRevGet(MV_VOID) +{ + return (mvBoardIdGet() & 0xFFFF); +} + +/******************************************************************************* +* mvBoardNameGet - Get Board name +* +* DESCRIPTION: +* This function returns a string describing the board model and revision. +* String is extracted from board I2C EEPROM. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvBoardNameGet(char *pNameBuff) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsSPrintf (pNameBuff, "Board unknown.\n"); + return MV_ERROR; + + } + + mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); + + return MV_OK; +} + +/******************************************************************************* +* mvBoardIsPortInSgmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE +* For all other options. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in SGMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) +{ + MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; + + if(ethPortNum >= BOARD_ETH_PORT_NUM) + { + mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); + return MV_FALSE; + } + return ethPortSgmiiSupport[ethPortNum]; +} + +/******************************************************************************* +* mvBoardIsPortInGmii - +* +* DESCRIPTION: +* This routine returns MV_TRUE for port number works in GMII or MV_FALSE +* For all other options. +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - port in GMII. +* MV_FALSE - other. +* +*******************************************************************************/ +MV_BOOL mvBoardIsPortInGmii(MV_VOID) +{ + MV_U32 devClassId, devClass = 0; + if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) + { + /* Get MPP module ID */ + devClassId = mvBoarModuleTypeGet(devClass); + if (MV_BOARD_MODULE_GMII_ID == devClassId) + return MV_TRUE; + } + else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) + return MV_TRUE; + + return MV_FALSE; +} +/******************************************************************************* +* mvBoardPhyAddrGet - Get the phy address +* +* DESCRIPTION: +* This routine returns the Phy address of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing Phy address, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; +} + +/******************************************************************************* +* mvBoardMacSpeedGet - Get the Mac speed +* +* DESCRIPTION: +* This routine returns the Mac speed if pre define of a given ethernet port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. +* +*******************************************************************************/ +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) +{ + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; +} + +/******************************************************************************* +* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication +* +* DESCRIPTION: +* This routine returns the IRQ number for the link status indication. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* the number of the IRQ for the link status indication, -1 if the port +* number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; +} + +/******************************************************************************* +* mvBoardSwitchPortGet - Get the mapping between the board connector and the +* Ethernet Switch port +* +* DESCRIPTION: +* This routine returns the matching Switch port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* boardPortNum - logical number of the connector on the board +* +* OUTPUT: +* None. +* +* RETURN: +* the matching Switch port, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); + return MV_ERROR; + } + if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) + { + mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; +} + +/******************************************************************************* +* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port +* +* DESCRIPTION: +* This routine returns the Switch CPU port. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* the Switch CPU port, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; +} + +/******************************************************************************* +* mvBoardIsSwitchConnected - Get switch connection status +* DESCRIPTION: +* This routine returns port's connection status +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 1 - if ethPortNum is connected to switch, 0 otherwise +* +*******************************************************************************/ +MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); + return MV_ERROR; + } + + if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) + { + mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); + return MV_ERROR; + } + + if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) + return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); + else + return 0; +} +/******************************************************************************* +* mvBoardSmiScanModeGet - Get Switch SMI scan mode +* +* DESCRIPTION: +* This routine returns Switch SMI scan mode. +* +* INPUT: +* ethPortNum - Ethernet port number. +* +* OUTPUT: +* None. +* +* RETURN: +* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. +* +*******************************************************************************/ +MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) +{ + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); + return MV_ERROR; + } + + return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; +} +/******************************************************************************* +* mvBoardSpecInitGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, +* otherwise return MV_FALSE. +* +* +*******************************************************************************/ + +MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) +{ + return MV_FALSE; +} + +/******************************************************************************* +* mvBoardTclkGet - Get the board Tclk (Controller clock) +* +* DESCRIPTION: +* This routine extract the controller core clock. +* This function uses the controller counters to make identification. +* Note: In order to avoid interference, make sure task context switch +* and interrupts will not occure during this function operation +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +MV_U32 mvBoardTclkGet(MV_VOID) +{ + if(mvCtrlModelGet()==MV_6281_DEV_ID) + { +#if defined(TCLK_AUTO_DETECT) + MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; + + tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + tmpTClkRate &= MSAR_TCLCK_MASK; + + switch (tmpTClkRate) + { + case MSAR_TCLCK_166: + return MV_BOARD_TCLK_166MHZ; + break; + case MSAR_TCLCK_200: + return MV_BOARD_TCLK_200MHZ; + break; + } +#else + return MV_BOARD_TCLK_200MHZ; +#endif + } + + return MV_BOARD_TCLK_166MHZ; + +} +/******************************************************************************* +* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU bus clock. +* +* INPUT: +* countNum - Counter number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +static MV_U32 mvBoard6180SysClkGet(MV_VOID) +{ + MV_U32 sysClkRate=0; + MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; + + sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; + sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; + + sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; + + return sysClkRate; + +} + +MV_U32 mvBoardSysClkGet(MV_VOID) +{ +#ifdef SYSCLK_AUTO_DETECT + MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; + MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; + MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; + + if(mvCtrlModelGet() == MV_6180_DEV_ID) + return mvBoard6180SysClkGet(); + + tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); + pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); + pClkRate = cpuCLK[pClkRate]; + + indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; + indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; + if(ddrRtio[indexDdrRtio][0] != 0) + sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); + else + sysClkRate = 0; + return sysClkRate; +#else + return MV_BOARD_DEFAULT_SYSCLK; +#endif +} + + +/******************************************************************************* +* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number +* +* DESCRIPTION: +* Multi-ported PCI Express bridges that is implemented on the board +* collapse interrupts across multiple conventional PCI/PCI-X buses. +* A dual-headed PCI Express bridge would map (or "swizzle") the +* interrupts per the following table (in accordance with the respective +* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# +* signals from its two logical PCI/PCI-X bridges, collapse the +* INTA#-INTD# signals from any internal sources, and convert the +* signals to in-band PCI Express messages. 10 +* This function returns the upstream interrupt as it was converted by +* the bridge, according to board configuration and the following table: +* PCI dev num +* Interrupt pin 7, 8, 9 +* A -> A D C +* B -> B A D +* C -> C B A +* D -> D C B +* +* +* INPUT: +* devNum - PCI/PCIX device number. +* intPin - PCI Int pin +* +* OUTPUT: +* None. +* +* RETURN: +* Int pin connected to the Interrupt controller +* +*******************************************************************************/ +MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) +{ + MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); + + if (realIntPin == 0) return 4; + else return realIntPin; + +} + +/******************************************************************************* +* mvBoardDebugLedNumGet - Get number of debug Leds +* +* DESCRIPTION: +* INPUT: +* boardId +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) +{ + return BOARD_INFO(boardId)->activeLedsNumber; +} + +/******************************************************************************* +* mvBoardDebugLeg - Set the board debug Leds +* +* DESCRIPTION: turn on/off status leds. +* Note: assume MPP leds are part of group 0 only. +* +* INPUT: +* hexNum - Number to be displied in hex by Leds. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvBoardDebugLed(MV_U32 hexNum) +{ + MV_U32 val = 0,totalMask, currentBitMask = 1,i; + MV_U32 boardId= mvBoardIdGet(); + + if (BOARD_INFO(boardId)->pLedGppPin == NULL) + return; + + totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; + hexNum &= totalMask; + totalMask = 0; + + for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) + { + if (hexNum & currentBitMask) + { + val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); + } + + totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); + + currentBitMask = (currentBitMask << 1); + } + + if (BOARD_INFO(boardId)->ledsPolarity) + { + mvGppValueSet(0, totalMask, val); + } + else + { + mvGppValueSet(0, totalMask, ~val); + } +} + + +/******************************************************************************* +* mvBoarGpioPinGet - mvBoarGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* class - MV_BOARD_GPP_CLASS enum. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) +{ + MV_U32 boardId, i; + MV_U32 indexFound = 0; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); + return MV_ERROR; + + } + + for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) + if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { + if (indexFound == index) + return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; + else + indexFound++; + + } + + return MV_ERROR; +} + + +/******************************************************************************* +* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardRTCGpioPinGet(MV_VOID) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); +} + + +/******************************************************************************* +* mvBoardReset - mvBoardReset +* +* DESCRIPTION: +* Reset the board +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +MV_VOID mvBoardReset(MV_VOID) +{ + MV_32 resetPin; + + /* Get gpp reset pin if define */ + resetPin = mvBoardResetGpioPinGet(); + if (resetPin != MV_ERROR) + { + MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); + MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); + + } + else + { + /* No gpp reset pin was found, try to reset ussing + system reset out */ + MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); + MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); + } +} + +/******************************************************************************* +* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardResetGpioPinGet(MV_VOID) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); +} +/******************************************************************************* +* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet +* +* DESCRIPTION: +* used for hotswap detection +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardSDIOGpioPinGet(MV_VOID) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); +} + +/******************************************************************************* +* mvBoardUSBVbusGpioPinGet - return Vbus input GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); +} + +/******************************************************************************* +* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP +* +* DESCRIPTION: +* +* INPUT: +* int devNo. +* +* OUTPUT: +* None. +* +* RETURN: +* GPIO pin number. The function return -1 for bad parameters. +* +*******************************************************************************/ +MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) +{ + return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); +} + + +/******************************************************************************* +* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins +* +* DESCRIPTION: +* This function returns a 32-bit mask of GPP pins that connected to +* interrupt generating sources on board. +* For example if UART channel A is hardwired to GPP pin 8 and +* UART channel B is hardwired to GPP pin 4 the fuinction will return +* the value 0x000000110 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* See description. The function return -1 if board is not identified. +* +*******************************************************************************/ +MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->intsGppMaskLow; +} +MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->intsGppMaskHigh; +} + + +/******************************************************************************* +* mvBoardMppGet - Get board dependent MPP register value +* +* DESCRIPTION: +* MPP settings are derived from board design. +* MPP group consist of 8 MPPs. An MPP group represent MPP +* control register. +* This function retrieves board dependend MPP register value. +* +* INPUT: +* mppGroupNum - MPP group number. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit value describing MPP control register value. +* +*******************************************************************************/ +MV_32 mvBoardMppGet(MV_U32 mppGroupNum) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + + } + + return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; +} + + +/******************************************************************************* +* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MODULE_ID_CLASS devClassId; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U32 maxMppGrp = 1; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + /* If MPP group can be defined by the module connected to it */ + if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) + { + /* Get MPP module ID */ + devClassId = mvBoarModuleTypeGet(devClass); + if (MV_ERROR != devClassId) + { + switch(devClassId) + { + case MV_BOARD_MODULE_TDM_ID: + case MV_BOARD_MODULE_TDM_5CHAN_ID: + mppGroupType = MV_BOARD_TDM; + break; + case MV_BOARD_MODULE_AUDIO_ID: + mppGroupType = MV_BOARD_AUDIO; + break; + case MV_BOARD_MODULE_RGMII_ID: + mppGroupType = MV_BOARD_RGMII; + break; + case MV_BOARD_MODULE_GMII_ID: + mppGroupType = MV_BOARD_GMII; + break; + case MV_BOARD_MODULE_TS_ID: + mppGroupType = MV_BOARD_TS; + break; + case MV_BOARD_MODULE_MII_ID: + mppGroupType = MV_BOARD_MII; + break; + default: + mppGroupType = MV_BOARD_OTHER; + break; + } + } + else + /* The module bay is empty */ + mppGroupType = MV_BOARD_OTHER; + + /* Update MPP group type */ + mvBoardMppGroupTypeSet(devClass, mppGroupType); + } + + /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ + if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) + MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); + else + { + if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) + { + MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); + MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); + MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); + } + else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) + { + /* Assumption that the MDC & MDIO should be 3.3V */ + MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); + /* Assumption that only ETH1 can be MII when using modules on DB */ + MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); + } + } + } +} + +/******************************************************************************* +* mvBoardMppGroupTypeGet +* +* DESCRIPTION: +* +* INPUT: +* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + return MV_ERROR; + + } + + if (mppGroupClass == MV_BOARD_MPP_GROUP_1) + return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; + else + return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; +} + +/******************************************************************************* +* mvBoardMppGroupTypeSet +* +* DESCRIPTION: +* +* INPUT: +* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. +* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, + MV_BOARD_MPP_TYPE_CLASS mppGroupType) +{ + MV_U32 boardId; + + boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardMppGet:Board unknown.\n"); + } + + if (mppGroupClass == MV_BOARD_MPP_GROUP_1) + BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; + else + BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; + +} + +/******************************************************************************* +* mvBoardMppMuxSet - Update MPP mux +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardMppMuxSet(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U8 muxVal = 0xf; + MV_U32 maxMppGrp = 1; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + + switch(mppGroupType) + { + case MV_BOARD_TDM: + muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); + break; + case MV_BOARD_AUDIO: + muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ + break; + case MV_BOARD_TS: + muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); + break; + default: + muxVal |= (devClass ? 0xf : 0); + break; + } + } + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); + twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 2; + twsiSlave.moreThen256 = MV_FALSE; + + + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + DB(mvOsPrintf("Board: twsi exp out val fail\n")); + return; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 6; + muxVal = 0; + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + DB(mvOsPrintf("Board: twsi exp change to out fail\n")); + return; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + +} + +/******************************************************************************* +* mvBoardTdmMppSet - set MPPs in TDM module +* +* DESCRIPTION: +* +* INPUT: type of second telephony device +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardTdmMppSet(MV_32 chType) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U8 muxVal = 1; + MV_U8 muxValMask = 1; + MV_U8 twsiVal; + MV_U32 maxMppGrp = 1; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + if(mppGroupType == MV_BOARD_TDM) + break; + } + + if(devClass == maxMppGrp) + return; /* TDM module not found */ + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 3; + twsiSlave.moreThen256 = MV_FALSE; + + if(mvBoardIdGet() == RD_88F6281A_ID) + { + muxVal = 0xc; + muxValMask = 0xf3; + } + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & muxValMask) | muxVal; + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board: twsi exp out val fail\n"); + return; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 7; + muxVal = 0xfe; + if(mvBoardIdGet() == RD_88F6281A_ID) + muxVal = 0xf3; + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & muxVal); + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board: twsi exp change to out fail\n"); + return; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + /* reset the line to 0 */ + twsiSlave.offset = 3; + muxVal = 0; + muxValMask = 1; + + if(mvBoardIdGet() == RD_88F6281A_ID) { + muxVal = 0x0; + muxValMask = 0xf3; + } + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & muxValMask) | muxVal; + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board: twsi exp out val fail\n"); + return; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + mvOsDelay(20); + + /* set the line to 1 */ + twsiSlave.offset = 3; + muxVal = 1; + muxValMask = 1; + + if(mvBoardIdGet() == RD_88F6281A_ID) + { + muxVal = 0xc; + muxValMask = 0xf3; + if(chType) /* FXS - issue reset properly */ + { + MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); + mvOsDelay(50); + MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); + } + else /* FXO - issue reset via TDM_CODEC_RST*/ + { + /* change MPP44 type to TDM_CODEC_RST(0x2) */ + MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); + } + } + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & muxValMask) | muxVal; + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board: twsi exp out val fail\n"); + return; + } + + /* TBD - 5 channels */ +#if defined(MV_TDM_5CHANNELS) + /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ + MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); + mvGppPolaritySet(1, MV_GPP6, 0); + + twsiSlave.offset = 6; + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & ~BIT2); + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board: twsi exp change to out fail\n"); + return; + } + + + twsiSlave.offset = 2; + + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + muxVal = (twsiVal & ~BIT2); + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) + { + mvOsPrintf("Board: twsi exp change to out fail\n"); + return; + } +#endif + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + +} +/******************************************************************************* +* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ + +MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) +{ + switch(mvBoardIdGet()) + { + case RD_88F6281A_ID: + *connMode = DAISY_CHAIN_MODE; + *irqMode = INTERRUPT_TO_TDM; + break; + case DB_88F6281A_BP_ID: + *connMode = DUAL_CHIP_SELECT_MODE; + *irqMode = INTERRUPT_TO_TDM; + break; + case RD_88F6192A_ID: + *connMode = DUAL_CHIP_SELECT_MODE; + *irqMode = INTERRUPT_TO_TDM; + break; + case DB_88F6192A_BP_ID: + *connMode = DUAL_CHIP_SELECT_MODE; + *irqMode = INTERRUPT_TO_TDM; + break; + default: + *connMode = *irqMode = -1; + mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); + } + return; + +} + +/******************************************************************************* +* mvBoardMppModuleTypePrint - print module detect +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvBoardMppModuleTypePrint(MV_VOID) +{ + + MV_BOARD_MPP_GROUP_CLASS devClass; + MV_BOARD_MPP_TYPE_CLASS mppGroupType; + MV_U32 devId; + MV_U32 maxMppGrp = 1; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_MODULE; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_MODULE; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_MODULE; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_MODULE; + break; + } + + for (devClass = 0; devClass < maxMppGrp; devClass++) + { + mppGroupType = mvBoardMppGroupTypeGet(devClass); + + switch(mppGroupType) + { + case MV_BOARD_TDM: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is TDM\n", devClass); + break; + case MV_BOARD_AUDIO: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is AUDIO\n", devClass); + break; + case MV_BOARD_RGMII: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is RGMII\n", devClass); + break; + case MV_BOARD_GMII: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is GMII\n", devClass); + break; + case MV_BOARD_TS: + if(devId != MV_6190_DEV_ID) + mvOsPrintf("Module %d is TS\n", devClass); + break; + default: + break; + } + } +} + +/* Board devices API managments */ + +/******************************************************************************* +* mvBoardGetDeviceNumber - Get number of device of some type on the board +* +* DESCRIPTION: +* +* INPUT: +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* number of those devices else the function returns 0 +* +* +*******************************************************************************/ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex=0,devNum; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); + return 0xFFFFFFFF; + + } + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) + { + if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) + { + foundIndex++; + } + } + + return foundIndex; + +} + +/******************************************************************************* +* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Base address else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); + + } + + return 0xFFFFFFFF; +} + +/******************************************************************************* +* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* Bus width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return 8; + } + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvBoardGetDeviceWidth - Get dev width of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev width else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + return devEntry->devWidth; + + return MV_ERROR; + +} + +/******************************************************************************* +* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* window size else the function returns 0xffffffff +* +* +*******************************************************************************/ +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId = mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + } + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + { + return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); + } + + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* boardGetDevEntry - returns the entry pointer of a device on the board +* +* DESCRIPTION: +* +* INPUT: +* devIndex - The device sequential number on the board +* devType - The device type ( Flash,RTC , etc .. ) +* +* OUTPUT: +* None. +* +* RETURN: +* If the device is found on the board the then the functions returns the +* dev number else the function returns 0x0 +* +* +*******************************************************************************/ +static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_U32 foundIndex=0,devIndex; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("boardGetDevEntry: Board unknown.\n"); + return NULL; + + } + + for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) + { + /* TBR */ + /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) + continue;*/ + + if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) + { + if (foundIndex == devNum) + { + return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); + } + foundIndex++; + } + } + + /* device not found */ + return NULL; +} + +/* Get device CS number */ + +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) +{ + MV_DEV_CS_INFO* devEntry; + MV_U32 boardId= mvBoardIdGet(); + + if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) + { + mvOsPrintf("Board unknown.\n"); + return 0xFFFFFFFF; + + } + + + devEntry = boardGetDevEntry(devNum,devClass); + if (devEntry != NULL) + return devEntry->deviceCS; + + return 0xFFFFFFFF; + +} + +/******************************************************************************* +* mvBoardRtcTwsiAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardRtcTwsiAddrTypeGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardRtcTwsiAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardRtcTwsiAddrGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + return (0xFF); +} + +/******************************************************************************* +* mvBoardA2DTwsiAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardA2DTwsiAddrTypeGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardA2DTwsiAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardA2DTwsiAddrGet() +{ + int i; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + return (0xFF); +} + +/******************************************************************************* +* mvBoardTwsiExpAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) + { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + else + indexFound++; + } + + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardTwsiExpAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) + { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + else + indexFound++; + } + + return (0xFF); +} + + +/******************************************************************************* +* mvBoardTwsiSatRAddrTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) + { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; + else + indexFound++; + } + + return (MV_ERROR); +} + +/******************************************************************************* +* mvBoardTwsiSatRAddrGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) +{ + int i; + MV_U32 indexFound = 0; + MV_U32 boardId= mvBoardIdGet(); + + for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) + if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) + { + if (indexFound == index) + return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; + else + indexFound++; + } + + return (0xFF); +} + +/******************************************************************************* +* mvBoardNandWidthGet - +* +* DESCRIPTION: Get the width of the first NAND device in byte. +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: 1, 2, 4 or MV_ERROR +* +* +*******************************************************************************/ +/* */ +MV_32 mvBoardNandWidthGet(void) +{ + MV_U32 devNum; + MV_U32 devWidth; + MV_U32 boardId= mvBoardIdGet(); + + for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) + { + devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); + if (devWidth != MV_ERROR) + return (devWidth / 8); + } + + /* NAND wasn't found */ + return MV_ERROR; +} + +MV_U32 gBoardId = -1; + +/******************************************************************************* +* mvBoardIdGet - Get Board model +* +* DESCRIPTION: +* This function returns board ID. +* Board ID is 32bit word constructed of board model (16bit) and +* board revision (16bit) in the following way: 0xMMMMRRRR. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit board ID number, '-1' if board is undefined. +* +*******************************************************************************/ +MV_U32 mvBoardIdGet(MV_VOID) +{ + MV_U32 tmpBoardId = -1; + + if(gBoardId == -1) + { + #if defined(DB_88F6281A) + tmpBoardId = DB_88F6281A_BP_ID; + #elif defined(RD_88F6281A) + tmpBoardId = RD_88F6281A_ID; + #elif defined(DB_88F6192A) + tmpBoardId = DB_88F6192A_BP_ID; + #elif defined(DB_88F6190A) + tmpBoardId = DB_88F6190A_BP_ID; + #elif defined(RD_88F6192A) + tmpBoardId = RD_88F6192A_ID; + #elif defined(RD_88F6190A) + tmpBoardId = RD_88F6190A_ID; + #elif defined(DB_88F6180A) + tmpBoardId = DB_88F6180A_BP_ID; + #elif defined(RD_88F6281A_PCAC) + tmpBoardId = RD_88F6281A_PCAC_ID; + #elif defined(RD_88F6281A_SHEEVA_PLUG) + tmpBoardId = SHEEVA_PLUG_ID; + #elif defined(DB_CUSTOMER) + tmpBoardId = DB_CUSTOMER_ID; + #endif + gBoardId = tmpBoardId; + } + + return gBoardId; +} + + +/******************************************************************************* +* mvBoarModuleTypeGet - mvBoarModuleTypeGet +* +* DESCRIPTION: +* +* INPUT: +* group num - MV_BOARD_MPP_GROUP_CLASS enum +* +* OUTPUT: +* None. +* +* RETURN: +* module num - MV_BOARD_MODULE_CLASS enum +* +*******************************************************************************/ +MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U8 data; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: Read MPP module ID\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); + twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + + + if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) + { + DB(mvOsPrintf("Board: Read MPP module ID fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); + + return data; +} + +/******************************************************************************* +* mvBoarTwsiSatRGet - +* +* DESCRIPTION: +* +* INPUT: +* device num - one of three devices +* reg num - 0 or 1 +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + MV_U8 data; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: Read S@R device read\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); + twsiSlave.validOffset = MV_TRUE; + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) + { + DB(mvOsPrintf("Board: Read S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Read S@R succeded\n")); + + return data; +} + +/******************************************************************************* +* mvBoarTwsiSatRSet - +* +* DESCRIPTION: +* +* INPUT: +* devNum - one of three devices +* regNum - 0 or 1 +* regVal - value +* +* +* OUTPUT: +* None. +* +* RETURN: +* reg value +* +*******************************************************************************/ +MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) +{ + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); + twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); + twsiSlave.validOffset = MV_TRUE; + DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ + twsiSlave.slaveAddr.type, regVal)); + /* Use offset as command */ + twsiSlave.offset = regNum; + twsiSlave.moreThen256 = MV_FALSE; + if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) + { + DB(mvOsPrintf("Board: Write S@R fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: Write S@R succeded\n")); + + return MV_OK; +} + +/******************************************************************************* +* mvBoardSlicGpioPinGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +* +*******************************************************************************/ +MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) +{ + MV_U32 boardId; + boardId = mvBoardIdGet(); + + switch (boardId) + { + case DB_88F6281A_BP_ID: + case RD_88F6281A_ID: + default: + return MV_ERROR; + break; + + } +} + +/******************************************************************************* +* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A +* +* DESCRIPTION: +* +* INPUT: +* mode - MV_TRUE = on ; MV_FALSE = off +* +* OUTPUT: +* MV_STATUS - MV_OK , MV_ERROR. +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) +{ + + MV_U8 val = 1, twsiVal; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if(mvBoardIdGet() != RD_88F6281A_ID) + return MV_ERROR; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 3; + twsiSlave.moreThen256 = MV_FALSE; + if(mode == MV_TRUE) + val = 0x1; + else + val = 0; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xfe) | val; + + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp out val fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 7; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xfe); + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp change to out fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + return MV_OK; +} + +/******************************************************************************* +* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A +* +* DESCRIPTION: +* +* INPUT: +* mode - MV_TRUE = on ; MV_FALSE = off +* +* OUTPUT: +* MV_STATUS - MV_OK , MV_ERROR. +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) +{ + + MV_U8 val = 1, twsiVal; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if(mvBoardIdGet() != RD_88F6281A_ID) + return MV_ERROR; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 3; + twsiSlave.moreThen256 = MV_FALSE; + if(mode == MV_TRUE) + val = 0x2; + else + val = 0; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xfd) | val; + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp out val fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 7; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xfd); + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp change to out fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + return MV_OK; +} + +/******************************************************************************* +* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A +* +* DESCRIPTION: +* +* INPUT: +* mode - MV_TRUE = on ; MV_FALSE = off +* +* OUTPUT: +* MV_STATUS - MV_OK , MV_ERROR. +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) +{ + + MV_U8 val = 1, twsiVal; + MV_TWSI_SLAVE twsiSlave; + MV_TWSI_ADDR slave; + + if(mvBoardIdGet() != RD_88F6281A_ID) + return MV_ERROR; + + /* TWSI init */ + slave.type = ADDR7_BIT; + slave.address = 0; + mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); + + /* Read MPP module ID */ + DB(mvOsPrintf("Board: twsi exp set\n")); + twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + /* Offset is the first command after the address which indicate the register number to be read + in next operation */ + twsiSlave.offset = 3; + twsiSlave.moreThen256 = MV_FALSE; + if(mode == MV_TRUE) + val = 0x10; + else + val = 0; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xef) | val; + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp out val fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp out val succeded\n")); + + /* Change twsi exp to output */ + twsiSlave.offset = 7; + mvTwsiRead(0, &twsiSlave, &twsiVal, 1); + val = (twsiVal & 0xef); + if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) + { + DB(mvOsPrintf("Board: twsi exp change to out fail\n")); + return MV_ERROR; + } + DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); + return MV_OK; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h new file mode 100644 index 0000000..dead633 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h @@ -0,0 +1,376 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvBoardEnvLibh +#define __INCmvBoardEnvLibh + +/* defines */ +/* The below constant macros defines the board I2C EEPROM data offsets */ + + + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "boardEnv/mvBoardEnvSpec.h" + + +/* DUART stuff for Tclk detection only */ +#define DUART_BAUD_RATE 115200 +#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ + +/* Voice devices assembly modes */ +#define DAISY_CHAIN_MODE 1 +#define DUAL_CHIP_SELECT_MODE 0 +#define INTERRUPT_TO_MPP 1 +#define INTERRUPT_TO_TDM 0 + + +#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS +#define BOARD_ETH_SWITCH_PORT_NUM 5 + +#define MV_BOARD_MAX_USB_IF 1 +#define MV_BOARD_MAX_MPP 7 +#define MV_BOARD_NAME_LEN 0x20 + +typedef struct _boardData +{ + MV_U32 magic; + MV_U16 boardId; + MV_U8 boardVer; + MV_U8 boardRev; + MV_U32 reserved1; + MV_U32 reserved2; + +}BOARD_DATA; + +typedef enum _devBoardMppGroupClass +{ + MV_BOARD_MPP_GROUP_1, + MV_BOARD_MPP_GROUP_2, + MV_BOARD_MAX_MPP_GROUP +}MV_BOARD_MPP_GROUP_CLASS; + +typedef enum _devBoardMppTypeClass +{ + MV_BOARD_AUTO, + MV_BOARD_TDM, + MV_BOARD_AUDIO, + MV_BOARD_RGMII, + MV_BOARD_GMII, + MV_BOARD_TS, + MV_BOARD_MII, + MV_BOARD_OTHER +}MV_BOARD_MPP_TYPE_CLASS; + +typedef enum _devBoardModuleIdClass +{ + MV_BOARD_MODULE_TDM_ID = 1, + MV_BOARD_MODULE_AUDIO_ID, + MV_BOARD_MODULE_RGMII_ID, + MV_BOARD_MODULE_GMII_ID, + MV_BOARD_MODULE_TS_ID, + MV_BOARD_MODULE_MII_ID, + MV_BOARD_MODULE_TDM_5CHAN_ID, + MV_BOARD_MODULE_OTHER_ID +}MV_BOARD_MODULE_ID_CLASS; + +typedef struct _boardMppTypeInfo +{ + MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; + +}MV_BOARD_MPP_TYPE_INFO; + + +typedef enum _devBoardClass +{ + BOARD_DEV_NOR_FLASH, + BOARD_DEV_NAND_FLASH, + BOARD_DEV_SEVEN_SEG, + BOARD_DEV_FPGA, + BOARD_DEV_SRAM, + BOARD_DEV_SPI_FLASH, + BOARD_DEV_OTHER, +}MV_BOARD_DEV_CLASS; + +typedef enum _devTwsiBoardClass +{ + BOARD_TWSI_RTC, + BOARD_DEV_TWSI_EXP, + BOARD_DEV_TWSI_SATR, + BOARD_TWSI_AUDIO_DEC, + BOARD_TWSI_OTHER +}MV_BOARD_TWSI_CLASS; + +typedef enum _devGppBoardClass +{ + BOARD_GPP_RTC, + BOARD_GPP_MV_SWITCH, + BOARD_GPP_USB_VBUS, + BOARD_GPP_USB_VBUS_EN, + BOARD_GPP_USB_OC, + BOARD_GPP_USB_HOST_DEVICE, + BOARD_GPP_REF_CLCK, + BOARD_GPP_VOIP_SLIC, + BOARD_GPP_LIFELINE, + BOARD_GPP_BUTTON, + BOARD_GPP_TS_BUTTON_C, + BOARD_GPP_TS_BUTTON_U, + BOARD_GPP_TS_BUTTON_D, + BOARD_GPP_TS_BUTTON_L, + BOARD_GPP_TS_BUTTON_R, + BOARD_GPP_POWER_BUTTON, + BOARD_GPP_RESTOR_BUTTON, + BOARD_GPP_WPS_BUTTON, + BOARD_GPP_HDD0_POWER, + BOARD_GPP_HDD1_POWER, + BOARD_GPP_FAN_POWER, + BOARD_GPP_RESET, + BOARD_GPP_POWER_ON_LED, + BOARD_GPP_HDD_POWER, + BOARD_GPP_SDIO_POWER, + BOARD_GPP_SDIO_DETECT, + BOARD_GPP_SDIO_WP, + BOARD_GPP_SWITCH_PHY_INT, + BOARD_GPP_TSU_DIRCTION, + BOARD_GPP_OTHER +}MV_BOARD_GPP_CLASS; + + +typedef struct _devCsInfo +{ + MV_U8 deviceCS; + MV_U32 params; + MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ + MV_U8 devWidth; + +}MV_DEV_CS_INFO; + + +#define MV_BOARD_PHY_FORCE_10MB 0x0 +#define MV_BOARD_PHY_FORCE_100MB 0x1 +#define MV_BOARD_PHY_FORCE_1000MB 0x2 +#define MV_BOARD_PHY_SPEED_AUTO 0x3 + +typedef struct _boardSwitchInfo +{ + MV_32 linkStatusIrq; + MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; + MV_32 qdCpuPort; + MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ + MV_32 switchOnPort; + +}MV_BOARD_SWITCH_INFO; + +typedef struct _boardLedInfo +{ + MV_U8 activeLedsNumber; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + MV_U8* gppPinNum; /* Pointer to GPP values */ + +}MV_BOARD_LED_INFO; + +typedef struct _boardGppInfo +{ + MV_BOARD_GPP_CLASS devClass; + MV_U8 gppPinNum; + +}MV_BOARD_GPP_INFO; + + +typedef struct _boardTwsiInfo +{ + MV_BOARD_TWSI_CLASS devClass; + MV_U8 twsiDevAddr; + MV_U8 twsiDevAddrType; + +}MV_BOARD_TWSI_INFO; + + +typedef enum _boardMacSpeed +{ + BOARD_MAC_SPEED_10M, + BOARD_MAC_SPEED_100M, + BOARD_MAC_SPEED_1000M, + BOARD_MAC_SPEED_AUTO, + +}MV_BOARD_MAC_SPEED; + +typedef struct _boardMacInfo +{ + MV_BOARD_MAC_SPEED boardMacSpeed; + MV_U8 boardEthSmiAddr; + +}MV_BOARD_MAC_INFO; + +typedef struct _boardMppInfo +{ + MV_U32 mppGroup[MV_BOARD_MAX_MPP]; + +}MV_BOARD_MPP_INFO; + +typedef struct _boardInfo +{ + char boardName[MV_BOARD_NAME_LEN]; + MV_U8 numBoardMppTypeValue; + MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; + MV_U8 numBoardMppConfigValue; + MV_BOARD_MPP_INFO* pBoardMppConfigValue; + MV_U32 intsGppMaskLow; + MV_U32 intsGppMaskHigh; + MV_U8 numBoardDeviceIf; + MV_DEV_CS_INFO* pDevCsInfo; + MV_U8 numBoardTwsiDev; + MV_BOARD_TWSI_INFO* pBoardTwsiDev; + MV_U8 numBoardMacInfo; + MV_BOARD_MAC_INFO* pBoardMacInfo; + MV_U8 numBoardGppInfo; + MV_BOARD_GPP_INFO* pBoardGppInfo; + MV_U8 activeLedsNumber; + MV_U8* pLedGppPin; + MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ + /* GPP values */ + MV_U32 gppOutEnValLow; + MV_U32 gppOutEnValHigh; + MV_U32 gppOutValLow; + MV_U32 gppOutValHigh; + MV_U32 gppPolarityValLow; + MV_U32 gppPolarityValHigh; + + /* Switch Configuration */ + MV_BOARD_SWITCH_INFO* pSwitchInfo; +}MV_BOARD_INFO; + + + +MV_VOID mvBoardEnvInit(MV_VOID); +MV_U32 mvBoardIdGet(MV_VOID); +MV_U16 mvBoardModelGet(MV_VOID); +MV_U16 mvBoardRevGet(MV_VOID); +MV_STATUS mvBoardNameGet(char *pNameBuff); +MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); +MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); +MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); +MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); +MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); +MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); +MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); +MV_BOOL mvBoardIsPortInGmii(MV_VOID); +MV_U32 mvBoardTclkGet(MV_VOID); +MV_U32 mvBoardSysClkGet(MV_VOID); +MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); +MV_VOID mvBoardDebugLed(MV_U32 hexNum); +MV_32 mvBoardMppGet(MV_U32 mppGroupNum); + +MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); +MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); + +MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); +MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); + +MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); +MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); +MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); +MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); +MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); +MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); +MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, + MV_BOARD_MPP_TYPE_CLASS mppGroupType); +MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); +MV_VOID mvBoardMppMuxSet(MV_VOID); +MV_VOID mvBoardTdmMppSet(MV_32 chType); +MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); + +MV_VOID mvBoardMppModuleTypePrint(MV_VOID); +MV_VOID mvBoardReset(MV_VOID); +MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); +MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); +MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); +/* Board devices API managments */ +MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); +MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); + +/* Gpio Pin Connections API */ +MV_32 mvBoardUSBVbusGpioPinGet(int devId); +MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); +MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); + +MV_32 mvBoardResetGpioPinGet(MV_VOID); +MV_32 mvBoardRTCGpioPinGet(MV_VOID); +MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); +MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); +MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); + +MV_32 mvBoardSDIOGpioPinGet(MV_VOID); +MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); +MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); + +MV_32 mvBoardNandWidthGet(void); +MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); +MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); +#endif /* __INCmvBoardEnvLibh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c new file mode 100644 index 0000000..e256c4f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c @@ -0,0 +1,848 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvCommon.h" +#include "mvBoardEnvLib.h" +#include "mvBoardEnvSpec.h" +#include "twsi/mvTwsi.h" + +#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 +#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 + + +MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9} + }; + +MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + {{MV_BOARD_AUTO, MV_BOARD_AUTO} + }; + +MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_TSU_DIRCTION, 33} + /*muxed with TDM/Audio module via IOexpender + {BOARD_GPP_SDIO_DETECT, 38}, + {BOARD_GPP_USB_VBUS, 49}*/ + }; + +MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = + {{{ + DB_88F6281A_MPP0_7, + DB_88F6281A_MPP8_15, + DB_88F6281A_MPP16_23, + DB_88F6281A_MPP24_31, + DB_88F6281A_MPP32_39, + DB_88F6281A_MPP40_47, + DB_88F6281A_MPP48_55 + }}}; + + +MV_BOARD_INFO db88f6281AInfo = { + "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6281AInfoBoardMppTypeInfo, + DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6281AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6281AInfoBoardDeCsInfo, + DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6281AInfoBoardTwsiDev, + DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6281AInfoBoardMacInfo, + DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6281AInfoBoardGppInfo, + DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6281A_OE_LOW, /* gppOutEnLow */ + DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + BIT6, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + + +#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 +#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 +#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 +#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 + +MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_1000M, 0xa}, + {BOARD_MAC_SPEED_AUTO, 0xb} + }; + +MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = + /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, + MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ + {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, + {-1, {-1}, -1, -1, -1}}; + +MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} + }; + +MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = + {{MV_BOARD_RGMII, MV_BOARD_TDM} + }; + +MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + {{BOARD_GPP_SDIO_DETECT, 28}, + {BOARD_GPP_USB_OC, 29}, + {BOARD_GPP_WPS_BUTTON, 35}, + {BOARD_GPP_MV_SWITCH, 38}, + {BOARD_GPP_USB_VBUS, 49} + }; + +MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = + {{{ + RD_88F6281A_MPP0_7, + RD_88F6281A_MPP8_15, + RD_88F6281A_MPP16_23, + RD_88F6281A_MPP24_31, + RD_88F6281A_MPP32_39, + RD_88F6281A_MPP40_47, + RD_88F6281A_MPP48_55 + }}}; + +MV_BOARD_INFO rd88f6281AInfo = { + "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + rd88f6281AInfoBoardMppTypeInfo, + RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6281AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6281AInfoBoardDeCsInfo, + RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6281AInfoBoardTwsiDev, + RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6281AInfoBoardMacInfo, + RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6281AInfoBoardGppInfo, + RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + RD_88F6281A_OE_LOW, /* gppOutEnLow */ + RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ + RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ + RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + BIT6, /* gppPolarityValHigh */ + rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ +}; + + +#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 +#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 +#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 +#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 + +MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, + {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + { + {BOARD_MAC_SPEED_AUTO, 0x8}, + {BOARD_MAC_SPEED_AUTO, 0x9} + }; + +MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + {{MV_BOARD_AUTO, MV_BOARD_OTHER} + }; + +MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_SDIO_WP, 20}, + {BOARD_GPP_USB_VBUS, 22}, + {BOARD_GPP_SDIO_DETECT, 23}, + }; + +MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = + {{{ + DB_88F6192A_MPP0_7, + DB_88F6192A_MPP8_15, + DB_88F6192A_MPP16_23, + DB_88F6192A_MPP24_31, + DB_88F6192A_MPP32_35 + }}}; + +MV_BOARD_INFO db88f6192AInfo = { + "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6192AInfoBoardMppTypeInfo, + DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6192AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6192AInfoBoardDeCsInfo, + DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6192AInfoBoardTwsiDev, + DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6192AInfoBoardMacInfo, + DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6192AInfoBoardGppInfo, + DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6192A_OE_LOW, /* gppOutEnLow */ + DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + +#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 + +MV_BOARD_INFO db88f6190AInfo = { + "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6192AInfoBoardMppTypeInfo, + DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6192AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6192AInfoBoardDeCsInfo, + DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6192AInfoBoardTwsiDev, + DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6192AInfoBoardMacInfo, + DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + db88f6192AInfoBoardGppInfo, + DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6192A_OE_LOW, /* gppOutEnLow */ + DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + +#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 +#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE +#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 +#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 +#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 + +MV_U8 rd88f6192AInfoBoardDebugLedIf[] = + {17, 28, 29}; + +MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + {{MV_BOARD_OTHER, MV_BOARD_OTHER} + }; + +MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ + +MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + {BOARD_GPP_USB_VBUS_EN, 10}, + {BOARD_GPP_USB_HOST_DEVICE, 11}, + {BOARD_GPP_RESET, 14}, + {BOARD_GPP_POWER_ON_LED, 15}, + {BOARD_GPP_HDD_POWER, 16}, + {BOARD_GPP_WPS_BUTTON, 24}, + {BOARD_GPP_TS_BUTTON_C, 25}, + {BOARD_GPP_USB_VBUS, 26}, + {BOARD_GPP_USB_OC, 27}, + {BOARD_GPP_TS_BUTTON_U, 30}, + {BOARD_GPP_TS_BUTTON_R, 31}, + {BOARD_GPP_TS_BUTTON_L, 32}, + {BOARD_GPP_TS_BUTTON_D, 34}, + {BOARD_GPP_FAN_POWER, 35} + }; + +MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = + {{{ + RD_88F6192A_MPP0_7, + RD_88F6192A_MPP8_15, + RD_88F6192A_MPP16_23, + RD_88F6192A_MPP24_31, + RD_88F6192A_MPP32_35 + }}}; + +MV_BOARD_INFO rd88f6192AInfo = { + "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + rd88f6192AInfoBoardMppTypeInfo, + RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6192AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6192AInfoBoardDeCsInfo, + RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, + RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6192AInfoBoardMacInfo, + RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6192AInfoBoardGppInfo, + RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f6192AInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F6192A_OE_LOW, /* gppOutEnLow */ + RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ + RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ + RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + +MV_BOARD_INFO rd88f6190AInfo = { + "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + rd88f6192AInfoBoardMppTypeInfo, + RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6192AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6192AInfoBoardDeCsInfo, + RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + NULL, + RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6192AInfoBoardMacInfo, + RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + rd88f6192AInfoBoardGppInfo, + RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + rd88f6192AInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_88F6192A_OE_LOW, /* gppOutEnLow */ + RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ + RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ + RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + +#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 +#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 +#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 +#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 +#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 +#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 +#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 +#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 + +MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, + {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, + {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, + {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} + }; + +MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = + /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ + { + /* Muxed with TDM/Audio module via IOexpender + {BOARD_GPP_USB_VBUS, 6} */ + }; + +MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = + /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, + MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ + {{MV_BOARD_OTHER, MV_BOARD_AUTO} + }; + +MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = + {{{ + DB_88F6180A_MPP0_7, + DB_88F6180A_MPP8_15, + DB_88F6180A_MPP16_23, + DB_88F6180A_MPP24_31, + DB_88F6180A_MPP32_39, + DB_88F6180A_MPP40_44 + }}}; + +MV_BOARD_INFO db88f6180AInfo = { + "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + db88f6180AInfoBoardMppTypeInfo, + DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + db88f6180AInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + db88f6180AInfoBoardDeCsInfo, + DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + db88f6180AInfoBoardTwsiDev, + DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + db88f6180AInfoBoardMacInfo, + DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + NULL, + DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_88F6180A_OE_LOW, /* gppOutEnLow */ + DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ + DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ + DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + + +#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 +#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 +#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 +#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 +#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 +#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 +#else + #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 +#endif +#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 + +MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = + {38, 39, 40, 41}; + +MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x8} + }; + +MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + { + {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} + }; + +MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = + {{MV_BOARD_OTHER, MV_BOARD_OTHER} + }; + +MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = + {{{ + RD_88F6281A_PCAC_MPP0_7, + RD_88F6281A_PCAC_MPP8_15, + RD_88F6281A_PCAC_MPP16_23, + RD_88F6281A_PCAC_MPP24_31, + RD_88F6281A_PCAC_MPP32_39, + RD_88F6281A_PCAC_MPP40_47, + RD_88F6281A_PCAC_MPP48_55 + }}}; + +MV_BOARD_INFO rd88f6281APcacInfo = { + "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ + RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ + rd88f6281APcacInfoBoardMppTypeInfo, + RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + rd88f6281APcacInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + (1 << 3), /* intsGppMaskHigh */ + RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + rd88f6281APcacInfoBoardDeCsInfo, + RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + rd88f6281APcacInfoBoardTwsiDev, + RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + rd88f6281APcacInfoBoardMacInfo, + RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + 0, + RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ + RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ + RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ + RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + + +/* 6281 Sheeva Plug*/ + +#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 +#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 +#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 +#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 +#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 +#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 +#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 +#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 + +MV_U8 sheevaPlugInfoBoardDebugLedIf[] = + {49}; + +MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x0}}; + +MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; + +MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = + {{MV_BOARD_OTHER, MV_BOARD_OTHER} + }; + +MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ + +MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = + {{{ + RD_SHEEVA_PLUG_MPP0_7, + RD_SHEEVA_PLUG_MPP8_15, + RD_SHEEVA_PLUG_MPP16_23, + RD_SHEEVA_PLUG_MPP24_31, + RD_SHEEVA_PLUG_MPP32_39, + RD_SHEEVA_PLUG_MPP40_47, + RD_SHEEVA_PLUG_MPP48_55 + }}}; + +MV_BOARD_INFO sheevaPlugInfo = { + "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ + SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ + sheevaPlugInfoBoardMppTypeInfo, + SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + sheevaPlugInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + sheevaPlugInfoBoardDeCsInfo, + SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + sheevaPlugInfoBoardTwsiDev, + SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + sheevaPlugInfoBoardMacInfo, + SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + 0, + SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + sheevaPlugInfoBoardDebugLedIf, + 0, /* ledsPolarity */ + RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ + RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ + RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ + RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + +/* Customer specific board place holder*/ + +#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 +#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 +#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 +#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 +#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 +#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 +#else + #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 +#endif +#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 + +MV_U8 dbCustomerInfoBoardDebugLedIf[] = + {0}; + +MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = + /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ + {{BOARD_MAC_SPEED_AUTO, 0x0}}; + +MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = + /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ + {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; + +MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = + {{MV_BOARD_OTHER, MV_BOARD_OTHER} + }; + +MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = + /*{deviceCS, params, devType, devWidth}*/ +#if defined(MV_NAND) && defined(MV_NAND_BOOT) + {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ +#elif defined(MV_NAND) && defined(MV_SPI_BOOT) + { + {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ + {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ + }; +#else + {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ +#endif + +MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = + {{{ + DB_CUSTOMER_MPP0_7, + DB_CUSTOMER_MPP8_15, + DB_CUSTOMER_MPP16_23, + DB_CUSTOMER_MPP24_31, + DB_CUSTOMER_MPP32_39, + DB_CUSTOMER_MPP40_47, + DB_CUSTOMER_MPP48_55 + }}}; + +MV_BOARD_INFO dbCustomerInfo = { + "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ + DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ + dbCustomerInfoBoardMppTypeInfo, + DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ + dbCustomerInfoBoardMppConfigValue, + 0, /* intsGppMaskLow */ + 0, /* intsGppMaskHigh */ + DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ + dbCustomerInfoBoardDeCsInfo, + DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ + dbCustomerInfoBoardTwsiDev, + DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ + dbCustomerInfoBoardMacInfo, + DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ + 0, + DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ + NULL, + 0, /* ledsPolarity */ + DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ + DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ + DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ + DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ + 0, /* gppPolarityValLow */ + 0, /* gppPolarityValHigh */ + NULL /* pSwitchInfo */ +}; + +MV_BOARD_INFO* boardInfoTbl[] = { + &db88f6281AInfo, + &rd88f6281AInfo, + &db88f6192AInfo, + &rd88f6192AInfo, + &db88f6180AInfo, + &db88f6190AInfo, + &rd88f6190AInfo, + &rd88f6281APcacInfo, + &dbCustomerInfo, + &sheevaPlugInfo + }; + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h new file mode 100644 index 0000000..0372eee --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h @@ -0,0 +1,262 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvBoardEnvSpech +#define __INCmvBoardEnvSpech + +#include "mvSysHwConfig.h" + + +/* For future use */ +#define BD_ID_DATA_START_OFFS 0x0 +#define BD_DETECT_SEQ_OFFS 0x0 +#define BD_SYS_NUM_OFFS 0x4 +#define BD_NAME_OFFS 0x8 + +/* I2C bus addresses */ +#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ +#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM0_I2C_ADDR 0x56 +#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_DIMM1_I2C_ADDR 0x54 +#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_EEPROM_I2C_ADDR 0x51 +#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 +#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT +#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 +#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 + +#define BOOT_FLASH_INDEX 0 +#define MAIN_FLASH_INDEX 1 + +#define BOARD_ETH_START_PORT_NUM 0 + +/* Supported clocks */ +#define MV_BOARD_TCLK_100MHZ 100000000 +#define MV_BOARD_TCLK_125MHZ 125000000 +#define MV_BOARD_TCLK_133MHZ 133333333 +#define MV_BOARD_TCLK_150MHZ 150000000 +#define MV_BOARD_TCLK_166MHZ 166666667 +#define MV_BOARD_TCLK_200MHZ 200000000 + +#define MV_BOARD_SYSCLK_100MHZ 100000000 +#define MV_BOARD_SYSCLK_125MHZ 125000000 +#define MV_BOARD_SYSCLK_133MHZ 133333333 +#define MV_BOARD_SYSCLK_150MHZ 150000000 +#define MV_BOARD_SYSCLK_166MHZ 166666667 +#define MV_BOARD_SYSCLK_200MHZ 200000000 +#define MV_BOARD_SYSCLK_233MHZ 233333333 +#define MV_BOARD_SYSCLK_250MHZ 250000000 +#define MV_BOARD_SYSCLK_267MHZ 266666667 +#define MV_BOARD_SYSCLK_300MHZ 300000000 +#define MV_BOARD_SYSCLK_333MHZ 333333334 +#define MV_BOARD_SYSCLK_400MHZ 400000000 + +#define MV_BOARD_REFCLK_25MHZ 25000000 + +/* Board specific */ +/* =============================== */ + +/* boards ID numbers */ + +#define BOARD_ID_BASE 0x0 + +/* New board ID numbers */ +#define DB_88F6281A_BP_ID (BOARD_ID_BASE) +#define DB_88F6281_BP_MLL_ID 1680 +#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) +#define RD_88F6281_MLL_ID 1682 +#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) +#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) +#define RD_88F6192_MLL_ID 1681 +#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) +#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) +#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) +#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) +#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) +#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) +#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) + +/* DB-88F6281A-BP */ +#if defined(MV_NAND) + #define DB_88F6281A_MPP0_7 0x21111111 +#else + #define DB_88F6281A_MPP0_7 0x21112220 +#endif +#define DB_88F6281A_MPP8_15 0x11113311 +#define DB_88F6281A_MPP16_23 0x00551111 +#define DB_88F6281A_MPP24_31 0x00000000 +#define DB_88F6281A_MPP32_39 0x00000000 +#define DB_88F6281A_MPP40_47 0x00000000 +#define DB_88F6281A_MPP48_55 0x00000000 +#define DB_88F6281A_OE_LOW 0x0 +#if defined(MV_TDM_5CHANNELS) + #define DB_88F6281A_OE_HIGH (BIT6) +#else +#define DB_88F6281A_OE_HIGH 0x0 +#endif +#define DB_88F6281A_OE_VAL_LOW 0x0 +#define DB_88F6281A_OE_VAL_HIGH 0x0 + +/* RD-88F6281A */ +#if defined(MV_NAND) + #define RD_88F6281A_MPP0_7 0x21111111 +#else + #define RD_88F6281A_MPP0_7 0x21112220 +#endif +#define RD_88F6281A_MPP8_15 0x11113311 +#define RD_88F6281A_MPP16_23 0x33331111 +#define RD_88F6281A_MPP24_31 0x33003333 +#define RD_88F6281A_MPP32_39 0x20440533 +#define RD_88F6281A_MPP40_47 0x22202222 +#define RD_88F6281A_MPP48_55 0x00000002 +#define RD_88F6281A_OE_LOW (BIT28 | BIT29) +#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) +#define RD_88F6281A_OE_VAL_LOW 0x0 +#define RD_88F6281A_OE_VAL_HIGH 0x0 + +/* DB-88F6192A-BP */ +#if defined(MV_NAND) + #define DB_88F6192A_MPP0_7 0x21111111 +#else + #define DB_88F6192A_MPP0_7 0x21112220 +#endif +#define DB_88F6192A_MPP8_15 0x11113311 +#define DB_88F6192A_MPP16_23 0x00501111 +#define DB_88F6192A_MPP24_31 0x00000000 +#define DB_88F6192A_MPP32_35 0x00000000 +#define DB_88F6192A_OE_LOW (BIT22 | BIT23) +#define DB_88F6192A_OE_HIGH 0x0 +#define DB_88F6192A_OE_VAL_LOW 0x0 +#define DB_88F6192A_OE_VAL_HIGH 0x0 + +/* RD-88F6192A */ +#define RD_88F6192A_MPP0_7 0x01222222 +#define RD_88F6192A_MPP8_15 0x00000011 +#define RD_88F6192A_MPP16_23 0x05550000 +#define RD_88F6192A_MPP24_31 0x0 +#define RD_88F6192A_MPP32_35 0x0 +#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) +#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) +#define RD_88F6192A_OE_VAL_LOW 0x18400 +#define RD_88F6192A_OE_VAL_HIGH 0x8 + +/* DB-88F6180A-BP */ +#if defined(MV_NAND) + #define DB_88F6180A_MPP0_7 0x21111111 +#else + #define DB_88F6180A_MPP0_7 0x01112222 +#endif +#define DB_88F6180A_MPP8_15 0x11113311 +#define DB_88F6180A_MPP16_23 0x00001111 +#define DB_88F6180A_MPP24_31 0x0 +#define DB_88F6180A_MPP32_39 0x4444c000 +#define DB_88F6180A_MPP40_44 0x00044444 +#define DB_88F6180A_OE_LOW 0x0 +#define DB_88F6180A_OE_HIGH 0x0 +#define DB_88F6180A_OE_VAL_LOW 0x0 +#define DB_88F6180A_OE_VAL_HIGH 0x0 + +/* RD-88F6281A_PCAC */ +#define RD_88F6281A_PCAC_MPP0_7 0x21111111 +#define RD_88F6281A_PCAC_MPP8_15 0x00003311 +#define RD_88F6281A_PCAC_MPP16_23 0x00001100 +#define RD_88F6281A_PCAC_MPP24_31 0x00000000 +#define RD_88F6281A_PCAC_MPP32_39 0x00000000 +#define RD_88F6281A_PCAC_MPP40_47 0x00000000 +#define RD_88F6281A_PCAC_MPP48_55 0x00000000 +#define RD_88F6281A_PCAC_OE_LOW 0x0 +#define RD_88F6281A_PCAC_OE_HIGH 0x0 +#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 +#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 + +/* SHEEVA PLUG */ +#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 +#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 +#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 +#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 +#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 +#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 +#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 +#define RD_SHEEVA_PLUG_OE_LOW 0x0 +#define RD_SHEEVA_PLUG_OE_HIGH 0x0 +#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) +#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) + +/* DB-CUSTOMER */ +#define DB_CUSTOMER_MPP0_7 0x21111111 +#define DB_CUSTOMER_MPP8_15 0x00003311 +#define DB_CUSTOMER_MPP16_23 0x00001100 +#define DB_CUSTOMER_MPP24_31 0x00000000 +#define DB_CUSTOMER_MPP32_39 0x00000000 +#define DB_CUSTOMER_MPP40_47 0x00000000 +#define DB_CUSTOMER_MPP48_55 0x00000000 +#define DB_CUSTOMER_OE_LOW 0x0 +#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) +#define DB_CUSTOMER_OE_VAL_LOW 0x0 +#define DB_CUSTOMER_OE_VAL_HIGH 0x0 + +#endif /* __INCmvBoardEnvSpech */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c new file mode 100644 index 0000000..fed0fa1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c @@ -0,0 +1,320 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* locals */ + +/******************************************************************************* +* mvCpuPclkGet - Get the CPU pClk (pipe clock) +* +* DESCRIPTION: +* This routine extract the CPU core clock. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit clock cycles in MHertz. +* +*******************************************************************************/ +/* 6180 have different clk reset sampling */ + +static MV_U32 mvCpu6180PclkGet(MV_VOID) +{ + MV_U32 tmpPClkRate=0; + MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; + + tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; + tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; + + tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; + + return tmpPClkRate; +} + + +MV_U32 mvCpuPclkGet(MV_VOID) +{ +#if defined(PCLCK_AUTO_DETECT) + MV_U32 tmpPClkRate=0; + MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; + + if(mvCtrlModelGet() == MV_6180_DEV_ID) + return mvCpu6180PclkGet(); + + tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); + tmpPClkRate = cpuCLK[tmpPClkRate]; + + return tmpPClkRate; +#else + return MV_DEFAULT_PCLK +#endif +} + +/******************************************************************************* +* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) +* +* DESCRIPTION: +* This routine extract the CPU L2 clock. +* +* RETURN: +* 32bit clock cycles in Hertz. +* +*******************************************************************************/ +static MV_U32 mvCpu6180L2ClkGet(MV_VOID) +{ + MV_U32 L2ClkRate=0; + MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; + + L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); + L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; + L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; + + L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; + + return L2ClkRate; + +} + +MV_U32 mvCpuL2ClkGet(MV_VOID) +{ +#ifdef L2CLK_AUTO_DETECT + MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; + MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; + + if(mvCtrlModelGet() == MV_6180_DEV_ID) + return mvCpu6180L2ClkGet(); + + pClkRate = mvCpuPclkGet(); + + tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); + indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); + + L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); + + return L2ClkRate; +#else + return MV_BOARD_DEFAULT_L2CLK; +#endif +} + + +/******************************************************************************* +* mvCpuNameGet - Get CPU name +* +* DESCRIPTION: +* This function returns a string describing the CPU model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. +* +* RETURN: +* None. +*******************************************************************************/ +MV_VOID mvCpuNameGet(char *pNameBuff) +{ + MV_U32 cpuModel; + + cpuModel = mvOsCpuPartGet(); + + /* The CPU module is indicated in the Processor Version Register (PVR) */ + switch(cpuModel) + { + case CPU_PART_MRVL131: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); + break; + case CPU_PART_ARM926: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); + break; + case CPU_PART_ARM946: + mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); + break; + default: + mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); + break; + } /* switch */ + + return; +} + + +#define MV_PROC_STR_SIZE 50 + +static void mvCpuIfGetL2EccMode(MV_8 *buf) +{ + MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); + if (regVal & BIT2) + mvOsSPrintf(buf, "L2 ECC Enabled"); + else + mvOsSPrintf(buf, "L2 ECC Disabled"); +} + +static void mvCpuIfGetL2Mode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT22) + mvOsSPrintf(buf, "L2 Enabled"); + else + mvOsSPrintf(buf, "L2 Disabled"); +} + +static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT24) + mvOsSPrintf(buf, "L2 Prefetch Disabled"); + else + mvOsSPrintf(buf, "L2 Prefetch Enabled"); +} + +static void mvCpuIfGetWriteAllocMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT28) + mvOsSPrintf(buf, "Write Allocate Enabled"); + else + mvOsSPrintf(buf, "Write Allocate Disabled"); +} + +static void mvCpuIfGetCpuStreamMode(MV_8 *buf) +{ + MV_U32 regVal = 0; + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + if (regVal & BIT29) + mvOsSPrintf(buf, "CPU Streaming Enabled"); + else + mvOsSPrintf(buf, "CPU Streaming Disabled"); +} + +static void mvCpuIfPrintCpuRegs(void) +{ + MV_U32 regVal = 0; + + __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ + mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ + mvOsPrintf("Control Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ + mvOsPrintf("ID Code Reg = 0x%x\n",regVal); + + __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ + mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); + +} + +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) +{ + MV_U32 count = 0; + + MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; + MV_8 L2_En_str[MV_PROC_STR_SIZE]; + MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; + MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; + MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; + + mvCpuIfGetL2Mode(L2_En_str); + mvCpuIfGetL2EccMode(L2_ECC_str); + mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); + mvCpuIfGetWriteAllocMode(Write_Alloc_str); + mvCpuIfGetCpuStreamMode(Cpu_Stream_str); + mvCpuIfPrintCpuRegs(); + + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); + count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); + return count; +} + +MV_U32 whoAmI(MV_VOID) +{ + return 0; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h new file mode 100644 index 0000000..7f58b03 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h @@ -0,0 +1,99 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuh +#define __INCmvCpuh + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* defines */ +#define CPU_PART_MRVL131 0x131 +#define CPU_PART_ARM926 0x926 +#define CPU_PART_ARM946 0x946 +#define MV_CPU_ARM_CLK_ELM_SIZE 12 +#define MV_CPU_ARM_CLK_RATIO_OFF 8 +#define MV_CPU_ARM_CLK_DDR_OFF 4 + +#ifndef MV_ASMLANGUAGE +typedef struct _mvCpuArmClk +{ + MV_U32 cpuClk; /* CPU clock in MHz */ + MV_U32 ddrClk; /* DDR clock in MHz */ + MV_U32 l2Clk; /* CPU DDR clock ratio */ + +}MV_CPU_ARM_CLK; + +MV_U32 mvCpuPclkGet(MV_VOID); +MV_VOID mvCpuNameGet(char *pNameBuff); +MV_U32 mvCpuL2ClkGet(MV_VOID); +MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); +MV_U32 whoAmI(MV_VOID); + +#endif /* MV_ASMLANGUAGE */ + + +#endif /* __INCmvCpuh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c new file mode 100644 index 0000000..fbe7c56 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c @@ -0,0 +1,296 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvCtrlEnvAddrDec.h - Marvell controller address decode library +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include "ctrlEnv/mvCtrlEnvAddrDec.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ddr2/mvDramIfRegs.h" +#include "pex/mvPexRegs.h" + +#define MV_DEBUG + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* Default Attributes array */ +MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; +extern MV_TARGET *sampleAtResetTargetArray; +/* Dram\AHBToMbus\PEX share regsiter */ + +#define CTRL_DEC_BASE_OFFS 16 +#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) +#define CTRL_DEC_BASE_ALIGNMENT 0x10000 + +#define CTRL_DEC_SIZE_OFFS 16 +#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) +#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 + +#define CTRL_DEC_WIN_EN BIT0 + + + +/******************************************************************************* +* mvCtrlAddrDecToReg - Get address decode register format values +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) +{ + + MV_U32 baseToReg=0 , sizeToReg=0; + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; + + /* Write to address decode Base Address Register */ + pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; + pAddrDecRegs->baseReg |= baseToReg; + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + return MV_BAD_PARAM; + } + + /* set size */ + pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; + pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); + + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlRegToAddrDec - Extract address decode struct from registers. +* +* DESCRIPTION: +* This function extract address decode struct from address decode +* registers given as parameters. +* +* INPUT: +* pAddrDecRegs - Address decode register struct. +* +* OUTPUT: +* pAddrDecWin - Target window data structure. +* +* RETURN: +* MV_BAD_PARAM if address decode registers data is invalid. +* +*******************************************************************************/ +MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 sizeRegVal; + + sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> + CTRL_DEC_SIZE_OFFS; + + pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); + + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; + + pAddrDecWin->baseHigh = 0; + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlAttribGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, + MV_TARGET_ATTRIB *targetAttrib) +{ + + targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; + targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; + + return MV_OK; + +} + +/******************************************************************************* +* mvCtrlGetAttrib - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) +{ + MV_TARGET target; + MV_TARGET x; + for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) + { + x = MV_CHANGE_BOOT_CS(target); + if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && + (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) + { + /* found it */ + break; + } + } + + return target; +} + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, + MV_DEC_WIN_PARAMS *pWinParam) +{ + MV_U32 baseToReg=0, sizeToReg=0; + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; + + /* Write to address decode Base Address Register */ + pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; + pWinParam->baseAddr |= baseToReg; + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); + return MV_BAD_PARAM; + } + pWinParam->size = sizeToReg; + + pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; + pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; + + return MV_OK; +} + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, + MV_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttrib; + + pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; + + /* Upper 32bit address base is supported under PCI High Address remap */ + pAddrDecWin->addrWin.baseHigh = 0; + + /* Prepare sizeReg to ctrlRegToSize function */ + pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); + + if (-1 == pAddrDecWin->addrWin.size) + { + DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); + return MV_BAD_PARAM; + } + targetAttrib.targetId = pWinParam->targetId; + targetAttrib.attrib = pWinParam->attrib; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h new file mode 100644 index 0000000..946737f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h @@ -0,0 +1,203 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAddrDech +#define __INCmvCtrlEnvAddrDech + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" + + +/* defines */ +/* DUnit attributes */ +#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 +#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 +#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) + +#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 +#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 +#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) + +#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 +#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 +#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) + +#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 +#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 +#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) + +/* RUnit (Device) attributes */ +#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 +#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 +#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 +#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 +#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) + +#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 +#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 +#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) + +#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 +#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 +#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) + +/* LMaster (PCI) attributes */ +#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 +#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) + + +#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 +#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 +#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) +#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) + +#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 + +#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 +#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 +#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) +#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) + +#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 +#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 +#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 +#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 +#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) + +/* PEX Attributes */ +#define ATMWCR_WIN_PEX_TYPE_OFFS 3 +#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 +#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) +#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) + +/* typedefs */ + +/* Unsupported attributes for address decode: */ +/* 2) PCI0/1_REQ64n control */ + +typedef struct _mvDecRegs +{ + MV_U32 baseReg; + MV_U32 baseRegHigh; + MV_U32 sizeReg; + +}MV_DEC_REGS; + +typedef struct _mvTargetAttrib +{ + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ + +}MV_TARGET_ATTRIB; + + +/* This structure describes address decode window */ +typedef struct _mvDecWin +{ + MV_TARGET target; /* Target for addr decode window */ + MV_ADDR_WIN addrWin; /* Address window of target */ + MV_BOOL enable; /* Window enable/disable */ +}MV_DEC_WIN; + +typedef struct _mvDecWinParams +{ + MV_TARGET_ID targetId; /* Target ID field */ + MV_U8 attrib; /* Attribute field */ + MV_U32 baseAddr; /* Base address in register format */ + MV_U32 size; /* Size in register format */ +}MV_DEC_WIN_PARAMS; + + +/* mvCtrlEnvAddrDec API list */ + +MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, + MV_DEC_REGS *pAddrDecRegs); + +MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, + MV_ADDR_WIN *pAddrDecWin); + +MV_STATUS mvCtrlAttribGet(MV_TARGET target, + MV_TARGET_ATTRIB *targetAttrib); + +MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); + + +MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, + MV_DEC_WIN_PARAMS *pWinParam); + +MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, + MV_DEC_WIN *pAddrDecWin); + + + + +#endif /* __INCmvCtrlEnvAddrDech */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h new file mode 100644 index 0000000..6f6367a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h @@ -0,0 +1,98 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvAsmh +#define __INCmvCtrlEnvAsmh +#include "pex/mvPexRegs.h" + +#define CHIP_BOND_REG 0x10034 +#define PCKG_OPT_MASK_AS #3 +#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK + +/* Read device ID into toReg bits 15:0 from 0xd0000000 */ +/* defines */ +#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read device ID into toReg bits 15:0 from 0xf1000000*/ +#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ + MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ + and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ + +/* Read Revision into toReg bits 7:0 0xd0000000*/ +#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + +/* Read Revision into toReg bits 7:0 0xf1000000*/ +#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ + /* Read device revision */ \ + MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ + and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ + + +#endif /* __INCmvCtrlEnvAsmh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c new file mode 100644 index 0000000..adf451d --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c @@ -0,0 +1,1825 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "mvCommon.h" +#include "mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#include "ctrlEnv/sys/mvSysPex.h" +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +#include "ctrlEnv/sys/mvSysGbe.h" +#endif + +#if defined(MV_INCLUDE_XOR) +#include "ctrlEnv/sys/mvSysXor.h" +#endif + +#if defined(MV_INCLUDE_SATA) +#include "ctrlEnv/sys/mvSysSata.h" +#endif + +#if defined(MV_INCLUDE_USB) +#include "ctrlEnv/sys/mvSysUsb.h" +#endif + +#if defined(MV_INCLUDE_AUDIO) +#include "ctrlEnv/sys/mvSysAudio.h" +#endif + +#if defined(MV_INCLUDE_CESA) +#include "ctrlEnv/sys/mvSysCesa.h" +#endif + +#if defined(MV_INCLUDE_TS) +#include "ctrlEnv/sys/mvSysTs.h" +#endif + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/******************************************************************************* +* mvCtrlEnvInit - Initialize Marvell controller environment. +* +* DESCRIPTION: +* This function get environment information and initialize controller +* internal/external environment. For example +* 1) MPP settings according to board MPP macros. +* NOTE: It is the user responsibility to shut down all DMA channels +* in device and disable controller sub units interrupts during +* boot process. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCtrlEnvInit(MV_VOID) +{ + MV_U32 mppGroup; + MV_U32 devId; + MV_U32 boardId; + MV_U32 i; + MV_U32 maxMppGrp = 1; + MV_U32 mppVal = 0; + MV_U32 bootVal = 0; + MV_U32 mppGroupType = 0; + MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; + MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; + + devId = mvCtrlModelGet(); + boardId= mvBoardIdGet(); + + switch(devId){ + case MV_6281_DEV_ID: + maxMppGrp = MV_6281_MPP_MAX_GROUP; + break; + case MV_6192_DEV_ID: + maxMppGrp = MV_6192_MPP_MAX_GROUP; + break; + case MV_6190_DEV_ID: + maxMppGrp = MV_6190_MPP_MAX_GROUP; + break; + case MV_6180_DEV_ID: + maxMppGrp = MV_6180_MPP_MAX_GROUP; + break; + } + + /* MPP Init */ + /* We split mpp init to 3 phases: + * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write + * in phase 2. + * 2. We detect the mpp group type and according the mpp values [35:20]. + * 3. We detect the mpp group type and according the mpp values [49:36]. + */ + /* Mpp phase 1 mpp[19:0] */ + /* Read MPP group from board level and assign to MPP register */ + for (mppGroup = 0; mppGroup < 3; mppGroup++) + { + mppVal = mvBoardMppGet(mppGroup); + if (mppGroup == 0) + { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + if (mvCtrlIsBootFromSPI()) + { + mppVal &= ~0xffff; + bootVal &= 0xffff; + mppVal |= bootVal; + } + else if (mvCtrlIsBootFromSPIUseNAND()) + { + mppVal &= ~0xf0000000; + bootVal &= 0xf0000000; + mppVal |= bootVal; + } + else if (mvCtrlIsBootFromNAND()) + { + mppVal &= ~0xffffff; + bootVal &= 0xffffff; + mppVal |= bootVal; + } + } + + if (mppGroup == 2) + { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + if (mvCtrlIsBootFromNAND()) + { + mppVal &= ~0xff00; + bootVal &= 0xff00; + mppVal |= bootVal; + } + } + + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + + /* Identify MPPs group */ + mvBoardMppGroupIdUpdate(); + + /* Update MPPs mux relevent only on Marvell DB */ + if ((boardId == DB_88F6281A_BP_ID) || + (boardId == DB_88F6180A_BP_ID)) + mvBoardMppMuxSet(); + + mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); + + /* Mpp phase 2 */ + /* Read MPP group from board level and assign to MPP register */ + if (devId != MV_6180_DEV_ID) + { + i = 0; + for (mppGroup = 2; mppGroup < 5; mppGroup++) + { + if ((mppGroupType == MV_BOARD_OTHER) || + (boardId == RD_88F6281A_ID) || + (boardId == RD_88F6192A_ID) || + (boardId == RD_88F6190A_ID) || + (boardId == RD_88F6281A_PCAC_ID) || + (boardId == SHEEVA_PLUG_ID)) + mppVal = mvBoardMppGet(mppGroup); + else + { + mppVal = mppGroup1[mppGroupType][i]; + i++; + } + + /* Group 2 is shared mpp[23:16] */ + if (mppGroup == 2) + { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + mppVal &= ~0xffff; + bootVal &= 0xffff; + mppVal |= bootVal; + } + + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + } + + if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) + return MV_OK; + + /* Mpp phase 3 */ + mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); + /* Read MPP group from board level and assign to MPP register */ + i = 0; + for (mppGroup = 4; mppGroup < 7; mppGroup++) + { + if ((mppGroupType == MV_BOARD_OTHER) || + (boardId == RD_88F6281A_ID) || + (boardId == RD_88F6281A_PCAC_ID) || + (boardId == SHEEVA_PLUG_ID)) + mppVal = mvBoardMppGet(mppGroup); + else + { + mppVal = mppGroup2[mppGroupType][i]; + i++; + } + + /* Group 4 is shared mpp[35:32] */ + if (mppGroup == 4) + { + bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); + mppVal &= ~0xffff; + bootVal &= 0xffff; + mppVal |= bootVal; + } + + MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); + } + /* Update SSCG configuration register*/ + if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || + mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) + MV_REG_WRITE(0x100d8, 0x53); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlMppRegGet - return reg address of mpp group +* +* DESCRIPTION: +* +* INPUT: +* mppGroup - MPP group. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - Register address. +* +*******************************************************************************/ +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) +{ + MV_U32 ret; + + switch(mppGroup){ + case (0): ret = MPP_CONTROL_REG0; + break; + case (1): ret = MPP_CONTROL_REG1; + break; + case (2): ret = MPP_CONTROL_REG2; + break; + case (3): ret = MPP_CONTROL_REG3; + break; + case (4): ret = MPP_CONTROL_REG4; + break; + case (5): ret = MPP_CONTROL_REG5; + break; + case (6): ret = MPP_CONTROL_REG6; + break; + default: ret = MPP_CONTROL_REG0; + break; + } + return ret; +} +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. +* +* DESCRIPTION: +* This function returns Marvell controller number of PEX interfaces. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of PEX interfaces. If controller +* ID is undefined the function returns '0'. +* +*******************************************************************************/ +MV_U32 mvCtrlPexMaxIfGet(MV_VOID) +{ + + return MV_PEX_MAX_IF; +} +#endif + +#if defined(MV_INCLUDE_GIG_ETH) +/******************************************************************************* +* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. +* +* DESCRIPTION: +* This function returns Marvell controller number of etherent port. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of etherent port. +* +*******************************************************************************/ +MV_U32 mvCtrlEthMaxPortGet(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_ETH_MAX_PORTS; + break; + case MV_6192_DEV_ID: + return MV_6192_ETH_MAX_PORTS; + break; + case MV_6190_DEV_ID: + return MV_6190_ETH_MAX_PORTS; + break; + case MV_6180_DEV_ID: + return MV_6180_ETH_MAX_PORTS; + break; + } + return 0; + +} +#endif + +#if defined(MV_INCLUDE_XOR) +/******************************************************************************* +* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. +* +* DESCRIPTION: +* This function returns Marvell controller number of XOR channels. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Marvell controller number of XOR channels. +* +*******************************************************************************/ +MV_U32 mvCtrlXorMaxChanGet(MV_VOID) +{ + return MV_XOR_MAX_CHAN; +} +#endif + +#if defined(MV_INCLUDE_USB) +/******************************************************************************* +* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* returns number of Marvell USB controllers. +* +*******************************************************************************/ +MV_U32 mvCtrlUsbMaxGet(void) +{ + return MV_USB_MAX_PORTS; +} +#endif + + +#if defined(MV_INCLUDE_NAND) +/******************************************************************************* +* mvCtrlNandSupport - Return if this controller has integrated NAND flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if NAND is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlNandSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_NAND; + break; + case MV_6192_DEV_ID: + return MV_6192_NAND; + break; + case MV_6190_DEV_ID: + return MV_6190_NAND; + break; + case MV_6180_DEV_ID: + return MV_6180_NAND; + break; + } + return 0; + +} +#endif + +#if defined(MV_INCLUDE_SDIO) +/******************************************************************************* +* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if SDIO is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlSdioSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_SDIO; + break; + case MV_6192_DEV_ID: + return MV_6192_SDIO; + break; + case MV_6190_DEV_ID: + return MV_6190_SDIO; + break; + case MV_6180_DEV_ID: + return MV_6180_SDIO; + break; + } + return 0; + +} +#endif + +#if defined(MV_INCLUDE_TS) +/******************************************************************************* +* mvCtrlTsSupport - Return if this controller has integrated TS flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if TS is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlTsSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_TS; + break; + case MV_6192_DEV_ID: + return MV_6192_TS; + break; + case MV_6190_DEV_ID: + return MV_6190_TS; + break; + case MV_6180_DEV_ID: + return MV_6180_TS; + break; + } + return 0; +} +#endif + +#if defined(MV_INCLUDE_AUDIO) +/******************************************************************************* +* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if AUDIO is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlAudioSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_AUDIO; + break; + case MV_6192_DEV_ID: + return MV_6192_AUDIO; + break; + case MV_6190_DEV_ID: + return MV_6190_AUDIO; + break; + case MV_6180_DEV_ID: + return MV_6180_AUDIO; + break; + } + return 0; + +} +#endif + +#if defined(MV_INCLUDE_TDM) +/******************************************************************************* +* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if TDM is supported and MV_FALSE otherwise +* +*******************************************************************************/ +MV_U32 mvCtrlTdmSupport(MV_VOID) +{ + MV_U32 devId; + + devId = mvCtrlModelGet(); + + switch(devId){ + case MV_6281_DEV_ID: + return MV_6281_TDM; + break; + case MV_6192_DEV_ID: + return MV_6192_TDM; + break; + case MV_6190_DEV_ID: + return MV_6190_TDM; + break; + case MV_6180_DEV_ID: + return MV_6180_TDM; + break; + } + return 0; + +} +#endif + +/******************************************************************************* +* mvCtrlModelGet - Get Marvell controller device model (Id) +* +* DESCRIPTION: +* This function returns 16bit describing the device model (ID) as defined +* in PCI Device and Vendor ID configuration register offset 0x0. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 16bit desscribing Marvell controller ID +* +*******************************************************************************/ +MV_U16 mvCtrlModelGet(MV_VOID) +{ + MV_U32 devId; + + devId = MV_REG_READ(CHIP_BOND_REG); + devId &= PCKG_OPT_MASK; + + switch(devId){ + case 2: + return MV_6281_DEV_ID; + break; + case 1: + if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) + == MV_6190_DEV_ID) + return MV_6190_DEV_ID; + else + return MV_6192_DEV_ID; + break; + case 0: + return MV_6180_DEV_ID; + break; + } + + return 0; +} +/******************************************************************************* +* mvCtrlRevGet - Get Marvell controller device revision number +* +* DESCRIPTION: +* This function returns 8bit describing the device revision as defined +* in PCI Express Class Code and Revision ID Register. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 8bit desscribing Marvell controller revision number +* +*******************************************************************************/ +MV_U8 mvCtrlRevGet(MV_VOID) +{ + MV_U8 revNum; +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Check pex power state */ + MV_U32 pexPower; + pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); +#endif + revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) + /* Return to power off state */ + if (pexPower == MV_FALSE) + mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); +#endif + return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); +} + +/******************************************************************************* +* mvCtrlNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ +MV_STATUS mvCtrlNameGet(char *pNameBuff) +{ + mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, + mvCtrlModelGet(), mvCtrlRevGet()); + + return MV_OK; +} + +/******************************************************************************* +* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision +* +* DESCRIPTION: +* This function returns 32bit value describing both Device ID and Revision +* as defined in PCI Express Device and Vendor ID Register and device revision +* as defined in PCI Express Class Code and Revision ID Register. + +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing both controller device ID and revision number +* +*******************************************************************************/ +MV_U32 mvCtrlModelRevGet(MV_VOID) +{ + return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); +} + +/******************************************************************************* +* mvCtrlModelRevNameGet - Get Marvell controller name +* +* DESCRIPTION: +* This function returns a string describing the device model and revision. +* +* INPUT: +* None. +* +* OUTPUT: +* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. +* +* RETURN: +* +* MV_ERROR if informantion can not be read. +*******************************************************************************/ + +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) +{ + + switch (mvCtrlModelRevGet()) + { + case MV_6281_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); + break; + case MV_6192_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); + break; + case MV_6180_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); + break; + case MV_6190_A0_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); + break; + case MV_6281_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); + break; + case MV_6192_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); + break; + case MV_6180_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); + break; + case MV_6190_A1_ID: + mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); + break; + default: + mvCtrlNameGet(pNameBuff); + break; + } + + return MV_OK; +} + + +/******************************************************************************* +* ctrlWinOverlapTest - Test address windows for overlaping. +* +* DESCRIPTION: +* This function checks the given two address windows for overlaping. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* +* MV_TRUE if address window overlaps, MV_FALSE otherwise. +*******************************************************************************/ +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + /* check if we have overflow than 4G*/ + if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| + ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) + { + return MV_TRUE; + } + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size-1; + winTop2 = winBase2 + pAddrWin2->size-1; + + + if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || + ((winBase1 <= winBase2) && (winBase2 <= winTop1))) + { + return MV_TRUE; + } + else + { + return MV_FALSE; + } +} + +/******************************************************************************* +* ctrlWinWithinWinTest - Test address windows for overlaping. +* +* DESCRIPTION: +* This function checks the given win1 boundries is within +* win2 boundries. +* +* INPUT: +* pAddrWin1 - Address window 1. +* pAddrWin2 - Address window 2. +* +* OUTPUT: +* None. +* +* RETURN: +* +* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. +*******************************************************************************/ +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) +{ + MV_U32 winBase1, winBase2; + MV_U32 winTop1, winTop2; + + winBase1 = pAddrWin1->baseLow; + winBase2 = pAddrWin2->baseLow; + winTop1 = winBase1 + pAddrWin1->size -1; + winTop2 = winBase2 + pAddrWin2->size -1; + + if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || + ((winTop1 >= winBase2) && (winTop1 <= winTop2))) + { + return MV_TRUE; + } + else + { + return MV_FALSE; + } +} + +static const char* cntrlName[] = TARGETS_NAME_ARRAY; + +/******************************************************************************* +* mvCtrlTargetNameGet - Get Marvell controller target name +* +* DESCRIPTION: +* This function convert the trget enumeration to string. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Target name (const MV_8 *) +*******************************************************************************/ +const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) +{ + + if (target >= MAX_TARGETS) + { + return "target unknown"; + } + + return cntrlName[target]; +} + +/******************************************************************************* +* mvCtrlAddrDecShow - Print the Controller units address decode map. +* +* DESCRIPTION: +* This function the Controller units address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCtrlAddrDecShow(MV_VOID) +{ + mvCpuIfAddDecShow(); + mvAhbToMbusAddDecShow(); +#if defined(MV_INCLUDE_PEX) + mvPexAddrDecShow(); +#endif +#if defined(MV_INCLUDE_USB) + mvUsbAddrDecShow(); +#endif +#if defined(MV_INCLUDE_GIG_ETH) + mvEthAddrDecShow(); +#endif +#if defined(MV_INCLUDE_XOR) + mvXorAddrDecShow(); +#endif +#if defined(MV_INCLUDE_SATA) + mvSataAddrDecShow(); +#endif +#if defined(MV_INCLUDE_AUDIO) + mvAudioAddrDecShow(); +#endif +#if defined(MV_INCLUDE_TS) + mvTsuAddrDecShow(); +#endif +} + +/******************************************************************************* +* ctrlSizeToReg - Extract size value for register assignment. +* +* DESCRIPTION: +* Address decode size parameter must be programed from LSB to MSB as +* sequence of 1's followed by sequence of 0's. The number of 1's +* specifies the size of the window in 64 KB granularity (e.g. a +* value of 0x00ff specifies 256x64k = 16 MB). +* This function extract the size value from the size parameter according +* to given aligment paramter. For example for size 0x1000000 (16MB) and +* aligment 0x10000 (64KB) the function will return 0x00FF. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size register value correspond to size parameter. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) +{ + MV_U32 retVal; + + /* Check size parameter alignment */ + if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); + return -1; + } + + /* Take out the "alignment" portion out of the size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + /* and size is 0x1000000 (16MB) for example */ + while(alignment & 1) /* Check that alignmet LSB is set */ + { + size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ + alignment = (alignment >> 1); + } + + /* If after the alignment first '0' was met we still have '1' in */ + /* it then aligment is invalid (not power of 2) */ + if (alignment) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", + (MV_U32)alignment)); + return -1; + } + + /* Now the size is shifted right according to aligment: 0x0100 */ + size--; /* Now the size is a sequance of '1': 0x00ff */ + + retVal = size ; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + while(size & 1) /* Check that LSB is set */ + { + size = (size >> 1); /* If LSB is set, move one bit to the right */ + } + + if (size) /* Sequance of 1's is over. Check that we have no other 1's */ + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", + size)); + return -1; + } + + return retVal; + +} + +/******************************************************************************* +* ctrlRegToSize - Extract size value from register value. +* +* DESCRIPTION: +* This function extract a size value from the register size parameter +* according to given aligment paramter. For example for register size +* value 0xff and aligment 0x10000 the function will return 0x01000000. +* +* INPUT: +* regSize - Size as in register format. See ctrlSizeToReg. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size. +* If value is '-1' size parameter or aligment are invalid. +*******************************************************************************/ +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) +{ + MV_U32 temp; + + /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ + temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ + + while(temp & 1) /* Check that LSB is set */ + { + temp = (temp >> 1); /* If LSB is set, move one bit to the right */ + } + + if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ + { + DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", + regSize)); + return -1; + } + + + /* Check that aligment is a power of two */ + temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ + + while(temp & 1) /* Check that alignmet LSB is set */ + { + temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ + } + + /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ + /* then 'temp' is invalid (not power of 2) */ + if (temp) + { + DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", + alignment)); + return -1; + } + + regSize++; /* Now the size is 0x0100 */ + + /* Add in the "alignment" portion to the register size parameter */ + alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ + + while(alignment & 1) /* Check that alignmet LSB is set */ + { + regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ + alignment = (alignment >> 1); + } + + return regSize; +} + + +/******************************************************************************* +* ctrlSizeRegRoundUp - Round up given size +* +* DESCRIPTION: +* This function round up a given size to a size that fits the +* restrictions of size format given an aligment parameter. +* to given aligment paramter. For example for size parameter 0xa1000 and +* aligment 0x1000 the function will return 0xFF000. +* +* INPUT: +* size - Size. +* alignment - Size alignment. Note that alignment must be power of 2! +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit describing size value correspond to size in register. +*******************************************************************************/ +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) +{ + MV_U32 msbBit = 0; + MV_U32 retSize; + + /* Check if size parameter is already comply with restriction */ + if (!(-1 == ctrlSizeToReg(size, alignment))) + { + return size; + } + + while(size) + { + size = (size >> 1); + msbBit++; + } + + retSize = (1 << msbBit); + + if (retSize < alignment) + { + return alignment; + } + else + { + return retSize; + } +} +/******************************************************************************* +* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button +* was pressed and clear counter +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: number of milliseconds the reset button was pressed +*******************************************************************************/ +MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) +{ + static volatile MV_U32 Count = 0; + + if(!Count) { + Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); + Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); + /* clear counter for next boot */ + MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); + } + + DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); + + return Count; +} + +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) +{ + MV_U32 satr = 0; + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); + if(mvCtrlModelGet() == MV_6180_DEV_ID) + { + if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) + return MV_TRUE; + else + return MV_FALSE; + } + satr = satr & MSAR_BOOT_MODE_MASK; + if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) + return MV_TRUE; + else + return MV_FALSE; +} + +MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) +{ + MV_U32 satr = 0; + if(mvCtrlModelGet() == MV_6180_DEV_ID) + return MV_FALSE; + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); + satr = satr & MSAR_BOOT_MODE_MASK; + + if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) + return MV_TRUE; + else + return MV_FALSE; +} + +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) +{ + MV_U32 satr = 0; + satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); + if(mvCtrlModelGet() == MV_6180_DEV_ID) + { + if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) + return MV_TRUE; + else + return MV_FALSE; + } + satr = satr & MSAR_BOOT_MODE_MASK; + if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) + return MV_TRUE; + else + return MV_FALSE; +} + +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +/******************************************************************************* +* mvCtrlPwrSaveOn - Set Power save mode +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrSaveOn(MV_VOID) +{ + unsigned long old,temp; + /* Disable int */ + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + + /* Set SoC in power save */ + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); + /* Wait for int */ + __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); + + /* Enabled int */ + __asm__ __volatile__("msr cpsr_c, %0" + : + : "r" (old) + : "memory"); +} + + + +/******************************************************************************* +* mvCtrlPwrSaveOff - Go out of power save mode +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrSaveOff(MV_VOID) +{ + unsigned long old,temp; + /* Disable int */ + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + + /* Set SoC in power save */ + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); + /* Wait for int */ + __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); + + /* Enabled int */ + __asm__ __volatile__("msr cpsr_c, %0" + : + : "r" (old) + : "memory"); +} + +/******************************************************************************* +* mvCtrlPwrClckSet - Set Power State for specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_TS) + case TS_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + } + else + { + MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); + } + break; +#endif + + default: + + break; + + } +} + +/******************************************************************************* +* mvCtrlPwrClckGet - Get Power State of specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); + MV_BOOL state = MV_TRUE; + + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TS) + case TS_UNIT_ID: + if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SDIO) + case SDIO_UNIT_ID: + if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_TDM) + case TDM_UNIT_ID: + if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif + + default: + state = MV_TRUE; + break; + } + + + return state; +} +/******************************************************************************* +* mvCtrlPwrMemSet - Set Power State for memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +*******************************************************************************/ +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) +{ + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_INTEG_SATA) + case SATA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); + } + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); + } + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + if (enable == MV_FALSE) + { + MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); + } + else + { + MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); + } + break; +#endif + default: + + break; + + } +} + +/******************************************************************************* +* mvCtrlPwrMemGet - Get Power State of memory on specific Unit +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) +{ + MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); + MV_BOOL state = MV_TRUE; + + switch (unitId) + { +#if defined(MV_INCLUDE_PEX) + case PEX_UNIT_ID: + if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + + break; +#endif +#if defined(MV_INCLUDE_GIG_ETH) + case ETH_GIG_UNIT_ID: + if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_SATA) + case SATA_UNIT_ID: + if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_CESA) + case CESA_UNIT_ID: + if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_USB) + case USB_UNIT_ID: + if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_AUDIO) + case AUDIO_UNIT_ID: + if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif +#if defined(MV_INCLUDE_XOR) + case XOR_UNIT_ID: + if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) + { + state = MV_FALSE; + } + else state = MV_TRUE; + break; +#endif + + default: + state = MV_TRUE; + break; + } + + + return state; +} +#else +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} +#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ + + +/******************************************************************************* +* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_VOID mvMPPConfigToSPI(MV_VOID) +{ + MV_U32 mppVal = 0; + MV_U32 bootVal = 0; + + if(!mvCtrlIsBootFromSPIUseNAND()) + return; + mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ + bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); + bootVal &= 0xffff000f; + mppVal |= bootVal; + + MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); +} + + +/******************************************************************************* +* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +******************************************************************************/ +MV_VOID mvMPPConfigToDefault(MV_VOID) +{ + MV_U32 mppVal = 0; + MV_U32 bootVal = 0; + + if(!mvCtrlIsBootFromSPIUseNAND()) + return; + mppVal = mvBoardMppGet(0); + bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); + mppVal &= ~0xffff000f; + bootVal &= 0xffff000f; + mppVal |= bootVal; + + MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); +} + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h new file mode 100644 index 0000000..6e2e813 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h @@ -0,0 +1,185 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCtrlEnvLibh +#define __INCmvCtrlEnvLibh + +/* includes */ +#include "mvSysHwConfig.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mvOs.h" +#include "boardEnv/mvBoardEnvLib.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + + +/* typedefs */ + +/* This enumerator describes the possible HW cache coherency policies the */ +/* controllers supports. */ +typedef enum _mvCachePolicy +{ + NO_COHERENCY, /* No HW cache coherency support */ + WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ + WB_COHERENCY /* HW cache coherency supported in Write Back policy */ +}MV_CACHE_POLICY; + + +/* The swapping is referred to a 64-bit words (as this is the controller */ +/* internal data path width). This enumerator describes the possible */ +/* data swap types. Below is an example of the data 0x0011223344556677 */ +typedef enum _mvSwapType +{ + MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ + MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ + MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ + MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ + SWAP_TYPE_MAX /* Delimiter for this enumerator */ +}MV_SWAP_TYPE; + +/* This structure describes access rights for Access protection windows */ +/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ +/* Note that the permission enumerator coresponds to its register format. */ +/* For example, Read only premission is presented as "1" in register field. */ +typedef enum _mvAccessRights +{ + NO_ACCESS_ALLOWED = 0, /* No access allowed */ + READ_ONLY = 1, /* Read only permission */ + ACC_RESERVED = 2, /* Reserved access right */ + FULL_ACCESS = 3, /* Read and Write permission */ + MAX_ACC_RIGHTS +}MV_ACCESS_RIGHTS; + + +/* mcspLib.h API list */ + +MV_STATUS mvCtrlEnvInit(MV_VOID); +MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); + +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCtrlPexMaxIfGet(MV_VOID); +#else +#define mvCtrlPexMaxIfGet() (0) +#endif + +#define mvCtrlPciIfMaxIfGet() (0) + +#if defined(MV_INCLUDE_GIG_ETH) +MV_U32 mvCtrlEthMaxPortGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_XOR) +MV_U32 mvCtrlXorMaxChanGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_USB) +MV_U32 mvCtrlUsbMaxGet(MV_VOID); +#endif +#if defined(MV_INCLUDE_NAND) +MV_U32 mvCtrlNandSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_SDIO) +MV_U32 mvCtrlSdioSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_TS) +MV_U32 mvCtrlTsSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_AUDIO) +MV_U32 mvCtrlAudioSupport(MV_VOID); +#endif +#if defined(MV_INCLUDE_TDM) +MV_U32 mvCtrlTdmSupport(MV_VOID); +#endif + +MV_U16 mvCtrlModelGet(MV_VOID); +MV_U8 mvCtrlRevGet(MV_VOID); +MV_STATUS mvCtrlNameGet(char *pNameBuff); +MV_U32 mvCtrlModelRevGet(MV_VOID); +MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); +MV_VOID mvCtrlAddrDecShow(MV_VOID); +const MV_8* mvCtrlTargetNameGet(MV_TARGET target); +MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); +MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); +MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); +MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); +MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); +MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); + +MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); +MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); +MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); +MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); +MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); +#if defined(MV_INCLUDE_CLK_PWR_CNTRL) +MV_VOID mvCtrlPwrSaveOn(MV_VOID); +MV_VOID mvCtrlPwrSaveOff(MV_VOID); +#endif +MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); +MV_VOID mvMPPConfigToSPI(MV_VOID); +MV_VOID mvMPPConfigToDefault(MV_VOID); + + +#endif /* __INCmvCtrlEnvLibh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h new file mode 100644 index 0000000..ae3f141 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h @@ -0,0 +1,419 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvRegsh +#define __INCmvCtrlEnvRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* CV Support */ +#define PEX0_MEM0 PEX0_MEM +#define PCI0_MEM0 PEX0_MEM + +/* Controller revision info */ +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +/* Controler environment registers offsets */ + +/* Power Managment Control */ +#define POWER_MNG_MEM_CTRL_REG 0x20118 + +#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) +#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) +#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) + +#define PMC_PEXSTOPMEM_OFFS 1 +#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) +#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) +#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) + +#define PMC_USBSTOPMEM_OFFS 2 +#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) +#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) +#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) + +#define PMC_DUNITSTOPMEM_OFFS 3 +#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) +#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) + +#define PMC_RUNITSTOPMEM_OFFS 4 +#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) +#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) +#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) + +#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) +#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) +#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) + +#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) +#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) +#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) + +#define PMC_SESTOPMEM_OFFS 8 +#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) +#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) +#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) + +#define PMC_AUDIOSTOPMEM_OFFS 9 +#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) +#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) +#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) + +#define POWER_MNG_CTRL_REG 0x2011C + +#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) +#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) +#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) + +#define PMC_PEXPHYSTOPCLOCK_OFFS 1 +#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) +#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) +#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) + +#define PMC_PEXSTOPCLOCK_OFFS 2 +#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) +#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) +#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) + +#define PMC_USBSTOPCLOCK_OFFS 3 +#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) +#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) +#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) + +#define PMC_SDIOSTOPCLOCK_OFFS 4 +#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) +#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) + +#define PMC_TSSTOPCLOCK_OFFS 5 +#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) +#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) +#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) + +#define PMC_AUDIOSTOPCLOCK_OFFS 9 +#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) +#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) +#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) + +#define PMC_POWERSAVE_OFFS 11 +#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) +#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) +#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) + + + + +#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) +#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) +#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) +#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) + +#define PMC_SESTOPCLOCK_OFFS 17 +#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) +#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) + +#define PMC_TDMSTOPCLOCK_OFFS 20 +#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) +#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) + + +/* Controler environment registers offsets */ +#define MPP_CONTROL_REG0 0x10000 +#define MPP_CONTROL_REG1 0x10004 +#define MPP_CONTROL_REG2 0x10008 +#define MPP_CONTROL_REG3 0x1000C +#define MPP_CONTROL_REG4 0x10010 +#define MPP_CONTROL_REG5 0x10014 +#define MPP_CONTROL_REG6 0x10018 +#define MPP_SAMPLE_AT_RESET 0x10030 +#define CHIP_BOND_REG 0x10034 +#define SYSRST_LENGTH_COUNTER_REG 0x10050 +#define SLCR_COUNT_OFFS 0 +#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) +#define SLCR_CLR_OFFS 31 +#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) +#define PCKG_OPT_MASK 0x3 +#define MPP_OUTPUT_DRIVE_REG 0x100E0 +#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 +#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) +#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) +#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 +#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) +#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) + +#define MSAR_BOOT_MODE_OFFS 12 +#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) +#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) + +#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ + ((X & 0x2) << 1)) +#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 +#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 + +#define MSAR_TCLCK_OFFS 21 +#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) +#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) + + +#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ + ((X & 0x18) >> 1)) + +#define MSAR_CPUCLCK_OFFS_6180 2 +#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) + +#define MSAR_DDRCLCK_RTIO_OFFS 5 +#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) + +#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) + +#ifndef MV_ASMLANGUAGE +/* CPU clock for 6281,6192 0->Resereved */ +#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ + 600000000, 0, 800000000, 1000000000, \ + 0, 1200000000, 0, 0, \ + 1500000000, 0, 0, 0} + +/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ +#define MV_DDR_CLCK_RTIO_TBL {\ + {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ + {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ + {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ + {0, 0}, {0, 0}, {0, 0}, {0, 0} \ +} + +/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ +#define MV_L2_CLCK_RTIO_TBL {\ + {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ + {0, 0}, {0, 0}, {0, 0}, {0, 0} \ +} + +/* 6180 have different clk reset sampling */ +/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ +#define MV_CPU6180_DDR_L2_CLCK_TBL { \ + {0, 0, 0 },\ + {0, 0, 0 },\ + {0, 0, 0 },\ + {0, 0, 0 },\ + {0, 0, 0 },\ + {600000000, 200000000, 300000000 },\ + {800000000, 200000000, 400000000 },\ + {0, 0, 0 }\ +} + + + +/* These macros help units to identify a target Mbus Arbiter group */ +#define MV_TARGET_IS_DRAM(target) \ + ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) + +#define MV_TARGET_IS_PEX0(target) \ + ((target >= PEX0_MEM) && (target <= PEX0_IO)) + +#define MV_TARGET_IS_PEX1(target) 0 + +#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) + +#define MV_TARGET_IS_DEVICE(target) \ + ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) + +#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 + +#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ + (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ + (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ + & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) + + +#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ + sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ + MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ + ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ + >> MSAR_BOOT_MODE_OFFS)]:(target)) + +#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ + +#define BOOT_TARGETS_NAME_ARRAY { \ + TBL_TERM, \ + TBL_TERM, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + BOOT_ROM_CS, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM \ +} + +#define BOOT_TARGETS_NAME_ARRAY_6180 { \ + TBL_TERM, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM, \ + TBL_TERM, \ + BOOT_ROM_CS, \ + TBL_TERM, \ + TBL_TERM \ +} + + +/* For old competability */ +#define DEVICE_CS0 NFLASH_CS +#define DEVICE_CS1 SPI_CS +#define DEVICE_CS2 BOOT_ROM_CS +#define DEVICE_CS3 DEV_BOOCS +#define MV_BOOTDEVICE_INDEX 0 + +#define START_DEV_CS DEV_CS0 +#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) + +#define PCI_IF0_MEM0 PEX0_MEM +#define PCI_IF0_IO PEX0_IO + + +/* This enumerator defines the Marvell controller target ID */ +typedef enum _mvTargetId +{ + DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ + DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ + PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ + CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ + SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ + MAX_TARGETS_ID +}MV_TARGET_ID; + + +/* This enumerator described the possible Controller paripheral targets. */ +/* Controller peripherals are designated memory/IO address spaces that the */ +/* controller can access. They are also refered as "targets" */ +typedef enum _mvTarget +{ + TBL_TERM = -1, /* none valid target, used as targets list terminator*/ + SDRAM_CS0, /* SDRAM chip select 0 */ + SDRAM_CS1, /* SDRAM chip select 1 */ + SDRAM_CS2, /* SDRAM chip select 2 */ + SDRAM_CS3, /* SDRAM chip select 3 */ + PEX0_MEM, /* PCI Express 0 Memory */ + PEX0_IO, /* PCI Express 0 IO */ + INTER_REGS, /* Internal registers */ + NFLASH_CS, /* NFLASH_CS */ + SPI_CS, /* SPI_CS */ + BOOT_ROM_CS, /* BOOT_ROM_CS */ + DEV_BOOCS, /* DEV_BOOCS */ + CRYPT_ENG, /* Crypto Engine */ +#ifdef MV_INCLUDE_SAGE + SAGE_UNIT, /* SAGE Unit */ +#endif + MAX_TARGETS + +}MV_TARGET; + +#define TARGETS_DEF_ARRAY { \ + {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ + {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ + {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ + {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ + {0xFF, 0xFF }, /* INTER_REGS */ \ + {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ + {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ + {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ + {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ + {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ + {0x00, SAGE_TARGET_ID } \ +} + + +#define TARGETS_NAME_ARRAY { \ + "SDRAM_CS0", /* SDRAM_CS0 */ \ + "SDRAM_CS1", /* SDRAM_CS1 */ \ + "SDRAM_CS2", /* SDRAM_CS2 */ \ + "SDRAM_CS3", /* SDRAM_CS3 */ \ + "PEX0_MEM", /* PEX0_MEM */ \ + "PEX0_IO", /* PEX0_IO */ \ + "INTER_REGS", /* INTER_REGS */ \ + "NFLASH_CS", /* NFLASH_CS */ \ + "SPI_CS", /* SPI_CS */ \ + "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ + "DEV_BOOTCS", /* DEV_BOOCS */ \ + "CRYPT_ENG", /* CRYPT_ENG */ \ + "SAGE_UNIT" /* SAGE_UNIT */ \ +} +#endif /* MV_ASMLANGUAGE */ + + +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h new file mode 100644 index 0000000..e41d80a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h @@ -0,0 +1,257 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvCtrlEnvSpech +#define __INCmvCtrlEnvSpech + +#include "mvDeviceId.h" +#include "mvSysHwConfig.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define MV_ARM_SOC +#define SOC_NAME_PREFIX "MV88F" + + +/* units base and port numbers */ +#ifdef MV_ASMLANGUAGE +#define XOR_UNIT_BASE(unit) 0x60800 +#else +#define MV_XOR_REG_BASE 0x60000 +#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) +#endif + +#define TDM_REG_BASE 0xD0000 +#define USB_REG_BASE(dev) 0x50000 +#define AUDIO_REG_BASE 0xA0000 +#define SATA_REG_BASE 0x80000 +#define MV_CESA_REG_BASE 0x3D000 +#define MV_CESA_TDMA_REG_BASE 0x30000 +#define MV_SDIO_REG_BASE 0x90000 +#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) +#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) +#define DRAM_BASE 0x0 +#define CNTMR_BASE 0x20300 +#define TWSI_SLAVE_BASE(chanNum) 0x11000 +#define PEX_IF_BASE(pexIf) 0x40000 +#define MPP_REG_BASE 0x10000 +#define TSU_GLOBAL_REG_BASE 0xB4000 +#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 + +#define INTER_REGS_SIZE _1M +/* This define describes the TWSI interrupt bit and location */ +#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 +#define TWSI0_CPU_MAIN_INT_BIT (1<<29) +#define TWSI_SPEED 100000 + +#define MV_GPP_MAX_GROUP 2 +#define MV_CNTMR_MAX_COUNTER 2 +#define MV_UART_MAX_CHAN 2 +#define MV_XOR_MAX_UNIT 2 +#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ +#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ +#define MV_SATA_MAX_CHAN 2 + +#define MV_6281_MPP_MAX_MODULE 2 +#define MV_6192_MPP_MAX_MODULE 1 +#define MV_6190_MPP_MAX_MODULE 1 +#define MV_6180_MPP_MAX_MODULE 2 +#define MV_6281_MPP_MAX_GROUP 7 +#define MV_6192_MPP_MAX_GROUP 4 +#define MV_6190_MPP_MAX_GROUP 4 +#define MV_6180_MPP_MAX_GROUP 3 + +#define MV_DRAM_MAX_CS 4 + +/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ +#define MV_PCI_MAX_IF 0 +#define MV_PCI_START_IF 0 + +/* This define describes the maximum number of supported PEX Interfaces */ +#define MV_INCLUDE_PEX0 +#define MV_DISABLE_PEX_DEVICE_BAR +#define MV_PEX_MAX_IF 1 +#define MV_PEX_START_IF MV_PCI_MAX_IF + +/* This define describes the maximum number of supported PCI Interfaces */ +#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) + +#define MV_ETH_MAX_PORTS 2 +#define MV_6281_ETH_MAX_PORTS 2 +#define MV_6192_ETH_MAX_PORTS 2 +#define MV_6190_ETH_MAX_PORTS 1 +#define MV_6180_ETH_MAX_PORTS 1 + +#define MV_IDMA_MAX_CHAN 0 + +#define MV_USB_MAX_PORTS 1 + +#define MV_USB_VERSION 1 + + +#define MV_6281_NAND 1 +#define MV_6192_NAND 1 +#define MV_6190_NAND 1 +#define MV_6180_NAND 0 + +#define MV_6281_SDIO 1 +#define MV_6192_SDIO 1 +#define MV_6190_SDIO 1 +#define MV_6180_SDIO 1 + +#define MV_6281_TS 1 +#define MV_6192_TS 1 +#define MV_6190_TS 0 +#define MV_6180_TS 0 + +#define MV_6281_AUDIO 1 +#define MV_6192_AUDIO 1 +#define MV_6190_AUDIO 0 +#define MV_6180_AUDIO 1 + +#define MV_6281_TDM 1 +#define MV_6192_TDM 1 +#define MV_6190_TDM 0 +#define MV_6180_TDM 0 + +#define MV_DEVICE_MAX_CS 4 + +/* Others */ +#define PEX_HOST_BUS_NUM(pciIf) (pciIf) +#define PEX_HOST_DEV_NUM(pciIf) 0 + +#define PCI_IO(pciIf) (PEX0_IO) +#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) +/* CESA version #2: One channel, 2KB SRAM, TDMA */ +#if defined(MV_CESA_CHAIN_MODE_SUPPORT) + #define MV_CESA_VERSION 3 +#else +#define MV_CESA_VERSION 2 +#endif +#define MV_CESA_SRAM_SIZE 2*1024 +/* This define describes the maximum number of supported Ethernet ports */ +#define MV_ETH_VERSION 4 +#define MV_ETH_MAX_RXQ 8 +#define MV_ETH_MAX_TXQ 8 +#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } +/* This define describes the the support of USB */ +#define MV_USB_VERSION 1 + +#define MV_INCLUDE_SDRAM_CS0 +#define MV_INCLUDE_SDRAM_CS1 +#define MV_INCLUDE_SDRAM_CS2 +#define MV_INCLUDE_SDRAM_CS3 + +#define MV_INCLUDE_DEVICE_CS0 +#define MV_INCLUDE_DEVICE_CS1 +#define MV_INCLUDE_DEVICE_CS2 +#define MV_INCLUDE_DEVICE_CS3 + +#define MPP_GROUP_1_TYPE {\ + {0, 0, 0}, /* Reserved for AUTO */ \ + {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ + {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ + {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ + {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ + {0x11110000, 0x11111111, 0x0001}, /* TS */ \ + {0x33330000, 0x33333333, 0x3333} /* MII */ \ +} + +#define MPP_GROUP_2_TYPE {\ + {0, 0, 0}, /* Reserved for AUTO */ \ + {0x22220000, 0x22222222, 0x22}, /* TDM */ \ + {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ + {0, 0, 0}, /* N_A */ \ + {0, 0, 0}, /* N_A */ \ + {0x11110000, 0x11111111, 0x01} /* TS */ \ +} + +#ifndef MV_ASMLANGUAGE + +/* This enumerator defines the Marvell Units ID */ +typedef enum _mvUnitId +{ + DRAM_UNIT_ID, + PEX_UNIT_ID, + ETH_GIG_UNIT_ID, + USB_UNIT_ID, + IDMA_UNIT_ID, + XOR_UNIT_ID, + SATA_UNIT_ID, + TDM_UNIT_ID, + UART_UNIT_ID, + CESA_UNIT_ID, + SPI_UNIT_ID, + AUDIO_UNIT_ID, + SDIO_UNIT_ID, + TS_UNIT_ID, + MAX_UNITS_ID + +}MV_UNIT_ID; + +#endif + +#endif /* __INCmvCtrlEnvSpech */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c new file mode 100644 index 0000000..d21bb07 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c @@ -0,0 +1,1048 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#undef MV_DEBUG +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* typedefs */ + + +/* CPU address remap registers offsets are inconsecutive. This struct */ +/* describes address remap register offsets */ +typedef struct _ahbToMbusRemapRegOffs +{ + MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ + MV_U32 highRegOffs; /* High 32 bit remap register offset */ +}AHB_TO_MBUS_REMAP_REG_OFFS; + +/* locals */ +static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, + AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); + +/******************************************************************************* +* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK laways. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusInit(void) +{ + return MV_OK; + +} + +/******************************************************************************* +* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* This function sets +* address window, also known as address decode window. +* A new address decode window is set for specified winNum address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the winNum window, allowing CPU to access +* the winNum window. +* +* INPUT: +* winNum - Windows number. +* pAddrDecWin - CPU winNum window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU winNum window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + + /* read base register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + } + else + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read control register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + } + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + decRegs.sizeReg |= ATMWCR_WIN_ENABLE; + } + else + { + decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; + decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; + +#if !defined(MV_RUN_FROM_FLASH) + /* To be on the safe side we disable the window before writing the */ + /* new values. */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + mvAhbToMbusWinEnable(winNum,MV_FALSE); + } +#endif + + /* 3) Write to address decode Base Address Register */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); + } + + + /* Internal register space have no size */ + /* register. Do not perform size register assigment for those targets */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + /* Write to address decode Size Register */ + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window +* +* DESCRIPTION: +* Get the CPU peripheral winNum address window. +* +* INPUT: +* winNum - Peripheral winNum enumerator +* +* OUTPUT: +* pAddrDecWin - CPU winNum window information data structure. +* +* RETURN: +* MV_OK if winNum exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + + /* Internal register space size have no size register*/ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + } + else + { + decRegs.sizeReg = 0; + } + + + /* Read base and size */ + if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + } + else + { + decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); + } + + + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + { + pAddrDecWin->addrWin.size = INTER_REGS_SIZE; + pAddrDecWin->target = INTER_REGS; + pAddrDecWin->enable = MV_TRUE; + + return MV_OK; + } + + + if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + + } + + + + if (-1 == pAddrDecWin->addrWin.size) + { + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> + ATMWCR_WIN_ATTR_OFFS; + targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> + ATMWCR_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + if (INTER_REGS == target) + { + return MV_AHB_TO_MBUS_INTREG_WIN; + } + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) + { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + + } + + if (decWin.enable == MV_TRUE) + { + if (decWin.target == target) + { + return winNum; + } + + } + + } + + return 0xFFFFFFFF; + + +} + +/******************************************************************************* +* mvAhbToMbusWinAvailGet - Get First Available window number. +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 winNum; + + for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) + { + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + continue; + + if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); + return 0xffffffff; + + } + + if (decWin.enable == MV_FALSE) + { + return winNum; + } + + } + + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Peripheral winNum enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other winNum window. +* +*******************************************************************************/ +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) +{ + + /* Parameter checking */ + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + /* Internal registers bar can't be disable or enabled */ + if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) + { + return (enable ? MV_OK : MV_ERROR); + } + + if (enable == MV_TRUE) + { + /* enable the window */ + MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvAhbToMbusWinRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* After a CPU address hits one of PCI address decode windows there is an +* option to remap the address to a different one. For example, CPU +* executes a read from PCI winNum window address 0x1200.0000. This +* can be modified so the address on the PCI bus would be 0x1400.0000 +* Using the PCI address remap mechanism. +* +* INPUT: +* winNum - Peripheral winNum enumerator. Must be a PCI winNum. +* pAddrDecWin - CPU winNum window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddr; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; + + MV_U32 effectiveBaseAddress=0, + baseAddrValue=0,windowSizeValue=0; + + + /* Get registers offsets of given winNum */ + if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) + { + return 0xffffffff; + } + + /* 1) Set address remap low */ + baseAddr = pAddrWin->baseLow; + + /* Check base address aligment */ + /* + if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) + { + mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", + baseAddr); + return MV_ERROR; + } + */ + + /* BaseLow[31:16] => base register [31:16] */ + baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; + + MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); + + MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); + + + baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); + windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); + + baseAddrValue &= ATMWBR_BASE_MASK; + windowSizeValue &=ATMWCR_WIN_SIZE_MASK; + + /* Start calculating the effective Base Address */ + effectiveBaseAddress = baseAddrValue ; + + /* The effective base address will be combined from the chopped (if any) + remap value (according to the size value and remap mechanism) and the + window's base address */ + effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); + /* If the effectiveBaseAddress exceed the window boundaries return an + invalid value. */ + + if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) + { + mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); + return 0xffffffff; + } + + return effectiveBaseAddress; + + +} +/******************************************************************************* +* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets +* +* DESCRIPTION: +* +* INPUT: +* target1 - CPU Interface target 1 +* target2 - CPU Interface target 2 +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if targets are illigal, or if one of the targets is not +* associated to a valid window . +* MV_OK otherwise. +* +*******************************************************************************/ + + +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) +{ + MV_U32 winNum1,winNum2; + MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; + AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; + MV_U32 remapBaseLow1=0,remapBaseLow2=0; + MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; + + + /* Check parameters */ + if (target1 >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); + return MV_ERROR; + } + + if (target2 >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); + return MV_ERROR; + } + + + /* get window associated with this target */ + winNum1 = mvAhbToMbusWinTargetGet(target1); + + if (winNum1 == 0xffffffff) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", + target1,winNum1); + return MV_ERROR; + + } + + /* get window associated with this target */ + winNum2 = mvAhbToMbusWinTargetGet(target2); + + if (winNum2 == 0xffffffff) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", + target2,winNum2); + return MV_ERROR; + + } + + /* now Get original values of both Windows */ + if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", + winNum1); + return MV_ERROR; + + } + if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", + winNum2); + return MV_ERROR; + + } + + + /* disable both windows */ + if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", + winNum1); + return MV_ERROR; + + } + if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) + { + mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", + winNum2); + return MV_ERROR; + + } + + + /* now swap targets */ + + /* first save winDec2 values */ + winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; + winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; + winDecTemp.addrWin.size = winDec2.addrWin.size; + winDecTemp.enable = winDec2.enable; + winDecTemp.target = winDec2.target; + + /* winDec2 = winDec1 */ + winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; + winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; + winDec2.addrWin.size = winDec1.addrWin.size; + winDec2.enable = winDec1.enable; + winDec2.target = winDec1.target; + + + /* winDec1 = winDecTemp */ + winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; + winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; + winDec1.addrWin.size = winDecTemp.addrWin.size; + winDec1.enable = winDecTemp.enable; + winDec1.target = winDecTemp.target; + + + /* now set the new values */ + + + mvAhbToMbusWinSet(winNum1,&winDec1); + mvAhbToMbusWinSet(winNum2,&winDec2); + + + + + + /* now we will treat the remap windows if exist */ + + + /* now check if one or both windows has a remap window + as well after the swap ! */ + + /* if a window had a remap value differnt than the base value + before the swap , then after the swap the remap value will be + equal to the base value unless both windows has a remap windows*/ + + /* first get old values */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) + { + remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); + remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); + + } + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); + remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); + + + } + + /* now do the swap */ + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) + { + if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + /* Two windows has a remap !!! so swap */ + + MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); + MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); + + MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); + MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); + + + + } + else + { + /* remap == base */ + MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); + MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); + + } + + } + else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) + { + /* remap == base */ + MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); + MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); + + } + + + + return MV_OK; + + +} + + + +#if defined(MV_88F1181) + +/******************************************************************************* +* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. +* +* DESCRIPTION: +* This function sets CPU Mbus Arbiter +* +* INPUT: +* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At +* each clock cycle, the crossbar arbiter samples all +* requests and gives the bus to the next agent according +* to the "pizza". +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) +{ + MV_U32 sliceNum; + MV_U32 xbarCtrl = 0; + MV_MBUS_ARB_TARGET xbarTarget; + + /* 1) Set crossbar control low register */ + for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) + { + xbarTarget = pPizzaArbArray[sliceNum]; + + /* sliceNum parameter check */ + if (xbarTarget > MAX_MBUS_ARB_TARGETS) + { + mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", + xbarTarget); + return MV_ERROR; + } + xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); + } + /* Write to crossbar control low register */ + MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); + + xbarCtrl = 0; + + /* 2) Set crossbar control high register */ + for (sliceNum = MRLR_SLICE_NUM; + sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; + sliceNum++) + { + + xbarTarget = pPizzaArbArray[sliceNum]; + + /* sliceNum parameter check */ + if (xbarTarget > MAX_MBUS_ARB_TARGETS) + { + mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", + xbarTarget); + return MV_ERROR; + } + xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); + } + /* Write to crossbar control high register */ + MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvMbusArbCtrlSet - Set MBus Arbiter control register +* +* DESCRIPTION: +* +* INPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) +{ + + if (ctrl->highPrio == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); + } + + if (ctrl->fixedRoundRobin == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); + } + + if (ctrl->starvEn == MV_FALSE) + { + MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); + } + else + { + MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* mvMbusArbCtrlGet - Get MBus Arbiter control register +* +* DESCRIPTION: +* +* INPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* OUTPUT: +* ctrl - pointer to MV_MBUS_ARB_CTRL register +* +* RETURN: +* MV_ERROR if paramers to function invalid. +* +*******************************************************************************/ +MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) +{ + + MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); + + if (ctrlReg & MACR_ARB_ARM_TOP) + { + ctrl->highPrio = MV_TRUE; + } + else + { + ctrl->highPrio = MV_FALSE; + } + + if (ctrlReg & MACR_ARB_TARGET_FIXED) + { + ctrl->fixedRoundRobin = MV_TRUE; + } + else + { + ctrl->fixedRoundRobin = MV_FALSE; + } + + if (ctrlReg & MACR_ARB_REQ_CTRL_EN) + { + ctrl->starvEn = MV_TRUE; + } + else + { + ctrl->starvEn = MV_FALSE; + } + + + return MV_OK; +} + +#endif /* #if defined(MV_88F1181) */ + + + +/******************************************************************************* +* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets +* +* DESCRIPTION: +* CPU to PCI address remap registers offsets are inconsecutive. +* This function returns PCI address remap registers offsets. +* +* INPUT: +* winNum - Address decode window number. See MV_U32 enumerator. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if winNum is not a PCI one. +* +*******************************************************************************/ +static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, + AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) +{ + switch (winNum) + { + case 0: + case 1: + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + case 2: + case 3: + if((mvCtrlModelGet() == MV_5281_DEV_ID) || + (mvCtrlModelGet() == MV_1281_DEV_ID) || + (mvCtrlModelGet() == MV_6183_DEV_ID) || + (mvCtrlModelGet() == MV_6183L_DEV_ID)) + { + pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); + pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); + break; + } + else + { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", + winNum)); + return MV_NO_SUCH; + } + default: + { + pRemapRegs->lowRegOffs = 0; + pRemapRegs->highRegOffs = 0; + + DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", + winNum)); + return MV_NO_SUCH; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAhbToMbusAddDecShow(MV_VOID) +{ + MV_AHB_TO_MBUS_DEC_WIN win; + MV_U32 winNum; + mvOsOutput( "\n" ); + mvOsOutput( "AHB To MBUS Bridge:\n" ); + mvOsOutput( "-------------------\n" ); + + for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) + { + memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); + + mvOsOutput( "win%d - ", winNum ); + + if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + + } + else + mvOsOutput( "disable\n" ); + } + } + +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h new file mode 100644 index 0000000..1b352a1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h @@ -0,0 +1,130 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbush +#define __INCmvAhbToMbush + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* defines */ + +#if defined(MV_88F1181) +/* This enumerator defines the Marvell controller possible MBUS arbiter */ +/* target ports. It is used to define crossbar priority scheame (pizza) */ +typedef enum _mvMBusArbTargetId +{ + DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ + TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ + ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ + PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ + PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ + MAX_MBUS_ARB_TARGETS +}MV_MBUS_ARB_TARGET; + +typedef struct _mvMBusArbCtrl +{ + MV_BOOL starvEn; + MV_BOOL highPrio; + MV_BOOL fixedRoundRobin; + +}MV_MBUS_ARB_CTRL; + +#endif /* #if defined(MV_88F1181) */ + +typedef struct _mvAhbtoMbusDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_AHB_TO_MBUS_DEC_WIN; + +/* mvAhbToMbus.h API list */ + +MV_STATUS mvAhbToMbusInit(MV_VOID); +MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); +MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); +MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); +MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); +MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); +MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); + +#if defined(MV_88F1181) + +MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); +MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); +MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); + +#endif /* #if defined(MV_88F1181) */ + + +MV_VOID mvAhbToMbusAddDecShow(MV_VOID); + + +#endif /* __INCmvAhbToMbush */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h new file mode 100644 index 0000000..97dc631 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h @@ -0,0 +1,143 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvAhbToMbusRegsh +#define __INCmvAhbToMbusRegsh + +/******************************/ +/* ARM Address Map Registers */ +/******************************/ + +#define MAX_AHB_TO_MBUS_WINS 9 +#define MV_AHB_TO_MBUS_INTREG_WIN 8 + + +#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) +#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 + +/* Window Control Register */ +/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ +#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ + +#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated + with this window*/ +#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) + +#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes + Associated with this window */ +#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) + + +/* +Used with the Base register to set the address window size and location +Must be programed from LSB to MSB as sequence of 1’s followed +by sequence of 0’s. The number of 1’s specifies the size of the window +in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). + +NOTE: A value of 0x0 specifies 64KB size. +*/ +#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ +#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) +#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 + +/* Window Base Register */ +/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ + +/* +Used with the size field to set the address window size and location. +Corresponds to transaction address[31:16] +*/ +#define ATMWBR_BASE_OFFS 16 /* Base Address */ +#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) +#define ATMWBR_BASE_ALIGNMENT 0x10000 + +/* Window Remap Low Register */ +/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ + +/* +Used with the size field to specifies address bits[31:0] to be driven to +the target interface.: +target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) +*/ +#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ +#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) +#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 + +/* Window Remap High Register */ +/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ + +/* +Specifies address bits[63:32] to be driven to the target interface. +target_addr[63:32] = (RemapHigh[31:0] +*/ +#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ +#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) + + +#endif /* __INCmvAhbToMbusRegsh */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c new file mode 100644 index 0000000..872dc6e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c @@ -0,0 +1,1036 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvAhbToMbusRegs.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "mvSysHwConfig.h" +#include "mvSysDram.h" + +/*#define MV_DEBUG*/ +/* defines */ + +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* locals */ +/* static functions */ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +MV_TARGET * sampleAtResetTargetArray; +MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; +MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; +/******************************************************************************* +* mvCpuIfInit - Initialize Controller CPU interface +* +* DESCRIPTION: +* This function initialize Controller CPU interface: +* 1. Set CPU interface configuration registers. +* 2. Set CPU master Pizza arbiter control according to static +* configuration described in configuration file. +* 3. Opens CPU address decode windows. DRAM windows are assumed to be +* already set (auto detection). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) +{ + MV_U32 regVal; + MV_TARGET target; + MV_ADDR_WIN addrWin; + + if (cpuAddrWinMap == NULL) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); + return MV_ERROR; + } + + /*Initialize the boot target array according to device type*/ + if(mvCtrlModelGet() == MV_6180_DEV_ID) + sampleAtResetTargetArray = sampleAtResetTargetArray6180P; + else + sampleAtResetTargetArray = sampleAtResetTargetArrayP; + + /* Set ARM Configuration register */ + regVal = MV_REG_READ(CPU_CONFIG_REG); + regVal &= ~CPU_CONFIG_DEFAULT_MASK; + regVal |= CPU_CONFIG_DEFAULT; + MV_REG_WRITE(CPU_CONFIG_REG,regVal); + + /* First disable all CPU target windows */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) + { + if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) + { + continue; + } + +#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PCI(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + { + continue; + } +#endif +#if defined(MV_RUN_FROM_FLASH) + /* Don't disable the boot device. */ + if (target == DEV_BOOCS) + { + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); + } + +#if defined(MV_RUN_FROM_FLASH) + /* Resize the bootcs windows before other windows, because this */ + /* window is enabled and will cause an overlap if not resized. */ + target = DEV_BOOCS; + + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) + { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + +#endif /* MV_RUN_FROM_FLASH */ + + /* Go through all targets in user table until table terminator */ + for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) + { + +#if defined(MV_RUN_FROM_FLASH) + if (target == DEV_BOOCS) + { + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + + /* if DRAM auto sizing is used do not initialized DRAM target windows, */ + /* assuming this already has been done earlier. */ +#ifdef MV_DRAM_AUTO_SIZE + if (MV_TARGET_IS_DRAM(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PCI(target)) + { + continue; + } +#endif + +#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) + /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ + if (MV_TARGET_IS_PEX(target)) + { + continue; + } +#endif + /* If the target attribute is the same as the boot device attribute */ + /* then it's stays disable */ + if (MV_TARGET_IS_AS_BOOT(target)) + { + continue; + } + + if((0 == cpuAddrWinMap[target].addrWin.size) || + (DIS == cpuAddrWinMap[target].enable)) + + { + if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); + return MV_ERROR; + } + + } + else + { + if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) + { + DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); + return MV_ERROR; + } + + addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; + addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; + if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) + { + DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", + cpuAddrWinMap[target].winNum)); + } + + + } + } + + return MV_OK; + + +} + + +/******************************************************************************* +* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) +* address window, also known as address decode window. +* A new address decode window is set for specified target address window. +* If address decode window parameter structure enables the window, +* the routine will also enable the target window, allowing CPU to access +* the target window. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - CPU target window data structure. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if CPU target window was set correctly, MV_ERROR in case of +* address window overlapps with other active CPU target window or +* trying to assign 36bit base address while CPU does not support that. +* The function returns MV_NOT_SUPPORTED, if the target is unsupported. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_U32 existingWinNum; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); + return MV_BAD_PARAM; + } + + if (MV_TARGET_IS_DRAM(target)) + { + /* copy relevant data to MV_DRAM_DEC_WIN structure */ + addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; + addrDecWin.enable = pAddrDecWin->enable; + + + if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); + { + mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); + return MV_ERROR; + } + + } + else + { + /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ + decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; + decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; + decWin.addrWin.size = pAddrDecWin->addrWin.size; + decWin.enable = pAddrDecWin->enable; + decWin.target = target; + + existingWinNum = mvAhbToMbusWinTargetGet(target); + + /* check if there is already another Window configured + for this target */ + if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& + (existingWinNum != pAddrDecWin->winNum)) + { + /* if we want to enable the new winow number + passed by the user , then the old one should + be disabled */ + if (MV_TRUE == pAddrDecWin->enable) + { + /* be sure it is disabled */ + mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); + } + } + + if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); + return MV_ERROR; + } + + } + + return MV_OK; +} + +/******************************************************************************* +* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window +* +* DESCRIPTION: +* Get the CPU peripheral target address window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* pAddrDecWin - CPU target window information data structure. +* +* RETURN: +* MV_OK if target exist, MV_ERROR otherwise. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) +{ + + MV_U32 winNum=0xffffffff; + MV_AHB_TO_MBUS_DEC_WIN decWin; + MV_DRAM_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (MV_TARGET_IS_DRAM(target)) + { + if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", + target); + return MV_ERROR; + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; + pAddrDecWin->enable = addrDecWin.enable; + pAddrDecWin->winNum = 0xffffffff; + + } + else + { + /* get the Window number associated with this target */ + + winNum = mvAhbToMbusWinTargetGet(target); + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + return MV_NO_SUCH; + + } + + if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) + { + mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", + __FUNCTION__, winNum); + return MV_ERROR; + + } + + /* copy relevant data to MV_CPU_DEC_WIN structure */ + pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; + pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; + pAddrDecWin->addrWin.size = decWin.addrWin.size; + pAddrDecWin->enable = decWin.enable; + pAddrDecWin->winNum = winNum; + + } + + + + + return MV_OK; +} + + +/******************************************************************************* +* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window +* +* DESCRIPTION: +* This function enable/disable a CPU address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling CPU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* target - Peripheral target enumerator. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if protection window number was wrong, or the window +* overlapps other target window. +* +*******************************************************************************/ +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) +{ + MV_U32 winNum, temp; + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* get the window and check if it exist */ + temp = mvCpuIfTargetWinGet(target, &addrDecWin); + if (MV_NO_SUCH == temp) + { + return (enable? MV_ERROR: MV_OK); + } + else if( MV_OK != temp) + { + mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); + return MV_ERROR; + } + + + /* check overlap */ + + if (MV_TRUE == enable) + { + if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) + { + DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); + return MV_ERROR; + } + + } + + + if (MV_TARGET_IS_DRAM(target)) + { + if (mvDramIfWinEnable(target , enable) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); + return MV_ERROR; + + } + + } + else + { + /* get the Window number associated with this target */ + + winNum = mvAhbToMbusWinTargetGet(target); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + return (enable? MV_ERROR: MV_OK); + } + + if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) + { + mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", + winNum); + return MV_ERROR; + + } + + } + + return MV_OK; +} + + +/******************************************************************************* +* mvCpuIfTargetWinSizeGet - Get CPU target address window size +* +* DESCRIPTION: +* Get the size of CPU-to-peripheral target window. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit size. Function also returns '0' if window is closed. +* Function returns 0xFFFFFFFF in case of an error. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); + return 0; + } + + /* Get the winNum window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", + target); + return 0; + } + + /* Check if window is enabled */ + if (addrDecWin.enable == MV_TRUE) + { + return (addrDecWin.addrWin.size); + } + else + { + return 0; /* Window disabled. return 0 */ + } +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target low base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit low base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", + target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + { + return 0xffffffff; + } + return (addrDecWin.addrWin.baseLow); +} + +/******************************************************************************* +* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high +* +* DESCRIPTION: +* CPU-to-peripheral target address window base is constructed of +* two parts: Low and high. +* This function gets the CPU peripheral target high base address. +* +* INPUT: +* target - Peripheral target enumerator +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit high base address. +* +*******************************************************************************/ +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) +{ + MV_CPU_DEC_WIN addrDecWin; + + target = MV_CHANGE_BOOT_CS(target); + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + /* Get the target window */ + if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", + target); + return 0xffffffff; + } + + if (MV_FALSE == addrDecWin.enable) + { + return 0; + } + + return (addrDecWin.addrWin.baseHigh); +} + +#if defined(MV_INCLUDE_PEX) +/******************************************************************************* +* mvCpuIfPexRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pexTarget - Peripheral target enumerator. Must be a PEX target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PEX one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + + if (mvCtrlPexMaxIfGet() > 1) + { + if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) + { + mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); + return 0xffffffff; + } + + } + else + { + if (!MV_TARGET_IS_PEX0(pexTarget)) + { + mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); + return 0xffffffff; + } + + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pexTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + + } + + return mvAhbToMbusWinRemap(winNum , pAddrDecWin); +} + +#endif + +#if defined(MV_INCLUDE_PCI) +/******************************************************************************* +* mvCpuIfPciRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) +{ + MV_U32 winNum; + + /* Check parameters */ + if (!MV_TARGET_IS_PCI(pciTarget)) + { + mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); + return 0xffffffff; + } + + /* get the Window number associated with this target */ + winNum = mvAhbToMbusWinTargetGet(pciTarget); + + if (winNum >= MAX_AHB_TO_MBUS_WINS) + { + mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); + return 0xffffffff; + + } + + return mvAhbToMbusWinRemap(winNum , pAddrDecWin); +} +#endif /* MV_INCLUDE_PCI */ + + +/******************************************************************************* +* mvCpuIfPciIfRemap - Set CPU remap register for address windows. +* +* DESCRIPTION: +* +* INPUT: +* pciTarget - Peripheral target enumerator. Must be a PCI target. +* pAddrDecWin - CPU target window information data structure. +* Note that caller has to fill in the base field only. The +* size field is ignored. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if target is not a PCI one, MV_OK otherwise. +* +*******************************************************************************/ +MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) +{ +#if defined(MV_INCLUDE_PEX) + if (MV_TARGET_IS_PEX(pciIfTarget)) + { + return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); + } +#endif +#if defined(MV_INCLUDE_PCI) + + if (MV_TARGET_IS_PCI(pciIfTarget)) + { + return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); + } +#endif + return 0; +} + + + +/******************************************************************************* +* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address +* +* DESCRIPTION: +* +* INPUT: +* baseAddress - base address to be checked +* +* OUTPUT: +* None. +* +* RETURN: +* the target number that baseAddress belongs to or MAX_TARGETS is not +* found +* +*******************************************************************************/ + +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + + for( target = 0; target < MAX_TARGETS; target++ ) + { + if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) + { + if( win.enable ) + { + if ((baseAddress >= win.addrWin.baseLow) && + (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; + } + } + else return MAX_TARGETS; + + } + + return target; +} +/******************************************************************************* +* cpuTargetWinOverlap - Detect CPU address decode windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case CPU address decode +* windows overlapps. +* This function detects CPU address decode windows overlapping of a +* specified target. The function does not check the target itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* target - Peripheral target enumerator. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 targetNum; + MV_CPU_DEC_WIN addrDecWin; + MV_STATUS status; + + + for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) + { +#if defined(MV_RUN_FROM_FLASH) + if(MV_TARGET_IS_AS_BOOT(target)) + { + if (MV_CHANGE_BOOT_CS(targetNum) == target) + continue; + } +#endif /* MV_RUN_FROM_FLASH */ + + /* don't check our target or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); + if(MV_NO_SUCH == status) + { + continue; + } + if(MV_OK != status) + { + DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); + return MV_TRUE; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + DB(mvOsPrintf( + "cpuTargetWinOverlap: Required target %d overlap current %d\n", + target, targetNum)); + return MV_TRUE; + } + } + + return MV_FALSE; + +} + +/******************************************************************************* +* mvCpuIfAddDecShow - Print the CPU address decode map. +* +* DESCRIPTION: +* This function print the CPU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvCpuIfAddDecShow(MV_VOID) +{ + MV_CPU_DEC_WIN win; + MV_U32 target; + mvOsOutput( "\n" ); + mvOsOutput( "CPU Interface\n" ); + mvOsOutput( "-------------\n" ); + + for( target = 0; target < MAX_TARGETS; target++ ) + { + + memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); + + mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); + mvOsOutput( "...." ); + + if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "base %08x, ", win.addrWin.baseLow ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + + } + else + mvOsOutput( "disable\n" ); + } + else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) + { + mvOsOutput( "no such\n" ); + } + } +} + +/******************************************************************************* +* mvCpuIfEnablePex - Enable PCI Express. +* +* DESCRIPTION: +* This function Enable PCI Express. +* +* INPUT: +* pexIf - PEX interface number. +* pexType - MV_PEX_ROOT_COMPLEX - root complex device +* MV_PEX_END_POINT - end point device +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#if defined(MV_INCLUDE_PEX) +MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) +{ + /* Set pex mode incase S@R not exist */ + if( pexType == MV_PEX_END_POINT) + { + MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); + /* Change pex mode in capability reg */ + MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); + MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); + + } + else + { + MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); + } + + /* CPU config register Pex enable */ + MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); +} +#endif + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h new file mode 100644 index 0000000..224ed07 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h @@ -0,0 +1,120 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfh +#define __INCmvCpuIfh + +/* includes */ +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "ctrlEnv/sys/mvAhbToMbus.h" +#include "ddr2/mvDramIf.h" +#include "ctrlEnv/sys/mvSysDram.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif + +/* defines */ + +/* typedefs */ +/* This structure describes CPU interface address decode window */ +typedef struct _mvCpuIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_CPU_DEC_WIN; + + + +/* mvCpuIfLib.h API list */ + +/* mvCpuIfLib.h API list */ + +MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); +MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); +MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); +MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); +MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); +MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); +#if defined(MV_INCLUDE_PEX) +MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); +MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); +#endif +#if defined(MV_INCLUDE_PCI) +MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); +#endif +MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); + +MV_VOID mvCpuIfAddDecShow(MV_VOID); + +#if defined(MV88F6281) +MV_STATUS mvCpuIfBridgeReorderWAInit(void); +#endif + +#endif /* __INCmvCpuIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S new file mode 100644 index 0000000..b7efda0 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S @@ -0,0 +1,163 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvDeviceId.h" +#include "mvCtrlEnvRegs.h" +#include "mvCpuIfRegs.h" +#include "mvCtrlEnvAsm.h" + + +/******************************************************************************* +* mvCpuIfPreInit - Make early initialization of CPU interface. +* +* DESCRIPTION: +* The function will initialize the CPU interface parameters that must +* be initialize before any BUS activity towards the DDR interface, +* which means it must be executed from ROM. Because of that, the function +* is implemented in assembly code. +* The function configure the following CPU config register parameters: +* 1) CPU2MbusLTickDrv +* 2) CPU2MbusLTickSample. +* NOTE: This function must be called AFTER the internal register +* base is modified to INTER_REGS_BASE. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* r11 holds return function address. +*******************************************************************************/ +#define MV88F6281_PCKG_OPT 2 +#define MV88F6192_PCKG_OPT 1 +#define MV88F6180_PCKG_OPT 0 + + .globl _mvCpuIfPreInit +_mvCpuIfPreInit: + + mov r11, LR /* Save link register */ + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* goto calcConfigReg if device is 6281 */ + ldr r5, =MV88F6281_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* goto calcConfigReg if device is 6192/6190 */ + ldr r5, =MV88F6192_PCKG_OPT + cmp r4, r5 + beq calcConfigReg + + /* Else 6180 */ + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_CPUCLCK_MASK_6180 + and r5, r4, r5 + mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3_1 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4_1 + beq setConfigReg + b setConfigReg + +calcConfigReg: + /* Get the "sample on reset" register */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_DDRCLCK_RTIO_MASK + and r5, r4, r5 + mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 + cmp r5, #CPU_2_DDR_CLK_1x3 + beq setConfigReg + + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 + cmp r5, #CPU_2_DDR_CLK_1x4 + beq setConfigReg + + /* Else */ + ldr r4, =0 + +setConfigReg: + /* Read CPU Config register */ + MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) + ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) + and r7, r7, r5 /* Clear register fields */ + orr r7, r7, r4 /* Set the values according to the findings */ + MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) + +done: + mov PC, r11 /* r11 is saved link register */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h new file mode 100644 index 0000000..8cfeee2 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h @@ -0,0 +1,304 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvCpuIfRegsh +#define __INCmvCpuIfRegsh + +/****************************************/ +/* ARM Control and Status Registers Map */ +/****************************************/ + +#define CPU_CONFIG_REG 0x20100 +#define CPU_CTRL_STAT_REG 0x20104 +#define CPU_RSTOUTN_MASK_REG 0x20108 +#define CPU_SYS_SOFT_RST_REG 0x2010C +#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 +#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 +#define CPU_FTDLL_CONFIG_REG 0x20120 +#define CPU_L2_CONFIG_REG 0x20128 + + + +/* ARM Configuration register */ +/* CPU_CONFIG_REG (CCR) */ + + +/* Reset vector location */ +#define CCR_VEC_INIT_LOC_OFFS 1 +#define CCR_VEC_INIT_LOC_MASK BIT1 +/* reset at 0x00000000 */ +#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) +/* reset at 0xFFFF0000 */ +#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) + + +#define CCR_AHB_ERROR_PROP_OFFS 2 +#define CCR_AHB_ERROR_PROP_MASK BIT2 +/* Erros are not propogated to AHB */ +#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) +/* Erros are propogated to AHB */ +#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) + + +#define CCR_ENDIAN_INIT_OFFS 3 +#define CCR_ENDIAN_INIT_MASK BIT3 +#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) +#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) + + +#define CCR_INCR_EN_OFFS 4 +#define CCR_INCR_EN_MASK BIT4 +#define CCR_INCR_EN BIT4 + + +#define CCR_NCB_BLOCKING_OFFS 5 +#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) +#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) +#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) + +#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 +#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) +#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 +#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) +#define CCR_ICACH_PREF_BUF_ENABLE BIT16 +#define CCR_DCACH_PREF_BUF_ENABLE BIT17 + +/* Ratio options for CPU to DDR for 6281/6192/6190 */ +#define CPU_2_DDR_CLK_1x3 4 +#define CPU_2_DDR_CLK_1x4 6 + +/* Ratio options for CPU to DDR for 6281 only */ +#define CPU_2_DDR_CLK_2x9 7 +#define CPU_2_DDR_CLK_1x5 8 +#define CPU_2_DDR_CLK_1x6 9 + +/* Ratio options for CPU to DDR for 6180 only */ +#define CPU_2_DDR_CLK_1x3_1 0x5 +#define CPU_2_DDR_CLK_1x4_1 0x6 + +/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ +/* CPU to Mbus-L Tick Sample fields in CPU config register */ + +#define TICK_DRV_1x1 0 +#define TICK_DRV_1x2 0 +#define TICK_DRV_1x3 1 +#define TICK_DRV_1x4 2 +#define TICK_SMPL_1x1 0 +#define TICK_SMPL_1x2 1 +#define TICK_SMPL_1x3 0 +#define TICK_SMPL_1x4 0 + +#define CPU_2_MBUSL_DDR_CLK_1x2 \ + ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) +#define CPU_2_MBUSL_DDR_CLK_1x3 \ + ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) +#define CPU_2_MBUSL_DDR_CLK_1x4 \ + ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ + (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) + +/* ARM Control and Status register */ +/* CPU_CTRL_STAT_REG (CCSR) */ + + +/* +This is used to block PCI express\PCI from access Socrates/Feroceon GP +while ARM boot is still in progress +*/ + +#define CCSR_PCI_ACCESS_OFFS 0 +#define CCSR_PCI_ACCESS_MASK BIT0 +#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) +#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) + +#define CCSR_ARM_RESET BIT1 +#define CCSR_SELF_INT BIT2 +#define CCSR_BIG_ENDIAN BIT15 + + +/* RSTOUTn Mask Register */ +/* CPU_RSTOUTN_MASK_REG (CRMR) */ + +#define CRMR_PEX_RST_OUT_OFFS 0 +#define CRMR_PEX_RST_OUT_MASK BIT0 +#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) +#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) + +#define CRMR_WD_RST_OUT_OFFS 1 +#define CRMR_WD_RST_OUT_MASK BIT1 +#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) +#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) + +#define CRMR_SOFT_RST_OUT_OFFS 2 +#define CRMR_SOFT_RST_OUT_MASK BIT2 +#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) +#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) + +/* System Software Reset Register */ +/* CPU_SYS_SOFT_RST_REG (CSSRR) */ + +#define CSSRR_SYSTEM_SOFT_RST BIT0 + +/* AHB to Mbus Bridge Interrupt Cause Register*/ +/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ + +#define CAMCIR_ARM_SELF_INT BIT0 +#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 +#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 +#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 + + +/* AHB to Mbus Bridge Interrupt Mask Register*/ +/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ + +#define CAMCIR_ARM_SELF_INT_OFFS 0 +#define CAMCIR_ARM_SELF_INT_MASK BIT0 +#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) +#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) + + +#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 +#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 +#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) +#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) + +#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 +#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 +#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) +#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) + +#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 +#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 +#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) +#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) + +/* CPU FTDLL Config register (CFCR) fields */ +#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 +#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) +#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 +#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) +#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) +/* For Orion 2 D2 only */ +#define CFCR_MRVL_CPU_ID_OFFS 16 +#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 +#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) +#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) + +/* CPU_L2_CONFIG_REG fields */ +#ifdef MV_CPU_LE +#define CL2CR_L2_ECC_EN_OFFS 2 +#define CL2CR_L2_WT_MODE_OFFS 4 +#else +#define CL2CR_L2_ECC_EN_OFFS 26 +#define CL2CR_L2_WT_MODE_OFFS 28 +#endif + +#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) +#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) + +/*******************************************/ +/* Main Interrupt Controller Registers Map */ +/*******************************************/ + +#define CPU_MAIN_INT_CAUSE_REG 0x20200 +#define CPU_MAIN_IRQ_MASK_REG 0x20204 +#define CPU_MAIN_FIQ_MASK_REG 0x20208 +#define CPU_ENPOINT_MASK_REG 0x2020C +#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 +#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 +#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 +#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C + + +/*******************************************/ +/* ARM Doorbell Registers Map */ +/*******************************************/ + +#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 +#define CPU_HOST_TO_ARM_MASK_REG 0x20404 +#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 +#define CPU_ARM_TO_HOST_MASK_REG 0x2040C + + + +/* CPU control register map */ +/* Set bits means value is about to change according to new value */ +#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) + +#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) + +/* CPU Control and status defaults */ +#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) + + +#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) + +#endif /* __INCmvCpuIfRegsh */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c new file mode 100644 index 0000000..769475f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c @@ -0,0 +1,324 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvSysAudio.h" + +/******************************************************************************* +* mvAudioWinSet - Set AUDIO target address window +* +* DESCRIPTION: +* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) +* address window, also known as address decode window. +* After setting this target window, the AUDIO will be able to access the +* target within the address window. +* +* INPUT: +* winNum - AUDIO target address decode window number. +* pAddrDecWin - AUDIO target window data structure. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if address window overlapps with other address decode windows. +* MV_BAD_PARAM if base address is invalid parameter or target is +* unknown. +* +*******************************************************************************/ +MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttribs; + MV_DEC_REGS decRegs; + + /* Parameter checking */ + if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvAudioWinGet - Get AUDIO peripheral target address window. +* +* DESCRIPTION: +* Get AUDIO peripheral target address window. +* +* INPUT: +* winNum - AUDIO target address decode window number. +* +* OUTPUT: +* pAddrDecWin - AUDIO target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", + __FUNCTION__, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> + MV_AUDIO_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> + MV_AUDIO_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvAudioAddrDecShow - Print the AUDIO address decode map. +* +* DESCRIPTION: +* This function print the AUDIO address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvAudioAddrDecShow(MV_VOID) +{ + + MV_AUDIO_DEC_WIN win; + int i; + + if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) + return; + + + mvOsOutput( "\n" ); + mvOsOutput( "AUDIO:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvAudioWinGet( i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + + +/******************************************************************************* +* mvAudioWinInit - Initialize the integrated AUDIO target address window. +* +* DESCRIPTION: +* Initialize the AUDIO peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvAudioInit(MV_VOID) +{ + int winNum; + MV_AUDIO_DEC_WIN audioWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status; + + mvAudioHalInit(); + + /* Initiate Audio address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); + regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); + } + + for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) + { + + /* We will set the Window to DRAM_CS0 in default */ + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(SDRAM_CS0, + &cpuAddrDecWin); + + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; + audioWin.enable = MV_TRUE; + audioWin.target = SDRAM_CS0; + + if(MV_OK != mvAudioWinSet(winNum, &audioWin)) + { + return MV_ERROR; + } + } + } + + return MV_OK; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h new file mode 100644 index 0000000..f59eb9a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h @@ -0,0 +1,123 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysAudioH +#define __INCMVSysAudioH + +#include "mvCommon.h" +#include "audio/mvAudio.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +/***********************************/ +/* Audio Address Decoding registers*/ +/***********************************/ + +#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 +#define MV_AUDIO_RECORD_WIN_NUM 0 +#define MV_AUDIO_PLAYBACK_WIN_NUM 1 + +#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) +#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) + +#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) +#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) +#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) +#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) + + +/* BITs in Windows 0-3 Control and Base Registers */ +#define MV_AUDIO_WIN_ENABLE_BIT 0 +#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) +MV_TARGET tdmaAddrDecPrioTable[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + + TBL_TERM +}; + +/******************************************************************************* +* mvCesaWinGet - Get TDMA target address window. +* +* DESCRIPTION: +* Get TDMA target address window. +* +* INPUT: +* winNum - TDMA target address decode window number. +* +* OUTPUT: +* pDecWin - TDMA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) +{ + MV_DEC_WIN_PARAMS winParam; + MV_U32 sizeReg, baseReg; + + /* Parameter checking */ + if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) + { + mvOsPrintf("%s : ERR. Invalid winNum %d\n", + __FUNCTION__, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); + sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); + + /* Check if window is enabled */ + if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) + { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; + winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; + winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; + winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) + { + mvOsPrintf("Failed to translate register parameters to CESA address" \ + " decode window structure\n"); + return MV_ERROR; + } + } + else + { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case TDMA address decode +* windows overlapps. +* This function detects TDMA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE - if the given address window overlap current address +* decode map, +* MV_FALSE - otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) + { + mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) + { + mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pDecWin->target), + pDecWin->addrWin.baseLow, + pDecWin->addrWin.size); + return MV_ERROR; + } + + if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) + { + mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* set Size, Attributes and TargetID */ + sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | + ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | + ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); + + if (pDecWin->enable == MV_TRUE) + { + sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; + } + else + { + sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; + } + + /* Update Base value */ + baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); + + MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); + MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); + + return MV_OK; +} + + +static MV_STATUS mvCesaTdmaAddrDecInit (void) +{ + MV_U32 winNum; + MV_STATUS status; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_DEC_WIN cesaWin; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for(winNum=0; winNum= 2 */ + + + + +MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) +{ + MV_U32 cesaCryptEngBase; + MV_CPU_DEC_WIN addrDecWin; + + if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) + { + mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", + sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); + return MV_FAIL; + } +#if 0 + if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) + cesaCryptEngBase = addrDecWin.addrWin.baseLow; + else + { + mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); + return MV_ERROR; + } +#else + cesaCryptEngBase = (MV_U32)pSramBase; +#endif + +#if 0 /* Already done in the platform init */ +#if (MV_CESA_VERSION >= 2) + mvCesaTdmaAddrDecInit(); +#endif /* MV_CESA_VERSION >= 2 */ +#endif + return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, + osHandle); + +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h new file mode 100644 index 0000000..73bcdc5 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h @@ -0,0 +1,100 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __mvSysCesa_h__ +#define __mvSysCesa_h__ + + +#include "mvCommon.h" +#include "cesa/mvCesa.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIf.h" + +/***************************** TDMA Registers *************************************/ + +#define MV_CESA_TDMA_ADDR_DEC_WIN 4 + +#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) + +#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) + +#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 +#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) + +#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 +#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) + +#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 +#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) + +#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 +#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) + +#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 +#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) + + +MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); + +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c new file mode 100644 index 0000000..6f76c2c --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c @@ -0,0 +1,348 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ + +#include "ddr2/mvDramIf.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/sys/mvSysDram.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg=0,sizeReg=0; + MV_U32 baseToReg=0 , sizeToReg=0; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read base register*/ + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); + + /* read size register */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; + + /* Write to address decode Base Address Register */ + baseReg &= ~SCBAR_BASE_MASK; + baseReg |= baseToReg; + + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); + return MV_BAD_PARAM; + } + + /* set size */ + sizeReg &= ~SCSR_SIZE_MASK; + /* Size is located at upper 16 bits */ + sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + sizeReg |= SCSR_WIN_EN; + } + else + { + sizeReg &= ~SCSR_WIN_EN; + } + + /* 3) Write to address decode Base Address Register */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg,sizeReg; + MV_U32 sizeRegVal; + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); + + sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, + SCSR_SIZE_ALIGNMENT); + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) + { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; + + pAddrDecWin->addrWin.baseHigh = 0; + + + if (sizeReg & SCSR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", + target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", + target); + return MV_ERROR; + } + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) + { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf( + "sdramIfWinOverlap: Required target %d overlap winNum %d\n", + target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h new file mode 100644 index 0000000..7bd9c9d --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h @@ -0,0 +1,80 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __sysDram +#define __sysDram + +/* This structure describes CPU interface address decode window */ +typedef struct _mvDramIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_DRAM_DEC_WIN; + +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); + +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c new file mode 100644 index 0000000..7f6e4a5 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c @@ -0,0 +1,658 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "ctrlEnv/sys/mvSysGbe.h" + + + +typedef struct _mvEthDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_ETH_DEC_WIN; + +MV_TARGET ethAddrDecPrioTap[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_DEVICE_CS0) + DEVICE_CS0, +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEVICE_CS1, +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEVICE_CS2, +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEVICE_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_IO, +#endif + TBL_TERM +}; + +static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); +static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); +static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); + + +/******************************************************************************* +* mvEthWinInit - Initialize ETH address decode windows +* +* DESCRIPTION: +* This function initialize ETH window decode unit. It set the +* default address decode windows of the unit. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR if setting fail. +*******************************************************************************/ +/* Configure EthDrv memory map registes. */ +MV_STATUS mvEthWinInit (int port) +{ + MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; + MV_ETH_DEC_WIN ethWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + static MV_U32 accessProtReg = 0; + +#if (MV_ETH_VERSION <= 1) + static MV_BOOL isFirst = MV_TRUE; + + if(isFirst == MV_FALSE) + { + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); + return MV_OK; + } + isFirst = MV_FALSE; +#endif /* MV_GIGA_ETH_VERSION */ + + /* Initiate Ethernet address decode */ + + /* First disable all address decode windows */ + for(winNum=0; winNum= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + + decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; + decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; + /* set target ID */ + decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; + decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new + values */ + mvEthWinEnable(port, winNum, MV_FALSE); + MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); + + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvEthWinEnable(port, winNum, MV_TRUE); + } + + return MV_OK; +} + +/******************************************************************************* +* mvETHWinGet - Get dma peripheral target address window. +* +* DESCRIPTION: +* Get ETH peripheral target address window. +* +* INPUT: +* winNum - ETH to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - ETH target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); + decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; + targetAttrib.targetId = + (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvEthWinEnable - Enable/disable a ETH to target address window +* +* DESCRIPTION: +* This function enable/disable a ETH to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling ETH accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - ETH to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) +{ + MV_ETH_DEC_WIN addrDecWin; + + /* Parameter checking */ + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) + { + mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + else + { /* Overlap detected */ + mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { /* Disable address decode target window */ + MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); + } + return MV_OK; +} + +/******************************************************************************* +* mvEthWinTargetGet - Get Window number associated with target +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* window number +* +*******************************************************************************/ +MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) +{ + MV_ETH_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if (target >= MAX_TARGETS) + { + mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + for (winNum=0; winNum= mvCtrlEthMaxPortGet()) + { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); + return MV_ERROR; + } + + if (winNum >= ETH_MAX_DECODE_WIN) + { + mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) + { + mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); + return MV_ERROR; + } + /* Read current protection register */ + protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); + + /* Clear protection window field */ + protReg &= ~(ETH_PROT_WIN_MASK(winNum)); + + /* Set new protection field value */ + protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); + + /* Write protection register back */ + MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); + + return MV_OK; +} + +/******************************************************************************* +* ethWinOverlapDetect - Detect ETH address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case ETH address decode +* windows overlapps. +* This function detects ETH address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex; + MV_ETH_DEC_WIN addrDecWin; + + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); + + for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + /* Enabled CPU access to PCI-Express */ + mvCpuIfEnablePex(pexIf, pexType); + + /* Start with bars */ + /* First disable all PEX bars*/ + for (bar = 0; bar < PEX_MAX_BARS; bar++) + { + if (PEX_INTER_REGS_BAR != bar) + { + if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) + { + mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); + return MV_ERROR; + } + + } + + } + + /* and disable all PEX target windows */ + for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) + { + mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", + winNum); + return MV_ERROR; + + } + } + + /* Now, go through all bars*/ + + + +/******************************************************************************/ +/* Internal registers bar */ +/******************************************************************************/ + bar = PEX_INTER_REGS_BAR; + + /* we only open the bar , no need to open windows for this bar */ + + /* first get the CS attribute from the CPU Interface */ + if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); + return MV_ERROR; + } + + pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexBar.addrWin.size = addrDecWin.addrWin.size; + pexBar.enable = MV_TRUE; + + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + +/******************************************************************************/ +/* DRAM bar */ +/******************************************************************************/ + + bar = PEX_DRAM_BAR; + + pexBar.addrWin.size = 0; + + for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) + { + + status = mvCpuIfTargetWinGet(target,&addrDecWin); + + if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) + { + continue; + } + + /* first get attributes from CPU If */ + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); + return MV_ERROR; + } + if (addrDecWin.enable == MV_TRUE) + { + /* the base is the base of DRAM CS0 always */ + if (SDRAM_CS0 == target ) + { + pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + + } + + /* increment the bar size to be the sum of the size of all + DRAM chips selecs */ + pexBar.addrWin.size += addrDecWin.addrWin.size; + + /* set a Pex window for this target ! + DRAM CS always will have a Pex Window , and is not a + part of the priority table */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable =MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) + { + mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); + return MV_ERROR; + } + } + } + + /* check if the size of the bar is illeggal */ + if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) + { + /* try to get a good size */ + pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + } + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) + { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } + else + { + pexBar.enable = MV_TRUE; + + /* configure the bar */ + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* after the bar was configured then we enable the Pex windows*/ + for (winNum = 0;winNum < pexCurrWin ;winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) + { + mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); + return MV_ERROR; + } + + } + } + +/******************************************************************************/ +/* DEVICE bar */ +/******************************************************************************/ + +/* Open the Device BAR for non linux only */ +#ifndef MV_DISABLE_PEX_DEVICE_BAR + + /* then device bar*/ + bar = PEX_DEVICE_BAR; + + /* save the starting window */ + pexStartWindow = pexCurrWin; + pexBar.addrWin.size = 0; + pexBar.addrWin.baseLow = 0xffffffff; + pexBar.addrWin.baseHigh = 0; + maxBase = 0; + + for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) + { + status = mvCpuIfTargetWinGet(target,&addrDecWin); + + if (MV_NO_SUCH == status) + { + continue; + } + + if (MV_OK != status) + { + mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); + return MV_ERROR; + } + + if (addrDecWin.enable == MV_TRUE) + { + /* get the minimum base */ + if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) + { + pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; + } + + /* get the maximum base */ + if (addrDecWin.addrWin.baseLow > maxBase) + { + maxBase = addrDecWin.addrWin.baseLow; + sizeOfMaxBase = addrDecWin.addrWin.size; + } + + /* search in the priority table for this target */ + for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; + winIndex++) + { + if (pexDevBarPrioTable[winIndex] != target) + { + continue; + } + else if (pexDevBarPrioTable[winIndex] == target) + { + /*found it */ + + /* if the index of this target in the prio table is valid + then we set the Pex window for this target, a valid index is + an index that is lower than the number of the windows that + was not configured yet */ + + /* we subtract 2 always because the default and expantion + rom windows are always configured */ + if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) + { + /* set a Pex window for this target ! */ + pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; + pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; + pexWin.addrWin.size = addrDecWin.addrWin.size; + + /* we disable the windows at first because we are not + sure that it is witihin bar boundries */ + pexWin.enable = MV_FALSE; + pexWin.target = target; + pexWin.targetBar = bar; + + if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, + &pexWin)) + { + mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); + return MV_ERROR; + } + } + } + } + } + } + + pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; + pexBar.enable = MV_TRUE; + + /* check if the size of the bar is illegal */ + if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) + { + /* try to get a good size */ + pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + } + + /* check if the size and base are valid */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) + { + mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); + mvOsPrintf("it will be disabled\n"); + mvOsPrintf("please check Pex and CPU windows configuration\n"); + } + else + { + if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) + { + mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); + return MV_ERROR; + } + + /* now enable the windows */ + for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) + { + if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) + { + mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", + winNum); + return MV_ERROR; + } + } + } + +#endif + + return mvPexHalInit(pexIf, pexType); + +} + +/******************************************************************************* +* mvPexTargetWinSet - Set PEX to peripheral target address window BAR +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_OK if PEX BAR target window was set correctly, +* MV_BAD_PARAM on bad params +* MV_ERROR otherwise +* (e.g. address window overlapps with other active PEX target window). +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + PEX_WIN_REG_INFO winRegInfo; + MV_TARGET_ATTRIB targetAttribs; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + + if (MV_TRUE == pAddrDecWin->enable) + { + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested window overlaps with current windows */ + if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) + { + mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", + winNum); + return MV_BAD_PARAM; + } + + } + + + + /* read base register*/ + + if (winRegInfo.baseLowRegOffs) + { + decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); + } + else + { + decRegs.baseReg = 0; + } + + if (winRegInfo.sizeRegOffs) + { + decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); + } + else + { + decRegs.sizeReg =0; + } + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + /* enable\Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + decRegs.sizeReg |= PXWCR_WIN_EN; + } + else + { + decRegs.sizeReg &= ~PXWCR_WIN_EN; + } + + + /* clear bit location */ + decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; + + /* set bar Mapping */ + if (pAddrDecWin->targetBar == 1) + { + decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; + } + else if (pAddrDecWin->targetBar == 2) + { + decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; + decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~PXWCR_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; + + + /* 3) Write to address decode Base Address Register */ + + if (winRegInfo.baseLowRegOffs) + { + MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); + } + + /* write size reg */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT == winNum)|| + (MV_PEX_WIN_EXP_ROM == winNum)) + { + /* clear size because there is no size field*/ + decRegs.sizeReg &= ~PXWCR_SIZE_MASK; + + /* clear enable because there is no enable field*/ + decRegs.sizeReg &= ~PXWCR_WIN_EN; + + } + + MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); + } + + + return MV_OK; + +} + +/******************************************************************************* +* mvPexTargetWinGet - Get PEX to peripheral target address window +* +* DESCRIPTION: +* Get the PEX to peripheral target address window BAR. +* +* INPUT: +* pexIf - PEX interface number. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* pAddrBarWin - PEX target window information data structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin) +{ + MV_TARGET_ATTRIB targetAttrib; + MV_DEC_REGS decRegs; + + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + /* read base register*/ + if (winRegInfo.baseLowRegOffs) + { + decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); + } + else + { + decRegs.baseReg = 0; + } + + /* read size reg */ + if (winRegInfo.sizeRegOffs) + { + decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); + } + else + { + decRegs.sizeReg =0; + } + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + + } + + if (decRegs.sizeReg & PXWCR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + + } + + + #if 0 + if (-1 == pAddrDecWin->addrWin.size) + { + return MV_ERROR; + } + #endif + + + /* get target bar */ + if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) + { + pAddrDecWin->targetBar = 1; + } + else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == + PXWCR_WIN_BAR_MAP_BAR2 ) + { + pAddrDecWin->targetBar = 2; + } + + /* attrib and targetId */ + pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> + PXWCR_ATTRIB_OFFS; + pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> + PXWCR_TARGET_OFFS; + + targetAttrib.attrib = pAddrDecWin->attrib; + targetAttrib.targetId = pAddrDecWin->targetId; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + return MV_OK; + +} + + +/******************************************************************************* +* mvPexTargetWinEnable - Enable/disable a PEX BAR window +* +* DESCRIPTION: +* This function enable/disable a PEX BAR window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling PEX accesses for that BAR (before enabling the +* window it is tested for overlapping). Otherwise, the window will +* be disabled. +* +* INPUT: +* pexIf - PEX interface number. +* bar - BAR to be accessed by slave. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegInfo; + MV_PEX_DEC_WIN addrDecWin; + + /* Parameter checking */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); + return MV_BAD_PARAM; + } + + if (winNum >= PEX_MAX_TARGET_WIN) + { + mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); + return MV_BAD_PARAM; + + } + + + /* get the pex Window registers offsets */ + pexWinRegInfoGet(pexIf,winNum,&winRegInfo); + + + /* if the address windows is disabled , we only disable the appropriare + pex window and ignore other settings */ + + if (MV_FALSE == enable) + { + + /* this is not relevant to default and expantion rom + windows */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT != winNum)&& + (MV_PEX_WIN_EXP_ROM != winNum)) + { + MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); + } + } + + } + else + { + if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) + { + mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); + return MV_ERROR; + } + + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) + { + mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); + return MV_BAD_PARAM; + } + + if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) + { + mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", + winNum); + return MV_BAD_PARAM; + } + + + /* this is not relevant to default and expantion rom + windows */ + if (winRegInfo.sizeRegOffs) + { + if ((MV_PEX_WIN_DEFAULT != winNum)&& + (MV_PEX_WIN_EXP_ROM != winNum)) + { + MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); + } + } + + + } + + return MV_OK; + +} + + + +/******************************************************************************* +* mvPexTargetWinRemap - Set PEX to target address window remap. +* +* DESCRIPTION: +* The PEX interface supports remap of the BAR original address window. +* For each BAR it is possible to define a remap address. For example +* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified +* according to remap register but will also be targeted to the +* SDRAM CS[0]. +* +* INPUT: +* pexIf - PEX interface number. +* bar - Peripheral target enumerator accessed by slave. +* pAddrWin - Address window to be checked. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_REMAP_WIN *pAddrWin) +{ + + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", + pexIf); + return MV_BAD_PARAM; + } + if (MV_PEX_WIN_DEFAULT == winNum) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", + winNum); + return MV_BAD_PARAM; + + } + + if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) + { + mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + pexIf, + winNum, + pAddrWin->addrWin.baseLow, + pAddrWin->addrWin.size); + + return MV_ERROR; + } + + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + /* Set remap low register value */ + MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); + + /* Skip base high settings if the BAR has only base low (32-bit) */ + if (0 != winRegInfo.remapHighRegOffs) + { + MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); + } + + + if (pAddrWin->enable == MV_TRUE) + { + MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + else + { + MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPexTargetWinRemapEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, + MV_BOOL enable) +{ + PEX_WIN_REG_INFO winRegInfo; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", + pexIf); + return MV_BAD_PARAM; + } + if (MV_PEX_WIN_DEFAULT == winNum) + { + mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", + winNum); + return MV_BAD_PARAM; + + } + + + pexWinRegInfoGet(pexIf, winNum, &winRegInfo); + + if (enable == MV_TRUE) + { + MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + else + { + MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); + } + + return MV_OK; + +} + +/******************************************************************************* +* mvPexBarSet - Set PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexBarSet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin) +{ + MV_U32 regBaseLow; + MV_U32 regSize,sizeToReg; + + + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + + if (pAddrWin->addrWin.size == 0) + { + mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); + return MV_BAD_PARAM; + } + + + /* Check if the window complies with PEX spec */ + if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, + pAddrWin->addrWin.size)) + { + mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); + return MV_BAD_PARAM; + } + + /* 2) Check if the requested bar overlaps with current bars */ + if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) + { + mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); + return MV_BAD_PARAM; + } + + /* Get size register value according to window size */ + sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ + { + regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); + return MV_BAD_PARAM; + } + + regSize &= ~PXBCR_BAR_SIZE_MASK; + regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; + + MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); + + } + + /* set size */ + + + + /* Read base address low */ + regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, + PEX_MV_BAR_BASE(barNum))); + + /* clear current base */ + if (PEX_INTER_REGS_BAR == barNum) + { + regBaseLow &= ~PXBIR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); + } + else + { + regBaseLow &= ~PXBR_BASE_MASK; + regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); + } + + /* if we had a previous value that contain the bar type (MeM\IO), we want to + restore it */ + regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; + + + + /* write base low */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), + regBaseLow); + + if (pAddrWin->addrWin.baseHigh != 0) + { + /* Read base address high */ + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), + pAddrWin->addrWin.baseHigh); + + } + + /* lastly enable the Bar */ + if (pAddrWin->enable == MV_TRUE) + { + if (PEX_INTER_REGS_BAR != barNum) /* internal registers + are enabled always */ + { + MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + } + } + else if (MV_FALSE == pAddrWin->enable) + { + if (PEX_INTER_REGS_BAR != barNum) /* internal registers + are enabled always */ + { + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + } + + } + + + + return MV_OK; +} + + +/******************************************************************************* +* mvPexBarGet - Get PEX bar address and size +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPexBarGet(MV_U32 pexIf, + MV_U32 barNum, + MV_PEX_BAR *pAddrWin) +{ + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + /* read base low */ + pAddrWin->addrWin.baseLow = + MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); + + + if (PEX_INTER_REGS_BAR == barNum) + { + pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; + } + else + { + pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; + } + + + /* read base high */ + pAddrWin->addrWin.baseHigh = + MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); + + + /* Read bar size */ + if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ + { + pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); + + /* check if enable or not */ + if (pAddrWin->addrWin.size & PXBCR_BAR_EN) + { + pAddrWin->enable = MV_TRUE; + } + else + { + pAddrWin->enable = MV_FALSE; + } + + /* now get the size */ + pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; + pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; + + pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, + PXBCR_BAR_SIZE_ALIGNMENT); + + } + else /* PEX_INTER_REGS_BAR */ + { + pAddrWin->addrWin.size = INTER_REGS_SIZE; + pAddrWin->enable = MV_TRUE; + } + + + return MV_OK; +} + +/******************************************************************************* +* mvPexBarEnable - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + + +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) +{ + + MV_PEX_BAR pexBar; + + /* check parameters */ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + + if(barNum >= PEX_MAX_BARS) + { + mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); + return MV_BAD_PARAM; + } + + if (PEX_INTER_REGS_BAR == barNum) + { + if (MV_TRUE == enable) + { + return MV_OK; + } + else + { + return MV_ERROR; + } + } + + + if (MV_FALSE == enable) + { + /* disable bar and quit */ + MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); + return MV_OK; + } + + /* else */ + + if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) + { + mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); + return MV_ERROR; + + } + + if (MV_TRUE == pexBar.enable) + { + /* it is already enabled !!! */ + return MV_OK; + } + + /* else enable the bar*/ + + pexBar.enable = MV_TRUE; + + if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) + { + mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); + return MV_ERROR; + + } + + return MV_OK; +} + + +/******************************************************************************* +* pexWinOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, + MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 win; + MV_PEX_DEC_WIN addrDecWin; + + + for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) + { + /* don't check our target or illegal targets */ + if (winNum == win) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) + { + mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", + win); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", + winNum, win); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexIsWinWithinBar - Detect if address is within PEX bar boundries +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR addrDecWin; + + for(bar = 0; bar < PEX_MAX_BARS; bar++) + { + + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) + { + mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled bars */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + + if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) + { + return MV_TRUE; + } + } + + return MV_FALSE; + +} + +/******************************************************************************* +* pexBarOverlapDetect - Detect address windows overlapping +* +* DESCRIPTION: +* This function detects address window overlapping of a given address +* window in PEX BARs. +* +* INPUT: +* pAddrWin - Address window to be checked. +* bar - BAR to be accessed by slave. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, + MV_U32 barNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 bar; + MV_PEX_BAR barDecWin; + + + for(bar = 0; bar < PEX_MAX_BARS; bar++) + { + /* don't check our target or illegal targets */ + if (barNum == bar) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) + { + mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* don'nt check disabled bars */ + if (barDecWin.enable == MV_FALSE) + { + continue; + } + + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) + { + mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", + barNum, bar); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* pexBarIsValid - Check if the given address window is valid +* +* DESCRIPTION: +* PEX spec restrict BAR base to be aligned to BAR size. +* This function checks if the given address window is valid. +* +* INPUT: +* baseLow - 32bit low base address. +* size - Window size. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the address window is valid, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) +{ + + /* PCI spec restrict BAR base to be aligned to BAR size */ + if(MV_IS_NOT_ALIGN(baseLow, size)) + { + return MV_ERROR; + } + else + { + return MV_TRUE; + } + + return MV_TRUE; +} + +/******************************************************************************* +* pexBarRegInfoGet - Get BAR register information +* +* DESCRIPTION: +* PEX BARs registers offsets are inconsecutive. +* This function gets a PEX BAR register information like register offsets +* and function location of the BAR. +* +* INPUT: +* pexIf - PEX interface number. +* bar - The PEX BAR in question. +* +* OUTPUT: +* pBarRegInfo - BAR register info struct. +* +* RETURN: +* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK +* +*******************************************************************************/ +static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, + MV_U32 winNum, + PEX_WIN_REG_INFO *pWinRegInfo) +{ + + if ((winNum >= 0)&&(winNum <=3)) + { + pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); + pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); + pWinRegInfo->remapHighRegOffs = 0; + } + else if ((winNum >= 4)&&(winNum <=5)) + { + pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); + pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); + pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); + + } + else if (MV_PEX_WIN_DEFAULT == winNum) + { + pWinRegInfo->baseLowRegOffs = 0; + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); + pWinRegInfo->remapLowRegOffs = 0; + pWinRegInfo->remapHighRegOffs = 0; + } + else if (MV_PEX_WIN_EXP_ROM == winNum) + { + pWinRegInfo->baseLowRegOffs = 0; + pWinRegInfo->baseHighRegOffs = 0; + pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); + pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); + pWinRegInfo->remapHighRegOffs = 0; + + } + + return MV_OK; +} + +/******************************************************************************* +* pexBarNameGet - Get the string name of PEX BAR. +* +* DESCRIPTION: +* This function get the string name of PEX BAR. +* +* INPUT: +* bar - PEX bar number. +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string name of PEX BAR. +* +*******************************************************************************/ +const MV_8* pexBarNameGet( MV_U32 bar ) +{ + switch( bar ) + { + case PEX_INTER_REGS_BAR: + return "Internal Regs Bar0...."; + case PEX_DRAM_BAR: + return "DRAM Bar1............."; + case PEX_DEVICE_BAR: + return "Devices Bar2.........."; + default: + return "Bar unknown"; + } +} +/******************************************************************************* +* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). +* +* DESCRIPTION: +* This function print the PEX address decode map (BARs and windows). +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvPexAddrDecShow(MV_VOID) +{ + MV_PEX_BAR pexBar; + MV_PEX_DEC_WIN win; + MV_U32 pexIf; + MV_U32 bar,winNum; + + for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) + { + if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; + mvOsOutput( "\n" ); + mvOsOutput( "PEX%d:\n", pexIf ); + mvOsOutput( "-----\n" ); + + mvOsOutput( "\nPex Bars \n\n"); + + for( bar = 0; bar < PEX_MAX_BARS; bar++ ) + { + memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); + + mvOsOutput( "%s ", pexBarNameGet(bar) ); + + if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) + { + if( pexBar.enable ) + { + mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); + mvSizePrint( pexBar.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + mvOsOutput( "\nPex Decode Windows\n\n"); + + for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) + { + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "win%d - ", winNum ); + + if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) + { + if (win.enable) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + + + } + } + + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "default win - " ); + + if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) + { + mvOsOutput( "%s ", + mvCtrlTargetNameGet(win.target) ); + mvOsOutput( "\n" ); + } + memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); + + mvOsOutput( "Expansion ROM - " ); + + if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) + { + mvOsOutput( "%s ", + mvCtrlTargetNameGet(win.target) ); + mvOsOutput( "\n" ); + } + + } +} + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h new file mode 100644 index 0000000..3505613 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h @@ -0,0 +1,348 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCSysPEXH +#define __INCSysPEXH + +#include "mvCommon.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +/* 4KB granularity */ +#define MINIMUM_WINDOW_SIZE 0x1000 +#define MINIMUM_BAR_SIZE 0x1000 +#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 +#define BAR_SIZE_OFFS 12 +#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) + + + +#define MV_PEX_WIN_DEFAULT 6 +#define MV_PEX_WIN_EXP_ROM 7 +#define PEX_MAX_TARGET_WIN 8 + + +#define PEX_MAX_BARS 3 +#define PEX_INTER_REGS_BAR 0 +#define PEX_DRAM_BAR 1 +#define PEX_DEVICE_BAR 2 + +/*************************************/ +/* PCI Express BAR Control Registers */ +/*************************************/ +#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) +#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) + + +/* PCI Express BAR Control Register */ +/* PEX_BAR_CTRL_REG (PXBCR) */ + +#define PXBCR_BAR_EN BIT0 +#define PXBCR_BAR_SIZE_OFFS 16 +#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) +#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 + + + +/* PCI Express Expansion ROM BAR Control Register */ +/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ + +#define PXERBCR_EXPROM_EN BIT0 +#define PXERBCR_EXPROMSZ_OFFS 19 +#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) +#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) + +/************************************************/ +/* PCI Express Address Window Control Registers */ +/************************************************/ +#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ + (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) +#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ + (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) +#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ + (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) +#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ + (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) +#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ + (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) +#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ + (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) +#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ + (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) + +#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) +#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) +#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) + +/* PCI Express Window Control Register */ +/* PEX_WIN_CTRL_REG (PXWCR) */ + +#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ + +#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ +#define PXWCR_WIN_BAR_MAP_MASK BIT1 +#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) +#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) + +#define PXWCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) + +#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) + +#define PXWCR_SIZE_OFFS 16 /* size */ +#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) +#define PXWCR_SIZE_ALIGNMENT 0x10000 + +/* PCI Express Window Base Register */ +/* PEX_WIN_BASE_REG (PXWBR)*/ + +#define PXWBR_BASE_OFFS 16 /* address[31:16] */ +#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) +#define PXWBR_BASE_ALIGNMENT 0x10000 + +/* PCI Express Window Remap Register */ +/* PEX_WIN_REMAP_REG (PXWRR)*/ + +#define PXWRR_REMAP_EN BIT0 +#define PXWRR_REMAP_OFFS 16 +#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) +#define PXWRR_REMAP_ALIGNMENT 0x10000 + +/* PCI Express Window Remap (High) Register */ +/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ + +#define PXWRHR_REMAP_HIGH_OFFS 0 +#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) + +/* PCI Express Default Window Control Register */ +/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ + +#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) +#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Control Register */ +/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ + +#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ +#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) +#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ +#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) + +/* PCI Express Expansion ROM Window Remap Register */ +/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ + +#define PXWERRR_REMAP_EN BIT0 +#define PXWERRR_REMAP_OFFS 16 +#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) +#define PXWERRR_REMAP_ALIGNMENT 0x10000 + + + +/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ +/* PCI Express BAR0 Internal Register*/ +/*PEX BAR0_INTER_REG (PXBIR)*/ + +#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) +#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) + +#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ +#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) +#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) + + +/* PCI Express BAR0 Internal (High) Register*/ +/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ + +#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ +#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) + + +#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ +#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB +#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB +#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB + + +/* PCI Express BAR1 Register */ +/* PCI Express BAR2 Register*/ +/*PEX BAR1_REG (PXBR)*/ +/*PEX BAR2_REG (PXBR)*/ + +#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) +#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) +#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) + +#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ + +#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ +#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) +#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) + + +/* PCI Express BAR1 (High) Register*/ +/* PCI Express BAR2 (High) Register*/ +/*PEX BAR1_REG_HIGH (PXBRH)*/ +/*PEX BAR2_REG_HIGH (PXBRH)*/ + +#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ +#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) + +/* PCI Express Expansion ROM BAR Register*/ +/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ + +#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ + +#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) + +#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) + +#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) + +#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ +#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) + +/* PEX Bar attributes */ +typedef struct _mvPexBar +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_BAR; + +/* PEX Remap Window attributes */ +typedef struct _mvPexRemapWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_REMAP_WIN; + +/* PEX Remap Window attributes */ +typedef struct _mvPexDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_U32 targetBar; + MV_U8 attrib; /* chip select attributes */ + MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_PEX_DEC_WIN; + +/* Global Functions prototypes */ +/* mvPexHalInit - Initialize PEX interfaces*/ +MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); + + +/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ +MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin); + +/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ +MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_DEC_WIN *pAddrDecWin); + +/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ +MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); + +/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ +MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, + MV_PEX_REMAP_WIN *pAddrWin); + +/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ +MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, + MV_BOOL enable); + +/* mvPexBarSet - Set PEX bar address and size */ +MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); + +/* mvPexBarGet - Get PEX bar address and size */ +MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); + +/* mvPexBarEnable - enable\disable a PEX bar*/ +MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); + +/* mvPexAddrDecShow - Display address decode windows attributes */ +MV_VOID mvPexAddrDecShow(MV_VOID); + +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c new file mode 100644 index 0000000..f100a12 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c @@ -0,0 +1,430 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "mvTypes.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "cpu/mvCpu.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "sata/CoreDriver/mvRegs.h" +#include "ctrlEnv/sys/mvSysSata.h" + +MV_TARGET sataAddrDecPrioTab[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + TBL_TERM +}; + + +/******************************************************************************* +* sataWinOverlapDetect - Detect SATA address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case SATA address decode +* windows overlapps. +* This function detects SATA address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_SATA_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvSataWinGet - Get SATA peripheral target address window. +* +* DESCRIPTION: +* Get SATA peripheral target address window. +* +* INPUT: +* winNum - SATA target address decode window number. +* +* OUTPUT: +* pAddrDecWin - SATA target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> + MV_SATA_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> + MV_SATA_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvSataAddrDecShow - Print the SATA address decode map. +* +* DESCRIPTION: +* This function print the SATA address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSataAddrDecShow(MV_VOID) +{ + + MV_SATA_DEC_WIN win; + int i,j; + + + + for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) + { + if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) + return; + + mvOsOutput( "\n" ); + mvOsOutput( "SATA %d:\n", j ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvSataWinGet(j, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } + } +} + + +/******************************************************************************* +* mvSataWinInit - Initialize the integrated SATA target address window. +* +* DESCRIPTION: +* Initialize the SATA peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSataWinInit(MV_VOID) +{ + int winNum; + MV_SATA_DEC_WIN sataWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status, winPrioIndex = 0; + + /* Initiate Sata address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); + regVal &= ~MV_SATA_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); + } + + winNum = 0; + while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; + sataWin.enable = MV_TRUE; + sataWin.target = sataAddrDecPrioTab[winPrioIndex]; + + if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h new file mode 100644 index 0000000..325fb8d --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h @@ -0,0 +1,128 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysSataAddrDech +#define __INCMVSysSataAddrDech + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _mvSataDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_SATA_DEC_WIN; + + +#define MV_SATA_MAX_ADDR_DECODE_WIN 4 + +#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) +#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) + +/* BITs in Bridge Interrupt Cause and Mask registers */ +#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 +#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = 0; + decRegs.sizeReg = 0; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; + decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); + + /* set target ID */ + decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; + decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); + + if (pAddrDecWin->enable == MV_TRUE) + { + decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; + } + else + { + decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; + } + + MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); + MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvSdmmcWinGet - Get SDMMC peripheral target address window. +* +* DESCRIPTION: +* Get SDMMC peripheral target address window. +* +* INPUT: +* winNum - SDMMC target address decode window number. +*d +* OUTPUT: +* pAddrDecWin - SDMMC target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); + decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) + { + mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> + MV_SDMMC_WIN_ATTR_OFFSET; + targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> + MV_SDMMC_WIN_TARGET_OFFSET; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + return MV_OK; +} +/******************************************************************************* +* mvSdmmcAddrDecShow - Print the SDMMC address decode map. +* +* DESCRIPTION: +* This function print the SDMMC address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvSdmmcAddrDecShow(MV_VOID) +{ + + MV_SDMMC_DEC_WIN win; + int i,j=0; + + + + if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) + return; + + mvOsOutput( "\n" ); + mvOsOutput( "SDMMC %d:\n", j ); + mvOsOutput( "----\n" ); + + for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + mvOsOutput( "...." ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + + +/******************************************************************************* +* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. +* +* DESCRIPTION: +* Initialize the SDMMC peripheral target address window. +* +* INPUT: +* +* +* OUTPUT: +* +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvSdmmcWinInit(MV_VOID) +{ + int winNum; + MV_SDMMC_DEC_WIN sdmmcWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + MV_U32 status, winPrioIndex = 0; + + /* Initiate Sdmmc address decode */ + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); + regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; + MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); + } + + winNum = 0; + while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; + sdmmcWin.enable = MV_TRUE; + sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; + + if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h new file mode 100644 index 0000000..4c50a2b --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h @@ -0,0 +1,125 @@ + +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCMVSysSdmmcAddrDech +#define __INCMVSysSdmmcAddrDech + +#include "mvCommon.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/sys/mvCpuIf.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _mvSdmmcDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +} MV_SDMMC_DEC_WIN; + + +#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 + +#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) +#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) + + +/* BITs in Windows 0-3 Control and Base Registers */ +#define MV_SDMMC_WIN_ENABLE_BIT 0 +#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); + decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; + + if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); + + /* for the safe side we disable the window before writing the new + values */ + mvTdmWinEnable(winNum, MV_FALSE); + + ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); + ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); + ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); + + /* Write to address base and control registers */ + MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); + MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); + /* Enable address decode target window */ + if (pAddrDecWin->enable == MV_TRUE) + { + mvTdmWinEnable(winNum, MV_TRUE); + } + return MV_OK; +} + +/******************************************************************************* +* mvTdmWinGet - Get peripheral target address window. +* +* DESCRIPTION: +* Get TDM peripheral target address window. +* +* INPUT: +* winNum - TDM to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - TDM target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ + +MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) +{ + + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if (winNum >= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); + decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; + + if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; + targetAttrib.targetId = + (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvTdmWinEnable - Enable/disable a TDM to target address window +* +* DESCRIPTION: +* This function enable/disable a TDM to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling TDM accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - TDM to target address decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) +{ + MV_TDM_DEC_WIN addrDecWin; + + if (MV_TRUE == enable) + { + if (winNum >= TDM_MBUS_MAX_WIN) + { + mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + /* First check for overlap with other enabled windows */ + /* Get current window */ + if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) + { + mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); + } + else + { /* Overlap detected */ + mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { + MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); + } + return MV_OK; +} + + +/******************************************************************************* +* tdmWinOverlapDetect - Detect TDM address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case TDM address decode +* windows overlapps. +* This function detects TDM address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_TDM_DEC_WIN addrDecWin; + + for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + /* Do not check disabled windows */ + if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) + { + /* Get window parameters */ + if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + } + return MV_FALSE; +} + +/******************************************************************************* +* mvTdmAddrDecShow - Print the TDM address decode map. +* +* DESCRIPTION: +* This function print the TDM address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvTdmAddrDecShow(MV_VOID) +{ + MV_TDM_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "TDM:\n" ); + mvOsOutput( "----\n" ); + + for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if (mvTdmWinGet(i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %08x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); + mvOsOutput( "...." ); + mvSizePrint( win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h new file mode 100644 index 0000000..0d3140f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h @@ -0,0 +1,106 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSysTdmh +#define __INCmvSysTdmh + +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +typedef struct _mvTdmDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +} MV_TDM_DEC_WIN; + +MV_STATUS mvTdmWinInit(MV_VOID); +MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); +MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); +MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); +MV_VOID mvTdmAddrDecShow(MV_VOID); + + +#define TDM_MBUS_MAX_WIN 4 +#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) +#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) + +/* TDM_WIN_CTRL_REG bits */ +#define TDM_WIN_ENABLE_OFFS 0 +#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) + { + mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " + "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, mvCtrlTargetNameGet(pAddrDecWin->target), + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); + + if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) + { + mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); + return MV_ERROR; + } + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; + decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; + /* set target ID */ + decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; + decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; + + /* for the safe side we disable the window before writing the new */ + /* values */ + mvTsuWinEnable(winNum, MV_FALSE); + MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); + + /* Enable address decode target window */ + if(pAddrDecWin->enable == MV_TRUE) + { + mvTsuWinEnable(winNum,MV_TRUE); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuWinGet +* +* DESCRIPTION: +* Get TSU peripheral target address window. +* +* INPUT: +* winNum - TSU to target address decode window number. +* +* OUTPUT: +* pAddrDecWin - TSU target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS decRegs; + MV_TARGET_ATTRIB targetAttrib; + + /* Parameter checking */ + if(winNum >= TSU_MAX_DECODE_WIN) + { + mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); + return MV_NOT_SUPPORTED; + } + + decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); + decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); + + if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) + { + mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; + targetAttrib.targetId = + (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + /* Check if window is enabled */ + if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} + + +/******************************************************************************* +* mvTsuWinEnable +* +* DESCRIPTION: +* This function enable/disable a TSU to target address window. +* According to parameter 'enable' the routine will enable the +* window, thus enabling TSU accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - TSU to target address decode window number. +* enable - Enable / disable parameter. +* +* OUTPUT: +* N/A +* +* RETURN: +* MV_ERROR if decode window number was wrong or enabled window overlapps. +* +*******************************************************************************/ +MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) +{ + MV_TSU_DEC_WIN addrDecWin; + + /* Parameter checking */ + if(winNum >= TSU_MAX_DECODE_WIN) + { + mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); + return MV_ERROR; + } + + if(enable == MV_TRUE) + { + /* First check for overlap with other enabled windows */ + /* Get current window. */ + if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) + { + mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); + return MV_ERROR; + } + /* Check for overlapping. */ + if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode target window */ + MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), + TSU_WIN_CTRL_EN_MASK); + } + else + { + /* Overlap detected */ + mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); + return MV_ERROR; + } + } + else + { + /* Disable address decode target window */ + MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), + TSU_WIN_CTRL_EN_MASK); + } + return MV_OK; +} + +/******************************************************************************* +* mvTsuWinTargetGet +* +* DESCRIPTION: +* Get Window number associated with target +* +* INPUT: +* target - Target ID to get the window number for. +* OUTPUT: +* +* RETURN: +* window number or 0xFFFFFFFF on error. +* +*******************************************************************************/ +MV_U32 mvTsuWinTargetGet(MV_TARGET target) +{ + MV_TSU_DEC_WIN decWin; + MV_U32 winNum; + + /* Check parameters */ + if(target >= MAX_TARGETS) + { + mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); + return 0xffffffff; + } + + for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) + { + if(mvTsuWinGet(winNum,&decWin) != MV_OK) + { + mvOsPrintf("mvTsuWinGet: window returned error\n"); + return 0xffffffff; + } + + if (decWin.enable == MV_TRUE) + { + if(decWin.target == target) + { + return winNum; + } + } + } + return 0xFFFFFFFF; +} + + +/******************************************************************************* +* tsuWinOverlapDetect +* +* DESCRIPTION: +* Detect TSU address windows overlapping +* An unpredicted behaviur is expected in case TSU address decode +* windows overlapps. +* This function detects TSU address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 ctrlReg; + MV_U32 winNumIndex; + MV_TSU_DEC_WIN addrDecWin; + + for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) + { + /* Do not check window itself */ + if(winNumIndex == winNum) + { + continue; + } + + /* Do not check disabled windows */ + ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); + if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) + { + mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + return MV_FALSE; +} + + +/******************************************************************************* +* mvTsuAddrDecShow +* +* DESCRIPTION: +* Print the TSU address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvTsuAddrDecShow(void) +{ + MV_TSU_DEC_WIN win; + int i; + + if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) + return; + + mvOsOutput( "\n" ); + mvOsOutput( "TSU:\n"); + mvOsOutput( "----\n" ); + + for(i = 0; i < TSU_MAX_DECODE_WIN; i++) + { + memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); + mvOsOutput( "win%d - ", i ); + + if(mvTsuWinGet(i, &win ) == MV_OK ) + { + if(win.enable == MV_TRUE) + { + mvOsOutput("%s base %08x, ", + mvCtrlTargetNameGet(win.target), + win.addrWin.baseLow); + mvOsOutput( "...." ); + mvSizePrint(win.addrWin.size ); + mvOsOutput( "\n" ); + } + else + { + mvOsOutput( "disable\n" ); + } + } + } + return; +} + + +/******************************************************************************* +* mvTsuInit +* +* DESCRIPTION: +* Initialize the TSU unit, and get unit out of reset. +* +* INPUT: +* coreClock - The core clock at which the TSU should operate. +* mode - The mode on configure the unit into (serial/parallel). +* memHandle - Memory handle used for memory allocations. +* OUTPUT: +* None. +* RETURN: +* MV_OK - on success, +* +*******************************************************************************/ +MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, + void *osHandle) +{ + MV_STATUS status; + + status = mvTsuWinInit(); + if(status == MV_OK) + status = mvTsuHalInit(coreClock,mode,osHandle); + + return status; +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h new file mode 100644 index 0000000..4282589 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h @@ -0,0 +1,110 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSysTsh +#define __INCmvSysTsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "ts/mvTsu.h" +#include "ctrlEnv/sys/mvCpuIf.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define TSU_MAX_DECODE_WIN 4 + + +/*******************************************/ +/* TSU Windows Registers */ +/*******************************************/ +#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) +#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) + +/* TSU windows control register. */ +#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) +#define TSU_WIN_CTRL_TARGET_OFFS 4 +#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) +#define TSU_WIN_CTRL_ATTR_OFFS 8 +#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) +#define TSU_WIN_CTRL_SIZE_OFFS 16 +#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) + +/* TSU windows base register. */ +#define TSU_WIN_BASE_OFFS 16 +#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) + +MV_STATUS mvTsuWinInit(void); + +void mvTsuAddrDecShow(void); +MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, + void *osHandle); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvTsh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c new file mode 100644 index 0000000..195b5e1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c @@ -0,0 +1,497 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ctrlEnv/sys/mvSysUsb.h" + +MV_TARGET usbAddrDecPrioTab[] = +{ +#if defined(MV_INCLUDE_SDRAM_CS0) + SDRAM_CS0, +#endif +#if defined(MV_INCLUDE_SDRAM_CS1) + SDRAM_CS1, +#endif +#if defined(MV_INCLUDE_SDRAM_CS2) + SDRAM_CS2, +#endif +#if defined(MV_INCLUDE_SDRAM_CS3) + SDRAM_CS3, +#endif +#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) + CRYPT_ENG, +#endif +#if defined(MV_INCLUDE_PEX) + PEX0_MEM, +#endif + TBL_TERM +}; + + + +MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) +{ + MV_STATUS status; + + status = mvUsbWinInit(dev); + if(status != MV_OK) + return status; + + return mvUsbHalInit(dev, isHost); +} + + +/******************************************************************************* +* usbWinOverlapDetect - Detect USB address windows overlapping +* +* DESCRIPTION: +* An unpredicted behaviur is expected in case USB address decode +* windows overlapps. +* This function detects USB address decode windows overlapping of a +* specified window. The function does not check the window itself for +* overlapping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, + MV_ADDR_WIN *pAddrWin) +{ + MV_U32 winNumIndex; + MV_DEC_WIN addrDecWin; + + for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlapps with current windows */ + if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); + return MV_ERROR; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) + { + mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ + "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", + winNum, + mvCtrlTargetNameGet(pDecWin->target), + pDecWin->addrWin.baseLow, + pDecWin->addrWin.size); + return MV_ERROR; + } + + if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) + { + mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* set Size, Attributes and TargetID */ + sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | + ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | + ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); + +#if defined(MV645xx) || defined(MV646xx) + /* If window is DRAM with HW cache coherency, make sure bit2 is set */ + sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; + + if((MV_TARGET_IS_DRAM(pDecWin->target)) && + (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) + { + sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; + } + else + { + sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; + } +#endif /* MV645xx || MV646xx */ + + if (pDecWin->enable == MV_TRUE) + { + sizeReg |= MV_USB_WIN_ENABLE_MASK; + } + else + { + sizeReg &= ~MV_USB_WIN_ENABLE_MASK; + } + + /* Update Base value */ + baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); + + MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); + MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); + + return MV_OK; +} + +/******************************************************************************* +* mvUsbWinGet - Get USB peripheral target address window. +* +* DESCRIPTION: +* Get USB peripheral target address window. +* +* INPUT: +* winNum - USB target address decode window number. +* +* OUTPUT: +* pDecWin - USB target window data structure. +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) +{ + MV_DEC_WIN_PARAMS winParam; + MV_U32 sizeReg, baseReg; + + /* Parameter checking */ + if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) + { + mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", + __FUNCTION__, dev, winNum); + return MV_NOT_SUPPORTED; + } + + baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); + sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); + + /* Check if window is enabled */ + if(sizeReg & MV_USB_WIN_ENABLE_MASK) + { + pDecWin->enable = MV_TRUE; + + /* Extract window parameters from registers */ + winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; + winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; + winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; + winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); + + /* Translate the decode window parameters to address decode struct */ + if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) + { + mvOsPrintf("Failed to translate register parameters to USB address" \ + " decode window structure\n"); + return MV_ERROR; + } + } + else + { + pDecWin->enable = MV_FALSE; + } + return MV_OK; +} + +/******************************************************************************* +* mvUsbWinInit - +* +* INPUT: +* +* OUTPUT: +* +* RETURN: +* MV_ERROR if register parameters are invalid. +* +*******************************************************************************/ +MV_STATUS mvUsbWinInit(int dev) +{ + MV_STATUS status; + MV_DEC_WIN usbWin; + MV_CPU_DEC_WIN cpuAddrDecWin; + int winNum; + MV_U32 winPrioIndex = 0; + + /* First disable all address decode windows */ + for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) + { + MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); + } + + /* Go through all windows in user table until table terminator */ + winNum = 0; + while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && + (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) + { + /* first get attributes from CPU If */ + status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], + &cpuAddrDecWin); + + if(MV_NO_SUCH == status) + { + winPrioIndex++; + continue; + } + if (MV_OK != status) + { + mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); + return MV_ERROR; + } + + if (cpuAddrDecWin.enable == MV_TRUE) + { + usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; + usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; + usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; + usbWin.enable = MV_TRUE; + usbWin.target = usbAddrDecPrioTab[winPrioIndex]; + +#if defined(MV645xx) || defined(MV646xx) + /* Get the default attributes for that target window */ + mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); +#endif /* MV645xx || MV646xx */ + + if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) + { + return MV_ERROR; + } + winNum++; + } + winPrioIndex++; + } + return MV_OK; +} + +/******************************************************************************* +* mvUsbAddrDecShow - Print the USB address decode map. +* +* DESCRIPTION: +* This function print the USB address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvUsbAddrDecShow(MV_VOID) +{ + MV_DEC_WIN addrDecWin; + int i, winNum; + + mvOsOutput( "\n" ); + mvOsOutput( "USB:\n" ); + mvOsOutput( "----\n" ); + + for(i=0; i= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + if (pAddrDecWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + /* Check if the requested window overlaps with current windows */ + if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) + { + DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); + return MV_ERROR; + } + + xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); + xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); + + /* Get Base Address and size registers values */ + if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) + { + DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); + return MV_BAD_PARAM; + } + + + mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); + + /* set attributes */ + xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; + xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; + /* set target ID */ + xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; + xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; + + + /* Write to address decode Base Address Register */ + MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); + + /* Write to Size Register */ + MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + if (pAddrDecWin->enable) + { + MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + else + { + MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + } + return MV_OK; +} + +/******************************************************************************* +* mvXorTargetWinGet - Get xor peripheral target address window. +* +* DESCRIPTION: +* Get xor peripheral target address window. +* +* INPUT: +* winNum - One of the possible XOR memory decode windows. +* +* OUTPUT: +* base - Window base address. +* size - Window size. +* enable - window enable/disable. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) +{ + MV_DEC_REGS xorDecRegs; + MV_TARGET_ATTRIB targetAttrib; + MV_U32 chan=0,chanWinEn; + + /* Parameter checking */ + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); + return MV_ERROR; + } + + if (NULL == pAddrDecWin) + { + DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ + { + /* Check if enable bit is equal for all channels */ + if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & + XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) + { + mvOsPrintf("%s: ERR. Window enable field must be equal in " + "all channels(chan=%d)\n",__FUNCTION__, chan); + return MV_ERROR; + } + } + + + + xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); + xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); + + if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) + { + mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); + return MV_ERROR; + } + + /* attrib and targetId */ + targetAttrib.attrib = + (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; + targetAttrib.targetId = + (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; + + + pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); + + if(chanWinEn) + { + pAddrDecWin->enable = MV_TRUE; + } + else pAddrDecWin->enable = MV_FALSE; + + return MV_OK; +} + +/******************************************************************************* +* mvXorTargetWinEnable - Enable/disable a Xor address decode window +* +* DESCRIPTION: +* This function enable/disable a XOR address decode window. +* if parameter 'enable' == MV_TRUE the routine will enable the +* window, thus enabling XOR accesses (before enabling the window it is +* tested for overlapping). Otherwise, the window will be disabled. +* +* INPUT: +* winNum - Decode window number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) +{ + MV_XOR_DEC_WIN addrDecWin; + MV_U32 chan; + + /* Parameter checking */ + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { + /* Get current window */ + if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); + return MV_ERROR; + } + + /* Check for overlapping */ + if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) + { + /* Overlap detected */ + DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); + return MV_ERROR; + } + + /* No Overlap. Enable address decode target window */ + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + + } + else + { + /* Disable address decode target window */ + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), + XEXWCR_WIN_EN_MASK(winNum)); + } + + } + + return MV_OK; +} + +/******************************************************************************* +* mvXorSetProtWinSet - Configure access attributes of a XOR engine +* to one of the XOR memory windows. +* +* DESCRIPTION: +* Each engine can be configured with access attributes for each of the +* memory spaces. This function sets access attributes +* to a given window for the given engine +* +* INPUTS: +* chan - One of the possible engines. +* winNum - One of the possible XOR memory spaces. +* access - Protection access rights. +* write - Write rights. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, + MV_BOOL write) +{ + MV_U32 temp; + + /* Parameter checking */ + if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) + { + DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); + return MV_BAD_PARAM; + } + if (winNum >= XOR_MAX_ADDR_DEC_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & + (~XEXWCR_WIN_ACC_MASK(winNum)); + + /* if access is disable */ + if (!access) + { + /* disable access */ + temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); + } + /* if access is enable */ + else + { + /* if write is enable */ + if (write) + { + /* enable write */ + temp |= XEXWCR_WIN_ACC_RW(winNum); + } + /* if write is disable */ + else + { + /* disable write */ + temp |= XEXWCR_WIN_ACC_RO(winNum); + } + } + MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); + return MV_OK; +} + +/******************************************************************************* +* mvXorPciRemap - Set XOR remap register for PCI address windows. +* +* DESCRIPTION: +* only Windows 0-3 can be remapped. +* +* INPUT: +* winNum - window number +* pAddrDecWin - pointer to address space window structure +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) +{ + /* Parameter checking */ + if (winNum >= XOR_MAX_REMAP_WIN) + { + DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); + return MV_BAD_PARAM; + } + + MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); + + return MV_OK; +} + +/******************************************************************************* +* xorWinOverlapDetect - Detect XOR address windows overlaping +* +* DESCRIPTION: +* An unpredicted behaviour is expected in case XOR address decode +* windows overlaps. +* This function detects XOR address decode windows overlaping of a +* specified window. The function does not check the window itself for +* overlaping. The function also skipps disabled address decode windows. +* +* INPUT: +* winNum - address decode window number. +* pAddrDecWin - An address decode window struct. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlap current address +* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data +* from registers. +* +*******************************************************************************/ +static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) +{ + MV_U32 baseAddrEnableReg; + MV_U32 winNumIndex,chan; + MV_XOR_DEC_WIN addrDecWin; + + if (pAddrWin == NULL) + { + DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); + return MV_BAD_PTR; + } + + for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) + { + /* Read base address enable register. Do not check disabled windows */ + baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); + + for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) + { + /* Do not check window itself */ + if (winNumIndex == winNum) + { + continue; + } + + /* Do not check disabled windows */ + if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) + { + DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); + return MV_ERROR; + } + + if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) + { + return MV_TRUE; + } + } + } + + return MV_FALSE; +} + +static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) +{ + MV_XOR_DEC_WIN win; + int i; + + mvOsOutput( "\n" ); + mvOsOutput( "XOR %d:\n", unit ); + mvOsOutput( "----\n" ); + + for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) + { + memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); + + mvOsOutput( "win%d - ", i ); + + if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) + { + if( win.enable ) + { + mvOsOutput( "%s base %x, ", + mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); + + mvSizePrint( win.addrWin.size ); + + mvOsOutput( "\n" ); + } + else + mvOsOutput( "disable\n" ); + } + } +} + +/******************************************************************************* +* mvXorAddrDecShow - Print the XOR address decode map. +* +* DESCRIPTION: +* This function print the XOR address decode map. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID mvXorAddrDecShow(MV_VOID) +{ + int i; + + for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) + mvXorAddrDecShowUnit(i); + +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h new file mode 100644 index 0000000..73b2d9e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h @@ -0,0 +1,140 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCMVSysXorh +#define __INCMVSysXorh + + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ctrlEnv/sys/mvCpuIf.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ +#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ + +/* XOR Engine Address Decoding Register Map */ +#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) +#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) +#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) +#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) + +/* XOR Engine [0..1] Window Control Registers (XExWCR) */ +#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) +#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) +#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) +#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) + +#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) +#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) +#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) + +/* XOR Engine Base Address Registers (XEBARx) */ +#define XEBARX_TARGET_OFFS (0) +#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) +#define XEBARX_ATTR_OFFS (8) +#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) +#define XEBARX_BASE_OFFS (16) +#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) + +/* XOR Engine Size Mask Registers (XESMRx) */ +#define XESMRX_SIZE_MASK_OFFS (16) +#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) + +/* XOR Engine High Address Remap Register (XEHARRx1) */ +#define XEHARRX_REMAP_OFFS (0) +#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) + +typedef struct _mvXorDecWin +{ + MV_TARGET target; + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ + +}MV_XOR_DEC_WIN; + +MV_STATUS mvXorInit (MV_VOID); +MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, + MV_XOR_DEC_WIN *pAddrDecWin); +MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, + MV_XOR_DEC_WIN *pAddrDecWin); +MV_STATUS mvXorTargetWinEnable(MV_U32 unit, + MV_U32 winNum, MV_BOOL enable); +MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, + MV_BOOL write); +MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); + +MV_VOID mvXorAddrDecShow(MV_VOID); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c new file mode 100644 index 0000000..80325fc --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c @@ -0,0 +1,75 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "device/mvDevice.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h new file mode 100644 index 0000000..9350779 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h @@ -0,0 +1,74 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceH +#define __INCmvDeviceH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "device/mvDeviceRegs.h" + + +#endif /* #ifndef __INCmvDeviceH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h new file mode 100644 index 0000000..80778ad --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h @@ -0,0 +1,101 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDeviceRegsH +#define __INCmvDeviceRegsH + +#ifndef MV_ASMLANGUAGE +#include "ctrlEnv/mvCtrlEnvLib.h" +/* This enumerator describes the Marvell controller possible devices that */ +/* can be connected to its device interface. */ +typedef enum _mvDevice +{ +#if defined(MV_INCLUDE_DEVICE_CS0) + DEV_CS0 = 0, /* Device connected to dev CS[0] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS1) + DEV_CS1 = 1, /* Device connected to dev CS[1] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS2) + DEV_CS2 = 2, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS3) + DEV_CS3 = 3, /* Device connected to dev CS[2] */ +#endif +#if defined(MV_INCLUDE_DEVICE_CS4) + DEV_CS4 = 4, /* Device connected to BOOT dev */ +#endif + MV_DEV_MAX_CS = MV_DEVICE_MAX_CS +}MV_DEVICE; + + +#endif /* MV_ASMLANGUAGE */ + + +#define NAND_CTRL_REG 0x10470 + +#define NAND_ACTCEBOOT_BIT BIT1 + + +#endif /* #ifndef __INCmvDeviceRegsH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt new file mode 100644 index 0000000..4053116 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.5 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c new file mode 100644 index 0000000..75f7e88 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c @@ -0,0 +1,211 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ +/******************************************************************************* +* mvOsCpuArchLib.c - Marvell CPU architecture library +* +* DESCRIPTION: +* This library introduce Marvell API for OS dependent CPU architecture +* APIs. This library introduce single CPU architecture services APKI +* cross OS. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#include +#include "mvOs.h" + +static MV_U32 read_p15_c0 (void); + +/* defines */ +#define ARM_ID_REVISION_OFFS 0 +#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) + +#define ARM_ID_PART_NUM_OFFS 4 +#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) + +#define ARM_ID_ARCH_OFFS 16 +#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) + +#define ARM_ID_VAR_OFFS 20 +#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) + +#define ARM_ID_ASCII_OFFS 24 +#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) + + + +void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, + MV_U32 *memHandle) +{ + void *p = kmalloc( size, GFP_KERNEL ); + *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); + return p; +} +void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, + MV_U32 *memHandle) +{ + return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); +} + +void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, + MV_U32 memHandle) +{ + return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); +} + +void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, + MV_U32 memHandle ) +{ + return kfree( pVirtAddr ); +} + +int mvOsRand(void) +{ + int rand; + get_random_bytes(&rand, sizeof(rand) ); + return rand; +} + +/******************************************************************************* +* mvOsCpuVerGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Revision +* +*******************************************************************************/ +MV_U32 mvOsCpuRevGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); +} +/******************************************************************************* +* mvOsCpuPartGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Part number +* +*******************************************************************************/ +MV_U32 mvOsCpuPartGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); +} +/******************************************************************************* +* mvOsCpuArchGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Architicture number +* +*******************************************************************************/ +MV_U32 mvOsCpuArchGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); +} +/******************************************************************************* +* mvOsCpuVarGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Variant number +* +*******************************************************************************/ +MV_U32 mvOsCpuVarGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); +} +/******************************************************************************* +* mvOsCpuAsciiGet() - +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit CPU Variant number +* +*******************************************************************************/ +MV_U32 mvOsCpuAsciiGet( MV_VOID ) +{ + return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); +} + + + +/* +static unsigned long read_p15_c0 (void) +*/ +/* read co-processor 15, register #0 (ID register) */ +static MV_U32 read_p15_c0 (void) +{ + MV_U32 value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + + return value; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h new file mode 100644 index 0000000..8da562a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h @@ -0,0 +1,423 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ +#ifndef _MV_OS_LNX_H_ +#define _MV_OS_LNX_H_ + + +#ifdef __KERNEL__ +/* for kernel space */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "dbg-trace.h" + +extern void mv_early_printk(char *fmt,...); + +#define MV_ASM __asm__ __volatile__ +#define INLINE inline +#define MV_TRC_REC TRC_REC +#define mvOsPrintf printk +#define mvOsEarlyPrintf mv_early_printk +#define mvOsOutput printk +#define mvOsSPrintf sprintf +#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) +#define mvOsFree kfree +#define mvOsMemcpy memcpy +#define mvOsSleep(_mils_) mdelay(_mils_) +#define mvOsTaskLock() +#define mvOsTaskUnlock() +#define strtol simple_strtoul +#define mvOsDelay(x) mdelay(x) +#define mvOsUDelay(x) udelay(x) +#define mvCopyFromOs copy_from_user +#define mvCopyToOs copy_to_user + + +#include "mvTypes.h" +#include "mvCommon.h" + +#ifdef MV_NDEBUG +#define mvOsAssert(cond) +#else +#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } +#endif /* MV_NDEBUG */ + +#else /* __KERNEL__ */ + +/* for user space applications */ +#include +#include +#include +#include + +#define INLINE inline +#define mvOsPrintf printf +#define mvOsOutput printf +#define mvOsMalloc(_size_) malloc(_size_) +#define mvOsFree free +#define mvOsAssert(cond) assert(cond) + +#endif /* __KERNEL__ */ +#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ + pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) + +#define mvOsCacheClear(pDev, p, size ) \ + pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) + +#define mvOsCacheFlush(pDev, p, size ) \ + pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) + +#define mvOsCacheInvalidate(pDev, p, size) \ + pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) + +#define mvOsCacheUnmap(pDev, phys, size) \ + pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) + + +#define CPU_PHY_MEM(x) (MV_U32)x +#define CPU_MEMIO_CACHED_ADDR(x) (void*)x +#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x + + +/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ +#define MV_MEMIO32_WRITE(addr, data) \ + ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) + +#define MV_MEMIO32_READ(addr) \ + ((*((volatile unsigned int*)(addr)))) + +#define MV_MEMIO16_WRITE(addr, data) \ + ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) + +#define MV_MEMIO16_READ(addr) \ + ((*((volatile unsigned short*)(addr)))) + +#define MV_MEMIO8_WRITE(addr, data) \ + ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) + +#define MV_MEMIO8_READ(addr) \ + ((*((volatile unsigned char*)(addr)))) + + +/* No Fast Swap implementation (in assembler) for ARM */ +#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) +#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) +#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) +#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) + +/* 32 and 16 bit read/write in big/little endian mode */ + +/* 16bit write in little endian mode */ +#define MV_MEMIO_LE16_WRITE(addr, data) \ + MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) + +/* 16bit read in little endian mode */ +static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) +{ + MV_U16 data; + + data= (MV_U16)MV_MEMIO16_READ(addr); + + return (MV_U16)MV_16BIT_LE_FAST(data); +} + +/* 32bit write in little endian mode */ +#define MV_MEMIO_LE32_WRITE(addr, data) \ + MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) + +/* 32bit read in little endian mode */ +static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) +{ + MV_U32 data; + + data= (MV_U32)MV_MEMIO32_READ(addr); + + return (MV_U32)MV_32BIT_LE_FAST(data); +} + +static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) +{ + while(byteCount != 0) + { + *dstAddr = *srcAddr; + dstAddr++; + srcAddr++; + byteCount--; + } +} + +static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) +{ + MV_U64 division = 0; + + if(divisor == 1) + return divided; + + while(divided >= divisor) + { + division++; + divided -= divisor; + } + if (modulu != NULL) + *modulu = divided; + + return division; +} + +#if defined(MV_BRIDGE_SYNC_REORDER) +extern MV_U32 *mvUncachedParam; + +static __inline void mvOsBridgeReorderWA(void) +{ + volatile MV_U32 val = 0; + + val = mvUncachedParam[0]; +} +#endif + + +/* Flash APIs */ +#define MV_FL_8_READ MV_MEMIO8_READ +#define MV_FL_16_READ MV_MEMIO_LE16_READ +#define MV_FL_32_READ MV_MEMIO_LE32_READ +#define MV_FL_8_DATA_READ MV_MEMIO8_READ +#define MV_FL_16_DATA_READ MV_MEMIO16_READ +#define MV_FL_32_DATA_READ MV_MEMIO32_READ +#define MV_FL_8_WRITE MV_MEMIO8_WRITE +#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE +#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE +#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE +#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE +#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE + + +/* CPU cache information */ +#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ +#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ + +#ifdef CONFIG_L2_CACHE_ENABLE +/* Data cache flush one line */ +#define mvOsCacheLineFlushInv(handle, addr) \ +{ \ + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ + __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ + __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ +} + +#else + +/* Data cache flush one line */ +#define mvOsCacheLineFlushInv(handle, addr) \ +{ \ + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ +} +#endif + +#ifdef CONFIG_L2_CACHE_ENABLE +#define mvOsCacheLineInv(handle,addr) \ +{ \ + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ + __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ +} +#else +#define mvOsCacheLineInv(handle,addr) \ +{ \ + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ +} +#endif + +#ifdef CONFIG_L2_CACHE_ENABLE +/* Data cache flush one line */ +#define mvOsCacheLineFlush(handle, addr) \ +{ \ + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ + __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ + __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ +} + +#else +/* Data cache flush one line */ +#define mvOsCacheLineFlush(handle, addr) \ +{ \ + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ + __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ +} +#endif + +static __inline void mvOsPrefetch(const void *ptr) +{ +#ifdef CONFIG_USE_DSP + __asm__ __volatile__( + "pld\t%0" + : + : "o" (*(char *)ptr) + : "cc"); +#else + return; +#endif +} + + +/* Flush CPU pipe */ +#define CPU_PIPE_FLUSH + + + + + +/* register manipulations */ + +/****************************************************************************** +* This debug function enable the write of each register that u-boot access to +* to an array in the DRAM, the function record only MV_REG_WRITE access. +* The function could not be operate when booting from flash. +* In order to print the array we use the printreg command. +******************************************************************************/ +/* #define REG_DEBUG */ +#if defined(REG_DEBUG) +extern int reg_arry[2048][2]; +extern int reg_arry_index; +#endif + +/* Marvell controller register read/write macros */ +#define MV_REG_VALUE(offset) \ + (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) + +#define MV_REG_READ(offset) \ + (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) + +#if defined(REG_DEBUG) +#define MV_REG_WRITE(offset, val) \ + MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ + { \ + reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ + reg_arry[reg_arry_index][1] = (val);\ + reg_arry_index++;\ + } +#else +#define MV_REG_WRITE(offset, val) \ + MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); +#endif + +#define MV_REG_BYTE_READ(offset) \ + (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) + +#if defined(REG_DEBUG) +#define MV_REG_BYTE_WRITE(offset, val) \ + MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ + { \ + reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ + reg_arry[reg_arry_index][1] = (val);\ + reg_arry_index++;\ + } +#else +#define MV_REG_BYTE_WRITE(offset, val) \ + MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) +#endif + +#if defined(REG_DEBUG) +#define MV_REG_BIT_SET(offset, bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ + MV_32BIT_LE_FAST(bitMask)))); \ + { \ + reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ + reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ + reg_arry_index++;\ + } +#else +#define MV_REG_BIT_SET(offset, bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ + MV_32BIT_LE_FAST(bitMask)))) +#endif + +#if defined(REG_DEBUG) +#define MV_REG_BIT_RESET(offset,bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ + MV_32BIT_LE_FAST(~bitMask)))); \ + { \ + reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ + reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ + reg_arry_index++;\ + } +#else +#define MV_REG_BIT_RESET(offset,bitMask) \ + (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ + (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ + MV_32BIT_LE_FAST(~bitMask)))) +#endif + + + +/* ARM architecture APIs */ +MV_U32 mvOsCpuRevGet (MV_VOID); +MV_U32 mvOsCpuPartGet (MV_VOID); +MV_U32 mvOsCpuArchGet (MV_VOID); +MV_U32 mvOsCpuVarGet (MV_VOID); +MV_U32 mvOsCpuAsciiGet (MV_VOID); + +/* Other APIs */ +void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); +void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); +void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); +void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); +int mvOsRand(void); + +#endif /* _MV_OS_LNX_H_ */ + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h new file mode 100644 index 0000000..c925a9e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h @@ -0,0 +1,158 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +*******************************************************************************/ +/******************************************************************************* +* mvOsLinux.h - O.S. interface header file for Linux +* +* DESCRIPTION: +* This header file contains OS dependent definition under Linux +* +* DEPENDENCIES: +* Linux kernel header files. +* +* FILE REVISION NUMBER: +* $Revision: 1.1 $ +*******************************************************************************/ + +#ifndef __INCmvOsLinuxh +#define __INCmvOsLinuxh + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "mvOs.h" + + +/* Definitions */ +#define MV_DEFAULT_QUEUE_DEPTH 2 +#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION +#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN + +#ifdef CONFIG_MV88F6082 + #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE + #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 + #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN +#endif + +/* System dependent macro for flushing CPU write cache */ +#if defined (MV_BRIDGE_SYNC_REORDER) +#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ + wmb(); \ + mvOsBridgeReorderWA(); \ + } while (0) +#else +#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() +#endif /* CONFIG_MV78XX0 */ + +/* System dependent little endian from / to CPU conversions */ +#define MV_CPU_TO_LE16(x) cpu_to_le16(x) +#define MV_CPU_TO_LE32(x) cpu_to_le32(x) + +#define MV_LE16_TO_CPU(x) le16_to_cpu(x) +#define MV_LE32_TO_CPU(x) le32_to_cpu(x) + +#ifdef __BIG_ENDIAN_BITFIELD +#define MV_BIG_ENDIAN_BITFIELD +#endif + +/* System dependent register read / write in byte/word/dword variants */ +#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) +#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) +#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) +#define MV_REG_READ_BYTE(base, offset) readb(base + offset) +#define MV_REG_READ_WORD(base, offset) readw(base + offset) +#define MV_REG_READ_DWORD(base, offset) readl(base + offset) + + +/* Typedefs */ + +/* System dependant typedefs */ +typedef void *MV_VOID_PTR; +typedef u32 *MV_U32_PTR; +typedef u16 *MV_U16_PTR; +typedef u8 *MV_U8_PTR; +typedef char *MV_CHAR_PTR; +typedef void *MV_BUS_ADDR_T; +typedef unsigned long MV_CPU_FLAGS; + + +/* Structures */ +/* System dependent structure */ +typedef struct mvOsSemaphore +{ + int notUsed; +} MV_OS_SEMAPHORE; + + +/* Functions (User implemented)*/ + +/* Semaphore init, take and release */ +#define mvOsSemInit(x) MV_TRUE +#define mvOsSemTake(x) +#define mvOsSemRelease(x) + +/* Interrupt masking and unmasking functions */ +MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); +MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); + +/* Delay function in micro seconds resolution */ +void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); + +/* Typedefs */ +typedef enum mvBoolean +{ + MV_SFALSE, MV_STRUE +} MV_BOOLEAN; + +/* System logging function */ +#include "mvLog.h" +/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ +#ifdef MV_LOGGER +#define MV_SATA_SUPPORT_READ_WRITE_LONG +#endif + +#define MV_IAL_LOG_ID 3 + +#endif /* __INCmvOsLinuxh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h new file mode 100644 index 0000000..d761060 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h @@ -0,0 +1,375 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. + +*******************************************************************************/ +/******************************************************************************* +* mvSysHwCfg.h - Marvell system HW configuration file +* +* DESCRIPTION: +* None. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __INCmvSysHwConfigh +#define __INCmvSysHwConfigh + +#include "../../../../include/linux/autoconf.h" + +#define CONFIG_MARVELL 1 + +/* includes */ +#define _1K 0x00000400 +#define _4K 0x00001000 +#define _8K 0x00002000 +#define _16K 0x00004000 +#define _32K 0x00008000 +#define _64K 0x00010000 +#define _128K 0x00020000 +#define _256K 0x00040000 +#define _512K 0x00080000 + +#define _1M 0x00100000 +#define _2M 0x00200000 +#define _4M 0x00400000 +#define _8M 0x00800000 +#define _16M 0x01000000 +#define _32M 0x02000000 +#define _64M 0x04000000 +#define _128M 0x08000000 +#define _256M 0x10000000 +#define _512M 0x20000000 + +#define _1G 0x40000000 +#define _2G 0x80000000 + +/****************************************/ +/* Soc supporeted Units definitions */ +/****************************************/ + +#ifdef CONFIG_MV_INCLUDE_PEX +#define MV_INCLUDE_PEX +#endif +#ifdef CONFIG_MV_INCLUDE_TWSI +#define MV_INCLUDE_TWSI +#endif +#ifdef CONFIG_MV_INCLUDE_CESA +#define MV_INCLUDE_CESA +#endif +#ifdef CONFIG_MV_INCLUDE_GIG_ETH +#define MV_INCLUDE_GIG_ETH +#endif +#ifdef CONFIG_MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_INTEG_SATA +#define MV_INCLUDE_SATA +#endif +#ifdef CONFIG_MV_INCLUDE_USB +#define MV_INCLUDE_USB +#define MV_USB_VOLTAGE_FIX +#endif +#ifdef CONFIG_MV_INCLUDE_NAND +#define MV_INCLUDE_NAND +#endif +#ifdef CONFIG_MV_INCLUDE_TDM +#define MV_INCLUDE_TDM +#endif +#ifdef CONFIG_MV_INCLUDE_XOR +#define MV_INCLUDE_XOR +#endif +#ifdef CONFIG_MV_INCLUDE_TWSI +#define MV_INCLUDE_TWSI +#endif +#ifdef CONFIG_MV_INCLUDE_UART +#define MV_INCLUDE_UART +#endif +#ifdef CONFIG_MV_INCLUDE_SPI +#define MV_INCLUDE_SPI +#endif +#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD +#define MV_INCLUDE_SFLASH_MTD +#endif +#ifdef CONFIG_MV_INCLUDE_AUDIO +#define MV_INCLUDE_AUDIO +#endif +#ifdef CONFIG_MV_INCLUDE_TS +#define MV_INCLUDE_TS +#endif +#ifdef CONFIG_MV_INCLUDE_SDIO +#define MV_INCLUDE_SDIO +#endif + + +/* NAND flash stuff */ +#ifdef CONFIG_MV_NAND_BOOT +#define MV_NAND_BOOT +#endif +#ifdef CONFIG_MV_NAND +#define MV_NAND +#endif + +/* SPI flash stuff */ +#ifdef CONFIG_MV_SPI_BOOT +#define MV_SPI_BOOT +#endif + + +/****************************************************************/ +/************* General configuration ********************/ +/****************************************************************/ + +/* Enable Clock Power Control */ +#define MV_INCLUDE_CLK_PWR_CNTRL + +/* Disable the DEVICE BAR in the PEX */ +#define MV_DISABLE_PEX_DEVICE_BAR + +/* Allow the usage of early printings during initialization */ +#define MV_INCLUDE_EARLY_PRINTK + +/****************************************************************/ +/************* NFP configuration ********************************/ +/****************************************************************/ +#define MV_NFP_SEC_Q_SIZE 64 +#define MV_NFP_SEC_REQ_Q_SIZE 1000 + + + +/****************************************************************/ +/************* CESA configuration ********************/ +/****************************************************************/ + +#ifdef MV_INCLUDE_CESA + +#define MV_CESA_MAX_CHAN 4 + +/* Use 2K of SRAM */ +#define MV_CESA_MAX_BUF_SIZE 1600 + +#endif /* MV_INCLUDE_CESA */ + +#if defined(CONFIG_MV_INCLUDE_GIG_ETH) + +#ifdef CONFIG_MV_NFP_STATS +#define MV_FP_STATISTICS +#else +#undef MV_FP_STATISTICS +#endif +/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ +#define MV_ETH_SKB_REUSE_DEFAULT 1 +/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ +#define MV_ETH_TX_EN_DEFAULT 0 + +/* un-comment if you want to perform tx_done from within the poll function */ +/* #define ETH_TX_DONE_ISR */ + +/* put descriptors in uncached memory */ +/* #define ETH_DESCR_UNCACHED */ + +/* Descriptors location: DRAM/internal-SRAM */ +#define ETH_DESCR_IN_SDRAM +#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ + +#if defined(ETH_DESCR_IN_SRAM) +#if defined(ETH_DESCR_UNCACHED) + #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" +#else + #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" +#endif +#elif defined(ETH_DESCR_IN_SDRAM) +#if defined(ETH_DESCR_UNCACHED) + #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" +#else + #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" +#endif +#else + #error "Ethernet descriptors location undefined" +#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ + +/* SW Sync-Barrier: not relevant for 88fxx81*/ +/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ +/* In RX the CPU theoretically might see himself as the descriptor owner, */ +/* although the buffer hadn't been written to DRAM yet. Performance cost. */ +/* #define INCLUDE_SYNC_BARR */ + +/* Buffers cache coherency method (buffers in DRAM) */ +#ifndef MV_CACHE_COHER_SW +/* Taken from mvCommon.h */ +/* Memory uncached, HW or SW cache coherency is not needed */ +#define MV_UNCACHED 0 +/* Memory cached, HW cache coherency supported in WriteThrough mode */ +#define MV_CACHE_COHER_HW_WT 1 +/* Memory cached, HW cache coherency supported in WriteBack mode */ +#define MV_CACHE_COHER_HW_WB 2 +/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ +#define MV_CACHE_COHER_SW 3 + +#endif + +/* DRAM cache coherency configuration */ +#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW + + +#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ + +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) + #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) + #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" +#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) + #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" +#elif (ETHER_DRAM_COHER == MV_UNCACHED) +# define ETH_SDRAM_CONFIG_STR "DRAM uncached" +#else + #error "Ethernet-DRAM undefined" +#endif /* ETHER_DRAM_COHER */ + + +/****************************************************************/ +/************* Ethernet driver configuration ********************/ +/****************************************************************/ + +/* port's default queueus */ +#define ETH_DEF_TXQ 0 +#define ETH_DEF_RXQ 0 + +#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM +#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM + +/* interrupt coalescing setting */ +#define ETH_TX_COAL 200 +#define ETH_RX_COAL 200 + +/* Checksum offloading */ +#define TX_CSUM_OFFLOAD +#define RX_CSUM_OFFLOAD + +#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ + +/****************************************************************/ +/*************** Telephony configuration ************************/ +/****************************************************************/ +#if defined(CONFIG_MV_TDM_LINEAR_MODE) + #define MV_TDM_LINEAR_MODE +#elif defined(CONFIG_MV_TDM_ULAW_MODE) + #define MV_TDM_ULAW_MODE +#endif + +#if defined(CONFIG_MV_TDM_5CHANNELS) + #define MV_TDM_5CHANNELS +#endif + +#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) + #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE +#endif + +/* We use the following registers to store DRAM interface pre configuration */ +/* auto-detection results */ +/* IMPORTANT: We are using mask register for that purpose. Before writing */ +/* to units mask register, make sure main maks register is set to disable */ +/* all interrupts. */ +#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ +#define DRAM_BUF_REG1 0x30820 /* sdram config */ +#define DRAM_BUF_REG2 0x30830 /* sdram mode */ +#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ +#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ +#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ +#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ +#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ +#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ +#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ +#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ +#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ +#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ +#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ +#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ + +/* Following the pre-configuration registers default values restored after */ +/* auto-detection is done */ +#define DRAM_BUF_REG_DV 0 + +/* System Mapping */ +#define SDRAM_CS0_BASE 0x00000000 +#define SDRAM_CS0_SIZE _256M + +#define SDRAM_CS1_BASE 0x10000000 +#define SDRAM_CS1_SIZE _256M + +#define SDRAM_CS2_BASE 0x20000000 +#define SDRAM_CS2_SIZE _256M + +#define SDRAM_CS3_BASE 0x30000000 +#define SDRAM_CS3_SIZE _256M + +/* PEX */ +#define PEX0_MEM_BASE 0xe8000000 +#define PEX0_MEM_SIZE _128M + +#define PEX0_IO_BASE 0xf2000000 +#define PEX0_IO_SIZE _1M + +/* Device Chip Selects */ +#define NFLASH_CS_BASE 0xfa000000 +#define NFLASH_CS_SIZE _2M + +#define SPI_CS_BASE 0xf4000000 +#define SPI_CS_SIZE _16M + +#define CRYPT_ENG_BASE 0xf0000000 +#define CRYPT_ENG_SIZE _2M + +#define BOOTDEV_CS_BASE 0xff800000 +#define BOOTDEV_CS_SIZE _8M + +/* CS2 - BOOTROM */ +#define DEVICE_CS2_BASE 0xff900000 +#define DEVICE_CS2_SIZE _1M + +/* PEX Work arround */ +/* the target we will use for the workarround */ +#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM +/*a flag that indicates if we are going to use the +size and base of the target we using for the workarround +window */ +#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 +/* if the above flag is 0 then the following values +will be used for the workarround window base and size, +otherwise the following defines will be ignored */ +#define PEX_CONFIG_RW_WA_BASE 0xF3000000 +#define PEX_CONFIG_RW_WA_SIZE _16M + +/* Internal registers: size is defined in Controllerenvironment */ +#define INTER_REGS_BASE 0xFEE00000 + +/* DRAM detection stuff */ +#define MV_DRAM_AUTO_SIZE + +/* Board clock detection */ +#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ +#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ +#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ +#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ + +/* PEX-PCI\PCI-PCI Bridge*/ +#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ + + + +#endif /* __INCmvSysHwConfigh */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c new file mode 100644 index 0000000..717c150 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c @@ -0,0 +1,376 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvCntmr.h" +#include "cpu/mvCpu.h" + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +extern unsigned int whoAmI(void); + +/******************************************************************************* +* mvCntmrLoad - +* +* DESCRIPTION: +* Load an init Value to a given counter/timer +* +* INPUT: +* countNum - counter number +* value - value to be loaded +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) +{ + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); + return MV_BAD_PARAM;; + + } + + MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); + MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrRead - +* +* DESCRIPTION: +* Returns the value of the given Counter/Timer +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 counter value +*******************************************************************************/ +MV_U32 mvCntmrRead(MV_U32 countNum) +{ + return MV_REG_READ(CNTMR_VAL_REG(countNum)); +} + +/******************************************************************************* +* mvCntmrWrite - +* +* DESCRIPTION: +* Returns the value of the given Counter/Timer +* +* INPUT: +* countNum - counter number +* countVal - value to write +* +* OUTPUT: +* None. +* +* RETURN: +* None +*******************************************************************************/ +void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) +{ + MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); +} + +/******************************************************************************* +* mvCntmrCtrlSet - +* +* DESCRIPTION: +* Set the Control to a given counter/timer +* +* INPUT: +* countNum - counter number +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); + + + if (pCtrl->enable) /* enable counter\timer */ + { + cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); + } + else /* disable counter\timer */ + { + cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); + } + + if ( pCtrl->autoEnable ) /* Auto mode */ + { + cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); + + } + else /* no auto mode */ + { + cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); + } + + MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); + + return MV_OK; + +} + +/******************************************************************************* +* mvCntmrCtrlGet - +* +* DESCRIPTION: +* Get the Control value of a given counter/timer +* +* INPUT: +* countNum - counter number +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* Counter\Timer control value +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); + return MV_BAD_PARAM;; + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); + + /* enable counter\timer */ + if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) + { + pCtrl->enable = MV_TRUE; + } + else + { + pCtrl->enable = MV_FALSE; + } + + /* counter mode */ + if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) + { + pCtrl->autoEnable = MV_TRUE; + } + else + { + pCtrl->autoEnable = MV_FALSE; + } + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrEnable - +* +* DESCRIPTION: +* Set the Enable-Bit to logic '1' ==> starting the counter +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrEnable(MV_U32 countNum) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); + + /* enable counter\timer */ + cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); + + + MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrDisable - +* +* DESCRIPTION: +* Stop the counter/timer running, and returns its Value +* +* INPUT: +* countNum - counter number +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 counter\timer value +*******************************************************************************/ +MV_STATUS mvCntmrDisable(MV_U32 countNum) +{ + MV_U32 cntmrCtrl; + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); + return MV_BAD_PARAM;; + + } + + /* read control register */ + cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); + + /* disable counter\timer */ + cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); + + MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); + + return MV_OK; +} + +/******************************************************************************* +* mvCntmrStart - +* +* DESCRIPTION: +* Combined all the sub-operations above to one function: Load,setMode,Enable +* +* INPUT: +* countNum - counter number +* value - value of the counter\timer to be set +* pCtrl - pointer to MV_CNTMR_CTRL structure +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess +*******************************************************************************/ +MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, + MV_CNTMR_CTRL *pCtrl) +{ + + if (countNum >= MV_CNTMR_MAX_COUNTER ) + { + + mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); + return MV_BAD_PARAM;; + + } + + /* load value onto counter\timer */ + mvCntmrLoad(countNum,value); + + /* set the counter to load in the first time */ + mvCntmrWrite(countNum,value); + + /* set control for timer \ cunter and enable */ + mvCntmrCtrlSet(countNum,pCtrl); + + return MV_OK; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h new file mode 100644 index 0000000..b911d0f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvTmrWtdgh +#define __INCmvTmrWtdgh + +/* includes */ +#include "mvCommon.h" +#include "mvOs.h" +#include "cntmr/mvCntmrRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + + +/* This enumerator describe counters\watchdog numbers */ +typedef enum _mvCntmrID +{ + TIMER0 = 0, + TIMER1, + WATCHDOG, + TIMER2, + TIMER3, +}MV_CNTMR_ID; + + +/* Counter / Timer control structure */ +typedef struct _mvCntmrCtrl +{ + MV_BOOL enable; /* enable */ + MV_BOOL autoEnable; /* counter/Timer */ +}MV_CNTMR_CTRL; + + +/* Functions */ + +/* Load an init Value to a given counter/timer */ +MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); + +/* Returns the value of the given Counter/Timer */ +MV_U32 mvCntmrRead(MV_U32 countNum); + +/* Write a value of the given Counter/Timer */ +void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); + +/* Set the Control to a given counter/timer */ +MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); + +/* Get the value of a given counter/timer */ +MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); + +/* Set the Enable-Bit to logic '1' ==> starting the counter. */ +MV_STATUS mvCntmrEnable(MV_U32 countNum); + +/* Stop the counter/timer running, and returns its Value. */ +MV_STATUS mvCntmrDisable(MV_U32 countNum); + +/* Combined all the sub-operations above to one function: Load,setMode,Enable */ +MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, + MV_CNTMR_CTRL *pCtrl); + +#endif /* __INCmvTmrWtdgh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h new file mode 100644 index 0000000..b69bc66 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvTmrwtdgRegsh +#define __INCmvTmrwtdgRegsh + +/*******************************************/ +/* ARM Timers Registers Map */ +/*******************************************/ + +#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ + (((tmrNum) <= 3)?0:8)) +#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ + (((tmrNum) <= 3)?0:8)) +#define CNTMR_CTRL_REG (CNTMR_BASE) + +/*For MV78XX0*/ +#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) +#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) + +/* ARM Timers Registers Map */ +/*******************************************/ + + +/* ARM Timers Control Register */ +/* CPU_TIMERS_CTRL_REG (CTCR) */ + +#define TIMER0_NUM 0 +#define TIMER1_NUM 1 +#define WATCHDOG_NUM 2 +#define TIMER2_NUM 3 +#define TIMER3_NUM 4 + +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + + +/* ARM Timer\Watchdog Reload Register */ +/* CNTMR_RELOAD_REG (TRR) */ + +#define TRG_ARM_TIMER_REL_OFFS 0 +#define TRG_ARM_TIMER_REL_MASK 0xffffffff + +/* ARM Timer\Watchdog Register */ +/* CNTMR_VAL_REG (TVRG) */ + +#define TVR_ARM_TIMER_OFFS 0 +#define TVR_ARM_TIMER_MASK 0xffffffff +#define TVR_ARM_TIMER_MAX 0xffffffff + + + +#endif /* __INCmvTmrwtdgRegsh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c new file mode 100644 index 0000000..609e674 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c @@ -0,0 +1,207 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "mvOs.h" +#include "mvCpuCntrs.h" + + +const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = +{ + /*0*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, + MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, + MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, + }, + /*1*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, + MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, + }, + /*2*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, + MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, + }, + /*3*/ + { + MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, + MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, + MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, + MV_CPU_CNTRS_INVALID, + } +}; + +MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; + +MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; + +void mvCpuCntrsReset(void) +{ + MV_U32 reg = 0; + + MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); + MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); +} + +void program_counter(int counter, int op) +{ + MV_U32 reg = (1 << op) | 0x1; /*enable*/ + + switch(counter) + { + case 0: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); + return; + + case 1: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); + return; + + case 2: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); + return; + + case 3: + __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); + return; + + default: + mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); + } + return; +} + +void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; icounters_sum[i] = 0; + } + pEvent->num_of_measurements = 0; +} + + +MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) +{ + int i; + MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); + + if(event) + { + strncpy(event->name, name, sizeof(event->name)); + event->num_of_measurements = 0; + event->avg_sample_count = print_threshold; + for(i=0; icounters_before[i] = 0; + event->counters_after[i] = 0; + event->counters_sum[i] = 0; + } + } + return event; +} + +void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) +{ + if(event != NULL) + mvOsFree(event); +} + + +MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, + char* name, MV_U32 overhead) +{ + int i; + + /* Find required operations */ + for(i=0; inum_of_measurements < pEvent->avg_sample_count) + return; + + mvOsPrintf("%16s: ", pEvent->name); + for(i=0; icounters_sum[i], + pEvent->num_of_measurements, NULL); + if(counters_avg >= mvCpuCntrsTbl[i].overhead) + counters_avg -= mvCpuCntrsTbl[i].overhead; + else + counters_avg = 0; + + mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); + } + mvOsPrintf("\n"); + mvCpuCntrsEventClear(pEvent); + mvCpuCntrsReset(); +} + +void mvCpuCntrsStatus(void) +{ + int i; + + for(i=0; icounters_before[i] = mvCpuCntrsRead(i); +#else + pEvent->counters_before[1] = mvCpuCntrsRead(1); + pEvent->counters_before[3] = mvCpuCntrsRead(3); + pEvent->counters_before[0] = mvCpuCntrsRead(0); + pEvent->counters_before[2] = mvCpuCntrsRead(2); +#endif +} + +static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) +{ + int i; + +#if 0 + /* order is important - we want to measure the cycle count first here! */ + for(i=0; icounters_after[i] = mvCpuCntrsRead(i); +#else + pEvent->counters_after[2] = mvCpuCntrsRead(2); + pEvent->counters_after[0] = mvCpuCntrsRead(0); + pEvent->counters_after[3] = mvCpuCntrsRead(3); + pEvent->counters_after[1] = mvCpuCntrsRead(1); +#endif + + for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); + } + pEvent->num_of_measurements++; +} + + +#ifdef CONFIG_MV_CPU_PERF_CNTRS + +#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) + +#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) + +#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) + +#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) + +#else + +#define MV_CPU_CNTRS_READ(counter) +#define MV_CPU_CNTRS_START(event) +#define MV_CPU_CNTRS_STOP(event) +#define MV_CPU_CNTRS_SHOW(event) + +#endif /* CONFIG_MV_CPU_PERF_CNTRS */ + + +#endif /* __mvCpuCntrs_h__ */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c new file mode 100644 index 0000000..0333862 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c @@ -0,0 +1,143 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include "mvOs.h" +#include "mvCpuL2Cntrs.h" + + + +MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; + +MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; + +void mvCpuL2CntrsReset(void) +{ + MV_U32 reg = 0; + + MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); + MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); +} + +static void mvCpuL2CntrConfig(int counter, int op) +{ + MV_U32 reg = (1 << op) | 0x1; /*enable*/ + + switch(counter) + { + case 0: + MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); + return; + + case 1: + MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); + return; + + default: + mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); + } + return; +} + +void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; icounters_sum[i] = 0; + } + pEvent->num_of_measurements = 0; +} + + +MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) +{ + int i; + MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); + + if(event) + { + strncpy(event->name, name, sizeof(event->name)); + event->num_of_measurements = 0; + event->avg_sample_count = print_threshold; + for(i=0; icounters_before[i] = 0; + event->counters_after[i] = 0; + event->counters_sum[i] = 0; + } + } + return event; +} + +void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) +{ + if(event != NULL) + mvOsFree(event); +} + + +MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, + char* name, MV_U32 overhead) +{ + strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); + mvCpuL2CntrsTbl[counter].operation = op; + mvCpuL2CntrsTbl[counter].opIdx = op; + mvCpuL2CntrsTbl[counter].overhead = overhead; + mvCpuL2CntrConfig(counter, op); + mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", + counter, op, overhead); + return MV_OK; +} + +void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + MV_U64 counters_avg; + + if(pEvent->num_of_measurements < pEvent->avg_sample_count) + return; + + mvOsPrintf("%16s: ", pEvent->name); + for(i=0; icounters_sum[i], + pEvent->num_of_measurements, NULL); + + if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) + counters_avg -= mvCpuL2CntrsTbl[i].overhead; + else + counters_avg = 0; + + mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); + } + mvOsPrintf("\n"); + mvCpuL2CntrsEventClear(pEvent); + mvCpuL2CntrsReset(); +} + +void mvCpuL2CntrsStatus(void) +{ + int i; + + for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); +} + +static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) +{ + int i; + + for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); + pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); + } + pEvent->num_of_measurements++; +} + + +#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS + +#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) + +#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) + +#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) + +#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) + +#else + +#define MV_CPU_L2_CNTRS_READ(counter) +#define MV_CPU_L2_CNTRS_START(event) +#define MV_CPU_L2_CNTRS_STOP(event) +#define MV_CPU_L2_CNTRS_SHOW(event) + +#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ + + +#endif /* __mvCpuL2Cntrs_h__ */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c new file mode 100644 index 0000000..d1b8a3d --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c @@ -0,0 +1,1479 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "ddr1_2/mvDram.h" +#include "boardEnv/mvBoardEnvLib.h" + +#undef MV_DEBUG +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, + MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 cas2ps(MV_U8 spd_byte); +/******************************************************************************* +* mvDramBankGet - Get the DRAM bank paramters. +* +* DESCRIPTION: +* This function retrieves DRAM bank parameters as described in +* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board +* has its DRAM on DIMMs it will use its EEPROM to extract SPD data +* from it. Otherwise, if the DRAM is soldered on board, the function +* should insert its bank information into MV_DRAM_BANK_INFO struct. +* +* INPUT: +* bankNum - Board DRAM bank number. +* +* OUTPUT: +* pBankInfo - DRAM bank information struct. +* +* RETURN: +* MV_FAIL - Bank parameters could not be read. +* +*******************************************************************************/ +MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_DIMM_INFO dimmInfo; + + DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); + /* zero pBankInfo structure */ + memset(pBankInfo, 0, sizeof(*pBankInfo)); + + if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return MV_FAIL; + } + if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); + return MV_FAIL; + } + + /* convert Dimm info to Bank info */ + cpyDimm2BankInfo(&dimmInfo, pBankInfo); + + return MV_OK; +} + +/******************************************************************************* +* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. +* +* DESCRIPTION: +* Convert a Dimm info struct into a bank info struct. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* pBankInfo - DRAM bank information struct. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, + MV_DRAM_BANK_INFO *pBankInfo) +{ + pBankInfo->memoryType = pDimmInfo->memoryType; + + /* DIMM dimensions */ + pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; + pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; + pBankInfo->dataWidth = pDimmInfo->dataWidth; + pBankInfo->errorCheckType = pDimmInfo->errorCheckType; + pBankInfo->sdramWidth = pDimmInfo->sdramWidth; + pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; + pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; + pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; + pBankInfo->refreshInterval = pDimmInfo->refreshInterval; + + /* DIMM timing parameters */ + pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; + pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; + pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; + + pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; + pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; + pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; + pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; + pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; + pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; + pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; + pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; + + /* Parameters calculated from the extracted DIMM information */ + pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; + pBankInfo->deviceDensity = pDimmInfo->deviceDensity; + pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / + pDimmInfo->numOfModuleBanks; + + /* DIMM attributes (MV_TRUE for yes) */ + + if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || + (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) + { + if (pDimmInfo->dimmAttributes & BIT1) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ + { + if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + + return; +} + +/******************************************************************************* +* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. +* +* DESCRIPTION: +* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdCpy(MV_VOID) +{ + MV_U32 i; + MV_U32 spdChecksum; + + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[SPD_SIZE]; + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, + &twsiSlave, data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the DIMM 1 SPD */ + twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + for(i = 0 ; i < SPD_SIZE ; i++) + { + twsiSlave.offset = i; + if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, + &twsiSlave, &data[i], 1) ) + { + mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); + return MV_FAIL; + } + mvOsDelay(5); + } + + DB(puts("DRAM: Reading dimm info succeded.\n")); + return MV_OK; +} + +/******************************************************************************* +* dimmSpdGet - Get the SPD parameters. +* +* DESCRIPTION: +* Read the DIMM SPD parameters into given struct parameter. +* +* INPUT: +* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. +* +* OUTPUT: +* pDimmInfo - DIMM information structure. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) +{ + MV_U32 i; + MV_U32 density = 1; + MV_U32 spdChecksum; + + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[SPD_SIZE]; + + if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + twsiSlave.slaveAddr.address = (dimmNum == 0) ? + MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, + &twsiSlave, data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the dimmInfo structure*/ + for(i = 0 ; i < SPD_SIZE ; i++) + { + pDimmInfo->spdRawData[i] = data[i]; + DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); + } + + DB(mvOsPrintf("DRAM SPD Information:\n")); + + /* Memory type (DDR / SDRAM) */ + switch (data[DIMM_MEM_TYPE]) + { + case (DIMM_MEM_TYPE_SDRAM): + pDimmInfo->memoryType = MEM_TYPE_SDRAM; + DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); + break; + case (DIMM_MEM_TYPE_DDR1): + pDimmInfo->memoryType = MEM_TYPE_DDR1; + DB(mvOsPrintf("DRAM Memeory type DDR1\n")); + break; + case (DIMM_MEM_TYPE_DDR2): + pDimmInfo->memoryType = MEM_TYPE_DDR2; + DB(mvOsPrintf("DRAM Memeory type DDR2\n")); + break; + default: + mvOsPrintf("ERROR: Undefined memory type!\n"); + return MV_ERROR; + } + + + /* Number Of Row Addresses */ + pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; + DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); + + /* Number Of Column Addresses */ + pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; + DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); + + /* Number Of Module Banks */ + pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", + pDimmInfo->numOfModuleBanks)); + + /* Number of module banks encoded differently for DDR2 */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; + + /* Data Width */ + pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; + DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); + + /* Minimum Cycle Time At Max CasLatancy */ + pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); + + /* Error Check Type */ + pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; + DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", + pDimmInfo->errorCheckType)); + + /* Refresh Interval */ + pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; + DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", + pDimmInfo->refreshInterval)); + + /* Sdram Width */ + pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; + DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); + + /* Error Check Data Width */ + pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; + DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", + pDimmInfo->errorCheckDataWidth)); + + /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + + pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; + DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", + pDimmInfo->burstLengthSupported)); + + /* Number Of Banks On Each Device */ + pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", + pDimmInfo->numOfBanksOnEachDevice)); + + /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; + DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", + pDimmInfo->suportedCasLatencies)); + + /* For DDR2 only, get the DIMM type information */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + { + pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; + DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", + pDimmInfo->dimmTypeInfo)); + } + + /* SDRAM Modules Attributes */ + pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; + DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", + pDimmInfo->dimmAttributes)); + + /* Minimum Cycle Time At Max CasLatancy Minus 1*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); + + /* Minimum Cycle Time At Max CasLatancy Minus 2*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); + + pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; + DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", + pDimmInfo->minRowPrechargeTime)); + pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; + DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", + pDimmInfo->minRowActiveToRowActive)); + pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; + DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", + pDimmInfo->minRasToCasDelay)); + pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; + DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", + pDimmInfo->minRasPulseWidth)); + + /* DIMM Bank Density */ + pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; + DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", + pDimmInfo->dimmBankDensity)); + + /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ + pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; + DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", + pDimmInfo->minWriteRecoveryTime)); + + /* Only DDR2 includes Internal Write To Read Command Delay field. */ + pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; + DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", + pDimmInfo->minWriteToReadCmdDelay)); + + /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ + pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; + DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", + pDimmInfo->minReadToPrechCmdDelay)); + + /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ + pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; + DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", + pDimmInfo->minRefreshToActiveCmd)); + + /* calculating the sdram density. Representing device density from */ + /* bit 20 to allow representation of 4GB and above. */ + /* For example, if density is 512Mbit 0x20000000, will be represent in */ + /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ + /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ + density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); + pDimmInfo->deviceDensity = density * + pDimmInfo->numOfBanksOnEachDevice * + pDimmInfo->sdramWidth; + DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); + + /* Number of devices includeing Error correction */ + pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * + pDimmInfo->numOfModuleBanks; + DB(mvOsPrintf("DRAM numberOfDevices %d\n", + pDimmInfo->numberOfDevices)); + + pDimmInfo->size = 0; + + /* Note that pDimmInfo->size is in MB units */ + if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 8; /* Equal to 8MB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 4096; /* Equal to 4GB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 8192; /* Equal to 8GB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 16384; /* Equal to 16GB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + + pDimmInfo->size *= pDimmInfo->numOfModuleBanks; + + DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); + + return MV_OK; +} + +/******************************************************************************* +* dimmSpdPrint - Print the SPD parameters. +* +* DESCRIPTION: +* Print the Dimm SPD parameters. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID dimmSpdPrint(MV_U32 dimmNum) +{ + MV_DIMM_INFO dimmInfo; + MV_U32 i, temp = 0; + MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; + MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; + MV_U32 busClkPs; + MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, + temp_buf[40], *spdRawData; + + busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ + + spdRawData = dimmInfo.spdRawData; + + if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) + { + mvOsOutput("ERROR: Could not read SPD information!\n"); + return; + } + + /* find Manufactura of Dimm Module */ + mvOsOutput("\nManufacturer's JEDEC ID Code: "); + for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) + { + mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); + } + mvOsOutput("\n"); + + /* Manufacturer's Specific Data */ + for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; + } + mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); + + /* Module Part Number */ + for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; + } + mvOsOutput("Module Part Number: %s\n", temp_buf); + + /* Module Serial Number */ + for(i = 0; i < sizeof(MV_U32); i++) + { + temp |= spdRawData[95+i] << 8*i; + } + mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, + (long)temp); + + /* find Manufac-Data of Dimm Module */ + mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", + ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), + ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); + /* find modul_revision of Dimm Module */ + mvOsOutput("Module Revision: %d.%d\n", + spdRawData[91], spdRawData[92]); + + /* find manufac_place of Dimm Module */ + mvOsOutput("manufac_place: %d\n", spdRawData[72]); + + /* go over the first 35 I2C data bytes */ + for(i = 2 ; i <= 35 ; i++) + switch(i) + { + case 2: /* Memory type (DDR1/2 / SDRAM) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + mvOsOutput("Dram Type is: SDRAM\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + mvOsOutput("Dram Type is: SDRAM DDR1\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + mvOsOutput("Dram Type is: SDRAM DDR2\n"); + else + mvOsOutput("Dram Type unknown\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + mvOsOutput("Module Number of row addresses: %d\n", + dimmInfo.numOfRowAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + mvOsOutput("Module Number of col addresses: %d\n", + dimmInfo.numOfColAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + mvOsOutput("Number of Banks on Mod.: %d\n", + dimmInfo.numOfModuleBanks); + break; +/*----------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + mvOsOutput("Module Data Width: %d bit\n", + dimmInfo.dataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch(spdRawData[i]) + { + case 0x0: + mvOsOutput("Module is TTL_5V_TOLERANT\n"); + break; + case 0x1: + mvOsOutput("Module is LVTTL\n"); + break; + case 0x2: + mvOsOutput("Module is HSTL_1_5V\n"); + break; + case 0x3: + mvOsOutput("Module is SSTL_3_3V\n"); + break; + case 0x4: + mvOsOutput("Module is SSTL_2_5V\n"); + break; + case 0x5: + if (dimmInfo.memoryType != MEM_TYPE_SDRAM) + { + mvOsOutput("Module is SSTL_1_8V\n"); + break; + } + default: + mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); + break; + } + break; +/*----------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 11: /* Error Check Type */ + mvOsOutput("Error Check Type (0=NONE): %d\n", + dimmInfo.errorCheckType); + break; +/*----------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + mvOsOutput("Refresh Rate: %x\n", + dimmInfo.refreshInterval); + break; +/*----------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + mvOsOutput("Sdram Width: %d bits\n", + dimmInfo.sdramWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + mvOsOutput("Error Check Data Width: %d bits\n", + dimmInfo.errorCheckDataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay is unsupported */ + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + mvOsOutput("Minimum Clk Delay back to back: %d\n", + spdRawData[i]); + } + break; +/*----------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + mvOsOutput("Burst Length Supported: "); + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + if (dimmInfo.burstLengthSupported & BIT0) + mvOsOutput("1, "); + if (dimmInfo.burstLengthSupported & BIT1) + mvOsOutput("2, "); + } + if (dimmInfo.burstLengthSupported & BIT2) + mvOsOutput("4, "); + if (dimmInfo.burstLengthSupported & BIT3) + mvOsOutput("8, "); + + mvOsOutput(" Bit \n"); + break; +/*----------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + mvOsOutput("Number Of Banks On Each Chip: %d\n", + dimmInfo.numOfBanksOnEachDevice); + break; +/*----------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + mvOsOutput("Suported Cas Latencies: (CL) "); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + for (k = 0; k <=7; k++) + { + if (dimmInfo.suportedCasLatencies & (1 << k)) + mvOsOutput("%d, ", k+1); + } + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.suportedCasLatencies & BIT0) + mvOsOutput("1, "); + if (dimmInfo.suportedCasLatencies & BIT1) + mvOsOutput("1.5, "); + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("2.5, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("3.5, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("4, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("5, "); + } + else + mvOsOutput("?.?, "); + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 20: /* DDR2 DIMM type info */ + if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) + mvOsOutput("Registered DIMM (RDIMM)\n"); + else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) + mvOsOutput("Unbuffered DIMM (UDIMM)\n"); + else + mvOsOutput("Unknown DIMM type.\n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 21: /* SDRAM Modules Attributes */ + mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" Bufferd DQMB Input: Yes \n"); + else + mvOsOutput(" Bufferd DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" Registered DQMB Inputs: Yes \n"); + else + mvOsOutput(" Registered DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" redundant Row Addressing: Yes \n"); + else + mvOsOutput(" redundant Row Addressing: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); + else + mvOsOutput(" FET Switch On-Card Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + mvOsOutput(" Number of Active Registers on the DIMM: %d\n", + (dimmInfo.dimmAttributes & 0x3) + 1); + + mvOsOutput(" Number of PLLs on the DIMM: %d\n", + ((dimmInfo.dimmAttributes) >> 2) & 0x3); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" Analysis probe installed: Yes \n"); + else + mvOsOutput(" Analysis probe installed: No \n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Early Ras Precharge: Yes \n"); + else + mvOsOutput(" Early Ras Precharge: No \n"); + + if ( spdRawData[i] & BIT1 ) + mvOsOutput(" AutoPreCharge: Yes \n"); + else + mvOsOutput(" AutoPreCharge: No \n"); + + if ( spdRawData[i] & BIT2 ) + mvOsOutput(" Precharge All: Yes \n"); + else + mvOsOutput(" Precharge All: No \n"); + + if ( spdRawData[i] & BIT3 ) + mvOsOutput(" Write 1/ReadBurst: Yes \n"); + else + mvOsOutput(" Write 1/ReadBurst: No \n"); + + if ( spdRawData[i] & BIT4 ) + mvOsOutput(" lower VCC tolerance: 5%%\n"); + else + mvOsOutput(" lower VCC tolerance: 10%%\n"); + + if ( spdRawData[i] & BIT5 ) + mvOsOutput(" upper VCC tolerance: 5%%\n"); + else + mvOsOutput(" upper VCC tolerance: 10%%\n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + + if ( !(spdRawData[i] & BIT4) ) + mvOsOutput(" lower VCC tolerance: 0.2V\n"); + + if ( !(spdRawData[i] & BIT5) ) + mvOsOutput(" upper VCC tolerance: 0.2V\n"); + + if ( spdRawData[i] & BIT6 ) + mvOsOutput(" Concurrent Auto Preharge: Yes \n"); + else + mvOsOutput(" Concurrent Auto Preharge: No \n"); + + if ( spdRawData[i] & BIT7 ) + mvOsOutput(" Supports Fast AP: Yes \n"); + else + mvOsOutput(" Supports Fast AP: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + } + break; +/*----------------------------------------------------------------------------*/ + + case 23: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + + mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 25: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + } + mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = 0; + rightOfPoint = time_tmp; + } + mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ + trp_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trrd_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " + "%d.%d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; + mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " + "in Clk cycles %d\n", spdRawData[i], tras_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("8MB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("4GB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("8GB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("16GB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 36: /* Relevant for DDR2 only: Write Recovery Time */ + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + mvOsOutput("Write Recovery Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + } + +} + + +/* + * translate ns.ns/10 coding of SPD timing values + * into ps unit values + */ +/******************************************************************************* +* cas2ps - Translate x.y ns parameter to pico-seconds values +* +* DESCRIPTION: +* This function translates x.y nano seconds to its value in pico seconds. +* For example 3.75ns will return 3750. +* +* INPUT: +* spd_byte - DIMM SPD byte. +* +* OUTPUT: +* None. +* +* RETURN: +* value in pico seconds. +* +*******************************************************************************/ +static MV_U32 cas2ps(MV_U8 spd_byte) +{ + MV_U32 ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + if( ns10 < 10 ) { + ns10 *= 10; + } + else if( ns10 == 10 ) + ns10 = 25; + else if( ns10 == 11 ) + ns10 = 33; + else if( ns10 == 12 ) + ns10 = 66; + else if( ns10 == 13 ) + ns10 = 75; + else + { + mvOsOutput("cas2ps Err. unsupported cycle time.\n"); + } + + return (ns*1000 + ns10*10); +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h new file mode 100644 index 0000000..678e224 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h @@ -0,0 +1,191 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDram +#define __INCmvDram + +#include "ddr1_2/mvDramIf.h" +#include "twsi/mvTwsi.h" + +#define MAX_DIMM_NUM 2 +#define SPD_SIZE 128 + +/* Dimm spd offsets */ +#define DIMM_MEM_TYPE 2 +#define DIMM_ROW_NUM 3 +#define DIMM_COL_NUM 4 +#define DIMM_MODULE_BANK_NUM 5 +#define DIMM_DATA_WIDTH 6 +#define DIMM_VOLT_IF 8 +#define DIMM_MIN_CC_AT_MAX_CAS 9 +#define DIMM_ERR_CHECK_TYPE 11 +#define DIMM_REFRESH_INTERVAL 12 +#define DIMM_SDRAM_WIDTH 13 +#define DIMM_ERR_CHECK_DATA_WIDTH 14 +#define DIMM_MIN_CLK_DEL 15 +#define DIMM_BURST_LEN_SUP 16 +#define DIMM_DEV_BANK_NUM 17 +#define DIMM_SUP_CAL 18 +#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ +#define DIMM_BUF_ADDR_CONT_IN 21 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 +#define DIMM_MIN_ROW_PRECHARGE_TIME 27 +#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 +#define DIMM_MIN_RAS_TO_CAS_DELAY 29 +#define DIMM_MIN_RAS_PULSE_WIDTH 30 +#define DIMM_BANK_DENSITY 31 +#define DIMM_MIN_WRITE_RECOVERY_TIME 36 +#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 +#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 +#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 + +/* Dimm Memory Type values */ +#define DIMM_MEM_TYPE_SDRAM 0x4 +#define DIMM_MEM_TYPE_DDR1 0x7 +#define DIMM_MEM_TYPE_DDR2 0x8 + +#define DIMM_MODULE_MANU_OFFS 64 +#define DIMM_MODULE_MANU_SIZE 8 +#define DIMM_MODULE_VEN_OFFS 73 +#define DIMM_MODULE_VEN_SIZE 25 +#define DIMM_MODULE_ID_OFFS 99 +#define DIMM_MODULE_ID_SIZE 18 + +/* enumeration for voltage levels. */ +typedef enum _mvDimmVoltageIf +{ + TTL_5V_TOLERANT, + LVTTL, + HSTL_1_5V, + SSTL_3_3V, + SSTL_2_5V, + VOLTAGE_UNKNOWN, +} MV_DIMM_VOLTAGE_IF; + + +/* enumaration for SDRAM CAS Latencies. */ +typedef enum _mvDimmSdramCas +{ + SD_CL_1 =1, + SD_CL_2, + SD_CL_3, + SD_CL_4, + SD_CL_5, + SD_CL_6, + SD_CL_7, + SD_FAULT +}MV_DIMM_SDRAM_CAS; + + +/* DIMM information structure */ +typedef struct _mvDimmInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ + + MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 numOfModuleBanks; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + MV_U32 dimmBankDensity; + MV_U32 dimmTypeInfo; /* DDR2 only */ + MV_U32 dimmAttributes; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ + MV_U32 numberOfDevices; + +} MV_DIMM_INFO; + + +MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); +MV_VOID dimmSpdPrint(MV_U32 dimmNum); +MV_STATUS dimmSpdCpy(MV_VOID); + +#endif /* __INCmvDram */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c new file mode 100644 index 0000000..12fb26a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c @@ -0,0 +1,1599 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#include "ddr1_2/mvDramIf.h" +#include "ctrlEnv/sys/mvCpuIf.h" + + + +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* DRAM bank presence encoding */ +#define BANK_PRESENT_CS0 0x1 +#define BANK_PRESENT_CS0_CS1 0x3 +#define BANK_PRESENT_CS0_CS2 0x5 +#define BANK_PRESENT_CS0_CS1_CS2 0x7 +#define BANK_PRESENT_CS0_CS2_CS3 0xd +#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf + +/* locals */ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); +#if defined(MV_INC_BOARD_DDIM) +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); +static MV_U32 sdramModeRegCalc(MV_U32 minCas); +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, + MV_U32 forcedCl); +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, + MV_U32 minCas, MV_U32 busClk); +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, + MV_U32 busClk); + +/******************************************************************************* +* mvDramIfDetect - Prepare DRAM interface configuration values. +* +* DESCRIPTION: +* This function implements the full DRAM detection and timing +* configuration for best system performance. +* Since this routine runs from a ROM device (Boot Flash), its stack +* resides on RAM, that might be the system DRAM. Changing DRAM +* configuration values while keeping vital data in DRAM is risky. That +* is why the function does not preform the configuration setting but +* prepare those in predefined 32bit registers (in this case IDMA +* registers are used) for other routine to perform the settings. +* The function will call for board DRAM SPD information for each DRAM +* chip select. The function will then analyze those SPD parameters of +* all DRAM banks in order to decide on DRAM configuration compatible +* for all DRAM banks. +* The function will set the CPU DRAM address decode registers. +* Note: This routine prepares values that will overide configuration of +* mvDramBasicAsmInit(). +* +* INPUT: +* forcedCl - Forced CAL Latency. If equal to zero, do not force. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvDramIfDetect(MV_U32 forcedCl) +{ + MV_U32 retVal = MV_OK; /* return value */ + MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; + MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; + MV_U8 minCas; + MV_DRAM_DEC_WIN dramDecWin; + + dramDecWin.addrWin.baseHigh = 0; + + busClk = mvBoardSysClkGet(); + + if (0 == busClk) + { + mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); + return MV_ERROR; + } + + /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ +#if defined(MV_INCLUDE_SDRAM_CS1) + for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) + mvCpuIfTargetWinEnable(i, MV_FALSE); +#endif + + /* we will use bank 0 as the representative of the all the DRAM banks, */ + /* since bank 0 must exist. */ + for(i = 0; i < MV_DRAM_MAX_CS; i++) + { + /* if Bank exist */ + if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) + { + /* check it isn't SDRAM */ + if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) + { + mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); + return MV_ERROR; + } + /* All banks must support registry in order to activate it */ + if(bankInfo[i].registeredAddrAndControlInputs != + bankInfo[0].registeredAddrAndControlInputs) + { + mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); + return MV_ERROR; + } + + /* Init the CPU window decode */ + /* Note that the size in Bank info is in MB units */ + /* Note that the Dimm width might be different then the device DRAM width */ + temp = MV_REG_READ(SDRAM_CONFIG_REG); + + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; + dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); + size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); + + /* We can not change DRAM window settings while excecuting */ + /* code from it. That is why we skip the DRAM CS[0], saving */ + /* it to the ROM configuration routine */ + if(i == SDRAM_CS0) + { + MV_U32 sizeToReg; + + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" + ,i); + return MV_BAD_PARAM; + } + + /* Size is located at upper 16 bits */ + sizeToReg <<= SCSR_SIZE_OFFS; + + /* enable it */ + sizeToReg |= SCSR_WIN_EN; + + MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); + } + else + { + dramDecWin.addrWin.baseLow = base; + dramDecWin.addrWin.size = size; + dramDecWin.enable = MV_TRUE; + + if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) + { + mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", + SDRAM_CS0 + i); + return MV_ERROR; + } + } + + base += size; + + /* update the suportedCasLatencies mask */ + bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; + + } + else + { + if( i == 0 ) /* bank 0 doesn't exist */ + { + mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); + return MV_ERROR; + } + else + { + DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); + bankInfo[i].size = 0; /* Mark this bank as non exist */ + } + } + } + + /* calculate minimum CAS */ + minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); + if (0 == minCas) + { + mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", + (busClk / 1000000)); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + minCas = DDR2_CL_4; /* Continue with this CAS */ + mvOsPrintf("Set default CAS latency 4\n"); + } + else + { + minCas = DDR1_CL_3; /* Continue with this CAS */ + mvOsPrintf("Set default CAS latency 3\n"); + } + } + + /* calc SDRAM_CONFIG_REG and save it to temp register */ + temp = sdramConfigRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG1, temp); + + /* calc SDRAM_MODE_REG and save it to temp register */ + temp = sdramModeRegCalc(minCas); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG2, temp); + + /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ + temp = sdramExtModeRegCalc(&bankInfo[0]); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG10, temp); + + /* calc D_UNIT_CONTROL_LOW and save it to temp register */ + temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG3, temp); + + /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ + temp = sdramAddrCtrlRegCalc(&bankInfo[0]); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG4, temp); + + /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ + temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG5, temp); + + /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ + temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + MV_REG_WRITE(DRAM_BUF_REG6, temp); + + /* Config DDR2 On Die Termination (ODT) registers */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + sdramDDr2OdtConfig(bankInfo); + } + + /* Note that DDR SDRAM Address/Control and Data pad calibration */ + /* settings is done in mvSdramIfConfig.s */ + + return retVal; +} + +/******************************************************************************* +* minCasCalc - Calculate the Minimum CAS latency which can be used. +* +* DESCRIPTION: +* Calculate the minimum CAS latency that can be used, base on the DRAM +* parameters and the SDRAM bus Clock freq. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - bank info parameters. +* +* OUTPUT: +* None +* +* RETURN: +* The minimum CAS Latency. The function returns 0 if max CAS latency +* supported by banks is incompatible with system bus clock frequancy. +* +*******************************************************************************/ +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, + MV_U32 forcedCl) +{ + MV_U32 count = 1, j; + MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ + MV_U32 startBit, stopBit; + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + + /* If we are asked to use the forced CAL */ + if (forcedCl) + { + mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), + (forcedCl % 10)); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + if (forcedCl == 30) + pBankInfo->suportedCasLatencies = 0x08; + else if (forcedCl == 40) + pBankInfo->suportedCasLatencies = 0x10; + else + { + mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", + (forcedCl / 10), (forcedCl % 10)); + pBankInfo->suportedCasLatencies = 0x10; + } + } + else + { + if (forcedCl == 15) + pBankInfo->suportedCasLatencies = 0x02; + else if (forcedCl == 20) + pBankInfo->suportedCasLatencies = 0x04; + else if (forcedCl == 25) + pBankInfo->suportedCasLatencies = 0x08; + else if (forcedCl == 30) + pBankInfo->suportedCasLatencies = 0x10; + else if (forcedCl == 40) + pBankInfo->suportedCasLatencies = 0x40; + else + { + mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", + (forcedCl / 10), (forcedCl % 10)); + pBankInfo->suportedCasLatencies = 0x10; + } + } + + return pBankInfo->suportedCasLatencies; + } + + /* go over the supported cas mask from Max Cas down and check if the */ + /* SysClk stands in its time requirments. */ + + + DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo->suportedCasLatencies,busClkPs )); + for(j = 7; j > 0; j--) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) + { + case 1: + if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", + pBankInfo->suportedCasLatencies )); + + /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ + /* SDRAM DDR2 controller supports CL 3 to 5 */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ + stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ + } + else + { + startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ + stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ + } + + for(j = startBit; j <= stopBit ; j++) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); + return (BIT0 << j); + } + } + + return 0; +} + +/******************************************************************************* +* sdramConfigRegCalc - Calculate sdram config register +* +* DESCRIPTION: Calculate sdram config register optimized value based +* on the bank info parameters. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram config reg value. +* +*******************************************************************************/ +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 sdramConfig = 0; + MV_U32 refreshPeriod; + + busClk /= 1000000; /* we work with busClk in MHz */ + + sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); + + /* figure out the memory refresh internal */ + switch (pBankInfo->refreshInterval & 0xf) + { + case 0x0: /* refresh period is 15.625 usec */ + refreshPeriod = 15625; + break; + case 0x1: /* refresh period is 3.9 usec */ + refreshPeriod = 3900; + break; + case 0x2: /* refresh period is 7.8 usec */ + refreshPeriod = 7800; + break; + case 0x3: /* refresh period is 31.3 usec */ + refreshPeriod = 31300; + break; + case 0x4: /* refresh period is 62.5 usec */ + refreshPeriod = 62500; + break; + case 0x5: /* refresh period is 125 usec */ + refreshPeriod = 125000; + break; + default: /* refresh period undefined */ + mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); + return -1; + } + + /* Now the refreshPeriod is in register format value */ + refreshPeriod = (busClk * refreshPeriod) / 1000; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", + refreshPeriod)); + + /* make sure the refresh value is only 14 bits */ + if(refreshPeriod > SDRAM_REFRESH_MAX) + { + refreshPeriod = SDRAM_REFRESH_MAX; + DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", + refreshPeriod)); + } + + /* Clear the refresh field */ + sdramConfig &= ~SDRAM_REFRESH_MASK; + + /* Set new value to refresh field */ + sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); + + /* registered DRAM ? */ + if ( pBankInfo->registeredAddrAndControlInputs ) + { + /* it's registered DRAM, so set the reg. DRAM bit */ + sdramConfig |= SDRAM_REGISTERED; + mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); + } + + /* set DDR SDRAM devices configuration */ + sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ + + switch (pBankInfo->sdramWidth) + { + case 8: /* memory is x8 */ + sdramConfig |= SDRAM_DCFG_X8_DEV; + DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); + break; + case 16: + sdramConfig |= SDRAM_DCFG_X16_DEV; + DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); + break; + default: /* memory width unsupported */ + mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); + return -1; + } + + /* Set static default settings */ + sdramConfig |= SDRAM_CONFIG_DV; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", + sdramConfig)); + + return sdramConfig; +} + +/******************************************************************************* +* sdramModeRegCalc - Calculate sdram mode register +* +* DESCRIPTION: Calculate sdram mode register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramModeRegCalc(MV_U32 minCas) +{ + MV_U32 sdramMode; + + sdramMode = MV_REG_READ(SDRAM_MODE_REG); + + /* Clear CAS Latency field */ + sdramMode &= ~SDRAM_CL_MASK; + + mvOsPrintf("DRAM CAS Latency "); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + switch (minCas) + { + case DDR2_CL_3: + sdramMode |= SDRAM_DDR2_CL_3; + mvOsPrintf("3.\n"); + break; + case DDR2_CL_4: + sdramMode |= SDRAM_DDR2_CL_4; + mvOsPrintf("4.\n"); + break; + case DDR2_CL_5: + sdramMode |= SDRAM_DDR2_CL_5; + mvOsPrintf("5.\n"); + break; + default: + mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); + return -1; + } + sdramMode |= DDR2_MODE_REG_DV; + } + else /* DDR1 */ + { + switch (minCas) + { + case DDR1_CL_1_5: + sdramMode |= SDRAM_DDR1_CL_1_5; + mvOsPrintf("1.5\n"); + break; + case DDR1_CL_2: + sdramMode |= SDRAM_DDR1_CL_2; + mvOsPrintf("2\n"); + break; + case DDR1_CL_2_5: + sdramMode |= SDRAM_DDR1_CL_2_5; + mvOsPrintf("2.5\n"); + break; + case DDR1_CL_3: + sdramMode |= SDRAM_DDR1_CL_3; + mvOsPrintf("3\n"); + break; + case DDR1_CL_4: + sdramMode |= SDRAM_DDR1_CL_4; + mvOsPrintf("4\n"); + break; + default: + mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); + return -1; + } + sdramMode |= DDR1_MODE_REG_DV; + } + + DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); + + return sdramMode; +} + +/******************************************************************************* +* sdramExtModeRegCalc - Calculate sdram Extended mode register +* +* DESCRIPTION: +* Return sdram Extended mode register value based +* on the bank info parameters and bank presence. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram Extended mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 populateBanks = 0; + int bankNum; + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + return DDR_SDRAM_EXT_MODE_CS0_DV; + + case(BANK_PRESENT_CS0_CS1): + return DDR_SDRAM_EXT_MODE_CS0_DV; + + case(BANK_PRESENT_CS0_CS2): + return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; + + case(BANK_PRESENT_CS0_CS1_CS2): + return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; + + case(BANK_PRESENT_CS0_CS2_CS3): + return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; + + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; + + default: + mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); + return -1; + } + } + return 0; +} + +/******************************************************************************* +* dunitCtrlLowRegCalc - Calculate sdram dunit control low register +* +* DESCRIPTION: Calculate sdram dunit control low register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control low reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) +{ + MV_U32 dunitCtrlLow; + + dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); + + /* Clear StBurstDel field */ + dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; + +#ifdef MV_88W8660 + /* Clear address/control output timing field */ + dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; +#endif /* MV_88W8660 */ + + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstDel bits [27:24] */ + /********-********-********-********-********-********* + * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * + *********-********-********-********-********-********* +Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * + *********-********-********-********-********-********* +Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * + *********-********-********-********-********-*********/ + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + switch (minCas) + { + case DDR2_CL_3: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR2_CL_4: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + break; + default: + mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", + minCas); + return -1; + } + } + else /* DDR1 */ + { + switch (minCas) + { + case DDR1_CL_1_5: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR1_CL_2: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR1_CL_2_5: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR1_CL_3: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; + break; + case DDR1_CL_4: + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; + else + dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; + break; + default: + mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", + minCas); + return -1; + } + + } + DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); + + return dunitCtrlLow; +} + +/******************************************************************************* +* sdramAddrCtrlRegCalc - Calculate sdram address control register +* +* DESCRIPTION: Calculate sdram address control register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram address control reg value. +* +*******************************************************************************/ +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 addrCtrl = 0; + + /* Set Address Control register static configuration bits */ + addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); + + /* Set address control default value */ + addrCtrl |= SDRAM_ADDR_CTRL_DV; + + /* Clear DSize field */ + addrCtrl &= ~SDRAM_DSIZE_MASK; + + /* Note that density is in MB units */ + switch (pBankInfo->deviceDensity) + { + case 128: /* 128 Mbit */ + DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); + addrCtrl |= SDRAM_DSIZE_128Mb; + break; + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb; + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb; + break; + default: + mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfo->deviceDensity); + return -1; + } + + /* SDRAM address control */ + DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); + + return addrCtrl; +} + +/******************************************************************************* +* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register +* +* DESCRIPTION: +* This function calculates sdram timing control low register +* optimized value based on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timinf control low reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, + MV_U32 minCas, MV_U32 busClk) +{ + MV_U32 tRp = 0; + MV_U32 tRrd = 0; + MV_U32 tRcd = 0; + MV_U32 tRas = 0; + MV_U32 tWr = 0; + MV_U32 tWtr = 0; + MV_U32 tRtp = 0; + + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); + tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); + tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); + tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ + /* by shifting the data two bits right. */ + tRp = tRp >> 2; /* For example 0x50 -> 20ns */ + tRrd = tRrd >> 2; + tRcd = tRcd >> 2; + + /* Extract clock cycles from time parameter. We need to round up */ + tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); + /* Micron work around for 133MHz */ + if (busClk == 133) + tRp += 1; + DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); + tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRrd = 2 */ + if (tRrd < 2) + tRrd = 2; + DB(mvOsPrintf("tRrd = %d ", tRrd)); + tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRcd = %d ", tRcd)); + tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRas = %d ", tRas)); + + /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); + tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); + tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ + /* part by shifting the data two bits right. */ + tWr = tWr >> 2; /* For example 0x50 -> 20ns */ + tWtr = tWtr >> 2; + tRtp = tRtp >> 2; + + /* Extract clock cycles from time parameter. We need to round up */ + tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); + DB(mvOsPrintf("tWr = %d ", tWr)); + tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tWtr = 2 */ + if (tWtr < 2) + tWtr = 2; + DB(mvOsPrintf("tWtr = %d ", tWtr)); + tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRtp = 2 */ + if (tRtp < 2) + tRtp = 2; + DB(mvOsPrintf("tRtp = %d ", tRtp)); + } + else + { + tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); + + if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) + { + tWtr = 2; + } + else + { + tWtr = 1; + } + + tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ + } + + DB(mvOsPrintf("tWtr = %d\n", tWtr)); + + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + return (((tRp - 1) << SDRAM_TRP_OFFS) | + ((tRrd - 1) << SDRAM_TRRD_OFFS) | + ((tRcd - 1) << SDRAM_TRCD_OFFS) | + ((tRas - 1) << SDRAM_TRAS_OFFS) | + ((tWr - 1) << SDRAM_TWR_OFFS) | + ((tWtr - 1) << SDRAM_TWTR_OFFS) | + ((tRtp - 1) << SDRAM_TRTP_OFFS)); +} + +/******************************************************************************* +* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register +* +* DESCRIPTION: +* This function calculates sdram timing control high register +* optimized value based on the bank info parameters and the bus clock. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timinf control high reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, + MV_U32 busClk) +{ + MV_U32 tRfc; + MV_U32 timeNs = 0; + int bankNum; + MV_U32 sdramTw2wCyc = 0; + + busClk = busClk / 1000000; /* In MHz */ + + /* tRfc is different for DDR1 and DDR2. */ + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) + { + MV_U32 bankNum; + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); + } + else + { + if (pBankInfo[0].deviceDensity == _1G) + { + timeNs = SDRAM_TRFC_1G; + } + else + { + if (200 == busClk) + { + timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; + } + else + { + timeNs = SDRAM_TRFC_64_512M; + } + } + } + + tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); + + DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); + + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + sdramTw2wCyc++; + } + + /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ + if (sdramTw2wCyc > 1) + sdramTw2wCyc = 1; + else + sdramTw2wCyc = 0; + + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | + ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | + ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | + (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | + (sdramTw2wCyc << SDRAM_TW2W_OFFS)); + +} + +/******************************************************************************* +* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. +* +* DESCRIPTION: +* This function config DDR2 On Die Termination (ODT) registers. +* ODT configuration is done according to DIMM presence: +* +* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode +* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 +* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 +* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 +* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 +* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 +* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 +* +* INPUT: +* pBankInfo - bank info parameters. +* +* OUTPUT: +* None +* +* RETURN: +* None +*******************************************************************************/ +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 populateBanks = 0; + MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; + int bankNum; + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; + break; + case(BANK_PRESENT_CS0_CS1): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; + break; + case(BANK_PRESENT_CS0_CS2): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; + break; + case(BANK_PRESENT_CS0_CS1_CS2): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; + break; + case(BANK_PRESENT_CS0_CS2_CS3): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; + break; + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; + break; + default: + mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); + return; + } + MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); + MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); + MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); + return; +} +#endif /* defined(MV_INC_BOARD_DDIM) */ + +/******************************************************************************* +* mvDramIfWinSet - Set DRAM interface address decode window +* +* DESCRIPTION: +* This function sets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* pAddrDecWin - SDRAM address window structure. +* +* OUTPUT: +* None +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg=0,sizeReg=0; + MV_U32 baseToReg=0 , sizeToReg=0; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); + return MV_BAD_PARAM; + } + + /* Check if the requested window overlaps with current enabled windows */ + if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) + { + mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); + return MV_BAD_PARAM; + } + + /* check if address is aligned to the size */ + if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) + { + mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ + "\nAddress 0x%08x is unaligned to size 0x%x.\n", + target, + pAddrDecWin->addrWin.baseLow, + pAddrDecWin->addrWin.size); + return MV_ERROR; + } + + /* read base register*/ + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); + + /* read size register */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); + + /* BaseLow[31:16] => base register [31:16] */ + baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; + + /* Write to address decode Base Address Register */ + baseReg &= ~SCBAR_BASE_MASK; + baseReg |= baseToReg; + + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); + + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); + return MV_BAD_PARAM; + } + + /* set size */ + sizeReg &= ~SCSR_SIZE_MASK; + /* Size is located at upper 16 bits */ + sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); + + /* enable/Disable */ + if (MV_TRUE == pAddrDecWin->enable) + { + sizeReg |= SCSR_WIN_EN; + } + else + { + sizeReg &= ~SCSR_WIN_EN; + } + + /* 3) Write to address decode Base Address Register */ + MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); + + /* Write to address decode Size Register */ + MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinGet - Get DRAM interface address decode window +* +* DESCRIPTION: +* This function gets DRAM interface address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* pAddrDecWin - SDRAM address window structure. +* +* RETURN: +* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK +* otherwise. +*******************************************************************************/ +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) +{ + MV_U32 baseReg,sizeReg; + MV_U32 sizeRegVal; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Read base and size registers */ + sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); + baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); + + sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; + + pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, + SCSR_SIZE_ALIGNMENT); + + /* Check if ctrlRegToSize returned OK */ + if (-1 == pAddrDecWin->addrWin.size) + { + mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); + return MV_ERROR; + } + + /* Extract base address */ + /* Base register [31:16] ==> baseLow[31:16] */ + pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; + + pAddrDecWin->addrWin.baseHigh = 0; + + + if (sizeReg & SCSR_WIN_EN) + { + pAddrDecWin->enable = MV_TRUE; + } + else + { + pAddrDecWin->enable = MV_FALSE; + } + + return MV_OK; +} +/******************************************************************************* +* mvDramIfWinEnable - Enable/Disable SDRAM address decode window +* +* DESCRIPTION: +* This function enable/Disable SDRAM address decode window. +* +* INPUT: +* target - System target. Use only SDRAM targets. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_ERROR in case function parameter are invalid, MV_OK otherewise. +* +*******************************************************************************/ +MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(target)) + { + mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); + return MV_ERROR; + } + + if (enable == MV_TRUE) + { /* First check for overlap with other enabled windows */ + if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) + { + mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", + target); + return MV_ERROR; + } + /* Check for overlapping */ + if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) + { + /* No Overlap. Enable address decode winNum window */ + MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); + } + else + { /* Overlap detected */ + mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", + target); + return MV_ERROR; + } + } + else + { /* Disable address decode winNum window */ + MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); + } + + return MV_OK; +} + +/******************************************************************************* +* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window +* +* DESCRIPTION: +* This function scan each SDRAM address decode window to test if it +* overlapps the given address windoow +* +* INPUT: +* target - SDRAM target where the function skips checking. +* pAddrDecWin - The tested address window for overlapping with +* SDRAM windows. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if the given address window overlaps any enabled address +* decode map, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) +{ + MV_TARGET targetNum; + MV_DRAM_DEC_WIN addrDecWin; + + for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) + { + /* don't check our winNum or illegal targets */ + if (targetNum == target) + { + continue; + } + + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return MV_ERROR; + } + + /* Do not check disabled windows */ + if (MV_FALSE == addrDecWin.enable) + { + continue; + } + + if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) + { + mvOsPrintf( + "sdramIfWinOverlap: Required target %d overlap winNum %d\n", + target, targetNum); + return MV_TRUE; + } + } + + return MV_FALSE; +} + +/******************************************************************************* +* mvDramIfBankSizeGet - Get DRAM interface bank size. +* +* DESCRIPTION: +* This function returns the size of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled the function return '0'. In case +* or paramter is invalid, the function returns -1. +* +*******************************************************************************/ +MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(bankNum)) + { + mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); + return -1; + } + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return -1; + } + + if (MV_TRUE == addrDecWin.enable) + { + return addrDecWin.addrWin.size; + } + else + { + return 0; + } +} + + +/******************************************************************************* +* mvDramIfSizeGet - Get DRAM interface total size. +* +* DESCRIPTION: +* This function get the DRAM total size. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM total size. In case or paramter is invalid, the function +* returns -1. +* +*******************************************************************************/ +MV_32 mvDramIfSizeGet(MV_VOID) +{ + MV_U32 totalSize = 0, bankSize = 0, bankNum; + + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + bankSize = mvDramIfBankSizeGet(bankNum); + + if (-1 == bankSize) + { + mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); + return -1; + } + else + { + totalSize += bankSize; + } + } + + DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); + + return totalSize; +} + +/******************************************************************************* +* mvDramIfBankBaseGet - Get DRAM interface bank base. +* +* DESCRIPTION: +* This function returns the 32 bit base address of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled or paramter is invalid, the +* function returns -1. +* +*******************************************************************************/ +MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) +{ + MV_DRAM_DEC_WIN addrDecWin; + + /* Check parameters */ + if (!MV_TARGET_IS_DRAM(bankNum)) + { + mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); + return -1; + } + /* Get window parameters */ + if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) + { + mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); + return -1; + } + + if (MV_TRUE == addrDecWin.enable) + { + return addrDecWin.addrWin.baseLow; + } + else + { + return -1; + } +} + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h new file mode 100644 index 0000000..8bfa3e8 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h @@ -0,0 +1,179 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfh +#define __INCmvDramIfh + +/* includes */ +#include "ddr1_2/mvDramIfRegs.h" +#include "ddr1_2/mvDramIfConfig.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* defines */ +/* DRAM Timing parameters */ +#define SDRAM_TWR 15 /* ns tWr */ +#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ +#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ +#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ +#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ +#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ + +/* typedefs */ + +/* enumeration for memory types */ +typedef enum _mvMemoryType +{ + MEM_TYPE_SDRAM, + MEM_TYPE_DDR1, + MEM_TYPE_DDR2 +}MV_MEMORY_TYPE; + +/* enumeration for DDR1 supported CAS Latencies */ +typedef enum _mvDimmDdr1Cas +{ + DDR1_CL_1_5 = 0x02, + DDR1_CL_2 = 0x04, + DDR1_CL_2_5 = 0x08, + DDR1_CL_3 = 0x10, + DDR1_CL_4 = 0x40, + DDR1_CL_FAULT +} MV_DIMM_DDR1_CAS; + +/* enumeration for DDR2 supported CAS Latencies */ +typedef enum _mvDimmDdr2Cas +{ + DDR2_CL_3 = 0x08, + DDR2_CL_4 = 0x10, + DDR2_CL_5 = 0x20, + DDR2_CL_FAULT +} MV_DIMM_DDR2_CAS; + + +typedef struct _mvDramBankInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ + MV_U32 numberOfDevices; + + /* DIMM attributes (MV_TRUE for yes) */ + MV_BOOL registeredAddrAndControlInputs; + +}MV_DRAM_BANK_INFO; + +/* This structure describes CPU interface address decode window */ +typedef struct _mvDramIfDecWin +{ + MV_ADDR_WIN addrWin; /* An address window*/ + MV_BOOL enable; /* Address decode window is enabled/disabled */ +}MV_DRAM_DEC_WIN; + +#include "ddr1_2/mvDram.h" + +/* mvDramIf.h API list */ +MV_VOID mvDramIfBasicAsmInit(MV_VOID); +MV_STATUS mvDramIfDetect(MV_U32 forcedCl); +MV_VOID _mvDramIfConfig(MV_VOID); + +MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); +MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); +MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); +MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); +MV_32 mvDramIfSizeGet(MV_VOID); + +#if 0 +MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); +MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); +#endif + +#endif /* __INCmvDramIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S new file mode 100644 index 0000000..f2a9365 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S @@ -0,0 +1,988 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define MV_ASMLANGUAGE +#include "mvSysHwConfig.h" +#include "mvOsAsm.h" +#include "mvBoardEnvSpec.h" +#include "mvCpuIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvDramIfRegs.h" +#include "pex/mvPexRegs.h" +#include "pci/mvPciRegs.h" +#include "mvCtrlEnvSpec.h" +#include "mvCtrlEnvAsm.h" +#include "cpu/mvCpuArm.h" +#include "mvCommon.h" + +/* defines */ + +#if !defined(MV_INC_BOARD_DDIM) +.globl dramBoot1 +dramBoot1: + .word 0 + +/****************************************************************************** +* +* +* +* +*******************************************************************************/ +#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) + +/* PEX_PCI and PRPMC boards 256 MB*/ +#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 +#define STATIC_SDRAM_CONFIG 0x03248400 +#define STATIC_SDRAM_MODE 0x62 +#define STATIC_DUNIT_CTRL_LOW 0x4041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x0 + +#elif defined(DB_FPGA) + +/* FPGA DC boards 256 MB*/ +#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 +#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ +#define STATIC_SDRAM_MODE 0x22 +#define STATIC_DUNIT_CTRL_LOW 0x03041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x1 + +#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) + +/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ +#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 +#define STATIC_SDRAM_CONFIG 0x03158400 +#define STATIC_SDRAM_MODE 0x452 +#define STATIC_DUNIT_CTRL_LOW 0x06041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 +#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 +#define STATIC_SDRAM_EXT_MODE 0x00000440 + + +#elif defined(RD_88F6183AP) + +/* DDR2 1 devices 512Mbit by 16 bit */ +#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 +#define STATIC_SDRAM_CONFIG 0x1f154400 +#define STATIC_SDRAM_MODE 0x432 +#define STATIC_DUNIT_CTRL_LOW 0x04041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 +#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 +#define STATIC_SDRAM_EXT_MODE 0x00000440 + +/* 6082L MARVELL DIMM */ +#elif defined(DB_88F6082LBP) +#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 +#define STATIC_SDRAM_CONFIG 0x7f158400 +#define STATIC_SDRAM_MODE 0x432 +#define STATIC_DUNIT_CTRL_LOW 0x04041040 +#define STATIC_SDRAM_ADDR_CTRL 0x00000020 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 +#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 +#define STATIC_SDRAM_EXT_MODE 0x00000440 + +#elif defined(RD_88W8660_AP82S) + +/* Shark RD */ + +#if defined(MV_DRAM_32M) +#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x00000010 +#elif defined(MV_DRAM_16M) + +#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x00000000 + +#else +#error "NO DDR size selected" +#endif + +#define STATIC_SDRAM_CONFIG 0x03144400 +#define STATIC_SDRAM_MODE 0x62 +#define STATIC_DUNIT_CTRL_LOW 0x4041000 + +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x0 + +#elif defined(RD_88W8660) + +/* Shark RD */ +#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 +#define STATIC_SDRAM_CONFIG 0x03144400 +#define STATIC_SDRAM_MODE 0x62 +#define STATIC_DUNIT_CTRL_LOW 0x4041000 +#define STATIC_SDRAM_ADDR_CTRL 0x00000010 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x0 + +#else /* NAS */ + + +#if defined(RD_88F5182) + +#if defined(MV_88F5082) +#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x20 +#else +#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x20 +#endif + +#elif defined(RD_88F5182_3) + +#if defined(MV_88F5082) +#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x20 +#else +#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x20 +#endif + +#else + +#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 +#define STATIC_SDRAM_ADDR_CTRL 0x0 + +#endif + +#if defined(MV_88F5082) +#define STATIC_SDRAM_CONFIG 0x3144400 +#else +#define STATIC_SDRAM_CONFIG 0x3148400 +#endif +#define STATIC_SDRAM_MODE 0x62 +#define STATIC_DUNIT_CTRL_LOW 0x4041000 +#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 +#define STATIC_SDRAM_TIME_CTRL_HI 0x40c +#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 +#define STATIC_SDRAM_ODT_CTRL_HI 0x0 +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 +#define STATIC_SDRAM_EXT_MODE 0x0 + +#endif + + .globl _mvDramIfStaticInit +_mvDramIfStaticInit: + + mov r11, LR /* Save link register */ + mov r10, r2 + + /* If we boot from NAND jump to DRAM sddress */ + + mov r5, #1 + ldr r6, =dramBoot1 + str r5, [r6] /* We started executing from DRAM */ + + ldr r6, dramBoot1 + cmp r6, #0 + bne 1f + + + /* set all dram windows to 0 */ + mov r6, #0 + MV_REG_WRITE_ASM(r6, r5, 0x1504) + MV_REG_WRITE_ASM(r6, r5, 0x150c) + MV_REG_WRITE_ASM(r6, r5, 0x1514) + MV_REG_WRITE_ASM(r6, r5, 0x151c) + + /* set all dram configuration in temp registers */ + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) + ldr r6, = STATIC_SDRAM_CONFIG + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) + ldr r6, = STATIC_SDRAM_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) + ldr r6, = STATIC_DUNIT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) + ldr r6, = STATIC_SDRAM_ADDR_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) + ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) + ldr r6, = STATIC_SDRAM_TIME_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) + ldr r6, = STATIC_SDRAM_ODT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) + ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) + ldr r6, = STATIC_SDRAM_EXT_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) + + mov sp, #0 + bl _mvDramIfConfig +1: + mov r2, r10 + mov PC, r11 /* r11 is saved link register */ + +#else /* #if !defined(MV_INC_BOARD_DDIM) */ + +.globl dramBoot1 +dramBoot1: + .word 0 + +/******************************************************************************* +* mvDramIfBasicInit - Basic initialization of DRAM interface +* +* DESCRIPTION: +* The function will initialize the DRAM for basic usage. The function +* will use the TWSI assembly API to extract DIMM parameters according +* to which DRAM interface will be initialized. +* The function referes to the following DRAM parameters: +* 1) DIMM is registered or not. +* 2) DIMM width detection. +* 3) DIMM density. +* +* INPUT: +* r3 - required size for initial DRAM. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* Note: +* r4 holds I2C EEPROM address +* r5 holds SDRAM register base address +* r7 holds returned values +* r8 holds SDRAM various configuration registers value. +* r11 holds return function address. +*******************************************************************************/ +/* Setting the offsets of the I2C registers */ +#define NUM_OF_ROWS_OFFSET 3 +#define NUM_OF_COLS_OFFSET 4 +#define NUM_OF_RANKS 5 +#define SDRAM_WIDTH_OFFSET 13 +#define NUM_OF_BANKS_OFFSET 17 +#define SUPPORTED_CL_OFFSET 18 +#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ +#define SDRAM_MODULES_ATTR_OFFSET 21 + +#define DRAM_DEV_DENSITY_128M 0x080 +#define DRAM_DEV_DENSITY_256M 0x100 +#define DRAM_DEV_DENSITY_512M 0x200 + .globl _mvDramIfBasicInit + .extern _i2cInit + +_mvDramIfBasicInit: + + mov r11, LR /* Save link register */ + + mov r5, #1 + ldr r8, =dramBoot1 + str r5, [r8] /* We started executing from DRAM */ + + /* If we boot from NAND jump to DRAM sddress */ + ldr r8, dramBoot1 + cmp r8, #0 + movne pc, r11 + + + + bl _i2cInit /* Initialize TWSI master */ + + /* Get default SDRAM Config values */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + bic r8, r8, #SDRAM_DCFG_MASK + + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r4, r5); + + /* Return if OrionN */ + ldr r5, =MV_5180_DEV_ID + cmp r4, r5 + beq cat_through_end + + /* Return if Orion1 */ + ldr r5, =MV_5181_DEV_ID + cmp r4, r5 + beq cat_through_end + + /* Return if Nas */ + ldr r5, =MV_5182_DEV_ID + cmp r4, r5 + beq cat_through_end + + /* Return if Shark */ + ldr r5, =MV_8660_DEV_ID + cmp r4, r5 + beq cat_through_end + + /* goto calcConfigReg if bigger than Orion2*/ + ldr r5, =MV_5281_DEV_ID + cmp r4, r5 + bne cat_through + +cat_through: + /* set cat through - for better performance - in orion2 b0 and higher*/ + orr r8, r8, #SDRAM_CATTHR_EN + +cat_through_end: + + + /* Get registered/non registered info from DIMM */ + bl _is_Registered + beq nonRegistered + +setRegistered: + orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ + +nonRegistered: + /* Get SDRAM width */ + bl _get_width + + orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ + cmp r7, #16 + beq setConfigReg + + orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ + cmp r7, #8 + beq setConfigReg + + /* This is an error. return */ + b exit_ddrAutoConfig + +setConfigReg: + mov r8, r6 + ldr r6, =SDRAM_CONFIG_DV + orr r8, r8, r6 /* Add default settings */ + mov r6, r8 /* Do not swap r8 content */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) + + /* Set maximum CL supported by DIMM */ + bl _get_CAL + + /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ + clz r6, r7 + rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ + + /* Check the DDR version */ + tst r8, #SDRAM_DTYPE_DDR2 + bne casDdr2 + +casDdr1: + ldr r7, =3 /* stBurstDel field value */ + ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ + cmp r6, #1 /* If CL = 1.5 break */ + beq setModeReg + + ldr r7, =3 /* stBurstDel field value */ + ldr r8, =0x22 /* Assuming MAX CL = 2 */ + cmp r6, #2 /* If CL = 2 break */ + beq setModeReg + + ldr r7, =4 /* stBurstDel field value */ + ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ + cmp r6, #3 /* If CL = 2.5 break */ + beq setModeReg + + ldr r7, =4 /* stBurstDel field value */ + ldr r8, =0x32 /* Assuming MAX CL = 3 */ + cmp r6, #4 /* If CL = 3 break */ + beq setModeReg + + ldr r7, =5 /* stBurstDel field value */ + ldr r8, =0x42 /* Assuming MAX CL = 4 */ + cmp r6, #6 /* If CL = 4 break */ + b setModeReg + + b exit_ddrAutoConfig /* This is an error !! */ + +casDdr2: + ldr r7, =4 /* stBurstDel field value */ + ldr r8, =0x32 /* Assuming MAX CL = 3 */ + cmp r6, #3 /* If CL = 3 break */ + beq casDdr2Cont + + ldr r7, =5 /* stBurstDel field value */ + ldr r8, =0x42 /* Assuming MAX CL = 4 */ + cmp r6, #4 /* If CL = 4 break */ + beq casDdr2Cont + + /* CL 5 currently unsupported. We use CL 4 instead */ + ldr r7, =5 /* stBurstDel field value */ + ldr r8, =0x42 /* Assuming MAX CL = 5 */ + cmp r6, #5 /* If CL = 5 break */ + beq casDdr2Cont + + b exit_ddrAutoConfig /* This is an error !! */ +casDdr2Cont: + /* Write recovery for auto-precharge relevant only in DDR2 */ + orr r8, r8, #0x400 /* Default value */ + +setModeReg: + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to it's new value. */ + + /* write 'nop' to SDRAM operation */ + mov r6, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll1: + ldr r6, [r5] + cmp r6, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll1 + + /* Now its safe to write new value to SDRAM Mode register */ + MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) + + /* Make the Dunit write the DRAM its new mode */ + mov r6, #0x3 /* Mode Register Set command */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll2: + ldr r6, [r5] + cmp r6, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll2 + + /* Set Dunit control register according to max CL detected */ + /* If we use registered DIMM, add 1 to stBurstDel */ + MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) + tst r6, #SDRAM_REGISTERED + beq setDunitReg + add r7, r7, #1 + +setDunitReg: + ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV + orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + + + /* DIMM density configuration*/ + /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ +Density: + bl _getDensity + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + mov r6, #0x00 + cmp r8, #DRAM_DEV_DENSITY_128M + beq densCont + + mov r6, #0x10 + cmp r8, #DRAM_DEV_DENSITY_256M + beq densCont + + mov r6, #0x20 + cmp r8, #DRAM_DEV_DENSITY_512M + beq densCont + + /* This is an error. return */ + b exit_ddrAutoConfig + +densCont: + MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) + + /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + tst r8, #SDRAM_DTYPE_DDR2 + beq _extModeODTEnd + + + /* Set DDR Extended Mode register for working with CS[0] */ + /* write 'nop' to SDRAM operation */ + mov r6, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll3: + ldr r6, [r5] + cmp r6, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll3 + + /* Now its safe to write new value to SDRAM Extended Mode register */ + ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) + + /* Make the Dunit write the DRAM its new extended mode */ + mov r6, #0x4 /* Extended Mode Register Set command */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll4: + ldr r6, [r5] + cmp r6, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll4 + + /* ODT configuration is done for single bank CS[0] only */ + /* Config DDR2 On Die Termination (ODT) registers */ + ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV + MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) + + ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV + MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + + ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV + MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) + + + /* we will check what device we are running and perform + Initialization according to device value */ + +_extModeODTEnd: + + /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ + /* Does Not Work for Address/Control and Data Pads. */ + /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r6, r5); + /* Read device revision */ + MV_CTRL_REV_GET_ASM(r8, r5); + + /* Continue if OrionN */ + ldr r5, =MV_5180_DEV_ID + cmp r6, r5 + bne 1f + b glMem2End +1: + + /* Continue if Orion1 and device revision B1 */ + ldr r5, =MV_5181_DEV_ID + cmp r6, r5 + bne 1f + + cmp r8, #MV_5181_B1_REV + bge glMem2End + b glMem2Start +1: + + /* Orion NAS */ + ldr r5, =MV_5182_DEV_ID + cmp r6, r5 + beq glMem2Start + + /* Orion Shark */ + ldr r5, =MV_8660_DEV_ID + cmp r6, r5 + beq glMem2Start + + b glMem2End + +glMem2Start: + + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + /* Set Bit [31] to make the register writable */ + orr r8, r6, #SDRAM_WR_EN + + MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ + bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ + bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ + bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ + + /* Get the final N locked value of driving strength [22:17] */ + mov r5, r6 + mov r5, r5, LSL #9 + mov r5, r5, LSR #26 /* r5[5:0] = r6[22:17] */ + orr r5, r5, r5, LSL #6 /* r5[11:6] = r5[5:0] */ + + /* Write to both bits [5:0] and bits [11:6] */ + orr r6, r6, r5 + + MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + + /* Set Bit [31] to make the register writable */ + orr r8, r6, #SDRAM_WR_EN + + MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) + + bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ + bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ + bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ + bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ + + /* Get the final N locked value of driving strength [22:17] */ + mov r5, r6 + mov r5, r5, LSL #9 + mov r5, r5, LSR #26 + orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17] */ + + /* Write to both bits [5:0] and bits [11:6] */ + orr r6, r6, r5 + + MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + +glMem2End: + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + + /* Get SDRAM Config value */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + + /* Get DIMM type */ + tst r8, #SDRAM_DTYPE_DDR2 + beq ddr1StrengthVal + +ddr2StrengthVal: + ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV + ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV + b setDrvStrength +ddr1StrengthVal: + ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV + ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV + +setDrvStrength: + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ + + MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + HTOLL(r6,r5) + + bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ + bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK + orr r6, r4, r6 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + + orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ + + MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + HTOLL(r6,r5) + + bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ + bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK + orr r6, r8, r6 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) + + + /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ + /* Get the "sample on reset" register for the DDR frequancy */ + +#if defined(MV_RUN_FROM_FLASH) + /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ + ldr r7, = _cpuARMDDRCLK + ldr r4, =_start + ldr r4, [r4] + sub r7, r7, r4 + ldr r4, = Lrom_start_of_data + ldr r4, [r4] + add r7, r4, r7 +#else + /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ + ldr r7, = _cpuARMDDRCLK + ldr r4, =_start + sub r7, r7, r4 + add r7, r7, #CFG_MONITOR_BASE +#endif + /* Get the "sample on reset" register for the DDR frequancy */ + MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) + ldr r5, =MSAR_ARMDDRCLCK_MASK + and r5, r4, r5 +#if 0 /* YOTAM TO BE FIX */ + mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS +#endif + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r6, r8); + + /* Continue if TC90 */ + ldr r8, =MV_1281_DEV_ID + cmp r6, r6 + beq armClkMsb + + /* Continue if Orion2 */ + ldr r8, =MV_5281_DEV_ID + cmp r6, r8 +#if 0 /* YOTAM TO BE FIX */ + bne 1f +#endif + +armClkMsb: +#if 0 /* YOTAM TO BE FIX */ + tst r4, #MSAR_ARMDDRCLCK_H_MASK + beq 1f + orr r5, r5, #BIT4 +1: + ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE + mul r5, r4, r5 + add r7, r7, r5 + add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF + ldr r5, [r7] +#endif + + /* Get SDRAM Config value */ + MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) + + /* Get DIMM type */ + tst r8, #SDRAM_DTYPE_DDR2 + beq ddr1FtdllVal + +ddr2FtdllVal: + ldr r4, =FTDLL_DDR2_250MHZ + ldr r7, =_250MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_200MHZ + ldr r7, =_200MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_166MHZ + ldr r7, =_166MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_133MHZ + b setFtdllReg + +ddr1FtdllVal: + ldr r4, =FTDLL_DDR1_200MHZ + ldr r7, =_200MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR1_166MHZ + ldr r7, =_166MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR1_133MHZ + ldr r7, =_133MHz + cmp r5, r7 + beq setFtdllReg + ldr r4, =0 + +setFtdllReg: + +#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) + MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) + orr r8, r8, r4 + MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) + bic r8, r8, #1 + MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) +#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ + + +setTimingReg: + /* Set default Timing parameters */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + tst r8, #SDRAM_DTYPE_DDR2 + bne ddr2TimeParam + +ddr1TimeParam: + ldr r6, =DDR1_TIMING_LOW_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) + ldr r6, =DDR1_TIMING_HIGH_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) + b timeParamDone + +ddr2TimeParam: + ldr r6, =DDR2_TIMING_LOW_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) + ldr r6, =DDR2_TIMING_HIGH_DV + MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) + +timeParamDone: + /* Open CS[0] window to requested size and enable it. Disable other */ + /* windows */ + ldr r6, =SCBAR_BASE_MASK + sub r3, r3, #1 + and r3, r3, r6 + orr r3, r3, #1 /* Enable bank */ + MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) + ldr r6, =0 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) + +exit_ddrAutoConfig: + mov PC, r11 /* r11 is saved link register */ + + +/***************************************************************************************/ +/* r4 holds I2C EEPROM address + * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value + * r8 holds SDRAM various configuration registers value. + * r13 holds Link register + */ +/**************************/ +_getDensity: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ + bl _i2cRead + mov r8, r7 /* r8 save number of rows */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ + bl _i2cRead + add r8, r8, r7 /* r8 = number of rows + number of col */ + + mov r7, #0x1 + mov r8, r7, LSL r8 /* r8 = (1 << r8) */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ + bl _i2cRead + mul r8, r7, r8 + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ + bl _i2cRead + mul r7, r8, r7 + + mov PC, r13 + +/**************************/ +_get_width: + mov r13, LR /* Save link register */ + + /* Get SDRAM width (SPD offset 13) */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_WIDTH_OFFSET + bl _i2cRead /* result in r7 */ + + mov PC, r13 + +/**************************/ +_get_CAL: + mov r13, LR /* Save link register */ + + /* Set maximum CL supported by DIMM */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ + bl _i2cRead + + mov PC, r13 + +/**************************/ +/* R8 - sdram configuration register. + * Return value in flag if no-registered then Z-flag is set + */ +_is_Registered: + mov r13, LR /* Save link register */ + + /* Get registered/non registered info from DIMM */ + tst r8, #SDRAM_DTYPE_DDR2 + bne regDdr2 + +regDdr1: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_MODULES_ATTR_OFFSET + bl _i2cRead /* result in r7 */ + tst r7, #0x2 + b exit +regDdr2: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_INFO_OFFSET + bl _i2cRead /* result in r7 */ + tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ + /* or Mini-RDIMM (0x10) */ +exit: + mov PC, r13 + + +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S new file mode 100644 index 0000000..e34ebbf --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S @@ -0,0 +1,668 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvDramIfBasicAsm.s +* +* DESCRIPTION: +* Memory full detection and best timing configuration is done in +* C code. C runtime environment requires a stack. This module API +* initialize DRAM interface chip select 0 for basic functionality for +* the use of stack. +* The module API assumes DRAM information is stored in I2C EEPROM reside +* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM +* internal data structure is assumed to be orgenzied in common DRAM +* vendor SPD structure. +* NOTE: DFCDL values are assumed to be already initialized prior to +* this module API activity. +* +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvSysHwConfig.h" +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvCpuIfRegs.h" +#include "pex/mvPexRegs.h" +#include "pci/mvPciRegs.h" +#include "mvCtrlEnvSpec.h" +#include "mvCtrlEnvAsm.h" +#include "cpu/mvCpuArm.h" +#include "mvCommon.h" + +/* defines */ + +/* locals */ +.data +.globl _mvDramIfConfig + +.text + +/******************************************************************************* +* _mvDramIfConfig - Basic DRAM interface initialization. +* +* DESCRIPTION: +* The function will initialize the following DRAM parameters using the +* values prepared by mvDramIfDetect routine. Values are located +* in predefined registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ + +_mvDramIfConfig: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s +save_on_stack: + stmdb sp!, {r1, r2, r3, r4, r7, r11} +no_stack_s: + + /* 1) Write to SDRAM coniguration register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) + str r4, [r1] + + /* 2) Write Dunit control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) + str r4, [r1] + + /* 3) Write SDRAM address control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) + str r4, [r1] + + /* 4) Write SDRAM bank 0 size register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0)) + str r4, [r1] + + /* 5) Write SDRAM open pages control register */ + ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) + ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV + str r4, [r1] + + /* 6) Write SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) + str r4, [r1] + + /* 7) Write SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) + str r4, [r1] + + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to it’s new value. */ + + /* 8.1 write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) + + /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll1: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll1 + + /* 8.3 Now its safe to write new value to SDRAM Mode register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) + str r4, [r1] + + /* 8.4 Make the Dunit write the DRAM its new mode */ + mov r4, #0x3 /* Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll2: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll2 + +#ifndef DB_FPGA + /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ + MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG) + tst r4, #SDRAM_DTYPE_DDR2 + beq _extModeODTEnd +#endif /* DB_FPGA */ + + /* 9) Write SDRAM Extended mode register This operation should be */ + /* done for each memory bank */ + /* write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll3: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll3 + + /* Now its safe to write new value to SDRAM Extended Mode register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) + str r4, [r1] + + /* Go over each of the Banks */ + ldr r3, =0 /* r3 = DRAM bank Num */ + +extModeLoop: + /* Set the SDRAM Operation Control to each of the DRAM banks */ + mov r2, r3 /* Do not swap the bank counter value */ + MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG) + + /* Make the Dunit write the DRAM its new mode */ + mov r4, #0x4 /* Extended Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll4: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll4 +#ifndef DB_FPGA + add r3, r3, #1 + cmp r3, #4 /* 4 = Number of banks */ + bne extModeLoop + +extModeEnd: + /* Config DDR2 On Die Termination (ODT) registers */ + /* Write SDRAM DDR2 ODT control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) + str r4, [r1] + + /* Write SDRAM DDR2 ODT control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) + str r4, [r1] + + /* Write SDRAM DDR2 Dunit ODT control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) + str r4, [r1] + +#endif /* DB_FPGA */ +_extModeODTEnd: +#ifndef DB_FPGA + /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ + /* Does Not Work for Address/Control and Data Pads. */ + /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r3, r1); + /* Read device revision */ + MV_CTRL_REV_GET_ASM(r2, r1); + + /* Continue if OrionN */ + ldr r1, =MV_5180_DEV_ID + cmp r3, r1 + bne 1f + b glMem2End +1: + /* Continue if Orion1 and device revision B1 */ + ldr r1, =MV_5181_DEV_ID + cmp r3, r1 + bne 1f + + cmp r2, #MV_5181_B1_REV + bge glMem2End + b glMem2Start +1: + + /* Orion NAS */ + ldr r1, =MV_5182_DEV_ID + cmp r3, r1 + beq glMem2Start + + /* Orion NAS */ + ldr r1, =MV_5082_DEV_ID + cmp r3, r1 + beq glMem2Start + + /* Orion Shark */ + ldr r1, =MV_8660_DEV_ID + cmp r3, r1 + beq glMem2Start + + b glMem2End + +glMem2Start: + + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + /* Set Bit [31] to make the register writable */ + orr r2, r3, #SDRAM_WR_EN + + MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ + bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ + bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ + bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ + + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r3 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ + orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ + + /* Write to both bits [5:0] and bits [11:6] */ + orr r3, r3, r1 + + MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + + /* Set Bit [31] to make the register writable */ + orr r2, r3, #SDRAM_WR_EN + + MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG) + + bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ + bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ + bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ + bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ + + /* Get the final N locked value of driving strength [22:17] */ + mov r1, r3 + mov r1, r1, LSL #9 + mov r1, r1, LSR #26 + orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ + + /* Write to both bits [5:0] and bits [11:6] */ + orr r3, r3, r1 + + MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + +glMem2End: + + + /* Implement Guideline (GL# MEM-3) Drive Strength Value */ + /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */ + /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */ + + /* Get SDRAM Config value */ + MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG) + + /* Get DIMM type */ + tst r2, #SDRAM_DTYPE_DDR2 + beq ddr1StrengthVal + +ddr2StrengthVal: + ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV + ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV + b setDrvStrength +ddr1StrengthVal: + ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV + ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV + +setDrvStrength: + /* DDR SDRAM Address/Control Pads Calibration */ + MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ + + MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + HTOLL(r3,r1) + + bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ + bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK + orr r3, r4, r3 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) + + + /* DDR SDRAM Data Pads Calibration */ + MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + + orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ + + MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + HTOLL(r3,r1) + + bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ + bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK + orr r3, r2, r3 /* Set default value for DDR */ + + MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) + +#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) + /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ + /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */ + /* 88F5082, 88F5181L, 88F6082/L */ + + /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ + ldr r7, = _cpuARMDDRCLK + ldr r4, =_start + sub r7, r7, r4 + add r7, r7, #CFG_MONITOR_BASE + + /* Get the "sample on reset" register for the DDR frequancy */ + MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET) + ldr r1, =MSAR_ARMDDRCLCK_MASK + and r1, r4, r1 +#if 0 /* YOTAM TO BE FIX */ + mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS +#endif + + /* Read device ID */ + MV_CTRL_MODEL_GET_ASM(r3, r2); + + /* Continue if TC90 */ + ldr r2, =MV_1281_DEV_ID + cmp r3, r2 + beq armClkMsb + + /* Continue if Orion2 */ + ldr r2, =MV_5281_DEV_ID + cmp r3, r2 +#if 0 /* YOTAM TO BE FIX */ + bne 1f +#endif + +armClkMsb: +#if 0 /* YOTAM TO BE FIX */ + tst r4, #MSAR_ARMDDRCLCK_H_MASK + beq 1f + orr r1, r1, #BIT4 +1: + ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE + mul r1, r4, r1 + add r7, r7, r1 + add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF + ldr r1, [r7] +#endif + + /* Get SDRAM Config value */ + MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG) + + /* Get DIMM type */ + tst r2, #SDRAM_DTYPE_DDR2 + beq ddr1FtdllVal + +ddr2FtdllVal: + ldr r2, =MV_5281_DEV_ID + cmp r3, r2 + bne 2f + MV_CTRL_REV_GET_ASM(r3, r2) + cmp r3, #MV_5281_D0_REV + beq orin2_d0_ddr2_ftdll_val + cmp r3, #MV_5281_D1_REV + beq orin2_d1_ddr2_ftdll_val + cmp r3, #MV_5281_D2_REV + beq orin2_d1_ddr2_ftdll_val + b ddr2_default_val + +/* Set Orion 2 D1 ftdll values for DDR2 */ +orin2_d1_ddr2_ftdll_val: + ldr r4, =FTDLL_DDR2_250MHZ_5281_D1 + ldr r7, =_250MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_200MHZ_5281_D1 + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + b ddr2_default_val + +/* Set Orion 2 D0 ftdll values for DDR2 */ +orin2_d0_ddr2_ftdll_val: + ldr r4, =FTDLL_DDR2_250MHZ_5281_D0 + ldr r7, =_250MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_200MHZ_5281_D0 + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + b ddr2_default_val +2: + ldr r2, =MV_5182_DEV_ID + cmp r3, r2 + bne 3f + +/* Set Orion nas ftdll values for DDR2 */ +orin_nas_ftdll_val: + ldr r4, =FTDLL_DDR2_166MHZ_5182 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + +/* default values for all other devices */ +3: +ddr2_default_val: + ldr r4, =FTDLL_DDR2_250MHZ + ldr r7, =_250MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_200MHZ + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_166MHZ + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR2_133MHZ + ldr r7, =_133MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =0 + b setFtdllReg + +ddr1FtdllVal: + ldr r2, =MV_5281_DEV_ID + cmp r3, r2 + bne 2f + MV_CTRL_REV_GET_ASM(r3, r2) + cmp r3, #MV_5281_D0_REV + bge orin2_ddr1_ftdll_val + b ddr1_default_val + +/* Set Orion 2 D0 and above ftdll values for DDR1 */ +orin2_ddr1_ftdll_val: + ldr r4, =FTDLL_DDR1_200MHZ_5281_D0 + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + ldr r4, =FTDLL_DDR1_166MHZ_5281_D0 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + b ddr1_default_val +2: + ldr r2, =MV_5181_DEV_ID + cmp r3, r2 + bne 3f + MV_CTRL_REV_GET_ASM(r3, r2) + cmp r3, #MV_5181_B1_REV + bge orin1_ddr1_ftdll_val + b ddr1_default_val + +/* Set Orion 1 ftdll values for DDR1 */ +orin1_ddr1_ftdll_val: + ldr r4, =FTDLL_DDR1_166MHZ_5181_B1 + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg +3: +ddr1_default_val: + ldr r4, =FTDLL_DDR1_133MHZ + ldr r7, =_133MHz + cmp r1, r7 + beq setFtdllReg + + ldr r4, =FTDLL_DDR1_166MHZ + ldr r7, =_166MHz + cmp r1, r7 + beq setFtdllReg + + ldr r4, =FTDLL_DDR1_200MHZ + ldr r7, =_200MHz + cmp r1, r7 + beq setFtdllReg + + ldr r4, =0 + +setFtdllReg: + + MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) + HTOLL(r4,r1) + bic r4, r4, #1 + MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) + +#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */ +#endif /* DB_FPGA */ + +restoreTmpRegs: + /* Restore the registers we used to save the DDR detect values */ + + ldr r4, =DRAM_BUF_REG0_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0) + + ldr r4, =DRAM_BUF_REG1_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1) + + ldr r4, =DRAM_BUF_REG2_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2) + + ldr r4, =DRAM_BUF_REG3_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3) + + ldr r4, =DRAM_BUF_REG4_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4) + + ldr r4, =DRAM_BUF_REG5_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5) + + ldr r4, =DRAM_BUF_REG6_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6) + + ldr r4, =DRAM_BUF_REG7_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7) + + ldr r4, =DRAM_BUF_REG8_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8) + + ldr r4, =DRAM_BUF_REG9_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9) + + ldr r4, =DRAM_BUF_REG10_DV + MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10) + + + /* Restore registers */ + /* Save register on stack */ + cmp sp, #0 + beq no_stack_l +load_from_stack: + ldmia sp!, {r1, r2, r3, r4, r7, r11} +no_stack_l: + + mov pc, lr + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h new file mode 100644 index 0000000..a7c6644 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h @@ -0,0 +1,192 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfConfigh +#define __INCmvDramIfConfigh + +/* includes */ + +/* defines */ + +/* registers defaults values */ + +#define SDRAM_CONFIG_DV \ + (SDRAM_PERR_WRITE | \ + SDRAM_SRMODE | \ + SDRAM_SRCLK_GATED) + +#define SDRAM_DUNIT_CTRL_LOW_DV \ + (SDRAM_CTRL_POS_RISE | \ + SDRAM_CLK1DRV_NORMAL | \ + SDRAM_LOCKEN_ENABLE) + +#define SDRAM_ADDR_CTRL_DV 0 + +#define SDRAM_TIMING_CTRL_LOW_REG_DV \ + ((0x2 << SDRAM_TRCD_OFFS) | \ + (0x2 << SDRAM_TRP_OFFS) | \ + (0x1 << SDRAM_TWR_OFFS) | \ + (0x0 << SDRAM_TWTR_OFFS) | \ + (0x5 << SDRAM_TRAS_OFFS) | \ + (0x1 << SDRAM_TRRD_OFFS)) +/* TRFC 0x27, TW2W 0x1 */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ + ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ + ( 0x1 << SDRAM_TW2W_OFFS)) + +#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN + +/* DDR2 ODT default register values */ + +/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ +/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ + +#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 +#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F +#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 + +#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C +#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F +#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 + + +/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ +#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ + (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) +#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + + +#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ + (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) +#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +/* DDR SDRAM Mode Register default value */ +#define DDR1_MODE_REG_DV 0x00000000 +#define DDR2_MODE_REG_DV 0x00000400 + +/* DDR SDRAM Timing parameter default values */ +#define DDR1_TIMING_LOW_DV 0x11602220 +#define DDR1_TIMING_HIGH_DV 0x0000000d + +#define DDR2_TIMING_LOW_DV 0x11812220 +#define DDR2_TIMING_HIGH_DV 0x0000030f + +/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ +#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ + (0x7F<< 12) | \ + (0x1 << 22)) + +#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ + +#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ + (0x1 << 12) | \ + (0x3 << 14) | \ + (0x1 << 18) | \ + (0x1 << 22)) + + +#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ + (0x1 << 12) | \ + (0x1 << 14) | \ + (0x1 << 16) | \ + (0x1 << 19) | \ + (0xF << 20)) + +#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ + +#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ + (0x1 << 12) | \ + (0x1 << 14) | \ + (0x1 << 16) | \ + (0x1 << 19) | \ + (0xF << 20)) + +#define FTDLL_DDR2_250MHZ 0x445001 + +/* Orion 1 B1 and above */ +#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 + +/* Orion nas */ +#define FTDLL_DDR2_166MHZ_5182 0x597001 + +/* Orion 2 D0 and above */ +#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 +#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 +#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 +#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 +#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 +#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 +#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 + +#endif /* __INCmvDramIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h new file mode 100644 index 0000000..e9cd7c4 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h @@ -0,0 +1,306 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfRegsh +#define __INCmvDramIfRegsh + + +/* DDR SDRAM Controller Address Decode Registers */ +/* SDRAM CSn Base Address Register (SCBAR) */ +#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) +#define SCBAR_BASE_OFFS 16 +#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) +#define SCBAR_BASE_ALIGNMENT 0x10000 + +/* SDRAM CSn Size Register (SCSR) */ +#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) +#define SCSR_WIN_EN BIT0 +#define SCSR_SIZE_OFFS 16 +#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) +#define SCSR_SIZE_ALIGNMENT 0x10000 + +/* configuration register */ +#define SDRAM_CONFIG_REG 0x1400 +#define SDRAM_REFRESH_OFFS 0 +#define SDRAM_REFRESH_MAX 0x3000 +#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) +#define SDRAM_DWIDTH_OFFS 14 +#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DTYPE_OFFS 16 +#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) +#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) +#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) +#define SDRAM_REGISTERED (1 << 17) +#define SDRAM_PERR_OFFS 18 +#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) +#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) +#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) +#define SDRAM_DCFG_OFFS 20 +#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) +#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) +#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) +#define SDRAM_SRMODE (1 << 24) +#define SDRAM_SRCLK_OFFS 25 +#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_CATTH_OFFS 26 +#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) + + +/* dunit control register */ +#define SDRAM_DUNIT_CTRL_REG 0x1404 +#define SDRAM_CTRL_POS_OFFS 6 +#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CLK1DRV_OFFS 12 +#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_LOCKEN_OFFS 18 +#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) +#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) +#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) +#define SDRAM_ST_BURST_DEL_OFFS 24 +#define SDRAM_ST_BURST_DEL_MAX 0xf +#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) + { + mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); + return MV_ERROR; + } + + /* All banks must support registry in order to activate it */ + if(bankInfo[i].registeredAddrAndControlInputs != + bankInfo[0].registeredAddrAndControlInputs) + { + mvOsOutput("Dram: ERR. different Registered settings !!!\n"); + return MV_ERROR; + } + + /* All banks must support same ECC mode */ + if(bankInfo[i].errorCheckType != + bankInfo[0].errorCheckType) + { + mvOsOutput("Dram: ERR. different ECC settings !!!\n"); + return MV_ERROR; + } + + } + else + { + if( i == 0 ) /* bank 0 doesn't exist */ + { + mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); + return MV_ERROR; + } + else + { + DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); + bankInfo[i].size = 0; /* Mark this bank as non exist */ + } + } + } + +#ifdef MV_INCLUDE_SDRAM_CS2 + if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) + { + MV_DRAM_CS_order[0] = SDRAM_CS2; + MV_DRAM_CS_order[1] = SDRAM_CS3; + MV_DRAM_CS_order[2] = SDRAM_CS0; + MV_DRAM_CS_order[3] = SDRAM_CS1; + DRAM_CS_Order[0] = SDRAM_CS2; + DRAM_CS_Order[1] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS0; + DRAM_CS_Order[3] = SDRAM_CS1; + + } + else +#endif + { + MV_DRAM_CS_order[0] = SDRAM_CS0; + MV_DRAM_CS_order[1] = SDRAM_CS1; + DRAM_CS_Order[0] = SDRAM_CS0; + DRAM_CS_Order[1] = SDRAM_CS1; +#ifdef MV_INCLUDE_SDRAM_CS2 + MV_DRAM_CS_order[2] = SDRAM_CS2; + MV_DRAM_CS_order[3] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS2; + DRAM_CS_Order[3] = SDRAM_CS3; +#endif + } + + for(j = 0; j < MV_DRAM_MAX_CS; j++) + { + i = MV_DRAM_CS_order[j]; + + if (0 == bankInfo[i].size) + continue; + + /* Init the CPU window decode */ + /* Note that the Dimm width might be different then the device DRAM width */ +#ifdef MV78XX0 + temp = MV_REG_READ(SDRAM_CONFIG_REG); + deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; +#else + deviceW = 16 /* KW family */; +#endif + dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); + size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); + + /* We can not change DRAM window settings while excecuting */ + /* code from it. That is why we skip the DRAM CS[0], saving */ + /* it to the ROM configuration routine */ + + numOfAllDevices += bankInfo[i].numberOfDevices; + if (i == MV_DRAM_CS_order[0]) + { + MV_U32 sizeToReg; + /* Translate the given window size to register format */ + sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); + /* Size parameter validity check. */ + if (-1 == sizeToReg) + { + mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" + ,i); + return MV_BAD_PARAM; + } + + DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) + sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); + sizeToReg |= SCSR_WIN_EN; + MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); + } + else + { + dramDecWin.addrWin.baseLow = base; + dramDecWin.addrWin.size = size; + dramDecWin.enable = MV_TRUE; + DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); + + /* Check if the DRAM size is more then 3GByte */ + if (base < 0xC0000000) + { + DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); + if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) + { + mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); + return MV_ERROR; + } + } + } + + base += size; + + /* update the suportedCasLatencies mask */ + bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; + } + + /* calculate minimum CAS */ + minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); + if (0 == minCas) + { + mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", + (busClk / 1000000)); + + minCas = DDR2_CL_4; /* Continue with this CAS */ + mvOsOutput("Set default CAS latency 4\n"); + } + + /* calc SDRAM_CONFIG_REG and save it to temp register */ + temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); + return MV_ERROR; + } + + /* check if ECC is enabled by the user */ + if(eccDisable) + { + /* turn off ECC*/ + temp &= ~BIT18; + } + DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG1, temp); + + /* calc SDRAM_MODE_REG and save it to temp register */ + temp = sdramModeRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG2, temp); + + /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ + temp = sdramExtModeRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG10, temp); + + /* calc D_UNIT_CONTROL_LOW and save it to temp register */ + TTMode = MV_FALSE; + DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) + if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) + { + if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || + (numOfAllDevices > 18) ) + { + mvOsOutput("Enable 2T "); + TTMode = MV_TRUE; + } + } + + temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG3, temp); + + /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ + temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) + /* check if ECC is enabled by the user */ + if(eccDisable) + { + /* turn off sample stage if no ecc */ + temp &= ~SDRAM__D2P_EN;; + } + MV_REG_WRITE(DRAM_BUF_REG13, temp); + + /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ + temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG4, temp); + + /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ + temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG5, temp); + + /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ + temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG6, temp); + + sdramDDr2OdtConfig(bankInfo); + + /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ + temp = sdramDdr2TimeLoRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG11, temp); + + /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ + temp = sdramDdr2TimeHiRegCalc(minCas); + if(-1 == temp) + { + mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); + return MV_ERROR; + } + DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) + MV_REG_WRITE(DRAM_BUF_REG12, temp); +#endif + + /* Note that DDR SDRAM Address/Control and Data pad calibration */ + /* settings is done in mvSdramIfConfig.s */ + + return MV_OK; +} + + +/******************************************************************************* +* mvDramIfBankBaseGet - Get DRAM interface bank base. +* +* DESCRIPTION: +* This function returns the 32 bit base address of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled or paramter is invalid, the +* function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) +{ + DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", + bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); + return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); +} + +/******************************************************************************* +* mvDramIfBankSizeGet - Get DRAM interface bank size. +* +* DESCRIPTION: +* This function returns the size of a given DRAM bank. +* +* INPUT: +* bankNum - Bank number. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM bank size. If bank is disabled the function return '0'. In case +* or paramter is invalid, the function returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) +{ + DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", + bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); + return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); +} + + +/******************************************************************************* +* mvDramIfSizeGet - Get DRAM interface total size. +* +* DESCRIPTION: +* This function get the DRAM total size. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* DRAM total size. In case or paramter is invalid, the function +* returns -1. +* +*******************************************************************************/ +MV_U32 mvDramIfSizeGet(MV_VOID) +{ + MV_U32 size = 0, i; + + for(i = 0; i < MV_DRAM_MAX_CS; i++) + size += mvDramIfBankSizeGet(i); + + DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); + return size; +} + +/******************************************************************************* +* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. +* +* DESCRIPTION: +* The ECC single bit error threshold is the number of single bit +* errors to happen before the Dunit generates an interrupt. +* This function set single bit ECC threshold. +* +* INPUT: +* threshold - threshold. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. +* +*******************************************************************************/ +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) +{ + MV_U32 regVal; + + if (threshold > SECR_THRECC_MAX) + { + return MV_BAD_PARAM; + } + + regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); + regVal &= ~SECR_THRECC_MASK; + regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); + MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); + + return MV_OK; +} + +#ifndef MV_STATIC_DRAM_ON_BOARD +/******************************************************************************* +* minCasCalc - Calculate the Minimum CAS latency which can be used. +* +* DESCRIPTION: +* Calculate the minimum CAS latency that can be used, base on the DRAM +* parameters and the SDRAM bus Clock freq. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - bank info parameters. +* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. +* +* OUTPUT: +* None +* +* RETURN: +* The minimum CAS Latency. The function returns 0 if max CAS latency +* supported by banks is incompatible with system bus clock frequancy. +* +*******************************************************************************/ + +static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) +{ + MV_U32 count = 1, j; + MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ + MV_U32 startBit, stopBit; + MV_U32 minCas0 = 0, minCas2 = 0; + + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * + Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * + *********************************************************/ + + + /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ + if (forcedCl) + { + mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); + + if (forcedCl == 30) + pBankInfo->suportedCasLatencies = 0x08; + else if (forcedCl == 40) + pBankInfo->suportedCasLatencies = 0x10; + else if (forcedCl == 50) + pBankInfo->suportedCasLatencies = 0x20; + else if (forcedCl == 60) + pBankInfo->suportedCasLatencies = 0x40; + else + { + mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", + (forcedCl / 10), (forcedCl % 10)); + pBankInfo->suportedCasLatencies = 0x10; + } + + return pBankInfo->suportedCasLatencies; + } + + /* go over the supported cas mask from Max Cas down and check if the */ + /* SysClk stands in its time requirments. */ + + DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo->suportedCasLatencies,busClkPs )); + count = 1; + for(j = 7; j > 0; j--) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) + { + case 1: + if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", + pBankInfo->suportedCasLatencies )); + + count = 1; + DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", + pBankInfo2->suportedCasLatencies,busClkPs )); + for(j = 7; j > 0; j--) + { + if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) + { + /* Reset the bits for CL incompatible for the sysClk */ + switch (count) + { + case 1: + if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 2: + if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + case 3: + if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + count++; + break; + default: + pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); + break; + } + } + } + + DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", + pBankInfo2->suportedCasLatencies )); + + startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ + stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ + + for(j = startBit; j <= stopBit ; j++) + { + if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) + { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); + minCas0 = (BIT0 << j); + break; + } + } + + for(j = startBit; j <= stopBit ; j++) + { + if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) + { + DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); + minCas2 = (BIT0 << j); + break; + } + } + + if (minCas2 > minCas0) + return minCas2; + else + return minCas0; + + return 0; +} + +/******************************************************************************* +* sdramConfigRegCalc - Calculate sdram config register +* +* DESCRIPTION: Calculate sdram config register optimized value based +* on the bank info parameters. +* +* INPUT: +* busClk - the DRAM bus Clock. +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram config reg value. +* +*******************************************************************************/ +static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) +{ + MV_U32 sdramConfig = 0; + MV_U32 refreshPeriod; + + busClk /= 1000000; /* we work with busClk in MHz */ + + sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); + + /* figure out the memory refresh internal */ + switch (pBankInfo->refreshInterval & 0xf) + { + case 0x0: /* refresh period is 15.625 usec */ + refreshPeriod = 15625; + break; + case 0x1: /* refresh period is 3.9 usec */ + refreshPeriod = 3900; + break; + case 0x2: /* refresh period is 7.8 usec */ + refreshPeriod = 7800; + break; + case 0x3: /* refresh period is 31.3 usec */ + refreshPeriod = 31300; + break; + case 0x4: /* refresh period is 62.5 usec */ + refreshPeriod = 62500; + break; + case 0x5: /* refresh period is 125 usec */ + refreshPeriod = 125000; + break; + default: /* refresh period undefined */ + mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); + return -1; + } + + /* Now the refreshPeriod is in register format value */ + refreshPeriod = (busClk * refreshPeriod) / 1000; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", + refreshPeriod)); + + /* make sure the refresh value is only 14 bits */ + if(refreshPeriod > SDRAM_REFRESH_MAX) + { + refreshPeriod = SDRAM_REFRESH_MAX; + DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", + refreshPeriod)); + } + + /* Clear the refresh field */ + sdramConfig &= ~SDRAM_REFRESH_MASK; + + /* Set new value to refresh field */ + sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); + + /* registered DRAM ? */ + if ( pBankInfo->registeredAddrAndControlInputs ) + { + /* it's registered DRAM, so set the reg. DRAM bit */ + sdramConfig |= SDRAM_REGISTERED; + DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) + } + + /* ECC and IERR support */ + sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ + sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ + + if ( pBankInfo->errorCheckType ) + { + sdramConfig |= SDRAM_ECC_EN; + sdramConfig |= SDRAM_IERR_REPORTE; + DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); + } + else + { + sdramConfig |= SDRAM_ECC_DIS; + sdramConfig |= SDRAM_IERR_IGNORE; + DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); + } + /* Set static default settings */ + sdramConfig |= SDRAM_CONFIG_DV; + + DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", + sdramConfig)); + + return sdramConfig; +} + +/******************************************************************************* +* sdramModeRegCalc - Calculate sdram mode register +* +* DESCRIPTION: Calculate sdram mode register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramModeRegCalc(MV_U32 minCas) +{ + MV_U32 sdramMode; + + sdramMode = MV_REG_READ(SDRAM_MODE_REG); + + /* Clear CAS Latency field */ + sdramMode &= ~SDRAM_CL_MASK; + + DB(mvOsPrintf("DRAM CAS Latency ");) + + switch (minCas) + { + case DDR2_CL_3: + sdramMode |= SDRAM_DDR2_CL_3; + DB(mvOsPrintf("3.\n");) + break; + case DDR2_CL_4: + sdramMode |= SDRAM_DDR2_CL_4; + DB(mvOsPrintf("4.\n");) + break; + case DDR2_CL_5: + sdramMode |= SDRAM_DDR2_CL_5; + DB(mvOsPrintf("5.\n");) + break; + case DDR2_CL_6: + sdramMode |= SDRAM_DDR2_CL_6; + DB(mvOsPrintf("6.\n");) + break; + default: + mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); + return -1; + } + + DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); + + return sdramMode; +} +/******************************************************************************* +* sdramExtModeRegCalc - Calculate sdram Extended mode register +* +* DESCRIPTION: +* Return sdram Extended mode register value based +* on the bank info parameters and bank presence. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - DRAM frequency +* +* OUTPUT: +* None +* +* RETURN: +* sdram Extended mode reg value. +* +*******************************************************************************/ +static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 populateBanks = 0; + int bankNum; + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + case(BANK_PRESENT_CS0_CS1): + return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; + + case(BANK_PRESENT_CS0_CS2): + case(BANK_PRESENT_CS0_CS1_CS2): + case(BANK_PRESENT_CS0_CS2_CS3): + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + if (busClk >= MV_BOARD_SYSCLK_267MHZ) + return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; + else + return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; + + default: + mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); + return -1; + } + return 0; +} + +/******************************************************************************* +* dunitCtrlLowRegCalc - Calculate sdram dunit control low register +* +* DESCRIPTION: Calculate sdram dunit control low register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control low reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) +{ + MV_U32 dunitCtrlLow, cl; + MV_U32 sbOutR[4]={3,5,7,9} ; + MV_U32 sbOutU[4]={1,3,5,7} ; + + dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); + + DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); + + /* Clear StBurstOutDel field */ + dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; + + /* Clear StBurstInDel field */ + dunitCtrlLow &= ~SDRAM_SB_IN_MASK; + + /* Clear CtrlPos field */ + dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; + + /* Clear 2T field */ + dunitCtrlLow &= ~SDRAM_2T_MASK; + if (TTMode == MV_TRUE) + { + dunitCtrlLow |= SDRAM_2T_MODE; + } + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstInDel bits [27:24] */ + /* 200MHz - 267MHz None reg = CL + 1 */ + /* 200MHz - 267MHz reg = CL + 2 */ + /* > 267MHz None reg = CL + 2 */ + /* > 267MHz reg = CL + 3 */ + + /* For proper sample of read data set the Dunit Control register's */ + /* stBurstOutDel bits [23:20] */ + /********-********-********-********- + * CL=3 | CL=4 | CL=5 | CL=6 | + *********-********-********-********- + Not Reg. * 0001 | 0011 | 0101 | 0111 | + *********-********-********-********- + Registered * 0011 | 0101 | 0111 | 1001 | + *********-********-********-********/ + + /* Set Dunit Control low default value */ + dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; + + switch (minCas) + { + case DDR2_CL_3: cl = 3; break; + case DDR2_CL_4: cl = 4; break; + case DDR2_CL_5: cl = 5; break; + case DDR2_CL_6: cl = 6; break; + default: + mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); + return -1; + } + + /* registerd DDR SDRAM? */ + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + { + dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; + } + else + { + dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; + } + + DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); + + if (busClk <= MV_BOARD_SYSCLK_267MHZ) + { + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + cl = cl + 2; + else + cl = cl + 1; + } + else + { + if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) + cl = cl + 3; + else + cl = cl + 2; + } + + DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); + dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; + + DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); + + return dunitCtrlLow; +} + +/******************************************************************************* +* dunitCtrlHighRegCalc - Calculate sdram dunit control high register +* +* DESCRIPTION: Calculate sdram dunit control high register optimized value based +* on the bus clock. +* +* INPUT: +* busClk - DRAM frequency. +* +* OUTPUT: +* None +* +* RETURN: +* sdram dunit control high reg value. +* +*******************************************************************************/ +static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 dunitCtrlHigh; + dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); + if(busClk > MV_BOARD_SYSCLK_300MHZ) + dunitCtrlHigh |= SDRAM__P2D_EN; + else + dunitCtrlHigh &= ~SDRAM__P2D_EN; + + if(busClk > MV_BOARD_SYSCLK_267MHZ) + dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); + + /* If ECC support we turn on D2P sample */ + dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ + if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) + dunitCtrlHigh |= SDRAM__D2P_EN; + + return dunitCtrlHigh; +} + +/******************************************************************************* +* sdramAddrCtrlRegCalc - Calculate sdram address control register +* +* DESCRIPTION: Calculate sdram address control register optimized value based +* on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* +* OUTPUT: +* None +* +* RETURN: +* sdram address control reg value. +* +*******************************************************************************/ +static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) +{ + MV_U32 addrCtrl = 0; + + if (pBankInfoDIMM1->size) + { + switch (pBankInfoDIMM1->sdramWidth) + { + case 4: /* memory is x4 */ + mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); + return -1; + break; + case 8: /* memory is x8 */ + addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); + break; + case 16: + addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); + break; + default: /* memory width unsupported */ + mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); + return -1; + } + } + + switch (pBankInfo->sdramWidth) + { + case 4: /* memory is x4 */ + mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); + return -1; + break; + case 8: /* memory is x8 */ + addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); + break; + case 16: + addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); + DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); + break; + default: /* memory width unsupported */ + mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); + return -1; + } + + /* Note that density is in MB units */ + switch (pBankInfo->deviceDensity) + { + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); + break; + case 1024: /* 1 Gbit */ + DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); + addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); + break; + case 2048: /* 2 Gbit */ + DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); + addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); + break; + default: + mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfo->deviceDensity); + return -1; + } + + if (pBankInfoDIMM1->size) + { + switch (pBankInfoDIMM1->deviceDensity) + { + case 256: /* 256 Mbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); + addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); + break; + case 512: /* 512 Mbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); + addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); + break; + case 1024: /* 1 Gbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); + addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); + break; + case 2048: /* 2 Gbit */ + DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); + addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); + break; + default: + mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", + pBankInfoDIMM1->deviceDensity); + return -1; + } + } + /* SDRAM address control */ + DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); + + return addrCtrl; +} + +/******************************************************************************* +* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register +* +* DESCRIPTION: +* This function calculates sdram timing control low register +* optimized value based on the bank info parameters and the minCas. +* +* INPUT: +* pBankInfo - sdram bank parameters +* minCas - minimum CAS supported. +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timing control low reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) +{ + MV_U32 tRp = 0; + MV_U32 tRrd = 0; + MV_U32 tRcd = 0; + MV_U32 tRas = 0; + MV_U32 tWr = 0; + MV_U32 tWtr = 0; + MV_U32 tRtp = 0; + MV_U32 timeCtrlLow = 0; + + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); + tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); + tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); + tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ + /* by shifting the data two bits right. */ + tRp = tRp >> 2; /* For example 0x50 -> 20ns */ + tRrd = tRrd >> 2; + tRcd = tRcd >> 2; + + /* Extract clock cycles from time parameter. We need to round up */ + tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); + DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); + tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRrd = 2 */ + if (tRrd < 2) + tRrd = 2; + DB(mvOsPrintf("tRrd = %d ", tRrd)); + tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRcd = %d ", tRcd)); + tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); + DB(mvOsPrintf("tRas = %d ", tRas)); + + /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); + tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); + tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); + } + + /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ + /* part by shifting the data two bits right. */ + tWr = tWr >> 2; /* For example 0x50 -> 20ns */ + tWtr = tWtr >> 2; + tRtp = tRtp >> 2; + /* Extract clock cycles from time parameter. We need to round up */ + tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); + DB(mvOsPrintf("tWr = %d ", tWr)); + tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tWtr = 2 */ + if (tWtr < 2) + tWtr = 2; + DB(mvOsPrintf("tWtr = %d ", tWtr)); + tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); + /* JEDEC min reqeirments tRtp = 2 */ + if (tRtp < 2) + tRtp = 2; + DB(mvOsPrintf("tRtp = %d ", tRtp)); + + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | + ((tRrd - 1) << SDRAM_TRRD_OFFS) | + ((tRcd - 1) << SDRAM_TRCD_OFFS) | + (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| + ((tWr - 1) << SDRAM_TWR_OFFS) | + ((tWtr - 1) << SDRAM_TWTR_OFFS) | + ((tRtp - 1) << SDRAM_TRTP_OFFS)); + + /* Check extended tRas bit */ + if ((tRas - 1) & BIT4) + timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); + + return timeCtrlLow; +} + +/******************************************************************************* +* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register +* +* DESCRIPTION: +* This function calculates sdram timing control high register +* optimized value based on the bank info parameters and the bus clock. +* +* INPUT: +* pBankInfo - sdram bank parameters +* busClk - Bus clock +* +* OUTPUT: +* None +* +* RETURN: +* sdram timing control high reg value. +* +*******************************************************************************/ +static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) +{ + MV_U32 tRfc; + MV_U32 timingHigh; + MV_U32 timeNs = 0; + MV_U32 bankNum; + + busClk = busClk / 1000000; /* In MHz */ + + /* Set DDR timing high register static configuration bits */ + timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); + + /* Set DDR timing high register default value */ + timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; + + /* Clear tRfc field */ + timingHigh &= ~SDRAM_TRFC_MASK; + + /* Scan all DRAM banks to find maximum timing values */ + for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); + DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", + pBankInfo[bankNum].minRefreshToActiveCmd)); + } + if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) + { + timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; + } + + tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); + /* Note: value of 0 in register means one cycle, 1 means two and so on */ + DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); + timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); + DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); + + /* SDRAM timing high */ + DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); + + return timingHigh; +} +/******************************************************************************* +* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. +* +* DESCRIPTION: +* This function config DDR2 On Die Termination (ODT) registers. +* +* INPUT: +* pBankInfo - bank info parameters. +* +* OUTPUT: +* None +* +* RETURN: +* None +*******************************************************************************/ +static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) +{ + MV_U32 populateBanks = 0; + MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; + int bankNum; + + /* Represent the populate banks in binary form */ + for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) + { + if (0 != pBankInfo[bankNum].size) + { + populateBanks |= (1 << bankNum); + } + } + + switch(populateBanks) + { + case(BANK_PRESENT_CS0): + case(BANK_PRESENT_CS0_CS1): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; + break; + case(BANK_PRESENT_CS0_CS2): + case(BANK_PRESENT_CS0_CS1_CS2): + case(BANK_PRESENT_CS0_CS2_CS3): + case(BANK_PRESENT_CS0_CS2_CS3_CS4): + odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; + odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; + dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; + break; + default: + DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); + return; + } + /* DDR2 SDRAM ODT ctrl low */ + DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); + MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); + + /* DDR2 SDRAM ODT ctrl high */ + DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); + MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); + + /* DDR2 DUNIT ODT ctrl */ + if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || + (mvCtrlModelGet() == MV_76100_DEV_ID) || + (mvCtrlModelGet() == MV_78100_DEV_ID) || + (mvCtrlModelGet() == MV_78200_DEV_ID) ) + dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ + + DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); + MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); + return; +} +/******************************************************************************* +* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. +* +* DESCRIPTION: +* This function config DDR2 DRAM Timing low registers. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* DDR2 sdram timing low reg value. +*******************************************************************************/ +static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) +{ + MV_U8 cl = -1; + MV_U32 ddr2TimeLoReg; + + /* read and clear the feilds we are going to set */ + ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); + ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | + SD2TLR_TODT_OFF_RD_MASK | + SD2TLR_TODT_ON_CTRL_RD_MASK | + SD2TLR_TODT_OFF_CTRL_RD_MASK); + + if( minCas == DDR2_CL_3 ) + { + cl = 3; + } + else if( minCas == DDR2_CL_4 ) + { + cl = 4; + } + else if( minCas == DDR2_CL_5 ) + { + cl = 5; + } + else if( minCas == DDR2_CL_6 ) + { + cl = 6; + } + else + { + DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", + minCas)); + cl = 4; + } + + ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); + ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); + ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); + ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); + + /* DDR2 SDRAM timing low */ + DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); + + return ddr2TimeLoReg; +} + +/******************************************************************************* +* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. +* +* DESCRIPTION: +* This function config DDR2 DRAM Timing high registers. +* +* INPUT: +* minCas - minimum CAS supported. +* +* OUTPUT: +* None +* +* RETURN: +* DDR2 sdram timing high reg value. +*******************************************************************************/ +static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) +{ + MV_U8 cl = -1; + MV_U32 ddr2TimeHiReg; + + /* read and clear the feilds we are going to set */ + ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); + ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | + SD2THR_TODT_OFF_WR_MASK | + SD2THR_TODT_ON_CTRL_WR_MASK | + SD2THR_TODT_OFF_CTRL_WR_MASK); + + if( minCas == DDR2_CL_3 ) + { + cl = 3; + } + else if( minCas == DDR2_CL_4 ) + { + cl = 4; + } + else if( minCas == DDR2_CL_5 ) + { + cl = 5; + } + else if( minCas == DDR2_CL_6 ) + { + cl = 6; + } + else + { + mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", + minCas); + cl = 4; + } + + ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); + ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); + ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); + ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); + + /* DDR2 SDRAM timin high */ + DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); + + return ddr2TimeHiReg; +} +#endif + +/******************************************************************************* +* mvDramIfCalGet - Get CAS Latency +* +* DESCRIPTION: +* This function get the CAS Latency. +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* CAS latency times 10 (to avoid using floating point). +* +*******************************************************************************/ +MV_U32 mvDramIfCalGet(void) +{ + MV_U32 sdramCasLat, casLatMask; + + casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); + + switch (casLatMask) + { + case SDRAM_DDR2_CL_3: + sdramCasLat = 30; + break; + case SDRAM_DDR2_CL_4: + sdramCasLat = 40; + break; + case SDRAM_DDR2_CL_5: + sdramCasLat = 50; + break; + case SDRAM_DDR2_CL_6: + sdramCasLat = 60; + break; + default: + mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); + return -1; + } + + return sdramCasLat; +} + + +/******************************************************************************* +* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - +* +* DESCRIPTION: +* add support in power management. +* +* +* INPUT: +* None +* +* OUTPUT: +* None +* +* RETURN: +* None +* +*******************************************************************************/ + +MV_VOID mvDramIfSelfRefreshSet() +{ + MV_U32 operReg; + + operReg = MV_REG_READ(SDRAM_OPERATION_REG); + MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); + /* Read until register is reset to 0 */ + while(MV_REG_READ(SDRAM_OPERATION_REG)); +} +/******************************************************************************* +* mvDramIfDimGetSPDversion - return DIMM SPD version. +* +* DESCRIPTION: +* This function prints the DRAM controller information. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) +{ + MV_DIMM_INFO dimmInfo; + if (bankNum >= MV_DRAM_MAX_CS ) + { + DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); + return ; + } + memset(&dimmInfo,0,sizeof(dimmInfo)); + if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return ; + } + *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; + *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; +} +/******************************************************************************* +* mvDramIfShow - Show DRAM controller information. +* +* DESCRIPTION: +* This function prints the DRAM controller information. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvDramIfShow(void) +{ + int i, sdramCasLat, sdramCsSize; + MV_U32 Major=0, Minor=0; + + mvOsOutput("DRAM Controller info:\n"); + + mvOsOutput("Total DRAM "); + mvSizePrint(mvDramIfSizeGet()); + mvOsOutput("\n"); + + for(i = 0; i < MV_DRAM_MAX_CS; i++) + { + sdramCsSize = mvDramIfBankSizeGet(i); + if (sdramCsSize) + { + if (0 == (i & 1)) + { + mvDramIfDimGetSPDversion(&Major, &Minor,i); + mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); + } + mvOsOutput("\tDRAM CS[%d] ", i); + mvSizePrint(sdramCsSize); + mvOsOutput("\n"); + } + } + sdramCasLat = mvDramIfCalGet(); + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) + { + mvOsOutput("ECC enabled, "); + } + else + { + mvOsOutput("ECC Disabled, "); + } + + if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) + { + mvOsOutput("Registered DIMM\n"); + } + else + { + mvOsOutput("Non registered DIMM\n"); + } + + mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); +} +/******************************************************************************* +* mvDramIfGetFirstCS - find the DRAM bank on the lower address +* +* +* DESCRIPTION: +* This function return the fisrt CS on address 0 +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* SDRAM_CS0 or SDRAM_CS2 +* +*******************************************************************************/ +MV_U32 mvDramIfGetFirstCS(void) +{ + MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; + + if (DRAM_CS_Order[0] == N_A) + { + mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); +#ifdef MV_INCLUDE_SDRAM_CS2 + mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); +#endif + +#ifdef MV_INCLUDE_SDRAM_CS2 + if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) + { + DRAM_CS_Order[0] = SDRAM_CS2; + DRAM_CS_Order[1] = SDRAM_CS3; + DRAM_CS_Order[2] = SDRAM_CS0; + DRAM_CS_Order[3] = SDRAM_CS1; + + return SDRAM_CS2; + } +#endif + DRAM_CS_Order[0] = SDRAM_CS0; + DRAM_CS_Order[1] = SDRAM_CS1; +#ifdef MV_INCLUDE_SDRAM_CS2 + DRAM_CS_Order[2] = SDRAM_CS2; + DRAM_CS_Order[3] = SDRAM_CS3; +#endif + return SDRAM_CS0; + } + return DRAM_CS_Order[0]; +} +/******************************************************************************* +* mvDramIfGetCSorder - +* +* +* DESCRIPTION: +* This function return the fisrt CS on address 0 +* +* INPUT: +* CS number. +* +* OUTPUT: +* CS order. +* +* RETURN: +* SDRAM_CS0 or SDRAM_CS2 +* +* NOTE: mvDramIfGetFirstCS must be caled before this subroutine +*******************************************************************************/ +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) +{ + return DRAM_CS_Order[csOrder]; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h new file mode 100644 index 0000000..23f2e54 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h @@ -0,0 +1,172 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfh +#define __INCmvDramIfh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ +#include "ddr2/mvDramIfRegs.h" +#include "ddr2/mvDramIfConfig.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* defines */ +/* DRAM Timing parameters */ +#define SDRAM_TWR 15 /* ns tWr */ +#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ +#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ +#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ +#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ + +#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ +#define ECC_DISABLE 1 /* Force ECC to Disable */ +#define ECC_ENABLE 0 /* Force ECC to ENABLE */ +/* typedefs */ + +/* enumeration for memory types */ +typedef enum _mvMemoryType +{ + MEM_TYPE_SDRAM, + MEM_TYPE_DDR1, + MEM_TYPE_DDR2 +}MV_MEMORY_TYPE; + +/* enumeration for DDR2 supported CAS Latencies */ +typedef enum _mvDimmDdr2Cas +{ + DDR2_CL_3 = 0x08, + DDR2_CL_4 = 0x10, + DDR2_CL_5 = 0x20, + DDR2_CL_6 = 0x40, + DDR2_CL_FAULT +} MV_DIMM_DDR2_CAS; + + +typedef struct _mvDramBankInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ + MV_U32 numberOfDevices; + + /* DIMM attributes (MV_TRUE for yes) */ + MV_BOOL registeredAddrAndControlInputs; + MV_BOOL registeredDQMBinputs; + +}MV_DRAM_BANK_INFO; + +#include "ddr2/spd/mvSpd.h" + +/* mvDramIf.h API list */ +MV_VOID mvDramIfBasicAsmInit(MV_VOID); +MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); +MV_VOID _mvDramIfConfig(int entryNum); + +MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); +MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); +MV_U32 mvDramIfSizeGet(MV_VOID); +MV_U32 mvDramIfCalGet(void); +MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); +MV_VOID mvDramIfSelfRefreshSet(void); +void mvDramIfShow(void); +MV_U32 mvDramIfGetFirstCS(void); +MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); +MV_U32 mvDramCsSizeGet(MV_U32 csNum); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDramIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S new file mode 100644 index 0000000..7672381 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S @@ -0,0 +1,986 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#define _ASMLANGUAGE +#define MV_ASMLANGUAGE +#include "mvSysHwConfig.h" +#include "mvOsAsm.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "mvDramIfConfig.h" +#include "mvDramIfRegs.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "ctrlEnv/mvCtrlEnvAsm.h" +#include "mvCommon.h" + +/* defines */ + +#if defined(MV_STATIC_DRAM_ON_BOARD) +.globl dramBoot1 +dramBoot1: + .word 0 + +/****************************************************************************** +* +* +* +* +*******************************************************************************/ +#if defined(DB_MV78XX0) || defined(DB_MV88F632X) +/* DDR2 boards 512MB 333MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#elif defined(RD_MV78XX0_AMC) +/* On board DDR2 512MB 400MHz CL5 */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#elif defined(RD_MV78XX0_H3C) +/* DDR2 boards 512MB 333MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#elif defined(RD_MV78XX0_PCAC) +/* DDR2 boards 256MB 200MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ + +#else +/* DDR2 MV88F6281 boards 256MB 400MHz */ +#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ +#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ +#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ +#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ +#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ +#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ +#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ +#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ +#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ +#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ +#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ +#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ +#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ +#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ +#endif /* MV78XX0 */ + + .globl _mvDramIfStaticInit +_mvDramIfStaticInit: + + mov r11, LR /* Save link register */ + mov r10, r2 + +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) +#endif + + /*DDR SDRAM Initialization Control */ + ldr r6, =DSICR_INIT_EN + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + and r6, r6, #DSICR_INIT_EN + cmp r6, #0 + bne 2b + + /* If we boot from NAND jump to DRAM address */ + mov r5, #1 + ldr r6, =dramBoot1 + str r5, [r6] /* We started executing from DRAM */ + + ldr r6, dramBoot1 + cmp r6, #0 + bne 1f + + /* set all dram windows to 0 */ + mov r6, #0 + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) + + + /* set all dram configuration in temp registers */ + ldr r6, = STATIC_SDRAM0_BANK0_SIZE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) + ldr r6, = STATIC_SDRAM_CONFIG + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) + ldr r6, = STATIC_SDRAM_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) + ldr r6, = STATIC_DUNIT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) + ldr r6, = STATIC_SDRAM_ADDR_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) + ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) + ldr r6, = STATIC_SDRAM_TIME_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) + ldr r6, = STATIC_SDRAM_ODT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) + ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) + ldr r6, = STATIC_SDRAM_EXT_MODE + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) + ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) + ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) +#ifndef MV_NAND_BOOT + ldr r6, = STATIC_DUNIT_CTRL_HI + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) +#endif + + ldr sp,=0 + bl _mvDramIfConfig + ldr r0, =0 +#ifdef MV78XX0 + bl _mvDramIfEccMemInit +#endif +1: + mov r2, r10 + mov PC, r11 /* r11 is saved link register */ + +#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ + +.globl dramBoot1 +dramBoot1: + .word 0 + +/******************************************************************************* +* mvDramIfBasicInit - Basic initialization of DRAM interface +* +* DESCRIPTION: +* The function will initialize the DRAM for basic usage. The function +* will use the TWSI assembly API to extract DIMM parameters according +* to which DRAM interface will be initialized. +* The function referes to the following DRAM parameters: +* 1) DIMM is registered or not. +* 2) DIMM width detection. +* 3) DIMM density. +* +* INPUT: +* r3 - required size for initial DRAM. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +* Note: +* r4 holds I2C EEPROM address +* r5 holds SDRAM register base address +* r7 holds returned values +* r8 holds SDRAM various configuration registers value. +* r11 holds return function address. +*******************************************************************************/ +/* Setting the offsets of the I2C registers */ +#define DIMM_TYPE_OFFSET 2 +#define NUM_OF_ROWS_OFFSET 3 +#define NUM_OF_COLS_OFFSET 4 +#define NUM_OF_RANKS 5 +#define DIMM_CONFIG_TYPE 11 +#define SDRAM_WIDTH_OFFSET 13 +#define NUM_OF_BANKS_OFFSET 17 +#define SUPPORTED_CL_OFFSET 18 +#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ +#define SDRAM_MODULES_ATTR_OFFSET 21 +#define RANK_SIZE_OFFSET 31 + +#define DRAM_DEV_DENSITY_128M 128 +#define DRAM_DEV_DENSITY_256M 256 +#define DRAM_DEV_DENSITY_512M 512 +#define DRAM_DEV_DENSITY_1G 1024 +#define DRAM_DEV_DENSITY_2G 2048 + +#define DRAM_RANK_DENSITY_128M 0x20 +#define DRAM_RANK_DENSITY_256M 0x40 +#define DRAM_RANK_DENSITY_512M 0x80 +#define DRAM_RANK_DENSITY_1G 0x1 +#define DRAM_RANK_DENSITY_2G 0x2 + + .globl _mvDramIfBasicInit + .extern _i2cInit +_mvDramIfBasicInit: + + mov r11, LR /* Save link register */ + + /* Set Dunit high control register */ + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ + orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ +#ifdef MV78XX0 + orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ + orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ + orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ +#endif + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) +#endif + + /*DDR SDRAM Initialization Control */ + ldr r6, =DSICR_INIT_EN + MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) +2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) + and r6, r6, #DSICR_INIT_EN + cmp r6, #0 + bne 2b + + mov r5, #1 + ldr r8, =dramBoot1 + str r5, [r8] /* We started executing from DRAM */ + + /* If we boot from NAND jump to DRAM address */ + ldr r8, dramBoot1 + cmp r8, #0 + movne pc, r11 + + bl _i2cInit /* Initialize TWSI master */ + + /* Check if we have more then 1 dimm */ + ldr r6, =0 + MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) +#ifdef MV78XX0 + bl _is_Second_Dimm_Exist + beq single_dimm + ldr r6, =1 + MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) +single_dimm: + bl _i2cInit /* Initialize TWSI master */ +#endif + + /* Get default SDRAM Config values */ + MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) + + /* Get registered/non registered info from DIMM */ + bl _is_Registered + beq nonRegistered + +setRegistered: + orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ +nonRegistered: +#ifdef MV78XX0 + /* Get ECC/non ECC info from DIMM */ + bl _is_Ecc + beq setConfigReg + +setEcc: + orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ +#endif +setConfigReg: + MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) + + /* Set maximum CL supported by DIMM */ + bl _get_CAL + + /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ + clz r6, r7 + rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ + +casDdr2: + ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x32 /* Assuming MAX CL = 3 */ + cmp r6, #3 /* If CL = 3 break */ + beq casDdr2Cont + + ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x42 /* Assuming MAX CL = 4 */ + cmp r6, #4 /* If CL = 4 break */ + beq casDdr2Cont + + ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x52 /* Assuming MAX CL = 5 */ + cmp r6, #5 /* If CL = 5 break */ + beq casDdr2Cont + + ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ + ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ + ldr r8, =0x62 /* Assuming MAX CL = 6 */ + cmp r6, #6 /* If CL = 5 break */ + beq casDdr2Cont + + /* This is an error. return */ + b exit_ddrAutoConfig /* This is an error !! */ +casDdr2Cont: + + /* Get default SDRAM Mode values */ + MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) + bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ + orr r6, r6, r8 + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) + + /* Set Dunit control register according to max CL detected */ + MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) + tst r6, #SDRAM_REGISTERED + beq setDunitReg + mov r7, r3 + +setDunitReg: +#ifdef MV78XX0 + /* Set SDRAM Extended Mode register for double DIMM */ + /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + ble Clock333 + add r7, r7, #0x10 +Clock333: +#endif + + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) + bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ + orr r6, r6, #BIT4 /* Enable 2T mode */ + bic r6, r6, #BIT6 /* clear ctrlPos */ + orr r6, r6, r7, LSL #20 + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) + + /* Set Dunit high control register */ + MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) + orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ + orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ +#ifdef MV78XX0 + orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ + orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ + orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ +#endif + MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) + + /* DIMM density configuration*/ + /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ +Density: + /* Get bank 0 and 1 density */ + ldr r6, =0 + bl _getDensity + + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) + cmp r8, #DRAM_DEV_DENSITY_256M + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) + cmp r8, #DRAM_DEV_DENSITY_512M + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) + cmp r8, #DRAM_DEV_DENSITY_1G + beq get_bank_2_density + + mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) + cmp r8, #DRAM_DEV_DENSITY_2G + beq get_bank_2_density + + /* This is an error. return */ + b exit_ddrAutoConfig + +get_bank_2_density: + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne get_width + + /* Get bank 2 and 3 density */ + ldr r6, =2 + bl _getDensity + + mov r8, r7 + mov r8, r8, LSR #20 /* Move density 20 bits to the right */ + /* For example 0x10000000 --> 0x1000 */ + + orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) + cmp r8, #DRAM_DEV_DENSITY_256M + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) + cmp r8, #DRAM_DEV_DENSITY_512M + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) + cmp r8, #DRAM_DEV_DENSITY_1G + beq get_width + + and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) + orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) + cmp r8, #DRAM_DEV_DENSITY_2G + beq get_width + + /* This is an error. return */ + b exit_ddrAutoConfig + + /* Get SDRAM width */ +get_width: + /* Get bank 0 and 1 width */ + ldr r6, =0 + bl _get_width + + cmp r7, #8 /* x8 devices */ + beq get_bank_2_width + + orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ + cmp r7, #16 + beq get_bank_2_width + + /* This is an error. return */ + b exit_ddrAutoConfig + +get_bank_2_width: + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne densCont + + /* Get bank 2 and 3 width */ + ldr r6, =2 + bl _get_width + + cmp r7, #8 /* x8 devices */ + beq densCont + + orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ + cmp r7, #16 + beq densCont + + /* This is an error. return */ + b exit_ddrAutoConfig + +densCont: + MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) + + /* Set SDRAM timing control low register */ + ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT + /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) + + /* Set SDRAM timing control high register */ + ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + blt timingHighClock333 + orr r6, r6, #BIT9 + +timingHighClock333: + /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ + MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) + + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne single_dimm_odt + + /* Set SDRAM ODT control low register for double DIMM*/ + ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) + + /* Set DUNIT ODT control register for double DIMM */ + ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) + +#ifdef MV78XX0 + /* Set SDRAM Extended Mode register for double DIMM */ + /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ + + MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) + ldr r5, =MSAR_SYSCLCK_MASK + and r4, r4, r5 + ldr r5, =MSAR_SYSCLCK_267 + cmp r4, r5 + beq slow_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_300 + cmp r4, r5 + beq slow_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_333 + cmp r4, r5 + beq fast_dram_clock_rtt + ldr r5, =MSAR_SYSCLCK_400 + cmp r4, r5 + beq fast_dram_clock_rtt + + b slow_dram_clock_rtt + +fast_dram_clock_rtt: + ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + b odt_config_end +#endif +slow_dram_clock_rtt: + ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + b odt_config_end + +single_dimm_odt: + /* Set SDRAM ODT control low register */ + ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) + + /* Set DUNIT ODT control register */ + ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) + + /* Set SDRAM Extended Mode register */ + ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) + +odt_config_end: + /* SDRAM ODT control high register is left as default */ + MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) + + /*Read CL and set the DDR2 registers accordingly */ + MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) + and r6, r6, #SDRAM_CL_MASK + mov r4, r6 + orr r4, r4, r6, LSL #4 + orr r4, r4, r6, LSL #8 + orr r4, r4, r6, LSL #12 + mov r5, #0x30000 + add r4, r4, r5 + sub r4, r4, #0x30 + /* Set SDRAM Ddr2 Timing Low register */ + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) + + /* Set SDRAM Ddr2 Timing High register */ + mov r4, r4, LSR #4 + MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) + +timeParamDone: + /* Close all windows */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + and r6, r6,#~SCSR_SIZE_MASK + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + + /* Set sdram bank 0 size and enable it */ + ldr r6, =0 + bl _mvDramIfGetDimmSizeFromSpd +#ifdef MV78XX0 + /* Check DRAM width */ + MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) + ldr r5, =SDRAM_DWIDTH_MASK + and r4, r4, r5 + ldr r5, =SDRAM_DWIDTH_64BIT + cmp r4, r5 + beq dram_64bit_width + /* Utilize only 32bit width */ + mov r8, r8, LSR #1 +#else + /* Utilize only 16bit width */ + mov r8, r8, LSR #2 +#endif +dram_64bit_width: + /* Update first dimm size return value R8 */ + MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) + ldr r6, =~SCSR_SIZE_MASK + and r5, r5, r6 + orr r5, r5, r8 + MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) + + /* Clear bank 2 size */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#~SCSR_SIZE_MASK + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + + /* Check for second dimm */ + MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) + cmp r6, #1 + bne defualt_order + + /* Set sdram bank 2 size */ + ldr r6, =2 + bl _mvDramIfGetDimmSizeFromSpd +#ifdef MV78XX0 + /* Check DRAM width */ + MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) + ldr r5, =SDRAM_DWIDTH_MASK + and r4, r4, r5 + ldr r5, =SDRAM_DWIDTH_64BIT + cmp r4, r5 + beq dram_64bit_width2 + /* Utilize only 32bit width */ + mov r8, r8, LSR #1 +#else + /* Utilize only 16bit width */ + mov r8, r8, LSR #2 +#endif +dram_64bit_width2: + /* Update first dimm size return value R8 */ + MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) + ldr r6, =~SCSR_SIZE_MASK + and r5, r5, r6 + orr r5, r5, r8 + MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) + + /* Close windows 1 and 3 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + and r6, r6,#~1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) + + /* Check dimm size for setting dram bank order */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) + and r6, r6,#SCSR_SIZE_MASK + and r4, r4,#SCSR_SIZE_MASK + cmp r6, r4 + bge defualt_order + + /* Bank 2 is biger then bank 0 */ + ldr r6,=0 + MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) + + /* Open win 2 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + orr r6, r6,#1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) + + ldr sp,=0 + bl _mvDramIfConfig +#ifdef MV78XX0 + /* Init ECC on CS 2 */ + ldr r0, =2 + bl _mvDramIfEccMemInit +#endif + mov PC, r11 /* r11 is saved link register */ + +defualt_order: + + /* Open win 0 */ + MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + orr r6, r6,#1 + MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) + + ldr sp,=0 + bl _mvDramIfConfig +#ifdef MV78XX0 + /* Init ECC on CS 0 */ + ldr r0, =0 + bl _mvDramIfEccMemInit +#endif +exit_ddrAutoConfig: + mov PC, r11 /* r11 is saved link register */ + + +/***************************************************************************************/ +/* r4 holds I2C EEPROM address + * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value + * r8 holds SDRAM various configuration registers value. + * r13 holds Link register + */ +/**************************/ +_getDensity: + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ + bl _i2cRead + mov r8, r7 /* r8 save number of rows */ + + mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ + bl _i2cRead + add r8, r8, r7 /* r8 = number of rows + number of col */ + + mov r7, #0x1 + mov r8, r7, LSL r8 /* r8 = (1 << r8) */ + + mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ + bl _i2cRead + mul r8, r7, r8 + + mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ + bl _i2cRead + mul r7, r8, r7 + + mov PC, r13 + +/**************************/ +_get_width: + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + /* Get SDRAM width (SPD offset 13) */ + mov r7, #SDRAM_WIDTH_OFFSET + bl _i2cRead /* result in r7 */ + + mov PC, r13 + +/**************************/ +_get_CAL: + mov r13, LR /* Save link register */ + + /* Set maximum CL supported by DIMM */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ + bl _i2cRead + + mov PC, r13 + +/**************************/ +/* R8 - sdram configuration register. + * Return value in flag if no-registered then Z-flag is set + */ +_is_Registered: + mov r13, LR /* Save link register */ +#if defined(MV645xx) + /* Get registered/non registered info from DIMM */ + tst r8, #SDRAM_DTYPE_DDR2 + bne regDdr2 + +regDdr1: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #SDRAM_MODULES_ATTR_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x2 + b exit +#endif +regDdr2: + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_INFO_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ + /* or Mini-RDIMM (0x10) */ +exit: + mov PC, r13 + + +/**************************/ +/* Return value in flag if no-Ecc then Z-flag is set */ +_is_Ecc: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_CONFIG_TYPE + bl _i2cRead /* result in r7 */ + + tst r7, #0x2 /* bit 1 -> Data ECC */ + mov PC, r13 + +/**************************/ +/* Return value in flag if no second DIMM then Z-flag is set */ +_is_Second_Dimm_Exist: + mov r13, LR /* Save link register */ + + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ + mov r7, #DIMM_TYPE_OFFSET + bl _i2cRead /* result in r7 */ + + tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ + mov PC, r13 + +/******************************************************************************* +* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size +* +* DESCRIPTION: +* The function will read the bank 0 dram size(SPD version 1.0 and above ) +* +* INPUT: +* r6 - dram bank number. +* +* OUTPUT: +* none +*/ +_mvDramIfGetDimmSizeFromSpd: + + mov r13, LR /* Save link register */ + + /* Read SPD rank size from DIMM0 */ + mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ + + cmp r6, #0 + beq 1f + + /* Read SPD rank size from DIMM1 */ + mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ + +1: + mov r7, #RANK_SIZE_OFFSET /* offset 31 */ + bl _i2cRead + +pass_read: + ldr r8, =(0x7 << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_128M + beq endDimmSize + + ldr r8, =(0xf << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_256M + beq endDimmSize + + ldr r8, =(0x1f << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_512M + beq endDimmSize + + ldr r8, =(0x3f << SCSR_SIZE_OFFS) + cmp r7, #DRAM_RANK_DENSITY_1G + beq endDimmSize + + ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ +endDimmSize: + mov PC, r13 +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S new file mode 100644 index 0000000..88527e5 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S @@ -0,0 +1,528 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvDramIfBasicAsm.s +* +* DESCRIPTION: +* Memory full detection and best timing configuration is done in +* C code. C runtime environment requires a stack. This module API +* initialize DRAM interface chip select 0 for basic functionality for +* the use of stack. +* The module API assumes DRAM information is stored in I2C EEPROM reside +* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM +* internal data structure is assumed to be orgenzied in common DRAM +* vendor SPD structure. +* NOTE: DFCDL values are assumed to be already initialized prior to +* this module API activity. +* +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +/* includes */ +#define _ASMLANGUAGE +#define MV_ASMLANGUAGE +#include "mvOsAsm.h" +#include "mvSysHwConfig.h" +#include "mvDramIfRegs.h" +#include "mvDramIfConfig.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "mvCommon.h" + +/* defines */ + +/* locals */ +.data +.globl _mvDramIfConfig +.text +.globl _mvDramIfMemInit + +/******************************************************************************* +* _mvDramIfConfig - Basic DRAM interface initialization. +* +* DESCRIPTION: +* The function will initialize the following DRAM parameters using the +* values prepared by mvDramIfDetect routine. Values are located +* in predefined registers. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ + +_mvDramIfConfig: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s +save_on_stack: + stmdb sp!, {r1, r2, r3, r4} +no_stack_s: + + /* Dunit FTDLL Configuration Register */ + /* 0) Write to SDRAM FTDLL coniguration register */ + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) + str r4, [r1] + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) + str r4, [r1] + ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; + ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) + str r4, [r1] + + /* 1) Write to SDRAM coniguration register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) + str r4, [r1] + + /* 2) Write Dunit control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) + str r4, [r1] + + /* 2) Write Dunit control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) + str r4, [r1] + + /* 3) Write SDRAM address control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) + str r4, [r1] +#if defined(MV_STATIC_DRAM_ON_BOARD) + /* 4) Write SDRAM bank 0 size register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) + str r4, [r1] +#endif + + /* 5) Write SDRAM open pages control register */ + ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) + ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV + str r4, [r1] + + /* 6) Write SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) + str r4, [r1] + + /* 7) Write SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) + str r4, [r1] + + /* Config DDR2 On Die Termination (ODT) registers */ + /* Write SDRAM DDR2 ODT control low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) + str r4, [r1] + + /* Write SDRAM DDR2 ODT control high register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) + str r4, [r1] + + /* Write SDRAM DDR2 Dunit ODT control register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) + str r4, [r1] + + /* Write DDR2 SDRAM timing Low register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) + str r4, [r1] + + /* Write DDR2 SDRAM timing High register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) + str r4, [r1] + + /* 8) Write SDRAM mode register */ + /* The CPU must not attempt to change the SDRAM Mode register setting */ + /* prior to DRAM controller completion of the DRAM initialization */ + /* sequence. To guarantee this restriction, it is recommended that */ + /* the CPU sets the SDRAM Operation register to NOP command, performs */ + /* read polling until the register is back in Normal operation value, */ + /* and then sets SDRAM Mode register to its new value. */ + + /* 8.1 write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) + + /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll1: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll1 + + /* 8.3 Now its safe to write new value to SDRAM Mode register */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) + str r4, [r1] + + /* 8.4 Make the Dunit write the DRAM its new mode */ + mov r4, #0x3 /* Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll2: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll2 + + /* Now its safe to write new value to SDRAM Extended Mode regist */ + ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) + ldr r4, [r1] + ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) + str r4, [r1] + + /* 9) Write SDRAM Extended mode register This operation should be */ + /* done for each memory bank */ + /* write 'nop' to SDRAM operation */ + mov r4, #0x5 /* 'NOP' command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll3: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll3 + /* Go over each of the Banks */ + ldr r3, =0 /* r3 = DRAM bank Num */ + +extModeLoop: + /* Set the SDRAM Operation Control to each of the DRAM banks */ + mov r4, r3 /* Do not swap the bank counter value */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) + + /* Make the Dunit write the DRAM its new mode */ + mov r4, #0x4 /* Extended Mode Register Set command */ + MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) + + /* poll SDRAM operation. Make sure its back to normal operation */ +_sdramOpPoll4: + ldr r4, [r1] + cmp r4, #0 /* '0' = Normal SDRAM Mode */ + bne _sdramOpPoll4 + + add r3, r3, #1 + cmp r3, #4 /* 4 = Number of banks */ + bne extModeLoop + +extModeEnd: +cmp sp, #0 + beq no_stack_l + mov r1, LR /* Save link register */ +#if defined(MV78XX0) + bl _mvDramIfMemInit +#endif + mov LR,r1 /* restore link register */ +load_from_stack: + /* Restore registers */ + ldmia sp!, {r1, r2, r3, r4} +no_stack_l: + + mov pc, lr + + +/******************************************************************************* +* _mvDramIfEccMemInit - Basic DRAM ECC initialization. +* +* DESCRIPTION: +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ +#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ +#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ +/* XOR engine register offsets macros */ +#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4)) +#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4)) +#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30) +#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50) +#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60) +#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0) +#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4) +#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4)) +#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4)) + +/* XOR Engine Address Decoding Register Map */ +#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) +#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) +#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) + +.globl _mvDramIfEccMemInit +/******************************************************************************* +* _mvDramIfEccMemInit - mem init for dram cs +* +* DESCRIPTION: +* This function will clean the cs by ussing the XOR mem init. +* +* INPUT: +* r0 - dram bank number. +* +* OUTPUT: +* none +*/ +_mvDramIfEccMemInit: + + /* Save register on stack */ + cmp sp, #0 + beq no_stack_s1 +save_on_stack1: + stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} +no_stack_s1: + + ldr r1, = 0 + + /* Disable all XOR address decode windows to avoid possible overlap */ + MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) + + /* Init r5 to first XOR_SIZE_MASK_REG */ + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#0x04 + add r5, r5,#(INTER_REGS_BASE) + ldr r6, [r5] + HTOLL(r6,r5) + MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) + + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#(INTER_REGS_BASE) + ldr r6, [r5] + /* Update destination & size */ + MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) + HTOLL(r6,r5) + /* Init r6 to first XOR_BASE_ADDR_REG */ + ldr r4, = 0xf + ldr r5, = 0x1 + mov r5, r5, LSL r0 + bic r4, r4, r5 + mov r4, r4, LSL #8 + + orr r6, r6, r4 + MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) + + ldr r6, = 0xff0001 + MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) + + /* Configure XOR engine for memory init function. */ + MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) + and r6, r6, #~0x7 /* Clear operation mode field */ + orr r6, r6, #0x4 /* Set operation to memory init */ + MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) + + /* Set initVal in the XOR Engine Initial Value Registers */ + ldr r6, = 0xfeedfeed + MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) + ldr r6, = 0xfeedfeed + MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) + + /* Set block size using DRAM bank size */ + + mov r5, r0, LSL #3 + add r5, r5,#0x1500 + add r5, r5,#0x04 + add r5, r5,#(INTER_REGS_BASE) + + ldr r6, [r5] + HTOLL(r6,r5) + and r6, r6, #SCSR_SIZE_MASK + mov r5, r6, LSR #SCSR_SIZE_OFFS + add r5, r5, #1 + mov r6, r5, LSL #SCSR_SIZE_OFFS + MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) + + /* Clean interrupt cause*/ + MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) + + /* Clean error interrupt cause*/ + MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) + MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) + + /* Start transfer */ + MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) + orr r6, r6, #0x1 /* Preform start command */ + MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) + + /* Wait for engine to finish */ +waitForComplete: + MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) + and r6, r6, #2 + cmp r6, #0 + beq waitForComplete + + /* Clear all error report registers */ + MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) + MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) + + MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) + + cmp sp, #0 + beq no_stack_l1 +load_from_stack1: + ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} +no_stack_l1: + mov pc, lr + + +/******************************************************************************* +* mvDramIfMemInit - Use XOR to clear all memory. +* +* DESCRIPTION: +* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +#if defined(MV78XX0) + +_mvDramIfMemInit: + stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} + mov r6, LR /* Save link register */ + /* Check if dram bank 0 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) + and r3, r0, #SCSR_WIN_EN + cmp r3, #0 + beq no_bank_0 + MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) + cmp r0, #0 + beq no_bank_0 + mov r0,#0 + bl _mvDramIfEccMemInit + +no_bank_0: + /* Check if dram bank 1 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_1 + mov r0,#1 + bl _mvDramIfEccMemInit +no_bank_1: + /* Check if dram bank 2 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_2 + MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) + cmp r0, #0 + beq no_bank_2 + mov r0,#2 + bl _mvDramIfEccMemInit + +no_bank_2: + /* Check if dram bank 3 has to be init for ECC */ + MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) + and r0, r0, #SCSR_WIN_EN + cmp r0, #0 + beq no_bank_3 + mov r0,#3 + bl _mvDramIfEccMemInit +no_bank_3: + mov LR ,r6 /* restore link register */ + ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} + mov pc, lr +#endif + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h new file mode 100644 index 0000000..6141c46 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h @@ -0,0 +1,157 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvDramIfConfigh +#define __INCmvDramIfConfigh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* includes */ + +/* defines */ + +/* registers defaults values */ + +#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) + +#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ + (SDRAM_SRCLK_KEPT | \ + SDRAM_CLK1DRV_NORMAL | \ + (BIT28 | BIT29)) + +#define SDRAM_ADDR_CTRL_DV 2 + +#define SDRAM_TIMING_CTRL_LOW_REG_DV \ + ((0x2 << SDRAM_TRCD_OFFS) | \ + (0x2 << SDRAM_TRP_OFFS) | \ + (0x1 << SDRAM_TWR_OFFS) | \ + (0x0 << SDRAM_TWTR_OFFS) | \ + (0x5 << SDRAM_TRAS_OFFS) | \ + (0x1 << SDRAM_TRRD_OFFS)) + +/* Note: value of 0 in register means one cycle, 1 means two and so on */ +#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ + ((0x0 << SDRAM_TR2R_OFFS) | \ + (0x0 << SDRAM_TR2W_W2R_OFFS) | \ + (0x1 << SDRAM_TW2W_OFFS)) + +#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN + +/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ +/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ +/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ +/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ + +#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 +#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F +#ifdef MV78XX0 +#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 +#else +#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 +#endif + +#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C +#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 +#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F +#ifdef MV78XX0 +#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 +#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 +#else +#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 +#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 +#endif + +/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ +#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ + (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) + +/* DDR SDRAM Mode Register default value */ +#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) +/* DDR SDRAM Timing parameter default values */ +#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 +#define SDRAM_TRFC_DEFAULT_VALUE 0x34 +#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE +#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) + +#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) + +#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 +#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 +#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvDramIfh */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h new file mode 100644 index 0000000..369eda6 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h @@ -0,0 +1,423 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDramIfRegsh +#define __INCmvDramIfRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* DDR SDRAM Controller Address Decode Registers */ + /* SDRAM CSn Base Address Register (SCBAR) */ +#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) +#define SCBAR_BASE_OFFS 16 +#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) +#define SCBAR_BASE_ALIGNMENT 0x10000 + +/* SDRAM CSn Size Register (SCSR) */ +#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) +#define SCSR_SIZE_OFFS 24 +#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) +#define SCSR_SIZE_ALIGNMENT 0x1000000 +#define SCSR_WIN_EN BIT0 + +/* configuration register */ +#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) +#define SDRAM_REFRESH_OFFS 0 +#define SDRAM_REFRESH_MAX 0x3FFF +#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) +#define SDRAM_DWIDTH_OFFS 15 +#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) +#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) +#define SDRAM_REGISTERED (1 << 17) +#define SDRAM_ECC_OFFS 18 +#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) +#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) +#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) +#define SDRAM_IERR_OFFS 19 +#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) +#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) +#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) +#define SDRAM_SRMODE_OFFS 24 +#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) +#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) +#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) + +/* dunit control low register */ +#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) +#define SDRAM_2T_OFFS 4 +#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) +#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) + +#define SDRAM_SRCLK_OFFS 5 +#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) +#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) +#define SDRAM_CTRL_POS_OFFS 6 +#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) +#define SDRAM_CLK1DRV_OFFS 12 +#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) +#define SDRAM_CLK2DRV_OFFS 13 +#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) +#define SDRAM_SB_OUT_DEL_OFFS 20 +#define SDRAM_SB_OUT_DEL_MAX 0xf +#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + memset(pBankInfo, 0, sizeof(*pBankInfo)); + + if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); + return MV_FAIL; + } + if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) + { + DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); + return MV_FAIL; + } + /* convert Dimm info to Bank info */ + cpyDimm2BankInfo(&dimmInfo, pBankInfo); + return MV_OK; +} + +/******************************************************************************* +* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. +* +* DESCRIPTION: +* Convert a Dimm info struct into a bank info struct. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* pBankInfo - DRAM bank information struct. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, + MV_DRAM_BANK_INFO *pBankInfo) +{ + pBankInfo->memoryType = pDimmInfo->memoryType; + + /* DIMM dimensions */ + pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; + pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; + pBankInfo->dataWidth = pDimmInfo->dataWidth; + pBankInfo->errorCheckType = pDimmInfo->errorCheckType; + pBankInfo->sdramWidth = pDimmInfo->sdramWidth; + pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; + pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; + pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; + pBankInfo->refreshInterval = pDimmInfo->refreshInterval; + + /* DIMM timing parameters */ + pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; + pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; + pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; + + pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; + pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; + pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; + pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; + pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; + pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; + pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; + pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; + + /* Parameters calculated from the extracted DIMM information */ + pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; + pBankInfo->deviceDensity = pDimmInfo->deviceDensity; + pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / + pDimmInfo->numOfModuleBanks; + + /* DIMM attributes (MV_TRUE for yes) */ + + if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || + (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) + { + if (pDimmInfo->dimmAttributes & BIT1) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ + { + if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) + pBankInfo->registeredAddrAndControlInputs = MV_TRUE; + else + pBankInfo->registeredAddrAndControlInputs = MV_FALSE; + } + + return; +} +/******************************************************************************* +* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. +* +* DESCRIPTION: +* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdCpy(MV_VOID) +{ + MV_U32 i; + MV_U32 spdChecksum; + + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[SPD_SIZE]; + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the DIMM 1 SPD */ + twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + for(i = 0 ; i < SPD_SIZE ; i++) + { + twsiSlave.offset = i; + if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) + { + mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); + return MV_FAIL; + } + mvOsDelay(5); + } + + DB(puts("DRAM: Reading dimm info succeded.\n")); + return MV_OK; +} + +/******************************************************************************* +* dimmSpdGet - Get the SPD parameters. +* +* DESCRIPTION: +* Read the DIMM SPD parameters into given struct parameter. +* +* INPUT: +* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. +* +* OUTPUT: +* pDimmInfo - DIMM information structure. +* +* RETURN: +* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. +* +*******************************************************************************/ +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) +{ + MV_U32 i; + MV_U32 density = 1; + MV_U32 spdChecksum; + + MV_TWSI_SLAVE twsiSlave; + MV_U8 data[SPD_SIZE]; + + if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) + { + DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); + return MV_BAD_PARAM; + } + + /* zero dimmInfo structure */ + memset(data, 0, SPD_SIZE); + + /* read the dimm eeprom */ + DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); + twsiSlave.slaveAddr.address = (dimmNum == 0) ? + MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; + twsiSlave.slaveAddr.type = ADDR7_BIT; + twsiSlave.validOffset = MV_TRUE; + twsiSlave.offset = 0; + twsiSlave.moreThen256 = MV_FALSE; + + if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) + { + DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); + return MV_FAIL; + } + DB(puts("DRAM: Reading dimm info succeded.\n")); + + /* calculate SPD checksum */ + spdChecksum = 0; + + for(i = 0 ; i <= 62 ; i++) + { + spdChecksum += data[i]; + } + + if ((spdChecksum & 0xff) != data[63]) + { + DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", + (MV_U32)(spdChecksum & 0xff), data[63])); + } + else + { + DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); + } + + /* copy the SPD content 1:1 into the dimmInfo structure*/ + for(i = 0 ; i < SPD_SIZE ; i++) + { + pDimmInfo->spdRawData[i] = data[i]; + DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); + } + + DB(mvOsPrintf("DRAM SPD Information:\n")); + + /* Memory type (DDR / SDRAM) */ + switch (data[DIMM_MEM_TYPE]) + { + case (DIMM_MEM_TYPE_SDRAM): + pDimmInfo->memoryType = MEM_TYPE_SDRAM; + DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); + break; + case (DIMM_MEM_TYPE_DDR1): + pDimmInfo->memoryType = MEM_TYPE_DDR1; + DB(mvOsPrintf("DRAM Memeory type DDR1\n")); + break; + case (DIMM_MEM_TYPE_DDR2): + pDimmInfo->memoryType = MEM_TYPE_DDR2; + DB(mvOsPrintf("DRAM Memeory type DDR2\n")); + break; + default: + mvOsPrintf("ERROR: Undefined memory type!\n"); + return MV_ERROR; + } + + + /* Number Of Row Addresses */ + pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; + DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); + + /* Number Of Column Addresses */ + pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; + DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); + + /* Number Of Module Banks */ + pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", + pDimmInfo->numOfModuleBanks)); + + /* Number of module banks encoded differently for DDR2 */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; + + /* Data Width */ + pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; + DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); + + /* Minimum Cycle Time At Max CasLatancy */ + pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); + + /* Error Check Type */ + pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; + DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", + pDimmInfo->errorCheckType)); + + /* Refresh Interval */ + pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; + DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", + pDimmInfo->refreshInterval)); + + /* Sdram Width */ + pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; + DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); + + /* Error Check Data Width */ + pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; + DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", + pDimmInfo->errorCheckDataWidth)); + + /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + + pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; + DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", + pDimmInfo->burstLengthSupported)); + + /* Number Of Banks On Each Device */ + pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; + DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", + pDimmInfo->numOfBanksOnEachDevice)); + + /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; + DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", + pDimmInfo->suportedCasLatencies)); + + /* For DDR2 only, get the DIMM type information */ + if (pDimmInfo->memoryType == MEM_TYPE_DDR2) + { + pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; + DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", + pDimmInfo->dimmTypeInfo)); + } + + /* SDRAM Modules Attributes */ + pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; + DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", + pDimmInfo->dimmAttributes)); + + /* Minimum Cycle Time At Max CasLatancy Minus 1*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); + + /* Minimum Cycle Time At Max CasLatancy Minus 2*/ + pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = + cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); + + pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; + DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", + pDimmInfo->minRowPrechargeTime)); + pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; + DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", + pDimmInfo->minRowActiveToRowActive)); + pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; + DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", + pDimmInfo->minRasToCasDelay)); + pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; + DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", + pDimmInfo->minRasPulseWidth)); + + /* DIMM Bank Density */ + pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; + DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", + pDimmInfo->dimmBankDensity)); + + /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ + pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; + DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", + pDimmInfo->minWriteRecoveryTime)); + + /* Only DDR2 includes Internal Write To Read Command Delay field. */ + pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; + DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", + pDimmInfo->minWriteToReadCmdDelay)); + + /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ + pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; + DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", + pDimmInfo->minReadToPrechCmdDelay)); + + /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ + pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; + DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", + pDimmInfo->minRefreshToActiveCmd)); + + /* calculating the sdram density. Representing device density from */ + /* bit 20 to allow representation of 4GB and above. */ + /* For example, if density is 512Mbit 0x20000000, will be represent in */ + /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ + /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ + density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); + pDimmInfo->deviceDensity = density * + pDimmInfo->numOfBanksOnEachDevice * + pDimmInfo->sdramWidth; + DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); + + /* Number of devices includeing Error correction */ + pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * + pDimmInfo->numOfModuleBanks; + DB(mvOsPrintf("DRAM numberOfDevices %d\n", + pDimmInfo->numberOfDevices)); + + pDimmInfo->size = 0; + + /* Note that pDimmInfo->size is in MB units */ + if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 8; /* Equal to 8MB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 16; /* Equal to 16MB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 32; /* Equal to 32MB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 64; /* Equal to 64MB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (pDimmInfo->dimmBankDensity & BIT0) + pDimmInfo->size += 1024; /* Equal to 1GB */ + else if (pDimmInfo->dimmBankDensity & BIT1) + pDimmInfo->size += 2048; /* Equal to 2GB */ + else if (pDimmInfo->dimmBankDensity & BIT2) + pDimmInfo->size += 4096; /* Equal to 4GB */ + else if (pDimmInfo->dimmBankDensity & BIT3) + pDimmInfo->size += 8192; /* Equal to 8GB */ + else if (pDimmInfo->dimmBankDensity & BIT4) + pDimmInfo->size += 16384; /* Equal to 16GB */ + else if (pDimmInfo->dimmBankDensity & BIT5) + pDimmInfo->size += 128; /* Equal to 128MB */ + else if (pDimmInfo->dimmBankDensity & BIT6) + pDimmInfo->size += 256; /* Equal to 256MB */ + else if (pDimmInfo->dimmBankDensity & BIT7) + pDimmInfo->size += 512; /* Equal to 512MB */ + } + + pDimmInfo->size *= pDimmInfo->numOfModuleBanks; + + DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); + + return MV_OK; +} + +/******************************************************************************* +* dimmSpdPrint - Print the SPD parameters. +* +* DESCRIPTION: +* Print the Dimm SPD parameters. +* +* INPUT: +* pDimmInfo - DIMM information structure. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_VOID dimmSpdPrint(MV_U32 dimmNum) +{ + MV_DIMM_INFO dimmInfo; + MV_U32 i, temp = 0; + MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; + MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; + MV_U32 busClkPs; + MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, + temp_buf[40], *spdRawData; + + busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ + + spdRawData = dimmInfo.spdRawData; + + if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) + { + mvOsOutput("ERROR: Could not read SPD information!\n"); + return; + } + + /* find Manufactura of Dimm Module */ + mvOsOutput("\nManufacturer's JEDEC ID Code: "); + for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) + { + mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); + } + mvOsOutput("\n"); + + /* Manufacturer's Specific Data */ + for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; + } + mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); + + /* Module Part Number */ + for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) + { + temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; + } + mvOsOutput("Module Part Number: %s\n", temp_buf); + + /* Module Serial Number */ + for(i = 0; i < sizeof(MV_U32); i++) + { + temp |= spdRawData[95+i] << 8*i; + } + mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, + (long)temp); + + /* find Manufac-Data of Dimm Module */ + mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", + ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), + ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); + /* find modul_revision of Dimm Module */ + mvOsOutput("Module Revision: %d.%d\n", + spdRawData[62]/10, spdRawData[62]%10); + + /* find manufac_place of Dimm Module */ + mvOsOutput("manufac_place: %d\n", spdRawData[72]); + + /* go over the first 35 I2C data bytes */ + for(i = 2 ; i <= 35 ; i++) + switch(i) + { + case 2: /* Memory type (DDR1/2 / SDRAM) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + mvOsOutput("Dram Type is: SDRAM\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + mvOsOutput("Dram Type is: SDRAM DDR1\n"); + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + mvOsOutput("Dram Type is: SDRAM DDR2\n"); + else + mvOsOutput("Dram Type unknown\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 3: /* Number Of Row Addresses */ + mvOsOutput("Module Number of row addresses: %d\n", + dimmInfo.numOfRowAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 4: /* Number Of Column Addresses */ + mvOsOutput("Module Number of col addresses: %d\n", + dimmInfo.numOfColAddr); + break; +/*----------------------------------------------------------------------------*/ + + case 5: /* Number Of Module Banks */ + mvOsOutput("Number of Banks on Mod.: %d\n", + dimmInfo.numOfModuleBanks); + break; +/*----------------------------------------------------------------------------*/ + + case 6: /* Data Width */ + mvOsOutput("Module Data Width: %d bit\n", + dimmInfo.dataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 8: /* Voltage Interface */ + switch(spdRawData[i]) + { + case 0x0: + mvOsOutput("Module is TTL_5V_TOLERANT\n"); + break; + case 0x1: + mvOsOutput("Module is LVTTL\n"); + break; + case 0x2: + mvOsOutput("Module is HSTL_1_5V\n"); + break; + case 0x3: + mvOsOutput("Module is SSTL_3_3V\n"); + break; + case 0x4: + mvOsOutput("Module is SSTL_2_5V\n"); + break; + case 0x5: + if (dimmInfo.memoryType != MEM_TYPE_SDRAM) + { + mvOsOutput("Module is SSTL_1_8V\n"); + break; + } + default: + mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); + break; + } + break; +/*----------------------------------------------------------------------------*/ + + case 9: /* Minimum Cycle Time At Max CasLatancy */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 10: /* Clock To Data Out */ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 11: /* Error Check Type */ + mvOsOutput("Error Check Type (0=NONE): %d\n", + dimmInfo.errorCheckType); + break; +/*----------------------------------------------------------------------------*/ + + case 12: /* Refresh Interval */ + mvOsOutput("Refresh Rate: %x\n", + dimmInfo.refreshInterval); + break; +/*----------------------------------------------------------------------------*/ + + case 13: /* Sdram Width */ + mvOsOutput("Sdram Width: %d bits\n", + dimmInfo.sdramWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 14: /* Error Check Data Width */ + mvOsOutput("Error Check Data Width: %d bits\n", + dimmInfo.errorCheckDataWidth); + break; +/*----------------------------------------------------------------------------*/ + + case 15: /* Minimum Clock Delay is unsupported */ + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + mvOsOutput("Minimum Clk Delay back to back: %d\n", + spdRawData[i]); + } + break; +/*----------------------------------------------------------------------------*/ + + case 16: /* Burst Length Supported */ + /* SDRAM/DDR1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * + *********************************************************/ + /* DDR2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * + *********************************************************/ + mvOsOutput("Burst Length Supported: "); + if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || + (dimmInfo.memoryType == MEM_TYPE_DDR1)) + { + if (dimmInfo.burstLengthSupported & BIT0) + mvOsOutput("1, "); + if (dimmInfo.burstLengthSupported & BIT1) + mvOsOutput("2, "); + } + if (dimmInfo.burstLengthSupported & BIT2) + mvOsOutput("4, "); + if (dimmInfo.burstLengthSupported & BIT3) + mvOsOutput("8, "); + + mvOsOutput(" Bit \n"); + break; +/*----------------------------------------------------------------------------*/ + + case 17: /* Number Of Banks On Each Device */ + mvOsOutput("Number Of Banks On Each Chip: %d\n", + dimmInfo.numOfBanksOnEachDevice); + break; +/*----------------------------------------------------------------------------*/ + + case 18: /* Suported Cas Latencies */ + + /* SDRAM: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + ********************************************************/ + + /* DDR 1: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + *********************************************************/ + + /* DDR 2: + *******-******-******-******-******-******-******-******* + * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * + *******-******-******-******-******-******-******-******* + CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * + *********************************************************/ + + mvOsOutput("Suported Cas Latencies: (CL) "); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + for (k = 0; k <=7; k++) + { + if (dimmInfo.suportedCasLatencies & (1 << k)) + mvOsOutput("%d, ", k+1); + } + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.suportedCasLatencies & BIT0) + mvOsOutput("1, "); + if (dimmInfo.suportedCasLatencies & BIT1) + mvOsOutput("1.5, "); + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("2.5, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("3.5, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.suportedCasLatencies & BIT2) + mvOsOutput("2, "); + if (dimmInfo.suportedCasLatencies & BIT3) + mvOsOutput("3, "); + if (dimmInfo.suportedCasLatencies & BIT4) + mvOsOutput("4, "); + if (dimmInfo.suportedCasLatencies & BIT5) + mvOsOutput("5, "); + } + else + mvOsOutput("?.?, "); + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 20: /* DDR2 DIMM type info */ + if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) + mvOsOutput("Registered DIMM (RDIMM)\n"); + else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) + mvOsOutput("Unbuffered DIMM (UDIMM)\n"); + else + mvOsOutput("Unknown DIMM type.\n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 21: /* SDRAM Modules Attributes */ + mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" Bufferd DQMB Input: Yes \n"); + else + mvOsOutput(" Bufferd DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" Registered DQMB Inputs: Yes \n"); + else + mvOsOutput(" Registered DQMB Inputs: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" redundant Row Addressing: Yes \n"); + else + mvOsOutput(" redundant Row Addressing: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmAttributes & BIT0) + mvOsOutput(" Buffered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Buffered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT1) + mvOsOutput(" Registered Addr/Control Input: Yes\n"); + else + mvOsOutput(" Registered Addr/Control Input: No\n"); + + if (dimmInfo.dimmAttributes & BIT2) + mvOsOutput(" On-Card PLL (clock): Yes \n"); + else + mvOsOutput(" On-Card PLL (clock): No \n"); + + if (dimmInfo.dimmAttributes & BIT3) + mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); + else + mvOsOutput(" FET Switch On-Card Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT5) + mvOsOutput(" Differential Clock Input: Yes \n"); + else + mvOsOutput(" Differential Clock Input: No \n"); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + mvOsOutput(" Number of Active Registers on the DIMM: %d\n", + (dimmInfo.dimmAttributes & 0x3) + 1); + + mvOsOutput(" Number of PLLs on the DIMM: %d\n", + ((dimmInfo.dimmAttributes) >> 2) & 0x3); + + if (dimmInfo.dimmAttributes & BIT4) + mvOsOutput(" FET Switch External Enabled: Yes \n"); + else + mvOsOutput(" FET Switch External Enabled: No \n"); + + if (dimmInfo.dimmAttributes & BIT6) + mvOsOutput(" Analysis probe installed: Yes \n"); + else + mvOsOutput(" Analysis probe installed: No \n"); + } + + break; +/*----------------------------------------------------------------------------*/ + + case 22: /* Suported AutoPreCharge */ + mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Early Ras Precharge: Yes \n"); + else + mvOsOutput(" Early Ras Precharge: No \n"); + + if ( spdRawData[i] & BIT1 ) + mvOsOutput(" AutoPreCharge: Yes \n"); + else + mvOsOutput(" AutoPreCharge: No \n"); + + if ( spdRawData[i] & BIT2 ) + mvOsOutput(" Precharge All: Yes \n"); + else + mvOsOutput(" Precharge All: No \n"); + + if ( spdRawData[i] & BIT3 ) + mvOsOutput(" Write 1/ReadBurst: Yes \n"); + else + mvOsOutput(" Write 1/ReadBurst: No \n"); + + if ( spdRawData[i] & BIT4 ) + mvOsOutput(" lower VCC tolerance: 5%%\n"); + else + mvOsOutput(" lower VCC tolerance: 10%%\n"); + + if ( spdRawData[i] & BIT5 ) + mvOsOutput(" upper VCC tolerance: 5%%\n"); + else + mvOsOutput(" upper VCC tolerance: 10%%\n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + + if ( !(spdRawData[i] & BIT4) ) + mvOsOutput(" lower VCC tolerance: 0.2V\n"); + + if ( !(spdRawData[i] & BIT5) ) + mvOsOutput(" upper VCC tolerance: 0.2V\n"); + + if ( spdRawData[i] & BIT6 ) + mvOsOutput(" Concurrent Auto Preharge: Yes \n"); + else + mvOsOutput(" Concurrent Auto Preharge: No \n"); + + if ( spdRawData[i] & BIT7 ) + mvOsOutput(" Supports Fast AP: Yes \n"); + else + mvOsOutput(" Supports Fast AP: No \n"); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR2) + { + if ( spdRawData[i] & BIT0 ) + mvOsOutput(" Supports Weak Driver: Yes \n"); + else + mvOsOutput(" Supports Weak Driver: No \n"); + } + break; +/*----------------------------------------------------------------------------*/ + + case 23: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + + mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ + div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / div; + rightOfPoint = time_tmp % div; + mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 25: + /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + rightOfPoint = (spdRawData[i] & 0x0f) * 10; + + /* DDR2 addition of right of point */ + if ((spdRawData[i] & 0x0f) == 0xA) + { + rightOfPoint = 25; + } + if ((spdRawData[i] & 0x0f) == 0xB) + { + rightOfPoint = 33; + } + if ((spdRawData[i] & 0x0f) == 0xC) + { + rightOfPoint = 66; + } + if ((spdRawData[i] & 0x0f) == 0xD) + { + rightOfPoint = 75; + } + } + mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" + "(0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + leftOfPoint = (spdRawData[i] & 0xfc) >> 2; + rightOfPoint = (spdRawData[i] & 0x3) * 25; + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = 0; + rightOfPoint = time_tmp; + } + mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", + leftOfPoint, rightOfPoint ); + break; +/*----------------------------------------------------------------------------*/ + + case 27: /* Minimum Row Precharge Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ + trp_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 28: /* Minimum Row Active to Row Active Time */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trrd_clocks = (temp + (busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " + "%d.%d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 29: /* Minimum Ras-To-Cas Delay */ + shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; + maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0xff : 0xfc; + maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? + 0x00 : 0x03; + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); + rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; + temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ + trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; + mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " + "in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 30: /* Minimum Ras Pulse Width */ + tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; + mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " + "in Clk cycles %d\n", spdRawData[i], tras_clocks); + break; +/*----------------------------------------------------------------------------*/ + + case 31: /* Module Bank Density */ + mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); + + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("8MB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else if (dimmInfo.memoryType == MEM_TYPE_DDR1) + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("16MB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("32MB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("64MB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ + { + if (dimmInfo.dimmBankDensity & BIT0) + mvOsOutput("1GB, "); + if (dimmInfo.dimmBankDensity & BIT1) + mvOsOutput("2GB, "); + if (dimmInfo.dimmBankDensity & BIT2) + mvOsOutput("4GB, "); + if (dimmInfo.dimmBankDensity & BIT3) + mvOsOutput("8GB, "); + if (dimmInfo.dimmBankDensity & BIT4) + mvOsOutput("16GB, "); + if (dimmInfo.dimmBankDensity & BIT5) + mvOsOutput("128MB, "); + if (dimmInfo.dimmBankDensity & BIT6) + mvOsOutput("256MB, "); + if (dimmInfo.dimmBankDensity & BIT7) + mvOsOutput("512MB, "); + } + mvOsOutput("\n"); + break; +/*----------------------------------------------------------------------------*/ + + case 32: /* Address And Command Setup Time (measured in ns/1000) */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 33: /* Address And Command Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 34: /* Data Input Setup Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 35: /* Data Input Hold Time */ + if (dimmInfo.memoryType == MEM_TYPE_SDRAM) + { + rightOfPoint = (spdRawData[i] & 0x0f); + leftOfPoint = (spdRawData[i] & 0xf0) >> 4; + if(leftOfPoint > 7) + { + leftOfPoint *= -1; + } + } + else /* DDR1 or DDR2 */ + { + time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + + ((spdRawData[i] & 0x0f)); + leftOfPoint = time_tmp / 100; + rightOfPoint = time_tmp % 100; + } + mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + + case 36: /* Relevant for DDR2 only: Write Recovery Time */ + leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); + rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; + mvOsOutput("Write Recovery Time [ns]: %d.%d\n", + leftOfPoint, rightOfPoint); + break; +/*----------------------------------------------------------------------------*/ + } + +} + + +/* + * translate ns.ns/10 coding of SPD timing values + * into ps unit values + */ +/******************************************************************************* +* cas2ps - Translate x.y ns parameter to pico-seconds values +* +* DESCRIPTION: +* This function translates x.y nano seconds to its value in pico seconds. +* For example 3.75ns will return 3750. +* +* INPUT: +* spd_byte - DIMM SPD byte. +* +* OUTPUT: +* None. +* +* RETURN: +* value in pico seconds. +* +*******************************************************************************/ +static MV_U32 cas2ps(MV_U8 spd_byte) +{ + MV_U32 ns, ns10; + + /* isolate upper nibble */ + ns = (spd_byte >> 4) & 0x0F; + /* isolate lower nibble */ + ns10 = (spd_byte & 0x0F); + + if( ns10 < 10 ) { + ns10 *= 10; + } + else if( ns10 == 10 ) + ns10 = 25; + else if( ns10 == 11 ) + ns10 = 33; + else if( ns10 == 12 ) + ns10 = 66; + else if( ns10 == 13 ) + ns10 = 75; + else + { + mvOsOutput("cas2ps Err. unsupported cycle time.\n"); + } + + return (ns*1000 + ns10*10); +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h new file mode 100644 index 0000000..f955466 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h @@ -0,0 +1,192 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvDram +#define __INCmvDram + +#include "ddr2/mvDramIf.h" +#include "twsi/mvTwsi.h" + +#define MAX_DIMM_NUM 2 +#define SPD_SIZE 128 + +/* Dimm spd offsets */ +#define DIMM_MEM_TYPE 2 +#define DIMM_ROW_NUM 3 +#define DIMM_COL_NUM 4 +#define DIMM_MODULE_BANK_NUM 5 +#define DIMM_DATA_WIDTH 6 +#define DIMM_VOLT_IF 8 +#define DIMM_MIN_CC_AT_MAX_CAS 9 +#define DIMM_ERR_CHECK_TYPE 11 +#define DIMM_REFRESH_INTERVAL 12 +#define DIMM_SDRAM_WIDTH 13 +#define DIMM_ERR_CHECK_DATA_WIDTH 14 +#define DIMM_MIN_CLK_DEL 15 +#define DIMM_BURST_LEN_SUP 16 +#define DIMM_DEV_BANK_NUM 17 +#define DIMM_SUP_CAL 18 +#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ +#define DIMM_BUF_ADDR_CONT_IN 21 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 +#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 +#define DIMM_MIN_ROW_PRECHARGE_TIME 27 +#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 +#define DIMM_MIN_RAS_TO_CAS_DELAY 29 +#define DIMM_MIN_RAS_PULSE_WIDTH 30 +#define DIMM_BANK_DENSITY 31 +#define DIMM_MIN_WRITE_RECOVERY_TIME 36 +#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 +#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 +#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 +#define DIMM_SPD_VERSION 62 + +/* Dimm Memory Type values */ +#define DIMM_MEM_TYPE_SDRAM 0x4 +#define DIMM_MEM_TYPE_DDR1 0x7 +#define DIMM_MEM_TYPE_DDR2 0x8 + +#define DIMM_MODULE_MANU_OFFS 64 +#define DIMM_MODULE_MANU_SIZE 8 +#define DIMM_MODULE_VEN_OFFS 73 +#define DIMM_MODULE_VEN_SIZE 25 +#define DIMM_MODULE_ID_OFFS 99 +#define DIMM_MODULE_ID_SIZE 18 + +/* enumeration for voltage levels. */ +typedef enum _mvDimmVoltageIf +{ + TTL_5V_TOLERANT, + LVTTL, + HSTL_1_5V, + SSTL_3_3V, + SSTL_2_5V, + VOLTAGE_UNKNOWN, +} MV_DIMM_VOLTAGE_IF; + + +/* enumaration for SDRAM CAS Latencies. */ +typedef enum _mvDimmSdramCas +{ + SD_CL_1 =1, + SD_CL_2, + SD_CL_3, + SD_CL_4, + SD_CL_5, + SD_CL_6, + SD_CL_7, + SD_FAULT +}MV_DIMM_SDRAM_CAS; + + +/* DIMM information structure */ +typedef struct _mvDimmInfo +{ + MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ + + MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ + + /* DIMM dimensions */ + MV_U32 numOfRowAddr; + MV_U32 numOfColAddr; + MV_U32 numOfModuleBanks; + MV_U32 dataWidth; + MV_U32 errorCheckType; /* ECC , PARITY..*/ + MV_U32 sdramWidth; /* 4,8,16 or 32 */ + MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ + MV_U32 burstLengthSupported; + MV_U32 numOfBanksOnEachDevice; + MV_U32 suportedCasLatencies; + MV_U32 refreshInterval; + MV_U32 dimmBankDensity; + MV_U32 dimmTypeInfo; /* DDR2 only */ + MV_U32 dimmAttributes; + + /* DIMM timing parameters */ + MV_U32 minCycleTimeAtMaxCasLatPs; + MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; + MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; + MV_U32 minRowPrechargeTime; + MV_U32 minRowActiveToRowActive; + MV_U32 minRasToCasDelay; + MV_U32 minRasPulseWidth; + MV_U32 minWriteRecoveryTime; /* DDR2 only */ + MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ + MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ + MV_U32 minRefreshToActiveCmd; /* DDR2 only */ + + /* Parameters calculated from the extracted DIMM information */ + MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ + MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ + MV_U32 numberOfDevices; + +} MV_DIMM_INFO; + + +MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); +MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); +MV_VOID dimmSpdPrint(MV_U32 dimmNum); +MV_STATUS dimmSpdCpy(MV_VOID); + +#endif /* __INCmvDram */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c new file mode 100644 index 0000000..d24e788 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c @@ -0,0 +1,2952 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEth.c - Marvell's Gigabit Ethernet controller low level driver +* +* DESCRIPTION: +* This file introduce OS independent APIs to Marvell's Gigabit Ethernet +* controller. This Gigabit Ethernet Controller driver API controls +* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). +* 2) Data flow (i.e. port Send, Receive etc'). +* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) +* 4) MIB counters support (ethReadMibCounter) +* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) +* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. +* This struct includes configuration information as well as driver +* internal data needed for its operations. +* +* Supported Features: +* - OS independent. All required OS services are implemented via external +* OS dependent components (like osLayer or ethOsg) +* - The user is free from Rx/Tx queue managing. +* - Simple Gigabit Ethernet port operation API. +* - Simple Gigabit Ethernet port data flow API. +* - Data flow and operation API support per queue functionality. +* - Support cached descriptors for better performance. +* - PHY access and control API. +* - Port Configuration API. +* - Full control over Special and Other Multicast MAC tables. +* +*******************************************************************************/ +/* includes */ +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "eth-phy/mvEthPhy.h" +#include "eth/mvEth.h" +#include "eth/gbe/mvEthGbe.h" +#include "cpu/mvCpu.h" + +#ifdef INCLUDE_SYNC_BARR +#include "sys/mvCpuIf.h" +#endif + +#ifdef MV_RT_DEBUG +# define ETH_DEBUG +#endif + + +/* locals */ +MV_BOOL ethDescInSram; +MV_BOOL ethDescSwCoher; + +/* This array holds the control structure of each port */ +ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; + +/* Ethernet Port Local routines */ + +static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); + +static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); + +static void ethSetUcastTable(int portNo, int queue); + +static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); +static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); +static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); + +static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); +static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, + MV_ULONG* pPhysAddr, MV_U32 *memHandle); + +static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); + +static void mvEthPortSgmiiConfig(int port); + + + +/******************************************************************************/ +/* EthDrv Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthHalInit - Initialize the Giga Ethernet unit +* +* DESCRIPTION: +* This function initialize the Giga Ethernet unit. +* 1) Configure Address decode windows of the unit +* 2) Set registers to HW default values. +* 3) Clear and Disable interrupts +* +* INPUT: NONE +* +* RETURN: NONE +* +* NOTE: this function is called once in the boot process. +*******************************************************************************/ +void mvEthHalInit(void) +{ + int port; + + /* Init static data structures */ + for (port=0; port 0) + { + isSram = MV_TRUE; + #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) + isSwCoher = MV_TRUE; + #else + isSwCoher = MV_FALSE; + #endif + } +#endif /* ETH_DESCR_IN_SRAM */ + + if(pIsSram != NULL) + *pIsSram = isSram; + + if(pIsSwCoher != NULL) + *pIsSwCoher = isSwCoher; +} + + + +/******************************************************************************/ +/* Port Initialization functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthPortInit - Initialize the Ethernet port driver +* +* DESCRIPTION: +* This function initialize the ethernet port. +* 1) Allocate and initialize internal port Control structure. +* 2) Create RX and TX descriptor rings for default RX and TX queues +* 3) Disable RX and TX operations, clear cause registers and +* mask all interrupts. +* 4) Set all registers to default values and clean all MAC tables. +* +* INPUT: +* int portNo - Ethernet port number +* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure +* +* RETURN: +* void* - ethernet port handler, that should be passed to the most other +* functions dealing with this port. +* +* NOTE: This function is called once per port when loading the eth module. +*******************************************************************************/ +void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) +{ + int queue, descSize; + ETH_PORT_CTRL* pPortCtrl; + + /* Check validity of parameters */ + if( (portNo >= (int)mvCtrlEthMaxPortGet()) || + (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || + (pEthPortInit->maxRxPktSize < 1518) ) + { + mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); + return NULL; + } + if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) + { + mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", + portNo, pEthPortInit->rxDefQ); + return NULL; + } + + pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); + if(pPortCtrl == NULL) + { + mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", + (int)sizeof(ETH_PORT_CTRL), portNo); + return NULL; + } + + memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); + ethPortCtrl[portNo] = pPortCtrl; + + pPortCtrl->portState = MV_UNDEFINED_STATE; + + pPortCtrl->portNo = portNo; + + pPortCtrl->osHandle = pEthPortInit->osHandle; + + /* Copy Configuration parameters */ + pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; + pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; + pPortCtrl->portConfig.ejpMode = 0; + + for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; + } + for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; + } + + mvEthPortDisable(pPortCtrl); + + /* Set the board information regarding PHY address */ + mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); + + /* Create all requested RX queues */ + for(queue=0; queuerxQueueConfig[queue].descrNum == 0) + continue; + + /* Allocate memory for RX descriptors */ + descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + + CPU_D_CACHE_LINE_SIZE); + + pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = + ethAllocDescrMemory(pPortCtrl, descSize, + &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, + &pPortCtrl->rxQueue[queue].descBuf.memHandle); + pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; + if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) + { + mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", + pPortCtrl->portNo, queue, descSize, + ethDescInSram ? "SRAM" : "DRAM", + pPortCtrl->rxQueueConfig[queue].descrNum); + return NULL; + } + + ethInitRxDescRing(pPortCtrl, queue); + } + /* Create TX queues */ + for(queue=0; queuetxQueueConfig[queue].descrNum == 0) + continue; + + /* Allocate memory for TX descriptors */ + descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + + CPU_D_CACHE_LINE_SIZE); + + pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = + ethAllocDescrMemory(pPortCtrl, descSize, + &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, + &pPortCtrl->txQueue[queue].descBuf.memHandle); + pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; + if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) + { + mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", + pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", + pPortCtrl->txQueueConfig[queue].descrNum); + return NULL; + } + + ethInitTxDescRing(pPortCtrl, queue); + } + mvEthDefaultsSet(pPortCtrl); + + pPortCtrl->portState = MV_IDLE; + return pPortCtrl; +} + +/******************************************************************************* +* ethPortFinish - Finish the Ethernet port driver +* +* DESCRIPTION: +* This function finish the ethernet port. +* 1) Down ethernet port if needed. +* 2) Delete RX and TX descriptor rings for all created RX and TX queues +* 3) Free internal port Control structure. +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: NONE. +* +*******************************************************************************/ +void mvEthPortFinish(void* pPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + int queue, portNo = pPortCtrl->portNo; + + if(pPortCtrl->portState == MV_ACTIVE) + { + mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", + portNo); + mvEthPortDisable(pPortHndl); + } + + /* Free all allocated RX queues */ + for(queue=0; queuerxQueue[queue].descBuf); + } + + /* Free all allocated TX queues */ + for(queue=0; queuetxQueue[queue].descBuf); + } + + /* Free port control structure */ + mvOsFree(pPortCtrl); + + ethPortCtrl[portNo] = NULL; +} + +/******************************************************************************* +* mvEthDefaultsSet - Set defaults to the ethernet port +* +* DESCRIPTION: +* This function set default values to the ethernet port. +* 1) Clear Cause registers and Mask all interrupts +* 2) Clear all MAC tables +* 3) Set defaults to all registers +* 4) Reset all created RX and TX descriptors ring +* 5) Reset PHY +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure +* NOTE: +* This function update all the port configuration except those set +* Initialy by the OsGlue by MV_ETH_PORT_INIT. +* This function can be called after portDown to return the port setting +* to defaults. +*******************************************************************************/ +MV_STATUS mvEthDefaultsSet(void* pPortHndl) +{ + int ethPortNo, queue; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_U32 txPrio; + MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; + MV_BOARD_MAC_SPEED boardMacCfg; + + ethPortNo = pPortCtrl->portNo; + + /* Clear Cause registers */ + MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); + MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); + + /* Mask all interrupts */ + MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); + MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); + + portCfgReg = PORT_CONFIG_VALUE; + portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; + + boardMacCfg = mvBoardMacSpeedGet(ethPortNo); + + if(boardMacCfg == BOARD_MAC_SPEED_100M) + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; + } + else if(boardMacCfg == BOARD_MAC_SPEED_1000M) + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; + } + else + { + portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; + } + + /* build PORT_SDMA_CONFIG_REG */ + portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); + portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); + +#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ + (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) + /* some devices have restricted RX burst size when using HW coherency */ + portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); +#else + portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); +#endif + +#if defined(MV_CPU_BE) + /* big endian */ +# if defined(MV_ARM) + portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | + ETH_TX_NO_DATA_SWAP_MASK | + ETH_DESC_SWAP_MASK); +# elif defined(MV_PPC) + portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | + ETH_TX_DATA_SWAP_MASK | + ETH_NO_DESC_SWAP_MASK); +# else +# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" +# endif /* MV_ARM / MV_PPC */ + +#else /* MV_CPU_LE */ + /* little endian */ + portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | + ETH_TX_NO_DATA_SWAP_MASK | + ETH_NO_DESC_SWAP_MASK); +#endif /* MV_CPU_BE / MV_CPU_LE */ + + pPortCtrl->portRxQueueCmdReg = 0; + pPortCtrl->portTxQueueCmdReg = 0; + +#if (MV_ETH_VERSION >= 4) + if(pPortCtrl->portConfig.ejpMode == MV_TRUE) + { + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); + } + else + { + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) + } +#endif /* (MV_ETH_VERSION >= 4) */ + + ethSetUcastTable(ethPortNo, -1); + mvEthSetSpecialMcastTable(ethPortNo, -1); + mvEthSetOtherMcastTable(ethPortNo, -1); + + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + + portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); + + /* Update value of PortConfig register accordingly with all RxQueue types */ + pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; + pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; + + portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); + + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); + + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); + + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); + + /* Assignment of Tx CTRP of given queue */ + txPrio = 0; + + for(queue=0; queuetxQueue[queue]; + + if(pQueueCtrl->pFirstDescr != NULL) + { + ethResetTxDescRing(pPortCtrl, queue); + + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), + 0x3fffffff); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), + 0x03ffffff); + } + else + { + MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); + MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); + } + } + + /* Assignment of Rx CRDP of given queue */ + for(queue=0; queueportNo; + + if( (pPortCtrl->portState != MV_ACTIVE) && + (pPortCtrl->portState != MV_PAUSED) ) + { + mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", + ethPortNo, pPortCtrl->portState); + return MV_BAD_STATE; + } + + ethPortNo = pPortCtrl->portNo; + + /* Enable port RX. */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); + + /* Enable port TX. */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; + + pPortCtrl->portState = MV_ACTIVE; + + return MV_OK; +} + +/******************************************************************************* +* ethPortDown - Stop the Ethernet port activity. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE : used for port link down. +*******************************************************************************/ +MV_STATUS mvEthPortDown(void* pEthPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int ethPortNum = pPortCtrl->portNo; + unsigned int regData; + volatile int uDelay, mDelay; + + /* Stop Rx port activity. Check port Rx activity. */ + regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; + if(regData != 0) + { + /* Issue stop command for active channels only */ + MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); + } + + /* Stop Tx port activity. Check port Tx activity. */ + regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; + if(regData != 0) + { + /* Issue stop command for active channels only */ + MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), + (regData << ETH_TXQ_DISABLE_OFFSET) ); + } + + /* Force link down */ +/* + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); +*/ + /* Wait for all Rx activity to terminate. */ + mDelay = 0; + do + { + if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) + { + mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port RX Command register that all Rx queues are stopped */ + regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); + } + while(regData & 0xFF); + + /* Wait for all Tx activity to terminate. */ + mDelay = 0; + do + { + if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) + { + mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + /* Check port TX Command register that all Tx queues are stopped */ + regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); + } + while(regData & 0xFF); + + /* Double check to Verify that TX FIFO is Empty */ + mDelay = 0; + while(MV_TRUE) + { + do + { + if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) + { + mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", + ethPortNum, regData); + break; + } + mvOsDelay(1); + mDelay++; + + regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); + } + while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || + ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); + + if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) + break; + + /* Double check */ + regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); + if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && + ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) + { + break; + } + else + mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", + ethPortNum, mDelay, regData); + } + + /* Do NOT force link down */ +/* + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); +*/ + /* Wait about 2500 tclk cycles */ + uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); + mvOsUDelay(uDelay); + + pPortCtrl->portState = MV_PAUSED; + + return MV_OK; +} + + +/******************************************************************************* +* ethPortEnable - Enable the Ethernet port and Start RX and TX. +* +* DESCRIPTION: +* This routine enable the Ethernet port and Rx and Tx activity: +* +* Note: Each Rx and Tx queue descriptor's list must be initialized prior +* to calling this function (use etherInitTxDescRing for Tx queues and +* etherInitRxDescRing for Rx queues). +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE: main usage is to enable the port after ifconfig up. +*******************************************************************************/ +MV_STATUS mvEthPortEnable(void* pEthPortHndl) +{ + int ethPortNo; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + MV_U32 portSerialCtrlReg; + + ethPortNo = pPortCtrl->portNo; + + /* Enable port */ + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); + portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); + + mvEthMibCountersClear(pEthPortHndl); + + pPortCtrl->portState = MV_PAUSED; + + /* If Link is UP, Start RX and TX traffic */ + if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) + return( mvEthPortUp(pEthPortHndl) ); + + return MV_NOT_READY; +} + + +/******************************************************************************* +* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. +* +* DESCRIPTION: +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler +* +* RETURN: MV_STATUS +* MV_OK - Success, Others - Failure. +* +* NOTE: main usage is to disable the port after ifconfig down. +*******************************************************************************/ +MV_STATUS mvEthPortDisable(void* pEthPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int ethPortNum = pPortCtrl->portNo; + unsigned int regData; + volatile int mvDelay; + + if(pPortCtrl->portState == MV_ACTIVE) + { + /* Stop RX and TX activities */ + mvEthPortDown(pEthPortHndl); + } + + /* Reset the Enable bit in the Serial Control Register */ + regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); + regData &= ~(ETH_PORT_ENABLE_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); + + /* Wait about 2500 tclk cycles */ + mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); + for(mvDelay; mvDelay>0; mvDelay--); + + pPortCtrl->portState = MV_IDLE; + return MV_OK; +} + +/******************************************************************************* +* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. +* +* DESCRIPTION: +* This routine used to free buffers attached to the Tx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of TX queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. +* +* RETURN: +* MV_EMPTY - There is no more buffers in this queue. +* MV_OK - Buffer detached from the queue and pPktInfo structure +* filled with relevant information. +* +*******************************************************************************/ +MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_PKT_INFO* pPktInfo; + ETH_TX_DESC* pTxDesc; + int port = pPortCtrl->portNo; + + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || + (pQueueCtrl->resource == 0) ) + { + /* Free next descriptor */ + pQueueCtrl->resource++; + pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; + + /* pPktInfo is available only in descriptors which are last descriptors */ + pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; + if (pPktInfo) + pPktInfo->status = pTxDesc->cmdSts; + + pTxDesc->cmdSts = 0x0; + pTxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); + + pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); + + if (pPktInfo) + if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) + return pPktInfo; + } + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + return NULL; +} + + + +/******************************************************************************* +* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_EMPTY - There is no more buffers in this queue. +* MV_OK - Buffer detached from the queue and pBufInfo structure +* filled with relevant information. +* +*******************************************************************************/ +MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_RX_DESC* pRxDesc; + MV_PKT_INFO* pPktInfo; + int port = pPortCtrl->portNo; + + pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + if(pQueueCtrl->resource == 0) + { + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + + return NULL; + } + /* Free next descriptor */ + pQueueCtrl->resource--; + pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; + pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; + + pPktInfo->status = pRxDesc->cmdSts; + pRxDesc->cmdSts = 0x0; + pRxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); + + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); + return pPktInfo; +} + + +/******************************************************************************/ +/* Port Configuration functions */ +/******************************************************************************/ +/******************************************************************************* +* mvEthMruGet - Get MRU configuration for Max Rx packet size. +* +* INPUT: +* MV_U32 maxRxPktSize - max packet size. +* +* RETURN: MV_U32 - MRU configuration. +* +*******************************************************************************/ +static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) +{ + MV_U32 portSerialCtrlReg = 0; + + if(maxRxPktSize > 9192) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; + else if(maxRxPktSize > 9022) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; + else if(maxRxPktSize > 1552) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; + else if(maxRxPktSize > 1522) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; + else if(maxRxPktSize > 1518) + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; + else + portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; + + return portSerialCtrlReg; +} + +/******************************************************************************* +* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path +* +* DESCRIPTION: +* This routine sets the RX coalescing interrupt mechanism parameter. +* This parameter is a timeout counter, that counts in 64 tClk +* chunks, that when timeout event occurs a maskable interrupt occurs. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the required number is in micro seconds. +* +* INPUT: +* void* pPortHndl - Ethernet Port handler. +* MV_U32 uSec - Number of micro seconds between +* RX interrupts +* +* RETURN: +* None. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); + MV_U32 portSdmaCfgReg; + + portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); + portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; + + portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); + +#if (MV_ETH_VERSION >= 2) + /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ + if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) + portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; +#endif /* MV_ETH_VERSION >= 2 */ + + MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); + return coal; +} + +/******************************************************************************* +* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path +* +* DESCRIPTION: +* This routine sets the TX coalescing interrupt mechanism parameter. +* This parameter is a timeout counter, that counts in 64 tClk +* chunks, that when timeout event occurs a maskable interrupt +* occurs. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the required number is in micro seconds. +* +* INPUT: +* void* pPortHndl - Ethernet Port handler. +* MV_U32 uSec - Number of micro seconds between +* RX interrupts +* +* RETURN: +* None. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +*******************************************************************************/ +MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); + regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; + regVal |= ETH_TX_INTR_COAL_MASK(coal); + + /* Set TX Coalescing mechanism */ + MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); + return coal; +} + +/******************************************************************************* +* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds +* +* DESCRIPTION: +* This routine gets the RX and TX coalescing interrupt values. +* The parameter is calculated using the tCLK frequency of the +* MV-64xxx chip, and the returned numbers are in micro seconds. +* +* INPUTs: +* void* pPortHndl - Ethernet Port handler. +* +* OUTPUTs: +* MV_U32* pRxCoal - Number of micro seconds between RX interrupts +* MV_U32* pTxCoal - Number of micro seconds between TX interrupts +* +* RETURN: +* MV_STATUS MV_OK - success +* Others - failure. +* +* COMMENT: +* 1 sec - TCLK_RATE clocks +* 1 uSec - TCLK_RATE / 1,000,000 clocks +* +* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) +* +*******************************************************************************/ +MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) +{ + MV_U32 regVal, coal, usec; + + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + /* get TX Coalescing */ + regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); + coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); + + usec = (coal * 64) / (mvBoardTclkGet() / 1000000); + if(pTxCoal != NULL) + *pTxCoal = usec; + + /* Get RX Coalescing */ + regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); + coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); + +#if (MV_ETH_VERSION >= 2) + if(regVal & ETH_RX_INTR_COAL_MSB_MASK) + { + /* Add MSB */ + coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); + } +#endif /* MV_ETH_VERSION >= 2 */ + + usec = (coal * 64) / (mvBoardTclkGet() / 1000000); + if(pRxCoal != NULL) + *pRxCoal = usec; + + return MV_OK; +} + +/******************************************************************************* +* mvEthMaxRxSizeSet - +* +* DESCRIPTION: +* Change maximum receive size of the port. This configuration will take place +* after next call of ethPortSetDefaults() function. +* +* INPUT: +* +* RETURN: +*******************************************************************************/ +MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + MV_U32 portSerialCtrlReg; + + if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) + return MV_BAD_PARAM; + + pPortCtrl->portConfig.maxRxPktSize = maxRxSize; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); + portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; + portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); + + return MV_OK; +} + + +/******************************************************************************/ +/* MAC Filtering functions */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port +* +* DESCRIPTION: +* This routine used to free buffers attached to the Rx ring and should +* be called only when Giga Ethernet port is Down +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* MV_BOOL isPromisc - Promiscous mode +* MV_TRUE - accept all Broadcast, Multicast +* and Unicast packets +* MV_FALSE - accept all Broadcast, +* specially added Multicast and +* single Unicast packets +* +* RETURN: MV_STATUS MV_OK - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + int queue; + MV_U32 portCfgReg; + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + /* Set / Clear UPM bit in port configuration register */ + if(isPromisc) + { + /* Accept all multicast packets to RX default queue */ + queue = pPortCtrl->portConfig.rxDefQ; + portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; + memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); + } + else + { + /* Reject all Multicast addresses */ + queue = -1; + portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; + /* Clear all mcastCount */ + memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); + } + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + /* Set Special Multicast and Other Multicast tables */ + mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); + mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); + ethSetUcastTable(pPortCtrl->portNo, queue); + + return MV_OK; +} + +/******************************************************************************* +* mvEthMacAddrSet - This function Set the port Unicast address. +* +* DESCRIPTION: +* This function Set the port Ethernet MAC address. This address +* will be used to send Pause frames if enabled. Packets with this +* address will be accepted and dispatched to default RX queue +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler. +* char* pAddr - Address to be set +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + unsigned int macH; + unsigned int macL; + + if(queue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); + return MV_BAD_PARAM; + } + + if(queue != -1) + { + macL = (pAddr[4] << 8) | (pAddr[5]); + macH = (pAddr[0] << 24)| (pAddr[1] << 16) | + (pAddr[2] << 8) | (pAddr[3] << 0); + + MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); + MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); + } + + /* Accept frames of this address */ + ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); + + return MV_OK; +} + +/******************************************************************************* +* mvEthMacAddrGet - This function returns the port Unicast address. +* +* DESCRIPTION: +* This function returns the port Ethernet MAC address. +* +* INPUT: +* int portNo - Ethernet port number. +* char* pAddr - Pointer where address will be written to +* +* RETURN: MV_STATUS +* MV_OK - Success, Other - Faulure +* +*******************************************************************************/ +MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) +{ + unsigned int macH; + unsigned int macL; + + if(pAddr == NULL) + { + mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); + return MV_BAD_PARAM; + } + + macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); + macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); + pAddr[0] = (macH >> 24) & 0xff; + pAddr[1] = (macH >> 16) & 0xff; + pAddr[2] = (macH >> 8) & 0xff; + pAddr[3] = macH & 0xff; + pAddr[4] = (macL >> 8) & 0xff; + pAddr[5] = macL & 0xff; + + return MV_OK; +} + +/******************************************************************************* +* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. +* +* DESCRIPTION: +* +* INPUT: +* MV_U8* pAddr - Address to calculate CRC-8 +* +* RETURN: MV_U8 - CRC-8 of this MAC address +* +*******************************************************************************/ +MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) +{ + unsigned int macH; + unsigned int macL; + int macArray[48]; + int crc[8]; + int i; + unsigned char crcResult = 0; + + /* Calculate CRC-8 out of the given address */ + macH = (pAddr[0] << 8) | (pAddr[1]); + macL = (pAddr[2] << 24)| (pAddr[3] << 16) | + (pAddr[4] << 8) | (pAddr[5] << 0); + + for(i=0; i<32; i++) + macArray[i] = (macL >> i) & 0x1; + + for(i=32; i<48; i++) + macArray[i] = (macH >> (i - 32)) & 0x1; + + crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ + macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ + macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ + macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ + macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; + + crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ + macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ + macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ + macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ + macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ + macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; + + crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ + macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ + macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ + macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ + macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ + macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; + + crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ + macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ + macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ + macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ + macArray[3] ^ macArray[2] ^ macArray[1]; + + crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ + macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ + macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ + macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ + macArray[3] ^ macArray[2]; + + crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ + macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ + macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ + macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ + macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ + macArray[4] ^ macArray[3]; + + crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ + macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ + macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ + macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ + macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ + macArray[4]; + + crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ + macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ + macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ + macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ + macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; + + for(i=0; i<8; i++) + crcResult = crcResult | (crc[i] << i); + + return crcResult; +} +/******************************************************************************* +* mvEthMcastAddrSet - Multicast address settings. +* +* DESCRIPTION: +* This API controls the MV device MAC multicast support. +* The MV device supports multicast using two tables: +* 1) Special Multicast Table for MAC addresses of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* In this case, the function calls ethPortSmcAddr() routine to set the +* Special Multicast Table. +* 2) Other Multicast Table for multicast of another type. A CRC-8bit +* is used as an index to the Other Multicast Table entries in the +* DA-Filter table. +* In this case, the function calculates the CRC-8bit value and calls +* ethPortOmcAddr() routine to set the Other Multicast Table. +* +* INPUT: +* void* pEthPortHndl - Ethernet port handler. +* MV_U8* pAddr - Address to be set +* int queue - RX queue to capture all packets with this +* Multicast MAC address. +* -1 means delete this Multicast address. +* +* RETURN: MV_STATUS +* MV_TRUE - Success, Other - Failure +* +*******************************************************************************/ +MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + unsigned char crcResult = 0; + + if(queue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", + pPortCtrl->portNo, queue); + return MV_BAD_PARAM; + } + + if((pAddr[0] == 0x01) && + (pAddr[1] == 0x00) && + (pAddr[2] == 0x5E) && + (pAddr[3] == 0x00) && + (pAddr[4] == 0x00)) + { + ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); + } + else + { + crcResult = mvEthMcastCrc8Get(pAddr); + + /* Check Add counter for this CRC value */ + if(queue == -1) + { + if(pPortCtrl->mcastCount[crcResult] == 0) + { + mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, (unsigned)crcResult); + return MV_NO_SUCH; + } + + pPortCtrl->mcastCount[crcResult]--; + if(pPortCtrl->mcastCount[crcResult] != 0) + { + mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", + pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], + (unsigned)crcResult); + return MV_NO_CHANGE; + } + } + else + { + pPortCtrl->mcastCount[crcResult]++; + if(pPortCtrl->mcastCount[crcResult] > 1) + { + mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", + pPortCtrl->portNo, (unsigned)crcResult); + return MV_NO_CHANGE; + } + } + ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); + } + return MV_OK; +} + +/******************************************************************************* +* ethSetUcastTable - Unicast address settings. +* +* DESCRIPTION: +* Set all entries in the Unicast MAC Table queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +static void ethSetUcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xC; offset+=4) + MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); +} + +/******************************************************************************* +* mvEthSetSpecialMcastTable - Special Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xFC; offset+=4) + { + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + + offset), regValue); + } +} + +/******************************************************************************* +* mvEthSetOtherMcastTable - Other Multicast address settings. +* +* DESCRIPTION: +* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all +* INPUT: +* +* RETURN: +* +*******************************************************************************/ +MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) +{ + int offset; + MV_U32 regValue; + + if(queue == -1) + { + regValue = 0; + } + else + { + regValue = (((0x01 | (queue<<1)) << 0) | + ((0x01 | (queue<<1)) << 8) | + ((0x01 | (queue<<1)) << 16) | + ((0x01 | (queue<<1)) << 24)); + } + + for (offset=0; offset<=0xFC; offset+=4) + { + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + + offset), regValue); + } +} + +/******************************************************************************* +* ethSetUcastAddr - This function Set the port unicast address table +* +* DESCRIPTION: +* This function locates the proper entry in the Unicast table for the +* specified MAC nibble and sets its properties according to function +* parameters. +* +* INPUT: +* int ethPortNum - Port number. +* MV_U8 lastNibble - Unicast MAC Address last nibble. +* int queue - Rx queue number for this MAC address. +* value "-1" means remove address +* +* OUTPUT: +* This function add/removes MAC addresses from the port unicast address +* table. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) +{ + unsigned int unicastReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the Unicast table entry */ + lastNibble = (0xf & lastNibble); + tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ + regOffset = lastNibble % 4; /* Entry offset within the above register */ + + + unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + + tblOffset)); + + + if(queue == -1) + { + /* Clear accepts frame bit at specified unicast DA table entry */ + unicastReg &= ~(0xFF << (8*regOffset)); + } + else + { + unicastReg &= ~(0xFF << (8*regOffset)); + unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); + } + MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), + unicastReg); + + return MV_TRUE; +} + +/******************************************************************************* +* ethSetSpecialMcastAddr - Special Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device special MAC multicast support. +* The Special Multicast Table for MAC addresses supports MAC of the form +* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). +* The MAC DA[7:0] bits are used as a pointer to the Special Multicast +* Table entries in the DA-Filter table. +* This function set the Special Multicast Table appropriate entry +* according to the argument given. +* +* INPUT: +* int ethPortNum Port number. +* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). +* int queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) +{ + unsigned int smcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the SMC table entry */ + tblOffset = (lastByte / 4); /* Register offset from SMC table base */ + regOffset = lastByte % 4; /* Entry offset within the above register */ + + smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); + + if(queue == -1) + { + /* Clear accepts frame bit at specified Special DA table entry */ + smcTableReg &= ~(0xFF << (8 * regOffset)); + } + else + { + smcTableReg &= ~(0xFF << (8 * regOffset)); + smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); + } + MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + + tblOffset*4), smcTableReg); + + return MV_TRUE; +} + +/******************************************************************************* +* ethSetOtherMcastAddr - Multicast address settings. +* +* DESCRIPTION: +* This routine controls the MV device Other MAC multicast support. +* The Other Multicast Table is used for multicast of another type. +* A CRC-8bit is used as an index to the Other Multicast Table entries +* in the DA-Filter table. +* The function gets the CRC-8bit value from the calling routine and +* set the Other Multicast Table appropriate entry according to the +* CRC-8 argument given. +* +* INPUT: +* int ethPortNum Port number. +* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* int queue Rx queue number for this MAC address. +* +* OUTPUT: +* See description. +* +* RETURN: +* MV_TRUE is output succeeded. +* MV_FALSE if option parameter is invalid. +* +*******************************************************************************/ +static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) +{ + unsigned int omcTableReg; + unsigned int tblOffset; + unsigned int regOffset; + + /* Locate the OMC table entry */ + tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ + regOffset = crc8 % 4; /* Entry offset within the above register */ + + omcTableReg = MV_REG_READ( + (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); + + if(queue == -1) + { + /* Clear accepts frame bit at specified Other DA table entry */ + omcTableReg &= ~(0xFF << (8 * regOffset)); + } + else + { + omcTableReg &= ~(0xFF << (8 * regOffset)); + omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); + } + + MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), + omcTableReg); + + return MV_TRUE; +} + + +/******************************************************************************/ +/* MIB Counters functions */ +/******************************************************************************/ + + +/******************************************************************************* +* mvEthMibCounterRead - Read a MIB counter +* +* DESCRIPTION: +* This function reads a MIB counter of a specific ethernet port. +* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or +* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, +* so pHigh32 pointer should not be NULL in this case. +* +* INPUT: +* int ethPortNum - Ethernet Port number. +* unsigned int mibOffset - MIB counter offset. +* +* OUTPUT: +* MV_U32* pHigh32 - pointer to place where 32 most significant bits +* of the counter will be stored. +* +* RETURN: +* 32 low sgnificant bits of MIB counter value. +* +*******************************************************************************/ +MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, + MV_U32* pHigh32) +{ + int portNo; + MV_U32 valLow32, valHigh32; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + + portNo = pPortCtrl->portNo; + + valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); + + /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ + /* of a 64-bit MIB Counter. */ + if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || + (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) + { + valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); + if(pHigh32 != NULL) + *pHigh32 = valHigh32; + } + return valLow32; +} + +/******************************************************************************* +* mvEthMibCountersClear - Clear all MIB counters +* +* DESCRIPTION: +* This function clears all MIB counters +* +* INPUT: +* int ethPortNum - Ethernet Port number. +* +* +* RETURN: void +* +*******************************************************************************/ +void mvEthMibCountersClear(void* pPortHandle) +{ + int i, portNo; + unsigned int dummy; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + + portNo = pPortCtrl->portNo; + + /* Perform dummy reads from MIB counters */ + for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) + { + mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); + return -1; + } + regIdx = mvOsDivide(tos>>2, 10); + regOffs = mvOsReminder(tos>>2, 10); + + regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); + rxq = (regValue >> (regOffs*3)); + rxq &= 0x7; + + return rxq; +} + +/******************************************************************************* +* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue +* +* DESCRIPTION: +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int tos - TOS value in the IP header of the packet +* int rxq - RX Queue for packets with the configured TOS value +* Negative value (-1) means no special processing for these packets, +* so they will be processed as regular packets. +* +* RETURN: MV_STATUS +*******************************************************************************/ +MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) +{ + MV_U32 regValue; + int regIdx, regOffs; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + + if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) + { + mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); + return MV_BAD_PARAM; + } + if(tos > 0xFF) + { + mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); + return MV_BAD_PARAM; + } + regIdx = mvOsDivide(tos>>2, 10); + regOffs = mvOsReminder(tos>>2, 10); + + regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); + regValue &= ~(0x7 << (regOffs*3)); + regValue |= (rxq << (regOffs*3)); + + MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); + return MV_OK; +} + +/******************************************************************************* +* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with +* special priority bits [0-2] +* +* DESCRIPTION: +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int bpduQueue - Special queue to capture VLAN tagged packets with special +* priority. +* Negative value (-1) means no special processing for these packets, +* so they will be processed as regular packets. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 vlanPrioReg; + + if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); + return MV_BAD_PARAM; + } + if(vlanPrio >= 8) + { + mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); + return MV_BAD_PARAM; + } + + vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); + vlanPrioReg &= ~(0x7 << (vlanPrio*3)); + vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); + MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. +* +* DESCRIPTION: +* This function defines processing of BPDU packets. +* BPDU packets can be accepted and captured to one of RX queues +* or can be processing as regular Multicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int bpduQueue - Special queue to capture BPDU packets (DA is equal to +* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, +* except for the Flow-Control Pause packets). +* Negative value (-1) means no special processing for BPDU, +* packets so they will be processed as regular Multicast packets. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + MV_U32 portCfgExtReg; + + if(bpduQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); + return MV_BAD_PARAM; + } + + portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + if(bpduQueue >= 0) + { + pPortCtrl->portConfig.rxBpduQ = bpduQueue; + + portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxBpduQ = -1; + /* no special processing for BPDU packets */ + portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); + } + + MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthArpRxQueue - Configure RX queue to capture ARP packets. +* +* DESCRIPTION: +* This function defines processing of ARP (type=0x0806) packets. +* ARP packets can be accepted and captured to one of RX queues +* or can be processed as other Broadcast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int arpQueue - Special queue to capture ARP packets (type=0x806). +* Negative value (-1) means discard ARP packets +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(arpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(arpQueue >= 0) + { + pPortCtrl->portConfig.rxArpQ = arpQueue; + portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); + + portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); + } + else + { + pPortCtrl->portConfig.rxArpQ = -1; + portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. +* +* DESCRIPTION: +* This function defines processing of TCP packets. +* TCP packets can be accepted and captured to one of RX queues +* or can be processed as regular Unicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int tcpQueue - Special queue to capture TCP packets. Value "-1" +* means no special processing for TCP packets, +* so they will be processed as regular +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(tcpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); + return MV_BAD_PARAM; + } + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(tcpQueue >= 0) + { + pPortCtrl->portConfig.rxTcpQ = tcpQueue; + portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); + + portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxTcpQ = -1; + portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************* +* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. +* +* DESCRIPTION: +* This function defines processing of UDP packets. +* TCP packets can be accepted and captured to one of RX queues +* or can be processed as regular Unicast packets. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int udpQueue - Special queue to capture UDP packets. Value "-1" +* means no special processing for UDP packets, +* so they will be processed as regular +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_FAIL - Failed. +* +*******************************************************************************/ +MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + MV_U32 portCfgReg; + + if(udpQueue >= MV_ETH_RX_Q_NUM) + { + mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); + return MV_BAD_PARAM; + } + + portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); + + if(udpQueue >= 0) + { + pPortCtrl->portConfig.rxUdpQ = udpQueue; + portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; + portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); + + portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + } + else + { + pPortCtrl->portConfig.rxUdpQ = -1; + portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; + } + + MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); + + return MV_OK; +} + + +/******************************************************************************/ +/* Speed, Duplex, FlowControl routines */ +/******************************************************************************/ + +/******************************************************************************* +* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. +* +* DESCRIPTION: +* This function configure the port to work with desirable Duplex and Speed. +* Changing of these parameters are allowed only when port is disabled. +* This function disable the port if was enabled, change duplex and speed +* and, enable the port back if needed. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* ETH_PORT_SPEED speed - Speed of the port. +* ETH_PORT_SPEED duplex - Duplex of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. +* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) +* is not valid +* +*******************************************************************************/ +MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, + MV_ETH_PORT_DUPLEX duplex) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 portSerialCtrlReg; + + if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + /* Check validity */ + if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) + return MV_BAD_PARAM; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + /* Set Speed */ + switch(speed) + { + case MV_ETH_SPEED_AN: + portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; + break; + + case MV_ETH_SPEED_10: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; + break; + + case MV_ETH_SPEED_100: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; + portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; + break; + + case MV_ETH_SPEED_1000: + portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); + return MV_BAD_VALUE; + } + /* Set duplex */ + switch(duplex) + { + case MV_ETH_DUPLEX_AN: + portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + break; + + case MV_ETH_DUPLEX_HALF: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; + break; + + case MV_ETH_DUPLEX_FULL: + portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); + return MV_BAD_VALUE; + } + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthFlowCtrlSet - Set Flow Control of the port. +* +* DESCRIPTION: +* This function configure the port to work with desirable Duplex and +* Speed. Changing of these parameters are allowed only when port is +* disabled. This function disable the port if was enabled, change +* duplex and speed and, enable the port back if needed. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_PORT_FC flowControl - Flow control of the port. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_VALUE - Value flowControl parameters is not valid +* +*******************************************************************************/ +MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 portSerialCtrlReg; + + if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + switch(flowControl) + { + case MV_ETH_FC_AN_ADV_DIS: + portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_AN_ADV_SYM: + portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; + break; + + case MV_ETH_FC_DISABLE: + portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; + break; + + case MV_ETH_FC_ENABLE: + portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; + portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; + break; + + default: + mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); + return MV_BAD_VALUE; + } + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); + + return MV_OK; +} + +/******************************************************************************* +* mvEthHeaderModeSet - Set port header mode. +* +* DESCRIPTION: +* This function configures the port to work in Marvell-Header mode. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. +* +* RETURN: MV_STATUS +* MV_OK - Success +* MV_NOT_SUPPORTED- Feature not supported. +* MV_OUT_OF_RANGE - Failed. Port is out of valid range +* MV_NOT_FOUND - Failed. Port is not initialized. +* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. +* +*******************************************************************************/ +MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + MV_U32 mvHeaderReg; + MV_U32 numRxQ = MV_ETH_RX_Q_NUM; + + if((port < 0) || (port >= mvCtrlEthMaxPortGet())) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); + /* Disable header mode. */ + mvHeaderReg &= ~ETH_MVHDR_EN_MASK; + + if(headerMode != MV_ETH_DISABLE_HEADER_MODE) + { + /* Enable Header mode. */ + mvHeaderReg |= ETH_MVHDR_EN_MASK; + + /* Clear DA-Prefix & MHMask fields.*/ + mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); + + if(numRxQ > 1) + { + switch (headerMode) + { + case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; + break; + case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; + break; + case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): + mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; + break; + default: + break; + } + + switch (numRxQ) + { + case (4): + mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; + break; + case (8): + mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; + break; + default: + break; + } + } + } + + MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); + + return MV_OK; +} + +#if (MV_ETH_VERSION >= 4) +/******************************************************************************* +* mvEthEjpModeSet - Enable / Disable EJP policy for TX. +* +* DESCRIPTION: +* This function +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* MV_BOOL TRUE - enable EJP mode +* FALSE - disable EJP mode +* +* OUTPUT: MV_STATUS +* MV_OK - Success +* Other - Failure +* +* RETURN: None. +* +*******************************************************************************/ +MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + + if((port < 0) || (port >= mvCtrlEthMaxPortGet())) + return MV_OUT_OF_RANGE; + + pPortCtrl = ethPortCtrl[port]; + if(pPortCtrl == NULL) + return MV_NOT_FOUND; + + pPortCtrl->portConfig.ejpMode = mode; + if(mode) + { + /* EJP enabled */ + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); + } + else + { + /* EJP disabled */ + MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); + } + mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", + port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), + MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); + + return MV_OK; +} +#endif /* MV_ETH_VERSION >= 4 */ + +/******************************************************************************* +* mvEthStatusGet - Get major properties of the port . +* +* DESCRIPTION: +* This function get major properties of the port (link, speed, duplex, +* flowControl, etc) and return them using the single structure. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* OUTPUT: +* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status +* will be placed. +* +* RETURN: None. +* +*******************************************************************************/ +void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + + MV_U32 regValue; + + regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); + + if(regValue & ETH_GMII_SPEED_1000_MASK) + pStatus->speed = MV_ETH_SPEED_1000; + else if(regValue & ETH_MII_SPEED_100_MASK) + pStatus->speed = MV_ETH_SPEED_100; + else + pStatus->speed = MV_ETH_SPEED_10; + + if(regValue & ETH_LINK_UP_MASK) + pStatus->isLinkUp = MV_TRUE; + else + pStatus->isLinkUp = MV_FALSE; + + if(regValue & ETH_FULL_DUPLEX_MASK) + pStatus->duplex = MV_ETH_DUPLEX_FULL; + else + pStatus->duplex = MV_ETH_DUPLEX_HALF; + + + if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) + pStatus->flowControl = MV_ETH_FC_ENABLE; + else + pStatus->flowControl = MV_ETH_FC_DISABLE; +} + + +/******************************************************************************/ +/* PHY Control Functions */ +/******************************************************************************/ + + +/******************************************************************************* +* mvEthPhyAddrSet - Set the ethernet port PHY address. +* +* DESCRIPTION: +* This routine set the ethernet port PHY address according to given +* parameter. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* int phyAddr - PHY address +* +* RETURN: +* None. +* +*******************************************************************************/ +void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + regData &= ~ETH_PHY_ADDR_MASK; + regData |= phyAddr; + + MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); + + return; +} + +/******************************************************************************* +* mvEthPhyAddrGet - Get the ethernet port PHY address. +* +* DESCRIPTION: +* This routine returns the given ethernet port PHY address. +* +* INPUT: +* void* pPortHandle - Pointer to port specific handler; +* +* +* RETURN: int - PHY address. +* +*******************************************************************************/ +int mvEthPhyAddrGet(void* pPortHandle) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; + int port = pPortCtrl->portNo; + unsigned int regData; + + regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); + + return ((regData >> (5 * port)) & 0x1f); +} + +/******************************************************************************/ +/* Descriptor handling Functions */ +/******************************************************************************/ + +/******************************************************************************* +* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. +* +* DESCRIPTION: +* This function prepares a Rx chained list of descriptors and packet +* buffers in a form of a ring. The routine must be called after port +* initialization routine and before port start routine. +* The Ethernet SDMA engine uses CPU bus addresses to access the various +* devices in the system (i.e. DRAM). This function uses the ethernet +* struct 'virtual to physical' routine (set by the user) to set the ring +* with physical addresses. +* +* INPUT: +* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. +* int rxQueue Number of Rx queue. +* int rxDescNum Number of Rx descriptors +* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. +* +* OUTPUT: +* The routine updates the Ethernet port control struct with information +* regarding the Rx descriptors and buffers. +* +* RETURN: None +* +*******************************************************************************/ +static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) +{ + ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; + int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; + + /* Make sure descriptor address is cache line size aligned */ + pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pRxDesc = (ETH_RX_DESC*)pRxDescBase; + pRxPrevDesc = pRxDesc; + + /* initialize the Rx descriptors ring */ + for (ix=0; ixbufSize = 0x0; + pRxDesc->byteCnt = 0x0; + pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pRxDesc->bufPtr = 0x0; + pRxDesc->returnInfo = 0x0; + pRxPrevDesc = pRxDesc; + if(ix == (rxDescNum-1)) + { + /* Closing Rx descriptors ring */ + pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); + } + else + { + pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); + pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); + } + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); + } + + pQueueCtrl->pCurrentDescr = pRxDescBase; + pQueueCtrl->pUsedDescr = pRxDescBase; + + pQueueCtrl->pFirstDescr = pRxDescBase; + pQueueCtrl->pLastDescr = pRxDesc; + pQueueCtrl->resource = 0; +} + +void ethResetRxDescRing(void* pPortHndl, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; + ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; + + pQueueCtrl->resource = 0; + if(pQueueCtrl->pFirstDescr != NULL) + { + while(MV_TRUE) + { + pRxDesc->bufSize = 0x0; + pRxDesc->byteCnt = 0x0; + pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pRxDesc->bufPtr = 0x0; + pRxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); + if( (void*)pRxDesc == pQueueCtrl->pLastDescr) + break; + pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); + } + pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; + pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; + + /* Update RX Command register */ + pPortCtrl->portRxQueueCmdReg |= (1 << queue); + + /* update HW */ + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + } + else + { + /* Update RX Command register */ + pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); + + /* update HW */ + MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); + } +} + +/******************************************************************************* +* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. +* +* DESCRIPTION: +* This function prepares a Tx chained list of descriptors and packet +* buffers in a form of a ring. The routine must be called after port +* initialization routine and before port start routine. +* The Ethernet SDMA engine uses CPU bus addresses to access the various +* devices in the system (i.e. DRAM). This function uses the ethernet +* struct 'virtual to physical' routine (set by the user) to set the ring +* with physical addresses. +* +* INPUT: +* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. +* int txQueue Number of Tx queue. +* int txDescNum Number of Tx descriptors +* int txBuffSize Size of Tx buffer +* MV_U8* pTxDescBase Tx descriptors memory area base addr. +* +* OUTPUT: +* The routine updates the Ethernet port control struct with information +* regarding the Tx descriptors and buffers. +* +* RETURN: None. +* +*******************************************************************************/ +static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) +{ + ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; + int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; + ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; + + /* Make sure descriptor address is cache line size aligned */ + pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, + CPU_D_CACHE_LINE_SIZE); + + pTxDesc = (ETH_TX_DESC*)pTxDescBase; + pTxPrevDesc = pTxDesc; + + /* initialize the Tx descriptors ring */ + for (ix=0; ixbyteCnt = 0x0000; + pTxDesc->L4iChk = 0x0000; + pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pTxDesc->bufPtr = 0x0; + pTxDesc->returnInfo = 0x0; + + pTxPrevDesc = pTxDesc; + + if(ix == (txDescNum-1)) + { + /* Closing Tx descriptors ring */ + pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); + } + else + { + pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); + pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); + } + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); + } + + pQueueCtrl->pCurrentDescr = pTxDescBase; + pQueueCtrl->pUsedDescr = pTxDescBase; + + pQueueCtrl->pFirstDescr = pTxDescBase; + pQueueCtrl->pLastDescr = pTxDesc; + /* Leave one TX descriptor out of use */ + pQueueCtrl->resource = txDescNum - 1; +} + +void ethResetTxDescRing(void* pPortHndl, int queue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; + ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; + + pQueueCtrl->resource = 0; + if(pQueueCtrl->pFirstDescr != NULL) + { + while(MV_TRUE) + { + pTxDesc->byteCnt = 0x0000; + pTxDesc->L4iChk = 0x0000; + pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; + pTxDesc->bufPtr = 0x0; + pTxDesc->returnInfo = 0x0; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); + pQueueCtrl->resource++; + if( (void*)pTxDesc == pQueueCtrl->pLastDescr) + break; + pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); + } + /* Leave one TX descriptor out of use */ + pQueueCtrl->resource--; + pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; + pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; + + /* Update TX Command register */ + pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); + /* update HW */ + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), + (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); + } + else + { + /* Update TX Command register */ + pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); + /* update HW */ + MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); + } +} + +/******************************************************************************* +* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function allocates memory for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. +* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. +* +* INPUT: +* int size - size of memory should be allocated. +* +* RETURN: None +* +*******************************************************************************/ +static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, + MV_ULONG* pPhysAddr, MV_U32 *memHandle) +{ + MV_U8* pVirt; + +#if defined(ETH_DESCR_IN_SRAM) + if(ethDescInSram == MV_TRUE) + pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); + else +#endif /* ETH_DESCR_IN_SRAM */ + { +#ifdef ETH_DESCR_UNCACHED + pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, + pPhysAddr,memHandle); +#else + pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, + pPhysAddr, memHandle); +#endif /* ETH_DESCR_UNCACHED */ + } + memset(pVirt, 0, descSize); + + return pVirt; +} + +/******************************************************************************* +* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. +* +* DESCRIPTION: +* This function frees memory allocated for RX and TX descriptors. +* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. +* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. +* +* INPUT: +* void* pVirtAddr - virtual pointer to memory allocated for RX and TX +* desriptors. +* +* RETURN: None +* +*******************************************************************************/ +void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) +{ + if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) + return; + +#if defined(ETH_DESCR_IN_SRAM) + if( ethDescInSram ) + { + mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); + return; + } +#endif /* ETH_DESCR_IN_SRAM */ + +#ifdef ETH_DESCR_UNCACHED + mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr,pDescBuf->memHandle); +#else + mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, + pDescBuf->bufVirtPtr,pDescBuf->memHandle); +#endif /* ETH_DESCR_UNCACHED */ +} + +/******************************************************************************/ +/* Other Functions */ +/******************************************************************************/ + +void mvEthPortPowerUp(int port) +{ + MV_U32 regVal; + + /* MAC Cause register should be cleared */ + MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); + + if (mvBoardIsPortInSgmii(port)) + mvEthPortSgmiiConfig(port); + + /* Cancel Port Reset */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + regVal &= (~ETH_PORT_RESET_MASK); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); + while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); +} + +void mvEthPortPowerDown(int port) +{ + MV_U32 regVal; + + /* Port must be DISABLED */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); + if( (regVal & ETH_PORT_ENABLE_MASK) != 0) + { + mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", + port, regVal); + return; + } + + /* Port Reset (Read after write the register as a precaution) */ + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); + while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); +} + +static void mvEthPortSgmiiConfig(int port) +{ + MV_U32 regVal; + + regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); + + regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); + regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); + + MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); +} + + + + + + + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c new file mode 100644 index 0000000..f533475 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c @@ -0,0 +1,748 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEthDebug.c - Source file for user friendly debug functions +* +* DESCRIPTION: +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#include "mvOs.h" +#include "mvCommon.h" +#include "mvTypes.h" +#include "mv802_3.h" +#include "mvDebug.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "eth-phy/mvEthPhy.h" +#include "eth/mvEth.h" +#include "eth/gbe/mvEthDebug.h" + +/* #define mvOsPrintf printf */ + +void mvEthPortShow(void* pHndl); +void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); + +/******************************************************************************/ +/* Debug functions */ +/******************************************************************************/ +void ethRxCoal(int port, int usec) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthRxCoalSet(pHndl, usec); + } +} + +void ethTxCoal(int port, int usec) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthTxCoalSet(pHndl, usec); + } +} + +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthEjpModeSet(pHndl, mode); + } +} +#endif /* (MV_ETH_VERSION >= 4) */ + +void ethBpduRxQ(int port, int bpduQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthBpduRxQueue(pHndl, bpduQueue); + } +} + +void ethArpRxQ(int port, int arpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthArpRxQueue(pHndl, arpQueue); + } +} + +void ethTcpRxQ(int port, int tcpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthTcpRxQueue(pHndl, tcpQueue); + } +} + +void ethUdpRxQ(int port, int udpQueue) +{ + void* pHndl; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvEthUdpRxQueue(pHndl, udpQueue); + } +} + +void ethTxPolicyRegs(int port) +{ + int queue; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); + + if(pPortCtrl == NULL) + { + return; + } + mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", + port, pPortCtrl->portConfig.ejpMode); + for(queue=0; queuetxQueueConfig[queue].descrNum > 0) + mvOsPrintf("%d, ", queue); + } + mvOsPrintf("\n"); + + mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); + + mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", + ETH_TX_QUEUE_COMMAND_REG(port), + MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); + + mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", + ETH_TX_FIXED_PRIO_CFG_REG(port), + MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_RATE_CFG_REG(port), + MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); + + mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", + ETH_MAX_TRANSMIT_UNIT_REG(port), + MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_BUCKET_SIZE_REG(port), + MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); + + mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", + ETH_TX_TOKEN_BUCKET_COUNT_REG(port), + MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); + + for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), + ((macH >> 8) & 0xff), (macH & 0xff), + ((macL >> 8) & 0xff), (macL & 0xff) ); + + for (i=0; i<4; i++) + { + unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); + for(j=0; j<4; j++) + { + MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; + + mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, + (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); + } + } +} + +void ethMcastAdd(int port, char* macStr, int queue) +{ + void* pHndl; + MV_U8 macAddr[MV_MAC_ADDR_SIZE]; + + pHndl = mvEthPortHndlGet(port); + if(pHndl != NULL) + { + mvMacStrToHex(macStr, macAddr); + mvEthMcastAddrSet(pHndl, macAddr, queue); + } +} + +void ethPortMcast(int port) +{ + int tblIdx, regIdx; + MV_U32 regVal; + + mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", + port); + + for(tblIdx=0; tblIdx<(256/4); tblIdx++) + { + regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); + for(regIdx=0; regIdx<4; regIdx++) + { + if((regVal & (0x01 << (regIdx*8))) != 0) + { + mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", + tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); + } + } + } + mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); + for(tblIdx=0; tblIdx<(256/4); tblIdx++) + { + regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); + for(regIdx=0; regIdx<4; regIdx++) + { + if((regVal & (0x01 << (regIdx*8))) != 0) + { + mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", + tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); + } + } + } +} + + +/* Print status of Ethernet port */ +void mvEthPortShow(void* pHndl) +{ + MV_U32 regValue, rxCoal, txCoal; + int speed, queue, port; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; + + port = pPortCtrl->portNo; + + regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); + + mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", + port, ETH_PORT_STATUS_REG(port), regValue); + + mvOsPrintf("descInSram=%d, descSwCoher=%d\n", + ethDescInSram, ethDescSwCoher); + + if(regValue & ETH_GMII_SPEED_1000_MASK) + speed = 1000; + else if(regValue & ETH_MII_SPEED_100_MASK) + speed = 100; + else + speed = 10; + + mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); + + /* Link, Speed, Duplex, FlowControl */ + mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", + (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", + speed, + (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", + (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); + + mvOsPrintf("\n"); + + mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", + rxCoal, txCoal); + + mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", + pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, + pPortCtrl->portConfig.rxBpduQ, + pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); + + /* Print all RX and TX queues */ + for(queue=0; queuerxQueue[queue].pFirstDescr, + mvEthRxResourceGet(pPortCtrl, queue) ); + } + mvOsPrintf("\n"); + for(queue=0; queuetxQueue[queue].pFirstDescr, + mvEthTxResourceGet(pPortCtrl, queue) ); + } +} + +/* Print RX and TX queue of the Ethernet port */ +void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) +{ + ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; + ETH_QUEUE_CTRL *pQueueCtrl; + MV_U32 regValue; + ETH_RX_DESC *pRxDescr; + ETH_TX_DESC *pTxDescr; + int i, port = pPortCtrl->portNo; + + if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) + { + pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); + mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); + + mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", + ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), + MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); + + + if(pQueueCtrl->pFirstDescr != NULL) + { + mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", + (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, + pQueueCtrl->resource); + mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", + (MV_ULONG)pQueueCtrl->pCurrentDescr, + (MV_ULONG)pQueueCtrl->pUsedDescr); + + if(mode == 1) + { + pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; + i = 0; + do + { + mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", + i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), + pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, + (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, + ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); + + ETH_DESCR_INV(pPortCtrl, pRxDescr); + pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); + i++; + } while (pRxDescr != pQueueCtrl->pFirstDescr); + } + } + else + mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); + } + + if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) + { + pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); + mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); + + regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); + mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", + ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); + + if(pQueueCtrl->pFirstDescr != NULL) + { + mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", + (MV_ULONG)pQueueCtrl->pFirstDescr, + (MV_ULONG)pQueueCtrl->pLastDescr, + pQueueCtrl->resource); + mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", + (MV_ULONG)pQueueCtrl->pCurrentDescr, + (MV_ULONG)pQueueCtrl->pUsedDescr); + + if(mode == 1) + { + pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; + i = 0; + do + { + mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", + i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), + pTxDescr->cmdSts, pTxDescr->byteCnt, + (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, + pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); + + ETH_DESCR_INV(pPortCtrl, pTxDescr); + pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); + i++; + } while (pTxDescr != pQueueCtrl->pFirstDescr); + } + } + else + mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); + } +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h new file mode 100644 index 0000000..f026f96 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h @@ -0,0 +1,146 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __MV_ETH_DEBUG_H__ +#define __MV_ETH_DEBUG_H__ + +#if 0 +/* + ** Externs + */ +void ethBpduRxQ(int port, int bpduQueue); +void ethArpRxQ(int port, int bpduQueue); +void ethTcpRxQ(int port, int bpduQueue); +void ethUdpRxQ(int port, int bpduQueue); +void ethMcastAdd(int port, char* macStr, int queue); + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolicy( int port); +void ethTxPolicy( int port); +void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); +void ethRxPolQ(int port, int rxQueue, int rxQuota); +#endif /* INCLUDE_MULTI_QUEUE */ + +void print_egiga_stat(void *sc, unsigned int port); +void ethPortStatus (int port); +void ethPortQueues( int port, int rxQueue, int txQueue, int mode); +void ethPortMcast(int port); +void ethPortRegs(int port); +void ethPortCounters(int port); +void ethPortRmonCounters(int port); +void ethRxCoal(int port, int usec); +void ethTxCoal(int port, int usec); + +void ethRegs(int port); +void ethClearCounters(int port); +void ethUcastSet(int port, char* macStr, int queue); +void ethPortUcastShow(int port); + +#ifdef CONFIG_MV_ETH_HEADER +void run_com_header(const char *buffer); +#endif + +#ifdef INCLUDE_MULTI_QUEUE +void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); +void ethRxPolQ(int port, int queue, int quota); +void ethRxPolicy(int port); +void ethTxPolDef(int port, int txQ, char* headerHexStr); +void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); +void ethTxPolicy(int port); +#endif /* INCLUDE_MULTI_QUEUE */ + +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode) +#endif +#endif /* 0 */ + + + + +void ethRxCoal(int port, int usec); +void ethTxCoal(int port, int usec); +#if (MV_ETH_VERSION >= 4) +void ethEjpModeSet(int port, int mode); +#endif /* (MV_ETH_VERSION >= 4) */ + +void ethBpduRxQ(int port, int bpduQueue); +void ethArpRxQ(int port, int arpQueue); +void ethTcpRxQ(int port, int tcpQueue); +void ethUdpRxQ(int port, int udpQueue); +void ethTxPolicyRegs(int port); +void ethPortRegs(int port); +void ethRegs(int port); +void ethClearCounters(int port); +void ethPortCounters(int port); +void ethPortRmonCounters(int port); +void ethPortStatus(int port); +void ethPortQueues(int port, int rxQueue, int txQueue, int mode); +void ethUcastSet(int port, char* macStr, int queue); +void ethPortUcastShow(int port); +void ethMcastAdd(int port, char* macStr, int queue); +void ethPortMcast(int port); +void mvEthPortShow(void* pHndl); +void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); + +#endif diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h new file mode 100644 index 0000000..f4cae50 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h @@ -0,0 +1,751 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/******************************************************************************* +* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller +* +* DESCRIPTION: +* This header file contains macros typedefs and function declaration specific to +* the Marvell Gigabit Ethernet Controller. +* +* DEPENDENCIES: +* None. +* +*******************************************************************************/ + +#ifndef __mvEthGbe_h__ +#define __mvEthGbe_h__ + +extern MV_BOOL ethDescInSram; +extern MV_BOOL ethDescSwCoher; +extern ETH_PORT_CTRL* ethPortCtrl[]; + +static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) +{ +#if defined (ETH_DESCR_IN_SRAM) + if( ethDescInSram ) + return mvSramVirtToPhy(pDesc); + else +#endif /* ETH_DESCR_IN_SRAM */ + return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); +} +/* Return port handler */ +#define mvEthPortHndlGet(port) ethPortCtrl[port] + +/* Used as WA for HW/SW race on TX */ +static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) +{ + int deep = 0; + MV_U32 txCurrReg, txEnReg; + ETH_TX_DESC* pTxLastDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); + if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) + { + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; + return 0; + } + + pQueueCtrl = &pPortCtrl->txQueue[queue]; + pTxLastDesc = pQueueCtrl->pCurrentDescr; + txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); + if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) + { + /* All descriptors are processed, no chance for race */ + return 0; + } + + /* Check distance betwee HW and SW location: */ + /* If distance between HW and SW pointers is less than max_deep descriptors */ + /* Race condition is possible, so wait end of TX and restart TXQ */ + while(deep < max_deep) + { + pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); + if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) + { + int count = 0; + + while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) + { + count++; + if(count > 10000) + { + mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", + MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); + break; + } + txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); + } + + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; + return count; + } + deep++; + } + /* Distance between HW and SW pointers is more than max_deep descriptors, */ + /* So NO race condition - do nothing */ + return -1; +} + + +/* defines */ +#define ETH_CSUM_MIN_BYTE_COUNT 72 + +/* Tailgate and Kirwood have only 2K TX FIFO */ +#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) +#define ETH_CSUM_MAX_BYTE_COUNT 1600 +#else +#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 +#endif /* MV_ETH_VERSION */ + +#define ETH_MV_HEADER_SIZE 2 +#define ETH_MV_TX_EN + +/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ +#define MIN_TX_BUFF_LOAD 8 +#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) + +/* Default port configuration value */ +#define PORT_CONFIG_VALUE \ + ETH_DEF_RX_QUEUE_MASK(0) | \ + ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ + ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ + ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ + ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ + ETH_RX_CHECKSUM_WITH_PSEUDO_HDR + +/* Default port extend configuration value */ +#define PORT_CONFIG_EXTEND_VALUE 0 + +#define PORT_SERIAL_CONTROL_VALUE \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE | \ + ETH_SET_FULL_DUPLEX_MASK + +#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ + ETH_FORCE_LINK_PASS_MASK | \ + ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ + ETH_SET_FULL_DUPLEX_MASK | \ + ETH_SET_MII_SPEED_100_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + + +#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ + ETH_FORCE_LINK_PASS_MASK | \ + ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ + ETH_SET_FULL_DUPLEX_MASK | \ + ETH_SET_GMII_SPEED_1000_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + +#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ + ETH_DISABLE_FC_AUTO_NEG_MASK | \ + BIT9 | \ + ETH_IN_BAND_AN_EN_MASK | \ + ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ + ETH_MAX_RX_PACKET_1552BYTE + +/* Function headers: */ +MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); +MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); +MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); +MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); +MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); +MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); +MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); +/* Interrupt Coalesting functions */ +MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); +MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); +MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); + +/******************************************************************************/ +/* Data Flow functions */ +/******************************************************************************/ +static INLINE void mvEthPortTxRestart(void* pPortHndl) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; +} + +/* Get number of Free resources in specific TX queue */ +static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + return (pPortCtrl->txQueue[txQueue].resource); +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + return (pPortCtrl->rxQueue[rxQueue].resource); +} + +static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + if(pPortCtrl->txQueue[txQueue].resource == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + return MV_TRUE; + + return MV_FALSE; +} + +static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + { + return MV_TRUE; + } + return MV_FALSE; +} + +/* Get number of Free resources in specific RX queue */ +static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) +{ + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; + + if(pPortCtrl->rxQueue[rxQueue].resource == 0) + return MV_TRUE; + + return MV_FALSE; +} + +/******************************************************************************* +* mvEthPortTx - Send an Ethernet packet +* +* DESCRIPTION: +* This routine send a given packet described by pPktInfo parameter. +* Single buffer only. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* MV_PKT_INFO *pPktInfo - User packet to send. +* +* RETURN: +* MV_NO_RESOURCE - No enough resources to send this packet. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - Packet send successfully. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) +{ + ETH_TX_DESC* pTxCurrDesc; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + int portNo; + MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; + +#ifdef ETH_DEBUG + if(pPortCtrl->portState != MV_ACTIVE) + return MV_BAD_STATE; +#endif /* ETH_DEBUG */ + + portNo = pPortCtrl->portNo; + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + /* Get the Tx Desc ring indexes */ + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + /* Check if there is enough resources to send the packet */ + if(pQueueCtrl->resource == 0) + return MV_NO_RESOURCE; + + pTxCurrDesc->byteCnt = pBufInfo->dataSize; + + /* Flash Buffer */ + if(pPktInfo->pktSize != 0) + { +#ifdef MV_NETBSD + pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; + ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); +#else + pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); +#endif + pPktInfo->pktSize = 0; + } + else + pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; + + pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; + + /* There is only one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxCurrDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_FIRST_DESC_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + + pQueueCtrl->resource--; + pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + + /* Apply send command */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; + + return MV_OK; +} + + +/******************************************************************************* +* mvEthPortSgTx - Send an Ethernet packet +* +* DESCRIPTION: +* This routine send a given packet described by pBufInfo parameter. It +* supports transmitting of a packet spaned over multiple buffers. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* MV_PKT_INFO *pPktInfo - User packet to send. +* +* RETURN: +* MV_NO_RESOURCE - No enough resources to send this packet. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - Packet send successfully. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) +{ + ETH_TX_DESC* pTxFirstDesc; + ETH_TX_DESC* pTxCurrDesc; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + int portNo, bufCount; + MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; + MV_U8* pTxBuf; + +#ifdef ETH_DEBUG + if(pPortCtrl->portState != MV_ACTIVE) + return MV_BAD_STATE; +#endif /* ETH_DEBUG */ + + portNo = pPortCtrl->portNo; + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + /* Get the Tx Desc ring indexes */ + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + /* Check if there is enough resources to send the packet */ + if(pQueueCtrl->resource < pPktInfo->numFrags) + return MV_NO_RESOURCE; + + /* Remember first desc */ + pTxFirstDesc = pTxCurrDesc; + + bufCount = 0; + while(MV_TRUE) + { + if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) + { + /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ + /* to 64-bit boundary. Two options here: */ + /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ + /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ + /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ + pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; + mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); + pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); + } + else + { + /* Flash Buffer */ +#ifdef MV_NETBSD + pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; + ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); +#else + pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); +#endif + } + + pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; + bufCount++; + + if(bufCount >= pPktInfo->numFrags) + break; + + if(bufCount > 1) + { + /* There is middle buffer of the packet Not First and Not Last */ + pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + } + /* Go to next descriptor and next buffer */ + pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + } + /* Set last desc with DMA ownership and interrupt enable. */ + pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; + if(bufCount == 1) + { + /* There is only one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxCurrDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_FIRST_DESC_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + } + else + { + /* Last but not First */ + pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_ENABLE_INTERRUPT_MASK | + ETH_TX_ZERO_PADDING_MASK | + ETH_TX_LAST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); + + /* Update First when more than one buffer in the packet */ + /* The OSG might set some bits for checksum offload, so add them to first descriptor */ + pTxFirstDesc->cmdSts = pPktInfo->status | + ETH_BUFFER_OWNED_BY_DMA | + ETH_TX_GENERATE_CRC_MASK | + ETH_TX_FIRST_DESC_MASK; + + ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); + } + /* Update txQueue state */ + pQueueCtrl->resource -= bufCount; + pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); + + /* Apply send command */ + MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; + + return MV_OK; +} + +/******************************************************************************* +* mvEthPortTxDone - Free all used Tx descriptors and mBlks. +* +* DESCRIPTION: +* This routine returns the transmitted packet information to the caller. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int txQueue - Number of Tx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. +* +* RETURN: +* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. +* MV_EMPTY - No transmitted packets to return. TX Queue is empty. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - There is transmitted packet in the queue, +* 'pPktInfo' filled with relevant information. +* +*******************************************************************************/ +static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) +{ + ETH_TX_DESC* pTxCurrDesc; + ETH_TX_DESC* pTxUsedDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + MV_PKT_INFO* pPktInfo; + MV_U32 commandStatus; + + pQueueCtrl = &pPortCtrl->txQueue[txQueue]; + + pTxUsedDesc = pQueueCtrl->pUsedDescr; + pTxCurrDesc = pQueueCtrl->pCurrentDescr; + + while(MV_TRUE) + { + /* No more used descriptors */ + commandStatus = pTxUsedDesc->cmdSts; + if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) + { + ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); + return NULL; + } + if( (pTxUsedDesc == pTxCurrDesc) && + (pQueueCtrl->resource != 0) ) + { + return NULL; + } + pQueueCtrl->resource++; + pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); + if(commandStatus & (ETH_TX_LAST_DESC_MASK)) + { + pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; + pPktInfo->status = commandStatus; + return pPktInfo; + } + pTxUsedDesc = pQueueCtrl->pUsedDescr; + } +} + +/******************************************************************************* +* mvEthPortRx - Get new received packets from Rx queue. +* +* DESCRIPTION: +* This routine returns the received data to the caller. There is no +* data copying during routine operation. All information is returned +* using pointer to packet information struct passed from the caller. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* +* OUTPUT: +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_NO_RESOURCE - No free resources in RX queue. +* MV_ERROR - Unexpected Fatal error. +* MV_OK - New packet received and 'pBufInfo' structure filled +* with relevant information. +* +*******************************************************************************/ +static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) +{ + ETH_RX_DESC *pRxCurrDesc; + MV_U32 commandStatus; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + ETH_QUEUE_CTRL* pQueueCtrl; + MV_PKT_INFO* pPktInfo; + + pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); + + /* Check resources */ + if(pQueueCtrl->resource == 0) + { + mvOsPrintf("ethPortRx: no more resources\n"); + return NULL; + } + while(MV_TRUE) + { + /* Get the Rx Desc ring 'curr and 'used' indexes */ + pRxCurrDesc = pQueueCtrl->pCurrentDescr; + + commandStatus = pRxCurrDesc->cmdSts; + if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) + { + /* Nothing to receive... */ + ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); + return NULL; + } + + /* Valid RX only if FIRST and LAST bits are set */ + if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == + (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) + { + pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; + pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; + pPktInfo->status = commandStatus; + pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; + + pQueueCtrl->resource--; + /* Update 'curr' in data structure */ + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); + +#ifdef INCLUDE_SYNC_BARR + mvCpuIfSyncBarr(DRAM_TARGET); +#endif + return pPktInfo; + } + else + { + ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; + +#ifdef ETH_DEBUG + mvOsPrintf("ethDrv: Unexpected Jumbo frame: " + "status=0x%08x, byteCnt=%d, pData=0x%x\n", + commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); +#endif /* ETH_DEBUG */ + + /* move buffer from pCurrentDescr position to pUsedDescr position */ + pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; + pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; + pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; + + /* Return the descriptor to DMA ownership */ + pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | + ETH_RX_ENABLE_INTERRUPT_MASK; + + /* Flush descriptor and CPU pipe */ + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); + + /* Move the used descriptor pointer to the next descriptor */ + pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); + pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); + } + } +} + +/******************************************************************************* +* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. +* +* DESCRIPTION: +* This routine returns a Rx buffer back to the Rx ring. +* +* INPUT: +* void* pEthPortHndl - Ethernet Port handler. +* int rxQueue - Number of Rx queue. +* MV_PKT_INFO *pPktInfo - Pointer to received packet. +* +* RETURN: +* MV_ERROR - Unexpected Fatal error. +* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be +* returned to this queue. +* MV_FULL - Buffer returned successfully and RX queue became full. +* More buffers should not be returned at the time. +* MV_OK - Buffer returned successfully and there are more free +* places in the queue. +* +*******************************************************************************/ +static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) +{ + ETH_RX_DESC* pRxUsedDesc; + ETH_QUEUE_CTRL* pQueueCtrl; + ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; + + pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; + + /* Get 'used' Rx descriptor */ + pRxUsedDesc = pQueueCtrl->pUsedDescr; + + /* Check that ring is not FULL */ + if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && + (pQueueCtrl->resource != 0) ) + { + mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", + __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, + pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); + return MV_OUT_OF_RANGE; + } + + pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; + pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; + pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; + + /* Invalidate data buffer accordingly with pktSize */ + if(pPktInfo->pktSize != 0) + { + ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); + pPktInfo->pktSize = 0; + } + + /* Return the descriptor to DMA ownership */ + pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; + + /* Flush descriptor and CPU pipe */ + ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); + + pQueueCtrl->resource++; + + /* Move the used descriptor pointer to the next descriptor */ + pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); + + /* If ring became Full return MV_FULL */ + if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) + return MV_FULL; + + return MV_OK; +} + + +#endif /* __mvEthGbe_h__ */ + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h new file mode 100644 index 0000000..7b9f052 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h @@ -0,0 +1,700 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCmvEthRegsh +#define __INCmvEthRegsh + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/****************************************/ +/* Ethernet Unit Registers */ +/****************************************/ +#define ETH_REG_BASE MV_ETH_REG_BASE + +#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) +#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) +#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) +#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) +#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) +#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) +#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) + + +#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) +#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) +#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) + +#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) +#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) +#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) +#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) +#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) +#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) +#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) +#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) +#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) +#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) +#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) +#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) + +#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) +#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) + +#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) +#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) +#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) +#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) +#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) +#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) +#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) +#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) +#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) +#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) +#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) +#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) +#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) +#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) +#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) +#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) +#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) +#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) +#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) +#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) +#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) +#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) +#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) +#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) +#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) + +#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) +#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) +#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) + +#if (MV_ETH_VERSION >= 4) +#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) +#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) +#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) +#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) +#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) +#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) +#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) +#endif /* MV_ETH_VERSION >= 4 */ + +#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) +#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) +#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) +#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) + +/* Phy address register definitions */ +#define ETH_PHY_ADDR_OFFS 0 +#define ETH_PHY_ADDR_MASK (0x1f <= 4) +#define ETH_TX_EJP_RESET_BIT 0 +#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) + +#define ETH_TX_EJP_ENABLE_BIT 2 +#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) + +#define ETH_TX_LEGACY_WRR_BIT 3 +#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) +#endif /* (MV_ETH_VERSION >= 4) */ + +/***** BITs of Ethernet Port Status reg (PSR) *****/ +#define ETH_LINK_UP_BIT 1 +#define ETH_LINK_UP_MASK (1<= 4) +MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); +#endif /* (MV_ETH_VERSION >= 4) */ + +void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); + +/* Marvell Header control */ +MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); + +/* PHY routines */ +void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); +int mvEthPhyAddrGet(void* pPortHandle); + +/* Power management routines */ +void mvEthPortPowerDown(int port); +void mvEthPortPowerUp(int port); + +/******************** ETH PRIVATE ************************/ + +/*#define UNCACHED_TX_BUFFERS*/ +/*#define UNCACHED_RX_BUFFERS*/ + + +/* Port attributes */ +/* Size of a Tx/Rx descriptor used in chain list data structure */ +#define ETH_RX_DESC_ALIGNED_SIZE 32 +#define ETH_TX_DESC_ALIGNED_SIZE 32 + +#define TX_DISABLE_TIMEOUT_MSEC 1000 +#define RX_DISABLE_TIMEOUT_MSEC 1000 +#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 +#define PORT_DISABLE_WAIT_TCLOCKS 5000 + +/* Macros that save access to desc in order to find next desc pointer */ +#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ + ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ + (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ + (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) + +#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ + ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ + (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ + (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) + +#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ + ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ + (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ + (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) + +#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ + ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ + (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ + (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) + + +/* Queue specific information */ +typedef struct +{ + void* pFirstDescr; + void* pLastDescr; + void* pCurrentDescr; + void* pUsedDescr; + int resource; + MV_BUF_INFO descBuf; +} ETH_QUEUE_CTRL; + + +/* Ethernet port specific infomation */ +typedef struct _ethPortCtrl +{ + int portNo; + ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ + ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ + + MV_ETH_PORT_CFG portConfig; + MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; + MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; + + /* Register images - For DP */ + MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ + MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ + + MV_STATE portState; + + MV_U8 mcastCount[256]; + MV_U32* hashPtr; + void *osHandle; +} ETH_PORT_CTRL; + +/************** MACROs ****************/ + +/* MACROs to Flush / Invalidate TX / RX Buffers */ +#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) +# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ + mvOsCacheClear(NULL, (pAddr), (size)); \ + /*CPU_PIPE_FLUSH;*/ +#else +# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ + mvOsIoVirtToPhy(NULL, (pAddr)); +#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ + +#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) +# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ + mvOsCacheInvalidate (NULL, (pAddr), (size)); \ + /*CPU_PIPE_FLUSH;*/ +#else +# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) +#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ + +#ifdef ETH_DESCR_UNCACHED + +#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) +#define ETH_DESCR_INV(pPortCtrl, pDescr) + +#else + +#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ + mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) + +#define ETH_DESCR_INV(pPortCtrl, pDescr) \ + mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) + +#endif /* ETH_DESCR_UNCACHED */ + +#include "eth/gbe/mvEthGbe.h" + +#endif /* __mvEth_h__ */ + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt new file mode 100644 index 0000000..38a9264 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.4 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c new file mode 100644 index 0000000..889d4d9 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c @@ -0,0 +1,362 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "gpp/mvGpp.h" +#include "ctrlEnv/mvCtrlEnvLib.h" +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); + +/******************************************************************************* +* mvGppTypeSet - Enable a GPP (OUT) pin +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP type per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to input and GPP15 to output. +* mvGppTypeSet(0, (GPP8 | GPP15), +* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); + + /* Workaround for Erratum FE-MISC-70*/ + if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) + { + mask &= 0x2; + gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); + } /*End of WA*/ + + return MV_OK; + +} + +/******************************************************************************* +* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP blink per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to be static and GPP15 to be blinking. +* mvGppBlinkEn(0, (GPP8 | GPP15), +* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); + + return MV_OK; + +} +/******************************************************************************* +* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the type +* of corresponding GPP will be set. Other GPPs are ignored. +* value - 32bit value that describes GPP polarity per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 to the actual pin value and GPP15 to be inverted. +* mvGppPolaritySet(0, (GPP8 | GPP15), +* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) +{ + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); + return MV_BAD_PARAM; + } + + gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); + + return MV_OK; + +} + +/******************************************************************************* +* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. +* +* DESCRIPTION: +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* returned value is valid for it. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Get GPP8 and GPP15 value. +* mvGppPolarityGet(0, (GPP8 | GPP15)); +* +* RETURN: +* 32bit value that describes GPP polatity mode per pin. +* +*******************************************************************************/ +MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) +{ + MV_U32 regVal; + + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); + return MV_ERROR; + } + regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); + + return (regVal & mask); +} + +/******************************************************************************* +* mvGppValueGet - Get a GPP Pin list value. +* +* DESCRIPTION: +* This function get GPP value. +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* returned value is valid for it. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Get GPP8 and GPP15 value. +* mvGppValueGet(0, (GPP8 | GPP15)); +* +* RETURN: +* 32bit value that describes GPP activity mode per pin. +* +*******************************************************************************/ +MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) +{ + MV_U32 gppData; + + gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); + + gppData &= mask; + + return gppData; + +} + +/******************************************************************************* +* mvGppValueSet - Set a GPP Pin list value. +* +* DESCRIPTION: +* This function set value for given GPP pin list. +* +* INPUT: +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* value of corresponding GPP will be set accordingly. Other GPP +* are not affected. +* value - 32bit value that describes GPP value per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 value of '0' and GPP15 value of '1'. +* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) +{ + MV_U32 outEnable, tmp; + MV_U32 i; + + if (group >= MV_GPP_MAX_GROUP) + { + DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); + return MV_BAD_PARAM; + } + + /* verify that the gpp pin is configured as output */ + /* Note that in the register out enabled -> bit = '0'. */ + outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); + + /* Workaround for Erratum FE-MISC-70*/ + if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) + { + tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); + outEnable &= 0xfffffffd; + outEnable |= (tmp & 0x2); + } /*End of WA*/ + + for (i = 0 ; i < 32 ;i++) + { + if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) + { + mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ + "value to GPP %d in input mode.\n", i); + return MV_ERROR; + } + } + + gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); + + return MV_OK; + +} +/******************************************************************************* +* gppRegSet - Set a specific GPP pin on a specific GPP register +* +* DESCRIPTION: +* This function set a specific GPP pin on a specific GPP register +* +* INPUT: +* regOffs - GPP Register offset +* group - GPP group number +* mask - 32bit mask value. Each set bit in the mask means that the +* value of corresponding GPP will be set accordingly. Other GPP +* are not affected. +* value - 32bit value that describes GPP value per pin. +* +* OUTPUT: +* None. +* +* EXAMPLE: +* Set GPP8 value of '0' and GPP15 value of '1'. +* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) +{ + MV_U32 gppData; + + gppData = MV_REG_READ(regOffs); + + gppData &= ~mask; + + gppData |= (value & mask); + + MV_REG_WRITE(regOffs, gppData); +} + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h new file mode 100644 index 0000000..526d324 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h @@ -0,0 +1,118 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvGppH +#define __INCmvGppH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "gpp/mvGppRegs.h" + +/* These macros describes the GPP type. Each of the GPPs pins can */ +/* be assigned to act as a general purpose input or output pin. */ +#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ +#define MV_GPP_OUT 0 /* GPP output */ + + +/* These macros describes the GPP Out Enable. */ +#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ +#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ + +/* These macros describes the GPP Out Blinking. */ +/* When set and the corresponding bit in GPIO Data Out Enable Control */ +/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ +/* 2^24 TCLK clocks). */ +#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ +#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ + + +/* These macros describes the GPP Polarity. */ +/* When set to 1 GPIO Data In Register reflects the inverted value of the */ +/* corresponding pin. */ + +#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ +#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ + +/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ +MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); + +/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ +MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); + +/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ +MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); + +/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ +MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); + +/* mvGppValueGet - Get a GPP Pin list value.*/ +MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); + + +/* mvGppValueSet - Set a GPP Pin list value. */ +MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); + +#endif /* #ifndef __INCmvGppH */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h new file mode 100644 index 0000000..b6fec34 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h @@ -0,0 +1,116 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvGppRegsH +#define __INCmvGppRegsH + +#define MV_GPP0 BIT0 +#define MV_GPP1 BIT1 +#define MV_GPP2 BIT2 +#define MV_GPP3 BIT3 +#define MV_GPP4 BIT4 +#define MV_GPP5 BIT5 +#define MV_GPP6 BIT6 +#define MV_GPP7 BIT7 +#define MV_GPP8 BIT8 +#define MV_GPP9 BIT9 +#define MV_GPP10 BIT10 +#define MV_GPP11 BIT11 +#define MV_GPP12 BIT12 +#define MV_GPP13 BIT13 +#define MV_GPP14 BIT14 +#define MV_GPP15 BIT15 +#define MV_GPP16 BIT16 +#define MV_GPP17 BIT17 +#define MV_GPP18 BIT18 +#define MV_GPP19 BIT19 +#define MV_GPP20 BIT20 +#define MV_GPP21 BIT21 +#define MV_GPP22 BIT22 +#define MV_GPP23 BIT23 +#define MV_GPP24 BIT24 +#define MV_GPP25 BIT25 +#define MV_GPP26 BIT26 +#define MV_GPP27 BIT27 +#define MV_GPP28 BIT28 +#define MV_GPP29 BIT29 +#define MV_GPP30 BIT30 +#define MV_GPP31 BIT31 + + +/* registers offsets */ + +#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) +#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) +#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) +#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) +#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) +#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) +#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) +#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) + +#define GPP_DATA_OUT_SET_REG 0x10120 +#define GPP_DATA_OUT_CLEAR_REG 0x10124 + +#endif /* #ifndef __INCmvGppRegsH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c new file mode 100644 index 0000000..672d3e3 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.c @@ -0,0 +1,669 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvPciIf.h" +#include "ctrlEnv/sys/mvSysPex.h" + +#if defined(MV_INCLUDE_PCI) +#include "ctrlEnv/sys/mvSysPci.h" +#endif + + +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + + +/******************************************************************************* +* mvPciInit - Initialize PCI interfaces +* +* DESCRIPTION: +* +* INPUT: +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ + + +MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + + MV_PCI_MOD pciMod; + + if (PCI_IF_MODE_HOST == pciIfmode) + { + pciMod = MV_PCI_MOD_HOST; + } + else if (PCI_IF_MODE_DEVICE == pciIfmode) + { + pciMod = MV_PCI_MOD_DEVICE; + } + else + { + mvOsPrintf("%s: ERROR!!! Bus %d mode %d neither host nor device!\n", + __FUNCTION__, pciIf, pciIfmode); + return MV_FAIL; + } + + return mvPciInit(pciIf - MV_PCI_START_IF, pciMod); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + + MV_PEX_TYPE pexType; + + if (PCI_IF_MODE_HOST == pciIfmode) + { + pexType = MV_PEX_ROOT_COMPLEX; + } + else if (PCI_IF_MODE_DEVICE == pciIfmode) + { + pexType = MV_PEX_END_POINT; + } + else + { + mvOsPrintf("%s: ERROR!!! Bus %d type %d neither root complex nor" \ + " end point\n", __FUNCTION__, pciIf, pciIfmode); + return MV_FAIL; + } + return mvPexInit(pciIf - MV_PEX_START_IF, pexType); + + #else + return MV_OK; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/* PCI configuration space read write */ + +/******************************************************************************* +* mvPciConfigRead - Read from configuration space +* +* DESCRIPTION: +* This function performs a 32 bit read from PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to read from local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit register data, 0xffffffff on error +* +*******************************************************************************/ +MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciConfigRead(pciIf - MV_PCI_START_IF, + bus, + dev, + func, + regOff); + #else + return 0xffffffff; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexConfigRead(pciIf - MV_PEX_START_IF, + bus, + dev, + func, + regOff); + #else + return 0xffffffff; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return 0; + +} + +/******************************************************************************* +* mvPciConfigWrite - Write to configuration space +* +* DESCRIPTION: +* This function performs a 32 bit write to PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to write to local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* data - 32bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciConfigWrite(pciIf - MV_PCI_START_IF, + bus, + dev, + func, + regOff, + data); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexConfigWrite(pciIf - MV_PEX_START_IF, + bus, + dev, + func, + regOff, + data); + #else + return MV_OK; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/******************************************************************************* +* mvPciMasterEnable - Enable/disale PCI interface master transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI +* master is allowed to gain ownership on the bus, otherwise it is +* incapable to do so. +* +* INPUT: +* pciIf - PCI interface number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable) +{ + + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciMasterEnable(pciIf - MV_PCI_START_IF, + enable); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexMasterEnable(pciIf - MV_PEX_START_IF, + enable); + #else + return MV_OK; + #endif + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + + +/******************************************************************************* +* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, +* the PCI slave is allowed to respond to PCI IO space access (bit 0) +* and PCI memory space access (bit 1). +* +* INPUT: +* pciIf - PCI interface number. +* dev - PCI device number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, MV_BOOL enable) +{ + + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciSlaveEnable(pciIf - MV_PCI_START_IF,bus,dev, + enable); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexSlaveEnable(pciIf - MV_PEX_START_IF,bus,dev, + enable); + #else + return MV_OK; + #endif + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/******************************************************************************* +* mvPciLocalBusNumSet - Set PCI interface local bus number. +* +* DESCRIPTION: +* This function sets given PCI interface its local bus number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* busNum - Bus number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciLocalBusNumSet(pciIf - MV_PCI_START_IF, + busNum); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexLocalBusNumSet(pciIf - MV_PEX_START_IF, + busNum); + #else + return MV_OK; + #endif + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/******************************************************************************* +* mvPciLocalBusNumGet - Get PCI interface local bus number. +* +* DESCRIPTION: +* This function gets the local bus number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local bus number.0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciLocalBusNumGet(pciIf - MV_PCI_START_IF); + #else + return 0xFFFFFFFF; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexLocalBusNumGet(pciIf - MV_PEX_START_IF); + #else + return 0xFFFFFFFF; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n",__FUNCTION__, pciIf); + } + + return 0; + +} + + +/******************************************************************************* +* mvPciLocalDevNumSet - Set PCI interface local device number. +* +* DESCRIPTION: +* This function sets given PCI interface its local device number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* devNum - Device number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciLocalDevNumSet(pciIf - MV_PCI_START_IF, + devNum); + #else + return MV_OK; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexLocalDevNumSet(pciIf - MV_PEX_START_IF, + devNum); + #else + return MV_OK; + #endif + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return MV_FAIL; + +} + +/******************************************************************************* +* mvPciLocalDevNumGet - Get PCI interface local device number. +* +* DESCRIPTION: +* This function gets the local device number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local device number. 0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf) +{ + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + #if defined(MV_INCLUDE_PCI) + return mvPciLocalDevNumGet(pciIf - MV_PCI_START_IF); + #else + return 0xFFFFFFFF; + #endif + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + #if defined(MV_INCLUDE_PEX) + return mvPexLocalDevNumGet(pciIf - MV_PEX_START_IF); + #else + return 0xFFFFFFFF; + #endif + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return 0; + +} + +/******************************************************************************* +* mvPciIfTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ + +PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf) +{ + + if ((pciIf >= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) + { + return PCI_IF_TYPE_CONVEN_PCIX; + } + else if ((pciIf >= MV_PEX_START_IF) && + (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) + { + return PCI_IF_TYPE_PEX; + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return 0xffffffff; + +} + +/******************************************************************************* +* mvPciIfTypeGet - +* +* DESCRIPTION: +* +* INPUT: +* +* OUTPUT: +* None. +* +* RETURN: +* +*******************************************************************************/ + +MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) +{ + + PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); + + if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) + { + return (pciIf - MV_PCI_START_IF); + } + else if (PCI_IF_TYPE_PEX == pciIfType) + { + return (pciIf - MV_PEX_START_IF); + + } + else + { + mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); + } + + return 0xffffffff; + +} + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h new file mode 100644 index 0000000..9c2d160 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h @@ -0,0 +1,134 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPCIIFH +#define __INCPCIIFH + +#include "mvSysHwConfig.h" +#include "pci-if/mvPciIfRegs.h" +#if defined(MV_INCLUDE_PEX) +#include "pex/mvPex.h" +#endif +#if defined(MV_INCLUDE_PCI) +#include "pci/mvPci.h" +#endif +#include "ctrlEnv/mvCtrlEnvLib.h" +#include "ctrlEnv/mvCtrlEnvAddrDec.h" + +typedef enum _mvPCIIfType +{ + PCI_IF_TYPE_CONVEN_PCIX, + PCI_IF_TYPE_PEX + +}PCI_IF_TYPE; + +typedef enum _mvPCIIfMode +{ + PCI_IF_MODE_HOST, + PCI_IF_MODE_DEVICE +}PCI_IF_MODE; + + +/* Global Functions prototypes */ + +/* mvPciIfInit - Initialize PCI interfaces*/ +MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); + +/* mvPciIfConfigRead - Read from configuration space */ +MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func,MV_U32 regOff); + +/* mvPciIfConfigWrite - Write to configuration space */ +MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + +/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ +MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); + +/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ +MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, + MV_BOOL enable); + +/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ +MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); + +/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ +MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); + +/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ +MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); + +/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ +MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); + +/* mvPciIfTypeGet - Get PCI If type*/ +PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); + +MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); + +/* mvPciIfAddrDecShow - Display address decode windows attributes */ +MV_VOID mvPciIfAddrDecShow(MV_VOID); + +#endif /* #ifndef __INCPCIIFH */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h new file mode 100644 index 0000000..08d4d2d --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h @@ -0,0 +1,245 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPCIIFREGSH +#define __INCPCIIFREGSH + + +/* defines */ +#define MAX_PCI_DEVICES 32 +#define MAX_PCI_FUNCS 8 +#define MAX_PCI_BUSSES 128 + +/***************************************/ +/* PCI Configuration registers */ +/***************************************/ + +/*********************************************/ +/* PCI Configuration, Function 0, Registers */ +/*********************************************/ + + +/* Standard registers */ +#define PCI_DEVICE_AND_VENDOR_ID 0x000 +#define PCI_STATUS_AND_COMMAND 0x004 +#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 +#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C +#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) +#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C +#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define PCI_CAPABILTY_LIST_POINTER 0x034 +#define PCI_INTERRUPT_PIN_AND_LINE 0x03C + + +/* PCI Device and Vendor ID Register (PDVIR) */ +#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ +#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) + +#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ +#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) + +/* PCI Status and Command Register (PSCR) */ +#define PSCR_IO_EN BIT0 /* IO Enable */ +#define PSCR_MEM_EN BIT1 /* Memory Enable */ +#define PSCR_MASTER_EN BIT2 /* Master Enable */ +#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ +#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ +#define PSCR_VGA BIT5 /* VGA Palette Snoops */ +#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ +#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ +#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ +#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ +#define PSCR_CAP_LIST BIT20 /* Capability List Support */ +#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ +#define PSCR_UDF_EN BIT22 /* User definable features */ +#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ +#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ + +#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ +#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) +#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) + +#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ +#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ +#define PSCR_MABORT BIT29 /* Recieved Master Abort */ +#define PSCR_SYSERR BIT30 /* Signalled system error */ +#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ + +/* PCI configuration register offset=0x08 fields + (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ + +#define PCCRIR_REVID_OFFS 0 /* Revision ID */ +#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) + +#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ +#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) + +#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ +#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) + +#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ +#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) + +#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ +#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) + +/* PCI configuration register offset=0x0C fields + (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ + +#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ +#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) + +#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ +#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) + +#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ +#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) + +#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ + +#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ +#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) +#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) +#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) + + +#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ +#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) + +#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ +#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ + + +/* PCI Bar Base Low Register (PBBLR) */ +#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ + +#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ +#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) +#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) +#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) + +#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ + + +#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to + address bits [31:4] */ +#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) + +#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to + address bits [31:2] */ +#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) + + +#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ +#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) +#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) + + +/* PCI Bar Base High Fegister (PBBHR) */ +#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ +#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) + + +/* PCI configuration register offset=0x2C fields + (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ + +#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ +#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) + +#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ +#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) + +/* PCI configuration register offset=0x30 fields + (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ + +#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ + +#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ +#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) + +/* PCI configuration register offset=0x34 fields + (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ + +#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ +#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) + +/* PCI configuration register offset=0x3C fields + (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ + +#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ +#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) + +#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ +#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) + +#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ +#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) + +#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ +#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) + +#endif /* #ifndef __INCPCIIFREGSH */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c new file mode 100644 index 0000000..f216979 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c @@ -0,0 +1,1006 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/* includes */ +#include "mvPciUtils.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* #define MV_DEBUG */ +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x + #define mvOsPrintf printf +#else + #define DB(x) +#endif + +/* +This module only support scanning of Header type 00h of pci devices +There is no suppotr for Header type 01h of pci devices ( PCI bridges ) +*/ + + +static MV_STATUS pciDetectDevice(MV_U32 pciIf, + MV_U32 bus, + MV_U32 dev, + MV_U32 func, + MV_PCI_DEVICE *pPciAgent); + +static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, + MV_U32 bus, + MV_U32 dev, + MV_U32 func, + MV_PCI_DEVICE *pPciAgent); + + + + + + +/******************************************************************************* +* mvPciScan - Scan a PCI interface bus +* +* DESCRIPTION: +* Performs a full scan on a PCI interface and returns all possible details +* on the agents found on the bus. +* +* INPUT: +* pciIf - PCI Interface +* pPciAgents - Pointer to an Array of the pci agents to be detected +* pPciAgentsNum - pPciAgents array maximum number of elements +* +* OUTPUT: +* pPciAgents - Array of the pci agents detected on the bus +* pPciAgentsNum - Number of pci agents detected on the bus +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ + +MV_STATUS mvPciScan(MV_U32 pciIf, + MV_PCI_DEVICE *pPciAgents, + MV_U32 *pPciAgentsNum) +{ + + MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; + MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); + MV_PCI_DEVICE *pPciDevice; + MV_PCI_DEVICE *pMainDevice; + + DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); + /* Parameter checking */ + if (pciIf >= mvCtrlPexMaxIfGet()) + { + DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); + return MV_BAD_PARAM; + } + if (NULL == pPciAgents) + { + DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); + return MV_BAD_PARAM; + } + if (NULL == pPciAgentsNum) + { + DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); + return MV_BAD_PARAM; + } + + + DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); + /* Master enable the MV PCI master */ + if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) + { + DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); + return MV_ERROR; + + } + + DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); + + /* go through all busses */ + for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) + { + /* go through all possible devices on the local bus */ + for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) + { + /* always start with function equal to zero */ + funcIndex=0; + + pPciDevice=&pPciAgents[detectedDevNum]; + DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); + + if (MV_ERROR == pciDetectDevice(pciIf, + busIndex, + devIndex, + funcIndex, + pPciDevice)) + { + /* no device detected , try the next address */ + continue; + } + + /* We are here ! means we have detected a device*/ + /* always we start with only one function per device */ + pMainDevice = pPciDevice; + pPciDevice->funtionsNum = 1; + + + /* move on */ + detectedDevNum++; + + + /* check if we have no more room for a new device */ + if (detectedDevNum == *pPciAgentsNum) + { + DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); + return MV_ERROR; + } + + /* check the detected device if it is a multi functional device then + scan all device functions*/ + if (pPciDevice->isMultiFunction == MV_TRUE) + { + /* start with function number 1 because we have already detected + function 0 */ + for (funcIndex=1; funcIndexfuntionsNum++; + detectedDevNum++; + + /* check if we have no more room for a new device */ + if (detectedDevNum == *pPciAgentsNum) + { + DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); + return MV_ERROR; + } + + + } + } + + } + + } + + /* return the number of devices actually detected on the bus ! */ + *pPciAgentsNum = detectedDevNum; + + return MV_OK; + +} + + +/******************************************************************************* +* pciDetectDevice - Detect a pci device parameters +* +* DESCRIPTION: +* This function detect if a pci agent exist on certain address ! +* and if exists then it fills all possible information on the +* agent +* +* INPUT: +* pciIf - PCI Interface +* bus - Bus number +* dev - Device number +* func - Function number +* +* +* +* OUTPUT: +* pPciAgent - pointer to the pci agent filled with its information +* +* RETURN: +* MV_ERROR if no device , MV_OK otherwise +* +*******************************************************************************/ + +static MV_STATUS pciDetectDevice(MV_U32 pciIf, + MV_U32 bus, + MV_U32 dev, + MV_U32 func, + MV_PCI_DEVICE *pPciAgent) +{ + MV_U32 pciData; + + /* no Parameters checking ! because it is static function and it is assumed + that all parameters were checked in the calling function */ + + + /* Try read the PCI Vendor ID and Device ID */ + + /* We will scan only ourselves and the PCI slots that exist on the + board, because we may have a case that we have one slot that has + a Cardbus connector, and because CardBus answers all IDsels we want + to scan only this slot and ourseleves. + + */ + #if defined(MV_INCLUDE_PCI) + if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && + (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && + (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && + (DB_88F5181_DDR1_MNG != mvBoardIdGet())) + { + + if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) + { + return MV_ERROR; + } + } + #endif /* defined(MV_INCLUDE_PCI) */ + + pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); + + if (PCI_ERROR_CODE == pciData) + { + /* no device exist */ + return MV_ERROR; + } + + /* we are here ! means a device is detected */ + + /* fill basic information */ + pPciAgent->busNumber=bus; + pPciAgent->deviceNum=dev; + pPciAgent->function=func; + + /* Fill the PCI Vendor ID and Device ID */ + + pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; + pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; + + /* Read Status and command */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_STATUS_AND_COMMAND); + + + /* Fill related Status and Command information*/ + + if (pciData & PSCR_TAR_FAST_BB) + { + pPciAgent->isFastB2BCapable = MV_TRUE; + } + else + { + pPciAgent->isFastB2BCapable = MV_FALSE; + } + + if (pciData & PSCR_CAP_LIST) + { + pPciAgent->isCapListSupport=MV_TRUE; + } + else + { + pPciAgent->isCapListSupport=MV_FALSE; + } + + if (pciData & PSCR_66MHZ_EN) + { + pPciAgent->is66MHZCapable=MV_TRUE; + } + else + { + pPciAgent->is66MHZCapable=MV_FALSE; + } + + /* Read Class Code and Revision */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_CLASS_CODE_AND_REVISION_ID); + + + pPciAgent->baseClassCode = + (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; + + pPciAgent->subClassCode = + (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; + + pPciAgent->progIf = + (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; + + pPciAgent->revisionID = + (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; + + /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); + + + + pPciAgent->pciCacheLine= + (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; + pPciAgent->pciLatencyTimer= + (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; + + switch (pciData & PBHTLTCLR_HEADER_MASK) + { + case PBHTLTCLR_HEADER_STANDARD: + + pPciAgent->pciHeader=MV_PCI_STANDARD; + break; + case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: + + pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; + break; + + } + + if (pciData & PBHTLTCLR_MULTI_FUNC) + { + pPciAgent->isMultiFunction=MV_TRUE; + } + else + { + pPciAgent->isMultiFunction=MV_FALSE; + } + + if (pciData & PBHTLTCLR_BISTCAP) + { + pPciAgent->isBISTCapable=MV_TRUE; + } + else + { + pPciAgent->isBISTCapable=MV_FALSE; + } + + + /* read this device pci bars */ + + pciDetectDeviceBars(pciIf, + bus,dev,func, + pPciAgent); + + + /* check if we are bridge*/ + if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& + (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) + { + + /* Read P2P_BUSSES_NUM */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_BUSSES_NUM); + + pPciAgent->p2pPrimBusNum = + (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; + + pPciAgent->p2pSecBusNum = + (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; + + pPciAgent->p2pSubBusNum = + (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; + + pPciAgent->p2pSecLatencyTimer = + (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; + + /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_IO_BASE_LIMIT_SEC_STATUS); + + pPciAgent->p2pSecStatus = + (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; + + + pPciAgent->p2pIObase = + (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; + + /* clear low address (should be zero)*/ + pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; + + pPciAgent->p2pIOLimit = + (pciData & PIBLSS_IO_LIMIT_MASK); + + /* fill low address with 0xfff */ + pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; + + + switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) + { + case PIBLSS_ADD_CAP_16BIT: + + pPciAgent->bIO32 = MV_FALSE; + + break; + case PIBLSS_ADD_CAP_32BIT: + + pPciAgent->bIO32 = MV_TRUE; + + /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_IO_BASE_LIMIT_UPPER_16); + + pPciAgent->p2pIObase |= + (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; + + + pPciAgent->p2pIOLimit |= + (pciData & PRBU_IO_UPP_LIMIT_MASK); + + break; + + } + + + /* Read P2P_MEM_BASE_LIMIT */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_MEM_BASE_LIMIT); + + pPciAgent->p2pMemBase = + (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; + + /* clear low address */ + pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; + + pPciAgent->p2pMemLimit = + (pciData & PMBL_MEM_LIMIT_MASK); + + /* add 0xfffff */ + pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; + + + /* Read P2P_PREF_MEM_BASE_LIMIT */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_PREF_MEM_BASE_LIMIT); + + + pPciAgent->p2pPrefMemBase = + (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; + + /* get high address only */ + pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; + + + + pPciAgent->p2pPrefMemLimit = + (pciData & PRMBL_PREF_MEM_LIMIT_MASK); + + /* add 0xfffff */ + pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; + + switch (pciData & PRMBL_ADD_CAP_MASK) + { + case PRMBL_ADD_CAP_32BIT: + + pPciAgent->bPrefMem64 = MV_FALSE; + + /* Read P2P_PREF_BASE_UPPER_32 */ + pPciAgent->p2pPrefBaseUpper32Bits = 0; + + /* Read P2P_PREF_LIMIT_UPPER_32 */ + pPciAgent->p2pPrefLimitUpper32Bits = 0; + + break; + case PRMBL_ADD_CAP_64BIT: + + pPciAgent->bPrefMem64 = MV_TRUE; + + /* Read P2P_PREF_BASE_UPPER_32 */ + pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_PREF_BASE_UPPER_32); + + /* Read P2P_PREF_LIMIT_UPPER_32 */ + pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, + bus,dev,func, + P2P_PREF_LIMIT_UPPER_32); + + break; + + } + + } + else /* no bridge */ + { + /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); + + + pPciAgent->subSysVenID = + (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; + pPciAgent->subSysID = + (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; + + + /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_EXPANSION_ROM_BASE_ADDR_REG); + + + if (pciData & PERBAR_EXPROMEN) + { + pPciAgent->isExpRom = MV_TRUE; + } + else + { + pPciAgent->isExpRom = MV_FALSE; + } + + pPciAgent->expRomAddr = + (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; + + } + + + if (MV_TRUE == pPciAgent->isCapListSupport) + { + /* Read PCI_CAPABILTY_LIST_POINTER */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_CAPABILTY_LIST_POINTER); + + pPciAgent->capListPointer = + (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; + + } + + /* Read PCI_INTERRUPT_PIN_AND_LINE */ + pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_INTERRUPT_PIN_AND_LINE); + + + pPciAgent->irqLine= + (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; + + pPciAgent->intPin= + (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; + + pPciAgent->minGrant= + (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; + pPciAgent->maxLatency= + (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; + + mvPciClassNameGet(pPciAgent->baseClassCode, + (MV_8 *)pPciAgent->type); + + return MV_OK; + + +} + +/******************************************************************************* +* pciDetectDeviceBars - Detect a pci device bars +* +* DESCRIPTION: +* This function detects all pci agent bars +* +* INPUT: +* pciIf - PCI Interface +* bus - Bus number +* dev - Device number +* func - Function number +* +* +* +* OUTPUT: +* pPciAgent - pointer to the pci agent filled with its information +* +* RETURN: +* detected bars number +* +*******************************************************************************/ +static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, + MV_U32 bus, + MV_U32 dev, + MV_U32 func, + MV_PCI_DEVICE *pPciAgent) +{ + MV_U32 pciData,barIndex,detectedBar=0; + MV_U32 tmpBaseHigh=0,tmpBaseLow=0; + MV_U32 pciMaxBars=0; + + pPciAgent->barsNum=0; + + /* check if we are bridge*/ + if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& + (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) + { + pciMaxBars = 2; + } + else /* no bridge */ + { + pciMaxBars = 6; + } + + /* read this device pci bars */ + for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) + { + /* Read PCI_MEMORY_BAR_BASE_ADDR */ + tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + pPciAgent->pciBar[detectedBar].barOffset = + PCI_MEMORY_BAR_BASE_ADDR(barIndex); + + /* check if the bar is 32bit or 64bit bar */ + switch (pciData & PBBLR_TYPE_MASK) + { + case PBBLR_TYPE_32BIT_ADDR: + pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; + break; + case PBBLR_TYPE_64BIT_ADDR: + pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; + break; + + } + + /* check if it is memory or IO bar */ + if (pciData & PBBLR_IOSPACE) + { + pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; + } + else + { + pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; + } + + /* if it is memory bar then check if it is prefetchable */ + if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) + { + if (pciData & PBBLR_PREFETCH_EN) + { + pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; + } + else + { + pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; + } + + pPciAgent->pciBar[detectedBar].barBaseLow = + pciData & PBBLR_MEM_BASE_MASK; + + + } + else /* IO Bar */ + { + pPciAgent->pciBar[detectedBar].barBaseLow = + pciData & PBBLR_IO_BASE_MASK; + + } + + pPciAgent->pciBar[detectedBar].barBaseHigh=0; + + if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) + { + barIndex++; + + tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = + mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + + } + + /* calculating full base address (64bit) */ + pPciAgent->pciBar[detectedBar].barBaseAddr = + (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; + + pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; + + pPciAgent->pciBar[detectedBar].barBaseAddr |= + (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; + + + + /* get the sizes of the the bar */ + + pPciAgent->pciBar[detectedBar].barSizeHigh=0; + + if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && + (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) + + { + /* write oxffffffff to the bar to get the size */ + /* start with sizelow ( original value was saved in tmpBaseLow ) */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), + 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeLow = + mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); + + + + /* restore original value */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), + tmpBaseLow); + + + /* now do the same for BaseHigh */ + + /* write oxffffffff to the bar to get the size */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex), + 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeHigh = + mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + /* restore original value */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex), + tmpBaseHigh); + + if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& + (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) + { + /* this bar is not applicable for this device, + ignore all previous settings and check the next bar*/ + + /* we though this was a 64bit bar , and it seems this + was wrong ! so decrement barIndex */ + barIndex--; + continue; + } + + /* calculate the full 64 bit size */ + + if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) + { + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + + } + else + { + + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + + } + + + + } + else /* 32bit bar */ + { + /* write oxffffffff to the bar to get the size */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex), + 0xffffffff); + + /* read size */ + pPciAgent->pciBar[detectedBar].barSizeLow = + mvPciIfConfigRead(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex)); + + if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) + { + /* this bar is not applicable for this device, + ignore all previous settings and check the next bar*/ + continue; + } + + + /* restore original value */ + mvPciIfConfigWrite(pciIf, + bus,dev,func, + PCI_MEMORY_BAR_BASE_ADDR(barIndex), + tmpBaseLow); + + /* calculate size low */ + + if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) + { + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; + } + else + { + pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; + } + + pPciAgent->pciBar[detectedBar].barSizeLow = + ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; + + pPciAgent->pciBar[detectedBar].barSizeHigh = 0; + pPciAgent->pciBar[detectedBar].barSize = + (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; + + + } + + /* we are here ! this means we have already detected a bar for + this device , now move on */ + + detectedBar++; + pPciAgent->barsNum++; + } + + return detectedBar; +} + + +/******************************************************************************* +* mvPciClassNameGet - get PCI class name +* +* DESCRIPTION: +* This function returns the PCI class name +* +* INPUT: +* baseClassCode - Base Class Code. +* +* OUTPUT: +* pType - the class name +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) +{ + + switch(baseClassCode) + { + case 0x0: + strcpy(pType,"Old generation device"); + break; + case 0x1: + strcpy(pType,"Mass storage controller"); + break; + case 0x2: + strcpy(pType,"Network controller"); + break; + case 0x3: + strcpy(pType,"Display controller"); + break; + case 0x4: + strcpy(pType,"Multimedia device"); + break; + case 0x5: + strcpy(pType,"Memory controller"); + break; + case 0x6: + strcpy(pType,"Bridge Device"); + break; + case 0x7: + strcpy(pType,"Simple Communication controllers"); + break; + case 0x8: + strcpy(pType,"Base system peripherals"); + break; + case 0x9: + strcpy(pType,"Input Devices"); + break; + case 0xa: + strcpy(pType,"Docking stations"); + break; + case 0xb: + strcpy(pType,"Processors"); + break; + case 0xc: + strcpy(pType,"Serial bus controllers"); + break; + case 0xd: + strcpy(pType,"Wireless controllers"); + break; + case 0xe: + strcpy(pType,"Intelligent I/O controllers"); + break; + case 0xf: + strcpy(pType,"Satellite communication controllers"); + break; + case 0x10: + strcpy(pType,"Encryption/Decryption controllers"); + break; + case 0x11: + strcpy(pType,"Data acquisition and signal processing controllers"); + break; + default: + strcpy(pType,"Unknown device"); + break; + } + + return MV_OK; + +} + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h new file mode 100644 index 0000000..2ee0b17 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h @@ -0,0 +1,323 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvPciUtilsh +#define __INCmvPciUtilsh + +/* +This module only support scanning of Header type 00h of pci devices +There is no suppotr for Header type 01h of pci devices ( PCI bridges ) +*/ + +/* includes */ +#include "mvSysHwConfig.h" +#include "pci-if/mvPciIf.h" +#include "pci/mvPciRegs.h" + + + +/* PCI base address low bar mask */ +#define PCI_ERROR_CODE 0xffffffff + +#define PCI_BRIDGE_CLASS 0x6 +#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 + + +#define P2P_BUSSES_NUM 0x18 +#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C +#define P2P_MEM_BASE_LIMIT 0x20 +#define P2P_PREF_MEM_BASE_LIMIT 0x24 +#define P2P_PREF_BASE_UPPER_32 0x28 +#define P2P_PREF_LIMIT_UPPER_32 0x2C +#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 +#define P2P_EXP_ROM 0x38 + +/* P2P_BUSSES_NUM (PBM) */ + +#define PBM_PRIME_BUS_NUM_OFFS 0 +#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) + +#define PBM_SEC_BUS_NUM_OFFS 8 +#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) + +#define PBM_SUB_BUS_NUM_OFFS 16 +#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) + +#define PBM_SEC_LAT_TMR_OFFS 24 +#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) + +/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ + +#define PIBLSS_IO_BASE_OFFS 0 +#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) + +#define PIBLSS_ADD_CAP_OFFS 0 +#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) +#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) +#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) + +#define PIBLSS_LOW_ADDR_OFFS 0 +#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) + +#define PIBLSS_HIGH_ADDR_OFFS 12 +#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) + +#define PIBLSS_IO_LIMIT_OFFS 8 +#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) + +#define PIBLSS_SEC_STATUS_OFFS 16 +#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) + + +/* P2P_MEM_BASE_LIMIT (PMBL)*/ + +#define PMBL_MEM_BASE_OFFS 0 +#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) + +#define PMBL_MEM_LIMIT_OFFS 16 +#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) + + +#define PMBL_LOW_ADDR_OFFS 0 +#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) + +#define PMBL_HIGH_ADDR_OFFS 20 +#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) + + +/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ + +#define PRMBL_PREF_MEM_BASE_OFFS 0 +#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) + +#define PRMBL_PREF_MEM_LIMIT_OFFS 16 +#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); + return MV_BAD_PARAM; + } + + /* Set command register */ + MV_REG_WRITE(PCI_CMD_REG(pciIf), command); + + /* Upodate device max outstanding split tarnsaction */ + if ((command & PCR_CPU_TO_PCI_ORDER_EN) && + (command & PCR_PCI_TO_CPU_ORDER_EN)) + { + /* Read PCI-X command register */ + regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); + + /* clear bits 22:20 */ + regVal &= 0xff8fffff; + + /* set reset value */ + regVal |= (0x3 << 20); + + /* Write back the value */ + mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); + } + + return MV_OK; + + +} + + +/******************************************************************************* +* mvPciModeGet - Get PCI interface mode. +* +* DESCRIPTION: +* This function returns the given PCI interface mode. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* pPciMode - Pointer to PCI mode structure. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) +{ + MV_U32 pciMode; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + if (NULL == pPciMode) + { + mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); + return MV_BAD_PARAM; + } + + /* Read pci mode register */ + pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); + + switch (pciMode & PMR_PCI_MODE_MASK) + { + case PMR_PCI_MODE_CONV: + pPciMode->pciType = MV_PCI_CONV; + + if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) + { + pPciMode->pciSpeed = 66000000; /* 66MHZ */ + } + else + { + pPciMode->pciSpeed = 33000000; /* 33MHZ */ + } + + break; + + case PMR_PCI_MODE_PCIX_66MHZ: + pPciMode->pciType = MV_PCIX; + pPciMode->pciSpeed = 66000000; /* 66MHZ */ + break; + + case PMR_PCI_MODE_PCIX_100MHZ: + pPciMode->pciType = MV_PCIX; + pPciMode->pciSpeed = 100000000; /* 100MHZ */ + break; + + case PMR_PCI_MODE_PCIX_133MHZ: + pPciMode->pciType = MV_PCIX; + pPciMode->pciSpeed = 133000000; /* 133MHZ */ + break; + + default: + { + mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); + return MV_ERROR; + } + } + + switch (pciMode & PMR_PCI_64_MASK) + { + case PMR_PCI_64_64BIT: + pPciMode->pciWidth = MV_PCI_64; + break; + + case PMR_PCI_64_32BIT: + pPciMode->pciWidth = MV_PCI_32; + break; + + default: + { + mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); + return MV_ERROR; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvPciRetrySet - Set PCI retry counters +* +* DESCRIPTION: +* This function specifies the number of times the PCI controller +* retries a transaction before it quits. +* Applies to the PCI Master when acting as a requester. +* Applies to the PCI slave when acting as a completer (PCI-X mode). +* A 0x00 value means a "retry forever". +* +* INPUT: +* pciIf - PCI interface number. +* counter - Number of times PCI controller retry. Use counter value +* up to PRR_RETRY_CNTR_MAX. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) +{ + MV_U32 pciRetry; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + + if (counter >= PRR_RETRY_CNTR_MAX) + { + mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); + return MV_BAD_PARAM; + + } + + /* Reading PCI retry register */ + pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); + + pciRetry &= ~PRR_RETRY_CNTR_MASK; + + pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); + + /* write new value */ + MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); + + return MV_OK; +} + + +/******************************************************************************* +* mvPciDiscardTimerSet - Set PCI discard timer +* +* DESCRIPTION: +* This function set PCI discard timer. +* In conventional PCI mode: +* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed +* read buffers (non-completed delayed read) before invalidate the buffer. +* Set to '0' to disable the timer. The PCI slave waits for delayed +* read completion forever. +* In PCI-X mode: +* Specifies the number of PCLK cycles the PCI master waits for split +* completion transaction, before it invalidates the pre-allocated read +* buffer. +* Set to '0' to disable the timer. The PCI master waits for split +* completion forever. +* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, +* unless using the "wait for ever" setting 0x0. +* NOTE: Must not be updated while there are pending read requests. +* +* INPUT: +* pciIf - PCI interface number. +* pClkCycles - Number of PCI clock cycles. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) +{ + MV_U32 pciDiscardTimer; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", + pciIf); + return MV_BAD_PARAM; + } + + if (pClkCycles >= PDTR_TIMER_MIN) + { + mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", + pClkCycles); + return MV_BAD_PARAM; + + } + + /* Read PCI Discard Timer */ + pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); + + pciDiscardTimer &= ~PDTR_TIMER_MASK; + + pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); + + /* Write new value */ + MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); + + return MV_OK; + +} + +/* PCI Arbiter routines */ + +/******************************************************************************* +* mvPciArbEnable - PCI arbiter enable/disable +* +* DESCRIPTION: +* This fuction enable/disables a given PCI interface arbiter. +* NOTE: Arbiter setting can not be changed while in work. It should only +* be set once. +* INPUT: +* pciIf - PCI interface number. +* enable - Enable/disable parameter. If enable = MV_TRUE then enable. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) +{ + MV_U32 regVal; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); + return MV_ERROR; + } + + /* Set PCI Arbiter Control register according to default configuration */ + regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); + + /* Make sure arbiter disabled before changing its values */ + MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); + + regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; + + regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ + + if (MV_TRUE == enable) + { + regVal |= PACR_ARB_ENABLE; + } + else + { + regVal &= ~PACR_ARB_ENABLE; + } + + /* Write to register */ + MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); + + return MV_OK; +} + + +/******************************************************************************* +* mvPciArbParkDis - Disable arbiter parking on agent +* +* DESCRIPTION: +* This function disables the PCI arbiter from parking on the given agent +* list. +* +* INPUT: +* pciIf - PCI interface number. +* pciAgentMask - When a bit in the mask is set to '1', parking on +* the associated PCI master is disabled. Mask bit +* refers to bit 0 - 6. For example disable parking on PCI +* agent 3 set pciAgentMask 0x4 (bit 3 is set). +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) +{ + MV_U32 pciArbiterCtrl; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); + return MV_ERROR; + } + + /* Reading Arbiter Control register */ + pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); + + /* Arbiter must be disabled before changing parking */ + MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); + + /* do the change */ + pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; + pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); + + /* writing new value ( if th earbiter was enabled before the change */ + /* here it will be reenabled */ + MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); + + return MV_OK; +} + + +/******************************************************************************* +* mvPciArbBrokDetectSet - Set PCI arbiter broken detection +* +* DESCRIPTION: +* This function sets the maximum number of cycles that the arbiter +* waits for a PCI master to respond to its grant assertion. If a +* PCI agent fails to respond within this time, the PCI arbiter aborts +* the transaction and performs a new arbitration cycle. +* NOTE: Value must be greater than '1' for conventional PCI and +* greater than '5' for PCI-X. +* +* INPUT: +* pciIf - PCI interface number. +* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken +* master detection is disabled. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) +{ + MV_U32 pciArbiterCtrl; + MV_U32 pciMode; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", + pciIf); + return MV_BAD_PARAM; + } + + /* Checking PCI mode and if pClkCycles is legal value */ + pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); + pciMode &= PMR_PCI_MODE_MASK; + + if (PMR_PCI_MODE_CONV == pciMode) + { + if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) + return MV_ERROR; + } + else + { + if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) + return MV_ERROR; + } + + pClkCycles <<= PACR_BROKEN_VAL_OFFS; + + /* Reading Arbiter Control register */ + pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); + pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; + pciArbiterCtrl |= pClkCycles; + + /* Arbiter must be disabled before changing broken detection */ + MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); + + /* writing new value ( if th earbiter was enabled before the change */ + /* here it will be reenabled */ + + MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); + + return MV_OK; +} + +/* PCI configuration space read write */ + +/******************************************************************************* +* mvPciConfigRead - Read from configuration space +* +* DESCRIPTION: +* This function performs a 32 bit read from PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to read from local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit register data, 0xffffffff on error +* +*******************************************************************************/ +MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ + MV_U32 pciData = 0; + + /* Parameter checking */ + if (PCI_DEFAULT_IF != pciIf) + { + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); + return 0xFFFFFFFF; + } + } + + if (dev >= MAX_PCI_DEVICES) + { + DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); + return 0xFFFFFFFF; + } + + if (func >= MAX_PCI_FUNCS) + { + DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); + return 0xFFFFFFFF; + } + + if (bus >= MAX_PCI_BUSSES) + { + DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); + return MV_ERROR; + } + + + /* Creating PCI address to be passed */ + pciData |= (bus << PCAR_BUS_NUM_OFFS); + pciData |= (dev << PCAR_DEVICE_NUM_OFFS); + pciData |= (func << PCAR_FUNC_NUM_OFFS); + pciData |= (regOff & PCAR_REG_NUM_MASK); + + pciData |= PCAR_CONFIG_EN; + + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); + + /* In order to let the PCI controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) + { + return MV_ERROR; + } + /* Read the Data returned in the PCI Data register */ + pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); + + return pciData; +} + +/******************************************************************************* +* mvPciConfigWrite - Write to configuration space +* +* DESCRIPTION: +* This function performs a 32 bit write to PCI configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to write to local bus segment, use +* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pciIf - PCI interface number. +* bus - PCI segment bus number. +* dev - PCI device number. +* func - Function number. +* regOffs - Register offset. +* data - 32bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ + MV_U32 pciData = 0; + + /* Parameter checking */ + if (PCI_DEFAULT_IF != pciIf) + { + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", + pciIf); + return 0xFFFFFFFF; + } + } + + if (dev >= MAX_PCI_DEVICES) + { + mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); + return MV_BAD_PARAM; + } + + if (func >= MAX_PCI_FUNCS) + { + mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); + return MV_ERROR; + } + + if (bus >= MAX_PCI_BUSSES) + { + mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); + return MV_ERROR; + } + + /* Creating PCI address to be passed */ + pciData |= (bus << PCAR_BUS_NUM_OFFS); + pciData |= (dev << PCAR_DEVICE_NUM_OFFS); + pciData |= (func << PCAR_FUNC_NUM_OFFS); + pciData |= (regOff & PCAR_REG_NUM_MASK); + + pciData |= PCAR_CONFIG_EN; + + /* Write the address to the PCI configuration address register */ + MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); + + /* In order to let the PCI controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) + { + return MV_ERROR; + } + + /* Write the Data passed to the PCI Data register */ + MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); + + return MV_OK; +} + +/******************************************************************************* +* mvPciMasterEnable - Enable/disale PCI interface master transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI +* master is allowed to gain ownership on the bus, otherwise it is +* incapable to do so. +* +* INPUT: +* pciIf - PCI interface number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) +{ + MV_U32 pciCommandStatus; + MV_U32 RegOffs; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); + return MV_ERROR; + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + RegOffs = PCI_STATUS_AND_COMMAND; + + pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); + + if (MV_TRUE == enable) + { + pciCommandStatus |= PSCR_MASTER_EN; + } + else + { + pciCommandStatus &= ~PSCR_MASTER_EN; + } + + mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); + + return MV_OK; +} + + +/******************************************************************************* +* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. +* +* DESCRIPTION: +* This function performs read modified write to PCI command status +* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, +* the PCI slave is allowed to respond to PCI IO space access (bit 0) +* and PCI memory space access (bit 1). +* +* INPUT: +* pciIf - PCI interface number. +* dev - PCI device number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) +{ + MV_U32 pciCommandStatus; + MV_U32 RegOffs; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); + return MV_BAD_PARAM; + } + if (dev >= MAX_PCI_DEVICES) + { + mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); + return MV_BAD_PARAM; + + } + + RegOffs = PCI_STATUS_AND_COMMAND; + + pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); + + if (MV_TRUE == enable) + { + pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); + } + else + { + pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); + } + + mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); + + return MV_OK; +} + +/******************************************************************************* +* mvPciLocalBusNumSet - Set PCI interface local bus number. +* +* DESCRIPTION: +* This function sets given PCI interface its local bus number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* busNum - Bus number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) +{ + MV_U32 pciP2PConfig; + MV_PCI_MODE pciMode; + MV_U32 localBus; + MV_U32 localDev; + + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); + return MV_BAD_PARAM; + } + if (busNum >= MAX_PCI_BUSSES) + { + mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); + return MV_ERROR; + + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + + /* PCI interface mode */ + mvPciModeGet(pciIf, &pciMode); + + /* if PCI type is PCI-X then it is not allowed to change the dev number */ + if (MV_PCIX == pciMode.pciType) + { + pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); + + pciP2PConfig &= ~PXS_BN_MASK; + + pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; + + mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); + + } + else + { + pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); + + pciP2PConfig &= ~PPCR_BUS_NUM_MASK; + + pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; + + MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); + + } + + + return MV_OK; +} + + +/******************************************************************************* +* mvPciLocalBusNumGet - Get PCI interface local bus number. +* +* DESCRIPTION: +* This function gets the local bus number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local bus number.0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) +{ + MV_U32 pciP2PConfig; + + /* Parameter checking */ + if (PCI_DEFAULT_IF != pciIf) + { + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", + pciIf); + return 0xFFFFFFFF; + } + } + + pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); + pciP2PConfig &= PPCR_BUS_NUM_MASK; + return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); +} + + +/******************************************************************************* +* mvPciLocalDevNumSet - Set PCI interface local device number. +* +* DESCRIPTION: +* This function sets given PCI interface its local device number. +* Note: In case the PCI interface is PCI-X, the information is read-only. +* +* INPUT: +* pciIf - PCI interface number. +* devNum - Device number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) +{ + MV_U32 pciP2PConfig; + MV_PCI_MODE pciMode; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); + return MV_BAD_PARAM; + } + if (devNum >= MAX_PCI_DEVICES) + { + mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", + devNum); + return MV_BAD_PARAM; + + } + + localBus = mvPciLocalBusNumGet(pciIf); + localDev = mvPciLocalDevNumGet(pciIf); + + /* PCI interface mode */ + mvPciModeGet(pciIf, &pciMode); + + /* if PCI type is PCIX then it is not allowed to change the dev number */ + if (MV_PCIX == pciMode.pciType) + { + pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); + + pciP2PConfig &= ~PXS_DN_MASK; + + pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; + + mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); + } + else + { + pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); + + pciP2PConfig &= ~PPCR_DEV_NUM_MASK; + + pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; + + MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); + } + + return MV_OK; +} + +/******************************************************************************* +* mvPciLocalDevNumGet - Get PCI interface local device number. +* +* DESCRIPTION: +* This function gets the local device number of a given PCI interface. +* +* INPUT: +* pciIf - PCI interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local device number. 0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) +{ + MV_U32 pciP2PConfig; + + /* Parameter checking */ + + if (PCI_DEFAULT_IF != pciIf) + { + if (pciIf >= mvCtrlPciMaxIfGet()) + { + mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", + pciIf); + return 0xFFFFFFFF; + } + } + + pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); + + pciP2PConfig &= PPCR_DEV_NUM_MASK; + + return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); +} + + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h new file mode 100644 index 0000000..4746336 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h @@ -0,0 +1,185 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#ifndef __INCPCIH +#define __INCPCIH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "pci/mvPciRegs.h" + + +/* NOTE not supported in this driver: + + Built In Self Test (BIST) + Vital Product Data (VPD) + Message Signaled Interrupt (MSI) + Power Management + Compact PCI Hot Swap + Header retarget + +Registers not supported: +1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) +2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) +*/ + +/* defines */ +/* The number of supported PCI interfaces depend on Marvell controller */ +/* device number. This device number ID is located on the PCI unit */ +/* configuration header. This creates a loop where calling PCI */ +/* configuration read/write routine results a call to get PCI configuration */ +/* information etc. This macro defines a default PCI interface. This PCI */ +/* interface is sure to exist. */ +#define PCI_DEFAULT_IF 0 + + +/* typedefs */ +/* The Marvell controller supports both conventional PCI and PCI-X. */ +/* This enumeration describes the PCI type. */ +typedef enum _mvPciType +{ + MV_PCI_CONV, /* Conventional PCI */ + MV_PCIX /* PCI-X */ +}MV_PCI_TYPE; + +typedef enum _mvPciMod +{ + MV_PCI_MOD_HOST, + MV_PCI_MOD_DEVICE +}MV_PCI_MOD; + + +/* The Marvell controller supports both PCI width of 32 and 64 bit. */ +/* This enumerator describes PCI width */ +typedef enum _mvPciWidth +{ + MV_PCI_32, /* PCI width 32bit */ + MV_PCI_64 /* PCI width 64bit */ +}MV_PCI_WIDTH; + +/* This structure describes the PCI unit configured type, speed and width. */ +typedef struct _mvPciMode +{ + MV_PCI_TYPE pciType; /* PCI type */ + MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ + MV_PCI_WIDTH pciWidth; /* PCI bus width */ +}MV_PCI_MODE; + +/* mvPciInit - Initialize PCI interfaces*/ +MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); + +/* mvPciCommandSet - Set PCI comman register value.*/ +MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); + +/* mvPciModeGet - Get PCI interface mode.*/ +MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); + +/* mvPciRetrySet - Set PCI retry counters*/ +MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); + +/* mvPciDiscardTimerSet - Set PCI discard timer*/ +MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); + +/* mvPciArbEnable - PCI arbiter enable/disable*/ +MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); + +/* mvPciArbParkDis - Disable arbiter parking on agent */ +MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); + +/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ +MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); + +/* mvPciConfigRead - Read from configuration space */ +MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func,MV_U32 regOff); + +/* mvPciConfigWrite - Write to configuration space */ +MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + +/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ +MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); + +/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ +MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); + +/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ +MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); + +/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ +MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); + +/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ +MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); + +/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ +MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); + + +#endif /* #ifndef __INCPCIH */ + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h new file mode 100644 index 0000000..89d0ef1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h @@ -0,0 +1,411 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPCIREGSH +#define __INCPCIREGSH + + +#include "pci-if/mvPciIfRegs.h" +/* defines */ +#define MAX_PCI_DEVICES 32 +#define MAX_PCI_FUNCS 8 +#define MAX_PCI_BUSSES 128 + +/* enumerators */ + +/* This enumerator described the possible PCI slave targets. */ +/* PCI slave targets are designated memory/IO address spaces that the */ +/* PCI slave targets can access. They are also refered as "targets" */ +/* this enumeratoe order is determined by the content of : + PCI_BASE_ADDR_ENABLE_REG */ + + +/* registers offsetes defines */ + + + +/*************************/ +/* PCI control registers */ +/*************************/ +/* maen : should add new registers */ +#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) +#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) +#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) +#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) +#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) +#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) +#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ + (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) +#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ + (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) +#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ + (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) + +#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) + +/* PCI Dll Control (PDC)*/ +#define PDC_DLL_EN BIT0 + + +/* PCI Command Register (PCR) */ +#define PCR_MASTER_BYTE_SWAP_EN BIT0 +#define PCR_MASTER_WR_COMBINE_EN BIT4 +#define PCR_MASTER_RD_COMBINE_EN BIT5 +#define PCR_MASTER_WR_TRIG_WHOLE BIT6 +#define PCR_MASTER_RD_TRIG_WHOLE BIT7 +#define PCR_MASTER_MEM_RD_LINE_EN BIT8 +#define PCR_MASTER_MEM_RD_MULT_EN BIT9 +#define PCR_MASTER_WORD_SWAP_EN BIT10 +#define PCR_SLAVE_WORD_SWAP_EN BIT11 +#define PCR_NS_ACCORDING_RCV_TRANS BIT14 +#define PCR_MASTER_PCIX_REQ64N_EN BIT15 +#define PCR_SLAVE_BYTE_SWAP_EN BIT16 +#define PCR_MASTER_DAC_EN BIT17 +#define PCR_MASTER_M64_ALLIGN BIT18 +#define PCR_ERRORS_PROPAGATION_EN BIT19 +#define PCR_SLAVE_SWAP_ENABLE BIT20 +#define PCR_MASTER_SWAP_ENABLE BIT21 +#define PCR_MASTER_INT_SWAP_EN BIT22 +#define PCR_LOOP_BACK_ENABLE BIT23 +#define PCR_SLAVE_INTREG_SWAP_OFFS 24 +#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 +#define PCR_SLAVE_INTREG_BYTE_SWAP \ + (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) +#define PCR_SLAVE_INTREG_NO_SWAP \ + (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) +#define PCR_SLAVE_INTREG_BYTE_WORD \ + (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) +#define PCR_SLAVE_INTREG_WORD_SWAP \ + (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) +#define PCR_RESET_REASSERTION_EN BIT26 +#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 +#define PCR_CPU_TO_PCI_ORDER_EN BIT29 +#define PCR_PCI_TO_CPU_ORDER_EN BIT30 + +/* PCI Mode Register (PMR) */ +#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ +#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) +#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) + +#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ +#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) +#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) +#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) + +#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ +#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) +#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) +#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) +#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) +#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) + +#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ + +#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ +#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) +#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) + + +/* PCI Retry Register (PRR) */ +#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ +#define PRR_RETRY_CNTR_MAX 0xff +#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) + + +/* PCI Discard Timer Register (PDTR) */ +#define PDTR_TIMER_OFFS 0 /* Timer */ +#define PDTR_TIMER_MAX 0xffff +#define PDTR_TIMER_MIN 0x7F +#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) + + +/* PCI Arbiter Control Register (PACR) */ +#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ + +#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ +#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) +#define PACR_BROKEN_VAL_CONV_MIN 0x2 +#define PACR_BROKEN_VAL_PCIX_MIN 0x6 + +#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ +#define PACR_PARK_DIS_MAX_AGENT 0x3f +#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); + return MV_ERROR; + } + } + + pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); + + switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) + { + case PXCR_DEV_TYPE_CTRL_CMPLX: + pexMode->pexType = MV_PEX_ROOT_COMPLEX; + break; + case PXCR_DEV_TYPE_CTRL_POINT: + pexMode->pexType = MV_PEX_END_POINT; + break; + + } + + /* Check if we have link */ + if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) + { + pexMode->pexLinkUp = MV_FALSE; + + /* If there is no link, the auto negotiation data is worthless */ + pexMode->pexWidth = MV_PEX_WITDH_INVALID; + } + else + { + pexMode->pexLinkUp = MV_TRUE; + + /* We have link. The link width is now valid */ + pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); + pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> + PXLCSR_NEG_LNK_WDTH_OFFS); + } + + return MV_OK; +} + + +/* PEX configuration space read write */ + +/******************************************************************************* +* mvPexConfigRead - Read from configuration space +* +* DESCRIPTION: +* This function performs a 32 bit read from PEX configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to read from local bus segment, use +* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pexIf - PEX interface number. +* bus - PEX segment bus number. +* dev - PEX device number. +* func - Function number. +* regOffs - Register offset. +* +* OUTPUT: +* None. +* +* RETURN: +* 32bit register data, 0xffffffff on error +* +*******************************************************************************/ +MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ +#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) + return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); +} + +MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ +#endif + MV_U32 pexData = 0; + MV_U32 localDev,localBus; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) + { + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); + return 0xFFFFFFFF; + } + } + + if (dev >= MAX_PEX_DEVICES) + { + DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); + return 0xFFFFFFFF; + } + + if (func >= MAX_PEX_FUNCS) + { + DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); + return 0xFFFFFFFF; + } + + if (bus >= MAX_PEX_BUSSES) + { + DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); + return MV_ERROR; + } + + DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", + pexIf, bus, dev, func, regOff)); + + localDev = mvPexLocalDevNumGet(pexIf); + localBus = mvPexLocalBusNumGet(pexIf); + + /* Speed up the process. In case on no link, return MV_ERROR */ + if ((dev != localDev) || (bus != localBus)) + { + pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + if ((pexData & PXSR_DL_DOWN)) + { + return MV_ERROR; + } + } + + /* in PCI Express we have only one device number */ + /* and this number is the first number we encounter + else that the localDev*/ + /* spec pex define return on config read/write on any device */ + if (bus == localBus) + { + if (localDev == 0) + { + /* if local dev is 0 then the first number we encounter + after 0 is 1 */ + if ((dev != 1)&&(dev != localDev)) + { + return MV_ERROR; + } + } + else + { + /* if local dev is not 0 then the first number we encounter + is 0 */ + + if ((dev != 0)&&(dev != localDev)) + { + return MV_ERROR; + } + } + if(func != 0 ) /* i.e bridge */ + { + return MV_ERROR; + } + } + + + /* Creating PEX address to be passed */ + pexData = (bus << PXCAR_BUS_NUM_OFFS); + pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); + pexData |= (func << PXCAR_FUNC_NUM_OFFS); + pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + /* extended register space */ + pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> + PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); + + pexData |= PXCAR_CONFIG_EN; + + /* Write the address to the PEX configuration address register */ + MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); + + DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); + + + /* In order to let the PEX controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) + { + return MV_ERROR; + } + + /* cleaning Master Abort */ + MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), + PXSAC_MABORT); +#if 0 + /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ + /* This guideline is relevant for all devices except of the following devices: + 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above + 88F6183 A0 and above, 88F6183L */ + if ( ( (dev != localDev) || (bus != localBus) ) && + ( + !(MV_5281_DEV_ID == mvCtrlModelGet())&& + !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& + !(MV_1281_DEV_ID == mvCtrlModelGet())&& + !(MV_6183_DEV_ID == mvCtrlModelGet())&& + !(MV_6183L_DEV_ID == mvCtrlModelGet())&& + !(MV_6281_DEV_ID == mvCtrlModelGet())&& + !(MV_6192_DEV_ID == mvCtrlModelGet())&& + !(MV_6190_DEV_ID == mvCtrlModelGet())&& + !(MV_6180_DEV_ID == mvCtrlModelGet())&& + !(MV_78XX0_DEV_ID == mvCtrlModelGet()) + )) + { + + /* PCI-Express configuration read work-around */ + + /* we will use one of the Punit (AHBToMbus) windows to access the xbar + and read the data from there */ + /* + Need to configure the 2 free Punit (AHB to MBus bridge) + address decoding windows: + Configure the flash Window to handle Configuration space requests + for PEX0/1: + 1. write 0x7931/0x7941 to the flash window and the size, + 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn + 2. write base to flash window + + Configuration transactions from the CPU should write/read the data + to/from address of the form: + addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) + addr[27:24] = extended register number + addr[23:16] = bus number + addr[15:11] = device number + addr[10:8] = function number + addr[7:0] = register number + */ + + #include "ctrlEnv/sys/mvAhbToMbus.h" + { + MV_U32 winNum; + MV_AHB_TO_MBUS_DEC_WIN originWin; + MV_U32 pciAddr=0; + MV_U32 remapLow=0,remapHigh=0; + + /* + We will use DEV_CS2\Flash window for this workarround + */ + + winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); + + /* save remap values if exist */ + if ((1 == winNum)||(0 == winNum)) + { + remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); + remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); + + } + + + /* save the original window values */ + mvAhbToMbusWinGet(winNum,&originWin); + + if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) + { + /* set the window as xbar window */ + if (pexIf) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); + } + + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), + originWin.addrWin.baseLow); + + /*pciAddr = originWin.addrWin.baseLow;*/ + pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( + (MV_U32)originWin.addrWin.baseLow); + + } + else + { + /* set the window as xbar window */ + if (pexIf) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); + } + else + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), + (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); + } + + MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), + PEX_CONFIG_RW_WA_BASE); + + pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); + } + + + /* remap should be as base */ + if ((1 == winNum)||(0 == winNum)) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); + + } + + /* extended register space */ + pciAddr |= (bus << 16); + pciAddr |= (dev << 11); + pciAddr |= (func << 8); + pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + + pexData = *(MV_U32*)pciAddr; + pexData = MV_32BIT_LE(pexData); /* Data always in LE */ + + /* restore the original window values */ + mvAhbToMbusWinSet(winNum,&originWin); + + /* restore original remap values*/ + if ((1 == winNum)||(0 == winNum)) + { + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); + MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); + + } + } + } + else +#endif + { + /* Read the Data returned in the PEX Data register */ + pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); + + } + + DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); + + return pexData; + +} + +/******************************************************************************* +* mvPexConfigWrite - Write to configuration space +* +* DESCRIPTION: +* This function performs a 32 bit write to PEX configuration space. +* It supports both type 0 and type 1 of Configuration Transactions +* (local and over bridge). In order to write to local bus segment, use +* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers +* will result configuration transaction of type 1 (over bridge). +* +* INPUT: +* pexIf - PEX interface number. +* bus - PEX segment bus number. +* dev - PEX device number. +* func - Function number. +* regOffs - Register offset. +* data - 32bit data. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ +#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) + return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); +} + +MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ +#endif + MV_U32 pexData = 0; + MV_U32 localDev,localBus; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) + { + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", + pexIf); + return MV_ERROR; + } + } + + if (dev >= MAX_PEX_DEVICES) + { + mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); + return MV_BAD_PARAM; + } + + if (func >= MAX_PEX_FUNCS) + { + mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); + return MV_ERROR; + } + + if (bus >= MAX_PEX_BUSSES) + { + mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); + return MV_ERROR; + } + + + + localDev = mvPexLocalDevNumGet(pexIf); + localBus = mvPexLocalBusNumGet(pexIf); + + + /* in PCI Express we have only one device number other than ourselves*/ + /* and this number is the first number we encounter + else than the localDev that can be any valid dev number*/ + /* pex spec define return on config read/write on any device */ + if (bus == localBus) + { + + if (localDev == 0) + { + /* if local dev is 0 then the first number we encounter + after 0 is 1 */ + if ((dev != 1)&&(dev != localDev)) + { + return MV_ERROR; + } + + } + else + { + /* if local dev is not 0 then the first number we encounter + is 0 */ + + if ((dev != 0)&&(dev != localDev)) + { + return MV_ERROR; + } + } + + + } + + /* if we are not accessing ourselves , then check the link */ + if ((dev != localDev) || (bus != localBus) ) + { + /* workarround */ + /* when no link return MV_ERROR */ + + pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + if ((pexData & PXSR_DL_DOWN)) + { + return MV_ERROR; + } + + } + + pexData =0; + + /* Creating PEX address to be passed */ + pexData |= (bus << PXCAR_BUS_NUM_OFFS); + pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); + pexData |= (func << PXCAR_FUNC_NUM_OFFS); + pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ + /* extended register space */ + pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> + PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); + pexData |= PXCAR_CONFIG_EN; + + DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", + pexIf,bus,func,dev,regOff,data,pexData) ); + + /* Write the address to the PEX configuration address register */ + MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); + + /* Clear CPU pipe. Important where CPU can perform OOO execution */ + CPU_PIPE_FLUSH; + + /* In order to let the PEX controller absorbed the address of the read */ + /* transaction we perform a validity check that the address was written */ + if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) + { + return MV_ERROR; + } + + /* Write the Data passed to the PEX Data register */ + MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); + + return MV_OK; + +} + +/******************************************************************************* +* mvPexMasterEnable - Enable/disale PEX interface master transactions. +* +* DESCRIPTION: +* This function performs read modified write to PEX command status +* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX +* master is allowed to gain ownership on the bus, otherwise it is +* incapable to do so. +* +* INPUT: +* pexIf - PEX interface number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) +{ + MV_U32 pexCommandStatus; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_ERROR; + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, + PEX_STATUS_AND_COMMAND)); + + + if (MV_TRUE == enable) + { + pexCommandStatus |= PXSAC_MASTER_EN; + } + else + { + pexCommandStatus &= ~PXSAC_MASTER_EN; + } + + + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), + pexCommandStatus); + + return MV_OK; +} + + +/******************************************************************************* +* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. +* +* DESCRIPTION: +* This function performs read modified write to PEX command status +* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, +* the PEX slave is allowed to respond to PEX IO space access (bit 0) +* and PEX memory space access (bit 1). +* +* INPUT: +* pexIf - PEX interface number. +* dev - PEX device number. +* enable - Enable/disable parameter. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) +{ + MV_U32 pexCommandStatus; + MV_U32 RegOffs; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + if (dev >= MAX_PEX_DEVICES) + { + mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); + return MV_BAD_PARAM; + + } + + + RegOffs = PEX_STATUS_AND_COMMAND; + + pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); + + if (MV_TRUE == enable) + { + pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); + } + else + { + pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); + } + + mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); + + return MV_OK; + +} + +/******************************************************************************* +* mvPexLocalBusNumSet - Set PEX interface local bus number. +* +* DESCRIPTION: +* This function sets given PEX interface its local bus number. +* Note: In case the PEX interface is PEX-X, the information is read-only. +* +* INPUT: +* pexIf - PEX interface number. +* busNum - Bus number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PEX interface is PEX-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) +{ + MV_U32 pexStatus; + MV_U32 localBus; + MV_U32 localDev; + + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); + return MV_BAD_PARAM; + } + if (busNum >= MAX_PEX_BUSSES) + { + mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); + return MV_ERROR; + + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; + + pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; + + MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); + + + return MV_OK; +} + + +/******************************************************************************* +* mvPexLocalBusNumGet - Get PEX interface local bus number. +* +* DESCRIPTION: +* This function gets the local bus number of a given PEX interface. +* +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local bus number.0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) +{ + MV_U32 pexStatus; + + /* Parameter checking */ + if (PEX_DEFAULT_IF != pexIf) + { + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); + return 0xFFFFFFFF; + } + } + + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= PXSR_PEX_BUS_NUM_MASK; + + return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); + +} + + +/******************************************************************************* +* mvPexLocalDevNumSet - Set PEX interface local device number. +* +* DESCRIPTION: +* This function sets given PEX interface its local device number. +* Note: In case the PEX interface is PEX-X, the information is read-only. +* +* INPUT: +* pexIf - PEX interface number. +* devNum - Device number. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_NOT_ALLOWED in case PEX interface is PEX-X. +* MV_BAD_PARAM on bad parameters , +* otherwise MV_OK +* +*******************************************************************************/ +MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) +{ + MV_U32 pexStatus; + MV_U32 localBus; + MV_U32 localDev; + + /* Parameter checking */ + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); + return MV_BAD_PARAM; + } + if (devNum >= MAX_PEX_DEVICES) + { + mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", + devNum); + return MV_BAD_PARAM; + + } + + localBus = mvPexLocalBusNumGet(pexIf); + localDev = mvPexLocalDevNumGet(pexIf); + + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; + + pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; + + MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); + + + return MV_OK; +} + +/******************************************************************************* +* mvPexLocalDevNumGet - Get PEX interface local device number. +* +* DESCRIPTION: +* This function gets the local device number of a given PEX interface. +* +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None. +* +* RETURN: +* Local device number. 0xffffffff on Error +* +*******************************************************************************/ +MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) +{ + MV_U32 pexStatus; + + /* Parameter checking */ + + if (PEX_DEFAULT_IF != pexIf) + { + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", + pexIf); + return 0xFFFFFFFF; + } + } + + pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); + + pexStatus &= PXSR_PEX_DEV_NUM_MASK; + + return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); +} + +MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) +{ + + MV_U32 regAddr; + if (pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); + return; + } + regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); + *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); +} + + +MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) +{ + + MV_U32 regAddr; + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); + return; + } + regAddr = (((regOffset & 0x3fff) << 16) | value); + MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); +} + +/******************************************************************************* +* mvPexActiveStateLinkPMEnable +* +* DESCRIPTION: +* Enable Active Link State Power Management +* +* INPUT: +* pexIf - PEX interface number. +* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK on success , MV_ERROR otherwise +* +*******************************************************************************/ +MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) +{ + MV_U32 reg; + + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); + return MV_ERROR; + } + + reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; + if(enable == MV_TRUE) + reg |= PXPMER_L1_ASPM_EN_MASK; + MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); + + /* Enable / Disable L0/1 entry */ + reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) + & ~PXLCSR_ASPM_CNT_MASK; + if(enable == MV_TRUE) + reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; + MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); + + return MV_OK; +} + + +/******************************************************************************* +* mvPexForceX1 +* +* DESCRIPTION: +* shut down lanes 1-3 if recognize that attached to an x1 end-point +* INPUT: +* pexIf - PEX interface number. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK on success , MV_ERROR otherwise +* +*******************************************************************************/ +MV_U32 mvPexForceX1(MV_U32 pexIf) +{ + MV_U32 regData = 0; + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); + return MV_BAD_PARAM; + } + + regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; + regData |= PXCR_CONF_LINK_X1; + + MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); + return MV_OK; +} + +MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) +{ + if(pexIf >= mvCtrlPexMaxIfGet()) + { + mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); + return MV_FALSE; + } + return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); +} + + +MV_VOID mvPexPowerDown(MV_U32 pexIf) +{ + if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || + (mvCtrlModelGet() == MV_76100_DEV_ID) || + (mvCtrlModelGet() == MV_78100_DEV_ID) || + (mvCtrlModelGet() == MV_78200_DEV_ID) ) + { + mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); + } + else + { + MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); + } +} + + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h new file mode 100644 index 0000000..d8f1cdd --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h @@ -0,0 +1,168 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPEXH +#define __INCPEXH + +#include "mvCommon.h" +#include "mvOs.h" +#include "pex/mvPexRegs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + + + +/* NOTE not supported in this driver:*/ + + +/* defines */ +/* The number of supported PEX interfaces depend on Marvell controller */ +/* device number. This device number ID is located on the PEX unit */ +/* configuration header. This creates a loop where calling PEX */ +/* configuration read/write routine results a call to get PEX configuration */ +/* information etc. This macro defines a default PEX interface. This PEX */ +/* interface is sure to exist. */ +#define PEX_DEFAULT_IF 0 + + +/* typedefs */ +/* The Marvell controller supports both root complex and end point devices */ +/* This enumeration describes the PEX type. */ +typedef enum _mvPexType +{ + MV_PEX_ROOT_COMPLEX, /* root complex device */ + MV_PEX_END_POINT /* end point device */ +}MV_PEX_TYPE; + +typedef enum _mvPexWidth +{ + MV_PEX_WITDH_X1 = 1, + MV_PEX_WITDH_X2, + MV_PEX_WITDH_X3, + MV_PEX_WITDH_X4, + MV_PEX_WITDH_INVALID +}MV_PEX_WIDTH; + +/* PEX Bar attributes */ +typedef struct _mvPexMode +{ + MV_PEX_TYPE pexType; + MV_PEX_WIDTH pexWidth; + MV_BOOL pexLinkUp; +}MV_PEX_MODE; + + + +/* Global Functions prototypes */ +/* mvPexInit - Initialize PEX interfaces*/ +MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); + +/* mvPexModeGet - Get Pex If mode */ +MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); + +/* mvPexConfigRead - Read from configuration space */ +MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func,MV_U32 regOff); + +/* mvPexConfigWrite - Write to configuration space */ +MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + +/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ +MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); + +/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ +MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); + +/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ +MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); + +/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ +MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); + +/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ +MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); + +/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ +MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); +/* mvPexForceX1 - Force PEX interface to X1 mode. */ +MV_U32 mvPexForceX1(MV_U32 pexIf); + +/* mvPexIsPowerUp - Is PEX interface Power up? */ +MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); + +/* mvPexPowerDown - Power Down */ +MV_VOID mvPexPowerDown(MV_U32 pexIf); + +/* mvPexPowerUp - Power Up */ +MV_VOID mvPexPowerUp(MV_U32 pexIf); + +/* mvPexPhyRegRead - Pex phy read */ +MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); + +/* mvPexPhyRegWrite - Pex phy write */ +MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); + +MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); + +#endif /* #ifndef __INCPEXH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h new file mode 100644 index 0000000..8ac1698 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h @@ -0,0 +1,751 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCPEXREGSH +#define __INCPEXREGSH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +#define MAX_PEX_DEVICES 32 +#define MAX_PEX_FUNCS 8 +#define MAX_PEX_BUSSES 256 + + + +/*********************************************************/ +/* PCI Express Configuration Cycles Generation Registers */ +/*********************************************************/ + +#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) +#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) +#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) +/* PCI Express Configuration Address Register */ +/* PEX_CFG_ADDR_REG (PXCAR)*/ + +#define PXCAR_REG_NUM_OFFS 2 +#define PXCAR_REG_NUM_MAX 0x3F +#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) +#define PXCAR_FUNC_NUM_OFFS 8 +#define PXCAR_FUNC_NUM_MAX 0x7 +#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) +#define PXCAR_DEVICE_NUM_OFFS 11 +#define PXCAR_DEVICE_NUM_MAX 0x1F +#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) +#define PXCAR_BUS_NUM_OFFS 16 +#define PXCAR_BUS_NUM_MAX 0xFF +#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) +#define PXCAR_EXT_REG_NUM_OFFS 24 +#define PXCAR_EXT_REG_NUM_MAX 0xF + +/* in pci express register address is now the legacy register address (8 bits) +with the new extended register address (more 4 bits) , below is the mask of +the upper 4 bits of the full register address */ + +#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 +#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) +#define PXCAR_CONFIG_EN BIT31 + +#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 +#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) + +/* The traditional PCI spec defined 6-bit field to describe register offset.*/ +/* The new PCI Express extend the register offset by an extra 4-bits. */ +/* The below macro assign 10-bit register offset into the apprpreate */ +/* fields in the CFG_ADDR_REG */ +#define PXCAR_REG_OFFS_SET(regOffs) \ + ( (regOff & PXCAR_REG_NUM_MASK) | \ + ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) + +/***********************************/ +/* PCI Express Interrupt registers */ +/***********************************/ +#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) +#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) + +#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ + /* of the PCI Express */ +/* PCI Express Interrupt Cause */ +/* PEX_INT_CAUSE_REG (PXICR)*/ +/* PEX_INT_MASK_REG*/ +/* +NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets +upon an error event occurrence. A write of 0 clears the bit. A write of 1 has +no affect. Bits[24:27} are set and cleared upon reception of interrupt +emulation messages. + +Mask bit per cause bit. If a bit is set to 1, the corresponding event is +enabled. Mask does not affect setting of the Interrupt Cause register bits; +it only affects the assertion of the interrupt .*/ + + +#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction + while master is disabled */ +#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to + PCI Express internal register*/ +#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ +#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ +#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ +#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ +#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ +#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ +#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ +#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ +#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ + +#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ +#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ +#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ +#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ +#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ +#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ +#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ +#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ +#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ +#define PXICR_RCV_INTA BIT24 /* IntA status.*/ +#define PXICR_RCV_INTB BIT25 /* IntB status.*/ +#define PXICR_RCV_INTC BIT26 /* IntC status.*/ +#define PXICR_RCV_INTD BIT27 /* IntD status.*/ +#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ + + +/********************************************/ +/* PCI Express Control and Status Registers */ +/********************************************/ +#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) +#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) +#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) +#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) +#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) +#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) +#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) +#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) + + +#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) +/* PCI Express Control Register */ +/* PEX_CTRL_REG (PXCR) */ + +#define PXCR_CONF_LINK_OFFS 0 +#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) +#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) +#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) +#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ +#define PXCR_DEV_TYPE_CTRL_MASK BIT1 +#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) +#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) +#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping + to Memory Space Enable */ + +#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping + to Memory Space Enable*/ + +#define PXCR_RSRV1_OFFS 5 +#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) +#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) + +#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ +#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) + + +#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ +#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) + +#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ +#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ +#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ +#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ + +/* PCI Express Status Register */ +/* PEX_STATUS_REG (PXSR) */ + +#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ + +#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ +#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) + +#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ +#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) + +#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ +#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ +#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ +#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ + + +/* PCI Express Completion Timeout Register */ +/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ + +#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ +#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) + +/* PCI Express Power Management Extended Register */ +/* PEX_PWR_MNG_EXT_REG (PXPMER) */ + +#define PXPMER_L1_ASPM_EN_OFFS 1 +#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) + +/* PCI Express Flow Control Register */ +/* PEX_FLOW_CTRL_REG (PXFCR)*/ + +#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit + Initial Value.*/ +#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) + + +#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers + Flow Control Credit Initial Value*/ +#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) + +#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control + Credit Initial Value Infinite*/ + +#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) + +#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ +#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) + +/* PCI Express Acknowledge Timers (4X) Register */ +/* PEX_ACK_TMR_4X_REG (PXAT4R) */ +#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ +#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) +#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ +#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) + +/* PCI Express Acknowledge Timers (1X) Register */ +/* PEX_ACK_TMR_1X_REG (PXAT1R) */ + +#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout + Value for 1X Link*/ +#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) + +#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout + Value for 1X*/ +#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) + + +/* PCI Express TL Control Register */ +/* PEX_TL_CTRL_REG (PXTCR) */ + +#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ +#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) + +/* PCI Express Debug MAC Control Register */ +/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ + +#define PXDMCR_LINKUP BIT4 + + + +/**********************************************/ +/* PCI Express Configuration Header Registers */ +/**********************************************/ +#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) + +#define PEX_DEVICE_AND_VENDOR_ID 0x000 +#define PEX_STATUS_AND_COMMAND 0x004 +#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 +#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C +#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) +#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) +#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) +#define PEX_BAR0_INTER_REG 0x010 +#define PEX_BAR0_INTER_REG_HIGH 0x014 +#define PEX_BAR1_REG 0x018 +#define PEX_BAR1_REG_HIGH 0x01C +#define PEX_BAR2_REG 0x020 +#define PEX_BAR2_REG_HIGH 0x024 + +#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C +#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 +#define PEX_CAPABILTY_LIST_POINTER 0x034 +#define PEX_INTERRUPT_PIN_AND_LINE 0x03C + +/* capability list */ +#define PEX_POWER_MNG_CAPABILITY 0x040 +#define PEX_POWER_MNG_STATUS_CONTROL 0x044 + +#define PEX_MSI_MESSAGE_CONTROL 0x050 +#define PEX_MSI_MESSAGE_ADDR 0x054 +#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 +#define PEX_MSI_MESSAGE_DATA 0x05C + +#define PEX_CAPABILITY_REG 0x60 +#define PEX_DEV_CAPABILITY_REG 0x64 +#define PEX_DEV_CTRL_STAT_REG 0x68 +#define PEX_LINK_CAPABILITY_REG 0x6C +#define PEX_LINK_CTRL_STAT_REG 0x70 + +#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 +#define PEX_UNCORRECT_ERR_STAT_REG 0x104 +#define PEX_UNCORRECT_ERR_MASK_REG 0x108 +#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C +#define PEX_CORRECT_ERR_STAT_REG 0x110 +#define PEX_CORRECT_ERR_MASK_REG 0x114 +#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 +#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C +#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 +#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 +#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 + + + +/* PCI Express Device and Vendor ID Register*/ +/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ + +#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ +#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) + +#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ +#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) + + +/* PCI Express Command and Status Register*/ +/*PEX_STATUS_AND_COMMAND (PXSAC)*/ + +#define PXSAC_IO_EN BIT0 /* IO Enable */ +#define PXSAC_MEM_EN BIT1 /* Memory Enable */ +#define PXSAC_MASTER_EN BIT2 /* Master Enable */ +#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ +#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ +#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ +#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ +#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ +#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ +#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ +#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ +#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ +#define PXSAC_SYSERR BIT30 /* Signalled system error */ +#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ + + +/* PCI Express Class Code and Revision ID Register*/ +/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ + +#define PXCCARI_REVID_OFFS 0 /* Revision ID */ +#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) + +#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ +#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) + +#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ +#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) + +#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ +#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) + +#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ +#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) + + +/* PCI Express BIST, Header Type and Cache Line Size Register*/ +/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ + +#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ +#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) + +#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ +#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) + +#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ + +#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ +#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) +#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) +#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) + + +#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ +#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) + +#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ +#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ +#define PXBHTLTCL_BISTCAP_OFFS 31 +#define PXBHTLTCL_BISTCAP_MASK BIT31 +#define PXBHTLTCL_BISTCAP_VAL 0 + + +/* PCI Express Subsystem Device and Vendor ID */ +/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ + +#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ +#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) + +#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ +#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) + + +/* PCI Express Capability List Pointer Register*/ +/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ + +#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ +#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) + +/* PCI Express Interrupt Pin and Line Register */ +/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ + +#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ +#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) + +#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ +#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) + + +/* PCI Express Power Management Capability Header Register*/ +/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ + +#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ +#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) + +#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ +#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) + +#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ +#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) + +#define PXPMC_DSI BIT21/* Device Specific Initialization */ + +#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ +#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) + +#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ + +#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ + +#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ +#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) + +/* PCI Express Power Management Control and Status Register*/ +/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ + +#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ +#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) +#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) + +#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ + +#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ +#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) + +#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ +#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) + +#define PXPMSC_PME_STAT BIT15/* PME Status */ + +#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ +#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) + + +/* PCI Express MSI Message Control Register*/ +/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ + +#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ +#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) + +#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ +#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) + +#define PXMMC_MSI_EN BIT18 /* MSI Enable */ + +#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ +#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) + +#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ +#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) + +#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ + + +/* PCI Express MSI Message Address Register*/ +/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ + +#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to + Address[31:2] of the MSI MWr TLP*/ +#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) + + +/* PCI Express MSI Message Address (High) Register */ +/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ + +#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to + Address[63:32] of the MSI MWr TLP*/ +#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) + + +/* PCI Express MSI Message Data Register*/ +/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ + +#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ +#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) + + +/* PCI Express Capability Register*/ +/*PEX_CAPABILITY_REG (PXCR)*/ + +#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ +#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) + +#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ +#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) + +#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ +#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) + +#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ +#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) + +#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ + +#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ +#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) + + +/* PCI Express Device Capabilities Register */ +/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ + +#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ +#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) + +#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ +#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) +#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) + +#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ +#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) + + +#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ +#define PXDCR_ATT_BUT_PRS_MASK BIT12 +#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 + +#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ +#define PXDCR_ATT_IND_PRS_MASK BIT13 +#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 + +#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ +#define PXDCR_PWR_IND_PRS_MASK BIT14 +#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 + +#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit + Value*/ +#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) + +#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit + Scale */ +#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) + +/* PCI Express Device Control Status Register */ +/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ + +#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ +#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ +#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ +#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) + Reporting Enable*/ +#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ + +#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ +#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) +#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) +#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ + +#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ +#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) +#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) + +#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ +#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ +#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ +#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ +#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ + +#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ +#define PXDCSR_TRANS_PEND_MASK BIT21 +#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) + + +/* PCI Express Link Capabilities Register*/ +/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ + +#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ +#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) + +#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ +#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) + +#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ +#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) + +#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ +#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) +#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) + +#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ +#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) + +/* PCI Express Link Control Status Register */ +/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ + +#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ +#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) +#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) + +#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ +#define PXLCSR_RCB_MASK BIT3 +#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) +#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) + +#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ +#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ +#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ +#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ + +#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ +#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) + +#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ +#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) +#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) + +#define PXLCSR_LNK_TRN BIT27 /* Link Training */ + +#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ +#define PXLCSR_SLT_CLK_CFG_MASK BIT28 +#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) +#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) + +/* PCI Express Advanced Error Report Header Register */ +/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ + +/* PCI Express Uncorrectable Error Status Register*/ +/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ + +/* PCI Express Uncorrectable Error Mask Register */ +/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ + +/* PCI Express Uncorrectable Error Severity Register */ +/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ + +/* PCI Express Correctable Error Status Register */ +/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ + +/* PCI Express Correctable Error Mask Register */ +/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ + +/* PCI Express Advanced Error Capability and Control Register*/ +/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ + +/* PCI Express Header Log First DWORD Register*/ +/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ + +/* PCI Express Header Log Second DWORD Register*/ +/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ + +/* PCI Express Header Log Third DWORD Register*/ +/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ + +/* PCI Express Header Log Fourth DWORD Register*/ +/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #ifndef __INCPEXREGSH */ + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c new file mode 100644 index 0000000..19c871a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c @@ -0,0 +1,313 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "mvPex.h" + +//#define MV_DEBUG +/* defines */ +#ifdef MV_DEBUG + #define DB(x) x +#else + #define DB(x) +#endif + +/* locals */ +typedef struct +{ + MV_U32 data; + MV_U32 mask; +}PEX_HEADER_DATA; + +/* local function forwad decleration */ +MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff); +MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); +void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); + + +PEX_HEADER_DATA configHdr[16] = +{ +{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ +{0x00100007, 0x0000ffff}, /*[status register, command register] */ +{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ +{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ +{0x00000000, 0x00000000}, /*[base address 0] */ +{0x00000000, 0x00000000}, /*[base address 1] */ +{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ +{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ +{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ +{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ +{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ +{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ +{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ +{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ +{0x00000000, 0x00000000}, /*[expansion ROM base address] */ +{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ +}; + + +#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ + (data & configHdr[offset/4].mask)) +#define HEADER_READ(offset) configHdr[offset/4].data + +/******************************************************************************* +* mvVrtBrgPexInit - Initialize PEX interfaces +* +* DESCRIPTION: +* +* This function is responsible of intialization of the Pex Interface , It +* configure the Pex Bars and Windows in the following manner: +* +* Assumptions : +* Bar0 is always internal registers bar +* Bar1 is always the DRAM bar +* Bar2 is always the Device bar +* +* 1) Sets the Internal registers bar base by obtaining the base from +* the CPU Interface +* 2) Sets the DRAM bar base and size by getting the base and size from +* the CPU Interface when the size is the sum of all enabled DRAM +* chip selects and the base is the base of CS0 . +* 3) Sets the Device bar base and size by getting these values from the +* CPU Interface when the base is the base of the lowest base of the +* Device chip selects, and the +* +* +* INPUT: +* +* pexIf - PEX interface number. +* +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM +* +*******************************************************************************/ +MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) +{ + /* reset PEX tree to recover previous U-boot/Boot configurations */ + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + + + resetPexConfig(pexIf, localBus, 1); + return MV_OK; +} + + +MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, + MV_U32 regOff) +{ + + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + MV_U32 localDev = mvPexLocalDevNumGet(pexIf); + MV_U32 val; + if(bus == localBus) + { + if(dev > 1) + { +/* on the local device allow only device #0 & #1 */ + return 0xffffffff; + } + else + if (dev == localDev) + { + /* read the memory controller registers */ + return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); + } + else + { + /* access the virtual brg header */ + return HEADER_READ(regOff); + } + } + else + if(bus == (localBus + 1)) + { + /* access the device behind the virtual bridge */ + if((dev == localDev) || (dev > 1)) + { + return 0xffffffff; + } + else + { + /* access the device behind the virtual bridge, in this case + * change the bus number to the local bus number in order to + * generate type 0 config cycle + */ + mvPexLocalBusNumSet(pexIf, bus); + mvPexLocalDevNumSet(pexIf, 1); + val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); + mvPexLocalBusNumSet(pexIf, localBus); + mvPexLocalDevNumSet(pexIf, localDev); + return val; + } + } + /* for all other devices use the HW function to get the + * requested registers + */ + mvPexLocalDevNumSet(pexIf, 1); + val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); + mvPexLocalDevNumSet(pexIf, localDev); + return val; +} + + +MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data) +{ + MV_U32 localBus = mvPexLocalBusNumGet(pexIf); + MV_U32 localDev = mvPexLocalDevNumGet(pexIf); + MV_STATUS status; + + if(bus == localBus) + { + if(dev > 1) + { + /* on the local device allow only device #0 & #1 */ + return MV_ERROR; + } + else + if (dev == localDev) + { + /* read the memory controller registers */ + return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); + } + else + { + /* access the virtual brg header */ + HEADER_WRITE(data, regOff); + return MV_OK; + } + } + else + if(bus == (localBus + 1)) + { + /* access the device behind the virtual bridge */ + if((dev == localDev) || (dev > 1)) + { + return MV_ERROR; + } + else + { + /* access the device behind the virtual bridge, in this case + * change the bus number to the local bus number in order to + * generate type 0 config cycle + */ + //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); + mvPexLocalBusNumSet(pexIf, bus); + mvPexLocalDevNumSet(pexIf, 1); + status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); + mvPexLocalBusNumSet(pexIf, localBus); + mvPexLocalDevNumSet(pexIf, localDev); + return status; + + } + } + /* for all other devices use the HW function to get the + * requested registers + */ + mvPexLocalDevNumSet(pexIf, 1); + status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); + mvPexLocalDevNumSet(pexIf, localDev); + return status; +} + + + + +void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) +{ + MV_U32 tData; + MV_U32 i; + + /* restore the PEX configuration to initialization state */ + /* in case PEX P2P call recursive and reset config */ + tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); + if(tData != 0xffffffff) + { + /* agent had been found - check whether P2P */ + tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); + if((tData & 0xffff0000) == 0x06040000) + {/* P2P */ + /* get the sec bus and the subordinate */ + MV_U32 secBus; + tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); + secBus = ((tData >> 8) & 0xff); + /* now scan on sec bus */ + for(i = 0;i < 0xff;i++) + { + resetPexConfig(pexIf, secBus, i); + } + /* now reset this device */ + DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); + mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); + DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); + } + } +} + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h new file mode 100644 index 0000000..82eb72d --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h @@ -0,0 +1,82 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCVRTBRGPEXH +#define __INCVRTBRGPEXH + + +/* Global Functions prototypes */ +/* mvPexInit - Initialize PEX interfaces*/ +MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); + +/* mvPexConfigRead - Read from configuration space */ +MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func,MV_U32 regOff); + +/* mvPexConfigWrite - Write to configuration space */ +MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, + MV_U32 func, MV_U32 regOff, MV_U32 data); + + +#endif /* #ifndef __INCPEXH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c new file mode 100644 index 0000000..6c5bc19 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c @@ -0,0 +1,1522 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#include "mvOs.h" +#include "sflash/mvSFlash.h" +#include "sflash/mvSFlashSpec.h" +#include "spi/mvSpi.h" +#include "spi/mvSpiCmnd.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/* Globals */ +static MV_SFLASH_DEVICE_PARAMS sflash[] = { + /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ + { + MV_M25P_WREN_CMND_OPCD, + MV_M25P_WRDI_CMND_OPCD, + MV_M25P_RDID_CMND_OPCD, + MV_M25P_RDSR_CMND_OPCD, + MV_M25P_WRSR_CMND_OPCD, + MV_M25P_READ_CMND_OPCD, + MV_M25P_FAST_RD_CMND_OPCD, + MV_M25P_PP_CMND_OPCD, + MV_M25P_SE_CMND_OPCD, + MV_M25P_BE_CMND_OPCD, + MV_M25P_RES_CMND_OPCD, + MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ + MV_M25P32_SECTOR_SIZE, + MV_M25P32_SECTOR_NUMBER, + MV_M25P_PAGE_SIZE, + "ST M25P32", + MV_M25PXXX_ST_MANF_ID, + MV_M25P32_DEVICE_ID, + MV_M25P32_MAX_SPI_FREQ, + MV_M25P32_MAX_FAST_SPI_FREQ, + MV_M25P32_FAST_READ_DUMMY_BYTES + }, + /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ + { + MV_M25P_WREN_CMND_OPCD, + MV_M25P_WRDI_CMND_OPCD, + MV_M25P_RDID_CMND_OPCD, + MV_M25P_RDSR_CMND_OPCD, + MV_M25P_WRSR_CMND_OPCD, + MV_M25P_READ_CMND_OPCD, + MV_M25P_FAST_RD_CMND_OPCD, + MV_M25P_PP_CMND_OPCD, + MV_M25P_SE_CMND_OPCD, + MV_M25P_BE_CMND_OPCD, + MV_M25P_RES_CMND_OPCD, + MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ + MV_M25P64_SECTOR_SIZE, + MV_M25P64_SECTOR_NUMBER, + MV_M25P_PAGE_SIZE, + "ST M25P64", + MV_M25PXXX_ST_MANF_ID, + MV_M25P64_DEVICE_ID, + MV_M25P64_MAX_SPI_FREQ, + MV_M25P64_MAX_FAST_SPI_FREQ, + MV_M25P64_FAST_READ_DUMMY_BYTES + }, + /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ + { + MV_M25P_WREN_CMND_OPCD, + MV_M25P_WRDI_CMND_OPCD, + MV_M25P_RDID_CMND_OPCD, + MV_M25P_RDSR_CMND_OPCD, + MV_M25P_WRSR_CMND_OPCD, + MV_M25P_READ_CMND_OPCD, + MV_M25P_FAST_RD_CMND_OPCD, + MV_M25P_PP_CMND_OPCD, + MV_M25P_SE_CMND_OPCD, + MV_M25P_BE_CMND_OPCD, + MV_M25P_RES_CMND_OPCD, + MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ + MV_M25P128_SECTOR_SIZE, + MV_M25P128_SECTOR_NUMBER, + MV_M25P_PAGE_SIZE, + "ST M25P128", + MV_M25PXXX_ST_MANF_ID, + MV_M25P128_DEVICE_ID, + MV_M25P128_MAX_SPI_FREQ, + MV_M25P128_MAX_FAST_SPI_FREQ, + MV_M25P128_FAST_READ_DUMMY_BYTES + }, + /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ + { + MV_MX25L_WREN_CMND_OPCD, + MV_MX25L_WRDI_CMND_OPCD, + MV_MX25L_RDID_CMND_OPCD, + MV_MX25L_RDSR_CMND_OPCD, + MV_MX25L_WRSR_CMND_OPCD, + MV_MX25L_READ_CMND_OPCD, + MV_MX25L_FAST_RD_CMND_OPCD, + MV_MX25L_PP_CMND_OPCD, + MV_MX25L_SE_CMND_OPCD, + MV_MX25L_BE_CMND_OPCD, + MV_MX25L_RES_CMND_OPCD, + MV_MX25L_DP_CMND_OPCD, + MV_MX25L6405_SECTOR_SIZE, + MV_MX25L6405_SECTOR_NUMBER, + MV_MXIC_PAGE_SIZE, + "MXIC MX25L6405", + MV_MXIC_MANF_ID, + MV_MX25L6405_DEVICE_ID, + MV_MX25L6405_MAX_SPI_FREQ, + MV_MX25L6405_MAX_FAST_SPI_FREQ, + MV_MX25L6405_FAST_READ_DUMMY_BYTES + }, + /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ + { + MV_S25FL_WREN_CMND_OPCD, + MV_S25FL_WRDI_CMND_OPCD, + MV_S25FL_RDID_CMND_OPCD, + MV_S25FL_RDSR_CMND_OPCD, + MV_S25FL_WRSR_CMND_OPCD, + MV_S25FL_READ_CMND_OPCD, + MV_S25FL_FAST_RD_CMND_OPCD, + MV_S25FL_PP_CMND_OPCD, + MV_S25FL_SE_CMND_OPCD, + MV_S25FL_BE_CMND_OPCD, + MV_S25FL_RES_CMND_OPCD, + MV_S25FL_DP_CMND_OPCD, + MV_S25FL128_SECTOR_SIZE, + MV_S25FL128_SECTOR_NUMBER, + MV_S25FL_PAGE_SIZE, + "SPANSION S25FL128", + MV_SPANSION_MANF_ID, + MV_S25FL128_DEVICE_ID, + MV_S25FL128_MAX_SPI_FREQ, + MV_M25P128_MAX_FAST_SPI_FREQ, + MV_M25P128_FAST_READ_DUMMY_BYTES + } +}; + +/* Static Functions */ +static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); +static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); +static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); +static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); +static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ + MV_U8* pPageBuff, MV_U32 buffSize); +static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ + MV_U8* manId, MV_U16* devId); + +/******************************************************************************* +* mvWriteEnable - serialize the write enable sequence +* +* DESCRIPTION: +* transmit the sequence for write enable +* +********************************************************************************/ +static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) +{ + MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; + + + cmd[0] = sflash[pFlinfo->index].opcdWREN; + + return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); +} + +/******************************************************************************* +* mvStatusRegGet - Retrieve the value of the status register +* +* DESCRIPTION: +* perform the RDSR sequence to get the 8bit status register +* +********************************************************************************/ +static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; + MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; + + + + + cmd[0] = sflash[pFlinfo->index].opcdRDSR; + + if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, + MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) + return ret; + + *pStatReg = sr[0]; + + return MV_OK; +} + +/******************************************************************************* +* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared +* +* DESCRIPTION: +* Block waiting for the WIP (write in progress) to be cleared +* +********************************************************************************/ +static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U32 i; + MV_U8 stat; + + for (i=0; iindex].opcdWRSR; + cmd[1] = sr; + + if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) + return ret; + + if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) + return ret; + + mvOsDelay(1); + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashPageWr - Write up to 256 Bytes in the same page +* +* DESCRIPTION: +* Write a buffer up to the page size in length provided that the whole address +* range is within the same page (alligned to page bounderies) +* +*******************************************************************************/ +static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pPageBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; + + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that we do not cross the page bounderies */ + if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > + sflash[pFlinfo->index].pageSize) + { + DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) + return MV_OUT_OF_RANGE; + } + + /* Issue the Write enable command prior the page program command */ + if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) + return ret; + + cmd[0] = sflash[pFlinfo->index].opcdPP; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) + return ret; + + if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from +* the device using the default RDID opcode and the default WREN opcode. +* +* DESCRIPTION: +* This is used to detect a generic device that uses the default opcodes +* for the WREN and RDID. +* +********************************************************************************/ +static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) +{ + MV_STATUS ret; + MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; + MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; + + + + /* Use the default RDID opcode to read the IDs */ + cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ + if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) + return ret; + + *manId = id[0]; + *devId = 0; + *devId |= (id[1] << 8); + *devId |= id[2]; + + return MV_OK; +} + +/* +##################################################################################### +##################################################################################### +*/ + +/******************************************************************************* +* mvSFlashInit - Initialize the serial flash device +* +* DESCRIPTION: +* Perform the neccessary initialization and configuration +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* pFlinfo->baseAddr: base address in fast mode. +* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI +* flash device does not support read Id command with +* the standard opcode, then the user should supply this +* as an input to skip the autodetection process!!!! +* +* OUTPUT: +* pFlinfo: pointer to the Flash information structure after detection +* pFlinfo->manufacturerId: Manufacturer ID +* pFlinfo->deviceId: Device ID +* pFlinfo->sectorSize: size of the sector (all sectors are the same). +* pFlinfo->sectorNumber: number of sectors. +* pFlinfo->pageSize: size of the page. +* pFlinfo->index: Index of the detected flash in the sflash tabel +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U8 manf; + MV_U16 dev; + MV_U32 indx; + MV_BOOL detectFlag = MV_FALSE; + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ + if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); + return ret; + } + + /* First try to read the Manufacturer and Device IDs */ + if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); + return ret; + } + + /* loop over the whole table and look for the appropriate SFLASH */ + for (indx=0; indxmanufacturerId = manf; + pFlinfo->deviceId = dev; + pFlinfo->index = indx; + detectFlag = MV_TRUE; + } + } + + if(!detectFlag) + { + mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); + return MV_FAIL; + } + + /* fill the info based on the model detected */ + pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; + pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; + pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; + + /* Set the SPI frequency to the MAX allowed for the device for best performance */ + if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); + return ret; + } + + /* As default lock the SR */ + if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashSectorErase - Erasse a single sector of the serial flash +* +* DESCRIPTION: +* Issue the erase sector command and address +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* secNumber: sector Number to erase (0 -> (sectorNumber-1)) +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; + + MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); +#if 0 + MV_U32 i; + MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); + MV_U32 erasedWord = 0xFFFFFFFF; + MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); + MV_BOOL eraseNeeded = MV_FALSE; +#endif + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that the sector number is valid */ + if (secNumber >= pFlinfo->sectorNumber) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* we don't want to access SPI in direct mode from in-direct API, + becasue of timing issue between CS asserts. */ +#if 0 + /* First compare to FF and check if erase is needed */ + for (i=0; iindex].opcdSE; + cmd[1] = ((secAddr >> 16) & 0xFF); + cmd[2] = ((secAddr >> 8) & 0xFF); + cmd[3] = (secAddr & 0xFF); + + /* Issue the Write enable command prior the sector erase command */ + if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) + return ret; + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) + return ret; + + if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashChipErase - Erasse the whole serial flash +* +* DESCRIPTION: +* Issue the bulk (chip) erase command +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; + + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + cmd[0] = sflash[pFlinfo->index].opcdBE; + + /* Issue the Write enable command prior the Bulk erase command */ + if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) + return ret; + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) + return ret; + + if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) + return ret; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashBlockRd - Read from the serial flash +* +* DESCRIPTION: +* Issue the read command and address then perfom the needed read +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* offset: byte offset with the flash to start reading from +* pReadBuff: pointer to the buffer to read the data in +* buffSize: size of the buffer to read. +* +* OUTPUT: +* pReadBuff: pointer to the buffer containing the read data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pReadBuff, MV_U32 buffSize) +{ + MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; + + + /* check for NULL pointer */ + if ((pFlinfo == NULL) || (pReadBuff == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + cmd[0] = sflash[pFlinfo->index].opcdREAD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); +} + +/******************************************************************************* +* mvSFlashFastBlockRd - Fast read from the serial flash +* +* DESCRIPTION: +* Issue the fast read command and address then perfom the needed read +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* offset: byte offset with the flash to start reading from +* pReadBuff: pointer to the buffer to read the data in +* buffSize: size of the buffer to read. +* +* OUTPUT: +* pReadBuff: pointer to the buffer containing the read data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pReadBuff, MV_U32 buffSize) +{ + MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; + MV_STATUS ret; + + /* check for NULL pointer */ + if ((pFlinfo == NULL) || (pReadBuff == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* Set the SPI frequency to the MAX allowed for fast-read operations */ + mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); + if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); + return ret; + } + + cmd[0] = sflash[pFlinfo->index].opcdFSTRD; + cmd[1] = ((offset >> 16) & 0xFF); + cmd[2] = ((offset >> 8) & 0xFF); + cmd[3] = (offset & 0xFF); + + + ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, + sflash[pFlinfo->index].spiFastRdDummyBytes); + + /* Reset the SPI frequency to the MAX allowed for the device for best performance */ + if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) + { + mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); + return ret; + } + + return ret; +} + + +/******************************************************************************* +* mvSFlashBlockWr - Write a buffer with any size +* +* DESCRIPTION: +* write regardless of the page boundaries and size limit per Page +* program command +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* offset: byte offset within the flash region +* pWriteBuff: pointer to the buffer holding the data to program +* buffSize: size of the buffer to write +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pWriteBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U32 data2write = buffSize; + MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); + MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); + MV_U32 writeOffset = offset; + + /* check for NULL pointer */ +#ifndef CONFIG_MARVELL + if(NULL == pWriteBuff) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that the buffer size does not exceed the flash size */ + if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) + { + DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) + return MV_OUT_OF_RANGE; + } + + /* check if the total block size is less than the first chunk remainder */ + if (data2write < preAllSz) + preAllSz = data2write; + + /* check if programing does not start at a 64byte alligned offset */ + if (preAllSz) + { + if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) + return ret; + + /* increment pointers and counters */ + writeOffset += preAllSz; + data2write -= preAllSz; + pWriteBuff += preAllSz; + } + + /* program the data that fits in complete page chunks */ + while (data2write >= sflash[pFlinfo->index].pageSize) + { + if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) + return ret; + + /* increment pointers and counters */ + writeOffset += sflash[pFlinfo->index].pageSize; + data2write -= sflash[pFlinfo->index].pageSize; + pWriteBuff += sflash[pFlinfo->index].pageSize; + } + + /* program the last partial chunk */ + if (data2write) + { + if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) + return ret; + } + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashIdGet - Get the manufacturer and device IDs. +* +* DESCRIPTION: +* Get the Manufacturer and device IDs from the serial flash through +* writing the RDID command then reading 3 bytes of data. In case that +* this command was called for the first time in order to detect the +* manufacturer and device IDs, then the default RDID opcode will be used +* unless the device index is indicated by the user (in case the SPI flash +* does not use the default RDID opcode). +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* pManId: pointer to the 8bit variable to hold the manufacturing ID +* pDevId: pointer to the 16bit variable to hold the device ID +* +* OUTPUT: +* pManId: pointer to the 8bit variable holding the manufacturing ID +* pDevId: pointer to the 16bit variable holding the device ID +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; + MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; + + + + /* check for NULL pointer */ + if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); + else + cmd[0] = sflash[pFlinfo->index].opcdRDID; + + if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) + return ret; + + *pManId = id[0]; + *pDevId = 0; + *pDevId |= (id[1] << 8); + *pDevId |= id[2]; + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashWpRegionSet - Set the Write-Protected region +* +* DESCRIPTION: +* Set the Write-Protected region +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* wpRegion: which region will be protected +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) +{ + MV_U8 wpMask; + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* Check if the chip is an ST flash; then WP supports only 3 bits */ + if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) + { + switch (wpRegion) + { + case MV_WP_NONE: + wpMask = MV_M25P_STATUS_BP_NONE; + break; + + case MV_WP_UPR_1OF128: + DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + + case MV_WP_UPR_1OF64: + wpMask = MV_M25P_STATUS_BP_1_OF_64; + break; + + case MV_WP_UPR_1OF32: + wpMask = MV_M25P_STATUS_BP_1_OF_32; + break; + + case MV_WP_UPR_1OF16: + wpMask = MV_M25P_STATUS_BP_1_OF_16; + break; + + case MV_WP_UPR_1OF8: + wpMask = MV_M25P_STATUS_BP_1_OF_8; + break; + + case MV_WP_UPR_1OF4: + wpMask = MV_M25P_STATUS_BP_1_OF_4; + break; + + case MV_WP_UPR_1OF2: + wpMask = MV_M25P_STATUS_BP_1_OF_2; + break; + + case MV_WP_ALL: + wpMask = MV_M25P_STATUS_BP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + /* check if the manufacturer is MXIC then the WP is 4bits */ + else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) + { + switch (wpRegion) + { + case MV_WP_NONE: + wpMask = MV_MX25L_STATUS_BP_NONE; + break; + + case MV_WP_UPR_1OF128: + wpMask = MV_MX25L_STATUS_BP_1_OF_128; + break; + + case MV_WP_UPR_1OF64: + wpMask = MV_MX25L_STATUS_BP_1_OF_64; + break; + + case MV_WP_UPR_1OF32: + wpMask = MV_MX25L_STATUS_BP_1_OF_32; + break; + + case MV_WP_UPR_1OF16: + wpMask = MV_MX25L_STATUS_BP_1_OF_16; + break; + + case MV_WP_UPR_1OF8: + wpMask = MV_MX25L_STATUS_BP_1_OF_8; + break; + + case MV_WP_UPR_1OF4: + wpMask = MV_MX25L_STATUS_BP_1_OF_4; + break; + + case MV_WP_UPR_1OF2: + wpMask = MV_MX25L_STATUS_BP_1_OF_2; + break; + + case MV_WP_ALL: + wpMask = MV_MX25L_STATUS_BP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + /* check if the manufacturer is SPANSION then the WP is 4bits */ + else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) + { + switch (wpRegion) + { + case MV_WP_NONE: + wpMask = MV_S25FL_STATUS_BP_NONE; + break; + + case MV_WP_UPR_1OF128: + DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + + case MV_WP_UPR_1OF64: + wpMask = MV_S25FL_STATUS_BP_1_OF_64; + break; + + case MV_WP_UPR_1OF32: + wpMask = MV_S25FL_STATUS_BP_1_OF_32; + break; + + case MV_WP_UPR_1OF16: + wpMask = MV_S25FL_STATUS_BP_1_OF_16; + break; + + case MV_WP_UPR_1OF8: + wpMask = MV_S25FL_STATUS_BP_1_OF_8; + break; + + case MV_WP_UPR_1OF4: + wpMask = MV_S25FL_STATUS_BP_1_OF_4; + break; + + case MV_WP_UPR_1OF2: + wpMask = MV_S25FL_STATUS_BP_1_OF_2; + break; + + case MV_WP_ALL: + wpMask = MV_S25FL_STATUS_BP_ALL; + break; + + + default: + DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + } + else + { + DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* Verify that the SRWD bit is always set - register is s/w locked */ + wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; + + return mvStatusRegSet(pFlinfo, wpMask); +} + +/******************************************************************************* +* mvSFlashWpRegionGet - Get the Write-Protected region configured +* +* DESCRIPTION: +* Get from the chip the Write-Protected region configured +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* pWpRegion: pointer to the variable to return the WP region in +* +* OUTPUT: +* wpRegion: pointer to the variable holding the WP region configured +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) +{ + MV_STATUS ret; + MV_U8 reg; + + /* check for NULL pointer */ + if ((pFlinfo == NULL) || (pWpRegion == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) + return ret; + + /* Check if the chip is an ST flash; then WP supports only 3 bits */ + if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) + { + switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) + { + case MV_M25P_STATUS_BP_NONE: + *pWpRegion = MV_WP_NONE; + break; + + case MV_M25P_STATUS_BP_1_OF_64: + *pWpRegion = MV_WP_UPR_1OF64; + break; + + case MV_M25P_STATUS_BP_1_OF_32: + *pWpRegion = MV_WP_UPR_1OF32; + break; + + case MV_M25P_STATUS_BP_1_OF_16: + *pWpRegion = MV_WP_UPR_1OF16; + break; + + case MV_M25P_STATUS_BP_1_OF_8: + *pWpRegion = MV_WP_UPR_1OF8; + break; + + case MV_M25P_STATUS_BP_1_OF_4: + *pWpRegion = MV_WP_UPR_1OF4; + break; + + case MV_M25P_STATUS_BP_1_OF_2: + *pWpRegion = MV_WP_UPR_1OF2; + break; + + case MV_M25P_STATUS_BP_ALL: + *pWpRegion = MV_WP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) + return MV_BAD_VALUE; + } + } + /* check if the manufacturer is MXIC then the WP is 4bits */ + else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) + { + switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) + { + case MV_MX25L_STATUS_BP_NONE: + *pWpRegion = MV_WP_NONE; + break; + + case MV_MX25L_STATUS_BP_1_OF_128: + *pWpRegion = MV_WP_UPR_1OF128; + break; + + case MV_MX25L_STATUS_BP_1_OF_64: + *pWpRegion = MV_WP_UPR_1OF64; + break; + + case MV_MX25L_STATUS_BP_1_OF_32: + *pWpRegion = MV_WP_UPR_1OF32; + break; + + case MV_MX25L_STATUS_BP_1_OF_16: + *pWpRegion = MV_WP_UPR_1OF16; + break; + + case MV_MX25L_STATUS_BP_1_OF_8: + *pWpRegion = MV_WP_UPR_1OF8; + break; + + case MV_MX25L_STATUS_BP_1_OF_4: + *pWpRegion = MV_WP_UPR_1OF4; + break; + + case MV_MX25L_STATUS_BP_1_OF_2: + *pWpRegion = MV_WP_UPR_1OF2; + break; + + case MV_MX25L_STATUS_BP_ALL: + *pWpRegion = MV_WP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) + return MV_BAD_VALUE; + } + } + /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ + else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) + { + switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) + { + case MV_S25FL_STATUS_BP_NONE: + *pWpRegion = MV_WP_NONE; + break; + + case MV_S25FL_STATUS_BP_1_OF_64: + *pWpRegion = MV_WP_UPR_1OF64; + break; + + case MV_S25FL_STATUS_BP_1_OF_32: + *pWpRegion = MV_WP_UPR_1OF32; + break; + + case MV_S25FL_STATUS_BP_1_OF_16: + *pWpRegion = MV_WP_UPR_1OF16; + break; + + case MV_S25FL_STATUS_BP_1_OF_8: + *pWpRegion = MV_WP_UPR_1OF8; + break; + + case MV_S25FL_STATUS_BP_1_OF_4: + *pWpRegion = MV_WP_UPR_1OF4; + break; + + case MV_S25FL_STATUS_BP_1_OF_2: + *pWpRegion = MV_WP_UPR_1OF2; + break; + + case MV_S25FL_STATUS_BP_ALL: + *pWpRegion = MV_WP_ALL; + break; + + default: + DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) + return MV_BAD_VALUE; + } + } + else + { + DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + return MV_OK; +} + +/******************************************************************************* +* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp +* pin should be low to take effect +* +* DESCRIPTION: +* Lock the access to the Status Register for writing. This will +* cause the flash to enter the hardware protection mode if the W/Vpp +* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but +* the register will continue to be writable if WREN sequence was used. +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism +* +* OUTPUT: +* None +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) +{ + MV_STATUS ret; + MV_U8 reg; + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) + return ret; + + if (srLock) + reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; + else + reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; + + return mvStatusRegSet(pFlinfo, reg); +} + +/******************************************************************************* +* mvSFlashSizeGet - Get the size of the SPI flash +* +* DESCRIPTION: +* based on the sector number and size of each sector calculate the total +* size of the flash memory. +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Size of the flash in bytes. +* +* +*******************************************************************************/ +MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) +{ + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return 0; + } + + return (pFlinfo->sectorSize * pFlinfo->sectorNumber); +} + +/******************************************************************************* +* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode +* +* DESCRIPTION: +* Enter a special power save mode. +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Size of the flash in bytes. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; + + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return 0; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that power save mode is supported in the specific device */ + if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) + { + DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + } + + cmd[0] = sflash[pFlinfo->index].opcdPwrSave; + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) + return ret; + + return MV_OK; + +} + +/******************************************************************************* +* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode +* +* DESCRIPTION: +* Exit the deep power save mode. +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* Size of the flash in bytes. +* +* +*******************************************************************************/ +MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) +{ + MV_STATUS ret; + MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; + + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return 0; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return MV_BAD_PARAM; + } + + /* check that power save mode is supported in the specific device */ + if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) + { + DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) + return MV_NOT_SUPPORTED; + } + + cmd[0] = sflash[pFlinfo->index].opcdRES; + + if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) + return ret; + + /* add the delay needed for the device to wake up */ + mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ + + return MV_OK; + +} + +/******************************************************************************* +* mvSFlashModelGet - Retreive the string with the device manufacturer and model +* +* DESCRIPTION: +* Retreive the string with the device manufacturer and model +* +* INPUT: +* pFlinfo: pointer to the Flash information structure +* +* OUTPUT: +* None. +* +* RETURN: +* pointer to the string indicating the device manufacturer and model +* +* +*******************************************************************************/ +const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) +{ + static const MV_8 * unknModel = (const MV_8 *)"Unknown"; + + /* check for NULL pointer */ + if (pFlinfo == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return 0; + } + + /* Protection - check if the model was detected */ + if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) + { + DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) + return unknModel; + } + + return sflash[pFlinfo->index].deviceModel; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h new file mode 100644 index 0000000..f441a5c --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h @@ -0,0 +1,166 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSFlashH +#define __INCmvSFlashH + +#include "mvTypes.h" + +/* MCAROS */ +#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) +#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) + +/* Constants */ +#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF +/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ +#define MV_SFLASH_BASIC_SPI_FREQ 10000000 +/* enumerations */ +typedef enum +{ + MV_WP_NONE, /* Unprotect the whole chip */ + MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ + MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ + MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ + MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ + MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ + MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ + MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ + MV_WP_ALL /* Write protect the whole chip */ +} MV_SFLASH_WP_REGION; + +/* Type Definitions */ +typedef struct +{ + MV_U8 opcdWREN; /* Write enable opcode */ + MV_U8 opcdWRDI; /* Write disable opcode */ + MV_U8 opcdRDID; /* Read ID opcode */ + MV_U8 opcdRDSR; /* Read Status Register opcode */ + MV_U8 opcdWRSR; /* Write Status register opcode */ + MV_U8 opcdREAD; /* Read opcode */ + MV_U8 opcdFSTRD; /* Fast Read opcode */ + MV_U8 opcdPP; /* Page program opcode */ + MV_U8 opcdSE; /* Sector erase opcode */ + MV_U8 opcdBE; /* Bulk erase opcode */ + MV_U8 opcdRES; /* Read electronic signature */ + MV_U8 opcdPwrSave; /* Go into power save mode */ + MV_U32 sectorSize; /* Size of each sector */ + MV_U32 sectorNumber; /* Number of sectors */ + MV_U32 pageSize; /* size of each page */ + const char * deviceModel; /* string with the device model */ + MV_U32 manufacturerId; /* The manufacturer ID */ + MV_U32 deviceId; /* Device ID */ + MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ + MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ + MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ +} MV_SFLASH_DEVICE_PARAMS; + +typedef struct +{ + MV_U32 baseAddr; /* Flash Base Address used in fast mode */ + MV_U8 manufacturerId; /* Manufacturer ID */ + MV_U16 deviceId; /* Device ID */ + MV_U32 sectorSize; /* Size of each sector - all the same */ + MV_U32 sectorNumber; /* Number of sectors */ + MV_U32 pageSize; /* Page size - affect allignment */ + MV_U32 index; /* index of the device in the sflash table (internal parameter) */ +} MV_SFLASH_INFO; + +/* Function Prototypes */ +/* Init */ +MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); + +/* erase */ +MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); +MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); + +/* Read */ +MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pReadBuff, MV_U32 buffSize); +MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pReadBuff, MV_U32 buffSize); + +/* write regardless of the page boundaries and size limit per Page program command */ +MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, + MV_U8* pWriteBuff, MV_U32 buffSize); +/* Get IDs */ +MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); + +/* Set and Get the Write Protection region - if the Status register is not locked */ +MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); +MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); + +/* Lock the status register for writing - W/Vpp pin should be low to take effect */ +MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); + +/* Get the regions sizes */ +MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); + +/* Cause the falsh device to go into power save mode */ +MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); +MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); + +/* Retreive the string with the device manufacturer and model */ +const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); + +#endif /* __INCmvSFlashH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h new file mode 100644 index 0000000..eeb4426 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h @@ -0,0 +1,233 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSFlashSpecH +#define __INCmvSFlashSpecH + +/* Constants */ +#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ +#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ +#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ +#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ +#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ +#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ +#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ +#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ + +/* Status Register Bit Masks */ +#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ +#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ +#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ +#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) +#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) + +#define MV_SFLASH_MAX_WAIT_LOOP 1000000 +#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 + +#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ +#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ +#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 + +/********************************/ +/* ST M25Pxxx Device Specific */ +/********************************/ + +/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ +#define MV_M25PXXX_ST_MANF_ID 0x20 +#define MV_M25P32_DEVICE_ID 0x2016 +#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 +#define MV_M25P64_DEVICE_ID 0x2017 +#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 +#define MV_M25P128_DEVICE_ID 0x2018 +#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 + + +/* Sector Sizes and population per device model*/ +#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ +#define MV_M25P32_SECTOR_NUMBER 64 +#define MV_M25P64_SECTOR_NUMBER 128 +#define MV_M25P128_SECTOR_NUMBER 64 +#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ + +#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ +#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ +#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +/* Status Register Write Protect Bit Masks - 3bits */ +#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) + +/************************************/ +/* MXIC MX25L6405 Device Specific */ +/************************************/ + +/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ +#define MV_MXIC_MANF_ID 0xC2 +#define MV_MX25L6405_DEVICE_ID 0x2017 +#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ +#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ +#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 +#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ + +/* Sector Sizes and population per device model*/ +#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ +#define MV_MX25L6405_SECTOR_NUMBER 128 +#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ + +#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ +#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ +#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ +#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +/* Status Register Write Protect Bit Masks - 4bits */ +#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) + +/************************************/ +/* SPANSION S25FL128P Device Specific */ +/************************************/ + +/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ +#define MV_SPANSION_MANF_ID 0x01 +#define MV_S25FL128_DEVICE_ID 0x2018 +#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ +#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ +#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 + +/* Sector Sizes and population per device model*/ +#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ +#define MV_S25FL128_SECTOR_NUMBER 64 +#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ + +#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ +#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ +#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ +#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ +#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ +#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ +#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ +#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ +#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ +#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ +#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ +#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ + +/* Status Register Write Protect Bit Masks - 4bits */ +#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) +#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) + +#endif /* __INCmvSFlashSpecH */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt new file mode 100644 index 0000000..85bfa61 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.3 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c new file mode 100644 index 0000000..39e0b72 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c @@ -0,0 +1,576 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "spi/mvSpi.h" +#include "spi/mvSpiSpec.h" + +#include "ctrlEnv/mvCtrlEnvLib.h" + +/* #define MV_DEBUG */ +#ifdef MV_DEBUG +#define DB(x) x +#define mvOsPrintf printf +#else +#define DB(x) +#endif + + +/******************************************************************************* +* mvSpi16bitDataTxRx - Transmt and receive data +* +* DESCRIPTION: +* Tx data and block waiting for data to be transmitted +* +********************************************************************************/ +static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) +{ + MV_U32 i; + MV_BOOL ready = MV_FALSE; + + /* First clear the bit in the interrupt cause register */ + MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); + + /* Transmit data */ + MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); + + /* wait with timeout for memory ready */ + for (i=0; i> 8) & 0xFF); + +#elif defined(MV_CPU_BE) + + /* perform the data write to the buffer in two stages with 8bit each */ + MV_U8 * bptr = (MV_U8 *)pRxData; + MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); + *bptr = ((data >> 8) & 0xFF); + ++bptr; + *bptr = (data & 0xFF); + +#else + #error "CPU endianess isn't defined!\n" +#endif + + } + else + *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); + } + + return MV_OK; +} + + +/******************************************************************************* +* mvSpi8bitDataTxRx - Transmt and receive data (8bits) +* +* DESCRIPTION: +* Tx data and block waiting for data to be transmitted +* +********************************************************************************/ +static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) +{ + MV_U32 i; + MV_BOOL ready = MV_FALSE; + + /* First clear the bit in the interrupt cause register */ + MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); + + /* Transmit data */ + MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); + + /* wait with timeout for memory ready */ + for (i=0; i serialBaudRate) + continue; + + /* check for exact fit */ + if ((cpuClk / preScale[i]) == serialBaudRate) + { + bestPrescaleIndx = i; + break; + } + + /* check if this is better than the previous one */ + if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) + { + minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); + bestPrescaleIndx = i; + } + } + + if (bestPrescaleIndx > 14) + { + mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); + return MV_OUT_OF_RANGE; + } + + /* configure the Prescale */ + tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); + tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); + MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); + + return MV_OK; +} + +/******************************************************************************* +* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer +* +* DESCRIPTION: +* Assert The chip select - used to select an external SPI device +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_VOID mvSpiCsAssert(MV_VOID) +{ + /* For devices in which the SPI is muxed on the MPP with other interfaces*/ + mvMPPConfigToSPI(); + mvOsUDelay(1); + MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); +} + +/******************************************************************************* +* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a +* SPI transfer sequence +* +* DESCRIPTION: +* DeAssert the chip select pin +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +********************************************************************************/ +MV_VOID mvSpiCsDeassert(MV_VOID) +{ + MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); + + /* For devices in which the SPI is muxed on the MPP with other interfaces*/ + mvMPPConfigToDefault(); +} + +/******************************************************************************* +* mvSpiRead - Read a buffer over the SPI interface +* +* DESCRIPTION: +* Receive (read) a buffer over the SPI interface in 16bit chunks. If the +* buffer size is odd, then the last chunk will be 8bits. Chip select is not +* handled at this level. +* +* INPUT: +* pRxBuff: Pointer to the buffer to hold the received data +* buffSize: length of the pRxBuff +* +* OUTPUT: +* pRxBuff: Pointer to the buffer with the received data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U32 bytesLeft = buffSize; + MV_U16* rxPtr = (MV_U16*)pRxBuff; + + /* check for null parameters */ + if (pRxBuff == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Check that the buffer pointer and the buffer size are 16bit aligned */ + if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) + { + /* Verify that the SPI mode is in 16bit mode */ + MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX as long we have complete 16bit chunks */ + while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) + return ret; + + /* increment the pointers */ + rxPtr++; + bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; + } + + } + else + { + /* Verify that the SPI mode is in 8bit mode */ + MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX in 8bit chanks */ + while (bytesLeft > 0) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) + return ret; + /* increment the pointers */ + pRxBuff++; + bytesLeft--; + } + } + + return MV_OK; +} + +/******************************************************************************* +* mvSpiWrite - Transmit a buffer over the SPI interface +* +* DESCRIPTION: +* Transmit a buffer over the SPI interface in 16bit chunks. If the +* buffer size is odd, then the last chunk will be 8bits. No chip select +* action is taken. +* +* INPUT: +* pTxBuff: Pointer to the buffer holding the TX data +* buffSize: length of the pTxBuff +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U32 bytesLeft = buffSize; + MV_U16* txPtr = (MV_U16*)pTxBuff; + + /* check for null parameters */ + if (pTxBuff == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Check that the buffer pointer and the buffer size are 16bit aligned */ + if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) + { + /* Verify that the SPI mode is in 16bit mode */ + MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX as long we have complete 16bit chunks */ + while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) + return ret; + + /* increment the pointers */ + txPtr++; + bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; + } + } + else + { + + /* Verify that the SPI mode is in 8bit mode */ + MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX in 8bit chanks */ + while (bytesLeft > 0) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) + return ret; + + /* increment the pointers */ + pTxBuff++; + bytesLeft--; + } + } + + return MV_OK; +} + + +/******************************************************************************* +* mvSpiReadWrite - Read and Write a buffer simultanuosely +* +* DESCRIPTION: +* Transmit and receive a buffer over the SPI in 16bit chunks. If the +* buffer size is odd, then the last chunk will be 8bits. The SPI chip +* select is not handled implicitely. +* +* INPUT: +* pRxBuff: Pointer to the buffer to write the RX info in +* pTxBuff: Pointer to the buffer holding the TX info +* buffSize: length of both the pTxBuff and pRxBuff +* +* OUTPUT: +* pRxBuff: Pointer of the buffer holding the RX data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + MV_U32 bytesLeft = buffSize; + MV_U16* txPtr = (MV_U16*)pTxBuff; + MV_U16* rxPtr = (MV_U16*)pRxBuff; + + /* check for null parameters */ + if ((pRxBuff == NULL) || (pTxBuff == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* Check that the buffer pointer and the buffer size are 16bit aligned */ + if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) + { + /* Verify that the SPI mode is in 16bit mode */ + MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX as long we have complete 16bit chunks */ + while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) + { + /* Transmitted and wait for the transfer to be completed */ + if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) + return ret; + + /* increment the pointers */ + txPtr++; + rxPtr++; + bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; + } + } + else + { + /* Verify that the SPI mode is in 8bit mode */ + MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); + + /* TX/RX in 8bit chanks */ + while (bytesLeft > 0) + { + /* Transmitted and wait for the transfer to be completed */ + if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) + return ret; + pRxBuff++; + pTxBuff++; + bytesLeft--; + } + } + + return MV_OK; +} + + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h new file mode 100644 index 0000000..74859f0 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h @@ -0,0 +1,94 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSpihH +#define __INCmvSpihH + +#include "mvCommon.h" +#include "mvOs.h" +#include "ctrlEnv/mvCtrlEnvSpec.h" + +/* Function Prototypes */ +/* Init */ +MV_STATUS mvSpiInit (MV_U32 serialBaudRate); + +/* Set the Frequency of the Spi clock */ +MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); + +/* Assert the SPI chip select */ +MV_VOID mvSpiCsAssert (MV_VOID); + +/* De-assert the SPI chip select */ +MV_VOID mvSpiCsDeassert (MV_VOID); + +/* Simultanuous Read and write */ +MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); + +/* serialize a buffer on the TX line - Rx is ignored */ +MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); + +/* read from the RX line by writing dummy values to the TX line */ +MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); + +#endif /* __INCmvSpihH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c new file mode 100644 index 0000000..a5d5a64 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c @@ -0,0 +1,249 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#include "spi/mvSpi.h" +#include "spi/mvSpiSpec.h" + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + + +/******************************************************************************* +* mvSpiReadAndWrite - Read and Write a buffer simultanuousely +* +* DESCRIPTION: +* Transmit and receive a buffer over the SPI in 16bit chunks. If the +* buffer size is odd, then the last chunk will be 8bits. +* +* INPUT: +* pRxBuff: Pointer to the buffer to write the RX info in +* pTxBuff: Pointer to the buffer holding the TX info +* buffSize: length of both the pTxBuff and pRxBuff +* +* OUTPUT: +* pRxBuff: Pointer of the buffer holding the RX data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) +{ + MV_STATUS ret; + + /* check for null parameters */ + if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* First assert the chip select */ + mvSpiCsAssert(); + + ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); + + /* Finally deassert the chip select */ + mvSpiCsDeassert(); + + return ret; +} + +/******************************************************************************* +* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line +* +* DESCRIPTION: +* Assert the chip select line. Transmit the command buffer followed by +* the data buffer. Then deassert the CS line. +* +* INPUT: +* pCmndBuff: Pointer to the command buffer to transmit +* cmndSize: length of the command size +* pTxDataBuff: Pointer to the data buffer to transmit +* txDataSize: length of the data buffer +* +* OUTPUT: +* None. +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, + MV_U32 txDataSize) +{ + MV_STATUS ret = MV_OK, tempRet; + + /* check for null parameters */ +#ifndef CONFIG_MARVELL + if(NULL == pTxDataBuff) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } +#endif + + if (pCmndBuff == NULL) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* First assert the chip select */ + mvSpiCsAssert(); + + /* first write the command */ + if ((cmndSize) && (pCmndBuff != NULL)) + { + if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) + ret = tempRet; + } + + /* Then write the data buffer */ +#ifndef CONFIG_MARVELL + if (txDataSize) +#else + if ((txDataSize) && (pTxDataBuff != NULL)) +#endif + { + if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) + ret = tempRet; + } + + /* Finally deassert the chip select */ + mvSpiCsDeassert(); + + return ret; +} + +/******************************************************************************* +* mvSpiWriteThenRead - Serialize a command then read a data buffer +* +* DESCRIPTION: +* Assert the chip select line. Transmit the command buffer then read +* the data buffer. Then deassert the CS line. +* +* INPUT: +* pCmndBuff: Pointer to the command buffer to transmit +* cmndSize: length of the command size +* pRxDataBuff: Pointer to the buffer to read the data in +* txDataSize: length of the data buffer +* +* OUTPUT: +* pRxDataBuff: Pointer to the buffer holding the data +* +* RETURN: +* Success or Error code. +* +* +*******************************************************************************/ +MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, + MV_U32 rxDataSize,MV_U32 dummyBytesToRead) +{ + MV_STATUS ret = MV_OK, tempRet; + MV_U8 dummyByte; + + /* check for null parameters */ + if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) + { + mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); + return MV_BAD_PARAM; + } + + /* First assert the chip select */ + mvSpiCsAssert(); + + /* first write the command */ + if ((cmndSize) && (pCmndBuff != NULL)) + { + if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) + ret = tempRet; + } + + /* Read dummy bytes before real data. */ + while(dummyBytesToRead) + { + mvSpiRead(&dummyByte,1); + dummyBytesToRead--; + } + + /* Then write the data buffer */ + if ((rxDataSize) && (pRxDataBuff != NULL)) + { + if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) + ret = tempRet; + } + + /* Finally deassert the chip select */ + mvSpiCsDeassert(); + + return ret; +} + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h new file mode 100644 index 0000000..329e26b --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h @@ -0,0 +1,82 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSpiCmndhH +#define __INCmvSpiCmndhH + +#include "mvTypes.h" + +/* Function Prototypes */ + +/* Simultanuous Read and write */ +MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); + +/* write command - write a command and then write data */ +MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); + +/* read command - write a command and then read data by writing dummy data */ +MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, + MV_U32 rxDataSize,MV_U32 dummyBytesToRead); + +#endif /* __INCmvSpiCmndhH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h new file mode 100644 index 0000000..658159a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h @@ -0,0 +1,98 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +#ifndef __INCmvSpiSpecH +#define __INCmvSpiSpecH + +/* Constants */ +#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 +#define MV_SPI_16_BIT_CHUNK_SIZE 2 +#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF +#define MV_SPI_DUMMY_WRITE_8BITS 0xFF + +/* Marvell Flash Device Controller Registers */ +#define MV_SPI_CTRLR_OFST 0x10600 +#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) +#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) +#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) +#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) +#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) +#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) + +/* Serial Memory Interface Control Register Masks */ +#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ +#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ +#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) +#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) + +/* Serial Memory Interface Configuration Register Masks */ +#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ +#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ +#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ +#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) +#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) +#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) + +#endif /* __INCmvSpiSpecH */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt new file mode 100644 index 0000000..4053116 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt @@ -0,0 +1,4 @@ +Global HAL Version: FEROCEON_HAL_3_1_7 +Unit HAL Version: 3.1.5 +Description: This component includes an implementation of the unit HAL drivers + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c new file mode 100644 index 0000000..0bf8b75 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c @@ -0,0 +1,1023 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +#include "mvTwsi.h" +#include "mvTwsiSpec.h" +#include "cpu/mvCpu.h" + + +/*#define MV_DEBUG*/ +#ifdef MV_DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +static MV_VOID twsiIntFlgClr(MV_U8 chanNum); +static MV_BOOL twsiMainIntGet(MV_U8 chanNum); +static MV_VOID twsiAckBitSet(MV_U8 chanNum); +static MV_U32 twsiStsGet(MV_U8 chanNum); +static MV_VOID twsiReset(MV_U8 chanNum); +static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); +static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); +static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); +static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); +static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); + + +static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) +{ + if(timeout >= TWSI_TIMEOUT_VALUE) + { + DB(mvOsPrintf("%s",pString)); + return MV_TRUE; + } + return MV_FALSE; + +} +/******************************************************************************* +* mvTwsiStartBitSet - Set start bit on the bus +* +* DESCRIPTION: +* This routine sets the start bit on the TWSI bus. +* The routine first checks for interrupt flag condition, then it sets +* the start bit in the TWSI Control register. +* If the interrupt flag condition check previously was set, the function +* will clear it. +* The function then wait for the start bit to be cleared by the HW. +* Then it waits for the interrupt flag to be set and eventually, the +* TWSI status is checked to be 0x8 or 0x10(repeated start bit). +* +* INPUT: +* chanNum - TWSI channel. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK is start bit was set successfuly on the bus. +* MV_FAIL if interrupt flag was set before setting start bit. +* +*******************************************************************************/ +MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) +{ + MV_BOOL isIntFlag = MV_FALSE; + MV_U32 timeout, temp; + + DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); + /* check Int flag */ + if(twsiMainIntGet(chanNum)) + isIntFlag = MV_TRUE; + /* set start Bit */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); + + /* in case that the int flag was set before i.e. repeated start bit */ + if(isIntFlag){ + DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); + twsiIntFlgClr(chanNum); + } + + /* wait for interrupt */ + timeout = 0; + while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) + return MV_TIMEOUT; + + + /* check that start bit went down */ + if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) + { + mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); + return MV_FAIL; + } + + /* check the status */ + temp = twsiStsGet(chanNum); + if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) + { + mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); + return MV_FAIL; + } + + return MV_OK; + +} + +/******************************************************************************* +* mvTwsiStopBitSet - Set stop bit on the bus +* +* DESCRIPTION: +* This routine set the stop bit on the TWSI bus. +* The function then wait for the stop bit to be cleared by the HW. +* Finally the function checks for status of 0xF8. +* +* INPUT: +* chanNum - TWSI channel +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE is stop bit was set successfuly on the bus. +* +*******************************************************************************/ +MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) +{ + MV_U32 timeout, temp; + + /* Generate stop bit */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); + + twsiIntFlgClr(chanNum); + + /* wait for stop bit to come down */ + timeout = 0; + while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) + return MV_TIMEOUT; + + /* check that the stop bit went down */ + if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) + { + mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); + return MV_FAIL; + } + + /* check the status */ + temp = twsiStsGet(chanNum); + if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ + mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* twsiMainIntGet - Get twsi bit from main Interrupt cause. +* +* DESCRIPTION: +* This routine returns the twsi interrupt flag value. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. +* +*******************************************************************************/ +static MV_BOOL twsiMainIntGet(MV_U8 chanNum) +{ + MV_U32 temp; + + /* get the int flag bit */ + + temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); + if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) + return MV_TRUE; + + return MV_FALSE; +} +/******************************************************************************* +* twsiIntFlgClr - Clear Interrupt flag. +* +* DESCRIPTION: +* This routine clears the interrupt flag. It does NOT poll the interrupt +* to make sure the clear. After clearing the interrupt, it waits for at +* least 1 miliseconds. +* +* INPUT: +* chanNum - TWSI channel +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID twsiIntFlgClr(MV_U8 chanNum) +{ + MV_U32 temp; + + /* wait for 1 mili to prevent TWSI register write after write problems */ + mvOsDelay(1); + /* clear the int flag bit */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); + + /* wait for 1 mili sec for the clear to take effect */ + mvOsDelay(1); + + return; +} + + +/******************************************************************************* +* twsiAckBitSet - Set acknowledge bit on the bus +* +* DESCRIPTION: +* This routine set the acknowledge bit on the TWSI bus. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +static MV_VOID twsiAckBitSet(MV_U8 chanNum) +{ + MV_U32 temp; + + /*Set the Ack bit */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); + + /* Add delay of 1ms */ + mvOsDelay(1); + return; +} + + +/******************************************************************************* +* twsiInit - Initialize TWSI interface +* +* DESCRIPTION: +* This routine: +* -Reset the TWSI. +* -Initialize the TWSI clock baud rate according to given frequancy +* parameter based on Tclk frequancy and enables TWSI slave. +* -Set the ack bit. +* -Assign the TWSI slave address according to the TWSI address Type. +* +* +* INPUT: +* chanNum - TWSI channel +* frequancy - TWSI frequancy in KHz. (up to 100KHZ) +* +* OUTPUT: +* None. +* +* RETURN: +* Actual frequancy. +* +*******************************************************************************/ +MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) +{ + MV_U32 n,m,freq,margin,minMargin = 0xffffffff; + MV_U32 power; + MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; + + if(frequancy > 100000) + { + mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); + } + + DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); + /* Calucalte N and M for the TWSI clock baud rate */ + for(n = 0 ; n < 8 ; n++) + { + for(m = 0 ; m < 16 ; m++) + { + power = 2 << n; /* power = 2^(n+1) */ + freq = Tclk/(10*(m+1)*power); + margin = MV_ABS(frequancy - freq); + if(margin < minMargin) + { + minMargin = margin; + actualFreq = freq; + actualN = n; + actualM = m; + } + } + } + DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); + /* Reset the TWSI logic */ + twsiReset(chanNum); + + /* Set the baud rate */ + val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); + MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); + + /* Enable the TWSI and slave */ + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); + + /* set the TWSI slave address */ + if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ + { + /* writing the 2 most significant bits of the 10 bit address*/ + val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); + /* bits 7:3 must be 0x11110 */ + val |= TWSI_SLAVE_ADDR_10BIT_CONST; + /* set GCE bit */ + if(generalCallEnable) + val |= TWSI_SLAVE_ADDR_GCE_ENA; + /* write slave address */ + MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); + + /* writing the 8 least significant bits of the 10 bit address*/ + val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; + MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); + } + else /*7 bit address*/ + { + /* set the 7 Bits address */ + MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); + val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; + MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); + } + + /* unmask twsi int */ + val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); + /* Add delay of 1ms */ + mvOsDelay(1); + + return actualFreq; +} + + +/******************************************************************************* +* twsiStsGet - Get the TWSI status value. +* +* DESCRIPTION: +* This routine returns the TWSI status value. +* +* INPUT: +* chanNum - TWSI channel +* +* OUTPUT: +* None. +* +* RETURN: +* MV_U32 - the TWSI status. +* +*******************************************************************************/ +static MV_U32 twsiStsGet(MV_U8 chanNum) +{ + return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); + +} + +/******************************************************************************* +* twsiReset - Reset the TWSI. +* +* DESCRIPTION: +* Resets the TWSI logic and sets all TWSI registers to their reset values. +* +* INPUT: +* chanNum - TWSI channel +* +* OUTPUT: +* None. +* +* RETURN: +* None +* +*******************************************************************************/ +static MV_VOID twsiReset(MV_U8 chanNum) +{ + /* Reset the TWSI logic */ + MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); + + /* wait for 2 mili sec */ + mvOsDelay(2); + + return; +} + + + + +/******************************* POLICY ****************************************/ + + + +/******************************************************************************* +* mvTwsiAddrSet - Set address on TWSI bus. +* +* DESCRIPTION: +* This function Set address (7 or 10 Bit address) on the Twsi Bus. +* +* INPUT: +* chanNum - TWSI channel +* pTwsiAddr - twsi address. +* command - read / write . +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if setting the address completed succesfully. +* MV_FAIL otherwmise. +* +*******************************************************************************/ +MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) +{ + DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ + pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); + /* 10 Bit address */ + if(pTwsiAddr->type == ADDR10_BIT) + { + return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); + } + /* 7 Bit address */ + else + { + return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); + } + +} + +/******************************************************************************* +* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. +* +* DESCRIPTION: +* There are two address phases: +* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB +* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit +* to the Data register. Then it clears interrupt flag which drive +* the address on the TWSI bus. The function then waits for interrupt +* flag to be active and status 0x18 (write) or 0x40 (read) to be set. +* 2) write the rest of 10-bit address to data register and clears +* interrupt flag which drive the address on the TWSI bus. The +* function then waits for interrupt flag to be active and status +* 0xD0 (write) or 0xE0 (read) to be set. +* +* INPUT: +* chanNum - TWSI channel +* deviceAddress - twsi address. +* command - read / write . +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if setting the address completed succesfully. +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) +{ + MV_U32 val,timeout; + + /* writing the 2 most significant bits of the 10 bit address*/ + val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); + /* bits 7:3 must be 0x11110 */ + val |= TWSI_DATA_ADDR_10BIT_CONST; + /* set command */ + val |= command; + MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); + /* WA add a delay */ + mvOsDelay(1); + + /* clear Int flag */ + twsiIntFlgClr(chanNum); + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) + return MV_TIMEOUT; + + /* check the status */ + val = twsiStsGet(chanNum); + if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || + ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) + { + mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ + ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); + return MV_FAIL; + } + + /* set 8 LSB of the address */ + val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; + MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); + + /* clear Int flag */ + twsiIntFlgClr(chanNum); + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) + return MV_TIMEOUT; + + /* check the status */ + val = twsiStsGet(chanNum); + if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || + ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) + { + mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ + ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. +* +* DESCRIPTION: +* This function writes 7 bit address plus a write or read bit to the +* Data register. Then it clears interrupt flag which drive the address on +* the TWSI bus. The function then waits for interrupt flag to be active +* and status 0x18 (write) or 0x40 (read) to be set. +* +* INPUT: +* chanNum - TWSI channel +* deviceAddress - twsi address. +* command - read / write . +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if setting the address completed succesfully. +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) +{ + MV_U32 val,timeout; + + /* set the address */ + val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; + /* set command */ + val |= command; + MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); + /* WA add a delay */ + mvOsDelay(1); + + /* clear Int flag */ + twsiIntFlgClr(chanNum); + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) + return MV_TIMEOUT; + + /* check the status */ + val = twsiStsGet(chanNum); + if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || + ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) + { + /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't + want error messeges in case DIMM doesn't exist. */ + DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ + ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); + return MV_FAIL; + } + + return MV_OK; +} + +/******************************************************************************* +* twsiDataWrite - Trnasmit a data block over TWSI bus. +* +* DESCRIPTION: +* This function writes a given data block to TWSI bus in 8 bit granularity. +* first The function waits for interrupt flag to be active then +* For each 8-bit data: +* The function writes data to data register. It then clears +* interrupt flag which drives the data on the TWSI bus. +* The function then waits for interrupt flag to be active and status +* 0x28 to be set. +* +* +* INPUT: +* chanNum - TWSI channel +* pBlock - Data block. +* blockSize - number of chars in pBlock. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if transmiting the block completed succesfully, +* MV_BAD_PARAM - if pBlock is NULL, +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) +{ + MV_U32 timeout, temp, blockSizeWr = blockSize; + + if(NULL == pBlock) + return MV_BAD_PARAM; + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) + return MV_TIMEOUT; + + while(blockSizeWr) + { + /* write the data*/ + MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); + DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ + blockSize - blockSizeWr, *pBlock)); + pBlock++; + blockSizeWr--; + + twsiIntFlgClr(chanNum); + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) + return MV_TIMEOUT; + + /* check the status */ + temp = twsiStsGet(chanNum); + if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) + { + mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); + return MV_FAIL; + } + + } + + return MV_OK; +} + +/******************************************************************************* +* twsiDataReceive - Receive data block from TWSI bus. +* +* DESCRIPTION: +* This function receive data block from TWSI bus in 8bit granularity +* into pBlock buffer. +* first The function waits for interrupt flag to be active then +* For each 8-bit data: +* It clears the interrupt flag which allows the next data to be +* received from TWSI bus. +* The function waits for interrupt flag to be active, +* and status reg is 0x50. +* Then the function reads data from data register, and copies it to +* the given buffer. +* +* INPUT: +* chanNum - TWSI channel +* blockSize - number of bytes to read. +* +* OUTPUT: +* pBlock - Data block. +* +* RETURN: +* MV_OK - if receive transaction completed succesfully, +* MV_BAD_PARAM - if pBlock is NULL, +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) +{ + MV_U32 timeout, temp, blockSizeRd = blockSize; + if(NULL == pBlock) + return MV_BAD_PARAM; + + /* wait for Int to be Set */ + timeout = 0; + while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) + return MV_TIMEOUT; + + while(blockSizeRd) + { + if(blockSizeRd == 1) + { + /* clear ack and Int flag */ + temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); + temp &= ~(TWSI_CONTROL_ACK); + MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); + } + twsiIntFlgClr(chanNum); + /* wait for Int to be Set */ + timeout = 0; + while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); + + /* check for timeout */ + if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) + return MV_TIMEOUT; + + /* check the status */ + temp = twsiStsGet(chanNum); + if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) + { + mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); + return MV_FAIL; + } + else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) + { + mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); + return MV_FAIL; + } + + /* read the data*/ + *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); + DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ + blockSize - blockSizeRd,*pBlock)); + pBlock++; + blockSizeRd--; + } + + return MV_OK; +} + + + +/******************************************************************************* +* twsiTargetOffsSet - Set TWST target offset on TWSI bus. +* +* DESCRIPTION: +* The function support TWSI targets that have inside address space (for +* example EEPROMs). The function: +* 1) Convert the given offset into pBlock and size. +* in case the offset should be set to a TWSI slave which support +* more then 256 bytes offset, the offset setting will be done +* in 2 transactions. +* 2) Use twsiDataTransmit to place those on the bus. +* +* INPUT: +* chanNum - TWSI channel +* offset - offset to be set on the EEPROM device. +* moreThen256 - whether the EEPROM device support more then 256 byte offset. +* +* OUTPUT: +* None. +* +* RETURN: +* MV_OK - if setting the offset completed succesfully. +* MV_FAIL otherwmise. +* +*******************************************************************************/ +static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) +{ + MV_U8 offBlock[2]; + MV_U32 offSize; + + if(moreThen256 == MV_TRUE) + { + offBlock[0] = (offset >> 8) & 0xff; + offBlock[1] = offset & 0xff; + offSize = 2; + } + else + { + offBlock[0] = offset & 0xff; + offSize = 1; + } + DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ + offSize,offBlock[0],offBlock[1])); + return twsiDataTransmit(chanNum, offBlock, offSize); + +} + +/******************************************************************************* +* mvTwsiRead - Read data block from a TWSI Slave. +* +* DESCRIPTION: +* The function calls the following functions: +* -) mvTwsiStartBitSet(); +* if(EEPROM device) +* -) mvTwsiAddrSet(w); +* -) twsiTargetOffsSet(); +* -) mvTwsiStartBitSet(); +* -) mvTwsiAddrSet(r); +* -) twsiDataReceive(); +* -) mvTwsiStopBitSet(); +* +* INPUT: +* chanNum - TWSI channel +* pTwsiSlave - Twsi Slave structure. +* blockSize - number of bytes to read. +* +* OUTPUT: +* pBlock - Data block. +* +* RETURN: +* MV_OK - if EEPROM read transaction completed succesfully, +* MV_BAD_PARAM - if pBlock is NULL, +* MV_FAIL otherwmise. +* +*******************************************************************************/ +MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) +{ + if((NULL == pBlock) || (NULL == pTwsiSlave)) + return MV_BAD_PARAM; + if(MV_OK != mvTwsiStartBitSet(chanNum)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); + + /* in case offset exsist (i.e. eeprom ) */ + if(MV_TRUE == pTwsiSlave->validOffset) + { + if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); + if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); + if(MV_OK != mvTwsiStartBitSet(chanNum)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); + } + if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); + if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); + + if(MV_OK != mvTwsiStopBitSet(chanNum)) + { + return MV_FAIL; + } + + twsiAckBitSet(chanNum); + + DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); + + return MV_OK; +} + +/******************************************************************************* +* mvTwsiWrite - Write data block to a TWSI Slave. +* +* DESCRIPTION: +* The function calls the following functions: +* -) mvTwsiStartBitSet(); +* -) mvTwsiAddrSet(); +* -)if(EEPROM device) +* -) twsiTargetOffsSet(); +* -) twsiDataTransmit(); +* -) mvTwsiStopBitSet(); +* +* INPUT: +* chanNum - TWSI channel +* eepromAddress - eeprom address. +* blockSize - number of bytes to write. +* pBlock - Data block. +* +* OUTPUT: +* None +* +* RETURN: +* MV_OK - if EEPROM read transaction completed succesfully. +* MV_BAD_PARAM - if pBlock is NULL, +* MV_FAIL otherwmise. +* +* NOTE: Part of the EEPROM, required that the offset will be aligned to the +* max write burst supported. +*******************************************************************************/ +MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) +{ + if((NULL == pBlock) || (NULL == pTwsiSlave)) + return MV_BAD_PARAM; + + if(MV_OK != mvTwsiStartBitSet(chanNum)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + + DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); + if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); + + /* in case offset exsist (i.e. eeprom ) */ + if(MV_TRUE == pTwsiSlave->validOffset) + { + if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); + } + if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) + { + mvTwsiStopBitSet(chanNum); + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); + if(MV_OK != mvTwsiStopBitSet(chanNum)) + { + return MV_FAIL; + } + DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); + + return MV_OK; +} diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h new file mode 100644 index 0000000..bd5b6d0 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h @@ -0,0 +1,121 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef __INCmvTwsiH +#define __INCmvTwsiH + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* need to update this includes */ +#include "twsi/mvTwsiSpec.h" +#include "ctrlEnv/mvCtrlEnvLib.h" + + +/* The TWSI interface supports both 7-bit and 10-bit addressing. */ +/* This enumerator describes addressing type. */ +typedef enum _mvTwsiAddrType +{ + ADDR7_BIT, /* 7 bit address */ + ADDR10_BIT /* 10 bit address */ +}MV_TWSI_ADDR_TYPE; + +/* This structure describes TWSI address. */ +typedef struct _mvTwsiAddr +{ + MV_U32 address; /* address */ + MV_TWSI_ADDR_TYPE type; /* Address type */ +}MV_TWSI_ADDR; + +/* This structure describes a TWSI slave. */ +typedef struct _mvTwsiSlave +{ + MV_TWSI_ADDR slaveAddr; + MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ + MV_U32 offset; /* offset in the slave. */ + MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ +}MV_TWSI_SLAVE; + +/* This enumerator describes TWSI protocol commands. */ +typedef enum _mvTwsiCmd +{ + MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ + MV_TWSI_READ /* TWSI read command - 1 according to spec */ +}MV_TWSI_CMD; + +MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); +MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); +MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); + +MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); +MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); +MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvTwsiH */ + diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S new file mode 100644 index 0000000..9d81ef2 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S @@ -0,0 +1,457 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + + +/* includes */ +#define MV_ASMLANGUAGE +#include "ctrlEnv/mvCtrlEnvSpec.h" +#include "boardEnv/mvBoardEnvSpec.h" +#include "mvOsAsm.h" +#include "mvTwsiSpec.h" +#include "mvSysHwConfig.h" +#include "ctrlEnv/sys/mvCpuIfRegs.h" +#include "mvCommon.h" + +#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL + +/* defines */ +/* defines */ + + + .data + .global _i2cInit + .global _i2cRead + + .text + +/******************************************************************************* +* _i2cInit - Initialize TWSI interface +* +* DESCRIPTION: +* The function performs TWSI interface initialization. It resets the +* TWSI state machine and initialize its clock to 100KHz assuming Tclock +* of 133MHz. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +_i2cInit: + mov r9, LR /* Save link register */ + mov r0, #0 /* Make sure r0 is zero */ + + /* Reset the i2c Mechanism first */ + MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH)) + + bl _twsiDelay + bl _twsiDelay + + /* Initializing the I2C mechanism. Assuming Tclock frequency */ + /* of 166MHz. The I2C frequency in that case will be 100KHz. */ + /* For this settings, M = 9 and N = 3. Set the baud-rate with the */ + /* value of 0x2b (freq of ==> 100KHz */ + /* see spec for more details about the calculation of this value) */ + mov r6, #(9 << 3 | 3) + MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + + /* Enable the I2C master */ + /* Enable TWSI interrupt in main mask reg */ + mov r6, #0xC4 + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + + /* Let the slow TWSI machine get used to the idea that it is enabled */ + bl _twsiDelay + + + mov PC, r9 /* r9 is saved link register */ + +/******************************************************************************* +* _twsiDelay - Perform delay. +* +* DESCRIPTION: +* The function performs a delay to enable TWSI logic to stable. +* +* INPUT: +* None. +* +* OUTPUT: +* None. +* +* RETURN: +* None. +* +*******************************************************************************/ +_twsiDelay: + mov r10, #0x100000 /*was 0x400*/ + +_twsiDelayLoop: + subs r10, r10, #1 + bne _twsiDelayLoop + + mov PC, LR + +/******************************************************************************* +* _i2cRead - Read byte from I2C EEPROM device. +* +* DESCRIPTION: +* The function returns a byte from I2C EEPROM device. +* The EEPROM device is 7-bit address type. +* +* INPUT: +* r4 has the DIMM0 base address with shift 1 bit to the left +* r7 has the EEPROM offset +* +* OUTPUT: +* None. +* +* RETURN: +* r4 returns '0' if address can not be read. +* r7 has byte value in case read is successful. +* +*******************************************************************************/ +_i2cRead: + mov r9, LR /* Save link register */ + + /* Transmit the device address and desired offset within the EEPROM. */ + + /* Generate Start Bit */ + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + orr r6, r6, #TWSI_CONTROL_START_BIT + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + + /* Wait for the interrupt flag (bit3) to be set */ + mov r10, #0x50000 +loop_1: + subs r10, r10, #1 + beq loop_1_timeout +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_1 + +loop_1_timeout: + + /* Wait for the start bit to be reset by HW */ + mov r10, #0x50000 +loop_2: + subs r10, r10, #1 + beq loop_2_timeout + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + tst r6, #TWSI_CONTROL_START_BIT + bne loop_2 + +loop_2_timeout: + + /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */ + mov r10, #0x50000 +loop_3: + subs r10, r10, #1 + beq loop_3_timeout + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x08 + bne loop_3 + +loop_3_timeout: + + /* writing the address of (DIMM0/1 << 1) with write indication */ + mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */ + MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) + + bl _twsiDelay + /* Clear the interrupt flag */ + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Waiting for the interrupt flag to be set which means that the + address has been transmitted */ +loop_4: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_4 /* if tst = 0, then the bit is not set yet */ + + /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */ + mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */ + +loop_5: + subs r10, r10, #1 /* timeout count down */ + bne testStatus + mov r4, #0 /* r4 = 0 -> operation failed */ + b exit_i2cRead /* Exit if timeout (No DIMM) */ + +testStatus: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x18 + bne loop_5 + + + /* check if the offset is bigger than 256 byte*/ + tst r7, #0x80000000 + bne great_than_256 + + /* Write the offset to be read from the DIMM EEPROM */ + MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) + + b after_offset + +great_than_256: + mov r10, r7, LSR #8 + and r10, r10, #0xff + /* Write the offset0 to be read from the EEPROM */ + MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) + + /* Clear the interrupt flag ==> signaling that the address can now + be transmited */ + + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt to be set again ==> address has transmited */ +loop_6_1: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_6_1 + + /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ +loop_7_1: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x28 + bne loop_7_1 + + + mov r10, r7 + and r10, r10, #0xff + /* Write the offset1 to be read from the EEPROM */ + MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) + + + +after_offset: + + /* Clear the interrupt flag ==> signaling that the address can now + be transmited */ + + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt to be set again ==> address has transmited */ +loop_6: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_6 + + /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ +loop_7: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x28 + bne loop_7 + + /* Retransmit the device address with read indication to get the data */ + + /* generate a repeated start bit */ + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + orr r6, r6, #TWSI_CONTROL_START_BIT + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + + + /* Clear the interrupt flag ==> the start bit will be transmitted. */ + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt flag (bit3) to be set */ +loop_9: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_9 + + /* Wait for the start bit to be reset by HW */ +loop_8: + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + tst r6, #TWSI_CONTROL_START_BIT + bne loop_8 + + /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */ +loop_10: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x10 + bne loop_10 + + /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */ + mov r6, r4, LSL #1 + orr r6, r6, #1 /* Read operation address bit 0 must be 1 */ + MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) + + /* Clear the interrupt flag ==> the address will be transmitted */ + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt flag (bit3) to be set as a result of + transmitting the address. */ +loop_11: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_11 + + /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */ +loop_12: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x40 + bne loop_12 + + /* Clear the interrupt flag and the Acknoledge bit */ + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK) + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the interrupt flag (bit3) to be set */ +loop_14: +#ifdef MV78XX0 + MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) + tst r6, #BIT2 +#else + MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) + tst r6, #BIT5 +#endif + beq loop_14 + + /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */ +loop_15: + MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) + cmp r6, #0x58 + bne loop_15 + + /* Store the data in r7. */ + MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) + + /* Generate stop bit */ + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + orr r6, r6, #TWSI_CONTROL_STOP_BIT + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + + + /* Clear the interrupt flag */ + bl _twsiDelay + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET + MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + bl _twsiDelay + + /* Wait for the stop bit to be reset by HW */ +loop_16: + MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) + tst r6, #TWSI_CONTROL_INT_FLAG_SET + bne loop_16 + +exit_i2cRead: + mov PC, r9 /* r9 is saved link register */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h new file mode 100644 index 0000000..d0c2b9e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h @@ -0,0 +1,160 @@ +/******************************************************************************* +Copyright (C) Marvell International Ltd. and its affiliates + +This software file (the "File") is owned and distributed by Marvell +International Ltd. and/or its affiliates ("Marvell") under the following +alternative licensing terms. Once you have made an election to distribute the +File under one of the following license alternatives, please (i) delete this +introductory statement regarding license alternatives, (ii) delete the two +license alternatives that you have not elected to use and (iii) preserve the +Marvell copyright notice above. + +******************************************************************************** +Marvell Commercial License Option + +If you received this File from Marvell and you have entered into a commercial +license agreement (a "Commercial License") with Marvell, the File is licensed +to you under the terms of the applicable Commercial License. + +******************************************************************************** +Marvell GPL License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File in accordance with the terms and conditions of the General +Public License Version 2, June 1991 (the "GPL License"), a copy of which is +available along with the File in the license.txt file or by writing to the Free +Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or +on the worldwide web at http://www.gnu.org/licenses/gpl.txt. + +THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED +WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY +DISCLAIMED. The GPL License provides additional details about this warranty +disclaimer. +******************************************************************************** +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute and/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + * Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +/****************************************/ +/* TWSI Registers */ +/****************************************/ +#ifndef __INCmvTwsiSpech +#define __INCmvTwsiSpech + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines */ +#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) + +#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 +#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 +#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) +#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 +#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 +#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 + + +#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) +#define TWSI_EXTENDED_SLAVE_OFFS 0 +#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) + + +#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) +#define TWSI_DATA_COMMAND_OFFS 0x0 +#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) +#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) +#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) +#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 +#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) +#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 +#define TWSI_DATA_ADDR_10BIT_MASK 0x300 +#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 + + +#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) +#define TWSI_CONTROL_ACK BIT2 +#define TWSI_CONTROL_INT_FLAG_SET BIT3 +#define TWSI_CONTROL_STOP_BIT BIT4 +#define TWSI_CONTROL_START_BIT BIT5 +#define TWSI_CONTROL_ENA BIT6 +#define TWSI_CONTROL_INT_ENA BIT7 + + +#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) +#define TWSI_BAUD_RATE_N_OFFS 0 +#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) +#define TWSI_BAUD_RATE_M_OFFS 3 +#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) + +#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) + +/* defines */ +#define TWSI_TIMEOUT_VALUE 0x500 + +/* TWSI status codes */ +#define TWSI_BUS_ERROR 0x00 +#define TWSI_START_CON_TRA 0x08 +#define TWSI_REPEATED_START_CON_TRA 0x10 +#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 +#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 +#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 +#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 +#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 +#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 +#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 +#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 +#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 +#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 +#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 +#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 +#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 +#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 +#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 +#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 +#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 +#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 +#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 +#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 +#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 +#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 +#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 +#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 +#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 +#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 +#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 +#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCmvTwsiSpech */ diff --git a/target/linux/generic/files/crypto/ocf/ocf-bench.c b/target/linux/generic/files/crypto/ocf/ocf-bench.c new file mode 100644 index 0000000..a9a9538 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ocf-bench.c @@ -0,0 +1,514 @@ +/* + * A loadable module that benchmarks the OCF crypto speed from kernel space. + * + * Copyright (C) 2004-2010 David McCullough + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * ALTERNATIVELY, provided that this notice is retained in full, this product + * may be distributed under the terms of the GNU General Public License (GPL), + * in which case the provisions of the GPL apply INSTEAD OF those given above. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + */ + + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK +#define BENCH_IXP_ACCESS_LIB 1 +#endif +#ifdef BENCH_IXP_ACCESS_LIB +#include +#include +#include +#include +#include +#include +#include +#endif + +/* + * support for access lib version 1.4 + */ +#ifndef IX_MBUF_PRIV +#define IX_MBUF_PRIV(x) ((x)->priv) +#endif + +/* + * the number of simultaneously active requests + */ +static int request_q_len = 40; +module_param(request_q_len, int, 0); +MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); + +/* + * how many requests we want to have processed + */ +static int request_num = 1024; +module_param(request_num, int, 0); +MODULE_PARM_DESC(request_num, "run for at least this many requests"); + +/* + * the size of each request + */ +static int request_size = 1488; +module_param(request_size, int, 0); +MODULE_PARM_DESC(request_size, "size of each request"); + +/* + * OCF batching of requests + */ +static int request_batch = 1; +module_param(request_batch, int, 0); +MODULE_PARM_DESC(request_batch, "enable OCF request batching"); + +/* + * OCF immediate callback on completion + */ +static int request_cbimm = 1; +module_param(request_cbimm, int, 0); +MODULE_PARM_DESC(request_cbimm, "enable OCF immediate callback on completion"); + +/* + * a structure for each request + */ +typedef struct { + struct work_struct work; +#ifdef BENCH_IXP_ACCESS_LIB + IX_MBUF mbuf; +#endif + unsigned char *buffer; +} request_t; + +static request_t *requests; + +static spinlock_t ocfbench_counter_lock; +static int outstanding; +static int total; + +/*************************************************************************/ +/* + * OCF benchmark routines + */ + +static uint64_t ocf_cryptoid; +static unsigned long jstart, jstop; + +static int ocf_init(void); +static int ocf_cb(struct cryptop *crp); +static void ocf_request(void *arg); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +static void ocf_request_wq(struct work_struct *work); +#endif + +static int +ocf_init(void) +{ + int error; + struct cryptoini crie, cria; + struct cryptodesc crda, crde; + + memset(&crie, 0, sizeof(crie)); + memset(&cria, 0, sizeof(cria)); + memset(&crde, 0, sizeof(crde)); + memset(&crda, 0, sizeof(crda)); + + cria.cri_alg = CRYPTO_SHA1_HMAC; + cria.cri_klen = 20 * 8; + cria.cri_key = "0123456789abcdefghij"; + + //crie.cri_alg = CRYPTO_3DES_CBC; + crie.cri_alg = CRYPTO_AES_CBC; + crie.cri_klen = 24 * 8; + crie.cri_key = "0123456789abcdefghijklmn"; + + crie.cri_next = &cria; + + error = crypto_newsession(&ocf_cryptoid, &crie, + CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE); + if (error) { + printk("crypto_newsession failed %d\n", error); + return -1; + } + return 0; +} + +static int +ocf_cb(struct cryptop *crp) +{ + request_t *r = (request_t *) crp->crp_opaque; + unsigned long flags; + + if (crp->crp_etype) + printk("Error in OCF processing: %d\n", crp->crp_etype); + crypto_freereq(crp); + crp = NULL; + + /* do all requests but take at least 1 second */ + spin_lock_irqsave(&ocfbench_counter_lock, flags); + total++; + if (total > request_num && jstart + HZ < jiffies) { + outstanding--; + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + return 0; + } + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + + schedule_work(&r->work); + return 0; +} + + +static void +ocf_request(void *arg) +{ + request_t *r = arg; + struct cryptop *crp = crypto_getreq(2); + struct cryptodesc *crde, *crda; + unsigned long flags; + + if (!crp) { + spin_lock_irqsave(&ocfbench_counter_lock, flags); + outstanding--; + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + return; + } + + crde = crp->crp_desc; + crda = crde->crd_next; + + crda->crd_skip = 0; + crda->crd_flags = 0; + crda->crd_len = request_size; + crda->crd_inject = request_size; + crda->crd_alg = CRYPTO_SHA1_HMAC; + crda->crd_key = "0123456789abcdefghij"; + crda->crd_klen = 20 * 8; + + crde->crd_skip = 0; + crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; + crde->crd_len = request_size; + crde->crd_inject = request_size; + //crde->crd_alg = CRYPTO_3DES_CBC; + crde->crd_alg = CRYPTO_AES_CBC; + crde->crd_key = "0123456789abcdefghijklmn"; + crde->crd_klen = 24 * 8; + + crp->crp_ilen = request_size + 64; + crp->crp_flags = 0; + if (request_batch) + crp->crp_flags |= CRYPTO_F_BATCH; + if (request_cbimm) + crp->crp_flags |= CRYPTO_F_CBIMM; + crp->crp_buf = (caddr_t) r->buffer; + crp->crp_callback = ocf_cb; + crp->crp_sid = ocf_cryptoid; + crp->crp_opaque = (caddr_t) r; + crypto_dispatch(crp); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +static void +ocf_request_wq(struct work_struct *work) +{ + request_t *r = container_of(work, request_t, work); + ocf_request(r); +} +#endif + +static void +ocf_done(void) +{ + crypto_freesession(ocf_cryptoid); +} + +/*************************************************************************/ +#ifdef BENCH_IXP_ACCESS_LIB +/*************************************************************************/ +/* + * CryptoAcc benchmark routines + */ + +static IxCryptoAccCtx ixp_ctx; +static UINT32 ixp_ctx_id; +static IX_MBUF ixp_pri; +static IX_MBUF ixp_sec; +static int ixp_registered = 0; + +static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, + IxCryptoAccStatus status); +static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, + IxCryptoAccStatus status); +static void ixp_request(void *arg); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +static void ixp_request_wq(struct work_struct *work); +#endif + +static int +ixp_init(void) +{ + IxCryptoAccStatus status; + + ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; + ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; + ixp_ctx.cipherCtx.cipherKeyLen = 24; + ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; + ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; + memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); + + ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; + ixp_ctx.authCtx.authDigestLen = 12; + ixp_ctx.authCtx.aadLen = 0; + ixp_ctx.authCtx.authKeyLen = 20; + memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); + + ixp_ctx.useDifferentSrcAndDestMbufs = 0; + ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; + + IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; + IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); + IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; + IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); + + status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, + ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); + + if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { + while (!ixp_registered) + schedule(); + return ixp_registered < 0 ? -1 : 0; + } + + printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); + return -1; +} + +static void +ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) +{ + if (bufp) { + IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; + kfree(IX_MBUF_MDATA(bufp)); + IX_MBUF_MDATA(bufp) = NULL; + } + + if (IX_CRYPTO_ACC_STATUS_WAIT == status) + return; + if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) + ixp_registered = 1; + else + ixp_registered = -1; +} + +static void +ixp_perform_cb( + UINT32 ctx_id, + IX_MBUF *sbufp, + IX_MBUF *dbufp, + IxCryptoAccStatus status) +{ + request_t *r = NULL; + unsigned long flags; + + /* do all requests but take at least 1 second */ + spin_lock_irqsave(&ocfbench_counter_lock, flags); + total++; + if (total > request_num && jstart + HZ < jiffies) { + outstanding--; + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + return; + } + + if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { + printk("crappo %p %p\n", sbufp, r); + outstanding--; + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + return; + } + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + + schedule_work(&r->work); +} + +static void +ixp_request(void *arg) +{ + request_t *r = arg; + IxCryptoAccStatus status; + unsigned long flags; + + memset(&r->mbuf, 0, sizeof(r->mbuf)); + IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; + IX_MBUF_MDATA(&r->mbuf) = r->buffer; + IX_MBUF_PRIV(&r->mbuf) = r; + status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, + 0, request_size, 0, request_size, request_size, r->buffer); + if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { + printk("status1 = %d\n", status); + spin_lock_irqsave(&ocfbench_counter_lock, flags); + outstanding--; + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + return; + } + return; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) +static void +ixp_request_wq(struct work_struct *work) +{ + request_t *r = container_of(work, request_t, work); + ixp_request(r); +} +#endif + +static void +ixp_done(void) +{ + /* we should free the session here but I am lazy :-) */ +} + +/*************************************************************************/ +#endif /* BENCH_IXP_ACCESS_LIB */ +/*************************************************************************/ + +int +ocfbench_init(void) +{ + int i; + unsigned long mbps; + unsigned long flags; + + printk("Crypto Speed tests\n"); + + requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); + if (!requests) { + printk("malloc failed\n"); + return -EINVAL; + } + + for (i = 0; i < request_q_len; i++) { + /* +64 for return data */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + INIT_WORK(&requests[i].work, ocf_request_wq); +#else + INIT_WORK(&requests[i].work, ocf_request, &requests[i]); +#endif + requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); + if (!requests[i].buffer) { + printk("malloc failed\n"); + return -EINVAL; + } + memset(requests[i].buffer, '0' + i, request_size + 128); + } + + /* + * OCF benchmark + */ + printk("OCF: testing ...\n"); + if (ocf_init() == -1) + return -EINVAL; + + spin_lock_init(&ocfbench_counter_lock); + total = outstanding = 0; + jstart = jiffies; + for (i = 0; i < request_q_len; i++) { + spin_lock_irqsave(&ocfbench_counter_lock, flags); + outstanding++; + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + ocf_request(&requests[i]); + } + while (outstanding > 0) + schedule(); + jstop = jiffies; + + mbps = 0; + if (jstop > jstart) { + mbps = (unsigned long) total * (unsigned long) request_size * 8; + mbps /= ((jstop - jstart) * 1000) / HZ; + } + printk("OCF: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", + total, request_size, (int)(jstop - jstart), + ((int)mbps) / 1000, ((int)mbps) % 1000); + ocf_done(); + +#ifdef BENCH_IXP_ACCESS_LIB + /* + * IXP benchmark + */ + printk("IXP: testing ...\n"); + ixp_init(); + total = outstanding = 0; + jstart = jiffies; + for (i = 0; i < request_q_len; i++) { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + INIT_WORK(&requests[i].work, ixp_request_wq); +#else + INIT_WORK(&requests[i].work, ixp_request, &requests[i]); +#endif + spin_lock_irqsave(&ocfbench_counter_lock, flags); + outstanding++; + spin_unlock_irqrestore(&ocfbench_counter_lock, flags); + ixp_request(&requests[i]); + } + while (outstanding > 0) + schedule(); + jstop = jiffies; + + mbps = 0; + if (jstop > jstart) { + mbps = (unsigned long) total * (unsigned long) request_size * 8; + mbps /= ((jstop - jstart) * 1000) / HZ; + } + printk("IXP: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", + total, request_size, jstop - jstart, + ((int)mbps) / 1000, ((int)mbps) % 1000); + ixp_done(); +#endif /* BENCH_IXP_ACCESS_LIB */ + + for (i = 0; i < request_q_len; i++) + kfree(requests[i].buffer); + kfree(requests); + return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ +} + +static void __exit ocfbench_exit(void) +{ +} + +module_init(ocfbench_init); +module_exit(ocfbench_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); diff --git a/target/linux/generic/files/crypto/ocf/ocf-compat.h b/target/linux/generic/files/crypto/ocf/ocf-compat.h new file mode 100644 index 0000000..b38cf27 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ocf-compat.h @@ -0,0 +1,380 @@ +#ifndef _BSD_COMPAT_H_ +#define _BSD_COMPAT_H_ 1 +/****************************************************************************/ +/* + * Provide compat routines for older linux kernels and BSD kernels + * + * Written by David McCullough + * Copyright (C) 2010 David McCullough + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * ALTERNATIVELY, provided that this notice is retained in full, this file + * may be distributed under the terms of the GNU General Public License (GPL), + * in which case the provisions of the GPL apply INSTEAD OF those given above. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + */ +/****************************************************************************/ +#ifdef __KERNEL__ +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif + +/* + * fake some BSD driver interface stuff specifically for OCF use + */ + +typedef struct ocf_device *device_t; + +typedef struct { + int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); + int (*cryptodev_freesession)(device_t dev, u_int64_t tid); + int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); + int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); +} device_method_t; +#define DEVMETHOD(id, func) id: func + +struct ocf_device { + char name[32]; /* the driver name */ + char nameunit[32]; /* the driver name + HW instance */ + int unit; + device_method_t methods; + void *softc; +}; + +#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ + ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) +#define CRYPTODEV_FREESESSION(dev, sid) \ + ((*(dev)->methods.cryptodev_freesession)(dev, sid)) +#define CRYPTODEV_PROCESS(dev, crp, hint) \ + ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) +#define CRYPTODEV_KPROCESS(dev, krp, hint) \ + ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) + +#define device_get_name(dev) ((dev)->name) +#define device_get_nameunit(dev) ((dev)->nameunit) +#define device_get_unit(dev) ((dev)->unit) +#define device_get_softc(dev) ((dev)->softc) + +#define softc_device_decl \ + struct ocf_device _device; \ + device_t + +#define softc_device_init(_sc, _name, _unit, _methods) \ + if (1) {\ + strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ + snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ + (_sc)->_device.unit = _unit; \ + (_sc)->_device.methods = _methods; \ + (_sc)->_device.softc = (void *) _sc; \ + *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ + } else + +#define softc_get_device(_sc) (&(_sc)->_device) + +/* + * iomem support for 2.4 and 2.6 kernels + */ +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#define ocf_iomem_t unsigned long + +/* + * implement simple workqueue like support for older kernels + */ + +#include + +#define work_struct tq_struct + +#define INIT_WORK(wp, fp, ap) \ + do { \ + (wp)->sync = 0; \ + (wp)->routine = (fp); \ + (wp)->data = (ap); \ + } while (0) + +#define schedule_work(wp) \ + do { \ + queue_task((wp), &tq_immediate); \ + mark_bh(IMMEDIATE_BH); \ + } while (0) + +#define flush_scheduled_work() run_task_queue(&tq_immediate) + +#else +#define ocf_iomem_t void __iomem * + +#include + +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) +#include +#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) +#define files_fdtable(files) (files) +#endif + +#ifdef MODULE_PARM +#undef module_param /* just in case */ +#define module_param(a,b,c) MODULE_PARM(a,"i") +#endif + +#define bzero(s,l) memset(s,0,l) +#define bcopy(s,d,l) memcpy(d,s,l) +#define bcmp(x, y, l) memcmp(x,y,l) + +#define MIN(x,y) ((x) < (y) ? (x) : (y)) + +#define device_printf(dev, a...) ({ \ + printk("%s: ", device_get_nameunit(dev)); printk(a); \ + }) + +#undef printf +#define printf(fmt...) printk(fmt) + +#define KASSERT(c,p) if (!(c)) { printk p ; } else + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#define ocf_daemonize(str) \ + daemonize(); \ + spin_lock_irq(¤t->sigmask_lock); \ + sigemptyset(¤t->blocked); \ + recalc_sigpending(current); \ + spin_unlock_irq(¤t->sigmask_lock); \ + sprintf(current->comm, str); \ +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0) \ + spin_lock_irq(¤t->sigmask_lock); \ + sigemptyset(¤t->blocked); \ + recalc_sigpending(current); \ + spin_unlock_irq(¤t->sigmask_lock); \ + sprintf(current->comm, str); \ +#else +#define ocf_daemonize(str) daemonize(str); +#endif + +#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) +#define TAILQ_EMPTY(q) list_empty(q) +#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) + +#define read_random(p,l) get_random_bytes(p,l) + +#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) +#define strtoul simple_strtoul + +#define pci_get_vendor(dev) ((dev)->vendor) +#define pci_get_device(dev) ((dev)->device) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#define pci_set_consistent_dma_mask(dev, mask) (0) +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) +#define pci_dma_sync_single_for_cpu pci_dma_sync_single +#endif + +#ifndef DMA_32BIT_MASK +#define DMA_32BIT_MASK 0x00000000ffffffffULL +#endif + +#ifndef htole32 +#define htole32(x) cpu_to_le32(x) +#endif +#ifndef htobe32 +#define htobe32(x) cpu_to_be32(x) +#endif +#ifndef htole16 +#define htole16(x) cpu_to_le16(x) +#endif +#ifndef htobe16 +#define htobe16(x) cpu_to_be16(x) +#endif + +/* older kernels don't have these */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) +#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) +#define IRQ_NONE +#define IRQ_HANDLED +#define IRQ_WAKE_THREAD +#define IRQ_RETVAL +#define irqreturn_t void +typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); +#endif +#ifndef IRQF_SHARED +#define IRQF_SHARED SA_SHIRQ +#endif +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +# define strlcpy(dest,src,len) \ + ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) +#endif + +#ifndef MAX_ERRNO +#define MAX_ERRNO 4095 +#endif +#ifndef IS_ERR_VALUE +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) +#include +#endif +#ifndef IS_ERR_VALUE +#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) +#endif +#endif + +/* + * common debug for all + */ +#if 1 +#define dprintk(a...) do { if (debug) printk(a); } while(0) +#else +#define dprintk(a...) +#endif + +#ifndef SLAB_ATOMIC +/* Changed in 2.6.20, must use GFP_ATOMIC now */ +#define SLAB_ATOMIC GFP_ATOMIC +#endif + +/* + * need some additional support for older kernels */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) +#define pci_register_driver_compat(driver, rc) \ + do { \ + if ((rc) > 0) { \ + (rc) = 0; \ + } else if (rc == 0) { \ + (rc) = -ENODEV; \ + } else { \ + pci_unregister_driver(driver); \ + } \ + } while (0) +#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) +#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) +#else +#define pci_register_driver_compat(driver,rc) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + +#include +#include + +static inline void sg_set_page(struct scatterlist *sg, struct page *page, + unsigned int len, unsigned int offset) +{ + sg->page = page; + sg->offset = offset; + sg->length = len; +} + +static inline void *sg_virt(struct scatterlist *sg) +{ + return page_address(sg->page) + sg->offset; +} + +#define sg_init_table(sg, n) + +#define sg_mark_end(sg) + +#endif + +#ifndef late_initcall +#define late_initcall(init) module_init(init) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) || !defined(CONFIG_SMP) +#define ocf_for_each_cpu(cpu) for ((cpu) = 0; (cpu) == 0; (cpu)++) +#else +#define ocf_for_each_cpu(cpu) for_each_present_cpu(cpu) +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) +#include +#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) + +struct ocf_thread { + struct task_struct *task; + int (*func)(void *arg); + void *arg; +}; + +/* thread startup helper func */ +static inline int ocf_run_thread(void *arg) +{ + struct ocf_thread *t = (struct ocf_thread *) arg; + if (!t) + return -1; /* very bad */ + t->task = current; + daemonize(); + spin_lock_irq(¤t->sigmask_lock); + sigemptyset(¤t->blocked); + recalc_sigpending(current); + spin_unlock_irq(¤t->sigmask_lock); + return (*t->func)(t->arg); +} + +#define kthread_create(f,a,fmt...) \ + ({ \ + struct ocf_thread t; \ + pid_t p; \ + t.task = NULL; \ + t.func = (f); \ + t.arg = (a); \ + p = kernel_thread(ocf_run_thread, &t, CLONE_FS|CLONE_FILES); \ + while (p != (pid_t) -1 && t.task == NULL) \ + schedule(); \ + if (t.task) \ + snprintf(t.task->comm, sizeof(t.task->comm), fmt); \ + (t.task); \ + }) + +#define kthread_bind(t,cpu) /**/ + +#define kthread_should_stop() (strcmp(current->comm, "stopping") == 0) + +#define kthread_stop(t) \ + ({ \ + strcpy((t)->comm, "stopping"); \ + kill_proc((t)->pid, SIGTERM, 1); \ + do { \ + schedule(); \ + } while (kill_proc((t)->pid, SIGTERM, 1) == 0); \ + }) + +#else +#include +#endif + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) +#define skb_frag_page(x) ((x)->page) +#endif + +#endif /* __KERNEL__ */ + +/****************************************************************************/ +#endif /* _BSD_COMPAT_H_ */ diff --git a/target/linux/generic/files/crypto/ocf/ocfnull/Makefile b/target/linux/generic/files/crypto/ocf/ocfnull/Makefile new file mode 100644 index 0000000..044bcac --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ocfnull/Makefile @@ -0,0 +1,12 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o + +obj ?= . +EXTRA_CFLAGS += -I$(obj)/.. + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/ocfnull/ocfnull.c b/target/linux/generic/files/crypto/ocf/ocfnull/ocfnull.c new file mode 100644 index 0000000..9cf3f6e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ocfnull/ocfnull.c @@ -0,0 +1,204 @@ +/* + * An OCF module for determining the cost of crypto versus the cost of + * IPSec processing outside of OCF. This modules gives us the effect of + * zero cost encryption, of course you will need to run it at both ends + * since it does no crypto at all. + * + * Written by David McCullough + * Copyright (C) 2006-2010 David McCullough + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * ALTERNATIVELY, provided that this notice is retained in full, this product + * may be distributed under the terms of the GNU General Public License (GPL), + * in which case the provisions of the GPL apply INSTEAD OF those given above. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static int32_t null_id = -1; +static u_int32_t null_sesnum = 0; + +static int null_process(device_t, struct cryptop *, int); +static int null_newsession(device_t, u_int32_t *, struct cryptoini *); +static int null_freesession(device_t, u_int64_t); + +#define debug ocfnull_debug +int ocfnull_debug = 0; +module_param(ocfnull_debug, int, 0644); +MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); + +/* + * dummy device structure + */ + +static struct { + softc_device_decl sc_dev; +} nulldev; + +static device_method_t null_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, null_newsession), + DEVMETHOD(cryptodev_freesession,null_freesession), + DEVMETHOD(cryptodev_process, null_process), +}; + +/* + * Generate a new software session. + */ +static int +null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) +{ + dprintk("%s()\n", __FUNCTION__); + if (sid == NULL || cri == NULL) { + dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + if (null_sesnum == 0) + null_sesnum++; + *sid = null_sesnum++; + return 0; +} + + +/* + * Free a session. + */ +static int +null_freesession(device_t arg, u_int64_t tid) +{ + u_int32_t sid = CRYPTO_SESID2LID(tid); + + dprintk("%s()\n", __FUNCTION__); + if (sid > null_sesnum) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + /* Silently accept and return */ + if (sid == 0) + return 0; + return 0; +} + + +/* + * Process a request. + */ +static int +null_process(device_t arg, struct cryptop *crp, int hint) +{ + unsigned int lid; + + dprintk("%s()\n", __FUNCTION__); + + /* Sanity check */ + if (crp == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + + crp->crp_etype = 0; + + if (crp->crp_desc == NULL || crp->crp_buf == NULL) { + dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); + crp->crp_etype = EINVAL; + goto done; + } + + /* + * find the session we are using + */ + + lid = crp->crp_sid & 0xffffffff; + if (lid >= null_sesnum || lid == 0) { + crp->crp_etype = ENOENT; + dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); + goto done; + } + +done: + crypto_done(crp); + return 0; +} + + +/* + * our driver startup and shutdown routines + */ + +static int +null_init(void) +{ + dprintk("%s(%p)\n", __FUNCTION__, null_init); + + memset(&nulldev, 0, sizeof(nulldev)); + softc_device_init(&nulldev, "ocfnull", 0, null_methods); + + null_id = crypto_get_driverid(softc_get_device(&nulldev), + CRYPTOCAP_F_HARDWARE); + if (null_id < 0) + panic("ocfnull: crypto device cannot initialize!"); + +#define REGISTER(alg) \ + crypto_register(null_id,alg,0,0) + REGISTER(CRYPTO_DES_CBC); + REGISTER(CRYPTO_3DES_CBC); + REGISTER(CRYPTO_RIJNDAEL128_CBC); + REGISTER(CRYPTO_MD5); + REGISTER(CRYPTO_SHA1); + REGISTER(CRYPTO_MD5_HMAC); + REGISTER(CRYPTO_SHA1_HMAC); +#undef REGISTER + + return 0; +} + +static void +null_exit(void) +{ + dprintk("%s()\n", __FUNCTION__); + crypto_unregister_all(null_id); + null_id = -1; +} + +module_init(null_init); +module_exit(null_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); diff --git a/target/linux/generic/files/crypto/ocf/pasemi/Makefile b/target/linux/generic/files/crypto/ocf/pasemi/Makefile new file mode 100644 index 0000000..b0a3980 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/pasemi/Makefile @@ -0,0 +1,12 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_PASEMI) += pasemi.o + +obj ?= . +EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/pasemi/pasemi.c b/target/linux/generic/files/crypto/ocf/pasemi/pasemi.c new file mode 100644 index 0000000..216c578 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/pasemi/pasemi.c @@ -0,0 +1,1007 @@ +/* + * Copyright (C) 2007 PA Semi, Inc + * + * Driver for the PA Semi PWRficient DMA Crypto Engine + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pasemi_fnu.h" + +#define DRV_NAME "pasemi" + +#define TIMER_INTERVAL 1000 + +static void pasemi_dma_remove(struct pci_dev *pdev); +static struct pasdma_status volatile * dma_status; + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Enable debug"); + +static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) +{ + desc->postop = 0; + desc->quad[0] = hdr; + desc->quad_cnt = 1; + desc->size = 1; +} + +static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) +{ + desc->quad[desc->quad_cnt++] = val; + desc->size = (desc->quad_cnt + 1) / 2; +} + +static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) +{ + desc->quad[0] |= hdr; +} + +static int pasemi_desc_size(struct pasemi_desc *desc) +{ + return desc->size; +} + +static void pasemi_ring_add_desc( + struct pasemi_fnu_txring *ring, + struct pasemi_desc *desc, + struct cryptop *crp) { + int i; + int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); + + TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; + TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; + TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; + + for (i = 0; i < desc->quad_cnt; i += 2) { + ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); + ring->desc[ring_index] = desc->quad[i]; + ring->desc[ring_index + 1] = desc->quad[i + 1]; + ring->next_to_fill++; + } + + if (desc->quad_cnt & 1) + ring->desc[ring_index + 1] = 0; +} + +static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) +{ + out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), + incr); +} + +/* + * Generate a new software session. + */ +static int +pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) +{ + struct cryptoini *c, *encini = NULL, *macini = NULL; + struct pasemi_softc *sc = device_get_softc(dev); + struct pasemi_session *ses = NULL, **sespp; + int sesn, blksz = 0; + u64 ccmd = 0; + unsigned long flags; + struct pasemi_desc init_desc; + struct pasemi_fnu_txring *txring; + + DPRINTF("%s()\n", __FUNCTION__); + if (sidp == NULL || cri == NULL || sc == NULL) { + DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); + return -EINVAL; + } + for (c = cri; c != NULL; c = c->cri_next) { + if (ALG_IS_SIG(c->cri_alg)) { + if (macini) + return -EINVAL; + macini = c; + } else if (ALG_IS_CIPHER(c->cri_alg)) { + if (encini) + return -EINVAL; + encini = c; + } else { + DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); + return -EINVAL; + } + } + if (encini == NULL && macini == NULL) + return -EINVAL; + if (encini) { + /* validate key length */ + switch (encini->cri_alg) { + case CRYPTO_DES_CBC: + if (encini->cri_klen != 64) + return -EINVAL; + ccmd = DMA_CALGO_DES; + break; + case CRYPTO_3DES_CBC: + if (encini->cri_klen != 192) + return -EINVAL; + ccmd = DMA_CALGO_3DES; + break; + case CRYPTO_AES_CBC: + if (encini->cri_klen != 128 && + encini->cri_klen != 192 && + encini->cri_klen != 256) + return -EINVAL; + ccmd = DMA_CALGO_AES; + break; + case CRYPTO_ARC4: + if (encini->cri_klen != 128) + return -EINVAL; + ccmd = DMA_CALGO_ARC; + break; + default: + DPRINTF("UNKNOWN encini->cri_alg %d\n", + encini->cri_alg); + return -EINVAL; + } + } + + if (macini) { + switch (macini->cri_alg) { + case CRYPTO_MD5: + case CRYPTO_MD5_HMAC: + blksz = 16; + break; + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + blksz = 20; + break; + default: + DPRINTF("UNKNOWN macini->cri_alg %d\n", + macini->cri_alg); + return -EINVAL; + } + if (((macini->cri_klen + 7) / 8) > blksz) { + DPRINTF("key length %d bigger than blksize %d not supported\n", + ((macini->cri_klen + 7) / 8), blksz); + return -EINVAL; + } + } + + for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { + if (sc->sc_sessions[sesn] == NULL) { + sc->sc_sessions[sesn] = (struct pasemi_session *) + kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); + ses = sc->sc_sessions[sesn]; + break; + } else if (sc->sc_sessions[sesn]->used == 0) { + ses = sc->sc_sessions[sesn]; + break; + } + } + + if (ses == NULL) { + sespp = (struct pasemi_session **) + kzalloc(sc->sc_nsessions * 2 * + sizeof(struct pasemi_session *), GFP_ATOMIC); + if (sespp == NULL) + return -ENOMEM; + memcpy(sespp, sc->sc_sessions, + sc->sc_nsessions * sizeof(struct pasemi_session *)); + kfree(sc->sc_sessions); + sc->sc_sessions = sespp; + sesn = sc->sc_nsessions; + ses = sc->sc_sessions[sesn] = (struct pasemi_session *) + kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); + if (ses == NULL) + return -ENOMEM; + sc->sc_nsessions *= 2; + } + + ses->used = 1; + + ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, + sizeof(struct pasemi_session), DMA_TO_DEVICE); + + /* enter the channel scheduler */ + spin_lock_irqsave(&sc->sc_chnlock, flags); + + /* ARC4 has to be processed by the even channel */ + if (encini && (encini->cri_alg == CRYPTO_ARC4)) + ses->chan = sc->sc_lastchn & ~1; + else + ses->chan = sc->sc_lastchn; + sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; + + spin_unlock_irqrestore(&sc->sc_chnlock, flags); + + txring = &sc->tx[ses->chan]; + + if (encini) { + ses->ccmd = ccmd; + ses->keysz = (encini->cri_klen - 63) / 64; + memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); + + pasemi_desc_start(&init_desc, + XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); + pasemi_desc_build(&init_desc, + XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); + } + if (macini) { + if (macini->cri_alg == CRYPTO_MD5_HMAC || + macini->cri_alg == CRYPTO_SHA1_HMAC) + memcpy(ses->hkey, macini->cri_key, blksz); + else { + /* Load initialization constants(RFC 1321, 3174) */ + ses->hiv[0] = 0x67452301efcdab89ULL; + ses->hiv[1] = 0x98badcfe10325476ULL; + ses->hiv[2] = 0xc3d2e1f000000000ULL; + } + ses->hseq = 0ULL; + } + + spin_lock_irqsave(&txring->fill_lock, flags); + + if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - + txring->next_to_clean) > TX_RING_SIZE) { + spin_unlock_irqrestore(&txring->fill_lock, flags); + return ERESTART; + } + + if (encini) { + pasemi_ring_add_desc(txring, &init_desc, NULL); + pasemi_ring_incr(sc, ses->chan, + pasemi_desc_size(&init_desc)); + } + + txring->sesn = sesn; + spin_unlock_irqrestore(&txring->fill_lock, flags); + + *sidp = PASEMI_SID(sesn); + return 0; +} + +/* + * Deallocate a session. + */ +static int +pasemi_freesession(device_t dev, u_int64_t tid) +{ + struct pasemi_softc *sc = device_get_softc(dev); + int session; + u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; + + DPRINTF("%s()\n", __FUNCTION__); + + if (sc == NULL) + return -EINVAL; + session = PASEMI_SESSION(sid); + if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) + return -EINVAL; + + pci_unmap_single(sc->dma_pdev, + sc->sc_sessions[session]->dma_addr, + sizeof(struct pasemi_session), DMA_TO_DEVICE); + memset(sc->sc_sessions[session], 0, + sizeof(struct pasemi_session)); + + return 0; +} + +static int +pasemi_process(device_t dev, struct cryptop *crp, int hint) +{ + + int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; + struct pasemi_softc *sc = device_get_softc(dev); + struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; + caddr_t ivp; + struct pasemi_desc init_desc, work_desc; + struct pasemi_session *ses; + struct sk_buff *skb; + struct uio *uiop; + unsigned long flags; + struct pasemi_fnu_txring *txring; + + DPRINTF("%s()\n", __FUNCTION__); + + if (crp == NULL || crp->crp_callback == NULL || sc == NULL) + return -EINVAL; + + crp->crp_etype = 0; + if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) + return -EINVAL; + + ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; + + crd1 = crp->crp_desc; + if (crd1 == NULL) { + err = -EINVAL; + goto errout; + } + crd2 = crd1->crd_next; + + if (ALG_IS_SIG(crd1->crd_alg)) { + maccrd = crd1; + if (crd2 == NULL) + enccrd = NULL; + else if (ALG_IS_CIPHER(crd2->crd_alg) && + (crd2->crd_flags & CRD_F_ENCRYPT) == 0) + enccrd = crd2; + else + goto erralg; + } else if (ALG_IS_CIPHER(crd1->crd_alg)) { + enccrd = crd1; + if (crd2 == NULL) + maccrd = NULL; + else if (ALG_IS_SIG(crd2->crd_alg) && + (crd1->crd_flags & CRD_F_ENCRYPT)) + maccrd = crd2; + else + goto erralg; + } else + goto erralg; + + chsel = ses->chan; + + txring = &sc->tx[chsel]; + + if (enccrd && !maccrd) { + if (enccrd->crd_alg == CRYPTO_ARC4) + reinit = 1; + reinit_size = 0x40; + srclen = crp->crp_ilen; + + pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I + | XCT_FUN_FUN(chsel)); + if (enccrd->crd_flags & CRD_F_ENCRYPT) + pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); + else + pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); + } else if (enccrd && maccrd) { + if (enccrd->crd_alg == CRYPTO_ARC4) + reinit = 1; + reinit_size = 0x68; + + if (enccrd->crd_flags & CRD_F_ENCRYPT) { + /* Encrypt -> Authenticate */ + pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG + | XCT_FUN_A | XCT_FUN_FUN(chsel)); + srclen = maccrd->crd_skip + maccrd->crd_len; + } else { + /* Authenticate -> Decrypt */ + pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC + | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); + pasemi_desc_build(&work_desc, 0); + pasemi_desc_build(&work_desc, 0); + pasemi_desc_build(&work_desc, 0); + work_desc.postop = PASEMI_CHECK_SIG; + srclen = crp->crp_ilen; + } + + pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); + pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); + } else if (!enccrd && maccrd) { + srclen = maccrd->crd_len; + + pasemi_desc_start(&init_desc, + XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); + pasemi_desc_build(&init_desc, + XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); + + pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG + | XCT_FUN_A | XCT_FUN_FUN(chsel)); + } + + if (enccrd) { + switch (enccrd->crd_alg) { + case CRYPTO_3DES_CBC: + pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | + XCT_FUN_BCM_CBC); + ivsize = sizeof(u64); + break; + case CRYPTO_DES_CBC: + pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | + XCT_FUN_BCM_CBC); + ivsize = sizeof(u64); + break; + case CRYPTO_AES_CBC: + pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | + XCT_FUN_BCM_CBC); + ivsize = 2 * sizeof(u64); + break; + case CRYPTO_ARC4: + pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); + ivsize = 0; + break; + default: + printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", + enccrd->crd_alg); + err = -EINVAL; + goto errout; + } + + ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; + if (enccrd->crd_flags & CRD_F_ENCRYPT) { + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) + memcpy(ivp, enccrd->crd_iv, ivsize); + else + read_random(ivp, ivsize); + /* If IV is not present in the buffer already, it has to be copied there */ + if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) + crypto_copyback(crp->crp_flags, crp->crp_buf, + enccrd->crd_inject, ivsize, ivp); + } else { + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) + /* IV is provided expicitly in descriptor */ + memcpy(ivp, enccrd->crd_iv, ivsize); + else + /* IV is provided in the packet */ + crypto_copydata(crp->crp_flags, crp->crp_buf, + enccrd->crd_inject, ivsize, + ivp); + } + } + + if (maccrd) { + switch (maccrd->crd_alg) { + case CRYPTO_MD5: + pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | + XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); + break; + case CRYPTO_SHA1: + pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | + XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); + break; + case CRYPTO_MD5_HMAC: + pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | + XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); + break; + case CRYPTO_SHA1_HMAC: + pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | + XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); + break; + default: + printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", + maccrd->crd_alg); + err = -EINVAL; + goto errout; + } + } + + if (crp->crp_flags & CRYPTO_F_SKBUF) { + /* using SKB buffers */ + skb = (struct sk_buff *)crp->crp_buf; + if (skb_shinfo(skb)->nr_frags) { + printk(DRV_NAME ": skb frags unimplemented\n"); + err = -EINVAL; + goto errout; + } + pasemi_desc_build( + &work_desc, + XCT_FUN_DST_PTR(skb->len, pci_map_single( + sc->dma_pdev, skb->data, + skb->len, DMA_TO_DEVICE))); + pasemi_desc_build( + &work_desc, + XCT_FUN_SRC_PTR( + srclen, pci_map_single( + sc->dma_pdev, skb->data, + srclen, DMA_TO_DEVICE))); + pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); + } else if (crp->crp_flags & CRYPTO_F_IOV) { + /* using IOV buffers */ + uiop = (struct uio *)crp->crp_buf; + if (uiop->uio_iovcnt > 1) { + printk(DRV_NAME ": iov frags unimplemented\n"); + err = -EINVAL; + goto errout; + } + + /* crp_olen is never set; always use crp_ilen */ + pasemi_desc_build( + &work_desc, + XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( + sc->dma_pdev, + uiop->uio_iov->iov_base, + crp->crp_ilen, DMA_TO_DEVICE))); + pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); + + pasemi_desc_build( + &work_desc, + XCT_FUN_SRC_PTR(srclen, pci_map_single( + sc->dma_pdev, + uiop->uio_iov->iov_base, + srclen, DMA_TO_DEVICE))); + } else { + /* using contig buffers */ + pasemi_desc_build( + &work_desc, + XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( + sc->dma_pdev, + crp->crp_buf, + crp->crp_ilen, DMA_TO_DEVICE))); + pasemi_desc_build( + &work_desc, + XCT_FUN_SRC_PTR(srclen, pci_map_single( + sc->dma_pdev, + crp->crp_buf, srclen, + DMA_TO_DEVICE))); + pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); + } + + spin_lock_irqsave(&txring->fill_lock, flags); + + if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { + txring->sesn = PASEMI_SESSION(crp->crp_sid); + reinit = 1; + } + + if (enccrd) { + pasemi_desc_start(&init_desc, + XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); + pasemi_desc_build(&init_desc, + XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); + } + + if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + + pasemi_desc_size(&work_desc)) - + txring->next_to_clean) > TX_RING_SIZE) { + spin_unlock_irqrestore(&txring->fill_lock, flags); + err = ERESTART; + goto errout; + } + + pasemi_ring_add_desc(txring, &init_desc, NULL); + pasemi_ring_add_desc(txring, &work_desc, crp); + + pasemi_ring_incr(sc, chsel, + pasemi_desc_size(&init_desc) + + pasemi_desc_size(&work_desc)); + + spin_unlock_irqrestore(&txring->fill_lock, flags); + + mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); + + return 0; + +erralg: + printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", + crd1->crd_alg, crd2->crd_alg); + err = -EINVAL; + +errout: + if (err != ERESTART) { + crp->crp_etype = err; + crypto_done(crp); + } + return err; +} + +static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) +{ + int i, j, ring_idx; + struct pasemi_fnu_txring *ring = &sc->tx[chan]; + u16 delta_cnt; + int flags, loops = 10; + int desc_size; + struct cryptop *crp; + + spin_lock_irqsave(&ring->clean_lock, flags); + + while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] + & PAS_STATUS_PCNT_M) - ring->total_pktcnt) + && loops--) { + + for (i = 0; i < delta_cnt; i++) { + desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; + crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; + if (crp) { + ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); + if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { + /* Need to make sure signature matched, + * if not - return error */ + if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) + crp->crp_etype = -EINVAL; + } + crypto_done(TX_DESC_INFO(ring, + ring->next_to_clean).cf_crp); + TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; + pci_unmap_single( + sc->dma_pdev, + XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), + PCI_DMA_TODEVICE); + + ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; + + ring->next_to_clean++; + for (j = 1; j < desc_size; j++) { + ring_idx = 2 * + (ring->next_to_clean & + (TX_RING_SIZE-1)); + pci_unmap_single( + sc->dma_pdev, + XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), + PCI_DMA_TODEVICE); + if (ring->desc[ring_idx + 1]) + pci_unmap_single( + sc->dma_pdev, + XCT_PTR_ADDR_LEN( + ring->desc[ + ring_idx + 1]), + PCI_DMA_TODEVICE); + ring->desc[ring_idx] = + ring->desc[ring_idx + 1] = 0; + ring->next_to_clean++; + } + } else { + for (j = 0; j < desc_size; j++) { + ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); + ring->desc[ring_idx] = + ring->desc[ring_idx + 1] = 0; + ring->next_to_clean++; + } + } + } + + ring->total_pktcnt += delta_cnt; + } + spin_unlock_irqrestore(&ring->clean_lock, flags); + + return 0; +} + +static void sweepup_tx(struct pasemi_softc *sc) +{ + int i; + + for (i = 0; i < sc->sc_num_channels; i++) + pasemi_clean_tx(sc, i); +} + +static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) +{ + struct pasemi_softc *sc = arg; + unsigned int reg; + int chan = irq - sc->base_irq; + int chan_index = sc->base_chan + chan; + u64 stat = dma_status->tx_sta[chan_index]; + + DPRINTF("%s()\n", __FUNCTION__); + + if (!(stat & PAS_STATUS_CAUSE_M)) + return IRQ_NONE; + + pasemi_clean_tx(sc, chan); + + stat = dma_status->tx_sta[chan_index]; + + reg = PAS_IOB_DMA_TXCH_RESET_PINTC | + PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); + + if (stat & PAS_STATUS_SOFT) + reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; + + out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); + + + return IRQ_HANDLED; +} + +static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) +{ + u32 val; + int chan_index = chan + sc->base_chan; + int ret; + struct pasemi_fnu_txring *ring; + + ring = &sc->tx[chan]; + + spin_lock_init(&ring->fill_lock); + spin_lock_init(&ring->clean_lock); + + ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * + TX_RING_SIZE, GFP_KERNEL); + if (!ring->desc_info) + return -ENOMEM; + + /* Allocate descriptors */ + ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, + TX_RING_SIZE * + 2 * sizeof(u64), + &ring->dma, GFP_KERNEL); + if (!ring->desc) + return -ENOMEM; + + memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); + + out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); + + ring->total_pktcnt = 0; + + out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), + PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); + + val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); + val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); + + out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); + + out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), + PAS_DMA_TXCHAN_CFG_TY_FUNC | + PAS_DMA_TXCHAN_CFG_TATTR(chan) | + PAS_DMA_TXCHAN_CFG_WT(2)); + + /* enable tx channel */ + out_le32(sc->dma_regs + + PAS_DMA_TXCHAN_TCMDSTA(chan_index), + PAS_DMA_TXCHAN_TCMDSTA_EN); + + out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), + PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); + + ring->next_to_fill = 0; + ring->next_to_clean = 0; + + snprintf(ring->irq_name, sizeof(ring->irq_name), + "%s%d", "crypto", chan); + + ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); + ret = request_irq(ring->irq, (irq_handler_t) + pasemi_intr, 0, ring->irq_name, sc); + if (ret) { + printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", + ring->irq, ret); + ring->irq = -1; + return ret; + } + + setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); + + return 0; +} + +static device_method_t pasemi_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, pasemi_newsession), + DEVMETHOD(cryptodev_freesession, pasemi_freesession), + DEVMETHOD(cryptodev_process, pasemi_process), +}; + +/* Set up the crypto device structure, private data, + * and anything else we need before we start */ + +static int +pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + struct pasemi_softc *sc; + int ret, i; + + DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); + + sc = kzalloc(sizeof(*sc), GFP_KERNEL); + if (!sc) + return -ENOMEM; + + softc_device_init(sc, DRV_NAME, 1, pasemi_methods); + + pci_set_drvdata(pdev, sc); + + spin_lock_init(&sc->sc_chnlock); + + sc->sc_sessions = (struct pasemi_session **) + kzalloc(PASEMI_INITIAL_SESSIONS * + sizeof(struct pasemi_session *), GFP_ATOMIC); + if (sc->sc_sessions == NULL) { + ret = -ENOMEM; + goto out; + } + + sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; + sc->sc_lastchn = 0; + sc->base_irq = pdev->irq + 6; + sc->base_chan = 6; + sc->sc_cid = -1; + sc->dma_pdev = pdev; + + sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); + if (!sc->iob_pdev) { + dev_err(&pdev->dev, "Can't find I/O Bridge\n"); + ret = -ENODEV; + goto out; + } + + /* This is hardcoded and ugly, but we have some firmware versions + * who don't provide the register space in the device tree. Luckily + * they are at well-known locations so we can just do the math here. + */ + sc->dma_regs = + ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); + sc->iob_regs = + ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); + if (!sc->dma_regs || !sc->iob_regs) { + dev_err(&pdev->dev, "Can't map registers\n"); + ret = -ENODEV; + goto out; + } + + dma_status = __ioremap(0xfd800000, 0x1000, 0); + if (!dma_status) { + ret = -ENODEV; + dev_err(&pdev->dev, "Can't map dmastatus space\n"); + goto out; + } + + sc->tx = (struct pasemi_fnu_txring *) + kzalloc(sizeof(struct pasemi_fnu_txring) + * 8, GFP_KERNEL); + if (!sc->tx) { + ret = -ENOMEM; + goto out; + } + + /* Initialize the h/w */ + out_le32(sc->dma_regs + PAS_DMA_COM_CFG, + (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | + PAS_DMA_COM_CFG_FWF)); + out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); + + for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { + sc->sc_num_channels++; + ret = pasemi_dma_setup_tx_resources(sc, i); + if (ret) + goto out; + } + + sc->sc_cid = crypto_get_driverid(softc_get_device(sc), + CRYPTOCAP_F_HARDWARE); + if (sc->sc_cid < 0) { + printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); + ret = -ENXIO; + goto out; + } + + /* register algorithms with the framework */ + printk(DRV_NAME ":"); + + crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); + + return 0; + +out: + pasemi_dma_remove(pdev); + return ret; +} + +#define MAX_RETRIES 5000 + +static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) +{ + struct pasemi_fnu_txring *ring = &sc->tx[chan]; + int chan_index = chan + sc->base_chan; + int retries; + u32 stat; + + /* Stop the channel */ + out_le32(sc->dma_regs + + PAS_DMA_TXCHAN_TCMDSTA(chan_index), + PAS_DMA_TXCHAN_TCMDSTA_ST); + + for (retries = 0; retries < MAX_RETRIES; retries++) { + stat = in_le32(sc->dma_regs + + PAS_DMA_TXCHAN_TCMDSTA(chan_index)); + if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) + break; + cond_resched(); + } + + if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) + dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", + chan_index); + + /* Disable the channel */ + out_le32(sc->dma_regs + + PAS_DMA_TXCHAN_TCMDSTA(chan_index), + 0); + + if (ring->desc_info) + kfree((void *) ring->desc_info); + if (ring->desc) + dma_free_coherent(&sc->dma_pdev->dev, + TX_RING_SIZE * + 2 * sizeof(u64), + (void *) ring->desc, ring->dma); + if (ring->irq != -1) + free_irq(ring->irq, sc); + + del_timer(&ring->crypto_timer); +} + +static void pasemi_dma_remove(struct pci_dev *pdev) +{ + struct pasemi_softc *sc = pci_get_drvdata(pdev); + int i; + + DPRINTF("%s()\n", __FUNCTION__); + + if (sc->sc_cid >= 0) { + crypto_unregister_all(sc->sc_cid); + } + + if (sc->tx) { + for (i = 0; i < sc->sc_num_channels; i++) + pasemi_free_tx_resources(sc, i); + + kfree(sc->tx); + } + if (sc->sc_sessions) { + for (i = 0; i < sc->sc_nsessions; i++) + kfree(sc->sc_sessions[i]); + kfree(sc->sc_sessions); + } + if (sc->iob_pdev) + pci_dev_put(sc->iob_pdev); + if (sc->dma_regs) + iounmap(sc->dma_regs); + if (sc->iob_regs) + iounmap(sc->iob_regs); + kfree(sc); +} + +static struct pci_device_id pasemi_dma_pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, +}; + +MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); + +static struct pci_driver pasemi_dma_driver = { + .name = "pasemi_dma", + .id_table = pasemi_dma_pci_tbl, + .probe = pasemi_dma_probe, + .remove = pasemi_dma_remove, +}; + +static void __exit pasemi_dma_cleanup_module(void) +{ + pci_unregister_driver(&pasemi_dma_driver); + __iounmap(dma_status); + dma_status = NULL; +} + +int pasemi_dma_init_module(void) +{ + return pci_register_driver(&pasemi_dma_driver); +} + +module_init(pasemi_dma_init_module); +module_exit(pasemi_dma_cleanup_module); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); +MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); diff --git a/target/linux/generic/files/crypto/ocf/pasemi/pasemi_fnu.h b/target/linux/generic/files/crypto/ocf/pasemi/pasemi_fnu.h new file mode 100644 index 0000000..1a0dcc8 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/pasemi/pasemi_fnu.h @@ -0,0 +1,410 @@ +/* + * Copyright (C) 2007 PA Semi, Inc + * + * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and + * hardware register layouts. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef PASEMI_FNU_H +#define PASEMI_FNU_H + +#include + +#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) +#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) +#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } + +/* Must be a power of two */ +#define RX_RING_SIZE 512 +#define TX_RING_SIZE 512 +#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) +#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) +#define MAX_DESC_SIZE 8 +#define PASEMI_INITIAL_SESSIONS 10 +#define PASEMI_FNU_CHANNELS 8 + +/* DMA descriptor */ +struct pasemi_desc { + u64 quad[2*MAX_DESC_SIZE]; + int quad_cnt; + int size; + int postop; +}; + +/* + * Holds per descriptor data + */ +struct pasemi_desc_info { + int desc_size; + int desc_postop; +#define PASEMI_CHECK_SIG 0x1 + + struct cryptop *cf_crp; +}; + +/* + * Holds per channel data + */ +struct pasemi_fnu_txring { + volatile u64 *desc; + volatile struct + pasemi_desc_info *desc_info; + dma_addr_t dma; + struct timer_list crypto_timer; + spinlock_t fill_lock; + spinlock_t clean_lock; + unsigned int next_to_fill; + unsigned int next_to_clean; + u16 total_pktcnt; + int irq; + int sesn; + char irq_name[10]; +}; + +/* + * Holds data specific to a single pasemi device. + */ +struct pasemi_softc { + softc_device_decl sc_cdev; + struct pci_dev *dma_pdev; /* device backpointer */ + struct pci_dev *iob_pdev; /* device backpointer */ + void __iomem *dma_regs; + void __iomem *iob_regs; + int base_irq; + int base_chan; + int32_t sc_cid; /* crypto tag */ + int sc_nsessions; + struct pasemi_session **sc_sessions; + int sc_num_channels;/* number of crypto channels */ + + /* pointer to the array of txring datastructures, one txring per channel */ + struct pasemi_fnu_txring *tx; + + /* + * mutual exclusion for the channel scheduler + */ + spinlock_t sc_chnlock; + /* last channel used, for now use round-robin to allocate channels */ + int sc_lastchn; +}; + +struct pasemi_session { + u64 civ[2]; + u64 keysz; + u64 key[4]; + u64 ccmd; + u64 hkey[4]; + u64 hseq; + u64 giv[2]; + u64 hiv[4]; + + int used; + dma_addr_t dma_addr; + int chan; +}; + +/* status register layout in IOB region, at 0xfd800000 */ +struct pasdma_status { + u64 rx_sta[64]; + u64 tx_sta[20]; +}; + +#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ + (alg == CRYPTO_3DES_CBC) || \ + (alg == CRYPTO_AES_CBC) || \ + (alg == CRYPTO_ARC4) || \ + (alg == CRYPTO_NULL_CBC)) + +#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ + (alg == CRYPTO_MD5_HMAC) || \ + (alg == CRYPTO_SHA1) || \ + (alg == CRYPTO_SHA1_HMAC) || \ + (alg == CRYPTO_NULL_HMAC)) + +enum { + PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ + PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ + PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ + PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ + PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ +}; + +/* All these registers live in the PCI configuration space for the DMA PCI + * device. Use the normal PCI config access functions for them. + */ + +#define PAS_DMA_COM_CFG_FWF 0x18000000 + +#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ +#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ +#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ +#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ + +#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ +#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ +#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ +#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ +#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ +#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ +#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ +#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ +#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) +#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ +#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ +#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ +#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) +#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ +#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ +#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c +#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 +#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ + PAS_DMA_TXCHAN_CFG_TATTR_M) +#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 +#define PAS_DMA_TXCHAN_CFG_WT_S 6 +#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ + PAS_DMA_TXCHAN_CFG_WT_M) +#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 +#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 +#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ +#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ +#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ +#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) +#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) +#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 +#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 +#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ + PAS_DMA_TXCHAN_BASEL_BRBL_M) +#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) +#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff +#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 +#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ + PAS_DMA_TXCHAN_BASEU_BRBH_M) +/* # of cache lines worth of buffer ring */ +#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 +#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ +#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ + PAS_DMA_TXCHAN_BASEU_SIZ_M) + +#define PAS_STATUS_PCNT_M 0x000000000000ffffull +#define PAS_STATUS_PCNT_S 0 +#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull +#define PAS_STATUS_DCNT_S 16 +#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull +#define PAS_STATUS_BPCNT_S 32 +#define PAS_STATUS_CAUSE_M 0xf000000000000000ull +#define PAS_STATUS_TIMER 0x1000000000000000ull +#define PAS_STATUS_ERROR 0x2000000000000000ull +#define PAS_STATUS_SOFT 0x4000000000000000ull +#define PAS_STATUS_INT 0x8000000000000000ull + +#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) +#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff +#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 +#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ + PAS_IOB_DMA_RXCH_CFG_CNTTH_M) +#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) +#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff +#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 +#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ + PAS_IOB_DMA_TXCH_CFG_CNTTH_M) +#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) +#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 +#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff +#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 +#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ + PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) +#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) +#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 +#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff +#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 +#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ + PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) +#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) +#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 +#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 +#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ + PAS_IOB_DMA_RXCH_RESET_PCNT_M) +#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 +#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 +#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 +#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 +#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 +#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 +#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) +#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 +#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 +#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ + PAS_IOB_DMA_TXCH_RESET_PCNT_M) +#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 +#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 +#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 +#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 +#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 +#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 + +#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 +#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff +#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 +#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ + PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) + +/* Transmit descriptor fields */ +#define XCT_MACTX_T 0x8000000000000000ull +#define XCT_MACTX_ST 0x4000000000000000ull +#define XCT_MACTX_NORES 0x0000000000000000ull +#define XCT_MACTX_8BRES 0x1000000000000000ull +#define XCT_MACTX_24BRES 0x2000000000000000ull +#define XCT_MACTX_40BRES 0x3000000000000000ull +#define XCT_MACTX_I 0x0800000000000000ull +#define XCT_MACTX_O 0x0400000000000000ull +#define XCT_MACTX_E 0x0200000000000000ull +#define XCT_MACTX_VLAN_M 0x0180000000000000ull +#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull +#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull +#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull +#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull +#define XCT_MACTX_CRC_M 0x0060000000000000ull +#define XCT_MACTX_CRC_NOP 0x0000000000000000ull +#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull +#define XCT_MACTX_CRC_PAD 0x0040000000000000ull +#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull +#define XCT_MACTX_SS 0x0010000000000000ull +#define XCT_MACTX_LLEN_M 0x00007fff00000000ull +#define XCT_MACTX_LLEN_S 32ull +#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ + XCT_MACTX_LLEN_M) +#define XCT_MACTX_IPH_M 0x00000000f8000000ull +#define XCT_MACTX_IPH_S 27ull +#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ + XCT_MACTX_IPH_M) +#define XCT_MACTX_IPO_M 0x0000000007c00000ull +#define XCT_MACTX_IPO_S 22ull +#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ + XCT_MACTX_IPO_M) +#define XCT_MACTX_CSUM_M 0x0000000000000060ull +#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull +#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull +#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull +#define XCT_MACTX_V6 0x0000000000000010ull +#define XCT_MACTX_C 0x0000000000000004ull +#define XCT_MACTX_AL2 0x0000000000000002ull + +#define XCT_PTR_T 0x8000000000000000ull +#define XCT_PTR_LEN_M 0x7ffff00000000000ull +#define XCT_PTR_LEN_S 44 +#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ + XCT_PTR_LEN_M) +#define XCT_PTR_ADDR_M 0x00000fffffffffffull +#define XCT_PTR_ADDR_S 0 +#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ + XCT_PTR_ADDR_M) + +/* Function descriptor fields */ +#define XCT_FUN_T 0x8000000000000000ull +#define XCT_FUN_ST 0x4000000000000000ull +#define XCT_FUN_NORES 0x0000000000000000ull +#define XCT_FUN_8BRES 0x1000000000000000ull +#define XCT_FUN_24BRES 0x2000000000000000ull +#define XCT_FUN_40BRES 0x3000000000000000ull +#define XCT_FUN_I 0x0800000000000000ull +#define XCT_FUN_O 0x0400000000000000ull +#define XCT_FUN_E 0x0200000000000000ull +#define XCT_FUN_FUN_S 54 +#define XCT_FUN_FUN_M 0x01c0000000000000ull +#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ + XCT_FUN_FUN_M) +#define XCT_FUN_CRM_NOP 0x0000000000000000ull +#define XCT_FUN_CRM_SIG 0x0008000000000000ull +#define XCT_FUN_CRM_ENC 0x0010000000000000ull +#define XCT_FUN_CRM_DEC 0x0018000000000000ull +#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull +#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull +#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull +#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull +#define XCT_FUN_LLEN_M 0x0007ffff00000000ull +#define XCT_FUN_LLEN_S 32ULL +#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ + XCT_FUN_LLEN_M) +#define XCT_FUN_SHL_M 0x00000000f8000000ull +#define XCT_FUN_SHL_S 27ull +#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ + XCT_FUN_SHL_M) +#define XCT_FUN_CHL_M 0x0000000007c00000ull +#define XCT_FUN_CHL_S 22ull +#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ + XCT_FUN_CHL_M) +#define XCT_FUN_HSZ_M 0x00000000003c0000ull +#define XCT_FUN_HSZ_S 18ull +#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ + XCT_FUN_HSZ_M) +#define XCT_FUN_ALG_DES 0x0000000000000000ull +#define XCT_FUN_ALG_3DES 0x0000000000008000ull +#define XCT_FUN_ALG_AES 0x0000000000010000ull +#define XCT_FUN_ALG_ARC 0x0000000000018000ull +#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull +#define XCT_FUN_BCM_ECB 0x0000000000000000ull +#define XCT_FUN_BCM_CBC 0x0000000000001000ull +#define XCT_FUN_BCM_CFB 0x0000000000002000ull +#define XCT_FUN_BCM_OFB 0x0000000000003000ull +#define XCT_FUN_BCM_CNT 0x0000000000003800ull +#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull +#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull +#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull +#define XCT_FUN_BCP_ZRO 0x0000000000000200ull +#define XCT_FUN_BCP_PL 0x0000000000000400ull +#define XCT_FUN_BCP_INCR 0x0000000000000600ull +#define XCT_FUN_SIG_MD5 (0ull << 4) +#define XCT_FUN_SIG_SHA1 (2ull << 4) +#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) +#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) +#define XCT_FUN_A 0x0000000000000008ull +#define XCT_FUN_C 0x0000000000000004ull +#define XCT_FUN_AL2 0x0000000000000002ull +#define XCT_FUN_SE 0x0000000000000001ull + +#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) +#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ + 0x8000000000000000ull) + +#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull +#define XCT_CTRL_HDR_FUN_NUM_S 54 +#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull +#define XCT_CTRL_HDR_LEN_S 32 +#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull +#define XCT_CTRL_HDR_REG_S 0 + +#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ + ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ + & XCT_CTRL_HDR_FUN_NUM_M) | \ + ((((long)(len)) << \ + XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ + ((((long)(reg)) << \ + XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) + +/* Function config command options */ +#define DMA_CALGO_DES 0x00 +#define DMA_CALGO_3DES 0x01 +#define DMA_CALGO_AES 0x02 +#define DMA_CALGO_ARC 0x03 + +#define DMA_FN_CIV0 0x02 +#define DMA_FN_CIV1 0x03 +#define DMA_FN_HKEY0 0x0a + +#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ + (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) + +#endif /* PASEMI_FNU_H */ diff --git a/target/linux/generic/files/crypto/ocf/random.c b/target/linux/generic/files/crypto/ocf/random.c new file mode 100644 index 0000000..9fc070e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/random.c @@ -0,0 +1,317 @@ +/* + * A system independant way of adding entropy to the kernels pool + * this way the drivers can focus on the real work and we can take + * care of pushing it to the appropriate place in the kernel. + * + * This should be fast and callable from timers/interrupts + * + * Written by David McCullough + * Copyright (C) 2006-2010 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * ALTERNATIVELY, provided that this notice is retained in full, this product + * may be distributed under the terms of the GNU General Public License (GPL), + * in which case the provisions of the GPL apply INSTEAD OF those given above. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_OCF_FIPS +#include "rndtest.h" +#endif + +#ifndef HAS_RANDOM_INPUT_WAIT +#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" +#endif + +/* + * a hack to access the debug levels from the crypto driver + */ +extern int crypto_debug; +#define debug crypto_debug + +/* + * a list of all registered random providers + */ +static LIST_HEAD(random_ops); +static int started = 0; +static int initted = 0; + +struct random_op { + struct list_head random_list; + u_int32_t driverid; + int (*read_random)(void *arg, u_int32_t *buf, int len); + void *arg; +}; + +static struct task_struct *random_thread; +static int random_proc(void *arg); + +static spinlock_t random_lock; + +/* + * just init the spin locks + */ +static int +crypto_random_init(void) +{ + spin_lock_init(&random_lock); + initted = 1; + return(0); +} + +/* + * Add the given random reader to our list (if not present) + * and start the thread (if not already started) + * + * we have to assume that driver id is ok for now + */ +int +crypto_rregister( + u_int32_t driverid, + int (*read_random)(void *arg, u_int32_t *buf, int len), + void *arg) +{ + unsigned long flags; + int ret = 0; + struct random_op *rops, *tmp; + + dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, + __FUNCTION__, driverid, read_random, arg); + + if (!initted) + crypto_random_init(); + +#if 0 + struct cryptocap *cap; + + cap = crypto_checkdriver(driverid); + if (!cap) + return EINVAL; +#endif + + list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { + if (rops->driverid == driverid && rops->read_random == read_random) + return EEXIST; + } + + rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); + if (!rops) + return ENOMEM; + + rops->driverid = driverid; + rops->read_random = read_random; + rops->arg = arg; + + spin_lock_irqsave(&random_lock, flags); + list_add_tail(&rops->random_list, &random_ops); + if (!started) { + random_thread = kthread_run(random_proc, NULL, "ocf-random"); + if (IS_ERR(random_thread)) + ret = PTR_ERR(random_thread); + else + started = 1; + } + spin_unlock_irqrestore(&random_lock, flags); + + return ret; +} +EXPORT_SYMBOL(crypto_rregister); + +int +crypto_runregister_all(u_int32_t driverid) +{ + struct random_op *rops, *tmp; + unsigned long flags; + + dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); + + list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { + if (rops->driverid == driverid) { + list_del(&rops->random_list); + kfree(rops); + } + } + + spin_lock_irqsave(&random_lock, flags); + if (list_empty(&random_ops) && started) + kthread_stop(random_thread); + spin_unlock_irqrestore(&random_lock, flags); + return(0); +} +EXPORT_SYMBOL(crypto_runregister_all); + +/* + * while we can add entropy to random.c continue to read random data from + * the drivers and push it to random. + */ +static int +random_proc(void *arg) +{ + int n; + int wantcnt; + int bufcnt = 0; + int retval = 0; + int *buf = NULL; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + daemonize(); + spin_lock_irq(¤t->sigmask_lock); + sigemptyset(¤t->blocked); + recalc_sigpending(current); + spin_unlock_irq(¤t->sigmask_lock); + sprintf(current->comm, "ocf-random"); +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0) + recalc_sigpending(); + sprintf(current->comm, "ocf-random"); +#else + daemonize("ocf-random"); +#endif + + (void) get_fs(); + set_fs(get_ds()); + +#ifdef CONFIG_OCF_FIPS +#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) +#else +#define NUM_INT 32 +#endif + + /* + * some devices can transferr their RNG data direct into memory, + * so make sure it is device friendly + */ + buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); + if (NULL == buf) { + printk("crypto: RNG could not allocate memory\n"); + retval = -ENOMEM; + goto bad_alloc; + } + + wantcnt = NUM_INT; /* start by adding some entropy */ + + /* + * its possible due to errors or driver removal that we no longer + * have anything to do, if so exit or we will consume all the CPU + * doing nothing + */ + while (!list_empty(&random_ops)) { + struct random_op *rops, *tmp; + +#ifdef CONFIG_OCF_FIPS + if (wantcnt) + wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ +#endif + + /* see if we can get enough entropy to make the world + * a better place. + */ + while (bufcnt < wantcnt && bufcnt < NUM_INT) { + list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { + + n = (*rops->read_random)(rops->arg, &buf[bufcnt], + NUM_INT - bufcnt); + + /* on failure remove the random number generator */ + if (n == -1) { + list_del(&rops->random_list); + printk("crypto: RNG (driverid=0x%x) failed, disabling\n", + rops->driverid); + kfree(rops); + } else if (n > 0) + bufcnt += n; + } + /* give up CPU for a bit, just in case as this is a loop */ + schedule(); + } + + +#ifdef CONFIG_OCF_FIPS + if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { + dprintk("crypto: buffer had fips errors, discarding\n"); + bufcnt = 0; + } +#endif + + /* + * if we have a certified buffer, we can send some data + * to /dev/random and move along + */ + if (bufcnt > 0) { + /* add what we have */ + random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); + bufcnt = 0; + } + + /* give up CPU for a bit so we don't hog while filling */ + schedule(); + + /* wait for needing more */ + wantcnt = random_input_wait(); + + if (wantcnt <= 0) + wantcnt = 0; /* try to get some info again */ + else + /* round up to one word or we can loop forever */ + wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); + if (wantcnt > NUM_INT) { + wantcnt = NUM_INT; + } + + if (signal_pending(current)) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + spin_lock_irq(¤t->sigmask_lock); +#endif + flush_signals(current); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + spin_unlock_irq(¤t->sigmask_lock); +#endif + } + } + + kfree(buf); + +bad_alloc: + spin_lock_irq(&random_lock); + started = 0; + spin_unlock_irq(&random_lock); + + return retval; +} + diff --git a/target/linux/generic/files/crypto/ocf/rndtest.c b/target/linux/generic/files/crypto/ocf/rndtest.c new file mode 100644 index 0000000..7bed6a1 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/rndtest.c @@ -0,0 +1,300 @@ +/* $OpenBSD$ */ + +/* + * OCF/Linux port done by David McCullough + * Copyright (C) 2006-2010 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * The license and original author are listed below. + * + * Copyright (c) 2002 Jason L. Wright (jason@thought.net) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jason L. Wright + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rndtest.h" + +static struct rndtest_stats rndstats; + +static void rndtest_test(struct rndtest_state *); + +/* The tests themselves */ +static int rndtest_monobit(struct rndtest_state *); +static int rndtest_runs(struct rndtest_state *); +static int rndtest_longruns(struct rndtest_state *); +static int rndtest_chi_4(struct rndtest_state *); + +static int rndtest_runs_check(struct rndtest_state *, int, int *); +static void rndtest_runs_record(struct rndtest_state *, int, int *); + +static const struct rndtest_testfunc { + int (*test)(struct rndtest_state *); +} rndtest_funcs[] = { + { rndtest_monobit }, + { rndtest_runs }, + { rndtest_chi_4 }, + { rndtest_longruns }, +}; + +#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) + +static void +rndtest_test(struct rndtest_state *rsp) +{ + int i, rv = 0; + + rndstats.rst_tests++; + for (i = 0; i < RNDTEST_NTESTS; i++) + rv |= (*rndtest_funcs[i].test)(rsp); + rsp->rs_discard = (rv != 0); +} + + +extern int crypto_debug; +#define rndtest_verbose 2 +#define rndtest_report(rsp, failure, fmt, a...) \ + { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } + +#define RNDTEST_MONOBIT_MINONES 9725 +#define RNDTEST_MONOBIT_MAXONES 10275 + +static int +rndtest_monobit(struct rndtest_state *rsp) +{ + int i, ones = 0, j; + u_int8_t r; + + for (i = 0; i < RNDTEST_NBYTES; i++) { + r = rsp->rs_buf[i]; + for (j = 0; j < 8; j++, r <<= 1) + if (r & 0x80) + ones++; + } + if (ones > RNDTEST_MONOBIT_MINONES && + ones < RNDTEST_MONOBIT_MAXONES) { + if (rndtest_verbose > 1) + rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", + RNDTEST_MONOBIT_MINONES, ones, + RNDTEST_MONOBIT_MAXONES); + return (0); + } else { + if (rndtest_verbose) + rndtest_report(rsp, 1, + "monobit failed (%d ones)", ones); + rndstats.rst_monobit++; + return (-1); + } +} + +#define RNDTEST_RUNS_NINTERVAL 6 + +static const struct rndtest_runs_tabs { + u_int16_t min, max; +} rndtest_runs_tab[] = { + { 2343, 2657 }, + { 1135, 1365 }, + { 542, 708 }, + { 251, 373 }, + { 111, 201 }, + { 111, 201 }, +}; + +static int +rndtest_runs(struct rndtest_state *rsp) +{ + int i, j, ones, zeros, rv = 0; + int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; + u_int8_t c; + + bzero(onei, sizeof(onei)); + bzero(zeroi, sizeof(zeroi)); + ones = zeros = 0; + for (i = 0; i < RNDTEST_NBYTES; i++) { + c = rsp->rs_buf[i]; + for (j = 0; j < 8; j++, c <<= 1) { + if (c & 0x80) { + ones++; + rndtest_runs_record(rsp, zeros, zeroi); + zeros = 0; + } else { + zeros++; + rndtest_runs_record(rsp, ones, onei); + ones = 0; + } + } + } + rndtest_runs_record(rsp, ones, onei); + rndtest_runs_record(rsp, zeros, zeroi); + + rv |= rndtest_runs_check(rsp, 0, zeroi); + rv |= rndtest_runs_check(rsp, 1, onei); + + if (rv) + rndstats.rst_runs++; + + return (rv); +} + +static void +rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) +{ + if (len == 0) + return; + if (len > RNDTEST_RUNS_NINTERVAL) + len = RNDTEST_RUNS_NINTERVAL; + len -= 1; + intrv[len]++; +} + +static int +rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) +{ + int i, rv = 0; + + for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { + if (src[i] < rndtest_runs_tab[i].min || + src[i] > rndtest_runs_tab[i].max) { + rndtest_report(rsp, 1, + "%s interval %d failed (%d, %d-%d)", + val ? "ones" : "zeros", + i + 1, src[i], rndtest_runs_tab[i].min, + rndtest_runs_tab[i].max); + rv = -1; + } else { + rndtest_report(rsp, 0, + "runs pass %s interval %d (%d < %d < %d)", + val ? "ones" : "zeros", + i + 1, rndtest_runs_tab[i].min, src[i], + rndtest_runs_tab[i].max); + } + } + return (rv); +} + +static int +rndtest_longruns(struct rndtest_state *rsp) +{ + int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; + u_int8_t c; + + for (i = 0; i < RNDTEST_NBYTES; i++) { + c = rsp->rs_buf[i]; + for (j = 0; j < 8; j++, c <<= 1) { + if (c & 0x80) { + zeros = 0; + ones++; + if (ones > maxones) + maxones = ones; + } else { + ones = 0; + zeros++; + if (zeros > maxzeros) + maxzeros = zeros; + } + } + } + + if (maxones < 26 && maxzeros < 26) { + rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", + maxones, maxzeros); + return (0); + } else { + rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", + maxones, maxzeros); + rndstats.rst_longruns++; + return (-1); + } +} + +/* + * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, + * but it is really the chi^2 test over 4 bits (the poker test as described + * by Knuth vol 2 is something different, and I take him as authoritative + * on nomenclature over NIST). + */ +#define RNDTEST_CHI4_K 16 +#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) + +/* + * The unnormalized values are used so that we don't have to worry about + * fractional precision. The "real" value is found by: + * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) + */ +#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ +#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ + +static int +rndtest_chi_4(struct rndtest_state *rsp) +{ + unsigned int freq[RNDTEST_CHI4_K], i, sum; + + for (i = 0; i < RNDTEST_CHI4_K; i++) + freq[i] = 0; + + /* Get number of occurances of each 4 bit pattern */ + for (i = 0; i < RNDTEST_NBYTES; i++) { + freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; + freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; + } + + for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) + sum += freq[i] * freq[i]; + + if (sum >= 1563181 && sum <= 1576929) { + rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); + return (0); + } else { + rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); + rndstats.rst_chi++; + return (-1); + } +} + +int +rndtest_buf(unsigned char *buf) +{ + struct rndtest_state rsp; + + memset(&rsp, 0, sizeof(rsp)); + rsp.rs_buf = buf; + rndtest_test(&rsp); + return(rsp.rs_discard); +} + diff --git a/target/linux/generic/files/crypto/ocf/rndtest.h b/target/linux/generic/files/crypto/ocf/rndtest.h new file mode 100644 index 0000000..e9d8ec8 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/rndtest.h @@ -0,0 +1,54 @@ +/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ +/* $OpenBSD$ */ + +/* + * Copyright (c) 2002 Jason L. Wright (jason@thought.net) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Jason L. Wright + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +/* Some of the tests depend on these values */ +#define RNDTEST_NBYTES 2500 +#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) + +struct rndtest_state { + int rs_discard; /* discard/accept random data */ + u_int8_t *rs_buf; +}; + +struct rndtest_stats { + u_int32_t rst_discard; /* number of bytes discarded */ + u_int32_t rst_tests; /* number of test runs */ + u_int32_t rst_monobit; /* monobit test failures */ + u_int32_t rst_runs; /* 0/1 runs failures */ + u_int32_t rst_longruns; /* longruns failures */ + u_int32_t rst_chi; /* chi^2 failures */ +}; + +extern int rndtest_buf(unsigned char *buf); diff --git a/target/linux/generic/files/crypto/ocf/safe/Makefile b/target/linux/generic/files/crypto/ocf/safe/Makefile new file mode 100644 index 0000000..9a36b08 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/Makefile @@ -0,0 +1,12 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_SAFE) += safe.o + +obj ?= . +EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/safe/hmachack.h b/target/linux/generic/files/crypto/ocf/safe/hmachack.h new file mode 100644 index 0000000..598c958 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/hmachack.h @@ -0,0 +1,37 @@ +/* + * until we find a cleaner way, include the BSD md5/sha1 code + * here + */ +#ifdef HMAC_HACK +#define LITTLE_ENDIAN 1234 +#define BIG_ENDIAN 4321 +#ifdef __LITTLE_ENDIAN +#define BYTE_ORDER LITTLE_ENDIAN +#endif +#ifdef __BIG_ENDIAN +#define BYTE_ORDER BIG_ENDIAN +#endif + +u_int8_t hmac_ipad_buffer[64] = { + 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, + 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 +}; + +u_int8_t hmac_opad_buffer[64] = { + 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, + 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, + 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, + 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, + 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, + 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, + 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, + 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C +}; +#endif /* HMAC_HACK */ + diff --git a/target/linux/generic/files/crypto/ocf/safe/md5.c b/target/linux/generic/files/crypto/ocf/safe/md5.c new file mode 100644 index 0000000..077c42e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/md5.c @@ -0,0 +1,308 @@ +/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ +/* + * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if 0 +#include +__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); + +#include +#include +#include +#include +#include +#endif + +#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) + +#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) +#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) +#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) +#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) + +#define ROUND1(a, b, c, d, k, s, i) { \ + (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ + (a) = SHIFT((a), (s)); \ + (a) = (b) + (a); \ +} + +#define ROUND2(a, b, c, d, k, s, i) { \ + (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ + (a) = SHIFT((a), (s)); \ + (a) = (b) + (a); \ +} + +#define ROUND3(a, b, c, d, k, s, i) { \ + (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ + (a) = SHIFT((a), (s)); \ + (a) = (b) + (a); \ +} + +#define ROUND4(a, b, c, d, k, s, i) { \ + (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ + (a) = SHIFT((a), (s)); \ + (a) = (b) + (a); \ +} + +#define Sa 7 +#define Sb 12 +#define Sc 17 +#define Sd 22 + +#define Se 5 +#define Sf 9 +#define Sg 14 +#define Sh 20 + +#define Si 4 +#define Sj 11 +#define Sk 16 +#define Sl 23 + +#define Sm 6 +#define Sn 10 +#define So 15 +#define Sp 21 + +#define MD5_A0 0x67452301 +#define MD5_B0 0xefcdab89 +#define MD5_C0 0x98badcfe +#define MD5_D0 0x10325476 + +/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ +static const u_int32_t T[65] = { + 0, + 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, + 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, + 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, + 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, + + 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, + 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, + 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, + 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, + + 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, + 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, + 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, + 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, + + 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, + 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, + 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, + 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, +}; + +static const u_int8_t md5_paddat[MD5_BUFLEN] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, +}; + +static void md5_calc(u_int8_t *, md5_ctxt *); + +void md5_init(ctxt) + md5_ctxt *ctxt; +{ + ctxt->md5_n = 0; + ctxt->md5_i = 0; + ctxt->md5_sta = MD5_A0; + ctxt->md5_stb = MD5_B0; + ctxt->md5_stc = MD5_C0; + ctxt->md5_std = MD5_D0; + bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); +} + +void md5_loop(ctxt, input, len) + md5_ctxt *ctxt; + u_int8_t *input; + u_int len; /* number of bytes */ +{ + u_int gap, i; + + ctxt->md5_n += len * 8; /* byte to bit */ + gap = MD5_BUFLEN - ctxt->md5_i; + + if (len >= gap) { + bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), + gap); + md5_calc(ctxt->md5_buf, ctxt); + + for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { + md5_calc((u_int8_t *)(input + i), ctxt); + } + + ctxt->md5_i = len - i; + bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); + } else { + bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), + len); + ctxt->md5_i += len; + } +} + +void md5_pad(ctxt) + md5_ctxt *ctxt; +{ + u_int gap; + + /* Don't count up padding. Keep md5_n. */ + gap = MD5_BUFLEN - ctxt->md5_i; + if (gap > 8) { + bcopy(md5_paddat, + (void *)(ctxt->md5_buf + ctxt->md5_i), + gap - sizeof(ctxt->md5_n)); + } else { + /* including gap == 8 */ + bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), + gap); + md5_calc(ctxt->md5_buf, ctxt); + bcopy((md5_paddat + gap), + (void *)ctxt->md5_buf, + MD5_BUFLEN - sizeof(ctxt->md5_n)); + } + + /* 8 byte word */ +#if BYTE_ORDER == LITTLE_ENDIAN + bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); +#endif +#if BYTE_ORDER == BIG_ENDIAN + ctxt->md5_buf[56] = ctxt->md5_n8[7]; + ctxt->md5_buf[57] = ctxt->md5_n8[6]; + ctxt->md5_buf[58] = ctxt->md5_n8[5]; + ctxt->md5_buf[59] = ctxt->md5_n8[4]; + ctxt->md5_buf[60] = ctxt->md5_n8[3]; + ctxt->md5_buf[61] = ctxt->md5_n8[2]; + ctxt->md5_buf[62] = ctxt->md5_n8[1]; + ctxt->md5_buf[63] = ctxt->md5_n8[0]; +#endif + + md5_calc(ctxt->md5_buf, ctxt); +} + +void md5_result(digest, ctxt) + u_int8_t *digest; + md5_ctxt *ctxt; +{ + /* 4 byte words */ +#if BYTE_ORDER == LITTLE_ENDIAN + bcopy(&ctxt->md5_st8[0], digest, 16); +#endif +#if BYTE_ORDER == BIG_ENDIAN + digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; + digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; + digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; + digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; + digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; + digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; + digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; + digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; +#endif +} + +static void md5_calc(b64, ctxt) + u_int8_t *b64; + md5_ctxt *ctxt; +{ + u_int32_t A = ctxt->md5_sta; + u_int32_t B = ctxt->md5_stb; + u_int32_t C = ctxt->md5_stc; + u_int32_t D = ctxt->md5_std; +#if BYTE_ORDER == LITTLE_ENDIAN + u_int32_t *X = (u_int32_t *)b64; +#endif +#if BYTE_ORDER == BIG_ENDIAN + /* 4 byte words */ + /* what a brute force but fast! */ + u_int32_t X[16]; + u_int8_t *y = (u_int8_t *)X; + y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; + y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; + y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; + y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; + y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; + y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; + y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; + y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; + y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; + y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; + y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; + y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; + y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; + y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; + y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; + y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; +#endif + + ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); + ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); + ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); + ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); + ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); + ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); + ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); + ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); + + ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); + ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); + ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); + ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); + ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); + ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); + ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); + ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); + + ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); + ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); + ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); + ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); + ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); + ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); + ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); + ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); + + ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); + ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); + ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); + ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); + ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); + ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); + ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); + ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); + + ctxt->md5_sta += A; + ctxt->md5_stb += B; + ctxt->md5_stc += C; + ctxt->md5_std += D; +} diff --git a/target/linux/generic/files/crypto/ocf/safe/md5.h b/target/linux/generic/files/crypto/ocf/safe/md5.h new file mode 100644 index 0000000..690f5bf --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/md5.h @@ -0,0 +1,76 @@ +/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ +/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ + +/* + * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _NETINET6_MD5_H_ +#define _NETINET6_MD5_H_ + +#define MD5_BUFLEN 64 + +typedef struct { + union { + u_int32_t md5_state32[4]; + u_int8_t md5_state8[16]; + } md5_st; + +#define md5_sta md5_st.md5_state32[0] +#define md5_stb md5_st.md5_state32[1] +#define md5_stc md5_st.md5_state32[2] +#define md5_std md5_st.md5_state32[3] +#define md5_st8 md5_st.md5_state8 + + union { + u_int64_t md5_count64; + u_int8_t md5_count8[8]; + } md5_count; +#define md5_n md5_count.md5_count64 +#define md5_n8 md5_count.md5_count8 + + u_int md5_i; + u_int8_t md5_buf[MD5_BUFLEN]; +} md5_ctxt; + +extern void md5_init(md5_ctxt *); +extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); +extern void md5_pad(md5_ctxt *); +extern void md5_result(u_int8_t *, md5_ctxt *); + +/* compatibility */ +#define MD5_CTX md5_ctxt +#define MD5Init(x) md5_init((x)) +#define MD5Update(x, y, z) md5_loop((x), (y), (z)) +#define MD5Final(x, y) \ +do { \ + md5_pad((y)); \ + md5_result((x), (y)); \ +} while (0) + +#endif /* ! _NETINET6_MD5_H_*/ diff --git a/target/linux/generic/files/crypto/ocf/safe/safe.c b/target/linux/generic/files/crypto/ocf/safe/safe.c new file mode 100644 index 0000000..f4daa5f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/safe.c @@ -0,0 +1,2230 @@ +/*- + * Linux port done by David McCullough + * Copyright (C) 2004-2010 David McCullough + * The license and original author are listed below. + * + * Copyright (c) 2003 Sam Leffler, Errno Consulting + * Copyright (c) 2003 Global Technology Associates, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * +__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SafeNet SafeXcel-1141 hardware crypto accelerator + */ + +#include +#include +#include +#include + +#if 1 +#define DPRINTF(a) do { \ + if (debug) { \ + printk("%s: ", sc ? \ + device_get_nameunit(sc->sc_dev) : "safe"); \ + printk a; \ + } \ + } while (0) +#else +#define DPRINTF(a) +#endif + +/* + * until we find a cleaner way, include the BSD md5/sha1 code + * here + */ +#define HMAC_HACK 1 +#ifdef HMAC_HACK +#include +#include +#include +#include +#include +#endif /* HMAC_HACK */ + +/* add proc entry for this */ +struct safe_stats safestats; + +#define debug safe_debug +int safe_debug = 0; +module_param(safe_debug, int, 0644); +MODULE_PARM_DESC(safe_debug, "Enable debug"); + +static void safe_callback(struct safe_softc *, struct safe_ringentry *); +static void safe_feed(struct safe_softc *, struct safe_ringentry *); +#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) +static void safe_rng_init(struct safe_softc *); +int safe_rngbufsize = 8; /* 32 bytes each read */ +module_param(safe_rngbufsize, int, 0644); +MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); +int safe_rngmaxalarm = 8; /* max alarms before reset */ +module_param(safe_rngmaxalarm, int, 0644); +MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); +#endif /* SAFE_NO_RNG */ + +static void safe_totalreset(struct safe_softc *sc); +static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); +static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); +static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); +static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); +static int safe_kstart(struct safe_softc *sc); +static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); +static void safe_kfeed(struct safe_softc *sc); +static void safe_kpoll(unsigned long arg); +static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, + u_int32_t len, struct crparam *n); + +static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); +static int safe_freesession(device_t, u_int64_t); +static int safe_process(device_t, struct cryptop *, int); + +static device_method_t safe_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, safe_newsession), + DEVMETHOD(cryptodev_freesession,safe_freesession), + DEVMETHOD(cryptodev_process, safe_process), + DEVMETHOD(cryptodev_kprocess, safe_kprocess), +}; + +#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) +#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) + +#define SAFE_MAX_CHIPS 8 +static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; + +/* + * split our buffers up into safe DMAable byte fragments to avoid lockup + * bug in 1141 HW on rev 1.0. + */ + +static int +pci_map_linear( + struct safe_softc *sc, + struct safe_operand *buf, + void *addr, + int len) +{ + dma_addr_t tmp; + int chunk, tlen = len; + + tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); + + buf->mapsize += len; + while (len > 0) { + chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; + buf->segs[buf->nsegs].ds_addr = tmp; + buf->segs[buf->nsegs].ds_len = chunk; + buf->segs[buf->nsegs].ds_tlen = tlen; + buf->nsegs++; + tmp += chunk; + len -= chunk; + tlen = 0; + } + return 0; +} + +/* + * map in a given uio buffer (great on some arches :-) + */ + +static int +pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) +{ + struct iovec *iov = uio->uio_iov; + int n; + + DPRINTF(("%s()\n", __FUNCTION__)); + + buf->mapsize = 0; + buf->nsegs = 0; + + for (n = 0; n < uio->uio_iovcnt; n++) { + pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); + iov++; + } + + /* identify this buffer by the first segment */ + buf->map = (void *) buf->segs[0].ds_addr; + return(0); +} + +/* + * map in a given sk_buff + */ + +static int +pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) +{ + int i; + + DPRINTF(("%s()\n", __FUNCTION__)); + + buf->mapsize = 0; + buf->nsegs = 0; + + pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); + + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { + pci_map_linear(sc, buf, + page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) + + skb_shinfo(skb)->frags[i].page_offset, + skb_shinfo(skb)->frags[i].size); + } + + /* identify this buffer by the first segment */ + buf->map = (void *) buf->segs[0].ds_addr; + return(0); +} + + +#if 0 /* not needed at this time */ +static void +pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) +{ + int i; + + DPRINTF(("%s()\n", __FUNCTION__)); + for (i = 0; i < buf->nsegs; i++) + pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, + buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); +} +#endif + +static void +pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) +{ + int i; + DPRINTF(("%s()\n", __FUNCTION__)); + for (i = 0; i < buf->nsegs; i++) { + if (buf->segs[i].ds_tlen) { + DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); + pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, + buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); + DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); + } + buf->segs[i].ds_addr = 0; + buf->segs[i].ds_len = 0; + buf->segs[i].ds_tlen = 0; + } + buf->nsegs = 0; + buf->mapsize = 0; + buf->map = 0; +} + + +/* + * SafeXcel Interrupt routine + */ +static irqreturn_t +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) +safe_intr(int irq, void *arg) +#else +safe_intr(int irq, void *arg, struct pt_regs *regs) +#endif +{ + struct safe_softc *sc = arg; + int stat; + unsigned long flags; + + stat = READ_REG(sc, SAFE_HM_STAT); + + DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); + + if (stat == 0) /* shared irq, not for us */ + return IRQ_NONE; + + WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ + + if ((stat & SAFE_INT_PE_DDONE)) { + /* + * Descriptor(s) done; scan the ring and + * process completed operations. + */ + spin_lock_irqsave(&sc->sc_ringmtx, flags); + while (sc->sc_back != sc->sc_front) { + struct safe_ringentry *re = sc->sc_back; + +#ifdef SAFE_DEBUG + if (debug) { + safe_dump_ringstate(sc, __func__); + safe_dump_request(sc, __func__, re); + } +#endif + /* + * safe_process marks ring entries that were allocated + * but not used with a csr of zero. This insures the + * ring front pointer never needs to be set backwards + * in the event that an entry is allocated but not used + * because of a setup error. + */ + DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); + if (re->re_desc.d_csr != 0) { + if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { + DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); + break; + } + if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { + DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); + break; + } + sc->sc_nqchip--; + safe_callback(sc, re); + } + if (++(sc->sc_back) == sc->sc_ringtop) + sc->sc_back = sc->sc_ring; + } + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); + } + + /* + * Check to see if we got any DMA Error + */ + if (stat & SAFE_INT_PE_ERROR) { + printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), + (int)READ_REG(sc, SAFE_PE_DMASTAT)); + safestats.st_dmaerr++; + safe_totalreset(sc); +#if 0 + safe_feed(sc); +#endif + } + + if (sc->sc_needwakeup) { /* XXX check high watermark */ + int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); + DPRINTF(("%s: wakeup crypto %x\n", __func__, + sc->sc_needwakeup)); + sc->sc_needwakeup &= ~wakeup; + crypto_unblock(sc->sc_cid, wakeup); + } + + return IRQ_HANDLED; +} + +/* + * safe_feed() - post a request to chip + */ +static void +safe_feed(struct safe_softc *sc, struct safe_ringentry *re) +{ + DPRINTF(("%s()\n", __FUNCTION__)); +#ifdef SAFE_DEBUG + if (debug) { + safe_dump_ringstate(sc, __func__); + safe_dump_request(sc, __func__, re); + } +#endif + sc->sc_nqchip++; + if (sc->sc_nqchip > safestats.st_maxqchip) + safestats.st_maxqchip = sc->sc_nqchip; + /* poke h/w to check descriptor ring, any value can be written */ + WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); +} + +#define N(a) (sizeof(a) / sizeof (a[0])) +static void +safe_setup_enckey(struct safe_session *ses, caddr_t key) +{ + int i; + + bcopy(key, ses->ses_key, ses->ses_klen / 8); + + /* PE is little-endian, insure proper byte order */ + for (i = 0; i < N(ses->ses_key); i++) + ses->ses_key[i] = htole32(ses->ses_key[i]); +} + +static void +safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) +{ +#ifdef HMAC_HACK + MD5_CTX md5ctx; + SHA1_CTX sha1ctx; + int i; + + + for (i = 0; i < klen; i++) + key[i] ^= HMAC_IPAD_VAL; + + if (algo == CRYPTO_MD5_HMAC) { + MD5Init(&md5ctx); + MD5Update(&md5ctx, key, klen); + MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); + bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); + } else { + SHA1Init(&sha1ctx); + SHA1Update(&sha1ctx, key, klen); + SHA1Update(&sha1ctx, hmac_ipad_buffer, + SHA1_HMAC_BLOCK_LEN - klen); + bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); + } + + for (i = 0; i < klen; i++) + key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); + + if (algo == CRYPTO_MD5_HMAC) { + MD5Init(&md5ctx); + MD5Update(&md5ctx, key, klen); + MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); + bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); + } else { + SHA1Init(&sha1ctx); + SHA1Update(&sha1ctx, key, klen); + SHA1Update(&sha1ctx, hmac_opad_buffer, + SHA1_HMAC_BLOCK_LEN - klen); + bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); + } + + for (i = 0; i < klen; i++) + key[i] ^= HMAC_OPAD_VAL; + +#if 0 + /* + * this code prevents SHA working on a BE host, + * so it is obviously wrong. I think the byte + * swap setup we do with the chip fixes this for us + */ + + /* PE is little-endian, insure proper byte order */ + for (i = 0; i < N(ses->ses_hminner); i++) { + ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); + ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); + } +#endif +#else /* HMAC_HACK */ + printk("safe: md5/sha not implemented\n"); +#endif /* HMAC_HACK */ +} +#undef N + +/* + * Allocate a new 'session' and return an encoded session id. 'sidp' + * contains our registration id, and should contain an encoded session + * id on successful allocation. + */ +static int +safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) +{ + struct safe_softc *sc = device_get_softc(dev); + struct cryptoini *c, *encini = NULL, *macini = NULL; + struct safe_session *ses = NULL; + int sesn; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (sidp == NULL || cri == NULL || sc == NULL) + return (EINVAL); + + for (c = cri; c != NULL; c = c->cri_next) { + if (c->cri_alg == CRYPTO_MD5_HMAC || + c->cri_alg == CRYPTO_SHA1_HMAC || + c->cri_alg == CRYPTO_NULL_HMAC) { + if (macini) + return (EINVAL); + macini = c; + } else if (c->cri_alg == CRYPTO_DES_CBC || + c->cri_alg == CRYPTO_3DES_CBC || + c->cri_alg == CRYPTO_AES_CBC || + c->cri_alg == CRYPTO_NULL_CBC) { + if (encini) + return (EINVAL); + encini = c; + } else + return (EINVAL); + } + if (encini == NULL && macini == NULL) + return (EINVAL); + if (encini) { /* validate key length */ + switch (encini->cri_alg) { + case CRYPTO_DES_CBC: + if (encini->cri_klen != 64) + return (EINVAL); + break; + case CRYPTO_3DES_CBC: + if (encini->cri_klen != 192) + return (EINVAL); + break; + case CRYPTO_AES_CBC: + if (encini->cri_klen != 128 && + encini->cri_klen != 192 && + encini->cri_klen != 256) + return (EINVAL); + break; + } + } + + if (sc->sc_sessions == NULL) { + ses = sc->sc_sessions = (struct safe_session *) + kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); + if (ses == NULL) + return (ENOMEM); + memset(ses, 0, sizeof(struct safe_session)); + sesn = 0; + sc->sc_nsessions = 1; + } else { + for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { + if (sc->sc_sessions[sesn].ses_used == 0) { + ses = &sc->sc_sessions[sesn]; + break; + } + } + + if (ses == NULL) { + sesn = sc->sc_nsessions; + ses = (struct safe_session *) + kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); + if (ses == NULL) + return (ENOMEM); + memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); + bcopy(sc->sc_sessions, ses, sesn * + sizeof(struct safe_session)); + bzero(sc->sc_sessions, sesn * + sizeof(struct safe_session)); + kfree(sc->sc_sessions); + sc->sc_sessions = ses; + ses = &sc->sc_sessions[sesn]; + sc->sc_nsessions++; + } + } + + bzero(ses, sizeof(struct safe_session)); + ses->ses_used = 1; + + if (encini) { + ses->ses_klen = encini->cri_klen; + if (encini->cri_key != NULL) + safe_setup_enckey(ses, encini->cri_key); + } + + if (macini) { + ses->ses_mlen = macini->cri_mlen; + if (ses->ses_mlen == 0) { + if (macini->cri_alg == CRYPTO_MD5_HMAC) + ses->ses_mlen = MD5_HASH_LEN; + else + ses->ses_mlen = SHA1_HASH_LEN; + } + + if (macini->cri_key != NULL) { + safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, + macini->cri_klen / 8); + } + } + + *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); + return (0); +} + +/* + * Deallocate a session. + */ +static int +safe_freesession(device_t dev, u_int64_t tid) +{ + struct safe_softc *sc = device_get_softc(dev); + int session, ret; + u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (sc == NULL) + return (EINVAL); + + session = SAFE_SESSION(sid); + if (session < sc->sc_nsessions) { + bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); + ret = 0; + } else + ret = EINVAL; + return (ret); +} + + +static int +safe_process(device_t dev, struct cryptop *crp, int hint) +{ + struct safe_softc *sc = device_get_softc(dev); + int err = 0, i, nicealign, uniform; + struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; + int bypass, oplen, ivsize; + caddr_t iv; + int16_t coffset; + struct safe_session *ses; + struct safe_ringentry *re; + struct safe_sarec *sa; + struct safe_pdesc *pd; + u_int32_t cmd0, cmd1, staterec, rand_iv[4]; + unsigned long flags; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { + safestats.st_invalid++; + return (EINVAL); + } + if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { + safestats.st_badsession++; + return (EINVAL); + } + + spin_lock_irqsave(&sc->sc_ringmtx, flags); + if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { + safestats.st_ringfull++; + sc->sc_needwakeup |= CRYPTO_SYMQ; + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); + return (ERESTART); + } + re = sc->sc_front; + + staterec = re->re_sa.sa_staterec; /* save */ + /* NB: zero everything but the PE descriptor */ + bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); + re->re_sa.sa_staterec = staterec; /* restore */ + + re->re_crp = crp; + re->re_sesn = SAFE_SESSION(crp->crp_sid); + + re->re_src.nsegs = 0; + re->re_dst.nsegs = 0; + + if (crp->crp_flags & CRYPTO_F_SKBUF) { + re->re_src_skb = (struct sk_buff *)crp->crp_buf; + re->re_dst_skb = (struct sk_buff *)crp->crp_buf; + } else if (crp->crp_flags & CRYPTO_F_IOV) { + re->re_src_io = (struct uio *)crp->crp_buf; + re->re_dst_io = (struct uio *)crp->crp_buf; + } else { + safestats.st_badflags++; + err = EINVAL; + goto errout; /* XXX we don't handle contiguous blocks! */ + } + + sa = &re->re_sa; + ses = &sc->sc_sessions[re->re_sesn]; + + crd1 = crp->crp_desc; + if (crd1 == NULL) { + safestats.st_nodesc++; + err = EINVAL; + goto errout; + } + crd2 = crd1->crd_next; + + cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ + cmd1 = 0; + if (crd2 == NULL) { + if (crd1->crd_alg == CRYPTO_MD5_HMAC || + crd1->crd_alg == CRYPTO_SHA1_HMAC || + crd1->crd_alg == CRYPTO_NULL_HMAC) { + maccrd = crd1; + enccrd = NULL; + cmd0 |= SAFE_SA_CMD0_OP_HASH; + } else if (crd1->crd_alg == CRYPTO_DES_CBC || + crd1->crd_alg == CRYPTO_3DES_CBC || + crd1->crd_alg == CRYPTO_AES_CBC || + crd1->crd_alg == CRYPTO_NULL_CBC) { + maccrd = NULL; + enccrd = crd1; + cmd0 |= SAFE_SA_CMD0_OP_CRYPT; + } else { + safestats.st_badalg++; + err = EINVAL; + goto errout; + } + } else { + if ((crd1->crd_alg == CRYPTO_MD5_HMAC || + crd1->crd_alg == CRYPTO_SHA1_HMAC || + crd1->crd_alg == CRYPTO_NULL_HMAC) && + (crd2->crd_alg == CRYPTO_DES_CBC || + crd2->crd_alg == CRYPTO_3DES_CBC || + crd2->crd_alg == CRYPTO_AES_CBC || + crd2->crd_alg == CRYPTO_NULL_CBC) && + ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { + maccrd = crd1; + enccrd = crd2; + } else if ((crd1->crd_alg == CRYPTO_DES_CBC || + crd1->crd_alg == CRYPTO_3DES_CBC || + crd1->crd_alg == CRYPTO_AES_CBC || + crd1->crd_alg == CRYPTO_NULL_CBC) && + (crd2->crd_alg == CRYPTO_MD5_HMAC || + crd2->crd_alg == CRYPTO_SHA1_HMAC || + crd2->crd_alg == CRYPTO_NULL_HMAC) && + (crd1->crd_flags & CRD_F_ENCRYPT)) { + enccrd = crd1; + maccrd = crd2; + } else { + safestats.st_badalg++; + err = EINVAL; + goto errout; + } + cmd0 |= SAFE_SA_CMD0_OP_BOTH; + } + + if (enccrd) { + if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) + safe_setup_enckey(ses, enccrd->crd_key); + + if (enccrd->crd_alg == CRYPTO_DES_CBC) { + cmd0 |= SAFE_SA_CMD0_DES; + cmd1 |= SAFE_SA_CMD1_CBC; + ivsize = 2*sizeof(u_int32_t); + } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { + cmd0 |= SAFE_SA_CMD0_3DES; + cmd1 |= SAFE_SA_CMD1_CBC; + ivsize = 2*sizeof(u_int32_t); + } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { + cmd0 |= SAFE_SA_CMD0_AES; + cmd1 |= SAFE_SA_CMD1_CBC; + if (ses->ses_klen == 128) + cmd1 |= SAFE_SA_CMD1_AES128; + else if (ses->ses_klen == 192) + cmd1 |= SAFE_SA_CMD1_AES192; + else + cmd1 |= SAFE_SA_CMD1_AES256; + ivsize = 4*sizeof(u_int32_t); + } else { + cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; + ivsize = 0; + } + + /* + * Setup encrypt/decrypt state. When using basic ops + * we can't use an inline IV because hash/crypt offset + * must be from the end of the IV to the start of the + * crypt data and this leaves out the preceding header + * from the hash calculation. Instead we place the IV + * in the state record and set the hash/crypt offset to + * copy both the header+IV. + */ + if (enccrd->crd_flags & CRD_F_ENCRYPT) { + cmd0 |= SAFE_SA_CMD0_OUTBOUND; + + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) + iv = enccrd->crd_iv; + else + read_random((iv = (caddr_t) &rand_iv[0]), sizeof(rand_iv)); + if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { + crypto_copyback(crp->crp_flags, crp->crp_buf, + enccrd->crd_inject, ivsize, iv); + } + bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); + /* make iv LE */ + for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) + re->re_sastate.sa_saved_iv[i] = + cpu_to_le32(re->re_sastate.sa_saved_iv[i]); + cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; + re->re_flags |= SAFE_QFLAGS_COPYOUTIV; + } else { + cmd0 |= SAFE_SA_CMD0_INBOUND; + + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { + bcopy(enccrd->crd_iv, + re->re_sastate.sa_saved_iv, ivsize); + } else { + crypto_copydata(crp->crp_flags, crp->crp_buf, + enccrd->crd_inject, ivsize, + (caddr_t)re->re_sastate.sa_saved_iv); + } + /* make iv LE */ + for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) + re->re_sastate.sa_saved_iv[i] = + cpu_to_le32(re->re_sastate.sa_saved_iv[i]); + cmd0 |= SAFE_SA_CMD0_IVLD_STATE; + } + /* + * For basic encryption use the zero pad algorithm. + * This pads results to an 8-byte boundary and + * suppresses padding verification for inbound (i.e. + * decrypt) operations. + * + * NB: Not sure if the 8-byte pad boundary is a problem. + */ + cmd0 |= SAFE_SA_CMD0_PAD_ZERO; + + /* XXX assert key bufs have the same size */ + bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); + } + + if (maccrd) { + if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { + safe_setup_mackey(ses, maccrd->crd_alg, + maccrd->crd_key, maccrd->crd_klen / 8); + } + + if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { + cmd0 |= SAFE_SA_CMD0_MD5; + cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ + } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { + cmd0 |= SAFE_SA_CMD0_SHA1; + cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ + } else { + cmd0 |= SAFE_SA_CMD0_HASH_NULL; + } + /* + * Digest data is loaded from the SA and the hash + * result is saved to the state block where we + * retrieve it for return to the caller. + */ + /* XXX assert digest bufs have the same size */ + bcopy(ses->ses_hminner, sa->sa_indigest, + sizeof(sa->sa_indigest)); + bcopy(ses->ses_hmouter, sa->sa_outdigest, + sizeof(sa->sa_outdigest)); + + cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; + re->re_flags |= SAFE_QFLAGS_COPYOUTICV; + } + + if (enccrd && maccrd) { + /* + * The offset from hash data to the start of + * crypt data is the difference in the skips. + */ + bypass = maccrd->crd_skip; + coffset = enccrd->crd_skip - maccrd->crd_skip; + if (coffset < 0) { + DPRINTF(("%s: hash does not precede crypt; " + "mac skip %u enc skip %u\n", + __func__, maccrd->crd_skip, enccrd->crd_skip)); + safestats.st_skipmismatch++; + err = EINVAL; + goto errout; + } + oplen = enccrd->crd_skip + enccrd->crd_len; + if (maccrd->crd_skip + maccrd->crd_len != oplen) { + DPRINTF(("%s: hash amount %u != crypt amount %u\n", + __func__, maccrd->crd_skip + maccrd->crd_len, + oplen)); + safestats.st_lenmismatch++; + err = EINVAL; + goto errout; + } +#ifdef SAFE_DEBUG + if (debug) { + printf("mac: skip %d, len %d, inject %d\n", + maccrd->crd_skip, maccrd->crd_len, + maccrd->crd_inject); + printf("enc: skip %d, len %d, inject %d\n", + enccrd->crd_skip, enccrd->crd_len, + enccrd->crd_inject); + printf("bypass %d coffset %d oplen %d\n", + bypass, coffset, oplen); + } +#endif + if (coffset & 3) { /* offset must be 32-bit aligned */ + DPRINTF(("%s: coffset %u misaligned\n", + __func__, coffset)); + safestats.st_coffmisaligned++; + err = EINVAL; + goto errout; + } + coffset >>= 2; + if (coffset > 255) { /* offset must be <256 dwords */ + DPRINTF(("%s: coffset %u too big\n", + __func__, coffset)); + safestats.st_cofftoobig++; + err = EINVAL; + goto errout; + } + /* + * Tell the hardware to copy the header to the output. + * The header is defined as the data from the end of + * the bypass to the start of data to be encrypted. + * Typically this is the inline IV. Note that you need + * to do this even if src+dst are the same; it appears + * that w/o this bit the crypted data is written + * immediately after the bypass data. + */ + cmd1 |= SAFE_SA_CMD1_HDRCOPY; + /* + * Disable IP header mutable bit handling. This is + * needed to get correct HMAC calculations. + */ + cmd1 |= SAFE_SA_CMD1_MUTABLE; + } else { + if (enccrd) { + bypass = enccrd->crd_skip; + oplen = bypass + enccrd->crd_len; + } else { + bypass = maccrd->crd_skip; + oplen = bypass + maccrd->crd_len; + } + coffset = 0; + } + /* XXX verify multiple of 4 when using s/g */ + if (bypass > 96) { /* bypass offset must be <= 96 bytes */ + DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); + safestats.st_bypasstoobig++; + err = EINVAL; + goto errout; + } + + if (crp->crp_flags & CRYPTO_F_SKBUF) { + if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { + safestats.st_noload++; + err = ENOMEM; + goto errout; + } + } else if (crp->crp_flags & CRYPTO_F_IOV) { + if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { + safestats.st_noload++; + err = ENOMEM; + goto errout; + } + } + nicealign = safe_dmamap_aligned(sc, &re->re_src); + uniform = safe_dmamap_uniform(sc, &re->re_src); + + DPRINTF(("src nicealign %u uniform %u nsegs %u\n", + nicealign, uniform, re->re_src.nsegs)); + if (re->re_src.nsegs > 1) { + re->re_desc.d_src = sc->sc_spalloc.dma_paddr + + ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); + for (i = 0; i < re->re_src_nsegs; i++) { + /* NB: no need to check if there's space */ + pd = sc->sc_spfree; + if (++(sc->sc_spfree) == sc->sc_springtop) + sc->sc_spfree = sc->sc_spring; + + KASSERT((pd->pd_flags&3) == 0 || + (pd->pd_flags&3) == SAFE_PD_DONE, + ("bogus source particle descriptor; flags %x", + pd->pd_flags)); + pd->pd_addr = re->re_src_segs[i].ds_addr; + pd->pd_size = re->re_src_segs[i].ds_len; + pd->pd_flags = SAFE_PD_READY; + } + cmd0 |= SAFE_SA_CMD0_IGATHER; + } else { + /* + * No need for gather, reference the operand directly. + */ + re->re_desc.d_src = re->re_src_segs[0].ds_addr; + } + + if (enccrd == NULL && maccrd != NULL) { + /* + * Hash op; no destination needed. + */ + } else { + if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { + if (!nicealign) { + safestats.st_iovmisaligned++; + err = EINVAL; + goto errout; + } + if (uniform != 1) { + device_printf(sc->sc_dev, "!uniform source\n"); + if (!uniform) { + /* + * There's no way to handle the DMA + * requirements with this uio. We + * could create a separate DMA area for + * the result and then copy it back, + * but for now we just bail and return + * an error. Note that uio requests + * > SAFE_MAX_DSIZE are handled because + * the DMA map and segment list for the + * destination wil result in a + * destination particle list that does + * the necessary scatter DMA. + */ + safestats.st_iovnotuniform++; + err = EINVAL; + goto errout; + } + } else + re->re_dst = re->re_src; + } else { + safestats.st_badflags++; + err = EINVAL; + goto errout; + } + + if (re->re_dst.nsegs > 1) { + re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + + ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); + for (i = 0; i < re->re_dst_nsegs; i++) { + pd = sc->sc_dpfree; + KASSERT((pd->pd_flags&3) == 0 || + (pd->pd_flags&3) == SAFE_PD_DONE, + ("bogus dest particle descriptor; flags %x", + pd->pd_flags)); + if (++(sc->sc_dpfree) == sc->sc_dpringtop) + sc->sc_dpfree = sc->sc_dpring; + pd->pd_addr = re->re_dst_segs[i].ds_addr; + pd->pd_flags = SAFE_PD_READY; + } + cmd0 |= SAFE_SA_CMD0_OSCATTER; + } else { + /* + * No need for scatter, reference the operand directly. + */ + re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; + } + } + + /* + * All done with setup; fillin the SA command words + * and the packet engine descriptor. The operation + * is now ready for submission to the hardware. + */ + sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; + sa->sa_cmd1 = cmd1 + | (coffset << SAFE_SA_CMD1_OFFSET_S) + | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ + | SAFE_SA_CMD1_SRPCI + ; + /* + * NB: the order of writes is important here. In case the + * chip is scanning the ring because of an outstanding request + * it might nab this one too. In that case we need to make + * sure the setup is complete before we write the length + * field of the descriptor as it signals the descriptor is + * ready for processing. + */ + re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; + if (maccrd) + re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; + wmb(); + re->re_desc.d_len = oplen + | SAFE_PE_LEN_READY + | (bypass << SAFE_PE_LEN_BYPASS_S) + ; + + safestats.st_ipackets++; + safestats.st_ibytes += oplen; + + if (++(sc->sc_front) == sc->sc_ringtop) + sc->sc_front = sc->sc_ring; + + /* XXX honor batching */ + safe_feed(sc, re); + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); + return (0); + +errout: + if (re->re_src.map != re->re_dst.map) + pci_unmap_operand(sc, &re->re_dst); + if (re->re_src.map) + pci_unmap_operand(sc, &re->re_src); + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); + if (err != ERESTART) { + crp->crp_etype = err; + crypto_done(crp); + } else { + sc->sc_needwakeup |= CRYPTO_SYMQ; + } + return (err); +} + +static void +safe_callback(struct safe_softc *sc, struct safe_ringentry *re) +{ + struct cryptop *crp = (struct cryptop *)re->re_crp; + struct cryptodesc *crd; + + DPRINTF(("%s()\n", __FUNCTION__)); + + safestats.st_opackets++; + safestats.st_obytes += re->re_dst.mapsize; + + if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { + device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", + re->re_desc.d_csr, + re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); + safestats.st_peoperr++; + crp->crp_etype = EIO; /* something more meaningful? */ + } + + if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) + pci_unmap_operand(sc, &re->re_dst); + pci_unmap_operand(sc, &re->re_src); + + /* + * If result was written to a differet mbuf chain, swap + * it in as the return value and reclaim the original. + */ + if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { + device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); + /* kfree_skb(skb) */ + /* crp->crp_buf = (caddr_t)re->re_dst_skb */ + return; + } + + if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { + /* copy out ICV result */ + for (crd = crp->crp_desc; crd; crd = crd->crd_next) { + if (!(crd->crd_alg == CRYPTO_MD5_HMAC || + crd->crd_alg == CRYPTO_SHA1_HMAC || + crd->crd_alg == CRYPTO_NULL_HMAC)) + continue; + if (crd->crd_alg == CRYPTO_SHA1_HMAC) { + /* + * SHA-1 ICV's are byte-swapped; fix 'em up + * before copy them to their destination. + */ + re->re_sastate.sa_saved_indigest[0] = + cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); + re->re_sastate.sa_saved_indigest[1] = + cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); + re->re_sastate.sa_saved_indigest[2] = + cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); + } else { + re->re_sastate.sa_saved_indigest[0] = + cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); + re->re_sastate.sa_saved_indigest[1] = + cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); + re->re_sastate.sa_saved_indigest[2] = + cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); + } + crypto_copyback(crp->crp_flags, crp->crp_buf, + crd->crd_inject, + sc->sc_sessions[re->re_sesn].ses_mlen, + (caddr_t)re->re_sastate.sa_saved_indigest); + break; + } + } + crypto_done(crp); +} + + +#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) +#define SAFE_RNG_MAXWAIT 1000 + +static void +safe_rng_init(struct safe_softc *sc) +{ + u_int32_t w, v; + int i; + + DPRINTF(("%s()\n", __FUNCTION__)); + + WRITE_REG(sc, SAFE_RNG_CTRL, 0); + /* use default value according to the manual */ + WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ + WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); + + /* + * There is a bug in rev 1.0 of the 1140 that when the RNG + * is brought out of reset the ready status flag does not + * work until the RNG has finished its internal initialization. + * + * So in order to determine the device is through its + * initialization we must read the data register, using the + * status reg in the read in case it is initialized. Then read + * the data register until it changes from the first read. + * Once it changes read the data register until it changes + * again. At this time the RNG is considered initialized. + * This could take between 750ms - 1000ms in time. + */ + i = 0; + w = READ_REG(sc, SAFE_RNG_OUT); + do { + v = READ_REG(sc, SAFE_RNG_OUT); + if (v != w) { + w = v; + break; + } + DELAY(10); + } while (++i < SAFE_RNG_MAXWAIT); + + /* Wait Until data changes again */ + i = 0; + do { + v = READ_REG(sc, SAFE_RNG_OUT); + if (v != w) + break; + DELAY(10); + } while (++i < SAFE_RNG_MAXWAIT); +} + +static __inline void +safe_rng_disable_short_cycle(struct safe_softc *sc) +{ + DPRINTF(("%s()\n", __FUNCTION__)); + + WRITE_REG(sc, SAFE_RNG_CTRL, + READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); +} + +static __inline void +safe_rng_enable_short_cycle(struct safe_softc *sc) +{ + DPRINTF(("%s()\n", __FUNCTION__)); + + WRITE_REG(sc, SAFE_RNG_CTRL, + READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); +} + +static __inline u_int32_t +safe_rng_read(struct safe_softc *sc) +{ + int i; + + i = 0; + while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) + ; + return READ_REG(sc, SAFE_RNG_OUT); +} + +static int +safe_read_random(void *arg, u_int32_t *buf, int maxwords) +{ + struct safe_softc *sc = (struct safe_softc *) arg; + int i, rc; + + DPRINTF(("%s()\n", __FUNCTION__)); + + safestats.st_rng++; + /* + * Fetch the next block of data. + */ + if (maxwords > safe_rngbufsize) + maxwords = safe_rngbufsize; + if (maxwords > SAFE_RNG_MAXBUFSIZ) + maxwords = SAFE_RNG_MAXBUFSIZ; +retry: + /* read as much as we can */ + for (rc = 0; rc < maxwords; rc++) { + if (READ_REG(sc, SAFE_RNG_STAT) != 0) + break; + buf[rc] = READ_REG(sc, SAFE_RNG_OUT); + } + if (rc == 0) + return 0; + /* + * Check the comparator alarm count and reset the h/w if + * it exceeds our threshold. This guards against the + * hardware oscillators resonating with external signals. + */ + if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { + u_int32_t freq_inc, w; + + DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, + (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); + safestats.st_rngalarm++; + safe_rng_enable_short_cycle(sc); + freq_inc = 18; + for (i = 0; i < 64; i++) { + w = READ_REG(sc, SAFE_RNG_CNFG); + freq_inc = ((w + freq_inc) & 0x3fL); + w = ((w & ~0x3fL) | freq_inc); + WRITE_REG(sc, SAFE_RNG_CNFG, w); + + WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); + + (void) safe_rng_read(sc); + DELAY(25); + + if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { + safe_rng_disable_short_cycle(sc); + goto retry; + } + freq_inc = 1; + } + safe_rng_disable_short_cycle(sc); + } else + WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); + + return(rc); +} +#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ + + +/* + * Resets the board. Values in the regesters are left as is + * from the reset (i.e. initial values are assigned elsewhere). + */ +static void +safe_reset_board(struct safe_softc *sc) +{ + u_int32_t v; + /* + * Reset the device. The manual says no delay + * is needed between marking and clearing reset. + */ + DPRINTF(("%s()\n", __FUNCTION__)); + + v = READ_REG(sc, SAFE_PE_DMACFG) &~ + (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | + SAFE_PE_DMACFG_SGRESET); + WRITE_REG(sc, SAFE_PE_DMACFG, v + | SAFE_PE_DMACFG_PERESET + | SAFE_PE_DMACFG_PDRRESET + | SAFE_PE_DMACFG_SGRESET); + WRITE_REG(sc, SAFE_PE_DMACFG, v); +} + +/* + * Initialize registers we need to touch only once. + */ +static void +safe_init_board(struct safe_softc *sc) +{ + u_int32_t v, dwords; + + DPRINTF(("%s()\n", __FUNCTION__)); + + v = READ_REG(sc, SAFE_PE_DMACFG); + v &=~ ( SAFE_PE_DMACFG_PEMODE + | SAFE_PE_DMACFG_FSENA /* failsafe enable */ + | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ + | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ + | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ + | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ + | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ + | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ + ); + v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ + | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ + | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ + | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ + | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ + | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ +#if 0 + | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ +#endif + ; + WRITE_REG(sc, SAFE_PE_DMACFG, v); + +#ifdef __BIG_ENDIAN + /* tell the safenet that we are 4321 and not 1234 */ + WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); +#endif + + if (sc->sc_chiprev == SAFE_REV(1,0)) { + /* + * Avoid large PCI DMA transfers. Rev 1.0 has a bug where + * "target mode transfers" done while the chip is DMA'ing + * >1020 bytes cause the hardware to lockup. To avoid this + * we reduce the max PCI transfer size and use small source + * particle descriptors (<= 256 bytes). + */ + WRITE_REG(sc, SAFE_DMA_CFG, 256); + device_printf(sc->sc_dev, + "Reduce max DMA size to %u words for rev %u.%u WAR\n", + (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), + (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), + (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); + sc->sc_max_dsize = 256; + } else { + sc->sc_max_dsize = SAFE_MAX_DSIZE; + } + + /* NB: operands+results are overlaid */ + WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); + WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); + /* + * Configure ring entry size and number of items in the ring. + */ + KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, + ("PE ring entry not 32-bit aligned!")); + dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); + WRITE_REG(sc, SAFE_PE_RINGCFG, + (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); + WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ + + WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); + WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); + WRITE_REG(sc, SAFE_PE_PARTSIZE, + (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); + /* + * NB: destination particles are fixed size. We use + * an mbuf cluster and require all results go to + * clusters or smaller. + */ + WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); + + /* it's now safe to enable PE mode, do it */ + WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); + + /* + * Configure hardware to use level-triggered interrupts and + * to interrupt after each descriptor is processed. + */ + WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); + WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); + WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); + WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); +} + + +/* + * Clean up after a chip crash. + * It is assumed that the caller in splimp() + */ +static void +safe_cleanchip(struct safe_softc *sc) +{ + DPRINTF(("%s()\n", __FUNCTION__)); + + if (sc->sc_nqchip != 0) { + struct safe_ringentry *re = sc->sc_back; + + while (re != sc->sc_front) { + if (re->re_desc.d_csr != 0) + safe_free_entry(sc, re); + if (++re == sc->sc_ringtop) + re = sc->sc_ring; + } + sc->sc_back = re; + sc->sc_nqchip = 0; + } +} + +/* + * free a safe_q + * It is assumed that the caller is within splimp(). + */ +static int +safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) +{ + struct cryptop *crp; + + DPRINTF(("%s()\n", __FUNCTION__)); + + /* + * Free header MCR + */ + if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) +#ifdef NOTYET + m_freem(re->re_dst_m); +#else + printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); +#endif + + crp = (struct cryptop *)re->re_crp; + + re->re_desc.d_csr = 0; + + crp->crp_etype = EFAULT; + crypto_done(crp); + return(0); +} + +/* + * Routine to reset the chip and clean up. + * It is assumed that the caller is in splimp() + */ +static void +safe_totalreset(struct safe_softc *sc) +{ + DPRINTF(("%s()\n", __FUNCTION__)); + + safe_reset_board(sc); + safe_init_board(sc); + safe_cleanchip(sc); +} + +/* + * Is the operand suitable aligned for direct DMA. Each + * segment must be aligned on a 32-bit boundary and all + * but the last segment must be a multiple of 4 bytes. + */ +static int +safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) +{ + int i; + + DPRINTF(("%s()\n", __FUNCTION__)); + + for (i = 0; i < op->nsegs; i++) { + if (op->segs[i].ds_addr & 3) + return (0); + if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) + return (0); + } + return (1); +} + +/* + * Is the operand suitable for direct DMA as the destination + * of an operation. The hardware requires that each ``particle'' + * but the last in an operation result have the same size. We + * fix that size at SAFE_MAX_DSIZE bytes. This routine returns + * 0 if some segment is not a multiple of of this size, 1 if all + * segments are exactly this size, or 2 if segments are at worst + * a multple of this size. + */ +static int +safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) +{ + int result = 1; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (op->nsegs > 0) { + int i; + + for (i = 0; i < op->nsegs-1; i++) { + if (op->segs[i].ds_len % sc->sc_max_dsize) + return (0); + if (op->segs[i].ds_len != sc->sc_max_dsize) + result = 2; + } + } + return (result); +} + +static int +safe_kprocess(device_t dev, struct cryptkop *krp, int hint) +{ + struct safe_softc *sc = device_get_softc(dev); + struct safe_pkq *q; + unsigned long flags; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (sc == NULL) { + krp->krp_status = EINVAL; + goto err; + } + + if (krp->krp_op != CRK_MOD_EXP) { + krp->krp_status = EOPNOTSUPP; + goto err; + } + + q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); + if (q == NULL) { + krp->krp_status = ENOMEM; + goto err; + } + memset(q, 0, sizeof(*q)); + q->pkq_krp = krp; + INIT_LIST_HEAD(&q->pkq_list); + + spin_lock_irqsave(&sc->sc_pkmtx, flags); + list_add_tail(&q->pkq_list, &sc->sc_pkq); + safe_kfeed(sc); + spin_unlock_irqrestore(&sc->sc_pkmtx, flags); + return (0); + +err: + crypto_kdone(krp); + return (0); +} + +#define SAFE_CRK_PARAM_BASE 0 +#define SAFE_CRK_PARAM_EXP 1 +#define SAFE_CRK_PARAM_MOD 2 + +static int +safe_kstart(struct safe_softc *sc) +{ + struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; + int exp_bits, mod_bits, base_bits; + u_int32_t op, a_off, b_off, c_off, d_off; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { + krp->krp_status = EINVAL; + return (1); + } + + base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); + if (base_bits > 2048) + goto too_big; + if (base_bits <= 0) /* 5. base not zero */ + goto too_small; + + exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); + if (exp_bits > 2048) + goto too_big; + if (exp_bits <= 0) /* 1. exponent word length > 0 */ + goto too_small; /* 4. exponent not zero */ + + mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); + if (mod_bits > 2048) + goto too_big; + if (mod_bits <= 32) /* 2. modulus word length > 1 */ + goto too_small; /* 8. MSW of modulus != zero */ + if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ + goto too_small; + if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) + goto bad_domain; /* 6. modulus is odd */ + if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) + goto too_small; /* make sure result will fit */ + + /* 7. modulus > base */ + if (mod_bits < base_bits) + goto too_small; + if (mod_bits == base_bits) { + u_int8_t *basep, *modp; + int i; + + basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + + ((base_bits + 7) / 8) - 1; + modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + + ((mod_bits + 7) / 8) - 1; + + for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { + if (*modp < *basep) + goto too_small; + if (*modp > *basep) + break; + } + } + + /* And on the 9th step, he rested. */ + + WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); + WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); + if (mod_bits > 1024) { + op = SAFE_PK_FUNC_EXP4; + a_off = 0x000; + b_off = 0x100; + c_off = 0x200; + d_off = 0x300; + } else { + op = SAFE_PK_FUNC_EXP16; + a_off = 0x000; + b_off = 0x080; + c_off = 0x100; + d_off = 0x180; + } + sc->sc_pk_reslen = b_off - a_off; + sc->sc_pk_resoff = d_off; + + /* A is exponent, B is modulus, C is base, D is result */ + safe_kload_reg(sc, a_off, b_off - a_off, + &krp->krp_param[SAFE_CRK_PARAM_EXP]); + WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); + safe_kload_reg(sc, b_off, b_off - a_off, + &krp->krp_param[SAFE_CRK_PARAM_MOD]); + WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); + safe_kload_reg(sc, c_off, b_off - a_off, + &krp->krp_param[SAFE_CRK_PARAM_BASE]); + WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); + WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); + + WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); + + return (0); + +too_big: + krp->krp_status = E2BIG; + return (1); +too_small: + krp->krp_status = ERANGE; + return (1); +bad_domain: + krp->krp_status = EDOM; + return (1); +} + +static int +safe_ksigbits(struct safe_softc *sc, struct crparam *cr) +{ + u_int plen = (cr->crp_nbits + 7) / 8; + int i, sig = plen * 8; + u_int8_t c, *p = cr->crp_p; + + DPRINTF(("%s()\n", __FUNCTION__)); + + for (i = plen - 1; i >= 0; i--) { + c = p[i]; + if (c != 0) { + while ((c & 0x80) == 0) { + sig--; + c <<= 1; + } + break; + } + sig -= 8; + } + return (sig); +} + +static void +safe_kfeed(struct safe_softc *sc) +{ + struct safe_pkq *q, *tmp; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) + return; + if (sc->sc_pkq_cur != NULL) + return; + list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { + sc->sc_pkq_cur = q; + list_del(&q->pkq_list); + if (safe_kstart(sc) != 0) { + crypto_kdone(q->pkq_krp); + kfree(q); + sc->sc_pkq_cur = NULL; + } else { + /* op started, start polling */ + mod_timer(&sc->sc_pkto, jiffies + 1); + break; + } + } +} + +static void +safe_kpoll(unsigned long arg) +{ + struct safe_softc *sc = NULL; + struct safe_pkq *q; + struct crparam *res; + int i; + u_int32_t buf[64]; + unsigned long flags; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (arg >= SAFE_MAX_CHIPS) + return; + sc = safe_chip_idx[arg]; + if (!sc) { + DPRINTF(("%s() - bad callback\n", __FUNCTION__)); + return; + } + + spin_lock_irqsave(&sc->sc_pkmtx, flags); + if (sc->sc_pkq_cur == NULL) + goto out; + if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { + /* still running, check back later */ + mod_timer(&sc->sc_pkto, jiffies + 1); + goto out; + } + + q = sc->sc_pkq_cur; + res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; + bzero(buf, sizeof(buf)); + bzero(res->crp_p, (res->crp_nbits + 7) / 8); + for (i = 0; i < sc->sc_pk_reslen >> 2; i++) + buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + + sc->sc_pk_resoff + (i << 2))); + bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); + /* + * reduce the bits that need copying if possible + */ + res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); + res->crp_nbits = safe_ksigbits(sc, res); + + for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) + WRITE_REG(sc, i, 0); + + crypto_kdone(q->pkq_krp); + kfree(q); + sc->sc_pkq_cur = NULL; + + safe_kfeed(sc); +out: + spin_unlock_irqrestore(&sc->sc_pkmtx, flags); +} + +static void +safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, + struct crparam *n) +{ + u_int32_t buf[64], i; + + DPRINTF(("%s()\n", __FUNCTION__)); + + bzero(buf, sizeof(buf)); + bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); + + for (i = 0; i < len >> 2; i++) + WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), + cpu_to_le32(buf[i])); +} + +#ifdef SAFE_DEBUG +static void +safe_dump_dmastatus(struct safe_softc *sc, const char *tag) +{ + printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" + , tag + , READ_REG(sc, SAFE_DMA_ENDIAN) + , READ_REG(sc, SAFE_DMA_SRCADDR) + , READ_REG(sc, SAFE_DMA_DSTADDR) + , READ_REG(sc, SAFE_DMA_STAT) + ); +} + +static void +safe_dump_intrstate(struct safe_softc *sc, const char *tag) +{ + printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" + , tag + , READ_REG(sc, SAFE_HI_CFG) + , READ_REG(sc, SAFE_HI_MASK) + , READ_REG(sc, SAFE_HI_DESC_CNT) + , READ_REG(sc, SAFE_HU_STAT) + , READ_REG(sc, SAFE_HM_STAT) + ); +} + +static void +safe_dump_ringstate(struct safe_softc *sc, const char *tag) +{ + u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); + + /* NB: assume caller has lock on ring */ + printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", + tag, + estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), + (unsigned long)(sc->sc_back - sc->sc_ring), + (unsigned long)(sc->sc_front - sc->sc_ring)); +} + +static void +safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) +{ + int ix, nsegs; + + ix = re - sc->sc_ring; + printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" + , tag + , re, ix + , re->re_desc.d_csr + , re->re_desc.d_src + , re->re_desc.d_dst + , re->re_desc.d_sa + , re->re_desc.d_len + ); + if (re->re_src.nsegs > 1) { + ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / + sizeof(struct safe_pdesc); + for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { + printf(" spd[%u] %p: %p size %u flags %x" + , ix, &sc->sc_spring[ix] + , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr + , sc->sc_spring[ix].pd_size + , sc->sc_spring[ix].pd_flags + ); + if (sc->sc_spring[ix].pd_size == 0) + printf(" (zero!)"); + printf("\n"); + if (++ix == SAFE_TOTAL_SPART) + ix = 0; + } + } + if (re->re_dst.nsegs > 1) { + ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / + sizeof(struct safe_pdesc); + for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { + printf(" dpd[%u] %p: %p flags %x\n" + , ix, &sc->sc_dpring[ix] + , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr + , sc->sc_dpring[ix].pd_flags + ); + if (++ix == SAFE_TOTAL_DPART) + ix = 0; + } + } + printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", + re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); + printf("sa: key %x %x %x %x %x %x %x %x\n" + , re->re_sa.sa_key[0] + , re->re_sa.sa_key[1] + , re->re_sa.sa_key[2] + , re->re_sa.sa_key[3] + , re->re_sa.sa_key[4] + , re->re_sa.sa_key[5] + , re->re_sa.sa_key[6] + , re->re_sa.sa_key[7] + ); + printf("sa: indigest %x %x %x %x %x\n" + , re->re_sa.sa_indigest[0] + , re->re_sa.sa_indigest[1] + , re->re_sa.sa_indigest[2] + , re->re_sa.sa_indigest[3] + , re->re_sa.sa_indigest[4] + ); + printf("sa: outdigest %x %x %x %x %x\n" + , re->re_sa.sa_outdigest[0] + , re->re_sa.sa_outdigest[1] + , re->re_sa.sa_outdigest[2] + , re->re_sa.sa_outdigest[3] + , re->re_sa.sa_outdigest[4] + ); + printf("sr: iv %x %x %x %x\n" + , re->re_sastate.sa_saved_iv[0] + , re->re_sastate.sa_saved_iv[1] + , re->re_sastate.sa_saved_iv[2] + , re->re_sastate.sa_saved_iv[3] + ); + printf("sr: hashbc %u indigest %x %x %x %x %x\n" + , re->re_sastate.sa_saved_hashbc + , re->re_sastate.sa_saved_indigest[0] + , re->re_sastate.sa_saved_indigest[1] + , re->re_sastate.sa_saved_indigest[2] + , re->re_sastate.sa_saved_indigest[3] + , re->re_sastate.sa_saved_indigest[4] + ); +} + +static void +safe_dump_ring(struct safe_softc *sc, const char *tag) +{ + unsigned long flags; + + spin_lock_irqsave(&sc->sc_ringmtx, flags); + printf("\nSafeNet Ring State:\n"); + safe_dump_intrstate(sc, tag); + safe_dump_dmastatus(sc, tag); + safe_dump_ringstate(sc, tag); + if (sc->sc_nqchip) { + struct safe_ringentry *re = sc->sc_back; + do { + safe_dump_request(sc, tag, re); + if (++re == sc->sc_ringtop) + re = sc->sc_ring; + } while (re != sc->sc_front); + } + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); +} +#endif /* SAFE_DEBUG */ + + +static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) +{ + struct safe_softc *sc = NULL; + u32 mem_start, mem_len, cmd; + int i, rc, devinfo; + dma_addr_t raddr; + static int num_chips = 0; + + DPRINTF(("%s()\n", __FUNCTION__)); + + if (pci_enable_device(dev) < 0) + return(-ENODEV); + + if (!dev->irq) { + printk("safe: found device with no IRQ assigned. check BIOS settings!"); + pci_disable_device(dev); + return(-ENODEV); + } + + if (pci_set_mwi(dev)) { + printk("safe: pci_set_mwi failed!"); + return(-ENODEV); + } + + sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); + if (!sc) + return(-ENOMEM); + memset(sc, 0, sizeof(*sc)); + + softc_device_init(sc, "safe", num_chips, safe_methods); + + sc->sc_irq = -1; + sc->sc_cid = -1; + sc->sc_pcidev = dev; + if (num_chips < SAFE_MAX_CHIPS) { + safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; + num_chips++; + } + + INIT_LIST_HEAD(&sc->sc_pkq); + spin_lock_init(&sc->sc_pkmtx); + + pci_set_drvdata(sc->sc_pcidev, sc); + + /* we read its hardware registers as memory */ + mem_start = pci_resource_start(sc->sc_pcidev, 0); + mem_len = pci_resource_len(sc->sc_pcidev, 0); + + sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); + if (!sc->sc_base_addr) { + device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", + mem_start, mem_start + mem_len - 1); + goto out; + } + + /* fix up the bus size */ + if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { + device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); + goto out; + } + if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { + device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); + goto out; + } + + pci_set_master(sc->sc_pcidev); + + pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); + + if (!(cmd & PCI_COMMAND_MEMORY)) { + device_printf(sc->sc_dev, "failed to enable memory mapping\n"); + goto out; + } + + if (!(cmd & PCI_COMMAND_MASTER)) { + device_printf(sc->sc_dev, "failed to enable bus mastering\n"); + goto out; + } + + rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); + if (rc) { + device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); + goto out; + } + sc->sc_irq = dev->irq; + + sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & + (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); + + /* + * Allocate packet engine descriptors. + */ + sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, + SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), + &sc->sc_ringalloc.dma_paddr); + if (!sc->sc_ringalloc.dma_vaddr) { + device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); + goto out; + } + + /* + * Hookup the static portion of all our data structures. + */ + sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; + sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; + sc->sc_front = sc->sc_ring; + sc->sc_back = sc->sc_ring; + raddr = sc->sc_ringalloc.dma_paddr; + bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); + for (i = 0; i < SAFE_MAX_NQUEUE; i++) { + struct safe_ringentry *re = &sc->sc_ring[i]; + + re->re_desc.d_sa = raddr + + offsetof(struct safe_ringentry, re_sa); + re->re_sa.sa_staterec = raddr + + offsetof(struct safe_ringentry, re_sastate); + + raddr += sizeof (struct safe_ringentry); + } + spin_lock_init(&sc->sc_ringmtx); + + /* + * Allocate scatter and gather particle descriptors. + */ + sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, + SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), + &sc->sc_spalloc.dma_paddr); + if (!sc->sc_spalloc.dma_vaddr) { + device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); + goto out; + } + sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; + sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; + sc->sc_spfree = sc->sc_spring; + bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); + + sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, + SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), + &sc->sc_dpalloc.dma_paddr); + if (!sc->sc_dpalloc.dma_vaddr) { + device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); + goto out; + } + sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; + sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; + sc->sc_dpfree = sc->sc_dpring; + bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); + + sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); + if (sc->sc_cid < 0) { + device_printf(sc->sc_dev, "could not get crypto driver id\n"); + goto out; + } + + printf("%s:", device_get_nameunit(sc->sc_dev)); + + devinfo = READ_REG(sc, SAFE_DEVINFO); + if (devinfo & SAFE_DEVINFO_RNG) { + sc->sc_flags |= SAFE_FLAGS_RNG; + printf(" rng"); + } + if (devinfo & SAFE_DEVINFO_PKEY) { + printf(" key"); + sc->sc_flags |= SAFE_FLAGS_KEY; + crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); +#if 0 + crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); +#endif + init_timer(&sc->sc_pkto); + sc->sc_pkto.function = safe_kpoll; + sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); + } + if (devinfo & SAFE_DEVINFO_DES) { + printf(" des/3des"); + crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); + } + if (devinfo & SAFE_DEVINFO_AES) { + printf(" aes"); + crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); + } + if (devinfo & SAFE_DEVINFO_MD5) { + printf(" md5"); + crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); + } + if (devinfo & SAFE_DEVINFO_SHA1) { + printf(" sha1"); + crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); + } + printf(" null"); + crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); + /* XXX other supported algorithms */ + printf("\n"); + + safe_reset_board(sc); /* reset h/w */ + safe_init_board(sc); /* init h/w */ + +#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) + if (sc->sc_flags & SAFE_FLAGS_RNG) { + safe_rng_init(sc); + crypto_rregister(sc->sc_cid, safe_read_random, sc); + } +#endif /* SAFE_NO_RNG */ + + return (0); + +out: + if (sc->sc_cid >= 0) + crypto_unregister_all(sc->sc_cid); + if (sc->sc_irq != -1) + free_irq(sc->sc_irq, sc); + if (sc->sc_ringalloc.dma_vaddr) + pci_free_consistent(sc->sc_pcidev, + SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), + sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); + if (sc->sc_spalloc.dma_vaddr) + pci_free_consistent(sc->sc_pcidev, + SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), + sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); + if (sc->sc_dpalloc.dma_vaddr) + pci_free_consistent(sc->sc_pcidev, + SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), + sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); + kfree(sc); + return(-ENODEV); +} + +static void safe_remove(struct pci_dev *dev) +{ + struct safe_softc *sc = pci_get_drvdata(dev); + + DPRINTF(("%s()\n", __FUNCTION__)); + + /* XXX wait/abort active ops */ + + WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ + + del_timer_sync(&sc->sc_pkto); + + crypto_unregister_all(sc->sc_cid); + + safe_cleanchip(sc); + + if (sc->sc_irq != -1) + free_irq(sc->sc_irq, sc); + if (sc->sc_ringalloc.dma_vaddr) + pci_free_consistent(sc->sc_pcidev, + SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), + sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); + if (sc->sc_spalloc.dma_vaddr) + pci_free_consistent(sc->sc_pcidev, + SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), + sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); + if (sc->sc_dpalloc.dma_vaddr) + pci_free_consistent(sc->sc_pcidev, + SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), + sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); + sc->sc_irq = -1; + sc->sc_ringalloc.dma_vaddr = NULL; + sc->sc_spalloc.dma_vaddr = NULL; + sc->sc_dpalloc.dma_vaddr = NULL; +} + +static struct pci_device_id safe_pci_tbl[] = { + { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, + { }, +}; +MODULE_DEVICE_TABLE(pci, safe_pci_tbl); + +static struct pci_driver safe_driver = { + .name = "safe", + .id_table = safe_pci_tbl, + .probe = safe_probe, + .remove = safe_remove, + /* add PM stuff here one day */ +}; + +static int __init safe_init (void) +{ + struct safe_softc *sc = NULL; + int rc; + + DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); + + rc = pci_register_driver(&safe_driver); + pci_register_driver_compat(&safe_driver, rc); + + return rc; +} + +static void __exit safe_exit (void) +{ + pci_unregister_driver(&safe_driver); +} + +module_init(safe_init); +module_exit(safe_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("David McCullough "); +MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); diff --git a/target/linux/generic/files/crypto/ocf/safe/safereg.h b/target/linux/generic/files/crypto/ocf/safe/safereg.h new file mode 100644 index 0000000..dbaf98f --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/safereg.h @@ -0,0 +1,421 @@ +/*- + * Copyright (c) 2003 Sam Leffler, Errno Consulting + * Copyright (c) 2003 Global Technology Associates, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ + */ +#ifndef _SAFE_SAFEREG_H_ +#define _SAFE_SAFEREG_H_ + +/* + * Register definitions for SafeNet SafeXcel-1141 crypto device. + * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. + */ + +#define BS_BAR 0x10 /* DMA base address register */ +#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ +#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ + +#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ + +/* SafeNet */ +#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ + +#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ +#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ +#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ +#define SAFE_PE_SA 0x000c /* Packet Engine SA */ +#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ +#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ +#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ +#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ +#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ +#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ +#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ +#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ +#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ +#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ +#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ +#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ +#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ +#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ +#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ +#define SAFE_DEVID 0x0084 /* Device ID */ +#define SAFE_DEVINFO 0x0088 /* Device Info */ +#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ +#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ +#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ +#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ +#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ +#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ +#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ +#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ +#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ +#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ +#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ +#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ +#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ +#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ +#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ +#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ +#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ +#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ +#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ +#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ +#define SAFE_PK_FUNC 0x081c /* Public Key Function */ +#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ +#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ + +#define SAFE_RNG_OUT 0x0100 /* RNG Output */ +#define SAFE_RNG_STAT 0x0104 /* RNG Status */ +#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ +#define SAFE_RNG_A 0x010c /* RNG A */ +#define SAFE_RNG_B 0x0110 /* RNG B */ +#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ +#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ +#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ +#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ +#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ +#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ +#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ +#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ +#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ +#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ + +#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ +#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ +#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ +#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ +#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ +#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ +#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ +#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ +#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ +#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ +#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ +#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ +#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ +#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ +#define SAFE_PE_CSR_XECODE_S 20 +#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ +#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ +#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ +#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ +#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ +#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ +#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ +#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ +#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ +#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ +#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ +#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ +#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ +#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ +#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ + +/* + * Check the CSR to see if the PE has returned ownership to + * the host. Note that before processing a descriptor this + * must be done followed by a check of the SAFE_PE_LEN register + * status bits to avoid premature processing of a descriptor + * on its way back to the host. + */ +#define SAFE_PE_CSR_IS_DONE(_csr) \ + (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) + +#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ +#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ +#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ +#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ +#define SAFE_PE_LEN_BYPASS_S 24 + +#define SAFE_PE_LEN_IS_DONE(_len) \ + (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) + +/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ +#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ +#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ +#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ +#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ + +#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ +#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ +#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ + +#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ +#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ + +#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ +#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ +#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ +#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ +#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ +#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ +#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ +#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ +#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ +#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ +#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ +#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ +#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ +#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ +#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ +#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ +#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ + +#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ +#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ +#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ +#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ +#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ +#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ +#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ +#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ +#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ +#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ +#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ +#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ +#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ +#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ + +#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ +#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ +#define SAFE_PE_RINGCFG_OFFSET_S 16 + +#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ +#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ +#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ + +#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ + +#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ +#define SAFE_PE_ERNGSTAT_NEXT_S 16 + +#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ +#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ + +#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ +#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ +#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 +#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 +#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 +#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 +#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ +#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 +#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 +#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 +#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 + +#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ +#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ + +#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ +#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ +#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ + +#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ +#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ +#define SAFE_DEVINFO_REV_MAJ_S 4 +#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ +#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ +#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ +#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ +#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ +#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ +#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ +#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ +#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ +#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ +#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ + +#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) +#define SAFE_REV_MAJ(_chiprev) \ + (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) +#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) + +#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ +#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ +#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ +#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ +#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ +#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ +#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ +#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ +#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ +#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ +#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ +#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ + +#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ + +#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ +#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ +#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ +#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ +#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ +#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ +#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ +#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ +#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ +#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ + +/* + * Packet engine descriptor. Note that d_csr is a copy of the + * SAFE_PE_CSR register and all definitions apply, and d_len + * is a copy of the SAFE_PE_LEN register and all definitions apply. + * d_src and d_len may point directly to contiguous data or to a + * list of ``particle descriptors'' when using scatter/gather i/o. + */ +struct safe_desc { + u_int32_t d_csr; /* per-packet control/status */ + u_int32_t d_src; /* source address */ + u_int32_t d_dst; /* destination address */ + u_int32_t d_sa; /* SA address */ + u_int32_t d_len; /* length, bypass, status */ +}; + +/* + * Scatter/Gather particle descriptor. + * + * NB: scatter descriptors do not specify a size; this is fixed + * by the setting of the SAFE_PE_PARTCFG register. + */ +struct safe_pdesc { + u_int32_t pd_addr; /* particle address */ +#ifdef __BIG_ENDIAN + u_int16_t pd_flags; /* control word */ + u_int16_t pd_size; /* particle size (bytes) */ +#else + u_int16_t pd_flags; /* control word */ + u_int16_t pd_size; /* particle size (bytes) */ +#endif +}; + +#define SAFE_PD_READY 0x0001 /* ready for processing */ +#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ + +/* + * Security Association (SA) Record (Rev 1). One of these is + * required for each operation processed by the packet engine. + */ +struct safe_sarec { + u_int32_t sa_cmd0; + u_int32_t sa_cmd1; + u_int32_t sa_resv0; + u_int32_t sa_resv1; + u_int32_t sa_key[8]; /* DES/3DES/AES key */ + u_int32_t sa_indigest[5]; /* inner digest */ + u_int32_t sa_outdigest[5]; /* outer digest */ + u_int32_t sa_spi; /* SPI */ + u_int32_t sa_seqnum; /* sequence number */ + u_int32_t sa_seqmask[2]; /* sequence number mask */ + u_int32_t sa_resv2; + u_int32_t sa_staterec; /* address of state record */ + u_int32_t sa_resv3[2]; + u_int32_t sa_samgmt0; /* SA management field 0 */ + u_int32_t sa_samgmt1; /* SA management field 0 */ +}; + +#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ +#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ +#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ +#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ +#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ +#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ +#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ +#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ +#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ +#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ +#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ +#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ +#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ +#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ +#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ +#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ +#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ +#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ +#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ +#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ +#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ +#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ +#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ +#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ +#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ +#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ +#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ +#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ +#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ +#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ +#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ +#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ +#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ +#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ +#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ +#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ +#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ +#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ +#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ +#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ +#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ +#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ +#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ + +#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ +#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ +#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ +#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ +#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ +#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ +#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ +#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ +#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ +#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ +#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ +#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ +#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ +#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ +#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ +#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ +#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ +#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ +#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ +#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS +#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ +#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ +#define SAFE_SA_CMD1_OFFSET_S 16 +#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ +#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ +#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ +#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ + +/* + * Security Associate State Record (Rev 1). + */ +struct safe_sastate { + u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ + u_int32_t sa_saved_hashbc; /* saved hash byte count */ + u_int32_t sa_saved_indigest[5]; /* saved inner digest */ +}; +#endif /* _SAFE_SAFEREG_H_ */ diff --git a/target/linux/generic/files/crypto/ocf/safe/safevar.h b/target/linux/generic/files/crypto/ocf/safe/safevar.h new file mode 100644 index 0000000..11d8304 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/safevar.h @@ -0,0 +1,229 @@ +/*- + * The linux port of this code done by David McCullough + * Copyright (C) 2004-2010 David McCullough + * The license and original author are listed below. + * + * Copyright (c) 2003 Sam Leffler, Errno Consulting + * Copyright (c) 2003 Global Technology Associates, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ + */ +#ifndef _SAFE_SAFEVAR_H_ +#define _SAFE_SAFEVAR_H_ + +/* Maximum queue length */ +#ifndef SAFE_MAX_NQUEUE +#define SAFE_MAX_NQUEUE 60 +#endif + +#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ +#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ +#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ +#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ +#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ +/* total src+dst particle descriptors */ +#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) +#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) + +#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ + +#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) +#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) +#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) + +#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ +#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ +#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ + +#ifdef __KERNEL__ +/* + * State associated with the allocation of each chunk + * of memory setup for DMA. + */ +struct safe_dma_alloc { + dma_addr_t dma_paddr; + void *dma_vaddr; +}; + +/* + * Cryptographic operand state. One of these exists for each + * source and destination operand passed in from the crypto + * subsystem. When possible source and destination operands + * refer to the same memory. More often they are distinct. + * We track the virtual address of each operand as well as + * where each is mapped for DMA. + */ +struct safe_operand { + union { + struct sk_buff *skb; + struct uio *io; + } u; + void *map; + int mapsize; /* total number of bytes in segs */ + struct { + dma_addr_t ds_addr; + int ds_len; + int ds_tlen; + } segs[SAFE_MAX_PART]; + int nsegs; +}; + +/* + * Packet engine ring entry and cryptographic operation state. + * The packet engine requires a ring of descriptors that contain + * pointers to various cryptographic state. However the ring + * configuration register allows you to specify an arbitrary size + * for ring entries. We use this feature to collect most of the + * state for each cryptographic request into one spot. Other than + * ring entries only the ``particle descriptors'' (scatter/gather + * lists) and the actual operand data are kept separate. The + * particle descriptors must also be organized in rings. The + * operand data can be located aribtrarily (modulo alignment constraints). + * + * Note that the descriptor ring is mapped onto the PCI bus so + * the hardware can DMA data. This means the entire ring must be + * contiguous. + */ +struct safe_ringentry { + struct safe_desc re_desc; /* command descriptor */ + struct safe_sarec re_sa; /* SA record */ + struct safe_sastate re_sastate; /* SA state record */ + + struct cryptop *re_crp; /* crypto operation */ + + struct safe_operand re_src; /* source operand */ + struct safe_operand re_dst; /* destination operand */ + + int re_sesn; /* crypto session ID */ + int re_flags; +#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ +#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ +}; + +#define re_src_skb re_src.u.skb +#define re_src_io re_src.u.io +#define re_src_map re_src.map +#define re_src_nsegs re_src.nsegs +#define re_src_segs re_src.segs +#define re_src_mapsize re_src.mapsize + +#define re_dst_skb re_dst.u.skb +#define re_dst_io re_dst.u.io +#define re_dst_map re_dst.map +#define re_dst_nsegs re_dst.nsegs +#define re_dst_segs re_dst.segs +#define re_dst_mapsize re_dst.mapsize + +struct rndstate_test; + +struct safe_session { + u_int32_t ses_used; + u_int32_t ses_klen; /* key length in bits */ + u_int32_t ses_key[8]; /* DES/3DES/AES key */ + u_int32_t ses_mlen; /* hmac length in bytes */ + u_int32_t ses_hminner[5]; /* hmac inner state */ + u_int32_t ses_hmouter[5]; /* hmac outer state */ +}; + +struct safe_pkq { + struct list_head pkq_list; + struct cryptkop *pkq_krp; +}; + +struct safe_softc { + softc_device_decl sc_dev; + u32 sc_irq; + + struct pci_dev *sc_pcidev; + ocf_iomem_t sc_base_addr; + + u_int sc_chiprev; /* major/minor chip revision */ + int sc_flags; /* device specific flags */ +#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ +#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ + int sc_suspended; + int sc_needwakeup; /* notify crypto layer */ + int32_t sc_cid; /* crypto tag */ + + struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ + struct safe_ringentry *sc_ring; /* PE ring */ + struct safe_ringentry *sc_ringtop; /* PE ring top */ + struct safe_ringentry *sc_front; /* next free entry */ + struct safe_ringentry *sc_back; /* next pending entry */ + int sc_nqchip; /* # passed to chip */ + spinlock_t sc_ringmtx; /* PE ring lock */ + struct safe_pdesc *sc_spring; /* src particle ring */ + struct safe_pdesc *sc_springtop; /* src particle ring top */ + struct safe_pdesc *sc_spfree; /* next free src particle */ + struct safe_dma_alloc sc_spalloc; /* src particle ring state */ + struct safe_pdesc *sc_dpring; /* dest particle ring */ + struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ + struct safe_pdesc *sc_dpfree; /* next free dest particle */ + struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ + int sc_nsessions; /* # of sessions */ + struct safe_session *sc_sessions; /* sessions */ + + struct timer_list sc_pkto; /* PK polling */ + spinlock_t sc_pkmtx; /* PK lock */ + struct list_head sc_pkq; /* queue of PK requests */ + struct safe_pkq *sc_pkq_cur; /* current processing request */ + u_int32_t sc_pk_reslen, sc_pk_resoff; + + int sc_max_dsize; /* maximum safe DMA size */ +}; +#endif /* __KERNEL__ */ + +struct safe_stats { + u_int64_t st_ibytes; + u_int64_t st_obytes; + u_int32_t st_ipackets; + u_int32_t st_opackets; + u_int32_t st_invalid; /* invalid argument */ + u_int32_t st_badsession; /* invalid session id */ + u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ + u_int32_t st_nodesc; /* op submitted w/o descriptors */ + u_int32_t st_badalg; /* unsupported algorithm */ + u_int32_t st_ringfull; /* PE descriptor ring full */ + u_int32_t st_peoperr; /* PE marked error */ + u_int32_t st_dmaerr; /* PE DMA error */ + u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ + u_int32_t st_skipmismatch; /* enc part begins before auth part */ + u_int32_t st_lenmismatch; /* enc length different auth length */ + u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ + u_int32_t st_cofftoobig; /* crypto offset > 255 words */ + u_int32_t st_iovmisaligned; /* iov op not aligned */ + u_int32_t st_iovnotuniform; /* iov op not suitable */ + u_int32_t st_unaligned; /* unaligned src caused copy */ + u_int32_t st_notuniform; /* non-uniform src caused copy */ + u_int32_t st_nomap; /* bus_dmamap_create failed */ + u_int32_t st_noload; /* bus_dmamap_load_* failed */ + u_int32_t st_nombuf; /* MGET* failed */ + u_int32_t st_nomcl; /* MCLGET* failed */ + u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ + u_int32_t st_rng; /* RNG requests */ + u_int32_t st_rngalarm; /* RNG alarm requests */ + u_int32_t st_noicvcopy; /* ICV data copies suppressed */ +}; +#endif /* _SAFE_SAFEVAR_H_ */ diff --git a/target/linux/generic/files/crypto/ocf/safe/sha1.c b/target/linux/generic/files/crypto/ocf/safe/sha1.c new file mode 100644 index 0000000..4e360e2 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/sha1.c @@ -0,0 +1,279 @@ +/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ +/* + * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) + * based on: http://csrc.nist.gov/fips/fip180-1.txt + * implemented by Jun-ichiro itojun Itoh + */ + +#if 0 +#include +__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); + +#include +#include +#include +#include + +#include +#endif + +/* sanity check */ +#if BYTE_ORDER != BIG_ENDIAN +# if BYTE_ORDER != LITTLE_ENDIAN +# define unsupported 1 +# endif +#endif + +#ifndef unsupported + +/* constant table */ +static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; +#define K(t) _K[(t) / 20] + +#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) +#define F1(b, c, d) (((b) ^ (c)) ^ (d)) +#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) +#define F3(b, c, d) (((b) ^ (c)) ^ (d)) + +#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) + +#undef H +#define H(n) (ctxt->h.b32[(n)]) +#define COUNT (ctxt->count) +#define BCOUNT (ctxt->c.b64[0] / 8) +#define W(n) (ctxt->m.b32[(n)]) + +#define PUTBYTE(x) { \ + ctxt->m.b8[(COUNT % 64)] = (x); \ + COUNT++; \ + COUNT %= 64; \ + ctxt->c.b64[0] += 8; \ + if (COUNT % 64 == 0) \ + sha1_step(ctxt); \ + } + +#define PUTPAD(x) { \ + ctxt->m.b8[(COUNT % 64)] = (x); \ + COUNT++; \ + COUNT %= 64; \ + if (COUNT % 64 == 0) \ + sha1_step(ctxt); \ + } + +static void sha1_step(struct sha1_ctxt *); + +static void +sha1_step(ctxt) + struct sha1_ctxt *ctxt; +{ + u_int32_t a, b, c, d, e; + size_t t, s; + u_int32_t tmp; + +#if BYTE_ORDER == LITTLE_ENDIAN + struct sha1_ctxt tctxt; + bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); + ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; + ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; + ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; + ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; + ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; + ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; + ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; + ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; + ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; + ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; + ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; + ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; + ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; + ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; + ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; + ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; + ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; + ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; + ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; + ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; + ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; + ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; + ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; + ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; + ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; + ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; + ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; + ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; + ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; + ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; + ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; + ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; +#endif + + a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); + + for (t = 0; t < 20; t++) { + s = t & 0x0f; + if (t >= 16) { + W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); + } + tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); + e = d; d = c; c = S(30, b); b = a; a = tmp; + } + for (t = 20; t < 40; t++) { + s = t & 0x0f; + W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); + tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); + e = d; d = c; c = S(30, b); b = a; a = tmp; + } + for (t = 40; t < 60; t++) { + s = t & 0x0f; + W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); + tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); + e = d; d = c; c = S(30, b); b = a; a = tmp; + } + for (t = 60; t < 80; t++) { + s = t & 0x0f; + W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); + tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); + e = d; d = c; c = S(30, b); b = a; a = tmp; + } + + H(0) = H(0) + a; + H(1) = H(1) + b; + H(2) = H(2) + c; + H(3) = H(3) + d; + H(4) = H(4) + e; + + bzero(&ctxt->m.b8[0], 64); +} + +/*------------------------------------------------------------*/ + +void +sha1_init(ctxt) + struct sha1_ctxt *ctxt; +{ + bzero(ctxt, sizeof(struct sha1_ctxt)); + H(0) = 0x67452301; + H(1) = 0xefcdab89; + H(2) = 0x98badcfe; + H(3) = 0x10325476; + H(4) = 0xc3d2e1f0; +} + +void +sha1_pad(ctxt) + struct sha1_ctxt *ctxt; +{ + size_t padlen; /*pad length in bytes*/ + size_t padstart; + + PUTPAD(0x80); + + padstart = COUNT % 64; + padlen = 64 - padstart; + if (padlen < 8) { + bzero(&ctxt->m.b8[padstart], padlen); + COUNT += padlen; + COUNT %= 64; + sha1_step(ctxt); + padstart = COUNT % 64; /* should be 0 */ + padlen = 64 - padstart; /* should be 64 */ + } + bzero(&ctxt->m.b8[padstart], padlen - 8); + COUNT += (padlen - 8); + COUNT %= 64; +#if BYTE_ORDER == BIG_ENDIAN + PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); + PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); + PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); + PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); +#else + PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); + PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); + PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); + PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); +#endif +} + +void +sha1_loop(ctxt, input, len) + struct sha1_ctxt *ctxt; + const u_int8_t *input; + size_t len; +{ + size_t gaplen; + size_t gapstart; + size_t off; + size_t copysiz; + + off = 0; + + while (off < len) { + gapstart = COUNT % 64; + gaplen = 64 - gapstart; + + copysiz = (gaplen < len - off) ? gaplen : len - off; + bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); + COUNT += copysiz; + COUNT %= 64; + ctxt->c.b64[0] += copysiz * 8; + if (COUNT % 64 == 0) + sha1_step(ctxt); + off += copysiz; + } +} + +void +sha1_result(ctxt, digest0) + struct sha1_ctxt *ctxt; + caddr_t digest0; +{ + u_int8_t *digest; + + digest = (u_int8_t *)digest0; + sha1_pad(ctxt); +#if BYTE_ORDER == BIG_ENDIAN + bcopy(&ctxt->h.b8[0], digest, 20); +#else + digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; + digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; + digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; + digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; + digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; + digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; + digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; + digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; + digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; + digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; +#endif +} + +#endif /*unsupported*/ diff --git a/target/linux/generic/files/crypto/ocf/safe/sha1.h b/target/linux/generic/files/crypto/ocf/safe/sha1.h new file mode 100644 index 0000000..0e19d90 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/safe/sha1.h @@ -0,0 +1,72 @@ +/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ +/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ + +/* + * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +/* + * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) + * based on: http://csrc.nist.gov/fips/fip180-1.txt + * implemented by Jun-ichiro itojun Itoh + */ + +#ifndef _NETINET6_SHA1_H_ +#define _NETINET6_SHA1_H_ + +struct sha1_ctxt { + union { + u_int8_t b8[20]; + u_int32_t b32[5]; + } h; + union { + u_int8_t b8[8]; + u_int64_t b64[1]; + } c; + union { + u_int8_t b8[64]; + u_int32_t b32[16]; + } m; + u_int8_t count; +}; + +#ifdef __KERNEL__ +extern void sha1_init(struct sha1_ctxt *); +extern void sha1_pad(struct sha1_ctxt *); +extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); +extern void sha1_result(struct sha1_ctxt *, caddr_t); + +/* compatibilty with other SHA1 source codes */ +typedef struct sha1_ctxt SHA1_CTX; +#define SHA1Init(x) sha1_init((x)) +#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) +#define SHA1Final(x, y) sha1_result((y), (x)) +#endif /* __KERNEL__ */ + +#define SHA1_RESULTLEN (160/8) + +#endif /*_NETINET6_SHA1_H_*/ diff --git a/target/linux/generic/files/crypto/ocf/talitos/Makefile b/target/linux/generic/files/crypto/ocf/talitos/Makefile new file mode 100644 index 0000000..2591b8a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/talitos/Makefile @@ -0,0 +1,12 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_TALITOS) += talitos.o + +obj ?= . +EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/talitos/talitos.c b/target/linux/generic/files/crypto/ocf/talitos/talitos.c new file mode 100644 index 0000000..c4bc8c0 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/talitos/talitos.c @@ -0,0 +1,1355 @@ +/* + * crypto/ocf/talitos/talitos.c + * + * An OCF-Linux module that uses Freescale's SEC to do the crypto. + * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers + * + * Copyright (c) 2006 Freescale Semiconductor, Inc. + * + * This code written by Kim A. B. Phillips + * some code copied from files with the following: + * Copyright (C) 2004-2007 David McCullough + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * --------------------------------------------------------------------------- + * + * NOTES: + * + * The Freescale SEC (also known as 'talitos') resides on the + * internal bus, and runs asynchronous to the processor core. It has + * a wide gamut of cryptographic acceleration features, including single- + * pass IPsec (also known as algorithm chaining). To properly utilize + * all of the SEC's performance enhancing features, further reworking + * of higher level code (framework, applications) will be necessary. + * + * The following table shows which SEC version is present in which devices: + * + * Devices SEC version + * + * 8272, 8248 SEC 1.0 + * 885, 875 SEC 1.2 + * 8555E, 8541E SEC 2.0 + * 8349E SEC 2.01 + * 8548E SEC 2.1 + * + * The following table shows the features offered by each SEC version: + * + * Max. chan- + * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU + * + * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 + * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 + * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 + * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 + * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 + * + * Each execution unit in the SEC has two modes of execution; channel and + * slave/debug. This driver employs the channel infrastructure in the + * device for convenience. Only the RNG is directly accessed due to the + * convenience of its random fifo pool. The relationship between the + * channels and execution units is depicted in the following diagram: + * + * ------- ------------ + * ---| ch0 |---| | + * ------- | | + * | |------+-------+-------+-------+------------ + * ------- | | | | | | | + * ---| ch1 |---| | | | | | | + * ------- | | ------ ------ ------ ------ ------ + * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | + * ------- | | ------ ------ ------ ------ ------ + * ---| ch2 |---| | | | | | | + * ------- | | | | | | | + * | |------+-------+-------+-------+------------ + * ------- | | + * ---| ch3 |---| | + * ------- ------------ + * + * Channel ch0 may drive an aes operation to the aes unit (AESU), + * and, at the same time, ch1 may drive a message digest operation + * to the mdeu. Each channel has an input descriptor FIFO, and the + * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a + * a buffer overrun error is triggered. The controller is responsible + * for fetching the data from descriptor pointers, and passing the + * data to the appropriate EUs. The controller also writes the + * cryptographic operation's result to memory. The SEC notifies + * completion by triggering an interrupt and/or setting the 1st byte + * of the hdr field to 0xff. + * + * TODO: + * o support more algorithms + * o support more versions of the SEC + * o add support for linux 2.4 + * o scatter-gather (sg) support + * o add support for public key ops (PKEU) + * o add statistics + */ + +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include /* dma_map_single() */ +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) +#include +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) +#include +#endif + +#include +#include + +#define DRV_NAME "talitos" + +#include "talitos_dev.h" +#include "talitos_soft.h" + +#define read_random(p,l) get_random_bytes(p,l) + +const char talitos_driver_name[] = "Talitos OCF"; +const char talitos_driver_version[] = "0.2"; + +static int talitos_newsession(device_t dev, u_int32_t *sidp, + struct cryptoini *cri); +static int talitos_freesession(device_t dev, u_int64_t tid); +static int talitos_process(device_t dev, struct cryptop *crp, int hint); +static void dump_talitos_status(struct talitos_softc *sc); +static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, + int chsel); +static void talitos_doneprocessing(struct talitos_softc *sc); +static void talitos_init_device(struct talitos_softc *sc); +static void talitos_reset_device_master(struct talitos_softc *sc); +static void talitos_reset_device(struct talitos_softc *sc); +static void talitos_errorprocessing(struct talitos_softc *sc); +#ifdef CONFIG_PPC_MERGE +static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); +static int talitos_remove(struct of_device *ofdev); +#else +static int talitos_probe(struct platform_device *pdev); +static int talitos_remove(struct platform_device *pdev); +#endif +#ifdef CONFIG_OCF_RANDOMHARVEST +static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); +static void talitos_rng_init(struct talitos_softc *sc); +#endif + +static device_method_t talitos_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, talitos_newsession), + DEVMETHOD(cryptodev_freesession,talitos_freesession), + DEVMETHOD(cryptodev_process, talitos_process), +}; + +#define debug talitos_debug +int talitos_debug = 0; +module_param(talitos_debug, int, 0644); +MODULE_PARM_DESC(talitos_debug, "Enable debug"); + +static inline void talitos_write(volatile unsigned *addr, u32 val) +{ + out_be32(addr, val); +} + +static inline u32 talitos_read(volatile unsigned *addr) +{ + u32 val; + val = in_be32(addr); + return val; +} + +static void dump_talitos_status(struct talitos_softc *sc) +{ + unsigned int v, v_hi, i, *ptr; + v = talitos_read(sc->sc_base_addr + TALITOS_MCR); + v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); + printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", + device_get_nameunit(sc->sc_cdev), v, v_hi); + v = talitos_read(sc->sc_base_addr + TALITOS_IMR); + v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); + printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", + device_get_nameunit(sc->sc_cdev), v, v_hi); + v = talitos_read(sc->sc_base_addr + TALITOS_ISR); + v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); + printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", + device_get_nameunit(sc->sc_cdev), v, v_hi); + for (i = 0; i < sc->sc_num_channels; i++) { + v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + + TALITOS_CH_CDPR); + v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + + TALITOS_CH_CDPR_HI); + printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", + device_get_nameunit(sc->sc_cdev), i, v, v_hi); + } + for (i = 0; i < sc->sc_num_channels; i++) { + v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + + TALITOS_CH_CCPSR); + v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + + TALITOS_CH_CCPSR_HI); + printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", + device_get_nameunit(sc->sc_cdev), i, v, v_hi); + } + ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; + for (i = 0; i < 16; i++) { + v = talitos_read(ptr++); v_hi = talitos_read(ptr++); + printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", + device_get_nameunit(sc->sc_cdev), v, v_hi, i); + } + return; +} + + +#ifdef CONFIG_OCF_RANDOMHARVEST +/* + * pull random numbers off the RNG FIFO, not exceeding amount available + */ +static int +talitos_read_random(void *arg, u_int32_t *buf, int maxwords) +{ + struct talitos_softc *sc = (struct talitos_softc *) arg; + int rc; + u_int32_t v; + + DPRINTF("%s()\n", __FUNCTION__); + + /* check for things like FIFO underflow */ + v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); + if (unlikely(v)) { + printk(KERN_ERR "%s: RNGISR_HI error %08x\n", + device_get_nameunit(sc->sc_cdev), v); + return 0; + } + /* + * OFL is number of available 64-bit words, + * shift and convert to a 32-bit word count + */ + v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); + v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); + if (maxwords > v) + maxwords = v; + for (rc = 0; rc < maxwords; rc++) { + buf[rc] = talitos_read(sc->sc_base_addr + + TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); + } + if (maxwords & 1) { + /* + * RNG will complain with an AE in the RNGISR + * if we don't complete the pairs of 32-bit reads + * to its 64-bit register based FIFO + */ + v = talitos_read(sc->sc_base_addr + + TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); + } + + return rc; +} + +static void +talitos_rng_init(struct talitos_softc *sc) +{ + u_int32_t v; + + DPRINTF("%s()\n", __FUNCTION__); + /* reset RNG EU */ + v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); + v |= TALITOS_RNGRCR_HI_SR; + talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); + while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) + & TALITOS_RNGSR_HI_RD) == 0) + cpu_relax(); + /* + * we tell the RNG to start filling the RNG FIFO + * by writing the RNGDSR + */ + v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); + talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); + /* + * 64 bits of data will be pushed onto the FIFO every + * 256 SEC cycles until the FIFO is full. The RNG then + * attempts to keep the FIFO full. + */ + v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); + if (v) { + printk(KERN_ERR "%s: RNGISR_HI error %08x\n", + device_get_nameunit(sc->sc_cdev), v); + return; + } + /* + * n.b. we need to add a FIPS test here - if the RNG is going + * to fail, it's going to fail at reset time + */ + return; +} +#endif /* CONFIG_OCF_RANDOMHARVEST */ + +/* + * Generate a new software session. + */ +static int +talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) +{ + struct cryptoini *c, *encini = NULL, *macini = NULL; + struct talitos_softc *sc = device_get_softc(dev); + struct talitos_session *ses = NULL; + int sesn; + + DPRINTF("%s()\n", __FUNCTION__); + if (sidp == NULL || cri == NULL || sc == NULL) { + DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); + return EINVAL; + } + for (c = cri; c != NULL; c = c->cri_next) { + if (c->cri_alg == CRYPTO_MD5 || + c->cri_alg == CRYPTO_MD5_HMAC || + c->cri_alg == CRYPTO_SHA1 || + c->cri_alg == CRYPTO_SHA1_HMAC || + c->cri_alg == CRYPTO_NULL_HMAC) { + if (macini) + return EINVAL; + macini = c; + } else if (c->cri_alg == CRYPTO_DES_CBC || + c->cri_alg == CRYPTO_3DES_CBC || + c->cri_alg == CRYPTO_AES_CBC || + c->cri_alg == CRYPTO_NULL_CBC) { + if (encini) + return EINVAL; + encini = c; + } else { + DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); + return EINVAL; + } + } + if (encini == NULL && macini == NULL) + return EINVAL; + if (encini) { + /* validate key length */ + switch (encini->cri_alg) { + case CRYPTO_DES_CBC: + if (encini->cri_klen != 64) + return EINVAL; + break; + case CRYPTO_3DES_CBC: + if (encini->cri_klen != 192) { + return EINVAL; + } + break; + case CRYPTO_AES_CBC: + if (encini->cri_klen != 128 && + encini->cri_klen != 192 && + encini->cri_klen != 256) + return EINVAL; + break; + default: + DPRINTF("UNKNOWN encini->cri_alg %d\n", + encini->cri_alg); + return EINVAL; + } + } + + if (sc->sc_sessions == NULL) { + ses = sc->sc_sessions = (struct talitos_session *) + kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); + if (ses == NULL) + return ENOMEM; + memset(ses, 0, sizeof(struct talitos_session)); + sesn = 0; + sc->sc_nsessions = 1; + } else { + for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { + if (sc->sc_sessions[sesn].ses_used == 0) { + ses = &sc->sc_sessions[sesn]; + break; + } + } + + if (ses == NULL) { + /* allocating session */ + sesn = sc->sc_nsessions; + ses = (struct talitos_session *) kmalloc( + (sesn + 1) * sizeof(struct talitos_session), + SLAB_ATOMIC); + if (ses == NULL) + return ENOMEM; + memset(ses, 0, + (sesn + 1) * sizeof(struct talitos_session)); + memcpy(ses, sc->sc_sessions, + sesn * sizeof(struct talitos_session)); + memset(sc->sc_sessions, 0, + sesn * sizeof(struct talitos_session)); + kfree(sc->sc_sessions); + sc->sc_sessions = ses; + ses = &sc->sc_sessions[sesn]; + sc->sc_nsessions++; + } + } + + ses->ses_used = 1; + + if (encini) { + ses->ses_klen = (encini->cri_klen + 7) / 8; + memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); + if (macini) { + /* doing hash on top of cipher */ + ses->ses_hmac_len = (macini->cri_klen + 7) / 8; + memcpy(ses->ses_hmac, macini->cri_key, + ses->ses_hmac_len); + } + } else if (macini) { + /* doing hash */ + ses->ses_klen = (macini->cri_klen + 7) / 8; + memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); + } + + /* back compat way of determining MSC result len */ + if (macini) { + ses->ses_mlen = macini->cri_mlen; + if (ses->ses_mlen == 0) { + if (macini->cri_alg == CRYPTO_MD5_HMAC) + ses->ses_mlen = MD5_HASH_LEN; + else + ses->ses_mlen = SHA1_HASH_LEN; + } + } + + /* really should make up a template td here, + * and only fill things like i/o and direction in process() */ + + /* assign session ID */ + *sidp = TALITOS_SID(sc->sc_num, sesn); + return 0; +} + +/* + * Deallocate a session. + */ +static int +talitos_freesession(device_t dev, u_int64_t tid) +{ + struct talitos_softc *sc = device_get_softc(dev); + int session, ret; + u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; + + if (sc == NULL) + return EINVAL; + session = TALITOS_SESSION(sid); + if (session < sc->sc_nsessions) { + memset(&sc->sc_sessions[session], 0, + sizeof(sc->sc_sessions[session])); + ret = 0; + } else + ret = EINVAL; + return ret; +} + +/* + * launch device processing - it will come back with done notification + * in the form of an interrupt and/or HDR_DONE_BITS in header + */ +static int +talitos_submit( + struct talitos_softc *sc, + struct talitos_desc *td, + int chsel) +{ + u_int32_t v; + + v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); + talitos_write(sc->sc_base_addr + + chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); + talitos_write(sc->sc_base_addr + + chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); + return 0; +} + +static int +talitos_process(device_t dev, struct cryptop *crp, int hint) +{ + int i, err = 0, ivsize; + struct talitos_softc *sc = device_get_softc(dev); + struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; + caddr_t iv; + struct talitos_session *ses; + struct talitos_desc *td; + unsigned long flags; + /* descriptor mappings */ + int hmac_key, hmac_data, cipher_iv, cipher_key, + in_fifo, out_fifo, cipher_iv_out; + static int chsel = -1; + u_int32_t rand_iv[4]; + + DPRINTF("%s()\n", __FUNCTION__); + + if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { + return EINVAL; + } + crp->crp_etype = 0; + if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { + return EINVAL; + } + + ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; + + /* enter the channel scheduler */ + spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); + + /* reuse channel that already had/has requests for the required EU */ + for (i = 0; i < sc->sc_num_channels; i++) { + if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) + break; + } + if (i == sc->sc_num_channels) { + /* + * haven't seen this algo the last sc_num_channels or more + * use round robin in this case + * nb: sc->sc_num_channels must be power of 2 + */ + chsel = (chsel + 1) & (sc->sc_num_channels - 1); + } else { + /* + * matches channel with same target execution unit; + * use same channel in this case + */ + chsel = i; + } + sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; + + /* release the channel scheduler lock */ + spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); + + /* acquire the selected channel fifo lock */ + spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); + + /* find and reserve next available descriptor-cryptop pair */ + for (i = 0; i < sc->sc_chfifo_len; i++) { + if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { + /* + * ensure correct descriptor formation by + * avoiding inadvertently setting "optional" entries + * e.g. not using "optional" dptr2 for MD/HMAC descs + */ + memset(&sc->sc_chnfifo[chsel][i].cf_desc, + 0, sizeof(*td)); + /* reserve it with done notification request bit */ + sc->sc_chnfifo[chsel][i].cf_desc.hdr |= + TALITOS_DONE_NOTIFY; + break; + } + } + spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); + + if (i == sc->sc_chfifo_len) { + /* fifo full */ + err = ERESTART; + goto errout; + } + + td = &sc->sc_chnfifo[chsel][i].cf_desc; + sc->sc_chnfifo[chsel][i].cf_crp = crp; + + crd1 = crp->crp_desc; + if (crd1 == NULL) { + err = EINVAL; + goto errout; + } + crd2 = crd1->crd_next; + /* prevent compiler warning */ + hmac_key = 0; + hmac_data = 0; + if (crd2 == NULL) { + td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; + /* assign descriptor dword ptr mappings for this desc. type */ + cipher_iv = 1; + cipher_key = 2; + in_fifo = 3; + cipher_iv_out = 5; + if (crd1->crd_alg == CRYPTO_MD5_HMAC || + crd1->crd_alg == CRYPTO_SHA1_HMAC || + crd1->crd_alg == CRYPTO_SHA1 || + crd1->crd_alg == CRYPTO_MD5) { + out_fifo = 5; + maccrd = crd1; + enccrd = NULL; + } else if (crd1->crd_alg == CRYPTO_DES_CBC || + crd1->crd_alg == CRYPTO_3DES_CBC || + crd1->crd_alg == CRYPTO_AES_CBC || + crd1->crd_alg == CRYPTO_ARC4) { + out_fifo = 4; + maccrd = NULL; + enccrd = crd1; + } else { + DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); + err = EINVAL; + goto errout; + } + } else { + if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { + td->hdr |= TD_TYPE_IPSEC_ESP; + } else { + DPRINTF("unimplemented: multiple descriptor ipsec\n"); + err = EINVAL; + goto errout; + } + /* assign descriptor dword ptr mappings for this desc. type */ + hmac_key = 0; + hmac_data = 1; + cipher_iv = 2; + cipher_key = 3; + in_fifo = 4; + out_fifo = 5; + cipher_iv_out = 6; + if ((crd1->crd_alg == CRYPTO_MD5_HMAC || + crd1->crd_alg == CRYPTO_SHA1_HMAC || + crd1->crd_alg == CRYPTO_MD5 || + crd1->crd_alg == CRYPTO_SHA1) && + (crd2->crd_alg == CRYPTO_DES_CBC || + crd2->crd_alg == CRYPTO_3DES_CBC || + crd2->crd_alg == CRYPTO_AES_CBC || + crd2->crd_alg == CRYPTO_ARC4) && + ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { + maccrd = crd1; + enccrd = crd2; + } else if ((crd1->crd_alg == CRYPTO_DES_CBC || + crd1->crd_alg == CRYPTO_ARC4 || + crd1->crd_alg == CRYPTO_3DES_CBC || + crd1->crd_alg == CRYPTO_AES_CBC) && + (crd2->crd_alg == CRYPTO_MD5_HMAC || + crd2->crd_alg == CRYPTO_SHA1_HMAC || + crd2->crd_alg == CRYPTO_MD5 || + crd2->crd_alg == CRYPTO_SHA1) && + (crd1->crd_flags & CRD_F_ENCRYPT)) { + enccrd = crd1; + maccrd = crd2; + } else { + /* We cannot order the SEC as requested */ + printk("%s: cannot do the order\n", + device_get_nameunit(sc->sc_cdev)); + err = EINVAL; + goto errout; + } + } + /* assign in_fifo and out_fifo based on input/output struct type */ + if (crp->crp_flags & CRYPTO_F_SKBUF) { + /* using SKB buffers */ + struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; + if (skb_shinfo(skb)->nr_frags) { + printk("%s: skb frags unimplemented\n", + device_get_nameunit(sc->sc_cdev)); + err = EINVAL; + goto errout; + } + td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, + skb->len, DMA_TO_DEVICE); + td->ptr[in_fifo].len = skb->len; + td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, + skb->len, DMA_TO_DEVICE); + td->ptr[out_fifo].len = skb->len; + td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, + skb->len, DMA_TO_DEVICE); + } else if (crp->crp_flags & CRYPTO_F_IOV) { + /* using IOV buffers */ + struct uio *uiop = (struct uio *)crp->crp_buf; + if (uiop->uio_iovcnt > 1) { + printk("%s: iov frags unimplemented\n", + device_get_nameunit(sc->sc_cdev)); + err = EINVAL; + goto errout; + } + td->ptr[in_fifo].ptr = dma_map_single(NULL, + uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); + td->ptr[in_fifo].len = crp->crp_ilen; + /* crp_olen is never set; always use crp_ilen */ + td->ptr[out_fifo].ptr = dma_map_single(NULL, + uiop->uio_iov->iov_base, + crp->crp_ilen, DMA_TO_DEVICE); + td->ptr[out_fifo].len = crp->crp_ilen; + } else { + /* using contig buffers */ + td->ptr[in_fifo].ptr = dma_map_single(NULL, + crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); + td->ptr[in_fifo].len = crp->crp_ilen; + td->ptr[out_fifo].ptr = dma_map_single(NULL, + crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); + td->ptr[out_fifo].len = crp->crp_ilen; + } + if (enccrd) { + switch (enccrd->crd_alg) { + case CRYPTO_3DES_CBC: + td->hdr |= TALITOS_MODE0_DEU_3DES; + /* FALLTHROUGH */ + case CRYPTO_DES_CBC: + td->hdr |= TALITOS_SEL0_DEU + | TALITOS_MODE0_DEU_CBC; + if (enccrd->crd_flags & CRD_F_ENCRYPT) + td->hdr |= TALITOS_MODE0_DEU_ENC; + ivsize = 2*sizeof(u_int32_t); + DPRINTF("%cDES ses %d ch %d len %d\n", + (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', + (u32)TALITOS_SESSION(crp->crp_sid), + chsel, td->ptr[in_fifo].len); + break; + case CRYPTO_AES_CBC: + td->hdr |= TALITOS_SEL0_AESU + | TALITOS_MODE0_AESU_CBC; + if (enccrd->crd_flags & CRD_F_ENCRYPT) + td->hdr |= TALITOS_MODE0_AESU_ENC; + ivsize = 4*sizeof(u_int32_t); + DPRINTF("AES ses %d ch %d len %d\n", + (u32)TALITOS_SESSION(crp->crp_sid), + chsel, td->ptr[in_fifo].len); + break; + default: + printk("%s: unimplemented enccrd->crd_alg %d\n", + device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); + err = EINVAL; + goto errout; + } + /* + * Setup encrypt/decrypt state. When using basic ops + * we can't use an inline IV because hash/crypt offset + * must be from the end of the IV to the start of the + * crypt data and this leaves out the preceding header + * from the hash calculation. Instead we place the IV + * in the state record and set the hash/crypt offset to + * copy both the header+IV. + */ + if (enccrd->crd_flags & CRD_F_ENCRYPT) { + td->hdr |= TALITOS_DIR_OUTBOUND; + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) + iv = enccrd->crd_iv; + else + read_random((iv = (caddr_t) rand_iv), sizeof(rand_iv)); + if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { + crypto_copyback(crp->crp_flags, crp->crp_buf, + enccrd->crd_inject, ivsize, iv); + } + } else { + td->hdr |= TALITOS_DIR_INBOUND; + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { + iv = enccrd->crd_iv; + } else { + iv = (caddr_t) rand_iv; + crypto_copydata(crp->crp_flags, crp->crp_buf, + enccrd->crd_inject, ivsize, iv); + } + } + td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, + DMA_TO_DEVICE); + td->ptr[cipher_iv].len = ivsize; + /* + * we don't need the cipher iv out length/pointer + * field to do ESP IPsec. Therefore we set the len field as 0, + * which tells the SEC not to do anything with this len/ptr + * field. Previously, when length/pointer as pointing to iv, + * it gave us corruption of packets. + */ + td->ptr[cipher_iv_out].len = 0; + } + if (enccrd && maccrd) { + /* this is ipsec only for now */ + td->hdr |= TALITOS_SEL1_MDEU + | TALITOS_MODE1_MDEU_INIT + | TALITOS_MODE1_MDEU_PAD; + switch (maccrd->crd_alg) { + case CRYPTO_MD5: + td->hdr |= TALITOS_MODE1_MDEU_MD5; + break; + case CRYPTO_MD5_HMAC: + td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; + break; + case CRYPTO_SHA1: + td->hdr |= TALITOS_MODE1_MDEU_SHA1; + break; + case CRYPTO_SHA1_HMAC: + td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; + break; + default: + /* We cannot order the SEC as requested */ + printk("%s: cannot do the order\n", + device_get_nameunit(sc->sc_cdev)); + err = EINVAL; + goto errout; + } + if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || + (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { + /* + * The offset from hash data to the start of + * crypt data is the difference in the skips. + */ + /* ipsec only for now */ + td->ptr[hmac_key].ptr = dma_map_single(NULL, + ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); + td->ptr[hmac_key].len = ses->ses_hmac_len; + td->ptr[in_fifo].ptr += enccrd->crd_skip; + td->ptr[in_fifo].len = enccrd->crd_len; + td->ptr[out_fifo].ptr += enccrd->crd_skip; + td->ptr[out_fifo].len = enccrd->crd_len; + /* bytes of HMAC to postpend to ciphertext */ + td->ptr[out_fifo].extent = ses->ses_mlen; + td->ptr[hmac_data].ptr += maccrd->crd_skip; + td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; + } + if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { + printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", + device_get_nameunit(sc->sc_cdev)); + } + } + if (!enccrd && maccrd) { + /* single MD5 or SHA */ + td->hdr |= TALITOS_SEL0_MDEU + | TALITOS_MODE0_MDEU_INIT + | TALITOS_MODE0_MDEU_PAD; + switch (maccrd->crd_alg) { + case CRYPTO_MD5: + td->hdr |= TALITOS_MODE0_MDEU_MD5; + DPRINTF("MD5 ses %d ch %d len %d\n", + (u32)TALITOS_SESSION(crp->crp_sid), + chsel, td->ptr[in_fifo].len); + break; + case CRYPTO_MD5_HMAC: + td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; + break; + case CRYPTO_SHA1: + td->hdr |= TALITOS_MODE0_MDEU_SHA1; + DPRINTF("SHA1 ses %d ch %d len %d\n", + (u32)TALITOS_SESSION(crp->crp_sid), + chsel, td->ptr[in_fifo].len); + break; + case CRYPTO_SHA1_HMAC: + td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; + break; + default: + /* We cannot order the SEC as requested */ + DPRINTF("cannot do the order\n"); + err = EINVAL; + goto errout; + } + + if (crp->crp_flags & CRYPTO_F_IOV) + td->ptr[out_fifo].ptr += maccrd->crd_inject; + + if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || + (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { + td->ptr[hmac_key].ptr = dma_map_single(NULL, + ses->ses_hmac, ses->ses_hmac_len, + DMA_TO_DEVICE); + td->ptr[hmac_key].len = ses->ses_hmac_len; + } + } + else { + /* using process key (session data has duplicate) */ + td->ptr[cipher_key].ptr = dma_map_single(NULL, + enccrd->crd_key, (enccrd->crd_klen + 7) / 8, + DMA_TO_DEVICE); + td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; + } + /* descriptor complete - GO! */ + return talitos_submit(sc, td, chsel); + +errout: + if (err != ERESTART) { + crp->crp_etype = err; + crypto_done(crp); + } + return err; +} + +/* go through all channels descriptors, notifying OCF what has + * _and_hasn't_ successfully completed and reset the device + * (otherwise it's up to decoding desc hdrs!) + */ +static void talitos_errorprocessing(struct talitos_softc *sc) +{ + unsigned long flags; + int i, j; + + /* disable further scheduling until under control */ + spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); + + if (debug) dump_talitos_status(sc); + /* go through descriptors, try and salvage those successfully done, + * and EIO those that weren't + */ + for (i = 0; i < sc->sc_num_channels; i++) { + spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); + for (j = 0; j < sc->sc_chfifo_len; j++) { + if (sc->sc_chnfifo[i][j].cf_desc.hdr) { + if ((sc->sc_chnfifo[i][j].cf_desc.hdr + & TALITOS_HDR_DONE_BITS) + != TALITOS_HDR_DONE_BITS) { + /* this one didn't finish */ + /* signify in crp->etype */ + sc->sc_chnfifo[i][j].cf_crp->crp_etype + = EIO; + } + } else + continue; /* free entry */ + /* either way, notify ocf */ + crypto_done(sc->sc_chnfifo[i][j].cf_crp); + /* and tag it available again + * + * memset to ensure correct descriptor formation by + * avoiding inadvertently setting "optional" entries + * e.g. not using "optional" dptr2 MD/HMAC processing + */ + memset(&sc->sc_chnfifo[i][j].cf_desc, + 0, sizeof(struct talitos_desc)); + } + spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); + } + /* reset and initialize the SEC h/w device */ + talitos_reset_device(sc); + talitos_init_device(sc); +#ifdef CONFIG_OCF_RANDOMHARVEST + if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) + talitos_rng_init(sc); +#endif + + /* Okay. Stand by. */ + spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); + + return; +} + +/* go through all channels descriptors, notifying OCF what's been done */ +static void talitos_doneprocessing(struct talitos_softc *sc) +{ + unsigned long flags; + int i, j; + + /* go through descriptors looking for done bits */ + for (i = 0; i < sc->sc_num_channels; i++) { + spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); + for (j = 0; j < sc->sc_chfifo_len; j++) { + /* descriptor has done bits set? */ + if ((sc->sc_chnfifo[i][j].cf_desc.hdr + & TALITOS_HDR_DONE_BITS) + == TALITOS_HDR_DONE_BITS) { + /* notify ocf */ + crypto_done(sc->sc_chnfifo[i][j].cf_crp); + /* and tag it available again + * + * memset to ensure correct descriptor formation by + * avoiding inadvertently setting "optional" entries + * e.g. not using "optional" dptr2 MD/HMAC processing + */ + memset(&sc->sc_chnfifo[i][j].cf_desc, + 0, sizeof(struct talitos_desc)); + } + } + spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); + } + return; +} + +static irqreturn_t +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) +talitos_intr(int irq, void *arg) +#else +talitos_intr(int irq, void *arg, struct pt_regs *regs) +#endif +{ + struct talitos_softc *sc = arg; + u_int32_t v, v_hi; + + /* ack */ + v = talitos_read(sc->sc_base_addr + TALITOS_ISR); + v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); + talitos_write(sc->sc_base_addr + TALITOS_ICR, v); + talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); + + if (unlikely(v & TALITOS_ISR_ERROR)) { + /* Okay, Houston, we've had a problem here. */ + printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", + device_get_nameunit(sc->sc_cdev), v, v_hi); + talitos_errorprocessing(sc); + } else + if (likely(v & TALITOS_ISR_DONE)) { + talitos_doneprocessing(sc); + } + return IRQ_HANDLED; +} + +/* + * Initialize registers we need to touch only once. + */ +static void +talitos_init_device(struct talitos_softc *sc) +{ + u_int32_t v; + int i; + + DPRINTF("%s()\n", __FUNCTION__); + + /* init all channels */ + for (i = 0; i < sc->sc_num_channels; i++) { + v = talitos_read(sc->sc_base_addr + + i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); + v |= TALITOS_CH_CCCR_HI_CDWE + | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ + talitos_write(sc->sc_base_addr + + i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); + } + /* enable all interrupts */ + v = talitos_read(sc->sc_base_addr + TALITOS_IMR); + v |= TALITOS_IMR_ALL; + talitos_write(sc->sc_base_addr + TALITOS_IMR, v); + v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); + v |= TALITOS_IMR_HI_ERRONLY; + talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); + return; +} + +/* + * set the master reset bit on the device. + */ +static void +talitos_reset_device_master(struct talitos_softc *sc) +{ + u_int32_t v; + + /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ + v = talitos_read(sc->sc_base_addr + TALITOS_MCR); + talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); + + while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) + cpu_relax(); + + return; +} + +/* + * Resets the device. Values in the registers are left as is + * from the reset (i.e. initial values are assigned elsewhere). + */ +static void +talitos_reset_device(struct talitos_softc *sc) +{ + u_int32_t v; + int i; + + DPRINTF("%s()\n", __FUNCTION__); + + /* + * Master reset + * errata documentation: warning: certain SEC interrupts + * are not fully cleared by writing the MCR:SWR bit, + * set bit twice to completely reset + */ + talitos_reset_device_master(sc); /* once */ + talitos_reset_device_master(sc); /* and once again */ + + /* reset all channels */ + for (i = 0; i < sc->sc_num_channels; i++) { + v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + + TALITOS_CH_CCCR); + talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + + TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); + } +} + +/* Set up the crypto device structure, private data, + * and anything else we need before we start */ +#ifdef CONFIG_PPC_MERGE +static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) +#else +static int talitos_probe(struct platform_device *pdev) +#endif +{ + struct talitos_softc *sc = NULL; + struct resource *r; +#ifdef CONFIG_PPC_MERGE + struct device *device = &ofdev->dev; + struct device_node *np = ofdev->node; + const unsigned int *prop; + int err; + struct resource res; +#endif + static int num_chips = 0; + int rc; + int i; + + DPRINTF("%s()\n", __FUNCTION__); + + sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); + if (!sc) + return -ENOMEM; + memset(sc, 0, sizeof(*sc)); + + softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); + + sc->sc_irq = -1; + sc->sc_cid = -1; +#ifndef CONFIG_PPC_MERGE + sc->sc_dev = pdev; +#endif + sc->sc_num = num_chips++; + +#ifdef CONFIG_PPC_MERGE + dev_set_drvdata(device, sc); +#else + platform_set_drvdata(sc->sc_dev, sc); +#endif + + /* get the irq line */ +#ifdef CONFIG_PPC_MERGE + err = of_address_to_resource(np, 0, &res); + if (err) + return -EINVAL; + r = &res; + + sc->sc_irq = irq_of_parse_and_map(np, 0); +#else + /* get a pointer to the register memory */ + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + sc->sc_irq = platform_get_irq(pdev, 0); +#endif + rc = request_irq(sc->sc_irq, talitos_intr, 0, + device_get_nameunit(sc->sc_cdev), sc); + if (rc) { + printk(KERN_ERR "%s: failed to hook irq %d\n", + device_get_nameunit(sc->sc_cdev), sc->sc_irq); + sc->sc_irq = -1; + goto out; + } + + sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); + if (!sc->sc_base_addr) { + printk(KERN_ERR "%s: failed to ioremap\n", + device_get_nameunit(sc->sc_cdev)); + goto out; + } + + /* figure out our SEC's properties and capabilities */ + sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 + | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); + DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); + +#ifdef CONFIG_PPC_MERGE + /* get SEC properties from device tree, defaulting to SEC 2.0 */ + + prop = of_get_property(np, "num-channels", NULL); + sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; + + prop = of_get_property(np, "channel-fifo-len", NULL); + sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; + + prop = of_get_property(np, "exec-units-mask", NULL); + sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; + + prop = of_get_property(np, "descriptor-types-mask", NULL); + sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; +#else + /* bulk should go away with openfirmware flat device tree support */ + if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { + sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; + sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; + sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; + sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; + } else { + printk(KERN_ERR "%s: failed to id device\n", + device_get_nameunit(sc->sc_cdev)); + goto out; + } +#endif + + /* + 1 is for the meta-channel lock used by the channel scheduler */ + sc->sc_chnfifolock = (spinlock_t *) kmalloc( + (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); + if (!sc->sc_chnfifolock) + goto out; + for (i = 0; i < sc->sc_num_channels + 1; i++) { + spin_lock_init(&sc->sc_chnfifolock[i]); + } + + sc->sc_chnlastalg = (int *) kmalloc( + sc->sc_num_channels * sizeof(int), GFP_KERNEL); + if (!sc->sc_chnlastalg) + goto out; + memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); + + sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( + sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), + GFP_KERNEL); + if (!sc->sc_chnfifo) + goto out; + for (i = 0; i < sc->sc_num_channels; i++) { + sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( + sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), + GFP_KERNEL); + if (!sc->sc_chnfifo[i]) + goto out; + memset(sc->sc_chnfifo[i], 0, + sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); + } + + /* reset and initialize the SEC h/w device */ + talitos_reset_device(sc); + talitos_init_device(sc); + + sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); + if (sc->sc_cid < 0) { + printk(KERN_ERR "%s: could not get crypto driver id\n", + device_get_nameunit(sc->sc_cdev)); + goto out; + } + + /* register algorithms with the framework */ + printk("%s:", device_get_nameunit(sc->sc_cdev)); + + if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { + printk(" rng"); +#ifdef CONFIG_OCF_RANDOMHARVEST + talitos_rng_init(sc); + crypto_rregister(sc->sc_cid, talitos_read_random, sc); +#endif + } + if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { + printk(" des/3des"); + crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); + } + if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { + printk(" aes"); + crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); + } + if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { + printk(" md5"); + crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); + /* HMAC support only with IPsec for now */ + crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); + printk(" sha1"); + crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); + /* HMAC support only with IPsec for now */ + crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); + } + printk("\n"); + return 0; + +out: +#ifndef CONFIG_PPC_MERGE + talitos_remove(pdev); +#endif + return -ENOMEM; +} + +#ifdef CONFIG_PPC_MERGE +static int talitos_remove(struct of_device *ofdev) +#else +static int talitos_remove(struct platform_device *pdev) +#endif +{ +#ifdef CONFIG_PPC_MERGE + struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); +#else + struct talitos_softc *sc = platform_get_drvdata(pdev); +#endif + int i; + + DPRINTF("%s()\n", __FUNCTION__); + if (sc->sc_cid >= 0) + crypto_unregister_all(sc->sc_cid); + if (sc->sc_chnfifo) { + for (i = 0; i < sc->sc_num_channels; i++) + if (sc->sc_chnfifo[i]) + kfree(sc->sc_chnfifo[i]); + kfree(sc->sc_chnfifo); + } + if (sc->sc_chnlastalg) + kfree(sc->sc_chnlastalg); + if (sc->sc_chnfifolock) + kfree(sc->sc_chnfifolock); + if (sc->sc_irq != -1) + free_irq(sc->sc_irq, sc); + if (sc->sc_base_addr) + iounmap((void *) sc->sc_base_addr); + kfree(sc); + return 0; +} + +#ifdef CONFIG_PPC_MERGE +static struct of_device_id talitos_match[] = { + { + .type = "crypto", + .compatible = "talitos", + }, + {}, +}; + +MODULE_DEVICE_TABLE(of, talitos_match); + +static struct of_platform_driver talitos_driver = { + .name = DRV_NAME, + .match_table = talitos_match, + .probe = talitos_probe, + .remove = talitos_remove, +}; + +static int __init talitos_init(void) +{ + return of_register_platform_driver(&talitos_driver); +} + +static void __exit talitos_exit(void) +{ + of_unregister_platform_driver(&talitos_driver); +} +#else +/* Structure for a platform device driver */ +static struct platform_driver talitos_driver = { + .probe = talitos_probe, + .remove = talitos_remove, + .driver = { + .name = "fsl-sec2", + } +}; + +static int __init talitos_init(void) +{ + return platform_driver_register(&talitos_driver); +} + +static void __exit talitos_exit(void) +{ + platform_driver_unregister(&talitos_driver); +} +#endif + +module_init(talitos_init); +module_exit(talitos_exit); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("kim.phillips@freescale.com"); +MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); diff --git a/target/linux/generic/files/crypto/ocf/talitos/talitos_dev.h b/target/linux/generic/files/crypto/ocf/talitos/talitos_dev.h new file mode 100644 index 0000000..a8b0479 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/talitos/talitos_dev.h @@ -0,0 +1,277 @@ +/* + * Freescale SEC (talitos) device dependent data structures + * + * Copyright (c) 2006 Freescale Semiconductor, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* device ID register values */ +#define TALITOS_ID_SEC_2_0 0x40 +#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ + +/* + * following num_channels, channel-fifo-depth, exec-unit-mask, and + * descriptor-types-mask are for forward-compatibility with openfirmware + * flat device trees + */ + +/* + * num_channels : the number of channels available in each SEC version. + */ + +/* n.b. this driver requires these values be a power of 2 */ +#define TALITOS_NCHANNELS_SEC_1_0 4 +#define TALITOS_NCHANNELS_SEC_1_2 1 +#define TALITOS_NCHANNELS_SEC_2_0 4 +#define TALITOS_NCHANNELS_SEC_2_01 4 +#define TALITOS_NCHANNELS_SEC_2_1 4 +#define TALITOS_NCHANNELS_SEC_2_4 4 + +/* + * channel-fifo-depth : The number of descriptor + * pointers a channel fetch fifo can hold. + */ +#define TALITOS_CHFIFOLEN_SEC_1_0 1 +#define TALITOS_CHFIFOLEN_SEC_1_2 1 +#define TALITOS_CHFIFOLEN_SEC_2_0 24 +#define TALITOS_CHFIFOLEN_SEC_2_01 24 +#define TALITOS_CHFIFOLEN_SEC_2_1 24 +#define TALITOS_CHFIFOLEN_SEC_2_4 24 + +/* + * exec-unit-mask : The bitmask representing what Execution Units (EUs) + * are available. EU information should be encoded following the SEC's + * EU_SEL0 bitfield documentation, i.e. as follows: + * + * bit 31 = set if SEC permits no-EU selection (should be always set) + * bit 30 = set if SEC has the ARC4 EU (AFEU) + * bit 29 = set if SEC has the des/3des EU (DEU) + * bit 28 = set if SEC has the message digest EU (MDEU) + * bit 27 = set if SEC has the random number generator EU (RNG) + * bit 26 = set if SEC has the public key EU (PKEU) + * bit 25 = set if SEC has the aes EU (AESU) + * bit 24 = set if SEC has the Kasumi EU (KEU) + * + */ +#define TALITOS_HAS_EU_NONE (1<<0) +#define TALITOS_HAS_EU_AFEU (1<<1) +#define TALITOS_HAS_EU_DEU (1<<2) +#define TALITOS_HAS_EU_MDEU (1<<3) +#define TALITOS_HAS_EU_RNG (1<<4) +#define TALITOS_HAS_EU_PKEU (1<<5) +#define TALITOS_HAS_EU_AESU (1<<6) +#define TALITOS_HAS_EU_KEU (1<<7) + +/* the corresponding masks for each SEC version */ +#define TALITOS_HAS_EUS_SEC_1_0 0x7f +#define TALITOS_HAS_EUS_SEC_1_2 0x4d +#define TALITOS_HAS_EUS_SEC_2_0 0x7f +#define TALITOS_HAS_EUS_SEC_2_01 0x7f +#define TALITOS_HAS_EUS_SEC_2_1 0xff +#define TALITOS_HAS_EUS_SEC_2_4 0x7f + +/* + * descriptor-types-mask : The bitmask representing what descriptors + * are available. Descriptor type information should be encoded + * following the SEC's Descriptor Header Dword DESC_TYPE field + * documentation, i.e. as follows: + * + * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type + * bit 1 = set if SEC supports the ipsec_esp descriptor type + * bit 2 = set if SEC supports the common_nonsnoop desc. type + * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type + * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type + * bit 5 = set if SEC supports the srtp descriptor type + * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type + * bit 7 = set if SEC supports the pkeu_assemble descriptor type + * bit 8 = set if SEC supports the aesu_key_expand_output desc.type + * bit 9 = set if SEC supports the pkeu_ptmul descriptor type + * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type + * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type + * + * ..and so on and so forth. + */ +#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) +#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) +#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) + +/* the corresponding masks for each SEC version */ +#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf +#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf + +/* + * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register + */ + +/* global register offset addresses */ +#define TALITOS_ID 0x1020 +#define TALITOS_ID_HI 0x1024 +#define TALITOS_MCR 0x1030 /* master control register */ +#define TALITOS_MCR_HI 0x1038 /* master control register */ +#define TALITOS_MCR_SWR 0x1 +#define TALITOS_IMR 0x1008 /* interrupt mask register */ +#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ +#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ +#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ +#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ +#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ +#define TALITOS_ISR 0x1010 /* interrupt status register */ +#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ +#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ +#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ +#define TALITOS_ICR 0x1018 /* interrupt clear register */ +#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ + +/* channel register address stride */ +#define TALITOS_CH_OFFSET 0x100 + +/* channel register offset addresses and bits */ +#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ +#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ +#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ +#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ +#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ +#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ +#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ +#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ +#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ +#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ +#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ +#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ +#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel + * Descriptor Buffer (debug) */ + +/* execution unit register offset addresses and bits */ +#define TALITOS_DEUSR 0x2028 /* DEU status register */ +#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ +#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ +#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ +#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ +#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ +#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ +#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ +#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ +#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ +#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ +#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ +#define TALITOS_RNGSR 0xa028 /* RNG status register */ +#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ +#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ +#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ +#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ +#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ +#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ +#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ +#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ +#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ +#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ +#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ + +/* descriptor pointer entry */ +struct talitos_desc_ptr { + u16 len; /* length */ + u8 extent; /* jump (to s/g link table) and extent */ + u8 res; /* reserved */ + u32 ptr; /* pointer */ +}; + +/* descriptor */ +struct talitos_desc { + u32 hdr; /* header */ + u32 res; /* reserved */ + struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ +}; + +/* talitos descriptor header (hdr) bits */ + +/* primary execution unit select */ +#define TALITOS_SEL0_AFEU 0x10000000 +#define TALITOS_SEL0_DEU 0x20000000 +#define TALITOS_SEL0_MDEU 0x30000000 +#define TALITOS_SEL0_RNG 0x40000000 +#define TALITOS_SEL0_PKEU 0x50000000 +#define TALITOS_SEL0_AESU 0x60000000 + +/* primary execution unit mode (MODE0) and derivatives */ +#define TALITOS_MODE0_AESU_CBC 0x00200000 +#define TALITOS_MODE0_AESU_ENC 0x00100000 +#define TALITOS_MODE0_DEU_CBC 0x00400000 +#define TALITOS_MODE0_DEU_3DES 0x00200000 +#define TALITOS_MODE0_DEU_ENC 0x00100000 +#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ +#define TALITOS_MODE0_MDEU_HMAC 0x00800000 +#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ +#define TALITOS_MODE0_MDEU_MD5 0x00200000 +#define TALITOS_MODE0_MDEU_SHA256 0x00100000 +#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ +#define TALITOS_MODE0_MDEU_MD5_HMAC \ + (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) +#define TALITOS_MODE0_MDEU_SHA256_HMAC \ + (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) +#define TALITOS_MODE0_MDEU_SHA1_HMAC \ + (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) + +/* secondary execution unit select (SEL1) */ +/* it's MDEU or nothing */ +#define TALITOS_SEL1_MDEU 0x00030000 + +/* secondary execution unit mode (MODE1) and derivatives */ +#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ +#define TALITOS_MODE1_MDEU_HMAC 0x00000800 +#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ +#define TALITOS_MODE1_MDEU_MD5 0x00000200 +#define TALITOS_MODE1_MDEU_SHA256 0x00000100 +#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ +#define TALITOS_MODE1_MDEU_MD5_HMAC \ + (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) +#define TALITOS_MODE1_MDEU_SHA256_HMAC \ + (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) +#define TALITOS_MODE1_MDEU_SHA1_HMAC \ + (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) + +/* direction of overall data flow (DIR) */ +#define TALITOS_DIR_OUTBOUND 0x00000000 +#define TALITOS_DIR_INBOUND 0x00000002 + +/* done notification (DN) */ +#define TALITOS_DONE_NOTIFY 0x00000001 + +/* descriptor types */ +/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ +#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) +#define TD_TYPE_IPSEC_ESP (1 << 3) +#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) +#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) + +#define TALITOS_HDR_DONE_BITS 0xff000000 + +#define DPRINTF(a...) do { \ + if (debug) { \ + printk("%s: ", sc ? \ + device_get_nameunit(sc->sc_cdev) : "talitos"); \ + printk(a); \ + } \ + } while (0) diff --git a/target/linux/generic/files/crypto/ocf/talitos/talitos_soft.h b/target/linux/generic/files/crypto/ocf/talitos/talitos_soft.h new file mode 100644 index 0000000..eda9c2e --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/talitos/talitos_soft.h @@ -0,0 +1,76 @@ +/* + * Freescale SEC data structures for integration with ocf-linux + * + * Copyright (c) 2006 Freescale Semiconductor, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * paired descriptor and associated crypto operation + */ +struct desc_cryptop_pair { + struct talitos_desc cf_desc; /* descriptor ptr */ + struct cryptop *cf_crp; /* cryptop ptr */ +}; + +/* + * Holds data specific to a single talitos device. + */ +struct talitos_softc { + softc_device_decl sc_cdev; + struct platform_device *sc_dev; /* device backpointer */ + ocf_iomem_t sc_base_addr; + int sc_irq; + int sc_num; /* if we have multiple chips */ + int32_t sc_cid; /* crypto tag */ + u64 sc_chiprev; /* major/minor chip revision */ + int sc_nsessions; + struct talitos_session *sc_sessions; + int sc_num_channels;/* number of crypto channels */ + int sc_chfifo_len; /* channel fetch fifo len */ + int sc_exec_units; /* execution units mask */ + int sc_desc_types; /* descriptor types mask */ + /* + * mutual exclusion for intra-channel resources, e.g. fetch fifos + * the last entry is a meta-channel lock used by the channel scheduler + */ + spinlock_t *sc_chnfifolock; + /* sc_chnlastalgo contains last algorithm for that channel */ + int *sc_chnlastalg; + /* sc_chnfifo holds pending descriptor--crypto operation pairs */ + struct desc_cryptop_pair **sc_chnfifo; +}; + +struct talitos_session { + u_int32_t ses_used; + u_int32_t ses_klen; /* key length in bits */ + u_int32_t ses_key[8]; /* DES/3DES/AES key */ + u_int32_t ses_hmac[5]; /* hmac inner state */ + u_int32_t ses_hmac_len; /* hmac length */ + u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ +}; + +#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) +#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) diff --git a/target/linux/generic/files/crypto/ocf/ubsec_ssb/Makefile b/target/linux/generic/files/crypto/ocf/ubsec_ssb/Makefile new file mode 100644 index 0000000..f973efd --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ubsec_ssb/Makefile @@ -0,0 +1,12 @@ +# for SGlinux builds +-include $(ROOTDIR)/modules/.config + +obj-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb.o + +obj ?= . +EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ + +ifdef TOPDIR +-include $(TOPDIR)/Rules.make +endif + diff --git a/target/linux/generic/files/crypto/ocf/ubsec_ssb/bsdqueue.h b/target/linux/generic/files/crypto/ocf/ubsec_ssb/bsdqueue.h new file mode 100644 index 0000000..6010552 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ubsec_ssb/bsdqueue.h @@ -0,0 +1,527 @@ +/* $OpenBSD: queue.h,v 1.32 2007/04/30 18:42:34 pedro Exp $ */ +/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */ + +/* + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + */ + +#ifndef _BSD_SYS_QUEUE_H_ +#define _BSD_SYS_QUEUE_H_ + +/* + * This file defines five types of data structures: singly-linked lists, + * lists, simple queues, tail queues, and circular queues. + * + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A simple queue is headed by a pair of pointers, one the head of the + * list and the other to the tail of the list. The elements are singly + * linked to save space, so elements can only be removed from the + * head of the list. New elements can be added to the list before or after + * an existing element, at the head of the list, or at the end of the + * list. A simple queue may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * A circle queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or after + * an existing element, at the head of the list, or at the end of the list. + * A circle queue may be traversed in either direction, but has a more + * complex end of list detection. + * + * For details on the use of these macros, see the queue(3) manual page. + */ + +#if defined(QUEUE_MACRO_DEBUG) || (defined(_KERNEL) && defined(DIAGNOSTIC)) +#define _Q_INVALIDATE(a) (a) = ((void *)-1) +#else +#define _Q_INVALIDATE(a) +#endif + +/* + * Singly-linked List definitions. + */ +#define BSD_SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define BSD_SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define BSD_SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List access methods. + */ +#define BSD_SLIST_FIRST(head) ((head)->slh_first) +#define BSD_SLIST_END(head) NULL +#define BSD_SLIST_EMPTY(head) (BSD_SLIST_FIRST(head) == BSD_SLIST_END(head)) +#define BSD_SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define BSD_SLIST_FOREACH(var, head, field) \ + for((var) = BSD_SLIST_FIRST(head); \ + (var) != BSD_SLIST_END(head); \ + (var) = BSD_SLIST_NEXT(var, field)) + +#define BSD_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ + for ((varp) = &BSD_SLIST_FIRST((head)); \ + ((var) = *(varp)) != BSD_SLIST_END(head); \ + (varp) = &BSD_SLIST_NEXT((var), field)) + +/* + * Singly-linked List functions. + */ +#define BSD_SLIST_INIT(head) { \ + BSD_SLIST_FIRST(head) = BSD_SLIST_END(head); \ +} + +#define BSD_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + (elm)->field.sle_next = (slistelm)->field.sle_next; \ + (slistelm)->field.sle_next = (elm); \ +} while (0) + +#define BSD_SLIST_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.sle_next = (head)->slh_first; \ + (head)->slh_first = (elm); \ +} while (0) + +#define BSD_SLIST_REMOVE_NEXT(head, elm, field) do { \ + (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ +} while (0) + +#define BSD_SLIST_REMOVE_HEAD(head, field) do { \ + (head)->slh_first = (head)->slh_first->field.sle_next; \ +} while (0) + +#define BSD_SLIST_REMOVE(head, elm, type, field) do { \ + if ((head)->slh_first == (elm)) { \ + BSD_SLIST_REMOVE_HEAD((head), field); \ + } else { \ + struct type *curelm = (head)->slh_first; \ + \ + while (curelm->field.sle_next != (elm)) \ + curelm = curelm->field.sle_next; \ + curelm->field.sle_next = \ + curelm->field.sle_next->field.sle_next; \ + _Q_INVALIDATE((elm)->field.sle_next); \ + } \ +} while (0) + +/* + * List definitions. + */ +#define BSD_LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define BSD_LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define BSD_LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List access methods + */ +#define BSD_LIST_FIRST(head) ((head)->lh_first) +#define BSD_LIST_END(head) NULL +#define BSD_LIST_EMPTY(head) (BSD_LIST_FIRST(head) == BSD_LIST_END(head)) +#define BSD_LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define BSD_LIST_FOREACH(var, head, field) \ + for((var) = BSD_LIST_FIRST(head); \ + (var)!= BSD_LIST_END(head); \ + (var) = BSD_LIST_NEXT(var, field)) + +/* + * List functions. + */ +#define BSD_LIST_INIT(head) do { \ + BSD_LIST_FIRST(head) = BSD_LIST_END(head); \ +} while (0) + +#define BSD_LIST_INSERT_AFTER(listelm, elm, field) do { \ + if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ + (listelm)->field.le_next->field.le_prev = \ + &(elm)->field.le_next; \ + (listelm)->field.le_next = (elm); \ + (elm)->field.le_prev = &(listelm)->field.le_next; \ +} while (0) + +#define BSD_LIST_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + (elm)->field.le_next = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &(elm)->field.le_next; \ +} while (0) + +#define BSD_LIST_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.le_next = (head)->lh_first) != NULL) \ + (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ + (head)->lh_first = (elm); \ + (elm)->field.le_prev = &(head)->lh_first; \ +} while (0) + +#define BSD_LIST_REMOVE(elm, field) do { \ + if ((elm)->field.le_next != NULL) \ + (elm)->field.le_next->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = (elm)->field.le_next; \ + _Q_INVALIDATE((elm)->field.le_prev); \ + _Q_INVALIDATE((elm)->field.le_next); \ +} while (0) + +#define BSD_LIST_REPLACE(elm, elm2, field) do { \ + if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ + (elm2)->field.le_next->field.le_prev = \ + &(elm2)->field.le_next; \ + (elm2)->field.le_prev = (elm)->field.le_prev; \ + *(elm2)->field.le_prev = (elm2); \ + _Q_INVALIDATE((elm)->field.le_prev); \ + _Q_INVALIDATE((elm)->field.le_next); \ +} while (0) + +/* + * Simple queue definitions. + */ +#define BSD_SIMPLEQ_HEAD(name, type) \ +struct name { \ + struct type *sqh_first; /* first element */ \ + struct type **sqh_last; /* addr of last next element */ \ +} + +#define BSD_SIMPLEQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).sqh_first } + +#define BSD_SIMPLEQ_ENTRY(type) \ +struct { \ + struct type *sqe_next; /* next element */ \ +} + +/* + * Simple queue access methods. + */ +#define BSD_SIMPLEQ_FIRST(head) ((head)->sqh_first) +#define BSD_SIMPLEQ_END(head) NULL +#define BSD_SIMPLEQ_EMPTY(head) (BSD_SIMPLEQ_FIRST(head) == BSD_SIMPLEQ_END(head)) +#define BSD_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) + +#define BSD_SIMPLEQ_FOREACH(var, head, field) \ + for((var) = BSD_SIMPLEQ_FIRST(head); \ + (var) != BSD_SIMPLEQ_END(head); \ + (var) = BSD_SIMPLEQ_NEXT(var, field)) + +/* + * Simple queue functions. + */ +#define BSD_SIMPLEQ_INIT(head) do { \ + (head)->sqh_first = NULL; \ + (head)->sqh_last = &(head)->sqh_first; \ +} while (0) + +#define BSD_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ + (head)->sqh_last = &(elm)->field.sqe_next; \ + (head)->sqh_first = (elm); \ +} while (0) + +#define BSD_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.sqe_next = NULL; \ + *(head)->sqh_last = (elm); \ + (head)->sqh_last = &(elm)->field.sqe_next; \ +} while (0) + +#define BSD_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ + (head)->sqh_last = &(elm)->field.sqe_next; \ + (listelm)->field.sqe_next = (elm); \ +} while (0) + +#define BSD_SIMPLEQ_REMOVE_HEAD(head, field) do { \ + if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ + (head)->sqh_last = &(head)->sqh_first; \ +} while (0) + +/* + * Tail queue definitions. + */ +#define BSD_TAILQ_HEAD(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ +} + +#define BSD_TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first } + +#define BSD_TAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ +} + +/* + * tail queue access methods + */ +#define BSD_TAILQ_FIRST(head) ((head)->tqh_first) +#define BSD_TAILQ_END(head) NULL +#define BSD_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) +#define BSD_TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) +/* XXX */ +#define BSD_TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) +#define BSD_TAILQ_EMPTY(head) \ + (BSD_TAILQ_FIRST(head) == BSD_TAILQ_END(head)) + +#define BSD_TAILQ_FOREACH(var, head, field) \ + for((var) = BSD_TAILQ_FIRST(head); \ + (var) != BSD_TAILQ_END(head); \ + (var) = BSD_TAILQ_NEXT(var, field)) + +#define BSD_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for((var) = BSD_TAILQ_LAST(head, headname); \ + (var) != BSD_TAILQ_END(head); \ + (var) = BSD_TAILQ_PREV(var, headname, field)) + +/* + * Tail queue functions. + */ +#define BSD_TAILQ_INIT(head) do { \ + (head)->tqh_first = NULL; \ + (head)->tqh_last = &(head)->tqh_first; \ +} while (0) + +#define BSD_TAILQ_INSERT_HEAD(head, elm, field) do { \ + if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ + (head)->tqh_first->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (head)->tqh_first = (elm); \ + (elm)->field.tqe_prev = &(head)->tqh_first; \ +} while (0) + +#define BSD_TAILQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.tqe_next = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &(elm)->field.tqe_next; \ +} while (0) + +#define BSD_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ + (elm)->field.tqe_next->field.tqe_prev = \ + &(elm)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm)->field.tqe_next; \ + (listelm)->field.tqe_next = (elm); \ + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ +} while (0) + +#define BSD_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + (elm)->field.tqe_next = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ +} while (0) + +#define BSD_TAILQ_REMOVE(head, elm, field) do { \ + if (((elm)->field.tqe_next) != NULL) \ + (elm)->field.tqe_next->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ + _Q_INVALIDATE((elm)->field.tqe_prev); \ + _Q_INVALIDATE((elm)->field.tqe_next); \ +} while (0) + +#define BSD_TAILQ_REPLACE(head, elm, elm2, field) do { \ + if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ + (elm2)->field.tqe_next->field.tqe_prev = \ + &(elm2)->field.tqe_next; \ + else \ + (head)->tqh_last = &(elm2)->field.tqe_next; \ + (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ + *(elm2)->field.tqe_prev = (elm2); \ + _Q_INVALIDATE((elm)->field.tqe_prev); \ + _Q_INVALIDATE((elm)->field.tqe_next); \ +} while (0) + +/* + * Circular queue definitions. + */ +#define BSD_CIRCLEQ_HEAD(name, type) \ +struct name { \ + struct type *cqh_first; /* first element */ \ + struct type *cqh_last; /* last element */ \ +} + +#define BSD_CIRCLEQ_HEAD_INITIALIZER(head) \ + { BSD_CIRCLEQ_END(&head), BSD_CIRCLEQ_END(&head) } + +#define BSD_CIRCLEQ_ENTRY(type) \ +struct { \ + struct type *cqe_next; /* next element */ \ + struct type *cqe_prev; /* previous element */ \ +} + +/* + * Circular queue access methods + */ +#define BSD_CIRCLEQ_FIRST(head) ((head)->cqh_first) +#define BSD_CIRCLEQ_LAST(head) ((head)->cqh_last) +#define BSD_CIRCLEQ_END(head) ((void *)(head)) +#define BSD_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) +#define BSD_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) +#define BSD_CIRCLEQ_EMPTY(head) \ + (BSD_CIRCLEQ_FIRST(head) == BSD_CIRCLEQ_END(head)) + +#define BSD_CIRCLEQ_FOREACH(var, head, field) \ + for((var) = BSD_CIRCLEQ_FIRST(head); \ + (var) != BSD_CIRCLEQ_END(head); \ + (var) = BSD_CIRCLEQ_NEXT(var, field)) + +#define BSD_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ + for((var) = BSD_CIRCLEQ_LAST(head); \ + (var) != BSD_CIRCLEQ_END(head); \ + (var) = BSD_CIRCLEQ_PREV(var, field)) + +/* + * Circular queue functions. + */ +#define BSD_CIRCLEQ_INIT(head) do { \ + (head)->cqh_first = BSD_CIRCLEQ_END(head); \ + (head)->cqh_last = BSD_CIRCLEQ_END(head); \ +} while (0) + +#define BSD_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm)->field.cqe_next; \ + (elm)->field.cqe_prev = (listelm); \ + if ((listelm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ + (head)->cqh_last = (elm); \ + else \ + (listelm)->field.cqe_next->field.cqe_prev = (elm); \ + (listelm)->field.cqe_next = (elm); \ +} while (0) + +#define BSD_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm); \ + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ + if ((listelm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ + (head)->cqh_first = (elm); \ + else \ + (listelm)->field.cqe_prev->field.cqe_next = (elm); \ + (listelm)->field.cqe_prev = (elm); \ +} while (0) + +#define BSD_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ + (elm)->field.cqe_next = (head)->cqh_first; \ + (elm)->field.cqe_prev = BSD_CIRCLEQ_END(head); \ + if ((head)->cqh_last == BSD_CIRCLEQ_END(head)) \ + (head)->cqh_last = (elm); \ + else \ + (head)->cqh_first->field.cqe_prev = (elm); \ + (head)->cqh_first = (elm); \ +} while (0) + +#define BSD_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ + (elm)->field.cqe_next = BSD_CIRCLEQ_END(head); \ + (elm)->field.cqe_prev = (head)->cqh_last; \ + if ((head)->cqh_first == BSD_CIRCLEQ_END(head)) \ + (head)->cqh_first = (elm); \ + else \ + (head)->cqh_last->field.cqe_next = (elm); \ + (head)->cqh_last = (elm); \ +} while (0) + +#define BSD_CIRCLEQ_REMOVE(head, elm, field) do { \ + if ((elm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ + (head)->cqh_last = (elm)->field.cqe_prev; \ + else \ + (elm)->field.cqe_next->field.cqe_prev = \ + (elm)->field.cqe_prev; \ + if ((elm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ + (head)->cqh_first = (elm)->field.cqe_next; \ + else \ + (elm)->field.cqe_prev->field.cqe_next = \ + (elm)->field.cqe_next; \ + _Q_INVALIDATE((elm)->field.cqe_prev); \ + _Q_INVALIDATE((elm)->field.cqe_next); \ +} while (0) + +#define BSD_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ + if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ + BSD_CIRCLEQ_END(head)) \ + (head).cqh_last = (elm2); \ + else \ + (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ + if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ + BSD_CIRCLEQ_END(head)) \ + (head).cqh_first = (elm2); \ + else \ + (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ + _Q_INVALIDATE((elm)->field.cqe_prev); \ + _Q_INVALIDATE((elm)->field.cqe_next); \ +} while (0) + +#endif /* !_BSD_SYS_QUEUE_H_ */ diff --git a/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsec_ssb.c b/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsec_ssb.c new file mode 100644 index 0000000..e557e7a --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsec_ssb.c @@ -0,0 +1,2220 @@ + +/* + * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) + * Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com) + * Copyright (c) 2000 Jason L. Wright (jason@thought.net) + * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) + * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ +#undef UBSEC_DEBUG +#undef UBSEC_VERBOSE_DEBUG + +#ifdef UBSEC_VERBOSE_DEBUG +#define UBSEC_DEBUG +#endif + +/* + * uBsec BCM5365 hardware crypto accelerator + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * BSD queue + */ +//#include "bsdqueue.h" + +/* + * OCF + */ +#include +#include + +#define HMAC_HACK 1 + +#define HMAC_HACK 1 +#ifdef HMAC_HACK +#include +#include +#include +#include +#include +#endif + +#include "bsdqueue.h" +#include "ubsecreg.h" +#include "ubsecvar.h" + +#define DRV_MODULE_NAME "ubsec_ssb" +#define PFX DRV_MODULE_NAME ": " +#define DRV_MODULE_VERSION "0.02" +#define DRV_MODULE_RELDATE "Feb 21, 2009" + +#if 1 +#define DPRINTF(a...) \ + if (debug) \ + { \ + printk(DRV_MODULE_NAME ": " a); \ + } +#else +#define DPRINTF(a...) +#endif + +/* + * Prototypes + */ +static irqreturn_t ubsec_ssb_isr(int, void *, struct pt_regs *); +static int ubsec_ssb_probe(struct ssb_device *sdev, + const struct ssb_device_id *ent); +static void ubsec_ssb_remove(struct ssb_device *sdev); +int ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, + struct device *self); +static void ubsec_setup_mackey(struct ubsec_session *ses, int algo, + caddr_t key, int klen); +static int dma_map_skb(struct ubsec_softc *sc, + struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen); +static int dma_map_uio(struct ubsec_softc *sc, + struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen); +static void dma_unmap(struct ubsec_softc *sc, + struct ubsec_dma_alloc *q_map, int mlen); +static int ubsec_dmamap_aligned(struct ubsec_softc *sc, + const struct ubsec_dma_alloc *q_map, int mlen); + +#ifdef UBSEC_DEBUG +static int proc_read(char *buf, char **start, off_t offset, + int size, int *peof, void *data); +#endif + +void ubsec_reset_board(struct ubsec_softc *); +void ubsec_init_board(struct ubsec_softc *); +void ubsec_cleanchip(struct ubsec_softc *); +void ubsec_totalreset(struct ubsec_softc *); +int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); + +static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *); +static int ubsec_freesession(device_t, u_int64_t); +static int ubsec_process(device_t, struct cryptop *, int); + +void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); +void ubsec_feed(struct ubsec_softc *); +void ubsec_mcopy(struct sk_buff *, struct sk_buff *, int, int); +void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); +int ubsec_dma_malloc(struct ubsec_softc *, struct ubsec_dma_alloc *, + size_t, int); + +/* DEBUG crap... */ +void ubsec_dump_pb(struct ubsec_pktbuf *); +void ubsec_dump_mcr(struct ubsec_mcr *); + +#define READ_REG(sc,r) \ + ssb_read32((sc)->sdev, (r)); +#define WRITE_REG(sc,r,val) \ + ssb_write32((sc)->sdev, (r), (val)); +#define READ_REG_SDEV(sdev,r) \ + ssb_read32((sdev), (r)); +#define WRITE_REG_SDEV(sdev,r,val) \ + ssb_write32((sdev), (r), (val)); + +#define SWAP32(x) (x) = htole32(ntohl((x))) +#define HTOLE32(x) (x) = htole32(x) + +#ifdef __LITTLE_ENDIAN +#define letoh16(x) (x) +#define letoh32(x) (x) +#endif + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Enable debug output"); + +#define UBSEC_SSB_MAX_CHIPS 1 +static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS]; +static struct ubsec_stats ubsecstats; + +#ifdef UBSEC_DEBUG +static struct proc_dir_entry *procdebug; +#endif + +static struct ssb_device_id ubsec_ssb_tbl[] = { + /* Broadcom BCM5365P IPSec Core */ + SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV), + {}, +}; + +static struct ssb_driver ubsec_ssb_driver = { + .name = DRV_MODULE_NAME, + .id_table = ubsec_ssb_tbl, + .probe = ubsec_ssb_probe, + .remove = ubsec_ssb_remove, + /* + .suspend = ubsec_ssb_suspend, + .resume = ubsec_ssb_resume + */ +}; + +static device_method_t ubsec_ssb_methods = { + /* crypto device methods */ + DEVMETHOD(cryptodev_newsession, ubsec_newsession), + DEVMETHOD(cryptodev_freesession,ubsec_freesession), + DEVMETHOD(cryptodev_process, ubsec_process), +}; + +#ifdef UBSEC_DEBUG +static int +proc_read(char *buf, char **start, off_t offset, + int size, int *peof, void *data) +{ + int i = 0, byteswritten = 0, ret; + unsigned int stat, ctrl; +#ifdef UBSEC_VERBOSE_DEBUG + struct ubsec_q *q; + struct ubsec_dma *dmap; +#endif + + while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL)) + { + struct ubsec_softc *sc = ubsec_chip_idx[i]; + + stat = READ_REG(sc, BS_STAT); + ctrl = READ_REG(sc, BS_CTRL); + ret = snprintf((buf + byteswritten), + (size - byteswritten) , + "DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); + + byteswritten += ret; + +#ifdef UBSEC_VERBOSE_DEBUG + printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); + + /* Dump all queues MCRs */ + if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { + BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next) + { + dmap = q->q_dma; + ubsec_dump_mcr(&dmap->d_dma->d_mcr); + } + } +#endif + + i++; + } + + *peof = 1; + + return byteswritten; +} +#endif + +/* + * map in a given sk_buff + */ +static int +dma_map_skb(struct ubsec_softc *sc, struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen) +{ + int i = 0; + dma_addr_t tmp; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + /* + * We support only a limited number of fragments. + */ + if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER)) + { + printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); + return (-ENOMEM); + } + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb)); +#endif + + /* first data package */ + tmp = dma_map_single(sc->sc_dv, + skb->data, + skb_headlen(skb), + DMA_BIDIRECTIONAL); + + q_map[i].dma_paddr = tmp; + q_map[i].dma_vaddr = skb->data; + q_map[i].dma_size = skb_headlen(skb); + + if (unlikely(tmp == 0)) + { + printk(KERN_ERR "Could not map memory region for dma.\n"); + return (-EINVAL); + } + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp); +#endif + + + /* all other data packages */ + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1, + (unsigned int)page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) + + skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size); +#endif + + tmp = dma_map_single(sc->sc_dv, + page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) + + skb_shinfo(skb)->frags[i].page_offset, + skb_shinfo(skb)->frags[i].size, + DMA_BIDIRECTIONAL); + + q_map[i + 1].dma_paddr = tmp; + q_map[i + 1].dma_vaddr = (void*)(page_address(skb_frag_page(&skb_shinfo(skb)->frags[i])) + + skb_shinfo(skb)->frags[i].page_offset); + q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size; + + if (unlikely(tmp == 0)) + { + printk(KERN_ERR "Could not map memory region for dma.\n"); + return (-EINVAL); + } + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp); +#endif + + } + *mlen = i + 1; + + return(0); +} + +/* + * map in a given uio buffer + */ + +static int +dma_map_uio(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen) +{ + struct iovec *iov = uio->uio_iov; + int n; + dma_addr_t tmp; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + /* + * We support only a limited number of fragments. + */ + if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER)) + { + printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); + return (-ENOMEM); + } + + for (n = 0; n < uio->uio_iovcnt; n++) { +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len); +#endif + tmp = dma_map_single(sc->sc_dv, + iov->iov_base, + iov->iov_len, + DMA_BIDIRECTIONAL); + + q_map[n].dma_paddr = tmp; + q_map[n].dma_vaddr = iov->iov_base; + q_map[n].dma_size = iov->iov_len; + + if (unlikely(tmp == 0)) + { + printk(KERN_ERR "Could not map memory region for dma.\n"); + return (-EINVAL); + } + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp); +#endif + + iov++; + } + *mlen = n; + + return(0); +} + +static void +dma_unmap(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, int mlen) +{ + int i; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + for(i = 0; i < mlen; i++) + { +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size); +#endif + dma_unmap_single(sc->sc_dv, + q_map[i].dma_paddr, + q_map[i].dma_size, + DMA_BIDIRECTIONAL); + } + return; +} + +/* + * Is the operand suitable aligned for direct DMA. Each + * segment must be aligned on a 32-bit boundary and all + * but the last segment must be a multiple of 4 bytes. + */ +static int +ubsec_dmamap_aligned(struct ubsec_softc *sc, const struct ubsec_dma_alloc *q_map, int mlen) +{ + int i; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + for (i = 0; i < mlen; i++) { + if (q_map[i].dma_paddr & 3) + return (0); + if (i != (mlen - 1) && (q_map[i].dma_size & 3)) + return (0); + } + return (1); +} + + +#define N(a) (sizeof(a) / sizeof (a[0])) +static void +ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) +{ +#ifdef HMAC_HACK + MD5_CTX md5ctx; + SHA1_CTX sha1ctx; + int i; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + for (i = 0; i < klen; i++) + key[i] ^= HMAC_IPAD_VAL; + + if (algo == CRYPTO_MD5_HMAC) { + MD5Init(&md5ctx); + MD5Update(&md5ctx, key, klen); + MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); + bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); + } else { + SHA1Init(&sha1ctx); + SHA1Update(&sha1ctx, key, klen); + SHA1Update(&sha1ctx, hmac_ipad_buffer, + SHA1_HMAC_BLOCK_LEN - klen); + bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); + } + + for (i = 0; i < klen; i++) + key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); + + if (algo == CRYPTO_MD5_HMAC) { + MD5Init(&md5ctx); + MD5Update(&md5ctx, key, klen); + MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); + bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); + } else { + SHA1Init(&sha1ctx); + SHA1Update(&sha1ctx, key, klen); + SHA1Update(&sha1ctx, hmac_opad_buffer, + SHA1_HMAC_BLOCK_LEN - klen); + bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); + } + + for (i = 0; i < klen; i++) + key[i] ^= HMAC_OPAD_VAL; + +#else /* HMAC_HACK */ + DPRINTF("md5/sha not implemented\n"); +#endif /* HMAC_HACK */ +} +#undef N + +static int +ubsec_ssb_probe(struct ssb_device *sdev, + const struct ssb_device_id *ent) +{ + int err; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + err = ssb_bus_powerup(sdev->bus, 0); + if (err) { + dev_err(sdev->dev, "Failed to powerup the bus\n"); + goto err_out; + } + + err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr, + IRQF_SHARED, DRV_MODULE_NAME, sdev); + if (err) { + dev_err(sdev->dev, "Could not request irq\n"); + goto err_out_powerdown; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) + err = dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(32)) || + dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(32)); +#else + err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK); +#endif + if (err) { + dev_err(sdev->dev, + "Required 32BIT DMA mask unsupported by the system.\n"); + goto err_out_free_irq; + } + + printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n", + sdev->irq); + + DPRINTF("Vendor: %x, core id: %x, revision: %x\n", + sdev->id.vendor, sdev->id.coreid, sdev->id.revision); + + ssb_device_enable(sdev, 0); + + if (ubsec_attach(sdev, ent, sdev->dev) != 0) + goto err_out_disable; + +#ifdef UBSEC_DEBUG + procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL); + if (procdebug) + { + procdebug->read_proc = proc_read; + procdebug->data = NULL; + } else + DPRINTF("Unable to create proc file.\n"); +#endif + + return 0; + +err_out_disable: + ssb_device_disable(sdev, 0); + +err_out_free_irq: + free_irq(sdev->irq, sdev); + +err_out_powerdown: + ssb_bus_may_powerdown(sdev->bus); + +err_out: + return err; +} + +static void ubsec_ssb_remove(struct ssb_device *sdev) { + + struct ubsec_softc *sc; + unsigned int ctrlflgs; + struct ubsec_dma *dmap; + u_int32_t i; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL); + /* disable all IPSec Core interrupts globally */ + ctrlflgs ^= (BS_CTRL_MCR1INT | BS_CTRL_MCR2INT | + BS_CTRL_DMAERR); + WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs); + + free_irq(sdev->irq, sdev); + + sc = (struct ubsec_softc *)ssb_get_drvdata(sdev); + + /* unregister all crypto algorithms */ + crypto_unregister_all(sc->sc_cid); + + /* Free queue / dma memory */ + for (i = 0; i < UBS_MAX_NQUEUE; i++) { + struct ubsec_q *q; + + q = sc->sc_queuea[i]; + if (q != NULL) + { + dmap = q->q_dma; + if (dmap != NULL) + { + ubsec_dma_free(sc, &dmap->d_alloc); + q->q_dma = NULL; + } + kfree(q); + } + sc->sc_queuea[i] = NULL; + } + + ssb_device_disable(sdev, 0); + ssb_bus_may_powerdown(sdev->bus); + ssb_set_drvdata(sdev, NULL); + +#ifdef UBSEC_DEBUG + if (procdebug) + remove_proc_entry(DRV_MODULE_NAME, NULL); +#endif + +} + + +int +ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, + struct device *self) +{ + struct ubsec_softc *sc = NULL; + struct ubsec_dma *dmap; + u_int32_t i; + static int num_chips = 0; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + sc = (struct ubsec_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); + if (!sc) + return(-ENOMEM); + memset(sc, 0, sizeof(*sc)); + + sc->sc_dv = sdev->dev; + sc->sdev = sdev; + + spin_lock_init(&sc->sc_ringmtx); + + softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods); + + /* Maybe someday there are boards with more than one chip available */ + if (num_chips < UBSEC_SSB_MAX_CHIPS) { + ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc; + num_chips++; + } + + ssb_set_drvdata(sdev, sc); + + BSD_SIMPLEQ_INIT(&sc->sc_queue); + BSD_SIMPLEQ_INIT(&sc->sc_qchip); + BSD_SIMPLEQ_INIT(&sc->sc_queue2); + BSD_SIMPLEQ_INIT(&sc->sc_qchip2); + BSD_SIMPLEQ_INIT(&sc->sc_q2free); + + sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; + + sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); + if (sc->sc_cid < 0) { + device_printf(sc->sc_dev, "could not get crypto driver id\n"); + return -1; + } + + BSD_SIMPLEQ_INIT(&sc->sc_freequeue); + dmap = sc->sc_dmaa; + for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { + struct ubsec_q *q; + + q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL); + if (q == NULL) { + printf(": can't allocate queue buffers\n"); + break; + } + + if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) { + printf(": can't allocate dma buffers\n"); + kfree(q); + break; + } + dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; + + q->q_dma = dmap; + sc->sc_queuea[i] = q; + + BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); + } + + /* + * Reset Broadcom chip + */ + ubsec_reset_board(sc); + + /* + * Init Broadcom chip + */ + ubsec_init_board(sc); + + /* supported crypto algorithms */ + crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); + + if (sc->sc_flags & UBS_FLAGS_AES) { + crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); + printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n"); + } + else + printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n"); + + crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); + crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); + + return 0; +} + +/* + * UBSEC Interrupt routine + */ +static irqreturn_t +ubsec_ssb_isr(int irq, void *arg, struct pt_regs *regs) +{ + struct ubsec_softc *sc = NULL; + volatile u_int32_t stat; + struct ubsec_q *q; + struct ubsec_dma *dmap; + int npkts = 0, i; + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + sc = (struct ubsec_softc *)ssb_get_drvdata(arg); + + stat = READ_REG(sc, BS_STAT); + + stat &= sc->sc_statmask; + if (stat == 0) + return IRQ_NONE; + + WRITE_REG(sc, BS_STAT, stat); /* IACK */ + + /* + * Check to see if we have any packets waiting for us + */ + if ((stat & BS_STAT_MCR1_DONE)) { + while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { + q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); + dmap = q->q_dma; + + if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) + { + DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags); + break; + } + + BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); + + npkts = q->q_nstacked_mcrs; + /* + * search for further sc_qchip ubsec_q's that share + * the same MCR, and complete them too, they must be + * at the top. + */ + for (i = 0; i < npkts; i++) { + if(q->q_stacked_mcr[i]) + ubsec_callback(sc, q->q_stacked_mcr[i]); + else + break; + } + ubsec_callback(sc, q); + } + + /* + * Don't send any more packet to chip if there has been + * a DMAERR. + */ + if (likely(!(stat & BS_STAT_DMAERR))) + ubsec_feed(sc); + else + DPRINTF("DMA error occurred. Stop feeding crypto chip.\n"); + } + + /* + * Check to see if we got any DMA Error + */ + if (stat & BS_STAT_DMAERR) { + volatile u_int32_t a = READ_REG(sc, BS_ERR); + + printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME, + (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR); + + ubsecstats.hst_dmaerr++; + ubsec_totalreset(sc); + ubsec_feed(sc); + } + + return IRQ_HANDLED; +} + +/* + * ubsec_feed() - aggregate and post requests to chip + * It is assumed that the caller set splnet() + */ +void +ubsec_feed(struct ubsec_softc *sc) +{ +#ifdef UBSEC_VERBOSE_DEBUG + static int max; +#endif + struct ubsec_q *q, *q2; + int npkts, i; + void *v; + u_int32_t stat; + + npkts = sc->sc_nqueue; + if (npkts > UBS_MAX_AGGR) + npkts = UBS_MAX_AGGR; + if (npkts < 2) + goto feed1; + + stat = READ_REG(sc, BS_STAT); + + if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { + if(stat & BS_STAT_DMAERR) { + ubsec_totalreset(sc); + ubsecstats.hst_dmaerr++; + } + return; + } + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("merging %d records\n", npkts); + + /* XXX temporary aggregation statistics reporting code */ + if (max < npkts) { + max = npkts; + DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max); + } +#endif /* UBSEC_VERBOSE_DEBUG */ + + q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); + BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); + --sc->sc_nqueue; + +#if 0 + /* + * XXX + * We use dma_map_single() - no sync required! + */ + + bus_dmamap_sync(sc->sc_dmat, q->q_src_map, + 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + if (q->q_dst_map != NULL) + bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, + 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); +#endif + + q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ + + for (i = 0; i < q->q_nstacked_mcrs; i++) { + q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue); + +#if 0 + bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, + 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + if (q2->q_dst_map != NULL) + bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, + 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); +#endif + BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); + --sc->sc_nqueue; + + v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - + sizeof(struct ubsec_mcr_add); + bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); + q->q_stacked_mcr[i] = q2; + } + q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); + BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); +#if 0 + bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, + 0, q->q_dma->d_alloc.dma_map->dm_mapsize, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +#endif + WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_mcr)); +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("feed (1): q->chip %p %08x %08x\n", q, + (u_int32_t)q->q_dma->d_alloc.dma_paddr, + (u_int32_t)(q->q_dma->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_mcr))); +#endif /* UBSEC_DEBUG */ + return; + +feed1: + while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) { + stat = READ_REG(sc, BS_STAT); + + if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { + if(stat & BS_STAT_DMAERR) { + ubsec_totalreset(sc); + ubsecstats.hst_dmaerr++; + } + break; + } + + q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); + +#if 0 + bus_dmamap_sync(sc->sc_dmat, q->q_src_map, + 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); + if (q->q_dst_map != NULL) + bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, + 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); + bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, + 0, q->q_dma->d_alloc.dma_map->dm_mapsize, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +#endif + + WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_mcr)); +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("feed (2): q->chip %p %08x %08x\n", q, + (u_int32_t)q->q_dma->d_alloc.dma_paddr, + (u_int32_t)(q->q_dma->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_mcr))); +#endif /* UBSEC_DEBUG */ + BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); + --sc->sc_nqueue; + BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); + } +} + +/* + * Allocate a new 'session' and return an encoded session id. 'sidp' + * contains our registration id, and should contain an encoded session + * id on successful allocation. + */ +static int +ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) +{ + struct cryptoini *c, *encini = NULL, *macini = NULL; + struct ubsec_softc *sc = NULL; + struct ubsec_session *ses = NULL; + int sesn, i; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + if (sidp == NULL || cri == NULL) + return (EINVAL); + + sc = device_get_softc(dev); + + if (sc == NULL) + return (EINVAL); + + for (c = cri; c != NULL; c = c->cri_next) { + if (c->cri_alg == CRYPTO_MD5_HMAC || + c->cri_alg == CRYPTO_SHA1_HMAC) { + if (macini) + return (EINVAL); + macini = c; + } else if (c->cri_alg == CRYPTO_DES_CBC || + c->cri_alg == CRYPTO_3DES_CBC || + c->cri_alg == CRYPTO_AES_CBC) { + if (encini) + return (EINVAL); + encini = c; + } else + return (EINVAL); + } + if (encini == NULL && macini == NULL) + return (EINVAL); + + if (sc->sc_sessions == NULL) { + ses = sc->sc_sessions = (struct ubsec_session *)kmalloc( + sizeof(struct ubsec_session), SLAB_ATOMIC); + if (ses == NULL) + return (ENOMEM); + memset(ses, 0, sizeof(struct ubsec_session)); + sesn = 0; + sc->sc_nsessions = 1; + } else { + for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { + if (sc->sc_sessions[sesn].ses_used == 0) { + ses = &sc->sc_sessions[sesn]; + break; + } + } + + if (ses == NULL) { + sesn = sc->sc_nsessions; + ses = (struct ubsec_session *)kmalloc((sesn + 1) * + sizeof(struct ubsec_session), SLAB_ATOMIC); + if (ses == NULL) + return (ENOMEM); + memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session)); + bcopy(sc->sc_sessions, ses, sesn * + sizeof(struct ubsec_session)); + bzero(sc->sc_sessions, sesn * + sizeof(struct ubsec_session)); + kfree(sc->sc_sessions); + sc->sc_sessions = ses; + ses = &sc->sc_sessions[sesn]; + sc->sc_nsessions++; + } + } + + bzero(ses, sizeof(struct ubsec_session)); + ses->ses_used = 1; + if (encini) { + /* get an IV */ + /* XXX may read fewer than requested */ + read_random(ses->ses_iv, sizeof(ses->ses_iv)); + + /* Go ahead and compute key in ubsec's byte order */ + if (encini->cri_alg == CRYPTO_DES_CBC) { + /* DES uses the same key three times: + * 1st encrypt -> 2nd decrypt -> 3nd encrypt */ + bcopy(encini->cri_key, &ses->ses_key[0], 8); + bcopy(encini->cri_key, &ses->ses_key[2], 8); + bcopy(encini->cri_key, &ses->ses_key[4], 8); + ses->ses_keysize = 192; /* Fake! Actually its only 64bits .. + oh no it is even less: 54bits. */ + } else if(encini->cri_alg == CRYPTO_3DES_CBC) { + bcopy(encini->cri_key, ses->ses_key, 24); + ses->ses_keysize = 192; + } else if(encini->cri_alg == CRYPTO_AES_CBC) { + ses->ses_keysize = encini->cri_klen; + + if (ses->ses_keysize != 128 && + ses->ses_keysize != 192 && + ses->ses_keysize != 256) + { + DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize); + return (EINVAL); + } + bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8)); + } + + /* Hardware requires the keys in little endian byte order */ + for (i=0; i < (ses->ses_keysize / 32); i++) + SWAP32(ses->ses_key[i]); + } + + if (macini) { + ses->ses_mlen = macini->cri_mlen; + + if (ses->ses_mlen == 0 || + ses->ses_mlen > SHA1_HASH_LEN) { + + if (macini->cri_alg == CRYPTO_MD5_HMAC || + macini->cri_alg == CRYPTO_SHA1_HMAC) + { + ses->ses_mlen = DEFAULT_HMAC_LEN; + } else + { + /* + * Reserved for future usage. MD5/SHA1 calculations have + * different hash sizes. + */ + printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen); + return (EINVAL); + } + + } + + if (macini->cri_key != NULL) { + ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key, + macini->cri_klen / 8); + } + } + + *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); + return (0); +} + +/* + * Deallocate a session. + */ +static int +ubsec_freesession(device_t dev, u_int64_t tid) +{ + struct ubsec_softc *sc = device_get_softc(dev); + int session; + u_int32_t sid = ((u_int32_t)tid) & 0xffffffff; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + if (sc == NULL) + return (EINVAL); + + session = UBSEC_SESSION(sid); + if (session < sc->sc_nsessions) { + bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); + return (0); + } else + return (EINVAL); +} + +static int +ubsec_process(device_t dev, struct cryptop *crp, int hint) +{ + struct ubsec_q *q = NULL; + int err = 0, i, j, nicealign; + struct ubsec_softc *sc = device_get_softc(dev); + struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; + int encoffset = 0, macoffset = 0, cpskip, cpoffset; + int sskip, dskip, stheend, dtheend, ivsize = 8; + int16_t coffset; + struct ubsec_session *ses; + struct ubsec_generic_ctx ctx; + struct ubsec_dma *dmap = NULL; + unsigned long flags; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + if (unlikely(crp == NULL || crp->crp_callback == NULL)) { + ubsecstats.hst_invalid++; + return (EINVAL); + } + + if (unlikely(sc == NULL)) + return (EINVAL); + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("spin_lock_irqsave\n"); +#endif + spin_lock_irqsave(&sc->sc_ringmtx, flags); + //spin_lock_irq(&sc->sc_ringmtx); + + if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) { + ubsecstats.hst_queuefull++; +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("spin_unlock_irqrestore\n"); +#endif + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); + //spin_unlock_irq(&sc->sc_ringmtx); + err = ENOMEM; + goto errout2; + } + + q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue); + BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("spin_unlock_irqrestore\n"); +#endif + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); + //spin_unlock_irq(&sc->sc_ringmtx); + + dmap = q->q_dma; /* Save dma pointer */ + bzero(q, sizeof(struct ubsec_q)); + bzero(&ctx, sizeof(ctx)); + + q->q_sesn = UBSEC_SESSION(crp->crp_sid); + q->q_dma = dmap; + ses = &sc->sc_sessions[q->q_sesn]; + + if (crp->crp_flags & CRYPTO_F_SKBUF) { + q->q_src_m = (struct sk_buff *)crp->crp_buf; + q->q_dst_m = (struct sk_buff *)crp->crp_buf; + } else if (crp->crp_flags & CRYPTO_F_IOV) { + q->q_src_io = (struct uio *)crp->crp_buf; + q->q_dst_io = (struct uio *)crp->crp_buf; + } else { + err = EINVAL; + goto errout; /* XXX we don't handle contiguous blocks! */ + } + + bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); + + dmap->d_dma->d_mcr.mcr_pkts = htole16(1); + dmap->d_dma->d_mcr.mcr_flags = 0; + q->q_crp = crp; + + crd1 = crp->crp_desc; + if (crd1 == NULL) { + err = EINVAL; + goto errout; + } + crd2 = crd1->crd_next; + + if (crd2 == NULL) { + if (crd1->crd_alg == CRYPTO_MD5_HMAC || + crd1->crd_alg == CRYPTO_SHA1_HMAC) { + maccrd = crd1; + enccrd = NULL; + } else if (crd1->crd_alg == CRYPTO_DES_CBC || + crd1->crd_alg == CRYPTO_3DES_CBC || + crd1->crd_alg == CRYPTO_AES_CBC) { + maccrd = NULL; + enccrd = crd1; + } else { + err = EINVAL; + goto errout; + } + } else { + if ((crd1->crd_alg == CRYPTO_MD5_HMAC || + crd1->crd_alg == CRYPTO_SHA1_HMAC) && + (crd2->crd_alg == CRYPTO_DES_CBC || + crd2->crd_alg == CRYPTO_3DES_CBC || + crd2->crd_alg == CRYPTO_AES_CBC) && + ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { + maccrd = crd1; + enccrd = crd2; + } else if ((crd1->crd_alg == CRYPTO_DES_CBC || + crd1->crd_alg == CRYPTO_3DES_CBC || + crd1->crd_alg == CRYPTO_AES_CBC) && + (crd2->crd_alg == CRYPTO_MD5_HMAC || + crd2->crd_alg == CRYPTO_SHA1_HMAC) && + (crd1->crd_flags & CRD_F_ENCRYPT)) { + enccrd = crd1; + maccrd = crd2; + } else { + /* + * We cannot order the ubsec as requested + */ + printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n"); + err = EINVAL; + goto errout; + } + } + + /* Encryption/Decryption requested */ + if (enccrd) { + encoffset = enccrd->crd_skip; + + if (enccrd->crd_alg == CRYPTO_DES_CBC || + enccrd->crd_alg == CRYPTO_3DES_CBC) + { + ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); + ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES); + ivsize = 8; /* [3]DES uses 64bit IVs */ + } else { + ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_AES); + ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); + ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */ + + switch(ses->ses_keysize) + { + case 128: + ctx.pc_flags |= htole16(UBS_PKTCTX_AES128); + break; + case 192: + ctx.pc_flags |= htole16(UBS_PKTCTX_AES192); + break; + case 256: + ctx.pc_flags |= htole16(UBS_PKTCTX_AES256); + break; + default: + DPRINTF("invalid AES key size: %d\n", ses->ses_keysize); + err = EINVAL; + goto errout; + } + } + + if (enccrd->crd_flags & CRD_F_ENCRYPT) { + /* Direction: Outbound */ + + q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; + + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { + bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); + } else { + for(i=0; i < (ivsize / 4); i++) + ctx.pc_iv[i] = ses->ses_iv[i]; + } + + /* If there is no IV in the buffer -> copy it here */ + if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { + if (crp->crp_flags & CRYPTO_F_SKBUF) + /* + m_copyback(q->q_src_m, + enccrd->crd_inject, + 8, ctx.pc_iv); + */ + crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m, + enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); + else if (crp->crp_flags & CRYPTO_F_IOV) + /* + cuio_copyback(q->q_src_io, + enccrd->crd_inject, + 8, ctx.pc_iv); + */ + crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io, + enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); + } + } else { + /* Direction: Inbound */ + + ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); + + if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) + bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); + else if (crp->crp_flags & CRYPTO_F_SKBUF) + /* + m_copydata(q->q_src_m, enccrd->crd_inject, + 8, (caddr_t)ctx.pc_iv); + */ + crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m, + enccrd->crd_inject, ivsize, + (caddr_t)ctx.pc_iv); + else if (crp->crp_flags & CRYPTO_F_IOV) + /* + cuio_copydata(q->q_src_io, + enccrd->crd_inject, 8, + (caddr_t)ctx.pc_iv); + */ + crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io, + enccrd->crd_inject, ivsize, + (caddr_t)ctx.pc_iv); + + } + + /* Even though key & IV sizes differ from cipher to cipher + * copy / swap the full array lengths. Let the compiler unroll + * the loop to increase the cpu pipeline performance... */ + for(i=0; i < 8; i++) + ctx.pc_key[i] = ses->ses_key[i]; + for(i=0; i < 4; i++) + SWAP32(ctx.pc_iv[i]); + } + + /* Authentication requested */ + if (maccrd) { + macoffset = maccrd->crd_skip; + + if (maccrd->crd_alg == CRYPTO_MD5_HMAC) + ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); + else + ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); + + for (i = 0; i < 5; i++) { + ctx.pc_hminner[i] = ses->ses_hminner[i]; + ctx.pc_hmouter[i] = ses->ses_hmouter[i]; + + HTOLE32(ctx.pc_hminner[i]); + HTOLE32(ctx.pc_hmouter[i]); + } + } + + if (enccrd && maccrd) { + /* + * ubsec cannot handle packets where the end of encryption + * and authentication are not the same, or where the + * encrypted part begins before the authenticated part. + */ + if (((encoffset + enccrd->crd_len) != + (macoffset + maccrd->crd_len)) || + (enccrd->crd_skip < maccrd->crd_skip)) { + err = EINVAL; + goto errout; + } + sskip = maccrd->crd_skip; + cpskip = dskip = enccrd->crd_skip; + stheend = maccrd->crd_len; + dtheend = enccrd->crd_len; + coffset = enccrd->crd_skip - maccrd->crd_skip; + cpoffset = cpskip + dtheend; +#ifdef UBSEC_DEBUG + DPRINTF("mac: skip %d, len %d, inject %d\n", + maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); + DPRINTF("enc: skip %d, len %d, inject %d\n", + enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); + DPRINTF("src: skip %d, len %d\n", sskip, stheend); + DPRINTF("dst: skip %d, len %d\n", dskip, dtheend); + DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", + coffset, stheend, cpskip, cpoffset); +#endif + } else { + cpskip = dskip = sskip = macoffset + encoffset; + dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; + cpoffset = cpskip + dtheend; + coffset = 0; + } + ctx.pc_offset = htole16(coffset >> 2); + +#if 0 + if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, + 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { + err = ENOMEM; + goto errout; + } +#endif + + if (crp->crp_flags & CRYPTO_F_SKBUF) { +#if 0 + if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, + q->q_src_m, BUS_DMA_NOWAIT) != 0) { + bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); + q->q_src_map = NULL; + err = ENOMEM; + goto errout; + } +#endif + err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len); + if (unlikely(err != 0)) + goto errout; + + } else if (crp->crp_flags & CRYPTO_F_IOV) { +#if 0 + if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, + q->q_src_io, BUS_DMA_NOWAIT) != 0) { + bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); + q->q_src_map = NULL; + err = ENOMEM; + goto errout; + } +#endif + err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len); + if (unlikely(err != 0)) + goto errout; + } + + /* + * Check alignment + */ + nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len); + + dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); + +#ifdef UBSEC_DEBUG + DPRINTF("src skip: %d\n", sskip); +#endif + for (i = j = 0; i < q->q_src_len; i++) { + struct ubsec_pktbuf *pb; + size_t packl = q->q_src_map[i].dma_size; + dma_addr_t packp = q->q_src_map[i].dma_paddr; + + if (sskip >= packl) { + sskip -= packl; + continue; + } + + packl -= sskip; + packp += sskip; + sskip = 0; + + /* maximum fragment size is 0xfffc */ + if (packl > 0xfffc) { + DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); + err = EIO; + goto errout; + } + + if (j == 0) + pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; + else + pb = &dmap->d_dma->d_sbuf[j - 1]; + + pb->pb_addr = htole32(packp); + + if (stheend) { + if (packl > stheend) { + pb->pb_len = htole32(stheend); + stheend = 0; + } else { + pb->pb_len = htole32(packl); + stheend -= packl; + } + } else + pb->pb_len = htole32(packl); + + if ((i + 1) == q->q_src_len) + pb->pb_next = 0; + else + pb->pb_next = htole32(dmap->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_sbuf[j])); + j++; + } + + if (enccrd == NULL && maccrd != NULL) { + /* Authentication only */ + dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; + dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; + dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = + htole32(dmap->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_macbuf[0])); +#ifdef UBSEC_DEBUG + DPRINTF("opkt: %x %x %x\n", + dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, + dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, + dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); +#endif + } else { + if (crp->crp_flags & CRYPTO_F_IOV) { + if (!nicealign) { + err = EINVAL; + goto errout; + } +#if 0 + if (bus_dmamap_create(sc->sc_dmat, 0xfff0, + UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, + &q->q_dst_map) != 0) { + err = ENOMEM; + goto errout; + } + if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, + q->q_dst_io, BUS_DMA_NOWAIT) != 0) { + bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); + q->q_dst_map = NULL; + goto errout; + } +#endif + + /* HW shall copy the result into the source memory */ + for(i = 0; i < q->q_src_len; i++) + q->q_dst_map[i] = q->q_src_map[i]; + + q->q_dst_len = q->q_src_len; + q->q_has_dst = 0; + + } else if (crp->crp_flags & CRYPTO_F_SKBUF) { + if (nicealign) { + + /* HW shall copy the result into the source memory */ + q->q_dst_m = q->q_src_m; + for(i = 0; i < q->q_src_len; i++) + q->q_dst_map[i] = q->q_src_map[i]; + + q->q_dst_len = q->q_src_len; + q->q_has_dst = 0; + + } else { +#ifdef NOTYET + int totlen, len; + struct sk_buff *m, *top, **mp; + + totlen = q->q_src_map->dm_mapsize; + if (q->q_src_m->m_flags & M_PKTHDR) { + len = MHLEN; + MGETHDR(m, M_DONTWAIT, MT_DATA); + } else { + len = MLEN; + MGET(m, M_DONTWAIT, MT_DATA); + } + if (m == NULL) { + err = ENOMEM; + goto errout; + } + if (len == MHLEN) + M_DUP_PKTHDR(m, q->q_src_m); + if (totlen >= MINCLSIZE) { + MCLGET(m, M_DONTWAIT); + if (m->m_flags & M_EXT) + len = MCLBYTES; + } + m->m_len = len; + top = NULL; + mp = ⊤ + + while (totlen > 0) { + if (top) { + MGET(m, M_DONTWAIT, MT_DATA); + if (m == NULL) { + m_freem(top); + err = ENOMEM; + goto errout; + } + len = MLEN; + } + if (top && totlen >= MINCLSIZE) { + MCLGET(m, M_DONTWAIT); + if (m->m_flags & M_EXT) + len = MCLBYTES; + } + m->m_len = len = min(totlen, len); + totlen -= len; + *mp = m; + mp = &m->m_next; + } + q->q_dst_m = top; + ubsec_mcopy(q->q_src_m, q->q_dst_m, + cpskip, cpoffset); + if (bus_dmamap_create(sc->sc_dmat, 0xfff0, + UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, + &q->q_dst_map) != 0) { + err = ENOMEM; + goto errout; + } + if (bus_dmamap_load_mbuf(sc->sc_dmat, + q->q_dst_map, q->q_dst_m, + BUS_DMA_NOWAIT) != 0) { + bus_dmamap_destroy(sc->sc_dmat, + q->q_dst_map); + q->q_dst_map = NULL; + err = ENOMEM; + goto errout; + } +#else + device_printf(sc->sc_dev, + "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", + __FILE__, __LINE__); + err = EINVAL; + goto errout; +#endif + } + } else { + err = EINVAL; + goto errout; + } + +#ifdef UBSEC_DEBUG + DPRINTF("dst skip: %d\n", dskip); +#endif + for (i = j = 0; i < q->q_dst_len; i++) { + struct ubsec_pktbuf *pb; + size_t packl = q->q_dst_map[i].dma_size; + dma_addr_t packp = q->q_dst_map[i].dma_paddr; + + if (dskip >= packl) { + dskip -= packl; + continue; + } + + packl -= dskip; + packp += dskip; + dskip = 0; + + if (packl > 0xfffc) { + DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); + err = EIO; + goto errout; + } + + if (j == 0) + pb = &dmap->d_dma->d_mcr.mcr_opktbuf; + else + pb = &dmap->d_dma->d_dbuf[j - 1]; + + pb->pb_addr = htole32(packp); + + if (dtheend) { + if (packl > dtheend) { + pb->pb_len = htole32(dtheend); + dtheend = 0; + } else { + pb->pb_len = htole32(packl); + dtheend -= packl; + } + } else + pb->pb_len = htole32(packl); + + if ((i + 1) == q->q_dst_len) { + if (maccrd) + /* Authentication: + * The last fragment of the output buffer + * contains the HMAC. */ + pb->pb_next = htole32(dmap->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_macbuf[0])); + else + pb->pb_next = 0; + } else + pb->pb_next = htole32(dmap->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_dbuf[j])); + j++; + } + } + + dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + + offsetof(struct ubsec_dmachunk, d_ctx)); + + if (sc->sc_flags & UBS_FLAGS_LONGCTX) { + /* new Broadcom cards with dynamic long command context structure */ + + if (enccrd != NULL && + enccrd->crd_alg == CRYPTO_AES_CBC) + { + struct ubsec_pktctx_aes128 *ctxaes128; + struct ubsec_pktctx_aes192 *ctxaes192; + struct ubsec_pktctx_aes256 *ctxaes256; + + switch(ses->ses_keysize) + { + /* AES 128bit */ + case 128: + ctxaes128 = (struct ubsec_pktctx_aes128 *) + (dmap->d_alloc.dma_vaddr + + offsetof(struct ubsec_dmachunk, d_ctx)); + + ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128)); + ctxaes128->pc_type = ctx.pc_type; + ctxaes128->pc_flags = ctx.pc_flags; + ctxaes128->pc_offset = ctx.pc_offset; + for (i = 0; i < 4; i++) + ctxaes128->pc_aeskey[i] = ctx.pc_key[i]; + for (i = 0; i < 5; i++) + ctxaes128->pc_hminner[i] = ctx.pc_hminner[i]; + for (i = 0; i < 5; i++) + ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i]; + for (i = 0; i < 4; i++) + ctxaes128->pc_iv[i] = ctx.pc_iv[i]; + break; + + /* AES 192bit */ + case 192: + ctxaes192 = (struct ubsec_pktctx_aes192 *) + (dmap->d_alloc.dma_vaddr + + offsetof(struct ubsec_dmachunk, d_ctx)); + + ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192)); + ctxaes192->pc_type = ctx.pc_type; + ctxaes192->pc_flags = ctx.pc_flags; + ctxaes192->pc_offset = ctx.pc_offset; + for (i = 0; i < 6; i++) + ctxaes192->pc_aeskey[i] = ctx.pc_key[i]; + for (i = 0; i < 5; i++) + ctxaes192->pc_hminner[i] = ctx.pc_hminner[i]; + for (i = 0; i < 5; i++) + ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i]; + for (i = 0; i < 4; i++) + ctxaes192->pc_iv[i] = ctx.pc_iv[i]; + break; + + /* AES 256bit */ + case 256: + ctxaes256 = (struct ubsec_pktctx_aes256 *) + (dmap->d_alloc.dma_vaddr + + offsetof(struct ubsec_dmachunk, d_ctx)); + + ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256)); + ctxaes256->pc_type = ctx.pc_type; + ctxaes256->pc_flags = ctx.pc_flags; + ctxaes256->pc_offset = ctx.pc_offset; + for (i = 0; i < 8; i++) + ctxaes256->pc_aeskey[i] = ctx.pc_key[i]; + for (i = 0; i < 5; i++) + ctxaes256->pc_hminner[i] = ctx.pc_hminner[i]; + for (i = 0; i < 5; i++) + ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i]; + for (i = 0; i < 4; i++) + ctxaes256->pc_iv[i] = ctx.pc_iv[i]; + break; + + } + } else { + /* + * [3]DES / MD5_HMAC / SHA1_HMAC + * + * MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without + * encryption. + */ + struct ubsec_pktctx_des *ctxdes; + + ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr + + offsetof(struct ubsec_dmachunk, d_ctx)); + + ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des)); + ctxdes->pc_type = ctx.pc_type; + ctxdes->pc_flags = ctx.pc_flags; + ctxdes->pc_offset = ctx.pc_offset; + for (i = 0; i < 6; i++) + ctxdes->pc_deskey[i] = ctx.pc_key[i]; + for (i = 0; i < 5; i++) + ctxdes->pc_hminner[i] = ctx.pc_hminner[i]; + for (i = 0; i < 5; i++) + ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i]; + ctxdes->pc_iv[0] = ctx.pc_iv[0]; + ctxdes->pc_iv[1] = ctx.pc_iv[1]; + } + } else + { + /* old Broadcom card with fixed small command context structure */ + + /* + * [3]DES / MD5_HMAC / SHA1_HMAC + */ + struct ubsec_pktctx *ctxs; + + ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr + + offsetof(struct ubsec_dmachunk, d_ctx)); + + /* transform generic context into small context */ + for (i = 0; i < 6; i++) + ctxs->pc_deskey[i] = ctx.pc_key[i]; + for (i = 0; i < 5; i++) + ctxs->pc_hminner[i] = ctx.pc_hminner[i]; + for (i = 0; i < 5; i++) + ctxs->pc_hmouter[i] = ctx.pc_hmouter[i]; + ctxs->pc_iv[0] = ctx.pc_iv[0]; + ctxs->pc_iv[1] = ctx.pc_iv[1]; + ctxs->pc_flags = ctx.pc_flags; + ctxs->pc_offset = ctx.pc_offset; + } + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("spin_lock_irqsave\n"); +#endif + spin_lock_irqsave(&sc->sc_ringmtx, flags); + //spin_lock_irq(&sc->sc_ringmtx); + + BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); + sc->sc_nqueue++; + ubsecstats.hst_ipackets++; + ubsecstats.hst_ibytes += stheend; + ubsec_feed(sc); + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("spin_unlock_irqrestore\n"); +#endif + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); + //spin_unlock_irq(&sc->sc_ringmtx); + + return (0); + +errout: + if (q != NULL) { +#ifdef NOTYET + if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) + m_freem(q->q_dst_m); +#endif + + if ((q->q_has_dst == 1) && q->q_dst_len > 0) { +#if 0 + bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); + bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); +#endif + dma_unmap(sc, q->q_dst_map, q->q_dst_len); + } + if (q->q_src_len > 0) { +#if 0 + bus_dmamap_unload(sc->sc_dmat, q->q_src_map); + bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); +#endif + dma_unmap(sc, q->q_src_map, q->q_src_len); + } + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("spin_lock_irqsave\n"); +#endif + spin_lock_irqsave(&sc->sc_ringmtx, flags); + //spin_lock_irq(&sc->sc_ringmtx); + + BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); + +#ifdef UBSEC_VERBOSE_DEBUG + DPRINTF("spin_unlock_irqrestore\n"); +#endif + spin_unlock_irqrestore(&sc->sc_ringmtx, flags); + //spin_unlock_irq(&sc->sc_ringmtx); + + } + if (err == EINVAL) + ubsecstats.hst_invalid++; + else + ubsecstats.hst_nomem++; +errout2: + crp->crp_etype = err; + crypto_done(crp); + +#ifdef UBSEC_DEBUG + DPRINTF("%s() err = %x\n", __FUNCTION__, err); +#endif + + return (0); +} + +void +ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) +{ + struct cryptop *crp = (struct cryptop *)q->q_crp; + struct cryptodesc *crd; + struct ubsec_dma *dmap = q->q_dma; + int ivsize = 8; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + ubsecstats.hst_opackets++; + ubsecstats.hst_obytes += dmap->d_alloc.dma_size; + +#if 0 + bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, + dmap->d_alloc.dma_map->dm_mapsize, + BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); + if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { + bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, + 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); + bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); + } + bus_dmamap_sync(sc->sc_dmat, q->q_src_map, + 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->sc_dmat, q->q_src_map); + bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); +#endif + + if ((q->q_has_dst == 1) && q->q_dst_len > 0) + dma_unmap(sc, q->q_dst_map, q->q_dst_len); + + dma_unmap(sc, q->q_src_map, q->q_src_len); + +#ifdef NOTYET + if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) { + m_freem(q->q_src_m); + crp->crp_buf = (caddr_t)q->q_dst_m; + } +#endif + + /* copy out IV for future use */ + if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { + for (crd = crp->crp_desc; crd; crd = crd->crd_next) { + if (crd->crd_alg != CRYPTO_DES_CBC && + crd->crd_alg != CRYPTO_3DES_CBC && + crd->crd_alg != CRYPTO_AES_CBC) + continue; + + if (crd->crd_alg == CRYPTO_AES_CBC) + ivsize = 16; + else + ivsize = 8; + + if (crp->crp_flags & CRYPTO_F_SKBUF) +#if 0 + m_copydata((struct sk_buff *)crp->crp_buf, + crd->crd_skip + crd->crd_len - 8, 8, + (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); +#endif + crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, + crd->crd_skip + crd->crd_len - ivsize, ivsize, + (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); + + else if (crp->crp_flags & CRYPTO_F_IOV) { +#if 0 + cuio_copydata((struct uio *)crp->crp_buf, + crd->crd_skip + crd->crd_len - 8, 8, + (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); +#endif + crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, + crd->crd_skip + crd->crd_len - ivsize, ivsize, + (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); + + } + break; + } + } + + for (crd = crp->crp_desc; crd; crd = crd->crd_next) { + if (crd->crd_alg != CRYPTO_MD5_HMAC && + crd->crd_alg != CRYPTO_SHA1_HMAC) + continue; +#if 0 + if (crp->crp_flags & CRYPTO_F_SKBUF) + m_copyback((struct sk_buff *)crp->crp_buf, + crd->crd_inject, 12, + dmap->d_dma->d_macbuf); +#endif +#if 0 + /* BUG? it does not honor the mac len.. */ + crypto_copyback(crp->crp_flags, crp->crp_buf, + crd->crd_inject, 12, + (caddr_t)dmap->d_dma->d_macbuf); +#endif + crypto_copyback(crp->crp_flags, crp->crp_buf, + crd->crd_inject, + sc->sc_sessions[q->q_sesn].ses_mlen, + (caddr_t)dmap->d_dma->d_macbuf); +#if 0 + else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) + bcopy((caddr_t)dmap->d_dma->d_macbuf, + crp->crp_mac, 12); +#endif + break; + } + BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); + crypto_done(crp); +} + +void +ubsec_mcopy(struct sk_buff *srcm, struct sk_buff *dstm, int hoffset, int toffset) +{ + int i, j, dlen, slen; + caddr_t dptr, sptr; + + j = 0; + sptr = srcm->data; + slen = srcm->len; + dptr = dstm->data; + dlen = dstm->len; + + while (1) { + for (i = 0; i < min(slen, dlen); i++) { + if (j < hoffset || j >= toffset) + *dptr++ = *sptr++; + slen--; + dlen--; + j++; + } + if (slen == 0) { + srcm = srcm->next; + if (srcm == NULL) + return; + sptr = srcm->data; + slen = srcm->len; + } + if (dlen == 0) { + dstm = dstm->next; + if (dstm == NULL) + return; + dptr = dstm->data; + dlen = dstm->len; + } + } +} + +int +ubsec_dma_malloc(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma, + size_t size, int mapflags) +{ + dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv, + size, &dma->dma_paddr, GFP_KERNEL); + + if (likely(dma->dma_vaddr)) + { + dma->dma_size = size; + return (0); + } + + DPRINTF("could not allocate %d bytes of coherent memory.\n", size); + + return (1); +} + +void +ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) +{ + dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr, + dma->dma_paddr); +} + +/* + * Resets the board. Values in the regesters are left as is + * from the reset (i.e. initial values are assigned elsewhere). + */ +void +ubsec_reset_board(struct ubsec_softc *sc) +{ + volatile u_int32_t ctrl; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + DPRINTF("Send reset signal to chip.\n"); + + ctrl = READ_REG(sc, BS_CTRL); + ctrl |= BS_CTRL_RESET; + WRITE_REG(sc, BS_CTRL, ctrl); + + /* + * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us + */ + DELAY(10); +} + +/* + * Init Broadcom registers + */ +void +ubsec_init_board(struct ubsec_softc *sc) +{ + u_int32_t ctrl; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + DPRINTF("Initialize chip.\n"); + + ctrl = READ_REG(sc, BS_CTRL); + ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); + ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT | BS_CTRL_DMAERR; + + WRITE_REG(sc, BS_CTRL, ctrl); + + /* Set chip capabilities (BCM5365P) */ + sc->sc_flags |= UBS_FLAGS_LONGCTX | UBS_FLAGS_AES; +} + +/* + * Clean up after a chip crash. + * It is assumed that the caller has spin_lock_irq(sc_ringmtx). + */ +void +ubsec_cleanchip(struct ubsec_softc *sc) +{ + struct ubsec_q *q; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + DPRINTF("Clean up queues after chip crash.\n"); + + while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { + q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); + BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); + ubsec_free_q(sc, q); + } +} + +/* + * free a ubsec_q + * It is assumed that the caller has spin_lock_irq(sc_ringmtx). + */ +int +ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) +{ + struct ubsec_q *q2; + struct cryptop *crp; + int npkts; + int i; + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + + npkts = q->q_nstacked_mcrs; + + for (i = 0; i < npkts; i++) { + if(q->q_stacked_mcr[i]) { + q2 = q->q_stacked_mcr[i]; + + if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) +#ifdef NOTYET + m_freem(q2->q_dst_m); +#else + printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); +#endif + + crp = (struct cryptop *)q2->q_crp; + + BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); + + crp->crp_etype = EFAULT; + crypto_done(crp); + } else { + break; + } + } + + /* + * Free header MCR + */ + if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) +#ifdef NOTYET + m_freem(q->q_dst_m); +#else + printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); +#endif + + crp = (struct cryptop *)q->q_crp; + + BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); + + crp->crp_etype = EFAULT; + crypto_done(crp); + return(0); +} + +/* + * Routine to reset the chip and clean up. + * It is assumed that the caller has spin_lock_irq(sc_ringmtx). + */ +void +ubsec_totalreset(struct ubsec_softc *sc) +{ + +#ifdef UBSEC_DEBUG + DPRINTF("%s()\n", __FUNCTION__); +#endif + DPRINTF("initiate total chip reset.. \n"); + ubsec_reset_board(sc); + ubsec_init_board(sc); + ubsec_cleanchip(sc); +} + +void +ubsec_dump_pb(struct ubsec_pktbuf *pb) +{ + printf("addr 0x%x (0x%x) next 0x%x\n", + pb->pb_addr, pb->pb_len, pb->pb_next); +} + +void +ubsec_dump_mcr(struct ubsec_mcr *mcr) +{ + struct ubsec_mcr_add *ma; + int i; + + printf("MCR:\n"); + printf(" pkts: %u, flags 0x%x\n", + letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); + ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; + for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { + printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, + letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), + letoh16(ma->mcr_reserved)); + printf(" %d: ipkt ", i); + ubsec_dump_pb(&ma->mcr_ipktbuf); + printf(" %d: opkt ", i); + ubsec_dump_pb(&ma->mcr_opktbuf); + ma++; + } + printf("END MCR\n"); +} + +static int __init mod_init(void) { + return ssb_driver_register(&ubsec_ssb_driver); +} + +static void __exit mod_exit(void) { + ssb_driver_unregister(&ubsec_ssb_driver); +} + +module_init(mod_init); +module_exit(mod_exit); + +// Meta information +MODULE_AUTHOR("Daniel Mueller "); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core"); +MODULE_VERSION(DRV_MODULE_VERSION); + diff --git a/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsecreg.h b/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsecreg.h new file mode 100644 index 0000000..dafac5b --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsecreg.h @@ -0,0 +1,233 @@ + +/* + * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) + * Copyright (c) 2000 Theo de Raadt + * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ + +/* + * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband + * Security "uBSec" chip. Definitions from revision 2.8 of the product + * datasheet. + */ + +#define BS_BAR 0x10 /* DMA base address register */ +#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ +#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ + +#define UBS_PCI_RTY_SHIFT 8 +#define UBS_PCI_RTY_MASK 0xff +#define UBS_PCI_RTY(misc) \ + (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) + +#define UBS_PCI_TOUT_SHIFT 0 +#define UBS_PCI_TOUT_MASK 0xff +#define UBS_PCI_TOUT(misc) \ + (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) + +/* + * DMA Control & Status Registers (offset from BS_BAR) + */ +#define BS_MCR1 0x20 /* DMA Master Command Record 1 */ +#define BS_CTRL 0x24 /* DMA Control */ +#define BS_STAT 0x28 /* DMA Status */ +#define BS_ERR 0x2c /* DMA Error Address */ +#define BS_DEV_ID 0x34 /* IPSec Device ID */ + +/* BS_CTRL - DMA Control */ +#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ +#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ +#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ +#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ +#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ +#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ +#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ +#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */ +#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ +#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ +#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ +#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ +#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ +#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ +#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) + +/* BS_STAT - DMA Status */ +#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ +#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ +#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ +#define BS_STAT_DMAERR 0x10000000 /* DMA error */ +#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ +#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ +#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ +#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ + +/* BS_ERR - DMA Error Address */ +#define BS_ERR_ADDR 0xfffffffc /* error address mask */ +#define BS_ERR_READ 0x00000002 /* fault was on read */ + +struct ubsec_pktctx { + u_int32_t pc_deskey[6]; /* 3DES key */ + u_int32_t pc_hminner[5]; /* hmac inner state */ + u_int32_t pc_hmouter[5]; /* hmac outer state */ + u_int32_t pc_iv[2]; /* [3]DES iv */ + u_int16_t pc_flags; /* flags, below */ + u_int16_t pc_offset; /* crypto offset */ +} __attribute__ ((packed)); + +#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ +#define UBS_PKTCTX_ENC_AES 0x8000 /* use aes */ +#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ +#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ +#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ +#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ +#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ +#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ +#define UBS_PKTCTX_AES128 0x0 /* AES 128bit keys */ +#define UBS_PKTCTX_AES192 0x100 /* AES 192bit keys */ +#define UBS_PKTCTX_AES256 0x200 /* AES 256bit keys */ + +struct ubsec_pktctx_des { + volatile u_int16_t pc_len; /* length of ctx struct */ + volatile u_int16_t pc_type; /* context type */ + volatile u_int16_t pc_flags; /* flags, same as above */ + volatile u_int16_t pc_offset; /* crypto/auth offset */ + volatile u_int32_t pc_deskey[6]; /* 3DES key */ + volatile u_int32_t pc_iv[2]; /* [3]DES iv */ + volatile u_int32_t pc_hminner[5]; /* hmac inner state */ + volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ +} __attribute__ ((packed)); + +struct ubsec_pktctx_aes128 { + volatile u_int16_t pc_len; /* length of ctx struct */ + volatile u_int16_t pc_type; /* context type */ + volatile u_int16_t pc_flags; /* flags, same as above */ + volatile u_int16_t pc_offset; /* crypto/auth offset */ + volatile u_int32_t pc_aeskey[4]; /* AES 128bit key */ + volatile u_int32_t pc_iv[4]; /* AES iv */ + volatile u_int32_t pc_hminner[5]; /* hmac inner state */ + volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ +} __attribute__ ((packed)); + +struct ubsec_pktctx_aes192 { + volatile u_int16_t pc_len; /* length of ctx struct */ + volatile u_int16_t pc_type; /* context type */ + volatile u_int16_t pc_flags; /* flags, same as above */ + volatile u_int16_t pc_offset; /* crypto/auth offset */ + volatile u_int32_t pc_aeskey[6]; /* AES 192bit key */ + volatile u_int32_t pc_iv[4]; /* AES iv */ + volatile u_int32_t pc_hminner[5]; /* hmac inner state */ + volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ +} __attribute__ ((packed)); + +struct ubsec_pktctx_aes256 { + volatile u_int16_t pc_len; /* length of ctx struct */ + volatile u_int16_t pc_type; /* context type */ + volatile u_int16_t pc_flags; /* flags, same as above */ + volatile u_int16_t pc_offset; /* crypto/auth offset */ + volatile u_int32_t pc_aeskey[8]; /* AES 256bit key */ + volatile u_int32_t pc_iv[4]; /* AES iv */ + volatile u_int32_t pc_hminner[5]; /* hmac inner state */ + volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ +} __attribute__ ((packed)); + +#define UBS_PKTCTX_TYPE_IPSEC_DES 0x0000 +#define UBS_PKTCTX_TYPE_IPSEC_AES 0x0040 + +struct ubsec_pktbuf { + volatile u_int32_t pb_addr; /* address of buffer start */ + volatile u_int32_t pb_next; /* pointer to next pktbuf */ + volatile u_int32_t pb_len; /* packet length */ +} __attribute__ ((packed)); +#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ + +struct ubsec_mcr { + volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ + volatile u_int16_t mcr_flags; /* mcr flags (below) */ + volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ + struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ + volatile u_int16_t mcr_reserved; + volatile u_int16_t mcr_pktlen; + struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ +} __attribute__ ((packed)); + +struct ubsec_mcr_add { + volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ + struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ + volatile u_int16_t mcr_reserved; + volatile u_int16_t mcr_pktlen; + struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ +} __attribute__ ((packed)); + +#define UBS_MCR_DONE 0x0001 /* mcr has been processed */ +#define UBS_MCR_ERROR 0x0002 /* error in processing */ +#define UBS_MCR_ERRORCODE 0xff00 /* error type */ + +struct ubsec_ctx_keyop { + volatile u_int16_t ctx_len; /* command length */ + volatile u_int16_t ctx_op; /* operation code */ + volatile u_int8_t ctx_pad[60]; /* padding */ +} __attribute__ ((packed)); +#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ +#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ +#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ +#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ +#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ +#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ +#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ +#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ +#define UBS_CTXOP_MODADD 0x43 /* modular addition */ +#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ +#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ +#define UBS_CTXOP_MODRED 0x46 /* modular reduction */ +#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ +#define UBS_CTXOP_MODINV 0x48 /* modular inverse */ + +struct ubsec_ctx_rngbypass { + volatile u_int16_t rbp_len; /* command length, 64 */ + volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ + volatile u_int8_t rbp_pad[60]; /* padding */ +} __attribute__ ((packed)); + +/* modexp: C = (M ^ E) mod N */ +struct ubsec_ctx_modexp { + volatile u_int16_t me_len; /* command length */ + volatile u_int16_t me_op; /* modexp, 0x47 */ + volatile u_int16_t me_E_len; /* E (bits) */ + volatile u_int16_t me_N_len; /* N (bits) */ + u_int8_t me_N[2048/8]; /* N */ +} __attribute__ ((packed)); + +struct ubsec_ctx_rsapriv { + volatile u_int16_t rpr_len; /* command length */ + volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ + volatile u_int16_t rpr_q_len; /* q (bits) */ + volatile u_int16_t rpr_p_len; /* p (bits) */ + u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ + /* p, q, dp, dq, pinv */ +} __attribute__ ((packed)); diff --git a/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsecvar.h b/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsecvar.h new file mode 100644 index 0000000..c808f95 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/ubsec_ssb/ubsecvar.h @@ -0,0 +1,228 @@ + +/* + * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) + * Copyright (c) 2000 Theo de Raadt + * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Effort sponsored in part by the Defense Advanced Research Projects + * Agency (DARPA) and Air Force Research Laboratory, Air Force + * Materiel Command, USAF, under agreement number F30602-01-2-0537. + * + */ + +/* Maximum queue length */ +#ifndef UBS_MAX_NQUEUE +#define UBS_MAX_NQUEUE 60 +#endif + +#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ + +#ifndef UBS_MAX_AGGR +#define UBS_MAX_AGGR 5 /* Maximum aggregation count */ +#endif + +#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) +#define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff) +#define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) + +#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */ +#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */ +#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */ + +#define DEFAULT_HMAC_LEN 12 + +struct ubsec_dma_alloc { + dma_addr_t dma_paddr; + void *dma_vaddr; + /* + bus_dmamap_t dma_map; + bus_dma_segment_t dma_seg; + */ + size_t dma_size; + /* + int dma_nseg; + */ +}; + +struct ubsec_q2 { + BSD_SIMPLEQ_ENTRY(ubsec_q2) q_next; + struct ubsec_dma_alloc q_mcr; + struct ubsec_dma_alloc q_ctx; + u_int q_type; +}; + +struct ubsec_q2_rng { + struct ubsec_q2 rng_q; + struct ubsec_dma_alloc rng_buf; + int rng_used; +}; + +/* C = (M ^ E) mod N */ +#define UBS_MODEXP_PAR_M 0 +#define UBS_MODEXP_PAR_E 1 +#define UBS_MODEXP_PAR_N 2 +struct ubsec_q2_modexp { + struct ubsec_q2 me_q; + struct cryptkop * me_krp; + struct ubsec_dma_alloc me_M; + struct ubsec_dma_alloc me_E; + struct ubsec_dma_alloc me_C; + struct ubsec_dma_alloc me_epb; + int me_modbits; + int me_shiftbits; + int me_normbits; +}; + +#define UBS_RSAPRIV_PAR_P 0 +#define UBS_RSAPRIV_PAR_Q 1 +#define UBS_RSAPRIV_PAR_DP 2 +#define UBS_RSAPRIV_PAR_DQ 3 +#define UBS_RSAPRIV_PAR_PINV 4 +#define UBS_RSAPRIV_PAR_MSGIN 5 +#define UBS_RSAPRIV_PAR_MSGOUT 6 +struct ubsec_q2_rsapriv { + struct ubsec_q2 rpr_q; + struct cryptkop * rpr_krp; + struct ubsec_dma_alloc rpr_msgin; + struct ubsec_dma_alloc rpr_msgout; +}; + +#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */ + +struct ubsec_dmachunk { + struct ubsec_mcr d_mcr; + struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1]; + struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1]; + struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1]; + u_int32_t d_macbuf[5]; + union { + struct ubsec_pktctx_aes256 ctxaes256; + struct ubsec_pktctx_aes192 ctxaes192; + struct ubsec_pktctx_des ctxdes; + struct ubsec_pktctx_aes128 ctxaes128; + struct ubsec_pktctx ctx; + } d_ctx; +}; + +struct ubsec_dma { + BSD_SIMPLEQ_ENTRY(ubsec_dma) d_next; + struct ubsec_dmachunk *d_dma; + struct ubsec_dma_alloc d_alloc; +}; + +#define UBS_FLAGS_KEY 0x01 /* has key accelerator */ +#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */ +#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ +#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ +#define UBS_FLAGS_RNG 0x10 /* hardware rng */ +#define UBS_FLAGS_AES 0x20 /* hardware AES support */ + +struct ubsec_q { + BSD_SIMPLEQ_ENTRY(ubsec_q) q_next; + int q_nstacked_mcrs; + struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1]; + struct cryptop *q_crp; + struct ubsec_dma *q_dma; + + //struct mbuf *q_src_m, *q_dst_m; + struct sk_buff *q_src_m, *q_dst_m; + struct uio *q_src_io, *q_dst_io; + + /* + bus_dmamap_t q_src_map; + bus_dmamap_t q_dst_map; + */ + + /* DMA addresses for In-/Out packages */ + int q_src_len; + int q_dst_len; + struct ubsec_dma_alloc q_src_map[UBS_MAX_SCATTER]; + struct ubsec_dma_alloc q_dst_map[UBS_MAX_SCATTER]; + int q_has_dst; + + int q_sesn; + int q_flags; +}; + +struct ubsec_softc { + softc_device_decl sc_dev; + struct ssb_device *sdev; /* device backpointer */ + + struct device *sc_dv; /* generic device */ + void *sc_ih; /* interrupt handler cookie */ + int sc_flags; /* device specific flags */ + u_int32_t sc_statmask; /* interrupt status mask */ + int32_t sc_cid; /* crypto tag */ + BSD_SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ + int sc_nqueue; /* count enqueued, mcr1 */ + BSD_SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ + BSD_SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */ + BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ + int sc_nqueue2; /* count enqueued, mcr2 */ + BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ + int sc_nsessions; /* # of sessions */ + struct ubsec_session *sc_sessions; /* sessions */ + int sc_rnghz; /* rng poll time */ + struct ubsec_q2_rng sc_rng; + struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE]; + struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE]; + BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */ + spinlock_t sc_ringmtx; /* PE ring lock */ +}; + +#define UBSEC_QFLAGS_COPYOUTIV 0x1 + +struct ubsec_session { + u_int32_t ses_used; + u_int32_t ses_key[8]; /* 3DES/AES key */ + u_int32_t ses_hminner[5]; /* hmac inner state */ + u_int32_t ses_hmouter[5]; /* hmac outer state */ + u_int32_t ses_iv[4]; /* [3]DES/AES iv */ + u_int32_t ses_keysize; /* AES key size */ + u_int32_t ses_mlen; /* hmac/hash length */ +}; + +struct ubsec_stats { + u_int64_t hst_ibytes; + u_int64_t hst_obytes; + u_int32_t hst_ipackets; + u_int32_t hst_opackets; + u_int32_t hst_invalid; + u_int32_t hst_nomem; + u_int32_t hst_queuefull; + u_int32_t hst_dmaerr; + u_int32_t hst_mcrerr; + u_int32_t hst_nodmafree; +}; + +struct ubsec_generic_ctx { + u_int32_t pc_key[8]; /* [3]DES/AES key */ + u_int32_t pc_hminner[5]; /* hmac inner state */ + u_int32_t pc_hmouter[5]; /* hmac outer state */ + u_int32_t pc_iv[4]; /* [3]DES/AES iv */ + u_int16_t pc_flags; /* flags, below */ + u_int16_t pc_offset; /* crypto offset */ + u_int16_t pc_type; /* Cryptographic operation */ +}; + diff --git a/target/linux/generic/files/crypto/ocf/uio.h b/target/linux/generic/files/crypto/ocf/uio.h new file mode 100644 index 0000000..03a6249 --- /dev/null +++ b/target/linux/generic/files/crypto/ocf/uio.h @@ -0,0 +1,54 @@ +#ifndef _OCF_UIO_H_ +#define _OCF_UIO_H_ + +#include + +/* + * The linux uio.h doesn't have all we need. To be fully api compatible + * with the BSD cryptodev, we need to keep this around. Perhaps this can + * be moved back into the linux/uio.h + * + * Linux port done by David McCullough + * Copyright (C) 2006-2010 David McCullough + * Copyright (C) 2004-2005 Intel Corporation. + * + * LICENSE TERMS + * + * The free distribution and use of this software in both source and binary + * form is allowed (with or without changes) provided that: + * + * 1. distributions of this source code include the above copyright + * notice, this list of conditions and the following disclaimer; + * + * 2. distributions in binary form include the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other associated materials; + * + * 3. the copyright holder's name is not used to endorse products + * built using this software without specific written permission. + * + * ALTERNATIVELY, provided that this notice is retained in full, this product + * may be distributed under the terms of the GNU General Public License (GPL), + * in which case the provisions of the GPL apply INSTEAD OF those given above. + * + * DISCLAIMER + * + * This software is provided 'as is' with no explicit or implied warranties + * in respect of its properties, including, but not limited to, correctness + * and/or fitness for purpose. + * --------------------------------------------------------------------------- + */ + +struct uio { + struct iovec *uio_iov; + int uio_iovcnt; + off_t uio_offset; + int uio_resid; +#if 0 + enum uio_seg uio_segflg; + enum uio_rw uio_rw; + struct thread *uio_td; +#endif +}; + +#endif diff --git a/target/linux/generic/files/drivers/leds/ledtrig-morse.c b/target/linux/generic/files/drivers/leds/ledtrig-morse.c new file mode 100644 index 0000000..bc58afe --- /dev/null +++ b/target/linux/generic/files/drivers/leds/ledtrig-morse.c @@ -0,0 +1,366 @@ +/* + * LED Morse Trigger + * + * Copyright (C) 2007 Gabor Juhos + * + * This file was based on: drivers/led/ledtrig-timer.c + * Copyright 2005-2006 Openedhand Ltd. + * Author: Richard Purdie + * + * also based on the patch '[PATCH] 2.5.59 morse code panics' posted + * in the LKML by Tomas Szepe at Thu, 30 Jan 2003 + * Copyright (C) 2002 Andrew Rodland + * Copyright (C) 2003 Tomas Szepe + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "leds.h" + +#define MORSE_DELAY_BASE (HZ/2) + +#define MORSE_STATE_BLINK_START 0 +#define MORSE_STATE_BLINK_STOP 1 + +#define MORSE_DIT_LEN 1 +#define MORSE_DAH_LEN 3 +#define MORSE_SPACE_LEN 7 + +struct morse_trig_data { + unsigned long delay; + char *msg; + + unsigned char morse; + unsigned char state; + char *msgpos; + struct timer_list timer; +}; + +const unsigned char morsetable[] = { + 0122, 0, 0310, 0, 0, 0163, /* "#$%&' */ + 055, 0155, 0, 0, 0163, 0141, 0152, 0051, /* ()*+,-./ */ + 077, 076, 074, 070, 060, 040, 041, 043, 047, 057, /* 0-9 */ + 0107, 0125, 0, 0061, 0, 0114, 0, /* :;<=>?@ */ + 006, 021, 025, 011, 002, 024, 013, 020, 004, /* A-I */ + 036, 015, 022, 007, 005, 017, 026, 033, 012, /* J-R */ + 010, 003, 014, 030, 016, 031, 035, 023, /* S-Z */ + 0, 0, 0, 0, 0154 /* [\]^_ */ +}; + +static inline unsigned char tomorse(char c) { + if (c >= 'a' && c <= 'z') + c = c - 'a' + 'A'; + if (c >= '"' && c <= '_') { + return morsetable[c - '"']; + } else + return 0; +} + +static inline unsigned long dit_len(struct morse_trig_data *morse_data) +{ + return MORSE_DIT_LEN*morse_data->delay; +} + +static inline unsigned long dah_len(struct morse_trig_data *morse_data) +{ + return MORSE_DAH_LEN*morse_data->delay; +} + +static inline unsigned long space_len(struct morse_trig_data *morse_data) +{ + return MORSE_SPACE_LEN*morse_data->delay; +} + +static void morse_timer_function(unsigned long data) +{ + struct led_classdev *led_cdev = (struct led_classdev *)data; + struct morse_trig_data *morse_data = led_cdev->trigger_data; + unsigned long brightness = LED_OFF; + unsigned long delay = 0; + + if (!morse_data->msg) + goto set_led; + + switch (morse_data->state) { + case MORSE_STATE_BLINK_START: + /* Starting a new blink. We have a valid code in morse. */ + delay = (morse_data->morse & 001) ? dah_len(morse_data): + dit_len(morse_data); + brightness = LED_FULL; + morse_data->state = MORSE_STATE_BLINK_STOP; + morse_data->morse >>= 1; + break; + case MORSE_STATE_BLINK_STOP: + /* Coming off of a blink. */ + morse_data->state = MORSE_STATE_BLINK_START; + + if (morse_data->morse > 1) { + /* Not done yet, just a one-dit pause. */ + delay = dit_len(morse_data); + break; + } + + /* Get a new char, figure out how much space. */ + /* First time through */ + if (!morse_data->msgpos) + morse_data->msgpos = (char *)morse_data->msg; + + if (!*morse_data->msgpos) { + /* Repeating */ + morse_data->msgpos = (char *)morse_data->msg; + delay = space_len(morse_data); + } else { + /* Inter-letter space */ + delay = dah_len(morse_data); + } + + if (!(morse_data->morse = tomorse(*morse_data->msgpos))) { + delay = space_len(morse_data); + /* And get us back here */ + morse_data->state = MORSE_STATE_BLINK_STOP; + } + morse_data->msgpos++; + break; + } + + mod_timer(&morse_data->timer, jiffies + msecs_to_jiffies(delay)); + +set_led: + led_set_brightness(led_cdev, brightness); +} + +static ssize_t _morse_delay_show(struct led_classdev *led_cdev, char *buf) +{ + struct morse_trig_data *morse_data = led_cdev->trigger_data; + + sprintf(buf, "%lu\n", morse_data->delay); + + return strlen(buf) + 1; +} + +static ssize_t _morse_delay_store(struct led_classdev *led_cdev, + const char *buf, size_t size) +{ + struct morse_trig_data *morse_data = led_cdev->trigger_data; + char *after; + unsigned long state = simple_strtoul(buf, &after, 10); + size_t count = after - buf; + int ret = -EINVAL; + + if (*after && isspace(*after)) + count++; + + if (count == size) { + morse_data->delay = state; + mod_timer(&morse_data->timer, jiffies + 1); + ret = count; + } + + return ret; +} + +static ssize_t _morse_msg_show(struct led_classdev *led_cdev, char *buf) +{ + struct morse_trig_data *morse_data = led_cdev->trigger_data; + + if (!morse_data->msg) + sprintf(buf, "\n"); + else + sprintf(buf, "%s\n", morse_data->msg); + + return strlen(buf) + 1; +} + +static ssize_t _morse_msg_store(struct led_classdev *led_cdev, + const char *buf, size_t size) +{ + struct morse_trig_data *morse_data = led_cdev->trigger_data; + char *m; + + m = kmalloc(size, GFP_KERNEL); + if (!m) + return -ENOMEM; + + memcpy(m,buf,size); + m[size]='\0'; + + if (morse_data->msg) + kfree(morse_data->msg); + + morse_data->msg = m; + morse_data->msgpos = NULL; + morse_data->state = MORSE_STATE_BLINK_STOP; + + mod_timer(&morse_data->timer, jiffies + 1); + + return size; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23) +static ssize_t morse_delay_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + + return _morse_delay_show(led_cdev, buf); +} + +static ssize_t morse_delay_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + + return _morse_delay_store(led_cdev, buf, size); +} + +static ssize_t morse_msg_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + + return _morse_msg_show(led_cdev, buf); +} + +static ssize_t morse_msg_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + + return _morse_msg_store(led_cdev, buf, size); +} + +static DEVICE_ATTR(delay, 0644, morse_delay_show, morse_delay_store); +static DEVICE_ATTR(message, 0644, morse_msg_show, morse_msg_store); + +#define led_device_create_file(leddev, attr) \ + device_create_file(leddev->dev, &dev_attr_ ## attr) +#define led_device_remove_file(leddev, attr) \ + device_remove_file(leddev->dev, &dev_attr_ ## attr) + +#else +static ssize_t morse_delay_show(struct class_device *dev, char *buf) +{ + struct led_classdev *led_cdev = class_get_devdata(dev); + + return _morse_delay_show(led_cdev, buf); +} + +static ssize_t morse_delay_store(struct class_device *dev, const char *buf, + size_t size) +{ + struct led_classdev *led_cdev = class_get_devdata(dev); + + return _morse_delay_store(led_cdev, buf, size); +} + +static ssize_t morse_msg_show(struct class_device *dev, char *buf) +{ + struct led_classdev *led_cdev = class_get_devdata(dev); + + return _morse_msg_show(led_cdev, buf); +} + +static ssize_t morse_msg_store(struct class_device *dev, const char *buf, + size_t size) +{ + struct led_classdev *led_cdev = class_get_devdata(dev); + + return _morse_msg_store(led_cdev, buf, size); +} + +static CLASS_DEVICE_ATTR(delay, 0644, morse_delay_show, morse_delay_store); +static CLASS_DEVICE_ATTR(message, 0644, morse_msg_show, morse_msg_store); + +#define led_device_create_file(leddev, attr) \ + class_device_create_file(leddev->class_dev, &class_device_attr_ ## attr) +#define led_device_remove_file(leddev, attr) \ + class_device_remove_file(leddev->class_dev, &class_device_attr_ ## attr) + +#endif + +static void morse_trig_activate(struct led_classdev *led_cdev) +{ + struct morse_trig_data *morse_data; + int rc; + + morse_data = kzalloc(sizeof(*morse_data), GFP_KERNEL); + if (!morse_data) + return; + + morse_data->delay = MORSE_DELAY_BASE; + init_timer(&morse_data->timer); + morse_data->timer.function = morse_timer_function; + morse_data->timer.data = (unsigned long)led_cdev; + + rc = led_device_create_file(led_cdev, delay); + if (rc) goto err; + + rc = led_device_create_file(led_cdev, message); + if (rc) goto err_delay; + + led_cdev->trigger_data = morse_data; + + return; + +err_delay: + led_device_remove_file(led_cdev, delay); +err: + kfree(morse_data); +} + +static void morse_trig_deactivate(struct led_classdev *led_cdev) +{ + struct morse_trig_data *morse_data = led_cdev->trigger_data; + + if (!morse_data) + return; + + led_device_remove_file(led_cdev, message); + led_device_remove_file(led_cdev, delay); + + del_timer_sync(&morse_data->timer); + if (morse_data->msg) + kfree(morse_data->msg); + + kfree(morse_data); +} + +static struct led_trigger morse_led_trigger = { + .name = "morse", + .activate = morse_trig_activate, + .deactivate = morse_trig_deactivate, +}; + +static int __init morse_trig_init(void) +{ + return led_trigger_register(&morse_led_trigger); +} + +static void __exit morse_trig_exit(void) +{ + led_trigger_unregister(&morse_led_trigger); +} + +module_init(morse_trig_init); +module_exit(morse_trig_exit); + +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION("Morse LED trigger"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/files/drivers/leds/ledtrig-netdev.c b/target/linux/generic/files/drivers/leds/ledtrig-netdev.c new file mode 100644 index 0000000..4a20d7c --- /dev/null +++ b/target/linux/generic/files/drivers/leds/ledtrig-netdev.c @@ -0,0 +1,438 @@ +/* + * LED Kernel Netdev Trigger + * + * Toggles the LED to reflect the link and traffic state of a named net device + * + * Copyright 2007 Oliver Jowett + * + * Derived from ledtrig-timer.c which is: + * Copyright 2005-2006 Openedhand Ltd. + * Author: Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "leds.h" + +/* + * Configurable sysfs attributes: + * + * device_name - network device name to monitor + * + * interval - duration of LED blink, in milliseconds + * + * mode - either "none" (LED is off) or a space separated list of one or more of: + * link: LED's normal state reflects whether the link is up (has carrier) or not + * tx: LED blinks on transmitted data + * rx: LED blinks on receive data + * + * Some suggestions: + * + * Simple link status LED: + * $ echo netdev >someled/trigger + * $ echo eth0 >someled/device_name + * $ echo link >someled/mode + * + * Ethernet-style link/activity LED: + * $ echo netdev >someled/trigger + * $ echo eth0 >someled/device_name + * $ echo "link tx rx" >someled/mode + * + * Modem-style tx/rx LEDs: + * $ echo netdev >led1/trigger + * $ echo ppp0 >led1/device_name + * $ echo tx >led1/mode + * $ echo netdev >led2/trigger + * $ echo ppp0 >led2/device_name + * $ echo rx >led2/mode + * + */ + +#define MODE_LINK 1 +#define MODE_TX 2 +#define MODE_RX 4 + +struct led_netdev_data { + rwlock_t lock; + + struct timer_list timer; + struct notifier_block notifier; + + struct led_classdev *led_cdev; + struct net_device *net_dev; + + char device_name[IFNAMSIZ]; + unsigned interval; + unsigned mode; + unsigned link_up; + unsigned last_activity; +}; + +static void set_baseline_state(struct led_netdev_data *trigger_data) +{ + if ((trigger_data->mode & MODE_LINK) != 0 && trigger_data->link_up) + led_set_brightness(trigger_data->led_cdev, LED_FULL); + else + led_set_brightness(trigger_data->led_cdev, LED_OFF); + + if ((trigger_data->mode & (MODE_TX | MODE_RX)) != 0 && trigger_data->link_up) + mod_timer(&trigger_data->timer, jiffies + trigger_data->interval); + else + del_timer(&trigger_data->timer); +} + +static ssize_t led_device_name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct led_netdev_data *trigger_data = led_cdev->trigger_data; + + read_lock(&trigger_data->lock); + sprintf(buf, "%s\n", trigger_data->device_name); + read_unlock(&trigger_data->lock); + + return strlen(buf) + 1; +} + +static ssize_t led_device_name_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct led_netdev_data *trigger_data = led_cdev->trigger_data; + + if (size < 0 || size >= IFNAMSIZ) + return -EINVAL; + + write_lock(&trigger_data->lock); + + strcpy(trigger_data->device_name, buf); + if (size > 0 && trigger_data->device_name[size-1] == '\n') + trigger_data->device_name[size-1] = 0; + + if (trigger_data->device_name[0] != 0) { + /* check for existing device to update from */ + trigger_data->net_dev = dev_get_by_name(&init_net, trigger_data->device_name); + if (trigger_data->net_dev != NULL) + trigger_data->link_up = (dev_get_flags(trigger_data->net_dev) & IFF_LOWER_UP) != 0; + set_baseline_state(trigger_data); /* updates LEDs, may start timers */ + } + + write_unlock(&trigger_data->lock); + return size; +} + +static DEVICE_ATTR(device_name, 0644, led_device_name_show, led_device_name_store); + +static ssize_t led_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct led_netdev_data *trigger_data = led_cdev->trigger_data; + + read_lock(&trigger_data->lock); + + if (trigger_data->mode == 0) { + strcpy(buf, "none\n"); + } else { + if (trigger_data->mode & MODE_LINK) + strcat(buf, "link "); + if (trigger_data->mode & MODE_TX) + strcat(buf, "tx "); + if (trigger_data->mode & MODE_RX) + strcat(buf, "rx "); + strcat(buf, "\n"); + } + + read_unlock(&trigger_data->lock); + + return strlen(buf)+1; +} + +static ssize_t led_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct led_netdev_data *trigger_data = led_cdev->trigger_data; + char copybuf[128]; + int new_mode = -1; + char *p, *token; + + /* take a copy since we don't want to trash the inbound buffer when using strsep */ + strncpy(copybuf, buf, sizeof(copybuf)); + copybuf[sizeof(copybuf) - 1] = 0; + p = copybuf; + + while ((token = strsep(&p, " \t\n")) != NULL) { + if (!*token) + continue; + + if (new_mode == -1) + new_mode = 0; + + if (!strcmp(token, "none")) + new_mode = 0; + else if (!strcmp(token, "tx")) + new_mode |= MODE_TX; + else if (!strcmp(token, "rx")) + new_mode |= MODE_RX; + else if (!strcmp(token, "link")) + new_mode |= MODE_LINK; + else + return -EINVAL; + } + + if (new_mode == -1) + return -EINVAL; + + write_lock(&trigger_data->lock); + trigger_data->mode = new_mode; + set_baseline_state(trigger_data); + write_unlock(&trigger_data->lock); + + return size; +} + +static DEVICE_ATTR(mode, 0644, led_mode_show, led_mode_store); + +static ssize_t led_interval_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct led_netdev_data *trigger_data = led_cdev->trigger_data; + + read_lock(&trigger_data->lock); + sprintf(buf, "%u\n", jiffies_to_msecs(trigger_data->interval)); + read_unlock(&trigger_data->lock); + + return strlen(buf) + 1; +} + +static ssize_t led_interval_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct led_netdev_data *trigger_data = led_cdev->trigger_data; + int ret = -EINVAL; + char *after; + unsigned long value = simple_strtoul(buf, &after, 10); + size_t count = after - buf; + + if (isspace(*after)) + count++; + + /* impose some basic bounds on the timer interval */ + if (count == size && value >= 5 && value <= 10000) { + write_lock(&trigger_data->lock); + trigger_data->interval = msecs_to_jiffies(value); + set_baseline_state(trigger_data); /* resets timer */ + write_unlock(&trigger_data->lock); + ret = count; + } + + return ret; +} + +static DEVICE_ATTR(interval, 0644, led_interval_show, led_interval_store); + +static int netdev_trig_notify(struct notifier_block *nb, + unsigned long evt, + void *dv) +{ + struct net_device *dev = dv; + struct led_netdev_data *trigger_data = container_of(nb, struct led_netdev_data, notifier); + + if (evt != NETDEV_UP && evt != NETDEV_DOWN && evt != NETDEV_CHANGE && evt != NETDEV_REGISTER && evt != NETDEV_UNREGISTER) + return NOTIFY_DONE; + + write_lock(&trigger_data->lock); + + if (strcmp(dev->name, trigger_data->device_name)) + goto done; + + if (evt == NETDEV_REGISTER) { + if (trigger_data->net_dev != NULL) + dev_put(trigger_data->net_dev); + dev_hold(dev); + trigger_data->net_dev = dev; + trigger_data->link_up = 0; + goto done; + } + + if (evt == NETDEV_UNREGISTER && trigger_data->net_dev != NULL) { + dev_put(trigger_data->net_dev); + trigger_data->net_dev = NULL; + goto done; + } + + /* UP / DOWN / CHANGE */ + + trigger_data->link_up = (evt != NETDEV_DOWN && netif_carrier_ok(dev)); + set_baseline_state(trigger_data); + +done: + write_unlock(&trigger_data->lock); + return NOTIFY_DONE; +} + +/* here's the real work! */ +static void netdev_trig_timer(unsigned long arg) +{ + struct led_netdev_data *trigger_data = (struct led_netdev_data *)arg; + const struct net_device_stats *dev_stats; + unsigned new_activity; + + write_lock(&trigger_data->lock); + + if (!trigger_data->link_up || !trigger_data->net_dev || (trigger_data->mode & (MODE_TX | MODE_RX)) == 0) { + /* we don't need to do timer work, just reflect link state. */ + led_set_brightness(trigger_data->led_cdev, ((trigger_data->mode & MODE_LINK) != 0 && trigger_data->link_up) ? LED_FULL : LED_OFF); + goto no_restart; + } + + dev_stats = dev_get_stats(trigger_data->net_dev); + new_activity = + ((trigger_data->mode & MODE_TX) ? dev_stats->tx_packets : 0) + + ((trigger_data->mode & MODE_RX) ? dev_stats->rx_packets : 0); + + if (trigger_data->mode & MODE_LINK) { + /* base state is ON (link present) */ + /* if there's no link, we don't get this far and the LED is off */ + + /* OFF -> ON always */ + /* ON -> OFF on activity */ + if (trigger_data->led_cdev->brightness == LED_OFF) { + led_set_brightness(trigger_data->led_cdev, LED_FULL); + } else if (trigger_data->last_activity != new_activity) { + led_set_brightness(trigger_data->led_cdev, LED_OFF); + } + } else { + /* base state is OFF */ + /* ON -> OFF always */ + /* OFF -> ON on activity */ + if (trigger_data->led_cdev->brightness == LED_FULL) { + led_set_brightness(trigger_data->led_cdev, LED_OFF); + } else if (trigger_data->last_activity != new_activity) { + led_set_brightness(trigger_data->led_cdev, LED_FULL); + } + } + + trigger_data->last_activity = new_activity; + mod_timer(&trigger_data->timer, jiffies + trigger_data->interval); + +no_restart: + write_unlock(&trigger_data->lock); +} + +static void netdev_trig_activate(struct led_classdev *led_cdev) +{ + struct led_netdev_data *trigger_data; + int rc; + + trigger_data = kzalloc(sizeof(struct led_netdev_data), GFP_KERNEL); + if (!trigger_data) + return; + + rwlock_init(&trigger_data->lock); + + trigger_data->notifier.notifier_call = netdev_trig_notify; + trigger_data->notifier.priority = 10; + + setup_timer(&trigger_data->timer, netdev_trig_timer, (unsigned long) trigger_data); + + trigger_data->led_cdev = led_cdev; + trigger_data->net_dev = NULL; + trigger_data->device_name[0] = 0; + + trigger_data->mode = 0; + trigger_data->interval = msecs_to_jiffies(50); + trigger_data->link_up = 0; + trigger_data->last_activity = 0; + + led_cdev->trigger_data = trigger_data; + + rc = device_create_file(led_cdev->dev, &dev_attr_device_name); + if (rc) + goto err_out; + rc = device_create_file(led_cdev->dev, &dev_attr_mode); + if (rc) + goto err_out_device_name; + rc = device_create_file(led_cdev->dev, &dev_attr_interval); + if (rc) + goto err_out_mode; + + register_netdevice_notifier(&trigger_data->notifier); + return; + +err_out_mode: + device_remove_file(led_cdev->dev, &dev_attr_mode); +err_out_device_name: + device_remove_file(led_cdev->dev, &dev_attr_device_name); +err_out: + led_cdev->trigger_data = NULL; + kfree(trigger_data); +} + +static void netdev_trig_deactivate(struct led_classdev *led_cdev) +{ + struct led_netdev_data *trigger_data = led_cdev->trigger_data; + + if (trigger_data) { + unregister_netdevice_notifier(&trigger_data->notifier); + + device_remove_file(led_cdev->dev, &dev_attr_device_name); + device_remove_file(led_cdev->dev, &dev_attr_mode); + device_remove_file(led_cdev->dev, &dev_attr_interval); + + write_lock(&trigger_data->lock); + + if (trigger_data->net_dev) { + dev_put(trigger_data->net_dev); + trigger_data->net_dev = NULL; + } + + write_unlock(&trigger_data->lock); + + del_timer_sync(&trigger_data->timer); + + kfree(trigger_data); + } +} + +static struct led_trigger netdev_led_trigger = { + .name = "netdev", + .activate = netdev_trig_activate, + .deactivate = netdev_trig_deactivate, +}; + +static int __init netdev_trig_init(void) +{ + return led_trigger_register(&netdev_led_trigger); +} + +static void __exit netdev_trig_exit(void) +{ + led_trigger_unregister(&netdev_led_trigger); +} + +module_init(netdev_trig_init); +module_exit(netdev_trig_exit); + +MODULE_AUTHOR("Oliver Jowett "); +MODULE_DESCRIPTION("Netdev LED trigger"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/files/drivers/leds/ledtrig-usbdev.c b/target/linux/generic/files/drivers/leds/ledtrig-usbdev.c new file mode 100644 index 0000000..70b0e39 --- /dev/null +++ b/target/linux/generic/files/drivers/leds/ledtrig-usbdev.c @@ -0,0 +1,348 @@ +/* + * LED USB device Trigger + * + * Toggles the LED to reflect the presence and activity of an USB device + * Copyright (C) Gabor Juhos + * + * derived from ledtrig-netdev.c: + * Copyright 2007 Oliver Jowett + * + * ledtrig-netdev.c derived from ledtrig-timer.c: + * Copyright 2005-2006 Openedhand Ltd. + * Author: Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "leds.h" + +#define DEV_BUS_ID_SIZE 32 + +/* + * Configurable sysfs attributes: + * + * device_name - name of the USB device to monitor + * activity_interval - duration of LED blink, in milliseconds + */ + +struct usbdev_trig_data { + rwlock_t lock; + + struct timer_list timer; + struct notifier_block notifier; + + struct led_classdev *led_cdev; + struct usb_device *usb_dev; + + char device_name[DEV_BUS_ID_SIZE]; + unsigned interval; + int last_urbnum; +}; + +static void usbdev_trig_update_state(struct usbdev_trig_data *td) +{ + if (td->usb_dev) + led_set_brightness(td->led_cdev, LED_FULL); + else + led_set_brightness(td->led_cdev, LED_OFF); + + if (td->interval && td->usb_dev) + mod_timer(&td->timer, jiffies + td->interval); + else + del_timer(&td->timer); +} + +static ssize_t usbdev_trig_name_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct usbdev_trig_data *td = led_cdev->trigger_data; + + read_lock(&td->lock); + sprintf(buf, "%s\n", td->device_name); + read_unlock(&td->lock); + + return strlen(buf) + 1; +} + +static ssize_t usbdev_trig_name_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct usbdev_trig_data *td = led_cdev->trigger_data; + + if (size < 0 || size >= DEV_BUS_ID_SIZE) + return -EINVAL; + + write_lock(&td->lock); + + strcpy(td->device_name, buf); + if (size > 0 && td->device_name[size - 1] == '\n') + td->device_name[size - 1] = 0; + + if (td->device_name[0] != 0) { + struct usb_device *usb_dev; + + /* check for existing device to update from */ + usb_dev = usb_find_device_by_name(td->device_name); + if (usb_dev) { + if (td->usb_dev) + usb_put_dev(td->usb_dev); + + td->usb_dev = usb_dev; + td->last_urbnum = atomic_read(&usb_dev->urbnum); + } + + /* updates LEDs, may start timers */ + usbdev_trig_update_state(td); + } + + write_unlock(&td->lock); + return size; +} + +static DEVICE_ATTR(device_name, 0644, usbdev_trig_name_show, + usbdev_trig_name_store); + +static ssize_t usbdev_trig_interval_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct usbdev_trig_data *td = led_cdev->trigger_data; + + read_lock(&td->lock); + sprintf(buf, "%u\n", jiffies_to_msecs(td->interval)); + read_unlock(&td->lock); + + return strlen(buf) + 1; +} + +static ssize_t usbdev_trig_interval_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct usbdev_trig_data *td = led_cdev->trigger_data; + int ret = -EINVAL; + char *after; + unsigned long value = simple_strtoul(buf, &after, 10); + size_t count = after - buf; + + if (*after && isspace(*after)) + count++; + + if (count == size && value <= 10000) { + write_lock(&td->lock); + td->interval = msecs_to_jiffies(value); + usbdev_trig_update_state(td); /* resets timer */ + write_unlock(&td->lock); + ret = count; + } + + return ret; +} + +static DEVICE_ATTR(activity_interval, 0644, usbdev_trig_interval_show, + usbdev_trig_interval_store); + +static int usbdev_trig_notify(struct notifier_block *nb, + unsigned long evt, + void *data) +{ + struct usb_device *usb_dev; + struct usbdev_trig_data *td; + + if (evt != USB_DEVICE_ADD && evt != USB_DEVICE_REMOVE) + return NOTIFY_DONE; + + usb_dev = data; + td = container_of(nb, struct usbdev_trig_data, notifier); + + write_lock(&td->lock); + + if (strcmp(dev_name(&usb_dev->dev), td->device_name)) + goto done; + + if (evt == USB_DEVICE_ADD) { + usb_get_dev(usb_dev); + if (td->usb_dev != NULL) + usb_put_dev(td->usb_dev); + td->usb_dev = usb_dev; + td->last_urbnum = atomic_read(&usb_dev->urbnum); + } else if (evt == USB_DEVICE_REMOVE) { + if (td->usb_dev != NULL) { + usb_put_dev(td->usb_dev); + td->usb_dev = NULL; + } + } + + usbdev_trig_update_state(td); + +done: + write_unlock(&td->lock); + return NOTIFY_DONE; +} + +/* here's the real work! */ +static void usbdev_trig_timer(unsigned long arg) +{ + struct usbdev_trig_data *td = (struct usbdev_trig_data *)arg; + int new_urbnum; + + write_lock(&td->lock); + + if (!td->usb_dev || td->interval == 0) { + /* + * we don't need to do timer work, just reflect device presence + */ + if (td->usb_dev) + led_set_brightness(td->led_cdev, LED_FULL); + else + led_set_brightness(td->led_cdev, LED_OFF); + + goto no_restart; + } + + if (td->interval) + new_urbnum = atomic_read(&td->usb_dev->urbnum); + else + new_urbnum = 0; + + if (td->usb_dev) { + /* + * Base state is ON (device is present). If there's no device, + * we don't get this far and the LED is off. + * OFF -> ON always + * ON -> OFF on activity + */ + if (td->led_cdev->brightness == LED_OFF) + led_set_brightness(td->led_cdev, LED_FULL); + else if (td->last_urbnum != new_urbnum) + led_set_brightness(td->led_cdev, LED_OFF); + } else { + /* + * base state is OFF + * ON -> OFF always + * OFF -> ON on activity + */ + if (td->led_cdev->brightness == LED_FULL) + led_set_brightness(td->led_cdev, LED_OFF); + else if (td->last_urbnum != new_urbnum) + led_set_brightness(td->led_cdev, LED_FULL); + } + + td->last_urbnum = new_urbnum; + mod_timer(&td->timer, jiffies + td->interval); + +no_restart: + write_unlock(&td->lock); +} + +static void usbdev_trig_activate(struct led_classdev *led_cdev) +{ + struct usbdev_trig_data *td; + int rc; + + td = kzalloc(sizeof(struct usbdev_trig_data), GFP_KERNEL); + if (!td) + return; + + rwlock_init(&td->lock); + + td->notifier.notifier_call = usbdev_trig_notify; + td->notifier.priority = 10; + + setup_timer(&td->timer, usbdev_trig_timer, (unsigned long) td); + + td->led_cdev = led_cdev; + td->interval = msecs_to_jiffies(50); + + led_cdev->trigger_data = td; + + rc = device_create_file(led_cdev->dev, &dev_attr_device_name); + if (rc) + goto err_out; + + rc = device_create_file(led_cdev->dev, &dev_attr_activity_interval); + if (rc) + goto err_out_device_name; + + usb_register_notify(&td->notifier); + return; + +err_out_device_name: + device_remove_file(led_cdev->dev, &dev_attr_device_name); +err_out: + led_cdev->trigger_data = NULL; + kfree(td); +} + +static void usbdev_trig_deactivate(struct led_classdev *led_cdev) +{ + struct usbdev_trig_data *td = led_cdev->trigger_data; + + if (td) { + usb_unregister_notify(&td->notifier); + + device_remove_file(led_cdev->dev, &dev_attr_device_name); + device_remove_file(led_cdev->dev, &dev_attr_activity_interval); + + write_lock(&td->lock); + + if (td->usb_dev) { + usb_put_dev(td->usb_dev); + td->usb_dev = NULL; + } + + write_unlock(&td->lock); + + del_timer_sync(&td->timer); + + kfree(td); + } +} + +static struct led_trigger usbdev_led_trigger = { + .name = "usbdev", + .activate = usbdev_trig_activate, + .deactivate = usbdev_trig_deactivate, +}; + +static int __init usbdev_trig_init(void) +{ + return led_trigger_register(&usbdev_led_trigger); +} + +static void __exit usbdev_trig_exit(void) +{ + led_trigger_unregister(&usbdev_led_trigger); +} + +module_init(usbdev_trig_init); +module_exit(usbdev_trig_exit); + +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION("USB device LED trigger"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/Kconfig b/target/linux/generic/files/drivers/mtd/mtdsplit/Kconfig new file mode 100644 index 0000000..c4e3418 --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/Kconfig @@ -0,0 +1,51 @@ +config MTD_SPLIT + def_bool n + help + Generic MTD split support. + +config MTD_SPLIT_SUPPORT + def_bool MTD = y + +comment "Rootfs partition parsers" + +config MTD_SPLIT_SQUASHFS_ROOT + bool "Squashfs based root partition parser" + depends on MTD_SPLIT_SUPPORT + select MTD_SPLIT + default n + help + This provides a parsing function which allows to detect the + offset and size of the unused portion of a rootfs partition + containing a squashfs. + +comment "Firmware partition parsers" + +config MTD_SPLIT_SEAMA_FW + bool "Seama firmware parser" + depends on MTD_SPLIT_SUPPORT + select MTD_SPLIT + +config MTD_SPLIT_UIMAGE_FW + bool "uImage based firmware partition parser" + depends on MTD_SPLIT_SUPPORT + select MTD_SPLIT + +config MTD_SPLIT_FIT_FW + bool "FIT based firmware partition parser" + depends on MTD_SPLIT_SUPPORT + select MTD_SPLIT + +config MTD_SPLIT_LZMA_FW + bool "LZMA compressed kernel based firmware partition parser" + depends on MTD_SPLIT_SUPPORT + select MTD_SPLIT + +config MTD_SPLIT_TPLINK_FW + bool "TP-Link firmware parser" + depends on MTD_SPLIT_SUPPORT + select MTD_SPLIT + +config MTD_SPLIT_TRX_FW + bool "TRX image based firmware partition parser" + depends on MTD_SPLIT_SUPPORT + select MTD_SPLIT diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/Makefile b/target/linux/generic/files/drivers/mtd/mtdsplit/Makefile new file mode 100644 index 0000000..e09476b --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/Makefile @@ -0,0 +1,8 @@ +obj-$(CONFIG_MTD_SPLIT) += mtdsplit.o +obj-$(CONFIG_MTD_SPLIT_SEAMA_FW) += mtdsplit_seama.o +obj-$(CONFIG_MTD_SPLIT_SQUASHFS_ROOT) += mtdsplit_squashfs.o +obj-$(CONFIG_MTD_SPLIT_UIMAGE_FW) += mtdsplit_uimage.o +obj-$(CONFIG_MTD_SPLIT_FIT_FW) += mtdsplit_fit.o +obj-$(CONFIG_MTD_SPLIT_LZMA_FW) += mtdsplit_lzma.o +obj-$(CONFIG_MTD_SPLIT_TPLINK_FW) += mtdsplit_tplink.o +obj-$(CONFIG_MTD_SPLIT_TRX_FW) += mtdsplit_trx.o diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit.c new file mode 100644 index 0000000..162739f --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2009-2013 Felix Fietkau + * Copyright (C) 2009-2013 Gabor Juhos + * Copyright (C) 2012 Jonas Gorski + * Copyright (C) 2013 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#define pr_fmt(fmt) "mtdsplit: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include "mtdsplit.h" + +struct squashfs_super_block { + __le32 s_magic; + __le32 pad0[9]; + __le64 bytes_used; +}; + +int mtd_get_squashfs_len(struct mtd_info *master, + size_t offset, + size_t *squashfs_len) +{ + struct squashfs_super_block sb; + size_t retlen; + int err; + + err = mtd_read(master, offset, sizeof(sb), &retlen, (void *)&sb); + if (err || (retlen != sizeof(sb))) { + pr_alert("error occured while reading from \"%s\"\n", + master->name); + return -EIO; + } + + if (le32_to_cpu(sb.s_magic) != SQUASHFS_MAGIC) { + pr_alert("no squashfs found in \"%s\"\n", master->name); + return -EINVAL; + } + + retlen = le64_to_cpu(sb.bytes_used); + if (retlen <= 0) { + pr_alert("squashfs is empty in \"%s\"\n", master->name); + return -ENODEV; + } + + if (offset + retlen > master->size) { + pr_alert("squashfs has invalid size in \"%s\"\n", + master->name); + return -EINVAL; + } + + *squashfs_len = retlen; + return 0; +} +EXPORT_SYMBOL_GPL(mtd_get_squashfs_len); + +static ssize_t mtd_next_eb(struct mtd_info *mtd, size_t offset) +{ + return mtd_rounddown_to_eb(offset, mtd) + mtd->erasesize; +} + +int mtd_check_rootfs_magic(struct mtd_info *mtd, size_t offset) +{ + u32 magic; + size_t retlen; + int ret; + + ret = mtd_read(mtd, offset, sizeof(magic), &retlen, + (unsigned char *) &magic); + if (ret) + return ret; + + if (retlen != sizeof(magic)) + return -EIO; + + if (le32_to_cpu(magic) != SQUASHFS_MAGIC && + magic != 0x19852003) + return -EINVAL; + + return 0; +} +EXPORT_SYMBOL_GPL(mtd_check_rootfs_magic); + +int mtd_find_rootfs_from(struct mtd_info *mtd, + size_t from, + size_t limit, + size_t *ret_offset) +{ + size_t offset; + int err; + + for (offset = from; offset < limit; + offset = mtd_next_eb(mtd, offset)) { + err = mtd_check_rootfs_magic(mtd, offset); + if (err) + continue; + + *ret_offset = offset; + return 0; + } + + return -ENODEV; +} +EXPORT_SYMBOL_GPL(mtd_find_rootfs_from); + diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit.h b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit.h new file mode 100644 index 0000000..7ee88b0 --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2009-2013 Felix Fietkau + * Copyright (C) 2009-2013 Gabor Juhos + * Copyright (C) 2012 Jonas Gorski + * Copyright (C) 2013 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MTDSPLIT_H +#define _MTDSPLIT_H + +#define KERNEL_PART_NAME "kernel" +#define ROOTFS_PART_NAME "rootfs" + +#define ROOTFS_SPLIT_NAME "rootfs_data" + +#ifdef CONFIG_MTD_SPLIT +int mtd_get_squashfs_len(struct mtd_info *master, + size_t offset, + size_t *squashfs_len); + +int mtd_check_rootfs_magic(struct mtd_info *mtd, size_t offset); + +int mtd_find_rootfs_from(struct mtd_info *mtd, + size_t from, + size_t limit, + size_t *ret_offset); + +#else +static inline int mtd_get_squashfs_len(struct mtd_info *master, + size_t offset, + size_t *squashfs_len) +{ + return -ENODEV; +} + +static inline int mtd_check_rootfs_magic(struct mtd_info *mtd, size_t offset) +{ + return -EINVAL; +} + +static inline int mtd_find_rootfs_from(struct mtd_info *mtd, + size_t from, + size_t limit, + size_t *ret_offset) +{ + return -ENODEV; +} +#endif /* CONFIG_MTD_SPLIT */ + +#endif /* _MTDSPLIT_H */ diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_fit.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_fit.c new file mode 100644 index 0000000..d1087f6 --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_fit.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015 The Linux Foundation + * Copyright (C) 2014 Gabor Juhos + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtdsplit.h" + +struct fdt_header { + uint32_t magic; /* magic word FDT_MAGIC */ + uint32_t totalsize; /* total size of DT block */ + uint32_t off_dt_struct; /* offset to structure */ + uint32_t off_dt_strings; /* offset to strings */ + uint32_t off_mem_rsvmap; /* offset to memory reserve map */ + uint32_t version; /* format version */ + uint32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + uint32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + uint32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + uint32_t size_dt_struct; /* size of the structure block */ +}; + +static int +mtdsplit_fit_parse(struct mtd_info *mtd, struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct fdt_header hdr; + size_t hdr_len, retlen; + size_t offset; + size_t fit_offset, fit_size; + size_t rootfs_offset, rootfs_size; + struct mtd_partition *parts; + int ret; + + hdr_len = sizeof(struct fdt_header); + + /* Parse the MTD device & search for the FIT image location */ + for(offset = 0; offset < mtd->size; offset += mtd->erasesize) { + ret = mtd_read(mtd, 0, hdr_len, &retlen, (void*) &hdr); + if (ret) { + pr_err("read error in \"%s\" at offset 0x%llx\n", + mtd->name, (unsigned long long) offset); + return ret; + } + + if (retlen != hdr_len) { + pr_err("short read in \"%s\"\n", mtd->name); + return -EIO; + } + + /* Check the magic - see if this is a FIT image */ + if (be32_to_cpu(hdr.magic) != OF_DT_HEADER) { + pr_debug("no valid FIT image found in \"%s\" at offset %llx\n", + mtd->name, (unsigned long long) offset); + continue; + } + + /* We found a FIT image. Let's keep going */ + break; + } + + fit_offset = offset; + fit_size = be32_to_cpu(hdr.totalsize); + + if (fit_size == 0) { + pr_err("FIT image in \"%s\" at offset %llx has null size\n", + mtd->name, (unsigned long long) fit_offset); + return -ENODEV; + } + + /* Search for the rootfs partition after the FIT image */ + ret = mtd_find_rootfs_from(mtd, fit_offset + fit_size, + mtd->size, &rootfs_offset); + if (ret) { + pr_info("no rootfs found after FIT image in \"%s\"\n", + mtd->name); + return ret; + } + + rootfs_size = mtd->size - rootfs_offset; + + parts = kzalloc(2 * sizeof(*parts), GFP_KERNEL); + if (!parts) + return -ENOMEM; + + parts[0].name = KERNEL_PART_NAME; + parts[0].offset = fit_offset; + parts[0].size = mtd_rounddown_to_eb(fit_size, mtd) + mtd->erasesize; + + parts[1].name = ROOTFS_PART_NAME; + parts[1].offset = rootfs_offset; + parts[1].size = rootfs_size; + + *pparts = parts; + return 2; +} + +static struct mtd_part_parser uimage_parser = { + .owner = THIS_MODULE, + .name = "fit-fw", + .parse_fn = mtdsplit_fit_parse, + .type = MTD_PARSER_TYPE_FIRMWARE, +}; + +/************************************************** + * Init + **************************************************/ + +static int __init mtdsplit_fit_init(void) +{ + register_mtd_parser(&uimage_parser); + + return 0; +} + +module_init(mtdsplit_fit_init); diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_lzma.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_lzma.c new file mode 100644 index 0000000..64dc7cb --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_lzma.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2014 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "mtdsplit.h" + +#define LZMA_NR_PARTS 2 +#define LZMA_PROPERTIES_SIZE 5 + +struct lzma_header { + u8 props[LZMA_PROPERTIES_SIZE]; + u8 size_low[4]; + u8 size_high[4]; +}; + +static int mtdsplit_parse_lzma(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct lzma_header hdr; + size_t hdr_len, retlen; + size_t rootfs_offset; + u32 t; + struct mtd_partition *parts; + int err; + + hdr_len = sizeof(hdr); + err = mtd_read(master, 0, hdr_len, &retlen, (void *) &hdr); + if (err) + return err; + + if (retlen != hdr_len) + return -EIO; + + /* verify LZMA properties */ + if (hdr.props[0] >= (9 * 5 * 5)) + return -EINVAL; + + t = get_unaligned_le32(&hdr.props[1]); + if (!is_power_of_2(t)) + return -EINVAL; + + t = get_unaligned_le32(&hdr.size_high); + if (t) + return -EINVAL; + + err = mtd_find_rootfs_from(master, master->erasesize, + master->size, &rootfs_offset); + if (err) + return err; + + parts = kzalloc(LZMA_NR_PARTS * sizeof(*parts), GFP_KERNEL); + if (!parts) + return -ENOMEM; + + parts[0].name = KERNEL_PART_NAME; + parts[0].offset = 0; + parts[0].size = rootfs_offset; + + parts[1].name = ROOTFS_PART_NAME; + parts[1].offset = rootfs_offset; + parts[1].size = master->size - rootfs_offset; + + *pparts = parts; + return LZMA_NR_PARTS; +} + +static struct mtd_part_parser mtdsplit_lzma_parser = { + .owner = THIS_MODULE, + .name = "lzma-fw", + .parse_fn = mtdsplit_parse_lzma, + .type = MTD_PARSER_TYPE_FIRMWARE, +}; + +static int __init mtdsplit_lzma_init(void) +{ + register_mtd_parser(&mtdsplit_lzma_parser); + + return 0; +} + +subsys_initcall(mtdsplit_lzma_init); diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_seama.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_seama.c new file mode 100644 index 0000000..6f21f8f --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_seama.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtdsplit.h" + +#define SEAMA_MAGIC 0x5EA3A417 +#define SEAMA_NR_PARTS 2 +#define SEAMA_MIN_ROOTFS_OFFS 0x80000 /* 512KiB */ + +struct seama_header { + __be32 magic; /* should always be SEAMA_MAGIC. */ + __be16 reserved; /* reserved for */ + __be16 metasize; /* size of the META data */ + __be32 size; /* size of the image */ +}; + +static int mtdsplit_parse_seama(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct seama_header hdr; + size_t hdr_len, retlen, kernel_size; + size_t rootfs_offset; + struct mtd_partition *parts; + int err; + + hdr_len = sizeof(hdr); + err = mtd_read(master, 0, hdr_len, &retlen, (void *) &hdr); + if (err) + return err; + + if (retlen != hdr_len) + return -EIO; + + /* sanity checks */ + if (be32_to_cpu(hdr.magic) != SEAMA_MAGIC) + return -EINVAL; + + kernel_size = hdr_len + be32_to_cpu(hdr.size) + + be16_to_cpu(hdr.metasize); + if (kernel_size > master->size) + return -EINVAL; + + /* Find the rootfs after the kernel. */ + err = mtd_check_rootfs_magic(master, kernel_size); + if (!err) { + rootfs_offset = kernel_size; + } else { + /* + * The size in the header might cover the rootfs as well. + * Start the search from an arbitrary offset. + */ + err = mtd_find_rootfs_from(master, SEAMA_MIN_ROOTFS_OFFS, + master->size, &rootfs_offset); + if (err) + return err; + } + + parts = kzalloc(SEAMA_NR_PARTS * sizeof(*parts), GFP_KERNEL); + if (!parts) + return -ENOMEM; + + parts[0].name = KERNEL_PART_NAME; + parts[0].offset = 0; + parts[0].size = rootfs_offset; + + parts[1].name = ROOTFS_PART_NAME; + parts[1].offset = rootfs_offset; + parts[1].size = master->size - rootfs_offset; + + *pparts = parts; + return SEAMA_NR_PARTS; +} + +static struct mtd_part_parser mtdsplit_seama_parser = { + .owner = THIS_MODULE, + .name = "seama-fw", + .parse_fn = mtdsplit_parse_seama, + .type = MTD_PARSER_TYPE_FIRMWARE, +}; + +static int __init mtdsplit_seama_init(void) +{ + register_mtd_parser(&mtdsplit_seama_parser); + + return 0; +} + +subsys_initcall(mtdsplit_seama_init); diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_squashfs.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_squashfs.c new file mode 100644 index 0000000..3d80e07 --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_squashfs.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2013 Felix Fietkau + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtdsplit.h" + +static int +mtdsplit_parse_squashfs(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct mtd_partition *part; + struct mtd_info *parent_mtd; + size_t part_offset; + size_t squashfs_len; + int err; + + err = mtd_get_squashfs_len(master, 0, &squashfs_len); + if (err) + return err; + + parent_mtd = mtdpart_get_master(master); + part_offset = mtdpart_get_offset(master); + + part = kzalloc(sizeof(*part), GFP_KERNEL); + if (!part) { + pr_alert("unable to allocate memory for \"%s\" partition\n", + ROOTFS_SPLIT_NAME); + return -ENOMEM; + } + + part->name = ROOTFS_SPLIT_NAME; + part->offset = mtd_roundup_to_eb(part_offset + squashfs_len, + parent_mtd) - part_offset; + part->size = master->size - part->offset; + + *pparts = part; + return 1; +} + +static struct mtd_part_parser mtdsplit_squashfs_parser = { + .owner = THIS_MODULE, + .name = "squashfs-split", + .parse_fn = mtdsplit_parse_squashfs, + .type = MTD_PARSER_TYPE_ROOTFS, +}; + +static int __init mtdsplit_squashfs_init(void) +{ + register_mtd_parser(&mtdsplit_squashfs_parser); + + return 0; +} + +subsys_initcall(mtdsplit_squashfs_init); diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_tplink.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_tplink.c new file mode 100644 index 0000000..00c2d39 --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_tplink.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * Copyright (C) 2014 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mtdsplit.h" + +#define TPLINK_NR_PARTS 2 +#define TPLINK_MIN_ROOTFS_OFFS 0x80000 /* 512KiB */ + +#define MD5SUM_LEN 16 + +struct fw_v1 { + char vendor_name[24]; + char fw_version[36]; + uint32_t hw_id; /* hardware id */ + uint32_t hw_rev; /* hardware revision */ + uint32_t unk1; + uint8_t md5sum1[MD5SUM_LEN]; + uint32_t unk2; + uint8_t md5sum2[MD5SUM_LEN]; + uint32_t unk3; + uint32_t kernel_la; /* kernel load address */ + uint32_t kernel_ep; /* kernel entry point */ + uint32_t fw_length; /* total length of the firmware */ + uint32_t kernel_ofs; /* kernel data offset */ + uint32_t kernel_len; /* kernel data length */ + uint32_t rootfs_ofs; /* rootfs data offset */ + uint32_t rootfs_len; /* rootfs data length */ + uint32_t boot_ofs; /* bootloader data offset */ + uint32_t boot_len; /* bootloader data length */ + uint8_t pad[360]; +} __attribute__ ((packed)); + +struct fw_v2 { + char fw_version[48]; /* 0x04: fw version string */ + uint32_t hw_id; /* 0x34: hardware id */ + uint32_t hw_rev; /* 0x38: FIXME: hardware revision? */ + uint32_t unk1; /* 0x3c: 0x00000000 */ + uint8_t md5sum1[MD5SUM_LEN]; /* 0x40 */ + uint32_t unk2; /* 0x50: 0x00000000 */ + uint8_t md5sum2[MD5SUM_LEN]; /* 0x54 */ + uint32_t unk3; /* 0x64: 0xffffffff */ + + uint32_t kernel_la; /* 0x68: kernel load address */ + uint32_t kernel_ep; /* 0x6c: kernel entry point */ + uint32_t fw_length; /* 0x70: total length of the image */ + uint32_t kernel_ofs; /* 0x74: kernel data offset */ + uint32_t kernel_len; /* 0x78: kernel data length */ + uint32_t rootfs_ofs; /* 0x7c: rootfs data offset */ + uint32_t rootfs_len; /* 0x80: rootfs data length */ + uint32_t boot_ofs; /* 0x84: FIXME: seems to be unused */ + uint32_t boot_len; /* 0x88: FIXME: seems to be unused */ + uint16_t unk4; /* 0x8c: 0x55aa */ + uint8_t sver_hi; /* 0x8e */ + uint8_t sver_lo; /* 0x8f */ + uint8_t unk5; /* 0x90: magic: 0xa5 */ + uint8_t ver_hi; /* 0x91 */ + uint8_t ver_mid; /* 0x92 */ + uint8_t ver_lo; /* 0x93 */ + uint8_t pad[364]; +} __attribute__ ((packed)); + +struct tplink_fw_header { + uint32_t version; + union { + struct fw_v1 v1; + struct fw_v2 v2; + }; +}; + +static int mtdsplit_parse_tplink(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct tplink_fw_header hdr; + size_t hdr_len, retlen, kernel_size; + size_t rootfs_offset; + struct mtd_partition *parts; + int err; + + hdr_len = sizeof(hdr); + err = mtd_read(master, 0, hdr_len, &retlen, (void *) &hdr); + if (err) + return err; + + if (retlen != hdr_len) + return -EIO; + + switch (le32_to_cpu(hdr.version)) { + case 1: + if (be32_to_cpu(hdr.v1.kernel_ofs) != sizeof(hdr)) + return -EINVAL; + + kernel_size = sizeof(hdr) + be32_to_cpu(hdr.v1.kernel_len); + break; + case 2: + case 3: + if (be32_to_cpu(hdr.v2.kernel_ofs) != sizeof(hdr)) + return -EINVAL; + + kernel_size = sizeof(hdr) + be32_to_cpu(hdr.v2.kernel_len); + break; + default: + return -EINVAL; + } + + if (kernel_size > master->size) + return -EINVAL; + + /* Find the rootfs after the kernel. */ + err = mtd_check_rootfs_magic(master, kernel_size); + if (!err) { + rootfs_offset = kernel_size; + } else { + /* + * The size in the header might cover the rootfs as well. + * Start the search from an arbitrary offset. + */ + err = mtd_find_rootfs_from(master, TPLINK_MIN_ROOTFS_OFFS, + master->size, &rootfs_offset); + if (err) + return err; + } + + parts = kzalloc(TPLINK_NR_PARTS * sizeof(*parts), GFP_KERNEL); + if (!parts) + return -ENOMEM; + + parts[0].name = KERNEL_PART_NAME; + parts[0].offset = 0; + parts[0].size = rootfs_offset; + + parts[1].name = ROOTFS_PART_NAME; + parts[1].offset = rootfs_offset; + parts[1].size = master->size - rootfs_offset; + + *pparts = parts; + return TPLINK_NR_PARTS; +} + +static struct mtd_part_parser mtdsplit_tplink_parser = { + .owner = THIS_MODULE, + .name = "tplink-fw", + .parse_fn = mtdsplit_parse_tplink, + .type = MTD_PARSER_TYPE_FIRMWARE, +}; + +static int __init mtdsplit_tplink_init(void) +{ + register_mtd_parser(&mtdsplit_tplink_parser); + + return 0; +} + +subsys_initcall(mtdsplit_tplink_init); diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_trx.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_trx.c new file mode 100644 index 0000000..6efffce --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_trx.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * Copyright (C) 2014 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include "mtdsplit.h" + +#define TRX_MAGIC 0x30524448 /* "HDR0" */ + +struct trx_header { + __le32 magic; + __le32 len; + __le32 crc32; + __le32 flag_version; + __le32 offset[4]; +}; + +static int +read_trx_header(struct mtd_info *mtd, size_t offset, + struct trx_header *header) +{ + size_t header_len; + size_t retlen; + int ret; + + header_len = sizeof(*header); + ret = mtd_read(mtd, offset, header_len, &retlen, + (unsigned char *) header); + if (ret) { + pr_debug("read error in \"%s\"\n", mtd->name); + return ret; + } + + if (retlen != header_len) { + pr_debug("short read in \"%s\"\n", mtd->name); + return -EIO; + } + + return 0; +} + +static int +mtdsplit_parse_trx(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct mtd_partition *parts; + struct trx_header hdr; + int nr_parts; + size_t offset; + size_t trx_offset; + size_t trx_size = 0; + size_t rootfs_offset; + size_t rootfs_size = 0; + int ret; + + nr_parts = 2; + parts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL); + if (!parts) + return -ENOMEM; + + /* find trx image on erase block boundaries */ + for (offset = 0; offset < master->size; offset += master->erasesize) { + trx_size = 0; + + ret = read_trx_header(master, offset, &hdr); + if (ret) + continue; + + if (hdr.magic != cpu_to_le32(TRX_MAGIC)) { + pr_debug("no valid trx header found in \"%s\" at offset %llx\n", + master->name, (unsigned long long) offset); + continue; + } + + trx_size = le32_to_cpu(hdr.len); + if ((offset + trx_size) > master->size) { + pr_debug("trx image exceeds MTD device \"%s\"\n", + master->name); + continue; + } + break; + } + + if (trx_size == 0) { + pr_debug("no trx header found in \"%s\"\n", master->name); + ret = -ENODEV; + goto err; + } + + trx_offset = offset + hdr.offset[0]; + rootfs_offset = offset + hdr.offset[1]; + rootfs_size = master->size - rootfs_offset; + trx_size = rootfs_offset - trx_offset; + + if (rootfs_size == 0) { + pr_debug("no rootfs found in \"%s\"\n", master->name); + ret = -ENODEV; + goto err; + } + + parts[0].name = KERNEL_PART_NAME; + parts[0].offset = trx_offset; + parts[0].size = trx_size; + + parts[1].name = ROOTFS_PART_NAME; + parts[1].offset = rootfs_offset; + parts[1].size = rootfs_size; + + *pparts = parts; + return nr_parts; + +err: + kfree(parts); + return ret; +} + +static struct mtd_part_parser trx_parser = { + .owner = THIS_MODULE, + .name = "trx-fw", + .parse_fn = mtdsplit_parse_trx, + .type = MTD_PARSER_TYPE_FIRMWARE, +}; + +static int __init mtdsplit_trx_init(void) +{ + register_mtd_parser(&trx_parser); + + return 0; +} + +module_init(mtdsplit_trx_init); diff --git a/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c new file mode 100644 index 0000000..2602f98 --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtdsplit.h" + +/* + * uimage_header itself is only 64B, but it may be prepended with another data. + * Currently the biggest size is for Edimax devices: 20B + 64B + */ +#define MAX_HEADER_LEN 84 + +#define IH_MAGIC 0x27051956 /* Image Magic Number */ +#define IH_NMLEN 32 /* Image Name Length */ + +#define IH_OS_LINUX 5 /* Linux */ + +#define IH_TYPE_KERNEL 2 /* OS Kernel Image */ +#define IH_TYPE_FILESYSTEM 7 /* Filesystem Image */ + +/* + * Legacy format image header, + * all data in network byte order (aka natural aka bigendian). + */ +struct uimage_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +}; + +static int +read_uimage_header(struct mtd_info *mtd, size_t offset, u_char *buf, + size_t header_len) +{ + size_t retlen; + int ret; + + ret = mtd_read(mtd, offset, header_len, &retlen, buf); + if (ret) { + pr_debug("read error in \"%s\"\n", mtd->name); + return ret; + } + + if (retlen != header_len) { + pr_debug("short read in \"%s\"\n", mtd->name); + return -EIO; + } + + return 0; +} + +/** + * __mtdsplit_parse_uimage - scan partition and create kernel + rootfs parts + * + * @find_header: function to call for a block of data that will return offset + * of a valid uImage header if found + */ +static int __mtdsplit_parse_uimage(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data, + ssize_t (*find_header)(u_char *buf, size_t len)) +{ + struct mtd_partition *parts; + u_char *buf; + int nr_parts; + size_t offset; + size_t uimage_offset; + size_t uimage_size = 0; + size_t rootfs_offset; + size_t rootfs_size = 0; + int uimage_part, rf_part; + int ret; + + nr_parts = 2; + parts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL); + if (!parts) + return -ENOMEM; + + buf = vmalloc(MAX_HEADER_LEN); + if (!buf) { + ret = -ENOMEM; + goto err_free_parts; + } + + /* find uImage on erase block boundaries */ + for (offset = 0; offset < master->size; offset += master->erasesize) { + struct uimage_header *header; + + uimage_size = 0; + + ret = read_uimage_header(master, offset, buf, MAX_HEADER_LEN); + if (ret) + continue; + + ret = find_header(buf, MAX_HEADER_LEN); + if (ret < 0) { + pr_debug("no valid uImage found in \"%s\" at offset %llx\n", + master->name, (unsigned long long) offset); + continue; + } + header = (struct uimage_header *)(buf + ret); + + uimage_size = sizeof(*header) + be32_to_cpu(header->ih_size); + if ((offset + uimage_size) > master->size) { + pr_debug("uImage exceeds MTD device \"%s\"\n", + master->name); + continue; + } + break; + } + + if (uimage_size == 0) { + pr_debug("no uImage found in \"%s\"\n", master->name); + ret = -ENODEV; + goto err_free_buf; + } + + uimage_offset = offset; + + if (uimage_offset == 0) { + uimage_part = 0; + rf_part = 1; + + /* find the roots after the uImage */ + ret = mtd_find_rootfs_from(master, + uimage_offset + uimage_size, + master->size, + &rootfs_offset); + if (ret) { + pr_debug("no rootfs after uImage in \"%s\"\n", + master->name); + goto err_free_buf; + } + + rootfs_size = master->size - rootfs_offset; + uimage_size = rootfs_offset - uimage_offset; + } else { + rf_part = 0; + uimage_part = 1; + + /* check rootfs presence at offset 0 */ + ret = mtd_check_rootfs_magic(master, 0); + if (ret) { + pr_debug("no rootfs before uImage in \"%s\"\n", + master->name); + goto err_free_buf; + } + + rootfs_offset = 0; + rootfs_size = uimage_offset; + } + + if (rootfs_size == 0) { + pr_debug("no rootfs found in \"%s\"\n", master->name); + ret = -ENODEV; + goto err_free_buf; + } + + parts[uimage_part].name = KERNEL_PART_NAME; + parts[uimage_part].offset = uimage_offset; + parts[uimage_part].size = uimage_size; + + parts[rf_part].name = ROOTFS_PART_NAME; + parts[rf_part].offset = rootfs_offset; + parts[rf_part].size = rootfs_size; + + vfree(buf); + + *pparts = parts; + return nr_parts; + +err_free_buf: + vfree(buf); + +err_free_parts: + kfree(parts); + return ret; +} + +static ssize_t uimage_verify_default(u_char *buf, size_t len) +{ + struct uimage_header *header = (struct uimage_header *)buf; + + /* default sanity checks */ + if (be32_to_cpu(header->ih_magic) != IH_MAGIC) { + pr_debug("invalid uImage magic: %08x\n", + be32_to_cpu(header->ih_magic)); + return -EINVAL; + } + + if (header->ih_os != IH_OS_LINUX) { + pr_debug("invalid uImage OS: %08x\n", + be32_to_cpu(header->ih_os)); + return -EINVAL; + } + + if (header->ih_type != IH_TYPE_KERNEL) { + pr_debug("invalid uImage type: %08x\n", + be32_to_cpu(header->ih_type)); + return -EINVAL; + } + + return 0; +} + +static int +mtdsplit_uimage_parse_generic(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + return __mtdsplit_parse_uimage(master, pparts, data, + uimage_verify_default); +} + +static struct mtd_part_parser uimage_generic_parser = { + .owner = THIS_MODULE, + .name = "uimage-fw", + .parse_fn = mtdsplit_uimage_parse_generic, + .type = MTD_PARSER_TYPE_FIRMWARE, +}; + +#define FW_MAGIC_WNR2000V3 0x32303033 +#define FW_MAGIC_WNR2000V4 0x32303034 +#define FW_MAGIC_WNR2200 0x32323030 +#define FW_MAGIC_WNR612V2 0x32303631 +#define FW_MAGIC_WNR1000V2 0x31303031 +#define FW_MAGIC_WNR1000V2_VC 0x31303030 +#define FW_MAGIC_WNDR3700 0x33373030 +#define FW_MAGIC_WNDR3700V2 0x33373031 + +static ssize_t uimage_verify_wndr3700(u_char *buf, size_t len) +{ + struct uimage_header *header = (struct uimage_header *)buf; + uint8_t expected_type = IH_TYPE_FILESYSTEM; + + switch be32_to_cpu(header->ih_magic) { + case FW_MAGIC_WNR612V2: + case FW_MAGIC_WNR1000V2: + case FW_MAGIC_WNR1000V2_VC: + case FW_MAGIC_WNR2000V3: + case FW_MAGIC_WNR2200: + case FW_MAGIC_WNDR3700: + case FW_MAGIC_WNDR3700V2: + break; + case FW_MAGIC_WNR2000V4: + expected_type = IH_TYPE_KERNEL; + break; + default: + return -EINVAL; + } + + if (header->ih_os != IH_OS_LINUX || + header->ih_type != expected_type) + return -EINVAL; + + return 0; +} + +static int +mtdsplit_uimage_parse_netgear(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + return __mtdsplit_parse_uimage(master, pparts, data, + uimage_verify_wndr3700); +} + +static struct mtd_part_parser uimage_netgear_parser = { + .owner = THIS_MODULE, + .name = "netgear-fw", + .parse_fn = mtdsplit_uimage_parse_netgear, + .type = MTD_PARSER_TYPE_FIRMWARE, +}; + +/************************************************** + * Edimax + **************************************************/ + +#define FW_EDIMAX_OFFSET 20 +#define FW_MAGIC_EDIMAX 0x43535953 + +static ssize_t uimage_find_edimax(u_char *buf, size_t len) +{ + struct uimage_header *header; + + if (len < FW_EDIMAX_OFFSET + sizeof(*header)) { + pr_err("Buffer too small for checking Edimax header\n"); + return -ENOSPC; + } + + header = (struct uimage_header *)(buf + FW_EDIMAX_OFFSET); + + switch be32_to_cpu(header->ih_magic) { + case FW_MAGIC_EDIMAX: + break; + default: + return -EINVAL; + } + + if (header->ih_os != IH_OS_LINUX || + header->ih_type != IH_TYPE_FILESYSTEM) + return -EINVAL; + + return FW_EDIMAX_OFFSET; +} + +static int +mtdsplit_uimage_parse_edimax(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + return __mtdsplit_parse_uimage(master, pparts, data, + uimage_find_edimax); +} + +static struct mtd_part_parser uimage_edimax_parser = { + .owner = THIS_MODULE, + .name = "edimax-fw", + .parse_fn = mtdsplit_uimage_parse_edimax, + .type = MTD_PARSER_TYPE_FIRMWARE, +}; + +/************************************************** + * Init + **************************************************/ + +static int __init mtdsplit_uimage_init(void) +{ + register_mtd_parser(&uimage_generic_parser); + register_mtd_parser(&uimage_netgear_parser); + register_mtd_parser(&uimage_edimax_parser); + + return 0; +} + +module_init(mtdsplit_uimage_init); diff --git a/target/linux/generic/files/drivers/mtd/myloader.c b/target/linux/generic/files/drivers/mtd/myloader.c new file mode 100644 index 0000000..cd57369 --- /dev/null +++ b/target/linux/generic/files/drivers/mtd/myloader.c @@ -0,0 +1,182 @@ +/* + * Parse MyLoader-style flash partition tables and produce a Linux partition + * array to match. + * + * Copyright (C) 2007-2009 Gabor Juhos + * + * This file was based on drivers/mtd/redboot.c + * Author: Red Hat, Inc. - David Woodhouse + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BLOCK_LEN_MIN 0x10000 +#define PART_NAME_LEN 32 + +struct part_data { + struct mylo_partition_table tab; + char names[MYLO_MAX_PARTITIONS][PART_NAME_LEN]; +}; + +static int myloader_parse_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +{ + struct part_data *buf; + struct mylo_partition_table *tab; + struct mylo_partition *part; + struct mtd_partition *mtd_parts; + struct mtd_partition *mtd_part; + int num_parts; + int ret, i; + size_t retlen; + char *names; + unsigned long offset; + unsigned long blocklen; + + buf = vmalloc(sizeof(*buf)); + if (!buf) { + return -ENOMEM; + goto out; + } + tab = &buf->tab; + + blocklen = master->erasesize; + if (blocklen < BLOCK_LEN_MIN) + blocklen = BLOCK_LEN_MIN; + + offset = blocklen; + + /* Find the partition table */ + for (i = 0; i < 4; i++, offset += blocklen) { + printk(KERN_DEBUG "%s: searching for MyLoader partition table" + " at offset 0x%lx\n", master->name, offset); + + ret = mtd_read(master, offset, sizeof(*buf), &retlen, + (void *)buf); + if (ret) + goto out_free_buf; + + if (retlen != sizeof(*buf)) { + ret = -EIO; + goto out_free_buf; + } + + /* Check for Partition Table magic number */ + if (tab->magic == le32_to_cpu(MYLO_MAGIC_PARTITIONS)) + break; + + } + + if (tab->magic != le32_to_cpu(MYLO_MAGIC_PARTITIONS)) { + printk(KERN_DEBUG "%s: no MyLoader partition table found\n", + master->name); + ret = 0; + goto out_free_buf; + } + + /* The MyLoader and the Partition Table is always present */ + num_parts = 2; + + /* Detect number of used partitions */ + for (i = 0; i < MYLO_MAX_PARTITIONS; i++) { + part = &tab->partitions[i]; + + if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE) + continue; + + num_parts++; + } + + mtd_parts = kzalloc((num_parts * sizeof(*mtd_part) + + num_parts * PART_NAME_LEN), GFP_KERNEL); + + if (!mtd_parts) { + ret = -ENOMEM; + goto out_free_buf; + } + + mtd_part = mtd_parts; + names = (char *)&mtd_parts[num_parts]; + + strncpy(names, "myloader", PART_NAME_LEN); + mtd_part->name = names; + mtd_part->offset = 0; + mtd_part->size = offset; + mtd_part->mask_flags = MTD_WRITEABLE; + mtd_part++; + names += PART_NAME_LEN; + + strncpy(names, "partition_table", PART_NAME_LEN); + mtd_part->name = names; + mtd_part->offset = offset; + mtd_part->size = blocklen; + mtd_part->mask_flags = MTD_WRITEABLE; + mtd_part++; + names += PART_NAME_LEN; + + for (i = 0; i < MYLO_MAX_PARTITIONS; i++) { + part = &tab->partitions[i]; + + if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE) + continue; + + if ((buf->names[i][0]) && (buf->names[i][0] != '\xff')) + strncpy(names, buf->names[i], PART_NAME_LEN); + else + snprintf(names, PART_NAME_LEN, "partition%d", i); + + mtd_part->offset = le32_to_cpu(part->addr); + mtd_part->size = le32_to_cpu(part->size); + mtd_part->name = names; + mtd_part++; + names += PART_NAME_LEN; + } + + *pparts = mtd_parts; + ret = num_parts; + + out_free_buf: + vfree(buf); + out: + return ret; +} + +static struct mtd_part_parser myloader_mtd_parser = { + .owner = THIS_MODULE, + .parse_fn = myloader_parse_partitions, + .name = "MyLoader", +}; + +static int __init myloader_mtd_parser_init(void) +{ + register_mtd_parser(&myloader_mtd_parser); + + return 0; +} + +static void __exit myloader_mtd_parser_exit(void) +{ + deregister_mtd_parser(&myloader_mtd_parser); +} + +module_init(myloader_mtd_parser_init); +module_exit(myloader_mtd_parser_exit); + +MODULE_AUTHOR("Gabor Juhos "); +MODULE_DESCRIPTION("Parsing code for MyLoader partition tables"); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/generic/files/drivers/net/phy/adm6996.c b/target/linux/generic/files/drivers/net/phy/adm6996.c new file mode 100644 index 0000000..cada4aa --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/adm6996.c @@ -0,0 +1,1210 @@ +/* + * ADM6996 switch driver + * + * swconfig interface based on ar8216.c + * + * Copyright (c) 2008 Felix Fietkau + * VLAN support Copyright (c) 2010, 2011 Peter Lebbing + * Copyright (c) 2013 Hauke Mehrtens + * Copyright (c) 2014 Matti Laakso + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License v2 as published by the + * Free Software Foundation + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +/*#define DEBUG 1*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "adm6996.h" + +MODULE_DESCRIPTION("Infineon ADM6996 Switch"); +MODULE_AUTHOR("Felix Fietkau, Peter Lebbing "); +MODULE_LICENSE("GPL"); + +static const char * const adm6996_model_name[] = +{ + NULL, + "ADM6996FC", + "ADM6996M", + "ADM6996L" +}; + +struct adm6996_mib_desc { + unsigned int offset; + const char *name; +}; + +struct adm6996_priv { + struct switch_dev dev; + void *priv; + + u8 eecs; + u8 eesk; + u8 eedi; + u8 eerc; + + enum adm6996_model model; + + bool enable_vlan; + bool vlan_enabled; /* Current hardware state */ + +#ifdef DEBUG + u16 addr; /* Debugging: register address to operate on */ +#endif + + u16 pvid[ADM_NUM_PORTS]; /* Primary VLAN ID */ + u8 tagged_ports; + + u16 vlan_id[ADM_NUM_VLANS]; + u8 vlan_table[ADM_NUM_VLANS]; /* bitmap, 1 = port is member */ + u8 vlan_tagged[ADM_NUM_VLANS]; /* bitmap, 1 = tagged member */ + + struct mutex mib_lock; + char buf[2048]; + + struct mutex reg_mutex; + + /* use abstraction for regops, we want to add gpio support in the future */ + u16 (*read)(struct adm6996_priv *priv, enum admreg reg); + void (*write)(struct adm6996_priv *priv, enum admreg reg, u16 val); +}; + +#define to_adm(_dev) container_of(_dev, struct adm6996_priv, dev) +#define phy_to_adm(_phy) ((struct adm6996_priv *) (_phy)->priv) + +#define MIB_DESC(_o, _n) \ + { \ + .offset = (_o), \ + .name = (_n), \ + } + +static const struct adm6996_mib_desc adm6996_mibs[] = { + MIB_DESC(ADM_CL0, "RxPacket"), + MIB_DESC(ADM_CL6, "RxByte"), + MIB_DESC(ADM_CL12, "TxPacket"), + MIB_DESC(ADM_CL18, "TxByte"), + MIB_DESC(ADM_CL24, "Collision"), + MIB_DESC(ADM_CL30, "Error"), +}; + +static inline u16 +r16(struct adm6996_priv *priv, enum admreg reg) +{ + return priv->read(priv, reg); +} + +static inline void +w16(struct adm6996_priv *priv, enum admreg reg, u16 val) +{ + priv->write(priv, reg, val); +} + +/* Minimum timing constants */ +#define EECK_EDGE_TIME 3 /* 3us - max(adm 2.5us, 93c 1us) */ +#define EEDI_SETUP_TIME 1 /* 1us - max(adm 10ns, 93c 400ns) */ +#define EECS_SETUP_TIME 1 /* 1us - max(adm no, 93c 200ns) */ + +static void adm6996_gpio_write(struct adm6996_priv *priv, int cs, char *buf, unsigned int bits) +{ + int i, len = (bits + 7) / 8; + u8 mask; + + gpio_set_value(priv->eecs, cs); + udelay(EECK_EDGE_TIME); + + /* Byte assemble from MSB to LSB */ + for (i = 0; i < len; i++) { + /* Bit bang from MSB to LSB */ + for (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) { + /* Clock low */ + gpio_set_value(priv->eesk, 0); + udelay(EECK_EDGE_TIME); + + /* Output on rising edge */ + gpio_set_value(priv->eedi, (mask & buf[i])); + udelay(EEDI_SETUP_TIME); + + /* Clock high */ + gpio_set_value(priv->eesk, 1); + udelay(EECK_EDGE_TIME); + } + } + + /* Clock low */ + gpio_set_value(priv->eesk, 0); + udelay(EECK_EDGE_TIME); + + if (cs) + gpio_set_value(priv->eecs, 0); +} + +static void adm6996_gpio_read(struct adm6996_priv *priv, int cs, char *buf, unsigned int bits) +{ + int i, len = (bits + 7) / 8; + u8 mask; + + gpio_set_value(priv->eecs, cs); + udelay(EECK_EDGE_TIME); + + /* Byte assemble from MSB to LSB */ + for (i = 0; i < len; i++) { + u8 byte; + + /* Bit bang from MSB to LSB */ + for (mask = 0x80, byte = 0; mask && bits > 0; mask >>= 1, bits --) { + u8 gp; + + /* Clock low */ + gpio_set_value(priv->eesk, 0); + udelay(EECK_EDGE_TIME); + + /* Input on rising edge */ + gp = gpio_get_value(priv->eedi); + if (gp) + byte |= mask; + + /* Clock high */ + gpio_set_value(priv->eesk, 1); + udelay(EECK_EDGE_TIME); + } + + *buf++ = byte; + } + + /* Clock low */ + gpio_set_value(priv->eesk, 0); + udelay(EECK_EDGE_TIME); + + if (cs) + gpio_set_value(priv->eecs, 0); +} + +/* Advance clock(s) */ +static void adm6996_gpio_adclk(struct adm6996_priv *priv, int clocks) +{ + int i; + for (i = 0; i < clocks; i++) { + /* Clock high */ + gpio_set_value(priv->eesk, 1); + udelay(EECK_EDGE_TIME); + + /* Clock low */ + gpio_set_value(priv->eesk, 0); + udelay(EECK_EDGE_TIME); + } +} + +static u16 +adm6996_read_gpio_reg(struct adm6996_priv *priv, enum admreg reg) +{ + /* cmd: 01 10 T DD R RRRRRR */ + u8 bits[6] = { + 0xFF, 0xFF, 0xFF, 0xFF, + (0x06 << 4) | ((0 & 0x01) << 3 | (reg&64)>>6), + ((reg&63)<<2) + }; + + u8 rbits[4]; + + /* Enable GPIO outputs with all pins to 0 */ + gpio_direction_output(priv->eecs, 0); + gpio_direction_output(priv->eesk, 0); + gpio_direction_output(priv->eedi, 0); + + adm6996_gpio_write(priv, 0, bits, 46); + gpio_direction_input(priv->eedi); + adm6996_gpio_adclk(priv, 2); + adm6996_gpio_read(priv, 0, rbits, 32); + + /* Extra clock(s) required per datasheet */ + adm6996_gpio_adclk(priv, 2); + + /* Disable GPIO outputs */ + gpio_direction_input(priv->eecs); + gpio_direction_input(priv->eesk); + + /* EEPROM has 16-bit registers, but pumps out two registers in one request */ + return (reg & 0x01 ? (rbits[0]<<8) | rbits[1] : (rbits[2]<<8) | (rbits[3])); +} + +/* Write chip configuration register */ +/* Follow 93c66 timing and chip's min EEPROM timing requirement */ +static void +adm6996_write_gpio_reg(struct adm6996_priv *priv, enum admreg reg, u16 val) +{ + /* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */ + u8 bits[4] = { + (0x05 << 5) | (reg >> 3), + (reg << 5) | (u8)(val >> 11), + (u8)(val >> 3), + (u8)(val << 5) + }; + + /* Enable GPIO outputs with all pins to 0 */ + gpio_direction_output(priv->eecs, 0); + gpio_direction_output(priv->eesk, 0); + gpio_direction_output(priv->eedi, 0); + + /* Write cmd. Total 27 bits */ + adm6996_gpio_write(priv, 1, bits, 27); + + /* Extra clock(s) required per datasheet */ + adm6996_gpio_adclk(priv, 2); + + /* Disable GPIO outputs */ + gpio_direction_input(priv->eecs); + gpio_direction_input(priv->eesk); + gpio_direction_input(priv->eedi); +} + +static u16 +adm6996_read_mii_reg(struct adm6996_priv *priv, enum admreg reg) +{ + struct phy_device *phydev = priv->priv; + struct mii_bus *bus = phydev->bus; + + return bus->read(bus, PHYADDR(reg)); +} + +static void +adm6996_write_mii_reg(struct adm6996_priv *priv, enum admreg reg, u16 val) +{ + struct phy_device *phydev = priv->priv; + struct mii_bus *bus = phydev->bus; + + bus->write(bus, PHYADDR(reg), val); +} + +static int +adm6996_set_enable_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + + if (val->value.i > 1) + return -EINVAL; + + priv->enable_vlan = val->value.i; + + return 0; +}; + +static int +adm6996_get_enable_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + + val->value.i = priv->enable_vlan; + + return 0; +}; + +#ifdef DEBUG + +static int +adm6996_set_addr(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + + if (val->value.i > 1023) + return -EINVAL; + + priv->addr = val->value.i; + + return 0; +}; + +static int +adm6996_get_addr(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + + val->value.i = priv->addr; + + return 0; +}; + +static int +adm6996_set_data(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + + if (val->value.i > 65535) + return -EINVAL; + + w16(priv, priv->addr, val->value.i); + + return 0; +}; + +static int +adm6996_get_data(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + + val->value.i = r16(priv, priv->addr); + + return 0; +}; + +#endif /* def DEBUG */ + +static int +adm6996_set_pvid(struct switch_dev *dev, int port, int vlan) +{ + struct adm6996_priv *priv = to_adm(dev); + + pr_devel("set_pvid port %d vlan %d\n", port, vlan); + + if (vlan > ADM_VLAN_MAX_ID) + return -EINVAL; + + priv->pvid[port] = vlan; + + return 0; +} + +static int +adm6996_get_pvid(struct switch_dev *dev, int port, int *vlan) +{ + struct adm6996_priv *priv = to_adm(dev); + + pr_devel("get_pvid port %d\n", port); + *vlan = priv->pvid[port]; + + return 0; +} + +static int +adm6996_set_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + + pr_devel("set_vid port %d vid %d\n", val->port_vlan, val->value.i); + + if (val->value.i > ADM_VLAN_MAX_ID) + return -EINVAL; + + priv->vlan_id[val->port_vlan] = val->value.i; + + return 0; +}; + +static int +adm6996_get_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + + pr_devel("get_vid port %d\n", val->port_vlan); + + val->value.i = priv->vlan_id[val->port_vlan]; + + return 0; +}; + +static int +adm6996_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + u8 ports = priv->vlan_table[val->port_vlan]; + u8 tagged = priv->vlan_tagged[val->port_vlan]; + int i; + + pr_devel("get_ports port_vlan %d\n", val->port_vlan); + + val->len = 0; + + for (i = 0; i < ADM_NUM_PORTS; i++) { + struct switch_port *p; + + if (!(ports & (1 << i))) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if (tagged & (1 << i)) + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); + else + p->flags = 0; + } + + return 0; +}; + +static int +adm6996_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + u8 *ports = &priv->vlan_table[val->port_vlan]; + u8 *tagged = &priv->vlan_tagged[val->port_vlan]; + int i; + + pr_devel("set_ports port_vlan %d ports", val->port_vlan); + + *ports = 0; + *tagged = 0; + + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + +#ifdef DEBUG + pr_cont(" %d%s", p->id, + ((p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) ? "T" : + "")); +#endif + + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) { + *tagged |= (1 << p->id); + priv->tagged_ports |= (1 << p->id); + } + + *ports |= (1 << p->id); + } + +#ifdef DEBUG + pr_cont("\n"); +#endif + + return 0; +}; + +/* + * Precondition: reg_mutex must be held + */ +static void +adm6996_enable_vlan(struct adm6996_priv *priv) +{ + u16 reg; + + reg = r16(priv, ADM_OTBE_P2_PVID); + reg &= ~(ADM_OTBE_MASK); + w16(priv, ADM_OTBE_P2_PVID, reg); + reg = r16(priv, ADM_IFNTE); + reg &= ~(ADM_IFNTE_MASK); + w16(priv, ADM_IFNTE, reg); + reg = r16(priv, ADM_VID_CHECK); + reg |= ADM_VID_CHECK_MASK; + w16(priv, ADM_VID_CHECK, reg); + reg = r16(priv, ADM_SYSC0); + reg |= ADM_NTTE; + reg &= ~(ADM_RVID1); + w16(priv, ADM_SYSC0, reg); + reg = r16(priv, ADM_SYSC3); + reg |= ADM_TBV; + w16(priv, ADM_SYSC3, reg); +} + +static void +adm6996_enable_vlan_6996l(struct adm6996_priv *priv) +{ + u16 reg; + + reg = r16(priv, ADM_SYSC3); + reg |= ADM_TBV; + reg |= ADM_MAC_CLONE; + w16(priv, ADM_SYSC3, reg); +} + +/* + * Disable VLANs + * + * Sets VLAN mapping for port-based VLAN with all ports connected to + * eachother (this is also the power-on default). + * + * Precondition: reg_mutex must be held + */ +static void +adm6996_disable_vlan(struct adm6996_priv *priv) +{ + u16 reg; + int i; + + for (i = 0; i < ADM_NUM_VLANS; i++) { + reg = ADM_VLAN_FILT_MEMBER_MASK; + w16(priv, ADM_VLAN_FILT_L(i), reg); + reg = ADM_VLAN_FILT_VALID | ADM_VLAN_FILT_VID(1); + w16(priv, ADM_VLAN_FILT_H(i), reg); + } + + reg = r16(priv, ADM_OTBE_P2_PVID); + reg |= ADM_OTBE_MASK; + w16(priv, ADM_OTBE_P2_PVID, reg); + reg = r16(priv, ADM_IFNTE); + reg |= ADM_IFNTE_MASK; + w16(priv, ADM_IFNTE, reg); + reg = r16(priv, ADM_VID_CHECK); + reg &= ~(ADM_VID_CHECK_MASK); + w16(priv, ADM_VID_CHECK, reg); + reg = r16(priv, ADM_SYSC0); + reg &= ~(ADM_NTTE); + reg |= ADM_RVID1; + w16(priv, ADM_SYSC0, reg); + reg = r16(priv, ADM_SYSC3); + reg &= ~(ADM_TBV); + w16(priv, ADM_SYSC3, reg); +} + +/* + * Disable VLANs + * + * Sets VLAN mapping for port-based VLAN with all ports connected to + * eachother (this is also the power-on default). + * + * Precondition: reg_mutex must be held + */ +static void +adm6996_disable_vlan_6996l(struct adm6996_priv *priv) +{ + u16 reg; + int i; + + for (i = 0; i < ADM_NUM_VLANS; i++) { + w16(priv, ADM_VLAN_MAP(i), 0); + } + + reg = r16(priv, ADM_SYSC3); + reg &= ~(ADM_TBV); + reg &= ~(ADM_MAC_CLONE); + w16(priv, ADM_SYSC3, reg); +} + +/* + * Precondition: reg_mutex must be held + */ +static void +adm6996_apply_port_pvids(struct adm6996_priv *priv) +{ + u16 reg; + int i; + + for (i = 0; i < ADM_NUM_PORTS; i++) { + reg = r16(priv, adm_portcfg[i]); + reg &= ~(ADM_PORTCFG_PVID_MASK); + reg |= ADM_PORTCFG_PVID(priv->pvid[i]); + if (priv->model == ADM6996L) { + if (priv->tagged_ports & (1 << i)) + reg |= (1 << 4); + else + reg &= ~(1 << 4); + } + w16(priv, adm_portcfg[i], reg); + } + + w16(priv, ADM_P0_PVID, ADM_P0_PVID_VAL(priv->pvid[0])); + w16(priv, ADM_P1_PVID, ADM_P1_PVID_VAL(priv->pvid[1])); + reg = r16(priv, ADM_OTBE_P2_PVID); + reg &= ~(ADM_P2_PVID_MASK); + reg |= ADM_P2_PVID_VAL(priv->pvid[2]); + w16(priv, ADM_OTBE_P2_PVID, reg); + reg = ADM_P3_PVID_VAL(priv->pvid[3]); + reg |= ADM_P4_PVID_VAL(priv->pvid[4]); + w16(priv, ADM_P3_P4_PVID, reg); + reg = r16(priv, ADM_P5_PVID); + reg &= ~(ADM_P2_PVID_MASK); + reg |= ADM_P5_PVID_VAL(priv->pvid[5]); + w16(priv, ADM_P5_PVID, reg); +} + +/* + * Precondition: reg_mutex must be held + */ +static void +adm6996_apply_vlan_filters(struct adm6996_priv *priv) +{ + u8 ports, tagged; + u16 vid, reg; + int i; + + for (i = 0; i < ADM_NUM_VLANS; i++) { + vid = priv->vlan_id[i]; + ports = priv->vlan_table[i]; + tagged = priv->vlan_tagged[i]; + + if (ports == 0) { + /* Disable VLAN entry */ + w16(priv, ADM_VLAN_FILT_H(i), 0); + w16(priv, ADM_VLAN_FILT_L(i), 0); + continue; + } + + reg = ADM_VLAN_FILT_MEMBER(ports); + reg |= ADM_VLAN_FILT_TAGGED(tagged); + w16(priv, ADM_VLAN_FILT_L(i), reg); + reg = ADM_VLAN_FILT_VALID | ADM_VLAN_FILT_VID(vid); + w16(priv, ADM_VLAN_FILT_H(i), reg); + } +} + +static void +adm6996_apply_vlan_filters_6996l(struct adm6996_priv *priv) +{ + u8 ports; + u16 reg; + int i; + + for (i = 0; i < ADM_NUM_VLANS; i++) { + ports = priv->vlan_table[i]; + + if (ports == 0) { + /* Disable VLAN entry */ + w16(priv, ADM_VLAN_MAP(i), 0); + continue; + } else { + reg = ADM_VLAN_FILT(ports); + w16(priv, ADM_VLAN_MAP(i), reg); + } + } +} + +static int +adm6996_hw_apply(struct switch_dev *dev) +{ + struct adm6996_priv *priv = to_adm(dev); + + pr_devel("hw_apply\n"); + + mutex_lock(&priv->reg_mutex); + + if (!priv->enable_vlan) { + if (priv->vlan_enabled) { + if (priv->model == ADM6996L) + adm6996_disable_vlan_6996l(priv); + else + adm6996_disable_vlan(priv); + priv->vlan_enabled = 0; + } + goto out; + } + + if (!priv->vlan_enabled) { + if (priv->model == ADM6996L) + adm6996_enable_vlan_6996l(priv); + else + adm6996_enable_vlan(priv); + priv->vlan_enabled = 1; + } + + adm6996_apply_port_pvids(priv); + if (priv->model == ADM6996L) + adm6996_apply_vlan_filters_6996l(priv); + else + adm6996_apply_vlan_filters(priv); + +out: + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +/* + * Reset the switch + * + * The ADM6996 can't do a software-initiated reset, so we just initialise the + * registers we support in this driver. + * + * Precondition: reg_mutex must be held + */ +static void +adm6996_perform_reset (struct adm6996_priv *priv) +{ + int i; + + /* initialize port and vlan settings */ + for (i = 0; i < ADM_NUM_PORTS - 1; i++) { + w16(priv, adm_portcfg[i], ADM_PORTCFG_INIT | + ADM_PORTCFG_PVID(0)); + } + w16(priv, adm_portcfg[5], ADM_PORTCFG_CPU); + + if (priv->model == ADM6996M || priv->model == ADM6996FC) { + /* reset all PHY ports */ + for (i = 0; i < ADM_PHY_PORTS; i++) { + w16(priv, ADM_PHY_PORT(i), ADM_PHYCFG_INIT); + } + } + + priv->enable_vlan = 0; + priv->vlan_enabled = 0; + + for (i = 0; i < ADM_NUM_PORTS; i++) { + priv->pvid[i] = 0; + } + + for (i = 0; i < ADM_NUM_VLANS; i++) { + priv->vlan_id[i] = i; + priv->vlan_table[i] = 0; + priv->vlan_tagged[i] = 0; + } + + if (priv->model == ADM6996M) { + /* Clear VLAN priority map so prio's are unused */ + w16 (priv, ADM_VLAN_PRIOMAP, 0); + + adm6996_disable_vlan(priv); + adm6996_apply_port_pvids(priv); + } else if (priv->model == ADM6996L) { + /* Clear VLAN priority map so prio's are unused */ + w16 (priv, ADM_VLAN_PRIOMAP, 0); + + adm6996_disable_vlan_6996l(priv); + adm6996_apply_port_pvids(priv); + } +} + +static int +adm6996_reset_switch(struct switch_dev *dev) +{ + struct adm6996_priv *priv = to_adm(dev); + + pr_devel("reset\n"); + + mutex_lock(&priv->reg_mutex); + adm6996_perform_reset (priv); + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int +adm6996_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link) +{ + struct adm6996_priv *priv = to_adm(dev); + + u16 reg = 0; + + if (port >= ADM_NUM_PORTS) + return -EINVAL; + + switch (port) { + case 0: + reg = r16(priv, ADM_PS0); + break; + case 1: + reg = r16(priv, ADM_PS0); + reg = reg >> 8; + break; + case 2: + reg = r16(priv, ADM_PS1); + break; + case 3: + reg = r16(priv, ADM_PS1); + reg = reg >> 8; + break; + case 4: + reg = r16(priv, ADM_PS1); + reg = reg >> 12; + break; + case 5: + reg = r16(priv, ADM_PS2); + /* Bits 0, 1, 3 and 4. */ + reg = (reg & 3) | ((reg & 24) >> 1); + break; + default: + return -EINVAL; + } + + link->link = reg & ADM_PS_LS; + if (!link->link) + return 0; + link->aneg = true; + link->duplex = reg & ADM_PS_DS; + link->tx_flow = reg & ADM_PS_FCS; + link->rx_flow = reg & ADM_PS_FCS; + if (reg & ADM_PS_SS) + link->speed = SWITCH_PORT_SPEED_100; + else + link->speed = SWITCH_PORT_SPEED_10; + + return 0; +} + +static int +adm6996_sw_get_port_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct adm6996_priv *priv = to_adm(dev); + int port; + char *buf = priv->buf; + int i, len = 0; + u32 reg = 0; + + port = val->port_vlan; + if (port >= ADM_NUM_PORTS) + return -EINVAL; + + mutex_lock(&priv->mib_lock); + + len += snprintf(buf + len, sizeof(priv->buf) - len, + "Port %d MIB counters\n", + port); + + for (i = 0; i < ARRAY_SIZE(adm6996_mibs); i++) { + reg = r16(priv, adm6996_mibs[i].offset + ADM_OFFSET_PORT(port)); + reg += r16(priv, adm6996_mibs[i].offset + ADM_OFFSET_PORT(port) + 1) << 16; + len += snprintf(buf + len, sizeof(priv->buf) - len, + "%-12s: %u\n", + adm6996_mibs[i].name, + reg); + } + + mutex_unlock(&priv->mib_lock); + + val->value.s = buf; + val->len = len; + + return 0; +} + +static struct switch_attr adm6996_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLANs", + .set = adm6996_set_enable_vlan, + .get = adm6996_get_enable_vlan, + }, +#ifdef DEBUG + { + .type = SWITCH_TYPE_INT, + .name = "addr", + .description = + "Direct register access: set register address (0 - 1023)", + .set = adm6996_set_addr, + .get = adm6996_get_addr, + }, + { + .type = SWITCH_TYPE_INT, + .name = "data", + .description = + "Direct register access: read/write to register (0 - 65535)", + .set = adm6996_set_data, + .get = adm6996_get_data, + }, +#endif /* def DEBUG */ +}; + +static struct switch_attr adm6996_port[] = { + { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get port's MIB counters", + .set = NULL, + .get = adm6996_sw_get_port_mib, + }, +}; + +static struct switch_attr adm6996_vlan[] = { + { + .type = SWITCH_TYPE_INT, + .name = "vid", + .description = "VLAN ID", + .set = adm6996_set_vid, + .get = adm6996_get_vid, + }, +}; + +static struct switch_dev_ops adm6996_ops = { + .attr_global = { + .attr = adm6996_globals, + .n_attr = ARRAY_SIZE(adm6996_globals), + }, + .attr_port = { + .attr = adm6996_port, + .n_attr = ARRAY_SIZE(adm6996_port), + }, + .attr_vlan = { + .attr = adm6996_vlan, + .n_attr = ARRAY_SIZE(adm6996_vlan), + }, + .get_port_pvid = adm6996_get_pvid, + .set_port_pvid = adm6996_set_pvid, + .get_vlan_ports = adm6996_get_ports, + .set_vlan_ports = adm6996_set_ports, + .apply_config = adm6996_hw_apply, + .reset_switch = adm6996_reset_switch, + .get_port_link = adm6996_get_port_link, +}; + +static int adm6996_switch_init(struct adm6996_priv *priv, const char *alias, struct net_device *netdev) +{ + struct switch_dev *swdev; + u16 test, old; + + if (!priv->model) { + /* Detect type of chip */ + old = r16(priv, ADM_VID_CHECK); + test = old ^ (1 << 12); + w16(priv, ADM_VID_CHECK, test); + test ^= r16(priv, ADM_VID_CHECK); + if (test & (1 << 12)) { + /* + * Bit 12 of this register is read-only. + * This is the FC model. + */ + priv->model = ADM6996FC; + } else { + /* Bit 12 is read-write. This is the M model. */ + priv->model = ADM6996M; + w16(priv, ADM_VID_CHECK, old); + } + } + + swdev = &priv->dev; + swdev->name = (adm6996_model_name[priv->model]); + swdev->cpu_port = ADM_CPU_PORT; + swdev->ports = ADM_NUM_PORTS; + swdev->vlans = ADM_NUM_VLANS; + swdev->ops = &adm6996_ops; + swdev->alias = alias; + + /* The ADM6996L connected through GPIOs does not support any switch + status calls */ + if (priv->model == ADM6996L) { + adm6996_ops.attr_port.n_attr = 0; + adm6996_ops.get_port_link = NULL; + } + + pr_info ("%s: %s model PHY found.\n", alias, swdev->name); + + mutex_lock(&priv->reg_mutex); + adm6996_perform_reset (priv); + mutex_unlock(&priv->reg_mutex); + + if (priv->model == ADM6996M || priv->model == ADM6996L) { + return register_switch(swdev, netdev); + } + + return -ENODEV; +} + +static int adm6996_config_init(struct phy_device *pdev) +{ + struct adm6996_priv *priv; + int ret; + + pdev->supported = ADVERTISED_100baseT_Full; + pdev->advertising = ADVERTISED_100baseT_Full; + + if (pdev->addr != 0) { + pr_info ("%s: PHY overlaps ADM6996, providing fixed PHY 0x%x.\n" + , pdev->attached_dev->name, pdev->addr); + return 0; + } + + priv = devm_kzalloc(&pdev->dev, sizeof(struct adm6996_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->reg_mutex); + mutex_init(&priv->mib_lock); + priv->priv = pdev; + priv->read = adm6996_read_mii_reg; + priv->write = adm6996_write_mii_reg; + + ret = adm6996_switch_init(priv, pdev->attached_dev->name, pdev->attached_dev); + if (ret < 0) + return ret; + + pdev->priv = priv; + + return 0; +} + +/* + * Warning: phydev->priv is NULL if phydev->addr != 0 + */ +static int adm6996_read_status(struct phy_device *phydev) +{ + phydev->speed = SPEED_100; + phydev->duplex = DUPLEX_FULL; + phydev->link = 1; + return 0; +} + +/* + * Warning: phydev->priv is NULL if phydev->addr != 0 + */ +static int adm6996_config_aneg(struct phy_device *phydev) +{ + return 0; +} + +static int adm6996_fixup(struct phy_device *dev) +{ + struct mii_bus *bus = dev->bus; + u16 reg; + + /* Our custom registers are at PHY addresses 0-10. Claim those. */ + if (dev->addr > 10) + return 0; + + /* look for the switch on the bus */ + reg = bus->read(bus, PHYADDR(ADM_SIG0)) & ADM_SIG0_MASK; + if (reg != ADM_SIG0_VAL) + return 0; + + reg = bus->read(bus, PHYADDR(ADM_SIG1)) & ADM_SIG1_MASK; + if (reg != ADM_SIG1_VAL) + return 0; + + dev->phy_id = (ADM_SIG0_VAL << 16) | ADM_SIG1_VAL; + + return 0; +} + +static int adm6996_probe(struct phy_device *pdev) +{ + return 0; +} + +static void adm6996_remove(struct phy_device *pdev) +{ + struct adm6996_priv *priv = phy_to_adm(pdev); + + if (priv && (priv->model == ADM6996M || priv->model == ADM6996L)) + unregister_switch(&priv->dev); +} + +static int adm6996_soft_reset(struct phy_device *phydev) +{ + /* we don't need an extra reset */ + return 0; +} + +static struct phy_driver adm6996_phy_driver = { + .name = "Infineon ADM6996", + .phy_id = (ADM_SIG0_VAL << 16) | ADM_SIG1_VAL, + .phy_id_mask = 0xffffffff, + .features = PHY_BASIC_FEATURES, + .probe = adm6996_probe, + .remove = adm6996_remove, + .config_init = &adm6996_config_init, + .config_aneg = &adm6996_config_aneg, + .read_status = &adm6996_read_status, + .soft_reset = adm6996_soft_reset, + .driver = { .owner = THIS_MODULE,}, +}; + +static int adm6996_gpio_probe(struct platform_device *pdev) +{ + struct adm6996_gpio_platform_data *pdata = pdev->dev.platform_data; + struct adm6996_priv *priv; + int ret; + + if (!pdata) + return -EINVAL; + + priv = devm_kzalloc(&pdev->dev, sizeof(struct adm6996_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->reg_mutex); + mutex_init(&priv->mib_lock); + + priv->eecs = pdata->eecs; + priv->eedi = pdata->eedi; + priv->eerc = pdata->eerc; + priv->eesk = pdata->eesk; + + priv->model = pdata->model; + priv->read = adm6996_read_gpio_reg; + priv->write = adm6996_write_gpio_reg; + + ret = devm_gpio_request(&pdev->dev, priv->eecs, "adm_eecs"); + if (ret) + return ret; + ret = devm_gpio_request(&pdev->dev, priv->eedi, "adm_eedi"); + if (ret) + return ret; + ret = devm_gpio_request(&pdev->dev, priv->eerc, "adm_eerc"); + if (ret) + return ret; + ret = devm_gpio_request(&pdev->dev, priv->eesk, "adm_eesk"); + if (ret) + return ret; + + ret = adm6996_switch_init(priv, dev_name(&pdev->dev), NULL); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int adm6996_gpio_remove(struct platform_device *pdev) +{ + struct adm6996_priv *priv = platform_get_drvdata(pdev); + + if (priv && (priv->model == ADM6996M || priv->model == ADM6996L)) + unregister_switch(&priv->dev); + + return 0; +} + +static struct platform_driver adm6996_gpio_driver = { + .probe = adm6996_gpio_probe, + .remove = adm6996_gpio_remove, + .driver = { + .name = "adm6996_gpio", + }, +}; + +static int __init adm6996_init(void) +{ + int err; + + phy_register_fixup_for_id(PHY_ANY_ID, adm6996_fixup); + err = phy_driver_register(&adm6996_phy_driver); + if (err) + return err; + + err = platform_driver_register(&adm6996_gpio_driver); + if (err) + phy_driver_unregister(&adm6996_phy_driver); + + return err; +} + +static void __exit adm6996_exit(void) +{ + platform_driver_unregister(&adm6996_gpio_driver); + phy_driver_unregister(&adm6996_phy_driver); +} + +module_init(adm6996_init); +module_exit(adm6996_exit); diff --git a/target/linux/generic/files/drivers/net/phy/adm6996.h b/target/linux/generic/files/drivers/net/phy/adm6996.h new file mode 100644 index 0000000..66c77a0 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/adm6996.h @@ -0,0 +1,186 @@ +/* + * ADM6996 switch driver + * + * Copyright (c) 2008 Felix Fietkau + * Copyright (c) 2010,2011 Peter Lebbing + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License v2 as published by the + * Free Software Foundation + */ +#ifndef __ADM6996_H +#define __ADM6996_H + +/* + * ADM_PHY_PORTS: Number of ports with a PHY. + * We only control ports 0 to 3, because if 4 is connected, it is most likely + * not connected to the switch but to a separate MII and MAC for the WAN port. + */ +#define ADM_PHY_PORTS 4 +#define ADM_NUM_PORTS 6 +#define ADM_CPU_PORT 5 + +#define ADM_NUM_VLANS 16 +#define ADM_VLAN_MAX_ID 4094 + +enum admreg { + ADM_EEPROM_BASE = 0x0, + ADM_P0_CFG = ADM_EEPROM_BASE + 1, + ADM_P1_CFG = ADM_EEPROM_BASE + 3, + ADM_P2_CFG = ADM_EEPROM_BASE + 5, + ADM_P3_CFG = ADM_EEPROM_BASE + 7, + ADM_P4_CFG = ADM_EEPROM_BASE + 8, + ADM_P5_CFG = ADM_EEPROM_BASE + 9, + ADM_SYSC0 = ADM_EEPROM_BASE + 0xa, + ADM_VLAN_PRIOMAP = ADM_EEPROM_BASE + 0xe, + ADM_SYSC3 = ADM_EEPROM_BASE + 0x11, + /* Input Force No Tag Enable */ + ADM_IFNTE = ADM_EEPROM_BASE + 0x20, + ADM_VID_CHECK = ADM_EEPROM_BASE + 0x26, + ADM_P0_PVID = ADM_EEPROM_BASE + 0x28, + ADM_P1_PVID = ADM_EEPROM_BASE + 0x29, + /* Output Tag Bypass Enable and P2 PVID */ + ADM_OTBE_P2_PVID = ADM_EEPROM_BASE + 0x2a, + ADM_P3_P4_PVID = ADM_EEPROM_BASE + 0x2b, + ADM_P5_PVID = ADM_EEPROM_BASE + 0x2c, + ADM_EEPROM_EXT_BASE = 0x40, +#define ADM_VLAN_FILT_L(n) (ADM_EEPROM_EXT_BASE + 2 * (n)) +#define ADM_VLAN_FILT_H(n) (ADM_EEPROM_EXT_BASE + 1 + 2 * (n)) +#define ADM_VLAN_MAP(n) (ADM_EEPROM_BASE + 0x13 + n) + ADM_COUNTER_BASE = 0xa0, + ADM_SIG0 = ADM_COUNTER_BASE + 0, + ADM_SIG1 = ADM_COUNTER_BASE + 1, + ADM_PS0 = ADM_COUNTER_BASE + 2, + ADM_PS1 = ADM_COUNTER_BASE + 3, + ADM_PS2 = ADM_COUNTER_BASE + 4, + ADM_CL0 = ADM_COUNTER_BASE + 8, /* RxPacket */ + ADM_CL6 = ADM_COUNTER_BASE + 0x1a, /* RxByte */ + ADM_CL12 = ADM_COUNTER_BASE + 0x2c, /* TxPacket */ + ADM_CL18 = ADM_COUNTER_BASE + 0x3e, /* TxByte */ + ADM_CL24 = ADM_COUNTER_BASE + 0x50, /* Coll */ + ADM_CL30 = ADM_COUNTER_BASE + 0x62, /* Err */ +#define ADM_OFFSET_PORT(n) ((n * 4) - (n / 4) * 2 - (n / 5) * 2) + ADM_PHY_BASE = 0x200, +#define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n)) +}; + +/* Chip identification patterns */ +#define ADM_SIG0_MASK 0xffff +#define ADM_SIG0_VAL 0x1023 +#define ADM_SIG1_MASK 0xffff +#define ADM_SIG1_VAL 0x0007 + +enum { + ADM_PHYCFG_COLTST = (1 << 7), /* Enable collision test */ + ADM_PHYCFG_DPLX = (1 << 8), /* Enable full duplex */ + ADM_PHYCFG_ANEN_RST = (1 << 9), /* Restart auto negotiation (self clear) */ + ADM_PHYCFG_ISO = (1 << 10), /* Isolate PHY */ + ADM_PHYCFG_PDN = (1 << 11), /* Power down PHY */ + ADM_PHYCFG_ANEN = (1 << 12), /* Enable auto negotiation */ + ADM_PHYCFG_SPEED_100 = (1 << 13), /* Enable 100 Mbit/s */ + ADM_PHYCFG_LPBK = (1 << 14), /* Enable loopback operation */ + ADM_PHYCFG_RST = (1 << 15), /* Reset the port (self clear) */ + ADM_PHYCFG_INIT = ( + ADM_PHYCFG_RST | + ADM_PHYCFG_SPEED_100 | + ADM_PHYCFG_ANEN | + ADM_PHYCFG_ANEN_RST + ) +}; + +enum { + ADM_PORTCFG_FC = (1 << 0), /* Enable 802.x flow control */ + ADM_PORTCFG_AN = (1 << 1), /* Enable auto-negotiation */ + ADM_PORTCFG_SPEED_100 = (1 << 2), /* Enable 100 Mbit/s */ + ADM_PORTCFG_DPLX = (1 << 3), /* Enable full duplex */ + ADM_PORTCFG_OT = (1 << 4), /* Output tagged packets */ + ADM_PORTCFG_PD = (1 << 5), /* Port disable */ + ADM_PORTCFG_TV_PRIO = (1 << 6), /* 0 = VLAN based priority + * 1 = TOS based priority */ + ADM_PORTCFG_PPE = (1 << 7), /* Port based priority enable */ + ADM_PORTCFG_PP_S = (1 << 8), /* Port based priority, 2 bits */ + ADM_PORTCFG_PVID_BASE = (1 << 10), /* Primary VLAN id, 4 bits */ + ADM_PORTCFG_FSE = (1 << 14), /* Fx select enable */ + ADM_PORTCFG_CAM = (1 << 15), /* Crossover Auto MDIX */ + + ADM_PORTCFG_INIT = ( + ADM_PORTCFG_FC | + ADM_PORTCFG_AN | + ADM_PORTCFG_SPEED_100 | + ADM_PORTCFG_DPLX | + ADM_PORTCFG_CAM + ), + ADM_PORTCFG_CPU = ( + ADM_PORTCFG_FC | + ADM_PORTCFG_SPEED_100 | + ADM_PORTCFG_OT | + ADM_PORTCFG_DPLX + ), +}; + +#define ADM_PORTCFG_PPID(n) ((n & 0x3) << 8) +#define ADM_PORTCFG_PVID(n) ((n & 0xf) << 10) +#define ADM_PORTCFG_PVID_MASK (0xf << 10) + +#define ADM_IFNTE_MASK (0x3f << 9) +#define ADM_VID_CHECK_MASK (0x3f << 6) + +#define ADM_P0_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) +#define ADM_P1_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) +#define ADM_P2_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) +#define ADM_P3_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) +#define ADM_P4_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 8) +#define ADM_P5_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) +#define ADM_P2_PVID_MASK 0xff + +#define ADM_OTBE(n) (((n) & 0x3f) << 8) +#define ADM_OTBE_MASK (0x3f << 8) + +/* ADM_SYSC0 */ +enum { + ADM_NTTE = (1 << 2), /* New Tag Transmit Enable */ + ADM_RVID1 = (1 << 8) /* Replace VLAN ID 1 */ +}; + +/* Tag Based VLAN in ADM_SYSC3 */ +#define ADM_MAC_CLONE BIT(4) +#define ADM_TBV BIT(5) + +static const u8 adm_portcfg[] = { + [0] = ADM_P0_CFG, + [1] = ADM_P1_CFG, + [2] = ADM_P2_CFG, + [3] = ADM_P3_CFG, + [4] = ADM_P4_CFG, + [5] = ADM_P5_CFG, +}; + +/* Fields in ADM_VLAN_FILT_L(x) */ +#define ADM_VLAN_FILT_FID(n) (((n) & 0xf) << 12) +#define ADM_VLAN_FILT_TAGGED(n) (((n) & 0x3f) << 6) +#define ADM_VLAN_FILT_MEMBER(n) (((n) & 0x3f) << 0) +#define ADM_VLAN_FILT_MEMBER_MASK 0x3f +/* Fields in ADM_VLAN_FILT_H(x) */ +#define ADM_VLAN_FILT_VALID (1 << 15) +#define ADM_VLAN_FILT_VID(n) (((n) & 0xfff) << 0) + +/* Convert ports to a form for ADM6996L VLAN map */ +#define ADM_VLAN_FILT(ports) ((ports & 0x01) | ((ports & 0x02) << 1) | \ + ((ports & 0x04) << 2) | ((ports & 0x08) << 3) | \ + ((ports & 0x10) << 3) | ((ports & 0x20) << 3)) + +/* Port status register */ +enum { + ADM_PS_LS = (1 << 0), /* Link status */ + ADM_PS_SS = (1 << 1), /* Speed status */ + ADM_PS_DS = (1 << 2), /* Duplex status */ + ADM_PS_FCS = (1 << 3) /* Flow control status */ +}; + +/* + * Split the register address in phy id and register + * it will get combined again by the mdio bus op + */ +#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f) + +#endif diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.c b/target/linux/generic/files/drivers/net/phy/ar8216.c new file mode 100644 index 0000000..75db1f1 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/ar8216.c @@ -0,0 +1,2197 @@ +/* + * ar8216.c: AR8216 switch driver + * + * Copyright (C) 2009 Felix Fietkau + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ar8216.h" + +extern const struct ar8xxx_chip ar8327_chip; +extern const struct ar8xxx_chip ar8337_chip; + +#define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */ + +#define MIB_DESC(_s , _o, _n) \ + { \ + .size = (_s), \ + .offset = (_o), \ + .name = (_n), \ + } + +static const struct ar8xxx_mib_desc ar8216_mibs[] = { + MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"), + MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"), + MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"), + MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"), + MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"), + MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"), + MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"), + MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"), + MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"), + MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"), + MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"), + MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"), + MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"), + MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"), + MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"), + MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"), + MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"), + MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"), + MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"), + MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"), + MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"), + MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"), + MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"), + MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"), + MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"), + MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"), + MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"), + MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"), + MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"), + MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"), + MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"), + MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"), + MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"), + MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"), + MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"), + MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"), + MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"), +}; + +const struct ar8xxx_mib_desc ar8236_mibs[39] = { + MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"), + MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"), + MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"), + MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"), + MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"), + MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"), + MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"), + MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"), + MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"), + MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"), + MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"), + MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"), + MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"), + MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"), + MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"), + MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"), + MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"), + MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"), + MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"), + MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"), + MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"), + MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"), + MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"), + MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"), + MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"), + MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"), + MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"), + MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"), + MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"), + MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"), + MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"), + MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"), + MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"), + MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"), + MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"), + MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"), + MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"), + MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"), + MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"), +}; + +static DEFINE_MUTEX(ar8xxx_dev_list_lock); +static LIST_HEAD(ar8xxx_dev_list); + +/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */ +static int +ar8xxx_phy_poll_reset(struct mii_bus *bus) +{ + unsigned int sleep_msecs = 20; + int ret, elapsed, i; + + for (elapsed = sleep_msecs; elapsed <= 600; + elapsed += sleep_msecs) { + msleep(sleep_msecs); + for (i = 0; i < AR8XXX_NUM_PHYS; i++) { + ret = mdiobus_read(bus, i, MII_BMCR); + if (ret < 0) + return ret; + if (ret & BMCR_RESET) + break; + if (i == AR8XXX_NUM_PHYS - 1) { + usleep_range(1000, 2000); + return 0; + } + } + } + return -ETIMEDOUT; +} + +static int +ar8xxx_phy_check_aneg(struct phy_device *phydev) +{ + int ret; + + if (phydev->autoneg != AUTONEG_ENABLE) + return 0; + /* + * BMCR_ANENABLE might have been cleared + * by phy_init_hw in certain kernel versions + * therefore check for it + */ + ret = phy_read(phydev, MII_BMCR); + if (ret < 0) + return ret; + if (ret & BMCR_ANENABLE) + return 0; + + dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n"); + ret |= BMCR_ANENABLE | BMCR_ANRESTART; + return phy_write(phydev, MII_BMCR, ret); +} + +void +ar8xxx_phy_init(struct ar8xxx_priv *priv) +{ + int i; + struct mii_bus *bus; + + bus = priv->mii_bus; + for (i = 0; i < AR8XXX_NUM_PHYS; i++) { + if (priv->chip->phy_fixup) + priv->chip->phy_fixup(priv, i); + + /* initialize the port itself */ + mdiobus_write(bus, i, MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); + if (ar8xxx_has_gige(priv)) + mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL); + mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); + } + + ar8xxx_phy_poll_reset(bus); +} + +u32 +ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum) +{ + struct mii_bus *bus = priv->mii_bus; + u16 lo, hi; + + lo = bus->read(bus, phy_id, regnum); + hi = bus->read(bus, phy_id, regnum + 1); + + return (hi << 16) | lo; +} + +void +ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val) +{ + struct mii_bus *bus = priv->mii_bus; + u16 lo, hi; + + lo = val & 0xffff; + hi = (u16) (val >> 16); + + if (priv->chip->mii_lo_first) + { + bus->write(bus, phy_id, regnum, lo); + bus->write(bus, phy_id, regnum + 1, hi); + } else { + bus->write(bus, phy_id, regnum + 1, hi); + bus->write(bus, phy_id, regnum, lo); + } +} + +u32 +ar8xxx_read(struct ar8xxx_priv *priv, int reg) +{ + struct mii_bus *bus = priv->mii_bus; + u16 r1, r2, page; + u32 val; + + split_addr((u32) reg, &r1, &r2, &page); + + mutex_lock(&bus->mdio_lock); + + bus->write(bus, 0x18, 0, page); + wait_for_page_switch(); + val = ar8xxx_mii_read32(priv, 0x10 | r2, r1); + + mutex_unlock(&bus->mdio_lock); + + return val; +} + +void +ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val) +{ + struct mii_bus *bus = priv->mii_bus; + u16 r1, r2, page; + + split_addr((u32) reg, &r1, &r2, &page); + + mutex_lock(&bus->mdio_lock); + + bus->write(bus, 0x18, 0, page); + wait_for_page_switch(); + ar8xxx_mii_write32(priv, 0x10 | r2, r1, val); + + mutex_unlock(&bus->mdio_lock); +} + +u32 +ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val) +{ + struct mii_bus *bus = priv->mii_bus; + u16 r1, r2, page; + u32 ret; + + split_addr((u32) reg, &r1, &r2, &page); + + mutex_lock(&bus->mdio_lock); + + bus->write(bus, 0x18, 0, page); + wait_for_page_switch(); + + ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1); + ret &= ~mask; + ret |= val; + ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret); + + mutex_unlock(&bus->mdio_lock); + + return ret; +} + +void +ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr, + u16 dbg_addr, u16 dbg_data) +{ + struct mii_bus *bus = priv->mii_bus; + + mutex_lock(&bus->mdio_lock); + bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); + bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data); + mutex_unlock(&bus->mdio_lock); +} + +void +ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data) +{ + struct mii_bus *bus = priv->mii_bus; + + mutex_lock(&bus->mdio_lock); + bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr); + bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data); + mutex_unlock(&bus->mdio_lock); +} + +u16 +ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr) +{ + struct mii_bus *bus = priv->mii_bus; + u16 data; + + mutex_lock(&bus->mdio_lock); + bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr); + data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA); + mutex_unlock(&bus->mdio_lock); + + return data; +} + +static int +ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val, + unsigned timeout) +{ + int i; + + for (i = 0; i < timeout; i++) { + u32 t; + + t = ar8xxx_read(priv, reg); + if ((t & mask) == val) + return 0; + + usleep_range(1000, 2000); + } + + return -ETIMEDOUT; +} + +static int +ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op) +{ + unsigned mib_func = priv->chip->mib_func; + int ret; + + lockdep_assert_held(&priv->mib_lock); + + /* Capture the hardware statistics for all ports */ + ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S)); + + /* Wait for the capturing to complete. */ + ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10); + if (ret) + goto out; + + ret = 0; + +out: + return ret; +} + +static int +ar8xxx_mib_capture(struct ar8xxx_priv *priv) +{ + return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE); +} + +static int +ar8xxx_mib_flush(struct ar8xxx_priv *priv) +{ + return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH); +} + +static void +ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush) +{ + unsigned int base; + u64 *mib_stats; + int i; + + WARN_ON(port >= priv->dev.ports); + + lockdep_assert_held(&priv->mib_lock); + + base = priv->chip->reg_port_stats_start + + priv->chip->reg_port_stats_length * port; + + mib_stats = &priv->mib_stats[port * priv->chip->num_mibs]; + for (i = 0; i < priv->chip->num_mibs; i++) { + const struct ar8xxx_mib_desc *mib; + u64 t; + + mib = &priv->chip->mib_decs[i]; + t = ar8xxx_read(priv, base + mib->offset); + if (mib->size == 2) { + u64 hi; + + hi = ar8xxx_read(priv, base + mib->offset + 4); + t |= hi << 32; + } + + if (flush) + mib_stats[i] = 0; + else + mib_stats[i] += t; + } +} + +static void +ar8216_read_port_link(struct ar8xxx_priv *priv, int port, + struct switch_port_link *link) +{ + u32 status; + u32 speed; + + memset(link, '\0', sizeof(*link)); + + status = priv->chip->read_port_status(priv, port); + + link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO); + if (link->aneg) { + link->link = !!(status & AR8216_PORT_STATUS_LINK_UP); + } else { + link->link = true; + + if (priv->get_port_link) { + int err; + + err = priv->get_port_link(port); + if (err >= 0) + link->link = !!err; + } + } + + if (!link->link) + return; + + link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX); + link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW); + link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW); + + if (link->aneg && link->duplex && priv->chip->read_port_eee_status) + link->eee = priv->chip->read_port_eee_status(priv, port); + + speed = (status & AR8216_PORT_STATUS_SPEED) >> + AR8216_PORT_STATUS_SPEED_S; + + switch (speed) { + case AR8216_PORT_SPEED_10M: + link->speed = SWITCH_PORT_SPEED_10; + break; + case AR8216_PORT_SPEED_100M: + link->speed = SWITCH_PORT_SPEED_100; + break; + case AR8216_PORT_SPEED_1000M: + link->speed = SWITCH_PORT_SPEED_1000; + break; + default: + link->speed = SWITCH_PORT_SPEED_UNKNOWN; + break; + } +} + +static struct sk_buff * +ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb) +{ + struct ar8xxx_priv *priv = dev->phy_ptr; + unsigned char *buf; + + if (unlikely(!priv)) + goto error; + + if (!priv->vlan) + goto send; + + if (unlikely(skb_headroom(skb) < 2)) { + if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0) + goto error; + } + + buf = skb_push(skb, 2); + buf[0] = 0x10; + buf[1] = 0x80; + +send: + return skb; + +error: + dev_kfree_skb_any(skb); + return NULL; +} + +static void +ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb) +{ + struct ar8xxx_priv *priv; + unsigned char *buf; + int port, vlan; + + priv = dev->phy_ptr; + if (!priv) + return; + + /* don't strip the header if vlan mode is disabled */ + if (!priv->vlan) + return; + + /* strip header, get vlan id */ + buf = skb->data; + skb_pull(skb, 2); + + /* check for vlan header presence */ + if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00)) + return; + + port = buf[0] & 0xf; + + /* no need to fix up packets coming from a tagged source */ + if (priv->vlan_tagged & (1 << port)) + return; + + /* lookup port vid from local table, the switch passes an invalid vlan id */ + vlan = priv->vlan_id[priv->pvid[port]]; + + buf[14 + 2] &= 0xf0; + buf[14 + 2] |= vlan >> 8; + buf[15 + 2] = vlan & 0xff; +} + +int +ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val) +{ + int timeout = 20; + u32 t = 0; + + while (1) { + t = ar8xxx_read(priv, reg); + if ((t & mask) == val) + return 0; + + if (timeout-- <= 0) + break; + + udelay(10); + } + + pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n", + (unsigned int) reg, t, mask, val); + return -ETIMEDOUT; +} + +static void +ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val) +{ + if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0)) + return; + if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) { + val &= AR8216_VTUDATA_MEMBER; + val |= AR8216_VTUDATA_VALID; + ar8xxx_write(priv, AR8216_REG_VTU_DATA, val); + } + op |= AR8216_VTU_ACTIVE; + ar8xxx_write(priv, AR8216_REG_VTU, op); +} + +static void +ar8216_vtu_flush(struct ar8xxx_priv *priv) +{ + ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0); +} + +static void +ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask) +{ + u32 op; + + op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S); + ar8216_vtu_op(priv, op, port_mask); +} + +static int +ar8216_atu_flush(struct ar8xxx_priv *priv) +{ + int ret; + + ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0); + if (!ret) + ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH | + AR8216_ATU_ACTIVE); + + return ret; +} + +static int +ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port) +{ + u32 t; + int ret; + + ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0); + if (!ret) { + t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT; + t |= AR8216_ATU_ACTIVE; + ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t); + } + + return ret; +} + +static u32 +ar8216_read_port_status(struct ar8xxx_priv *priv, int port) +{ + return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port)); +} + +static void +ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members) +{ + u32 header; + u32 egress, ingress; + u32 pvid; + + if (priv->vlan) { + pvid = priv->vlan_id[priv->pvid[port]]; + if (priv->vlan_tagged & (1 << port)) + egress = AR8216_OUT_ADD_VLAN; + else + egress = AR8216_OUT_STRIP_VLAN; + ingress = AR8216_IN_SECURE; + } else { + pvid = port; + egress = AR8216_OUT_KEEP; + ingress = AR8216_IN_PORT_ONLY; + } + + if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU) + header = AR8216_PORT_CTRL_HEADER; + else + header = 0; + + ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port), + AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE | + AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE | + AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK, + AR8216_PORT_CTRL_LEARN | header | + (egress << AR8216_PORT_CTRL_VLAN_MODE_S) | + (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S)); + + ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port), + AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE | + AR8216_PORT_VLAN_DEFAULT_ID, + (members << AR8216_PORT_VLAN_DEST_PORTS_S) | + (ingress << AR8216_PORT_VLAN_MODE_S) | + (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S)); +} + +static int +ar8216_hw_init(struct ar8xxx_priv *priv) +{ + if (priv->initialized) + return 0; + + ar8xxx_phy_init(priv); + + priv->initialized = true; + return 0; +} + +static void +ar8216_init_globals(struct ar8xxx_priv *priv) +{ + /* standard atheros magic */ + ar8xxx_write(priv, 0x38, 0xc000050e); + + ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL, + AR8216_GCTRL_MTU, 1518 + 8 + 2); +} + +static void +ar8216_init_port(struct ar8xxx_priv *priv, int port) +{ + /* Enable port learning and tx */ + ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port), + AR8216_PORT_CTRL_LEARN | + (4 << AR8216_PORT_CTRL_STATE_S)); + + ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0); + + if (port == AR8216_PORT_CPU) { + ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port), + AR8216_PORT_STATUS_LINK_UP | + (ar8xxx_has_gige(priv) ? + AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) | + AR8216_PORT_STATUS_TXMAC | + AR8216_PORT_STATUS_RXMAC | + (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) | + (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) | + AR8216_PORT_STATUS_DUPLEX); + } else { + ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port), + AR8216_PORT_STATUS_LINK_AUTO); + } +} + +static void +ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1) +{ + int timeout = 20; + + while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) + udelay(10); + + if (!timeout) + pr_err("ar8216: timeout waiting for atu to become ready\n"); +} + +static void ar8216_get_arl_entry(struct ar8xxx_priv *priv, + struct arl_entry *a, u32 *status, enum arl_op op) +{ + struct mii_bus *bus = priv->mii_bus; + u16 r2, page; + u16 r1_func0, r1_func1, r1_func2; + u32 t, val0, val1, val2; + int i; + + split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page); + r2 |= 0x10; + + r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e; + r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e; + + switch (op) { + case AR8XXX_ARL_INITIALIZE: + /* all ATU registers are on the same page + * therefore set page only once + */ + bus->write(bus, 0x18, 0, page); + wait_for_page_switch(); + + ar8216_wait_atu_ready(priv, r2, r1_func0); + + ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT); + ar8xxx_mii_write32(priv, r2, r1_func1, 0); + ar8xxx_mii_write32(priv, r2, r1_func2, 0); + break; + case AR8XXX_ARL_GET_NEXT: + t = ar8xxx_mii_read32(priv, r2, r1_func0); + t |= AR8216_ATU_ACTIVE; + ar8xxx_mii_write32(priv, r2, r1_func0, t); + ar8216_wait_atu_ready(priv, r2, r1_func0); + + val0 = ar8xxx_mii_read32(priv, r2, r1_func0); + val1 = ar8xxx_mii_read32(priv, r2, r1_func1); + val2 = ar8xxx_mii_read32(priv, r2, r1_func2); + + *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S; + if (!*status) + break; + + i = 0; + t = AR8216_ATU_PORT0; + while (!(val2 & t) && ++i < priv->dev.ports) + t <<= 1; + + a->port = i; + a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S; + a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S; + a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S; + a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S; + a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S; + a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S; + break; + } +} + +static void +ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members) +{ + u32 egress, ingress; + u32 pvid; + + if (priv->vlan) { + pvid = priv->vlan_id[priv->pvid[port]]; + if (priv->vlan_tagged & (1 << port)) + egress = AR8216_OUT_ADD_VLAN; + else + egress = AR8216_OUT_STRIP_VLAN; + ingress = AR8216_IN_SECURE; + } else { + pvid = port; + egress = AR8216_OUT_KEEP; + ingress = AR8216_IN_PORT_ONLY; + } + + ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port), + AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE | + AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE | + AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK, + AR8216_PORT_CTRL_LEARN | + (egress << AR8216_PORT_CTRL_VLAN_MODE_S) | + (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S)); + + ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port), + AR8236_PORT_VLAN_DEFAULT_ID, + (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S)); + + ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port), + AR8236_PORT_VLAN2_VLAN_MODE | + AR8236_PORT_VLAN2_MEMBER, + (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) | + (members << AR8236_PORT_VLAN2_MEMBER_S)); +} + +static void +ar8236_init_globals(struct ar8xxx_priv *priv) +{ + /* enable jumbo frames */ + ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL, + AR8316_GCTRL_MTU, 9018 + 8 + 2); + + /* enable cpu port to receive arp frames */ + ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL, + AR8236_ATU_CTRL_RES); + + /* enable cpu port to receive multicast and broadcast frames */ + ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK, + AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN); + + /* Enable MIB counters */ + ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN, + (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) | + AR8236_MIB_EN); +} + +static int +ar8316_hw_init(struct ar8xxx_priv *priv) +{ + u32 val, newval; + + val = ar8xxx_read(priv, AR8316_REG_POSTRIP); + + if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) { + if (priv->port4_phy) { + /* value taken from Ubiquiti RouterStation Pro */ + newval = 0x81461bea; + pr_info("ar8316: Using port 4 as PHY\n"); + } else { + newval = 0x01261be2; + pr_info("ar8316: Using port 4 as switch port\n"); + } + } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) { + /* value taken from AVM Fritz!Box 7390 sources */ + newval = 0x010e5b71; + } else { + /* no known value for phy interface */ + pr_err("ar8316: unsupported mii mode: %d.\n", + priv->phy->interface); + return -EINVAL; + } + + if (val == newval) + goto out; + + ar8xxx_write(priv, AR8316_REG_POSTRIP, newval); + + if (priv->port4_phy && + priv->phy->interface == PHY_INTERFACE_MODE_RGMII) { + /* work around for phy4 rgmii mode */ + ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c); + /* rx delay */ + ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e); + /* tx delay */ + ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47); + msleep(1000); + } + + ar8xxx_phy_init(priv); + +out: + priv->initialized = true; + return 0; +} + +static void +ar8316_init_globals(struct ar8xxx_priv *priv) +{ + /* standard atheros magic */ + ar8xxx_write(priv, 0x38, 0xc000050e); + + /* enable cpu port to receive multicast and broadcast frames */ + ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f); + + /* enable jumbo frames */ + ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL, + AR8316_GCTRL_MTU, 9018 + 8 + 2); + + /* Enable MIB counters */ + ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN, + (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) | + AR8236_MIB_EN); +} + +int +ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + priv->vlan = !!val->value.i; + return 0; +} + +int +ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + val->value.i = priv->vlan; + return 0; +} + + +int +ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + /* make sure no invalid PVIDs get set */ + + if (vlan >= dev->vlans) + return -EINVAL; + + priv->pvid[port] = vlan; + return 0; +} + +int +ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + *vlan = priv->pvid[port]; + return 0; +} + +static int +ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + priv->vlan_id[val->port_vlan] = val->value.i; + return 0; +} + +static int +ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + val->value.i = priv->vlan_id[val->port_vlan]; + return 0; +} + +int +ar8xxx_sw_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + ar8216_read_port_link(priv, port, link); + return 0; +} + +static int +ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + u8 ports = priv->vlan_table[val->port_vlan]; + int i; + + val->len = 0; + for (i = 0; i < dev->ports; i++) { + struct switch_port *p; + + if (!(ports & (1 << i))) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if (priv->vlan_tagged & (1 << i)) + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); + else + p->flags = 0; + } + return 0; +} + +static int +ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + u8 *vt = &priv->vlan_table[val->port_vlan]; + int i, j; + + *vt = 0; + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) { + priv->vlan_tagged |= (1 << p->id); + } else { + priv->vlan_tagged &= ~(1 << p->id); + priv->pvid[p->id] = val->port_vlan; + + /* make sure that an untagged port does not + * appear in other vlans */ + for (j = 0; j < AR8X16_MAX_VLANS; j++) { + if (j == val->port_vlan) + continue; + priv->vlan_table[j] &= ~(1 << p->id); + } + } + + *vt |= 1 << p->id; + } + return 0; +} + +static void +ar8216_set_mirror_regs(struct ar8xxx_priv *priv) +{ + int port; + + /* reset all mirror registers */ + ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT, + AR8216_GLOBAL_CPUPORT_MIRROR_PORT, + (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S)); + for (port = 0; port < AR8216_NUM_PORTS; port++) { + ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port), + AR8216_PORT_CTRL_MIRROR_RX); + + ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port), + AR8216_PORT_CTRL_MIRROR_TX); + } + + /* now enable mirroring if necessary */ + if (priv->source_port >= AR8216_NUM_PORTS || + priv->monitor_port >= AR8216_NUM_PORTS || + priv->source_port == priv->monitor_port) { + return; + } + + ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT, + AR8216_GLOBAL_CPUPORT_MIRROR_PORT, + (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S)); + + if (priv->mirror_rx) + ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port), + AR8216_PORT_CTRL_MIRROR_RX); + + if (priv->mirror_tx) + ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port), + AR8216_PORT_CTRL_MIRROR_TX); +} + +int +ar8xxx_sw_hw_apply(struct switch_dev *dev) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + u8 portmask[AR8X16_MAX_PORTS]; + int i, j; + + mutex_lock(&priv->reg_mutex); + /* flush all vlan translation unit entries */ + priv->chip->vtu_flush(priv); + + memset(portmask, 0, sizeof(portmask)); + if (!priv->init) { + /* calculate the port destination masks and load vlans + * into the vlan translation unit */ + for (j = 0; j < AR8X16_MAX_VLANS; j++) { + u8 vp = priv->vlan_table[j]; + + if (!vp) + continue; + + for (i = 0; i < dev->ports; i++) { + u8 mask = (1 << i); + if (vp & mask) + portmask[i] |= vp & ~mask; + } + + priv->chip->vtu_load_vlan(priv, priv->vlan_id[j], + priv->vlan_table[j]); + } + } else { + /* vlan disabled: + * isolate all ports, but connect them to the cpu port */ + for (i = 0; i < dev->ports; i++) { + if (i == AR8216_PORT_CPU) + continue; + + portmask[i] = 1 << AR8216_PORT_CPU; + portmask[AR8216_PORT_CPU] |= (1 << i); + } + } + + /* update the port destination mask registers and tag settings */ + for (i = 0; i < dev->ports; i++) { + priv->chip->setup_port(priv, i, portmask[i]); + } + + priv->chip->set_mirror_regs(priv); + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +int +ar8xxx_sw_reset_switch(struct switch_dev *dev) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + const struct ar8xxx_chip *chip = priv->chip; + int i; + + mutex_lock(&priv->reg_mutex); + memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) - + offsetof(struct ar8xxx_priv, vlan)); + + for (i = 0; i < AR8X16_MAX_VLANS; i++) + priv->vlan_id[i] = i; + + /* Configure all ports */ + for (i = 0; i < dev->ports; i++) + chip->init_port(priv, i); + + priv->mirror_rx = false; + priv->mirror_tx = false; + priv->source_port = 0; + priv->monitor_port = 0; + + chip->init_globals(priv); + + mutex_unlock(&priv->reg_mutex); + + return chip->sw_hw_apply(dev); +} + +int +ar8xxx_sw_set_reset_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + unsigned int len; + int ret; + + if (!ar8xxx_has_mib_counters(priv)) + return -EOPNOTSUPP; + + mutex_lock(&priv->mib_lock); + + len = priv->dev.ports * priv->chip->num_mibs * + sizeof(*priv->mib_stats); + memset(priv->mib_stats, '\0', len); + ret = ar8xxx_mib_flush(priv); + if (ret) + goto unlock; + + ret = 0; + +unlock: + mutex_unlock(&priv->mib_lock); + return ret; +} + +int +ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + mutex_lock(&priv->reg_mutex); + priv->mirror_rx = !!val->value.i; + priv->chip->set_mirror_regs(priv); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +int +ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + val->value.i = priv->mirror_rx; + return 0; +} + +int +ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + mutex_lock(&priv->reg_mutex); + priv->mirror_tx = !!val->value.i; + priv->chip->set_mirror_regs(priv); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +int +ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + val->value.i = priv->mirror_tx; + return 0; +} + +int +ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + mutex_lock(&priv->reg_mutex); + priv->monitor_port = val->value.i; + priv->chip->set_mirror_regs(priv); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +int +ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + val->value.i = priv->monitor_port; + return 0; +} + +int +ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + + mutex_lock(&priv->reg_mutex); + priv->source_port = val->value.i; + priv->chip->set_mirror_regs(priv); + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +int +ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + val->value.i = priv->source_port; + return 0; +} + +int +ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + int port; + int ret; + + if (!ar8xxx_has_mib_counters(priv)) + return -EOPNOTSUPP; + + port = val->port_vlan; + if (port >= dev->ports) + return -EINVAL; + + mutex_lock(&priv->mib_lock); + ret = ar8xxx_mib_capture(priv); + if (ret) + goto unlock; + + ar8xxx_mib_fetch_port_stat(priv, port, true); + + ret = 0; + +unlock: + mutex_unlock(&priv->mib_lock); + return ret; +} + +int +ar8xxx_sw_get_port_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + const struct ar8xxx_chip *chip = priv->chip; + u64 *mib_stats; + int port; + int ret; + char *buf = priv->buf; + int i, len = 0; + + if (!ar8xxx_has_mib_counters(priv)) + return -EOPNOTSUPP; + + port = val->port_vlan; + if (port >= dev->ports) + return -EINVAL; + + mutex_lock(&priv->mib_lock); + ret = ar8xxx_mib_capture(priv); + if (ret) + goto unlock; + + ar8xxx_mib_fetch_port_stat(priv, port, false); + + len += snprintf(buf + len, sizeof(priv->buf) - len, + "Port %d MIB counters\n", + port); + + mib_stats = &priv->mib_stats[port * chip->num_mibs]; + for (i = 0; i < chip->num_mibs; i++) + len += snprintf(buf + len, sizeof(priv->buf) - len, + "%-12s: %llu\n", + chip->mib_decs[i].name, + mib_stats[i]); + + val->value.s = buf; + val->len = len; + + ret = 0; + +unlock: + mutex_unlock(&priv->mib_lock); + return ret; +} + +int +ar8xxx_sw_get_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + struct mii_bus *bus = priv->mii_bus; + const struct ar8xxx_chip *chip = priv->chip; + char *buf = priv->arl_buf; + int i, j, k, len = 0; + struct arl_entry *a, *a1; + u32 status; + + if (!chip->get_arl_entry) + return -EOPNOTSUPP; + + mutex_lock(&priv->reg_mutex); + mutex_lock(&bus->mdio_lock); + + chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE); + + for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) { + a = &priv->arl_table[i]; + duplicate: + chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT); + + if (!status) + break; + + /* avoid duplicates + * ARL table can include multiple valid entries + * per MAC, just with differing status codes + */ + for (j = 0; j < i; ++j) { + a1 = &priv->arl_table[j]; + if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac))) + goto duplicate; + } + } + + mutex_unlock(&bus->mdio_lock); + + len += snprintf(buf + len, sizeof(priv->arl_buf) - len, + "address resolution table\n"); + + if (i == AR8XXX_NUM_ARL_RECORDS) + len += snprintf(buf + len, sizeof(priv->arl_buf) - len, + "Too many entries found, displaying the first %d only!\n", + AR8XXX_NUM_ARL_RECORDS); + + for (j = 0; j < priv->dev.ports; ++j) { + for (k = 0; k < i; ++k) { + a = &priv->arl_table[k]; + if (a->port != j) + continue; + len += snprintf(buf + len, sizeof(priv->arl_buf) - len, + "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + j, + a->mac[5], a->mac[4], a->mac[3], + a->mac[2], a->mac[1], a->mac[0]); + } + } + + val->value.s = buf; + val->len = len; + + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +int +ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + int ret; + + mutex_lock(&priv->reg_mutex); + ret = priv->chip->atu_flush(priv); + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +int +ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + int port, ret; + + port = val->port_vlan; + if (port >= dev->ports) + return -EINVAL; + + mutex_lock(&priv->reg_mutex); + ret = priv->chip->atu_flush_port(priv, port); + mutex_unlock(&priv->reg_mutex); + + return ret; +} + +static const struct switch_attr ar8xxx_sw_attr_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = ar8xxx_sw_set_vlan, + .get = ar8xxx_sw_get_vlan, + .max = 1 + }, + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mibs", + .description = "Reset all MIB counters", + .set = ar8xxx_sw_set_reset_mibs, + }, + { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_rx", + .description = "Enable mirroring of RX packets", + .set = ar8xxx_sw_set_mirror_rx_enable, + .get = ar8xxx_sw_get_mirror_rx_enable, + .max = 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_tx", + .description = "Enable mirroring of TX packets", + .set = ar8xxx_sw_set_mirror_tx_enable, + .get = ar8xxx_sw_get_mirror_tx_enable, + .max = 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "mirror_monitor_port", + .description = "Mirror monitor port", + .set = ar8xxx_sw_set_mirror_monitor_port, + .get = ar8xxx_sw_get_mirror_monitor_port, + .max = AR8216_NUM_PORTS - 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "mirror_source_port", + .description = "Mirror source port", + .set = ar8xxx_sw_set_mirror_source_port, + .get = ar8xxx_sw_get_mirror_source_port, + .max = AR8216_NUM_PORTS - 1 + }, + { + .type = SWITCH_TYPE_STRING, + .name = "arl_table", + .description = "Get ARL table", + .set = NULL, + .get = ar8xxx_sw_get_arl_table, + }, + { + .type = SWITCH_TYPE_NOVAL, + .name = "flush_arl_table", + .description = "Flush ARL table", + .set = ar8xxx_sw_set_flush_arl_table, + }, +}; + +const struct switch_attr ar8xxx_sw_attr_port[] = { + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mib", + .description = "Reset single port MIB counters", + .set = ar8xxx_sw_set_port_reset_mib, + }, + { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get port's MIB counters", + .set = NULL, + .get = ar8xxx_sw_get_port_mib, + }, + { + .type = SWITCH_TYPE_NOVAL, + .name = "flush_arl_table", + .description = "Flush port's ARL table entries", + .set = ar8xxx_sw_set_flush_port_arl_table, + }, +}; + +const struct switch_attr ar8xxx_sw_attr_vlan[1] = { + { + .type = SWITCH_TYPE_INT, + .name = "vid", + .description = "VLAN ID (0-4094)", + .set = ar8xxx_sw_set_vid, + .get = ar8xxx_sw_get_vid, + .max = 4094, + }, +}; + +static const struct switch_dev_ops ar8xxx_sw_ops = { + .attr_global = { + .attr = ar8xxx_sw_attr_globals, + .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals), + }, + .attr_port = { + .attr = ar8xxx_sw_attr_port, + .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port), + }, + .attr_vlan = { + .attr = ar8xxx_sw_attr_vlan, + .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan), + }, + .get_port_pvid = ar8xxx_sw_get_pvid, + .set_port_pvid = ar8xxx_sw_set_pvid, + .get_vlan_ports = ar8xxx_sw_get_ports, + .set_vlan_ports = ar8xxx_sw_set_ports, + .apply_config = ar8xxx_sw_hw_apply, + .reset_switch = ar8xxx_sw_reset_switch, + .get_port_link = ar8xxx_sw_get_port_link, +}; + +static const struct ar8xxx_chip ar8216_chip = { + .caps = AR8XXX_CAP_MIB_COUNTERS, + + .reg_port_stats_start = 0x19000, + .reg_port_stats_length = 0xa0, + + .name = "Atheros AR8216", + .ports = AR8216_NUM_PORTS, + .vlans = AR8216_NUM_VLANS, + .swops = &ar8xxx_sw_ops, + + .hw_init = ar8216_hw_init, + .init_globals = ar8216_init_globals, + .init_port = ar8216_init_port, + .setup_port = ar8216_setup_port, + .read_port_status = ar8216_read_port_status, + .atu_flush = ar8216_atu_flush, + .atu_flush_port = ar8216_atu_flush_port, + .vtu_flush = ar8216_vtu_flush, + .vtu_load_vlan = ar8216_vtu_load_vlan, + .set_mirror_regs = ar8216_set_mirror_regs, + .get_arl_entry = ar8216_get_arl_entry, + .sw_hw_apply = ar8xxx_sw_hw_apply, + + .num_mibs = ARRAY_SIZE(ar8216_mibs), + .mib_decs = ar8216_mibs, + .mib_func = AR8216_REG_MIB_FUNC +}; + +static const struct ar8xxx_chip ar8236_chip = { + .caps = AR8XXX_CAP_MIB_COUNTERS, + + .reg_port_stats_start = 0x20000, + .reg_port_stats_length = 0x100, + + .name = "Atheros AR8236", + .ports = AR8216_NUM_PORTS, + .vlans = AR8216_NUM_VLANS, + .swops = &ar8xxx_sw_ops, + + .hw_init = ar8216_hw_init, + .init_globals = ar8236_init_globals, + .init_port = ar8216_init_port, + .setup_port = ar8236_setup_port, + .read_port_status = ar8216_read_port_status, + .atu_flush = ar8216_atu_flush, + .atu_flush_port = ar8216_atu_flush_port, + .vtu_flush = ar8216_vtu_flush, + .vtu_load_vlan = ar8216_vtu_load_vlan, + .set_mirror_regs = ar8216_set_mirror_regs, + .get_arl_entry = ar8216_get_arl_entry, + .sw_hw_apply = ar8xxx_sw_hw_apply, + + .num_mibs = ARRAY_SIZE(ar8236_mibs), + .mib_decs = ar8236_mibs, + .mib_func = AR8216_REG_MIB_FUNC +}; + +static const struct ar8xxx_chip ar8316_chip = { + .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS, + + .reg_port_stats_start = 0x20000, + .reg_port_stats_length = 0x100, + + .name = "Atheros AR8316", + .ports = AR8216_NUM_PORTS, + .vlans = AR8X16_MAX_VLANS, + .swops = &ar8xxx_sw_ops, + + .hw_init = ar8316_hw_init, + .init_globals = ar8316_init_globals, + .init_port = ar8216_init_port, + .setup_port = ar8216_setup_port, + .read_port_status = ar8216_read_port_status, + .atu_flush = ar8216_atu_flush, + .atu_flush_port = ar8216_atu_flush_port, + .vtu_flush = ar8216_vtu_flush, + .vtu_load_vlan = ar8216_vtu_load_vlan, + .set_mirror_regs = ar8216_set_mirror_regs, + .get_arl_entry = ar8216_get_arl_entry, + .sw_hw_apply = ar8xxx_sw_hw_apply, + + .num_mibs = ARRAY_SIZE(ar8236_mibs), + .mib_decs = ar8236_mibs, + .mib_func = AR8216_REG_MIB_FUNC +}; + +static int +ar8xxx_id_chip(struct ar8xxx_priv *priv) +{ + u32 val; + u16 id; + int i; + + val = ar8xxx_read(priv, AR8216_REG_CTRL); + if (val == ~0) + return -ENODEV; + + id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION); + for (i = 0; i < AR8X16_PROBE_RETRIES; i++) { + u16 t; + + val = ar8xxx_read(priv, AR8216_REG_CTRL); + if (val == ~0) + return -ENODEV; + + t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION); + if (t != id) + return -ENODEV; + } + + priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S; + priv->chip_rev = (id & AR8216_CTRL_REVISION); + + switch (priv->chip_ver) { + case AR8XXX_VER_AR8216: + priv->chip = &ar8216_chip; + break; + case AR8XXX_VER_AR8236: + priv->chip = &ar8236_chip; + break; + case AR8XXX_VER_AR8316: + priv->chip = &ar8316_chip; + break; + case AR8XXX_VER_AR8327: + priv->chip = &ar8327_chip; + break; + case AR8XXX_VER_AR8337: + priv->chip = &ar8337_chip; + break; + default: + pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n", + priv->chip_ver, priv->chip_rev); + + return -ENODEV; + } + + return 0; +} + +static void +ar8xxx_mib_work_func(struct work_struct *work) +{ + struct ar8xxx_priv *priv; + int err; + + priv = container_of(work, struct ar8xxx_priv, mib_work.work); + + mutex_lock(&priv->mib_lock); + + err = ar8xxx_mib_capture(priv); + if (err) + goto next_port; + + ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false); + +next_port: + priv->mib_next_port++; + if (priv->mib_next_port >= priv->dev.ports) + priv->mib_next_port = 0; + + mutex_unlock(&priv->mib_lock); + schedule_delayed_work(&priv->mib_work, + msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY)); +} + +static int +ar8xxx_mib_init(struct ar8xxx_priv *priv) +{ + unsigned int len; + + if (!ar8xxx_has_mib_counters(priv)) + return 0; + + BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs); + + len = priv->dev.ports * priv->chip->num_mibs * + sizeof(*priv->mib_stats); + priv->mib_stats = kzalloc(len, GFP_KERNEL); + + if (!priv->mib_stats) + return -ENOMEM; + + return 0; +} + +static void +ar8xxx_mib_start(struct ar8xxx_priv *priv) +{ + if (!ar8xxx_has_mib_counters(priv)) + return; + + schedule_delayed_work(&priv->mib_work, + msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY)); +} + +static void +ar8xxx_mib_stop(struct ar8xxx_priv *priv) +{ + if (!ar8xxx_has_mib_counters(priv)) + return; + + cancel_delayed_work(&priv->mib_work); +} + +static struct ar8xxx_priv * +ar8xxx_create(void) +{ + struct ar8xxx_priv *priv; + + priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + + mutex_init(&priv->reg_mutex); + mutex_init(&priv->mib_lock); + INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func); + + return priv; +} + +static void +ar8xxx_free(struct ar8xxx_priv *priv) +{ + if (priv->chip && priv->chip->cleanup) + priv->chip->cleanup(priv); + + kfree(priv->chip_data); + kfree(priv->mib_stats); + kfree(priv); +} + +static int +ar8xxx_probe_switch(struct ar8xxx_priv *priv) +{ + const struct ar8xxx_chip *chip; + struct switch_dev *swdev; + int ret; + + ret = ar8xxx_id_chip(priv); + if (ret) + return ret; + + chip = priv->chip; + + swdev = &priv->dev; + swdev->cpu_port = AR8216_PORT_CPU; + swdev->name = chip->name; + swdev->vlans = chip->vlans; + swdev->ports = chip->ports; + swdev->ops = chip->swops; + + ret = ar8xxx_mib_init(priv); + if (ret) + return ret; + + return 0; +} + +static int +ar8xxx_start(struct ar8xxx_priv *priv) +{ + int ret; + + priv->init = true; + + ret = priv->chip->hw_init(priv); + if (ret) + return ret; + + ret = ar8xxx_sw_reset_switch(&priv->dev); + if (ret) + return ret; + + priv->init = false; + + ar8xxx_mib_start(priv); + + return 0; +} + +static int +ar8xxx_phy_config_init(struct phy_device *phydev) +{ + struct ar8xxx_priv *priv = phydev->priv; + struct net_device *dev = phydev->attached_dev; + int ret; + + if (WARN_ON(!priv)) + return -ENODEV; + + if (priv->chip->config_at_probe) + return ar8xxx_phy_check_aneg(phydev); + + priv->phy = phydev; + + if (phydev->addr != 0) { + if (chip_is_ar8316(priv)) { + /* switch device has been initialized, reinit */ + priv->dev.ports = (AR8216_NUM_PORTS - 1); + priv->initialized = false; + priv->port4_phy = true; + ar8316_hw_init(priv); + return 0; + } + + return 0; + } + + ret = ar8xxx_start(priv); + if (ret) + return ret; + + /* VID fixup only needed on ar8216 */ + if (chip_is_ar8216(priv)) { + dev->phy_ptr = priv; + dev->priv_flags |= IFF_NO_IP_ALIGN; + dev->eth_mangle_rx = ar8216_mangle_rx; + dev->eth_mangle_tx = ar8216_mangle_tx; + } + + return 0; +} + +static bool +ar8xxx_check_link_states(struct ar8xxx_priv *priv) +{ + bool link_new, changed = false; + u32 status; + int i; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < priv->dev.ports; i++) { + status = priv->chip->read_port_status(priv, i); + link_new = !!(status & AR8216_PORT_STATUS_LINK_UP); + if (link_new == priv->link_up[i]) + continue; + + priv->link_up[i] = link_new; + changed = true; + /* flush ARL entries for this port if it went down*/ + if (!link_new) + priv->chip->atu_flush_port(priv, i); + dev_info(&priv->phy->dev, "Port %d is %s\n", + i, link_new ? "up" : "down"); + } + + mutex_unlock(&priv->reg_mutex); + + return changed; +} + +static int +ar8xxx_phy_read_status(struct phy_device *phydev) +{ + struct ar8xxx_priv *priv = phydev->priv; + struct switch_port_link link; + + /* check for switch port link changes */ + if (phydev->state == PHY_CHANGELINK) + ar8xxx_check_link_states(priv); + + if (phydev->addr != 0) + return genphy_read_status(phydev); + + ar8216_read_port_link(priv, phydev->addr, &link); + phydev->link = !!link.link; + if (!phydev->link) + return 0; + + switch (link.speed) { + case SWITCH_PORT_SPEED_10: + phydev->speed = SPEED_10; + break; + case SWITCH_PORT_SPEED_100: + phydev->speed = SPEED_100; + break; + case SWITCH_PORT_SPEED_1000: + phydev->speed = SPEED_1000; + break; + default: + phydev->speed = 0; + } + phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF; + + phydev->state = PHY_RUNNING; + netif_carrier_on(phydev->attached_dev); + phydev->adjust_link(phydev->attached_dev); + + return 0; +} + +static int +ar8xxx_phy_config_aneg(struct phy_device *phydev) +{ + if (phydev->addr == 0) + return 0; + + return genphy_config_aneg(phydev); +} + +static const u32 ar8xxx_phy_ids[] = { + 0x004dd033, + 0x004dd034, /* AR8327 */ + 0x004dd036, /* AR8337 */ + 0x004dd041, + 0x004dd042, + 0x004dd043, /* AR8236 */ +}; + +static bool +ar8xxx_phy_match(u32 phy_id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++) + if (phy_id == ar8xxx_phy_ids[i]) + return true; + + return false; +} + +static bool +ar8xxx_is_possible(struct mii_bus *bus) +{ + unsigned i; + + for (i = 0; i < 4; i++) { + u32 phy_id; + + phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16; + phy_id |= mdiobus_read(bus, i, MII_PHYSID2); + if (!ar8xxx_phy_match(phy_id)) { + pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n", + dev_name(&bus->dev), i, phy_id); + return false; + } + } + + return true; +} + +static int +ar8xxx_phy_probe(struct phy_device *phydev) +{ + struct ar8xxx_priv *priv; + struct switch_dev *swdev; + int ret; + + /* skip PHYs at unused adresses */ + if (phydev->addr != 0 && phydev->addr != 4) + return -ENODEV; + + if (!ar8xxx_is_possible(phydev->bus)) + return -ENODEV; + + mutex_lock(&ar8xxx_dev_list_lock); + list_for_each_entry(priv, &ar8xxx_dev_list, list) + if (priv->mii_bus == phydev->bus) + goto found; + + priv = ar8xxx_create(); + if (priv == NULL) { + ret = -ENOMEM; + goto unlock; + } + + priv->mii_bus = phydev->bus; + + ret = ar8xxx_probe_switch(priv); + if (ret) + goto free_priv; + + swdev = &priv->dev; + swdev->alias = dev_name(&priv->mii_bus->dev); + ret = register_switch(swdev, NULL); + if (ret) + goto free_priv; + + pr_info("%s: %s rev. %u switch registered on %s\n", + swdev->devname, swdev->name, priv->chip_rev, + dev_name(&priv->mii_bus->dev)); + +found: + priv->use_count++; + + if (phydev->addr == 0) { + if (ar8xxx_has_gige(priv)) { + phydev->supported = SUPPORTED_1000baseT_Full; + phydev->advertising = ADVERTISED_1000baseT_Full; + } else { + phydev->supported = SUPPORTED_100baseT_Full; + phydev->advertising = ADVERTISED_100baseT_Full; + } + + if (priv->chip->config_at_probe) { + priv->phy = phydev; + + ret = ar8xxx_start(priv); + if (ret) + goto err_unregister_switch; + } + } else { + if (ar8xxx_has_gige(priv)) { + phydev->supported |= SUPPORTED_1000baseT_Full; + phydev->advertising |= ADVERTISED_1000baseT_Full; + } + } + + phydev->priv = priv; + + list_add(&priv->list, &ar8xxx_dev_list); + + mutex_unlock(&ar8xxx_dev_list_lock); + + return 0; + +err_unregister_switch: + if (--priv->use_count) + goto unlock; + + unregister_switch(&priv->dev); + +free_priv: + ar8xxx_free(priv); +unlock: + mutex_unlock(&ar8xxx_dev_list_lock); + return ret; +} + +static void +ar8xxx_phy_detach(struct phy_device *phydev) +{ + struct net_device *dev = phydev->attached_dev; + + if (!dev) + return; + + dev->phy_ptr = NULL; + dev->priv_flags &= ~IFF_NO_IP_ALIGN; + dev->eth_mangle_rx = NULL; + dev->eth_mangle_tx = NULL; +} + +static void +ar8xxx_phy_remove(struct phy_device *phydev) +{ + struct ar8xxx_priv *priv = phydev->priv; + + if (WARN_ON(!priv)) + return; + + phydev->priv = NULL; + if (--priv->use_count > 0) + return; + + mutex_lock(&ar8xxx_dev_list_lock); + list_del(&priv->list); + mutex_unlock(&ar8xxx_dev_list_lock); + + unregister_switch(&priv->dev); + ar8xxx_mib_stop(priv); + ar8xxx_free(priv); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) +static int +ar8xxx_phy_soft_reset(struct phy_device *phydev) +{ + /* we don't need an extra reset */ + return 0; +} +#endif + +static struct phy_driver ar8xxx_phy_driver = { + .phy_id = 0x004d0000, + .name = "Atheros AR8216/AR8236/AR8316", + .phy_id_mask = 0xffff0000, + .features = PHY_BASIC_FEATURES, + .probe = ar8xxx_phy_probe, + .remove = ar8xxx_phy_remove, + .detach = ar8xxx_phy_detach, + .config_init = ar8xxx_phy_config_init, + .config_aneg = ar8xxx_phy_config_aneg, + .read_status = ar8xxx_phy_read_status, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) + .soft_reset = ar8xxx_phy_soft_reset, +#endif + .driver = { .owner = THIS_MODULE }, +}; + +int __init +ar8xxx_init(void) +{ + return phy_driver_register(&ar8xxx_phy_driver); +} + +void __exit +ar8xxx_exit(void) +{ + phy_driver_unregister(&ar8xxx_phy_driver); +} + +module_init(ar8xxx_init); +module_exit(ar8xxx_exit); +MODULE_LICENSE("GPL"); + diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h new file mode 100644 index 0000000..14fe928 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -0,0 +1,628 @@ +/* + * ar8216.h: AR8216 switch driver + * + * Copyright (C) 2009 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AR8216_H +#define __AR8216_H + +#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) + +#define AR8XXX_CAP_GIGE BIT(0) +#define AR8XXX_CAP_MIB_COUNTERS BIT(1) + +#define AR8XXX_NUM_PHYS 5 +#define AR8216_PORT_CPU 0 +#define AR8216_NUM_PORTS 6 +#define AR8216_NUM_VLANS 16 +#define AR8316_NUM_VLANS 4096 + +/* size of the vlan table */ +#define AR8X16_MAX_VLANS 128 +#define AR8X16_PROBE_RETRIES 10 +#define AR8X16_MAX_PORTS 8 + +/* Atheros specific MII registers */ +#define MII_ATH_MMD_ADDR 0x0d +#define MII_ATH_MMD_DATA 0x0e +#define MII_ATH_DBG_ADDR 0x1d +#define MII_ATH_DBG_DATA 0x1e + +#define AR8216_REG_CTRL 0x0000 +#define AR8216_CTRL_REVISION BITS(0, 8) +#define AR8216_CTRL_REVISION_S 0 +#define AR8216_CTRL_VERSION BITS(8, 8) +#define AR8216_CTRL_VERSION_S 8 +#define AR8216_CTRL_RESET BIT(31) + +#define AR8216_REG_FLOOD_MASK 0x002C +#define AR8216_FM_UNI_DEST_PORTS BITS(0, 6) +#define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6) +#define AR8236_FM_CPU_BROADCAST_EN BIT(26) +#define AR8236_FM_CPU_BCAST_FWD_EN BIT(25) + +#define AR8216_REG_GLOBAL_CTRL 0x0030 +#define AR8216_GCTRL_MTU BITS(0, 11) +#define AR8236_GCTRL_MTU BITS(0, 14) +#define AR8316_GCTRL_MTU BITS(0, 14) + +#define AR8216_REG_VTU 0x0040 +#define AR8216_VTU_OP BITS(0, 3) +#define AR8216_VTU_OP_NOOP 0x0 +#define AR8216_VTU_OP_FLUSH 0x1 +#define AR8216_VTU_OP_LOAD 0x2 +#define AR8216_VTU_OP_PURGE 0x3 +#define AR8216_VTU_OP_REMOVE_PORT 0x4 +#define AR8216_VTU_ACTIVE BIT(3) +#define AR8216_VTU_FULL BIT(4) +#define AR8216_VTU_PORT BITS(8, 4) +#define AR8216_VTU_PORT_S 8 +#define AR8216_VTU_VID BITS(16, 12) +#define AR8216_VTU_VID_S 16 +#define AR8216_VTU_PRIO BITS(28, 3) +#define AR8216_VTU_PRIO_S 28 +#define AR8216_VTU_PRIO_EN BIT(31) + +#define AR8216_REG_VTU_DATA 0x0044 +#define AR8216_VTUDATA_MEMBER BITS(0, 10) +#define AR8236_VTUDATA_MEMBER BITS(0, 7) +#define AR8216_VTUDATA_VALID BIT(11) + +#define AR8216_REG_ATU_FUNC0 0x0050 +#define AR8216_ATU_OP BITS(0, 3) +#define AR8216_ATU_OP_NOOP 0x0 +#define AR8216_ATU_OP_FLUSH 0x1 +#define AR8216_ATU_OP_LOAD 0x2 +#define AR8216_ATU_OP_PURGE 0x3 +#define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4 +#define AR8216_ATU_OP_FLUSH_PORT 0x5 +#define AR8216_ATU_OP_GET_NEXT 0x6 +#define AR8216_ATU_ACTIVE BIT(3) +#define AR8216_ATU_PORT_NUM BITS(8, 4) +#define AR8216_ATU_PORT_NUM_S 8 +#define AR8216_ATU_FULL_VIO BIT(12) +#define AR8216_ATU_ADDR5 BITS(16, 8) +#define AR8216_ATU_ADDR5_S 16 +#define AR8216_ATU_ADDR4 BITS(24, 8) +#define AR8216_ATU_ADDR4_S 24 + +#define AR8216_REG_ATU_FUNC1 0x0054 +#define AR8216_ATU_ADDR3 BITS(0, 8) +#define AR8216_ATU_ADDR3_S 0 +#define AR8216_ATU_ADDR2 BITS(8, 8) +#define AR8216_ATU_ADDR2_S 8 +#define AR8216_ATU_ADDR1 BITS(16, 8) +#define AR8216_ATU_ADDR1_S 16 +#define AR8216_ATU_ADDR0 BITS(24, 8) +#define AR8216_ATU_ADDR0_S 24 + +#define AR8216_REG_ATU_FUNC2 0x0058 +#define AR8216_ATU_PORTS BITS(0, 6) +#define AR8216_ATU_PORT0 BIT(0) +#define AR8216_ATU_PORT1 BIT(1) +#define AR8216_ATU_PORT2 BIT(2) +#define AR8216_ATU_PORT3 BIT(3) +#define AR8216_ATU_PORT4 BIT(4) +#define AR8216_ATU_PORT5 BIT(5) +#define AR8216_ATU_STATUS BITS(16, 4) +#define AR8216_ATU_STATUS_S 16 + +#define AR8216_REG_ATU_CTRL 0x005C +#define AR8216_ATU_CTRL_AGE_EN BIT(17) +#define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) +#define AR8216_ATU_CTRL_AGE_TIME_S 0 +#define AR8236_ATU_CTRL_RES BIT(20) + +#define AR8216_REG_MIB_FUNC 0x0080 +#define AR8216_MIB_TIMER BITS(0, 16) +#define AR8216_MIB_AT_HALF_EN BIT(16) +#define AR8216_MIB_BUSY BIT(17) +#define AR8216_MIB_FUNC BITS(24, 3) +#define AR8216_MIB_FUNC_S 24 +#define AR8216_MIB_FUNC_NO_OP 0x0 +#define AR8216_MIB_FUNC_FLUSH 0x1 +#define AR8216_MIB_FUNC_CAPTURE 0x3 +#define AR8236_MIB_EN BIT(30) + +#define AR8216_REG_GLOBAL_CPUPORT 0x0078 +#define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4) +#define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4 + +#define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1)) +#define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000) +#define AR8216_PORT_STATUS_SPEED BITS(0,2) +#define AR8216_PORT_STATUS_SPEED_S 0 +#define AR8216_PORT_STATUS_TXMAC BIT(2) +#define AR8216_PORT_STATUS_RXMAC BIT(3) +#define AR8216_PORT_STATUS_TXFLOW BIT(4) +#define AR8216_PORT_STATUS_RXFLOW BIT(5) +#define AR8216_PORT_STATUS_DUPLEX BIT(6) +#define AR8216_PORT_STATUS_LINK_UP BIT(8) +#define AR8216_PORT_STATUS_LINK_AUTO BIT(9) +#define AR8216_PORT_STATUS_LINK_PAUSE BIT(10) + +#define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004) + +/* port forwarding state */ +#define AR8216_PORT_CTRL_STATE BITS(0, 3) +#define AR8216_PORT_CTRL_STATE_S 0 + +#define AR8216_PORT_CTRL_LEARN_LOCK BIT(7) + +/* egress 802.1q mode */ +#define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2) +#define AR8216_PORT_CTRL_VLAN_MODE_S 8 + +#define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10) +#define AR8216_PORT_CTRL_HEADER BIT(11) +#define AR8216_PORT_CTRL_MAC_LOOP BIT(12) +#define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13) +#define AR8216_PORT_CTRL_LEARN BIT(14) +#define AR8216_PORT_CTRL_MIRROR_TX BIT(16) +#define AR8216_PORT_CTRL_MIRROR_RX BIT(17) + +#define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008) + +#define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12) +#define AR8216_PORT_VLAN_DEFAULT_ID_S 0 + +#define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9) +#define AR8216_PORT_VLAN_DEST_PORTS_S 16 + +/* bit0 added to the priority field of egress frames */ +#define AR8216_PORT_VLAN_TX_PRIO BIT(27) + +/* port default priority */ +#define AR8216_PORT_VLAN_PRIORITY BITS(28, 2) +#define AR8216_PORT_VLAN_PRIORITY_S 28 + +/* ingress 802.1q mode */ +#define AR8216_PORT_VLAN_MODE BITS(30, 2) +#define AR8216_PORT_VLAN_MODE_S 30 + +#define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c) +#define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010) + +#define AR8216_STATS_RXBROAD 0x00 +#define AR8216_STATS_RXPAUSE 0x04 +#define AR8216_STATS_RXMULTI 0x08 +#define AR8216_STATS_RXFCSERR 0x0c +#define AR8216_STATS_RXALIGNERR 0x10 +#define AR8216_STATS_RXRUNT 0x14 +#define AR8216_STATS_RXFRAGMENT 0x18 +#define AR8216_STATS_RX64BYTE 0x1c +#define AR8216_STATS_RX128BYTE 0x20 +#define AR8216_STATS_RX256BYTE 0x24 +#define AR8216_STATS_RX512BYTE 0x28 +#define AR8216_STATS_RX1024BYTE 0x2c +#define AR8216_STATS_RXMAXBYTE 0x30 +#define AR8216_STATS_RXTOOLONG 0x34 +#define AR8216_STATS_RXGOODBYTE 0x38 +#define AR8216_STATS_RXBADBYTE 0x40 +#define AR8216_STATS_RXOVERFLOW 0x48 +#define AR8216_STATS_FILTERED 0x4c +#define AR8216_STATS_TXBROAD 0x50 +#define AR8216_STATS_TXPAUSE 0x54 +#define AR8216_STATS_TXMULTI 0x58 +#define AR8216_STATS_TXUNDERRUN 0x5c +#define AR8216_STATS_TX64BYTE 0x60 +#define AR8216_STATS_TX128BYTE 0x64 +#define AR8216_STATS_TX256BYTE 0x68 +#define AR8216_STATS_TX512BYTE 0x6c +#define AR8216_STATS_TX1024BYTE 0x70 +#define AR8216_STATS_TXMAXBYTE 0x74 +#define AR8216_STATS_TXOVERSIZE 0x78 +#define AR8216_STATS_TXBYTE 0x7c +#define AR8216_STATS_TXCOLLISION 0x84 +#define AR8216_STATS_TXABORTCOL 0x88 +#define AR8216_STATS_TXMULTICOL 0x8c +#define AR8216_STATS_TXSINGLECOL 0x90 +#define AR8216_STATS_TXEXCDEFER 0x94 +#define AR8216_STATS_TXDEFER 0x98 +#define AR8216_STATS_TXLATECOL 0x9c + +#define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008) +#define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12) +#define AR8236_PORT_VLAN_DEFAULT_ID_S 16 +#define AR8236_PORT_VLAN_PRIORITY BITS(29, 3) +#define AR8236_PORT_VLAN_PRIORITY_S 28 + +#define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c) +#define AR8236_PORT_VLAN2_MEMBER BITS(16, 7) +#define AR8236_PORT_VLAN2_MEMBER_S 16 +#define AR8236_PORT_VLAN2_TX_PRIO BIT(23) +#define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2) +#define AR8236_PORT_VLAN2_VLAN_MODE_S 30 + +#define AR8236_STATS_RXBROAD 0x00 +#define AR8236_STATS_RXPAUSE 0x04 +#define AR8236_STATS_RXMULTI 0x08 +#define AR8236_STATS_RXFCSERR 0x0c +#define AR8236_STATS_RXALIGNERR 0x10 +#define AR8236_STATS_RXRUNT 0x14 +#define AR8236_STATS_RXFRAGMENT 0x18 +#define AR8236_STATS_RX64BYTE 0x1c +#define AR8236_STATS_RX128BYTE 0x20 +#define AR8236_STATS_RX256BYTE 0x24 +#define AR8236_STATS_RX512BYTE 0x28 +#define AR8236_STATS_RX1024BYTE 0x2c +#define AR8236_STATS_RX1518BYTE 0x30 +#define AR8236_STATS_RXMAXBYTE 0x34 +#define AR8236_STATS_RXTOOLONG 0x38 +#define AR8236_STATS_RXGOODBYTE 0x3c +#define AR8236_STATS_RXBADBYTE 0x44 +#define AR8236_STATS_RXOVERFLOW 0x4c +#define AR8236_STATS_FILTERED 0x50 +#define AR8236_STATS_TXBROAD 0x54 +#define AR8236_STATS_TXPAUSE 0x58 +#define AR8236_STATS_TXMULTI 0x5c +#define AR8236_STATS_TXUNDERRUN 0x60 +#define AR8236_STATS_TX64BYTE 0x64 +#define AR8236_STATS_TX128BYTE 0x68 +#define AR8236_STATS_TX256BYTE 0x6c +#define AR8236_STATS_TX512BYTE 0x70 +#define AR8236_STATS_TX1024BYTE 0x74 +#define AR8236_STATS_TX1518BYTE 0x78 +#define AR8236_STATS_TXMAXBYTE 0x7c +#define AR8236_STATS_TXOVERSIZE 0x80 +#define AR8236_STATS_TXBYTE 0x84 +#define AR8236_STATS_TXCOLLISION 0x8c +#define AR8236_STATS_TXABORTCOL 0x90 +#define AR8236_STATS_TXMULTICOL 0x94 +#define AR8236_STATS_TXSINGLECOL 0x98 +#define AR8236_STATS_TXEXCDEFER 0x9c +#define AR8236_STATS_TXDEFER 0xa0 +#define AR8236_STATS_TXLATECOL 0xa4 + +#define AR8316_REG_POSTRIP 0x0008 +#define AR8316_POSTRIP_MAC0_GMII_EN BIT(0) +#define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1) +#define AR8316_POSTRIP_PHY4_GMII_EN BIT(2) +#define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3) +#define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4) +#define AR8316_POSTRIP_RTL_MODE BIT(5) +#define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6) +#define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7) +#define AR8316_POSTRIP_SERDES_EN BIT(8) +#define AR8316_POSTRIP_SEL_ANA_RST BIT(9) +#define AR8316_POSTRIP_GATE_25M_EN BIT(10) +#define AR8316_POSTRIP_SEL_CLK25M BIT(11) +#define AR8316_POSTRIP_HIB_PULSE_HW BIT(12) +#define AR8316_POSTRIP_DBG_MODE_I BIT(13) +#define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14) +#define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15) +#define AR8316_POSTRIP_POWER_DOWN_HW BIT(16) +#define AR8316_POSTRIP_LPW_STATE_EN BIT(17) +#define AR8316_POSTRIP_MAN_EN BIT(18) +#define AR8316_POSTRIP_PHY_PLL_ON BIT(19) +#define AR8316_POSTRIP_LPW_EXIT BIT(20) +#define AR8316_POSTRIP_TXDELAY_S0 BIT(21) +#define AR8316_POSTRIP_TXDELAY_S1 BIT(22) +#define AR8316_POSTRIP_RXDELAY_S0 BIT(23) +#define AR8316_POSTRIP_LED_OPEN_EN BIT(24) +#define AR8316_POSTRIP_SPI_EN BIT(25) +#define AR8316_POSTRIP_RXDELAY_S1 BIT(26) +#define AR8316_POSTRIP_POWER_ON_SEL BIT(31) + +/* port speed */ +enum { + AR8216_PORT_SPEED_10M = 0, + AR8216_PORT_SPEED_100M = 1, + AR8216_PORT_SPEED_1000M = 2, + AR8216_PORT_SPEED_ERR = 3, +}; + +/* ingress 802.1q mode */ +enum { + AR8216_IN_PORT_ONLY = 0, + AR8216_IN_PORT_FALLBACK = 1, + AR8216_IN_VLAN_ONLY = 2, + AR8216_IN_SECURE = 3 +}; + +/* egress 802.1q mode */ +enum { + AR8216_OUT_KEEP = 0, + AR8216_OUT_STRIP_VLAN = 1, + AR8216_OUT_ADD_VLAN = 2 +}; + +/* port forwarding state */ +enum { + AR8216_PORT_STATE_DISABLED = 0, + AR8216_PORT_STATE_BLOCK = 1, + AR8216_PORT_STATE_LISTEN = 2, + AR8216_PORT_STATE_LEARN = 3, + AR8216_PORT_STATE_FORWARD = 4 +}; + +enum { + AR8XXX_VER_AR8216 = 0x01, + AR8XXX_VER_AR8236 = 0x03, + AR8XXX_VER_AR8316 = 0x10, + AR8XXX_VER_AR8327 = 0x12, + AR8XXX_VER_AR8337 = 0x13, +}; + +#define AR8XXX_NUM_ARL_RECORDS 100 + +enum arl_op { + AR8XXX_ARL_INITIALIZE, + AR8XXX_ARL_GET_NEXT +}; + +struct arl_entry { + u8 port; + u8 mac[6]; +}; + +struct ar8xxx_priv; + +struct ar8xxx_mib_desc { + unsigned int size; + unsigned int offset; + const char *name; +}; + +struct ar8xxx_chip { + unsigned long caps; + bool config_at_probe; + bool mii_lo_first; + + /* parameters to calculate REG_PORT_STATS_BASE */ + unsigned reg_port_stats_start; + unsigned reg_port_stats_length; + + int (*hw_init)(struct ar8xxx_priv *priv); + void (*cleanup)(struct ar8xxx_priv *priv); + + const char *name; + int vlans; + int ports; + const struct switch_dev_ops *swops; + + void (*init_globals)(struct ar8xxx_priv *priv); + void (*init_port)(struct ar8xxx_priv *priv, int port); + void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members); + u32 (*read_port_status)(struct ar8xxx_priv *priv, int port); + u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port); + int (*atu_flush)(struct ar8xxx_priv *priv); + int (*atu_flush_port)(struct ar8xxx_priv *priv, int port); + void (*vtu_flush)(struct ar8xxx_priv *priv); + void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask); + void (*phy_fixup)(struct ar8xxx_priv *priv, int phy); + void (*set_mirror_regs)(struct ar8xxx_priv *priv); + void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a, + u32 *status, enum arl_op op); + int (*sw_hw_apply)(struct switch_dev *dev); + + const struct ar8xxx_mib_desc *mib_decs; + unsigned num_mibs; + unsigned mib_func; +}; + +struct ar8xxx_priv { + struct switch_dev dev; + struct mii_bus *mii_bus; + struct phy_device *phy; + + int (*get_port_link)(unsigned port); + + const struct net_device_ops *ndo_old; + struct net_device_ops ndo; + struct mutex reg_mutex; + u8 chip_ver; + u8 chip_rev; + const struct ar8xxx_chip *chip; + void *chip_data; + bool initialized; + bool port4_phy; + char buf[2048]; + struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS]; + char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256]; + bool link_up[AR8X16_MAX_PORTS]; + + bool init; + + struct mutex mib_lock; + struct delayed_work mib_work; + int mib_next_port; + u64 *mib_stats; + + struct list_head list; + unsigned int use_count; + + /* all fields below are cleared on reset */ + bool vlan; + u16 vlan_id[AR8X16_MAX_VLANS]; + u8 vlan_table[AR8X16_MAX_VLANS]; + u8 vlan_tagged; + u16 pvid[AR8X16_MAX_PORTS]; + + /* mirroring */ + bool mirror_rx; + bool mirror_tx; + int source_port; + int monitor_port; +}; + +u32 +ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum); +void +ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val); +u32 +ar8xxx_read(struct ar8xxx_priv *priv, int reg); +void +ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val); +u32 +ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val); + +void +ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr, + u16 dbg_addr, u16 dbg_data); +void +ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data); +u16 +ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr); +void +ar8xxx_phy_init(struct ar8xxx_priv *priv); +int +ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_reset_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan); +int +ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan); +int +ar8xxx_sw_hw_apply(struct switch_dev *dev); +int +ar8xxx_sw_reset_switch(struct switch_dev *dev); +int +ar8xxx_sw_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link); +int +ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_port_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_get_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int +ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val); + +static inline struct ar8xxx_priv * +swdev_to_ar8xxx(struct switch_dev *swdev) +{ + return container_of(swdev, struct ar8xxx_priv, dev); +} + +static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv) +{ + return priv->chip->caps & AR8XXX_CAP_GIGE; +} + +static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv) +{ + return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS; +} + +static inline bool chip_is_ar8216(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8216; +} + +static inline bool chip_is_ar8236(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8236; +} + +static inline bool chip_is_ar8316(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8316; +} + +static inline bool chip_is_ar8327(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8327; +} + +static inline bool chip_is_ar8337(struct ar8xxx_priv *priv) +{ + return priv->chip_ver == AR8XXX_VER_AR8337; +} + +static inline void +ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val) +{ + ar8xxx_rmw(priv, reg, 0, val); +} + +static inline void +ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val) +{ + ar8xxx_rmw(priv, reg, val, 0); +} + +static inline void +split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) +{ + regaddr >>= 1; + *r1 = regaddr & 0x1e; + + regaddr >>= 5; + *r2 = regaddr & 0x7; + + regaddr >>= 3; + *page = regaddr & 0x1ff; +} + +static inline void +wait_for_page_switch(void) +{ + udelay(5); +} + +#endif diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.c b/target/linux/generic/files/drivers/net/phy/ar8327.c new file mode 100644 index 0000000..1802b9e --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/ar8327.c @@ -0,0 +1,1268 @@ +/* + * ar8327.c: AR8216 switch driver + * + * Copyright (C) 2009 Felix Fietkau + * Copyright (C) 2011-2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ar8216.h" +#include "ar8327.h" + +extern const struct ar8xxx_mib_desc ar8236_mibs[39]; +extern const struct switch_attr ar8xxx_sw_attr_vlan[1]; + +static u32 +ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg) +{ + u32 t; + + if (!cfg) + return 0; + + t = 0; + switch (cfg->mode) { + case AR8327_PAD_NC: + break; + + case AR8327_PAD_MAC2MAC_MII: + t = AR8327_PAD_MAC_MII_EN; + if (cfg->rxclk_sel) + t |= AR8327_PAD_MAC_MII_RXCLK_SEL; + if (cfg->txclk_sel) + t |= AR8327_PAD_MAC_MII_TXCLK_SEL; + break; + + case AR8327_PAD_MAC2MAC_GMII: + t = AR8327_PAD_MAC_GMII_EN; + if (cfg->rxclk_sel) + t |= AR8327_PAD_MAC_GMII_RXCLK_SEL; + if (cfg->txclk_sel) + t |= AR8327_PAD_MAC_GMII_TXCLK_SEL; + break; + + case AR8327_PAD_MAC_SGMII: + t = AR8327_PAD_SGMII_EN; + + /* + * WAR for the QUalcomm Atheros AP136 board. + * It seems that RGMII TX/RX delay settings needs to be + * applied for SGMII mode as well, The ethernet is not + * reliable without this. + */ + t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; + t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; + if (cfg->rxclk_delay_en) + t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; + if (cfg->txclk_delay_en) + t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; + + if (cfg->sgmii_delay_en) + t |= AR8327_PAD_SGMII_DELAY_EN; + + break; + + case AR8327_PAD_MAC2PHY_MII: + t = AR8327_PAD_PHY_MII_EN; + if (cfg->rxclk_sel) + t |= AR8327_PAD_PHY_MII_RXCLK_SEL; + if (cfg->txclk_sel) + t |= AR8327_PAD_PHY_MII_TXCLK_SEL; + break; + + case AR8327_PAD_MAC2PHY_GMII: + t = AR8327_PAD_PHY_GMII_EN; + if (cfg->pipe_rxclk_sel) + t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL; + if (cfg->rxclk_sel) + t |= AR8327_PAD_PHY_GMII_RXCLK_SEL; + if (cfg->txclk_sel) + t |= AR8327_PAD_PHY_GMII_TXCLK_SEL; + break; + + case AR8327_PAD_MAC_RGMII: + t = AR8327_PAD_RGMII_EN; + t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; + t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; + if (cfg->rxclk_delay_en) + t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; + if (cfg->txclk_delay_en) + t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; + break; + + case AR8327_PAD_PHY_GMII: + t = AR8327_PAD_PHYX_GMII_EN; + break; + + case AR8327_PAD_PHY_RGMII: + t = AR8327_PAD_PHYX_RGMII_EN; + break; + + case AR8327_PAD_PHY_MII: + t = AR8327_PAD_PHYX_MII_EN; + break; + } + + if (cfg->mac06_exchange_en) + t |= AR8337_PAD_MAC06_EXCHANGE_EN; + + return t; +} + +static void +ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy) +{ + switch (priv->chip_rev) { + case 1: + /* For 100M waveform */ + ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea); + /* Turn on Gigabit clock */ + ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0); + break; + + case 2: + ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c); + ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0); + /* fallthrough */ + case 4: + ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d); + ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f); + + ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860); + ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46); + ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000); + break; + } +} + +static u32 +ar8327_get_port_init_status(struct ar8327_port_cfg *cfg) +{ + u32 t; + + if (!cfg->force_link) + return AR8216_PORT_STATUS_LINK_AUTO; + + t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC; + t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0; + t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0; + t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0; + + switch (cfg->speed) { + case AR8327_PORT_SPEED_10: + t |= AR8216_PORT_SPEED_10M; + break; + case AR8327_PORT_SPEED_100: + t |= AR8216_PORT_SPEED_100M; + break; + case AR8327_PORT_SPEED_1000: + t |= AR8216_PORT_SPEED_1000M; + break; + } + + return t; +} + +#define AR8327_LED_ENTRY(_num, _reg, _shift) \ + [_num] = { .reg = (_reg), .shift = (_shift) } + +static const struct ar8327_led_entry +ar8327_led_map[AR8327_NUM_LEDS] = { + AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14), + AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14), + AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14), + + AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8), + AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10), + AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12), + + AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14), + AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16), + AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18), + + AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20), + AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22), + AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24), + + AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30), + AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30), + AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30), +}; + +static void +ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num, + enum ar8327_led_pattern pattern) +{ + const struct ar8327_led_entry *entry; + + entry = &ar8327_led_map[led_num]; + ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg), + (3 << entry->shift), pattern << entry->shift); +} + +static void +ar8327_led_work_func(struct work_struct *work) +{ + struct ar8327_led *aled; + u8 pattern; + + aled = container_of(work, struct ar8327_led, led_work); + + spin_lock(&aled->lock); + pattern = aled->pattern; + spin_unlock(&aled->lock); + + ar8327_set_led_pattern(aled->sw_priv, aled->led_num, + pattern); +} + +static void +ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern) +{ + if (aled->pattern == pattern) + return; + + aled->pattern = pattern; + schedule_work(&aled->led_work); +} + +static inline struct ar8327_led * +led_cdev_to_ar8327_led(struct led_classdev *led_cdev) +{ + return container_of(led_cdev, struct ar8327_led, cdev); +} + +static int +ar8327_led_blink_set(struct led_classdev *led_cdev, + unsigned long *delay_on, + unsigned long *delay_off) +{ + struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev); + + if (*delay_on == 0 && *delay_off == 0) { + *delay_on = 125; + *delay_off = 125; + } + + if (*delay_on != 125 || *delay_off != 125) { + /* + * The hardware only supports blinking at 4Hz. Fall back + * to software implementation in other cases. + */ + return -EINVAL; + } + + spin_lock(&aled->lock); + + aled->enable_hw_mode = false; + ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK); + + spin_unlock(&aled->lock); + + return 0; +} + +static void +ar8327_led_set_brightness(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev); + u8 pattern; + bool active; + + active = (brightness != LED_OFF); + active ^= aled->active_low; + + pattern = (active) ? AR8327_LED_PATTERN_ON : + AR8327_LED_PATTERN_OFF; + + spin_lock(&aled->lock); + + aled->enable_hw_mode = false; + ar8327_led_schedule_change(aled, pattern); + + spin_unlock(&aled->lock); +} + +static ssize_t +ar8327_led_enable_hw_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev); + ssize_t ret = 0; + + spin_lock(&aled->lock); + ret += sprintf(buf, "%d\n", aled->enable_hw_mode); + spin_unlock(&aled->lock); + + return ret; +} + +static ssize_t +ar8327_led_enable_hw_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev); + u8 pattern; + u8 value; + int ret; + + ret = kstrtou8(buf, 10, &value); + if (ret < 0) + return -EINVAL; + + spin_lock(&aled->lock); + + aled->enable_hw_mode = !!value; + if (aled->enable_hw_mode) + pattern = AR8327_LED_PATTERN_RULE; + else + pattern = AR8327_LED_PATTERN_OFF; + + ar8327_led_schedule_change(aled, pattern); + + spin_unlock(&aled->lock); + + return size; +} + +static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR, + ar8327_led_enable_hw_mode_show, + ar8327_led_enable_hw_mode_store); + +static int +ar8327_led_register(struct ar8327_led *aled) +{ + int ret; + + ret = led_classdev_register(NULL, &aled->cdev); + if (ret < 0) + return ret; + + if (aled->mode == AR8327_LED_MODE_HW) { + ret = device_create_file(aled->cdev.dev, + &dev_attr_enable_hw_mode); + if (ret) + goto err_unregister; + } + + return 0; + +err_unregister: + led_classdev_unregister(&aled->cdev); + return ret; +} + +static void +ar8327_led_unregister(struct ar8327_led *aled) +{ + if (aled->mode == AR8327_LED_MODE_HW) + device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode); + + led_classdev_unregister(&aled->cdev); + cancel_work_sync(&aled->led_work); +} + +static int +ar8327_led_create(struct ar8xxx_priv *priv, + const struct ar8327_led_info *led_info) +{ + struct ar8327_data *data = priv->chip_data; + struct ar8327_led *aled; + int ret; + + if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS)) + return 0; + + if (!led_info->name) + return -EINVAL; + + if (led_info->led_num >= AR8327_NUM_LEDS) + return -EINVAL; + + aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1, + GFP_KERNEL); + if (!aled) + return -ENOMEM; + + aled->sw_priv = priv; + aled->led_num = led_info->led_num; + aled->active_low = led_info->active_low; + aled->mode = led_info->mode; + + if (aled->mode == AR8327_LED_MODE_HW) + aled->enable_hw_mode = true; + + aled->name = (char *)(aled + 1); + strcpy(aled->name, led_info->name); + + aled->cdev.name = aled->name; + aled->cdev.brightness_set = ar8327_led_set_brightness; + aled->cdev.blink_set = ar8327_led_blink_set; + aled->cdev.default_trigger = led_info->default_trigger; + + spin_lock_init(&aled->lock); + mutex_init(&aled->mutex); + INIT_WORK(&aled->led_work, ar8327_led_work_func); + + ret = ar8327_led_register(aled); + if (ret) + goto err_free; + + data->leds[data->num_leds++] = aled; + + return 0; + +err_free: + kfree(aled); + return ret; +} + +static void +ar8327_led_destroy(struct ar8327_led *aled) +{ + ar8327_led_unregister(aled); + kfree(aled); +} + +static void +ar8327_leds_init(struct ar8xxx_priv *priv) +{ + struct ar8327_data *data = priv->chip_data; + unsigned i; + + if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS)) + return; + + for (i = 0; i < data->num_leds; i++) { + struct ar8327_led *aled; + + aled = data->leds[i]; + + if (aled->enable_hw_mode) + aled->pattern = AR8327_LED_PATTERN_RULE; + else + aled->pattern = AR8327_LED_PATTERN_OFF; + + ar8327_set_led_pattern(priv, aled->led_num, aled->pattern); + } +} + +static void +ar8327_leds_cleanup(struct ar8xxx_priv *priv) +{ + struct ar8327_data *data = priv->chip_data; + unsigned i; + + if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS)) + return; + + for (i = 0; i < data->num_leds; i++) { + struct ar8327_led *aled; + + aled = data->leds[i]; + ar8327_led_destroy(aled); + } + + kfree(data->leds); +} + +static int +ar8327_hw_config_pdata(struct ar8xxx_priv *priv, + struct ar8327_platform_data *pdata) +{ + struct ar8327_led_cfg *led_cfg; + struct ar8327_data *data = priv->chip_data; + u32 pos, new_pos; + u32 t; + + if (!pdata) + return -EINVAL; + + priv->get_port_link = pdata->get_port_link; + + data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg); + data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg); + + t = ar8327_get_pad_cfg(pdata->pad0_cfg); + ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t); + t = ar8327_get_pad_cfg(pdata->pad5_cfg); + ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t); + t = ar8327_get_pad_cfg(pdata->pad6_cfg); + ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t); + + pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP); + new_pos = pos; + + led_cfg = pdata->led_cfg; + if (led_cfg) { + if (led_cfg->open_drain) + new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN; + else + new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN; + + ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0); + ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1); + ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2); + ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3); + + if (new_pos != pos) + new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL; + } + + if (pdata->sgmii_cfg) { + t = pdata->sgmii_cfg->sgmii_ctrl; + if (priv->chip_rev == 1) + t |= AR8327_SGMII_CTRL_EN_PLL | + AR8327_SGMII_CTRL_EN_RX | + AR8327_SGMII_CTRL_EN_TX; + else + t &= ~(AR8327_SGMII_CTRL_EN_PLL | + AR8327_SGMII_CTRL_EN_RX | + AR8327_SGMII_CTRL_EN_TX); + + ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t); + + if (pdata->sgmii_cfg->serdes_aen) + new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN; + else + new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN; + } + + ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos); + + if (pdata->leds && pdata->num_leds) { + int i; + + data->leds = kzalloc(pdata->num_leds * sizeof(void *), + GFP_KERNEL); + if (!data->leds) + return -ENOMEM; + + for (i = 0; i < pdata->num_leds; i++) + ar8327_led_create(priv, &pdata->leds[i]); + } + + return 0; +} + +#ifdef CONFIG_OF +static int +ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np) +{ + struct ar8327_data *data = priv->chip_data; + const __be32 *paddr; + int len; + int i; + + paddr = of_get_property(np, "qca,ar8327-initvals", &len); + if (!paddr || len < (2 * sizeof(*paddr))) + return -EINVAL; + + len /= sizeof(*paddr); + + for (i = 0; i < len - 1; i += 2) { + u32 reg; + u32 val; + + reg = be32_to_cpup(paddr + i); + val = be32_to_cpup(paddr + i + 1); + + switch (reg) { + case AR8327_REG_PORT_STATUS(0): + data->port0_status = val; + break; + case AR8327_REG_PORT_STATUS(6): + data->port6_status = val; + break; + default: + ar8xxx_write(priv, reg, val); + break; + } + } + + return 0; +} +#else +static inline int +ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np) +{ + return -EINVAL; +} +#endif + +static int +ar8327_hw_init(struct ar8xxx_priv *priv) +{ + int ret; + + priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL); + if (!priv->chip_data) + return -ENOMEM; + + if (priv->phy->dev.of_node) + ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node); + else + ret = ar8327_hw_config_pdata(priv, + priv->phy->dev.platform_data); + + if (ret) + return ret; + + ar8327_leds_init(priv); + + ar8xxx_phy_init(priv); + + return 0; +} + +static void +ar8327_cleanup(struct ar8xxx_priv *priv) +{ + ar8327_leds_cleanup(priv); +} + +static void +ar8327_init_globals(struct ar8xxx_priv *priv) +{ + struct ar8327_data *data = priv->chip_data; + u32 t; + int i; + + /* enable CPU port and disable mirror port */ + t = AR8327_FWD_CTRL0_CPU_PORT_EN | + AR8327_FWD_CTRL0_MIRROR_PORT; + ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t); + + /* forward multicast and broadcast frames to CPU */ + t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) | + (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) | + (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S); + ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t); + + /* enable jumbo frames */ + ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE, + AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2); + + /* Enable MIB counters */ + ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN, + AR8327_MODULE_EN_MIB); + + /* Disable EEE on all phy's due to stability issues */ + for (i = 0; i < AR8XXX_NUM_PHYS; i++) + data->eee[i] = false; +} + +static void +ar8327_init_port(struct ar8xxx_priv *priv, int port) +{ + struct ar8327_data *data = priv->chip_data; + u32 t; + + if (port == AR8216_PORT_CPU) + t = data->port0_status; + else if (port == 6) + t = data->port6_status; + else + t = AR8216_PORT_STATUS_LINK_AUTO; + + ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t); + ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0); + + t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S; + t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S; + ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t); + + t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S; + ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t); + + t = AR8327_PORT_LOOKUP_LEARN; + t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; + ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t); +} + +static u32 +ar8327_read_port_status(struct ar8xxx_priv *priv, int port) +{ + u32 t; + + t = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port)); + /* map the flow control autoneg result bits to the flow control bits + * used in forced mode to allow ar8216_read_port_link detect + * flow control properly if autoneg is used + */ + if (t & AR8216_PORT_STATUS_LINK_UP && + t & AR8216_PORT_STATUS_LINK_AUTO) { + t &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW); + if (t & AR8327_PORT_STATUS_TXFLOW_AUTO) + t |= AR8216_PORT_STATUS_TXFLOW; + if (t & AR8327_PORT_STATUS_RXFLOW_AUTO) + t |= AR8216_PORT_STATUS_RXFLOW; + } + + return t; +} + +static u32 +ar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port) +{ + int phy; + u16 t; + + if (port >= priv->dev.ports) + return 0; + + if (port == 0 || port == 6) + return 0; + + phy = port - 1; + + /* EEE Ability Auto-negotiation Result */ + ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x8000); + t = ar8xxx_phy_mmd_read(priv, phy, 0x4007); + + return mmd_eee_adv_to_ethtool_adv_t(t); +} + +static int +ar8327_atu_flush(struct ar8xxx_priv *priv) +{ + int ret; + + ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC, + AR8327_ATU_FUNC_BUSY, 0); + if (!ret) + ar8xxx_write(priv, AR8327_REG_ATU_FUNC, + AR8327_ATU_FUNC_OP_FLUSH | + AR8327_ATU_FUNC_BUSY); + + return ret; +} + +static int +ar8327_atu_flush_port(struct ar8xxx_priv *priv, int port) +{ + u32 t; + int ret; + + ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC, + AR8327_ATU_FUNC_BUSY, 0); + if (!ret) { + t = (port << AR8327_ATU_PORT_NUM_S); + t |= AR8327_ATU_FUNC_OP_FLUSH_PORT; + t |= AR8327_ATU_FUNC_BUSY; + ar8xxx_write(priv, AR8327_REG_ATU_FUNC, t); + } + + return ret; +} + +static void +ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val) +{ + if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1, + AR8327_VTU_FUNC1_BUSY, 0)) + return; + + if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD) + ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val); + + op |= AR8327_VTU_FUNC1_BUSY; + ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op); +} + +static void +ar8327_vtu_flush(struct ar8xxx_priv *priv) +{ + ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0); +} + +static void +ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask) +{ + u32 op; + u32 val; + int i; + + op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S); + val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL; + for (i = 0; i < AR8327_NUM_PORTS; i++) { + u32 mode; + + if ((port_mask & BIT(i)) == 0) + mode = AR8327_VTU_FUNC0_EG_MODE_NOT; + else if (priv->vlan == 0) + mode = AR8327_VTU_FUNC0_EG_MODE_KEEP; + else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid)) + mode = AR8327_VTU_FUNC0_EG_MODE_TAG; + else + mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG; + + val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i); + } + ar8327_vtu_op(priv, op, val); +} + +static void +ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members) +{ + u32 t; + u32 egress, ingress; + u32 pvid = priv->vlan_id[priv->pvid[port]]; + + if (priv->vlan) { + egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD; + ingress = AR8216_IN_SECURE; + } else { + egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH; + ingress = AR8216_IN_PORT_ONLY; + } + + t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S; + t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S; + ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t); + + t = AR8327_PORT_VLAN1_PORT_VLAN_PROP; + t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S; + ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t); + + t = members; + t |= AR8327_PORT_LOOKUP_LEARN; + t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S; + t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; + ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t); +} + +static int +ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + u8 ports = priv->vlan_table[val->port_vlan]; + int i; + + val->len = 0; + for (i = 0; i < dev->ports; i++) { + struct switch_port *p; + + if (!(ports & (1 << i))) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan)) + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); + else + p->flags = 0; + } + return 0; +} + +static int +ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + u8 *vt = &priv->vlan_table[val->port_vlan]; + int i; + + *vt = 0; + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) { + if (val->port_vlan == priv->pvid[p->id]) { + priv->vlan_tagged |= (1 << p->id); + } + } else { + priv->vlan_tagged &= ~(1 << p->id); + priv->pvid[p->id] = val->port_vlan; + } + + *vt |= 1 << p->id; + } + return 0; +} + +static void +ar8327_set_mirror_regs(struct ar8xxx_priv *priv) +{ + int port; + + /* reset all mirror registers */ + ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0, + AR8327_FWD_CTRL0_MIRROR_PORT, + (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S)); + for (port = 0; port < AR8327_NUM_PORTS; port++) { + ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port), + AR8327_PORT_LOOKUP_ING_MIRROR_EN); + + ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port), + AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN); + } + + /* now enable mirroring if necessary */ + if (priv->source_port >= AR8327_NUM_PORTS || + priv->monitor_port >= AR8327_NUM_PORTS || + priv->source_port == priv->monitor_port) { + return; + } + + ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0, + AR8327_FWD_CTRL0_MIRROR_PORT, + (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S)); + + if (priv->mirror_rx) + ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port), + AR8327_PORT_LOOKUP_ING_MIRROR_EN); + + if (priv->mirror_tx) + ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port), + AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN); +} + +static int +ar8327_sw_set_eee(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + struct ar8327_data *data = priv->chip_data; + int port = val->port_vlan; + int phy; + + if (port >= dev->ports) + return -EINVAL; + if (port == 0 || port == 6) + return -EOPNOTSUPP; + + phy = port - 1; + + data->eee[phy] = !!(val->value.i); + + return 0; +} + +static int +ar8327_sw_get_eee(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + const struct ar8327_data *data = priv->chip_data; + int port = val->port_vlan; + int phy; + + if (port >= dev->ports) + return -EINVAL; + if (port == 0 || port == 6) + return -EOPNOTSUPP; + + phy = port - 1; + + val->value.i = data->eee[phy]; + + return 0; +} + +static void +ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1) +{ + int timeout = 20; + + while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout) + udelay(10); + + if (!timeout) + pr_err("ar8327: timeout waiting for atu to become ready\n"); +} + +static void ar8327_get_arl_entry(struct ar8xxx_priv *priv, + struct arl_entry *a, u32 *status, enum arl_op op) +{ + struct mii_bus *bus = priv->mii_bus; + u16 r2, page; + u16 r1_data0, r1_data1, r1_data2, r1_func; + u32 t, val0, val1, val2; + int i; + + split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page); + r2 |= 0x10; + + r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e; + r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e; + r1_func = (AR8327_REG_ATU_FUNC >> 1) & 0x1e; + + switch (op) { + case AR8XXX_ARL_INITIALIZE: + /* all ATU registers are on the same page + * therefore set page only once + */ + bus->write(bus, 0x18, 0, page); + wait_for_page_switch(); + + ar8327_wait_atu_ready(priv, r2, r1_func); + + ar8xxx_mii_write32(priv, r2, r1_data0, 0); + ar8xxx_mii_write32(priv, r2, r1_data1, 0); + ar8xxx_mii_write32(priv, r2, r1_data2, 0); + break; + case AR8XXX_ARL_GET_NEXT: + ar8xxx_mii_write32(priv, r2, r1_func, + AR8327_ATU_FUNC_OP_GET_NEXT | + AR8327_ATU_FUNC_BUSY); + ar8327_wait_atu_ready(priv, r2, r1_func); + + val0 = ar8xxx_mii_read32(priv, r2, r1_data0); + val1 = ar8xxx_mii_read32(priv, r2, r1_data1); + val2 = ar8xxx_mii_read32(priv, r2, r1_data2); + + *status = val2 & AR8327_ATU_STATUS; + if (!*status) + break; + + i = 0; + t = AR8327_ATU_PORT0; + while (!(val1 & t) && ++i < AR8327_NUM_PORTS) + t <<= 1; + + a->port = i; + a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S; + a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S; + a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S; + a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S; + a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S; + a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S; + break; + } +} + +static int +ar8327_sw_hw_apply(struct switch_dev *dev) +{ + struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); + const struct ar8327_data *data = priv->chip_data; + int ret, i; + + ret = ar8xxx_sw_hw_apply(dev); + if (ret) + return ret; + + for (i=0; i < AR8XXX_NUM_PHYS; i++) { + if (data->eee[i]) + ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL, + AR8327_EEE_CTRL_DISABLE_PHY(i)); + else + ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL, + AR8327_EEE_CTRL_DISABLE_PHY(i)); + } + + return 0; +} + +static const struct switch_attr ar8327_sw_attr_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = ar8xxx_sw_set_vlan, + .get = ar8xxx_sw_get_vlan, + .max = 1 + }, + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mibs", + .description = "Reset all MIB counters", + .set = ar8xxx_sw_set_reset_mibs, + }, + { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_rx", + .description = "Enable mirroring of RX packets", + .set = ar8xxx_sw_set_mirror_rx_enable, + .get = ar8xxx_sw_get_mirror_rx_enable, + .max = 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_tx", + .description = "Enable mirroring of TX packets", + .set = ar8xxx_sw_set_mirror_tx_enable, + .get = ar8xxx_sw_get_mirror_tx_enable, + .max = 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "mirror_monitor_port", + .description = "Mirror monitor port", + .set = ar8xxx_sw_set_mirror_monitor_port, + .get = ar8xxx_sw_get_mirror_monitor_port, + .max = AR8327_NUM_PORTS - 1 + }, + { + .type = SWITCH_TYPE_INT, + .name = "mirror_source_port", + .description = "Mirror source port", + .set = ar8xxx_sw_set_mirror_source_port, + .get = ar8xxx_sw_get_mirror_source_port, + .max = AR8327_NUM_PORTS - 1 + }, + { + .type = SWITCH_TYPE_STRING, + .name = "arl_table", + .description = "Get ARL table", + .set = NULL, + .get = ar8xxx_sw_get_arl_table, + }, + { + .type = SWITCH_TYPE_NOVAL, + .name = "flush_arl_table", + .description = "Flush ARL table", + .set = ar8xxx_sw_set_flush_arl_table, + }, +}; + +static const struct switch_attr ar8327_sw_attr_port[] = { + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mib", + .description = "Reset single port MIB counters", + .set = ar8xxx_sw_set_port_reset_mib, + }, + { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get port's MIB counters", + .set = NULL, + .get = ar8xxx_sw_get_port_mib, + }, + { + .type = SWITCH_TYPE_INT, + .name = "enable_eee", + .description = "Enable EEE PHY sleep mode", + .set = ar8327_sw_set_eee, + .get = ar8327_sw_get_eee, + .max = 1, + }, + { + .type = SWITCH_TYPE_NOVAL, + .name = "flush_arl_table", + .description = "Flush port's ARL table entries", + .set = ar8xxx_sw_set_flush_port_arl_table, + }, +}; + +static const struct switch_dev_ops ar8327_sw_ops = { + .attr_global = { + .attr = ar8327_sw_attr_globals, + .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals), + }, + .attr_port = { + .attr = ar8327_sw_attr_port, + .n_attr = ARRAY_SIZE(ar8327_sw_attr_port), + }, + .attr_vlan = { + .attr = ar8xxx_sw_attr_vlan, + .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan), + }, + .get_port_pvid = ar8xxx_sw_get_pvid, + .set_port_pvid = ar8xxx_sw_set_pvid, + .get_vlan_ports = ar8327_sw_get_ports, + .set_vlan_ports = ar8327_sw_set_ports, + .apply_config = ar8327_sw_hw_apply, + .reset_switch = ar8xxx_sw_reset_switch, + .get_port_link = ar8xxx_sw_get_port_link, +}; + +const struct ar8xxx_chip ar8327_chip = { + .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS, + .config_at_probe = true, + .mii_lo_first = true, + + .name = "Atheros AR8327", + .ports = AR8327_NUM_PORTS, + .vlans = AR8X16_MAX_VLANS, + .swops = &ar8327_sw_ops, + + .reg_port_stats_start = 0x1000, + .reg_port_stats_length = 0x100, + + .hw_init = ar8327_hw_init, + .cleanup = ar8327_cleanup, + .init_globals = ar8327_init_globals, + .init_port = ar8327_init_port, + .setup_port = ar8327_setup_port, + .read_port_status = ar8327_read_port_status, + .read_port_eee_status = ar8327_read_port_eee_status, + .atu_flush = ar8327_atu_flush, + .atu_flush_port = ar8327_atu_flush_port, + .vtu_flush = ar8327_vtu_flush, + .vtu_load_vlan = ar8327_vtu_load_vlan, + .phy_fixup = ar8327_phy_fixup, + .set_mirror_regs = ar8327_set_mirror_regs, + .get_arl_entry = ar8327_get_arl_entry, + .sw_hw_apply = ar8327_sw_hw_apply, + + .num_mibs = ARRAY_SIZE(ar8236_mibs), + .mib_decs = ar8236_mibs, + .mib_func = AR8327_REG_MIB_FUNC +}; + +const struct ar8xxx_chip ar8337_chip = { + .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS, + .config_at_probe = true, + .mii_lo_first = true, + + .name = "Atheros AR8337", + .ports = AR8327_NUM_PORTS, + .vlans = AR8X16_MAX_VLANS, + .swops = &ar8327_sw_ops, + + .reg_port_stats_start = 0x1000, + .reg_port_stats_length = 0x100, + + .hw_init = ar8327_hw_init, + .cleanup = ar8327_cleanup, + .init_globals = ar8327_init_globals, + .init_port = ar8327_init_port, + .setup_port = ar8327_setup_port, + .read_port_status = ar8327_read_port_status, + .read_port_eee_status = ar8327_read_port_eee_status, + .atu_flush = ar8327_atu_flush, + .atu_flush_port = ar8327_atu_flush_port, + .vtu_flush = ar8327_vtu_flush, + .vtu_load_vlan = ar8327_vtu_load_vlan, + .phy_fixup = ar8327_phy_fixup, + .set_mirror_regs = ar8327_set_mirror_regs, + .get_arl_entry = ar8327_get_arl_entry, + .sw_hw_apply = ar8327_sw_hw_apply, + + .num_mibs = ARRAY_SIZE(ar8236_mibs), + .mib_decs = ar8236_mibs, + .mib_func = AR8327_REG_MIB_FUNC +}; + diff --git a/target/linux/generic/files/drivers/net/phy/ar8327.h b/target/linux/generic/files/drivers/net/phy/ar8327.h new file mode 100644 index 0000000..8d1fb3b --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/ar8327.h @@ -0,0 +1,252 @@ +/* + * ar8327.h: AR8216 switch driver + * + * Copyright (C) 2009 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AR8327_H +#define __AR8327_H + +#define AR8327_NUM_PORTS 7 +#define AR8327_NUM_LEDS 15 +#define AR8327_PORTS_ALL 0x7f +#define AR8327_NUM_LED_CTRL_REGS 4 + +#define AR8327_REG_MASK 0x000 + +#define AR8327_REG_PAD0_MODE 0x004 +#define AR8327_REG_PAD5_MODE 0x008 +#define AR8327_REG_PAD6_MODE 0x00c +#define AR8327_PAD_MAC_MII_RXCLK_SEL BIT(0) +#define AR8327_PAD_MAC_MII_TXCLK_SEL BIT(1) +#define AR8327_PAD_MAC_MII_EN BIT(2) +#define AR8327_PAD_MAC_GMII_RXCLK_SEL BIT(4) +#define AR8327_PAD_MAC_GMII_TXCLK_SEL BIT(5) +#define AR8327_PAD_MAC_GMII_EN BIT(6) +#define AR8327_PAD_SGMII_EN BIT(7) +#define AR8327_PAD_PHY_MII_RXCLK_SEL BIT(8) +#define AR8327_PAD_PHY_MII_TXCLK_SEL BIT(9) +#define AR8327_PAD_PHY_MII_EN BIT(10) +#define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL BIT(11) +#define AR8327_PAD_PHY_GMII_RXCLK_SEL BIT(12) +#define AR8327_PAD_PHY_GMII_TXCLK_SEL BIT(13) +#define AR8327_PAD_PHY_GMII_EN BIT(14) +#define AR8327_PAD_PHYX_GMII_EN BIT(16) +#define AR8327_PAD_PHYX_RGMII_EN BIT(17) +#define AR8327_PAD_PHYX_MII_EN BIT(18) +#define AR8327_PAD_SGMII_DELAY_EN BIT(19) +#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) +#define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 +#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) +#define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 +#define AR8327_PAD_RGMII_RXCLK_DELAY_EN BIT(24) +#define AR8327_PAD_RGMII_TXCLK_DELAY_EN BIT(25) +#define AR8327_PAD_RGMII_EN BIT(26) + +#define AR8327_REG_POWER_ON_STRIP 0x010 +#define AR8327_POWER_ON_STRIP_POWER_ON_SEL BIT(31) +#define AR8327_POWER_ON_STRIP_LED_OPEN_EN BIT(24) +#define AR8327_POWER_ON_STRIP_SERDES_AEN BIT(7) + +#define AR8327_REG_INT_STATUS0 0x020 +#define AR8327_INT0_VT_DONE BIT(20) + +#define AR8327_REG_INT_STATUS1 0x024 +#define AR8327_REG_INT_MASK0 0x028 +#define AR8327_REG_INT_MASK1 0x02c + +#define AR8327_REG_MODULE_EN 0x030 +#define AR8327_MODULE_EN_MIB BIT(0) + +#define AR8327_REG_MIB_FUNC 0x034 +#define AR8327_MIB_CPU_KEEP BIT(20) + +#define AR8327_REG_SERVICE_TAG 0x048 +#define AR8327_REG_LED_CTRL(_i) (0x050 + (_i) * 4) +#define AR8327_REG_LED_CTRL0 0x050 +#define AR8327_REG_LED_CTRL1 0x054 +#define AR8327_REG_LED_CTRL2 0x058 +#define AR8327_REG_LED_CTRL3 0x05c +#define AR8327_REG_MAC_ADDR0 0x060 +#define AR8327_REG_MAC_ADDR1 0x064 + +#define AR8327_REG_MAX_FRAME_SIZE 0x078 +#define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) + +#define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) +#define AR8327_PORT_STATUS_TXFLOW_AUTO BIT(10) +#define AR8327_PORT_STATUS_RXFLOW_AUTO BIT(11) + +#define AR8327_REG_HEADER_CTRL 0x098 +#define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) + +#define AR8327_REG_SGMII_CTRL 0x0e0 +#define AR8327_SGMII_CTRL_EN_PLL BIT(1) +#define AR8327_SGMII_CTRL_EN_RX BIT(2) +#define AR8327_SGMII_CTRL_EN_TX BIT(3) + +#define AR8327_REG_EEE_CTRL 0x100 +#define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) + +#define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) +#define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) +#define AR8327_PORT_VLAN0_DEF_SVID_S 0 +#define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) +#define AR8327_PORT_VLAN0_DEF_CVID_S 16 + +#define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) +#define AR8327_PORT_VLAN1_PORT_VLAN_PROP BIT(6) +#define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) +#define AR8327_PORT_VLAN1_OUT_MODE_S 12 +#define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 +#define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 +#define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 +#define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 + +#define AR8327_REG_ATU_DATA0 0x600 +#define AR8327_ATU_ADDR0 BITS(0, 8) +#define AR8327_ATU_ADDR0_S 0 +#define AR8327_ATU_ADDR1 BITS(8, 8) +#define AR8327_ATU_ADDR1_S 8 +#define AR8327_ATU_ADDR2 BITS(16, 8) +#define AR8327_ATU_ADDR2_S 16 +#define AR8327_ATU_ADDR3 BITS(24, 8) +#define AR8327_ATU_ADDR3_S 24 +#define AR8327_REG_ATU_DATA1 0x604 +#define AR8327_ATU_ADDR4 BITS(0, 8) +#define AR8327_ATU_ADDR4_S 0 +#define AR8327_ATU_ADDR5 BITS(8, 8) +#define AR8327_ATU_ADDR5_S 8 +#define AR8327_ATU_PORTS BITS(16, 7) +#define AR8327_ATU_PORT0 BIT(16) +#define AR8327_ATU_PORT1 BIT(17) +#define AR8327_ATU_PORT2 BIT(18) +#define AR8327_ATU_PORT3 BIT(19) +#define AR8327_ATU_PORT4 BIT(20) +#define AR8327_ATU_PORT5 BIT(21) +#define AR8327_ATU_PORT6 BIT(22) +#define AR8327_REG_ATU_DATA2 0x608 +#define AR8327_ATU_STATUS BITS(0, 4) + +#define AR8327_REG_ATU_FUNC 0x60c +#define AR8327_ATU_FUNC_OP BITS(0, 4) +#define AR8327_ATU_FUNC_OP_NOOP 0x0 +#define AR8327_ATU_FUNC_OP_FLUSH 0x1 +#define AR8327_ATU_FUNC_OP_LOAD 0x2 +#define AR8327_ATU_FUNC_OP_PURGE 0x3 +#define AR8327_ATU_FUNC_OP_FLUSH_UNLOCKED 0x4 +#define AR8327_ATU_FUNC_OP_FLUSH_PORT 0x5 +#define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 +#define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 +#define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 +#define AR8327_ATU_PORT_NUM BITS(8, 4) +#define AR8327_ATU_PORT_NUM_S 8 +#define AR8327_ATU_FUNC_BUSY BIT(31) + +#define AR8327_REG_VTU_FUNC0 0x0610 +#define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) +#define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) +#define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 +#define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 +#define AR8327_VTU_FUNC0_EG_MODE_TAG 2 +#define AR8327_VTU_FUNC0_EG_MODE_NOT 3 +#define AR8327_VTU_FUNC0_IVL BIT(19) +#define AR8327_VTU_FUNC0_VALID BIT(20) + +#define AR8327_REG_VTU_FUNC1 0x0614 +#define AR8327_VTU_FUNC1_OP BITS(0, 3) +#define AR8327_VTU_FUNC1_OP_NOOP 0 +#define AR8327_VTU_FUNC1_OP_FLUSH 1 +#define AR8327_VTU_FUNC1_OP_LOAD 2 +#define AR8327_VTU_FUNC1_OP_PURGE 3 +#define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 +#define AR8327_VTU_FUNC1_OP_GET_NEXT 5 +#define AR8327_VTU_FUNC1_OP_GET_ONE 6 +#define AR8327_VTU_FUNC1_FULL BIT(4) +#define AR8327_VTU_FUNC1_PORT BIT(8, 4) +#define AR8327_VTU_FUNC1_PORT_S 8 +#define AR8327_VTU_FUNC1_VID BIT(16, 12) +#define AR8327_VTU_FUNC1_VID_S 16 +#define AR8327_VTU_FUNC1_BUSY BIT(31) + +#define AR8327_REG_FWD_CTRL0 0x620 +#define AR8327_FWD_CTRL0_CPU_PORT_EN BIT(10) +#define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) +#define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 + +#define AR8327_REG_FWD_CTRL1 0x624 +#define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) +#define AR8327_FWD_CTRL1_UC_FLOOD_S 0 +#define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) +#define AR8327_FWD_CTRL1_MC_FLOOD_S 8 +#define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) +#define AR8327_FWD_CTRL1_BC_FLOOD_S 16 +#define AR8327_FWD_CTRL1_IGMP BITS(24, 7) +#define AR8327_FWD_CTRL1_IGMP_S 24 + +#define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) +#define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) +#define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) +#define AR8327_PORT_LOOKUP_IN_MODE_S 8 +#define AR8327_PORT_LOOKUP_STATE BITS(16, 3) +#define AR8327_PORT_LOOKUP_STATE_S 16 +#define AR8327_PORT_LOOKUP_LEARN BIT(20) +#define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25) + +#define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) + +#define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) +#define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) + +#define AR8337_PAD_MAC06_EXCHANGE_EN BIT(31) + +enum ar8327_led_pattern { + AR8327_LED_PATTERN_OFF = 0, + AR8327_LED_PATTERN_BLINK, + AR8327_LED_PATTERN_ON, + AR8327_LED_PATTERN_RULE, +}; + +struct ar8327_led_entry { + unsigned reg; + unsigned shift; +}; + +struct ar8327_led { + struct led_classdev cdev; + struct ar8xxx_priv *sw_priv; + + char *name; + bool active_low; + u8 led_num; + enum ar8327_led_mode mode; + + struct mutex mutex; + spinlock_t lock; + struct work_struct led_work; + bool enable_hw_mode; + enum ar8327_led_pattern pattern; +}; + +struct ar8327_data { + u32 port0_status; + u32 port6_status; + + struct ar8327_led **leds; + unsigned int num_leds; + + /* all fields below are cleared on reset */ + bool eee[AR8XXX_NUM_PHYS]; +}; + +#endif diff --git a/target/linux/generic/files/drivers/net/phy/b53/Kconfig b/target/linux/generic/files/drivers/net/phy/b53/Kconfig new file mode 100644 index 0000000..67e053e --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/Kconfig @@ -0,0 +1,37 @@ +menuconfig B53 + tristate "Broadcom bcm53xx managed switch support" + depends on SWCONFIG + help + This driver adds support for Broadcom managed switch chips. It supports + BCM5325E, BCM5365, BCM539x, BCM53115 and BCM53125 as well as BCM63XX + integrated switches. + +config B53_SPI_DRIVER + tristate "B53 SPI connected switch driver" + depends on B53 && SPI + help + Select to enable support for registering switches configured through SPI. + +config B53_PHY_DRIVER + tristate "B53 MDIO connected switch driver" + depends on B53 + select B53_PHY_FIXUP + help + Select to enable support for registering switches configured through MDIO. + +config B53_MMAP_DRIVER + tristate "B53 MMAP connected switch driver" + depends on B53 + help + Select to enable support for memory-mapped switches like the BCM63XX + integrated switches. + +config B53_SRAB_DRIVER + tristate "B53 SRAB connected switch driver" + depends on B53 + help + Select to enable support for memory-mapped Switch Register Access + Bridge Registers (SRAB) like it is found on the BCM53010 + +config B53_PHY_FIXUP + bool diff --git a/target/linux/generic/files/drivers/net/phy/b53/Makefile b/target/linux/generic/files/drivers/net/phy/b53/Makefile new file mode 100644 index 0000000..7cc39c7 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/Makefile @@ -0,0 +1,10 @@ +obj-$(CONFIG_B53) += b53_common.o + +obj-$(CONFIG_B53_PHY_FIXUP) += b53_phy_fixup.o + +obj-$(CONFIG_B53_MMAP_DRIVER) += b53_mmap.o +obj-$(CONFIG_B53_SRAB_DRIVER) += b53_srab.o +obj-$(CONFIG_B53_PHY_DRIVER) += b53_mdio.o +obj-$(CONFIG_B53_SPI_DRIVER) += b53_spi.o + +ccflags-y += -Werror diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c new file mode 100644 index 0000000..859d8d1 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c @@ -0,0 +1,1457 @@ +/* + * B53 switch driver main logic + * + * Copyright (C) 2011-2013 Jonas Gorski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include "b53_regs.h" +#include "b53_priv.h" + +/* buffer size needed for displaying all MIBs with max'd values */ +#define B53_BUF_SIZE 1188 + +struct b53_mib_desc { + u8 size; + u8 offset; + const char *name; +}; + + +/* BCM5365 MIB counters */ +static const struct b53_mib_desc b53_mibs_65[] = { + { 8, 0x00, "TxOctets" }, + { 4, 0x08, "TxDropPkts" }, + { 4, 0x10, "TxBroadcastPkts" }, + { 4, 0x14, "TxMulticastPkts" }, + { 4, 0x18, "TxUnicastPkts" }, + { 4, 0x1c, "TxCollisions" }, + { 4, 0x20, "TxSingleCollision" }, + { 4, 0x24, "TxMultipleCollision" }, + { 4, 0x28, "TxDeferredTransmit" }, + { 4, 0x2c, "TxLateCollision" }, + { 4, 0x30, "TxExcessiveCollision" }, + { 4, 0x38, "TxPausePkts" }, + { 8, 0x44, "RxOctets" }, + { 4, 0x4c, "RxUndersizePkts" }, + { 4, 0x50, "RxPausePkts" }, + { 4, 0x54, "Pkts64Octets" }, + { 4, 0x58, "Pkts65to127Octets" }, + { 4, 0x5c, "Pkts128to255Octets" }, + { 4, 0x60, "Pkts256to511Octets" }, + { 4, 0x64, "Pkts512to1023Octets" }, + { 4, 0x68, "Pkts1024to1522Octets" }, + { 4, 0x6c, "RxOversizePkts" }, + { 4, 0x70, "RxJabbers" }, + { 4, 0x74, "RxAlignmentErrors" }, + { 4, 0x78, "RxFCSErrors" }, + { 8, 0x7c, "RxGoodOctets" }, + { 4, 0x84, "RxDropPkts" }, + { 4, 0x88, "RxUnicastPkts" }, + { 4, 0x8c, "RxMulticastPkts" }, + { 4, 0x90, "RxBroadcastPkts" }, + { 4, 0x94, "RxSAChanges" }, + { 4, 0x98, "RxFragments" }, + { }, +}; + +/* BCM63xx MIB counters */ +static const struct b53_mib_desc b53_mibs_63xx[] = { + { 8, 0x00, "TxOctets" }, + { 4, 0x08, "TxDropPkts" }, + { 4, 0x0c, "TxQoSPkts" }, + { 4, 0x10, "TxBroadcastPkts" }, + { 4, 0x14, "TxMulticastPkts" }, + { 4, 0x18, "TxUnicastPkts" }, + { 4, 0x1c, "TxCollisions" }, + { 4, 0x20, "TxSingleCollision" }, + { 4, 0x24, "TxMultipleCollision" }, + { 4, 0x28, "TxDeferredTransmit" }, + { 4, 0x2c, "TxLateCollision" }, + { 4, 0x30, "TxExcessiveCollision" }, + { 4, 0x38, "TxPausePkts" }, + { 8, 0x3c, "TxQoSOctets" }, + { 8, 0x44, "RxOctets" }, + { 4, 0x4c, "RxUndersizePkts" }, + { 4, 0x50, "RxPausePkts" }, + { 4, 0x54, "Pkts64Octets" }, + { 4, 0x58, "Pkts65to127Octets" }, + { 4, 0x5c, "Pkts128to255Octets" }, + { 4, 0x60, "Pkts256to511Octets" }, + { 4, 0x64, "Pkts512to1023Octets" }, + { 4, 0x68, "Pkts1024to1522Octets" }, + { 4, 0x6c, "RxOversizePkts" }, + { 4, 0x70, "RxJabbers" }, + { 4, 0x74, "RxAlignmentErrors" }, + { 4, 0x78, "RxFCSErrors" }, + { 8, 0x7c, "RxGoodOctets" }, + { 4, 0x84, "RxDropPkts" }, + { 4, 0x88, "RxUnicastPkts" }, + { 4, 0x8c, "RxMulticastPkts" }, + { 4, 0x90, "RxBroadcastPkts" }, + { 4, 0x94, "RxSAChanges" }, + { 4, 0x98, "RxFragments" }, + { 4, 0xa0, "RxSymbolErrors" }, + { 4, 0xa4, "RxQoSPkts" }, + { 8, 0xa8, "RxQoSOctets" }, + { 4, 0xb0, "Pkts1523to2047Octets" }, + { 4, 0xb4, "Pkts2048to4095Octets" }, + { 4, 0xb8, "Pkts4096to8191Octets" }, + { 4, 0xbc, "Pkts8192to9728Octets" }, + { 4, 0xc0, "RxDiscarded" }, + { } +}; + +/* MIB counters */ +static const struct b53_mib_desc b53_mibs[] = { + { 8, 0x00, "TxOctets" }, + { 4, 0x08, "TxDropPkts" }, + { 4, 0x10, "TxBroadcastPkts" }, + { 4, 0x14, "TxMulticastPkts" }, + { 4, 0x18, "TxUnicastPkts" }, + { 4, 0x1c, "TxCollisions" }, + { 4, 0x20, "TxSingleCollision" }, + { 4, 0x24, "TxMultipleCollision" }, + { 4, 0x28, "TxDeferredTransmit" }, + { 4, 0x2c, "TxLateCollision" }, + { 4, 0x30, "TxExcessiveCollision" }, + { 4, 0x38, "TxPausePkts" }, + { 8, 0x50, "RxOctets" }, + { 4, 0x58, "RxUndersizePkts" }, + { 4, 0x5c, "RxPausePkts" }, + { 4, 0x60, "Pkts64Octets" }, + { 4, 0x64, "Pkts65to127Octets" }, + { 4, 0x68, "Pkts128to255Octets" }, + { 4, 0x6c, "Pkts256to511Octets" }, + { 4, 0x70, "Pkts512to1023Octets" }, + { 4, 0x74, "Pkts1024to1522Octets" }, + { 4, 0x78, "RxOversizePkts" }, + { 4, 0x7c, "RxJabbers" }, + { 4, 0x80, "RxAlignmentErrors" }, + { 4, 0x84, "RxFCSErrors" }, + { 8, 0x88, "RxGoodOctets" }, + { 4, 0x90, "RxDropPkts" }, + { 4, 0x94, "RxUnicastPkts" }, + { 4, 0x98, "RxMulticastPkts" }, + { 4, 0x9c, "RxBroadcastPkts" }, + { 4, 0xa0, "RxSAChanges" }, + { 4, 0xa4, "RxFragments" }, + { 4, 0xa8, "RxJumboPkts" }, + { 4, 0xac, "RxSymbolErrors" }, + { 4, 0xc0, "RxDiscarded" }, + { } +}; + +static int b53_do_vlan_op(struct b53_device *dev, u8 op) +{ + unsigned int i; + + b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op); + + for (i = 0; i < 10; i++) { + u8 vta; + + b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta); + if (!(vta & VTA_START_CMD)) + return 0; + + usleep_range(100, 200); + } + + return -EIO; +} + +static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members, + u16 untag) +{ + if (is5325(dev)) { + u32 entry = 0; + + if (members) { + entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) | + members; + if (dev->core_rev >= 3) + entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S; + else + entry |= VA_VALID_25; + } + + b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry); + b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid | + VTA_RW_STATE_WR | VTA_RW_OP_EN); + } else if (is5365(dev)) { + u16 entry = 0; + + if (members) + entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) | + members | VA_VALID_65; + + b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry); + b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid | + VTA_RW_STATE_WR | VTA_RW_OP_EN); + } else { + b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid); + b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], + (untag << VTE_UNTAG_S) | members); + + b53_do_vlan_op(dev, VTA_CMD_WRITE); + } +} + +void b53_set_forwarding(struct b53_device *dev, int enable) +{ + u8 mgmt; + + b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); + + if (enable) + mgmt |= SM_SW_FWD_EN; + else + mgmt &= ~SM_SW_FWD_EN; + + b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); +} + +static void b53_enable_vlan(struct b53_device *dev, int enable) +{ + u8 mgmt, vc0, vc1, vc4 = 0, vc5; + + b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0); + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1); + + if (is5325(dev) || is5365(dev)) { + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5); + } else if (is63xx(dev)) { + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4); + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5); + } else { + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4); + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5); + } + + mgmt &= ~SM_SW_FWD_MODE; + + if (enable) { + vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID; + vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN; + vc4 &= ~VC4_ING_VID_CHECK_MASK; + vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S; + vc5 |= VC5_DROP_VTABLE_MISS; + + if (is5325(dev)) + vc0 &= ~VC0_RESERVED_1; + + if (is5325(dev) || is5365(dev)) + vc1 |= VC1_RX_MCST_TAG_EN; + + if (!is5325(dev) && !is5365(dev)) { + if (dev->allow_vid_4095) + vc5 |= VC5_VID_FFF_EN; + else + vc5 &= ~VC5_VID_FFF_EN; + } + } else { + vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID); + vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN); + vc4 &= ~VC4_ING_VID_CHECK_MASK; + vc5 &= ~VC5_DROP_VTABLE_MISS; + + if (is5325(dev) || is5365(dev)) + vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S; + else + vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S; + + if (is5325(dev) || is5365(dev)) + vc1 &= ~VC1_RX_MCST_TAG_EN; + + if (!is5325(dev) && !is5365(dev)) + vc5 &= ~VC5_VID_FFF_EN; + } + + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0); + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1); + + if (is5325(dev) || is5365(dev)) { + /* enable the high 8 bit vid check on 5325 */ + if (is5325(dev) && enable) + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, + VC3_HIGH_8BIT_EN); + else + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); + + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4); + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5); + } else if (is63xx(dev)) { + b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0); + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4); + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5); + } else { + b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0); + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4); + b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5); + } + + b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); +} + +static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100) +{ + u32 port_mask = 0; + u16 max_size = JMS_MIN_SIZE; + + if (is5325(dev) || is5365(dev)) + return -EINVAL; + + if (enable) { + port_mask = dev->enabled_ports; + max_size = JMS_MAX_SIZE; + if (allow_10_100) + port_mask |= JPM_10_100_JUMBO_EN; + } + + b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask); + return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size); +} + +static int b53_flush_arl(struct b53_device *dev) +{ + unsigned int i; + + b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, + FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC); + + for (i = 0; i < 10; i++) { + u8 fast_age_ctrl; + + b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, + &fast_age_ctrl); + + if (!(fast_age_ctrl & FAST_AGE_DONE)) + return 0; + + mdelay(1); + } + + pr_warn("time out while flushing ARL\n"); + + return -EINVAL; +} + +static void b53_enable_ports(struct b53_device *dev) +{ + unsigned i; + + b53_for_each_port(dev, i) { + u8 port_ctrl; + u16 pvlan_mask; + + /* + * prevent leaking packets between wan and lan in unmanaged + * mode through port vlans. + */ + if (dev->enable_vlan || is_cpu_port(dev, i)) + pvlan_mask = 0x1ff; + else if (is531x5(dev) || is5301x(dev)) + /* BCM53115 may use a different port as cpu port */ + pvlan_mask = BIT(dev->sw_dev.cpu_port); + else + pvlan_mask = BIT(B53_CPU_PORT); + + /* BCM5325 CPU port is at 8 */ + if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25) + i = B53_CPU_PORT; + + if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7)) + /* disable unused ports 6 & 7 */ + port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE; + else if (i == B53_CPU_PORT) + port_ctrl = PORT_CTRL_RX_BCST_EN | + PORT_CTRL_RX_MCST_EN | + PORT_CTRL_RX_UCST_EN; + else + port_ctrl = 0; + + b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), + pvlan_mask); + + /* port state is handled by bcm63xx_enet driver */ + if (!is63xx(dev) && !(is5301x(dev) && i == 6)) + b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i), + port_ctrl); + } +} + +static void b53_enable_mib(struct b53_device *dev) +{ + u8 gc; + + b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); + + gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN); + + b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc); +} + +static int b53_apply(struct b53_device *dev) +{ + int i; + + /* clear all vlan entries */ + if (is5325(dev) || is5365(dev)) { + for (i = 1; i < dev->sw_dev.vlans; i++) + b53_set_vlan_entry(dev, i, 0, 0); + } else { + b53_do_vlan_op(dev, VTA_CMD_CLEAR); + } + + b53_enable_vlan(dev, dev->enable_vlan); + + /* fill VLAN table */ + if (dev->enable_vlan) { + for (i = 0; i < dev->sw_dev.vlans; i++) { + struct b53_vlan *vlan = &dev->vlans[i]; + + if (!vlan->members) + continue; + + b53_set_vlan_entry(dev, i, vlan->members, vlan->untag); + } + + b53_for_each_port(dev, i) + b53_write16(dev, B53_VLAN_PAGE, + B53_VLAN_PORT_DEF_TAG(i), + dev->ports[i].pvid); + } else { + b53_for_each_port(dev, i) + b53_write16(dev, B53_VLAN_PAGE, + B53_VLAN_PORT_DEF_TAG(i), 1); + + } + + b53_enable_ports(dev); + + if (!is5325(dev) && !is5365(dev)) + b53_set_jumbo(dev, dev->enable_jumbo, 1); + + return 0; +} + +static void b53_switch_reset_gpio(struct b53_device *dev) +{ + int gpio = dev->reset_gpio; + + if (gpio < 0) + return; + + /* + * Reset sequence: RESET low(50ms)->high(20ms) + */ + gpio_set_value(gpio, 0); + mdelay(50); + + gpio_set_value(gpio, 1); + mdelay(20); + + dev->current_page = 0xff; +} + +static int b53_switch_reset(struct b53_device *dev) +{ + u8 cpu_port = dev->sw_dev.cpu_port; + u8 mgmt; + + b53_switch_reset_gpio(dev); + + if (is539x(dev)) { + b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83); + b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00); + } + + b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); + + if (!(mgmt & SM_SW_FWD_EN)) { + mgmt &= ~SM_SW_FWD_MODE; + mgmt |= SM_SW_FWD_EN; + + b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); + b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt); + + if (!(mgmt & SM_SW_FWD_EN)) { + pr_err("Failed to enable switch!\n"); + return -EINVAL; + } + } + + /* enable all ports */ + b53_enable_ports(dev); + + /* configure MII port if necessary */ + if (is5325(dev)) { + u8 mii_port_override; + + b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + &mii_port_override); + /* reverse mii needs to be enabled */ + if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) { + b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + mii_port_override | PORT_OVERRIDE_RV_MII_25); + b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + &mii_port_override); + + if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) { + pr_err("Failed to enable reverse MII mode\n"); + return -EINVAL; + } + } + } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) { + u8 mii_port_override; + + b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + &mii_port_override); + b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + mii_port_override | PORT_OVERRIDE_EN | + PORT_OVERRIDE_LINK); + } else if (is5301x(dev)) { + if (cpu_port == 8) { + u8 mii_port_override; + + b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + &mii_port_override); + mii_port_override |= PORT_OVERRIDE_LINK | + PORT_OVERRIDE_RX_FLOW | + PORT_OVERRIDE_TX_FLOW | + PORT_OVERRIDE_SPEED_2000M | + PORT_OVERRIDE_EN; + b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL, + mii_port_override); + + /* TODO: Ports 5 & 7 require some extra handling */ + } else { + u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port); + u8 gmii_po; + + b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po); + gmii_po |= GMII_PO_LINK | + GMII_PO_RX_FLOW | + GMII_PO_TX_FLOW | + GMII_PO_EN | + GMII_PO_SPEED_2000M; + b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po); + } + } + + b53_enable_mib(dev); + + return b53_flush_arl(dev); +} + +/* + * Swconfig glue functions + */ + +static int b53_global_get_vlan_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + + val->value.i = priv->enable_vlan; + + return 0; +} + +static int b53_global_set_vlan_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + + priv->enable_vlan = val->value.i; + + return 0; +} + +static int b53_global_get_jumbo_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + + val->value.i = priv->enable_jumbo; + + return 0; +} + +static int b53_global_set_jumbo_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + + priv->enable_jumbo = val->value.i; + + return 0; +} + +static int b53_global_get_4095_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + + val->value.i = priv->allow_vid_4095; + + return 0; +} + +static int b53_global_set_4095_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + + priv->allow_vid_4095 = val->value.i; + + return 0; +} + +static int b53_global_get_ports(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + + val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x", + priv->enabled_ports); + val->value.s = priv->buf; + + return 0; +} + +static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val) +{ + struct b53_device *priv = sw_to_b53(dev); + + *val = priv->ports[port].pvid; + + return 0; +} + +static int b53_port_set_pvid(struct switch_dev *dev, int port, int val) +{ + struct b53_device *priv = sw_to_b53(dev); + + if (val > 15 && is5325(priv)) + return -EINVAL; + if (val == 4095 && !priv->allow_vid_4095) + return -EINVAL; + + priv->ports[port].pvid = val; + + return 0; +} + +static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + struct switch_port *port = &val->value.ports[0]; + struct b53_vlan *vlan = &priv->vlans[val->port_vlan]; + int i; + + val->len = 0; + + if (!vlan->members) + return 0; + + for (i = 0; i < dev->ports; i++) { + if (!(vlan->members & BIT(i))) + continue; + + + if (!(vlan->untag & BIT(i))) + port->flags = BIT(SWITCH_PORT_FLAG_TAGGED); + else + port->flags = 0; + + port->id = i; + val->len++; + port++; + } + + return 0; +} + +static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + struct switch_port *port; + struct b53_vlan *vlan = &priv->vlans[val->port_vlan]; + int i; + + /* only BCM5325 and BCM5365 supports VID 0 */ + if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv)) + return -EINVAL; + + /* VLAN 4095 needs special handling */ + if (val->port_vlan == 4095 && !priv->allow_vid_4095) + return -EINVAL; + + port = &val->value.ports[0]; + vlan->members = 0; + vlan->untag = 0; + for (i = 0; i < val->len; i++, port++) { + vlan->members |= BIT(port->id); + + if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) { + vlan->untag |= BIT(port->id); + priv->ports[port->id].pvid = val->port_vlan; + }; + } + + /* ignore disabled ports */ + vlan->members &= priv->enabled_ports; + vlan->untag &= priv->enabled_ports; + + return 0; +} + +static int b53_port_get_link(struct switch_dev *dev, int port, + struct switch_port_link *link) +{ + struct b53_device *priv = sw_to_b53(dev); + + if (is_cpu_port(priv, port)) { + link->link = 1; + link->duplex = 1; + link->speed = is5325(priv) || is5365(priv) ? + SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000; + link->aneg = 0; + } else if (priv->enabled_ports & BIT(port)) { + u32 speed; + u16 lnk, duplex; + + b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk); + b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex); + + lnk = (lnk >> port) & 1; + duplex = (duplex >> port) & 1; + + if (is5325(priv) || is5365(priv)) { + u16 tmp; + + b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp); + speed = SPEED_PORT_FE(tmp, port); + } else { + b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed); + speed = SPEED_PORT_GE(speed, port); + } + + link->link = lnk; + if (lnk) { + link->duplex = duplex; + switch (speed) { + case SPEED_STAT_10M: + link->speed = SWITCH_PORT_SPEED_10; + break; + case SPEED_STAT_100M: + link->speed = SWITCH_PORT_SPEED_100; + break; + case SPEED_STAT_1000M: + link->speed = SWITCH_PORT_SPEED_1000; + break; + } + } + + link->aneg = 1; + } else { + link->link = 0; + } + + return 0; + +} + +static int b53_global_reset_switch(struct switch_dev *dev) +{ + struct b53_device *priv = sw_to_b53(dev); + + /* reset vlans */ + priv->enable_vlan = 0; + priv->enable_jumbo = 0; + priv->allow_vid_4095 = 0; + + memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans); + memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports); + + return b53_switch_reset(priv); +} + +static int b53_global_apply_config(struct switch_dev *dev) +{ + struct b53_device *priv = sw_to_b53(dev); + + /* disable switching */ + b53_set_forwarding(priv, 0); + + b53_apply(priv); + + /* enable switching */ + b53_set_forwarding(priv, 1); + + return 0; +} + + +static int b53_global_reset_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *priv = sw_to_b53(dev); + u8 gc; + + b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc); + + b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB); + mdelay(1); + b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB); + mdelay(1); + + return 0; +} + +static int b53_port_get_mib(struct switch_dev *sw_dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct b53_device *dev = sw_to_b53(sw_dev); + const struct b53_mib_desc *mibs; + int port = val->port_vlan; + int len = 0; + + if (!(BIT(port) & dev->enabled_ports)) + return -1; + + if (is5365(dev)) { + if (port == 5) + port = 8; + + mibs = b53_mibs_65; + } else if (is63xx(dev)) { + mibs = b53_mibs_63xx; + } else { + mibs = b53_mibs; + } + + dev->buf[0] = 0; + + for (; mibs->size > 0; mibs++) { + u64 val; + + if (mibs->size == 8) { + b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val); + } else { + u32 val32; + + b53_read32(dev, B53_MIB_PAGE(port), mibs->offset, + &val32); + val = val32; + } + + len += snprintf(dev->buf + len, B53_BUF_SIZE - len, + "%-20s: %llu\n", mibs->name, val); + } + + val->len = len; + val->value.s = dev->buf; + + return 0; +} + +static struct switch_attr b53_global_ops_25[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = b53_global_set_vlan_enable, + .get = b53_global_get_vlan_enable, + .max = 1, + }, + { + .type = SWITCH_TYPE_STRING, + .name = "ports", + .description = "Available ports (as bitmask)", + .get = b53_global_get_ports, + }, +}; + +static struct switch_attr b53_global_ops_65[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = b53_global_set_vlan_enable, + .get = b53_global_get_vlan_enable, + .max = 1, + }, + { + .type = SWITCH_TYPE_STRING, + .name = "ports", + .description = "Available ports (as bitmask)", + .get = b53_global_get_ports, + }, + { + .type = SWITCH_TYPE_INT, + .name = "reset_mib", + .description = "Reset MIB counters", + .set = b53_global_reset_mib, + }, +}; + +static struct switch_attr b53_global_ops[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = b53_global_set_vlan_enable, + .get = b53_global_get_vlan_enable, + .max = 1, + }, + { + .type = SWITCH_TYPE_STRING, + .name = "ports", + .description = "Available Ports (as bitmask)", + .get = b53_global_get_ports, + }, + { + .type = SWITCH_TYPE_INT, + .name = "reset_mib", + .description = "Reset MIB counters", + .set = b53_global_reset_mib, + }, + { + .type = SWITCH_TYPE_INT, + .name = "enable_jumbo", + .description = "Enable Jumbo Frames", + .set = b53_global_set_jumbo_enable, + .get = b53_global_get_jumbo_enable, + .max = 1, + }, + { + .type = SWITCH_TYPE_INT, + .name = "allow_vid_4095", + .description = "Allow VID 4095", + .set = b53_global_set_4095_enable, + .get = b53_global_get_4095_enable, + .max = 1, + }, +}; + +static struct switch_attr b53_port_ops[] = { + { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get port's MIB counters", + .get = b53_port_get_mib, + }, +}; + +static struct switch_attr b53_no_ops[] = { +}; + +static const struct switch_dev_ops b53_switch_ops_25 = { + .attr_global = { + .attr = b53_global_ops_25, + .n_attr = ARRAY_SIZE(b53_global_ops_25), + }, + .attr_port = { + .attr = b53_no_ops, + .n_attr = ARRAY_SIZE(b53_no_ops), + }, + .attr_vlan = { + .attr = b53_no_ops, + .n_attr = ARRAY_SIZE(b53_no_ops), + }, + + .get_vlan_ports = b53_vlan_get_ports, + .set_vlan_ports = b53_vlan_set_ports, + .get_port_pvid = b53_port_get_pvid, + .set_port_pvid = b53_port_set_pvid, + .apply_config = b53_global_apply_config, + .reset_switch = b53_global_reset_switch, + .get_port_link = b53_port_get_link, +}; + +static const struct switch_dev_ops b53_switch_ops_65 = { + .attr_global = { + .attr = b53_global_ops_65, + .n_attr = ARRAY_SIZE(b53_global_ops_65), + }, + .attr_port = { + .attr = b53_port_ops, + .n_attr = ARRAY_SIZE(b53_port_ops), + }, + .attr_vlan = { + .attr = b53_no_ops, + .n_attr = ARRAY_SIZE(b53_no_ops), + }, + + .get_vlan_ports = b53_vlan_get_ports, + .set_vlan_ports = b53_vlan_set_ports, + .get_port_pvid = b53_port_get_pvid, + .set_port_pvid = b53_port_set_pvid, + .apply_config = b53_global_apply_config, + .reset_switch = b53_global_reset_switch, + .get_port_link = b53_port_get_link, +}; + +static const struct switch_dev_ops b53_switch_ops = { + .attr_global = { + .attr = b53_global_ops, + .n_attr = ARRAY_SIZE(b53_global_ops), + }, + .attr_port = { + .attr = b53_port_ops, + .n_attr = ARRAY_SIZE(b53_port_ops), + }, + .attr_vlan = { + .attr = b53_no_ops, + .n_attr = ARRAY_SIZE(b53_no_ops), + }, + + .get_vlan_ports = b53_vlan_get_ports, + .set_vlan_ports = b53_vlan_set_ports, + .get_port_pvid = b53_port_get_pvid, + .set_port_pvid = b53_port_set_pvid, + .apply_config = b53_global_apply_config, + .reset_switch = b53_global_reset_switch, + .get_port_link = b53_port_get_link, +}; + +struct b53_chip_data { + u32 chip_id; + const char *dev_name; + const char *alias; + u16 vlans; + u16 enabled_ports; + u8 cpu_port; + u8 vta_regs[3]; + u8 duplex_reg; + u8 jumbo_pm_reg; + u8 jumbo_size_reg; + const struct switch_dev_ops *sw_ops; +}; + +#define B53_VTA_REGS \ + { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY } +#define B53_VTA_REGS_9798 \ + { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 } +#define B53_VTA_REGS_63XX \ + { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX } + +static const struct b53_chip_data b53_switch_chips[] = { + { + .chip_id = BCM5325_DEVICE_ID, + .dev_name = "BCM5325", + .alias = "bcm5325", + .vlans = 16, + .enabled_ports = 0x1f, + .cpu_port = B53_CPU_PORT_25, + .duplex_reg = B53_DUPLEX_STAT_FE, + .sw_ops = &b53_switch_ops_25, + }, + { + .chip_id = BCM5365_DEVICE_ID, + .dev_name = "BCM5365", + .alias = "bcm5365", + .vlans = 256, + .enabled_ports = 0x1f, + .cpu_port = B53_CPU_PORT_25, + .duplex_reg = B53_DUPLEX_STAT_FE, + .sw_ops = &b53_switch_ops_65, + }, + { + .chip_id = BCM5395_DEVICE_ID, + .dev_name = "BCM5395", + .alias = "bcm5395", + .vlans = 4096, + .enabled_ports = 0x1f, + .cpu_port = B53_CPU_PORT, + .vta_regs = B53_VTA_REGS, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM5397_DEVICE_ID, + .dev_name = "BCM5397", + .alias = "bcm5397", + .vlans = 4096, + .enabled_ports = 0x1f, + .cpu_port = B53_CPU_PORT, + .vta_regs = B53_VTA_REGS_9798, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM5398_DEVICE_ID, + .dev_name = "BCM5398", + .alias = "bcm5398", + .vlans = 4096, + .enabled_ports = 0x7f, + .cpu_port = B53_CPU_PORT, + .vta_regs = B53_VTA_REGS_9798, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM53115_DEVICE_ID, + .dev_name = "BCM53115", + .alias = "bcm53115", + .vlans = 4096, + .enabled_ports = 0x1f, + .vta_regs = B53_VTA_REGS, + .cpu_port = B53_CPU_PORT, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM53125_DEVICE_ID, + .dev_name = "BCM53125", + .alias = "bcm53125", + .vlans = 4096, + .enabled_ports = 0x1f, + .cpu_port = B53_CPU_PORT, + .vta_regs = B53_VTA_REGS, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM53128_DEVICE_ID, + .dev_name = "BCM53128", + .alias = "bcm53128", + .vlans = 4096, + .enabled_ports = 0x1ff, + .cpu_port = B53_CPU_PORT, + .vta_regs = B53_VTA_REGS, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM63XX_DEVICE_ID, + .dev_name = "BCM63xx", + .alias = "bcm63xx", + .vlans = 4096, + .enabled_ports = 0, /* pdata must provide them */ + .cpu_port = B53_CPU_PORT, + .vta_regs = B53_VTA_REGS_63XX, + .duplex_reg = B53_DUPLEX_STAT_63XX, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM53010_DEVICE_ID, + .dev_name = "BCM53010", + .alias = "bcm53011", + .vlans = 4096, + .enabled_ports = 0x1f, + .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ + .vta_regs = B53_VTA_REGS, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM53011_DEVICE_ID, + .dev_name = "BCM53011", + .alias = "bcm53011", + .vlans = 4096, + .enabled_ports = 0x1bf, + .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ + .vta_regs = B53_VTA_REGS, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM53012_DEVICE_ID, + .dev_name = "BCM53012", + .alias = "bcm53011", + .vlans = 4096, + .enabled_ports = 0x1bf, + .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ + .vta_regs = B53_VTA_REGS, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM53018_DEVICE_ID, + .dev_name = "BCM53018", + .alias = "bcm53018", + .vlans = 4096, + .enabled_ports = 0x1f, + .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ + .vta_regs = B53_VTA_REGS, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, + { + .chip_id = BCM53019_DEVICE_ID, + .dev_name = "BCM53019", + .alias = "bcm53019", + .vlans = 4096, + .enabled_ports = 0x1f, + .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ + .vta_regs = B53_VTA_REGS, + .duplex_reg = B53_DUPLEX_STAT_GE, + .jumbo_pm_reg = B53_JUMBO_PORT_MASK, + .jumbo_size_reg = B53_JUMBO_MAX_SIZE, + .sw_ops = &b53_switch_ops, + }, +}; + +static int b53_switch_init(struct b53_device *dev) +{ + struct switch_dev *sw_dev = &dev->sw_dev; + unsigned i; + int ret; + + for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) { + const struct b53_chip_data *chip = &b53_switch_chips[i]; + + if (chip->chip_id == dev->chip_id) { + sw_dev->name = chip->dev_name; + if (!sw_dev->alias) + sw_dev->alias = chip->alias; + if (!dev->enabled_ports) + dev->enabled_ports = chip->enabled_ports; + dev->duplex_reg = chip->duplex_reg; + dev->vta_regs[0] = chip->vta_regs[0]; + dev->vta_regs[1] = chip->vta_regs[1]; + dev->vta_regs[2] = chip->vta_regs[2]; + dev->jumbo_pm_reg = chip->jumbo_pm_reg; + sw_dev->ops = chip->sw_ops; + sw_dev->cpu_port = chip->cpu_port; + sw_dev->vlans = chip->vlans; + break; + } + } + + if (!sw_dev->name) + return -EINVAL; + + /* check which BCM5325x version we have */ + if (is5325(dev)) { + u8 vc4; + + b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4); + + /* check reserved bits */ + switch (vc4 & 3) { + case 1: + /* BCM5325E */ + break; + case 3: + /* BCM5325F - do not use port 4 */ + dev->enabled_ports &= ~BIT(4); + break; + default: +/* On the BCM47XX SoCs this is the supported internal switch.*/ +#ifndef CONFIG_BCM47XX + /* BCM5325M */ + return -EINVAL; +#else + break; +#endif + } + } else if (dev->chip_id == BCM53115_DEVICE_ID) { + u64 strap_value; + + b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); + /* use second IMP port if GMII is enabled */ + if (strap_value & SV_GMII_CTRL_115) + sw_dev->cpu_port = 5; + } + + /* cpu port is always last */ + sw_dev->ports = sw_dev->cpu_port + 1; + dev->enabled_ports |= BIT(sw_dev->cpu_port); + + dev->ports = devm_kzalloc(dev->dev, + sizeof(struct b53_port) * sw_dev->ports, + GFP_KERNEL); + if (!dev->ports) + return -ENOMEM; + + dev->vlans = devm_kzalloc(dev->dev, + sizeof(struct b53_vlan) * sw_dev->vlans, + GFP_KERNEL); + if (!dev->vlans) + return -ENOMEM; + + dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL); + if (!dev->buf) + return -ENOMEM; + + dev->reset_gpio = b53_switch_get_reset_gpio(dev); + if (dev->reset_gpio >= 0) { + ret = devm_gpio_request_one(dev->dev, dev->reset_gpio, + GPIOF_OUT_INIT_HIGH, "robo_reset"); + if (ret) + return ret; + } + + return b53_switch_reset(dev); +} + +struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops, + void *priv) +{ + struct b53_device *dev; + + dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL); + if (!dev) + return NULL; + + dev->dev = base; + dev->ops = ops; + dev->priv = priv; + mutex_init(&dev->reg_mutex); + + return dev; +} +EXPORT_SYMBOL(b53_switch_alloc); + +int b53_switch_detect(struct b53_device *dev) +{ + u32 id32; + u16 tmp; + u8 id8; + int ret; + + ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8); + if (ret) + return ret; + + switch (id8) { + case 0: + /* + * BCM5325 and BCM5365 do not have this register so reads + * return 0. But the read operation did succeed, so assume + * this is one of them. + * + * Next check if we can write to the 5325's VTA register; for + * 5365 it is read only. + */ + + b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf); + b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp); + + if (tmp == 0xf) + dev->chip_id = BCM5325_DEVICE_ID; + else + dev->chip_id = BCM5365_DEVICE_ID; + break; + case BCM5395_DEVICE_ID: + case BCM5397_DEVICE_ID: + case BCM5398_DEVICE_ID: + dev->chip_id = id8; + break; + default: + ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32); + if (ret) + return ret; + + switch (id32) { + case BCM53115_DEVICE_ID: + case BCM53125_DEVICE_ID: + case BCM53128_DEVICE_ID: + case BCM53010_DEVICE_ID: + case BCM53011_DEVICE_ID: + case BCM53012_DEVICE_ID: + case BCM53018_DEVICE_ID: + case BCM53019_DEVICE_ID: + dev->chip_id = id32; + break; + default: + pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n", + id8, id32); + return -ENODEV; + } + } + + if (dev->chip_id == BCM5325_DEVICE_ID) + return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25, + &dev->core_rev); + else + return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID, + &dev->core_rev); +} +EXPORT_SYMBOL(b53_switch_detect); + +int b53_switch_register(struct b53_device *dev) +{ + int ret; + + if (dev->pdata) { + dev->chip_id = dev->pdata->chip_id; + dev->enabled_ports = dev->pdata->enabled_ports; + dev->sw_dev.alias = dev->pdata->alias; + } + + if (!dev->chip_id && b53_switch_detect(dev)) + return -EINVAL; + + ret = b53_switch_init(dev); + if (ret) + return ret; + + pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev); + + return register_switch(&dev->sw_dev, NULL); +} +EXPORT_SYMBOL(b53_switch_register); + +MODULE_AUTHOR("Jonas Gorski "); +MODULE_DESCRIPTION("B53 switch library"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c b/target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c new file mode 100644 index 0000000..3c25f0e --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c @@ -0,0 +1,425 @@ +/* + * B53 register access through MII registers + * + * Copyright (C) 2011-2013 Jonas Gorski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include + +#include "b53_priv.h" + +#define B53_PSEUDO_PHY 0x1e /* Register Access Pseudo PHY */ + +/* MII registers */ +#define REG_MII_PAGE 0x10 /* MII Page register */ +#define REG_MII_ADDR 0x11 /* MII Address register */ +#define REG_MII_DATA0 0x18 /* MII Data register 0 */ +#define REG_MII_DATA1 0x19 /* MII Data register 1 */ +#define REG_MII_DATA2 0x1a /* MII Data register 2 */ +#define REG_MII_DATA3 0x1b /* MII Data register 3 */ + +#define REG_MII_PAGE_ENABLE BIT(0) +#define REG_MII_ADDR_WRITE BIT(0) +#define REG_MII_ADDR_READ BIT(1) + +static int b53_mdio_op(struct b53_device *dev, u8 page, u8 reg, u16 op) +{ + int i; + u16 v; + int ret; + struct mii_bus *bus = dev->priv; + + if (dev->current_page != page) { + /* set page number */ + v = (page << 8) | REG_MII_PAGE_ENABLE; + ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_PAGE, v); + if (ret) + return ret; + dev->current_page = page; + } + + /* set register address */ + v = (reg << 8) | op; + ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_ADDR, v); + if (ret) + return ret; + + /* check if operation completed */ + for (i = 0; i < 5; ++i) { + v = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_ADDR); + if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ))) + break; + usleep_range(10, 100); + } + + if (WARN_ON(i == 5)) + return -EIO; + + return 0; +} + +static int b53_mdio_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) +{ + struct mii_bus *bus = dev->priv; + int ret; + + ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); + if (ret) + return ret; + + *val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0) & 0xff; + + return 0; +} + +static int b53_mdio_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) +{ + struct mii_bus *bus = dev->priv; + int ret; + + ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); + if (ret) + return ret; + + *val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0); + + return 0; +} + +static int b53_mdio_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) +{ + struct mii_bus *bus = dev->priv; + int ret; + + ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); + if (ret) + return ret; + + *val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0); + *val |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA1) << 16; + + return 0; +} + +static int b53_mdio_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + struct mii_bus *bus = dev->priv; + u64 temp = 0; + int i; + int ret; + + ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); + if (ret) + return ret; + + for (i = 2; i >= 0; i--) { + temp <<= 16; + temp |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i); + } + + *val = temp; + + return 0; +} + +static int b53_mdio_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + struct mii_bus *bus = dev->priv; + u64 temp = 0; + int i; + int ret; + + ret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ); + if (ret) + return ret; + + for (i = 3; i >= 0; i--) { + temp <<= 16; + temp |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i); + } + + *val = temp; + + return 0; +} + +static int b53_mdio_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) +{ + struct mii_bus *bus = dev->priv; + int ret; + + ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0, value); + if (ret) + return ret; + + return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); +} + +static int b53_mdio_write16(struct b53_device *dev, u8 page, u8 reg, + u16 value) +{ + struct mii_bus *bus = dev->priv; + int ret; + + ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0, value); + if (ret) + return ret; + + return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); +} + +static int b53_mdio_write32(struct b53_device *dev, u8 page, u8 reg, + u32 value) +{ + struct mii_bus *bus = dev->priv; + unsigned int i; + u32 temp = value; + + for (i = 0; i < 2; i++) { + int ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i, + temp & 0xffff); + if (ret) + return ret; + temp >>= 16; + } + + return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); + +} + +static int b53_mdio_write48(struct b53_device *dev, u8 page, u8 reg, + u64 value) +{ + struct mii_bus *bus = dev->priv; + unsigned i; + u64 temp = value; + + for (i = 0; i < 3; i++) { + int ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i, + temp & 0xffff); + if (ret) + return ret; + temp >>= 16; + } + + return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); + +} + +static int b53_mdio_write64(struct b53_device *dev, u8 page, u8 reg, + u64 value) +{ + struct mii_bus *bus = dev->priv; + unsigned i; + u64 temp = value; + + for (i = 0; i < 4; i++) { + int ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i, + temp & 0xffff); + if (ret) + return ret; + temp >>= 16; + } + + return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); +} + +static struct b53_io_ops b53_mdio_ops = { + .read8 = b53_mdio_read8, + .read16 = b53_mdio_read16, + .read32 = b53_mdio_read32, + .read48 = b53_mdio_read48, + .read64 = b53_mdio_read64, + .write8 = b53_mdio_write8, + .write16 = b53_mdio_write16, + .write32 = b53_mdio_write32, + .write48 = b53_mdio_write48, + .write64 = b53_mdio_write64, +}; + +static int b53_phy_probe(struct phy_device *phydev) +{ + struct b53_device dev; + int ret; + + /* allow the generic phy driver to take over */ + if (phydev->addr != B53_PSEUDO_PHY && phydev->addr != 0) + return -ENODEV; + + dev.current_page = 0xff; + dev.priv = phydev->bus; + dev.ops = &b53_mdio_ops; + dev.pdata = NULL; + mutex_init(&dev.reg_mutex); + + ret = b53_switch_detect(&dev); + if (ret) + return ret; + + if (is5325(&dev) || is5365(&dev)) + phydev->supported = SUPPORTED_100baseT_Full; + else + phydev->supported = SUPPORTED_1000baseT_Full; + + phydev->advertising = phydev->supported; + + return 0; +} + +static int b53_phy_config_init(struct phy_device *phydev) +{ + struct b53_device *dev; + int ret; + + dev = b53_switch_alloc(&phydev->dev, &b53_mdio_ops, phydev->bus); + if (!dev) + return -ENOMEM; + + /* we don't use page 0xff, so force a page set */ + dev->current_page = 0xff; + /* force the ethX as alias */ + dev->sw_dev.alias = phydev->attached_dev->name; + + ret = b53_switch_register(dev); + if (ret) { + dev_err(dev->dev, "failed to register switch: %i\n", ret); + return ret; + } + + phydev->priv = dev; + + return 0; +} + +static void b53_phy_remove(struct phy_device *phydev) +{ + struct b53_device *priv = phydev->priv; + + if (!priv) + return; + + b53_switch_remove(priv); + + phydev->priv = NULL; +} + +static int b53_phy_config_aneg(struct phy_device *phydev) +{ + return 0; +} + +static int b53_phy_read_status(struct phy_device *phydev) +{ + struct b53_device *priv = phydev->priv; + + if (is5325(priv) || is5365(priv)) + phydev->speed = 100; + else + phydev->speed = 1000; + + phydev->duplex = DUPLEX_FULL; + phydev->link = 1; + phydev->state = PHY_RUNNING; + + netif_carrier_on(phydev->attached_dev); + phydev->adjust_link(phydev->attached_dev); + + return 0; +} + +/* BCM5325, BCM539x */ +static struct phy_driver b53_phy_driver_id1 = { + .phy_id = 0x0143bc00, + .name = "Broadcom B53 (1)", + .phy_id_mask = 0x1ffffc00, + .features = 0, + .probe = b53_phy_probe, + .remove = b53_phy_remove, + .config_aneg = b53_phy_config_aneg, + .config_init = b53_phy_config_init, + .read_status = b53_phy_read_status, + .driver = { + .owner = THIS_MODULE, + }, +}; + +/* BCM53125, BCM53128 */ +static struct phy_driver b53_phy_driver_id2 = { + .phy_id = 0x03625c00, + .name = "Broadcom B53 (2)", + .phy_id_mask = 0x1ffffc00, + .features = 0, + .probe = b53_phy_probe, + .remove = b53_phy_remove, + .config_aneg = b53_phy_config_aneg, + .config_init = b53_phy_config_init, + .read_status = b53_phy_read_status, + .driver = { + .owner = THIS_MODULE, + }, +}; + +/* BCM5365 */ +static struct phy_driver b53_phy_driver_id3 = { + .phy_id = 0x00406000, + .name = "Broadcom B53 (3)", + .phy_id_mask = 0x1ffffc00, + .features = 0, + .probe = b53_phy_probe, + .remove = b53_phy_remove, + .config_aneg = b53_phy_config_aneg, + .config_init = b53_phy_config_init, + .read_status = b53_phy_read_status, + .driver = { + .owner = THIS_MODULE, + }, +}; + +int __init b53_phy_driver_register(void) +{ + int ret; + + ret = phy_driver_register(&b53_phy_driver_id1); + if (ret) + return ret; + + ret = phy_driver_register(&b53_phy_driver_id2); + if (ret) + goto err1; + + ret = phy_driver_register(&b53_phy_driver_id3); + if (!ret) + return 0; + + phy_driver_unregister(&b53_phy_driver_id2); +err1: + phy_driver_unregister(&b53_phy_driver_id1); + return ret; +} + +void __exit b53_phy_driver_unregister(void) +{ + phy_driver_unregister(&b53_phy_driver_id3); + phy_driver_unregister(&b53_phy_driver_id2); + phy_driver_unregister(&b53_phy_driver_id1); +} + +module_init(b53_phy_driver_register); +module_exit(b53_phy_driver_unregister); + +MODULE_DESCRIPTION("B53 MDIO access driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_mmap.c b/target/linux/generic/files/drivers/net/phy/b53/b53_mmap.c new file mode 100644 index 0000000..ab1895e --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_mmap.c @@ -0,0 +1,241 @@ +/* + * B53 register access through memory mapped registers + * + * Copyright (C) 2012-2013 Jonas Gorski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include + +#include "b53_priv.h" + +static int b53_mmap_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) +{ + u8 __iomem *regs = dev->priv; + + *val = readb(regs + (page << 8) + reg); + + return 0; +} + +static int b53_mmap_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) +{ + u8 __iomem *regs = dev->priv; + + if (WARN_ON(reg % 2)) + return -EINVAL; + + if (dev->pdata && dev->pdata->big_endian) + *val = readw_be(regs + (page << 8) + reg); + else + *val = readw(regs + (page << 8) + reg); + + return 0; +} + +static int b53_mmap_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) +{ + u8 __iomem *regs = dev->priv; + + if (WARN_ON(reg % 4)) + return -EINVAL; + + if (dev->pdata && dev->pdata->big_endian) + *val = readl_be(regs + (page << 8) + reg); + else + *val = readl(regs + (page << 8) + reg); + + return 0; +} + +static int b53_mmap_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + if (WARN_ON(reg % 2)) + return -EINVAL; + + if (reg % 4) { + u16 lo; + u32 hi; + + b53_mmap_read16(dev, page, reg, &lo); + b53_mmap_read32(dev, page, reg + 2, &hi); + + *val = ((u64)hi << 16) | lo; + } else { + u32 lo; + u16 hi; + + b53_mmap_read32(dev, page, reg, &lo); + b53_mmap_read16(dev, page, reg + 4, &hi); + + *val = ((u64)hi << 32) | lo; + } + + return 0; +} + +static int b53_mmap_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + u32 hi, lo; + + if (WARN_ON(reg % 4)) + return -EINVAL; + + b53_mmap_read32(dev, page, reg, &lo); + b53_mmap_read32(dev, page, reg + 4, &hi); + + *val = ((u64)hi << 32) | lo; + + return 0; +} + +static int b53_mmap_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) +{ + u8 __iomem *regs = dev->priv; + + writeb(value, regs + (page << 8) + reg); + + return 0; +} + +static int b53_mmap_write16(struct b53_device *dev, u8 page, u8 reg, + u16 value) +{ + u8 __iomem *regs = dev->priv; + + if (WARN_ON(reg % 2)) + return -EINVAL; + + if (dev->pdata && dev->pdata->big_endian) + writew_be(value, regs + (page << 8) + reg); + else + writew(value, regs + (page << 8) + reg); + + return 0; +} + +static int b53_mmap_write32(struct b53_device *dev, u8 page, u8 reg, + u32 value) +{ + u8 __iomem *regs = dev->priv; + + if (WARN_ON(reg % 4)) + return -EINVAL; + + if (dev->pdata && dev->pdata->big_endian) + writel_be(value, regs + (page << 8) + reg); + else + writel(value, regs + (page << 8) + reg); + + return 0; +} + +static int b53_mmap_write48(struct b53_device *dev, u8 page, u8 reg, + u64 value) +{ + if (WARN_ON(reg % 2)) + return -EINVAL; + + if (reg % 4) { + u32 hi = (u32)(value >> 16); + u16 lo = (u16)value; + + b53_mmap_write16(dev, page, reg, lo); + b53_mmap_write32(dev, page, reg + 2, hi); + } else { + u16 hi = (u16)(value >> 32); + u32 lo = (u32)value; + + b53_mmap_write32(dev, page, reg, lo); + b53_mmap_write16(dev, page, reg + 4, hi); + } + + return 0; +} + +static int b53_mmap_write64(struct b53_device *dev, u8 page, u8 reg, + u64 value) +{ + u32 hi, lo; + + hi = (u32)(value >> 32); + lo = (u32)value; + + if (WARN_ON(reg % 4)) + return -EINVAL; + + b53_mmap_write32(dev, page, reg, lo); + b53_mmap_write32(dev, page, reg + 4, hi); + + return 0; +} + +static struct b53_io_ops b53_mmap_ops = { + .read8 = b53_mmap_read8, + .read16 = b53_mmap_read16, + .read32 = b53_mmap_read32, + .read48 = b53_mmap_read48, + .read64 = b53_mmap_read64, + .write8 = b53_mmap_write8, + .write16 = b53_mmap_write16, + .write32 = b53_mmap_write32, + .write48 = b53_mmap_write48, + .write64 = b53_mmap_write64, +}; + +static int b53_mmap_probe(struct platform_device *pdev) +{ + struct b53_platform_data *pdata = pdev->dev.platform_data; + struct b53_device *dev; + + if (!pdata) + return -EINVAL; + + dev = b53_switch_alloc(&pdev->dev, &b53_mmap_ops, pdata->regs); + if (!dev) + return -ENOMEM; + + if (pdata) + dev->pdata = pdata; + + platform_set_drvdata(pdev, dev); + + return b53_switch_register(dev); +} + +static int b53_mmap_remove(struct platform_device *pdev) +{ + struct b53_device *dev = platform_get_drvdata(pdev); + + if (dev) + b53_switch_remove(dev); + + return 0; +} + +static struct platform_driver b53_mmap_driver = { + .probe = b53_mmap_probe, + .remove = b53_mmap_remove, + .driver = { + .name = "b53-switch", + }, +}; + +module_platform_driver(b53_mmap_driver); +MODULE_AUTHOR("Jonas Gorski "); +MODULE_DESCRIPTION("B53 MMAP access driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_phy_fixup.c b/target/linux/generic/files/drivers/net/phy/b53/b53_phy_fixup.c new file mode 100644 index 0000000..72d1373 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_phy_fixup.c @@ -0,0 +1,55 @@ +/* + * B53 PHY Fixup call + * + * Copyright (C) 2013 Jonas Gorski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include + +#define B53_PSEUDO_PHY 0x1e /* Register Access Pseudo PHY */ + +#define B53_BRCM_OUI_1 0x0143bc00 +#define B53_BRCM_OUI_2 0x03625c00 +#define B53_BRCM_OUI_3 0x00406000 + +static int b53_phy_fixup(struct phy_device *dev) +{ + u32 phy_id; + struct mii_bus *bus = dev->bus; + + if (dev->addr != B53_PSEUDO_PHY) + return 0; + + /* read the first port's id */ + phy_id = mdiobus_read(bus, 0, 2) << 16; + phy_id |= mdiobus_read(bus, 0, 3); + + if ((phy_id & 0xfffffc00) == B53_BRCM_OUI_1 || + (phy_id & 0xfffffc00) == B53_BRCM_OUI_2 || + (phy_id & 0xfffffc00) == B53_BRCM_OUI_3) { + dev->phy_id = phy_id; + } + + return 0; +} + +int __init b53_phy_fixup_register(void) +{ + return phy_register_fixup_for_id(PHY_ANY_ID, b53_phy_fixup); +} + +subsys_initcall(b53_phy_fixup_register); diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_priv.h b/target/linux/generic/files/drivers/net/phy/b53/b53_priv.h new file mode 100644 index 0000000..0c4c394 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_priv.h @@ -0,0 +1,329 @@ +/* + * B53 common definitions + * + * Copyright (C) 2011-2013 Jonas Gorski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __B53_PRIV_H +#define __B53_PRIV_H + +#include +#include +#include + +struct b53_device; + +struct b53_io_ops { + int (*read8)(struct b53_device *dev, u8 page, u8 reg, u8 *value); + int (*read16)(struct b53_device *dev, u8 page, u8 reg, u16 *value); + int (*read32)(struct b53_device *dev, u8 page, u8 reg, u32 *value); + int (*read48)(struct b53_device *dev, u8 page, u8 reg, u64 *value); + int (*read64)(struct b53_device *dev, u8 page, u8 reg, u64 *value); + int (*write8)(struct b53_device *dev, u8 page, u8 reg, u8 value); + int (*write16)(struct b53_device *dev, u8 page, u8 reg, u16 value); + int (*write32)(struct b53_device *dev, u8 page, u8 reg, u32 value); + int (*write48)(struct b53_device *dev, u8 page, u8 reg, u64 value); + int (*write64)(struct b53_device *dev, u8 page, u8 reg, u64 value); +}; + +enum { + BCM5325_DEVICE_ID = 0x25, + BCM5365_DEVICE_ID = 0x65, + BCM5395_DEVICE_ID = 0x95, + BCM5397_DEVICE_ID = 0x97, + BCM5398_DEVICE_ID = 0x98, + BCM53115_DEVICE_ID = 0x53115, + BCM53125_DEVICE_ID = 0x53125, + BCM53128_DEVICE_ID = 0x53128, + BCM63XX_DEVICE_ID = 0x6300, + BCM53010_DEVICE_ID = 0x53010, + BCM53011_DEVICE_ID = 0x53011, + BCM53012_DEVICE_ID = 0x53012, + BCM53018_DEVICE_ID = 0x53018, + BCM53019_DEVICE_ID = 0x53019, +}; + +#define B53_N_PORTS 9 +#define B53_N_PORTS_25 6 + +struct b53_vlan { + unsigned int members:B53_N_PORTS; + unsigned int untag:B53_N_PORTS; +}; + +struct b53_port { + unsigned int pvid:12; +}; + +struct b53_device { + struct switch_dev sw_dev; + struct b53_platform_data *pdata; + + struct mutex reg_mutex; + const struct b53_io_ops *ops; + + /* chip specific data */ + u32 chip_id; + u8 core_rev; + u8 vta_regs[3]; + u8 duplex_reg; + u8 jumbo_pm_reg; + u8 jumbo_size_reg; + int reset_gpio; + + /* used ports mask */ + u16 enabled_ports; + + /* connect specific data */ + u8 current_page; + struct device *dev; + void *priv; + + /* run time configuration */ + unsigned enable_vlan:1; + unsigned enable_jumbo:1; + unsigned allow_vid_4095:1; + + struct b53_port *ports; + struct b53_vlan *vlans; + + char *buf; +}; + +#define b53_for_each_port(dev, i) \ + for (i = 0; i < B53_N_PORTS; i++) \ + if (dev->enabled_ports & BIT(i)) + + + +static inline int is5325(struct b53_device *dev) +{ + return dev->chip_id == BCM5325_DEVICE_ID; +} + +static inline int is5365(struct b53_device *dev) +{ +#ifdef CONFIG_BCM47XX + return dev->chip_id == BCM5365_DEVICE_ID; +#else + return 0; +#endif +} + +static inline int is5397_98(struct b53_device *dev) +{ + return dev->chip_id == BCM5397_DEVICE_ID || + dev->chip_id == BCM5398_DEVICE_ID; +} + +static inline int is539x(struct b53_device *dev) +{ + return dev->chip_id == BCM5395_DEVICE_ID || + dev->chip_id == BCM5397_DEVICE_ID || + dev->chip_id == BCM5398_DEVICE_ID; +} + +static inline int is531x5(struct b53_device *dev) +{ + return dev->chip_id == BCM53115_DEVICE_ID || + dev->chip_id == BCM53125_DEVICE_ID || + dev->chip_id == BCM53128_DEVICE_ID; +} + +static inline int is63xx(struct b53_device *dev) +{ +#ifdef CONFIG_BCM63XX + return dev->chip_id == BCM63XX_DEVICE_ID; +#else + return 0; +#endif +} + +static inline int is5301x(struct b53_device *dev) +{ + return dev->chip_id == BCM53010_DEVICE_ID || + dev->chip_id == BCM53011_DEVICE_ID || + dev->chip_id == BCM53012_DEVICE_ID || + dev->chip_id == BCM53018_DEVICE_ID || + dev->chip_id == BCM53019_DEVICE_ID; +} + +#define B53_CPU_PORT_25 5 +#define B53_CPU_PORT 8 + +static inline int is_cpu_port(struct b53_device *dev, int port) +{ + return dev->sw_dev.cpu_port == port; +} + +static inline struct b53_device *sw_to_b53(struct switch_dev *sw) +{ + return container_of(sw, struct b53_device, sw_dev); +} + +struct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops, + void *priv); + +int b53_switch_detect(struct b53_device *dev); + +int b53_switch_register(struct b53_device *dev); + +static inline void b53_switch_remove(struct b53_device *dev) +{ + unregister_switch(&dev->sw_dev); +} + +static inline int b53_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->read8(dev, page, reg, val); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->read16(dev, page, reg, val); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->read32(dev, page, reg, val); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->read48(dev, page, reg, val); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->read64(dev, page, reg, val); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->write8(dev, page, reg, value); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_write16(struct b53_device *dev, u8 page, u8 reg, + u16 value) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->write16(dev, page, reg, value); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_write32(struct b53_device *dev, u8 page, u8 reg, + u32 value) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->write32(dev, page, reg, value); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_write48(struct b53_device *dev, u8 page, u8 reg, + u64 value) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->write48(dev, page, reg, value); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +static inline int b53_write64(struct b53_device *dev, u8 page, u8 reg, + u64 value) +{ + int ret; + + mutex_lock(&dev->reg_mutex); + ret = dev->ops->write64(dev, page, reg, value); + mutex_unlock(&dev->reg_mutex); + + return ret; +} + +#ifdef CONFIG_BCM47XX + +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) +#include +#else +#include +#endif +#include +static inline int b53_switch_get_reset_gpio(struct b53_device *dev) +{ + enum bcm47xx_board board = bcm47xx_board_get(); + + switch (board) { + case BCM47XX_BOARD_LINKSYS_WRT300NV11: + case BCM47XX_BOARD_LINKSYS_WRT310NV1: + return 8; + default: + return bcm47xx_nvram_gpio_pin("robo_reset"); + } +} +#else +static inline int b53_switch_get_reset_gpio(struct b53_device *dev) +{ + return -ENOENT; +} +#endif +#endif diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h new file mode 100644 index 0000000..144e1c8 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h @@ -0,0 +1,347 @@ +/* + * B53 register definitions + * + * Copyright (C) 2004 Broadcom Corporation + * Copyright (C) 2011-2013 Jonas Gorski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __B53_REGS_H +#define __B53_REGS_H + +/* Management Port (SMP) Page offsets */ +#define B53_CTRL_PAGE 0x00 /* Control */ +#define B53_STAT_PAGE 0x01 /* Status */ +#define B53_MGMT_PAGE 0x02 /* Management Mode */ +#define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */ +#define B53_ARLCTRL_PAGE 0x04 /* ARL Control */ +#define B53_ARLIO_PAGE 0x05 /* ARL Access */ +#define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */ +#define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ + +/* PHY Registers */ +#define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ +#define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */ +#define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */ + +/* MIB registers */ +#define B53_MIB_PAGE(i) (0x20 + (i)) + +/* Quality of Service (QoS) Registers */ +#define B53_QOS_PAGE 0x30 + +/* Port VLAN Page */ +#define B53_PVLAN_PAGE 0x31 + +/* VLAN Registers */ +#define B53_VLAN_PAGE 0x34 + +/* Jumbo Frame Registers */ +#define B53_JUMBO_PAGE 0x40 + +/* CFP Configuration Registers Page */ +#define B53_CFP_PAGE 0xa1 + +/************************************************************************* + * Control Page registers + *************************************************************************/ + +/* Port Control Register (8 bit) */ +#define B53_PORT_CTRL(i) (0x00 + (i)) +#define PORT_CTRL_RX_DISABLE BIT(0) +#define PORT_CTRL_TX_DISABLE BIT(1) +#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ +#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ +#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ +#define PORT_CTRL_STP_STATE_S 5 +#define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S) + +/* SMP Control Register (8 bit) */ +#define B53_SMP_CTRL 0x0a + +/* Switch Mode Control Register (8 bit) */ +#define B53_SWITCH_MODE 0x0b +#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ +#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ + +/* IMP Port state override register (8 bit) */ +#define B53_PORT_OVERRIDE_CTRL 0x0e +#define PORT_OVERRIDE_LINK BIT(0) +#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ +#define PORT_OVERRIDE_SPEED_S 2 +#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) +#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) +#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) +#define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ +#define PORT_OVERRIDE_RX_FLOW BIT(4) +#define PORT_OVERRIDE_TX_FLOW BIT(5) +#define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */ +#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ + +/* Power-down mode control */ +#define B53_PD_MODE_CTRL_25 0x0f + +/* IP Multicast control (8 bit) */ +#define B53_IP_MULTICAST_CTRL 0x21 +#define B53_IPMC_FWD_EN BIT(1) +#define B53_UC_FWD_EN BIT(6) +#define B53_MC_FWD_EN BIT(7) + +/* (16 bit) */ +#define B53_UC_FLOOD_MASK 0x32 +#define B53_MC_FLOOD_MASK 0x34 +#define B53_IPMC_FLOOD_MASK 0x36 + +/* + * Override Ports 0-7 State on devices with xMII interfaces (8 bit) + * + * For port 8 still use B53_PORT_OVERRIDE_CTRL + * Please note that not all ports are available on every hardware, e.g. BCM5301X + * don't include overriding port 6, BCM63xx also have some limitations. + */ +#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i)) +#define GMII_PO_LINK BIT(0) +#define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ +#define GMII_PO_SPEED_S 2 +#define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S) +#define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S) +#define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S) +#define GMII_PO_RX_FLOW BIT(4) +#define GMII_PO_TX_FLOW BIT(5) +#define GMII_PO_EN BIT(6) /* Use the register contents */ +#define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */ + +/* Software reset register (8 bit) */ +#define B53_SOFTRESET 0x79 + +/* Fast Aging Control register (8 bit) */ +#define B53_FAST_AGE_CTRL 0x88 +#define FAST_AGE_STATIC BIT(0) +#define FAST_AGE_DYNAMIC BIT(1) +#define FAST_AGE_PORT BIT(2) +#define FAST_AGE_VLAN BIT(3) +#define FAST_AGE_STP BIT(4) +#define FAST_AGE_MC BIT(5) +#define FAST_AGE_DONE BIT(7) + +/************************************************************************* + * Status Page registers + *************************************************************************/ + +/* Link Status Summary Register (16bit) */ +#define B53_LINK_STAT 0x00 + +/* Link Status Change Register (16 bit) */ +#define B53_LINK_STAT_CHANGE 0x02 + +/* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */ +#define B53_SPEED_STAT 0x04 +#define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1) +#define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3) +#define SPEED_STAT_10M 0 +#define SPEED_STAT_100M 1 +#define SPEED_STAT_1000M 2 + +/* Duplex Status Summary (16 bit) */ +#define B53_DUPLEX_STAT_FE 0x06 +#define B53_DUPLEX_STAT_GE 0x08 +#define B53_DUPLEX_STAT_63XX 0x0c + +/* Revision ID register for BCM5325 */ +#define B53_REV_ID_25 0x50 + +/* Strap Value (48 bit) */ +#define B53_STRAP_VALUE 0x70 +#define SV_GMII_CTRL_115 BIT(27) + +/************************************************************************* + * Management Mode Page Registers + *************************************************************************/ + +/* Global Management Config Register (8 bit) */ +#define B53_GLOBAL_CONFIG 0x00 +#define GC_RESET_MIB 0x01 +#define GC_RX_BPDU_EN 0x02 +#define GC_MIB_AC_HDR_EN 0x10 +#define GC_MIB_AC_EN 0x20 +#define GC_FRM_MGMT_PORT_M 0xC0 +#define GC_FRM_MGMT_PORT_04 0x00 +#define GC_FRM_MGMT_PORT_MII 0x80 + +/* Broadcom Header control register (8 bit) */ +#define B53_BRCM_HDR 0x03 +#define BRCM_HDR_EN BIT(0) /* Enable tagging on IMP port */ + +/* Device ID register (8 or 32 bit) */ +#define B53_DEVICE_ID 0x30 + +/* Revision ID register (8 bit) */ +#define B53_REV_ID 0x40 + +/************************************************************************* + * ARL Access Page Registers + *************************************************************************/ + +/* VLAN Table Access Register (8 bit) */ +#define B53_VT_ACCESS 0x80 +#define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */ +#define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */ +#define VTA_CMD_WRITE 0 +#define VTA_CMD_READ 1 +#define VTA_CMD_CLEAR 2 +#define VTA_START_CMD BIT(7) + +/* VLAN Table Index Register (16 bit) */ +#define B53_VT_INDEX 0x81 +#define B53_VT_INDEX_9798 0x61 +#define B53_VT_INDEX_63XX 0x62 + +/* VLAN Table Entry Register (32 bit) */ +#define B53_VT_ENTRY 0x83 +#define B53_VT_ENTRY_9798 0x63 +#define B53_VT_ENTRY_63XX 0x64 +#define VTE_MEMBERS 0x1ff +#define VTE_UNTAG_S 9 +#define VTE_UNTAG (0x1ff << 9) + +/************************************************************************* + * Port VLAN Registers + *************************************************************************/ + +/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ +#define B53_PVLAN_PORT_MASK(i) ((i) * 2) + +/************************************************************************* + * 802.1Q Page Registers + *************************************************************************/ + +/* Global QoS Control (8 bit) */ +#define B53_QOS_GLOBAL_CTL 0x00 + +/* Enable 802.1Q for individual Ports (16 bit) */ +#define B53_802_1P_EN 0x04 + +/************************************************************************* + * VLAN Page Registers + *************************************************************************/ + +/* VLAN Control 0 (8 bit) */ +#define B53_VLAN_CTRL0 0x00 +#define VC0_8021PF_CTRL_MASK 0x3 +#define VC0_8021PF_CTRL_NONE 0x0 +#define VC0_8021PF_CTRL_CHANGE_PRI 0x1 +#define VC0_8021PF_CTRL_CHANGE_VID 0x2 +#define VC0_8021PF_CTRL_CHANGE_BOTH 0x3 +#define VC0_8021QF_CTRL_MASK 0xc +#define VC0_8021QF_CTRL_CHANGE_PRI 0x1 +#define VC0_8021QF_CTRL_CHANGE_VID 0x2 +#define VC0_8021QF_CTRL_CHANGE_BOTH 0x3 +#define VC0_RESERVED_1 BIT(1) +#define VC0_DROP_VID_MISS BIT(4) +#define VC0_VID_HASH_VID BIT(5) +#define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */ +#define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */ + +/* VLAN Control 1 (8 bit) */ +#define B53_VLAN_CTRL1 0x01 +#define VC1_RX_MCST_TAG_EN BIT(1) +#define VC1_RX_MCST_FWD_EN BIT(2) +#define VC1_RX_MCST_UNTAG_EN BIT(3) + +/* VLAN Control 2 (8 bit) */ +#define B53_VLAN_CTRL2 0x02 + +/* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */ +#define B53_VLAN_CTRL3 0x03 +#define B53_VLAN_CTRL3_63XX 0x04 +#define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */ +#define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */ + +/* VLAN Control 4 (8 bit) */ +#define B53_VLAN_CTRL4 0x05 +#define B53_VLAN_CTRL4_25 0x04 +#define B53_VLAN_CTRL4_63XX 0x06 +#define VC4_ING_VID_CHECK_S 6 +#define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S) +#define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */ +#define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */ +#define VC4_NO_ING_VID_CHK 2 /* do not check */ +#define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */ + +/* VLAN Control 5 (8 bit) */ +#define B53_VLAN_CTRL5 0x06 +#define B53_VLAN_CTRL5_25 0x05 +#define B53_VLAN_CTRL5_63XX 0x07 +#define VC5_VID_FFF_EN BIT(2) +#define VC5_DROP_VTABLE_MISS BIT(3) + +/* VLAN Control 6 (8 bit) */ +#define B53_VLAN_CTRL6 0x07 +#define B53_VLAN_CTRL6_63XX 0x08 + +/* VLAN Table Access Register (16 bit) */ +#define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */ +#define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */ +#define VTA_VID_LOW_MASK_25 0xf +#define VTA_VID_LOW_MASK_65 0xff +#define VTA_VID_HIGH_S_25 4 +#define VTA_VID_HIGH_S_65 8 +#define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E) +#define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65) +#define VTA_RW_STATE BIT(12) +#define VTA_RW_STATE_RD 0 +#define VTA_RW_STATE_WR BIT(12) +#define VTA_RW_OP_EN BIT(13) + +/* VLAN Read/Write Registers for (16/32 bit) */ +#define B53_VLAN_WRITE_25 0x08 +#define B53_VLAN_WRITE_65 0x0a +#define B53_VLAN_READ 0x0c +#define VA_MEMBER_MASK 0x3f +#define VA_UNTAG_S_25 6 +#define VA_UNTAG_MASK_25 0x3f +#define VA_UNTAG_S_65 7 +#define VA_UNTAG_MASK_65 0x1f +#define VA_VID_HIGH_S 12 +#define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S) +#define VA_VALID_25 BIT(20) +#define VA_VALID_25_R4 BIT(24) +#define VA_VALID_65 BIT(14) + +/* VLAN Port Default Tag (16 bit) */ +#define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i)) + +/************************************************************************* + * Jumbo Frame Page Registers + *************************************************************************/ + +/* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */ +#define B53_JUMBO_PORT_MASK 0x01 +#define B53_JUMBO_PORT_MASK_63XX 0x04 +#define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */ + +/* Good Frame Max Size without 802.1Q TAG (16 bit) */ +#define B53_JUMBO_MAX_SIZE 0x05 +#define B53_JUMBO_MAX_SIZE_63XX 0x08 +#define JMS_MIN_SIZE 1518 +#define JMS_MAX_SIZE 9724 + +/************************************************************************* + * CFP Configuration Page Registers + *************************************************************************/ + +/* CFP Control Register with ports map (8 bit) */ +#define B53_CFP_CTRL 0x00 + +#endif /* !__B53_REGS_H */ diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_spi.c b/target/linux/generic/files/drivers/net/phy/b53/b53_spi.c new file mode 100644 index 0000000..469a8dd --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_spi.c @@ -0,0 +1,330 @@ +/* + * B53 register access through SPI + * + * Copyright (C) 2011-2013 Jonas Gorski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include + +#include +#include +#include +#include + +#include "b53_priv.h" + +#define B53_SPI_DATA 0xf0 + +#define B53_SPI_STATUS 0xfe +#define B53_SPI_CMD_SPIF BIT(7) +#define B53_SPI_CMD_RACK BIT(5) + +#define B53_SPI_CMD_READ 0x00 +#define B53_SPI_CMD_WRITE 0x01 +#define B53_SPI_CMD_NORMAL 0x60 +#define B53_SPI_CMD_FAST 0x10 + +#define B53_SPI_PAGE_SELECT 0xff + +static inline int b53_spi_read_reg(struct spi_device *spi, u8 reg, u8 *val, + unsigned len) +{ + u8 txbuf[2]; + + txbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_READ; + txbuf[1] = reg; + + return spi_write_then_read(spi, txbuf, 2, val, len); +} + +static inline int b53_spi_clear_status(struct spi_device *spi) +{ + unsigned int i; + u8 rxbuf; + int ret; + + for (i = 0; i < 10; i++) { + ret = b53_spi_read_reg(spi, B53_SPI_STATUS, &rxbuf, 1); + if (ret) + return ret; + + if (!(rxbuf & B53_SPI_CMD_SPIF)) + break; + + mdelay(1); + } + + if (i == 10) + return -EIO; + + return 0; +} + +static inline int b53_spi_set_page(struct spi_device *spi, u8 page) +{ + u8 txbuf[3]; + + txbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE; + txbuf[1] = B53_SPI_PAGE_SELECT; + txbuf[2] = page; + + return spi_write(spi, txbuf, sizeof(txbuf)); +} + +static inline int b53_prepare_reg_access(struct spi_device *spi, u8 page) +{ + int ret = b53_spi_clear_status(spi); + + if (ret) + return ret; + + return b53_spi_set_page(spi, page); +} + +static int b53_spi_prepare_reg_read(struct spi_device *spi, u8 reg) +{ + u8 rxbuf; + int retry_count; + int ret; + + ret = b53_spi_read_reg(spi, reg, &rxbuf, 1); + if (ret) + return ret; + + for (retry_count = 0; retry_count < 10; retry_count++) { + ret = b53_spi_read_reg(spi, B53_SPI_STATUS, &rxbuf, 1); + if (ret) + return ret; + + if (rxbuf & B53_SPI_CMD_RACK) + break; + + mdelay(1); + } + + if (retry_count == 10) + return -EIO; + + return 0; +} + +static int b53_spi_read(struct b53_device *dev, u8 page, u8 reg, u8 *data, + unsigned len) +{ + struct spi_device *spi = dev->priv; + int ret; + + ret = b53_prepare_reg_access(spi, page); + if (ret) + return ret; + + ret = b53_spi_prepare_reg_read(spi, reg); + if (ret) + return ret; + + return b53_spi_read_reg(spi, B53_SPI_DATA, data, len); +} + +static int b53_spi_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) +{ + return b53_spi_read(dev, page, reg, val, 1); +} + +static int b53_spi_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) +{ + int ret = b53_spi_read(dev, page, reg, (u8 *)val, 2); + + if (!ret) + *val = le16_to_cpu(*val); + + return ret; +} + +static int b53_spi_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) +{ + int ret = b53_spi_read(dev, page, reg, (u8 *)val, 4); + + if (!ret) + *val = le32_to_cpu(*val); + + return ret; +} + +static int b53_spi_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + int ret; + + *val = 0; + ret = b53_spi_read(dev, page, reg, (u8 *)val, 6); + if (!ret) + *val = le64_to_cpu(*val); + + return ret; +} + +static int b53_spi_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + int ret = b53_spi_read(dev, page, reg, (u8 *)val, 8); + + if (!ret) + *val = le64_to_cpu(*val); + + return ret; +} + +static int b53_spi_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) +{ + struct spi_device *spi = dev->priv; + int ret; + u8 txbuf[3]; + + ret = b53_prepare_reg_access(spi, page); + if (ret) + return ret; + + txbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE; + txbuf[1] = reg; + txbuf[2] = value; + + return spi_write(spi, txbuf, sizeof(txbuf)); +} + +static int b53_spi_write16(struct b53_device *dev, u8 page, u8 reg, u16 value) +{ + struct spi_device *spi = dev->priv; + int ret; + u8 txbuf[4]; + + ret = b53_prepare_reg_access(spi, page); + if (ret) + return ret; + + txbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE; + txbuf[1] = reg; + put_unaligned_le16(value, &txbuf[2]); + + return spi_write(spi, txbuf, sizeof(txbuf)); +} + +static int b53_spi_write32(struct b53_device *dev, u8 page, u8 reg, u32 value) +{ + struct spi_device *spi = dev->priv; + int ret; + u8 txbuf[6]; + + ret = b53_prepare_reg_access(spi, page); + if (ret) + return ret; + + txbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE; + txbuf[1] = reg; + put_unaligned_le32(value, &txbuf[2]); + + return spi_write(spi, txbuf, sizeof(txbuf)); +} + +static int b53_spi_write48(struct b53_device *dev, u8 page, u8 reg, u64 value) +{ + struct spi_device *spi = dev->priv; + int ret; + u8 txbuf[10]; + + ret = b53_prepare_reg_access(spi, page); + if (ret) + return ret; + + txbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE; + txbuf[1] = reg; + put_unaligned_le64(value, &txbuf[2]); + + return spi_write(spi, txbuf, sizeof(txbuf) - 2); +} + +static int b53_spi_write64(struct b53_device *dev, u8 page, u8 reg, u64 value) +{ + struct spi_device *spi = dev->priv; + int ret; + u8 txbuf[10]; + + ret = b53_prepare_reg_access(spi, page); + if (ret) + return ret; + + txbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE; + txbuf[1] = reg; + put_unaligned_le64(value, &txbuf[2]); + + return spi_write(spi, txbuf, sizeof(txbuf)); +} + +static struct b53_io_ops b53_spi_ops = { + .read8 = b53_spi_read8, + .read16 = b53_spi_read16, + .read32 = b53_spi_read32, + .read48 = b53_spi_read48, + .read64 = b53_spi_read64, + .write8 = b53_spi_write8, + .write16 = b53_spi_write16, + .write32 = b53_spi_write32, + .write48 = b53_spi_write48, + .write64 = b53_spi_write64, +}; + +static int b53_spi_probe(struct spi_device *spi) +{ + struct b53_device *dev; + int ret; + + dev = b53_switch_alloc(&spi->dev, &b53_spi_ops, spi); + if (!dev) + return -ENOMEM; + + if (spi->dev.platform_data) + dev->pdata = spi->dev.platform_data; + + ret = b53_switch_register(dev); + if (ret) + return ret; + + spi_set_drvdata(spi, dev); + + return 0; +} + +static int b53_spi_remove(struct spi_device *spi) +{ + struct b53_device *dev = spi_get_drvdata(spi); + + if (dev) + b53_switch_remove(dev); + + return 0; +} + +static struct spi_driver b53_spi_driver = { + .driver = { + .name = "b53-switch", + .bus = &spi_bus_type, + .owner = THIS_MODULE, + }, + .probe = b53_spi_probe, + .remove = b53_spi_remove, +}; + +module_spi_driver(b53_spi_driver); + +MODULE_AUTHOR("Jonas Gorski "); +MODULE_DESCRIPTION("B53 SPI access driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_srab.c b/target/linux/generic/files/drivers/net/phy/b53/b53_srab.c new file mode 100644 index 0000000..012daa3 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_srab.c @@ -0,0 +1,378 @@ +/* + * B53 register access through Switch Register Access Bridge Registers + * + * Copyright (C) 2013 Hauke Mehrtens + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include + +#include "b53_priv.h" + +/* command and status register of the SRAB */ +#define B53_SRAB_CMDSTAT 0x2c +#define B53_SRAB_CMDSTAT_RST BIT(2) +#define B53_SRAB_CMDSTAT_WRITE BIT(1) +#define B53_SRAB_CMDSTAT_GORDYN BIT(0) +#define B53_SRAB_CMDSTAT_PAGE 24 +#define B53_SRAB_CMDSTAT_REG 16 + +/* high order word of write data to switch registe */ +#define B53_SRAB_WD_H 0x30 + +/* low order word of write data to switch registe */ +#define B53_SRAB_WD_L 0x34 + +/* high order word of read data from switch register */ +#define B53_SRAB_RD_H 0x38 + +/* low order word of read data from switch register */ +#define B53_SRAB_RD_L 0x3c + +/* command and status register of the SRAB */ +#define B53_SRAB_CTRLS 0x40 +#define B53_SRAB_CTRLS_RCAREQ BIT(3) +#define B53_SRAB_CTRLS_RCAGNT BIT(4) +#define B53_SRAB_CTRLS_SW_INIT_DONE BIT(6) + +/* the register captures interrupt pulses from the switch */ +#define B53_SRAB_INTR 0x44 + +static int b53_srab_request_grant(struct b53_device *dev) +{ + u8 __iomem *regs = dev->priv; + u32 ctrls; + int i; + + ctrls = readl(regs + B53_SRAB_CTRLS); + ctrls |= B53_SRAB_CTRLS_RCAREQ; + writel(ctrls, regs + B53_SRAB_CTRLS); + + for (i = 0; i < 20; i++) { + ctrls = readl(regs + B53_SRAB_CTRLS); + if (ctrls & B53_SRAB_CTRLS_RCAGNT) + break; + usleep_range(10, 100); + } + if (WARN_ON(i == 5)) + return -EIO; + + return 0; +} + +static void b53_srab_release_grant(struct b53_device *dev) +{ + u8 __iomem *regs = dev->priv; + u32 ctrls; + + ctrls = readl(regs + B53_SRAB_CTRLS); + ctrls &= ~B53_SRAB_CTRLS_RCAREQ; + writel(ctrls, regs + B53_SRAB_CTRLS); +} + +static int b53_srab_op(struct b53_device *dev, u8 page, u8 reg, u32 op) +{ + int i; + u32 cmdstat; + u8 __iomem *regs = dev->priv; + + /* set register address */ + cmdstat = (page << B53_SRAB_CMDSTAT_PAGE) | + (reg << B53_SRAB_CMDSTAT_REG) | + B53_SRAB_CMDSTAT_GORDYN | + op; + writel(cmdstat, regs + B53_SRAB_CMDSTAT); + + /* check if operation completed */ + for (i = 0; i < 5; ++i) { + cmdstat = readl(regs + B53_SRAB_CMDSTAT); + if (!(cmdstat & B53_SRAB_CMDSTAT_GORDYN)) + break; + usleep_range(10, 100); + } + + if (WARN_ON(i == 5)) + return -EIO; + + return 0; +} + +static int b53_srab_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + ret = b53_srab_op(dev, page, reg, 0); + if (ret) + goto err; + + *val = readl(regs + B53_SRAB_RD_L) & 0xff; + +err: + b53_srab_release_grant(dev); + + return ret; +} + +static int b53_srab_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + ret = b53_srab_op(dev, page, reg, 0); + if (ret) + goto err; + + *val = readl(regs + B53_SRAB_RD_L) & 0xffff; + +err: + b53_srab_release_grant(dev); + + return ret; +} + +static int b53_srab_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + ret = b53_srab_op(dev, page, reg, 0); + if (ret) + goto err; + + *val = readl(regs + B53_SRAB_RD_L); + +err: + b53_srab_release_grant(dev); + + return ret; +} + +static int b53_srab_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + ret = b53_srab_op(dev, page, reg, 0); + if (ret) + goto err; + + *val = readl(regs + B53_SRAB_RD_L); + *val += ((u64)readl(regs + B53_SRAB_RD_H) & 0xffff) << 32; + +err: + b53_srab_release_grant(dev); + + return ret; +} + +static int b53_srab_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + ret = b53_srab_op(dev, page, reg, 0); + if (ret) + goto err; + + *val = readl(regs + B53_SRAB_RD_L); + *val += (u64)readl(regs + B53_SRAB_RD_H) << 32; + +err: + b53_srab_release_grant(dev); + + return ret; +} + +static int b53_srab_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + writel(value, regs + B53_SRAB_WD_L); + + ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); + +err: + b53_srab_release_grant(dev); + + return ret; +} + +static int b53_srab_write16(struct b53_device *dev, u8 page, u8 reg, + u16 value) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + writel(value, regs + B53_SRAB_WD_L); + + ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); + +err: + b53_srab_release_grant(dev); + + return ret; +} + +static int b53_srab_write32(struct b53_device *dev, u8 page, u8 reg, + u32 value) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + writel(value, regs + B53_SRAB_WD_L); + + ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); + +err: + b53_srab_release_grant(dev); + + return ret; + +} + +static int b53_srab_write48(struct b53_device *dev, u8 page, u8 reg, + u64 value) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + writel((u32)value, regs + B53_SRAB_WD_L); + writel((u16)(value >> 32), regs + B53_SRAB_WD_H); + + ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); + +err: + b53_srab_release_grant(dev); + + return ret; + +} + +static int b53_srab_write64(struct b53_device *dev, u8 page, u8 reg, + u64 value) +{ + u8 __iomem *regs = dev->priv; + int ret = 0; + + ret = b53_srab_request_grant(dev); + if (ret) + goto err; + + writel((u32)value, regs + B53_SRAB_WD_L); + writel((u32)(value >> 32), regs + B53_SRAB_WD_H); + + ret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE); + +err: + b53_srab_release_grant(dev); + + return ret; +} + +static struct b53_io_ops b53_srab_ops = { + .read8 = b53_srab_read8, + .read16 = b53_srab_read16, + .read32 = b53_srab_read32, + .read48 = b53_srab_read48, + .read64 = b53_srab_read64, + .write8 = b53_srab_write8, + .write16 = b53_srab_write16, + .write32 = b53_srab_write32, + .write48 = b53_srab_write48, + .write64 = b53_srab_write64, +}; + +static int b53_srab_probe(struct platform_device *pdev) +{ + struct b53_platform_data *pdata = pdev->dev.platform_data; + struct b53_device *dev; + + if (!pdata) + return -EINVAL; + + dev = b53_switch_alloc(&pdev->dev, &b53_srab_ops, pdata->regs); + if (!dev) + return -ENOMEM; + + if (pdata) + dev->pdata = pdata; + + platform_set_drvdata(pdev, dev); + + return b53_switch_register(dev); +} + +static int b53_srab_remove(struct platform_device *pdev) +{ + struct b53_device *dev = platform_get_drvdata(pdev); + + if (dev) + b53_switch_remove(dev); + + return 0; +} + +static struct platform_driver b53_srab_driver = { + .probe = b53_srab_probe, + .remove = b53_srab_remove, + .driver = { + .name = "b53-srab-switch", + }, +}; + +module_platform_driver(b53_srab_driver); +MODULE_AUTHOR("Hauke Mehrtens "); +MODULE_DESCRIPTION("B53 Switch Register Access Bridge Registers (SRAB) access driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/target/linux/generic/files/drivers/net/phy/ip17xx.c b/target/linux/generic/files/drivers/net/phy/ip17xx.c new file mode 100644 index 0000000..c82c39e --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/ip17xx.c @@ -0,0 +1,1410 @@ +/* + * ip17xx.c: Swconfig configuration for IC+ IP17xx switch family + * + * Copyright (C) 2008 Patrick Horn + * Copyright (C) 2008, 2010 Martin Mares + * Copyright (C) 2009 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_VLANS 16 +#define MAX_PORTS 9 +#undef DUMP_MII_IO + +typedef struct ip17xx_reg { + u16 p; // phy + u16 m; // mii +} reg; +typedef char bitnum; + +#define NOTSUPPORTED {-1,-1} + +#define REG_SUPP(x) (((x).m != ((u16)-1)) && ((x).p != (u16)-1)) + +struct ip17xx_state; + +/*********** CONSTANTS ***********/ +struct register_mappings { + char *NAME; + u16 MODEL_NO; // Compare to bits 4-9 of MII register 0,3. + bitnum NUM_PORTS; + bitnum CPU_PORT; + +/* The default VLAN for each port. + Default: 0x0001 for Ports 0,1,2,3 + 0x0002 for Ports 4,5 */ + reg VLAN_DEFAULT_TAG_REG[MAX_PORTS]; + +/* These ports are tagged. + Default: 0x00 */ + reg ADD_TAG_REG; + reg REMOVE_TAG_REG; + bitnum ADD_TAG_BIT[MAX_PORTS]; +/* These ports are untagged. + Default: 0x00 (i.e. do not alter any VLAN tags...) + Maybe set to 0 if user disables VLANs. */ + bitnum REMOVE_TAG_BIT[MAX_PORTS]; + +/* Port M and Port N are on the same VLAN. + Default: All ports on all VLANs. */ +// Use register {29, 19+N/2} + reg VLAN_LOOKUP_REG; +// Port 5 uses register {30, 18} but same as odd bits. + reg VLAN_LOOKUP_REG_5; // in a different register on IP175C. + bitnum VLAN_LOOKUP_EVEN_BIT[MAX_PORTS]; + bitnum VLAN_LOOKUP_ODD_BIT[MAX_PORTS]; + +/* This VLAN corresponds to which ports. + Default: 0x2f,0x30,0x3f,0x3f... */ + reg TAG_VLAN_MASK_REG; + bitnum TAG_VLAN_MASK_EVEN_BIT[MAX_PORTS]; + bitnum TAG_VLAN_MASK_ODD_BIT[MAX_PORTS]; + + int RESET_VAL; + reg RESET_REG; + + reg MODE_REG; + int MODE_VAL; + +/* General flags */ + reg ROUTER_CONTROL_REG; + reg VLAN_CONTROL_REG; + bitnum TAG_VLAN_BIT; + bitnum ROUTER_EN_BIT; + bitnum NUMLAN_GROUPS_MAX; + bitnum NUMLAN_GROUPS_BIT; + + reg MII_REGISTER_EN; + bitnum MII_REGISTER_EN_BIT; + + // set to 1 for 178C, 0 for 175C. + bitnum SIMPLE_VLAN_REGISTERS; // 175C has two vlans per register but 178C has only one. + + // Pointers to functions which manipulate hardware state + int (*update_state)(struct ip17xx_state *state); + int (*set_vlan_mode)(struct ip17xx_state *state); + int (*reset)(struct ip17xx_state *state); +}; + +static int ip175c_update_state(struct ip17xx_state *state); +static int ip175c_set_vlan_mode(struct ip17xx_state *state); +static int ip175c_reset(struct ip17xx_state *state); + +static const struct register_mappings IP178C = { + .NAME = "IP178C", + .MODEL_NO = 0x18, + .VLAN_DEFAULT_TAG_REG = { + {30,3},{30,4},{30,5},{30,6},{30,7},{30,8}, + {30,9},{30,10},{30,11}, + }, + + .ADD_TAG_REG = {30,12}, + .ADD_TAG_BIT = {0,1,2,3,4,5,6,7,8}, + .REMOVE_TAG_REG = {30,13}, + .REMOVE_TAG_BIT = {4,5,6,7,8,9,10,11,12}, + + .SIMPLE_VLAN_REGISTERS = 1, + + .VLAN_LOOKUP_REG = {31,0},// +N + .VLAN_LOOKUP_REG_5 = NOTSUPPORTED, // not used with SIMPLE_VLAN_REGISTERS + .VLAN_LOOKUP_EVEN_BIT = {0,1,2,3,4,5,6,7,8}, + .VLAN_LOOKUP_ODD_BIT = {0,1,2,3,4,5,6,7,8}, + + .TAG_VLAN_MASK_REG = {30,14}, // +N + .TAG_VLAN_MASK_EVEN_BIT = {0,1,2,3,4,5,6,7,8}, + .TAG_VLAN_MASK_ODD_BIT = {0,1,2,3,4,5,6,7,8}, + + .RESET_VAL = 0x55AA, + .RESET_REG = {30,0}, + .MODE_VAL = 0, + .MODE_REG = NOTSUPPORTED, + + .ROUTER_CONTROL_REG = {30,30}, + .ROUTER_EN_BIT = 11, + .NUMLAN_GROUPS_MAX = 8, + .NUMLAN_GROUPS_BIT = 8, // {0-2} + + .VLAN_CONTROL_REG = {30,13}, + .TAG_VLAN_BIT = 3, + + .CPU_PORT = 8, + .NUM_PORTS = 9, + + .MII_REGISTER_EN = NOTSUPPORTED, + + .update_state = ip175c_update_state, + .set_vlan_mode = ip175c_set_vlan_mode, + .reset = ip175c_reset, +}; + +static const struct register_mappings IP175C = { + .NAME = "IP175C", + .MODEL_NO = 0x18, + .VLAN_DEFAULT_TAG_REG = { + {29,24},{29,25},{29,26},{29,27},{29,28},{29,30}, + NOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED + }, + + .ADD_TAG_REG = {29,23}, + .REMOVE_TAG_REG = {29,23}, + .ADD_TAG_BIT = {11,12,13,14,15,1,-1,-1,-1}, + .REMOVE_TAG_BIT = {6,7,8,9,10,0,-1,-1,-1}, + + .SIMPLE_VLAN_REGISTERS = 0, + + .VLAN_LOOKUP_REG = {29,19},// +N/2 + .VLAN_LOOKUP_REG_5 = {30,18}, + .VLAN_LOOKUP_EVEN_BIT = {8,9,10,11,12,15,-1,-1,-1}, + .VLAN_LOOKUP_ODD_BIT = {0,1,2,3,4,7,-1,-1,-1}, + + .TAG_VLAN_MASK_REG = {30,1}, // +N/2 + .TAG_VLAN_MASK_EVEN_BIT = {0,1,2,3,4,5,-1,-1,-1}, + .TAG_VLAN_MASK_ODD_BIT = {8,9,10,11,12,13,-1,-1,-1}, + + .RESET_VAL = 0x175C, + .RESET_REG = {30,0}, + .MODE_VAL = 0x175C, + .MODE_REG = {29,31}, + + .ROUTER_CONTROL_REG = {30,9}, + .ROUTER_EN_BIT = 3, + .NUMLAN_GROUPS_MAX = 8, + .NUMLAN_GROUPS_BIT = 0, // {0-2} + + .VLAN_CONTROL_REG = {30,9}, + .TAG_VLAN_BIT = 7, + + .NUM_PORTS = 6, + .CPU_PORT = 5, + + .MII_REGISTER_EN = NOTSUPPORTED, + + .update_state = ip175c_update_state, + .set_vlan_mode = ip175c_set_vlan_mode, + .reset = ip175c_reset, +}; + +static const struct register_mappings IP175A = { + .NAME = "IP175A", + .MODEL_NO = 0x05, + .VLAN_DEFAULT_TAG_REG = { + {0,24},{0,25},{0,26},{0,27},{0,28},NOTSUPPORTED, + NOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED + }, + + .ADD_TAG_REG = {0,23}, + .REMOVE_TAG_REG = {0,23}, + .ADD_TAG_BIT = {11,12,13,14,15,-1,-1,-1,-1}, + .REMOVE_TAG_BIT = {6,7,8,9,10,-1,-1,-1,-1}, + + .SIMPLE_VLAN_REGISTERS = 0, + + // Only programmable via EEPROM + .VLAN_LOOKUP_REG = NOTSUPPORTED,// +N/2 + .VLAN_LOOKUP_REG_5 = NOTSUPPORTED, + .VLAN_LOOKUP_EVEN_BIT = {8,9,10,11,12,-1,-1,-1,-1}, + .VLAN_LOOKUP_ODD_BIT = {0,1,2,3,4,-1,-1,-1,-1}, + + .TAG_VLAN_MASK_REG = NOTSUPPORTED, // +N/2, + .TAG_VLAN_MASK_EVEN_BIT = {-1,-1,-1,-1,-1,-1,-1,-1,-1}, + .TAG_VLAN_MASK_ODD_BIT = {-1,-1,-1,-1,-1,-1,-1,-1,-1}, + + .RESET_VAL = -1, + .RESET_REG = NOTSUPPORTED, + .MODE_VAL = 0, + .MODE_REG = NOTSUPPORTED, + + .ROUTER_CONTROL_REG = NOTSUPPORTED, + .VLAN_CONTROL_REG = NOTSUPPORTED, + .TAG_VLAN_BIT = -1, + .ROUTER_EN_BIT = -1, + .NUMLAN_GROUPS_MAX = -1, + .NUMLAN_GROUPS_BIT = -1, // {0-2} + + .NUM_PORTS = 5, + .CPU_PORT = 4, + + .MII_REGISTER_EN = {0, 18}, + .MII_REGISTER_EN_BIT = 7, + + .update_state = ip175c_update_state, + .set_vlan_mode = ip175c_set_vlan_mode, + .reset = ip175c_reset, +}; + + +static int ip175d_update_state(struct ip17xx_state *state); +static int ip175d_set_vlan_mode(struct ip17xx_state *state); +static int ip175d_reset(struct ip17xx_state *state); + +static const struct register_mappings IP175D = { + .NAME = "IP175D", + .MODEL_NO = 0x18, + + // The IP175D has a completely different interface, so we leave most + // of the registers undefined and switch to different code paths. + + .VLAN_DEFAULT_TAG_REG = { + NOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED, + NOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED, + }, + + .ADD_TAG_REG = NOTSUPPORTED, + .REMOVE_TAG_REG = NOTSUPPORTED, + + .SIMPLE_VLAN_REGISTERS = 0, + + .VLAN_LOOKUP_REG = NOTSUPPORTED, + .VLAN_LOOKUP_REG_5 = NOTSUPPORTED, + .TAG_VLAN_MASK_REG = NOTSUPPORTED, + + .RESET_VAL = 0x175D, + .RESET_REG = {20,2}, + .MODE_REG = NOTSUPPORTED, + + .ROUTER_CONTROL_REG = NOTSUPPORTED, + .ROUTER_EN_BIT = -1, + .NUMLAN_GROUPS_BIT = -1, + + .VLAN_CONTROL_REG = NOTSUPPORTED, + .TAG_VLAN_BIT = -1, + + .NUM_PORTS = 6, + .CPU_PORT = 5, + + .MII_REGISTER_EN = NOTSUPPORTED, + + .update_state = ip175d_update_state, + .set_vlan_mode = ip175d_set_vlan_mode, + .reset = ip175d_reset, +}; + +struct ip17xx_state { + struct switch_dev dev; + struct mii_bus *mii_bus; + bool registered; + + int router_mode; // ROUTER_EN + int vlan_enabled; // TAG_VLAN_EN + struct port_state { + u16 pvid; + unsigned int shareports; + } ports[MAX_PORTS]; + unsigned int add_tag; + unsigned int remove_tag; + int num_vlans; + struct vlan_state { + unsigned int ports; + unsigned int tag; // VLAN tag (IP175D only) + } vlans[MAX_VLANS]; + const struct register_mappings *regs; + reg proc_mii; // phy/reg for the low level register access via swconfig + + char buf[80]; +}; + +#define get_state(_dev) container_of((_dev), struct ip17xx_state, dev) + +static int ip_phy_read(struct ip17xx_state *state, int port, int reg) +{ + int val = mdiobus_read(state->mii_bus, port, reg); + if (val < 0) + pr_warning("IP17xx: Unable to get MII register %d,%d: error %d\n", port, reg, -val); +#ifdef DUMP_MII_IO + else + pr_debug("IP17xx: Read MII(%d,%d) -> %04x\n", port, reg, val); +#endif + return val; +} + +static int ip_phy_write(struct ip17xx_state *state, int port, int reg, u16 val) +{ + int err; + +#ifdef DUMP_MII_IO + pr_debug("IP17xx: Write MII(%d,%d) <- %04x\n", port, reg, val); +#endif + err = mdiobus_write(state->mii_bus, port, reg, val); + if (err < 0) + pr_warning("IP17xx: Unable to write MII register %d,%d: error %d\n", port, reg, -err); + return err; +} + +static int ip_phy_write_masked(struct ip17xx_state *state, int port, int reg, unsigned int mask, unsigned int data) +{ + int val = ip_phy_read(state, port, reg); + if (val < 0) + return 0; + return ip_phy_write(state, port, reg, (val & ~mask) | data); +} + +static int getPhy(struct ip17xx_state *state, reg mii) +{ + if (!REG_SUPP(mii)) + return -EFAULT; + return ip_phy_read(state, mii.p, mii.m); +} + +static int setPhy(struct ip17xx_state *state, reg mii, u16 value) +{ + int err; + + if (!REG_SUPP(mii)) + return -EFAULT; + err = ip_phy_write(state, mii.p, mii.m, value); + if (err < 0) + return err; + mdelay(2); + getPhy(state, mii); + return 0; +} + + +/** + * These two macros are to simplify the mapping of logical bits to the bits in hardware. + * NOTE: these macros will return if there is an error! + */ + +#define GET_PORT_BITS(state, bits, addr, bit_lookup) \ + do { \ + int i, val = getPhy((state), (addr)); \ + if (val < 0) \ + return val; \ + (bits) = 0; \ + for (i = 0; i < MAX_PORTS; i++) { \ + if ((bit_lookup)[i] == -1) continue; \ + if (val & (1<<(bit_lookup)[i])) \ + (bits) |= (1<>i)<<(bit_lookup)[i]); \ + } \ + val = setPhy((state), (addr), val); \ + if (val < 0) \ + return val; \ + } while (0) + + +static int get_model(struct ip17xx_state *state) +{ + int id1, id2; + int oui_id, model_no, rev_no, chip_no; + + id1 = ip_phy_read(state, 0, 2); + id2 = ip_phy_read(state, 0, 3); + oui_id = (id1 << 6) | ((id2 >> 10) & 0x3f); + model_no = (id2 >> 4) & 0x3f; + rev_no = id2 & 0xf; + pr_debug("IP17xx: Identified oui=%06x model=%02x rev=%X\n", oui_id, model_no, rev_no); + + if (oui_id != 0x0090c3) // No other oui_id should have reached us anyway + return -ENODEV; + + if (model_no == IP175A.MODEL_NO) { + state->regs = &IP175A; + } else if (model_no == IP175C.MODEL_NO) { + /* + * Several models share the same model_no: + * 178C has more PHYs, so we try whether the device responds to a read from PHY5 + * 175D has a new chip ID register + * 175C has neither + */ + if (ip_phy_read(state, 5, 2) == 0x0243) { + state->regs = &IP178C; + } else { + chip_no = ip_phy_read(state, 20, 0); + pr_debug("IP17xx: Chip ID register reads %04x\n", chip_no); + if (chip_no == 0x175d) { + state->regs = &IP175D; + } else { + state->regs = &IP175C; + } + } + } else { + pr_warning("IP17xx: Found an unknown IC+ switch with model number %02x, revision %X.\n", model_no, rev_no); + return -EPERM; + } + return 0; +} + +/*** Low-level functions for the older models ***/ + +/** Only set vlan and router flags in the switch **/ +static int ip175c_set_flags(struct ip17xx_state *state) +{ + int val; + + if (!REG_SUPP(state->regs->ROUTER_CONTROL_REG)) { + return 0; + } + + val = getPhy(state, state->regs->ROUTER_CONTROL_REG); + if (val < 0) { + return val; + } + if (state->regs->ROUTER_EN_BIT >= 0) { + if (state->router_mode) { + val |= (1<regs->ROUTER_EN_BIT); + } else { + val &= (~(1<regs->ROUTER_EN_BIT)); + } + } + if (state->regs->TAG_VLAN_BIT >= 0) { + if (state->vlan_enabled) { + val |= (1<regs->TAG_VLAN_BIT); + } else { + val &= (~(1<regs->TAG_VLAN_BIT)); + } + } + if (state->regs->NUMLAN_GROUPS_BIT >= 0) { + val &= (~((state->regs->NUMLAN_GROUPS_MAX-1)<regs->NUMLAN_GROUPS_BIT)); + if (state->num_vlans > state->regs->NUMLAN_GROUPS_MAX) { + val |= state->regs->NUMLAN_GROUPS_MAX << state->regs->NUMLAN_GROUPS_BIT; + } else if (state->num_vlans >= 1) { + val |= (state->num_vlans-1) << state->regs->NUMLAN_GROUPS_BIT; + } + } + return setPhy(state, state->regs->ROUTER_CONTROL_REG, val); +} + +/** Set all VLAN and port state. Usually you should call "correct_vlan_state" first. **/ +static int ip175c_set_state(struct ip17xx_state *state) +{ + int j; + int i; + SET_PORT_BITS(state, state->add_tag, + state->regs->ADD_TAG_REG, state->regs->ADD_TAG_BIT); + SET_PORT_BITS(state, state->remove_tag, + state->regs->REMOVE_TAG_REG, state->regs->REMOVE_TAG_BIT); + + if (REG_SUPP(state->regs->VLAN_LOOKUP_REG)) { + for (j=0; jregs->NUM_PORTS; j++) { + reg addr; + const bitnum *bit_lookup = (j%2==0)? + state->regs->VLAN_LOOKUP_EVEN_BIT: + state->regs->VLAN_LOOKUP_ODD_BIT; + + addr = state->regs->VLAN_LOOKUP_REG; + if (state->regs->SIMPLE_VLAN_REGISTERS) { + addr.m += j; + } else { + switch (j) { + case 0: + case 1: + break; + case 2: + case 3: + addr.m+=1; + break; + case 4: + addr.m+=2; + break; + case 5: + addr = state->regs->VLAN_LOOKUP_REG_5; + break; + default: + addr.m = -1; // shouldn't get here, but... + break; + } + } + //printf("shareports for %d is %02X\n",j,state->ports[j].shareports); + if (REG_SUPP(addr)) { + SET_PORT_BITS(state, state->ports[j].shareports, addr, bit_lookup); + } + } + } + if (REG_SUPP(state->regs->TAG_VLAN_MASK_REG)) { + for (j=0; jregs->TAG_VLAN_MASK_REG; + const bitnum *bit_lookup = (j%2==0)? + state->regs->TAG_VLAN_MASK_EVEN_BIT: + state->regs->TAG_VLAN_MASK_ODD_BIT; + unsigned int vlan_mask; + if (state->regs->SIMPLE_VLAN_REGISTERS) { + addr.m += j; + } else { + addr.m += j/2; + } + vlan_mask = state->vlans[j].ports; + SET_PORT_BITS(state, vlan_mask, addr, bit_lookup); + } + } + + for (i=0; iregs->VLAN_DEFAULT_TAG_REG[i])) { + int err = setPhy(state, state->regs->VLAN_DEFAULT_TAG_REG[i], + state->ports[i].pvid); + if (err < 0) { + return err; + } + } + } + + return ip175c_set_flags(state); +} + +/** + * Uses only the VLAN port mask and the add tag mask to generate the other fields: + * which ports are part of the same VLAN, removing vlan tags, and VLAN tag ids. + */ +static void ip175c_correct_vlan_state(struct ip17xx_state *state) +{ + int i, j; + state->num_vlans = 0; + for (i=0; ivlans[i].ports != 0) { + state->num_vlans = i+1; // Hack -- we need to store the "set" vlans somewhere... + } + } + + for (i=0; iregs->NUM_PORTS; i++) { + unsigned int portmask = (1<vlan_enabled) { + // Share with everybody! + state->ports[i].shareports = (1<regs->NUM_PORTS)-1; + continue; + } + state->ports[i].shareports = portmask; + for (j=0; jvlans[j].ports & portmask) + state->ports[i].shareports |= state->vlans[j].ports; + } + } +} + +static int ip175c_update_state(struct ip17xx_state *state) +{ + ip175c_correct_vlan_state(state); + return ip175c_set_state(state); +} + +static int ip175c_set_vlan_mode(struct ip17xx_state *state) +{ + return ip175c_update_state(state); +} + +static int ip175c_reset(struct ip17xx_state *state) +{ + int err; + + if (REG_SUPP(state->regs->MODE_REG)) { + err = setPhy(state, state->regs->MODE_REG, state->regs->MODE_VAL); + if (err < 0) + return err; + err = getPhy(state, state->regs->MODE_REG); + if (err < 0) + return err; + } + + return ip175c_update_state(state); +} + +/*** Low-level functions for IP175D ***/ + +static int ip175d_update_state(struct ip17xx_state *state) +{ + unsigned int filter_mask = 0; + unsigned int ports[16], add[16], rem[16]; + int i, j; + int err = 0; + + for (i = 0; i < 16; i++) { + ports[i] = 0; + add[i] = 0; + rem[i] = 0; + if (!state->vlan_enabled) { + err |= ip_phy_write(state, 22, 14+i, i+1); // default tags + ports[i] = 0x3f; + continue; + } + if (!state->vlans[i].tag) { + // Reset the filter + err |= ip_phy_write(state, 22, 14+i, 0); // tag + continue; + } + filter_mask |= 1 << i; + err |= ip_phy_write(state, 22, 14+i, state->vlans[i].tag); + ports[i] = state->vlans[i].ports; + for (j = 0; j < 6; j++) { + if (ports[i] & (1 << j)) { + if (state->add_tag & (1 << j)) + add[i] |= 1 << j; + if (state->remove_tag & (1 << j)) + rem[i] |= 1 << j; + } + } + } + + // Port masks, tag adds and removals + for (i = 0; i < 8; i++) { + err |= ip_phy_write(state, 23, i, ports[2*i] | (ports[2*i+1] << 8)); + err |= ip_phy_write(state, 23, 8+i, add[2*i] | (add[2*i+1] << 8)); + err |= ip_phy_write(state, 23, 16+i, rem[2*i] | (rem[2*i+1] << 8)); + } + err |= ip_phy_write(state, 22, 10, filter_mask); + + // Default VLAN tag for each port + for (i = 0; i < 6; i++) + err |= ip_phy_write(state, 22, 4+i, state->vlans[state->ports[i].pvid].tag); + + return (err ? -EIO : 0); +} + +static int ip175d_set_vlan_mode(struct ip17xx_state *state) +{ + int i; + int err = 0; + + if (state->vlan_enabled) { + // VLAN classification rules: tag-based VLANs, use VID to classify, + // drop packets that cannot be classified. + err |= ip_phy_write_masked(state, 22, 0, 0x3fff, 0x003f); + + // Ingress rules: CFI=1 dropped, null VID is untagged, VID=1 passed, + // VID=0xfff discarded, admin both tagged and untagged, ingress + // filters enabled. + err |= ip_phy_write_masked(state, 22, 1, 0x0fff, 0x0c3f); + + // Egress rules: IGMP processing off, keep VLAN header off + err |= ip_phy_write_masked(state, 22, 2, 0x0fff, 0x0000); + } else { + // VLAN classification rules: everything off & clear table + err |= ip_phy_write_masked(state, 22, 0, 0xbfff, 0x8000); + + // Ingress and egress rules: set to defaults + err |= ip_phy_write_masked(state, 22, 1, 0x0fff, 0x0c3f); + err |= ip_phy_write_masked(state, 22, 2, 0x0fff, 0x0000); + } + + // Reset default VLAN for each port to 0 + for (i = 0; i < 6; i++) + state->ports[i].pvid = 0; + + err |= ip175d_update_state(state); + + return (err ? -EIO : 0); +} + +static int ip175d_reset(struct ip17xx_state *state) +{ + int err = 0; + + // Disable the special tagging mode + err |= ip_phy_write_masked(state, 21, 22, 0x0003, 0x0000); + + // Set 802.1q protocol type + err |= ip_phy_write(state, 22, 3, 0x8100); + + state->vlan_enabled = 0; + err |= ip175d_set_vlan_mode(state); + + return (err ? -EIO : 0); +} + +/*** High-level functions ***/ + +static int ip17xx_get_enable_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + + val->value.i = state->vlan_enabled; + return 0; +} + +static void ip17xx_reset_vlan_config(struct ip17xx_state *state) +{ + int i; + + state->remove_tag = (state->vlan_enabled ? ((1<regs->NUM_PORTS)-1) : 0x0000); + state->add_tag = 0x0000; + for (i = 0; i < MAX_VLANS; i++) { + state->vlans[i].ports = 0x0000; + state->vlans[i].tag = (i ? i : 16); + } + for (i = 0; i < MAX_PORTS; i++) + state->ports[i].pvid = 0; +} + +static int ip17xx_set_enable_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int enable; + + enable = val->value.i; + if (state->vlan_enabled == enable) { + // Do not change any state. + return 0; + } + state->vlan_enabled = enable; + + // Otherwise, if we are switching state, set fields to a known default. + ip17xx_reset_vlan_config(state); + + return state->regs->set_vlan_mode(state); +} + +static int ip17xx_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int b; + int ind; + unsigned int ports; + + if (val->port_vlan >= dev->vlans || val->port_vlan < 0) + return -EINVAL; + + ports = state->vlans[val->port_vlan].ports; + b = 0; + ind = 0; + while (b < MAX_PORTS) { + if (ports&1) { + int istagged = ((state->add_tag >> b) & 1); + val->value.ports[ind].id = b; + val->value.ports[ind].flags = (istagged << SWITCH_PORT_FLAG_TAGGED); + ind++; + } + b++; + ports >>= 1; + } + val->len = ind; + + return 0; +} + +static int ip17xx_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int i; + + if (val->port_vlan >= dev->vlans || val->port_vlan < 0) + return -EINVAL; + + state->vlans[val->port_vlan].ports = 0; + for (i = 0; i < val->len; i++) { + unsigned int bitmask = (1<value.ports[i].id); + state->vlans[val->port_vlan].ports |= bitmask; + if (val->value.ports[i].flags & (1<add_tag |= bitmask; + state->remove_tag &= (~bitmask); + } else { + state->add_tag &= (~bitmask); + state->remove_tag |= bitmask; + } + } + + return state->regs->update_state(state); +} + +static int ip17xx_apply(struct switch_dev *dev) +{ + struct ip17xx_state *state = get_state(dev); + + if (REG_SUPP(state->regs->MII_REGISTER_EN)) { + int val = getPhy(state, state->regs->MII_REGISTER_EN); + if (val < 0) { + return val; + } + val |= (1<regs->MII_REGISTER_EN_BIT); + return setPhy(state, state->regs->MII_REGISTER_EN, val); + } + return 0; +} + +static int ip17xx_reset(struct switch_dev *dev) +{ + struct ip17xx_state *state = get_state(dev); + int i, err; + + if (REG_SUPP(state->regs->RESET_REG)) { + err = setPhy(state, state->regs->RESET_REG, state->regs->RESET_VAL); + if (err < 0) + return err; + err = getPhy(state, state->regs->RESET_REG); + + /* + * Data sheet specifies reset period to be 2 msec. + * (I don't see any mention of the 2ms delay in the IP178C spec, only + * in IP175C, but it can't hurt.) + */ + mdelay(2); + } + + /* reset switch ports */ + for (i = 0; i < state->regs->NUM_PORTS-1; i++) { + err = ip_phy_write(state, i, MII_BMCR, BMCR_RESET); + if (err < 0) + return err; + } + + state->router_mode = 0; + state->vlan_enabled = 0; + ip17xx_reset_vlan_config(state); + + return state->regs->reset(state); +} + +static int ip17xx_get_tagged(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + + if (state->add_tag & (1<port_vlan)) { + if (state->remove_tag & (1<port_vlan)) + val->value.i = 3; // shouldn't ever happen. + else + val->value.i = 1; + } else { + if (state->remove_tag & (1<port_vlan)) + val->value.i = 0; + else + val->value.i = 2; + } + return 0; +} + +static int ip17xx_set_tagged(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + + state->add_tag &= ~(1<port_vlan); + state->remove_tag &= ~(1<port_vlan); + + if (val->value.i == 0) + state->remove_tag |= (1<port_vlan); + if (val->value.i == 1) + state->add_tag |= (1<port_vlan); + + return state->regs->update_state(state); +} + +/** Get the current phy address */ +static int ip17xx_get_phy(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + + val->value.i = state->proc_mii.p; + return 0; +} + +/** Set a new phy address for low level access to registers */ +static int ip17xx_set_phy(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int new_reg = val->value.i; + + if (new_reg < 0 || new_reg > 31) + state->proc_mii.p = (u16)-1; + else + state->proc_mii.p = (u16)new_reg; + return 0; +} + +/** Get the current register number */ +static int ip17xx_get_reg(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + + val->value.i = state->proc_mii.m; + return 0; +} + +/** Set a new register address for low level access to registers */ +static int ip17xx_set_reg(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int new_reg = val->value.i; + + if (new_reg < 0 || new_reg > 31) + state->proc_mii.m = (u16)-1; + else + state->proc_mii.m = (u16)new_reg; + return 0; +} + +/** Get the register content of state->proc_mii */ +static int ip17xx_get_val(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int retval = -EINVAL; + if (REG_SUPP(state->proc_mii)) + retval = getPhy(state, state->proc_mii); + + if (retval < 0) { + return retval; + } else { + val->value.i = retval; + return 0; + } +} + +/** Write a value to the register defined by phy/reg above */ +static int ip17xx_set_val(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int myval, err = -EINVAL; + + myval = val->value.i; + if (myval <= 0xffff && myval >= 0 && REG_SUPP(state->proc_mii)) { + err = setPhy(state, state->proc_mii, (u16)myval); + } + return err; +} + +static int ip17xx_read_name(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + val->value.s = state->regs->NAME; // Just a const pointer, won't be freed by swconfig. + return 0; +} + +static int ip17xx_get_tag(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int vlan = val->port_vlan; + + if (vlan < 0 || vlan >= MAX_VLANS) + return -EINVAL; + + val->value.i = state->vlans[vlan].tag; + return 0; +} + +static int ip17xx_set_tag(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int vlan = val->port_vlan; + int tag = val->value.i; + + if (vlan < 0 || vlan >= MAX_VLANS) + return -EINVAL; + + if (tag < 0 || tag > 4095) + return -EINVAL; + + state->vlans[vlan].tag = tag; + return state->regs->update_state(state); +} + +static int ip17xx_set_port_speed(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int nr = val->port_vlan; + int ctrl; + int autoneg; + int speed; + if (val->value.i == 100) { + speed = 1; + autoneg = 0; + } else if (val->value.i == 10) { + speed = 0; + autoneg = 0; + } else { + autoneg = 1; + speed = 1; + } + + /* Can't set speed for cpu port */ + if (nr == state->regs->CPU_PORT) + return -EINVAL; + + if (nr >= dev->ports || nr < 0) + return -EINVAL; + + ctrl = ip_phy_read(state, nr, 0); + if (ctrl < 0) + return -EIO; + + ctrl &= (~(1<<12)); + ctrl &= (~(1<<13)); + ctrl |= (autoneg<<12); + ctrl |= (speed<<13); + + return ip_phy_write(state, nr, 0, ctrl); +} + +static int ip17xx_get_port_speed(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int nr = val->port_vlan; + int speed, status; + + if (nr == state->regs->CPU_PORT) { + val->value.i = 100; + return 0; + } + + if (nr >= dev->ports || nr < 0) + return -EINVAL; + + status = ip_phy_read(state, nr, 1); + speed = ip_phy_read(state, nr, 18); + if (status < 0 || speed < 0) + return -EIO; + + if (status & 4) + val->value.i = ((speed & (1<<11)) ? 100 : 10); + else + val->value.i = 0; + + return 0; +} + +static int ip17xx_get_port_status(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct ip17xx_state *state = get_state(dev); + int ctrl, speed, status; + int nr = val->port_vlan; + int len; + char *buf = state->buf; // fixed-length at 80. + + if (nr == state->regs->CPU_PORT) { + sprintf(buf, "up, 100 Mbps, cpu port"); + val->value.s = buf; + return 0; + } + + if (nr >= dev->ports || nr < 0) + return -EINVAL; + + ctrl = ip_phy_read(state, nr, 0); + status = ip_phy_read(state, nr, 1); + speed = ip_phy_read(state, nr, 18); + if (ctrl < 0 || status < 0 || speed < 0) + return -EIO; + + if (status & 4) + len = sprintf(buf, "up, %d Mbps, %s duplex", + ((speed & (1<<11)) ? 100 : 10), + ((speed & (1<<10)) ? "full" : "half")); + else + len = sprintf(buf, "down"); + + if (ctrl & (1<<12)) { + len += sprintf(buf+len, ", auto-negotiate"); + if (!(status & (1<<5))) + len += sprintf(buf+len, " (in progress)"); + } else { + len += sprintf(buf+len, ", fixed speed (%d)", + ((ctrl & (1<<13)) ? 100 : 10)); + } + + buf[len] = '\0'; + val->value.s = buf; + return 0; +} + +static int ip17xx_get_pvid(struct switch_dev *dev, int port, int *val) +{ + struct ip17xx_state *state = get_state(dev); + + *val = state->ports[port].pvid; + return 0; +} + +static int ip17xx_set_pvid(struct switch_dev *dev, int port, int val) +{ + struct ip17xx_state *state = get_state(dev); + + if (val < 0 || val >= MAX_VLANS) + return -EINVAL; + + state->ports[port].pvid = val; + return state->regs->update_state(state); +} + + +enum Ports { + IP17XX_PORT_STATUS, + IP17XX_PORT_LINK, + IP17XX_PORT_TAGGED, + IP17XX_PORT_PVID, +}; + +enum Globals { + IP17XX_ENABLE_VLAN, + IP17XX_GET_NAME, + IP17XX_REGISTER_PHY, + IP17XX_REGISTER_MII, + IP17XX_REGISTER_VALUE, + IP17XX_REGISTER_ERRNO, +}; + +enum Vlans { + IP17XX_VLAN_TAG, +}; + +static const struct switch_attr ip17xx_global[] = { + [IP17XX_ENABLE_VLAN] = { + .id = IP17XX_ENABLE_VLAN, + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Flag to enable or disable VLANs and tagging", + .get = ip17xx_get_enable_vlan, + .set = ip17xx_set_enable_vlan, + }, + [IP17XX_GET_NAME] = { + .id = IP17XX_GET_NAME, + .type = SWITCH_TYPE_STRING, + .description = "Returns the type of IC+ chip.", + .name = "name", + .get = ip17xx_read_name, + .set = NULL, + }, + /* jal: added for low level debugging etc. */ + [IP17XX_REGISTER_PHY] = { + .id = IP17XX_REGISTER_PHY, + .type = SWITCH_TYPE_INT, + .description = "Direct register access: set PHY (0-4, or 29,30,31)", + .name = "phy", + .get = ip17xx_get_phy, + .set = ip17xx_set_phy, + }, + [IP17XX_REGISTER_MII] = { + .id = IP17XX_REGISTER_MII, + .type = SWITCH_TYPE_INT, + .description = "Direct register access: set MII register number (0-31)", + .name = "reg", + .get = ip17xx_get_reg, + .set = ip17xx_set_reg, + }, + [IP17XX_REGISTER_VALUE] = { + .id = IP17XX_REGISTER_VALUE, + .type = SWITCH_TYPE_INT, + .description = "Direct register access: read/write to register (0-65535)", + .name = "val", + .get = ip17xx_get_val, + .set = ip17xx_set_val, + }, +}; + +static const struct switch_attr ip17xx_vlan[] = { + [IP17XX_VLAN_TAG] = { + .id = IP17XX_VLAN_TAG, + .type = SWITCH_TYPE_INT, + .description = "VLAN ID (0-4095) [IP175D only]", + .name = "vid", + .get = ip17xx_get_tag, + .set = ip17xx_set_tag, + } +}; + +static const struct switch_attr ip17xx_port[] = { + [IP17XX_PORT_STATUS] = { + .id = IP17XX_PORT_STATUS, + .type = SWITCH_TYPE_STRING, + .description = "Returns Detailed port status", + .name = "status", + .get = ip17xx_get_port_status, + .set = NULL, + }, + [IP17XX_PORT_LINK] = { + .id = IP17XX_PORT_LINK, + .type = SWITCH_TYPE_INT, + .description = "Link speed. Can write 0 for auto-negotiate, or 10 or 100", + .name = "link", + .get = ip17xx_get_port_speed, + .set = ip17xx_set_port_speed, + }, + [IP17XX_PORT_TAGGED] = { + .id = IP17XX_PORT_LINK, + .type = SWITCH_TYPE_INT, + .description = "0 = untag, 1 = add tags, 2 = do not alter (This value is reset if vlans are altered)", + .name = "tagged", + .get = ip17xx_get_tagged, + .set = ip17xx_set_tagged, + }, +}; + +static const struct switch_dev_ops ip17xx_ops = { + .attr_global = { + .attr = ip17xx_global, + .n_attr = ARRAY_SIZE(ip17xx_global), + }, + .attr_port = { + .attr = ip17xx_port, + .n_attr = ARRAY_SIZE(ip17xx_port), + }, + .attr_vlan = { + .attr = ip17xx_vlan, + .n_attr = ARRAY_SIZE(ip17xx_vlan), + }, + + .get_port_pvid = ip17xx_get_pvid, + .set_port_pvid = ip17xx_set_pvid, + .get_vlan_ports = ip17xx_get_ports, + .set_vlan_ports = ip17xx_set_ports, + .apply_config = ip17xx_apply, + .reset_switch = ip17xx_reset, +}; + +static int ip17xx_probe(struct phy_device *pdev) +{ + struct ip17xx_state *state; + struct switch_dev *dev; + int err; + + /* We only attach to PHY 0, but use all available PHYs */ + if (pdev->addr != 0) + return -ENODEV; + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return -ENOMEM; + + dev = &state->dev; + + pdev->priv = state; + state->mii_bus = pdev->bus; + + err = get_model(state); + if (err < 0) + goto error; + + dev->vlans = MAX_VLANS; + dev->cpu_port = state->regs->CPU_PORT; + dev->ports = state->regs->NUM_PORTS; + dev->name = state->regs->NAME; + dev->ops = &ip17xx_ops; + + pr_info("IP17xx: Found %s at %s\n", dev->name, dev_name(&pdev->dev)); + return 0; + +error: + kfree(state); + return err; +} + +static int ip17xx_config_init(struct phy_device *pdev) +{ + struct ip17xx_state *state = pdev->priv; + struct net_device *dev = pdev->attached_dev; + int err; + + err = register_switch(&state->dev, dev); + if (err < 0) + return err; + + state->registered = true; + ip17xx_reset(&state->dev); + return 0; +} + +static void ip17xx_remove(struct phy_device *pdev) +{ + struct ip17xx_state *state = pdev->priv; + + if (state->registered) + unregister_switch(&state->dev); + kfree(state); +} + +static int ip17xx_config_aneg(struct phy_device *pdev) +{ + return 0; +} + +static int ip17xx_aneg_done(struct phy_device *pdev) +{ + return BMSR_ANEGCOMPLETE; +} + +static int ip17xx_update_link(struct phy_device *pdev) +{ + pdev->link = 1; + return 0; +} + +static int ip17xx_read_status(struct phy_device *pdev) +{ + pdev->speed = SPEED_100; + pdev->duplex = DUPLEX_FULL; + pdev->pause = pdev->asym_pause = 0; + pdev->link = 1; + + return 0; +} + +static struct phy_driver ip17xx_driver = { + .name = "IC+ IP17xx", + .phy_id = 0x02430c00, + .phy_id_mask = 0x0ffffc00, + .features = PHY_BASIC_FEATURES, + .probe = ip17xx_probe, + .remove = ip17xx_remove, + .config_init = ip17xx_config_init, + .config_aneg = ip17xx_config_aneg, + .aneg_done = ip17xx_aneg_done, + .update_link = ip17xx_update_link, + .read_status = ip17xx_read_status, + .driver = { .owner = THIS_MODULE }, +}; + +static struct phy_driver ip175a_driver = { + .name = "IC+ IP175A", + .phy_id = 0x02430c50, + .phy_id_mask = 0x0ffffff0, + .features = PHY_BASIC_FEATURES, + .probe = ip17xx_probe, + .remove = ip17xx_remove, + .config_init = ip17xx_config_init, + .config_aneg = ip17xx_config_aneg, + .aneg_done = ip17xx_aneg_done, + .update_link = ip17xx_update_link, + .read_status = ip17xx_read_status, + .driver = { .owner = THIS_MODULE }, +}; + + +int __init ip17xx_init(void) +{ + int ret; + + ret = phy_driver_register(&ip175a_driver); + if (ret < 0) + return ret; + + return phy_driver_register(&ip17xx_driver); +} + +void __exit ip17xx_exit(void) +{ + phy_driver_unregister(&ip17xx_driver); + phy_driver_unregister(&ip175a_driver); +} + +MODULE_AUTHOR("Patrick Horn "); +MODULE_AUTHOR("Felix Fietkau "); +MODULE_AUTHOR("Martin Mares "); +MODULE_LICENSE("GPL"); + +module_init(ip17xx_init); +module_exit(ip17xx_exit); diff --git a/target/linux/generic/files/drivers/net/phy/mvsw61xx.c b/target/linux/generic/files/drivers/net/phy/mvsw61xx.c new file mode 100644 index 0000000..f879056 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/mvsw61xx.c @@ -0,0 +1,854 @@ +/* + * Marvell 88E61xx switch driver + * + * Copyright (c) 2014 Claudio Leite + * Copyright (c) 2014 Nikita Nazarenko + * + * Based on code (c) 2008 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License v2 as published by the + * Free Software Foundation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mvsw61xx.h" + +MODULE_DESCRIPTION("Marvell 88E61xx Switch driver"); +MODULE_AUTHOR("Claudio Leite "); +MODULE_AUTHOR("Nikita Nazarenko "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:mvsw61xx"); + +/* + * Register access is done through direct or indirect addressing, + * depending on how the switch is physically connected. + * + * Direct addressing: all port and global registers directly + * accessible via an address/register pair + * + * Indirect addressing: switch is mapped at a single address, + * port and global registers accessible via a single command/data + * register pair + */ + +static int +mvsw61xx_wait_mask_raw(struct mii_bus *bus, int addr, + int reg, u16 mask, u16 val) +{ + int i = 100; + u16 r; + + do { + r = bus->read(bus, addr, reg); + if ((r & mask) == val) + return 0; + } while (--i > 0); + + return -ETIMEDOUT; +} + +static u16 +r16(struct mii_bus *bus, bool indirect, int base_addr, int addr, int reg) +{ + u16 ind_addr; + + if (!indirect) + return bus->read(bus, addr, reg); + + /* Indirect read: First, make sure switch is free */ + mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD, + MV_INDIRECT_INPROGRESS, 0); + + /* Load address and request read */ + ind_addr = MV_INDIRECT_READ | (addr << MV_INDIRECT_ADDR_S) | reg; + bus->write(bus, base_addr, MV_INDIRECT_REG_CMD, + ind_addr); + + /* Wait until it's ready */ + mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD, + MV_INDIRECT_INPROGRESS, 0); + + /* Read the requested data */ + return bus->read(bus, base_addr, MV_INDIRECT_REG_DATA); +} + +static void +w16(struct mii_bus *bus, bool indirect, int base_addr, int addr, + int reg, u16 val) +{ + u16 ind_addr; + + if (!indirect) { + bus->write(bus, addr, reg, val); + return; + } + + /* Indirect write: First, make sure switch is free */ + mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD, + MV_INDIRECT_INPROGRESS, 0); + + /* Load the data to be written */ + bus->write(bus, base_addr, MV_INDIRECT_REG_DATA, val); + + /* Wait again for switch to be free */ + mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD, + MV_INDIRECT_INPROGRESS, 0); + + /* Load address, and issue write command */ + ind_addr = MV_INDIRECT_WRITE | (addr << MV_INDIRECT_ADDR_S) | reg; + bus->write(bus, base_addr, MV_INDIRECT_REG_CMD, + ind_addr); +} + +/* swconfig support */ + +static inline u16 +sr16(struct switch_dev *dev, int addr, int reg) +{ + struct mvsw61xx_state *state = get_state(dev); + + return r16(state->bus, state->is_indirect, state->base_addr, addr, reg); +} + +static inline void +sw16(struct switch_dev *dev, int addr, int reg, u16 val) +{ + struct mvsw61xx_state *state = get_state(dev); + + w16(state->bus, state->is_indirect, state->base_addr, addr, reg, val); +} + +static int +mvsw61xx_wait_mask_s(struct switch_dev *dev, int addr, + int reg, u16 mask, u16 val) +{ + int i = 100; + u16 r; + + do { + r = sr16(dev, addr, reg) & mask; + if (r == val) + return 0; + } while (--i > 0); + + return -ETIMEDOUT; +} + +static int +mvsw61xx_get_port_mask(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + char *buf = state->buf; + int port, len, i; + u16 reg; + + port = val->port_vlan; + reg = sr16(dev, MV_PORTREG(VLANMAP, port)) & MV_PORTS_MASK; + + len = sprintf(buf, "0x%04x: ", reg); + + for (i = 0; i < MV_PORTS; i++) { + if (reg & (1 << i)) + len += sprintf(buf + len, "%d ", i); + else if (i == port) + len += sprintf(buf + len, "(%d) ", i); + } + + val->value.s = buf; + + return 0; +} + +static int +mvsw61xx_get_port_qmode(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + + val->value.i = state->ports[val->port_vlan].qmode; + + return 0; +} + +static int +mvsw61xx_set_port_qmode(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + + state->ports[val->port_vlan].qmode = val->value.i; + + return 0; +} + +static int +mvsw61xx_get_port_pvid(struct switch_dev *dev, int port, int *val) +{ + struct mvsw61xx_state *state = get_state(dev); + + *val = state->ports[port].pvid; + + return 0; +} + +static int +mvsw61xx_set_port_pvid(struct switch_dev *dev, int port, int val) +{ + struct mvsw61xx_state *state = get_state(dev); + + if (val < 0 || val >= MV_VLANS) + return -EINVAL; + + state->ports[port].pvid = (u16)val; + + return 0; +} + +static int +mvsw61xx_get_port_link(struct switch_dev *dev, int port, + struct switch_port_link *link) +{ + u16 status, speed; + + status = sr16(dev, MV_PORTREG(STATUS, port)); + + link->link = status & MV_PORT_STATUS_LINK; + if (!link->link) + return 0; + + link->duplex = status & MV_PORT_STATUS_FDX; + + speed = (status & MV_PORT_STATUS_SPEED_MASK) >> + MV_PORT_STATUS_SPEED_SHIFT; + + switch (speed) { + case MV_PORT_STATUS_SPEED_10: + link->speed = SWITCH_PORT_SPEED_10; + break; + case MV_PORT_STATUS_SPEED_100: + link->speed = SWITCH_PORT_SPEED_100; + break; + case MV_PORT_STATUS_SPEED_1000: + link->speed = SWITCH_PORT_SPEED_1000; + break; + } + + return 0; +} + +static int mvsw61xx_get_vlan_ports(struct switch_dev *dev, + struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + int i, j, mode, vno; + + vno = val->port_vlan; + + if (vno <= 0 || vno >= dev->vlans) + return -EINVAL; + + for (i = 0, j = 0; i < dev->ports; i++) { + if (state->vlans[vno].mask & (1 << i)) { + val->value.ports[j].id = i; + + mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf; + if (mode == MV_VTUCTL_EGRESS_TAGGED) + val->value.ports[j].flags = + (1 << SWITCH_PORT_FLAG_TAGGED); + else + val->value.ports[j].flags = 0; + + j++; + } + } + + val->len = j; + + return 0; +} + +static int mvsw61xx_set_vlan_ports(struct switch_dev *dev, + struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + int i, mode, pno, vno; + + vno = val->port_vlan; + + if (vno <= 0 || vno >= dev->vlans) + return -EINVAL; + + state->vlans[vno].mask = 0; + state->vlans[vno].port_mode = 0; + state->vlans[vno].port_sstate = 0; + + if(state->vlans[vno].vid == 0) + state->vlans[vno].vid = vno; + + for (i = 0; i < val->len; i++) { + pno = val->value.ports[i].id; + + state->vlans[vno].mask |= (1 << pno); + if (val->value.ports[i].flags & + (1 << SWITCH_PORT_FLAG_TAGGED)) + mode = MV_VTUCTL_EGRESS_TAGGED; + else + mode = MV_VTUCTL_EGRESS_UNTAGGED; + + state->vlans[vno].port_mode |= mode << (pno * 4); + state->vlans[vno].port_sstate |= + MV_STUCTL_STATE_FORWARDING << (pno * 4 + 2); + } + + /* + * DISCARD is nonzero, so it must be explicitly + * set on ports not in the VLAN. + */ + for (i = 0; i < dev->ports; i++) + if (!(state->vlans[vno].mask & (1 << i))) + state->vlans[vno].port_mode |= + MV_VTUCTL_DISCARD << (i * 4); + + return 0; +} + +static int mvsw61xx_get_vlan_port_based(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + int vno = val->port_vlan; + + if (vno <= 0 || vno >= dev->vlans) + return -EINVAL; + + if (state->vlans[vno].port_based) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + +static int mvsw61xx_set_vlan_port_based(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + int vno = val->port_vlan; + + if (vno <= 0 || vno >= dev->vlans) + return -EINVAL; + + if (val->value.i == 1) + state->vlans[vno].port_based = true; + else + state->vlans[vno].port_based = false; + + return 0; +} + +static int mvsw61xx_get_vid(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + int vno = val->port_vlan; + + if (vno <= 0 || vno >= dev->vlans) + return -EINVAL; + + val->value.i = state->vlans[vno].vid; + + return 0; +} + +static int mvsw61xx_set_vid(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + int vno = val->port_vlan; + + if (vno <= 0 || vno >= dev->vlans) + return -EINVAL; + + state->vlans[vno].vid = val->value.i; + + return 0; +} + +static int mvsw61xx_get_enable_vlan(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + + val->value.i = state->vlan_enabled; + + return 0; +} + +static int mvsw61xx_set_enable_vlan(struct switch_dev *dev, + const struct switch_attr *attr, struct switch_val *val) +{ + struct mvsw61xx_state *state = get_state(dev); + + state->vlan_enabled = val->value.i; + + return 0; +} + +static int mvsw61xx_vtu_program(struct switch_dev *dev) +{ + struct mvsw61xx_state *state = get_state(dev); + u16 v1, v2, s1, s2; + int i; + + /* Flush */ + mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP), + MV_VTUOP_INPROGRESS, 0); + sw16(dev, MV_GLOBALREG(VTU_OP), + MV_VTUOP_INPROGRESS | MV_VTUOP_PURGE); + + /* Write VLAN table */ + for (i = 1; i < dev->vlans; i++) { + if (state->vlans[i].mask == 0 || + state->vlans[i].vid == 0 || + state->vlans[i].port_based == true) + continue; + + mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP), + MV_VTUOP_INPROGRESS, 0); + + /* Write per-VLAN port state into STU */ + s1 = (u16) (state->vlans[i].port_sstate & 0xffff); + s2 = (u16) ((state->vlans[i].port_sstate >> 16) & 0xffff); + + sw16(dev, MV_GLOBALREG(VTU_VID), MV_VTU_VID_VALID); + sw16(dev, MV_GLOBALREG(VTU_SID), i); + sw16(dev, MV_GLOBALREG(VTU_DATA1), s1); + sw16(dev, MV_GLOBALREG(VTU_DATA2), s2); + sw16(dev, MV_GLOBALREG(VTU_DATA3), 0); + + sw16(dev, MV_GLOBALREG(VTU_OP), + MV_VTUOP_INPROGRESS | MV_VTUOP_STULOAD); + mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP), + MV_VTUOP_INPROGRESS, 0); + + /* Write VLAN information into VTU */ + v1 = (u16) (state->vlans[i].port_mode & 0xffff); + v2 = (u16) ((state->vlans[i].port_mode >> 16) & 0xffff); + + sw16(dev, MV_GLOBALREG(VTU_VID), + MV_VTU_VID_VALID | state->vlans[i].vid); + sw16(dev, MV_GLOBALREG(VTU_SID), i); + sw16(dev, MV_GLOBALREG(VTU_FID), i); + sw16(dev, MV_GLOBALREG(VTU_DATA1), v1); + sw16(dev, MV_GLOBALREG(VTU_DATA2), v2); + sw16(dev, MV_GLOBALREG(VTU_DATA3), 0); + + sw16(dev, MV_GLOBALREG(VTU_OP), + MV_VTUOP_INPROGRESS | MV_VTUOP_LOAD); + mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP), + MV_VTUOP_INPROGRESS, 0); + } + + return 0; +} + +static void mvsw61xx_vlan_port_config(struct switch_dev *dev, int vno) +{ + struct mvsw61xx_state *state = get_state(dev); + int i, mode; + + for (i = 0; i < dev->ports; i++) { + if (!(state->vlans[vno].mask & (1 << i))) + continue; + + mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf; + + if(mode != MV_VTUCTL_EGRESS_TAGGED) + state->ports[i].pvid = state->vlans[vno].vid; + + if (state->vlans[vno].port_based) { + state->ports[i].mask |= state->vlans[vno].mask; + state->ports[i].fdb = vno; + } + else + state->ports[i].qmode = MV_8021Q_MODE_SECURE; + } +} + +static int mvsw61xx_update_state(struct switch_dev *dev) +{ + struct mvsw61xx_state *state = get_state(dev); + int i; + u16 reg; + + if (!state->registered) + return -EINVAL; + + /* + * Set 802.1q-only mode if vlan_enabled is true. + * + * Without this, even if 802.1q is enabled for + * a port/VLAN, it still depends on the port-based + * VLAN mask being set. + * + * With this setting, port-based VLANs are still + * functional, provided the VID is not in the VTU. + */ + reg = sr16(dev, MV_GLOBAL2REG(SDET_POLARITY)); + + if (state->vlan_enabled) + reg |= MV_8021Q_VLAN_ONLY; + else + reg &= ~MV_8021Q_VLAN_ONLY; + + sw16(dev, MV_GLOBAL2REG(SDET_POLARITY), reg); + + /* + * Set port-based VLAN masks on each port + * based only on VLAN definitions known to + * the driver (i.e. in state). + * + * This means any pre-existing port mapping is + * wiped out once our driver is initialized. + */ + for (i = 0; i < dev->ports; i++) { + state->ports[i].mask = 0; + state->ports[i].qmode = MV_8021Q_MODE_DISABLE; + } + + for (i = 0; i < dev->vlans; i++) + mvsw61xx_vlan_port_config(dev, i); + + for (i = 0; i < dev->ports; i++) { + reg = sr16(dev, MV_PORTREG(VLANID, i)) & ~MV_PVID_MASK; + reg |= state->ports[i].pvid; + sw16(dev, MV_PORTREG(VLANID, i), reg); + + state->ports[i].mask &= ~(1 << i); + + /* set default forwarding DB number and port mask */ + reg = sr16(dev, MV_PORTREG(CONTROL1, i)) & ~MV_FDB_HI_MASK; + reg |= (state->ports[i].fdb >> MV_FDB_HI_SHIFT) & + MV_FDB_HI_MASK; + sw16(dev, MV_PORTREG(CONTROL1, i), reg); + + reg = ((state->ports[i].fdb & 0xf) << MV_FDB_LO_SHIFT) | + state->ports[i].mask; + sw16(dev, MV_PORTREG(VLANMAP, i), reg); + + reg = sr16(dev, MV_PORTREG(CONTROL2, i)) & + ~MV_8021Q_MODE_MASK; + reg |= state->ports[i].qmode << MV_8021Q_MODE_SHIFT; + sw16(dev, MV_PORTREG(CONTROL2, i), reg); + } + + mvsw61xx_vtu_program(dev); + + return 0; +} + +static int mvsw61xx_apply(struct switch_dev *dev) +{ + return mvsw61xx_update_state(dev); +} + +static int mvsw61xx_reset(struct switch_dev *dev) +{ + struct mvsw61xx_state *state = get_state(dev); + int i; + u16 reg; + + /* Disable all ports before reset */ + for (i = 0; i < dev->ports; i++) { + reg = sr16(dev, MV_PORTREG(CONTROL, i)) & + ~MV_PORTCTRL_FORWARDING; + sw16(dev, MV_PORTREG(CONTROL, i), reg); + } + + reg = sr16(dev, MV_GLOBALREG(CONTROL)) | MV_CONTROL_RESET; + + sw16(dev, MV_GLOBALREG(CONTROL), reg); + if (mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(CONTROL), + MV_CONTROL_RESET, 0) < 0) + return -ETIMEDOUT; + + for (i = 0; i < dev->ports; i++) { + state->ports[i].fdb = 0; + state->ports[i].qmode = 0; + state->ports[i].mask = 0; + state->ports[i].pvid = 0; + + /* Force flow control off */ + reg = sr16(dev, MV_PORTREG(PHYCTL, i)) & ~MV_PHYCTL_FC_MASK; + reg |= MV_PHYCTL_FC_DISABLE; + sw16(dev, MV_PORTREG(PHYCTL, i), reg); + + /* Set port association vector */ + sw16(dev, MV_PORTREG(ASSOC, i), (1 << i)); + } + + for (i = 0; i < dev->vlans; i++) { + state->vlans[i].port_based = false; + state->vlans[i].mask = 0; + state->vlans[i].vid = 0; + state->vlans[i].port_mode = 0; + state->vlans[i].port_sstate = 0; + } + + state->vlan_enabled = 0; + + mvsw61xx_update_state(dev); + + /* Re-enable ports */ + for (i = 0; i < dev->ports; i++) { + reg = sr16(dev, MV_PORTREG(CONTROL, i)) | + MV_PORTCTRL_FORWARDING; + sw16(dev, MV_PORTREG(CONTROL, i), reg); + } + + return 0; +} + +enum { + MVSW61XX_ENABLE_VLAN, +}; + +enum { + MVSW61XX_VLAN_PORT_BASED, + MVSW61XX_VLAN_ID, +}; + +enum { + MVSW61XX_PORT_MASK, + MVSW61XX_PORT_QMODE, +}; + +static const struct switch_attr mvsw61xx_global[] = { + [MVSW61XX_ENABLE_VLAN] = { + .id = MVSW61XX_ENABLE_VLAN, + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable 802.1q VLAN support", + .get = mvsw61xx_get_enable_vlan, + .set = mvsw61xx_set_enable_vlan, + }, +}; + +static const struct switch_attr mvsw61xx_vlan[] = { + [MVSW61XX_VLAN_PORT_BASED] = { + .id = MVSW61XX_VLAN_PORT_BASED, + .type = SWITCH_TYPE_INT, + .name = "port_based", + .description = "Use port-based (non-802.1q) VLAN only", + .get = mvsw61xx_get_vlan_port_based, + .set = mvsw61xx_set_vlan_port_based, + }, + [MVSW61XX_VLAN_ID] = { + .id = MVSW61XX_VLAN_ID, + .type = SWITCH_TYPE_INT, + .name = "vid", + .description = "Get/set VLAN ID", + .get = mvsw61xx_get_vid, + .set = mvsw61xx_set_vid, + }, +}; + +static const struct switch_attr mvsw61xx_port[] = { + [MVSW61XX_PORT_MASK] = { + .id = MVSW61XX_PORT_MASK, + .type = SWITCH_TYPE_STRING, + .description = "Port-based VLAN mask", + .name = "mask", + .get = mvsw61xx_get_port_mask, + .set = NULL, + }, + [MVSW61XX_PORT_QMODE] = { + .id = MVSW61XX_PORT_QMODE, + .type = SWITCH_TYPE_INT, + .description = "802.1q mode: 0=off/1=fallback/2=check/3=secure", + .name = "qmode", + .get = mvsw61xx_get_port_qmode, + .set = mvsw61xx_set_port_qmode, + }, +}; + +static const struct switch_dev_ops mvsw61xx_ops = { + .attr_global = { + .attr = mvsw61xx_global, + .n_attr = ARRAY_SIZE(mvsw61xx_global), + }, + .attr_vlan = { + .attr = mvsw61xx_vlan, + .n_attr = ARRAY_SIZE(mvsw61xx_vlan), + }, + .attr_port = { + .attr = mvsw61xx_port, + .n_attr = ARRAY_SIZE(mvsw61xx_port), + }, + .get_port_link = mvsw61xx_get_port_link, + .get_port_pvid = mvsw61xx_get_port_pvid, + .set_port_pvid = mvsw61xx_set_port_pvid, + .get_vlan_ports = mvsw61xx_get_vlan_ports, + .set_vlan_ports = mvsw61xx_set_vlan_ports, + .apply_config = mvsw61xx_apply, + .reset_switch = mvsw61xx_reset, +}; + +/* end swconfig stuff */ + +static int mvsw61xx_probe(struct platform_device *pdev) +{ + struct mvsw61xx_state *state; + struct device_node *np = pdev->dev.of_node; + struct device_node *mdio; + char *model_str; + u32 val; + int err; + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return -ENOMEM; + + mdio = of_parse_phandle(np, "mii-bus", 0); + if (!mdio) { + dev_err(&pdev->dev, "Couldn't get MII bus handle\n"); + err = -ENODEV; + goto out_err; + } + + state->bus = of_mdio_find_bus(mdio); + if (!state->bus) { + dev_err(&pdev->dev, "Couldn't find MII bus from handle\n"); + err = -ENODEV; + goto out_err; + } + + state->is_indirect = of_property_read_bool(np, "is-indirect"); + + if (state->is_indirect) { + if (of_property_read_u32(np, "reg", &val)) { + dev_err(&pdev->dev, "Switch address not specified\n"); + err = -ENODEV; + goto out_err; + } + + state->base_addr = val; + } else { + state->base_addr = MV_BASE; + } + + state->model = r16(state->bus, state->is_indirect, state->base_addr, + MV_PORTREG(IDENT, 0)) & MV_IDENT_MASK; + + switch(state->model) { + case MV_IDENT_VALUE_6171: + model_str = MV_IDENT_STR_6171; + break; + case MV_IDENT_VALUE_6172: + model_str = MV_IDENT_STR_6172; + break; + case MV_IDENT_VALUE_6176: + model_str = MV_IDENT_STR_6176; + break; + default: + dev_err(&pdev->dev, "No compatible switch found at 0x%02x\n", + state->base_addr); + err = -ENODEV; + goto out_err; + } + + platform_set_drvdata(pdev, state); + dev_info(&pdev->dev, "Found %s at %s:%02x\n", model_str, + state->bus->id, state->base_addr); + + dev_info(&pdev->dev, "Using %sdirect addressing\n", + (state->is_indirect ? "in" : "")); + + if (of_property_read_u32(np, "cpu-port-0", &val)) { + dev_err(&pdev->dev, "CPU port not set\n"); + err = -ENODEV; + goto out_err; + } + + state->cpu_port0 = val; + + if (!of_property_read_u32(np, "cpu-port-1", &val)) + state->cpu_port1 = val; + else + state->cpu_port1 = -1; + + state->dev.vlans = MV_VLANS; + state->dev.cpu_port = state->cpu_port0; + state->dev.ports = MV_PORTS; + state->dev.name = model_str; + state->dev.ops = &mvsw61xx_ops; + state->dev.alias = dev_name(&pdev->dev); + + err = register_switch(&state->dev, NULL); + if (err < 0) + goto out_err; + + state->registered = true; + + return 0; +out_err: + kfree(state); + return err; +} + +static int +mvsw61xx_remove(struct platform_device *pdev) +{ + struct mvsw61xx_state *state = platform_get_drvdata(pdev); + + if (state->registered) + unregister_switch(&state->dev); + + kfree(state); + + return 0; +} + +static const struct of_device_id mvsw61xx_match[] = { + { .compatible = "marvell,88e6171" }, + { .compatible = "marvell,88e6172" }, + { .compatible = "marvell,88e6176" }, + { } +}; +MODULE_DEVICE_TABLE(of, mvsw61xx_match); + +static struct platform_driver mvsw61xx_driver = { + .probe = mvsw61xx_probe, + .remove = mvsw61xx_remove, + .driver = { + .name = "mvsw61xx", + .of_match_table = of_match_ptr(mvsw61xx_match), + .owner = THIS_MODULE, + }, +}; + +static int __init mvsw61xx_module_init(void) +{ + return platform_driver_register(&mvsw61xx_driver); +} +late_initcall(mvsw61xx_module_init); + +static void __exit mvsw61xx_module_exit(void) +{ + platform_driver_unregister(&mvsw61xx_driver); +} +module_exit(mvsw61xx_module_exit); diff --git a/target/linux/generic/files/drivers/net/phy/mvsw61xx.h b/target/linux/generic/files/drivers/net/phy/mvsw61xx.h new file mode 100644 index 0000000..dbc6c92 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/mvsw61xx.h @@ -0,0 +1,266 @@ +/* + * Marvell 88E61xx switch driver + * + * Copyright (c) 2014 Claudio Leite + * Copyright (c) 2014 Nikita Nazarenko + * + * Based on code (c) 2008 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License v2 as published by the + * Free Software Foundation + */ + +#ifndef __MVSW61XX_H +#define __MVSW61XX_H + +#define MV_PORTS 7 +#define MV_PORTS_MASK ((1 << MV_PORTS) - 1) + +#define MV_BASE 0x10 + +#define MV_SWITCHPORT_BASE 0x10 +#define MV_SWITCHPORT(_n) (MV_SWITCHPORT_BASE + (_n)) +#define MV_SWITCHREGS (MV_BASE + 0xb) + +#define MV_VLANS 64 + +enum { + MV_PORT_STATUS = 0x00, + MV_PORT_PHYCTL = 0x01, + MV_PORT_JAMCTL = 0x02, + MV_PORT_IDENT = 0x03, + MV_PORT_CONTROL = 0x04, + MV_PORT_CONTROL1 = 0x05, + MV_PORT_VLANMAP = 0x06, + MV_PORT_VLANID = 0x07, + MV_PORT_CONTROL2 = 0x08, + MV_PORT_ASSOC = 0x0b, + MV_PORT_RX_DISCARD_LOW = 0x10, + MV_PORT_RX_DISCARD_HIGH = 0x11, + MV_PORT_IN_FILTERED = 0x12, + MV_PORT_OUT_ACCEPTED = 0x13, +}; +#define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type + +enum { + MV_PORT_STATUS_FDX = (1 << 10), + MV_PORT_STATUS_LINK = (1 << 11), +}; + +enum { + MV_PORT_STATUS_SPEED_10 = 0x00, + MV_PORT_STATUS_SPEED_100 = 0x01, + MV_PORT_STATUS_SPEED_1000 = 0x02, +}; +#define MV_PORT_STATUS_SPEED_SHIFT 8 +#define MV_PORT_STATUS_SPEED_MASK (3 << 8) + +enum { + MV_PORTCTRL_DISABLED = (0 << 0), + MV_PORTCTRL_BLOCKING = (1 << 0), + MV_PORTCTRL_LEARNING = (2 << 0), + MV_PORTCTRL_FORWARDING = (3 << 0), + MV_PORTCTRL_VLANTUN = (1 << 7), + MV_PORTCTRL_EGRESS = (1 << 12), +}; + +#define MV_PHYCTL_FC_MASK (3 << 6) + +enum { + MV_PHYCTL_FC_ENABLE = (3 << 6), + MV_PHYCTL_FC_DISABLE = (1 << 6), +}; + +enum { + MV_8021Q_EGRESS_UNMODIFIED = 0x00, + MV_8021Q_EGRESS_UNTAGGED = 0x01, + MV_8021Q_EGRESS_TAGGED = 0x02, + MV_8021Q_EGRESS_ADDTAG = 0x03, +}; + +#define MV_8021Q_MODE_SHIFT 10 +#define MV_8021Q_MODE_MASK (0x3 << MV_8021Q_MODE_SHIFT) + +enum { + MV_8021Q_MODE_DISABLE = 0x00, + MV_8021Q_MODE_FALLBACK = 0x01, + MV_8021Q_MODE_CHECK = 0x02, + MV_8021Q_MODE_SECURE = 0x03, +}; + +enum { + MV_8021Q_VLAN_ONLY = (1 << 15), +}; + +#define MV_PORTASSOC_MONITOR (1 << 15) + +enum { + MV_SWITCH_ATU_FID0 = 0x01, + MV_SWITCH_ATU_FID1 = 0x02, + MV_SWITCH_ATU_SID = 0x03, + MV_SWITCH_CTRL = 0x04, + MV_SWITCH_ATU_CTRL = 0x0a, + MV_SWITCH_ATU_OP = 0x0b, + MV_SWITCH_ATU_DATA = 0x0c, + MV_SWITCH_ATU_MAC0 = 0x0d, + MV_SWITCH_ATU_MAC1 = 0x0e, + MV_SWITCH_ATU_MAC2 = 0x0f, + MV_SWITCH_GLOBAL = 0x1b, + MV_SWITCH_GLOBAL2 = 0x1c, +}; +#define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type + +enum { + MV_SWITCHCTL_EEIE = (1 << 0), + MV_SWITCHCTL_PHYIE = (1 << 1), + MV_SWITCHCTL_ATUDONE = (1 << 2), + MV_SWITCHCTL_ATUIE = (1 << 3), + MV_SWITCHCTL_CTRMODE = (1 << 8), + MV_SWITCHCTL_RELOAD = (1 << 9), + MV_SWITCHCTL_MSIZE = (1 << 10), + MV_SWITCHCTL_DROP = (1 << 13), +}; + +enum { +#define MV_ATUCTL_AGETIME_MIN 16 +#define MV_ATUCTL_AGETIME_MAX 4080 +#define MV_ATUCTL_AGETIME(_n) ((((_n) / 16) & 0xff) << 4) + MV_ATUCTL_ATU_256 = (0 << 12), + MV_ATUCTL_ATU_512 = (1 << 12), + MV_ATUCTL_ATU_1K = (2 << 12), + MV_ATUCTL_ATUMASK = (3 << 12), + MV_ATUCTL_NO_LEARN = (1 << 14), + MV_ATUCTL_RESET = (1 << 15), +}; + +enum { +#define MV_ATUOP_DBNUM(_n) ((_n) & 0x0f) + MV_ATUOP_NOOP = (0 << 12), + MV_ATUOP_FLUSH_ALL = (1 << 12), + MV_ATUOP_FLUSH_U = (2 << 12), + MV_ATUOP_LOAD_DB = (3 << 12), + MV_ATUOP_GET_NEXT = (4 << 12), + MV_ATUOP_FLUSH_DB = (5 << 12), + MV_ATUOP_FLUSH_DB_UU = (6 << 12), + MV_ATUOP_INPROGRESS = (1 << 15), +}; + +enum { + MV_GLOBAL_STATUS = 0x00, + MV_GLOBAL_ATU_FID = 0x01, + MV_GLOBAL_VTU_FID = 0x02, + MV_GLOBAL_VTU_SID = 0x03, + MV_GLOBAL_CONTROL = 0x04, + MV_GLOBAL_VTU_OP = 0x05, + MV_GLOBAL_VTU_VID = 0x06, + MV_GLOBAL_VTU_DATA1 = 0x07, + MV_GLOBAL_VTU_DATA2 = 0x08, + MV_GLOBAL_VTU_DATA3 = 0x09, + MV_GLOBAL_CONTROL2 = 0x1c, +}; +#define MV_GLOBALREG(_type) MV_SWITCH_GLOBAL, MV_GLOBAL_##_type + +enum { + MV_GLOBAL2_SDET_POLARITY = 0x1d, +}; +#define MV_GLOBAL2REG(_type) MV_SWITCH_GLOBAL2, MV_GLOBAL2_##_type + +enum { + MV_VTU_VID_VALID = (1 << 12), +}; + +enum { + MV_VTUOP_PURGE = (1 << 12), + MV_VTUOP_LOAD = (3 << 12), + MV_VTUOP_INPROGRESS = (1 << 15), + MV_VTUOP_STULOAD = (5 << 12), + MV_VTUOP_VTU_GET_NEXT = (4 << 12), + MV_VTUOP_STU_GET_NEXT = (6 << 12), + MV_VTUOP_GET_VIOLATION = (7 << 12), +}; + +enum { + MV_CONTROL_RESET = (1 << 15), + MV_CONTROL_PPU_ENABLE = (1 << 14), +}; + +enum { + MV_VTUCTL_EGRESS_UNMODIFIED = (0 << 0), + MV_VTUCTL_EGRESS_UNTAGGED = (1 << 0), + MV_VTUCTL_EGRESS_TAGGED = (2 << 0), + MV_VTUCTL_DISCARD = (3 << 0), +}; + +enum { + MV_STUCTL_STATE_DISABLED = (0 << 0), + MV_STUCTL_STATE_BLOCKING = (1 << 0), + MV_STUCTL_STATE_LEARNING = (2 << 0), + MV_STUCTL_STATE_FORWARDING = (3 << 0), +}; + +enum { + MV_INDIRECT_REG_CMD = 0, + MV_INDIRECT_REG_DATA = 1, +}; + +enum { + MV_INDIRECT_INPROGRESS = 0x8000, + MV_INDIRECT_WRITE = 0x9400, + MV_INDIRECT_READ = 0x9800, +}; +#define MV_INDIRECT_ADDR_S 5 + +#define MV_IDENT_MASK 0xfff0 + +#define MV_IDENT_VALUE_6171 0x1710 +#define MV_IDENT_STR_6171 "MV88E6171" + +#define MV_IDENT_VALUE_6172 0x1720 +#define MV_IDENT_STR_6172 "MV88E6172" + +#define MV_IDENT_VALUE_6176 0x1760 +#define MV_IDENT_STR_6176 "MV88E6176" + +#define MV_PVID_MASK 0x0fff + +#define MV_FDB_HI_MASK 0x00ff +#define MV_FDB_LO_MASK 0xf000 +#define MV_FDB_HI_SHIFT 4 +#define MV_FDB_LO_SHIFT 12 + +struct mvsw61xx_state { + struct switch_dev dev; + struct mii_bus *bus; + int base_addr; + u16 model; + + bool registered; + bool is_indirect; + + int cpu_port0; + int cpu_port1; + + int vlan_enabled; + struct port_state { + u16 fdb; + u16 pvid; + u16 mask; + u8 qmode; + } ports[MV_PORTS]; + + struct vlan_state { + bool port_based; + + u16 mask; + u16 vid; + u32 port_mode; + u32 port_sstate; + } vlans[MV_VLANS]; + + char buf[128]; +}; + +#define get_state(_dev) container_of((_dev), struct mvsw61xx_state, dev) + +#endif diff --git a/target/linux/generic/files/drivers/net/phy/mvswitch.c b/target/linux/generic/files/drivers/net/phy/mvswitch.c new file mode 100644 index 0000000..af73ec2 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/mvswitch.c @@ -0,0 +1,433 @@ +/* + * Marvell 88E6060 switch driver + * Copyright (c) 2008 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License v2 as published by the + * Free Software Foundation + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include "mvswitch.h" + +/* Undefine this to use trailer mode instead. + * I don't know if header mode works with all chips */ +#define HEADER_MODE 1 + +MODULE_DESCRIPTION("Marvell 88E6060 Switch driver"); +MODULE_AUTHOR("Felix Fietkau"); +MODULE_LICENSE("GPL"); + +#define MVSWITCH_MAGIC 0x88E6060 + +struct mvswitch_priv { + netdev_features_t orig_features; + u8 vlans[16]; +}; + +#define to_mvsw(_phy) ((struct mvswitch_priv *) (_phy)->priv) + +static inline u16 +r16(struct phy_device *phydev, int addr, int reg) +{ + return phydev->bus->read(phydev->bus, addr, reg); +} + +static inline void +w16(struct phy_device *phydev, int addr, int reg, u16 val) +{ + phydev->bus->write(phydev->bus, addr, reg, val); +} + + +static struct sk_buff * +mvswitch_mangle_tx(struct net_device *dev, struct sk_buff *skb) +{ + struct mvswitch_priv *priv; + char *buf = NULL; + u16 vid; + + priv = dev->phy_ptr; + if (unlikely(!priv)) + goto error; + + if (unlikely(skb->len < 16)) + goto error; + +#ifdef HEADER_MODE + if (__vlan_hwaccel_get_tag(skb, &vid)) + goto error; + + if (skb_cloned(skb) || (skb->len <= 62) || (skb_headroom(skb) < MV_HEADER_SIZE)) { + if (pskb_expand_head(skb, MV_HEADER_SIZE, (skb->len < 62 ? 62 - skb->len : 0), GFP_ATOMIC)) + goto error_expand; + if (skb->len < 62) + skb->len = 62; + } + buf = skb_push(skb, MV_HEADER_SIZE); +#else + if (__vlan_get_tag(skb, &vid)) + goto error; + + if (unlikely((vid > 15 || !priv->vlans[vid]))) + goto error; + + if (skb->len <= 64) { + if (pskb_expand_head(skb, 0, 64 + MV_TRAILER_SIZE - skb->len, GFP_ATOMIC)) + goto error_expand; + + buf = skb->data + 64; + skb->len = 64 + MV_TRAILER_SIZE; + } else { + if (skb_cloned(skb) || unlikely(skb_tailroom(skb) < 4)) { + if (pskb_expand_head(skb, 0, 4, GFP_ATOMIC)) + goto error_expand; + } + buf = skb_put(skb, 4); + } + + /* move the ethernet header 4 bytes forward, overwriting the vlan tag */ + memmove(skb->data + 4, skb->data, 12); + skb->data += 4; + skb->len -= 4; + skb->mac_header += 4; +#endif + + if (!buf) + goto error; + + +#ifdef HEADER_MODE + /* prepend the tag */ + *((__be16 *) buf) = cpu_to_be16( + ((vid << MV_HEADER_VLAN_S) & MV_HEADER_VLAN_M) | + ((priv->vlans[vid] << MV_HEADER_PORTS_S) & MV_HEADER_PORTS_M) + ); +#else + /* append the tag */ + *((__be32 *) buf) = cpu_to_be32(( + (MV_TRAILER_OVERRIDE << MV_TRAILER_FLAGS_S) | + ((priv->vlans[vid] & MV_TRAILER_PORTS_M) << MV_TRAILER_PORTS_S) + )); +#endif + + return skb; + +error_expand: + if (net_ratelimit()) + printk("%s: failed to expand/update skb for the switch\n", dev->name); + +error: + /* any errors? drop the packet! */ + dev_kfree_skb_any(skb); + return NULL; +} + +static void +mvswitch_mangle_rx(struct net_device *dev, struct sk_buff *skb) +{ + struct mvswitch_priv *priv; + unsigned char *buf; + int vlan = -1; + int i; + + priv = dev->phy_ptr; + if (WARN_ON_ONCE(!priv)) + return; + +#ifdef HEADER_MODE + buf = skb->data; + skb_pull(skb, MV_HEADER_SIZE); +#else + buf = skb->data + skb->len - MV_TRAILER_SIZE; + if (buf[0] != 0x80) + return; +#endif + + /* look for the vlan matching the incoming port */ + for (i = 0; i < ARRAY_SIZE(priv->vlans); i++) { + if ((1 << buf[1]) & priv->vlans[i]) + vlan = i; + } + + if (vlan == -1) + return; + + __vlan_hwaccel_put_tag(skb, vlan); +} + + +static int +mvswitch_wait_mask(struct phy_device *pdev, int addr, int reg, u16 mask, u16 val) +{ + int i = 100; + u16 r; + + do { + r = r16(pdev, addr, reg) & mask; + if (r == val) + return 0; + } while(--i > 0); + return -ETIMEDOUT; +} + +static int +mvswitch_config_init(struct phy_device *pdev) +{ + struct mvswitch_priv *priv = to_mvsw(pdev); + struct net_device *dev = pdev->attached_dev; + u8 vlmap = 0; + int i; + + if (!dev) + return -EINVAL; + + printk("%s: Marvell 88E6060 PHY driver attached.\n", dev->name); + pdev->supported = ADVERTISED_100baseT_Full; + pdev->advertising = ADVERTISED_100baseT_Full; + dev->phy_ptr = priv; + pdev->irq = PHY_POLL; +#ifdef HEADER_MODE + dev->flags |= IFF_PROMISC; +#endif + + /* initialize default vlans */ + for (i = 0; i < MV_PORTS; i++) + priv->vlans[(i == MV_WANPORT ? 2 : 1)] |= (1 << i); + + /* before entering reset, disable all ports */ + for (i = 0; i < MV_PORTS; i++) + w16(pdev, MV_PORTREG(CONTROL, i), 0x00); + + msleep(2); /* wait for the status change to settle in */ + + /* put the ATU in reset */ + w16(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET); + + i = mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET, 0); + if (i < 0) { + printk("%s: Timeout waiting for the switch to reset.\n", dev->name); + return i; + } + + /* set the ATU flags */ + w16(pdev, MV_SWITCHREG(ATU_CTRL), + MV_ATUCTL_NO_LEARN | + MV_ATUCTL_ATU_1K | + MV_ATUCTL_AGETIME(MV_ATUCTL_AGETIME_MIN) /* minimum without disabling ageing */ + ); + + /* initialize the cpu port */ + w16(pdev, MV_PORTREG(CONTROL, MV_CPUPORT), +#ifdef HEADER_MODE + MV_PORTCTRL_HEADER | +#else + MV_PORTCTRL_RXTR | + MV_PORTCTRL_TXTR | +#endif + MV_PORTCTRL_ENABLED + ); + /* wait for the phy change to settle in */ + msleep(2); + for (i = 0; i < MV_PORTS; i++) { + u8 pvid = 0; + int j; + + vlmap = 0; + + /* look for the matching vlan */ + for (j = 0; j < ARRAY_SIZE(priv->vlans); j++) { + if (priv->vlans[j] & (1 << i)) { + vlmap = priv->vlans[j]; + pvid = j; + } + } + /* leave port unconfigured if it's not part of a vlan */ + if (!vlmap) + continue; + + /* add the cpu port to the allowed destinations list */ + vlmap |= (1 << MV_CPUPORT); + + /* take port out of its own vlan destination map */ + vlmap &= ~(1 << i); + + /* apply vlan settings */ + w16(pdev, MV_PORTREG(VLANMAP, i), + MV_PORTVLAN_PORTS(vlmap) | + MV_PORTVLAN_ID(i) + ); + + /* re-enable port */ + w16(pdev, MV_PORTREG(CONTROL, i), + MV_PORTCTRL_ENABLED + ); + } + + w16(pdev, MV_PORTREG(VLANMAP, MV_CPUPORT), + MV_PORTVLAN_ID(MV_CPUPORT) + ); + + /* set the port association vector */ + for (i = 0; i <= MV_PORTS; i++) { + w16(pdev, MV_PORTREG(ASSOC, i), + MV_PORTASSOC_PORTS(1 << i) + ); + } + + /* init switch control */ + w16(pdev, MV_SWITCHREG(CTRL), + MV_SWITCHCTL_MSIZE | + MV_SWITCHCTL_DROP + ); + + dev->eth_mangle_rx = mvswitch_mangle_rx; + dev->eth_mangle_tx = mvswitch_mangle_tx; + priv->orig_features = dev->features; + +#ifdef HEADER_MODE + dev->priv_flags |= IFF_NO_IP_ALIGN; + dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; +#else + dev->features |= NETIF_F_HW_VLAN_RX; +#endif + + return 0; +} + +static int +mvswitch_read_status(struct phy_device *pdev) +{ + pdev->speed = SPEED_100; + pdev->duplex = DUPLEX_FULL; + pdev->link = 1; + + /* XXX ugly workaround: we can't force the switch + * to gracefully handle hosts moving from one port to another, + * so we have to regularly clear the ATU database */ + + /* wait for the ATU to become available */ + mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0); + + /* flush the ATU */ + w16(pdev, MV_SWITCHREG(ATU_OP), + MV_ATUOP_INPROGRESS | + MV_ATUOP_FLUSH_ALL + ); + + /* wait for operation to complete */ + mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0); + + return 0; +} + +static int +mvswitch_config_aneg(struct phy_device *phydev) +{ + return 0; +} + +static void +mvswitch_detach(struct phy_device *pdev) +{ + struct mvswitch_priv *priv = to_mvsw(pdev); + struct net_device *dev = pdev->attached_dev; + + if (!dev) + return; + + dev->phy_ptr = NULL; + dev->eth_mangle_rx = NULL; + dev->eth_mangle_tx = NULL; + dev->features = priv->orig_features; + dev->priv_flags &= ~IFF_NO_IP_ALIGN; +} + +static void +mvswitch_remove(struct phy_device *pdev) +{ + struct mvswitch_priv *priv = to_mvsw(pdev); + + kfree(priv); +} + +static int +mvswitch_probe(struct phy_device *pdev) +{ + struct mvswitch_priv *priv; + + priv = kzalloc(sizeof(struct mvswitch_priv), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + pdev->priv = priv; + + return 0; +} + +static int +mvswitch_fixup(struct phy_device *dev) +{ + u16 reg; + + if (dev->addr != 0x10) + return 0; + + reg = dev->bus->read(dev->bus, MV_PORTREG(IDENT, 0)) & MV_IDENT_MASK; + if (reg != MV_IDENT_VALUE) + return 0; + + dev->phy_id = MVSWITCH_MAGIC; + return 0; +} + + +static struct phy_driver mvswitch_driver = { + .name = "Marvell 88E6060", + .phy_id = MVSWITCH_MAGIC, + .phy_id_mask = 0xffffffff, + .features = PHY_BASIC_FEATURES, + .probe = &mvswitch_probe, + .remove = &mvswitch_remove, + .detach = &mvswitch_detach, + .config_init = &mvswitch_config_init, + .config_aneg = &mvswitch_config_aneg, + .read_status = &mvswitch_read_status, + .driver = { .owner = THIS_MODULE,}, +}; + +static int __init +mvswitch_init(void) +{ + phy_register_fixup_for_id(PHY_ANY_ID, mvswitch_fixup); + return phy_driver_register(&mvswitch_driver); +} + +static void __exit +mvswitch_exit(void) +{ + phy_driver_unregister(&mvswitch_driver); +} + +module_init(mvswitch_init); +module_exit(mvswitch_exit); diff --git a/target/linux/generic/files/drivers/net/phy/mvswitch.h b/target/linux/generic/files/drivers/net/phy/mvswitch.h new file mode 100644 index 0000000..1563eec --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/mvswitch.h @@ -0,0 +1,145 @@ +/* + * Marvell 88E6060 switch driver + * Copyright (c) 2008 Felix Fietkau + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License v2 as published by the + * Free Software Foundation + */ +#ifndef __MVSWITCH_H +#define __MVSWITCH_H + +#define MV_HEADER_SIZE 2 +#define MV_HEADER_PORTS_M 0x001f +#define MV_HEADER_PORTS_S 0 +#define MV_HEADER_VLAN_M 0xf000 +#define MV_HEADER_VLAN_S 12 + +#define MV_TRAILER_SIZE 4 +#define MV_TRAILER_PORTS_M 0x1f +#define MV_TRAILER_PORTS_S 16 +#define MV_TRAILER_FLAGS_S 24 +#define MV_TRAILER_OVERRIDE 0x80 + + +#define MV_PORTS 5 +#define MV_WANPORT 4 +#define MV_CPUPORT 5 + +#define MV_BASE 0x10 + +#define MV_PHYPORT_BASE (MV_BASE + 0x0) +#define MV_PHYPORT(_n) (MV_PHYPORT_BASE + (_n)) +#define MV_SWITCHPORT_BASE (MV_BASE + 0x8) +#define MV_SWITCHPORT(_n) (MV_SWITCHPORT_BASE + (_n)) +#define MV_SWITCHREGS (MV_BASE + 0xf) + +enum { + MV_PHY_CONTROL = 0x00, + MV_PHY_STATUS = 0x01, + MV_PHY_IDENT0 = 0x02, + MV_PHY_IDENT1 = 0x03, + MV_PHY_ANEG = 0x04, + MV_PHY_LINK_ABILITY = 0x05, + MV_PHY_ANEG_EXPAND = 0x06, + MV_PHY_XMIT_NEXTP = 0x07, + MV_PHY_LINK_NEXTP = 0x08, + MV_PHY_CONTROL1 = 0x10, + MV_PHY_STATUS1 = 0x11, + MV_PHY_INTR_EN = 0x12, + MV_PHY_INTR_STATUS = 0x13, + MV_PHY_INTR_PORT = 0x14, + MV_PHY_RECV_COUNTER = 0x16, + MV_PHY_LED_PARALLEL = 0x16, + MV_PHY_LED_STREAM = 0x17, + MV_PHY_LED_CTRL = 0x18, + MV_PHY_LED_OVERRIDE = 0x19, + MV_PHY_VCT_CTRL = 0x1a, + MV_PHY_VCT_STATUS = 0x1b, + MV_PHY_CONTROL2 = 0x1e +}; +#define MV_PHYREG(_type, _port) MV_PHYPORT(_port), MV_PHY_##_type + +enum { + MV_PORT_STATUS = 0x00, + MV_PORT_IDENT = 0x03, + MV_PORT_CONTROL = 0x04, + MV_PORT_VLANMAP = 0x06, + MV_PORT_ASSOC = 0x0b, + MV_PORT_RXCOUNT = 0x10, + MV_PORT_TXCOUNT = 0x11, +}; +#define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type + +enum { + MV_PORTCTRL_BLOCK = (1 << 0), + MV_PORTCTRL_LEARN = (2 << 0), + MV_PORTCTRL_ENABLED = (3 << 0), + MV_PORTCTRL_VLANTUN = (1 << 7), /* Enforce VLANs on packets */ + MV_PORTCTRL_RXTR = (1 << 8), /* Enable Marvell packet trailer for ingress */ + MV_PORTCTRL_HEADER = (1 << 11), /* Enable Marvell packet header mode for port */ + MV_PORTCTRL_TXTR = (1 << 14), /* Enable Marvell packet trailer for egress */ + MV_PORTCTRL_FORCEFL = (1 << 15), /* force flow control */ +}; + +#define MV_PORTVLAN_ID(_n) (((_n) & 0xf) << 12) +#define MV_PORTVLAN_PORTS(_n) ((_n) & 0x3f) + +#define MV_PORTASSOC_PORTS(_n) ((_n) & 0x1f) +#define MV_PORTASSOC_MONITOR (1 << 15) + +enum { + MV_SWITCH_MAC0 = 0x01, + MV_SWITCH_MAC1 = 0x02, + MV_SWITCH_MAC2 = 0x03, + MV_SWITCH_CTRL = 0x04, + MV_SWITCH_ATU_CTRL = 0x0a, + MV_SWITCH_ATU_OP = 0x0b, + MV_SWITCH_ATU_DATA = 0x0c, + MV_SWITCH_ATU_MAC0 = 0x0d, + MV_SWITCH_ATU_MAC1 = 0x0e, + MV_SWITCH_ATU_MAC2 = 0x0f, +}; +#define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type + +enum { + MV_SWITCHCTL_EEIE = (1 << 0), /* EEPROM interrupt enable */ + MV_SWITCHCTL_PHYIE = (1 << 1), /* PHY interrupt enable */ + MV_SWITCHCTL_ATUDONE= (1 << 2), /* ATU done interrupt enable */ + MV_SWITCHCTL_ATUIE = (1 << 3), /* ATU interrupt enable */ + MV_SWITCHCTL_CTRMODE= (1 << 8), /* statistics for rx and tx errors */ + MV_SWITCHCTL_RELOAD = (1 << 9), /* reload registers from eeprom */ + MV_SWITCHCTL_MSIZE = (1 << 10), /* increase maximum frame size */ + MV_SWITCHCTL_DROP = (1 << 13), /* discard frames with excessive collisions */ +}; + +enum { +#define MV_ATUCTL_AGETIME_MIN 16 +#define MV_ATUCTL_AGETIME_MAX 4080 +#define MV_ATUCTL_AGETIME(_n) ((((_n) / 16) & 0xff) << 4) + MV_ATUCTL_ATU_256 = (0 << 12), + MV_ATUCTL_ATU_512 = (1 << 12), + MV_ATUCTL_ATU_1K = (2 << 12), + MV_ATUCTL_ATUMASK = (3 << 12), + MV_ATUCTL_NO_LEARN = (1 << 14), + MV_ATUCTL_RESET = (1 << 15), +}; + +enum { +#define MV_ATUOP_DBNUM(_n) ((_n) & 0x0f) + + MV_ATUOP_NOOP = (0 << 12), + MV_ATUOP_FLUSH_ALL = (1 << 12), + MV_ATUOP_FLUSH_U = (2 << 12), + MV_ATUOP_LOAD_DB = (3 << 12), + MV_ATUOP_GET_NEXT = (4 << 12), + MV_ATUOP_FLUSH_DB = (5 << 12), + MV_ATUOP_FLUSH_DB_UU= (6 << 12), + + MV_ATUOP_INPROGRESS = (1 << 15), +}; + +#define MV_IDENT_MASK 0xfff0 +#define MV_IDENT_VALUE 0x0600 + +#endif diff --git a/target/linux/generic/files/drivers/net/phy/psb6970.c b/target/linux/generic/files/drivers/net/phy/psb6970.c new file mode 100644 index 0000000..2fcd299 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/psb6970.c @@ -0,0 +1,438 @@ +/* + * Lantiq PSB6970 (Tantos) Switch driver + * + * Copyright (c) 2009,2010 Team Embedded. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License v2 as published by the + * Free Software Foundation. + * + * The switch programming done in this driver follows the + * "Ethernet Traffic Separation using VLAN" Application Note as + * published by Lantiq. + */ + +#include +#include +#include +#include + +#define PSB6970_MAX_VLANS 16 +#define PSB6970_NUM_PORTS 7 +#define PSB6970_DEFAULT_PORT_CPU 6 +#define PSB6970_IS_CPU_PORT(x) ((x) > 4) + +#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f) + +/* --- Identification --- */ +#define PSB6970_CI0 0x0100 +#define PSB6970_CI0_MASK 0x000f +#define PSB6970_CI1 0x0101 +#define PSB6970_CI1_VAL 0x2599 +#define PSB6970_CI1_MASK 0xffff + +/* --- VLAN filter table --- */ +#define PSB6970_VFxL(i) ((i)*2+0x10) /* VLAN Filter Low */ +#define PSB6970_VFxL_VV (1 << 15) /* VLAN_Valid */ + +#define PSB6970_VFxH(i) ((i)*2+0x11) /* VLAN Filter High */ +#define PSB6970_VFxH_TM_SHIFT 7 /* Tagged Member */ + +/* --- Port registers --- */ +#define PSB6970_EC(p) ((p)*0x20+2) /* Extended Control */ +#define PSB6970_EC_IFNTE (1 << 1) /* Input Force No Tag Enable */ + +#define PSB6970_PBVM(p) ((p)*0x20+3) /* Port Base VLAN Map */ +#define PSB6970_PBVM_VMCE (1 << 8) +#define PSB6970_PBVM_AOVTP (1 << 9) +#define PSB6970_PBVM_VSD (1 << 10) +#define PSB6970_PBVM_VC (1 << 11) /* VID Check with VID table */ +#define PSB6970_PBVM_TBVE (1 << 13) /* Tag-Based VLAN enable */ + +#define PSB6970_DVID(p) ((p)*0x20+4) /* Default VLAN ID & Priority */ + +struct psb6970_priv { + struct switch_dev dev; + struct phy_device *phy; + u16 (*read) (struct phy_device* phydev, int reg); + void (*write) (struct phy_device* phydev, int reg, u16 val); + struct mutex reg_mutex; + + /* all fields below are cleared on reset */ + bool vlan; + u16 vlan_id[PSB6970_MAX_VLANS]; + u8 vlan_table[PSB6970_MAX_VLANS]; + u8 vlan_tagged; + u16 pvid[PSB6970_NUM_PORTS]; +}; + +#define to_psb6970(_dev) container_of(_dev, struct psb6970_priv, dev) + +static u16 psb6970_mii_read(struct phy_device *phydev, int reg) +{ + return phydev->bus->read(phydev->bus, PHYADDR(reg)); +} + +static void psb6970_mii_write(struct phy_device *phydev, int reg, u16 val) +{ + phydev->bus->write(phydev->bus, PHYADDR(reg), val); +} + +static int +psb6970_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct psb6970_priv *priv = to_psb6970(dev); + priv->vlan = !!val->value.i; + return 0; +} + +static int +psb6970_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct psb6970_priv *priv = to_psb6970(dev); + val->value.i = priv->vlan; + return 0; +} + +static int psb6970_set_pvid(struct switch_dev *dev, int port, int vlan) +{ + struct psb6970_priv *priv = to_psb6970(dev); + + /* make sure no invalid PVIDs get set */ + if (vlan >= dev->vlans) + return -EINVAL; + + priv->pvid[port] = vlan; + return 0; +} + +static int psb6970_get_pvid(struct switch_dev *dev, int port, int *vlan) +{ + struct psb6970_priv *priv = to_psb6970(dev); + *vlan = priv->pvid[port]; + return 0; +} + +static int +psb6970_set_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct psb6970_priv *priv = to_psb6970(dev); + priv->vlan_id[val->port_vlan] = val->value.i; + return 0; +} + +static int +psb6970_get_vid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct psb6970_priv *priv = to_psb6970(dev); + val->value.i = priv->vlan_id[val->port_vlan]; + return 0; +} + +static struct switch_attr psb6970_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = psb6970_set_vlan, + .get = psb6970_get_vlan, + .max = 1}, +}; + +static struct switch_attr psb6970_port[] = { +}; + +static struct switch_attr psb6970_vlan[] = { + { + .type = SWITCH_TYPE_INT, + .name = "vid", + .description = "VLAN ID (0-4094)", + .set = psb6970_set_vid, + .get = psb6970_get_vid, + .max = 4094, + }, +}; + +static int psb6970_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct psb6970_priv *priv = to_psb6970(dev); + u8 ports = priv->vlan_table[val->port_vlan]; + int i; + + val->len = 0; + for (i = 0; i < PSB6970_NUM_PORTS; i++) { + struct switch_port *p; + + if (!(ports & (1 << i))) + continue; + + p = &val->value.ports[val->len++]; + p->id = i; + if (priv->vlan_tagged & (1 << i)) + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); + else + p->flags = 0; + } + return 0; +} + +static int psb6970_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct psb6970_priv *priv = to_psb6970(dev); + u8 *vt = &priv->vlan_table[val->port_vlan]; + int i, j; + + *vt = 0; + for (i = 0; i < val->len; i++) { + struct switch_port *p = &val->value.ports[i]; + + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) + priv->vlan_tagged |= (1 << p->id); + else { + priv->vlan_tagged &= ~(1 << p->id); + priv->pvid[p->id] = val->port_vlan; + + /* make sure that an untagged port does not + * appear in other vlans */ + for (j = 0; j < PSB6970_MAX_VLANS; j++) { + if (j == val->port_vlan) + continue; + priv->vlan_table[j] &= ~(1 << p->id); + } + } + + *vt |= 1 << p->id; + } + return 0; +} + +static int psb6970_hw_apply(struct switch_dev *dev) +{ + struct psb6970_priv *priv = to_psb6970(dev); + int i, j; + + mutex_lock(&priv->reg_mutex); + + if (priv->vlan) { + /* into the vlan translation unit */ + for (j = 0; j < PSB6970_MAX_VLANS; j++) { + u8 vp = priv->vlan_table[j]; + + if (vp) { + priv->write(priv->phy, PSB6970_VFxL(j), + PSB6970_VFxL_VV | priv->vlan_id[j]); + priv->write(priv->phy, PSB6970_VFxH(j), + ((vp & priv-> + vlan_tagged) << + PSB6970_VFxH_TM_SHIFT) | vp); + } else /* clear VLAN Valid flag for unused vlans */ + priv->write(priv->phy, PSB6970_VFxL(j), 0); + + } + } + + /* update the port destination mask registers and tag settings */ + for (i = 0; i < PSB6970_NUM_PORTS; i++) { + int dvid = 1, pbvm = 0x7f | PSB6970_PBVM_VSD, ec = 0; + + if (priv->vlan) { + ec = PSB6970_EC_IFNTE; + dvid = priv->vlan_id[priv->pvid[i]]; + pbvm |= PSB6970_PBVM_TBVE | PSB6970_PBVM_VMCE; + + if ((i << 1) & priv->vlan_tagged) + pbvm |= PSB6970_PBVM_AOVTP | PSB6970_PBVM_VC; + } + + priv->write(priv->phy, PSB6970_PBVM(i), pbvm); + + if (!PSB6970_IS_CPU_PORT(i)) { + priv->write(priv->phy, PSB6970_EC(i), ec); + priv->write(priv->phy, PSB6970_DVID(i), dvid); + } + } + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int psb6970_reset_switch(struct switch_dev *dev) +{ + struct psb6970_priv *priv = to_psb6970(dev); + int i; + + mutex_lock(&priv->reg_mutex); + + memset(&priv->vlan, 0, sizeof(struct psb6970_priv) - + offsetof(struct psb6970_priv, vlan)); + + for (i = 0; i < PSB6970_MAX_VLANS; i++) + priv->vlan_id[i] = i; + + mutex_unlock(&priv->reg_mutex); + + return psb6970_hw_apply(dev); +} + +static const struct switch_dev_ops psb6970_ops = { + .attr_global = { + .attr = psb6970_globals, + .n_attr = ARRAY_SIZE(psb6970_globals), + }, + .attr_port = { + .attr = psb6970_port, + .n_attr = ARRAY_SIZE(psb6970_port), + }, + .attr_vlan = { + .attr = psb6970_vlan, + .n_attr = ARRAY_SIZE(psb6970_vlan), + }, + .get_port_pvid = psb6970_get_pvid, + .set_port_pvid = psb6970_set_pvid, + .get_vlan_ports = psb6970_get_ports, + .set_vlan_ports = psb6970_set_ports, + .apply_config = psb6970_hw_apply, + .reset_switch = psb6970_reset_switch, +}; + +static int psb6970_config_init(struct phy_device *pdev) +{ + struct psb6970_priv *priv; + struct net_device *dev = pdev->attached_dev; + struct switch_dev *swdev; + int ret; + + priv = kzalloc(sizeof(struct psb6970_priv), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + priv->phy = pdev; + + if (pdev->addr == 0) + printk(KERN_INFO "%s: psb6970 switch driver attached.\n", + pdev->attached_dev->name); + + if (pdev->addr != 0) { + kfree(priv); + return 0; + } + + pdev->supported = pdev->advertising = SUPPORTED_100baseT_Full; + + mutex_init(&priv->reg_mutex); + priv->read = psb6970_mii_read; + priv->write = psb6970_mii_write; + + pdev->priv = priv; + + swdev = &priv->dev; + swdev->cpu_port = PSB6970_DEFAULT_PORT_CPU; + swdev->ops = &psb6970_ops; + + swdev->name = "Lantiq PSB6970"; + swdev->vlans = PSB6970_MAX_VLANS; + swdev->ports = PSB6970_NUM_PORTS; + + if ((ret = register_switch(&priv->dev, pdev->attached_dev)) < 0) { + kfree(priv); + goto done; + } + + ret = psb6970_reset_switch(&priv->dev); + if (ret) { + kfree(priv); + goto done; + } + + dev->phy_ptr = priv; + +done: + return ret; +} + +static int psb6970_read_status(struct phy_device *phydev) +{ + phydev->speed = SPEED_100; + phydev->duplex = DUPLEX_FULL; + phydev->link = 1; + + phydev->state = PHY_RUNNING; + netif_carrier_on(phydev->attached_dev); + phydev->adjust_link(phydev->attached_dev); + + return 0; +} + +static int psb6970_config_aneg(struct phy_device *phydev) +{ + return 0; +} + +static int psb6970_probe(struct phy_device *pdev) +{ + return 0; +} + +static void psb6970_remove(struct phy_device *pdev) +{ + struct psb6970_priv *priv = pdev->priv; + + if (!priv) + return; + + if (pdev->addr == 0) + unregister_switch(&priv->dev); + kfree(priv); +} + +static int psb6970_fixup(struct phy_device *dev) +{ + struct mii_bus *bus = dev->bus; + u16 reg; + + /* look for the switch on the bus */ + reg = bus->read(bus, PHYADDR(PSB6970_CI1)) & PSB6970_CI1_MASK; + if (reg != PSB6970_CI1_VAL) + return 0; + + dev->phy_id = (reg << 16); + dev->phy_id |= bus->read(bus, PHYADDR(PSB6970_CI0)) & PSB6970_CI0_MASK; + + return 0; +} + +static struct phy_driver psb6970_driver = { + .name = "Lantiq PSB6970", + .phy_id = PSB6970_CI1_VAL << 16, + .phy_id_mask = 0xffff0000, + .features = PHY_BASIC_FEATURES, + .probe = psb6970_probe, + .remove = psb6970_remove, + .config_init = &psb6970_config_init, + .config_aneg = &psb6970_config_aneg, + .read_status = &psb6970_read_status, + .driver = {.owner = THIS_MODULE}, +}; + +int __init psb6970_init(void) +{ + phy_register_fixup_for_id(PHY_ANY_ID, psb6970_fixup); + return phy_driver_register(&psb6970_driver); +} + +module_init(psb6970_init); + +void __exit psb6970_exit(void) +{ + phy_driver_unregister(&psb6970_driver); +} + +module_exit(psb6970_exit); + +MODULE_DESCRIPTION("Lantiq PSB6970 Switch"); +MODULE_AUTHOR("Ithamar R. Adema "); +MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/files/drivers/net/phy/rtl8306.c b/target/linux/generic/files/drivers/net/phy/rtl8306.c new file mode 100644 index 0000000..e280e93 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/rtl8306.c @@ -0,0 +1,1060 @@ +/* + * rtl8306.c: RTL8306S switch driver + * + * Copyright (C) 2009 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//#define DEBUG 1 + +/* Global (PHY0) */ +#define RTL8306_REG_PAGE 16 +#define RTL8306_REG_PAGE_LO (1 << 15) +#define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */ + +#define RTL8306_NUM_VLANS 16 +#define RTL8306_NUM_PORTS 6 +#define RTL8306_PORT_CPU 5 +#define RTL8306_NUM_PAGES 4 +#define RTL8306_NUM_REGS 32 + +#define RTL_NAME_S "RTL8306S" +#define RTL_NAME_SD "RTL8306SD" +#define RTL_NAME_SDM "RTL8306SDM" +#define RTL_NAME_UNKNOWN "RTL8306(unknown)" + +#define RTL8306_MAGIC 0x8306 + +static LIST_HEAD(phydevs); + +struct rtl_priv { + struct list_head list; + struct switch_dev dev; + int page; + int type; + int do_cpu; + struct mii_bus *bus; + char hwname[sizeof(RTL_NAME_UNKNOWN)]; + bool fixup; +}; + +struct rtl_phyregs { + int nway; + int speed; + int duplex; +}; + +#define to_rtl(_dev) container_of(_dev, struct rtl_priv, dev) + +enum { + RTL_TYPE_S, + RTL_TYPE_SD, + RTL_TYPE_SDM, +}; + +struct rtl_reg { + int page; + int phy; + int reg; + int bits; + int shift; + int inverted; +}; + +#define RTL_VLAN_REGOFS(name) \ + (RTL_REG_VLAN1_##name - RTL_REG_VLAN0_##name) + +#define RTL_PORT_REGOFS(name) \ + (RTL_REG_PORT1_##name - RTL_REG_PORT0_##name) + +#define RTL_PORT_REG(id, reg) \ + (RTL_REG_PORT0_##reg + (id * RTL_PORT_REGOFS(reg))) + +#define RTL_VLAN_REG(id, reg) \ + (RTL_REG_VLAN0_##reg + (id * RTL_VLAN_REGOFS(reg))) + +#define RTL_GLOBAL_REGATTR(reg) \ + .id = RTL_REG_##reg, \ + .type = SWITCH_TYPE_INT, \ + .ofs = 0, \ + .set = rtl_attr_set_int, \ + .get = rtl_attr_get_int + +#define RTL_PORT_REGATTR(reg) \ + .id = RTL_REG_PORT0_##reg, \ + .type = SWITCH_TYPE_INT, \ + .ofs = RTL_PORT_REGOFS(reg), \ + .set = rtl_attr_set_port_int, \ + .get = rtl_attr_get_port_int + +#define RTL_VLAN_REGATTR(reg) \ + .id = RTL_REG_VLAN0_##reg, \ + .type = SWITCH_TYPE_INT, \ + .ofs = RTL_VLAN_REGOFS(reg), \ + .set = rtl_attr_set_vlan_int, \ + .get = rtl_attr_get_vlan_int + +enum rtl_regidx { + RTL_REG_CHIPID, + RTL_REG_CHIPVER, + RTL_REG_CHIPTYPE, + RTL_REG_CPUPORT, + + RTL_REG_EN_CPUPORT, + RTL_REG_EN_TAG_OUT, + RTL_REG_EN_TAG_CLR, + RTL_REG_EN_TAG_IN, + RTL_REG_TRAP_CPU, + RTL_REG_CPU_LINKUP, + RTL_REG_TRUNK_PORTSEL, + RTL_REG_EN_TRUNK, + RTL_REG_RESET, + + RTL_REG_VLAN_ENABLE, + RTL_REG_VLAN_FILTER, + RTL_REG_VLAN_TAG_ONLY, + RTL_REG_VLAN_TAG_AWARE, +#define RTL_VLAN_ENUM(id) \ + RTL_REG_VLAN##id##_VID, \ + RTL_REG_VLAN##id##_PORTMASK + RTL_VLAN_ENUM(0), + RTL_VLAN_ENUM(1), + RTL_VLAN_ENUM(2), + RTL_VLAN_ENUM(3), + RTL_VLAN_ENUM(4), + RTL_VLAN_ENUM(5), + RTL_VLAN_ENUM(6), + RTL_VLAN_ENUM(7), + RTL_VLAN_ENUM(8), + RTL_VLAN_ENUM(9), + RTL_VLAN_ENUM(10), + RTL_VLAN_ENUM(11), + RTL_VLAN_ENUM(12), + RTL_VLAN_ENUM(13), + RTL_VLAN_ENUM(14), + RTL_VLAN_ENUM(15), +#define RTL_PORT_ENUM(id) \ + RTL_REG_PORT##id##_PVID, \ + RTL_REG_PORT##id##_NULL_VID_REPLACE, \ + RTL_REG_PORT##id##_NON_PVID_DISCARD, \ + RTL_REG_PORT##id##_VID_INSERT, \ + RTL_REG_PORT##id##_TAG_INSERT, \ + RTL_REG_PORT##id##_LINK, \ + RTL_REG_PORT##id##_SPEED, \ + RTL_REG_PORT##id##_NWAY, \ + RTL_REG_PORT##id##_NRESTART, \ + RTL_REG_PORT##id##_DUPLEX, \ + RTL_REG_PORT##id##_RXEN, \ + RTL_REG_PORT##id##_TXEN + RTL_PORT_ENUM(0), + RTL_PORT_ENUM(1), + RTL_PORT_ENUM(2), + RTL_PORT_ENUM(3), + RTL_PORT_ENUM(4), + RTL_PORT_ENUM(5), +}; + +static const struct rtl_reg rtl_regs[] = { + [RTL_REG_CHIPID] = { 0, 4, 30, 16, 0, 0 }, + [RTL_REG_CHIPVER] = { 0, 4, 31, 8, 0, 0 }, + [RTL_REG_CHIPTYPE] = { 0, 4, 31, 2, 8, 0 }, + + /* CPU port number */ + [RTL_REG_CPUPORT] = { 2, 4, 21, 3, 0, 0 }, + /* Enable CPU port function */ + [RTL_REG_EN_CPUPORT] = { 3, 2, 21, 1, 15, 1 }, + /* Enable CPU port tag insertion */ + [RTL_REG_EN_TAG_OUT] = { 3, 2, 21, 1, 12, 0 }, + /* Enable CPU port tag removal */ + [RTL_REG_EN_TAG_CLR] = { 3, 2, 21, 1, 11, 0 }, + /* Enable CPU port tag checking */ + [RTL_REG_EN_TAG_IN] = { 0, 4, 21, 1, 7, 0 }, + [RTL_REG_EN_TRUNK] = { 0, 0, 19, 1, 11, 1 }, + [RTL_REG_TRUNK_PORTSEL] = { 0, 0, 16, 1, 6, 1 }, + [RTL_REG_RESET] = { 0, 0, 16, 1, 12, 0 }, + + [RTL_REG_TRAP_CPU] = { 3, 2, 22, 1, 6, 0 }, + [RTL_REG_CPU_LINKUP] = { 0, 6, 22, 1, 15, 0 }, + + [RTL_REG_VLAN_TAG_ONLY] = { 0, 0, 16, 1, 8, 1 }, + [RTL_REG_VLAN_FILTER] = { 0, 0, 16, 1, 9, 1 }, + [RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16, 1, 10, 1 }, + [RTL_REG_VLAN_ENABLE] = { 0, 0, 18, 1, 8, 1 }, + +#define RTL_VLAN_REGS(id, phy, page, regofs) \ + [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \ + [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 } + RTL_VLAN_REGS( 0, 0, 0, 0), + RTL_VLAN_REGS( 1, 1, 0, 0), + RTL_VLAN_REGS( 2, 2, 0, 0), + RTL_VLAN_REGS( 3, 3, 0, 0), + RTL_VLAN_REGS( 4, 4, 0, 0), + RTL_VLAN_REGS( 5, 0, 1, 2), + RTL_VLAN_REGS( 6, 1, 1, 2), + RTL_VLAN_REGS( 7, 2, 1, 2), + RTL_VLAN_REGS( 8, 3, 1, 2), + RTL_VLAN_REGS( 9, 4, 1, 2), + RTL_VLAN_REGS(10, 0, 1, 4), + RTL_VLAN_REGS(11, 1, 1, 4), + RTL_VLAN_REGS(12, 2, 1, 4), + RTL_VLAN_REGS(13, 3, 1, 4), + RTL_VLAN_REGS(14, 4, 1, 4), + RTL_VLAN_REGS(15, 0, 1, 6), + +#define REG_PORT_SETTING(port, phy) \ + [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \ + [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \ + [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \ + [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \ + [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \ + [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \ + [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \ + [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \ + [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \ + [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \ + [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 } + + REG_PORT_SETTING(0, 0), + REG_PORT_SETTING(1, 1), + REG_PORT_SETTING(2, 2), + REG_PORT_SETTING(3, 3), + REG_PORT_SETTING(4, 4), + REG_PORT_SETTING(5, 6), + +#define REG_PORT_PVID(phy, page, regofs) \ + { page, phy, 24 + regofs, 4, 12, 0 } + [RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0), + [RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0), + [RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0), + [RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0), + [RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0), + [RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2), +}; + + +static inline void +rtl_set_page(struct rtl_priv *priv, unsigned int page) +{ + struct mii_bus *bus = priv->bus; + u16 pgsel; + + if (priv->fixup) + return; + + if (priv->page == page) + return; + + BUG_ON(page > RTL8306_NUM_PAGES); + pgsel = bus->read(bus, 0, RTL8306_REG_PAGE); + pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI); + if (page & (1 << 0)) + pgsel |= RTL8306_REG_PAGE_LO; + if (!(page & (1 << 1))) /* bit is inverted */ + pgsel |= RTL8306_REG_PAGE_HI; + bus->write(bus, 0, RTL8306_REG_PAGE, pgsel); +} + +static inline int +rtl_w16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 val) +{ + struct rtl_priv *priv = to_rtl(dev); + struct mii_bus *bus = priv->bus; + + rtl_set_page(priv, page); + bus->write(bus, phy, reg, val); + bus->read(bus, phy, reg); /* flush */ + return 0; +} + +static inline int +rtl_r16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg) +{ + struct rtl_priv *priv = to_rtl(dev); + struct mii_bus *bus = priv->bus; + + rtl_set_page(priv, page); + return bus->read(bus, phy, reg); +} + +static inline u16 +rtl_rmw(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 mask, u16 val) +{ + struct rtl_priv *priv = to_rtl(dev); + struct mii_bus *bus = priv->bus; + u16 r; + + rtl_set_page(priv, page); + r = bus->read(bus, phy, reg); + r &= ~mask; + r |= val; + bus->write(bus, phy, reg, r); + return bus->read(bus, phy, reg); /* flush */ +} + + +static inline int +rtl_get(struct switch_dev *dev, enum rtl_regidx s) +{ + const struct rtl_reg *r = &rtl_regs[s]; + u16 val; + + BUG_ON(s >= ARRAY_SIZE(rtl_regs)); + if (r->bits == 0) /* unimplemented */ + return 0; + + val = rtl_r16(dev, r->page, r->phy, r->reg); + + if (r->shift > 0) + val >>= r->shift; + + if (r->inverted) + val = ~val; + + val &= (1 << r->bits) - 1; + + return val; +} + +static int +rtl_set(struct switch_dev *dev, enum rtl_regidx s, unsigned int val) +{ + const struct rtl_reg *r = &rtl_regs[s]; + u16 mask = 0xffff; + + BUG_ON(s >= ARRAY_SIZE(rtl_regs)); + + if (r->bits == 0) /* unimplemented */ + return 0; + + if (r->shift > 0) + val <<= r->shift; + + if (r->inverted) + val = ~val; + + if (r->bits != 16) { + mask = (1 << r->bits) - 1; + mask <<= r->shift; + } + val &= mask; + return rtl_rmw(dev, r->page, r->phy, r->reg, mask, val); +} + +static void +rtl_phy_save(struct switch_dev *dev, int port, struct rtl_phyregs *regs) +{ + regs->nway = rtl_get(dev, RTL_PORT_REG(port, NWAY)); + regs->speed = rtl_get(dev, RTL_PORT_REG(port, SPEED)); + regs->duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX)); +} + +static void +rtl_phy_restore(struct switch_dev *dev, int port, struct rtl_phyregs *regs) +{ + rtl_set(dev, RTL_PORT_REG(port, NWAY), regs->nway); + rtl_set(dev, RTL_PORT_REG(port, SPEED), regs->speed); + rtl_set(dev, RTL_PORT_REG(port, DUPLEX), regs->duplex); +} + +static void +rtl_port_set_enable(struct switch_dev *dev, int port, int enabled) +{ + rtl_set(dev, RTL_PORT_REG(port, RXEN), enabled); + rtl_set(dev, RTL_PORT_REG(port, TXEN), enabled); + + if ((port >= 5) || !enabled) + return; + + /* restart autonegotiation if enabled */ + rtl_set(dev, RTL_PORT_REG(port, NRESTART), 1); +} + +static int +rtl_hw_apply(struct switch_dev *dev) +{ + int i; + int trunk_en, trunk_psel; + struct rtl_phyregs port5; + + rtl_phy_save(dev, 5, &port5); + + /* disable rx/tx from PHYs */ + for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) { + rtl_port_set_enable(dev, i, 0); + } + + /* save trunking status */ + trunk_en = rtl_get(dev, RTL_REG_EN_TRUNK); + trunk_psel = rtl_get(dev, RTL_REG_TRUNK_PORTSEL); + + /* trunk port 3 and 4 + * XXX: Big WTF, but RealTek seems to do it */ + rtl_set(dev, RTL_REG_EN_TRUNK, 1); + rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 1); + + /* execute the software reset */ + rtl_set(dev, RTL_REG_RESET, 1); + + /* wait for the reset to complete, + * but don't wait for too long */ + for (i = 0; i < 10; i++) { + if (rtl_get(dev, RTL_REG_RESET) == 0) + break; + + msleep(1); + } + + /* enable rx/tx from PHYs */ + for (i = 0; i < RTL8306_NUM_PORTS - 1; i++) { + rtl_port_set_enable(dev, i, 1); + } + + /* restore trunking settings */ + rtl_set(dev, RTL_REG_EN_TRUNK, trunk_en); + rtl_set(dev, RTL_REG_TRUNK_PORTSEL, trunk_psel); + rtl_phy_restore(dev, 5, &port5); + + rtl_set(dev, RTL_REG_CPU_LINKUP, 1); + + return 0; +} + +static void +rtl_hw_init(struct switch_dev *dev) +{ + struct rtl_priv *priv = to_rtl(dev); + int cpu_mask = 1 << dev->cpu_port; + int i; + + rtl_set(dev, RTL_REG_VLAN_ENABLE, 0); + rtl_set(dev, RTL_REG_VLAN_FILTER, 0); + rtl_set(dev, RTL_REG_EN_TRUNK, 0); + rtl_set(dev, RTL_REG_TRUNK_PORTSEL, 0); + + /* initialize cpu port settings */ + if (priv->do_cpu) { + rtl_set(dev, RTL_REG_CPUPORT, dev->cpu_port); + rtl_set(dev, RTL_REG_EN_CPUPORT, 1); + } else { + rtl_set(dev, RTL_REG_CPUPORT, 7); + rtl_set(dev, RTL_REG_EN_CPUPORT, 0); + } + rtl_set(dev, RTL_REG_EN_TAG_OUT, 0); + rtl_set(dev, RTL_REG_EN_TAG_IN, 0); + rtl_set(dev, RTL_REG_EN_TAG_CLR, 0); + + /* reset all vlans */ + for (i = 0; i < RTL8306_NUM_VLANS; i++) { + rtl_set(dev, RTL_VLAN_REG(i, VID), i); + rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), 0); + } + + /* default to port isolation */ + for (i = 0; i < RTL8306_NUM_PORTS; i++) { + unsigned long mask; + + if ((1 << i) == cpu_mask) + mask = ((1 << RTL8306_NUM_PORTS) - 1) & ~cpu_mask; /* all bits set */ + else + mask = cpu_mask | (1 << i); + + rtl_set(dev, RTL_VLAN_REG(i, PORTMASK), mask); + rtl_set(dev, RTL_PORT_REG(i, PVID), i); + rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1); + rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), 1); + rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), 3); + } + rtl_hw_apply(dev); +} + +#ifdef DEBUG +static int +rtl_set_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct rtl_priv *priv = to_rtl(dev); + priv->do_cpu = val->value.i; + rtl_hw_init(dev); + return 0; +} + +static int +rtl_get_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct rtl_priv *priv = to_rtl(dev); + val->value.i = priv->do_cpu; + return 0; +} + +static int +rtl_set_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + dev->cpu_port = val->value.i; + rtl_hw_init(dev); + return 0; +} + +static int +rtl_get_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + val->value.i = dev->cpu_port; + return 0; +} +#endif + +static int +rtl_reset(struct switch_dev *dev) +{ + rtl_hw_init(dev); + return 0; +} + +static int +rtl_attr_set_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + int idx = attr->id + (val->port_vlan * attr->ofs); + struct rtl_phyregs port; + + if (attr->id >= ARRAY_SIZE(rtl_regs)) + return -EINVAL; + + if ((attr->max > 0) && (val->value.i > attr->max)) + return -EINVAL; + + /* access to phy register 22 on port 4/5 + * needs phy status save/restore */ + if ((val->port_vlan > 3) && + (rtl_regs[idx].reg == 22) && + (rtl_regs[idx].page == 0)) { + + rtl_phy_save(dev, val->port_vlan, &port); + rtl_set(dev, idx, val->value.i); + rtl_phy_restore(dev, val->port_vlan, &port); + } else { + rtl_set(dev, idx, val->value.i); + } + + return 0; +} + +static int +rtl_attr_get_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + int idx = attr->id + (val->port_vlan * attr->ofs); + + if (idx >= ARRAY_SIZE(rtl_regs)) + return -EINVAL; + + val->value.i = rtl_get(dev, idx); + return 0; +} + +static int +rtl_attr_set_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + if (val->port_vlan >= RTL8306_NUM_PORTS) + return -EINVAL; + + return rtl_attr_set_int(dev, attr, val); +} + +static int +rtl_attr_get_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + if (val->port_vlan >= RTL8306_NUM_PORTS) + return -EINVAL; + return rtl_attr_get_int(dev, attr, val); +} + +static int +rtl_get_port_link(struct switch_dev *dev, int port, struct switch_port_link *link) +{ + if (port >= RTL8306_NUM_PORTS) + return -EINVAL; + + link->link = rtl_get(dev, RTL_PORT_REG(port, LINK)); + if (!link->link) + return 0; + + link->duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX)); + link->aneg = rtl_get(dev, RTL_PORT_REG(port, NWAY)); + + if (rtl_get(dev, RTL_PORT_REG(port, SPEED))) + link->speed = SWITCH_PORT_SPEED_100; + else + link->speed = SWITCH_PORT_SPEED_10; + + return 0; +} + +static int +rtl_attr_set_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + if (val->port_vlan >= dev->vlans) + return -EINVAL; + + return rtl_attr_set_int(dev, attr, val); +} + +static int +rtl_attr_get_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + if (val->port_vlan >= dev->vlans) + return -EINVAL; + + return rtl_attr_get_int(dev, attr, val); +} + +static int +rtl_get_ports(struct switch_dev *dev, struct switch_val *val) +{ + unsigned int i, mask; + + mask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK)); + for (i = 0; i < RTL8306_NUM_PORTS; i++) { + struct switch_port *port; + + if (!(mask & (1 << i))) + continue; + + port = &val->value.ports[val->len]; + port->id = i; + if (rtl_get(dev, RTL_PORT_REG(i, TAG_INSERT)) == 2 || i == dev->cpu_port) + port->flags = (1 << SWITCH_PORT_FLAG_TAGGED); + val->len++; + } + + return 0; +} + +static int +rtl_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + struct rtl_priv *priv = to_rtl(dev); + struct rtl_phyregs port; + int en = val->value.i; + int i; + + rtl_set(dev, RTL_REG_EN_TAG_OUT, en && priv->do_cpu); + rtl_set(dev, RTL_REG_EN_TAG_IN, en && priv->do_cpu); + rtl_set(dev, RTL_REG_EN_TAG_CLR, en && priv->do_cpu); + rtl_set(dev, RTL_REG_VLAN_TAG_AWARE, en); + if (en) + rtl_set(dev, RTL_REG_VLAN_FILTER, en); + + for (i = 0; i < RTL8306_NUM_PORTS; i++) { + if (i > 3) + rtl_phy_save(dev, val->port_vlan, &port); + rtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1); + rtl_set(dev, RTL_PORT_REG(i, VID_INSERT), (en ? (i == dev->cpu_port ? 0 : 1) : 1)); + rtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), (en ? (i == dev->cpu_port ? 2 : 1) : 3)); + if (i > 3) + rtl_phy_restore(dev, val->port_vlan, &port); + } + rtl_set(dev, RTL_REG_VLAN_ENABLE, en); + + return 0; +} + +static int +rtl_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) +{ + val->value.i = rtl_get(dev, RTL_REG_VLAN_ENABLE); + return 0; +} + +static int +rtl_set_ports(struct switch_dev *dev, struct switch_val *val) +{ + unsigned int mask = 0; + unsigned int oldmask; + int i; + + for(i = 0; i < val->len; i++) + { + struct switch_port *port = &val->value.ports[i]; + bool tagged = false; + + mask |= (1 << port->id); + + if (port->id == dev->cpu_port) + continue; + + if ((i == dev->cpu_port) || + (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED))) + tagged = true; + + /* fix up PVIDs for added ports */ + if (!tagged) + rtl_set(dev, RTL_PORT_REG(port->id, PVID), val->port_vlan); + + rtl_set(dev, RTL_PORT_REG(port->id, NON_PVID_DISCARD), (tagged ? 0 : 1)); + rtl_set(dev, RTL_PORT_REG(port->id, VID_INSERT), (tagged ? 0 : 1)); + rtl_set(dev, RTL_PORT_REG(port->id, TAG_INSERT), (tagged ? 2 : 1)); + } + + oldmask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK)); + rtl_set(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK), mask); + + /* fix up PVIDs for removed ports, default to last vlan */ + oldmask &= ~mask; + for (i = 0; i < RTL8306_NUM_PORTS; i++) { + if (!(oldmask & (1 << i))) + continue; + + if (i == dev->cpu_port) + continue; + + if (rtl_get(dev, RTL_PORT_REG(i, PVID)) == val->port_vlan) + rtl_set(dev, RTL_PORT_REG(i, PVID), dev->vlans - 1); + } + + return 0; +} + +static struct switch_attr rtl_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .max = 1, + .set = rtl_set_vlan, + .get = rtl_get_vlan, + }, + { + RTL_GLOBAL_REGATTR(EN_TRUNK), + .name = "trunk", + .description = "Enable port trunking", + .max = 1, + }, + { + RTL_GLOBAL_REGATTR(TRUNK_PORTSEL), + .name = "trunk_sel", + .description = "Select ports for trunking (0: 0,1 - 1: 3,4)", + .max = 1, + }, +#ifdef DEBUG + { + RTL_GLOBAL_REGATTR(VLAN_FILTER), + .name = "vlan_filter", + .description = "Filter incoming packets for allowed VLANS", + .max = 1, + }, + { + .type = SWITCH_TYPE_INT, + .name = "cpuport", + .description = "CPU Port", + .set = rtl_set_cpuport, + .get = rtl_get_cpuport, + .max = RTL8306_NUM_PORTS, + }, + { + .type = SWITCH_TYPE_INT, + .name = "use_cpuport", + .description = "CPU Port handling flag", + .set = rtl_set_use_cpuport, + .get = rtl_get_use_cpuport, + .max = RTL8306_NUM_PORTS, + }, + { + RTL_GLOBAL_REGATTR(TRAP_CPU), + .name = "trap_cpu", + .description = "VLAN trap to CPU", + .max = 1, + }, + { + RTL_GLOBAL_REGATTR(VLAN_TAG_AWARE), + .name = "vlan_tag_aware", + .description = "Enable VLAN tag awareness", + .max = 1, + }, + { + RTL_GLOBAL_REGATTR(VLAN_TAG_ONLY), + .name = "tag_only", + .description = "Only accept tagged packets", + .max = 1, + }, +#endif +}; +static struct switch_attr rtl_port[] = { + { + RTL_PORT_REGATTR(PVID), + .name = "pvid", + .description = "Port VLAN ID", + .max = RTL8306_NUM_VLANS - 1, + }, +#ifdef DEBUG + { + RTL_PORT_REGATTR(NULL_VID_REPLACE), + .name = "null_vid", + .description = "NULL VID gets replaced by port default vid", + .max = 1, + }, + { + RTL_PORT_REGATTR(NON_PVID_DISCARD), + .name = "non_pvid_discard", + .description = "discard packets with VID != PVID", + .max = 1, + }, + { + RTL_PORT_REGATTR(VID_INSERT), + .name = "vid_insert_remove", + .description = "how should the switch insert and remove vids ?", + .max = 3, + }, + { + RTL_PORT_REGATTR(TAG_INSERT), + .name = "tag_insert", + .description = "tag insertion handling", + .max = 3, + }, +#endif +}; + +static struct switch_attr rtl_vlan[] = { + { + RTL_VLAN_REGATTR(VID), + .name = "vid", + .description = "VLAN ID (1-4095)", + .max = 4095, + }, +}; + +static const struct switch_dev_ops rtl8306_ops = { + .attr_global = { + .attr = rtl_globals, + .n_attr = ARRAY_SIZE(rtl_globals), + }, + .attr_port = { + .attr = rtl_port, + .n_attr = ARRAY_SIZE(rtl_port), + }, + .attr_vlan = { + .attr = rtl_vlan, + .n_attr = ARRAY_SIZE(rtl_vlan), + }, + + .get_vlan_ports = rtl_get_ports, + .set_vlan_ports = rtl_set_ports, + .apply_config = rtl_hw_apply, + .reset_switch = rtl_reset, + .get_port_link = rtl_get_port_link, +}; + +static int +rtl8306_config_init(struct phy_device *pdev) +{ + struct net_device *netdev = pdev->attached_dev; + struct rtl_priv *priv = pdev->priv; + struct switch_dev *dev = &priv->dev; + struct switch_val val; + unsigned int chipid, chipver, chiptype; + int err; + + /* Only init the switch for the primary PHY */ + if (pdev->addr != 0) + return 0; + + val.value.i = 1; + priv->dev.cpu_port = RTL8306_PORT_CPU; + priv->dev.ports = RTL8306_NUM_PORTS; + priv->dev.vlans = RTL8306_NUM_VLANS; + priv->dev.ops = &rtl8306_ops; + priv->do_cpu = 0; + priv->page = -1; + priv->bus = pdev->bus; + + chipid = rtl_get(dev, RTL_REG_CHIPID); + chipver = rtl_get(dev, RTL_REG_CHIPVER); + chiptype = rtl_get(dev, RTL_REG_CHIPTYPE); + switch(chiptype) { + case 0: + case 2: + strncpy(priv->hwname, RTL_NAME_S, sizeof(priv->hwname)); + priv->type = RTL_TYPE_S; + break; + case 1: + strncpy(priv->hwname, RTL_NAME_SD, sizeof(priv->hwname)); + priv->type = RTL_TYPE_SD; + break; + case 3: + strncpy(priv->hwname, RTL_NAME_SDM, sizeof(priv->hwname)); + priv->type = RTL_TYPE_SDM; + break; + default: + strncpy(priv->hwname, RTL_NAME_UNKNOWN, sizeof(priv->hwname)); + break; + } + + dev->name = priv->hwname; + rtl_hw_init(dev); + + printk(KERN_INFO "Registering %s switch with Chip ID: 0x%04x, version: 0x%04x\n", priv->hwname, chipid, chipver); + + err = register_switch(dev, netdev); + if (err < 0) { + kfree(priv); + return err; + } + + return 0; +} + + +static int +rtl8306_fixup(struct phy_device *pdev) +{ + struct rtl_priv priv; + u16 chipid; + + /* Attach to primary LAN port and WAN port */ + if (pdev->addr != 0 && pdev->addr != 4) + return 0; + + memset(&priv, 0, sizeof(priv)); + priv.fixup = true; + priv.page = -1; + priv.bus = pdev->bus; + chipid = rtl_get(&priv.dev, RTL_REG_CHIPID); + if (chipid == 0x5988) + pdev->phy_id = RTL8306_MAGIC; + + return 0; +} + +static int +rtl8306_probe(struct phy_device *pdev) +{ + struct rtl_priv *priv; + + list_for_each_entry(priv, &phydevs, list) { + /* + * share one rtl_priv instance between virtual phy + * devices on the same bus + */ + if (priv->bus == pdev->bus) + goto found; + } + priv = kzalloc(sizeof(struct rtl_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->bus = pdev->bus; + +found: + pdev->priv = priv; + return 0; +} + +static void +rtl8306_remove(struct phy_device *pdev) +{ + struct rtl_priv *priv = pdev->priv; + unregister_switch(&priv->dev); + kfree(priv); +} + +static int +rtl8306_config_aneg(struct phy_device *pdev) +{ + struct rtl_priv *priv = pdev->priv; + + /* Only for WAN */ + if (pdev->addr == 0) + return 0; + + /* Restart autonegotiation */ + rtl_set(&priv->dev, RTL_PORT_REG(4, NWAY), 1); + rtl_set(&priv->dev, RTL_PORT_REG(4, NRESTART), 1); + + return 0; +} + +static int +rtl8306_read_status(struct phy_device *pdev) +{ + struct rtl_priv *priv = pdev->priv; + struct switch_dev *dev = &priv->dev; + + if (pdev->addr == 4) { + /* WAN */ + pdev->speed = rtl_get(dev, RTL_PORT_REG(4, SPEED)) ? SPEED_100 : SPEED_10; + pdev->duplex = rtl_get(dev, RTL_PORT_REG(4, DUPLEX)) ? DUPLEX_FULL : DUPLEX_HALF; + pdev->link = !!rtl_get(dev, RTL_PORT_REG(4, LINK)); + } else { + /* LAN */ + pdev->speed = SPEED_100; + pdev->duplex = DUPLEX_FULL; + pdev->link = 1; + } + + /* + * Bypass generic PHY status read, + * it doesn't work with this switch + */ + if (pdev->link) { + pdev->state = PHY_RUNNING; + netif_carrier_on(pdev->attached_dev); + pdev->adjust_link(pdev->attached_dev); + } else { + pdev->state = PHY_NOLINK; + netif_carrier_off(pdev->attached_dev); + pdev->adjust_link(pdev->attached_dev); + } + + return 0; +} + + +static struct phy_driver rtl8306_driver = { + .name = "Realtek RTL8306S", + .flags = PHY_HAS_MAGICANEG, + .phy_id = RTL8306_MAGIC, + .phy_id_mask = 0xffffffff, + .features = PHY_BASIC_FEATURES, + .probe = &rtl8306_probe, + .remove = &rtl8306_remove, + .config_init = &rtl8306_config_init, + .config_aneg = &rtl8306_config_aneg, + .read_status = &rtl8306_read_status, + .driver = { .owner = THIS_MODULE,}, +}; + + +static int __init +rtl_init(void) +{ + phy_register_fixup_for_id(PHY_ANY_ID, rtl8306_fixup); + return phy_driver_register(&rtl8306_driver); +} + +static void __exit +rtl_exit(void) +{ + phy_driver_unregister(&rtl8306_driver); +} + +module_init(rtl_init); +module_exit(rtl_exit); +MODULE_LICENSE("GPL"); + diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c new file mode 100644 index 0000000..699234d --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.c @@ -0,0 +1,1449 @@ +/* + * Realtek RTL8366 SMI interface driver + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_RTL8366_SMI_DEBUG_FS +#include +#endif + +#include "rtl8366_smi.h" + +#define RTL8366_SMI_ACK_RETRY_COUNT 5 + +#define RTL8366_SMI_HW_STOP_DELAY 25 /* msecs */ +#define RTL8366_SMI_HW_START_DELAY 100 /* msecs */ + +static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi) +{ + ndelay(smi->clk_delay); +} + +static void rtl8366_smi_start(struct rtl8366_smi *smi) +{ + unsigned int sda = smi->gpio_sda; + unsigned int sck = smi->gpio_sck; + + /* + * Set GPIO pins to output mode, with initial state: + * SCK = 0, SDA = 1 + */ + gpio_direction_output(sck, 0); + gpio_direction_output(sda, 1); + rtl8366_smi_clk_delay(smi); + + /* CLK 1: 0 -> 1, 1 -> 0 */ + gpio_set_value(sck, 1); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sck, 0); + rtl8366_smi_clk_delay(smi); + + /* CLK 2: */ + gpio_set_value(sck, 1); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sda, 0); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sck, 0); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sda, 1); +} + +static void rtl8366_smi_stop(struct rtl8366_smi *smi) +{ + unsigned int sda = smi->gpio_sda; + unsigned int sck = smi->gpio_sck; + + rtl8366_smi_clk_delay(smi); + gpio_set_value(sda, 0); + gpio_set_value(sck, 1); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sda, 1); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sck, 1); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sck, 0); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sck, 1); + + /* add a click */ + rtl8366_smi_clk_delay(smi); + gpio_set_value(sck, 0); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sck, 1); + + /* set GPIO pins to input mode */ + gpio_direction_input(sda); + gpio_direction_input(sck); +} + +static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len) +{ + unsigned int sda = smi->gpio_sda; + unsigned int sck = smi->gpio_sck; + + for (; len > 0; len--) { + rtl8366_smi_clk_delay(smi); + + /* prepare data */ + gpio_set_value(sda, !!(data & ( 1 << (len - 1)))); + rtl8366_smi_clk_delay(smi); + + /* clocking */ + gpio_set_value(sck, 1); + rtl8366_smi_clk_delay(smi); + gpio_set_value(sck, 0); + } +} + +static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data) +{ + unsigned int sda = smi->gpio_sda; + unsigned int sck = smi->gpio_sck; + + gpio_direction_input(sda); + + for (*data = 0; len > 0; len--) { + u32 u; + + rtl8366_smi_clk_delay(smi); + + /* clocking */ + gpio_set_value(sck, 1); + rtl8366_smi_clk_delay(smi); + u = !!gpio_get_value(sda); + gpio_set_value(sck, 0); + + *data |= (u << (len - 1)); + } + + gpio_direction_output(sda, 0); +} + +static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi) +{ + int retry_cnt; + + retry_cnt = 0; + do { + u32 ack; + + rtl8366_smi_read_bits(smi, 1, &ack); + if (ack == 0) + break; + + if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT) { + dev_err(smi->parent, "ACK timeout\n"); + return -ETIMEDOUT; + } + } while (1); + + return 0; +} + +static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data) +{ + rtl8366_smi_write_bits(smi, data, 8); + return rtl8366_smi_wait_for_ack(smi); +} + +static int rtl8366_smi_write_byte_noack(struct rtl8366_smi *smi, u8 data) +{ + rtl8366_smi_write_bits(smi, data, 8); + return 0; +} + +static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data) +{ + u32 t; + + /* read data */ + rtl8366_smi_read_bits(smi, 8, &t); + *data = (t & 0xff); + + /* send an ACK */ + rtl8366_smi_write_bits(smi, 0x00, 1); + + return 0; +} + +static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data) +{ + u32 t; + + /* read data */ + rtl8366_smi_read_bits(smi, 8, &t); + *data = (t & 0xff); + + /* send an ACK */ + rtl8366_smi_write_bits(smi, 0x01, 1); + + return 0; +} + +int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data) +{ + unsigned long flags; + u8 lo = 0; + u8 hi = 0; + int ret; + + spin_lock_irqsave(&smi->lock, flags); + + rtl8366_smi_start(smi); + + /* send READ command */ + ret = rtl8366_smi_write_byte(smi, smi->cmd_read); + if (ret) + goto out; + + /* set ADDR[7:0] */ + ret = rtl8366_smi_write_byte(smi, addr & 0xff); + if (ret) + goto out; + + /* set ADDR[15:8] */ + ret = rtl8366_smi_write_byte(smi, addr >> 8); + if (ret) + goto out; + + /* read DATA[7:0] */ + rtl8366_smi_read_byte0(smi, &lo); + /* read DATA[15:8] */ + rtl8366_smi_read_byte1(smi, &hi); + + *data = ((u32) lo) | (((u32) hi) << 8); + + ret = 0; + + out: + rtl8366_smi_stop(smi); + spin_unlock_irqrestore(&smi->lock, flags); + + return ret; +} +EXPORT_SYMBOL_GPL(rtl8366_smi_read_reg); + +static int __rtl8366_smi_write_reg(struct rtl8366_smi *smi, + u32 addr, u32 data, bool ack) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&smi->lock, flags); + + rtl8366_smi_start(smi); + + /* send WRITE command */ + ret = rtl8366_smi_write_byte(smi, smi->cmd_write); + if (ret) + goto out; + + /* set ADDR[7:0] */ + ret = rtl8366_smi_write_byte(smi, addr & 0xff); + if (ret) + goto out; + + /* set ADDR[15:8] */ + ret = rtl8366_smi_write_byte(smi, addr >> 8); + if (ret) + goto out; + + /* write DATA[7:0] */ + ret = rtl8366_smi_write_byte(smi, data & 0xff); + if (ret) + goto out; + + /* write DATA[15:8] */ + if (ack) + ret = rtl8366_smi_write_byte(smi, data >> 8); + else + ret = rtl8366_smi_write_byte_noack(smi, data >> 8); + if (ret) + goto out; + + ret = 0; + + out: + rtl8366_smi_stop(smi); + spin_unlock_irqrestore(&smi->lock, flags); + + return ret; +} + +int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data) +{ + return __rtl8366_smi_write_reg(smi, addr, data, true); +} +EXPORT_SYMBOL_GPL(rtl8366_smi_write_reg); + +int rtl8366_smi_write_reg_noack(struct rtl8366_smi *smi, u32 addr, u32 data) +{ + return __rtl8366_smi_write_reg(smi, addr, data, false); +} +EXPORT_SYMBOL_GPL(rtl8366_smi_write_reg_noack); + +int rtl8366_smi_rmwr(struct rtl8366_smi *smi, u32 addr, u32 mask, u32 data) +{ + u32 t; + int err; + + err = rtl8366_smi_read_reg(smi, addr, &t); + if (err) + return err; + + err = rtl8366_smi_write_reg(smi, addr, (t & ~mask) | data); + return err; + +} +EXPORT_SYMBOL_GPL(rtl8366_smi_rmwr); + +static int rtl8366_reset(struct rtl8366_smi *smi) +{ + if (smi->hw_reset) { + smi->hw_reset(true); + msleep(RTL8366_SMI_HW_STOP_DELAY); + smi->hw_reset(false); + msleep(RTL8366_SMI_HW_START_DELAY); + return 0; + } + + return smi->ops->reset_chip(smi); +} + +static int rtl8366_mc_is_used(struct rtl8366_smi *smi, int mc_index, int *used) +{ + int err; + int i; + + *used = 0; + for (i = 0; i < smi->num_ports; i++) { + int index = 0; + + err = smi->ops->get_mc_index(smi, i, &index); + if (err) + return err; + + if (mc_index == index) { + *used = 1; + break; + } + } + + return 0; +} + +static int rtl8366_set_vlan(struct rtl8366_smi *smi, int vid, u32 member, + u32 untag, u32 fid) +{ + struct rtl8366_vlan_4k vlan4k; + int err; + int i; + + /* Update the 4K table */ + err = smi->ops->get_vlan_4k(smi, vid, &vlan4k); + if (err) + return err; + + vlan4k.member = member; + vlan4k.untag = untag; + vlan4k.fid = fid; + err = smi->ops->set_vlan_4k(smi, &vlan4k); + if (err) + return err; + + /* Try to find an existing MC entry for this VID */ + for (i = 0; i < smi->num_vlan_mc; i++) { + struct rtl8366_vlan_mc vlanmc; + + err = smi->ops->get_vlan_mc(smi, i, &vlanmc); + if (err) + return err; + + if (vid == vlanmc.vid) { + /* update the MC entry */ + vlanmc.member = member; + vlanmc.untag = untag; + vlanmc.fid = fid; + + err = smi->ops->set_vlan_mc(smi, i, &vlanmc); + break; + } + } + + return err; +} + +static int rtl8366_get_pvid(struct rtl8366_smi *smi, int port, int *val) +{ + struct rtl8366_vlan_mc vlanmc; + int err; + int index; + + err = smi->ops->get_mc_index(smi, port, &index); + if (err) + return err; + + err = smi->ops->get_vlan_mc(smi, index, &vlanmc); + if (err) + return err; + + *val = vlanmc.vid; + return 0; +} + +static int rtl8366_set_pvid(struct rtl8366_smi *smi, unsigned port, + unsigned vid) +{ + struct rtl8366_vlan_mc vlanmc; + struct rtl8366_vlan_4k vlan4k; + int err; + int i; + + /* Try to find an existing MC entry for this VID */ + for (i = 0; i < smi->num_vlan_mc; i++) { + err = smi->ops->get_vlan_mc(smi, i, &vlanmc); + if (err) + return err; + + if (vid == vlanmc.vid) { + err = smi->ops->set_vlan_mc(smi, i, &vlanmc); + if (err) + return err; + + err = smi->ops->set_mc_index(smi, port, i); + return err; + } + } + + /* We have no MC entry for this VID, try to find an empty one */ + for (i = 0; i < smi->num_vlan_mc; i++) { + err = smi->ops->get_vlan_mc(smi, i, &vlanmc); + if (err) + return err; + + if (vlanmc.vid == 0 && vlanmc.member == 0) { + /* Update the entry from the 4K table */ + err = smi->ops->get_vlan_4k(smi, vid, &vlan4k); + if (err) + return err; + + vlanmc.vid = vid; + vlanmc.member = vlan4k.member; + vlanmc.untag = vlan4k.untag; + vlanmc.fid = vlan4k.fid; + err = smi->ops->set_vlan_mc(smi, i, &vlanmc); + if (err) + return err; + + err = smi->ops->set_mc_index(smi, port, i); + return err; + } + } + + /* MC table is full, try to find an unused entry and replace it */ + for (i = 0; i < smi->num_vlan_mc; i++) { + int used; + + err = rtl8366_mc_is_used(smi, i, &used); + if (err) + return err; + + if (!used) { + /* Update the entry from the 4K table */ + err = smi->ops->get_vlan_4k(smi, vid, &vlan4k); + if (err) + return err; + + vlanmc.vid = vid; + vlanmc.member = vlan4k.member; + vlanmc.untag = vlan4k.untag; + vlanmc.fid = vlan4k.fid; + err = smi->ops->set_vlan_mc(smi, i, &vlanmc); + if (err) + return err; + + err = smi->ops->set_mc_index(smi, port, i); + return err; + } + } + + dev_err(smi->parent, + "all VLAN member configurations are in use\n"); + + return -ENOSPC; +} + +int rtl8366_enable_vlan(struct rtl8366_smi *smi, int enable) +{ + int err; + + err = smi->ops->enable_vlan(smi, enable); + if (err) + return err; + + smi->vlan_enabled = enable; + + if (!enable) { + smi->vlan4k_enabled = 0; + err = smi->ops->enable_vlan4k(smi, enable); + } + + return err; +} +EXPORT_SYMBOL_GPL(rtl8366_enable_vlan); + +static int rtl8366_enable_vlan4k(struct rtl8366_smi *smi, int enable) +{ + int err; + + if (enable) { + err = smi->ops->enable_vlan(smi, enable); + if (err) + return err; + + smi->vlan_enabled = enable; + } + + err = smi->ops->enable_vlan4k(smi, enable); + if (err) + return err; + + smi->vlan4k_enabled = enable; + return 0; +} + +int rtl8366_enable_all_ports(struct rtl8366_smi *smi, int enable) +{ + int port; + int err; + + for (port = 0; port < smi->num_ports; port++) { + err = smi->ops->enable_port(smi, port, enable); + if (err) + return err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(rtl8366_enable_all_ports); + +int rtl8366_reset_vlan(struct rtl8366_smi *smi) +{ + struct rtl8366_vlan_mc vlanmc; + int err; + int i; + + rtl8366_enable_vlan(smi, 0); + rtl8366_enable_vlan4k(smi, 0); + + /* clear VLAN member configurations */ + vlanmc.vid = 0; + vlanmc.priority = 0; + vlanmc.member = 0; + vlanmc.untag = 0; + vlanmc.fid = 0; + for (i = 0; i < smi->num_vlan_mc; i++) { + err = smi->ops->set_vlan_mc(smi, i, &vlanmc); + if (err) + return err; + } + + return 0; +} +EXPORT_SYMBOL_GPL(rtl8366_reset_vlan); + +static int rtl8366_init_vlan(struct rtl8366_smi *smi) +{ + int port; + int err; + + err = rtl8366_reset_vlan(smi); + if (err) + return err; + + for (port = 0; port < smi->num_ports; port++) { + u32 mask; + + if (port == smi->cpu_port) + mask = (1 << smi->num_ports) - 1; + else + mask = (1 << port) | (1 << smi->cpu_port); + + err = rtl8366_set_vlan(smi, (port + 1), mask, mask, 0); + if (err) + return err; + + err = rtl8366_set_pvid(smi, port, (port + 1)); + if (err) + return err; + } + + return rtl8366_enable_vlan(smi, 1); +} + +#ifdef CONFIG_RTL8366_SMI_DEBUG_FS +int rtl8366_debugfs_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} +EXPORT_SYMBOL_GPL(rtl8366_debugfs_open); + +static ssize_t rtl8366_read_debugfs_vlan_mc(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data; + int i, len = 0; + char *buf = smi->buf; + + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%2s %6s %4s %6s %6s %3s\n", + "id", "vid","prio", "member", "untag", "fid"); + + for (i = 0; i < smi->num_vlan_mc; ++i) { + struct rtl8366_vlan_mc vlanmc; + + smi->ops->get_vlan_mc(smi, i, &vlanmc); + + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%2d %6d %4d 0x%04x 0x%04x %3d\n", + i, vlanmc.vid, vlanmc.priority, + vlanmc.member, vlanmc.untag, vlanmc.fid); + } + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +#define RTL8366_VLAN4K_PAGE_SIZE 64 +#define RTL8366_VLAN4K_NUM_PAGES (4096 / RTL8366_VLAN4K_PAGE_SIZE) + +static ssize_t rtl8366_read_debugfs_vlan_4k(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data; + int i, len = 0; + int offset; + char *buf = smi->buf; + + if (smi->dbg_vlan_4k_page >= RTL8366_VLAN4K_NUM_PAGES) { + len += snprintf(buf + len, sizeof(smi->buf) - len, + "invalid page: %u\n", smi->dbg_vlan_4k_page); + return simple_read_from_buffer(user_buf, count, ppos, buf, len); + } + + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%4s %6s %6s %3s\n", + "vid", "member", "untag", "fid"); + + offset = RTL8366_VLAN4K_PAGE_SIZE * smi->dbg_vlan_4k_page; + for (i = 0; i < RTL8366_VLAN4K_PAGE_SIZE; i++) { + struct rtl8366_vlan_4k vlan4k; + + smi->ops->get_vlan_4k(smi, offset + i, &vlan4k); + + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%4d 0x%04x 0x%04x %3d\n", + vlan4k.vid, vlan4k.member, + vlan4k.untag, vlan4k.fid); + } + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t rtl8366_read_debugfs_pvid(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data; + char *buf = smi->buf; + int len = 0; + int i; + + len += snprintf(buf + len, sizeof(smi->buf) - len, "%4s %4s\n", + "port", "pvid"); + + for (i = 0; i < smi->num_ports; i++) { + int pvid; + int err; + + err = rtl8366_get_pvid(smi, i, &pvid); + if (err) + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%4d error\n", i); + else + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%4d %4d\n", i, pvid); + } + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t rtl8366_read_debugfs_reg(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data; + u32 t, reg = smi->dbg_reg; + int err, len = 0; + char *buf = smi->buf; + + memset(buf, '\0', sizeof(smi->buf)); + + err = rtl8366_smi_read_reg(smi, reg, &t); + if (err) { + len += snprintf(buf, sizeof(smi->buf), + "Read failed (reg: 0x%04x)\n", reg); + return simple_read_from_buffer(user_buf, count, ppos, buf, len); + } + + len += snprintf(buf, sizeof(smi->buf), "reg = 0x%04x, val = 0x%04x\n", + reg, t); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t rtl8366_write_debugfs_reg(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data; + unsigned long data; + u32 reg = smi->dbg_reg; + int err; + size_t len; + char *buf = smi->buf; + + len = min(count, sizeof(smi->buf) - 1); + if (copy_from_user(buf, user_buf, len)) { + dev_err(smi->parent, "copy from user failed\n"); + return -EFAULT; + } + + buf[len] = '\0'; + if (len > 0 && buf[len - 1] == '\n') + buf[len - 1] = '\0'; + + + if (kstrtoul(buf, 16, &data)) { + dev_err(smi->parent, "Invalid reg value %s\n", buf); + } else { + err = rtl8366_smi_write_reg(smi, reg, data); + if (err) { + dev_err(smi->parent, + "writing reg 0x%04x val 0x%04lx failed\n", + reg, data); + } + } + + return count; +} + +static ssize_t rtl8366_read_debugfs_mibs(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct rtl8366_smi *smi = file->private_data; + int i, j, len = 0; + char *buf = smi->buf; + + len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s", + "Counter"); + + for (i = 0; i < smi->num_ports; i++) { + char port_buf[10]; + + snprintf(port_buf, sizeof(port_buf), "Port %d", i); + len += snprintf(buf + len, sizeof(smi->buf) - len, " %12s", + port_buf); + } + len += snprintf(buf + len, sizeof(smi->buf) - len, "\n"); + + for (i = 0; i < smi->num_mib_counters; i++) { + len += snprintf(buf + len, sizeof(smi->buf) - len, "%-36s ", + smi->mib_counters[i].name); + for (j = 0; j < smi->num_ports; j++) { + unsigned long long counter = 0; + + if (!smi->ops->get_mib_counter(smi, i, j, &counter)) + len += snprintf(buf + len, + sizeof(smi->buf) - len, + "%12llu ", counter); + else + len += snprintf(buf + len, + sizeof(smi->buf) - len, + "%12s ", "error"); + } + len += snprintf(buf + len, sizeof(smi->buf) - len, "\n"); + } + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_rtl8366_regs = { + .read = rtl8366_read_debugfs_reg, + .write = rtl8366_write_debugfs_reg, + .open = rtl8366_debugfs_open, + .owner = THIS_MODULE +}; + +static const struct file_operations fops_rtl8366_vlan_mc = { + .read = rtl8366_read_debugfs_vlan_mc, + .open = rtl8366_debugfs_open, + .owner = THIS_MODULE +}; + +static const struct file_operations fops_rtl8366_vlan_4k = { + .read = rtl8366_read_debugfs_vlan_4k, + .open = rtl8366_debugfs_open, + .owner = THIS_MODULE +}; + +static const struct file_operations fops_rtl8366_pvid = { + .read = rtl8366_read_debugfs_pvid, + .open = rtl8366_debugfs_open, + .owner = THIS_MODULE +}; + +static const struct file_operations fops_rtl8366_mibs = { + .read = rtl8366_read_debugfs_mibs, + .open = rtl8366_debugfs_open, + .owner = THIS_MODULE +}; + +static void rtl8366_debugfs_init(struct rtl8366_smi *smi) +{ + struct dentry *node; + struct dentry *root; + + if (!smi->debugfs_root) + smi->debugfs_root = debugfs_create_dir(dev_name(smi->parent), + NULL); + + if (!smi->debugfs_root) { + dev_err(smi->parent, "Unable to create debugfs dir\n"); + return; + } + root = smi->debugfs_root; + + node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, + &smi->dbg_reg); + if (!node) { + dev_err(smi->parent, "Creating debugfs file '%s' failed\n", + "reg"); + return; + } + + node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi, + &fops_rtl8366_regs); + if (!node) { + dev_err(smi->parent, "Creating debugfs file '%s' failed\n", + "val"); + return; + } + + node = debugfs_create_file("vlan_mc", S_IRUSR, root, smi, + &fops_rtl8366_vlan_mc); + if (!node) { + dev_err(smi->parent, "Creating debugfs file '%s' failed\n", + "vlan_mc"); + return; + } + + node = debugfs_create_u8("vlan_4k_page", S_IRUGO | S_IWUSR, root, + &smi->dbg_vlan_4k_page); + if (!node) { + dev_err(smi->parent, "Creating debugfs file '%s' failed\n", + "vlan_4k_page"); + return; + } + + node = debugfs_create_file("vlan_4k", S_IRUSR, root, smi, + &fops_rtl8366_vlan_4k); + if (!node) { + dev_err(smi->parent, "Creating debugfs file '%s' failed\n", + "vlan_4k"); + return; + } + + node = debugfs_create_file("pvid", S_IRUSR, root, smi, + &fops_rtl8366_pvid); + if (!node) { + dev_err(smi->parent, "Creating debugfs file '%s' failed\n", + "pvid"); + return; + } + + node = debugfs_create_file("mibs", S_IRUSR, smi->debugfs_root, smi, + &fops_rtl8366_mibs); + if (!node) + dev_err(smi->parent, "Creating debugfs file '%s' failed\n", + "mibs"); +} + +static void rtl8366_debugfs_remove(struct rtl8366_smi *smi) +{ + if (smi->debugfs_root) { + debugfs_remove_recursive(smi->debugfs_root); + smi->debugfs_root = NULL; + } +} +#else +static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {} +static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {} +#endif /* CONFIG_RTL8366_SMI_DEBUG_FS */ + +static int rtl8366_smi_mii_init(struct rtl8366_smi *smi) +{ + int ret; + int i; + + smi->mii_bus = mdiobus_alloc(); + if (smi->mii_bus == NULL) { + ret = -ENOMEM; + goto err; + } + + smi->mii_bus->priv = (void *) smi; + smi->mii_bus->name = dev_name(smi->parent); + smi->mii_bus->read = smi->ops->mii_read; + smi->mii_bus->write = smi->ops->mii_write; + snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s", + dev_name(smi->parent)); + smi->mii_bus->parent = smi->parent; + smi->mii_bus->phy_mask = ~(0x1f); + smi->mii_bus->irq = smi->mii_irq; + for (i = 0; i < PHY_MAX_ADDR; i++) + smi->mii_irq[i] = PHY_POLL; + + ret = mdiobus_register(smi->mii_bus); + if (ret) + goto err_free; + + return 0; + + err_free: + mdiobus_free(smi->mii_bus); + err: + return ret; +} + +static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi) +{ + mdiobus_unregister(smi->mii_bus); + mdiobus_free(smi->mii_bus); +} + +int rtl8366_sw_reset_switch(struct switch_dev *dev) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + int err; + + err = rtl8366_reset(smi); + if (err) + return err; + + err = smi->ops->setup(smi); + if (err) + return err; + + err = rtl8366_reset_vlan(smi); + if (err) + return err; + + err = rtl8366_enable_vlan(smi, 1); + if (err) + return err; + + return rtl8366_enable_all_ports(smi, 1); +} +EXPORT_SYMBOL_GPL(rtl8366_sw_reset_switch); + +int rtl8366_sw_get_port_pvid(struct switch_dev *dev, int port, int *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + return rtl8366_get_pvid(smi, port, val); +} +EXPORT_SYMBOL_GPL(rtl8366_sw_get_port_pvid); + +int rtl8366_sw_set_port_pvid(struct switch_dev *dev, int port, int val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + return rtl8366_set_pvid(smi, port, val); +} +EXPORT_SYMBOL_GPL(rtl8366_sw_set_port_pvid); + +int rtl8366_sw_get_port_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + int i, len = 0; + unsigned long long counter = 0; + char *buf = smi->buf; + + if (val->port_vlan >= smi->num_ports) + return -EINVAL; + + len += snprintf(buf + len, sizeof(smi->buf) - len, + "Port %d MIB counters\n", + val->port_vlan); + + for (i = 0; i < smi->num_mib_counters; ++i) { + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%-36s: ", smi->mib_counters[i].name); + if (!smi->ops->get_mib_counter(smi, i, val->port_vlan, + &counter)) + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%llu\n", counter); + else + len += snprintf(buf + len, sizeof(smi->buf) - len, + "%s\n", "error"); + } + + val->value.s = buf; + val->len = len; + return 0; +} +EXPORT_SYMBOL_GPL(rtl8366_sw_get_port_mib); + +int rtl8366_sw_get_vlan_info(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + int i; + u32 len = 0; + struct rtl8366_vlan_4k vlan4k; + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + char *buf = smi->buf; + int err; + + if (!smi->ops->is_vlan_valid(smi, val->port_vlan)) + return -EINVAL; + + memset(buf, '\0', sizeof(smi->buf)); + + err = smi->ops->get_vlan_4k(smi, val->port_vlan, &vlan4k); + if (err) + return err; + + len += snprintf(buf + len, sizeof(smi->buf) - len, + "VLAN %d: Ports: '", vlan4k.vid); + + for (i = 0; i < smi->num_ports; i++) { + if (!(vlan4k.member & (1 << i))) + continue; + + len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i, + (vlan4k.untag & (1 << i)) ? "" : "t"); + } + + len += snprintf(buf + len, sizeof(smi->buf) - len, + "', members=%04x, untag=%04x, fid=%u", + vlan4k.member, vlan4k.untag, vlan4k.fid); + + val->value.s = buf; + val->len = len; + + return 0; +} +EXPORT_SYMBOL_GPL(rtl8366_sw_get_vlan_info); + +int rtl8366_sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + struct switch_port *port; + struct rtl8366_vlan_4k vlan4k; + int i; + + if (!smi->ops->is_vlan_valid(smi, val->port_vlan)) + return -EINVAL; + + smi->ops->get_vlan_4k(smi, val->port_vlan, &vlan4k); + + port = &val->value.ports[0]; + val->len = 0; + for (i = 0; i < smi->num_ports; i++) { + if (!(vlan4k.member & BIT(i))) + continue; + + port->id = i; + port->flags = (vlan4k.untag & BIT(i)) ? + 0 : BIT(SWITCH_PORT_FLAG_TAGGED); + val->len++; + port++; + } + return 0; +} +EXPORT_SYMBOL_GPL(rtl8366_sw_get_vlan_ports); + +int rtl8366_sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + struct switch_port *port; + u32 member = 0; + u32 untag = 0; + int err; + int i; + + if (!smi->ops->is_vlan_valid(smi, val->port_vlan)) + return -EINVAL; + + port = &val->value.ports[0]; + for (i = 0; i < val->len; i++, port++) { + int pvid = 0; + member |= BIT(port->id); + + if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) + untag |= BIT(port->id); + + /* + * To ensure that we have a valid MC entry for this VLAN, + * initialize the port VLAN ID here. + */ + err = rtl8366_get_pvid(smi, port->id, &pvid); + if (err < 0) + return err; + if (pvid == 0) { + err = rtl8366_set_pvid(smi, port->id, val->port_vlan); + if (err < 0) + return err; + } + } + + return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0); +} +EXPORT_SYMBOL_GPL(rtl8366_sw_set_vlan_ports); + +int rtl8366_sw_get_vlan_fid(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_vlan_4k vlan4k; + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + int err; + + if (!smi->ops->is_vlan_valid(smi, val->port_vlan)) + return -EINVAL; + + err = smi->ops->get_vlan_4k(smi, val->port_vlan, &vlan4k); + if (err) + return err; + + val->value.i = vlan4k.fid; + + return 0; +} +EXPORT_SYMBOL_GPL(rtl8366_sw_get_vlan_fid); + +int rtl8366_sw_set_vlan_fid(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_vlan_4k vlan4k; + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + int err; + + if (!smi->ops->is_vlan_valid(smi, val->port_vlan)) + return -EINVAL; + + if (val->value.i < 0 || val->value.i > attr->max) + return -EINVAL; + + err = smi->ops->get_vlan_4k(smi, val->port_vlan, &vlan4k); + if (err) + return err; + + return rtl8366_set_vlan(smi, val->port_vlan, + vlan4k.member, + vlan4k.untag, + val->value.i); +} +EXPORT_SYMBOL_GPL(rtl8366_sw_set_vlan_fid); + +int rtl8366_sw_get_vlan_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (attr->ofs > 2) + return -EINVAL; + + if (attr->ofs == 1) + val->value.i = smi->vlan_enabled; + else + val->value.i = smi->vlan4k_enabled; + + return 0; +} +EXPORT_SYMBOL_GPL(rtl8366_sw_get_vlan_enable); + +int rtl8366_sw_set_vlan_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + int err; + + if (attr->ofs > 2) + return -EINVAL; + + if (attr->ofs == 1) + err = rtl8366_enable_vlan(smi, val->value.i); + else + err = rtl8366_enable_vlan4k(smi, val->value.i); + + return err; +} +EXPORT_SYMBOL_GPL(rtl8366_sw_set_vlan_enable); + +struct rtl8366_smi *rtl8366_smi_alloc(struct device *parent) +{ + struct rtl8366_smi *smi; + + BUG_ON(!parent); + + smi = kzalloc(sizeof(*smi), GFP_KERNEL); + if (!smi) { + dev_err(parent, "no memory for private data\n"); + return NULL; + } + + smi->parent = parent; + return smi; +} +EXPORT_SYMBOL_GPL(rtl8366_smi_alloc); + +static int __rtl8366_smi_init(struct rtl8366_smi *smi, const char *name) +{ + int err; + + err = gpio_request(smi->gpio_sda, name); + if (err) { + printk(KERN_ERR "rtl8366_smi: gpio_request failed for %u, err=%d\n", + smi->gpio_sda, err); + goto err_out; + } + + err = gpio_request(smi->gpio_sck, name); + if (err) { + printk(KERN_ERR "rtl8366_smi: gpio_request failed for %u, err=%d\n", + smi->gpio_sck, err); + goto err_free_sda; + } + + spin_lock_init(&smi->lock); + + /* start the switch */ + if (smi->hw_reset) { + smi->hw_reset(false); + msleep(RTL8366_SMI_HW_START_DELAY); + } + + return 0; + + err_free_sda: + gpio_free(smi->gpio_sda); + err_out: + return err; +} + +static void __rtl8366_smi_cleanup(struct rtl8366_smi *smi) +{ + if (smi->hw_reset) + smi->hw_reset(true); + + gpio_free(smi->gpio_sck); + gpio_free(smi->gpio_sda); +} + +enum rtl8366_type rtl8366_smi_detect(struct rtl8366_platform_data *pdata) +{ + static struct rtl8366_smi smi; + enum rtl8366_type type = RTL8366_TYPE_UNKNOWN; + u32 reg = 0; + + memset(&smi, 0, sizeof(smi)); + smi.gpio_sda = pdata->gpio_sda; + smi.gpio_sck = pdata->gpio_sck; + smi.clk_delay = 10; + smi.cmd_read = 0xa9; + smi.cmd_write = 0xa8; + + if (__rtl8366_smi_init(&smi, "rtl8366")) + goto out; + + if (rtl8366_smi_read_reg(&smi, 0x5c, ®)) + goto cleanup; + + switch(reg) { + case 0x6027: + printk("Found an RTL8366S switch\n"); + type = RTL8366_TYPE_S; + break; + case 0x5937: + printk("Found an RTL8366RB switch\n"); + type = RTL8366_TYPE_RB; + break; + default: + printk("Found an Unknown RTL8366 switch (id=0x%04x)\n", reg); + break; + } + +cleanup: + __rtl8366_smi_cleanup(&smi); +out: + return type; +} + +int rtl8366_smi_init(struct rtl8366_smi *smi) +{ + int err; + + if (!smi->ops) + return -EINVAL; + + err = __rtl8366_smi_init(smi, dev_name(smi->parent)); + if (err) + goto err_out; + + dev_info(smi->parent, "using GPIO pins %u (SDA) and %u (SCK)\n", + smi->gpio_sda, smi->gpio_sck); + + err = smi->ops->detect(smi); + if (err) { + dev_err(smi->parent, "chip detection failed, err=%d\n", err); + goto err_free_sck; + } + + err = rtl8366_reset(smi); + if (err) + goto err_free_sck; + + err = smi->ops->setup(smi); + if (err) { + dev_err(smi->parent, "chip setup failed, err=%d\n", err); + goto err_free_sck; + } + + err = rtl8366_init_vlan(smi); + if (err) { + dev_err(smi->parent, "VLAN initialization failed, err=%d\n", + err); + goto err_free_sck; + } + + err = rtl8366_enable_all_ports(smi, 1); + if (err) + goto err_free_sck; + + err = rtl8366_smi_mii_init(smi); + if (err) + goto err_free_sck; + + rtl8366_debugfs_init(smi); + + return 0; + + err_free_sck: + __rtl8366_smi_cleanup(smi); + err_out: + return err; +} +EXPORT_SYMBOL_GPL(rtl8366_smi_init); + +void rtl8366_smi_cleanup(struct rtl8366_smi *smi) +{ + rtl8366_debugfs_remove(smi); + rtl8366_smi_mii_cleanup(smi); + __rtl8366_smi_cleanup(smi); +} +EXPORT_SYMBOL_GPL(rtl8366_smi_cleanup); + +#ifdef CONFIG_OF +int rtl8366_smi_probe_of(struct platform_device *pdev, struct rtl8366_smi *smi) +{ + int sck = of_get_named_gpio(pdev->dev.of_node, "gpio-sck", 0); + int sda = of_get_named_gpio(pdev->dev.of_node, "gpio-sda", 0); + + if (!gpio_is_valid(sck) || !gpio_is_valid(sda)) { + dev_err(&pdev->dev, "gpios missing in devictree\n"); + return -EINVAL; + } + + smi->gpio_sda = sda; + smi->gpio_sck = sck; + + return 0; +} +#else +static inline int rtl8366_smi_probe_of(struct platform_device *pdev, struct rtl8366_smi *smi) +{ + return -ENODEV; +} +#endif + +int rtl8366_smi_probe_plat(struct platform_device *pdev, struct rtl8366_smi *smi) +{ + struct rtl8366_platform_data *pdata = pdev->dev.platform_data; + + if (!pdev->dev.platform_data) { + dev_err(&pdev->dev, "no platform data specified\n"); + return -EINVAL; + } + + smi->gpio_sda = pdata->gpio_sda; + smi->gpio_sck = pdata->gpio_sck; + smi->hw_reset = pdata->hw_reset; + + return 0; +} + + +struct rtl8366_smi *rtl8366_smi_probe(struct platform_device *pdev) +{ + struct rtl8366_smi *smi; + int err; + + smi = rtl8366_smi_alloc(&pdev->dev); + if (!smi) + return NULL; + + if (pdev->dev.of_node) + err = rtl8366_smi_probe_of(pdev, smi); + else + err = rtl8366_smi_probe_plat(pdev, smi); + + if (err) + goto free_smi; + + return smi; + +free_smi: + kfree(smi); + return NULL; +} +EXPORT_SYMBOL_GPL(rtl8366_smi_probe); + +MODULE_DESCRIPTION("Realtek RTL8366 SMI interface driver"); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h new file mode 100644 index 0000000..bd41385 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/rtl8366_smi.h @@ -0,0 +1,152 @@ +/* + * Realtek RTL8366 SMI interface driver defines + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RTL8366_SMI_H +#define _RTL8366_SMI_H + +#include +#include +#include + +struct rtl8366_smi_ops; +struct rtl8366_vlan_ops; +struct mii_bus; +struct dentry; +struct inode; +struct file; + +struct rtl8366_mib_counter { + unsigned base; + unsigned offset; + unsigned length; + const char *name; +}; + +struct rtl8366_smi { + struct device *parent; + unsigned int gpio_sda; + unsigned int gpio_sck; + void (*hw_reset)(bool active); + unsigned int clk_delay; /* ns */ + u8 cmd_read; + u8 cmd_write; + spinlock_t lock; + struct mii_bus *mii_bus; + int mii_irq[PHY_MAX_ADDR]; + struct switch_dev sw_dev; + + unsigned int cpu_port; + unsigned int num_ports; + unsigned int num_vlan_mc; + unsigned int num_mib_counters; + struct rtl8366_mib_counter *mib_counters; + + struct rtl8366_smi_ops *ops; + + int vlan_enabled; + int vlan4k_enabled; + + char buf[4096]; +#ifdef CONFIG_RTL8366_SMI_DEBUG_FS + struct dentry *debugfs_root; + u16 dbg_reg; + u8 dbg_vlan_4k_page; +#endif +}; + +struct rtl8366_vlan_mc { + u16 vid; + u16 untag; + u16 member; + u8 fid; + u8 priority; +}; + +struct rtl8366_vlan_4k { + u16 vid; + u16 untag; + u16 member; + u8 fid; +}; + +struct rtl8366_smi_ops { + int (*detect)(struct rtl8366_smi *smi); + int (*reset_chip)(struct rtl8366_smi *smi); + int (*setup)(struct rtl8366_smi *smi); + + int (*mii_read)(struct mii_bus *bus, int addr, int reg); + int (*mii_write)(struct mii_bus *bus, int addr, int reg, u16 val); + + int (*get_vlan_mc)(struct rtl8366_smi *smi, u32 index, + struct rtl8366_vlan_mc *vlanmc); + int (*set_vlan_mc)(struct rtl8366_smi *smi, u32 index, + const struct rtl8366_vlan_mc *vlanmc); + int (*get_vlan_4k)(struct rtl8366_smi *smi, u32 vid, + struct rtl8366_vlan_4k *vlan4k); + int (*set_vlan_4k)(struct rtl8366_smi *smi, + const struct rtl8366_vlan_4k *vlan4k); + int (*get_mc_index)(struct rtl8366_smi *smi, int port, int *val); + int (*set_mc_index)(struct rtl8366_smi *smi, int port, int index); + int (*get_mib_counter)(struct rtl8366_smi *smi, int counter, + int port, unsigned long long *val); + int (*is_vlan_valid)(struct rtl8366_smi *smi, unsigned vlan); + int (*enable_vlan)(struct rtl8366_smi *smi, int enable); + int (*enable_vlan4k)(struct rtl8366_smi *smi, int enable); + int (*enable_port)(struct rtl8366_smi *smi, int port, int enable); +}; + +struct rtl8366_smi *rtl8366_smi_alloc(struct device *parent); +int rtl8366_smi_init(struct rtl8366_smi *smi); +void rtl8366_smi_cleanup(struct rtl8366_smi *smi); +int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data); +int rtl8366_smi_write_reg_noack(struct rtl8366_smi *smi, u32 addr, u32 data); +int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data); +int rtl8366_smi_rmwr(struct rtl8366_smi *smi, u32 addr, u32 mask, u32 data); + +int rtl8366_reset_vlan(struct rtl8366_smi *smi); +int rtl8366_enable_vlan(struct rtl8366_smi *smi, int enable); +int rtl8366_enable_all_ports(struct rtl8366_smi *smi, int enable); + +#ifdef CONFIG_RTL8366_SMI_DEBUG_FS +int rtl8366_debugfs_open(struct inode *inode, struct file *file); +#endif + +static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw) +{ + return container_of(sw, struct rtl8366_smi, sw_dev); +} + +int rtl8366_sw_reset_switch(struct switch_dev *dev); +int rtl8366_sw_get_port_pvid(struct switch_dev *dev, int port, int *val); +int rtl8366_sw_set_port_pvid(struct switch_dev *dev, int port, int val); +int rtl8366_sw_get_port_mib(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int rtl8366_sw_get_vlan_info(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int rtl8366_sw_get_vlan_fid(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int rtl8366_sw_set_vlan_fid(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int rtl8366_sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val); +int rtl8366_sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val); +int rtl8366_sw_get_vlan_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); +int rtl8366_sw_set_vlan_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val); + +struct rtl8366_smi* rtl8366_smi_probe(struct platform_device *pdev); + +#endif /* _RTL8366_SMI_H */ diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366rb.c b/target/linux/generic/files/drivers/net/phy/rtl8366rb.c new file mode 100644 index 0000000..f4ec748 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/rtl8366rb.c @@ -0,0 +1,1496 @@ +/* + * Platform driver for the Realtek RTL8366RB ethernet switch + * + * Copyright (C) 2009-2010 Gabor Juhos + * Copyright (C) 2010 Antti Seppälä + * Copyright (C) 2010 Roman Yeryomin + * Copyright (C) 2011 Colin Leitner + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtl8366_smi.h" + +#define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver" +#define RTL8366RB_DRIVER_VER "0.2.4" + +#define RTL8366RB_PHY_NO_MAX 4 +#define RTL8366RB_PHY_PAGE_MAX 7 +#define RTL8366RB_PHY_ADDR_MAX 31 + +/* Switch Global Configuration register */ +#define RTL8366RB_SGCR 0x0000 +#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0) +#define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4) +#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3) +#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0) +#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1) +#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2) +#define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3) +#define RTL8366RB_SGCR_EN_VLAN BIT(13) +#define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14) + +/* Port Enable Control register */ +#define RTL8366RB_PECR 0x0001 + +/* Port Mirror Control Register */ +#define RTL8366RB_PMCR 0x0007 +#define RTL8366RB_PMCR_SOURCE_PORT(_x) (_x) +#define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f +#define RTL8366RB_PMCR_MONITOR_PORT(_x) ((_x) << 4) +#define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0 +#define RTL8366RB_PMCR_MIRROR_RX BIT(8) +#define RTL8366RB_PMCR_MIRROR_TX BIT(9) +#define RTL8366RB_PMCR_MIRROR_SPC BIT(10) +#define RTL8366RB_PMCR_MIRROR_ISO BIT(11) + +/* Switch Security Control registers */ +#define RTL8366RB_SSCR0 0x0002 +#define RTL8366RB_SSCR1 0x0003 +#define RTL8366RB_SSCR2 0x0004 +#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0) + +#define RTL8366RB_RESET_CTRL_REG 0x0100 +#define RTL8366RB_CHIP_CTRL_RESET_HW 1 +#define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1) + +#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A +#define RTL8366RB_CHIP_VERSION_MASK 0xf +#define RTL8366RB_CHIP_ID_REG 0x0509 +#define RTL8366RB_CHIP_ID_8366 0x5937 + +/* PHY registers control */ +#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000 +#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002 + +#define RTL8366RB_PHY_CTRL_READ 1 +#define RTL8366RB_PHY_CTRL_WRITE 0 + +#define RTL8366RB_PHY_REG_MASK 0x1f +#define RTL8366RB_PHY_PAGE_OFFSET 5 +#define RTL8366RB_PHY_PAGE_MASK (0xf << 5) +#define RTL8366RB_PHY_NO_OFFSET 9 +#define RTL8366RB_PHY_NO_MASK (0x1f << 9) + +#define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f + +/* LED control registers */ +#define RTL8366RB_LED_BLINKRATE_REG 0x0430 +#define RTL8366RB_LED_BLINKRATE_BIT 0 +#define RTL8366RB_LED_BLINKRATE_MASK 0x0007 + +#define RTL8366RB_LED_CTRL_REG 0x0431 +#define RTL8366RB_LED_0_1_CTRL_REG 0x0432 +#define RTL8366RB_LED_2_3_CTRL_REG 0x0433 + +#define RTL8366RB_MIB_COUNT 33 +#define RTL8366RB_GLOBAL_MIB_COUNT 1 +#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050 +#define RTL8366RB_MIB_COUNTER_BASE 0x1000 +#define RTL8366RB_MIB_CTRL_REG 0x13F0 +#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC +#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0) +#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1) +#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p)) +#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11) + +#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063 +#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \ + (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4) +#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf +#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) + + +#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C +#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185 + + +#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180 +#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01 +#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01 + +#define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3) + + +#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014 +#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003 +#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004 +#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010 +#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020 +#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040 +#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080 + + +#define RTL8366RB_PORT_NUM_CPU 5 +#define RTL8366RB_NUM_PORTS 6 +#define RTL8366RB_NUM_VLANS 16 +#define RTL8366RB_NUM_LEDGROUPS 4 +#define RTL8366RB_NUM_VIDS 4096 +#define RTL8366RB_PRIORITYMAX 7 +#define RTL8366RB_FIDMAX 7 + + +#define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */ +#define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */ +#define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */ +#define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */ +#define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */ + +#define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */ + +#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \ + RTL8366RB_PORT_2 | \ + RTL8366RB_PORT_3 | \ + RTL8366RB_PORT_4 | \ + RTL8366RB_PORT_5 | \ + RTL8366RB_PORT_CPU) + +#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \ + RTL8366RB_PORT_2 | \ + RTL8366RB_PORT_3 | \ + RTL8366RB_PORT_4 | \ + RTL8366RB_PORT_5) + +#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \ + RTL8366RB_PORT_2 | \ + RTL8366RB_PORT_3 | \ + RTL8366RB_PORT_4) + +#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU + +#define RTL8366RB_VLAN_VID_MASK 0xfff +#define RTL8366RB_VLAN_PRIORITY_SHIFT 12 +#define RTL8366RB_VLAN_PRIORITY_MASK 0x7 +#define RTL8366RB_VLAN_UNTAG_SHIFT 8 +#define RTL8366RB_VLAN_UNTAG_MASK 0xff +#define RTL8366RB_VLAN_MEMBER_MASK 0xff +#define RTL8366RB_VLAN_FID_MASK 0x7 + + +/* Port ingress bandwidth control */ +#define RTL8366RB_IB_BASE 0x0200 +#define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum) +#define RTL8366RB_IB_BDTH_MASK 0x3fff +#define RTL8366RB_IB_PREIFG_OFFSET 14 +#define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET) + +/* Port egress bandwidth control */ +#define RTL8366RB_EB_BASE 0x02d1 +#define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum) +#define RTL8366RB_EB_BDTH_MASK 0x3fff +#define RTL8366RB_EB_PREIFG_REG 0x02f8 +#define RTL8366RB_EB_PREIFG_OFFSET 9 +#define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET) + +#define RTL8366RB_BDTH_SW_MAX 1048512 +#define RTL8366RB_BDTH_UNIT 64 +#define RTL8366RB_BDTH_REG_DEFAULT 16383 + +/* QOS */ +#define RTL8366RB_QOS_BIT 15 +#define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT) +/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */ +#define RTL8366RB_QOS_DEFAULT_PREIFG 1 + + +static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = { + { 0, 0, 4, "IfInOctets" }, + { 0, 4, 4, "EtherStatsOctets" }, + { 0, 8, 2, "EtherStatsUnderSizePkts" }, + { 0, 10, 2, "EtherFragments" }, + { 0, 12, 2, "EtherStatsPkts64Octets" }, + { 0, 14, 2, "EtherStatsPkts65to127Octets" }, + { 0, 16, 2, "EtherStatsPkts128to255Octets" }, + { 0, 18, 2, "EtherStatsPkts256to511Octets" }, + { 0, 20, 2, "EtherStatsPkts512to1023Octets" }, + { 0, 22, 2, "EtherStatsPkts1024to1518Octets" }, + { 0, 24, 2, "EtherOversizeStats" }, + { 0, 26, 2, "EtherStatsJabbers" }, + { 0, 28, 2, "IfInUcastPkts" }, + { 0, 30, 2, "EtherStatsMulticastPkts" }, + { 0, 32, 2, "EtherStatsBroadcastPkts" }, + { 0, 34, 2, "EtherStatsDropEvents" }, + { 0, 36, 2, "Dot3StatsFCSErrors" }, + { 0, 38, 2, "Dot3StatsSymbolErrors" }, + { 0, 40, 2, "Dot3InPauseFrames" }, + { 0, 42, 2, "Dot3ControlInUnknownOpcodes" }, + { 0, 44, 4, "IfOutOctets" }, + { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, + { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, + { 0, 52, 2, "Dot3sDeferredTransmissions" }, + { 0, 54, 2, "Dot3StatsLateCollisions" }, + { 0, 56, 2, "EtherStatsCollisions" }, + { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, + { 0, 60, 2, "Dot3OutPauseFrames" }, + { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, + { 0, 64, 2, "Dot1dTpPortInDiscards" }, + { 0, 66, 2, "IfOutUcastPkts" }, + { 0, 68, 2, "IfOutMulticastPkts" }, + { 0, 70, 2, "IfOutBroadcastPkts" }, +}; + +#define REG_WR(_smi, _reg, _val) \ + do { \ + err = rtl8366_smi_write_reg(_smi, _reg, _val); \ + if (err) \ + return err; \ + } while (0) + +#define REG_RMW(_smi, _reg, _mask, _val) \ + do { \ + err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \ + if (err) \ + return err; \ + } while (0) + +static int rtl8366rb_reset_chip(struct rtl8366_smi *smi) +{ + int timeout = 10; + u32 data; + + rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG, + RTL8366RB_CHIP_CTRL_RESET_HW); + do { + msleep(1); + if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data)) + return -EIO; + + if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW)) + break; + } while (--timeout); + + if (!timeout) { + printk("Timeout waiting for the switch to reset\n"); + return -EIO; + } + + return 0; +} + +static int rtl8366rb_setup(struct rtl8366_smi *smi) +{ + int err; + + /* set maximum packet length to 1536 bytes */ + REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK, + RTL8366RB_SGCR_MAX_LENGTH_1536); + + /* enable learning for all ports */ + REG_WR(smi, RTL8366RB_SSCR0, 0); + + /* enable auto ageing for all ports */ + REG_WR(smi, RTL8366RB_SSCR1, 0); + + /* + * discard VLAN tagged packets if the port is not a member of + * the VLAN with which the packets is associated. + */ + REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL); + + /* don't drop packets whose DA has not been learned */ + REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0); + + return 0; +} + +static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi, + u32 phy_no, u32 page, u32 addr, u32 *data) +{ + u32 reg; + int ret; + + if (phy_no > RTL8366RB_PHY_NO_MAX) + return -EINVAL; + + if (page > RTL8366RB_PHY_PAGE_MAX) + return -EINVAL; + + if (addr > RTL8366RB_PHY_ADDR_MAX) + return -EINVAL; + + ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG, + RTL8366RB_PHY_CTRL_READ); + if (ret) + return ret; + + reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) | + ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) | + (addr & RTL8366RB_PHY_REG_MASK); + + ret = rtl8366_smi_write_reg(smi, reg, 0); + if (ret) + return ret; + + ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data); + if (ret) + return ret; + + return 0; +} + +static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi, + u32 phy_no, u32 page, u32 addr, u32 data) +{ + u32 reg; + int ret; + + if (phy_no > RTL8366RB_PHY_NO_MAX) + return -EINVAL; + + if (page > RTL8366RB_PHY_PAGE_MAX) + return -EINVAL; + + if (addr > RTL8366RB_PHY_ADDR_MAX) + return -EINVAL; + + ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG, + RTL8366RB_PHY_CTRL_WRITE); + if (ret) + return ret; + + reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) | + ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) | + (addr & RTL8366RB_PHY_REG_MASK); + + ret = rtl8366_smi_write_reg(smi, reg, data); + if (ret) + return ret; + + return 0; +} + +static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter, + int port, unsigned long long *val) +{ + int i; + int err; + u32 addr, data; + u64 mibvalue; + + if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT) + return -EINVAL; + + addr = RTL8366RB_MIB_COUNTER_BASE + + RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) + + rtl8366rb_mib_counters[counter].offset; + + /* + * Writing access counter address first + * then ASIC will prepare 64bits counter wait for being retrived + */ + data = 0; /* writing data will be discard by ASIC */ + err = rtl8366_smi_write_reg(smi, addr, data); + if (err) + return err; + + /* read MIB control register */ + err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data); + if (err) + return err; + + if (data & RTL8366RB_MIB_CTRL_BUSY_MASK) + return -EBUSY; + + if (data & RTL8366RB_MIB_CTRL_RESET_MASK) + return -EIO; + + mibvalue = 0; + for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) { + err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data); + if (err) + return err; + + mibvalue = (mibvalue << 16) | (data & 0xFFFF); + } + + *val = mibvalue; + return 0; +} + +static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, + struct rtl8366_vlan_4k *vlan4k) +{ + u32 data[3]; + int err; + int i; + + memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); + + if (vid >= RTL8366RB_NUM_VIDS) + return -EINVAL; + + /* write VID */ + err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, + vid & RTL8366RB_VLAN_VID_MASK); + if (err) + return err; + + /* write table access control word */ + err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG, + RTL8366RB_TABLE_VLAN_READ_CTRL); + if (err) + return err; + + for (i = 0; i < 3; i++) { + err = rtl8366_smi_read_reg(smi, + RTL8366RB_VLAN_TABLE_READ_BASE + i, + &data[i]); + if (err) + return err; + } + + vlan4k->vid = vid; + vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & + RTL8366RB_VLAN_UNTAG_MASK; + vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; + vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK; + + return 0; +} + +static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi, + const struct rtl8366_vlan_4k *vlan4k) +{ + u32 data[3]; + int err; + int i; + + if (vlan4k->vid >= RTL8366RB_NUM_VIDS || + vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK || + vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK || + vlan4k->fid > RTL8366RB_FIDMAX) + return -EINVAL; + + data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK; + data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) | + ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) << + RTL8366RB_VLAN_UNTAG_SHIFT); + data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK; + + for (i = 0; i < 3; i++) { + err = rtl8366_smi_write_reg(smi, + RTL8366RB_VLAN_TABLE_WRITE_BASE + i, + data[i]); + if (err) + return err; + } + + /* write table access control word */ + err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG, + RTL8366RB_TABLE_VLAN_WRITE_CTRL); + + return err; +} + +static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index, + struct rtl8366_vlan_mc *vlanmc) +{ + u32 data[3]; + int err; + int i; + + memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); + + if (index >= RTL8366RB_NUM_VLANS) + return -EINVAL; + + for (i = 0; i < 3; i++) { + err = rtl8366_smi_read_reg(smi, + RTL8366RB_VLAN_MC_BASE(index) + i, + &data[i]); + if (err) + return err; + } + + vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK; + vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) & + RTL8366RB_VLAN_PRIORITY_MASK; + vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & + RTL8366RB_VLAN_UNTAG_MASK; + vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; + vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK; + + return 0; +} + +static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index, + const struct rtl8366_vlan_mc *vlanmc) +{ + u32 data[3]; + int err; + int i; + + if (index >= RTL8366RB_NUM_VLANS || + vlanmc->vid >= RTL8366RB_NUM_VIDS || + vlanmc->priority > RTL8366RB_PRIORITYMAX || + vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK || + vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK || + vlanmc->fid > RTL8366RB_FIDMAX) + return -EINVAL; + + data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) | + ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) << + RTL8366RB_VLAN_PRIORITY_SHIFT); + data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) | + ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) << + RTL8366RB_VLAN_UNTAG_SHIFT); + data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK; + + for (i = 0; i < 3; i++) { + err = rtl8366_smi_write_reg(smi, + RTL8366RB_VLAN_MC_BASE(index) + i, + data[i]); + if (err) + return err; + } + + return 0; +} + +static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val) +{ + u32 data; + int err; + + if (port >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port), + &data); + if (err) + return err; + + *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) & + RTL8366RB_PORT_VLAN_CTRL_MASK; + + return 0; + +} + +static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index) +{ + if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port), + RTL8366RB_PORT_VLAN_CTRL_MASK << + RTL8366RB_PORT_VLAN_CTRL_SHIFT(port), + (index & RTL8366RB_PORT_VLAN_CTRL_MASK) << + RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)); +} + +static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan) +{ + unsigned max = RTL8366RB_NUM_VLANS; + + if (smi->vlan4k_enabled) + max = RTL8366RB_NUM_VIDS - 1; + + if (vlan == 0 || vlan >= max) + return 0; + + return 1; +} + +static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN, + (enable) ? RTL8366RB_SGCR_EN_VLAN : 0); +} + +static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, + RTL8366RB_SGCR_EN_VLAN_4KTB, + (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0); +} + +static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port), + (enable) ? 0 : (1 << port)); +} + +static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0, + RTL8366RB_MIB_CTRL_GLOBAL_RESET); +} + +static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data); + + val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK)); + + return 0; +} + +static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (val->value.i >= 6) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, + RTL8366RB_LED_BLINKRATE_MASK, + val->value.i); +} + +static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data); + val->value.i = !data; + + return 0; +} + + +static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 portmask = 0; + int err = 0; + + if (!val->value.i) + portmask = RTL8366RB_PORT_ALL; + + /* set learning for all ports */ + REG_WR(smi, RTL8366RB_SSCR0, portmask); + + /* set auto ageing for all ports */ + REG_WR(smi, RTL8366RB_SSCR1, portmask); + + return 0; +} + +static int rtl8366rb_sw_get_port_link(struct switch_dev *dev, + int port, + struct switch_port_link *link) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data = 0; + u32 speed; + + if (port >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2), + &data); + + if (port % 2) + data = data >> 8; + + link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK); + if (!link->link) + return 0; + + link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK); + link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK); + link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK); + link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK); + + speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK); + switch (speed) { + case 0: + link->speed = SWITCH_PORT_SPEED_10; + break; + case 1: + link->speed = SWITCH_PORT_SPEED_100; + break; + case 2: + link->speed = SWITCH_PORT_SPEED_1000; + break; + default: + link->speed = SWITCH_PORT_SPEED_UNKNOWN; + break; + } + + return 0; +} + +static int rtl8366rb_sw_set_port_led(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + u32 mask; + u32 reg; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) { + reg = RTL8366RB_LED_BLINKRATE_REG; + mask = 0xF << 4; + data = val->value.i << 4; + } else { + reg = RTL8366RB_LED_CTRL_REG; + mask = 0xF << (val->port_vlan * 4), + data = val->value.i << (val->port_vlan * 4); + } + + return rtl8366_smi_rmwr(smi, reg, mask, data); +} + +static int rtl8366rb_sw_get_port_led(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data = 0; + + if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data); + val->value.i = (data >> (val->port_vlan * 4)) & 0x000F; + + return 0; +} + +static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 mask, data; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + mask = 1 << val->port_vlan ; + if (val->value.i) + data = mask; + else + data = 0; + + return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data); +} + +static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data); + if (data & (1 << val->port_vlan)) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + +static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX) + val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT; + else + val->value.i = RTL8366RB_BDTH_REG_DEFAULT; + + return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan), + RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK, + val->value.i | + (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET)); + +} + +static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data); + data &= RTL8366RB_IB_BDTH_MASK; + if (data < RTL8366RB_IB_BDTH_MASK) + data += 1; + + val->value.i = (int)data * RTL8366RB_BDTH_UNIT; + + return 0; +} + +static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG, + RTL8366RB_EB_PREIFG_MASK, + (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET)); + + if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX) + val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT; + else + val->value.i = RTL8366RB_BDTH_REG_DEFAULT; + + return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan), + RTL8366RB_EB_BDTH_MASK, val->value.i ); + +} + +static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data); + data &= RTL8366RB_EB_BDTH_MASK; + if (data < RTL8366RB_EB_BDTH_MASK) + data += 1; + + val->value.i = (int)data * RTL8366RB_BDTH_UNIT; + + return 0; +} + +static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->value.i) + data = RTL8366RB_QOS_MASK; + else + data = 0; + + return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data); +} + +static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data); + if (data & RTL8366RB_QOS_MASK) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + +static int rtl8366rb_sw_set_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->value.i) + data = RTL8366RB_PMCR_MIRROR_RX; + else + data = 0; + + return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_RX, data); +} + +static int rtl8366rb_sw_get_mirror_rx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data); + if (data & RTL8366RB_PMCR_MIRROR_RX) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + +static int rtl8366rb_sw_set_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->value.i) + data = RTL8366RB_PMCR_MIRROR_TX; + else + data = 0; + + return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_TX, data); +} + +static int rtl8366rb_sw_get_mirror_tx_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data); + if (data & RTL8366RB_PMCR_MIRROR_TX) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + +static int rtl8366rb_sw_set_monitor_isolation_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->value.i) + data = RTL8366RB_PMCR_MIRROR_ISO; + else + data = 0; + + return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_ISO, data); +} + +static int rtl8366rb_sw_get_monitor_isolation_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data); + if (data & RTL8366RB_PMCR_MIRROR_ISO) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + +static int rtl8366rb_sw_set_mirror_pause_frames_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + if (val->value.i) + data = RTL8366RB_PMCR_MIRROR_SPC; + else + data = 0; + + return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_SPC, data); +} + +static int rtl8366rb_sw_get_mirror_pause_frames_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data); + if (data & RTL8366RB_PMCR_MIRROR_SPC) + val->value.i = 1; + else + val->value.i = 0; + + return 0; +} + +static int rtl8366rb_sw_set_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + data = RTL8366RB_PMCR_MONITOR_PORT(val->value.i); + + return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MONITOR_PORT_MASK, data); +} + +static int rtl8366rb_sw_get_mirror_monitor_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data); + val->value.i = (data & RTL8366RB_PMCR_MONITOR_PORT_MASK) >> 4; + + return 0; +} + +static int rtl8366rb_sw_set_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + data = RTL8366RB_PMCR_SOURCE_PORT(val->value.i); + + return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_SOURCE_PORT_MASK, data); +} + +static int rtl8366rb_sw_get_mirror_source_port(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data); + val->value.i = data & RTL8366RB_PMCR_SOURCE_PORT_MASK; + + return 0; +} + +static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (val->port_vlan >= RTL8366RB_NUM_PORTS) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0, + RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan)); +} + +static struct switch_attr rtl8366rb_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_learning", + .description = "Enable learning, enable aging", + .set = rtl8366rb_sw_set_learning_enable, + .get = rtl8366rb_sw_get_learning_enable, + .max = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = rtl8366_sw_set_vlan_enable, + .get = rtl8366_sw_get_vlan_enable, + .max = 1, + .ofs = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan4k", + .description = "Enable VLAN 4K mode", + .set = rtl8366_sw_set_vlan_enable, + .get = rtl8366_sw_get_vlan_enable, + .max = 1, + .ofs = 2 + }, { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mibs", + .description = "Reset all MIB counters", + .set = rtl8366rb_sw_reset_mibs, + }, { + .type = SWITCH_TYPE_INT, + .name = "blinkrate", + .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms," + " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)", + .set = rtl8366rb_sw_set_blinkrate, + .get = rtl8366rb_sw_get_blinkrate, + .max = 5 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_qos", + .description = "Enable QOS", + .set = rtl8366rb_sw_set_qos_enable, + .get = rtl8366rb_sw_get_qos_enable, + .max = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_rx", + .description = "Enable mirroring of RX packets", + .set = rtl8366rb_sw_set_mirror_rx_enable, + .get = rtl8366rb_sw_get_mirror_rx_enable, + .max = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_tx", + .description = "Enable mirroring of TX packets", + .set = rtl8366rb_sw_set_mirror_tx_enable, + .get = rtl8366rb_sw_get_mirror_tx_enable, + .max = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_monitor_isolation", + .description = "Enable isolation of monitor port (TX packets will be dropped)", + .set = rtl8366rb_sw_set_monitor_isolation_enable, + .get = rtl8366rb_sw_get_monitor_isolation_enable, + .max = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_mirror_pause_frames", + .description = "Enable mirroring of RX pause frames", + .set = rtl8366rb_sw_set_mirror_pause_frames_enable, + .get = rtl8366rb_sw_get_mirror_pause_frames_enable, + .max = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "mirror_monitor_port", + .description = "Mirror monitor port", + .set = rtl8366rb_sw_set_mirror_monitor_port, + .get = rtl8366rb_sw_get_mirror_monitor_port, + .max = 5 + }, { + .type = SWITCH_TYPE_INT, + .name = "mirror_source_port", + .description = "Mirror source port", + .set = rtl8366rb_sw_set_mirror_source_port, + .get = rtl8366rb_sw_get_mirror_source_port, + .max = 5 + }, +}; + +static struct switch_attr rtl8366rb_port[] = { + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mib", + .description = "Reset single port MIB counters", + .set = rtl8366rb_sw_reset_port_mibs, + }, { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get MIB counters for port", + .max = 33, + .set = NULL, + .get = rtl8366_sw_get_port_mib, + }, { + .type = SWITCH_TYPE_INT, + .name = "led", + .description = "Get/Set port group (0 - 3) led mode (0 - 15)", + .max = 15, + .set = rtl8366rb_sw_set_port_led, + .get = rtl8366rb_sw_get_port_led, + }, { + .type = SWITCH_TYPE_INT, + .name = "disable", + .description = "Get/Set port state (enabled or disabled)", + .max = 1, + .set = rtl8366rb_sw_set_port_disable, + .get = rtl8366rb_sw_get_port_disable, + }, { + .type = SWITCH_TYPE_INT, + .name = "rate_in", + .description = "Get/Set port ingress (incoming) bandwidth limit in kbps", + .max = RTL8366RB_BDTH_SW_MAX, + .set = rtl8366rb_sw_set_port_rate_in, + .get = rtl8366rb_sw_get_port_rate_in, + }, { + .type = SWITCH_TYPE_INT, + .name = "rate_out", + .description = "Get/Set port egress (outgoing) bandwidth limit in kbps", + .max = RTL8366RB_BDTH_SW_MAX, + .set = rtl8366rb_sw_set_port_rate_out, + .get = rtl8366rb_sw_get_port_rate_out, + }, +}; + +static struct switch_attr rtl8366rb_vlan[] = { + { + .type = SWITCH_TYPE_STRING, + .name = "info", + .description = "Get vlan information", + .max = 1, + .set = NULL, + .get = rtl8366_sw_get_vlan_info, + }, { + .type = SWITCH_TYPE_INT, + .name = "fid", + .description = "Get/Set vlan FID", + .max = RTL8366RB_FIDMAX, + .set = rtl8366_sw_set_vlan_fid, + .get = rtl8366_sw_get_vlan_fid, + }, +}; + +static const struct switch_dev_ops rtl8366_ops = { + .attr_global = { + .attr = rtl8366rb_globals, + .n_attr = ARRAY_SIZE(rtl8366rb_globals), + }, + .attr_port = { + .attr = rtl8366rb_port, + .n_attr = ARRAY_SIZE(rtl8366rb_port), + }, + .attr_vlan = { + .attr = rtl8366rb_vlan, + .n_attr = ARRAY_SIZE(rtl8366rb_vlan), + }, + + .get_vlan_ports = rtl8366_sw_get_vlan_ports, + .set_vlan_ports = rtl8366_sw_set_vlan_ports, + .get_port_pvid = rtl8366_sw_get_port_pvid, + .set_port_pvid = rtl8366_sw_set_port_pvid, + .reset_switch = rtl8366_sw_reset_switch, + .get_port_link = rtl8366rb_sw_get_port_link, +}; + +static int rtl8366rb_switch_init(struct rtl8366_smi *smi) +{ + struct switch_dev *dev = &smi->sw_dev; + int err; + + dev->name = "RTL8366RB"; + dev->cpu_port = RTL8366RB_PORT_NUM_CPU; + dev->ports = RTL8366RB_NUM_PORTS; + dev->vlans = RTL8366RB_NUM_VIDS; + dev->ops = &rtl8366_ops; + dev->alias = dev_name(smi->parent); + + err = register_switch(dev, NULL); + if (err) + dev_err(smi->parent, "switch registration failed\n"); + + return err; +} + +static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi) +{ + unregister_switch(&smi->sw_dev); +} + +static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg) +{ + struct rtl8366_smi *smi = bus->priv; + u32 val = 0; + int err; + + err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val); + if (err) + return 0xffff; + + return val; +} + +static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) +{ + struct rtl8366_smi *smi = bus->priv; + u32 t; + int err; + + err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val); + /* flush write */ + (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t); + + return err; +} + +static int rtl8366rb_detect(struct rtl8366_smi *smi) +{ + u32 chip_id = 0; + u32 chip_ver = 0; + int ret; + + ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id); + if (ret) { + dev_err(smi->parent, "unable to read chip id\n"); + return ret; + } + + switch (chip_id) { + case RTL8366RB_CHIP_ID_8366: + break; + default: + dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id); + return -ENODEV; + } + + ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG, + &chip_ver); + if (ret) { + dev_err(smi->parent, "unable to read chip version\n"); + return ret; + } + + dev_info(smi->parent, "RTL%04x ver. %u chip found\n", + chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK); + + return 0; +} + +static struct rtl8366_smi_ops rtl8366rb_smi_ops = { + .detect = rtl8366rb_detect, + .reset_chip = rtl8366rb_reset_chip, + .setup = rtl8366rb_setup, + + .mii_read = rtl8366rb_mii_read, + .mii_write = rtl8366rb_mii_write, + + .get_vlan_mc = rtl8366rb_get_vlan_mc, + .set_vlan_mc = rtl8366rb_set_vlan_mc, + .get_vlan_4k = rtl8366rb_get_vlan_4k, + .set_vlan_4k = rtl8366rb_set_vlan_4k, + .get_mc_index = rtl8366rb_get_mc_index, + .set_mc_index = rtl8366rb_set_mc_index, + .get_mib_counter = rtl8366rb_get_mib_counter, + .is_vlan_valid = rtl8366rb_is_vlan_valid, + .enable_vlan = rtl8366rb_enable_vlan, + .enable_vlan4k = rtl8366rb_enable_vlan4k, + .enable_port = rtl8366rb_enable_port, +}; + +static int rtl8366rb_probe(struct platform_device *pdev) +{ + static int rtl8366_smi_version_printed; + struct rtl8366_smi *smi; + int err; + + if (!rtl8366_smi_version_printed++) + printk(KERN_NOTICE RTL8366RB_DRIVER_DESC + " version " RTL8366RB_DRIVER_VER"\n"); + + smi = rtl8366_smi_probe(pdev); + if (!smi) + return -ENODEV; + + smi->clk_delay = 10; + smi->cmd_read = 0xa9; + smi->cmd_write = 0xa8; + smi->ops = &rtl8366rb_smi_ops; + smi->cpu_port = RTL8366RB_PORT_NUM_CPU; + smi->num_ports = RTL8366RB_NUM_PORTS; + smi->num_vlan_mc = RTL8366RB_NUM_VLANS; + smi->mib_counters = rtl8366rb_mib_counters; + smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters); + + err = rtl8366_smi_init(smi); + if (err) + goto err_free_smi; + + platform_set_drvdata(pdev, smi); + + err = rtl8366rb_switch_init(smi); + if (err) + goto err_clear_drvdata; + + return 0; + + err_clear_drvdata: + platform_set_drvdata(pdev, NULL); + rtl8366_smi_cleanup(smi); + err_free_smi: + kfree(smi); + return err; +} + +static int rtl8366rb_remove(struct platform_device *pdev) +{ + struct rtl8366_smi *smi = platform_get_drvdata(pdev); + + if (smi) { + rtl8366rb_switch_cleanup(smi); + platform_set_drvdata(pdev, NULL); + rtl8366_smi_cleanup(smi); + kfree(smi); + } + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id rtl8366rb_match[] = { + { .compatible = "rtl8366rb" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rtl8366rb_match); +#endif + +static struct platform_driver rtl8366rb_driver = { + .driver = { + .name = RTL8366RB_DRIVER_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(rtl8366rb_match), + }, + .probe = rtl8366rb_probe, + .remove = rtl8366rb_remove, +}; + +static int __init rtl8366rb_module_init(void) +{ + return platform_driver_register(&rtl8366rb_driver); +} +module_init(rtl8366rb_module_init); + +static void __exit rtl8366rb_module_exit(void) +{ + platform_driver_unregister(&rtl8366rb_driver); +} +module_exit(rtl8366rb_module_exit); + +MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC); +MODULE_VERSION(RTL8366RB_DRIVER_VER); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_AUTHOR("Antti Seppälä "); +MODULE_AUTHOR("Roman Yeryomin "); +MODULE_AUTHOR("Colin Leitner "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME); diff --git a/target/linux/generic/files/drivers/net/phy/rtl8366s.c b/target/linux/generic/files/drivers/net/phy/rtl8366s.c new file mode 100644 index 0000000..3dc2a87 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/rtl8366s.c @@ -0,0 +1,1148 @@ +/* + * Platform driver for the Realtek RTL8366S ethernet switch + * + * Copyright (C) 2009-2010 Gabor Juhos + * Copyright (C) 2010 Antti Seppälä + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtl8366_smi.h" + +#define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver" +#define RTL8366S_DRIVER_VER "0.2.2" + +#define RTL8366S_PHY_NO_MAX 4 +#define RTL8366S_PHY_PAGE_MAX 7 +#define RTL8366S_PHY_ADDR_MAX 31 + +/* Switch Global Configuration register */ +#define RTL8366S_SGCR 0x0000 +#define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0) +#define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4) +#define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3) +#define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0) +#define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1) +#define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2) +#define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3) +#define RTL8366S_SGCR_EN_VLAN BIT(13) + +/* Port Enable Control register */ +#define RTL8366S_PECR 0x0001 + +/* Switch Security Control registers */ +#define RTL8366S_SSCR0 0x0002 +#define RTL8366S_SSCR1 0x0003 +#define RTL8366S_SSCR2 0x0004 +#define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0) + +#define RTL8366S_RESET_CTRL_REG 0x0100 +#define RTL8366S_CHIP_CTRL_RESET_HW 1 +#define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1) + +#define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104 +#define RTL8366S_CHIP_VERSION_MASK 0xf +#define RTL8366S_CHIP_ID_REG 0x0105 +#define RTL8366S_CHIP_ID_8366 0x8366 + +/* PHY registers control */ +#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028 +#define RTL8366S_PHY_ACCESS_DATA_REG 0x8029 + +#define RTL8366S_PHY_CTRL_READ 1 +#define RTL8366S_PHY_CTRL_WRITE 0 + +#define RTL8366S_PHY_REG_MASK 0x1f +#define RTL8366S_PHY_PAGE_OFFSET 5 +#define RTL8366S_PHY_PAGE_MASK (0x7 << 5) +#define RTL8366S_PHY_NO_OFFSET 9 +#define RTL8366S_PHY_NO_MASK (0x1f << 9) + +/* LED control registers */ +#define RTL8366S_LED_BLINKRATE_REG 0x0420 +#define RTL8366S_LED_BLINKRATE_BIT 0 +#define RTL8366S_LED_BLINKRATE_MASK 0x0007 + +#define RTL8366S_LED_CTRL_REG 0x0421 +#define RTL8366S_LED_0_1_CTRL_REG 0x0422 +#define RTL8366S_LED_2_3_CTRL_REG 0x0423 + +#define RTL8366S_MIB_COUNT 33 +#define RTL8366S_GLOBAL_MIB_COUNT 1 +#define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040 +#define RTL8366S_MIB_COUNTER_BASE 0x1000 +#define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008 +#define RTL8366S_MIB_COUNTER_BASE2 0x1180 +#define RTL8366S_MIB_CTRL_REG 0x11F0 +#define RTL8366S_MIB_CTRL_USER_MASK 0x01FF +#define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001 +#define RTL8366S_MIB_CTRL_RESET_MASK 0x0002 + +#define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004 +#define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003 +#define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC + + +#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058 +#define RTL8366S_PORT_VLAN_CTRL_REG(_p) \ + (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4) +#define RTL8366S_PORT_VLAN_CTRL_MASK 0xf +#define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) + + +#define RTL8366S_VLAN_TABLE_READ_BASE 0x018B +#define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185 + +#define RTL8366S_VLAN_TB_CTRL_REG 0x010F + +#define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180 +#define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01 +#define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01 + +#define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2) + +#define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379 + +#define RTL8366S_PORT_LINK_STATUS_BASE 0x0060 +#define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003 +#define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004 +#define RTL8366S_PORT_STATUS_LINK_MASK 0x0010 +#define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020 +#define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040 +#define RTL8366S_PORT_STATUS_AN_MASK 0x0080 + + +#define RTL8366S_PORT_NUM_CPU 5 +#define RTL8366S_NUM_PORTS 6 +#define RTL8366S_NUM_VLANS 16 +#define RTL8366S_NUM_LEDGROUPS 4 +#define RTL8366S_NUM_VIDS 4096 +#define RTL8366S_PRIORITYMAX 7 +#define RTL8366S_FIDMAX 7 + + +#define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */ +#define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */ +#define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */ +#define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */ + +#define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */ +#define RTL8366S_PORT_CPU (1 << 5) /* CPU port */ + +#define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \ + RTL8366S_PORT_2 | \ + RTL8366S_PORT_3 | \ + RTL8366S_PORT_4 | \ + RTL8366S_PORT_UNKNOWN | \ + RTL8366S_PORT_CPU) + +#define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \ + RTL8366S_PORT_2 | \ + RTL8366S_PORT_3 | \ + RTL8366S_PORT_4 | \ + RTL8366S_PORT_UNKNOWN) + +#define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \ + RTL8366S_PORT_2 | \ + RTL8366S_PORT_3 | \ + RTL8366S_PORT_4) + +#define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \ + RTL8366S_PORT_CPU) + +#define RTL8366S_VLAN_VID_MASK 0xfff +#define RTL8366S_VLAN_PRIORITY_SHIFT 12 +#define RTL8366S_VLAN_PRIORITY_MASK 0x7 +#define RTL8366S_VLAN_MEMBER_MASK 0x3f +#define RTL8366S_VLAN_UNTAG_SHIFT 6 +#define RTL8366S_VLAN_UNTAG_MASK 0x3f +#define RTL8366S_VLAN_FID_SHIFT 12 +#define RTL8366S_VLAN_FID_MASK 0x7 + +static struct rtl8366_mib_counter rtl8366s_mib_counters[] = { + { 0, 0, 4, "IfInOctets" }, + { 0, 4, 4, "EtherStatsOctets" }, + { 0, 8, 2, "EtherStatsUnderSizePkts" }, + { 0, 10, 2, "EtherFragments" }, + { 0, 12, 2, "EtherStatsPkts64Octets" }, + { 0, 14, 2, "EtherStatsPkts65to127Octets" }, + { 0, 16, 2, "EtherStatsPkts128to255Octets" }, + { 0, 18, 2, "EtherStatsPkts256to511Octets" }, + { 0, 20, 2, "EtherStatsPkts512to1023Octets" }, + { 0, 22, 2, "EtherStatsPkts1024to1518Octets" }, + { 0, 24, 2, "EtherOversizeStats" }, + { 0, 26, 2, "EtherStatsJabbers" }, + { 0, 28, 2, "IfInUcastPkts" }, + { 0, 30, 2, "EtherStatsMulticastPkts" }, + { 0, 32, 2, "EtherStatsBroadcastPkts" }, + { 0, 34, 2, "EtherStatsDropEvents" }, + { 0, 36, 2, "Dot3StatsFCSErrors" }, + { 0, 38, 2, "Dot3StatsSymbolErrors" }, + { 0, 40, 2, "Dot3InPauseFrames" }, + { 0, 42, 2, "Dot3ControlInUnknownOpcodes" }, + { 0, 44, 4, "IfOutOctets" }, + { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, + { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, + { 0, 52, 2, "Dot3sDeferredTransmissions" }, + { 0, 54, 2, "Dot3StatsLateCollisions" }, + { 0, 56, 2, "EtherStatsCollisions" }, + { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, + { 0, 60, 2, "Dot3OutPauseFrames" }, + { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, + + /* + * The following counters are accessible at a different + * base address. + */ + { 1, 0, 2, "Dot1dTpPortInDiscards" }, + { 1, 2, 2, "IfOutUcastPkts" }, + { 1, 4, 2, "IfOutMulticastPkts" }, + { 1, 6, 2, "IfOutBroadcastPkts" }, +}; + +#define REG_WR(_smi, _reg, _val) \ + do { \ + err = rtl8366_smi_write_reg(_smi, _reg, _val); \ + if (err) \ + return err; \ + } while (0) + +#define REG_RMW(_smi, _reg, _mask, _val) \ + do { \ + err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \ + if (err) \ + return err; \ + } while (0) + +static int rtl8366s_reset_chip(struct rtl8366_smi *smi) +{ + int timeout = 10; + u32 data; + + rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG, + RTL8366S_CHIP_CTRL_RESET_HW); + do { + msleep(1); + if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data)) + return -EIO; + + if (!(data & RTL8366S_CHIP_CTRL_RESET_HW)) + break; + } while (--timeout); + + if (!timeout) { + printk("Timeout waiting for the switch to reset\n"); + return -EIO; + } + + return 0; +} + +static int rtl8366s_setup(struct rtl8366_smi *smi) +{ + struct rtl8366_platform_data *pdata; + int err; + + pdata = smi->parent->platform_data; + if (pdata && pdata->num_initvals && pdata->initvals) { + unsigned i; + + dev_info(smi->parent, "applying initvals\n"); + for (i = 0; i < pdata->num_initvals; i++) + REG_WR(smi, pdata->initvals[i].reg, + pdata->initvals[i].val); + } + + /* set maximum packet length to 1536 bytes */ + REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK, + RTL8366S_SGCR_MAX_LENGTH_1536); + + /* enable learning for all ports */ + REG_WR(smi, RTL8366S_SSCR0, 0); + + /* enable auto ageing for all ports */ + REG_WR(smi, RTL8366S_SSCR1, 0); + + /* + * discard VLAN tagged packets if the port is not a member of + * the VLAN with which the packets is associated. + */ + REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL); + + /* don't drop packets whose DA has not been learned */ + REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0); + + return 0; +} + +static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi, + u32 phy_no, u32 page, u32 addr, u32 *data) +{ + u32 reg; + int ret; + + if (phy_no > RTL8366S_PHY_NO_MAX) + return -EINVAL; + + if (page > RTL8366S_PHY_PAGE_MAX) + return -EINVAL; + + if (addr > RTL8366S_PHY_ADDR_MAX) + return -EINVAL; + + ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, + RTL8366S_PHY_CTRL_READ); + if (ret) + return ret; + + reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | + ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | + (addr & RTL8366S_PHY_REG_MASK); + + ret = rtl8366_smi_write_reg(smi, reg, 0); + if (ret) + return ret; + + ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data); + if (ret) + return ret; + + return 0; +} + +static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi, + u32 phy_no, u32 page, u32 addr, u32 data) +{ + u32 reg; + int ret; + + if (phy_no > RTL8366S_PHY_NO_MAX) + return -EINVAL; + + if (page > RTL8366S_PHY_PAGE_MAX) + return -EINVAL; + + if (addr > RTL8366S_PHY_ADDR_MAX) + return -EINVAL; + + ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, + RTL8366S_PHY_CTRL_WRITE); + if (ret) + return ret; + + reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | + ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | + (addr & RTL8366S_PHY_REG_MASK); + + ret = rtl8366_smi_write_reg(smi, reg, data); + if (ret) + return ret; + + return 0; +} + +static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter, + int port, unsigned long long *val) +{ + int i; + int err; + u32 addr, data; + u64 mibvalue; + + if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT) + return -EINVAL; + + switch (rtl8366s_mib_counters[counter].base) { + case 0: + addr = RTL8366S_MIB_COUNTER_BASE + + RTL8366S_MIB_COUNTER_PORT_OFFSET * port; + break; + + case 1: + addr = RTL8366S_MIB_COUNTER_BASE2 + + RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port; + break; + + default: + return -EINVAL; + } + + addr += rtl8366s_mib_counters[counter].offset; + + /* + * Writing access counter address first + * then ASIC will prepare 64bits counter wait for being retrived + */ + data = 0; /* writing data will be discard by ASIC */ + err = rtl8366_smi_write_reg(smi, addr, data); + if (err) + return err; + + /* read MIB control register */ + err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data); + if (err) + return err; + + if (data & RTL8366S_MIB_CTRL_BUSY_MASK) + return -EBUSY; + + if (data & RTL8366S_MIB_CTRL_RESET_MASK) + return -EIO; + + mibvalue = 0; + for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) { + err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data); + if (err) + return err; + + mibvalue = (mibvalue << 16) | (data & 0xFFFF); + } + + *val = mibvalue; + return 0; +} + +static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, + struct rtl8366_vlan_4k *vlan4k) +{ + u32 data[2]; + int err; + int i; + + memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); + + if (vid >= RTL8366S_NUM_VIDS) + return -EINVAL; + + /* write VID */ + err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, + vid & RTL8366S_VLAN_VID_MASK); + if (err) + return err; + + /* write table access control word */ + err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, + RTL8366S_TABLE_VLAN_READ_CTRL); + if (err) + return err; + + for (i = 0; i < 2; i++) { + err = rtl8366_smi_read_reg(smi, + RTL8366S_VLAN_TABLE_READ_BASE + i, + &data[i]); + if (err) + return err; + } + + vlan4k->vid = vid; + vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) & + RTL8366S_VLAN_UNTAG_MASK; + vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK; + vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) & + RTL8366S_VLAN_FID_MASK; + + return 0; +} + +static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi, + const struct rtl8366_vlan_4k *vlan4k) +{ + u32 data[2]; + int err; + int i; + + if (vlan4k->vid >= RTL8366S_NUM_VIDS || + vlan4k->member > RTL8366S_VLAN_MEMBER_MASK || + vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK || + vlan4k->fid > RTL8366S_FIDMAX) + return -EINVAL; + + data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK; + data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) | + ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) << + RTL8366S_VLAN_UNTAG_SHIFT) | + ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) << + RTL8366S_VLAN_FID_SHIFT); + + for (i = 0; i < 2; i++) { + err = rtl8366_smi_write_reg(smi, + RTL8366S_VLAN_TABLE_WRITE_BASE + i, + data[i]); + if (err) + return err; + } + + /* write table access control word */ + err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, + RTL8366S_TABLE_VLAN_WRITE_CTRL); + + return err; +} + +static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index, + struct rtl8366_vlan_mc *vlanmc) +{ + u32 data[2]; + int err; + int i; + + memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); + + if (index >= RTL8366S_NUM_VLANS) + return -EINVAL; + + for (i = 0; i < 2; i++) { + err = rtl8366_smi_read_reg(smi, + RTL8366S_VLAN_MC_BASE(index) + i, + &data[i]); + if (err) + return err; + } + + vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK; + vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) & + RTL8366S_VLAN_PRIORITY_MASK; + vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) & + RTL8366S_VLAN_UNTAG_MASK; + vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK; + vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) & + RTL8366S_VLAN_FID_MASK; + + return 0; +} + +static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index, + const struct rtl8366_vlan_mc *vlanmc) +{ + u32 data[2]; + int err; + int i; + + if (index >= RTL8366S_NUM_VLANS || + vlanmc->vid >= RTL8366S_NUM_VIDS || + vlanmc->priority > RTL8366S_PRIORITYMAX || + vlanmc->member > RTL8366S_VLAN_MEMBER_MASK || + vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK || + vlanmc->fid > RTL8366S_FIDMAX) + return -EINVAL; + + data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) | + ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) << + RTL8366S_VLAN_PRIORITY_SHIFT); + data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) | + ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) << + RTL8366S_VLAN_UNTAG_SHIFT) | + ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) << + RTL8366S_VLAN_FID_SHIFT); + + for (i = 0; i < 2; i++) { + err = rtl8366_smi_write_reg(smi, + RTL8366S_VLAN_MC_BASE(index) + i, + data[i]); + if (err) + return err; + } + + return 0; +} + +static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val) +{ + u32 data; + int err; + + if (port >= RTL8366S_NUM_PORTS) + return -EINVAL; + + err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), + &data); + if (err) + return err; + + *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) & + RTL8366S_PORT_VLAN_CTRL_MASK; + + return 0; +} + +static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index) +{ + if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), + RTL8366S_PORT_VLAN_CTRL_MASK << + RTL8366S_PORT_VLAN_CTRL_SHIFT(port), + (index & RTL8366S_PORT_VLAN_CTRL_MASK) << + RTL8366S_PORT_VLAN_CTRL_SHIFT(port)); +} + +static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN, + (enable) ? RTL8366S_SGCR_EN_VLAN : 0); +} + +static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG, + 1, (enable) ? 1 : 0); +} + +static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan) +{ + unsigned max = RTL8366S_NUM_VLANS; + + if (smi->vlan4k_enabled) + max = RTL8366S_NUM_VIDS - 1; + + if (vlan == 0 || vlan >= max) + return 0; + + return 1; +} + +static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port), + (enable) ? 0 : (1 << port)); +} + +static int rtl8366s_sw_reset_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2)); +} + +static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data); + + val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK)); + + return 0; +} + +static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (val->value.i >= 6) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, + RTL8366S_LED_BLINKRATE_MASK, + val->value.i); +} + +static int rtl8366s_sw_get_max_length(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data); + + val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4); + + return 0; +} + +static int rtl8366s_sw_set_max_length(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + char length_code; + + switch (val->value.i) { + case 0: + length_code = RTL8366S_SGCR_MAX_LENGTH_1522; + break; + case 1: + length_code = RTL8366S_SGCR_MAX_LENGTH_1536; + break; + case 2: + length_code = RTL8366S_SGCR_MAX_LENGTH_1552; + break; + case 3: + length_code = RTL8366S_SGCR_MAX_LENGTH_16000; + break; + default: + return -EINVAL; + } + + return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, + RTL8366S_SGCR_MAX_LENGTH_MASK, + length_code); +} + +static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data); + val->value.i = !data; + + return 0; +} + + +static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 portmask = 0; + int err = 0; + + if (!val->value.i) + portmask = RTL8366S_PORT_ALL; + + /* set learning for all ports */ + REG_WR(smi, RTL8366S_SSCR0, portmask); + + /* set auto ageing for all ports */ + REG_WR(smi, RTL8366S_SSCR1, portmask); + + return 0; +} + +static int rtl8366s_sw_get_port_link(struct switch_dev *dev, + int port, + struct switch_port_link *link) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data = 0; + u32 speed; + + if (port >= RTL8366S_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2), + &data); + + if (port % 2) + data = data >> 8; + + link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK); + if (!link->link) + return 0; + + link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK); + link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK); + link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK); + link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK); + + speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK); + switch (speed) { + case 0: + link->speed = SWITCH_PORT_SPEED_10; + break; + case 1: + link->speed = SWITCH_PORT_SPEED_100; + break; + case 2: + link->speed = SWITCH_PORT_SPEED_1000; + break; + default: + link->speed = SWITCH_PORT_SPEED_UNKNOWN; + break; + } + + return 0; +} + +static int rtl8366s_sw_set_port_led(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + u32 mask; + u32 reg; + + if (val->port_vlan >= RTL8366S_NUM_PORTS || + (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN) + return -EINVAL; + + if (val->port_vlan == RTL8366S_PORT_NUM_CPU) { + reg = RTL8366S_LED_BLINKRATE_REG; + mask = 0xF << 4; + data = val->value.i << 4; + } else { + reg = RTL8366S_LED_CTRL_REG; + mask = 0xF << (val->port_vlan * 4), + data = val->value.i << (val->port_vlan * 4); + } + + return rtl8366_smi_rmwr(smi, reg, mask, data); +} + +static int rtl8366s_sw_get_port_led(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data = 0; + + if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data); + val->value.i = (data >> (val->port_vlan * 4)) & 0x000F; + + return 0; +} + +static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + if (val->port_vlan >= RTL8366S_NUM_PORTS) + return -EINVAL; + + + return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, + 0, (1 << (val->port_vlan + 3))); +} + +static struct switch_attr rtl8366s_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_learning", + .description = "Enable learning, enable aging", + .set = rtl8366s_sw_set_learning_enable, + .get = rtl8366s_sw_get_learning_enable, + .max = 1, + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = rtl8366_sw_set_vlan_enable, + .get = rtl8366_sw_get_vlan_enable, + .max = 1, + .ofs = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan4k", + .description = "Enable VLAN 4K mode", + .set = rtl8366_sw_set_vlan_enable, + .get = rtl8366_sw_get_vlan_enable, + .max = 1, + .ofs = 2 + }, { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mibs", + .description = "Reset all MIB counters", + .set = rtl8366s_sw_reset_mibs, + }, { + .type = SWITCH_TYPE_INT, + .name = "blinkrate", + .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms," + " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)", + .set = rtl8366s_sw_set_blinkrate, + .get = rtl8366s_sw_get_blinkrate, + .max = 5 + }, { + .type = SWITCH_TYPE_INT, + .name = "max_length", + .description = "Get/Set the maximum length of valid packets" + " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))", + .set = rtl8366s_sw_set_max_length, + .get = rtl8366s_sw_get_max_length, + .max = 3, + }, +}; + +static struct switch_attr rtl8366s_port[] = { + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mib", + .description = "Reset single port MIB counters", + .set = rtl8366s_sw_reset_port_mibs, + }, { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get MIB counters for port", + .max = 33, + .set = NULL, + .get = rtl8366_sw_get_port_mib, + }, { + .type = SWITCH_TYPE_INT, + .name = "led", + .description = "Get/Set port group (0 - 3) led mode (0 - 15)", + .max = 15, + .set = rtl8366s_sw_set_port_led, + .get = rtl8366s_sw_get_port_led, + }, +}; + +static struct switch_attr rtl8366s_vlan[] = { + { + .type = SWITCH_TYPE_STRING, + .name = "info", + .description = "Get vlan information", + .max = 1, + .set = NULL, + .get = rtl8366_sw_get_vlan_info, + }, { + .type = SWITCH_TYPE_INT, + .name = "fid", + .description = "Get/Set vlan FID", + .max = RTL8366S_FIDMAX, + .set = rtl8366_sw_set_vlan_fid, + .get = rtl8366_sw_get_vlan_fid, + }, +}; + +static const struct switch_dev_ops rtl8366_ops = { + .attr_global = { + .attr = rtl8366s_globals, + .n_attr = ARRAY_SIZE(rtl8366s_globals), + }, + .attr_port = { + .attr = rtl8366s_port, + .n_attr = ARRAY_SIZE(rtl8366s_port), + }, + .attr_vlan = { + .attr = rtl8366s_vlan, + .n_attr = ARRAY_SIZE(rtl8366s_vlan), + }, + + .get_vlan_ports = rtl8366_sw_get_vlan_ports, + .set_vlan_ports = rtl8366_sw_set_vlan_ports, + .get_port_pvid = rtl8366_sw_get_port_pvid, + .set_port_pvid = rtl8366_sw_set_port_pvid, + .reset_switch = rtl8366_sw_reset_switch, + .get_port_link = rtl8366s_sw_get_port_link, +}; + +static int rtl8366s_switch_init(struct rtl8366_smi *smi) +{ + struct switch_dev *dev = &smi->sw_dev; + int err; + + dev->name = "RTL8366S"; + dev->cpu_port = RTL8366S_PORT_NUM_CPU; + dev->ports = RTL8366S_NUM_PORTS; + dev->vlans = RTL8366S_NUM_VIDS; + dev->ops = &rtl8366_ops; + dev->alias = dev_name(smi->parent); + + err = register_switch(dev, NULL); + if (err) + dev_err(smi->parent, "switch registration failed\n"); + + return err; +} + +static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi) +{ + unregister_switch(&smi->sw_dev); +} + +static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg) +{ + struct rtl8366_smi *smi = bus->priv; + u32 val = 0; + int err; + + err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val); + if (err) + return 0xffff; + + return val; +} + +static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) +{ + struct rtl8366_smi *smi = bus->priv; + u32 t; + int err; + + err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val); + /* flush write */ + (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t); + + return err; +} + +static int rtl8366s_detect(struct rtl8366_smi *smi) +{ + u32 chip_id = 0; + u32 chip_ver = 0; + int ret; + + ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id); + if (ret) { + dev_err(smi->parent, "unable to read chip id\n"); + return ret; + } + + switch (chip_id) { + case RTL8366S_CHIP_ID_8366: + break; + default: + dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id); + return -ENODEV; + } + + ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG, + &chip_ver); + if (ret) { + dev_err(smi->parent, "unable to read chip version\n"); + return ret; + } + + dev_info(smi->parent, "RTL%04x ver. %u chip found\n", + chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK); + + return 0; +} + +static struct rtl8366_smi_ops rtl8366s_smi_ops = { + .detect = rtl8366s_detect, + .reset_chip = rtl8366s_reset_chip, + .setup = rtl8366s_setup, + + .mii_read = rtl8366s_mii_read, + .mii_write = rtl8366s_mii_write, + + .get_vlan_mc = rtl8366s_get_vlan_mc, + .set_vlan_mc = rtl8366s_set_vlan_mc, + .get_vlan_4k = rtl8366s_get_vlan_4k, + .set_vlan_4k = rtl8366s_set_vlan_4k, + .get_mc_index = rtl8366s_get_mc_index, + .set_mc_index = rtl8366s_set_mc_index, + .get_mib_counter = rtl8366_get_mib_counter, + .is_vlan_valid = rtl8366s_is_vlan_valid, + .enable_vlan = rtl8366s_enable_vlan, + .enable_vlan4k = rtl8366s_enable_vlan4k, + .enable_port = rtl8366s_enable_port, +}; + +static int rtl8366s_probe(struct platform_device *pdev) +{ + static int rtl8366_smi_version_printed; + struct rtl8366_smi *smi; + int err; + + if (!rtl8366_smi_version_printed++) + printk(KERN_NOTICE RTL8366S_DRIVER_DESC + " version " RTL8366S_DRIVER_VER"\n"); + + smi = rtl8366_smi_probe(pdev); + if (!smi) + return -ENODEV; + + smi->clk_delay = 10; + smi->cmd_read = 0xa9; + smi->cmd_write = 0xa8; + smi->ops = &rtl8366s_smi_ops; + smi->cpu_port = RTL8366S_PORT_NUM_CPU; + smi->num_ports = RTL8366S_NUM_PORTS; + smi->num_vlan_mc = RTL8366S_NUM_VLANS; + smi->mib_counters = rtl8366s_mib_counters; + smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters); + + err = rtl8366_smi_init(smi); + if (err) + goto err_free_smi; + + platform_set_drvdata(pdev, smi); + + err = rtl8366s_switch_init(smi); + if (err) + goto err_clear_drvdata; + + return 0; + + err_clear_drvdata: + platform_set_drvdata(pdev, NULL); + rtl8366_smi_cleanup(smi); + err_free_smi: + kfree(smi); + return err; +} + +static int rtl8366s_remove(struct platform_device *pdev) +{ + struct rtl8366_smi *smi = platform_get_drvdata(pdev); + + if (smi) { + rtl8366s_switch_cleanup(smi); + platform_set_drvdata(pdev, NULL); + rtl8366_smi_cleanup(smi); + kfree(smi); + } + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id rtl8366s_match[] = { + { .compatible = "realtek,rtl8366s" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rtl8366s_match); +#endif + +static struct platform_driver rtl8366s_driver = { + .driver = { + .name = RTL8366S_DRIVER_NAME, + .owner = THIS_MODULE, +#ifdef CONFIG_OF + .of_match_table = of_match_ptr(rtl8366s_match), +#endif + }, + .probe = rtl8366s_probe, + .remove = rtl8366s_remove, +}; + +static int __init rtl8366s_module_init(void) +{ + return platform_driver_register(&rtl8366s_driver); +} +module_init(rtl8366s_module_init); + +static void __exit rtl8366s_module_exit(void) +{ + platform_driver_unregister(&rtl8366s_driver); +} +module_exit(rtl8366s_module_exit); + +MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC); +MODULE_VERSION(RTL8366S_DRIVER_VER); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_AUTHOR("Antti Seppälä "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME); diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367.c b/target/linux/generic/files/drivers/net/phy/rtl8367.c new file mode 100644 index 0000000..4978a8c --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/rtl8367.c @@ -0,0 +1,1835 @@ +/* + * Platform driver for the Realtek RTL8367R/M ethernet switches + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtl8366_smi.h" + +#define RTL8367_RESET_DELAY 1000 /* msecs*/ + +#define RTL8367_PHY_ADDR_MAX 8 +#define RTL8367_PHY_REG_MAX 31 + +#define RTL8367_VID_MASK 0xffff +#define RTL8367_FID_MASK 0xfff +#define RTL8367_UNTAG_MASK 0xffff +#define RTL8367_MEMBER_MASK 0xffff + +#define RTL8367_PORT_CFG_REG(_p) (0x000e + 0x20 * (_p)) +#define RTL8367_PORT_CFG_EGRESS_MODE_SHIFT 4 +#define RTL8367_PORT_CFG_EGRESS_MODE_MASK 0x3 +#define RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL 0 +#define RTL8367_PORT_CFG_EGRESS_MODE_KEEP 1 +#define RTL8367_PORT_CFG_EGRESS_MODE_PRI 2 +#define RTL8367_PORT_CFG_EGRESS_MODE_REAL 3 + +#define RTL8367_BYPASS_LINE_RATE_REG 0x03f7 + +#define RTL8367_TA_CTRL_REG 0x0500 +#define RTL8367_TA_CTRL_STATUS BIT(12) +#define RTL8367_TA_CTRL_METHOD BIT(5) +#define RTL8367_TA_CTRL_CMD_SHIFT 4 +#define RTL8367_TA_CTRL_CMD_READ 0 +#define RTL8367_TA_CTRL_CMD_WRITE 1 +#define RTL8367_TA_CTRL_TABLE_SHIFT 0 +#define RTL8367_TA_CTRL_TABLE_ACLRULE 1 +#define RTL8367_TA_CTRL_TABLE_ACLACT 2 +#define RTL8367_TA_CTRL_TABLE_CVLAN 3 +#define RTL8367_TA_CTRL_TABLE_L2 4 +#define RTL8367_TA_CTRL_CVLAN_READ \ + ((RTL8367_TA_CTRL_CMD_READ << RTL8367_TA_CTRL_CMD_SHIFT) | \ + RTL8367_TA_CTRL_TABLE_CVLAN) +#define RTL8367_TA_CTRL_CVLAN_WRITE \ + ((RTL8367_TA_CTRL_CMD_WRITE << RTL8367_TA_CTRL_CMD_SHIFT) | \ + RTL8367_TA_CTRL_TABLE_CVLAN) + +#define RTL8367_TA_ADDR_REG 0x0501 +#define RTL8367_TA_ADDR_MASK 0x3fff + +#define RTL8367_TA_DATA_REG(_x) (0x0503 + (_x)) +#define RTL8367_TA_VLAN_DATA_SIZE 4 +#define RTL8367_TA_VLAN_VID_MASK RTL8367_VID_MASK +#define RTL8367_TA_VLAN_MEMBER_SHIFT 0 +#define RTL8367_TA_VLAN_MEMBER_MASK RTL8367_MEMBER_MASK +#define RTL8367_TA_VLAN_FID_SHIFT 0 +#define RTL8367_TA_VLAN_FID_MASK RTL8367_FID_MASK +#define RTL8367_TA_VLAN_UNTAG1_SHIFT 14 +#define RTL8367_TA_VLAN_UNTAG1_MASK 0x3 +#define RTL8367_TA_VLAN_UNTAG2_SHIFT 0 +#define RTL8367_TA_VLAN_UNTAG2_MASK 0x3fff + +#define RTL8367_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2) +#define RTL8367_VLAN_PVID_CTRL_MASK 0x1f +#define RTL8367_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2)) + +#define RTL8367_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4) +#define RTL8367_VLAN_MC_DATA_SIZE 4 +#define RTL8367_VLAN_MC_MEMBER_SHIFT 0 +#define RTL8367_VLAN_MC_MEMBER_MASK RTL8367_MEMBER_MASK +#define RTL8367_VLAN_MC_FID_SHIFT 0 +#define RTL8367_VLAN_MC_FID_MASK RTL8367_FID_MASK +#define RTL8367_VLAN_MC_EVID_SHIFT 0 +#define RTL8367_VLAN_MC_EVID_MASK RTL8367_VID_MASK + +#define RTL8367_VLAN_CTRL_REG 0x07a8 +#define RTL8367_VLAN_CTRL_ENABLE BIT(0) + +#define RTL8367_VLAN_INGRESS_REG 0x07a9 + +#define RTL8367_PORT_ISOLATION_REG(_p) (0x08a2 + (_p)) + +#define RTL8367_MIB_COUNTER_REG(_x) (0x1000 + (_x)) + +#define RTL8367_MIB_ADDRESS_REG 0x1004 + +#define RTL8367_MIB_CTRL_REG(_x) (0x1005 + (_x)) +#define RTL8367_MIB_CTRL_GLOBAL_RESET_MASK BIT(11) +#define RTL8367_MIB_CTRL_QM_RESET_MASK BIT(10) +#define RTL8367_MIB_CTRL_PORT_RESET_MASK(_p) BIT(2 + (_p)) +#define RTL8367_MIB_CTRL_RESET_MASK BIT(1) +#define RTL8367_MIB_CTRL_BUSY_MASK BIT(0) + +#define RTL8367_MIB_COUNT 36 +#define RTL8367_MIB_COUNTER_PORT_OFFSET 0x0050 + +#define RTL8367_SWC0_REG 0x1200 +#define RTL8367_SWC0_MAX_LENGTH_SHIFT 13 +#define RTL8367_SWC0_MAX_LENGTH(_x) ((_x) << 13) +#define RTL8367_SWC0_MAX_LENGTH_MASK RTL8367_SWC0_MAX_LENGTH(0x3) +#define RTL8367_SWC0_MAX_LENGTH_1522 RTL8367_SWC0_MAX_LENGTH(0) +#define RTL8367_SWC0_MAX_LENGTH_1536 RTL8367_SWC0_MAX_LENGTH(1) +#define RTL8367_SWC0_MAX_LENGTH_1552 RTL8367_SWC0_MAX_LENGTH(2) +#define RTL8367_SWC0_MAX_LENGTH_16000 RTL8367_SWC0_MAX_LENGTH(3) + +#define RTL8367_CHIP_NUMBER_REG 0x1300 + +#define RTL8367_CHIP_VER_REG 0x1301 +#define RTL8367_CHIP_VER_RLVID_SHIFT 12 +#define RTL8367_CHIP_VER_RLVID_MASK 0xf +#define RTL8367_CHIP_VER_MCID_SHIFT 8 +#define RTL8367_CHIP_VER_MCID_MASK 0xf +#define RTL8367_CHIP_VER_BOID_SHIFT 4 +#define RTL8367_CHIP_VER_BOID_MASK 0xf + +#define RTL8367_CHIP_MODE_REG 0x1302 +#define RTL8367_CHIP_MODE_MASK 0x7 + +#define RTL8367_CHIP_DEBUG0_REG 0x1303 +#define RTL8367_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x)) + +#define RTL8367_CHIP_DEBUG1_REG 0x1304 + +#define RTL8367_DIS_REG 0x1305 +#define RTL8367_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x)) +#define RTL8367_DIS_RGMII_SHIFT(_x) (4 * (_x)) +#define RTL8367_DIS_RGMII_MASK 0x7 + +#define RTL8367_EXT_RGMXF_REG(_x) (0x1306 + (_x)) +#define RTL8367_EXT_RGMXF_DUMMY0_SHIFT 5 +#define RTL8367_EXT_RGMXF_DUMMY0_MASK 0x7ff +#define RTL8367_EXT_RGMXF_TXDELAY_SHIFT 3 +#define RTL8367_EXT_RGMXF_TXDELAY_MASK 1 +#define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7 + +#define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x)) +#define RTL8367_DI_FORCE_MODE BIT(12) +#define RTL8367_DI_FORCE_NWAY BIT(7) +#define RTL8367_DI_FORCE_TXPAUSE BIT(6) +#define RTL8367_DI_FORCE_RXPAUSE BIT(5) +#define RTL8367_DI_FORCE_LINK BIT(4) +#define RTL8367_DI_FORCE_DUPLEX BIT(2) +#define RTL8367_DI_FORCE_SPEED_MASK 3 +#define RTL8367_DI_FORCE_SPEED_10 0 +#define RTL8367_DI_FORCE_SPEED_100 1 +#define RTL8367_DI_FORCE_SPEED_1000 2 + +#define RTL8367_MAC_FORCE_REG(_x) (0x1312 + (_x)) + +#define RTL8367_CHIP_RESET_REG 0x1322 +#define RTL8367_CHIP_RESET_SW BIT(1) +#define RTL8367_CHIP_RESET_HW BIT(0) + +#define RTL8367_PORT_STATUS_REG(_p) (0x1352 + (_p)) +#define RTL8367_PORT_STATUS_NWAY BIT(7) +#define RTL8367_PORT_STATUS_TXPAUSE BIT(6) +#define RTL8367_PORT_STATUS_RXPAUSE BIT(5) +#define RTL8367_PORT_STATUS_LINK BIT(4) +#define RTL8367_PORT_STATUS_DUPLEX BIT(2) +#define RTL8367_PORT_STATUS_SPEED_MASK 0x0003 +#define RTL8367_PORT_STATUS_SPEED_10 0 +#define RTL8367_PORT_STATUS_SPEED_100 1 +#define RTL8367_PORT_STATUS_SPEED_1000 2 + +#define RTL8367_RTL_NO_REG 0x13c0 +#define RTL8367_RTL_NO_8367R 0x3670 +#define RTL8367_RTL_NO_8367M 0x3671 + +#define RTL8367_RTL_VER_REG 0x13c1 +#define RTL8367_RTL_VER_MASK 0xf + +#define RTL8367_RTL_MAGIC_ID_REG 0x13c2 +#define RTL8367_RTL_MAGIC_ID_VAL 0x0249 + +#define RTL8367_LED_SYS_CONFIG_REG 0x1b00 +#define RTL8367_LED_MODE_REG 0x1b02 +#define RTL8367_LED_MODE_RATE_M 0x7 +#define RTL8367_LED_MODE_RATE_S 1 + +#define RTL8367_LED_CONFIG_REG 0x1b03 +#define RTL8367_LED_CONFIG_DATA_S 12 +#define RTL8367_LED_CONFIG_DATA_M 0x3 +#define RTL8367_LED_CONFIG_SEL BIT(14) +#define RTL8367_LED_CONFIG_LED_CFG_M 0xf + +#define RTL8367_PARA_LED_IO_EN1_REG 0x1b24 +#define RTL8367_PARA_LED_IO_EN2_REG 0x1b25 +#define RTL8367_PARA_LED_IO_EN_PMASK 0xff + +#define RTL8367_IA_CTRL_REG 0x1f00 +#define RTL8367_IA_CTRL_RW(_x) ((_x) << 1) +#define RTL8367_IA_CTRL_RW_READ RTL8367_IA_CTRL_RW(0) +#define RTL8367_IA_CTRL_RW_WRITE RTL8367_IA_CTRL_RW(1) +#define RTL8367_IA_CTRL_CMD_MASK BIT(0) + +#define RTL8367_IA_STATUS_REG 0x1f01 +#define RTL8367_IA_STATUS_PHY_BUSY BIT(2) +#define RTL8367_IA_STATUS_SDS_BUSY BIT(1) +#define RTL8367_IA_STATUS_MDX_BUSY BIT(0) + +#define RTL8367_IA_ADDRESS_REG 0x1f02 + +#define RTL8367_IA_WRITE_DATA_REG 0x1f03 +#define RTL8367_IA_READ_DATA_REG 0x1f04 + +#define RTL8367_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r)) + +#define RTL8367_CPU_PORT_NUM 9 +#define RTL8367_NUM_PORTS 10 +#define RTL8367_NUM_VLANS 32 +#define RTL8367_NUM_LEDGROUPS 4 +#define RTL8367_NUM_VIDS 4096 +#define RTL8367_PRIORITYMAX 7 +#define RTL8367_FIDMAX 7 + +#define RTL8367_PORT_0 BIT(0) +#define RTL8367_PORT_1 BIT(1) +#define RTL8367_PORT_2 BIT(2) +#define RTL8367_PORT_3 BIT(3) +#define RTL8367_PORT_4 BIT(4) +#define RTL8367_PORT_5 BIT(5) +#define RTL8367_PORT_6 BIT(6) +#define RTL8367_PORT_7 BIT(7) +#define RTL8367_PORT_E1 BIT(8) /* external port 1 */ +#define RTL8367_PORT_E0 BIT(9) /* external port 0 */ + +#define RTL8367_PORTS_ALL \ + (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \ + RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \ + RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1 | \ + RTL8367_PORT_E0) + +#define RTL8367_PORTS_ALL_BUT_CPU \ + (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \ + RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \ + RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1) + +struct rtl8367_initval { + u16 reg; + u16 val; +}; + +static struct rtl8366_mib_counter rtl8367_mib_counters[] = { + { 0, 0, 4, "IfInOctets" }, + { 0, 4, 2, "Dot3StatsFCSErrors" }, + { 0, 6, 2, "Dot3StatsSymbolErrors" }, + { 0, 8, 2, "Dot3InPauseFrames" }, + { 0, 10, 2, "Dot3ControlInUnknownOpcodes" }, + { 0, 12, 2, "EtherStatsFragments" }, + { 0, 14, 2, "EtherStatsJabbers" }, + { 0, 16, 2, "IfInUcastPkts" }, + { 0, 18, 2, "EtherStatsDropEvents" }, + { 0, 20, 4, "EtherStatsOctets" }, + + { 0, 24, 2, "EtherStatsUnderSizePkts" }, + { 0, 26, 2, "EtherOversizeStats" }, + { 0, 28, 2, "EtherStatsPkts64Octets" }, + { 0, 30, 2, "EtherStatsPkts65to127Octets" }, + { 0, 32, 2, "EtherStatsPkts128to255Octets" }, + { 0, 34, 2, "EtherStatsPkts256to511Octets" }, + { 0, 36, 2, "EtherStatsPkts512to1023Octets" }, + { 0, 38, 2, "EtherStatsPkts1024to1518Octets" }, + { 0, 40, 2, "EtherStatsMulticastPkts" }, + { 0, 42, 2, "EtherStatsBroadcastPkts" }, + + { 0, 44, 4, "IfOutOctets" }, + + { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, + { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, + { 0, 52, 2, "Dot3sDeferredTransmissions" }, + { 0, 54, 2, "Dot3StatsLateCollisions" }, + { 0, 56, 2, "EtherStatsCollisions" }, + { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, + { 0, 60, 2, "Dot3OutPauseFrames" }, + { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, + { 0, 64, 2, "Dot1dTpPortInDiscards" }, + { 0, 66, 2, "IfOutUcastPkts" }, + { 0, 68, 2, "IfOutMulticastPkts" }, + { 0, 70, 2, "IfOutBroadcastPkts" }, + { 0, 72, 2, "OutOampduPkts" }, + { 0, 74, 2, "InOampduPkts" }, + { 0, 76, 2, "PktgenPkts" }, +}; + +#define REG_RD(_smi, _reg, _val) \ + do { \ + err = rtl8366_smi_read_reg(_smi, _reg, _val); \ + if (err) \ + return err; \ + } while (0) + +#define REG_WR(_smi, _reg, _val) \ + do { \ + err = rtl8366_smi_write_reg(_smi, _reg, _val); \ + if (err) \ + return err; \ + } while (0) + +#define REG_RMW(_smi, _reg, _mask, _val) \ + do { \ + err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \ + if (err) \ + return err; \ + } while (0) + +static const struct rtl8367_initval rtl8367_initvals_0_0[] = { + {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006}, + {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048}, + {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412}, + {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0}, + {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4}, + {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7}, + {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003}, + {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2}, + {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207}, + {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620}, + {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede}, + {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1}, + {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00}, + {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002}, + {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000}, + {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f}, + {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A}, + {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005}, + {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA}, + {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055}, + {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354}, + {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB}, + {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1006}, {0x121e, 0x03e8}, + {0x121f, 0x02b3}, {0x1220, 0x028f}, {0x1221, 0x029b}, {0x1222, 0x0277}, + {0x1223, 0x02b3}, {0x1224, 0x028f}, {0x1225, 0x029b}, {0x1226, 0x0277}, + {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, {0x1230, 0x00b4}, + {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024}, + {0x0219, 0x0032}, {0x0200, 0x03e8}, {0x0201, 0x03e8}, {0x0202, 0x03e8}, + {0x0203, 0x03e8}, {0x0204, 0x03e8}, {0x0205, 0x03e8}, {0x0206, 0x03e8}, + {0x0207, 0x03e8}, {0x0218, 0x0032}, {0x0208, 0x029b}, {0x0209, 0x029b}, + {0x020a, 0x029b}, {0x020b, 0x029b}, {0x020c, 0x029b}, {0x020d, 0x029b}, + {0x020e, 0x029b}, {0x020f, 0x029b}, {0x0210, 0x029b}, {0x0211, 0x029b}, + {0x0212, 0x029b}, {0x0213, 0x029b}, {0x0214, 0x029b}, {0x0215, 0x029b}, + {0x0216, 0x029b}, {0x0217, 0x029b}, {0x0900, 0x0000}, {0x0901, 0x0000}, + {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, + {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, + {0x0802, 0x0100}, {0x1700, 0x014C}, {0x0301, 0x00FF}, {0x12AA, 0x0096}, + {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4}, + {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340}, + {0x133f, 0x0010}, {0x20A0, 0x1940}, {0x20C0, 0x1940}, {0x20E0, 0x1940}, +}; + +static const struct rtl8367_initval rtl8367_initvals_0_1[] = { + {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006}, + {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048}, + {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412}, + {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0}, + {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4}, + {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7}, + {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003}, + {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2}, + {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207}, + {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620}, + {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede}, + {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1}, + {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00}, + {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002}, + {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000}, + {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f}, + {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A}, + {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005}, + {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA}, + {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055}, + {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354}, + {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB}, + {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1b06}, {0x121e, 0x07f0}, + {0x121f, 0x0438}, {0x1220, 0x040f}, {0x1221, 0x040f}, {0x1222, 0x03eb}, + {0x1223, 0x0438}, {0x1224, 0x040f}, {0x1225, 0x040f}, {0x1226, 0x03eb}, + {0x1227, 0x0144}, {0x1228, 0x0138}, {0x122f, 0x0144}, {0x1230, 0x0138}, + {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024}, + {0x0219, 0x0032}, {0x0200, 0x07d0}, {0x0201, 0x07d0}, {0x0202, 0x07d0}, + {0x0203, 0x07d0}, {0x0204, 0x07d0}, {0x0205, 0x07d0}, {0x0206, 0x07d0}, + {0x0207, 0x07d0}, {0x0218, 0x0032}, {0x0208, 0x0190}, {0x0209, 0x0190}, + {0x020a, 0x0190}, {0x020b, 0x0190}, {0x020c, 0x0190}, {0x020d, 0x0190}, + {0x020e, 0x0190}, {0x020f, 0x0190}, {0x0210, 0x0190}, {0x0211, 0x0190}, + {0x0212, 0x0190}, {0x0213, 0x0190}, {0x0214, 0x0190}, {0x0215, 0x0190}, + {0x0216, 0x0190}, {0x0217, 0x0190}, {0x0900, 0x0000}, {0x0901, 0x0000}, + {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, + {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, + {0x0802, 0x0100}, {0x1700, 0x0125}, {0x0301, 0x00FF}, {0x12AA, 0x0096}, + {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4}, + {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340}, + {0x133f, 0x0010}, +}; + +static const struct rtl8367_initval rtl8367_initvals_1_0[] = { + {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000}, + {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030}, + {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82}, + {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938}, + {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001}, + {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007}, + {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C}, + {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, + {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0}, + {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7}, + {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA}, + {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A}, + {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D}, + {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806}, + {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5}, + {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB}, + {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0}, + {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89}, + {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF}, + {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640}, + {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729}, + {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00}, + {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B}, + {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32}, + {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52}, + {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C}, + {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D}, + {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053}, + {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B}, + {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771}, + {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7}, + {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A}, + {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600}, + {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000}, + {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65}, + {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007}, + {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010}, + {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000}, + {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115}, + {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C}, + {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4}, + {0x121D, 0x7D16}, {0x121E, 0x03E8}, {0x121F, 0x024E}, {0x1220, 0x0230}, + {0x1221, 0x0244}, {0x1222, 0x0226}, {0x1223, 0x024E}, {0x1224, 0x0230}, + {0x1225, 0x0244}, {0x1226, 0x0226}, {0x1227, 0x00C0}, {0x1228, 0x00B4}, + {0x122F, 0x00C0}, {0x1230, 0x00B4}, {0x0208, 0x03E8}, {0x0209, 0x03E8}, + {0x020A, 0x03E8}, {0x020B, 0x03E8}, {0x020C, 0x03E8}, {0x020D, 0x03E8}, + {0x020E, 0x03E8}, {0x020F, 0x03E8}, {0x0210, 0x03E8}, {0x0211, 0x03E8}, + {0x0212, 0x03E8}, {0x0213, 0x03E8}, {0x0214, 0x03E8}, {0x0215, 0x03E8}, + {0x0216, 0x03E8}, {0x0217, 0x03E8}, {0x0900, 0x0000}, {0x0901, 0x0000}, + {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087B, 0x0000}, + {0x087C, 0xFF00}, {0x087D, 0x0000}, {0x087E, 0x0000}, {0x0801, 0x0100}, + {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, + {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, + {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, {0x2200, 0x1340}, + {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x20A0, 0x1940}, + {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050}, +}; + +static const struct rtl8367_initval rtl8367_initvals_1_1[] = { + {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000}, + {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030}, + {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82}, + {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938}, + {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001}, + {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007}, + {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C}, + {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, + {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0}, + {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7}, + {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA}, + {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A}, + {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D}, + {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806}, + {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5}, + {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB}, + {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0}, + {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89}, + {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF}, + {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640}, + {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729}, + {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00}, + {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B}, + {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32}, + {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52}, + {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C}, + {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D}, + {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053}, + {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B}, + {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771}, + {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7}, + {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A}, + {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600}, + {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000}, + {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65}, + {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007}, + {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010}, + {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000}, + {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115}, + {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C}, + {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4}, + {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, + {0x0865, 0x3210}, {0x087B, 0x0000}, {0x087C, 0xFF00}, {0x087D, 0x0000}, + {0x087E, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, + {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, + {0x0A25, 0x2040}, {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, + {0x0A29, 0x2040}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, + {0x2200, 0x1340}, {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, + {0x1B03, 0x0876}, +}; + +static const struct rtl8367_initval rtl8367_initvals_2_0[] = { + {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000}, + {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048}, + {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8}, + {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207}, + {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000}, + {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005}, + {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000}, + {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7}, + {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e}, + {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201}, + {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e}, + {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000}, + {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00}, + {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6}, + {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140}, + {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4}, + {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa}, + {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a}, + {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978}, + {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806}, + {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5}, + {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425}, + {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e}, + {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68}, + {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d}, + {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365}, + {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d}, + {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036}, + {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce}, + {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530}, + {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a}, + {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100}, + {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306}, + {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77}, + {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f}, + {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405}, + {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010}, + {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x7D16}, + {0x121e, 0x03e8}, {0x121f, 0x024e}, {0x1220, 0x0230}, {0x1221, 0x0244}, + {0x1222, 0x0226}, {0x1223, 0x024e}, {0x1224, 0x0230}, {0x1225, 0x0244}, + {0x1226, 0x0226}, {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, + {0x1230, 0x00b4}, {0x0208, 0x03e8}, {0x0209, 0x03e8}, {0x020a, 0x03e8}, + {0x020b, 0x03e8}, {0x020c, 0x03e8}, {0x020d, 0x03e8}, {0x020e, 0x03e8}, + {0x020f, 0x03e8}, {0x0210, 0x03e8}, {0x0211, 0x03e8}, {0x0212, 0x03e8}, + {0x0213, 0x03e8}, {0x0214, 0x03e8}, {0x0215, 0x03e8}, {0x0216, 0x03e8}, + {0x0217, 0x03e8}, {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, + {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, {0x087c, 0xff00}, + {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, + {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, + {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, {0x20A0, 0x1940}, + {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050}, +}; + +static const struct rtl8367_initval rtl8367_initvals_2_1[] = { + {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000}, + {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048}, + {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8}, + {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207}, + {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000}, + {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005}, + {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000}, + {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7}, + {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e}, + {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201}, + {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e}, + {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000}, + {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00}, + {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6}, + {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140}, + {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4}, + {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa}, + {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a}, + {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978}, + {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806}, + {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5}, + {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425}, + {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e}, + {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68}, + {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d}, + {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365}, + {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d}, + {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036}, + {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce}, + {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530}, + {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a}, + {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100}, + {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306}, + {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77}, + {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f}, + {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405}, + {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010}, + {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x0900, 0x0000}, + {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, + {0x087b, 0x0000}, {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, + {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, + {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A25, 0x2040}, + {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, + {0x130c, 0x0050}, +}; + +static int rtl8367_write_initvals(struct rtl8366_smi *smi, + const struct rtl8367_initval *initvals, + int count) +{ + int err; + int i; + + for (i = 0; i < count; i++) + REG_WR(smi, initvals[i].reg, initvals[i].val); + + return 0; +} + +static int rtl8367_read_phy_reg(struct rtl8366_smi *smi, + u32 phy_addr, u32 phy_reg, u32 *val) +{ + int timeout; + u32 data; + int err; + + if (phy_addr > RTL8367_PHY_ADDR_MAX) + return -EINVAL; + + if (phy_reg > RTL8367_PHY_REG_MAX) + return -EINVAL; + + REG_RD(smi, RTL8367_IA_STATUS_REG, &data); + if (data & RTL8367_IA_STATUS_PHY_BUSY) + return -ETIMEDOUT; + + /* prepare address */ + REG_WR(smi, RTL8367_IA_ADDRESS_REG, + RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg)); + + /* send read command */ + REG_WR(smi, RTL8367_IA_CTRL_REG, + RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_READ); + + timeout = 5; + do { + REG_RD(smi, RTL8367_IA_STATUS_REG, &data); + if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0) + break; + + if (timeout--) { + dev_err(smi->parent, "phy read timed out\n"); + return -ETIMEDOUT; + } + + udelay(1); + } while (1); + + /* read data */ + REG_RD(smi, RTL8367_IA_READ_DATA_REG, val); + + dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n", + phy_addr, phy_reg, *val); + return 0; +} + +static int rtl8367_write_phy_reg(struct rtl8366_smi *smi, + u32 phy_addr, u32 phy_reg, u32 val) +{ + int timeout; + u32 data; + int err; + + dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n", + phy_addr, phy_reg, val); + + if (phy_addr > RTL8367_PHY_ADDR_MAX) + return -EINVAL; + + if (phy_reg > RTL8367_PHY_REG_MAX) + return -EINVAL; + + REG_RD(smi, RTL8367_IA_STATUS_REG, &data); + if (data & RTL8367_IA_STATUS_PHY_BUSY) + return -ETIMEDOUT; + + /* preapre data */ + REG_WR(smi, RTL8367_IA_WRITE_DATA_REG, val); + + /* prepare address */ + REG_WR(smi, RTL8367_IA_ADDRESS_REG, + RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg)); + + /* send write command */ + REG_WR(smi, RTL8367_IA_CTRL_REG, + RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_WRITE); + + timeout = 5; + do { + REG_RD(smi, RTL8367_IA_STATUS_REG, &data); + if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0) + break; + + if (timeout--) { + dev_err(smi->parent, "phy write timed out\n"); + return -ETIMEDOUT; + } + + udelay(1); + } while (1); + + return 0; +} + +static int rtl8367_init_regs0(struct rtl8366_smi *smi, unsigned mode) +{ + const struct rtl8367_initval *initvals; + int count; + int err; + + switch (mode) { + case 0: + initvals = rtl8367_initvals_0_0; + count = ARRAY_SIZE(rtl8367_initvals_0_0); + break; + + case 1: + case 2: + initvals = rtl8367_initvals_0_1; + count = ARRAY_SIZE(rtl8367_initvals_0_1); + break; + + default: + dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode); + return -ENODEV; + } + + err = rtl8367_write_initvals(smi, initvals, count); + if (err) + return err; + + /* TODO: complete this */ + + return 0; +} + +static int rtl8367_init_regs1(struct rtl8366_smi *smi, unsigned mode) +{ + const struct rtl8367_initval *initvals; + int count; + + switch (mode) { + case 0: + initvals = rtl8367_initvals_1_0; + count = ARRAY_SIZE(rtl8367_initvals_1_0); + break; + + case 1: + case 2: + initvals = rtl8367_initvals_1_1; + count = ARRAY_SIZE(rtl8367_initvals_1_1); + break; + + default: + dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode); + return -ENODEV; + } + + return rtl8367_write_initvals(smi, initvals, count); +} + +static int rtl8367_init_regs2(struct rtl8366_smi *smi, unsigned mode) +{ + const struct rtl8367_initval *initvals; + int count; + + switch (mode) { + case 0: + initvals = rtl8367_initvals_2_0; + count = ARRAY_SIZE(rtl8367_initvals_2_0); + break; + + case 1: + case 2: + initvals = rtl8367_initvals_2_1; + count = ARRAY_SIZE(rtl8367_initvals_2_1); + break; + + default: + dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode); + return -ENODEV; + } + + return rtl8367_write_initvals(smi, initvals, count); +} + +static int rtl8367_init_regs(struct rtl8366_smi *smi) +{ + u32 data; + u32 rlvid; + u32 mode; + int err; + + REG_WR(smi, RTL8367_RTL_MAGIC_ID_REG, RTL8367_RTL_MAGIC_ID_VAL); + + REG_RD(smi, RTL8367_CHIP_VER_REG, &data); + rlvid = (data >> RTL8367_CHIP_VER_RLVID_SHIFT) & + RTL8367_CHIP_VER_RLVID_MASK; + + REG_RD(smi, RTL8367_CHIP_MODE_REG, &data); + mode = data & RTL8367_CHIP_MODE_MASK; + + switch (rlvid) { + case 0: + err = rtl8367_init_regs0(smi, mode); + break; + + case 1: + err = rtl8367_write_phy_reg(smi, 0, 31, 5); + if (err) + break; + + err = rtl8367_write_phy_reg(smi, 0, 5, 0x3ffe); + if (err) + break; + + err = rtl8367_read_phy_reg(smi, 0, 6, &data); + if (err) + break; + + if (data == 0x94eb) { + err = rtl8367_init_regs1(smi, mode); + } else if (data == 0x2104) { + err = rtl8367_init_regs2(smi, mode); + } else { + dev_err(smi->parent, "unknow phy data %04x\n", data); + return -ENODEV; + } + + break; + + default: + dev_err(smi->parent, "unknow rlvid %u\n", rlvid); + err = -ENODEV; + break; + } + + return err; +} + +static int rtl8367_reset_chip(struct rtl8366_smi *smi) +{ + int timeout = 10; + int err; + u32 data; + + REG_WR(smi, RTL8367_CHIP_RESET_REG, RTL8367_CHIP_RESET_HW); + msleep(RTL8367_RESET_DELAY); + + do { + REG_RD(smi, RTL8367_CHIP_RESET_REG, &data); + if (!(data & RTL8367_CHIP_RESET_HW)) + break; + + msleep(1); + } while (--timeout); + + if (!timeout) { + dev_err(smi->parent, "chip reset timed out\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int rtl8367_extif_set_mode(struct rtl8366_smi *smi, int id, + enum rtl8367_extif_mode mode) +{ + int err; + + /* set port mode */ + switch (mode) { + case RTL8367_EXTIF_MODE_RGMII: + case RTL8367_EXTIF_MODE_RGMII_33V: + REG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367); + REG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777); + break; + + case RTL8367_EXTIF_MODE_TMII_MAC: + case RTL8367_EXTIF_MODE_TMII_PHY: + REG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG, + BIT((id + 1) % 2), BIT((id + 1) % 2)); + break; + + case RTL8367_EXTIF_MODE_GMII: + REG_RMW(smi, RTL8367_CHIP_DEBUG0_REG, + RTL8367_CHIP_DEBUG0_DUMMY0(id), + RTL8367_CHIP_DEBUG0_DUMMY0(id)); + REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), BIT(6)); + break; + + case RTL8367_EXTIF_MODE_MII_MAC: + case RTL8367_EXTIF_MODE_MII_PHY: + case RTL8367_EXTIF_MODE_DISABLED: + REG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG, + BIT((id + 1) % 2), 0); + REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), 0); + break; + + default: + dev_err(smi->parent, + "invalid mode for external interface %d\n", id); + return -EINVAL; + } + + REG_RMW(smi, RTL8367_DIS_REG, + RTL8367_DIS_RGMII_MASK << RTL8367_DIS_RGMII_SHIFT(id), + mode << RTL8367_DIS_RGMII_SHIFT(id)); + + return 0; +} + +static int rtl8367_extif_set_force(struct rtl8366_smi *smi, int id, + struct rtl8367_port_ability *pa) +{ + u32 mask; + u32 val; + int err; + + mask = (RTL8367_DI_FORCE_MODE | + RTL8367_DI_FORCE_NWAY | + RTL8367_DI_FORCE_TXPAUSE | + RTL8367_DI_FORCE_RXPAUSE | + RTL8367_DI_FORCE_LINK | + RTL8367_DI_FORCE_DUPLEX | + RTL8367_DI_FORCE_SPEED_MASK); + + val = pa->speed; + val |= pa->force_mode ? RTL8367_DI_FORCE_MODE : 0; + val |= pa->nway ? RTL8367_DI_FORCE_NWAY : 0; + val |= pa->txpause ? RTL8367_DI_FORCE_TXPAUSE : 0; + val |= pa->rxpause ? RTL8367_DI_FORCE_RXPAUSE : 0; + val |= pa->link ? RTL8367_DI_FORCE_LINK : 0; + val |= pa->duplex ? RTL8367_DI_FORCE_DUPLEX : 0; + + REG_RMW(smi, RTL8367_DI_FORCE_REG(id), mask, val); + + return 0; +} + +static int rtl8367_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id, + unsigned txdelay, unsigned rxdelay) +{ + u32 mask; + u32 val; + int err; + + mask = (RTL8367_EXT_RGMXF_RXDELAY_MASK | + (RTL8367_EXT_RGMXF_TXDELAY_MASK << + RTL8367_EXT_RGMXF_TXDELAY_SHIFT)); + + val = rxdelay; + val |= txdelay << RTL8367_EXT_RGMXF_TXDELAY_SHIFT; + + REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), mask, val); + + return 0; +} + +static int rtl8367_extif_init(struct rtl8366_smi *smi, int id, + struct rtl8367_extif_config *cfg) +{ + enum rtl8367_extif_mode mode; + int err; + + mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED; + + err = rtl8367_extif_set_mode(smi, id, mode); + if (err) + return err; + + if (mode != RTL8367_EXTIF_MODE_DISABLED) { + err = rtl8367_extif_set_force(smi, id, &cfg->ability); + if (err) + return err; + + err = rtl8367_extif_set_rgmii_delay(smi, id, cfg->txdelay, + cfg->rxdelay); + if (err) + return err; + } + + return 0; +} + +static int rtl8367_led_group_set_ports(struct rtl8366_smi *smi, + unsigned int group, u16 port_mask) +{ + u32 reg; + u32 s; + int err; + + port_mask &= RTL8367_PARA_LED_IO_EN_PMASK; + s = (group % 2) * 8; + reg = RTL8367_PARA_LED_IO_EN1_REG + (group / 2); + + REG_RMW(smi, reg, (RTL8367_PARA_LED_IO_EN_PMASK << s), port_mask << s); + + return 0; +} + +static int rtl8367_led_group_set_mode(struct rtl8366_smi *smi, + unsigned int mode) +{ + u16 mask; + u16 set; + int err; + + mode &= RTL8367_LED_CONFIG_DATA_M; + + mask = (RTL8367_LED_CONFIG_DATA_M << RTL8367_LED_CONFIG_DATA_S) | + RTL8367_LED_CONFIG_SEL; + set = (mode << RTL8367_LED_CONFIG_DATA_S) | RTL8367_LED_CONFIG_SEL; + + REG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set); + + return 0; +} + +static int rtl8367_led_group_set_config(struct rtl8366_smi *smi, + unsigned int led, unsigned int cfg) +{ + u16 mask; + u16 set; + int err; + + mask = (RTL8367_LED_CONFIG_LED_CFG_M << (led * 4)) | + RTL8367_LED_CONFIG_SEL; + set = (cfg & RTL8367_LED_CONFIG_LED_CFG_M) << (led * 4); + + REG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set); + return 0; +} + +static int rtl8367_led_op_select_parallel(struct rtl8366_smi *smi) +{ + int err; + + REG_WR(smi, RTL8367_LED_SYS_CONFIG_REG, 0x1472); + return 0; +} + +static int rtl8367_led_blinkrate_set(struct rtl8366_smi *smi, unsigned int rate) +{ + u16 mask; + u16 set; + int err; + + mask = RTL8367_LED_MODE_RATE_M << RTL8367_LED_MODE_RATE_S; + set = (rate & RTL8367_LED_MODE_RATE_M) << RTL8367_LED_MODE_RATE_S; + REG_RMW(smi, RTL8367_LED_MODE_REG, mask, set); + + return 0; +} + +#ifdef CONFIG_OF +static int rtl8367_extif_init_of(struct rtl8366_smi *smi, int id, + const char *name) +{ + struct rtl8367_extif_config *cfg; + const __be32 *prop; + int size; + int err; + + prop = of_get_property(smi->parent->of_node, name, &size); + if (!prop) + return rtl8367_extif_init(smi, id, NULL); + + if (size != (9 * sizeof(*prop))) { + dev_err(smi->parent, "%s property is invalid\n", name); + return -EINVAL; + } + + cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL); + if (!cfg) + return -ENOMEM; + + cfg->txdelay = be32_to_cpup(prop++); + cfg->rxdelay = be32_to_cpup(prop++); + cfg->mode = be32_to_cpup(prop++); + cfg->ability.force_mode = be32_to_cpup(prop++); + cfg->ability.txpause = be32_to_cpup(prop++); + cfg->ability.rxpause = be32_to_cpup(prop++); + cfg->ability.link = be32_to_cpup(prop++); + cfg->ability.duplex = be32_to_cpup(prop++); + cfg->ability.speed = be32_to_cpup(prop++); + + err = rtl8367_extif_init(smi, id, cfg); + kfree(cfg); + + return err; +} +#else +static int rtl8367_extif_init_of(struct rtl8366_smi *smi, int id, + const char *name) +{ + return -EINVAL; +} +#endif + +static int rtl8367_setup(struct rtl8366_smi *smi) +{ + struct rtl8367_platform_data *pdata; + int err; + int i; + + pdata = smi->parent->platform_data; + + err = rtl8367_init_regs(smi); + if (err) + return err; + + /* initialize external interfaces */ + if (smi->parent->of_node) { + err = rtl8367_extif_init_of(smi, 0, "realtek,extif0"); + if (err) + return err; + + err = rtl8367_extif_init_of(smi, 1, "realtek,extif1"); + if (err) + return err; + } else { + err = rtl8367_extif_init(smi, 0, pdata->extif0_cfg); + if (err) + return err; + + err = rtl8367_extif_init(smi, 1, pdata->extif1_cfg); + if (err) + return err; + } + + /* set maximum packet length to 1536 bytes */ + REG_RMW(smi, RTL8367_SWC0_REG, RTL8367_SWC0_MAX_LENGTH_MASK, + RTL8367_SWC0_MAX_LENGTH_1536); + + /* + * discard VLAN tagged packets if the port is not a member of + * the VLAN with which the packets is associated. + */ + REG_WR(smi, RTL8367_VLAN_INGRESS_REG, RTL8367_PORTS_ALL); + + /* + * Setup egress tag mode for each port. + */ + for (i = 0; i < RTL8367_NUM_PORTS; i++) + REG_RMW(smi, + RTL8367_PORT_CFG_REG(i), + RTL8367_PORT_CFG_EGRESS_MODE_MASK << + RTL8367_PORT_CFG_EGRESS_MODE_SHIFT, + RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL << + RTL8367_PORT_CFG_EGRESS_MODE_SHIFT); + + /* setup LEDs */ + err = rtl8367_led_group_set_ports(smi, 0, RTL8367_PORTS_ALL); + if (err) + return err; + + err = rtl8367_led_group_set_mode(smi, 0); + if (err) + return err; + + err = rtl8367_led_op_select_parallel(smi); + if (err) + return err; + + err = rtl8367_led_blinkrate_set(smi, 1); + if (err) + return err; + + err = rtl8367_led_group_set_config(smi, 0, 2); + if (err) + return err; + + return 0; +} + +static int rtl8367_get_mib_counter(struct rtl8366_smi *smi, int counter, + int port, unsigned long long *val) +{ + struct rtl8366_mib_counter *mib; + int offset; + int i; + int err; + u32 addr, data; + u64 mibvalue; + + if (port > RTL8367_NUM_PORTS || counter >= RTL8367_MIB_COUNT) + return -EINVAL; + + mib = &rtl8367_mib_counters[counter]; + addr = RTL8367_MIB_COUNTER_PORT_OFFSET * port + mib->offset; + + /* + * Writing access counter address first + * then ASIC will prepare 64bits counter wait for being retrived + */ + REG_WR(smi, RTL8367_MIB_ADDRESS_REG, addr >> 2); + + /* read MIB control register */ + REG_RD(smi, RTL8367_MIB_CTRL_REG(0), &data); + + if (data & RTL8367_MIB_CTRL_BUSY_MASK) + return -EBUSY; + + if (data & RTL8367_MIB_CTRL_RESET_MASK) + return -EIO; + + if (mib->length == 4) + offset = 3; + else + offset = (mib->offset + 1) % 4; + + mibvalue = 0; + for (i = 0; i < mib->length; i++) { + REG_RD(smi, RTL8367_MIB_COUNTER_REG(offset - i), &data); + mibvalue = (mibvalue << 16) | (data & 0xFFFF); + } + + *val = mibvalue; + return 0; +} + +static int rtl8367_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, + struct rtl8366_vlan_4k *vlan4k) +{ + u32 data[RTL8367_TA_VLAN_DATA_SIZE]; + int err; + int i; + + memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); + + if (vid >= RTL8367_NUM_VIDS) + return -EINVAL; + + /* write VID */ + REG_WR(smi, RTL8367_TA_ADDR_REG, vid); + + /* write table access control word */ + REG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_READ); + + for (i = 0; i < ARRAY_SIZE(data); i++) + REG_RD(smi, RTL8367_TA_DATA_REG(i), &data[i]); + + vlan4k->vid = vid; + vlan4k->member = (data[0] >> RTL8367_TA_VLAN_MEMBER_SHIFT) & + RTL8367_TA_VLAN_MEMBER_MASK; + vlan4k->fid = (data[1] >> RTL8367_TA_VLAN_FID_SHIFT) & + RTL8367_TA_VLAN_FID_MASK; + vlan4k->untag = (data[2] >> RTL8367_TA_VLAN_UNTAG1_SHIFT) & + RTL8367_TA_VLAN_UNTAG1_MASK; + vlan4k->untag |= ((data[3] >> RTL8367_TA_VLAN_UNTAG2_SHIFT) & + RTL8367_TA_VLAN_UNTAG2_MASK) << 2; + + return 0; +} + +static int rtl8367_set_vlan_4k(struct rtl8366_smi *smi, + const struct rtl8366_vlan_4k *vlan4k) +{ + u32 data[RTL8367_TA_VLAN_DATA_SIZE]; + int err; + int i; + + if (vlan4k->vid >= RTL8367_NUM_VIDS || + vlan4k->member > RTL8367_TA_VLAN_MEMBER_MASK || + vlan4k->untag > RTL8367_UNTAG_MASK || + vlan4k->fid > RTL8367_FIDMAX) + return -EINVAL; + + data[0] = (vlan4k->member & RTL8367_TA_VLAN_MEMBER_MASK) << + RTL8367_TA_VLAN_MEMBER_SHIFT; + data[1] = (vlan4k->fid & RTL8367_TA_VLAN_FID_MASK) << + RTL8367_TA_VLAN_FID_SHIFT; + data[2] = (vlan4k->untag & RTL8367_TA_VLAN_UNTAG1_MASK) << + RTL8367_TA_VLAN_UNTAG1_SHIFT; + data[3] = ((vlan4k->untag >> 2) & RTL8367_TA_VLAN_UNTAG2_MASK) << + RTL8367_TA_VLAN_UNTAG2_SHIFT; + + for (i = 0; i < ARRAY_SIZE(data); i++) + REG_WR(smi, RTL8367_TA_DATA_REG(i), data[i]); + + /* write VID */ + REG_WR(smi, RTL8367_TA_ADDR_REG, + vlan4k->vid & RTL8367_TA_VLAN_VID_MASK); + + /* write table access control word */ + REG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_WRITE); + + return 0; +} + +static int rtl8367_get_vlan_mc(struct rtl8366_smi *smi, u32 index, + struct rtl8366_vlan_mc *vlanmc) +{ + u32 data[RTL8367_VLAN_MC_DATA_SIZE]; + int err; + int i; + + memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); + + if (index >= RTL8367_NUM_VLANS) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(data); i++) + REG_RD(smi, RTL8367_VLAN_MC_BASE(index) + i, &data[i]); + + vlanmc->member = (data[0] >> RTL8367_VLAN_MC_MEMBER_SHIFT) & + RTL8367_VLAN_MC_MEMBER_MASK; + vlanmc->fid = (data[1] >> RTL8367_VLAN_MC_FID_SHIFT) & + RTL8367_VLAN_MC_FID_MASK; + vlanmc->vid = (data[3] >> RTL8367_VLAN_MC_EVID_SHIFT) & + RTL8367_VLAN_MC_EVID_MASK; + + return 0; +} + +static int rtl8367_set_vlan_mc(struct rtl8366_smi *smi, u32 index, + const struct rtl8366_vlan_mc *vlanmc) +{ + u32 data[RTL8367_VLAN_MC_DATA_SIZE]; + int err; + int i; + + if (index >= RTL8367_NUM_VLANS || + vlanmc->vid >= RTL8367_NUM_VIDS || + vlanmc->priority > RTL8367_PRIORITYMAX || + vlanmc->member > RTL8367_VLAN_MC_MEMBER_MASK || + vlanmc->untag > RTL8367_UNTAG_MASK || + vlanmc->fid > RTL8367_FIDMAX) + return -EINVAL; + + data[0] = (vlanmc->member & RTL8367_VLAN_MC_MEMBER_MASK) << + RTL8367_VLAN_MC_MEMBER_SHIFT; + data[1] = (vlanmc->fid & RTL8367_VLAN_MC_FID_MASK) << + RTL8367_VLAN_MC_FID_SHIFT; + data[2] = 0; + data[3] = (vlanmc->vid & RTL8367_VLAN_MC_EVID_MASK) << + RTL8367_VLAN_MC_EVID_SHIFT; + + for (i = 0; i < ARRAY_SIZE(data); i++) + REG_WR(smi, RTL8367_VLAN_MC_BASE(index) + i, data[i]); + + return 0; +} + +static int rtl8367_get_mc_index(struct rtl8366_smi *smi, int port, int *val) +{ + u32 data; + int err; + + if (port >= RTL8367_NUM_PORTS) + return -EINVAL; + + REG_RD(smi, RTL8367_VLAN_PVID_CTRL_REG(port), &data); + + *val = (data >> RTL8367_VLAN_PVID_CTRL_SHIFT(port)) & + RTL8367_VLAN_PVID_CTRL_MASK; + + return 0; +} + +static int rtl8367_set_mc_index(struct rtl8366_smi *smi, int port, int index) +{ + if (port >= RTL8367_NUM_PORTS || index >= RTL8367_NUM_VLANS) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8367_VLAN_PVID_CTRL_REG(port), + RTL8367_VLAN_PVID_CTRL_MASK << + RTL8367_VLAN_PVID_CTRL_SHIFT(port), + (index & RTL8367_VLAN_PVID_CTRL_MASK) << + RTL8367_VLAN_PVID_CTRL_SHIFT(port)); +} + +static int rtl8367_enable_vlan(struct rtl8366_smi *smi, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8367_VLAN_CTRL_REG, + RTL8367_VLAN_CTRL_ENABLE, + (enable) ? RTL8367_VLAN_CTRL_ENABLE : 0); +} + +static int rtl8367_enable_vlan4k(struct rtl8366_smi *smi, int enable) +{ + return 0; +} + +static int rtl8367_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan) +{ + unsigned max = RTL8367_NUM_VLANS; + + if (smi->vlan4k_enabled) + max = RTL8367_NUM_VIDS - 1; + + if (vlan == 0 || vlan >= max) + return 0; + + return 1; +} + +static int rtl8367_enable_port(struct rtl8366_smi *smi, int port, int enable) +{ + int err; + + REG_WR(smi, RTL8367_PORT_ISOLATION_REG(port), + (enable) ? RTL8367_PORTS_ALL : 0); + + return 0; +} + +static int rtl8367_sw_reset_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + return rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(0), 0, + RTL8367_MIB_CTRL_GLOBAL_RESET_MASK); +} + +static int rtl8367_sw_get_port_link(struct switch_dev *dev, + int port, + struct switch_port_link *link) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data = 0; + u32 speed; + + if (port >= RTL8367_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8367_PORT_STATUS_REG(port), &data); + + link->link = !!(data & RTL8367_PORT_STATUS_LINK); + if (!link->link) + return 0; + + link->duplex = !!(data & RTL8367_PORT_STATUS_DUPLEX); + link->rx_flow = !!(data & RTL8367_PORT_STATUS_RXPAUSE); + link->tx_flow = !!(data & RTL8367_PORT_STATUS_TXPAUSE); + link->aneg = !!(data & RTL8367_PORT_STATUS_NWAY); + + speed = (data & RTL8367_PORT_STATUS_SPEED_MASK); + switch (speed) { + case 0: + link->speed = SWITCH_PORT_SPEED_10; + break; + case 1: + link->speed = SWITCH_PORT_SPEED_100; + break; + case 2: + link->speed = SWITCH_PORT_SPEED_1000; + break; + default: + link->speed = SWITCH_PORT_SPEED_UNKNOWN; + break; + } + + return 0; +} + +static int rtl8367_sw_get_max_length(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8367_SWC0_REG, &data); + val->value.i = (data & RTL8367_SWC0_MAX_LENGTH_MASK) >> + RTL8367_SWC0_MAX_LENGTH_SHIFT; + + return 0; +} + +static int rtl8367_sw_set_max_length(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 max_len; + + switch (val->value.i) { + case 0: + max_len = RTL8367_SWC0_MAX_LENGTH_1522; + break; + case 1: + max_len = RTL8367_SWC0_MAX_LENGTH_1536; + break; + case 2: + max_len = RTL8367_SWC0_MAX_LENGTH_1552; + break; + case 3: + max_len = RTL8367_SWC0_MAX_LENGTH_16000; + break; + default: + return -EINVAL; + } + + return rtl8366_smi_rmwr(smi, RTL8367_SWC0_REG, + RTL8367_SWC0_MAX_LENGTH_MASK, max_len); +} + + +static int rtl8367_sw_reset_port_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + int port; + + port = val->port_vlan; + if (port >= RTL8367_NUM_PORTS) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(port / 8), 0, + RTL8367_MIB_CTRL_PORT_RESET_MASK(port % 8)); +} + +static struct switch_attr rtl8367_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = rtl8366_sw_set_vlan_enable, + .get = rtl8366_sw_get_vlan_enable, + .max = 1, + .ofs = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan4k", + .description = "Enable VLAN 4K mode", + .set = rtl8366_sw_set_vlan_enable, + .get = rtl8366_sw_get_vlan_enable, + .max = 1, + .ofs = 2 + }, { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mibs", + .description = "Reset all MIB counters", + .set = rtl8367_sw_reset_mibs, + }, { + .type = SWITCH_TYPE_INT, + .name = "max_length", + .description = "Get/Set the maximum length of valid packets" + "(0:1522, 1:1536, 2:1552, 3:16000)", + .set = rtl8367_sw_set_max_length, + .get = rtl8367_sw_get_max_length, + .max = 3, + } +}; + +static struct switch_attr rtl8367_port[] = { + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mib", + .description = "Reset single port MIB counters", + .set = rtl8367_sw_reset_port_mibs, + }, { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get MIB counters for port", + .max = 33, + .set = NULL, + .get = rtl8366_sw_get_port_mib, + }, +}; + +static struct switch_attr rtl8367_vlan[] = { + { + .type = SWITCH_TYPE_STRING, + .name = "info", + .description = "Get vlan information", + .max = 1, + .set = NULL, + .get = rtl8366_sw_get_vlan_info, + }, { + .type = SWITCH_TYPE_INT, + .name = "fid", + .description = "Get/Set vlan FID", + .max = RTL8367_FIDMAX, + .set = rtl8366_sw_set_vlan_fid, + .get = rtl8366_sw_get_vlan_fid, + }, +}; + +static const struct switch_dev_ops rtl8367_sw_ops = { + .attr_global = { + .attr = rtl8367_globals, + .n_attr = ARRAY_SIZE(rtl8367_globals), + }, + .attr_port = { + .attr = rtl8367_port, + .n_attr = ARRAY_SIZE(rtl8367_port), + }, + .attr_vlan = { + .attr = rtl8367_vlan, + .n_attr = ARRAY_SIZE(rtl8367_vlan), + }, + + .get_vlan_ports = rtl8366_sw_get_vlan_ports, + .set_vlan_ports = rtl8366_sw_set_vlan_ports, + .get_port_pvid = rtl8366_sw_get_port_pvid, + .set_port_pvid = rtl8366_sw_set_port_pvid, + .reset_switch = rtl8366_sw_reset_switch, + .get_port_link = rtl8367_sw_get_port_link, +}; + +static int rtl8367_switch_init(struct rtl8366_smi *smi) +{ + struct switch_dev *dev = &smi->sw_dev; + int err; + + dev->name = "RTL8367"; + dev->cpu_port = RTL8367_CPU_PORT_NUM; + dev->ports = RTL8367_NUM_PORTS; + dev->vlans = RTL8367_NUM_VIDS; + dev->ops = &rtl8367_sw_ops; + dev->alias = dev_name(smi->parent); + + err = register_switch(dev, NULL); + if (err) + dev_err(smi->parent, "switch registration failed\n"); + + return err; +} + +static void rtl8367_switch_cleanup(struct rtl8366_smi *smi) +{ + unregister_switch(&smi->sw_dev); +} + +static int rtl8367_mii_read(struct mii_bus *bus, int addr, int reg) +{ + struct rtl8366_smi *smi = bus->priv; + u32 val = 0; + int err; + + err = rtl8367_read_phy_reg(smi, addr, reg, &val); + if (err) + return 0xffff; + + return val; +} + +static int rtl8367_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) +{ + struct rtl8366_smi *smi = bus->priv; + u32 t; + int err; + + err = rtl8367_write_phy_reg(smi, addr, reg, val); + if (err) + return err; + + /* flush write */ + (void) rtl8367_read_phy_reg(smi, addr, reg, &t); + + return err; +} + +static int rtl8367_detect(struct rtl8366_smi *smi) +{ + u32 rtl_no = 0; + u32 rtl_ver = 0; + char *chip_name; + int ret; + + ret = rtl8366_smi_read_reg(smi, RTL8367_RTL_NO_REG, &rtl_no); + if (ret) { + dev_err(smi->parent, "unable to read chip number\n"); + return ret; + } + + switch (rtl_no) { + case RTL8367_RTL_NO_8367R: + chip_name = "8367R"; + break; + case RTL8367_RTL_NO_8367M: + chip_name = "8367M"; + break; + default: + dev_err(smi->parent, "unknown chip number (%04x)\n", rtl_no); + return -ENODEV; + } + + ret = rtl8366_smi_read_reg(smi, RTL8367_RTL_VER_REG, &rtl_ver); + if (ret) { + dev_err(smi->parent, "unable to read chip version\n"); + return ret; + } + + dev_info(smi->parent, "RTL%s ver. %u chip found\n", + chip_name, rtl_ver & RTL8367_RTL_VER_MASK); + + return 0; +} + +static struct rtl8366_smi_ops rtl8367_smi_ops = { + .detect = rtl8367_detect, + .reset_chip = rtl8367_reset_chip, + .setup = rtl8367_setup, + + .mii_read = rtl8367_mii_read, + .mii_write = rtl8367_mii_write, + + .get_vlan_mc = rtl8367_get_vlan_mc, + .set_vlan_mc = rtl8367_set_vlan_mc, + .get_vlan_4k = rtl8367_get_vlan_4k, + .set_vlan_4k = rtl8367_set_vlan_4k, + .get_mc_index = rtl8367_get_mc_index, + .set_mc_index = rtl8367_set_mc_index, + .get_mib_counter = rtl8367_get_mib_counter, + .is_vlan_valid = rtl8367_is_vlan_valid, + .enable_vlan = rtl8367_enable_vlan, + .enable_vlan4k = rtl8367_enable_vlan4k, + .enable_port = rtl8367_enable_port, +}; + +static int rtl8367_probe(struct platform_device *pdev) +{ + struct rtl8366_smi *smi; + int err; + + smi = rtl8366_smi_probe(pdev); + if (!smi) + return -ENODEV; + + smi->clk_delay = 1500; + smi->cmd_read = 0xb9; + smi->cmd_write = 0xb8; + smi->ops = &rtl8367_smi_ops; + smi->cpu_port = RTL8367_CPU_PORT_NUM; + smi->num_ports = RTL8367_NUM_PORTS; + smi->num_vlan_mc = RTL8367_NUM_VLANS; + smi->mib_counters = rtl8367_mib_counters; + smi->num_mib_counters = ARRAY_SIZE(rtl8367_mib_counters); + + err = rtl8366_smi_init(smi); + if (err) + goto err_free_smi; + + platform_set_drvdata(pdev, smi); + + err = rtl8367_switch_init(smi); + if (err) + goto err_clear_drvdata; + + return 0; + + err_clear_drvdata: + platform_set_drvdata(pdev, NULL); + rtl8366_smi_cleanup(smi); + err_free_smi: + kfree(smi); + return err; +} + +static int rtl8367_remove(struct platform_device *pdev) +{ + struct rtl8366_smi *smi = platform_get_drvdata(pdev); + + if (smi) { + rtl8367_switch_cleanup(smi); + platform_set_drvdata(pdev, NULL); + rtl8366_smi_cleanup(smi); + kfree(smi); + } + + return 0; +} + +static void rtl8367_shutdown(struct platform_device *pdev) +{ + struct rtl8366_smi *smi = platform_get_drvdata(pdev); + + if (smi) + rtl8367_reset_chip(smi); +} + +#ifdef CONFIG_OF +static const struct of_device_id rtl8367_match[] = { + { .compatible = "realtek,rtl8367" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rtl8367_match); +#endif + +static struct platform_driver rtl8367_driver = { + .driver = { + .name = RTL8367_DRIVER_NAME, + .owner = THIS_MODULE, +#ifdef CONFIG_OF + .of_match_table = of_match_ptr(rtl8367_match), +#endif + }, + .probe = rtl8367_probe, + .remove = rtl8367_remove, + .shutdown = rtl8367_shutdown, +}; + +static int __init rtl8367_module_init(void) +{ + return platform_driver_register(&rtl8367_driver); +} +module_init(rtl8367_module_init); + +static void __exit rtl8367_module_exit(void) +{ + platform_driver_unregister(&rtl8367_driver); +} +module_exit(rtl8367_module_exit); + +MODULE_DESCRIPTION(RTL8367_DRIVER_DESC); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" RTL8367_DRIVER_NAME); diff --git a/target/linux/generic/files/drivers/net/phy/rtl8367b.c b/target/linux/generic/files/drivers/net/phy/rtl8367b.c new file mode 100644 index 0000000..a82f696 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c @@ -0,0 +1,1602 @@ +/* + * Platform driver for the Realtek RTL8367R-VB ethernet switches + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rtl8366_smi.h" + +#define RTL8367B_RESET_DELAY 1000 /* msecs*/ + +#define RTL8367B_PHY_ADDR_MAX 8 +#define RTL8367B_PHY_REG_MAX 31 + +#define RTL8367B_VID_MASK 0x3fff +#define RTL8367B_FID_MASK 0xf +#define RTL8367B_UNTAG_MASK 0xff +#define RTL8367B_MEMBER_MASK 0xff + +#define RTL8367B_PORT_MISC_CFG_REG(_p) (0x000e + 0x20 * (_p)) +#define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT 4 +#define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK 0x3 +#define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL 0 +#define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP 1 +#define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI 2 +#define RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL 3 + +#define RTL8367B_BYPASS_LINE_RATE_REG 0x03f7 + +#define RTL8367B_TA_CTRL_REG 0x0500 /*GOOD*/ +#define RTL8367B_TA_CTRL_SPA_SHIFT 8 +#define RTL8367B_TA_CTRL_SPA_MASK 0x7 +#define RTL8367B_TA_CTRL_METHOD BIT(4)/*GOOD*/ +#define RTL8367B_TA_CTRL_CMD_SHIFT 3 +#define RTL8367B_TA_CTRL_CMD_READ 0 +#define RTL8367B_TA_CTRL_CMD_WRITE 1 +#define RTL8367B_TA_CTRL_TABLE_SHIFT 0 /*GOOD*/ +#define RTL8367B_TA_CTRL_TABLE_ACLRULE 1 +#define RTL8367B_TA_CTRL_TABLE_ACLACT 2 +#define RTL8367B_TA_CTRL_TABLE_CVLAN 3 +#define RTL8367B_TA_CTRL_TABLE_L2 4 +#define RTL8367B_TA_CTRL_CVLAN_READ \ + ((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \ + RTL8367B_TA_CTRL_TABLE_CVLAN) +#define RTL8367B_TA_CTRL_CVLAN_WRITE \ + ((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \ + RTL8367B_TA_CTRL_TABLE_CVLAN) + +#define RTL8367B_TA_ADDR_REG 0x0501/*GOOD*/ +#define RTL8367B_TA_ADDR_MASK 0x3fff/*GOOD*/ + +#define RTL8367B_TA_LUT_REG 0x0502/*GOOD*/ + +#define RTL8367B_TA_WRDATA_REG(_x) (0x0510 + (_x))/*GOOD*/ +#define RTL8367B_TA_VLAN_NUM_WORDS 2 +#define RTL8367B_TA_VLAN_VID_MASK RTL8367B_VID_MASK +#define RTL8367B_TA_VLAN0_MEMBER_SHIFT 0 +#define RTL8367B_TA_VLAN0_MEMBER_MASK RTL8367B_MEMBER_MASK +#define RTL8367B_TA_VLAN0_UNTAG_SHIFT 8 +#define RTL8367B_TA_VLAN0_UNTAG_MASK RTL8367B_MEMBER_MASK +#define RTL8367B_TA_VLAN1_FID_SHIFT 0 +#define RTL8367B_TA_VLAN1_FID_MASK RTL8367B_FID_MASK + +#define RTL8367B_TA_RDDATA_REG(_x) (0x0520 + (_x))/*GOOD*/ + +#define RTL8367B_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2) /*GOOD*/ +#define RTL8367B_VLAN_PVID_CTRL_MASK 0x1f /*GOOD*/ +#define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2)) /*GOOD*/ + +#define RTL8367B_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4) /*GOOD*/ +#define RTL8367B_VLAN_MC_NUM_WORDS 4 /*GOOD*/ +#define RTL8367B_VLAN_MC0_MEMBER_SHIFT 0/*GOOD*/ +#define RTL8367B_VLAN_MC0_MEMBER_MASK RTL8367B_MEMBER_MASK/*GOOD*/ +#define RTL8367B_VLAN_MC1_FID_SHIFT 0/*GOOD*/ +#define RTL8367B_VLAN_MC1_FID_MASK RTL8367B_FID_MASK/*GOOD*/ +#define RTL8367B_VLAN_MC3_EVID_SHIFT 0/*GOOD*/ +#define RTL8367B_VLAN_MC3_EVID_MASK RTL8367B_VID_MASK/*GOOD*/ + +#define RTL8367B_VLAN_CTRL_REG 0x07a8 /*GOOD*/ +#define RTL8367B_VLAN_CTRL_ENABLE BIT(0) + +#define RTL8367B_VLAN_INGRESS_REG 0x07a9 /*GOOD*/ + +#define RTL8367B_PORT_ISOLATION_REG(_p) (0x08a2 + (_p)) /*GOOD*/ + +#define RTL8367B_MIB_COUNTER_REG(_x) (0x1000 + (_x)) /*GOOD*/ +#define RTL8367B_MIB_COUNTER_PORT_OFFSET 0x007c /*GOOD*/ + +#define RTL8367B_MIB_ADDRESS_REG 0x1004 /*GOOD*/ + +#define RTL8367B_MIB_CTRL0_REG(_x) (0x1005 + (_x)) /*GOOD*/ +#define RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK BIT(11) /*GOOD*/ +#define RTL8367B_MIB_CTRL0_QM_RESET_MASK BIT(10) /*GOOD*/ +#define RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/ +#define RTL8367B_MIB_CTRL0_RESET_MASK BIT(1) /*GOOD*/ +#define RTL8367B_MIB_CTRL0_BUSY_MASK BIT(0) /*GOOD*/ + +#define RTL8367B_SWC0_REG 0x1200/*GOOD*/ +#define RTL8367B_SWC0_MAX_LENGTH_SHIFT 13/*GOOD*/ +#define RTL8367B_SWC0_MAX_LENGTH(_x) ((_x) << 13) /*GOOD*/ +#define RTL8367B_SWC0_MAX_LENGTH_MASK RTL8367B_SWC0_MAX_LENGTH(0x3) +#define RTL8367B_SWC0_MAX_LENGTH_1522 RTL8367B_SWC0_MAX_LENGTH(0) +#define RTL8367B_SWC0_MAX_LENGTH_1536 RTL8367B_SWC0_MAX_LENGTH(1) +#define RTL8367B_SWC0_MAX_LENGTH_1552 RTL8367B_SWC0_MAX_LENGTH(2) +#define RTL8367B_SWC0_MAX_LENGTH_16000 RTL8367B_SWC0_MAX_LENGTH(3) + +#define RTL8367B_CHIP_NUMBER_REG 0x1300/*GOOD*/ + +#define RTL8367B_CHIP_VER_REG 0x1301/*GOOD*/ +#define RTL8367B_CHIP_VER_RLVID_SHIFT 12/*GOOD*/ +#define RTL8367B_CHIP_VER_RLVID_MASK 0xf/*GOOD*/ +#define RTL8367B_CHIP_VER_MCID_SHIFT 8/*GOOD*/ +#define RTL8367B_CHIP_VER_MCID_MASK 0xf/*GOOD*/ +#define RTL8367B_CHIP_VER_BOID_SHIFT 4/*GOOD*/ +#define RTL8367B_CHIP_VER_BOID_MASK 0xf/*GOOD*/ +#define RTL8367B_CHIP_VER_AFE_SHIFT 0/*GOOD*/ +#define RTL8367B_CHIP_VER_AFE_MASK 0x1/*GOOD*/ + +#define RTL8367B_CHIP_MODE_REG 0x1302 +#define RTL8367B_CHIP_MODE_MASK 0x7 + +#define RTL8367B_CHIP_DEBUG0_REG 0x1303 +#define RTL8367B_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x)) + +#define RTL8367B_CHIP_DEBUG1_REG 0x1304 + +#define RTL8367B_DIS_REG 0x1305 +#define RTL8367B_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x)) +#define RTL8367B_DIS_RGMII_SHIFT(_x) (4 * (_x)) +#define RTL8367B_DIS_RGMII_MASK 0x7 + +#define RTL8367B_EXT_RGMXF_REG(_x) (0x1306 + (_x)) +#define RTL8367B_EXT_RGMXF_DUMMY0_SHIFT 5 +#define RTL8367B_EXT_RGMXF_DUMMY0_MASK 0x7ff +#define RTL8367B_EXT_RGMXF_TXDELAY_SHIFT 3 +#define RTL8367B_EXT_RGMXF_TXDELAY_MASK 1 +#define RTL8367B_EXT_RGMXF_RXDELAY_MASK 0x7 + +#define RTL8367B_DI_FORCE_REG(_x) (0x1310 + (_x)) +#define RTL8367B_DI_FORCE_MODE BIT(12) +#define RTL8367B_DI_FORCE_NWAY BIT(7) +#define RTL8367B_DI_FORCE_TXPAUSE BIT(6) +#define RTL8367B_DI_FORCE_RXPAUSE BIT(5) +#define RTL8367B_DI_FORCE_LINK BIT(4) +#define RTL8367B_DI_FORCE_DUPLEX BIT(2) +#define RTL8367B_DI_FORCE_SPEED_MASK 3 +#define RTL8367B_DI_FORCE_SPEED_10 0 +#define RTL8367B_DI_FORCE_SPEED_100 1 +#define RTL8367B_DI_FORCE_SPEED_1000 2 + +#define RTL8367B_MAC_FORCE_REG(_x) (0x1312 + (_x)) + +#define RTL8367B_CHIP_RESET_REG 0x1322 /*GOOD*/ +#define RTL8367B_CHIP_RESET_SW BIT(1) /*GOOD*/ +#define RTL8367B_CHIP_RESET_HW BIT(0) /*GOOD*/ + +#define RTL8367B_PORT_STATUS_REG(_p) (0x1352 + (_p)) /*GOOD*/ +#define RTL8367B_PORT_STATUS_EN_1000_SPI BIT(11) /*GOOD*/ +#define RTL8367B_PORT_STATUS_EN_100_SPI BIT(10)/*GOOD*/ +#define RTL8367B_PORT_STATUS_NWAY_FAULT BIT(9)/*GOOD*/ +#define RTL8367B_PORT_STATUS_LINK_MASTER BIT(8)/*GOOD*/ +#define RTL8367B_PORT_STATUS_NWAY BIT(7)/*GOOD*/ +#define RTL8367B_PORT_STATUS_TXPAUSE BIT(6)/*GOOD*/ +#define RTL8367B_PORT_STATUS_RXPAUSE BIT(5)/*GOOD*/ +#define RTL8367B_PORT_STATUS_LINK BIT(4)/*GOOD*/ +#define RTL8367B_PORT_STATUS_DUPLEX BIT(2)/*GOOD*/ +#define RTL8367B_PORT_STATUS_SPEED_MASK 0x0003/*GOOD*/ +#define RTL8367B_PORT_STATUS_SPEED_10 0/*GOOD*/ +#define RTL8367B_PORT_STATUS_SPEED_100 1/*GOOD*/ +#define RTL8367B_PORT_STATUS_SPEED_1000 2/*GOOD*/ + +#define RTL8367B_RTL_MAGIC_ID_REG 0x13c2 +#define RTL8367B_RTL_MAGIC_ID_VAL 0x0249 + +#define RTL8367B_IA_CTRL_REG 0x1f00 +#define RTL8367B_IA_CTRL_RW(_x) ((_x) << 1) +#define RTL8367B_IA_CTRL_RW_READ RTL8367B_IA_CTRL_RW(0) +#define RTL8367B_IA_CTRL_RW_WRITE RTL8367B_IA_CTRL_RW(1) +#define RTL8367B_IA_CTRL_CMD_MASK BIT(0) + +#define RTL8367B_IA_STATUS_REG 0x1f01 +#define RTL8367B_IA_STATUS_PHY_BUSY BIT(2) +#define RTL8367B_IA_STATUS_SDS_BUSY BIT(1) +#define RTL8367B_IA_STATUS_MDX_BUSY BIT(0) + +#define RTL8367B_IA_ADDRESS_REG 0x1f02 +#define RTL8367B_IA_WRITE_DATA_REG 0x1f03 +#define RTL8367B_IA_READ_DATA_REG 0x1f04 + +#define RTL8367B_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r)) + +#define RTL8367B_NUM_MIB_COUNTERS 58 + +#define RTL8367B_CPU_PORT_NUM 5 +#define RTL8367B_NUM_PORTS 8 +#define RTL8367B_NUM_VLANS 32 +#define RTL8367B_NUM_VIDS 4096 +#define RTL8367B_PRIORITYMAX 7 +#define RTL8367B_FIDMAX 7 + +#define RTL8367B_PORT_0 BIT(0) +#define RTL8367B_PORT_1 BIT(1) +#define RTL8367B_PORT_2 BIT(2) +#define RTL8367B_PORT_3 BIT(3) +#define RTL8367B_PORT_4 BIT(4) +#define RTL8367B_PORT_E0 BIT(5) /* External port 0 */ +#define RTL8367B_PORT_E1 BIT(6) /* External port 1 */ +#define RTL8367B_PORT_E2 BIT(7) /* External port 2 */ + +#define RTL8367B_PORTS_ALL \ + (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \ + RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \ + RTL8367B_PORT_E1 | RTL8367B_PORT_E2) + +#define RTL8367B_PORTS_ALL_BUT_CPU \ + (RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 | \ + RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 | \ + RTL8367B_PORT_E2) + +struct rtl8367b_initval { + u16 reg; + u16 val; +}; + +static struct rtl8366_mib_counter +rtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = { + {0, 0, 4, "ifInOctets" }, + {0, 4, 2, "dot3StatsFCSErrors" }, + {0, 6, 2, "dot3StatsSymbolErrors" }, + {0, 8, 2, "dot3InPauseFrames" }, + {0, 10, 2, "dot3ControlInUnknownOpcodes" }, + {0, 12, 2, "etherStatsFragments" }, + {0, 14, 2, "etherStatsJabbers" }, + {0, 16, 2, "ifInUcastPkts" }, + {0, 18, 2, "etherStatsDropEvents" }, + {0, 20, 2, "ifInMulticastPkts" }, + {0, 22, 2, "ifInBroadcastPkts" }, + {0, 24, 2, "inMldChecksumError" }, + {0, 26, 2, "inIgmpChecksumError" }, + {0, 28, 2, "inMldSpecificQuery" }, + {0, 30, 2, "inMldGeneralQuery" }, + {0, 32, 2, "inIgmpSpecificQuery" }, + {0, 34, 2, "inIgmpGeneralQuery" }, + {0, 36, 2, "inMldLeaves" }, + {0, 38, 2, "inIgmpLeaves" }, + + {0, 40, 4, "etherStatsOctets" }, + {0, 44, 2, "etherStatsUnderSizePkts" }, + {0, 46, 2, "etherOversizeStats" }, + {0, 48, 2, "etherStatsPkts64Octets" }, + {0, 50, 2, "etherStatsPkts65to127Octets" }, + {0, 52, 2, "etherStatsPkts128to255Octets" }, + {0, 54, 2, "etherStatsPkts256to511Octets" }, + {0, 56, 2, "etherStatsPkts512to1023Octets" }, + {0, 58, 2, "etherStatsPkts1024to1518Octets" }, + + {0, 60, 4, "ifOutOctets" }, + {0, 64, 2, "dot3StatsSingleCollisionFrames" }, + {0, 66, 2, "dot3StatMultipleCollisionFrames" }, + {0, 68, 2, "dot3sDeferredTransmissions" }, + {0, 70, 2, "dot3StatsLateCollisions" }, + {0, 72, 2, "etherStatsCollisions" }, + {0, 74, 2, "dot3StatsExcessiveCollisions" }, + {0, 76, 2, "dot3OutPauseFrames" }, + {0, 78, 2, "ifOutDiscards" }, + {0, 80, 2, "dot1dTpPortInDiscards" }, + {0, 82, 2, "ifOutUcastPkts" }, + {0, 84, 2, "ifOutMulticastPkts" }, + {0, 86, 2, "ifOutBroadcastPkts" }, + {0, 88, 2, "outOampduPkts" }, + {0, 90, 2, "inOampduPkts" }, + {0, 92, 2, "inIgmpJoinsSuccess" }, + {0, 94, 2, "inIgmpJoinsFail" }, + {0, 96, 2, "inMldJoinsSuccess" }, + {0, 98, 2, "inMldJoinsFail" }, + {0, 100, 2, "inReportSuppressionDrop" }, + {0, 102, 2, "inLeaveSuppressionDrop" }, + {0, 104, 2, "outIgmpReports" }, + {0, 106, 2, "outIgmpLeaves" }, + {0, 108, 2, "outIgmpGeneralQuery" }, + {0, 110, 2, "outIgmpSpecificQuery" }, + {0, 112, 2, "outMldReports" }, + {0, 114, 2, "outMldLeaves" }, + {0, 116, 2, "outMldGeneralQuery" }, + {0, 118, 2, "outMldSpecificQuery" }, + {0, 120, 2, "inKnownMulticastPkts" }, +}; + +#define REG_RD(_smi, _reg, _val) \ + do { \ + err = rtl8366_smi_read_reg(_smi, _reg, _val); \ + if (err) \ + return err; \ + } while (0) + +#define REG_WR(_smi, _reg, _val) \ + do { \ + err = rtl8366_smi_write_reg(_smi, _reg, _val); \ + if (err) \ + return err; \ + } while (0) + +#define REG_RMW(_smi, _reg, _mask, _val) \ + do { \ + err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \ + if (err) \ + return err; \ + } while (0) + +static const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = { + {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14}, + {0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002}, + {0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000}, + {0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000}, + {0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000}, + {0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013}, + {0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, + {0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02}, + {0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115}, + {0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, + {0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007}, + {0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044}, + {0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1}, + {0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026}, + {0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010}, + {0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000}, + {0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E}, + {0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00}, + {0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01}, + {0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02}, + {0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03}, + {0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04}, + {0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05}, + {0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06}, + {0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00}, + {0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000}, + {0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015}, + {0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340}, + {0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E}, + {0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000}, + {0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E}, + {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E}, + {0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280}, + {0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080}, + {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201}, + {0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1}, + {0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E}, + {0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0}, + {0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0}, + {0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0}, + {0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0}, + {0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0}, + {0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0}, + {0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0}, + {0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2}, + {0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4}, + {0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4}, + {0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA}, + {0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA}, + {0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85}, + {0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B}, + {0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A}, + {0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A}, + {0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B}, + {0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF}, + {0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8}, + {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620}, + {0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225}, + {0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302}, + {0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1}, + {0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282}, + {0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6}, + {0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0}, + {0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4}, + {0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305}, + {0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E}, + {0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E}, + {0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25}, + {0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B}, + {0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B}, + {0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0}, + {0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4}, + {0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C}, + {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23}, + {0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359}, + {0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC}, + {0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29}, + {0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1}, + {0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85}, + {0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29}, + {0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE}, + {0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0}, + {0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, + {0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0}, + {0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84}, + {0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72}, + {0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC}, + {0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85}, + {0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, + {0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1}, + {0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B}, + {0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7}, + {0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC}, + {0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602}, + {0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02}, + {0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602}, + {0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE}, + {0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD}, + {0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15}, + {0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14}, + {0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14}, + {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14}, + {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9}, + {0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22}, + {0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC}, + {0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15}, + {0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15}, + {0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F}, + {0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13}, + {0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15}, + {0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15}, + {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87}, + {0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0}, + {0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0}, + {0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4}, + {0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12}, + {0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12}, + {0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14}, + {0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14}, + {0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA}, + {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146}, + {0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0}, + {0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F}, + {0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21}, + {0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF}, + {0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5}, + {0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10}, + {0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459}, + {0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F}, + {0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96}, + {0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF}, + {0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0}, + {0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F}, + {0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159}, + {0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C}, + {0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302}, + {0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34}, + {0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0}, + {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D}, + {0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A}, + {0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34}, + {0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34}, + {0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0}, + {0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D}, + {0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF}, + {0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498}, + {0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03}, + {0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207}, + {0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD}, + {0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31}, + {0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31}, + {0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284}, + {0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE}, + {0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02}, + {0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4}, + {0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0}, + {0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1}, + {0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1}, + {0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, + {0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE}, + {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A}, + {0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, + {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0}, + {0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A}, + {0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1}, + {0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2}, + {0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C}, + {0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02}, + {0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA}, + {0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11}, + {0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04}, + {0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE}, + {0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE}, + {0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE}, + {0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34}, + {0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11}, + {0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, + {0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2}, + {0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, + {0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85}, + {0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0}, + {0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20}, + {0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21}, + {0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE}, + {0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284}, + {0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8}, + {0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402}, + {0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285}, + {0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B}, + {0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85}, + {0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D}, + {0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B}, + {0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8}, + {0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1}, + {0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5}, + {0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021}, + {0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000}, + {0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA}, + {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212}, + {0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26}, + {0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02}, + {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8}, + {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22}, + {0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02}, + {0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464}, + {0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480}, + {0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142}, + {0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000}, + {0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010}, + {0x13EB, 0x11BB} +}; + +static const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = { + {0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA}, + {0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078}, + {0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00}, + {0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000}, + {0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000}, + {0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000}, + {0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030}, + {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E}, + {0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B}, + {0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00}, + {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E}, + {0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100}, + {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280}, + {0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080}, + {0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201}, + {0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0}, + {0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1}, + {0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE}, + {0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1}, + {0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD}, + {0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7}, + {0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20}, + {0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9}, + {0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A}, + {0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E}, + {0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5}, + {0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2}, + {0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC}, + {0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE}, + {0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, + {0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685}, + {0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85}, + {0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC}, + {0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140}, + {0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E}, + {0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22}, + {0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340}, + {0x133E, 0x000E}, {0x133F, 0x0010}, +}; + +static int rtl8367b_write_initvals(struct rtl8366_smi *smi, + const struct rtl8367b_initval *initvals, + int count) +{ + int err; + int i; + + for (i = 0; i < count; i++) + REG_WR(smi, initvals[i].reg, initvals[i].val); + + return 0; +} + +static int rtl8367b_read_phy_reg(struct rtl8366_smi *smi, + u32 phy_addr, u32 phy_reg, u32 *val) +{ + int timeout; + u32 data; + int err; + + if (phy_addr > RTL8367B_PHY_ADDR_MAX) + return -EINVAL; + + if (phy_reg > RTL8367B_PHY_REG_MAX) + return -EINVAL; + + REG_RD(smi, RTL8367B_IA_STATUS_REG, &data); + if (data & RTL8367B_IA_STATUS_PHY_BUSY) + return -ETIMEDOUT; + + /* prepare address */ + REG_WR(smi, RTL8367B_IA_ADDRESS_REG, + RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg)); + + /* send read command */ + REG_WR(smi, RTL8367B_IA_CTRL_REG, + RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ); + + timeout = 5; + do { + REG_RD(smi, RTL8367B_IA_STATUS_REG, &data); + if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0) + break; + + if (timeout--) { + dev_err(smi->parent, "phy read timed out\n"); + return -ETIMEDOUT; + } + + udelay(1); + } while (1); + + /* read data */ + REG_RD(smi, RTL8367B_IA_READ_DATA_REG, val); + + dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n", + phy_addr, phy_reg, *val); + return 0; +} + +static int rtl8367b_write_phy_reg(struct rtl8366_smi *smi, + u32 phy_addr, u32 phy_reg, u32 val) +{ + int timeout; + u32 data; + int err; + + dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n", + phy_addr, phy_reg, val); + + if (phy_addr > RTL8367B_PHY_ADDR_MAX) + return -EINVAL; + + if (phy_reg > RTL8367B_PHY_REG_MAX) + return -EINVAL; + + REG_RD(smi, RTL8367B_IA_STATUS_REG, &data); + if (data & RTL8367B_IA_STATUS_PHY_BUSY) + return -ETIMEDOUT; + + /* preapre data */ + REG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val); + + /* prepare address */ + REG_WR(smi, RTL8367B_IA_ADDRESS_REG, + RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg)); + + /* send write command */ + REG_WR(smi, RTL8367B_IA_CTRL_REG, + RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE); + + timeout = 5; + do { + REG_RD(smi, RTL8367B_IA_STATUS_REG, &data); + if ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0) + break; + + if (timeout--) { + dev_err(smi->parent, "phy write timed out\n"); + return -ETIMEDOUT; + } + + udelay(1); + } while (1); + + return 0; +} + +static int rtl8367b_init_regs(struct rtl8366_smi *smi) +{ + const struct rtl8367b_initval *initvals; + u32 chip_ver; + u32 rlvid; + int count; + int err; + + REG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL); + REG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver); + + rlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) & + RTL8367B_CHIP_VER_RLVID_MASK; + + switch (rlvid) { + case 0: + initvals = rtl8367r_vb_initvals_0; + count = ARRAY_SIZE(rtl8367r_vb_initvals_0); + break; + + case 1: + initvals = rtl8367r_vb_initvals_1; + count = ARRAY_SIZE(rtl8367r_vb_initvals_1); + break; + + default: + dev_err(smi->parent, "unknow rlvid %u\n", rlvid); + return -ENODEV; + } + + /* TODO: disable RLTP */ + + return rtl8367b_write_initvals(smi, initvals, count); +} + +static int rtl8367b_reset_chip(struct rtl8366_smi *smi) +{ + int timeout = 10; + int err; + u32 data; + + REG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW); + msleep(RTL8367B_RESET_DELAY); + + do { + REG_RD(smi, RTL8367B_CHIP_RESET_REG, &data); + if (!(data & RTL8367B_CHIP_RESET_HW)) + break; + + msleep(1); + } while (--timeout); + + if (!timeout) { + dev_err(smi->parent, "chip reset timed out\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id, + enum rtl8367_extif_mode mode) +{ + int err; + + /* set port mode */ + switch (mode) { + case RTL8367_EXTIF_MODE_RGMII: + case RTL8367_EXTIF_MODE_RGMII_33V: + REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0367); + REG_WR(smi, RTL8367B_CHIP_DEBUG1_REG, 0x7777); + break; + + case RTL8367_EXTIF_MODE_TMII_MAC: + case RTL8367_EXTIF_MODE_TMII_PHY: + REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, + BIT((id + 1) % 2), BIT((id + 1) % 2)); + break; + + case RTL8367_EXTIF_MODE_GMII: + REG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG, + RTL8367B_CHIP_DEBUG0_DUMMY0(id), + RTL8367B_CHIP_DEBUG0_DUMMY0(id)); + REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6)); + break; + + case RTL8367_EXTIF_MODE_MII_MAC: + case RTL8367_EXTIF_MODE_MII_PHY: + case RTL8367_EXTIF_MODE_DISABLED: + REG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, + BIT((id + 1) % 2), 0); + REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0); + break; + + default: + dev_err(smi->parent, + "invalid mode for external interface %d\n", id); + return -EINVAL; + } + + REG_RMW(smi, RTL8367B_DIS_REG, + RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id), + mode << RTL8367B_DIS_RGMII_SHIFT(id)); + + return 0; +} + +static int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id, + struct rtl8367_port_ability *pa) +{ + u32 mask; + u32 val; + int err; + + mask = (RTL8367B_DI_FORCE_MODE | + RTL8367B_DI_FORCE_NWAY | + RTL8367B_DI_FORCE_TXPAUSE | + RTL8367B_DI_FORCE_RXPAUSE | + RTL8367B_DI_FORCE_LINK | + RTL8367B_DI_FORCE_DUPLEX | + RTL8367B_DI_FORCE_SPEED_MASK); + + val = pa->speed; + val |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0; + val |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0; + val |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0; + val |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0; + val |= pa->link ? RTL8367B_DI_FORCE_LINK : 0; + val |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0; + + REG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val); + + return 0; +} + +static int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id, + unsigned txdelay, unsigned rxdelay) +{ + u32 mask; + u32 val; + int err; + + mask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK | + (RTL8367B_EXT_RGMXF_TXDELAY_MASK << + RTL8367B_EXT_RGMXF_TXDELAY_SHIFT)); + + val = rxdelay; + val |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT; + + REG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val); + + return 0; +} + +static int rtl8367b_extif_init(struct rtl8366_smi *smi, int id, + struct rtl8367_extif_config *cfg) +{ + enum rtl8367_extif_mode mode; + int err; + + mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED; + + err = rtl8367b_extif_set_mode(smi, id, mode); + if (err) + return err; + + if (mode != RTL8367_EXTIF_MODE_DISABLED) { + err = rtl8367b_extif_set_force(smi, id, &cfg->ability); + if (err) + return err; + + err = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay, + cfg->rxdelay); + if (err) + return err; + } + + return 0; +} + +#ifdef CONFIG_OF +static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id, + const char *name) +{ + struct rtl8367_extif_config *cfg; + const __be32 *prop; + int size; + int err; + + prop = of_get_property(smi->parent->of_node, name, &size); + if (!prop) + return rtl8367b_extif_init(smi, id, NULL); + + if (size != (9 * sizeof(*prop))) { + dev_err(smi->parent, "%s property is invalid\n", name); + return -EINVAL; + } + + cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL); + if (!cfg) + return -ENOMEM; + + cfg->txdelay = be32_to_cpup(prop++); + cfg->rxdelay = be32_to_cpup(prop++); + cfg->mode = be32_to_cpup(prop++); + cfg->ability.force_mode = be32_to_cpup(prop++); + cfg->ability.txpause = be32_to_cpup(prop++); + cfg->ability.rxpause = be32_to_cpup(prop++); + cfg->ability.link = be32_to_cpup(prop++); + cfg->ability.duplex = be32_to_cpup(prop++); + cfg->ability.speed = be32_to_cpup(prop++); + + err = rtl8367b_extif_init(smi, id, cfg); + kfree(cfg); + + return err; +} +#else +static int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id, + const char *name) +{ + return -EINVAL; +} +#endif + +static int rtl8367b_setup(struct rtl8366_smi *smi) +{ + struct rtl8367_platform_data *pdata; + int err; + int i; + + pdata = smi->parent->platform_data; + + err = rtl8367b_init_regs(smi); + if (err) + return err; + + /* initialize external interfaces */ + if (smi->parent->of_node) { + err = rtl8367b_extif_init_of(smi, 0, "realtek,extif0"); + if (err) + return err; + + err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1"); + if (err) + return err; + } else { + err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg); + if (err) + return err; + + err = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg); + if (err) + return err; + } + + /* set maximum packet length to 1536 bytes */ + REG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK, + RTL8367B_SWC0_MAX_LENGTH_1536); + + /* + * discard VLAN tagged packets if the port is not a member of + * the VLAN with which the packets is associated. + */ + REG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL); + + /* + * Setup egress tag mode for each port. + */ + for (i = 0; i < RTL8367B_NUM_PORTS; i++) + REG_RMW(smi, + RTL8367B_PORT_MISC_CFG_REG(i), + RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK << + RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT, + RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL << + RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT); + + return 0; +} + +static int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter, + int port, unsigned long long *val) +{ + struct rtl8366_mib_counter *mib; + int offset; + int i; + int err; + u32 addr, data; + u64 mibvalue; + + if (port > RTL8367B_NUM_PORTS || + counter >= RTL8367B_NUM_MIB_COUNTERS) + return -EINVAL; + + mib = &rtl8367b_mib_counters[counter]; + addr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset; + + /* + * Writing access counter address first + * then ASIC will prepare 64bits counter wait for being retrived + */ + REG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2); + + /* read MIB control register */ + REG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data); + + if (data & RTL8367B_MIB_CTRL0_BUSY_MASK) + return -EBUSY; + + if (data & RTL8367B_MIB_CTRL0_RESET_MASK) + return -EIO; + + if (mib->length == 4) + offset = 3; + else + offset = (mib->offset + 1) % 4; + + mibvalue = 0; + for (i = 0; i < mib->length; i++) { + REG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data); + mibvalue = (mibvalue << 16) | (data & 0xFFFF); + } + + *val = mibvalue; + return 0; +} + +static int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, + struct rtl8366_vlan_4k *vlan4k) +{ + u32 data[RTL8367B_TA_VLAN_NUM_WORDS]; + int err; + int i; + + memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); + + if (vid >= RTL8367B_NUM_VIDS) + return -EINVAL; + + /* write VID */ + REG_WR(smi, RTL8367B_TA_ADDR_REG, vid); + + /* write table access control word */ + REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ); + + for (i = 0; i < ARRAY_SIZE(data); i++) + REG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]); + + vlan4k->vid = vid; + vlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) & + RTL8367B_TA_VLAN0_MEMBER_MASK; + vlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) & + RTL8367B_TA_VLAN0_UNTAG_MASK; + vlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) & + RTL8367B_TA_VLAN1_FID_MASK; + + return 0; +} + +static int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi, + const struct rtl8366_vlan_4k *vlan4k) +{ + u32 data[RTL8367B_TA_VLAN_NUM_WORDS]; + int err; + int i; + + if (vlan4k->vid >= RTL8367B_NUM_VIDS || + vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK || + vlan4k->untag > RTL8367B_UNTAG_MASK || + vlan4k->fid > RTL8367B_FIDMAX) + return -EINVAL; + + memset(data, 0, sizeof(data)); + + data[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) << + RTL8367B_TA_VLAN0_MEMBER_SHIFT; + data[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) << + RTL8367B_TA_VLAN0_UNTAG_SHIFT; + data[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) << + RTL8367B_TA_VLAN1_FID_SHIFT; + + for (i = 0; i < ARRAY_SIZE(data); i++) + REG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]); + + /* write VID */ + REG_WR(smi, RTL8367B_TA_ADDR_REG, + vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK); + + /* write table access control word */ + REG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE); + + return 0; +} + +static int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index, + struct rtl8366_vlan_mc *vlanmc) +{ + u32 data[RTL8367B_VLAN_MC_NUM_WORDS]; + int err; + int i; + + memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); + + if (index >= RTL8367B_NUM_VLANS) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(data); i++) + REG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]); + + vlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) & + RTL8367B_VLAN_MC0_MEMBER_MASK; + vlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) & + RTL8367B_VLAN_MC1_FID_MASK; + vlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) & + RTL8367B_VLAN_MC3_EVID_MASK; + + return 0; +} + +static int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index, + const struct rtl8366_vlan_mc *vlanmc) +{ + u32 data[RTL8367B_VLAN_MC_NUM_WORDS]; + int err; + int i; + + if (index >= RTL8367B_NUM_VLANS || + vlanmc->vid >= RTL8367B_NUM_VIDS || + vlanmc->priority > RTL8367B_PRIORITYMAX || + vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK || + vlanmc->untag > RTL8367B_UNTAG_MASK || + vlanmc->fid > RTL8367B_FIDMAX) + return -EINVAL; + + data[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) << + RTL8367B_VLAN_MC0_MEMBER_SHIFT; + data[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) << + RTL8367B_VLAN_MC1_FID_SHIFT; + data[2] = 0; + data[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) << + RTL8367B_VLAN_MC3_EVID_SHIFT; + + for (i = 0; i < ARRAY_SIZE(data); i++) + REG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]); + + return 0; +} + +static int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val) +{ + u32 data; + int err; + + if (port >= RTL8367B_NUM_PORTS) + return -EINVAL; + + REG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data); + + *val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) & + RTL8367B_VLAN_PVID_CTRL_MASK; + + return 0; +} + +static int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index) +{ + if (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), + RTL8367B_VLAN_PVID_CTRL_MASK << + RTL8367B_VLAN_PVID_CTRL_SHIFT(port), + (index & RTL8367B_VLAN_PVID_CTRL_MASK) << + RTL8367B_VLAN_PVID_CTRL_SHIFT(port)); +} + +static int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable) +{ + return rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG, + RTL8367B_VLAN_CTRL_ENABLE, + (enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0); +} + +static int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable) +{ + return 0; +} + +static int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan) +{ + unsigned max = RTL8367B_NUM_VLANS; + + if (smi->vlan4k_enabled) + max = RTL8367B_NUM_VIDS - 1; + + if (vlan == 0 || vlan >= max) + return 0; + + return 1; +} + +static int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable) +{ + int err; + + REG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port), + (enable) ? RTL8367B_PORTS_ALL : 0); + + return 0; +} + +static int rtl8367b_sw_reset_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + + return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0, + RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK); +} + +static int rtl8367b_sw_get_port_link(struct switch_dev *dev, + int port, + struct switch_port_link *link) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data = 0; + u32 speed; + + if (port >= RTL8367B_NUM_PORTS) + return -EINVAL; + + rtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data); + + link->link = !!(data & RTL8367B_PORT_STATUS_LINK); + if (!link->link) + return 0; + + link->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX); + link->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE); + link->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE); + link->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY); + + speed = (data & RTL8367B_PORT_STATUS_SPEED_MASK); + switch (speed) { + case 0: + link->speed = SWITCH_PORT_SPEED_10; + break; + case 1: + link->speed = SWITCH_PORT_SPEED_100; + break; + case 2: + link->speed = SWITCH_PORT_SPEED_1000; + break; + default: + link->speed = SWITCH_PORT_SPEED_UNKNOWN; + break; + } + + return 0; +} + +static int rtl8367b_sw_get_max_length(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 data; + + rtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data); + val->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >> + RTL8367B_SWC0_MAX_LENGTH_SHIFT; + + return 0; +} + +static int rtl8367b_sw_set_max_length(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + u32 max_len; + + switch (val->value.i) { + case 0: + max_len = RTL8367B_SWC0_MAX_LENGTH_1522; + break; + case 1: + max_len = RTL8367B_SWC0_MAX_LENGTH_1536; + break; + case 2: + max_len = RTL8367B_SWC0_MAX_LENGTH_1552; + break; + case 3: + max_len = RTL8367B_SWC0_MAX_LENGTH_16000; + break; + default: + return -EINVAL; + } + + return rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG, + RTL8367B_SWC0_MAX_LENGTH_MASK, max_len); +} + + +static int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev, + const struct switch_attr *attr, + struct switch_val *val) +{ + struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); + int port; + + port = val->port_vlan; + if (port >= RTL8367B_NUM_PORTS) + return -EINVAL; + + return rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0, + RTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8)); +} + +static struct switch_attr rtl8367b_globals[] = { + { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan", + .description = "Enable VLAN mode", + .set = rtl8366_sw_set_vlan_enable, + .get = rtl8366_sw_get_vlan_enable, + .max = 1, + .ofs = 1 + }, { + .type = SWITCH_TYPE_INT, + .name = "enable_vlan4k", + .description = "Enable VLAN 4K mode", + .set = rtl8366_sw_set_vlan_enable, + .get = rtl8366_sw_get_vlan_enable, + .max = 1, + .ofs = 2 + }, { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mibs", + .description = "Reset all MIB counters", + .set = rtl8367b_sw_reset_mibs, + }, { + .type = SWITCH_TYPE_INT, + .name = "max_length", + .description = "Get/Set the maximum length of valid packets" + "(0:1522, 1:1536, 2:1552, 3:16000)", + .set = rtl8367b_sw_set_max_length, + .get = rtl8367b_sw_get_max_length, + .max = 3, + } +}; + +static struct switch_attr rtl8367b_port[] = { + { + .type = SWITCH_TYPE_NOVAL, + .name = "reset_mib", + .description = "Reset single port MIB counters", + .set = rtl8367b_sw_reset_port_mibs, + }, { + .type = SWITCH_TYPE_STRING, + .name = "mib", + .description = "Get MIB counters for port", + .max = 33, + .set = NULL, + .get = rtl8366_sw_get_port_mib, + }, +}; + +static struct switch_attr rtl8367b_vlan[] = { + { + .type = SWITCH_TYPE_STRING, + .name = "info", + .description = "Get vlan information", + .max = 1, + .set = NULL, + .get = rtl8366_sw_get_vlan_info, + }, +}; + +static const struct switch_dev_ops rtl8367b_sw_ops = { + .attr_global = { + .attr = rtl8367b_globals, + .n_attr = ARRAY_SIZE(rtl8367b_globals), + }, + .attr_port = { + .attr = rtl8367b_port, + .n_attr = ARRAY_SIZE(rtl8367b_port), + }, + .attr_vlan = { + .attr = rtl8367b_vlan, + .n_attr = ARRAY_SIZE(rtl8367b_vlan), + }, + + .get_vlan_ports = rtl8366_sw_get_vlan_ports, + .set_vlan_ports = rtl8366_sw_set_vlan_ports, + .get_port_pvid = rtl8366_sw_get_port_pvid, + .set_port_pvid = rtl8366_sw_set_port_pvid, + .reset_switch = rtl8366_sw_reset_switch, + .get_port_link = rtl8367b_sw_get_port_link, +}; + +static int rtl8367b_switch_init(struct rtl8366_smi *smi) +{ + struct switch_dev *dev = &smi->sw_dev; + int err; + + dev->name = "RTL8367B"; + dev->cpu_port = RTL8367B_CPU_PORT_NUM; + dev->ports = RTL8367B_NUM_PORTS; + dev->vlans = RTL8367B_NUM_VIDS; + dev->ops = &rtl8367b_sw_ops; + dev->alias = dev_name(smi->parent); + + err = register_switch(dev, NULL); + if (err) + dev_err(smi->parent, "switch registration failed\n"); + + return err; +} + +static void rtl8367b_switch_cleanup(struct rtl8366_smi *smi) +{ + unregister_switch(&smi->sw_dev); +} + +static int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg) +{ + struct rtl8366_smi *smi = bus->priv; + u32 val = 0; + int err; + + err = rtl8367b_read_phy_reg(smi, addr, reg, &val); + if (err) + return 0xffff; + + return val; +} + +static int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) +{ + struct rtl8366_smi *smi = bus->priv; + u32 t; + int err; + + err = rtl8367b_write_phy_reg(smi, addr, reg, val); + if (err) + return err; + + /* flush write */ + (void) rtl8367b_read_phy_reg(smi, addr, reg, &t); + + return err; +} + +static int rtl8367b_detect(struct rtl8366_smi *smi) +{ + const char *chip_name; + u32 chip_num; + u32 chip_ver; + u32 chip_mode; + int ret; + + /* TODO: improve chip detection */ + rtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG, + RTL8367B_RTL_MAGIC_ID_VAL); + + ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num); + if (ret) { + dev_err(smi->parent, "unable to read %s register\n", + "chip number"); + return ret; + } + + ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver); + if (ret) { + dev_err(smi->parent, "unable to read %s register\n", + "chip version"); + return ret; + } + + ret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode); + if (ret) { + dev_err(smi->parent, "unable to read %s register\n", + "chip mode"); + return ret; + } + + switch (chip_ver) { + case 0x1000: + chip_name = "8367RB"; + break; + case 0x1010: + chip_name = "8367R-VB"; + break; + default: + dev_err(smi->parent, + "unknown chip num:%04x ver:%04x, mode:%04x\n", + chip_num, chip_ver, chip_mode); + return -ENODEV; + } + + dev_info(smi->parent, "RTL%s chip found\n", chip_name); + + return 0; +} + +static struct rtl8366_smi_ops rtl8367b_smi_ops = { + .detect = rtl8367b_detect, + .reset_chip = rtl8367b_reset_chip, + .setup = rtl8367b_setup, + + .mii_read = rtl8367b_mii_read, + .mii_write = rtl8367b_mii_write, + + .get_vlan_mc = rtl8367b_get_vlan_mc, + .set_vlan_mc = rtl8367b_set_vlan_mc, + .get_vlan_4k = rtl8367b_get_vlan_4k, + .set_vlan_4k = rtl8367b_set_vlan_4k, + .get_mc_index = rtl8367b_get_mc_index, + .set_mc_index = rtl8367b_set_mc_index, + .get_mib_counter = rtl8367b_get_mib_counter, + .is_vlan_valid = rtl8367b_is_vlan_valid, + .enable_vlan = rtl8367b_enable_vlan, + .enable_vlan4k = rtl8367b_enable_vlan4k, + .enable_port = rtl8367b_enable_port, +}; + +static int rtl8367b_probe(struct platform_device *pdev) +{ + struct rtl8366_smi *smi; + int err; + + smi = rtl8366_smi_probe(pdev); + if (!smi) + return -ENODEV; + + smi->clk_delay = 1500; + smi->cmd_read = 0xb9; + smi->cmd_write = 0xb8; + smi->ops = &rtl8367b_smi_ops; + smi->cpu_port = RTL8367B_CPU_PORT_NUM; + smi->num_ports = RTL8367B_NUM_PORTS; + smi->num_vlan_mc = RTL8367B_NUM_VLANS; + smi->mib_counters = rtl8367b_mib_counters; + smi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters); + + err = rtl8366_smi_init(smi); + if (err) + goto err_free_smi; + + platform_set_drvdata(pdev, smi); + + err = rtl8367b_switch_init(smi); + if (err) + goto err_clear_drvdata; + + return 0; + + err_clear_drvdata: + platform_set_drvdata(pdev, NULL); + rtl8366_smi_cleanup(smi); + err_free_smi: + kfree(smi); + return err; +} + +static int rtl8367b_remove(struct platform_device *pdev) +{ + struct rtl8366_smi *smi = platform_get_drvdata(pdev); + + if (smi) { + rtl8367b_switch_cleanup(smi); + platform_set_drvdata(pdev, NULL); + rtl8366_smi_cleanup(smi); + kfree(smi); + } + + return 0; +} + +static void rtl8367b_shutdown(struct platform_device *pdev) +{ + struct rtl8366_smi *smi = platform_get_drvdata(pdev); + + if (smi) + rtl8367b_reset_chip(smi); +} + +#ifdef CONFIG_OF +static const struct of_device_id rtl8367b_match[] = { + { .compatible = "realtek,rtl8367b" }, + { .compatible = "rtl8367b" }, + {}, +}; +MODULE_DEVICE_TABLE(of, rtl8367b_match); +#endif + +static struct platform_driver rtl8367b_driver = { + .driver = { + .name = RTL8367B_DRIVER_NAME, + .owner = THIS_MODULE, +#ifdef CONFIG_OF + .of_match_table = of_match_ptr(rtl8367b_match), +#endif + }, + .probe = rtl8367b_probe, + .remove = rtl8367b_remove, + .shutdown = rtl8367b_shutdown, +}; + +module_platform_driver(rtl8367b_driver); + +MODULE_DESCRIPTION(RTL8367B_DRIVER_DESC); +MODULE_AUTHOR("Gabor Juhos "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" RTL8367B_DRIVER_NAME); + diff --git a/target/linux/generic/files/drivers/net/phy/swconfig.c b/target/linux/generic/files/drivers/net/phy/swconfig.c new file mode 100644 index 0000000..6bb3be1 --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/swconfig.c @@ -0,0 +1,1153 @@ +/* + * swconfig.c: Switch configuration API + * + * Copyright (C) 2008 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SWCONFIG_DEVNAME "switch%d" + +#include "swconfig_leds.c" + +MODULE_AUTHOR("Felix Fietkau "); +MODULE_LICENSE("GPL"); + +static int swdev_id; +static struct list_head swdevs; +static DEFINE_SPINLOCK(swdevs_lock); +struct swconfig_callback; + +struct swconfig_callback { + struct sk_buff *msg; + struct genlmsghdr *hdr; + struct genl_info *info; + int cmd; + + /* callback for filling in the message data */ + int (*fill)(struct swconfig_callback *cb, void *arg); + + /* callback for closing the message before sending it */ + int (*close)(struct swconfig_callback *cb, void *arg); + + struct nlattr *nest[4]; + int args[4]; +}; + +/* defaults */ + +static int +swconfig_get_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + int ret; + if (val->port_vlan >= dev->vlans) + return -EINVAL; + + if (!dev->ops->get_vlan_ports) + return -EOPNOTSUPP; + + ret = dev->ops->get_vlan_ports(dev, val); + return ret; +} + +static int +swconfig_set_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct switch_port *ports = val->value.ports; + const struct switch_dev_ops *ops = dev->ops; + int i; + + if (val->port_vlan >= dev->vlans) + return -EINVAL; + + /* validate ports */ + if (val->len > dev->ports) + return -EINVAL; + + if (!ops->set_vlan_ports) + return -EOPNOTSUPP; + + for (i = 0; i < val->len; i++) { + if (ports[i].id >= dev->ports) + return -EINVAL; + + if (ops->set_port_pvid && + !(ports[i].flags & (1 << SWITCH_PORT_FLAG_TAGGED))) + ops->set_port_pvid(dev, ports[i].id, val->port_vlan); + } + + return ops->set_vlan_ports(dev, val); +} + +static int +swconfig_set_pvid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + if (val->port_vlan >= dev->ports) + return -EINVAL; + + if (!dev->ops->set_port_pvid) + return -EOPNOTSUPP; + + return dev->ops->set_port_pvid(dev, val->port_vlan, val->value.i); +} + +static int +swconfig_get_pvid(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + if (val->port_vlan >= dev->ports) + return -EINVAL; + + if (!dev->ops->get_port_pvid) + return -EOPNOTSUPP; + + return dev->ops->get_port_pvid(dev, val->port_vlan, &val->value.i); +} + +static const char * +swconfig_speed_str(enum switch_port_speed speed) +{ + switch (speed) { + case SWITCH_PORT_SPEED_10: + return "10baseT"; + case SWITCH_PORT_SPEED_100: + return "100baseT"; + case SWITCH_PORT_SPEED_1000: + return "1000baseT"; + default: + break; + } + + return "unknown"; +} + +static int +swconfig_get_link(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + struct switch_port_link link; + int len; + int ret; + + if (val->port_vlan >= dev->ports) + return -EINVAL; + + if (!dev->ops->get_port_link) + return -EOPNOTSUPP; + + memset(&link, 0, sizeof(link)); + ret = dev->ops->get_port_link(dev, val->port_vlan, &link); + if (ret) + return ret; + + memset(dev->buf, 0, sizeof(dev->buf)); + + if (link.link) + len = snprintf(dev->buf, sizeof(dev->buf), + "port:%d link:up speed:%s %s-duplex %s%s%s%s%s", + val->port_vlan, + swconfig_speed_str(link.speed), + link.duplex ? "full" : "half", + link.tx_flow ? "txflow " : "", + link.rx_flow ? "rxflow " : "", + link.eee & ADVERTISED_100baseT_Full ? "eee100 " : "", + link.eee & ADVERTISED_1000baseT_Full ? "eee1000 " : "", + link.aneg ? "auto" : ""); + else + len = snprintf(dev->buf, sizeof(dev->buf), "port:%d link:down", + val->port_vlan); + + val->value.s = dev->buf; + val->len = len; + + return 0; +} + +static int +swconfig_apply_config(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + /* don't complain if not supported by the switch driver */ + if (!dev->ops->apply_config) + return 0; + + return dev->ops->apply_config(dev); +} + +static int +swconfig_reset_switch(struct switch_dev *dev, const struct switch_attr *attr, + struct switch_val *val) +{ + /* don't complain if not supported by the switch driver */ + if (!dev->ops->reset_switch) + return 0; + + return dev->ops->reset_switch(dev); +} + +enum global_defaults { + GLOBAL_APPLY, + GLOBAL_RESET, +}; + +enum vlan_defaults { + VLAN_PORTS, +}; + +enum port_defaults { + PORT_PVID, + PORT_LINK, +}; + +static struct switch_attr default_global[] = { + [GLOBAL_APPLY] = { + .type = SWITCH_TYPE_NOVAL, + .name = "apply", + .description = "Activate changes in the hardware", + .set = swconfig_apply_config, + }, + [GLOBAL_RESET] = { + .type = SWITCH_TYPE_NOVAL, + .name = "reset", + .description = "Reset the switch", + .set = swconfig_reset_switch, + } +}; + +static struct switch_attr default_port[] = { + [PORT_PVID] = { + .type = SWITCH_TYPE_INT, + .name = "pvid", + .description = "Primary VLAN ID", + .set = swconfig_set_pvid, + .get = swconfig_get_pvid, + }, + [PORT_LINK] = { + .type = SWITCH_TYPE_STRING, + .name = "link", + .description = "Get port link information", + .set = NULL, + .get = swconfig_get_link, + } +}; + +static struct switch_attr default_vlan[] = { + [VLAN_PORTS] = { + .type = SWITCH_TYPE_PORTS, + .name = "ports", + .description = "VLAN port mapping", + .set = swconfig_set_vlan_ports, + .get = swconfig_get_vlan_ports, + }, +}; + +static const struct switch_attr * +swconfig_find_attr_by_name(const struct switch_attrlist *alist, + const char *name) +{ + int i; + + for (i = 0; i < alist->n_attr; i++) + if (strcmp(name, alist->attr[i].name) == 0) + return &alist->attr[i]; + + return NULL; +} + +static void swconfig_defaults_init(struct switch_dev *dev) +{ + const struct switch_dev_ops *ops = dev->ops; + + dev->def_global = 0; + dev->def_vlan = 0; + dev->def_port = 0; + + if (ops->get_vlan_ports || ops->set_vlan_ports) + set_bit(VLAN_PORTS, &dev->def_vlan); + + if (ops->get_port_pvid || ops->set_port_pvid) + set_bit(PORT_PVID, &dev->def_port); + + if (ops->get_port_link && + !swconfig_find_attr_by_name(&ops->attr_port, "link")) + set_bit(PORT_LINK, &dev->def_port); + + /* always present, can be no-op */ + set_bit(GLOBAL_APPLY, &dev->def_global); + set_bit(GLOBAL_RESET, &dev->def_global); +} + + +static struct genl_family switch_fam = { + .id = GENL_ID_GENERATE, + .name = "switch", + .hdrsize = 0, + .version = 1, + .maxattr = SWITCH_ATTR_MAX, +}; + +static const struct nla_policy switch_policy[SWITCH_ATTR_MAX+1] = { + [SWITCH_ATTR_ID] = { .type = NLA_U32 }, + [SWITCH_ATTR_OP_ID] = { .type = NLA_U32 }, + [SWITCH_ATTR_OP_PORT] = { .type = NLA_U32 }, + [SWITCH_ATTR_OP_VLAN] = { .type = NLA_U32 }, + [SWITCH_ATTR_OP_VALUE_INT] = { .type = NLA_U32 }, + [SWITCH_ATTR_OP_VALUE_STR] = { .type = NLA_NUL_STRING }, + [SWITCH_ATTR_OP_VALUE_PORTS] = { .type = NLA_NESTED }, + [SWITCH_ATTR_TYPE] = { .type = NLA_U32 }, +}; + +static const struct nla_policy port_policy[SWITCH_PORT_ATTR_MAX+1] = { + [SWITCH_PORT_ID] = { .type = NLA_U32 }, + [SWITCH_PORT_FLAG_TAGGED] = { .type = NLA_FLAG }, +}; + +static inline void +swconfig_lock(void) +{ + spin_lock(&swdevs_lock); +} + +static inline void +swconfig_unlock(void) +{ + spin_unlock(&swdevs_lock); +} + +static struct switch_dev * +swconfig_get_dev(struct genl_info *info) +{ + struct switch_dev *dev = NULL; + struct switch_dev *p; + int id; + + if (!info->attrs[SWITCH_ATTR_ID]) + goto done; + + id = nla_get_u32(info->attrs[SWITCH_ATTR_ID]); + swconfig_lock(); + list_for_each_entry(p, &swdevs, dev_list) { + if (id != p->id) + continue; + + dev = p; + break; + } + if (dev) + mutex_lock(&dev->sw_mutex); + else + pr_debug("device %d not found\n", id); + swconfig_unlock(); +done: + return dev; +} + +static inline void +swconfig_put_dev(struct switch_dev *dev) +{ + mutex_unlock(&dev->sw_mutex); +} + +static int +swconfig_dump_attr(struct swconfig_callback *cb, void *arg) +{ + struct switch_attr *op = arg; + struct genl_info *info = cb->info; + struct sk_buff *msg = cb->msg; + int id = cb->args[0]; + void *hdr; + + hdr = genlmsg_put(msg, info->snd_portid, info->snd_seq, &switch_fam, + NLM_F_MULTI, SWITCH_CMD_NEW_ATTR); + if (IS_ERR(hdr)) + return -1; + + if (nla_put_u32(msg, SWITCH_ATTR_OP_ID, id)) + goto nla_put_failure; + if (nla_put_u32(msg, SWITCH_ATTR_OP_TYPE, op->type)) + goto nla_put_failure; + if (nla_put_string(msg, SWITCH_ATTR_OP_NAME, op->name)) + goto nla_put_failure; + if (op->description) + if (nla_put_string(msg, SWITCH_ATTR_OP_DESCRIPTION, + op->description)) + goto nla_put_failure; + + genlmsg_end(msg, hdr); + return msg->len; +nla_put_failure: + genlmsg_cancel(msg, hdr); + return -EMSGSIZE; +} + +/* spread multipart messages across multiple message buffers */ +static int +swconfig_send_multipart(struct swconfig_callback *cb, void *arg) +{ + struct genl_info *info = cb->info; + int restart = 0; + int err; + + do { + if (!cb->msg) { + cb->msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); + if (cb->msg == NULL) + goto error; + } + + if (!(cb->fill(cb, arg) < 0)) + break; + + /* fill failed, check if this was already the second attempt */ + if (restart) + goto error; + + /* try again in a new message, send the current one */ + restart = 1; + if (cb->close) { + if (cb->close(cb, arg) < 0) + goto error; + } + err = genlmsg_reply(cb->msg, info); + cb->msg = NULL; + if (err < 0) + goto error; + + } while (restart); + + return 0; + +error: + if (cb->msg) + nlmsg_free(cb->msg); + return -1; +} + +static int +swconfig_list_attrs(struct sk_buff *skb, struct genl_info *info) +{ + struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); + const struct switch_attrlist *alist; + struct switch_dev *dev; + struct swconfig_callback cb; + int err = -EINVAL; + int i; + + /* defaults */ + struct switch_attr *def_list; + unsigned long *def_active; + int n_def; + + dev = swconfig_get_dev(info); + if (!dev) + return -EINVAL; + + switch (hdr->cmd) { + case SWITCH_CMD_LIST_GLOBAL: + alist = &dev->ops->attr_global; + def_list = default_global; + def_active = &dev->def_global; + n_def = ARRAY_SIZE(default_global); + break; + case SWITCH_CMD_LIST_VLAN: + alist = &dev->ops->attr_vlan; + def_list = default_vlan; + def_active = &dev->def_vlan; + n_def = ARRAY_SIZE(default_vlan); + break; + case SWITCH_CMD_LIST_PORT: + alist = &dev->ops->attr_port; + def_list = default_port; + def_active = &dev->def_port; + n_def = ARRAY_SIZE(default_port); + break; + default: + WARN_ON(1); + goto out; + } + + memset(&cb, 0, sizeof(cb)); + cb.info = info; + cb.fill = swconfig_dump_attr; + for (i = 0; i < alist->n_attr; i++) { + if (alist->attr[i].disabled) + continue; + cb.args[0] = i; + err = swconfig_send_multipart(&cb, (void *) &alist->attr[i]); + if (err < 0) + goto error; + } + + /* defaults */ + for (i = 0; i < n_def; i++) { + if (!test_bit(i, def_active)) + continue; + cb.args[0] = SWITCH_ATTR_DEFAULTS_OFFSET + i; + err = swconfig_send_multipart(&cb, (void *) &def_list[i]); + if (err < 0) + goto error; + } + swconfig_put_dev(dev); + + if (!cb.msg) + return 0; + + return genlmsg_reply(cb.msg, info); + +error: + if (cb.msg) + nlmsg_free(cb.msg); +out: + swconfig_put_dev(dev); + return err; +} + +static const struct switch_attr * +swconfig_lookup_attr(struct switch_dev *dev, struct genl_info *info, + struct switch_val *val) +{ + struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); + const struct switch_attrlist *alist; + const struct switch_attr *attr = NULL; + int attr_id; + + /* defaults */ + struct switch_attr *def_list; + unsigned long *def_active; + int n_def; + + if (!info->attrs[SWITCH_ATTR_OP_ID]) + goto done; + + switch (hdr->cmd) { + case SWITCH_CMD_SET_GLOBAL: + case SWITCH_CMD_GET_GLOBAL: + alist = &dev->ops->attr_global; + def_list = default_global; + def_active = &dev->def_global; + n_def = ARRAY_SIZE(default_global); + break; + case SWITCH_CMD_SET_VLAN: + case SWITCH_CMD_GET_VLAN: + alist = &dev->ops->attr_vlan; + def_list = default_vlan; + def_active = &dev->def_vlan; + n_def = ARRAY_SIZE(default_vlan); + if (!info->attrs[SWITCH_ATTR_OP_VLAN]) + goto done; + val->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_VLAN]); + if (val->port_vlan >= dev->vlans) + goto done; + break; + case SWITCH_CMD_SET_PORT: + case SWITCH_CMD_GET_PORT: + alist = &dev->ops->attr_port; + def_list = default_port; + def_active = &dev->def_port; + n_def = ARRAY_SIZE(default_port); + if (!info->attrs[SWITCH_ATTR_OP_PORT]) + goto done; + val->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_PORT]); + if (val->port_vlan >= dev->ports) + goto done; + break; + default: + WARN_ON(1); + goto done; + } + + if (!alist) + goto done; + + attr_id = nla_get_u32(info->attrs[SWITCH_ATTR_OP_ID]); + if (attr_id >= SWITCH_ATTR_DEFAULTS_OFFSET) { + attr_id -= SWITCH_ATTR_DEFAULTS_OFFSET; + if (attr_id >= n_def) + goto done; + if (!test_bit(attr_id, def_active)) + goto done; + attr = &def_list[attr_id]; + } else { + if (attr_id >= alist->n_attr) + goto done; + attr = &alist->attr[attr_id]; + } + + if (attr->disabled) + attr = NULL; + +done: + if (!attr) + pr_debug("attribute lookup failed\n"); + val->attr = attr; + return attr; +} + +static int +swconfig_parse_ports(struct sk_buff *msg, struct nlattr *head, + struct switch_val *val, int max) +{ + struct nlattr *nla; + int rem; + + val->len = 0; + nla_for_each_nested(nla, head, rem) { + struct nlattr *tb[SWITCH_PORT_ATTR_MAX+1]; + struct switch_port *port = &val->value.ports[val->len]; + + if (val->len >= max) + return -EINVAL; + + if (nla_parse_nested(tb, SWITCH_PORT_ATTR_MAX, nla, + port_policy)) + return -EINVAL; + + if (!tb[SWITCH_PORT_ID]) + return -EINVAL; + + port->id = nla_get_u32(tb[SWITCH_PORT_ID]); + if (tb[SWITCH_PORT_FLAG_TAGGED]) + port->flags |= (1 << SWITCH_PORT_FLAG_TAGGED); + val->len++; + } + + return 0; +} + +static int +swconfig_set_attr(struct sk_buff *skb, struct genl_info *info) +{ + const struct switch_attr *attr; + struct switch_dev *dev; + struct switch_val val; + int err = -EINVAL; + + dev = swconfig_get_dev(info); + if (!dev) + return -EINVAL; + + memset(&val, 0, sizeof(val)); + attr = swconfig_lookup_attr(dev, info, &val); + if (!attr || !attr->set) + goto error; + + val.attr = attr; + switch (attr->type) { + case SWITCH_TYPE_NOVAL: + break; + case SWITCH_TYPE_INT: + if (!info->attrs[SWITCH_ATTR_OP_VALUE_INT]) + goto error; + val.value.i = + nla_get_u32(info->attrs[SWITCH_ATTR_OP_VALUE_INT]); + break; + case SWITCH_TYPE_STRING: + if (!info->attrs[SWITCH_ATTR_OP_VALUE_STR]) + goto error; + val.value.s = + nla_data(info->attrs[SWITCH_ATTR_OP_VALUE_STR]); + break; + case SWITCH_TYPE_PORTS: + val.value.ports = dev->portbuf; + memset(dev->portbuf, 0, + sizeof(struct switch_port) * dev->ports); + + /* TODO: implement multipart? */ + if (info->attrs[SWITCH_ATTR_OP_VALUE_PORTS]) { + err = swconfig_parse_ports(skb, + info->attrs[SWITCH_ATTR_OP_VALUE_PORTS], + &val, dev->ports); + if (err < 0) + goto error; + } else { + val.len = 0; + err = 0; + } + break; + default: + goto error; + } + + err = attr->set(dev, attr, &val); +error: + swconfig_put_dev(dev); + return err; +} + +static int +swconfig_close_portlist(struct swconfig_callback *cb, void *arg) +{ + if (cb->nest[0]) + nla_nest_end(cb->msg, cb->nest[0]); + return 0; +} + +static int +swconfig_send_port(struct swconfig_callback *cb, void *arg) +{ + const struct switch_port *port = arg; + struct nlattr *p = NULL; + + if (!cb->nest[0]) { + cb->nest[0] = nla_nest_start(cb->msg, cb->cmd); + if (!cb->nest[0]) + return -1; + } + + p = nla_nest_start(cb->msg, SWITCH_ATTR_PORT); + if (!p) + goto error; + + if (nla_put_u32(cb->msg, SWITCH_PORT_ID, port->id)) + goto nla_put_failure; + if (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) { + if (nla_put_flag(cb->msg, SWITCH_PORT_FLAG_TAGGED)) + goto nla_put_failure; + } + + nla_nest_end(cb->msg, p); + return 0; + +nla_put_failure: + nla_nest_cancel(cb->msg, p); +error: + nla_nest_cancel(cb->msg, cb->nest[0]); + return -1; +} + +static int +swconfig_send_ports(struct sk_buff **msg, struct genl_info *info, int attr, + const struct switch_val *val) +{ + struct swconfig_callback cb; + int err = 0; + int i; + + if (!val->value.ports) + return -EINVAL; + + memset(&cb, 0, sizeof(cb)); + cb.cmd = attr; + cb.msg = *msg; + cb.info = info; + cb.fill = swconfig_send_port; + cb.close = swconfig_close_portlist; + + cb.nest[0] = nla_nest_start(cb.msg, cb.cmd); + for (i = 0; i < val->len; i++) { + err = swconfig_send_multipart(&cb, &val->value.ports[i]); + if (err) + goto done; + } + err = val->len; + swconfig_close_portlist(&cb, NULL); + *msg = cb.msg; + +done: + return err; +} + +static int +swconfig_get_attr(struct sk_buff *skb, struct genl_info *info) +{ + struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); + const struct switch_attr *attr; + struct switch_dev *dev; + struct sk_buff *msg = NULL; + struct switch_val val; + int err = -EINVAL; + int cmd = hdr->cmd; + + dev = swconfig_get_dev(info); + if (!dev) + return -EINVAL; + + memset(&val, 0, sizeof(val)); + attr = swconfig_lookup_attr(dev, info, &val); + if (!attr || !attr->get) + goto error; + + if (attr->type == SWITCH_TYPE_PORTS) { + val.value.ports = dev->portbuf; + memset(dev->portbuf, 0, + sizeof(struct switch_port) * dev->ports); + } + + err = attr->get(dev, attr, &val); + if (err) + goto error; + + msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); + if (!msg) + goto error; + + hdr = genlmsg_put(msg, info->snd_portid, info->snd_seq, &switch_fam, + 0, cmd); + if (IS_ERR(hdr)) + goto nla_put_failure; + + switch (attr->type) { + case SWITCH_TYPE_INT: + if (nla_put_u32(msg, SWITCH_ATTR_OP_VALUE_INT, val.value.i)) + goto nla_put_failure; + break; + case SWITCH_TYPE_STRING: + if (nla_put_string(msg, SWITCH_ATTR_OP_VALUE_STR, val.value.s)) + goto nla_put_failure; + break; + case SWITCH_TYPE_PORTS: + err = swconfig_send_ports(&msg, info, + SWITCH_ATTR_OP_VALUE_PORTS, &val); + if (err < 0) + goto nla_put_failure; + break; + default: + pr_debug("invalid type in attribute\n"); + err = -EINVAL; + goto error; + } + genlmsg_end(msg, hdr); + err = msg->len; + if (err < 0) + goto nla_put_failure; + + swconfig_put_dev(dev); + return genlmsg_reply(msg, info); + +nla_put_failure: + if (msg) + nlmsg_free(msg); +error: + swconfig_put_dev(dev); + if (!err) + err = -ENOMEM; + return err; +} + +static int +swconfig_send_switch(struct sk_buff *msg, u32 pid, u32 seq, int flags, + const struct switch_dev *dev) +{ + struct nlattr *p = NULL, *m = NULL; + void *hdr; + int i; + + hdr = genlmsg_put(msg, pid, seq, &switch_fam, flags, + SWITCH_CMD_NEW_ATTR); + if (IS_ERR(hdr)) + return -1; + + if (nla_put_u32(msg, SWITCH_ATTR_ID, dev->id)) + goto nla_put_failure; + if (nla_put_string(msg, SWITCH_ATTR_DEV_NAME, dev->devname)) + goto nla_put_failure; + if (nla_put_string(msg, SWITCH_ATTR_ALIAS, dev->alias)) + goto nla_put_failure; + if (nla_put_string(msg, SWITCH_ATTR_NAME, dev->name)) + goto nla_put_failure; + if (nla_put_u32(msg, SWITCH_ATTR_VLANS, dev->vlans)) + goto nla_put_failure; + if (nla_put_u32(msg, SWITCH_ATTR_PORTS, dev->ports)) + goto nla_put_failure; + if (nla_put_u32(msg, SWITCH_ATTR_CPU_PORT, dev->cpu_port)) + goto nla_put_failure; + + m = nla_nest_start(msg, SWITCH_ATTR_PORTMAP); + if (!m) + goto nla_put_failure; + for (i = 0; i < dev->ports; i++) { + p = nla_nest_start(msg, SWITCH_ATTR_PORTS); + if (!p) + continue; + if (dev->portmap[i].s) { + if (nla_put_string(msg, SWITCH_PORTMAP_SEGMENT, + dev->portmap[i].s)) + goto nla_put_failure; + if (nla_put_u32(msg, SWITCH_PORTMAP_VIRT, + dev->portmap[i].virt)) + goto nla_put_failure; + } + nla_nest_end(msg, p); + } + nla_nest_end(msg, m); + genlmsg_end(msg, hdr); + return msg->len; +nla_put_failure: + genlmsg_cancel(msg, hdr); + return -EMSGSIZE; +} + +static int swconfig_dump_switches(struct sk_buff *skb, + struct netlink_callback *cb) +{ + struct switch_dev *dev; + int start = cb->args[0]; + int idx = 0; + + swconfig_lock(); + list_for_each_entry(dev, &swdevs, dev_list) { + if (++idx <= start) + continue; + if (swconfig_send_switch(skb, NETLINK_CB(cb->skb).portid, + cb->nlh->nlmsg_seq, NLM_F_MULTI, + dev) < 0) + break; + } + swconfig_unlock(); + cb->args[0] = idx; + + return skb->len; +} + +static int +swconfig_done(struct netlink_callback *cb) +{ + return 0; +} + +static struct genl_ops swconfig_ops[] = { + { + .cmd = SWITCH_CMD_LIST_GLOBAL, + .doit = swconfig_list_attrs, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_LIST_VLAN, + .doit = swconfig_list_attrs, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_LIST_PORT, + .doit = swconfig_list_attrs, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_GET_GLOBAL, + .doit = swconfig_get_attr, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_GET_VLAN, + .doit = swconfig_get_attr, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_GET_PORT, + .doit = swconfig_get_attr, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_SET_GLOBAL, + .doit = swconfig_set_attr, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_SET_VLAN, + .doit = swconfig_set_attr, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_SET_PORT, + .doit = swconfig_set_attr, + .policy = switch_policy, + }, + { + .cmd = SWITCH_CMD_GET_SWITCH, + .dumpit = swconfig_dump_switches, + .policy = switch_policy, + .done = swconfig_done, + } +}; + +#ifdef CONFIG_OF +void +of_switch_load_portmap(struct switch_dev *dev) +{ + struct device_node *port; + + if (!dev->of_node) + return; + + for_each_child_of_node(dev->of_node, port) { + const __be32 *prop; + const char *segment; + int size, phys; + + if (!of_device_is_compatible(port, "swconfig,port")) + continue; + + if (of_property_read_string(port, "swconfig,segment", &segment)) + continue; + + prop = of_get_property(port, "swconfig,portmap", &size); + if (!prop) + continue; + + if (size != (2 * sizeof(*prop))) { + pr_err("%s: failed to parse port mapping\n", + port->name); + continue; + } + + phys = be32_to_cpup(prop++); + if ((phys < 0) | (phys >= dev->ports)) { + pr_err("%s: physical port index out of range\n", + port->name); + continue; + } + + dev->portmap[phys].s = kstrdup(segment, GFP_KERNEL); + dev->portmap[phys].virt = be32_to_cpup(prop); + pr_debug("Found port: %s, physical: %d, virtual: %d\n", + segment, phys, dev->portmap[phys].virt); + } +} +#endif + +int +register_switch(struct switch_dev *dev, struct net_device *netdev) +{ + struct switch_dev *sdev; + const int max_switches = 8 * sizeof(unsigned long); + unsigned long in_use = 0; + int err; + int i; + + INIT_LIST_HEAD(&dev->dev_list); + if (netdev) { + dev->netdev = netdev; + if (!dev->alias) + dev->alias = netdev->name; + } + BUG_ON(!dev->alias); + + if (dev->ports > 0) { + dev->portbuf = kzalloc(sizeof(struct switch_port) * + dev->ports, GFP_KERNEL); + if (!dev->portbuf) + return -ENOMEM; + dev->portmap = kzalloc(sizeof(struct switch_portmap) * + dev->ports, GFP_KERNEL); + if (!dev->portmap) { + kfree(dev->portbuf); + return -ENOMEM; + } + } + swconfig_defaults_init(dev); + mutex_init(&dev->sw_mutex); + swconfig_lock(); + dev->id = ++swdev_id; + + list_for_each_entry(sdev, &swdevs, dev_list) { + if (!sscanf(sdev->devname, SWCONFIG_DEVNAME, &i)) + continue; + if (i < 0 || i > max_switches) + continue; + + set_bit(i, &in_use); + } + i = find_first_zero_bit(&in_use, max_switches); + + if (i == max_switches) { + swconfig_unlock(); + return -ENFILE; + } + +#ifdef CONFIG_OF + if (dev->ports) + of_switch_load_portmap(dev); +#endif + + /* fill device name */ + snprintf(dev->devname, IFNAMSIZ, SWCONFIG_DEVNAME, i); + + list_add_tail(&dev->dev_list, &swdevs); + swconfig_unlock(); + + err = swconfig_create_led_trigger(dev); + if (err) + return err; + + return 0; +} +EXPORT_SYMBOL_GPL(register_switch); + +void +unregister_switch(struct switch_dev *dev) +{ + swconfig_destroy_led_trigger(dev); + kfree(dev->portbuf); + mutex_lock(&dev->sw_mutex); + swconfig_lock(); + list_del(&dev->dev_list); + swconfig_unlock(); + mutex_unlock(&dev->sw_mutex); +} +EXPORT_SYMBOL_GPL(unregister_switch); + + +static int __init +swconfig_init(void) +{ + int err; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)) + int i; +#endif + + INIT_LIST_HEAD(&swdevs); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0)) + err = genl_register_family(&switch_fam); + if (err) + return err; + + for (i = 0; i < ARRAY_SIZE(swconfig_ops); i++) { + err = genl_register_ops(&switch_fam, &swconfig_ops[i]); + if (err) + goto unregister; + } + return 0; + +unregister: + genl_unregister_family(&switch_fam); + return err; +#else + err = genl_register_family_with_ops(&switch_fam, swconfig_ops); + if (err) + return err; + return 0; +#endif +} + +static void __exit +swconfig_exit(void) +{ + genl_unregister_family(&switch_fam); +} + +module_init(swconfig_init); +module_exit(swconfig_exit); + diff --git a/target/linux/generic/files/drivers/net/phy/swconfig_leds.c b/target/linux/generic/files/drivers/net/phy/swconfig_leds.c new file mode 100644 index 0000000..abd7bed --- /dev/null +++ b/target/linux/generic/files/drivers/net/phy/swconfig_leds.c @@ -0,0 +1,354 @@ +/* + * swconfig_led.c: LED trigger support for the switch configuration API + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + */ + +#ifdef CONFIG_SWCONFIG_LEDS + +#include +#include +#include +#include + +#define SWCONFIG_LED_TIMER_INTERVAL (HZ / 10) +#define SWCONFIG_LED_NUM_PORTS 32 + +struct switch_led_trigger { + struct led_trigger trig; + struct switch_dev *swdev; + + struct delayed_work sw_led_work; + u32 port_mask; + u32 port_link; + unsigned long port_traffic[SWCONFIG_LED_NUM_PORTS]; +}; + +struct swconfig_trig_data { + struct led_classdev *led_cdev; + struct switch_dev *swdev; + + rwlock_t lock; + u32 port_mask; + + bool prev_link; + unsigned long prev_traffic; + enum led_brightness prev_brightness; +}; + +static void +swconfig_trig_set_brightness(struct swconfig_trig_data *trig_data, + enum led_brightness brightness) +{ + led_set_brightness(trig_data->led_cdev, brightness); + trig_data->prev_brightness = brightness; +} + +static void +swconfig_trig_update_port_mask(struct led_trigger *trigger) +{ + struct list_head *entry; + struct switch_led_trigger *sw_trig; + u32 port_mask; + + if (!trigger) + return; + + sw_trig = (void *) trigger; + + port_mask = 0; + read_lock(&trigger->leddev_list_lock); + list_for_each(entry, &trigger->led_cdevs) { + struct led_classdev *led_cdev; + struct swconfig_trig_data *trig_data; + + led_cdev = list_entry(entry, struct led_classdev, trig_list); + trig_data = led_cdev->trigger_data; + if (trig_data) { + read_lock(&trig_data->lock); + port_mask |= trig_data->port_mask; + read_unlock(&trig_data->lock); + } + } + read_unlock(&trigger->leddev_list_lock); + + sw_trig->port_mask = port_mask; + + if (port_mask) + schedule_delayed_work(&sw_trig->sw_led_work, + SWCONFIG_LED_TIMER_INTERVAL); + else + cancel_delayed_work_sync(&sw_trig->sw_led_work); +} + +static ssize_t +swconfig_trig_port_mask_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct swconfig_trig_data *trig_data = led_cdev->trigger_data; + unsigned long port_mask; + ssize_t ret = -EINVAL; + char *after; + size_t count; + + port_mask = simple_strtoul(buf, &after, 16); + count = after - buf; + + if (*after && isspace(*after)) + count++; + + if (count == size) { + bool changed; + + write_lock(&trig_data->lock); + + changed = (trig_data->port_mask != port_mask); + if (changed) { + trig_data->port_mask = port_mask; + if (port_mask == 0) + swconfig_trig_set_brightness(trig_data, LED_OFF); + } + + write_unlock(&trig_data->lock); + + if (changed) + swconfig_trig_update_port_mask(led_cdev->trigger); + + ret = count; + } + + return ret; +} + +static ssize_t +swconfig_trig_port_mask_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct swconfig_trig_data *trig_data = led_cdev->trigger_data; + + read_lock(&trig_data->lock); + sprintf(buf, "%#x\n", trig_data->port_mask); + read_unlock(&trig_data->lock); + + return strlen(buf) + 1; +} + +static DEVICE_ATTR(port_mask, 0644, swconfig_trig_port_mask_show, + swconfig_trig_port_mask_store); + +static void +swconfig_trig_activate(struct led_classdev *led_cdev) +{ + struct switch_led_trigger *sw_trig; + struct swconfig_trig_data *trig_data; + int err; + + if (led_cdev->trigger->activate != swconfig_trig_activate) + return; + + trig_data = kzalloc(sizeof(struct swconfig_trig_data), GFP_KERNEL); + if (!trig_data) + return; + + sw_trig = (void *) led_cdev->trigger; + + rwlock_init(&trig_data->lock); + trig_data->led_cdev = led_cdev; + trig_data->swdev = sw_trig->swdev; + led_cdev->trigger_data = trig_data; + + err = device_create_file(led_cdev->dev, &dev_attr_port_mask); + if (err) + goto err_free; + + return; + +err_free: + led_cdev->trigger_data = NULL; + kfree(trig_data); +} + +static void +swconfig_trig_deactivate(struct led_classdev *led_cdev) +{ + struct swconfig_trig_data *trig_data; + + swconfig_trig_update_port_mask(led_cdev->trigger); + + trig_data = (void *) led_cdev->trigger_data; + if (trig_data) { + device_remove_file(led_cdev->dev, &dev_attr_port_mask); + kfree(trig_data); + } +} + +static void +swconfig_trig_led_event(struct switch_led_trigger *sw_trig, + struct led_classdev *led_cdev) +{ + struct swconfig_trig_data *trig_data; + u32 port_mask; + bool link; + + trig_data = led_cdev->trigger_data; + if (!trig_data) + return; + + read_lock(&trig_data->lock); + port_mask = trig_data->port_mask; + read_unlock(&trig_data->lock); + + link = !!(sw_trig->port_link & port_mask); + if (!link) { + if (link != trig_data->prev_link) + swconfig_trig_set_brightness(trig_data, LED_OFF); + } else { + unsigned long traffic; + int i; + + traffic = 0; + for (i = 0; i < SWCONFIG_LED_NUM_PORTS; i++) { + if (port_mask & (1 << i)) + traffic += sw_trig->port_traffic[i]; + } + + if (trig_data->prev_brightness != LED_FULL) + swconfig_trig_set_brightness(trig_data, LED_FULL); + else if (traffic != trig_data->prev_traffic) + swconfig_trig_set_brightness(trig_data, LED_OFF); + + trig_data->prev_traffic = traffic; + } + + trig_data->prev_link = link; +} + +static void +swconfig_trig_update_leds(struct switch_led_trigger *sw_trig) +{ + struct list_head *entry; + struct led_trigger *trigger; + + trigger = &sw_trig->trig; + read_lock(&trigger->leddev_list_lock); + list_for_each(entry, &trigger->led_cdevs) { + struct led_classdev *led_cdev; + + led_cdev = list_entry(entry, struct led_classdev, trig_list); + swconfig_trig_led_event(sw_trig, led_cdev); + } + read_unlock(&trigger->leddev_list_lock); +} + +static void +swconfig_led_work_func(struct work_struct *work) +{ + struct switch_led_trigger *sw_trig; + struct switch_dev *swdev; + u32 port_mask; + u32 link; + int i; + + sw_trig = container_of(work, struct switch_led_trigger, + sw_led_work.work); + + port_mask = sw_trig->port_mask; + swdev = sw_trig->swdev; + + link = 0; + for (i = 0; i < SWCONFIG_LED_NUM_PORTS; i++) { + u32 port_bit; + + port_bit = BIT(i); + if ((port_mask & port_bit) == 0) + continue; + + if (swdev->ops->get_port_link) { + struct switch_port_link port_link; + + memset(&port_link, '\0', sizeof(port_link)); + swdev->ops->get_port_link(swdev, i, &port_link); + + if (port_link.link) + link |= port_bit; + } + + if (swdev->ops->get_port_stats) { + struct switch_port_stats port_stats; + + memset(&port_stats, '\0', sizeof(port_stats)); + swdev->ops->get_port_stats(swdev, i, &port_stats); + sw_trig->port_traffic[i] = port_stats.tx_bytes + + port_stats.rx_bytes; + } + } + + sw_trig->port_link = link; + + swconfig_trig_update_leds(sw_trig); + + schedule_delayed_work(&sw_trig->sw_led_work, + SWCONFIG_LED_TIMER_INTERVAL); +} + +static int +swconfig_create_led_trigger(struct switch_dev *swdev) +{ + struct switch_led_trigger *sw_trig; + int err; + + if (!swdev->ops->get_port_link) + return 0; + + sw_trig = kzalloc(sizeof(struct switch_led_trigger), GFP_KERNEL); + if (!sw_trig) + return -ENOMEM; + + sw_trig->swdev = swdev; + sw_trig->trig.name = swdev->devname; + sw_trig->trig.activate = swconfig_trig_activate; + sw_trig->trig.deactivate = swconfig_trig_deactivate; + + INIT_DELAYED_WORK(&sw_trig->sw_led_work, swconfig_led_work_func); + + err = led_trigger_register(&sw_trig->trig); + if (err) + goto err_free; + + swdev->led_trigger = sw_trig; + + return 0; + +err_free: + kfree(sw_trig); + return err; +} + +static void +swconfig_destroy_led_trigger(struct switch_dev *swdev) +{ + struct switch_led_trigger *sw_trig; + + sw_trig = swdev->led_trigger; + if (sw_trig) { + cancel_delayed_work_sync(&sw_trig->sw_led_work); + led_trigger_unregister(&sw_trig->trig); + kfree(sw_trig); + } +} + +#else /* SWCONFIG_LEDS */ +static inline int +swconfig_create_led_trigger(struct switch_dev *swdev) { return 0; } + +static inline void +swconfig_destroy_led_trigger(struct switch_dev *swdev) { } +#endif /* CONFIG_SWCONFIG_LEDS */ diff --git a/target/linux/generic/files/fs/yaffs2/Kconfig b/target/linux/generic/files/fs/yaffs2/Kconfig new file mode 100644 index 0000000..408570f --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/Kconfig @@ -0,0 +1,171 @@ +# +# yaffs file system configurations +# + +config YAFFS_FS + tristate "yaffs2 file system support" + default n + depends on MTD_BLOCK + select YAFFS_YAFFS1 + select YAFFS_YAFFS2 + help + yaffs2, or Yet Another Flash File System, is a file system + optimised for NAND Flash chips. + + To compile the yaffs2 file system support as a module, choose M + here: the module will be called yaffs2. + + If unsure, say N. + + Further information on yaffs2 is available at + . + +config YAFFS_YAFFS1 + bool "512 byte / page devices" + depends on YAFFS_FS + default y + help + Enable yaffs1 support -- yaffs for 512 byte / page devices + + Not needed for 2K-page devices. + + If unsure, say Y. + +config YAFFS_9BYTE_TAGS + bool "Use older-style on-NAND data format with pageStatus byte" + depends on YAFFS_YAFFS1 + default n + help + + Older-style on-NAND data format has a "pageStatus" byte to record + chunk/page state. This byte is zero when the page is discarded. + Choose this option if you have existing on-NAND data using this + format that you need to continue to support. New data written + also uses the older-style format. Note: Use of this option + generally requires that MTD's oob layout be adjusted to use the + older-style format. See notes on tags formats and MTD versions + in yaffs_mtdif1.c. + + If unsure, say N. + +config YAFFS_DOES_ECC + bool "Lets yaffs do its own ECC" + depends on YAFFS_FS && YAFFS_YAFFS1 && !YAFFS_9BYTE_TAGS + default n + help + This enables yaffs to use its own ECC functions instead of using + the ones from the generic MTD-NAND driver. + + If unsure, say N. + +config YAFFS_ECC_WRONG_ORDER + bool "Use the same ecc byte order as Steven Hill's nand_ecc.c" + depends on YAFFS_FS && YAFFS_DOES_ECC && !YAFFS_9BYTE_TAGS + default n + help + This makes yaffs_ecc.c use the same ecc byte order as Steven + Hill's nand_ecc.c. If not set, then you get the same ecc byte + order as SmartMedia. + + If unsure, say N. + +config YAFFS_YAFFS2 + bool "2048 byte (or larger) / page devices" + depends on YAFFS_FS + default y + help + Enable yaffs2 support -- yaffs for >= 2K bytes per page devices + + If unsure, say Y. + +config YAFFS_AUTO_YAFFS2 + bool "Autoselect yaffs2 format" + depends on YAFFS_YAFFS2 + default y + help + Without this, you need to explicitely use yaffs2 as the file + system type. With this, you can say "yaffs" and yaffs or yaffs2 + will be used depending on the device page size (yaffs on + 512-byte page devices, yaffs2 on 2K page devices). + + If unsure, say Y. + +config YAFFS_DISABLE_TAGS_ECC + bool "Disable yaffs from doing ECC on tags by default" + depends on YAFFS_FS && YAFFS_YAFFS2 + default n + help + This defaults yaffs to using its own ECC calculations on tags instead of + just relying on the MTD. + This behavior can also be overridden with tags_ecc_on and + tags_ecc_off mount options. + + If unsure, say N. + +config YAFFS_ALWAYS_CHECK_CHUNK_ERASED + bool "Force chunk erase check" + depends on YAFFS_FS + default n + help + Normally yaffs only checks chunks before writing until an erased + chunk is found. This helps to detect any partially written + chunks that might have happened due to power loss. + + Enabling this forces on the test that chunks are erased in flash + before writing to them. This takes more time but is potentially + a bit more secure. + + Suggest setting Y during development and ironing out driver + issues etc. Suggest setting to N if you want faster writing. + + If unsure, say Y. + +config YAFFS_EMPTY_LOST_AND_FOUND + bool "Empty lost and found on boot" + depends on YAFFS_FS + default n + help + If this is enabled then the contents of lost and found is + automatically dumped at mount. + + If unsure, say N. + +config YAFFS_DISABLE_BLOCK_REFRESHING + bool "Disable yaffs2 block refreshing" + depends on YAFFS_FS + default n + help + If this is set, then block refreshing is disabled. + Block refreshing infrequently refreshes the oldest block in + a yaffs2 file system. This mechanism helps to refresh flash to + mitigate against data loss. This is particularly useful for MLC. + + If unsure, say N. + +config YAFFS_DISABLE_BACKGROUND + bool "Disable yaffs2 background processing" + depends on YAFFS_FS + default n + help + If this is set, then background processing is disabled. + Background processing makes many foreground activities faster. + + If unsure, say N. + +config YAFFS_DISABLE_BAD_BLOCK_MARKING + bool "Disable yaffs2 bad block marking" + depends on YAFFS_FS + default n + help + Useful during early flash bring up to prevent problems causing + lots of bad block marking. + + If unsure, say N. + +config YAFFS_XATTR + bool "Enable yaffs2 xattr support" + depends on YAFFS_FS + default y + help + If this is set then yaffs2 will provide xattr support. + If unsure, say Y. diff --git a/target/linux/generic/files/fs/yaffs2/Makefile b/target/linux/generic/files/fs/yaffs2/Makefile new file mode 100644 index 0000000..f9a9fb1 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the linux YAFFS filesystem routines. +# + +obj-$(CONFIG_YAFFS_FS) += yaffs.o + +yaffs-y := yaffs_ecc.o yaffs_vfs.o yaffs_guts.o yaffs_checkptrw.o +yaffs-y += yaffs_packedtags1.o yaffs_packedtags2.o yaffs_nand.o +yaffs-y += yaffs_tagscompat.o yaffs_tagsmarshall.o +yaffs-y += yaffs_mtdif.o +yaffs-y += yaffs_nameval.o yaffs_attribs.o +yaffs-y += yaffs_allocator.o +yaffs-y += yaffs_yaffs1.o +yaffs-y += yaffs_yaffs2.o +yaffs-y += yaffs_bitmap.o +yaffs-y += yaffs_summary.o +yaffs-y += yaffs_verify.o + diff --git a/target/linux/generic/files/fs/yaffs2/NOTE.openwrt b/target/linux/generic/files/fs/yaffs2/NOTE.openwrt new file mode 100644 index 0000000..e84fbe6 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/NOTE.openwrt @@ -0,0 +1,4 @@ +The yaffs2 source has been fetched from the yaffs2 GIT tree. + +URL: git://www.aleph1.co.uk/yaffs2 +Version: 583dbd9cc2668870cb013f051ba59f7d3e513dae (2015-06-02) diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_allocator.c b/target/linux/generic/files/fs/yaffs2/yaffs_allocator.c new file mode 100644 index 0000000..c8f2861 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_allocator.c @@ -0,0 +1,357 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_allocator.h" +#include "yaffs_guts.h" +#include "yaffs_trace.h" +#include "yportenv.h" + +/* + * Each entry in yaffs_tnode_list and yaffs_obj_list hold blocks + * of approx 100 objects that are themn allocated singly. + * This is basically a simplified slab allocator. + * + * We don't use the Linux slab allocator because slab does not allow + * us to dump all the objects in one hit when we do a umount and tear + * down all the tnodes and objects. slab requires that we first free + * the individual objects. + * + * Once yaffs has been mainlined I shall try to motivate for a change + * to slab to provide the extra features we need here. + */ + +struct yaffs_tnode_list { + struct yaffs_tnode_list *next; + struct yaffs_tnode *tnodes; +}; + +struct yaffs_obj_list { + struct yaffs_obj_list *next; + struct yaffs_obj *objects; +}; + +struct yaffs_allocator { + int n_tnodes_created; + struct yaffs_tnode *free_tnodes; + int n_free_tnodes; + struct yaffs_tnode_list *alloc_tnode_list; + + int n_obj_created; + struct list_head free_objs; + int n_free_objects; + + struct yaffs_obj_list *allocated_obj_list; +}; + +static void yaffs_deinit_raw_tnodes(struct yaffs_dev *dev) +{ + struct yaffs_allocator *allocator = + (struct yaffs_allocator *)dev->allocator; + struct yaffs_tnode_list *tmp; + + if (!allocator) { + BUG(); + return; + } + + while (allocator->alloc_tnode_list) { + tmp = allocator->alloc_tnode_list->next; + + kfree(allocator->alloc_tnode_list->tnodes); + kfree(allocator->alloc_tnode_list); + allocator->alloc_tnode_list = tmp; + } + + allocator->free_tnodes = NULL; + allocator->n_free_tnodes = 0; + allocator->n_tnodes_created = 0; +} + +static void yaffs_init_raw_tnodes(struct yaffs_dev *dev) +{ + struct yaffs_allocator *allocator = dev->allocator; + + if (!allocator) { + BUG(); + return; + } + + allocator->alloc_tnode_list = NULL; + allocator->free_tnodes = NULL; + allocator->n_free_tnodes = 0; + allocator->n_tnodes_created = 0; +} + +static int yaffs_create_tnodes(struct yaffs_dev *dev, int n_tnodes) +{ + struct yaffs_allocator *allocator = + (struct yaffs_allocator *)dev->allocator; + int i; + struct yaffs_tnode *new_tnodes; + u8 *mem; + struct yaffs_tnode *curr; + struct yaffs_tnode *next; + struct yaffs_tnode_list *tnl; + + if (!allocator) { + BUG(); + return YAFFS_FAIL; + } + + if (n_tnodes < 1) + return YAFFS_OK; + + /* make these things */ + new_tnodes = kmalloc(n_tnodes * dev->tnode_size, GFP_NOFS); + mem = (u8 *) new_tnodes; + + if (!new_tnodes) { + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs: Could not allocate Tnodes"); + return YAFFS_FAIL; + } + + /* New hookup for wide tnodes */ + for (i = 0; i < n_tnodes - 1; i++) { + curr = (struct yaffs_tnode *)&mem[i * dev->tnode_size]; + next = (struct yaffs_tnode *)&mem[(i + 1) * dev->tnode_size]; + curr->internal[0] = next; + } + + curr = (struct yaffs_tnode *)&mem[(n_tnodes - 1) * dev->tnode_size]; + curr->internal[0] = allocator->free_tnodes; + allocator->free_tnodes = (struct yaffs_tnode *)mem; + + allocator->n_free_tnodes += n_tnodes; + allocator->n_tnodes_created += n_tnodes; + + /* Now add this bunch of tnodes to a list for freeing up. + * NB If we can't add this to the management list it isn't fatal + * but it just means we can't free this bunch of tnodes later. + */ + tnl = kmalloc(sizeof(struct yaffs_tnode_list), GFP_NOFS); + if (!tnl) { + yaffs_trace(YAFFS_TRACE_ERROR, + "Could not add tnodes to management list"); + return YAFFS_FAIL; + } else { + tnl->tnodes = new_tnodes; + tnl->next = allocator->alloc_tnode_list; + allocator->alloc_tnode_list = tnl; + } + + yaffs_trace(YAFFS_TRACE_ALLOCATE, "Tnodes added"); + + return YAFFS_OK; +} + +struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev) +{ + struct yaffs_allocator *allocator = + (struct yaffs_allocator *)dev->allocator; + struct yaffs_tnode *tn = NULL; + + if (!allocator) { + BUG(); + return NULL; + } + + /* If there are none left make more */ + if (!allocator->free_tnodes) + yaffs_create_tnodes(dev, YAFFS_ALLOCATION_NTNODES); + + if (allocator->free_tnodes) { + tn = allocator->free_tnodes; + allocator->free_tnodes = allocator->free_tnodes->internal[0]; + allocator->n_free_tnodes--; + } + + return tn; +} + +/* FreeTnode frees up a tnode and puts it back on the free list */ +void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) +{ + struct yaffs_allocator *allocator = dev->allocator; + + if (!allocator) { + BUG(); + return; + } + + if (tn) { + tn->internal[0] = allocator->free_tnodes; + allocator->free_tnodes = tn; + allocator->n_free_tnodes++; + } + dev->checkpoint_blocks_required = 0; /* force recalculation */ +} + +/*--------------- yaffs_obj alloaction ------------------------ + * + * Free yaffs_objs are stored in a list using obj->siblings. + * The blocks of allocated objects are stored in a linked list. + */ + +static void yaffs_init_raw_objs(struct yaffs_dev *dev) +{ + struct yaffs_allocator *allocator = dev->allocator; + + if (!allocator) { + BUG(); + return; + } + + allocator->allocated_obj_list = NULL; + INIT_LIST_HEAD(&allocator->free_objs); + allocator->n_free_objects = 0; +} + +static void yaffs_deinit_raw_objs(struct yaffs_dev *dev) +{ + struct yaffs_allocator *allocator = dev->allocator; + struct yaffs_obj_list *tmp; + + if (!allocator) { + BUG(); + return; + } + + while (allocator->allocated_obj_list) { + tmp = allocator->allocated_obj_list->next; + kfree(allocator->allocated_obj_list->objects); + kfree(allocator->allocated_obj_list); + allocator->allocated_obj_list = tmp; + } + + INIT_LIST_HEAD(&allocator->free_objs); + allocator->n_free_objects = 0; + allocator->n_obj_created = 0; +} + +static int yaffs_create_free_objs(struct yaffs_dev *dev, int n_obj) +{ + struct yaffs_allocator *allocator = dev->allocator; + int i; + struct yaffs_obj *new_objs; + struct yaffs_obj_list *list; + + if (!allocator) { + BUG(); + return YAFFS_FAIL; + } + + if (n_obj < 1) + return YAFFS_OK; + + /* make these things */ + new_objs = kmalloc(n_obj * sizeof(struct yaffs_obj), GFP_NOFS); + list = kmalloc(sizeof(struct yaffs_obj_list), GFP_NOFS); + + if (!new_objs || !list) { + kfree(new_objs); + new_objs = NULL; + kfree(list); + list = NULL; + yaffs_trace(YAFFS_TRACE_ALLOCATE, + "Could not allocate more objects"); + return YAFFS_FAIL; + } + + /* Hook them into the free list */ + for (i = 0; i < n_obj; i++) + list_add(&new_objs[i].siblings, &allocator->free_objs); + + allocator->n_free_objects += n_obj; + allocator->n_obj_created += n_obj; + + /* Now add this bunch of Objects to a list for freeing up. */ + + list->objects = new_objs; + list->next = allocator->allocated_obj_list; + allocator->allocated_obj_list = list; + + return YAFFS_OK; +} + +struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev) +{ + struct yaffs_obj *obj = NULL; + struct list_head *lh; + struct yaffs_allocator *allocator = dev->allocator; + + if (!allocator) { + BUG(); + return obj; + } + + /* If there are none left make more */ + if (list_empty(&allocator->free_objs)) + yaffs_create_free_objs(dev, YAFFS_ALLOCATION_NOBJECTS); + + if (!list_empty(&allocator->free_objs)) { + lh = allocator->free_objs.next; + obj = list_entry(lh, struct yaffs_obj, siblings); + list_del_init(lh); + allocator->n_free_objects--; + } + + return obj; +} + +void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj) +{ + + struct yaffs_allocator *allocator = dev->allocator; + + if (!allocator) { + BUG(); + return; + } + + /* Link into the free list. */ + list_add(&obj->siblings, &allocator->free_objs); + allocator->n_free_objects++; +} + +void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev) +{ + + if (!dev->allocator) { + BUG(); + return; + } + + yaffs_deinit_raw_tnodes(dev); + yaffs_deinit_raw_objs(dev); + kfree(dev->allocator); + dev->allocator = NULL; +} + +void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev) +{ + struct yaffs_allocator *allocator; + + if (dev->allocator) { + BUG(); + return; + } + + allocator = kmalloc(sizeof(struct yaffs_allocator), GFP_NOFS); + if (allocator) { + dev->allocator = allocator; + yaffs_init_raw_tnodes(dev); + yaffs_init_raw_objs(dev); + } +} + diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_allocator.h b/target/linux/generic/files/fs/yaffs2/yaffs_allocator.h new file mode 100644 index 0000000..a8cc322 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_allocator.h @@ -0,0 +1,30 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_ALLOCATOR_H__ +#define __YAFFS_ALLOCATOR_H__ + +#include "yaffs_guts.h" + +void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev); +void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev); + +struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev); +void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn); + +struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev); +void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_attribs.c b/target/linux/generic/files/fs/yaffs2/yaffs_attribs.c new file mode 100644 index 0000000..711941f --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_attribs.c @@ -0,0 +1,132 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_guts.h" +#include "yaffs_attribs.h" + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) +#define IATTR_UID ia_uid +#define IATTR_GID ia_gid +#else +#define IATTR_UID ia_uid.val +#define IATTR_GID ia_gid.val +#endif + +void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh) +{ + obj->yst_uid = oh->yst_uid; + obj->yst_gid = oh->yst_gid; + obj->yst_atime = oh->yst_atime; + obj->yst_mtime = oh->yst_mtime; + obj->yst_ctime = oh->yst_ctime; + obj->yst_rdev = oh->yst_rdev; +} + +void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj) +{ + oh->yst_uid = obj->yst_uid; + oh->yst_gid = obj->yst_gid; + oh->yst_atime = obj->yst_atime; + oh->yst_mtime = obj->yst_mtime; + oh->yst_ctime = obj->yst_ctime; + oh->yst_rdev = obj->yst_rdev; + +} + +void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c) +{ + obj->yst_mtime = Y_CURRENT_TIME; + if (do_a) + obj->yst_atime = obj->yst_mtime; + if (do_c) + obj->yst_ctime = obj->yst_mtime; +} + +void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev) +{ + yaffs_load_current_time(obj, 1, 1); + obj->yst_rdev = rdev; + obj->yst_uid = uid; + obj->yst_gid = gid; +} + +static loff_t yaffs_get_file_size(struct yaffs_obj *obj) +{ + YCHAR *alias = NULL; + obj = yaffs_get_equivalent_obj(obj); + + switch (obj->variant_type) { + case YAFFS_OBJECT_TYPE_FILE: + return obj->variant.file_variant.file_size; + case YAFFS_OBJECT_TYPE_SYMLINK: + alias = obj->variant.symlink_variant.alias; + if (!alias) + return 0; + return strnlen(alias, YAFFS_MAX_ALIAS_LENGTH); + default: + return 0; + } +} + +int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr) +{ + unsigned int valid = attr->ia_valid; + + if (valid & ATTR_MODE) + obj->yst_mode = attr->ia_mode; + if (valid & ATTR_UID) + obj->yst_uid = attr->IATTR_UID; + if (valid & ATTR_GID) + obj->yst_gid = attr->IATTR_GID; + + if (valid & ATTR_ATIME) + obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime); + if (valid & ATTR_CTIME) + obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime); + if (valid & ATTR_MTIME) + obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime); + + if (valid & ATTR_SIZE) + yaffs_resize_file(obj, attr->ia_size); + + yaffs_update_oh(obj, NULL, 1, 0, 0, NULL); + + return YAFFS_OK; + +} + +int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr) +{ + unsigned int valid = 0; + + attr->ia_mode = obj->yst_mode; + valid |= ATTR_MODE; + attr->IATTR_UID = obj->yst_uid; + valid |= ATTR_UID; + attr->IATTR_GID = obj->yst_gid; + valid |= ATTR_GID; + + Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime; + valid |= ATTR_ATIME; + Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime; + valid |= ATTR_CTIME; + Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime; + valid |= ATTR_MTIME; + + attr->ia_size = yaffs_get_file_size(obj); + valid |= ATTR_SIZE; + + attr->ia_valid = valid; + + return YAFFS_OK; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_attribs.h b/target/linux/generic/files/fs/yaffs2/yaffs_attribs.h new file mode 100644 index 0000000..5b21b08 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_attribs.h @@ -0,0 +1,28 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_ATTRIBS_H__ +#define __YAFFS_ATTRIBS_H__ + +#include "yaffs_guts.h" + +void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh); +void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj); +void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev); +void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c); +int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr); +int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_bitmap.c b/target/linux/generic/files/fs/yaffs2/yaffs_bitmap.c new file mode 100644 index 0000000..4440e93 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_bitmap.c @@ -0,0 +1,97 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_bitmap.h" +#include "yaffs_trace.h" +/* + * Chunk bitmap manipulations + */ + +static inline u8 *yaffs_block_bits(struct yaffs_dev *dev, int blk) +{ + if (blk < dev->internal_start_block || blk > dev->internal_end_block) { + yaffs_trace(YAFFS_TRACE_ERROR, + "BlockBits block %d is not valid", + blk); + BUG(); + } + return dev->chunk_bits + + (dev->chunk_bit_stride * (blk - dev->internal_start_block)); +} + +void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk) +{ + if (blk < dev->internal_start_block || blk > dev->internal_end_block || + chunk < 0 || chunk >= dev->param.chunks_per_block) { + yaffs_trace(YAFFS_TRACE_ERROR, + "Chunk Id (%d:%d) invalid", + blk, chunk); + BUG(); + } +} + +void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk) +{ + u8 *blk_bits = yaffs_block_bits(dev, blk); + + memset(blk_bits, 0, dev->chunk_bit_stride); +} + +void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) +{ + u8 *blk_bits = yaffs_block_bits(dev, blk); + + yaffs_verify_chunk_bit_id(dev, blk, chunk); + blk_bits[chunk / 8] &= ~(1 << (chunk & 7)); +} + +void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) +{ + u8 *blk_bits = yaffs_block_bits(dev, blk); + + yaffs_verify_chunk_bit_id(dev, blk, chunk); + blk_bits[chunk / 8] |= (1 << (chunk & 7)); +} + +int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) +{ + u8 *blk_bits = yaffs_block_bits(dev, blk); + + yaffs_verify_chunk_bit_id(dev, blk, chunk); + return (blk_bits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0; +} + +int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk) +{ + u8 *blk_bits = yaffs_block_bits(dev, blk); + int i; + + for (i = 0; i < dev->chunk_bit_stride; i++) { + if (*blk_bits) + return 1; + blk_bits++; + } + return 0; +} + +int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk) +{ + u8 *blk_bits = yaffs_block_bits(dev, blk); + int i; + int n = 0; + + for (i = 0; i < dev->chunk_bit_stride; i++, blk_bits++) + n += hweight8(*blk_bits); + + return n; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_bitmap.h b/target/linux/generic/files/fs/yaffs2/yaffs_bitmap.h new file mode 100644 index 0000000..e26b37d --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_bitmap.h @@ -0,0 +1,33 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +/* + * Chunk bitmap manipulations + */ + +#ifndef __YAFFS_BITMAP_H__ +#define __YAFFS_BITMAP_H__ + +#include "yaffs_guts.h" + +void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk); +void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk); +void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); +void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); +int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); +int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk); +int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_checkptrw.c b/target/linux/generic/files/fs/yaffs2/yaffs_checkptrw.c new file mode 100644 index 0000000..16ee1e0 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_checkptrw.c @@ -0,0 +1,466 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_checkptrw.h" +#include "yaffs_getblockinfo.h" + +struct yaffs_checkpt_chunk_hdr { + int version; + int seq; + u32 sum; + u32 xor; +} ; + + +static int apply_chunk_offset(struct yaffs_dev *dev, int chunk) +{ + return chunk - dev->chunk_offset; +} + +static int apply_block_offset(struct yaffs_dev *dev, int block) +{ + return block - dev->block_offset; +} + +static void yaffs2_checkpt_init_chunk_hdr(struct yaffs_dev *dev) +{ + struct yaffs_checkpt_chunk_hdr hdr; + + hdr.version = YAFFS_CHECKPOINT_VERSION; + hdr.seq = dev->checkpt_page_seq; + hdr.sum = dev->checkpt_sum; + hdr.xor = dev->checkpt_xor; + + dev->checkpt_byte_offs = sizeof(hdr); + + memcpy(dev->checkpt_buffer, &hdr, sizeof(hdr)); +} + +static int yaffs2_checkpt_check_chunk_hdr(struct yaffs_dev *dev) +{ + struct yaffs_checkpt_chunk_hdr hdr; + + memcpy(&hdr, dev->checkpt_buffer, sizeof(hdr)); + + dev->checkpt_byte_offs = sizeof(hdr); + + return hdr.version == YAFFS_CHECKPOINT_VERSION && + hdr.seq == dev->checkpt_page_seq && + hdr.sum == dev->checkpt_sum && + hdr.xor == dev->checkpt_xor; +} + +static int yaffs2_checkpt_space_ok(struct yaffs_dev *dev) +{ + int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks; + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "checkpt blocks_avail = %d", blocks_avail); + + return (blocks_avail <= 0) ? 0 : 1; +} + +static int yaffs_checkpt_erase(struct yaffs_dev *dev) +{ + int i; + + if (!dev->drv.drv_erase_fn) + return 0; + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "checking blocks %d to %d", + dev->internal_start_block, dev->internal_end_block); + + for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { + struct yaffs_block_info *bi = yaffs_get_block_info(dev, i); + int offset_i = apply_block_offset(dev, i); + int result; + + if (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "erasing checkpt block %d", i); + + dev->n_erasures++; + + result = dev->drv.drv_erase_fn(dev, offset_i); + if(result) { + bi->block_state = YAFFS_BLOCK_STATE_EMPTY; + dev->n_erased_blocks++; + dev->n_free_chunks += + dev->param.chunks_per_block; + } else { + dev->drv.drv_mark_bad_fn(dev, offset_i); + bi->block_state = YAFFS_BLOCK_STATE_DEAD; + } + } + } + + dev->blocks_in_checkpt = 0; + + return 1; +} + +static void yaffs2_checkpt_find_erased_block(struct yaffs_dev *dev) +{ + int i; + int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks; + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "allocating checkpt block: erased %d reserved %d avail %d next %d ", + dev->n_erased_blocks, dev->param.n_reserved_blocks, + blocks_avail, dev->checkpt_next_block); + + if (dev->checkpt_next_block >= 0 && + dev->checkpt_next_block <= dev->internal_end_block && + blocks_avail > 0) { + + for (i = dev->checkpt_next_block; i <= dev->internal_end_block; + i++) { + struct yaffs_block_info *bi; + + bi = yaffs_get_block_info(dev, i); + if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { + dev->checkpt_next_block = i + 1; + dev->checkpt_cur_block = i; + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "allocating checkpt block %d", i); + return; + } + } + } + yaffs_trace(YAFFS_TRACE_CHECKPOINT, "out of checkpt blocks"); + + dev->checkpt_next_block = -1; + dev->checkpt_cur_block = -1; +} + +static void yaffs2_checkpt_find_block(struct yaffs_dev *dev) +{ + int i; + struct yaffs_ext_tags tags; + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "find next checkpt block: start: blocks %d next %d", + dev->blocks_in_checkpt, dev->checkpt_next_block); + + if (dev->blocks_in_checkpt < dev->checkpt_max_blocks) + for (i = dev->checkpt_next_block; i <= dev->internal_end_block; + i++) { + int chunk = i * dev->param.chunks_per_block; + enum yaffs_block_state state; + u32 seq; + + dev->tagger.read_chunk_tags_fn(dev, + apply_chunk_offset(dev, chunk), + NULL, &tags); + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "find next checkpt block: search: block %d state %d oid %d seq %d eccr %d", + i, (int) state, + tags.obj_id, tags.seq_number, + tags.ecc_result); + + if (tags.seq_number != YAFFS_SEQUENCE_CHECKPOINT_DATA) + continue; + + dev->tagger.query_block_fn(dev, + apply_block_offset(dev, i), + &state, &seq); + if (state == YAFFS_BLOCK_STATE_DEAD) + continue; + + /* Right kind of block */ + dev->checkpt_next_block = tags.obj_id; + dev->checkpt_cur_block = i; + dev->checkpt_block_list[dev->blocks_in_checkpt] = i; + dev->blocks_in_checkpt++; + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "found checkpt block %d", i); + return; + } + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, "found no more checkpt blocks"); + + dev->checkpt_next_block = -1; + dev->checkpt_cur_block = -1; +} + +int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing) +{ + int i; + + dev->checkpt_open_write = writing; + + /* Got the functions we need? */ + if (!dev->tagger.write_chunk_tags_fn || + !dev->tagger.read_chunk_tags_fn || + !dev->drv.drv_erase_fn || + !dev->drv.drv_mark_bad_fn) + return 0; + + if (writing && !yaffs2_checkpt_space_ok(dev)) + return 0; + + if (!dev->checkpt_buffer) + dev->checkpt_buffer = + kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS); + if (!dev->checkpt_buffer) + return 0; + + dev->checkpt_page_seq = 0; + dev->checkpt_byte_count = 0; + dev->checkpt_sum = 0; + dev->checkpt_xor = 0; + dev->checkpt_cur_block = -1; + dev->checkpt_cur_chunk = -1; + dev->checkpt_next_block = dev->internal_start_block; + + if (writing) { + memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk); + yaffs2_checkpt_init_chunk_hdr(dev); + return yaffs_checkpt_erase(dev); + } + + /* Opening for a read */ + /* Set to a value that will kick off a read */ + dev->checkpt_byte_offs = dev->data_bytes_per_chunk; + /* A checkpoint block list of 1 checkpoint block per 16 block is + * (hopefully) going to be way more than we need */ + dev->blocks_in_checkpt = 0; + dev->checkpt_max_blocks = + (dev->internal_end_block - dev->internal_start_block) / 16 + 2; + if (!dev->checkpt_block_list) + dev->checkpt_block_list = + kmalloc(sizeof(int) * dev->checkpt_max_blocks, GFP_NOFS); + + if (!dev->checkpt_block_list) + return 0; + + for (i = 0; i < dev->checkpt_max_blocks; i++) + dev->checkpt_block_list[i] = -1; + + return 1; +} + +int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum) +{ + u32 composite_sum; + + composite_sum = (dev->checkpt_sum << 8) | (dev->checkpt_xor & 0xff); + *sum = composite_sum; + return 1; +} + +static int yaffs2_checkpt_flush_buffer(struct yaffs_dev *dev) +{ + int chunk; + int offset_chunk; + struct yaffs_ext_tags tags; + + if (dev->checkpt_cur_block < 0) { + yaffs2_checkpt_find_erased_block(dev); + dev->checkpt_cur_chunk = 0; + } + + if (dev->checkpt_cur_block < 0) + return 0; + + tags.is_deleted = 0; + tags.obj_id = dev->checkpt_next_block; /* Hint to next place to look */ + tags.chunk_id = dev->checkpt_page_seq + 1; + tags.seq_number = YAFFS_SEQUENCE_CHECKPOINT_DATA; + tags.n_bytes = dev->data_bytes_per_chunk; + if (dev->checkpt_cur_chunk == 0) { + /* First chunk we write for the block? Set block state to + checkpoint */ + struct yaffs_block_info *bi = + yaffs_get_block_info(dev, dev->checkpt_cur_block); + bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; + dev->blocks_in_checkpt++; + } + + chunk = + dev->checkpt_cur_block * dev->param.chunks_per_block + + dev->checkpt_cur_chunk; + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "checkpoint wite buffer nand %d(%d:%d) objid %d chId %d", + chunk, dev->checkpt_cur_block, dev->checkpt_cur_chunk, + tags.obj_id, tags.chunk_id); + + offset_chunk = apply_chunk_offset(dev, chunk); + + dev->n_page_writes++; + + dev->tagger.write_chunk_tags_fn(dev, offset_chunk, + dev->checkpt_buffer, &tags); + dev->checkpt_page_seq++; + dev->checkpt_cur_chunk++; + if (dev->checkpt_cur_chunk >= dev->param.chunks_per_block) { + dev->checkpt_cur_chunk = 0; + dev->checkpt_cur_block = -1; + } + memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk); + + yaffs2_checkpt_init_chunk_hdr(dev); + + + return 1; +} + +int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes) +{ + int i = 0; + int ok = 1; + u8 *data_bytes = (u8 *) data; + + if (!dev->checkpt_buffer) + return 0; + + if (!dev->checkpt_open_write) + return -1; + + while (i < n_bytes && ok) { + dev->checkpt_buffer[dev->checkpt_byte_offs] = *data_bytes; + dev->checkpt_sum += *data_bytes; + dev->checkpt_xor ^= *data_bytes; + + dev->checkpt_byte_offs++; + i++; + data_bytes++; + dev->checkpt_byte_count++; + + if (dev->checkpt_byte_offs < 0 || + dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) + ok = yaffs2_checkpt_flush_buffer(dev); + } + + return i; +} + +int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes) +{ + int i = 0; + struct yaffs_ext_tags tags; + int chunk; + int offset_chunk; + u8 *data_bytes = (u8 *) data; + + if (!dev->checkpt_buffer) + return 0; + + if (dev->checkpt_open_write) + return -1; + + while (i < n_bytes) { + + if (dev->checkpt_byte_offs < 0 || + dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) { + + if (dev->checkpt_cur_block < 0) { + yaffs2_checkpt_find_block(dev); + dev->checkpt_cur_chunk = 0; + } + + /* Bail out if we can't find a checpoint block */ + if (dev->checkpt_cur_block < 0) + break; + + chunk = dev->checkpt_cur_block * + dev->param.chunks_per_block + + dev->checkpt_cur_chunk; + + offset_chunk = apply_chunk_offset(dev, chunk); + dev->n_page_reads++; + + /* Read in the next chunk */ + dev->tagger.read_chunk_tags_fn(dev, + offset_chunk, + dev->checkpt_buffer, + &tags); + + /* Bail out if the chunk is corrupted. */ + if (tags.chunk_id != (dev->checkpt_page_seq + 1) || + tags.ecc_result > YAFFS_ECC_RESULT_FIXED || + tags.seq_number != YAFFS_SEQUENCE_CHECKPOINT_DATA) + break; + + /* Bail out if it is not a checkpoint chunk. */ + if(!yaffs2_checkpt_check_chunk_hdr(dev)) + break; + + dev->checkpt_page_seq++; + dev->checkpt_cur_chunk++; + + if (dev->checkpt_cur_chunk >= + dev->param.chunks_per_block) + dev->checkpt_cur_block = -1; + + } + + *data_bytes = dev->checkpt_buffer[dev->checkpt_byte_offs]; + dev->checkpt_sum += *data_bytes; + dev->checkpt_xor ^= *data_bytes; + dev->checkpt_byte_offs++; + i++; + data_bytes++; + dev->checkpt_byte_count++; + } + + return i; /* Number of bytes read */ +} + +int yaffs_checkpt_close(struct yaffs_dev *dev) +{ + int i; + + if (dev->checkpt_open_write) { + if (dev->checkpt_byte_offs != + sizeof(sizeof(struct yaffs_checkpt_chunk_hdr))) + yaffs2_checkpt_flush_buffer(dev); + } else if (dev->checkpt_block_list) { + for (i = 0; + i < dev->blocks_in_checkpt && + dev->checkpt_block_list[i] >= 0; i++) { + int blk = dev->checkpt_block_list[i]; + struct yaffs_block_info *bi = NULL; + + if (dev->internal_start_block <= blk && + blk <= dev->internal_end_block) + bi = yaffs_get_block_info(dev, blk); + if (bi && bi->block_state == YAFFS_BLOCK_STATE_EMPTY) + bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; + } + } + + dev->n_free_chunks -= + dev->blocks_in_checkpt * dev->param.chunks_per_block; + dev->n_erased_blocks -= dev->blocks_in_checkpt; + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, "checkpoint byte count %d", + dev->checkpt_byte_count); + + if (dev->checkpt_buffer) + return 1; + else + return 0; +} + +int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev) +{ + /* Erase the checkpoint data */ + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "checkpoint invalidate of %d blocks", + dev->blocks_in_checkpt); + + return yaffs_checkpt_erase(dev); +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_checkptrw.h b/target/linux/generic/files/fs/yaffs2/yaffs_checkptrw.h new file mode 100644 index 0000000..cdbaba7 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_checkptrw.h @@ -0,0 +1,33 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_CHECKPTRW_H__ +#define __YAFFS_CHECKPTRW_H__ + +#include "yaffs_guts.h" + +int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing); + +int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes); + +int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes); + +int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum); + +int yaffs_checkpt_close(struct yaffs_dev *dev); + +int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_ecc.c b/target/linux/generic/files/fs/yaffs2/yaffs_ecc.c new file mode 100644 index 0000000..9294107 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_ecc.c @@ -0,0 +1,281 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * This code implements the ECC algorithm used in SmartMedia. + * + * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. + * The two unused bit are set to 1. + * The ECC can correct single bit errors in a 256-byte page of data. Thus, two + * such ECC blocks are used on a 512-byte NAND page. + * + */ + +#include "yportenv.h" + +#include "yaffs_ecc.h" + +/* Table generated by gen-ecc.c + * Using a table means we do not have to calculate p1..p4 and p1'..p4' + * for each byte of data. These are instead provided in a table in bits7..2. + * Bit 0 of each entry indicates whether the entry has an odd or even parity, + * and therefore this bytes influence on the line parity. + */ + +static const unsigned char column_parity_table[] = { + 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, + 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, + 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, + 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, + 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, + 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, + 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, + 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, + 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, + 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, + 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, + 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, + 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, + 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, + 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, + 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, + 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, + 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, + 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, + 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, + 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, + 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, + 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, + 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, + 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, + 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, + 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, + 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, + 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, + 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, + 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, + 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, +}; + + +/* Calculate the ECC for a 256-byte block of data */ +void yaffs_ecc_calc(const unsigned char *data, unsigned char *ecc) +{ + unsigned int i; + unsigned char col_parity = 0; + unsigned char line_parity = 0; + unsigned char line_parity_prime = 0; + unsigned char t; + unsigned char b; + + for (i = 0; i < 256; i++) { + b = column_parity_table[*data++]; + col_parity ^= b; + + if (b & 0x01) { /* odd number of bits in the byte */ + line_parity ^= i; + line_parity_prime ^= ~i; + } + } + + ecc[2] = (~col_parity) | 0x03; + + t = 0; + if (line_parity & 0x80) + t |= 0x80; + if (line_parity_prime & 0x80) + t |= 0x40; + if (line_parity & 0x40) + t |= 0x20; + if (line_parity_prime & 0x40) + t |= 0x10; + if (line_parity & 0x20) + t |= 0x08; + if (line_parity_prime & 0x20) + t |= 0x04; + if (line_parity & 0x10) + t |= 0x02; + if (line_parity_prime & 0x10) + t |= 0x01; + ecc[1] = ~t; + + t = 0; + if (line_parity & 0x08) + t |= 0x80; + if (line_parity_prime & 0x08) + t |= 0x40; + if (line_parity & 0x04) + t |= 0x20; + if (line_parity_prime & 0x04) + t |= 0x10; + if (line_parity & 0x02) + t |= 0x08; + if (line_parity_prime & 0x02) + t |= 0x04; + if (line_parity & 0x01) + t |= 0x02; + if (line_parity_prime & 0x01) + t |= 0x01; + ecc[0] = ~t; + +} + +/* Correct the ECC on a 256 byte block of data */ + +int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc, + const unsigned char *test_ecc) +{ + unsigned char d0, d1, d2; /* deltas */ + + d0 = read_ecc[0] ^ test_ecc[0]; + d1 = read_ecc[1] ^ test_ecc[1]; + d2 = read_ecc[2] ^ test_ecc[2]; + + if ((d0 | d1 | d2) == 0) + return 0; /* no error */ + + if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 && + ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 && + ((d2 ^ (d2 >> 1)) & 0x54) == 0x54) { + /* Single bit (recoverable) error in data */ + + unsigned byte; + unsigned bit; + + bit = byte = 0; + + if (d1 & 0x80) + byte |= 0x80; + if (d1 & 0x20) + byte |= 0x40; + if (d1 & 0x08) + byte |= 0x20; + if (d1 & 0x02) + byte |= 0x10; + if (d0 & 0x80) + byte |= 0x08; + if (d0 & 0x20) + byte |= 0x04; + if (d0 & 0x08) + byte |= 0x02; + if (d0 & 0x02) + byte |= 0x01; + + if (d2 & 0x80) + bit |= 0x04; + if (d2 & 0x20) + bit |= 0x02; + if (d2 & 0x08) + bit |= 0x01; + + data[byte] ^= (1 << bit); + + return 1; /* Corrected the error */ + } + + if ((hweight8(d0) + hweight8(d1) + hweight8(d2)) == 1) { + /* Reccoverable error in ecc */ + + read_ecc[0] = test_ecc[0]; + read_ecc[1] = test_ecc[1]; + read_ecc[2] = test_ecc[2]; + + return 1; /* Corrected the error */ + } + + /* Unrecoverable error */ + + return -1; + +} + +/* + * ECCxxxOther does ECC calcs on arbitrary n bytes of data + */ +void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes, + struct yaffs_ecc_other *ecc_other) +{ + unsigned int i; + unsigned char col_parity = 0; + unsigned line_parity = 0; + unsigned line_parity_prime = 0; + unsigned char b; + + for (i = 0; i < n_bytes; i++) { + b = column_parity_table[*data++]; + col_parity ^= b; + + if (b & 0x01) { + /* odd number of bits in the byte */ + line_parity ^= i; + line_parity_prime ^= ~i; + } + + } + + ecc_other->col_parity = (col_parity >> 2) & 0x3f; + ecc_other->line_parity = line_parity; + ecc_other->line_parity_prime = line_parity_prime; +} + +int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes, + struct yaffs_ecc_other *read_ecc, + const struct yaffs_ecc_other *test_ecc) +{ + unsigned char delta_col; /* column parity delta */ + unsigned delta_line; /* line parity delta */ + unsigned delta_line_prime; /* line parity delta */ + unsigned bit; + + delta_col = read_ecc->col_parity ^ test_ecc->col_parity; + delta_line = read_ecc->line_parity ^ test_ecc->line_parity; + delta_line_prime = + read_ecc->line_parity_prime ^ test_ecc->line_parity_prime; + + if ((delta_col | delta_line | delta_line_prime) == 0) + return 0; /* no error */ + + if (delta_line == ~delta_line_prime && + (((delta_col ^ (delta_col >> 1)) & 0x15) == 0x15)) { + /* Single bit (recoverable) error in data */ + + bit = 0; + + if (delta_col & 0x20) + bit |= 0x04; + if (delta_col & 0x08) + bit |= 0x02; + if (delta_col & 0x02) + bit |= 0x01; + + if (delta_line >= n_bytes) + return -1; + + data[delta_line] ^= (1 << bit); + + return 1; /* corrected */ + } + + if ((hweight32(delta_line) + + hweight32(delta_line_prime) + + hweight8(delta_col)) == 1) { + /* Reccoverable error in ecc */ + + *read_ecc = *test_ecc; + return 1; /* corrected */ + } + + /* Unrecoverable error */ + + return -1; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_ecc.h b/target/linux/generic/files/fs/yaffs2/yaffs_ecc.h new file mode 100644 index 0000000..17d47bd --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_ecc.h @@ -0,0 +1,44 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +/* + * This code implements the ECC algorithm used in SmartMedia. + * + * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. + * The two unused bit are set to 1. + * The ECC can correct single bit errors in a 256-byte page of data. + * Thus, two such ECC blocks are used on a 512-byte NAND page. + * + */ + +#ifndef __YAFFS_ECC_H__ +#define __YAFFS_ECC_H__ + +struct yaffs_ecc_other { + unsigned char col_parity; + unsigned line_parity; + unsigned line_parity_prime; +}; + +void yaffs_ecc_calc(const unsigned char *data, unsigned char *ecc); +int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc, + const unsigned char *test_ecc); + +void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes, + struct yaffs_ecc_other *ecc); +int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes, + struct yaffs_ecc_other *read_ecc, + const struct yaffs_ecc_other *test_ecc); +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_getblockinfo.h b/target/linux/generic/files/fs/yaffs2/yaffs_getblockinfo.h new file mode 100644 index 0000000..8fd0802 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_getblockinfo.h @@ -0,0 +1,35 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_GETBLOCKINFO_H__ +#define __YAFFS_GETBLOCKINFO_H__ + +#include "yaffs_guts.h" +#include "yaffs_trace.h" + +/* Function to manipulate block info */ +static inline struct yaffs_block_info *yaffs_get_block_info(struct yaffs_dev + *dev, int blk) +{ + if (blk < dev->internal_start_block || blk > dev->internal_end_block) { + yaffs_trace(YAFFS_TRACE_ERROR, + "**>> yaffs: get_block_info block %d is not valid", + blk); + BUG(); + } + return &dev->block_info[blk - dev->internal_start_block]; +} + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_guts.c b/target/linux/generic/files/fs/yaffs2/yaffs_guts.c new file mode 100644 index 0000000..89fb2a9 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_guts.c @@ -0,0 +1,5140 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yportenv.h" +#include "yaffs_trace.h" + +#include "yaffs_guts.h" +#include "yaffs_getblockinfo.h" +#include "yaffs_tagscompat.h" +#include "yaffs_tagsmarshall.h" +#include "yaffs_nand.h" +#include "yaffs_yaffs1.h" +#include "yaffs_yaffs2.h" +#include "yaffs_bitmap.h" +#include "yaffs_verify.h" +#include "yaffs_nand.h" +#include "yaffs_packedtags2.h" +#include "yaffs_nameval.h" +#include "yaffs_allocator.h" +#include "yaffs_attribs.h" +#include "yaffs_summary.h" + +/* Note YAFFS_GC_GOOD_ENOUGH must be <= YAFFS_GC_PASSIVE_THRESHOLD */ +#define YAFFS_GC_GOOD_ENOUGH 2 +#define YAFFS_GC_PASSIVE_THRESHOLD 4 + +#include "yaffs_ecc.h" + +/* Forward declarations */ + +static int yaffs_wr_data_obj(struct yaffs_obj *in, int inode_chunk, + const u8 *buffer, int n_bytes, int use_reserve); + +static void yaffs_fix_null_name(struct yaffs_obj *obj, YCHAR *name, + int buffer_size); + +/* Function to calculate chunk and offset */ + +void yaffs_addr_to_chunk(struct yaffs_dev *dev, loff_t addr, + int *chunk_out, u32 *offset_out) +{ + int chunk; + u32 offset; + + chunk = (u32) (addr >> dev->chunk_shift); + + if (dev->chunk_div == 1) { + /* easy power of 2 case */ + offset = (u32) (addr & dev->chunk_mask); + } else { + /* Non power-of-2 case */ + + loff_t chunk_base; + + chunk /= dev->chunk_div; + + chunk_base = ((loff_t) chunk) * dev->data_bytes_per_chunk; + offset = (u32) (addr - chunk_base); + } + + *chunk_out = chunk; + *offset_out = offset; +} + +/* Function to return the number of shifts for a power of 2 greater than or + * equal to the given number + * Note we don't try to cater for all possible numbers and this does not have to + * be hellishly efficient. + */ + +static inline u32 calc_shifts_ceiling(u32 x) +{ + int extra_bits; + int shifts; + + shifts = extra_bits = 0; + + while (x > 1) { + if (x & 1) + extra_bits++; + x >>= 1; + shifts++; + } + + if (extra_bits) + shifts++; + + return shifts; +} + +/* Function to return the number of shifts to get a 1 in bit 0 + */ + +static inline u32 calc_shifts(u32 x) +{ + u32 shifts; + + shifts = 0; + + if (!x) + return 0; + + while (!(x & 1)) { + x >>= 1; + shifts++; + } + + return shifts; +} + +/* + * Temporary buffer manipulations. + */ + +static int yaffs_init_tmp_buffers(struct yaffs_dev *dev) +{ + int i; + u8 *buf = (u8 *) 1; + + memset(dev->temp_buffer, 0, sizeof(dev->temp_buffer)); + + for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) { + dev->temp_buffer[i].in_use = 0; + buf = kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS); + dev->temp_buffer[i].buffer = buf; + } + + return buf ? YAFFS_OK : YAFFS_FAIL; +} + +u8 *yaffs_get_temp_buffer(struct yaffs_dev * dev) +{ + int i; + + dev->temp_in_use++; + if (dev->temp_in_use > dev->max_temp) + dev->max_temp = dev->temp_in_use; + + for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { + if (dev->temp_buffer[i].in_use == 0) { + dev->temp_buffer[i].in_use = 1; + return dev->temp_buffer[i].buffer; + } + } + + yaffs_trace(YAFFS_TRACE_BUFFERS, "Out of temp buffers"); + /* + * If we got here then we have to allocate an unmanaged one + * This is not good. + */ + + dev->unmanaged_buffer_allocs++; + return kmalloc(dev->data_bytes_per_chunk, GFP_NOFS); + +} + +void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 *buffer) +{ + int i; + + dev->temp_in_use--; + + for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { + if (dev->temp_buffer[i].buffer == buffer) { + dev->temp_buffer[i].in_use = 0; + return; + } + } + + if (buffer) { + /* assume it is an unmanaged one. */ + yaffs_trace(YAFFS_TRACE_BUFFERS, + "Releasing unmanaged temp buffer"); + kfree(buffer); + dev->unmanaged_buffer_deallocs++; + } + +} + +/* + * Functions for robustisizing TODO + * + */ + +static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk, + const u8 *data, + const struct yaffs_ext_tags *tags) +{ + (void) dev; + (void) nand_chunk; + (void) data; + (void) tags; +} + +static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk, + const struct yaffs_ext_tags *tags) +{ + (void) dev; + (void) nand_chunk; + (void) tags; +} + +void yaffs_handle_chunk_error(struct yaffs_dev *dev, + struct yaffs_block_info *bi) +{ + if (!bi->gc_prioritise) { + bi->gc_prioritise = 1; + dev->has_pending_prioritised_gc = 1; + bi->chunk_error_strikes++; + + if (bi->chunk_error_strikes > 3) { + bi->needs_retiring = 1; /* Too many stikes, so retire */ + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs: Block struck out"); + + } + } +} + +static void yaffs_handle_chunk_wr_error(struct yaffs_dev *dev, int nand_chunk, + int erased_ok) +{ + int flash_block = nand_chunk / dev->param.chunks_per_block; + struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block); + + yaffs_handle_chunk_error(dev, bi); + + if (erased_ok) { + /* Was an actual write failure, + * so mark the block for retirement.*/ + bi->needs_retiring = 1; + yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, + "**>> Block %d needs retiring", flash_block); + } + + /* Delete the chunk */ + yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); + yaffs_skip_rest_of_block(dev); +} + +/* + * Verification code + */ + +/* + * Simple hash function. Needs to have a reasonable spread + */ + +static inline int yaffs_hash_fn(int n) +{ + if (n < 0) + n = -n; + return n % YAFFS_NOBJECT_BUCKETS; +} + +/* + * Access functions to useful fake objects. + * Note that root might have a presence in NAND if permissions are set. + */ + +struct yaffs_obj *yaffs_root(struct yaffs_dev *dev) +{ + return dev->root_dir; +} + +struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev) +{ + return dev->lost_n_found; +} + +/* + * Erased NAND checking functions + */ + +int yaffs_check_ff(u8 *buffer, int n_bytes) +{ + /* Horrible, slow implementation */ + while (n_bytes--) { + if (*buffer != 0xff) + return 0; + buffer++; + } + return 1; +} + +static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk) +{ + int retval = YAFFS_OK; + u8 *data = yaffs_get_temp_buffer(dev); + struct yaffs_ext_tags tags; + int result; + + result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags); + + if (tags.ecc_result > YAFFS_ECC_RESULT_NO_ERROR) + retval = YAFFS_FAIL; + + if (!yaffs_check_ff(data, dev->data_bytes_per_chunk) || + tags.chunk_used) { + yaffs_trace(YAFFS_TRACE_NANDACCESS, + "Chunk %d not erased", nand_chunk); + retval = YAFFS_FAIL; + } + + yaffs_release_temp_buffer(dev, data); + + return retval; + +} + +static int yaffs_verify_chunk_written(struct yaffs_dev *dev, + int nand_chunk, + const u8 *data, + struct yaffs_ext_tags *tags) +{ + int retval = YAFFS_OK; + struct yaffs_ext_tags temp_tags; + u8 *buffer = yaffs_get_temp_buffer(dev); + int result; + + result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags); + if (memcmp(buffer, data, dev->data_bytes_per_chunk) || + temp_tags.obj_id != tags->obj_id || + temp_tags.chunk_id != tags->chunk_id || + temp_tags.n_bytes != tags->n_bytes) + retval = YAFFS_FAIL; + + yaffs_release_temp_buffer(dev, buffer); + + return retval; +} + + +int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks) +{ + int reserved_chunks; + int reserved_blocks = dev->param.n_reserved_blocks; + int checkpt_blocks; + + checkpt_blocks = yaffs_calc_checkpt_blocks_required(dev); + + reserved_chunks = + (reserved_blocks + checkpt_blocks) * dev->param.chunks_per_block; + + return (dev->n_free_chunks > (reserved_chunks + n_chunks)); +} + +static int yaffs_find_alloc_block(struct yaffs_dev *dev) +{ + int i; + struct yaffs_block_info *bi; + + if (dev->n_erased_blocks < 1) { + /* Hoosterman we've got a problem. + * Can't get space to gc + */ + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs tragedy: no more erased blocks"); + + return -1; + } + + /* Find an empty block. */ + + for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { + dev->alloc_block_finder++; + if (dev->alloc_block_finder < dev->internal_start_block + || dev->alloc_block_finder > dev->internal_end_block) { + dev->alloc_block_finder = dev->internal_start_block; + } + + bi = yaffs_get_block_info(dev, dev->alloc_block_finder); + + if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { + bi->block_state = YAFFS_BLOCK_STATE_ALLOCATING; + dev->seq_number++; + bi->seq_number = dev->seq_number; + dev->n_erased_blocks--; + yaffs_trace(YAFFS_TRACE_ALLOCATE, + "Allocated block %d, seq %d, %d left" , + dev->alloc_block_finder, dev->seq_number, + dev->n_erased_blocks); + return dev->alloc_block_finder; + } + } + + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs tragedy: no more erased blocks, but there should have been %d", + dev->n_erased_blocks); + + return -1; +} + +static int yaffs_alloc_chunk(struct yaffs_dev *dev, int use_reserver, + struct yaffs_block_info **block_ptr) +{ + int ret_val; + struct yaffs_block_info *bi; + + if (dev->alloc_block < 0) { + /* Get next block to allocate off */ + dev->alloc_block = yaffs_find_alloc_block(dev); + dev->alloc_page = 0; + } + + if (!use_reserver && !yaffs_check_alloc_available(dev, 1)) { + /* No space unless we're allowed to use the reserve. */ + return -1; + } + + if (dev->n_erased_blocks < dev->param.n_reserved_blocks + && dev->alloc_page == 0) + yaffs_trace(YAFFS_TRACE_ALLOCATE, "Allocating reserve"); + + /* Next page please.... */ + if (dev->alloc_block >= 0) { + bi = yaffs_get_block_info(dev, dev->alloc_block); + + ret_val = (dev->alloc_block * dev->param.chunks_per_block) + + dev->alloc_page; + bi->pages_in_use++; + yaffs_set_chunk_bit(dev, dev->alloc_block, dev->alloc_page); + + dev->alloc_page++; + + dev->n_free_chunks--; + + /* If the block is full set the state to full */ + if (dev->alloc_page >= dev->param.chunks_per_block) { + bi->block_state = YAFFS_BLOCK_STATE_FULL; + dev->alloc_block = -1; + } + + if (block_ptr) + *block_ptr = bi; + + return ret_val; + } + + yaffs_trace(YAFFS_TRACE_ERROR, + "!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!"); + + return -1; +} + +static int yaffs_get_erased_chunks(struct yaffs_dev *dev) +{ + int n; + + n = dev->n_erased_blocks * dev->param.chunks_per_block; + + if (dev->alloc_block > 0) + n += (dev->param.chunks_per_block - dev->alloc_page); + + return n; + +} + +/* + * yaffs_skip_rest_of_block() skips over the rest of the allocation block + * if we don't want to write to it. + */ +void yaffs_skip_rest_of_block(struct yaffs_dev *dev) +{ + struct yaffs_block_info *bi; + + if (dev->alloc_block > 0) { + bi = yaffs_get_block_info(dev, dev->alloc_block); + if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING) { + bi->block_state = YAFFS_BLOCK_STATE_FULL; + dev->alloc_block = -1; + } + } +} + +static int yaffs_write_new_chunk(struct yaffs_dev *dev, + const u8 *data, + struct yaffs_ext_tags *tags, int use_reserver) +{ + int attempts = 0; + int write_ok = 0; + int chunk; + + yaffs2_checkpt_invalidate(dev); + + do { + struct yaffs_block_info *bi = 0; + int erased_ok = 0; + + chunk = yaffs_alloc_chunk(dev, use_reserver, &bi); + if (chunk < 0) { + /* no space */ + break; + } + + /* First check this chunk is erased, if it needs + * checking. The checking policy (unless forced + * always on) is as follows: + * + * Check the first page we try to write in a block. + * If the check passes then we don't need to check any + * more. If the check fails, we check again... + * If the block has been erased, we don't need to check. + * + * However, if the block has been prioritised for gc, + * then we think there might be something odd about + * this block and stop using it. + * + * Rationale: We should only ever see chunks that have + * not been erased if there was a partially written + * chunk due to power loss. This checking policy should + * catch that case with very few checks and thus save a + * lot of checks that are most likely not needed. + * + * Mods to the above + * If an erase check fails or the write fails we skip the + * rest of the block. + */ + + /* let's give it a try */ + attempts++; + + if (dev->param.always_check_erased) + bi->skip_erased_check = 0; + + if (!bi->skip_erased_check) { + erased_ok = yaffs_check_chunk_erased(dev, chunk); + if (erased_ok != YAFFS_OK) { + yaffs_trace(YAFFS_TRACE_ERROR, + "**>> yaffs chunk %d was not erased", + chunk); + + /* If not erased, delete this one, + * skip rest of block and + * try another chunk */ + yaffs_chunk_del(dev, chunk, 1, __LINE__); + yaffs_skip_rest_of_block(dev); + continue; + } + } + + write_ok = yaffs_wr_chunk_tags_nand(dev, chunk, data, tags); + + if (!bi->skip_erased_check) + write_ok = + yaffs_verify_chunk_written(dev, chunk, data, tags); + + if (write_ok != YAFFS_OK) { + /* Clean up aborted write, skip to next block and + * try another chunk */ + yaffs_handle_chunk_wr_error(dev, chunk, erased_ok); + continue; + } + + bi->skip_erased_check = 1; + + /* Copy the data into the robustification buffer */ + yaffs_handle_chunk_wr_ok(dev, chunk, data, tags); + + } while (write_ok != YAFFS_OK && + (yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts)); + + if (!write_ok) + chunk = -1; + + if (attempts > 1) { + yaffs_trace(YAFFS_TRACE_ERROR, + "**>> yaffs write required %d attempts", + attempts); + dev->n_retried_writes += (attempts - 1); + } + + return chunk; +} + +/* + * Block retiring for handling a broken block. + */ + +static void yaffs_retire_block(struct yaffs_dev *dev, int flash_block) +{ + struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block); + + yaffs2_checkpt_invalidate(dev); + + yaffs2_clear_oldest_dirty_seq(dev, bi); + + if (yaffs_mark_bad(dev, flash_block) != YAFFS_OK) { + if (yaffs_erase_block(dev, flash_block) != YAFFS_OK) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs: Failed to mark bad and erase block %d", + flash_block); + } else { + struct yaffs_ext_tags tags; + int chunk_id = + flash_block * dev->param.chunks_per_block; + + u8 *buffer = yaffs_get_temp_buffer(dev); + + memset(buffer, 0xff, dev->data_bytes_per_chunk); + memset(&tags, 0, sizeof(tags)); + tags.seq_number = YAFFS_SEQUENCE_BAD_BLOCK; + if (dev->tagger.write_chunk_tags_fn(dev, chunk_id - + dev->chunk_offset, + buffer, + &tags) != YAFFS_OK) + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs: Failed to write bad block marker to block %d", + flash_block); + + yaffs_release_temp_buffer(dev, buffer); + } + } + + bi->block_state = YAFFS_BLOCK_STATE_DEAD; + bi->gc_prioritise = 0; + bi->needs_retiring = 0; + + dev->n_retired_blocks++; +} + +/*---------------- Name handling functions ------------*/ + +static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR *name, + const YCHAR *oh_name, int buff_size) +{ +#ifdef CONFIG_YAFFS_AUTO_UNICODE + if (dev->param.auto_unicode) { + if (*oh_name) { + /* It is an ASCII name, do an ASCII to + * unicode conversion */ + const char *ascii_oh_name = (const char *)oh_name; + int n = buff_size - 1; + while (n > 0 && *ascii_oh_name) { + *name = *ascii_oh_name; + name++; + ascii_oh_name++; + n--; + } + } else { + strncpy(name, oh_name + 1, buff_size - 1); + } + } else { +#else + (void) dev; + { +#endif + strncpy(name, oh_name, buff_size - 1); + } +} + +static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR *oh_name, + const YCHAR *name) +{ +#ifdef CONFIG_YAFFS_AUTO_UNICODE + + int is_ascii; + const YCHAR *w; + + if (dev->param.auto_unicode) { + + is_ascii = 1; + w = name; + + /* Figure out if the name will fit in ascii character set */ + while (is_ascii && *w) { + if ((*w) & 0xff00) + is_ascii = 0; + w++; + } + + if (is_ascii) { + /* It is an ASCII name, so convert unicode to ascii */ + char *ascii_oh_name = (char *)oh_name; + int n = YAFFS_MAX_NAME_LENGTH - 1; + while (n > 0 && *name) { + *ascii_oh_name = *name; + name++; + ascii_oh_name++; + n--; + } + } else { + /* Unicode name, so save starting at the second YCHAR */ + *oh_name = 0; + strncpy(oh_name + 1, name, YAFFS_MAX_NAME_LENGTH - 2); + } + } else { +#else + dev = dev; + { +#endif + strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1); + } +} + +static u16 yaffs_calc_name_sum(const YCHAR *name) +{ + u16 sum = 0; + u16 i = 1; + + if (!name) + return 0; + + while ((*name) && i < (YAFFS_MAX_NAME_LENGTH / 2)) { + + /* 0x1f mask is case insensitive */ + sum += ((*name) & 0x1f) * i; + i++; + name++; + } + return sum; +} + + +void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR * name) +{ + memset(obj->short_name, 0, sizeof(obj->short_name)); + + if (name && !name[0]) { + yaffs_fix_null_name(obj, obj->short_name, + YAFFS_SHORT_NAME_LENGTH); + name = obj->short_name; + } else if (name && + strnlen(name, YAFFS_SHORT_NAME_LENGTH + 1) <= + YAFFS_SHORT_NAME_LENGTH) { + strcpy(obj->short_name, name); + } + + obj->sum = yaffs_calc_name_sum(name); +} + +void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj, + const struct yaffs_obj_hdr *oh) +{ +#ifdef CONFIG_YAFFS_AUTO_UNICODE + YCHAR tmp_name[YAFFS_MAX_NAME_LENGTH + 1]; + memset(tmp_name, 0, sizeof(tmp_name)); + yaffs_load_name_from_oh(obj->my_dev, tmp_name, oh->name, + YAFFS_MAX_NAME_LENGTH + 1); + yaffs_set_obj_name(obj, tmp_name); +#else + yaffs_set_obj_name(obj, oh->name); +#endif +} + +loff_t yaffs_max_file_size(struct yaffs_dev *dev) +{ + if(sizeof(loff_t) < 8) + return YAFFS_MAX_FILE_SIZE_32; + else + return ((loff_t) YAFFS_MAX_CHUNK_ID) * dev->data_bytes_per_chunk; +} + +/*-------------------- TNODES ------------------- + + * List of spare tnodes + * The list is hooked together using the first pointer + * in the tnode. + */ + +struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev) +{ + struct yaffs_tnode *tn = yaffs_alloc_raw_tnode(dev); + + if (tn) { + memset(tn, 0, dev->tnode_size); + dev->n_tnodes++; + } + + dev->checkpoint_blocks_required = 0; /* force recalculation */ + + return tn; +} + +/* FreeTnode frees up a tnode and puts it back on the free list */ +static void yaffs_free_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) +{ + yaffs_free_raw_tnode(dev, tn); + dev->n_tnodes--; + dev->checkpoint_blocks_required = 0; /* force recalculation */ +} + +static void yaffs_deinit_tnodes_and_objs(struct yaffs_dev *dev) +{ + yaffs_deinit_raw_tnodes_and_objs(dev); + dev->n_obj = 0; + dev->n_tnodes = 0; +} + +static void yaffs_load_tnode_0(struct yaffs_dev *dev, struct yaffs_tnode *tn, + unsigned pos, unsigned val) +{ + u32 *map = (u32 *) tn; + u32 bit_in_map; + u32 bit_in_word; + u32 word_in_map; + u32 mask; + + pos &= YAFFS_TNODES_LEVEL0_MASK; + val >>= dev->chunk_grp_bits; + + bit_in_map = pos * dev->tnode_width; + word_in_map = bit_in_map / 32; + bit_in_word = bit_in_map & (32 - 1); + + mask = dev->tnode_mask << bit_in_word; + + map[word_in_map] &= ~mask; + map[word_in_map] |= (mask & (val << bit_in_word)); + + if (dev->tnode_width > (32 - bit_in_word)) { + bit_in_word = (32 - bit_in_word); + word_in_map++; + mask = + dev->tnode_mask >> bit_in_word; + map[word_in_map] &= ~mask; + map[word_in_map] |= (mask & (val >> bit_in_word)); + } +} + +u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn, + unsigned pos) +{ + u32 *map = (u32 *) tn; + u32 bit_in_map; + u32 bit_in_word; + u32 word_in_map; + u32 val; + + pos &= YAFFS_TNODES_LEVEL0_MASK; + + bit_in_map = pos * dev->tnode_width; + word_in_map = bit_in_map / 32; + bit_in_word = bit_in_map & (32 - 1); + + val = map[word_in_map] >> bit_in_word; + + if (dev->tnode_width > (32 - bit_in_word)) { + bit_in_word = (32 - bit_in_word); + word_in_map++; + val |= (map[word_in_map] << bit_in_word); + } + + val &= dev->tnode_mask; + val <<= dev->chunk_grp_bits; + + return val; +} + +/* ------------------- End of individual tnode manipulation -----------------*/ + +/* ---------Functions to manipulate the look-up tree (made up of tnodes) ------ + * The look up tree is represented by the top tnode and the number of top_level + * in the tree. 0 means only the level 0 tnode is in the tree. + */ + +/* FindLevel0Tnode finds the level 0 tnode, if one exists. */ +struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, + struct yaffs_file_var *file_struct, + u32 chunk_id) +{ + struct yaffs_tnode *tn = file_struct->top; + u32 i; + int required_depth; + int level = file_struct->top_level; + + (void) dev; + + /* Check sane level and chunk Id */ + if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL) + return NULL; + + if (chunk_id > YAFFS_MAX_CHUNK_ID) + return NULL; + + /* First check we're tall enough (ie enough top_level) */ + + i = chunk_id >> YAFFS_TNODES_LEVEL0_BITS; + required_depth = 0; + while (i) { + i >>= YAFFS_TNODES_INTERNAL_BITS; + required_depth++; + } + + if (required_depth > file_struct->top_level) + return NULL; /* Not tall enough, so we can't find it */ + + /* Traverse down to level 0 */ + while (level > 0 && tn) { + tn = tn->internal[(chunk_id >> + (YAFFS_TNODES_LEVEL0_BITS + + (level - 1) * + YAFFS_TNODES_INTERNAL_BITS)) & + YAFFS_TNODES_INTERNAL_MASK]; + level--; + } + + return tn; +} + +/* add_find_tnode_0 finds the level 0 tnode if it exists, + * otherwise first expands the tree. + * This happens in two steps: + * 1. If the tree isn't tall enough, then make it taller. + * 2. Scan down the tree towards the level 0 tnode adding tnodes if required. + * + * Used when modifying the tree. + * + * If the tn argument is NULL, then a fresh tnode will be added otherwise the + * specified tn will be plugged into the ttree. + */ + +struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev, + struct yaffs_file_var *file_struct, + u32 chunk_id, + struct yaffs_tnode *passed_tn) +{ + int required_depth; + int i; + int l; + struct yaffs_tnode *tn; + u32 x; + + /* Check sane level and page Id */ + if (file_struct->top_level < 0 || + file_struct->top_level > YAFFS_TNODES_MAX_LEVEL) + return NULL; + + if (chunk_id > YAFFS_MAX_CHUNK_ID) + return NULL; + + /* First check we're tall enough (ie enough top_level) */ + + x = chunk_id >> YAFFS_TNODES_LEVEL0_BITS; + required_depth = 0; + while (x) { + x >>= YAFFS_TNODES_INTERNAL_BITS; + required_depth++; + } + + if (required_depth > file_struct->top_level) { + /* Not tall enough, gotta make the tree taller */ + for (i = file_struct->top_level; i < required_depth; i++) { + + tn = yaffs_get_tnode(dev); + + if (tn) { + tn->internal[0] = file_struct->top; + file_struct->top = tn; + file_struct->top_level++; + } else { + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs: no more tnodes"); + return NULL; + } + } + } + + /* Traverse down to level 0, adding anything we need */ + + l = file_struct->top_level; + tn = file_struct->top; + + if (l > 0) { + while (l > 0 && tn) { + x = (chunk_id >> + (YAFFS_TNODES_LEVEL0_BITS + + (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) & + YAFFS_TNODES_INTERNAL_MASK; + + if ((l > 1) && !tn->internal[x]) { + /* Add missing non-level-zero tnode */ + tn->internal[x] = yaffs_get_tnode(dev); + if (!tn->internal[x]) + return NULL; + } else if (l == 1) { + /* Looking from level 1 at level 0 */ + if (passed_tn) { + /* If we already have one, release it */ + if (tn->internal[x]) + yaffs_free_tnode(dev, + tn->internal[x]); + tn->internal[x] = passed_tn; + + } else if (!tn->internal[x]) { + /* Don't have one, none passed in */ + tn->internal[x] = yaffs_get_tnode(dev); + if (!tn->internal[x]) + return NULL; + } + } + + tn = tn->internal[x]; + l--; + } + } else { + /* top is level 0 */ + if (passed_tn) { + memcpy(tn, passed_tn, + (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8); + yaffs_free_tnode(dev, passed_tn); + } + } + + return tn; +} + +static int yaffs_tags_match(const struct yaffs_ext_tags *tags, int obj_id, + int chunk_obj) +{ + return (tags->chunk_id == chunk_obj && + tags->obj_id == obj_id && + !tags->is_deleted) ? 1 : 0; + +} + +static int yaffs_find_chunk_in_group(struct yaffs_dev *dev, int the_chunk, + struct yaffs_ext_tags *tags, int obj_id, + int inode_chunk) +{ + int j; + + for (j = 0; the_chunk && j < dev->chunk_grp_size; j++) { + if (yaffs_check_chunk_bit + (dev, the_chunk / dev->param.chunks_per_block, + the_chunk % dev->param.chunks_per_block)) { + + if (dev->chunk_grp_size == 1) + return the_chunk; + else { + yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL, + tags); + if (yaffs_tags_match(tags, + obj_id, inode_chunk)) { + /* found it; */ + return the_chunk; + } + } + } + the_chunk++; + } + return -1; +} + +int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk, + struct yaffs_ext_tags *tags) +{ + /*Get the Tnode, then get the level 0 offset chunk offset */ + struct yaffs_tnode *tn; + int the_chunk = -1; + struct yaffs_ext_tags local_tags; + int ret_val = -1; + struct yaffs_dev *dev = in->my_dev; + + if (!tags) { + /* Passed a NULL, so use our own tags space */ + tags = &local_tags; + } + + tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk); + + if (!tn) + return ret_val; + + the_chunk = yaffs_get_group_base(dev, tn, inode_chunk); + + ret_val = yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id, + inode_chunk); + return ret_val; +} + +static int yaffs_find_del_file_chunk(struct yaffs_obj *in, int inode_chunk, + struct yaffs_ext_tags *tags) +{ + /* Get the Tnode, then get the level 0 offset chunk offset */ + struct yaffs_tnode *tn; + int the_chunk = -1; + struct yaffs_ext_tags local_tags; + struct yaffs_dev *dev = in->my_dev; + int ret_val = -1; + + if (!tags) { + /* Passed a NULL, so use our own tags space */ + tags = &local_tags; + } + + tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk); + + if (!tn) + return ret_val; + + the_chunk = yaffs_get_group_base(dev, tn, inode_chunk); + + ret_val = yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id, + inode_chunk); + + /* Delete the entry in the filestructure (if found) */ + if (ret_val != -1) + yaffs_load_tnode_0(dev, tn, inode_chunk, 0); + + return ret_val; +} + +int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk, + int nand_chunk, int in_scan) +{ + /* NB in_scan is zero unless scanning. + * For forward scanning, in_scan is > 0; + * for backward scanning in_scan is < 0 + * + * nand_chunk = 0 is a dummy insert to make sure the tnodes are there. + */ + + struct yaffs_tnode *tn; + struct yaffs_dev *dev = in->my_dev; + int existing_cunk; + struct yaffs_ext_tags existing_tags; + struct yaffs_ext_tags new_tags; + unsigned existing_serial, new_serial; + + if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) { + /* Just ignore an attempt at putting a chunk into a non-file + * during scanning. + * If it is not during Scanning then something went wrong! + */ + if (!in_scan) { + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs tragedy:attempt to put data chunk into a non-file" + ); + BUG(); + } + + yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); + return YAFFS_OK; + } + + tn = yaffs_add_find_tnode_0(dev, + &in->variant.file_variant, + inode_chunk, NULL); + if (!tn) + return YAFFS_FAIL; + + if (!nand_chunk) + /* Dummy insert, bail now */ + return YAFFS_OK; + + existing_cunk = yaffs_get_group_base(dev, tn, inode_chunk); + + if (in_scan != 0) { + /* If we're scanning then we need to test for duplicates + * NB This does not need to be efficient since it should only + * happen when the power fails during a write, then only one + * chunk should ever be affected. + * + * Correction for YAFFS2: This could happen quite a lot and we + * need to think about efficiency! TODO + * Update: For backward scanning we don't need to re-read tags + * so this is quite cheap. + */ + + if (existing_cunk > 0) { + /* NB Right now existing chunk will not be real + * chunk_id if the chunk group size > 1 + * thus we have to do a FindChunkInFile to get the + * real chunk id. + * + * We have a duplicate now we need to decide which + * one to use: + * + * Backwards scanning YAFFS2: The old one is what + * we use, dump the new one. + * YAFFS1: Get both sets of tags and compare serial + * numbers. + */ + + if (in_scan > 0) { + /* Only do this for forward scanning */ + yaffs_rd_chunk_tags_nand(dev, + nand_chunk, + NULL, &new_tags); + + /* Do a proper find */ + existing_cunk = + yaffs_find_chunk_in_file(in, inode_chunk, + &existing_tags); + } + + if (existing_cunk <= 0) { + /*Hoosterman - how did this happen? */ + + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs tragedy: existing chunk < 0 in scan" + ); + + } + + /* NB The deleted flags should be false, otherwise + * the chunks will not be loaded during a scan + */ + + if (in_scan > 0) { + new_serial = new_tags.serial_number; + existing_serial = existing_tags.serial_number; + } + + if ((in_scan > 0) && + (existing_cunk <= 0 || + ((existing_serial + 1) & 3) == new_serial)) { + /* Forward scanning. + * Use new + * Delete the old one and drop through to + * update the tnode + */ + yaffs_chunk_del(dev, existing_cunk, 1, + __LINE__); + } else { + /* Backward scanning or we want to use the + * existing one + * Delete the new one and return early so that + * the tnode isn't changed + */ + yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); + return YAFFS_OK; + } + } + + } + + if (existing_cunk == 0) + in->n_data_chunks++; + + yaffs_load_tnode_0(dev, tn, inode_chunk, nand_chunk); + + return YAFFS_OK; +} + +static void yaffs_soft_del_chunk(struct yaffs_dev *dev, int chunk) +{ + struct yaffs_block_info *the_block; + unsigned block_no; + + yaffs_trace(YAFFS_TRACE_DELETION, "soft delete chunk %d", chunk); + + block_no = chunk / dev->param.chunks_per_block; + the_block = yaffs_get_block_info(dev, block_no); + if (the_block) { + the_block->soft_del_pages++; + dev->n_free_chunks++; + yaffs2_update_oldest_dirty_seq(dev, block_no, the_block); + } +} + +/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all + * the chunks in the file. + * All soft deleting does is increment the block's softdelete count and pulls + * the chunk out of the tnode. + * Thus, essentially this is the same as DeleteWorker except that the chunks + * are soft deleted. + */ + +static int yaffs_soft_del_worker(struct yaffs_obj *in, struct yaffs_tnode *tn, + u32 level, int chunk_offset) +{ + int i; + int the_chunk; + int all_done = 1; + struct yaffs_dev *dev = in->my_dev; + + if (!tn) + return 1; + + if (level > 0) { + for (i = YAFFS_NTNODES_INTERNAL - 1; + all_done && i >= 0; + i--) { + if (tn->internal[i]) { + all_done = + yaffs_soft_del_worker(in, + tn->internal[i], + level - 1, + (chunk_offset << + YAFFS_TNODES_INTERNAL_BITS) + + i); + if (all_done) { + yaffs_free_tnode(dev, + tn->internal[i]); + tn->internal[i] = NULL; + } else { + /* Can this happen? */ + } + } + } + return (all_done) ? 1 : 0; + } + + /* level 0 */ + for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) { + the_chunk = yaffs_get_group_base(dev, tn, i); + if (the_chunk) { + yaffs_soft_del_chunk(dev, the_chunk); + yaffs_load_tnode_0(dev, tn, i, 0); + } + } + return 1; +} + +static void yaffs_remove_obj_from_dir(struct yaffs_obj *obj) +{ + struct yaffs_dev *dev = obj->my_dev; + struct yaffs_obj *parent; + + yaffs_verify_obj_in_dir(obj); + parent = obj->parent; + + yaffs_verify_dir(parent); + + if (dev && dev->param.remove_obj_fn) + dev->param.remove_obj_fn(obj); + + list_del_init(&obj->siblings); + obj->parent = NULL; + + yaffs_verify_dir(parent); +} + +void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj) +{ + if (!directory) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "tragedy: Trying to add an object to a null pointer directory" + ); + BUG(); + return; + } + if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "tragedy: Trying to add an object to a non-directory" + ); + BUG(); + } + + if (obj->siblings.prev == NULL) { + /* Not initialised */ + BUG(); + } + + yaffs_verify_dir(directory); + + yaffs_remove_obj_from_dir(obj); + + /* Now add it */ + list_add(&obj->siblings, &directory->variant.dir_variant.children); + obj->parent = directory; + + if (directory == obj->my_dev->unlinked_dir + || directory == obj->my_dev->del_dir) { + obj->unlinked = 1; + obj->my_dev->n_unlinked_files++; + obj->rename_allowed = 0; + } + + yaffs_verify_dir(directory); + yaffs_verify_obj_in_dir(obj); +} + +static int yaffs_change_obj_name(struct yaffs_obj *obj, + struct yaffs_obj *new_dir, + const YCHAR *new_name, int force, int shadows) +{ + int unlink_op; + int del_op; + struct yaffs_obj *existing_target; + + if (new_dir == NULL) + new_dir = obj->parent; /* use the old directory */ + + if (new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "tragedy: yaffs_change_obj_name: new_dir is not a directory" + ); + BUG(); + } + + unlink_op = (new_dir == obj->my_dev->unlinked_dir); + del_op = (new_dir == obj->my_dev->del_dir); + + existing_target = yaffs_find_by_name(new_dir, new_name); + + /* If the object is a file going into the unlinked directory, + * then it is OK to just stuff it in since duplicate names are OK. + * else only proceed if the new name does not exist and we're putting + * it into a directory. + */ + if (!(unlink_op || del_op || force || + shadows > 0 || !existing_target) || + new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) + return YAFFS_FAIL; + + yaffs_set_obj_name(obj, new_name); + obj->dirty = 1; + yaffs_add_obj_to_dir(new_dir, obj); + + if (unlink_op) + obj->unlinked = 1; + + /* If it is a deletion then we mark it as a shrink for gc */ + if (yaffs_update_oh(obj, new_name, 0, del_op, shadows, NULL) >= 0) + return YAFFS_OK; + + return YAFFS_FAIL; +} + +/*------------------------ Short Operations Cache ------------------------------ + * In many situations where there is no high level buffering a lot of + * reads might be short sequential reads, and a lot of writes may be short + * sequential writes. eg. scanning/writing a jpeg file. + * In these cases, a short read/write cache can provide a huge perfomance + * benefit with dumb-as-a-rock code. + * In Linux, the page cache provides read buffering and the short op cache + * provides write buffering. + * + * There are a small number (~10) of cache chunks per device so that we don't + * need a very intelligent search. + */ + +static int yaffs_obj_cache_dirty(struct yaffs_obj *obj) +{ + struct yaffs_dev *dev = obj->my_dev; + int i; + struct yaffs_cache *cache; + int n_caches = obj->my_dev->param.n_caches; + + for (i = 0; i < n_caches; i++) { + cache = &dev->cache[i]; + if (cache->object == obj && cache->dirty) + return 1; + } + + return 0; +} + +static void yaffs_flush_single_cache(struct yaffs_cache *cache, int discard) +{ + + if (!cache || cache->locked) + return; + + /* Write it out and free it up if need be.*/ + if (cache->dirty) { + yaffs_wr_data_obj(cache->object, + cache->chunk_id, + cache->data, + cache->n_bytes, + 1); + + cache->dirty = 0; + } + + if (discard) + cache->object = NULL; +} + +static void yaffs_flush_file_cache(struct yaffs_obj *obj, int discard) +{ + struct yaffs_dev *dev = obj->my_dev; + int i; + struct yaffs_cache *cache; + int n_caches = obj->my_dev->param.n_caches; + + if (n_caches < 1) + return; + + + /* Find the chunks for this object and flush them. */ + for (i = 0; i < n_caches; i++) { + cache = &dev->cache[i]; + if (cache->object == obj) + yaffs_flush_single_cache(cache, discard); + } + +} + + +void yaffs_flush_whole_cache(struct yaffs_dev *dev, int discard) +{ + struct yaffs_obj *obj; + int n_caches = dev->param.n_caches; + int i; + + /* Find a dirty object in the cache and flush it... + * until there are no further dirty objects. + */ + do { + obj = NULL; + for (i = 0; i < n_caches && !obj; i++) { + if (dev->cache[i].object && dev->cache[i].dirty) + obj = dev->cache[i].object; + } + if (obj) + yaffs_flush_file_cache(obj, discard); + } while (obj); + +} + +/* Grab us an unused cache chunk for use. + * First look for an empty one. + * Then look for the least recently used non-dirty one. + * Then look for the least recently used dirty one...., flush and look again. + */ +static struct yaffs_cache *yaffs_grab_chunk_worker(struct yaffs_dev *dev) +{ + int i; + + if (dev->param.n_caches > 0) { + for (i = 0; i < dev->param.n_caches; i++) { + if (!dev->cache[i].object) + return &dev->cache[i]; + } + } + + return NULL; +} + +static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev) +{ + struct yaffs_cache *cache; + int usage; + int i; + + if (dev->param.n_caches < 1) + return NULL; + + /* First look for an unused cache */ + + cache = yaffs_grab_chunk_worker(dev); + + if (cache) + return cache; + + /* + * Thery were all in use. + * Find the LRU cache and flush it if it is dirty. + */ + + usage = -1; + cache = NULL; + + for (i = 0; i < dev->param.n_caches; i++) { + if (dev->cache[i].object && + !dev->cache[i].locked && + (dev->cache[i].last_use < usage || !cache)) { + usage = dev->cache[i].last_use; + cache = &dev->cache[i]; + } + } + +#if 1 + yaffs_flush_single_cache(cache, 1); +#else + yaffs_flush_file_cache(cache->object, 1); + cache = yaffs_grab_chunk_worker(dev); +#endif + + return cache; +} + +/* Find a cached chunk */ +static struct yaffs_cache *yaffs_find_chunk_cache(const struct yaffs_obj *obj, + int chunk_id) +{ + struct yaffs_dev *dev = obj->my_dev; + int i; + + if (dev->param.n_caches < 1) + return NULL; + + for (i = 0; i < dev->param.n_caches; i++) { + if (dev->cache[i].object == obj && + dev->cache[i].chunk_id == chunk_id) { + dev->cache_hits++; + + return &dev->cache[i]; + } + } + return NULL; +} + +/* Mark the chunk for the least recently used algorithym */ +static void yaffs_use_cache(struct yaffs_dev *dev, struct yaffs_cache *cache, + int is_write) +{ + int i; + + if (dev->param.n_caches < 1) + return; + + if (dev->cache_last_use < 0 || + dev->cache_last_use > 100000000) { + /* Reset the cache usages */ + for (i = 1; i < dev->param.n_caches; i++) + dev->cache[i].last_use = 0; + + dev->cache_last_use = 0; + } + dev->cache_last_use++; + cache->last_use = dev->cache_last_use; + + if (is_write) + cache->dirty = 1; +} + +/* Invalidate a single cache page. + * Do this when a whole page gets written, + * ie the short cache for this page is no longer valid. + */ +static void yaffs_invalidate_chunk_cache(struct yaffs_obj *object, int chunk_id) +{ + struct yaffs_cache *cache; + + if (object->my_dev->param.n_caches > 0) { + cache = yaffs_find_chunk_cache(object, chunk_id); + + if (cache) + cache->object = NULL; + } +} + +/* Invalidate all the cache pages associated with this object + * Do this whenever ther file is deleted or resized. + */ +static void yaffs_invalidate_whole_cache(struct yaffs_obj *in) +{ + int i; + struct yaffs_dev *dev = in->my_dev; + + if (dev->param.n_caches > 0) { + /* Invalidate it. */ + for (i = 0; i < dev->param.n_caches; i++) { + if (dev->cache[i].object == in) + dev->cache[i].object = NULL; + } + } +} + +static void yaffs_unhash_obj(struct yaffs_obj *obj) +{ + int bucket; + struct yaffs_dev *dev = obj->my_dev; + + /* If it is still linked into the bucket list, free from the list */ + if (!list_empty(&obj->hash_link)) { + list_del_init(&obj->hash_link); + bucket = yaffs_hash_fn(obj->obj_id); + dev->obj_bucket[bucket].count--; + } +} + +/* FreeObject frees up a Object and puts it back on the free list */ +static void yaffs_free_obj(struct yaffs_obj *obj) +{ + struct yaffs_dev *dev; + + if (!obj) { + BUG(); + return; + } + dev = obj->my_dev; + yaffs_trace(YAFFS_TRACE_OS, "FreeObject %p inode %p", + obj, obj->my_inode); + if (obj->parent) + BUG(); + if (!list_empty(&obj->siblings)) + BUG(); + + if (obj->my_inode) { + /* We're still hooked up to a cached inode. + * Don't delete now, but mark for later deletion + */ + obj->defered_free = 1; + return; + } + + yaffs_unhash_obj(obj); + + yaffs_free_raw_obj(dev, obj); + dev->n_obj--; + dev->checkpoint_blocks_required = 0; /* force recalculation */ +} + +void yaffs_handle_defered_free(struct yaffs_obj *obj) +{ + if (obj->defered_free) + yaffs_free_obj(obj); +} + +static int yaffs_generic_obj_del(struct yaffs_obj *in) +{ + /* Iinvalidate the file's data in the cache, without flushing. */ + yaffs_invalidate_whole_cache(in); + + if (in->my_dev->param.is_yaffs2 && in->parent != in->my_dev->del_dir) { + /* Move to unlinked directory so we have a deletion record */ + yaffs_change_obj_name(in, in->my_dev->del_dir, _Y("deleted"), 0, + 0); + } + + yaffs_remove_obj_from_dir(in); + yaffs_chunk_del(in->my_dev, in->hdr_chunk, 1, __LINE__); + in->hdr_chunk = 0; + + yaffs_free_obj(in); + return YAFFS_OK; + +} + +static void yaffs_soft_del_file(struct yaffs_obj *obj) +{ + if (!obj->deleted || + obj->variant_type != YAFFS_OBJECT_TYPE_FILE || + obj->soft_del) + return; + + if (obj->n_data_chunks <= 0) { + /* Empty file with no duplicate object headers, + * just delete it immediately */ + yaffs_free_tnode(obj->my_dev, obj->variant.file_variant.top); + obj->variant.file_variant.top = NULL; + yaffs_trace(YAFFS_TRACE_TRACING, + "yaffs: Deleting empty file %d", + obj->obj_id); + yaffs_generic_obj_del(obj); + } else { + yaffs_soft_del_worker(obj, + obj->variant.file_variant.top, + obj->variant. + file_variant.top_level, 0); + obj->soft_del = 1; + } +} + +/* Pruning removes any part of the file structure tree that is beyond the + * bounds of the file (ie that does not point to chunks). + * + * A file should only get pruned when its size is reduced. + * + * Before pruning, the chunks must be pulled from the tree and the + * level 0 tnode entries must be zeroed out. + * Could also use this for file deletion, but that's probably better handled + * by a special case. + * + * This function is recursive. For levels > 0 the function is called again on + * any sub-tree. For level == 0 we just check if the sub-tree has data. + * If there is no data in a subtree then it is pruned. + */ + +static struct yaffs_tnode *yaffs_prune_worker(struct yaffs_dev *dev, + struct yaffs_tnode *tn, u32 level, + int del0) +{ + int i; + int has_data; + + if (!tn) + return tn; + + has_data = 0; + + if (level > 0) { + for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) { + if (tn->internal[i]) { + tn->internal[i] = + yaffs_prune_worker(dev, + tn->internal[i], + level - 1, + (i == 0) ? del0 : 1); + } + + if (tn->internal[i]) + has_data++; + } + } else { + int tnode_size_u32 = dev->tnode_size / sizeof(u32); + u32 *map = (u32 *) tn; + + for (i = 0; !has_data && i < tnode_size_u32; i++) { + if (map[i]) + has_data++; + } + } + + if (has_data == 0 && del0) { + /* Free and return NULL */ + yaffs_free_tnode(dev, tn); + tn = NULL; + } + return tn; +} + +static int yaffs_prune_tree(struct yaffs_dev *dev, + struct yaffs_file_var *file_struct) +{ + int i; + int has_data; + int done = 0; + struct yaffs_tnode *tn; + + if (file_struct->top_level < 1) + return YAFFS_OK; + + file_struct->top = + yaffs_prune_worker(dev, file_struct->top, file_struct->top_level, 0); + + /* Now we have a tree with all the non-zero branches NULL but + * the height is the same as it was. + * Let's see if we can trim internal tnodes to shorten the tree. + * We can do this if only the 0th element in the tnode is in use + * (ie all the non-zero are NULL) + */ + + while (file_struct->top_level && !done) { + tn = file_struct->top; + + has_data = 0; + for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) { + if (tn->internal[i]) + has_data++; + } + + if (!has_data) { + file_struct->top = tn->internal[0]; + file_struct->top_level--; + yaffs_free_tnode(dev, tn); + } else { + done = 1; + } + } + + return YAFFS_OK; +} + +/*-------------------- End of File Structure functions.-------------------*/ + +/* alloc_empty_obj gets us a clean Object.*/ +static struct yaffs_obj *yaffs_alloc_empty_obj(struct yaffs_dev *dev) +{ + struct yaffs_obj *obj = yaffs_alloc_raw_obj(dev); + + if (!obj) + return obj; + + dev->n_obj++; + + /* Now sweeten it up... */ + + memset(obj, 0, sizeof(struct yaffs_obj)); + obj->being_created = 1; + + obj->my_dev = dev; + obj->hdr_chunk = 0; + obj->variant_type = YAFFS_OBJECT_TYPE_UNKNOWN; + INIT_LIST_HEAD(&(obj->hard_links)); + INIT_LIST_HEAD(&(obj->hash_link)); + INIT_LIST_HEAD(&obj->siblings); + + /* Now make the directory sane */ + if (dev->root_dir) { + obj->parent = dev->root_dir; + list_add(&(obj->siblings), + &dev->root_dir->variant.dir_variant.children); + } + + /* Add it to the lost and found directory. + * NB Can't put root or lost-n-found in lost-n-found so + * check if lost-n-found exists first + */ + if (dev->lost_n_found) + yaffs_add_obj_to_dir(dev->lost_n_found, obj); + + obj->being_created = 0; + + dev->checkpoint_blocks_required = 0; /* force recalculation */ + + return obj; +} + +static int yaffs_find_nice_bucket(struct yaffs_dev *dev) +{ + int i; + int l = 999; + int lowest = 999999; + + /* Search for the shortest list or one that + * isn't too long. + */ + + for (i = 0; i < 10 && lowest > 4; i++) { + dev->bucket_finder++; + dev->bucket_finder %= YAFFS_NOBJECT_BUCKETS; + if (dev->obj_bucket[dev->bucket_finder].count < lowest) { + lowest = dev->obj_bucket[dev->bucket_finder].count; + l = dev->bucket_finder; + } + } + + return l; +} + +static int yaffs_new_obj_id(struct yaffs_dev *dev) +{ + int bucket = yaffs_find_nice_bucket(dev); + int found = 0; + struct list_head *i; + u32 n = (u32) bucket; + + /* + * Now find an object value that has not already been taken + * by scanning the list, incrementing each time by number of buckets. + */ + while (!found) { + found = 1; + n += YAFFS_NOBJECT_BUCKETS; + list_for_each(i, &dev->obj_bucket[bucket].list) { + /* Check if this value is already taken. */ + if (i && list_entry(i, struct yaffs_obj, + hash_link)->obj_id == n) + found = 0; + } + } + return n; +} + +static void yaffs_hash_obj(struct yaffs_obj *in) +{ + int bucket = yaffs_hash_fn(in->obj_id); + struct yaffs_dev *dev = in->my_dev; + + list_add(&in->hash_link, &dev->obj_bucket[bucket].list); + dev->obj_bucket[bucket].count++; +} + +struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number) +{ + int bucket = yaffs_hash_fn(number); + struct list_head *i; + struct yaffs_obj *in; + + list_for_each(i, &dev->obj_bucket[bucket].list) { + /* Look if it is in the list */ + in = list_entry(i, struct yaffs_obj, hash_link); + if (in->obj_id == number) { + /* Don't show if it is defered free */ + if (in->defered_free) + return NULL; + return in; + } + } + + return NULL; +} + +static struct yaffs_obj *yaffs_new_obj(struct yaffs_dev *dev, int number, + enum yaffs_obj_type type) +{ + struct yaffs_obj *the_obj = NULL; + struct yaffs_tnode *tn = NULL; + + if (number < 0) + number = yaffs_new_obj_id(dev); + + if (type == YAFFS_OBJECT_TYPE_FILE) { + tn = yaffs_get_tnode(dev); + if (!tn) + return NULL; + } + + the_obj = yaffs_alloc_empty_obj(dev); + if (!the_obj) { + if (tn) + yaffs_free_tnode(dev, tn); + return NULL; + } + + the_obj->fake = 0; + the_obj->rename_allowed = 1; + the_obj->unlink_allowed = 1; + the_obj->obj_id = number; + yaffs_hash_obj(the_obj); + the_obj->variant_type = type; + yaffs_load_current_time(the_obj, 1, 1); + + switch (type) { + case YAFFS_OBJECT_TYPE_FILE: + the_obj->variant.file_variant.file_size = 0; + the_obj->variant.file_variant.scanned_size = 0; + the_obj->variant.file_variant.shrink_size = + yaffs_max_file_size(dev); + the_obj->variant.file_variant.top_level = 0; + the_obj->variant.file_variant.top = tn; + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + INIT_LIST_HEAD(&the_obj->variant.dir_variant.children); + INIT_LIST_HEAD(&the_obj->variant.dir_variant.dirty); + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + case YAFFS_OBJECT_TYPE_HARDLINK: + case YAFFS_OBJECT_TYPE_SPECIAL: + /* No action required */ + break; + case YAFFS_OBJECT_TYPE_UNKNOWN: + /* todo this should not happen */ + break; + } + return the_obj; +} + +static struct yaffs_obj *yaffs_create_fake_dir(struct yaffs_dev *dev, + int number, u32 mode) +{ + + struct yaffs_obj *obj = + yaffs_new_obj(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY); + + if (!obj) + return NULL; + + obj->fake = 1; /* it is fake so it might not use NAND */ + obj->rename_allowed = 0; + obj->unlink_allowed = 0; + obj->deleted = 0; + obj->unlinked = 0; + obj->yst_mode = mode; + obj->my_dev = dev; + obj->hdr_chunk = 0; /* Not a valid chunk. */ + return obj; + +} + + +static void yaffs_init_tnodes_and_objs(struct yaffs_dev *dev) +{ + int i; + + dev->n_obj = 0; + dev->n_tnodes = 0; + yaffs_init_raw_tnodes_and_objs(dev); + + for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { + INIT_LIST_HEAD(&dev->obj_bucket[i].list); + dev->obj_bucket[i].count = 0; + } +} + +struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev, + int number, + enum yaffs_obj_type type) +{ + struct yaffs_obj *the_obj = NULL; + + if (number > 0) + the_obj = yaffs_find_by_number(dev, number); + + if (!the_obj) + the_obj = yaffs_new_obj(dev, number, type); + + return the_obj; + +} + +YCHAR *yaffs_clone_str(const YCHAR *str) +{ + YCHAR *new_str = NULL; + int len; + + if (!str) + str = _Y(""); + + len = strnlen(str, YAFFS_MAX_ALIAS_LENGTH); + new_str = kmalloc((len + 1) * sizeof(YCHAR), GFP_NOFS); + if (new_str) { + strncpy(new_str, str, len); + new_str[len] = 0; + } + return new_str; + +} +/* + *yaffs_update_parent() handles fixing a directories mtime and ctime when a new + * link (ie. name) is created or deleted in the directory. + * + * ie. + * create dir/a : update dir's mtime/ctime + * rm dir/a: update dir's mtime/ctime + * modify dir/a: don't update dir's mtimme/ctime + * + * This can be handled immediately or defered. Defering helps reduce the number + * of updates when many files in a directory are changed within a brief period. + * + * If the directory updating is defered then yaffs_update_dirty_dirs must be + * called periodically. + */ + +static void yaffs_update_parent(struct yaffs_obj *obj) +{ + struct yaffs_dev *dev; + + if (!obj) + return; + dev = obj->my_dev; + obj->dirty = 1; + yaffs_load_current_time(obj, 0, 1); + if (dev->param.defered_dir_update) { + struct list_head *link = &obj->variant.dir_variant.dirty; + + if (list_empty(link)) { + list_add(link, &dev->dirty_dirs); + yaffs_trace(YAFFS_TRACE_BACKGROUND, + "Added object %d to dirty directories", + obj->obj_id); + } + + } else { + yaffs_update_oh(obj, NULL, 0, 0, 0, NULL); + } +} + +void yaffs_update_dirty_dirs(struct yaffs_dev *dev) +{ + struct list_head *link; + struct yaffs_obj *obj; + struct yaffs_dir_var *d_s; + union yaffs_obj_var *o_v; + + yaffs_trace(YAFFS_TRACE_BACKGROUND, "Update dirty directories"); + + while (!list_empty(&dev->dirty_dirs)) { + link = dev->dirty_dirs.next; + list_del_init(link); + + d_s = list_entry(link, struct yaffs_dir_var, dirty); + o_v = list_entry(d_s, union yaffs_obj_var, dir_variant); + obj = list_entry(o_v, struct yaffs_obj, variant); + + yaffs_trace(YAFFS_TRACE_BACKGROUND, "Update directory %d", + obj->obj_id); + + if (obj->dirty) + yaffs_update_oh(obj, NULL, 0, 0, 0, NULL); + } +} + +/* + * Mknod (create) a new object. + * equiv_obj only has meaning for a hard link; + * alias_str only has meaning for a symlink. + * rdev only has meaning for devices (a subset of special objects) + */ + +static struct yaffs_obj *yaffs_create_obj(enum yaffs_obj_type type, + struct yaffs_obj *parent, + const YCHAR *name, + u32 mode, + u32 uid, + u32 gid, + struct yaffs_obj *equiv_obj, + const YCHAR *alias_str, u32 rdev) +{ + struct yaffs_obj *in; + YCHAR *str = NULL; + struct yaffs_dev *dev = parent->my_dev; + + /* Check if the entry exists. + * If it does then fail the call since we don't want a dup. */ + if (yaffs_find_by_name(parent, name)) + return NULL; + + if (type == YAFFS_OBJECT_TYPE_SYMLINK) { + str = yaffs_clone_str(alias_str); + if (!str) + return NULL; + } + + in = yaffs_new_obj(dev, -1, type); + + if (!in) { + kfree(str); + return NULL; + } + + in->hdr_chunk = 0; + in->valid = 1; + in->variant_type = type; + + in->yst_mode = mode; + + yaffs_attribs_init(in, gid, uid, rdev); + + in->n_data_chunks = 0; + + yaffs_set_obj_name(in, name); + in->dirty = 1; + + yaffs_add_obj_to_dir(parent, in); + + in->my_dev = parent->my_dev; + + switch (type) { + case YAFFS_OBJECT_TYPE_SYMLINK: + in->variant.symlink_variant.alias = str; + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + in->variant.hardlink_variant.equiv_obj = equiv_obj; + in->variant.hardlink_variant.equiv_id = equiv_obj->obj_id; + list_add(&in->hard_links, &equiv_obj->hard_links); + break; + case YAFFS_OBJECT_TYPE_FILE: + case YAFFS_OBJECT_TYPE_DIRECTORY: + case YAFFS_OBJECT_TYPE_SPECIAL: + case YAFFS_OBJECT_TYPE_UNKNOWN: + /* do nothing */ + break; + } + + if (yaffs_update_oh(in, name, 0, 0, 0, NULL) < 0) { + /* Could not create the object header, fail */ + yaffs_del_obj(in); + in = NULL; + } + + if (in) + yaffs_update_parent(parent); + + return in; +} + +struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent, + const YCHAR *name, u32 mode, u32 uid, + u32 gid) +{ + return yaffs_create_obj(YAFFS_OBJECT_TYPE_FILE, parent, name, mode, + uid, gid, NULL, NULL, 0); +} + +struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR *name, + u32 mode, u32 uid, u32 gid) +{ + return yaffs_create_obj(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name, + mode, uid, gid, NULL, NULL, 0); +} + +struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent, + const YCHAR *name, u32 mode, u32 uid, + u32 gid, u32 rdev) +{ + return yaffs_create_obj(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode, + uid, gid, NULL, NULL, rdev); +} + +struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent, + const YCHAR *name, u32 mode, u32 uid, + u32 gid, const YCHAR *alias) +{ + return yaffs_create_obj(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode, + uid, gid, NULL, alias, 0); +} + +/* yaffs_link_obj returns the object id of the equivalent object.*/ +struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR * name, + struct yaffs_obj *equiv_obj) +{ + /* Get the real object in case we were fed a hard link obj */ + equiv_obj = yaffs_get_equivalent_obj(equiv_obj); + + if (yaffs_create_obj(YAFFS_OBJECT_TYPE_HARDLINK, + parent, name, 0, 0, 0, + equiv_obj, NULL, 0)) + return equiv_obj; + + return NULL; + +} + + + +/*---------------------- Block Management and Page Allocation -------------*/ + +static void yaffs_deinit_blocks(struct yaffs_dev *dev) +{ + if (dev->block_info_alt && dev->block_info) + vfree(dev->block_info); + else + kfree(dev->block_info); + + dev->block_info_alt = 0; + + dev->block_info = NULL; + + if (dev->chunk_bits_alt && dev->chunk_bits) + vfree(dev->chunk_bits); + else + kfree(dev->chunk_bits); + dev->chunk_bits_alt = 0; + dev->chunk_bits = NULL; +} + +static int yaffs_init_blocks(struct yaffs_dev *dev) +{ + int n_blocks = dev->internal_end_block - dev->internal_start_block + 1; + + dev->block_info = NULL; + dev->chunk_bits = NULL; + dev->alloc_block = -1; /* force it to get a new one */ + + /* If the first allocation strategy fails, thry the alternate one */ + dev->block_info = + kmalloc(n_blocks * sizeof(struct yaffs_block_info), GFP_NOFS); + if (!dev->block_info) { + dev->block_info = + vmalloc(n_blocks * sizeof(struct yaffs_block_info)); + dev->block_info_alt = 1; + } else { + dev->block_info_alt = 0; + } + + if (!dev->block_info) + goto alloc_error; + + /* Set up dynamic blockinfo stuff. Round up bytes. */ + dev->chunk_bit_stride = (dev->param.chunks_per_block + 7) / 8; + dev->chunk_bits = + kmalloc(dev->chunk_bit_stride * n_blocks, GFP_NOFS); + if (!dev->chunk_bits) { + dev->chunk_bits = + vmalloc(dev->chunk_bit_stride * n_blocks); + dev->chunk_bits_alt = 1; + } else { + dev->chunk_bits_alt = 0; + } + if (!dev->chunk_bits) + goto alloc_error; + + + memset(dev->block_info, 0, n_blocks * sizeof(struct yaffs_block_info)); + memset(dev->chunk_bits, 0, dev->chunk_bit_stride * n_blocks); + return YAFFS_OK; + +alloc_error: + yaffs_deinit_blocks(dev); + return YAFFS_FAIL; +} + + +void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no) +{ + struct yaffs_block_info *bi = yaffs_get_block_info(dev, block_no); + int erased_ok = 0; + int i; + + /* If the block is still healthy erase it and mark as clean. + * If the block has had a data failure, then retire it. + */ + + yaffs_trace(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE, + "yaffs_block_became_dirty block %d state %d %s", + block_no, bi->block_state, + (bi->needs_retiring) ? "needs retiring" : ""); + + yaffs2_clear_oldest_dirty_seq(dev, bi); + + bi->block_state = YAFFS_BLOCK_STATE_DIRTY; + + /* If this is the block being garbage collected then stop gc'ing */ + if (block_no == dev->gc_block) + dev->gc_block = 0; + + /* If this block is currently the best candidate for gc + * then drop as a candidate */ + if (block_no == dev->gc_dirtiest) { + dev->gc_dirtiest = 0; + dev->gc_pages_in_use = 0; + } + + if (!bi->needs_retiring) { + yaffs2_checkpt_invalidate(dev); + erased_ok = yaffs_erase_block(dev, block_no); + if (!erased_ok) { + dev->n_erase_failures++; + yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, + "**>> Erasure failed %d", block_no); + } + } + + /* Verify erasure if needed */ + if (erased_ok && + ((yaffs_trace_mask & YAFFS_TRACE_ERASE) || + !yaffs_skip_verification(dev))) { + for (i = 0; i < dev->param.chunks_per_block; i++) { + if (!yaffs_check_chunk_erased(dev, + block_no * dev->param.chunks_per_block + i)) { + yaffs_trace(YAFFS_TRACE_ERROR, + ">>Block %d erasure supposedly OK, but chunk %d not erased", + block_no, i); + } + } + } + + if (!erased_ok) { + /* We lost a block of free space */ + dev->n_free_chunks -= dev->param.chunks_per_block; + yaffs_retire_block(dev, block_no); + yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, + "**>> Block %d retired", block_no); + return; + } + + /* Clean it up... */ + bi->block_state = YAFFS_BLOCK_STATE_EMPTY; + bi->seq_number = 0; + dev->n_erased_blocks++; + bi->pages_in_use = 0; + bi->soft_del_pages = 0; + bi->has_shrink_hdr = 0; + bi->skip_erased_check = 1; /* Clean, so no need to check */ + bi->gc_prioritise = 0; + bi->has_summary = 0; + + yaffs_clear_chunk_bits(dev, block_no); + + yaffs_trace(YAFFS_TRACE_ERASE, "Erased block %d", block_no); +} + +static inline int yaffs_gc_process_chunk(struct yaffs_dev *dev, + struct yaffs_block_info *bi, + int old_chunk, u8 *buffer) +{ + int new_chunk; + int mark_flash = 1; + struct yaffs_ext_tags tags; + struct yaffs_obj *object; + int matching_chunk; + int ret_val = YAFFS_OK; + + memset(&tags, 0, sizeof(tags)); + yaffs_rd_chunk_tags_nand(dev, old_chunk, + buffer, &tags); + object = yaffs_find_by_number(dev, tags.obj_id); + + yaffs_trace(YAFFS_TRACE_GC_DETAIL, + "Collecting chunk in block %d, %d %d %d ", + dev->gc_chunk, tags.obj_id, + tags.chunk_id, tags.n_bytes); + + if (object && !yaffs_skip_verification(dev)) { + if (tags.chunk_id == 0) + matching_chunk = + object->hdr_chunk; + else if (object->soft_del) + /* Defeat the test */ + matching_chunk = old_chunk; + else + matching_chunk = + yaffs_find_chunk_in_file + (object, tags.chunk_id, + NULL); + + if (old_chunk != matching_chunk) + yaffs_trace(YAFFS_TRACE_ERROR, + "gc: page in gc mismatch: %d %d %d %d", + old_chunk, + matching_chunk, + tags.obj_id, + tags.chunk_id); + } + + if (!object) { + yaffs_trace(YAFFS_TRACE_ERROR, + "page %d in gc has no object: %d %d %d ", + old_chunk, + tags.obj_id, tags.chunk_id, + tags.n_bytes); + } + + if (object && + object->deleted && + object->soft_del && tags.chunk_id != 0) { + /* Data chunk in a soft deleted file, + * throw it away. + * It's a soft deleted data chunk, + * No need to copy this, just forget + * about it and fix up the object. + */ + + /* Free chunks already includes + * softdeleted chunks, how ever this + * chunk is going to soon be really + * deleted which will increment free + * chunks. We have to decrement free + * chunks so this works out properly. + */ + dev->n_free_chunks--; + bi->soft_del_pages--; + + object->n_data_chunks--; + if (object->n_data_chunks <= 0) { + /* remeber to clean up obj */ + dev->gc_cleanup_list[dev->n_clean_ups] = tags.obj_id; + dev->n_clean_ups++; + } + mark_flash = 0; + } else if (object) { + /* It's either a data chunk in a live + * file or an ObjectHeader, so we're + * interested in it. + * NB Need to keep the ObjectHeaders of + * deleted files until the whole file + * has been deleted off + */ + tags.serial_number++; + dev->n_gc_copies++; + + if (tags.chunk_id == 0) { + /* It is an object Id, + * We need to nuke the + * shrinkheader flags since its + * work is done. + * Also need to clean up + * shadowing. + */ + struct yaffs_obj_hdr *oh; + oh = (struct yaffs_obj_hdr *) buffer; + + oh->is_shrink = 0; + tags.extra_is_shrink = 0; + oh->shadows_obj = 0; + oh->inband_shadowed_obj_id = 0; + tags.extra_shadows = 0; + + /* Update file size */ + if (object->variant_type == YAFFS_OBJECT_TYPE_FILE) { + yaffs_oh_size_load(oh, + object->variant.file_variant.file_size); + tags.extra_file_size = + object->variant.file_variant.file_size; + } + + yaffs_verify_oh(object, oh, &tags, 1); + new_chunk = + yaffs_write_new_chunk(dev, (u8 *) oh, &tags, 1); + } else { + new_chunk = + yaffs_write_new_chunk(dev, buffer, &tags, 1); + } + + if (new_chunk < 0) { + ret_val = YAFFS_FAIL; + } else { + + /* Now fix up the Tnodes etc. */ + + if (tags.chunk_id == 0) { + /* It's a header */ + object->hdr_chunk = new_chunk; + object->serial = tags.serial_number; + } else { + /* It's a data chunk */ + yaffs_put_chunk_in_file(object, tags.chunk_id, + new_chunk, 0); + } + } + } + if (ret_val == YAFFS_OK) + yaffs_chunk_del(dev, old_chunk, mark_flash, __LINE__); + return ret_val; +} + +static int yaffs_gc_block(struct yaffs_dev *dev, int block, int whole_block) +{ + int old_chunk; + int ret_val = YAFFS_OK; + int i; + int is_checkpt_block; + int max_copies; + int chunks_before = yaffs_get_erased_chunks(dev); + int chunks_after; + struct yaffs_block_info *bi = yaffs_get_block_info(dev, block); + + is_checkpt_block = (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT); + + yaffs_trace(YAFFS_TRACE_TRACING, + "Collecting block %d, in use %d, shrink %d, whole_block %d", + block, bi->pages_in_use, bi->has_shrink_hdr, + whole_block); + + /*yaffs_verify_free_chunks(dev); */ + + if (bi->block_state == YAFFS_BLOCK_STATE_FULL) + bi->block_state = YAFFS_BLOCK_STATE_COLLECTING; + + bi->has_shrink_hdr = 0; /* clear the flag so that the block can erase */ + + dev->gc_disable = 1; + + yaffs_summary_gc(dev, block); + + if (is_checkpt_block || !yaffs_still_some_chunks(dev, block)) { + yaffs_trace(YAFFS_TRACE_TRACING, + "Collecting block %d that has no chunks in use", + block); + yaffs_block_became_dirty(dev, block); + } else { + + u8 *buffer = yaffs_get_temp_buffer(dev); + + yaffs_verify_blk(dev, bi, block); + + max_copies = (whole_block) ? dev->param.chunks_per_block : 5; + old_chunk = block * dev->param.chunks_per_block + dev->gc_chunk; + + for (/* init already done */ ; + ret_val == YAFFS_OK && + dev->gc_chunk < dev->param.chunks_per_block && + (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) && + max_copies > 0; + dev->gc_chunk++, old_chunk++) { + if (yaffs_check_chunk_bit(dev, block, dev->gc_chunk)) { + /* Page is in use and might need to be copied */ + max_copies--; + ret_val = yaffs_gc_process_chunk(dev, bi, + old_chunk, buffer); + } + } + yaffs_release_temp_buffer(dev, buffer); + } + + yaffs_verify_collected_blk(dev, bi, block); + + if (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) { + /* + * The gc did not complete. Set block state back to FULL + * because checkpointing does not restore gc. + */ + bi->block_state = YAFFS_BLOCK_STATE_FULL; + } else { + /* The gc completed. */ + /* Do any required cleanups */ + for (i = 0; i < dev->n_clean_ups; i++) { + /* Time to delete the file too */ + struct yaffs_obj *object = + yaffs_find_by_number(dev, dev->gc_cleanup_list[i]); + if (object) { + yaffs_free_tnode(dev, + object->variant.file_variant.top); + object->variant.file_variant.top = NULL; + yaffs_trace(YAFFS_TRACE_GC, + "yaffs: About to finally delete object %d", + object->obj_id); + yaffs_generic_obj_del(object); + object->my_dev->n_deleted_files--; + } + + } + chunks_after = yaffs_get_erased_chunks(dev); + if (chunks_before >= chunks_after) + yaffs_trace(YAFFS_TRACE_GC, + "gc did not increase free chunks before %d after %d", + chunks_before, chunks_after); + dev->gc_block = 0; + dev->gc_chunk = 0; + dev->n_clean_ups = 0; + } + + dev->gc_disable = 0; + + return ret_val; +} + +/* + * find_gc_block() selects the dirtiest block (or close enough) + * for garbage collection. + */ + +static unsigned yaffs_find_gc_block(struct yaffs_dev *dev, + int aggressive, int background) +{ + int i; + int iterations; + unsigned selected = 0; + int prioritised = 0; + int prioritised_exist = 0; + struct yaffs_block_info *bi; + int threshold; + + /* First let's see if we need to grab a prioritised block */ + if (dev->has_pending_prioritised_gc && !aggressive) { + dev->gc_dirtiest = 0; + bi = dev->block_info; + for (i = dev->internal_start_block; + i <= dev->internal_end_block && !selected; i++) { + + if (bi->gc_prioritise) { + prioritised_exist = 1; + if (bi->block_state == YAFFS_BLOCK_STATE_FULL && + yaffs_block_ok_for_gc(dev, bi)) { + selected = i; + prioritised = 1; + } + } + bi++; + } + + /* + * If there is a prioritised block and none was selected then + * this happened because there is at least one old dirty block + * gumming up the works. Let's gc the oldest dirty block. + */ + + if (prioritised_exist && + !selected && dev->oldest_dirty_block > 0) + selected = dev->oldest_dirty_block; + + if (!prioritised_exist) /* None found, so we can clear this */ + dev->has_pending_prioritised_gc = 0; + } + + /* If we're doing aggressive GC then we are happy to take a less-dirty + * block, and search harder. + * else (leasurely gc), then we only bother to do this if the + * block has only a few pages in use. + */ + + if (!selected) { + int pages_used; + int n_blocks = + dev->internal_end_block - dev->internal_start_block + 1; + if (aggressive) { + threshold = dev->param.chunks_per_block; + iterations = n_blocks; + } else { + int max_threshold; + + if (background) + max_threshold = dev->param.chunks_per_block / 2; + else + max_threshold = dev->param.chunks_per_block / 8; + + if (max_threshold < YAFFS_GC_PASSIVE_THRESHOLD) + max_threshold = YAFFS_GC_PASSIVE_THRESHOLD; + + threshold = background ? (dev->gc_not_done + 2) * 2 : 0; + if (threshold < YAFFS_GC_PASSIVE_THRESHOLD) + threshold = YAFFS_GC_PASSIVE_THRESHOLD; + if (threshold > max_threshold) + threshold = max_threshold; + + iterations = n_blocks / 16 + 1; + if (iterations > 100) + iterations = 100; + } + + for (i = 0; + i < iterations && + (dev->gc_dirtiest < 1 || + dev->gc_pages_in_use > YAFFS_GC_GOOD_ENOUGH); + i++) { + dev->gc_block_finder++; + if (dev->gc_block_finder < dev->internal_start_block || + dev->gc_block_finder > dev->internal_end_block) + dev->gc_block_finder = + dev->internal_start_block; + + bi = yaffs_get_block_info(dev, dev->gc_block_finder); + + pages_used = bi->pages_in_use - bi->soft_del_pages; + + if (bi->block_state == YAFFS_BLOCK_STATE_FULL && + pages_used < dev->param.chunks_per_block && + (dev->gc_dirtiest < 1 || + pages_used < dev->gc_pages_in_use) && + yaffs_block_ok_for_gc(dev, bi)) { + dev->gc_dirtiest = dev->gc_block_finder; + dev->gc_pages_in_use = pages_used; + } + } + + if (dev->gc_dirtiest > 0 && dev->gc_pages_in_use <= threshold) + selected = dev->gc_dirtiest; + } + + /* + * If nothing has been selected for a while, try the oldest dirty + * because that's gumming up the works. + */ + + if (!selected && dev->param.is_yaffs2 && + dev->gc_not_done >= (background ? 10 : 20)) { + yaffs2_find_oldest_dirty_seq(dev); + if (dev->oldest_dirty_block > 0) { + selected = dev->oldest_dirty_block; + dev->gc_dirtiest = selected; + dev->oldest_dirty_gc_count++; + bi = yaffs_get_block_info(dev, selected); + dev->gc_pages_in_use = + bi->pages_in_use - bi->soft_del_pages; + } else { + dev->gc_not_done = 0; + } + } + + if (selected) { + yaffs_trace(YAFFS_TRACE_GC, + "GC Selected block %d with %d free, prioritised:%d", + selected, + dev->param.chunks_per_block - dev->gc_pages_in_use, + prioritised); + + dev->n_gc_blocks++; + if (background) + dev->bg_gcs++; + + dev->gc_dirtiest = 0; + dev->gc_pages_in_use = 0; + dev->gc_not_done = 0; + if (dev->refresh_skip > 0) + dev->refresh_skip--; + } else { + dev->gc_not_done++; + yaffs_trace(YAFFS_TRACE_GC, + "GC none: finder %d skip %d threshold %d dirtiest %d using %d oldest %d%s", + dev->gc_block_finder, dev->gc_not_done, threshold, + dev->gc_dirtiest, dev->gc_pages_in_use, + dev->oldest_dirty_block, background ? " bg" : ""); + } + + return selected; +} + +/* New garbage collector + * If we're very low on erased blocks then we do aggressive garbage collection + * otherwise we do "leasurely" garbage collection. + * Aggressive gc looks further (whole array) and will accept less dirty blocks. + * Passive gc only inspects smaller areas and only accepts more dirty blocks. + * + * The idea is to help clear out space in a more spread-out manner. + * Dunno if it really does anything useful. + */ +static int yaffs_check_gc(struct yaffs_dev *dev, int background) +{ + int aggressive = 0; + int gc_ok = YAFFS_OK; + int max_tries = 0; + int min_erased; + int erased_chunks; + int checkpt_block_adjust; + + if (dev->param.gc_control_fn && + (dev->param.gc_control_fn(dev) & 1) == 0) + return YAFFS_OK; + + if (dev->gc_disable) + /* Bail out so we don't get recursive gc */ + return YAFFS_OK; + + /* This loop should pass the first time. + * Only loops here if the collection does not increase space. + */ + + do { + max_tries++; + + checkpt_block_adjust = yaffs_calc_checkpt_blocks_required(dev); + + min_erased = + dev->param.n_reserved_blocks + checkpt_block_adjust + 1; + erased_chunks = + dev->n_erased_blocks * dev->param.chunks_per_block; + + /* If we need a block soon then do aggressive gc. */ + if (dev->n_erased_blocks < min_erased) + aggressive = 1; + else { + if (!background + && erased_chunks > (dev->n_free_chunks / 4)) + break; + + if (dev->gc_skip > 20) + dev->gc_skip = 20; + if (erased_chunks < dev->n_free_chunks / 2 || + dev->gc_skip < 1 || background) + aggressive = 0; + else { + dev->gc_skip--; + break; + } + } + + dev->gc_skip = 5; + + /* If we don't already have a block being gc'd then see if we + * should start another */ + + if (dev->gc_block < 1 && !aggressive) { + dev->gc_block = yaffs2_find_refresh_block(dev); + dev->gc_chunk = 0; + dev->n_clean_ups = 0; + } + if (dev->gc_block < 1) { + dev->gc_block = + yaffs_find_gc_block(dev, aggressive, background); + dev->gc_chunk = 0; + dev->n_clean_ups = 0; + } + + if (dev->gc_block > 0) { + dev->all_gcs++; + if (!aggressive) + dev->passive_gc_count++; + + yaffs_trace(YAFFS_TRACE_GC, + "yaffs: GC n_erased_blocks %d aggressive %d", + dev->n_erased_blocks, aggressive); + + gc_ok = yaffs_gc_block(dev, dev->gc_block, aggressive); + } + + if (dev->n_erased_blocks < (dev->param.n_reserved_blocks) && + dev->gc_block > 0) { + yaffs_trace(YAFFS_TRACE_GC, + "yaffs: GC !!!no reclaim!!! n_erased_blocks %d after try %d block %d", + dev->n_erased_blocks, max_tries, + dev->gc_block); + } + } while ((dev->n_erased_blocks < dev->param.n_reserved_blocks) && + (dev->gc_block > 0) && (max_tries < 2)); + + return aggressive ? gc_ok : YAFFS_OK; +} + +/* + * yaffs_bg_gc() + * Garbage collects. Intended to be called from a background thread. + * Returns non-zero if at least half the free chunks are erased. + */ +int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency) +{ + int erased_chunks = dev->n_erased_blocks * dev->param.chunks_per_block; + + yaffs_trace(YAFFS_TRACE_BACKGROUND, "Background gc %u", urgency); + + yaffs_check_gc(dev, 1); + return erased_chunks > dev->n_free_chunks / 2; +} + +/*-------------------- Data file manipulation -----------------*/ + +static int yaffs_rd_data_obj(struct yaffs_obj *in, int inode_chunk, u8 * buffer) +{ + int nand_chunk = yaffs_find_chunk_in_file(in, inode_chunk, NULL); + + if (nand_chunk >= 0) + return yaffs_rd_chunk_tags_nand(in->my_dev, nand_chunk, + buffer, NULL); + else { + yaffs_trace(YAFFS_TRACE_NANDACCESS, + "Chunk %d not found zero instead", + nand_chunk); + /* get sane (zero) data if you read a hole */ + memset(buffer, 0, in->my_dev->data_bytes_per_chunk); + return 0; + } + +} + +void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash, + int lyn) +{ + int block; + int page; + struct yaffs_ext_tags tags; + struct yaffs_block_info *bi; + + if (chunk_id <= 0) + return; + + dev->n_deletions++; + block = chunk_id / dev->param.chunks_per_block; + page = chunk_id % dev->param.chunks_per_block; + + if (!yaffs_check_chunk_bit(dev, block, page)) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Deleting invalid chunk %d", chunk_id); + + bi = yaffs_get_block_info(dev, block); + + yaffs2_update_oldest_dirty_seq(dev, block, bi); + + yaffs_trace(YAFFS_TRACE_DELETION, + "line %d delete of chunk %d", + lyn, chunk_id); + + if (!dev->param.is_yaffs2 && mark_flash && + bi->block_state != YAFFS_BLOCK_STATE_COLLECTING) { + + memset(&tags, 0, sizeof(tags)); + tags.is_deleted = 1; + yaffs_wr_chunk_tags_nand(dev, chunk_id, NULL, &tags); + yaffs_handle_chunk_update(dev, chunk_id, &tags); + } else { + dev->n_unmarked_deletions++; + } + + /* Pull out of the management area. + * If the whole block became dirty, this will kick off an erasure. + */ + if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING || + bi->block_state == YAFFS_BLOCK_STATE_FULL || + bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN || + bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) { + dev->n_free_chunks++; + yaffs_clear_chunk_bit(dev, block, page); + bi->pages_in_use--; + + if (bi->pages_in_use == 0 && + !bi->has_shrink_hdr && + bi->block_state != YAFFS_BLOCK_STATE_ALLOCATING && + bi->block_state != YAFFS_BLOCK_STATE_NEEDS_SCAN) { + yaffs_block_became_dirty(dev, block); + } + } +} + +static int yaffs_wr_data_obj(struct yaffs_obj *in, int inode_chunk, + const u8 *buffer, int n_bytes, int use_reserve) +{ + /* Find old chunk Need to do this to get serial number + * Write new one and patch into tree. + * Invalidate old tags. + */ + + int prev_chunk_id; + struct yaffs_ext_tags prev_tags; + int new_chunk_id; + struct yaffs_ext_tags new_tags; + struct yaffs_dev *dev = in->my_dev; + + yaffs_check_gc(dev, 0); + + /* Get the previous chunk at this location in the file if it exists. + * If it does not exist then put a zero into the tree. This creates + * the tnode now, rather than later when it is harder to clean up. + */ + prev_chunk_id = yaffs_find_chunk_in_file(in, inode_chunk, &prev_tags); + if (prev_chunk_id < 1 && + !yaffs_put_chunk_in_file(in, inode_chunk, 0, 0)) + return 0; + + /* Set up new tags */ + memset(&new_tags, 0, sizeof(new_tags)); + + new_tags.chunk_id = inode_chunk; + new_tags.obj_id = in->obj_id; + new_tags.serial_number = + (prev_chunk_id > 0) ? prev_tags.serial_number + 1 : 1; + new_tags.n_bytes = n_bytes; + + if (n_bytes < 1 || n_bytes > dev->param.total_bytes_per_chunk) { + yaffs_trace(YAFFS_TRACE_ERROR, + "Writing %d bytes to chunk!!!!!!!!!", + n_bytes); + BUG(); + } + + new_chunk_id = + yaffs_write_new_chunk(dev, buffer, &new_tags, use_reserve); + + if (new_chunk_id > 0) { + yaffs_put_chunk_in_file(in, inode_chunk, new_chunk_id, 0); + + if (prev_chunk_id > 0) + yaffs_chunk_del(dev, prev_chunk_id, 1, __LINE__); + + yaffs_verify_file_sane(in); + } + return new_chunk_id; + +} + + + +static int yaffs_do_xattrib_mod(struct yaffs_obj *obj, int set, + const YCHAR *name, const void *value, int size, + int flags) +{ + struct yaffs_xattr_mod xmod; + int result; + + xmod.set = set; + xmod.name = name; + xmod.data = value; + xmod.size = size; + xmod.flags = flags; + xmod.result = -ENOSPC; + + result = yaffs_update_oh(obj, NULL, 0, 0, 0, &xmod); + + if (result > 0) + return xmod.result; + else + return -ENOSPC; +} + +static int yaffs_apply_xattrib_mod(struct yaffs_obj *obj, char *buffer, + struct yaffs_xattr_mod *xmod) +{ + int retval = 0; + int x_offs = sizeof(struct yaffs_obj_hdr); + struct yaffs_dev *dev = obj->my_dev; + int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr); + char *x_buffer = buffer + x_offs; + + if (xmod->set) + retval = + nval_set(x_buffer, x_size, xmod->name, xmod->data, + xmod->size, xmod->flags); + else + retval = nval_del(x_buffer, x_size, xmod->name); + + obj->has_xattr = nval_hasvalues(x_buffer, x_size); + obj->xattr_known = 1; + xmod->result = retval; + + return retval; +} + +static int yaffs_do_xattrib_fetch(struct yaffs_obj *obj, const YCHAR *name, + void *value, int size) +{ + char *buffer = NULL; + int result; + struct yaffs_ext_tags tags; + struct yaffs_dev *dev = obj->my_dev; + int x_offs = sizeof(struct yaffs_obj_hdr); + int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr); + char *x_buffer; + int retval = 0; + + if (obj->hdr_chunk < 1) + return -ENODATA; + + /* If we know that the object has no xattribs then don't do all the + * reading and parsing. + */ + if (obj->xattr_known && !obj->has_xattr) { + if (name) + return -ENODATA; + else + return 0; + } + + buffer = (char *)yaffs_get_temp_buffer(dev); + if (!buffer) + return -ENOMEM; + + result = + yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, (u8 *) buffer, &tags); + + if (result != YAFFS_OK) + retval = -ENOENT; + else { + x_buffer = buffer + x_offs; + + if (!obj->xattr_known) { + obj->has_xattr = nval_hasvalues(x_buffer, x_size); + obj->xattr_known = 1; + } + + if (name) + retval = nval_get(x_buffer, x_size, name, value, size); + else + retval = nval_list(x_buffer, x_size, value, size); + } + yaffs_release_temp_buffer(dev, (u8 *) buffer); + return retval; +} + +int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR * name, + const void *value, int size, int flags) +{ + return yaffs_do_xattrib_mod(obj, 1, name, value, size, flags); +} + +int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR * name) +{ + return yaffs_do_xattrib_mod(obj, 0, name, NULL, 0, 0); +} + +int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR * name, void *value, + int size) +{ + return yaffs_do_xattrib_fetch(obj, name, value, size); +} + +int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size) +{ + return yaffs_do_xattrib_fetch(obj, NULL, buffer, size); +} + +static void yaffs_check_obj_details_loaded(struct yaffs_obj *in) +{ + u8 *buf; + struct yaffs_obj_hdr *oh; + struct yaffs_dev *dev; + struct yaffs_ext_tags tags; + int result; + int alloc_failed = 0; + + if (!in || !in->lazy_loaded || in->hdr_chunk < 1) + return; + + dev = in->my_dev; + in->lazy_loaded = 0; + buf = yaffs_get_temp_buffer(dev); + + result = yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags); + oh = (struct yaffs_obj_hdr *)buf; + + in->yst_mode = oh->yst_mode; + yaffs_load_attribs(in, oh); + yaffs_set_obj_name_from_oh(in, oh); + + if (in->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) { + in->variant.symlink_variant.alias = + yaffs_clone_str(oh->alias); + if (!in->variant.symlink_variant.alias) + alloc_failed = 1; /* Not returned */ + } + yaffs_release_temp_buffer(dev, buf); +} + +/* UpdateObjectHeader updates the header on NAND for an object. + * If name is not NULL, then that new name is used. + */ +int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, int force, + int is_shrink, int shadows, struct yaffs_xattr_mod *xmod) +{ + + struct yaffs_block_info *bi; + struct yaffs_dev *dev = in->my_dev; + int prev_chunk_id; + int ret_val = 0; + int result = 0; + int new_chunk_id; + struct yaffs_ext_tags new_tags; + struct yaffs_ext_tags old_tags; + const YCHAR *alias = NULL; + u8 *buffer = NULL; + YCHAR old_name[YAFFS_MAX_NAME_LENGTH + 1]; + struct yaffs_obj_hdr *oh = NULL; + loff_t file_size = 0; + + strcpy(old_name, _Y("silly old name")); + + if (in->fake && in != dev->root_dir && !force && !xmod) + return ret_val; + + yaffs_check_gc(dev, 0); + yaffs_check_obj_details_loaded(in); + + buffer = yaffs_get_temp_buffer(in->my_dev); + oh = (struct yaffs_obj_hdr *)buffer; + + prev_chunk_id = in->hdr_chunk; + + if (prev_chunk_id > 0) { + result = yaffs_rd_chunk_tags_nand(dev, prev_chunk_id, + buffer, &old_tags); + + yaffs_verify_oh(in, oh, &old_tags, 0); + memcpy(old_name, oh->name, sizeof(oh->name)); + memset(buffer, 0xff, sizeof(struct yaffs_obj_hdr)); + } else { + memset(buffer, 0xff, dev->data_bytes_per_chunk); + } + + oh->type = in->variant_type; + oh->yst_mode = in->yst_mode; + oh->shadows_obj = oh->inband_shadowed_obj_id = shadows; + + yaffs_load_attribs_oh(oh, in); + + if (in->parent) + oh->parent_obj_id = in->parent->obj_id; + else + oh->parent_obj_id = 0; + + if (name && *name) { + memset(oh->name, 0, sizeof(oh->name)); + yaffs_load_oh_from_name(dev, oh->name, name); + } else if (prev_chunk_id > 0) { + memcpy(oh->name, old_name, sizeof(oh->name)); + } else { + memset(oh->name, 0, sizeof(oh->name)); + } + + oh->is_shrink = is_shrink; + + switch (in->variant_type) { + case YAFFS_OBJECT_TYPE_UNKNOWN: + /* Should not happen */ + break; + case YAFFS_OBJECT_TYPE_FILE: + if (oh->parent_obj_id != YAFFS_OBJECTID_DELETED && + oh->parent_obj_id != YAFFS_OBJECTID_UNLINKED) + file_size = in->variant.file_variant.file_size; + yaffs_oh_size_load(oh, file_size); + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + oh->equiv_id = in->variant.hardlink_variant.equiv_id; + break; + case YAFFS_OBJECT_TYPE_SPECIAL: + /* Do nothing */ + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + /* Do nothing */ + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + alias = in->variant.symlink_variant.alias; + if (!alias) + alias = _Y("no alias"); + strncpy(oh->alias, alias, YAFFS_MAX_ALIAS_LENGTH); + oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0; + break; + } + + /* process any xattrib modifications */ + if (xmod) + yaffs_apply_xattrib_mod(in, (char *)buffer, xmod); + + /* Tags */ + memset(&new_tags, 0, sizeof(new_tags)); + in->serial++; + new_tags.chunk_id = 0; + new_tags.obj_id = in->obj_id; + new_tags.serial_number = in->serial; + + /* Add extra info for file header */ + new_tags.extra_available = 1; + new_tags.extra_parent_id = oh->parent_obj_id; + new_tags.extra_file_size = file_size; + new_tags.extra_is_shrink = oh->is_shrink; + new_tags.extra_equiv_id = oh->equiv_id; + new_tags.extra_shadows = (oh->shadows_obj > 0) ? 1 : 0; + new_tags.extra_obj_type = in->variant_type; + yaffs_verify_oh(in, oh, &new_tags, 1); + + /* Create new chunk in NAND */ + new_chunk_id = + yaffs_write_new_chunk(dev, buffer, &new_tags, + (prev_chunk_id > 0) ? 1 : 0); + + if (buffer) + yaffs_release_temp_buffer(dev, buffer); + + if (new_chunk_id < 0) + return new_chunk_id; + + in->hdr_chunk = new_chunk_id; + + if (prev_chunk_id > 0) + yaffs_chunk_del(dev, prev_chunk_id, 1, __LINE__); + + if (!yaffs_obj_cache_dirty(in)) + in->dirty = 0; + + /* If this was a shrink, then mark the block + * that the chunk lives on */ + if (is_shrink) { + bi = yaffs_get_block_info(in->my_dev, + new_chunk_id / + in->my_dev->param.chunks_per_block); + bi->has_shrink_hdr = 1; + } + + + return new_chunk_id; +} + +/*--------------------- File read/write ------------------------ + * Read and write have very similar structures. + * In general the read/write has three parts to it + * An incomplete chunk to start with (if the read/write is not chunk-aligned) + * Some complete chunks + * An incomplete chunk to end off with + * + * Curve-balls: the first chunk might also be the last chunk. + */ + +int yaffs_file_rd(struct yaffs_obj *in, u8 * buffer, loff_t offset, int n_bytes) +{ + int chunk; + u32 start; + int n_copy; + int n = n_bytes; + int n_done = 0; + struct yaffs_cache *cache; + struct yaffs_dev *dev; + + dev = in->my_dev; + + while (n > 0) { + yaffs_addr_to_chunk(dev, offset, &chunk, &start); + chunk++; + + /* OK now check for the curveball where the start and end are in + * the same chunk. + */ + if ((start + n) < dev->data_bytes_per_chunk) + n_copy = n; + else + n_copy = dev->data_bytes_per_chunk - start; + + cache = yaffs_find_chunk_cache(in, chunk); + + /* If the chunk is already in the cache or it is less than + * a whole chunk or we're using inband tags then use the cache + * (if there is caching) else bypass the cache. + */ + if (cache || n_copy != dev->data_bytes_per_chunk || + dev->param.inband_tags) { + if (dev->param.n_caches > 0) { + + /* If we can't find the data in the cache, + * then load it up. */ + + if (!cache) { + cache = + yaffs_grab_chunk_cache(in->my_dev); + cache->object = in; + cache->chunk_id = chunk; + cache->dirty = 0; + cache->locked = 0; + yaffs_rd_data_obj(in, chunk, + cache->data); + cache->n_bytes = 0; + } + + yaffs_use_cache(dev, cache, 0); + + cache->locked = 1; + + memcpy(buffer, &cache->data[start], n_copy); + + cache->locked = 0; + } else { + /* Read into the local buffer then copy.. */ + + u8 *local_buffer = + yaffs_get_temp_buffer(dev); + yaffs_rd_data_obj(in, chunk, local_buffer); + + memcpy(buffer, &local_buffer[start], n_copy); + + yaffs_release_temp_buffer(dev, local_buffer); + } + } else { + /* A full chunk. Read directly into the buffer. */ + yaffs_rd_data_obj(in, chunk, buffer); + } + n -= n_copy; + offset += n_copy; + buffer += n_copy; + n_done += n_copy; + } + return n_done; +} + +int yaffs_do_file_wr(struct yaffs_obj *in, const u8 *buffer, loff_t offset, + int n_bytes, int write_through) +{ + + int chunk; + u32 start; + int n_copy; + int n = n_bytes; + int n_done = 0; + int n_writeback; + loff_t start_write = offset; + int chunk_written = 0; + u32 n_bytes_read; + loff_t chunk_start; + struct yaffs_dev *dev; + + dev = in->my_dev; + + while (n > 0 && chunk_written >= 0) { + yaffs_addr_to_chunk(dev, offset, &chunk, &start); + + if (((loff_t)chunk) * + dev->data_bytes_per_chunk + start != offset || + start >= dev->data_bytes_per_chunk) { + yaffs_trace(YAFFS_TRACE_ERROR, + "AddrToChunk of offset %lld gives chunk %d start %d", + offset, chunk, start); + } + chunk++; /* File pos to chunk in file offset */ + + /* OK now check for the curveball where the start and end are in + * the same chunk. + */ + + if ((start + n) < dev->data_bytes_per_chunk) { + n_copy = n; + + /* Now calculate how many bytes to write back.... + * If we're overwriting and not writing to then end of + * file then we need to write back as much as was there + * before. + */ + + chunk_start = (((loff_t)(chunk - 1)) * + dev->data_bytes_per_chunk); + + if (chunk_start > in->variant.file_variant.file_size) + n_bytes_read = 0; /* Past end of file */ + else + n_bytes_read = + in->variant.file_variant.file_size - + chunk_start; + + if (n_bytes_read > dev->data_bytes_per_chunk) + n_bytes_read = dev->data_bytes_per_chunk; + + n_writeback = + (n_bytes_read > + (start + n)) ? n_bytes_read : (start + n); + + if (n_writeback < 0 || + n_writeback > dev->data_bytes_per_chunk) + BUG(); + + } else { + n_copy = dev->data_bytes_per_chunk - start; + n_writeback = dev->data_bytes_per_chunk; + } + + if (n_copy != dev->data_bytes_per_chunk || + !dev->param.cache_bypass_aligned || + dev->param.inband_tags) { + /* An incomplete start or end chunk (or maybe both + * start and end chunk), or we're using inband tags, + * or we're forcing writes through the cache, + * so we want to use the cache buffers. + */ + if (dev->param.n_caches > 0) { + struct yaffs_cache *cache; + + /* If we can't find the data in the cache, then + * load the cache */ + cache = yaffs_find_chunk_cache(in, chunk); + + if (!cache && + yaffs_check_alloc_available(dev, 1)) { + cache = yaffs_grab_chunk_cache(dev); + cache->object = in; + cache->chunk_id = chunk; + cache->dirty = 0; + cache->locked = 0; + yaffs_rd_data_obj(in, chunk, + cache->data); + } else if (cache && + !cache->dirty && + !yaffs_check_alloc_available(dev, + 1)) { + /* Drop the cache if it was a read cache + * item and no space check has been made + * for it. + */ + cache = NULL; + } + + if (cache) { + yaffs_use_cache(dev, cache, 1); + cache->locked = 1; + + memcpy(&cache->data[start], buffer, + n_copy); + + cache->locked = 0; + cache->n_bytes = n_writeback; + + if (write_through) { + chunk_written = + yaffs_wr_data_obj + (cache->object, + cache->chunk_id, + cache->data, + cache->n_bytes, 1); + cache->dirty = 0; + } + } else { + chunk_written = -1; /* fail write */ + } + } else { + /* An incomplete start or end chunk (or maybe + * both start and end chunk). Read into the + * local buffer then copy over and write back. + */ + + u8 *local_buffer = yaffs_get_temp_buffer(dev); + + yaffs_rd_data_obj(in, chunk, local_buffer); + memcpy(&local_buffer[start], buffer, n_copy); + + chunk_written = + yaffs_wr_data_obj(in, chunk, + local_buffer, + n_writeback, 0); + + yaffs_release_temp_buffer(dev, local_buffer); + } + } else { + /* A full chunk. Write directly from the buffer. */ + + chunk_written = + yaffs_wr_data_obj(in, chunk, buffer, + dev->data_bytes_per_chunk, 0); + + /* Since we've overwritten the cached data, + * we better invalidate it. */ + yaffs_invalidate_chunk_cache(in, chunk); + } + + if (chunk_written >= 0) { + n -= n_copy; + offset += n_copy; + buffer += n_copy; + n_done += n_copy; + } + } + + /* Update file object */ + + if ((start_write + n_done) > in->variant.file_variant.file_size) + in->variant.file_variant.file_size = (start_write + n_done); + + in->dirty = 1; + return n_done; +} + +int yaffs_wr_file(struct yaffs_obj *in, const u8 *buffer, loff_t offset, + int n_bytes, int write_through) +{ + yaffs2_handle_hole(in, offset); + return yaffs_do_file_wr(in, buffer, offset, n_bytes, write_through); +} + +/* ---------------------- File resizing stuff ------------------ */ + +static void yaffs_prune_chunks(struct yaffs_obj *in, loff_t new_size) +{ + + struct yaffs_dev *dev = in->my_dev; + loff_t old_size = in->variant.file_variant.file_size; + int i; + int chunk_id; + u32 dummy; + int last_del; + int start_del; + + if (old_size > 0) + yaffs_addr_to_chunk(dev, old_size - 1, &last_del, &dummy); + else + last_del = 0; + + yaffs_addr_to_chunk(dev, new_size + dev->data_bytes_per_chunk - 1, + &start_del, &dummy); + last_del++; + start_del++; + + /* Delete backwards so that we don't end up with holes if + * power is lost part-way through the operation. + */ + for (i = last_del; i >= start_del; i--) { + /* NB this could be optimised somewhat, + * eg. could retrieve the tags and write them without + * using yaffs_chunk_del + */ + + chunk_id = yaffs_find_del_file_chunk(in, i, NULL); + + if (chunk_id < 1) + continue; + + if (chunk_id < + (dev->internal_start_block * dev->param.chunks_per_block) || + chunk_id >= + ((dev->internal_end_block + 1) * + dev->param.chunks_per_block)) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "Found daft chunk_id %d for %d", + chunk_id, i); + } else { + in->n_data_chunks--; + yaffs_chunk_del(dev, chunk_id, 1, __LINE__); + } + } +} + +void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size) +{ + int new_full; + u32 new_partial; + struct yaffs_dev *dev = obj->my_dev; + + yaffs_addr_to_chunk(dev, new_size, &new_full, &new_partial); + + yaffs_prune_chunks(obj, new_size); + + if (new_partial != 0) { + int last_chunk = 1 + new_full; + u8 *local_buffer = yaffs_get_temp_buffer(dev); + + /* Rewrite the last chunk with its new size and zero pad */ + yaffs_rd_data_obj(obj, last_chunk, local_buffer); + memset(local_buffer + new_partial, 0, + dev->data_bytes_per_chunk - new_partial); + + yaffs_wr_data_obj(obj, last_chunk, local_buffer, + new_partial, 1); + + yaffs_release_temp_buffer(dev, local_buffer); + } + + obj->variant.file_variant.file_size = new_size; + + yaffs_prune_tree(dev, &obj->variant.file_variant); +} + +int yaffs_resize_file(struct yaffs_obj *in, loff_t new_size) +{ + struct yaffs_dev *dev = in->my_dev; + loff_t old_size = in->variant.file_variant.file_size; + + yaffs_flush_file_cache(in, 1); + yaffs_invalidate_whole_cache(in); + + yaffs_check_gc(dev, 0); + + if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) + return YAFFS_FAIL; + + if (new_size == old_size) + return YAFFS_OK; + + if (new_size > old_size) { + yaffs2_handle_hole(in, new_size); + in->variant.file_variant.file_size = new_size; + } else { + /* new_size < old_size */ + yaffs_resize_file_down(in, new_size); + } + + /* Write a new object header to reflect the resize. + * show we've shrunk the file, if need be + * Do this only if the file is not in the deleted directories + * and is not shadowed. + */ + if (in->parent && + !in->is_shadowed && + in->parent->obj_id != YAFFS_OBJECTID_UNLINKED && + in->parent->obj_id != YAFFS_OBJECTID_DELETED) + yaffs_update_oh(in, NULL, 0, 0, 0, NULL); + + return YAFFS_OK; +} + +int yaffs_flush_file(struct yaffs_obj *in, + int update_time, + int data_sync, + int discard_cache) +{ + if (!in->dirty) + return YAFFS_OK; + + yaffs_flush_file_cache(in, discard_cache); + + if (data_sync) + return YAFFS_OK; + + if (update_time) + yaffs_load_current_time(in, 0, 0); + + return (yaffs_update_oh(in, NULL, 0, 0, 0, NULL) >= 0) ? + YAFFS_OK : YAFFS_FAIL; +} + + +/* yaffs_del_file deletes the whole file data + * and the inode associated with the file. + * It does not delete the links associated with the file. + */ +static int yaffs_unlink_file_if_needed(struct yaffs_obj *in) +{ + int ret_val; + int del_now = 0; + struct yaffs_dev *dev = in->my_dev; + + if (!in->my_inode) + del_now = 1; + + if (del_now) { + ret_val = + yaffs_change_obj_name(in, in->my_dev->del_dir, + _Y("deleted"), 0, 0); + yaffs_trace(YAFFS_TRACE_TRACING, + "yaffs: immediate deletion of file %d", + in->obj_id); + in->deleted = 1; + in->my_dev->n_deleted_files++; + if (dev->param.disable_soft_del || dev->param.is_yaffs2) + yaffs_resize_file(in, 0); + yaffs_soft_del_file(in); + } else { + ret_val = + yaffs_change_obj_name(in, in->my_dev->unlinked_dir, + _Y("unlinked"), 0, 0); + } + return ret_val; +} + +static int yaffs_del_file(struct yaffs_obj *in) +{ + int ret_val = YAFFS_OK; + int deleted; /* Need to cache value on stack if in is freed */ + struct yaffs_dev *dev = in->my_dev; + + if (dev->param.disable_soft_del || dev->param.is_yaffs2) + yaffs_resize_file(in, 0); + + if (in->n_data_chunks > 0) { + /* Use soft deletion if there is data in the file. + * That won't be the case if it has been resized to zero. + */ + if (!in->unlinked) + ret_val = yaffs_unlink_file_if_needed(in); + + deleted = in->deleted; + + if (ret_val == YAFFS_OK && in->unlinked && !in->deleted) { + in->deleted = 1; + deleted = 1; + in->my_dev->n_deleted_files++; + yaffs_soft_del_file(in); + } + return deleted ? YAFFS_OK : YAFFS_FAIL; + } else { + /* The file has no data chunks so we toss it immediately */ + yaffs_free_tnode(in->my_dev, in->variant.file_variant.top); + in->variant.file_variant.top = NULL; + yaffs_generic_obj_del(in); + + return YAFFS_OK; + } +} + +int yaffs_is_non_empty_dir(struct yaffs_obj *obj) +{ + return (obj && + obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) && + !(list_empty(&obj->variant.dir_variant.children)); +} + +static int yaffs_del_dir(struct yaffs_obj *obj) +{ + /* First check that the directory is empty. */ + if (yaffs_is_non_empty_dir(obj)) + return YAFFS_FAIL; + + return yaffs_generic_obj_del(obj); +} + +static int yaffs_del_symlink(struct yaffs_obj *in) +{ + kfree(in->variant.symlink_variant.alias); + in->variant.symlink_variant.alias = NULL; + + return yaffs_generic_obj_del(in); +} + +static int yaffs_del_link(struct yaffs_obj *in) +{ + /* remove this hardlink from the list associated with the equivalent + * object + */ + list_del_init(&in->hard_links); + return yaffs_generic_obj_del(in); +} + +int yaffs_del_obj(struct yaffs_obj *obj) +{ + int ret_val = -1; + + switch (obj->variant_type) { + case YAFFS_OBJECT_TYPE_FILE: + ret_val = yaffs_del_file(obj); + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + if (!list_empty(&obj->variant.dir_variant.dirty)) { + yaffs_trace(YAFFS_TRACE_BACKGROUND, + "Remove object %d from dirty directories", + obj->obj_id); + list_del_init(&obj->variant.dir_variant.dirty); + } + return yaffs_del_dir(obj); + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + ret_val = yaffs_del_symlink(obj); + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + ret_val = yaffs_del_link(obj); + break; + case YAFFS_OBJECT_TYPE_SPECIAL: + ret_val = yaffs_generic_obj_del(obj); + break; + case YAFFS_OBJECT_TYPE_UNKNOWN: + ret_val = 0; + break; /* should not happen. */ + } + return ret_val; +} + + +static void yaffs_empty_dir_to_dir(struct yaffs_obj *from_dir, + struct yaffs_obj *to_dir) +{ + struct yaffs_obj *obj; + struct list_head *lh; + struct list_head *n; + + list_for_each_safe(lh, n, &from_dir->variant.dir_variant.children) { + obj = list_entry(lh, struct yaffs_obj, siblings); + yaffs_add_obj_to_dir(to_dir, obj); + } +} + +struct yaffs_obj *yaffs_retype_obj(struct yaffs_obj *obj, + enum yaffs_obj_type type) +{ + /* Tear down the old variant */ + switch (obj->variant_type) { + case YAFFS_OBJECT_TYPE_FILE: + /* Nuke file data */ + yaffs_resize_file(obj, 0); + yaffs_free_tnode(obj->my_dev, obj->variant.file_variant.top); + obj->variant.file_variant.top = NULL; + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + /* Put the children in lost and found. */ + yaffs_empty_dir_to_dir(obj, obj->my_dev->lost_n_found); + if (!list_empty(&obj->variant.dir_variant.dirty)) + list_del_init(&obj->variant.dir_variant.dirty); + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + /* Nuke symplink data */ + kfree(obj->variant.symlink_variant.alias); + obj->variant.symlink_variant.alias = NULL; + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + list_del_init(&obj->hard_links); + break; + default: + break; + } + + memset(&obj->variant, 0, sizeof(obj->variant)); + + /*Set up new variant if the memset is not enough. */ + switch (type) { + case YAFFS_OBJECT_TYPE_DIRECTORY: + INIT_LIST_HEAD(&obj->variant.dir_variant.children); + INIT_LIST_HEAD(&obj->variant.dir_variant.dirty); + break; + case YAFFS_OBJECT_TYPE_FILE: + case YAFFS_OBJECT_TYPE_SYMLINK: + case YAFFS_OBJECT_TYPE_HARDLINK: + default: + break; + } + + obj->variant_type = type; + + return obj; + +} + +static int yaffs_unlink_worker(struct yaffs_obj *obj) +{ + int del_now = 0; + + if (!obj) + return YAFFS_FAIL; + + if (!obj->my_inode) + del_now = 1; + + yaffs_update_parent(obj->parent); + + if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) { + return yaffs_del_link(obj); + } else if (!list_empty(&obj->hard_links)) { + /* Curve ball: We're unlinking an object that has a hardlink. + * + * This problem arises because we are not strictly following + * The Linux link/inode model. + * + * We can't really delete the object. + * Instead, we do the following: + * - Select a hardlink. + * - Unhook it from the hard links + * - Move it from its parent directory so that the rename works. + * - Rename the object to the hardlink's name. + * - Delete the hardlink + */ + + struct yaffs_obj *hl; + struct yaffs_obj *parent; + int ret_val; + YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; + + hl = list_entry(obj->hard_links.next, struct yaffs_obj, + hard_links); + + yaffs_get_obj_name(hl, name, YAFFS_MAX_NAME_LENGTH + 1); + parent = hl->parent; + + list_del_init(&hl->hard_links); + + yaffs_add_obj_to_dir(obj->my_dev->unlinked_dir, hl); + + ret_val = yaffs_change_obj_name(obj, parent, name, 0, 0); + + if (ret_val == YAFFS_OK) + ret_val = yaffs_generic_obj_del(hl); + + return ret_val; + + } else if (del_now) { + switch (obj->variant_type) { + case YAFFS_OBJECT_TYPE_FILE: + return yaffs_del_file(obj); + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + list_del_init(&obj->variant.dir_variant.dirty); + return yaffs_del_dir(obj); + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + return yaffs_del_symlink(obj); + break; + case YAFFS_OBJECT_TYPE_SPECIAL: + return yaffs_generic_obj_del(obj); + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + case YAFFS_OBJECT_TYPE_UNKNOWN: + default: + return YAFFS_FAIL; + } + } else if (yaffs_is_non_empty_dir(obj)) { + return YAFFS_FAIL; + } else { + return yaffs_change_obj_name(obj, obj->my_dev->unlinked_dir, + _Y("unlinked"), 0, 0); + } +} + +static int yaffs_unlink_obj(struct yaffs_obj *obj) +{ + if (obj && obj->unlink_allowed) + return yaffs_unlink_worker(obj); + + return YAFFS_FAIL; +} + +int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR *name) +{ + struct yaffs_obj *obj; + + obj = yaffs_find_by_name(dir, name); + return yaffs_unlink_obj(obj); +} + +/* Note: + * If old_name is NULL then we take old_dir as the object to be renamed. + */ +int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR *old_name, + struct yaffs_obj *new_dir, const YCHAR *new_name) +{ + struct yaffs_obj *obj = NULL; + struct yaffs_obj *existing_target = NULL; + int force = 0; + int result; + struct yaffs_dev *dev; + + if (!old_dir || old_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + BUG(); + return YAFFS_FAIL; + } + if (!new_dir || new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + BUG(); + return YAFFS_FAIL; + } + + dev = old_dir->my_dev; + +#ifdef CONFIG_YAFFS_CASE_INSENSITIVE + /* Special case for case insemsitive systems. + * While look-up is case insensitive, the name isn't. + * Therefore we might want to change x.txt to X.txt + */ + if (old_dir == new_dir && + old_name && new_name && + strcmp(old_name, new_name) == 0) + force = 1; +#endif + + if (strnlen(new_name, YAFFS_MAX_NAME_LENGTH + 1) > + YAFFS_MAX_NAME_LENGTH) + /* ENAMETOOLONG */ + return YAFFS_FAIL; + + if (old_name) + obj = yaffs_find_by_name(old_dir, old_name); + else{ + obj = old_dir; + old_dir = obj->parent; + } + + if (obj && obj->rename_allowed) { + /* Now handle an existing target, if there is one */ + existing_target = yaffs_find_by_name(new_dir, new_name); + if (yaffs_is_non_empty_dir(existing_target)) { + return YAFFS_FAIL; /* ENOTEMPTY */ + } else if (existing_target && existing_target != obj) { + /* Nuke the target first, using shadowing, + * but only if it isn't the same object. + * + * Note we must disable gc here otherwise it can mess + * up the shadowing. + * + */ + dev->gc_disable = 1; + yaffs_change_obj_name(obj, new_dir, new_name, force, + existing_target->obj_id); + existing_target->is_shadowed = 1; + yaffs_unlink_obj(existing_target); + dev->gc_disable = 0; + } + + result = yaffs_change_obj_name(obj, new_dir, new_name, 1, 0); + + yaffs_update_parent(old_dir); + if (new_dir != old_dir) + yaffs_update_parent(new_dir); + + return result; + } + return YAFFS_FAIL; +} + +/*----------------------- Initialisation Scanning ---------------------- */ + +void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id, + int backward_scanning) +{ + struct yaffs_obj *obj; + + if (backward_scanning) { + /* Handle YAFFS2 case (backward scanning) + * If the shadowed object exists then ignore. + */ + obj = yaffs_find_by_number(dev, obj_id); + if (obj) + return; + } + + /* Let's create it (if it does not exist) assuming it is a file so that + * it can do shrinking etc. + * We put it in unlinked dir to be cleaned up after the scanning + */ + obj = + yaffs_find_or_create_by_number(dev, obj_id, YAFFS_OBJECT_TYPE_FILE); + if (!obj) + return; + obj->is_shadowed = 1; + yaffs_add_obj_to_dir(dev->unlinked_dir, obj); + obj->variant.file_variant.shrink_size = 0; + obj->valid = 1; /* So that we don't read any other info. */ +} + +void yaffs_link_fixup(struct yaffs_dev *dev, struct list_head *hard_list) +{ + struct list_head *lh; + struct list_head *save; + struct yaffs_obj *hl; + struct yaffs_obj *in; + + list_for_each_safe(lh, save, hard_list) { + hl = list_entry(lh, struct yaffs_obj, hard_links); + in = yaffs_find_by_number(dev, + hl->variant.hardlink_variant.equiv_id); + + if (in) { + /* Add the hardlink pointers */ + hl->variant.hardlink_variant.equiv_obj = in; + list_add(&hl->hard_links, &in->hard_links); + } else { + /* Todo Need to report/handle this better. + * Got a problem... hardlink to a non-existant object + */ + hl->variant.hardlink_variant.equiv_obj = NULL; + INIT_LIST_HEAD(&hl->hard_links); + } + } +} + +static void yaffs_strip_deleted_objs(struct yaffs_dev *dev) +{ + /* + * Sort out state of unlinked and deleted objects after scanning. + */ + struct list_head *i; + struct list_head *n; + struct yaffs_obj *l; + + if (dev->read_only) + return; + + /* Soft delete all the unlinked files */ + list_for_each_safe(i, n, + &dev->unlinked_dir->variant.dir_variant.children) { + l = list_entry(i, struct yaffs_obj, siblings); + yaffs_del_obj(l); + } + + list_for_each_safe(i, n, &dev->del_dir->variant.dir_variant.children) { + l = list_entry(i, struct yaffs_obj, siblings); + yaffs_del_obj(l); + } +} + +/* + * This code iterates through all the objects making sure that they are rooted. + * Any unrooted objects are re-rooted in lost+found. + * An object needs to be in one of: + * - Directly under deleted, unlinked + * - Directly or indirectly under root. + * + * Note: + * This code assumes that we don't ever change the current relationships + * between directories: + * root_dir->parent == unlinked_dir->parent == del_dir->parent == NULL + * lost-n-found->parent == root_dir + * + * This fixes the problem where directories might have inadvertently been + * deleted leaving the object "hanging" without being rooted in the + * directory tree. + */ + +static int yaffs_has_null_parent(struct yaffs_dev *dev, struct yaffs_obj *obj) +{ + return (obj == dev->del_dir || + obj == dev->unlinked_dir || obj == dev->root_dir); +} + +static void yaffs_fix_hanging_objs(struct yaffs_dev *dev) +{ + struct yaffs_obj *obj; + struct yaffs_obj *parent; + int i; + struct list_head *lh; + struct list_head *n; + int depth_limit; + int hanging; + + if (dev->read_only) + return; + + /* Iterate through the objects in each hash entry, + * looking at each object. + * Make sure it is rooted. + */ + + for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { + list_for_each_safe(lh, n, &dev->obj_bucket[i].list) { + obj = list_entry(lh, struct yaffs_obj, hash_link); + parent = obj->parent; + + if (yaffs_has_null_parent(dev, obj)) { + /* These directories are not hanging */ + hanging = 0; + } else if (!parent || + parent->variant_type != + YAFFS_OBJECT_TYPE_DIRECTORY) { + hanging = 1; + } else if (yaffs_has_null_parent(dev, parent)) { + hanging = 0; + } else { + /* + * Need to follow the parent chain to + * see if it is hanging. + */ + hanging = 0; + depth_limit = 100; + + while (parent != dev->root_dir && + parent->parent && + parent->parent->variant_type == + YAFFS_OBJECT_TYPE_DIRECTORY && + depth_limit > 0) { + parent = parent->parent; + depth_limit--; + } + if (parent != dev->root_dir) + hanging = 1; + } + if (hanging) { + yaffs_trace(YAFFS_TRACE_SCAN, + "Hanging object %d moved to lost and found", + obj->obj_id); + yaffs_add_obj_to_dir(dev->lost_n_found, obj); + } + } + } +} + +/* + * Delete directory contents for cleaning up lost and found. + */ +static void yaffs_del_dir_contents(struct yaffs_obj *dir) +{ + struct yaffs_obj *obj; + struct list_head *lh; + struct list_head *n; + + if (dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) + BUG(); + + list_for_each_safe(lh, n, &dir->variant.dir_variant.children) { + obj = list_entry(lh, struct yaffs_obj, siblings); + if (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) + yaffs_del_dir_contents(obj); + yaffs_trace(YAFFS_TRACE_SCAN, + "Deleting lost_found object %d", + obj->obj_id); + yaffs_unlink_obj(obj); + } +} + +static void yaffs_empty_l_n_f(struct yaffs_dev *dev) +{ + yaffs_del_dir_contents(dev->lost_n_found); +} + + +struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *directory, + const YCHAR *name) +{ + int sum; + struct list_head *i; + YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1]; + struct yaffs_obj *l; + + if (!name) + return NULL; + + if (!directory) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "tragedy: yaffs_find_by_name: null pointer directory" + ); + BUG(); + return NULL; + } + if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "tragedy: yaffs_find_by_name: non-directory" + ); + BUG(); + } + + sum = yaffs_calc_name_sum(name); + + list_for_each(i, &directory->variant.dir_variant.children) { + l = list_entry(i, struct yaffs_obj, siblings); + + if (l->parent != directory) + BUG(); + + yaffs_check_obj_details_loaded(l); + + /* Special case for lost-n-found */ + if (l->obj_id == YAFFS_OBJECTID_LOSTNFOUND) { + if (!strcmp(name, YAFFS_LOSTNFOUND_NAME)) + return l; + } else if (l->sum == sum || l->hdr_chunk <= 0) { + /* LostnFound chunk called Objxxx + * Do a real check + */ + yaffs_get_obj_name(l, buffer, + YAFFS_MAX_NAME_LENGTH + 1); + if (!strncmp(name, buffer, YAFFS_MAX_NAME_LENGTH)) + return l; + } + } + return NULL; +} + +/* GetEquivalentObject dereferences any hard links to get to the + * actual object. + */ + +struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj) +{ + if (obj && obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) { + obj = obj->variant.hardlink_variant.equiv_obj; + yaffs_check_obj_details_loaded(obj); + } + return obj; +} + +/* + * A note or two on object names. + * * If the object name is missing, we then make one up in the form objnnn + * + * * ASCII names are stored in the object header's name field from byte zero + * * Unicode names are historically stored starting from byte zero. + * + * Then there are automatic Unicode names... + * The purpose of these is to save names in a way that can be read as + * ASCII or Unicode names as appropriate, thus allowing a Unicode and ASCII + * system to share files. + * + * These automatic unicode are stored slightly differently... + * - If the name can fit in the ASCII character space then they are saved as + * ascii names as per above. + * - If the name needs Unicode then the name is saved in Unicode + * starting at oh->name[1]. + + */ +static void yaffs_fix_null_name(struct yaffs_obj *obj, YCHAR *name, + int buffer_size) +{ + /* Create an object name if we could not find one. */ + if (strnlen(name, YAFFS_MAX_NAME_LENGTH) == 0) { + YCHAR local_name[20]; + YCHAR num_string[20]; + YCHAR *x = &num_string[19]; + unsigned v = obj->obj_id; + num_string[19] = 0; + while (v > 0) { + x--; + *x = '0' + (v % 10); + v /= 10; + } + /* make up a name */ + strcpy(local_name, YAFFS_LOSTNFOUND_PREFIX); + strcat(local_name, x); + strncpy(name, local_name, buffer_size - 1); + } +} + +int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR *name, int buffer_size) +{ + memset(name, 0, buffer_size * sizeof(YCHAR)); + yaffs_check_obj_details_loaded(obj); + if (obj->obj_id == YAFFS_OBJECTID_LOSTNFOUND) { + strncpy(name, YAFFS_LOSTNFOUND_NAME, buffer_size - 1); + } else if (obj->short_name[0]) { + strcpy(name, obj->short_name); + } else if (obj->hdr_chunk > 0) { + int result; + u8 *buffer = yaffs_get_temp_buffer(obj->my_dev); + + struct yaffs_obj_hdr *oh = (struct yaffs_obj_hdr *)buffer; + + memset(buffer, 0, obj->my_dev->data_bytes_per_chunk); + + if (obj->hdr_chunk > 0) { + result = yaffs_rd_chunk_tags_nand(obj->my_dev, + obj->hdr_chunk, + buffer, NULL); + } + yaffs_load_name_from_oh(obj->my_dev, name, oh->name, + buffer_size); + + yaffs_release_temp_buffer(obj->my_dev, buffer); + } + + yaffs_fix_null_name(obj, name, buffer_size); + + return strnlen(name, YAFFS_MAX_NAME_LENGTH); +} + +loff_t yaffs_get_obj_length(struct yaffs_obj *obj) +{ + /* Dereference any hard linking */ + obj = yaffs_get_equivalent_obj(obj); + + if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) + return obj->variant.file_variant.file_size; + if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) { + if (!obj->variant.symlink_variant.alias) + return 0; + return strnlen(obj->variant.symlink_variant.alias, + YAFFS_MAX_ALIAS_LENGTH); + } else { + /* Only a directory should drop through to here */ + return obj->my_dev->data_bytes_per_chunk; + } +} + +int yaffs_get_obj_link_count(struct yaffs_obj *obj) +{ + int count = 0; + struct list_head *i; + + if (!obj->unlinked) + count++; /* the object itself */ + + list_for_each(i, &obj->hard_links) + count++; /* add the hard links; */ + + return count; +} + +int yaffs_get_obj_inode(struct yaffs_obj *obj) +{ + obj = yaffs_get_equivalent_obj(obj); + + return obj->obj_id; +} + +unsigned yaffs_get_obj_type(struct yaffs_obj *obj) +{ + obj = yaffs_get_equivalent_obj(obj); + + switch (obj->variant_type) { + case YAFFS_OBJECT_TYPE_FILE: + return DT_REG; + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + return DT_DIR; + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + return DT_LNK; + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + return DT_REG; + break; + case YAFFS_OBJECT_TYPE_SPECIAL: + if (S_ISFIFO(obj->yst_mode)) + return DT_FIFO; + if (S_ISCHR(obj->yst_mode)) + return DT_CHR; + if (S_ISBLK(obj->yst_mode)) + return DT_BLK; + if (S_ISSOCK(obj->yst_mode)) + return DT_SOCK; + return DT_REG; + break; + default: + return DT_REG; + break; + } +} + +YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj) +{ + obj = yaffs_get_equivalent_obj(obj); + if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) + return yaffs_clone_str(obj->variant.symlink_variant.alias); + else + return yaffs_clone_str(_Y("")); +} + +/*--------------------------- Initialisation code -------------------------- */ + +static int yaffs_check_dev_fns(struct yaffs_dev *dev) +{ + struct yaffs_driver *drv = &dev->drv; + struct yaffs_tags_handler *tagger = &dev->tagger; + + /* Common functions, gotta have */ + if (!drv->drv_read_chunk_fn || + !drv->drv_write_chunk_fn || + !drv->drv_erase_fn) + return 0; + + if (dev->param.is_yaffs2 && + (!drv->drv_mark_bad_fn || !drv->drv_check_bad_fn)) + return 0; + + /* Install the default tags marshalling functions if needed. */ + yaffs_tags_compat_install(dev); + yaffs_tags_marshall_install(dev); + + /* Check we now have the marshalling functions required. */ + if (!tagger->write_chunk_tags_fn || + !tagger->read_chunk_tags_fn || + !tagger->query_block_fn || + !tagger->mark_bad_fn) + return 0; + + return 1; +} + +static int yaffs_create_initial_dir(struct yaffs_dev *dev) +{ + /* Initialise the unlinked, deleted, root and lost+found directories */ + dev->lost_n_found = dev->root_dir = NULL; + dev->unlinked_dir = dev->del_dir = NULL; + dev->unlinked_dir = + yaffs_create_fake_dir(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR); + dev->del_dir = + yaffs_create_fake_dir(dev, YAFFS_OBJECTID_DELETED, S_IFDIR); + dev->root_dir = + yaffs_create_fake_dir(dev, YAFFS_OBJECTID_ROOT, + YAFFS_ROOT_MODE | S_IFDIR); + dev->lost_n_found = + yaffs_create_fake_dir(dev, YAFFS_OBJECTID_LOSTNFOUND, + YAFFS_LOSTNFOUND_MODE | S_IFDIR); + + if (dev->lost_n_found && dev->root_dir && dev->unlinked_dir + && dev->del_dir) { + yaffs_add_obj_to_dir(dev->root_dir, dev->lost_n_found); + return YAFFS_OK; + } + return YAFFS_FAIL; +} + +/* Low level init. + * Typically only used by yaffs_guts_initialise, but also used by the + * Low level yaffs driver tests. + */ + +int yaffs_guts_ll_init(struct yaffs_dev *dev) +{ + + + yaffs_trace(YAFFS_TRACE_TRACING, "yaffs: yaffs_ll_init()"); + + if (!dev) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs: Need a device" + ); + return YAFFS_FAIL; + } + + if (dev->ll_init) + return YAFFS_OK; + + dev->internal_start_block = dev->param.start_block; + dev->internal_end_block = dev->param.end_block; + dev->block_offset = 0; + dev->chunk_offset = 0; + dev->n_free_chunks = 0; + + dev->gc_block = 0; + + if (dev->param.start_block == 0) { + dev->internal_start_block = dev->param.start_block + 1; + dev->internal_end_block = dev->param.end_block + 1; + dev->block_offset = 1; + dev->chunk_offset = dev->param.chunks_per_block; + } + + /* Check geometry parameters. */ + + if ((!dev->param.inband_tags && dev->param.is_yaffs2 && + dev->param.total_bytes_per_chunk < 1024) || + (!dev->param.is_yaffs2 && + dev->param.total_bytes_per_chunk < 512) || + (dev->param.inband_tags && !dev->param.is_yaffs2) || + dev->param.chunks_per_block < 2 || + dev->param.n_reserved_blocks < 2 || + dev->internal_start_block <= 0 || + dev->internal_end_block <= 0 || + dev->internal_end_block <= + (dev->internal_start_block + dev->param.n_reserved_blocks + 2) + ) { + /* otherwise it is too small */ + yaffs_trace(YAFFS_TRACE_ALWAYS, + "NAND geometry problems: chunk size %d, type is yaffs%s, inband_tags %d ", + dev->param.total_bytes_per_chunk, + dev->param.is_yaffs2 ? "2" : "", + dev->param.inband_tags); + return YAFFS_FAIL; + } + + /* Sort out space for inband tags, if required */ + if (dev->param.inband_tags) + dev->data_bytes_per_chunk = + dev->param.total_bytes_per_chunk - + sizeof(struct yaffs_packed_tags2_tags_only); + else + dev->data_bytes_per_chunk = dev->param.total_bytes_per_chunk; + + /* Got the right mix of functions? */ + if (!yaffs_check_dev_fns(dev)) { + /* Function missing */ + yaffs_trace(YAFFS_TRACE_ALWAYS, + "device function(s) missing or wrong"); + + return YAFFS_FAIL; + } + + if (yaffs_init_nand(dev) != YAFFS_OK) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "InitialiseNAND failed"); + return YAFFS_FAIL; + } + + return YAFFS_OK; +} + + +int yaffs_guts_format_dev(struct yaffs_dev *dev) +{ + int i; + enum yaffs_block_state state; + u32 dummy; + + if(yaffs_guts_ll_init(dev) != YAFFS_OK) + return YAFFS_FAIL; + + if(dev->is_mounted) + return YAFFS_FAIL; + + for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { + yaffs_query_init_block_state(dev, i, &state, &dummy); + if (state != YAFFS_BLOCK_STATE_DEAD) + yaffs_erase_block(dev, i); + } + + return YAFFS_OK; +} + + +int yaffs_guts_initialise(struct yaffs_dev *dev) +{ + int init_failed = 0; + unsigned x; + int bits; + + if(yaffs_guts_ll_init(dev) != YAFFS_OK) + return YAFFS_FAIL; + + if (dev->is_mounted) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "device already mounted"); + return YAFFS_FAIL; + } + + dev->is_mounted = 1; + + /* OK now calculate a few things for the device */ + + /* + * Calculate all the chunk size manipulation numbers: + */ + x = dev->data_bytes_per_chunk; + /* We always use dev->chunk_shift and dev->chunk_div */ + dev->chunk_shift = calc_shifts(x); + x >>= dev->chunk_shift; + dev->chunk_div = x; + /* We only use chunk mask if chunk_div is 1 */ + dev->chunk_mask = (1 << dev->chunk_shift) - 1; + + /* + * Calculate chunk_grp_bits. + * We need to find the next power of 2 > than internal_end_block + */ + + x = dev->param.chunks_per_block * (dev->internal_end_block + 1); + + bits = calc_shifts_ceiling(x); + + /* Set up tnode width if wide tnodes are enabled. */ + if (!dev->param.wide_tnodes_disabled) { + /* bits must be even so that we end up with 32-bit words */ + if (bits & 1) + bits++; + if (bits < 16) + dev->tnode_width = 16; + else + dev->tnode_width = bits; + } else { + dev->tnode_width = 16; + } + + dev->tnode_mask = (1 << dev->tnode_width) - 1; + + /* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled), + * so if the bitwidth of the + * chunk range we're using is greater than 16 we need + * to figure out chunk shift and chunk_grp_size + */ + + if (bits <= dev->tnode_width) + dev->chunk_grp_bits = 0; + else + dev->chunk_grp_bits = bits - dev->tnode_width; + + dev->tnode_size = (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8; + if (dev->tnode_size < sizeof(struct yaffs_tnode)) + dev->tnode_size = sizeof(struct yaffs_tnode); + + dev->chunk_grp_size = 1 << dev->chunk_grp_bits; + + if (dev->param.chunks_per_block < dev->chunk_grp_size) { + /* We have a problem because the soft delete won't work if + * the chunk group size > chunks per block. + * This can be remedied by using larger "virtual blocks". + */ + yaffs_trace(YAFFS_TRACE_ALWAYS, "chunk group too large"); + + return YAFFS_FAIL; + } + + /* Finished verifying the device, continue with initialisation */ + + /* More device initialisation */ + dev->all_gcs = 0; + dev->passive_gc_count = 0; + dev->oldest_dirty_gc_count = 0; + dev->bg_gcs = 0; + dev->gc_block_finder = 0; + dev->buffered_block = -1; + dev->doing_buffered_block_rewrite = 0; + dev->n_deleted_files = 0; + dev->n_bg_deletions = 0; + dev->n_unlinked_files = 0; + dev->n_ecc_fixed = 0; + dev->n_ecc_unfixed = 0; + dev->n_tags_ecc_fixed = 0; + dev->n_tags_ecc_unfixed = 0; + dev->n_erase_failures = 0; + dev->n_erased_blocks = 0; + dev->gc_disable = 0; + dev->has_pending_prioritised_gc = 1; + /* Assume the worst for now, will get fixed on first GC */ + INIT_LIST_HEAD(&dev->dirty_dirs); + dev->oldest_dirty_seq = 0; + dev->oldest_dirty_block = 0; + + /* Initialise temporary buffers and caches. */ + if (!yaffs_init_tmp_buffers(dev)) + init_failed = 1; + + dev->cache = NULL; + dev->gc_cleanup_list = NULL; + + if (!init_failed && dev->param.n_caches > 0) { + int i; + void *buf; + int cache_bytes = + dev->param.n_caches * sizeof(struct yaffs_cache); + + if (dev->param.n_caches > YAFFS_MAX_SHORT_OP_CACHES) + dev->param.n_caches = YAFFS_MAX_SHORT_OP_CACHES; + + dev->cache = kmalloc(cache_bytes, GFP_NOFS); + + buf = (u8 *) dev->cache; + + if (dev->cache) + memset(dev->cache, 0, cache_bytes); + + for (i = 0; i < dev->param.n_caches && buf; i++) { + dev->cache[i].object = NULL; + dev->cache[i].last_use = 0; + dev->cache[i].dirty = 0; + dev->cache[i].data = buf = + kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS); + } + if (!buf) + init_failed = 1; + + dev->cache_last_use = 0; + } + + dev->cache_hits = 0; + + if (!init_failed) { + dev->gc_cleanup_list = + kmalloc(dev->param.chunks_per_block * sizeof(u32), + GFP_NOFS); + if (!dev->gc_cleanup_list) + init_failed = 1; + } + + if (dev->param.is_yaffs2) + dev->param.use_header_file_size = 1; + + if (!init_failed && !yaffs_init_blocks(dev)) + init_failed = 1; + + yaffs_init_tnodes_and_objs(dev); + + if (!init_failed && !yaffs_create_initial_dir(dev)) + init_failed = 1; + + if (!init_failed && dev->param.is_yaffs2 && + !dev->param.disable_summary && + !yaffs_summary_init(dev)) + init_failed = 1; + + if (!init_failed) { + /* Now scan the flash. */ + if (dev->param.is_yaffs2) { + if (yaffs2_checkpt_restore(dev)) { + yaffs_check_obj_details_loaded(dev->root_dir); + yaffs_trace(YAFFS_TRACE_CHECKPOINT | + YAFFS_TRACE_MOUNT, + "yaffs: restored from checkpoint" + ); + } else { + + /* Clean up the mess caused by an aborted + * checkpoint load then scan backwards. + */ + yaffs_deinit_blocks(dev); + + yaffs_deinit_tnodes_and_objs(dev); + + dev->n_erased_blocks = 0; + dev->n_free_chunks = 0; + dev->alloc_block = -1; + dev->alloc_page = -1; + dev->n_deleted_files = 0; + dev->n_unlinked_files = 0; + dev->n_bg_deletions = 0; + + if (!init_failed && !yaffs_init_blocks(dev)) + init_failed = 1; + + yaffs_init_tnodes_and_objs(dev); + + if (!init_failed + && !yaffs_create_initial_dir(dev)) + init_failed = 1; + + if (!init_failed && !yaffs2_scan_backwards(dev)) + init_failed = 1; + } + } else if (!yaffs1_scan(dev)) { + init_failed = 1; + } + + yaffs_strip_deleted_objs(dev); + yaffs_fix_hanging_objs(dev); + if (dev->param.empty_lost_n_found) + yaffs_empty_l_n_f(dev); + } + + if (init_failed) { + /* Clean up the mess */ + yaffs_trace(YAFFS_TRACE_TRACING, + "yaffs: yaffs_guts_initialise() aborted."); + + yaffs_deinitialise(dev); + return YAFFS_FAIL; + } + + /* Zero out stats */ + dev->n_page_reads = 0; + dev->n_page_writes = 0; + dev->n_erasures = 0; + dev->n_gc_copies = 0; + dev->n_retried_writes = 0; + + dev->n_retired_blocks = 0; + + yaffs_verify_free_chunks(dev); + yaffs_verify_blocks(dev); + + /* Clean up any aborted checkpoint data */ + if (!dev->is_checkpointed && dev->blocks_in_checkpt > 0) + yaffs2_checkpt_invalidate(dev); + + yaffs_trace(YAFFS_TRACE_TRACING, + "yaffs: yaffs_guts_initialise() done."); + return YAFFS_OK; +} + +void yaffs_deinitialise(struct yaffs_dev *dev) +{ + if (dev->is_mounted) { + int i; + + yaffs_deinit_blocks(dev); + yaffs_deinit_tnodes_and_objs(dev); + yaffs_summary_deinit(dev); + + if (dev->param.n_caches > 0 && dev->cache) { + + for (i = 0; i < dev->param.n_caches; i++) { + kfree(dev->cache[i].data); + dev->cache[i].data = NULL; + } + + kfree(dev->cache); + dev->cache = NULL; + } + + kfree(dev->gc_cleanup_list); + + for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { + kfree(dev->temp_buffer[i].buffer); + dev->temp_buffer[i].buffer = NULL; + } + + kfree(dev->checkpt_buffer); + dev->checkpt_buffer = NULL; + kfree(dev->checkpt_block_list); + dev->checkpt_block_list = NULL; + + dev->is_mounted = 0; + + yaffs_deinit_nand(dev); + } +} + +int yaffs_count_free_chunks(struct yaffs_dev *dev) +{ + int n_free = 0; + int b; + struct yaffs_block_info *blk; + + blk = dev->block_info; + for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) { + switch (blk->block_state) { + case YAFFS_BLOCK_STATE_EMPTY: + case YAFFS_BLOCK_STATE_ALLOCATING: + case YAFFS_BLOCK_STATE_COLLECTING: + case YAFFS_BLOCK_STATE_FULL: + n_free += + (dev->param.chunks_per_block - blk->pages_in_use + + blk->soft_del_pages); + break; + default: + break; + } + blk++; + } + return n_free; +} + +int yaffs_get_n_free_chunks(struct yaffs_dev *dev) +{ + /* This is what we report to the outside world */ + int n_free; + int n_dirty_caches; + int blocks_for_checkpt; + int i; + + n_free = dev->n_free_chunks; + n_free += dev->n_deleted_files; + + /* Now count and subtract the number of dirty chunks in the cache. */ + + for (n_dirty_caches = 0, i = 0; i < dev->param.n_caches; i++) { + if (dev->cache[i].dirty) + n_dirty_caches++; + } + + n_free -= n_dirty_caches; + + n_free -= + ((dev->param.n_reserved_blocks + 1) * dev->param.chunks_per_block); + + /* Now figure checkpoint space and report that... */ + blocks_for_checkpt = yaffs_calc_checkpt_blocks_required(dev); + + n_free -= (blocks_for_checkpt * dev->param.chunks_per_block); + + if (n_free < 0) + n_free = 0; + + return n_free; +} + + + +/* + * Marshalling functions to get loff_t file sizes into and out of + * object headers. + */ +void yaffs_oh_size_load(struct yaffs_obj_hdr *oh, loff_t fsize) +{ + oh->file_size_low = (fsize & 0xFFFFFFFF); + oh->file_size_high = ((fsize >> 32) & 0xFFFFFFFF); +} + +loff_t yaffs_oh_to_size(struct yaffs_obj_hdr *oh) +{ + loff_t retval; + + if (sizeof(loff_t) >= 8 && ~(oh->file_size_high)) + retval = (((loff_t) oh->file_size_high) << 32) | + (((loff_t) oh->file_size_low) & 0xFFFFFFFF); + else + retval = (loff_t) oh->file_size_low; + + return retval; +} + + +void yaffs_count_blocks_by_state(struct yaffs_dev *dev, int bs[10]) +{ + int i; + struct yaffs_block_info *bi; + int s; + + for(i = 0; i < 10; i++) + bs[i] = 0; + + for(i = dev->internal_start_block; i <= dev->internal_end_block; i++) { + bi = yaffs_get_block_info(dev, i); + s = bi->block_state; + if(s > YAFFS_BLOCK_STATE_DEAD || s < YAFFS_BLOCK_STATE_UNKNOWN) + bs[0]++; + else + bs[s]++; + } +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_guts.h b/target/linux/generic/files/fs/yaffs2/yaffs_guts.h new file mode 100644 index 0000000..231f8ac --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_guts.h @@ -0,0 +1,1010 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_GUTS_H__ +#define __YAFFS_GUTS_H__ + +#include "yportenv.h" + +#define YAFFS_OK 1 +#define YAFFS_FAIL 0 + +/* Give us a Y=0x59, + * Give us an A=0x41, + * Give us an FF=0xff + * Give us an S=0x53 + * And what have we got... + */ +#define YAFFS_MAGIC 0x5941ff53 + +/* + * Tnodes form a tree with the tnodes in "levels" + * Levels greater than 0 hold 8 slots which point to other tnodes. + * Those at level 0 hold 16 slots which point to chunks in NAND. + * + * A maximum level of 8 thust supports files of size up to: + * + * 2^(3*MAX_LEVEL+4) + * + * Thus a max level of 8 supports files with up to 2^^28 chunks which gives + * a maximum file size of around 512Gbytees with 2k chunks. + */ +#define YAFFS_NTNODES_LEVEL0 16 +#define YAFFS_TNODES_LEVEL0_BITS 4 +#define YAFFS_TNODES_LEVEL0_MASK 0xf + +#define YAFFS_NTNODES_INTERNAL (YAFFS_NTNODES_LEVEL0 / 2) +#define YAFFS_TNODES_INTERNAL_BITS (YAFFS_TNODES_LEVEL0_BITS - 1) +#define YAFFS_TNODES_INTERNAL_MASK 0x7 +#define YAFFS_TNODES_MAX_LEVEL 8 +#define YAFFS_TNODES_MAX_BITS (YAFFS_TNODES_LEVEL0_BITS + \ + YAFFS_TNODES_INTERNAL_BITS * \ + YAFFS_TNODES_MAX_LEVEL) +#define YAFFS_MAX_CHUNK_ID ((1 << YAFFS_TNODES_MAX_BITS) - 1) + +#define YAFFS_MAX_FILE_SIZE_32 0x7fffffff + +/* Constants for YAFFS1 mode */ +#define YAFFS_BYTES_PER_SPARE 16 +#define YAFFS_BYTES_PER_CHUNK 512 +#define YAFFS_CHUNK_SIZE_SHIFT 9 +#define YAFFS_CHUNKS_PER_BLOCK 32 +#define YAFFS_BYTES_PER_BLOCK (YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK) + +#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 1024 +#define YAFFS_MIN_YAFFS2_SPARE_SIZE 32 + + + +#define YAFFS_ALLOCATION_NOBJECTS 100 +#define YAFFS_ALLOCATION_NTNODES 100 +#define YAFFS_ALLOCATION_NLINKS 100 + +#define YAFFS_NOBJECT_BUCKETS 256 + +#define YAFFS_OBJECT_SPACE 0x40000 +#define YAFFS_MAX_OBJECT_ID (YAFFS_OBJECT_SPACE - 1) + +/* Binary data version stamps */ +#define YAFFS_SUMMARY_VERSION 1 +#define YAFFS_CHECKPOINT_VERSION 7 + +#ifdef CONFIG_YAFFS_UNICODE +#define YAFFS_MAX_NAME_LENGTH 127 +#define YAFFS_MAX_ALIAS_LENGTH 79 +#else +#define YAFFS_MAX_NAME_LENGTH 255 +#define YAFFS_MAX_ALIAS_LENGTH 159 +#endif + +#define YAFFS_SHORT_NAME_LENGTH 15 + +/* Some special object ids for pseudo objects */ +#define YAFFS_OBJECTID_ROOT 1 +#define YAFFS_OBJECTID_LOSTNFOUND 2 +#define YAFFS_OBJECTID_UNLINKED 3 +#define YAFFS_OBJECTID_DELETED 4 + +/* Fake object Id for summary data */ +#define YAFFS_OBJECTID_SUMMARY 0x10 + +/* Pseudo object ids for checkpointing */ +#define YAFFS_OBJECTID_CHECKPOINT_DATA 0x20 +#define YAFFS_SEQUENCE_CHECKPOINT_DATA 0x21 + +#define YAFFS_MAX_SHORT_OP_CACHES 20 + +#define YAFFS_N_TEMP_BUFFERS 6 + +/* We limit the number attempts at sucessfully saving a chunk of data. + * Small-page devices have 32 pages per block; large-page devices have 64. + * Default to something in the order of 5 to 10 blocks worth of chunks. + */ +#define YAFFS_WR_ATTEMPTS (5*64) + +/* Sequence numbers are used in YAFFS2 to determine block allocation order. + * The range is limited slightly to help distinguish bad numbers from good. + * This also allows us to perhaps in the future use special numbers for + * special purposes. + * EFFFFF00 allows the allocation of 8 blocks/second (~1Mbytes) for 15 years, + * and is a larger number than the lifetime of a 2GB device. + */ +#define YAFFS_LOWEST_SEQUENCE_NUMBER 0x00001000 +#define YAFFS_HIGHEST_SEQUENCE_NUMBER 0xefffff00 + +/* Special sequence number for bad block that failed to be marked bad */ +#define YAFFS_SEQUENCE_BAD_BLOCK 0xffff0000 + +/* ChunkCache is used for short read/write operations.*/ +struct yaffs_cache { + struct yaffs_obj *object; + int chunk_id; + int last_use; + int dirty; + int n_bytes; /* Only valid if the cache is dirty */ + int locked; /* Can't push out or flush while locked. */ + u8 *data; +}; + +/* yaffs1 tags structures in RAM + * NB This uses bitfield. Bitfields should not straddle a u32 boundary + * otherwise the structure size will get blown out. + */ + +struct yaffs_tags { + u32 chunk_id:20; + u32 serial_number:2; + u32 n_bytes_lsb:10; + u32 obj_id:18; + u32 ecc:12; + u32 n_bytes_msb:2; +}; + +union yaffs_tags_union { + struct yaffs_tags as_tags; + u8 as_bytes[8]; +}; + + +/* Stuff used for extended tags in YAFFS2 */ + +enum yaffs_ecc_result { + YAFFS_ECC_RESULT_UNKNOWN, + YAFFS_ECC_RESULT_NO_ERROR, + YAFFS_ECC_RESULT_FIXED, + YAFFS_ECC_RESULT_UNFIXED +}; + +enum yaffs_obj_type { + YAFFS_OBJECT_TYPE_UNKNOWN, + YAFFS_OBJECT_TYPE_FILE, + YAFFS_OBJECT_TYPE_SYMLINK, + YAFFS_OBJECT_TYPE_DIRECTORY, + YAFFS_OBJECT_TYPE_HARDLINK, + YAFFS_OBJECT_TYPE_SPECIAL +}; + +#define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL + +struct yaffs_ext_tags { + unsigned chunk_used; /* Status of the chunk: used or unused */ + unsigned obj_id; /* If 0 this is not used */ + unsigned chunk_id; /* If 0 this is a header, else a data chunk */ + unsigned n_bytes; /* Only valid for data chunks */ + + /* The following stuff only has meaning when we read */ + enum yaffs_ecc_result ecc_result; + unsigned block_bad; + + /* YAFFS 1 stuff */ + unsigned is_deleted; /* The chunk is marked deleted */ + unsigned serial_number; /* Yaffs1 2-bit serial number */ + + /* YAFFS2 stuff */ + unsigned seq_number; /* The sequence number of this block */ + + /* Extra info if this is an object header (YAFFS2 only) */ + + unsigned extra_available; /* Extra info available if not zero */ + unsigned extra_parent_id; /* The parent object */ + unsigned extra_is_shrink; /* Is it a shrink header? */ + unsigned extra_shadows; /* Does this shadow another object? */ + + enum yaffs_obj_type extra_obj_type; /* What object type? */ + + loff_t extra_file_size; /* Length if it is a file */ + unsigned extra_equiv_id; /* Equivalent object for a hard link */ +}; + +/* Spare structure for YAFFS1 */ +struct yaffs_spare { + u8 tb0; + u8 tb1; + u8 tb2; + u8 tb3; + u8 page_status; /* set to 0 to delete the chunk */ + u8 block_status; + u8 tb4; + u8 tb5; + u8 ecc1[3]; + u8 tb6; + u8 tb7; + u8 ecc2[3]; +}; + +/*Special structure for passing through to mtd */ +struct yaffs_nand_spare { + struct yaffs_spare spare; + int eccres1; + int eccres2; +}; + +/* Block data in RAM */ + +enum yaffs_block_state { + YAFFS_BLOCK_STATE_UNKNOWN = 0, + + YAFFS_BLOCK_STATE_SCANNING, + /* Being scanned */ + + YAFFS_BLOCK_STATE_NEEDS_SCAN, + /* The block might have something on it (ie it is allocating or full, + * perhaps empty) but it needs to be scanned to determine its true + * state. + * This state is only valid during scanning. + * NB We tolerate empty because the pre-scanner might be incapable of + * deciding + * However, if this state is returned on a YAFFS2 device, + * then we expect a sequence number + */ + + YAFFS_BLOCK_STATE_EMPTY, + /* This block is empty */ + + YAFFS_BLOCK_STATE_ALLOCATING, + /* This block is partially allocated. + * At least one page holds valid data. + * This is the one currently being used for page + * allocation. Should never be more than one of these. + * If a block is only partially allocated at mount it is treated as + * full. + */ + + YAFFS_BLOCK_STATE_FULL, + /* All the pages in this block have been allocated. + * If a block was only partially allocated when mounted we treat + * it as fully allocated. + */ + + YAFFS_BLOCK_STATE_DIRTY, + /* The block was full and now all chunks have been deleted. + * Erase me, reuse me. + */ + + YAFFS_BLOCK_STATE_CHECKPOINT, + /* This block is assigned to holding checkpoint data. */ + + YAFFS_BLOCK_STATE_COLLECTING, + /* This block is being garbage collected */ + + YAFFS_BLOCK_STATE_DEAD + /* This block has failed and is not in use */ +}; + +#define YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1) + +struct yaffs_block_info { + + s32 soft_del_pages:10; /* number of soft deleted pages */ + s32 pages_in_use:10; /* number of pages in use */ + u32 block_state:4; /* One of the above block states. */ + /* NB use unsigned because enum is sometimes + * an int */ + u32 needs_retiring:1; /* Data has failed on this block, */ + /*need to get valid data off and retire*/ + u32 skip_erased_check:1;/* Skip the erased check on this block */ + u32 gc_prioritise:1; /* An ECC check or blank check has failed. + Block should be prioritised for GC */ + u32 chunk_error_strikes:3; /* How many times we've had ecc etc + failures on this block and tried to reuse it */ + u32 has_summary:1; /* The block has a summary */ + + u32 has_shrink_hdr:1; /* This block has at least one shrink header */ + u32 seq_number; /* block sequence number for yaffs2 */ + +}; + +/* -------------------------- Object structure -------------------------------*/ +/* This is the object structure as stored on NAND */ + +struct yaffs_obj_hdr { + enum yaffs_obj_type type; + + /* Apply to everything */ + int parent_obj_id; + u16 sum_no_longer_used; /* checksum of name. No longer used */ + YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; + + /* The following apply to all object types except for hard links */ + u32 yst_mode; /* protection */ + + u32 yst_uid; + u32 yst_gid; + u32 yst_atime; + u32 yst_mtime; + u32 yst_ctime; + + /* File size applies to files only */ + u32 file_size_low; + + /* Equivalent object id applies to hard links only. */ + int equiv_id; + + /* Alias is for symlinks only. */ + YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1]; + + u32 yst_rdev; /* stuff for block and char devices (major/min) */ + + u32 win_ctime[2]; + u32 win_atime[2]; + u32 win_mtime[2]; + + u32 inband_shadowed_obj_id; + u32 inband_is_shrink; + + u32 file_size_high; + u32 reserved[1]; + int shadows_obj; /* This object header shadows the + specified object if > 0 */ + + /* is_shrink applies to object headers written when wemake a hole. */ + u32 is_shrink; + +}; + +/*--------------------------- Tnode -------------------------- */ + +struct yaffs_tnode { + struct yaffs_tnode *internal[YAFFS_NTNODES_INTERNAL]; +}; + +/*------------------------ Object -----------------------------*/ +/* An object can be one of: + * - a directory (no data, has children links + * - a regular file (data.... not prunes :->). + * - a symlink [symbolic link] (the alias). + * - a hard link + */ + +struct yaffs_file_var { + loff_t file_size; + loff_t scanned_size; + loff_t shrink_size; + int top_level; + struct yaffs_tnode *top; +}; + +struct yaffs_dir_var { + struct list_head children; /* list of child links */ + struct list_head dirty; /* Entry for list of dirty directories */ +}; + +struct yaffs_symlink_var { + YCHAR *alias; +}; + +struct yaffs_hardlink_var { + struct yaffs_obj *equiv_obj; + u32 equiv_id; +}; + +union yaffs_obj_var { + struct yaffs_file_var file_variant; + struct yaffs_dir_var dir_variant; + struct yaffs_symlink_var symlink_variant; + struct yaffs_hardlink_var hardlink_variant; +}; + +struct yaffs_obj { + u8 deleted:1; /* This should only apply to unlinked files. */ + u8 soft_del:1; /* it has also been soft deleted */ + u8 unlinked:1; /* An unlinked file.*/ + u8 fake:1; /* A fake object has no presence on NAND. */ + u8 rename_allowed:1; /* Some objects cannot be renamed. */ + u8 unlink_allowed:1; + u8 dirty:1; /* the object needs to be written to flash */ + u8 valid:1; /* When the file system is being loaded up, this + * object might be created before the data + * is available + * ie. file data chunks encountered before + * the header. + */ + u8 lazy_loaded:1; /* This object has been lazy loaded and + * is missing some detail */ + + u8 defered_free:1; /* Object is removed from NAND, but is + * still in the inode cache. + * Free of object is defered. + * until the inode is released. + */ + u8 being_created:1; /* This object is still being created + * so skip some verification checks. */ + u8 is_shadowed:1; /* This object is shadowed on the way + * to being renamed. */ + + u8 xattr_known:1; /* We know if this has object has xattribs + * or not. */ + u8 has_xattr:1; /* This object has xattribs. + * Only valid if xattr_known. */ + + u8 serial; /* serial number of chunk in NAND.*/ + u16 sum; /* sum of the name to speed searching */ + + struct yaffs_dev *my_dev; /* The device I'm on */ + + struct list_head hash_link; /* list of objects in hash bucket */ + + struct list_head hard_links; /* hard linked object chain*/ + + /* directory structure stuff */ + /* also used for linking up the free list */ + struct yaffs_obj *parent; + struct list_head siblings; + + /* Where's my object header in NAND? */ + int hdr_chunk; + + int n_data_chunks; /* Number of data chunks for this file. */ + + u32 obj_id; /* the object id value */ + + u32 yst_mode; + + YCHAR short_name[YAFFS_SHORT_NAME_LENGTH + 1]; + +#ifdef CONFIG_YAFFS_WINCE + u32 win_ctime[2]; + u32 win_mtime[2]; + u32 win_atime[2]; +#else + u32 yst_uid; + u32 yst_gid; + u32 yst_atime; + u32 yst_mtime; + u32 yst_ctime; +#endif + + u32 yst_rdev; + + void *my_inode; + + enum yaffs_obj_type variant_type; + + union yaffs_obj_var variant; + +}; + +struct yaffs_obj_bucket { + struct list_head list; + int count; +}; + +/* yaffs_checkpt_obj holds the definition of an object as dumped + * by checkpointing. + */ + +struct yaffs_checkpt_obj { + int struct_type; + u32 obj_id; + u32 parent_id; + int hdr_chunk; + enum yaffs_obj_type variant_type:3; + u8 deleted:1; + u8 soft_del:1; + u8 unlinked:1; + u8 fake:1; + u8 rename_allowed:1; + u8 unlink_allowed:1; + u8 serial; + int n_data_chunks; + loff_t size_or_equiv_obj; +}; + +/*--------------------- Temporary buffers ---------------- + * + * These are chunk-sized working buffers. Each device has a few. + */ + +struct yaffs_buffer { + u8 *buffer; + int in_use; +}; + +/*----------------- Device ---------------------------------*/ + +struct yaffs_param { + const YCHAR *name; + + /* + * Entry parameters set up way early. Yaffs sets up the rest. + * The structure should be zeroed out before use so that unused + * and default values are zero. + */ + + int inband_tags; /* Use unband tags */ + u32 total_bytes_per_chunk; /* Should be >= 512, does not need to + be a power of 2 */ + int chunks_per_block; /* does not need to be a power of 2 */ + int spare_bytes_per_chunk; /* spare area size */ + int start_block; /* Start block we're allowed to use */ + int end_block; /* End block we're allowed to use */ + int n_reserved_blocks; /* Tuneable so that we can reduce + * reserved blocks on NOR and RAM. */ + + int n_caches; /* If <= 0, then short op caching is disabled, + * else the number of short op caches. + */ + int cache_bypass_aligned; /* If non-zero then bypass the cache for + * aligned writes. + */ + + int use_nand_ecc; /* Flag to decide whether or not to use + * NAND driver ECC on data (yaffs1) */ + int tags_9bytes; /* Use 9 byte tags */ + int no_tags_ecc; /* Flag to decide whether or not to do ECC + * on packed tags (yaffs2) */ + + int is_yaffs2; /* Use yaffs2 mode on this device */ + + int empty_lost_n_found; /* Auto-empty lost+found directory on mount */ + + int refresh_period; /* How often to check for a block refresh */ + + /* Checkpoint control. Can be set before or after initialisation */ + u8 skip_checkpt_rd; + u8 skip_checkpt_wr; + + int enable_xattr; /* Enable xattribs */ + + int max_objects; /* + * Set to limit the number of objects created. + * 0 = no limit. + */ + + /* The remove_obj_fn function must be supplied by OS flavours that + * need it. + * yaffs direct uses it to implement the faster readdir. + * Linux uses it to protect the directory during unlocking. + */ + void (*remove_obj_fn) (struct yaffs_obj *obj); + + /* Callback to mark the superblock dirty */ + void (*sb_dirty_fn) (struct yaffs_dev *dev); + + /* Callback to control garbage collection. */ + unsigned (*gc_control_fn) (struct yaffs_dev *dev); + + /* Debug control flags. Don't use unless you know what you're doing */ + int use_header_file_size; /* Flag to determine if we should use + * file sizes from the header */ + int disable_lazy_load; /* Disable lazy loading on this device */ + int wide_tnodes_disabled; /* Set to disable wide tnodes */ + int disable_soft_del; /* yaffs 1 only: Set to disable the use of + * softdeletion. */ + + int defered_dir_update; /* Set to defer directory updates */ + +#ifdef CONFIG_YAFFS_AUTO_UNICODE + int auto_unicode; +#endif + int always_check_erased; /* Force chunk erased check always on */ + + int disable_summary; + int disable_bad_block_marking; + +}; + +struct yaffs_driver { + int (*drv_write_chunk_fn) (struct yaffs_dev *dev, int nand_chunk, + const u8 *data, int data_len, + const u8 *oob, int oob_len); + int (*drv_read_chunk_fn) (struct yaffs_dev *dev, int nand_chunk, + u8 *data, int data_len, + u8 *oob, int oob_len, + enum yaffs_ecc_result *ecc_result); + int (*drv_erase_fn) (struct yaffs_dev *dev, int block_no); + int (*drv_mark_bad_fn) (struct yaffs_dev *dev, int block_no); + int (*drv_check_bad_fn) (struct yaffs_dev *dev, int block_no); + int (*drv_initialise_fn) (struct yaffs_dev *dev); + int (*drv_deinitialise_fn) (struct yaffs_dev *dev); +}; + +struct yaffs_tags_handler { + int (*write_chunk_tags_fn) (struct yaffs_dev *dev, + int nand_chunk, const u8 *data, + const struct yaffs_ext_tags *tags); + int (*read_chunk_tags_fn) (struct yaffs_dev *dev, + int nand_chunk, u8 *data, + struct yaffs_ext_tags *tags); + + int (*query_block_fn) (struct yaffs_dev *dev, int block_no, + enum yaffs_block_state *state, + u32 *seq_number); + int (*mark_bad_fn) (struct yaffs_dev *dev, int block_no); +}; + +struct yaffs_dev { + struct yaffs_param param; + struct yaffs_driver drv; + struct yaffs_tags_handler tagger; + + /* Context storage. Holds extra OS specific data for this device */ + + void *os_context; + void *driver_context; + + struct list_head dev_list; + + int ll_init; + /* Runtime parameters. Set up by YAFFS. */ + int data_bytes_per_chunk; + + /* Non-wide tnode stuff */ + u16 chunk_grp_bits; /* Number of bits that need to be resolved if + * the tnodes are not wide enough. + */ + u16 chunk_grp_size; /* == 2^^chunk_grp_bits */ + + /* Stuff to support wide tnodes */ + u32 tnode_width; + u32 tnode_mask; + u32 tnode_size; + + /* Stuff for figuring out file offset to chunk conversions */ + u32 chunk_shift; /* Shift value */ + u32 chunk_div; /* Divisor after shifting: 1 for 2^n sizes */ + u32 chunk_mask; /* Mask to use for power-of-2 case */ + + int is_mounted; + int read_only; + int is_checkpointed; + + /* Stuff to support block offsetting to support start block zero */ + int internal_start_block; + int internal_end_block; + int block_offset; + int chunk_offset; + + /* Runtime checkpointing stuff */ + int checkpt_page_seq; /* running sequence number of checkpt pages */ + int checkpt_byte_count; + int checkpt_byte_offs; + u8 *checkpt_buffer; + int checkpt_open_write; + int blocks_in_checkpt; + int checkpt_cur_chunk; + int checkpt_cur_block; + int checkpt_next_block; + int *checkpt_block_list; + int checkpt_max_blocks; + u32 checkpt_sum; + u32 checkpt_xor; + + int checkpoint_blocks_required; /* Number of blocks needed to store + * current checkpoint set */ + + /* Block Info */ + struct yaffs_block_info *block_info; + u8 *chunk_bits; /* bitmap of chunks in use */ + u8 block_info_alt:1; /* allocated using alternative alloc */ + u8 chunk_bits_alt:1; /* allocated using alternative alloc */ + int chunk_bit_stride; /* Number of bytes of chunk_bits per block. + * Must be consistent with chunks_per_block. + */ + + int n_erased_blocks; + int alloc_block; /* Current block being allocated off */ + u32 alloc_page; + int alloc_block_finder; /* Used to search for next allocation block */ + + /* Object and Tnode memory management */ + void *allocator; + int n_obj; + int n_tnodes; + + int n_hardlinks; + + struct yaffs_obj_bucket obj_bucket[YAFFS_NOBJECT_BUCKETS]; + u32 bucket_finder; + + int n_free_chunks; + + /* Garbage collection control */ + u32 *gc_cleanup_list; /* objects to delete at the end of a GC. */ + u32 n_clean_ups; + + unsigned has_pending_prioritised_gc; /* We think this device might + have pending prioritised gcs */ + unsigned gc_disable; + unsigned gc_block_finder; + unsigned gc_dirtiest; + unsigned gc_pages_in_use; + unsigned gc_not_done; + unsigned gc_block; + unsigned gc_chunk; + unsigned gc_skip; + struct yaffs_summary_tags *gc_sum_tags; + + /* Special directories */ + struct yaffs_obj *root_dir; + struct yaffs_obj *lost_n_found; + + int buffered_block; /* Which block is buffered here? */ + int doing_buffered_block_rewrite; + + struct yaffs_cache *cache; + int cache_last_use; + + /* Stuff for background deletion and unlinked files. */ + struct yaffs_obj *unlinked_dir; /* Directory where unlinked and deleted + files live. */ + struct yaffs_obj *del_dir; /* Directory where deleted objects are + sent to disappear. */ + struct yaffs_obj *unlinked_deletion; /* Current file being + background deleted. */ + int n_deleted_files; /* Count of files awaiting deletion; */ + int n_unlinked_files; /* Count of unlinked files. */ + int n_bg_deletions; /* Count of background deletions. */ + + /* Temporary buffer management */ + struct yaffs_buffer temp_buffer[YAFFS_N_TEMP_BUFFERS]; + int max_temp; + int temp_in_use; + int unmanaged_buffer_allocs; + int unmanaged_buffer_deallocs; + + /* yaffs2 runtime stuff */ + unsigned seq_number; /* Sequence number of currently + allocating block */ + unsigned oldest_dirty_seq; + unsigned oldest_dirty_block; + + /* Block refreshing */ + int refresh_skip; /* A skip down counter. + * Refresh happens when this gets to zero. */ + + /* Dirty directory handling */ + struct list_head dirty_dirs; /* List of dirty directories */ + + /* Summary */ + int chunks_per_summary; + struct yaffs_summary_tags *sum_tags; + + /* Statistics */ + u32 n_page_writes; + u32 n_page_reads; + u32 n_erasures; + u32 n_bad_queries; + u32 n_bad_markings; + u32 n_erase_failures; + u32 n_gc_copies; + u32 all_gcs; + u32 passive_gc_count; + u32 oldest_dirty_gc_count; + u32 n_gc_blocks; + u32 bg_gcs; + u32 n_retried_writes; + u32 n_retired_blocks; + u32 n_ecc_fixed; + u32 n_ecc_unfixed; + u32 n_tags_ecc_fixed; + u32 n_tags_ecc_unfixed; + u32 n_deletions; + u32 n_unmarked_deletions; + u32 refresh_count; + u32 cache_hits; + u32 tags_used; + u32 summary_used; + +}; + +/* The CheckpointDevice structure holds the device information that changes + *at runtime and must be preserved over unmount/mount cycles. + */ +struct yaffs_checkpt_dev { + int struct_type; + int n_erased_blocks; + int alloc_block; /* Current block being allocated off */ + u32 alloc_page; + int n_free_chunks; + + int n_deleted_files; /* Count of files awaiting deletion; */ + int n_unlinked_files; /* Count of unlinked files. */ + int n_bg_deletions; /* Count of background deletions. */ + + /* yaffs2 runtime stuff */ + unsigned seq_number; /* Sequence number of currently + * allocating block */ + +}; + +struct yaffs_checkpt_validity { + int struct_type; + u32 magic; + u32 version; + u32 head; +}; + +struct yaffs_shadow_fixer { + int obj_id; + int shadowed_id; + struct yaffs_shadow_fixer *next; +}; + +/* Structure for doing xattr modifications */ +struct yaffs_xattr_mod { + int set; /* If 0 then this is a deletion */ + const YCHAR *name; + const void *data; + int size; + int flags; + int result; +}; + +/*----------------------- YAFFS Functions -----------------------*/ + +int yaffs_guts_initialise(struct yaffs_dev *dev); +void yaffs_deinitialise(struct yaffs_dev *dev); + +int yaffs_get_n_free_chunks(struct yaffs_dev *dev); + +int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR * old_name, + struct yaffs_obj *new_dir, const YCHAR * new_name); + +int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR * name); +int yaffs_del_obj(struct yaffs_obj *obj); +struct yaffs_obj *yaffs_retype_obj(struct yaffs_obj *obj, + enum yaffs_obj_type type); + + +int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR * name, int buffer_size); +loff_t yaffs_get_obj_length(struct yaffs_obj *obj); +int yaffs_get_obj_inode(struct yaffs_obj *obj); +unsigned yaffs_get_obj_type(struct yaffs_obj *obj); +int yaffs_get_obj_link_count(struct yaffs_obj *obj); + +/* File operations */ +int yaffs_file_rd(struct yaffs_obj *obj, u8 * buffer, loff_t offset, + int n_bytes); +int yaffs_wr_file(struct yaffs_obj *obj, const u8 * buffer, loff_t offset, + int n_bytes, int write_trhrough); +int yaffs_resize_file(struct yaffs_obj *obj, loff_t new_size); + +struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent, + const YCHAR *name, u32 mode, u32 uid, + u32 gid); + +int yaffs_flush_file(struct yaffs_obj *in, + int update_time, + int data_sync, + int discard_cache); + +/* Flushing and checkpointing */ +void yaffs_flush_whole_cache(struct yaffs_dev *dev, int discard); + +int yaffs_checkpoint_save(struct yaffs_dev *dev); +int yaffs_checkpoint_restore(struct yaffs_dev *dev); + +/* Directory operations */ +struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR *name, + u32 mode, u32 uid, u32 gid); +struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *the_dir, + const YCHAR *name); +struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number); + +/* Link operations */ +struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR *name, + struct yaffs_obj *equiv_obj); + +struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj); + +/* Symlink operations */ +struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent, + const YCHAR *name, u32 mode, u32 uid, + u32 gid, const YCHAR *alias); +YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj); + +/* Special inodes (fifos, sockets and devices) */ +struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent, + const YCHAR *name, u32 mode, u32 uid, + u32 gid, u32 rdev); + +int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR *name, + const void *value, int size, int flags); +int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR *name, void *value, + int size); +int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size); +int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR *name); + +/* Special directories */ +struct yaffs_obj *yaffs_root(struct yaffs_dev *dev); +struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev); + +void yaffs_handle_defered_free(struct yaffs_obj *obj); + +void yaffs_update_dirty_dirs(struct yaffs_dev *dev); + +int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency); + +/* Debug dump */ +int yaffs_dump_obj(struct yaffs_obj *obj); + +void yaffs_guts_test(struct yaffs_dev *dev); +int yaffs_guts_ll_init(struct yaffs_dev *dev); + + +/* A few useful functions to be used within the core files*/ +void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash, + int lyn); +int yaffs_check_ff(u8 *buffer, int n_bytes); +void yaffs_handle_chunk_error(struct yaffs_dev *dev, + struct yaffs_block_info *bi); + +u8 *yaffs_get_temp_buffer(struct yaffs_dev *dev); +void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 *buffer); + +struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev, + int number, + enum yaffs_obj_type type); +int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk, + int nand_chunk, int in_scan); +void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR *name); +void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj, + const struct yaffs_obj_hdr *oh); +void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj); +YCHAR *yaffs_clone_str(const YCHAR *str); +void yaffs_link_fixup(struct yaffs_dev *dev, struct list_head *hard_list); +void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no); +int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, + int force, int is_shrink, int shadows, + struct yaffs_xattr_mod *xop); +void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id, + int backward_scanning); +int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks); +struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev); +struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev, + struct yaffs_file_var *file_struct, + u32 chunk_id, + struct yaffs_tnode *passed_tn); + +int yaffs_do_file_wr(struct yaffs_obj *in, const u8 *buffer, loff_t offset, + int n_bytes, int write_trhrough); +void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size); +void yaffs_skip_rest_of_block(struct yaffs_dev *dev); + +int yaffs_count_free_chunks(struct yaffs_dev *dev); + +struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, + struct yaffs_file_var *file_struct, + u32 chunk_id); + +u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn, + unsigned pos); + +int yaffs_is_non_empty_dir(struct yaffs_obj *obj); + +int yaffs_guts_format_dev(struct yaffs_dev *dev); + +void yaffs_addr_to_chunk(struct yaffs_dev *dev, loff_t addr, + int *chunk_out, u32 *offset_out); +/* + * Marshalling functions to get loff_t file sizes into aand out of + * object headers. + */ +void yaffs_oh_size_load(struct yaffs_obj_hdr *oh, loff_t fsize); +loff_t yaffs_oh_to_size(struct yaffs_obj_hdr *oh); +loff_t yaffs_max_file_size(struct yaffs_dev *dev); + +/* + * Debug function to count number of blocks in each state + * NB Needs to be called with correct number of integers + */ + +void yaffs_count_blocks_by_state(struct yaffs_dev *dev, int bs[10]); + +int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk, + struct yaffs_ext_tags *tags); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_linux.h b/target/linux/generic/files/fs/yaffs2/yaffs_linux.h new file mode 100644 index 0000000..c20ab14 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_linux.h @@ -0,0 +1,48 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_LINUX_H__ +#define __YAFFS_LINUX_H__ + +#include "yportenv.h" + +struct yaffs_linux_context { + struct list_head context_list; /* List of these we have mounted */ + struct yaffs_dev *dev; + struct super_block *super; + struct task_struct *bg_thread; /* Background thread for this device */ + int bg_running; + struct mutex gross_lock; /* Gross locking mutex*/ + u8 *spare_buffer; /* For mtdif2 use. Don't know the buffer size + * at compile time so we have to allocate it. + */ + struct list_head search_contexts; + struct task_struct *readdir_process; + unsigned mount_id; + int dirty; +}; + +#define yaffs_dev_to_lc(dev) ((struct yaffs_linux_context *)((dev)->os_context)) +#define yaffs_dev_to_mtd(dev) ((struct mtd_info *)((dev)->driver_context)) + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) +#define WRITE_SIZE_STR "writesize" +#define WRITE_SIZE(mtd) ((mtd)->writesize) +#else +#define WRITE_SIZE_STR "oobblock" +#define WRITE_SIZE(mtd) ((mtd)->oobblock) +#endif + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_mtdif.c b/target/linux/generic/files/fs/yaffs2/yaffs_mtdif.c new file mode 100644 index 0000000..7c01461 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_mtdif.c @@ -0,0 +1,310 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yportenv.h" + +#include "yaffs_mtdif.h" + +#include "linux/mtd/mtd.h" +#include "linux/types.h" +#include "linux/time.h" +#include "linux/mtd/nand.h" +#include "linux/kernel.h" +#include "linux/version.h" +#include "linux/types.h" +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) +#include "uapi/linux/major.h" +#endif + +#include "yaffs_trace.h" +#include "yaffs_guts.h" +#include "yaffs_linux.h" + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) +#define MTD_OPS_AUTO_OOB MTD_OOB_AUTO +#endif + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) +#define mtd_erase(m, ei) (m)->erase(m, ei) +#define mtd_write_oob(m, addr, pops) (m)->write_oob(m, addr, pops) +#define mtd_read_oob(m, addr, pops) (m)->read_oob(m, addr, pops) +#define mtd_block_isbad(m, offs) (m)->block_isbad(m, offs) +#define mtd_block_markbad(m, offs) (m)->block_markbad(m, offs) +#endif + + + +int nandmtd_erase_block(struct yaffs_dev *dev, int block_no) +{ + struct mtd_info *mtd = yaffs_dev_to_mtd(dev); + u32 addr = + ((loff_t) block_no) * dev->param.total_bytes_per_chunk * + dev->param.chunks_per_block; + struct erase_info ei; + int retval = 0; + + ei.mtd = mtd; + ei.addr = addr; + ei.len = dev->param.total_bytes_per_chunk * dev->param.chunks_per_block; + ei.time = 1000; + ei.retries = 2; + ei.callback = NULL; + ei.priv = (u_long) dev; + + retval = mtd_erase(mtd, &ei); + + if (retval == 0) + return YAFFS_OK; + + return YAFFS_FAIL; +} + + +static int yaffs_mtd_write(struct yaffs_dev *dev, int nand_chunk, + const u8 *data, int data_len, + const u8 *oob, int oob_len) +{ + struct mtd_info *mtd = yaffs_dev_to_mtd(dev); + loff_t addr; + struct mtd_oob_ops ops; + int retval; + + yaffs_trace(YAFFS_TRACE_MTD, + "yaffs_mtd_write(%p, %d, %p, %d, %p, %d)\n", + dev, nand_chunk, data, data_len, oob, oob_len); + + if (!data || !data_len) { + data = NULL; + data_len = 0; + } + + if (!oob || !oob_len) { + oob = NULL; + oob_len = 0; + } + + addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk; + memset(&ops, 0, sizeof(ops)); + ops.mode = MTD_OPS_AUTO_OOB; + ops.len = (data) ? data_len : 0; + ops.ooblen = oob_len; + ops.datbuf = (u8 *)data; + ops.oobbuf = (u8 *)oob; + + retval = mtd_write_oob(mtd, addr, &ops); + if (retval) { + yaffs_trace(YAFFS_TRACE_MTD, + "write_oob failed, chunk %d, mtd error %d", + nand_chunk, retval); + } + return retval ? YAFFS_FAIL : YAFFS_OK; +} + +static int yaffs_mtd_read(struct yaffs_dev *dev, int nand_chunk, + u8 *data, int data_len, + u8 *oob, int oob_len, + enum yaffs_ecc_result *ecc_result) +{ + struct mtd_info *mtd = yaffs_dev_to_mtd(dev); + loff_t addr; + struct mtd_oob_ops ops; + int retval; + + addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk; + memset(&ops, 0, sizeof(ops)); + ops.mode = MTD_OPS_AUTO_OOB; + ops.len = (data) ? data_len : 0; + ops.ooblen = oob_len; + ops.datbuf = data; + ops.oobbuf = oob; + +#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 20)) + /* In MTD 2.6.18 to 2.6.19 nand_base.c:nand_do_read_oob() has a bug; + * help it out with ops.len = ops.ooblen when ops.datbuf == NULL. + */ + ops.len = (ops.datbuf) ? ops.len : ops.ooblen; +#endif + /* Read page and oob using MTD. + * Check status and determine ECC result. + */ + retval = mtd_read_oob(mtd, addr, &ops); + if (retval) + yaffs_trace(YAFFS_TRACE_MTD, + "read_oob failed, chunk %d, mtd error %d", + nand_chunk, retval); + + switch (retval) { + case 0: + /* no error */ + if(ecc_result) + *ecc_result = YAFFS_ECC_RESULT_NO_ERROR; + break; + + case -EUCLEAN: + /* MTD's ECC fixed the data */ + if(ecc_result) + *ecc_result = YAFFS_ECC_RESULT_FIXED; + dev->n_ecc_fixed++; + break; + + case -EBADMSG: + default: + /* MTD's ECC could not fix the data */ + dev->n_ecc_unfixed++; + if(ecc_result) + *ecc_result = YAFFS_ECC_RESULT_UNFIXED; + return YAFFS_FAIL; + } + + return YAFFS_OK; +} + +static int yaffs_mtd_erase(struct yaffs_dev *dev, int block_no) +{ + struct mtd_info *mtd = yaffs_dev_to_mtd(dev); + + loff_t addr; + struct erase_info ei; + int retval = 0; + u32 block_size; + + block_size = dev->param.total_bytes_per_chunk * + dev->param.chunks_per_block; + addr = ((loff_t) block_no) * block_size; + + ei.mtd = mtd; + ei.addr = addr; + ei.len = block_size; + ei.time = 1000; + ei.retries = 2; + ei.callback = NULL; + ei.priv = (u_long) dev; + + retval = mtd_erase(mtd, &ei); + + if (retval == 0) + return YAFFS_OK; + + return YAFFS_FAIL; +} + +static int yaffs_mtd_mark_bad(struct yaffs_dev *dev, int block_no) +{ + struct mtd_info *mtd = yaffs_dev_to_mtd(dev); + int blocksize = dev->param.chunks_per_block * dev->param.total_bytes_per_chunk; + int retval; + + yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, "marking block %d bad", block_no); + + retval = mtd_block_markbad(mtd, (loff_t) blocksize * block_no); + return (retval) ? YAFFS_FAIL : YAFFS_OK; +} + +static int yaffs_mtd_check_bad(struct yaffs_dev *dev, int block_no) +{ + struct mtd_info *mtd = yaffs_dev_to_mtd(dev); + int blocksize = dev->param.chunks_per_block * dev->param.total_bytes_per_chunk; + int retval; + + yaffs_trace(YAFFS_TRACE_MTD, "checking block %d bad", block_no); + + retval = mtd_block_isbad(mtd, (loff_t) blocksize * block_no); + return (retval) ? YAFFS_FAIL : YAFFS_OK; +} + +static int yaffs_mtd_initialise(struct yaffs_dev *dev) +{ + return YAFFS_OK; +} + +static int yaffs_mtd_deinitialise(struct yaffs_dev *dev) +{ + return YAFFS_OK; +} + + +void yaffs_mtd_drv_install(struct yaffs_dev *dev) +{ + struct yaffs_driver *drv = &dev->drv; + + drv->drv_write_chunk_fn = yaffs_mtd_write; + drv->drv_read_chunk_fn = yaffs_mtd_read; + drv->drv_erase_fn = yaffs_mtd_erase; + drv->drv_mark_bad_fn = yaffs_mtd_mark_bad; + drv->drv_check_bad_fn = yaffs_mtd_check_bad; + drv->drv_initialise_fn = yaffs_mtd_initialise; + drv->drv_deinitialise_fn = yaffs_mtd_deinitialise; +} + + +struct mtd_info * yaffs_get_mtd_device(dev_t sdev) +{ + struct mtd_info *mtd; + + mtd = yaffs_get_mtd_device(sdev); + + /* Check it's an mtd device..... */ + if (MAJOR(sdev) != MTD_BLOCK_MAJOR) + return NULL; /* This isn't an mtd device */ + + /* Check it's NAND */ + if (mtd->type != MTD_NANDFLASH) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs: MTD device is not NAND it's type %d", + mtd->type); + return NULL; + } + + yaffs_trace(YAFFS_TRACE_OS, " %s %d", WRITE_SIZE_STR, WRITE_SIZE(mtd)); + yaffs_trace(YAFFS_TRACE_OS, " oobsize %d", mtd->oobsize); + yaffs_trace(YAFFS_TRACE_OS, " erasesize %d", mtd->erasesize); +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) + yaffs_trace(YAFFS_TRACE_OS, " size %u", mtd->size); +#else + yaffs_trace(YAFFS_TRACE_OS, " size %lld", mtd->size); +#endif + + return mtd; +} + +int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags) +{ + if (yaffs_version == 2) { + if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || + mtd->oobsize < YAFFS_MIN_YAFFS2_SPARE_SIZE) && + !inband_tags) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "MTD device does not have the right page sizes" + ); + return -1; + } + } else { + if (WRITE_SIZE(mtd) < YAFFS_BYTES_PER_CHUNK || + mtd->oobsize != YAFFS_BYTES_PER_SPARE) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "MTD device does not support have the right page sizes" + ); + return -1; + } + } + + return 0; +} + + +void yaffs_put_mtd_device(struct mtd_info *mtd) +{ + if(mtd) + put_mtd_device(mtd); +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_mtdif.h b/target/linux/generic/files/fs/yaffs2/yaffs_mtdif.h new file mode 100644 index 0000000..9cff224 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_mtdif.h @@ -0,0 +1,25 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_MTDIF_H__ +#define __YAFFS_MTDIF_H__ + +#include "yaffs_guts.h" + +void yaffs_mtd_drv_install(struct yaffs_dev *dev); +struct mtd_info * yaffs_get_mtd_device(dev_t sdev); +void yaffs_put_mtd_device(struct mtd_info *mtd); +int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags); +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_nameval.c b/target/linux/generic/files/fs/yaffs2/yaffs_nameval.c new file mode 100644 index 0000000..4bdf4ed --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_nameval.c @@ -0,0 +1,208 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * This simple implementation of a name-value store assumes a small number of +* values and fits into a small finite buffer. + * + * Each attribute is stored as a record: + * sizeof(int) bytes record size. + * strnlen+1 bytes name null terminated. + * nbytes value. + * ---------- + * total size stored in record size + * + * This code has not been tested with unicode yet. + */ + +#include "yaffs_nameval.h" + +#include "yportenv.h" + +static int nval_find(const char *xb, int xb_size, const YCHAR *name, + int *exist_size) +{ + int pos = 0; + int size; + + memcpy(&size, xb, sizeof(int)); + while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { + if (!strncmp((YCHAR *) (xb + pos + sizeof(int)), + name, size)) { + if (exist_size) + *exist_size = size; + return pos; + } + pos += size; + if (pos < xb_size - sizeof(int)) + memcpy(&size, xb + pos, sizeof(int)); + else + size = 0; + } + if (exist_size) + *exist_size = 0; + return -ENODATA; +} + +static int nval_used(const char *xb, int xb_size) +{ + int pos = 0; + int size; + + memcpy(&size, xb + pos, sizeof(int)); + while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { + pos += size; + if (pos < xb_size - sizeof(int)) + memcpy(&size, xb + pos, sizeof(int)); + else + size = 0; + } + return pos; +} + +int nval_del(char *xb, int xb_size, const YCHAR *name) +{ + int pos = nval_find(xb, xb_size, name, NULL); + int size; + + if (pos < 0 || pos >= xb_size) + return -ENODATA; + + /* Find size, shift rest over this record, + * then zero out the rest of buffer */ + memcpy(&size, xb + pos, sizeof(int)); + memcpy(xb + pos, xb + pos + size, xb_size - (pos + size)); + memset(xb + (xb_size - size), 0, size); + return 0; +} + +int nval_set(char *xb, int xb_size, const YCHAR *name, const char *buf, + int bsize, int flags) +{ + int pos; + int namelen = strnlen(name, xb_size); + int reclen; + int size_exist = 0; + int space; + int start; + + pos = nval_find(xb, xb_size, name, &size_exist); + + if (flags & XATTR_CREATE && pos >= 0) + return -EEXIST; + if (flags & XATTR_REPLACE && pos < 0) + return -ENODATA; + + start = nval_used(xb, xb_size); + space = xb_size - start + size_exist; + + reclen = (sizeof(int) + namelen + 1 + bsize); + + if (reclen > space) + return -ENOSPC; + + if (pos >= 0) { + nval_del(xb, xb_size, name); + start = nval_used(xb, xb_size); + } + + pos = start; + + memcpy(xb + pos, &reclen, sizeof(int)); + pos += sizeof(int); + strncpy((YCHAR *) (xb + pos), name, reclen); + pos += (namelen + 1); + memcpy(xb + pos, buf, bsize); + return 0; +} + +int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf, + int bsize) +{ + int pos = nval_find(xb, xb_size, name, NULL); + int size; + + if (pos >= 0 && pos < xb_size) { + + memcpy(&size, xb + pos, sizeof(int)); + pos += sizeof(int); /* advance past record length */ + size -= sizeof(int); + + /* Advance over name string */ + while (xb[pos] && size > 0 && pos < xb_size) { + pos++; + size--; + } + /*Advance over NUL */ + pos++; + size--; + + /* If bsize is zero then this is a size query. + * Return the size, but don't copy. + */ + if (!bsize) + return size; + + if (size <= bsize) { + memcpy(buf, xb + pos, size); + return size; + } + } + if (pos >= 0) + return -ERANGE; + + return -ENODATA; +} + +int nval_list(const char *xb, int xb_size, char *buf, int bsize) +{ + int pos = 0; + int size; + int name_len; + int ncopied = 0; + int filled = 0; + + memcpy(&size, xb + pos, sizeof(int)); + while (size > sizeof(int) && + size <= xb_size && + (pos + size) < xb_size && + !filled) { + pos += sizeof(int); + size -= sizeof(int); + name_len = strnlen((YCHAR *) (xb + pos), size); + if (ncopied + name_len + 1 < bsize) { + memcpy(buf, xb + pos, name_len * sizeof(YCHAR)); + buf += name_len; + *buf = '\0'; + buf++; + if (sizeof(YCHAR) > 1) { + *buf = '\0'; + buf++; + } + ncopied += (name_len + 1); + } else { + filled = 1; + } + pos += size; + if (pos < xb_size - sizeof(int)) + memcpy(&size, xb + pos, sizeof(int)); + else + size = 0; + } + return ncopied; +} + +int nval_hasvalues(const char *xb, int xb_size) +{ + return nval_used(xb, xb_size) > 0; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_nameval.h b/target/linux/generic/files/fs/yaffs2/yaffs_nameval.h new file mode 100644 index 0000000..951e64f --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_nameval.h @@ -0,0 +1,28 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __NAMEVAL_H__ +#define __NAMEVAL_H__ + +#include "yportenv.h" + +int nval_del(char *xb, int xb_size, const YCHAR * name); +int nval_set(char *xb, int xb_size, const YCHAR * name, const char *buf, + int bsize, int flags); +int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf, + int bsize); +int nval_list(const char *xb, int xb_size, char *buf, int bsize); +int nval_hasvalues(const char *xb, int xb_size); +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_nand.c b/target/linux/generic/files/fs/yaffs2/yaffs_nand.c new file mode 100644 index 0000000..0d8499b --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_nand.c @@ -0,0 +1,122 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_nand.h" +#include "yaffs_tagscompat.h" + +#include "yaffs_getblockinfo.h" +#include "yaffs_summary.h" + +static int apply_chunk_offset(struct yaffs_dev *dev, int chunk) +{ + return chunk - dev->chunk_offset; +} + +int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk, + u8 *buffer, struct yaffs_ext_tags *tags) +{ + int result; + struct yaffs_ext_tags local_tags; + int flash_chunk = apply_chunk_offset(dev, nand_chunk); + + dev->n_page_reads++; + + /* If there are no tags provided use local tags. */ + if (!tags) + tags = &local_tags; + + result = dev->tagger.read_chunk_tags_fn(dev, flash_chunk, buffer, tags); + if (tags && tags->ecc_result > YAFFS_ECC_RESULT_NO_ERROR) { + + struct yaffs_block_info *bi; + bi = yaffs_get_block_info(dev, + nand_chunk / + dev->param.chunks_per_block); + yaffs_handle_chunk_error(dev, bi); + } + return result; +} + +int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev, + int nand_chunk, + const u8 *buffer, struct yaffs_ext_tags *tags) +{ + int result; + int flash_chunk = apply_chunk_offset(dev, nand_chunk); + + dev->n_page_writes++; + + if (!tags) { + yaffs_trace(YAFFS_TRACE_ERROR, "Writing with no tags"); + BUG(); + return YAFFS_FAIL; + } + + tags->seq_number = dev->seq_number; + tags->chunk_used = 1; + yaffs_trace(YAFFS_TRACE_WRITE, + "Writing chunk %d tags %d %d", + nand_chunk, tags->obj_id, tags->chunk_id); + + result = dev->tagger.write_chunk_tags_fn(dev, flash_chunk, + buffer, tags); + + yaffs_summary_add(dev, tags, nand_chunk); + + return result; +} + +int yaffs_mark_bad(struct yaffs_dev *dev, int block_no) +{ + block_no -= dev->block_offset; + dev->n_bad_markings++; + + if (dev->param.disable_bad_block_marking) + return YAFFS_OK; + + return dev->tagger.mark_bad_fn(dev, block_no); +} + + +int yaffs_query_init_block_state(struct yaffs_dev *dev, + int block_no, + enum yaffs_block_state *state, + u32 *seq_number) +{ + block_no -= dev->block_offset; + return dev->tagger.query_block_fn(dev, block_no, state, seq_number); +} + +int yaffs_erase_block(struct yaffs_dev *dev, int block_no) +{ + int result; + + block_no -= dev->block_offset; + dev->n_erasures++; + result = dev->drv.drv_erase_fn(dev, block_no); + return result; +} + +int yaffs_init_nand(struct yaffs_dev *dev) +{ + if (dev->drv.drv_initialise_fn) + return dev->drv.drv_initialise_fn(dev); + return YAFFS_OK; +} + +int yaffs_deinit_nand(struct yaffs_dev *dev) +{ + if (dev->drv.drv_deinitialise_fn) + return dev->drv.drv_deinitialise_fn(dev); + return YAFFS_OK; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_nand.h b/target/linux/generic/files/fs/yaffs2/yaffs_nand.h new file mode 100644 index 0000000..804e97a --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_nand.h @@ -0,0 +1,39 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_NAND_H__ +#define __YAFFS_NAND_H__ +#include "yaffs_guts.h" + +int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk, + u8 *buffer, struct yaffs_ext_tags *tags); + +int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev, + int nand_chunk, + const u8 *buffer, struct yaffs_ext_tags *tags); + +int yaffs_mark_bad(struct yaffs_dev *dev, int block_no); + +int yaffs_query_init_block_state(struct yaffs_dev *dev, + int block_no, + enum yaffs_block_state *state, + unsigned *seq_number); + +int yaffs_erase_block(struct yaffs_dev *dev, int flash_block); + +int yaffs_init_nand(struct yaffs_dev *dev); +int yaffs_deinit_nand(struct yaffs_dev *dev); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_packedtags1.c b/target/linux/generic/files/fs/yaffs2/yaffs_packedtags1.c new file mode 100644 index 0000000..dd9a331 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_packedtags1.c @@ -0,0 +1,56 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_packedtags1.h" +#include "yportenv.h" + +static const u8 all_ff[20] = { + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff +}; + +void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt, + const struct yaffs_ext_tags *t) +{ + pt->chunk_id = t->chunk_id; + pt->serial_number = t->serial_number; + pt->n_bytes = t->n_bytes; + pt->obj_id = t->obj_id; + pt->ecc = 0; + pt->deleted = (t->is_deleted) ? 0 : 1; + pt->unused_stuff = 0; + pt->should_be_ff = 0xffffffff; +} + +void yaffs_unpack_tags1(struct yaffs_ext_tags *t, + const struct yaffs_packed_tags1 *pt) +{ + + if (memcmp(all_ff, pt, sizeof(struct yaffs_packed_tags1))) { + t->block_bad = 0; + if (pt->should_be_ff != 0xffffffff) + t->block_bad = 1; + t->chunk_used = 1; + t->obj_id = pt->obj_id; + t->chunk_id = pt->chunk_id; + t->n_bytes = pt->n_bytes; + t->ecc_result = YAFFS_ECC_RESULT_NO_ERROR; + t->is_deleted = (pt->deleted) ? 0 : 1; + t->serial_number = pt->serial_number; + } else { + memset(t, 0, sizeof(struct yaffs_ext_tags)); + } +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_packedtags1.h b/target/linux/generic/files/fs/yaffs2/yaffs_packedtags1.h new file mode 100644 index 0000000..3015d58 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_packedtags1.h @@ -0,0 +1,39 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */ + +#ifndef __YAFFS_PACKEDTAGS1_H__ +#define __YAFFS_PACKEDTAGS1_H__ + +#include "yaffs_guts.h" + +struct yaffs_packed_tags1 { + u32 chunk_id:20; + u32 serial_number:2; + u32 n_bytes:10; + u32 obj_id:18; + u32 ecc:12; + u32 deleted:1; + u32 unused_stuff:1; + unsigned should_be_ff; + +}; + +void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt, + const struct yaffs_ext_tags *t); +void yaffs_unpack_tags1(struct yaffs_ext_tags *t, + const struct yaffs_packed_tags1 *pt); +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_packedtags2.c b/target/linux/generic/files/fs/yaffs2/yaffs_packedtags2.c new file mode 100644 index 0000000..e1d18cc --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_packedtags2.c @@ -0,0 +1,197 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_packedtags2.h" +#include "yportenv.h" +#include "yaffs_trace.h" + +/* This code packs a set of extended tags into a binary structure for + * NAND storage + */ + +/* Some of the information is "extra" struff which can be packed in to + * speed scanning + * This is defined by having the EXTRA_HEADER_INFO_FLAG set. + */ + +/* Extra flags applied to chunk_id */ + +#define EXTRA_HEADER_INFO_FLAG 0x80000000 +#define EXTRA_SHRINK_FLAG 0x40000000 +#define EXTRA_SHADOWS_FLAG 0x20000000 +#define EXTRA_SPARE_FLAGS 0x10000000 + +#define ALL_EXTRA_FLAGS 0xf0000000 + +/* Also, the top 4 bits of the object Id are set to the object type. */ +#define EXTRA_OBJECT_TYPE_SHIFT (28) +#define EXTRA_OBJECT_TYPE_MASK ((0x0f) << EXTRA_OBJECT_TYPE_SHIFT) + +static void yaffs_dump_packed_tags2_tags_only( + const struct yaffs_packed_tags2_tags_only *ptt) +{ + yaffs_trace(YAFFS_TRACE_MTD, + "packed tags obj %d chunk %d byte %d seq %d", + ptt->obj_id, ptt->chunk_id, ptt->n_bytes, ptt->seq_number); +} + +static void yaffs_dump_packed_tags2(const struct yaffs_packed_tags2 *pt) +{ + yaffs_dump_packed_tags2_tags_only(&pt->t); +} + +static void yaffs_dump_tags2(const struct yaffs_ext_tags *t) +{ + yaffs_trace(YAFFS_TRACE_MTD, + "ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d", + t->ecc_result, t->block_bad, t->chunk_used, t->obj_id, + t->chunk_id, t->n_bytes, t->is_deleted, t->serial_number, + t->seq_number); + +} + +static int yaffs_check_tags_extra_packable(const struct yaffs_ext_tags *t) +{ + if (t->chunk_id != 0 || !t->extra_available) + return 0; + + /* Check if the file size is too long to store */ + if (t->extra_obj_type == YAFFS_OBJECT_TYPE_FILE && + (t->extra_file_size >> 31) != 0) + return 0; + return 1; +} + +void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *ptt, + const struct yaffs_ext_tags *t) +{ + ptt->chunk_id = t->chunk_id; + ptt->seq_number = t->seq_number; + ptt->n_bytes = t->n_bytes; + ptt->obj_id = t->obj_id; + + /* Only store extra tags for object headers. + * If it is a file then only store if the file size is short\ + * enough to fit. + */ + if (yaffs_check_tags_extra_packable(t)) { + /* Store the extra header info instead */ + /* We save the parent object in the chunk_id */ + ptt->chunk_id = EXTRA_HEADER_INFO_FLAG | t->extra_parent_id; + if (t->extra_is_shrink) + ptt->chunk_id |= EXTRA_SHRINK_FLAG; + if (t->extra_shadows) + ptt->chunk_id |= EXTRA_SHADOWS_FLAG; + + ptt->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; + ptt->obj_id |= (t->extra_obj_type << EXTRA_OBJECT_TYPE_SHIFT); + + if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) + ptt->n_bytes = t->extra_equiv_id; + else if (t->extra_obj_type == YAFFS_OBJECT_TYPE_FILE) + ptt->n_bytes = (unsigned) t->extra_file_size; + else + ptt->n_bytes = 0; + } + + yaffs_dump_packed_tags2_tags_only(ptt); + yaffs_dump_tags2(t); +} + +void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt, + const struct yaffs_ext_tags *t, int tags_ecc) +{ + yaffs_pack_tags2_tags_only(&pt->t, t); + + if (tags_ecc) + yaffs_ecc_calc_other((unsigned char *)&pt->t, + sizeof(struct yaffs_packed_tags2_tags_only), + &pt->ecc); +} + +void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, + struct yaffs_packed_tags2_tags_only *ptt) +{ + memset(t, 0, sizeof(struct yaffs_ext_tags)); + + if (ptt->seq_number == 0xffffffff) + return; + + t->block_bad = 0; + t->chunk_used = 1; + t->obj_id = ptt->obj_id; + t->chunk_id = ptt->chunk_id; + t->n_bytes = ptt->n_bytes; + t->is_deleted = 0; + t->serial_number = 0; + t->seq_number = ptt->seq_number; + + /* Do extra header info stuff */ + if (ptt->chunk_id & EXTRA_HEADER_INFO_FLAG) { + t->chunk_id = 0; + t->n_bytes = 0; + + t->extra_available = 1; + t->extra_parent_id = ptt->chunk_id & (~(ALL_EXTRA_FLAGS)); + t->extra_is_shrink = ptt->chunk_id & EXTRA_SHRINK_FLAG ? 1 : 0; + t->extra_shadows = ptt->chunk_id & EXTRA_SHADOWS_FLAG ? 1 : 0; + t->extra_obj_type = ptt->obj_id >> EXTRA_OBJECT_TYPE_SHIFT; + t->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; + + if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) + t->extra_equiv_id = ptt->n_bytes; + else + t->extra_file_size = ptt->n_bytes; + } + yaffs_dump_packed_tags2_tags_only(ptt); + yaffs_dump_tags2(t); +} + +void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt, + int tags_ecc) +{ + enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_NO_ERROR; + + if (pt->t.seq_number != 0xffffffff && tags_ecc) { + /* Chunk is in use and we need to do ECC */ + + struct yaffs_ecc_other ecc; + int result; + yaffs_ecc_calc_other((unsigned char *)&pt->t, + sizeof(struct yaffs_packed_tags2_tags_only), + &ecc); + result = + yaffs_ecc_correct_other((unsigned char *)&pt->t, + sizeof(struct yaffs_packed_tags2_tags_only), + &pt->ecc, &ecc); + switch (result) { + case 0: + ecc_result = YAFFS_ECC_RESULT_NO_ERROR; + break; + case 1: + ecc_result = YAFFS_ECC_RESULT_FIXED; + break; + case -1: + ecc_result = YAFFS_ECC_RESULT_UNFIXED; + break; + default: + ecc_result = YAFFS_ECC_RESULT_UNKNOWN; + } + } + yaffs_unpack_tags2_tags_only(t, &pt->t); + + t->ecc_result = ecc_result; + + yaffs_dump_packed_tags2(pt); + yaffs_dump_tags2(t); +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_packedtags2.h b/target/linux/generic/files/fs/yaffs2/yaffs_packedtags2.h new file mode 100644 index 0000000..675e719 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_packedtags2.h @@ -0,0 +1,47 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +/* This is used to pack YAFFS2 tags, not YAFFS1tags. */ + +#ifndef __YAFFS_PACKEDTAGS2_H__ +#define __YAFFS_PACKEDTAGS2_H__ + +#include "yaffs_guts.h" +#include "yaffs_ecc.h" + +struct yaffs_packed_tags2_tags_only { + unsigned seq_number; + unsigned obj_id; + unsigned chunk_id; + unsigned n_bytes; +}; + +struct yaffs_packed_tags2 { + struct yaffs_packed_tags2_tags_only t; + struct yaffs_ecc_other ecc; +}; + +/* Full packed tags with ECC, used for oob tags */ +void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt, + const struct yaffs_ext_tags *t, int tags_ecc); +void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt, + int tags_ecc); + +/* Only the tags part (no ECC for use with inband tags */ +void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *pt, + const struct yaffs_ext_tags *t); +void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, + struct yaffs_packed_tags2_tags_only *pt); +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_summary.c b/target/linux/generic/files/fs/yaffs2/yaffs_summary.c new file mode 100644 index 0000000..3c9e723 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_summary.c @@ -0,0 +1,312 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Summaries write the useful part of the tags for the chunks in a block into an + * an array which is written to the last n chunks of the block. + * Reading the summaries gives all the tags for the block in one read. Much + * faster. + * + * Chunks holding summaries are marked with tags making it look like + * they are part of a fake file. + * + * The summary could also be used during gc. + * + */ + +#include "yaffs_summary.h" +#include "yaffs_packedtags2.h" +#include "yaffs_nand.h" +#include "yaffs_getblockinfo.h" +#include "yaffs_bitmap.h" + +/* + * The summary is built up in an array of summary tags. + * This gets written to the last one or two (maybe more) chunks in a block. + * A summary header is written as the first part of each chunk of summary data. + * The summary header must match or the summary is rejected. + */ + +/* Summary tags don't need the sequence number because that is redundant. */ +struct yaffs_summary_tags { + unsigned obj_id; + unsigned chunk_id; + unsigned n_bytes; +}; + +/* Summary header */ +struct yaffs_summary_header { + unsigned version; /* Must match current version */ + unsigned block; /* Must be this block */ + unsigned seq; /* Must be this sequence number */ + unsigned sum; /* Just add up all the bytes in the tags */ +}; + + +static void yaffs_summary_clear(struct yaffs_dev *dev) +{ + if (!dev->sum_tags) + return; + memset(dev->sum_tags, 0, dev->chunks_per_summary * + sizeof(struct yaffs_summary_tags)); +} + + +void yaffs_summary_deinit(struct yaffs_dev *dev) +{ + kfree(dev->sum_tags); + dev->sum_tags = NULL; + kfree(dev->gc_sum_tags); + dev->gc_sum_tags = NULL; + dev->chunks_per_summary = 0; +} + +int yaffs_summary_init(struct yaffs_dev *dev) +{ + int sum_bytes; + int chunks_used; /* Number of chunks used by summary */ + int sum_tags_bytes; + + sum_bytes = dev->param.chunks_per_block * + sizeof(struct yaffs_summary_tags); + + chunks_used = (sum_bytes + dev->data_bytes_per_chunk - 1)/ + (dev->data_bytes_per_chunk - + sizeof(struct yaffs_summary_header)); + + dev->chunks_per_summary = dev->param.chunks_per_block - chunks_used; + sum_tags_bytes = sizeof(struct yaffs_summary_tags) * + dev->chunks_per_summary; + dev->sum_tags = kmalloc(sum_tags_bytes, GFP_NOFS); + dev->gc_sum_tags = kmalloc(sum_tags_bytes, GFP_NOFS); + if (!dev->sum_tags || !dev->gc_sum_tags) { + yaffs_summary_deinit(dev); + return YAFFS_FAIL; + } + + yaffs_summary_clear(dev); + + return YAFFS_OK; +} + +static unsigned yaffs_summary_sum(struct yaffs_dev *dev) +{ + u8 *sum_buffer = (u8 *)dev->sum_tags; + int i; + unsigned sum = 0; + + i = sizeof(struct yaffs_summary_tags) * + dev->chunks_per_summary; + while (i > 0) { + sum += *sum_buffer; + sum_buffer++; + i--; + } + + return sum; +} + +static int yaffs_summary_write(struct yaffs_dev *dev, int blk) +{ + struct yaffs_ext_tags tags; + u8 *buffer; + u8 *sum_buffer = (u8 *)dev->sum_tags; + int n_bytes; + int chunk_in_nand; + int chunk_in_block; + int result; + int this_tx; + struct yaffs_summary_header hdr; + int sum_bytes_per_chunk = dev->data_bytes_per_chunk - sizeof(hdr); + struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk); + + buffer = yaffs_get_temp_buffer(dev); + n_bytes = sizeof(struct yaffs_summary_tags) * + dev->chunks_per_summary; + memset(&tags, 0, sizeof(struct yaffs_ext_tags)); + tags.obj_id = YAFFS_OBJECTID_SUMMARY; + tags.chunk_id = 1; + chunk_in_block = dev->chunks_per_summary; + chunk_in_nand = dev->alloc_block * dev->param.chunks_per_block + + dev->chunks_per_summary; + hdr.version = YAFFS_SUMMARY_VERSION; + hdr.block = blk; + hdr.seq = bi->seq_number; + hdr.sum = yaffs_summary_sum(dev); + + do { + this_tx = n_bytes; + if (this_tx > sum_bytes_per_chunk) + this_tx = sum_bytes_per_chunk; + memcpy(buffer, &hdr, sizeof(hdr)); + memcpy(buffer + sizeof(hdr), sum_buffer, this_tx); + tags.n_bytes = this_tx + sizeof(hdr); + result = yaffs_wr_chunk_tags_nand(dev, chunk_in_nand, + buffer, &tags); + + if (result != YAFFS_OK) + break; + yaffs_set_chunk_bit(dev, blk, chunk_in_block); + bi->pages_in_use++; + dev->n_free_chunks--; + + n_bytes -= this_tx; + sum_buffer += this_tx; + chunk_in_nand++; + chunk_in_block++; + tags.chunk_id++; + } while (result == YAFFS_OK && n_bytes > 0); + yaffs_release_temp_buffer(dev, buffer); + + + if (result == YAFFS_OK) + bi->has_summary = 1; + + + return result; +} + +int yaffs_summary_read(struct yaffs_dev *dev, + struct yaffs_summary_tags *st, + int blk) +{ + struct yaffs_ext_tags tags; + u8 *buffer; + u8 *sum_buffer = (u8 *)st; + int n_bytes; + int chunk_id; + int chunk_in_nand; + int chunk_in_block; + int result; + int this_tx; + struct yaffs_summary_header hdr; + struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk); + int sum_bytes_per_chunk = dev->data_bytes_per_chunk - sizeof(hdr); + int sum_tags_bytes; + + sum_tags_bytes = sizeof(struct yaffs_summary_tags) * + dev->chunks_per_summary; + buffer = yaffs_get_temp_buffer(dev); + n_bytes = sizeof(struct yaffs_summary_tags) * dev->chunks_per_summary; + chunk_in_block = dev->chunks_per_summary; + chunk_in_nand = blk * dev->param.chunks_per_block + + dev->chunks_per_summary; + chunk_id = 1; + do { + this_tx = n_bytes; + if (this_tx > sum_bytes_per_chunk) + this_tx = sum_bytes_per_chunk; + result = yaffs_rd_chunk_tags_nand(dev, chunk_in_nand, + buffer, &tags); + + if (tags.chunk_id != chunk_id || + tags.obj_id != YAFFS_OBJECTID_SUMMARY || + tags.chunk_used == 0 || + tags.ecc_result > YAFFS_ECC_RESULT_FIXED || + tags.n_bytes != (this_tx + sizeof(hdr))) + result = YAFFS_FAIL; + if (result != YAFFS_OK) + break; + + if (st == dev->sum_tags) { + /* If we're scanning then update the block info */ + yaffs_set_chunk_bit(dev, blk, chunk_in_block); + bi->pages_in_use++; + } + memcpy(&hdr, buffer, sizeof(hdr)); + memcpy(sum_buffer, buffer + sizeof(hdr), this_tx); + n_bytes -= this_tx; + sum_buffer += this_tx; + chunk_in_nand++; + chunk_in_block++; + chunk_id++; + } while (result == YAFFS_OK && n_bytes > 0); + yaffs_release_temp_buffer(dev, buffer); + + if (result == YAFFS_OK) { + /* Verify header */ + if (hdr.version != YAFFS_SUMMARY_VERSION || + hdr.seq != bi->seq_number || + hdr.sum != yaffs_summary_sum(dev)) + result = YAFFS_FAIL; + } + + if (st == dev->sum_tags && result == YAFFS_OK) + bi->has_summary = 1; + + return result; +} + +int yaffs_summary_add(struct yaffs_dev *dev, + struct yaffs_ext_tags *tags, + int chunk_in_nand) +{ + struct yaffs_packed_tags2_tags_only tags_only; + struct yaffs_summary_tags *sum_tags; + int block_in_nand = chunk_in_nand / dev->param.chunks_per_block; + int chunk_in_block = chunk_in_nand % dev->param.chunks_per_block; + + if (!dev->sum_tags) + return YAFFS_OK; + + if (chunk_in_block >= 0 && chunk_in_block < dev->chunks_per_summary) { + yaffs_pack_tags2_tags_only(&tags_only, tags); + sum_tags = &dev->sum_tags[chunk_in_block]; + sum_tags->chunk_id = tags_only.chunk_id; + sum_tags->n_bytes = tags_only.n_bytes; + sum_tags->obj_id = tags_only.obj_id; + + if (chunk_in_block == dev->chunks_per_summary - 1) { + /* Time to write out the summary */ + yaffs_summary_write(dev, block_in_nand); + yaffs_summary_clear(dev); + yaffs_skip_rest_of_block(dev); + } + } + return YAFFS_OK; +} + +int yaffs_summary_fetch(struct yaffs_dev *dev, + struct yaffs_ext_tags *tags, + int chunk_in_block) +{ + struct yaffs_packed_tags2_tags_only tags_only; + struct yaffs_summary_tags *sum_tags; + if (chunk_in_block >= 0 && chunk_in_block < dev->chunks_per_summary) { + sum_tags = &dev->sum_tags[chunk_in_block]; + tags_only.chunk_id = sum_tags->chunk_id; + tags_only.n_bytes = sum_tags->n_bytes; + tags_only.obj_id = sum_tags->obj_id; + yaffs_unpack_tags2_tags_only(tags, &tags_only); + return YAFFS_OK; + } + return YAFFS_FAIL; +} + +void yaffs_summary_gc(struct yaffs_dev *dev, int blk) +{ + struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk); + int i; + + if (!bi->has_summary) + return; + + for (i = dev->chunks_per_summary; + i < dev->param.chunks_per_block; + i++) { + if (yaffs_check_chunk_bit(dev, blk, i)) { + yaffs_clear_chunk_bit(dev, blk, i); + bi->pages_in_use--; + dev->n_free_chunks++; + } + } +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_summary.h b/target/linux/generic/files/fs/yaffs2/yaffs_summary.h new file mode 100644 index 0000000..be141d0 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_summary.h @@ -0,0 +1,37 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_SUMMARY_H__ +#define __YAFFS_SUMMARY_H__ + +#include "yaffs_packedtags2.h" + + +int yaffs_summary_init(struct yaffs_dev *dev); +void yaffs_summary_deinit(struct yaffs_dev *dev); + +int yaffs_summary_add(struct yaffs_dev *dev, + struct yaffs_ext_tags *tags, + int chunk_in_block); +int yaffs_summary_fetch(struct yaffs_dev *dev, + struct yaffs_ext_tags *tags, + int chunk_in_block); +int yaffs_summary_read(struct yaffs_dev *dev, + struct yaffs_summary_tags *st, + int blk); +void yaffs_summary_gc(struct yaffs_dev *dev, int blk); + + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_tagscompat.c b/target/linux/generic/files/fs/yaffs2/yaffs_tagscompat.c new file mode 100644 index 0000000..092430b --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_tagscompat.c @@ -0,0 +1,381 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_guts.h" +#include "yaffs_tagscompat.h" +#include "yaffs_ecc.h" +#include "yaffs_getblockinfo.h" +#include "yaffs_trace.h" + +static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk); + + +/********** Tags ECC calculations *********/ + + +void yaffs_calc_tags_ecc(struct yaffs_tags *tags) +{ + /* Calculate an ecc */ + unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes; + unsigned i, j; + unsigned ecc = 0; + unsigned bit = 0; + + tags->ecc = 0; + + for (i = 0; i < 8; i++) { + for (j = 1; j & 0xff; j <<= 1) { + bit++; + if (b[i] & j) + ecc ^= bit; + } + } + tags->ecc = ecc; +} + +int yaffs_check_tags_ecc(struct yaffs_tags *tags) +{ + unsigned ecc = tags->ecc; + + yaffs_calc_tags_ecc(tags); + + ecc ^= tags->ecc; + + if (ecc && ecc <= 64) { + /* TODO: Handle the failure better. Retire? */ + unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes; + + ecc--; + + b[ecc / 8] ^= (1 << (ecc & 7)); + + /* Now recvalc the ecc */ + yaffs_calc_tags_ecc(tags); + + return 1; /* recovered error */ + } else if (ecc) { + /* Wierd ecc failure value */ + /* TODO Need to do somethiong here */ + return -1; /* unrecovered error */ + } + return 0; +} + +/********** Tags **********/ + +static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr, + struct yaffs_tags *tags_ptr) +{ + union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr; + + yaffs_calc_tags_ecc(tags_ptr); + + spare_ptr->tb0 = tu->as_bytes[0]; + spare_ptr->tb1 = tu->as_bytes[1]; + spare_ptr->tb2 = tu->as_bytes[2]; + spare_ptr->tb3 = tu->as_bytes[3]; + spare_ptr->tb4 = tu->as_bytes[4]; + spare_ptr->tb5 = tu->as_bytes[5]; + spare_ptr->tb6 = tu->as_bytes[6]; + spare_ptr->tb7 = tu->as_bytes[7]; +} + +static void yaffs_get_tags_from_spare(struct yaffs_dev *dev, + struct yaffs_spare *spare_ptr, + struct yaffs_tags *tags_ptr) +{ + union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr; + int result; + + tu->as_bytes[0] = spare_ptr->tb0; + tu->as_bytes[1] = spare_ptr->tb1; + tu->as_bytes[2] = spare_ptr->tb2; + tu->as_bytes[3] = spare_ptr->tb3; + tu->as_bytes[4] = spare_ptr->tb4; + tu->as_bytes[5] = spare_ptr->tb5; + tu->as_bytes[6] = spare_ptr->tb6; + tu->as_bytes[7] = spare_ptr->tb7; + + result = yaffs_check_tags_ecc(tags_ptr); + if (result > 0) + dev->n_tags_ecc_fixed++; + else if (result < 0) + dev->n_tags_ecc_unfixed++; +} + +static void yaffs_spare_init(struct yaffs_spare *spare) +{ + memset(spare, 0xff, sizeof(struct yaffs_spare)); +} + +static int yaffs_wr_nand(struct yaffs_dev *dev, + int nand_chunk, const u8 *data, + struct yaffs_spare *spare) +{ + int data_size = dev->data_bytes_per_chunk; + + return dev->drv.drv_write_chunk_fn(dev, nand_chunk, + data, data_size, + (u8 *) spare, sizeof(*spare)); +} + +static int yaffs_rd_chunk_nand(struct yaffs_dev *dev, + int nand_chunk, + u8 *data, + struct yaffs_spare *spare, + enum yaffs_ecc_result *ecc_result, + int correct_errors) +{ + int ret_val; + struct yaffs_spare local_spare; + int data_size; + int spare_size; + int ecc_result1, ecc_result2; + u8 calc_ecc[3]; + + if (!spare) { + /* If we don't have a real spare, then we use a local one. */ + /* Need this for the calculation of the ecc */ + spare = &local_spare; + } + data_size = dev->data_bytes_per_chunk; + spare_size = sizeof(struct yaffs_spare); + + if (dev->param.use_nand_ecc) + return dev->drv.drv_read_chunk_fn(dev, nand_chunk, + data, data_size, + (u8 *) spare, spare_size, + ecc_result); + + + /* Handle the ECC at this level. */ + + ret_val = dev->drv.drv_read_chunk_fn(dev, nand_chunk, + data, data_size, + (u8 *)spare, spare_size, + NULL); + if (!data || !correct_errors) + return ret_val; + + /* Do ECC correction if needed. */ + yaffs_ecc_calc(data, calc_ecc); + ecc_result1 = yaffs_ecc_correct(data, spare->ecc1, calc_ecc); + yaffs_ecc_calc(&data[256], calc_ecc); + ecc_result2 = yaffs_ecc_correct(&data[256], spare->ecc2, calc_ecc); + + if (ecc_result1 > 0) { + yaffs_trace(YAFFS_TRACE_ERROR, + "**>>yaffs ecc error fix performed on chunk %d:0", + nand_chunk); + dev->n_ecc_fixed++; + } else if (ecc_result1 < 0) { + yaffs_trace(YAFFS_TRACE_ERROR, + "**>>yaffs ecc error unfixed on chunk %d:0", + nand_chunk); + dev->n_ecc_unfixed++; + } + + if (ecc_result2 > 0) { + yaffs_trace(YAFFS_TRACE_ERROR, + "**>>yaffs ecc error fix performed on chunk %d:1", + nand_chunk); + dev->n_ecc_fixed++; + } else if (ecc_result2 < 0) { + yaffs_trace(YAFFS_TRACE_ERROR, + "**>>yaffs ecc error unfixed on chunk %d:1", + nand_chunk); + dev->n_ecc_unfixed++; + } + + if (ecc_result1 || ecc_result2) { + /* We had a data problem on this page */ + yaffs_handle_rd_data_error(dev, nand_chunk); + } + + if (ecc_result1 < 0 || ecc_result2 < 0) + *ecc_result = YAFFS_ECC_RESULT_UNFIXED; + else if (ecc_result1 > 0 || ecc_result2 > 0) + *ecc_result = YAFFS_ECC_RESULT_FIXED; + else + *ecc_result = YAFFS_ECC_RESULT_NO_ERROR; + + return ret_val; +} + +/* + * Functions for robustisizing + */ + +static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk) +{ + int flash_block = nand_chunk / dev->param.chunks_per_block; + + /* Mark the block for retirement */ + yaffs_get_block_info(dev, flash_block + dev->block_offset)-> + needs_retiring = 1; + yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, + "**>>Block %d marked for retirement", + flash_block); + + /* TODO: + * Just do a garbage collection on the affected block + * then retire the block + * NB recursion + */ +} + +static int yaffs_tags_compat_wr(struct yaffs_dev *dev, + int nand_chunk, + const u8 *data, const struct yaffs_ext_tags *ext_tags) +{ + struct yaffs_spare spare; + struct yaffs_tags tags; + + yaffs_spare_init(&spare); + + if (ext_tags->is_deleted) + spare.page_status = 0; + else { + tags.obj_id = ext_tags->obj_id; + tags.chunk_id = ext_tags->chunk_id; + + tags.n_bytes_lsb = ext_tags->n_bytes & (1024 - 1); + + if (dev->data_bytes_per_chunk >= 1024) + tags.n_bytes_msb = (ext_tags->n_bytes >> 10) & 3; + else + tags.n_bytes_msb = 3; + + tags.serial_number = ext_tags->serial_number; + + if (!dev->param.use_nand_ecc && data) { + yaffs_ecc_calc(data, spare.ecc1); + yaffs_ecc_calc(&data[256], spare.ecc2); + } + + yaffs_load_tags_to_spare(&spare, &tags); + } + return yaffs_wr_nand(dev, nand_chunk, data, &spare); +} + +static int yaffs_tags_compat_rd(struct yaffs_dev *dev, + int nand_chunk, + u8 *data, struct yaffs_ext_tags *ext_tags) +{ + struct yaffs_spare spare; + struct yaffs_tags tags; + enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_UNKNOWN; + static struct yaffs_spare spare_ff; + static int init; + int deleted; + + if (!init) { + memset(&spare_ff, 0xff, sizeof(spare_ff)); + init = 1; + } + + if (!yaffs_rd_chunk_nand(dev, nand_chunk, + data, &spare, &ecc_result, 1)) + return YAFFS_FAIL; + + /* ext_tags may be NULL */ + if (!ext_tags) + return YAFFS_OK; + + deleted = (hweight8(spare.page_status) < 7) ? 1 : 0; + + ext_tags->is_deleted = deleted; + ext_tags->ecc_result = ecc_result; + ext_tags->block_bad = 0; /* We're reading it */ + /* therefore it is not a bad block */ + ext_tags->chunk_used = + memcmp(&spare_ff, &spare, sizeof(spare_ff)) ? 1 : 0; + + if (ext_tags->chunk_used) { + yaffs_get_tags_from_spare(dev, &spare, &tags); + ext_tags->obj_id = tags.obj_id; + ext_tags->chunk_id = tags.chunk_id; + ext_tags->n_bytes = tags.n_bytes_lsb; + + if (dev->data_bytes_per_chunk >= 1024) + ext_tags->n_bytes |= + (((unsigned)tags.n_bytes_msb) << 10); + + ext_tags->serial_number = tags.serial_number; + } + + return YAFFS_OK; +} + +static int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int flash_block) +{ + struct yaffs_spare spare; + + memset(&spare, 0xff, sizeof(struct yaffs_spare)); + + spare.block_status = 'Y'; + + yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block, NULL, + &spare); + yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block + 1, + NULL, &spare); + + return YAFFS_OK; +} + +static int yaffs_tags_compat_query_block(struct yaffs_dev *dev, + int block_no, + enum yaffs_block_state *state, + u32 *seq_number) +{ + struct yaffs_spare spare0, spare1; + static struct yaffs_spare spare_ff; + static int init; + enum yaffs_ecc_result dummy; + + if (!init) { + memset(&spare_ff, 0xff, sizeof(spare_ff)); + init = 1; + } + + *seq_number = 0; + + /* Look for bad block markers in the first two chunks */ + yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block, + NULL, &spare0, &dummy, 0); + yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block + 1, + NULL, &spare1, &dummy, 0); + + if (hweight8(spare0.block_status & spare1.block_status) < 7) + *state = YAFFS_BLOCK_STATE_DEAD; + else if (memcmp(&spare_ff, &spare0, sizeof(spare_ff)) == 0) + *state = YAFFS_BLOCK_STATE_EMPTY; + else + *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; + + return YAFFS_OK; +} + +void yaffs_tags_compat_install(struct yaffs_dev *dev) +{ + if(dev->param.is_yaffs2) + return; + if(!dev->tagger.write_chunk_tags_fn) + dev->tagger.write_chunk_tags_fn = yaffs_tags_compat_wr; + if(!dev->tagger.read_chunk_tags_fn) + dev->tagger.read_chunk_tags_fn = yaffs_tags_compat_rd; + if(!dev->tagger.query_block_fn) + dev->tagger.query_block_fn = yaffs_tags_compat_query_block; + if(!dev->tagger.mark_bad_fn) + dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_tagscompat.h b/target/linux/generic/files/fs/yaffs2/yaffs_tagscompat.h new file mode 100644 index 0000000..92d298a --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_tagscompat.h @@ -0,0 +1,44 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_TAGSCOMPAT_H__ +#define __YAFFS_TAGSCOMPAT_H__ + + +#include "yaffs_guts.h" + +#if 0 + + +int yaffs_tags_compat_wr(struct yaffs_dev *dev, + int nand_chunk, + const u8 *data, const struct yaffs_ext_tags *tags); +int yaffs_tags_compat_rd(struct yaffs_dev *dev, + int nand_chunk, + u8 *data, struct yaffs_ext_tags *tags); +int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no); +int yaffs_tags_compat_query_block(struct yaffs_dev *dev, + int block_no, + enum yaffs_block_state *state, + u32 *seq_number); + +#endif + + +void yaffs_tags_compat_install(struct yaffs_dev *dev); +void yaffs_calc_tags_ecc(struct yaffs_tags *tags); +int yaffs_check_tags_ecc(struct yaffs_tags *tags); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_tagsmarshall.c b/target/linux/generic/files/fs/yaffs2/yaffs_tagsmarshall.c new file mode 100644 index 0000000..44a83b1 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_tagsmarshall.c @@ -0,0 +1,199 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_guts.h" +#include "yaffs_trace.h" +#include "yaffs_packedtags2.h" + +static int yaffs_tags_marshall_write(struct yaffs_dev *dev, + int nand_chunk, const u8 *data, + const struct yaffs_ext_tags *tags) +{ + struct yaffs_packed_tags2 pt; + int retval; + + int packed_tags_size = + dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt); + void *packed_tags_ptr = + dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt; + + yaffs_trace(YAFFS_TRACE_MTD, + "yaffs_tags_marshall_write chunk %d data %p tags %p", + nand_chunk, data, tags); + + /* For yaffs2 writing there must be both data and tags. + * If we're using inband tags, then the tags are stuffed into + * the end of the data buffer. + */ + if (!data || !tags) + BUG(); + else if (dev->param.inband_tags) { + struct yaffs_packed_tags2_tags_only *pt2tp; + pt2tp = + (struct yaffs_packed_tags2_tags_only *)(data + + dev-> + data_bytes_per_chunk); + yaffs_pack_tags2_tags_only(pt2tp, tags); + } else { + yaffs_pack_tags2(&pt, tags, !dev->param.no_tags_ecc); + } + + retval = dev->drv.drv_write_chunk_fn(dev, nand_chunk, + data, dev->param.total_bytes_per_chunk, + (dev->param.inband_tags) ? NULL : packed_tags_ptr, + (dev->param.inband_tags) ? 0 : packed_tags_size); + + return retval; +} + +static int yaffs_tags_marshall_read(struct yaffs_dev *dev, + int nand_chunk, u8 *data, + struct yaffs_ext_tags *tags) +{ + int retval = 0; + int local_data = 0; + u8 spare_buffer[100]; + enum yaffs_ecc_result ecc_result; + + struct yaffs_packed_tags2 pt; + + int packed_tags_size = + dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt); + void *packed_tags_ptr = + dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt; + + yaffs_trace(YAFFS_TRACE_MTD, + "yaffs_tags_marshall_read chunk %d data %p tags %p", + nand_chunk, data, tags); + + if (dev->param.inband_tags) { + if (!data) { + local_data = 1; + data = yaffs_get_temp_buffer(dev); + } + } + + if (dev->param.inband_tags || (data && !tags)) + retval = dev->drv.drv_read_chunk_fn(dev, nand_chunk, + data, dev->param.total_bytes_per_chunk, + NULL, 0, + &ecc_result); + else if (tags) + retval = dev->drv.drv_read_chunk_fn(dev, nand_chunk, + data, dev->param.total_bytes_per_chunk, + spare_buffer, packed_tags_size, + &ecc_result); + else + BUG(); + + + if (dev->param.inband_tags) { + if (tags) { + struct yaffs_packed_tags2_tags_only *pt2tp; + pt2tp = + (struct yaffs_packed_tags2_tags_only *) + &data[dev->data_bytes_per_chunk]; + yaffs_unpack_tags2_tags_only(tags, pt2tp); + } + } else if (tags) { + memcpy(packed_tags_ptr, spare_buffer, packed_tags_size); + yaffs_unpack_tags2(tags, &pt, !dev->param.no_tags_ecc); + } + + if (local_data) + yaffs_release_temp_buffer(dev, data); + + if (tags && ecc_result == YAFFS_ECC_RESULT_UNFIXED) { + tags->ecc_result = YAFFS_ECC_RESULT_UNFIXED; + dev->n_ecc_unfixed++; + } + + if (tags && ecc_result == -YAFFS_ECC_RESULT_FIXED) { + if (tags->ecc_result <= YAFFS_ECC_RESULT_NO_ERROR) + tags->ecc_result = YAFFS_ECC_RESULT_FIXED; + dev->n_ecc_fixed++; + } + + if (ecc_result < YAFFS_ECC_RESULT_UNFIXED) + return YAFFS_OK; + else + return YAFFS_FAIL; +} + +static int yaffs_tags_marshall_query_block(struct yaffs_dev *dev, int block_no, + enum yaffs_block_state *state, + u32 *seq_number) +{ + int retval; + + yaffs_trace(YAFFS_TRACE_MTD, "yaffs_tags_marshall_query_block %d", + block_no); + + retval = dev->drv.drv_check_bad_fn(dev, block_no); + + if (retval== YAFFS_FAIL) { + yaffs_trace(YAFFS_TRACE_MTD, "block is bad"); + + *state = YAFFS_BLOCK_STATE_DEAD; + *seq_number = 0; + } else { + struct yaffs_ext_tags t; + + yaffs_tags_marshall_read(dev, + block_no * dev->param.chunks_per_block, + NULL, &t); + + if (t.chunk_used) { + *seq_number = t.seq_number; + *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; + } else { + *seq_number = 0; + *state = YAFFS_BLOCK_STATE_EMPTY; + } + } + + yaffs_trace(YAFFS_TRACE_MTD, + "block query returns seq %d state %d", + *seq_number, *state); + + if (retval == 0) + return YAFFS_OK; + else + return YAFFS_FAIL; +} + +static int yaffs_tags_marshall_mark_bad(struct yaffs_dev *dev, int block_no) +{ + return dev->drv.drv_mark_bad_fn(dev, block_no); + +} + + +void yaffs_tags_marshall_install(struct yaffs_dev *dev) +{ + if (!dev->param.is_yaffs2) + return; + + if (!dev->tagger.write_chunk_tags_fn) + dev->tagger.write_chunk_tags_fn = yaffs_tags_marshall_write; + + if (!dev->tagger.read_chunk_tags_fn) + dev->tagger.read_chunk_tags_fn = yaffs_tags_marshall_read; + + if (!dev->tagger.query_block_fn) + dev->tagger.query_block_fn = yaffs_tags_marshall_query_block; + + if (!dev->tagger.mark_bad_fn) + dev->tagger.mark_bad_fn = yaffs_tags_marshall_mark_bad; + +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_tagsmarshall.h b/target/linux/generic/files/fs/yaffs2/yaffs_tagsmarshall.h new file mode 100644 index 0000000..bf3e68a --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_tagsmarshall.h @@ -0,0 +1,22 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_TAGSMARSHALL_H__ +#define __YAFFS_TAGSMARSHALL_H__ + +#include "yaffs_guts.h" +void yaffs_tags_marshall_install(struct yaffs_dev *dev); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_trace.h b/target/linux/generic/files/fs/yaffs2/yaffs_trace.h new file mode 100644 index 0000000..fd26054 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_trace.h @@ -0,0 +1,57 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YTRACE_H__ +#define __YTRACE_H__ + +extern unsigned int yaffs_trace_mask; +extern unsigned int yaffs_wr_attempts; + +/* + * Tracing flags. + * The flags masked in YAFFS_TRACE_ALWAYS are always traced. + */ + +#define YAFFS_TRACE_OS 0x00000002 +#define YAFFS_TRACE_ALLOCATE 0x00000004 +#define YAFFS_TRACE_SCAN 0x00000008 +#define YAFFS_TRACE_BAD_BLOCKS 0x00000010 +#define YAFFS_TRACE_ERASE 0x00000020 +#define YAFFS_TRACE_GC 0x00000040 +#define YAFFS_TRACE_WRITE 0x00000080 +#define YAFFS_TRACE_TRACING 0x00000100 +#define YAFFS_TRACE_DELETION 0x00000200 +#define YAFFS_TRACE_BUFFERS 0x00000400 +#define YAFFS_TRACE_NANDACCESS 0x00000800 +#define YAFFS_TRACE_GC_DETAIL 0x00001000 +#define YAFFS_TRACE_SCAN_DEBUG 0x00002000 +#define YAFFS_TRACE_MTD 0x00004000 +#define YAFFS_TRACE_CHECKPOINT 0x00008000 + +#define YAFFS_TRACE_VERIFY 0x00010000 +#define YAFFS_TRACE_VERIFY_NAND 0x00020000 +#define YAFFS_TRACE_VERIFY_FULL 0x00040000 +#define YAFFS_TRACE_VERIFY_ALL 0x000f0000 + +#define YAFFS_TRACE_SYNC 0x00100000 +#define YAFFS_TRACE_BACKGROUND 0x00200000 +#define YAFFS_TRACE_LOCK 0x00400000 +#define YAFFS_TRACE_MOUNT 0x00800000 + +#define YAFFS_TRACE_ERROR 0x40000000 +#define YAFFS_TRACE_BUG 0x80000000 +#define YAFFS_TRACE_ALWAYS 0xf0000000 + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_verify.c b/target/linux/generic/files/fs/yaffs2/yaffs_verify.c new file mode 100644 index 0000000..e8f2f0a --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_verify.c @@ -0,0 +1,529 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_verify.h" +#include "yaffs_trace.h" +#include "yaffs_bitmap.h" +#include "yaffs_getblockinfo.h" +#include "yaffs_nand.h" + +int yaffs_skip_verification(struct yaffs_dev *dev) +{ + (void) dev; + return !(yaffs_trace_mask & + (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL)); +} + +static int yaffs_skip_full_verification(struct yaffs_dev *dev) +{ + (void) dev; + return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_FULL)); +} + +static int yaffs_skip_nand_verification(struct yaffs_dev *dev) +{ + (void) dev; + return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_NAND)); +} + +static const char * const block_state_name[] = { + "Unknown", + "Needs scan", + "Scanning", + "Empty", + "Allocating", + "Full", + "Dirty", + "Checkpoint", + "Collecting", + "Dead" +}; + +void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, int n) +{ + int actually_used; + int in_use; + + if (yaffs_skip_verification(dev)) + return; + + /* Report illegal runtime states */ + if (bi->block_state >= YAFFS_NUMBER_OF_BLOCK_STATES) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Block %d has undefined state %d", + n, bi->block_state); + + switch (bi->block_state) { + case YAFFS_BLOCK_STATE_UNKNOWN: + case YAFFS_BLOCK_STATE_SCANNING: + case YAFFS_BLOCK_STATE_NEEDS_SCAN: + yaffs_trace(YAFFS_TRACE_VERIFY, + "Block %d has bad run-state %s", + n, block_state_name[bi->block_state]); + } + + /* Check pages in use and soft deletions are legal */ + + actually_used = bi->pages_in_use - bi->soft_del_pages; + + if (bi->pages_in_use < 0 || + bi->pages_in_use > dev->param.chunks_per_block || + bi->soft_del_pages < 0 || + bi->soft_del_pages > dev->param.chunks_per_block || + actually_used < 0 || actually_used > dev->param.chunks_per_block) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Block %d has illegal values pages_in_used %d soft_del_pages %d", + n, bi->pages_in_use, bi->soft_del_pages); + + /* Check chunk bitmap legal */ + in_use = yaffs_count_chunk_bits(dev, n); + if (in_use != bi->pages_in_use) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Block %d has inconsistent values pages_in_use %d counted chunk bits %d", + n, bi->pages_in_use, in_use); +} + +void yaffs_verify_collected_blk(struct yaffs_dev *dev, + struct yaffs_block_info *bi, int n) +{ + yaffs_verify_blk(dev, bi, n); + + /* After collection the block should be in the erased state */ + + if (bi->block_state != YAFFS_BLOCK_STATE_COLLECTING && + bi->block_state != YAFFS_BLOCK_STATE_EMPTY) { + yaffs_trace(YAFFS_TRACE_ERROR, + "Block %d is in state %d after gc, should be erased", + n, bi->block_state); + } +} + +void yaffs_verify_blocks(struct yaffs_dev *dev) +{ + int i; + int state_count[YAFFS_NUMBER_OF_BLOCK_STATES]; + int illegal_states = 0; + + if (yaffs_skip_verification(dev)) + return; + + memset(state_count, 0, sizeof(state_count)); + + for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { + struct yaffs_block_info *bi = yaffs_get_block_info(dev, i); + yaffs_verify_blk(dev, bi, i); + + if (bi->block_state < YAFFS_NUMBER_OF_BLOCK_STATES) + state_count[bi->block_state]++; + else + illegal_states++; + } + + yaffs_trace(YAFFS_TRACE_VERIFY, "Block summary"); + + yaffs_trace(YAFFS_TRACE_VERIFY, + "%d blocks have illegal states", + illegal_states); + if (state_count[YAFFS_BLOCK_STATE_ALLOCATING] > 1) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Too many allocating blocks"); + + for (i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++) + yaffs_trace(YAFFS_TRACE_VERIFY, + "%s %d blocks", + block_state_name[i], state_count[i]); + + if (dev->blocks_in_checkpt != state_count[YAFFS_BLOCK_STATE_CHECKPOINT]) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Checkpoint block count wrong dev %d count %d", + dev->blocks_in_checkpt, + state_count[YAFFS_BLOCK_STATE_CHECKPOINT]); + + if (dev->n_erased_blocks != state_count[YAFFS_BLOCK_STATE_EMPTY]) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Erased block count wrong dev %d count %d", + dev->n_erased_blocks, + state_count[YAFFS_BLOCK_STATE_EMPTY]); + + if (state_count[YAFFS_BLOCK_STATE_COLLECTING] > 1) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Too many collecting blocks %d (max is 1)", + state_count[YAFFS_BLOCK_STATE_COLLECTING]); +} + +/* + * Verify the object header. oh must be valid, but obj and tags may be NULL in + * which case those tests will not be performed. + */ +void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, + struct yaffs_ext_tags *tags, int parent_check) +{ + if (obj && yaffs_skip_verification(obj->my_dev)) + return; + + if (!(tags && obj && oh)) { + yaffs_trace(YAFFS_TRACE_VERIFY, + "Verifying object header tags %p obj %p oh %p", + tags, obj, oh); + return; + } + + if (oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN || + oh->type > YAFFS_OBJECT_TYPE_MAX) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d header type is illegal value 0x%x", + tags->obj_id, oh->type); + + if (tags->obj_id != obj->obj_id) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d header mismatch obj_id %d", + tags->obj_id, obj->obj_id); + + /* + * Check that the object's parent ids match if parent_check requested. + * + * Tests do not apply to the root object. + */ + + if (parent_check && tags->obj_id > 1 && !obj->parent) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d header mismatch parent_id %d obj->parent is NULL", + tags->obj_id, oh->parent_obj_id); + + if (parent_check && obj->parent && + oh->parent_obj_id != obj->parent->obj_id && + (oh->parent_obj_id != YAFFS_OBJECTID_UNLINKED || + obj->parent->obj_id != YAFFS_OBJECTID_DELETED)) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d header mismatch parent_id %d parent_obj_id %d", + tags->obj_id, oh->parent_obj_id, + obj->parent->obj_id); + + if (tags->obj_id > 1 && oh->name[0] == 0) /* Null name */ + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d header name is NULL", + obj->obj_id); + + if (tags->obj_id > 1 && ((u8) (oh->name[0])) == 0xff) /* Junk name */ + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d header name is 0xff", + obj->obj_id); +} + +void yaffs_verify_file(struct yaffs_obj *obj) +{ + u32 x; + int required_depth; + int actual_depth; + int last_chunk; + u32 offset_in_chunk; + u32 the_chunk; + + u32 i; + struct yaffs_dev *dev; + struct yaffs_ext_tags tags; + struct yaffs_tnode *tn; + u32 obj_id; + + if (!obj) + return; + + if (yaffs_skip_verification(obj->my_dev)) + return; + + dev = obj->my_dev; + obj_id = obj->obj_id; + + + /* Check file size is consistent with tnode depth */ + yaffs_addr_to_chunk(dev, obj->variant.file_variant.file_size, + &last_chunk, &offset_in_chunk); + last_chunk++; + x = last_chunk >> YAFFS_TNODES_LEVEL0_BITS; + required_depth = 0; + while (x > 0) { + x >>= YAFFS_TNODES_INTERNAL_BITS; + required_depth++; + } + + actual_depth = obj->variant.file_variant.top_level; + + /* Check that the chunks in the tnode tree are all correct. + * We do this by scanning through the tnode tree and + * checking the tags for every chunk match. + */ + + if (yaffs_skip_nand_verification(dev)) + return; + + for (i = 1; i <= last_chunk; i++) { + tn = yaffs_find_tnode_0(dev, &obj->variant.file_variant, i); + + if (!tn) + continue; + + the_chunk = yaffs_get_group_base(dev, tn, i); + if (the_chunk > 0) { + yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL, + &tags); + if (tags.obj_id != obj_id || tags.chunk_id != i) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Object %d chunk_id %d NAND mismatch chunk %d tags (%d:%d)", + obj_id, i, the_chunk, + tags.obj_id, tags.chunk_id); + } + } +} + +void yaffs_verify_link(struct yaffs_obj *obj) +{ + if (obj && yaffs_skip_verification(obj->my_dev)) + return; + + /* Verify sane equivalent object */ +} + +void yaffs_verify_symlink(struct yaffs_obj *obj) +{ + if (obj && yaffs_skip_verification(obj->my_dev)) + return; + + /* Verify symlink string */ +} + +void yaffs_verify_special(struct yaffs_obj *obj) +{ + if (obj && yaffs_skip_verification(obj->my_dev)) + return; +} + +void yaffs_verify_obj(struct yaffs_obj *obj) +{ + struct yaffs_dev *dev; + u32 chunk_min; + u32 chunk_max; + u32 chunk_id_ok; + u32 chunk_in_range; + u32 chunk_wrongly_deleted; + u32 chunk_valid; + + if (!obj) + return; + + if (obj->being_created) + return; + + dev = obj->my_dev; + + if (yaffs_skip_verification(dev)) + return; + + /* Check sane object header chunk */ + + chunk_min = dev->internal_start_block * dev->param.chunks_per_block; + chunk_max = + (dev->internal_end_block + 1) * dev->param.chunks_per_block - 1; + + chunk_in_range = (((unsigned)(obj->hdr_chunk)) >= chunk_min && + ((unsigned)(obj->hdr_chunk)) <= chunk_max); + chunk_id_ok = chunk_in_range || (obj->hdr_chunk == 0); + chunk_valid = chunk_in_range && + yaffs_check_chunk_bit(dev, + obj->hdr_chunk / dev->param.chunks_per_block, + obj->hdr_chunk % dev->param.chunks_per_block); + chunk_wrongly_deleted = chunk_in_range && !chunk_valid; + + if (!obj->fake && (!chunk_id_ok || chunk_wrongly_deleted)) + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d has chunk_id %d %s %s", + obj->obj_id, obj->hdr_chunk, + chunk_id_ok ? "" : ",out of range", + chunk_wrongly_deleted ? ",marked as deleted" : ""); + + if (chunk_valid && !yaffs_skip_nand_verification(dev)) { + struct yaffs_ext_tags tags; + struct yaffs_obj_hdr *oh; + u8 *buffer = yaffs_get_temp_buffer(dev); + + oh = (struct yaffs_obj_hdr *)buffer; + + yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, buffer, &tags); + + yaffs_verify_oh(obj, oh, &tags, 1); + + yaffs_release_temp_buffer(dev, buffer); + } + + /* Verify it has a parent */ + if (obj && !obj->fake && (!obj->parent || obj->parent->my_dev != dev)) { + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d has parent pointer %p which does not look like an object", + obj->obj_id, obj->parent); + } + + /* Verify parent is a directory */ + if (obj->parent && + obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d's parent is not a directory (type %d)", + obj->obj_id, obj->parent->variant_type); + } + + switch (obj->variant_type) { + case YAFFS_OBJECT_TYPE_FILE: + yaffs_verify_file(obj); + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + yaffs_verify_symlink(obj); + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + yaffs_verify_dir(obj); + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + yaffs_verify_link(obj); + break; + case YAFFS_OBJECT_TYPE_SPECIAL: + yaffs_verify_special(obj); + break; + case YAFFS_OBJECT_TYPE_UNKNOWN: + default: + yaffs_trace(YAFFS_TRACE_VERIFY, + "Obj %d has illegaltype %d", + obj->obj_id, obj->variant_type); + break; + } +} + +void yaffs_verify_objects(struct yaffs_dev *dev) +{ + struct yaffs_obj *obj; + int i; + struct list_head *lh; + + if (yaffs_skip_verification(dev)) + return; + + /* Iterate through the objects in each hash entry */ + + for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { + list_for_each(lh, &dev->obj_bucket[i].list) { + obj = list_entry(lh, struct yaffs_obj, hash_link); + yaffs_verify_obj(obj); + } + } +} + +void yaffs_verify_obj_in_dir(struct yaffs_obj *obj) +{ + struct list_head *lh; + struct yaffs_obj *list_obj; + int count = 0; + + if (!obj) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "No object to verify"); + BUG(); + return; + } + + if (yaffs_skip_verification(obj->my_dev)) + return; + + if (!obj->parent) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "Object does not have parent"); + BUG(); + return; + } + + if (obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "Parent is not directory"); + BUG(); + } + + /* Iterate through the objects in each hash entry */ + + list_for_each(lh, &obj->parent->variant.dir_variant.children) { + list_obj = list_entry(lh, struct yaffs_obj, siblings); + yaffs_verify_obj(list_obj); + if (obj == list_obj) + count++; + } + + if (count != 1) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "Object in directory %d times", + count); + BUG(); + } +} + +void yaffs_verify_dir(struct yaffs_obj *directory) +{ + struct list_head *lh; + struct yaffs_obj *list_obj; + + if (!directory) { + BUG(); + return; + } + + if (yaffs_skip_full_verification(directory->my_dev)) + return; + + if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "Directory has wrong type: %d", + directory->variant_type); + BUG(); + } + + /* Iterate through the objects in each hash entry */ + + list_for_each(lh, &directory->variant.dir_variant.children) { + list_obj = list_entry(lh, struct yaffs_obj, siblings); + if (list_obj->parent != directory) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "Object in directory list has wrong parent %p", + list_obj->parent); + BUG(); + } + yaffs_verify_obj_in_dir(list_obj); + } +} + +static int yaffs_free_verification_failures; + +void yaffs_verify_free_chunks(struct yaffs_dev *dev) +{ + int counted; + int difference; + + if (yaffs_skip_verification(dev)) + return; + + counted = yaffs_count_free_chunks(dev); + + difference = dev->n_free_chunks - counted; + + if (difference) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "Freechunks verification failure %d %d %d", + dev->n_free_chunks, counted, difference); + yaffs_free_verification_failures++; + } +} + +int yaffs_verify_file_sane(struct yaffs_obj *in) +{ + (void) in; + return YAFFS_OK; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_verify.h b/target/linux/generic/files/fs/yaffs2/yaffs_verify.h new file mode 100644 index 0000000..4f4af8d --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_verify.h @@ -0,0 +1,43 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_VERIFY_H__ +#define __YAFFS_VERIFY_H__ + +#include "yaffs_guts.h" + +void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, + int n); +void yaffs_verify_collected_blk(struct yaffs_dev *dev, + struct yaffs_block_info *bi, int n); +void yaffs_verify_blocks(struct yaffs_dev *dev); + +void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, + struct yaffs_ext_tags *tags, int parent_check); +void yaffs_verify_file(struct yaffs_obj *obj); +void yaffs_verify_link(struct yaffs_obj *obj); +void yaffs_verify_symlink(struct yaffs_obj *obj); +void yaffs_verify_special(struct yaffs_obj *obj); +void yaffs_verify_obj(struct yaffs_obj *obj); +void yaffs_verify_objects(struct yaffs_dev *dev); +void yaffs_verify_obj_in_dir(struct yaffs_obj *obj); +void yaffs_verify_dir(struct yaffs_obj *directory); +void yaffs_verify_free_chunks(struct yaffs_dev *dev); + +int yaffs_verify_file_sane(struct yaffs_obj *obj); + +int yaffs_skip_verification(struct yaffs_dev *dev); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_vfs.c b/target/linux/generic/files/fs/yaffs2/yaffs_vfs.c new file mode 100644 index 0000000..864a5dc --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_vfs.c @@ -0,0 +1,3665 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * Acknowledgements: + * Luc van OostenRyck for numerous patches. + * Nick Bane for numerous patches. + * Nick Bane for 2.5/2.6 integration. + * Andras Toth for mknod rdev issue. + * Michael Fischer for finding the problem with inode inconsistency. + * Some code bodily lifted from JFFS + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * + * This is the file system front-end to YAFFS that hooks it up to + * the VFS. + * + * Special notes: + * >> 2.4: sb->u.generic_sbp points to the struct yaffs_dev associated with + * this superblock + * >> 2.6: sb->s_fs_info points to the struct yaffs_dev associated with this + * superblock + * >> inode->u.generic_ip points to the associated struct yaffs_obj. + */ + +/* + * There are two variants of the VFS glue code. This variant should compile + * for any version of Linux. + */ +#include + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 10)) +#define YAFFS_COMPILE_BACKGROUND +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 23)) +#define YAFFS_COMPILE_FREEZER +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) +#define YAFFS_COMPILE_EXPORTFS +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) +#define YAFFS_USE_SETATTR_COPY +#define YAFFS_USE_TRUNCATE_SETSIZE +#endif +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) +#define YAFFS_HAS_EVICT_INODE +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13)) +#define YAFFS_NEW_FOLLOW_LINK 1 +#else +#define YAFFS_NEW_FOLLOW_LINK 0 +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) +#define YAFFS_HAS_WRITE_SUPER +#endif + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) +#include +#endif + +#include +#include +#include +#include +#include +#include +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)) +#include +#endif +#include +#include +#include +#include +#include + +#if (YAFFS_NEW_FOLLOW_LINK == 1) +#include +#endif + +#ifdef YAFFS_COMPILE_EXPORTFS +#include +#endif + +#ifdef YAFFS_COMPILE_BACKGROUND +#include +#include +#endif +#ifdef YAFFS_COMPILE_FREEZER +#include +#endif + +#include + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) + +#include + +#define UnlockPage(p) unlock_page(p) +#define Page_Uptodate(page) test_bit(PG_uptodate, &(page)->flags) + +/* FIXME: use sb->s_id instead ? */ +#define yaffs_devname(sb, buf) bdevname(sb->s_bdev, buf) + +#else + +#include +#define BDEVNAME_SIZE 0 +#define yaffs_devname(sb, buf) kdevname(sb->s_dev) + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) +/* added NCB 26/5/2006 for 2.4.25-vrs2-tcl1 kernel */ +#define __user +#endif + +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) +#define YPROC_ROOT (&proc_root) +#else +#define YPROC_ROOT NULL +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) +#define Y_INIT_TIMER(a) init_timer(a) +#else +#define Y_INIT_TIMER(a) init_timer_on_stack(a) +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 27)) +#define YAFFS_USE_WRITE_BEGIN_END 1 +#else +#define YAFFS_USE_WRITE_BEGIN_END 0 +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) +#define YAFFS_SUPER_HAS_DIRTY +#endif + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) +#define set_nlink(inode, count) do { (inode)->i_nlink = (count); } while(0) +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 28)) +static uint32_t YCALCBLOCKS(uint64_t partition_size, uint32_t block_size) +{ + uint64_t result = partition_size; + do_div(result, block_size); + return (uint32_t) result; +} +#else +#define YCALCBLOCKS(s, b) ((s)/(b)) +#endif + +#include +#include + +#include "yportenv.h" +#include "yaffs_trace.h" +#include "yaffs_guts.h" +#include "yaffs_attribs.h" + +#include "yaffs_linux.h" + +#include "yaffs_mtdif.h" +#include "yaffs_packedtags2.h" +#include "yaffs_getblockinfo.h" + +unsigned int yaffs_trace_mask = + YAFFS_TRACE_BAD_BLOCKS | + YAFFS_TRACE_ALWAYS | + 0; + +unsigned int yaffs_wr_attempts = YAFFS_WR_ATTEMPTS; +unsigned int yaffs_auto_checkpoint = 1; +unsigned int yaffs_gc_control = 1; +unsigned int yaffs_bg_enable = 1; +unsigned int yaffs_auto_select = 1; +/* Module Parameters */ +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +module_param(yaffs_trace_mask, uint, 0644); +module_param(yaffs_wr_attempts, uint, 0644); +module_param(yaffs_auto_checkpoint, uint, 0644); +module_param(yaffs_gc_control, uint, 0644); +module_param(yaffs_bg_enable, uint, 0644); +#else +MODULE_PARM(yaffs_trace_mask, "i"); +MODULE_PARM(yaffs_wr_attempts, "i"); +MODULE_PARM(yaffs_auto_checkpoint, "i"); +MODULE_PARM(yaffs_gc_control, "i"); +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) +/* use iget and read_inode */ +#define Y_IGET(sb, inum) iget((sb), (inum)) + +#else +/* Call local equivalent */ +#define YAFFS_USE_OWN_IGET +#define Y_IGET(sb, inum) yaffs_iget((sb), (inum)) + +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) +#define yaffs_inode_to_obj_lv(iptr) ((iptr)->i_private) +#else +#define yaffs_inode_to_obj_lv(iptr) ((iptr)->u.generic_ip) +#endif + +#define yaffs_inode_to_obj(iptr) \ + ((struct yaffs_obj *)(yaffs_inode_to_obj_lv(iptr))) +#define yaffs_dentry_to_obj(dptr) yaffs_inode_to_obj((dptr)->d_inode) + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +#define yaffs_super_to_dev(sb) ((struct yaffs_dev *)sb->s_fs_info) +#else +#define yaffs_super_to_dev(sb) ((struct yaffs_dev *)sb->u.generic_sbp) +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) +#define Y_CLEAR_INODE(i) clear_inode(i) +#else +#define Y_CLEAR_INODE(i) end_writeback(i) +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0)) +#define YAFFS_USE_DIR_ITERATE +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,12,0)) +#define YAFFS_NEW_PROCFS +#include +#endif + + +#define update_dir_time(dir) do {\ + (dir)->i_ctime = (dir)->i_mtime = CURRENT_TIME; \ + } while (0) + +static void yaffs_fill_inode_from_obj(struct inode *inode, + struct yaffs_obj *obj); + + +static void yaffs_gross_lock(struct yaffs_dev *dev) +{ + yaffs_trace(YAFFS_TRACE_LOCK, "yaffs locking %p", current); + mutex_lock(&(yaffs_dev_to_lc(dev)->gross_lock)); + yaffs_trace(YAFFS_TRACE_LOCK, "yaffs locked %p", current); +} + +static void yaffs_gross_unlock(struct yaffs_dev *dev) +{ + yaffs_trace(YAFFS_TRACE_LOCK, "yaffs unlocking %p", current); + mutex_unlock(&(yaffs_dev_to_lc(dev)->gross_lock)); +} + + +static int yaffs_readpage_nolock(struct file *f, struct page *pg) +{ + /* Lifted from jffs2 */ + + struct yaffs_obj *obj; + unsigned char *pg_buf; + int ret; + loff_t pos = ((loff_t) pg->index) << PAGE_CACHE_SHIFT; + struct yaffs_dev *dev; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readpage_nolock at %lld, size %08x", + (long long)pos, + (unsigned)PAGE_CACHE_SIZE); + + obj = yaffs_dentry_to_obj(f->f_dentry); + + dev = obj->my_dev; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) + BUG_ON(!PageLocked(pg)); +#else + if (!PageLocked(pg)) + PAGE_BUG(pg); +#endif + + pg_buf = kmap(pg); + /* FIXME: Can kmap fail? */ + + yaffs_gross_lock(dev); + + ret = yaffs_file_rd(obj, pg_buf, pos, PAGE_CACHE_SIZE); + + yaffs_gross_unlock(dev); + + if (ret >= 0) + ret = 0; + + if (ret) { + ClearPageUptodate(pg); + SetPageError(pg); + } else { + SetPageUptodate(pg); + ClearPageError(pg); + } + + flush_dcache_page(pg); + kunmap(pg); + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_readpage_nolock done"); + return ret; +} + +static int yaffs_readpage_unlock(struct file *f, struct page *pg) +{ + int ret = yaffs_readpage_nolock(f, pg); + UnlockPage(pg); + return ret; +} + +static int yaffs_readpage(struct file *f, struct page *pg) +{ + int ret; + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_readpage"); + ret = yaffs_readpage_unlock(f, pg); + yaffs_trace(YAFFS_TRACE_OS, "yaffs_readpage done"); + return ret; +} + + +static void yaffs_set_super_dirty_val(struct yaffs_dev *dev, int val) +{ + struct yaffs_linux_context *lc = yaffs_dev_to_lc(dev); + + if (lc) + lc->dirty = val; + +# ifdef YAFFS_SUPER_HAS_DIRTY + { + struct super_block *sb = lc->super; + + if (sb) + sb->s_dirt = val; + } +#endif + +} + +static void yaffs_set_super_dirty(struct yaffs_dev *dev) +{ + yaffs_set_super_dirty_val(dev, 1); +} + +static void yaffs_clear_super_dirty(struct yaffs_dev *dev) +{ + yaffs_set_super_dirty_val(dev, 0); +} + +static int yaffs_check_super_dirty(struct yaffs_dev *dev) +{ + struct yaffs_linux_context *lc = yaffs_dev_to_lc(dev); + + if (lc && lc->dirty) + return 1; + +# ifdef YAFFS_SUPER_HAS_DIRTY + { + struct super_block *sb = lc->super; + + if (sb && sb->s_dirt) + return 1; + } +#endif + return 0; + +} + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +static int yaffs_writepage(struct page *page, struct writeback_control *wbc) +#else +static int yaffs_writepage(struct page *page) +#endif +{ + struct yaffs_dev *dev; + struct address_space *mapping = page->mapping; + struct inode *inode; + unsigned long end_index; + char *buffer; + struct yaffs_obj *obj; + int n_written = 0; + unsigned n_bytes; + loff_t i_size; + + if (!mapping) + BUG(); + inode = mapping->host; + if (!inode) + BUG(); + i_size = i_size_read(inode); + + end_index = i_size >> PAGE_CACHE_SHIFT; + + if (page->index < end_index) + n_bytes = PAGE_CACHE_SIZE; + else { + n_bytes = i_size & (PAGE_CACHE_SIZE - 1); + + if (page->index > end_index || !n_bytes) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_writepage at %lld, inode size = %lld!!", + ((loff_t)page->index) << PAGE_CACHE_SHIFT, + inode->i_size); + yaffs_trace(YAFFS_TRACE_OS, + " -> don't care!!"); + + zero_user_segment(page, 0, PAGE_CACHE_SIZE); + set_page_writeback(page); + unlock_page(page); + end_page_writeback(page); + return 0; + } + } + + if (n_bytes != PAGE_CACHE_SIZE) + zero_user_segment(page, n_bytes, PAGE_CACHE_SIZE); + + get_page(page); + + buffer = kmap(page); + + obj = yaffs_inode_to_obj(inode); + dev = obj->my_dev; + yaffs_gross_lock(dev); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_writepage at %lld, size %08x", + ((loff_t)page->index) << PAGE_CACHE_SHIFT, n_bytes); + yaffs_trace(YAFFS_TRACE_OS, + "writepag0: obj = %lld, ino = %lld", + obj->variant.file_variant.file_size, inode->i_size); + + n_written = yaffs_wr_file(obj, buffer, + ((loff_t)page->index) << PAGE_CACHE_SHIFT, n_bytes, 0); + + yaffs_set_super_dirty(dev); + + yaffs_trace(YAFFS_TRACE_OS, + "writepag1: obj = %lld, ino = %lld", + obj->variant.file_variant.file_size, inode->i_size); + + yaffs_gross_unlock(dev); + + kunmap(page); + set_page_writeback(page); + unlock_page(page); + end_page_writeback(page); + put_page(page); + + return (n_written == n_bytes) ? 0 : -ENOSPC; +} + +/* Space holding and freeing is done to ensure we have space available for write_begin/end */ +/* For now we just assume few parallel writes and check against a small number. */ +/* Todo: need to do this with a counter to handle parallel reads better */ + +static ssize_t yaffs_hold_space(struct file *f) +{ + struct yaffs_obj *obj; + struct yaffs_dev *dev; + + int n_free_chunks; + + obj = yaffs_dentry_to_obj(f->f_dentry); + + dev = obj->my_dev; + + yaffs_gross_lock(dev); + + n_free_chunks = yaffs_get_n_free_chunks(dev); + + yaffs_gross_unlock(dev); + + return (n_free_chunks > 20) ? 1 : 0; +} + +static void yaffs_release_space(struct file *f) +{ + struct yaffs_obj *obj; + struct yaffs_dev *dev; + + obj = yaffs_dentry_to_obj(f->f_dentry); + + dev = obj->my_dev; + + yaffs_gross_lock(dev); + + yaffs_gross_unlock(dev); +} + +#if (YAFFS_USE_WRITE_BEGIN_END > 0) +static int yaffs_write_begin(struct file *filp, struct address_space *mapping, + loff_t pos, unsigned len, unsigned flags, + struct page **pagep, void **fsdata) +{ + struct page *pg = NULL; + pgoff_t index = pos >> PAGE_CACHE_SHIFT; + + int ret = 0; + int space_held = 0; + + /* Get a page */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28) + pg = grab_cache_page_write_begin(mapping, index, flags); +#else + pg = __grab_cache_page(mapping, index); +#endif + + *pagep = pg; + if (!pg) { + ret = -ENOMEM; + goto out; + } + yaffs_trace(YAFFS_TRACE_OS, + "start yaffs_write_begin index %d(%x) uptodate %d", + (int)index, (int)index, Page_Uptodate(pg) ? 1 : 0); + + /* Get fs space */ + space_held = yaffs_hold_space(filp); + + if (!space_held) { + ret = -ENOSPC; + goto out; + } + + /* Update page if required */ + + if (!Page_Uptodate(pg)) + ret = yaffs_readpage_nolock(filp, pg); + + if (ret) + goto out; + + /* Happy path return */ + yaffs_trace(YAFFS_TRACE_OS, "end yaffs_write_begin - ok"); + + return 0; + +out: + yaffs_trace(YAFFS_TRACE_OS, + "end yaffs_write_begin fail returning %d", ret); + if (space_held) + yaffs_release_space(filp); + if (pg) { + unlock_page(pg); + page_cache_release(pg); + } + return ret; +} + +#else + +static int yaffs_prepare_write(struct file *f, struct page *pg, + unsigned offset, unsigned to) +{ + yaffs_trace(YAFFS_TRACE_OS, "yaffs_prepair_write"); + + if (!Page_Uptodate(pg)) + return yaffs_readpage_nolock(f, pg); + return 0; +} +#endif + + +static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n, + loff_t * pos) +{ + struct yaffs_obj *obj; + int n_written; + loff_t ipos; + struct inode *inode; + struct yaffs_dev *dev; + + obj = yaffs_dentry_to_obj(f->f_dentry); + + if (!obj) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_file_write: hey obj is null!"); + return -EINVAL; + } + + dev = obj->my_dev; + + yaffs_gross_lock(dev); + + inode = f->f_dentry->d_inode; + + if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) + ipos = inode->i_size; + else + ipos = *pos; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_file_write about to write writing %u(%x) bytes to object %d at %lld", + (unsigned)n, (unsigned)n, obj->obj_id, ipos); + + n_written = yaffs_wr_file(obj, buf, ipos, n, 0); + + yaffs_set_super_dirty(dev); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_file_write: %d(%x) bytes written", + (unsigned)n, (unsigned)n); + + if (n_written > 0) { + ipos += n_written; + *pos = ipos; + if (ipos > inode->i_size) { + inode->i_size = ipos; + inode->i_blocks = (ipos + 511) >> 9; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_file_write size updated to %lld bytes, %d blocks", + ipos, (int)(inode->i_blocks)); + } + + } + yaffs_gross_unlock(dev); + return (n_written == 0) && (n > 0) ? -ENOSPC : n_written; +} + + +#if (YAFFS_USE_WRITE_BEGIN_END > 0) +static int yaffs_write_end(struct file *filp, struct address_space *mapping, + loff_t pos, unsigned len, unsigned copied, + struct page *pg, void *fsdadata) +{ + int ret = 0; + void *addr, *kva; + uint32_t offset_into_page = pos & (PAGE_CACHE_SIZE - 1); + + kva = kmap(pg); + addr = kva + offset_into_page; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_write_end addr %p pos %lld n_bytes %d", + addr, pos, copied); + + ret = yaffs_file_write(filp, addr, copied, &pos); + + if (ret != copied) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_write_end not same size ret %d copied %d", + ret, copied); + SetPageError(pg); + } + + kunmap(pg); + + yaffs_release_space(filp); + unlock_page(pg); + page_cache_release(pg); + return ret; +} +#else + +static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset, + unsigned to) +{ + void *addr, *kva; + + loff_t pos = (((loff_t) pg->index) << PAGE_CACHE_SHIFT) + offset; + int n_bytes = to - offset; + int n_written; + + kva = kmap(pg); + addr = kva + offset; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_commit_write addr %p pos %lld n_bytes %d", + addr, pos, n_bytes); + + n_written = yaffs_file_write(f, addr, n_bytes, &pos); + + if (n_written != n_bytes) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_commit_write not same size n_written %d n_bytes %d", + n_written, n_bytes); + SetPageError(pg); + } + kunmap(pg); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_commit_write returning %d", + n_written == n_bytes ? 0 : n_written); + + return n_written == n_bytes ? 0 : n_written; +} +#endif + +static struct address_space_operations yaffs_file_address_operations = { + .readpage = yaffs_readpage, + .writepage = yaffs_writepage, +#if (YAFFS_USE_WRITE_BEGIN_END > 0) + .write_begin = yaffs_write_begin, + .write_end = yaffs_write_end, +#else + .prepare_write = yaffs_prepare_write, + .commit_write = yaffs_commit_write, +#endif +}; + + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) +static int yaffs_file_flush(struct file *file, fl_owner_t id) +#else +static int yaffs_file_flush(struct file *file) +#endif +{ + struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_dentry); + + struct yaffs_dev *dev = obj->my_dev; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_file_flush object %d (%s)", + obj->obj_id, + obj->dirty ? "dirty" : "clean"); + + yaffs_gross_lock(dev); + + yaffs_flush_file(obj, 1, 0, 0); + + yaffs_gross_unlock(dev); + + return 0; +} + + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) +static int yaffs_sync_object(struct file *file, loff_t start, loff_t end, int datasync) +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) +static int yaffs_sync_object(struct file *file, int datasync) +#else +static int yaffs_sync_object(struct file *file, struct dentry *dentry, + int datasync) +#endif +{ + struct yaffs_obj *obj; + struct yaffs_dev *dev; +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) + struct dentry *dentry = file->f_path.dentry; +#endif + + obj = yaffs_dentry_to_obj(dentry); + + dev = obj->my_dev; + + yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, + "yaffs_sync_object"); + yaffs_gross_lock(dev); + yaffs_flush_file(obj, 1, datasync, 0); + yaffs_gross_unlock(dev); + return 0; +} + + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) +static const struct file_operations yaffs_file_operations = { + .read = do_sync_read, + .write = do_sync_write, + .aio_read = generic_file_aio_read, + .aio_write = generic_file_aio_write, + .mmap = generic_file_mmap, + .flush = yaffs_file_flush, + .fsync = yaffs_sync_object, + .splice_read = generic_file_splice_read, + .splice_write = generic_file_splice_write, + .llseek = generic_file_llseek, +}; + +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) + +static const struct file_operations yaffs_file_operations = { + .read = do_sync_read, + .write = do_sync_write, + .aio_read = generic_file_aio_read, + .aio_write = generic_file_aio_write, + .mmap = generic_file_mmap, + .flush = yaffs_file_flush, + .fsync = yaffs_sync_object, + .sendfile = generic_file_sendfile, +}; + +#else + +static const struct file_operations yaffs_file_operations = { + .read = generic_file_read, + .write = generic_file_write, + .mmap = generic_file_mmap, + .flush = yaffs_file_flush, + .fsync = yaffs_sync_object, +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) + .sendfile = generic_file_sendfile, +#endif +}; +#endif + + + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) +static void zero_user_segment(struct page *page, unsigned start, unsigned end) +{ + void *kaddr = kmap_atomic(page, KM_USER0); + memset(kaddr + start, 0, end - start); + kunmap_atomic(kaddr, KM_USER0); + flush_dcache_page(page); +} +#endif + + +static int yaffs_vfs_setsize(struct inode *inode, loff_t newsize) +{ +#ifdef YAFFS_USE_TRUNCATE_SETSIZE + truncate_setsize(inode, newsize); + return 0; +#else + truncate_inode_pages(&inode->i_data, newsize); + return 0; +#endif + +} + + +static int yaffs_vfs_setattr(struct inode *inode, struct iattr *attr) +{ +#ifdef YAFFS_USE_SETATTR_COPY + setattr_copy(inode, attr); + return 0; +#else + return inode_setattr(inode, attr); +#endif + +} + +static int yaffs_setattr(struct dentry *dentry, struct iattr *attr) +{ + struct inode *inode = dentry->d_inode; + int error = 0; + struct yaffs_dev *dev; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_setattr of object %d", + yaffs_inode_to_obj(inode)->obj_id); +#if 0 + /* Fail if a requested resize >= 2GB */ + if (attr->ia_valid & ATTR_SIZE && (attr->ia_size >> 31)) + error = -EINVAL; +#endif + + if (error == 0) + error = inode_change_ok(inode, attr); + if (error == 0) { + int result; + if (!error) { + error = yaffs_vfs_setattr(inode, attr); + yaffs_trace(YAFFS_TRACE_OS, "inode_setattr called"); + if (attr->ia_valid & ATTR_SIZE) { + yaffs_vfs_setsize(inode, attr->ia_size); + inode->i_blocks = (inode->i_size + 511) >> 9; + } + } + dev = yaffs_inode_to_obj(inode)->my_dev; + if (attr->ia_valid & ATTR_SIZE) { + yaffs_trace(YAFFS_TRACE_OS, + "resize to %d(%x)", + (int)(attr->ia_size), + (int)(attr->ia_size)); + } + yaffs_gross_lock(dev); + result = yaffs_set_attribs(yaffs_inode_to_obj(inode), attr); + if (result == YAFFS_OK) { + error = 0; + } else { + error = -EPERM; + } + yaffs_gross_unlock(dev); + + } + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_setattr done returning %d", error); + + return error; +} + +static int yaffs_setxattr(struct dentry *dentry, const char *name, + const void *value, size_t size, int flags) +{ + struct inode *inode = dentry->d_inode; + int error = 0; + struct yaffs_dev *dev; + struct yaffs_obj *obj = yaffs_inode_to_obj(inode); + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_setxattr of object %d", obj->obj_id); + + if (error == 0) { + int result; + dev = obj->my_dev; + yaffs_gross_lock(dev); + result = yaffs_set_xattrib(obj, name, value, size, flags); + if (result == YAFFS_OK) + error = 0; + else if (result < 0) + error = result; + yaffs_gross_unlock(dev); + + } + yaffs_trace(YAFFS_TRACE_OS, "yaffs_setxattr done returning %d", error); + + return error; +} + +static ssize_t yaffs_getxattr(struct dentry * dentry, const char *name, + void *buff, size_t size) +{ + struct inode *inode = dentry->d_inode; + int error = 0; + struct yaffs_dev *dev; + struct yaffs_obj *obj = yaffs_inode_to_obj(inode); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_getxattr \"%s\" from object %d", + name, obj->obj_id); + + if (error == 0) { + dev = obj->my_dev; + yaffs_gross_lock(dev); + error = yaffs_get_xattrib(obj, name, buff, size); + yaffs_gross_unlock(dev); + + } + yaffs_trace(YAFFS_TRACE_OS, "yaffs_getxattr done returning %d", error); + + return error; +} + +static int yaffs_removexattr(struct dentry *dentry, const char *name) +{ + struct inode *inode = dentry->d_inode; + int error = 0; + struct yaffs_dev *dev; + struct yaffs_obj *obj = yaffs_inode_to_obj(inode); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_removexattr of object %d", obj->obj_id); + + if (error == 0) { + int result; + dev = obj->my_dev; + yaffs_gross_lock(dev); + result = yaffs_remove_xattrib(obj, name); + if (result == YAFFS_OK) + error = 0; + else if (result < 0) + error = result; + yaffs_gross_unlock(dev); + + } + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_removexattr done returning %d", error); + + return error; +} + +static ssize_t yaffs_listxattr(struct dentry * dentry, char *buff, size_t size) +{ + struct inode *inode = dentry->d_inode; + int error = 0; + struct yaffs_dev *dev; + struct yaffs_obj *obj = yaffs_inode_to_obj(inode); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_listxattr of object %d", obj->obj_id); + + if (error == 0) { + dev = obj->my_dev; + yaffs_gross_lock(dev); + error = yaffs_list_xattrib(obj, buff, size); + yaffs_gross_unlock(dev); + + } + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_listxattr done returning %d", error); + + return error; +} + + +static const struct inode_operations yaffs_file_inode_operations = { + .setattr = yaffs_setattr, + .setxattr = yaffs_setxattr, + .getxattr = yaffs_getxattr, + .listxattr = yaffs_listxattr, + .removexattr = yaffs_removexattr, +}; + + +static int yaffs_readlink(struct dentry *dentry, char __user * buffer, + int buflen) +{ + unsigned char *alias; + int ret; + + struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; + + yaffs_gross_lock(dev); + + alias = yaffs_get_symlink_alias(yaffs_dentry_to_obj(dentry)); + + yaffs_gross_unlock(dev); + + if (!alias) + return -ENOMEM; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0) + ret = vfs_readlink(dentry, buffer, buflen, alias); +#else + ret = readlink_copy(buffer, buflen, alias); +#endif + kfree(alias); + return ret; +} + +#if (YAFFS_NEW_FOLLOW_LINK == 1) +static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) +{ + void *ret; +#else +static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) +{ + int ret +#endif + unsigned char *alias; + int ret_int = 0; + struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; + + yaffs_gross_lock(dev); + + alias = yaffs_get_symlink_alias(yaffs_dentry_to_obj(dentry)); + yaffs_gross_unlock(dev); + + if (!alias) { + ret_int = -ENOMEM; + goto out; + } +#if (YAFFS_NEW_FOLLOW_LINK == 1) + nd_set_link(nd, alias); + ret = alias; +out: + if (ret_int) + ret = ERR_PTR(ret_int); + return ret; +#else + ret = vfs_follow_link(nd, alias); + kfree(alias); +out: + if (ret_int) + ret = ret_int; + return ret; +#endif +} + + +#ifdef YAFFS_HAS_PUT_INODE + +/* For now put inode is just for debugging + * Put inode is called when the inode **structure** is put. + */ +static void yaffs_put_inode(struct inode *inode) +{ + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_put_inode: ino %d, count %d"), + (int)inode->i_ino, atomic_read(&inode->i_count); + +} +#endif + +#if (YAFFS_NEW_FOLLOW_LINK == 1) +void yaffs_put_link(struct dentry *dentry, struct nameidata *nd, void *alias) +{ + kfree(alias); +} +#endif + +static const struct inode_operations yaffs_symlink_inode_operations = { + .readlink = yaffs_readlink, + .follow_link = yaffs_follow_link, +#if (YAFFS_NEW_FOLLOW_LINK == 1) + .put_link = yaffs_put_link, +#endif + .setattr = yaffs_setattr, + .setxattr = yaffs_setxattr, + .getxattr = yaffs_getxattr, + .listxattr = yaffs_listxattr, + .removexattr = yaffs_removexattr, +}; + +#ifdef YAFFS_USE_OWN_IGET + +static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino) +{ + struct inode *inode; + struct yaffs_obj *obj; + struct yaffs_dev *dev = yaffs_super_to_dev(sb); + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_iget for %lu", ino); + + inode = iget_locked(sb, ino); + if (!inode) + return ERR_PTR(-ENOMEM); + if (!(inode->i_state & I_NEW)) + return inode; + + /* NB This is called as a side effect of other functions, but + * we had to release the lock to prevent deadlocks, so + * need to lock again. + */ + + yaffs_gross_lock(dev); + + obj = yaffs_find_by_number(dev, inode->i_ino); + + yaffs_fill_inode_from_obj(inode, obj); + + yaffs_gross_unlock(dev); + + unlock_new_inode(inode); + return inode; +} + +#else + +static void yaffs_read_inode(struct inode *inode) +{ + /* NB This is called as a side effect of other functions, but + * we had to release the lock to prevent deadlocks, so + * need to lock again. + */ + + struct yaffs_obj *obj; + struct yaffs_dev *dev = yaffs_super_to_dev(inode->i_sb); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_read_inode for %d", (int)inode->i_ino); + + if (current != yaffs_dev_to_lc(dev)->readdir_process) + yaffs_gross_lock(dev); + + obj = yaffs_find_by_number(dev, inode->i_ino); + + yaffs_fill_inode_from_obj(inode, obj); + + if (current != yaffs_dev_to_lc(dev)->readdir_process) + yaffs_gross_unlock(dev); +} + +#endif + + + +struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev, + struct yaffs_obj *obj) +{ + struct inode *inode; + + if (!sb) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_get_inode for NULL super_block!!"); + return NULL; + + } + + if (!obj) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_get_inode for NULL object!!"); + return NULL; + + } + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_get_inode for object %d", obj->obj_id); + + inode = Y_IGET(sb, obj->obj_id); + if (IS_ERR(inode)) + return NULL; + + /* NB Side effect: iget calls back to yaffs_read_inode(). */ + /* iget also increments the inode's i_count */ + /* NB You can't be holding gross_lock or deadlock will happen! */ + + return inode; +} + + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) +#define YCRED(x) x +#else +#define YCRED(x) (x->cred) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) +#define YPROC_uid(p) (YCRED(p)->fsuid) +#define YPROC_gid(p) (YCRED(p)->fsgid) +#define EXTRACT_gid(x) x +#define EXTRACT_uid(x) x +#define MAKE_gid(x) x +#define MAKE_uid(x) x +#else +#define YPROC_uid(p) from_kuid(&init_user_ns, YCRED(p)->fsuid) +#define YPROC_gid(p) from_kgid(&init_user_ns, YCRED(p)->fsgid) +#define EXTRACT_gid(x) from_kgid(&init_user_ns, x) +#define EXTRACT_uid(x) from_kuid(&init_user_ns, x) +#define MAKE_gid(x) make_kgid(&init_user_ns, x) +#define MAKE_uid(x) make_kuid(&init_user_ns, x) +#endif + + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) +static int yaffs_mknod(struct inode *dir, struct dentry *dentry, umode_t mode, + dev_t rdev) +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, + dev_t rdev) +#else +static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, + int rdev) +#endif +{ + struct inode *inode; + + struct yaffs_obj *obj = NULL; + struct yaffs_dev *dev; + + struct yaffs_obj *parent = yaffs_inode_to_obj(dir); + + int error = -ENOSPC; + uid_t uid = YPROC_uid(current); + gid_t gid = + (dir->i_mode & S_ISGID) ? EXTRACT_gid(dir->i_gid) : YPROC_gid(current); + + if ((dir->i_mode & S_ISGID) && S_ISDIR(mode)) + mode |= S_ISGID; + + if (parent) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_mknod: parent object %d type %d", + parent->obj_id, parent->variant_type); + } else { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_mknod: could not get parent object"); + return -EPERM; + } + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_mknod: making oject for %s, mode %x dev %x", + dentry->d_name.name, mode, rdev); + + dev = parent->my_dev; + + yaffs_gross_lock(dev); + + switch (mode & S_IFMT) { + default: + /* Special (socket, fifo, device...) */ + yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod: making special"); +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) + obj = + yaffs_create_special(parent, dentry->d_name.name, mode, uid, + gid, old_encode_dev(rdev)); +#else + obj = + yaffs_create_special(parent, dentry->d_name.name, mode, uid, + gid, rdev); +#endif + break; + case S_IFREG: /* file */ + yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod: making file"); + obj = yaffs_create_file(parent, dentry->d_name.name, mode, uid, + gid); + break; + case S_IFDIR: /* directory */ + yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod: making directory"); + obj = yaffs_create_dir(parent, dentry->d_name.name, mode, + uid, gid); + break; + case S_IFLNK: /* symlink */ + yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod: making symlink"); + obj = NULL; /* Do we ever get here? */ + break; + } + + /* Can not call yaffs_get_inode() with gross lock held */ + yaffs_gross_unlock(dev); + + if (obj) { + inode = yaffs_get_inode(dir->i_sb, mode, rdev, obj); + d_instantiate(dentry, inode); + update_dir_time(dir); + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_mknod created object %d count = %d", + obj->obj_id, atomic_read(&inode->i_count)); + error = 0; + yaffs_fill_inode_from_obj(dir, parent); + } else { + yaffs_trace(YAFFS_TRACE_OS, "yaffs_mknod failed making object"); + error = -ENOMEM; + } + + return error; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) +static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) +#else +static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode) +#endif +{ + int ret_val; + yaffs_trace(YAFFS_TRACE_OS, "yaffs_mkdir"); + ret_val = yaffs_mknod(dir, dentry, mode | S_IFDIR, 0); + return ret_val; +} + + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +static int yaffs_create(struct inode *dir, struct dentry *dentry, umode_t mode, + bool dummy) +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) +static int yaffs_create(struct inode *dir, struct dentry *dentry, umode_t mode, + struct nameidata *n) +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode, + struct nameidata *n) +#else +static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode) +#endif +{ + yaffs_trace(YAFFS_TRACE_OS, "yaffs_create"); + return yaffs_mknod(dir, dentry, mode | S_IFREG, 0); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, + unsigned int dummy) +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, + struct nameidata *n) +#else +static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry) +#endif +{ + struct yaffs_obj *obj; + struct inode *inode = NULL; /* NCB 2.5/2.6 needs NULL here */ + + struct yaffs_dev *dev = yaffs_inode_to_obj(dir)->my_dev; + + if (current != yaffs_dev_to_lc(dev)->readdir_process) + yaffs_gross_lock(dev); + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_lookup for %d:%s", + yaffs_inode_to_obj(dir)->obj_id, dentry->d_name.name); + + obj = yaffs_find_by_name(yaffs_inode_to_obj(dir), dentry->d_name.name); + + obj = yaffs_get_equivalent_obj(obj); /* in case it was a hardlink */ + + /* Can't hold gross lock when calling yaffs_get_inode() */ + if (current != yaffs_dev_to_lc(dev)->readdir_process) + yaffs_gross_unlock(dev); + + if (obj) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_lookup found %d", obj->obj_id); + + inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); + } else { + yaffs_trace(YAFFS_TRACE_OS, "yaffs_lookup not found"); + + } + +/* added NCB for 2.5/6 compatability - forces add even if inode is + * NULL which creates dentry hash */ + d_add(dentry, inode); + + return NULL; +} + +/* + * Create a link... + */ +static int yaffs_link(struct dentry *old_dentry, struct inode *dir, + struct dentry *dentry) +{ + struct inode *inode = old_dentry->d_inode; + struct yaffs_obj *obj = NULL; + struct yaffs_obj *link = NULL; + struct yaffs_dev *dev; + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_link"); + + obj = yaffs_inode_to_obj(inode); + dev = obj->my_dev; + + yaffs_gross_lock(dev); + + if (!S_ISDIR(inode->i_mode)) /* Don't link directories */ + link = + yaffs_link_obj(yaffs_inode_to_obj(dir), dentry->d_name.name, + obj); + + if (link) { + set_nlink(old_dentry->d_inode, yaffs_get_obj_link_count(obj)); + d_instantiate(dentry, old_dentry->d_inode); + atomic_inc(&old_dentry->d_inode->i_count); + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_link link count %d i_count %d", + old_dentry->d_inode->i_nlink, + atomic_read(&old_dentry->d_inode->i_count)); + } + + yaffs_gross_unlock(dev); + + if (link) { + update_dir_time(dir); + return 0; + } + + return -EPERM; +} + +static int yaffs_symlink(struct inode *dir, struct dentry *dentry, + const char *symname) +{ + struct yaffs_obj *obj; + struct yaffs_dev *dev; + uid_t uid = YPROC_uid(current); + gid_t gid = + (dir->i_mode & S_ISGID) ? EXTRACT_gid(dir->i_gid) : YPROC_gid(current); + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_symlink"); + + if (strnlen(dentry->d_name.name, YAFFS_MAX_NAME_LENGTH + 1) > + YAFFS_MAX_NAME_LENGTH) + return -ENAMETOOLONG; + + if (strnlen(symname, YAFFS_MAX_ALIAS_LENGTH + 1) > + YAFFS_MAX_ALIAS_LENGTH) + return -ENAMETOOLONG; + + dev = yaffs_inode_to_obj(dir)->my_dev; + yaffs_gross_lock(dev); + obj = yaffs_create_symlink(yaffs_inode_to_obj(dir), dentry->d_name.name, + S_IFLNK | S_IRWXUGO, uid, gid, symname); + yaffs_gross_unlock(dev); + + if (obj) { + struct inode *inode; + + inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); + d_instantiate(dentry, inode); + update_dir_time(dir); + yaffs_trace(YAFFS_TRACE_OS, "symlink created OK"); + return 0; + } else { + yaffs_trace(YAFFS_TRACE_OS, "symlink not created"); + } + + return -ENOMEM; +} + +/* + * The VFS layer already does all the dentry stuff for rename. + * + * NB: POSIX says you can rename an object over an old object of the same name + */ +static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry, + struct inode *new_dir, struct dentry *new_dentry) +{ + struct yaffs_dev *dev; + int ret_val = YAFFS_FAIL; + struct yaffs_obj *target; + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_rename"); + dev = yaffs_inode_to_obj(old_dir)->my_dev; + + yaffs_gross_lock(dev); + + /* Check if the target is an existing directory that is not empty. */ + target = yaffs_find_by_name(yaffs_inode_to_obj(new_dir), + new_dentry->d_name.name); + + if (target && target->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY && + !list_empty(&target->variant.dir_variant.children)) { + + yaffs_trace(YAFFS_TRACE_OS, "target is non-empty dir"); + + ret_val = YAFFS_FAIL; + } else { + /* Now does unlinking internally using shadowing mechanism */ + yaffs_trace(YAFFS_TRACE_OS, "calling yaffs_rename_obj"); + + ret_val = yaffs_rename_obj(yaffs_inode_to_obj(old_dir), + old_dentry->d_name.name, + yaffs_inode_to_obj(new_dir), + new_dentry->d_name.name); + } + yaffs_gross_unlock(dev); + + if (ret_val == YAFFS_OK) { + if (target) + inode_dec_link_count(new_dentry->d_inode); + + update_dir_time(old_dir); + if (old_dir != new_dir) + update_dir_time(new_dir); + return 0; + } else { + return -ENOTEMPTY; + } +} + + + + +static int yaffs_unlink(struct inode *dir, struct dentry *dentry) +{ + int ret_val; + + struct yaffs_dev *dev; + struct yaffs_obj *obj; + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_unlink %d:%s", + (int)(dir->i_ino), dentry->d_name.name); + obj = yaffs_inode_to_obj(dir); + dev = obj->my_dev; + + yaffs_gross_lock(dev); + + ret_val = yaffs_unlinker(obj, dentry->d_name.name); + + if (ret_val == YAFFS_OK) { + inode_dec_link_count(dentry->d_inode); + dir->i_version++; + yaffs_gross_unlock(dev); + update_dir_time(dir); + return 0; + } + yaffs_gross_unlock(dev); + return -ENOTEMPTY; +} + + + +static const struct inode_operations yaffs_dir_inode_operations = { + .create = yaffs_create, + .lookup = yaffs_lookup, + .link = yaffs_link, + .unlink = yaffs_unlink, + .symlink = yaffs_symlink, + .mkdir = yaffs_mkdir, + .rmdir = yaffs_unlink, + .mknod = yaffs_mknod, + .rename = yaffs_rename, + .setattr = yaffs_setattr, + .setxattr = yaffs_setxattr, + .getxattr = yaffs_getxattr, + .listxattr = yaffs_listxattr, + .removexattr = yaffs_removexattr, +}; + +/*-----------------------------------------------------------------*/ +/* Directory search context allows us to unlock access to yaffs during + * filldir without causing problems with the directory being modified. + * This is similar to the tried and tested mechanism used in yaffs direct. + * + * A search context iterates along a doubly linked list of siblings in the + * directory. If the iterating object is deleted then this would corrupt + * the list iteration, likely causing a crash. The search context avoids + * this by using the remove_obj_fn to move the search context to the + * next object before the object is deleted. + * + * Many readdirs (and thus seach conexts) may be alive simulateously so + * each struct yaffs_dev has a list of these. + * + * A seach context lives for the duration of a readdir. + * + * All these functions must be called while yaffs is locked. + */ + +struct yaffs_search_context { + struct yaffs_dev *dev; + struct yaffs_obj *dir_obj; + struct yaffs_obj *next_return; + struct list_head others; +}; + +/* + * yaffs_new_search() creates a new search context, initialises it and + * adds it to the device's search context list. + * + * Called at start of readdir. + */ +static struct yaffs_search_context *yaffs_new_search(struct yaffs_obj *dir) +{ + struct yaffs_dev *dev = dir->my_dev; + struct yaffs_search_context *sc = + kmalloc(sizeof(struct yaffs_search_context), GFP_NOFS); + if (sc) { + sc->dir_obj = dir; + sc->dev = dev; + if (list_empty(&sc->dir_obj->variant.dir_variant.children)) + sc->next_return = NULL; + else + sc->next_return = + list_entry(dir->variant.dir_variant.children.next, + struct yaffs_obj, siblings); + INIT_LIST_HEAD(&sc->others); + list_add(&sc->others, &(yaffs_dev_to_lc(dev)->search_contexts)); + } + return sc; +} + +/* + * yaffs_search_end() disposes of a search context and cleans up. + */ +static void yaffs_search_end(struct yaffs_search_context *sc) +{ + if (sc) { + list_del(&sc->others); + kfree(sc); + } +} + +/* + * yaffs_search_advance() moves a search context to the next object. + * Called when the search iterates or when an object removal causes + * the search context to be moved to the next object. + */ +static void yaffs_search_advance(struct yaffs_search_context *sc) +{ + if (!sc) + return; + + if (sc->next_return == NULL || + list_empty(&sc->dir_obj->variant.dir_variant.children)) + sc->next_return = NULL; + else { + struct list_head *next = sc->next_return->siblings.next; + + if (next == &sc->dir_obj->variant.dir_variant.children) + sc->next_return = NULL; /* end of list */ + else + sc->next_return = + list_entry(next, struct yaffs_obj, siblings); + } +} + +/* + * yaffs_remove_obj_callback() is called when an object is unlinked. + * We check open search contexts and advance any which are currently + * on the object being iterated. + */ +static void yaffs_remove_obj_callback(struct yaffs_obj *obj) +{ + + struct list_head *i; + struct yaffs_search_context *sc; + struct list_head *search_contexts = + &(yaffs_dev_to_lc(obj->my_dev)->search_contexts); + + /* Iterate through the directory search contexts. + * If any are currently on the object being removed, then advance + * the search context to the next object to prevent a hanging pointer. + */ + list_for_each(i, search_contexts) { + sc = list_entry(i, struct yaffs_search_context, others); + if (sc->next_return == obj) + yaffs_search_advance(sc); + } + +} + + +/*-----------------------------------------------------------------*/ + +#ifdef YAFFS_USE_DIR_ITERATE +static int yaffs_iterate(struct file *f, struct dir_context *dc) +{ + struct yaffs_obj *obj; + struct yaffs_dev *dev; + struct yaffs_search_context *sc; + unsigned long curoffs; + struct yaffs_obj *l; + int ret_val = 0; + + char name[YAFFS_MAX_NAME_LENGTH + 1]; + + obj = yaffs_dentry_to_obj(f->f_dentry); + dev = obj->my_dev; + + yaffs_gross_lock(dev); + + yaffs_dev_to_lc(dev)->readdir_process = current; + + sc = yaffs_new_search(obj); + if (!sc) { + ret_val = -ENOMEM; + goto out; + } + + if (!dir_emit_dots(f, dc)) + return 0; + + curoffs = 1; + + while (sc->next_return) { + curoffs++; + l = sc->next_return; + if (curoffs >= dc->pos) { + int this_inode = yaffs_get_obj_inode(l); + int this_type = yaffs_get_obj_type(l); + + yaffs_get_obj_name(l, name, YAFFS_MAX_NAME_LENGTH + 1); + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readdir: %s inode %d", + name, yaffs_get_obj_inode(l)); + + yaffs_gross_unlock(dev); + + if (!dir_emit(dc, + name, + strlen(name), + this_inode, + this_type)) { + yaffs_gross_lock(dev); + goto out; + } + + yaffs_gross_lock(dev); + + dc->pos++; + f->f_pos++; + } + yaffs_search_advance(sc); + } + +out: + yaffs_search_end(sc); + yaffs_dev_to_lc(dev)->readdir_process = NULL; + yaffs_gross_unlock(dev); + + return ret_val; +} + +#else + +static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir) +{ + struct yaffs_obj *obj; + struct yaffs_dev *dev; + struct yaffs_search_context *sc; + struct inode *inode = f->f_dentry->d_inode; + unsigned long offset, curoffs; + struct yaffs_obj *l; + int ret_val = 0; + + char name[YAFFS_MAX_NAME_LENGTH + 1]; + + obj = yaffs_dentry_to_obj(f->f_dentry); + dev = obj->my_dev; + + yaffs_gross_lock(dev); + + yaffs_dev_to_lc(dev)->readdir_process = current; + + offset = f->f_pos; + + sc = yaffs_new_search(obj); + if (!sc) { + ret_val = -ENOMEM; + goto out; + } + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readdir: starting at %d", (int)offset); + + if (offset == 0) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readdir: entry . ino %d", + (int)inode->i_ino); + yaffs_gross_unlock(dev); + if (filldir(dirent, ".", 1, offset, inode->i_ino, DT_DIR) < 0) { + yaffs_gross_lock(dev); + goto out; + } + yaffs_gross_lock(dev); + offset++; + f->f_pos++; + } + if (offset == 1) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readdir: entry .. ino %d", + (int)f->f_dentry->d_parent->d_inode->i_ino); + yaffs_gross_unlock(dev); + if (filldir(dirent, "..", 2, offset, + f->f_dentry->d_parent->d_inode->i_ino, + DT_DIR) < 0) { + yaffs_gross_lock(dev); + goto out; + } + yaffs_gross_lock(dev); + offset++; + f->f_pos++; + } + + curoffs = 1; + + /* If the directory has changed since the open or last call to + readdir, rewind to after the 2 canned entries. */ + if (f->f_version != inode->i_version) { + offset = 2; + f->f_pos = offset; + f->f_version = inode->i_version; + } + + while (sc->next_return) { + curoffs++; + l = sc->next_return; + if (curoffs >= offset) { + int this_inode = yaffs_get_obj_inode(l); + int this_type = yaffs_get_obj_type(l); + + yaffs_get_obj_name(l, name, YAFFS_MAX_NAME_LENGTH + 1); + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readdir: %s inode %d", + name, yaffs_get_obj_inode(l)); + + yaffs_gross_unlock(dev); + + if (filldir(dirent, + name, + strlen(name), + offset, this_inode, this_type) < 0) { + yaffs_gross_lock(dev); + goto out; + } + + yaffs_gross_lock(dev); + + offset++; + f->f_pos++; + } + yaffs_search_advance(sc); + } + +out: + yaffs_search_end(sc); + yaffs_dev_to_lc(dev)->readdir_process = NULL; + yaffs_gross_unlock(dev); + + return ret_val; +} + +#endif + +static const struct file_operations yaffs_dir_operations = { + .read = generic_read_dir, +#ifdef YAFFS_USE_DIR_ITERATE + .iterate = yaffs_iterate, +#else + .readdir = yaffs_readdir, +#endif + .fsync = yaffs_sync_object, + .llseek = generic_file_llseek, +}; + +static void yaffs_fill_inode_from_obj(struct inode *inode, + struct yaffs_obj *obj) +{ + if (inode && obj) { + + /* Check mode against the variant type and attempt to repair if broken. */ + u32 mode = obj->yst_mode; + switch (obj->variant_type) { + case YAFFS_OBJECT_TYPE_FILE: + if (!S_ISREG(mode)) { + obj->yst_mode &= ~S_IFMT; + obj->yst_mode |= S_IFREG; + } + + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + if (!S_ISLNK(mode)) { + obj->yst_mode &= ~S_IFMT; + obj->yst_mode |= S_IFLNK; + } + + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + if (!S_ISDIR(mode)) { + obj->yst_mode &= ~S_IFMT; + obj->yst_mode |= S_IFDIR; + } + + break; + case YAFFS_OBJECT_TYPE_UNKNOWN: + case YAFFS_OBJECT_TYPE_HARDLINK: + case YAFFS_OBJECT_TYPE_SPECIAL: + default: + /* TODO? */ + break; + } + + inode->i_flags |= S_NOATIME; + + inode->i_ino = obj->obj_id; + inode->i_mode = obj->yst_mode; + inode->i_uid = MAKE_uid(obj->yst_uid); + inode->i_gid = MAKE_gid(obj->yst_gid); +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) + inode->i_blksize = inode->i_sb->s_blocksize; +#endif +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) + + inode->i_rdev = old_decode_dev(obj->yst_rdev); + inode->i_atime.tv_sec = (time_t) (obj->yst_atime); + inode->i_atime.tv_nsec = 0; + inode->i_mtime.tv_sec = (time_t) obj->yst_mtime; + inode->i_mtime.tv_nsec = 0; + inode->i_ctime.tv_sec = (time_t) obj->yst_ctime; + inode->i_ctime.tv_nsec = 0; +#else + inode->i_rdev = obj->yst_rdev; + inode->i_atime = obj->yst_atime; + inode->i_mtime = obj->yst_mtime; + inode->i_ctime = obj->yst_ctime; +#endif + inode->i_size = yaffs_get_obj_length(obj); + inode->i_blocks = (inode->i_size + 511) >> 9; + + set_nlink(inode, yaffs_get_obj_link_count(obj)); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_fill_inode mode %x uid %d gid %d size %lld count %d", + inode->i_mode, obj->yst_uid, obj->yst_gid, + inode->i_size, atomic_read(&inode->i_count)); + + switch (obj->yst_mode & S_IFMT) { + default: /* fifo, device or socket */ +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) + init_special_inode(inode, obj->yst_mode, + old_decode_dev(obj->yst_rdev)); +#else + init_special_inode(inode, obj->yst_mode, + (dev_t) (obj->yst_rdev)); +#endif + break; + case S_IFREG: /* file */ + inode->i_op = &yaffs_file_inode_operations; + inode->i_fop = &yaffs_file_operations; + inode->i_mapping->a_ops = + &yaffs_file_address_operations; + break; + case S_IFDIR: /* directory */ + inode->i_op = &yaffs_dir_inode_operations; + inode->i_fop = &yaffs_dir_operations; + break; + case S_IFLNK: /* symlink */ + inode->i_op = &yaffs_symlink_inode_operations; + break; + } + + yaffs_inode_to_obj_lv(inode) = obj; + + obj->my_inode = inode; + + } else { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_fill_inode invalid parameters"); + } + +} + + + +/* + * yaffs background thread functions . + * yaffs_bg_thread_fn() the thread function + * yaffs_bg_start() launches the background thread. + * yaffs_bg_stop() cleans up the background thread. + * + * NB: + * The thread should only run after the yaffs is initialised + * The thread should be stopped before yaffs is unmounted. + * The thread should not do any writing while the fs is in read only. + */ + +static unsigned yaffs_bg_gc_urgency(struct yaffs_dev *dev) +{ + unsigned erased_chunks = + dev->n_erased_blocks * dev->param.chunks_per_block; + struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); + unsigned scattered = 0; /* Free chunks not in an erased block */ + + if (erased_chunks < dev->n_free_chunks) + scattered = (dev->n_free_chunks - erased_chunks); + + if (!context->bg_running) + return 0; + else if (scattered < (dev->param.chunks_per_block * 2)) + return 0; + else if (erased_chunks > dev->n_free_chunks / 2) + return 0; + else if (erased_chunks > dev->n_free_chunks / 4) + return 1; + else + return 2; +} + +#ifdef YAFFS_COMPILE_BACKGROUND + +void yaffs_background_waker(unsigned long data) +{ + wake_up_process((struct task_struct *)data); +} + +static int yaffs_bg_thread_fn(void *data) +{ + struct yaffs_dev *dev = (struct yaffs_dev *)data; + struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); + unsigned long now = jiffies; + unsigned long next_dir_update = now; + unsigned long next_gc = now; + unsigned long expires; + unsigned int urgency; + + int gc_result; + struct timer_list timer; + + yaffs_trace(YAFFS_TRACE_BACKGROUND, + "yaffs_background starting for dev %p", (void *)dev); + +#ifdef YAFFS_COMPILE_FREEZER + set_freezable(); +#endif + while (context->bg_running) { + yaffs_trace(YAFFS_TRACE_BACKGROUND, "yaffs_background"); + + if (kthread_should_stop()) + break; + +#ifdef YAFFS_COMPILE_FREEZER + if (try_to_freeze()) + continue; +#endif + yaffs_gross_lock(dev); + + now = jiffies; + + if (time_after(now, next_dir_update) && yaffs_bg_enable) { + yaffs_update_dirty_dirs(dev); + next_dir_update = now + HZ; + } + + if (time_after(now, next_gc) && yaffs_bg_enable) { + if (!dev->is_checkpointed) { + urgency = yaffs_bg_gc_urgency(dev); + gc_result = yaffs_bg_gc(dev, urgency); + if (urgency > 1) + next_gc = now + HZ / 20 + 1; + else if (urgency > 0) + next_gc = now + HZ / 10 + 1; + else + next_gc = now + HZ * 2; + } else { + /* + * gc not running so set to next_dir_update + * to cut down on wake ups + */ + next_gc = next_dir_update; + } + } + yaffs_gross_unlock(dev); +#if 1 + expires = next_dir_update; + if (time_before(next_gc, expires)) + expires = next_gc; + if (time_before(expires, now)) + expires = now + HZ; + + Y_INIT_TIMER(&timer); + timer.expires = expires + 1; + timer.data = (unsigned long)current; + timer.function = yaffs_background_waker; + + set_current_state(TASK_INTERRUPTIBLE); + add_timer(&timer); + schedule(); + del_timer_sync(&timer); +#else + msleep(10); +#endif + } + + return 0; +} + +static int yaffs_bg_start(struct yaffs_dev *dev) +{ + int retval = 0; + struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); + + if (dev->read_only) + return -1; + + context->bg_running = 1; + + context->bg_thread = kthread_run(yaffs_bg_thread_fn, + (void *)dev, "yaffs-bg-%d", + context->mount_id); + + if (IS_ERR(context->bg_thread)) { + retval = PTR_ERR(context->bg_thread); + context->bg_thread = NULL; + context->bg_running = 0; + } + return retval; +} + +static void yaffs_bg_stop(struct yaffs_dev *dev) +{ + struct yaffs_linux_context *ctxt = yaffs_dev_to_lc(dev); + + ctxt->bg_running = 0; + + if (ctxt->bg_thread) { + kthread_stop(ctxt->bg_thread); + ctxt->bg_thread = NULL; + } +} +#else +static int yaffs_bg_thread_fn(void *data) +{ + return 0; +} + +static int yaffs_bg_start(struct yaffs_dev *dev) +{ + return 0; +} + +static void yaffs_bg_stop(struct yaffs_dev *dev) +{ +} +#endif + + +static void yaffs_flush_inodes(struct super_block *sb) +{ + struct inode *iptr; + struct yaffs_obj *obj; + + list_for_each_entry(iptr, &sb->s_inodes, i_sb_list) { + obj = yaffs_inode_to_obj(iptr); + if (obj) { + yaffs_trace(YAFFS_TRACE_OS, + "flushing obj %d", + obj->obj_id); + yaffs_flush_file(obj, 1, 0, 0); + } + } +} + +static void yaffs_flush_super(struct super_block *sb, int do_checkpoint) +{ + struct yaffs_dev *dev = yaffs_super_to_dev(sb); + if (!dev) + return; + + yaffs_flush_inodes(sb); + yaffs_update_dirty_dirs(dev); + yaffs_flush_whole_cache(dev, 1); + if (do_checkpoint) + yaffs_checkpoint_save(dev); +} + +static LIST_HEAD(yaffs_context_list); +struct mutex yaffs_context_lock; + +static void yaffs_put_super(struct super_block *sb) +{ + struct yaffs_dev *dev = yaffs_super_to_dev(sb); + struct mtd_info *mtd = yaffs_dev_to_mtd(dev); + + yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_ALWAYS, + "yaffs_put_super"); + + yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_BACKGROUND, + "Shutting down yaffs background thread"); + yaffs_bg_stop(dev); + yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_BACKGROUND, + "yaffs background thread shut down"); + + yaffs_gross_lock(dev); + + yaffs_flush_super(sb, 1); + + yaffs_deinitialise(dev); + + yaffs_gross_unlock(dev); + + mutex_lock(&yaffs_context_lock); + list_del_init(&(yaffs_dev_to_lc(dev)->context_list)); + mutex_unlock(&yaffs_context_lock); + + if (yaffs_dev_to_lc(dev)->spare_buffer) { + kfree(yaffs_dev_to_lc(dev)->spare_buffer); + yaffs_dev_to_lc(dev)->spare_buffer = NULL; + } + + kfree(dev); + + yaffs_put_mtd_device(mtd); + + yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_ALWAYS, + "yaffs_put_super done"); +} + + +static unsigned yaffs_gc_control_callback(struct yaffs_dev *dev) +{ + return yaffs_gc_control; +} + + +#ifdef YAFFS_COMPILE_EXPORTFS + +static struct inode *yaffs2_nfs_get_inode(struct super_block *sb, uint64_t ino, + uint32_t generation) +{ + return Y_IGET(sb, ino); +} + +static struct dentry *yaffs2_fh_to_dentry(struct super_block *sb, + struct fid *fid, int fh_len, + int fh_type) +{ + return generic_fh_to_dentry(sb, fid, fh_len, fh_type, + yaffs2_nfs_get_inode); +} + +static struct dentry *yaffs2_fh_to_parent(struct super_block *sb, + struct fid *fid, int fh_len, + int fh_type) +{ + return generic_fh_to_parent(sb, fid, fh_len, fh_type, + yaffs2_nfs_get_inode); +} + +struct dentry *yaffs2_get_parent(struct dentry *dentry) +{ + + struct super_block *sb = dentry->d_inode->i_sb; + struct dentry *parent = ERR_PTR(-ENOENT); + struct inode *inode; + unsigned long parent_ino; + struct yaffs_obj *d_obj; + struct yaffs_obj *parent_obj; + + d_obj = yaffs_inode_to_obj(dentry->d_inode); + + if (d_obj) { + parent_obj = d_obj->parent; + if (parent_obj) { + parent_ino = yaffs_get_obj_inode(parent_obj); + inode = Y_IGET(sb, parent_ino); + + if (IS_ERR(inode)) { + parent = ERR_CAST(inode); + } else { + parent = d_obtain_alias(inode); + if (!IS_ERR(parent)) { + parent = ERR_PTR(-ENOMEM); + iput(inode); + } + } + } + } + + return parent; +} + +/* Just declare a zero structure as a NULL value implies + * using the default functions of exportfs. + */ + +static struct export_operations yaffs_export_ops = { + .fh_to_dentry = yaffs2_fh_to_dentry, + .fh_to_parent = yaffs2_fh_to_parent, + .get_parent = yaffs2_get_parent, +}; + +#endif + +static void yaffs_unstitch_obj(struct inode *inode, struct yaffs_obj *obj) +{ + /* Clear the association between the inode and + * the struct yaffs_obj. + */ + obj->my_inode = NULL; + yaffs_inode_to_obj_lv(inode) = NULL; + + /* If the object freeing was deferred, then the real + * free happens now. + * This should fix the inode inconsistency problem. + */ + yaffs_handle_defered_free(obj); +} + +#ifdef YAFFS_HAS_EVICT_INODE +/* yaffs_evict_inode combines into one operation what was previously done in + * yaffs_clear_inode() and yaffs_delete_inode() + * + */ +static void yaffs_evict_inode(struct inode *inode) +{ + struct yaffs_obj *obj; + struct yaffs_dev *dev; + int deleteme = 0; + + obj = yaffs_inode_to_obj(inode); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_evict_inode: ino %d, count %d %s", + (int)inode->i_ino, atomic_read(&inode->i_count), + obj ? "object exists" : "null object"); + + if (!inode->i_nlink && !is_bad_inode(inode)) + deleteme = 1; + truncate_inode_pages(&inode->i_data, 0); + Y_CLEAR_INODE(inode); + + if (deleteme && obj) { + dev = obj->my_dev; + yaffs_gross_lock(dev); + yaffs_del_obj(obj); + yaffs_gross_unlock(dev); + } + if (obj) { + dev = obj->my_dev; + yaffs_gross_lock(dev); + yaffs_unstitch_obj(inode, obj); + yaffs_gross_unlock(dev); + } +} +#else + +/* clear is called to tell the fs to release any per-inode data it holds. + * The object might still exist on disk and is just being thrown out of the cache + * or else the object has actually been deleted and we're being called via + * the chain + * yaffs_delete_inode() -> clear_inode()->yaffs_clear_inode() + */ + +static void yaffs_clear_inode(struct inode *inode) +{ + struct yaffs_obj *obj; + struct yaffs_dev *dev; + + obj = yaffs_inode_to_obj(inode); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_clear_inode: ino %d, count %d %s", + (int)inode->i_ino, atomic_read(&inode->i_count), + obj ? "object exists" : "null object"); + + if (obj) { + dev = obj->my_dev; + yaffs_gross_lock(dev); + yaffs_unstitch_obj(inode, obj); + yaffs_gross_unlock(dev); + } + +} + +/* delete is called when the link count is zero and the inode + * is put (ie. nobody wants to know about it anymore, time to + * delete the file). + * NB Must call clear_inode() + */ +static void yaffs_delete_inode(struct inode *inode) +{ + struct yaffs_obj *obj = yaffs_inode_to_obj(inode); + struct yaffs_dev *dev; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_delete_inode: ino %d, count %d %s", + (int)inode->i_ino, atomic_read(&inode->i_count), + obj ? "object exists" : "null object"); + + if (obj) { + dev = obj->my_dev; + yaffs_gross_lock(dev); + yaffs_del_obj(obj); + yaffs_gross_unlock(dev); + } +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13)) + truncate_inode_pages(&inode->i_data, 0); +#endif + clear_inode(inode); +} +#endif + + + + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) +static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf) +{ + struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; + struct super_block *sb = dentry->d_sb; +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf) +{ + struct yaffs_dev *dev = yaffs_super_to_dev(sb); +#else +static int yaffs_statfs(struct super_block *sb, struct statfs *buf) +{ + struct yaffs_dev *dev = yaffs_super_to_dev(sb); +#endif + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_statfs"); + + yaffs_gross_lock(dev); + + buf->f_type = YAFFS_MAGIC; + buf->f_bsize = sb->s_blocksize; + buf->f_namelen = 255; + + if (dev->data_bytes_per_chunk & (dev->data_bytes_per_chunk - 1)) { + /* Do this if chunk size is not a power of 2 */ + + uint64_t bytes_in_dev; + uint64_t bytes_free; + + bytes_in_dev = + ((uint64_t) + ((dev->param.end_block - dev->param.start_block + + 1))) * ((uint64_t) (dev->param.chunks_per_block * + dev->data_bytes_per_chunk)); + + do_div(bytes_in_dev, sb->s_blocksize); /* bytes_in_dev becomes the number of blocks */ + buf->f_blocks = bytes_in_dev; + + bytes_free = ((uint64_t) (yaffs_get_n_free_chunks(dev))) * + ((uint64_t) (dev->data_bytes_per_chunk)); + + do_div(bytes_free, sb->s_blocksize); + + buf->f_bfree = bytes_free; + + } else if (sb->s_blocksize > dev->data_bytes_per_chunk) { + + buf->f_blocks = + (dev->param.end_block - dev->param.start_block + 1) * + dev->param.chunks_per_block / + (sb->s_blocksize / dev->data_bytes_per_chunk); + buf->f_bfree = + yaffs_get_n_free_chunks(dev) / + (sb->s_blocksize / dev->data_bytes_per_chunk); + } else { + buf->f_blocks = + (dev->param.end_block - dev->param.start_block + 1) * + dev->param.chunks_per_block * + (dev->data_bytes_per_chunk / sb->s_blocksize); + + buf->f_bfree = + yaffs_get_n_free_chunks(dev) * + (dev->data_bytes_per_chunk / sb->s_blocksize); + } + + buf->f_files = 0; + buf->f_ffree = 0; + buf->f_bavail = buf->f_bfree; + + yaffs_gross_unlock(dev); + return 0; +} + + + +static int yaffs_do_sync_fs(struct super_block *sb, int request_checkpoint) +{ + + struct yaffs_dev *dev = yaffs_super_to_dev(sb); + unsigned int oneshot_checkpoint = (yaffs_auto_checkpoint & 4); + unsigned gc_urgent = yaffs_bg_gc_urgency(dev); + int do_checkpoint; + int dirty = yaffs_check_super_dirty(dev); + + yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC | YAFFS_TRACE_BACKGROUND, + "yaffs_do_sync_fs: gc-urgency %d %s %s%s", + gc_urgent, + dirty ? "dirty" : "clean", + request_checkpoint ? "checkpoint requested" : "no checkpoint", + oneshot_checkpoint ? " one-shot" : ""); + + yaffs_gross_lock(dev); + do_checkpoint = ((request_checkpoint && !gc_urgent) || + oneshot_checkpoint) && !dev->is_checkpointed; + + if (dirty || do_checkpoint) { + yaffs_flush_super(sb, !dev->is_checkpointed && do_checkpoint); + yaffs_clear_super_dirty(dev); + if (oneshot_checkpoint) + yaffs_auto_checkpoint &= ~4; + } + yaffs_gross_unlock(dev); + + return 0; +} + + +#ifdef YAFFS_HAS_WRITE_SUPER +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) +static void yaffs_write_super(struct super_block *sb) +#else +static int yaffs_write_super(struct super_block *sb) +#endif +{ + unsigned request_checkpoint = (yaffs_auto_checkpoint >= 2); + + yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC | YAFFS_TRACE_BACKGROUND, + "yaffs_write_super %s", + request_checkpoint ? " checkpt" : ""); + + yaffs_do_sync_fs(sb, request_checkpoint); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + return 0; +#endif +} +#endif + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) +static int yaffs_sync_fs(struct super_block *sb, int wait) +#else +static int yaffs_sync_fs(struct super_block *sb) +#endif +{ + unsigned request_checkpoint = (yaffs_auto_checkpoint >= 1); + + yaffs_trace(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, + "yaffs_sync_fs%s", request_checkpoint ? " checkpt" : ""); + + yaffs_do_sync_fs(sb, request_checkpoint); + + return 0; +} + +/* the function only is used to change dev->read_only when this file system + * is remounted. + */ +static int yaffs_remount_fs(struct super_block *sb, int *flags, char *data) +{ + int read_only = 0; + struct mtd_info *mtd; + struct yaffs_dev *dev = 0; + + /* Get the device */ + mtd = get_mtd_device(NULL, MINOR(sb->s_dev)); + if (!mtd) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "MTD device #%u doesn't appear to exist", + MINOR(sb->s_dev)); + return 1; + } + + /* Check it's NAND */ + if (mtd->type != MTD_NANDFLASH) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "MTD device is not NAND it's type %d", + mtd->type); + return 1; + } + + read_only = ((*flags & MS_RDONLY) != 0); + if (!read_only && !(mtd->flags & MTD_WRITEABLE)) { + read_only = 1; + printk(KERN_INFO + "yaffs: mtd is read only, setting superblock read only"); + *flags |= MS_RDONLY; + } + + dev = sb->s_fs_info; + dev->read_only = read_only; + + return 0; +} + +static const struct super_operations yaffs_super_ops = { + .statfs = yaffs_statfs, + +#ifndef YAFFS_USE_OWN_IGET + .read_inode = yaffs_read_inode, +#endif +#ifdef YAFFS_HAS_PUT_INODE + .put_inode = yaffs_put_inode, +#endif + .put_super = yaffs_put_super, +#ifdef YAFFS_HAS_EVICT_INODE + .evict_inode = yaffs_evict_inode, +#else + .delete_inode = yaffs_delete_inode, + .clear_inode = yaffs_clear_inode, +#endif + .sync_fs = yaffs_sync_fs, +#ifdef YAFFS_HAS_WRITE_SUPER + .write_super = yaffs_write_super, +#endif + .remount_fs = yaffs_remount_fs, +}; + +struct yaffs_options { + int inband_tags; + int skip_checkpoint_read; + int skip_checkpoint_write; + int no_cache; + int tags_ecc_on; + int tags_ecc_overridden; + int lazy_loading_enabled; + int lazy_loading_overridden; + int empty_lost_and_found; + int empty_lost_and_found_overridden; + int disable_summary; +}; + +#define MAX_OPT_LEN 30 +static int yaffs_parse_options(struct yaffs_options *options, + const char *options_str) +{ + char cur_opt[MAX_OPT_LEN + 1]; + int p; + int error = 0; + + /* Parse through the options which is a comma seperated list */ + + while (options_str && *options_str && !error) { + memset(cur_opt, 0, MAX_OPT_LEN + 1); + p = 0; + + while (*options_str == ',') + options_str++; + + while (*options_str && *options_str != ',') { + if (p < MAX_OPT_LEN) { + cur_opt[p] = *options_str; + p++; + } + options_str++; + } + + if (!strcmp(cur_opt, "inband-tags")) { + options->inband_tags = 1; + } else if (!strcmp(cur_opt, "tags-ecc-off")) { + options->tags_ecc_on = 0; + options->tags_ecc_overridden = 1; + } else if (!strcmp(cur_opt, "tags-ecc-on")) { + options->tags_ecc_on = 1; + options->tags_ecc_overridden = 1; + } else if (!strcmp(cur_opt, "lazy-loading-off")) { + options->lazy_loading_enabled = 0; + options->lazy_loading_overridden = 1; + } else if (!strcmp(cur_opt, "lazy-loading-on")) { + options->lazy_loading_enabled = 1; + options->lazy_loading_overridden = 1; + } else if (!strcmp(cur_opt, "disable-summary")) { + options->disable_summary = 1; + } else if (!strcmp(cur_opt, "empty-lost-and-found-off")) { + options->empty_lost_and_found = 0; + options->empty_lost_and_found_overridden = 1; + } else if (!strcmp(cur_opt, "empty-lost-and-found-on")) { + options->empty_lost_and_found = 1; + options->empty_lost_and_found_overridden = 1; + } else if (!strcmp(cur_opt, "no-cache")) { + options->no_cache = 1; + } else if (!strcmp(cur_opt, "no-checkpoint-read")) { + options->skip_checkpoint_read = 1; + } else if (!strcmp(cur_opt, "no-checkpoint-write")) { + options->skip_checkpoint_write = 1; + } else if (!strcmp(cur_opt, "no-checkpoint")) { + options->skip_checkpoint_read = 1; + options->skip_checkpoint_write = 1; + } else { + printk(KERN_INFO "yaffs: Bad mount option \"%s\"\n", + cur_opt); + error = 1; + } + } + + return error; +} + + +static struct dentry *yaffs_make_root(struct inode *inode) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) + struct dentry *root = d_alloc_root(inode); + + if (!root) + iput(inode); + + return root; +#else + return d_make_root(inode); +#endif +} + + + + +static struct super_block *yaffs_internal_read_super(int yaffs_version, + struct super_block *sb, + void *data, int silent) +{ + int n_blocks; + struct inode *inode = NULL; + struct dentry *root; + struct yaffs_dev *dev = 0; + char devname_buf[BDEVNAME_SIZE + 1]; + struct mtd_info *mtd; + int err; + char *data_str = (char *)data; + struct yaffs_linux_context *context = NULL; + struct yaffs_param *param; + + int read_only = 0; + int inband_tags = 0; + + struct yaffs_options options; + + unsigned mount_id; + int found; + struct yaffs_linux_context *context_iterator; + struct list_head *l; + + if (!sb) { + printk(KERN_INFO "yaffs: sb is NULL\n"); + return NULL; + } + + sb->s_magic = YAFFS_MAGIC; + sb->s_op = &yaffs_super_ops; + sb->s_flags |= MS_NOATIME; + + read_only = ((sb->s_flags & MS_RDONLY) != 0); + +#ifdef YAFFS_COMPILE_EXPORTFS + sb->s_export_op = &yaffs_export_ops; +#endif + + if (!sb->s_dev) + printk(KERN_INFO "yaffs: sb->s_dev is NULL\n"); + else if (!yaffs_devname(sb, devname_buf)) + printk(KERN_INFO "yaffs: devname is NULL\n"); + else + printk(KERN_INFO "yaffs: dev is %d name is \"%s\" %s\n", + sb->s_dev, + yaffs_devname(sb, devname_buf), read_only ? "ro" : "rw"); + + if (!data_str) + data_str = ""; + + printk(KERN_INFO "yaffs: passed flags \"%s\"\n", data_str); + + memset(&options, 0, sizeof(options)); + + if (yaffs_parse_options(&options, data_str)) { + /* Option parsing failed */ + return NULL; + } + + sb->s_blocksize = PAGE_CACHE_SIZE; + sb->s_blocksize_bits = PAGE_CACHE_SHIFT; + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_read_super: Using yaffs%d", yaffs_version); + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_read_super: block size %d", (int)(sb->s_blocksize)); + + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs: Attempting MTD mount of %u.%u,\"%s\"", + MAJOR(sb->s_dev), MINOR(sb->s_dev), + yaffs_devname(sb, devname_buf)); + + /* Get the device */ + mtd = get_mtd_device(NULL, MINOR(sb->s_dev)); + if (IS_ERR(mtd)) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs: MTD device %u either not valid or unavailable", + MINOR(sb->s_dev)); + return NULL; + } + + if (yaffs_auto_select && yaffs_version == 1 && WRITE_SIZE(mtd) >= 2048) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting yaffs2"); + yaffs_version = 2; + } + + /* Added NCB 26/5/2006 for completeness */ + if (yaffs_version == 2 && !options.inband_tags + && WRITE_SIZE(mtd) == 512) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting yaffs1"); + yaffs_version = 1; + } + + if (mtd->oobavail < sizeof(struct yaffs_packed_tags2) || + options.inband_tags) + inband_tags = 1; + + if(yaffs_verify_mtd(mtd, yaffs_version, inband_tags) < 0) + return NULL; + + /* OK, so if we got here, we have an MTD that's NAND and looks + * like it has the right capabilities + * Set the struct yaffs_dev up for mtd + */ + + if (!read_only && !(mtd->flags & MTD_WRITEABLE)) { + read_only = 1; + printk(KERN_INFO + "yaffs: mtd is read only, setting superblock read only\n" + ); + sb->s_flags |= MS_RDONLY; + } + + dev = kmalloc(sizeof(struct yaffs_dev), GFP_KERNEL); + context = kmalloc(sizeof(struct yaffs_linux_context), GFP_KERNEL); + + if (!dev || !context) { + kfree(dev); + kfree(context); + dev = NULL; + context = NULL; + + /* Deep shit could not allocate device structure */ + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs_read_super: Failed trying to allocate struct yaffs_dev." + ); + return NULL; + } + memset(dev, 0, sizeof(struct yaffs_dev)); + param = &(dev->param); + + memset(context, 0, sizeof(struct yaffs_linux_context)); + dev->os_context = context; + INIT_LIST_HEAD(&(context->context_list)); + context->dev = dev; + context->super = sb; + + dev->read_only = read_only; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) + sb->s_fs_info = dev; +#else + sb->u.generic_sbp = dev; +#endif + + + dev->driver_context = mtd; + param->name = mtd->name; + + /* Set up the memory size parameters.... */ + + + param->n_reserved_blocks = 5; + param->n_caches = (options.no_cache) ? 0 : 10; + param->inband_tags = inband_tags; + + param->enable_xattr = 1; + if (options.lazy_loading_overridden) + param->disable_lazy_load = !options.lazy_loading_enabled; + + param->defered_dir_update = 1; + + if (options.tags_ecc_overridden) + param->no_tags_ecc = !options.tags_ecc_on; + + param->empty_lost_n_found = 1; + param->refresh_period = 500; + param->disable_summary = options.disable_summary; + + +#ifdef CONFIG_YAFFS_DISABLE_BAD_BLOCK_MARKING + param->disable_bad_block_marking = 1; +#endif + if (options.empty_lost_and_found_overridden) + param->empty_lost_n_found = options.empty_lost_and_found; + + /* ... and the functions. */ + if (yaffs_version == 2) { + param->is_yaffs2 = 1; +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) + param->total_bytes_per_chunk = mtd->writesize; + param->chunks_per_block = mtd->erasesize / mtd->writesize; +#else + param->total_bytes_per_chunk = mtd->oobblock; + param->chunks_per_block = mtd->erasesize / mtd->oobblock; +#endif + n_blocks = YCALCBLOCKS(mtd->size, mtd->erasesize); + + param->start_block = 0; + param->end_block = n_blocks - 1; + } else { + param->is_yaffs2 = 0; + n_blocks = YCALCBLOCKS(mtd->size, + YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK); + + param->chunks_per_block = YAFFS_CHUNKS_PER_BLOCK; + param->total_bytes_per_chunk = YAFFS_BYTES_PER_CHUNK; + } + + param->start_block = 0; + param->end_block = n_blocks - 1; + + yaffs_mtd_drv_install(dev); + + param->sb_dirty_fn = yaffs_set_super_dirty; + param->gc_control_fn = yaffs_gc_control_callback; + + yaffs_dev_to_lc(dev)->super = sb; + + param->use_nand_ecc = 1; + + param->skip_checkpt_rd = options.skip_checkpoint_read; + param->skip_checkpt_wr = options.skip_checkpoint_write; + + mutex_lock(&yaffs_context_lock); + /* Get a mount id */ + found = 0; + for (mount_id = 0; !found; mount_id++) { + found = 1; + list_for_each(l, &yaffs_context_list) { + context_iterator = + list_entry(l, struct yaffs_linux_context, + context_list); + if (context_iterator->mount_id == mount_id) + found = 0; + } + } + context->mount_id = mount_id; + + list_add_tail(&(yaffs_dev_to_lc(dev)->context_list), + &yaffs_context_list); + mutex_unlock(&yaffs_context_lock); + + /* Directory search handling... */ + INIT_LIST_HEAD(&(yaffs_dev_to_lc(dev)->search_contexts)); + param->remove_obj_fn = yaffs_remove_obj_callback; + + mutex_init(&(yaffs_dev_to_lc(dev)->gross_lock)); + + yaffs_gross_lock(dev); + + err = yaffs_guts_initialise(dev); + + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_read_super: guts initialised %s", + (err == YAFFS_OK) ? "OK" : "FAILED"); + + if (err == YAFFS_OK) + yaffs_bg_start(dev); + + if (!context->bg_thread) + param->defered_dir_update = 0; + + sb->s_maxbytes = yaffs_max_file_size(dev); + + /* Release lock before yaffs_get_inode() */ + yaffs_gross_unlock(dev); + + /* Create root inode */ + if (err == YAFFS_OK) + inode = yaffs_get_inode(sb, S_IFDIR | 0755, 0, yaffs_root(dev)); + + if (!inode) + return NULL; + + inode->i_op = &yaffs_dir_inode_operations; + inode->i_fop = &yaffs_dir_operations; + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_read_super: got root inode"); + + root = yaffs_make_root(inode); + + if (!root) + return NULL; + + sb->s_root = root; + if(!dev->is_checkpointed) + yaffs_set_super_dirty(dev); + + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs_read_super: is_checkpointed %d", + dev->is_checkpointed); + + yaffs_trace(YAFFS_TRACE_OS, "yaffs_read_super: done"); + return sb; +} + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +static int yaffs_internal_read_super_mtd(struct super_block *sb, void *data, + int silent) +{ + return yaffs_internal_read_super(1, sb, data, silent) ? 0 : -EINVAL; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) +static struct dentry *yaffs_mount(struct file_system_type *fs_type, int flags, + const char *dev_name, void *data) +{ + return mount_bdev(fs_type, flags, dev_name, data, yaffs_internal_read_super_mtd); +} +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) +static int yaffs_read_super(struct file_system_type *fs, + int flags, const char *dev_name, + void *data, struct vfsmount *mnt) +{ + + return get_sb_bdev(fs, flags, dev_name, data, + yaffs_internal_read_super_mtd, mnt); +} +#else +static struct super_block *yaffs_read_super(struct file_system_type *fs, + int flags, const char *dev_name, + void *data) +{ + + return get_sb_bdev(fs, flags, dev_name, data, + yaffs_internal_read_super_mtd); +} +#endif + +static struct file_system_type yaffs_fs_type = { + .owner = THIS_MODULE, + .name = "yaffs", +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) + .mount = yaffs_mount, +#else + .get_sb = yaffs_read_super, +#endif + .kill_sb = kill_block_super, + .fs_flags = FS_REQUIRES_DEV, +}; +#else +static struct super_block *yaffs_read_super(struct super_block *sb, void *data, + int silent) +{ + return yaffs_internal_read_super(1, sb, data, silent); +} + +static DECLARE_FSTYPE(yaffs_fs_type, "yaffs", yaffs_read_super, + FS_REQUIRES_DEV); +#endif + + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +static int yaffs2_internal_read_super_mtd(struct super_block *sb, void *data, + int silent) +{ + return yaffs_internal_read_super(2, sb, data, silent) ? 0 : -EINVAL; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) +static struct dentry *yaffs2_mount(struct file_system_type *fs_type, int flags, + const char *dev_name, void *data) +{ + return mount_bdev(fs_type, flags, dev_name, data, yaffs2_internal_read_super_mtd); +} +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) +static int yaffs2_read_super(struct file_system_type *fs, + int flags, const char *dev_name, void *data, + struct vfsmount *mnt) +{ + return get_sb_bdev(fs, flags, dev_name, data, + yaffs2_internal_read_super_mtd, mnt); +} +#else +static struct super_block *yaffs2_read_super(struct file_system_type *fs, + int flags, const char *dev_name, + void *data) +{ + + return get_sb_bdev(fs, flags, dev_name, data, + yaffs2_internal_read_super_mtd); +} +#endif + +static struct file_system_type yaffs2_fs_type = { + .owner = THIS_MODULE, + .name = "yaffs2", +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) + .mount = yaffs2_mount, +#else + .get_sb = yaffs2_read_super, +#endif + .kill_sb = kill_block_super, + .fs_flags = FS_REQUIRES_DEV, +}; +#else +static struct super_block *yaffs2_read_super(struct super_block *sb, + void *data, int silent) +{ + return yaffs_internal_read_super(2, sb, data, silent); +} + +static DECLARE_FSTYPE(yaffs2_fs_type, "yaffs2", yaffs2_read_super, + FS_REQUIRES_DEV); +#endif + + +static struct proc_dir_entry *my_proc_entry; + +static char *yaffs_dump_dev_part0(char *buf, struct yaffs_dev *dev) +{ + struct yaffs_param *param = &dev->param; + int bs[10]; + + yaffs_count_blocks_by_state(dev,bs); + + buf += sprintf(buf, "start_block.......... %d\n", param->start_block); + buf += sprintf(buf, "end_block............ %d\n", param->end_block); + buf += sprintf(buf, "total_bytes_per_chunk %d\n", + param->total_bytes_per_chunk); + buf += sprintf(buf, "use_nand_ecc......... %d\n", param->use_nand_ecc); + buf += sprintf(buf, "no_tags_ecc.......... %d\n", param->no_tags_ecc); + buf += sprintf(buf, "is_yaffs2............ %d\n", param->is_yaffs2); + buf += sprintf(buf, "inband_tags.......... %d\n", param->inband_tags); + buf += sprintf(buf, "empty_lost_n_found... %d\n", + param->empty_lost_n_found); + buf += sprintf(buf, "disable_lazy_load.... %d\n", + param->disable_lazy_load); + buf += sprintf(buf, "disable_bad_block_mrk %d\n", + param->disable_bad_block_marking); + buf += sprintf(buf, "refresh_period....... %d\n", + param->refresh_period); + buf += sprintf(buf, "n_caches............. %d\n", param->n_caches); + buf += sprintf(buf, "n_reserved_blocks.... %d\n", + param->n_reserved_blocks); + buf += sprintf(buf, "always_check_erased.. %d\n", + param->always_check_erased); + buf += sprintf(buf, "\n"); + buf += sprintf(buf, "block count by state\n"); + buf += sprintf(buf, "0:%d 1:%d 2:%d 3:%d 4:%d\n", + bs[0], bs[1], bs[2], bs[3], bs[4]); + buf += sprintf(buf, "5:%d 6:%d 7:%d 8:%d 9:%d\n", + bs[5], bs[6], bs[7], bs[8], bs[9]); + + return buf; +} + +static char *yaffs_dump_dev_part1(char *buf, struct yaffs_dev *dev) +{ + buf += sprintf(buf, "max file size....... %lld\n", + (long long) yaffs_max_file_size(dev)); + buf += sprintf(buf, "data_bytes_per_chunk. %d\n", + dev->data_bytes_per_chunk); + buf += sprintf(buf, "chunk_grp_bits....... %d\n", dev->chunk_grp_bits); + buf += sprintf(buf, "chunk_grp_size....... %d\n", dev->chunk_grp_size); + buf += sprintf(buf, "n_erased_blocks...... %d\n", dev->n_erased_blocks); + buf += sprintf(buf, "blocks_in_checkpt.... %d\n", + dev->blocks_in_checkpt); + buf += sprintf(buf, "\n"); + buf += sprintf(buf, "n_tnodes............. %d\n", dev->n_tnodes); + buf += sprintf(buf, "n_obj................ %d\n", dev->n_obj); + buf += sprintf(buf, "n_free_chunks........ %d\n", dev->n_free_chunks); + buf += sprintf(buf, "\n"); + buf += sprintf(buf, "n_page_writes........ %u\n", dev->n_page_writes); + buf += sprintf(buf, "n_page_reads......... %u\n", dev->n_page_reads); + buf += sprintf(buf, "n_erasures........... %u\n", dev->n_erasures); + buf += sprintf(buf, "n_gc_copies.......... %u\n", dev->n_gc_copies); + buf += sprintf(buf, "all_gcs.............. %u\n", dev->all_gcs); + buf += sprintf(buf, "passive_gc_count..... %u\n", + dev->passive_gc_count); + buf += sprintf(buf, "oldest_dirty_gc_count %u\n", + dev->oldest_dirty_gc_count); + buf += sprintf(buf, "n_gc_blocks.......... %u\n", dev->n_gc_blocks); + buf += sprintf(buf, "bg_gcs............... %u\n", dev->bg_gcs); + buf += sprintf(buf, "n_retried_writes..... %u\n", + dev->n_retried_writes); + buf += sprintf(buf, "n_retired_blocks..... %u\n", + dev->n_retired_blocks); + buf += sprintf(buf, "n_ecc_fixed.......... %u\n", dev->n_ecc_fixed); + buf += sprintf(buf, "n_ecc_unfixed........ %u\n", dev->n_ecc_unfixed); + buf += sprintf(buf, "n_tags_ecc_fixed..... %u\n", + dev->n_tags_ecc_fixed); + buf += sprintf(buf, "n_tags_ecc_unfixed... %u\n", + dev->n_tags_ecc_unfixed); + buf += sprintf(buf, "cache_hits........... %u\n", dev->cache_hits); + buf += sprintf(buf, "n_deleted_files...... %u\n", dev->n_deleted_files); + buf += sprintf(buf, "n_unlinked_files..... %u\n", + dev->n_unlinked_files); + buf += sprintf(buf, "refresh_count........ %u\n", dev->refresh_count); + buf += sprintf(buf, "n_bg_deletions....... %u\n", dev->n_bg_deletions); + buf += sprintf(buf, "tags_used............ %u\n", dev->tags_used); + buf += sprintf(buf, "summary_used......... %u\n", dev->summary_used); + + return buf; +} + +static int yaffs_proc_read(char *page, + char **start, + off_t offset, int count, int *eof, void *data) +{ + struct list_head *item; + char *buf = page; + int step = offset; + int n = 0; + + /* Get proc_file_read() to step 'offset' by one on each sucessive call. + * We use 'offset' (*ppos) to indicate where we are in dev_list. + * This also assumes the user has posted a read buffer large + * enough to hold the complete output; but that's life in /proc. + */ + + *(int *)start = 1; + + /* Print header first */ + if (step == 0) + buf += + sprintf(buf, + "Multi-version YAFFS." + "\n"); + else if (step == 1) + buf += sprintf(buf, "\n"); + else { + step -= 2; + + mutex_lock(&yaffs_context_lock); + + /* Locate and print the Nth entry. Order N-squared but N is small. */ + list_for_each(item, &yaffs_context_list) { + struct yaffs_linux_context *dc = + list_entry(item, struct yaffs_linux_context, + context_list); + struct yaffs_dev *dev = dc->dev; + + if (n < (step & ~1)) { + n += 2; + continue; + } + if ((step & 1) == 0) { + buf += + sprintf(buf, "\nDevice %d \"%s\"\n", n, + dev->param.name); + buf = yaffs_dump_dev_part0(buf, dev); + } else { + buf = yaffs_dump_dev_part1(buf, dev); + } + + break; + } + mutex_unlock(&yaffs_context_lock); + } + + return buf - page < count ? buf - page : count; +} + +/** + * Set the verbosity of the warnings and error messages. + * + * Note that the names can only be a..z or _ with the current code. + */ + +static struct { + char *mask_name; + unsigned mask_bitfield; +} mask_flags[] = { + {"allocate", YAFFS_TRACE_ALLOCATE}, + {"always", YAFFS_TRACE_ALWAYS}, + {"background", YAFFS_TRACE_BACKGROUND}, + {"bad_blocks", YAFFS_TRACE_BAD_BLOCKS}, + {"buffers", YAFFS_TRACE_BUFFERS}, + {"bug", YAFFS_TRACE_BUG}, + {"checkpt", YAFFS_TRACE_CHECKPOINT}, + {"deletion", YAFFS_TRACE_DELETION}, + {"erase", YAFFS_TRACE_ERASE}, + {"error", YAFFS_TRACE_ERROR}, + {"gc_detail", YAFFS_TRACE_GC_DETAIL}, + {"gc", YAFFS_TRACE_GC}, + {"lock", YAFFS_TRACE_LOCK}, + {"mtd", YAFFS_TRACE_MTD}, + {"nandaccess", YAFFS_TRACE_NANDACCESS}, + {"os", YAFFS_TRACE_OS}, + {"scan_debug", YAFFS_TRACE_SCAN_DEBUG}, + {"scan", YAFFS_TRACE_SCAN}, + {"mount", YAFFS_TRACE_MOUNT}, + {"tracing", YAFFS_TRACE_TRACING}, + {"sync", YAFFS_TRACE_SYNC}, + {"write", YAFFS_TRACE_WRITE}, + {"verify", YAFFS_TRACE_VERIFY}, + {"verify_nand", YAFFS_TRACE_VERIFY_NAND}, + {"verify_full", YAFFS_TRACE_VERIFY_FULL}, + {"verify_all", YAFFS_TRACE_VERIFY_ALL}, + {"all", 0xffffffff}, + {"none", 0}, + {NULL, 0}, +}; + +#define MAX_MASK_NAME_LENGTH 40 +static int yaffs_proc_write_trace_options(struct file *file, const char *buf, + unsigned long count) +{ + unsigned rg = 0, mask_bitfield; + char *end; + char *mask_name; + const char *x; + char substring[MAX_MASK_NAME_LENGTH + 1]; + int i; + int done = 0; + int add, len = 0; + int pos = 0; + + rg = yaffs_trace_mask; + + while (!done && (pos < count)) { + done = 1; + while ((pos < count) && isspace(buf[pos])) + pos++; + + switch (buf[pos]) { + case '+': + case '-': + case '=': + add = buf[pos]; + pos++; + break; + + default: + add = ' '; + break; + } + mask_name = NULL; + + mask_bitfield = simple_strtoul(buf + pos, &end, 0); + + if (end > buf + pos) { + mask_name = "numeral"; + len = end - (buf + pos); + pos += len; + done = 0; + } else { + for (x = buf + pos, i = 0; + (*x == '_' || (*x >= 'a' && *x <= 'z')) && + i < MAX_MASK_NAME_LENGTH; x++, i++, pos++) + substring[i] = *x; + substring[i] = '\0'; + + for (i = 0; mask_flags[i].mask_name != NULL; i++) { + if (strcmp(substring, mask_flags[i].mask_name) + == 0) { + mask_name = mask_flags[i].mask_name; + mask_bitfield = + mask_flags[i].mask_bitfield; + done = 0; + break; + } + } + } + + if (mask_name != NULL) { + done = 0; + switch (add) { + case '-': + rg &= ~mask_bitfield; + break; + case '+': + rg |= mask_bitfield; + break; + case '=': + rg = mask_bitfield; + break; + default: + rg |= mask_bitfield; + break; + } + } + } + + yaffs_trace_mask = rg | YAFFS_TRACE_ALWAYS; + + printk(KERN_DEBUG "new trace = 0x%08X\n", yaffs_trace_mask); + + if (rg & YAFFS_TRACE_ALWAYS) { + for (i = 0; mask_flags[i].mask_name != NULL; i++) { + char flag; + flag = ((rg & mask_flags[i].mask_bitfield) == + mask_flags[i].mask_bitfield) ? '+' : '-'; + printk(KERN_DEBUG "%c%s\n", flag, + mask_flags[i].mask_name); + } + } + + return count; +} + +/* Debug strings are of the form: + * .bnnn print info on block n + * .cobjn,chunkn print nand chunk id for objn:chunkn + */ + +static int yaffs_proc_debug_write(struct file *file, const char *buf, + unsigned long count) +{ + + char str[100]; + char *p0; + char *p1; + long p1_val; + long p0_val; + char cmd; + struct list_head *item; + + memset(str, 0, sizeof(str)); + memcpy(str, buf, min((size_t)count, sizeof(str) -1)); + + cmd = str[1]; + + p0 = str + 2; + + p1 = p0; + + while (*p1 && *p1 != ',') { + p1++; + } + *p1 = '\0'; + p1++; + + p0_val = simple_strtol(p0, NULL, 0); + p1_val = simple_strtol(p1, NULL, 0); + + + mutex_lock(&yaffs_context_lock); + + /* Locate and print the Nth entry. Order N-squared but N is small. */ + list_for_each(item, &yaffs_context_list) { + struct yaffs_linux_context *dc = + list_entry(item, struct yaffs_linux_context, + context_list); + struct yaffs_dev *dev = dc->dev; + + if (cmd == 'b') { + struct yaffs_block_info *bi; + + bi = yaffs_get_block_info(dev,p0_val); + + if(bi) { + printk("Block %d: state %d, retire %d, use %d, seq %d\n", + (int)p0_val, bi->block_state, + bi->needs_retiring, bi->pages_in_use, + bi->seq_number); + } + } else if (cmd == 'c') { + struct yaffs_obj *obj; + int nand_chunk; + + obj = yaffs_find_by_number(dev, p0_val); + if (!obj) + printk("No obj %d\n", (int)p0_val); + else { + if(p1_val == 0) + nand_chunk = obj->hdr_chunk; + else + nand_chunk = + yaffs_find_chunk_in_file(obj, + p1_val, NULL); + printk("Nand chunk for %d:%d is %d\n", + (int)p0_val, (int)p1_val, nand_chunk); + } + } + } + + mutex_unlock(&yaffs_context_lock); + + return count; +} + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) +static int yaffs_proc_write(struct file *file, const char *buf, + unsigned long count, void *ppos) +#else +static ssize_t yaffs_proc_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +#endif +{ + if (buf[0] == '.') + return yaffs_proc_debug_write(file, buf, count); + return yaffs_proc_write_trace_options(file, buf, count); +} + +/* Stuff to handle installation of file systems */ +struct file_system_to_install { + struct file_system_type *fst; + int installed; +}; + +static struct file_system_to_install fs_to_install[] = { + {&yaffs_fs_type, 0}, + {&yaffs2_fs_type, 0}, + {NULL, 0} +}; + + +#ifdef YAFFS_NEW_PROCFS +static int yaffs_proc_show(struct seq_file *m, void *v) +{ + /* FIXME: Unify in a better way? */ + char buffer[512]; + char *start; + int len; + + len = yaffs_proc_read(buffer, &start, 0, sizeof(buffer), NULL, NULL); + seq_puts(m, buffer); + return 0; +} + +static int yaffs_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, yaffs_proc_show, NULL); +} + +static struct file_operations procfs_ops = { + .owner = THIS_MODULE, + .open = yaffs_proc_open, + .read = seq_read, + .write = yaffs_proc_write, +}; + +static int yaffs_procfs_init(void) +{ + /* Install the proc_fs entries */ + my_proc_entry = proc_create("yaffs", + S_IRUGO | S_IFREG, + YPROC_ROOT, + &procfs_ops); + + if (my_proc_entry) { + return 0; + } else { + return -ENOMEM; + } +} + +#else + + +static int yaffs_procfs_init(void) +{ + /* Install the proc_fs entries */ + my_proc_entry = create_proc_entry("yaffs", + S_IRUGO | S_IFREG, YPROC_ROOT); + + if (my_proc_entry) { + my_proc_entry->write_proc = yaffs_proc_write; + my_proc_entry->read_proc = yaffs_proc_read; + my_proc_entry->data = NULL; + return 0; + } else { + return -ENOMEM; + } +} + +#endif + + +static int __init init_yaffs_fs(void) +{ + int error = 0; + struct file_system_to_install *fsinst; + + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs Installing."); + + mutex_init(&yaffs_context_lock); + + error = yaffs_procfs_init(); + if (error) + return error; + + /* Now add the file system entries */ + + fsinst = fs_to_install; + + while (fsinst->fst && !error) { + error = register_filesystem(fsinst->fst); + if (!error) + fsinst->installed = 1; + fsinst++; + } + + /* Any errors? uninstall */ + if (error) { + fsinst = fs_to_install; + + while (fsinst->fst) { + if (fsinst->installed) { + unregister_filesystem(fsinst->fst); + fsinst->installed = 0; + } + fsinst++; + } + } + + return error; +} + +static void __exit exit_yaffs_fs(void) +{ + + struct file_system_to_install *fsinst; + + yaffs_trace(YAFFS_TRACE_ALWAYS, + "yaffs removing."); + + remove_proc_entry("yaffs", YPROC_ROOT); + + fsinst = fs_to_install; + + while (fsinst->fst) { + if (fsinst->installed) { + unregister_filesystem(fsinst->fst); + fsinst->installed = 0; + } + fsinst++; + } +} + +module_init(init_yaffs_fs) + module_exit(exit_yaffs_fs) + + MODULE_DESCRIPTION("YAFFS2 - a NAND specific flash file system"); +MODULE_AUTHOR("Charles Manning, Aleph One Ltd., 2002-2011"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_yaffs1.c b/target/linux/generic/files/fs/yaffs2/yaffs_yaffs1.c new file mode 100644 index 0000000..d277e20 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_yaffs1.c @@ -0,0 +1,422 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_yaffs1.h" +#include "yportenv.h" +#include "yaffs_trace.h" +#include "yaffs_bitmap.h" +#include "yaffs_getblockinfo.h" +#include "yaffs_nand.h" +#include "yaffs_attribs.h" + +int yaffs1_scan(struct yaffs_dev *dev) +{ + struct yaffs_ext_tags tags; + int blk; + int result; + int chunk; + int c; + int deleted; + enum yaffs_block_state state; + LIST_HEAD(hard_list); + struct yaffs_block_info *bi; + u32 seq_number; + struct yaffs_obj_hdr *oh; + struct yaffs_obj *in; + struct yaffs_obj *parent; + int alloc_failed = 0; + struct yaffs_shadow_fixer *shadow_fixers = NULL; + u8 *chunk_data; + + yaffs_trace(YAFFS_TRACE_SCAN, + "yaffs1_scan starts intstartblk %d intendblk %d...", + dev->internal_start_block, dev->internal_end_block); + + chunk_data = yaffs_get_temp_buffer(dev); + + dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER; + + /* Scan all the blocks to determine their state */ + bi = dev->block_info; + for (blk = dev->internal_start_block; blk <= dev->internal_end_block; + blk++) { + yaffs_clear_chunk_bits(dev, blk); + bi->pages_in_use = 0; + bi->soft_del_pages = 0; + + yaffs_query_init_block_state(dev, blk, &state, &seq_number); + + bi->block_state = state; + bi->seq_number = seq_number; + + if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK) + bi->block_state = state = YAFFS_BLOCK_STATE_DEAD; + + yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, + "Block scanning block %d state %d seq %d", + blk, state, seq_number); + + if (state == YAFFS_BLOCK_STATE_DEAD) { + yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, + "block %d is bad", blk); + } else if (state == YAFFS_BLOCK_STATE_EMPTY) { + yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "Block empty "); + dev->n_erased_blocks++; + dev->n_free_chunks += dev->param.chunks_per_block; + } + bi++; + } + + /* For each block.... */ + for (blk = dev->internal_start_block; + !alloc_failed && blk <= dev->internal_end_block; blk++) { + + cond_resched(); + + bi = yaffs_get_block_info(dev, blk); + state = bi->block_state; + + deleted = 0; + + /* For each chunk in each block that needs scanning.... */ + for (c = 0; + !alloc_failed && c < dev->param.chunks_per_block && + state == YAFFS_BLOCK_STATE_NEEDS_SCAN; c++) { + /* Read the tags and decide what to do */ + chunk = blk * dev->param.chunks_per_block + c; + + result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, + &tags); + + /* Let's have a good look at this chunk... */ + + if (tags.ecc_result == YAFFS_ECC_RESULT_UNFIXED || + tags.is_deleted) { + /* YAFFS1 only... + * A deleted chunk + */ + deleted++; + dev->n_free_chunks++; + } else if (!tags.chunk_used) { + /* An unassigned chunk in the block + * This means that either the block is empty or + * this is the one being allocated from + */ + + if (c == 0) { + /* We're looking at the first chunk in + *the block so the block is unused */ + state = YAFFS_BLOCK_STATE_EMPTY; + dev->n_erased_blocks++; + } else { + /* this is the block being allocated */ + yaffs_trace(YAFFS_TRACE_SCAN, + " Allocating from %d %d", + blk, c); + state = YAFFS_BLOCK_STATE_ALLOCATING; + dev->alloc_block = blk; + dev->alloc_page = c; + dev->alloc_block_finder = blk; + + } + + dev->n_free_chunks += + (dev->param.chunks_per_block - c); + } else if (tags.chunk_id > 0) { + /* chunk_id > 0 so it is a data chunk... */ + unsigned int endpos; + + yaffs_set_chunk_bit(dev, blk, c); + bi->pages_in_use++; + + in = yaffs_find_or_create_by_number(dev, + tags.obj_id, + YAFFS_OBJECT_TYPE_FILE); + /* PutChunkIntoFile checks for a clash + * (two data chunks with the same chunk_id). + */ + + if (!in) + alloc_failed = 1; + + if (in) { + if (!yaffs_put_chunk_in_file + (in, tags.chunk_id, chunk, 1)) + alloc_failed = 1; + } + + endpos = + (tags.chunk_id - 1) * + dev->data_bytes_per_chunk + + tags.n_bytes; + if (in && + in->variant_type == + YAFFS_OBJECT_TYPE_FILE && + in->variant.file_variant.scanned_size < + endpos) { + in->variant.file_variant.scanned_size = + endpos; + if (!dev->param.use_header_file_size) { + in->variant. + file_variant.file_size = + in->variant. + file_variant.scanned_size; + } + + } + } else { + /* chunk_id == 0, so it is an ObjectHeader. + * Make the object + */ + yaffs_set_chunk_bit(dev, blk, c); + bi->pages_in_use++; + + result = yaffs_rd_chunk_tags_nand(dev, chunk, + chunk_data, + NULL); + + oh = (struct yaffs_obj_hdr *)chunk_data; + + in = yaffs_find_by_number(dev, tags.obj_id); + if (in && in->variant_type != oh->type) { + /* This should not happen, but somehow + * Wev'e ended up with an obj_id that + * has been reused but not yet deleted, + * and worse still it has changed type. + * Delete the old object. + */ + + yaffs_del_obj(in); + in = NULL; + } + + in = yaffs_find_or_create_by_number(dev, + tags.obj_id, + oh->type); + + if (!in) + alloc_failed = 1; + + if (in && oh->shadows_obj > 0) { + + struct yaffs_shadow_fixer *fixer; + fixer = + kmalloc(sizeof + (struct yaffs_shadow_fixer), + GFP_NOFS); + if (fixer) { + fixer->next = shadow_fixers; + shadow_fixers = fixer; + fixer->obj_id = tags.obj_id; + fixer->shadowed_id = + oh->shadows_obj; + yaffs_trace(YAFFS_TRACE_SCAN, + " Shadow fixer: %d shadows %d", + fixer->obj_id, + fixer->shadowed_id); + + } + + } + + if (in && in->valid) { + /* We have already filled this one. + * We have a duplicate and need to + * resolve it. */ + + unsigned existing_serial = in->serial; + unsigned new_serial = + tags.serial_number; + + if (((existing_serial + 1) & 3) == + new_serial) { + /* Use new one - destroy the + * exisiting one */ + yaffs_chunk_del(dev, + in->hdr_chunk, + 1, __LINE__); + in->valid = 0; + } else { + /* Use existing - destroy + * this one. */ + yaffs_chunk_del(dev, chunk, 1, + __LINE__); + } + } + + if (in && !in->valid && + (tags.obj_id == YAFFS_OBJECTID_ROOT || + tags.obj_id == + YAFFS_OBJECTID_LOSTNFOUND)) { + /* We only load some info, don't fiddle + * with directory structure */ + in->valid = 1; + in->variant_type = oh->type; + + in->yst_mode = oh->yst_mode; + yaffs_load_attribs(in, oh); + in->hdr_chunk = chunk; + in->serial = tags.serial_number; + + } else if (in && !in->valid) { + /* we need to load this info */ + + in->valid = 1; + in->variant_type = oh->type; + + in->yst_mode = oh->yst_mode; + yaffs_load_attribs(in, oh); + in->hdr_chunk = chunk; + in->serial = tags.serial_number; + + yaffs_set_obj_name_from_oh(in, oh); + in->dirty = 0; + + /* directory stuff... + * hook up to parent + */ + + parent = + yaffs_find_or_create_by_number + (dev, oh->parent_obj_id, + YAFFS_OBJECT_TYPE_DIRECTORY); + if (!parent) + alloc_failed = 1; + if (parent && parent->variant_type == + YAFFS_OBJECT_TYPE_UNKNOWN) { + /* Set up as a directory */ + parent->variant_type = + YAFFS_OBJECT_TYPE_DIRECTORY; + INIT_LIST_HEAD(&parent-> + variant.dir_variant. + children); + } else if (!parent || + parent->variant_type != + YAFFS_OBJECT_TYPE_DIRECTORY) { + /* Hoosterman, a problem.... + * We're trying to use a + * non-directory as a directory + */ + + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." + ); + parent = dev->lost_n_found; + } + + yaffs_add_obj_to_dir(parent, in); + + switch (in->variant_type) { + case YAFFS_OBJECT_TYPE_UNKNOWN: + /* Todo got a problem */ + break; + case YAFFS_OBJECT_TYPE_FILE: + if (dev->param. + use_header_file_size) + in->variant. + file_variant.file_size + = yaffs_oh_to_size(oh); + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + in->variant. + hardlink_variant.equiv_id = + oh->equiv_id; + list_add(&in->hard_links, + &hard_list); + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + /* Do nothing */ + break; + case YAFFS_OBJECT_TYPE_SPECIAL: + /* Do nothing */ + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + in->variant.symlink_variant. + alias = + yaffs_clone_str(oh->alias); + if (!in->variant. + symlink_variant.alias) + alloc_failed = 1; + break; + } + } + } + } + + if (state == YAFFS_BLOCK_STATE_NEEDS_SCAN) { + /* If we got this far while scanning, + * then the block is fully allocated. */ + state = YAFFS_BLOCK_STATE_FULL; + } + + if (state == YAFFS_BLOCK_STATE_ALLOCATING) { + /* If the block was partially allocated then + * treat it as fully allocated. */ + state = YAFFS_BLOCK_STATE_FULL; + dev->alloc_block = -1; + } + + bi->block_state = state; + + /* Now let's see if it was dirty */ + if (bi->pages_in_use == 0 && + !bi->has_shrink_hdr && + bi->block_state == YAFFS_BLOCK_STATE_FULL) + yaffs_block_became_dirty(dev, blk); + } + + /* Ok, we've done all the scanning. + * Fix up the hard link chains. + * We should now have scanned all the objects, now it's time to add + * these hardlinks. + */ + + yaffs_link_fixup(dev, &hard_list); + + /* + * Fix up any shadowed objects. + * There should not be more than one of these. + */ + { + struct yaffs_shadow_fixer *fixer; + struct yaffs_obj *obj; + + while (shadow_fixers) { + fixer = shadow_fixers; + shadow_fixers = fixer->next; + /* Complete the rename transaction by deleting the + * shadowed object then setting the object header + to unshadowed. + */ + obj = yaffs_find_by_number(dev, fixer->shadowed_id); + if (obj) + yaffs_del_obj(obj); + + obj = yaffs_find_by_number(dev, fixer->obj_id); + + if (obj) + yaffs_update_oh(obj, NULL, 1, 0, 0, NULL); + + kfree(fixer); + } + } + + yaffs_release_temp_buffer(dev, chunk_data); + + if (alloc_failed) + return YAFFS_FAIL; + + yaffs_trace(YAFFS_TRACE_SCAN, "yaffs1_scan ends"); + + return YAFFS_OK; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_yaffs1.h b/target/linux/generic/files/fs/yaffs2/yaffs_yaffs1.h new file mode 100644 index 0000000..97e2fdd --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_yaffs1.h @@ -0,0 +1,22 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_YAFFS1_H__ +#define __YAFFS_YAFFS1_H__ + +#include "yaffs_guts.h" +int yaffs1_scan(struct yaffs_dev *dev); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_yaffs2.c b/target/linux/generic/files/fs/yaffs2/yaffs_yaffs2.c new file mode 100644 index 0000000..9fb7c94 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_yaffs2.c @@ -0,0 +1,1532 @@ +/* + * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "yaffs_guts.h" +#include "yaffs_trace.h" +#include "yaffs_yaffs2.h" +#include "yaffs_checkptrw.h" +#include "yaffs_bitmap.h" +#include "yaffs_nand.h" +#include "yaffs_getblockinfo.h" +#include "yaffs_verify.h" +#include "yaffs_attribs.h" +#include "yaffs_summary.h" + +/* + * Checkpoints are really no benefit on very small partitions. + * + * To save space on small partitions don't bother with checkpoints unless + * the partition is at least this big. + */ +#define YAFFS_CHECKPOINT_MIN_BLOCKS 60 +#define YAFFS_SMALL_HOLE_THRESHOLD 4 + +/* + * Oldest Dirty Sequence Number handling. + */ + +/* yaffs_calc_oldest_dirty_seq() + * yaffs2_find_oldest_dirty_seq() + * Calculate the oldest dirty sequence number if we don't know it. + */ +void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev) +{ + int i; + unsigned seq; + unsigned block_no = 0; + struct yaffs_block_info *b; + + if (!dev->param.is_yaffs2) + return; + + /* Find the oldest dirty sequence number. */ + seq = dev->seq_number + 1; + b = dev->block_info; + for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { + if (b->block_state == YAFFS_BLOCK_STATE_FULL && + (b->pages_in_use - b->soft_del_pages) < + dev->param.chunks_per_block && + b->seq_number < seq) { + seq = b->seq_number; + block_no = i; + } + b++; + } + + if (block_no) { + dev->oldest_dirty_seq = seq; + dev->oldest_dirty_block = block_no; + } +} + +void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev) +{ + if (!dev->param.is_yaffs2) + return; + + if (!dev->oldest_dirty_seq) + yaffs_calc_oldest_dirty_seq(dev); +} + +/* + * yaffs_clear_oldest_dirty_seq() + * Called when a block is erased or marked bad. (ie. when its seq_number + * becomes invalid). If the value matches the oldest then we clear + * dev->oldest_dirty_seq to force its recomputation. + */ +void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev, + struct yaffs_block_info *bi) +{ + + if (!dev->param.is_yaffs2) + return; + + if (!bi || bi->seq_number == dev->oldest_dirty_seq) { + dev->oldest_dirty_seq = 0; + dev->oldest_dirty_block = 0; + } +} + +/* + * yaffs2_update_oldest_dirty_seq() + * Update the oldest dirty sequence number whenever we dirty a block. + * Only do this if the oldest_dirty_seq is actually being tracked. + */ +void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no, + struct yaffs_block_info *bi) +{ + if (!dev->param.is_yaffs2) + return; + + if (dev->oldest_dirty_seq) { + if (dev->oldest_dirty_seq > bi->seq_number) { + dev->oldest_dirty_seq = bi->seq_number; + dev->oldest_dirty_block = block_no; + } + } +} + +int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi) +{ + + if (!dev->param.is_yaffs2) + return 1; /* disqualification only applies to yaffs2. */ + + if (!bi->has_shrink_hdr) + return 1; /* can gc */ + + yaffs2_find_oldest_dirty_seq(dev); + + /* Can't do gc of this block if there are any blocks older than this + * one that have discarded pages. + */ + return (bi->seq_number <= dev->oldest_dirty_seq); +} + +/* + * yaffs2_find_refresh_block() + * periodically finds the oldest full block by sequence number for refreshing. + * Only for yaffs2. + */ +u32 yaffs2_find_refresh_block(struct yaffs_dev *dev) +{ + u32 b; + u32 oldest = 0; + u32 oldest_seq = 0; + struct yaffs_block_info *bi; + + if (!dev->param.is_yaffs2) + return oldest; + + /* + * If refresh period < 10 then refreshing is disabled. + */ + if (dev->param.refresh_period < 10) + return oldest; + + /* + * Fix broken values. + */ + if (dev->refresh_skip > dev->param.refresh_period) + dev->refresh_skip = dev->param.refresh_period; + + if (dev->refresh_skip > 0) + return oldest; + + /* + * Refresh skip is now zero. + * We'll do a refresh this time around.... + * Update the refresh skip and find the oldest block. + */ + dev->refresh_skip = dev->param.refresh_period; + dev->refresh_count++; + bi = dev->block_info; + for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) { + + if (bi->block_state == YAFFS_BLOCK_STATE_FULL) { + + if (oldest < 1 || bi->seq_number < oldest_seq) { + oldest = b; + oldest_seq = bi->seq_number; + } + } + bi++; + } + + if (oldest > 0) { + yaffs_trace(YAFFS_TRACE_GC, + "GC refresh count %d selected block %d with seq_number %d", + dev->refresh_count, oldest, oldest_seq); + } + + return oldest; +} + +int yaffs2_checkpt_required(struct yaffs_dev *dev) +{ + int nblocks; + + if (!dev->param.is_yaffs2) + return 0; + + nblocks = dev->internal_end_block - dev->internal_start_block + 1; + + return !dev->param.skip_checkpt_wr && + !dev->read_only && (nblocks >= YAFFS_CHECKPOINT_MIN_BLOCKS); +} + +int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev) +{ + int retval; + int n_bytes = 0; + int n_blocks; + int dev_blocks; + + if (!dev->param.is_yaffs2) + return 0; + + if (!dev->checkpoint_blocks_required && yaffs2_checkpt_required(dev)) { + /* Not a valid value so recalculate */ + dev_blocks = dev->param.end_block - dev->param.start_block + 1; + n_bytes += sizeof(struct yaffs_checkpt_validity); + n_bytes += sizeof(struct yaffs_checkpt_dev); + n_bytes += dev_blocks * sizeof(struct yaffs_block_info); + n_bytes += dev_blocks * dev->chunk_bit_stride; + n_bytes += + (sizeof(struct yaffs_checkpt_obj) + sizeof(u32)) * + dev->n_obj; + n_bytes += (dev->tnode_size + sizeof(u32)) * dev->n_tnodes; + n_bytes += sizeof(struct yaffs_checkpt_validity); + n_bytes += sizeof(u32); /* checksum */ + + /* Round up and add 2 blocks to allow for some bad blocks, + * so add 3 */ + + n_blocks = + (n_bytes / + (dev->data_bytes_per_chunk * + dev->param.chunks_per_block)) + 3; + + dev->checkpoint_blocks_required = n_blocks; + } + + retval = dev->checkpoint_blocks_required - dev->blocks_in_checkpt; + if (retval < 0) + retval = 0; + return retval; +} + +/*--------------------- Checkpointing --------------------*/ + +static int yaffs2_wr_checkpt_validity_marker(struct yaffs_dev *dev, int head) +{ + struct yaffs_checkpt_validity cp; + + memset(&cp, 0, sizeof(cp)); + + cp.struct_type = sizeof(cp); + cp.magic = YAFFS_MAGIC; + cp.version = YAFFS_CHECKPOINT_VERSION; + cp.head = (head) ? 1 : 0; + + return (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)) ? 1 : 0; +} + +static int yaffs2_rd_checkpt_validity_marker(struct yaffs_dev *dev, int head) +{ + struct yaffs_checkpt_validity cp; + int ok; + + ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); + + if (ok) + ok = (cp.struct_type == sizeof(cp)) && + (cp.magic == YAFFS_MAGIC) && + (cp.version == YAFFS_CHECKPOINT_VERSION) && + (cp.head == ((head) ? 1 : 0)); + return ok ? 1 : 0; +} + +static void yaffs2_dev_to_checkpt_dev(struct yaffs_checkpt_dev *cp, + struct yaffs_dev *dev) +{ + cp->n_erased_blocks = dev->n_erased_blocks; + cp->alloc_block = dev->alloc_block; + cp->alloc_page = dev->alloc_page; + cp->n_free_chunks = dev->n_free_chunks; + + cp->n_deleted_files = dev->n_deleted_files; + cp->n_unlinked_files = dev->n_unlinked_files; + cp->n_bg_deletions = dev->n_bg_deletions; + cp->seq_number = dev->seq_number; + +} + +static void yaffs_checkpt_dev_to_dev(struct yaffs_dev *dev, + struct yaffs_checkpt_dev *cp) +{ + dev->n_erased_blocks = cp->n_erased_blocks; + dev->alloc_block = cp->alloc_block; + dev->alloc_page = cp->alloc_page; + dev->n_free_chunks = cp->n_free_chunks; + + dev->n_deleted_files = cp->n_deleted_files; + dev->n_unlinked_files = cp->n_unlinked_files; + dev->n_bg_deletions = cp->n_bg_deletions; + dev->seq_number = cp->seq_number; +} + +static int yaffs2_wr_checkpt_dev(struct yaffs_dev *dev) +{ + struct yaffs_checkpt_dev cp; + u32 n_bytes; + u32 n_blocks = dev->internal_end_block - dev->internal_start_block + 1; + int ok; + + /* Write device runtime values */ + yaffs2_dev_to_checkpt_dev(&cp, dev); + cp.struct_type = sizeof(cp); + + ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)); + if (!ok) + return 0; + + /* Write block info */ + n_bytes = n_blocks * sizeof(struct yaffs_block_info); + ok = (yaffs2_checkpt_wr(dev, dev->block_info, n_bytes) == n_bytes); + if (!ok) + return 0; + + /* Write chunk bits */ + n_bytes = n_blocks * dev->chunk_bit_stride; + ok = (yaffs2_checkpt_wr(dev, dev->chunk_bits, n_bytes) == n_bytes); + + return ok ? 1 : 0; +} + +static int yaffs2_rd_checkpt_dev(struct yaffs_dev *dev) +{ + struct yaffs_checkpt_dev cp; + u32 n_bytes; + u32 n_blocks = + (dev->internal_end_block - dev->internal_start_block + 1); + int ok; + + ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); + if (!ok) + return 0; + + if (cp.struct_type != sizeof(cp)) + return 0; + + yaffs_checkpt_dev_to_dev(dev, &cp); + + n_bytes = n_blocks * sizeof(struct yaffs_block_info); + + ok = (yaffs2_checkpt_rd(dev, dev->block_info, n_bytes) == n_bytes); + + if (!ok) + return 0; + + n_bytes = n_blocks * dev->chunk_bit_stride; + + ok = (yaffs2_checkpt_rd(dev, dev->chunk_bits, n_bytes) == n_bytes); + + return ok ? 1 : 0; +} + +static void yaffs2_obj_checkpt_obj(struct yaffs_checkpt_obj *cp, + struct yaffs_obj *obj) +{ + cp->obj_id = obj->obj_id; + cp->parent_id = (obj->parent) ? obj->parent->obj_id : 0; + cp->hdr_chunk = obj->hdr_chunk; + cp->variant_type = obj->variant_type; + cp->deleted = obj->deleted; + cp->soft_del = obj->soft_del; + cp->unlinked = obj->unlinked; + cp->fake = obj->fake; + cp->rename_allowed = obj->rename_allowed; + cp->unlink_allowed = obj->unlink_allowed; + cp->serial = obj->serial; + cp->n_data_chunks = obj->n_data_chunks; + + if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) + cp->size_or_equiv_obj = obj->variant.file_variant.file_size; + else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) + cp->size_or_equiv_obj = obj->variant.hardlink_variant.equiv_id; +} + +static int yaffs2_checkpt_obj_to_obj(struct yaffs_obj *obj, + struct yaffs_checkpt_obj *cp) +{ + struct yaffs_obj *parent; + + if (obj->variant_type != cp->variant_type) { + yaffs_trace(YAFFS_TRACE_ERROR, + "Checkpoint read object %d type %d chunk %d does not match existing object type %d", + cp->obj_id, cp->variant_type, cp->hdr_chunk, + obj->variant_type); + return 0; + } + + obj->obj_id = cp->obj_id; + + if (cp->parent_id) + parent = yaffs_find_or_create_by_number(obj->my_dev, + cp->parent_id, + YAFFS_OBJECT_TYPE_DIRECTORY); + else + parent = NULL; + + if (parent) { + if (parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { + yaffs_trace(YAFFS_TRACE_ALWAYS, + "Checkpoint read object %d parent %d type %d chunk %d Parent type, %d, not directory", + cp->obj_id, cp->parent_id, + cp->variant_type, cp->hdr_chunk, + parent->variant_type); + return 0; + } + yaffs_add_obj_to_dir(parent, obj); + } + + obj->hdr_chunk = cp->hdr_chunk; + obj->variant_type = cp->variant_type; + obj->deleted = cp->deleted; + obj->soft_del = cp->soft_del; + obj->unlinked = cp->unlinked; + obj->fake = cp->fake; + obj->rename_allowed = cp->rename_allowed; + obj->unlink_allowed = cp->unlink_allowed; + obj->serial = cp->serial; + obj->n_data_chunks = cp->n_data_chunks; + + if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) + obj->variant.file_variant.file_size = cp->size_or_equiv_obj; + else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) + obj->variant.hardlink_variant.equiv_id = cp->size_or_equiv_obj; + + if (obj->hdr_chunk > 0) + obj->lazy_loaded = 1; + return 1; +} + +static int yaffs2_checkpt_tnode_worker(struct yaffs_obj *in, + struct yaffs_tnode *tn, u32 level, + int chunk_offset) +{ + int i; + struct yaffs_dev *dev = in->my_dev; + int ok = 1; + u32 base_offset; + + if (!tn) + return 1; + + if (level > 0) { + for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) { + if (!tn->internal[i]) + continue; + ok = yaffs2_checkpt_tnode_worker(in, + tn->internal[i], + level - 1, + (chunk_offset << + YAFFS_TNODES_INTERNAL_BITS) + i); + } + return ok; + } + + /* Level 0 tnode */ + base_offset = chunk_offset << YAFFS_TNODES_LEVEL0_BITS; + ok = (yaffs2_checkpt_wr(dev, &base_offset, sizeof(base_offset)) == + sizeof(base_offset)); + if (ok) + ok = (yaffs2_checkpt_wr(dev, tn, dev->tnode_size) == + dev->tnode_size); + + return ok; +} + +static int yaffs2_wr_checkpt_tnodes(struct yaffs_obj *obj) +{ + u32 end_marker = ~0; + int ok = 1; + + if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE) + return ok; + + ok = yaffs2_checkpt_tnode_worker(obj, + obj->variant.file_variant.top, + obj->variant.file_variant. + top_level, 0); + if (ok) + ok = (yaffs2_checkpt_wr(obj->my_dev, &end_marker, + sizeof(end_marker)) == sizeof(end_marker)); + + return ok ? 1 : 0; +} + +static int yaffs2_rd_checkpt_tnodes(struct yaffs_obj *obj) +{ + u32 base_chunk; + int ok = 1; + struct yaffs_dev *dev = obj->my_dev; + struct yaffs_file_var *file_stuct_ptr = &obj->variant.file_variant; + struct yaffs_tnode *tn; + int nread = 0; + + ok = (yaffs2_checkpt_rd(dev, &base_chunk, sizeof(base_chunk)) == + sizeof(base_chunk)); + + while (ok && (~base_chunk)) { + nread++; + /* Read level 0 tnode */ + + tn = yaffs_get_tnode(dev); + if (tn) + ok = (yaffs2_checkpt_rd(dev, tn, dev->tnode_size) == + dev->tnode_size); + else + ok = 0; + + if (tn && ok) + ok = yaffs_add_find_tnode_0(dev, + file_stuct_ptr, + base_chunk, tn) ? 1 : 0; + + if (ok) + ok = (yaffs2_checkpt_rd + (dev, &base_chunk, + sizeof(base_chunk)) == sizeof(base_chunk)); + } + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "Checkpoint read tnodes %d records, last %d. ok %d", + nread, base_chunk, ok); + + return ok ? 1 : 0; +} + +static int yaffs2_wr_checkpt_objs(struct yaffs_dev *dev) +{ + struct yaffs_obj *obj; + struct yaffs_checkpt_obj cp; + int i; + int ok = 1; + struct list_head *lh; + + /* Iterate through the objects in each hash entry, + * dumping them to the checkpointing stream. + */ + + for (i = 0; ok && i < YAFFS_NOBJECT_BUCKETS; i++) { + list_for_each(lh, &dev->obj_bucket[i].list) { + obj = list_entry(lh, struct yaffs_obj, hash_link); + if (!obj->defered_free) { + yaffs2_obj_checkpt_obj(&cp, obj); + cp.struct_type = sizeof(cp); + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "Checkpoint write object %d parent %d type %d chunk %d obj addr %p", + cp.obj_id, cp.parent_id, + cp.variant_type, cp.hdr_chunk, obj); + + ok = (yaffs2_checkpt_wr(dev, &cp, + sizeof(cp)) == sizeof(cp)); + + if (ok && + obj->variant_type == + YAFFS_OBJECT_TYPE_FILE) + ok = yaffs2_wr_checkpt_tnodes(obj); + } + } + } + + /* Dump end of list */ + memset(&cp, 0xff, sizeof(struct yaffs_checkpt_obj)); + cp.struct_type = sizeof(cp); + + if (ok) + ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)); + + return ok ? 1 : 0; +} + +static int yaffs2_rd_checkpt_objs(struct yaffs_dev *dev) +{ + struct yaffs_obj *obj; + struct yaffs_checkpt_obj cp; + int ok = 1; + int done = 0; + LIST_HEAD(hard_list); + + + while (ok && !done) { + ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); + if (cp.struct_type != sizeof(cp)) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "struct size %d instead of %d ok %d", + cp.struct_type, (int)sizeof(cp), ok); + ok = 0; + } + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "Checkpoint read object %d parent %d type %d chunk %d ", + cp.obj_id, cp.parent_id, cp.variant_type, + cp.hdr_chunk); + + if (ok && cp.obj_id == ~0) { + done = 1; + } else if (ok) { + obj = + yaffs_find_or_create_by_number(dev, cp.obj_id, + cp.variant_type); + if (obj) { + ok = yaffs2_checkpt_obj_to_obj(obj, &cp); + if (!ok) + break; + if (obj->variant_type == + YAFFS_OBJECT_TYPE_FILE) { + ok = yaffs2_rd_checkpt_tnodes(obj); + } else if (obj->variant_type == + YAFFS_OBJECT_TYPE_HARDLINK) { + list_add(&obj->hard_links, &hard_list); + } + } else { + ok = 0; + } + } + } + + if (ok) + yaffs_link_fixup(dev, &hard_list); + + return ok ? 1 : 0; +} + +static int yaffs2_wr_checkpt_sum(struct yaffs_dev *dev) +{ + u32 checkpt_sum; + int ok; + + yaffs2_get_checkpt_sum(dev, &checkpt_sum); + + ok = (yaffs2_checkpt_wr(dev, &checkpt_sum, sizeof(checkpt_sum)) == + sizeof(checkpt_sum)); + + if (!ok) + return 0; + + return 1; +} + +static int yaffs2_rd_checkpt_sum(struct yaffs_dev *dev) +{ + u32 checkpt_sum0; + u32 checkpt_sum1; + int ok; + + yaffs2_get_checkpt_sum(dev, &checkpt_sum0); + + ok = (yaffs2_checkpt_rd(dev, &checkpt_sum1, sizeof(checkpt_sum1)) == + sizeof(checkpt_sum1)); + + if (!ok) + return 0; + + if (checkpt_sum0 != checkpt_sum1) + return 0; + + return 1; +} + +static int yaffs2_wr_checkpt_data(struct yaffs_dev *dev) +{ + int ok = 1; + + if (!yaffs2_checkpt_required(dev)) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "skipping checkpoint write"); + ok = 0; + } + + if (ok) + ok = yaffs2_checkpt_open(dev, 1); + + if (ok) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "write checkpoint validity"); + ok = yaffs2_wr_checkpt_validity_marker(dev, 1); + } + if (ok) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "write checkpoint device"); + ok = yaffs2_wr_checkpt_dev(dev); + } + if (ok) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "write checkpoint objects"); + ok = yaffs2_wr_checkpt_objs(dev); + } + if (ok) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "write checkpoint validity"); + ok = yaffs2_wr_checkpt_validity_marker(dev, 0); + } + + if (ok) + ok = yaffs2_wr_checkpt_sum(dev); + + if (!yaffs_checkpt_close(dev)) + ok = 0; + + if (ok) + dev->is_checkpointed = 1; + else + dev->is_checkpointed = 0; + + return dev->is_checkpointed; +} + +static int yaffs2_rd_checkpt_data(struct yaffs_dev *dev) +{ + int ok = 1; + + if (!dev->param.is_yaffs2) + ok = 0; + + if (ok && dev->param.skip_checkpt_rd) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "skipping checkpoint read"); + ok = 0; + } + + if (ok) + ok = yaffs2_checkpt_open(dev, 0); /* open for read */ + + if (ok) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "read checkpoint validity"); + ok = yaffs2_rd_checkpt_validity_marker(dev, 1); + } + if (ok) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "read checkpoint device"); + ok = yaffs2_rd_checkpt_dev(dev); + } + if (ok) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "read checkpoint objects"); + ok = yaffs2_rd_checkpt_objs(dev); + } + if (ok) { + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "read checkpoint validity"); + ok = yaffs2_rd_checkpt_validity_marker(dev, 0); + } + + if (ok) { + ok = yaffs2_rd_checkpt_sum(dev); + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "read checkpoint checksum %d", ok); + } + + if (!yaffs_checkpt_close(dev)) + ok = 0; + + if (ok) + dev->is_checkpointed = 1; + else + dev->is_checkpointed = 0; + + return ok ? 1 : 0; +} + +void yaffs2_checkpt_invalidate(struct yaffs_dev *dev) +{ + if (dev->is_checkpointed || dev->blocks_in_checkpt > 0) { + dev->is_checkpointed = 0; + yaffs2_checkpt_invalidate_stream(dev); + } + if (dev->param.sb_dirty_fn) + dev->param.sb_dirty_fn(dev); +} + +int yaffs_checkpoint_save(struct yaffs_dev *dev) +{ + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "save entry: is_checkpointed %d", + dev->is_checkpointed); + + yaffs_verify_objects(dev); + yaffs_verify_blocks(dev); + yaffs_verify_free_chunks(dev); + + if (!dev->is_checkpointed) { + yaffs2_checkpt_invalidate(dev); + yaffs2_wr_checkpt_data(dev); + } + + yaffs_trace(YAFFS_TRACE_CHECKPOINT | YAFFS_TRACE_MOUNT, + "save exit: is_checkpointed %d", + dev->is_checkpointed); + + return dev->is_checkpointed; +} + +int yaffs2_checkpt_restore(struct yaffs_dev *dev) +{ + int retval; + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "restore entry: is_checkpointed %d", + dev->is_checkpointed); + + retval = yaffs2_rd_checkpt_data(dev); + + if (dev->is_checkpointed) { + yaffs_verify_objects(dev); + yaffs_verify_blocks(dev); + yaffs_verify_free_chunks(dev); + } + + yaffs_trace(YAFFS_TRACE_CHECKPOINT, + "restore exit: is_checkpointed %d", + dev->is_checkpointed); + + return retval; +} + +int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size) +{ + /* if new_size > old_file_size. + * We're going to be writing a hole. + * If the hole is small then write zeros otherwise write a start + * of hole marker. + */ + loff_t old_file_size; + loff_t increase; + int small_hole; + int result = YAFFS_OK; + struct yaffs_dev *dev = NULL; + u8 *local_buffer = NULL; + int small_increase_ok = 0; + + if (!obj) + return YAFFS_FAIL; + + if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE) + return YAFFS_FAIL; + + dev = obj->my_dev; + + /* Bail out if not yaffs2 mode */ + if (!dev->param.is_yaffs2) + return YAFFS_OK; + + old_file_size = obj->variant.file_variant.file_size; + + if (new_size <= old_file_size) + return YAFFS_OK; + + increase = new_size - old_file_size; + + if (increase < YAFFS_SMALL_HOLE_THRESHOLD * dev->data_bytes_per_chunk && + yaffs_check_alloc_available(dev, YAFFS_SMALL_HOLE_THRESHOLD + 1)) + small_hole = 1; + else + small_hole = 0; + + if (small_hole) + local_buffer = yaffs_get_temp_buffer(dev); + + if (local_buffer) { + /* fill hole with zero bytes */ + loff_t pos = old_file_size; + int this_write; + int written; + memset(local_buffer, 0, dev->data_bytes_per_chunk); + small_increase_ok = 1; + + while (increase > 0 && small_increase_ok) { + this_write = increase; + if (this_write > dev->data_bytes_per_chunk) + this_write = dev->data_bytes_per_chunk; + written = + yaffs_do_file_wr(obj, local_buffer, pos, this_write, + 0); + if (written == this_write) { + pos += this_write; + increase -= this_write; + } else { + small_increase_ok = 0; + } + } + + yaffs_release_temp_buffer(dev, local_buffer); + + /* If out of space then reverse any chunks we've added */ + if (!small_increase_ok) + yaffs_resize_file_down(obj, old_file_size); + } + + if (!small_increase_ok && + obj->parent && + obj->parent->obj_id != YAFFS_OBJECTID_UNLINKED && + obj->parent->obj_id != YAFFS_OBJECTID_DELETED) { + /* Write a hole start header with the old file size */ + yaffs_update_oh(obj, NULL, 0, 1, 0, NULL); + } + + return result; +} + +struct yaffs_block_index { + int seq; + int block; +}; + +static int yaffs2_ybicmp(const void *a, const void *b) +{ + int aseq = ((struct yaffs_block_index *)a)->seq; + int bseq = ((struct yaffs_block_index *)b)->seq; + int ablock = ((struct yaffs_block_index *)a)->block; + int bblock = ((struct yaffs_block_index *)b)->block; + + if (aseq == bseq) + return ablock - bblock; + + return aseq - bseq; +} + +static inline int yaffs2_scan_chunk(struct yaffs_dev *dev, + struct yaffs_block_info *bi, + int blk, int chunk_in_block, + int *found_chunks, + u8 *chunk_data, + struct list_head *hard_list, + int summary_available) +{ + struct yaffs_obj_hdr *oh; + struct yaffs_obj *in; + struct yaffs_obj *parent; + int equiv_id; + loff_t file_size; + int is_shrink; + int is_unlinked; + struct yaffs_ext_tags tags; + int result; + int alloc_failed = 0; + int chunk = blk * dev->param.chunks_per_block + chunk_in_block; + struct yaffs_file_var *file_var; + struct yaffs_hardlink_var *hl_var; + struct yaffs_symlink_var *sl_var; + + if (summary_available) { + result = yaffs_summary_fetch(dev, &tags, chunk_in_block); + tags.seq_number = bi->seq_number; + } + + if (!summary_available || tags.obj_id == 0) { + result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags); + dev->tags_used++; + } else { + dev->summary_used++; + } + + /* Let's have a good look at this chunk... */ + + if (!tags.chunk_used) { + /* An unassigned chunk in the block. + * If there are used chunks after this one, then + * it is a chunk that was skipped due to failing + * the erased check. Just skip it so that it can + * be deleted. + * But, more typically, We get here when this is + * an unallocated chunk and his means that + * either the block is empty or this is the one + * being allocated from + */ + + if (*found_chunks) { + /* This is a chunk that was skipped due + * to failing the erased check */ + } else if (chunk_in_block == 0) { + /* We're looking at the first chunk in + * the block so the block is unused */ + bi->block_state = YAFFS_BLOCK_STATE_EMPTY; + dev->n_erased_blocks++; + } else { + if (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN || + bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING) { + if (dev->seq_number == bi->seq_number) { + /* Allocating from this block*/ + yaffs_trace(YAFFS_TRACE_SCAN, + " Allocating from %d %d", + blk, chunk_in_block); + + bi->block_state = + YAFFS_BLOCK_STATE_ALLOCATING; + dev->alloc_block = blk; + dev->alloc_page = chunk_in_block; + dev->alloc_block_finder = blk; + } else { + /* This is a partially written block + * that is not the current + * allocation block. + */ + yaffs_trace(YAFFS_TRACE_SCAN, + "Partially written block %d detected. gc will fix this.", + blk); + } + } + } + + dev->n_free_chunks++; + + } else if (tags.ecc_result == + YAFFS_ECC_RESULT_UNFIXED) { + yaffs_trace(YAFFS_TRACE_SCAN, + " Unfixed ECC in chunk(%d:%d), chunk ignored", + blk, chunk_in_block); + dev->n_free_chunks++; + } else if (tags.obj_id > YAFFS_MAX_OBJECT_ID || + tags.chunk_id > YAFFS_MAX_CHUNK_ID || + tags.obj_id == YAFFS_OBJECTID_SUMMARY || + (tags.chunk_id > 0 && + tags.n_bytes > dev->data_bytes_per_chunk) || + tags.seq_number != bi->seq_number) { + yaffs_trace(YAFFS_TRACE_SCAN, + "Chunk (%d:%d) with bad tags:obj = %d, chunk_id = %d, n_bytes = %d, ignored", + blk, chunk_in_block, tags.obj_id, + tags.chunk_id, tags.n_bytes); + dev->n_free_chunks++; + } else if (tags.chunk_id > 0) { + /* chunk_id > 0 so it is a data chunk... */ + loff_t endpos; + loff_t chunk_base = (tags.chunk_id - 1) * + dev->data_bytes_per_chunk; + + *found_chunks = 1; + + yaffs_set_chunk_bit(dev, blk, chunk_in_block); + bi->pages_in_use++; + + in = yaffs_find_or_create_by_number(dev, + tags.obj_id, + YAFFS_OBJECT_TYPE_FILE); + if (!in) + /* Out of memory */ + alloc_failed = 1; + + if (in && + in->variant_type == YAFFS_OBJECT_TYPE_FILE && + chunk_base < in->variant.file_variant.shrink_size) { + /* This has not been invalidated by + * a resize */ + if (!yaffs_put_chunk_in_file(in, tags.chunk_id, + chunk, -1)) + alloc_failed = 1; + + /* File size is calculated by looking at + * the data chunks if we have not + * seen an object header yet. + * Stop this practice once we find an + * object header. + */ + endpos = chunk_base + tags.n_bytes; + + if (!in->valid && + in->variant.file_variant.scanned_size < endpos) { + in->variant.file_variant. + scanned_size = endpos; + in->variant.file_variant. + file_size = endpos; + } + } else if (in) { + /* This chunk has been invalidated by a + * resize, or a past file deletion + * so delete the chunk*/ + yaffs_chunk_del(dev, chunk, 1, __LINE__); + } + } else { + /* chunk_id == 0, so it is an ObjectHeader. + * Thus, we read in the object header and make + * the object + */ + *found_chunks = 1; + + yaffs_set_chunk_bit(dev, blk, chunk_in_block); + bi->pages_in_use++; + + oh = NULL; + in = NULL; + + if (tags.extra_available) { + in = yaffs_find_or_create_by_number(dev, + tags.obj_id, + tags.extra_obj_type); + if (!in) + alloc_failed = 1; + } + + if (!in || + (!in->valid && dev->param.disable_lazy_load) || + tags.extra_shadows || + (!in->valid && (tags.obj_id == YAFFS_OBJECTID_ROOT || + tags.obj_id == YAFFS_OBJECTID_LOSTNFOUND))) { + + /* If we don't have valid info then we + * need to read the chunk + * TODO In future we can probably defer + * reading the chunk and living with + * invalid data until needed. + */ + + result = yaffs_rd_chunk_tags_nand(dev, + chunk, + chunk_data, + NULL); + + oh = (struct yaffs_obj_hdr *)chunk_data; + + if (dev->param.inband_tags) { + /* Fix up the header if they got + * corrupted by inband tags */ + oh->shadows_obj = + oh->inband_shadowed_obj_id; + oh->is_shrink = + oh->inband_is_shrink; + } + + if (!in) { + in = yaffs_find_or_create_by_number(dev, + tags.obj_id, oh->type); + if (!in) + alloc_failed = 1; + } + } + + if (!in) { + /* TODO Hoosterman we have a problem! */ + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs tragedy: Could not make object for object %d at chunk %d during scan", + tags.obj_id, chunk); + return YAFFS_FAIL; + } + + if (in->valid) { + /* We have already filled this one. + * We have a duplicate that will be + * discarded, but we first have to suck + * out resize info if it is a file. + */ + if ((in->variant_type == YAFFS_OBJECT_TYPE_FILE) && + ((oh && oh->type == YAFFS_OBJECT_TYPE_FILE) || + (tags.extra_available && + tags.extra_obj_type == YAFFS_OBJECT_TYPE_FILE) + )) { + loff_t this_size = (oh) ? + yaffs_oh_to_size(oh) : + tags.extra_file_size; + u32 parent_obj_id = (oh) ? + oh->parent_obj_id : + tags.extra_parent_id; + + is_shrink = (oh) ? + oh->is_shrink : + tags.extra_is_shrink; + + /* If it is deleted (unlinked + * at start also means deleted) + * we treat the file size as + * being zeroed at this point. + */ + if (parent_obj_id == YAFFS_OBJECTID_DELETED || + parent_obj_id == YAFFS_OBJECTID_UNLINKED) { + this_size = 0; + is_shrink = 1; + } + + if (is_shrink && + in->variant.file_variant.shrink_size > + this_size) + in->variant.file_variant.shrink_size = + this_size; + + if (is_shrink) + bi->has_shrink_hdr = 1; + } + /* Use existing - destroy this one. */ + yaffs_chunk_del(dev, chunk, 1, __LINE__); + } + + if (!in->valid && in->variant_type != + (oh ? oh->type : tags.extra_obj_type)) { + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs tragedy: Bad type, %d != %d, for object %d at chunk %d during scan", + oh ? oh->type : tags.extra_obj_type, + in->variant_type, tags.obj_id, + chunk); + in = yaffs_retype_obj(in, oh ? oh->type : tags.extra_obj_type); + } + + if (!in->valid && + (tags.obj_id == YAFFS_OBJECTID_ROOT || + tags.obj_id == YAFFS_OBJECTID_LOSTNFOUND)) { + /* We only load some info, don't fiddle + * with directory structure */ + in->valid = 1; + + if (oh) { + in->yst_mode = oh->yst_mode; + yaffs_load_attribs(in, oh); + in->lazy_loaded = 0; + } else { + in->lazy_loaded = 1; + } + in->hdr_chunk = chunk; + + } else if (!in->valid) { + /* we need to load this info */ + in->valid = 1; + in->hdr_chunk = chunk; + if (oh) { + in->variant_type = oh->type; + in->yst_mode = oh->yst_mode; + yaffs_load_attribs(in, oh); + + if (oh->shadows_obj > 0) + yaffs_handle_shadowed_obj(dev, + oh->shadows_obj, 1); + + yaffs_set_obj_name_from_oh(in, oh); + parent = yaffs_find_or_create_by_number(dev, + oh->parent_obj_id, + YAFFS_OBJECT_TYPE_DIRECTORY); + file_size = yaffs_oh_to_size(oh); + is_shrink = oh->is_shrink; + equiv_id = oh->equiv_id; + } else { + in->variant_type = tags.extra_obj_type; + parent = yaffs_find_or_create_by_number(dev, + tags.extra_parent_id, + YAFFS_OBJECT_TYPE_DIRECTORY); + file_size = tags.extra_file_size; + is_shrink = tags.extra_is_shrink; + equiv_id = tags.extra_equiv_id; + in->lazy_loaded = 1; + } + in->dirty = 0; + + if (!parent) + alloc_failed = 1; + + /* directory stuff... + * hook up to parent + */ + + if (parent && + parent->variant_type == YAFFS_OBJECT_TYPE_UNKNOWN) { + /* Set up as a directory */ + parent->variant_type = + YAFFS_OBJECT_TYPE_DIRECTORY; + INIT_LIST_HEAD(&parent-> + variant.dir_variant.children); + } else if (!parent || + parent->variant_type != + YAFFS_OBJECT_TYPE_DIRECTORY) { + /* Hoosterman, another problem.... + * Trying to use a non-directory as a directory + */ + + yaffs_trace(YAFFS_TRACE_ERROR, + "yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." + ); + parent = dev->lost_n_found; + } + yaffs_add_obj_to_dir(parent, in); + + is_unlinked = (parent == dev->del_dir) || + (parent == dev->unlinked_dir); + + if (is_shrink) + /* Mark the block */ + bi->has_shrink_hdr = 1; + + /* Note re hardlinks. + * Since we might scan a hardlink before its equivalent + * object is scanned we put them all in a list. + * After scanning is complete, we should have all the + * objects, so we run through this list and fix up all + * the chains. + */ + + switch (in->variant_type) { + case YAFFS_OBJECT_TYPE_UNKNOWN: + /* Todo got a problem */ + break; + case YAFFS_OBJECT_TYPE_FILE: + file_var = &in->variant.file_variant; + if (file_var->scanned_size < file_size) { + /* This covers the case where the file + * size is greater than the data held. + * This will happen if the file is + * resized to be larger than its + * current data extents. + */ + file_var->file_size = file_size; + file_var->scanned_size = file_size; + } + + if (file_var->shrink_size > file_size) + file_var->shrink_size = file_size; + + break; + case YAFFS_OBJECT_TYPE_HARDLINK: + hl_var = &in->variant.hardlink_variant; + if (!is_unlinked) { + hl_var->equiv_id = equiv_id; + list_add(&in->hard_links, hard_list); + } + break; + case YAFFS_OBJECT_TYPE_DIRECTORY: + /* Do nothing */ + break; + case YAFFS_OBJECT_TYPE_SPECIAL: + /* Do nothing */ + break; + case YAFFS_OBJECT_TYPE_SYMLINK: + sl_var = &in->variant.symlink_variant; + if (oh) { + sl_var->alias = + yaffs_clone_str(oh->alias); + if (!sl_var->alias) + alloc_failed = 1; + } + break; + } + } + } + return alloc_failed ? YAFFS_FAIL : YAFFS_OK; +} + +int yaffs2_scan_backwards(struct yaffs_dev *dev) +{ + int blk; + int block_iter; + int start_iter; + int end_iter; + int n_to_scan = 0; + enum yaffs_block_state state; + int c; + LIST_HEAD(hard_list); + struct yaffs_block_info *bi; + u32 seq_number; + int n_blocks = dev->internal_end_block - dev->internal_start_block + 1; + u8 *chunk_data; + int found_chunks; + int alloc_failed = 0; + struct yaffs_block_index *block_index = NULL; + int alt_block_index = 0; + int summary_available; + + yaffs_trace(YAFFS_TRACE_SCAN, + "yaffs2_scan_backwards starts intstartblk %d intendblk %d...", + dev->internal_start_block, dev->internal_end_block); + + dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER; + + block_index = + kmalloc(n_blocks * sizeof(struct yaffs_block_index), GFP_NOFS); + + if (!block_index) { + block_index = + vmalloc(n_blocks * sizeof(struct yaffs_block_index)); + alt_block_index = 1; + } + + if (!block_index) { + yaffs_trace(YAFFS_TRACE_SCAN, + "yaffs2_scan_backwards() could not allocate block index!" + ); + return YAFFS_FAIL; + } + + dev->blocks_in_checkpt = 0; + + chunk_data = yaffs_get_temp_buffer(dev); + + /* Scan all the blocks to determine their state */ + bi = dev->block_info; + for (blk = dev->internal_start_block; blk <= dev->internal_end_block; + blk++) { + yaffs_clear_chunk_bits(dev, blk); + bi->pages_in_use = 0; + bi->soft_del_pages = 0; + + yaffs_query_init_block_state(dev, blk, &state, &seq_number); + + bi->block_state = state; + bi->seq_number = seq_number; + + if (bi->seq_number == YAFFS_SEQUENCE_CHECKPOINT_DATA) + bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; + if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK) + bi->block_state = YAFFS_BLOCK_STATE_DEAD; + + yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, + "Block scanning block %d state %d seq %d", + blk, bi->block_state, seq_number); + + if (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT) { + dev->blocks_in_checkpt++; + + } else if (bi->block_state == YAFFS_BLOCK_STATE_DEAD) { + yaffs_trace(YAFFS_TRACE_BAD_BLOCKS, + "block %d is bad", blk); + } else if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { + yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "Block empty "); + dev->n_erased_blocks++; + dev->n_free_chunks += dev->param.chunks_per_block; + } else if (bi->block_state == + YAFFS_BLOCK_STATE_NEEDS_SCAN) { + /* Determine the highest sequence number */ + if (seq_number >= YAFFS_LOWEST_SEQUENCE_NUMBER && + seq_number < YAFFS_HIGHEST_SEQUENCE_NUMBER) { + block_index[n_to_scan].seq = seq_number; + block_index[n_to_scan].block = blk; + n_to_scan++; + if (seq_number >= dev->seq_number) + dev->seq_number = seq_number; + } else { + /* TODO: Nasty sequence number! */ + yaffs_trace(YAFFS_TRACE_SCAN, + "Block scanning block %d has bad sequence number %d", + blk, seq_number); + } + } + bi++; + } + + yaffs_trace(YAFFS_TRACE_ALWAYS, "%d blocks to be sorted...", n_to_scan); + + cond_resched(); + + /* Sort the blocks by sequence number */ + sort(block_index, n_to_scan, sizeof(struct yaffs_block_index), + yaffs2_ybicmp, NULL); + + cond_resched(); + + yaffs_trace(YAFFS_TRACE_SCAN, "...done"); + + /* Now scan the blocks looking at the data. */ + start_iter = 0; + end_iter = n_to_scan - 1; + yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "%d blocks to scan", n_to_scan); + + /* For each block.... backwards */ + for (block_iter = end_iter; + !alloc_failed && block_iter >= start_iter; + block_iter--) { + /* Cooperative multitasking! This loop can run for so + long that watchdog timers expire. */ + cond_resched(); + + /* get the block to scan in the correct order */ + blk = block_index[block_iter].block; + bi = yaffs_get_block_info(dev, blk); + + summary_available = yaffs_summary_read(dev, dev->sum_tags, blk); + + /* For each chunk in each block that needs scanning.... */ + found_chunks = 0; + if (summary_available) + c = dev->chunks_per_summary - 1; + else + c = dev->param.chunks_per_block - 1; + + for (/* c is already initialised */; + !alloc_failed && c >= 0 && + (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN || + bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING); + c--) { + /* Scan backwards... + * Read the tags and decide what to do + */ + if (yaffs2_scan_chunk(dev, bi, blk, c, + &found_chunks, chunk_data, + &hard_list, summary_available) == + YAFFS_FAIL) + alloc_failed = 1; + } + + if (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN) { + /* If we got this far while scanning, then the block + * is fully allocated. */ + bi->block_state = YAFFS_BLOCK_STATE_FULL; + } + + /* Now let's see if it was dirty */ + if (bi->pages_in_use == 0 && + !bi->has_shrink_hdr && + bi->block_state == YAFFS_BLOCK_STATE_FULL) { + yaffs_block_became_dirty(dev, blk); + } + } + + yaffs_skip_rest_of_block(dev); + + if (alt_block_index) + vfree(block_index); + else + kfree(block_index); + + /* Ok, we've done all the scanning. + * Fix up the hard link chains. + * We have scanned all the objects, now it's time to add these + * hardlinks. + */ + yaffs_link_fixup(dev, &hard_list); + + yaffs_release_temp_buffer(dev, chunk_data); + + if (alloc_failed) + return YAFFS_FAIL; + + yaffs_trace(YAFFS_TRACE_SCAN, "yaffs2_scan_backwards ends"); + + return YAFFS_OK; +} diff --git a/target/linux/generic/files/fs/yaffs2/yaffs_yaffs2.h b/target/linux/generic/files/fs/yaffs2/yaffs_yaffs2.h new file mode 100644 index 0000000..2363bfd --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yaffs_yaffs2.h @@ -0,0 +1,39 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YAFFS_YAFFS2_H__ +#define __YAFFS_YAFFS2_H__ + +#include "yaffs_guts.h" + +void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev); +void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev); +void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev, + struct yaffs_block_info *bi); +void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no, + struct yaffs_block_info *bi); +int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi); +u32 yaffs2_find_refresh_block(struct yaffs_dev *dev); +int yaffs2_checkpt_required(struct yaffs_dev *dev); +int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev); + +void yaffs2_checkpt_invalidate(struct yaffs_dev *dev); +int yaffs2_checkpt_save(struct yaffs_dev *dev); +int yaffs2_checkpt_restore(struct yaffs_dev *dev); + +int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size); +int yaffs2_scan_backwards(struct yaffs_dev *dev); + +#endif diff --git a/target/linux/generic/files/fs/yaffs2/yportenv.h b/target/linux/generic/files/fs/yaffs2/yportenv.h new file mode 100644 index 0000000..8975af3 --- /dev/null +++ b/target/linux/generic/files/fs/yaffs2/yportenv.h @@ -0,0 +1,85 @@ +/* + * YAFFS: Yet another Flash File System . A NAND-flash specific file system. + * + * Copyright (C) 2002-2011 Aleph One Ltd. + * for Toby Churchill Ltd and Brightstar Engineering + * + * Created by Charles Manning + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2.1 as + * published by the Free Software Foundation. + * + * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. + */ + +#ifndef __YPORTENV_H__ +#define __YPORTENV_H__ + +/* + * Define the MTD version in terms of Linux Kernel versions + * This allows yaffs to be used independantly of the kernel + * as well as with it. + */ + +#define MTD_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) + +#ifdef YAFFS_OUT_OF_TREE +#include "moduleconfig.h" +#endif + +#include +#define MTD_VERSION_CODE LINUX_VERSION_CODE + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* These type wrappings are used to support Unicode names in WinCE. */ +#define YCHAR char +#define YUCHAR unsigned char +#define _Y(x) x + +#define YAFFS_LOSTNFOUND_NAME "lost+found" +#define YAFFS_LOSTNFOUND_PREFIX "obj" + + +#define YAFFS_ROOT_MODE 0755 +#define YAFFS_LOSTNFOUND_MODE 0700 + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) +#define Y_CURRENT_TIME CURRENT_TIME.tv_sec +#define Y_TIME_CONVERT(x) (x).tv_sec +#else +#define Y_CURRENT_TIME CURRENT_TIME +#define Y_TIME_CONVERT(x) (x) +#endif + +#define compile_time_assertion(assertion) \ + ({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; }) + + +#define yaffs_printf(msk, fmt, ...) \ + printk(KERN_DEBUG "yaffs: " fmt "\n", ##__VA_ARGS__) + +#define yaffs_trace(msk, fmt, ...) do { \ + if (yaffs_trace_mask & (msk)) \ + printk(KERN_DEBUG "yaffs: " fmt "\n", ##__VA_ARGS__); \ +} while (0) + + +#endif diff --git a/target/linux/generic/files/include/linux/ar8216_platform.h b/target/linux/generic/files/include/linux/ar8216_platform.h new file mode 100644 index 0000000..d70f11a --- /dev/null +++ b/target/linux/generic/files/include/linux/ar8216_platform.h @@ -0,0 +1,133 @@ +/* + * AR8216 switch driver platform data + * + * Copyright (C) 2012 Gabor Juhos + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AR8216_PLATFORM_H +#define AR8216_PLATFORM_H + +enum ar8327_pad_mode { + AR8327_PAD_NC = 0, + AR8327_PAD_MAC2MAC_MII, + AR8327_PAD_MAC2MAC_GMII, + AR8327_PAD_MAC_SGMII, + AR8327_PAD_MAC2PHY_MII, + AR8327_PAD_MAC2PHY_GMII, + AR8327_PAD_MAC_RGMII, + AR8327_PAD_PHY_GMII, + AR8327_PAD_PHY_RGMII, + AR8327_PAD_PHY_MII, +}; + +enum ar8327_clk_delay_sel { + AR8327_CLK_DELAY_SEL0 = 0, + AR8327_CLK_DELAY_SEL1, + AR8327_CLK_DELAY_SEL2, + AR8327_CLK_DELAY_SEL3, +}; + +struct ar8327_pad_cfg { + enum ar8327_pad_mode mode; + bool rxclk_sel; + bool txclk_sel; + bool pipe_rxclk_sel; + bool txclk_delay_en; + bool rxclk_delay_en; + bool sgmii_delay_en; + enum ar8327_clk_delay_sel txclk_delay_sel; + enum ar8327_clk_delay_sel rxclk_delay_sel; + bool mac06_exchange_en; +}; + +enum ar8327_port_speed { + AR8327_PORT_SPEED_10 = 0, + AR8327_PORT_SPEED_100, + AR8327_PORT_SPEED_1000, +}; + +struct ar8327_port_cfg { + int force_link:1; + enum ar8327_port_speed speed; + int txpause:1; + int rxpause:1; + int duplex:1; +}; + +struct ar8327_sgmii_cfg { + u32 sgmii_ctrl; + bool serdes_aen; +}; + +struct ar8327_led_cfg { + u32 led_ctrl0; + u32 led_ctrl1; + u32 led_ctrl2; + u32 led_ctrl3; + bool open_drain; +}; + +enum ar8327_led_num { + AR8327_LED_PHY0_0 = 0, + AR8327_LED_PHY0_1, + AR8327_LED_PHY0_2, + AR8327_LED_PHY1_0, + AR8327_LED_PHY1_1, + AR8327_LED_PHY1_2, + AR8327_LED_PHY2_0, + AR8327_LED_PHY2_1, + AR8327_LED_PHY2_2, + AR8327_LED_PHY3_0, + AR8327_LED_PHY3_1, + AR8327_LED_PHY3_2, + AR8327_LED_PHY4_0, + AR8327_LED_PHY4_1, + AR8327_LED_PHY4_2, +}; + +enum ar8327_led_mode { + AR8327_LED_MODE_HW = 0, + AR8327_LED_MODE_SW, +}; + +struct ar8327_led_info { + const char *name; + const char *default_trigger; + bool active_low; + enum ar8327_led_num led_num; + enum ar8327_led_mode mode; +}; + +#define AR8327_LED_INFO(_led, _mode, _name) { \ + .name = (_name), \ + .led_num = AR8327_LED_ ## _led, \ + .mode = AR8327_LED_MODE_ ## _mode \ +} + +struct ar8327_platform_data { + struct ar8327_pad_cfg *pad0_cfg; + struct ar8327_pad_cfg *pad5_cfg; + struct ar8327_pad_cfg *pad6_cfg; + struct ar8327_sgmii_cfg *sgmii_cfg; + struct ar8327_port_cfg port0_cfg; + struct ar8327_port_cfg port6_cfg; + struct ar8327_led_cfg *led_cfg; + + int (*get_port_link)(unsigned port); + + unsigned num_leds; + const struct ar8327_led_info *leds; +}; + +#endif /* AR8216_PLATFORM_H */ + diff --git a/target/linux/generic/files/include/linux/ath5k_platform.h b/target/linux/generic/files/include/linux/ath5k_platform.h new file mode 100644 index 0000000..ec85224 --- /dev/null +++ b/target/linux/generic/files/include/linux/ath5k_platform.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2009 Gabor Juhos + * Copyright (c) 2009 Imre Kaloz + * Copyright (c) 2010 Daniel Golle + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _LINUX_ATH5K_PLATFORM_H +#define _LINUX_ATH5K_PLATFORM_H + +#define ATH5K_PLAT_EEP_MAX_WORDS 2048 + +struct ath5k_platform_data { + u16 *eeprom_data; + u8 *macaddr; +}; + +#endif /* _LINUX_ATH5K_PLATFORM_H */ diff --git a/target/linux/generic/files/include/linux/ath9k_platform.h b/target/linux/generic/files/include/linux/ath9k_platform.h new file mode 100644 index 0000000..9fa7016 --- /dev/null +++ b/target/linux/generic/files/include/linux/ath9k_platform.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2009 Gabor Juhos + * Copyright (c) 2009 Imre Kaloz + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _LINUX_ATH9K_PLATFORM_H +#define _LINUX_ATH9K_PLATFORM_H + +#define ATH9K_PLAT_EEP_MAX_WORDS 2048 + +struct ath9k_platform_data { + const char *eeprom_name; + + u16 eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS]; + u8 *macaddr; + + int led_pin; + u32 gpio_mask; + u32 gpio_val; + + bool endian_check; + bool is_clk_25mhz; + bool tx_gain_buffalo; + bool disable_2ghz; + bool disable_5ghz; + + int (*get_mac_revision)(void); + int (*external_reset)(void); + + bool use_eeprom; + + int num_leds; + const struct gpio_led *leds; +}; + +#endif /* _LINUX_ATH9K_PLATFORM_H */ diff --git a/target/linux/generic/files/include/linux/myloader.h b/target/linux/generic/files/include/linux/myloader.h new file mode 100644 index 0000000..d89e415 --- /dev/null +++ b/target/linux/generic/files/include/linux/myloader.h @@ -0,0 +1,121 @@ +/* + * Compex's MyLoader specific definitions + * + * Copyright (C) 2006-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _MYLOADER_H_ +#define _MYLOADER_H_ + +/* Myloader specific magic numbers */ +#define MYLO_MAGIC_SYS_PARAMS 0x20021107 +#define MYLO_MAGIC_PARTITIONS 0x20021103 +#define MYLO_MAGIC_BOARD_PARAMS 0x20021103 + +/* Vendor ID's (seems to be same as the PCI vendor ID's) */ +#define VENID_COMPEX 0x11F6 + +/* Devices based on the ADM5120 */ +#define DEVID_COMPEX_NP27G 0x0078 +#define DEVID_COMPEX_NP28G 0x044C +#define DEVID_COMPEX_NP28GHS 0x044E +#define DEVID_COMPEX_WP54Gv1C 0x0514 +#define DEVID_COMPEX_WP54G 0x0515 +#define DEVID_COMPEX_WP54AG 0x0546 +#define DEVID_COMPEX_WPP54AG 0x0550 +#define DEVID_COMPEX_WPP54G 0x0555 + +/* Devices based on the Atheros AR2317 */ +#define DEVID_COMPEX_NP25G 0x05E6 +#define DEVID_COMPEX_WPE53G 0x05DC + +/* Devices based on the Atheros AR71xx */ +#define DEVID_COMPEX_WP543 0x0640 +#define DEVID_COMPEX_WPE72 0x0672 + +/* Devices based on the IXP422 */ +#define DEVID_COMPEX_WP18 0x047E +#define DEVID_COMPEX_NP18A 0x0489 + +/* Other devices */ +#define DEVID_COMPEX_NP26G8M 0x03E8 +#define DEVID_COMPEX_NP26G16M 0x03E9 + +struct mylo_partition { + uint16_t flags; /* partition flags */ + uint16_t type; /* type of the partition */ + uint32_t addr; /* relative address of the partition from the + flash start */ + uint32_t size; /* size of the partition in bytes */ + uint32_t param; /* if this is the active partition, the + MyLoader load code to this address */ +}; + +#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition, + * MyLoader loads firmware from here */ +#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */ +#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */ +#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM + * before decompression */ +#define PARTITION_FLAG_LZMA 0x0100 /* partition data compressed by LZMA */ +#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */ + +#define PARTITION_TYPE_FREE 0 +#define PARTITION_TYPE_USED 1 + +#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the + partition table */ + +struct mylo_partition_table { + uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */ + uint32_t res0; /* unknown/unused */ + uint32_t res1; /* unknown/unused */ + uint32_t res2; /* unknown/unused */ + struct mylo_partition partitions[MYLO_MAX_PARTITIONS]; +}; + +struct mylo_partition_header { + uint32_t len; /* length of the partition data */ + uint32_t crc; /* CRC value of the partition data */ +}; + +struct mylo_system_params { + uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */ + uint32_t res0; + uint32_t res1; + uint32_t mylo_ver; + uint16_t vid; /* Vendor ID */ + uint16_t did; /* Device ID */ + uint16_t svid; /* Sub Vendor ID */ + uint16_t sdid; /* Sub Device ID */ + uint32_t rev; /* device revision */ + uint32_t fwhi; + uint32_t fwlo; + uint32_t tftp_addr; + uint32_t prog_start; + uint32_t flash_size; /* size of boot FLASH in bytes */ + uint32_t dram_size; /* size of onboard RAM in bytes */ +}; + +struct mylo_eth_addr { + uint8_t mac[6]; + uint8_t csum[2]; +}; + +#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address + in the board parameters */ + +struct mylo_board_params { + uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */ + uint32_t res0; + uint32_t res1; + uint32_t res2; + struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT]; +}; + +#endif /* _MYLOADER_H_*/ diff --git a/target/linux/generic/files/include/linux/platform_data/adm6996-gpio.h b/target/linux/generic/files/include/linux/platform_data/adm6996-gpio.h new file mode 100644 index 0000000..e4fcfaf --- /dev/null +++ b/target/linux/generic/files/include/linux/platform_data/adm6996-gpio.h @@ -0,0 +1,30 @@ +/* + * ADM6996 GPIO platform data + * + * Copyright (C) 2013 Hauke Mehrtens + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License v2 as published by the + * Free Software Foundation + */ + +#ifndef __PLATFORM_ADM6996_GPIO_H +#define __PLATFORM_ADM6996_GPIO_H + +#include + +enum adm6996_model { + ADM6996FC = 1, + ADM6996M = 2, + ADM6996L = 3, +}; + +struct adm6996_gpio_platform_data { + u8 eecs; + u8 eesk; + u8 eedi; + u8 eerc; + enum adm6996_model model; +}; + +#endif diff --git a/target/linux/generic/files/include/linux/platform_data/b53.h b/target/linux/generic/files/include/linux/platform_data/b53.h new file mode 100644 index 0000000..7842741 --- /dev/null +++ b/target/linux/generic/files/include/linux/platform_data/b53.h @@ -0,0 +1,36 @@ +/* + * B53 platform data + * + * Copyright (C) 2013 Jonas Gorski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __B53_H +#define __B53_H + +#include + +struct b53_platform_data { + u32 chip_id; + u16 enabled_ports; + + /* allow to specify an ethX alias */ + const char *alias; + + /* only used by MMAP'd driver */ + unsigned big_endian:1; + void __iomem *regs; +}; + +#endif diff --git a/target/linux/generic/files/include/linux/platform_data/brcmfmac-sdio.h b/target/linux/generic/files/include/linux/platform_data/brcmfmac-sdio.h new file mode 100644 index 0000000..1ade657 --- /dev/null +++ b/target/linux/generic/files/include/linux/platform_data/brcmfmac-sdio.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2013 Broadcom Corporation + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _LINUX_BRCMFMAC_PLATFORM_H +#define _LINUX_BRCMFMAC_PLATFORM_H + +/* + * Platform specific driver functions and data. Through the platform specific + * device data functions can be provided to help the brcmfmac driver to + * operate with the device in combination with the used platform. + * + * Use the platform data in the following (similar) way: + * + * +#include + + +static void brcmfmac_power_on(void) +{ +} + +static void brcmfmac_power_off(void) +{ +} + +static void brcmfmac_reset(void) +{ +} + +static struct brcmfmac_sdio_platform_data brcmfmac_sdio_pdata = { + .power_on = brcmfmac_power_on, + .power_off = brcmfmac_power_off, + .reset = brcmfmac_reset +}; + +static struct platform_device brcmfmac_device = { + .name = BRCMFMAC_SDIO_PDATA_NAME, + .id = PLATFORM_DEVID_NONE, + .dev.platform_data = &brcmfmac_sdio_pdata +}; + +void __init brcmfmac_init_pdata(void) +{ + brcmfmac_sdio_pdata.oob_irq_supported = true; + brcmfmac_sdio_pdata.oob_irq_nr = gpio_to_irq(GPIO_BRCMF_SDIO_OOB); + brcmfmac_sdio_pdata.oob_irq_flags = IORESOURCE_IRQ | + IORESOURCE_IRQ_HIGHLEVEL; + platform_device_register(&brcmfmac_device); +} + * + * + * Note: the brcmfmac can be loaded as module or be statically built-in into + * the kernel. If built-in then do note that it uses module_init (and + * module_exit) routines which equal device_initcall. So if you intend to + * create a module with the platform specific data for the brcmfmac and have + * it built-in to the kernel then use a higher initcall then device_initcall + * (see init.h). If this is not done then brcmfmac will load without problems + * but will not pickup the platform data. + * + * When the driver does not "detect" platform driver data then it will continue + * without reporting anything and just assume there is no data needed. Which is + * probably true for most platforms. + * + * Explanation of the platform_data fields: + * + * drive_strength: is the preferred drive_strength to be used for the SDIO + * pins. If 0 then a default value will be used. This is the target drive + * strength, the exact drive strength which will be used depends on the + * capabilities of the device. + * + * oob_irq_supported: does the board have support for OOB interrupts. SDIO + * in-band interrupts are relatively slow and for having less overhead on + * interrupt processing an out of band interrupt can be used. If the HW + * supports this then enable this by setting this field to true and configure + * the oob related fields. + * + * oob_irq_nr, oob_irq_flags: the OOB interrupt information. The values are + * used for registering the irq using request_irq function. + * + * power_on: This function is called by the brcmfmac when the module gets + * loaded. This can be particularly useful for low power devices. The platform + * spcific routine may for example decide to power up the complete device. + * If there is no use-case for this function then provide NULL. + * + * power_off: This function is called by the brcmfmac when the module gets + * unloaded. At this point the device can be powered down or otherwise be reset. + * So if an actual power_off is not supported but reset is then reset the device + * when this function gets called. This can be particularly useful for low power + * devices. If there is no use-case for this function (either power-down or + * reset) then provide NULL. + * + * reset: This function can get called if the device communication broke down. + * This functionality is particularly useful in case of SDIO type devices. It is + * possible to reset a dongle via sdio data interface, but it requires that + * this is fully functional. This function is chip/module specific and this + * function should return only after the complete reset has completed. + */ + +#define BRCMFMAC_SDIO_PDATA_NAME "brcmfmac_sdio" + +struct brcmfmac_sdio_platform_data { + unsigned int drive_strength; + bool oob_irq_supported; + unsigned int oob_irq_nr; + unsigned long oob_irq_flags; + void (*power_on)(void); + void (*power_off)(void); + void (*reset)(void); +}; + +#endif /* _LINUX_BRCMFMAC_PLATFORM_H */ diff --git a/target/linux/generic/files/include/linux/routerboot.h b/target/linux/generic/files/include/linux/routerboot.h new file mode 100644 index 0000000..3cda858 --- /dev/null +++ b/target/linux/generic/files/include/linux/routerboot.h @@ -0,0 +1,106 @@ +/* + * Mikrotik's RouterBOOT definitions + * + * Copyright (C) 2007-2008 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _ROUTERBOOT_H +#define _ROUTERBOOT_H + +#define RB_MAC_SIZE 6 + +/* + * Magic numbers + */ +#define RB_MAGIC_HARD 0x64726148 /* "Hard" */ +#define RB_MAGIC_SOFT 0x74666F53 /* "Soft" */ +#define RB_MAGIC_DAWN 0x6E776144 /* "Dawn" */ + +#define RB_ID_TERMINATOR 0 + +/* + * ID values for Hardware settings + */ +#define RB_ID_HARD_01 1 +#define RB_ID_HARD_02 2 +#define RB_ID_FLASH_INFO 3 +#define RB_ID_MAC_ADDRESS_PACK 4 +#define RB_ID_BOARD_NAME 5 +#define RB_ID_BIOS_VERSION 6 +#define RB_ID_HARD_07 7 +#define RB_ID_SDRAM_TIMINGS 8 +#define RB_ID_DEVICE_TIMINGS 9 +#define RB_ID_SOFTWARE_ID 10 +#define RB_ID_SERIAL_NUMBER 11 +#define RB_ID_HARD_12 12 +#define RB_ID_MEMORY_SIZE 13 +#define RB_ID_MAC_ADDRESS_COUNT 14 +#define RB_ID_HW_OPTIONS 21 +#define RB_ID_WLAN_DATA 22 + +/* + * ID values for Software settings + */ +#define RB_ID_UART_SPEED 1 +#define RB_ID_BOOT_DELAY 2 +#define RB_ID_BOOT_DEVICE 3 +#define RB_ID_BOOT_KEY 4 +#define RB_ID_CPU_MODE 5 +#define RB_ID_FW_VERSION 6 +#define RB_ID_SOFT_07 7 +#define RB_ID_SOFT_08 8 +#define RB_ID_BOOT_PROTOCOL 9 +#define RB_ID_SOFT_10 10 +#define RB_ID_SOFT_11 11 + +/* + * UART_SPEED values + */ +#define RB_UART_SPEED_115200 0 +#define RB_UART_SPEED_57600 1 +#define RB_UART_SPEED_38400 2 +#define RB_UART_SPEED_19200 3 +#define RB_UART_SPEED_9600 4 +#define RB_UART_SPEED_4800 5 +#define RB_UART_SPEED_2400 6 +#define RB_UART_SPEED_1200 7 + +/* + * BOOT_DELAY values + */ +#define RB_BOOT_DELAY_0SEC 0 +#define RB_BOOT_DELAY_1SEC 1 +#define RB_BOOT_DELAY_2SEC 2 + +/* + * BOOT_DEVICE values + */ +#define RB_BOOT_DEVICE_ETHER 0 +#define RB_BOOT_DEVICE_NANDETH 1 +#define RB_BOOT_DEVICE_ETHONCE 2 +#define RB_BOOT_DEVICE_NANDONLY 3 + +/* + * BOOT_KEY values + */ +#define RB_BOOT_KEY_ANY 0 +#define RB_BOOT_KEY_DEL 1 + +/* + * CPU_MODE values + */ +#define RB_CPU_MODE_POWERSAVE 0 +#define RB_CPU_MODE_REGULAR 1 + +/* + * BOOT_PROTOCOL values + */ +#define RB_BOOT_PROTOCOL_BOOTP 0 +#define RB_BOOT_PROTOCOL_DHCP 1 + +#endif /* _ROUTERBOOT_H */ diff --git a/target/linux/generic/files/include/linux/rt2x00_platform.h b/target/linux/generic/files/include/linux/rt2x00_platform.h new file mode 100644 index 0000000..80483ef --- /dev/null +++ b/target/linux/generic/files/include/linux/rt2x00_platform.h @@ -0,0 +1,24 @@ +/* + * Platform data definition for the rt2x00 driver + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _RT2X00_PLATFORM_H +#define _RT2X00_PLATFORM_H + +struct rt2x00_platform_data { + char *eeprom_file_name; + const u8 *mac_address; + + int disable_2ghz; + int disable_5ghz; + int clk_is_20mhz; +}; + +#endif /* _RT2X00_PLATFORM_H */ diff --git a/target/linux/generic/files/include/linux/rtl8366.h b/target/linux/generic/files/include/linux/rtl8366.h new file mode 100644 index 0000000..78daed2 --- /dev/null +++ b/target/linux/generic/files/include/linux/rtl8366.h @@ -0,0 +1,40 @@ +/* + * Platform data definition for the Realtek RTL8366RB/S ethernet switch driver + * + * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RTL8366_H +#define _RTL8366_H + +#define RTL8366_DRIVER_NAME "rtl8366" +#define RTL8366S_DRIVER_NAME "rtl8366s" +#define RTL8366RB_DRIVER_NAME "rtl8366rb" + +enum rtl8366_type { + RTL8366_TYPE_UNKNOWN, + RTL8366_TYPE_S, + RTL8366_TYPE_RB, +}; + +struct rtl8366_initval { + unsigned reg; + u16 val; +}; + +struct rtl8366_platform_data { + unsigned gpio_sda; + unsigned gpio_sck; + void (*hw_reset)(bool active); + + unsigned num_initvals; + struct rtl8366_initval *initvals; +}; + +enum rtl8366_type rtl8366_smi_detect(struct rtl8366_platform_data *pdata); + +#endif /* _RTL8366_H */ diff --git a/target/linux/generic/files/include/linux/rtl8367.h b/target/linux/generic/files/include/linux/rtl8367.h new file mode 100644 index 0000000..855de6a --- /dev/null +++ b/target/linux/generic/files/include/linux/rtl8367.h @@ -0,0 +1,60 @@ +/* + * Platform data definition for the Realtek RTL8367 ethernet switch driver + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef _RTL8367_H +#define _RTL8367_H + +#define RTL8367_DRIVER_NAME "rtl8367" +#define RTL8367B_DRIVER_NAME "rtl8367b" + +enum rtl8367_port_speed { + RTL8367_PORT_SPEED_10 = 0, + RTL8367_PORT_SPEED_100, + RTL8367_PORT_SPEED_1000, +}; + +struct rtl8367_port_ability { + int force_mode; + int nway; + int txpause; + int rxpause; + int link; + int duplex; + enum rtl8367_port_speed speed; +}; + +enum rtl8367_extif_mode { + RTL8367_EXTIF_MODE_DISABLED = 0, + RTL8367_EXTIF_MODE_RGMII, + RTL8367_EXTIF_MODE_MII_MAC, + RTL8367_EXTIF_MODE_MII_PHY, + RTL8367_EXTIF_MODE_TMII_MAC, + RTL8367_EXTIF_MODE_TMII_PHY, + RTL8367_EXTIF_MODE_GMII, + RTL8367_EXTIF_MODE_RGMII_33V, +}; + +struct rtl8367_extif_config { + unsigned int txdelay; + unsigned int rxdelay; + enum rtl8367_extif_mode mode; + struct rtl8367_port_ability ability; +}; + +struct rtl8367_platform_data { + unsigned gpio_sda; + unsigned gpio_sck; + void (*hw_reset)(bool active); + + struct rtl8367_extif_config *extif0_cfg; + struct rtl8367_extif_config *extif1_cfg; +}; + +#endif /* _RTL8367_H */ diff --git a/target/linux/generic/files/include/linux/switch.h b/target/linux/generic/files/include/linux/switch.h new file mode 100644 index 0000000..4291364 --- /dev/null +++ b/target/linux/generic/files/include/linux/switch.h @@ -0,0 +1,169 @@ +/* + * switch.h: Switch configuration API + * + * Copyright (C) 2008 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _LINUX_SWITCH_H +#define _LINUX_SWITCH_H + +#include +#include + +struct switch_dev; +struct switch_op; +struct switch_val; +struct switch_attr; +struct switch_attrlist; +struct switch_led_trigger; + +int register_switch(struct switch_dev *dev, struct net_device *netdev); +void unregister_switch(struct switch_dev *dev); + +/** + * struct switch_attrlist - attribute list + * + * @n_attr: number of attributes + * @attr: pointer to the attributes array + */ +struct switch_attrlist { + int n_attr; + const struct switch_attr *attr; +}; + +enum switch_port_speed { + SWITCH_PORT_SPEED_UNKNOWN = 0, + SWITCH_PORT_SPEED_10 = 10, + SWITCH_PORT_SPEED_100 = 100, + SWITCH_PORT_SPEED_1000 = 1000, +}; + +struct switch_port_link { + bool link; + bool duplex; + bool aneg; + bool tx_flow; + bool rx_flow; + enum switch_port_speed speed; + /* in ethtool adv_t format */ + u32 eee; +}; + +struct switch_port_stats { + unsigned long tx_bytes; + unsigned long rx_bytes; +}; + +/** + * struct switch_dev_ops - switch driver operations + * + * @attr_global: global switch attribute list + * @attr_port: port attribute list + * @attr_vlan: vlan attribute list + * + * Callbacks: + * + * @get_vlan_ports: read the port list of a VLAN + * @set_vlan_ports: set the port list of a VLAN + * + * @get_port_pvid: get the primary VLAN ID of a port + * @set_port_pvid: set the primary VLAN ID of a port + * + * @apply_config: apply all changed settings to the switch + * @reset_switch: resetting the switch + */ +struct switch_dev_ops { + struct switch_attrlist attr_global, attr_port, attr_vlan; + + int (*get_vlan_ports)(struct switch_dev *dev, struct switch_val *val); + int (*set_vlan_ports)(struct switch_dev *dev, struct switch_val *val); + + int (*get_port_pvid)(struct switch_dev *dev, int port, int *val); + int (*set_port_pvid)(struct switch_dev *dev, int port, int val); + + int (*apply_config)(struct switch_dev *dev); + int (*reset_switch)(struct switch_dev *dev); + + int (*get_port_link)(struct switch_dev *dev, int port, + struct switch_port_link *link); + int (*get_port_stats)(struct switch_dev *dev, int port, + struct switch_port_stats *stats); +}; + +struct switch_dev { + struct device_node *of_node; + const struct switch_dev_ops *ops; + /* will be automatically filled */ + char devname[IFNAMSIZ]; + + const char *name; + /* NB: either alias or netdev must be set */ + const char *alias; + struct net_device *netdev; + + int ports; + int vlans; + int cpu_port; + + /* the following fields are internal for swconfig */ + int id; + struct list_head dev_list; + unsigned long def_global, def_port, def_vlan; + + struct mutex sw_mutex; + struct switch_port *portbuf; + struct switch_portmap *portmap; + + char buf[128]; + +#ifdef CONFIG_SWCONFIG_LEDS + struct switch_led_trigger *led_trigger; +#endif +}; + +struct switch_port { + u32 id; + u32 flags; +}; + +struct switch_portmap { + u32 virt; + const char *s; +}; + +struct switch_val { + const struct switch_attr *attr; + int port_vlan; + int len; + union { + const char *s; + u32 i; + struct switch_port *ports; + } value; +}; + +struct switch_attr { + int disabled; + int type; + const char *name; + const char *description; + + int (*set)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); + int (*get)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); + + /* for driver internal use */ + int id; + int ofs; + int max; +}; + +#endif /* _LINUX_SWITCH_H */ diff --git a/target/linux/generic/files/include/uapi/linux/switch.h b/target/linux/generic/files/include/uapi/linux/switch.h new file mode 100644 index 0000000..a59b239 --- /dev/null +++ b/target/linux/generic/files/include/uapi/linux/switch.h @@ -0,0 +1,103 @@ +/* + * switch.h: Switch configuration API + * + * Copyright (C) 2008 Felix Fietkau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _UAPI_LINUX_SWITCH_H +#define _UAPI_LINUX_SWITCH_H + +#include +#include +#include +#include +#ifndef __KERNEL__ +#include +#include +#include +#endif + +/* main attributes */ +enum { + SWITCH_ATTR_UNSPEC, + /* global */ + SWITCH_ATTR_TYPE, + /* device */ + SWITCH_ATTR_ID, + SWITCH_ATTR_DEV_NAME, + SWITCH_ATTR_ALIAS, + SWITCH_ATTR_NAME, + SWITCH_ATTR_VLANS, + SWITCH_ATTR_PORTS, + SWITCH_ATTR_PORTMAP, + SWITCH_ATTR_CPU_PORT, + /* attributes */ + SWITCH_ATTR_OP_ID, + SWITCH_ATTR_OP_TYPE, + SWITCH_ATTR_OP_NAME, + SWITCH_ATTR_OP_PORT, + SWITCH_ATTR_OP_VLAN, + SWITCH_ATTR_OP_VALUE_INT, + SWITCH_ATTR_OP_VALUE_STR, + SWITCH_ATTR_OP_VALUE_PORTS, + SWITCH_ATTR_OP_DESCRIPTION, + /* port lists */ + SWITCH_ATTR_PORT, + SWITCH_ATTR_MAX +}; + +enum { + /* port map */ + SWITCH_PORTMAP_PORTS, + SWITCH_PORTMAP_SEGMENT, + SWITCH_PORTMAP_VIRT, + SWITCH_PORTMAP_MAX +}; + +/* commands */ +enum { + SWITCH_CMD_UNSPEC, + SWITCH_CMD_GET_SWITCH, + SWITCH_CMD_NEW_ATTR, + SWITCH_CMD_LIST_GLOBAL, + SWITCH_CMD_GET_GLOBAL, + SWITCH_CMD_SET_GLOBAL, + SWITCH_CMD_LIST_PORT, + SWITCH_CMD_GET_PORT, + SWITCH_CMD_SET_PORT, + SWITCH_CMD_LIST_VLAN, + SWITCH_CMD_GET_VLAN, + SWITCH_CMD_SET_VLAN +}; + +/* data types */ +enum switch_val_type { + SWITCH_TYPE_UNSPEC, + SWITCH_TYPE_INT, + SWITCH_TYPE_STRING, + SWITCH_TYPE_PORTS, + SWITCH_TYPE_NOVAL, +}; + +/* port nested attributes */ +enum { + SWITCH_PORT_UNSPEC, + SWITCH_PORT_ID, + SWITCH_PORT_FLAG_TAGGED, + SWITCH_PORT_ATTR_MAX +}; + +#define SWITCH_ATTR_DEFAULTS_OFFSET 0x1000 + + +#endif /* _UAPI_LINUX_SWITCH_H */ diff --git a/target/linux/generic/image/Makefile b/target/linux/generic/image/Makefile new file mode 100644 index 0000000..e733e0a --- /dev/null +++ b/target/linux/generic/image/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (C) 2006-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +# use default targets for everything + +$(eval $(call BuildImage)) diff --git a/target/linux/generic/image/initramfs-base-files.txt b/target/linux/generic/image/initramfs-base-files.txt new file mode 100644 index 0000000..eda5d0d --- /dev/null +++ b/target/linux/generic/image/initramfs-base-files.txt @@ -0,0 +1,9 @@ +nod /dev/console 600 0 0 c 5 1 +nod /dev/null 666 0 0 c 1 3 +nod /dev/zero 666 0 0 c 1 5 +nod /dev/tty 666 0 0 c 5 0 +nod /dev/tty0 660 0 0 c 4 0 +nod /dev/tty1 660 0 0 c 4 1 +nod /dev/random 666 0 0 c 1 8 +nod /dev/urandom 666 0 0 c 1 9 +dir /dev/pts 755 0 0 diff --git a/target/linux/generic/image/lzma-loader/Makefile b/target/linux/generic/image/lzma-loader/Makefile new file mode 100644 index 0000000..d75a446 --- /dev/null +++ b/target/linux/generic/image/lzma-loader/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME := loader +PKG_VERSION := 0.05 + +PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)-$(PKG_VERSION)$(LOADER_TYPE) + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +$(PKG_BUILD_DIR)/lzma.elf: $(PKG_BUILD_DIR)/.prepared $(PKG_BUILD_DIR)/vmlinux.lzma + PATH="$(TARGET_PATH)" $(MAKE) -C $(PKG_BUILD_DIR) \ + CC="$(TARGET_CC)" CROSS_COMPILE="$(TARGET_CROSS)" \ + RAMSIZE=$(RAMSIZE) \ + LOADADDR=$(LOADADDR) \ + KERNEL_ENTRY=$(KERNEL_ENTRY) \ + IMAGE_COPY=$(IMAGE_COPY) + + +$(PKG_BUILD_DIR)/vmlinux.lzma: $(KDIR)/vmlinux.lzma + $(CP) $< $@ + +$(KDIR)/loader$(LOADER_TYPE).elf: $(PKG_BUILD_DIR)/lzma.elf + $(CP) $< $@ + +$(KDIR)/loader$(LOADER_TYPE).bin: $(PKG_BUILD_DIR)/lzma.bin + $(CP) $< $@ + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: $(KDIR)/loader$(LOADER_TYPE).elf $(KDIR)/loader$(LOADER_TYPE).bin +install: + +clean: + rm -rf $(PKG_BUILD_DIR) + rm -f $(KDIR)/loader.elf + rm -f $(KDIR)/loader.bin diff --git a/target/linux/generic/image/lzma-loader/src/LzmaDecode.c b/target/linux/generic/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 0000000..c90a0d3 --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,590 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.22 Copyright (c) 1999-2005 Igor Pavlov (2005-06-10) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#ifndef Byte +#define Byte unsigned char +#endif + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \ + BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +#if 0 +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} +#endif + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + return LZMA_RESULT_DATA_ERROR; + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/generic/image/lzma-loader/src/LzmaDecode.h b/target/linux/generic/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 0000000..213062a --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,131 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.21 Copyright (c) 1999-2005 Igor Pavlov (2005-06-08) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +/* #define _LZMA_SYSTEM_SIZE_T */ +/* Use system's size_t. You can use it to enable 64-bit sizes supporting*/ + +#ifndef UInt32 +#ifdef _LZMA_UINT32_IS_ULONG +#define UInt32 unsigned long +#else +#define UInt32 unsigned int +#endif +#endif + +#ifndef SizeT +#ifdef _LZMA_SYSTEM_SIZE_T +#include +#define SizeT size_t +#else +#define SizeT UInt32 +#endif +#endif + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb unsigned short +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/target/linux/generic/image/lzma-loader/src/Makefile b/target/linux/generic/image/lzma-loader/src/Makefile new file mode 100644 index 0000000..910172c --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/Makefile @@ -0,0 +1,68 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +RAMSTART = 0x80000000 +RAMSIZE = 0x00100000 # 1MB +LOADADDR = 0x80400000 # RAM start + 4M +KERNEL_ENTRY = 0x80001000 +IMAGE_COPY:=0 + +CROSS_COMPILE = mips-linux- + +OBJCOPY:= $(CROSS_COMPILE)objcopy -O binary -R .reginfo -R .note -R .comment -R .mdebug -S +CFLAGS := -fno-builtin -Os -G 0 -ffunction-sections -mno-abicalls -fno-pic -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap -Wall -DRAMSTART=${RAMSTART} -DRAMSIZE=${RAMSIZE} -DKERNEL_ENTRY=${KERNEL_ENTRY} -D_LZMA_IN_CB +ifeq ($(IMAGE_COPY),1) +CFLAGS += -DLOADADDR=${LOADADDR} -DIMAGE_COPY=1 +endif + +.S.s: + $(CPP) $(CFLAGS) $< -o $*.s +.S.o: + $(CC) $(CFLAGS) -c $< -o $*.o +.c.o: + $(CC) $(CFLAGS) -c $< -o $*.o + +CC = $(CROSS_COMPILE)gcc +LD = $(CROSS_COMPILE)ld +OBJDUMP = $(CROSS_COMPILE)objdump + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +# Drop some uninteresting sections in the kernel. +# This is only relevant for ELF kernels but doesn't hurt a.out +drop-sections = .reginfo .mdebug .comment +strip-flags = $(addprefix --remove-section=,$(drop-sections)) + +all : lzma.elf lzma.bin + +lzma.lds: lzma.lds.in + sed -e 's,@LOADADDR@,$(LOADADDR),g' -e 's,@ENTRY@,_start,g' $< >$@ + +kernel.o: vmlinux.lzma lzma.lds + $(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $< + +lzma.bin: lzma.elf + $(OBJCOPY) $< $@ + +ifeq ($(IMAGE_COPY),1) +LOADER_ENTRY ?= $(KERNEL_ENTRY) +lzma.o: decompress.o LzmaDecode.o kernel.o + sed -e 's,@LOADADDR@,$(LOADADDR),g' -e 's,@ENTRY@,entry,g' lzma.lds.in >lzma-stage2.lds + $(LD) -static --no-warn-mismatch -e entry -Tlzma-stage2.lds -o temp-$@ $^ + $(OBJCOPY) temp-$@ lzma.tmp + @echo "SECTIONS { .data : { code_start = .; *(.data) code_stop = .; }}" > lzma-data.lds + $(LD) -no-warn-mismatch -T lzma-data.lds -r -o $@ -b binary lzma.tmp --oformat $(O_FORMAT) + +lzma.elf: start.o lzma.o + sed -e 's,@LOADADDR@,$(LOADER_ENTRY),g' lzma-copy.lds.in >lzma-copy.lds + $(LD) -s -Tlzma-copy.lds -o $@ $^ +else +lzma.elf: start.o decompress.o LzmaDecode.o kernel.o + $(LD) -s -Tlzma.lds -o $@ $^ +endif + +clean: + rm -f *.o lzma.elf lzma.bin *.tmp *.lds diff --git a/target/linux/generic/image/lzma-loader/src/decompress.c b/target/linux/generic/image/lzma-loader/src/decompress.c new file mode 100644 index 0000000..45ac509 --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/decompress.c @@ -0,0 +1,157 @@ +/* + * LZMA compressed kernel decompressor for bcm947xx boards + * + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * + * Please note, this was code based on the bunzip2 decompressor code + * by Manuel Novoa III (mjn3@codepoet.org), although the only thing left + * is an idea and part of original vendor code + * + * + * 12-Mar-2005 Mineharu Takahara + * pass actual output size to decoder (stream mode + * compressed input is not a requirement anymore) + * + * 24-Apr-2005 Oleg I. Vdovikin + * reordered functions using lds script, removed forward decl + * + * ??-Nov-2005 Mike Baker + * reorder the script as an lzma wrapper; do not depend on flash access + */ + +#include "LzmaDecode.h" + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) + +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 + +#define cache_unroll(base,op) \ + __asm__ __volatile__( \ + ".set noreorder;\n" \ + ".set mips3;\n" \ + "cache %1, (%0);\n" \ + ".set mips0;\n" \ + ".set reorder\n" \ + : \ + : "r" (base), \ + "i" (op)); + + +static __inline__ void blast_icache(unsigned long size, unsigned long lsize) +{ + unsigned long start = KSEG0; + unsigned long end = (start + size); + + while(start < end) { + cache_unroll(start,Index_Invalidate_I); + start += lsize; + } +} + +static __inline__ void blast_dcache(unsigned long size, unsigned long lsize) +{ + unsigned long start = KSEG0; + unsigned long end = (start + size); + + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_D); + start += lsize; + } +} + +unsigned char *data; + +static int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize) +{ + *bufferSize = 1; + *buffer = data; + ++data; + return LZMA_RESULT_OK; +} + +static __inline__ unsigned char get_byte(void) +{ + unsigned char *buffer; + UInt32 fake; + + return read_byte(0, &buffer, &fake), *buffer; +} + +/* This puts lzma workspace 128k below RAM end. + * That should be enough for both lzma and stack + */ +static char *buffer = (char *)(RAMSTART + RAMSIZE - 0x00020000); +extern char lzma_start[]; +extern char lzma_end[]; + +/* should be the first function */ +void entry(unsigned long icache_size, unsigned long icache_lsize, + unsigned long dcache_size, unsigned long dcache_lsize) +{ + unsigned int i; /* temp value */ + unsigned int osize; /* uncompressed size */ + volatile unsigned int arg0, arg1, arg2, arg3; + + /* restore argument registers */ + __asm__ __volatile__ ("ori %0, $12, 0":"=r"(arg0)); + __asm__ __volatile__ ("ori %0, $13, 0":"=r"(arg1)); + __asm__ __volatile__ ("ori %0, $14, 0":"=r"(arg2)); + __asm__ __volatile__ ("ori %0, $15, 0":"=r"(arg3)); + + ILzmaInCallback callback; + CLzmaDecoderState vs; + callback.Read = read_byte; + + data = lzma_start; + + /* lzma args */ + i = get_byte(); + vs.Properties.lc = i % 9, i = i / 9; + vs.Properties.lp = i % 5, vs.Properties.pb = i / 5; + + vs.Probs = (CProb *)buffer; + + /* skip rest of the LZMA coder property */ + for (i = 0; i < 4; i++) + get_byte(); + + /* read the lower half of uncompressed size in the header */ + osize = ((unsigned int)get_byte()) + + ((unsigned int)get_byte() << 8) + + ((unsigned int)get_byte() << 16) + + ((unsigned int)get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + for (i = 0; i < 4; i++) + get_byte(); + + /* decompress kernel */ + if ((i = LzmaDecode(&vs, &callback, + (unsigned char*)KERNEL_ENTRY, osize, &osize)) == LZMA_RESULT_OK) + { + blast_dcache(dcache_size, dcache_lsize); + blast_icache(icache_size, icache_lsize); + + /* Jump to load address */ + ((void (*)(int a0, int a1, int a2, int a3)) KERNEL_ENTRY)(arg0, arg1, arg2, arg3); + } +} diff --git a/target/linux/generic/image/lzma-loader/src/lzma-copy.lds.in b/target/linux/generic/image/lzma-loader/src/lzma-copy.lds.in new file mode 100644 index 0000000..fbc87ab --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/lzma-copy.lds.in @@ -0,0 +1,20 @@ +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = @LOADADDR@; + .text : + { + _ftext = . ; + *(.text) + *(.rodata) + } =0 + + .reginfo : { *(.reginfo) } + + .bss : + { + *(.bss) + } +} diff --git a/target/linux/generic/image/lzma-loader/src/lzma.lds.in b/target/linux/generic/image/lzma-loader/src/lzma.lds.in new file mode 100644 index 0000000..6021cec --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/lzma.lds.in @@ -0,0 +1,24 @@ +OUTPUT_ARCH(mips) +ENTRY(@ENTRY@) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = @LOADADDR@; + .text : + { + _ftext = . ; + *(.text.entry) + *(.text) + *(.rodata) + lzma_start = .; + kernel.o + lzma_end = .; + } =0 + + .reginfo : { *(.reginfo) } + + .bss : + { + *(.bss) + } +} diff --git a/target/linux/generic/image/lzma-loader/src/print.c b/target/linux/generic/image/lzma-loader/src/print.c new file mode 100644 index 0000000..950687b --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/print.c @@ -0,0 +1,324 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "print.h" + +/* macros */ +#define IsDigit(x) ( ((x) >= '0') && ((x) <= '9') ) +#define Ctod(x) ( (x) - '0') + +/* forward declaration */ +extern int PrintChar(char *, char, int, int); +extern int PrintString(char *, char *, int, int); +extern int PrintNum(char *, unsigned long, int, int, int, int, char, int); + +/* private variable */ +static const char theFatalMsg[] = "fatal error in lp_Print!"; + +/* -*- + * A low level printf() function. + */ +void +lp_Print(void (*output)(void *, char *, int), + void * arg, + char *fmt, + va_list ap) +{ + +#define OUTPUT(arg, s, l) \ + { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \ + (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \ + } else { \ + (*output)(arg, s, l); \ + } \ + } + + char buf[LP_MAX_BUF]; + + char c; + char *s; + long int num; + + int longFlag; + int negFlag; + int width; + int prec; + int ladjust; + char padc; + + int length; + + for(;;) { + { + /* scan for the next '%' */ + char *fmtStart = fmt; + while ( (*fmt != '\0') && (*fmt != '%')) { + fmt ++; + } + + /* flush the string found so far */ + OUTPUT(arg, fmtStart, fmt-fmtStart); + + /* are we hitting the end? */ + if (*fmt == '\0') break; + } + + /* we found a '%' */ + fmt ++; + + /* check for long */ + if (*fmt == 'l') { + longFlag = 1; + fmt ++; + } else { + longFlag = 0; + } + + /* check for other prefixes */ + width = 0; + prec = -1; + ladjust = 0; + padc = ' '; + + if (*fmt == '-') { + ladjust = 1; + fmt ++; + } + + if (*fmt == '0') { + padc = '0'; + fmt++; + } + + if (IsDigit(*fmt)) { + while (IsDigit(*fmt)) { + width = 10 * width + Ctod(*fmt++); + } + } + + if (*fmt == '.') { + fmt ++; + if (IsDigit(*fmt)) { + prec = 0; + while (IsDigit(*fmt)) { + prec = prec*10 + Ctod(*fmt++); + } + } + } + + + /* check format flag */ + negFlag = 0; + switch (*fmt) { + case 'b': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'd': + case 'D': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + if (num < 0) { + num = - num; + negFlag = 1; + } + length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'o': + case 'O': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'u': + case 'U': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'x': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'X': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1); + OUTPUT(arg, buf, length); + break; + + case 'c': + c = (char)va_arg(ap, int); + length = PrintChar(buf, c, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case 's': + s = (char*)va_arg(ap, char *); + length = PrintString(buf, s, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case '\0': + fmt --; + break; + + default: + /* output this char as it is */ + OUTPUT(arg, fmt, 1); + } /* switch (*fmt) */ + + fmt ++; + } /* for(;;) */ + + /* special termination call */ + OUTPUT(arg, "\0", 1); +} + + +/* --------------- local help functions --------------------- */ +int +PrintChar(char * buf, char c, int length, int ladjust) +{ + int i; + + if (length < 1) length = 1; + if (ladjust) { + *buf = c; + for (i=1; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-1; i++) buf[i] = ' '; + buf[length - 1] = c; + } + return length; +} + +int +PrintString(char * buf, char* s, int length, int ladjust) +{ + int i; + int len=0; + char* s1 = s; + while (*s1++) len++; + if (length < len) length = len; + + if (ladjust) { + for (i=0; i< len; i++) buf[i] = s[i]; + for (i=len; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-len; i++) buf[i] = ' '; + for (i=length-len; i < length; i++) buf[i] = s[i-length+len]; + } + return length; +} + +int +PrintNum(char * buf, unsigned long u, int base, int negFlag, + int length, int ladjust, char padc, int upcase) +{ + /* algorithm : + * 1. prints the number from left to right in reverse form. + * 2. fill the remaining spaces with padc if length is longer than + * the actual length + * TRICKY : if left adjusted, no "0" padding. + * if negtive, insert "0" padding between "0" and number. + * 3. if (!ladjust) we reverse the whole string including paddings + * 4. otherwise we only reverse the actual string representing the num. + */ + + int actualLength =0; + char *p = buf; + int i; + + do { + int tmp = u %base; + if (tmp <= 9) { + *p++ = '0' + tmp; + } else if (upcase) { + *p++ = 'A' + tmp - 10; + } else { + *p++ = 'a' + tmp - 10; + } + u /= base; + } while (u != 0); + + if (negFlag) { + *p++ = '-'; + } + + /* figure out actual length and adjust the maximum length */ + actualLength = p - buf; + if (length < actualLength) length = actualLength; + + /* add padding */ + if (ladjust) { + padc = ' '; + } + if (negFlag && !ladjust && (padc == '0')) { + for (i = actualLength-1; i< length-1; i++) buf[i] = padc; + buf[length -1] = '-'; + } else { + for (i = actualLength; i< length; i++) buf[i] = padc; + } + + + /* prepare to reverse the string */ + { + int begin = 0; + int end; + if (ladjust) { + end = actualLength - 1; + } else { + end = length -1; + } + + while (end > begin) { + char tmp = buf[begin]; + buf[begin] = buf[end]; + buf[end] = tmp; + begin ++; + end --; + } + } + + /* adjust the string pointer */ + return length; +} diff --git a/target/linux/generic/image/lzma-loader/src/print.h b/target/linux/generic/image/lzma-loader/src/print.h new file mode 100644 index 0000000..b051463 --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/print.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _print_h_ +#define _print_h_ + +#include + +/* this is the maximum width for a variable */ +#define LP_MAX_BUF 80 + +/* -*- + * output function takes an void pointer which is passed in as the + * second argument in lp_Print(). This black-box argument gives output + * function a way to track state. + * + * The second argument in output function is a pointer to char buffer. + * The third argument specifies the number of chars to outputed. + * + * output function cannot assume the buffer is null-terminated after + * l number of chars. + */ +void lp_Print(void (*output)(void *, char *, int), + void * arg, + char *fmt, + va_list ap); + +#endif diff --git a/target/linux/generic/image/lzma-loader/src/printf.c b/target/linux/generic/image/lzma-loader/src/printf.c new file mode 100644 index 0000000..49bd50d --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/printf.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "printf.h" +#include "print.h" +#include "uart16550.h" + +static void myoutput(void *arg, char *s, int l) +{ + int i; + + // special termination call + if ((l==1) && (s[0] == '\0')) return; + + for (i=0; i< l; i++) { + Uart16550Put(s[i]); + if (s[i] == '\n') Uart16550Put('\r'); + } +} + +void printf(char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + lp_Print(myoutput, 0, fmt, ap); + va_end(ap); +} diff --git a/target/linux/generic/image/lzma-loader/src/printf.h b/target/linux/generic/image/lzma-loader/src/printf.h new file mode 100644 index 0000000..9b1c1df --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/printf.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _printf_h_ +#define _printf_h_ + +#include +void printf(char *fmt, ...); + +#endif /* _printf_h_ */ diff --git a/target/linux/generic/image/lzma-loader/src/start.S b/target/linux/generic/image/lzma-loader/src/start.S new file mode 100644 index 0000000..8642933 --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/start.S @@ -0,0 +1,160 @@ +#include +#include + +#define KSEG0 0x80000000 + +#define C0_CONFIG $16 +#define C0_TAGLO $28 +#define C0_TAGHI $29 + +#define CONF1_DA_SHIFT 7 /* D$ associativity */ +#define CONF1_DA_MASK 0x00000380 +#define CONF1_DA_BASE 1 +#define CONF1_DL_SHIFT 10 /* D$ line size */ +#define CONF1_DL_MASK 0x00001c00 +#define CONF1_DL_BASE 2 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */ +#define CONF1_DS_MASK 0x0000e000 +#define CONF1_DS_BASE 64 +#define CONF1_IA_SHIFT 16 /* I$ associativity */ +#define CONF1_IA_MASK 0x00070000 +#define CONF1_IA_BASE 1 +#define CONF1_IL_SHIFT 19 /* I$ line size */ +#define CONF1_IL_MASK 0x00380000 +#define CONF1_IL_BASE 2 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */ +#define CONF1_IS_MASK 0x01c00000 +#define CONF1_IS_BASE 64 + +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 + +LEAF(_start) + + .set mips32 + .set noreorder + + /* save argument registers */ + move t4, a0 + move t5, a1 + move t6, a2 + move t7, a3 + + /* set up stack */ + li sp, RAMSTART + RAMSIZE - 16 + +#ifdef IMAGE_COPY + /* Copy decompressor code to the right place */ + li t2, LOADADDR + add a0, t2, 0 + la a1, code_start + la a2, code_stop +$L1: + lw t0, 0(a1) + sw t0, 0(a0) + add a1, 4 + add a0, 4 + blt a1, a2, $L1 + nop +#endif + + /* At this point we need to invalidate dcache and */ + /* icache before jumping to new code */ + +1: /* Get cache sizes */ + mfc0 s0,C0_CONFIG,1 + + li s1,CONF1_DL_MASK + and s1,s0 + beq s1,zero,nodc + nop + + srl s1,CONF1_DL_SHIFT + li t0,CONF1_DL_BASE + sll s1,t0,s1 /* s1 has D$ cache line size */ + + li s2,CONF1_DA_MASK + and s2,s0 + srl s2,CONF1_DA_SHIFT + addiu s2,CONF1_DA_BASE /* s2 now has D$ associativity */ + + li t0,CONF1_DS_MASK + and t0,s0 + srl t0,CONF1_DS_SHIFT + li s3,CONF1_DS_BASE + sll s3,s3,t0 /* s3 has D$ sets per way */ + + multu s2,s3 /* sets/way * associativity */ + mflo t0 /* total cache lines */ + + multu s1,t0 /* D$ linesize * lines */ + mflo s2 /* s2 is now D$ size in bytes */ + + /* Initilize the D$: */ + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + li t0,KSEG0 /* Just an address for the first $ line */ + addu t1,t0,s2 /* + size of cache == end */ + +1: cache Index_Writeback_Inv_D,0(t0) + bne t0,t1,1b + addu t0,s1 + +nodc: + /* Now we get to do it all again for the I$ */ + + move s3,zero /* just in case there is no icache */ + move s4,zero + + li t0,CONF1_IL_MASK + and t0,s0 + beq t0,zero,noic + nop + + srl t0,CONF1_IL_SHIFT + li s3,CONF1_IL_BASE + sll s3,t0 /* s3 has I$ cache line size */ + + li t0,CONF1_IA_MASK + and t0,s0 + srl t0,CONF1_IA_SHIFT + addiu s4,t0,CONF1_IA_BASE /* s4 now has I$ associativity */ + + li t0,CONF1_IS_MASK + and t0,s0 + srl t0,CONF1_IS_SHIFT + li s5,CONF1_IS_BASE + sll s5,t0 /* s5 has I$ sets per way */ + + multu s4,s5 /* sets/way * associativity */ + mflo t0 /* s4 is now total cache lines */ + + multu s3,t0 /* I$ linesize * lines */ + mflo s4 /* s4 is cache size in bytes */ + + /* Initilize the I$: */ + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + li t0,KSEG0 /* Just an address for the first $ line */ + addu t1,t0,s4 /* + size of cache == end */ + +1: cache Index_Invalidate_I,0(t0) + bne t0,t1,1b + addu t0,s3 +noic: + /* jump to main */ + move a0,s3 /* icache line size */ + move a1,s4 /* icache size */ + move a2,s1 /* dcache line size */ +#ifdef IMAGE_COPY + jal t2 +#else + jal entry +#endif + move a3,s2 /* dcache size */ + + .set reorder +END(_start) + diff --git a/target/linux/generic/image/lzma-loader/src/uart16550.c b/target/linux/generic/image/lzma-loader/src/uart16550.c new file mode 100644 index 0000000..7df5727 --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/uart16550.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + + +#include "uart16550.h" + +/* === CONFIG === */ + +#define BASE 0xb8058000 +#define MAX_BAUD 1152000 +#define REG_OFFSET 4 + +/* === END OF CONFIG === */ + +/* register offset */ +#define OFS_RCV_BUFFER (0*REG_OFFSET) +#define OFS_TRANS_HOLD (0*REG_OFFSET) +#define OFS_SEND_BUFFER (0*REG_OFFSET) +#define OFS_INTR_ENABLE (1*REG_OFFSET) +#define OFS_INTR_ID (2*REG_OFFSET) +#define OFS_DATA_FORMAT (3*REG_OFFSET) +#define OFS_LINE_CONTROL (3*REG_OFFSET) +#define OFS_MODEM_CONTROL (4*REG_OFFSET) +#define OFS_RS232_OUTPUT (4*REG_OFFSET) +#define OFS_LINE_STATUS (5*REG_OFFSET) +#define OFS_MODEM_STATUS (6*REG_OFFSET) +#define OFS_RS232_INPUT (6*REG_OFFSET) +#define OFS_SCRATCH_PAD (7*REG_OFFSET) + +#define OFS_DIVISOR_LSB (0*REG_OFFSET) +#define OFS_DIVISOR_MSB (1*REG_OFFSET) + + +/* memory-mapped read/write of the port */ +#define UART16550_READ(y) (*((volatile uint32*)(BASE + y))) +#define UART16550_WRITE(y, z) ((*((volatile uint32*)(BASE + y))) = z) + +#define DEBUG_LED (*(unsigned short*)0xb7ffffc0) +#define OutputLED(x) (DEBUG_LED = x) + +void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop) +{ + /* disable interrupts */ + UART16550_WRITE(OFS_INTR_ENABLE, 0); + + /* set up buad rate */ + { + uint32 divisor; + + /* set DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x80); + + /* set divisor */ + divisor = MAX_BAUD / baud; + UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); + UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8); + + /* clear DIAB bit */ + UART16550_WRITE(OFS_LINE_CONTROL, 0x0); + } + + /* set data format */ + UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); +} + +uint8 Uart16550GetPoll() +{ + while((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0); + return UART16550_READ(OFS_RCV_BUFFER); +} + + +void Uart16550Put(uint8 byte) +{ + while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0); + UART16550_WRITE(OFS_SEND_BUFFER, byte); +} + diff --git a/target/linux/generic/image/lzma-loader/src/uart16550.h b/target/linux/generic/image/lzma-loader/src/uart16550.h new file mode 100644 index 0000000..b3fd6fd --- /dev/null +++ b/target/linux/generic/image/lzma-loader/src/uart16550.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _uart16550_h_ +#define _uart16550_h_ + +typedef unsigned char uint8; +typedef unsigned int uint32; + +#define UART16550_BAUD_2400 2400 +#define UART16550_BAUD_4800 4800 +#define UART16550_BAUD_9600 9600 +#define UART16550_BAUD_19200 19200 +#define UART16550_BAUD_38400 38400 +#define UART16550_BAUD_57600 57600 +#define UART16550_BAUD_115200 115200 + +#define UART16550_PARITY_NONE 0 +#define UART16550_PARITY_ODD 0x08 +#define UART16550_PARITY_EVEN 0x18 +#define UART16550_PARITY_MARK 0x28 +#define UART16550_PARITY_SPACE 0x38 + +#define UART16550_DATA_5BIT 0x0 +#define UART16550_DATA_6BIT 0x1 +#define UART16550_DATA_7BIT 0x2 +#define UART16550_DATA_8BIT 0x3 + +#define UART16550_STOP_1BIT 0x0 +#define UART16550_STOP_2BIT 0x4 + +void Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop); + +/* blocking call */ +uint8 Uart16550GetPoll(); + +void Uart16550Put(uint8 byte); + +#endif diff --git a/target/linux/generic/image/relocate/Makefile b/target/linux/generic/image/relocate/Makefile new file mode 100644 index 0000000..5f6ebeb --- /dev/null +++ b/target/linux/generic/image/relocate/Makefile @@ -0,0 +1,74 @@ +# +# Makefile for the kernel relocation stub for MIPS devices +# +# Copyright (C) 2011 Gabor Juhos +# Copyright (C) 2015 Felix Fietkau +# +# Some parts of this file was based on the OpenWrt specific lzma-loader +# for the BCM47xx and ADM5120 based boards: +# Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) +# Copyright (C) 2005 Mineharu Takahara +# Copyright (C) 2005 by Oleg I. Vdovikin +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. +# + +LOADADDR := +LZMA_TEXT_START := 0x81000000 +LOADER_DATA := +BOARD := +FLASH_OFFS := +FLASH_MAX := +PLATFORM := +CACHELINE_SIZE := 32 + +CC := $(CROSS_COMPILE)gcc +LD := $(CROSS_COMPILE)ld +OBJCOPY := $(CROSS_COMPILE)objcopy +OBJDUMP := $(CROSS_COMPILE)objdump + +BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug -S + +CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \ + -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \ + -fno-common -ffreestanding -fhonour-copts \ + -mabi=32 -march=mips32r2 \ + -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap \ + -DCONFIG_CACHELINE_SIZE=$(CACHELINE_SIZE) \ + -DKERNEL_ADDR=$(KERNEL_ADDR) + +ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +LDFLAGS = -static --gc-sections -no-warn-mismatch +LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START) + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +OBJECTS := head.o + +all: head.o loader.bin + +# Don't build dependencies, this may die if $(CC) isn't gcc +dep: + +install: + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $< + +%.o : %.S + $(CC) $(ASFLAGS) -c -o $@ $< + +loader: $(OBJECTS) + $(LD) $(LDFLAGS) -o $@ $(OBJECTS) + +loader.bin: loader + $(OBJCOPY) $(BIN_FLAGS) $< $@ + +mrproper: clean + +clean: + rm -f loader *.elf *.bin *.o diff --git a/target/linux/generic/image/relocate/cacheops.h b/target/linux/generic/image/relocate/cacheops.h new file mode 100644 index 0000000..70bcad7 --- /dev/null +++ b/target/linux/generic/image/relocate/cacheops.h @@ -0,0 +1,85 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 + +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +#endif /* __ASM_CACHEOPS_H */ diff --git a/target/linux/generic/image/relocate/cp0regdef.h b/target/linux/generic/image/relocate/cp0regdef.h new file mode 100644 index 0000000..c1188ad --- /dev/null +++ b/target/linux/generic/image/relocate/cp0regdef.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * + * Copyright (C) 2001, Monta Vista Software + * Author: jsun@mvista.com or jsun@junsun.net + */ +#ifndef _cp0regdef_h_ +#define _cp0regdef_h_ + +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 + +#endif diff --git a/target/linux/generic/image/relocate/head.S b/target/linux/generic/image/relocate/head.S new file mode 100644 index 0000000..3e5b374 --- /dev/null +++ b/target/linux/generic/image/relocate/head.S @@ -0,0 +1,159 @@ +/* + * Kernel relocation stub for MIPS devices + * + * Copyright (C) 2015 Felix Fietkau + * + * Based on: + * + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "cp0regdef.h" +#include "cacheops.h" + +#define KSEG0 0x80000000 + + .macro ehb + sll zero, 3 + .endm + + .macro reset + li t0, 0xbe000034 + lw t1, 0(t0) + ori t1, 1 + sw t1, 0(t0) + .endm + + .text + +LEAF(startup) + .set noreorder + .set mips32 + + .fill 0x10000 + + mtc0 zero, CP0_WATCHLO # clear watch registers + mtc0 zero, CP0_WATCHHI + mtc0 zero, CP0_CAUSE # clear before writing status register + + mfc0 t0, CP0_STATUS + li t1, 0x1000001f + or t0, t1 + xori t0, 0x1f + mtc0 t0, CP0_STATUS + ehb + + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + ehb + + la t0, __reloc_label # get linked address of label + bal __reloc_label # branch and link to label to + nop # get actual address +__reloc_label: + subu t0, ra, t0 # get reloc_delta + + /* Copy our code to the right place */ + la t1, _code_start # get linked address of _code_start + la t2, _code_end # get linked address of _code_end + + addu t4, t2, t0 # calculate actual address of _code_end + lw t5, 0(t4) # get extra data size + + add t2, t5 + add t2, 4 + + add t0, t1 # calculate actual address of _code_start + +__reloc_copy: + lw t3, 0(t0) + sw t3, 0(t1) + add t1, 4 + blt t1, t2, __reloc_copy + add t0, 4 + + /* flush cache */ + la t0, _code_start + la t1, _code_end + + li t2, ~(CONFIG_CACHELINE_SIZE - 1) + and t0, t2 + and t1, t2 + li t2, CONFIG_CACHELINE_SIZE + + b __flush_check + nop + +__flush_line: + cache Hit_Writeback_Inv_D, 0(t0) + cache Hit_Invalidate_I, 0(t0) + add t0, t2 + +__flush_check: + bne t0, t1, __flush_line + nop + + sync + + la t0, __reloc_back + j t0 + nop + +__reloc_back: + la t0, _code_end + add t0, 4 + + addu t1, t0, t5 + + li t2, KERNEL_ADDR + +__kernel_copy: + lw t3, 0(t0) + sw t3, 0(t2) + add t0, 4 + blt t0, t1, __kernel_copy + add t2, 4 + + /* flush cache */ + li t0, KERNEL_ADDR + addu t1, t0, t5 + + add t1, CONFIG_CACHELINE_SIZE - 1 + li t2, ~(CONFIG_CACHELINE_SIZE - 1) + and t0, t2 + and t1, t2 + li t2, CONFIG_CACHELINE_SIZE + + b __kernel_flush_check + nop + +__kernel_flush_line: + cache Hit_Writeback_Inv_D, 0(t0) + cache Hit_Invalidate_I, 0(t0) + add t0, t2 + +__kernel_flush_check: + bne t0, t1, __kernel_flush_line + nop + + sync + + li t0, KERNEL_ADDR + jr t0 + nop + + .set reorder +END(startup) diff --git a/target/linux/generic/image/relocate/loader.lds b/target/linux/generic/image/relocate/loader.lds new file mode 100644 index 0000000..98ca209 --- /dev/null +++ b/target/linux/generic/image/relocate/loader.lds @@ -0,0 +1,16 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + _code_start = .; + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.data) + *(.data.*) + } + + . = ALIGN(32); + + _code_end = .; +} diff --git a/target/linux/generic/patches-3.18/000-keep_initrafs_the_default.patch b/target/linux/generic/patches-3.18/000-keep_initrafs_the_default.patch new file mode 100644 index 0000000..d4164ca --- /dev/null +++ b/target/linux/generic/patches-3.18/000-keep_initrafs_the_default.patch @@ -0,0 +1,25 @@ +Upstream changed the default rootfs to tmpfs when none has been passed +to the kernel - this doesn't fit our purposes, so change it back. + +Signed-off-by: Imre Kaloz + +--- a/init/do_mounts.c ++++ b/init/do_mounts.c +@@ -623,6 +623,7 @@ int __init init_rootfs(void) + if (err) + return err; + ++#if 0 + if (IS_ENABLED(CONFIG_TMPFS) && !saved_root_name[0] && + (!root_fs_names || strstr(root_fs_names, "tmpfs"))) { + err = shmem_init(); +@@ -630,6 +631,9 @@ int __init init_rootfs(void) + } else { + err = init_ramfs_fs(); + } ++#else ++ err = init_ramfs_fs(); ++#endif + + if (err) + unregister_filesystem(&rootfs_fs_type); diff --git a/target/linux/generic/patches-3.18/020-ssb_update.patch b/target/linux/generic/patches-3.18/020-ssb_update.patch new file mode 100644 index 0000000..f94d160 --- /dev/null +++ b/target/linux/generic/patches-3.18/020-ssb_update.patch @@ -0,0 +1,134 @@ +--- a/drivers/ssb/pcihost_wrapper.c ++++ b/drivers/ssb/pcihost_wrapper.c +@@ -11,15 +11,17 @@ + * Licensed under the GNU/GPL. See COPYING for details. + */ + ++#include + #include + #include + #include + #include + + +-#ifdef CONFIG_PM +-static int ssb_pcihost_suspend(struct pci_dev *dev, pm_message_t state) ++#ifdef CONFIG_PM_SLEEP ++static int ssb_pcihost_suspend(struct device *d) + { ++ struct pci_dev *dev = to_pci_dev(d); + struct ssb_bus *ssb = pci_get_drvdata(dev); + int err; + +@@ -28,17 +30,23 @@ static int ssb_pcihost_suspend(struct pc + return err; + pci_save_state(dev); + pci_disable_device(dev); +- pci_set_power_state(dev, pci_choose_state(dev, state)); ++ ++ /* if there is a wakeup enabled child device on ssb bus, ++ enable pci wakeup posibility. */ ++ device_set_wakeup_enable(d, d->power.wakeup_path); ++ ++ pci_prepare_to_sleep(dev); + + return 0; + } + +-static int ssb_pcihost_resume(struct pci_dev *dev) ++static int ssb_pcihost_resume(struct device *d) + { ++ struct pci_dev *dev = to_pci_dev(d); + struct ssb_bus *ssb = pci_get_drvdata(dev); + int err; + +- pci_set_power_state(dev, PCI_D0); ++ pci_back_from_sleep(dev); + err = pci_enable_device(dev); + if (err) + return err; +@@ -49,10 +57,12 @@ static int ssb_pcihost_resume(struct pci + + return 0; + } +-#else /* CONFIG_PM */ +-# define ssb_pcihost_suspend NULL +-# define ssb_pcihost_resume NULL +-#endif /* CONFIG_PM */ ++ ++static const struct dev_pm_ops ssb_pcihost_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(ssb_pcihost_suspend, ssb_pcihost_resume) ++}; ++ ++#endif /* CONFIG_PM_SLEEP */ + + static int ssb_pcihost_probe(struct pci_dev *dev, + const struct pci_device_id *id) +@@ -115,8 +125,9 @@ int ssb_pcihost_register(struct pci_driv + { + driver->probe = ssb_pcihost_probe; + driver->remove = ssb_pcihost_remove; +- driver->suspend = ssb_pcihost_suspend; +- driver->resume = ssb_pcihost_resume; ++#ifdef CONFIG_PM_SLEEP ++ driver->driver.pm = &ssb_pcihost_pm_ops; ++#endif + + return pci_register_driver(driver); + } +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -357,6 +357,16 @@ static void ssb_pcicore_init_hostmode(st + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, + SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); + ++ /* ++ * Accessing PCI config without a proper delay after devices reset (not ++ * GPIO reset) was causing reboots on WRT300N v1.0 (BCM4704). ++ * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it ++ * completely. Flushing all writes was also tested but with no luck. ++ * The same problem was reported for WRT350N v1 (BCM4705), so we just ++ * sleep here unconditionally. ++ */ ++ usleep_range(1000, 2000); ++ + /* Enable PCI bridge BAR0 prefetch and burst */ + val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); +--- a/drivers/ssb/main.c ++++ b/drivers/ssb/main.c +@@ -90,25 +90,6 @@ found: + } + #endif /* CONFIG_SSB_PCMCIAHOST */ + +-#ifdef CONFIG_SSB_SDIOHOST +-struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func) +-{ +- struct ssb_bus *bus; +- +- ssb_buses_lock(); +- list_for_each_entry(bus, &buses, list) { +- if (bus->bustype == SSB_BUSTYPE_SDIO && +- bus->host_sdio == func) +- goto found; +- } +- bus = NULL; +-found: +- ssb_buses_unlock(); +- +- return bus; +-} +-#endif /* CONFIG_SSB_SDIOHOST */ +- + int ssb_for_each_bus_call(unsigned long data, + int (*func)(struct ssb_bus *bus, unsigned long data)) + { +@@ -1154,6 +1135,8 @@ static u32 ssb_tmslow_reject_bitmask(str + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ + case SSB_IDLOW_SSBREV_27: /* same here */ + return SSB_TMSLOW_REJECT; /* this is a guess */ ++ case SSB_IDLOW_SSBREV: ++ break; + default: + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); + } diff --git a/target/linux/generic/patches-3.18/021-ssb_sprom.patch b/target/linux/generic/patches-3.18/021-ssb_sprom.patch new file mode 100644 index 0000000..52d8080 --- /dev/null +++ b/target/linux/generic/patches-3.18/021-ssb_sprom.patch @@ -0,0 +1,32 @@ +--- a/include/linux/ssb/ssb.h ++++ b/include/linux/ssb/ssb.h +@@ -29,10 +29,13 @@ struct ssb_sprom { + u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */ + u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */ + u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */ ++ u8 et2mac[6] __aligned(sizeof(u16)); /* MAC address for extra Ethernet */ + u8 et0phyaddr; /* MII address for enet0 */ + u8 et1phyaddr; /* MII address for enet1 */ ++ u8 et2phyaddr; /* MII address for enet2 */ + u8 et0mdcport; /* MDIO for enet0 */ + u8 et1mdcport; /* MDIO for enet1 */ ++ u8 et2mdcport; /* MDIO for enet2 */ + u16 dev_id; /* Device ID overriding e.g. PCI ID */ + u16 board_rev; /* Board revision number from SPROM. */ + u16 board_num; /* Board number from SPROM. */ +@@ -88,11 +91,14 @@ struct ssb_sprom { + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */ + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */ + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */ ++ u32 boardflags; ++ u32 boardflags2; ++ u32 boardflags3; ++ /* TODO: Switch all drivers to new u32 fields and drop below ones */ + u16 boardflags_lo; /* Board flags (bits 0-15) */ + u16 boardflags_hi; /* Board flags (bits 16-31) */ + u16 boardflags2_lo; /* Board flags (bits 32-47) */ + u16 boardflags2_hi; /* Board flags (bits 48-63) */ +- /* TODO store board flags in a single u64 */ + + struct ssb_sprom_core_pwr_info core_pwr_info[4]; + diff --git a/target/linux/generic/patches-3.18/025-bcma_backport.patch b/target/linux/generic/patches-3.18/025-bcma_backport.patch new file mode 100644 index 0000000..ca24e86 --- /dev/null +++ b/target/linux/generic/patches-3.18/025-bcma_backport.patch @@ -0,0 +1,286 @@ +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -24,6 +24,7 @@ struct bcma_bus; + /* main.c */ + bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, + int timeout); ++void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core); + int bcma_bus_register(struct bcma_bus *bus); + void bcma_bus_unregister(struct bcma_bus *bus); + int __init bcma_bus_early_register(struct bcma_bus *bus, +--- a/drivers/bcma/driver_chipcommon.c ++++ b/drivers/bcma/driver_chipcommon.c +@@ -339,7 +339,7 @@ void bcma_chipco_serial_init(struct bcma + return; + } + +- irq = bcma_core_irq(cc->core); ++ irq = bcma_core_irq(cc->core, 0); + + /* Determine the registers of the UARTs */ + cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); +--- a/drivers/bcma/driver_gpio.c ++++ b/drivers/bcma/driver_gpio.c +@@ -152,7 +152,7 @@ static int bcma_gpio_irq_domain_init(str + handle_simple_irq); + } + +- hwirq = bcma_core_irq(cc->core); ++ hwirq = bcma_core_irq(cc->core, 0); + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio", + cc); + if (err) +@@ -183,7 +183,7 @@ static void bcma_gpio_irq_domain_exit(st + return; + + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO); +- free_irq(bcma_core_irq(cc->core), cc); ++ free_irq(bcma_core_irq(cc->core, 0), cc); + for (gpio = 0; gpio < chip->ngpio; gpio++) { + int irq = irq_find_mapping(cc->irq_domain, gpio); + +--- a/drivers/bcma/driver_mips.c ++++ b/drivers/bcma/driver_mips.c +@@ -115,7 +115,7 @@ static u32 bcma_core_mips_irqflag(struct + * If disabled, 5 is returned. + * If not supported, 6 is returned. + */ +-static unsigned int bcma_core_mips_irq(struct bcma_device *dev) ++unsigned int bcma_core_mips_irq(struct bcma_device *dev) + { + struct bcma_device *mdev = dev->bus->drv_mips.core; + u32 irqflag; +@@ -133,13 +133,6 @@ static unsigned int bcma_core_mips_irq(s + return 5; + } + +-unsigned int bcma_core_irq(struct bcma_device *dev) +-{ +- unsigned int mips_irq = bcma_core_mips_irq(dev); +- return mips_irq <= 4 ? mips_irq + 2 : 0; +-} +-EXPORT_SYMBOL(bcma_core_irq); +- + static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) + { + unsigned int oldirq = bcma_core_mips_irq(dev); +@@ -423,7 +416,7 @@ void bcma_core_mips_init(struct bcma_drv + break; + default: + list_for_each_entry(core, &bus->cores, list) { +- core->irq = bcma_core_irq(core); ++ core->irq = bcma_core_irq(core, 0); + } + bcma_err(bus, + "Unknown device (0x%x) found, can not configure IRQs\n", +--- a/drivers/bcma/driver_pci_host.c ++++ b/drivers/bcma/driver_pci_host.c +@@ -593,7 +593,7 @@ int bcma_core_pci_plat_dev_init(struct p + pr_info("PCI: Fixing up device %s\n", pci_name(dev)); + + /* Fix up interrupt lines */ +- dev->irq = bcma_core_irq(pc_host->pdev->core); ++ dev->irq = bcma_core_irq(pc_host->pdev->core, 0); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + + readrq = pcie_get_readrq(dev); +@@ -617,6 +617,6 @@ int bcma_core_pci_pcibios_map_irq(const + + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host, + pci_ops); +- return bcma_core_irq(pc_host->pdev->core); ++ return bcma_core_irq(pc_host->pdev->core, 0); + } + EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq); +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + + MODULE_DESCRIPTION("Broadcom's specific AMBA driver"); + MODULE_LICENSE("GPL"); +@@ -153,6 +154,46 @@ static struct device_node *bcma_of_find_ + return NULL; + } + ++static int bcma_of_irq_parse(struct platform_device *parent, ++ struct bcma_device *core, ++ struct of_phandle_args *out_irq, int num) ++{ ++ __be32 laddr[1]; ++ int rc; ++ ++ if (core->dev.of_node) { ++ rc = of_irq_parse_one(core->dev.of_node, num, out_irq); ++ if (!rc) ++ return rc; ++ } ++ ++ out_irq->np = parent->dev.of_node; ++ out_irq->args_count = 1; ++ out_irq->args[0] = num; ++ ++ laddr[0] = cpu_to_be32(core->addr); ++ return of_irq_parse_raw(laddr, out_irq); ++} ++ ++static unsigned int bcma_of_get_irq(struct platform_device *parent, ++ struct bcma_device *core, int num) ++{ ++ struct of_phandle_args out_irq; ++ int ret; ++ ++ if (!parent || !parent->dev.of_node) ++ return 0; ++ ++ ret = bcma_of_irq_parse(parent, core, &out_irq, num); ++ if (ret) { ++ bcma_debug(core->bus, "bcma_of_get_irq() failed with rc=%d\n", ++ ret); ++ return 0; ++ } ++ ++ return irq_create_of_mapping(&out_irq); ++} ++ + static void bcma_of_fill_device(struct platform_device *parent, + struct bcma_device *core) + { +@@ -161,18 +202,47 @@ static void bcma_of_fill_device(struct p + node = bcma_of_find_child_device(parent, core); + if (node) + core->dev.of_node = node; ++ ++ core->irq = bcma_of_get_irq(parent, core, 0); + } + #else + static void bcma_of_fill_device(struct platform_device *parent, + struct bcma_device *core) + { + } ++static inline unsigned int bcma_of_get_irq(struct platform_device *parent, ++ struct bcma_device *core, int num) ++{ ++ return 0; ++} + #endif /* CONFIG_OF */ + +-static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core) ++unsigned int bcma_core_irq(struct bcma_device *core, int num) + { +- int err; ++ struct bcma_bus *bus = core->bus; ++ unsigned int mips_irq; ++ ++ switch (bus->hosttype) { ++ case BCMA_HOSTTYPE_PCI: ++ return bus->host_pci->irq; ++ case BCMA_HOSTTYPE_SOC: ++ if (bus->drv_mips.core && num == 0) { ++ mips_irq = bcma_core_mips_irq(core); ++ return mips_irq <= 4 ? mips_irq + 2 : 0; ++ } ++ if (bus->host_pdev) ++ return bcma_of_get_irq(bus->host_pdev, core, num); ++ return 0; ++ case BCMA_HOSTTYPE_SDIO: ++ return 0; ++ } + ++ return 0; ++} ++EXPORT_SYMBOL(bcma_core_irq); ++ ++void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core) ++{ + core->dev.release = bcma_release_core_dev; + core->dev.bus = &bcma_bus_type; + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index); +@@ -196,6 +266,11 @@ static void bcma_register_core(struct bc + case BCMA_HOSTTYPE_SDIO: + break; + } ++} ++ ++static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core) ++{ ++ int err; + + err = device_register(&core->dev); + if (err) { +--- a/drivers/bcma/scan.c ++++ b/drivers/bcma/scan.c +@@ -505,6 +505,7 @@ int bcma_bus_scan(struct bcma_bus *bus) + bus->nr_cores++; + other_core = bcma_find_core_reverse(bus, core->id.id); + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1; ++ bcma_prepare_core(bus, core); + + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", + core->core_index, bcma_device_name(&core->id), +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -447,4 +447,6 @@ extern u32 bcma_chipco_pll_read(struct b + #define BCMA_DMA_TRANSLATION_DMA64_CMT 0x80000000 /* Client Mode Translation for 64-bit DMA */ + extern u32 bcma_core_dma_translation(struct bcma_device *core); + ++extern unsigned int bcma_core_irq(struct bcma_device *core, int num); ++ + #endif /* LINUX_BCMA_H_ */ +--- a/include/linux/bcma/bcma_driver_mips.h ++++ b/include/linux/bcma/bcma_driver_mips.h +@@ -43,12 +43,12 @@ struct bcma_drv_mips { + extern void bcma_core_mips_init(struct bcma_drv_mips *mcore); + extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore); + +-extern unsigned int bcma_core_irq(struct bcma_device *core); ++extern unsigned int bcma_core_mips_irq(struct bcma_device *dev); + #else + static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { } + static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { } + +-static inline unsigned int bcma_core_irq(struct bcma_device *core) ++static inline unsigned int bcma_core_mips_irq(struct bcma_device *dev) + { + return 0; + } +--- a/Documentation/devicetree/bindings/bus/bcma.txt ++++ b/Documentation/devicetree/bindings/bus/bcma.txt +@@ -8,6 +8,11 @@ Required properties: + + The cores on the AXI bus are automatically detected by bcma with the + memory ranges they are using and they get registered afterwards. ++Automatic detection of the IRQ number is not working on ++BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide ++them manually through device tree. Use an interrupt-map to specify the ++IRQ used by the devices on the bus. The first address is just an index, ++because we do not have any special register. + + The top-level axi bus may contain children representing attached cores + (devices). This is needed since some hardware details can't be auto +@@ -22,6 +27,22 @@ Example: + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0x000fffff 0xffff>; ++ interrupt-map = ++ /* Ethernet Controller 0 */ ++ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, ++ ++ /* Ethernet Controller 1 */ ++ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; ++ ++ /* PCIe Controller 0 */ ++ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, ++ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon { + reg = <0x00000000 0x1000>; diff --git a/target/linux/generic/patches-3.18/026-bcma-from-3.20.patch b/target/linux/generic/patches-3.18/026-bcma-from-3.20.patch new file mode 100644 index 0000000..17c06b0 --- /dev/null +++ b/target/linux/generic/patches-3.18/026-bcma-from-3.20.patch @@ -0,0 +1,527 @@ +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -25,22 +25,18 @@ struct bcma_bus; + bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, + int timeout); + void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core); ++void bcma_init_bus(struct bcma_bus *bus); + int bcma_bus_register(struct bcma_bus *bus); + void bcma_bus_unregister(struct bcma_bus *bus); +-int __init bcma_bus_early_register(struct bcma_bus *bus, +- struct bcma_device *core_cc, +- struct bcma_device *core_mips); ++int __init bcma_bus_early_register(struct bcma_bus *bus); + #ifdef CONFIG_PM + int bcma_bus_suspend(struct bcma_bus *bus); + int bcma_bus_resume(struct bcma_bus *bus); + #endif + + /* scan.c */ ++void bcma_detect_chip(struct bcma_bus *bus); + int bcma_bus_scan(struct bcma_bus *bus); +-int __init bcma_bus_scan_early(struct bcma_bus *bus, +- struct bcma_device_id *match, +- struct bcma_device *core); +-void bcma_init_bus(struct bcma_bus *bus); + + /* sprom.c */ + int bcma_sprom_get(struct bcma_bus *bus); +@@ -111,6 +107,14 @@ extern int bcma_chipco_watchdog_register + #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE + bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc); + void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc); ++#else ++static inline bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) ++{ ++ return false; ++} ++static inline void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) ++{ ++} + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ + + #ifdef CONFIG_BCMA_DRIVER_GPIO +--- a/drivers/bcma/driver_chipcommon.c ++++ b/drivers/bcma/driver_chipcommon.c +@@ -79,7 +79,9 @@ static int bcma_chipco_watchdog_ticks_pe + + if (cc->capabilities & BCMA_CC_CAP_PMU) { + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) +- /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */ ++ /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP ++ * clock ++ */ + return bcma_chipco_get_alp_clock(cc) / 4000; + else + /* based on 32KHz ILP clock */ +@@ -97,7 +99,8 @@ int bcma_chipco_watchdog_register(struct + wdt.driver_data = cc; + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; +- wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; ++ wdt.max_timer_ms = ++ bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; + + pdev = platform_device_register_data(NULL, "bcm47xx-wdt", + cc->core->bus->num, &wdt, +@@ -175,7 +178,6 @@ void bcma_core_chipcommon_init(struct bc + u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) + { + u32 maxt; +- enum bcma_clkmode clkmode; + + maxt = bcma_chipco_watchdog_get_max_timer(cc); + if (cc->capabilities & BCMA_CC_CAP_PMU) { +@@ -185,8 +187,13 @@ u32 bcma_chipco_watchdog_timer_set(struc + ticks = maxt; + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); + } else { +- clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC; +- bcma_core_set_clockmode(cc->core, clkmode); ++ struct bcma_bus *bus = cc->core->bus; ++ ++ if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 && ++ bus->chipinfo.id != BCMA_CHIP_ID_BCM53018) ++ bcma_core_set_clockmode(cc->core, ++ ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC); ++ + if (ticks > maxt) + ticks = maxt; + /* instant NMI */ +@@ -335,7 +342,8 @@ void bcma_chipco_serial_init(struct bcma + | BCMA_CC_CORECTL_UARTCLKEN); + } + } else { +- bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev); ++ bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ++ ccrev); + return; + } + +--- a/drivers/bcma/driver_pci.c ++++ b/drivers/bcma/driver_pci.c +@@ -145,6 +145,47 @@ static u16 bcma_pcie_mdio_writeread(stru + } + + /************************************************** ++ * Early init. ++ **************************************************/ ++ ++static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc) ++{ ++ struct bcma_device *core = pc->core; ++ u16 val16, core_index; ++ uint regoff; ++ ++ regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET); ++ core_index = (u16)core->core_index; ++ ++ val16 = pcicore_read16(pc, regoff); ++ if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT) ++ != core_index) { ++ val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) | ++ (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK); ++ pcicore_write16(pc, regoff, val16); ++ } ++} ++ ++/* ++ * Apply some early fixes required before accessing SPROM. ++ * See also si_pci_fixcfg. ++ */ ++void bcma_core_pci_early_init(struct bcma_drv_pci *pc) ++{ ++ if (pc->early_setup_done) ++ return; ++ ++ pc->hostmode = bcma_core_pci_is_in_hostmode(pc); ++ if (pc->hostmode) ++ goto out; ++ ++ bcma_core_pci_fixcfg(pc); ++ ++out: ++ pc->early_setup_done = true; ++} ++ ++/************************************************** + * Workarounds. + **************************************************/ + +@@ -175,24 +216,6 @@ static void bcma_pcicore_serdes_workarou + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN); + } + +-static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc) +-{ +- struct bcma_device *core = pc->core; +- u16 val16, core_index; +- uint regoff; +- +- regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET); +- core_index = (u16)core->core_index; +- +- val16 = pcicore_read16(pc, regoff); +- if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT) +- != core_index) { +- val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) | +- (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK); +- pcicore_write16(pc, regoff, val16); +- } +-} +- + /* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */ + /* Needs to happen when coming out of 'standby'/'hibernate' */ + static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc) +@@ -216,7 +239,6 @@ static void bcma_core_pci_config_fixup(s + + static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) + { +- bcma_core_pci_fixcfg(pc); + bcma_pcicore_serdes_workaround(pc); + bcma_core_pci_config_fixup(pc); + } +@@ -226,13 +248,11 @@ void bcma_core_pci_init(struct bcma_drv_ + if (pc->setup_done) + return; + +-#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE +- pc->hostmode = bcma_core_pci_is_in_hostmode(pc); ++ bcma_core_pci_early_init(pc); ++ + if (pc->hostmode) + bcma_core_pci_hostmode_init(pc); +-#endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ +- +- if (!pc->hostmode) ++ else + bcma_core_pci_clientmode_init(pc); + } + +--- a/drivers/bcma/host_pci.c ++++ b/drivers/bcma/host_pci.c +@@ -13,10 +13,12 @@ + + static void bcma_host_pci_switch_core(struct bcma_device *core) + { ++ int win2 = core->bus->host_is_pcie2 ? ++ BCMA_PCIE2_BAR0_WIN2 : BCMA_PCI_BAR0_WIN2; ++ + pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN, + core->addr); +- pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2, +- core->wrap); ++ pci_write_config_dword(core->bus->host_pci, win2, core->wrap); + core->bus->mapped_core = core; + bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id); + } +--- a/drivers/bcma/host_soc.c ++++ b/drivers/bcma/host_soc.c +@@ -193,7 +193,7 @@ int __init bcma_host_soc_init(struct bcm + int err; + + /* Scan bus and initialize it */ +- err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips); ++ err = bcma_bus_early_register(bus); + if (err) + iounmap(bus->mmio); + +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -268,6 +268,18 @@ void bcma_prepare_core(struct bcma_bus * + } + } + ++void bcma_init_bus(struct bcma_bus *bus) ++{ ++ mutex_lock(&bcma_buses_mutex); ++ bus->num = bcma_bus_next_num++; ++ mutex_unlock(&bcma_buses_mutex); ++ ++ INIT_LIST_HEAD(&bus->cores); ++ bus->nr_cores = 0; ++ ++ bcma_detect_chip(bus); ++} ++ + static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core) + { + int err; +@@ -356,12 +368,19 @@ static void bcma_unregister_cores(struct + struct bcma_device *core, *tmp; + + list_for_each_entry_safe(core, tmp, &bus->cores, list) { ++ if (!core->dev_registered) ++ continue; + list_del(&core->list); +- if (core->dev_registered) +- device_unregister(&core->dev); ++ device_unregister(&core->dev); + } + if (bus->hosttype == BCMA_HOSTTYPE_SOC) + platform_device_unregister(bus->drv_cc.watchdog); ++ ++ /* Now noone uses internally-handled cores, we can free them */ ++ list_for_each_entry_safe(core, tmp, &bus->cores, list) { ++ list_del(&core->list); ++ kfree(core); ++ } + } + + int bcma_bus_register(struct bcma_bus *bus) +@@ -369,10 +388,6 @@ int bcma_bus_register(struct bcma_bus *b + int err; + struct bcma_device *core; + +- mutex_lock(&bcma_buses_mutex); +- bus->num = bcma_bus_next_num++; +- mutex_unlock(&bcma_buses_mutex); +- + /* Scan for devices (cores) */ + err = bcma_bus_scan(bus); + if (err) { +@@ -387,6 +402,13 @@ int bcma_bus_register(struct bcma_bus *b + bcma_core_chipcommon_early_init(&bus->drv_cc); + } + ++ /* Early init PCIE core */ ++ core = bcma_find_core(bus, BCMA_CORE_PCIE); ++ if (core) { ++ bus->drv_pci[0].core = core; ++ bcma_core_pci_early_init(&bus->drv_pci[0]); ++ } ++ + /* Cores providing flash access go before SPROM init */ + list_for_each_entry(core, &bus->cores, list) { + if (bcma_is_core_needed_early(core->id.id)) +@@ -459,7 +481,6 @@ int bcma_bus_register(struct bcma_bus *b + + void bcma_bus_unregister(struct bcma_bus *bus) + { +- struct bcma_device *cores[3]; + int err; + + err = bcma_gpio_unregister(&bus->drv_cc); +@@ -470,46 +491,23 @@ void bcma_bus_unregister(struct bcma_bus + + bcma_core_chipcommon_b_free(&bus->drv_cc_b); + +- cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K); +- cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE); +- cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON); +- + bcma_unregister_cores(bus); +- +- kfree(cores[2]); +- kfree(cores[1]); +- kfree(cores[0]); + } + +-int __init bcma_bus_early_register(struct bcma_bus *bus, +- struct bcma_device *core_cc, +- struct bcma_device *core_mips) ++/* ++ * This is a special version of bus registration function designed for SoCs. ++ * It scans bus and performs basic initialization of main cores only. ++ * Please note it requires memory allocation, however it won't try to sleep. ++ */ ++int __init bcma_bus_early_register(struct bcma_bus *bus) + { + int err; + struct bcma_device *core; +- struct bcma_device_id match; +- +- match.manuf = BCMA_MANUF_BCM; +- match.id = bcma_cc_core_id(bus); +- match.class = BCMA_CL_SIM; +- match.rev = BCMA_ANY_REV; + +- /* Scan for chip common core */ +- err = bcma_bus_scan_early(bus, &match, core_cc); +- if (err) { +- bcma_err(bus, "Failed to scan for common core: %d\n", err); +- return -1; +- } +- +- match.manuf = BCMA_MANUF_MIPS; +- match.id = BCMA_CORE_MIPS_74K; +- match.class = BCMA_CL_SIM; +- match.rev = BCMA_ANY_REV; +- +- /* Scan for mips core */ +- err = bcma_bus_scan_early(bus, &match, core_mips); ++ /* Scan for devices (cores) */ ++ err = bcma_bus_scan(bus); + if (err) { +- bcma_err(bus, "Failed to scan for mips core: %d\n", err); ++ bcma_err(bus, "Failed to scan bus: %d\n", err); + return -1; + } + +--- a/drivers/bcma/scan.c ++++ b/drivers/bcma/scan.c +@@ -435,15 +435,12 @@ static int bcma_get_next_core(struct bcm + return 0; + } + +-void bcma_init_bus(struct bcma_bus *bus) ++void bcma_detect_chip(struct bcma_bus *bus) + { + s32 tmp; + struct bcma_chipinfo *chipinfo = &(bus->chipinfo); + char chip_id[8]; + +- INIT_LIST_HEAD(&bus->cores); +- bus->nr_cores = 0; +- + bcma_scan_switch_core(bus, BCMA_ADDR_BASE); + + tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID); +@@ -464,6 +461,10 @@ int bcma_bus_scan(struct bcma_bus *bus) + + int err, core_num = 0; + ++ /* Skip if bus was already scanned (e.g. during early register) */ ++ if (bus->nr_cores) ++ return 0; ++ + erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM); + if (bus->hosttype == BCMA_HOSTTYPE_SOC) { + eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE); +@@ -519,64 +520,6 @@ int bcma_bus_scan(struct bcma_bus *bus) + out: + if (bus->hosttype == BCMA_HOSTTYPE_SOC) + iounmap(eromptr); +- +- return err; +-} +- +-int __init bcma_bus_scan_early(struct bcma_bus *bus, +- struct bcma_device_id *match, +- struct bcma_device *core) +-{ +- u32 erombase; +- u32 __iomem *eromptr, *eromend; +- +- int err = -ENODEV; +- int core_num = 0; +- +- erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM); +- if (bus->hosttype == BCMA_HOSTTYPE_SOC) { +- eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE); +- if (!eromptr) +- return -ENOMEM; +- } else { +- eromptr = bus->mmio; +- } +- +- eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32); +- +- bcma_scan_switch_core(bus, erombase); +- +- while (eromptr < eromend) { +- memset(core, 0, sizeof(*core)); +- INIT_LIST_HEAD(&core->list); +- core->bus = bus; +- +- err = bcma_get_next_core(bus, &eromptr, match, core_num, core); +- if (err == -ENODEV) { +- core_num++; +- continue; +- } else if (err == -ENXIO) +- continue; +- else if (err == -ESPIPE) +- break; +- else if (err < 0) +- goto out; +- +- core->core_index = core_num++; +- bus->nr_cores++; +- bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", +- core->core_index, bcma_device_name(&core->id), +- core->id.manuf, core->id.id, core->id.rev, +- core->id.class); +- +- list_add_tail(&core->list, &bus->cores); +- err = 0; +- break; +- } +- +-out: +- if (bus->hosttype == BCMA_HOSTTYPE_SOC) +- iounmap(eromptr); + + return err; + } +--- a/drivers/bcma/sprom.c ++++ b/drivers/bcma/sprom.c +@@ -579,7 +579,8 @@ int bcma_sprom_get(struct bcma_bus *bus) + u16 offset = BCMA_CC_SPROM; + u16 *sprom; + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4, +- SSB_SPROMSIZE_WORDS_R10, }; ++ SSB_SPROMSIZE_WORDS_R10, ++ SSB_SPROMSIZE_WORDS_R11, }; + int i, err = 0; + + if (!bus->drv_cc.core) +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -318,6 +318,7 @@ struct bcma_bus { + const struct bcma_host_ops *ops; + + enum bcma_hosttype hosttype; ++ bool host_is_pcie2; /* Used for BCMA_HOSTTYPE_PCI only */ + union { + /* Pointer to the PCI bus (only for BCMA_HOSTTYPE_PCI) */ + struct pci_dev *host_pci; +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -223,6 +223,7 @@ struct bcma_drv_pci_host { + + struct bcma_drv_pci { + struct bcma_device *core; ++ u8 early_setup_done:1; + u8 setup_done:1; + u8 hostmode:1; + +@@ -237,6 +238,7 @@ struct bcma_drv_pci { + #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val) + #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val) + ++extern void bcma_core_pci_early_init(struct bcma_drv_pci *pc); + extern void bcma_core_pci_init(struct bcma_drv_pci *pc); + extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, + struct bcma_device *core, bool enable); +--- a/include/linux/bcma/bcma_regs.h ++++ b/include/linux/bcma/bcma_regs.h +@@ -64,6 +64,8 @@ + #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ + #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ + ++#define BCMA_PCIE2_BAR0_WIN2 0x70 ++ + /* SiliconBackplane Address Map. + * All regions may not exist on all chips. + */ +--- a/include/linux/bcma/bcma_soc.h ++++ b/include/linux/bcma/bcma_soc.h +@@ -5,8 +5,6 @@ + + struct bcma_soc { + struct bcma_bus bus; +- struct bcma_device core_cc; +- struct bcma_device core_mips; + }; + + int __init bcma_host_soc_register(struct bcma_soc *soc); +--- a/include/linux/ssb/ssb_regs.h ++++ b/include/linux/ssb/ssb_regs.h +@@ -173,6 +173,7 @@ + #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16)) + #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16)) + #define SSB_SPROMSIZE_WORDS_R10 230 ++#define SSB_SPROMSIZE_WORDS_R11 234 + #define SSB_SPROM_BASE1 0x1000 + #define SSB_SPROM_BASE31 0x0800 + #define SSB_SPROM_REVISION 0x007E diff --git a/target/linux/generic/patches-3.18/027-bcma-from-4.1.patch b/target/linux/generic/patches-3.18/027-bcma-from-4.1.patch new file mode 100644 index 0000000..1d751a0 --- /dev/null +++ b/target/linux/generic/patches-3.18/027-bcma-from-4.1.patch @@ -0,0 +1,680 @@ +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -26,6 +26,7 @@ bool bcma_wait_value(struct bcma_device + int timeout); + void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core); + void bcma_init_bus(struct bcma_bus *bus); ++void bcma_unregister_cores(struct bcma_bus *bus); + int bcma_bus_register(struct bcma_bus *bus); + void bcma_bus_unregister(struct bcma_bus *bus); + int __init bcma_bus_early_register(struct bcma_bus *bus); +@@ -42,6 +43,9 @@ int bcma_bus_scan(struct bcma_bus *bus); + int bcma_sprom_get(struct bcma_bus *bus); + + /* driver_chipcommon.c */ ++void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); ++void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); ++void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); + #ifdef CONFIG_BCMA_DRIVER_MIPS + void bcma_chipco_serial_init(struct bcma_drv_cc *cc); + extern struct platform_device bcma_pflash_dev; +@@ -52,6 +56,8 @@ int bcma_core_chipcommon_b_init(struct b + void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb); + + /* driver_chipcommon_pmu.c */ ++void bcma_pmu_early_init(struct bcma_drv_cc *cc); ++void bcma_pmu_init(struct bcma_drv_cc *cc); + u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc); + u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc); + +@@ -100,7 +106,35 @@ static inline void __exit bcma_host_soc_ + #endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */ + + /* driver_pci.c */ ++#ifdef CONFIG_BCMA_DRIVER_PCI + u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); ++void bcma_core_pci_early_init(struct bcma_drv_pci *pc); ++void bcma_core_pci_init(struct bcma_drv_pci *pc); ++void bcma_core_pci_up(struct bcma_drv_pci *pc); ++void bcma_core_pci_down(struct bcma_drv_pci *pc); ++#else ++static inline void bcma_core_pci_early_init(struct bcma_drv_pci *pc) ++{ ++ WARN_ON(pc->core->bus->hosttype == BCMA_HOSTTYPE_PCI); ++} ++static inline void bcma_core_pci_init(struct bcma_drv_pci *pc) ++{ ++ /* Initialization is required for PCI hosted bus */ ++ WARN_ON(pc->core->bus->hosttype == BCMA_HOSTTYPE_PCI); ++} ++#endif ++ ++/* driver_pcie2.c */ ++#ifdef CONFIG_BCMA_DRIVER_PCI ++void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2); ++void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2); ++#else ++static inline void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2) ++{ ++ /* Initialization is required for PCI hosted bus */ ++ WARN_ON(pcie2->core->bus->hosttype == BCMA_HOSTTYPE_PCI); ++} ++#endif + + extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc); + +@@ -117,6 +151,39 @@ static inline void bcma_core_pci_hostmod + } + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ + ++/************************************************** ++ * driver_mips.c ++ **************************************************/ ++ ++#ifdef CONFIG_BCMA_DRIVER_MIPS ++unsigned int bcma_core_mips_irq(struct bcma_device *dev); ++void bcma_core_mips_early_init(struct bcma_drv_mips *mcore); ++void bcma_core_mips_init(struct bcma_drv_mips *mcore); ++#else ++static inline unsigned int bcma_core_mips_irq(struct bcma_device *dev) ++{ ++ return 0; ++} ++static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) ++{ ++} ++static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) ++{ ++} ++#endif ++ ++/************************************************** ++ * driver_gmac_cmn.c ++ **************************************************/ ++ ++#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN ++void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc); ++#else ++static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) ++{ ++} ++#endif ++ + #ifdef CONFIG_BCMA_DRIVER_GPIO + /* driver_gpio.c */ + int bcma_gpio_init(struct bcma_drv_cc *cc); +--- a/drivers/bcma/driver_gpio.c ++++ b/drivers/bcma/driver_gpio.c +@@ -17,6 +17,8 @@ + + #include "bcma_private.h" + ++#define BCMA_GPIO_MAX_PINS 32 ++ + static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip) + { + return container_of(chip, struct bcma_drv_cc, gpio); +@@ -76,7 +78,7 @@ static void bcma_gpio_free(struct gpio_c + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); + } + +-#if IS_BUILTIN(CONFIG_BCM47XX) ++#if IS_BUILTIN(CONFIG_BCM47XX) || IS_BUILTIN(CONFIG_ARCH_BCM_5301X) + static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) + { + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); +@@ -204,6 +206,7 @@ static void bcma_gpio_irq_domain_exit(st + + int bcma_gpio_init(struct bcma_drv_cc *cc) + { ++ struct bcma_bus *bus = cc->core->bus; + struct gpio_chip *chip = &cc->gpio; + int err; + +@@ -215,14 +218,14 @@ int bcma_gpio_init(struct bcma_drv_cc *c + chip->set = bcma_gpio_set_value; + chip->direction_input = bcma_gpio_direction_input; + chip->direction_output = bcma_gpio_direction_output; +-#if IS_BUILTIN(CONFIG_BCM47XX) ++#if IS_BUILTIN(CONFIG_BCM47XX) || IS_BUILTIN(CONFIG_ARCH_BCM_5301X) + chip->to_irq = bcma_gpio_to_irq; + #endif + #if IS_BUILTIN(CONFIG_OF) + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) + chip->of_node = cc->core->dev.of_node; + #endif +- switch (cc->core->bus->chipinfo.id) { ++ switch (bus->chipinfo.id) { + case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: + chip->ngpio = 32; +@@ -231,13 +234,17 @@ int bcma_gpio_init(struct bcma_drv_cc *c + chip->ngpio = 16; + } + +- /* There is just one SoC in one device and its GPIO addresses should be +- * deterministic to address them more easily. The other buses could get +- * a random base number. */ +- if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) +- chip->base = 0; +- else +- chip->base = -1; ++ /* ++ * On MIPS we register GPIO devices (LEDs, buttons) using absolute GPIO ++ * pin numbers. We don't have Device Tree there and we can't really use ++ * relative (per chip) numbers. ++ * So let's use predictable base for BCM47XX and "random" for all other. ++ */ ++#if IS_BUILTIN(CONFIG_BCM47XX) ++ chip->base = bus->num * BCMA_GPIO_MAX_PINS; ++#else ++ chip->base = -1; ++#endif + + err = bcma_gpio_irq_domain_init(cc); + if (err) +--- a/drivers/bcma/driver_pci.c ++++ b/drivers/bcma/driver_pci.c +@@ -282,39 +282,6 @@ void bcma_core_pci_power_save(struct bcm + } + EXPORT_SYMBOL_GPL(bcma_core_pci_power_save); + +-int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, +- bool enable) +-{ +- struct pci_dev *pdev; +- u32 coremask, tmp; +- int err = 0; +- +- if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) { +- /* This bcma device is not on a PCI host-bus. So the IRQs are +- * not routed through the PCI core. +- * So we must not enable routing through the PCI core. */ +- goto out; +- } +- +- pdev = pc->core->bus->host_pci; +- +- err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); +- if (err) +- goto out; +- +- coremask = BIT(core->core_index) << 8; +- if (enable) +- tmp |= coremask; +- else +- tmp &= ~coremask; +- +- err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp); +- +-out: +- return err; +-} +-EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); +- + static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend) + { + u32 w; +@@ -328,28 +295,12 @@ static void bcma_core_pci_extend_L1timer + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); + } + +-void bcma_core_pci_up(struct bcma_bus *bus) ++void bcma_core_pci_up(struct bcma_drv_pci *pc) + { +- struct bcma_drv_pci *pc; +- +- if (bus->hosttype != BCMA_HOSTTYPE_PCI) +- return; +- +- pc = &bus->drv_pci[0]; +- + bcma_core_pci_extend_L1timer(pc, true); + } +-EXPORT_SYMBOL_GPL(bcma_core_pci_up); + +-void bcma_core_pci_down(struct bcma_bus *bus) ++void bcma_core_pci_down(struct bcma_drv_pci *pc) + { +- struct bcma_drv_pci *pc; +- +- if (bus->hosttype != BCMA_HOSTTYPE_PCI) +- return; +- +- pc = &bus->drv_pci[0]; +- + bcma_core_pci_extend_L1timer(pc, false); + } +-EXPORT_SYMBOL_GPL(bcma_core_pci_down); +--- a/drivers/bcma/driver_pci_host.c ++++ b/drivers/bcma/driver_pci_host.c +@@ -11,6 +11,7 @@ + + #include "bcma_private.h" + #include ++#include + #include + #include + #include +--- a/drivers/bcma/driver_pcie2.c ++++ b/drivers/bcma/driver_pcie2.c +@@ -10,6 +10,7 @@ + + #include "bcma_private.h" + #include ++#include + + /************************************************** + * R/W ops. +@@ -156,14 +157,23 @@ static void pciedev_reg_pm_clk_period(st + + void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2) + { +- struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo; ++ struct bcma_bus *bus = pcie2->core->bus; ++ struct bcma_chipinfo *ci = &bus->chipinfo; + u32 tmp; + + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54)); + if ((tmp & 0xe) >> 1 == 2) + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17); + +- /* TODO: Do we need pcie_reqsize? */ ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4360: ++ case BCMA_CHIP_ID_BCM4352: ++ pcie2->reqsize = 1024; ++ break; ++ default: ++ pcie2->reqsize = 128; ++ break; ++ } + + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3) + bcma_core_pcie2_war_delay_perst_enab(pcie2, true); +@@ -173,3 +183,18 @@ void bcma_core_pcie2_init(struct bcma_dr + pciedev_crwlpciegen2_180(pcie2); + pciedev_crwlpciegen2_182(pcie2); + } ++ ++/************************************************** ++ * Runtime ops. ++ **************************************************/ ++ ++void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2) ++{ ++ struct bcma_bus *bus = pcie2->core->bus; ++ struct pci_dev *dev = bus->host_pci; ++ int err; ++ ++ err = pcie_set_readrq(dev, pcie2->reqsize); ++ if (err) ++ bcma_err(bus, "Error setting PCI_EXP_DEVCTL_READRQ: %d\n", err); ++} +--- a/drivers/bcma/host_pci.c ++++ b/drivers/bcma/host_pci.c +@@ -213,16 +213,26 @@ static int bcma_host_pci_probe(struct pc + /* Initialize struct, detect chip */ + bcma_init_bus(bus); + ++ /* Scan bus to find out generation of PCIe core */ ++ err = bcma_bus_scan(bus); ++ if (err) ++ goto err_pci_unmap_mmio; ++ ++ if (bcma_find_core(bus, BCMA_CORE_PCIE2)) ++ bus->host_is_pcie2 = true; ++ + /* Register */ + err = bcma_bus_register(bus); + if (err) +- goto err_pci_unmap_mmio; ++ goto err_unregister_cores; + + pci_set_drvdata(dev, bus); + + out: + return err; + ++err_unregister_cores: ++ bcma_unregister_cores(bus); + err_pci_unmap_mmio: + pci_iounmap(dev, bus->mmio); + err_pci_release_regions: +@@ -283,9 +293,12 @@ static const struct pci_device_id bcma_p + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43b1) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */ + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */ +@@ -310,3 +323,65 @@ void __exit bcma_host_pci_exit(void) + { + pci_unregister_driver(&bcma_pci_bridge_driver); + } ++ ++/************************************************** ++ * Runtime ops for drivers. ++ **************************************************/ ++ ++/* See also pcicore_up */ ++void bcma_host_pci_up(struct bcma_bus *bus) ++{ ++ if (bus->hosttype != BCMA_HOSTTYPE_PCI) ++ return; ++ ++ if (bus->host_is_pcie2) ++ bcma_core_pcie2_up(&bus->drv_pcie2); ++ else ++ bcma_core_pci_up(&bus->drv_pci[0]); ++} ++EXPORT_SYMBOL_GPL(bcma_host_pci_up); ++ ++/* See also pcicore_down */ ++void bcma_host_pci_down(struct bcma_bus *bus) ++{ ++ if (bus->hosttype != BCMA_HOSTTYPE_PCI) ++ return; ++ ++ if (!bus->host_is_pcie2) ++ bcma_core_pci_down(&bus->drv_pci[0]); ++} ++EXPORT_SYMBOL_GPL(bcma_host_pci_down); ++ ++/* See also si_pci_setup */ ++int bcma_host_pci_irq_ctl(struct bcma_bus *bus, struct bcma_device *core, ++ bool enable) ++{ ++ struct pci_dev *pdev; ++ u32 coremask, tmp; ++ int err = 0; ++ ++ if (bus->hosttype != BCMA_HOSTTYPE_PCI) { ++ /* This bcma device is not on a PCI host-bus. So the IRQs are ++ * not routed through the PCI core. ++ * So we must not enable routing through the PCI core. */ ++ goto out; ++ } ++ ++ pdev = bus->host_pci; ++ ++ err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); ++ if (err) ++ goto out; ++ ++ coremask = BIT(core->core_index) << 8; ++ if (enable) ++ tmp |= coremask; ++ else ++ tmp &= ~coremask; ++ ++ err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp); ++ ++out: ++ return err; ++} ++EXPORT_SYMBOL_GPL(bcma_host_pci_irq_ctl); +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -363,7 +363,7 @@ static int bcma_register_devices(struct + return 0; + } + +-static void bcma_unregister_cores(struct bcma_bus *bus) ++void bcma_unregister_cores(struct bcma_bus *bus) + { + struct bcma_device *core, *tmp; + +--- a/drivers/net/wireless/b43/main.c ++++ b/drivers/net/wireless/b43/main.c +@@ -4770,7 +4770,7 @@ static void b43_wireless_core_exit(struc + switch (dev->dev->bus_type) { + #ifdef CONFIG_B43_BCMA + case B43_BUS_BCMA: +- bcma_core_pci_down(dev->dev->bdev->bus); ++ bcma_host_pci_down(dev->dev->bdev->bus); + break; + #endif + #ifdef CONFIG_B43_SSB +@@ -4817,9 +4817,9 @@ static int b43_wireless_core_init(struct + switch (dev->dev->bus_type) { + #ifdef CONFIG_B43_BCMA + case B43_BUS_BCMA: +- bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0], ++ bcma_host_pci_irq_ctl(dev->dev->bdev->bus, + dev->dev->bdev, true); +- bcma_core_pci_up(dev->dev->bdev->bus); ++ bcma_host_pci_up(dev->dev->bdev->bus); + break; + #endif + #ifdef CONFIG_B43_SSB +--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c ++++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c +@@ -4669,7 +4669,7 @@ static int brcms_b_attach(struct brcms_c + brcms_c_coredisable(wlc_hw); + + /* Match driver "down" state */ +- bcma_core_pci_down(wlc_hw->d11core->bus); ++ bcma_host_pci_down(wlc_hw->d11core->bus); + + /* turn off pll and xtal to match driver "down" state */ + brcms_b_xtal(wlc_hw, OFF); +@@ -4960,7 +4960,7 @@ static int brcms_b_up_prep(struct brcms_ + * Configure pci/pcmcia here instead of in brcms_c_attach() + * to allow mfg hotswap: down, hotswap (chip power cycle), up. + */ +- bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core, ++ bcma_host_pci_irq_ctl(wlc_hw->d11core->bus, wlc_hw->d11core, + true); + + /* +@@ -4970,12 +4970,12 @@ static int brcms_b_up_prep(struct brcms_ + */ + if (brcms_b_radio_read_hwdisabled(wlc_hw)) { + /* put SB PCI in down state again */ +- bcma_core_pci_down(wlc_hw->d11core->bus); ++ bcma_host_pci_down(wlc_hw->d11core->bus); + brcms_b_xtal(wlc_hw, OFF); + return -ENOMEDIUM; + } + +- bcma_core_pci_up(wlc_hw->d11core->bus); ++ bcma_host_pci_up(wlc_hw->d11core->bus); + + /* reset the d11 core */ + brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); +@@ -5172,7 +5172,7 @@ static int brcms_b_down_finish(struct br + + /* turn off primary xtal and pll */ + if (!wlc_hw->noreset) { +- bcma_core_pci_down(wlc_hw->d11core->bus); ++ bcma_host_pci_down(wlc_hw->d11core->bus); + brcms_b_xtal(wlc_hw, OFF); + } + } +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -434,6 +434,27 @@ static inline struct bcma_device *bcma_f + return bcma_find_core_unit(bus, coreid, 0); + } + ++#ifdef CONFIG_BCMA_HOST_PCI ++extern void bcma_host_pci_up(struct bcma_bus *bus); ++extern void bcma_host_pci_down(struct bcma_bus *bus); ++extern int bcma_host_pci_irq_ctl(struct bcma_bus *bus, ++ struct bcma_device *core, bool enable); ++#else ++static inline void bcma_host_pci_up(struct bcma_bus *bus) ++{ ++} ++static inline void bcma_host_pci_down(struct bcma_bus *bus) ++{ ++} ++static inline int bcma_host_pci_irq_ctl(struct bcma_bus *bus, ++ struct bcma_device *core, bool enable) ++{ ++ if (bus->hosttype == BCMA_HOSTTYPE_PCI) ++ return -ENOTSUPP; ++ return 0; ++} ++#endif ++ + extern bool bcma_core_is_enabled(struct bcma_device *core); + extern void bcma_core_disable(struct bcma_device *core, u32 flags); + extern int bcma_core_enable(struct bcma_device *core, u32 flags); +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -238,13 +238,13 @@ struct bcma_drv_pci { + #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val) + #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val) + +-extern void bcma_core_pci_early_init(struct bcma_drv_pci *pc); +-extern void bcma_core_pci_init(struct bcma_drv_pci *pc); +-extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, +- struct bcma_device *core, bool enable); +-extern void bcma_core_pci_up(struct bcma_bus *bus); +-extern void bcma_core_pci_down(struct bcma_bus *bus); ++#ifdef CONFIG_BCMA_DRIVER_PCI + extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up); ++#else ++static inline void bcma_core_pci_power_save(struct bcma_bus *bus, bool up) ++{ ++} ++#endif + + extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); + extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); +--- a/include/linux/bcma/bcma_driver_pcie2.h ++++ b/include/linux/bcma/bcma_driver_pcie2.h +@@ -143,6 +143,8 @@ + + struct bcma_drv_pcie2 { + struct bcma_device *core; ++ ++ u16 reqsize; + }; + + #define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset) +@@ -153,6 +155,4 @@ struct bcma_drv_pcie2 { + #define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set) + #define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask) + +-void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2); +- + #endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */ +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE + config BCMA_HOST_PCI + bool "Support for BCMA on PCI-host bus" + depends on BCMA_HOST_PCI_POSSIBLE ++ select BCMA_DRIVER_PCI + default y + + config BCMA_DRIVER_PCI_HOSTMODE +@@ -44,6 +45,22 @@ config BCMA_HOST_SOC + + If unsure, say N + ++config BCMA_DRIVER_PCI ++ bool "BCMA Broadcom PCI core driver" ++ depends on BCMA && PCI ++ default y ++ help ++ BCMA bus may have many versions of PCIe core. This driver ++ supports: ++ 1) PCIe core working in clientmode ++ 2) PCIe Gen 2 clientmode core ++ ++ In general PCIe (Gen 2) clientmode core is required on PCIe ++ hosted buses. It's responsible for initialization and basic ++ hardware management. ++ This driver is also prerequisite for a hostmode PCIe core ++ support. ++ + config BCMA_DRIVER_MIPS + bool "BCMA Broadcom MIPS core driver" + depends on BCMA && MIPS +--- a/drivers/bcma/Makefile ++++ b/drivers/bcma/Makefile +@@ -3,8 +3,8 @@ bcma-y += driver_chipcommon.o driver + bcma-y += driver_chipcommon_b.o + bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o + bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o +-bcma-y += driver_pci.o +-bcma-y += driver_pcie2.o ++bcma-$(CONFIG_BCMA_DRIVER_PCI) += driver_pci.o ++bcma-$(CONFIG_BCMA_DRIVER_PCI) += driver_pcie2.o + bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o + bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o + bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -663,14 +663,6 @@ struct bcma_drv_cc_b { + #define bcma_cc_maskset32(cc, offset, mask, set) \ + bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) + +-extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); +-extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); +- +-extern void bcma_chipco_suspend(struct bcma_drv_cc *cc); +-extern void bcma_chipco_resume(struct bcma_drv_cc *cc); +- +-void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); +- + extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); + + extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); +@@ -690,9 +682,6 @@ u32 bcma_chipco_gpio_pullup(struct bcma_ + u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); + + /* PMU support */ +-extern void bcma_pmu_init(struct bcma_drv_cc *cc); +-extern void bcma_pmu_early_init(struct bcma_drv_cc *cc); +- + extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, + u32 value); + extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, +--- a/include/linux/bcma/bcma_driver_gmac_cmn.h ++++ b/include/linux/bcma/bcma_driver_gmac_cmn.h +@@ -91,10 +91,4 @@ struct bcma_drv_gmac_cmn { + #define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val) + #define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val) + +-#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN +-extern void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc); +-#else +-static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { } +-#endif +- + #endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */ +--- a/include/linux/bcma/bcma_driver_mips.h ++++ b/include/linux/bcma/bcma_driver_mips.h +@@ -39,21 +39,6 @@ struct bcma_drv_mips { + u8 early_setup_done:1; + }; + +-#ifdef CONFIG_BCMA_DRIVER_MIPS +-extern void bcma_core_mips_init(struct bcma_drv_mips *mcore); +-extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore); +- +-extern unsigned int bcma_core_mips_irq(struct bcma_device *dev); +-#else +-static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { } +-static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { } +- +-static inline unsigned int bcma_core_mips_irq(struct bcma_device *dev) +-{ +- return 0; +-} +-#endif +- + extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore); + + #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */ diff --git a/target/linux/generic/patches-3.18/028-bcma-from-4.2.patch b/target/linux/generic/patches-3.18/028-bcma-from-4.2.patch new file mode 100644 index 0000000..ba3df18 --- /dev/null +++ b/target/linux/generic/patches-3.18/028-bcma-from-4.2.patch @@ -0,0 +1,86 @@ +--- a/drivers/bcma/driver_gpio.c ++++ b/drivers/bcma/driver_gpio.c +@@ -226,6 +226,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c + chip->of_node = cc->core->dev.of_node; + #endif + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4707: + case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: + chip->ngpio = 32; +@@ -235,16 +236,17 @@ int bcma_gpio_init(struct bcma_drv_cc *c + } + + /* +- * On MIPS we register GPIO devices (LEDs, buttons) using absolute GPIO +- * pin numbers. We don't have Device Tree there and we can't really use +- * relative (per chip) numbers. +- * So let's use predictable base for BCM47XX and "random" for all other. ++ * Register SoC GPIO devices with absolute GPIO pin base. ++ * On MIPS, we don't have Device Tree and we can't use relative (per chip) ++ * GPIO numbers. ++ * On some ARM devices, user space may want to access some system GPIO ++ * pins directly, which is easier to do with a predictable GPIO base. + */ +-#if IS_BUILTIN(CONFIG_BCM47XX) +- chip->base = bus->num * BCMA_GPIO_MAX_PINS; +-#else +- chip->base = -1; +-#endif ++ if (IS_BUILTIN(CONFIG_BCM47XX) || ++ cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) ++ chip->base = bus->num * BCMA_GPIO_MAX_PINS; ++ else ++ chip->base = -1; + + err = bcma_gpio_irq_domain_init(cc); + if (err) +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -29,12 +29,6 @@ config BCMA_HOST_PCI + select BCMA_DRIVER_PCI + default y + +-config BCMA_DRIVER_PCI_HOSTMODE +- bool "Driver for PCI core working in hostmode" +- depends on BCMA && MIPS && BCMA_HOST_PCI +- help +- PCI core hostmode operation (external PCI bus). +- + config BCMA_HOST_SOC + bool "Support for BCMA in a SoC" + depends on BCMA +@@ -61,6 +55,12 @@ config BCMA_DRIVER_PCI + This driver is also prerequisite for a hostmode PCIe core + support. + ++config BCMA_DRIVER_PCI_HOSTMODE ++ bool "Driver for PCI core working in hostmode" ++ depends on BCMA && MIPS && BCMA_DRIVER_PCI ++ help ++ PCI core hostmode operation (external PCI bus). ++ + config BCMA_DRIVER_MIPS + bool "BCMA Broadcom MIPS core driver" + depends on BCMA && MIPS +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -246,7 +246,18 @@ static inline void bcma_core_pci_power_s + } + #endif + ++#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE + extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); + extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); ++#else ++static inline int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) ++{ ++ return -ENOTSUPP; ++} ++static inline int bcma_core_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ return -ENOTSUPP; ++} ++#endif + + #endif /* LINUX_BCMA_DRIVER_PCI_H_ */ diff --git a/target/linux/generic/patches-3.18/029-bcma-from-4.4.patch b/target/linux/generic/patches-3.18/029-bcma-from-4.4.patch new file mode 100644 index 0000000..5704081 --- /dev/null +++ b/target/linux/generic/patches-3.18/029-bcma-from-4.4.patch @@ -0,0 +1,26 @@ +commit 55acca90da52b85299c033354e51ddaa7b73e019 +Author: Hante Meuleman +Date: Fri Sep 18 22:08:17 2015 +0200 + + brcmfmac: Add support for the BCM4365 and BCM4366 PCIE devices. + + This patch adds support for the BCM4365 and BCM4366 11ac Wave2 + PCIE devices. + + Reviewed-by: Arend Van Spriel + Reviewed-by: Pieter-Paul Giesberts + Signed-off-by: Hante Meuleman + Signed-off-by: Arend van Spriel + Signed-off-by: Kalle Valo + +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -151,6 +151,8 @@ struct bcma_host_ops { + #define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */ + #define BCMA_CORE_USB30_DEV 0x83D + #define BCMA_CORE_ARM_CR4 0x83E ++#define BCMA_CORE_ARM_CA7 0x847 ++#define BCMA_CORE_SYS_MEM 0x849 + #define BCMA_CORE_DEFAULT 0xFFF + + #define BCMA_MAX_NR_CORES 16 diff --git a/target/linux/generic/patches-3.18/030-nl80211-Allow-set-network-namespace-by-fd.patch b/target/linux/generic/patches-3.18/030-nl80211-Allow-set-network-namespace-by-fd.patch new file mode 100644 index 0000000..52a2391 --- /dev/null +++ b/target/linux/generic/patches-3.18/030-nl80211-Allow-set-network-namespace-by-fd.patch @@ -0,0 +1,21 @@ +From: Vadim Kochan +Date: Mon, 12 Jan 2015 16:34:05 +0200 +Subject: [PATCH] nl80211: Allow set network namespace by fd + +Added new NL80211_ATTR_NETNS_FD which allows to +set namespace via nl80211 by fd. + +Signed-off-by: Vadim Kochan +Signed-off-by: Johannes Berg +--- + +--- a/net/core/net_namespace.c ++++ b/net/core/net_namespace.c +@@ -361,6 +361,7 @@ struct net *get_net_ns_by_fd(int fd) + return ERR_PTR(-EINVAL); + } + #endif ++EXPORT_SYMBOL_GPL(get_net_ns_by_fd); + + struct net *get_net_ns_by_pid(pid_t pid) + { diff --git a/target/linux/generic/patches-3.18/040-mtd-bcm47xxpart-backports-from-3.19.patch b/target/linux/generic/patches-3.18/040-mtd-bcm47xxpart-backports-from-3.19.patch new file mode 100644 index 0000000..b2d53f9 --- /dev/null +++ b/target/linux/generic/patches-3.18/040-mtd-bcm47xxpart-backports-from-3.19.patch @@ -0,0 +1,50 @@ +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -15,8 +15,12 @@ + #include + #include + +-/* 10 parts were found on sflash on Netgear WNDR4500 */ +-#define BCM47XXPART_MAX_PARTS 12 ++/* ++ * NAND flash on Netgear R6250 was verified to contain 15 partitions. ++ * This will result in allocating too big array for some old devices, but the ++ * memory will be freed soon anyway (see mtd_device_parse_register). ++ */ ++#define BCM47XXPART_MAX_PARTS 20 + + /* + * Amount of bytes we read when analyzing each block of flash memory. +@@ -168,18 +172,26 @@ static int bcm47xxpart_parse(struct mtd_ + i++; + } + +- bcm47xxpart_add_part(&parts[curr_part++], "linux", +- offset + trx->offset[i], 0); +- i++; ++ if (trx->offset[i]) { ++ bcm47xxpart_add_part(&parts[curr_part++], ++ "linux", ++ offset + trx->offset[i], ++ 0); ++ i++; ++ } + + /* + * Pure rootfs size is known and can be calculated as: + * trx->length - trx->offset[i]. We don't fill it as + * we want to have jffs2 (overlay) in the same mtd. + */ +- bcm47xxpart_add_part(&parts[curr_part++], "rootfs", +- offset + trx->offset[i], 0); +- i++; ++ if (trx->offset[i]) { ++ bcm47xxpart_add_part(&parts[curr_part++], ++ "rootfs", ++ offset + trx->offset[i], ++ 0); ++ i++; ++ } + + last_trx_part = curr_part - 1; + diff --git a/target/linux/generic/patches-3.18/041-mtd-bcm47xxpart-backports-from-3.20.patch b/target/linux/generic/patches-3.18/041-mtd-bcm47xxpart-backports-from-3.20.patch new file mode 100644 index 0000000..59180c2 --- /dev/null +++ b/target/linux/generic/patches-3.18/041-mtd-bcm47xxpart-backports-from-3.20.patch @@ -0,0 +1,95 @@ +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -15,6 +15,8 @@ + #include + #include + ++#include ++ + /* + * NAND flash on Netgear R6250 was verified to contain 15 partitions. + * This will result in allocating too big array for some old devices, but the +@@ -39,7 +41,8 @@ + #define ML_MAGIC1 0x39685a42 + #define ML_MAGIC2 0x26594131 + #define TRX_MAGIC 0x30524448 +-#define SQSH_MAGIC 0x71736873 /* shsq */ ++#define SHSQ_MAGIC 0x71736873 /* shsq (weird ZTE H218N endianness) */ ++#define UBI_EC_MAGIC 0x23494255 /* UBI# */ + + struct trx_header { + uint32_t magic; +@@ -50,7 +53,7 @@ struct trx_header { + uint32_t offset[3]; + } __packed; + +-static void bcm47xxpart_add_part(struct mtd_partition *part, char *name, ++static void bcm47xxpart_add_part(struct mtd_partition *part, const char *name, + u64 offset, uint32_t mask_flags) + { + part->name = name; +@@ -58,6 +61,26 @@ static void bcm47xxpart_add_part(struct + part->mask_flags = mask_flags; + } + ++static const char *bcm47xxpart_trx_data_part_name(struct mtd_info *master, ++ size_t offset) ++{ ++ uint32_t buf; ++ size_t bytes_read; ++ ++ if (mtd_read(master, offset, sizeof(buf), &bytes_read, ++ (uint8_t *)&buf) < 0) { ++ pr_err("mtd_read error while parsing (offset: 0x%X)!\n", ++ offset); ++ goto out_default; ++ } ++ ++ if (buf == UBI_EC_MAGIC) ++ return "ubi"; ++ ++out_default: ++ return "rootfs"; ++} ++ + static int bcm47xxpart_parse(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) +@@ -73,8 +96,12 @@ static int bcm47xxpart_parse(struct mtd_ + int last_trx_part = -1; + int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, }; + +- if (blocksize <= 0x10000) +- blocksize = 0x10000; ++ /* ++ * Some really old flashes (like AT45DB*) had smaller erasesize-s, but ++ * partitions were aligned to at least 0x1000 anyway. ++ */ ++ if (blocksize < 0x1000) ++ blocksize = 0x1000; + + /* Alloc */ + parts = kzalloc(sizeof(struct mtd_partition) * BCM47XXPART_MAX_PARTS, +@@ -186,8 +213,11 @@ static int bcm47xxpart_parse(struct mtd_ + * we want to have jffs2 (overlay) in the same mtd. + */ + if (trx->offset[i]) { ++ const char *name; ++ ++ name = bcm47xxpart_trx_data_part_name(master, offset + trx->offset[i]); + bcm47xxpart_add_part(&parts[curr_part++], +- "rootfs", ++ name, + offset + trx->offset[i], + 0); + i++; +@@ -205,7 +235,8 @@ static int bcm47xxpart_parse(struct mtd_ + } + + /* Squashfs on devices not using TRX */ +- if (buf[0x000 / 4] == SQSH_MAGIC) { ++ if (le32_to_cpu(buf[0x000 / 4]) == SQUASHFS_MAGIC || ++ buf[0x000 / 4] == SHSQ_MAGIC) { + bcm47xxpart_add_part(&parts[curr_part++], "rootfs", + offset, 0); + continue; diff --git a/target/linux/generic/patches-3.18/050-backport_netfilter_rtcache.patch b/target/linux/generic/patches-3.18/050-backport_netfilter_rtcache.patch new file mode 100644 index 0000000..9f23db6 --- /dev/null +++ b/target/linux/generic/patches-3.18/050-backport_netfilter_rtcache.patch @@ -0,0 +1,509 @@ +Subject: netfilter: conntrack: cache route for forwarded connections + +... to avoid per-packet FIB lookup if possible. + +The cached dst is re-used provided the input interface +is the same as that of the previous packet in the same direction. + +If not, the cached dst is invalidated. + +For ipv6 we also need to store sernum, else dst_check doesn't work, +pointed out by Eric Dumazet. + +This should speed up forwarding when conntrack is already in use +anyway, especially when using reverse path filtering -- active RPF +enforces two FIB lookups for each packet. + +Before the routing cache removal this didn't matter since RPF was performed +only when route cache didn't yield a result; but without route cache it +comes at higher price. + +Julian Anastasov suggested to add NETDEV_UNREGISTER handler to +avoid holding on to dsts of 'frozen' conntracks. + +Signed-off-by: Florian Westphal + +--- a/include/net/netfilter/nf_conntrack_extend.h ++++ b/include/net/netfilter/nf_conntrack_extend.h +@@ -30,6 +30,9 @@ enum nf_ct_ext_id { + #if IS_ENABLED(CONFIG_NETFILTER_SYNPROXY) + NF_CT_EXT_SYNPROXY, + #endif ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_RTCACHE) ++ NF_CT_EXT_RTCACHE, ++#endif + NF_CT_EXT_NUM, + }; + +@@ -43,6 +46,7 @@ enum nf_ct_ext_id { + #define NF_CT_EXT_TIMEOUT_TYPE struct nf_conn_timeout + #define NF_CT_EXT_LABELS_TYPE struct nf_conn_labels + #define NF_CT_EXT_SYNPROXY_TYPE struct nf_conn_synproxy ++#define NF_CT_EXT_RTCACHE_TYPE struct nf_conn_rtcache + + /* Extensions: optional stuff which isn't permanently in struct. */ + struct nf_ct_ext { +--- /dev/null ++++ b/include/net/netfilter/nf_conntrack_rtcache.h +@@ -0,0 +1,34 @@ ++#include ++#include ++#include ++ ++struct dst_entry; ++ ++struct nf_conn_dst_cache { ++ struct dst_entry *dst; ++ int iif; ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ u32 cookie; ++#endif ++ ++}; ++ ++struct nf_conn_rtcache { ++ struct nf_conn_dst_cache cached_dst[IP_CT_DIR_MAX]; ++}; ++ ++static inline ++struct nf_conn_rtcache *nf_ct_rtcache_find(const struct nf_conn *ct) ++{ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_RTCACHE) ++ return nf_ct_ext_find(ct, NF_CT_EXT_RTCACHE); ++#else ++ return NULL; ++#endif ++} ++ ++static inline int nf_conn_rtcache_iif_get(const struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ return rtc->cached_dst[dir].iif; ++} +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -106,6 +106,18 @@ config NF_CONNTRACK_EVENTS + + If unsure, say `N'. + ++config NF_CONNTRACK_RTCACHE ++ tristate "Cache route entries in conntrack objects" ++ depends on NETFILTER_ADVANCED ++ depends on NF_CONNTRACK ++ help ++ If this option is enabled, the connection tracking code will ++ cache routing information for each connection that is being ++ forwarded, at a cost of 32 bytes per conntrack object. ++ ++ To compile it as a module, choose M here. If unsure, say N. ++ The module will be called nf_conntrack_rtcache. ++ + config NF_CONNTRACK_TIMEOUT + bool 'Connection tracking timeout' + depends on NETFILTER_ADVANCED +--- a/net/netfilter/Makefile ++++ b/net/netfilter/Makefile +@@ -18,6 +18,9 @@ obj-$(CONFIG_NETFILTER_NETLINK_LOG) += n + # connection tracking + obj-$(CONFIG_NF_CONNTRACK) += nf_conntrack.o + ++# optional conntrack route cache extension ++obj-$(CONFIG_NF_CONNTRACK_RTCACHE) += nf_conntrack_rtcache.o ++ + # SCTP protocol connection tracking + obj-$(CONFIG_NF_CT_PROTO_DCCP) += nf_conntrack_proto_dccp.o + obj-$(CONFIG_NF_CT_PROTO_GRE) += nf_conntrack_proto_gre.o +--- /dev/null ++++ b/net/netfilter/nf_conntrack_rtcache.c +@@ -0,0 +1,391 @@ ++/* route cache for netfilter. ++ * ++ * (C) 2014 Red Hat GmbH ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++#include ++#endif ++ ++static void __nf_conn_rtcache_destroy(struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ struct dst_entry *dst = rtc->cached_dst[dir].dst; ++ ++ dst_release(dst); ++} ++ ++static void nf_conn_rtcache_destroy(struct nf_conn *ct) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ ++ if (!rtc) ++ return; ++ ++ __nf_conn_rtcache_destroy(rtc, IP_CT_DIR_ORIGINAL); ++ __nf_conn_rtcache_destroy(rtc, IP_CT_DIR_REPLY); ++} ++ ++static void nf_ct_rtcache_ext_add(struct nf_conn *ct) ++{ ++ struct nf_conn_rtcache *rtc; ++ ++ rtc = nf_ct_ext_add(ct, NF_CT_EXT_RTCACHE, GFP_ATOMIC); ++ if (rtc) { ++ rtc->cached_dst[IP_CT_DIR_ORIGINAL].iif = -1; ++ rtc->cached_dst[IP_CT_DIR_ORIGINAL].dst = NULL; ++ rtc->cached_dst[IP_CT_DIR_REPLY].iif = -1; ++ rtc->cached_dst[IP_CT_DIR_REPLY].dst = NULL; ++ } ++} ++ ++static struct nf_conn_rtcache *nf_ct_rtcache_find_usable(struct nf_conn *ct) ++{ ++ if (nf_ct_is_untracked(ct)) ++ return NULL; ++ return nf_ct_rtcache_find(ct); ++} ++ ++static struct dst_entry * ++nf_conn_rtcache_dst_get(const struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ return rtc->cached_dst[dir].dst; ++} ++ ++static u32 nf_rtcache_get_cookie(int pf, const struct dst_entry *dst) ++{ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ if (pf == NFPROTO_IPV6) { ++ const struct rt6_info *rt = (const struct rt6_info *)dst; ++ ++ if (rt->rt6i_node) ++ return (u32)rt->rt6i_node->fn_sernum; ++ } ++#endif ++ return 0; ++} ++ ++static void nf_conn_rtcache_dst_set(int pf, ++ struct nf_conn_rtcache *rtc, ++ struct dst_entry *dst, ++ enum ip_conntrack_dir dir, int iif) ++{ ++ if (rtc->cached_dst[dir].iif != iif) ++ rtc->cached_dst[dir].iif = iif; ++ ++ if (rtc->cached_dst[dir].dst != dst) { ++ struct dst_entry *old; ++ ++ dst_hold(dst); ++ ++ old = xchg(&rtc->cached_dst[dir].dst, dst); ++ dst_release(old); ++ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ if (pf == NFPROTO_IPV6) ++ rtc->cached_dst[dir].cookie = ++ nf_rtcache_get_cookie(pf, dst); ++#endif ++ } ++} ++ ++static void nf_conn_rtcache_dst_obsolete(struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ struct dst_entry *old; ++ ++ pr_debug("Invalidate iif %d for dir %d on cache %p\n", ++ rtc->cached_dst[dir].iif, dir, rtc); ++ ++ old = xchg(&rtc->cached_dst[dir].dst, NULL); ++ dst_release(old); ++ rtc->cached_dst[dir].iif = -1; ++} ++ ++static unsigned int nf_rtcache_in(const struct nf_hook_ops *ops, ++ struct sk_buff *skb, ++ const struct net_device *in, ++ const struct net_device *out, ++ int (*okfn)(struct sk_buff *)) ++{ ++ struct nf_conn_rtcache *rtc; ++ enum ip_conntrack_info ctinfo; ++ enum ip_conntrack_dir dir; ++ struct dst_entry *dst; ++ struct nf_conn *ct; ++ int iif; ++ u32 cookie; ++ ++ if (skb_dst(skb) || skb->sk) ++ return NF_ACCEPT; ++ ++ ct = nf_ct_get(skb, &ctinfo); ++ if (!ct) ++ return NF_ACCEPT; ++ ++ rtc = nf_ct_rtcache_find_usable(ct); ++ if (!rtc) ++ return NF_ACCEPT; ++ ++ /* if iif changes, don't use cache and let ip stack ++ * do route lookup. ++ * ++ * If rp_filter is enabled it might toss skb, so ++ * we don't want to avoid these checks. ++ */ ++ dir = CTINFO2DIR(ctinfo); ++ iif = nf_conn_rtcache_iif_get(rtc, dir); ++ if (in->ifindex != iif) { ++ pr_debug("ct %p, iif %d, cached iif %d, skip cached entry\n", ++ ct, iif, in->ifindex); ++ return NF_ACCEPT; ++ } ++ dst = nf_conn_rtcache_dst_get(rtc, dir); ++ if (dst == NULL) ++ return NF_ACCEPT; ++ ++ cookie = nf_rtcache_get_cookie(ops->pf, dst); ++ ++ dst = dst_check(dst, cookie); ++ pr_debug("obtained dst %p for skb %p, cookie %d\n", dst, skb, cookie); ++ if (likely(dst)) ++ skb_dst_set_noref_force(skb, dst); ++ else ++ nf_conn_rtcache_dst_obsolete(rtc, dir); ++ ++ return NF_ACCEPT; ++} ++ ++static unsigned int nf_rtcache_forward(const struct nf_hook_ops *ops, ++ struct sk_buff *skb, ++ const struct net_device *in, ++ const struct net_device *out, ++ int (*okfn)(struct sk_buff *)) ++{ ++ struct nf_conn_rtcache *rtc; ++ enum ip_conntrack_info ctinfo; ++ enum ip_conntrack_dir dir; ++ struct nf_conn *ct; ++ struct dst_entry *dst = skb_dst(skb); ++ int iif; ++ ++ ct = nf_ct_get(skb, &ctinfo); ++ if (!ct) ++ return NF_ACCEPT; ++ ++ if (dst && dst_xfrm(dst)) ++ return NF_ACCEPT; ++ ++ if (!nf_ct_is_confirmed(ct)) { ++ if (WARN_ON(nf_ct_rtcache_find(ct))) ++ return NF_ACCEPT; ++ nf_ct_rtcache_ext_add(ct); ++ return NF_ACCEPT; ++ } ++ ++ rtc = nf_ct_rtcache_find_usable(ct); ++ if (!rtc) ++ return NF_ACCEPT; ++ ++ dir = CTINFO2DIR(ctinfo); ++ iif = nf_conn_rtcache_iif_get(rtc, dir); ++ pr_debug("ct %p, skb %p, dir %d, iif %d, cached iif %d\n", ++ ct, skb, dir, iif, in->ifindex); ++ if (likely(in->ifindex == iif)) ++ return NF_ACCEPT; ++ ++ nf_conn_rtcache_dst_set(ops->pf, rtc, skb_dst(skb), dir, in->ifindex); ++ return NF_ACCEPT; ++} ++ ++static int nf_rtcache_dst_remove(struct nf_conn *ct, void *data) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ struct net_device *dev = data; ++ ++ if (!rtc) ++ return 0; ++ ++ if (dev->ifindex == rtc->cached_dst[IP_CT_DIR_ORIGINAL].iif || ++ dev->ifindex == rtc->cached_dst[IP_CT_DIR_REPLY].iif) { ++ nf_conn_rtcache_dst_obsolete(rtc, IP_CT_DIR_ORIGINAL); ++ nf_conn_rtcache_dst_obsolete(rtc, IP_CT_DIR_REPLY); ++ } ++ ++ return 0; ++} ++ ++static int nf_rtcache_netdev_event(struct notifier_block *this, ++ unsigned long event, void *ptr) ++{ ++ struct net_device *dev = netdev_notifier_info_to_dev(ptr); ++ struct net *net = dev_net(dev); ++ ++ if (event == NETDEV_DOWN) ++ nf_ct_iterate_cleanup(net, nf_rtcache_dst_remove, dev, 0, 0); ++ ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block nf_rtcache_notifier = { ++ .notifier_call = nf_rtcache_netdev_event, ++}; ++ ++static struct nf_hook_ops rtcache_ops[] = { ++ { ++ .hook = nf_rtcache_in, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV4, ++ .hooknum = NF_INET_PRE_ROUTING, ++ .priority = NF_IP_PRI_LAST, ++ }, ++ { ++ .hook = nf_rtcache_forward, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV4, ++ .hooknum = NF_INET_FORWARD, ++ .priority = NF_IP_PRI_LAST, ++ }, ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ { ++ .hook = nf_rtcache_in, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV6, ++ .hooknum = NF_INET_PRE_ROUTING, ++ .priority = NF_IP_PRI_LAST, ++ }, ++ { ++ .hook = nf_rtcache_forward, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV6, ++ .hooknum = NF_INET_FORWARD, ++ .priority = NF_IP_PRI_LAST, ++ }, ++#endif ++}; ++ ++static struct nf_ct_ext_type rtcache_extend __read_mostly = { ++ .len = sizeof(struct nf_conn_rtcache), ++ .align = __alignof__(struct nf_conn_rtcache), ++ .id = NF_CT_EXT_RTCACHE, ++ .destroy = nf_conn_rtcache_destroy, ++}; ++ ++static int __init nf_conntrack_rtcache_init(void) ++{ ++ int ret = nf_ct_extend_register(&rtcache_extend); ++ ++ if (ret < 0) { ++ pr_err("nf_conntrack_rtcache: Unable to register extension\n"); ++ return ret; ++ } ++ ++ ret = nf_register_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ if (ret < 0) { ++ nf_ct_extend_unregister(&rtcache_extend); ++ return ret; ++ } ++ ++ ret = register_netdevice_notifier(&nf_rtcache_notifier); ++ if (ret) { ++ nf_unregister_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ nf_ct_extend_unregister(&rtcache_extend); ++ } ++ ++ return ret; ++} ++ ++static int nf_rtcache_ext_remove(struct nf_conn *ct, void *data) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ ++ return rtc != NULL; ++} ++ ++static bool __exit nf_conntrack_rtcache_wait_for_dying(struct net *net) ++{ ++ bool wait = false; ++ int cpu; ++ ++ for_each_possible_cpu(cpu) { ++ struct nf_conntrack_tuple_hash *h; ++ struct hlist_nulls_node *n; ++ struct nf_conn *ct; ++ struct ct_pcpu *pcpu = per_cpu_ptr(net->ct.pcpu_lists, cpu); ++ ++ rcu_read_lock(); ++ spin_lock_bh(&pcpu->lock); ++ ++ hlist_nulls_for_each_entry(h, n, &pcpu->dying, hnnode) { ++ ct = nf_ct_tuplehash_to_ctrack(h); ++ if (nf_ct_rtcache_find(ct) != NULL) { ++ wait = true; ++ break; ++ } ++ } ++ spin_unlock_bh(&pcpu->lock); ++ rcu_read_unlock(); ++ } ++ ++ return wait; ++} ++ ++static void __exit nf_conntrack_rtcache_fini(void) ++{ ++ struct net *net; ++ int count = 0; ++ ++ /* remove hooks so no new connections get rtcache extension */ ++ nf_unregister_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ ++ synchronize_net(); ++ ++ unregister_netdevice_notifier(&nf_rtcache_notifier); ++ ++ rtnl_lock(); ++ ++ /* zap all conntracks with rtcache extension */ ++ for_each_net(net) ++ nf_ct_iterate_cleanup(net, nf_rtcache_ext_remove, NULL, 0, 0); ++ ++ for_each_net(net) { ++ /* .. and make sure they're gone from dying list, too */ ++ while (nf_conntrack_rtcache_wait_for_dying(net)) { ++ msleep(200); ++ WARN_ONCE(++count > 25, "Waiting for all rtcache conntracks to go away\n"); ++ } ++ } ++ ++ rtnl_unlock(); ++ synchronize_net(); ++ nf_ct_extend_unregister(&rtcache_extend); ++} ++module_init(nf_conntrack_rtcache_init); ++module_exit(nf_conntrack_rtcache_fini); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Florian Westphal "); ++MODULE_DESCRIPTION("Conntrack route cache extension"); diff --git a/target/linux/generic/patches-3.18/051-02-bridge-allow-setting-hash_max-multicast_router-if-in.patch b/target/linux/generic/patches-3.18/051-02-bridge-allow-setting-hash_max-multicast_router-if-in.patch new file mode 100644 index 0000000..f7f88f8 --- /dev/null +++ b/target/linux/generic/patches-3.18/051-02-bridge-allow-setting-hash_max-multicast_router-if-in.patch @@ -0,0 +1,99 @@ +From 6ae4ae8e512bd229f806c22f8a2cd751e4f987c2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Linus=20L=C3=BCssing?= +Date: Sat, 23 May 2015 03:12:34 +0200 +Subject: [PATCH] bridge: allow setting hash_max + multicast_router if + interface is down +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Network managers like netifd (used in OpenWRT for instance) try to +configure interface options after creation but before setting the +interface up. + +Unfortunately the sysfs / bridge currently only allows to configure the +hash_max and multicast_router options when the bridge interface is up. +But since br_multicast_init() doesn't start any timers and only sets +default values and initializes timers it should be save to reconfigure +the default values after that, before things actually get active after +the bridge is set up. + +Signed-off-by: Linus Lüssing +Signed-off-by: David S. Miller +--- + net/bridge/br_multicast.c | 24 +++--------------------- + 1 file changed, 3 insertions(+), 21 deletions(-) + +--- a/net/bridge/br_multicast.c ++++ b/net/bridge/br_multicast.c +@@ -1948,11 +1948,9 @@ out: + + int br_multicast_set_router(struct net_bridge *br, unsigned long val) + { +- int err = -ENOENT; ++ int err = -EINVAL; + + spin_lock_bh(&br->multicast_lock); +- if (!netif_running(br->dev)) +- goto unlock; + + switch (val) { + case 0: +@@ -1963,13 +1961,8 @@ int br_multicast_set_router(struct net_b + br->multicast_router = val; + err = 0; + break; +- +- default: +- err = -EINVAL; +- break; + } + +-unlock: + spin_unlock_bh(&br->multicast_lock); + + return err; +@@ -1978,11 +1971,9 @@ unlock: + int br_multicast_set_port_router(struct net_bridge_port *p, unsigned long val) + { + struct net_bridge *br = p->br; +- int err = -ENOENT; ++ int err = -EINVAL; + + spin_lock(&br->multicast_lock); +- if (!netif_running(br->dev) || p->state == BR_STATE_DISABLED) +- goto unlock; + + switch (val) { + case 0: +@@ -2004,13 +1995,8 @@ int br_multicast_set_port_router(struct + + br_multicast_add_router(br, p); + break; +- +- default: +- err = -EINVAL; +- break; + } + +-unlock: + spin_unlock(&br->multicast_lock); + + return err; +@@ -2115,15 +2101,11 @@ unlock: + + int br_multicast_set_hash_max(struct net_bridge *br, unsigned long val) + { +- int err = -ENOENT; ++ int err = -EINVAL; + u32 old; + struct net_bridge_mdb_htable *mdb; + + spin_lock_bh(&br->multicast_lock); +- if (!netif_running(br->dev)) +- goto unlock; +- +- err = -EINVAL; + if (!is_power_of_2(val)) + goto unlock; + diff --git a/target/linux/generic/patches-3.18/060-mips_decompressor_memmove.patch b/target/linux/generic/patches-3.18/060-mips_decompressor_memmove.patch new file mode 100644 index 0000000..d215b80 --- /dev/null +++ b/target/linux/generic/patches-3.18/060-mips_decompressor_memmove.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/boot/compressed/string.c ++++ b/arch/mips/boot/compressed/string.c +@@ -26,3 +26,19 @@ void *memset(void *s, int c, size_t n) + ss[i] = c; + return s; + } ++ ++void *memmove(void *__dest, __const void *__src, size_t count) ++{ ++ unsigned char *d = __dest; ++ const unsigned char *s = __src; ++ ++ if (__dest == __src) ++ return __dest; ++ ++ if (__dest < __src) ++ return memcpy(__dest, __src, count); ++ ++ while (count--) ++ d[count] = s[count]; ++ return __dest; ++} diff --git a/target/linux/generic/patches-3.18/070-bgmac-register-napi-before-the-device.patch b/target/linux/generic/patches-3.18/070-bgmac-register-napi-before-the-device.patch new file mode 100644 index 0000000..aa45860 --- /dev/null +++ b/target/linux/generic/patches-3.18/070-bgmac-register-napi-before-the-device.patch @@ -0,0 +1,44 @@ +From 6216642f200258708e47170ff14ba8ecb486f4f0 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 18 Jan 2015 19:49:58 +0100 +Subject: [PATCH] bgmac: register napi before the device + +napi should get registered before the netdev and not after. + +Signed-off-by: Hauke Mehrtens +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1515,6 +1515,8 @@ static int bgmac_probe(struct bcma_devic + if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM) + bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n"); + ++ netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); ++ + err = bgmac_mii_register(bgmac); + if (err) { + bgmac_err(bgmac, "Cannot register MDIO\n"); +@@ -1529,8 +1531,6 @@ static int bgmac_probe(struct bcma_devic + + netif_carrier_off(net_dev); + +- netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); +- + return 0; + + err_mii_unregister: +@@ -1549,9 +1549,9 @@ static void bgmac_remove(struct bcma_dev + { + struct bgmac *bgmac = bcma_get_drvdata(core); + +- netif_napi_del(&bgmac->napi); + unregister_netdev(bgmac->net_dev); + bgmac_mii_unregister(bgmac); ++ netif_napi_del(&bgmac->napi); + bgmac_dma_free(bgmac); + bcma_set_drvdata(core, NULL); + free_netdev(bgmac->net_dev); diff --git a/target/linux/generic/patches-3.18/071-bgmac-activate-irqs-only-if-there-is-nothing-to-poll.patch b/target/linux/generic/patches-3.18/071-bgmac-activate-irqs-only-if-there-is-nothing-to-poll.patch new file mode 100644 index 0000000..cc43d36 --- /dev/null +++ b/target/linux/generic/patches-3.18/071-bgmac-activate-irqs-only-if-there-is-nothing-to-poll.patch @@ -0,0 +1,30 @@ +From 43f159c60a99318b1ef7d1d7c16c4dfdd06bfd90 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 18 Jan 2015 19:49:59 +0100 +Subject: [PATCH] bgmac: activate irqs only if there is nothing to poll + +IRQs should only get activated when there is nothing to poll in the +queue any more and to after every poll. + +Signed-off-by: Hauke Mehrtens +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1167,10 +1167,10 @@ static int bgmac_poll(struct napi_struct + bgmac->int_status = 0; + } + +- if (handled < weight) ++ if (handled < weight) { + napi_complete(napi); +- +- bgmac_chip_intrs_on(bgmac); ++ bgmac_chip_intrs_on(bgmac); ++ } + + return handled; + } diff --git a/target/linux/generic/patches-3.18/072-bgmac-fix-device-initialization-on-Northstar-SoCs-co.patch b/target/linux/generic/patches-3.18/072-bgmac-fix-device-initialization-on-Northstar-SoCs-co.patch new file mode 100644 index 0000000..121d2f4 --- /dev/null +++ b/target/linux/generic/patches-3.18/072-bgmac-fix-device-initialization-on-Northstar-SoCs-co.patch @@ -0,0 +1,40 @@ +From 21697336d46b71dd031f29e426dda0b1e7f06cc0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 11 Feb 2015 18:06:34 +0100 +Subject: [PATCH] bgmac: fix device initialization on Northstar SoCs (condition + typo) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +On Northstar (Broadcom's ARM architecture) we need to manually enable +all cores. Code for that is already in place, but the condition for it +was wrong. + +Signed-off-by: Rafał Miłecki +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1412,6 +1412,7 @@ static void bgmac_mii_unregister(struct + /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */ + static int bgmac_probe(struct bcma_device *core) + { ++ struct bcma_chipinfo *ci = &core->bus->chipinfo; + struct net_device *net_dev; + struct bgmac *bgmac; + struct ssb_sprom *sprom = &core->bus->sprom; +@@ -1474,8 +1475,8 @@ static int bgmac_probe(struct bcma_devic + bgmac_chip_reset(bgmac); + + /* For Northstar, we have to take all GMAC core out of reset */ +- if (core->id.id == BCMA_CHIP_ID_BCM4707 || +- core->id.id == BCMA_CHIP_ID_BCM53018) { ++ if (ci->id == BCMA_CHIP_ID_BCM4707 || ++ ci->id == BCMA_CHIP_ID_BCM53018) { + struct bcma_device *ns_core; + int ns_gmac; + diff --git a/target/linux/generic/patches-3.18/073-bgmac-Clean-warning-messages.patch b/target/linux/generic/patches-3.18/073-bgmac-Clean-warning-messages.patch new file mode 100644 index 0000000..17fe5df --- /dev/null +++ b/target/linux/generic/patches-3.18/073-bgmac-Clean-warning-messages.patch @@ -0,0 +1,50 @@ +From 8edfe3b6fad28da191c8fa15e4e0d8f7335a0091 Mon Sep 17 00:00:00 2001 +From: Peter Senna Tschudin +Date: Sat, 7 Mar 2015 12:10:26 +0100 +Subject: [PATCH] bgmac: Clean warning messages +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +On my test environment the throughput of a file transfer drops +from 4.4MBps to 116KBps due the number of repeated warning +messages. This patch removes the warning messages as DMA works +correctly with addresses using 0xC0000000 bits. + +Signed-off-by: Peter Senna Tschudin +Acked-by: Rafał Miłecki +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 7 ------- + 1 file changed, 7 deletions(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -302,9 +302,6 @@ static int bgmac_dma_rx_skb_for_slot(str + slot->skb = skb; + slot->dma_addr = dma_addr; + +- if (slot->dma_addr & 0xC0000000) +- bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); +- + return 0; + } + +@@ -505,8 +502,6 @@ static int bgmac_dma_alloc(struct bgmac + ring->mmio_base); + goto err_dma_free; + } +- if (ring->dma_base & 0xC0000000) +- bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); + + ring->unaligned = bgmac_dma_unaligned(bgmac, ring, + BGMAC_DMA_RING_TX); +@@ -536,8 +531,6 @@ static int bgmac_dma_alloc(struct bgmac + err = -ENOMEM; + goto err_dma_free; + } +- if (ring->dma_base & 0xC0000000) +- bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n"); + + ring->unaligned = bgmac_dma_unaligned(bgmac, ring, + BGMAC_DMA_RING_RX); diff --git a/target/linux/generic/patches-3.18/074-bgmac-register-fixed-PHY-for-ARM-BCM470X-BCM5301X-ch.patch b/target/linux/generic/patches-3.18/074-bgmac-register-fixed-PHY-for-ARM-BCM470X-BCM5301X-ch.patch new file mode 100644 index 0000000..9f0baff --- /dev/null +++ b/target/linux/generic/patches-3.18/074-bgmac-register-fixed-PHY-for-ARM-BCM470X-BCM5301X-ch.patch @@ -0,0 +1,76 @@ +From c25b23b8a387e7d31f7a74af8e37b61e9e6ebb21 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 20 Mar 2015 23:14:31 +0100 +Subject: [PATCH] bgmac: register fixed PHY for ARM BCM470X / BCM5301X chipsets +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +On ARM SoCs with bgmac Ethernet hardware we don't have any normal PHY. +There is always a switch attached but it's not even controlled over MDIO +like in case of MIPS devices. +We need a fixed PHY to be able to send/receive packets from the switch. + +Signed-off-by: Rafał Miłecki +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 34 ++++++++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1330,13 +1331,46 @@ static void bgmac_adjust_link(struct net + } + } + ++static int bgmac_fixed_phy_register(struct bgmac *bgmac) ++{ ++ struct fixed_phy_status fphy_status = { ++ .link = 1, ++ .speed = SPEED_1000, ++ .duplex = DUPLEX_FULL, ++ }; ++ struct phy_device *phy_dev; ++ int err; ++ ++ phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); ++ if (!phy_dev || IS_ERR(phy_dev)) { ++ bgmac_err(bgmac, "Failed to register fixed PHY device\n"); ++ return -ENODEV; ++ } ++ ++ err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, ++ PHY_INTERFACE_MODE_MII); ++ if (err) { ++ bgmac_err(bgmac, "Connecting PHY failed\n"); ++ return err; ++ } ++ ++ bgmac->phy_dev = phy_dev; ++ ++ return err; ++} ++ + static int bgmac_mii_register(struct bgmac *bgmac) + { ++ struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + char bus_id[MII_BUS_ID_SIZE + 3]; + int i, err = 0; + ++ if (ci->id == BCMA_CHIP_ID_BCM4707 || ++ ci->id == BCMA_CHIP_ID_BCM53018) ++ return bgmac_fixed_phy_register(bgmac); ++ + mii_bus = mdiobus_alloc(); + if (!mii_bus) + return -ENOMEM; diff --git a/target/linux/generic/patches-3.18/075-bgmac-allow-enabling-on-ARCH_BCM_5301X.patch b/target/linux/generic/patches-3.18/075-bgmac-allow-enabling-on-ARCH_BCM_5301X.patch new file mode 100644 index 0000000..4513667 --- /dev/null +++ b/target/linux/generic/patches-3.18/075-bgmac-allow-enabling-on-ARCH_BCM_5301X.patch @@ -0,0 +1,28 @@ +From fc300dc3733fdc328e6e10c7b8379b60c26cd648 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 20 Mar 2015 23:14:32 +0100 +Subject: [PATCH] bgmac: allow enabling on ARCH_BCM_5301X +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Home routers based on ARM SoCs like BCM4708 also have bcma bus with core +supported by bgmac. + +Signed-off-by: Rafał Miłecki +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/broadcom/Kconfig ++++ b/drivers/net/ethernet/broadcom/Kconfig +@@ -143,7 +143,7 @@ config BNX2X_SRIOV + + config BGMAC + tristate "BCMA bus GBit core support" +- depends on BCMA_HOST_SOC && HAS_DMA && BCM47XX ++ depends on BCMA_HOST_SOC && HAS_DMA && (BCM47XX || ARCH_BCM_5301X) + select PHYLIB + ---help--- + This driver supports GBit MAC and BCM4706 GBit MAC cores on BCMA bus. diff --git a/target/linux/generic/patches-3.18/076-net-phy-export-fixed_phy_register.patch b/target/linux/generic/patches-3.18/076-net-phy-export-fixed_phy_register.patch new file mode 100644 index 0000000..939016c --- /dev/null +++ b/target/linux/generic/patches-3.18/076-net-phy-export-fixed_phy_register.patch @@ -0,0 +1,30 @@ +From 37e9a6904520b525b542ecd67201164d06fdb95a Mon Sep 17 00:00:00 2001 +From: Mark Salter +Date: Thu, 11 Dec 2014 23:03:26 -0500 +Subject: [PATCH] net: phy: export fixed_phy_register() + +When building the bcmgenet driver as module, I get: + +ERROR: "fixed_phy_register" [drivers/net/ethernet/broadcom/genet/genet.ko] undefined! + +commit b0ba512e225d72 ("net: bcmgenet: enable driver to work without device +tree") which added a call to fixed_phy_register. But fixed_phy_register +needs to be exported if used from a module. + +Signed-off-by: Mark Salter +Acked-by: Florian Fainelli +Signed-off-by: David S. Miller +--- + drivers/net/phy/fixed.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/phy/fixed.c ++++ b/drivers/net/phy/fixed.c +@@ -274,6 +274,7 @@ struct phy_device *fixed_phy_register(un + + return phy; + } ++EXPORT_SYMBOL_GPL(fixed_phy_register); + + static int __init fixed_mdio_bus_init(void) + { diff --git a/target/linux/generic/patches-3.18/077-01-bgmac-fix-descriptor-frame-start-end-definitions.patch b/target/linux/generic/patches-3.18/077-01-bgmac-fix-descriptor-frame-start-end-definitions.patch new file mode 100644 index 0000000..fdfae3a --- /dev/null +++ b/target/linux/generic/patches-3.18/077-01-bgmac-fix-descriptor-frame-start-end-definitions.patch @@ -0,0 +1,24 @@ +From: Felix Fietkau +Date: Mon, 23 Mar 2015 02:40:06 +0100 +Subject: [PATCH] bgmac: fix descriptor frame start/end definitions + +The start-of-frame and end-of-frame bits were accidentally swapped. +In the current code it does not make any difference, since they are +always used together. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -345,8 +345,8 @@ + + #define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */ + #define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */ +-#define BGMAC_DESC_CTL0_SOF 0x40000000 /* Start of frame */ +-#define BGMAC_DESC_CTL0_EOF 0x80000000 /* End of frame */ ++#define BGMAC_DESC_CTL0_EOF 0x40000000 /* End of frame */ ++#define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */ + #define BGMAC_DESC_CTL1_LEN 0x00001FFF + + #define BGMAC_PHY_NOREGS 0x1E diff --git a/target/linux/generic/patches-3.18/077-02-bgmac-implement-GRO-and-use-build_skb.patch b/target/linux/generic/patches-3.18/077-02-bgmac-implement-GRO-and-use-build_skb.patch new file mode 100644 index 0000000..2a2df60 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-02-bgmac-implement-GRO-and-use-build_skb.patch @@ -0,0 +1,189 @@ +From: Felix Fietkau +Date: Mon, 23 Mar 2015 02:41:25 +0100 +Subject: [PATCH] bgmac: implement GRO and use build_skb + +This improves performance for routing and local rx + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -276,31 +276,31 @@ static int bgmac_dma_rx_skb_for_slot(str + struct bgmac_slot_info *slot) + { + struct device *dma_dev = bgmac->core->dma_dev; +- struct sk_buff *skb; + dma_addr_t dma_addr; + struct bgmac_rx_header *rx; ++ void *buf; + + /* Alloc skb */ +- skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE); +- if (!skb) ++ buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); ++ if (!buf) + return -ENOMEM; + + /* Poison - if everything goes fine, hardware will overwrite it */ +- rx = (struct bgmac_rx_header *)skb->data; ++ rx = buf; + rx->len = cpu_to_le16(0xdead); + rx->flags = cpu_to_le16(0xbeef); + + /* Map skb for the DMA */ +- dma_addr = dma_map_single(dma_dev, skb->data, +- BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); ++ dma_addr = dma_map_single(dma_dev, buf, BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); + if (dma_mapping_error(dma_dev, dma_addr)) { + bgmac_err(bgmac, "DMA mapping error\n"); +- dev_kfree_skb(skb); ++ put_page(virt_to_head_page(buf)); + return -ENOMEM; + } + + /* Update the slot */ +- slot->skb = skb; ++ slot->buf = buf; + slot->dma_addr = dma_addr; + + return 0; +@@ -343,8 +343,9 @@ static int bgmac_dma_rx_read(struct bgma + while (ring->start != ring->end) { + struct device *dma_dev = bgmac->core->dma_dev; + struct bgmac_slot_info *slot = &ring->slots[ring->start]; +- struct sk_buff *skb = slot->skb; +- struct bgmac_rx_header *rx; ++ struct bgmac_rx_header *rx = slot->buf; ++ struct sk_buff *skb; ++ void *buf = slot->buf; + u16 len, flags; + + /* Unmap buffer to make it accessible to the CPU */ +@@ -352,7 +353,6 @@ static int bgmac_dma_rx_read(struct bgma + BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); + + /* Get info from the header */ +- rx = (struct bgmac_rx_header *)skb->data; + len = le16_to_cpu(rx->len); + flags = le16_to_cpu(rx->flags); + +@@ -393,12 +393,13 @@ static int bgmac_dma_rx_read(struct bgma + dma_unmap_single(dma_dev, old_dma_addr, + BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); + ++ skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); + skb_put(skb, BGMAC_RX_FRAME_OFFSET + len); + skb_pull(skb, BGMAC_RX_FRAME_OFFSET); + + skb_checksum_none_assert(skb); + skb->protocol = eth_type_trans(skb, bgmac->net_dev); +- netif_receive_skb(skb); ++ napi_gro_receive(&bgmac->napi, skb); + handled++; + } while (0); + +@@ -434,12 +435,11 @@ static bool bgmac_dma_unaligned(struct b + return false; + } + +-static void bgmac_dma_ring_free(struct bgmac *bgmac, +- struct bgmac_dma_ring *ring) ++static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) + { + struct device *dma_dev = bgmac->core->dma_dev; + struct bgmac_slot_info *slot; +- int size; + int i; + + for (i = 0; i < ring->num_slots; i++) { +@@ -451,23 +451,55 @@ static void bgmac_dma_ring_free(struct b + dev_kfree_skb(slot->skb); + } + } ++} ++ ++static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_slot_info *slot; ++ int i; ++ ++ for (i = 0; i < ring->num_slots; i++) { ++ slot = &ring->slots[i]; ++ if (!slot->buf) ++ continue; + +- if (ring->cpu_base) { +- /* Free ring of descriptors */ +- size = ring->num_slots * sizeof(struct bgmac_dma_desc); +- dma_free_coherent(dma_dev, size, ring->cpu_base, +- ring->dma_base); ++ if (slot->dma_addr) ++ dma_unmap_single(dma_dev, slot->dma_addr, ++ BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++ put_page(virt_to_head_page(slot->buf)); + } + } + ++static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ int size; ++ ++ if (!ring->cpu_base) ++ return; ++ ++ /* Free ring of descriptors */ ++ size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ dma_free_coherent(dma_dev, size, ring->cpu_base, ++ ring->dma_base); ++} ++ + static void bgmac_dma_free(struct bgmac *bgmac) + { + int i; + +- for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) +- bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]); +- for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) +- bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]); ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { ++ bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); ++ } ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { ++ bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); ++ } + } + + static int bgmac_dma_alloc(struct bgmac *bgmac) +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -362,6 +362,8 @@ + #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ + #define BGMAC_RX_MAX_FRAME_SIZE 1536 /* Copied from b44/tg3 */ + #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) ++#define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE) + \ ++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) + + #define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */ + #define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */ +@@ -383,7 +385,10 @@ + #define ETHER_MAX_LEN 1518 + + struct bgmac_slot_info { +- struct sk_buff *skb; ++ union { ++ struct sk_buff *skb; ++ void *buf; ++ }; + dma_addr_t dma_addr; + }; + diff --git a/target/linux/generic/patches-3.18/077-03-bgmac-implement-scatter-gather-support.patch b/target/linux/generic/patches-3.18/077-03-bgmac-implement-scatter-gather-support.patch new file mode 100644 index 0000000..5cb21a5 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-03-bgmac-implement-scatter-gather-support.patch @@ -0,0 +1,267 @@ +From: Felix Fietkau +Date: Mon, 23 Mar 2015 02:42:26 +0100 +Subject: [PATCH] bgmac: implement scatter/gather support + +Always use software checksumming, since the hardware does not have any +checksum offload support. +This significantly improves local TCP tx performance. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -115,53 +115,91 @@ static void bgmac_dma_tx_enable(struct b + bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); + } + ++static void ++bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, ++ int i, int len, u32 ctl0) ++{ ++ struct bgmac_slot_info *slot; ++ struct bgmac_dma_desc *dma_desc; ++ u32 ctl1; ++ ++ if (i == ring->num_slots - 1) ++ ctl0 |= BGMAC_DESC_CTL0_EOT; ++ ++ ctl1 = len & BGMAC_DESC_CTL1_LEN; ++ ++ slot = &ring->slots[i]; ++ dma_desc = &ring->cpu_base[i]; ++ dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); ++ dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); ++ dma_desc->ctl0 = cpu_to_le32(ctl0); ++ dma_desc->ctl1 = cpu_to_le32(ctl1); ++} ++ + static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, + struct bgmac_dma_ring *ring, + struct sk_buff *skb) + { + struct device *dma_dev = bgmac->core->dma_dev; + struct net_device *net_dev = bgmac->net_dev; +- struct bgmac_dma_desc *dma_desc; +- struct bgmac_slot_info *slot; +- u32 ctl0, ctl1; ++ struct bgmac_slot_info *slot = &ring->slots[ring->end]; + int free_slots; ++ int nr_frags; ++ u32 flags; ++ int index = ring->end; ++ int i; + + if (skb->len > BGMAC_DESC_CTL1_LEN) { + bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); +- goto err_stop_drop; ++ goto err_drop; + } + ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ skb_checksum_help(skb); ++ ++ nr_frags = skb_shinfo(skb)->nr_frags; ++ + if (ring->start <= ring->end) + free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS; + else + free_slots = ring->start - ring->end; +- if (free_slots == 1) { ++ ++ if (free_slots <= nr_frags + 1) { + bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); + netif_stop_queue(net_dev); + return NETDEV_TX_BUSY; + } + +- slot = &ring->slots[ring->end]; +- slot->skb = skb; +- slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len, ++ slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), + DMA_TO_DEVICE); +- if (dma_mapping_error(dma_dev, slot->dma_addr)) { +- bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", +- ring->mmio_base); +- goto err_stop_drop; +- } ++ if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) ++ goto err_dma_head; + +- ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF; +- if (ring->end == ring->num_slots - 1) +- ctl0 |= BGMAC_DESC_CTL0_EOT; +- ctl1 = skb->len & BGMAC_DESC_CTL1_LEN; ++ flags = BGMAC_DESC_CTL0_SOF; ++ if (!nr_frags) ++ flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; ++ ++ bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); ++ flags = 0; ++ ++ for (i = 0; i < nr_frags; i++) { ++ struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; ++ int len = skb_frag_size(frag); ++ ++ index = (index + 1) % BGMAC_TX_RING_SLOTS; ++ slot = &ring->slots[index]; ++ slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, ++ len, DMA_TO_DEVICE); ++ if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) ++ goto err_dma; + +- dma_desc = ring->cpu_base; +- dma_desc += ring->end; +- dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); +- dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); +- dma_desc->ctl0 = cpu_to_le32(ctl0); +- dma_desc->ctl1 = cpu_to_le32(ctl1); ++ if (i == nr_frags - 1) ++ flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; ++ ++ bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); ++ } ++ ++ slot->skb = skb; + + netdev_sent_queue(net_dev, skb->len); + +@@ -170,20 +208,35 @@ static netdev_tx_t bgmac_dma_tx_add(stru + /* Increase ring->end to point empty slot. We tell hardware the first + * slot it should *not* read. + */ +- if (++ring->end >= BGMAC_TX_RING_SLOTS) +- ring->end = 0; ++ ring->end = (index + 1) % BGMAC_TX_RING_SLOTS; + bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, + ring->index_base + + ring->end * sizeof(struct bgmac_dma_desc)); + +- /* Always keep one slot free to allow detecting bugged calls. */ +- if (--free_slots == 1) ++ free_slots -= nr_frags + 1; ++ if (free_slots < 8) + netif_stop_queue(net_dev); + + return NETDEV_TX_OK; + +-err_stop_drop: +- netif_stop_queue(net_dev); ++err_dma: ++ dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), ++ DMA_TO_DEVICE); ++ ++ while (i > 0) { ++ int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; ++ struct bgmac_slot_info *slot = &ring->slots[index]; ++ u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); ++ int len = ctl1 & BGMAC_DESC_CTL1_LEN; ++ ++ dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); ++ } ++ ++err_dma_head: ++ bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", ++ ring->mmio_base); ++ ++err_drop: + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } +@@ -205,32 +258,45 @@ static void bgmac_dma_tx_free(struct bgm + + while (ring->start != empty_slot) { + struct bgmac_slot_info *slot = &ring->slots[ring->start]; ++ u32 ctl1 = le32_to_cpu(ring->cpu_base[ring->start].ctl1); ++ int len = ctl1 & BGMAC_DESC_CTL1_LEN; + +- if (slot->skb) { ++ if (!slot->dma_addr) { ++ bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", ++ ring->start, ring->end); ++ goto next; ++ } ++ ++ if (ctl1 & BGMAC_DESC_CTL0_SOF) + /* Unmap no longer used buffer */ +- dma_unmap_single(dma_dev, slot->dma_addr, +- slot->skb->len, DMA_TO_DEVICE); +- slot->dma_addr = 0; ++ dma_unmap_single(dma_dev, slot->dma_addr, len, ++ DMA_TO_DEVICE); ++ else ++ dma_unmap_page(dma_dev, slot->dma_addr, len, ++ DMA_TO_DEVICE); + ++ if (slot->skb) { + bytes_compl += slot->skb->len; + pkts_compl++; + + /* Free memory! :) */ + dev_kfree_skb(slot->skb); + slot->skb = NULL; +- } else { +- bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", +- ring->start, ring->end); + } + ++next: ++ slot->dma_addr = 0; + if (++ring->start >= BGMAC_TX_RING_SLOTS) + ring->start = 0; + freed = true; + } + ++ if (!pkts_compl) ++ return; ++ + netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); + +- if (freed && netif_queue_stopped(bgmac->net_dev)) ++ if (netif_queue_stopped(bgmac->net_dev)) + netif_wake_queue(bgmac->net_dev); + } + +@@ -439,17 +505,25 @@ static void bgmac_dma_tx_ring_free(struc + struct bgmac_dma_ring *ring) + { + struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_dma_desc *dma_desc = ring->cpu_base; + struct bgmac_slot_info *slot; + int i; + + for (i = 0; i < ring->num_slots; i++) { ++ int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; ++ + slot = &ring->slots[i]; +- if (slot->skb) { +- if (slot->dma_addr) +- dma_unmap_single(dma_dev, slot->dma_addr, +- slot->skb->len, DMA_TO_DEVICE); +- dev_kfree_skb(slot->skb); +- } ++ dev_kfree_skb(slot->skb); ++ ++ if (!slot->dma_addr) ++ continue; ++ ++ if (slot->skb) ++ dma_unmap_single(dma_dev, slot->dma_addr, ++ len, DMA_TO_DEVICE); ++ else ++ dma_unmap_page(dma_dev, slot->dma_addr, ++ len, DMA_TO_DEVICE); + } + } + +@@ -1583,6 +1657,10 @@ static int bgmac_probe(struct bcma_devic + goto err_dma_free; + } + ++ net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; ++ net_dev->hw_features = net_dev->features; ++ net_dev->vlan_features = net_dev->features; ++ + err = register_netdev(bgmac->net_dev); + if (err) { + bgmac_err(bgmac, "Cannot register net device\n"); diff --git a/target/linux/generic/patches-3.18/077-04-bgmac-simplify-tx-ring-index-handling.patch b/target/linux/generic/patches-3.18/077-04-bgmac-simplify-tx-ring-index-handling.patch new file mode 100644 index 0000000..241a308 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-04-bgmac-simplify-tx-ring-index-handling.patch @@ -0,0 +1,125 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 09:58:56 +0200 +Subject: [PATCH] bgmac: simplify tx ring index handling + +Keep incrementing ring->start and ring->end instead of pointing it to +the actual ring slot entry. This simplifies the calculation of the +number of free slots. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -142,11 +142,10 @@ static netdev_tx_t bgmac_dma_tx_add(stru + { + struct device *dma_dev = bgmac->core->dma_dev; + struct net_device *net_dev = bgmac->net_dev; +- struct bgmac_slot_info *slot = &ring->slots[ring->end]; +- int free_slots; ++ int index = ring->end % BGMAC_TX_RING_SLOTS; ++ struct bgmac_slot_info *slot = &ring->slots[index]; + int nr_frags; + u32 flags; +- int index = ring->end; + int i; + + if (skb->len > BGMAC_DESC_CTL1_LEN) { +@@ -159,12 +158,10 @@ static netdev_tx_t bgmac_dma_tx_add(stru + + nr_frags = skb_shinfo(skb)->nr_frags; + +- if (ring->start <= ring->end) +- free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS; +- else +- free_slots = ring->start - ring->end; +- +- if (free_slots <= nr_frags + 1) { ++ /* ring->end - ring->start will return the number of valid slots, ++ * even when ring->end overflows ++ */ ++ if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { + bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); + netif_stop_queue(net_dev); + return NETDEV_TX_BUSY; +@@ -200,7 +197,7 @@ static netdev_tx_t bgmac_dma_tx_add(stru + } + + slot->skb = skb; +- ++ ring->end += nr_frags + 1; + netdev_sent_queue(net_dev, skb->len); + + wmb(); +@@ -208,13 +205,12 @@ static netdev_tx_t bgmac_dma_tx_add(stru + /* Increase ring->end to point empty slot. We tell hardware the first + * slot it should *not* read. + */ +- ring->end = (index + 1) % BGMAC_TX_RING_SLOTS; + bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, + ring->index_base + +- ring->end * sizeof(struct bgmac_dma_desc)); ++ (ring->end % BGMAC_TX_RING_SLOTS) * ++ sizeof(struct bgmac_dma_desc)); + +- free_slots -= nr_frags + 1; +- if (free_slots < 8) ++ if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) + netif_stop_queue(net_dev); + + return NETDEV_TX_OK; +@@ -256,17 +252,17 @@ static void bgmac_dma_tx_free(struct bgm + empty_slot &= BGMAC_DMA_TX_STATDPTR; + empty_slot /= sizeof(struct bgmac_dma_desc); + +- while (ring->start != empty_slot) { +- struct bgmac_slot_info *slot = &ring->slots[ring->start]; +- u32 ctl1 = le32_to_cpu(ring->cpu_base[ring->start].ctl1); +- int len = ctl1 & BGMAC_DESC_CTL1_LEN; ++ while (ring->start != ring->end) { ++ int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; ++ struct bgmac_slot_info *slot = &ring->slots[slot_idx]; ++ u32 ctl1; ++ int len; + +- if (!slot->dma_addr) { +- bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", +- ring->start, ring->end); +- goto next; +- } ++ if (slot_idx == empty_slot) ++ break; + ++ ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); ++ len = ctl1 & BGMAC_DESC_CTL1_LEN; + if (ctl1 & BGMAC_DESC_CTL0_SOF) + /* Unmap no longer used buffer */ + dma_unmap_single(dma_dev, slot->dma_addr, len, +@@ -284,10 +280,8 @@ static void bgmac_dma_tx_free(struct bgm + slot->skb = NULL; + } + +-next: + slot->dma_addr = 0; +- if (++ring->start >= BGMAC_TX_RING_SLOTS) +- ring->start = 0; ++ ring->start++; + freed = true; + } + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -414,10 +414,10 @@ enum bgmac_dma_ring_type { + * empty. + */ + struct bgmac_dma_ring { +- u16 num_slots; +- u16 start; +- u16 end; ++ u32 start; ++ u32 end; + ++ u16 num_slots; + u16 mmio_base; + struct bgmac_dma_desc *cpu_base; + dma_addr_t dma_base; diff --git a/target/linux/generic/patches-3.18/077-05-bgmac-leave-interrupts-disabled-as-long-as-there-is-.patch b/target/linux/generic/patches-3.18/077-05-bgmac-leave-interrupts-disabled-as-long-as-there-is-.patch new file mode 100644 index 0000000..3bbe9ea --- /dev/null +++ b/target/linux/generic/patches-3.18/077-05-bgmac-leave-interrupts-disabled-as-long-as-there-is-.patch @@ -0,0 +1,87 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 10:08:04 +0200 +Subject: [PATCH] bgmac: leave interrupts disabled as long as there is work + to do + +Always poll rx and tx during NAPI poll instead of relying on the status +of the first interrupt. This prevents bgmac_poll from leaving unfinished +work around until the next IRQ. +In my tests this makes bridging/routing throughput under heavy load more +stable and ensures that no new IRQs arrive as long as bgmac_poll uses up +the entire budget. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1109,8 +1109,6 @@ static void bgmac_chip_reset(struct bgma + bgmac_phy_init(bgmac); + + netdev_reset_queue(bgmac->net_dev); +- +- bgmac->int_status = 0; + } + + static void bgmac_chip_intrs_on(struct bgmac *bgmac) +@@ -1225,14 +1223,13 @@ static irqreturn_t bgmac_interrupt(int i + if (!int_status) + return IRQ_NONE; + +- /* Ack */ +- bgmac_write(bgmac, BGMAC_INT_STATUS, int_status); ++ int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); ++ if (int_status) ++ bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status); + + /* Disable new interrupts until handling existing ones */ + bgmac_chip_intrs_off(bgmac); + +- bgmac->int_status = int_status; +- + napi_schedule(&bgmac->napi); + + return IRQ_HANDLED; +@@ -1241,25 +1238,17 @@ static irqreturn_t bgmac_interrupt(int i + static int bgmac_poll(struct napi_struct *napi, int weight) + { + struct bgmac *bgmac = container_of(napi, struct bgmac, napi); +- struct bgmac_dma_ring *ring; + int handled = 0; + +- if (bgmac->int_status & BGMAC_IS_TX0) { +- ring = &bgmac->tx_ring[0]; +- bgmac_dma_tx_free(bgmac, ring); +- bgmac->int_status &= ~BGMAC_IS_TX0; +- } ++ /* Ack */ ++ bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); + +- if (bgmac->int_status & BGMAC_IS_RX) { +- ring = &bgmac->rx_ring[0]; +- handled += bgmac_dma_rx_read(bgmac, ring, weight); +- bgmac->int_status &= ~BGMAC_IS_RX; +- } ++ bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); ++ handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); + +- if (bgmac->int_status) { +- bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status); +- bgmac->int_status = 0; +- } ++ /* Poll again if more events arrived in the meantime */ ++ if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) ++ return handled; + + if (handled < weight) { + napi_complete(napi); +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -452,7 +452,6 @@ struct bgmac { + + /* Int */ + u32 int_mask; +- u32 int_status; + + /* Current MAC state */ + int mac_speed; diff --git a/target/linux/generic/patches-3.18/077-06-bgmac-set-received-skb-headroom-to-NET_SKB_PAD.patch b/target/linux/generic/patches-3.18/077-06-bgmac-set-received-skb-headroom-to-NET_SKB_PAD.patch new file mode 100644 index 0000000..2c490ef --- /dev/null +++ b/target/linux/generic/patches-3.18/077-06-bgmac-set-received-skb-headroom-to-NET_SKB_PAD.patch @@ -0,0 +1,66 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 10:13:28 +0200 +Subject: [PATCH] bgmac: set received skb headroom to NET_SKB_PAD + +A packet buffer offset of 30 bytes is inefficient, because the first 2 +bytes end up in a different cacheline. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -346,13 +346,13 @@ static int bgmac_dma_rx_skb_for_slot(str + return -ENOMEM; + + /* Poison - if everything goes fine, hardware will overwrite it */ +- rx = buf; ++ rx = buf + BGMAC_RX_BUF_OFFSET; + rx->len = cpu_to_le16(0xdead); + rx->flags = cpu_to_le16(0xbeef); + + /* Map skb for the DMA */ +- dma_addr = dma_map_single(dma_dev, buf, BGMAC_RX_BUF_SIZE, +- DMA_FROM_DEVICE); ++ dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, ++ BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(dma_dev, dma_addr)) { + bgmac_err(bgmac, "DMA mapping error\n"); + put_page(virt_to_head_page(buf)); +@@ -403,7 +403,7 @@ static int bgmac_dma_rx_read(struct bgma + while (ring->start != ring->end) { + struct device *dma_dev = bgmac->core->dma_dev; + struct bgmac_slot_info *slot = &ring->slots[ring->start]; +- struct bgmac_rx_header *rx = slot->buf; ++ struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; + struct sk_buff *skb; + void *buf = slot->buf; + u16 len, flags; +@@ -454,8 +454,10 @@ static int bgmac_dma_rx_read(struct bgma + BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); + + skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); +- skb_put(skb, BGMAC_RX_FRAME_OFFSET + len); +- skb_pull(skb, BGMAC_RX_FRAME_OFFSET); ++ skb_put(skb, BGMAC_RX_FRAME_OFFSET + ++ BGMAC_RX_BUF_OFFSET + len); ++ skb_pull(skb, BGMAC_RX_FRAME_OFFSET + ++ BGMAC_RX_BUF_OFFSET); + + skb_checksum_none_assert(skb); + skb->protocol = eth_type_trans(skb, bgmac->net_dev); +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -360,9 +360,11 @@ + + #define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */ + #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ ++#define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ ++ BGMAC_RX_FRAME_OFFSET) + #define BGMAC_RX_MAX_FRAME_SIZE 1536 /* Copied from b44/tg3 */ + #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) +-#define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE) + \ ++#define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) + + #define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */ diff --git a/target/linux/generic/patches-3.18/077-07-bgmac-simplify-rx-DMA-error-handling.patch b/target/linux/generic/patches-3.18/077-07-bgmac-simplify-rx-DMA-error-handling.patch new file mode 100644 index 0000000..2ca9d10 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-07-bgmac-simplify-rx-DMA-error-handling.patch @@ -0,0 +1,130 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 22:23:07 +0200 +Subject: [PATCH] bgmac: simplify/optimize rx DMA error handling + +Allocate a new buffer before processing the completed one. If allocation +fails, reuse the old buffer. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -386,6 +386,19 @@ static void bgmac_dma_rx_setup_desc(stru + dma_desc->ctl1 = cpu_to_le32(ctl1); + } + ++static void bgmac_dma_rx_poison_buf(struct device *dma_dev, ++ struct bgmac_slot_info *slot) ++{ ++ struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; ++ ++ dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++ rx->len = cpu_to_le16(0xdead); ++ rx->flags = cpu_to_le16(0xbeef); ++ dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++} ++ + static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, + int weight) + { +@@ -406,53 +419,35 @@ static int bgmac_dma_rx_read(struct bgma + struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; + struct sk_buff *skb; + void *buf = slot->buf; ++ dma_addr_t dma_addr = slot->dma_addr; + u16 len, flags; + +- /* Unmap buffer to make it accessible to the CPU */ +- dma_sync_single_for_cpu(dma_dev, slot->dma_addr, +- BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); +- +- /* Get info from the header */ +- len = le16_to_cpu(rx->len); +- flags = le16_to_cpu(rx->flags); +- + do { +- dma_addr_t old_dma_addr = slot->dma_addr; +- int err; ++ /* Prepare new skb as replacement */ ++ if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { ++ bgmac_dma_rx_poison_buf(dma_dev, slot); ++ break; ++ } ++ ++ /* Unmap buffer to make it accessible to the CPU */ ++ dma_unmap_single(dma_dev, dma_addr, ++ BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); ++ ++ /* Get info from the header */ ++ len = le16_to_cpu(rx->len); ++ flags = le16_to_cpu(rx->flags); + + /* Check for poison and drop or pass the packet */ + if (len == 0xdead && flags == 0xbeef) { + bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", + ring->start); +- dma_sync_single_for_device(dma_dev, +- slot->dma_addr, +- BGMAC_RX_BUF_SIZE, +- DMA_FROM_DEVICE); ++ put_page(virt_to_head_page(buf)); + break; + } + + /* Omit CRC. */ + len -= ETH_FCS_LEN; + +- /* Prepare new skb as replacement */ +- err = bgmac_dma_rx_skb_for_slot(bgmac, slot); +- if (err) { +- /* Poison the old skb */ +- rx->len = cpu_to_le16(0xdead); +- rx->flags = cpu_to_le16(0xbeef); +- +- dma_sync_single_for_device(dma_dev, +- slot->dma_addr, +- BGMAC_RX_BUF_SIZE, +- DMA_FROM_DEVICE); +- break; +- } +- bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); +- +- /* Unmap old skb, we'll pass it to the netfif */ +- dma_unmap_single(dma_dev, old_dma_addr, +- BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); +- + skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); + skb_put(skb, BGMAC_RX_FRAME_OFFSET + + BGMAC_RX_BUF_OFFSET + len); +@@ -465,6 +460,8 @@ static int bgmac_dma_rx_read(struct bgma + handled++; + } while (0); + ++ bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); ++ + if (++ring->start >= BGMAC_RX_RING_SLOTS) + ring->start = 0; + +@@ -532,14 +529,14 @@ static void bgmac_dma_rx_ring_free(struc + + for (i = 0; i < ring->num_slots; i++) { + slot = &ring->slots[i]; +- if (!slot->buf) ++ if (!slot->dma_addr) + continue; + +- if (slot->dma_addr) +- dma_unmap_single(dma_dev, slot->dma_addr, +- BGMAC_RX_BUF_SIZE, +- DMA_FROM_DEVICE); ++ dma_unmap_single(dma_dev, slot->dma_addr, ++ BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); + put_page(virt_to_head_page(slot->buf)); ++ slot->dma_addr = 0; + } + } + diff --git a/target/linux/generic/patches-3.18/077-08-bgmac-add-check-for-oversized-packets.patch b/target/linux/generic/patches-3.18/077-08-bgmac-add-check-for-oversized-packets.patch new file mode 100644 index 0000000..705aa2d --- /dev/null +++ b/target/linux/generic/patches-3.18/077-08-bgmac-add-check-for-oversized-packets.patch @@ -0,0 +1,27 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 22:28:20 +0200 +Subject: [PATCH] bgmac: add check for oversized packets + +In very rare cases, the MAC can catch an internal buffer that is bigger +than it's supposed to be. Instead of crashing the kernel, simply pass +the buffer back to the hardware + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -445,6 +445,13 @@ static int bgmac_dma_rx_read(struct bgma + break; + } + ++ if (len > BGMAC_RX_ALLOC_SIZE) { ++ bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n", ++ ring->start); ++ put_page(virt_to_head_page(buf)); ++ break; ++ } ++ + /* Omit CRC. */ + len -= ETH_FCS_LEN; + diff --git a/target/linux/generic/patches-3.18/077-09-bgmac-increase-rx-ring-size-from-511-to-512.patch b/target/linux/generic/patches-3.18/077-09-bgmac-increase-rx-ring-size-from-511-to-512.patch new file mode 100644 index 0000000..4888cc3 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-09-bgmac-increase-rx-ring-size-from-511-to-512.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 22:36:16 +0200 +Subject: [PATCH] bgmac: increase rx ring size from 511 to 512 + +Limiting it to 511 looks like a failed attempt at leaving one descriptor +empty to allow the hardware to stop processing a buffer that has not +been prepared yet. However, this doesn't work because this affects the +total ring size as well + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -356,7 +356,7 @@ + #define BGMAC_MAX_RX_RINGS 1 + + #define BGMAC_TX_RING_SLOTS 128 +-#define BGMAC_RX_RING_SLOTS 512 - 1 /* Why -1? Well, Broadcom does that... */ ++#define BGMAC_RX_RING_SLOTS 512 + + #define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */ + #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ diff --git a/target/linux/generic/patches-3.18/077-10-bgmac-simplify-dma-init-cleanup.patch b/target/linux/generic/patches-3.18/077-10-bgmac-simplify-dma-init-cleanup.patch new file mode 100644 index 0000000..f8d7921 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-10-bgmac-simplify-dma-init-cleanup.patch @@ -0,0 +1,184 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 23:19:32 +0200 +Subject: [PATCH] bgmac: simplify dma init/cleanup + +Instead of allocating buffers at device init time and initializing +descriptors at device open, do both at the same time (during open). +Free all buffers when closing the device. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -562,18 +562,26 @@ static void bgmac_dma_ring_desc_free(str + ring->dma_base); + } + +-static void bgmac_dma_free(struct bgmac *bgmac) ++static void bgmac_dma_cleanup(struct bgmac *bgmac) + { + int i; + +- for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) + bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); +- bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); +- } +- for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { ++ ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) + bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); ++} ++ ++static void bgmac_dma_free(struct bgmac *bgmac) ++{ ++ int i; ++ ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); ++ ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) + bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); +- } + } + + static int bgmac_dma_alloc(struct bgmac *bgmac) +@@ -621,8 +629,6 @@ static int bgmac_dma_alloc(struct bgmac + } + + for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { +- int j; +- + ring = &bgmac->rx_ring[i]; + ring->num_slots = BGMAC_RX_RING_SLOTS; + ring->mmio_base = ring_base[i]; +@@ -645,15 +651,6 @@ static int bgmac_dma_alloc(struct bgmac + ring->index_base = lower_32_bits(ring->dma_base); + else + ring->index_base = 0; +- +- /* Alloc RX slots */ +- for (j = 0; j < ring->num_slots; j++) { +- err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); +- if (err) { +- bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n"); +- goto err_dma_free; +- } +- } + } + + return 0; +@@ -663,10 +660,10 @@ err_dma_free: + return -ENOMEM; + } + +-static void bgmac_dma_init(struct bgmac *bgmac) ++static int bgmac_dma_init(struct bgmac *bgmac) + { + struct bgmac_dma_ring *ring; +- int i; ++ int i, err; + + for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { + ring = &bgmac->tx_ring[i]; +@@ -698,8 +695,13 @@ static void bgmac_dma_init(struct bgmac + if (ring->unaligned) + bgmac_dma_rx_enable(bgmac, ring); + +- for (j = 0; j < ring->num_slots; j++) ++ for (j = 0; j < ring->num_slots; j++) { ++ err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); ++ if (err) ++ goto error; ++ + bgmac_dma_rx_setup_desc(bgmac, ring, j); ++ } + + bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, + ring->index_base + +@@ -708,6 +710,12 @@ static void bgmac_dma_init(struct bgmac + ring->start = 0; + ring->end = 0; + } ++ ++ return 0; ++ ++error: ++ bgmac_dma_cleanup(bgmac); ++ return err; + } + + /************************************************** +@@ -1183,11 +1191,8 @@ static void bgmac_enable(struct bgmac *b + } + + /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ +-static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) ++static void bgmac_chip_init(struct bgmac *bgmac) + { +- struct bgmac_dma_ring *ring; +- int i; +- + /* 1 interrupt per received frame */ + bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); + +@@ -1205,16 +1210,7 @@ static void bgmac_chip_init(struct bgmac + + bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); + +- if (full_init) { +- bgmac_dma_init(bgmac); +- if (1) /* FIXME: is there any case we don't want IRQs? */ +- bgmac_chip_intrs_on(bgmac); +- } else { +- for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { +- ring = &bgmac->rx_ring[i]; +- bgmac_dma_rx_enable(bgmac, ring); +- } +- } ++ bgmac_chip_intrs_on(bgmac); + + bgmac_enable(bgmac); + } +@@ -1274,23 +1270,27 @@ static int bgmac_open(struct net_device + int err = 0; + + bgmac_chip_reset(bgmac); ++ ++ err = bgmac_dma_init(bgmac); ++ if (err) ++ return err; ++ + /* Specs say about reclaiming rings here, but we do that in DMA init */ +- bgmac_chip_init(bgmac, true); ++ bgmac_chip_init(bgmac); + + err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, + KBUILD_MODNAME, net_dev); + if (err < 0) { + bgmac_err(bgmac, "IRQ request error: %d!\n", err); +- goto err_out; ++ bgmac_dma_cleanup(bgmac); ++ return err; + } + napi_enable(&bgmac->napi); + + phy_start(bgmac->phy_dev); + + netif_carrier_on(net_dev); +- +-err_out: +- return err; ++ return 0; + } + + static int bgmac_stop(struct net_device *net_dev) +@@ -1306,6 +1306,7 @@ static int bgmac_stop(struct net_device + free_irq(bgmac->core->irq, net_dev); + + bgmac_chip_reset(bgmac); ++ bgmac_dma_cleanup(bgmac); + + return 0; + } diff --git a/target/linux/generic/patches-3.18/077-11-bgmac-fix-DMA-rx-corruption.patch b/target/linux/generic/patches-3.18/077-11-bgmac-fix-DMA-rx-corruption.patch new file mode 100644 index 0000000..2e670d8 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-11-bgmac-fix-DMA-rx-corruption.patch @@ -0,0 +1,88 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 11:59:47 +0200 +Subject: [PATCH] bgmac: fix DMA rx corruption + +The driver needs to inform the hardware about the first invalid (not yet +filled) rx slot, by writing its DMA descriptor pointer offset to the +BGMAC_DMA_RX_INDEX register. + +This register was set to a value exceeding the rx ring size, effectively +allowing the hardware constant access to the full ring, regardless of +which slots are initialized. + +To fix this issue, always mark the last filled rx slot as invalid. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -366,6 +366,16 @@ static int bgmac_dma_rx_skb_for_slot(str + return 0; + } + ++static void bgmac_dma_rx_update_index(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ wmb(); ++ ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, ++ ring->index_base + ++ ring->end * sizeof(struct bgmac_dma_desc)); ++} ++ + static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, + struct bgmac_dma_ring *ring, int desc_idx) + { +@@ -384,6 +394,8 @@ static void bgmac_dma_rx_setup_desc(stru + dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); + dma_desc->ctl0 = cpu_to_le32(ctl0); + dma_desc->ctl1 = cpu_to_le32(ctl1); ++ ++ ring->end = desc_idx; + } + + static void bgmac_dma_rx_poison_buf(struct device *dma_dev, +@@ -411,9 +423,7 @@ static int bgmac_dma_rx_read(struct bgma + end_slot &= BGMAC_DMA_RX_STATDPTR; + end_slot /= sizeof(struct bgmac_dma_desc); + +- ring->end = end_slot; +- +- while (ring->start != ring->end) { ++ while (ring->start != end_slot) { + struct device *dma_dev = bgmac->core->dma_dev; + struct bgmac_slot_info *slot = &ring->slots[ring->start]; + struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; +@@ -476,6 +486,8 @@ static int bgmac_dma_rx_read(struct bgma + break; + } + ++ bgmac_dma_rx_update_index(bgmac, ring); ++ + return handled; + } + +@@ -695,6 +707,8 @@ static int bgmac_dma_init(struct bgmac * + if (ring->unaligned) + bgmac_dma_rx_enable(bgmac, ring); + ++ ring->start = 0; ++ ring->end = 0; + for (j = 0; j < ring->num_slots; j++) { + err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); + if (err) +@@ -703,12 +717,7 @@ static int bgmac_dma_init(struct bgmac * + bgmac_dma_rx_setup_desc(bgmac, ring, j); + } + +- bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, +- ring->index_base + +- ring->num_slots * sizeof(struct bgmac_dma_desc)); +- +- ring->start = 0; +- ring->end = 0; ++ bgmac_dma_rx_update_index(bgmac, ring); + } + + return 0; diff --git a/target/linux/generic/patches-3.18/077-12-bgmac-drop-ring-num_slots.patch b/target/linux/generic/patches-3.18/077-12-bgmac-drop-ring-num_slots.patch new file mode 100644 index 0000000..4cd2e3f --- /dev/null +++ b/target/linux/generic/patches-3.18/077-12-bgmac-drop-ring-num_slots.patch @@ -0,0 +1,132 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 23:28:38 +0200 +Subject: [PATCH] bgmac: drop ring->num_slots + +The ring size is always known at compile time, so make the code a bit +more efficient + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -123,7 +123,7 @@ bgmac_dma_tx_add_buf(struct bgmac *bgmac + struct bgmac_dma_desc *dma_desc; + u32 ctl1; + +- if (i == ring->num_slots - 1) ++ if (i == BGMAC_TX_RING_SLOTS - 1) + ctl0 |= BGMAC_DESC_CTL0_EOT; + + ctl1 = len & BGMAC_DESC_CTL1_LEN; +@@ -382,7 +382,7 @@ static void bgmac_dma_rx_setup_desc(stru + struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; + u32 ctl0 = 0, ctl1 = 0; + +- if (desc_idx == ring->num_slots - 1) ++ if (desc_idx == BGMAC_RX_RING_SLOTS - 1) + ctl0 |= BGMAC_DESC_CTL0_EOT; + ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; + /* Is there any BGMAC device that requires extension? */ +@@ -521,7 +521,7 @@ static void bgmac_dma_tx_ring_free(struc + struct bgmac_slot_info *slot; + int i; + +- for (i = 0; i < ring->num_slots; i++) { ++ for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) { + int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; + + slot = &ring->slots[i]; +@@ -546,7 +546,7 @@ static void bgmac_dma_rx_ring_free(struc + struct bgmac_slot_info *slot; + int i; + +- for (i = 0; i < ring->num_slots; i++) { ++ for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) { + slot = &ring->slots[i]; + if (!slot->dma_addr) + continue; +@@ -560,7 +560,8 @@ static void bgmac_dma_rx_ring_free(struc + } + + static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, +- struct bgmac_dma_ring *ring) ++ struct bgmac_dma_ring *ring, ++ int num_slots) + { + struct device *dma_dev = bgmac->core->dma_dev; + int size; +@@ -569,7 +570,7 @@ static void bgmac_dma_ring_desc_free(str + return; + + /* Free ring of descriptors */ +- size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ size = num_slots * sizeof(struct bgmac_dma_desc); + dma_free_coherent(dma_dev, size, ring->cpu_base, + ring->dma_base); + } +@@ -590,10 +591,12 @@ static void bgmac_dma_free(struct bgmac + int i; + + for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) +- bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i], ++ BGMAC_TX_RING_SLOTS); + + for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) +- bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i], ++ BGMAC_RX_RING_SLOTS); + } + + static int bgmac_dma_alloc(struct bgmac *bgmac) +@@ -616,11 +619,10 @@ static int bgmac_dma_alloc(struct bgmac + + for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { + ring = &bgmac->tx_ring[i]; +- ring->num_slots = BGMAC_TX_RING_SLOTS; + ring->mmio_base = ring_base[i]; + + /* Alloc ring of descriptors */ +- size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc); + ring->cpu_base = dma_zalloc_coherent(dma_dev, size, + &ring->dma_base, + GFP_KERNEL); +@@ -642,11 +644,10 @@ static int bgmac_dma_alloc(struct bgmac + + for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { + ring = &bgmac->rx_ring[i]; +- ring->num_slots = BGMAC_RX_RING_SLOTS; + ring->mmio_base = ring_base[i]; + + /* Alloc ring of descriptors */ +- size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc); + ring->cpu_base = dma_zalloc_coherent(dma_dev, size, + &ring->dma_base, + GFP_KERNEL); +@@ -709,7 +710,7 @@ static int bgmac_dma_init(struct bgmac * + + ring->start = 0; + ring->end = 0; +- for (j = 0; j < ring->num_slots; j++) { ++ for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) { + err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); + if (err) + goto error; +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -419,11 +419,10 @@ struct bgmac_dma_ring { + u32 start; + u32 end; + +- u16 num_slots; +- u16 mmio_base; + struct bgmac_dma_desc *cpu_base; + dma_addr_t dma_base; + u32 index_base; /* Used for unaligned rings only, otherwise 0 */ ++ u16 mmio_base; + bool unaligned; + + struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS]; diff --git a/target/linux/generic/patches-3.18/077-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch b/target/linux/generic/patches-3.18/077-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch new file mode 100644 index 0000000..a3d9fd6 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch @@ -0,0 +1,24 @@ +From: Felix Fietkau +Date: Mon, 13 Apr 2015 15:54:04 +0200 +Subject: [PATCH] bgmac: fix MAC soft-reset bit for corerev > 4 + +Only core revisions older than 4 use BGMAC_CMDCFG_SR_REV0 + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -198,9 +198,9 @@ + #define BGMAC_CMDCFG_TAI 0x00000200 + #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ + #define BGMAC_CMDCFG_HD_SHIFT 10 +-#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */ +-#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */ +-#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) ++#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */ ++#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */ ++#define BGMAC_CMDCFG_SR(rev) ((rev >= 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) + #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ + #define BGMAC_CMDCFG_AE 0x00400000 + #define BGMAC_CMDCFG_CFE 0x00800000 diff --git a/target/linux/generic/patches-3.18/077-14-bgmac-reset-all-4-GMAC-cores-on-init.patch b/target/linux/generic/patches-3.18/077-14-bgmac-reset-all-4-GMAC-cores-on-init.patch new file mode 100644 index 0000000..2a913a6 --- /dev/null +++ b/target/linux/generic/patches-3.18/077-14-bgmac-reset-all-4-GMAC-cores-on-init.patch @@ -0,0 +1,28 @@ +From: Felix Fietkau +Date: Mon, 13 Apr 2015 15:56:26 +0200 +Subject: [PATCH] bgmac: reset all 4 GMAC cores on init + +On a BCM4709 based device, I found that GMAC cores may be enabled at +probe time, but only become usable after a full reset. +Disable cores before re-enabling them to ensure that they are properly +reset. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1623,8 +1623,11 @@ static int bgmac_probe(struct bcma_devic + ns_core = bcma_find_core_unit(core->bus, + BCMA_CORE_MAC_GBIT, + ns_gmac); +- if (ns_core && !bcma_core_is_enabled(ns_core)) +- bcma_core_enable(ns_core, 0); ++ if (!ns_core) ++ continue; ++ ++ bcma_core_disable(ns_core, 0); ++ bcma_core_enable(ns_core, 0); + } + } + diff --git a/target/linux/generic/patches-3.18/080-00-fib_trie-Fix-proc-net-fib_trie-when-CONFIG_IP_MULTIP.patch b/target/linux/generic/patches-3.18/080-00-fib_trie-Fix-proc-net-fib_trie-when-CONFIG_IP_MULTIP.patch new file mode 100644 index 0000000..5d99367 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-00-fib_trie-Fix-proc-net-fib_trie-when-CONFIG_IP_MULTIP.patch @@ -0,0 +1,46 @@ +From: Alexander Duyck +Date: Tue, 2 Dec 2014 10:58:21 -0800 +Subject: [PATCH] fib_trie: Fix /proc/net/fib_trie when + CONFIG_IP_MULTIPLE_TABLES is not defined + +In recent testing I had disabled CONFIG_IP_MULTIPLE_TABLES and as a result +when I ran "cat /proc/net/fib_trie" the main trie was displayed multiple +times. I found that the problem line of code was in the function +fib_trie_seq_next. Specifically the line below caused the indexes to go in +the opposite direction of our traversal: + + h = tb->tb_id & (FIB_TABLE_HASHSZ - 1); + +This issue was that the RT tables are defined such that RT_TABLE_LOCAL is ID +255, while it is located at TABLE_LOCAL_INDEX of 0, and RT_TABLE_MAIN is 254 +with a TABLE_MAIN_INDEX of 1. This means that the above line will return 1 +for the local table and 0 for main. The result is that fib_trie_seq_next +will return NULL at the end of the local table, fib_trie_seq_start will +return the start of the main table, and then fib_trie_seq_next will loop on +main forever as h will always return 0. + +The fix for this is to reverse the ordering of the two tables. It has the +advantage of making it so that the tables now print in the same order +regardless of if multiple tables are enabled or not. In order to make the +definition consistent with the multiple tables case I simply masked the to +RT_TABLE_XXX values by (FIB_TABLE_HASHSZ - 1). This way the two table +layouts should always stay consistent. + +Fixes: 93456b6 ("[IPV4]: Unify access to the routing tables") +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/include/net/ip_fib.h ++++ b/include/net/ip_fib.h +@@ -201,8 +201,8 @@ void fib_free_table(struct fib_table *tb + + #ifndef CONFIG_IP_MULTIPLE_TABLES + +-#define TABLE_LOCAL_INDEX 0 +-#define TABLE_MAIN_INDEX 1 ++#define TABLE_LOCAL_INDEX (RT_TABLE_LOCAL & (FIB_TABLE_HASHSZ - 1)) ++#define TABLE_MAIN_INDEX (RT_TABLE_MAIN & (FIB_TABLE_HASHSZ - 1)) + + static inline struct fib_table *fib_get_table(struct net *net, u32 id) + { diff --git a/target/linux/generic/patches-3.18/080-01-fib_trie-Fix-trie-balancing-issue-if-new-node-pushes.patch b/target/linux/generic/patches-3.18/080-01-fib_trie-Fix-trie-balancing-issue-if-new-node-pushes.patch new file mode 100644 index 0000000..4e09f8a --- /dev/null +++ b/target/linux/generic/patches-3.18/080-01-fib_trie-Fix-trie-balancing-issue-if-new-node-pushes.patch @@ -0,0 +1,72 @@ +From: Alexander Duyck +Date: Wed, 10 Dec 2014 21:49:22 -0800 +Subject: [PATCH] fib_trie: Fix trie balancing issue if new node pushes down + existing node + +This patch addresses an issue with the level compression of the fib_trie. +Specifically in the case of adding a new leaf that triggers a new node to +be added that takes the place of the old node. The result is a trie where +the 1 child tnode is on one side and one leaf is on the other which gives +you a very deep trie. Below is the script I used to generate a trie on +dummy0 with a 10.X.X.X family of addresses. + + ip link add type dummy + ipval=184549374 + bit=2 + for i in `seq 1 23` + do + ifconfig dummy0:$bit $ipval/8 + ipval=`expr $ipval - $bit` + bit=`expr $bit \* 2` + done + cat /proc/net/fib_triestat + +Running the script before the patch: + + Local: + Aver depth: 10.82 + Max depth: 23 + Leaves: 29 + Prefixes: 30 + Internal nodes: 27 + 1: 26 2: 1 + Pointers: 56 + Null ptrs: 1 + Total size: 5 kB + +After applying the patch and repeating: + + Local: + Aver depth: 4.72 + Max depth: 9 + Leaves: 29 + Prefixes: 30 + Internal nodes: 12 + 1: 3 2: 2 3: 7 + Pointers: 70 + Null ptrs: 30 + Total size: 4 kB + +What this fix does is start the rebalance at the newly created tnode +instead of at the parent tnode. This way if there is a gap between the +parent and the new node it doesn't prevent the new tnode from being +coalesced with any pre-existing nodes that may have been pushed into one +of the new nodes child branches. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -1143,8 +1143,9 @@ static struct list_head *fib_insert_node + put_child(tp, cindex, (struct rt_trie_node *)tn); + } else { + rcu_assign_pointer(t->trie, (struct rt_trie_node *)tn); +- tp = tn; + } ++ ++ tp = tn; + } + + if (tp && tp->pos + tp->bits > 32) diff --git a/target/linux/generic/patches-3.18/080-02-fib_trie-Update-usage-stats-to-be-percpu-instead-of-.patch b/target/linux/generic/patches-3.18/080-02-fib_trie-Update-usage-stats-to-be-percpu-instead-of-.patch new file mode 100644 index 0000000..2e6deb5 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-02-fib_trie-Update-usage-stats-to-be-percpu-instead-of-.patch @@ -0,0 +1,200 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:55:29 -0800 +Subject: [PATCH] fib_trie: Update usage stats to be percpu instead of + global variables + +The trie usage stats were currently being shared by all threads that were +calling fib_table_lookup. As a result when multiple threads were +performing lookups simultaneously the trie would begin to cache bounce +between those threads. + +In order to prevent this I have updated the usage stats to use a set of +percpu variables. By doing this we should be able to avoid the cache +bouncing and still make use of these stats. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_frontend.c ++++ b/net/ipv4/fib_frontend.c +@@ -67,7 +67,7 @@ static int __net_init fib4_rules_init(st + return 0; + + fail: +- kfree(local_table); ++ fib_free_table(local_table); + return -ENOMEM; + } + #else +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -153,7 +153,7 @@ struct trie_stat { + struct trie { + struct rt_trie_node __rcu *trie; + #ifdef CONFIG_IP_FIB_TRIE_STATS +- struct trie_use_stats stats; ++ struct trie_use_stats __percpu *stats; + #endif + }; + +@@ -631,7 +631,7 @@ static struct rt_trie_node *resize(struc + if (IS_ERR(tn)) { + tn = old_tn; + #ifdef CONFIG_IP_FIB_TRIE_STATS +- t->stats.resize_node_skipped++; ++ this_cpu_inc(t->stats->resize_node_skipped); + #endif + break; + } +@@ -658,7 +658,7 @@ static struct rt_trie_node *resize(struc + if (IS_ERR(tn)) { + tn = old_tn; + #ifdef CONFIG_IP_FIB_TRIE_STATS +- t->stats.resize_node_skipped++; ++ this_cpu_inc(t->stats->resize_node_skipped); + #endif + break; + } +@@ -1357,7 +1357,7 @@ static int check_leaf(struct fib_table * + err = fib_props[fa->fa_type].error; + if (err) { + #ifdef CONFIG_IP_FIB_TRIE_STATS +- t->stats.semantic_match_passed++; ++ this_cpu_inc(t->stats->semantic_match_passed); + #endif + return err; + } +@@ -1372,7 +1372,7 @@ static int check_leaf(struct fib_table * + continue; + + #ifdef CONFIG_IP_FIB_TRIE_STATS +- t->stats.semantic_match_passed++; ++ this_cpu_inc(t->stats->semantic_match_passed); + #endif + res->prefixlen = li->plen; + res->nh_sel = nhsel; +@@ -1388,7 +1388,7 @@ static int check_leaf(struct fib_table * + } + + #ifdef CONFIG_IP_FIB_TRIE_STATS +- t->stats.semantic_match_miss++; ++ this_cpu_inc(t->stats->semantic_match_miss); + #endif + } + +@@ -1399,6 +1399,9 @@ int fib_table_lookup(struct fib_table *t + struct fib_result *res, int fib_flags) + { + struct trie *t = (struct trie *) tb->tb_data; ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ struct trie_use_stats __percpu *stats = t->stats; ++#endif + int ret; + struct rt_trie_node *n; + struct tnode *pn; +@@ -1417,7 +1420,7 @@ int fib_table_lookup(struct fib_table *t + goto failed; + + #ifdef CONFIG_IP_FIB_TRIE_STATS +- t->stats.gets++; ++ this_cpu_inc(stats->gets); + #endif + + /* Just a leaf? */ +@@ -1441,7 +1444,7 @@ int fib_table_lookup(struct fib_table *t + + if (n == NULL) { + #ifdef CONFIG_IP_FIB_TRIE_STATS +- t->stats.null_node_hit++; ++ this_cpu_inc(stats->null_node_hit); + #endif + goto backtrace; + } +@@ -1576,7 +1579,7 @@ backtrace: + chopped_off = 0; + + #ifdef CONFIG_IP_FIB_TRIE_STATS +- t->stats.backtrack++; ++ this_cpu_inc(stats->backtrack); + #endif + goto backtrace; + } +@@ -1830,6 +1833,11 @@ int fib_table_flush(struct fib_table *tb + + void fib_free_table(struct fib_table *tb) + { ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ struct trie *t = (struct trie *)tb->tb_data; ++ ++ free_percpu(t->stats); ++#endif /* CONFIG_IP_FIB_TRIE_STATS */ + kfree(tb); + } + +@@ -1973,7 +1981,14 @@ struct fib_table *fib_trie_table(u32 id) + tb->tb_num_default = 0; + + t = (struct trie *) tb->tb_data; +- memset(t, 0, sizeof(*t)); ++ RCU_INIT_POINTER(t->trie, NULL); ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ t->stats = alloc_percpu(struct trie_use_stats); ++ if (!t->stats) { ++ kfree(tb); ++ tb = NULL; ++ } ++#endif + + return tb; + } +@@ -2139,18 +2154,31 @@ static void trie_show_stats(struct seq_f + + #ifdef CONFIG_IP_FIB_TRIE_STATS + static void trie_show_usage(struct seq_file *seq, +- const struct trie_use_stats *stats) ++ const struct trie_use_stats __percpu *stats) + { ++ struct trie_use_stats s = { 0 }; ++ int cpu; ++ ++ /* loop through all of the CPUs and gather up the stats */ ++ for_each_possible_cpu(cpu) { ++ const struct trie_use_stats *pcpu = per_cpu_ptr(stats, cpu); ++ ++ s.gets += pcpu->gets; ++ s.backtrack += pcpu->backtrack; ++ s.semantic_match_passed += pcpu->semantic_match_passed; ++ s.semantic_match_miss += pcpu->semantic_match_miss; ++ s.null_node_hit += pcpu->null_node_hit; ++ s.resize_node_skipped += pcpu->resize_node_skipped; ++ } ++ + seq_printf(seq, "\nCounters:\n---------\n"); +- seq_printf(seq, "gets = %u\n", stats->gets); +- seq_printf(seq, "backtracks = %u\n", stats->backtrack); ++ seq_printf(seq, "gets = %u\n", s.gets); ++ seq_printf(seq, "backtracks = %u\n", s.backtrack); + seq_printf(seq, "semantic match passed = %u\n", +- stats->semantic_match_passed); +- seq_printf(seq, "semantic match miss = %u\n", +- stats->semantic_match_miss); +- seq_printf(seq, "null node hit= %u\n", stats->null_node_hit); +- seq_printf(seq, "skipped node resize = %u\n\n", +- stats->resize_node_skipped); ++ s.semantic_match_passed); ++ seq_printf(seq, "semantic match miss = %u\n", s.semantic_match_miss); ++ seq_printf(seq, "null node hit= %u\n", s.null_node_hit); ++ seq_printf(seq, "skipped node resize = %u\n\n", s.resize_node_skipped); + } + #endif /* CONFIG_IP_FIB_TRIE_STATS */ + +@@ -2191,7 +2219,7 @@ static int fib_triestat_seq_show(struct + trie_collect_stats(t, &stat); + trie_show_stats(seq, &stat); + #ifdef CONFIG_IP_FIB_TRIE_STATS +- trie_show_usage(seq, &t->stats); ++ trie_show_usage(seq, t->stats); + #endif + } + } diff --git a/target/linux/generic/patches-3.18/080-03-fib_trie-Make-leaf-and-tnode-more-uniform.patch b/target/linux/generic/patches-3.18/080-03-fib_trie-Make-leaf-and-tnode-more-uniform.patch new file mode 100644 index 0000000..4c727cd --- /dev/null +++ b/target/linux/generic/patches-3.18/080-03-fib_trie-Make-leaf-and-tnode-more-uniform.patch @@ -0,0 +1,421 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:55:35 -0800 +Subject: [PATCH] fib_trie: Make leaf and tnode more uniform + +This change makes some fundamental changes to the way leaves and tnodes are +constructed. The big differences are: +1. Leaves now populate pos and bits indicating their full key size. +2. Trie nodes now mask out their lower bits to be consistent with the leaf +3. Both structures have been reordered so that rt_trie_node now consisists + of a much larger region including the pos, bits, and rcu portions of + the tnode structure. + +On 32b systems this will result in the leaf being 4B larger as the pos and +bits values were added to a hole created by the key as it was only 4B in +length. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -87,24 +87,38 @@ + + typedef unsigned int t_key; + +-#define T_TNODE 0 +-#define T_LEAF 1 +-#define NODE_TYPE_MASK 0x1UL +-#define NODE_TYPE(node) ((node)->parent & NODE_TYPE_MASK) ++#define IS_TNODE(n) ((n)->bits) ++#define IS_LEAF(n) (!(n)->bits) + +-#define IS_TNODE(n) (!(n->parent & T_LEAF)) +-#define IS_LEAF(n) (n->parent & T_LEAF) ++struct tnode { ++ t_key key; ++ unsigned char bits; /* 2log(KEYLENGTH) bits needed */ ++ unsigned char pos; /* 2log(KEYLENGTH) bits needed */ ++ struct tnode __rcu *parent; ++ union { ++ struct rcu_head rcu; ++ struct tnode *tnode_free; ++ }; ++ unsigned int full_children; /* KEYLENGTH bits needed */ ++ unsigned int empty_children; /* KEYLENGTH bits needed */ ++ struct rt_trie_node __rcu *child[0]; ++}; + + struct rt_trie_node { +- unsigned long parent; + t_key key; ++ unsigned char bits; ++ unsigned char pos; ++ struct tnode __rcu *parent; ++ struct rcu_head rcu; + }; + + struct leaf { +- unsigned long parent; + t_key key; +- struct hlist_head list; ++ unsigned char bits; ++ unsigned char pos; ++ struct tnode __rcu *parent; + struct rcu_head rcu; ++ struct hlist_head list; + }; + + struct leaf_info { +@@ -115,20 +129,6 @@ struct leaf_info { + struct rcu_head rcu; + }; + +-struct tnode { +- unsigned long parent; +- t_key key; +- unsigned char pos; /* 2log(KEYLENGTH) bits needed */ +- unsigned char bits; /* 2log(KEYLENGTH) bits needed */ +- unsigned int full_children; /* KEYLENGTH bits needed */ +- unsigned int empty_children; /* KEYLENGTH bits needed */ +- union { +- struct rcu_head rcu; +- struct tnode *tnode_free; +- }; +- struct rt_trie_node __rcu *child[0]; +-}; +- + #ifdef CONFIG_IP_FIB_TRIE_STATS + struct trie_use_stats { + unsigned int gets; +@@ -176,38 +176,27 @@ static const int sync_pages = 128; + static struct kmem_cache *fn_alias_kmem __read_mostly; + static struct kmem_cache *trie_leaf_kmem __read_mostly; + +-/* +- * caller must hold RTNL +- */ +-static inline struct tnode *node_parent(const struct rt_trie_node *node) +-{ +- unsigned long parent; ++/* caller must hold RTNL */ ++#define node_parent(n) rtnl_dereference((n)->parent) + +- parent = rcu_dereference_index_check(node->parent, lockdep_rtnl_is_held()); ++/* caller must hold RCU read lock or RTNL */ ++#define node_parent_rcu(n) rcu_dereference_rtnl((n)->parent) + +- return (struct tnode *)(parent & ~NODE_TYPE_MASK); +-} +- +-/* +- * caller must hold RCU read lock or RTNL +- */ +-static inline struct tnode *node_parent_rcu(const struct rt_trie_node *node) ++/* wrapper for rcu_assign_pointer */ ++static inline void node_set_parent(struct rt_trie_node *node, struct tnode *ptr) + { +- unsigned long parent; +- +- parent = rcu_dereference_index_check(node->parent, rcu_read_lock_held() || +- lockdep_rtnl_is_held()); +- +- return (struct tnode *)(parent & ~NODE_TYPE_MASK); ++ if (node) ++ rcu_assign_pointer(node->parent, ptr); + } + +-/* Same as rcu_assign_pointer +- * but that macro() assumes that value is a pointer. ++#define NODE_INIT_PARENT(n, p) RCU_INIT_POINTER((n)->parent, p) ++ ++/* This provides us with the number of children in this node, in the case of a ++ * leaf this will return 0 meaning none of the children are accessible. + */ +-static inline void node_set_parent(struct rt_trie_node *node, struct tnode *ptr) ++static inline int tnode_child_length(const struct tnode *tn) + { +- smp_wmb(); +- node->parent = (unsigned long)ptr | NODE_TYPE(node); ++ return (1ul << tn->bits) & ~(1ul); + } + + /* +@@ -215,7 +204,7 @@ static inline void node_set_parent(struc + */ + static inline struct rt_trie_node *tnode_get_child(const struct tnode *tn, unsigned int i) + { +- BUG_ON(i >= 1U << tn->bits); ++ BUG_ON(i >= tnode_child_length(tn)); + + return rtnl_dereference(tn->child[i]); + } +@@ -225,16 +214,11 @@ static inline struct rt_trie_node *tnode + */ + static inline struct rt_trie_node *tnode_get_child_rcu(const struct tnode *tn, unsigned int i) + { +- BUG_ON(i >= 1U << tn->bits); ++ BUG_ON(i >= tnode_child_length(tn)); + + return rcu_dereference_rtnl(tn->child[i]); + } + +-static inline int tnode_child_length(const struct tnode *tn) +-{ +- return 1 << tn->bits; +-} +- + static inline t_key mask_pfx(t_key k, unsigned int l) + { + return (l == 0) ? 0 : k >> (KEYLENGTH-l) << (KEYLENGTH-l); +@@ -336,11 +320,6 @@ static inline int tkey_mismatch(t_key a, + + */ + +-static inline void check_tnode(const struct tnode *tn) +-{ +- WARN_ON(tn && tn->pos+tn->bits > 32); +-} +- + static const int halve_threshold = 25; + static const int inflate_threshold = 50; + static const int halve_threshold_root = 15; +@@ -426,11 +405,20 @@ static void tnode_free_flush(void) + } + } + +-static struct leaf *leaf_new(void) ++static struct leaf *leaf_new(t_key key) + { + struct leaf *l = kmem_cache_alloc(trie_leaf_kmem, GFP_KERNEL); + if (l) { +- l->parent = T_LEAF; ++ l->parent = NULL; ++ /* set key and pos to reflect full key value ++ * any trailing zeros in the key should be ignored ++ * as the nodes are searched ++ */ ++ l->key = key; ++ l->pos = KEYLENGTH; ++ /* set bits to 0 indicating we are not a tnode */ ++ l->bits = 0; ++ + INIT_HLIST_HEAD(&l->list); + } + return l; +@@ -451,12 +439,16 @@ static struct tnode *tnode_new(t_key key + { + size_t sz = sizeof(struct tnode) + (sizeof(struct rt_trie_node *) << bits); + struct tnode *tn = tnode_alloc(sz); ++ unsigned int shift = pos + bits; ++ ++ /* verify bits and pos their msb bits clear and values are valid */ ++ BUG_ON(!bits || (shift > KEYLENGTH)); + + if (tn) { +- tn->parent = T_TNODE; ++ tn->parent = NULL; + tn->pos = pos; + tn->bits = bits; +- tn->key = key; ++ tn->key = mask_pfx(key, pos); + tn->full_children = 0; + tn->empty_children = 1<pos == tn->pos + tn->bits; ++ return n && IS_TNODE(n) && (n->pos == (tn->pos + tn->bits)); + } + + static inline void put_child(struct tnode *tn, int i, +@@ -514,8 +503,7 @@ static void tnode_put_child_reorg(struct + else if (!wasfull && isfull) + tn->full_children++; + +- if (n) +- node_set_parent(n, tn); ++ node_set_parent(n, tn); + + rcu_assign_pointer(tn->child[i], n); + } +@@ -523,7 +511,7 @@ static void tnode_put_child_reorg(struct + #define MAX_WORK 10 + static struct rt_trie_node *resize(struct trie *t, struct tnode *tn) + { +- int i; ++ struct rt_trie_node *n = NULL; + struct tnode *old_tn; + int inflate_threshold_use; + int halve_threshold_use; +@@ -536,12 +524,11 @@ static struct rt_trie_node *resize(struc + tn, inflate_threshold, halve_threshold); + + /* No children */ +- if (tn->empty_children == tnode_child_length(tn)) { +- tnode_free_safe(tn); +- return NULL; +- } ++ if (tn->empty_children > (tnode_child_length(tn) - 1)) ++ goto no_children; ++ + /* One child */ +- if (tn->empty_children == tnode_child_length(tn) - 1) ++ if (tn->empty_children == (tnode_child_length(tn) - 1)) + goto one_child; + /* + * Double as long as the resulting node has a number of +@@ -607,11 +594,9 @@ static struct rt_trie_node *resize(struc + * + */ + +- check_tnode(tn); +- + /* Keep root node larger */ + +- if (!node_parent((struct rt_trie_node *)tn)) { ++ if (!node_parent(tn)) { + inflate_threshold_use = inflate_threshold_root; + halve_threshold_use = halve_threshold_root; + } else { +@@ -637,8 +622,6 @@ static struct rt_trie_node *resize(struc + } + } + +- check_tnode(tn); +- + /* Return if at least one inflate is run */ + if (max_work != MAX_WORK) + return (struct rt_trie_node *) tn; +@@ -666,21 +649,16 @@ static struct rt_trie_node *resize(struc + + + /* Only one child remains */ +- if (tn->empty_children == tnode_child_length(tn) - 1) { ++ if (tn->empty_children == (tnode_child_length(tn) - 1)) { ++ unsigned long i; + one_child: +- for (i = 0; i < tnode_child_length(tn); i++) { +- struct rt_trie_node *n; +- +- n = rtnl_dereference(tn->child[i]); +- if (!n) +- continue; +- +- /* compress one level */ +- +- node_set_parent(n, NULL); +- tnode_free_safe(tn); +- return n; +- } ++ for (i = tnode_child_length(tn); !n && i;) ++ n = tnode_get_child(tn, --i); ++no_children: ++ /* compress one level */ ++ node_set_parent(n, NULL); ++ tnode_free_safe(tn); ++ return n; + } + return (struct rt_trie_node *) tn; + } +@@ -760,8 +738,7 @@ static struct tnode *inflate(struct trie + + /* A leaf or an internal node with skipped bits */ + +- if (IS_LEAF(node) || ((struct tnode *) node)->pos > +- tn->pos + tn->bits - 1) { ++ if (IS_LEAF(node) || (node->pos > (tn->pos + tn->bits - 1))) { + put_child(tn, + tkey_extract_bits(node->key, oldtnode->pos, oldtnode->bits + 1), + node); +@@ -958,11 +935,9 @@ fib_find_node(struct trie *t, u32 key) + pos = 0; + n = rcu_dereference_rtnl(t->trie); + +- while (n != NULL && NODE_TYPE(n) == T_TNODE) { ++ while (n && IS_TNODE(n)) { + tn = (struct tnode *) n; + +- check_tnode(tn); +- + if (tkey_sub_equals(tn->key, pos, tn->pos-pos, key)) { + pos = tn->pos + tn->bits; + n = tnode_get_child_rcu(tn, +@@ -988,7 +963,7 @@ static void trie_rebalance(struct trie * + + key = tn->key; + +- while (tn != NULL && (tp = node_parent((struct rt_trie_node *)tn)) != NULL) { ++ while (tn != NULL && (tp = node_parent(tn)) != NULL) { + cindex = tkey_extract_bits(key, tp->pos, tp->bits); + wasfull = tnode_full(tp, tnode_get_child(tp, cindex)); + tn = (struct tnode *)resize(t, tn); +@@ -996,7 +971,7 @@ static void trie_rebalance(struct trie * + tnode_put_child_reorg(tp, cindex, + (struct rt_trie_node *)tn, wasfull); + +- tp = node_parent((struct rt_trie_node *) tn); ++ tp = node_parent(tn); + if (!tp) + rcu_assign_pointer(t->trie, (struct rt_trie_node *)tn); + +@@ -1048,11 +1023,9 @@ static struct list_head *fib_insert_node + * If it doesn't, we need to replace it with a T_TNODE. + */ + +- while (n != NULL && NODE_TYPE(n) == T_TNODE) { ++ while (n && IS_TNODE(n)) { + tn = (struct tnode *) n; + +- check_tnode(tn); +- + if (tkey_sub_equals(tn->key, pos, tn->pos-pos, key)) { + tp = tn; + pos = tn->pos + tn->bits; +@@ -1087,12 +1060,11 @@ static struct list_head *fib_insert_node + insert_leaf_info(&l->list, li); + goto done; + } +- l = leaf_new(); ++ l = leaf_new(key); + + if (!l) + return NULL; + +- l->key = key; + li = leaf_info_new(plen); + + if (!li) { +@@ -1569,7 +1541,7 @@ backtrace: + if (chopped_off <= pn->bits) { + cindex &= ~(1 << (chopped_off-1)); + } else { +- struct tnode *parent = node_parent_rcu((struct rt_trie_node *) pn); ++ struct tnode *parent = node_parent_rcu(pn); + if (!parent) + goto failed; + +@@ -1597,7 +1569,7 @@ EXPORT_SYMBOL_GPL(fib_table_lookup); + */ + static void trie_leaf_remove(struct trie *t, struct leaf *l) + { +- struct tnode *tp = node_parent((struct rt_trie_node *) l); ++ struct tnode *tp = node_parent(l); + + pr_debug("entering trie_leaf_remove(%p)\n", l); + +@@ -2374,7 +2346,7 @@ static int fib_trie_seq_show(struct seq_ + + if (IS_TNODE(n)) { + struct tnode *tn = (struct tnode *) n; +- __be32 prf = htonl(mask_pfx(tn->key, tn->pos)); ++ __be32 prf = htonl(tn->key); + + seq_indent(seq, iter->depth-1); + seq_printf(seq, " +-- %pI4/%d %d %d %d\n", diff --git a/target/linux/generic/patches-3.18/080-04-fib_trie-Merge-tnode_free-and-leaf_free-into-node_fr.patch b/target/linux/generic/patches-3.18/080-04-fib_trie-Merge-tnode_free-and-leaf_free-into-node_fr.patch new file mode 100644 index 0000000..3f8d030 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-04-fib_trie-Merge-tnode_free-and-leaf_free-into-node_fr.patch @@ -0,0 +1,209 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:55:41 -0800 +Subject: [PATCH] fib_trie: Merge tnode_free and leaf_free into node_free + +Both the leaf and the tnode had an rcu_head in them, but they had them in +slightly different places. Since we now have them in the same spot and +know that any node with bits == 0 is a leaf and the rest are either vmalloc +or kmalloc tnodes depending on the value of bits it makes it easy to combine +the functions and reduce overhead. + +In addition I have taken advantage of the rcu_head pointer to go ahead and +put together a simple linked list instead of using the tnode pointer as +this way we can merge either type of structure for freeing. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -95,15 +95,17 @@ struct tnode { + unsigned char bits; /* 2log(KEYLENGTH) bits needed */ + unsigned char pos; /* 2log(KEYLENGTH) bits needed */ + struct tnode __rcu *parent; +- union { +- struct rcu_head rcu; +- struct tnode *tnode_free; +- }; ++ struct rcu_head rcu; ++ /* everything above this comment must be the same as rt_trie_node */ + unsigned int full_children; /* KEYLENGTH bits needed */ + unsigned int empty_children; /* KEYLENGTH bits needed */ + struct rt_trie_node __rcu *child[0]; + }; + ++/* This struct represents the shared bits between tnode and leaf. If any ++ * ordering is changed here is must also be updated in tnode and leaf as ++ * well. ++ */ + struct rt_trie_node { + t_key key; + unsigned char bits; +@@ -118,6 +120,7 @@ struct leaf { + unsigned char pos; + struct tnode __rcu *parent; + struct rcu_head rcu; ++ /* everything above this comment must be the same as rt_trie_node */ + struct hlist_head list; + }; + +@@ -163,7 +166,7 @@ static struct rt_trie_node *resize(struc + static struct tnode *inflate(struct trie *t, struct tnode *tn); + static struct tnode *halve(struct trie *t, struct tnode *tn); + /* tnodes to free after resize(); protected by RTNL */ +-static struct tnode *tnode_free_head; ++static struct callback_head *tnode_free_head; + static size_t tnode_free_size; + + /* +@@ -336,17 +339,23 @@ static inline void alias_free_mem_rcu(st + call_rcu(&fa->rcu, __alias_free_mem); + } + +-static void __leaf_free_rcu(struct rcu_head *head) +-{ +- struct leaf *l = container_of(head, struct leaf, rcu); +- kmem_cache_free(trie_leaf_kmem, l); +-} ++#define TNODE_KMALLOC_MAX \ ++ ilog2((PAGE_SIZE - sizeof(struct tnode)) / sizeof(struct rt_trie_node *)) + +-static inline void free_leaf(struct leaf *l) ++static void __node_free_rcu(struct rcu_head *head) + { +- call_rcu(&l->rcu, __leaf_free_rcu); ++ struct rt_trie_node *n = container_of(head, struct rt_trie_node, rcu); ++ ++ if (IS_LEAF(n)) ++ kmem_cache_free(trie_leaf_kmem, n); ++ else if (n->bits <= TNODE_KMALLOC_MAX) ++ kfree(n); ++ else ++ vfree(n); + } + ++#define node_free(n) call_rcu(&n->rcu, __node_free_rcu) ++ + static inline void free_leaf_info(struct leaf_info *leaf) + { + kfree_rcu(leaf, rcu); +@@ -360,43 +369,24 @@ static struct tnode *tnode_alloc(size_t + return vzalloc(size); + } + +-static void __tnode_free_rcu(struct rcu_head *head) +-{ +- struct tnode *tn = container_of(head, struct tnode, rcu); +- size_t size = sizeof(struct tnode) + +- (sizeof(struct rt_trie_node *) << tn->bits); +- +- if (size <= PAGE_SIZE) +- kfree(tn); +- else +- vfree(tn); +-} +- +-static inline void tnode_free(struct tnode *tn) +-{ +- if (IS_LEAF(tn)) +- free_leaf((struct leaf *) tn); +- else +- call_rcu(&tn->rcu, __tnode_free_rcu); +-} +- + static void tnode_free_safe(struct tnode *tn) + { + BUG_ON(IS_LEAF(tn)); +- tn->tnode_free = tnode_free_head; +- tnode_free_head = tn; +- tnode_free_size += sizeof(struct tnode) + +- (sizeof(struct rt_trie_node *) << tn->bits); ++ tn->rcu.next = tnode_free_head; ++ tnode_free_head = &tn->rcu; + } + + static void tnode_free_flush(void) + { +- struct tnode *tn; ++ struct callback_head *head; ++ ++ while ((head = tnode_free_head)) { ++ struct tnode *tn = container_of(head, struct tnode, rcu); ++ ++ tnode_free_head = head->next; ++ tnode_free_size += offsetof(struct tnode, child[1 << tn->bits]); + +- while ((tn = tnode_free_head)) { +- tnode_free_head = tn->tnode_free; +- tn->tnode_free = NULL; +- tnode_free(tn); ++ node_free(tn); + } + + if (tnode_free_size >= PAGE_SIZE * sync_pages) { +@@ -437,7 +427,7 @@ static struct leaf_info *leaf_info_new(i + + static struct tnode *tnode_new(t_key key, int pos, int bits) + { +- size_t sz = sizeof(struct tnode) + (sizeof(struct rt_trie_node *) << bits); ++ size_t sz = offsetof(struct tnode, child[1 << bits]); + struct tnode *tn = tnode_alloc(sz); + unsigned int shift = pos + bits; + +@@ -666,15 +656,15 @@ no_children: + + static void tnode_clean_free(struct tnode *tn) + { ++ struct rt_trie_node *tofree; + int i; +- struct tnode *tofree; + + for (i = 0; i < tnode_child_length(tn); i++) { +- tofree = (struct tnode *)rtnl_dereference(tn->child[i]); ++ tofree = rtnl_dereference(tn->child[i]); + if (tofree) +- tnode_free(tofree); ++ node_free(tofree); + } +- tnode_free(tn); ++ node_free(tn); + } + + static struct tnode *inflate(struct trie *t, struct tnode *tn) +@@ -717,7 +707,7 @@ static struct tnode *inflate(struct trie + inode->bits - 1); + + if (!right) { +- tnode_free(left); ++ node_free(left); + goto nomem; + } + +@@ -1068,7 +1058,7 @@ static struct list_head *fib_insert_node + li = leaf_info_new(plen); + + if (!li) { +- free_leaf(l); ++ node_free(l); + return NULL; + } + +@@ -1100,7 +1090,7 @@ static struct list_head *fib_insert_node + + if (!tn) { + free_leaf_info(li); +- free_leaf(l); ++ node_free(l); + return NULL; + } + +@@ -1580,7 +1570,7 @@ static void trie_leaf_remove(struct trie + } else + RCU_INIT_POINTER(t->trie, NULL); + +- free_leaf(l); ++ node_free(l); + } + + /* diff --git a/target/linux/generic/patches-3.18/080-05-fib_trie-Merge-leaf-into-tnode.patch b/target/linux/generic/patches-3.18/080-05-fib_trie-Merge-leaf-into-tnode.patch new file mode 100644 index 0000000..a3393bf --- /dev/null +++ b/target/linux/generic/patches-3.18/080-05-fib_trie-Merge-leaf-into-tnode.patch @@ -0,0 +1,928 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:55:47 -0800 +Subject: [PATCH] fib_trie: Merge leaf into tnode + +This change makes it so that leaf and tnode are the same struct. As a +result there is no need for rt_trie_node anymore since everyting can be +merged into tnode. + +On 32b systems this results in the leaf being 4 bytes larger, however I +don't know if that is really an issue as this and an eariler patch that +added bits & pos have increased the size from 20 to 28. If I am not +mistaken slub/slab allocate on power of 2 sizes so 20 was likely being +rounded up to 32 anyway. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -96,32 +96,16 @@ struct tnode { + unsigned char pos; /* 2log(KEYLENGTH) bits needed */ + struct tnode __rcu *parent; + struct rcu_head rcu; +- /* everything above this comment must be the same as rt_trie_node */ +- unsigned int full_children; /* KEYLENGTH bits needed */ +- unsigned int empty_children; /* KEYLENGTH bits needed */ +- struct rt_trie_node __rcu *child[0]; +-}; +- +-/* This struct represents the shared bits between tnode and leaf. If any +- * ordering is changed here is must also be updated in tnode and leaf as +- * well. +- */ +-struct rt_trie_node { +- t_key key; +- unsigned char bits; +- unsigned char pos; +- struct tnode __rcu *parent; +- struct rcu_head rcu; +-}; +- +-struct leaf { +- t_key key; +- unsigned char bits; +- unsigned char pos; +- struct tnode __rcu *parent; +- struct rcu_head rcu; +- /* everything above this comment must be the same as rt_trie_node */ +- struct hlist_head list; ++ union { ++ /* The fields in this struct are valid if bits > 0 (TNODE) */ ++ struct { ++ unsigned int full_children; /* KEYLENGTH bits needed */ ++ unsigned int empty_children; /* KEYLENGTH bits needed */ ++ struct tnode __rcu *child[0]; ++ }; ++ /* This list pointer if valid if bits == 0 (LEAF) */ ++ struct hlist_head list; ++ }; + }; + + struct leaf_info { +@@ -154,15 +138,15 @@ struct trie_stat { + }; + + struct trie { +- struct rt_trie_node __rcu *trie; ++ struct tnode __rcu *trie; + #ifdef CONFIG_IP_FIB_TRIE_STATS + struct trie_use_stats __percpu *stats; + #endif + }; + +-static void tnode_put_child_reorg(struct tnode *tn, int i, struct rt_trie_node *n, ++static void tnode_put_child_reorg(struct tnode *tn, int i, struct tnode *n, + int wasfull); +-static struct rt_trie_node *resize(struct trie *t, struct tnode *tn); ++static struct tnode *resize(struct trie *t, struct tnode *tn); + static struct tnode *inflate(struct trie *t, struct tnode *tn); + static struct tnode *halve(struct trie *t, struct tnode *tn); + /* tnodes to free after resize(); protected by RTNL */ +@@ -186,10 +170,10 @@ static struct kmem_cache *trie_leaf_kmem + #define node_parent_rcu(n) rcu_dereference_rtnl((n)->parent) + + /* wrapper for rcu_assign_pointer */ +-static inline void node_set_parent(struct rt_trie_node *node, struct tnode *ptr) ++static inline void node_set_parent(struct tnode *n, struct tnode *tp) + { +- if (node) +- rcu_assign_pointer(node->parent, ptr); ++ if (n) ++ rcu_assign_pointer(n->parent, tp); + } + + #define NODE_INIT_PARENT(n, p) RCU_INIT_POINTER((n)->parent, p) +@@ -205,7 +189,7 @@ static inline int tnode_child_length(con + /* + * caller must hold RTNL + */ +-static inline struct rt_trie_node *tnode_get_child(const struct tnode *tn, unsigned int i) ++static inline struct tnode *tnode_get_child(const struct tnode *tn, unsigned int i) + { + BUG_ON(i >= tnode_child_length(tn)); + +@@ -215,7 +199,7 @@ static inline struct rt_trie_node *tnode + /* + * caller must hold RCU read lock or RTNL + */ +-static inline struct rt_trie_node *tnode_get_child_rcu(const struct tnode *tn, unsigned int i) ++static inline struct tnode *tnode_get_child_rcu(const struct tnode *tn, unsigned int i) + { + BUG_ON(i >= tnode_child_length(tn)); + +@@ -340,11 +324,11 @@ static inline void alias_free_mem_rcu(st + } + + #define TNODE_KMALLOC_MAX \ +- ilog2((PAGE_SIZE - sizeof(struct tnode)) / sizeof(struct rt_trie_node *)) ++ ilog2((PAGE_SIZE - sizeof(struct tnode)) / sizeof(struct tnode *)) + + static void __node_free_rcu(struct rcu_head *head) + { +- struct rt_trie_node *n = container_of(head, struct rt_trie_node, rcu); ++ struct tnode *n = container_of(head, struct tnode, rcu); + + if (IS_LEAF(n)) + kmem_cache_free(trie_leaf_kmem, n); +@@ -395,9 +379,9 @@ static void tnode_free_flush(void) + } + } + +-static struct leaf *leaf_new(t_key key) ++static struct tnode *leaf_new(t_key key) + { +- struct leaf *l = kmem_cache_alloc(trie_leaf_kmem, GFP_KERNEL); ++ struct tnode *l = kmem_cache_alloc(trie_leaf_kmem, GFP_KERNEL); + if (l) { + l->parent = NULL; + /* set key and pos to reflect full key value +@@ -444,7 +428,7 @@ static struct tnode *tnode_new(t_key key + } + + pr_debug("AT %p s=%zu %zu\n", tn, sizeof(struct tnode), +- sizeof(struct rt_trie_node *) << bits); ++ sizeof(struct tnode *) << bits); + return tn; + } + +@@ -453,13 +437,13 @@ static struct tnode *tnode_new(t_key key + * and no bits are skipped. See discussion in dyntree paper p. 6 + */ + +-static inline int tnode_full(const struct tnode *tn, const struct rt_trie_node *n) ++static inline int tnode_full(const struct tnode *tn, const struct tnode *n) + { + return n && IS_TNODE(n) && (n->pos == (tn->pos + tn->bits)); + } + + static inline void put_child(struct tnode *tn, int i, +- struct rt_trie_node *n) ++ struct tnode *n) + { + tnode_put_child_reorg(tn, i, n, -1); + } +@@ -469,10 +453,10 @@ static inline void put_child(struct tnod + * Update the value of full_children and empty_children. + */ + +-static void tnode_put_child_reorg(struct tnode *tn, int i, struct rt_trie_node *n, ++static void tnode_put_child_reorg(struct tnode *tn, int i, struct tnode *n, + int wasfull) + { +- struct rt_trie_node *chi = rtnl_dereference(tn->child[i]); ++ struct tnode *chi = rtnl_dereference(tn->child[i]); + int isfull; + + BUG_ON(i >= 1<bits); +@@ -499,10 +483,9 @@ static void tnode_put_child_reorg(struct + } + + #define MAX_WORK 10 +-static struct rt_trie_node *resize(struct trie *t, struct tnode *tn) ++static struct tnode *resize(struct trie *t, struct tnode *tn) + { +- struct rt_trie_node *n = NULL; +- struct tnode *old_tn; ++ struct tnode *old_tn, *n = NULL; + int inflate_threshold_use; + int halve_threshold_use; + int max_work; +@@ -614,7 +597,7 @@ static struct rt_trie_node *resize(struc + + /* Return if at least one inflate is run */ + if (max_work != MAX_WORK) +- return (struct rt_trie_node *) tn; ++ return tn; + + /* + * Halve as long as the number of empty children in this +@@ -650,13 +633,13 @@ no_children: + tnode_free_safe(tn); + return n; + } +- return (struct rt_trie_node *) tn; ++ return tn; + } + + + static void tnode_clean_free(struct tnode *tn) + { +- struct rt_trie_node *tofree; ++ struct tnode *tofree; + int i; + + for (i = 0; i < tnode_child_length(tn); i++) { +@@ -667,10 +650,10 @@ static void tnode_clean_free(struct tnod + node_free(tn); + } + +-static struct tnode *inflate(struct trie *t, struct tnode *tn) ++static struct tnode *inflate(struct trie *t, struct tnode *oldtnode) + { +- struct tnode *oldtnode = tn; +- int olen = tnode_child_length(tn); ++ int olen = tnode_child_length(oldtnode); ++ struct tnode *tn; + int i; + + pr_debug("In inflate\n"); +@@ -690,11 +673,8 @@ static struct tnode *inflate(struct trie + for (i = 0; i < olen; i++) { + struct tnode *inode; + +- inode = (struct tnode *) tnode_get_child(oldtnode, i); +- if (inode && +- IS_TNODE(inode) && +- inode->pos == oldtnode->pos + oldtnode->bits && +- inode->bits > 1) { ++ inode = tnode_get_child(oldtnode, i); ++ if (tnode_full(oldtnode, inode) && inode->bits > 1) { + struct tnode *left, *right; + t_key m = ~0U << (KEYLENGTH - 1) >> inode->pos; + +@@ -711,33 +691,29 @@ static struct tnode *inflate(struct trie + goto nomem; + } + +- put_child(tn, 2*i, (struct rt_trie_node *) left); +- put_child(tn, 2*i+1, (struct rt_trie_node *) right); ++ put_child(tn, 2*i, left); ++ put_child(tn, 2*i+1, right); + } + } + + for (i = 0; i < olen; i++) { +- struct tnode *inode; +- struct rt_trie_node *node = tnode_get_child(oldtnode, i); ++ struct tnode *inode = tnode_get_child(oldtnode, i); + struct tnode *left, *right; + int size, j; + + /* An empty child */ +- if (node == NULL) ++ if (inode == NULL) + continue; + + /* A leaf or an internal node with skipped bits */ +- +- if (IS_LEAF(node) || (node->pos > (tn->pos + tn->bits - 1))) { ++ if (!tnode_full(oldtnode, inode)) { + put_child(tn, +- tkey_extract_bits(node->key, oldtnode->pos, oldtnode->bits + 1), +- node); ++ tkey_extract_bits(inode->key, tn->pos, tn->bits), ++ inode); + continue; + } + + /* An internal node with two children */ +- inode = (struct tnode *) node; +- + if (inode->bits == 1) { + put_child(tn, 2*i, rtnl_dereference(inode->child[0])); + put_child(tn, 2*i+1, rtnl_dereference(inode->child[1])); +@@ -769,12 +745,12 @@ static struct tnode *inflate(struct trie + * bit to zero. + */ + +- left = (struct tnode *) tnode_get_child(tn, 2*i); ++ left = tnode_get_child(tn, 2*i); + put_child(tn, 2*i, NULL); + + BUG_ON(!left); + +- right = (struct tnode *) tnode_get_child(tn, 2*i+1); ++ right = tnode_get_child(tn, 2*i+1); + put_child(tn, 2*i+1, NULL); + + BUG_ON(!right); +@@ -796,12 +772,11 @@ nomem: + return ERR_PTR(-ENOMEM); + } + +-static struct tnode *halve(struct trie *t, struct tnode *tn) ++static struct tnode *halve(struct trie *t, struct tnode *oldtnode) + { +- struct tnode *oldtnode = tn; +- struct rt_trie_node *left, *right; ++ int olen = tnode_child_length(oldtnode); ++ struct tnode *tn, *left, *right; + int i; +- int olen = tnode_child_length(tn); + + pr_debug("In halve\n"); + +@@ -830,7 +805,7 @@ static struct tnode *halve(struct trie * + if (!newn) + goto nomem; + +- put_child(tn, i/2, (struct rt_trie_node *)newn); ++ put_child(tn, i/2, newn); + } + + } +@@ -855,7 +830,7 @@ static struct tnode *halve(struct trie * + } + + /* Two nonempty children */ +- newBinNode = (struct tnode *) tnode_get_child(tn, i/2); ++ newBinNode = tnode_get_child(tn, i/2); + put_child(tn, i/2, NULL); + put_child(newBinNode, 0, left); + put_child(newBinNode, 1, right); +@@ -871,7 +846,7 @@ nomem: + /* readside must use rcu_read_lock currently dump routines + via get_fa_head and dump */ + +-static struct leaf_info *find_leaf_info(struct leaf *l, int plen) ++static struct leaf_info *find_leaf_info(struct tnode *l, int plen) + { + struct hlist_head *head = &l->list; + struct leaf_info *li; +@@ -883,7 +858,7 @@ static struct leaf_info *find_leaf_info( + return NULL; + } + +-static inline struct list_head *get_fa_head(struct leaf *l, int plen) ++static inline struct list_head *get_fa_head(struct tnode *l, int plen) + { + struct leaf_info *li = find_leaf_info(l, plen); + +@@ -915,32 +890,25 @@ static void insert_leaf_info(struct hlis + + /* rcu_read_lock needs to be hold by caller from readside */ + +-static struct leaf * +-fib_find_node(struct trie *t, u32 key) ++static struct tnode *fib_find_node(struct trie *t, u32 key) + { +- int pos; +- struct tnode *tn; +- struct rt_trie_node *n; +- +- pos = 0; +- n = rcu_dereference_rtnl(t->trie); ++ struct tnode *n = rcu_dereference_rtnl(t->trie); ++ int pos = 0; + + while (n && IS_TNODE(n)) { +- tn = (struct tnode *) n; +- +- if (tkey_sub_equals(tn->key, pos, tn->pos-pos, key)) { +- pos = tn->pos + tn->bits; +- n = tnode_get_child_rcu(tn, ++ if (tkey_sub_equals(n->key, pos, n->pos-pos, key)) { ++ pos = n->pos + n->bits; ++ n = tnode_get_child_rcu(n, + tkey_extract_bits(key, +- tn->pos, +- tn->bits)); ++ n->pos, ++ n->bits)); + } else + break; + } + /* Case we have found a leaf. Compare prefixes */ + + if (n != NULL && IS_LEAF(n) && tkey_equals(key, n->key)) +- return (struct leaf *)n; ++ return n; + + return NULL; + } +@@ -956,14 +924,13 @@ static void trie_rebalance(struct trie * + while (tn != NULL && (tp = node_parent(tn)) != NULL) { + cindex = tkey_extract_bits(key, tp->pos, tp->bits); + wasfull = tnode_full(tp, tnode_get_child(tp, cindex)); +- tn = (struct tnode *)resize(t, tn); ++ tn = resize(t, tn); + +- tnode_put_child_reorg(tp, cindex, +- (struct rt_trie_node *)tn, wasfull); ++ tnode_put_child_reorg(tp, cindex, tn, wasfull); + + tp = node_parent(tn); + if (!tp) +- rcu_assign_pointer(t->trie, (struct rt_trie_node *)tn); ++ rcu_assign_pointer(t->trie, tn); + + tnode_free_flush(); + if (!tp) +@@ -973,9 +940,9 @@ static void trie_rebalance(struct trie * + + /* Handle last (top) tnode */ + if (IS_TNODE(tn)) +- tn = (struct tnode *)resize(t, tn); ++ tn = resize(t, tn); + +- rcu_assign_pointer(t->trie, (struct rt_trie_node *)tn); ++ rcu_assign_pointer(t->trie, tn); + tnode_free_flush(); + } + +@@ -985,8 +952,8 @@ static struct list_head *fib_insert_node + { + int pos, newpos; + struct tnode *tp = NULL, *tn = NULL; +- struct rt_trie_node *n; +- struct leaf *l; ++ struct tnode *n; ++ struct tnode *l; + int missbit; + struct list_head *fa_head = NULL; + struct leaf_info *li; +@@ -1014,17 +981,15 @@ static struct list_head *fib_insert_node + */ + + while (n && IS_TNODE(n)) { +- tn = (struct tnode *) n; +- +- if (tkey_sub_equals(tn->key, pos, tn->pos-pos, key)) { +- tp = tn; +- pos = tn->pos + tn->bits; +- n = tnode_get_child(tn, ++ if (tkey_sub_equals(n->key, pos, n->pos-pos, key)) { ++ tp = n; ++ pos = n->pos + n->bits; ++ n = tnode_get_child(n, + tkey_extract_bits(key, +- tn->pos, +- tn->bits)); ++ n->pos, ++ n->bits)); + +- BUG_ON(n && node_parent(n) != tn); ++ BUG_ON(n && node_parent(n) != tp); + } else + break; + } +@@ -1040,14 +1005,13 @@ static struct list_head *fib_insert_node + /* Case 1: n is a leaf. Compare prefixes */ + + if (n != NULL && IS_LEAF(n) && tkey_equals(key, n->key)) { +- l = (struct leaf *) n; + li = leaf_info_new(plen); + + if (!li) + return NULL; + + fa_head = &li->falh; +- insert_leaf_info(&l->list, li); ++ insert_leaf_info(&n->list, li); + goto done; + } + l = leaf_new(key); +@@ -1068,10 +1032,10 @@ static struct list_head *fib_insert_node + if (t->trie && n == NULL) { + /* Case 2: n is NULL, and will just insert a new leaf */ + +- node_set_parent((struct rt_trie_node *)l, tp); ++ node_set_parent(l, tp); + + cindex = tkey_extract_bits(key, tp->pos, tp->bits); +- put_child(tp, cindex, (struct rt_trie_node *)l); ++ put_child(tp, cindex, l); + } else { + /* Case 3: n is a LEAF or a TNODE and the key doesn't match. */ + /* +@@ -1094,17 +1058,17 @@ static struct list_head *fib_insert_node + return NULL; + } + +- node_set_parent((struct rt_trie_node *)tn, tp); ++ node_set_parent(tn, tp); + + missbit = tkey_extract_bits(key, newpos, 1); +- put_child(tn, missbit, (struct rt_trie_node *)l); ++ put_child(tn, missbit, l); + put_child(tn, 1-missbit, n); + + if (tp) { + cindex = tkey_extract_bits(key, tp->pos, tp->bits); +- put_child(tp, cindex, (struct rt_trie_node *)tn); ++ put_child(tp, cindex, tn); + } else { +- rcu_assign_pointer(t->trie, (struct rt_trie_node *)tn); ++ rcu_assign_pointer(t->trie, tn); + } + + tp = tn; +@@ -1134,7 +1098,7 @@ int fib_table_insert(struct fib_table *t + u8 tos = cfg->fc_tos; + u32 key, mask; + int err; +- struct leaf *l; ++ struct tnode *l; + + if (plen > 32) + return -EINVAL; +@@ -1292,7 +1256,7 @@ err: + } + + /* should be called with rcu_read_lock */ +-static int check_leaf(struct fib_table *tb, struct trie *t, struct leaf *l, ++static int check_leaf(struct fib_table *tb, struct trie *t, struct tnode *l, + t_key key, const struct flowi4 *flp, + struct fib_result *res, int fib_flags) + { +@@ -1365,7 +1329,7 @@ int fib_table_lookup(struct fib_table *t + struct trie_use_stats __percpu *stats = t->stats; + #endif + int ret; +- struct rt_trie_node *n; ++ struct tnode *n; + struct tnode *pn; + unsigned int pos, bits; + t_key key = ntohl(flp->daddr); +@@ -1387,11 +1351,11 @@ int fib_table_lookup(struct fib_table *t + + /* Just a leaf? */ + if (IS_LEAF(n)) { +- ret = check_leaf(tb, t, (struct leaf *)n, key, flp, res, fib_flags); ++ ret = check_leaf(tb, t, n, key, flp, res, fib_flags); + goto found; + } + +- pn = (struct tnode *) n; ++ pn = n; + chopped_off = 0; + + while (pn) { +@@ -1412,13 +1376,13 @@ int fib_table_lookup(struct fib_table *t + } + + if (IS_LEAF(n)) { +- ret = check_leaf(tb, t, (struct leaf *)n, key, flp, res, fib_flags); ++ ret = check_leaf(tb, t, n, key, flp, res, fib_flags); + if (ret > 0) + goto backtrace; + goto found; + } + +- cn = (struct tnode *)n; ++ cn = n; + + /* + * It's a tnode, and we can do some extra checks here if we +@@ -1506,7 +1470,7 @@ int fib_table_lookup(struct fib_table *t + current_prefix_length = mp; + } + +- pn = (struct tnode *)n; /* Descend */ ++ pn = n; /* Descend */ + chopped_off = 0; + continue; + +@@ -1557,7 +1521,7 @@ EXPORT_SYMBOL_GPL(fib_table_lookup); + /* + * Remove the leaf and return parent. + */ +-static void trie_leaf_remove(struct trie *t, struct leaf *l) ++static void trie_leaf_remove(struct trie *t, struct tnode *l) + { + struct tnode *tp = node_parent(l); + +@@ -1584,7 +1548,7 @@ int fib_table_delete(struct fib_table *t + u8 tos = cfg->fc_tos; + struct fib_alias *fa, *fa_to_delete; + struct list_head *fa_head; +- struct leaf *l; ++ struct tnode *l; + struct leaf_info *li; + + if (plen > 32) +@@ -1682,7 +1646,7 @@ static int trie_flush_list(struct list_h + return found; + } + +-static int trie_flush_leaf(struct leaf *l) ++static int trie_flush_leaf(struct tnode *l) + { + int found = 0; + struct hlist_head *lih = &l->list; +@@ -1704,7 +1668,7 @@ static int trie_flush_leaf(struct leaf * + * Scan for the next right leaf starting at node p->child[idx] + * Since we have back pointer, no recursion necessary. + */ +-static struct leaf *leaf_walk_rcu(struct tnode *p, struct rt_trie_node *c) ++static struct tnode *leaf_walk_rcu(struct tnode *p, struct tnode *c) + { + do { + t_key idx; +@@ -1720,47 +1684,46 @@ static struct leaf *leaf_walk_rcu(struct + continue; + + if (IS_LEAF(c)) +- return (struct leaf *) c; ++ return c; + + /* Rescan start scanning in new node */ +- p = (struct tnode *) c; ++ p = c; + idx = 0; + } + + /* Node empty, walk back up to parent */ +- c = (struct rt_trie_node *) p; ++ c = p; + } while ((p = node_parent_rcu(c)) != NULL); + + return NULL; /* Root of trie */ + } + +-static struct leaf *trie_firstleaf(struct trie *t) ++static struct tnode *trie_firstleaf(struct trie *t) + { +- struct tnode *n = (struct tnode *)rcu_dereference_rtnl(t->trie); ++ struct tnode *n = rcu_dereference_rtnl(t->trie); + + if (!n) + return NULL; + + if (IS_LEAF(n)) /* trie is just a leaf */ +- return (struct leaf *) n; ++ return n; + + return leaf_walk_rcu(n, NULL); + } + +-static struct leaf *trie_nextleaf(struct leaf *l) ++static struct tnode *trie_nextleaf(struct tnode *l) + { +- struct rt_trie_node *c = (struct rt_trie_node *) l; +- struct tnode *p = node_parent_rcu(c); ++ struct tnode *p = node_parent_rcu(l); + + if (!p) + return NULL; /* trie with just one leaf */ + +- return leaf_walk_rcu(p, c); ++ return leaf_walk_rcu(p, l); + } + +-static struct leaf *trie_leafindex(struct trie *t, int index) ++static struct tnode *trie_leafindex(struct trie *t, int index) + { +- struct leaf *l = trie_firstleaf(t); ++ struct tnode *l = trie_firstleaf(t); + + while (l && index-- > 0) + l = trie_nextleaf(l); +@@ -1775,7 +1738,7 @@ static struct leaf *trie_leafindex(struc + int fib_table_flush(struct fib_table *tb) + { + struct trie *t = (struct trie *) tb->tb_data; +- struct leaf *l, *ll = NULL; ++ struct tnode *l, *ll = NULL; + int found = 0; + + for (l = trie_firstleaf(t); l; l = trie_nextleaf(l)) { +@@ -1840,7 +1803,7 @@ static int fn_trie_dump_fa(t_key key, in + return skb->len; + } + +-static int fn_trie_dump_leaf(struct leaf *l, struct fib_table *tb, ++static int fn_trie_dump_leaf(struct tnode *l, struct fib_table *tb, + struct sk_buff *skb, struct netlink_callback *cb) + { + struct leaf_info *li; +@@ -1876,7 +1839,7 @@ static int fn_trie_dump_leaf(struct leaf + int fib_table_dump(struct fib_table *tb, struct sk_buff *skb, + struct netlink_callback *cb) + { +- struct leaf *l; ++ struct tnode *l; + struct trie *t = (struct trie *) tb->tb_data; + t_key key = cb->args[2]; + int count = cb->args[3]; +@@ -1922,7 +1885,7 @@ void __init fib_trie_init(void) + 0, SLAB_PANIC, NULL); + + trie_leaf_kmem = kmem_cache_create("ip_fib_trie", +- max(sizeof(struct leaf), ++ max(sizeof(struct tnode), + sizeof(struct leaf_info)), + 0, SLAB_PANIC, NULL); + } +@@ -1965,7 +1928,7 @@ struct fib_trie_iter { + unsigned int depth; + }; + +-static struct rt_trie_node *fib_trie_get_next(struct fib_trie_iter *iter) ++static struct tnode *fib_trie_get_next(struct fib_trie_iter *iter) + { + struct tnode *tn = iter->tnode; + unsigned int cindex = iter->index; +@@ -1979,7 +1942,7 @@ static struct rt_trie_node *fib_trie_get + iter->tnode, iter->index, iter->depth); + rescan: + while (cindex < (1<bits)) { +- struct rt_trie_node *n = tnode_get_child_rcu(tn, cindex); ++ struct tnode *n = tnode_get_child_rcu(tn, cindex); + + if (n) { + if (IS_LEAF(n)) { +@@ -1987,7 +1950,7 @@ rescan: + iter->index = cindex + 1; + } else { + /* push down one level */ +- iter->tnode = (struct tnode *) n; ++ iter->tnode = n; + iter->index = 0; + ++iter->depth; + } +@@ -1998,7 +1961,7 @@ rescan: + } + + /* Current node exhausted, pop back up */ +- p = node_parent_rcu((struct rt_trie_node *)tn); ++ p = node_parent_rcu(tn); + if (p) { + cindex = tkey_extract_bits(tn->key, p->pos, p->bits)+1; + tn = p; +@@ -2010,10 +1973,10 @@ rescan: + return NULL; + } + +-static struct rt_trie_node *fib_trie_get_first(struct fib_trie_iter *iter, ++static struct tnode *fib_trie_get_first(struct fib_trie_iter *iter, + struct trie *t) + { +- struct rt_trie_node *n; ++ struct tnode *n; + + if (!t) + return NULL; +@@ -2023,7 +1986,7 @@ static struct rt_trie_node *fib_trie_get + return NULL; + + if (IS_TNODE(n)) { +- iter->tnode = (struct tnode *) n; ++ iter->tnode = n; + iter->index = 0; + iter->depth = 1; + } else { +@@ -2037,7 +2000,7 @@ static struct rt_trie_node *fib_trie_get + + static void trie_collect_stats(struct trie *t, struct trie_stat *s) + { +- struct rt_trie_node *n; ++ struct tnode *n; + struct fib_trie_iter iter; + + memset(s, 0, sizeof(*s)); +@@ -2045,7 +2008,6 @@ static void trie_collect_stats(struct tr + rcu_read_lock(); + for (n = fib_trie_get_first(&iter, t); n; n = fib_trie_get_next(&iter)) { + if (IS_LEAF(n)) { +- struct leaf *l = (struct leaf *)n; + struct leaf_info *li; + + s->leaves++; +@@ -2053,18 +2015,17 @@ static void trie_collect_stats(struct tr + if (iter.depth > s->maxdepth) + s->maxdepth = iter.depth; + +- hlist_for_each_entry_rcu(li, &l->list, hlist) ++ hlist_for_each_entry_rcu(li, &n->list, hlist) + ++s->prefixes; + } else { +- const struct tnode *tn = (const struct tnode *) n; + int i; + + s->tnodes++; +- if (tn->bits < MAX_STAT_DEPTH) +- s->nodesizes[tn->bits]++; ++ if (n->bits < MAX_STAT_DEPTH) ++ s->nodesizes[n->bits]++; + +- for (i = 0; i < (1<bits); i++) +- if (!tn->child[i]) ++ for (i = 0; i < tnode_child_length(n); i++) ++ if (!rcu_access_pointer(n->child[i])) + s->nullpointers++; + } + } +@@ -2088,7 +2049,7 @@ static void trie_show_stats(struct seq_f + seq_printf(seq, "\tMax depth: %u\n", stat->maxdepth); + + seq_printf(seq, "\tLeaves: %u\n", stat->leaves); +- bytes = sizeof(struct leaf) * stat->leaves; ++ bytes = sizeof(struct tnode) * stat->leaves; + + seq_printf(seq, "\tPrefixes: %u\n", stat->prefixes); + bytes += sizeof(struct leaf_info) * stat->prefixes; +@@ -2109,7 +2070,7 @@ static void trie_show_stats(struct seq_f + seq_putc(seq, '\n'); + seq_printf(seq, "\tPointers: %u\n", pointers); + +- bytes += sizeof(struct rt_trie_node *) * pointers; ++ bytes += sizeof(struct tnode *) * pointers; + seq_printf(seq, "Null ptrs: %u\n", stat->nullpointers); + seq_printf(seq, "Total size: %u kB\n", (bytes + 1023) / 1024); + } +@@ -2163,7 +2124,7 @@ static int fib_triestat_seq_show(struct + seq_printf(seq, + "Basic info: size of leaf:" + " %Zd bytes, size of tnode: %Zd bytes.\n", +- sizeof(struct leaf), sizeof(struct tnode)); ++ sizeof(struct tnode), sizeof(struct tnode)); + + for (h = 0; h < FIB_TABLE_HASHSZ; h++) { + struct hlist_head *head = &net->ipv4.fib_table_hash[h]; +@@ -2202,7 +2163,7 @@ static const struct file_operations fib_ + .release = single_release_net, + }; + +-static struct rt_trie_node *fib_trie_get_idx(struct seq_file *seq, loff_t pos) ++static struct tnode *fib_trie_get_idx(struct seq_file *seq, loff_t pos) + { + struct fib_trie_iter *iter = seq->private; + struct net *net = seq_file_net(seq); +@@ -2214,7 +2175,7 @@ static struct rt_trie_node *fib_trie_get + struct fib_table *tb; + + hlist_for_each_entry_rcu(tb, head, tb_hlist) { +- struct rt_trie_node *n; ++ struct tnode *n; + + for (n = fib_trie_get_first(iter, + (struct trie *) tb->tb_data); +@@ -2243,7 +2204,7 @@ static void *fib_trie_seq_next(struct se + struct fib_table *tb = iter->tb; + struct hlist_node *tb_node; + unsigned int h; +- struct rt_trie_node *n; ++ struct tnode *n; + + ++*pos; + /* next node in same table */ +@@ -2329,29 +2290,26 @@ static inline const char *rtn_type(char + static int fib_trie_seq_show(struct seq_file *seq, void *v) + { + const struct fib_trie_iter *iter = seq->private; +- struct rt_trie_node *n = v; ++ struct tnode *n = v; + + if (!node_parent_rcu(n)) + fib_table_print(seq, iter->tb); + + if (IS_TNODE(n)) { +- struct tnode *tn = (struct tnode *) n; +- __be32 prf = htonl(tn->key); ++ __be32 prf = htonl(n->key); + +- seq_indent(seq, iter->depth-1); ++ seq_indent(seq, iter->depth - 1); + seq_printf(seq, " +-- %pI4/%d %d %d %d\n", +- &prf, tn->pos, tn->bits, tn->full_children, +- tn->empty_children); +- ++ &prf, n->pos, n->bits, n->full_children, ++ n->empty_children); + } else { +- struct leaf *l = (struct leaf *) n; + struct leaf_info *li; +- __be32 val = htonl(l->key); ++ __be32 val = htonl(n->key); + + seq_indent(seq, iter->depth); + seq_printf(seq, " |-- %pI4\n", &val); + +- hlist_for_each_entry_rcu(li, &l->list, hlist) { ++ hlist_for_each_entry_rcu(li, &n->list, hlist) { + struct fib_alias *fa; + + list_for_each_entry_rcu(fa, &li->falh, fa_list) { +@@ -2401,9 +2359,9 @@ struct fib_route_iter { + t_key key; + }; + +-static struct leaf *fib_route_get_idx(struct fib_route_iter *iter, loff_t pos) ++static struct tnode *fib_route_get_idx(struct fib_route_iter *iter, loff_t pos) + { +- struct leaf *l = NULL; ++ struct tnode *l = NULL; + struct trie *t = iter->main_trie; + + /* use cache location of last found key */ +@@ -2448,7 +2406,7 @@ static void *fib_route_seq_start(struct + static void *fib_route_seq_next(struct seq_file *seq, void *v, loff_t *pos) + { + struct fib_route_iter *iter = seq->private; +- struct leaf *l = v; ++ struct tnode *l = v; + + ++*pos; + if (v == SEQ_START_TOKEN) { +@@ -2494,7 +2452,7 @@ static unsigned int fib_flag_trans(int t + */ + static int fib_route_seq_show(struct seq_file *seq, void *v) + { +- struct leaf *l = v; ++ struct tnode *l = v; + struct leaf_info *li; + + if (v == SEQ_START_TOKEN) { diff --git a/target/linux/generic/patches-3.18/080-06-fib_trie-Optimize-fib_table_lookup-to-avoid-wasting-.patch b/target/linux/generic/patches-3.18/080-06-fib_trie-Optimize-fib_table_lookup-to-avoid-wasting-.patch new file mode 100644 index 0000000..e844126 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-06-fib_trie-Optimize-fib_table_lookup-to-avoid-wasting-.patch @@ -0,0 +1,343 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:55:54 -0800 +Subject: [PATCH] fib_trie: Optimize fib_table_lookup to avoid wasting + time on loops/variables + +This patch is meant to reduce the complexity of fib_table_lookup by reducing +the number of variables to the bare minimum while still keeping the same if +not improved functionality versus the original. + +Most of this change was started off by the desire to rid the function of +chopped_off and current_prefix_length as they actually added very little to +the function since they only applied when computing the cindex. I was able +to replace them mostly with just a check for the prefix match. As long as +the prefix between the key and the node being tested was the same we know +we can search the tnode fully versus just testing cindex 0. + +The second portion of the change ended up being a massive reordering. +Originally the calls to check_leaf were up near the start of the loop, and +the backtracing and descending into lower levels of tnodes was later. This +didn't make much sense as the structure of the tree means the leaves are +always the last thing to be tested. As such I reordered things so that we +instead have a loop that will delve into the tree and only exit when we +have either found a leaf or we have exhausted the tree. The advantage of +rearranging things like this is that we can fully inline check_leaf since +there is now only one reference to it in the function. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -90,6 +90,9 @@ typedef unsigned int t_key; + #define IS_TNODE(n) ((n)->bits) + #define IS_LEAF(n) (!(n)->bits) + ++#define get_shift(_kv) (KEYLENGTH - (_kv)->pos - (_kv)->bits) ++#define get_index(_key, _kv) (((_key) ^ (_kv)->key) >> get_shift(_kv)) ++ + struct tnode { + t_key key; + unsigned char bits; /* 2log(KEYLENGTH) bits needed */ +@@ -1281,7 +1284,7 @@ static int check_leaf(struct fib_table * + continue; + fib_alias_accessed(fa); + err = fib_props[fa->fa_type].error; +- if (err) { ++ if (unlikely(err < 0)) { + #ifdef CONFIG_IP_FIB_TRIE_STATS + this_cpu_inc(t->stats->semantic_match_passed); + #endif +@@ -1303,7 +1306,7 @@ static int check_leaf(struct fib_table * + res->prefixlen = li->plen; + res->nh_sel = nhsel; + res->type = fa->fa_type; +- res->scope = fa->fa_info->fib_scope; ++ res->scope = fi->fib_scope; + res->fi = fi; + res->table = tb; + res->fa_head = &li->falh; +@@ -1321,23 +1324,24 @@ static int check_leaf(struct fib_table * + return 1; + } + ++static inline t_key prefix_mismatch(t_key key, struct tnode *n) ++{ ++ t_key prefix = n->key; ++ ++ return (key ^ prefix) & (prefix | -prefix); ++} ++ + int fib_table_lookup(struct fib_table *tb, const struct flowi4 *flp, + struct fib_result *res, int fib_flags) + { +- struct trie *t = (struct trie *) tb->tb_data; ++ struct trie *t = (struct trie *)tb->tb_data; + #ifdef CONFIG_IP_FIB_TRIE_STATS + struct trie_use_stats __percpu *stats = t->stats; + #endif +- int ret; +- struct tnode *n; +- struct tnode *pn; +- unsigned int pos, bits; +- t_key key = ntohl(flp->daddr); +- unsigned int chopped_off; +- t_key cindex = 0; +- unsigned int current_prefix_length = KEYLENGTH; +- struct tnode *cn; +- t_key pref_mismatch; ++ const t_key key = ntohl(flp->daddr); ++ struct tnode *n, *pn; ++ t_key cindex; ++ int ret = 1; + + rcu_read_lock(); + +@@ -1349,170 +1353,102 @@ int fib_table_lookup(struct fib_table *t + this_cpu_inc(stats->gets); + #endif + +- /* Just a leaf? */ +- if (IS_LEAF(n)) { +- ret = check_leaf(tb, t, n, key, flp, res, fib_flags); +- goto found; +- } +- + pn = n; +- chopped_off = 0; +- +- while (pn) { +- pos = pn->pos; +- bits = pn->bits; ++ cindex = 0; + +- if (!chopped_off) +- cindex = tkey_extract_bits(mask_pfx(key, current_prefix_length), +- pos, bits); +- +- n = tnode_get_child_rcu(pn, cindex); +- +- if (n == NULL) { +-#ifdef CONFIG_IP_FIB_TRIE_STATS +- this_cpu_inc(stats->null_node_hit); +-#endif +- goto backtrace; +- } ++ /* Step 1: Travel to the longest prefix match in the trie */ ++ for (;;) { ++ unsigned long index = get_index(key, n); ++ ++ /* This bit of code is a bit tricky but it combines multiple ++ * checks into a single check. The prefix consists of the ++ * prefix plus zeros for the "bits" in the prefix. The index ++ * is the difference between the key and this value. From ++ * this we can actually derive several pieces of data. ++ * if !(index >> bits) ++ * we know the value is child index ++ * else ++ * we have a mismatch in skip bits and failed ++ */ ++ if (index >> n->bits) ++ break; + +- if (IS_LEAF(n)) { +- ret = check_leaf(tb, t, n, key, flp, res, fib_flags); +- if (ret > 0) +- goto backtrace; ++ /* we have found a leaf. Prefixes have already been compared */ ++ if (IS_LEAF(n)) + goto found; +- } +- +- cn = n; + +- /* +- * It's a tnode, and we can do some extra checks here if we +- * like, to avoid descending into a dead-end branch. +- * This tnode is in the parent's child array at index +- * key[p_pos..p_pos+p_bits] but potentially with some bits +- * chopped off, so in reality the index may be just a +- * subprefix, padded with zero at the end. +- * We can also take a look at any skipped bits in this +- * tnode - everything up to p_pos is supposed to be ok, +- * and the non-chopped bits of the index (se previous +- * paragraph) are also guaranteed ok, but the rest is +- * considered unknown. +- * +- * The skipped bits are key[pos+bits..cn->pos]. +- */ +- +- /* If current_prefix_length < pos+bits, we are already doing +- * actual prefix matching, which means everything from +- * pos+(bits-chopped_off) onward must be zero along some +- * branch of this subtree - otherwise there is *no* valid +- * prefix present. Here we can only check the skipped +- * bits. Remember, since we have already indexed into the +- * parent's child array, we know that the bits we chopped of +- * *are* zero. ++ /* only record pn and cindex if we are going to be chopping ++ * bits later. Otherwise we are just wasting cycles. + */ +- +- /* NOTA BENE: Checking only skipped bits +- for the new node here */ +- +- if (current_prefix_length < pos+bits) { +- if (tkey_extract_bits(cn->key, current_prefix_length, +- cn->pos - current_prefix_length) +- || !(cn->child[0])) +- goto backtrace; ++ if (index) { ++ pn = n; ++ cindex = index; + } + +- /* +- * If chopped_off=0, the index is fully validated and we +- * only need to look at the skipped bits for this, the new, +- * tnode. What we actually want to do is to find out if +- * these skipped bits match our key perfectly, or if we will +- * have to count on finding a matching prefix further down, +- * because if we do, we would like to have some way of +- * verifying the existence of such a prefix at this point. +- */ +- +- /* The only thing we can do at this point is to verify that +- * any such matching prefix can indeed be a prefix to our +- * key, and if the bits in the node we are inspecting that +- * do not match our key are not ZERO, this cannot be true. +- * Thus, find out where there is a mismatch (before cn->pos) +- * and verify that all the mismatching bits are zero in the +- * new tnode's key. +- */ ++ n = rcu_dereference(n->child[index]); ++ if (unlikely(!n)) ++ goto backtrace; ++ } + +- /* +- * Note: We aren't very concerned about the piece of +- * the key that precede pn->pos+pn->bits, since these +- * have already been checked. The bits after cn->pos +- * aren't checked since these are by definition +- * "unknown" at this point. Thus, what we want to see +- * is if we are about to enter the "prefix matching" +- * state, and in that case verify that the skipped +- * bits that will prevail throughout this subtree are +- * zero, as they have to be if we are to find a +- * matching prefix. ++ /* Step 2: Sort out leaves and begin backtracing for longest prefix */ ++ for (;;) { ++ /* record the pointer where our next node pointer is stored */ ++ struct tnode __rcu **cptr = n->child; ++ ++ /* This test verifies that none of the bits that differ ++ * between the key and the prefix exist in the region of ++ * the lsb and higher in the prefix. + */ ++ if (unlikely(prefix_mismatch(key, n))) ++ goto backtrace; + +- pref_mismatch = mask_pfx(cn->key ^ key, cn->pos); ++ /* exit out and process leaf */ ++ if (unlikely(IS_LEAF(n))) ++ break; + +- /* +- * In short: If skipped bits in this node do not match +- * the search key, enter the "prefix matching" +- * state.directly. ++ /* Don't bother recording parent info. Since we are in ++ * prefix match mode we will have to come back to wherever ++ * we started this traversal anyway + */ +- if (pref_mismatch) { +- /* fls(x) = __fls(x) + 1 */ +- int mp = KEYLENGTH - __fls(pref_mismatch) - 1; +- +- if (tkey_extract_bits(cn->key, mp, cn->pos - mp) != 0) +- goto backtrace; +- +- if (current_prefix_length >= cn->pos) +- current_prefix_length = mp; +- } +- +- pn = n; /* Descend */ +- chopped_off = 0; +- continue; + ++ while ((n = rcu_dereference(*cptr)) == NULL) { + backtrace: +- chopped_off++; +- +- /* As zero don't change the child key (cindex) */ +- while ((chopped_off <= pn->bits) +- && !(cindex & (1<<(chopped_off-1)))) +- chopped_off++; +- +- /* Decrease current_... with bits chopped off */ +- if (current_prefix_length > pn->pos + pn->bits - chopped_off) +- current_prefix_length = pn->pos + pn->bits +- - chopped_off; +- +- /* +- * Either we do the actual chop off according or if we have +- * chopped off all bits in this tnode walk up to our parent. +- */ +- +- if (chopped_off <= pn->bits) { +- cindex &= ~(1 << (chopped_off-1)); +- } else { +- struct tnode *parent = node_parent_rcu(pn); +- if (!parent) +- goto failed; +- +- /* Get Child's index */ +- cindex = tkey_extract_bits(pn->key, parent->pos, parent->bits); +- pn = parent; +- chopped_off = 0; +- + #ifdef CONFIG_IP_FIB_TRIE_STATS +- this_cpu_inc(stats->backtrack); ++ if (!n) ++ this_cpu_inc(stats->null_node_hit); + #endif +- goto backtrace; ++ /* If we are at cindex 0 there are no more bits for ++ * us to strip at this level so we must ascend back ++ * up one level to see if there are any more bits to ++ * be stripped there. ++ */ ++ while (!cindex) { ++ t_key pkey = pn->key; ++ ++ pn = node_parent_rcu(pn); ++ if (unlikely(!pn)) ++ goto failed; ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ this_cpu_inc(stats->backtrack); ++#endif ++ /* Get Child's index */ ++ cindex = get_index(pkey, pn); ++ } ++ ++ /* strip the least significant bit from the cindex */ ++ cindex &= cindex - 1; ++ ++ /* grab pointer for next child node */ ++ cptr = &pn->child[cindex]; + } + } +-failed: +- ret = 1; ++ + found: ++ /* Step 3: Process the leaf, if that fails fall back to backtracing */ ++ ret = check_leaf(tb, t, n, key, flp, res, fib_flags); ++ if (unlikely(ret > 0)) ++ goto backtrace; ++failed: + rcu_read_unlock(); + return ret; + } diff --git a/target/linux/generic/patches-3.18/080-07-fib_trie-Optimize-fib_find_node.patch b/target/linux/generic/patches-3.18/080-07-fib_trie-Optimize-fib_find_node.patch new file mode 100644 index 0000000..0193f75 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-07-fib_trie-Optimize-fib_find_node.patch @@ -0,0 +1,64 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:00 -0800 +Subject: [PATCH] fib_trie: Optimize fib_find_node + +This patch makes use of the same features I made use of for +fib_table_lookup to streamline fib_find_node. The resultant code should be +smaller and run faster than the original. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -892,28 +892,34 @@ static void insert_leaf_info(struct hlis + } + + /* rcu_read_lock needs to be hold by caller from readside */ +- + static struct tnode *fib_find_node(struct trie *t, u32 key) + { + struct tnode *n = rcu_dereference_rtnl(t->trie); +- int pos = 0; + +- while (n && IS_TNODE(n)) { +- if (tkey_sub_equals(n->key, pos, n->pos-pos, key)) { +- pos = n->pos + n->bits; +- n = tnode_get_child_rcu(n, +- tkey_extract_bits(key, +- n->pos, +- n->bits)); +- } else ++ while (n) { ++ unsigned long index = get_index(key, n); ++ ++ /* This bit of code is a bit tricky but it combines multiple ++ * checks into a single check. The prefix consists of the ++ * prefix plus zeros for the bits in the cindex. The index ++ * is the difference between the key and this value. From ++ * this we can actually derive several pieces of data. ++ * if !(index >> bits) ++ * we know the value is cindex ++ * else ++ * we have a mismatch in skip bits and failed ++ */ ++ if (index >> n->bits) ++ return NULL; ++ ++ /* we have found a leaf. Prefixes have already been compared */ ++ if (IS_LEAF(n)) + break; +- } +- /* Case we have found a leaf. Compare prefixes */ + +- if (n != NULL && IS_LEAF(n) && tkey_equals(key, n->key)) +- return n; ++ n = rcu_dereference_rtnl(n->child[index]); ++ } + +- return NULL; ++ return n; + } + + static void trie_rebalance(struct trie *t, struct tnode *tn) diff --git a/target/linux/generic/patches-3.18/080-08-fib_trie-Optimize-fib_table_insert.patch b/target/linux/generic/patches-3.18/080-08-fib_trie-Optimize-fib_table_insert.patch new file mode 100644 index 0000000..b328d2c --- /dev/null +++ b/target/linux/generic/patches-3.18/080-08-fib_trie-Optimize-fib_table_insert.patch @@ -0,0 +1,276 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:06 -0800 +Subject: [PATCH] fib_trie: Optimize fib_table_insert + +This patch updates the fib_table_insert function to take advantage of the +changes made to improve the performance of fib_table_lookup. As a result +the code should be smaller and run faster then the original. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -222,31 +222,6 @@ static inline t_key tkey_extract_bits(t_ + return 0; + } + +-static inline int tkey_equals(t_key a, t_key b) +-{ +- return a == b; +-} +- +-static inline int tkey_sub_equals(t_key a, int offset, int bits, t_key b) +-{ +- if (bits == 0 || offset >= KEYLENGTH) +- return 1; +- bits = bits > KEYLENGTH ? KEYLENGTH : bits; +- return ((a ^ b) << offset) >> (KEYLENGTH - bits) == 0; +-} +- +-static inline int tkey_mismatch(t_key a, int offset, t_key b) +-{ +- t_key diff = a ^ b; +- int i = offset; +- +- if (!diff) +- return 0; +- while ((diff << i) >> (KEYLENGTH-1) == 0) +- i++; +- return i; +-} +- + /* + To understand this stuff, an understanding of keys and all their bits is + necessary. Every node in the trie has a key associated with it, but not +@@ -485,6 +460,15 @@ static void tnode_put_child_reorg(struct + rcu_assign_pointer(tn->child[i], n); + } + ++static void put_child_root(struct tnode *tp, struct trie *t, ++ t_key key, struct tnode *n) ++{ ++ if (tp) ++ put_child(tp, get_index(key, tp), n); ++ else ++ rcu_assign_pointer(t->trie, n); ++} ++ + #define MAX_WORK 10 + static struct tnode *resize(struct trie *t, struct tnode *tn) + { +@@ -959,138 +943,100 @@ static void trie_rebalance(struct trie * + + static struct list_head *fib_insert_node(struct trie *t, u32 key, int plen) + { +- int pos, newpos; +- struct tnode *tp = NULL, *tn = NULL; +- struct tnode *n; +- struct tnode *l; +- int missbit; + struct list_head *fa_head = NULL; ++ struct tnode *l, *n, *tp = NULL; + struct leaf_info *li; +- t_key cindex; + +- pos = 0; ++ li = leaf_info_new(plen); ++ if (!li) ++ return NULL; ++ fa_head = &li->falh; ++ + n = rtnl_dereference(t->trie); + + /* If we point to NULL, stop. Either the tree is empty and we should + * just put a new leaf in if, or we have reached an empty child slot, + * and we should just put our new leaf in that. +- * If we point to a T_TNODE, check if it matches our key. Note that +- * a T_TNODE might be skipping any number of bits - its 'pos' need +- * not be the parent's 'pos'+'bits'! +- * +- * If it does match the current key, get pos/bits from it, extract +- * the index from our key, push the T_TNODE and walk the tree. +- * +- * If it doesn't, we have to replace it with a new T_TNODE. + * +- * If we point to a T_LEAF, it might or might not have the same key +- * as we do. If it does, just change the value, update the T_LEAF's +- * value, and return it. +- * If it doesn't, we need to replace it with a T_TNODE. ++ * If we hit a node with a key that does't match then we should stop ++ * and create a new tnode to replace that node and insert ourselves ++ * and the other node into the new tnode. + */ ++ while (n) { ++ unsigned long index = get_index(key, n); + +- while (n && IS_TNODE(n)) { +- if (tkey_sub_equals(n->key, pos, n->pos-pos, key)) { +- tp = n; +- pos = n->pos + n->bits; +- n = tnode_get_child(n, +- tkey_extract_bits(key, +- n->pos, +- n->bits)); +- +- BUG_ON(n && node_parent(n) != tp); +- } else ++ /* This bit of code is a bit tricky but it combines multiple ++ * checks into a single check. The prefix consists of the ++ * prefix plus zeros for the "bits" in the prefix. The index ++ * is the difference between the key and this value. From ++ * this we can actually derive several pieces of data. ++ * if !(index >> bits) ++ * we know the value is child index ++ * else ++ * we have a mismatch in skip bits and failed ++ */ ++ if (index >> n->bits) + break; +- } +- +- /* +- * n ----> NULL, LEAF or TNODE +- * +- * tp is n's (parent) ----> NULL or TNODE +- */ + +- BUG_ON(tp && IS_LEAF(tp)); +- +- /* Case 1: n is a leaf. Compare prefixes */ +- +- if (n != NULL && IS_LEAF(n) && tkey_equals(key, n->key)) { +- li = leaf_info_new(plen); +- +- if (!li) +- return NULL; ++ /* we have found a leaf. Prefixes have already been compared */ ++ if (IS_LEAF(n)) { ++ /* Case 1: n is a leaf, and prefixes match*/ ++ insert_leaf_info(&n->list, li); ++ return fa_head; ++ } + +- fa_head = &li->falh; +- insert_leaf_info(&n->list, li); +- goto done; ++ tp = n; ++ n = rcu_dereference_rtnl(n->child[index]); + } +- l = leaf_new(key); +- +- if (!l) +- return NULL; + +- li = leaf_info_new(plen); +- +- if (!li) { +- node_free(l); ++ l = leaf_new(key); ++ if (!l) { ++ free_leaf_info(li); + return NULL; + } + +- fa_head = &li->falh; + insert_leaf_info(&l->list, li); + +- if (t->trie && n == NULL) { +- /* Case 2: n is NULL, and will just insert a new leaf */ +- +- node_set_parent(l, tp); +- +- cindex = tkey_extract_bits(key, tp->pos, tp->bits); +- put_child(tp, cindex, l); +- } else { +- /* Case 3: n is a LEAF or a TNODE and the key doesn't match. */ +- /* +- * Add a new tnode here +- * first tnode need some special handling +- */ ++ /* Case 2: n is a LEAF or a TNODE and the key doesn't match. ++ * ++ * Add a new tnode here ++ * first tnode need some special handling ++ * leaves us in position for handling as case 3 ++ */ ++ if (n) { ++ struct tnode *tn; ++ int newpos; + +- if (n) { +- pos = tp ? tp->pos+tp->bits : 0; +- newpos = tkey_mismatch(key, pos, n->key); +- tn = tnode_new(n->key, newpos, 1); +- } else { +- newpos = 0; +- tn = tnode_new(key, newpos, 1); /* First tnode */ +- } ++ newpos = KEYLENGTH - __fls(n->key ^ key) - 1; + ++ tn = tnode_new(key, newpos, 1); + if (!tn) { + free_leaf_info(li); + node_free(l); + return NULL; + } + +- node_set_parent(tn, tp); +- +- missbit = tkey_extract_bits(key, newpos, 1); +- put_child(tn, missbit, l); +- put_child(tn, 1-missbit, n); +- +- if (tp) { +- cindex = tkey_extract_bits(key, tp->pos, tp->bits); +- put_child(tp, cindex, tn); +- } else { +- rcu_assign_pointer(t->trie, tn); +- } ++ /* initialize routes out of node */ ++ NODE_INIT_PARENT(tn, tp); ++ put_child(tn, get_index(key, tn) ^ 1, n); ++ ++ /* start adding routes into the node */ ++ put_child_root(tp, t, key, tn); ++ node_set_parent(n, tn); + ++ /* parent now has a NULL spot where the leaf can go */ + tp = tn; + } + +- if (tp && tp->pos + tp->bits > 32) +- pr_warn("fib_trie tp=%p pos=%d, bits=%d, key=%0x plen=%d\n", +- tp, tp->pos, tp->bits, key, plen); +- +- /* Rebalance the trie */ ++ /* Case 3: n is NULL, and will just insert a new leaf */ ++ if (tp) { ++ NODE_INIT_PARENT(l, tp); ++ put_child(tp, get_index(key, tp), l); ++ trie_rebalance(t, tp); ++ } else { ++ rcu_assign_pointer(t->trie, l); ++ } + +- trie_rebalance(t, tp); +-done: + return fa_head; + } + +@@ -1470,11 +1416,11 @@ static void trie_leaf_remove(struct trie + pr_debug("entering trie_leaf_remove(%p)\n", l); + + if (tp) { +- t_key cindex = tkey_extract_bits(l->key, tp->pos, tp->bits); +- put_child(tp, cindex, NULL); ++ put_child(tp, get_index(l->key, tp), NULL); + trie_rebalance(t, tp); +- } else ++ } else { + RCU_INIT_POINTER(t->trie, NULL); ++ } + + node_free(l); + } diff --git a/target/linux/generic/patches-3.18/080-09-fib_trie-Update-meaning-of-pos-to-represent-unchecke.patch b/target/linux/generic/patches-3.18/080-09-fib_trie-Update-meaning-of-pos-to-represent-unchecke.patch new file mode 100644 index 0000000..a0d3476 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-09-fib_trie-Update-meaning-of-pos-to-represent-unchecke.patch @@ -0,0 +1,346 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:12 -0800 +Subject: [PATCH] fib_trie: Update meaning of pos to represent unchecked + bits + +This change moves the pos value to the other side of the "bits" field. By +doing this it actually simplifies a significant amount of code in the trie. + +For example when halving a tree we know that the bit lost exists at +oldnode->pos, and if we inflate the tree the new bit being add is at +tn->pos. Previously to find those bits you would have to subtract pos and +bits from the keylength or start with a value of (1 << 31) and then shift +that. + +There are a number of spots throughout the code that benefit from this. In +the case of the hot-path searches the main advantage is that we can drop 2 +or more operations from the search path as we no longer need to compute the +value for the index to be shifted by and can instead just use the raw pos +value. + +In addition the tkey_extract_bits is now defunct and can be replaced by +get_index since the two operations were doing the same thing, but now +get_index does it much more quickly as it is only an xor and shift versus a +pair of shifts and a subtraction. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -90,8 +90,7 @@ typedef unsigned int t_key; + #define IS_TNODE(n) ((n)->bits) + #define IS_LEAF(n) (!(n)->bits) + +-#define get_shift(_kv) (KEYLENGTH - (_kv)->pos - (_kv)->bits) +-#define get_index(_key, _kv) (((_key) ^ (_kv)->key) >> get_shift(_kv)) ++#define get_index(_key, _kv) (((_key) ^ (_kv)->key) >> (_kv)->pos) + + struct tnode { + t_key key; +@@ -209,81 +208,64 @@ static inline struct tnode *tnode_get_ch + return rcu_dereference_rtnl(tn->child[i]); + } + +-static inline t_key mask_pfx(t_key k, unsigned int l) +-{ +- return (l == 0) ? 0 : k >> (KEYLENGTH-l) << (KEYLENGTH-l); +-} +- +-static inline t_key tkey_extract_bits(t_key a, unsigned int offset, unsigned int bits) +-{ +- if (offset < KEYLENGTH) +- return ((t_key)(a << offset)) >> (KEYLENGTH - bits); +- else +- return 0; +-} +- +-/* +- To understand this stuff, an understanding of keys and all their bits is +- necessary. Every node in the trie has a key associated with it, but not +- all of the bits in that key are significant. +- +- Consider a node 'n' and its parent 'tp'. +- +- If n is a leaf, every bit in its key is significant. Its presence is +- necessitated by path compression, since during a tree traversal (when +- searching for a leaf - unless we are doing an insertion) we will completely +- ignore all skipped bits we encounter. Thus we need to verify, at the end of +- a potentially successful search, that we have indeed been walking the +- correct key path. +- +- Note that we can never "miss" the correct key in the tree if present by +- following the wrong path. Path compression ensures that segments of the key +- that are the same for all keys with a given prefix are skipped, but the +- skipped part *is* identical for each node in the subtrie below the skipped +- bit! trie_insert() in this implementation takes care of that - note the +- call to tkey_sub_equals() in trie_insert(). +- +- if n is an internal node - a 'tnode' here, the various parts of its key +- have many different meanings. +- +- Example: +- _________________________________________________________________ +- | i | i | i | i | i | i | i | N | N | N | S | S | S | S | S | C | +- ----------------------------------------------------------------- +- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +- +- _________________________________________________________________ +- | C | C | C | u | u | u | u | u | u | u | u | u | u | u | u | u | +- ----------------------------------------------------------------- +- 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +- +- tp->pos = 7 +- tp->bits = 3 +- n->pos = 15 +- n->bits = 4 +- +- First, let's just ignore the bits that come before the parent tp, that is +- the bits from 0 to (tp->pos-1). They are *known* but at this point we do +- not use them for anything. +- +- The bits from (tp->pos) to (tp->pos + tp->bits - 1) - "N", above - are the +- index into the parent's child array. That is, they will be used to find +- 'n' among tp's children. +- +- The bits from (tp->pos + tp->bits) to (n->pos - 1) - "S" - are skipped bits +- for the node n. +- +- All the bits we have seen so far are significant to the node n. The rest +- of the bits are really not needed or indeed known in n->key. +- +- The bits from (n->pos) to (n->pos + n->bits - 1) - "C" - are the index into +- n's child array, and will of course be different for each child. +- +- +- The rest of the bits, from (n->pos + n->bits) onward, are completely unknown +- at this point. +- +-*/ ++/* To understand this stuff, an understanding of keys and all their bits is ++ * necessary. Every node in the trie has a key associated with it, but not ++ * all of the bits in that key are significant. ++ * ++ * Consider a node 'n' and its parent 'tp'. ++ * ++ * If n is a leaf, every bit in its key is significant. Its presence is ++ * necessitated by path compression, since during a tree traversal (when ++ * searching for a leaf - unless we are doing an insertion) we will completely ++ * ignore all skipped bits we encounter. Thus we need to verify, at the end of ++ * a potentially successful search, that we have indeed been walking the ++ * correct key path. ++ * ++ * Note that we can never "miss" the correct key in the tree if present by ++ * following the wrong path. Path compression ensures that segments of the key ++ * that are the same for all keys with a given prefix are skipped, but the ++ * skipped part *is* identical for each node in the subtrie below the skipped ++ * bit! trie_insert() in this implementation takes care of that. ++ * ++ * if n is an internal node - a 'tnode' here, the various parts of its key ++ * have many different meanings. ++ * ++ * Example: ++ * _________________________________________________________________ ++ * | i | i | i | i | i | i | i | N | N | N | S | S | S | S | S | C | ++ * ----------------------------------------------------------------- ++ * 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ++ * ++ * _________________________________________________________________ ++ * | C | C | C | u | u | u | u | u | u | u | u | u | u | u | u | u | ++ * ----------------------------------------------------------------- ++ * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ++ * ++ * tp->pos = 22 ++ * tp->bits = 3 ++ * n->pos = 13 ++ * n->bits = 4 ++ * ++ * First, let's just ignore the bits that come before the parent tp, that is ++ * the bits from (tp->pos + tp->bits) to 31. They are *known* but at this ++ * point we do not use them for anything. ++ * ++ * The bits from (tp->pos) to (tp->pos + tp->bits - 1) - "N", above - are the ++ * index into the parent's child array. That is, they will be used to find ++ * 'n' among tp's children. ++ * ++ * The bits from (n->pos + n->bits) to (tn->pos - 1) - "S" - are skipped bits ++ * for the node n. ++ * ++ * All the bits we have seen so far are significant to the node n. The rest ++ * of the bits are really not needed or indeed known in n->key. ++ * ++ * The bits from (n->pos) to (n->pos + n->bits - 1) - "C" - are the index into ++ * n's child array, and will of course be different for each child. ++ * ++ * The rest of the bits, from 0 to (n->pos + n->bits), are completely unknown ++ * at this point. ++ */ + + static const int halve_threshold = 25; + static const int inflate_threshold = 50; +@@ -367,7 +349,7 @@ static struct tnode *leaf_new(t_key key) + * as the nodes are searched + */ + l->key = key; +- l->pos = KEYLENGTH; ++ l->pos = 0; + /* set bits to 0 indicating we are not a tnode */ + l->bits = 0; + +@@ -400,7 +382,7 @@ static struct tnode *tnode_new(t_key key + tn->parent = NULL; + tn->pos = pos; + tn->bits = bits; +- tn->key = mask_pfx(key, pos); ++ tn->key = (shift < KEYLENGTH) ? (key >> shift) << shift : 0; + tn->full_children = 0; + tn->empty_children = 1<pos == (tn->pos + tn->bits)); ++ return n && ((n->pos + n->bits) == tn->pos) && IS_TNODE(n); + } + + static inline void put_child(struct tnode *tn, int i, +@@ -641,11 +621,12 @@ static struct tnode *inflate(struct trie + { + int olen = tnode_child_length(oldtnode); + struct tnode *tn; ++ t_key m; + int i; + + pr_debug("In inflate\n"); + +- tn = tnode_new(oldtnode->key, oldtnode->pos, oldtnode->bits + 1); ++ tn = tnode_new(oldtnode->key, oldtnode->pos - 1, oldtnode->bits + 1); + + if (!tn) + return ERR_PTR(-ENOMEM); +@@ -656,21 +637,18 @@ static struct tnode *inflate(struct trie + * fails. In case of failure we return the oldnode and inflate + * of tnode is ignored. + */ ++ for (i = 0, m = 1u << tn->pos; i < olen; i++) { ++ struct tnode *inode = tnode_get_child(oldtnode, i); + +- for (i = 0; i < olen; i++) { +- struct tnode *inode; +- +- inode = tnode_get_child(oldtnode, i); +- if (tnode_full(oldtnode, inode) && inode->bits > 1) { ++ if (tnode_full(oldtnode, inode) && (inode->bits > 1)) { + struct tnode *left, *right; +- t_key m = ~0U << (KEYLENGTH - 1) >> inode->pos; + +- left = tnode_new(inode->key&(~m), inode->pos + 1, ++ left = tnode_new(inode->key & ~m, inode->pos, + inode->bits - 1); + if (!left) + goto nomem; + +- right = tnode_new(inode->key|m, inode->pos + 1, ++ right = tnode_new(inode->key | m, inode->pos, + inode->bits - 1); + + if (!right) { +@@ -694,9 +672,7 @@ static struct tnode *inflate(struct trie + + /* A leaf or an internal node with skipped bits */ + if (!tnode_full(oldtnode, inode)) { +- put_child(tn, +- tkey_extract_bits(inode->key, tn->pos, tn->bits), +- inode); ++ put_child(tn, get_index(inode->key, tn), inode); + continue; + } + +@@ -767,7 +743,7 @@ static struct tnode *halve(struct trie * + + pr_debug("In halve\n"); + +- tn = tnode_new(oldtnode->key, oldtnode->pos, oldtnode->bits - 1); ++ tn = tnode_new(oldtnode->key, oldtnode->pos + 1, oldtnode->bits - 1); + + if (!tn) + return ERR_PTR(-ENOMEM); +@@ -787,7 +763,7 @@ static struct tnode *halve(struct trie * + if (left && right) { + struct tnode *newn; + +- newn = tnode_new(left->key, tn->pos + tn->bits, 1); ++ newn = tnode_new(left->key, oldtnode->pos, 1); + + if (!newn) + goto nomem; +@@ -915,7 +891,7 @@ static void trie_rebalance(struct trie * + key = tn->key; + + while (tn != NULL && (tp = node_parent(tn)) != NULL) { +- cindex = tkey_extract_bits(key, tp->pos, tp->bits); ++ cindex = get_index(key, tp); + wasfull = tnode_full(tp, tnode_get_child(tp, cindex)); + tn = resize(t, tn); + +@@ -1005,11 +981,8 @@ static struct list_head *fib_insert_node + */ + if (n) { + struct tnode *tn; +- int newpos; +- +- newpos = KEYLENGTH - __fls(n->key ^ key) - 1; + +- tn = tnode_new(key, newpos, 1); ++ tn = tnode_new(key, __fls(key ^ n->key), 1); + if (!tn) { + free_leaf_info(li); + node_free(l); +@@ -1559,12 +1532,7 @@ static int trie_flush_leaf(struct tnode + static struct tnode *leaf_walk_rcu(struct tnode *p, struct tnode *c) + { + do { +- t_key idx; +- +- if (c) +- idx = tkey_extract_bits(c->key, p->pos, p->bits) + 1; +- else +- idx = 0; ++ t_key idx = c ? idx = get_index(c->key, p) + 1 : 0; + + while (idx < 1u << p->bits) { + c = tnode_get_child_rcu(p, idx++); +@@ -1851,7 +1819,7 @@ rescan: + /* Current node exhausted, pop back up */ + p = node_parent_rcu(tn); + if (p) { +- cindex = tkey_extract_bits(tn->key, p->pos, p->bits)+1; ++ cindex = get_index(tn->key, p) + 1; + tn = p; + --iter->depth; + goto rescan; +@@ -2186,10 +2154,10 @@ static int fib_trie_seq_show(struct seq_ + if (IS_TNODE(n)) { + __be32 prf = htonl(n->key); + +- seq_indent(seq, iter->depth - 1); +- seq_printf(seq, " +-- %pI4/%d %d %d %d\n", +- &prf, n->pos, n->bits, n->full_children, +- n->empty_children); ++ seq_indent(seq, iter->depth-1); ++ seq_printf(seq, " +-- %pI4/%zu %u %u %u\n", ++ &prf, KEYLENGTH - n->pos - n->bits, n->bits, ++ n->full_children, n->empty_children); + } else { + struct leaf_info *li; + __be32 val = htonl(n->key); diff --git a/target/linux/generic/patches-3.18/080-10-fib_trie-Use-unsigned-long-for-anything-dealing-with.patch b/target/linux/generic/patches-3.18/080-10-fib_trie-Use-unsigned-long-for-anything-dealing-with.patch new file mode 100644 index 0000000..487a25f --- /dev/null +++ b/target/linux/generic/patches-3.18/080-10-fib_trie-Use-unsigned-long-for-anything-dealing-with.patch @@ -0,0 +1,186 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:18 -0800 +Subject: [PATCH] fib_trie: Use unsigned long for anything dealing with a + shift by bits + +This change makes it so that anything that can be shifted by, or compared +to a value shifted by bits is updated to be an unsigned long. This is +mostly a precaution against an insanely huge address space that somehow +starts coming close to the 2^32 root node size which would require +something like 1.5 billion addresses. + +I chose unsigned long instead of unsigned long long since I do not believe +it is possible to allocate a 32 bit tnode on a 32 bit system as the memory +consumed would be 16GB + 28B which exceeds the addressible space for any +one process. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -146,8 +146,8 @@ struct trie { + #endif + }; + +-static void tnode_put_child_reorg(struct tnode *tn, int i, struct tnode *n, +- int wasfull); ++static void tnode_put_child_reorg(struct tnode *tn, unsigned long i, ++ struct tnode *n, int wasfull); + static struct tnode *resize(struct trie *t, struct tnode *tn); + static struct tnode *inflate(struct trie *t, struct tnode *tn); + static struct tnode *halve(struct trie *t, struct tnode *tn); +@@ -183,25 +183,23 @@ static inline void node_set_parent(struc + /* This provides us with the number of children in this node, in the case of a + * leaf this will return 0 meaning none of the children are accessible. + */ +-static inline int tnode_child_length(const struct tnode *tn) ++static inline unsigned long tnode_child_length(const struct tnode *tn) + { + return (1ul << tn->bits) & ~(1ul); + } + +-/* +- * caller must hold RTNL +- */ +-static inline struct tnode *tnode_get_child(const struct tnode *tn, unsigned int i) ++/* caller must hold RTNL */ ++static inline struct tnode *tnode_get_child(const struct tnode *tn, ++ unsigned long i) + { + BUG_ON(i >= tnode_child_length(tn)); + + return rtnl_dereference(tn->child[i]); + } + +-/* +- * caller must hold RCU read lock or RTNL +- */ +-static inline struct tnode *tnode_get_child_rcu(const struct tnode *tn, unsigned int i) ++/* caller must hold RCU read lock or RTNL */ ++static inline struct tnode *tnode_get_child_rcu(const struct tnode *tn, ++ unsigned long i) + { + BUG_ON(i >= tnode_child_length(tn)); + +@@ -400,7 +398,7 @@ static inline int tnode_full(const struc + return n && ((n->pos + n->bits) == tn->pos) && IS_TNODE(n); + } + +-static inline void put_child(struct tnode *tn, int i, ++static inline void put_child(struct tnode *tn, unsigned long i, + struct tnode *n) + { + tnode_put_child_reorg(tn, i, n, -1); +@@ -411,13 +409,13 @@ static inline void put_child(struct tnod + * Update the value of full_children and empty_children. + */ + +-static void tnode_put_child_reorg(struct tnode *tn, int i, struct tnode *n, +- int wasfull) ++static void tnode_put_child_reorg(struct tnode *tn, unsigned long i, ++ struct tnode *n, int wasfull) + { + struct tnode *chi = rtnl_dereference(tn->child[i]); + int isfull; + +- BUG_ON(i >= 1<bits); ++ BUG_ON(i >= tnode_child_length(tn)); + + /* update emptyChildren */ + if (n == NULL && chi != NULL) +@@ -607,10 +605,10 @@ no_children: + static void tnode_clean_free(struct tnode *tn) + { + struct tnode *tofree; +- int i; ++ unsigned long i; + + for (i = 0; i < tnode_child_length(tn); i++) { +- tofree = rtnl_dereference(tn->child[i]); ++ tofree = tnode_get_child(tn, i); + if (tofree) + node_free(tofree); + } +@@ -619,10 +617,10 @@ static void tnode_clean_free(struct tnod + + static struct tnode *inflate(struct trie *t, struct tnode *oldtnode) + { +- int olen = tnode_child_length(oldtnode); ++ unsigned long olen = tnode_child_length(oldtnode); + struct tnode *tn; ++ unsigned long i; + t_key m; +- int i; + + pr_debug("In inflate\n"); + +@@ -664,7 +662,7 @@ static struct tnode *inflate(struct trie + for (i = 0; i < olen; i++) { + struct tnode *inode = tnode_get_child(oldtnode, i); + struct tnode *left, *right; +- int size, j; ++ unsigned long size, j; + + /* An empty child */ + if (inode == NULL) +@@ -737,7 +735,7 @@ nomem: + + static struct tnode *halve(struct trie *t, struct tnode *oldtnode) + { +- int olen = tnode_child_length(oldtnode); ++ unsigned long olen = tnode_child_length(oldtnode); + struct tnode *tn, *left, *right; + int i; + +@@ -1532,9 +1530,9 @@ static int trie_flush_leaf(struct tnode + static struct tnode *leaf_walk_rcu(struct tnode *p, struct tnode *c) + { + do { +- t_key idx = c ? idx = get_index(c->key, p) + 1 : 0; ++ unsigned long idx = c ? idx = get_index(c->key, p) + 1 : 0; + +- while (idx < 1u << p->bits) { ++ while (idx < tnode_child_length(p)) { + c = tnode_get_child_rcu(p, idx++); + if (!c) + continue; +@@ -1786,8 +1784,8 @@ struct fib_trie_iter { + + static struct tnode *fib_trie_get_next(struct fib_trie_iter *iter) + { ++ unsigned long cindex = iter->index; + struct tnode *tn = iter->tnode; +- unsigned int cindex = iter->index; + struct tnode *p; + + /* A single entry routing table */ +@@ -1797,7 +1795,7 @@ static struct tnode *fib_trie_get_next(s + pr_debug("get_next iter={node=%p index=%d depth=%d}\n", + iter->tnode, iter->index, iter->depth); + rescan: +- while (cindex < (1<bits)) { ++ while (cindex < tnode_child_length(tn)) { + struct tnode *n = tnode_get_child_rcu(tn, cindex); + + if (n) { +@@ -1874,15 +1872,16 @@ static void trie_collect_stats(struct tr + hlist_for_each_entry_rcu(li, &n->list, hlist) + ++s->prefixes; + } else { +- int i; ++ unsigned long i; + + s->tnodes++; + if (n->bits < MAX_STAT_DEPTH) + s->nodesizes[n->bits]++; + +- for (i = 0; i < tnode_child_length(n); i++) ++ for (i = 0; i < tnode_child_length(n); i++) { + if (!rcu_access_pointer(n->child[i])) + s->nullpointers++; ++ } + } + } + rcu_read_unlock(); diff --git a/target/linux/generic/patches-3.18/080-11-fib_trie-Push-rcu_read_lock-unlock-to-callers.patch b/target/linux/generic/patches-3.18/080-11-fib_trie-Push-rcu_read_lock-unlock-to-callers.patch new file mode 100644 index 0000000..b36bcd8 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-11-fib_trie-Push-rcu_read_lock-unlock-to-callers.patch @@ -0,0 +1,403 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:24 -0800 +Subject: [PATCH] fib_trie: Push rcu_read_lock/unlock to callers + +This change is to start cleaning up some of the rcu_read_lock/unlock +handling. I realized while reviewing the code there are several spots that +I don't believe are being handled correctly or are masking warnings by +locally calling rcu_read_lock/unlock instead of calling them at the correct +level. + +A common example is a call to fib_get_table followed by fib_table_lookup. +The rcu_read_lock/unlock ought to wrap both but there are several spots where +they were not wrapped. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/include/net/ip_fib.h ++++ b/include/net/ip_fib.h +@@ -222,16 +222,19 @@ static inline struct fib_table *fib_new_ + static inline int fib_lookup(struct net *net, const struct flowi4 *flp, + struct fib_result *res) + { +- struct fib_table *table; ++ int err = -ENETUNREACH; + +- table = fib_get_table(net, RT_TABLE_LOCAL); +- if (!fib_table_lookup(table, flp, res, FIB_LOOKUP_NOREF)) +- return 0; +- +- table = fib_get_table(net, RT_TABLE_MAIN); +- if (!fib_table_lookup(table, flp, res, FIB_LOOKUP_NOREF)) +- return 0; +- return -ENETUNREACH; ++ rcu_read_lock(); ++ ++ if (!fib_table_lookup(fib_get_table(net, RT_TABLE_LOCAL), flp, res, ++ FIB_LOOKUP_NOREF) || ++ !fib_table_lookup(fib_get_table(net, RT_TABLE_MAIN), flp, res, ++ FIB_LOOKUP_NOREF)) ++ err = 0; ++ ++ rcu_read_unlock(); ++ ++ return err; + } + + #else /* CONFIG_IP_MULTIPLE_TABLES */ +@@ -247,20 +250,25 @@ static inline int fib_lookup(struct net + struct fib_result *res) + { + if (!net->ipv4.fib_has_custom_rules) { ++ int err = -ENETUNREACH; ++ ++ rcu_read_lock(); ++ + res->tclassid = 0; +- if (net->ipv4.fib_local && +- !fib_table_lookup(net->ipv4.fib_local, flp, res, +- FIB_LOOKUP_NOREF)) +- return 0; +- if (net->ipv4.fib_main && +- !fib_table_lookup(net->ipv4.fib_main, flp, res, +- FIB_LOOKUP_NOREF)) +- return 0; +- if (net->ipv4.fib_default && +- !fib_table_lookup(net->ipv4.fib_default, flp, res, +- FIB_LOOKUP_NOREF)) +- return 0; +- return -ENETUNREACH; ++ if ((net->ipv4.fib_local && ++ !fib_table_lookup(net->ipv4.fib_local, flp, res, ++ FIB_LOOKUP_NOREF)) || ++ (net->ipv4.fib_main && ++ !fib_table_lookup(net->ipv4.fib_main, flp, res, ++ FIB_LOOKUP_NOREF)) || ++ (net->ipv4.fib_default && ++ !fib_table_lookup(net->ipv4.fib_default, flp, res, ++ FIB_LOOKUP_NOREF))) ++ err = 0; ++ ++ rcu_read_unlock(); ++ ++ return err; + } + return __fib_lookup(net, flp, res); + } +--- a/net/ipv4/fib_frontend.c ++++ b/net/ipv4/fib_frontend.c +@@ -109,6 +109,7 @@ struct fib_table *fib_new_table(struct n + return tb; + } + ++/* caller must hold either rtnl or rcu read lock */ + struct fib_table *fib_get_table(struct net *net, u32 id) + { + struct fib_table *tb; +@@ -119,15 +120,11 @@ struct fib_table *fib_get_table(struct n + id = RT_TABLE_MAIN; + h = id & (FIB_TABLE_HASHSZ - 1); + +- rcu_read_lock(); + head = &net->ipv4.fib_table_hash[h]; + hlist_for_each_entry_rcu(tb, head, tb_hlist) { +- if (tb->tb_id == id) { +- rcu_read_unlock(); ++ if (tb->tb_id == id) + return tb; +- } + } +- rcu_read_unlock(); + return NULL; + } + #endif /* CONFIG_IP_MULTIPLE_TABLES */ +@@ -167,16 +164,18 @@ static inline unsigned int __inet_dev_ad + if (ipv4_is_multicast(addr)) + return RTN_MULTICAST; + ++ rcu_read_lock(); ++ + local_table = fib_get_table(net, RT_TABLE_LOCAL); + if (local_table) { + ret = RTN_UNICAST; +- rcu_read_lock(); + if (!fib_table_lookup(local_table, &fl4, &res, FIB_LOOKUP_NOREF)) { + if (!dev || dev == res.fi->fib_dev) + ret = res.type; + } +- rcu_read_unlock(); + } ++ ++ rcu_read_unlock(); + return ret; + } + +@@ -919,7 +918,7 @@ void fib_del_ifaddr(struct in_ifaddr *if + #undef BRD1_OK + } + +-static void nl_fib_lookup(struct fib_result_nl *frn, struct fib_table *tb) ++static void nl_fib_lookup(struct net *net, struct fib_result_nl *frn) + { + + struct fib_result res; +@@ -929,6 +928,11 @@ static void nl_fib_lookup(struct fib_res + .flowi4_tos = frn->fl_tos, + .flowi4_scope = frn->fl_scope, + }; ++ struct fib_table *tb; ++ ++ rcu_read_lock(); ++ ++ tb = fib_get_table(net, frn->tb_id_in); + + frn->err = -ENOENT; + if (tb) { +@@ -945,6 +949,8 @@ static void nl_fib_lookup(struct fib_res + } + local_bh_enable(); + } ++ ++ rcu_read_unlock(); + } + + static void nl_fib_input(struct sk_buff *skb) +@@ -952,7 +958,6 @@ static void nl_fib_input(struct sk_buff + struct net *net; + struct fib_result_nl *frn; + struct nlmsghdr *nlh; +- struct fib_table *tb; + u32 portid; + + net = sock_net(skb->sk); +@@ -967,9 +972,7 @@ static void nl_fib_input(struct sk_buff + nlh = nlmsg_hdr(skb); + + frn = (struct fib_result_nl *) nlmsg_data(nlh); +- tb = fib_get_table(net, frn->tb_id_in); +- +- nl_fib_lookup(frn, tb); ++ nl_fib_lookup(net, frn); + + portid = NETLINK_CB(skb).portid; /* netlink portid */ + NETLINK_CB(skb).portid = 0; /* from kernel */ +--- a/net/ipv4/fib_rules.c ++++ b/net/ipv4/fib_rules.c +@@ -81,27 +81,25 @@ static int fib4_rule_action(struct fib_r + break; + + case FR_ACT_UNREACHABLE: +- err = -ENETUNREACH; +- goto errout; ++ return -ENETUNREACH; + + case FR_ACT_PROHIBIT: +- err = -EACCES; +- goto errout; ++ return -EACCES; + + case FR_ACT_BLACKHOLE: + default: +- err = -EINVAL; +- goto errout; ++ return -EINVAL; + } + ++ rcu_read_lock(); ++ + tbl = fib_get_table(rule->fr_net, rule->table); +- if (!tbl) +- goto errout; ++ if (tbl) ++ err = fib_table_lookup(tbl, &flp->u.ip4, ++ (struct fib_result *)arg->result, ++ arg->flags); + +- err = fib_table_lookup(tbl, &flp->u.ip4, (struct fib_result *) arg->result, arg->flags); +- if (err > 0) +- err = -EAGAIN; +-errout: ++ rcu_read_unlock(); + return err; + } + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -1181,72 +1181,6 @@ err: + return err; + } + +-/* should be called with rcu_read_lock */ +-static int check_leaf(struct fib_table *tb, struct trie *t, struct tnode *l, +- t_key key, const struct flowi4 *flp, +- struct fib_result *res, int fib_flags) +-{ +- struct leaf_info *li; +- struct hlist_head *hhead = &l->list; +- +- hlist_for_each_entry_rcu(li, hhead, hlist) { +- struct fib_alias *fa; +- +- if (l->key != (key & li->mask_plen)) +- continue; +- +- list_for_each_entry_rcu(fa, &li->falh, fa_list) { +- struct fib_info *fi = fa->fa_info; +- int nhsel, err; +- +- if (fa->fa_tos && fa->fa_tos != flp->flowi4_tos) +- continue; +- if (fi->fib_dead) +- continue; +- if (fa->fa_info->fib_scope < flp->flowi4_scope) +- continue; +- fib_alias_accessed(fa); +- err = fib_props[fa->fa_type].error; +- if (unlikely(err < 0)) { +-#ifdef CONFIG_IP_FIB_TRIE_STATS +- this_cpu_inc(t->stats->semantic_match_passed); +-#endif +- return err; +- } +- if (fi->fib_flags & RTNH_F_DEAD) +- continue; +- for (nhsel = 0; nhsel < fi->fib_nhs; nhsel++) { +- const struct fib_nh *nh = &fi->fib_nh[nhsel]; +- +- if (nh->nh_flags & RTNH_F_DEAD) +- continue; +- if (flp->flowi4_oif && flp->flowi4_oif != nh->nh_oif) +- continue; +- +-#ifdef CONFIG_IP_FIB_TRIE_STATS +- this_cpu_inc(t->stats->semantic_match_passed); +-#endif +- res->prefixlen = li->plen; +- res->nh_sel = nhsel; +- res->type = fa->fa_type; +- res->scope = fi->fib_scope; +- res->fi = fi; +- res->table = tb; +- res->fa_head = &li->falh; +- if (!(fib_flags & FIB_LOOKUP_NOREF)) +- atomic_inc(&fi->fib_clntref); +- return 0; +- } +- } +- +-#ifdef CONFIG_IP_FIB_TRIE_STATS +- this_cpu_inc(t->stats->semantic_match_miss); +-#endif +- } +- +- return 1; +-} +- + static inline t_key prefix_mismatch(t_key key, struct tnode *n) + { + t_key prefix = n->key; +@@ -1254,6 +1188,7 @@ static inline t_key prefix_mismatch(t_ke + return (key ^ prefix) & (prefix | -prefix); + } + ++/* should be called with rcu_read_lock */ + int fib_table_lookup(struct fib_table *tb, const struct flowi4 *flp, + struct fib_result *res, int fib_flags) + { +@@ -1263,14 +1198,12 @@ int fib_table_lookup(struct fib_table *t + #endif + const t_key key = ntohl(flp->daddr); + struct tnode *n, *pn; ++ struct leaf_info *li; + t_key cindex; +- int ret = 1; +- +- rcu_read_lock(); + + n = rcu_dereference(t->trie); + if (!n) +- goto failed; ++ return -EAGAIN; + + #ifdef CONFIG_IP_FIB_TRIE_STATS + this_cpu_inc(stats->gets); +@@ -1350,7 +1283,7 @@ backtrace: + + pn = node_parent_rcu(pn); + if (unlikely(!pn)) +- goto failed; ++ return -EAGAIN; + #ifdef CONFIG_IP_FIB_TRIE_STATS + this_cpu_inc(stats->backtrack); + #endif +@@ -1368,12 +1301,62 @@ backtrace: + + found: + /* Step 3: Process the leaf, if that fails fall back to backtracing */ +- ret = check_leaf(tb, t, n, key, flp, res, fib_flags); +- if (unlikely(ret > 0)) +- goto backtrace; +-failed: +- rcu_read_unlock(); +- return ret; ++ hlist_for_each_entry_rcu(li, &n->list, hlist) { ++ struct fib_alias *fa; ++ ++ if ((key ^ n->key) & li->mask_plen) ++ continue; ++ ++ list_for_each_entry_rcu(fa, &li->falh, fa_list) { ++ struct fib_info *fi = fa->fa_info; ++ int nhsel, err; ++ ++ if (fa->fa_tos && fa->fa_tos != flp->flowi4_tos) ++ continue; ++ if (fi->fib_dead) ++ continue; ++ if (fa->fa_info->fib_scope < flp->flowi4_scope) ++ continue; ++ fib_alias_accessed(fa); ++ err = fib_props[fa->fa_type].error; ++ if (unlikely(err < 0)) { ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ this_cpu_inc(stats->semantic_match_passed); ++#endif ++ return err; ++ } ++ if (fi->fib_flags & RTNH_F_DEAD) ++ continue; ++ for (nhsel = 0; nhsel < fi->fib_nhs; nhsel++) { ++ const struct fib_nh *nh = &fi->fib_nh[nhsel]; ++ ++ if (nh->nh_flags & RTNH_F_DEAD) ++ continue; ++ if (flp->flowi4_oif && flp->flowi4_oif != nh->nh_oif) ++ continue; ++ ++ if (!(fib_flags & FIB_LOOKUP_NOREF)) ++ atomic_inc(&fi->fib_clntref); ++ ++ res->prefixlen = li->plen; ++ res->nh_sel = nhsel; ++ res->type = fa->fa_type; ++ res->scope = fi->fib_scope; ++ res->fi = fi; ++ res->table = tb; ++ res->fa_head = &li->falh; ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ this_cpu_inc(stats->semantic_match_passed); ++#endif ++ return err; ++ } ++ } ++ ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ this_cpu_inc(stats->semantic_match_miss); ++#endif ++ } ++ goto backtrace; + } + EXPORT_SYMBOL_GPL(fib_table_lookup); + diff --git a/target/linux/generic/patches-3.18/080-12-fib_trie-Move-resize-to-after-inflate-halve.patch b/target/linux/generic/patches-3.18/080-12-fib_trie-Move-resize-to-after-inflate-halve.patch new file mode 100644 index 0000000..a373add --- /dev/null +++ b/target/linux/generic/patches-3.18/080-12-fib_trie-Move-resize-to-after-inflate-halve.patch @@ -0,0 +1,345 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:31 -0800 +Subject: [PATCH] fib_trie: Move resize to after inflate/halve + +This change consists of a cut/paste of resize to behind inflate and halve +so that I could remove the two function prototypes. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -149,8 +149,6 @@ struct trie { + static void tnode_put_child_reorg(struct tnode *tn, unsigned long i, + struct tnode *n, int wasfull); + static struct tnode *resize(struct trie *t, struct tnode *tn); +-static struct tnode *inflate(struct trie *t, struct tnode *tn); +-static struct tnode *halve(struct trie *t, struct tnode *tn); + /* tnodes to free after resize(); protected by RTNL */ + static struct callback_head *tnode_free_head; + static size_t tnode_free_size; +@@ -447,161 +445,6 @@ static void put_child_root(struct tnode + rcu_assign_pointer(t->trie, n); + } + +-#define MAX_WORK 10 +-static struct tnode *resize(struct trie *t, struct tnode *tn) +-{ +- struct tnode *old_tn, *n = NULL; +- int inflate_threshold_use; +- int halve_threshold_use; +- int max_work; +- +- if (!tn) +- return NULL; +- +- pr_debug("In tnode_resize %p inflate_threshold=%d threshold=%d\n", +- tn, inflate_threshold, halve_threshold); +- +- /* No children */ +- if (tn->empty_children > (tnode_child_length(tn) - 1)) +- goto no_children; +- +- /* One child */ +- if (tn->empty_children == (tnode_child_length(tn) - 1)) +- goto one_child; +- /* +- * Double as long as the resulting node has a number of +- * nonempty nodes that are above the threshold. +- */ +- +- /* +- * From "Implementing a dynamic compressed trie" by Stefan Nilsson of +- * the Helsinki University of Technology and Matti Tikkanen of Nokia +- * Telecommunications, page 6: +- * "A node is doubled if the ratio of non-empty children to all +- * children in the *doubled* node is at least 'high'." +- * +- * 'high' in this instance is the variable 'inflate_threshold'. It +- * is expressed as a percentage, so we multiply it with +- * tnode_child_length() and instead of multiplying by 2 (since the +- * child array will be doubled by inflate()) and multiplying +- * the left-hand side by 100 (to handle the percentage thing) we +- * multiply the left-hand side by 50. +- * +- * The left-hand side may look a bit weird: tnode_child_length(tn) +- * - tn->empty_children is of course the number of non-null children +- * in the current node. tn->full_children is the number of "full" +- * children, that is non-null tnodes with a skip value of 0. +- * All of those will be doubled in the resulting inflated tnode, so +- * we just count them one extra time here. +- * +- * A clearer way to write this would be: +- * +- * to_be_doubled = tn->full_children; +- * not_to_be_doubled = tnode_child_length(tn) - tn->empty_children - +- * tn->full_children; +- * +- * new_child_length = tnode_child_length(tn) * 2; +- * +- * new_fill_factor = 100 * (not_to_be_doubled + 2*to_be_doubled) / +- * new_child_length; +- * if (new_fill_factor >= inflate_threshold) +- * +- * ...and so on, tho it would mess up the while () loop. +- * +- * anyway, +- * 100 * (not_to_be_doubled + 2*to_be_doubled) / new_child_length >= +- * inflate_threshold +- * +- * avoid a division: +- * 100 * (not_to_be_doubled + 2*to_be_doubled) >= +- * inflate_threshold * new_child_length +- * +- * expand not_to_be_doubled and to_be_doubled, and shorten: +- * 100 * (tnode_child_length(tn) - tn->empty_children + +- * tn->full_children) >= inflate_threshold * new_child_length +- * +- * expand new_child_length: +- * 100 * (tnode_child_length(tn) - tn->empty_children + +- * tn->full_children) >= +- * inflate_threshold * tnode_child_length(tn) * 2 +- * +- * shorten again: +- * 50 * (tn->full_children + tnode_child_length(tn) - +- * tn->empty_children) >= inflate_threshold * +- * tnode_child_length(tn) +- * +- */ +- +- /* Keep root node larger */ +- +- if (!node_parent(tn)) { +- inflate_threshold_use = inflate_threshold_root; +- halve_threshold_use = halve_threshold_root; +- } else { +- inflate_threshold_use = inflate_threshold; +- halve_threshold_use = halve_threshold; +- } +- +- max_work = MAX_WORK; +- while ((tn->full_children > 0 && max_work-- && +- 50 * (tn->full_children + tnode_child_length(tn) +- - tn->empty_children) +- >= inflate_threshold_use * tnode_child_length(tn))) { +- +- old_tn = tn; +- tn = inflate(t, tn); +- +- if (IS_ERR(tn)) { +- tn = old_tn; +-#ifdef CONFIG_IP_FIB_TRIE_STATS +- this_cpu_inc(t->stats->resize_node_skipped); +-#endif +- break; +- } +- } +- +- /* Return if at least one inflate is run */ +- if (max_work != MAX_WORK) +- return tn; +- +- /* +- * Halve as long as the number of empty children in this +- * node is above threshold. +- */ +- +- max_work = MAX_WORK; +- while (tn->bits > 1 && max_work-- && +- 100 * (tnode_child_length(tn) - tn->empty_children) < +- halve_threshold_use * tnode_child_length(tn)) { +- +- old_tn = tn; +- tn = halve(t, tn); +- if (IS_ERR(tn)) { +- tn = old_tn; +-#ifdef CONFIG_IP_FIB_TRIE_STATS +- this_cpu_inc(t->stats->resize_node_skipped); +-#endif +- break; +- } +- } +- +- +- /* Only one child remains */ +- if (tn->empty_children == (tnode_child_length(tn) - 1)) { +- unsigned long i; +-one_child: +- for (i = tnode_child_length(tn); !n && i;) +- n = tnode_get_child(tn, --i); +-no_children: +- /* compress one level */ +- node_set_parent(n, NULL); +- tnode_free_safe(tn); +- return n; +- } +- return tn; +-} +- +- + static void tnode_clean_free(struct tnode *tn) + { + struct tnode *tofree; +@@ -804,6 +647,160 @@ nomem: + return ERR_PTR(-ENOMEM); + } + ++#define MAX_WORK 10 ++static struct tnode *resize(struct trie *t, struct tnode *tn) ++{ ++ struct tnode *old_tn, *n = NULL; ++ int inflate_threshold_use; ++ int halve_threshold_use; ++ int max_work; ++ ++ if (!tn) ++ return NULL; ++ ++ pr_debug("In tnode_resize %p inflate_threshold=%d threshold=%d\n", ++ tn, inflate_threshold, halve_threshold); ++ ++ /* No children */ ++ if (tn->empty_children > (tnode_child_length(tn) - 1)) ++ goto no_children; ++ ++ /* One child */ ++ if (tn->empty_children == (tnode_child_length(tn) - 1)) ++ goto one_child; ++ /* ++ * Double as long as the resulting node has a number of ++ * nonempty nodes that are above the threshold. ++ */ ++ ++ /* ++ * From "Implementing a dynamic compressed trie" by Stefan Nilsson of ++ * the Helsinki University of Technology and Matti Tikkanen of Nokia ++ * Telecommunications, page 6: ++ * "A node is doubled if the ratio of non-empty children to all ++ * children in the *doubled* node is at least 'high'." ++ * ++ * 'high' in this instance is the variable 'inflate_threshold'. It ++ * is expressed as a percentage, so we multiply it with ++ * tnode_child_length() and instead of multiplying by 2 (since the ++ * child array will be doubled by inflate()) and multiplying ++ * the left-hand side by 100 (to handle the percentage thing) we ++ * multiply the left-hand side by 50. ++ * ++ * The left-hand side may look a bit weird: tnode_child_length(tn) ++ * - tn->empty_children is of course the number of non-null children ++ * in the current node. tn->full_children is the number of "full" ++ * children, that is non-null tnodes with a skip value of 0. ++ * All of those will be doubled in the resulting inflated tnode, so ++ * we just count them one extra time here. ++ * ++ * A clearer way to write this would be: ++ * ++ * to_be_doubled = tn->full_children; ++ * not_to_be_doubled = tnode_child_length(tn) - tn->empty_children - ++ * tn->full_children; ++ * ++ * new_child_length = tnode_child_length(tn) * 2; ++ * ++ * new_fill_factor = 100 * (not_to_be_doubled + 2*to_be_doubled) / ++ * new_child_length; ++ * if (new_fill_factor >= inflate_threshold) ++ * ++ * ...and so on, tho it would mess up the while () loop. ++ * ++ * anyway, ++ * 100 * (not_to_be_doubled + 2*to_be_doubled) / new_child_length >= ++ * inflate_threshold ++ * ++ * avoid a division: ++ * 100 * (not_to_be_doubled + 2*to_be_doubled) >= ++ * inflate_threshold * new_child_length ++ * ++ * expand not_to_be_doubled and to_be_doubled, and shorten: ++ * 100 * (tnode_child_length(tn) - tn->empty_children + ++ * tn->full_children) >= inflate_threshold * new_child_length ++ * ++ * expand new_child_length: ++ * 100 * (tnode_child_length(tn) - tn->empty_children + ++ * tn->full_children) >= ++ * inflate_threshold * tnode_child_length(tn) * 2 ++ * ++ * shorten again: ++ * 50 * (tn->full_children + tnode_child_length(tn) - ++ * tn->empty_children) >= inflate_threshold * ++ * tnode_child_length(tn) ++ * ++ */ ++ ++ /* Keep root node larger */ ++ ++ if (!node_parent(tn)) { ++ inflate_threshold_use = inflate_threshold_root; ++ halve_threshold_use = halve_threshold_root; ++ } else { ++ inflate_threshold_use = inflate_threshold; ++ halve_threshold_use = halve_threshold; ++ } ++ ++ max_work = MAX_WORK; ++ while ((tn->full_children > 0 && max_work-- && ++ 50 * (tn->full_children + tnode_child_length(tn) ++ - tn->empty_children) ++ >= inflate_threshold_use * tnode_child_length(tn))) { ++ ++ old_tn = tn; ++ tn = inflate(t, tn); ++ ++ if (IS_ERR(tn)) { ++ tn = old_tn; ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ this_cpu_inc(t->stats->resize_node_skipped); ++#endif ++ break; ++ } ++ } ++ ++ /* Return if at least one inflate is run */ ++ if (max_work != MAX_WORK) ++ return tn; ++ ++ /* ++ * Halve as long as the number of empty children in this ++ * node is above threshold. ++ */ ++ ++ max_work = MAX_WORK; ++ while (tn->bits > 1 && max_work-- && ++ 100 * (tnode_child_length(tn) - tn->empty_children) < ++ halve_threshold_use * tnode_child_length(tn)) { ++ ++ old_tn = tn; ++ tn = halve(t, tn); ++ if (IS_ERR(tn)) { ++ tn = old_tn; ++#ifdef CONFIG_IP_FIB_TRIE_STATS ++ this_cpu_inc(t->stats->resize_node_skipped); ++#endif ++ break; ++ } ++ } ++ ++ ++ /* Only one child remains */ ++ if (tn->empty_children == (tnode_child_length(tn) - 1)) { ++ unsigned long i; ++one_child: ++ for (i = tnode_child_length(tn); !n && i;) ++ n = tnode_get_child(tn, --i); ++no_children: ++ /* compress one level */ ++ node_set_parent(n, NULL); ++ tnode_free_safe(tn); ++ return n; ++ } ++ return tn; ++} ++ + /* readside must use rcu_read_lock currently dump routines + via get_fa_head and dump */ + diff --git a/target/linux/generic/patches-3.18/080-13-fib_trie-Add-functions-should_inflate-and-should_hal.patch b/target/linux/generic/patches-3.18/080-13-fib_trie-Add-functions-should_inflate-and-should_hal.patch new file mode 100644 index 0000000..c01d57a --- /dev/null +++ b/target/linux/generic/patches-3.18/080-13-fib_trie-Add-functions-should_inflate-and-should_hal.patch @@ -0,0 +1,250 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:37 -0800 +Subject: [PATCH] fib_trie: Add functions should_inflate and should_halve + +This change pulls the logic for if we should inflate/halve the nodes out +into separate functions. It also addresses what I believe is a bug where 1 +full node is all that is needed to keep a node from ever being halved. + +Simple script to reproduce the issue: + modprobe dummy; ifconfig dummy0 up + for i in `seq 0 255`; do ifconfig dummy0:$i 10.0.${i}.1/24 up; done + ifconfig dummy0:256 10.0.255.33/16 up + for i in `seq 0 254`; do ifconfig dummy0:$i down; done + +Results from /proc/net/fib_triestat +Before: + Local: + Aver depth: 3.00 + Max depth: 4 + Leaves: 17 + Prefixes: 18 + Internal nodes: 11 + 1: 8 2: 2 10: 1 + Pointers: 1048 + Null ptrs: 1021 + Total size: 11 kB +After: + Local: + Aver depth: 3.41 + Max depth: 5 + Leaves: 17 + Prefixes: 18 + Internal nodes: 12 + 1: 8 2: 3 3: 1 + Pointers: 36 + Null ptrs: 8 + Total size: 3 kB + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -647,12 +647,94 @@ nomem: + return ERR_PTR(-ENOMEM); + } + ++/* From "Implementing a dynamic compressed trie" by Stefan Nilsson of ++ * the Helsinki University of Technology and Matti Tikkanen of Nokia ++ * Telecommunications, page 6: ++ * "A node is doubled if the ratio of non-empty children to all ++ * children in the *doubled* node is at least 'high'." ++ * ++ * 'high' in this instance is the variable 'inflate_threshold'. It ++ * is expressed as a percentage, so we multiply it with ++ * tnode_child_length() and instead of multiplying by 2 (since the ++ * child array will be doubled by inflate()) and multiplying ++ * the left-hand side by 100 (to handle the percentage thing) we ++ * multiply the left-hand side by 50. ++ * ++ * The left-hand side may look a bit weird: tnode_child_length(tn) ++ * - tn->empty_children is of course the number of non-null children ++ * in the current node. tn->full_children is the number of "full" ++ * children, that is non-null tnodes with a skip value of 0. ++ * All of those will be doubled in the resulting inflated tnode, so ++ * we just count them one extra time here. ++ * ++ * A clearer way to write this would be: ++ * ++ * to_be_doubled = tn->full_children; ++ * not_to_be_doubled = tnode_child_length(tn) - tn->empty_children - ++ * tn->full_children; ++ * ++ * new_child_length = tnode_child_length(tn) * 2; ++ * ++ * new_fill_factor = 100 * (not_to_be_doubled + 2*to_be_doubled) / ++ * new_child_length; ++ * if (new_fill_factor >= inflate_threshold) ++ * ++ * ...and so on, tho it would mess up the while () loop. ++ * ++ * anyway, ++ * 100 * (not_to_be_doubled + 2*to_be_doubled) / new_child_length >= ++ * inflate_threshold ++ * ++ * avoid a division: ++ * 100 * (not_to_be_doubled + 2*to_be_doubled) >= ++ * inflate_threshold * new_child_length ++ * ++ * expand not_to_be_doubled and to_be_doubled, and shorten: ++ * 100 * (tnode_child_length(tn) - tn->empty_children + ++ * tn->full_children) >= inflate_threshold * new_child_length ++ * ++ * expand new_child_length: ++ * 100 * (tnode_child_length(tn) - tn->empty_children + ++ * tn->full_children) >= ++ * inflate_threshold * tnode_child_length(tn) * 2 ++ * ++ * shorten again: ++ * 50 * (tn->full_children + tnode_child_length(tn) - ++ * tn->empty_children) >= inflate_threshold * ++ * tnode_child_length(tn) ++ * ++ */ ++static bool should_inflate(const struct tnode *tn) ++{ ++ unsigned long used = tnode_child_length(tn); ++ unsigned long threshold = used; ++ ++ /* Keep root node larger */ ++ threshold *= node_parent(tn) ? inflate_threshold : ++ inflate_threshold_root; ++ used += tn->full_children; ++ used -= tn->empty_children; ++ ++ return tn->pos && ((50 * used) >= threshold); ++} ++ ++static bool should_halve(const struct tnode *tn) ++{ ++ unsigned long used = tnode_child_length(tn); ++ unsigned long threshold = used; ++ ++ /* Keep root node larger */ ++ threshold *= node_parent(tn) ? halve_threshold : ++ halve_threshold_root; ++ used -= tn->empty_children; ++ ++ return (tn->bits > 1) && ((100 * used) < threshold); ++} ++ + #define MAX_WORK 10 + static struct tnode *resize(struct trie *t, struct tnode *tn) + { + struct tnode *old_tn, *n = NULL; +- int inflate_threshold_use; +- int halve_threshold_use; + int max_work; + + if (!tn) +@@ -668,86 +750,12 @@ static struct tnode *resize(struct trie + /* One child */ + if (tn->empty_children == (tnode_child_length(tn) - 1)) + goto one_child; +- /* +- * Double as long as the resulting node has a number of +- * nonempty nodes that are above the threshold. +- */ + +- /* +- * From "Implementing a dynamic compressed trie" by Stefan Nilsson of +- * the Helsinki University of Technology and Matti Tikkanen of Nokia +- * Telecommunications, page 6: +- * "A node is doubled if the ratio of non-empty children to all +- * children in the *doubled* node is at least 'high'." +- * +- * 'high' in this instance is the variable 'inflate_threshold'. It +- * is expressed as a percentage, so we multiply it with +- * tnode_child_length() and instead of multiplying by 2 (since the +- * child array will be doubled by inflate()) and multiplying +- * the left-hand side by 100 (to handle the percentage thing) we +- * multiply the left-hand side by 50. +- * +- * The left-hand side may look a bit weird: tnode_child_length(tn) +- * - tn->empty_children is of course the number of non-null children +- * in the current node. tn->full_children is the number of "full" +- * children, that is non-null tnodes with a skip value of 0. +- * All of those will be doubled in the resulting inflated tnode, so +- * we just count them one extra time here. +- * +- * A clearer way to write this would be: +- * +- * to_be_doubled = tn->full_children; +- * not_to_be_doubled = tnode_child_length(tn) - tn->empty_children - +- * tn->full_children; +- * +- * new_child_length = tnode_child_length(tn) * 2; +- * +- * new_fill_factor = 100 * (not_to_be_doubled + 2*to_be_doubled) / +- * new_child_length; +- * if (new_fill_factor >= inflate_threshold) +- * +- * ...and so on, tho it would mess up the while () loop. +- * +- * anyway, +- * 100 * (not_to_be_doubled + 2*to_be_doubled) / new_child_length >= +- * inflate_threshold +- * +- * avoid a division: +- * 100 * (not_to_be_doubled + 2*to_be_doubled) >= +- * inflate_threshold * new_child_length +- * +- * expand not_to_be_doubled and to_be_doubled, and shorten: +- * 100 * (tnode_child_length(tn) - tn->empty_children + +- * tn->full_children) >= inflate_threshold * new_child_length +- * +- * expand new_child_length: +- * 100 * (tnode_child_length(tn) - tn->empty_children + +- * tn->full_children) >= +- * inflate_threshold * tnode_child_length(tn) * 2 +- * +- * shorten again: +- * 50 * (tn->full_children + tnode_child_length(tn) - +- * tn->empty_children) >= inflate_threshold * +- * tnode_child_length(tn) +- * ++ /* Double as long as the resulting node has a number of ++ * nonempty nodes that are above the threshold. + */ +- +- /* Keep root node larger */ +- +- if (!node_parent(tn)) { +- inflate_threshold_use = inflate_threshold_root; +- halve_threshold_use = halve_threshold_root; +- } else { +- inflate_threshold_use = inflate_threshold; +- halve_threshold_use = halve_threshold; +- } +- + max_work = MAX_WORK; +- while ((tn->full_children > 0 && max_work-- && +- 50 * (tn->full_children + tnode_child_length(tn) +- - tn->empty_children) +- >= inflate_threshold_use * tnode_child_length(tn))) { +- ++ while (should_inflate(tn) && max_work--) { + old_tn = tn; + tn = inflate(t, tn); + +@@ -764,16 +772,11 @@ static struct tnode *resize(struct trie + if (max_work != MAX_WORK) + return tn; + +- /* +- * Halve as long as the number of empty children in this ++ /* Halve as long as the number of empty children in this + * node is above threshold. + */ +- + max_work = MAX_WORK; +- while (tn->bits > 1 && max_work-- && +- 100 * (tnode_child_length(tn) - tn->empty_children) < +- halve_threshold_use * tnode_child_length(tn)) { +- ++ while (should_halve(tn) && max_work--) { + old_tn = tn; + tn = halve(t, tn); + if (IS_ERR(tn)) { diff --git a/target/linux/generic/patches-3.18/080-14-fib_trie-Push-assignment-of-child-to-parent-down-int.patch b/target/linux/generic/patches-3.18/080-14-fib_trie-Push-assignment-of-child-to-parent-down-int.patch new file mode 100644 index 0000000..8f26e32 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-14-fib_trie-Push-assignment-of-child-to-parent-down-int.patch @@ -0,0 +1,336 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:43 -0800 +Subject: [PATCH] fib_trie: Push assignment of child to parent down into + inflate/halve + +This change makes it so that the assignment of the tnode to the parent is +handled directly within whatever function is currently handling the node be +it inflate, halve, or resize. By doing this we can avoid some of the need +to set NULL pointers in the tree while we are resizing the subnodes. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -146,9 +146,7 @@ struct trie { + #endif + }; + +-static void tnode_put_child_reorg(struct tnode *tn, unsigned long i, +- struct tnode *n, int wasfull); +-static struct tnode *resize(struct trie *t, struct tnode *tn); ++static void resize(struct trie *t, struct tnode *tn); + /* tnodes to free after resize(); protected by RTNL */ + static struct callback_head *tnode_free_head; + static size_t tnode_free_size; +@@ -396,22 +394,13 @@ static inline int tnode_full(const struc + return n && ((n->pos + n->bits) == tn->pos) && IS_TNODE(n); + } + +-static inline void put_child(struct tnode *tn, unsigned long i, +- struct tnode *n) +-{ +- tnode_put_child_reorg(tn, i, n, -1); +-} +- +- /* +- * Add a child at position i overwriting the old value. +- * Update the value of full_children and empty_children. +- */ +- +-static void tnode_put_child_reorg(struct tnode *tn, unsigned long i, +- struct tnode *n, int wasfull) ++/* Add a child at position i overwriting the old value. ++ * Update the value of full_children and empty_children. ++ */ ++static void put_child(struct tnode *tn, unsigned long i, struct tnode *n) + { + struct tnode *chi = rtnl_dereference(tn->child[i]); +- int isfull; ++ int isfull, wasfull; + + BUG_ON(i >= tnode_child_length(tn)); + +@@ -422,10 +411,9 @@ static void tnode_put_child_reorg(struct + tn->empty_children--; + + /* update fullChildren */ +- if (wasfull == -1) +- wasfull = tnode_full(tn, chi); +- ++ wasfull = tnode_full(tn, chi); + isfull = tnode_full(tn, n); ++ + if (wasfull && !isfull) + tn->full_children--; + else if (!wasfull && isfull) +@@ -458,9 +446,10 @@ static void tnode_clean_free(struct tnod + node_free(tn); + } + +-static struct tnode *inflate(struct trie *t, struct tnode *oldtnode) ++static int inflate(struct trie *t, struct tnode *oldtnode) + { + unsigned long olen = tnode_child_length(oldtnode); ++ struct tnode *tp = node_parent(oldtnode); + struct tnode *tn; + unsigned long i; + t_key m; +@@ -468,9 +457,8 @@ static struct tnode *inflate(struct trie + pr_debug("In inflate\n"); + + tn = tnode_new(oldtnode->key, oldtnode->pos - 1, oldtnode->bits + 1); +- + if (!tn) +- return ERR_PTR(-ENOMEM); ++ return -ENOMEM; + + /* + * Preallocate and store tnodes before the actual work so we +@@ -564,30 +552,36 @@ static struct tnode *inflate(struct trie + put_child(left, j, rtnl_dereference(inode->child[j])); + put_child(right, j, rtnl_dereference(inode->child[j + size])); + } +- put_child(tn, 2*i, resize(t, left)); +- put_child(tn, 2*i+1, resize(t, right)); ++ ++ put_child(tn, 2 * i, left); ++ put_child(tn, 2 * i + 1, right); + + tnode_free_safe(inode); ++ ++ resize(t, left); ++ resize(t, right); + } ++ ++ put_child_root(tp, t, tn->key, tn); + tnode_free_safe(oldtnode); +- return tn; ++ return 0; + nomem: + tnode_clean_free(tn); +- return ERR_PTR(-ENOMEM); ++ return -ENOMEM; + } + +-static struct tnode *halve(struct trie *t, struct tnode *oldtnode) ++static int halve(struct trie *t, struct tnode *oldtnode) + { + unsigned long olen = tnode_child_length(oldtnode); ++ struct tnode *tp = node_parent(oldtnode); + struct tnode *tn, *left, *right; + int i; + + pr_debug("In halve\n"); + + tn = tnode_new(oldtnode->key, oldtnode->pos + 1, oldtnode->bits - 1); +- + if (!tn) +- return ERR_PTR(-ENOMEM); ++ return -ENOMEM; + + /* + * Preallocate and store tnodes before the actual work so we +@@ -606,8 +600,10 @@ static struct tnode *halve(struct trie * + + newn = tnode_new(left->key, oldtnode->pos, 1); + +- if (!newn) +- goto nomem; ++ if (!newn) { ++ tnode_clean_free(tn); ++ return -ENOMEM; ++ } + + put_child(tn, i/2, newn); + } +@@ -635,16 +631,18 @@ static struct tnode *halve(struct trie * + + /* Two nonempty children */ + newBinNode = tnode_get_child(tn, i/2); +- put_child(tn, i/2, NULL); + put_child(newBinNode, 0, left); + put_child(newBinNode, 1, right); +- put_child(tn, i/2, resize(t, newBinNode)); ++ ++ put_child(tn, i / 2, newBinNode); ++ ++ resize(t, newBinNode); + } ++ ++ put_child_root(tp, t, tn->key, tn); + tnode_free_safe(oldtnode); +- return tn; +-nomem: +- tnode_clean_free(tn); +- return ERR_PTR(-ENOMEM); ++ ++ return 0; + } + + /* From "Implementing a dynamic compressed trie" by Stefan Nilsson of +@@ -704,45 +702,48 @@ nomem: + * tnode_child_length(tn) + * + */ +-static bool should_inflate(const struct tnode *tn) ++static bool should_inflate(const struct tnode *tp, const struct tnode *tn) + { + unsigned long used = tnode_child_length(tn); + unsigned long threshold = used; + + /* Keep root node larger */ +- threshold *= node_parent(tn) ? inflate_threshold : +- inflate_threshold_root; ++ threshold *= tp ? inflate_threshold : inflate_threshold_root; + used += tn->full_children; + used -= tn->empty_children; + + return tn->pos && ((50 * used) >= threshold); + } + +-static bool should_halve(const struct tnode *tn) ++static bool should_halve(const struct tnode *tp, const struct tnode *tn) + { + unsigned long used = tnode_child_length(tn); + unsigned long threshold = used; + + /* Keep root node larger */ +- threshold *= node_parent(tn) ? halve_threshold : +- halve_threshold_root; ++ threshold *= tp ? halve_threshold : halve_threshold_root; + used -= tn->empty_children; + + return (tn->bits > 1) && ((100 * used) < threshold); + } + + #define MAX_WORK 10 +-static struct tnode *resize(struct trie *t, struct tnode *tn) ++static void resize(struct trie *t, struct tnode *tn) + { +- struct tnode *old_tn, *n = NULL; ++ struct tnode *tp = node_parent(tn), *n = NULL; ++ struct tnode __rcu **cptr; + int max_work; + +- if (!tn) +- return NULL; +- + pr_debug("In tnode_resize %p inflate_threshold=%d threshold=%d\n", + tn, inflate_threshold, halve_threshold); + ++ /* track the tnode via the pointer from the parent instead of ++ * doing it ourselves. This way we can let RCU fully do its ++ * thing without us interfering ++ */ ++ cptr = tp ? &tp->child[get_index(tn->key, tp)] : &t->trie; ++ BUG_ON(tn != rtnl_dereference(*cptr)); ++ + /* No children */ + if (tn->empty_children > (tnode_child_length(tn) - 1)) + goto no_children; +@@ -755,39 +756,35 @@ static struct tnode *resize(struct trie + * nonempty nodes that are above the threshold. + */ + max_work = MAX_WORK; +- while (should_inflate(tn) && max_work--) { +- old_tn = tn; +- tn = inflate(t, tn); +- +- if (IS_ERR(tn)) { +- tn = old_tn; ++ while (should_inflate(tp, tn) && max_work--) { ++ if (inflate(t, tn)) { + #ifdef CONFIG_IP_FIB_TRIE_STATS + this_cpu_inc(t->stats->resize_node_skipped); + #endif + break; + } ++ ++ tn = rtnl_dereference(*cptr); + } + + /* Return if at least one inflate is run */ + if (max_work != MAX_WORK) +- return tn; ++ return; + + /* Halve as long as the number of empty children in this + * node is above threshold. + */ + max_work = MAX_WORK; +- while (should_halve(tn) && max_work--) { +- old_tn = tn; +- tn = halve(t, tn); +- if (IS_ERR(tn)) { +- tn = old_tn; ++ while (should_halve(tp, tn) && max_work--) { ++ if (halve(t, tn)) { + #ifdef CONFIG_IP_FIB_TRIE_STATS + this_cpu_inc(t->stats->resize_node_skipped); + #endif + break; + } +- } + ++ tn = rtnl_dereference(*cptr); ++ } + + /* Only one child remains */ + if (tn->empty_children == (tnode_child_length(tn) - 1)) { +@@ -797,11 +794,12 @@ one_child: + n = tnode_get_child(tn, --i); + no_children: + /* compress one level */ +- node_set_parent(n, NULL); ++ put_child_root(tp, t, tn->key, n); ++ node_set_parent(n, tp); ++ ++ /* drop dead node */ + tnode_free_safe(tn); +- return n; + } +- return tn; + } + + /* readside must use rcu_read_lock currently dump routines +@@ -882,34 +880,19 @@ static struct tnode *fib_find_node(struc + + static void trie_rebalance(struct trie *t, struct tnode *tn) + { +- int wasfull; +- t_key cindex, key; + struct tnode *tp; + +- key = tn->key; +- +- while (tn != NULL && (tp = node_parent(tn)) != NULL) { +- cindex = get_index(key, tp); +- wasfull = tnode_full(tp, tnode_get_child(tp, cindex)); +- tn = resize(t, tn); +- +- tnode_put_child_reorg(tp, cindex, tn, wasfull); +- +- tp = node_parent(tn); +- if (!tp) +- rcu_assign_pointer(t->trie, tn); ++ while ((tp = node_parent(tn)) != NULL) { ++ resize(t, tn); + + tnode_free_flush(); +- if (!tp) +- break; + tn = tp; + } + + /* Handle last (top) tnode */ + if (IS_TNODE(tn)) +- tn = resize(t, tn); ++ resize(t, tn); + +- rcu_assign_pointer(t->trie, tn); + tnode_free_flush(); + } + diff --git a/target/linux/generic/patches-3.18/080-15-fib_trie-Push-tnode-flushing-down-to-inflate-halve.patch b/target/linux/generic/patches-3.18/080-15-fib_trie-Push-tnode-flushing-down-to-inflate-halve.patch new file mode 100644 index 0000000..51178a0 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-15-fib_trie-Push-tnode-flushing-down-to-inflate-halve.patch @@ -0,0 +1,237 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:49 -0800 +Subject: [PATCH] fib_trie: Push tnode flushing down to inflate/halve + +This change pushes the tnode freeing down into the inflate and halve +functions. It makes more sense here as we have a better grasp of what is +going on and when a given cluster of nodes is ready to be freed. + +I believe this may address a bug in the freeing logic as well. For some +reason if the freelist got to a certain size we would call +synchronize_rcu(). I'm assuming that what they meant to do is call +synchronize_rcu() after they had handed off that much memory via +call_rcu(). As such that is what I have updated the behavior to be. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -147,8 +147,6 @@ struct trie { + }; + + static void resize(struct trie *t, struct tnode *tn); +-/* tnodes to free after resize(); protected by RTNL */ +-static struct callback_head *tnode_free_head; + static size_t tnode_free_size; + + /* +@@ -307,32 +305,6 @@ static struct tnode *tnode_alloc(size_t + return vzalloc(size); + } + +-static void tnode_free_safe(struct tnode *tn) +-{ +- BUG_ON(IS_LEAF(tn)); +- tn->rcu.next = tnode_free_head; +- tnode_free_head = &tn->rcu; +-} +- +-static void tnode_free_flush(void) +-{ +- struct callback_head *head; +- +- while ((head = tnode_free_head)) { +- struct tnode *tn = container_of(head, struct tnode, rcu); +- +- tnode_free_head = head->next; +- tnode_free_size += offsetof(struct tnode, child[1 << tn->bits]); +- +- node_free(tn); +- } +- +- if (tnode_free_size >= PAGE_SIZE * sync_pages) { +- tnode_free_size = 0; +- synchronize_rcu(); +- } +-} +- + static struct tnode *leaf_new(t_key key) + { + struct tnode *l = kmem_cache_alloc(trie_leaf_kmem, GFP_KERNEL); +@@ -433,17 +405,33 @@ static void put_child_root(struct tnode + rcu_assign_pointer(t->trie, n); + } + +-static void tnode_clean_free(struct tnode *tn) ++static inline void tnode_free_init(struct tnode *tn) + { +- struct tnode *tofree; +- unsigned long i; ++ tn->rcu.next = NULL; ++} ++ ++static inline void tnode_free_append(struct tnode *tn, struct tnode *n) ++{ ++ n->rcu.next = tn->rcu.next; ++ tn->rcu.next = &n->rcu; ++} + +- for (i = 0; i < tnode_child_length(tn); i++) { +- tofree = tnode_get_child(tn, i); +- if (tofree) +- node_free(tofree); ++static void tnode_free(struct tnode *tn) ++{ ++ struct callback_head *head = &tn->rcu; ++ ++ while (head) { ++ head = head->next; ++ tnode_free_size += offsetof(struct tnode, child[1 << tn->bits]); ++ node_free(tn); ++ ++ tn = container_of(head, struct tnode, rcu); ++ } ++ ++ if (tnode_free_size >= PAGE_SIZE * sync_pages) { ++ tnode_free_size = 0; ++ synchronize_rcu(); + } +- node_free(tn); + } + + static int inflate(struct trie *t, struct tnode *oldtnode) +@@ -476,20 +464,23 @@ static int inflate(struct trie *t, struc + inode->bits - 1); + if (!left) + goto nomem; ++ tnode_free_append(tn, left); + + right = tnode_new(inode->key | m, inode->pos, + inode->bits - 1); + +- if (!right) { +- node_free(left); ++ if (!right) + goto nomem; +- } ++ tnode_free_append(tn, right); + + put_child(tn, 2*i, left); + put_child(tn, 2*i+1, right); + } + } + ++ /* prepare oldtnode to be freed */ ++ tnode_free_init(oldtnode); ++ + for (i = 0; i < olen; i++) { + struct tnode *inode = tnode_get_child(oldtnode, i); + struct tnode *left, *right; +@@ -505,12 +496,13 @@ static int inflate(struct trie *t, struc + continue; + } + ++ /* drop the node in the old tnode free list */ ++ tnode_free_append(oldtnode, inode); ++ + /* An internal node with two children */ + if (inode->bits == 1) { + put_child(tn, 2*i, rtnl_dereference(inode->child[0])); + put_child(tn, 2*i+1, rtnl_dereference(inode->child[1])); +- +- tnode_free_safe(inode); + continue; + } + +@@ -556,17 +548,19 @@ static int inflate(struct trie *t, struc + put_child(tn, 2 * i, left); + put_child(tn, 2 * i + 1, right); + +- tnode_free_safe(inode); +- ++ /* resize child nodes */ + resize(t, left); + resize(t, right); + } + + put_child_root(tp, t, tn->key, tn); +- tnode_free_safe(oldtnode); ++ ++ /* we completed without error, prepare to free old node */ ++ tnode_free(oldtnode); + return 0; + nomem: +- tnode_clean_free(tn); ++ /* all pointers should be clean so we are done */ ++ tnode_free(tn); + return -ENOMEM; + } + +@@ -599,17 +593,20 @@ static int halve(struct trie *t, struct + struct tnode *newn; + + newn = tnode_new(left->key, oldtnode->pos, 1); +- + if (!newn) { +- tnode_clean_free(tn); ++ tnode_free(tn); + return -ENOMEM; + } ++ tnode_free_append(tn, newn); + + put_child(tn, i/2, newn); + } + + } + ++ /* prepare oldtnode to be freed */ ++ tnode_free_init(oldtnode); ++ + for (i = 0; i < olen; i += 2) { + struct tnode *newBinNode; + +@@ -636,11 +633,14 @@ static int halve(struct trie *t, struct + + put_child(tn, i / 2, newBinNode); + ++ /* resize child node */ + resize(t, newBinNode); + } + + put_child_root(tp, t, tn->key, tn); +- tnode_free_safe(oldtnode); ++ ++ /* all pointers should be clean so we are done */ ++ tnode_free(oldtnode); + + return 0; + } +@@ -798,7 +798,8 @@ no_children: + node_set_parent(n, tp); + + /* drop dead node */ +- tnode_free_safe(tn); ++ tnode_free_init(tn); ++ tnode_free(tn); + } + } + +@@ -884,16 +885,12 @@ static void trie_rebalance(struct trie * + + while ((tp = node_parent(tn)) != NULL) { + resize(t, tn); +- +- tnode_free_flush(); + tn = tp; + } + + /* Handle last (top) tnode */ + if (IS_TNODE(tn)) + resize(t, tn); +- +- tnode_free_flush(); + } + + /* only used from updater-side */ diff --git a/target/linux/generic/patches-3.18/080-16-fib_trie-inflate-halve-nodes-in-a-more-RCU-friendly-.patch b/target/linux/generic/patches-3.18/080-16-fib_trie-inflate-halve-nodes-in-a-more-RCU-friendly-.patch new file mode 100644 index 0000000..d6b600c --- /dev/null +++ b/target/linux/generic/patches-3.18/080-16-fib_trie-inflate-halve-nodes-in-a-more-RCU-friendly-.patch @@ -0,0 +1,345 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:56:55 -0800 +Subject: [PATCH] fib_trie: inflate/halve nodes in a more RCU friendly + way + +This change pulls the node_set_parent functionality out of put_child_reorg +and instead leaves that to the function to take care of as well. By doing +this we can fully construct the new cluster of tnodes and all of the +pointers out of it before we start routing pointers into it. + +I am suspecting this will likely fix some concurency issues though I don't +have a good test to show as such. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -391,8 +391,6 @@ static void put_child(struct tnode *tn, + else if (!wasfull && isfull) + tn->full_children++; + +- node_set_parent(n, tn); +- + rcu_assign_pointer(tn->child[i], n); + } + +@@ -436,10 +434,8 @@ static void tnode_free(struct tnode *tn) + + static int inflate(struct trie *t, struct tnode *oldtnode) + { +- unsigned long olen = tnode_child_length(oldtnode); +- struct tnode *tp = node_parent(oldtnode); +- struct tnode *tn; +- unsigned long i; ++ struct tnode *inode, *node0, *node1, *tn, *tp; ++ unsigned long i, j, k; + t_key m; + + pr_debug("In inflate\n"); +@@ -448,43 +444,13 @@ static int inflate(struct trie *t, struc + if (!tn) + return -ENOMEM; + +- /* +- * Preallocate and store tnodes before the actual work so we +- * don't get into an inconsistent state if memory allocation +- * fails. In case of failure we return the oldnode and inflate +- * of tnode is ignored. ++ /* Assemble all of the pointers in our cluster, in this case that ++ * represents all of the pointers out of our allocated nodes that ++ * point to existing tnodes and the links between our allocated ++ * nodes. + */ +- for (i = 0, m = 1u << tn->pos; i < olen; i++) { +- struct tnode *inode = tnode_get_child(oldtnode, i); +- +- if (tnode_full(oldtnode, inode) && (inode->bits > 1)) { +- struct tnode *left, *right; +- +- left = tnode_new(inode->key & ~m, inode->pos, +- inode->bits - 1); +- if (!left) +- goto nomem; +- tnode_free_append(tn, left); +- +- right = tnode_new(inode->key | m, inode->pos, +- inode->bits - 1); +- +- if (!right) +- goto nomem; +- tnode_free_append(tn, right); +- +- put_child(tn, 2*i, left); +- put_child(tn, 2*i+1, right); +- } +- } +- +- /* prepare oldtnode to be freed */ +- tnode_free_init(oldtnode); +- +- for (i = 0; i < olen; i++) { +- struct tnode *inode = tnode_get_child(oldtnode, i); +- struct tnode *left, *right; +- unsigned long size, j; ++ for (i = tnode_child_length(oldtnode), m = 1u << tn->pos; i;) { ++ inode = tnode_get_child(oldtnode, --i); + + /* An empty child */ + if (inode == NULL) +@@ -496,65 +462,99 @@ static int inflate(struct trie *t, struc + continue; + } + +- /* drop the node in the old tnode free list */ +- tnode_free_append(oldtnode, inode); +- + /* An internal node with two children */ + if (inode->bits == 1) { +- put_child(tn, 2*i, rtnl_dereference(inode->child[0])); +- put_child(tn, 2*i+1, rtnl_dereference(inode->child[1])); ++ put_child(tn, 2 * i + 1, tnode_get_child(inode, 1)); ++ put_child(tn, 2 * i, tnode_get_child(inode, 0)); + continue; + } + +- /* An internal node with more than two children */ +- + /* We will replace this node 'inode' with two new +- * ones, 'left' and 'right', each with half of the ++ * ones, 'node0' and 'node1', each with half of the + * original children. The two new nodes will have + * a position one bit further down the key and this + * means that the "significant" part of their keys + * (see the discussion near the top of this file) + * will differ by one bit, which will be "0" in +- * left's key and "1" in right's key. Since we are ++ * node0's key and "1" in node1's key. Since we are + * moving the key position by one step, the bit that + * we are moving away from - the bit at position +- * (inode->pos) - is the one that will differ between +- * left and right. So... we synthesize that bit in the +- * two new keys. +- * The mask 'm' below will be a single "one" bit at +- * the position (inode->pos) ++ * (tn->pos) - is the one that will differ between ++ * node0 and node1. So... we synthesize that bit in the ++ * two new keys. + */ ++ node1 = tnode_new(inode->key | m, inode->pos, inode->bits - 1); ++ if (!node1) ++ goto nomem; ++ tnode_free_append(tn, node1); ++ ++ node0 = tnode_new(inode->key & ~m, inode->pos, inode->bits - 1); ++ if (!node0) ++ goto nomem; ++ tnode_free_append(tn, node0); ++ ++ /* populate child pointers in new nodes */ ++ for (k = tnode_child_length(inode), j = k / 2; j;) { ++ put_child(node1, --j, tnode_get_child(inode, --k)); ++ put_child(node0, j, tnode_get_child(inode, j)); ++ put_child(node1, --j, tnode_get_child(inode, --k)); ++ put_child(node0, j, tnode_get_child(inode, j)); ++ } ++ ++ /* link new nodes to parent */ ++ NODE_INIT_PARENT(node1, tn); ++ NODE_INIT_PARENT(node0, tn); ++ ++ /* link parent to nodes */ ++ put_child(tn, 2 * i + 1, node1); ++ put_child(tn, 2 * i, node0); ++ } ++ ++ /* setup the parent pointer into and out of this node */ ++ tp = node_parent(oldtnode); ++ NODE_INIT_PARENT(tn, tp); ++ put_child_root(tp, t, tn->key, tn); + +- /* Use the old key, but set the new significant +- * bit to zero. +- */ ++ /* prepare oldtnode to be freed */ ++ tnode_free_init(oldtnode); + +- left = tnode_get_child(tn, 2*i); +- put_child(tn, 2*i, NULL); ++ /* update all child nodes parent pointers to route to us */ ++ for (i = tnode_child_length(oldtnode); i;) { ++ inode = tnode_get_child(oldtnode, --i); + +- BUG_ON(!left); ++ /* A leaf or an internal node with skipped bits */ ++ if (!tnode_full(oldtnode, inode)) { ++ node_set_parent(inode, tn); ++ continue; ++ } + +- right = tnode_get_child(tn, 2*i+1); +- put_child(tn, 2*i+1, NULL); ++ /* drop the node in the old tnode free list */ ++ tnode_free_append(oldtnode, inode); + +- BUG_ON(!right); ++ /* fetch new nodes */ ++ node1 = tnode_get_child(tn, 2 * i + 1); ++ node0 = tnode_get_child(tn, 2 * i); + +- size = tnode_child_length(left); +- for (j = 0; j < size; j++) { +- put_child(left, j, rtnl_dereference(inode->child[j])); +- put_child(right, j, rtnl_dereference(inode->child[j + size])); ++ /* bits == 1 then node0 and node1 represent inode's children */ ++ if (inode->bits == 1) { ++ node_set_parent(node1, tn); ++ node_set_parent(node0, tn); ++ continue; + } + +- put_child(tn, 2 * i, left); +- put_child(tn, 2 * i + 1, right); ++ /* update parent pointers in child node's children */ ++ for (k = tnode_child_length(inode), j = k / 2; j;) { ++ node_set_parent(tnode_get_child(inode, --k), node1); ++ node_set_parent(tnode_get_child(inode, --j), node0); ++ node_set_parent(tnode_get_child(inode, --k), node1); ++ node_set_parent(tnode_get_child(inode, --j), node0); ++ } + + /* resize child nodes */ +- resize(t, left); +- resize(t, right); ++ resize(t, node1); ++ resize(t, node0); + } + +- put_child_root(tp, t, tn->key, tn); +- + /* we completed without error, prepare to free old node */ + tnode_free(oldtnode); + return 0; +@@ -566,10 +566,8 @@ nomem: + + static int halve(struct trie *t, struct tnode *oldtnode) + { +- unsigned long olen = tnode_child_length(oldtnode); +- struct tnode *tp = node_parent(oldtnode); +- struct tnode *tn, *left, *right; +- int i; ++ struct tnode *tn, *tp, *inode, *node0, *node1; ++ unsigned long i; + + pr_debug("In halve\n"); + +@@ -577,68 +575,64 @@ static int halve(struct trie *t, struct + if (!tn) + return -ENOMEM; + +- /* +- * Preallocate and store tnodes before the actual work so we +- * don't get into an inconsistent state if memory allocation +- * fails. In case of failure we return the oldnode and halve +- * of tnode is ignored. ++ /* Assemble all of the pointers in our cluster, in this case that ++ * represents all of the pointers out of our allocated nodes that ++ * point to existing tnodes and the links between our allocated ++ * nodes. + */ ++ for (i = tnode_child_length(oldtnode); i;) { ++ node1 = tnode_get_child(oldtnode, --i); ++ node0 = tnode_get_child(oldtnode, --i); + +- for (i = 0; i < olen; i += 2) { +- left = tnode_get_child(oldtnode, i); +- right = tnode_get_child(oldtnode, i+1); ++ /* At least one of the children is empty */ ++ if (!node1 || !node0) { ++ put_child(tn, i / 2, node1 ? : node0); ++ continue; ++ } + + /* Two nonempty children */ +- if (left && right) { +- struct tnode *newn; +- +- newn = tnode_new(left->key, oldtnode->pos, 1); +- if (!newn) { +- tnode_free(tn); +- return -ENOMEM; +- } +- tnode_free_append(tn, newn); +- +- put_child(tn, i/2, newn); ++ inode = tnode_new(node0->key, oldtnode->pos, 1); ++ if (!inode) { ++ tnode_free(tn); ++ return -ENOMEM; + } ++ tnode_free_append(tn, inode); + ++ /* initialize pointers out of node */ ++ put_child(inode, 1, node1); ++ put_child(inode, 0, node0); ++ NODE_INIT_PARENT(inode, tn); ++ ++ /* link parent to node */ ++ put_child(tn, i / 2, inode); + } + ++ /* setup the parent pointer out of and back into this node */ ++ tp = node_parent(oldtnode); ++ NODE_INIT_PARENT(tn, tp); ++ put_child_root(tp, t, tn->key, tn); ++ + /* prepare oldtnode to be freed */ + tnode_free_init(oldtnode); + +- for (i = 0; i < olen; i += 2) { +- struct tnode *newBinNode; +- +- left = tnode_get_child(oldtnode, i); +- right = tnode_get_child(oldtnode, i+1); +- +- /* At least one of the children is empty */ +- if (left == NULL) { +- if (right == NULL) /* Both are empty */ +- continue; +- put_child(tn, i/2, right); +- continue; +- } +- +- if (right == NULL) { +- put_child(tn, i/2, left); ++ /* update all of the child parent pointers */ ++ for (i = tnode_child_length(tn); i;) { ++ inode = tnode_get_child(tn, --i); ++ ++ /* only new tnodes will be considered "full" nodes */ ++ if (!tnode_full(tn, inode)) { ++ node_set_parent(inode, tn); + continue; + } + + /* Two nonempty children */ +- newBinNode = tnode_get_child(tn, i/2); +- put_child(newBinNode, 0, left); +- put_child(newBinNode, 1, right); +- +- put_child(tn, i / 2, newBinNode); ++ node_set_parent(tnode_get_child(inode, 1), inode); ++ node_set_parent(tnode_get_child(inode, 0), inode); + + /* resize child node */ +- resize(t, newBinNode); ++ resize(t, inode); + } + +- put_child_root(tp, t, tn->key, tn); +- + /* all pointers should be clean so we are done */ + tnode_free(oldtnode); + diff --git a/target/linux/generic/patches-3.18/080-17-fib_trie-Remove-checks-for-index-tnode_child_length-.patch b/target/linux/generic/patches-3.18/080-17-fib_trie-Remove-checks-for-index-tnode_child_length-.patch new file mode 100644 index 0000000..8f7c671 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-17-fib_trie-Remove-checks-for-index-tnode_child_length-.patch @@ -0,0 +1,95 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:57:02 -0800 +Subject: [PATCH] fib_trie: Remove checks for index >= tnode_child_length + from tnode_get_child + +For some reason the compiler doesn't seem to understand that when we are in +a loop that runs from tnode_child_length - 1 to 0 we don't expect the value +of tn->bits to change. As such every call to tnode_get_child was rerunning +tnode_chile_length which ended up consuming quite a bit of space in the +resultant assembly code. + +I have gone though and verified that in all cases where tnode_get_child +is used we are either winding though a fixed loop from tnode_child_length - +1 to 0, or are in a fastpath case where we are verifying the value by +either checking for any remaining bits after shifting index by bits and +testing for leaf, or by using tnode_child_length. + +size net/ipv4/fib_trie.o +Before: + text data bss dec hex filename + 15506 376 8 15890 3e12 net/ipv4/fib_trie.o + +After: + text data bss dec hex filename + 14827 376 8 15211 3b6b net/ipv4/fib_trie.o + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -186,8 +186,6 @@ static inline unsigned long tnode_child_ + static inline struct tnode *tnode_get_child(const struct tnode *tn, + unsigned long i) + { +- BUG_ON(i >= tnode_child_length(tn)); +- + return rtnl_dereference(tn->child[i]); + } + +@@ -195,8 +193,6 @@ static inline struct tnode *tnode_get_ch + static inline struct tnode *tnode_get_child_rcu(const struct tnode *tn, + unsigned long i) + { +- BUG_ON(i >= tnode_child_length(tn)); +- + return rcu_dereference_rtnl(tn->child[i]); + } + +@@ -371,7 +367,7 @@ static inline int tnode_full(const struc + */ + static void put_child(struct tnode *tn, unsigned long i, struct tnode *n) + { +- struct tnode *chi = rtnl_dereference(tn->child[i]); ++ struct tnode *chi = tnode_get_child(tn, i); + int isfull, wasfull; + + BUG_ON(i >= tnode_child_length(tn)); +@@ -867,7 +863,7 @@ static struct tnode *fib_find_node(struc + if (IS_LEAF(n)) + break; + +- n = rcu_dereference_rtnl(n->child[index]); ++ n = tnode_get_child_rcu(n, index); + } + + return n; +@@ -934,7 +930,7 @@ static struct list_head *fib_insert_node + } + + tp = n; +- n = rcu_dereference_rtnl(n->child[index]); ++ n = tnode_get_child_rcu(n, index); + } + + l = leaf_new(key); +@@ -1215,7 +1211,7 @@ int fib_table_lookup(struct fib_table *t + cindex = index; + } + +- n = rcu_dereference(n->child[index]); ++ n = tnode_get_child_rcu(n, index); + if (unlikely(!n)) + goto backtrace; + } +@@ -1835,7 +1831,7 @@ static void trie_collect_stats(struct tr + if (n->bits < MAX_STAT_DEPTH) + s->nodesizes[n->bits]++; + +- for (i = 0; i < tnode_child_length(n); i++) { ++ for (i = tnode_child_length(n); i--;) { + if (!rcu_access_pointer(n->child[i])) + s->nullpointers++; + } diff --git a/target/linux/generic/patches-3.18/080-18-fib_trie-Add-tracking-value-for-suffix-length.patch b/target/linux/generic/patches-3.18/080-18-fib_trie-Add-tracking-value-for-suffix-length.patch new file mode 100644 index 0000000..6a4a45e --- /dev/null +++ b/target/linux/generic/patches-3.18/080-18-fib_trie-Add-tracking-value-for-suffix-length.patch @@ -0,0 +1,234 @@ +From: Alexander Duyck +Date: Wed, 31 Dec 2014 10:57:08 -0800 +Subject: [PATCH] fib_trie: Add tracking value for suffix length + +This change adds a tracking value for the maximum suffix length of all +prefixes stored in any given tnode. With this value we can determine if we +need to backtrace or not based on if the suffix is greater than the pos +value. + +By doing this we can reduce the CPU overhead for lookups in the local table +as many of the prefixes there are 32b long and have a suffix length of 0 +meaning we can immediately backtrace to the root node without needing to +test any of the nodes between it and where we ended up. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -96,6 +96,7 @@ struct tnode { + t_key key; + unsigned char bits; /* 2log(KEYLENGTH) bits needed */ + unsigned char pos; /* 2log(KEYLENGTH) bits needed */ ++ unsigned char slen; + struct tnode __rcu *parent; + struct rcu_head rcu; + union { +@@ -311,6 +312,7 @@ static struct tnode *leaf_new(t_key key) + * as the nodes are searched + */ + l->key = key; ++ l->slen = 0; + l->pos = 0; + /* set bits to 0 indicating we are not a tnode */ + l->bits = 0; +@@ -342,6 +344,7 @@ static struct tnode *tnode_new(t_key key + + if (tn) { + tn->parent = NULL; ++ tn->slen = pos; + tn->pos = pos; + tn->bits = bits; + tn->key = (shift < KEYLENGTH) ? (key >> shift) << shift : 0; +@@ -387,6 +390,9 @@ static void put_child(struct tnode *tn, + else if (!wasfull && isfull) + tn->full_children++; + ++ if (n && (tn->slen < n->slen)) ++ tn->slen = n->slen; ++ + rcu_assign_pointer(tn->child[i], n); + } + +@@ -635,6 +641,41 @@ static int halve(struct trie *t, struct + return 0; + } + ++static unsigned char update_suffix(struct tnode *tn) ++{ ++ unsigned char slen = tn->pos; ++ unsigned long stride, i; ++ ++ /* search though the list of children looking for nodes that might ++ * have a suffix greater than the one we currently have. This is ++ * why we start with a stride of 2 since a stride of 1 would ++ * represent the nodes with suffix length equal to tn->pos ++ */ ++ for (i = 0, stride = 0x2ul ; i < tnode_child_length(tn); i += stride) { ++ struct tnode *n = tnode_get_child(tn, i); ++ ++ if (!n || (n->slen <= slen)) ++ continue; ++ ++ /* update stride and slen based on new value */ ++ stride <<= (n->slen - slen); ++ slen = n->slen; ++ i &= ~(stride - 1); ++ ++ /* if slen covers all but the last bit we can stop here ++ * there will be nothing longer than that since only node ++ * 0 and 1 << (bits - 1) could have that as their suffix ++ * length. ++ */ ++ if ((slen + 1) >= (tn->pos + tn->bits)) ++ break; ++ } ++ ++ tn->slen = slen; ++ ++ return slen; ++} ++ + /* From "Implementing a dynamic compressed trie" by Stefan Nilsson of + * the Helsinki University of Technology and Matti Tikkanen of Nokia + * Telecommunications, page 6: +@@ -790,6 +831,19 @@ no_children: + /* drop dead node */ + tnode_free_init(tn); + tnode_free(tn); ++ return; ++ } ++ ++ /* Return if at least one deflate was run */ ++ if (max_work != MAX_WORK) ++ return; ++ ++ /* push the suffix length to the parent node */ ++ if (tn->slen > tn->pos) { ++ unsigned char slen = update_suffix(tn); ++ ++ if (tp && (slen > tp->slen)) ++ tp->slen = slen; + } + } + +@@ -818,8 +872,58 @@ static inline struct list_head *get_fa_h + return &li->falh; + } + +-static void insert_leaf_info(struct hlist_head *head, struct leaf_info *new) ++static void leaf_pull_suffix(struct tnode *l) ++{ ++ struct tnode *tp = node_parent(l); ++ ++ while (tp && (tp->slen > tp->pos) && (tp->slen > l->slen)) { ++ if (update_suffix(tp) > l->slen) ++ break; ++ tp = node_parent(tp); ++ } ++} ++ ++static void leaf_push_suffix(struct tnode *l) ++{ ++ struct tnode *tn = node_parent(l); ++ ++ /* if this is a new leaf then tn will be NULL and we can sort ++ * out parent suffix lengths as a part of trie_rebalance ++ */ ++ while (tn && (tn->slen < l->slen)) { ++ tn->slen = l->slen; ++ tn = node_parent(tn); ++ } ++} ++ ++static void remove_leaf_info(struct tnode *l, struct leaf_info *old) ++{ ++ struct hlist_node *prev; ++ ++ /* record the location of the pointer to this object */ ++ prev = rtnl_dereference(hlist_pprev_rcu(&old->hlist)); ++ ++ /* remove the leaf info from the list */ ++ hlist_del_rcu(&old->hlist); ++ ++ /* if we emptied the list this leaf will be freed and we can sort ++ * out parent suffix lengths as a part of trie_rebalance ++ */ ++ if (hlist_empty(&l->list)) ++ return; ++ ++ /* if we removed the tail then we need to update slen */ ++ if (!rcu_access_pointer(hlist_next_rcu(prev))) { ++ struct leaf_info *li = hlist_entry(prev, typeof(*li), hlist); ++ ++ l->slen = KEYLENGTH - li->plen; ++ leaf_pull_suffix(l); ++ } ++} ++ ++static void insert_leaf_info(struct tnode *l, struct leaf_info *new) + { ++ struct hlist_head *head = &l->list; + struct leaf_info *li = NULL, *last = NULL; + + if (hlist_empty(head)) { +@@ -836,6 +940,12 @@ static void insert_leaf_info(struct hlis + else + hlist_add_before_rcu(&new->hlist, &li->hlist); + } ++ ++ /* if we added to the tail node then we need to update slen */ ++ if (!rcu_access_pointer(hlist_next_rcu(&new->hlist))) { ++ l->slen = KEYLENGTH - new->plen; ++ leaf_push_suffix(l); ++ } + } + + /* rcu_read_lock needs to be hold by caller from readside */ +@@ -925,7 +1035,7 @@ static struct list_head *fib_insert_node + /* we have found a leaf. Prefixes have already been compared */ + if (IS_LEAF(n)) { + /* Case 1: n is a leaf, and prefixes match*/ +- insert_leaf_info(&n->list, li); ++ insert_leaf_info(n, li); + return fa_head; + } + +@@ -939,7 +1049,7 @@ static struct list_head *fib_insert_node + return NULL; + } + +- insert_leaf_info(&l->list, li); ++ insert_leaf_info(l, li); + + /* Case 2: n is a LEAF or a TNODE and the key doesn't match. + * +@@ -1206,7 +1316,7 @@ int fib_table_lookup(struct fib_table *t + /* only record pn and cindex if we are going to be chopping + * bits later. Otherwise we are just wasting cycles. + */ +- if (index) { ++ if (n->slen > n->pos) { + pn = n; + cindex = index; + } +@@ -1225,7 +1335,7 @@ int fib_table_lookup(struct fib_table *t + * between the key and the prefix exist in the region of + * the lsb and higher in the prefix. + */ +- if (unlikely(prefix_mismatch(key, n))) ++ if (unlikely(prefix_mismatch(key, n)) || (n->slen == n->pos)) + goto backtrace; + + /* exit out and process leaf */ +@@ -1425,7 +1535,7 @@ int fib_table_delete(struct fib_table *t + tb->tb_num_default--; + + if (list_empty(fa_head)) { +- hlist_del_rcu(&li->hlist); ++ remove_leaf_info(l, li); + free_leaf_info(li); + } + diff --git a/target/linux/generic/patches-3.18/080-19-fib_trie-Use-index-0ul-n-bits-instead-of-index-n-bit.patch b/target/linux/generic/patches-3.18/080-19-fib_trie-Use-index-0ul-n-bits-instead-of-index-n-bit.patch new file mode 100644 index 0000000..d5fc112 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-19-fib_trie-Use-index-0ul-n-bits-instead-of-index-n-bit.patch @@ -0,0 +1,52 @@ +From: Alexander Duyck +Date: Thu, 22 Jan 2015 15:51:08 -0800 +Subject: [PATCH] fib_trie: Use index & (~0ul << n->bits) instead of index >> + n->bits + +In doing performance testing and analysis of the changes I recently found +that by shifting the index I had created an unnecessary dependency. + +I have updated the code so that we instead shift a mask by bits and then +just test against that as that should save us about 2 CPU cycles since we +can generate the mask while the key and pos are being processed. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -961,12 +961,12 @@ static struct tnode *fib_find_node(struc + * prefix plus zeros for the bits in the cindex. The index + * is the difference between the key and this value. From + * this we can actually derive several pieces of data. +- * if !(index >> bits) +- * we know the value is cindex +- * else ++ * if (index & (~0ul << bits)) + * we have a mismatch in skip bits and failed ++ * else ++ * we know the value is cindex + */ +- if (index >> n->bits) ++ if (index & (~0ul << n->bits)) + return NULL; + + /* we have found a leaf. Prefixes have already been compared */ +@@ -1301,12 +1301,12 @@ int fib_table_lookup(struct fib_table *t + * prefix plus zeros for the "bits" in the prefix. The index + * is the difference between the key and this value. From + * this we can actually derive several pieces of data. +- * if !(index >> bits) +- * we know the value is child index +- * else ++ * if (index & (~0ul << bits)) + * we have a mismatch in skip bits and failed ++ * else ++ * we know the value is cindex + */ +- if (index >> n->bits) ++ if (index & (~0ul << n->bits)) + break; + + /* we have found a leaf. Prefixes have already been compared */ diff --git a/target/linux/generic/patches-3.18/080-20-fib_trie-Fix-RCU-bug-and-merge-similar-bits-of-infla.patch b/target/linux/generic/patches-3.18/080-20-fib_trie-Fix-RCU-bug-and-merge-similar-bits-of-infla.patch new file mode 100644 index 0000000..7e26127 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-20-fib_trie-Fix-RCU-bug-and-merge-similar-bits-of-infla.patch @@ -0,0 +1,267 @@ +From: Alexander Duyck +Date: Thu, 22 Jan 2015 15:51:14 -0800 +Subject: [PATCH] fib_trie: Fix RCU bug and merge similar bits of inflate/halve + +This patch addresses two issues. + +The first issue is the fact that I believe I had the RCU freeing sequence +slightly out of order. As a result we could get into an issue if a caller +went into a child of a child of the new node, then backtraced into the to be +freed parent, and then attempted to access a child of a child that may have +been consumed in a resize of one of the new nodes children. To resolve this I +have moved the resize after we have freed the oldtnode. The only side effect +of this is that we will now be calling resize on more nodes in the case of +inflate due to the fact that we don't have a good way to test to see if a +full_tnode on the new node was there before or after the allocation. This +should have minimal impact however since the node should already be +correctly size so it is just the cost of calling should_inflate that we +will be taking on the node which is only a couple of cycles. + +The second issue is the fact that inflate and halve were essentially doing +the same thing after the new node was added to the trie replacing the old +one. As such it wasn't really necessary to keep the code in both functions +so I have split it out into two other functions, called replace and +update_children. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -396,8 +396,30 @@ static void put_child(struct tnode *tn, + rcu_assign_pointer(tn->child[i], n); + } + +-static void put_child_root(struct tnode *tp, struct trie *t, +- t_key key, struct tnode *n) ++static void update_children(struct tnode *tn) ++{ ++ unsigned long i; ++ ++ /* update all of the child parent pointers */ ++ for (i = tnode_child_length(tn); i;) { ++ struct tnode *inode = tnode_get_child(tn, --i); ++ ++ if (!inode) ++ continue; ++ ++ /* Either update the children of a tnode that ++ * already belongs to us or update the child ++ * to point to ourselves. ++ */ ++ if (node_parent(inode) == tn) ++ update_children(inode); ++ else ++ node_set_parent(inode, tn); ++ } ++} ++ ++static inline void put_child_root(struct tnode *tp, struct trie *t, ++ t_key key, struct tnode *n) + { + if (tp) + put_child(tp, get_index(key, tp), n); +@@ -434,10 +456,35 @@ static void tnode_free(struct tnode *tn) + } + } + ++static void replace(struct trie *t, struct tnode *oldtnode, struct tnode *tn) ++{ ++ struct tnode *tp = node_parent(oldtnode); ++ unsigned long i; ++ ++ /* setup the parent pointer out of and back into this node */ ++ NODE_INIT_PARENT(tn, tp); ++ put_child_root(tp, t, tn->key, tn); ++ ++ /* update all of the child parent pointers */ ++ update_children(tn); ++ ++ /* all pointers should be clean so we are done */ ++ tnode_free(oldtnode); ++ ++ /* resize children now that oldtnode is freed */ ++ for (i = tnode_child_length(tn); i;) { ++ struct tnode *inode = tnode_get_child(tn, --i); ++ ++ /* resize child node */ ++ if (tnode_full(tn, inode)) ++ resize(t, inode); ++ } ++} ++ + static int inflate(struct trie *t, struct tnode *oldtnode) + { +- struct tnode *inode, *node0, *node1, *tn, *tp; +- unsigned long i, j, k; ++ struct tnode *tn; ++ unsigned long i; + t_key m; + + pr_debug("In inflate\n"); +@@ -446,13 +493,18 @@ static int inflate(struct trie *t, struc + if (!tn) + return -ENOMEM; + ++ /* prepare oldtnode to be freed */ ++ tnode_free_init(oldtnode); ++ + /* Assemble all of the pointers in our cluster, in this case that + * represents all of the pointers out of our allocated nodes that + * point to existing tnodes and the links between our allocated + * nodes. + */ + for (i = tnode_child_length(oldtnode), m = 1u << tn->pos; i;) { +- inode = tnode_get_child(oldtnode, --i); ++ struct tnode *inode = tnode_get_child(oldtnode, --i); ++ struct tnode *node0, *node1; ++ unsigned long j, k; + + /* An empty child */ + if (inode == NULL) +@@ -464,6 +516,9 @@ static int inflate(struct trie *t, struc + continue; + } + ++ /* drop the node in the old tnode free list */ ++ tnode_free_append(oldtnode, inode); ++ + /* An internal node with two children */ + if (inode->bits == 1) { + put_child(tn, 2 * i + 1, tnode_get_child(inode, 1)); +@@ -488,9 +543,9 @@ static int inflate(struct trie *t, struc + node1 = tnode_new(inode->key | m, inode->pos, inode->bits - 1); + if (!node1) + goto nomem; +- tnode_free_append(tn, node1); ++ node0 = tnode_new(inode->key, inode->pos, inode->bits - 1); + +- node0 = tnode_new(inode->key & ~m, inode->pos, inode->bits - 1); ++ tnode_free_append(tn, node1); + if (!node0) + goto nomem; + tnode_free_append(tn, node0); +@@ -512,53 +567,9 @@ static int inflate(struct trie *t, struc + put_child(tn, 2 * i, node0); + } + +- /* setup the parent pointer into and out of this node */ +- tp = node_parent(oldtnode); +- NODE_INIT_PARENT(tn, tp); +- put_child_root(tp, t, tn->key, tn); ++ /* setup the parent pointers into and out of this node */ ++ replace(t, oldtnode, tn); + +- /* prepare oldtnode to be freed */ +- tnode_free_init(oldtnode); +- +- /* update all child nodes parent pointers to route to us */ +- for (i = tnode_child_length(oldtnode); i;) { +- inode = tnode_get_child(oldtnode, --i); +- +- /* A leaf or an internal node with skipped bits */ +- if (!tnode_full(oldtnode, inode)) { +- node_set_parent(inode, tn); +- continue; +- } +- +- /* drop the node in the old tnode free list */ +- tnode_free_append(oldtnode, inode); +- +- /* fetch new nodes */ +- node1 = tnode_get_child(tn, 2 * i + 1); +- node0 = tnode_get_child(tn, 2 * i); +- +- /* bits == 1 then node0 and node1 represent inode's children */ +- if (inode->bits == 1) { +- node_set_parent(node1, tn); +- node_set_parent(node0, tn); +- continue; +- } +- +- /* update parent pointers in child node's children */ +- for (k = tnode_child_length(inode), j = k / 2; j;) { +- node_set_parent(tnode_get_child(inode, --k), node1); +- node_set_parent(tnode_get_child(inode, --j), node0); +- node_set_parent(tnode_get_child(inode, --k), node1); +- node_set_parent(tnode_get_child(inode, --j), node0); +- } +- +- /* resize child nodes */ +- resize(t, node1); +- resize(t, node0); +- } +- +- /* we completed without error, prepare to free old node */ +- tnode_free(oldtnode); + return 0; + nomem: + /* all pointers should be clean so we are done */ +@@ -568,7 +579,7 @@ nomem: + + static int halve(struct trie *t, struct tnode *oldtnode) + { +- struct tnode *tn, *tp, *inode, *node0, *node1; ++ struct tnode *tn; + unsigned long i; + + pr_debug("In halve\n"); +@@ -577,14 +588,18 @@ static int halve(struct trie *t, struct + if (!tn) + return -ENOMEM; + ++ /* prepare oldtnode to be freed */ ++ tnode_free_init(oldtnode); ++ + /* Assemble all of the pointers in our cluster, in this case that + * represents all of the pointers out of our allocated nodes that + * point to existing tnodes and the links between our allocated + * nodes. + */ + for (i = tnode_child_length(oldtnode); i;) { +- node1 = tnode_get_child(oldtnode, --i); +- node0 = tnode_get_child(oldtnode, --i); ++ struct tnode *node1 = tnode_get_child(oldtnode, --i); ++ struct tnode *node0 = tnode_get_child(oldtnode, --i); ++ struct tnode *inode; + + /* At least one of the children is empty */ + if (!node1 || !node0) { +@@ -609,34 +624,8 @@ static int halve(struct trie *t, struct + put_child(tn, i / 2, inode); + } + +- /* setup the parent pointer out of and back into this node */ +- tp = node_parent(oldtnode); +- NODE_INIT_PARENT(tn, tp); +- put_child_root(tp, t, tn->key, tn); +- +- /* prepare oldtnode to be freed */ +- tnode_free_init(oldtnode); +- +- /* update all of the child parent pointers */ +- for (i = tnode_child_length(tn); i;) { +- inode = tnode_get_child(tn, --i); +- +- /* only new tnodes will be considered "full" nodes */ +- if (!tnode_full(tn, inode)) { +- node_set_parent(inode, tn); +- continue; +- } +- +- /* Two nonempty children */ +- node_set_parent(tnode_get_child(inode, 1), inode); +- node_set_parent(tnode_get_child(inode, 0), inode); +- +- /* resize child node */ +- resize(t, inode); +- } +- +- /* all pointers should be clean so we are done */ +- tnode_free(oldtnode); ++ /* setup the parent pointers into and out of this node */ ++ replace(t, oldtnode, tn); + + return 0; + } diff --git a/target/linux/generic/patches-3.18/080-21-fib_trie-Fall-back-to-slen-update-on-inflate-halve-f.patch b/target/linux/generic/patches-3.18/080-21-fib_trie-Fall-back-to-slen-update-on-inflate-halve-f.patch new file mode 100644 index 0000000..058b33b --- /dev/null +++ b/target/linux/generic/patches-3.18/080-21-fib_trie-Fall-back-to-slen-update-on-inflate-halve-f.patch @@ -0,0 +1,61 @@ +From: Alexander Duyck +Date: Thu, 22 Jan 2015 15:51:20 -0800 +Subject: [PATCH] fib_trie: Fall back to slen update on inflate/halve failure + +This change corrects an issue where if inflate or halve fails we were +exiting the resize function without at least updating the slen for the +node. To correct this I have moved the update of max_size into the while +loop so that it is only decremented on a successful call to either inflate +or halve. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -752,7 +752,7 @@ static void resize(struct trie *t, struc + { + struct tnode *tp = node_parent(tn), *n = NULL; + struct tnode __rcu **cptr; +- int max_work; ++ int max_work = MAX_WORK; + + pr_debug("In tnode_resize %p inflate_threshold=%d threshold=%d\n", + tn, inflate_threshold, halve_threshold); +@@ -775,8 +775,7 @@ static void resize(struct trie *t, struc + /* Double as long as the resulting node has a number of + * nonempty nodes that are above the threshold. + */ +- max_work = MAX_WORK; +- while (should_inflate(tp, tn) && max_work--) { ++ while (should_inflate(tp, tn) && max_work) { + if (inflate(t, tn)) { + #ifdef CONFIG_IP_FIB_TRIE_STATS + this_cpu_inc(t->stats->resize_node_skipped); +@@ -784,6 +783,7 @@ static void resize(struct trie *t, struc + break; + } + ++ max_work--; + tn = rtnl_dereference(*cptr); + } + +@@ -794,8 +794,7 @@ static void resize(struct trie *t, struc + /* Halve as long as the number of empty children in this + * node is above threshold. + */ +- max_work = MAX_WORK; +- while (should_halve(tp, tn) && max_work--) { ++ while (should_halve(tp, tn) && max_work) { + if (halve(t, tn)) { + #ifdef CONFIG_IP_FIB_TRIE_STATS + this_cpu_inc(t->stats->resize_node_skipped); +@@ -803,6 +802,7 @@ static void resize(struct trie *t, struc + break; + } + ++ max_work--; + tn = rtnl_dereference(*cptr); + } + diff --git a/target/linux/generic/patches-3.18/080-22-fib_trie-Add-collapse-and-should_collapse-to-resize.patch b/target/linux/generic/patches-3.18/080-22-fib_trie-Add-collapse-and-should_collapse-to-resize.patch new file mode 100644 index 0000000..19b7db7 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-22-fib_trie-Add-collapse-and-should_collapse-to-resize.patch @@ -0,0 +1,206 @@ +From: Alexander Duyck +Date: Thu, 22 Jan 2015 15:51:26 -0800 +Subject: [PATCH] fib_trie: Add collapse() and should_collapse() to resize + +This patch really does two things. + +First it pulls the logic for determining if we should collapse one node out +of the tree and the actual code doing the collapse into a separate pair of +functions. This helps to make the changes to these areas more readable. + +Second it encodes the upper 32b of the empty_children value onto the +full_children value in the case of bits == KEYLENGTH. By doing this we are +able to handle the case of a 32b node where empty_children would appear to +be 0 when it was actually 1ul << 32. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -83,7 +83,8 @@ + + #define MAX_STAT_DEPTH 32 + +-#define KEYLENGTH (8*sizeof(t_key)) ++#define KEYLENGTH (8*sizeof(t_key)) ++#define KEY_MAX ((t_key)~0) + + typedef unsigned int t_key; + +@@ -102,8 +103,8 @@ struct tnode { + union { + /* The fields in this struct are valid if bits > 0 (TNODE) */ + struct { +- unsigned int full_children; /* KEYLENGTH bits needed */ +- unsigned int empty_children; /* KEYLENGTH bits needed */ ++ t_key empty_children; /* KEYLENGTH bits needed */ ++ t_key full_children; /* KEYLENGTH bits needed */ + struct tnode __rcu *child[0]; + }; + /* This list pointer if valid if bits == 0 (LEAF) */ +@@ -302,6 +303,16 @@ static struct tnode *tnode_alloc(size_t + return vzalloc(size); + } + ++static inline void empty_child_inc(struct tnode *n) ++{ ++ ++n->empty_children ? : ++n->full_children; ++} ++ ++static inline void empty_child_dec(struct tnode *n) ++{ ++ n->empty_children-- ? : n->full_children--; ++} ++ + static struct tnode *leaf_new(t_key key) + { + struct tnode *l = kmem_cache_alloc(trie_leaf_kmem, GFP_KERNEL); +@@ -335,7 +346,7 @@ static struct leaf_info *leaf_info_new(i + + static struct tnode *tnode_new(t_key key, int pos, int bits) + { +- size_t sz = offsetof(struct tnode, child[1 << bits]); ++ size_t sz = offsetof(struct tnode, child[1ul << bits]); + struct tnode *tn = tnode_alloc(sz); + unsigned int shift = pos + bits; + +@@ -348,8 +359,10 @@ static struct tnode *tnode_new(t_key key + tn->pos = pos; + tn->bits = bits; + tn->key = (shift < KEYLENGTH) ? (key >> shift) << shift : 0; +- tn->full_children = 0; +- tn->empty_children = 1<full_children = 1; ++ else ++ tn->empty_children = 1ul << bits; + } + + pr_debug("AT %p s=%zu %zu\n", tn, sizeof(struct tnode), +@@ -375,11 +388,11 @@ static void put_child(struct tnode *tn, + + BUG_ON(i >= tnode_child_length(tn)); + +- /* update emptyChildren */ ++ /* update emptyChildren, overflow into fullChildren */ + if (n == NULL && chi != NULL) +- tn->empty_children++; +- else if (n != NULL && chi == NULL) +- tn->empty_children--; ++ empty_child_inc(tn); ++ if (n != NULL && chi == NULL) ++ empty_child_dec(tn); + + /* update fullChildren */ + wasfull = tnode_full(tn, chi); +@@ -630,6 +643,24 @@ static int halve(struct trie *t, struct + return 0; + } + ++static void collapse(struct trie *t, struct tnode *oldtnode) ++{ ++ struct tnode *n, *tp; ++ unsigned long i; ++ ++ /* scan the tnode looking for that one child that might still exist */ ++ for (n = NULL, i = tnode_child_length(oldtnode); !n && i;) ++ n = tnode_get_child(oldtnode, --i); ++ ++ /* compress one level */ ++ tp = node_parent(oldtnode); ++ put_child_root(tp, t, oldtnode->key, n); ++ node_set_parent(n, tp); ++ ++ /* drop dead node */ ++ node_free(oldtnode); ++} ++ + static unsigned char update_suffix(struct tnode *tn) + { + unsigned char slen = tn->pos; +@@ -729,10 +760,12 @@ static bool should_inflate(const struct + + /* Keep root node larger */ + threshold *= tp ? inflate_threshold : inflate_threshold_root; +- used += tn->full_children; + used -= tn->empty_children; ++ used += tn->full_children; + +- return tn->pos && ((50 * used) >= threshold); ++ /* if bits == KEYLENGTH then pos = 0, and will fail below */ ++ ++ return (used > 1) && tn->pos && ((50 * used) >= threshold); + } + + static bool should_halve(const struct tnode *tp, const struct tnode *tn) +@@ -744,13 +777,29 @@ static bool should_halve(const struct tn + threshold *= tp ? halve_threshold : halve_threshold_root; + used -= tn->empty_children; + +- return (tn->bits > 1) && ((100 * used) < threshold); ++ /* if bits == KEYLENGTH then used = 100% on wrap, and will fail below */ ++ ++ return (used > 1) && (tn->bits > 1) && ((100 * used) < threshold); ++} ++ ++static bool should_collapse(const struct tnode *tn) ++{ ++ unsigned long used = tnode_child_length(tn); ++ ++ used -= tn->empty_children; ++ ++ /* account for bits == KEYLENGTH case */ ++ if ((tn->bits == KEYLENGTH) && tn->full_children) ++ used -= KEY_MAX; ++ ++ /* One child or none, time to drop us from the trie */ ++ return used < 2; + } + + #define MAX_WORK 10 + static void resize(struct trie *t, struct tnode *tn) + { +- struct tnode *tp = node_parent(tn), *n = NULL; ++ struct tnode *tp = node_parent(tn); + struct tnode __rcu **cptr; + int max_work = MAX_WORK; + +@@ -764,14 +813,6 @@ static void resize(struct trie *t, struc + cptr = tp ? &tp->child[get_index(tn->key, tp)] : &t->trie; + BUG_ON(tn != rtnl_dereference(*cptr)); + +- /* No children */ +- if (tn->empty_children > (tnode_child_length(tn) - 1)) +- goto no_children; +- +- /* One child */ +- if (tn->empty_children == (tnode_child_length(tn) - 1)) +- goto one_child; +- + /* Double as long as the resulting node has a number of + * nonempty nodes that are above the threshold. + */ +@@ -807,19 +848,8 @@ static void resize(struct trie *t, struc + } + + /* Only one child remains */ +- if (tn->empty_children == (tnode_child_length(tn) - 1)) { +- unsigned long i; +-one_child: +- for (i = tnode_child_length(tn); !n && i;) +- n = tnode_get_child(tn, --i); +-no_children: +- /* compress one level */ +- put_child_root(tp, t, tn->key, n); +- node_set_parent(n, tp); +- +- /* drop dead node */ +- tnode_free_init(tn); +- tnode_free(tn); ++ if (should_collapse(tn)) { ++ collapse(t, tn); + return; + } + diff --git a/target/linux/generic/patches-3.18/080-23-fib_trie-Use-empty_children-instead-of-counting-empt.patch b/target/linux/generic/patches-3.18/080-23-fib_trie-Use-empty_children-instead-of-counting-empt.patch new file mode 100644 index 0000000..160fbe1 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-23-fib_trie-Use-empty_children-instead-of-counting-empt.patch @@ -0,0 +1,34 @@ +From: Alexander Duyck +Date: Thu, 22 Jan 2015 15:51:33 -0800 +Subject: [PATCH] fib_trie: Use empty_children instead of counting empty nodes + in stats collection + +It doesn't make much sense to count the pointers ourselves when +empty_children already has a count for the number of NULL pointers stored +in the tnode. As such save ourselves the cycles and just use +empty_children. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -1954,16 +1954,10 @@ static void trie_collect_stats(struct tr + hlist_for_each_entry_rcu(li, &n->list, hlist) + ++s->prefixes; + } else { +- unsigned long i; +- + s->tnodes++; + if (n->bits < MAX_STAT_DEPTH) + s->nodesizes[n->bits]++; +- +- for (i = tnode_child_length(n); i--;) { +- if (!rcu_access_pointer(n->child[i])) +- s->nullpointers++; +- } ++ s->nullpointers += n->empty_children; + } + } + rcu_read_unlock(); diff --git a/target/linux/generic/patches-3.18/080-24-fib_trie-Move-fib_find_alias-to-file-where-it-is-use.patch b/target/linux/generic/patches-3.18/080-24-fib_trie-Move-fib_find_alias-to-file-where-it-is-use.patch new file mode 100644 index 0000000..5eba700 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-24-fib_trie-Move-fib_find_alias-to-file-where-it-is-use.patch @@ -0,0 +1,79 @@ +From: Alexander Duyck +Date: Thu, 22 Jan 2015 15:51:39 -0800 +Subject: [PATCH] fib_trie: Move fib_find_alias to file where it is used + +The function fib_find_alias is only accessed by functions in fib_trie.c as +such it makes sense to relocate it and cast it as static so that the +compiler can take advantage of optimizations it can do to it as a local +function. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_lookup.h ++++ b/net/ipv4/fib_lookup.h +@@ -32,7 +32,6 @@ int fib_dump_info(struct sk_buff *skb, u + unsigned int); + void rtmsg_fib(int event, __be32 key, struct fib_alias *fa, int dst_len, + u32 tb_id, const struct nl_info *info, unsigned int nlm_flags); +-struct fib_alias *fib_find_alias(struct list_head *fah, u8 tos, u32 prio); + + static inline void fib_result_assign(struct fib_result *res, + struct fib_info *fi) +--- a/net/ipv4/fib_semantics.c ++++ b/net/ipv4/fib_semantics.c +@@ -410,24 +410,6 @@ errout: + rtnl_set_sk_err(info->nl_net, RTNLGRP_IPV4_ROUTE, err); + } + +-/* Return the first fib alias matching TOS with +- * priority less than or equal to PRIO. +- */ +-struct fib_alias *fib_find_alias(struct list_head *fah, u8 tos, u32 prio) +-{ +- if (fah) { +- struct fib_alias *fa; +- list_for_each_entry(fa, fah, fa_list) { +- if (fa->fa_tos > tos) +- continue; +- if (fa->fa_info->fib_priority >= prio || +- fa->fa_tos < tos) +- return fa; +- } +- } +- return NULL; +-} +- + static int fib_detect_death(struct fib_info *fi, int order, + struct fib_info **last_resort, int *last_idx, + int dflt) +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -998,6 +998,26 @@ static struct tnode *fib_find_node(struc + return n; + } + ++/* Return the first fib alias matching TOS with ++ * priority less than or equal to PRIO. ++ */ ++static struct fib_alias *fib_find_alias(struct list_head *fah, u8 tos, u32 prio) ++{ ++ struct fib_alias *fa; ++ ++ if (!fah) ++ return NULL; ++ ++ list_for_each_entry(fa, fah, fa_list) { ++ if (fa->fa_tos > tos) ++ continue; ++ if (fa->fa_info->fib_priority >= prio || fa->fa_tos < tos) ++ return fa; ++ } ++ ++ return NULL; ++} ++ + static void trie_rebalance(struct trie *t, struct tnode *tn) + { + struct tnode *tp; diff --git a/target/linux/generic/patches-3.18/080-25-fib_trie-Various-clean-ups-for-handling-slen.patch b/target/linux/generic/patches-3.18/080-25-fib_trie-Various-clean-ups-for-handling-slen.patch new file mode 100644 index 0000000..c7739d0 --- /dev/null +++ b/target/linux/generic/patches-3.18/080-25-fib_trie-Various-clean-ups-for-handling-slen.patch @@ -0,0 +1,116 @@ +From: Alexander Duyck +Date: Thu, 22 Jan 2015 15:51:45 -0800 +Subject: [PATCH] fib_trie: Various clean-ups for handling slen + +While doing further work on the fib_trie I noted a few items. + +First I was using calls that were far more complicated than they needed to +be for determining when to push/pull the suffix length. I have updated the +code to reflect the simplier logic. + +The second issue is that I realised we weren't necessarily handling the +case of a leaf_info struct surviving a flush. I have updated the logic so +that now we will call pull_suffix in the event of having a leaf info value +left in the leaf after flushing it. + +Signed-off-by: Alexander Duyck +Signed-off-by: David S. Miller +--- + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -917,27 +917,20 @@ static void leaf_push_suffix(struct tnod + + static void remove_leaf_info(struct tnode *l, struct leaf_info *old) + { +- struct hlist_node *prev; +- +- /* record the location of the pointer to this object */ +- prev = rtnl_dereference(hlist_pprev_rcu(&old->hlist)); ++ /* record the location of the previous list_info entry */ ++ struct hlist_node **pprev = old->hlist.pprev; ++ struct leaf_info *li = hlist_entry(pprev, typeof(*li), hlist.next); + + /* remove the leaf info from the list */ + hlist_del_rcu(&old->hlist); + +- /* if we emptied the list this leaf will be freed and we can sort +- * out parent suffix lengths as a part of trie_rebalance +- */ +- if (hlist_empty(&l->list)) ++ /* only access li if it is pointing at the last valid hlist_node */ ++ if (hlist_empty(&l->list) || (*pprev)) + return; + +- /* if we removed the tail then we need to update slen */ +- if (!rcu_access_pointer(hlist_next_rcu(prev))) { +- struct leaf_info *li = hlist_entry(prev, typeof(*li), hlist); +- +- l->slen = KEYLENGTH - li->plen; +- leaf_pull_suffix(l); +- } ++ /* update the trie with the latest suffix length */ ++ l->slen = KEYLENGTH - li->plen; ++ leaf_pull_suffix(l); + } + + static void insert_leaf_info(struct tnode *l, struct leaf_info *new) +@@ -961,7 +954,7 @@ static void insert_leaf_info(struct tnod + } + + /* if we added to the tail node then we need to update slen */ +- if (!rcu_access_pointer(hlist_next_rcu(&new->hlist))) { ++ if (l->slen < (KEYLENGTH - new->plen)) { + l->slen = KEYLENGTH - new->plen; + leaf_push_suffix(l); + } +@@ -1613,6 +1606,7 @@ static int trie_flush_leaf(struct tnode + struct hlist_head *lih = &l->list; + struct hlist_node *tmp; + struct leaf_info *li = NULL; ++ unsigned char plen = KEYLENGTH; + + hlist_for_each_entry_safe(li, tmp, lih, hlist) { + found += trie_flush_list(&li->falh); +@@ -1620,8 +1614,14 @@ static int trie_flush_leaf(struct tnode + if (list_empty(&li->falh)) { + hlist_del_rcu(&li->hlist); + free_leaf_info(li); ++ continue; + } ++ ++ plen = li->plen; + } ++ ++ l->slen = KEYLENGTH - plen; ++ + return found; + } + +@@ -1700,13 +1700,22 @@ int fib_table_flush(struct fib_table *tb + for (l = trie_firstleaf(t); l; l = trie_nextleaf(l)) { + found += trie_flush_leaf(l); + +- if (ll && hlist_empty(&ll->list)) +- trie_leaf_remove(t, ll); ++ if (ll) { ++ if (hlist_empty(&ll->list)) ++ trie_leaf_remove(t, ll); ++ else ++ leaf_pull_suffix(ll); ++ } ++ + ll = l; + } + +- if (ll && hlist_empty(&ll->list)) +- trie_leaf_remove(t, ll); ++ if (ll) { ++ if (hlist_empty(&ll->list)) ++ trie_leaf_remove(t, ll); ++ else ++ leaf_pull_suffix(ll); ++ } + + pr_debug("trie_flush found=%d\n", found); + return found; diff --git a/target/linux/generic/patches-3.18/081-pppoe-Use-workqueue-to-die-properly-when-a-PADT-is-r.patch b/target/linux/generic/patches-3.18/081-pppoe-Use-workqueue-to-die-properly-when-a-PADT-is-r.patch new file mode 100644 index 0000000..de85830 --- /dev/null +++ b/target/linux/generic/patches-3.18/081-pppoe-Use-workqueue-to-die-properly-when-a-PADT-is-r.patch @@ -0,0 +1,89 @@ +From: Simon Farnsworth +Date: Sun, 1 Mar 2015 10:54:39 +0000 +Subject: [PATCH] pppoe: Use workqueue to die properly when a PADT is received + +When a PADT frame is received, the socket may not be in a good state to +close down the PPP interface. The current implementation handles this by +simply blocking all further PPP traffic, and hoping that the lack of traffic +will trigger the user to investigate. + +Use schedule_work to get to a process context from which we clear down the +PPP interface, in a fashion analogous to hangup on a TTY-based PPP +interface. This causes pppd to disconnect immediately, and allows tools to +take immediate corrective action. + +Note that pppd's rp_pppoe.so plugin has code in it to disable the session +when it disconnects; however, as a consequence of this patch, the session is +already disabled before rp_pppoe.so is asked to disable the session. The +result is a harmless error message: + +Failed to disconnect PPPoE socket: 114 Operation already in progress + +This message is safe to ignore, as long as the error is 114 Operation +already in progress; in that specific case, it means that the PPPoE session +has already been disabled before pppd tried to disable it. + +Signed-off-by: Simon Farnsworth +Tested-by: Dan Williams +Tested-by: Christoph Schulz +Signed-off-by: David S. Miller +--- + +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -455,6 +455,18 @@ out: + return NET_RX_DROP; + } + ++static void pppoe_unbind_sock_work(struct work_struct *work) ++{ ++ struct pppox_sock *po = container_of(work, struct pppox_sock, ++ proto.pppoe.padt_work); ++ struct sock *sk = sk_pppox(po); ++ ++ lock_sock(sk); ++ pppox_unbind_sock(sk); ++ release_sock(sk); ++ sock_put(sk); ++} ++ + /************************************************************************ + * + * Receive a PPPoE Discovery frame. +@@ -500,7 +512,8 @@ static int pppoe_disc_rcv(struct sk_buff + } + + bh_unlock_sock(sk); +- sock_put(sk); ++ if (!schedule_work(&po->proto.pppoe.padt_work)) ++ sock_put(sk); + } + + abort: +@@ -613,6 +626,8 @@ static int pppoe_connect(struct socket * + + lock_sock(sk); + ++ INIT_WORK(&po->proto.pppoe.padt_work, pppoe_unbind_sock_work); ++ + error = -EINVAL; + if (sp->sa_protocol != PX_PROTO_OE) + goto end; +--- a/include/linux/if_pppox.h ++++ b/include/linux/if_pppox.h +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + + static inline struct pppoe_hdr *pppoe_hdr(const struct sk_buff *skb) +@@ -32,6 +33,7 @@ struct pppoe_opt { + struct pppoe_addr pa; /* what this socket is bound to*/ + struct sockaddr_pppox relay; /* what socket data will be + relayed to (PPPoE relaying) */ ++ struct work_struct padt_work;/* Work item for handling PADT */ + }; + + struct pptp_opt { diff --git a/target/linux/generic/patches-3.18/082-ipv6-ip6_fragment-fix-headroom-tests-and-skb-leak.patch b/target/linux/generic/patches-3.18/082-ipv6-ip6_fragment-fix-headroom-tests-and-skb-leak.patch new file mode 100644 index 0000000..7c833c4 --- /dev/null +++ b/target/linux/generic/patches-3.18/082-ipv6-ip6_fragment-fix-headroom-tests-and-skb-leak.patch @@ -0,0 +1,101 @@ +From: Florian Westphal +Date: Thu, 17 Sep 2015 11:24:48 +0100 +Subject: [PATCH] ipv6: ip6_fragment: fix headroom tests and skb leak + +David Woodhouse reports skb_under_panic when we try to push ethernet +header to fragmented ipv6 skbs: + + skbuff: skb_under_panic: text:c1277f1e len:1294 put:14 head:dec98000 + data:dec97ffc tail:0xdec9850a end:0xdec98f40 dev:br-lan +[..] +ip6_finish_output2+0x196/0x4da + +David further debugged this: + [..] offending fragments were arriving here with skb_headroom(skb)==10. + Which is reasonable, being the Solos ADSL card's header of 8 bytes + followed by 2 bytes of PPP frame type. + +The problem is that if netfilter ipv6 defragmentation is used, skb_cow() +in ip6_forward will only see reassembled skb. + +Therefore, headroom is overestimated by 8 bytes (we pulled fragment +header) and we don't check the skbs in the frag_list either. + +We can't do these checks in netfilter defrag since outdev isn't known yet. + +Furthermore, existing tests in ip6_fragment did not consider the fragment +or ipv6 header size when checking headroom of the fraglist skbs. + +While at it, also fix a skb leak on memory allocation -- ip6_fragment +must consume the skb. + +I tested this e1000 driver hacked to not allocate additional headroom +(we end up in slowpath, since LL_RESERVED_SPACE is 16). + +If 2 bytes of headroom are allocated, fastpath is taken (14 byte +ethernet header was pulled, so 16 byte headroom available in all +fragments). + +Reported-by: David Woodhouse +Diagnosed-by: David Woodhouse +Signed-off-by: Florian Westphal +Closes 20532 +--- + +--- a/net/ipv6/ip6_output.c ++++ b/net/ipv6/ip6_output.c +@@ -594,20 +594,22 @@ int ip6_fragment(struct sk_buff *skb, in + } + mtu -= hlen + sizeof(struct frag_hdr); + ++ hroom = LL_RESERVED_SPACE(rt->dst.dev); + if (skb_has_frag_list(skb)) { + int first_len = skb_pagelen(skb); + struct sk_buff *frag2; + + if (first_len - hlen > mtu || + ((first_len - hlen) & 7) || +- skb_cloned(skb)) ++ skb_cloned(skb) || ++ skb_headroom(skb) < (hroom + sizeof(struct frag_hdr))) + goto slow_path; + + skb_walk_frags(skb, frag) { + /* Correct geometry. */ + if (frag->len > mtu || + ((frag->len & 7) && frag->next) || +- skb_headroom(frag) < hlen) ++ skb_headroom(frag) < (hlen + hroom + sizeof(struct frag_hdr))) + goto slow_path_clean; + + /* Partially cloned skb? */ +@@ -624,8 +626,6 @@ int ip6_fragment(struct sk_buff *skb, in + + err = 0; + offset = 0; +- frag = skb_shinfo(skb)->frag_list; +- skb_frag_list_init(skb); + /* BUILD HEADER */ + + *prevhdr = NEXTHDR_FRAGMENT; +@@ -633,8 +633,11 @@ int ip6_fragment(struct sk_buff *skb, in + if (!tmp_hdr) { + IP6_INC_STATS(net, ip6_dst_idev(skb_dst(skb)), + IPSTATS_MIB_FRAGFAILS); +- return -ENOMEM; ++ err = -ENOMEM; ++ goto fail; + } ++ frag = skb_shinfo(skb)->frag_list; ++ skb_frag_list_init(skb); + + __skb_pull(skb, hlen); + fh = (struct frag_hdr *)__skb_push(skb, sizeof(struct frag_hdr)); +@@ -732,7 +735,6 @@ slow_path: + */ + + *prevhdr = NEXTHDR_FRAGMENT; +- hroom = LL_RESERVED_SPACE(rt->dst.dev); + troom = rt->dst.dev->needed_tailroom; + + /* diff --git a/target/linux/generic/patches-3.18/083-solos-pci-Increase-headroom-on-received-packets.patch b/target/linux/generic/patches-3.18/083-solos-pci-Increase-headroom-on-received-packets.patch new file mode 100644 index 0000000..7f9f926 --- /dev/null +++ b/target/linux/generic/patches-3.18/083-solos-pci-Increase-headroom-on-received-packets.patch @@ -0,0 +1,54 @@ +From: David Woodhouse +Date: Thu, 17 Sep 2015 11:19:53 +0100 +Subject: [PATCH] solos-pci: Increase headroom on received packets +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +A comment in include/linux/skbuff.h says that: + + * Various parts of the networking layer expect at least 32 bytes of + * headroom, you should not reduce this. + +This was demonstrated by a panic when handling fragmented IPv6 packets: +http://marc.info/?l=linux-netdev&m=144236093519172&w=2 + +It's not entirely clear if that comment is still valid — and if it is, +perhaps netif_rx() ought to be enforcing it with a warning. + +But either way, it is rather stupid from a performance point of view +for us to be receiving packets into a buffer which doesn't have enough +room to prepend an Ethernet header — it means that *every* incoming +packet is going to be need to be reallocated. So let's fix that. + +Signed-off-by: David Woodhouse +--- + +--- a/drivers/atm/solos-pci.c ++++ b/drivers/atm/solos-pci.c +@@ -805,7 +805,12 @@ static void solos_bh(unsigned long card_ + continue; + } + +- skb = alloc_skb(size + 1, GFP_ATOMIC); ++ /* Use netdev_alloc_skb() because it adds NET_SKB_PAD of ++ * headroom, and ensures we can route packets back out an ++ * Ethernet interface (for example) without having to ++ * reallocate. Adding NET_IP_ALIGN also ensures that both ++ * PPPoATM and PPPoEoBR2684 packets end up aligned. */ ++ skb = netdev_alloc_skb_ip_align(NULL, size + 1); + if (!skb) { + if (net_ratelimit()) + dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n"); +@@ -869,7 +874,10 @@ static void solos_bh(unsigned long card_ + /* Allocate RX skbs for any ports which need them */ + if (card->using_dma && card->atmdev[port] && + !card->rx_skb[port]) { +- struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC); ++ /* Unlike the MMIO case (qv) we can't add NET_IP_ALIGN ++ * here; the FPGA can only DMA to addresses which are ++ * aligned to 4 bytes. */ ++ struct sk_buff *skb = dev_alloc_skb(RX_DMA_SIZE); + if (skb) { + SKB_CB(skb)->dma_addr = + pci_map_single(card->dev, skb->data, diff --git a/target/linux/generic/patches-3.18/090-overlayfs-fallback-to-readonly-when-full.patch b/target/linux/generic/patches-3.18/090-overlayfs-fallback-to-readonly-when-full.patch new file mode 100644 index 0000000..6fbbc25 --- /dev/null +++ b/target/linux/generic/patches-3.18/090-overlayfs-fallback-to-readonly-when-full.patch @@ -0,0 +1,109 @@ +[linux-unionfs added to Cc] + +On Tue, May 19, 2015 at 09:51:20AM +0200, Bastian Bittorf wrote: +> Hi Miklos, +> +> sorry for writing directly to you, feel free to forward +> this to the appropriate mailinglist. +> +> we have a problem with mainline overlay filesystem on kernel 3.18: +> https://dev.openwrt.org/ticket/19564 +> +> 2 things are odd: +> when the working filesystem is full, overlays fails with: +> +> overlayfs: failed to create directory /overlay/work/work +> +> what is strange, that we call it with: +> +> mount(overlay, "/mnt", "overlay", MS_NOATIME, lowerdir) +> +> see here: +> http://nbd.name/gitweb.cgi?p=fstools.git;a=blob;f=libfstools/mount.c;h=81176ce399b4cd8e2d347c0008c13dec92407f55;hb=e6004000ff15d7bd32cf5663e8690fc94d7ec747#l125 +> +> do you have an idea whats wrong? +> 1) is it really needed, that we need space for creating dir "/overlay/work"? +> 2) why does overlay need "/overlay/work/work"? + +The work directory is needed for atomic copy-up and similar. It is not actually +necessary to mount a read-only overlay. Post 4.0 it is possible to mount the +overlay without workdir (but even then it won't happen automatically in case the +upper fs is full, so this should be fixed in the latest kernel too). + +Could you please try the following patch? If the workdir can't be created it +will fall back to mounting the overlay read-only. + +Thanks, +Miklos + +--- + fs/overlayfs/copy_up.c | 3 +++ + fs/overlayfs/dir.c | 9 +++++++++ + fs/overlayfs/super.c | 12 +++++++++--- + 3 files changed, 21 insertions(+), 3 deletions(-) + +--- a/fs/overlayfs/copy_up.c ++++ b/fs/overlayfs/copy_up.c +@@ -300,6 +300,9 @@ int ovl_copy_up_one(struct dentry *paren + struct cred *override_cred; + char *link = NULL; + ++ if (WARN_ON(!workdir)) ++ return -EROFS; ++ + ovl_path_upper(parent, &parentpath); + upperdir = parentpath.dentry; + +--- a/fs/overlayfs/dir.c ++++ b/fs/overlayfs/dir.c +@@ -222,6 +222,9 @@ static struct dentry *ovl_clear_empty(st + struct kstat stat; + int err; + ++ if (WARN_ON(!workdir)) ++ return ERR_PTR(-EROFS); ++ + err = ovl_lock_rename_workdir(workdir, upperdir); + if (err) + goto out; +@@ -322,6 +325,9 @@ static int ovl_create_over_whiteout(stru + struct dentry *newdentry; + int err; + ++ if (WARN_ON(!workdir)) ++ return -EROFS; ++ + err = ovl_lock_rename_workdir(workdir, upperdir); + if (err) + goto out; +@@ -506,6 +512,9 @@ static int ovl_remove_and_whiteout(struc + struct dentry *opaquedir = NULL; + int err; + ++ if (WARN_ON(!workdir)) ++ return -EROFS; ++ + if (is_dir) { + opaquedir = ovl_check_empty_and_clear(dentry); + err = PTR_ERR(opaquedir); +--- a/fs/overlayfs/super.c ++++ b/fs/overlayfs/super.c +@@ -741,9 +741,15 @@ static int ovl_fill_super(struct super_b + ufs->workdir = ovl_workdir_create(ufs->upper_mnt, workpath.dentry); + err = PTR_ERR(ufs->workdir); + if (IS_ERR(ufs->workdir)) { +- pr_err("overlayfs: failed to create directory %s/%s\n", +- ufs->config.workdir, OVL_WORKDIR_NAME); +- goto out_put_lower_mnt; ++ if (err == -ENOSPC || err == -EROFS) { ++ pr_warning("overlayfs: failed to create work directory (%s), mounting read-only\n", err == ENOSPC ? "ENOSPC" : "EROFS"); ++ sb->s_flags |= MS_RDONLY; ++ ufs->workdir = NULL; ++ } else { ++ pr_err("overlayfs: failed to create directory %s/%s\n", ++ ufs->config.workdir, OVL_WORKDIR_NAME); ++ goto out_put_lower_mnt; ++ } + } + + /* diff --git a/target/linux/generic/patches-3.18/091-mtd-spi-nor-add-support-Spansion_S25FL164K b/target/linux/generic/patches-3.18/091-mtd-spi-nor-add-support-Spansion_S25FL164K new file mode 100644 index 0000000..d9831f4 --- /dev/null +++ b/target/linux/generic/patches-3.18/091-mtd-spi-nor-add-support-Spansion_S25FL164K @@ -0,0 +1,10 @@ +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -566,6 +566,7 @@ static const struct spi_device_id spi_no + { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, + { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, + { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, ++ { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, + + /* SST -- large erase sizes are "overlays", "sectors" are 4K */ + { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, diff --git a/target/linux/generic/patches-3.18/092-01-spi-Check-to-see-if-the-device-is-processing-a-messa.patch b/target/linux/generic/patches-3.18/092-01-spi-Check-to-see-if-the-device-is-processing-a-messa.patch new file mode 100644 index 0000000..fa3ab6a --- /dev/null +++ b/target/linux/generic/patches-3.18/092-01-spi-Check-to-see-if-the-device-is-processing-a-messa.patch @@ -0,0 +1,47 @@ +From: Mark Brown +Date: Tue, 9 Dec 2014 19:46:56 +0000 +Subject: [PATCH] spi: Check to see if the device is processing a message + before we idle + +cur_msg is updated under the queue lock and holds the message we are +currently processing. Since currently we only ever do removals in the +pump kthread it doesn't matter in what order we do things but we want +to be able to push things out from the submitting thread so pull the +check to see if we're currently handling a message before we check to +see if the queue is idle. + +Signed-off-by: Mark Brown +--- + +--- a/drivers/spi/spi.c ++++ b/drivers/spi/spi.c +@@ -891,8 +891,16 @@ static void spi_pump_messages(struct kth + bool was_busy = false; + int ret; + +- /* Lock queue and check for queue work */ ++ /* Lock queue */ + spin_lock_irqsave(&master->queue_lock, flags); ++ ++ /* Make sure we are not already running a message */ ++ if (master->cur_msg) { ++ spin_unlock_irqrestore(&master->queue_lock, flags); ++ return; ++ } ++ ++ /* Check if the queue is idle */ + if (list_empty(&master->queue) || !master->running) { + if (!master->busy) { + spin_unlock_irqrestore(&master->queue_lock, flags); +@@ -916,11 +924,6 @@ static void spi_pump_messages(struct kth + return; + } + +- /* Make sure we are not already running a message */ +- if (master->cur_msg) { +- spin_unlock_irqrestore(&master->queue_lock, flags); +- return; +- } + /* Extract head of queue */ + master->cur_msg = + list_first_entry(&master->queue, struct spi_message, queue); diff --git a/target/linux/generic/patches-3.18/092-02-spi-Pump-transfers-inside-calling-context-for-spi_sy.patch b/target/linux/generic/patches-3.18/092-02-spi-Pump-transfers-inside-calling-context-for-spi_sy.patch new file mode 100644 index 0000000..b74b4cb --- /dev/null +++ b/target/linux/generic/patches-3.18/092-02-spi-Pump-transfers-inside-calling-context-for-spi_sy.patch @@ -0,0 +1,184 @@ +From: Mark Brown +Date: Tue, 9 Dec 2014 21:38:05 +0000 +Subject: [PATCH] spi: Pump transfers inside calling context for spi_sync() + +If we are using the standard SPI message pump (which all drivers should be +transitioning over to) then special case the message enqueue and instead of +starting the worker thread to push messages to the hardware do so in the +context of the caller if the controller is idle. This avoids a context +switch in the common case where the controller has a single user in a +single thread, for short PIO transfers there may be no need to context +switch away from the calling context to complete the transfer. + +The code is a bit more complex than is desirable in part due to the need +to handle drivers not using the standard queue and in part due to handling +the various combinations of bus locking and asynchronous submission in +interrupt context. + +It is still suboptimal since it will still wake the message pump for each +transfer in order to schedule idling of the hardware and if multiple +contexts are using the controller simultaneously a caller may end up +pumping a message for some random other thread rather than for itself, +and if the thread ends up deferring due to another context idling the +hardware then it will just busy wait. It can, however, have the benefit +of aggregating power up and down of the hardware when a caller performs +a series of transfers back to back without any need for the use of +spi_async(). + +Signed-off-by: Mark Brown +--- + +--- a/drivers/spi/spi.c ++++ b/drivers/spi/spi.c +@@ -882,6 +882,9 @@ EXPORT_SYMBOL_GPL(spi_finalize_current_t + * needs processing and if so call out to the driver to initialize hardware + * and transfer each message. + * ++ * Note that it is called both from the kthread itself and also from ++ * inside spi_sync(); the queue extraction handling at the top of the ++ * function should deal with this safely. + */ + static void spi_pump_messages(struct kthread_work *work) + { +@@ -900,6 +903,13 @@ static void spi_pump_messages(struct kth + return; + } + ++ /* If another context is idling the device then defer */ ++ if (master->idling) { ++ queue_kthread_work(&master->kworker, &master->pump_messages); ++ spin_unlock_irqrestore(&master->queue_lock, flags); ++ return; ++ } ++ + /* Check if the queue is idle */ + if (list_empty(&master->queue) || !master->running) { + if (!master->busy) { +@@ -907,7 +917,9 @@ static void spi_pump_messages(struct kth + return; + } + master->busy = false; ++ master->idling = true; + spin_unlock_irqrestore(&master->queue_lock, flags); ++ + kfree(master->dummy_rx); + master->dummy_rx = NULL; + kfree(master->dummy_tx); +@@ -921,6 +933,10 @@ static void spi_pump_messages(struct kth + pm_runtime_put_autosuspend(master->dev.parent); + } + trace_spi_master_idle(master); ++ ++ spin_lock_irqsave(&master->queue_lock, flags); ++ master->idling = false; ++ spin_unlock_irqrestore(&master->queue_lock, flags); + return; + } + +@@ -1166,12 +1182,9 @@ static int spi_destroy_queue(struct spi_ + return 0; + } + +-/** +- * spi_queued_transfer - transfer function for queued transfers +- * @spi: spi device which is requesting transfer +- * @msg: spi message which is to handled is queued to driver queue +- */ +-static int spi_queued_transfer(struct spi_device *spi, struct spi_message *msg) ++static int __spi_queued_transfer(struct spi_device *spi, ++ struct spi_message *msg, ++ bool need_pump) + { + struct spi_master *master = spi->master; + unsigned long flags; +@@ -1186,13 +1199,23 @@ static int spi_queued_transfer(struct sp + msg->status = -EINPROGRESS; + + list_add_tail(&msg->queue, &master->queue); +- if (!master->busy) ++ if (!master->busy && need_pump) + queue_kthread_work(&master->kworker, &master->pump_messages); + + spin_unlock_irqrestore(&master->queue_lock, flags); + return 0; + } + ++/** ++ * spi_queued_transfer - transfer function for queued transfers ++ * @spi: spi device which is requesting transfer ++ * @msg: spi message which is to handled is queued to driver queue ++ */ ++static int spi_queued_transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ return __spi_queued_transfer(spi, msg, true); ++} ++ + static int spi_master_initialize_queue(struct spi_master *master) + { + int ret; +@@ -2104,19 +2127,46 @@ static int __spi_sync(struct spi_device + DECLARE_COMPLETION_ONSTACK(done); + int status; + struct spi_master *master = spi->master; ++ unsigned long flags; ++ ++ status = __spi_validate(spi, message); ++ if (status != 0) ++ return status; + + message->complete = spi_complete; + message->context = &done; ++ message->spi = spi; + + if (!bus_locked) + mutex_lock(&master->bus_lock_mutex); + +- status = spi_async_locked(spi, message); ++ /* If we're not using the legacy transfer method then we will ++ * try to transfer in the calling context so special case. ++ * This code would be less tricky if we could remove the ++ * support for driver implemented message queues. ++ */ ++ if (master->transfer == spi_queued_transfer) { ++ spin_lock_irqsave(&master->bus_lock_spinlock, flags); ++ ++ trace_spi_message_submit(message); ++ ++ status = __spi_queued_transfer(spi, message, false); ++ ++ spin_unlock_irqrestore(&master->bus_lock_spinlock, flags); ++ } else { ++ status = spi_async_locked(spi, message); ++ } + + if (!bus_locked) + mutex_unlock(&master->bus_lock_mutex); + + if (status == 0) { ++ /* Push out the messages in the calling context if we ++ * can. ++ */ ++ if (master->transfer == spi_queued_transfer) ++ spi_pump_messages(&master->pump_messages); ++ + wait_for_completion(&done); + status = message->status; + } +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -260,6 +260,7 @@ static inline void spi_unregister_driver + * @pump_messages: work struct for scheduling work to the message pump + * @queue_lock: spinlock to syncronise access to message queue + * @queue: message queue ++ * @idling: the device is entering idle state + * @cur_msg: the currently in-flight message + * @cur_msg_prepared: spi_prepare_message was called for the currently + * in-flight message +@@ -425,6 +426,7 @@ struct spi_master { + spinlock_t queue_lock; + struct list_head queue; + struct spi_message *cur_msg; ++ bool idling; + bool busy; + bool running; + bool rt; diff --git a/target/linux/generic/patches-3.18/092-03-spi-Only-idle-the-message-pump-in-the-worker-kthread.patch b/target/linux/generic/patches-3.18/092-03-spi-Only-idle-the-message-pump-in-the-worker-kthread.patch new file mode 100644 index 0000000..a5d85be --- /dev/null +++ b/target/linux/generic/patches-3.18/092-03-spi-Only-idle-the-message-pump-in-the-worker-kthread.patch @@ -0,0 +1,83 @@ +From: Mark Brown +Date: Wed, 10 Dec 2014 13:46:33 +0000 +Subject: [PATCH] spi: Only idle the message pump in the worker kthread + +In order to avoid the situation where the kthread is waiting for another +context to make the hardware idle let the message pump know if it's being +called from the worker thread context and if it isn't then defer to the +worker thread instead of idling the hardware immediately. This will ensure +that if this situation happens we block rather than busy waiting. + +Signed-off-by: Mark Brown +--- + +--- a/drivers/spi/spi.c ++++ b/drivers/spi/spi.c +@@ -875,8 +875,9 @@ void spi_finalize_current_transfer(struc + EXPORT_SYMBOL_GPL(spi_finalize_current_transfer); + + /** +- * spi_pump_messages - kthread work function which processes spi message queue +- * @work: pointer to kthread work struct contained in the master struct ++ * __spi_pump_messages - function which processes spi message queue ++ * @master: master to process queue for ++ * @in_kthread: true if we are in the context of the message pump thread + * + * This function checks if there is any spi message in the queue that + * needs processing and if so call out to the driver to initialize hardware +@@ -886,10 +887,8 @@ EXPORT_SYMBOL_GPL(spi_finalize_current_t + * inside spi_sync(); the queue extraction handling at the top of the + * function should deal with this safely. + */ +-static void spi_pump_messages(struct kthread_work *work) ++static void __spi_pump_messages(struct spi_master *master, bool in_kthread) + { +- struct spi_master *master = +- container_of(work, struct spi_master, pump_messages); + unsigned long flags; + bool was_busy = false; + int ret; +@@ -916,6 +915,15 @@ static void spi_pump_messages(struct kth + spin_unlock_irqrestore(&master->queue_lock, flags); + return; + } ++ ++ /* Only do teardown in the thread */ ++ if (!in_kthread) { ++ queue_kthread_work(&master->kworker, ++ &master->pump_messages); ++ spin_unlock_irqrestore(&master->queue_lock, flags); ++ return; ++ } ++ + master->busy = false; + master->idling = true; + spin_unlock_irqrestore(&master->queue_lock, flags); +@@ -1004,6 +1012,18 @@ static void spi_pump_messages(struct kth + } + } + ++/** ++ * spi_pump_messages - kthread work function which processes spi message queue ++ * @work: pointer to kthread work struct contained in the master struct ++ */ ++static void spi_pump_messages(struct kthread_work *work) ++{ ++ struct spi_master *master = ++ container_of(work, struct spi_master, pump_messages); ++ ++ __spi_pump_messages(master, true); ++} ++ + static int spi_init_queue(struct spi_master *master) + { + struct sched_param param = { .sched_priority = MAX_RT_PRIO - 1 }; +@@ -2165,7 +2185,7 @@ static int __spi_sync(struct spi_device + * can. + */ + if (master->transfer == spi_queued_transfer) +- spi_pump_messages(&master->pump_messages); ++ __spi_pump_messages(master, false); + + wait_for_completion(&done); + status = message->status; diff --git a/target/linux/generic/patches-3.18/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch b/target/linux/generic/patches-3.18/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch new file mode 100644 index 0000000..4c5cd59 --- /dev/null +++ b/target/linux/generic/patches-3.18/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch @@ -0,0 +1,146 @@ +From 279c6c7fa64f5763e6b9f05e7ab3840092e702e7 Mon Sep 17 00:00:00 2001 +From: Stephen Hemminger +Date: Mon, 29 Jun 2015 14:57:48 -1000 +Subject: [PATCH] api: fix compatibility of linux/in.h with netinet/in.h + +u +This fixes breakage to iproute2 build with recent kernel headers +caused by: + commit a263653ed798216c0069922d7b5237ca49436007 + Author: Pablo Neira Ayuso + Date: Wed Jun 17 10:28:27 2015 -0500 + + netfilter: don't pull include/linux/netfilter.h from netns headers + +The issue is that definitions in linux/in.h overlap with those +in netinet/in.h. This patch solves this by introducing the same +mechanism as was used to solve the same problem with linux/in6.h + +Signed-off-by: Stephen Hemminger +Signed-off-by: David S. Miller +--- + include/uapi/linux/in.h | 16 +++++++++++++--- + include/uapi/linux/libc-compat.h | 22 ++++++++++++++++++++++ + 2 files changed, 35 insertions(+), 3 deletions(-) + +--- a/include/uapi/linux/in.h ++++ b/include/uapi/linux/in.h +@@ -19,8 +19,10 @@ + #define _UAPI_LINUX_IN_H + + #include ++#include + #include + ++#if __UAPI_DEF_IN_IPPROTO + /* Standard well-defined IP protocols. */ + enum { + IPPROTO_IP = 0, /* Dummy protocol for TCP */ +@@ -73,12 +75,14 @@ enum { + #define IPPROTO_RAW IPPROTO_RAW + IPPROTO_MAX + }; ++#endif + +- ++#if __UAPI_DEF_IN_ADDR + /* Internet address. */ + struct in_addr { + __be32 s_addr; + }; ++#endif + + #define IP_TOS 1 + #define IP_TTL 2 +@@ -154,6 +158,7 @@ struct in_addr { + + /* Request struct for multicast socket ops */ + ++#if __UAPI_DEF_IP_MREQ + struct ip_mreq { + struct in_addr imr_multiaddr; /* IP multicast address of group */ + struct in_addr imr_interface; /* local IP address of interface */ +@@ -205,14 +210,18 @@ struct group_filter { + #define GROUP_FILTER_SIZE(numsrc) \ + (sizeof(struct group_filter) - sizeof(struct __kernel_sockaddr_storage) \ + + (numsrc) * sizeof(struct __kernel_sockaddr_storage)) ++#endif + ++#if __UAPI_DEF_IN_PKTINFO + struct in_pktinfo { + int ipi_ifindex; + struct in_addr ipi_spec_dst; + struct in_addr ipi_addr; + }; ++#endif + + /* Structure describing an Internet (IP) socket address. */ ++#if __UAPI_DEF_SOCKADDR_IN + #define __SOCK_SIZE__ 16 /* sizeof(struct sockaddr) */ + struct sockaddr_in { + __kernel_sa_family_t sin_family; /* Address family */ +@@ -224,8 +233,9 @@ struct sockaddr_in { + sizeof(unsigned short int) - sizeof(struct in_addr)]; + }; + #define sin_zero __pad /* for BSD UNIX comp. -FvK */ ++#endif + +- ++#if __UAPI_DEF_IN_CLASS + /* + * Definitions of the bits in an Internet address integer. + * On subnets, host and network parts are found according +@@ -276,7 +286,7 @@ struct sockaddr_in { + #define INADDR_ALLHOSTS_GROUP 0xe0000001U /* 224.0.0.1 */ + #define INADDR_ALLRTRS_GROUP 0xe0000002U /* 224.0.0.2 */ + #define INADDR_MAX_LOCAL_GROUP 0xe00000ffU /* 224.0.0.255 */ +- ++#endif + + /* contains the htonl type stuff.. */ + #include +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -56,6 +56,13 @@ + + /* GLIBC headers included first so don't define anything + * that would already be defined. */ ++#define __UAPI_DEF_IN_ADDR 0 ++#define __UAPI_DEF_IN_IPPROTO 0 ++#define __UAPI_DEF_IN_PKTINFO 0 ++#define __UAPI_DEF_IP_MREQ 0 ++#define __UAPI_DEF_SOCKADDR_IN 0 ++#define __UAPI_DEF_IN_CLASS 0 ++ + #define __UAPI_DEF_IN6_ADDR 0 + /* The exception is the in6_addr macros which must be defined + * if the glibc code didn't define them. This guard matches +@@ -76,6 +83,13 @@ + /* Linux headers included first, and we must define everything + * we need. The expectation is that glibc will check the + * __UAPI_DEF_* defines and adjust appropriately. */ ++#define __UAPI_DEF_IN_ADDR 1 ++#define __UAPI_DEF_IN_IPPROTO 1 ++#define __UAPI_DEF_IN_PKTINFO 1 ++#define __UAPI_DEF_IP_MREQ 1 ++#define __UAPI_DEF_SOCKADDR_IN 1 ++#define __UAPI_DEF_IN_CLASS 1 ++ + #define __UAPI_DEF_IN6_ADDR 1 + /* We unconditionally define the in6_addr macros and glibc must + * coordinate. */ +@@ -99,6 +113,14 @@ + * that we need. */ + #else /* !defined(__GLIBC__) */ + ++/* Definitions for in.h */ ++#define __UAPI_DEF_IN_ADDR 1 ++#define __UAPI_DEF_IN_IPPROTO 1 ++#define __UAPI_DEF_IN_PKTINFO 1 ++#define __UAPI_DEF_IP_MREQ 1 ++#define __UAPI_DEF_SOCKADDR_IN 1 ++#define __UAPI_DEF_IN_CLASS 1 ++ + /* Definitions for in6.h */ + #define __UAPI_DEF_IN6_ADDR 1 + #define __UAPI_DEF_IN6_ADDR_ALT 1 diff --git a/target/linux/generic/patches-3.18/099-module_arch_freeing_init-new-hook-for-archs-before-m.patch b/target/linux/generic/patches-3.18/099-module_arch_freeing_init-new-hook-for-archs-before-m.patch new file mode 100644 index 0000000..d00f751 --- /dev/null +++ b/target/linux/generic/patches-3.18/099-module_arch_freeing_init-new-hook-for-archs-before-m.patch @@ -0,0 +1,182 @@ +From: Rusty Russell +Date: Tue, 20 Jan 2015 09:07:04 +1030 +Subject: [PATCH] module_arch_freeing_init(): new hook for archs before module->module_init freed. + +Archs have been abusing module_free() to clean up their arch-specific +allocations. Since module_free() is also (ab)used by BPF and trace code, +let's keep it to simple allocations, and provide a hook called before +that. + +This means that avr32, ia64, parisc and s390 no longer need to implement +their own module_free() at all. avr32 doesn't need module_finalize() +either. + +Signed-off-by: Rusty Russell +Cc: Chris Metcalf +Cc: Haavard Skinnemoen +Cc: Hans-Christian Egtvedt +Cc: Tony Luck +Cc: Fenghua Yu +Cc: "James E.J. Bottomley" +Cc: Helge Deller +Cc: Martin Schwidefsky +Cc: Heiko Carstens +Cc: linux-kernel@vger.kernel.org +Cc: linux-ia64@vger.kernel.org +Cc: linux-parisc@vger.kernel.org +Cc: linux-s390@vger.kernel.org + +Origin: backport, https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=d453cded05ee219b77815ea194dc36efa5398bca +--- + arch/avr32/kernel/module.c | 13 +------------ + arch/ia64/kernel/module.c | 6 ++---- + arch/parisc/kernel/module.c | 6 +----- + arch/s390/kernel/module.c | 10 +++------- + arch/tile/kernel/module.c | 2 +- + include/linux/moduleloader.h | 2 ++ + kernel/module.c | 7 +++++++ + 7 files changed, 17 insertions(+), 29 deletions(-) + +--- a/arch/avr32/kernel/module.c ++++ b/arch/avr32/kernel/module.c +@@ -19,12 +19,10 @@ + #include + #include + +-void module_free(struct module *mod, void *module_region) ++void module_arch_freeing_init(struct module *mod) + { + vfree(mod->arch.syminfo); + mod->arch.syminfo = NULL; +- +- vfree(module_region); + } + + static inline int check_rela(Elf32_Rela *rela, struct module *module, +@@ -291,12 +289,3 @@ int apply_relocate_add(Elf32_Shdr *sechd + + return ret; + } +- +-int module_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, +- struct module *module) +-{ +- vfree(module->arch.syminfo); +- module->arch.syminfo = NULL; +- +- return 0; +-} +--- a/arch/ia64/kernel/module.c ++++ b/arch/ia64/kernel/module.c +@@ -305,14 +305,12 @@ plt_target (struct plt_entry *plt) + #endif /* !USE_BRL */ + + void +-module_free (struct module *mod, void *module_region) ++module_arch_freeing_init (struct module *mod) + { +- if (mod && mod->arch.init_unw_table && +- module_region == mod->module_init) { ++ if (mod->arch.init_unw_table) { + unw_remove_unwind_table(mod->arch.init_unw_table); + mod->arch.init_unw_table = NULL; + } +- vfree(module_region); + } + + /* Have we already seen one of these relocations? */ +--- a/arch/parisc/kernel/module.c ++++ b/arch/parisc/kernel/module.c +@@ -298,14 +298,10 @@ static inline unsigned long count_stubs( + } + #endif + +- +-/* Free memory returned from module_alloc */ +-void module_free(struct module *mod, void *module_region) ++void module_arch_freeing_init(struct module *mod) + { + kfree(mod->arch.section); + mod->arch.section = NULL; +- +- vfree(module_region); + } + + /* Additional bytes needed in front of individual sections */ +--- a/arch/s390/kernel/module.c ++++ b/arch/s390/kernel/module.c +@@ -55,14 +55,10 @@ void *module_alloc(unsigned long size) + } + #endif + +-/* Free memory returned from module_alloc */ +-void module_free(struct module *mod, void *module_region) ++void module_arch_freeing_init(struct module *mod) + { +- if (mod) { +- vfree(mod->arch.syminfo); +- mod->arch.syminfo = NULL; +- } +- vfree(module_region); ++ vfree(mod->arch.syminfo); ++ mod->arch.syminfo = NULL; + } + + static void check_rela(Elf_Rela *rela, struct module *me) +--- a/arch/tile/kernel/module.c ++++ b/arch/tile/kernel/module.c +@@ -83,7 +83,7 @@ void module_free(struct module *mod, voi + 0, 0, 0, NULL, NULL, 0); + + /* +- * FIXME: If module_region == mod->module_init, trim exception ++ * FIXME: Add module_arch_freeing_init to trim exception + * table entries. + */ + } +--- a/include/linux/moduleloader.h ++++ b/include/linux/moduleloader.h +@@ -82,4 +82,6 @@ int module_finalize(const Elf_Ehdr *hdr, + /* Any cleanup needed when module leaves. */ + void module_arch_cleanup(struct module *mod); + ++/* Any cleanup before freeing mod->module_init */ ++void module_arch_freeing_init(struct module *mod); + #endif +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -1833,6 +1833,10 @@ void __weak module_arch_cleanup(struct m + { + } + ++void __weak module_arch_freeing_init(struct module *mod) ++{ ++} ++ + /* Free a module, remove from lists, etc. */ + static void free_module(struct module *mod) + { +@@ -1865,6 +1869,7 @@ static void free_module(struct module *m + + /* This may be NULL, but that's OK */ + unset_module_init_ro_nx(mod); ++ module_arch_freeing_init(mod); + module_free(mod, mod->module_init); + kfree(mod->args); + percpu_modfree(mod); +@@ -2954,6 +2959,7 @@ static struct module *layout_and_allocat + static void module_deallocate(struct module *mod, struct load_info *info) + { + percpu_modfree(mod); ++ module_arch_freeing_init(mod); + module_free(mod, mod->module_init); + module_free(mod, mod->module_core); + } +@@ -3077,6 +3083,7 @@ static int do_init_module(struct module + mod->strtab = mod->core_strtab; + #endif + unset_module_init_ro_nx(mod); ++ module_arch_freeing_init(mod); + module_free(mod, mod->module_init); + mod->module_init = NULL; + mod->init_size = 0; diff --git a/target/linux/generic/patches-3.18/100-pppoe-drop-pppoe-device-in-pppoe_unbind_sock_work.patch b/target/linux/generic/patches-3.18/100-pppoe-drop-pppoe-device-in-pppoe_unbind_sock_work.patch new file mode 100644 index 0000000..c461b3e --- /dev/null +++ b/target/linux/generic/patches-3.18/100-pppoe-drop-pppoe-device-in-pppoe_unbind_sock_work.patch @@ -0,0 +1,27 @@ +From: Felix Fietkau +Date: Sat, 9 May 2015 23:03:47 +0200 +Subject: [PATCH] pppoe: drop pppoe device in pppoe_unbind_sock_work + +After receiving a PADT and the socket is closed, user space will no +longer drop the reference to the pppoe device. +This leads to errors like this: + +[ 488.570000] unregister_netdevice: waiting for eth0.2 to become free. Usage count = 2 + +Fixes: 287f3a943fe ("pppoe: Use workqueue to die properly when a PADT is received") +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -462,6 +462,10 @@ static void pppoe_unbind_sock_work(struc + struct sock *sk = sk_pppox(po); + + lock_sock(sk); ++ if (po->pppoe_dev) { ++ dev_put(po->pppoe_dev); ++ po->pppoe_dev = NULL; ++ } + pppox_unbind_sock(sk); + release_sock(sk); + sock_put(sk); diff --git a/target/linux/generic/patches-3.18/101-pppoe-fix-disconnect-crash.patch b/target/linux/generic/patches-3.18/101-pppoe-fix-disconnect-crash.patch new file mode 100644 index 0000000..f2e6e45 --- /dev/null +++ b/target/linux/generic/patches-3.18/101-pppoe-fix-disconnect-crash.patch @@ -0,0 +1,16 @@ +Fix crash with actions performed on the underlying interface (MAC address, +MTU or link state update). This triggers pppoe_flush_dev(), which cleans up +the device without announcing it in sk->sk_state. + +Patch by Guillaume Nault (pulled from netdev@vger) + +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -313,7 +313,6 @@ static void pppoe_flush_dev(struct net_d + if (po->pppoe_dev == dev && + sk->sk_state & (PPPOX_CONNECTED | PPPOX_BOUND | PPPOX_ZOMBIE)) { + pppox_unbind_sock(sk); +- sk->sk_state = PPPOX_ZOMBIE; + sk->sk_state_change(sk); + po->pppoe_dev = NULL; + dev_put(dev); diff --git a/target/linux/generic/patches-3.18/102-ehci_hcd_ignore_oc.patch b/target/linux/generic/patches-3.18/102-ehci_hcd_ignore_oc.patch new file mode 100644 index 0000000..a564559 --- /dev/null +++ b/target/linux/generic/patches-3.18/102-ehci_hcd_ignore_oc.patch @@ -0,0 +1,82 @@ +From 1e311820ec3055e3f08e687de6564692a7cec675 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:29 +0100 +Subject: [PATCH 11/12] USB: EHCI: add ignore_oc flag to disable overcurrent + checking + +This patch adds an ignore_oc flag which can be set by EHCI controller +not supporting or wanting to disable overcurrent checking. The EHCI +platform data in include/linux/usb/ehci_pdriver.h is also augmented to +take advantage of this new flag. + +Signed-off-by: Florian Fainelli +--- + drivers/usb/host/ehci-hcd.c | 2 +- + drivers/usb/host/ehci-hub.c | 4 ++-- + drivers/usb/host/ehci-platform.c | 1 + + drivers/usb/host/ehci.h | 1 + + include/linux/usb/ehci_pdriver.h | 1 + + 5 files changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -633,7 +633,7 @@ static int ehci_run (struct usb_hcd *hcd + "USB %x.%x started, EHCI %x.%02x%s\n", + ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), + temp >> 8, temp & 0xff, +- ignore_oc ? ", overcurrent ignored" : ""); ++ (ignore_oc || ehci->ignore_oc) ? ", overcurrent ignored" : ""); + + ehci_writel(ehci, INTR_MASK, + &ehci->regs->intr_enable); /* Turn On Interrupts */ +--- a/drivers/usb/host/ehci-hub.c ++++ b/drivers/usb/host/ehci-hub.c +@@ -635,7 +635,7 @@ ehci_hub_status_data (struct usb_hcd *hc + * always set, seem to clear PORT_OCC and PORT_CSC when writing to + * PORT_POWER; that's surprising, but maybe within-spec. + */ +- if (!ignore_oc) ++ if (!ignore_oc && !ehci->ignore_oc) + mask = PORT_CSC | PORT_PEC | PORT_OCC; + else + mask = PORT_CSC | PORT_PEC; +@@ -995,7 +995,7 @@ int ehci_hub_control( + if (temp & PORT_PEC) + status |= USB_PORT_STAT_C_ENABLE << 16; + +- if ((temp & PORT_OCC) && !ignore_oc){ ++ if ((temp & PORT_OCC) && (!ignore_oc && !ehci->ignore_oc)){ + status |= USB_PORT_STAT_C_OVERCURRENT << 16; + + /* +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -226,6 +226,8 @@ static int ehci_platform_probe(struct pl + ehci->big_endian_desc = 1; + if (pdata->big_endian_mmio) + ehci->big_endian_mmio = 1; ++ if (pdata->ignore_oc) ++ ehci->ignore_oc = 1; + + #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO + if (ehci->big_endian_mmio) { +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -226,6 +226,7 @@ struct ehci_hcd { /* one per controlle + unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ + unsigned need_oc_pp_cycle:1; /* MPC834X port power */ + unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ ++ unsigned ignore_oc:1; + + /* required for usb32 quirk */ + #define OHCI_CTRL_HCFS (3 << 6) +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -45,6 +45,7 @@ struct usb_ehci_pdata { + unsigned big_endian_desc:1; + unsigned big_endian_mmio:1; + unsigned no_io_watchdog:1; ++ unsigned ignore_oc:1; + + /* Turn on all power and clocks */ + int (*power_on)(struct platform_device *pdev); diff --git a/target/linux/generic/patches-3.18/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch b/target/linux/generic/patches-3.18/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch new file mode 100644 index 0000000..4ffa3c2 --- /dev/null +++ b/target/linux/generic/patches-3.18/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch @@ -0,0 +1,86 @@ +From: Felix Fietkau +Date: Fri, 10 Apr 2015 13:35:29 +0200 +Subject: [PATCH] jffs2: use .rename2 and add RENAME_WHITEOUT support + +It is required for renames on overlayfs + +Signed-off-by: Felix Fietkau +--- + +--- a/fs/jffs2/dir.c ++++ b/fs/jffs2/dir.c +@@ -35,7 +35,7 @@ static int jffs2_mkdir (struct inode *,s + static int jffs2_rmdir (struct inode *,struct dentry *); + static int jffs2_mknod (struct inode *,struct dentry *,umode_t,dev_t); + static int jffs2_rename (struct inode *, struct dentry *, +- struct inode *, struct dentry *); ++ struct inode *, struct dentry *, unsigned int); + + const struct file_operations jffs2_dir_operations = + { +@@ -57,7 +57,7 @@ const struct inode_operations jffs2_dir_ + .mkdir = jffs2_mkdir, + .rmdir = jffs2_rmdir, + .mknod = jffs2_mknod, +- .rename = jffs2_rename, ++ .rename2 = jffs2_rename, + .get_acl = jffs2_get_acl, + .set_acl = jffs2_set_acl, + .setattr = jffs2_setattr, +@@ -756,8 +756,27 @@ static int jffs2_mknod (struct inode *di + return ret; + } + ++static int jffs2_whiteout(struct inode *old_dir, struct dentry *old_dentry) ++{ ++ struct dentry *wh; ++ int err; ++ ++ wh = d_alloc(old_dentry->d_parent, &old_dentry->d_name); ++ if (!wh) ++ return -ENOMEM; ++ ++ err = jffs2_mknod(old_dir, wh, S_IFCHR | WHITEOUT_MODE, ++ WHITEOUT_DEV); ++ if (err) ++ return err; ++ ++ d_rehash(wh); ++ return 0; ++} ++ + static int jffs2_rename (struct inode *old_dir_i, struct dentry *old_dentry, +- struct inode *new_dir_i, struct dentry *new_dentry) ++ struct inode *new_dir_i, struct dentry *new_dentry, ++ unsigned int flags) + { + int ret; + struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb); +@@ -765,6 +784,9 @@ static int jffs2_rename (struct inode *o + uint8_t type; + uint32_t now; + ++ if (flags & ~RENAME_WHITEOUT) ++ return -EINVAL; ++ + /* The VFS will check for us and prevent trying to rename a + * file over a directory and vice versa, but if it's a directory, + * the VFS can't check whether the victim is empty. The filesystem +@@ -828,9 +850,14 @@ static int jffs2_rename (struct inode *o + if (S_ISDIR(old_dentry->d_inode->i_mode) && !victim_f) + inc_nlink(new_dir_i); + +- /* Unlink the original */ +- ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), +- old_dentry->d_name.name, old_dentry->d_name.len, NULL, now); ++ if (flags & RENAME_WHITEOUT) ++ /* Replace with whiteout */ ++ ret = jffs2_whiteout(old_dir_i, old_dentry); ++ else ++ /* Unlink the original */ ++ ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), ++ old_dentry->d_name.name, ++ old_dentry->d_name.len, NULL, now); + + /* We don't touch inode->i_nlink */ + diff --git a/target/linux/generic/patches-3.18/111-jffs2-add-RENAME_EXCHANGE-support.patch b/target/linux/generic/patches-3.18/111-jffs2-add-RENAME_EXCHANGE-support.patch new file mode 100644 index 0000000..df208da --- /dev/null +++ b/target/linux/generic/patches-3.18/111-jffs2-add-RENAME_EXCHANGE-support.patch @@ -0,0 +1,58 @@ +From: Felix Fietkau +Date: Sat, 25 Apr 2015 12:41:32 +0200 +Subject: [PATCH] jffs2: add RENAME_EXCHANGE support + +Signed-off-by: Felix Fietkau +--- + +--- a/fs/jffs2/dir.c ++++ b/fs/jffs2/dir.c +@@ -784,7 +784,7 @@ static int jffs2_rename (struct inode *o + uint8_t type; + uint32_t now; + +- if (flags & ~RENAME_WHITEOUT) ++ if (flags & ~(RENAME_WHITEOUT | RENAME_EXCHANGE)) + return -EINVAL; + + /* The VFS will check for us and prevent trying to rename a +@@ -792,7 +792,7 @@ static int jffs2_rename (struct inode *o + * the VFS can't check whether the victim is empty. The filesystem + * needs to do that for itself. + */ +- if (new_dentry->d_inode) { ++ if (new_dentry->d_inode && !(flags & RENAME_EXCHANGE)) { + victim_f = JFFS2_INODE_INFO(new_dentry->d_inode); + if (S_ISDIR(new_dentry->d_inode->i_mode)) { + struct jffs2_full_dirent *fd; +@@ -827,7 +827,7 @@ static int jffs2_rename (struct inode *o + if (ret) + return ret; + +- if (victim_f) { ++ if (victim_f && !(flags & RENAME_EXCHANGE)) { + /* There was a victim. Kill it off nicely */ + if (S_ISDIR(new_dentry->d_inode->i_mode)) + clear_nlink(new_dentry->d_inode); +@@ -853,6 +853,12 @@ static int jffs2_rename (struct inode *o + if (flags & RENAME_WHITEOUT) + /* Replace with whiteout */ + ret = jffs2_whiteout(old_dir_i, old_dentry); ++ else if (flags & RENAME_EXCHANGE) ++ /* Replace the original */ ++ ret = jffs2_do_link(c, JFFS2_INODE_INFO(old_dir_i), ++ new_dentry->d_inode->i_ino, type, ++ old_dentry->d_name.name, old_dentry->d_name.len, ++ now); + else + /* Unlink the original */ + ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), +@@ -879,7 +885,7 @@ static int jffs2_rename (struct inode *o + return ret; + } + +- if (S_ISDIR(old_dentry->d_inode->i_mode)) ++ if (S_ISDIR(old_dentry->d_inode->i_mode) && !(flags & RENAME_EXCHANGE)) + drop_nlink(old_dir_i); + + new_dir_i->i_mtime = new_dir_i->i_ctime = old_dir_i->i_mtime = old_dir_i->i_ctime = ITIME(now); diff --git a/target/linux/generic/patches-3.18/120-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/patches-3.18/120-bridge_allow_receiption_on_disabled_port.patch new file mode 100644 index 0000000..d80ef18 --- /dev/null +++ b/target/linux/generic/patches-3.18/120-bridge_allow_receiption_on_disabled_port.patch @@ -0,0 +1,54 @@ +From: Stephen Hemminger +Subject: bridge: allow receiption on disabled port + +When an ethernet device is enslaved to a bridge, and the bridge STP +detects loss of carrier (or operational state down), then normally +packet receiption is blocked. + +This breaks control applications like WPA which maybe expecting to +receive packets to negotiate to bring link up. The bridge needs to +block forwarding packets from these disabled ports, but there is no +hard requirement to not allow local packet delivery. + +Signed-off-by: Stephen Hemminger +Signed-off-by: Felix Fietkau + +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -146,11 +146,13 @@ EXPORT_SYMBOL_GPL(br_handle_frame_finish + static int br_handle_local_finish(struct sk_buff *skb) + { + struct net_bridge_port *p = br_port_get_rcu(skb->dev); +- u16 vid = 0; ++ if (p->state != BR_STATE_DISABLED) { ++ u16 vid = 0; + +- /* check if vlan is allowed, to avoid spoofing */ +- if (p->flags & BR_LEARNING && br_should_learn(p, skb, &vid)) +- br_fdb_update(p->br, p, eth_hdr(skb)->h_source, vid, false); ++ /* check if vlan is allowed, to avoid spoofing */ ++ if (p->flags & BR_LEARNING && br_should_learn(p, skb, &vid)) ++ br_fdb_update(p->br, p, eth_hdr(skb)->h_source, vid, false); ++ } + return 0; /* process further */ + } + +@@ -224,6 +226,18 @@ rx_handler_result_t br_handle_frame(stru + + forward: + switch (p->state) { ++ case BR_STATE_DISABLED: ++ if (ether_addr_equal(p->br->dev->dev_addr, dest)) ++ skb->pkt_type = PACKET_HOST; ++ ++ if (NF_HOOK(NFPROTO_BRIDGE, NF_BR_PRE_ROUTING, skb, skb->dev, NULL, ++ br_handle_local_finish)) ++ break; ++ ++ BR_INPUT_SKB_CB(skb)->brdev = p->br->dev; ++ br_pass_frame_up(skb); ++ break; ++ + case BR_STATE_FORWARDING: + rhook = rcu_dereference(br_should_route_hook); + if (rhook) { diff --git a/target/linux/generic/patches-3.18/132-mips_inline_dma_ops.patch b/target/linux/generic/patches-3.18/132-mips_inline_dma_ops.patch new file mode 100644 index 0000000..8795bde --- /dev/null +++ b/target/linux/generic/patches-3.18/132-mips_inline_dma_ops.patch @@ -0,0 +1,688 @@ +From 2c58080407554e1bac8fd50d23cb02420524caed Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Mon, 12 Aug 2013 12:50:22 +0200 +Subject: [PATCH] MIPS: partially inline dma ops + +Several DMA ops are no-op on many platforms, and the indirection through +the mips_dma_map_ops function table is causing the compiler to emit +unnecessary code. + +Inlining visibly improves network performance in my tests (on a 24Kc +based system), and also slightly reduces code size of a few drivers. + +Signed-off-by: Felix Fietkau +--- + arch/mips/Kconfig | 4 + + arch/mips/include/asm/dma-mapping.h | 360 +++++++++++++++++++++++++++++++++++- + arch/mips/mm/dma-default.c | 163 ++-------------- + 3 files changed, 373 insertions(+), 154 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1450,6 +1450,7 @@ config CPU_CAVIUM_OCTEON + select CPU_SUPPORTS_HUGEPAGES + select USB_EHCI_BIG_ENDIAN_MMIO + select MIPS_L1_CACHE_SHIFT_7 ++ select SYS_HAS_DMA_OPS + help + The Cavium Octeon processor is a highly integrated chip containing + many ethernet hardware widgets for networking tasks. The processor +@@ -1705,6 +1706,9 @@ config MIPS_MALTA_PM + bool + default y + ++config SYS_HAS_DMA_OPS ++ bool ++ + # + # CPU may reorder R->R, R->W, W->R, W->W + # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC +--- a/arch/mips/include/asm/dma-mapping.h ++++ b/arch/mips/include/asm/dma-mapping.h +@@ -1,9 +1,16 @@ + #ifndef _ASM_DMA_MAPPING_H + #define _ASM_DMA_MAPPING_H + ++#include ++#include ++#include ++#include ++#include ++ + #include + #include + #include ++#include + #include + + #ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */ +@@ -12,12 +19,48 @@ + + extern struct dma_map_ops *mips_dma_map_ops; + ++void __dma_sync(struct page *page, unsigned long offset, size_t size, ++ enum dma_data_direction direction); ++void *mips_dma_alloc_coherent(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp, ++ struct dma_attrs *attrs); ++void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, ++ dma_addr_t dma_handle, struct dma_attrs *attrs); ++ + static inline struct dma_map_ops *get_dma_ops(struct device *dev) + { ++#ifdef CONFIG_SYS_HAS_DMA_OPS + if (dev && dev->archdata.dma_ops) + return dev->archdata.dma_ops; + else + return mips_dma_map_ops; ++#else ++ return NULL; ++#endif ++} ++ ++/* ++ * Warning on the terminology - Linux calls an uncached area coherent; ++ * MIPS terminology calls memory areas with hardware maintained coherency ++ * coherent. ++ */ ++ ++static inline int cpu_needs_post_dma_flush(struct device *dev) ++{ ++#ifndef CONFIG_SYS_HAS_CPU_R10000 ++ return 0; ++#endif ++ return !plat_device_is_coherent(dev) && ++ (boot_cpu_type() == CPU_R10000 || ++ boot_cpu_type() == CPU_R12000 || ++ boot_cpu_type() == CPU_BMIPS5000); ++} ++ ++static inline struct page *dma_addr_to_page(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return pfn_to_page( ++ plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); + } + + static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) +@@ -30,12 +73,304 @@ static inline bool dma_capable(struct de + + static inline void dma_mark_clean(void *addr, size_t size) {} + +-#include ++static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr, ++ size_t size, ++ enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ unsigned long offset = (unsigned long)ptr & ~PAGE_MASK; ++ struct page *page = virt_to_page(ptr); ++ dma_addr_t addr; ++ ++ kmemcheck_mark_initialized(ptr, size); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ addr = ops->map_page(dev, page, offset, size, dir, attrs); ++ } else { ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, offset, size, dir); ++ ++ addr = plat_map_dma_mem_page(dev, page) + offset; ++ } ++ debug_dma_map_page(dev, page, offset, size, dir, addr, true); ++ return addr; ++} ++ ++static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr, ++ size_t size, ++ enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->unmap_page(dev, addr, size, dir, attrs); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ ++ plat_unmap_dma_mem(dev, addr, size, dir); ++ } ++ debug_dma_unmap_page(dev, addr, size, dir, true); ++} ++ ++static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, ++ int nents, enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ int i, ents; ++ struct scatterlist *s; ++ ++ for_each_sg(sg, s, nents, i) ++ kmemcheck_mark_initialized(sg_virt(s), s->length); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ents = ops->map_sg(dev, sg, nents, dir, attrs); ++ } else { ++ for_each_sg(sg, s, nents, i) { ++ struct page *page = sg_page(s); ++ ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, s->offset, s->length, dir); ++#ifdef CONFIG_NEED_SG_DMA_LENGTH ++ s->dma_length = s->length; ++#endif ++ s->dma_address = ++ plat_map_dma_mem_page(dev, page) + s->offset; ++ } ++ ents = nents; ++ } ++ debug_dma_map_sg(dev, sg, nents, ents, dir); ++ ++ return ents; ++} ++ ++static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, ++ int nents, enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ debug_dma_unmap_sg(dev, sg, nents, dir); ++ if (ops) { ++ ops->unmap_sg(dev, sg, nents, dir, attrs); ++ return; ++ } ++ ++ for_each_sg(sg, s, nents, i) { ++ if (!plat_device_is_coherent(dev) && dir != DMA_TO_DEVICE) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ plat_unmap_dma_mem(dev, s->dma_address, s->length, dir); ++ } ++} ++ ++static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, ++ size_t offset, size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ dma_addr_t addr; ++ ++ kmemcheck_mark_initialized(page_address(page) + offset, size); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ addr = ops->map_page(dev, page, offset, size, dir, NULL); ++ } else { ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, offset, size, dir); ++ ++ addr = plat_map_dma_mem_page(dev, page) + offset; ++ } ++ debug_dma_map_page(dev, page, offset, size, dir, addr, false); ++ ++ return addr; ++} ++ ++static inline void dma_unmap_page(struct device *dev, dma_addr_t addr, ++ size_t size, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->unmap_page(dev, addr, size, dir, NULL); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ ++ plat_unmap_dma_mem(dev, addr, size, dir); ++ } ++ debug_dma_unmap_page(dev, addr, size, dir, false); ++} ++ ++static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_cpu(dev, addr, size, dir); ++ else if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_for_cpu(dev, addr, size, dir); ++} ++ ++static inline void dma_sync_single_for_device(struct device *dev, ++ dma_addr_t addr, size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_device(dev, addr, size, dir); ++ else if (!plat_device_is_coherent(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_for_device(dev, addr, size, dir); ++} ++ ++static inline void dma_sync_single_range_for_cpu(struct device *dev, ++ dma_addr_t addr, ++ unsigned long offset, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ const struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_cpu(dev, addr + offset, size, dir); ++ else if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr + offset), ++ (addr + offset) & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_range_for_cpu(dev, addr, offset, size, dir); ++} ++ ++static inline void dma_sync_single_range_for_device(struct device *dev, ++ dma_addr_t addr, ++ unsigned long offset, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ const struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_device(dev, addr + offset, size, dir); ++ else if (!plat_device_is_coherent(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr + offset), ++ (addr + offset) & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_range_for_device(dev, addr, offset, size, dir); ++} ++ ++static inline void ++dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, ++ int nelems, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_sg_for_cpu(dev, sg, nelems, dir); ++ else if (cpu_needs_post_dma_flush(dev)) { ++ for_each_sg(sg, s, nelems, i) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ } ++ debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); ++} ++ ++static inline void ++dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, ++ int nelems, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_sg_for_device(dev, sg, nelems, dir); ++ else if (!plat_device_is_coherent(dev)) { ++ for_each_sg(sg, s, nelems, i) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ } ++ debug_dma_sync_sg_for_device(dev, sg, nelems, dir); ++ ++} ++ ++#define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, NULL) ++#define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, NULL) ++#define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, NULL) ++#define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, NULL) ++ ++extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, ++ void *cpu_addr, dma_addr_t dma_addr, size_t size); ++ ++/** ++ * dma_mmap_attrs - map a coherent DMA allocation into user space ++ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices ++ * @vma: vm_area_struct describing requested user mapping ++ * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs ++ * @handle: device-view address returned from dma_alloc_attrs ++ * @size: size of memory originally requested in dma_alloc_attrs ++ * @attrs: attributes of mapping properties requested in dma_alloc_attrs ++ * ++ * Map a coherent DMA buffer previously allocated by dma_alloc_attrs ++ * into user space. The coherent DMA buffer must not be freed by the ++ * driver until the user space mapping has been released. ++ */ ++static inline int ++dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, ++ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ BUG_ON(!ops); ++ if (ops && ops->mmap) ++ return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); ++ return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size); ++} ++ ++#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL) ++ ++int ++dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, ++ void *cpu_addr, dma_addr_t dma_addr, size_t size); ++ ++static inline int ++dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, ++ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ BUG_ON(!ops); ++ if (ops && ops->get_sgtable) ++ return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, ++ attrs); ++ return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size); ++} ++ ++#define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, NULL) ++ + + static inline int dma_supported(struct device *dev, u64 mask) + { + struct dma_map_ops *ops = get_dma_ops(dev); +- return ops->dma_supported(dev, mask); ++ if (ops) ++ return ops->dma_supported(dev, mask); ++ return plat_dma_supported(dev, mask); + } + + static inline int dma_mapping_error(struct device *dev, u64 mask) +@@ -43,7 +378,9 @@ static inline int dma_mapping_error(stru + struct dma_map_ops *ops = get_dma_ops(dev); + + debug_dma_mapping_error(dev, mask); +- return ops->mapping_error(dev, mask); ++ if (ops) ++ return ops->mapping_error(dev, mask); ++ return 0; + } + + static inline int +@@ -54,7 +391,7 @@ dma_set_mask(struct device *dev, u64 mas + if(!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + +- if (ops->set_dma_mask) ++ if (ops && ops->set_dma_mask) + return ops->set_dma_mask(dev, mask); + + *dev->dma_mask = mask; +@@ -74,7 +411,11 @@ static inline void *dma_alloc_attrs(stru + void *ret; + struct dma_map_ops *ops = get_dma_ops(dev); + +- ret = ops->alloc(dev, size, dma_handle, gfp, attrs); ++ if (ops) ++ ret = ops->alloc(dev, size, dma_handle, gfp, attrs); ++ else ++ ret = mips_dma_alloc_coherent(dev, size, dma_handle, gfp, ++ attrs); + + debug_dma_alloc_coherent(dev, size, *dma_handle, ret); + +@@ -89,7 +430,10 @@ static inline void dma_free_attrs(struct + { + struct dma_map_ops *ops = get_dma_ops(dev); + +- ops->free(dev, size, vaddr, dma_handle, attrs); ++ if (ops) ++ ops->free(dev, size, vaddr, dma_handle, attrs); ++ else ++ mips_dma_free_coherent(dev, size, vaddr, dma_handle, attrs); + + debug_dma_free_coherent(dev, size, vaddr, dma_handle); + } +--- a/arch/mips/mm/dma-default.c ++++ b/arch/mips/mm/dma-default.c +@@ -26,7 +26,7 @@ + + #ifdef CONFIG_DMA_MAYBE_COHERENT + int coherentio = 0; /* User defined DMA coherency from command line. */ +-EXPORT_SYMBOL_GPL(coherentio); ++EXPORT_SYMBOL(coherentio); + int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ + + static int __init setcoherentio(char *str) +@@ -46,30 +46,6 @@ static int __init setnocoherentio(char * + early_param("nocoherentio", setnocoherentio); + #endif + +-static inline struct page *dma_addr_to_page(struct device *dev, +- dma_addr_t dma_addr) +-{ +- return pfn_to_page( +- plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); +-} +- +-/* +- * The affected CPUs below in 'cpu_needs_post_dma_flush()' can +- * speculatively fill random cachelines with stale data at any time, +- * requiring an extra flush post-DMA. +- * +- * Warning on the terminology - Linux calls an uncached area coherent; +- * MIPS terminology calls memory areas with hardware maintained coherency +- * coherent. +- */ +-static inline int cpu_needs_post_dma_flush(struct device *dev) +-{ +- return !plat_device_is_coherent(dev) && +- (boot_cpu_type() == CPU_R10000 || +- boot_cpu_type() == CPU_R12000 || +- boot_cpu_type() == CPU_BMIPS5000); +-} +- + static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) + { + gfp_t dma_flag; +@@ -125,8 +101,9 @@ void *dma_alloc_noncoherent(struct devic + } + EXPORT_SYMBOL(dma_alloc_noncoherent); + +-static void *mips_dma_alloc_coherent(struct device *dev, size_t size, +- dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) ++void *mips_dma_alloc_coherent(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp, ++ struct dma_attrs *attrs) + { + void *ret; + struct page *page = NULL; +@@ -157,6 +134,7 @@ static void *mips_dma_alloc_coherent(str + + return ret; + } ++EXPORT_SYMBOL(mips_dma_alloc_coherent); + + + void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, +@@ -167,8 +145,8 @@ void dma_free_noncoherent(struct device + } + EXPORT_SYMBOL(dma_free_noncoherent); + +-static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, +- dma_addr_t dma_handle, struct dma_attrs *attrs) ++void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, ++ dma_addr_t dma_handle, struct dma_attrs *attrs) + { + unsigned long addr = (unsigned long) vaddr; + int order = get_order(size); +@@ -188,6 +166,7 @@ static void mips_dma_free_coherent(struc + if (!dma_release_from_contiguous(dev, page, count)) + __free_pages(page, get_order(size)); + } ++EXPORT_SYMBOL(mips_dma_free_coherent); + + static inline void __dma_sync_virtual(void *addr, size_t size, + enum dma_data_direction direction) +@@ -216,8 +195,8 @@ static inline void __dma_sync_virtual(vo + * If highmem is not configured then the bulk of this loop gets + * optimized out. + */ +-static inline void __dma_sync(struct page *page, +- unsigned long offset, size_t size, enum dma_data_direction direction) ++void __dma_sync(struct page *page, unsigned long offset, size_t size, ++ enum dma_data_direction direction) + { + size_t left = size; + +@@ -246,108 +225,7 @@ static inline void __dma_sync(struct pag + left -= len; + } while (left); + } +- +-static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, +- size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) +-{ +- if (cpu_needs_post_dma_flush(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_addr), +- dma_addr & ~PAGE_MASK, size, direction); +- +- plat_unmap_dma_mem(dev, dma_addr, size, direction); +-} +- +-static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg, +- int nents, enum dma_data_direction direction, struct dma_attrs *attrs) +-{ +- int i; +- +- for (i = 0; i < nents; i++, sg++) { +- if (!plat_device_is_coherent(dev)) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-#ifdef CONFIG_NEED_SG_DMA_LENGTH +- sg->dma_length = sg->length; +-#endif +- sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + +- sg->offset; +- } +- +- return nents; +-} +- +-static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page, +- unsigned long offset, size_t size, enum dma_data_direction direction, +- struct dma_attrs *attrs) +-{ +- if (!plat_device_is_coherent(dev)) +- __dma_sync(page, offset, size, direction); +- +- return plat_map_dma_mem_page(dev, page) + offset; +-} +- +-static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg, +- int nhwentries, enum dma_data_direction direction, +- struct dma_attrs *attrs) +-{ +- int i; +- +- for (i = 0; i < nhwentries; i++, sg++) { +- if (!plat_device_is_coherent(dev) && +- direction != DMA_TO_DEVICE) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +- plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction); +- } +-} +- +-static void mips_dma_sync_single_for_cpu(struct device *dev, +- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +-{ +- if (cpu_needs_post_dma_flush(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_handle), +- dma_handle & ~PAGE_MASK, size, direction); +-} +- +-static void mips_dma_sync_single_for_device(struct device *dev, +- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +-{ +- if (!plat_device_is_coherent(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_handle), +- dma_handle & ~PAGE_MASK, size, direction); +-} +- +-static void mips_dma_sync_sg_for_cpu(struct device *dev, +- struct scatterlist *sg, int nelems, enum dma_data_direction direction) +-{ +- int i; +- +- if (cpu_needs_post_dma_flush(dev)) +- for (i = 0; i < nelems; i++, sg++) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-} +- +-static void mips_dma_sync_sg_for_device(struct device *dev, +- struct scatterlist *sg, int nelems, enum dma_data_direction direction) +-{ +- int i; +- +- if (!plat_device_is_coherent(dev)) +- for (i = 0; i < nelems; i++, sg++) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-} +- +-int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +-{ +- return 0; +-} +- +-int mips_dma_supported(struct device *dev, u64 mask) +-{ +- return plat_dma_supported(dev, mask); +-} ++EXPORT_SYMBOL(__dma_sync); + + void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) +@@ -360,23 +238,10 @@ void dma_cache_sync(struct device *dev, + + EXPORT_SYMBOL(dma_cache_sync); + +-static struct dma_map_ops mips_default_dma_map_ops = { +- .alloc = mips_dma_alloc_coherent, +- .free = mips_dma_free_coherent, +- .map_page = mips_dma_map_page, +- .unmap_page = mips_dma_unmap_page, +- .map_sg = mips_dma_map_sg, +- .unmap_sg = mips_dma_unmap_sg, +- .sync_single_for_cpu = mips_dma_sync_single_for_cpu, +- .sync_single_for_device = mips_dma_sync_single_for_device, +- .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu, +- .sync_sg_for_device = mips_dma_sync_sg_for_device, +- .mapping_error = mips_dma_mapping_error, +- .dma_supported = mips_dma_supported +-}; +- +-struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops; ++#ifdef CONFIG_SYS_HAS_DMA_OPS ++struct dma_map_ops *mips_dma_map_ops = NULL; + EXPORT_SYMBOL(mips_dma_map_ops); ++#endif + + #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) + diff --git a/target/linux/generic/patches-3.18/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch b/target/linux/generic/patches-3.18/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch new file mode 100644 index 0000000..ebbe1bb --- /dev/null +++ b/target/linux/generic/patches-3.18/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch @@ -0,0 +1,53 @@ +From 71a0a72456b48de972d7ed613b06a22a3aa9057f Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 26 Sep 2015 13:41:43 +0800 +Subject: [PATCH] MIPS: UAPI: Ignore __arch_swab{16,32,64} when using MIPS16 + +Some GCC versions (e.g. 4.8.3) can incorrectly inline a function with +MIPS32 instructions into another function with MIPS16 code [1], causing +the assembler to genereate incorrect binary code or fail right away +complaining about unrecognized opcode. + +In the case of __arch_swab{16,32}, when inlined by the compiler with +flags `-mips32r2 -mips16 -Os', the assembler can fail with the following +error. + + {standard input}:79: Error: unrecognized opcode `wsbh $2,$2' + +For performance concerns and to workaround the issue already existing in +older compilers, just ignore these 2 functions when compiling with +mips16 enabled. + + [1] Inlining nomips16 function into mips16 function can result in + undefined builtins, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55777 + +Signed-off-by: Yousong Zhou +Cc: Maciej W. Rozycki +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/11241/ +Signed-off-by: Ralf Baechle +--- + arch/mips/include/uapi/asm/swab.h | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/arch/mips/include/uapi/asm/swab.h ++++ b/arch/mips/include/uapi/asm/swab.h +@@ -13,8 +13,9 @@ + + #define __SWAB_64_THRU_32__ + +-#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ +- defined(_MIPS_ARCH_LOONGSON3A) ++#if !defined(__mips16) && \ ++ ((defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ ++ defined(_MIPS_ARCH_LOONGSON3A)) + + static inline __attribute_const__ __u16 __arch_swab16(__u16 x) + { +@@ -65,5 +66,5 @@ static inline __attribute_const__ __u64 + } + #define __arch_swab64 __arch_swab64 + #endif /* __mips64 */ +-#endif /* MIPS R2 or newer or Loongson 3A */ ++#endif /* (not __mips16) and (MIPS R2 or newer or Loongson 3A) */ + #endif /* _ASM_SWAB_H */ diff --git a/target/linux/generic/patches-3.18/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch b/target/linux/generic/patches-3.18/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch new file mode 100644 index 0000000..bd34f96 --- /dev/null +++ b/target/linux/generic/patches-3.18/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch @@ -0,0 +1,175 @@ +From 173b0add0cff6558f950c0cb1eacfb729d482711 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 17 May 2015 18:48:38 +0200 +Subject: [PATCH 4/8] mtd: part: add generic parsing of linux,part-probe + +This moves the linux,part-probe device tree parsing code from +physmap_of.c to mtdpart.c. Now all drivers can use this feature by just +providing a reference to their device tree node in struct +mtd_part_parser_data. + +Signed-off-by: Hauke Mehrtens +--- + Documentation/devicetree/bindings/mtd/nand.txt | 16 ++++++++++ + drivers/mtd/maps/physmap_of.c | 40 +----------------------- + drivers/mtd/mtdpart.c | 43 ++++++++++++++++++++++++++ + 3 files changed, 60 insertions(+), 39 deletions(-) + +--- a/Documentation/devicetree/bindings/mtd/nand.txt ++++ b/Documentation/devicetree/bindings/mtd/nand.txt +@@ -12,6 +12,22 @@ + - nand-ecc-step-size: integer representing the number of data bytes + that are covered by a single ECC step. + ++- linux,part-probe: list of name as strings of the partition parser ++ which should be used to parse the partition table. ++ They will be tried in the specified ordering and ++ the next one will be used if the previous one ++ failed. ++ ++ Example: linux,part-probe = "cmdlinepart", "ofpart"; ++ ++ This is also the default value, which will be used ++ if this attribute is not specified. It could be ++ that the flash driver in use overwrote the default ++ value and uses some other default. ++ ++ Possible values are: bcm47xxpart, afs, ar7part, ++ ofoldpart, ofpart, bcm63xxpart, RedBoot, cmdlinepart ++ + The ECC strength and ECC step size properties define the correction capability + of a controller. Together, they say a controller can correct "{strength} bit + errors per {size} bytes". +--- a/drivers/mtd/maps/physmap_of.c ++++ b/drivers/mtd/maps/physmap_of.c +@@ -114,45 +114,9 @@ static struct mtd_info *obsolete_probe(s + static const char * const part_probe_types_def[] = { + "cmdlinepart", "RedBoot", "ofpart", "ofoldpart", NULL }; + +-static const char * const *of_get_probes(struct device_node *dp) +-{ +- const char *cp; +- int cplen; +- unsigned int l; +- unsigned int count; +- const char **res; +- +- cp = of_get_property(dp, "linux,part-probe", &cplen); +- if (cp == NULL) +- return part_probe_types_def; +- +- count = 0; +- for (l = 0; l != cplen; l++) +- if (cp[l] == 0) +- count++; +- +- res = kzalloc((count + 1)*sizeof(*res), GFP_KERNEL); +- count = 0; +- while (cplen > 0) { +- res[count] = cp; +- l = strlen(cp) + 1; +- cp += l; +- cplen -= l; +- count++; +- } +- return res; +-} +- +-static void of_free_probes(const char * const *probes) +-{ +- if (probes != part_probe_types_def) +- kfree(probes); +-} +- + static struct of_device_id of_flash_match[]; + static int of_flash_probe(struct platform_device *dev) + { +- const char * const *part_probe_types; + const struct of_device_id *match; + struct device_node *dp = dev->dev.of_node; + struct resource res; +@@ -302,10 +266,8 @@ static int of_flash_probe(struct platfor + goto err_out; + + ppdata.of_node = dp; +- part_probe_types = of_get_probes(dp); +- mtd_device_parse_register(info->cmtd, part_probe_types, &ppdata, ++ mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata, + NULL, 0); +- of_free_probes(part_probe_types); + + kfree(mtd_list); + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + #include + + #include "mtdcore.h" +@@ -702,6 +703,40 @@ void deregister_mtd_parser(struct mtd_pa + EXPORT_SYMBOL_GPL(deregister_mtd_parser); + + /* ++ * Parses the linux,part-probe device tree property. ++ * When a non null value is returned it has to be freed with kfree() by ++ * the caller. ++ */ ++static const char * const *of_get_probes(struct device_node *dp) ++{ ++ const char *cp; ++ int cplen; ++ unsigned int l; ++ unsigned int count; ++ const char **res; ++ ++ cp = of_get_property(dp, "linux,part-probe", &cplen); ++ if (cp == NULL) ++ return NULL; ++ ++ count = 0; ++ for (l = 0; l != cplen; l++) ++ if (cp[l] == 0) ++ count++; ++ ++ res = kzalloc((count + 1) * sizeof(*res), GFP_KERNEL); ++ count = 0; ++ while (cplen > 0) { ++ res[count] = cp; ++ l = strlen(cp) + 1; ++ cp += l; ++ cplen -= l; ++ count++; ++ } ++ return res; ++} ++ ++/* + * Do not forget to update 'parse_mtd_partitions()' kerneldoc comment if you + * are changing this array! + */ +@@ -737,6 +772,13 @@ int parse_mtd_partitions(struct mtd_info + { + struct mtd_part_parser *parser; + int ret = 0; ++ const char *const *types_of = NULL; ++ ++ if (data && data->of_node) { ++ types_of = of_get_probes(data->of_node); ++ if (types_of != NULL) ++ types = types_of; ++ } + + if (!types) + types = default_mtd_part_types; +@@ -755,6 +797,7 @@ int parse_mtd_partitions(struct mtd_info + break; + } + } ++ kfree(types_of); + return ret; + } + diff --git a/target/linux/generic/patches-3.18/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch b/target/linux/generic/patches-3.18/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch new file mode 100644 index 0000000..a17e398 --- /dev/null +++ b/target/linux/generic/patches-3.18/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch @@ -0,0 +1,41 @@ +From 9612e686b235dc9e33c8dfb5e6d2ff2b2140fb9d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 21:01:30 +0200 +Subject: [PATCH V2] usb: xhci: make USB_XHCI_PLATFORM selectable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Right now xhci-plat-hcd can be built when using one of platform specific +drivers only (mvebu/rcar). There shouldn't be such limitation as some +platforms may not require any quirks and may want to just use a generic +driver ("generic-xhci" / "xhci-hcd"). + +Signed-off-by: Rafał Miłecki +--- +Greg/Mathias: I'm not sure if it's more like USB subsystem stuff or xHCI +Could you decide which one of you could pick that, please? + +V2: Drop useless "default n", thanks Sergei :) +--- + drivers/usb/host/Kconfig | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -32,7 +32,14 @@ config USB_XHCI_PCI + default y + + config USB_XHCI_PLATFORM +- tristate ++ tristate "Generic xHCI driver for a platform device" ++ ---help--- ++ Adds an xHCI host driver for a generic platform device, which ++ provides a memory space and an irq. ++ It is also a prerequisite for platform specific drivers that ++ implement some extra quirks. ++ ++ If unsure, say N. + + config USB_XHCI_MVEBU + tristate "xHCI support for Marvell Armada 375/38x" diff --git a/target/linux/generic/patches-3.18/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch b/target/linux/generic/patches-3.18/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch new file mode 100644 index 0000000..09cbe0c --- /dev/null +++ b/target/linux/generic/patches-3.18/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch @@ -0,0 +1,228 @@ +From 4a0e3e989d66bb7204b163d9cfaa7fa96d0f2023 Mon Sep 17 00:00:00 2001 +From: Enrico Mioso +Date: Wed, 8 Jul 2015 13:05:57 +0200 +Subject: [PATCH] cdc_ncm: Add support for moving NDP to end of NCM frame + +NCM specs are not actually mandating a specific position in the frame for +the NDP (Network Datagram Pointer). However, some Huawei devices will +ignore our aggregates if it is not placed after the datagrams it points +to. Add support for doing just this, in a per-device configurable way. +While at it, update NCM subdrivers, disabling this functionality in all of +them, except in huawei_cdc_ncm where it is enabled instead. +We aren't making any distinction between different Huawei NCM devices, +based on what the vendor driver does. Standard NCM devices are left +unaffected: if they are compliant, they should be always usable, still +stay on the safe side. + +This change has been tested and working with a Huawei E3131 device (which +works regardless of NDP position), a Huawei E3531 (also working both +ways) and an E3372 (which mandates NDP to be after indexed datagrams). + +V1->V2: +- corrected wrong NDP acronym definition +- fixed possible NULL pointer dereference +- patch cleanup +V2->V3: +- Properly account for the NDP size when writing new packets to SKB + +Signed-off-by: Enrico Mioso +Signed-off-by: David S. Miller +--- + drivers/net/usb/cdc_mbim.c | 2 +- + drivers/net/usb/cdc_ncm.c | 61 ++++++++++++++++++++++++++++++++++++---- + drivers/net/usb/huawei_cdc_ncm.c | 7 +++-- + include/linux/usb/cdc_ncm.h | 7 ++++- + 4 files changed, 67 insertions(+), 10 deletions(-) + +--- a/drivers/net/usb/cdc_mbim.c ++++ b/drivers/net/usb/cdc_mbim.c +@@ -158,7 +158,7 @@ static int cdc_mbim_bind(struct usbnet * + if (!cdc_ncm_comm_intf_is_mbim(intf->cur_altsetting)) + goto err; + +- ret = cdc_ncm_bind_common(dev, intf, data_altsetting); ++ ret = cdc_ncm_bind_common(dev, intf, data_altsetting, 0); + if (ret) + goto err; + +--- a/drivers/net/usb/cdc_ncm.c ++++ b/drivers/net/usb/cdc_ncm.c +@@ -684,10 +684,12 @@ static void cdc_ncm_free(struct cdc_ncm_ + ctx->tx_curr_skb = NULL; + } + ++ kfree(ctx->delayed_ndp16); ++ + kfree(ctx); + } + +-int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting) ++int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting, int drvflags) + { + const struct usb_cdc_union_desc *union_desc = NULL; + struct cdc_ncm_ctx *ctx; +@@ -855,6 +857,17 @@ advance: + /* finish setting up the device specific data */ + cdc_ncm_setup(dev); + ++ /* Device-specific flags */ ++ ctx->drvflags = drvflags; ++ ++ /* Allocate the delayed NDP if needed. */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { ++ ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); ++ if (!ctx->delayed_ndp16) ++ goto error2; ++ dev_info(&intf->dev, "NDP will be placed at end of frame for this device."); ++ } ++ + /* override ethtool_ops */ + dev->net->ethtool_ops = &cdc_ncm_ethtool_ops; + +@@ -954,8 +967,11 @@ static int cdc_ncm_bind(struct usbnet *d + if (cdc_ncm_select_altsetting(intf) != CDC_NCM_COMM_ALTSETTING_NCM) + return -ENODEV; + +- /* The NCM data altsetting is fixed */ +- ret = cdc_ncm_bind_common(dev, intf, CDC_NCM_DATA_ALTSETTING_NCM); ++ /* The NCM data altsetting is fixed, so we hard-coded it. ++ * Additionally, generic NCM devices are assumed to accept arbitrarily ++ * placed NDP. ++ */ ++ ret = cdc_ncm_bind_common(dev, intf, CDC_NCM_DATA_ALTSETTING_NCM, 0); + + /* + * We should get an event when network connection is "connected" or +@@ -986,6 +1002,14 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + struct usb_cdc_ncm_nth16 *nth16 = (void *)skb->data; + size_t ndpoffset = le16_to_cpu(nth16->wNdpIndex); + ++ /* If NDP should be moved to the end of the NCM package, we can't follow the ++ * NTH16 header as we would normally do. NDP isn't written to the SKB yet, and ++ * the wNdpIndex field in the header is actually not consistent with reality. It will be later. ++ */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) ++ if (ctx->delayed_ndp16->dwSignature == sign) ++ return ctx->delayed_ndp16; ++ + /* follow the chain of NDPs, looking for a match */ + while (ndpoffset) { + ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb->data + ndpoffset); +@@ -995,7 +1019,8 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + } + + /* align new NDP */ +- cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_max); ++ if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) ++ cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_max); + + /* verify that there is room for the NDP and the datagram (reserve) */ + if ((ctx->tx_max - skb->len - reserve) < ctx->max_ndp_size) +@@ -1008,7 +1033,11 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + nth16->wNdpIndex = cpu_to_le16(skb->len); + + /* push a new empty NDP */ +- ndp16 = (struct usb_cdc_ncm_ndp16 *)memset(skb_put(skb, ctx->max_ndp_size), 0, ctx->max_ndp_size); ++ if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) ++ ndp16 = (struct usb_cdc_ncm_ndp16 *)memset(skb_put(skb, ctx->max_ndp_size), 0, ctx->max_ndp_size); ++ else ++ ndp16 = ctx->delayed_ndp16; ++ + ndp16->dwSignature = sign; + ndp16->wLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_ndp16) + sizeof(struct usb_cdc_ncm_dpe16)); + return ndp16; +@@ -1023,6 +1052,15 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + struct sk_buff *skb_out; + u16 n = 0, index, ndplen; + u8 ready2send = 0; ++ u32 delayed_ndp_size; ++ ++ /* When our NDP gets written in cdc_ncm_ndp(), then skb_out->len gets updated ++ * accordingly. Otherwise, we should check here. ++ */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) ++ delayed_ndp_size = ctx->max_ndp_size; ++ else ++ delayed_ndp_size = 0; + + /* if there is a remaining skb, it gets priority */ + if (skb != NULL) { +@@ -1077,7 +1115,7 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + cdc_ncm_align_tail(skb_out, ctx->tx_modulus, ctx->tx_remainder, ctx->tx_max); + + /* check if we had enough room left for both NDP and frame */ +- if (!ndp16 || skb_out->len + skb->len > ctx->tx_max) { ++ if (!ndp16 || skb_out->len + skb->len + delayed_ndp_size > ctx->tx_max) { + if (n == 0) { + /* won't fit, MTU problem? */ + dev_kfree_skb_any(skb); +@@ -1150,6 +1188,17 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + /* variables will be reset at next call */ + } + ++ /* If requested, put NDP at end of frame. */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { ++ nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; ++ cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_max); ++ nth16->wNdpIndex = cpu_to_le16(skb_out->len); ++ memcpy(skb_put(skb_out, ctx->max_ndp_size), ctx->delayed_ndp16, ctx->max_ndp_size); ++ ++ /* Zero out delayed NDP - signature checking will naturally fail. */ ++ ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); ++ } ++ + /* If collected data size is less or equal ctx->min_tx_pkt + * bytes, we send buffers as it is. If we get more data, it + * would be more efficient for USB HS mobile device with DMA +--- a/drivers/net/usb/huawei_cdc_ncm.c ++++ b/drivers/net/usb/huawei_cdc_ncm.c +@@ -73,11 +73,14 @@ static int huawei_cdc_ncm_bind(struct us + struct usb_driver *subdriver = ERR_PTR(-ENODEV); + int ret = -ENODEV; + struct huawei_cdc_ncm_state *drvstate = (void *)&usbnet_dev->data; ++ int drvflags = 0; + + /* altsetting should always be 1 for NCM devices - so we hard-coded +- * it here ++ * it here. Some huawei devices will need the NDP part of the NCM package to ++ * be at the end of the frame. + */ +- ret = cdc_ncm_bind_common(usbnet_dev, intf, 1); ++ drvflags |= CDC_NCM_FLAG_NDP_TO_END; ++ ret = cdc_ncm_bind_common(usbnet_dev, intf, 1, drvflags); + if (ret) + goto err; + +--- a/include/linux/usb/cdc_ncm.h ++++ b/include/linux/usb/cdc_ncm.h +@@ -80,6 +80,9 @@ + #define CDC_NCM_TIMER_INTERVAL_MIN 5UL + #define CDC_NCM_TIMER_INTERVAL_MAX (U32_MAX / NSEC_PER_USEC) + ++/* Driver flags */ ++#define CDC_NCM_FLAG_NDP_TO_END 0x02 /* NDP is placed at end of frame */ ++ + #define cdc_ncm_comm_intf_is_mbim(x) ((x)->desc.bInterfaceSubClass == USB_CDC_SUBCLASS_MBIM && \ + (x)->desc.bInterfaceProtocol == USB_CDC_PROTO_NONE) + #define cdc_ncm_data_intf_is_mbim(x) ((x)->desc.bInterfaceProtocol == USB_CDC_MBIM_PROTO_NTB) +@@ -103,9 +106,11 @@ struct cdc_ncm_ctx { + + spinlock_t mtx; + atomic_t stop; ++ int drvflags; + + u32 timer_interval; + u32 max_ndp_size; ++ struct usb_cdc_ncm_ndp16 *delayed_ndp16; + + u32 tx_timer_pending; + u32 tx_curr_frame_num; +@@ -133,7 +138,7 @@ struct cdc_ncm_ctx { + }; + + u8 cdc_ncm_select_altsetting(struct usb_interface *intf); +-int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting); ++int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting, int drvflags); + void cdc_ncm_unbind(struct usbnet *dev, struct usb_interface *intf); + struct sk_buff *cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign); + int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); diff --git a/target/linux/generic/patches-3.18/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch b/target/linux/generic/patches-3.18/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch new file mode 100644 index 0000000..5a3dc06 --- /dev/null +++ b/target/linux/generic/patches-3.18/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch @@ -0,0 +1,35 @@ +From a95f03e51471dbdbafd3391991d867ac2358ed02 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 23 Aug 2015 14:23:29 +0200 +Subject: [PATCH] usb: ehci-orion: fix probe for !GENERIC_PHY + +Commit d445913ce0ab7f ("usb: ehci-orion: add optional PHY support") +added support for optional phys, but devm_phy_optional_get returns +-ENOSYS if GENERIC_PHY is not enabled. + +This causes probe failures, even when there are no phys specified: + +[ 1.443365] orion-ehci f1058000.usb: init f1058000.usb fail, -38 +[ 1.449403] orion-ehci: probe of f1058000.usb failed with error -38 + +Similar to dwc3, treat -ENOSYS as no phy. + +Fixes: d445913ce0ab7f ("usb: ehci-orion: add optional PHY support") + +Signed-off-by: Jonas Gorski +--- + drivers/usb/host/ehci-orion.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/ehci-orion.c ++++ b/drivers/usb/host/ehci-orion.c +@@ -226,7 +226,8 @@ static int ehci_orion_drv_probe(struct p + priv->phy = devm_phy_optional_get(&pdev->dev, "usb"); + if (IS_ERR(priv->phy)) { + err = PTR_ERR(priv->phy); +- goto err_phy_get; ++ if (err != -ENOSYS) ++ goto err_phy_get; + } else { + err = phy_init(priv->phy); + if (err) diff --git a/target/linux/generic/patches-3.18/200-fix_localversion.patch b/target/linux/generic/patches-3.18/200-fix_localversion.patch new file mode 100644 index 0000000..70228bb --- /dev/null +++ b/target/linux/generic/patches-3.18/200-fix_localversion.patch @@ -0,0 +1,11 @@ +--- a/scripts/setlocalversion ++++ b/scripts/setlocalversion +@@ -165,7 +165,7 @@ else + # annotated or signed tagged state (as git describe only + # looks at signed or annotated tags - git tag -a/-s) and + # LOCALVERSION= is not specified +- if test "${LOCALVERSION+set}" != "set"; then ++ if test "${CONFIG_LOCALVERSION+set}" != "set"; then + scm=$(scm_version --short) + res="$res${scm:++}" + fi diff --git a/target/linux/generic/patches-3.18/201-extra_optimization.patch b/target/linux/generic/patches-3.18/201-extra_optimization.patch new file mode 100644 index 0000000..7ec93a4 --- /dev/null +++ b/target/linux/generic/patches-3.18/201-extra_optimization.patch @@ -0,0 +1,14 @@ +--- a/Makefile ++++ b/Makefile +@@ -612,9 +612,9 @@ include $(srctree)/arch/$(SRCARCH)/Makef + KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,) + + ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE +-KBUILD_CFLAGS += -Os $(call cc-disable-warning,maybe-uninitialized,) ++KBUILD_CFLAGS += -Os $(EXTRA_OPTIMIZATION) $(call cc-disable-warning,maybe-uninitialized,) + else +-KBUILD_CFLAGS += -O2 ++KBUILD_CFLAGS += -O2 -fno-reorder-blocks -fno-tree-ch $(EXTRA_OPTIMIZATION) + endif + + # Tell gcc to never replace conditional load with a non-conditional one diff --git a/target/linux/generic/patches-3.18/202-reduce_module_size.patch b/target/linux/generic/patches-3.18/202-reduce_module_size.patch new file mode 100644 index 0000000..b98ea4e --- /dev/null +++ b/target/linux/generic/patches-3.18/202-reduce_module_size.patch @@ -0,0 +1,11 @@ +--- a/Makefile ++++ b/Makefile +@@ -409,7 +409,7 @@ KBUILD_CFLAGS_KERNEL := + KBUILD_AFLAGS := -D__ASSEMBLY__ + KBUILD_AFLAGS_MODULE := -DMODULE + KBUILD_CFLAGS_MODULE := -DMODULE +-KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds ++KBUILD_LDFLAGS_MODULE = -T $(srctree)/scripts/module-common.lds $(if $(CONFIG_PROFILING),,-s) + + # Read KERNELRELEASE from include/config/kernel.release (if it exists) + KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) diff --git a/target/linux/generic/patches-3.18/203-kallsyms_uncompressed.patch b/target/linux/generic/patches-3.18/203-kallsyms_uncompressed.patch new file mode 100644 index 0000000..b9d8220 --- /dev/null +++ b/target/linux/generic/patches-3.18/203-kallsyms_uncompressed.patch @@ -0,0 +1,108 @@ +--- a/scripts/kallsyms.c ++++ b/scripts/kallsyms.c +@@ -58,6 +58,7 @@ static struct addr_range percpu_range = + static struct sym_entry *table; + static unsigned int table_size, table_cnt; + static int all_symbols = 0; ++static int uncompressed = 0; + static int absolute_percpu = 0; + static char symbol_prefix_char = '\0'; + static unsigned long long kernel_start_addr = 0; +@@ -392,6 +393,9 @@ static void write_src(void) + + free(markers); + ++ if (uncompressed) ++ return; ++ + output_label("kallsyms_token_table"); + off = 0; + for (i = 0; i < 256; i++) { +@@ -450,6 +454,9 @@ static void *find_token(unsigned char *s + { + int i; + ++ if (uncompressed) ++ return NULL; ++ + for (i = 0; i < len - 1; i++) { + if (str[i] == token[0] && str[i+1] == token[1]) + return &str[i]; +@@ -522,6 +529,9 @@ static void optimize_result(void) + { + int i, best; + ++ if (uncompressed) ++ return; ++ + /* using the '\0' symbol last allows compress_symbols to use standard + * fast string functions */ + for (i = 255; i >= 0; i--) { +@@ -692,7 +702,9 @@ int main(int argc, char **argv) + } else if (strncmp(argv[i], "--page-offset=", 14) == 0) { + const char *p = &argv[i][14]; + kernel_start_addr = strtoull(p, NULL, 16); +- } else ++ } else if (strcmp(argv[i], "--uncompressed") == 0) ++ uncompressed = 1; ++ else + usage(); + } + } else if (argc != 1) +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1338,6 +1338,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW + the unaligned access emulation. + see arch/parisc/kernel/unaligned.c for reference + ++config KALLSYMS_UNCOMPRESSED ++ bool "Keep kallsyms uncompressed" ++ depends on KALLSYMS ++ help ++ Normally kallsyms contains compressed symbols (using a token table), ++ reducing the uncompressed kernel image size. Keeping the symbol table ++ uncompressed significantly improves the size of this part in compressed ++ kernel images. ++ ++ Say N unless you need compressed kernel images to be small. ++ + config HAVE_PCSPKR_PLATFORM + bool + +--- a/scripts/link-vmlinux.sh ++++ b/scripts/link-vmlinux.sh +@@ -90,6 +90,10 @@ kallsyms() + kallsymopt="${kallsymopt} --absolute-percpu" + fi + ++ if [ -n "${CONFIG_KALLSYMS_UNCOMPRESSED}" ]; then ++ kallsymopt="${kallsymopt} --uncompressed" ++ fi ++ + local aflags="${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL} \ + ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" + +--- a/kernel/kallsyms.c ++++ b/kernel/kallsyms.c +@@ -109,6 +109,11 @@ static unsigned int kallsyms_expand_symb + * For every byte on the compressed symbol data, copy the table + * entry for that byte. + */ ++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED ++ memcpy(result, data + 1, len - 1); ++ result += len - 1; ++ len = 0; ++#endif + while (len) { + tptr = &kallsyms_token_table[kallsyms_token_index[*data]]; + data++; +@@ -141,6 +146,9 @@ tail: + */ + static char kallsyms_get_symbol_type(unsigned int off) + { ++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED ++ return kallsyms_names[off + 1]; ++#endif + /* + * Get just the first code, look it up in the token table, + * and return the first char from this token. diff --git a/target/linux/generic/patches-3.18/204-module_strip.patch b/target/linux/generic/patches-3.18/204-module_strip.patch new file mode 100644 index 0000000..09bffe0 --- /dev/null +++ b/target/linux/generic/patches-3.18/204-module_strip.patch @@ -0,0 +1,194 @@ +From: Felix Fietkau +Subject: [PATCH] build: add a hack for removing non-essential module info + +Signed-off-by: Felix Fietkau +--- +--- a/include/linux/module.h ++++ b/include/linux/module.h +@@ -84,9 +84,10 @@ void trim_init_extable(struct module *m) + + /* Generic info of form tag = "info" */ + #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info) ++#define MODULE_INFO_STRIP(tag, info) __MODULE_INFO_STRIP(tag, tag, info) + + /* For userspace: you can also call me... */ +-#define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias) ++#define MODULE_ALIAS(_alias) MODULE_INFO_STRIP(alias, _alias) + + /* Soft module dependencies. See man modprobe.d for details. + * Example: MODULE_SOFTDEP("pre: module-foo module-bar post: module-baz") +@@ -127,12 +128,12 @@ void trim_init_extable(struct module *m) + * Author(s), use "Name " or just "Name", for multiple + * authors use multiple MODULE_AUTHOR() statements/lines. + */ +-#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author) ++#define MODULE_AUTHOR(_author) MODULE_INFO_STRIP(author, _author) + + /* What your module does. */ +-#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description) ++#define MODULE_DESCRIPTION(_description) MODULE_INFO_STRIP(description, _description) + +-#ifdef MODULE ++#if defined(MODULE) && !defined(CONFIG_MODULE_STRIPPED) + /* Creates an alias so file2alias.c can find device table. */ + #define MODULE_DEVICE_TABLE(type, name) \ + extern const struct type##_device_id __mod_##type##__##name##_device_table \ +@@ -159,7 +160,9 @@ void trim_init_extable(struct module *m) + */ + + #if defined(MODULE) || !defined(CONFIG_SYSFS) +-#define MODULE_VERSION(_version) MODULE_INFO(version, _version) ++#define MODULE_VERSION(_version) MODULE_INFO_STRIP(version, _version) ++#elif defined(CONFIG_MODULE_STRIPPED) ++#define MODULE_VERSION(_version) __MODULE_INFO_DISABLED(version) + #else + #define MODULE_VERSION(_version) \ + static struct module_version_attribute ___modver_attr = { \ +@@ -181,7 +184,7 @@ void trim_init_extable(struct module *m) + /* Optional firmware file (or files) needed by the module + * format is simply firmware file name. Multiple firmware + * files require multiple MODULE_FIRMWARE() specifiers */ +-#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware) ++#define MODULE_FIRMWARE(_firmware) MODULE_INFO_STRIP(firmware, _firmware) + + /* Given an address, look for it in the exception tables */ + const struct exception_table_entry *search_exception_tables(unsigned long add); +--- a/include/linux/moduleparam.h ++++ b/include/linux/moduleparam.h +@@ -16,6 +16,16 @@ + /* Chosen so that structs with an unsigned long line up. */ + #define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long)) + ++/* This struct is here for syntactic coherency, it is not used */ ++#define __MODULE_INFO_DISABLED(name) \ ++ struct __UNIQUE_ID(name) {} ++ ++#ifdef CONFIG_MODULE_STRIPPED ++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO_DISABLED(name) ++#else ++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO(tag, name, info) ++#endif ++ + #ifdef MODULE + #define __MODULE_INFO(tag, name, info) \ + static const char __UNIQUE_ID(name)[] \ +@@ -23,8 +33,7 @@ static const char __UNIQUE_ID(name)[] + = __stringify(tag) "=" info + #else /* !MODULE */ + /* This struct is here for syntactic coherency, it is not used */ +-#define __MODULE_INFO(tag, name, info) \ +- struct __UNIQUE_ID(name) {} ++#define __MODULE_INFO(tag, name, info) __MODULE_INFO_DISABLED(name) + #endif + #define __MODULE_PARM_TYPE(name, _type) \ + __MODULE_INFO(parmtype, name##type, #name ":" _type) +@@ -32,7 +41,7 @@ static const char __UNIQUE_ID(name)[] + /* One for each parameter, describing how to use it. Some files do + multiple of these per line, so can't just use MODULE_INFO. */ + #define MODULE_PARM_DESC(_parm, desc) \ +- __MODULE_INFO(parm, _parm, #_parm ":" desc) ++ __MODULE_INFO_STRIP(parm, _parm, #_parm ":" desc) + + struct kernel_param; + +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1987,6 +1987,13 @@ config MODULE_COMPRESS_XZ + + endchoice + ++config MODULE_STRIPPED ++ bool "Reduce module size" ++ depends on MODULES ++ help ++ Remove module parameter descriptions, author info, version, aliases, ++ device tables, etc. ++ + endif # MODULES + + config INIT_ALL_POSSIBLE +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -2670,6 +2670,7 @@ static struct module *setup_load_info(st + + static int check_modinfo(struct module *mod, struct load_info *info, int flags) + { ++#ifndef CONFIG_MODULE_STRIPPED + const char *modmagic = get_modinfo(info, "vermagic"); + int err; + +@@ -2695,6 +2696,7 @@ static int check_modinfo(struct module * + pr_warn("%s: module is from the staging directory, the quality " + "is unknown, you have been warned.\n", mod->name); + } ++#endif + + /* Set up license info based on the info section */ + set_license(mod, get_modinfo(info, "license")); +--- a/scripts/mod/modpost.c ++++ b/scripts/mod/modpost.c +@@ -1726,7 +1726,9 @@ static void read_symbols(char *modname) + symname = remove_dot(info.strtab + sym->st_name); + + handle_modversions(mod, &info, sym, symname); ++#ifndef CONFIG_MODULE_STRIPPED + handle_moddevtable(mod, &info, sym, symname); ++#endif + } + if (!is_vmlinux(modname) || + (is_vmlinux(modname) && vmlinux_section_warnings)) +@@ -1870,7 +1872,9 @@ static void add_header(struct buffer *b, + buf_printf(b, "#include \n"); + buf_printf(b, "#include \n"); + buf_printf(b, "\n"); ++#ifndef CONFIG_MODULE_STRIPPED + buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n"); ++#endif + buf_printf(b, "\n"); + buf_printf(b, "__visible struct module __this_module\n"); + buf_printf(b, "__attribute__((section(\".gnu.linkonce.this_module\"))) = {\n"); +@@ -1887,16 +1891,20 @@ static void add_header(struct buffer *b, + + static void add_intree_flag(struct buffer *b, int is_intree) + { ++#ifndef CONFIG_MODULE_STRIPPED + if (is_intree) + buf_printf(b, "\nMODULE_INFO(intree, \"Y\");\n"); ++#endif + } + + static void add_staging_flag(struct buffer *b, const char *name) + { ++#ifndef CONFIG_MODULE_STRIPPED + static const char *staging_dir = "drivers/staging"; + + if (strncmp(staging_dir, name, strlen(staging_dir)) == 0) + buf_printf(b, "\nMODULE_INFO(staging, \"Y\");\n"); ++#endif + } + + /** +@@ -1989,11 +1997,13 @@ static void add_depends(struct buffer *b + + static void add_srcversion(struct buffer *b, struct module *mod) + { ++#ifndef CONFIG_MODULE_STRIPPED + if (mod->srcversion[0]) { + buf_printf(b, "\n"); + buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n", + mod->srcversion); + } ++#endif + } + + static void write_if_changed(struct buffer *b, const char *fname) +@@ -2224,7 +2234,9 @@ int main(int argc, char **argv) + add_staging_flag(&buf, mod->name); + err |= add_versions(&buf, mod); + add_depends(&buf, mod, modules); ++#ifndef CONFIG_MODULE_STRIPPED + add_moddevtable(&buf, mod); ++#endif + add_srcversion(&buf, mod); + + sprintf(fname, "%s.mod.c", mod->name); diff --git a/target/linux/generic/patches-3.18/205-backtrace_module_info.patch b/target/linux/generic/patches-3.18/205-backtrace_module_info.patch new file mode 100644 index 0000000..f83b21e --- /dev/null +++ b/target/linux/generic/patches-3.18/205-backtrace_module_info.patch @@ -0,0 +1,36 @@ +--- a/lib/vsprintf.c ++++ b/lib/vsprintf.c +@@ -614,8 +614,10 @@ char *symbol_string(char *buf, char *end + struct printf_spec spec, const char *fmt) + { + unsigned long value; +-#ifdef CONFIG_KALLSYMS + char sym[KSYM_SYMBOL_LEN]; ++#ifndef CONFIG_KALLSYMS ++ struct module *mod; ++ int len; + #endif + + if (fmt[1] == 'R') +@@ -629,15 +631,15 @@ char *symbol_string(char *buf, char *end + sprint_symbol(sym, value); + else + sprint_symbol_no_offset(sym, value); +- +- return string(buf, end, sym, spec); + #else +- spec.field_width = 2 * sizeof(void *); +- spec.flags |= SPECIAL | SMALL | ZEROPAD; +- spec.base = 16; ++ len = snprintf(sym, sizeof(sym), "0x%lx", value); + +- return number(buf, end, value, spec); ++ mod = __module_address(value); ++ if (mod) ++ snprintf(sym + len, sizeof(sym) - len, " [%s@%p+0x%x]", ++ mod->name, mod->module_core, mod->core_size); + #endif ++ return string(buf, end, sym, spec); + } + + static noinline_for_stack diff --git a/target/linux/generic/patches-3.18/210-darwin_scripts_include.patch b/target/linux/generic/patches-3.18/210-darwin_scripts_include.patch new file mode 100644 index 0000000..dc554de --- /dev/null +++ b/target/linux/generic/patches-3.18/210-darwin_scripts_include.patch @@ -0,0 +1,3088 @@ +--- a/scripts/kallsyms.c ++++ b/scripts/kallsyms.c +@@ -22,6 +22,35 @@ + #include + #include + #include ++#ifdef __APPLE__ ++/* Darwin has no memmem implementation, this one is ripped of the uClibc-0.9.28 source */ ++void *memmem (const void *haystack, size_t haystack_len, ++ const void *needle, size_t needle_len) ++{ ++ const char *begin; ++ const char *const last_possible ++ = (const char *) haystack + haystack_len - needle_len; ++ ++ if (needle_len == 0) ++ /* The first occurrence of the empty string is deemed to occur at ++ the beginning of the string. */ ++ return (void *) haystack; ++ ++ /* Sanity check, otherwise the loop might search through the whole ++ memory. */ ++ if (__builtin_expect (haystack_len < needle_len, 0)) ++ return NULL; ++ ++ for (begin = (const char *) haystack; begin <= last_possible; ++begin) ++ if (begin[0] == ((const char *) needle)[0] && ++ !memcmp ((const void *) &begin[1], ++ (const void *) ((const char *) needle + 1), ++ needle_len - 1)) ++ return (void *) begin; ++ ++ return NULL; ++} ++#endif + + #ifndef ARRAY_SIZE + #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) +--- a/scripts/kconfig/Makefile ++++ b/scripts/kconfig/Makefile +@@ -151,6 +151,9 @@ check-lxdialog := $(srctree)/$(src)/lxd + # we really need to do so. (Do not call gcc as part of make mrproper) + HOST_EXTRACFLAGS += $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags) \ + -DLOCALE ++ifeq ($(shell uname -s),Darwin) ++HOST_LOADLIBES += -lncurses ++endif + + # =========================================================================== + # Shared Makefile for the various kconfig executables: +--- a/scripts/mod/mk_elfconfig.c ++++ b/scripts/mod/mk_elfconfig.c +@@ -1,7 +1,11 @@ + #include + #include + #include ++#ifndef __APPLE__ + #include ++#else ++#include "elf.h" ++#endif + + int + main(int argc, char **argv) +--- a/scripts/mod/modpost.h ++++ b/scripts/mod/modpost.h +@@ -7,7 +7,11 @@ + #include + #include + #include ++#if !(defined(__APPLE__) || defined(__CYGWIN__)) + #include ++#else ++#include "elf.h" ++#endif + + #include "elfconfig.h" + +--- /dev/null ++++ b/scripts/mod/elf.h +@@ -0,0 +1,3007 @@ ++/* This file defines standard ELF types, structures, and macros. ++ Copyright (C) 1995-2012 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, see ++ . */ ++ ++#ifndef _ELF_H ++#define _ELF_H 1 ++ ++/* Standard ELF types. */ ++ ++#include ++ ++/* Type for a 16-bit quantity. */ ++typedef uint16_t Elf32_Half; ++typedef uint16_t Elf64_Half; ++ ++/* Types for signed and unsigned 32-bit quantities. */ ++typedef uint32_t Elf32_Word; ++typedef int32_t Elf32_Sword; ++typedef uint32_t Elf64_Word; ++typedef int32_t Elf64_Sword; ++ ++/* Types for signed and unsigned 64-bit quantities. */ ++typedef uint64_t Elf32_Xword; ++typedef int64_t Elf32_Sxword; ++typedef uint64_t Elf64_Xword; ++typedef int64_t Elf64_Sxword; ++ ++/* Type of addresses. */ ++typedef uint32_t Elf32_Addr; ++typedef uint64_t Elf64_Addr; ++ ++/* Type of file offsets. */ ++typedef uint32_t Elf32_Off; ++typedef uint64_t Elf64_Off; ++ ++/* Type for section indices, which are 16-bit quantities. */ ++typedef uint16_t Elf32_Section; ++typedef uint16_t Elf64_Section; ++ ++/* Type for version symbol information. */ ++typedef Elf32_Half Elf32_Versym; ++typedef Elf64_Half Elf64_Versym; ++ ++ ++/* The ELF file header. This appears at the start of every ELF file. */ ++ ++#define EI_NIDENT (16) ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf32_Half e_type; /* Object file type */ ++ Elf32_Half e_machine; /* Architecture */ ++ Elf32_Word e_version; /* Object file version */ ++ Elf32_Addr e_entry; /* Entry point virtual address */ ++ Elf32_Off e_phoff; /* Program header table file offset */ ++ Elf32_Off e_shoff; /* Section header table file offset */ ++ Elf32_Word e_flags; /* Processor-specific flags */ ++ Elf32_Half e_ehsize; /* ELF header size in bytes */ ++ Elf32_Half e_phentsize; /* Program header table entry size */ ++ Elf32_Half e_phnum; /* Program header table entry count */ ++ Elf32_Half e_shentsize; /* Section header table entry size */ ++ Elf32_Half e_shnum; /* Section header table entry count */ ++ Elf32_Half e_shstrndx; /* Section header string table index */ ++} Elf32_Ehdr; ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf64_Half e_type; /* Object file type */ ++ Elf64_Half e_machine; /* Architecture */ ++ Elf64_Word e_version; /* Object file version */ ++ Elf64_Addr e_entry; /* Entry point virtual address */ ++ Elf64_Off e_phoff; /* Program header table file offset */ ++ Elf64_Off e_shoff; /* Section header table file offset */ ++ Elf64_Word e_flags; /* Processor-specific flags */ ++ Elf64_Half e_ehsize; /* ELF header size in bytes */ ++ Elf64_Half e_phentsize; /* Program header table entry size */ ++ Elf64_Half e_phnum; /* Program header table entry count */ ++ Elf64_Half e_shentsize; /* Section header table entry size */ ++ Elf64_Half e_shnum; /* Section header table entry count */ ++ Elf64_Half e_shstrndx; /* Section header string table index */ ++} Elf64_Ehdr; ++ ++/* Fields in the e_ident array. The EI_* macros are indices into the ++ array. The macros under each EI_* macro are the values the byte ++ may have. */ ++ ++#define EI_MAG0 0 /* File identification byte 0 index */ ++#define ELFMAG0 0x7f /* Magic number byte 0 */ ++ ++#define EI_MAG1 1 /* File identification byte 1 index */ ++#define ELFMAG1 'E' /* Magic number byte 1 */ ++ ++#define EI_MAG2 2 /* File identification byte 2 index */ ++#define ELFMAG2 'L' /* Magic number byte 2 */ ++ ++#define EI_MAG3 3 /* File identification byte 3 index */ ++#define ELFMAG3 'F' /* Magic number byte 3 */ ++ ++/* Conglomeration of the identification bytes, for easy testing as a word. */ ++#define ELFMAG "\177ELF" ++#define SELFMAG 4 ++ ++#define EI_CLASS 4 /* File class byte index */ ++#define ELFCLASSNONE 0 /* Invalid class */ ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++#define ELFCLASSNUM 3 ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATANONE 0 /* Invalid data encoding */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ ++#define ELFDATANUM 3 ++ ++#define EI_VERSION 6 /* File version byte index */ ++ /* Value must be EV_CURRENT */ ++ ++#define EI_OSABI 7 /* OS ABI identification */ ++#define ELFOSABI_NONE 0 /* UNIX System V ABI */ ++#define ELFOSABI_SYSV 0 /* Alias. */ ++#define ELFOSABI_HPUX 1 /* HP-UX */ ++#define ELFOSABI_NETBSD 2 /* NetBSD. */ ++#define ELFOSABI_GNU 3 /* Object uses GNU ELF extensions. */ ++#define ELFOSABI_LINUX ELFOSABI_GNU /* Compatibility alias. */ ++#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ ++#define ELFOSABI_AIX 7 /* IBM AIX. */ ++#define ELFOSABI_IRIX 8 /* SGI Irix. */ ++#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ ++#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ ++#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ ++#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ ++#define ELFOSABI_ARM_AEABI 64 /* ARM EABI */ ++#define ELFOSABI_ARM 97 /* ARM */ ++#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ ++ ++#define EI_ABIVERSION 8 /* ABI version */ ++ ++#define EI_PAD 9 /* Byte index of padding bytes */ ++ ++/* Legal values for e_type (object file type). */ ++ ++#define ET_NONE 0 /* No file type */ ++#define ET_REL 1 /* Relocatable file */ ++#define ET_EXEC 2 /* Executable file */ ++#define ET_DYN 3 /* Shared object file */ ++#define ET_CORE 4 /* Core file */ ++#define ET_NUM 5 /* Number of defined types */ ++#define ET_LOOS 0xfe00 /* OS-specific range start */ ++#define ET_HIOS 0xfeff /* OS-specific range end */ ++#define ET_LOPROC 0xff00 /* Processor-specific range start */ ++#define ET_HIPROC 0xffff /* Processor-specific range end */ ++ ++/* Legal values for e_machine (architecture). */ ++ ++#define EM_NONE 0 /* No machine */ ++#define EM_M32 1 /* AT&T WE 32100 */ ++#define EM_SPARC 2 /* SUN SPARC */ ++#define EM_386 3 /* Intel 80386 */ ++#define EM_68K 4 /* Motorola m68k family */ ++#define EM_88K 5 /* Motorola m88k family */ ++#define EM_860 7 /* Intel 80860 */ ++#define EM_MIPS 8 /* MIPS R3000 big-endian */ ++#define EM_S370 9 /* IBM System/370 */ ++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ ++ ++#define EM_PARISC 15 /* HPPA */ ++#define EM_VPP500 17 /* Fujitsu VPP500 */ ++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ ++#define EM_960 19 /* Intel 80960 */ ++#define EM_PPC 20 /* PowerPC */ ++#define EM_PPC64 21 /* PowerPC 64-bit */ ++#define EM_S390 22 /* IBM S390 */ ++ ++#define EM_V800 36 /* NEC V800 series */ ++#define EM_FR20 37 /* Fujitsu FR20 */ ++#define EM_RH32 38 /* TRW RH-32 */ ++#define EM_RCE 39 /* Motorola RCE */ ++#define EM_ARM 40 /* ARM */ ++#define EM_FAKE_ALPHA 41 /* Digital Alpha */ ++#define EM_SH 42 /* Hitachi SH */ ++#define EM_SPARCV9 43 /* SPARC v9 64-bit */ ++#define EM_TRICORE 44 /* Siemens Tricore */ ++#define EM_ARC 45 /* Argonaut RISC Core */ ++#define EM_H8_300 46 /* Hitachi H8/300 */ ++#define EM_H8_300H 47 /* Hitachi H8/300H */ ++#define EM_H8S 48 /* Hitachi H8S */ ++#define EM_H8_500 49 /* Hitachi H8/500 */ ++#define EM_IA_64 50 /* Intel Merced */ ++#define EM_MIPS_X 51 /* Stanford MIPS-X */ ++#define EM_COLDFIRE 52 /* Motorola Coldfire */ ++#define EM_68HC12 53 /* Motorola M68HC12 */ ++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ ++#define EM_PCP 55 /* Siemens PCP */ ++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ ++#define EM_NDR1 57 /* Denso NDR1 microprocessor */ ++#define EM_STARCORE 58 /* Motorola Start*Core processor */ ++#define EM_ME16 59 /* Toyota ME16 processor */ ++#define EM_ST100 60 /* STMicroelectronic ST100 processor */ ++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ ++#define EM_X86_64 62 /* AMD x86-64 architecture */ ++#define EM_PDSP 63 /* Sony DSP Processor */ ++ ++#define EM_FX66 66 /* Siemens FX66 microcontroller */ ++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ ++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ ++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ ++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ ++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ ++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ ++#define EM_SVX 73 /* Silicon Graphics SVx */ ++#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ ++#define EM_VAX 75 /* Digital VAX */ ++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ ++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ ++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ ++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ ++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ ++#define EM_HUANY 81 /* Harvard University machine-independent object files */ ++#define EM_PRISM 82 /* SiTera Prism */ ++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ ++#define EM_FR30 84 /* Fujitsu FR30 */ ++#define EM_D10V 85 /* Mitsubishi D10V */ ++#define EM_D30V 86 /* Mitsubishi D30V */ ++#define EM_V850 87 /* NEC v850 */ ++#define EM_M32R 88 /* Mitsubishi M32R */ ++#define EM_MN10300 89 /* Matsushita MN10300 */ ++#define EM_MN10200 90 /* Matsushita MN10200 */ ++#define EM_PJ 91 /* picoJava */ ++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ ++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ ++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ ++#define EM_TILEPRO 188 /* Tilera TILEPro */ ++#define EM_TILEGX 191 /* Tilera TILE-Gx */ ++#define EM_NUM 192 ++ ++/* If it is necessary to assign new unofficial EM_* values, please ++ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the ++ chances of collision with official or non-GNU unofficial values. */ ++ ++#define EM_ALPHA 0x9026 ++ ++/* Legal values for e_version (version). */ ++ ++#define EV_NONE 0 /* Invalid ELF version */ ++#define EV_CURRENT 1 /* Current version */ ++#define EV_NUM 2 ++ ++/* Section header. */ ++ ++typedef struct ++{ ++ Elf32_Word sh_name; /* Section name (string tbl index) */ ++ Elf32_Word sh_type; /* Section type */ ++ Elf32_Word sh_flags; /* Section flags */ ++ Elf32_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf32_Off sh_offset; /* Section file offset */ ++ Elf32_Word sh_size; /* Section size in bytes */ ++ Elf32_Word sh_link; /* Link to another section */ ++ Elf32_Word sh_info; /* Additional section information */ ++ Elf32_Word sh_addralign; /* Section alignment */ ++ Elf32_Word sh_entsize; /* Entry size if section holds table */ ++} Elf32_Shdr; ++ ++typedef struct ++{ ++ Elf64_Word sh_name; /* Section name (string tbl index) */ ++ Elf64_Word sh_type; /* Section type */ ++ Elf64_Xword sh_flags; /* Section flags */ ++ Elf64_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf64_Off sh_offset; /* Section file offset */ ++ Elf64_Xword sh_size; /* Section size in bytes */ ++ Elf64_Word sh_link; /* Link to another section */ ++ Elf64_Word sh_info; /* Additional section information */ ++ Elf64_Xword sh_addralign; /* Section alignment */ ++ Elf64_Xword sh_entsize; /* Entry size if section holds table */ ++} Elf64_Shdr; ++ ++/* Special section indices. */ ++ ++#define SHN_UNDEF 0 /* Undefined section */ ++#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ ++#define SHN_LOPROC 0xff00 /* Start of processor-specific */ ++#define SHN_BEFORE 0xff00 /* Order section before all others ++ (Solaris). */ ++#define SHN_AFTER 0xff01 /* Order section after all others ++ (Solaris). */ ++#define SHN_HIPROC 0xff1f /* End of processor-specific */ ++#define SHN_LOOS 0xff20 /* Start of OS-specific */ ++#define SHN_HIOS 0xff3f /* End of OS-specific */ ++#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ ++#define SHN_COMMON 0xfff2 /* Associated symbol is common */ ++#define SHN_XINDEX 0xffff /* Index is in extra table. */ ++#define SHN_HIRESERVE 0xffff /* End of reserved indices */ ++ ++/* Legal values for sh_type (section type). */ ++ ++#define SHT_NULL 0 /* Section header table entry unused */ ++#define SHT_PROGBITS 1 /* Program data */ ++#define SHT_SYMTAB 2 /* Symbol table */ ++#define SHT_STRTAB 3 /* String table */ ++#define SHT_RELA 4 /* Relocation entries with addends */ ++#define SHT_HASH 5 /* Symbol hash table */ ++#define SHT_DYNAMIC 6 /* Dynamic linking information */ ++#define SHT_NOTE 7 /* Notes */ ++#define SHT_NOBITS 8 /* Program space with no data (bss) */ ++#define SHT_REL 9 /* Relocation entries, no addends */ ++#define SHT_SHLIB 10 /* Reserved */ ++#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ ++#define SHT_INIT_ARRAY 14 /* Array of constructors */ ++#define SHT_FINI_ARRAY 15 /* Array of destructors */ ++#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ ++#define SHT_GROUP 17 /* Section group */ ++#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ ++#define SHT_NUM 19 /* Number of defined types. */ ++#define SHT_LOOS 0x60000000 /* Start OS-specific. */ ++#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes. */ ++#define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ ++#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ ++#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ ++#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ ++#define SHT_SUNW_move 0x6ffffffa ++#define SHT_SUNW_COMDAT 0x6ffffffb ++#define SHT_SUNW_syminfo 0x6ffffffc ++#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ ++#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ ++#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ ++#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ ++#define SHT_HIOS 0x6fffffff /* End OS-specific type */ ++#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define SHT_LOUSER 0x80000000 /* Start of application-specific */ ++#define SHT_HIUSER 0x8fffffff /* End of application-specific */ ++ ++/* Legal values for sh_flags (section flags). */ ++ ++#define SHF_WRITE (1 << 0) /* Writable */ ++#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ ++#define SHF_EXECINSTR (1 << 2) /* Executable */ ++#define SHF_MERGE (1 << 4) /* Might be merged */ ++#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ ++#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ ++#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ ++#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling ++ required */ ++#define SHF_GROUP (1 << 9) /* Section is member of a group. */ ++#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ ++#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ ++#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ ++#define SHF_ORDERED (1 << 30) /* Special ordering requirement ++ (Solaris). */ ++#define SHF_EXCLUDE (1 << 31) /* Section is excluded unless ++ referenced or allocated (Solaris).*/ ++ ++/* Section group handling. */ ++#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ ++ ++/* Symbol table entry. */ ++ ++typedef struct ++{ ++ Elf32_Word st_name; /* Symbol name (string tbl index) */ ++ Elf32_Addr st_value; /* Symbol value */ ++ Elf32_Word st_size; /* Symbol size */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf32_Section st_shndx; /* Section index */ ++} Elf32_Sym; ++ ++typedef struct ++{ ++ Elf64_Word st_name; /* Symbol name (string tbl index) */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf64_Section st_shndx; /* Section index */ ++ Elf64_Addr st_value; /* Symbol value */ ++ Elf64_Xword st_size; /* Symbol size */ ++} Elf64_Sym; ++ ++/* The syminfo section if available contains additional information about ++ every dynamic symbol. */ ++ ++typedef struct ++{ ++ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf32_Half si_flags; /* Per symbol flags */ ++} Elf32_Syminfo; ++ ++typedef struct ++{ ++ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf64_Half si_flags; /* Per symbol flags */ ++} Elf64_Syminfo; ++ ++/* Possible values for si_boundto. */ ++#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ ++#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ ++#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ ++ ++/* Possible bitmasks for si_flags. */ ++#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ ++#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ ++#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ ++#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy ++ loaded */ ++/* Syminfo version values. */ ++#define SYMINFO_NONE 0 ++#define SYMINFO_CURRENT 1 ++#define SYMINFO_NUM 2 ++ ++ ++/* How to extract and insert information held in the st_info field. */ ++ ++#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) ++#define ELF32_ST_TYPE(val) ((val) & 0xf) ++#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) ++ ++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ ++#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) ++#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) ++#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) ++ ++/* Legal values for ST_BIND subfield of st_info (symbol binding). */ ++ ++#define STB_LOCAL 0 /* Local symbol */ ++#define STB_GLOBAL 1 /* Global symbol */ ++#define STB_WEAK 2 /* Weak symbol */ ++#define STB_NUM 3 /* Number of defined types. */ ++#define STB_LOOS 10 /* Start of OS-specific */ ++#define STB_GNU_UNIQUE 10 /* Unique symbol. */ ++#define STB_HIOS 12 /* End of OS-specific */ ++#define STB_LOPROC 13 /* Start of processor-specific */ ++#define STB_HIPROC 15 /* End of processor-specific */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_NOTYPE 0 /* Symbol type is unspecified */ ++#define STT_OBJECT 1 /* Symbol is a data object */ ++#define STT_FUNC 2 /* Symbol is a code object */ ++#define STT_SECTION 3 /* Symbol associated with a section */ ++#define STT_FILE 4 /* Symbol's name is file name */ ++#define STT_COMMON 5 /* Symbol is a common data object */ ++#define STT_TLS 6 /* Symbol is thread-local data object*/ ++#define STT_NUM 7 /* Number of defined types. */ ++#define STT_LOOS 10 /* Start of OS-specific */ ++#define STT_GNU_IFUNC 10 /* Symbol is indirect code object */ ++#define STT_HIOS 12 /* End of OS-specific */ ++#define STT_LOPROC 13 /* Start of processor-specific */ ++#define STT_HIPROC 15 /* End of processor-specific */ ++ ++ ++/* Symbol table indices are found in the hash buckets and chain table ++ of a symbol hash table section. This special index value indicates ++ the end of a chain, meaning no further symbols are found in that bucket. */ ++ ++#define STN_UNDEF 0 /* End of a chain. */ ++ ++ ++/* How to extract and insert information held in the st_other field. */ ++ ++#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) ++ ++/* For ELF64 the definitions are the same. */ ++#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) ++ ++/* Symbol visibility specification encoded in the st_other field. */ ++#define STV_DEFAULT 0 /* Default symbol visibility rules */ ++#define STV_INTERNAL 1 /* Processor specific hidden class */ ++#define STV_HIDDEN 2 /* Sym unavailable in other modules */ ++#define STV_PROTECTED 3 /* Not preemptible, not exported */ ++ ++ ++/* Relocation table entry without addend (in section of type SHT_REL). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++} Elf32_Rel; ++ ++/* I have seen two different definitions of the Elf64_Rel and ++ Elf64_Rela structures, so we'll leave them out until Novell (or ++ whoever) gets their act together. */ ++/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++} Elf64_Rel; ++ ++/* Relocation table entry with addend (in section of type SHT_RELA). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++ Elf32_Sword r_addend; /* Addend */ ++} Elf32_Rela; ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++ Elf64_Sxword r_addend; /* Addend */ ++} Elf64_Rela; ++ ++/* How to extract and insert information held in the r_info field. */ ++ ++#define ELF32_R_SYM(val) ((val) >> 8) ++#define ELF32_R_TYPE(val) ((val) & 0xff) ++#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) ++ ++#define ELF64_R_SYM(i) ((i) >> 32) ++#define ELF64_R_TYPE(i) ((i) & 0xffffffff) ++#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) ++ ++/* Program segment header. */ ++ ++typedef struct ++{ ++ Elf32_Word p_type; /* Segment type */ ++ Elf32_Off p_offset; /* Segment file offset */ ++ Elf32_Addr p_vaddr; /* Segment virtual address */ ++ Elf32_Addr p_paddr; /* Segment physical address */ ++ Elf32_Word p_filesz; /* Segment size in file */ ++ Elf32_Word p_memsz; /* Segment size in memory */ ++ Elf32_Word p_flags; /* Segment flags */ ++ Elf32_Word p_align; /* Segment alignment */ ++} Elf32_Phdr; ++ ++typedef struct ++{ ++ Elf64_Word p_type; /* Segment type */ ++ Elf64_Word p_flags; /* Segment flags */ ++ Elf64_Off p_offset; /* Segment file offset */ ++ Elf64_Addr p_vaddr; /* Segment virtual address */ ++ Elf64_Addr p_paddr; /* Segment physical address */ ++ Elf64_Xword p_filesz; /* Segment size in file */ ++ Elf64_Xword p_memsz; /* Segment size in memory */ ++ Elf64_Xword p_align; /* Segment alignment */ ++} Elf64_Phdr; ++ ++/* Special value for e_phnum. This indicates that the real number of ++ program headers is too large to fit into e_phnum. Instead the real ++ value is in the field sh_info of section 0. */ ++ ++#define PN_XNUM 0xffff ++ ++/* Legal values for p_type (segment type). */ ++ ++#define PT_NULL 0 /* Program header table entry unused */ ++#define PT_LOAD 1 /* Loadable program segment */ ++#define PT_DYNAMIC 2 /* Dynamic linking information */ ++#define PT_INTERP 3 /* Program interpreter */ ++#define PT_NOTE 4 /* Auxiliary information */ ++#define PT_SHLIB 5 /* Reserved */ ++#define PT_PHDR 6 /* Entry for header table itself */ ++#define PT_TLS 7 /* Thread-local storage segment */ ++#define PT_NUM 8 /* Number of defined types */ ++#define PT_LOOS 0x60000000 /* Start of OS-specific */ ++#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ ++#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ ++#define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ ++#define PT_LOSUNW 0x6ffffffa ++#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ ++#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ ++#define PT_HISUNW 0x6fffffff ++#define PT_HIOS 0x6fffffff /* End of OS-specific */ ++#define PT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define PT_HIPROC 0x7fffffff /* End of processor-specific */ ++ ++/* Legal values for p_flags (segment flags). */ ++ ++#define PF_X (1 << 0) /* Segment is executable */ ++#define PF_W (1 << 1) /* Segment is writable */ ++#define PF_R (1 << 2) /* Segment is readable */ ++#define PF_MASKOS 0x0ff00000 /* OS-specific */ ++#define PF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Legal values for note segment descriptor types for core files. */ ++ ++#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ ++#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ ++#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ ++#define NT_PRXREG 4 /* Contains copy of prxregset struct */ ++#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ ++#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ ++#define NT_AUXV 6 /* Contains copy of auxv array */ ++#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ ++#define NT_ASRS 8 /* Contains copy of asrset struct */ ++#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ ++#define NT_PSINFO 13 /* Contains copy of psinfo struct */ ++#define NT_PRCRED 14 /* Contains copy of prcred struct */ ++#define NT_UTSNAME 15 /* Contains copy of utsname struct */ ++#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ ++#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ ++#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ ++#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ ++#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ ++#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ ++#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ ++#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ ++#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ ++#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ ++ ++/* Legal values for the note segment descriptor types for object files. */ ++ ++#define NT_VERSION 1 /* Contains a version string. */ ++ ++ ++/* Dynamic section entry. */ ++ ++typedef struct ++{ ++ Elf32_Sword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf32_Word d_val; /* Integer value */ ++ Elf32_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf32_Dyn; ++ ++typedef struct ++{ ++ Elf64_Sxword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf64_Xword d_val; /* Integer value */ ++ Elf64_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf64_Dyn; ++ ++/* Legal values for d_tag (dynamic entry type). */ ++ ++#define DT_NULL 0 /* Marks end of dynamic section */ ++#define DT_NEEDED 1 /* Name of needed library */ ++#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ ++#define DT_PLTGOT 3 /* Processor defined value */ ++#define DT_HASH 4 /* Address of symbol hash table */ ++#define DT_STRTAB 5 /* Address of string table */ ++#define DT_SYMTAB 6 /* Address of symbol table */ ++#define DT_RELA 7 /* Address of Rela relocs */ ++#define DT_RELASZ 8 /* Total size of Rela relocs */ ++#define DT_RELAENT 9 /* Size of one Rela reloc */ ++#define DT_STRSZ 10 /* Size of string table */ ++#define DT_SYMENT 11 /* Size of one symbol table entry */ ++#define DT_INIT 12 /* Address of init function */ ++#define DT_FINI 13 /* Address of termination function */ ++#define DT_SONAME 14 /* Name of shared object */ ++#define DT_RPATH 15 /* Library search path (deprecated) */ ++#define DT_SYMBOLIC 16 /* Start symbol search here */ ++#define DT_REL 17 /* Address of Rel relocs */ ++#define DT_RELSZ 18 /* Total size of Rel relocs */ ++#define DT_RELENT 19 /* Size of one Rel reloc */ ++#define DT_PLTREL 20 /* Type of reloc in PLT */ ++#define DT_DEBUG 21 /* For debugging; unspecified */ ++#define DT_TEXTREL 22 /* Reloc might modify .text */ ++#define DT_JMPREL 23 /* Address of PLT relocs */ ++#define DT_BIND_NOW 24 /* Process relocations of object */ ++#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ ++#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ ++#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ ++#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ ++#define DT_RUNPATH 29 /* Library search path */ ++#define DT_FLAGS 30 /* Flags for the object being loaded */ ++#define DT_ENCODING 32 /* Start of encoded range */ ++#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ ++#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ ++#define DT_NUM 34 /* Number used */ ++#define DT_LOOS 0x6000000d /* Start of OS-specific */ ++#define DT_HIOS 0x6ffff000 /* End of OS-specific */ ++#define DT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define DT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ ++ ++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the ++ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's ++ approach. */ ++#define DT_VALRNGLO 0x6ffffd00 ++#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ ++#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ ++#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ ++#define DT_CHECKSUM 0x6ffffdf8 ++#define DT_PLTPADSZ 0x6ffffdf9 ++#define DT_MOVEENT 0x6ffffdfa ++#define DT_MOVESZ 0x6ffffdfb ++#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ ++#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting ++ the following DT_* entry. */ ++#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ ++#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ ++#define DT_VALRNGHI 0x6ffffdff ++#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ ++#define DT_VALNUM 12 ++ ++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the ++ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. ++ ++ If any adjustment is made to the ELF object after it has been ++ built these entries will need to be adjusted. */ ++#define DT_ADDRRNGLO 0x6ffffe00 ++#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ ++#define DT_TLSDESC_PLT 0x6ffffef6 ++#define DT_TLSDESC_GOT 0x6ffffef7 ++#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ ++#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ ++#define DT_CONFIG 0x6ffffefa /* Configuration information. */ ++#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ ++#define DT_AUDIT 0x6ffffefc /* Object auditing. */ ++#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ ++#define DT_MOVETAB 0x6ffffefe /* Move table. */ ++#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ ++#define DT_ADDRRNGHI 0x6ffffeff ++#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ ++#define DT_ADDRNUM 11 ++ ++/* The versioning entry types. The next are defined as part of the ++ GNU extension. */ ++#define DT_VERSYM 0x6ffffff0 ++ ++#define DT_RELACOUNT 0x6ffffff9 ++#define DT_RELCOUNT 0x6ffffffa ++ ++/* These were chosen by Sun. */ ++#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ ++#define DT_VERDEF 0x6ffffffc /* Address of version definition ++ table */ ++#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ ++#define DT_VERNEED 0x6ffffffe /* Address of table with needed ++ versions */ ++#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ ++#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ ++#define DT_VERSIONTAGNUM 16 ++ ++/* Sun added these machine-independent extensions in the "processor-specific" ++ range. Be compatible. */ ++#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ ++#define DT_FILTER 0x7fffffff /* Shared object to get values from */ ++#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) ++#define DT_EXTRANUM 3 ++ ++/* Values of `d_un.d_val' in the DT_FLAGS entry. */ ++#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ ++#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ ++#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ ++#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ ++#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ ++ ++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 ++ entry in the dynamic section. */ ++#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ ++#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ ++#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ ++#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ ++#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ ++#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ ++#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ ++#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ ++#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ ++#define DF_1_TRANS 0x00000200 ++#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ ++#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ ++#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ ++#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ ++#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ ++#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ ++#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ ++ ++/* Flags for the feature selection in DT_FEATURE_1. */ ++#define DTF_1_PARINIT 0x00000001 ++#define DTF_1_CONFEXP 0x00000002 ++ ++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ ++#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ ++#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not ++ generally available. */ ++ ++/* Version definition sections. */ ++ ++typedef struct ++{ ++ Elf32_Half vd_version; /* Version revision */ ++ Elf32_Half vd_flags; /* Version information */ ++ Elf32_Half vd_ndx; /* Version Index */ ++ Elf32_Half vd_cnt; /* Number of associated aux entries */ ++ Elf32_Word vd_hash; /* Version name hash value */ ++ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf32_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf32_Verdef; ++ ++typedef struct ++{ ++ Elf64_Half vd_version; /* Version revision */ ++ Elf64_Half vd_flags; /* Version information */ ++ Elf64_Half vd_ndx; /* Version Index */ ++ Elf64_Half vd_cnt; /* Number of associated aux entries */ ++ Elf64_Word vd_hash; /* Version name hash value */ ++ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf64_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf64_Verdef; ++ ++ ++/* Legal values for vd_version (version revision). */ ++#define VER_DEF_NONE 0 /* No version */ ++#define VER_DEF_CURRENT 1 /* Current version */ ++#define VER_DEF_NUM 2 /* Given version number */ ++ ++/* Legal values for vd_flags (version information flags). */ ++#define VER_FLG_BASE 0x1 /* Version definition of file itself */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++/* Versym symbol index values. */ ++#define VER_NDX_LOCAL 0 /* Symbol is local. */ ++#define VER_NDX_GLOBAL 1 /* Symbol is global. */ ++#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ ++#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ ++ ++/* Auxialiary version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vda_name; /* Version or dependency names */ ++ Elf32_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf32_Verdaux; ++ ++typedef struct ++{ ++ Elf64_Word vda_name; /* Version or dependency names */ ++ Elf64_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf64_Verdaux; ++ ++ ++/* Version dependency section. */ ++ ++typedef struct ++{ ++ Elf32_Half vn_version; /* Version of structure */ ++ Elf32_Half vn_cnt; /* Number of associated aux entries */ ++ Elf32_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf32_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf32_Verneed; ++ ++typedef struct ++{ ++ Elf64_Half vn_version; /* Version of structure */ ++ Elf64_Half vn_cnt; /* Number of associated aux entries */ ++ Elf64_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf64_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf64_Verneed; ++ ++ ++/* Legal values for vn_version (version revision). */ ++#define VER_NEED_NONE 0 /* No version */ ++#define VER_NEED_CURRENT 1 /* Current version */ ++#define VER_NEED_NUM 2 /* Given version number */ ++ ++/* Auxiliary needed version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vna_hash; /* Hash value of dependency name */ ++ Elf32_Half vna_flags; /* Dependency specific information */ ++ Elf32_Half vna_other; /* Unused */ ++ Elf32_Word vna_name; /* Dependency name string offset */ ++ Elf32_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf32_Vernaux; ++ ++typedef struct ++{ ++ Elf64_Word vna_hash; /* Hash value of dependency name */ ++ Elf64_Half vna_flags; /* Dependency specific information */ ++ Elf64_Half vna_other; /* Unused */ ++ Elf64_Word vna_name; /* Dependency name string offset */ ++ Elf64_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf64_Vernaux; ++ ++ ++/* Legal values for vna_flags. */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++ ++/* Auxiliary vector. */ ++ ++/* This vector is normally only used by the program interpreter. The ++ usual definition in an ABI supplement uses the name auxv_t. The ++ vector is not usually defined in a standard file, but it ++ can't hurt. We rename it to avoid conflicts. The sizes of these ++ types are an arrangement between the exec server and the program ++ interpreter, so we don't fully specify them here. */ ++ ++typedef struct ++{ ++ uint32_t a_type; /* Entry type */ ++ union ++ { ++ uint32_t a_val; /* Integer value */ ++ /* We use to have pointer elements added here. We cannot do that, ++ though, since it does not work when using 32-bit definitions ++ on 64-bit platforms and vice versa. */ ++ } a_un; ++} Elf32_auxv_t; ++ ++typedef struct ++{ ++ uint64_t a_type; /* Entry type */ ++ union ++ { ++ uint64_t a_val; /* Integer value */ ++ /* We use to have pointer elements added here. We cannot do that, ++ though, since it does not work when using 32-bit definitions ++ on 64-bit platforms and vice versa. */ ++ } a_un; ++} Elf64_auxv_t; ++ ++/* Legal values for a_type (entry type). */ ++ ++#define AT_NULL 0 /* End of vector */ ++#define AT_IGNORE 1 /* Entry should be ignored */ ++#define AT_EXECFD 2 /* File descriptor of program */ ++#define AT_PHDR 3 /* Program headers for program */ ++#define AT_PHENT 4 /* Size of program header entry */ ++#define AT_PHNUM 5 /* Number of program headers */ ++#define AT_PAGESZ 6 /* System page size */ ++#define AT_BASE 7 /* Base address of interpreter */ ++#define AT_FLAGS 8 /* Flags */ ++#define AT_ENTRY 9 /* Entry point of program */ ++#define AT_NOTELF 10 /* Program is not ELF */ ++#define AT_UID 11 /* Real uid */ ++#define AT_EUID 12 /* Effective uid */ ++#define AT_GID 13 /* Real gid */ ++#define AT_EGID 14 /* Effective gid */ ++#define AT_CLKTCK 17 /* Frequency of times() */ ++ ++/* Some more special a_type values describing the hardware. */ ++#define AT_PLATFORM 15 /* String identifying platform. */ ++#define AT_HWCAP 16 /* Machine dependent hints about ++ processor capabilities. */ ++ ++/* This entry gives some information about the FPU initialization ++ performed by the kernel. */ ++#define AT_FPUCW 18 /* Used FPU control word. */ ++ ++/* Cache block sizes. */ ++#define AT_DCACHEBSIZE 19 /* Data cache block size. */ ++#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ ++#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ ++ ++/* A special ignored value for PPC, used by the kernel to control the ++ interpretation of the AUXV. Must be > 16. */ ++#define AT_IGNOREPPC 22 /* Entry should be ignored. */ ++ ++#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ ++ ++#define AT_BASE_PLATFORM 24 /* String identifying real platforms.*/ ++ ++#define AT_RANDOM 25 /* Address of 16 random bytes. */ ++ ++#define AT_EXECFN 31 /* Filename of executable. */ ++ ++/* Pointer to the global system page used for system calls and other ++ nice things. */ ++#define AT_SYSINFO 32 ++#define AT_SYSINFO_EHDR 33 ++ ++/* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains ++ log2 of line size; mask those to get cache size. */ ++#define AT_L1I_CACHESHAPE 34 ++#define AT_L1D_CACHESHAPE 35 ++#define AT_L2_CACHESHAPE 36 ++#define AT_L3_CACHESHAPE 37 ++ ++/* Note section contents. Each entry in the note section begins with ++ a header of a fixed form. */ ++ ++typedef struct ++{ ++ Elf32_Word n_namesz; /* Length of the note's name. */ ++ Elf32_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf32_Word n_type; /* Type of the note. */ ++} Elf32_Nhdr; ++ ++typedef struct ++{ ++ Elf64_Word n_namesz; /* Length of the note's name. */ ++ Elf64_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf64_Word n_type; /* Type of the note. */ ++} Elf64_Nhdr; ++ ++/* Known names of notes. */ ++ ++/* Solaris entries in the note section have this name. */ ++#define ELF_NOTE_SOLARIS "SUNW Solaris" ++ ++/* Note entries for GNU systems have this name. */ ++#define ELF_NOTE_GNU "GNU" ++ ++ ++/* Defined types of notes for Solaris. */ ++ ++/* Value of descriptor (one word) is desired pagesize for the binary. */ ++#define ELF_NOTE_PAGESIZE_HINT 1 ++ ++ ++/* Defined note types for GNU systems. */ ++ ++/* ABI information. The descriptor consists of words: ++ word 0: OS descriptor ++ word 1: major version of the ABI ++ word 2: minor version of the ABI ++ word 3: subminor version of the ABI ++*/ ++#define NT_GNU_ABI_TAG 1 ++#define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ ++ ++/* Known OSes. These values can appear in word 0 of an ++ NT_GNU_ABI_TAG note section entry. */ ++#define ELF_NOTE_OS_LINUX 0 ++#define ELF_NOTE_OS_GNU 1 ++#define ELF_NOTE_OS_SOLARIS2 2 ++#define ELF_NOTE_OS_FREEBSD 3 ++ ++/* Synthetic hwcap information. The descriptor begins with two words: ++ word 0: number of entries ++ word 1: bitmask of enabled entries ++ Then follow variable-length entries, one byte followed by a ++ '\0'-terminated hwcap name string. The byte gives the bit ++ number to test if enabled, (1U << bit) & bitmask. */ ++#define NT_GNU_HWCAP 2 ++ ++/* Build ID bits as generated by ld --build-id. ++ The descriptor consists of any nonzero number of bytes. */ ++#define NT_GNU_BUILD_ID 3 ++ ++/* Version note generated by GNU gold containing a version string. */ ++#define NT_GNU_GOLD_VERSION 4 ++ ++ ++/* Move records. */ ++typedef struct ++{ ++ Elf32_Xword m_value; /* Symbol value. */ ++ Elf32_Word m_info; /* Size and index. */ ++ Elf32_Word m_poffset; /* Symbol offset. */ ++ Elf32_Half m_repeat; /* Repeat count. */ ++ Elf32_Half m_stride; /* Stride info. */ ++} Elf32_Move; ++ ++typedef struct ++{ ++ Elf64_Xword m_value; /* Symbol value. */ ++ Elf64_Xword m_info; /* Size and index. */ ++ Elf64_Xword m_poffset; /* Symbol offset. */ ++ Elf64_Half m_repeat; /* Repeat count. */ ++ Elf64_Half m_stride; /* Stride info. */ ++} Elf64_Move; ++ ++/* Macro to construct move records. */ ++#define ELF32_M_SYM(info) ((info) >> 8) ++#define ELF32_M_SIZE(info) ((unsigned char) (info)) ++#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) ++ ++#define ELF64_M_SYM(info) ELF32_M_SYM (info) ++#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) ++#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) ++ ++ ++/* Motorola 68k specific definitions. */ ++ ++/* Values for Elf32_Ehdr.e_flags. */ ++#define EF_CPU32 0x00810000 ++ ++/* m68k relocs. */ ++ ++#define R_68K_NONE 0 /* No reloc */ ++#define R_68K_32 1 /* Direct 32 bit */ ++#define R_68K_16 2 /* Direct 16 bit */ ++#define R_68K_8 3 /* Direct 8 bit */ ++#define R_68K_PC32 4 /* PC relative 32 bit */ ++#define R_68K_PC16 5 /* PC relative 16 bit */ ++#define R_68K_PC8 6 /* PC relative 8 bit */ ++#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ ++#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ ++#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ ++#define R_68K_GOT32O 10 /* 32 bit GOT offset */ ++#define R_68K_GOT16O 11 /* 16 bit GOT offset */ ++#define R_68K_GOT8O 12 /* 8 bit GOT offset */ ++#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ ++#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ ++#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ ++#define R_68K_PLT32O 16 /* 32 bit PLT offset */ ++#define R_68K_PLT16O 17 /* 16 bit PLT offset */ ++#define R_68K_PLT8O 18 /* 8 bit PLT offset */ ++#define R_68K_COPY 19 /* Copy symbol at runtime */ ++#define R_68K_GLOB_DAT 20 /* Create GOT entry */ ++#define R_68K_JMP_SLOT 21 /* Create PLT entry */ ++#define R_68K_RELATIVE 22 /* Adjust by program base */ ++#define R_68K_TLS_GD32 25 /* 32 bit GOT offset for GD */ ++#define R_68K_TLS_GD16 26 /* 16 bit GOT offset for GD */ ++#define R_68K_TLS_GD8 27 /* 8 bit GOT offset for GD */ ++#define R_68K_TLS_LDM32 28 /* 32 bit GOT offset for LDM */ ++#define R_68K_TLS_LDM16 29 /* 16 bit GOT offset for LDM */ ++#define R_68K_TLS_LDM8 30 /* 8 bit GOT offset for LDM */ ++#define R_68K_TLS_LDO32 31 /* 32 bit module-relative offset */ ++#define R_68K_TLS_LDO16 32 /* 16 bit module-relative offset */ ++#define R_68K_TLS_LDO8 33 /* 8 bit module-relative offset */ ++#define R_68K_TLS_IE32 34 /* 32 bit GOT offset for IE */ ++#define R_68K_TLS_IE16 35 /* 16 bit GOT offset for IE */ ++#define R_68K_TLS_IE8 36 /* 8 bit GOT offset for IE */ ++#define R_68K_TLS_LE32 37 /* 32 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_LE16 38 /* 16 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_LE8 39 /* 8 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_DTPMOD32 40 /* 32 bit module number */ ++#define R_68K_TLS_DTPREL32 41 /* 32 bit module-relative offset */ ++#define R_68K_TLS_TPREL32 42 /* 32 bit TP-relative offset */ ++/* Keep this the last entry. */ ++#define R_68K_NUM 43 ++ ++/* Intel 80386 specific definitions. */ ++ ++/* i386 relocs. */ ++ ++#define R_386_NONE 0 /* No reloc */ ++#define R_386_32 1 /* Direct 32 bit */ ++#define R_386_PC32 2 /* PC relative 32 bit */ ++#define R_386_GOT32 3 /* 32 bit GOT entry */ ++#define R_386_PLT32 4 /* 32 bit PLT address */ ++#define R_386_COPY 5 /* Copy symbol at runtime */ ++#define R_386_GLOB_DAT 6 /* Create GOT entry */ ++#define R_386_JMP_SLOT 7 /* Create PLT entry */ ++#define R_386_RELATIVE 8 /* Adjust by program base */ ++#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ ++#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ ++#define R_386_32PLT 11 ++#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ ++#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS ++ block offset */ ++#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block ++ offset */ ++#define R_386_TLS_LE 17 /* Offset relative to static TLS ++ block */ ++#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of ++ general dynamic thread local data */ ++#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of ++ local dynamic thread local data ++ in LE code */ ++#define R_386_16 20 ++#define R_386_PC16 21 ++#define R_386_8 22 ++#define R_386_PC8 23 ++#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic ++ thread local data */ ++#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ ++#define R_386_TLS_GD_CALL 26 /* Relocation for call to ++ __tls_get_addr() */ ++#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ ++#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic ++ thread local data in LE code */ ++#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ ++#define R_386_TLS_LDM_CALL 30 /* Relocation for call to ++ __tls_get_addr() in LDM code */ ++#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ ++#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ ++#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS ++ block offset */ ++#define R_386_TLS_LE_32 34 /* Negated offset relative to static ++ TLS block */ ++#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ ++#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ ++#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ ++/* 38? */ ++#define R_386_TLS_GOTDESC 39 /* GOT offset for TLS descriptor. */ ++#define R_386_TLS_DESC_CALL 40 /* Marker of call through TLS ++ descriptor for ++ relaxation. */ ++#define R_386_TLS_DESC 41 /* TLS descriptor containing ++ pointer to code and to ++ argument, returning the TLS ++ offset for the symbol. */ ++#define R_386_IRELATIVE 42 /* Adjust indirectly by program base */ ++/* Keep this the last entry. */ ++#define R_386_NUM 43 ++ ++/* SUN SPARC specific definitions. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ ++ ++/* Values for Elf64_Ehdr.e_flags. */ ++ ++#define EF_SPARCV9_MM 3 ++#define EF_SPARCV9_TSO 0 ++#define EF_SPARCV9_PSO 1 ++#define EF_SPARCV9_RMO 2 ++#define EF_SPARC_LEDATA 0x800000 /* little endian data */ ++#define EF_SPARC_EXT_MASK 0xFFFF00 ++#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ ++#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ ++#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ ++#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ ++ ++/* SPARC relocs. */ ++ ++#define R_SPARC_NONE 0 /* No reloc */ ++#define R_SPARC_8 1 /* Direct 8 bit */ ++#define R_SPARC_16 2 /* Direct 16 bit */ ++#define R_SPARC_32 3 /* Direct 32 bit */ ++#define R_SPARC_DISP8 4 /* PC relative 8 bit */ ++#define R_SPARC_DISP16 5 /* PC relative 16 bit */ ++#define R_SPARC_DISP32 6 /* PC relative 32 bit */ ++#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ ++#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ ++#define R_SPARC_HI22 9 /* High 22 bit */ ++#define R_SPARC_22 10 /* Direct 22 bit */ ++#define R_SPARC_13 11 /* Direct 13 bit */ ++#define R_SPARC_LO10 12 /* Truncated 10 bit */ ++#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ ++#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ ++#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ ++#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ ++#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ ++#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ ++#define R_SPARC_COPY 19 /* Copy symbol at runtime */ ++#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ ++#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ ++#define R_SPARC_RELATIVE 22 /* Adjust by program base */ ++#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ ++ ++/* Additional Sparc64 relocs. */ ++ ++#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ ++#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ ++#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ ++#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ ++#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ ++#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ ++#define R_SPARC_10 30 /* Direct 10 bit */ ++#define R_SPARC_11 31 /* Direct 11 bit */ ++#define R_SPARC_64 32 /* Direct 64 bit */ ++#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ ++#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ ++#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ ++#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ ++#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ ++#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ ++#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ ++#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ ++#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ ++#define R_SPARC_GLOB_JMP 42 /* was part of v9 ABI but was removed */ ++#define R_SPARC_7 43 /* Direct 7 bit */ ++#define R_SPARC_5 44 /* Direct 5 bit */ ++#define R_SPARC_6 45 /* Direct 6 bit */ ++#define R_SPARC_DISP64 46 /* PC relative 64 bit */ ++#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ ++#define R_SPARC_HIX22 48 /* High 22 bit complemented */ ++#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ ++#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ ++#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ ++#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ ++#define R_SPARC_REGISTER 53 /* Global register usage */ ++#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ ++#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ ++#define R_SPARC_TLS_GD_HI22 56 ++#define R_SPARC_TLS_GD_LO10 57 ++#define R_SPARC_TLS_GD_ADD 58 ++#define R_SPARC_TLS_GD_CALL 59 ++#define R_SPARC_TLS_LDM_HI22 60 ++#define R_SPARC_TLS_LDM_LO10 61 ++#define R_SPARC_TLS_LDM_ADD 62 ++#define R_SPARC_TLS_LDM_CALL 63 ++#define R_SPARC_TLS_LDO_HIX22 64 ++#define R_SPARC_TLS_LDO_LOX10 65 ++#define R_SPARC_TLS_LDO_ADD 66 ++#define R_SPARC_TLS_IE_HI22 67 ++#define R_SPARC_TLS_IE_LO10 68 ++#define R_SPARC_TLS_IE_LD 69 ++#define R_SPARC_TLS_IE_LDX 70 ++#define R_SPARC_TLS_IE_ADD 71 ++#define R_SPARC_TLS_LE_HIX22 72 ++#define R_SPARC_TLS_LE_LOX10 73 ++#define R_SPARC_TLS_DTPMOD32 74 ++#define R_SPARC_TLS_DTPMOD64 75 ++#define R_SPARC_TLS_DTPOFF32 76 ++#define R_SPARC_TLS_DTPOFF64 77 ++#define R_SPARC_TLS_TPOFF32 78 ++#define R_SPARC_TLS_TPOFF64 79 ++#define R_SPARC_GOTDATA_HIX22 80 ++#define R_SPARC_GOTDATA_LOX10 81 ++#define R_SPARC_GOTDATA_OP_HIX22 82 ++#define R_SPARC_GOTDATA_OP_LOX10 83 ++#define R_SPARC_GOTDATA_OP 84 ++#define R_SPARC_H34 85 ++#define R_SPARC_SIZE32 86 ++#define R_SPARC_SIZE64 87 ++#define R_SPARC_WDISP10 88 ++#define R_SPARC_JMP_IREL 248 ++#define R_SPARC_IRELATIVE 249 ++#define R_SPARC_GNU_VTINHERIT 250 ++#define R_SPARC_GNU_VTENTRY 251 ++#define R_SPARC_REV32 252 ++/* Keep this the last entry. */ ++#define R_SPARC_NUM 253 ++ ++/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ ++ ++#define DT_SPARC_REGISTER 0x70000001 ++#define DT_SPARC_NUM 2 ++ ++/* MIPS R3000 specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ ++#define EF_MIPS_PIC 2 /* Contains PIC code */ ++#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ ++#define EF_MIPS_XGOT 8 ++#define EF_MIPS_64BIT_WHIRL 16 ++#define EF_MIPS_ABI2 32 ++#define EF_MIPS_ABI_ON32 64 ++#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ ++ ++/* Legal values for MIPS architecture level. */ ++ ++#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* The following are non-official names and should not be used. */ ++ ++#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* Special section indices. */ ++ ++#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ ++#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ ++#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ ++#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ ++#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ ++#define SHT_MIPS_MSYM 0x70000001 ++#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ ++#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ ++#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ ++#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ ++#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ ++#define SHT_MIPS_PACKAGE 0x70000007 ++#define SHT_MIPS_PACKSYM 0x70000008 ++#define SHT_MIPS_RELD 0x70000009 ++#define SHT_MIPS_IFACE 0x7000000b ++#define SHT_MIPS_CONTENT 0x7000000c ++#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ ++#define SHT_MIPS_SHDR 0x70000010 ++#define SHT_MIPS_FDESC 0x70000011 ++#define SHT_MIPS_EXTSYM 0x70000012 ++#define SHT_MIPS_DENSE 0x70000013 ++#define SHT_MIPS_PDESC 0x70000014 ++#define SHT_MIPS_LOCSYM 0x70000015 ++#define SHT_MIPS_AUXSYM 0x70000016 ++#define SHT_MIPS_OPTSYM 0x70000017 ++#define SHT_MIPS_LOCSTR 0x70000018 ++#define SHT_MIPS_LINE 0x70000019 ++#define SHT_MIPS_RFDESC 0x7000001a ++#define SHT_MIPS_DELTASYM 0x7000001b ++#define SHT_MIPS_DELTAINST 0x7000001c ++#define SHT_MIPS_DELTACLASS 0x7000001d ++#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ ++#define SHT_MIPS_DELTADECL 0x7000001f ++#define SHT_MIPS_SYMBOL_LIB 0x70000020 ++#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ ++#define SHT_MIPS_TRANSLATE 0x70000022 ++#define SHT_MIPS_PIXIE 0x70000023 ++#define SHT_MIPS_XLATE 0x70000024 ++#define SHT_MIPS_XLATE_DEBUG 0x70000025 ++#define SHT_MIPS_WHIRL 0x70000026 ++#define SHT_MIPS_EH_REGION 0x70000027 ++#define SHT_MIPS_XLATE_OLD 0x70000028 ++#define SHT_MIPS_PDR_EXCEPTION 0x70000029 ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ ++#define SHF_MIPS_MERGE 0x20000000 ++#define SHF_MIPS_ADDR 0x40000000 ++#define SHF_MIPS_STRINGS 0x80000000 ++#define SHF_MIPS_NOSTRIP 0x08000000 ++#define SHF_MIPS_LOCAL 0x04000000 ++#define SHF_MIPS_NAMES 0x02000000 ++#define SHF_MIPS_NODUPE 0x01000000 ++ ++ ++/* Symbol tables. */ ++ ++/* MIPS specific values for `st_other'. */ ++#define STO_MIPS_DEFAULT 0x0 ++#define STO_MIPS_INTERNAL 0x1 ++#define STO_MIPS_HIDDEN 0x2 ++#define STO_MIPS_PROTECTED 0x3 ++#define STO_MIPS_PLT 0x8 ++#define STO_MIPS_SC_ALIGN_UNUSED 0xff ++ ++/* MIPS specific values for `st_info'. */ ++#define STB_MIPS_SPLIT_COMMON 13 ++ ++/* Entries found in sections of type SHT_MIPS_GPTAB. */ ++ ++typedef union ++{ ++ struct ++ { ++ Elf32_Word gt_current_g_value; /* -G value used for compilation */ ++ Elf32_Word gt_unused; /* Not used */ ++ } gt_header; /* First entry in section */ ++ struct ++ { ++ Elf32_Word gt_g_value; /* If this value were used for -G */ ++ Elf32_Word gt_bytes; /* This many bytes would be used */ ++ } gt_entry; /* Subsequent entries in section */ ++} Elf32_gptab; ++ ++/* Entry found in sections of type SHT_MIPS_REGINFO. */ ++ ++typedef struct ++{ ++ Elf32_Word ri_gprmask; /* General registers used */ ++ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ ++ Elf32_Sword ri_gp_value; /* $gp register value */ ++} Elf32_RegInfo; ++ ++/* Entries found in sections of type SHT_MIPS_OPTIONS. */ ++ ++typedef struct ++{ ++ unsigned char kind; /* Determines interpretation of the ++ variable part of descriptor. */ ++ unsigned char size; /* Size of descriptor, including header. */ ++ Elf32_Section section; /* Section header index of section affected, ++ 0 for global options. */ ++ Elf32_Word info; /* Kind-specific information. */ ++} Elf_Options; ++ ++/* Values for `kind' field in Elf_Options. */ ++ ++#define ODK_NULL 0 /* Undefined. */ ++#define ODK_REGINFO 1 /* Register usage information. */ ++#define ODK_EXCEPTIONS 2 /* Exception processing options. */ ++#define ODK_PAD 3 /* Section padding options. */ ++#define ODK_HWPATCH 4 /* Hardware workarounds performed */ ++#define ODK_FILL 5 /* record the fill value used by the linker. */ ++#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ ++#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ ++#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ ++ ++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ ++ ++#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ ++#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ ++#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ ++#define OEX_SMM 0x20000 /* Force sequential memory mode? */ ++#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ ++#define OEX_PRECISEFP OEX_FPDBUG ++#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ ++ ++#define OEX_FPU_INVAL 0x10 ++#define OEX_FPU_DIV0 0x08 ++#define OEX_FPU_OFLO 0x04 ++#define OEX_FPU_UFLO 0x02 ++#define OEX_FPU_INEX 0x01 ++ ++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ ++ ++#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ ++#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ ++#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ ++#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ ++ ++#define OPAD_PREFIX 0x1 ++#define OPAD_POSTFIX 0x2 ++#define OPAD_SYMBOL 0x4 ++ ++/* Entry found in `.options' section. */ ++ ++typedef struct ++{ ++ Elf32_Word hwp_flags1; /* Extra flags. */ ++ Elf32_Word hwp_flags2; /* Extra flags. */ ++} Elf_Options_Hw; ++ ++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ ++ ++#define OHWA0_R4KEOP_CHECKED 0x00000001 ++#define OHWA1_R4KEOP_CLEAN 0x00000002 ++ ++/* MIPS relocs. */ ++ ++#define R_MIPS_NONE 0 /* No reloc */ ++#define R_MIPS_16 1 /* Direct 16 bit */ ++#define R_MIPS_32 2 /* Direct 32 bit */ ++#define R_MIPS_REL32 3 /* PC relative 32 bit */ ++#define R_MIPS_26 4 /* Direct 26 bit shifted */ ++#define R_MIPS_HI16 5 /* High 16 bit */ ++#define R_MIPS_LO16 6 /* Low 16 bit */ ++#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ ++#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ ++#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ ++#define R_MIPS_PC16 10 /* PC relative 16 bit */ ++#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ ++#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ ++ ++#define R_MIPS_SHIFT5 16 ++#define R_MIPS_SHIFT6 17 ++#define R_MIPS_64 18 ++#define R_MIPS_GOT_DISP 19 ++#define R_MIPS_GOT_PAGE 20 ++#define R_MIPS_GOT_OFST 21 ++#define R_MIPS_GOT_HI16 22 ++#define R_MIPS_GOT_LO16 23 ++#define R_MIPS_SUB 24 ++#define R_MIPS_INSERT_A 25 ++#define R_MIPS_INSERT_B 26 ++#define R_MIPS_DELETE 27 ++#define R_MIPS_HIGHER 28 ++#define R_MIPS_HIGHEST 29 ++#define R_MIPS_CALL_HI16 30 ++#define R_MIPS_CALL_LO16 31 ++#define R_MIPS_SCN_DISP 32 ++#define R_MIPS_REL16 33 ++#define R_MIPS_ADD_IMMEDIATE 34 ++#define R_MIPS_PJUMP 35 ++#define R_MIPS_RELGOT 36 ++#define R_MIPS_JALR 37 ++#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ ++#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ ++#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ ++#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ ++#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ ++#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ ++#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ ++#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ ++#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ ++#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ ++#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ ++#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ ++#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ ++#define R_MIPS_GLOB_DAT 51 ++#define R_MIPS_COPY 126 ++#define R_MIPS_JUMP_SLOT 127 ++/* Keep this the last entry. */ ++#define R_MIPS_NUM 128 ++ ++/* Legal values for p_type field of Elf32_Phdr. */ ++ ++#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ ++#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ ++#define PT_MIPS_OPTIONS 0x70000002 ++ ++/* Special program header types. */ ++ ++#define PF_MIPS_LOCAL 0x10000000 ++ ++/* Legal values for d_tag field of Elf32_Dyn. */ ++ ++#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ ++#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ ++#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ ++#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ ++#define DT_MIPS_FLAGS 0x70000005 /* Flags */ ++#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ ++#define DT_MIPS_MSYM 0x70000007 ++#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ ++#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ ++#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ ++#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ ++#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ ++#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ ++#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ ++#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ ++#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ ++#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ ++#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ ++#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in ++ DT_MIPS_DELTA_CLASS. */ ++#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ ++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in ++ DT_MIPS_DELTA_INSTANCE. */ ++#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ ++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in ++ DT_MIPS_DELTA_RELOC. */ ++#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta ++ relocations refer to. */ ++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in ++ DT_MIPS_DELTA_SYM. */ ++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the ++ class declaration. */ ++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in ++ DT_MIPS_DELTA_CLASSSYM. */ ++#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ ++#define DT_MIPS_PIXIE_INIT 0x70000023 ++#define DT_MIPS_SYMBOL_LIB 0x70000024 ++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 ++#define DT_MIPS_LOCAL_GOTIDX 0x70000026 ++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 ++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 ++#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ ++#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ ++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b ++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ ++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve ++ function stored in GOT. */ ++#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added ++ by rld on dlopen() calls. */ ++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ ++#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ ++#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ ++/* The address of .got.plt in an executable using the new non-PIC ABI. */ ++#define DT_MIPS_PLTGOT 0x70000032 ++/* The base of the PLT in an executable using the new non-PIC ABI if that ++ PLT is writable. For a non-writable PLT, this is omitted or has a zero ++ value. */ ++#define DT_MIPS_RWPLT 0x70000034 ++#define DT_MIPS_NUM 0x35 ++ ++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ ++ ++#define RHF_NONE 0 /* No flags */ ++#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ ++#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ ++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ ++#define RHF_NO_MOVE (1 << 3) ++#define RHF_SGI_ONLY (1 << 4) ++#define RHF_GUARANTEE_INIT (1 << 5) ++#define RHF_DELTA_C_PLUS_PLUS (1 << 6) ++#define RHF_GUARANTEE_START_INIT (1 << 7) ++#define RHF_PIXIE (1 << 8) ++#define RHF_DEFAULT_DELAY_LOAD (1 << 9) ++#define RHF_REQUICKSTART (1 << 10) ++#define RHF_REQUICKSTARTED (1 << 11) ++#define RHF_CORD (1 << 12) ++#define RHF_NO_UNRES_UNDEF (1 << 13) ++#define RHF_RLD_ORDER_SAFE (1 << 14) ++ ++/* Entries found in sections of type SHT_MIPS_LIBLIST. */ ++ ++typedef struct ++{ ++ Elf32_Word l_name; /* Name (string table index) */ ++ Elf32_Word l_time_stamp; /* Timestamp */ ++ Elf32_Word l_checksum; /* Checksum */ ++ Elf32_Word l_version; /* Interface version */ ++ Elf32_Word l_flags; /* Flags */ ++} Elf32_Lib; ++ ++typedef struct ++{ ++ Elf64_Word l_name; /* Name (string table index) */ ++ Elf64_Word l_time_stamp; /* Timestamp */ ++ Elf64_Word l_checksum; /* Checksum */ ++ Elf64_Word l_version; /* Interface version */ ++ Elf64_Word l_flags; /* Flags */ ++} Elf64_Lib; ++ ++ ++/* Legal values for l_flags. */ ++ ++#define LL_NONE 0 ++#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ ++#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ ++#define LL_REQUIRE_MINOR (1 << 2) ++#define LL_EXPORTS (1 << 3) ++#define LL_DELAY_LOAD (1 << 4) ++#define LL_DELTA (1 << 5) ++ ++/* Entries found in sections of type SHT_MIPS_CONFLICT. */ ++ ++typedef Elf32_Addr Elf32_Conflict; ++ ++ ++/* HPPA specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ ++#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ ++#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ ++#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ ++#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch ++ prediction. */ ++#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ ++#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ ++ ++/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ ++ ++#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ ++#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ ++#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ ++ ++/* Additional section indeces. */ ++ ++#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared ++ symbols in ANSI C. */ ++#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ ++#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ ++#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ ++#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ ++#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ ++ ++#define STT_HP_OPAQUE (STT_LOOS + 0x1) ++#define STT_HP_STUB (STT_LOOS + 0x2) ++ ++/* HPPA relocs. */ ++ ++#define R_PARISC_NONE 0 /* No reloc. */ ++#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ ++#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ ++#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ ++#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ ++#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ ++#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ ++#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ ++#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ ++#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ ++#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ ++#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ ++#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ ++#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ ++#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ ++#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ ++#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ ++#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ ++#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ ++#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ ++#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ ++#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ ++#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ ++#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ ++#define R_PARISC_FPTR64 64 /* 64 bits function address. */ ++#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ ++#define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ ++#define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ ++#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ ++#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ ++#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ ++#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ ++#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ ++#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ ++#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ ++#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ ++#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ ++#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ ++#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ ++#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ ++#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ ++#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ ++#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LORESERVE 128 ++#define R_PARISC_COPY 128 /* Copy relocation. */ ++#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ ++#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ ++#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ ++#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ ++#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ ++#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ ++#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ ++#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ ++#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_GNU_VTENTRY 232 ++#define R_PARISC_GNU_VTINHERIT 233 ++#define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ ++#define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ ++#define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ ++#define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ ++#define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ ++#define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ ++#define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ ++#define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ ++#define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ ++#define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ ++#define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ ++#define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ ++#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L ++#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R ++#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L ++#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R ++#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 ++#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 ++#define R_PARISC_HIRESERVE 255 ++ ++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PT_HP_TLS (PT_LOOS + 0x0) ++#define PT_HP_CORE_NONE (PT_LOOS + 0x1) ++#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) ++#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) ++#define PT_HP_CORE_COMM (PT_LOOS + 0x4) ++#define PT_HP_CORE_PROC (PT_LOOS + 0x5) ++#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) ++#define PT_HP_CORE_STACK (PT_LOOS + 0x7) ++#define PT_HP_CORE_SHM (PT_LOOS + 0x8) ++#define PT_HP_CORE_MMF (PT_LOOS + 0x9) ++#define PT_HP_PARALLEL (PT_LOOS + 0x10) ++#define PT_HP_FASTBIND (PT_LOOS + 0x11) ++#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) ++#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) ++#define PT_HP_STACK (PT_LOOS + 0x14) ++ ++#define PT_PARISC_ARCHEXT 0x70000000 ++#define PT_PARISC_UNWIND 0x70000001 ++ ++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PF_PARISC_SBP 0x08000000 ++ ++#define PF_HP_PAGE_SIZE 0x00100000 ++#define PF_HP_FAR_SHARED 0x00200000 ++#define PF_HP_NEAR_SHARED 0x00400000 ++#define PF_HP_CODE 0x01000000 ++#define PF_HP_MODIFY 0x02000000 ++#define PF_HP_LAZYSWAP 0x04000000 ++#define PF_HP_SBP 0x08000000 ++ ++ ++/* Alpha specific definitions. */ ++ ++/* Legal values for e_flags field of Elf64_Ehdr. */ ++ ++#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ ++#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ ++ ++/* Legal values for sh_type field of Elf64_Shdr. */ ++ ++/* These two are primerily concerned with ECOFF debugging info. */ ++#define SHT_ALPHA_DEBUG 0x70000001 ++#define SHT_ALPHA_REGINFO 0x70000002 ++ ++/* Legal values for sh_flags field of Elf64_Shdr. */ ++ ++#define SHF_ALPHA_GPREL 0x10000000 ++ ++/* Legal values for st_other field of Elf64_Sym. */ ++#define STO_ALPHA_NOPV 0x80 /* No PV required. */ ++#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ ++ ++/* Alpha relocs. */ ++ ++#define R_ALPHA_NONE 0 /* No reloc */ ++#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ ++#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ ++#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ ++#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ ++#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ ++#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ ++#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ ++#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ ++#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ ++#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ ++#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ ++#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ ++#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ ++#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ ++#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ ++#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ ++#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ ++#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ ++#define R_ALPHA_TLS_GD_HI 28 ++#define R_ALPHA_TLSGD 29 ++#define R_ALPHA_TLS_LDM 30 ++#define R_ALPHA_DTPMOD64 31 ++#define R_ALPHA_GOTDTPREL 32 ++#define R_ALPHA_DTPREL64 33 ++#define R_ALPHA_DTPRELHI 34 ++#define R_ALPHA_DTPRELLO 35 ++#define R_ALPHA_DTPREL16 36 ++#define R_ALPHA_GOTTPREL 37 ++#define R_ALPHA_TPREL64 38 ++#define R_ALPHA_TPRELHI 39 ++#define R_ALPHA_TPRELLO 40 ++#define R_ALPHA_TPREL16 41 ++/* Keep this the last entry. */ ++#define R_ALPHA_NUM 46 ++ ++/* Magic values of the LITUSE relocation addend. */ ++#define LITUSE_ALPHA_ADDR 0 ++#define LITUSE_ALPHA_BASE 1 ++#define LITUSE_ALPHA_BYTOFF 2 ++#define LITUSE_ALPHA_JSR 3 ++#define LITUSE_ALPHA_TLS_GD 4 ++#define LITUSE_ALPHA_TLS_LDM 5 ++ ++/* Legal values for d_tag of Elf64_Dyn. */ ++#define DT_ALPHA_PLTRO (DT_LOPROC + 0) ++#define DT_ALPHA_NUM 1 ++ ++/* PowerPC specific declarations */ ++ ++/* Values for Elf32/64_Ehdr.e_flags. */ ++#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ ++ ++/* Cygnus local bits below */ ++#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ ++#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib ++ flag */ ++ ++/* PowerPC relocations defined by the ABIs */ ++#define R_PPC_NONE 0 ++#define R_PPC_ADDR32 1 /* 32bit absolute address */ ++#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ ++#define R_PPC_ADDR16 3 /* 16bit absolute address */ ++#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ ++#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ ++#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ ++#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ ++#define R_PPC_ADDR14_BRTAKEN 8 ++#define R_PPC_ADDR14_BRNTAKEN 9 ++#define R_PPC_REL24 10 /* PC relative 26 bit */ ++#define R_PPC_REL14 11 /* PC relative 16 bit */ ++#define R_PPC_REL14_BRTAKEN 12 ++#define R_PPC_REL14_BRNTAKEN 13 ++#define R_PPC_GOT16 14 ++#define R_PPC_GOT16_LO 15 ++#define R_PPC_GOT16_HI 16 ++#define R_PPC_GOT16_HA 17 ++#define R_PPC_PLTREL24 18 ++#define R_PPC_COPY 19 ++#define R_PPC_GLOB_DAT 20 ++#define R_PPC_JMP_SLOT 21 ++#define R_PPC_RELATIVE 22 ++#define R_PPC_LOCAL24PC 23 ++#define R_PPC_UADDR32 24 ++#define R_PPC_UADDR16 25 ++#define R_PPC_REL32 26 ++#define R_PPC_PLT32 27 ++#define R_PPC_PLTREL32 28 ++#define R_PPC_PLT16_LO 29 ++#define R_PPC_PLT16_HI 30 ++#define R_PPC_PLT16_HA 31 ++#define R_PPC_SDAREL16 32 ++#define R_PPC_SECTOFF 33 ++#define R_PPC_SECTOFF_LO 34 ++#define R_PPC_SECTOFF_HI 35 ++#define R_PPC_SECTOFF_HA 36 ++ ++/* PowerPC relocations defined for the TLS access ABI. */ ++#define R_PPC_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ ++#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ ++#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ ++#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ ++#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ ++#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ ++#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ ++#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ ++#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ ++ ++/* The remaining relocs are from the Embedded ELF ABI, and are not ++ in the SVR4 ELF ABI. */ ++#define R_PPC_EMB_NADDR32 101 ++#define R_PPC_EMB_NADDR16 102 ++#define R_PPC_EMB_NADDR16_LO 103 ++#define R_PPC_EMB_NADDR16_HI 104 ++#define R_PPC_EMB_NADDR16_HA 105 ++#define R_PPC_EMB_SDAI16 106 ++#define R_PPC_EMB_SDA2I16 107 ++#define R_PPC_EMB_SDA2REL 108 ++#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ ++#define R_PPC_EMB_MRKREF 110 ++#define R_PPC_EMB_RELSEC16 111 ++#define R_PPC_EMB_RELST_LO 112 ++#define R_PPC_EMB_RELST_HI 113 ++#define R_PPC_EMB_RELST_HA 114 ++#define R_PPC_EMB_BIT_FLD 115 ++#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ ++ ++/* Diab tool relocations. */ ++#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ ++#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ ++#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ ++#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ ++#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ ++#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ ++ ++/* GNU extension to support local ifunc. */ ++#define R_PPC_IRELATIVE 248 ++ ++/* GNU relocs used in PIC code sequences. */ ++#define R_PPC_REL16 249 /* half16 (sym+add-.) */ ++#define R_PPC_REL16_LO 250 /* half16 (sym+add-.)@l */ ++#define R_PPC_REL16_HI 251 /* half16 (sym+add-.)@h */ ++#define R_PPC_REL16_HA 252 /* half16 (sym+add-.)@ha */ ++ ++/* This is a phony reloc to handle any old fashioned TOC16 references ++ that may still be in object files. */ ++#define R_PPC_TOC16 255 ++ ++/* PowerPC specific values for the Dyn d_tag field. */ ++#define DT_PPC_GOT (DT_LOPROC + 0) ++#define DT_PPC_NUM 1 ++ ++/* PowerPC64 relocations defined by the ABIs */ ++#define R_PPC64_NONE R_PPC_NONE ++#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ ++#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ ++#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ ++#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ ++#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ ++#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ ++#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ ++#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN ++#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN ++#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ ++#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ ++#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN ++#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN ++#define R_PPC64_GOT16 R_PPC_GOT16 ++#define R_PPC64_GOT16_LO R_PPC_GOT16_LO ++#define R_PPC64_GOT16_HI R_PPC_GOT16_HI ++#define R_PPC64_GOT16_HA R_PPC_GOT16_HA ++ ++#define R_PPC64_COPY R_PPC_COPY ++#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT ++#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT ++#define R_PPC64_RELATIVE R_PPC_RELATIVE ++ ++#define R_PPC64_UADDR32 R_PPC_UADDR32 ++#define R_PPC64_UADDR16 R_PPC_UADDR16 ++#define R_PPC64_REL32 R_PPC_REL32 ++#define R_PPC64_PLT32 R_PPC_PLT32 ++#define R_PPC64_PLTREL32 R_PPC_PLTREL32 ++#define R_PPC64_PLT16_LO R_PPC_PLT16_LO ++#define R_PPC64_PLT16_HI R_PPC_PLT16_HI ++#define R_PPC64_PLT16_HA R_PPC_PLT16_HA ++ ++#define R_PPC64_SECTOFF R_PPC_SECTOFF ++#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO ++#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ++#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA ++#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ ++#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ ++#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ ++#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ ++#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ ++#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ ++#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ ++#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ ++#define R_PPC64_PLT64 45 /* doubleword64 L + A */ ++#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ ++#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ ++#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ ++#define R_PPC64_TOC 51 /* doubleword64 .TOC */ ++#define R_PPC64_PLTGOT16 52 /* half16* M + A */ ++#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ ++#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ ++#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ ++ ++#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ ++#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ ++#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ ++#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ ++#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ ++#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ ++#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ ++#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ ++#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ ++#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ ++#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ ++ ++/* PowerPC64 relocations defined for the TLS access ABI. */ ++#define R_PPC64_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ ++#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ ++#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ ++#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ ++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ ++#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ ++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ ++#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ ++#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ ++#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ ++#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ ++#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ ++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ ++#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ ++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ ++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ ++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ ++ ++/* GNU extension to support local ifunc. */ ++#define R_PPC64_JMP_IREL 247 ++#define R_PPC64_IRELATIVE 248 ++#define R_PPC64_REL16 249 /* half16 (sym+add-.) */ ++#define R_PPC64_REL16_LO 250 /* half16 (sym+add-.)@l */ ++#define R_PPC64_REL16_HI 251 /* half16 (sym+add-.)@h */ ++#define R_PPC64_REL16_HA 252 /* half16 (sym+add-.)@ha */ ++ ++/* PowerPC64 specific values for the Dyn d_tag field. */ ++#define DT_PPC64_GLINK (DT_LOPROC + 0) ++#define DT_PPC64_OPD (DT_LOPROC + 1) ++#define DT_PPC64_OPDSZ (DT_LOPROC + 2) ++#define DT_PPC64_NUM 3 ++ ++ ++/* ARM specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_ARM_RELEXEC 0x01 ++#define EF_ARM_HASENTRY 0x02 ++#define EF_ARM_INTERWORK 0x04 ++#define EF_ARM_APCS_26 0x08 ++#define EF_ARM_APCS_FLOAT 0x10 ++#define EF_ARM_PIC 0x20 ++#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ ++#define EF_ARM_NEW_ABI 0x80 ++#define EF_ARM_OLD_ABI 0x100 ++#define EF_ARM_SOFT_FLOAT 0x200 ++#define EF_ARM_VFP_FLOAT 0x400 ++#define EF_ARM_MAVERICK_FLOAT 0x800 ++ ++ ++/* Other constants defined in the ARM ELF spec. version B-01. */ ++/* NB. These conflict with values defined above. */ ++#define EF_ARM_SYMSARESORTED 0x04 ++#define EF_ARM_DYNSYMSUSESEGIDX 0x08 ++#define EF_ARM_MAPSYMSFIRST 0x10 ++#define EF_ARM_EABIMASK 0XFF000000 ++ ++/* Constants defined in AAELF. */ ++#define EF_ARM_BE8 0x00800000 ++#define EF_ARM_LE8 0x00400000 ++ ++#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) ++#define EF_ARM_EABI_UNKNOWN 0x00000000 ++#define EF_ARM_EABI_VER1 0x01000000 ++#define EF_ARM_EABI_VER2 0x02000000 ++#define EF_ARM_EABI_VER3 0x03000000 ++#define EF_ARM_EABI_VER4 0x04000000 ++#define EF_ARM_EABI_VER5 0x05000000 ++ ++/* Additional symbol types for Thumb. */ ++#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ ++#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ ++ ++/* ARM-specific values for sh_flags */ ++#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ ++#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined ++ in the input to a link step. */ ++ ++/* ARM-specific program header flags */ ++#define PF_ARM_SB 0x10000000 /* Segment contains the location ++ addressed by the static base. */ ++#define PF_ARM_PI 0x20000000 /* Position-independent segment. */ ++#define PF_ARM_ABS 0x40000000 /* Absolute segment. */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */ ++#define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */ ++#define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */ ++ ++ ++/* ARM relocs. */ ++ ++#define R_ARM_NONE 0 /* No reloc */ ++#define R_ARM_PC24 1 /* PC relative 26 bit branch */ ++#define R_ARM_ABS32 2 /* Direct 32 bit */ ++#define R_ARM_REL32 3 /* PC relative 32 bit */ ++#define R_ARM_PC13 4 ++#define R_ARM_ABS16 5 /* Direct 16 bit */ ++#define R_ARM_ABS12 6 /* Direct 12 bit */ ++#define R_ARM_THM_ABS5 7 ++#define R_ARM_ABS8 8 /* Direct 8 bit */ ++#define R_ARM_SBREL32 9 ++#define R_ARM_THM_PC22 10 ++#define R_ARM_THM_PC8 11 ++#define R_ARM_AMP_VCALL9 12 ++#define R_ARM_SWI24 13 /* Obsolete static relocation. */ ++#define R_ARM_TLS_DESC 13 /* Dynamic relocation. */ ++#define R_ARM_THM_SWI8 14 ++#define R_ARM_XPC25 15 ++#define R_ARM_THM_XPC22 16 ++#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ ++#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ ++#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ ++#define R_ARM_COPY 20 /* Copy symbol at runtime */ ++#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ ++#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ ++#define R_ARM_RELATIVE 23 /* Adjust by program base */ ++#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ ++#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ ++#define R_ARM_GOT32 26 /* 32 bit GOT entry */ ++#define R_ARM_PLT32 27 /* 32 bit PLT address */ ++#define R_ARM_ALU_PCREL_7_0 32 ++#define R_ARM_ALU_PCREL_15_8 33 ++#define R_ARM_ALU_PCREL_23_15 34 ++#define R_ARM_LDR_SBREL_11_0 35 ++#define R_ARM_ALU_SBREL_19_12 36 ++#define R_ARM_ALU_SBREL_27_20 37 ++#define R_ARM_TLS_GOTDESC 90 ++#define R_ARM_TLS_CALL 91 ++#define R_ARM_TLS_DESCSEQ 92 ++#define R_ARM_THM_TLS_CALL 93 ++#define R_ARM_GNU_VTENTRY 100 ++#define R_ARM_GNU_VTINHERIT 101 ++#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ ++#define R_ARM_THM_PC9 103 /* thumb conditional branch */ ++#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic ++ thread local data */ ++#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic ++ thread local data */ ++#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS ++ block */ ++#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of ++ static TLS block offset */ ++#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static ++ TLS block */ ++#define R_ARM_THM_TLS_DESCSEQ 129 ++#define R_ARM_IRELATIVE 160 ++#define R_ARM_RXPC25 249 ++#define R_ARM_RSBREL32 250 ++#define R_ARM_THM_RPC22 251 ++#define R_ARM_RREL32 252 ++#define R_ARM_RABS22 253 ++#define R_ARM_RPC24 254 ++#define R_ARM_RBASE 255 ++/* Keep this the last entry. */ ++#define R_ARM_NUM 256 ++ ++/* IA-64 specific declarations. */ ++ ++/* Processor specific flags for the Ehdr e_flags field. */ ++#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ ++#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ ++#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ ++#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ ++#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) ++#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) ++#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) ++ ++/* Processor specific flags for the Phdr p_flags field. */ ++#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ ++#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ ++ ++/* Processor specific flags for the Shdr sh_flags field. */ ++#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ ++#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Dyn d_tag field. */ ++#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) ++#define DT_IA_64_NUM 1 ++ ++/* IA-64 relocations. */ ++#define R_IA64_NONE 0x00 /* none */ ++#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ ++#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ ++#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ ++#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ ++#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ ++#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ ++#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ ++#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ ++#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ ++#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ ++#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ ++#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ ++#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ ++#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ ++#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ ++#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ ++#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ ++#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ ++#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ ++#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ ++#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ ++#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ ++#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ ++#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ ++#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ ++#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ ++#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ ++#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ ++#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ ++#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ ++#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ ++#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ ++#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ ++#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ ++#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ ++#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ ++#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ ++#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ ++#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ ++#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ ++#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ ++#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ ++#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ ++#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ ++#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ ++#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ ++#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ ++#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ ++#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ ++#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ ++#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ ++#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ ++#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ ++#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ ++#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ ++#define R_IA64_COPY 0x84 /* copy relocation */ ++#define R_IA64_SUB 0x85 /* Addend and symbol difference */ ++#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ ++#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ ++#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ ++#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ ++#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ ++#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ ++#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ ++#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ ++#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ ++#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ ++#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ ++#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ ++#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ ++#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ ++#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ ++#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ ++ ++/* SH specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_SH_MACH_MASK 0x1f ++#define EF_SH_UNKNOWN 0x0 ++#define EF_SH1 0x1 ++#define EF_SH2 0x2 ++#define EF_SH3 0x3 ++#define EF_SH_DSP 0x4 ++#define EF_SH3_DSP 0x5 ++#define EF_SH4AL_DSP 0x6 ++#define EF_SH3E 0x8 ++#define EF_SH4 0x9 ++#define EF_SH2E 0xb ++#define EF_SH4A 0xc ++#define EF_SH2A 0xd ++#define EF_SH4_NOFPU 0x10 ++#define EF_SH4A_NOFPU 0x11 ++#define EF_SH4_NOMMU_NOFPU 0x12 ++#define EF_SH2A_NOFPU 0x13 ++#define EF_SH3_NOMMU 0x14 ++#define EF_SH2A_SH4_NOFPU 0x15 ++#define EF_SH2A_SH3_NOFPU 0x16 ++#define EF_SH2A_SH4 0x17 ++#define EF_SH2A_SH3E 0x18 ++ ++/* SH relocs. */ ++#define R_SH_NONE 0 ++#define R_SH_DIR32 1 ++#define R_SH_REL32 2 ++#define R_SH_DIR8WPN 3 ++#define R_SH_IND12W 4 ++#define R_SH_DIR8WPL 5 ++#define R_SH_DIR8WPZ 6 ++#define R_SH_DIR8BP 7 ++#define R_SH_DIR8W 8 ++#define R_SH_DIR8L 9 ++#define R_SH_SWITCH16 25 ++#define R_SH_SWITCH32 26 ++#define R_SH_USES 27 ++#define R_SH_COUNT 28 ++#define R_SH_ALIGN 29 ++#define R_SH_CODE 30 ++#define R_SH_DATA 31 ++#define R_SH_LABEL 32 ++#define R_SH_SWITCH8 33 ++#define R_SH_GNU_VTINHERIT 34 ++#define R_SH_GNU_VTENTRY 35 ++#define R_SH_TLS_GD_32 144 ++#define R_SH_TLS_LD_32 145 ++#define R_SH_TLS_LDO_32 146 ++#define R_SH_TLS_IE_32 147 ++#define R_SH_TLS_LE_32 148 ++#define R_SH_TLS_DTPMOD32 149 ++#define R_SH_TLS_DTPOFF32 150 ++#define R_SH_TLS_TPOFF32 151 ++#define R_SH_GOT32 160 ++#define R_SH_PLT32 161 ++#define R_SH_COPY 162 ++#define R_SH_GLOB_DAT 163 ++#define R_SH_JMP_SLOT 164 ++#define R_SH_RELATIVE 165 ++#define R_SH_GOTOFF 166 ++#define R_SH_GOTPC 167 ++/* Keep this the last entry. */ ++#define R_SH_NUM 256 ++ ++/* S/390 specific definitions. */ ++ ++/* Valid values for the e_flags field. */ ++ ++#define EF_S390_HIGH_GPRS 0x00000001 /* High GPRs kernel facility needed. */ ++ ++/* Additional s390 relocs */ ++ ++#define R_390_NONE 0 /* No reloc. */ ++#define R_390_8 1 /* Direct 8 bit. */ ++#define R_390_12 2 /* Direct 12 bit. */ ++#define R_390_16 3 /* Direct 16 bit. */ ++#define R_390_32 4 /* Direct 32 bit. */ ++#define R_390_PC32 5 /* PC relative 32 bit. */ ++#define R_390_GOT12 6 /* 12 bit GOT offset. */ ++#define R_390_GOT32 7 /* 32 bit GOT offset. */ ++#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ ++#define R_390_COPY 9 /* Copy symbol at runtime. */ ++#define R_390_GLOB_DAT 10 /* Create GOT entry. */ ++#define R_390_JMP_SLOT 11 /* Create PLT entry. */ ++#define R_390_RELATIVE 12 /* Adjust by program base. */ ++#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ ++#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ ++#define R_390_GOT16 15 /* 16 bit GOT offset. */ ++#define R_390_PC16 16 /* PC relative 16 bit. */ ++#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ ++#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ ++#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ ++#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ ++#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ ++#define R_390_64 22 /* Direct 64 bit. */ ++#define R_390_PC64 23 /* PC relative 64 bit. */ ++#define R_390_GOT64 24 /* 64 bit GOT offset. */ ++#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ ++#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ ++#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ ++#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ ++#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ ++#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ ++#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ ++#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ ++#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ ++#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ ++#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ ++#define R_390_TLS_GDCALL 38 /* Tag for function call in general ++ dynamic TLS code. */ ++#define R_390_TLS_LDCALL 39 /* Tag for function call in local ++ dynamic TLS code. */ ++#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ ++#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ ++#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS ++ block. */ ++#define R_390_20 57 /* Direct 20 bit. */ ++#define R_390_GOT20 58 /* 20 bit GOT offset. */ ++#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ ++#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_IRELATIVE 61 /* STT_GNU_IFUNC relocation. */ ++/* Keep this the last entry. */ ++#define R_390_NUM 62 ++ ++ ++/* CRIS relocations. */ ++#define R_CRIS_NONE 0 ++#define R_CRIS_8 1 ++#define R_CRIS_16 2 ++#define R_CRIS_32 3 ++#define R_CRIS_8_PCREL 4 ++#define R_CRIS_16_PCREL 5 ++#define R_CRIS_32_PCREL 6 ++#define R_CRIS_GNU_VTINHERIT 7 ++#define R_CRIS_GNU_VTENTRY 8 ++#define R_CRIS_COPY 9 ++#define R_CRIS_GLOB_DAT 10 ++#define R_CRIS_JUMP_SLOT 11 ++#define R_CRIS_RELATIVE 12 ++#define R_CRIS_16_GOT 13 ++#define R_CRIS_32_GOT 14 ++#define R_CRIS_16_GOTPLT 15 ++#define R_CRIS_32_GOTPLT 16 ++#define R_CRIS_32_GOTREL 17 ++#define R_CRIS_32_PLT_GOTREL 18 ++#define R_CRIS_32_PLT_PCREL 19 ++ ++#define R_CRIS_NUM 20 ++ ++ ++/* AMD x86-64 relocations. */ ++#define R_X86_64_NONE 0 /* No reloc */ ++#define R_X86_64_64 1 /* Direct 64 bit */ ++#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ ++#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ ++#define R_X86_64_PLT32 4 /* 32 bit PLT address */ ++#define R_X86_64_COPY 5 /* Copy symbol at runtime */ ++#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ ++#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ ++#define R_X86_64_RELATIVE 8 /* Adjust by program base */ ++#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative ++ offset to GOT */ ++#define R_X86_64_32 10 /* Direct 32 bit zero extended */ ++#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ ++#define R_X86_64_16 12 /* Direct 16 bit zero extended */ ++#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ ++#define R_X86_64_8 14 /* Direct 8 bit sign extended */ ++#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ ++#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ ++#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ ++#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ ++#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset ++ to two GOT entries for GD symbol */ ++#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset ++ to two GOT entries for LD symbol */ ++#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ ++#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset ++ to GOT entry for IE symbol */ ++#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ ++#define R_X86_64_PC64 24 /* PC relative 64 bit */ ++#define R_X86_64_GOTOFF64 25 /* 64 bit offset to GOT */ ++#define R_X86_64_GOTPC32 26 /* 32 bit signed pc relative ++ offset to GOT */ ++#define R_X86_64_GOT64 27 /* 64-bit GOT entry offset */ ++#define R_X86_64_GOTPCREL64 28 /* 64-bit PC relative offset ++ to GOT entry */ ++#define R_X86_64_GOTPC64 29 /* 64-bit PC relative offset to GOT */ ++#define R_X86_64_GOTPLT64 30 /* like GOT64, says PLT entry needed */ ++#define R_X86_64_PLTOFF64 31 /* 64-bit GOT relative offset ++ to PLT entry */ ++#define R_X86_64_SIZE32 32 /* Size of symbol plus 32-bit addend */ ++#define R_X86_64_SIZE64 33 /* Size of symbol plus 64-bit addend */ ++#define R_X86_64_GOTPC32_TLSDESC 34 /* GOT offset for TLS descriptor. */ ++#define R_X86_64_TLSDESC_CALL 35 /* Marker for call through TLS ++ descriptor. */ ++#define R_X86_64_TLSDESC 36 /* TLS descriptor. */ ++#define R_X86_64_IRELATIVE 37 /* Adjust indirectly by program base */ ++#define R_X86_64_RELATIVE64 38 /* 64-bit adjust by program base */ ++ ++#define R_X86_64_NUM 39 ++ ++ ++/* AM33 relocations. */ ++#define R_MN10300_NONE 0 /* No reloc. */ ++#define R_MN10300_32 1 /* Direct 32 bit. */ ++#define R_MN10300_16 2 /* Direct 16 bit. */ ++#define R_MN10300_8 3 /* Direct 8 bit. */ ++#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ ++#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ ++#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ ++#define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ ++#define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ ++#define R_MN10300_24 9 /* Direct 24 bit. */ ++#define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ ++#define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ ++#define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ ++#define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ ++#define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ ++#define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ ++#define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ ++#define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ ++#define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ ++#define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ ++#define R_MN10300_COPY 20 /* Copy symbol at runtime. */ ++#define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ ++#define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ ++#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ ++ ++#define R_MN10300_NUM 24 ++ ++ ++/* M32R relocs. */ ++#define R_M32R_NONE 0 /* No reloc. */ ++#define R_M32R_16 1 /* Direct 16 bit. */ ++#define R_M32R_32 2 /* Direct 32 bit. */ ++#define R_M32R_24 3 /* Direct 24 bit. */ ++#define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ ++#define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ ++#define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ ++#define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ ++#define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ ++#define R_M32R_LO16 9 /* Low 16 bit. */ ++#define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ ++#define R_M32R_GNU_VTINHERIT 11 ++#define R_M32R_GNU_VTENTRY 12 ++/* M32R relocs use SHT_RELA. */ ++#define R_M32R_16_RELA 33 /* Direct 16 bit. */ ++#define R_M32R_32_RELA 34 /* Direct 32 bit. */ ++#define R_M32R_24_RELA 35 /* Direct 24 bit. */ ++#define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ ++#define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ ++#define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ ++#define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ ++#define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ ++#define R_M32R_LO16_RELA 41 /* Low 16 bit */ ++#define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ ++#define R_M32R_RELA_GNU_VTINHERIT 43 ++#define R_M32R_RELA_GNU_VTENTRY 44 ++#define R_M32R_REL32 45 /* PC relative 32 bit. */ ++ ++#define R_M32R_GOT24 48 /* 24 bit GOT entry */ ++#define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ ++#define R_M32R_COPY 50 /* Copy symbol at runtime */ ++#define R_M32R_GLOB_DAT 51 /* Create GOT entry */ ++#define R_M32R_JMP_SLOT 52 /* Create PLT entry */ ++#define R_M32R_RELATIVE 53 /* Adjust by program base */ ++#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ ++#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ ++#define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned ++ low */ ++#define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed ++ low */ ++#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ ++#define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to ++ GOT with unsigned low */ ++#define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to ++ GOT with signed low */ ++#define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to ++ GOT */ ++#define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT ++ with unsigned low */ ++#define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT ++ with signed low */ ++#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ ++#define R_M32R_NUM 256 /* Keep this the last entry. */ ++ ++ ++/* TILEPro relocations. */ ++#define R_TILEPRO_NONE 0 /* No reloc */ ++#define R_TILEPRO_32 1 /* Direct 32 bit */ ++#define R_TILEPRO_16 2 /* Direct 16 bit */ ++#define R_TILEPRO_8 3 /* Direct 8 bit */ ++#define R_TILEPRO_32_PCREL 4 /* PC relative 32 bit */ ++#define R_TILEPRO_16_PCREL 5 /* PC relative 16 bit */ ++#define R_TILEPRO_8_PCREL 6 /* PC relative 8 bit */ ++#define R_TILEPRO_LO16 7 /* Low 16 bit */ ++#define R_TILEPRO_HI16 8 /* High 16 bit */ ++#define R_TILEPRO_HA16 9 /* High 16 bit, adjusted */ ++#define R_TILEPRO_COPY 10 /* Copy relocation */ ++#define R_TILEPRO_GLOB_DAT 11 /* Create GOT entry */ ++#define R_TILEPRO_JMP_SLOT 12 /* Create PLT entry */ ++#define R_TILEPRO_RELATIVE 13 /* Adjust by program base */ ++#define R_TILEPRO_BROFF_X1 14 /* X1 pipe branch offset */ ++#define R_TILEPRO_JOFFLONG_X1 15 /* X1 pipe jump offset */ ++#define R_TILEPRO_JOFFLONG_X1_PLT 16 /* X1 pipe jump offset to PLT */ ++#define R_TILEPRO_IMM8_X0 17 /* X0 pipe 8-bit */ ++#define R_TILEPRO_IMM8_Y0 18 /* Y0 pipe 8-bit */ ++#define R_TILEPRO_IMM8_X1 19 /* X1 pipe 8-bit */ ++#define R_TILEPRO_IMM8_Y1 20 /* Y1 pipe 8-bit */ ++#define R_TILEPRO_MT_IMM15_X1 21 /* X1 pipe mtspr */ ++#define R_TILEPRO_MF_IMM15_X1 22 /* X1 pipe mfspr */ ++#define R_TILEPRO_IMM16_X0 23 /* X0 pipe 16-bit */ ++#define R_TILEPRO_IMM16_X1 24 /* X1 pipe 16-bit */ ++#define R_TILEPRO_IMM16_X0_LO 25 /* X0 pipe low 16-bit */ ++#define R_TILEPRO_IMM16_X1_LO 26 /* X1 pipe low 16-bit */ ++#define R_TILEPRO_IMM16_X0_HI 27 /* X0 pipe high 16-bit */ ++#define R_TILEPRO_IMM16_X1_HI 28 /* X1 pipe high 16-bit */ ++#define R_TILEPRO_IMM16_X0_HA 29 /* X0 pipe high 16-bit, adjusted */ ++#define R_TILEPRO_IMM16_X1_HA 30 /* X1 pipe high 16-bit, adjusted */ ++#define R_TILEPRO_IMM16_X0_PCREL 31 /* X0 pipe PC relative 16 bit */ ++#define R_TILEPRO_IMM16_X1_PCREL 32 /* X1 pipe PC relative 16 bit */ ++#define R_TILEPRO_IMM16_X0_LO_PCREL 33 /* X0 pipe PC relative low 16 bit */ ++#define R_TILEPRO_IMM16_X1_LO_PCREL 34 /* X1 pipe PC relative low 16 bit */ ++#define R_TILEPRO_IMM16_X0_HI_PCREL 35 /* X0 pipe PC relative high 16 bit */ ++#define R_TILEPRO_IMM16_X1_HI_PCREL 36 /* X1 pipe PC relative high 16 bit */ ++#define R_TILEPRO_IMM16_X0_HA_PCREL 37 /* X0 pipe PC relative ha() 16 bit */ ++#define R_TILEPRO_IMM16_X1_HA_PCREL 38 /* X1 pipe PC relative ha() 16 bit */ ++#define R_TILEPRO_IMM16_X0_GOT 39 /* X0 pipe 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT 40 /* X1 pipe 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_LO 41 /* X0 pipe low 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_LO 42 /* X1 pipe low 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_HI 43 /* X0 pipe high 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_HI 44 /* X1 pipe high 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_HA 45 /* X0 pipe ha() 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_HA 46 /* X1 pipe ha() 16-bit GOT offset */ ++#define R_TILEPRO_MMSTART_X0 47 /* X0 pipe mm "start" */ ++#define R_TILEPRO_MMEND_X0 48 /* X0 pipe mm "end" */ ++#define R_TILEPRO_MMSTART_X1 49 /* X1 pipe mm "start" */ ++#define R_TILEPRO_MMEND_X1 50 /* X1 pipe mm "end" */ ++#define R_TILEPRO_SHAMT_X0 51 /* X0 pipe shift amount */ ++#define R_TILEPRO_SHAMT_X1 52 /* X1 pipe shift amount */ ++#define R_TILEPRO_SHAMT_Y0 53 /* Y0 pipe shift amount */ ++#define R_TILEPRO_SHAMT_Y1 54 /* Y1 pipe shift amount */ ++#define R_TILEPRO_DEST_IMM8_X1 55 /* X1 pipe destination 8-bit */ ++/* Relocs 56-59 are currently not defined. */ ++#define R_TILEPRO_TLS_GD_CALL 60 /* "jal" for TLS GD */ ++#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 /* X0 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 /* X1 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 /* Y0 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 /* Y1 pipe "addi" for TLS GD */ ++#define R_TILEPRO_TLS_IE_LOAD 65 /* "lw_tls" for TLS IE */ ++#define R_TILEPRO_IMM16_X0_TLS_GD 66 /* X0 pipe 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD 67 /* X1 pipe 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68 /* X0 pipe low 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69 /* X1 pipe low 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70 /* X0 pipe high 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71 /* X1 pipe high 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72 /* X0 pipe ha() 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73 /* X1 pipe ha() 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE 74 /* X0 pipe 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE 75 /* X1 pipe 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76 /* X0 pipe low 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77 /* X1 pipe low 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78 /* X0 pipe high 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79 /* X1 pipe high 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80 /* X0 pipe ha() 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81 /* X1 pipe ha() 16-bit TLS IE offset */ ++#define R_TILEPRO_TLS_DTPMOD32 82 /* ID of module containing symbol */ ++#define R_TILEPRO_TLS_DTPOFF32 83 /* Offset in TLS block */ ++#define R_TILEPRO_TLS_TPOFF32 84 /* Offset in static TLS block */ ++#define R_TILEPRO_IMM16_X0_TLS_LE 85 /* X0 pipe 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE 86 /* X1 pipe 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87 /* X0 pipe low 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88 /* X1 pipe low 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89 /* X0 pipe high 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90 /* X1 pipe high 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91 /* X0 pipe ha() 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92 /* X1 pipe ha() 16-bit TLS LE offset */ ++ ++#define R_TILEPRO_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ ++#define R_TILEPRO_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ ++ ++#define R_TILEPRO_NUM 130 ++ ++ ++/* TILE-Gx relocations. */ ++#define R_TILEGX_NONE 0 /* No reloc */ ++#define R_TILEGX_64 1 /* Direct 64 bit */ ++#define R_TILEGX_32 2 /* Direct 32 bit */ ++#define R_TILEGX_16 3 /* Direct 16 bit */ ++#define R_TILEGX_8 4 /* Direct 8 bit */ ++#define R_TILEGX_64_PCREL 5 /* PC relative 64 bit */ ++#define R_TILEGX_32_PCREL 6 /* PC relative 32 bit */ ++#define R_TILEGX_16_PCREL 7 /* PC relative 16 bit */ ++#define R_TILEGX_8_PCREL 8 /* PC relative 8 bit */ ++#define R_TILEGX_HW0 9 /* hword 0 16-bit */ ++#define R_TILEGX_HW1 10 /* hword 1 16-bit */ ++#define R_TILEGX_HW2 11 /* hword 2 16-bit */ ++#define R_TILEGX_HW3 12 /* hword 3 16-bit */ ++#define R_TILEGX_HW0_LAST 13 /* last hword 0 16-bit */ ++#define R_TILEGX_HW1_LAST 14 /* last hword 1 16-bit */ ++#define R_TILEGX_HW2_LAST 15 /* last hword 2 16-bit */ ++#define R_TILEGX_COPY 16 /* Copy relocation */ ++#define R_TILEGX_GLOB_DAT 17 /* Create GOT entry */ ++#define R_TILEGX_JMP_SLOT 18 /* Create PLT entry */ ++#define R_TILEGX_RELATIVE 19 /* Adjust by program base */ ++#define R_TILEGX_BROFF_X1 20 /* X1 pipe branch offset */ ++#define R_TILEGX_JUMPOFF_X1 21 /* X1 pipe jump offset */ ++#define R_TILEGX_JUMPOFF_X1_PLT 22 /* X1 pipe jump offset to PLT */ ++#define R_TILEGX_IMM8_X0 23 /* X0 pipe 8-bit */ ++#define R_TILEGX_IMM8_Y0 24 /* Y0 pipe 8-bit */ ++#define R_TILEGX_IMM8_X1 25 /* X1 pipe 8-bit */ ++#define R_TILEGX_IMM8_Y1 26 /* Y1 pipe 8-bit */ ++#define R_TILEGX_DEST_IMM8_X1 27 /* X1 pipe destination 8-bit */ ++#define R_TILEGX_MT_IMM14_X1 28 /* X1 pipe mtspr */ ++#define R_TILEGX_MF_IMM14_X1 29 /* X1 pipe mfspr */ ++#define R_TILEGX_MMSTART_X0 30 /* X0 pipe mm "start" */ ++#define R_TILEGX_MMEND_X0 31 /* X0 pipe mm "end" */ ++#define R_TILEGX_SHAMT_X0 32 /* X0 pipe shift amount */ ++#define R_TILEGX_SHAMT_X1 33 /* X1 pipe shift amount */ ++#define R_TILEGX_SHAMT_Y0 34 /* Y0 pipe shift amount */ ++#define R_TILEGX_SHAMT_Y1 35 /* Y1 pipe shift amount */ ++#define R_TILEGX_IMM16_X0_HW0 36 /* X0 pipe hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0 37 /* X1 pipe hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1 38 /* X0 pipe hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1 39 /* X1 pipe hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2 40 /* X0 pipe hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2 41 /* X1 pipe hword 2 */ ++#define R_TILEGX_IMM16_X0_HW3 42 /* X0 pipe hword 3 */ ++#define R_TILEGX_IMM16_X1_HW3 43 /* X1 pipe hword 3 */ ++#define R_TILEGX_IMM16_X0_HW0_LAST 44 /* X0 pipe last hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_LAST 45 /* X1 pipe last hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_LAST 46 /* X0 pipe last hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_LAST 47 /* X1 pipe last hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_LAST 48 /* X0 pipe last hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_LAST 49 /* X1 pipe last hword 2 */ ++#define R_TILEGX_IMM16_X0_HW0_PCREL 50 /* X0 pipe PC relative hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_PCREL 51 /* X1 pipe PC relative hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_PCREL 52 /* X0 pipe PC relative hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_PCREL 53 /* X1 pipe PC relative hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_PCREL 54 /* X0 pipe PC relative hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_PCREL 55 /* X1 pipe PC relative hword 2 */ ++#define R_TILEGX_IMM16_X0_HW3_PCREL 56 /* X0 pipe PC relative hword 3 */ ++#define R_TILEGX_IMM16_X1_HW3_PCREL 57 /* X1 pipe PC relative hword 3 */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */ ++#define R_TILEGX_IMM16_X0_HW0_GOT 64 /* X0 pipe hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW0_GOT 65 /* X1 pipe hword 0 GOT offset */ ++/* Relocs 66-71 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */ ++/* Relocs 76-77 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78 /* X0 pipe hword 0 TLS GD offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79 /* X1 pipe hword 0 TLS GD offset */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80 /* X0 pipe hword 0 TLS LE offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81 /* X1 pipe hword 0 TLS LE offset */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */ ++/* Relocs 90-91 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92 /* X0 pipe hword 0 TLS IE offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93 /* X1 pipe hword 0 TLS IE offset */ ++/* Relocs 94-99 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */ ++/* Relocs 104-105 are currently not defined. */ ++#define R_TILEGX_TLS_DTPMOD64 106 /* 64-bit ID of symbol's module */ ++#define R_TILEGX_TLS_DTPOFF64 107 /* 64-bit offset in TLS block */ ++#define R_TILEGX_TLS_TPOFF64 108 /* 64-bit offset in static TLS block */ ++#define R_TILEGX_TLS_DTPMOD32 109 /* 32-bit ID of symbol's module */ ++#define R_TILEGX_TLS_DTPOFF32 110 /* 32-bit offset in TLS block */ ++#define R_TILEGX_TLS_TPOFF32 111 /* 32-bit offset in static TLS block */ ++#define R_TILEGX_TLS_GD_CALL 112 /* "jal" for TLS GD */ ++#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113 /* X0 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114 /* X1 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 /* Y0 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 /* Y1 pipe "addi" for TLS GD */ ++#define R_TILEGX_TLS_IE_LOAD 117 /* "ld_tls" for TLS IE */ ++#define R_TILEGX_IMM8_X0_TLS_ADD 118 /* X0 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_X1_TLS_ADD 119 /* X1 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_Y0_TLS_ADD 120 /* Y0 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_Y1_TLS_ADD 121 /* Y1 pipe "addi" for TLS GD/IE */ ++ ++#define R_TILEGX_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ ++#define R_TILEGX_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ ++ ++#define R_TILEGX_NUM 130 ++ ++#endif /* elf.h */ diff --git a/target/linux/generic/patches-3.18/212-byteshift_portability.patch b/target/linux/generic/patches-3.18/212-byteshift_portability.patch new file mode 100644 index 0000000..0f23ba9 --- /dev/null +++ b/target/linux/generic/patches-3.18/212-byteshift_portability.patch @@ -0,0 +1,51 @@ +--- a/tools/include/tools/be_byteshift.h ++++ b/tools/include/tools/be_byteshift.h +@@ -1,6 +1,10 @@ + #ifndef _TOOLS_BE_BYTESHIFT_H + #define _TOOLS_BE_BYTESHIFT_H + ++#ifndef __linux__ ++#include "linux_types.h" ++#endif ++ + #include + + static inline uint16_t __get_unaligned_be16(const uint8_t *p) +--- a/tools/include/tools/le_byteshift.h ++++ b/tools/include/tools/le_byteshift.h +@@ -1,6 +1,10 @@ + #ifndef _TOOLS_LE_BYTESHIFT_H + #define _TOOLS_LE_BYTESHIFT_H + ++#ifndef __linux__ ++#include "linux_types.h" ++#endif ++ + #include + + static inline uint16_t __get_unaligned_le16(const uint8_t *p) +--- /dev/null ++++ b/tools/include/tools/linux_types.h +@@ -0,0 +1,22 @@ ++#ifndef __LINUX_TYPES_H ++#define __LINUX_TYPES_H ++ ++#include ++ ++typedef uint8_t __u8; ++typedef uint8_t __be8; ++typedef uint8_t __le8; ++ ++typedef uint16_t __u16; ++typedef uint16_t __be16; ++typedef uint16_t __le16; ++ ++typedef uint32_t __u32; ++typedef uint32_t __be32; ++typedef uint32_t __le32; ++ ++typedef uint64_t __u64; ++typedef uint64_t __be64; ++typedef uint64_t __le64; ++ ++#endif diff --git a/target/linux/generic/patches-3.18/213-x86_vdso_portability.patch b/target/linux/generic/patches-3.18/213-x86_vdso_portability.patch new file mode 100644 index 0000000..937ab90 --- /dev/null +++ b/target/linux/generic/patches-3.18/213-x86_vdso_portability.patch @@ -0,0 +1,13 @@ +--- a/arch/x86/vdso/vdso2c.c ++++ b/arch/x86/vdso/vdso2c.c +@@ -63,8 +63,8 @@ + + #include + +-#include +-#include ++#include ++#include + + const char *outfilename; + diff --git a/target/linux/generic/patches-3.18/214-spidev_h_portability.patch b/target/linux/generic/patches-3.18/214-spidev_h_portability.patch new file mode 100644 index 0000000..dbee090 --- /dev/null +++ b/target/linux/generic/patches-3.18/214-spidev_h_portability.patch @@ -0,0 +1,11 @@ +--- a/include/uapi/linux/spi/spidev.h ++++ b/include/uapi/linux/spi/spidev.h +@@ -111,7 +111,7 @@ struct spi_ioc_transfer { + + /* not all platforms use or _IOC_TYPECHECK() ... */ + #define SPI_MSGSIZE(N) \ +- ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ ++ ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << 13)) \ + ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) + #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + diff --git a/target/linux/generic/patches-3.18/220-gc_sections.patch b/target/linux/generic/patches-3.18/220-gc_sections.patch new file mode 100644 index 0000000..775e11c --- /dev/null +++ b/target/linux/generic/patches-3.18/220-gc_sections.patch @@ -0,0 +1,531 @@ +From: Felix Fietkau + +use -ffunction-sections, -fdata-sections and --gc-sections + +In combination with kernel symbol export stripping this significantly reduces +the kernel image size. Used on both ARM and MIPS architectures. + +Signed-off-by: Felix Fietkau +Signed-off-by: Jonas Gorski +Signed-off-by: Gabor Juhos +--- + +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -89,10 +89,14 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + # + cflags-y += -G 0 -mno-abicalls -fno-pic -pipe + cflags-y += -msoft-float +-LDFLAGS_vmlinux += -G 0 -static -n -nostdlib ++LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections + KBUILD_AFLAGS_MODULE += -mlong-calls + KBUILD_CFLAGS_MODULE += -mlong-calls + ++ifndef CONFIG_FUNCTION_TRACER ++KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections ++endif ++ + # + # pass -msoft-float to GAS if it supports it. However on newer binutils + # (specifically newer than 2.24.51.20140728) we then also need to explicitly +--- a/arch/mips/kernel/vmlinux.lds.S ++++ b/arch/mips/kernel/vmlinux.lds.S +@@ -67,7 +67,7 @@ SECTIONS + /* Exception table for data bus errors */ + __dbe_table : { + __start___dbe_table = .; +- *(__dbe_table) ++ KEEP(*(__dbe_table)) + __stop___dbe_table = .; + } + +@@ -112,7 +112,7 @@ SECTIONS + . = ALIGN(4); + .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) { + __mips_machines_start = .; +- *(.mips.machines.init) ++ KEEP(*(.mips.machines.init)) + __mips_machines_end = .; + } + +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -89,7 +89,7 @@ + #ifdef CONFIG_FTRACE_MCOUNT_RECORD + #define MCOUNT_REC() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_mcount_loc) = .; \ +- *(__mcount_loc) \ ++ KEEP(*(__mcount_loc)) \ + VMLINUX_SYMBOL(__stop_mcount_loc) = .; + #else + #define MCOUNT_REC() +@@ -97,7 +97,7 @@ + + #ifdef CONFIG_TRACE_BRANCH_PROFILING + #define LIKELY_PROFILE() VMLINUX_SYMBOL(__start_annotated_branch_profile) = .; \ +- *(_ftrace_annotated_branch) \ ++ KEEP(*(_ftrace_annotated_branch)) \ + VMLINUX_SYMBOL(__stop_annotated_branch_profile) = .; + #else + #define LIKELY_PROFILE() +@@ -105,7 +105,7 @@ + + #ifdef CONFIG_PROFILE_ALL_BRANCHES + #define BRANCH_PROFILE() VMLINUX_SYMBOL(__start_branch_profile) = .; \ +- *(_ftrace_branch) \ ++ KEEP(*(_ftrace_branch)) \ + VMLINUX_SYMBOL(__stop_branch_profile) = .; + #else + #define BRANCH_PROFILE() +@@ -114,7 +114,7 @@ + #ifdef CONFIG_KPROBES + #define KPROBE_BLACKLIST() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_kprobe_blacklist) = .; \ +- *(_kprobe_blacklist) \ ++ KEEP(*(_kprobe_blacklist)) \ + VMLINUX_SYMBOL(__stop_kprobe_blacklist) = .; + #else + #define KPROBE_BLACKLIST() +@@ -123,7 +123,7 @@ + #ifdef CONFIG_EVENT_TRACING + #define FTRACE_EVENTS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_ftrace_events) = .; \ +- *(_ftrace_events) \ ++ KEEP(*(_ftrace_events)) \ + VMLINUX_SYMBOL(__stop_ftrace_events) = .; + #else + #define FTRACE_EVENTS() +@@ -131,7 +131,7 @@ + + #ifdef CONFIG_TRACING + #define TRACE_PRINTKS() VMLINUX_SYMBOL(__start___trace_bprintk_fmt) = .; \ +- *(__trace_printk_fmt) /* Trace_printk fmt' pointer */ \ ++ KEEP(*(__trace_printk_fmt)) /* Trace_printk fmt' pointer */ \ + VMLINUX_SYMBOL(__stop___trace_bprintk_fmt) = .; + #define TRACEPOINT_STR() VMLINUX_SYMBOL(__start___tracepoint_str) = .; \ + *(__tracepoint_str) /* Trace_printk fmt' pointer */ \ +@@ -144,7 +144,7 @@ + #ifdef CONFIG_FTRACE_SYSCALLS + #define TRACE_SYSCALLS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_syscalls_metadata) = .; \ +- *(__syscalls_metadata) \ ++ KEEP(*(__syscalls_metadata)) \ + VMLINUX_SYMBOL(__stop_syscalls_metadata) = .; + #else + #define TRACE_SYSCALLS() +@@ -158,8 +158,8 @@ + #define _OF_TABLE_1(name) \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__##name##_of_table) = .; \ +- *(__##name##_of_table) \ +- *(__##name##_of_table_end) ++ KEEP(*(__##name##_of_table)) \ ++ KEEP(*(__##name##_of_table_end)) + + #define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc) + #define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip) +@@ -171,7 +171,7 @@ + #define KERNEL_DTB() \ + STRUCT_ALIGN(); \ + VMLINUX_SYMBOL(__dtb_start) = .; \ +- *(.dtb.init.rodata) \ ++ KEEP(*(.dtb.init.rodata)) \ + VMLINUX_SYMBOL(__dtb_end) = .; + + /* .data section */ +@@ -187,16 +187,17 @@ + /* implement dynamic printk debug */ \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__start___jump_table) = .; \ +- *(__jump_table) \ ++ KEEP(*(__jump_table)) \ + VMLINUX_SYMBOL(__stop___jump_table) = .; \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__start___verbose) = .; \ +- *(__verbose) \ ++ KEEP(*(__verbose)) \ + VMLINUX_SYMBOL(__stop___verbose) = .; \ + LIKELY_PROFILE() \ + BRANCH_PROFILE() \ + TRACE_PRINTKS() \ +- TRACEPOINT_STR() ++ TRACEPOINT_STR() \ ++ *(.data.[a-zA-Z_]*) + + /* + * Data section helpers +@@ -250,35 +251,35 @@ + /* PCI quirks */ \ + .pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \ +- *(.pci_fixup_early) \ ++ KEEP(*(.pci_fixup_early)) \ + VMLINUX_SYMBOL(__end_pci_fixups_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_header) = .; \ +- *(.pci_fixup_header) \ ++ KEEP(*(.pci_fixup_header)) \ + VMLINUX_SYMBOL(__end_pci_fixups_header) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_final) = .; \ +- *(.pci_fixup_final) \ ++ KEEP(*(.pci_fixup_final)) \ + VMLINUX_SYMBOL(__end_pci_fixups_final) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_enable) = .; \ +- *(.pci_fixup_enable) \ ++ KEEP(*(.pci_fixup_enable)) \ + VMLINUX_SYMBOL(__end_pci_fixups_enable) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume) = .; \ +- *(.pci_fixup_resume) \ ++ KEEP(*(.pci_fixup_resume)) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .; \ +- *(.pci_fixup_resume_early) \ ++ KEEP(*(.pci_fixup_resume_early)) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \ +- *(.pci_fixup_suspend) \ ++ KEEP(*(.pci_fixup_suspend)) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend_late) = .; \ +- *(.pci_fixup_suspend_late) \ ++ KEEP(*(.pci_fixup_suspend_late)) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \ + } \ + \ + /* Built-in firmware blobs */ \ + .builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_builtin_fw) = .; \ +- *(.builtin_fw) \ ++ KEEP(*(.builtin_fw)) \ + VMLINUX_SYMBOL(__end_builtin_fw) = .; \ + } \ + \ +@@ -287,49 +288,49 @@ + /* Kernel symbol table: Normal symbols */ \ + __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab) = .; \ +- *(SORT(___ksymtab+*)) \ ++ KEEP(*(SORT(___ksymtab+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \ +- *(SORT(___ksymtab_gpl+*)) \ ++ KEEP(*(SORT(___ksymtab_gpl+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \ + } \ + \ + /* Kernel symbol table: Normal unused symbols */ \ + __ksymtab_unused : AT(ADDR(__ksymtab_unused) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_unused) = .; \ +- *(SORT(___ksymtab_unused+*)) \ ++ KEEP(*(SORT(___ksymtab_unused+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_unused) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only unused symbols */ \ + __ksymtab_unused_gpl : AT(ADDR(__ksymtab_unused_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_unused_gpl) = .; \ +- *(SORT(___ksymtab_unused_gpl+*)) \ ++ KEEP(*(SORT(___ksymtab_unused_gpl+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_unused_gpl) = .; \ + } \ + \ + /* Kernel symbol table: GPL-future-only symbols */ \ + __ksymtab_gpl_future : AT(ADDR(__ksymtab_gpl_future) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl_future) = .; \ +- *(SORT(___ksymtab_gpl_future+*)) \ ++ KEEP(*(SORT(___ksymtab_gpl_future+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl_future) = .; \ + } \ + \ + /* Kernel symbol table: Normal symbols */ \ + __kcrctab : AT(ADDR(__kcrctab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab) = .; \ +- *(SORT(___kcrctab+*)) \ ++ KEEP(*(SORT(___kcrctab+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_gpl) = .; \ +- *(SORT(___kcrctab_gpl+*)) \ ++ KEEP(*(SORT(___kcrctab_gpl+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_gpl) = .; \ + } \ + \ +@@ -343,14 +344,14 @@ + /* Kernel symbol table: GPL-only unused symbols */ \ + __kcrctab_unused_gpl : AT(ADDR(__kcrctab_unused_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_unused_gpl) = .; \ +- *(SORT(___kcrctab_unused_gpl+*)) \ ++ KEEP(*(SORT(___kcrctab_unused_gpl+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_unused_gpl) = .; \ + } \ + \ + /* Kernel symbol table: GPL-future-only symbols */ \ + __kcrctab_gpl_future : AT(ADDR(__kcrctab_gpl_future) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_gpl_future) = .; \ +- *(SORT(___kcrctab_gpl_future+*)) \ ++ KEEP(*(SORT(___kcrctab_gpl_future+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_gpl_future) = .; \ + } \ + \ +@@ -369,14 +370,14 @@ + /* Built-in module parameters. */ \ + __param : AT(ADDR(__param) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___param) = .; \ +- *(__param) \ ++ KEEP(*(__param)) \ + VMLINUX_SYMBOL(__stop___param) = .; \ + } \ + \ + /* Built-in module versions. */ \ + __modver : AT(ADDR(__modver) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___modver) = .; \ +- *(__modver) \ ++ KEEP(*(__modver)) \ + VMLINUX_SYMBOL(__stop___modver) = .; \ + . = ALIGN((align)); \ + VMLINUX_SYMBOL(__end_rodata) = .; \ +@@ -432,7 +433,7 @@ + #define ENTRY_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__entry_text_start) = .; \ +- *(.entry.text) \ ++ KEEP(*(.entry.text)) \ + VMLINUX_SYMBOL(__entry_text_end) = .; + + #ifdef CONFIG_FUNCTION_GRAPH_TRACER +@@ -460,7 +461,7 @@ + . = ALIGN(align); \ + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ex_table) = .; \ +- *(__ex_table) \ ++ KEEP(*(__ex_table)) \ + VMLINUX_SYMBOL(__stop___ex_table) = .; \ + } + +@@ -476,8 +477,8 @@ + #ifdef CONFIG_CONSTRUCTORS + #define KERNEL_CTORS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__ctors_start) = .; \ +- *(.ctors) \ +- *(.init_array) \ ++ KEEP(*(.ctors)) \ ++ KEEP(*(.init_array)) \ + VMLINUX_SYMBOL(__ctors_end) = .; + #else + #define KERNEL_CTORS() +@@ -525,7 +526,7 @@ + #define SBSS(sbss_align) \ + . = ALIGN(sbss_align); \ + .sbss : AT(ADDR(.sbss) - LOAD_OFFSET) { \ +- *(.sbss) \ ++ *(.sbss .sbss.*) \ + *(.scommon) \ + } + +@@ -543,7 +544,7 @@ + BSS_FIRST_SECTIONS \ + *(.bss..page_aligned) \ + *(.dynbss) \ +- *(.bss) \ ++ *(.bss .bss.*) \ + *(COMMON) \ + } + +@@ -592,7 +593,7 @@ + . = ALIGN(8); \ + __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___bug_table) = .; \ +- *(__bug_table) \ ++ KEEP(*(__bug_table)) \ + VMLINUX_SYMBOL(__stop___bug_table) = .; \ + } + #else +@@ -604,7 +605,7 @@ + . = ALIGN(4); \ + .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__tracedata_start) = .; \ +- *(.tracedata) \ ++ KEEP(*(.tracedata)) \ + VMLINUX_SYMBOL(__tracedata_end) = .; \ + } + #else +@@ -621,17 +622,17 @@ + #define INIT_SETUP(initsetup_align) \ + . = ALIGN(initsetup_align); \ + VMLINUX_SYMBOL(__setup_start) = .; \ +- *(.init.setup) \ ++ KEEP(*(.init.setup)) \ + VMLINUX_SYMBOL(__setup_end) = .; + + #define INIT_CALLS_LEVEL(level) \ + VMLINUX_SYMBOL(__initcall##level##_start) = .; \ +- *(.initcall##level##.init) \ +- *(.initcall##level##s.init) \ ++ KEEP(*(.initcall##level##.init)) \ ++ KEEP(*(.initcall##level##s.init)) \ + + #define INIT_CALLS \ + VMLINUX_SYMBOL(__initcall_start) = .; \ +- *(.initcallearly.init) \ ++ KEEP(*(.initcallearly.init)) \ + INIT_CALLS_LEVEL(0) \ + INIT_CALLS_LEVEL(1) \ + INIT_CALLS_LEVEL(2) \ +@@ -645,21 +646,21 @@ + + #define CON_INITCALL \ + VMLINUX_SYMBOL(__con_initcall_start) = .; \ +- *(.con_initcall.init) \ ++ KEEP(*(.con_initcall.init)) \ + VMLINUX_SYMBOL(__con_initcall_end) = .; + + #define SECURITY_INITCALL \ + VMLINUX_SYMBOL(__security_initcall_start) = .; \ +- *(.security_initcall.init) \ ++ KEEP(*(.security_initcall.init)) \ + VMLINUX_SYMBOL(__security_initcall_end) = .; + + #ifdef CONFIG_BLK_DEV_INITRD + #define INIT_RAM_FS \ + . = ALIGN(4); \ + VMLINUX_SYMBOL(__initramfs_start) = .; \ +- *(.init.ramfs) \ ++ KEEP(*(.init.ramfs)) \ + . = ALIGN(8); \ +- *(.init.ramfs.info) ++ KEEP(*(.init.ramfs.info)) + #else + #define INIT_RAM_FS + #endif +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -18,11 +18,16 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) + LDFLAGS_vmlinux += --be8 + LDFLAGS_MODULE += --be8 + endif ++LDFLAGS_vmlinux += --gc-sections + + OBJCOPYFLAGS :=-O binary -R .comment -S + GZFLAGS :=-9 + #KBUILD_CFLAGS +=-pipe + ++ifndef CONFIG_FUNCTION_TRACER ++KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections ++endif ++ + # Never generate .eh_frame + KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) + +--- a/arch/arm/kernel/vmlinux.lds.S ++++ b/arch/arm/kernel/vmlinux.lds.S +@@ -12,13 +12,13 @@ + #define PROC_INFO \ + . = ALIGN(4); \ + VMLINUX_SYMBOL(__proc_info_begin) = .; \ +- *(.proc.info.init) \ ++ KEEP(*(.proc.info.init)) \ + VMLINUX_SYMBOL(__proc_info_end) = .; + + #define IDMAP_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__idmap_text_start) = .; \ +- *(.idmap.text) \ ++ KEEP(*(.idmap.text)) \ + VMLINUX_SYMBOL(__idmap_text_end) = .; \ + . = ALIGN(32); \ + VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \ +@@ -93,7 +93,7 @@ SECTIONS + .text : { /* Real text segment */ + _stext = .; /* Text and read-only data */ + __exception_text_start = .; +- *(.exception.text) ++ KEEP(*(.exception.text)) + __exception_text_end = .; + IRQENTRY_TEXT + TEXT_TEXT +@@ -118,7 +118,7 @@ SECTIONS + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { + __start___ex_table = .; + #ifdef CONFIG_MMU +- *(__ex_table) ++ KEEP(*(__ex_table)) + #endif + __stop___ex_table = .; + } +@@ -130,12 +130,12 @@ SECTIONS + . = ALIGN(8); + .ARM.unwind_idx : { + __start_unwind_idx = .; +- *(.ARM.exidx*) ++ KEEP(*(.ARM.exidx*)) + __stop_unwind_idx = .; + } + .ARM.unwind_tab : { + __start_unwind_tab = .; +- *(.ARM.extab*) ++ KEEP(*(.ARM.extab*)) + __stop_unwind_tab = .; + } + #endif +@@ -154,14 +154,14 @@ SECTIONS + */ + __vectors_start = .; + .vectors 0 : AT(__vectors_start) { +- *(.vectors) ++ KEEP(*(.vectors)) + } + . = __vectors_start + SIZEOF(.vectors); + __vectors_end = .; + + __stubs_start = .; + .stubs 0x1000 : AT(__stubs_start) { +- *(.stubs) ++ KEEP(*(.stubs)) + } + . = __stubs_start + SIZEOF(.stubs); + __stubs_end = .; +@@ -175,24 +175,24 @@ SECTIONS + } + .init.arch.info : { + __arch_info_begin = .; +- *(.arch.info.init) ++ KEEP(*(.arch.info.init)) + __arch_info_end = .; + } + .init.tagtable : { + __tagtable_begin = .; +- *(.taglist.init) ++ KEEP(*(.taglist.init)) + __tagtable_end = .; + } + #ifdef CONFIG_SMP_ON_UP + .init.smpalt : { + __smpalt_begin = .; +- *(.alt.smp.init) ++ KEEP(*(.alt.smp.init)) + __smpalt_end = .; + } + #endif + .init.pv_table : { + __pv_table_begin = .; +- *(.pv_table) ++ KEEP(*(.pv_table)) + __pv_table_end = .; + } + .init.data : { +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -122,6 +122,7 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) + ORIG_CFLAGS := $(KBUILD_CFLAGS) + KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) + endif ++KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL)) + + ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) + asflags-y := -DZIMAGE diff --git a/target/linux/generic/patches-3.18/221-module_exports.patch b/target/linux/generic/patches-3.18/221-module_exports.patch new file mode 100644 index 0000000..f2cad7a --- /dev/null +++ b/target/linux/generic/patches-3.18/221-module_exports.patch @@ -0,0 +1,88 @@ +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -54,6 +54,16 @@ + #define LOAD_OFFSET 0 + #endif + ++#ifndef SYMTAB_KEEP ++#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*))) ++#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*))) ++#endif ++ ++#ifndef SYMTAB_DISCARD ++#define SYMTAB_DISCARD ++#define SYMTAB_DISCARD_GPL ++#endif ++ + #include + + /* Align . to a 8 byte boundary equals to maximum function alignment. */ +@@ -288,14 +298,14 @@ + /* Kernel symbol table: Normal symbols */ \ + __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab) = .; \ +- KEEP(*(SORT(___ksymtab+*))) \ ++ SYMTAB_KEEP \ + VMLINUX_SYMBOL(__stop___ksymtab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \ +- KEEP(*(SORT(___ksymtab_gpl+*))) \ ++ SYMTAB_KEEP_GPL \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \ + } \ + \ +@@ -357,7 +367,7 @@ + \ + /* Kernel symbol table: strings */ \ + __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \ +- *(__ksymtab_strings) \ ++ *(__ksymtab_strings+*) \ + } \ + \ + /* __*init sections */ \ +@@ -679,6 +689,8 @@ + EXIT_TEXT \ + EXIT_DATA \ + EXIT_CALL \ ++ SYMTAB_DISCARD \ ++ SYMTAB_DISCARD_GPL \ + *(.discard) \ + *(.discard.*) \ + } +--- a/scripts/Makefile.build ++++ b/scripts/Makefile.build +@@ -298,7 +298,7 @@ targets += $(extra-y) $(MAKECMDGOALS) $( + # Linker scripts preprocessor (.lds.S -> .lds) + # --------------------------------------------------------------------------- + quiet_cmd_cpp_lds_S = LDS $@ +- cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \ ++ cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -C -U$(ARCH) \ + -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< + + $(obj)/%.lds: $(src)/%.lds.S FORCE +--- a/include/linux/export.h ++++ b/include/linux/export.h +@@ -52,12 +52,19 @@ extern struct module __this_module; + #define __CRC_SYMBOL(sym, sec) + #endif + ++#ifdef MODULE ++#define __EXPORT_SUFFIX(sym) ++#else ++#define __EXPORT_SUFFIX(sym) "+" #sym ++#endif ++ + /* For every exported symbol, place a struct in the __ksymtab section */ + #define __EXPORT_SYMBOL(sym, sec) \ + extern typeof(sym) sym; \ + __CRC_SYMBOL(sym, sec) \ + static const char __kstrtab_##sym[] \ +- __attribute__((section("__ksymtab_strings"), aligned(1))) \ ++ __attribute__((section("__ksymtab_strings" \ ++ __EXPORT_SUFFIX(sym)), aligned(1))) \ + = VMLINUX_SYMBOL_STR(sym); \ + extern const struct kernel_symbol __ksymtab_##sym; \ + __visible const struct kernel_symbol __ksymtab_##sym \ diff --git a/target/linux/generic/patches-3.18/230-openwrt_lzma_options.patch b/target/linux/generic/patches-3.18/230-openwrt_lzma_options.patch new file mode 100644 index 0000000..e59fdcd --- /dev/null +++ b/target/linux/generic/patches-3.18/230-openwrt_lzma_options.patch @@ -0,0 +1,58 @@ +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -325,7 +325,7 @@ cmd_bzip2 = (cat $(filter-out FORCE,$^) + + quiet_cmd_lzma = LZMA $@ + cmd_lzma = (cat $(filter-out FORCE,$^) | \ +- lzma -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ ++ lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + + quiet_cmd_lzo = LZO $@ +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -226,7 +226,7 @@ cpio_list= + output="/dev/stdout" + output_file="" + is_cpio_compressed= +-compr="gzip -n -9 -f" ++compr="gzip -n -9 -f -" + + arg="$1" + case "$arg" in +@@ -242,13 +242,13 @@ case "$arg" in + output=${cpio_list} + echo "$output_file" | grep -q "\.gz$" \ + && [ -x "`which gzip 2> /dev/null`" ] \ +- && compr="gzip -n -9 -f" ++ && compr="gzip -n -9 -f -" + echo "$output_file" | grep -q "\.bz2$" \ + && [ -x "`which bzip2 2> /dev/null`" ] \ +- && compr="bzip2 -9 -f" ++ && compr="bzip2 -9 -f -" + echo "$output_file" | grep -q "\.lzma$" \ + && [ -x "`which lzma 2> /dev/null`" ] \ +- && compr="lzma -9 -f" ++ && compr="lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so" + echo "$output_file" | grep -q "\.xz$" \ + && [ -x "`which xz 2> /dev/null`" ] \ + && compr="xz --check=crc32 --lzma2=dict=1MiB" +@@ -315,7 +315,7 @@ if [ ! -z ${output_file} ]; then + if [ "${is_cpio_compressed}" = "compressed" ]; then + cat ${cpio_tfile} > ${output_file} + else +- (cat ${cpio_tfile} | ${compr} - > ${output_file}) \ ++ (cat ${cpio_tfile} | ${compr} > ${output_file}) \ + || (rm -f ${output_file} ; false) + fi + [ -z ${cpio_file} ] && rm ${cpio_tfile} +--- a/lib/decompress.c ++++ b/lib/decompress.c +@@ -48,6 +48,7 @@ static const struct compress_format comp + { {037, 0236}, "gzip", gunzip }, + { {0x42, 0x5a}, "bzip2", bunzip2 }, + { {0x5d, 0x00}, "lzma", unlzma }, ++ { {0x6d, 0x00}, "lzma-openwrt", unlzma }, + { {0xfd, 0x37}, "xz", unxz }, + { {0x89, 0x4c}, "lzo", unlzo }, + { {0x02, 0x21}, "lz4", unlz4 }, diff --git a/target/linux/generic/patches-3.18/250-netfilter_depends.patch b/target/linux/generic/patches-3.18/250-netfilter_depends.patch new file mode 100644 index 0000000..47be4a0 --- /dev/null +++ b/target/linux/generic/patches-3.18/250-netfilter_depends.patch @@ -0,0 +1,18 @@ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -210,7 +210,6 @@ config NF_CONNTRACK_FTP + + config NF_CONNTRACK_H323 + tristate "H.323 protocol support" +- depends on (IPV6 || IPV6=n) + depends on NETFILTER_ADVANCED + help + H.323 is a VoIP signalling protocol from ITU-T. As one of the most +@@ -907,7 +906,6 @@ config NETFILTER_XT_TARGET_SECMARK + + config NETFILTER_XT_TARGET_TCPMSS + tristate '"TCPMSS" target support' +- depends on (IPV6 || IPV6=n) + default m if NETFILTER_ADVANCED=n + ---help--- + This option adds a `TCPMSS' target, which allows you to alter the diff --git a/target/linux/generic/patches-3.18/251-sound_kconfig.patch b/target/linux/generic/patches-3.18/251-sound_kconfig.patch new file mode 100644 index 0000000..c2ebace --- /dev/null +++ b/target/linux/generic/patches-3.18/251-sound_kconfig.patch @@ -0,0 +1,18 @@ +--- a/sound/core/Kconfig ++++ b/sound/core/Kconfig +@@ -10,13 +10,13 @@ config SND_DMAENGINE_PCM + tristate + + config SND_HWDEP +- tristate ++ tristate "Sound hardware support" + + config SND_RAWMIDI + tristate + + config SND_COMPRESS_OFFLOAD +- tristate ++ tristate "Compression offloading support" + + # To be effective this also requires INPUT - users should say: + # select SND_JACK if INPUT=y || INPUT=SND diff --git a/target/linux/generic/patches-3.18/252-mv_cesa_depends.patch b/target/linux/generic/patches-3.18/252-mv_cesa_depends.patch new file mode 100644 index 0000000..fee28db --- /dev/null +++ b/target/linux/generic/patches-3.18/252-mv_cesa_depends.patch @@ -0,0 +1,10 @@ +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -164,6 +164,7 @@ config CRYPTO_DEV_MV_CESA + depends on PLAT_ORION + select CRYPTO_ALGAPI + select CRYPTO_AES ++ select CRYPTO_HASH2 + select CRYPTO_BLKCIPHER2 + select CRYPTO_HASH + help diff --git a/target/linux/generic/patches-3.18/253-ssb_b43_default_on.patch b/target/linux/generic/patches-3.18/253-ssb_b43_default_on.patch new file mode 100644 index 0000000..29d2a41 --- /dev/null +++ b/target/linux/generic/patches-3.18/253-ssb_b43_default_on.patch @@ -0,0 +1,29 @@ +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -29,6 +29,7 @@ config SSB_SPROM + config SSB_BLOCKIO + bool + depends on SSB ++ default y + + config SSB_PCIHOST_POSSIBLE + bool +@@ -49,7 +50,7 @@ config SSB_PCIHOST + config SSB_B43_PCI_BRIDGE + bool + depends on SSB_PCIHOST +- default n ++ default y + + config SSB_PCMCIAHOST_POSSIBLE + bool +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -17,6 +17,7 @@ config BCMA + config BCMA_BLOCKIO + bool + depends on BCMA ++ default y + + config BCMA_HOST_PCI_POSSIBLE + bool diff --git a/target/linux/generic/patches-3.18/254-textsearch_kconfig_hacks.patch b/target/linux/generic/patches-3.18/254-textsearch_kconfig_hacks.patch new file mode 100644 index 0000000..3c3b1e1 --- /dev/null +++ b/target/linux/generic/patches-3.18/254-textsearch_kconfig_hacks.patch @@ -0,0 +1,23 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -320,16 +320,16 @@ config BCH_CONST_T + # Textsearch support is select'ed if needed + # + config TEXTSEARCH +- boolean ++ boolean "Textsearch support" + + config TEXTSEARCH_KMP +- tristate ++ tristate "Textsearch KMP" + + config TEXTSEARCH_BM +- tristate ++ tristate "Textsearch BM" + + config TEXTSEARCH_FSM +- tristate ++ tristate "Textsearch FSM" + + config BTREE + boolean diff --git a/target/linux/generic/patches-3.18/255-lib80211_kconfig_hacks.patch b/target/linux/generic/patches-3.18/255-lib80211_kconfig_hacks.patch new file mode 100644 index 0000000..d875235 --- /dev/null +++ b/target/linux/generic/patches-3.18/255-lib80211_kconfig_hacks.patch @@ -0,0 +1,31 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -183,7 +183,7 @@ config CFG80211_WEXT + extensions with cfg80211-based drivers. + + config LIB80211 +- tristate ++ tristate "LIB80211" + default n + help + This options enables a library of common routines used +@@ -192,13 +192,16 @@ config LIB80211 + Drivers should select this themselves if needed. + + config LIB80211_CRYPT_WEP +- tristate ++ tristate "LIB80211_CRYPT_WEP" ++ select LIB80211 + + config LIB80211_CRYPT_CCMP +- tristate ++ tristate "LIB80211_CRYPT_CCMP" ++ select LIB80211 + + config LIB80211_CRYPT_TKIP +- tristate ++ tristate "LIB80211_CRYPT_TKIP" ++ select LIB80211 + + config LIB80211_DEBUG + bool "lib80211 debugging messages" diff --git a/target/linux/generic/patches-3.18/256-crypto_add_kconfig_prompts.patch b/target/linux/generic/patches-3.18/256-crypto_add_kconfig_prompts.patch new file mode 100644 index 0000000..f9f6c0e --- /dev/null +++ b/target/linux/generic/patches-3.18/256-crypto_add_kconfig_prompts.patch @@ -0,0 +1,47 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -32,7 +32,7 @@ config CRYPTO_FIPS + this is. + + config CRYPTO_ALGAPI +- tristate ++ tristate "ALGAPI" + select CRYPTO_ALGAPI2 + help + This option provides the API for cryptographic algorithms. +@@ -41,7 +41,7 @@ config CRYPTO_ALGAPI2 + tristate + + config CRYPTO_AEAD +- tristate ++ tristate "AEAD" + select CRYPTO_AEAD2 + select CRYPTO_ALGAPI + +@@ -50,7 +50,7 @@ config CRYPTO_AEAD2 + select CRYPTO_ALGAPI2 + + config CRYPTO_BLKCIPHER +- tristate ++ tristate "BLKCIPHER" + select CRYPTO_BLKCIPHER2 + select CRYPTO_ALGAPI + +@@ -61,7 +61,7 @@ config CRYPTO_BLKCIPHER2 + select CRYPTO_WORKQUEUE + + config CRYPTO_HASH +- tristate ++ tristate "HASH" + select CRYPTO_HASH2 + select CRYPTO_ALGAPI + +@@ -70,7 +70,7 @@ config CRYPTO_HASH2 + select CRYPTO_ALGAPI2 + + config CRYPTO_RNG +- tristate ++ tristate "RNG" + select CRYPTO_RNG2 + select CRYPTO_ALGAPI + diff --git a/target/linux/generic/patches-3.18/257-wireless_ext_kconfig_hack.patch b/target/linux/generic/patches-3.18/257-wireless_ext_kconfig_hack.patch new file mode 100644 index 0000000..daac589 --- /dev/null +++ b/target/linux/generic/patches-3.18/257-wireless_ext_kconfig_hack.patch @@ -0,0 +1,22 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -1,5 +1,5 @@ + config WIRELESS_EXT +- bool ++ bool "Wireless extensions" + + config WEXT_CORE + def_bool y +@@ -11,10 +11,10 @@ config WEXT_PROC + depends on WEXT_CORE + + config WEXT_SPY +- bool ++ bool "WEXT_SPY" + + config WEXT_PRIV +- bool ++ bool "WEXT_PRIV" + + config CFG80211 + tristate "cfg80211 - wireless configuration API" diff --git a/target/linux/generic/patches-3.18/258-netfilter_netlink_kconfig_hack.patch b/target/linux/generic/patches-3.18/258-netfilter_netlink_kconfig_hack.patch new file mode 100644 index 0000000..9d827c2 --- /dev/null +++ b/target/linux/generic/patches-3.18/258-netfilter_netlink_kconfig_hack.patch @@ -0,0 +1,11 @@ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -2,7 +2,7 @@ menu "Core Netfilter Configuration" + depends on NET && INET && NETFILTER + + config NETFILTER_NETLINK +- tristate ++ tristate "Netfilter NFNETLINK interface" + + config NETFILTER_NETLINK_ACCT + tristate "Netfilter NFACCT over NFNETLINK interface" diff --git a/target/linux/generic/patches-3.18/259-regmap_dynamic.patch b/target/linux/generic/patches-3.18/259-regmap_dynamic.patch new file mode 100644 index 0000000..b1d4ad2 --- /dev/null +++ b/target/linux/generic/patches-3.18/259-regmap_dynamic.patch @@ -0,0 +1,80 @@ +--- a/drivers/base/regmap/Kconfig ++++ b/drivers/base/regmap/Kconfig +@@ -3,26 +3,31 @@ + # subsystems should select the appropriate symbols. + + config REGMAP +- default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_MMIO || REGMAP_IRQ) + select LZO_COMPRESS + select LZO_DECOMPRESS + select IRQ_DOMAIN if REGMAP_IRQ +- bool ++ tristate "Regmap" + + config REGMAP_I2C +- tristate ++ tristate "Regmap I2C" ++ select REGMAP + depends on I2C + + config REGMAP_SPI +- tristate ++ tristate "Regmap SPI" ++ select REGMAP ++ depends on SPI_MASTER + depends on SPI + + config REGMAP_SPMI ++ select REGMAP + tristate + depends on SPMI + + config REGMAP_MMIO +- tristate ++ tristate "Regmap MMIO" ++ select REGMAP + + config REGMAP_IRQ ++ select REGMAP + bool +--- a/include/linux/regmap.h ++++ b/include/linux/regmap.h +@@ -49,7 +49,7 @@ struct reg_default { + unsigned int def; + }; + +-#ifdef CONFIG_REGMAP ++#if IS_ENABLED(CONFIG_REGMAP) + + enum regmap_endian { + /* Unspecified -> 0 -> Backwards compatible default */ +--- a/drivers/base/regmap/Makefile ++++ b/drivers/base/regmap/Makefile +@@ -1,6 +1,8 @@ +-obj-$(CONFIG_REGMAP) += regmap.o regcache.o +-obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-lzo.o regcache-flat.o +-obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o ++regmap-core-objs = regmap.o regcache.o regcache-rbtree.o regcache-lzo.o regcache-flat.o ++ifdef CONFIG_DEBUG_FS ++regmap-core-objs += regmap-debugfs.o ++endif ++obj-$(CONFIG_REGMAP) += regmap-core.o + obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o + obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o + obj-$(CONFIG_REGMAP_SPMI) += regmap-spmi.o +--- a/drivers/base/regmap/regmap.c ++++ b/drivers/base/regmap/regmap.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -2630,3 +2631,5 @@ static int __init regmap_initcall(void) + return 0; + } + postcore_initcall(regmap_initcall); ++ ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-3.18/260-crypto_test_dependencies.patch b/target/linux/generic/patches-3.18/260-crypto_test_dependencies.patch new file mode 100644 index 0000000..8a96fd9 --- /dev/null +++ b/target/linux/generic/patches-3.18/260-crypto_test_dependencies.patch @@ -0,0 +1,37 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -96,10 +96,10 @@ config CRYPTO_MANAGER + + config CRYPTO_MANAGER2 + def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) +- select CRYPTO_AEAD2 +- select CRYPTO_HASH2 +- select CRYPTO_BLKCIPHER2 +- select CRYPTO_PCOMP2 ++ select CRYPTO_AEAD2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_HASH2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_BLKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_PCOMP2 if !CRYPTO_MANAGER_DISABLE_TESTS + + config CRYPTO_USER + tristate "Userspace cryptographic algorithm configuration" +--- a/crypto/algboss.c ++++ b/crypto/algboss.c +@@ -248,6 +248,9 @@ static int cryptomgr_schedule_test(struc + type = alg->cra_flags; + + /* This piece of crap needs to disappear into per-type test hooks. */ ++#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS ++ type |= CRYPTO_ALG_TESTED; ++#else + if ((!((type ^ CRYPTO_ALG_TYPE_BLKCIPHER) & + CRYPTO_ALG_TYPE_BLKCIPHER_MASK) && !(type & CRYPTO_ALG_GENIV) && + ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == +@@ -256,6 +259,7 @@ static int cryptomgr_schedule_test(struc + (!((type ^ CRYPTO_ALG_TYPE_AEAD) & CRYPTO_ALG_TYPE_MASK) && + alg->cra_type == &crypto_nivaead_type && alg->cra_aead.ivsize)) + type |= CRYPTO_ALG_TESTED; ++#endif + + param->type = type; + diff --git a/target/linux/generic/patches-3.18/262-compressor_kconfig_hack.patch b/target/linux/generic/patches-3.18/262-compressor_kconfig_hack.patch new file mode 100644 index 0000000..51b4fc8 --- /dev/null +++ b/target/linux/generic/patches-3.18/262-compressor_kconfig_hack.patch @@ -0,0 +1,35 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -205,25 +205,25 @@ config RANDOM32_SELFTEST + # compression support is select'ed if needed + # + config ZLIB_INFLATE +- tristate ++ tristate "ZLIB inflate support" + + config ZLIB_DEFLATE +- tristate ++ tristate "ZLIB deflate support" + + config LZO_COMPRESS +- tristate ++ tristate "LZO compress support" + + config LZO_DECOMPRESS +- tristate ++ tristate "LZO decompress support" + + config LZ4_COMPRESS +- tristate ++ tristate "LZ4 compress support" + + config LZ4HC_COMPRESS +- tristate ++ tristate "LZ4HC compress support" + + config LZ4_DECOMPRESS +- tristate ++ tristate "LZ4 decompress support" + + source "lib/xz/Kconfig" + diff --git a/target/linux/generic/patches-3.18/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch b/target/linux/generic/patches-3.18/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch new file mode 100644 index 0000000..762f498 --- /dev/null +++ b/target/linux/generic/patches-3.18/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch @@ -0,0 +1,34 @@ +From 8b05e325824d3b38e52a7748b3b5dc34dc1c0f6d Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 14:37:54 +0200 +Subject: [PATCH 1/3] uapi/kernel.h: glibc specific inclusion of sysinfo.h + +including sysinfo.h from kernel.h makes no sense whatsoever, +but removing it breaks glibc's userspace header, +which includes kernel.h instead of sysinfo.h from their sys/sysinfo.h. +this seems to be a historical mistake. +on musl, including any header that uses kernel.h directly or indirectly +plus sys/sysinfo.h will produce a compile error due to redefinition of +struct sysinfo from sys/sysinfo.h. +so for now, only include it on glibc or when including from kernel +in order not to break their headers. + +Signed-off-by: John Spencer +Signed-off-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/kernel.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/include/uapi/linux/kernel.h ++++ b/include/uapi/linux/kernel.h +@@ -1,7 +1,9 @@ + #ifndef _UAPI_LINUX_KERNEL_H + #define _UAPI_LINUX_KERNEL_H + ++#if defined(__KERNEL__) || defined( __GLIBC__) + #include ++#endif + + /* + * 'kernel.h' contains some often-used function prototypes etc diff --git a/target/linux/generic/patches-3.18/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch b/target/linux/generic/patches-3.18/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch new file mode 100644 index 0000000..891299e --- /dev/null +++ b/target/linux/generic/patches-3.18/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch @@ -0,0 +1,81 @@ +From f972afc2509eebcb00d370256c55b112a3b5ffca Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 16:50:40 +0200 +Subject: [PATCH 2/3] uapi/libc-compat.h: do not rely on __GLIBC__ + +Musl provides the same structs as glibc, but does not provide a define to +allow its detection. Since the absence of __GLIBC__ also can mean that it +is included from the kernel, change the __GLIBC__ detection to +!__KERNEL__, which should always be true when included from userspace. + +Signed-off-by: John Spencer +Tested-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/libc-compat.h | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -48,13 +48,13 @@ + #ifndef _UAPI_LIBC_COMPAT_H + #define _UAPI_LIBC_COMPAT_H + +-/* We have included glibc headers... */ +-#if defined(__GLIBC__) ++/* We have included libc headers... */ ++#if !defined(__KERNEL__) + +-/* Coordinate with glibc netinet/in.h header. */ ++/* Coordinate with libc netinet/in.h header. */ + #if defined(_NETINET_IN_H) + +-/* GLIBC headers included first so don't define anything ++/* LIBC headers included first so don't define anything + * that would already be defined. */ + #define __UAPI_DEF_IN_ADDR 0 + #define __UAPI_DEF_IN_IPPROTO 0 +@@ -68,7 +68,7 @@ + * if the glibc code didn't define them. This guard matches + * the guard in glibc/inet/netinet/in.h which defines the + * additional in6_addr macros e.g. s6_addr16, and s6_addr32. */ +-#if defined(__USE_MISC) || defined (__USE_GNU) ++#if !defined(__GLIBC__) || defined(__USE_MISC) || defined (__USE_GNU) + #define __UAPI_DEF_IN6_ADDR_ALT 0 + #else + #define __UAPI_DEF_IN6_ADDR_ALT 1 +@@ -81,7 +81,7 @@ + #else + + /* Linux headers included first, and we must define everything +- * we need. The expectation is that glibc will check the ++ * we need. The expectation is that the libc will check the + * __UAPI_DEF_* defines and adjust appropriately. */ + #define __UAPI_DEF_IN_ADDR 1 + #define __UAPI_DEF_IN_IPPROTO 1 +@@ -91,7 +91,7 @@ + #define __UAPI_DEF_IN_CLASS 1 + + #define __UAPI_DEF_IN6_ADDR 1 +-/* We unconditionally define the in6_addr macros and glibc must ++/* We unconditionally define the in6_addr macros and the libc must + * coordinate. */ + #define __UAPI_DEF_IN6_ADDR_ALT 1 + #define __UAPI_DEF_SOCKADDR_IN6 1 +@@ -111,7 +111,7 @@ + /* If we did not see any headers from any supported C libraries, + * or we are being included in the kernel, then define everything + * that we need. */ +-#else /* !defined(__GLIBC__) */ ++#else /* defined(__KERNEL__) */ + + /* Definitions for in.h */ + #define __UAPI_DEF_IN_ADDR 1 +@@ -132,6 +132,6 @@ + /* Definitions for xattr.h */ + #define __UAPI_DEF_XATTR 1 + +-#endif /* __GLIBC__ */ ++#endif /* __KERNEL__ */ + + #endif /* _UAPI_LIBC_COMPAT_H */ diff --git a/target/linux/generic/patches-3.18/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch b/target/linux/generic/patches-3.18/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch new file mode 100644 index 0000000..feea4c3 --- /dev/null +++ b/target/linux/generic/patches-3.18/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch @@ -0,0 +1,67 @@ +From fcbb6fed85ea9ff4feb4f1ebd4f0f235fdaf06b6 Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 16:53:03 +0200 +Subject: [PATCH 3/3] uapi/if_ether.h: prevent redefinition of struct ethhdr + +Musl provides its own ethhdr struct definition. Add a guard to prevent +its definition of the appropriate musl header has already been included. + +Signed-off-by: John Spencer +Tested-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/if_ether.h | 3 +++ + include/uapi/linux/libc-compat.h | 11 +++++++++++ + 2 files changed, 14 insertions(+) + +--- a/include/uapi/linux/if_ether.h ++++ b/include/uapi/linux/if_ether.h +@@ -22,6 +22,7 @@ + #define _UAPI_LINUX_IF_ETHER_H + + #include ++#include + + /* + * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble +@@ -134,11 +135,13 @@ + * This is an Ethernet frame header. + */ + ++#if __UAPI_DEF_ETHHDR + struct ethhdr { + unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ + unsigned char h_source[ETH_ALEN]; /* source ether addr */ + __be16 h_proto; /* packet type ID field */ + } __attribute__((packed)); ++#endif + + + #endif /* _UAPI_LINUX_IF_ETHER_H */ +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -51,6 +51,14 @@ + /* We have included libc headers... */ + #if !defined(__KERNEL__) + ++/* musl defines the ethhdr struct itself in its netinet/if_ether.h. ++ * Glibc just includes the kernel header and uses a different guard. */ ++#if defined(_NETINET_IF_ETHER_H) ++#define __UAPI_DEF_ETHHDR 0 ++#else ++#define __UAPI_DEF_ETHHDR 1 ++#endif ++ + /* Coordinate with libc netinet/in.h header. */ + #if defined(_NETINET_IN_H) + +@@ -113,6 +121,9 @@ + * that we need. */ + #else /* defined(__KERNEL__) */ + ++/* Definitions for if_ether.h */ ++#define __UAPI_DEF_ETHHDR 1 ++ + /* Definitions for in.h */ + #define __UAPI_DEF_IN_ADDR 1 + #define __UAPI_DEF_IN_IPPROTO 1 diff --git a/target/linux/generic/patches-3.18/300-mips_expose_boot_raw.patch b/target/linux/generic/patches-3.18/300-mips_expose_boot_raw.patch new file mode 100644 index 0000000..69d61f2 --- /dev/null +++ b/target/linux/generic/patches-3.18/300-mips_expose_boot_raw.patch @@ -0,0 +1,39 @@ +From: Mark Miller + +This exposes the CONFIG_BOOT_RAW symbol in Kconfig. This is needed on +certain Broadcom chipsets running CFE in order to load the kernel. + +Signed-off-by: Mark Miller +Acked-by: Rob Landley +--- +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -892,9 +892,6 @@ config FW_ARC + config ARCH_MAY_HAVE_PC_FDC + bool + +-config BOOT_RAW +- bool +- + config CEVT_BCM1480 + bool + +@@ -2503,6 +2500,18 @@ config USE_OF + config BUILTIN_DTB + bool + ++config BOOT_RAW ++ bool "Enable the kernel to be executed from the load address" ++ default n ++ help ++ Allow the kernel to be executed from the load address for ++ bootloaders which cannot read the ELF format. This places ++ a jump to start_kernel at the load address. ++ ++ If unsure, say N. ++ ++ ++ + endmenu + + config LOCKDEP_SUPPORT diff --git a/target/linux/generic/patches-3.18/301-mips_image_cmdline_hack.patch b/target/linux/generic/patches-3.18/301-mips_image_cmdline_hack.patch new file mode 100644 index 0000000..c87d448 --- /dev/null +++ b/target/linux/generic/patches-3.18/301-mips_image_cmdline_hack.patch @@ -0,0 +1,28 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -988,6 +988,10 @@ config SYNC_R4K + config MIPS_MACHINE + def_bool n + ++config IMAGE_CMDLINE_HACK ++ bool "OpenWrt specific image command line hack" ++ default n ++ + config NO_IOPORT_MAP + def_bool n + +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -80,6 +80,12 @@ FEXPORT(__kernel_entry) + j kernel_entry + #endif + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++ .ascii "CMDLINE:" ++EXPORT(__image_cmdline) ++ .fill 0x400 ++#endif /* CONFIG_IMAGE_CMDLINE_HACK */ ++ + __REF + + NESTED(kernel_entry, 16, sp) # kernel entry point diff --git a/target/linux/generic/patches-3.18/302-mips_no_branch_likely.patch b/target/linux/generic/patches-3.18/302-mips_no_branch_likely.patch new file mode 100644 index 0000000..44c6b04 --- /dev/null +++ b/target/linux/generic/patches-3.18/302-mips_no_branch_likely.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -87,7 +87,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + # machines may also. Since BFD is incredibly buggy with respect to + # crossformat linking we rely on the elf2ecoff tool for format conversion. + # +-cflags-y += -G 0 -mno-abicalls -fno-pic -pipe ++cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely + cflags-y += -msoft-float + LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections + KBUILD_AFLAGS_MODULE += -mlong-calls diff --git a/target/linux/generic/patches-3.18/304-mips_disable_fpu.patch b/target/linux/generic/patches-3.18/304-mips_disable_fpu.patch new file mode 100644 index 0000000..779e20a --- /dev/null +++ b/target/linux/generic/patches-3.18/304-mips_disable_fpu.patch @@ -0,0 +1,105 @@ +From: Manuel Lauss +Subject: [RFC PATCH v4 2/2] MIPS: make FPU emulator optional +Date: Mon, 7 Apr 2014 12:57:04 +0200 +Message-Id: <1396868224-252888-2-git-send-email-manuel.lauss@gmail.com> + +This small patch makes the MIPS FPU emulator optional. The kernel +kills float-users on systems without a hardware FPU by sending a SIGILL. + +Disabling the emulator shrinks vmlinux by about 54kBytes (32bit, +optimizing for size). + +Signed-off-by: Manuel Lauss +--- +v4: rediffed because of patch 1/2, should now work with micromips as well +v3: updated patch description with size savings. +v2: incorporated changes suggested by Jonas Gorski + force the fpu emulator on for micromips: relocating the parts + of the mmips code in the emulator to other areas would be a + much larger change; I went the cheap route instead with this. + + arch/mips/Kbuild | 2 +- + arch/mips/Kconfig | 14 ++++++++++++++ + arch/mips/include/asm/fpu.h | 5 +++-- + arch/mips/include/asm/fpu_emulator.h | 15 +++++++++++++++ + 4 files changed, 33 insertions(+), 3 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2495,6 +2495,20 @@ config MIPS_O32_FP64_SUPPORT + + If unsure, say N. + ++config MIPS_FPU_EMULATOR ++ bool "MIPS FPU Emulator" ++ default y ++ help ++ This option lets you disable the built-in MIPS FPU (Coprocessor 1) ++ emulator, which handles floating-point instructions on processors ++ without a hardware FPU. It is generally a good idea to keep the ++ emulator built-in, unless you are perfectly sure you have a ++ complete soft-float environment. With the emulator disabled, all ++ users of float operations will be killed with an illegal instr- ++ uction exception. ++ ++ Say Y, please. ++ + config USE_OF + bool + select OF +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -275,7 +275,7 @@ OBJCOPYFLAGS += --remove-section=.regin + head-y := arch/mips/kernel/head.o + + libs-y += arch/mips/lib/ +-libs-y += arch/mips/math-emu/ ++libs-$(CONFIG_MIPS_FPU_EMULATOR) += arch/mips/math-emu/ + + # See arch/mips/Kbuild for content of core part of the kernel + core-y += arch/mips/ +--- a/arch/mips/include/asm/fpu.h ++++ b/arch/mips/include/asm/fpu.h +@@ -169,8 +169,10 @@ static inline int init_fpu(void) + ret = __own_fpu(); + if (!ret) + _init_fpu(); +- } else ++ } else if (IS_ENABLED(CONFIG_MIPS_FPU_EMULATOR)) + fpu_emulator_init_fpu(); ++ else ++ ret = SIGILL; + + return ret; + } +--- a/arch/mips/include/asm/fpu_emulator.h ++++ b/arch/mips/include/asm/fpu_emulator.h +@@ -30,6 +30,7 @@ + #include + #include + ++#ifdef CONFIG_MIPS_FPU_EMULATOR + #ifdef CONFIG_DEBUG_FS + + struct mips_fpu_emulator_stats { +@@ -65,6 +66,20 @@ extern int do_dsemulret(struct pt_regs * + extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, + struct mips_fpu_struct *ctx, int has_fpu, + void *__user *fault_addr); ++#else /* no CONFIG_MIPS_FPU_EMULATOR */ ++static inline int do_dsemulret(struct pt_regs *xcp) ++{ ++ return 0; /* 0 means error, should never get here anyway */ ++} ++ ++static inline int fpu_emulator_cop1Handler(struct pt_regs *xcp, ++ struct mips_fpu_struct *ctx, int has_fpu, ++ void *__user *fault_addr) ++{ ++ return SIGILL; /* we don't speak MIPS FPU */ ++} ++#endif /* CONFIG_MIPS_FPU_EMULATOR */ ++ + int process_fpemu_return(int sig, void __user *fault_addr); + int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, + unsigned long *contpc); diff --git a/target/linux/generic/patches-3.18/305-mips_module_reloc.patch b/target/linux/generic/patches-3.18/305-mips_module_reloc.patch new file mode 100644 index 0000000..f8ca914 --- /dev/null +++ b/target/linux/generic/patches-3.18/305-mips_module_reloc.patch @@ -0,0 +1,353 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -90,8 +90,13 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely + cflags-y += -msoft-float + LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections ++ifdef CONFIG_64BIT + KBUILD_AFLAGS_MODULE += -mlong-calls + KBUILD_CFLAGS_MODULE += -mlong-calls ++else ++KBUILD_AFLAGS_MODULE += -mno-long-calls ++KBUILD_CFLAGS_MODULE += -mno-long-calls ++endif + + ifndef CONFIG_FUNCTION_TRACER + KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections +--- a/arch/mips/include/asm/module.h ++++ b/arch/mips/include/asm/module.h +@@ -11,6 +11,11 @@ struct mod_arch_specific { + const struct exception_table_entry *dbe_start; + const struct exception_table_entry *dbe_end; + struct mips_hi16 *r_mips_hi16_list; ++ ++ void *phys_plt_tbl; ++ void *virt_plt_tbl; ++ unsigned int phys_plt_offset; ++ unsigned int virt_plt_offset; + }; + + typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ +--- a/arch/mips/kernel/module.c ++++ b/arch/mips/kernel/module.c +@@ -43,14 +43,222 @@ struct mips_hi16 { + static LIST_HEAD(dbe_list); + static DEFINE_SPINLOCK(dbe_lock); + +-#ifdef MODULE_START ++/* ++ * Get the potential max trampolines size required of the init and ++ * non-init sections. Only used if we cannot find enough contiguous ++ * physically mapped memory to put the module into. ++ */ ++static unsigned int ++get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, ++ const char *secstrings, unsigned int symindex, bool is_init) ++{ ++ unsigned long ret = 0; ++ unsigned int i, j; ++ Elf_Sym *syms; ++ ++ /* Everything marked ALLOC (this includes the exported symbols) */ ++ for (i = 1; i < hdr->e_shnum; ++i) { ++ unsigned int info = sechdrs[i].sh_info; ++ ++ if (sechdrs[i].sh_type != SHT_REL ++ && sechdrs[i].sh_type != SHT_RELA) ++ continue; ++ ++ /* Not a valid relocation section? */ ++ if (info >= hdr->e_shnum) ++ continue; ++ ++ /* Don't bother with non-allocated sections */ ++ if (!(sechdrs[info].sh_flags & SHF_ALLOC)) ++ continue; ++ ++ /* If it's called *.init*, and we're not init, we're ++ not interested */ ++ if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0) ++ != is_init) ++ continue; ++ ++ syms = (Elf_Sym *) sechdrs[symindex].sh_addr; ++ if (sechdrs[i].sh_type == SHT_REL) { ++ Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr; ++ unsigned int size = sechdrs[i].sh_size / sizeof(*rel); ++ ++ for (j = 0; j < size; ++j) { ++ Elf_Sym *sym; ++ ++ if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26) ++ continue; ++ ++ sym = syms + ELF_MIPS_R_SYM(rel[j]); ++ if (!is_init && sym->st_shndx != SHN_UNDEF) ++ continue; ++ ++ ret += 4 * sizeof(int); ++ } ++ } else { ++ Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr; ++ unsigned int size = sechdrs[i].sh_size / sizeof(*rela); ++ ++ for (j = 0; j < size; ++j) { ++ Elf_Sym *sym; ++ ++ if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26) ++ continue; ++ ++ sym = syms + ELF_MIPS_R_SYM(rela[j]); ++ if (!is_init && sym->st_shndx != SHN_UNDEF) ++ continue; ++ ++ ret += 4 * sizeof(int); ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++#ifndef MODULE_START ++static void *alloc_phys(unsigned long size) ++{ ++ unsigned order; ++ struct page *page; ++ struct page *p; ++ ++ size = PAGE_ALIGN(size); ++ order = get_order(size); ++ ++ page = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN | ++ __GFP_THISNODE, order); ++ if (!page) ++ return NULL; ++ ++ split_page(page, order); ++ ++ for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p) ++ __free_page(p); ++ ++ return page_address(page); ++} ++#endif ++ ++static void free_phys(void *ptr, unsigned long size) ++{ ++ struct page *page; ++ struct page *end; ++ ++ page = virt_to_page(ptr); ++ end = page + (PAGE_ALIGN(size) >> PAGE_SHIFT); ++ ++ for (; page < end; ++page) ++ __free_page(page); ++} ++ ++ + void *module_alloc(unsigned long size) + { ++#ifdef MODULE_START + return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, + GFP_KERNEL, PAGE_KERNEL, NUMA_NO_NODE, + __builtin_return_address(0)); ++#else ++ void *ptr; ++ ++ if (size == 0) ++ return NULL; ++ ++ ptr = alloc_phys(size); ++ ++ /* If we failed to allocate physically contiguous memory, ++ * fall back to regular vmalloc. The module loader code will ++ * create jump tables to handle long jumps */ ++ if (!ptr) ++ return vmalloc(size); ++ ++ return ptr; ++#endif + } ++ ++static inline bool is_phys_addr(void *ptr) ++{ ++#ifdef CONFIG_64BIT ++ return (KSEGX((unsigned long)ptr) == CKSEG0); ++#else ++ return (KSEGX(ptr) == KSEG0); + #endif ++} ++ ++/* Free memory returned from module_alloc */ ++void module_free(struct module *mod, void *module_region) ++{ ++ if (is_phys_addr(module_region)) { ++ if (mod->module_init == module_region) ++ free_phys(module_region, mod->init_size); ++ else if (mod->module_core == module_region) ++ free_phys(module_region, mod->core_size); ++ else ++ BUG(); ++ } else { ++ vfree(module_region); ++ } ++} ++ ++static void *__module_alloc(int size, bool phys) ++{ ++ void *ptr; ++ ++ if (phys) ++ ptr = kmalloc(size, GFP_KERNEL); ++ else ++ ptr = vmalloc(size); ++ return ptr; ++} ++ ++static void __module_free(void *ptr) ++{ ++ if (is_phys_addr(ptr)) ++ kfree(ptr); ++ else ++ vfree(ptr); ++} ++ ++int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, ++ char *secstrings, struct module *mod) ++{ ++ unsigned int symindex = 0; ++ unsigned int core_size, init_size; ++ int i; ++ ++ mod->arch.phys_plt_offset = 0; ++ mod->arch.virt_plt_offset = 0; ++ mod->arch.phys_plt_tbl = NULL; ++ mod->arch.virt_plt_tbl = NULL; ++ ++ if (IS_ENABLED(CONFIG_64BIT)) ++ return 0; ++ ++ for (i = 1; i < hdr->e_shnum; i++) ++ if (sechdrs[i].sh_type == SHT_SYMTAB) ++ symindex = i; ++ ++ core_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false); ++ init_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true); ++ ++ if ((core_size + init_size) == 0) ++ return 0; ++ ++ mod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1); ++ if (!mod->arch.phys_plt_tbl) ++ return -ENOMEM; ++ ++ mod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0); ++ if (!mod->arch.virt_plt_tbl) { ++ __module_free(mod->arch.phys_plt_tbl); ++ mod->arch.phys_plt_tbl = NULL; ++ return -ENOMEM; ++ } ++ ++ return 0; ++} + + int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v) + { +@@ -64,8 +272,39 @@ static int apply_r_mips_32_rel(struct mo + return 0; + } + ++static Elf_Addr add_plt_entry_to(unsigned *plt_offset, ++ void *start, Elf_Addr v) ++{ ++ unsigned *tramp = start + *plt_offset; ++ *plt_offset += 4 * sizeof(int); ++ ++ /* adjust carry for addiu */ ++ if (v & 0x00008000) ++ v += 0x10000; ++ ++ tramp[0] = 0x3c190000 | (v >> 16); /* lui t9, hi16 */ ++ tramp[1] = 0x27390000 | (v & 0xffff); /* addiu t9, t9, lo16 */ ++ tramp[2] = 0x03200008; /* jr t9 */ ++ tramp[3] = 0x00000000; /* nop */ ++ ++ return (Elf_Addr) tramp; ++} ++ ++static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v) ++{ ++ if (is_phys_addr(location)) ++ return add_plt_entry_to(&me->arch.phys_plt_offset, ++ me->arch.phys_plt_tbl, v); ++ else ++ return add_plt_entry_to(&me->arch.virt_plt_offset, ++ me->arch.virt_plt_tbl, v); ++ ++} ++ + static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v) + { ++ u32 ofs = *location & 0x03ffffff; ++ + if (v % 4) { + pr_err("module %s: dangerous R_MIPS_26 REL relocation\n", + me->name); +@@ -73,14 +312,17 @@ static int apply_r_mips_26_rel(struct mo + } + + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { +- printk(KERN_ERR +- "module %s: relocation overflow\n", +- me->name); +- return -ENOEXEC; ++ v = add_plt_entry(me, location, v + (ofs << 2)); ++ if (!v) { ++ printk(KERN_ERR ++ "module %s: relocation overflow\n", me->name); ++ return -ENOEXEC; ++ } ++ ofs = 0; + } + + *location = (*location & ~0x03ffffff) | +- ((*location + (v >> 2)) & 0x03ffffff); ++ ((ofs + (v >> 2)) & 0x03ffffff); + + return 0; + } +@@ -287,9 +529,33 @@ int module_finalize(const Elf_Ehdr *hdr, + list_add(&me->arch.dbe_list, &dbe_list); + spin_unlock_irq(&dbe_lock); + } ++ ++ /* Get rid of the fixup trampoline if we're running the module ++ * from physically mapped address space */ ++ if (me->arch.phys_plt_offset == 0) { ++ __module_free(me->arch.phys_plt_tbl); ++ me->arch.phys_plt_tbl = NULL; ++ } ++ if (me->arch.virt_plt_offset == 0) { ++ __module_free(me->arch.virt_plt_tbl); ++ me->arch.virt_plt_tbl = NULL; ++ } ++ + return 0; + } + ++void module_arch_freeing_init(struct module *mod) ++{ ++ if (mod->arch.phys_plt_tbl) { ++ __module_free(mod->arch.phys_plt_tbl); ++ mod->arch.phys_plt_tbl = NULL; ++ } ++ if (mod->arch.virt_plt_tbl) { ++ __module_free(mod->arch.virt_plt_tbl); ++ mod->arch.virt_plt_tbl = NULL; ++ } ++} ++ + void module_arch_cleanup(struct module *mod) + { + spin_lock_irq(&dbe_lock); diff --git a/target/linux/generic/patches-3.18/306-mips_mem_functions_performance.patch b/target/linux/generic/patches-3.18/306-mips_mem_functions_performance.patch new file mode 100644 index 0000000..9818677 --- /dev/null +++ b/target/linux/generic/patches-3.18/306-mips_mem_functions_performance.patch @@ -0,0 +1,83 @@ +--- a/arch/mips/include/asm/string.h ++++ b/arch/mips/include/asm/string.h +@@ -133,11 +133,44 @@ strncmp(__const__ char *__cs, __const__ + + #define __HAVE_ARCH_MEMSET + extern void *memset(void *__s, int __c, size_t __count); ++#define memset(__s, __c, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memset((__s), (__c), __len); \ ++ else \ ++ __ret = __builtin_memset((__s), (__c), __len); \ ++ __ret; \ ++}) + + #define __HAVE_ARCH_MEMCPY + extern void *memcpy(void *__to, __const__ void *__from, size_t __n); ++#define memcpy(dst, src, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memcpy((dst), (src), __len); \ ++ else \ ++ __ret = __builtin_memcpy((dst), (src), __len); \ ++ __ret; \ ++}) + + #define __HAVE_ARCH_MEMMOVE + extern void *memmove(void *__dest, __const__ void *__src, size_t __n); ++#define memmove(dst, src, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memmove((dst), (src), __len); \ ++ else \ ++ __ret = __builtin_memmove((dst), (src), __len); \ ++ __ret; \ ++}) ++ ++#define __HAVE_ARCH_MEMCMP ++#define memcmp(src1, src2, len) __builtin_memcmp((src1), (src2), (len)) + + #endif /* _ASM_STRING_H */ +--- a/arch/mips/lib/Makefile ++++ b/arch/mips/lib/Makefile +@@ -4,7 +4,7 @@ + + lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ + mips-atomic.o strlen_user.o strncpy_user.o \ +- strnlen_user.o uncached.o ++ strnlen_user.o uncached.o memcmp.o + + obj-y += iomap.o + obj-$(CONFIG_PCI) += iomap-pci.o +--- /dev/null ++++ b/arch/mips/lib/memcmp.c +@@ -0,0 +1,22 @@ ++/* ++ * copied from linux/lib/string.c ++ * ++ * Copyright (C) 1991, 1992 Linus Torvalds ++ */ ++ ++#include ++#include ++ ++#undef memcmp ++int memcmp(const void *cs, const void *ct, size_t count) ++{ ++ const unsigned char *su1, *su2; ++ int res = 0; ++ ++ for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) ++ if ((res = *su1 - *su2) != 0) ++ break; ++ return res; ++} ++EXPORT_SYMBOL(memcmp); ++ diff --git a/target/linux/generic/patches-3.18/307-mips_highmem_offset.patch b/target/linux/generic/patches-3.18/307-mips_highmem_offset.patch new file mode 100644 index 0000000..c9f0c84 --- /dev/null +++ b/target/linux/generic/patches-3.18/307-mips_highmem_offset.patch @@ -0,0 +1,17 @@ +Adjust highmem offset to 0x10000000 to ensure that all kmalloc allocations +stay within the same 256M boundary. This ensures that -mlong-calls is not +needed on systems with more than 256M RAM. + +Signed-off-by: Felix Fietkau +--- +--- a/arch/mips/include/asm/mach-generic/spaces.h ++++ b/arch/mips/include/asm/mach-generic/spaces.h +@@ -44,7 +44,7 @@ + * Memory above this physical address will be considered highmem. + */ + #ifndef HIGHMEM_START +-#define HIGHMEM_START _AC(0x20000000, UL) ++#define HIGHMEM_START _AC(0x10000000, UL) + #endif + + #endif /* CONFIG_32BIT */ diff --git a/target/linux/generic/patches-3.18/309-mips_fuse_workaround.patch b/target/linux/generic/patches-3.18/309-mips_fuse_workaround.patch new file mode 100644 index 0000000..934b119 --- /dev/null +++ b/target/linux/generic/patches-3.18/309-mips_fuse_workaround.patch @@ -0,0 +1,32 @@ +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -38,6 +38,7 @@ void (*__flush_cache_vunmap)(void); + + void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size); + EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); ++EXPORT_SYMBOL(__flush_cache_all); + void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size); + + /* MIPS specific cache operations */ +--- a/fs/fuse/dev.c ++++ b/fs/fuse/dev.c +@@ -20,6 +20,9 @@ + #include + #include + #include ++#ifdef CONFIG_MIPS ++#include ++#endif + + MODULE_ALIAS_MISCDEV(FUSE_MINOR); + MODULE_ALIAS("devname:fuse"); +@@ -749,6 +752,9 @@ static int fuse_copy_fill(struct fuse_co + static int fuse_copy_do(struct fuse_copy_state *cs, void **val, unsigned *size) + { + unsigned ncpy = min(*size, cs->len); ++#ifdef CONFIG_MIPS ++ __flush_cache_all(); ++#endif + if (val) { + void *pgaddr = kmap_atomic(cs->pg); + void *buf = pgaddr + cs->offset; diff --git a/target/linux/generic/patches-3.18/310-arm_module_unresolved_weak_sym.patch b/target/linux/generic/patches-3.18/310-arm_module_unresolved_weak_sym.patch new file mode 100644 index 0000000..9210c1d --- /dev/null +++ b/target/linux/generic/patches-3.18/310-arm_module_unresolved_weak_sym.patch @@ -0,0 +1,13 @@ +--- a/arch/arm/kernel/module.c ++++ b/arch/arm/kernel/module.c +@@ -83,6 +83,10 @@ apply_relocate(Elf32_Shdr *sechdrs, cons + return -ENOEXEC; + } + ++ if ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) && ++ ELF_ST_BIND(sym->st_info) == STB_WEAK) ++ continue; ++ + loc = dstsec->sh_addr + rel->r_offset; + + switch (ELF32_R_TYPE(rel->r_info)) { diff --git a/target/linux/generic/patches-3.18/320-ppc4xx_optimization.patch b/target/linux/generic/patches-3.18/320-ppc4xx_optimization.patch new file mode 100644 index 0000000..8673de4 --- /dev/null +++ b/target/linux/generic/patches-3.18/320-ppc4xx_optimization.patch @@ -0,0 +1,31 @@ +Upstream doesn't optimize the kernel and bootwrappers for ppc44x because +they still want to support gcc 3.3 -- well, we don't. + +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -203,7 +203,8 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) + KBUILD_CFLAGS += -mno-sched-epilog + endif + +-cpu-as-$(CONFIG_4xx) += -Wa,-m405 ++cpu-as-$(CONFIG_40x) += -Wa,-m405 ++cpu-as-$(CONFIG_44x) += -Wa,-m440 + cpu-as-$(CONFIG_ALTIVEC) += -Wa,-maltivec + cpu-as-$(CONFIG_E200) += -Wa,-me200 + +--- a/arch/powerpc/boot/Makefile ++++ b/arch/powerpc/boot/Makefile +@@ -45,10 +45,10 @@ BOOTCFLAGS += -I$(obj) -I$(srctree)/$(ob + DTC_FLAGS ?= -p 1024 + + $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 ++$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440 + $(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 ++$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=440 ++$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440 + $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 + $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 + $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405 diff --git a/target/linux/generic/patches-3.18/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/patches-3.18/321-powerpc_crtsavres_prereq.patch new file mode 100644 index 0000000..ab6ea7b --- /dev/null +++ b/target/linux/generic/patches-3.18/321-powerpc_crtsavres_prereq.patch @@ -0,0 +1,10 @@ +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -165,7 +165,6 @@ CPP = $(CC) -E $(KBUILD_CFLAGS) + + CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__ + +-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o + + ifeq ($(CONFIG_476FPE_ERR46),y) + KBUILD_LDFLAGS_MODULE += --ppc476-workaround \ diff --git a/target/linux/generic/patches-3.18/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch b/target/linux/generic/patches-3.18/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch new file mode 100644 index 0000000..a69d197 --- /dev/null +++ b/target/linux/generic/patches-3.18/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch @@ -0,0 +1,298 @@ +From d8582dcf1ed66eee88a11e4760f42c0d6c8822be Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 31 Jan 2015 22:26:03 +0800 +Subject: [PATCH 331/331] MIPS: kexec: Accept command line parameters from + userspace. + +Signed-off-by: Yousong Zhou +--- + arch/mips/kernel/machine_kexec.c | 153 +++++++++++++++++++++++++++++++----- + arch/mips/kernel/machine_kexec.h | 20 +++++ + arch/mips/kernel/relocate_kernel.S | 21 +++-- + 3 files changed, 167 insertions(+), 27 deletions(-) + create mode 100644 arch/mips/kernel/machine_kexec.h + +--- a/arch/mips/kernel/machine_kexec.c ++++ b/arch/mips/kernel/machine_kexec.c +@@ -10,45 +10,145 @@ + #include + #include + ++#include + #include + #include +- +-extern const unsigned char relocate_new_kernel[]; +-extern const size_t relocate_new_kernel_size; +- +-extern unsigned long kexec_start_address; +-extern unsigned long kexec_indirection_page; ++#include ++#include "machine_kexec.h" + + int (*_machine_kexec_prepare)(struct kimage *) = NULL; + void (*_machine_kexec_shutdown)(void) = NULL; + void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL; ++ + #ifdef CONFIG_SMP + void (*relocated_kexec_smp_wait) (void *); + atomic_t kexec_ready_to_reboot = ATOMIC_INIT(0); + #endif + +-int +-machine_kexec_prepare(struct kimage *kimage) ++static void machine_kexec_print_args(void) + { ++ unsigned long argc = (int)kexec_args[0]; ++ int i; ++ ++ pr_info("kexec_args[0] (argc): %lu\n", argc); ++ pr_info("kexec_args[1] (argv): %p\n", (void *)kexec_args[1]); ++ pr_info("kexec_args[2] (env ): %p\n", (void *)kexec_args[2]); ++ pr_info("kexec_args[3] (desc): %p\n", (void *)kexec_args[3]); ++ ++ for (i = 0; i < argc; i++) { ++ pr_info("kexec_argv[%d] = %p, %s\n", ++ i, kexec_argv[i], kexec_argv[i]); ++ } ++} ++ ++static void machine_kexec_init_argv(struct kimage *image) ++{ ++ void __user *buf = NULL; ++ size_t bufsz; ++ size_t size; ++ int i; ++ ++ bufsz = 0; ++ for (i = 0; i < image->nr_segments; i++) { ++ struct kexec_segment *seg; ++ ++ seg = &image->segment[i]; ++ if (seg->bufsz < 6) ++ continue; ++ ++ if (strncmp((char *) seg->buf, "kexec ", 6)) ++ continue; ++ ++ buf = seg->buf; ++ bufsz = seg->bufsz; ++ break; ++ } ++ ++ if (!buf) ++ return; ++ ++ size = KEXEC_COMMAND_LINE_SIZE; ++ size = min(size, bufsz); ++ if (size < bufsz) ++ pr_warn("kexec command line truncated to %zd bytes\n", size); ++ ++ /* Copy to kernel space */ ++ copy_from_user(kexec_argv_buf, buf, size); ++ kexec_argv_buf[size - 1] = 0; ++} ++ ++static void machine_kexec_parse_argv(struct kimage *image) ++{ ++ char *reboot_code_buffer; ++ int reloc_delta; ++ char *ptr; ++ int argc; ++ int i; ++ ++ ptr = kexec_argv_buf; ++ argc = 0; ++ ++ /* ++ * convert command line string to array of parameters ++ * (as bootloader does). ++ */ ++ while (ptr && *ptr && (KEXEC_MAX_ARGC > argc)) { ++ if (*ptr == ' ') { ++ *ptr++ = '\0'; ++ continue; ++ } ++ ++ kexec_argv[argc++] = ptr; ++ ptr = strchr(ptr, ' '); ++ } ++ ++ if (!argc) ++ return; ++ ++ kexec_args[0] = argc; ++ kexec_args[1] = (unsigned long)kexec_argv; ++ kexec_args[2] = 0; ++ kexec_args[3] = 0; ++ ++ reboot_code_buffer = page_address(image->control_code_page); ++ reloc_delta = reboot_code_buffer - (char *)kexec_relocate_new_kernel; ++ ++ kexec_args[1] += reloc_delta; ++ for (i = 0; i < argc; i++) ++ kexec_argv[i] += reloc_delta; ++} ++ ++int machine_kexec_prepare(struct kimage *kimage) ++{ ++ /* ++ * Whenever arguments passed from kexec-tools, Init the arguments as ++ * the original ones to try avoiding booting failure. ++ */ ++ ++ kexec_args[0] = fw_arg0; ++ kexec_args[1] = fw_arg1; ++ kexec_args[2] = fw_arg2; ++ kexec_args[3] = fw_arg3; ++ ++ machine_kexec_init_argv(kimage); ++ machine_kexec_parse_argv(kimage); ++ + if (_machine_kexec_prepare) + return _machine_kexec_prepare(kimage); + return 0; + } + +-void +-machine_kexec_cleanup(struct kimage *kimage) ++void machine_kexec_cleanup(struct kimage *kimage) + { + } + +-void +-machine_shutdown(void) ++void machine_shutdown(void) + { + if (_machine_kexec_shutdown) + _machine_kexec_shutdown(); + } + +-void +-machine_crash_shutdown(struct pt_regs *regs) ++void machine_crash_shutdown(struct pt_regs *regs) + { + if (_machine_crash_shutdown) + _machine_crash_shutdown(regs); +@@ -66,10 +166,12 @@ machine_kexec(struct kimage *image) + unsigned long *ptr; + + reboot_code_buffer = +- (unsigned long)page_address(image->control_code_page); ++ (unsigned long)page_address(image->control_code_page); ++ pr_info("reboot_code_buffer = %p\n", (void *)reboot_code_buffer); + + kexec_start_address = + (unsigned long) phys_to_virt(image->start); ++ pr_info("kexec_start_address = %p\n", (void *)kexec_start_address); + + if (image->type == KEXEC_TYPE_DEFAULT) { + kexec_indirection_page = +@@ -77,9 +179,19 @@ machine_kexec(struct kimage *image) + } else { + kexec_indirection_page = (unsigned long)&image->head; + } ++ pr_info("kexec_indirection_page = %p\n", (void *)kexec_indirection_page); + +- memcpy((void*)reboot_code_buffer, relocate_new_kernel, +- relocate_new_kernel_size); ++ pr_info("Where is memcpy: %p\n", memcpy); ++ pr_info("kexec_relocate_new_kernel = %p, kexec_relocate_new_kernel_end = %p\n", ++ (void *)kexec_relocate_new_kernel, &kexec_relocate_new_kernel_end); ++ pr_info("Copy %lu bytes from %p to %p\n", KEXEC_RELOCATE_NEW_KERNEL_SIZE, ++ (void *)kexec_relocate_new_kernel, (void *)reboot_code_buffer); ++ memcpy((void*)reboot_code_buffer, kexec_relocate_new_kernel, ++ KEXEC_RELOCATE_NEW_KERNEL_SIZE); ++ ++ pr_info("Before _print_args().\n"); ++ machine_kexec_print_args(); ++ pr_info("Before eval loop.\n"); + + /* + * The generic kexec code builds a page list with physical +@@ -98,15 +210,16 @@ machine_kexec(struct kimage *image) + /* + * we do not want to be bothered. + */ ++ pr_info("Before irq_disable.\n"); + local_irq_disable(); + +- printk("Will call new kernel at %08lx\n", image->start); +- printk("Bye ...\n"); ++ pr_info("Will call new kernel at %08lx\n", image->start); ++ pr_info("Bye ...\n"); + __flush_cache_all(); + #ifdef CONFIG_SMP + /* All secondary cpus now may jump to kexec_wait cycle */ + relocated_kexec_smp_wait = reboot_code_buffer + +- (void *)(kexec_smp_wait - relocate_new_kernel); ++ (void *)(kexec_smp_wait - kexec_relocate_new_kernel); + smp_wmb(); + atomic_set(&kexec_ready_to_reboot, 1); + #endif +--- /dev/null ++++ b/arch/mips/kernel/machine_kexec.h +@@ -0,0 +1,20 @@ ++#ifndef _MACHINE_KEXEC_H ++#define _MACHINE_KEXEC_H ++ ++#ifndef __ASSEMBLY__ ++extern const unsigned char kexec_relocate_new_kernel[]; ++extern unsigned long kexec_relocate_new_kernel_end; ++extern unsigned long kexec_start_address; ++extern unsigned long kexec_indirection_page; ++ ++extern char kexec_argv_buf[]; ++extern char *kexec_argv[]; ++ ++#define KEXEC_RELOCATE_NEW_KERNEL_SIZE ((unsigned long)&kexec_relocate_new_kernel_end - (unsigned long)kexec_relocate_new_kernel) ++#endif /* !__ASSEMBLY__ */ ++ ++#define KEXEC_COMMAND_LINE_SIZE 256 ++#define KEXEC_ARGV_SIZE (KEXEC_COMMAND_LINE_SIZE / 16) ++#define KEXEC_MAX_ARGC (KEXEC_ARGV_SIZE / sizeof(long)) ++ ++#endif +--- a/arch/mips/kernel/relocate_kernel.S ++++ b/arch/mips/kernel/relocate_kernel.S +@@ -12,8 +12,9 @@ + #include + #include + #include ++#include "machine_kexec.h" + +-LEAF(relocate_new_kernel) ++LEAF(kexec_relocate_new_kernel) + PTR_L a0, arg0 + PTR_L a1, arg1 + PTR_L a2, arg2 +@@ -98,7 +99,7 @@ done: + #endif + /* jump to kexec_start_address */ + j s1 +- END(relocate_new_kernel) ++ END(kexec_relocate_new_kernel) + + #ifdef CONFIG_SMP + /* +@@ -184,9 +185,15 @@ kexec_indirection_page: + PTR 0 + .size kexec_indirection_page, PTRSIZE + +-relocate_new_kernel_end: ++kexec_argv_buf: ++ EXPORT(kexec_argv_buf) ++ .skip KEXEC_COMMAND_LINE_SIZE ++ .size kexec_argv_buf, KEXEC_COMMAND_LINE_SIZE ++ ++kexec_argv: ++ EXPORT(kexec_argv) ++ .skip KEXEC_ARGV_SIZE ++ .size kexec_argv, KEXEC_ARGV_SIZE + +-relocate_new_kernel_size: +- EXPORT(relocate_new_kernel_size) +- PTR relocate_new_kernel_end - relocate_new_kernel +- .size relocate_new_kernel_size, PTRSIZE ++kexec_relocate_new_kernel_end: ++ EXPORT(kexec_relocate_new_kernel_end) diff --git a/target/linux/generic/patches-3.18/400-mtd-add-rootfs-split-support.patch b/target/linux/generic/patches-3.18/400-mtd-add-rootfs-split-support.patch new file mode 100644 index 0000000..0a6e134 --- /dev/null +++ b/target/linux/generic/patches-3.18/400-mtd-add-rootfs-split-support.patch @@ -0,0 +1,171 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -12,6 +12,23 @@ menuconfig MTD + + if MTD + ++menu "OpenWrt specific MTD options" ++ ++config MTD_ROOTFS_ROOT_DEV ++ bool "Automatically set 'rootfs' partition to be root filesystem" ++ default y ++ ++config MTD_SPLIT_FIRMWARE ++ bool "Automatically split firmware partition for kernel+rootfs" ++ default y ++ ++config MTD_SPLIT_FIRMWARE_NAME ++ string "Firmware partition name" ++ depends on MTD_SPLIT_FIRMWARE ++ default "firmware" ++ ++endmenu ++ + config MTD_TESTS + tristate "MTD tests support (DANGEROUS)" + depends on m +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -30,9 +30,11 @@ + #include + #include + #include ++#include + #include + + #include "mtdcore.h" ++#include "mtdsplit/mtdsplit.h" + + /* Our partition linked list */ + static LIST_HEAD(mtd_partitions); +@@ -46,13 +48,14 @@ struct mtd_part { + struct list_head list; + }; + ++static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part); ++ + /* + * Given a pointer to the MTD object in the mtd_part structure, we can retrieve + * the pointer to that structure with this macro. + */ + #define PART(x) ((struct mtd_part *)(x)) + +- + /* + * MTD methods which simply translate the effective address and pass through + * to the _real_ device. +@@ -548,8 +551,10 @@ out_register: + return slave; + } + +-int mtd_add_partition(struct mtd_info *master, const char *name, +- long long offset, long long length) ++ ++static int ++__mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length, bool dup_check) + { + struct mtd_partition part; + struct mtd_part *p, *new; +@@ -581,21 +586,24 @@ int mtd_add_partition(struct mtd_info *m + end = offset + length; + + mutex_lock(&mtd_partitions_mutex); +- list_for_each_entry(p, &mtd_partitions, list) +- if (p->master == master) { +- if ((start >= p->offset) && +- (start < (p->offset + p->mtd.size))) +- goto err_inv; +- +- if ((end >= p->offset) && +- (end < (p->offset + p->mtd.size))) +- goto err_inv; +- } ++ if (dup_check) { ++ list_for_each_entry(p, &mtd_partitions, list) ++ if (p->master == master) { ++ if ((start >= p->offset) && ++ (start < (p->offset + p->mtd.size))) ++ goto err_inv; ++ ++ if ((end >= p->offset) && ++ (end < (p->offset + p->mtd.size))) ++ goto err_inv; ++ } ++ } + + list_add(&new->list, &mtd_partitions); + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&new->mtd); ++ mtd_partition_split(master, new); + + return ret; + err_inv: +@@ -605,6 +613,12 @@ err_inv: + } + EXPORT_SYMBOL_GPL(mtd_add_partition); + ++int mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length) ++{ ++ return __mtd_add_partition(master, name, offset, length, true); ++} ++ + int mtd_del_partition(struct mtd_info *master, int partno) + { + struct mtd_part *slave, *next; +@@ -628,6 +642,35 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME ++#define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME ++#else ++#define SPLIT_FIRMWARE_NAME "unused" ++#endif ++ ++static void split_firmware(struct mtd_info *master, struct mtd_part *part) ++{ ++} ++ ++void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++} ++ ++static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part) ++{ ++ static int rootfs_found = 0; ++ ++ if (rootfs_found) ++ return; ++ ++ if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && ++ config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) ++ split_firmware(master, part); ++ ++ arch_split_mtd_part(master, part->mtd.name, part->offset, ++ part->mtd.size); ++} + /* + * This function, given a master MTD object and a partition table, creates + * and registers slave MTD objects which are bound to the master according to +@@ -657,6 +700,7 @@ int add_mtd_partitions(struct mtd_info * + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&slave->mtd); ++ mtd_partition_split(master, slave); + + cur_offset = slave->offset + slave->mtd.size; + } +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -84,5 +84,7 @@ int mtd_add_partition(struct mtd_info *m + long long offset, long long length); + int mtd_del_partition(struct mtd_info *master, int partno); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); ++extern void __weak arch_split_mtd_part(struct mtd_info *master, ++ const char *name, int offset, int size); + + #endif diff --git a/target/linux/generic/patches-3.18/401-mtd-add-support-for-different-partition-parser-types.patch b/target/linux/generic/patches-3.18/401-mtd-add-support-for-different-partition-parser-types.patch new file mode 100644 index 0000000..6842341 --- /dev/null +++ b/target/linux/generic/patches-3.18/401-mtd-add-support-for-different-partition-parser-types.patch @@ -0,0 +1,113 @@ +From 02cff0ccaa6d364f5c1eeea83f47ac80ccc967d4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 3 Sep 2013 18:11:50 +0200 +Subject: [PATCH] mtd: add support for different partition parser types + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/mtdpart.c | 56 ++++++++++++++++++++++++++++++++++++++++ + include/linux/mtd/partitions.h | 11 ++++++++ + 2 files changed, 67 insertions(+) + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -730,6 +730,30 @@ static struct mtd_part_parser *get_parti + + #define put_partition_parser(p) do { module_put((p)->owner); } while (0) + ++static struct mtd_part_parser * ++get_partition_parser_by_type(enum mtd_parser_type type, ++ struct mtd_part_parser *start) ++{ ++ struct mtd_part_parser *p, *ret = NULL; ++ ++ spin_lock(&part_parser_lock); ++ ++ p = list_prepare_entry(start, &part_parsers, list); ++ if (start) ++ put_partition_parser(start); ++ ++ list_for_each_entry_continue(p, &part_parsers, list) { ++ if (p->type == type && try_module_get(p->owner)) { ++ ret = p; ++ break; ++ } ++ } ++ ++ spin_unlock(&part_parser_lock); ++ ++ return ret; ++} ++ + void register_mtd_parser(struct mtd_part_parser *p) + { + spin_lock(&part_parser_lock); +@@ -845,6 +869,38 @@ int parse_mtd_partitions(struct mtd_info + return ret; + } + ++int parse_mtd_partitions_by_type(struct mtd_info *master, ++ enum mtd_parser_type type, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct mtd_part_parser *prev = NULL; ++ int ret = 0; ++ ++ while (1) { ++ struct mtd_part_parser *parser; ++ ++ parser = get_partition_parser_by_type(type, prev); ++ if (!parser) ++ break; ++ ++ ret = (*parser->parse_fn)(master, pparts, data); ++ ++ if (ret > 0) { ++ put_partition_parser(parser); ++ printk(KERN_NOTICE ++ "%d %s partitions found on MTD device %s\n", ++ ret, parser->name, master->name); ++ break; ++ } ++ ++ prev = parser; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(parse_mtd_partitions_by_type); ++ + int mtd_is_partition(const struct mtd_info *mtd) + { + struct mtd_part *part; +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -68,12 +68,17 @@ struct mtd_part_parser_data { + * Functions dealing with the various ways of partitioning the space + */ + ++enum mtd_parser_type { ++ MTD_PARSER_TYPE_DEVICE = 0, ++}; ++ + struct mtd_part_parser { + struct list_head list; + struct module *owner; + const char *name; + int (*parse_fn)(struct mtd_info *, struct mtd_partition **, + struct mtd_part_parser_data *); ++ enum mtd_parser_type type; + }; + + extern void register_mtd_parser(struct mtd_part_parser *parser); +@@ -87,4 +92,9 @@ uint64_t mtd_get_device_size(const struc + extern void __weak arch_split_mtd_part(struct mtd_info *master, + const char *name, int offset, int size); + ++int parse_mtd_partitions_by_type(struct mtd_info *master, ++ enum mtd_parser_type type, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data); ++ + #endif diff --git a/target/linux/generic/patches-3.18/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch b/target/linux/generic/patches-3.18/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch new file mode 100644 index 0000000..dead0fb --- /dev/null +++ b/target/linux/generic/patches-3.18/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch @@ -0,0 +1,72 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -642,6 +642,37 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++static int ++run_parsers_by_type(struct mtd_part *slave, enum mtd_parser_type type) ++{ ++ struct mtd_partition *parts; ++ int nr_parts; ++ int i; ++ ++ nr_parts = parse_mtd_partitions_by_type(&slave->mtd, type, &parts, ++ NULL); ++ if (nr_parts <= 0) ++ return nr_parts; ++ ++ if (WARN_ON(!parts)) ++ return 0; ++ ++ for (i = 0; i < nr_parts; i++) { ++ /* adjust partition offsets */ ++ parts[i].offset += slave->offset; ++ ++ __mtd_add_partition(slave->master, ++ parts[i].name, ++ parts[i].offset, ++ parts[i].size, ++ false); ++ } ++ ++ kfree(parts); ++ ++ return nr_parts; ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -650,6 +681,7 @@ EXPORT_SYMBOL_GPL(mtd_del_partition); + + static void split_firmware(struct mtd_info *master, struct mtd_part *part) + { ++ run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); + } + + void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, +@@ -664,6 +696,12 @@ static void mtd_partition_split(struct m + if (rootfs_found) + return; + ++ if (!strcmp(part->mtd.name, "rootfs")) { ++ run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); ++ ++ rootfs_found = 1; ++ } ++ + if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && + config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) + split_firmware(master, part); +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -70,6 +70,8 @@ struct mtd_part_parser_data { + + enum mtd_parser_type { + MTD_PARSER_TYPE_DEVICE = 0, ++ MTD_PARSER_TYPE_ROOTFS, ++ MTD_PARSER_TYPE_FIRMWARE, + }; + + struct mtd_part_parser { diff --git a/target/linux/generic/patches-3.18/403-mtd-hook-mtdsplit-to-Kbuild.patch b/target/linux/generic/patches-3.18/403-mtd-hook-mtdsplit-to-Kbuild.patch new file mode 100644 index 0000000..0cf1c38 --- /dev/null +++ b/target/linux/generic/patches-3.18/403-mtd-hook-mtdsplit-to-Kbuild.patch @@ -0,0 +1,22 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -27,6 +27,8 @@ config MTD_SPLIT_FIRMWARE_NAME + depends on MTD_SPLIT_FIRMWARE + default "firmware" + ++source "drivers/mtd/mtdsplit/Kconfig" ++ + endmenu + + config MTD_TESTS +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -6,6 +6,8 @@ + obj-$(CONFIG_MTD) += mtd.o + mtd-y := mtdcore.o mtdsuper.o mtdconcat.o mtdpart.o mtdchar.o + ++obj-$(CONFIG_MTD_SPLIT) += mtdsplit/ ++ + obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o diff --git a/target/linux/generic/patches-3.18/404-mtd-add-more-helper-functions.patch b/target/linux/generic/patches-3.18/404-mtd-add-more-helper-functions.patch new file mode 100644 index 0000000..b2f62c1 --- /dev/null +++ b/target/linux/generic/patches-3.18/404-mtd-add-more-helper-functions.patch @@ -0,0 +1,101 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -446,14 +446,12 @@ static struct mtd_part *allocate_partiti + if (slave->offset == MTDPART_OFS_APPEND) + slave->offset = cur_offset; + if (slave->offset == MTDPART_OFS_NXTBLK) { +- slave->offset = cur_offset; +- if (mtd_mod_by_eb(cur_offset, master) != 0) { +- /* Round up to next erasesize */ +- slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize; ++ /* Round up to next erasesize */ ++ slave->offset = mtd_roundup_to_eb(cur_offset, master); ++ if (slave->offset != cur_offset) + printk(KERN_NOTICE "Moving partition %d: " + "0x%012llx -> 0x%012llx\n", partno, + (unsigned long long)cur_offset, (unsigned long long)slave->offset); +- } + } + if (slave->offset == MTDPART_OFS_RETAIN) { + slave->offset = cur_offset; +@@ -673,6 +671,17 @@ run_parsers_by_type(struct mtd_part *sla + return nr_parts; + } + ++static inline unsigned long ++mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len) ++{ ++ unsigned long mask = mtd->erasesize - 1; ++ ++ len += offset & mask; ++ len = (len + mask) & ~mask; ++ len -= offset & mask; ++ return len; ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -956,6 +965,24 @@ int mtd_is_partition(const struct mtd_in + } + EXPORT_SYMBOL_GPL(mtd_is_partition); + ++struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd) ++{ ++ if (!mtd_is_partition(mtd)) ++ return (struct mtd_info *)mtd; ++ ++ return PART(mtd)->master; ++} ++EXPORT_SYMBOL_GPL(mtdpart_get_master); ++ ++uint64_t mtdpart_get_offset(const struct mtd_info *mtd) ++{ ++ if (!mtd_is_partition(mtd)) ++ return 0; ++ ++ return PART(mtd)->offset; ++} ++EXPORT_SYMBOL_GPL(mtdpart_get_offset); ++ + /* Returns the size of the entire flash chip */ + uint64_t mtd_get_device_size(const struct mtd_info *mtd) + { +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -90,6 +90,8 @@ int mtd_is_partition(const struct mtd_in + int mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length); + int mtd_del_partition(struct mtd_info *master, int partno); ++struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd); ++uint64_t mtdpart_get_offset(const struct mtd_info *mtd); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); + extern void __weak arch_split_mtd_part(struct mtd_info *master, + const char *name, int offset, int size); +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -333,6 +333,24 @@ static inline uint32_t mtd_mod_by_eb(uin + return do_div(sz, mtd->erasesize); + } + ++static inline uint64_t mtd_roundup_to_eb(uint64_t sz, struct mtd_info *mtd) ++{ ++ if (mtd_mod_by_eb(sz, mtd) == 0) ++ return sz; ++ ++ /* Round up to next erase block */ ++ return (mtd_div_by_eb(sz, mtd) + 1) * mtd->erasesize; ++} ++ ++static inline uint64_t mtd_rounddown_to_eb(uint64_t sz, struct mtd_info *mtd) ++{ ++ if (mtd_mod_by_eb(sz, mtd) == 0) ++ return sz; ++ ++ /* Round down to the start of the current erase block */ ++ return (mtd_div_by_eb(sz, mtd)) * mtd->erasesize; ++} ++ + static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd) + { + if (mtd->writesize_shift) diff --git a/target/linux/generic/patches-3.18/405-mtd-old-firmware-uimage-splitter.patch b/target/linux/generic/patches-3.18/405-mtd-old-firmware-uimage-splitter.patch new file mode 100644 index 0000000..7e74c4e --- /dev/null +++ b/target/linux/generic/patches-3.18/405-mtd-old-firmware-uimage-splitter.patch @@ -0,0 +1,70 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -27,6 +27,11 @@ config MTD_SPLIT_FIRMWARE_NAME + depends on MTD_SPLIT_FIRMWARE + default "firmware" + ++config MTD_UIMAGE_SPLIT ++ bool "Enable split support for firmware partitions containing a uImage" ++ depends on MTD_SPLIT_FIRMWARE ++ default y ++ + source "drivers/mtd/mtdsplit/Kconfig" + + endmenu +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -682,6 +682,37 @@ mtd_pad_erasesize(struct mtd_info *mtd, + return len; + } + ++#define UBOOT_MAGIC 0x27051956 ++ ++static void split_uimage(struct mtd_info *master, struct mtd_part *part) ++{ ++ struct { ++ __be32 magic; ++ __be32 pad[2]; ++ __be32 size; ++ } hdr; ++ size_t len; ++ ++ if (mtd_read(master, part->offset, sizeof(hdr), &len, (void *) &hdr)) ++ return; ++ ++ if (len != sizeof(hdr) || hdr.magic != cpu_to_be32(UBOOT_MAGIC)) ++ return; ++ ++ len = be32_to_cpu(hdr.size) + 0x40; ++ len = mtd_pad_erasesize(master, part->offset, len); ++ if (len + master->erasesize > part->mtd.size) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_SPLIT_UIMAGE_FW)) ++ pr_err("Dedicated partitioner didn't split firmware partition, please fill a bug report!\n"); ++ else ++ pr_warn("Support for built-in firmware splitter will be removed, please use CONFIG_MTD_SPLIT_UIMAGE_FW\n"); ++ ++ __mtd_add_partition(master, "rootfs", part->offset + len, ++ part->mtd.size - len, false); ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -690,7 +721,14 @@ mtd_pad_erasesize(struct mtd_info *mtd, + + static void split_firmware(struct mtd_info *master, struct mtd_part *part) + { +- run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); ++ int ret; ++ ++ ret = run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); ++ if (ret > 0) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_UIMAGE_SPLIT)) ++ split_uimage(master, part); + } + + void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, diff --git a/target/linux/generic/patches-3.18/406-mtd-old-rootfs-squashfs-splitter.patch b/target/linux/generic/patches-3.18/406-mtd-old-rootfs-squashfs-splitter.patch new file mode 100644 index 0000000..cc548ef --- /dev/null +++ b/target/linux/generic/patches-3.18/406-mtd-old-rootfs-squashfs-splitter.patch @@ -0,0 +1,76 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -18,6 +18,11 @@ config MTD_ROOTFS_ROOT_DEV + bool "Automatically set 'rootfs' partition to be root filesystem" + default y + ++config MTD_ROOTFS_SPLIT ++ bool "Automatically split 'rootfs' partition for squashfs" ++ select MTD_SPLIT ++ default y ++ + config MTD_SPLIT_FIRMWARE + bool "Automatically split firmware partition for kernel+rootfs" + default y +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -682,6 +682,47 @@ mtd_pad_erasesize(struct mtd_info *mtd, + return len; + } + ++static int split_squashfs(struct mtd_info *master, int offset, int *split_offset) ++{ ++ size_t squashfs_len; ++ int len, ret; ++ ++ ret = mtd_get_squashfs_len(master, offset, &squashfs_len); ++ if (ret) ++ return ret; ++ ++ len = mtd_pad_erasesize(master, offset, squashfs_len); ++ *split_offset = offset + len; ++ ++ return 0; ++} ++ ++static void split_rootfs_data(struct mtd_info *master, struct mtd_part *part) ++{ ++ unsigned int split_offset = 0; ++ unsigned int split_size; ++ int ret; ++ ++ ret = split_squashfs(master, part->offset, &split_offset); ++ if (ret) ++ return; ++ ++ if (split_offset <= 0) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_SPLIT_SQUASHFS_ROOT)) ++ pr_err("Dedicated partitioner didn't create \"rootfs_data\" partition, please fill a bug report!\n"); ++ else ++ pr_warn("Support for built-in \"rootfs_data\" splitter will be removed, please use CONFIG_MTD_SPLIT_SQUASHFS_ROOT\n"); ++ ++ split_size = part->mtd.size - (split_offset - part->offset); ++ printk(KERN_INFO "mtd: partition \"%s\" created automatically, ofs=0x%x, len=0x%x\n", ++ ROOTFS_SPLIT_NAME, split_offset, split_size); ++ ++ __mtd_add_partition(master, ROOTFS_SPLIT_NAME, split_offset, ++ split_size, false); ++} ++ + #define UBOOT_MAGIC 0x27051956 + + static void split_uimage(struct mtd_info *master, struct mtd_part *part) +@@ -744,7 +785,10 @@ static void mtd_partition_split(struct m + return; + + if (!strcmp(part->mtd.name, "rootfs")) { +- run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); ++ int num = run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); ++ ++ if (num <= 0 && config_enabled(CONFIG_MTD_ROOTFS_SPLIT)) ++ split_rootfs_data(master, part); + + rootfs_found = 1; + } diff --git a/target/linux/generic/patches-3.18/410-mtd-move-forward-declaration-of-struct-mtd_info.patch b/target/linux/generic/patches-3.18/410-mtd-move-forward-declaration-of-struct-mtd_info.patch new file mode 100644 index 0000000..78ebbf8 --- /dev/null +++ b/target/linux/generic/patches-3.18/410-mtd-move-forward-declaration-of-struct-mtd_info.patch @@ -0,0 +1,18 @@ +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -35,6 +35,7 @@ + * Note: writeable partitions require their size and offset be + * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK). + */ ++struct mtd_info; + + struct mtd_partition { + const char *name; /* identifier string */ +@@ -50,7 +51,6 @@ struct mtd_partition { + #define MTDPART_SIZ_FULL (0) + + +-struct mtd_info; + struct device_node; + + /** diff --git a/target/linux/generic/patches-3.18/411-mtd-partial_eraseblock_write.patch b/target/linux/generic/patches-3.18/411-mtd-partial_eraseblock_write.patch new file mode 100644 index 0000000..5d5c6ed --- /dev/null +++ b/target/linux/generic/patches-3.18/411-mtd-partial_eraseblock_write.patch @@ -0,0 +1,142 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -36,6 +36,8 @@ + #include "mtdcore.h" + #include "mtdsplit/mtdsplit.h" + ++#define MTD_ERASE_PARTIAL 0x8000 /* partition only covers parts of an erase block */ ++ + /* Our partition linked list */ + static LIST_HEAD(mtd_partitions); + static DEFINE_MUTEX(mtd_partitions_mutex); +@@ -234,13 +236,61 @@ static int part_erase(struct mtd_info *m + struct mtd_part *part = PART(mtd); + int ret; + ++ ++ instr->partial_start = false; ++ if (mtd->flags & MTD_ERASE_PARTIAL) { ++ size_t readlen = 0; ++ u64 mtd_ofs; ++ ++ instr->erase_buf = kmalloc(part->master->erasesize, GFP_ATOMIC); ++ if (!instr->erase_buf) ++ return -ENOMEM; ++ ++ mtd_ofs = part->offset + instr->addr; ++ instr->erase_buf_ofs = do_div(mtd_ofs, part->master->erasesize); ++ ++ if (instr->erase_buf_ofs > 0) { ++ instr->addr -= instr->erase_buf_ofs; ++ ret = mtd_read(part->master, ++ instr->addr + part->offset, ++ part->master->erasesize, ++ &readlen, instr->erase_buf); ++ ++ instr->len += instr->erase_buf_ofs; ++ instr->partial_start = true; ++ } else { ++ mtd_ofs = part->offset + part->mtd.size; ++ instr->erase_buf_ofs = part->master->erasesize - ++ do_div(mtd_ofs, part->master->erasesize); ++ ++ if (instr->erase_buf_ofs > 0) { ++ instr->len += instr->erase_buf_ofs; ++ ret = mtd_read(part->master, ++ part->offset + instr->addr + ++ instr->len - part->master->erasesize, ++ part->master->erasesize, &readlen, ++ instr->erase_buf); ++ } else { ++ ret = 0; ++ } ++ } ++ if (ret < 0) { ++ kfree(instr->erase_buf); ++ return ret; ++ } ++ ++ } ++ + instr->addr += part->offset; + ret = part->master->_erase(part->master, instr); + if (ret) { + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; ++ if (mtd->flags & MTD_ERASE_PARTIAL) ++ kfree(instr->erase_buf); + } ++ + return ret; + } + +@@ -248,7 +298,25 @@ void mtd_erase_callback(struct erase_inf + { + if (instr->mtd->_erase == part_erase) { + struct mtd_part *part = PART(instr->mtd); ++ size_t wrlen = 0; + ++ if (instr->mtd->flags & MTD_ERASE_PARTIAL) { ++ if (instr->partial_start) { ++ part->master->_write(part->master, ++ instr->addr, instr->erase_buf_ofs, ++ &wrlen, instr->erase_buf); ++ instr->addr += instr->erase_buf_ofs; ++ } else { ++ instr->len -= instr->erase_buf_ofs; ++ part->master->_write(part->master, ++ instr->addr + instr->len, ++ instr->erase_buf_ofs, &wrlen, ++ instr->erase_buf + ++ part->master->erasesize - ++ instr->erase_buf_ofs); ++ } ++ kfree(instr->erase_buf); ++ } + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; +@@ -515,17 +583,20 @@ static struct mtd_part *allocate_partiti + if ((slave->mtd.flags & MTD_WRITEABLE) && + mtd_mod_by_eb(slave->offset, &slave->mtd)) { + /* Doesn't start on a boundary of major erase size */ +- /* FIXME: Let it be writable if it is on a boundary of +- * _minor_ erase size though */ +- slave->mtd.flags &= ~MTD_WRITEABLE; +- printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase block boundary -- force read-only\n", +- part->name); ++ slave->mtd.flags |= MTD_ERASE_PARTIAL; ++ if (((u32) slave->mtd.size) > master->erasesize) ++ slave->mtd.flags &= ~MTD_WRITEABLE; ++ else ++ slave->mtd.erasesize = slave->mtd.size; + } + if ((slave->mtd.flags & MTD_WRITEABLE) && +- mtd_mod_by_eb(slave->mtd.size, &slave->mtd)) { +- slave->mtd.flags &= ~MTD_WRITEABLE; +- printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase block -- force read-only\n", +- part->name); ++ mtd_mod_by_eb(slave->offset + slave->mtd.size, &slave->mtd)) { ++ slave->mtd.flags |= MTD_ERASE_PARTIAL; ++ ++ if ((u32) slave->mtd.size > master->erasesize) ++ slave->mtd.flags &= ~MTD_WRITEABLE; ++ else ++ slave->mtd.erasesize = slave->mtd.size; + } + + slave->mtd.ecclayout = master->ecclayout; +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -55,6 +55,10 @@ struct erase_info { + u_long priv; + u_char state; + struct erase_info *next; ++ ++ u8 *erase_buf; ++ u32 erase_buf_ofs; ++ bool partial_start; + }; + + struct mtd_erase_region_info { diff --git a/target/linux/generic/patches-3.18/412-mtd-partial_eraseblock_unlock.patch b/target/linux/generic/patches-3.18/412-mtd-partial_eraseblock_unlock.patch new file mode 100644 index 0000000..62f9d5b --- /dev/null +++ b/target/linux/generic/patches-3.18/412-mtd-partial_eraseblock_unlock.patch @@ -0,0 +1,18 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -335,7 +335,14 @@ static int part_lock(struct mtd_info *mt + static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) + { + struct mtd_part *part = PART(mtd); +- return part->master->_unlock(part->master, ofs + part->offset, len); ++ ++ ofs += part->offset; ++ if (mtd->flags & MTD_ERASE_PARTIAL) { ++ /* round up len to next erasesize and round down offset to prev block */ ++ len = (mtd_div_by_eb(len, part->master) + 1) * part->master->erasesize; ++ ofs &= ~(part->master->erasesize - 1); ++ } ++ return part->master->_unlock(part->master, ofs, len); + } + + static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) diff --git a/target/linux/generic/patches-3.18/420-mtd-redboot_space.patch b/target/linux/generic/patches-3.18/420-mtd-redboot_space.patch new file mode 100644 index 0000000..f74affc --- /dev/null +++ b/target/linux/generic/patches-3.18/420-mtd-redboot_space.patch @@ -0,0 +1,30 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -265,14 +265,21 @@ static int parse_redboot_partitions(stru + #endif + names += strlen(names)+1; + +-#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + if(fl->next && fl->img->flash_base + fl->img->size + master->erasesize <= fl->next->img->flash_base) { +- i++; +- parts[i].offset = parts[i-1].size + parts[i-1].offset; +- parts[i].size = fl->next->img->flash_base - parts[i].offset; +- parts[i].name = nullname; +- } ++ if (!strcmp(parts[i].name, "rootfs")) { ++ parts[i].size = fl->next->img->flash_base; ++ parts[i].size &= ~(master->erasesize - 1); ++ parts[i].size -= parts[i].offset; ++#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED ++ nrparts--; ++ } else { ++ i++; ++ parts[i].offset = parts[i-1].size + parts[i-1].offset; ++ parts[i].size = fl->next->img->flash_base - parts[i].offset; ++ parts[i].name = nullname; + #endif ++ } ++ } + tmp_fl = fl; + fl = fl->next; + kfree(tmp_fl); diff --git a/target/linux/generic/patches-3.18/430-mtd-add-myloader-partition-parser.patch b/target/linux/generic/patches-3.18/430-mtd-add-myloader-partition-parser.patch new file mode 100644 index 0000000..25e0ecd --- /dev/null +++ b/target/linux/generic/patches-3.18/430-mtd-add-myloader-partition-parser.patch @@ -0,0 +1,35 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -184,6 +184,22 @@ config MTD_BCM47XX_PARTS + This provides partitions parser for devices based on BCM47xx + boards. + ++config MTD_MYLOADER_PARTS ++ tristate "MyLoader partition parsing" ++ depends on ADM5120 || ATH25 || ATH79 ++ ---help--- ++ MyLoader is a bootloader which allows the user to define partitions ++ in flash devices, by putting a table in the second erase block ++ on the device, similar to a partition table. This table gives the ++ offsets and lengths of the user defined partitions. ++ ++ If you need code which can detect and parse these tables, and ++ register MTD 'partitions' corresponding to each image detected, ++ enable this option. ++ ++ You will still need the parsing functions to be called by the driver ++ for your particular device. It won't happen automatically. ++ + comment "User Modules And Translation Layers" + + # +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o ++obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/generic/patches-3.18/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch b/target/linux/generic/patches-3.18/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch new file mode 100644 index 0000000..a30e698 --- /dev/null +++ b/target/linux/generic/patches-3.18/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch @@ -0,0 +1,34 @@ +From 841e59ba3e496d86ca5f069204d5e5c1ad43c01d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 27 Jan 2015 22:29:21 +0100 +Subject: [PATCH] mtd: bcm47xxpart: support for Xiaomi specific board_data + partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/bcm47xxpart.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -33,6 +33,7 @@ + /* Magics */ + #define BOARD_DATA_MAGIC 0x5246504D /* MPFR */ + #define BOARD_DATA_MAGIC2 0xBD0D0BBD ++#define BOARD_DATA_XIAOMI_MAGIC 0x474D4442 /* GMDB */ + #define CFE_MAGIC 0x43464531 /* 1EFC */ + #define FACTORY_MAGIC 0x59544346 /* FCTY */ + #define NVRAM_HEADER 0x48534C46 /* FLSH */ +@@ -262,7 +263,8 @@ static int bcm47xxpart_parse(struct mtd_ + } + + /* Some devices (ex. WNDR3700v3) don't have a standard 'MPFR' */ +- if (buf[0x000 / 4] == BOARD_DATA_MAGIC2) { ++ if (buf[0x000 / 4] == BOARD_DATA_MAGIC2 || ++ le32_to_cpu(buf[0x000 / 4]) == BOARD_DATA_XIAOMI_MAGIC) { + bcm47xxpart_add_part(&parts[curr_part++], "board_data", + offset, MTD_WRITEABLE); + continue; diff --git a/target/linux/generic/patches-3.18/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch b/target/linux/generic/patches-3.18/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch new file mode 100644 index 0000000..1edc995 --- /dev/null +++ b/target/linux/generic/patches-3.18/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch @@ -0,0 +1,42 @@ +From fd54aa583296f9adfb1f519affbc10ba521eb809 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 28 Jan 2015 22:14:41 +0100 +Subject: [PATCH] mtd: bcm47xxpart: detect T_Meter partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It can be found on many Netgear devices. It consists of many 0x30 blocks +starting with 4D 54. + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/bcm47xxpart.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -39,6 +39,7 @@ + #define NVRAM_HEADER 0x48534C46 /* FLSH */ + #define POT_MAGIC1 0x54544f50 /* POTT */ + #define POT_MAGIC2 0x504f /* OP */ ++#define T_METER_MAGIC 0x4D540000 /* MT */ + #define ML_MAGIC1 0x39685a42 + #define ML_MAGIC2 0x26594131 + #define TRX_MAGIC 0x30524448 +@@ -176,6 +177,15 @@ static int bcm47xxpart_parse(struct mtd_ + MTD_WRITEABLE); + continue; + } ++ ++ /* T_Meter */ ++ if ((le32_to_cpu(buf[0x000 / 4]) & 0xFFFF0000) == T_METER_MAGIC && ++ (le32_to_cpu(buf[0x030 / 4]) & 0xFFFF0000) == T_METER_MAGIC && ++ (le32_to_cpu(buf[0x060 / 4]) & 0xFFFF0000) == T_METER_MAGIC) { ++ bcm47xxpart_add_part(&parts[curr_part++], "T_Meter", offset, ++ MTD_WRITEABLE); ++ continue; ++ } + + /* TRX */ + if (buf[0x000 / 4] == TRX_MAGIC) { diff --git a/target/linux/generic/patches-3.18/440-block2mtd_init.patch b/target/linux/generic/patches-3.18/440-block2mtd_init.patch new file mode 100644 index 0000000..5ab6026 --- /dev/null +++ b/target/linux/generic/patches-3.18/440-block2mtd_init.patch @@ -0,0 +1,107 @@ +--- a/drivers/mtd/devices/block2mtd.c ++++ b/drivers/mtd/devices/block2mtd.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -209,11 +210,12 @@ static void block2mtd_free_device(struct + } + + +-static struct block2mtd_dev *add_device(char *devname, int erase_size) ++static struct block2mtd_dev *add_device(char *devname, int erase_size, const char *mtdname) + { + const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL; + struct block_device *bdev; + struct block2mtd_dev *dev; ++ struct mtd_partition *part; + char *name; + + if (!devname) +@@ -257,13 +259,16 @@ static struct block2mtd_dev *add_device( + + /* Setup the MTD structure */ + /* make the name contain the block device in */ +- name = kasprintf(GFP_KERNEL, "block2mtd: %s", devname); ++ if (!mtdname) ++ mtdname = devname; ++ name = kmalloc(strlen(mtdname) + 1, GFP_KERNEL); + if (!name) + goto err_destroy_mutex; + ++ strcpy(name, mtdname); + dev->mtd.name = name; + +- dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK; ++ dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK & ~(erase_size - 1); + dev->mtd.erasesize = erase_size; + dev->mtd.writesize = 1; + dev->mtd.writebufsize = PAGE_SIZE; +@@ -276,15 +281,18 @@ static struct block2mtd_dev *add_device( + dev->mtd.priv = dev; + dev->mtd.owner = THIS_MODULE; + +- if (mtd_device_register(&dev->mtd, NULL, 0)) { ++ part = kzalloc(sizeof(struct mtd_partition), GFP_KERNEL); ++ part->name = name; ++ part->offset = 0; ++ part->size = dev->mtd.size; ++ if (mtd_device_register(&dev->mtd, part, 1)) { + /* Device didn't get added, so free the entry */ + goto err_destroy_mutex; + } + list_add(&dev->list, &blkmtd_device_list); + pr_info("mtd%d: [%s] erase_size = %dKiB [%d]\n", + dev->mtd.index, +- dev->mtd.name + strlen("block2mtd: "), +- dev->mtd.erasesize >> 10, dev->mtd.erasesize); ++ mtdname, dev->mtd.erasesize >> 10, dev->mtd.erasesize); + return dev; + + err_destroy_mutex: +@@ -353,9 +361,9 @@ static char block2mtd_paramline[80 + 12] + + static int block2mtd_setup2(const char *val) + { +- char buf[80 + 12]; /* 80 for device, 12 for erase size */ ++ char buf[80 + 12 + 80]; /* 80 for device, 12 for erase size, 80 for name */ + char *str = buf; +- char *token[2]; ++ char *token[3]; + char *name; + size_t erase_size = PAGE_SIZE; + int i, ret; +@@ -368,7 +376,7 @@ static int block2mtd_setup2(const char * + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 2; i++) ++ for (i = 0; i < 3; i++) + token[i] = strsep(&str, ","); + + if (str) { +@@ -394,8 +402,10 @@ static int block2mtd_setup2(const char * + return 0; + } + } ++ if (token[2] && (strlen(token[2]) + 1 > 80)) ++ pr_err("mtd device name too long\n"); + +- add_device(name, erase_size); ++ add_device(name, erase_size, token[2]); + + return 0; + } +@@ -429,7 +439,7 @@ static int block2mtd_setup(const char *v + + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); +-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,]\""); ++MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); + + static int __init block2mtd_init(void) + { diff --git a/target/linux/generic/patches-3.18/441-block2mtd_probe.patch b/target/linux/generic/patches-3.18/441-block2mtd_probe.patch new file mode 100644 index 0000000..6836a48 --- /dev/null +++ b/target/linux/generic/patches-3.18/441-block2mtd_probe.patch @@ -0,0 +1,110 @@ +--- a/drivers/mtd/devices/block2mtd.c ++++ b/drivers/mtd/devices/block2mtd.c +@@ -10,6 +10,7 @@ + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + + #include ++#include + #include + #include + #include +@@ -210,13 +211,16 @@ static void block2mtd_free_device(struct + } + + +-static struct block2mtd_dev *add_device(char *devname, int erase_size, const char *mtdname) ++static struct block2mtd_dev *add_device(char *devname, int erase_size, const char *mtdname, int timeout) + { + const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL; +- struct block_device *bdev; ++ struct block_device *bdev = ERR_PTR(-ENODEV); + struct block2mtd_dev *dev; + struct mtd_partition *part; + char *name; ++#ifndef MODULE ++ int i; ++#endif + + if (!devname) + return NULL; +@@ -227,15 +231,20 @@ static struct block2mtd_dev *add_device( + + /* Get a handle on the device */ + bdev = blkdev_get_by_path(devname, mode, dev); ++ + #ifndef MODULE +- if (IS_ERR(bdev)) { ++ for (i = 0; IS_ERR(bdev) && i <= timeout; i++) { ++ dev_t devt; + +- /* We might not have rootfs mounted at this point. Try +- to resolve the device name by other means. */ ++ if (i) ++ msleep(1000); ++ wait_for_device_probe(); ++ ++ devt = name_to_dev_t(devname); ++ if (!devt) ++ continue; + +- dev_t devt = name_to_dev_t(devname); +- if (devt) +- bdev = blkdev_get_by_dev(devt, mode, dev); ++ bdev = blkdev_get_by_dev(devt, mode, dev); + } + #endif + +@@ -361,11 +370,12 @@ static char block2mtd_paramline[80 + 12] + + static int block2mtd_setup2(const char *val) + { +- char buf[80 + 12 + 80]; /* 80 for device, 12 for erase size, 80 for name */ ++ char buf[80 + 12 + 80 + 8]; /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ + char *str = buf; +- char *token[3]; ++ char *token[4]; + char *name; + size_t erase_size = PAGE_SIZE; ++ unsigned long timeout = 0; + int i, ret; + + if (strnlen(val, sizeof(buf)) >= sizeof(buf)) { +@@ -376,7 +386,7 @@ static int block2mtd_setup2(const char * + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 3; i++) ++ for (i = 0; i < 4; i++) + token[i] = strsep(&str, ","); + + if (str) { +@@ -405,7 +415,10 @@ static int block2mtd_setup2(const char * + if (token[2] && (strlen(token[2]) + 1 > 80)) + pr_err("mtd device name too long\n"); + +- add_device(name, erase_size, token[2]); ++ if (token[3] && kstrtoul(token[3], 0, &timeout)) ++ pr_err("invalid timeout\n"); ++ ++ add_device(name, erase_size, token[2], timeout); + + return 0; + } +@@ -439,7 +452,7 @@ static int block2mtd_setup(const char *v + + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); +-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); ++MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,[,]]]\""); + + static int __init block2mtd_init(void) + { +@@ -474,7 +487,7 @@ static void block2mtd_exit(void) + } + + +-module_init(block2mtd_init); ++late_initcall(block2mtd_init); + module_exit(block2mtd_exit); + + MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-3.18/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch b/target/linux/generic/patches-3.18/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch new file mode 100644 index 0000000..0f5abaa --- /dev/null +++ b/target/linux/generic/patches-3.18/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch @@ -0,0 +1,37 @@ +--- + drivers/mtd/nand/plat_nand.c | 13 ++++++++++++- + include/linux/mtd/nand.h | 1 + + 2 files changed, 13 insertions(+), 1 deletion(-) + +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -851,6 +851,7 @@ struct platform_nand_chip { + unsigned int options; + unsigned int bbt_options; + const char **part_probe_types; ++ int (*chip_fixup)(struct mtd_info *mtd); + }; + + /* Keep gcc happy */ +--- a/drivers/mtd/nand/plat_nand.c ++++ b/drivers/mtd/nand/plat_nand.c +@@ -90,7 +90,18 @@ static int plat_nand_probe(struct platfo + } + + /* Scan to find existence of the device */ +- if (nand_scan(&data->mtd, pdata->chip.nr_chips)) { ++ if (nand_scan_ident(&data->mtd, pdata->chip.nr_chips, NULL)) { ++ err = -ENXIO; ++ goto out; ++ } ++ ++ if (pdata->chip.chip_fixup) { ++ err = pdata->chip.chip_fixup(&data->mtd); ++ if (err) ++ goto out; ++ } ++ ++ if (nand_scan_tail(&data->mtd)) { + err = -ENXIO; + goto out; + } diff --git a/target/linux/generic/patches-3.18/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch b/target/linux/generic/patches-3.18/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch new file mode 100644 index 0000000..6a2092c --- /dev/null +++ b/target/linux/generic/patches-3.18/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/nand/nand_ecc.c ++++ b/drivers/mtd/nand/nand_ecc.c +@@ -507,7 +507,7 @@ int __nand_correct_data(unsigned char *b + return 1; /* error in ECC data; no action needed */ + + pr_err("%s: uncorrectable ECC error\n", __func__); +- return -1; ++ return -EBADMSG; + } + EXPORT_SYMBOL(__nand_correct_data); + diff --git a/target/linux/generic/patches-3.18/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch b/target/linux/generic/patches-3.18/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch new file mode 100644 index 0000000..68fbd12 --- /dev/null +++ b/target/linux/generic/patches-3.18/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -809,7 +809,7 @@ static int get_chip(struct map_info *map + return 0; + + case FL_ERASING: +- if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || ++ if (1 /* no suspend */ || !cfip || !(cfip->EraseSuspend & (0x1|0x2)) || + !(mode == FL_READY || mode == FL_POINT || + (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) + goto sleep; diff --git a/target/linux/generic/patches-3.18/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch b/target/linux/generic/patches-3.18/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch new file mode 100644 index 0000000..c437a14 --- /dev/null +++ b/target/linux/generic/patches-3.18/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch @@ -0,0 +1,18 @@ +From: George Kashperko + +Issue map read after Write Buffer Load command to ensure chip is ready +to receive data. +Signed-off-by: George Kashperko +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 1 + + 1 file changed, 1 insertion(+) +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1830,6 +1830,7 @@ static int __xipram do_write_buffer(stru + + /* Write Buffer Load */ + map_write(map, CMD(0x25), cmd_adr); ++ (void) map_read(map, cmd_adr); + + chip->state = FL_WRITING_TO_BUFFER; + diff --git a/target/linux/generic/patches-3.18/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch b/target/linux/generic/patches-3.18/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch new file mode 100644 index 0000000..dca6895 --- /dev/null +++ b/target/linux/generic/patches-3.18/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch @@ -0,0 +1,20 @@ +From eef9dfc4e821408af1af13aa0cc707fc496fb7c6 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 11 Dec 2013 19:05:59 +0100 +Subject: [PATCH] m25p80: add support for the Winbond W25X05 flash + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/devices/m25p80.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -617,6 +617,7 @@ static const struct spi_device_id spi_no + { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, + + /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ ++ { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, + { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, + { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, + { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, diff --git a/target/linux/generic/patches-3.18/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch b/target/linux/generic/patches-3.18/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch new file mode 100644 index 0000000..8082fa6 --- /dev/null +++ b/target/linux/generic/patches-3.18/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch @@ -0,0 +1,21 @@ +From 0d7388de0911c1a4fc4a8a3898ef9d0ab818ca08 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 7 Apr 2015 18:35:15 +0200 +Subject: [PATCH] mtd: spi-nor: add support for the Macronix MX25L512E SPI + flash chip + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/spi-nor/spi-nor.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -517,6 +517,7 @@ static const struct spi_device_id spi_no + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, + + /* Macronix */ ++ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, + { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, + { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, diff --git a/target/linux/generic/patches-3.18/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch b/target/linux/generic/patches-3.18/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch new file mode 100644 index 0000000..f572237 --- /dev/null +++ b/target/linux/generic/patches-3.18/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch @@ -0,0 +1,22 @@ +From 34e2b403040a2f9d3ba071d95a7f42457e2950f9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 7 Apr 2015 18:35:15 +0200 +Subject: [PATCH] mtd: spi-nor: add support for the ISSI SI25CD512 SPI flash + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/spi-nor/spi-nor.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -516,6 +516,9 @@ static const struct spi_device_id spi_no + { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, + ++ /* ISSI */ ++ { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, ++ + /* Macronix */ + { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, diff --git a/target/linux/generic/patches-3.18/480-mtd-set-rootfs-to-be-root-dev.patch b/target/linux/generic/patches-3.18/480-mtd-set-rootfs-to-be-root-dev.patch new file mode 100644 index 0000000..8fc3578 --- /dev/null +++ b/target/linux/generic/patches-3.18/480-mtd-set-rootfs-to-be-root-dev.patch @@ -0,0 +1,26 @@ +--- a/drivers/mtd/mtdcore.c ++++ b/drivers/mtd/mtdcore.c +@@ -37,6 +37,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -456,6 +457,15 @@ int add_mtd_device(struct mtd_info *mtd) + of this try_ nonsense, and no bitching about it + either. :) */ + __module_get(THIS_MODULE); ++ ++ if (!strcmp(mtd->name, "rootfs") && ++ config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ ROOT_DEV == 0) { ++ pr_notice("mtd: device %d (%s) set to be root filesystem\n", ++ mtd->index, mtd->name); ++ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index); ++ } ++ + return 0; + + fail_added: diff --git a/target/linux/generic/patches-3.18/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/patches-3.18/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch new file mode 100644 index 0000000..d7b20b8 --- /dev/null +++ b/target/linux/generic/patches-3.18/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch @@ -0,0 +1,76 @@ +From 8a52e4100d7c3a4a1dfddfa02b8864a9b0068c13 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 17 May 2014 03:36:18 +0200 +Subject: [PATCH 1/5] ubi: auto-attach mtd device named "ubi" or "data" on boot +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/drivers/mtd/ubi/build.c ++++ b/drivers/mtd/ubi/build.c +@@ -1209,6 +1209,49 @@ static struct mtd_info * __init open_mtd + return mtd; + } + ++/* ++ * This function tries attaching mtd partitions named either "ubi" or "data" ++ * during boot. ++ */ ++static void __init ubi_auto_attach(void) ++{ ++ int err; ++ struct mtd_info *mtd; ++ ++ /* try attaching mtd device named "ubi" or "data" */ ++ mtd = open_mtd_device("ubi"); ++ if (IS_ERR(mtd)) ++ mtd = open_mtd_device("data"); ++ ++ if (!IS_ERR(mtd)) { ++ size_t len; ++ char magic[4]; ++ ++ /* check for a valid ubi magic */ ++ err = mtd_read(mtd, 0, 4, &len, (void *) magic); ++ if (!err && len == 4 && strncmp(magic, "UBI#", 4)) { ++ ubi_err("no valid UBI magic found inside mtd%d", mtd->index); ++ put_mtd_device(mtd); ++ return; ++ } ++ ++ /* auto-add only media types where UBI makes sense */ ++ if (mtd->type == MTD_NANDFLASH || ++ mtd->type == MTD_NORFLASH || ++ mtd->type == MTD_DATAFLASH || ++ mtd->type == MTD_MLCNANDFLASH) { ++ mutex_lock(&ubi_devices_mutex); ++ ubi_msg("auto-attach mtd%d", mtd->index); ++ err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0); ++ mutex_unlock(&ubi_devices_mutex); ++ if (err < 0) { ++ ubi_err("cannot attach mtd%d", mtd->index); ++ put_mtd_device(mtd); ++ } ++ } ++ } ++} ++ + static int __init ubi_init(void) + { + int err, i, k; +@@ -1298,6 +1341,12 @@ static int __init ubi_init(void) + } + } + ++ /* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd ++ * parameter was given */ ++ if (config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ !ubi_is_module() && !mtd_devs) ++ ubi_auto_attach(); ++ + err = ubiblock_init(); + if (err) { + ubi_err("block: cannot initialize, error %d", err); diff --git a/target/linux/generic/patches-3.18/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/patches-3.18/491-ubi-auto-create-ubiblock-device-for-rootfs.patch new file mode 100644 index 0000000..b152fba --- /dev/null +++ b/target/linux/generic/patches-3.18/491-ubi-auto-create-ubiblock-device-for-rootfs.patch @@ -0,0 +1,69 @@ +From 0f3966579815f889bb2fcb4846152c35f65e79c4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 15 May 2014 21:06:33 +0200 +Subject: [PATCH 2/5] ubi: auto-create ubiblock device for rootfs +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/block.c | 42 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -615,6 +615,44 @@ static int __init ubiblock_create_from_p + return ret; + } + ++#define UBIFS_NODE_MAGIC 0x06101831 ++static inline int ubi_vol_is_ubifs(struct ubi_volume_desc *desc) ++{ ++ int ret; ++ uint32_t magic_of, magic; ++ ret = ubi_read(desc, 0, (char *)&magic_of, 0, 4); ++ if (ret) ++ return 0; ++ magic = le32_to_cpu(magic_of); ++ return magic == UBIFS_NODE_MAGIC; ++} ++ ++static void __init ubiblock_create_auto_rootfs(void) ++{ ++ int ubi_num, ret, is_ubifs; ++ struct ubi_volume_desc *desc; ++ struct ubi_volume_info vi; ++ ++ for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) { ++ desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY); ++ if (IS_ERR(desc)) ++ continue; ++ ++ ubi_get_volume_info(desc, &vi); ++ is_ubifs = ubi_vol_is_ubifs(desc); ++ ubi_close_volume(desc); ++ if (is_ubifs) ++ break; ++ ++ ret = ubiblock_create(&vi); ++ if (ret) ++ ubi_err("block: can't add '%s' volume, err=%d\n", ++ vi.name, ret); ++ /* always break if we get here */ ++ break; ++ } ++} ++ + static void ubiblock_remove_all(void) + { + struct ubiblock *next; +@@ -645,6 +683,10 @@ int __init ubiblock_init(void) + if (ret) + goto err_remove; + ++ /* auto-attach "rootfs" volume if existing and non-ubifs */ ++ if (config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV)) ++ ubiblock_create_auto_rootfs(); ++ + /* + * Block devices are only created upon user requests, so we ignore + * existing volumes. diff --git a/target/linux/generic/patches-3.18/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch b/target/linux/generic/patches-3.18/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch new file mode 100644 index 0000000..e4f31fd --- /dev/null +++ b/target/linux/generic/patches-3.18/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch @@ -0,0 +1,53 @@ +From eea9e1785e4c05c2a3444506aabafa0ae958538f Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 17 May 2014 03:35:02 +0200 +Subject: [PATCH 4/5] try auto-mounting ubi0:rootfs in init/do_mounts.c +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + init/do_mounts.c | 26 +++++++++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +--- a/init/do_mounts.c ++++ b/init/do_mounts.c +@@ -433,7 +433,27 @@ retry: + out: + put_page(page); + } +- ++ ++static int __init mount_ubi_rootfs(void) ++{ ++ int flags = MS_SILENT; ++ int err, tried = 0; ++ ++ while (tried < 2) { ++ err = do_mount_root("ubi0:rootfs", "ubifs", flags, \ ++ root_mount_data); ++ switch (err) { ++ case -EACCES: ++ flags |= MS_RDONLY; ++ tried++; ++ default: ++ return err; ++ } ++ } ++ ++ return -EINVAL; ++} ++ + #ifdef CONFIG_ROOT_NFS + + #define NFSROOT_TIMEOUT_MIN 5 +@@ -527,6 +547,10 @@ void __init mount_root(void) + change_floppy("root floppy"); + } + #endif ++#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV ++ if (!mount_ubi_rootfs()) ++ return; ++#endif + #ifdef CONFIG_BLOCK + create_dev("/dev/root", ROOT_DEV); + mount_block_root("/dev/root", root_mountflags); diff --git a/target/linux/generic/patches-3.18/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/patches-3.18/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch new file mode 100644 index 0000000..46917d1 --- /dev/null +++ b/target/linux/generic/patches-3.18/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch @@ -0,0 +1,37 @@ +From cd68d1b12b5ea4c01a664c064179ada42bf55d3d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 15 May 2014 20:55:42 +0200 +Subject: [PATCH 5/5] ubi: set ROOT_DEV to ubiblock "rootfs" if unset +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/block.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -48,6 +48,7 @@ + #include + #include + #include ++#include + + #include "ubi-media.h" + #include "ubi.h" +@@ -448,6 +449,15 @@ int ubiblock_create(struct ubi_volume_in + add_disk(dev->gd); + ubi_msg("%s created from ubi%d:%d(%s)", + dev->gd->disk_name, dev->ubi_num, dev->vol_id, vi->name); ++ ++ if (!strcmp(vi->name, "rootfs") && ++ config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ ROOT_DEV == 0) { ++ pr_notice("ubiblock: device ubiblock%d_%d (%s) set to be root filesystem\n", ++ dev->ubi_num, dev->vol_id, vi->name); ++ ROOT_DEV = MKDEV(gd->major, gd->first_minor); ++ } ++ + return 0; + + out_free_queue: diff --git a/target/linux/generic/patches-3.18/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/patches-3.18/494-mtd-ubi-add-EOF-marker-support.patch new file mode 100644 index 0000000..cd02c13 --- /dev/null +++ b/target/linux/generic/patches-3.18/494-mtd-ubi-add-EOF-marker-support.patch @@ -0,0 +1,51 @@ +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -800,6 +800,13 @@ out_unlock: + return err; + } + ++static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech) ++{ ++ return ech->padding1[0] == 'E' && ++ ech->padding1[1] == 'O' && ++ ech->padding1[2] == 'F'; ++} ++ + /** + * scan_peb - scan and process UBI headers of a PEB. + * @ubi: UBI device description object +@@ -830,9 +837,21 @@ static int scan_peb(struct ubi_device *u + return 0; + } + +- err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); +- if (err < 0) +- return err; ++ if (!ai->eof_found) { ++ err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); ++ if (err < 0) ++ return err; ++ ++ if (ec_hdr_has_eof(ech)) { ++ ubi_msg("EOF marker found, PEBs from %d will be erased", ++ pnum); ++ ai->eof_found = true; ++ } ++ } ++ ++ if (ai->eof_found) ++ err = UBI_IO_FF_BITFLIPS; ++ + switch (err) { + case 0: + break; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -701,6 +701,7 @@ struct ubi_attach_info { + int mean_ec; + uint64_t ec_sum; + int ec_count; ++ bool eof_found; + struct kmem_cache *aeb_slab_cache; + }; + diff --git a/target/linux/generic/patches-3.18/500-yaffs-Kbuild-integration.patch b/target/linux/generic/patches-3.18/500-yaffs-Kbuild-integration.patch new file mode 100644 index 0000000..de6643a --- /dev/null +++ b/target/linux/generic/patches-3.18/500-yaffs-Kbuild-integration.patch @@ -0,0 +1,18 @@ +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -39,6 +39,7 @@ source "fs/gfs2/Kconfig" + source "fs/ocfs2/Kconfig" + source "fs/btrfs/Kconfig" + source "fs/nilfs2/Kconfig" ++source "fs/yaffs2/Kconfig" + + endif # BLOCK + +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -126,3 +126,5 @@ obj-y += exofs/ # Multiple modules + obj-$(CONFIG_CEPH_FS) += ceph/ + obj-$(CONFIG_PSTORE) += pstore/ + obj-$(CONFIG_EFIVAR_FS) += efivarfs/ ++obj-$(CONFIG_YAFFS_FS) += yaffs2/ ++ diff --git a/target/linux/generic/patches-3.18/502-yaffs-fix-compat-tags-handling.patch b/target/linux/generic/patches-3.18/502-yaffs-fix-compat-tags-handling.patch new file mode 100644 index 0000000..a18cf6f --- /dev/null +++ b/target/linux/generic/patches-3.18/502-yaffs-fix-compat-tags-handling.patch @@ -0,0 +1,239 @@ +Subject: yaffs: fix compat tags handling + +Signed-off-by: Gabor Juhos +--- +--- a/fs/yaffs2/yaffs_tagscompat.c ++++ b/fs/yaffs2/yaffs_tagscompat.c +@@ -17,7 +17,9 @@ + #include "yaffs_getblockinfo.h" + #include "yaffs_trace.h" + ++#if 0 + static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk); ++#endif + + + /********** Tags ECC calculations *********/ +@@ -71,6 +73,7 @@ int yaffs_check_tags_ecc(struct yaffs_ta + return 0; + } + ++#if 0 + /********** Tags **********/ + + static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr, +@@ -379,3 +382,214 @@ void yaffs_tags_compat_install(struct ya + if(!dev->tagger.mark_bad_fn) + dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; + } ++#else ++ ++#include "yaffs_packedtags1.h" ++ ++static int yaffs_tags_compat_write(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *data, ++ const struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags1 pt1; ++ u8 tag_buf[9]; ++ int retval; ++ ++ /* we assume that yaffs_packed_tags1 and yaffs_tags are compatible */ ++ compile_time_assertion(sizeof(struct yaffs_packed_tags1) == 12); ++ compile_time_assertion(sizeof(struct yaffs_tags) == 8); ++ ++ yaffs_pack_tags1(&pt1, tags); ++ yaffs_calc_tags_ecc((struct yaffs_tags *)&pt1); ++ ++ /* When deleting a chunk, the upper layer provides only skeletal ++ * tags, one with is_deleted set. However, we need to update the ++ * tags, not erase them completely. So we use the NAND write property ++ * that only zeroed-bits stick and set tag bytes to all-ones and ++ * zero just the (not) deleted bit. ++ */ ++ if (!dev->param.tags_9bytes) { ++ if (tags->is_deleted) { ++ memset(&pt1, 0xff, 8); ++ /* clear delete status bit to indicate deleted */ ++ pt1.deleted = 0; ++ } ++ memcpy(tag_buf, &pt1, 8); ++ } else { ++ if (tags->is_deleted) { ++ memset(tag_buf, 0xff, 8); ++ tag_buf[8] = 0; ++ } else { ++ memcpy(tag_buf, &pt1, 8); ++ tag_buf[8] = 0xff; ++ } ++ } ++ ++ retval = dev->drv.drv_write_chunk_fn(dev, nand_chunk, ++ data, ++ (data) ? dev->data_bytes_per_chunk : 0, ++ tag_buf, ++ (dev->param.tags_9bytes) ? 9 : 8); ++ ++ return retval; ++} ++ ++/* Return with empty extended tags but add ecc_result. ++ */ ++static int return_empty_tags(struct yaffs_ext_tags *tags, ++ enum yaffs_ecc_result ecc_result, ++ int retval) ++{ ++ if (tags) { ++ memset(tags, 0, sizeof(*tags)); ++ tags->ecc_result = ecc_result; ++ } ++ ++ return retval; ++} ++ ++static int yaffs_tags_compat_read(struct yaffs_dev *dev, ++ int nand_chunk, ++ u8 *data, ++ struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags1 pt1; ++ enum yaffs_ecc_result ecc_result; ++ int retval; ++ int deleted; ++ u8 tag_buf[9]; ++ ++ retval = dev->drv.drv_read_chunk_fn(dev, nand_chunk, ++ data, dev->param.total_bytes_per_chunk, ++ tag_buf, ++ (dev->param.tags_9bytes) ? 9 : 8, ++ &ecc_result); ++ ++ switch (ecc_result) { ++ case YAFFS_ECC_RESULT_NO_ERROR: ++ case YAFFS_ECC_RESULT_FIXED: ++ break; ++ ++ case YAFFS_ECC_RESULT_UNFIXED: ++ default: ++ return_empty_tags(tags, YAFFS_ECC_RESULT_UNFIXED, 0); ++ tags->block_bad = dev->drv.drv_check_bad_fn(dev, nand_chunk); ++ return YAFFS_FAIL; ++ } ++ ++ /* Check for a blank/erased chunk. */ ++ if (yaffs_check_ff(tag_buf, 8)) { ++ /* when blank, upper layers want ecc_result to be <= NO_ERROR */ ++ return return_empty_tags(tags, YAFFS_ECC_RESULT_NO_ERROR, ++ YAFFS_OK); ++ } ++ ++ memcpy(&pt1, tag_buf, 8); ++ ++ if (!dev->param.tags_9bytes) { ++ /* Read deleted status (bit) then return it to it's non-deleted ++ * state before performing tags mini-ECC check. pt1.deleted is ++ * inverted. ++ */ ++ deleted = !pt1.deleted; ++ pt1.deleted = 1; ++ } else { ++ deleted = (hweight8(tag_buf[8]) < 7) ? 1 : 0; ++ } ++ ++ /* Check the packed tags mini-ECC and correct if necessary/possible. */ ++ retval = yaffs_check_tags_ecc((struct yaffs_tags *)&pt1); ++ switch (retval) { ++ case 0: ++ /* no tags error, use MTD result */ ++ break; ++ case 1: ++ /* recovered tags-ECC error */ ++ dev->n_tags_ecc_fixed++; ++ if (ecc_result == YAFFS_ECC_RESULT_NO_ERROR) ++ ecc_result = YAFFS_ECC_RESULT_FIXED; ++ break; ++ default: ++ /* unrecovered tags-ECC error */ ++ dev->n_tags_ecc_unfixed++; ++ return return_empty_tags(tags, YAFFS_ECC_RESULT_UNFIXED, ++ YAFFS_FAIL); ++ } ++ ++ /* Unpack the tags to extended form and set ECC result. ++ * [set should_be_ff just to keep yaffs_unpack_tags1 happy] ++ */ ++ pt1.should_be_ff = 0xffffffff; ++ yaffs_unpack_tags1(tags, &pt1); ++ tags->ecc_result = ecc_result; ++ ++ /* Set deleted state */ ++ tags->is_deleted = deleted; ++ return YAFFS_OK; ++} ++ ++static int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no) ++{ ++ return dev->drv.drv_mark_bad_fn(dev, block_no); ++} ++ ++static int yaffs_tags_compat_query_block(struct yaffs_dev *dev, ++ int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number) ++{ ++ struct yaffs_ext_tags tags; ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, "%s %d", __func__, block_no); ++ ++ *seq_number = 0; ++ ++ retval = dev->drv.drv_check_bad_fn(dev, block_no); ++ if (retval == YAFFS_FAIL) { ++ *state = YAFFS_BLOCK_STATE_DEAD; ++ goto out; ++ } ++ ++ yaffs_tags_compat_read(dev, block_no * dev->param.chunks_per_block, ++ NULL, &tags); ++ ++ if (tags.ecc_result != YAFFS_ECC_RESULT_NO_ERROR) { ++ yaffs_trace(YAFFS_TRACE_MTD, "block %d is marked bad", ++ block_no); ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else if (tags.chunk_used) { ++ *seq_number = tags.seq_number; ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else { ++ *state = YAFFS_BLOCK_STATE_EMPTY; ++ } ++ ++ retval = YAFFS_OK; ++ ++out: ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "block query returns seq %u state %d", ++ *seq_number, *state); ++ ++ return retval; ++} ++ ++void yaffs_tags_compat_install(struct yaffs_dev *dev) ++{ ++ if (dev->param.is_yaffs2) ++ return; ++ ++ if (!dev->tagger.write_chunk_tags_fn) ++ dev->tagger.write_chunk_tags_fn = yaffs_tags_compat_write; ++ ++ if (!dev->tagger.read_chunk_tags_fn) ++ dev->tagger.read_chunk_tags_fn = yaffs_tags_compat_read; ++ ++ if (!dev->tagger.query_block_fn) ++ dev->tagger.query_block_fn = yaffs_tags_compat_query_block; ++ ++ if (!dev->tagger.mark_bad_fn) ++ dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; ++} ++#endif diff --git a/target/linux/generic/patches-3.18/503-yaffs-add-tags-9bytes-mount-option.patch b/target/linux/generic/patches-3.18/503-yaffs-add-tags-9bytes-mount-option.patch new file mode 100644 index 0000000..3f51baf --- /dev/null +++ b/target/linux/generic/patches-3.18/503-yaffs-add-tags-9bytes-mount-option.patch @@ -0,0 +1,115 @@ +Subject: yaffs: add support for tags-9bytes mount option + +Signed-off-by: Gabor Juhos +--- +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -2644,6 +2644,7 @@ static const struct super_operations yaf + + struct yaffs_options { + int inband_tags; ++ int tags_9bytes; + int skip_checkpoint_read; + int skip_checkpoint_write; + int no_cache; +@@ -2683,6 +2684,8 @@ static int yaffs_parse_options(struct ya + + if (!strcmp(cur_opt, "inband-tags")) { + options->inband_tags = 1; ++ } else if (!strcmp(cur_opt, "tags-9bytes")) { ++ options->tags_9bytes = 1; + } else if (!strcmp(cur_opt, "tags-ecc-off")) { + options->tags_ecc_on = 0; + options->tags_ecc_overridden = 1; +@@ -2756,7 +2759,6 @@ static struct super_block *yaffs_interna + struct yaffs_param *param; + + int read_only = 0; +- int inband_tags = 0; + + struct yaffs_options options; + +@@ -2796,6 +2798,9 @@ static struct super_block *yaffs_interna + + memset(&options, 0, sizeof(options)); + ++ if (IS_ENABLED(CONFIG_YAFFS_9BYTE_TAGS)) ++ options.tags_9bytes = 1; ++ + if (yaffs_parse_options(&options, data_str)) { + /* Option parsing failed */ + return NULL; +@@ -2829,17 +2834,22 @@ static struct super_block *yaffs_interna + } + + /* Added NCB 26/5/2006 for completeness */ +- if (yaffs_version == 2 && !options.inband_tags +- && WRITE_SIZE(mtd) == 512) { ++ if (yaffs_version == 2 && ++ (!options.inband_tags || options.tags_9bytes) && ++ WRITE_SIZE(mtd) == 512) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting yaffs1"); + yaffs_version = 1; + } + +- if (mtd->oobavail < sizeof(struct yaffs_packed_tags2) || +- options.inband_tags) +- inband_tags = 1; ++ if (yaffs_version == 2 && ++ mtd->oobavail < sizeof(struct yaffs_packed_tags2)) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting inband tags"); ++ options.inband_tags = 1; ++ } + +- if(yaffs_verify_mtd(mtd, yaffs_version, inband_tags) < 0) ++ err = yaffs_verify_mtd(mtd, yaffs_version, options.inband_tags, ++ options.tags_9bytes); ++ if (err < 0) + return NULL; + + /* OK, so if we got here, we have an MTD that's NAND and looks +@@ -2896,7 +2906,8 @@ static struct super_block *yaffs_interna + + param->n_reserved_blocks = 5; + param->n_caches = (options.no_cache) ? 0 : 10; +- param->inband_tags = inband_tags; ++ param->inband_tags = options.inband_tags; ++ param->tags_9bytes = options.tags_9bytes; + + param->enable_xattr = 1; + if (options.lazy_loading_overridden) +--- a/fs/yaffs2/yaffs_mtdif.c ++++ b/fs/yaffs2/yaffs_mtdif.c +@@ -278,7 +278,8 @@ struct mtd_info * yaffs_get_mtd_device(d + return mtd; + } + +-int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags) ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags, ++ int tags_9bytes) + { + if (yaffs_version == 2) { + if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || +@@ -297,6 +298,12 @@ int yaffs_verify_mtd(struct mtd_info *mt + ); + return -1; + } ++ ++ if (tags_9bytes && mtd->oobavail < 9) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "MTD device does not support 9-byte tags"); ++ return -1; ++ } + } + + return 0; +--- a/fs/yaffs2/yaffs_mtdif.h ++++ b/fs/yaffs2/yaffs_mtdif.h +@@ -21,5 +21,6 @@ + void yaffs_mtd_drv_install(struct yaffs_dev *dev); + struct mtd_info * yaffs_get_mtd_device(dev_t sdev); + void yaffs_put_mtd_device(struct mtd_info *mtd); +-int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags); ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags, ++ int tags_9bytes); + #endif diff --git a/target/linux/generic/patches-3.18/504-yaffs-3.16-new-fops.patch b/target/linux/generic/patches-3.18/504-yaffs-3.16-new-fops.patch new file mode 100644 index 0000000..11c6da0 --- /dev/null +++ b/target/linux/generic/patches-3.18/504-yaffs-3.16-new-fops.patch @@ -0,0 +1,25 @@ +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -774,7 +774,21 @@ static int yaffs_sync_object(struct file + } + + +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) ++static const struct file_operations yaffs_file_operations = { ++ .read = new_sync_read, ++ .read_iter = generic_file_read_iter, ++ .write = new_sync_write, ++ .write_iter = generic_file_write_iter, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++ .splice_read = generic_file_splice_read, ++ .splice_write = iter_file_splice_write, ++ .llseek = generic_file_llseek, ++}; ++ ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) + static const struct file_operations yaffs_file_operations = { + .read = do_sync_read, + .write = do_sync_write, diff --git a/target/linux/generic/patches-3.18/520-squashfs_update_xz_comp_opts.patch b/target/linux/generic/patches-3.18/520-squashfs_update_xz_comp_opts.patch new file mode 100644 index 0000000..ad11b30 --- /dev/null +++ b/target/linux/generic/patches-3.18/520-squashfs_update_xz_comp_opts.patch @@ -0,0 +1,25 @@ +From f31b7c0efa255dd17a5f584022a319387f09b0d8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 12 Apr 2011 19:55:41 +0200 +Subject: [PATCH] squashfs: update xz compressor options struct. + +Update the xz compressor options struct to match the squashfs userspace +one. +--- + fs/squashfs/xz_wrapper.c | 4 +++- + 1 files changed, 3 insertions(+), 1 deletions(-) + +--- a/fs/squashfs/xz_wrapper.c ++++ b/fs/squashfs/xz_wrapper.c +@@ -40,8 +40,10 @@ struct squashfs_xz { + }; + + struct disk_comp_opts { +- __le32 dictionary_size; + __le32 flags; ++ __le16 bit_opts; ++ __le16 fb; ++ __le32 dictionary_size; + }; + + struct comp_opts { diff --git a/target/linux/generic/patches-3.18/530-jffs2_make_lzma_available.patch b/target/linux/generic/patches-3.18/530-jffs2_make_lzma_available.patch new file mode 100644 index 0000000..c92209a --- /dev/null +++ b/target/linux/generic/patches-3.18/530-jffs2_make_lzma_available.patch @@ -0,0 +1,5142 @@ +--- a/fs/jffs2/Kconfig ++++ b/fs/jffs2/Kconfig +@@ -139,6 +139,15 @@ config JFFS2_LZO + This feature was added in July, 2007. Say 'N' if you need + compatibility with older bootloaders or kernels. + ++config JFFS2_LZMA ++ bool "JFFS2 LZMA compression support" if JFFS2_COMPRESSION_OPTIONS ++ select LZMA_COMPRESS ++ select LZMA_DECOMPRESS ++ depends on JFFS2_FS ++ default n ++ help ++ JFFS2 wrapper to the LZMA C SDK ++ + config JFFS2_RTIME + bool "JFFS2 RTIME compression support" if JFFS2_COMPRESSION_OPTIONS + depends on JFFS2_FS +--- a/fs/jffs2/Makefile ++++ b/fs/jffs2/Makefile +@@ -18,4 +18,7 @@ jffs2-$(CONFIG_JFFS2_RUBIN) += compr_rub + jffs2-$(CONFIG_JFFS2_RTIME) += compr_rtime.o + jffs2-$(CONFIG_JFFS2_ZLIB) += compr_zlib.o + jffs2-$(CONFIG_JFFS2_LZO) += compr_lzo.o ++jffs2-$(CONFIG_JFFS2_LZMA) += compr_lzma.o + jffs2-$(CONFIG_JFFS2_SUMMARY) += summary.o ++ ++CFLAGS_compr_lzma.o += -Iinclude/linux -Ilib/lzma +--- a/fs/jffs2/compr.c ++++ b/fs/jffs2/compr.c +@@ -378,6 +378,9 @@ int __init jffs2_compressors_init(void) + #ifdef CONFIG_JFFS2_LZO + jffs2_lzo_init(); + #endif ++#ifdef CONFIG_JFFS2_LZMA ++ jffs2_lzma_init(); ++#endif + /* Setting default compression mode */ + #ifdef CONFIG_JFFS2_CMODE_NONE + jffs2_compression_mode = JFFS2_COMPR_MODE_NONE; +@@ -401,6 +404,9 @@ int __init jffs2_compressors_init(void) + int jffs2_compressors_exit(void) + { + /* Unregistering compressors */ ++#ifdef CONFIG_JFFS2_LZMA ++ jffs2_lzma_exit(); ++#endif + #ifdef CONFIG_JFFS2_LZO + jffs2_lzo_exit(); + #endif +--- a/fs/jffs2/compr.h ++++ b/fs/jffs2/compr.h +@@ -29,9 +29,9 @@ + #define JFFS2_DYNRUBIN_PRIORITY 20 + #define JFFS2_LZARI_PRIORITY 30 + #define JFFS2_RTIME_PRIORITY 50 +-#define JFFS2_ZLIB_PRIORITY 60 +-#define JFFS2_LZO_PRIORITY 80 +- ++#define JFFS2_LZMA_PRIORITY 70 ++#define JFFS2_ZLIB_PRIORITY 80 ++#define JFFS2_LZO_PRIORITY 90 + + #define JFFS2_RUBINMIPS_DISABLED /* RUBINs will be used only */ + #define JFFS2_DYNRUBIN_DISABLED /* for decompression */ +@@ -101,5 +101,9 @@ void jffs2_zlib_exit(void); + int jffs2_lzo_init(void); + void jffs2_lzo_exit(void); + #endif ++#ifdef CONFIG_JFFS2_LZMA ++int jffs2_lzma_init(void); ++void jffs2_lzma_exit(void); ++#endif + + #endif /* __JFFS2_COMPR_H__ */ +--- /dev/null ++++ b/fs/jffs2/compr_lzma.c +@@ -0,0 +1,128 @@ ++/* ++ * JFFS2 -- Journalling Flash File System, Version 2. ++ * ++ * For licensing information, see the file 'LICENCE' in this directory. ++ * ++ * JFFS2 wrapper to the LZMA C SDK ++ * ++ */ ++ ++#include ++#include "compr.h" ++ ++#ifdef __KERNEL__ ++ static DEFINE_MUTEX(deflate_mutex); ++#endif ++ ++CLzmaEncHandle *p; ++Byte propsEncoded[LZMA_PROPS_SIZE]; ++SizeT propsSize = sizeof(propsEncoded); ++ ++STATIC void lzma_free_workspace(void) ++{ ++ LzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc); ++} ++ ++STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props) ++{ ++ if ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL) ++ { ++ PRINT_ERROR("Failed to allocate lzma deflate workspace\n"); ++ return -ENOMEM; ++ } ++ ++ if (LzmaEnc_SetProps(p, props) != SZ_OK) ++ { ++ lzma_free_workspace(); ++ return -1; ++ } ++ ++ if (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK) ++ { ++ lzma_free_workspace(); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out, ++ uint32_t *sourcelen, uint32_t *dstlen) ++{ ++ SizeT compress_size = (SizeT)(*dstlen); ++ int ret; ++ ++ #ifdef __KERNEL__ ++ mutex_lock(&deflate_mutex); ++ #endif ++ ++ ret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen, ++ 0, NULL, &lzma_alloc, &lzma_alloc); ++ ++ #ifdef __KERNEL__ ++ mutex_unlock(&deflate_mutex); ++ #endif ++ ++ if (ret != SZ_OK) ++ return -1; ++ ++ *dstlen = (uint32_t)compress_size; ++ ++ return 0; ++} ++ ++STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out, ++ uint32_t srclen, uint32_t destlen) ++{ ++ int ret; ++ SizeT dl = (SizeT)destlen; ++ SizeT sl = (SizeT)srclen; ++ ELzmaStatus status; ++ ++ ret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded, ++ propsSize, LZMA_FINISH_ANY, &status, &lzma_alloc); ++ ++ if (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen) ++ return -1; ++ ++ return 0; ++} ++ ++static struct jffs2_compressor jffs2_lzma_comp = { ++ .priority = JFFS2_LZMA_PRIORITY, ++ .name = "lzma", ++ .compr = JFFS2_COMPR_LZMA, ++ .compress = &jffs2_lzma_compress, ++ .decompress = &jffs2_lzma_decompress, ++ .disabled = 0, ++}; ++ ++int INIT jffs2_lzma_init(void) ++{ ++ int ret; ++ CLzmaEncProps props; ++ LzmaEncProps_Init(&props); ++ ++ props.dictSize = LZMA_BEST_DICT(0x2000); ++ props.level = LZMA_BEST_LEVEL; ++ props.lc = LZMA_BEST_LC; ++ props.lp = LZMA_BEST_LP; ++ props.pb = LZMA_BEST_PB; ++ props.fb = LZMA_BEST_FB; ++ ++ ret = lzma_alloc_workspace(&props); ++ if (ret < 0) ++ return ret; ++ ++ ret = jffs2_register_compressor(&jffs2_lzma_comp); ++ if (ret) ++ lzma_free_workspace(); ++ ++ return ret; ++} ++ ++void jffs2_lzma_exit(void) ++{ ++ jffs2_unregister_compressor(&jffs2_lzma_comp); ++ lzma_free_workspace(); ++} +--- a/fs/jffs2/super.c ++++ b/fs/jffs2/super.c +@@ -375,14 +375,41 @@ static int __init init_jffs2_fs(void) + BUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68); + BUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32); + +- pr_info("version 2.2." ++ pr_info("version 2.2" + #ifdef CONFIG_JFFS2_FS_WRITEBUFFER + " (NAND)" + #endif + #ifdef CONFIG_JFFS2_SUMMARY +- " (SUMMARY) " ++ " (SUMMARY)" + #endif +- " © 2001-2006 Red Hat, Inc.\n"); ++#ifdef CONFIG_JFFS2_ZLIB ++ " (ZLIB)" ++#endif ++#ifdef CONFIG_JFFS2_LZO ++ " (LZO)" ++#endif ++#ifdef CONFIG_JFFS2_LZMA ++ " (LZMA)" ++#endif ++#ifdef CONFIG_JFFS2_RTIME ++ " (RTIME)" ++#endif ++#ifdef CONFIG_JFFS2_RUBIN ++ " (RUBIN)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_NONE ++ " (CMODE_NONE)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_PRIORITY ++ " (CMODE_PRIORITY)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_SIZE ++ " (CMODE_SIZE)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_FAVOURLZO ++ " (CMODE_FAVOURLZO)" ++#endif ++ " (c) 2001-2006 Red Hat, Inc.\n"); + + jffs2_inode_cachep = kmem_cache_create("jffs2_i", + sizeof(struct jffs2_inode_info), +--- a/include/uapi/linux/jffs2.h ++++ b/include/uapi/linux/jffs2.h +@@ -46,6 +46,7 @@ + #define JFFS2_COMPR_DYNRUBIN 0x05 + #define JFFS2_COMPR_ZLIB 0x06 + #define JFFS2_COMPR_LZO 0x07 ++#define JFFS2_COMPR_LZMA 0x08 + /* Compatibility flags. */ + #define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ + #define JFFS2_NODE_ACCURATE 0x2000 +--- /dev/null ++++ b/include/linux/lzma.h +@@ -0,0 +1,62 @@ ++#ifndef __LZMA_H__ ++#define __LZMA_H__ ++ ++#ifdef __KERNEL__ ++ #include ++ #include ++ #include ++ #include ++ #include ++ #define LZMA_MALLOC vmalloc ++ #define LZMA_FREE vfree ++ #define PRINT_ERROR(msg) printk(KERN_WARNING #msg) ++ #define INIT __init ++ #define STATIC static ++#else ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #ifndef PAGE_SIZE ++ extern int page_size; ++ #define PAGE_SIZE page_size ++ #endif ++ #define LZMA_MALLOC malloc ++ #define LZMA_FREE free ++ #define PRINT_ERROR(msg) fprintf(stderr, msg) ++ #define INIT ++ #define STATIC ++#endif ++ ++#include "lzma/LzmaDec.h" ++#include "lzma/LzmaEnc.h" ++ ++#define LZMA_BEST_LEVEL (9) ++#define LZMA_BEST_LC (0) ++#define LZMA_BEST_LP (0) ++#define LZMA_BEST_PB (0) ++#define LZMA_BEST_FB (273) ++ ++#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2) ++ ++static void *p_lzma_malloc(void *p, size_t size) ++{ ++ if (size == 0) ++ return NULL; ++ ++ return LZMA_MALLOC(size); ++} ++ ++static void p_lzma_free(void *p, void *address) ++{ ++ if (address != NULL) ++ LZMA_FREE(address); ++} ++ ++static ISzAlloc lzma_alloc = {p_lzma_malloc, p_lzma_free}; ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzFind.h +@@ -0,0 +1,115 @@ ++/* LzFind.h -- Match finder for LZ algorithms ++2009-04-22 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZ_FIND_H ++#define __LZ_FIND_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef UInt32 CLzRef; ++ ++typedef struct _CMatchFinder ++{ ++ Byte *buffer; ++ UInt32 pos; ++ UInt32 posLimit; ++ UInt32 streamPos; ++ UInt32 lenLimit; ++ ++ UInt32 cyclicBufferPos; ++ UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */ ++ ++ UInt32 matchMaxLen; ++ CLzRef *hash; ++ CLzRef *son; ++ UInt32 hashMask; ++ UInt32 cutValue; ++ ++ Byte *bufferBase; ++ ISeqInStream *stream; ++ int streamEndWasReached; ++ ++ UInt32 blockSize; ++ UInt32 keepSizeBefore; ++ UInt32 keepSizeAfter; ++ ++ UInt32 numHashBytes; ++ int directInput; ++ size_t directInputRem; ++ int btMode; ++ int bigHash; ++ UInt32 historySize; ++ UInt32 fixedHashSize; ++ UInt32 hashSizeSum; ++ UInt32 numSons; ++ SRes result; ++ UInt32 crc[256]; ++} CMatchFinder; ++ ++#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer) ++#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)]) ++ ++#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) ++ ++int MatchFinder_NeedMove(CMatchFinder *p); ++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p); ++void MatchFinder_MoveBlock(CMatchFinder *p); ++void MatchFinder_ReadIfRequired(CMatchFinder *p); ++ ++void MatchFinder_Construct(CMatchFinder *p); ++ ++/* Conditions: ++ historySize <= 3 GB ++ keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB ++*/ ++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, ++ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, ++ ISzAlloc *alloc); ++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); ++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems); ++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue); ++ ++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, ++ UInt32 *distances, UInt32 maxLen); ++ ++/* ++Conditions: ++ Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func. ++ Mf_GetPointerToCurrentPos_Func's result must be used only before any other function ++*/ ++ ++typedef void (*Mf_Init_Func)(void *object); ++typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index); ++typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object); ++typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object); ++typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances); ++typedef void (*Mf_Skip_Func)(void *object, UInt32); ++ ++typedef struct _IMatchFinder ++{ ++ Mf_Init_Func Init; ++ Mf_GetIndexByte_Func GetIndexByte; ++ Mf_GetNumAvailableBytes_Func GetNumAvailableBytes; ++ Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos; ++ Mf_GetMatches_Func GetMatches; ++ Mf_Skip_Func Skip; ++} IMatchFinder; ++ ++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); ++ ++void MatchFinder_Init(CMatchFinder *p); ++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); ++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); ++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); ++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzHash.h +@@ -0,0 +1,54 @@ ++/* LzHash.h -- HASH functions for LZ algorithms ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZ_HASH_H ++#define __LZ_HASH_H ++ ++#define kHash2Size (1 << 10) ++#define kHash3Size (1 << 16) ++#define kHash4Size (1 << 20) ++ ++#define kFix3HashSize (kHash2Size) ++#define kFix4HashSize (kHash2Size + kHash3Size) ++#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size) ++ ++#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8); ++ ++#define HASH3_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; } ++ ++#define HASH4_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; } ++ ++#define HASH5_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \ ++ hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \ ++ hash4Value &= (kHash4Size - 1); } ++ ++/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */ ++#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF; ++ ++ ++#define MT_HASH2_CALC \ ++ hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1); ++ ++#define MT_HASH3_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); } ++ ++#define MT_HASH4_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); } ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzmaDec.h +@@ -0,0 +1,231 @@ ++/* LzmaDec.h -- LZMA Decoder ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZMA_DEC_H ++#define __LZMA_DEC_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* #define _LZMA_PROB32 */ ++/* _LZMA_PROB32 can increase the speed on some CPUs, ++ but memory usage for CLzmaDec::probs will be doubled in that case */ ++ ++#ifdef _LZMA_PROB32 ++#define CLzmaProb UInt32 ++#else ++#define CLzmaProb UInt16 ++#endif ++ ++ ++/* ---------- LZMA Properties ---------- */ ++ ++#define LZMA_PROPS_SIZE 5 ++ ++typedef struct _CLzmaProps ++{ ++ unsigned lc, lp, pb; ++ UInt32 dicSize; ++} CLzmaProps; ++ ++/* LzmaProps_Decode - decodes properties ++Returns: ++ SZ_OK ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++*/ ++ ++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); ++ ++ ++/* ---------- LZMA Decoder state ---------- */ ++ ++/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case. ++ Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */ ++ ++#define LZMA_REQUIRED_INPUT_MAX 20 ++ ++typedef struct ++{ ++ CLzmaProps prop; ++ CLzmaProb *probs; ++ Byte *dic; ++ const Byte *buf; ++ UInt32 range, code; ++ SizeT dicPos; ++ SizeT dicBufSize; ++ UInt32 processedPos; ++ UInt32 checkDicSize; ++ unsigned state; ++ UInt32 reps[4]; ++ unsigned remainLen; ++ int needFlush; ++ int needInitState; ++ UInt32 numProbs; ++ unsigned tempBufSize; ++ Byte tempBuf[LZMA_REQUIRED_INPUT_MAX]; ++} CLzmaDec; ++ ++#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } ++ ++void LzmaDec_Init(CLzmaDec *p); ++ ++/* There are two types of LZMA streams: ++ 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. ++ 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ ++ ++typedef enum ++{ ++ LZMA_FINISH_ANY, /* finish at any point */ ++ LZMA_FINISH_END /* block must be finished at the end */ ++} ELzmaFinishMode; ++ ++/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!! ++ ++ You must use LZMA_FINISH_END, when you know that current output buffer ++ covers last bytes of block. In other cases you must use LZMA_FINISH_ANY. ++ ++ If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK, ++ and output value of destLen will be less than output buffer size limit. ++ You can check status result also. ++ ++ You can use multiple checks to test data integrity after full decompression: ++ 1) Check Result and "status" variable. ++ 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize. ++ 3) Check that output(srcLen) = compressedSize, if you know real compressedSize. ++ You must use correct finish mode in that case. */ ++ ++typedef enum ++{ ++ LZMA_STATUS_NOT_SPECIFIED, /* use main error code instead */ ++ LZMA_STATUS_FINISHED_WITH_MARK, /* stream was finished with end mark. */ ++ LZMA_STATUS_NOT_FINISHED, /* stream was not finished */ ++ LZMA_STATUS_NEEDS_MORE_INPUT, /* you must provide more input bytes */ ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK /* there is probability that stream was finished without end mark */ ++} ELzmaStatus; ++ ++/* ELzmaStatus is used only as output value for function call */ ++ ++ ++/* ---------- Interfaces ---------- */ ++ ++/* There are 3 levels of interfaces: ++ 1) Dictionary Interface ++ 2) Buffer Interface ++ 3) One Call Interface ++ You can select any of these interfaces, but don't mix functions from different ++ groups for same object. */ ++ ++ ++/* There are two variants to allocate state for Dictionary Interface: ++ 1) LzmaDec_Allocate / LzmaDec_Free ++ 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs ++ You can use variant 2, if you set dictionary buffer manually. ++ For Buffer Interface you must always use variant 1. ++ ++LzmaDec_Allocate* can return: ++ SZ_OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++*/ ++ ++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); ++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); ++ ++SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); ++void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); ++ ++/* ---------- Dictionary Interface ---------- */ ++ ++/* You can use it, if you want to eliminate the overhead for data copying from ++ dictionary to some other external buffer. ++ You must work with CLzmaDec variables directly in this interface. ++ ++ STEPS: ++ LzmaDec_Constr() ++ LzmaDec_Allocate() ++ for (each new stream) ++ { ++ LzmaDec_Init() ++ while (it needs more decompression) ++ { ++ LzmaDec_DecodeToDic() ++ use data from CLzmaDec::dic and update CLzmaDec::dicPos ++ } ++ } ++ LzmaDec_Free() ++*/ ++ ++/* LzmaDec_DecodeToDic ++ ++ The decoding to internal dictionary buffer (CLzmaDec::dic). ++ You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (dicLimit). ++ LZMA_FINISH_ANY - Decode just dicLimit bytes. ++ LZMA_FINISH_END - Stream must be finished after dicLimit. ++ ++Returns: ++ SZ_OK ++ status: ++ LZMA_STATUS_FINISHED_WITH_MARK ++ LZMA_STATUS_NOT_FINISHED ++ LZMA_STATUS_NEEDS_MORE_INPUT ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK ++ SZ_ERROR_DATA - Data error ++*/ ++ ++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, ++ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); ++ ++ ++/* ---------- Buffer Interface ---------- */ ++ ++/* It's zlib-like interface. ++ See LzmaDec_DecodeToDic description for information about STEPS and return results, ++ but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need ++ to work with CLzmaDec variables manually. ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (*destLen). ++ LZMA_FINISH_ANY - Decode just destLen bytes. ++ LZMA_FINISH_END - Stream must be finished after (*destLen). ++*/ ++ ++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, ++ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); ++ ++ ++/* ---------- One Call Interface ---------- */ ++ ++/* LzmaDecode ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (*destLen). ++ LZMA_FINISH_ANY - Decode just destLen bytes. ++ LZMA_FINISH_END - Stream must be finished after (*destLen). ++ ++Returns: ++ SZ_OK ++ status: ++ LZMA_STATUS_FINISHED_WITH_MARK ++ LZMA_STATUS_NOT_FINISHED ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK ++ SZ_ERROR_DATA - Data error ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++ SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src). ++*/ ++ ++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ++ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, ++ ELzmaStatus *status, ISzAlloc *alloc); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzmaEnc.h +@@ -0,0 +1,80 @@ ++/* LzmaEnc.h -- LZMA Encoder ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZMA_ENC_H ++#define __LZMA_ENC_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define LZMA_PROPS_SIZE 5 ++ ++typedef struct _CLzmaEncProps ++{ ++ int level; /* 0 <= level <= 9 */ ++ UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version ++ (1 << 12) <= dictSize <= (1 << 30) for 64-bit version ++ default = (1 << 24) */ ++ int lc; /* 0 <= lc <= 8, default = 3 */ ++ int lp; /* 0 <= lp <= 4, default = 0 */ ++ int pb; /* 0 <= pb <= 4, default = 2 */ ++ int algo; /* 0 - fast, 1 - normal, default = 1 */ ++ int fb; /* 5 <= fb <= 273, default = 32 */ ++ int btMode; /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */ ++ int numHashBytes; /* 2, 3 or 4, default = 4 */ ++ UInt32 mc; /* 1 <= mc <= (1 << 30), default = 32 */ ++ unsigned writeEndMark; /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */ ++ int numThreads; /* 1 or 2, default = 2 */ ++} CLzmaEncProps; ++ ++void LzmaEncProps_Init(CLzmaEncProps *p); ++void LzmaEncProps_Normalize(CLzmaEncProps *p); ++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2); ++ ++ ++/* ---------- CLzmaEncHandle Interface ---------- */ ++ ++/* LzmaEnc_* functions can return the following exit codes: ++Returns: ++ SZ_OK - OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_PARAM - Incorrect paramater in props ++ SZ_ERROR_WRITE - Write callback error. ++ SZ_ERROR_PROGRESS - some break from progress callback ++ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) ++*/ ++ ++typedef void * CLzmaEncHandle; ++ ++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc); ++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); ++SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); ++SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); ++SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++ ++/* ---------- One Call Interface ---------- */ ++ ++/* LzmaEncode ++Return code: ++ SZ_OK - OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_PARAM - Incorrect paramater ++ SZ_ERROR_OUTPUT_EOF - output buffer overflow ++ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) ++*/ ++ ++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/Types.h +@@ -0,0 +1,226 @@ ++/* Types.h -- Basic types ++2009-11-23 : Igor Pavlov : Public domain */ ++ ++#ifndef __7Z_TYPES_H ++#define __7Z_TYPES_H ++ ++#include ++ ++#ifdef _WIN32 ++#include ++#endif ++ ++#ifndef EXTERN_C_BEGIN ++#ifdef __cplusplus ++#define EXTERN_C_BEGIN extern "C" { ++#define EXTERN_C_END } ++#else ++#define EXTERN_C_BEGIN ++#define EXTERN_C_END ++#endif ++#endif ++ ++EXTERN_C_BEGIN ++ ++#define SZ_OK 0 ++ ++#define SZ_ERROR_DATA 1 ++#define SZ_ERROR_MEM 2 ++#define SZ_ERROR_CRC 3 ++#define SZ_ERROR_UNSUPPORTED 4 ++#define SZ_ERROR_PARAM 5 ++#define SZ_ERROR_INPUT_EOF 6 ++#define SZ_ERROR_OUTPUT_EOF 7 ++#define SZ_ERROR_READ 8 ++#define SZ_ERROR_WRITE 9 ++#define SZ_ERROR_PROGRESS 10 ++#define SZ_ERROR_FAIL 11 ++#define SZ_ERROR_THREAD 12 ++ ++#define SZ_ERROR_ARCHIVE 16 ++#define SZ_ERROR_NO_ARCHIVE 17 ++ ++typedef int SRes; ++ ++#ifdef _WIN32 ++typedef DWORD WRes; ++#else ++typedef int WRes; ++#endif ++ ++#ifndef RINOK ++#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; } ++#endif ++ ++typedef unsigned char Byte; ++typedef short Int16; ++typedef unsigned short UInt16; ++ ++#ifdef _LZMA_UINT32_IS_ULONG ++typedef long Int32; ++typedef unsigned long UInt32; ++#else ++typedef int Int32; ++typedef unsigned int UInt32; ++#endif ++ ++#ifdef _SZ_NO_INT_64 ++ ++/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers. ++ NOTES: Some code will work incorrectly in that case! */ ++ ++typedef long Int64; ++typedef unsigned long UInt64; ++ ++#else ++ ++#if defined(_MSC_VER) || defined(__BORLANDC__) ++typedef __int64 Int64; ++typedef unsigned __int64 UInt64; ++#else ++typedef long long int Int64; ++typedef unsigned long long int UInt64; ++#endif ++ ++#endif ++ ++#ifdef _LZMA_NO_SYSTEM_SIZE_T ++typedef UInt32 SizeT; ++#else ++typedef size_t SizeT; ++#endif ++ ++typedef int Bool; ++#define True 1 ++#define False 0 ++ ++ ++#ifdef _WIN32 ++#define MY_STD_CALL __stdcall ++#else ++#define MY_STD_CALL ++#endif ++ ++#ifdef _MSC_VER ++ ++#if _MSC_VER >= 1300 ++#define MY_NO_INLINE __declspec(noinline) ++#else ++#define MY_NO_INLINE ++#endif ++ ++#define MY_CDECL __cdecl ++#define MY_FAST_CALL __fastcall ++ ++#else ++ ++#define MY_CDECL ++#define MY_FAST_CALL ++ ++#endif ++ ++ ++/* The following interfaces use first parameter as pointer to structure */ ++ ++typedef struct ++{ ++ SRes (*Read)(void *p, void *buf, size_t *size); ++ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. ++ (output(*size) < input(*size)) is allowed */ ++} ISeqInStream; ++ ++/* it can return SZ_ERROR_INPUT_EOF */ ++SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size); ++SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType); ++SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf); ++ ++typedef struct ++{ ++ size_t (*Write)(void *p, const void *buf, size_t size); ++ /* Returns: result - the number of actually written bytes. ++ (result < size) means error */ ++} ISeqOutStream; ++ ++typedef enum ++{ ++ SZ_SEEK_SET = 0, ++ SZ_SEEK_CUR = 1, ++ SZ_SEEK_END = 2 ++} ESzSeek; ++ ++typedef struct ++{ ++ SRes (*Read)(void *p, void *buf, size_t *size); /* same as ISeqInStream::Read */ ++ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); ++} ISeekInStream; ++ ++typedef struct ++{ ++ SRes (*Look)(void *p, void **buf, size_t *size); ++ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. ++ (output(*size) > input(*size)) is not allowed ++ (output(*size) < input(*size)) is allowed */ ++ SRes (*Skip)(void *p, size_t offset); ++ /* offset must be <= output(*size) of Look */ ++ ++ SRes (*Read)(void *p, void *buf, size_t *size); ++ /* reads directly (without buffer). It's same as ISeqInStream::Read */ ++ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); ++} ILookInStream; ++ ++SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size); ++SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset); ++ ++/* reads via ILookInStream::Read */ ++SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType); ++SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size); ++ ++#define LookToRead_BUF_SIZE (1 << 14) ++ ++typedef struct ++{ ++ ILookInStream s; ++ ISeekInStream *realStream; ++ size_t pos; ++ size_t size; ++ Byte buf[LookToRead_BUF_SIZE]; ++} CLookToRead; ++ ++void LookToRead_CreateVTable(CLookToRead *p, int lookahead); ++void LookToRead_Init(CLookToRead *p); ++ ++typedef struct ++{ ++ ISeqInStream s; ++ ILookInStream *realStream; ++} CSecToLook; ++ ++void SecToLook_CreateVTable(CSecToLook *p); ++ ++typedef struct ++{ ++ ISeqInStream s; ++ ILookInStream *realStream; ++} CSecToRead; ++ ++void SecToRead_CreateVTable(CSecToRead *p); ++ ++typedef struct ++{ ++ SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize); ++ /* Returns: result. (result != SZ_OK) means break. ++ Value (UInt64)(Int64)-1 for size means unknown value. */ ++} ICompressProgress; ++ ++typedef struct ++{ ++ void *(*Alloc)(void *p, size_t size); ++ void (*Free)(void *p, void *address); /* address can be 0 */ ++} ISzAlloc; ++ ++#define IAlloc_Alloc(p, size) (p)->Alloc((p), size) ++#define IAlloc_Free(p, a) (p)->Free((p), a) ++ ++EXTERN_C_END ++ ++#endif +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -227,6 +227,12 @@ config LZ4_DECOMPRESS + + source "lib/xz/Kconfig" + ++config LZMA_COMPRESS ++ tristate ++ ++config LZMA_DECOMPRESS ++ tristate ++ + # + # These all provide a common interface (hence the apparent duplication with + # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -2,6 +2,16 @@ + # Makefile for some libs needed in the kernel. + # + ++ifdef CONFIG_JFFS2_ZLIB ++ CONFIG_ZLIB_INFLATE:=y ++ CONFIG_ZLIB_DEFLATE:=y ++endif ++ ++ifdef CONFIG_JFFS2_LZMA ++ CONFIG_LZMA_DECOMPRESS:=y ++ CONFIG_LZMA_COMPRESS:=y ++endif ++ + ifdef CONFIG_FUNCTION_TRACER + ORIG_CFLAGS := $(KBUILD_CFLAGS) + KBUILD_CFLAGS = $(subst -pg,,$(ORIG_CFLAGS)) +@@ -85,6 +95,8 @@ obj-$(CONFIG_LZ4HC_COMPRESS) += lz4/ + obj-$(CONFIG_LZ4_DECOMPRESS) += lz4/ + obj-$(CONFIG_XZ_DEC) += xz/ + obj-$(CONFIG_RAID6_PQ) += raid6/ ++obj-$(CONFIG_LZMA_COMPRESS) += lzma/ ++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ + + lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o + lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o +--- /dev/null ++++ b/lib/lzma/LzFind.c +@@ -0,0 +1,761 @@ ++/* LzFind.c -- Match finder for LZ algorithms ++2009-04-22 : Igor Pavlov : Public domain */ ++ ++#include ++ ++#include "LzFind.h" ++#include "LzHash.h" ++ ++#define kEmptyHashValue 0 ++#define kMaxValForNormalize ((UInt32)0xFFFFFFFF) ++#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */ ++#define kNormalizeMask (~(kNormalizeStepMin - 1)) ++#define kMaxHistorySize ((UInt32)3 << 30) ++ ++#define kStartMaxLen 3 ++ ++static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ if (!p->directInput) ++ { ++ alloc->Free(alloc, p->bufferBase); ++ p->bufferBase = 0; ++ } ++} ++ ++/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */ ++ ++static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) ++{ ++ UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; ++ if (p->directInput) ++ { ++ p->blockSize = blockSize; ++ return 1; ++ } ++ if (p->bufferBase == 0 || p->blockSize != blockSize) ++ { ++ LzInWindow_Free(p, alloc); ++ p->blockSize = blockSize; ++ p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize); ++ } ++ return (p->bufferBase != 0); ++} ++ ++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } ++Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } ++ ++UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } ++ ++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) ++{ ++ p->posLimit -= subValue; ++ p->pos -= subValue; ++ p->streamPos -= subValue; ++} ++ ++static void MatchFinder_ReadBlock(CMatchFinder *p) ++{ ++ if (p->streamEndWasReached || p->result != SZ_OK) ++ return; ++ if (p->directInput) ++ { ++ UInt32 curSize = 0xFFFFFFFF - p->streamPos; ++ if (curSize > p->directInputRem) ++ curSize = (UInt32)p->directInputRem; ++ p->directInputRem -= curSize; ++ p->streamPos += curSize; ++ if (p->directInputRem == 0) ++ p->streamEndWasReached = 1; ++ return; ++ } ++ for (;;) ++ { ++ Byte *dest = p->buffer + (p->streamPos - p->pos); ++ size_t size = (p->bufferBase + p->blockSize - dest); ++ if (size == 0) ++ return; ++ p->result = p->stream->Read(p->stream, dest, &size); ++ if (p->result != SZ_OK) ++ return; ++ if (size == 0) ++ { ++ p->streamEndWasReached = 1; ++ return; ++ } ++ p->streamPos += (UInt32)size; ++ if (p->streamPos - p->pos > p->keepSizeAfter) ++ return; ++ } ++} ++ ++void MatchFinder_MoveBlock(CMatchFinder *p) ++{ ++ memmove(p->bufferBase, ++ p->buffer - p->keepSizeBefore, ++ (size_t)(p->streamPos - p->pos + p->keepSizeBefore)); ++ p->buffer = p->bufferBase + p->keepSizeBefore; ++} ++ ++int MatchFinder_NeedMove(CMatchFinder *p) ++{ ++ if (p->directInput) ++ return 0; ++ /* if (p->streamEndWasReached) return 0; */ ++ return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); ++} ++ ++void MatchFinder_ReadIfRequired(CMatchFinder *p) ++{ ++ if (p->streamEndWasReached) ++ return; ++ if (p->keepSizeAfter >= p->streamPos - p->pos) ++ MatchFinder_ReadBlock(p); ++} ++ ++static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) ++{ ++ if (MatchFinder_NeedMove(p)) ++ MatchFinder_MoveBlock(p); ++ MatchFinder_ReadBlock(p); ++} ++ ++static void MatchFinder_SetDefaultSettings(CMatchFinder *p) ++{ ++ p->cutValue = 32; ++ p->btMode = 1; ++ p->numHashBytes = 4; ++ p->bigHash = 0; ++} ++ ++#define kCrcPoly 0xEDB88320 ++ ++void MatchFinder_Construct(CMatchFinder *p) ++{ ++ UInt32 i; ++ p->bufferBase = 0; ++ p->directInput = 0; ++ p->hash = 0; ++ MatchFinder_SetDefaultSettings(p); ++ ++ for (i = 0; i < 256; i++) ++ { ++ UInt32 r = i; ++ int j; ++ for (j = 0; j < 8; j++) ++ r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1)); ++ p->crc[i] = r; ++ } ++} ++ ++static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->hash); ++ p->hash = 0; ++} ++ ++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ MatchFinder_FreeThisClassMemory(p, alloc); ++ LzInWindow_Free(p, alloc); ++} ++ ++static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc) ++{ ++ size_t sizeInBytes = (size_t)num * sizeof(CLzRef); ++ if (sizeInBytes / sizeof(CLzRef) != num) ++ return 0; ++ return (CLzRef *)alloc->Alloc(alloc, sizeInBytes); ++} ++ ++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, ++ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, ++ ISzAlloc *alloc) ++{ ++ UInt32 sizeReserv; ++ if (historySize > kMaxHistorySize) ++ { ++ MatchFinder_Free(p, alloc); ++ return 0; ++ } ++ sizeReserv = historySize >> 1; ++ if (historySize > ((UInt32)2 << 30)) ++ sizeReserv = historySize >> 2; ++ sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19); ++ ++ p->keepSizeBefore = historySize + keepAddBufferBefore + 1; ++ p->keepSizeAfter = matchMaxLen + keepAddBufferAfter; ++ /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */ ++ if (LzInWindow_Create(p, sizeReserv, alloc)) ++ { ++ UInt32 newCyclicBufferSize = historySize + 1; ++ UInt32 hs; ++ p->matchMaxLen = matchMaxLen; ++ { ++ p->fixedHashSize = 0; ++ if (p->numHashBytes == 2) ++ hs = (1 << 16) - 1; ++ else ++ { ++ hs = historySize - 1; ++ hs |= (hs >> 1); ++ hs |= (hs >> 2); ++ hs |= (hs >> 4); ++ hs |= (hs >> 8); ++ hs >>= 1; ++ hs |= 0xFFFF; /* don't change it! It's required for Deflate */ ++ if (hs > (1 << 24)) ++ { ++ if (p->numHashBytes == 3) ++ hs = (1 << 24) - 1; ++ else ++ hs >>= 1; ++ } ++ } ++ p->hashMask = hs; ++ hs++; ++ if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size; ++ if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size; ++ if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size; ++ hs += p->fixedHashSize; ++ } ++ ++ { ++ UInt32 prevSize = p->hashSizeSum + p->numSons; ++ UInt32 newSize; ++ p->historySize = historySize; ++ p->hashSizeSum = hs; ++ p->cyclicBufferSize = newCyclicBufferSize; ++ p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize); ++ newSize = p->hashSizeSum + p->numSons; ++ if (p->hash != 0 && prevSize == newSize) ++ return 1; ++ MatchFinder_FreeThisClassMemory(p, alloc); ++ p->hash = AllocRefs(newSize, alloc); ++ if (p->hash != 0) ++ { ++ p->son = p->hash + p->hashSizeSum; ++ return 1; ++ } ++ } ++ } ++ MatchFinder_Free(p, alloc); ++ return 0; ++} ++ ++static void MatchFinder_SetLimits(CMatchFinder *p) ++{ ++ UInt32 limit = kMaxValForNormalize - p->pos; ++ UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos; ++ if (limit2 < limit) ++ limit = limit2; ++ limit2 = p->streamPos - p->pos; ++ if (limit2 <= p->keepSizeAfter) ++ { ++ if (limit2 > 0) ++ limit2 = 1; ++ } ++ else ++ limit2 -= p->keepSizeAfter; ++ if (limit2 < limit) ++ limit = limit2; ++ { ++ UInt32 lenLimit = p->streamPos - p->pos; ++ if (lenLimit > p->matchMaxLen) ++ lenLimit = p->matchMaxLen; ++ p->lenLimit = lenLimit; ++ } ++ p->posLimit = p->pos + limit; ++} ++ ++void MatchFinder_Init(CMatchFinder *p) ++{ ++ UInt32 i; ++ for (i = 0; i < p->hashSizeSum; i++) ++ p->hash[i] = kEmptyHashValue; ++ p->cyclicBufferPos = 0; ++ p->buffer = p->bufferBase; ++ p->pos = p->streamPos = p->cyclicBufferSize; ++ p->result = SZ_OK; ++ p->streamEndWasReached = 0; ++ MatchFinder_ReadBlock(p); ++ MatchFinder_SetLimits(p); ++} ++ ++static UInt32 MatchFinder_GetSubValue(CMatchFinder *p) ++{ ++ return (p->pos - p->historySize - 1) & kNormalizeMask; ++} ++ ++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) ++{ ++ UInt32 i; ++ for (i = 0; i < numItems; i++) ++ { ++ UInt32 value = items[i]; ++ if (value <= subValue) ++ value = kEmptyHashValue; ++ else ++ value -= subValue; ++ items[i] = value; ++ } ++} ++ ++static void MatchFinder_Normalize(CMatchFinder *p) ++{ ++ UInt32 subValue = MatchFinder_GetSubValue(p); ++ MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons); ++ MatchFinder_ReduceOffsets(p, subValue); ++} ++ ++static void MatchFinder_CheckLimits(CMatchFinder *p) ++{ ++ if (p->pos == kMaxValForNormalize) ++ MatchFinder_Normalize(p); ++ if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos) ++ MatchFinder_CheckAndMoveAndRead(p); ++ if (p->cyclicBufferPos == p->cyclicBufferSize) ++ p->cyclicBufferPos = 0; ++ MatchFinder_SetLimits(p); ++} ++ ++static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, ++ UInt32 *distances, UInt32 maxLen) ++{ ++ son[_cyclicBufferPos] = curMatch; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ return distances; ++ { ++ const Byte *pb = cur - delta; ++ curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)]; ++ if (pb[maxLen] == cur[maxLen] && *pb == *cur) ++ { ++ UInt32 len = 0; ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ if (maxLen < len) ++ { ++ *distances++ = maxLen = len; ++ *distances++ = delta - 1; ++ if (len == lenLimit) ++ return distances; ++ } ++ } ++ } ++ } ++} ++ ++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, ++ UInt32 *distances, UInt32 maxLen) ++{ ++ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; ++ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); ++ UInt32 len0 = 0, len1 = 0; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ { ++ *ptr0 = *ptr1 = kEmptyHashValue; ++ return distances; ++ } ++ { ++ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); ++ const Byte *pb = cur - delta; ++ UInt32 len = (len0 < len1 ? len0 : len1); ++ if (pb[len] == cur[len]) ++ { ++ if (++len != lenLimit && pb[len] == cur[len]) ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ if (maxLen < len) ++ { ++ *distances++ = maxLen = len; ++ *distances++ = delta - 1; ++ if (len == lenLimit) ++ { ++ *ptr1 = pair[0]; ++ *ptr0 = pair[1]; ++ return distances; ++ } ++ } ++ } ++ if (pb[len] < cur[len]) ++ { ++ *ptr1 = curMatch; ++ ptr1 = pair + 1; ++ curMatch = *ptr1; ++ len1 = len; ++ } ++ else ++ { ++ *ptr0 = curMatch; ++ ptr0 = pair; ++ curMatch = *ptr0; ++ len0 = len; ++ } ++ } ++ } ++} ++ ++static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue) ++{ ++ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; ++ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); ++ UInt32 len0 = 0, len1 = 0; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ { ++ *ptr0 = *ptr1 = kEmptyHashValue; ++ return; ++ } ++ { ++ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); ++ const Byte *pb = cur - delta; ++ UInt32 len = (len0 < len1 ? len0 : len1); ++ if (pb[len] == cur[len]) ++ { ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ { ++ if (len == lenLimit) ++ { ++ *ptr1 = pair[0]; ++ *ptr0 = pair[1]; ++ return; ++ } ++ } ++ } ++ if (pb[len] < cur[len]) ++ { ++ *ptr1 = curMatch; ++ ptr1 = pair + 1; ++ curMatch = *ptr1; ++ len1 = len; ++ } ++ else ++ { ++ *ptr0 = curMatch; ++ ptr0 = pair; ++ curMatch = *ptr0; ++ len0 = len; ++ } ++ } ++ } ++} ++ ++#define MOVE_POS \ ++ ++p->cyclicBufferPos; \ ++ p->buffer++; \ ++ if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); ++ ++#define MOVE_POS_RET MOVE_POS return offset; ++ ++static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } ++ ++#define GET_MATCHES_HEADER2(minLen, ret_op) \ ++ UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ ++ lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ ++ cur = p->buffer; ++ ++#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0) ++#define SKIP_HEADER(minLen) GET_MATCHES_HEADER2(minLen, continue) ++ ++#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue ++ ++#define GET_MATCHES_FOOTER(offset, maxLen) \ ++ offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \ ++ distances + offset, maxLen) - distances); MOVE_POS_RET; ++ ++#define SKIP_FOOTER \ ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS; ++ ++static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(2) ++ HASH2_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = 0; ++ GET_MATCHES_FOOTER(offset, 1) ++} ++ ++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = 0; ++ GET_MATCHES_FOOTER(offset, 2) ++} ++ ++static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, delta2, maxLen, offset; ++ GET_MATCHES_HEADER(3) ++ ++ HASH3_CALC; ++ ++ delta2 = p->pos - p->hash[hash2Value]; ++ curMatch = p->hash[kFix3HashSize + hashValue]; ++ ++ p->hash[hash2Value] = ++ p->hash[kFix3HashSize + hashValue] = p->pos; ++ ++ ++ maxLen = 2; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[0] = maxLen; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ if (maxLen == lenLimit) ++ { ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); ++ MOVE_POS_RET; ++ } ++ } ++ GET_MATCHES_FOOTER(offset, maxLen) ++} ++ ++static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; ++ GET_MATCHES_HEADER(4) ++ ++ HASH4_CALC; ++ ++ delta2 = p->pos - p->hash[ hash2Value]; ++ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ ++ maxLen = 1; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ distances[0] = maxLen = 2; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ } ++ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) ++ { ++ maxLen = 3; ++ distances[offset + 1] = delta3 - 1; ++ offset += 2; ++ delta2 = delta3; ++ } ++ if (offset != 0) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[offset - 2] = maxLen; ++ if (maxLen == lenLimit) ++ { ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); ++ MOVE_POS_RET; ++ } ++ } ++ if (maxLen < 3) ++ maxLen = 3; ++ GET_MATCHES_FOOTER(offset, maxLen) ++} ++ ++static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; ++ GET_MATCHES_HEADER(4) ++ ++ HASH4_CALC; ++ ++ delta2 = p->pos - p->hash[ hash2Value]; ++ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ ++ maxLen = 1; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ distances[0] = maxLen = 2; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ } ++ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) ++ { ++ maxLen = 3; ++ distances[offset + 1] = delta3 - 1; ++ offset += 2; ++ delta2 = delta3; ++ } ++ if (offset != 0) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[offset - 2] = maxLen; ++ if (maxLen == lenLimit) ++ { ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS_RET; ++ } ++ } ++ if (maxLen < 3) ++ maxLen = 3; ++ offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), ++ distances + offset, maxLen) - (distances)); ++ MOVE_POS_RET ++} ++ ++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), ++ distances, 2) - (distances)); ++ MOVE_POS_RET ++} ++ ++static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(2) ++ HASH2_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value; ++ SKIP_HEADER(3) ++ HASH3_CALC; ++ curMatch = p->hash[kFix3HashSize + hashValue]; ++ p->hash[hash2Value] = ++ p->hash[kFix3HashSize + hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value, hash3Value; ++ SKIP_HEADER(4) ++ HASH4_CALC; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = p->pos; ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value, hash3Value; ++ SKIP_HEADER(4) ++ HASH4_CALC; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS ++ } ++ while (--num != 0); ++} ++ ++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS ++ } ++ while (--num != 0); ++} ++ ++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) ++{ ++ vTable->Init = (Mf_Init_Func)MatchFinder_Init; ++ vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; ++ vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; ++ vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; ++ if (!p->btMode) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip; ++ } ++ else if (p->numHashBytes == 2) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip; ++ } ++ else if (p->numHashBytes == 3) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip; ++ } ++ else ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; ++ } ++} +--- /dev/null ++++ b/lib/lzma/LzmaDec.c +@@ -0,0 +1,999 @@ ++/* LzmaDec.c -- LZMA Decoder ++2009-09-20 : Igor Pavlov : Public domain */ ++ ++#include "LzmaDec.h" ++ ++#include ++ ++#define kNumTopBits 24 ++#define kTopValue ((UInt32)1 << kNumTopBits) ++ ++#define kNumBitModelTotalBits 11 ++#define kBitModelTotal (1 << kNumBitModelTotalBits) ++#define kNumMoveBits 5 ++ ++#define RC_INIT_SIZE 5 ++ ++#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); } ++ ++#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) ++#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits)); ++#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits)); ++#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \ ++ { UPDATE_0(p); i = (i + i); A0; } else \ ++ { UPDATE_1(p); i = (i + i) + 1; A1; } ++#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;) ++ ++#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); } ++#define TREE_DECODE(probs, limit, i) \ ++ { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; } ++ ++/* #define _LZMA_SIZE_OPT */ ++ ++#ifdef _LZMA_SIZE_OPT ++#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i) ++#else ++#define TREE_6_DECODE(probs, i) \ ++ { i = 1; \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ i -= 0x40; } ++#endif ++ ++#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); } ++ ++#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) ++#define UPDATE_0_CHECK range = bound; ++#define UPDATE_1_CHECK range -= bound; code -= bound; ++#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \ ++ { UPDATE_0_CHECK; i = (i + i); A0; } else \ ++ { UPDATE_1_CHECK; i = (i + i) + 1; A1; } ++#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;) ++#define TREE_DECODE_CHECK(probs, limit, i) \ ++ { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; } ++ ++ ++#define kNumPosBitsMax 4 ++#define kNumPosStatesMax (1 << kNumPosBitsMax) ++ ++#define kLenNumLowBits 3 ++#define kLenNumLowSymbols (1 << kLenNumLowBits) ++#define kLenNumMidBits 3 ++#define kLenNumMidSymbols (1 << kLenNumMidBits) ++#define kLenNumHighBits 8 ++#define kLenNumHighSymbols (1 << kLenNumHighBits) ++ ++#define LenChoice 0 ++#define LenChoice2 (LenChoice + 1) ++#define LenLow (LenChoice2 + 1) ++#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) ++#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) ++#define kNumLenProbs (LenHigh + kLenNumHighSymbols) ++ ++ ++#define kNumStates 12 ++#define kNumLitStates 7 ++ ++#define kStartPosModelIndex 4 ++#define kEndPosModelIndex 14 ++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) ++ ++#define kNumPosSlotBits 6 ++#define kNumLenToPosStates 4 ++ ++#define kNumAlignBits 4 ++#define kAlignTableSize (1 << kNumAlignBits) ++ ++#define kMatchMinLen 2 ++#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) ++ ++#define IsMatch 0 ++#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) ++#define IsRepG0 (IsRep + kNumStates) ++#define IsRepG1 (IsRepG0 + kNumStates) ++#define IsRepG2 (IsRepG1 + kNumStates) ++#define IsRep0Long (IsRepG2 + kNumStates) ++#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) ++#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) ++#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) ++#define LenCoder (Align + kAlignTableSize) ++#define RepLenCoder (LenCoder + kNumLenProbs) ++#define Literal (RepLenCoder + kNumLenProbs) ++ ++#define LZMA_BASE_SIZE 1846 ++#define LZMA_LIT_SIZE 768 ++ ++#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp))) ++ ++#if Literal != LZMA_BASE_SIZE ++StopCompilingDueBUG ++#endif ++ ++#define LZMA_DIC_MIN (1 << 12) ++ ++/* First LZMA-symbol is always decoded. ++And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization ++Out: ++ Result: ++ SZ_OK - OK ++ SZ_ERROR_DATA - Error ++ p->remainLen: ++ < kMatchSpecLenStart : normal remain ++ = kMatchSpecLenStart : finished ++ = kMatchSpecLenStart + 1 : Flush marker ++ = kMatchSpecLenStart + 2 : State Init Marker ++*/ ++ ++static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit) ++{ ++ CLzmaProb *probs = p->probs; ++ ++ unsigned state = p->state; ++ UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3]; ++ unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1; ++ unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1; ++ unsigned lc = p->prop.lc; ++ ++ Byte *dic = p->dic; ++ SizeT dicBufSize = p->dicBufSize; ++ SizeT dicPos = p->dicPos; ++ ++ UInt32 processedPos = p->processedPos; ++ UInt32 checkDicSize = p->checkDicSize; ++ unsigned len = 0; ++ ++ const Byte *buf = p->buf; ++ UInt32 range = p->range; ++ UInt32 code = p->code; ++ ++ do ++ { ++ CLzmaProb *prob; ++ UInt32 bound; ++ unsigned ttt; ++ unsigned posState = processedPos & pbMask; ++ ++ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0(prob) ++ { ++ unsigned symbol; ++ UPDATE_0(prob); ++ prob = probs + Literal; ++ if (checkDicSize != 0 || processedPos != 0) ++ prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + ++ (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc)))); ++ ++ if (state < kNumLitStates) ++ { ++ state -= (state < 4) ? state : 3; ++ symbol = 1; ++ do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100); ++ } ++ else ++ { ++ unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ unsigned offs = 0x100; ++ state -= (state < 10) ? 3 : 6; ++ symbol = 1; ++ do ++ { ++ unsigned bit; ++ CLzmaProb *probLit; ++ matchByte <<= 1; ++ bit = (matchByte & offs); ++ probLit = prob + offs + bit + symbol; ++ GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit) ++ } ++ while (symbol < 0x100); ++ } ++ dic[dicPos++] = (Byte)symbol; ++ processedPos++; ++ continue; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ prob = probs + IsRep + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ state += kNumStates; ++ prob = probs + LenCoder; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ if (checkDicSize == 0 && processedPos == 0) ++ return SZ_ERROR_DATA; ++ prob = probs + IsRepG0 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ dicPos++; ++ processedPos++; ++ state = state < kNumLitStates ? 9 : 11; ++ continue; ++ } ++ UPDATE_1(prob); ++ } ++ else ++ { ++ UInt32 distance; ++ UPDATE_1(prob); ++ prob = probs + IsRepG1 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ distance = rep1; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ prob = probs + IsRepG2 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ distance = rep2; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ distance = rep3; ++ rep3 = rep2; ++ } ++ rep2 = rep1; ++ } ++ rep1 = rep0; ++ rep0 = distance; ++ } ++ state = state < kNumLitStates ? 8 : 11; ++ prob = probs + RepLenCoder; ++ } ++ { ++ unsigned limit, offset; ++ CLzmaProb *probLen = prob + LenChoice; ++ IF_BIT_0(probLen) ++ { ++ UPDATE_0(probLen); ++ probLen = prob + LenLow + (posState << kLenNumLowBits); ++ offset = 0; ++ limit = (1 << kLenNumLowBits); ++ } ++ else ++ { ++ UPDATE_1(probLen); ++ probLen = prob + LenChoice2; ++ IF_BIT_0(probLen) ++ { ++ UPDATE_0(probLen); ++ probLen = prob + LenMid + (posState << kLenNumMidBits); ++ offset = kLenNumLowSymbols; ++ limit = (1 << kLenNumMidBits); ++ } ++ else ++ { ++ UPDATE_1(probLen); ++ probLen = prob + LenHigh; ++ offset = kLenNumLowSymbols + kLenNumMidSymbols; ++ limit = (1 << kLenNumHighBits); ++ } ++ } ++ TREE_DECODE(probLen, limit, len); ++ len += offset; ++ } ++ ++ if (state >= kNumStates) ++ { ++ UInt32 distance; ++ prob = probs + PosSlot + ++ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); ++ TREE_6_DECODE(prob, distance); ++ if (distance >= kStartPosModelIndex) ++ { ++ unsigned posSlot = (unsigned)distance; ++ int numDirectBits = (int)(((distance >> 1) - 1)); ++ distance = (2 | (distance & 1)); ++ if (posSlot < kEndPosModelIndex) ++ { ++ distance <<= numDirectBits; ++ prob = probs + SpecPos + distance - posSlot - 1; ++ { ++ UInt32 mask = 1; ++ unsigned i = 1; ++ do ++ { ++ GET_BIT2(prob + i, i, ; , distance |= mask); ++ mask <<= 1; ++ } ++ while (--numDirectBits != 0); ++ } ++ } ++ else ++ { ++ numDirectBits -= kNumAlignBits; ++ do ++ { ++ NORMALIZE ++ range >>= 1; ++ ++ { ++ UInt32 t; ++ code -= range; ++ t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */ ++ distance = (distance << 1) + (t + 1); ++ code += range & t; ++ } ++ /* ++ distance <<= 1; ++ if (code >= range) ++ { ++ code -= range; ++ distance |= 1; ++ } ++ */ ++ } ++ while (--numDirectBits != 0); ++ prob = probs + Align; ++ distance <<= kNumAlignBits; ++ { ++ unsigned i = 1; ++ GET_BIT2(prob + i, i, ; , distance |= 1); ++ GET_BIT2(prob + i, i, ; , distance |= 2); ++ GET_BIT2(prob + i, i, ; , distance |= 4); ++ GET_BIT2(prob + i, i, ; , distance |= 8); ++ } ++ if (distance == (UInt32)0xFFFFFFFF) ++ { ++ len += kMatchSpecLenStart; ++ state -= kNumStates; ++ break; ++ } ++ } ++ } ++ rep3 = rep2; ++ rep2 = rep1; ++ rep1 = rep0; ++ rep0 = distance + 1; ++ if (checkDicSize == 0) ++ { ++ if (distance >= processedPos) ++ return SZ_ERROR_DATA; ++ } ++ else if (distance >= checkDicSize) ++ return SZ_ERROR_DATA; ++ state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3; ++ } ++ ++ len += kMatchMinLen; ++ ++ if (limit == dicPos) ++ return SZ_ERROR_DATA; ++ { ++ SizeT rem = limit - dicPos; ++ unsigned curLen = ((rem < len) ? (unsigned)rem : len); ++ SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0); ++ ++ processedPos += curLen; ++ ++ len -= curLen; ++ if (pos + curLen <= dicBufSize) ++ { ++ Byte *dest = dic + dicPos; ++ ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos; ++ const Byte *lim = dest + curLen; ++ dicPos += curLen; ++ do ++ *(dest) = (Byte)*(dest + src); ++ while (++dest != lim); ++ } ++ else ++ { ++ do ++ { ++ dic[dicPos++] = dic[pos]; ++ if (++pos == dicBufSize) ++ pos = 0; ++ } ++ while (--curLen != 0); ++ } ++ } ++ } ++ } ++ while (dicPos < limit && buf < bufLimit); ++ NORMALIZE; ++ p->buf = buf; ++ p->range = range; ++ p->code = code; ++ p->remainLen = len; ++ p->dicPos = dicPos; ++ p->processedPos = processedPos; ++ p->reps[0] = rep0; ++ p->reps[1] = rep1; ++ p->reps[2] = rep2; ++ p->reps[3] = rep3; ++ p->state = state; ++ ++ return SZ_OK; ++} ++ ++static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit) ++{ ++ if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart) ++ { ++ Byte *dic = p->dic; ++ SizeT dicPos = p->dicPos; ++ SizeT dicBufSize = p->dicBufSize; ++ unsigned len = p->remainLen; ++ UInt32 rep0 = p->reps[0]; ++ if (limit - dicPos < len) ++ len = (unsigned)(limit - dicPos); ++ ++ if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len) ++ p->checkDicSize = p->prop.dicSize; ++ ++ p->processedPos += len; ++ p->remainLen -= len; ++ while (len-- != 0) ++ { ++ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ dicPos++; ++ } ++ p->dicPos = dicPos; ++ } ++} ++ ++static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit) ++{ ++ do ++ { ++ SizeT limit2 = limit; ++ if (p->checkDicSize == 0) ++ { ++ UInt32 rem = p->prop.dicSize - p->processedPos; ++ if (limit - p->dicPos > rem) ++ limit2 = p->dicPos + rem; ++ } ++ RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit)); ++ if (p->processedPos >= p->prop.dicSize) ++ p->checkDicSize = p->prop.dicSize; ++ LzmaDec_WriteRem(p, limit); ++ } ++ while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart); ++ ++ if (p->remainLen > kMatchSpecLenStart) ++ { ++ p->remainLen = kMatchSpecLenStart; ++ } ++ return 0; ++} ++ ++typedef enum ++{ ++ DUMMY_ERROR, /* unexpected end of input stream */ ++ DUMMY_LIT, ++ DUMMY_MATCH, ++ DUMMY_REP ++} ELzmaDummy; ++ ++static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize) ++{ ++ UInt32 range = p->range; ++ UInt32 code = p->code; ++ const Byte *bufLimit = buf + inSize; ++ CLzmaProb *probs = p->probs; ++ unsigned state = p->state; ++ ELzmaDummy res; ++ ++ { ++ CLzmaProb *prob; ++ UInt32 bound; ++ unsigned ttt; ++ unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1); ++ ++ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK ++ ++ /* if (bufLimit - buf >= 7) return DUMMY_LIT; */ ++ ++ prob = probs + Literal; ++ if (p->checkDicSize != 0 || p->processedPos != 0) ++ prob += (LZMA_LIT_SIZE * ++ ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + ++ (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc)))); ++ ++ if (state < kNumLitStates) ++ { ++ unsigned symbol = 1; ++ do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100); ++ } ++ else ++ { ++ unsigned matchByte = p->dic[p->dicPos - p->reps[0] + ++ ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)]; ++ unsigned offs = 0x100; ++ unsigned symbol = 1; ++ do ++ { ++ unsigned bit; ++ CLzmaProb *probLit; ++ matchByte <<= 1; ++ bit = (matchByte & offs); ++ probLit = prob + offs + bit + symbol; ++ GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit) ++ } ++ while (symbol < 0x100); ++ } ++ res = DUMMY_LIT; ++ } ++ else ++ { ++ unsigned len; ++ UPDATE_1_CHECK; ++ ++ prob = probs + IsRep + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ state = 0; ++ prob = probs + LenCoder; ++ res = DUMMY_MATCH; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ res = DUMMY_REP; ++ prob = probs + IsRepG0 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ NORMALIZE_CHECK; ++ return DUMMY_REP; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ } ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ prob = probs + IsRepG1 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ prob = probs + IsRepG2 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ } ++ } ++ } ++ state = kNumStates; ++ prob = probs + RepLenCoder; ++ } ++ { ++ unsigned limit, offset; ++ CLzmaProb *probLen = prob + LenChoice; ++ IF_BIT_0_CHECK(probLen) ++ { ++ UPDATE_0_CHECK; ++ probLen = prob + LenLow + (posState << kLenNumLowBits); ++ offset = 0; ++ limit = 1 << kLenNumLowBits; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ probLen = prob + LenChoice2; ++ IF_BIT_0_CHECK(probLen) ++ { ++ UPDATE_0_CHECK; ++ probLen = prob + LenMid + (posState << kLenNumMidBits); ++ offset = kLenNumLowSymbols; ++ limit = 1 << kLenNumMidBits; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ probLen = prob + LenHigh; ++ offset = kLenNumLowSymbols + kLenNumMidSymbols; ++ limit = 1 << kLenNumHighBits; ++ } ++ } ++ TREE_DECODE_CHECK(probLen, limit, len); ++ len += offset; ++ } ++ ++ if (state < 4) ++ { ++ unsigned posSlot; ++ prob = probs + PosSlot + ++ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << ++ kNumPosSlotBits); ++ TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot); ++ if (posSlot >= kStartPosModelIndex) ++ { ++ int numDirectBits = ((posSlot >> 1) - 1); ++ ++ /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */ ++ ++ if (posSlot < kEndPosModelIndex) ++ { ++ prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1; ++ } ++ else ++ { ++ numDirectBits -= kNumAlignBits; ++ do ++ { ++ NORMALIZE_CHECK ++ range >>= 1; ++ code -= range & (((code - range) >> 31) - 1); ++ /* if (code >= range) code -= range; */ ++ } ++ while (--numDirectBits != 0); ++ prob = probs + Align; ++ numDirectBits = kNumAlignBits; ++ } ++ { ++ unsigned i = 1; ++ do ++ { ++ GET_BIT_CHECK(prob + i, i); ++ } ++ while (--numDirectBits != 0); ++ } ++ } ++ } ++ } ++ } ++ NORMALIZE_CHECK; ++ return res; ++} ++ ++ ++static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data) ++{ ++ p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]); ++ p->range = 0xFFFFFFFF; ++ p->needFlush = 0; ++} ++ ++void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) ++{ ++ p->needFlush = 1; ++ p->remainLen = 0; ++ p->tempBufSize = 0; ++ ++ if (initDic) ++ { ++ p->processedPos = 0; ++ p->checkDicSize = 0; ++ p->needInitState = 1; ++ } ++ if (initState) ++ p->needInitState = 1; ++} ++ ++void LzmaDec_Init(CLzmaDec *p) ++{ ++ p->dicPos = 0; ++ LzmaDec_InitDicAndState(p, True, True); ++} ++ ++static void LzmaDec_InitStateReal(CLzmaDec *p) ++{ ++ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp)); ++ UInt32 i; ++ CLzmaProb *probs = p->probs; ++ for (i = 0; i < numProbs; i++) ++ probs[i] = kBitModelTotal >> 1; ++ p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1; ++ p->state = 0; ++ p->needInitState = 0; ++} ++ ++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, ++ ELzmaFinishMode finishMode, ELzmaStatus *status) ++{ ++ SizeT inSize = *srcLen; ++ (*srcLen) = 0; ++ LzmaDec_WriteRem(p, dicLimit); ++ ++ *status = LZMA_STATUS_NOT_SPECIFIED; ++ ++ while (p->remainLen != kMatchSpecLenStart) ++ { ++ int checkEndMarkNow; ++ ++ if (p->needFlush != 0) ++ { ++ for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--) ++ p->tempBuf[p->tempBufSize++] = *src++; ++ if (p->tempBufSize < RC_INIT_SIZE) ++ { ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (p->tempBuf[0] != 0) ++ return SZ_ERROR_DATA; ++ ++ LzmaDec_InitRc(p, p->tempBuf); ++ p->tempBufSize = 0; ++ } ++ ++ checkEndMarkNow = 0; ++ if (p->dicPos >= dicLimit) ++ { ++ if (p->remainLen == 0 && p->code == 0) ++ { ++ *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK; ++ return SZ_OK; ++ } ++ if (finishMode == LZMA_FINISH_ANY) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_OK; ++ } ++ if (p->remainLen != 0) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ checkEndMarkNow = 1; ++ } ++ ++ if (p->needInitState) ++ LzmaDec_InitStateReal(p); ++ ++ if (p->tempBufSize == 0) ++ { ++ SizeT processed; ++ const Byte *bufLimit; ++ if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) ++ { ++ int dummyRes = LzmaDec_TryDummy(p, src, inSize); ++ if (dummyRes == DUMMY_ERROR) ++ { ++ memcpy(p->tempBuf, src, inSize); ++ p->tempBufSize = (unsigned)inSize; ++ (*srcLen) += inSize; ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ bufLimit = src; ++ } ++ else ++ bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX; ++ p->buf = src; ++ if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0) ++ return SZ_ERROR_DATA; ++ processed = (SizeT)(p->buf - src); ++ (*srcLen) += processed; ++ src += processed; ++ inSize -= processed; ++ } ++ else ++ { ++ unsigned rem = p->tempBufSize, lookAhead = 0; ++ while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize) ++ p->tempBuf[rem++] = src[lookAhead++]; ++ p->tempBufSize = rem; ++ if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) ++ { ++ int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem); ++ if (dummyRes == DUMMY_ERROR) ++ { ++ (*srcLen) += lookAhead; ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ } ++ p->buf = p->tempBuf; ++ if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0) ++ return SZ_ERROR_DATA; ++ lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf)); ++ (*srcLen) += lookAhead; ++ src += lookAhead; ++ inSize -= lookAhead; ++ p->tempBufSize = 0; ++ } ++ } ++ if (p->code == 0) ++ *status = LZMA_STATUS_FINISHED_WITH_MARK; ++ return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; ++} ++ ++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) ++{ ++ SizeT outSize = *destLen; ++ SizeT inSize = *srcLen; ++ *srcLen = *destLen = 0; ++ for (;;) ++ { ++ SizeT inSizeCur = inSize, outSizeCur, dicPos; ++ ELzmaFinishMode curFinishMode; ++ SRes res; ++ if (p->dicPos == p->dicBufSize) ++ p->dicPos = 0; ++ dicPos = p->dicPos; ++ if (outSize > p->dicBufSize - dicPos) ++ { ++ outSizeCur = p->dicBufSize; ++ curFinishMode = LZMA_FINISH_ANY; ++ } ++ else ++ { ++ outSizeCur = dicPos + outSize; ++ curFinishMode = finishMode; ++ } ++ ++ res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); ++ src += inSizeCur; ++ inSize -= inSizeCur; ++ *srcLen += inSizeCur; ++ outSizeCur = p->dicPos - dicPos; ++ memcpy(dest, p->dic + dicPos, outSizeCur); ++ dest += outSizeCur; ++ outSize -= outSizeCur; ++ *destLen += outSizeCur; ++ if (res != 0) ++ return res; ++ if (outSizeCur == 0 || outSize == 0) ++ return SZ_OK; ++ } ++} ++ ++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->probs); ++ p->probs = 0; ++} ++ ++static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->dic); ++ p->dic = 0; ++} ++ ++void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ LzmaDec_FreeProbs(p, alloc); ++ LzmaDec_FreeDict(p, alloc); ++} ++ ++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) ++{ ++ UInt32 dicSize; ++ Byte d; ++ ++ if (size < LZMA_PROPS_SIZE) ++ return SZ_ERROR_UNSUPPORTED; ++ else ++ dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24); ++ ++ if (dicSize < LZMA_DIC_MIN) ++ dicSize = LZMA_DIC_MIN; ++ p->dicSize = dicSize; ++ ++ d = data[0]; ++ if (d >= (9 * 5 * 5)) ++ return SZ_ERROR_UNSUPPORTED; ++ ++ p->lc = d % 9; ++ d /= 9; ++ p->pb = d / 5; ++ p->lp = d % 5; ++ ++ return SZ_OK; ++} ++ ++static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc) ++{ ++ UInt32 numProbs = LzmaProps_GetNumProbs(propNew); ++ if (p->probs == 0 || numProbs != p->numProbs) ++ { ++ LzmaDec_FreeProbs(p, alloc); ++ p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb)); ++ p->numProbs = numProbs; ++ if (p->probs == 0) ++ return SZ_ERROR_MEM; ++ } ++ return SZ_OK; ++} ++ ++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++{ ++ CLzmaProps propNew; ++ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); ++ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); ++ p->prop = propNew; ++ return SZ_OK; ++} ++ ++SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++{ ++ CLzmaProps propNew; ++ SizeT dicBufSize; ++ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); ++ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); ++ dicBufSize = propNew.dicSize; ++ if (p->dic == 0 || dicBufSize != p->dicBufSize) ++ { ++ LzmaDec_FreeDict(p, alloc); ++ p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); ++ if (p->dic == 0) ++ { ++ LzmaDec_FreeProbs(p, alloc); ++ return SZ_ERROR_MEM; ++ } ++ } ++ p->dicBufSize = dicBufSize; ++ p->prop = propNew; ++ return SZ_OK; ++} ++ ++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ++ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, ++ ELzmaStatus *status, ISzAlloc *alloc) ++{ ++ CLzmaDec p; ++ SRes res; ++ SizeT inSize = *srcLen; ++ SizeT outSize = *destLen; ++ *srcLen = *destLen = 0; ++ if (inSize < RC_INIT_SIZE) ++ return SZ_ERROR_INPUT_EOF; ++ ++ LzmaDec_Construct(&p); ++ res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc); ++ if (res != 0) ++ return res; ++ p.dic = dest; ++ p.dicBufSize = outSize; ++ ++ LzmaDec_Init(&p); ++ ++ *srcLen = inSize; ++ res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status); ++ ++ if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT) ++ res = SZ_ERROR_INPUT_EOF; ++ ++ (*destLen) = p.dicPos; ++ LzmaDec_FreeProbs(&p, alloc); ++ return res; ++} +--- /dev/null ++++ b/lib/lzma/LzmaEnc.c +@@ -0,0 +1,2271 @@ ++/* LzmaEnc.c -- LZMA Encoder ++2009-11-24 : Igor Pavlov : Public domain */ ++ ++#include ++ ++/* #define SHOW_STAT */ ++/* #define SHOW_STAT2 */ ++ ++#if defined(SHOW_STAT) || defined(SHOW_STAT2) ++#include ++#endif ++ ++#include "LzmaEnc.h" ++ ++/* disable MT */ ++#define _7ZIP_ST ++ ++#include "LzFind.h" ++#ifndef _7ZIP_ST ++#include "LzFindMt.h" ++#endif ++ ++#ifdef SHOW_STAT ++static int ttt = 0; ++#endif ++ ++#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1) ++ ++#define kBlockSize (9 << 10) ++#define kUnpackBlockSize (1 << 18) ++#define kMatchArraySize (1 << 21) ++#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX) ++ ++#define kNumMaxDirectBits (31) ++ ++#define kNumTopBits 24 ++#define kTopValue ((UInt32)1 << kNumTopBits) ++ ++#define kNumBitModelTotalBits 11 ++#define kBitModelTotal (1 << kNumBitModelTotalBits) ++#define kNumMoveBits 5 ++#define kProbInitValue (kBitModelTotal >> 1) ++ ++#define kNumMoveReducingBits 4 ++#define kNumBitPriceShiftBits 4 ++#define kBitPrice (1 << kNumBitPriceShiftBits) ++ ++void LzmaEncProps_Init(CLzmaEncProps *p) ++{ ++ p->level = 5; ++ p->dictSize = p->mc = 0; ++ p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1; ++ p->writeEndMark = 0; ++} ++ ++void LzmaEncProps_Normalize(CLzmaEncProps *p) ++{ ++ int level = p->level; ++ if (level < 0) level = 5; ++ p->level = level; ++ if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26))); ++ if (p->lc < 0) p->lc = 3; ++ if (p->lp < 0) p->lp = 0; ++ if (p->pb < 0) p->pb = 2; ++ if (p->algo < 0) p->algo = (level < 5 ? 0 : 1); ++ if (p->fb < 0) p->fb = (level < 7 ? 32 : 64); ++ if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1); ++ if (p->numHashBytes < 0) p->numHashBytes = 4; ++ if (p->mc == 0) p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1); ++ if (p->numThreads < 0) ++ p->numThreads = ++ #ifndef _7ZIP_ST ++ ((p->btMode && p->algo) ? 2 : 1); ++ #else ++ 1; ++ #endif ++} ++ ++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) ++{ ++ CLzmaEncProps props = *props2; ++ LzmaEncProps_Normalize(&props); ++ return props.dictSize; ++} ++ ++/* #define LZMA_LOG_BSR */ ++/* Define it for Intel's CPU */ ++ ++ ++#ifdef LZMA_LOG_BSR ++ ++#define kDicLogSizeMaxCompress 30 ++ ++#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } ++ ++UInt32 GetPosSlot1(UInt32 pos) ++{ ++ UInt32 res; ++ BSR2_RET(pos, res); ++ return res; ++} ++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } ++#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); } ++ ++#else ++ ++#define kNumLogBits (9 + (int)sizeof(size_t) / 2) ++#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) ++ ++void LzmaEnc_FastPosInit(Byte *g_FastPos) ++{ ++ int c = 2, slotFast; ++ g_FastPos[0] = 0; ++ g_FastPos[1] = 1; ++ ++ for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++) ++ { ++ UInt32 k = (1 << ((slotFast >> 1) - 1)); ++ UInt32 j; ++ for (j = 0; j < k; j++, c++) ++ g_FastPos[c] = (Byte)slotFast; ++ } ++} ++ ++#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \ ++ (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \ ++ res = p->g_FastPos[pos >> i] + (i * 2); } ++/* ++#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \ ++ p->g_FastPos[pos >> 6] + 12 : \ ++ p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; } ++*/ ++ ++#define GetPosSlot1(pos) p->g_FastPos[pos] ++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } ++#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); } ++ ++#endif ++ ++ ++#define LZMA_NUM_REPS 4 ++ ++typedef unsigned CState; ++ ++typedef struct ++{ ++ UInt32 price; ++ ++ CState state; ++ int prev1IsChar; ++ int prev2; ++ ++ UInt32 posPrev2; ++ UInt32 backPrev2; ++ ++ UInt32 posPrev; ++ UInt32 backPrev; ++ UInt32 backs[LZMA_NUM_REPS]; ++} COptimal; ++ ++#define kNumOpts (1 << 12) ++ ++#define kNumLenToPosStates 4 ++#define kNumPosSlotBits 6 ++#define kDicLogSizeMin 0 ++#define kDicLogSizeMax 32 ++#define kDistTableSizeMax (kDicLogSizeMax * 2) ++ ++ ++#define kNumAlignBits 4 ++#define kAlignTableSize (1 << kNumAlignBits) ++#define kAlignMask (kAlignTableSize - 1) ++ ++#define kStartPosModelIndex 4 ++#define kEndPosModelIndex 14 ++#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex) ++ ++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) ++ ++#ifdef _LZMA_PROB32 ++#define CLzmaProb UInt32 ++#else ++#define CLzmaProb UInt16 ++#endif ++ ++#define LZMA_PB_MAX 4 ++#define LZMA_LC_MAX 8 ++#define LZMA_LP_MAX 4 ++ ++#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX) ++ ++ ++#define kLenNumLowBits 3 ++#define kLenNumLowSymbols (1 << kLenNumLowBits) ++#define kLenNumMidBits 3 ++#define kLenNumMidSymbols (1 << kLenNumMidBits) ++#define kLenNumHighBits 8 ++#define kLenNumHighSymbols (1 << kLenNumHighBits) ++ ++#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) ++ ++#define LZMA_MATCH_LEN_MIN 2 ++#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1) ++ ++#define kNumStates 12 ++ ++typedef struct ++{ ++ CLzmaProb choice; ++ CLzmaProb choice2; ++ CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits]; ++ CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits]; ++ CLzmaProb high[kLenNumHighSymbols]; ++} CLenEnc; ++ ++typedef struct ++{ ++ CLenEnc p; ++ UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal]; ++ UInt32 tableSize; ++ UInt32 counters[LZMA_NUM_PB_STATES_MAX]; ++} CLenPriceEnc; ++ ++typedef struct ++{ ++ UInt32 range; ++ Byte cache; ++ UInt64 low; ++ UInt64 cacheSize; ++ Byte *buf; ++ Byte *bufLim; ++ Byte *bufBase; ++ ISeqOutStream *outStream; ++ UInt64 processed; ++ SRes res; ++} CRangeEnc; ++ ++typedef struct ++{ ++ CLzmaProb *litProbs; ++ ++ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ CLzmaProb isRep[kNumStates]; ++ CLzmaProb isRepG0[kNumStates]; ++ CLzmaProb isRepG1[kNumStates]; ++ CLzmaProb isRepG2[kNumStates]; ++ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ ++ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; ++ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; ++ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; ++ ++ CLenPriceEnc lenEnc; ++ CLenPriceEnc repLenEnc; ++ ++ UInt32 reps[LZMA_NUM_REPS]; ++ UInt32 state; ++} CSaveState; ++ ++typedef struct ++{ ++ IMatchFinder matchFinder; ++ void *matchFinderObj; ++ ++ #ifndef _7ZIP_ST ++ Bool mtMode; ++ CMatchFinderMt matchFinderMt; ++ #endif ++ ++ CMatchFinder matchFinderBase; ++ ++ #ifndef _7ZIP_ST ++ Byte pad[128]; ++ #endif ++ ++ UInt32 optimumEndIndex; ++ UInt32 optimumCurrentIndex; ++ ++ UInt32 longestMatchLength; ++ UInt32 numPairs; ++ UInt32 numAvail; ++ COptimal opt[kNumOpts]; ++ ++ #ifndef LZMA_LOG_BSR ++ Byte g_FastPos[1 << kNumLogBits]; ++ #endif ++ ++ UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits]; ++ UInt32 matches[LZMA_MATCH_LEN_MAX * 2 + 2 + 1]; ++ UInt32 numFastBytes; ++ UInt32 additionalOffset; ++ UInt32 reps[LZMA_NUM_REPS]; ++ UInt32 state; ++ ++ UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax]; ++ UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances]; ++ UInt32 alignPrices[kAlignTableSize]; ++ UInt32 alignPriceCount; ++ ++ UInt32 distTableSize; ++ ++ unsigned lc, lp, pb; ++ unsigned lpMask, pbMask; ++ ++ CLzmaProb *litProbs; ++ ++ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ CLzmaProb isRep[kNumStates]; ++ CLzmaProb isRepG0[kNumStates]; ++ CLzmaProb isRepG1[kNumStates]; ++ CLzmaProb isRepG2[kNumStates]; ++ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ ++ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; ++ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; ++ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; ++ ++ CLenPriceEnc lenEnc; ++ CLenPriceEnc repLenEnc; ++ ++ unsigned lclp; ++ ++ Bool fastMode; ++ ++ CRangeEnc rc; ++ ++ Bool writeEndMark; ++ UInt64 nowPos64; ++ UInt32 matchPriceCount; ++ Bool finished; ++ Bool multiThread; ++ ++ SRes result; ++ UInt32 dictSize; ++ UInt32 matchFinderCycles; ++ ++ int needInit; ++ ++ CSaveState saveState; ++} CLzmaEnc; ++ ++void LzmaEnc_SaveState(CLzmaEncHandle pp) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ CSaveState *dest = &p->saveState; ++ int i; ++ dest->lenEnc = p->lenEnc; ++ dest->repLenEnc = p->repLenEnc; ++ dest->state = p->state; ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); ++ memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); ++ } ++ for (i = 0; i < kNumLenToPosStates; i++) ++ memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); ++ memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); ++ memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); ++ memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); ++ memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); ++ memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); ++ memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); ++ memcpy(dest->reps, p->reps, sizeof(p->reps)); ++ memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb)); ++} ++ ++void LzmaEnc_RestoreState(CLzmaEncHandle pp) ++{ ++ CLzmaEnc *dest = (CLzmaEnc *)pp; ++ const CSaveState *p = &dest->saveState; ++ int i; ++ dest->lenEnc = p->lenEnc; ++ dest->repLenEnc = p->repLenEnc; ++ dest->state = p->state; ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); ++ memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); ++ } ++ for (i = 0; i < kNumLenToPosStates; i++) ++ memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); ++ memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); ++ memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); ++ memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); ++ memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); ++ memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); ++ memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); ++ memcpy(dest->reps, p->reps, sizeof(p->reps)); ++ memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb)); ++} ++ ++SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ CLzmaEncProps props = *props2; ++ LzmaEncProps_Normalize(&props); ++ ++ if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX || ++ props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30)) ++ return SZ_ERROR_PARAM; ++ p->dictSize = props.dictSize; ++ p->matchFinderCycles = props.mc; ++ { ++ unsigned fb = props.fb; ++ if (fb < 5) ++ fb = 5; ++ if (fb > LZMA_MATCH_LEN_MAX) ++ fb = LZMA_MATCH_LEN_MAX; ++ p->numFastBytes = fb; ++ } ++ p->lc = props.lc; ++ p->lp = props.lp; ++ p->pb = props.pb; ++ p->fastMode = (props.algo == 0); ++ p->matchFinderBase.btMode = props.btMode; ++ { ++ UInt32 numHashBytes = 4; ++ if (props.btMode) ++ { ++ if (props.numHashBytes < 2) ++ numHashBytes = 2; ++ else if (props.numHashBytes < 4) ++ numHashBytes = props.numHashBytes; ++ } ++ p->matchFinderBase.numHashBytes = numHashBytes; ++ } ++ ++ p->matchFinderBase.cutValue = props.mc; ++ ++ p->writeEndMark = props.writeEndMark; ++ ++ #ifndef _7ZIP_ST ++ /* ++ if (newMultiThread != _multiThread) ++ { ++ ReleaseMatchFinder(); ++ _multiThread = newMultiThread; ++ } ++ */ ++ p->multiThread = (props.numThreads > 1); ++ #endif ++ ++ return SZ_OK; ++} ++ ++static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 4, 5}; ++static const int kMatchNextStates[kNumStates] = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10}; ++static const int kRepNextStates[kNumStates] = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11}; ++static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11}; ++ ++#define IsCharState(s) ((s) < 7) ++ ++#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1) ++ ++#define kInfinityPrice (1 << 30) ++ ++static void RangeEnc_Construct(CRangeEnc *p) ++{ ++ p->outStream = 0; ++ p->bufBase = 0; ++} ++ ++#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize) ++ ++#define RC_BUF_SIZE (1 << 16) ++static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc) ++{ ++ if (p->bufBase == 0) ++ { ++ p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE); ++ if (p->bufBase == 0) ++ return 0; ++ p->bufLim = p->bufBase + RC_BUF_SIZE; ++ } ++ return 1; ++} ++ ++static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->bufBase); ++ p->bufBase = 0; ++} ++ ++static void RangeEnc_Init(CRangeEnc *p) ++{ ++ /* Stream.Init(); */ ++ p->low = 0; ++ p->range = 0xFFFFFFFF; ++ p->cacheSize = 1; ++ p->cache = 0; ++ ++ p->buf = p->bufBase; ++ ++ p->processed = 0; ++ p->res = SZ_OK; ++} ++ ++static void RangeEnc_FlushStream(CRangeEnc *p) ++{ ++ size_t num; ++ if (p->res != SZ_OK) ++ return; ++ num = p->buf - p->bufBase; ++ if (num != p->outStream->Write(p->outStream, p->bufBase, num)) ++ p->res = SZ_ERROR_WRITE; ++ p->processed += num; ++ p->buf = p->bufBase; ++} ++ ++static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p) ++{ ++ if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0) ++ { ++ Byte temp = p->cache; ++ do ++ { ++ Byte *buf = p->buf; ++ *buf++ = (Byte)(temp + (Byte)(p->low >> 32)); ++ p->buf = buf; ++ if (buf == p->bufLim) ++ RangeEnc_FlushStream(p); ++ temp = 0xFF; ++ } ++ while (--p->cacheSize != 0); ++ p->cache = (Byte)((UInt32)p->low >> 24); ++ } ++ p->cacheSize++; ++ p->low = (UInt32)p->low << 8; ++} ++ ++static void RangeEnc_FlushData(CRangeEnc *p) ++{ ++ int i; ++ for (i = 0; i < 5; i++) ++ RangeEnc_ShiftLow(p); ++} ++ ++static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits) ++{ ++ do ++ { ++ p->range >>= 1; ++ p->low += p->range & (0 - ((value >> --numBits) & 1)); ++ if (p->range < kTopValue) ++ { ++ p->range <<= 8; ++ RangeEnc_ShiftLow(p); ++ } ++ } ++ while (numBits != 0); ++} ++ ++static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol) ++{ ++ UInt32 ttt = *prob; ++ UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt; ++ if (symbol == 0) ++ { ++ p->range = newBound; ++ ttt += (kBitModelTotal - ttt) >> kNumMoveBits; ++ } ++ else ++ { ++ p->low += newBound; ++ p->range -= newBound; ++ ttt -= ttt >> kNumMoveBits; ++ } ++ *prob = (CLzmaProb)ttt; ++ if (p->range < kTopValue) ++ { ++ p->range <<= 8; ++ RangeEnc_ShiftLow(p); ++ } ++} ++ ++static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol) ++{ ++ symbol |= 0x100; ++ do ++ { ++ RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1); ++ symbol <<= 1; ++ } ++ while (symbol < 0x10000); ++} ++ ++static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte) ++{ ++ UInt32 offs = 0x100; ++ symbol |= 0x100; ++ do ++ { ++ matchByte <<= 1; ++ RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1); ++ symbol <<= 1; ++ offs &= ~(matchByte ^ symbol); ++ } ++ while (symbol < 0x10000); ++} ++ ++void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) ++{ ++ UInt32 i; ++ for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) ++ { ++ const int kCyclesBits = kNumBitPriceShiftBits; ++ UInt32 w = i; ++ UInt32 bitCount = 0; ++ int j; ++ for (j = 0; j < kCyclesBits; j++) ++ { ++ w = w * w; ++ bitCount <<= 1; ++ while (w >= ((UInt32)1 << 16)) ++ { ++ w >>= 1; ++ bitCount++; ++ } ++ } ++ ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount); ++ } ++} ++ ++ ++#define GET_PRICE(prob, symbol) \ ++ p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; ++ ++#define GET_PRICEa(prob, symbol) \ ++ ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; ++ ++#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits] ++#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] ++ ++#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits] ++#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] ++ ++static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ symbol |= 0x100; ++ do ++ { ++ price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1); ++ symbol <<= 1; ++ } ++ while (symbol < 0x10000); ++ return price; ++} ++ ++static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ UInt32 offs = 0x100; ++ symbol |= 0x100; ++ do ++ { ++ matchByte <<= 1; ++ price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1); ++ symbol <<= 1; ++ offs &= ~(matchByte ^ symbol); ++ } ++ while (symbol < 0x10000); ++ return price; ++} ++ ++ ++static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) ++{ ++ UInt32 m = 1; ++ int i; ++ for (i = numBitLevels; i != 0;) ++ { ++ UInt32 bit; ++ i--; ++ bit = (symbol >> i) & 1; ++ RangeEnc_EncodeBit(rc, probs + m, bit); ++ m = (m << 1) | bit; ++ } ++} ++ ++static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) ++{ ++ UInt32 m = 1; ++ int i; ++ for (i = 0; i < numBitLevels; i++) ++ { ++ UInt32 bit = symbol & 1; ++ RangeEnc_EncodeBit(rc, probs + m, bit); ++ m = (m << 1) | bit; ++ symbol >>= 1; ++ } ++} ++ ++static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ symbol |= (1 << numBitLevels); ++ while (symbol != 1) ++ { ++ price += GET_PRICEa(probs[symbol >> 1], symbol & 1); ++ symbol >>= 1; ++ } ++ return price; ++} ++ ++static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ UInt32 m = 1; ++ int i; ++ for (i = numBitLevels; i != 0; i--) ++ { ++ UInt32 bit = symbol & 1; ++ symbol >>= 1; ++ price += GET_PRICEa(probs[m], bit); ++ m = (m << 1) | bit; ++ } ++ return price; ++} ++ ++ ++static void LenEnc_Init(CLenEnc *p) ++{ ++ unsigned i; ++ p->choice = p->choice2 = kProbInitValue; ++ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++) ++ p->low[i] = kProbInitValue; ++ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++) ++ p->mid[i] = kProbInitValue; ++ for (i = 0; i < kLenNumHighSymbols; i++) ++ p->high[i] = kProbInitValue; ++} ++ ++static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState) ++{ ++ if (symbol < kLenNumLowSymbols) ++ { ++ RangeEnc_EncodeBit(rc, &p->choice, 0); ++ RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol); ++ } ++ else ++ { ++ RangeEnc_EncodeBit(rc, &p->choice, 1); ++ if (symbol < kLenNumLowSymbols + kLenNumMidSymbols) ++ { ++ RangeEnc_EncodeBit(rc, &p->choice2, 0); ++ RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols); ++ } ++ else ++ { ++ RangeEnc_EncodeBit(rc, &p->choice2, 1); ++ RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols); ++ } ++ } ++} ++ ++static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices) ++{ ++ UInt32 a0 = GET_PRICE_0a(p->choice); ++ UInt32 a1 = GET_PRICE_1a(p->choice); ++ UInt32 b0 = a1 + GET_PRICE_0a(p->choice2); ++ UInt32 b1 = a1 + GET_PRICE_1a(p->choice2); ++ UInt32 i = 0; ++ for (i = 0; i < kLenNumLowSymbols; i++) ++ { ++ if (i >= numSymbols) ++ return; ++ prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices); ++ } ++ for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++) ++ { ++ if (i >= numSymbols) ++ return; ++ prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices); ++ } ++ for (; i < numSymbols; i++) ++ prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices); ++} ++ ++static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices) ++{ ++ LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices); ++ p->counters[posState] = p->tableSize; ++} ++ ++static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices) ++{ ++ UInt32 posState; ++ for (posState = 0; posState < numPosStates; posState++) ++ LenPriceEnc_UpdateTable(p, posState, ProbPrices); ++} ++ ++static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices) ++{ ++ LenEnc_Encode(&p->p, rc, symbol, posState); ++ if (updatePrice) ++ if (--p->counters[posState] == 0) ++ LenPriceEnc_UpdateTable(p, posState, ProbPrices); ++} ++ ++ ++ ++ ++static void MovePos(CLzmaEnc *p, UInt32 num) ++{ ++ #ifdef SHOW_STAT ++ ttt += num; ++ printf("\n MovePos %d", num); ++ #endif ++ if (num != 0) ++ { ++ p->additionalOffset += num; ++ p->matchFinder.Skip(p->matchFinderObj, num); ++ } ++} ++ ++static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes) ++{ ++ UInt32 lenRes = 0, numPairs; ++ p->numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); ++ numPairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matches); ++ #ifdef SHOW_STAT ++ printf("\n i = %d numPairs = %d ", ttt, numPairs / 2); ++ ttt++; ++ { ++ UInt32 i; ++ for (i = 0; i < numPairs; i += 2) ++ printf("%2d %6d | ", p->matches[i], p->matches[i + 1]); ++ } ++ #endif ++ if (numPairs > 0) ++ { ++ lenRes = p->matches[numPairs - 2]; ++ if (lenRes == p->numFastBytes) ++ { ++ const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ UInt32 distance = p->matches[numPairs - 1] + 1; ++ UInt32 numAvail = p->numAvail; ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ { ++ const Byte *pby2 = pby - distance; ++ for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++); ++ } ++ } ++ } ++ p->additionalOffset++; ++ *numDistancePairsRes = numPairs; ++ return lenRes; ++} ++ ++ ++#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False; ++#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False; ++#define IsShortRep(p) ((p)->backPrev == 0) ++ ++static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState) ++{ ++ return ++ GET_PRICE_0(p->isRepG0[state]) + ++ GET_PRICE_0(p->isRep0Long[state][posState]); ++} ++ ++static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState) ++{ ++ UInt32 price; ++ if (repIndex == 0) ++ { ++ price = GET_PRICE_0(p->isRepG0[state]); ++ price += GET_PRICE_1(p->isRep0Long[state][posState]); ++ } ++ else ++ { ++ price = GET_PRICE_1(p->isRepG0[state]); ++ if (repIndex == 1) ++ price += GET_PRICE_0(p->isRepG1[state]); ++ else ++ { ++ price += GET_PRICE_1(p->isRepG1[state]); ++ price += GET_PRICE(p->isRepG2[state], repIndex - 2); ++ } ++ } ++ return price; ++} ++ ++static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState) ++{ ++ return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] + ++ GetPureRepPrice(p, repIndex, state, posState); ++} ++ ++static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur) ++{ ++ UInt32 posMem = p->opt[cur].posPrev; ++ UInt32 backMem = p->opt[cur].backPrev; ++ p->optimumEndIndex = cur; ++ do ++ { ++ if (p->opt[cur].prev1IsChar) ++ { ++ MakeAsChar(&p->opt[posMem]) ++ p->opt[posMem].posPrev = posMem - 1; ++ if (p->opt[cur].prev2) ++ { ++ p->opt[posMem - 1].prev1IsChar = False; ++ p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2; ++ p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2; ++ } ++ } ++ { ++ UInt32 posPrev = posMem; ++ UInt32 backCur = backMem; ++ ++ backMem = p->opt[posPrev].backPrev; ++ posMem = p->opt[posPrev].posPrev; ++ ++ p->opt[posPrev].backPrev = backCur; ++ p->opt[posPrev].posPrev = cur; ++ cur = posPrev; ++ } ++ } ++ while (cur != 0); ++ *backRes = p->opt[0].backPrev; ++ p->optimumCurrentIndex = p->opt[0].posPrev; ++ return p->optimumCurrentIndex; ++} ++ ++#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300) ++ ++static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes) ++{ ++ UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur; ++ UInt32 matchPrice, repMatchPrice, normalMatchPrice; ++ UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS]; ++ UInt32 *matches; ++ const Byte *data; ++ Byte curByte, matchByte; ++ if (p->optimumEndIndex != p->optimumCurrentIndex) ++ { ++ const COptimal *opt = &p->opt[p->optimumCurrentIndex]; ++ UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex; ++ *backRes = opt->backPrev; ++ p->optimumCurrentIndex = opt->posPrev; ++ return lenRes; ++ } ++ p->optimumCurrentIndex = p->optimumEndIndex = 0; ++ ++ if (p->additionalOffset == 0) ++ mainLen = ReadMatchDistances(p, &numPairs); ++ else ++ { ++ mainLen = p->longestMatchLength; ++ numPairs = p->numPairs; ++ } ++ ++ numAvail = p->numAvail; ++ if (numAvail < 2) ++ { ++ *backRes = (UInt32)(-1); ++ return 1; ++ } ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ repMaxIndex = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 lenTest; ++ const Byte *data2; ++ reps[i] = p->reps[i]; ++ data2 = data - (reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ { ++ repLens[i] = 0; ++ continue; ++ } ++ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); ++ repLens[i] = lenTest; ++ if (lenTest > repLens[repMaxIndex]) ++ repMaxIndex = i; ++ } ++ if (repLens[repMaxIndex] >= p->numFastBytes) ++ { ++ UInt32 lenRes; ++ *backRes = repMaxIndex; ++ lenRes = repLens[repMaxIndex]; ++ MovePos(p, lenRes - 1); ++ return lenRes; ++ } ++ ++ matches = p->matches; ++ if (mainLen >= p->numFastBytes) ++ { ++ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 1); ++ return mainLen; ++ } ++ curByte = *data; ++ matchByte = *(data - (reps[0] + 1)); ++ ++ if (mainLen < 2 && curByte != matchByte && repLens[repMaxIndex] < 2) ++ { ++ *backRes = (UInt32)-1; ++ return 1; ++ } ++ ++ p->opt[0].state = (CState)p->state; ++ ++ posState = (position & p->pbMask); ++ ++ { ++ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); ++ p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) + ++ (!IsCharState(p->state) ? ++ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : ++ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); ++ } ++ ++ MakeAsChar(&p->opt[1]); ++ ++ matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]); ++ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]); ++ ++ if (matchByte == curByte) ++ { ++ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState); ++ if (shortRepPrice < p->opt[1].price) ++ { ++ p->opt[1].price = shortRepPrice; ++ MakeAsShortRep(&p->opt[1]); ++ } ++ } ++ lenEnd = ((mainLen >= repLens[repMaxIndex]) ? mainLen : repLens[repMaxIndex]); ++ ++ if (lenEnd < 2) ++ { ++ *backRes = p->opt[1].backPrev; ++ return 1; ++ } ++ ++ p->opt[1].posPrev = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ p->opt[0].backs[i] = reps[i]; ++ ++ len = lenEnd; ++ do ++ p->opt[len--].price = kInfinityPrice; ++ while (len >= 2); ++ ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 repLen = repLens[i]; ++ UInt32 price; ++ if (repLen < 2) ++ continue; ++ price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState); ++ do ++ { ++ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2]; ++ COptimal *opt = &p->opt[repLen]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = 0; ++ opt->backPrev = i; ++ opt->prev1IsChar = False; ++ } ++ } ++ while (--repLen >= 2); ++ } ++ ++ normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]); ++ ++ len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2); ++ if (len <= mainLen) ++ { ++ UInt32 offs = 0; ++ while (len > matches[offs]) ++ offs += 2; ++ for (; ; len++) ++ { ++ COptimal *opt; ++ UInt32 distance = matches[offs + 1]; ++ ++ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN]; ++ UInt32 lenToPosState = GetLenToPosState(len); ++ if (distance < kNumFullDistances) ++ curAndLenPrice += p->distancesPrices[lenToPosState][distance]; ++ else ++ { ++ UInt32 slot; ++ GetPosSlot2(distance, slot); ++ curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot]; ++ } ++ opt = &p->opt[len]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = 0; ++ opt->backPrev = distance + LZMA_NUM_REPS; ++ opt->prev1IsChar = False; ++ } ++ if (len == matches[offs]) ++ { ++ offs += 2; ++ if (offs == numPairs) ++ break; ++ } ++ } ++ } ++ ++ cur = 0; ++ ++ #ifdef SHOW_STAT2 ++ if (position >= 0) ++ { ++ unsigned i; ++ printf("\n pos = %4X", position); ++ for (i = cur; i <= lenEnd; i++) ++ printf("\nprice[%4X] = %d", position - cur + i, p->opt[i].price); ++ } ++ #endif ++ ++ for (;;) ++ { ++ UInt32 numAvailFull, newLen, numPairs, posPrev, state, posState, startLen; ++ UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice; ++ Bool nextIsChar; ++ Byte curByte, matchByte; ++ const Byte *data; ++ COptimal *curOpt; ++ COptimal *nextOpt; ++ ++ cur++; ++ if (cur == lenEnd) ++ return Backward(p, backRes, cur); ++ ++ newLen = ReadMatchDistances(p, &numPairs); ++ if (newLen >= p->numFastBytes) ++ { ++ p->numPairs = numPairs; ++ p->longestMatchLength = newLen; ++ return Backward(p, backRes, cur); ++ } ++ position++; ++ curOpt = &p->opt[cur]; ++ posPrev = curOpt->posPrev; ++ if (curOpt->prev1IsChar) ++ { ++ posPrev--; ++ if (curOpt->prev2) ++ { ++ state = p->opt[curOpt->posPrev2].state; ++ if (curOpt->backPrev2 < LZMA_NUM_REPS) ++ state = kRepNextStates[state]; ++ else ++ state = kMatchNextStates[state]; ++ } ++ else ++ state = p->opt[posPrev].state; ++ state = kLiteralNextStates[state]; ++ } ++ else ++ state = p->opt[posPrev].state; ++ if (posPrev == cur - 1) ++ { ++ if (IsShortRep(curOpt)) ++ state = kShortRepNextStates[state]; ++ else ++ state = kLiteralNextStates[state]; ++ } ++ else ++ { ++ UInt32 pos; ++ const COptimal *prevOpt; ++ if (curOpt->prev1IsChar && curOpt->prev2) ++ { ++ posPrev = curOpt->posPrev2; ++ pos = curOpt->backPrev2; ++ state = kRepNextStates[state]; ++ } ++ else ++ { ++ pos = curOpt->backPrev; ++ if (pos < LZMA_NUM_REPS) ++ state = kRepNextStates[state]; ++ else ++ state = kMatchNextStates[state]; ++ } ++ prevOpt = &p->opt[posPrev]; ++ if (pos < LZMA_NUM_REPS) ++ { ++ UInt32 i; ++ reps[0] = prevOpt->backs[pos]; ++ for (i = 1; i <= pos; i++) ++ reps[i] = prevOpt->backs[i - 1]; ++ for (; i < LZMA_NUM_REPS; i++) ++ reps[i] = prevOpt->backs[i]; ++ } ++ else ++ { ++ UInt32 i; ++ reps[0] = (pos - LZMA_NUM_REPS); ++ for (i = 1; i < LZMA_NUM_REPS; i++) ++ reps[i] = prevOpt->backs[i - 1]; ++ } ++ } ++ curOpt->state = (CState)state; ++ ++ curOpt->backs[0] = reps[0]; ++ curOpt->backs[1] = reps[1]; ++ curOpt->backs[2] = reps[2]; ++ curOpt->backs[3] = reps[3]; ++ ++ curPrice = curOpt->price; ++ nextIsChar = False; ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ curByte = *data; ++ matchByte = *(data - (reps[0] + 1)); ++ ++ posState = (position & p->pbMask); ++ ++ curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]); ++ { ++ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); ++ curAnd1Price += ++ (!IsCharState(state) ? ++ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : ++ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); ++ } ++ ++ nextOpt = &p->opt[cur + 1]; ++ ++ if (curAnd1Price < nextOpt->price) ++ { ++ nextOpt->price = curAnd1Price; ++ nextOpt->posPrev = cur; ++ MakeAsChar(nextOpt); ++ nextIsChar = True; ++ } ++ ++ matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]); ++ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]); ++ ++ if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0)) ++ { ++ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState); ++ if (shortRepPrice <= nextOpt->price) ++ { ++ nextOpt->price = shortRepPrice; ++ nextOpt->posPrev = cur; ++ MakeAsShortRep(nextOpt); ++ nextIsChar = True; ++ } ++ } ++ numAvailFull = p->numAvail; ++ { ++ UInt32 temp = kNumOpts - 1 - cur; ++ if (temp < numAvailFull) ++ numAvailFull = temp; ++ } ++ ++ if (numAvailFull < 2) ++ continue; ++ numAvail = (numAvailFull <= p->numFastBytes ? numAvailFull : p->numFastBytes); ++ ++ if (!nextIsChar && matchByte != curByte) /* speed optimization */ ++ { ++ /* try Literal + rep0 */ ++ UInt32 temp; ++ UInt32 lenTest2; ++ const Byte *data2 = data - (reps[0] + 1); ++ UInt32 limit = p->numFastBytes + 1; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ ++ for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++); ++ lenTest2 = temp - 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kLiteralNextStates[state]; ++ UInt32 posStateNext = (position + 1) & p->pbMask; ++ UInt32 nextRepMatchPrice = curAnd1Price + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ UInt32 offset = cur + 1 + lenTest2; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = False; ++ } ++ } ++ } ++ } ++ ++ startLen = 2; /* speed optimization */ ++ { ++ UInt32 repIndex; ++ for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++) ++ { ++ UInt32 lenTest; ++ UInt32 lenTestTemp; ++ UInt32 price; ++ const Byte *data2 = data - (reps[repIndex] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); ++ while (lenEnd < cur + lenTest) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ lenTestTemp = lenTest; ++ price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState); ++ do ++ { ++ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2]; ++ COptimal *opt = &p->opt[cur + lenTest]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur; ++ opt->backPrev = repIndex; ++ opt->prev1IsChar = False; ++ } ++ } ++ while (--lenTest >= 2); ++ lenTest = lenTestTemp; ++ ++ if (repIndex == 0) ++ startLen = lenTest + 1; ++ ++ /* if (_maxMode) */ ++ { ++ UInt32 lenTest2 = lenTest + 1; ++ UInt32 limit = lenTest2 + p->numFastBytes; ++ UInt32 nextRepMatchPrice; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); ++ lenTest2 -= lenTest + 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kRepNextStates[state]; ++ UInt32 posStateNext = (position + lenTest) & p->pbMask; ++ UInt32 curAndLenCharPrice = ++ price + p->repLenEnc.prices[posState][lenTest - 2] + ++ GET_PRICE_0(p->isMatch[state2][posStateNext]) + ++ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), ++ data[lenTest], data2[lenTest], p->ProbPrices); ++ state2 = kLiteralNextStates[state2]; ++ posStateNext = (position + lenTest + 1) & p->pbMask; ++ nextRepMatchPrice = curAndLenCharPrice + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ UInt32 offset = cur + lenTest + 1 + lenTest2; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + lenTest + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = True; ++ opt->posPrev2 = cur; ++ opt->backPrev2 = repIndex; ++ } ++ } ++ } ++ } ++ } ++ } ++ /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */ ++ if (newLen > numAvail) ++ { ++ newLen = numAvail; ++ for (numPairs = 0; newLen > matches[numPairs]; numPairs += 2); ++ matches[numPairs] = newLen; ++ numPairs += 2; ++ } ++ if (newLen >= startLen) ++ { ++ UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]); ++ UInt32 offs, curBack, posSlot; ++ UInt32 lenTest; ++ while (lenEnd < cur + newLen) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ ++ offs = 0; ++ while (startLen > matches[offs]) ++ offs += 2; ++ curBack = matches[offs + 1]; ++ GetPosSlot2(curBack, posSlot); ++ for (lenTest = /*2*/ startLen; ; lenTest++) ++ { ++ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN]; ++ UInt32 lenToPosState = GetLenToPosState(lenTest); ++ COptimal *opt; ++ if (curBack < kNumFullDistances) ++ curAndLenPrice += p->distancesPrices[lenToPosState][curBack]; ++ else ++ curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask]; ++ ++ opt = &p->opt[cur + lenTest]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur; ++ opt->backPrev = curBack + LZMA_NUM_REPS; ++ opt->prev1IsChar = False; ++ } ++ ++ if (/*_maxMode && */lenTest == matches[offs]) ++ { ++ /* Try Match + Literal + Rep0 */ ++ const Byte *data2 = data - (curBack + 1); ++ UInt32 lenTest2 = lenTest + 1; ++ UInt32 limit = lenTest2 + p->numFastBytes; ++ UInt32 nextRepMatchPrice; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); ++ lenTest2 -= lenTest + 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kMatchNextStates[state]; ++ UInt32 posStateNext = (position + lenTest) & p->pbMask; ++ UInt32 curAndLenCharPrice = curAndLenPrice + ++ GET_PRICE_0(p->isMatch[state2][posStateNext]) + ++ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), ++ data[lenTest], data2[lenTest], p->ProbPrices); ++ state2 = kLiteralNextStates[state2]; ++ posStateNext = (posStateNext + 1) & p->pbMask; ++ nextRepMatchPrice = curAndLenCharPrice + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 offset = cur + lenTest + 1 + lenTest2; ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + lenTest + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = True; ++ opt->posPrev2 = cur; ++ opt->backPrev2 = curBack + LZMA_NUM_REPS; ++ } ++ } ++ } ++ offs += 2; ++ if (offs == numPairs) ++ break; ++ curBack = matches[offs + 1]; ++ if (curBack >= kNumFullDistances) ++ GetPosSlot2(curBack, posSlot); ++ } ++ } ++ } ++ } ++} ++ ++#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist)) ++ ++static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes) ++{ ++ UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i; ++ const Byte *data; ++ const UInt32 *matches; ++ ++ if (p->additionalOffset == 0) ++ mainLen = ReadMatchDistances(p, &numPairs); ++ else ++ { ++ mainLen = p->longestMatchLength; ++ numPairs = p->numPairs; ++ } ++ ++ numAvail = p->numAvail; ++ *backRes = (UInt32)-1; ++ if (numAvail < 2) ++ return 1; ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ ++ repLen = repIndex = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 len; ++ const Byte *data2 = data - (p->reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ for (len = 2; len < numAvail && data[len] == data2[len]; len++); ++ if (len >= p->numFastBytes) ++ { ++ *backRes = i; ++ MovePos(p, len - 1); ++ return len; ++ } ++ if (len > repLen) ++ { ++ repIndex = i; ++ repLen = len; ++ } ++ } ++ ++ matches = p->matches; ++ if (mainLen >= p->numFastBytes) ++ { ++ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 1); ++ return mainLen; ++ } ++ ++ mainDist = 0; /* for GCC */ ++ if (mainLen >= 2) ++ { ++ mainDist = matches[numPairs - 1]; ++ while (numPairs > 2 && mainLen == matches[numPairs - 4] + 1) ++ { ++ if (!ChangePair(matches[numPairs - 3], mainDist)) ++ break; ++ numPairs -= 2; ++ mainLen = matches[numPairs - 2]; ++ mainDist = matches[numPairs - 1]; ++ } ++ if (mainLen == 2 && mainDist >= 0x80) ++ mainLen = 1; ++ } ++ ++ if (repLen >= 2 && ( ++ (repLen + 1 >= mainLen) || ++ (repLen + 2 >= mainLen && mainDist >= (1 << 9)) || ++ (repLen + 3 >= mainLen && mainDist >= (1 << 15)))) ++ { ++ *backRes = repIndex; ++ MovePos(p, repLen - 1); ++ return repLen; ++ } ++ ++ if (mainLen < 2 || numAvail <= 2) ++ return 1; ++ ++ p->longestMatchLength = ReadMatchDistances(p, &p->numPairs); ++ if (p->longestMatchLength >= 2) ++ { ++ UInt32 newDistance = matches[p->numPairs - 1]; ++ if ((p->longestMatchLength >= mainLen && newDistance < mainDist) || ++ (p->longestMatchLength == mainLen + 1 && !ChangePair(mainDist, newDistance)) || ++ (p->longestMatchLength > mainLen + 1) || ++ (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist))) ++ return 1; ++ } ++ ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 len, limit; ++ const Byte *data2 = data - (p->reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ limit = mainLen - 1; ++ for (len = 2; len < limit && data[len] == data2[len]; len++); ++ if (len >= limit) ++ return 1; ++ } ++ *backRes = mainDist + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 2); ++ return mainLen; ++} ++ ++static void WriteEndMarker(CLzmaEnc *p, UInt32 posState) ++{ ++ UInt32 len; ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); ++ p->state = kMatchNextStates[p->state]; ++ len = LZMA_MATCH_LEN_MIN; ++ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1); ++ RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits); ++ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask); ++} ++ ++static SRes CheckErrors(CLzmaEnc *p) ++{ ++ if (p->result != SZ_OK) ++ return p->result; ++ if (p->rc.res != SZ_OK) ++ p->result = SZ_ERROR_WRITE; ++ if (p->matchFinderBase.result != SZ_OK) ++ p->result = SZ_ERROR_READ; ++ if (p->result != SZ_OK) ++ p->finished = True; ++ return p->result; ++} ++ ++static SRes Flush(CLzmaEnc *p, UInt32 nowPos) ++{ ++ /* ReleaseMFStream(); */ ++ p->finished = True; ++ if (p->writeEndMark) ++ WriteEndMarker(p, nowPos & p->pbMask); ++ RangeEnc_FlushData(&p->rc); ++ RangeEnc_FlushStream(&p->rc); ++ return CheckErrors(p); ++} ++ ++static void FillAlignPrices(CLzmaEnc *p) ++{ ++ UInt32 i; ++ for (i = 0; i < kAlignTableSize; i++) ++ p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices); ++ p->alignPriceCount = 0; ++} ++ ++static void FillDistancesPrices(CLzmaEnc *p) ++{ ++ UInt32 tempPrices[kNumFullDistances]; ++ UInt32 i, lenToPosState; ++ for (i = kStartPosModelIndex; i < kNumFullDistances; i++) ++ { ++ UInt32 posSlot = GetPosSlot1(i); ++ UInt32 footerBits = ((posSlot >> 1) - 1); ++ UInt32 base = ((2 | (posSlot & 1)) << footerBits); ++ tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices); ++ } ++ ++ for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++) ++ { ++ UInt32 posSlot; ++ const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState]; ++ UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState]; ++ for (posSlot = 0; posSlot < p->distTableSize; posSlot++) ++ posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices); ++ for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++) ++ posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits); ++ ++ { ++ UInt32 *distancesPrices = p->distancesPrices[lenToPosState]; ++ UInt32 i; ++ for (i = 0; i < kStartPosModelIndex; i++) ++ distancesPrices[i] = posSlotPrices[i]; ++ for (; i < kNumFullDistances; i++) ++ distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i]; ++ } ++ } ++ p->matchPriceCount = 0; ++} ++ ++void LzmaEnc_Construct(CLzmaEnc *p) ++{ ++ RangeEnc_Construct(&p->rc); ++ MatchFinder_Construct(&p->matchFinderBase); ++ #ifndef _7ZIP_ST ++ MatchFinderMt_Construct(&p->matchFinderMt); ++ p->matchFinderMt.MatchFinder = &p->matchFinderBase; ++ #endif ++ ++ { ++ CLzmaEncProps props; ++ LzmaEncProps_Init(&props); ++ LzmaEnc_SetProps(p, &props); ++ } ++ ++ #ifndef LZMA_LOG_BSR ++ LzmaEnc_FastPosInit(p->g_FastPos); ++ #endif ++ ++ LzmaEnc_InitPriceTables(p->ProbPrices); ++ p->litProbs = 0; ++ p->saveState.litProbs = 0; ++} ++ ++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc) ++{ ++ void *p; ++ p = alloc->Alloc(alloc, sizeof(CLzmaEnc)); ++ if (p != 0) ++ LzmaEnc_Construct((CLzmaEnc *)p); ++ return p; ++} ++ ++void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->litProbs); ++ alloc->Free(alloc, p->saveState.litProbs); ++ p->litProbs = 0; ++ p->saveState.litProbs = 0; ++} ++ ++void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ #ifndef _7ZIP_ST ++ MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); ++ #endif ++ MatchFinder_Free(&p->matchFinderBase, allocBig); ++ LzmaEnc_FreeLits(p, alloc); ++ RangeEnc_Free(&p->rc, alloc); ++} ++ ++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig); ++ alloc->Free(alloc, p); ++} ++ ++static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize) ++{ ++ UInt32 nowPos32, startPos32; ++ if (p->needInit) ++ { ++ p->matchFinder.Init(p->matchFinderObj); ++ p->needInit = 0; ++ } ++ ++ if (p->finished) ++ return p->result; ++ RINOK(CheckErrors(p)); ++ ++ nowPos32 = (UInt32)p->nowPos64; ++ startPos32 = nowPos32; ++ ++ if (p->nowPos64 == 0) ++ { ++ UInt32 numPairs; ++ Byte curByte; ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) ++ return Flush(p, nowPos32); ++ ReadMatchDistances(p, &numPairs); ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0); ++ p->state = kLiteralNextStates[p->state]; ++ curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset); ++ LitEnc_Encode(&p->rc, p->litProbs, curByte); ++ p->additionalOffset--; ++ nowPos32++; ++ } ++ ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0) ++ for (;;) ++ { ++ UInt32 pos, len, posState; ++ ++ if (p->fastMode) ++ len = GetOptimumFast(p, &pos); ++ else ++ len = GetOptimum(p, nowPos32, &pos); ++ ++ #ifdef SHOW_STAT2 ++ printf("\n pos = %4X, len = %d pos = %d", nowPos32, len, pos); ++ #endif ++ ++ posState = nowPos32 & p->pbMask; ++ if (len == 1 && pos == (UInt32)-1) ++ { ++ Byte curByte; ++ CLzmaProb *probs; ++ const Byte *data; ++ ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0); ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; ++ curByte = *data; ++ probs = LIT_PROBS(nowPos32, *(data - 1)); ++ if (IsCharState(p->state)) ++ LitEnc_Encode(&p->rc, probs, curByte); ++ else ++ LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1)); ++ p->state = kLiteralNextStates[p->state]; ++ } ++ else ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); ++ if (pos < LZMA_NUM_REPS) ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1); ++ if (pos == 0) ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0); ++ RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1)); ++ } ++ else ++ { ++ UInt32 distance = p->reps[pos]; ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1); ++ if (pos == 1) ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0); ++ else ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1); ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2); ++ if (pos == 3) ++ p->reps[3] = p->reps[2]; ++ p->reps[2] = p->reps[1]; ++ } ++ p->reps[1] = p->reps[0]; ++ p->reps[0] = distance; ++ } ++ if (len == 1) ++ p->state = kShortRepNextStates[p->state]; ++ else ++ { ++ LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ p->state = kRepNextStates[p->state]; ++ } ++ } ++ else ++ { ++ UInt32 posSlot; ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); ++ p->state = kMatchNextStates[p->state]; ++ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ pos -= LZMA_NUM_REPS; ++ GetPosSlot(pos, posSlot); ++ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot); ++ ++ if (posSlot >= kStartPosModelIndex) ++ { ++ UInt32 footerBits = ((posSlot >> 1) - 1); ++ UInt32 base = ((2 | (posSlot & 1)) << footerBits); ++ UInt32 posReduced = pos - base; ++ ++ if (posSlot < kEndPosModelIndex) ++ RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced); ++ else ++ { ++ RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits); ++ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask); ++ p->alignPriceCount++; ++ } ++ } ++ p->reps[3] = p->reps[2]; ++ p->reps[2] = p->reps[1]; ++ p->reps[1] = p->reps[0]; ++ p->reps[0] = pos; ++ p->matchPriceCount++; ++ } ++ } ++ p->additionalOffset -= len; ++ nowPos32 += len; ++ if (p->additionalOffset == 0) ++ { ++ UInt32 processed; ++ if (!p->fastMode) ++ { ++ if (p->matchPriceCount >= (1 << 7)) ++ FillDistancesPrices(p); ++ if (p->alignPriceCount >= kAlignTableSize) ++ FillAlignPrices(p); ++ } ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) ++ break; ++ processed = nowPos32 - startPos32; ++ if (useLimits) ++ { ++ if (processed + kNumOpts + 300 >= maxUnpackSize || ++ RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize) ++ break; ++ } ++ else if (processed >= (1 << 15)) ++ { ++ p->nowPos64 += nowPos32 - startPos32; ++ return CheckErrors(p); ++ } ++ } ++ } ++ p->nowPos64 += nowPos32 - startPos32; ++ return Flush(p, nowPos32); ++} ++ ++#define kBigHashDicLimit ((UInt32)1 << 24) ++ ++static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ UInt32 beforeSize = kNumOpts; ++ Bool btMode; ++ if (!RangeEnc_Alloc(&p->rc, alloc)) ++ return SZ_ERROR_MEM; ++ btMode = (p->matchFinderBase.btMode != 0); ++ #ifndef _7ZIP_ST ++ p->mtMode = (p->multiThread && !p->fastMode && btMode); ++ #endif ++ ++ { ++ unsigned lclp = p->lc + p->lp; ++ if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp) ++ { ++ LzmaEnc_FreeLits(p, alloc); ++ p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); ++ p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); ++ if (p->litProbs == 0 || p->saveState.litProbs == 0) ++ { ++ LzmaEnc_FreeLits(p, alloc); ++ return SZ_ERROR_MEM; ++ } ++ p->lclp = lclp; ++ } ++ } ++ ++ p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit); ++ ++ if (beforeSize + p->dictSize < keepWindowSize) ++ beforeSize = keepWindowSize - p->dictSize; ++ ++ #ifndef _7ZIP_ST ++ if (p->mtMode) ++ { ++ RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)); ++ p->matchFinderObj = &p->matchFinderMt; ++ MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder); ++ } ++ else ++ #endif ++ { ++ if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)) ++ return SZ_ERROR_MEM; ++ p->matchFinderObj = &p->matchFinderBase; ++ MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder); ++ } ++ return SZ_OK; ++} ++ ++void LzmaEnc_Init(CLzmaEnc *p) ++{ ++ UInt32 i; ++ p->state = 0; ++ for (i = 0 ; i < LZMA_NUM_REPS; i++) ++ p->reps[i] = 0; ++ ++ RangeEnc_Init(&p->rc); ++ ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ UInt32 j; ++ for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++) ++ { ++ p->isMatch[i][j] = kProbInitValue; ++ p->isRep0Long[i][j] = kProbInitValue; ++ } ++ p->isRep[i] = kProbInitValue; ++ p->isRepG0[i] = kProbInitValue; ++ p->isRepG1[i] = kProbInitValue; ++ p->isRepG2[i] = kProbInitValue; ++ } ++ ++ { ++ UInt32 num = 0x300 << (p->lp + p->lc); ++ for (i = 0; i < num; i++) ++ p->litProbs[i] = kProbInitValue; ++ } ++ ++ { ++ for (i = 0; i < kNumLenToPosStates; i++) ++ { ++ CLzmaProb *probs = p->posSlotEncoder[i]; ++ UInt32 j; ++ for (j = 0; j < (1 << kNumPosSlotBits); j++) ++ probs[j] = kProbInitValue; ++ } ++ } ++ { ++ for (i = 0; i < kNumFullDistances - kEndPosModelIndex; i++) ++ p->posEncoders[i] = kProbInitValue; ++ } ++ ++ LenEnc_Init(&p->lenEnc.p); ++ LenEnc_Init(&p->repLenEnc.p); ++ ++ for (i = 0; i < (1 << kNumAlignBits); i++) ++ p->posAlignEncoder[i] = kProbInitValue; ++ ++ p->optimumEndIndex = 0; ++ p->optimumCurrentIndex = 0; ++ p->additionalOffset = 0; ++ ++ p->pbMask = (1 << p->pb) - 1; ++ p->lpMask = (1 << p->lp) - 1; ++} ++ ++void LzmaEnc_InitPrices(CLzmaEnc *p) ++{ ++ if (!p->fastMode) ++ { ++ FillDistancesPrices(p); ++ FillAlignPrices(p); ++ } ++ ++ p->lenEnc.tableSize = ++ p->repLenEnc.tableSize = ++ p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN; ++ LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices); ++ LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices); ++} ++ ++static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ UInt32 i; ++ for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++) ++ if (p->dictSize <= ((UInt32)1 << i)) ++ break; ++ p->distTableSize = i * 2; ++ ++ p->finished = False; ++ p->result = SZ_OK; ++ RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig)); ++ LzmaEnc_Init(p); ++ LzmaEnc_InitPrices(p); ++ p->nowPos64 = 0; ++ return SZ_OK; ++} ++ ++static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ p->matchFinderBase.stream = inStream; ++ p->needInit = 1; ++ p->rc.outStream = outStream; ++ return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig); ++} ++ ++SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, ++ ISeqInStream *inStream, UInt32 keepWindowSize, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ p->matchFinderBase.stream = inStream; ++ p->needInit = 1; ++ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); ++} ++ ++static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) ++{ ++ p->matchFinderBase.directInput = 1; ++ p->matchFinderBase.bufferBase = (Byte *)src; ++ p->matchFinderBase.directInputRem = srcLen; ++} ++ ++SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, ++ UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ LzmaEnc_SetInputBuf(p, src, srcLen); ++ p->needInit = 1; ++ ++ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); ++} ++ ++void LzmaEnc_Finish(CLzmaEncHandle pp) ++{ ++ #ifndef _7ZIP_ST ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ if (p->mtMode) ++ MatchFinderMt_ReleaseStream(&p->matchFinderMt); ++ #else ++ pp = pp; ++ #endif ++} ++ ++typedef struct ++{ ++ ISeqOutStream funcTable; ++ Byte *data; ++ SizeT rem; ++ Bool overflow; ++} CSeqOutStreamBuf; ++ ++static size_t MyWrite(void *pp, const void *data, size_t size) ++{ ++ CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp; ++ if (p->rem < size) ++ { ++ size = p->rem; ++ p->overflow = True; ++ } ++ memcpy(p->data, data, size); ++ p->rem -= size; ++ p->data += size; ++ return size; ++} ++ ++ ++UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp) ++{ ++ const CLzmaEnc *p = (CLzmaEnc *)pp; ++ return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); ++} ++ ++const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp) ++{ ++ const CLzmaEnc *p = (CLzmaEnc *)pp; ++ return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; ++} ++ ++SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, ++ Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ UInt64 nowPos64; ++ SRes res; ++ CSeqOutStreamBuf outStream; ++ ++ outStream.funcTable.Write = MyWrite; ++ outStream.data = dest; ++ outStream.rem = *destLen; ++ outStream.overflow = False; ++ ++ p->writeEndMark = False; ++ p->finished = False; ++ p->result = SZ_OK; ++ ++ if (reInit) ++ LzmaEnc_Init(p); ++ LzmaEnc_InitPrices(p); ++ nowPos64 = p->nowPos64; ++ RangeEnc_Init(&p->rc); ++ p->rc.outStream = &outStream.funcTable; ++ ++ res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize); ++ ++ *unpackSize = (UInt32)(p->nowPos64 - nowPos64); ++ *destLen -= outStream.rem; ++ if (outStream.overflow) ++ return SZ_ERROR_OUTPUT_EOF; ++ ++ return res; ++} ++ ++static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) ++{ ++ SRes res = SZ_OK; ++ ++ #ifndef _7ZIP_ST ++ Byte allocaDummy[0x300]; ++ int i = 0; ++ for (i = 0; i < 16; i++) ++ allocaDummy[i] = (Byte)i; ++ #endif ++ ++ for (;;) ++ { ++ res = LzmaEnc_CodeOneBlock(p, False, 0, 0); ++ if (res != SZ_OK || p->finished != 0) ++ break; ++ if (progress != 0) ++ { ++ res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc)); ++ if (res != SZ_OK) ++ { ++ res = SZ_ERROR_PROGRESS; ++ break; ++ } ++ } ++ } ++ LzmaEnc_Finish(p); ++ return res; ++} ++ ++SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig)); ++ return LzmaEnc_Encode2((CLzmaEnc *)pp, progress); ++} ++ ++SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ int i; ++ UInt32 dictSize = p->dictSize; ++ if (*size < LZMA_PROPS_SIZE) ++ return SZ_ERROR_PARAM; ++ *size = LZMA_PROPS_SIZE; ++ props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc); ++ ++ for (i = 11; i <= 30; i++) ++ { ++ if (dictSize <= ((UInt32)2 << i)) ++ { ++ dictSize = (2 << i); ++ break; ++ } ++ if (dictSize <= ((UInt32)3 << i)) ++ { ++ dictSize = (3 << i); ++ break; ++ } ++ } ++ ++ for (i = 0; i < 4; i++) ++ props[1 + i] = (Byte)(dictSize >> (8 * i)); ++ return SZ_OK; ++} ++ ++SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ SRes res; ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ ++ CSeqOutStreamBuf outStream; ++ ++ LzmaEnc_SetInputBuf(p, src, srcLen); ++ ++ outStream.funcTable.Write = MyWrite; ++ outStream.data = dest; ++ outStream.rem = *destLen; ++ outStream.overflow = False; ++ ++ p->writeEndMark = writeEndMark; ++ ++ p->rc.outStream = &outStream.funcTable; ++ res = LzmaEnc_MemPrepare(pp, src, srcLen, 0, alloc, allocBig); ++ if (res == SZ_OK) ++ res = LzmaEnc_Encode2(p, progress); ++ ++ *destLen -= outStream.rem; ++ if (outStream.overflow) ++ return SZ_ERROR_OUTPUT_EOF; ++ return res; ++} ++ ++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc); ++ SRes res; ++ if (p == 0) ++ return SZ_ERROR_MEM; ++ ++ res = LzmaEnc_SetProps(p, props); ++ if (res == SZ_OK) ++ { ++ res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize); ++ if (res == SZ_OK) ++ res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen, ++ writeEndMark, progress, alloc, allocBig); ++ } ++ ++ LzmaEnc_Destroy(p, alloc, allocBig); ++ return res; ++} +--- /dev/null ++++ b/lib/lzma/Makefile +@@ -0,0 +1,7 @@ ++lzma_compress-objs := LzFind.o LzmaEnc.o ++lzma_decompress-objs := LzmaDec.o ++ ++obj-$(CONFIG_LZMA_COMPRESS) += lzma_compress.o ++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma_decompress.o ++ ++EXTRA_CFLAGS += -Iinclude/linux -Iinclude/linux/lzma -include types.h diff --git a/target/linux/generic/patches-3.18/531-debloat_lzma.patch b/target/linux/generic/patches-3.18/531-debloat_lzma.patch new file mode 100644 index 0000000..aa3c498 --- /dev/null +++ b/target/linux/generic/patches-3.18/531-debloat_lzma.patch @@ -0,0 +1,1024 @@ +--- a/include/linux/lzma/LzmaDec.h ++++ b/include/linux/lzma/LzmaDec.h +@@ -31,14 +31,6 @@ typedef struct _CLzmaProps + UInt32 dicSize; + } CLzmaProps; + +-/* LzmaProps_Decode - decodes properties +-Returns: +- SZ_OK +- SZ_ERROR_UNSUPPORTED - Unsupported properties +-*/ +- +-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); +- + + /* ---------- LZMA Decoder state ---------- */ + +@@ -70,8 +62,6 @@ typedef struct + + #define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } + +-void LzmaDec_Init(CLzmaDec *p); +- + /* There are two types of LZMA streams: + 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. + 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ +@@ -108,97 +98,6 @@ typedef enum + + /* ELzmaStatus is used only as output value for function call */ + +- +-/* ---------- Interfaces ---------- */ +- +-/* There are 3 levels of interfaces: +- 1) Dictionary Interface +- 2) Buffer Interface +- 3) One Call Interface +- You can select any of these interfaces, but don't mix functions from different +- groups for same object. */ +- +- +-/* There are two variants to allocate state for Dictionary Interface: +- 1) LzmaDec_Allocate / LzmaDec_Free +- 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs +- You can use variant 2, if you set dictionary buffer manually. +- For Buffer Interface you must always use variant 1. +- +-LzmaDec_Allocate* can return: +- SZ_OK +- SZ_ERROR_MEM - Memory allocation error +- SZ_ERROR_UNSUPPORTED - Unsupported properties +-*/ +- +-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); +-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); +- +-SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); +-void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); +- +-/* ---------- Dictionary Interface ---------- */ +- +-/* You can use it, if you want to eliminate the overhead for data copying from +- dictionary to some other external buffer. +- You must work with CLzmaDec variables directly in this interface. +- +- STEPS: +- LzmaDec_Constr() +- LzmaDec_Allocate() +- for (each new stream) +- { +- LzmaDec_Init() +- while (it needs more decompression) +- { +- LzmaDec_DecodeToDic() +- use data from CLzmaDec::dic and update CLzmaDec::dicPos +- } +- } +- LzmaDec_Free() +-*/ +- +-/* LzmaDec_DecodeToDic +- +- The decoding to internal dictionary buffer (CLzmaDec::dic). +- You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! +- +-finishMode: +- It has meaning only if the decoding reaches output limit (dicLimit). +- LZMA_FINISH_ANY - Decode just dicLimit bytes. +- LZMA_FINISH_END - Stream must be finished after dicLimit. +- +-Returns: +- SZ_OK +- status: +- LZMA_STATUS_FINISHED_WITH_MARK +- LZMA_STATUS_NOT_FINISHED +- LZMA_STATUS_NEEDS_MORE_INPUT +- LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK +- SZ_ERROR_DATA - Data error +-*/ +- +-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, +- const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); +- +- +-/* ---------- Buffer Interface ---------- */ +- +-/* It's zlib-like interface. +- See LzmaDec_DecodeToDic description for information about STEPS and return results, +- but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need +- to work with CLzmaDec variables manually. +- +-finishMode: +- It has meaning only if the decoding reaches output limit (*destLen). +- LZMA_FINISH_ANY - Decode just destLen bytes. +- LZMA_FINISH_END - Stream must be finished after (*destLen). +-*/ +- +-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, +- const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); +- +- + /* ---------- One Call Interface ---------- */ + + /* LzmaDecode +--- a/lib/lzma/LzmaDec.c ++++ b/lib/lzma/LzmaDec.c +@@ -682,7 +682,7 @@ static void LzmaDec_InitRc(CLzmaDec *p, + p->needFlush = 0; + } + +-void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) ++static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) + { + p->needFlush = 1; + p->remainLen = 0; +@@ -698,7 +698,7 @@ void LzmaDec_InitDicAndState(CLzmaDec *p + p->needInitState = 1; + } + +-void LzmaDec_Init(CLzmaDec *p) ++static void LzmaDec_Init(CLzmaDec *p) + { + p->dicPos = 0; + LzmaDec_InitDicAndState(p, True, True); +@@ -716,7 +716,7 @@ static void LzmaDec_InitStateReal(CLzmaD + p->needInitState = 0; + } + +-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, ++static SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, + ELzmaFinishMode finishMode, ELzmaStatus *status) + { + SizeT inSize = *srcLen; +@@ -837,65 +837,13 @@ SRes LzmaDec_DecodeToDic(CLzmaDec *p, Si + return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; + } + +-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) +-{ +- SizeT outSize = *destLen; +- SizeT inSize = *srcLen; +- *srcLen = *destLen = 0; +- for (;;) +- { +- SizeT inSizeCur = inSize, outSizeCur, dicPos; +- ELzmaFinishMode curFinishMode; +- SRes res; +- if (p->dicPos == p->dicBufSize) +- p->dicPos = 0; +- dicPos = p->dicPos; +- if (outSize > p->dicBufSize - dicPos) +- { +- outSizeCur = p->dicBufSize; +- curFinishMode = LZMA_FINISH_ANY; +- } +- else +- { +- outSizeCur = dicPos + outSize; +- curFinishMode = finishMode; +- } +- +- res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); +- src += inSizeCur; +- inSize -= inSizeCur; +- *srcLen += inSizeCur; +- outSizeCur = p->dicPos - dicPos; +- memcpy(dest, p->dic + dicPos, outSizeCur); +- dest += outSizeCur; +- outSize -= outSizeCur; +- *destLen += outSizeCur; +- if (res != 0) +- return res; +- if (outSizeCur == 0 || outSize == 0) +- return SZ_OK; +- } +-} +- +-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) ++static void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) + { + alloc->Free(alloc, p->probs); + p->probs = 0; + } + +-static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) +-{ +- alloc->Free(alloc, p->dic); +- p->dic = 0; +-} +- +-void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) +-{ +- LzmaDec_FreeProbs(p, alloc); +- LzmaDec_FreeDict(p, alloc); +-} +- +-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) ++static SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) + { + UInt32 dicSize; + Byte d; +@@ -935,7 +883,7 @@ static SRes LzmaDec_AllocateProbs2(CLzma + return SZ_OK; + } + +-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++static SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) + { + CLzmaProps propNew; + RINOK(LzmaProps_Decode(&propNew, props, propsSize)); +@@ -943,28 +891,6 @@ SRes LzmaDec_AllocateProbs(CLzmaDec *p, + p->prop = propNew; + return SZ_OK; + } +- +-SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) +-{ +- CLzmaProps propNew; +- SizeT dicBufSize; +- RINOK(LzmaProps_Decode(&propNew, props, propsSize)); +- RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); +- dicBufSize = propNew.dicSize; +- if (p->dic == 0 || dicBufSize != p->dicBufSize) +- { +- LzmaDec_FreeDict(p, alloc); +- p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); +- if (p->dic == 0) +- { +- LzmaDec_FreeProbs(p, alloc); +- return SZ_ERROR_MEM; +- } +- } +- p->dicBufSize = dicBufSize; +- p->prop = propNew; +- return SZ_OK; +-} + + SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, + const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, +--- a/include/linux/lzma/LzmaEnc.h ++++ b/include/linux/lzma/LzmaEnc.h +@@ -31,9 +31,6 @@ typedef struct _CLzmaEncProps + } CLzmaEncProps; + + void LzmaEncProps_Init(CLzmaEncProps *p); +-void LzmaEncProps_Normalize(CLzmaEncProps *p); +-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2); +- + + /* ---------- CLzmaEncHandle Interface ---------- */ + +@@ -53,26 +50,9 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc * + void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); + SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); + SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); +-SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); + SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, + int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); + +-/* ---------- One Call Interface ---------- */ +- +-/* LzmaEncode +-Return code: +- SZ_OK - OK +- SZ_ERROR_MEM - Memory allocation error +- SZ_ERROR_PARAM - Incorrect paramater +- SZ_ERROR_OUTPUT_EOF - output buffer overflow +- SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) +-*/ +- +-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, +- const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); +- + #ifdef __cplusplus + } + #endif +--- a/lib/lzma/LzmaEnc.c ++++ b/lib/lzma/LzmaEnc.c +@@ -53,7 +53,7 @@ void LzmaEncProps_Init(CLzmaEncProps *p) + p->writeEndMark = 0; + } + +-void LzmaEncProps_Normalize(CLzmaEncProps *p) ++static void LzmaEncProps_Normalize(CLzmaEncProps *p) + { + int level = p->level; + if (level < 0) level = 5; +@@ -76,7 +76,7 @@ void LzmaEncProps_Normalize(CLzmaEncProp + #endif + } + +-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) ++static UInt32 __maybe_unused LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) + { + CLzmaEncProps props = *props2; + LzmaEncProps_Normalize(&props); +@@ -93,7 +93,7 @@ UInt32 LzmaEncProps_GetDictSize(const CL + + #define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } + +-UInt32 GetPosSlot1(UInt32 pos) ++static UInt32 GetPosSlot1(UInt32 pos) + { + UInt32 res; + BSR2_RET(pos, res); +@@ -107,7 +107,7 @@ UInt32 GetPosSlot1(UInt32 pos) + #define kNumLogBits (9 + (int)sizeof(size_t) / 2) + #define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) + +-void LzmaEnc_FastPosInit(Byte *g_FastPos) ++static void LzmaEnc_FastPosInit(Byte *g_FastPos) + { + int c = 2, slotFast; + g_FastPos[0] = 0; +@@ -339,58 +339,6 @@ typedef struct + CSaveState saveState; + } CLzmaEnc; + +-void LzmaEnc_SaveState(CLzmaEncHandle pp) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- CSaveState *dest = &p->saveState; +- int i; +- dest->lenEnc = p->lenEnc; +- dest->repLenEnc = p->repLenEnc; +- dest->state = p->state; +- +- for (i = 0; i < kNumStates; i++) +- { +- memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); +- memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); +- } +- for (i = 0; i < kNumLenToPosStates; i++) +- memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); +- memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); +- memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); +- memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); +- memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); +- memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); +- memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); +- memcpy(dest->reps, p->reps, sizeof(p->reps)); +- memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb)); +-} +- +-void LzmaEnc_RestoreState(CLzmaEncHandle pp) +-{ +- CLzmaEnc *dest = (CLzmaEnc *)pp; +- const CSaveState *p = &dest->saveState; +- int i; +- dest->lenEnc = p->lenEnc; +- dest->repLenEnc = p->repLenEnc; +- dest->state = p->state; +- +- for (i = 0; i < kNumStates; i++) +- { +- memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); +- memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); +- } +- for (i = 0; i < kNumLenToPosStates; i++) +- memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); +- memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); +- memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); +- memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); +- memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); +- memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); +- memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); +- memcpy(dest->reps, p->reps, sizeof(p->reps)); +- memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb)); +-} +- + SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -600,7 +548,7 @@ static void LitEnc_EncodeMatched(CRangeE + while (symbol < 0x10000); + } + +-void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) ++static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) + { + UInt32 i; + for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) +@@ -1676,7 +1624,7 @@ static void FillDistancesPrices(CLzmaEnc + p->matchPriceCount = 0; + } + +-void LzmaEnc_Construct(CLzmaEnc *p) ++static void LzmaEnc_Construct(CLzmaEnc *p) + { + RangeEnc_Construct(&p->rc); + MatchFinder_Construct(&p->matchFinderBase); +@@ -1709,7 +1657,7 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc * + return p; + } + +-void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) ++static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) + { + alloc->Free(alloc, p->litProbs); + alloc->Free(alloc, p->saveState.litProbs); +@@ -1717,7 +1665,7 @@ void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAl + p->saveState.litProbs = 0; + } + +-void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) ++static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) + { + #ifndef _7ZIP_ST + MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); +@@ -1947,7 +1895,7 @@ static SRes LzmaEnc_Alloc(CLzmaEnc *p, U + return SZ_OK; + } + +-void LzmaEnc_Init(CLzmaEnc *p) ++static void LzmaEnc_Init(CLzmaEnc *p) + { + UInt32 i; + p->state = 0; +@@ -2005,7 +1953,7 @@ void LzmaEnc_Init(CLzmaEnc *p) + p->lpMask = (1 << p->lp) - 1; + } + +-void LzmaEnc_InitPrices(CLzmaEnc *p) ++static void LzmaEnc_InitPrices(CLzmaEnc *p) + { + if (!p->fastMode) + { +@@ -2037,26 +1985,6 @@ static SRes LzmaEnc_AllocAndInit(CLzmaEn + return SZ_OK; + } + +-static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- p->matchFinderBase.stream = inStream; +- p->needInit = 1; +- p->rc.outStream = outStream; +- return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig); +-} +- +-SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, +- ISeqInStream *inStream, UInt32 keepWindowSize, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- p->matchFinderBase.stream = inStream; +- p->needInit = 1; +- return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); +-} +- + static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) + { + p->matchFinderBase.directInput = 1; +@@ -2064,7 +1992,7 @@ static void LzmaEnc_SetInputBuf(CLzmaEnc + p->matchFinderBase.directInputRem = srcLen; + } + +-SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, ++static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, + UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2074,7 +2002,7 @@ SRes LzmaEnc_MemPrepare(CLzmaEncHandle p + return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); + } + +-void LzmaEnc_Finish(CLzmaEncHandle pp) ++static void LzmaEnc_Finish(CLzmaEncHandle pp) + { + #ifndef _7ZIP_ST + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2107,53 +2035,6 @@ static size_t MyWrite(void *pp, const vo + return size; + } + +- +-UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp) +-{ +- const CLzmaEnc *p = (CLzmaEnc *)pp; +- return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); +-} +- +-const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp) +-{ +- const CLzmaEnc *p = (CLzmaEnc *)pp; +- return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; +-} +- +-SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, +- Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- UInt64 nowPos64; +- SRes res; +- CSeqOutStreamBuf outStream; +- +- outStream.funcTable.Write = MyWrite; +- outStream.data = dest; +- outStream.rem = *destLen; +- outStream.overflow = False; +- +- p->writeEndMark = False; +- p->finished = False; +- p->result = SZ_OK; +- +- if (reInit) +- LzmaEnc_Init(p); +- LzmaEnc_InitPrices(p); +- nowPos64 = p->nowPos64; +- RangeEnc_Init(&p->rc); +- p->rc.outStream = &outStream.funcTable; +- +- res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize); +- +- *unpackSize = (UInt32)(p->nowPos64 - nowPos64); +- *destLen -= outStream.rem; +- if (outStream.overflow) +- return SZ_ERROR_OUTPUT_EOF; +- +- return res; +-} +- + static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) + { + SRes res = SZ_OK; +@@ -2184,13 +2065,6 @@ static SRes LzmaEnc_Encode2(CLzmaEnc *p, + return res; + } + +-SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig)); +- return LzmaEnc_Encode2((CLzmaEnc *)pp, progress); +-} +- + SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2247,25 +2121,3 @@ SRes LzmaEnc_MemEncode(CLzmaEncHandle pp + return SZ_ERROR_OUTPUT_EOF; + return res; + } +- +-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, +- const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc); +- SRes res; +- if (p == 0) +- return SZ_ERROR_MEM; +- +- res = LzmaEnc_SetProps(p, props); +- if (res == SZ_OK) +- { +- res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize); +- if (res == SZ_OK) +- res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen, +- writeEndMark, progress, alloc, allocBig); +- } +- +- LzmaEnc_Destroy(p, alloc, allocBig); +- return res; +-} +--- a/include/linux/lzma/LzFind.h ++++ b/include/linux/lzma/LzFind.h +@@ -55,11 +55,6 @@ typedef struct _CMatchFinder + + #define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) + +-int MatchFinder_NeedMove(CMatchFinder *p); +-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p); +-void MatchFinder_MoveBlock(CMatchFinder *p); +-void MatchFinder_ReadIfRequired(CMatchFinder *p); +- + void MatchFinder_Construct(CMatchFinder *p); + + /* Conditions: +@@ -70,12 +65,6 @@ int MatchFinder_Create(CMatchFinder *p, + UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, + ISzAlloc *alloc); + void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); +-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems); +-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue); +- +-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, +- UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, +- UInt32 *distances, UInt32 maxLen); + + /* + Conditions: +@@ -102,12 +91,6 @@ typedef struct _IMatchFinder + + void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); + +-void MatchFinder_Init(CMatchFinder *p); +-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); +-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); +-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); +-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); +- + #ifdef __cplusplus + } + #endif +--- a/lib/lzma/LzFind.c ++++ b/lib/lzma/LzFind.c +@@ -14,9 +14,15 @@ + + #define kStartMaxLen 3 + ++#if 0 ++#define DIRECT_INPUT p->directInput ++#else ++#define DIRECT_INPUT 1 ++#endif ++ + static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) + { +- if (!p->directInput) ++ if (!DIRECT_INPUT) + { + alloc->Free(alloc, p->bufferBase); + p->bufferBase = 0; +@@ -28,7 +34,7 @@ static void LzInWindow_Free(CMatchFinder + static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) + { + UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; +- if (p->directInput) ++ if (DIRECT_INPUT) + { + p->blockSize = blockSize; + return 1; +@@ -42,12 +48,12 @@ static int LzInWindow_Create(CMatchFinde + return (p->bufferBase != 0); + } + +-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } +-Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } ++static Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } ++static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } + +-UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } ++static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } + +-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) ++static void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) + { + p->posLimit -= subValue; + p->pos -= subValue; +@@ -58,7 +64,7 @@ static void MatchFinder_ReadBlock(CMatch + { + if (p->streamEndWasReached || p->result != SZ_OK) + return; +- if (p->directInput) ++ if (DIRECT_INPUT) + { + UInt32 curSize = 0xFFFFFFFF - p->streamPos; + if (curSize > p->directInputRem) +@@ -89,7 +95,7 @@ static void MatchFinder_ReadBlock(CMatch + } + } + +-void MatchFinder_MoveBlock(CMatchFinder *p) ++static void MatchFinder_MoveBlock(CMatchFinder *p) + { + memmove(p->bufferBase, + p->buffer - p->keepSizeBefore, +@@ -97,22 +103,14 @@ void MatchFinder_MoveBlock(CMatchFinder + p->buffer = p->bufferBase + p->keepSizeBefore; + } + +-int MatchFinder_NeedMove(CMatchFinder *p) ++static int MatchFinder_NeedMove(CMatchFinder *p) + { +- if (p->directInput) ++ if (DIRECT_INPUT) + return 0; + /* if (p->streamEndWasReached) return 0; */ + return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); + } + +-void MatchFinder_ReadIfRequired(CMatchFinder *p) +-{ +- if (p->streamEndWasReached) +- return; +- if (p->keepSizeAfter >= p->streamPos - p->pos) +- MatchFinder_ReadBlock(p); +-} +- + static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) + { + if (MatchFinder_NeedMove(p)) +@@ -268,7 +266,7 @@ static void MatchFinder_SetLimits(CMatch + p->posLimit = p->pos + limit; + } + +-void MatchFinder_Init(CMatchFinder *p) ++static void MatchFinder_Init(CMatchFinder *p) + { + UInt32 i; + for (i = 0; i < p->hashSizeSum; i++) +@@ -287,7 +285,7 @@ static UInt32 MatchFinder_GetSubValue(CM + return (p->pos - p->historySize - 1) & kNormalizeMask; + } + +-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) ++static void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) + { + UInt32 i; + for (i = 0; i < numItems; i++) +@@ -319,38 +317,7 @@ static void MatchFinder_CheckLimits(CMat + MatchFinder_SetLimits(p); + } + +-static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, +- UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, +- UInt32 *distances, UInt32 maxLen) +-{ +- son[_cyclicBufferPos] = curMatch; +- for (;;) +- { +- UInt32 delta = pos - curMatch; +- if (cutValue-- == 0 || delta >= _cyclicBufferSize) +- return distances; +- { +- const Byte *pb = cur - delta; +- curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)]; +- if (pb[maxLen] == cur[maxLen] && *pb == *cur) +- { +- UInt32 len = 0; +- while (++len != lenLimit) +- if (pb[len] != cur[len]) +- break; +- if (maxLen < len) +- { +- *distances++ = maxLen = len; +- *distances++ = delta - 1; +- if (len == lenLimit) +- return distances; +- } +- } +- } +- } +-} +- +-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++static UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, + UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, + UInt32 *distances, UInt32 maxLen) + { +@@ -460,10 +427,10 @@ static void SkipMatchesSpec(UInt32 lenLi + p->buffer++; \ + if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); + +-#define MOVE_POS_RET MOVE_POS return offset; +- + static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } + ++#define MOVE_POS_RET MatchFinder_MovePos(p); return offset; ++ + #define GET_MATCHES_HEADER2(minLen, ret_op) \ + UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ + lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ +@@ -479,62 +446,7 @@ static void MatchFinder_MovePos(CMatchFi + distances + offset, maxLen) - distances); MOVE_POS_RET; + + #define SKIP_FOOTER \ +- SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS; +- +-static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(2) +- HASH2_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = 0; +- GET_MATCHES_FOOTER(offset, 1) +-} +- +-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = 0; +- GET_MATCHES_FOOTER(offset, 2) +-} +- +-static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 hash2Value, delta2, maxLen, offset; +- GET_MATCHES_HEADER(3) +- +- HASH3_CALC; +- +- delta2 = p->pos - p->hash[hash2Value]; +- curMatch = p->hash[kFix3HashSize + hashValue]; +- +- p->hash[hash2Value] = +- p->hash[kFix3HashSize + hashValue] = p->pos; +- +- +- maxLen = 2; +- offset = 0; +- if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) +- { +- for (; maxLen != lenLimit; maxLen++) +- if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) +- break; +- distances[0] = maxLen; +- distances[1] = delta2 - 1; +- offset = 2; +- if (maxLen == lenLimit) +- { +- SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); +- MOVE_POS_RET; +- } +- } +- GET_MATCHES_FOOTER(offset, maxLen) +-} ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MatchFinder_MovePos(p); + + static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) + { +@@ -583,108 +495,6 @@ static UInt32 Bt4_MatchFinder_GetMatches + GET_MATCHES_FOOTER(offset, maxLen) + } + +-static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; +- GET_MATCHES_HEADER(4) +- +- HASH4_CALC; +- +- delta2 = p->pos - p->hash[ hash2Value]; +- delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; +- curMatch = p->hash[kFix4HashSize + hashValue]; +- +- p->hash[ hash2Value] = +- p->hash[kFix3HashSize + hash3Value] = +- p->hash[kFix4HashSize + hashValue] = p->pos; +- +- maxLen = 1; +- offset = 0; +- if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) +- { +- distances[0] = maxLen = 2; +- distances[1] = delta2 - 1; +- offset = 2; +- } +- if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) +- { +- maxLen = 3; +- distances[offset + 1] = delta3 - 1; +- offset += 2; +- delta2 = delta3; +- } +- if (offset != 0) +- { +- for (; maxLen != lenLimit; maxLen++) +- if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) +- break; +- distances[offset - 2] = maxLen; +- if (maxLen == lenLimit) +- { +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS_RET; +- } +- } +- if (maxLen < 3) +- maxLen = 3; +- offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), +- distances + offset, maxLen) - (distances)); +- MOVE_POS_RET +-} +- +-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), +- distances, 2) - (distances)); +- MOVE_POS_RET +-} +- +-static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(2) +- HASH2_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- +-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- +-static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- UInt32 hash2Value; +- SKIP_HEADER(3) +- HASH3_CALC; +- curMatch = p->hash[kFix3HashSize + hashValue]; +- p->hash[hash2Value] = +- p->hash[kFix3HashSize + hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- + static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) + { + do +@@ -701,61 +511,12 @@ static void Bt4_MatchFinder_Skip(CMatchF + while (--num != 0); + } + +-static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- UInt32 hash2Value, hash3Value; +- SKIP_HEADER(4) +- HASH4_CALC; +- curMatch = p->hash[kFix4HashSize + hashValue]; +- p->hash[ hash2Value] = +- p->hash[kFix3HashSize + hash3Value] = +- p->hash[kFix4HashSize + hashValue] = p->pos; +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS +- } +- while (--num != 0); +-} +- +-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS +- } +- while (--num != 0); +-} +- + void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) + { + vTable->Init = (Mf_Init_Func)MatchFinder_Init; + vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; + vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; + vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; +- if (!p->btMode) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip; +- } +- else if (p->numHashBytes == 2) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip; +- } +- else if (p->numHashBytes == 3) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip; +- } +- else +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; +- } ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; + } diff --git a/target/linux/generic/patches-3.18/532-jffs2_eofdetect.patch b/target/linux/generic/patches-3.18/532-jffs2_eofdetect.patch new file mode 100644 index 0000000..9cbe183 --- /dev/null +++ b/target/linux/generic/patches-3.18/532-jffs2_eofdetect.patch @@ -0,0 +1,56 @@ +--- a/fs/jffs2/build.c ++++ b/fs/jffs2/build.c +@@ -114,6 +114,16 @@ static int jffs2_build_filesystem(struct + dbg_fsbuild("scanned flash completely\n"); + jffs2_dbg_dump_block_lists_nolock(c); + ++ if (c->flags & (1 << 7)) { ++ printk("%s(): unlocking the mtd device... ", __func__); ++ mtd_unlock(c->mtd, 0, c->mtd->size); ++ printk("done.\n"); ++ ++ printk("%s(): erasing all blocks after the end marker... ", __func__); ++ jffs2_erase_pending_blocks(c, -1); ++ printk("done.\n"); ++ } ++ + dbg_fsbuild("pass 1 starting\n"); + c->flags |= JFFS2_SB_FLAG_BUILDING; + /* Now scan the directory tree, increasing nlink according to every dirent found. */ +--- a/fs/jffs2/scan.c ++++ b/fs/jffs2/scan.c +@@ -148,8 +148,14 @@ int jffs2_scan_medium(struct jffs2_sb_in + /* reset summary info for next eraseblock scan */ + jffs2_sum_reset_collected(s); + +- ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), +- buf_size, s); ++ if (c->flags & (1 << 7)) { ++ if (mtd_block_isbad(c->mtd, jeb->offset)) ++ ret = BLK_STATE_BADBLOCK; ++ else ++ ret = BLK_STATE_ALLFF; ++ } else ++ ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), ++ buf_size, s); + + if (ret < 0) + goto out; +@@ -561,6 +567,17 @@ full_scan: + return err; + } + ++ if ((buf[0] == 0xde) && ++ (buf[1] == 0xad) && ++ (buf[2] == 0xc0) && ++ (buf[3] == 0xde)) { ++ /* end of filesystem. erase everything after this point */ ++ printk("%s(): End of filesystem marker found at 0x%x\n", __func__, jeb->offset); ++ c->flags |= (1 << 7); ++ ++ return BLK_STATE_ALLFF; ++ } ++ + /* We temporarily use 'ofs' as a pointer into the buffer/jeb */ + ofs = 0; + max_ofs = EMPTY_SCAN_SIZE(c->sector_size); diff --git a/target/linux/generic/patches-3.18/540-crypto-xz-decompression-support.patch b/target/linux/generic/patches-3.18/540-crypto-xz-decompression-support.patch new file mode 100644 index 0000000..00b0b7c --- /dev/null +++ b/target/linux/generic/patches-3.18/540-crypto-xz-decompression-support.patch @@ -0,0 +1,146 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -1437,6 +1437,13 @@ config CRYPTO_LZ4HC + help + This is the LZ4 high compression mode algorithm. + ++config CRYPTO_XZ ++ tristate "XZ compression algorithm" ++ select CRYPTO_ALGAPI ++ select XZ_DEC ++ help ++ This is the XZ algorithm. Only decompression is supported for now. ++ + comment "Random Number Generation" + + config CRYPTO_ANSI_CPRNG +--- a/crypto/Makefile ++++ b/crypto/Makefile +@@ -89,6 +89,7 @@ obj-$(CONFIG_CRYPTO_AUTHENC) += authenc. + obj-$(CONFIG_CRYPTO_LZO) += lzo.o + obj-$(CONFIG_CRYPTO_LZ4) += lz4.o + obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o ++obj-$(CONFIG_CRYPTO_XZ) += xz.o + obj-$(CONFIG_CRYPTO_842) += 842.o + obj-$(CONFIG_CRYPTO_RNG2) += rng.o + obj-$(CONFIG_CRYPTO_RNG2) += krng.o +--- /dev/null ++++ b/crypto/xz.c +@@ -0,0 +1,117 @@ ++/* ++ * Cryptographic API. ++ * ++ * XZ decompression support. ++ * ++ * Copyright (c) 2012 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct xz_comp_ctx { ++ struct xz_dec *decomp_state; ++ struct xz_buf decomp_buf; ++}; ++ ++static int crypto_xz_decomp_init(struct xz_comp_ctx *ctx) ++{ ++ ctx->decomp_state = xz_dec_init(XZ_SINGLE, 0); ++ if (!ctx->decomp_state) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static void crypto_xz_decomp_exit(struct xz_comp_ctx *ctx) ++{ ++ xz_dec_end(ctx->decomp_state); ++} ++ ++static int crypto_xz_init(struct crypto_tfm *tfm) ++{ ++ struct xz_comp_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ return crypto_xz_decomp_init(ctx); ++} ++ ++static void crypto_xz_exit(struct crypto_tfm *tfm) ++{ ++ struct xz_comp_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ crypto_xz_decomp_exit(ctx); ++} ++ ++static int crypto_xz_compress(struct crypto_tfm *tfm, const u8 *src, ++ unsigned int slen, u8 *dst, unsigned int *dlen) ++{ ++ return -EOPNOTSUPP; ++} ++ ++static int crypto_xz_decompress(struct crypto_tfm *tfm, const u8 *src, ++ unsigned int slen, u8 *dst, unsigned int *dlen) ++{ ++ struct xz_comp_ctx *dctx = crypto_tfm_ctx(tfm); ++ struct xz_buf *xz_buf = &dctx->decomp_buf; ++ int ret; ++ ++ memset(xz_buf, '\0', sizeof(struct xz_buf)); ++ ++ xz_buf->in = (u8 *) src; ++ xz_buf->in_pos = 0; ++ xz_buf->in_size = slen; ++ xz_buf->out = (u8 *) dst; ++ xz_buf->out_pos = 0; ++ xz_buf->out_size = *dlen; ++ ++ ret = xz_dec_run(dctx->decomp_state, xz_buf); ++ if (ret != XZ_STREAM_END) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ *dlen = xz_buf->out_pos; ++ ret = 0; ++ ++out: ++ return ret; ++} ++ ++static struct crypto_alg crypto_xz_alg = { ++ .cra_name = "xz", ++ .cra_flags = CRYPTO_ALG_TYPE_COMPRESS, ++ .cra_ctxsize = sizeof(struct xz_comp_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_list = LIST_HEAD_INIT(crypto_xz_alg.cra_list), ++ .cra_init = crypto_xz_init, ++ .cra_exit = crypto_xz_exit, ++ .cra_u = { .compress = { ++ .coa_compress = crypto_xz_compress, ++ .coa_decompress = crypto_xz_decompress } } ++}; ++ ++static int __init crypto_xz_mod_init(void) ++{ ++ return crypto_register_alg(&crypto_xz_alg); ++} ++ ++static void __exit crypto_xz_mod_exit(void) ++{ ++ crypto_unregister_alg(&crypto_xz_alg); ++} ++ ++module_init(crypto_xz_mod_init); ++module_exit(crypto_xz_mod_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Crypto XZ decompression support"); ++MODULE_AUTHOR("Gabor Juhos "); diff --git a/target/linux/generic/patches-3.18/541-ubifs-xz-decompression-support.patch b/target/linux/generic/patches-3.18/541-ubifs-xz-decompression-support.patch new file mode 100644 index 0000000..f85689c --- /dev/null +++ b/target/linux/generic/patches-3.18/541-ubifs-xz-decompression-support.patch @@ -0,0 +1,92 @@ +--- a/fs/ubifs/Kconfig ++++ b/fs/ubifs/Kconfig +@@ -5,8 +5,10 @@ config UBIFS_FS + select CRYPTO if UBIFS_FS_ADVANCED_COMPR + select CRYPTO if UBIFS_FS_LZO + select CRYPTO if UBIFS_FS_ZLIB ++ select CRYPTO if UBIFS_FS_XZ + select CRYPTO_LZO if UBIFS_FS_LZO + select CRYPTO_DEFLATE if UBIFS_FS_ZLIB ++ select CRYPTO_XZ if UBIFS_FS_XZ + depends on MTD_UBI + help + UBIFS is a file system for flash devices which works on top of UBI. +@@ -35,3 +37,12 @@ config UBIFS_FS_ZLIB + default y + help + Zlib compresses better than LZO but it is slower. Say 'Y' if unsure. ++ ++config UBIFS_FS_XZ ++ bool "XZ decompression support" if UBIFS_FS_ADVANCED_COMPR ++ depends on UBIFS_FS ++ default y ++ help ++ XZ compresses better the ZLIB but it is slower.. ++ Say 'Y' if unsure. ++ +--- a/fs/ubifs/compress.c ++++ b/fs/ubifs/compress.c +@@ -71,6 +71,24 @@ static struct ubifs_compressor zlib_comp + }; + #endif + ++#ifdef CONFIG_UBIFS_FS_XZ ++static DEFINE_MUTEX(xz_enc_mutex); ++static DEFINE_MUTEX(xz_dec_mutex); ++ ++static struct ubifs_compressor xz_compr = { ++ .compr_type = UBIFS_COMPR_XZ, ++ .comp_mutex = &xz_enc_mutex, ++ .decomp_mutex = &xz_dec_mutex, ++ .name = "xz", ++ .capi_name = "xz", ++}; ++#else ++static struct ubifs_compressor xz_compr = { ++ .compr_type = UBIFS_COMPR_XZ, ++ .name = "xz", ++}; ++#endif ++ + /* All UBIFS compressors */ + struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT]; + +@@ -232,9 +250,15 @@ int __init ubifs_compressors_init(void) + if (err) + goto out_lzo; + ++ err = compr_init(&xz_compr); ++ if (err) ++ goto out_zlib; ++ + ubifs_compressors[UBIFS_COMPR_NONE] = &none_compr; + return 0; + ++out_zlib: ++ compr_exit(&zlib_compr); + out_lzo: + compr_exit(&lzo_compr); + return err; +@@ -247,4 +271,5 @@ void ubifs_compressors_exit(void) + { + compr_exit(&lzo_compr); + compr_exit(&zlib_compr); ++ compr_exit(&xz_compr); + } +--- a/fs/ubifs/ubifs-media.h ++++ b/fs/ubifs/ubifs-media.h +@@ -332,12 +332,14 @@ enum { + * UBIFS_COMPR_NONE: no compression + * UBIFS_COMPR_LZO: LZO compression + * UBIFS_COMPR_ZLIB: ZLIB compression ++ * UBIFS_COMPR_XZ: XZ compression + * UBIFS_COMPR_TYPES_CNT: count of supported compression types + */ + enum { + UBIFS_COMPR_NONE, + UBIFS_COMPR_LZO, + UBIFS_COMPR_ZLIB, ++ UBIFS_COMPR_XZ, + UBIFS_COMPR_TYPES_CNT, + }; + diff --git a/target/linux/generic/patches-3.18/550-ubifs-symlink-xattr-support.patch b/target/linux/generic/patches-3.18/550-ubifs-symlink-xattr-support.patch new file mode 100644 index 0000000..d3f2ccc --- /dev/null +++ b/target/linux/generic/patches-3.18/550-ubifs-symlink-xattr-support.patch @@ -0,0 +1,55 @@ +--- a/fs/ubifs/file.c ++++ b/fs/ubifs/file.c +@@ -1573,6 +1573,10 @@ const struct inode_operations ubifs_syml + .follow_link = ubifs_follow_link, + .setattr = ubifs_setattr, + .getattr = ubifs_getattr, ++ .setxattr = ubifs_setxattr, ++ .getxattr = ubifs_getxattr, ++ .listxattr = ubifs_listxattr, ++ .removexattr = ubifs_removexattr, + }; + + const struct file_operations ubifs_file_operations = { +--- a/fs/ubifs/journal.c ++++ b/fs/ubifs/journal.c +@@ -572,6 +572,13 @@ int ubifs_jnl_update(struct ubifs_info * + aligned_dlen = ALIGN(dlen, 8); + aligned_ilen = ALIGN(ilen, 8); + len = aligned_dlen + aligned_ilen + UBIFS_INO_NODE_SZ; ++ if (xent) { ++ /* ++ * Make sure to account for host_ui->data_len in ++ * length calculation in case there is extended attribute. ++ */ ++ len += host_ui->data_len; ++ } + dent = kmalloc(len, GFP_NOFS); + if (!dent) + return -ENOMEM; +@@ -648,7 +655,8 @@ int ubifs_jnl_update(struct ubifs_info * + + ino_key_init(c, &ino_key, dir->i_ino); + ino_offs += aligned_ilen; +- err = ubifs_tnc_add(c, &ino_key, lnum, ino_offs, UBIFS_INO_NODE_SZ); ++ err = ubifs_tnc_add(c, &ino_key, lnum, ino_offs, ++ UBIFS_INO_NODE_SZ + host_ui->data_len); + if (err) + goto out_ro; + +--- a/fs/ubifs/xattr.c ++++ b/fs/ubifs/xattr.c +@@ -209,12 +209,12 @@ static int change_xattr(struct ubifs_inf + goto out_free; + } + inode->i_size = ui->ui_size = size; +- ui->data_len = size; + + mutex_lock(&host_ui->ui_mutex); + host->i_ctime = ubifs_current_time(host); + host_ui->xattr_size -= CALC_XATTR_BYTES(ui->data_len); + host_ui->xattr_size += CALC_XATTR_BYTES(size); ++ ui->data_len = size; + + /* + * It is important to write the host inode after the xattr inode diff --git a/target/linux/generic/patches-3.18/551-ubifs-fix-default-compression-selection.patch b/target/linux/generic/patches-3.18/551-ubifs-fix-default-compression-selection.patch new file mode 100644 index 0000000..1b0f307 --- /dev/null +++ b/target/linux/generic/patches-3.18/551-ubifs-fix-default-compression-selection.patch @@ -0,0 +1,29 @@ +--- a/fs/ubifs/sb.c ++++ b/fs/ubifs/sb.c +@@ -63,6 +63,17 @@ + /* Default time granularity in nanoseconds */ + #define DEFAULT_TIME_GRAN 1000000000 + ++static int get_default_compressor(void) ++{ ++ if (ubifs_compr_present(UBIFS_COMPR_LZO)) ++ return UBIFS_COMPR_LZO; ++ ++ if (ubifs_compr_present(UBIFS_COMPR_ZLIB)) ++ return UBIFS_COMPR_ZLIB; ++ ++ return UBIFS_COMPR_NONE; ++} ++ + /** + * create_default_filesystem - format empty UBI volume. + * @c: UBIFS file-system description object +@@ -183,7 +194,7 @@ static int create_default_filesystem(str + if (c->mount_opts.override_compr) + sup->default_compr = cpu_to_le16(c->mount_opts.compr_type); + else +- sup->default_compr = cpu_to_le16(UBIFS_COMPR_LZO); ++ sup->default_compr = cpu_to_le16(get_default_compressor()); + + generate_random_uuid(sup->uuid); + diff --git a/target/linux/generic/patches-3.18/600-netfilter_conntrack_flush.patch b/target/linux/generic/patches-3.18/600-netfilter_conntrack_flush.patch new file mode 100644 index 0000000..bc6ed3e --- /dev/null +++ b/target/linux/generic/patches-3.18/600-netfilter_conntrack_flush.patch @@ -0,0 +1,86 @@ +--- a/net/netfilter/nf_conntrack_standalone.c ++++ b/net/netfilter/nf_conntrack_standalone.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #ifdef CONFIG_SYSCTL + #include +@@ -262,10 +263,66 @@ static int ct_open(struct inode *inode, + sizeof(struct ct_iter_state)); + } + ++struct kill_request { ++ u16 family; ++ union nf_inet_addr addr; ++}; ++ ++static int kill_matching(struct nf_conn *i, void *data) ++{ ++ struct kill_request *kr = data; ++ struct nf_conntrack_tuple *t1 = &i->tuplehash[IP_CT_DIR_ORIGINAL].tuple; ++ struct nf_conntrack_tuple *t2 = &i->tuplehash[IP_CT_DIR_REPLY].tuple; ++ ++ if (!kr->family) ++ return 1; ++ ++ if (t1->src.l3num != kr->family) ++ return 0; ++ ++ return (nf_inet_addr_cmp(&kr->addr, &t1->src.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t1->dst.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t2->src.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t2->dst.u3)); ++} ++ ++static ssize_t ct_file_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *seq = file->private_data; ++ struct net *net = seq_file_net(seq); ++ struct kill_request kr = { }; ++ char req[INET6_ADDRSTRLEN] = { }; ++ ++ if (count == 0) ++ return 0; ++ ++ if (count >= INET6_ADDRSTRLEN) ++ count = INET6_ADDRSTRLEN - 1; ++ ++ if (copy_from_user(req, buf, count)) ++ return -EFAULT; ++ ++ if (strnchr(req, count, ':')) { ++ kr.family = AF_INET6; ++ if (!in6_pton(req, count, (void *)&kr.addr, '\n', NULL)) ++ return -EINVAL; ++ } else if (strnchr(req, count, '.')) { ++ kr.family = AF_INET; ++ if (!in4_pton(req, count, (void *)&kr.addr, '\n', NULL)) ++ return -EINVAL; ++ } ++ ++ nf_ct_iterate_cleanup(net, kill_matching, &kr, 0, 0); ++ ++ return count; ++} ++ + static const struct file_operations ct_file_ops = { + .owner = THIS_MODULE, + .open = ct_open, + .read = seq_read, ++ .write = ct_file_write, + .llseek = seq_lseek, + .release = seq_release_net, + }; +@@ -367,7 +424,7 @@ static int nf_conntrack_standalone_init_ + { + struct proc_dir_entry *pde; + +- pde = proc_create("nf_conntrack", 0440, net->proc_net, &ct_file_ops); ++ pde = proc_create("nf_conntrack", 0660, net->proc_net, &ct_file_ops); + if (!pde) + goto out_nf_conntrack; + diff --git a/target/linux/generic/patches-3.18/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/patches-3.18/610-netfilter_match_bypass_default_checks.patch new file mode 100644 index 0000000..358d64b --- /dev/null +++ b/target/linux/generic/patches-3.18/610-netfilter_match_bypass_default_checks.patch @@ -0,0 +1,93 @@ +--- a/include/uapi/linux/netfilter_ipv4/ip_tables.h ++++ b/include/uapi/linux/netfilter_ipv4/ip_tables.h +@@ -87,6 +87,7 @@ struct ipt_ip { + #define IPT_F_FRAG 0x01 /* Set if rule is a fragment rule */ + #define IPT_F_GOTO 0x02 /* Set if jump is a goto */ + #define IPT_F_MASK 0x03 /* All possible flag bits mask. */ ++#define IPT_F_NO_DEF_MATCH 0x80 /* Internal: no default match rules present */ + + /* Values for "inv" field in struct ipt_ip. */ + #define IPT_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -82,6 +82,9 @@ ip_packet_match(const struct iphdr *ip, + + #define FWINV(bool, invflg) ((bool) ^ !!(ipinfo->invflags & (invflg))) + ++ if (ipinfo->flags & IPT_F_NO_DEF_MATCH) ++ return true; ++ + if (FWINV((ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, + IPT_INV_SRCIP) || + FWINV((ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, +@@ -135,6 +138,29 @@ ip_packet_match(const struct iphdr *ip, + return true; + } + ++static void ++ip_checkdefault(struct ipt_ip *ip) ++{ ++ static const char iface_mask[IFNAMSIZ] = {}; ++ ++ if (ip->invflags || ip->flags & IPT_F_FRAG) ++ return; ++ ++ if (memcmp(ip->iniface_mask, iface_mask, IFNAMSIZ) != 0) ++ return; ++ ++ if (memcmp(ip->outiface_mask, iface_mask, IFNAMSIZ) != 0) ++ return; ++ ++ if (ip->smsk.s_addr || ip->dmsk.s_addr) ++ return; ++ ++ if (ip->proto) ++ return; ++ ++ ip->flags |= IPT_F_NO_DEF_MATCH; ++} ++ + static bool + ip_checkentry(const struct ipt_ip *ip) + { +@@ -565,7 +591,7 @@ static void cleanup_match(struct xt_entr + } + + static int +-check_entry(const struct ipt_entry *e, const char *name) ++check_entry(struct ipt_entry *e, const char *name) + { + const struct xt_entry_target *t; + +@@ -574,6 +600,8 @@ check_entry(const struct ipt_entry *e, c + return -EINVAL; + } + ++ ip_checkdefault(&e->ip); ++ + if (e->target_offset + sizeof(struct xt_entry_target) > + e->next_offset) + return -EINVAL; +@@ -935,6 +963,7 @@ copy_entries_to_user(unsigned int total_ + const struct xt_table_info *private = table->private; + int ret = 0; + const void *loc_cpu_entry; ++ u8 flags; + + counters = alloc_counters(table); + if (IS_ERR(counters)) +@@ -965,6 +994,14 @@ copy_entries_to_user(unsigned int total_ + ret = -EFAULT; + goto free_counters; + } ++ ++ flags = e->ip.flags & IPT_F_MASK; ++ if (copy_to_user(userptr + off ++ + offsetof(struct ipt_entry, ip.flags), ++ &flags, sizeof(flags)) != 0) { ++ ret = -EFAULT; ++ goto free_counters; ++ } + + for (i = sizeof(struct ipt_entry); + i < e->target_offset; diff --git a/target/linux/generic/patches-3.18/611-netfilter_match_bypass_default_table.patch b/target/linux/generic/patches-3.18/611-netfilter_match_bypass_default_table.patch new file mode 100644 index 0000000..ef993c8 --- /dev/null +++ b/target/linux/generic/patches-3.18/611-netfilter_match_bypass_default_table.patch @@ -0,0 +1,94 @@ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -310,6 +310,33 @@ struct ipt_entry *ipt_next_entry(const s + return (void *)entry + entry->next_offset; + } + ++static bool ++ipt_handle_default_rule(struct ipt_entry *e, unsigned int *verdict) ++{ ++ struct xt_entry_target *t; ++ struct xt_standard_target *st; ++ ++ if (e->target_offset != sizeof(struct ipt_entry)) ++ return false; ++ ++ if (!(e->ip.flags & IPT_F_NO_DEF_MATCH)) ++ return false; ++ ++ t = ipt_get_target(e); ++ if (t->u.kernel.target->target) ++ return false; ++ ++ st = (struct xt_standard_target *) t; ++ if (st->verdict == XT_RETURN) ++ return false; ++ ++ if (st->verdict >= 0) ++ return false; ++ ++ *verdict = (unsigned)(-st->verdict) - 1; ++ return true; ++} ++ + /* Returns one of the generic firewall policies, like NF_ACCEPT. */ + unsigned int + ipt_do_table(struct sk_buff *skb, +@@ -331,9 +358,33 @@ ipt_do_table(struct sk_buff *skb, + unsigned int addend; + + /* Initialization */ ++ IP_NF_ASSERT(table->valid_hooks & (1 << hook)); ++ local_bh_disable(); ++ private = table->private; ++ cpu = smp_processor_id(); ++ /* ++ * Ensure we load private-> members after we've fetched the base ++ * pointer. ++ */ ++ smp_read_barrier_depends(); ++ table_base = private->entries[cpu]; ++ ++ e = get_entry(table_base, private->hook_entry[hook]); ++ if (ipt_handle_default_rule(e, &verdict)) { ++ ADD_COUNTER(e->counters, skb->len, 1); ++ local_bh_enable(); ++ return verdict; ++ } ++ + ip = ip_hdr(skb); + indev = in ? in->name : nulldevname; + outdev = out ? out->name : nulldevname; ++ ++ addend = xt_write_recseq_begin(); ++ jumpstack = (struct ipt_entry **)private->jumpstack[cpu]; ++ stackptr = per_cpu_ptr(private->stackptr, cpu); ++ origptr = *stackptr; ++ + /* We handle fragments by dealing with the first fragment as + * if it was a normal packet. All other fragments are treated + * normally, except that they will NEVER match rules that ask +@@ -348,23 +399,6 @@ ipt_do_table(struct sk_buff *skb, + acpar.family = NFPROTO_IPV4; + acpar.hooknum = hook; + +- IP_NF_ASSERT(table->valid_hooks & (1 << hook)); +- local_bh_disable(); +- addend = xt_write_recseq_begin(); +- private = table->private; +- cpu = smp_processor_id(); +- /* +- * Ensure we load private-> members after we've fetched the base +- * pointer. +- */ +- smp_read_barrier_depends(); +- table_base = private->entries[cpu]; +- jumpstack = (struct ipt_entry **)private->jumpstack[cpu]; +- stackptr = per_cpu_ptr(private->stackptr, cpu); +- origptr = *stackptr; +- +- e = get_entry(table_base, private->hook_entry[hook]); +- + pr_debug("Entering %s(hook %u); sp at %u (UF %p)\n", + table->name, hook, origptr, + get_entry(table_base, private->underflow[hook])); diff --git a/target/linux/generic/patches-3.18/612-netfilter_match_reduce_memory_access.patch b/target/linux/generic/patches-3.18/612-netfilter_match_reduce_memory_access.patch new file mode 100644 index 0000000..72172d8 --- /dev/null +++ b/target/linux/generic/patches-3.18/612-netfilter_match_reduce_memory_access.patch @@ -0,0 +1,16 @@ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -85,9 +85,11 @@ ip_packet_match(const struct iphdr *ip, + if (ipinfo->flags & IPT_F_NO_DEF_MATCH) + return true; + +- if (FWINV((ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, ++ if (FWINV(ipinfo->smsk.s_addr && ++ (ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, + IPT_INV_SRCIP) || +- FWINV((ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, ++ FWINV(ipinfo->dmsk.s_addr && ++ (ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, + IPT_INV_DSTIP)) { + dprintf("Source or dest mismatch.\n"); + diff --git a/target/linux/generic/patches-3.18/613-netfilter_optional_tcp_window_check.patch b/target/linux/generic/patches-3.18/613-netfilter_optional_tcp_window_check.patch new file mode 100644 index 0000000..1d3b37c --- /dev/null +++ b/target/linux/generic/patches-3.18/613-netfilter_optional_tcp_window_check.patch @@ -0,0 +1,36 @@ +--- a/net/netfilter/nf_conntrack_proto_tcp.c ++++ b/net/netfilter/nf_conntrack_proto_tcp.c +@@ -33,6 +33,9 @@ + #include + #include + ++/* Do not check the TCP window for incoming packets */ ++static int nf_ct_tcp_no_window_check __read_mostly = 1; ++ + /* "Be conservative in what you do, + be liberal in what you accept from others." + If it's non-zero, we mark only out of window RST segments as INVALID. */ +@@ -515,6 +518,9 @@ static bool tcp_in_window(const struct n + s32 receiver_offset; + bool res, in_recv_win; + ++ if (nf_ct_tcp_no_window_check) ++ return true; ++ + /* + * Get the required data from the packet. + */ +@@ -1452,6 +1458,13 @@ static struct ctl_table tcp_sysctl_table + .mode = 0644, + .proc_handler = proc_dointvec, + }, ++ { ++ .procname = "nf_conntrack_tcp_no_window_check", ++ .data = &nf_ct_tcp_no_window_check, ++ .maxlen = sizeof(unsigned int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec, ++ }, + { } + }; + diff --git a/target/linux/generic/patches-3.18/615-netfilter_add_xt_id_match.patch b/target/linux/generic/patches-3.18/615-netfilter_add_xt_id_match.patch new file mode 100644 index 0000000..45f59a2 --- /dev/null +++ b/target/linux/generic/patches-3.18/615-netfilter_add_xt_id_match.patch @@ -0,0 +1,95 @@ +--- a/include/uapi/linux/netfilter/Kbuild ++++ b/include/uapi/linux/netfilter/Kbuild +@@ -55,6 +55,7 @@ header-y += xt_ecn.h + header-y += xt_esp.h + header-y += xt_hashlimit.h + header-y += xt_helper.h ++header-y += xt_id.h + header-y += xt_ipcomp.h + header-y += xt_iprange.h + header-y += xt_ipvs.h +--- /dev/null ++++ b/include/uapi/linux/netfilter/xt_id.h +@@ -0,0 +1,8 @@ ++#ifndef _XT_ID_H ++#define _XT_ID_H ++ ++struct xt_id_info { ++ u32 id; ++}; ++ ++#endif /* XT_ID_H */ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -1157,6 +1157,13 @@ config NETFILTER_XT_MATCH_IPCOMP + + To compile it as a module, choose M here. If unsure, say N. + ++config NETFILTER_XT_MATCH_ID ++ tristate '"id" match support' ++ depends on NETFILTER_ADVANCED ++ ---help--- ++ This option adds a `id' dummy-match, which allows you to put ++ numeric IDs into your iptables ruleset. ++ + config NETFILTER_XT_MATCH_IPRANGE + tristate '"iprange" address range match support' + depends on NETFILTER_ADVANCED +--- a/net/netfilter/Makefile ++++ b/net/netfilter/Makefile +@@ -143,6 +143,7 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_ESP) += + obj-$(CONFIG_NETFILTER_XT_MATCH_HASHLIMIT) += xt_hashlimit.o + obj-$(CONFIG_NETFILTER_XT_MATCH_HELPER) += xt_helper.o + obj-$(CONFIG_NETFILTER_XT_MATCH_HL) += xt_hl.o ++obj-$(CONFIG_NETFILTER_XT_MATCH_ID) += xt_id.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPCOMP) += xt_ipcomp.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPRANGE) += xt_iprange.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPVS) += xt_ipvs.o +--- /dev/null ++++ b/net/netfilter/xt_id.c +@@ -0,0 +1,45 @@ ++/* ++ * Implements a dummy match to allow attaching IDs to rules ++ * ++ * 2014-08-01 Jo-Philipp Wich ++ */ ++ ++#include ++#include ++#include ++#include ++ ++MODULE_AUTHOR("Jo-Philipp Wich "); ++MODULE_DESCRIPTION("Xtables: No-op match which can be tagged with a 32bit ID"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("ipt_id"); ++MODULE_ALIAS("ip6t_id"); ++ ++static bool ++id_mt(const struct sk_buff *skb, struct xt_action_param *par) ++{ ++ /* We always match */ ++ return true; ++} ++ ++static struct xt_match id_mt_reg __read_mostly = { ++ .name = "id", ++ .revision = 0, ++ .family = NFPROTO_UNSPEC, ++ .match = id_mt, ++ .matchsize = sizeof(struct xt_id_info), ++ .me = THIS_MODULE, ++}; ++ ++static int __init id_mt_init(void) ++{ ++ return xt_register_match(&id_mt_reg); ++} ++ ++static void __exit id_mt_exit(void) ++{ ++ xt_unregister_match(&id_mt_reg); ++} ++ ++module_init(id_mt_init); ++module_exit(id_mt_exit); diff --git a/target/linux/generic/patches-3.18/616-net_optimize_xfrm_calls.patch b/target/linux/generic/patches-3.18/616-net_optimize_xfrm_calls.patch new file mode 100644 index 0000000..2a64d54 --- /dev/null +++ b/target/linux/generic/patches-3.18/616-net_optimize_xfrm_calls.patch @@ -0,0 +1,12 @@ +--- a/net/netfilter/nf_nat_core.c ++++ b/net/netfilter/nf_nat_core.c +@@ -90,6 +90,9 @@ int nf_xfrm_me_harder(struct sk_buff *sk + struct dst_entry *dst; + int err; + ++ if (skb->dev && !dev_net(skb->dev)->xfrm.policy_count[XFRM_POLICY_OUT]) ++ return 0; ++ + err = xfrm_decode_session(skb, &fl, family); + if (err < 0) + return err; diff --git a/target/linux/generic/patches-3.18/620-sched_esfq.patch b/target/linux/generic/patches-3.18/620-sched_esfq.patch new file mode 100644 index 0000000..9726e4a --- /dev/null +++ b/target/linux/generic/patches-3.18/620-sched_esfq.patch @@ -0,0 +1,791 @@ +--- a/include/uapi/linux/pkt_sched.h ++++ b/include/uapi/linux/pkt_sched.h +@@ -226,6 +226,33 @@ struct tc_sfq_xstats { + __s32 allot; + }; + ++/* ESFQ section */ ++ ++enum ++{ ++ /* traditional */ ++ TCA_SFQ_HASH_CLASSIC, ++ TCA_SFQ_HASH_DST, ++ TCA_SFQ_HASH_SRC, ++ TCA_SFQ_HASH_FWMARK, ++ /* conntrack */ ++ TCA_SFQ_HASH_CTORIGDST, ++ TCA_SFQ_HASH_CTORIGSRC, ++ TCA_SFQ_HASH_CTREPLDST, ++ TCA_SFQ_HASH_CTREPLSRC, ++ TCA_SFQ_HASH_CTNATCHG, ++}; ++ ++struct tc_esfq_qopt ++{ ++ unsigned quantum; /* Bytes per round allocated to flow */ ++ int perturb_period; /* Period of hash perturbation */ ++ __u32 limit; /* Maximal packets in queue */ ++ unsigned divisor; /* Hash divisor */ ++ unsigned flows; /* Maximal number of flows */ ++ unsigned hash_kind; /* Hash function to use for flow identification */ ++}; ++ + /* RED section */ + + enum { +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -148,6 +148,37 @@ config NET_SCH_SFQ + To compile this code as a module, choose M here: the + module will be called sch_sfq. + ++config NET_SCH_ESFQ ++ tristate "Enhanced Stochastic Fairness Queueing (ESFQ)" ++ ---help--- ++ Say Y here if you want to use the Enhanced Stochastic Fairness ++ Queueing (ESFQ) packet scheduling algorithm for some of your network ++ devices or as a leaf discipline for a classful qdisc such as HTB or ++ CBQ (see the top of for details and ++ references to the SFQ algorithm). ++ ++ This is an enchanced SFQ version which allows you to control some ++ hardcoded values in the SFQ scheduler. ++ ++ ESFQ also adds control of the hash function used to identify packet ++ flows. The original SFQ discipline hashes by connection; ESFQ add ++ several other hashing methods, such as by src IP or by dst IP, which ++ can be more fair to users in some networking situations. ++ ++ To compile this code as a module, choose M here: the ++ module will be called sch_esfq. ++ ++config NET_SCH_ESFQ_NFCT ++ bool "Connection Tracking Hash Types" ++ depends on NET_SCH_ESFQ && NF_CONNTRACK ++ ---help--- ++ Say Y here to enable support for hashing based on netfilter connection ++ tracking information. This is useful for a router that is also using ++ NAT to connect privately-addressed hosts to the Internet. If you want ++ to provide fair distribution of upstream bandwidth, ESFQ must use ++ connection tracking information, since all outgoing packets will share ++ the same source address. ++ + config NET_SCH_TEQL + tristate "True Link Equalizer (TEQL)" + ---help--- +--- a/net/sched/Makefile ++++ b/net/sched/Makefile +@@ -26,6 +26,7 @@ obj-$(CONFIG_NET_SCH_INGRESS) += sch_ing + obj-$(CONFIG_NET_SCH_DSMARK) += sch_dsmark.o + obj-$(CONFIG_NET_SCH_SFB) += sch_sfb.o + obj-$(CONFIG_NET_SCH_SFQ) += sch_sfq.o ++obj-$(CONFIG_NET_SCH_ESFQ) += sch_esfq.o + obj-$(CONFIG_NET_SCH_TBF) += sch_tbf.o + obj-$(CONFIG_NET_SCH_TEQL) += sch_teql.o + obj-$(CONFIG_NET_SCH_PRIO) += sch_prio.o +--- /dev/null ++++ b/net/sched/sch_esfq.c +@@ -0,0 +1,702 @@ ++/* ++ * net/sched/sch_esfq.c Extended Stochastic Fairness Queueing discipline. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Authors: Alexey Kuznetsov, ++ * ++ * Changes: Alexander Atanasov, ++ * Added dynamic depth,limit,divisor,hash_kind options. ++ * Added dst and src hashes. ++ * ++ * Alexander Clouter, ++ * Ported ESFQ to Linux 2.6. ++ * ++ * Corey Hickey, ++ * Maintenance of the Linux 2.6 port. ++ * Added fwmark hash (thanks to Robert Kurjata). ++ * Added usage of jhash. ++ * Added conntrack support. ++ * Added ctnatchg hash (thanks to Ben Pfountz). ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++#include ++#endif ++ ++/* Stochastic Fairness Queuing algorithm. ++ For more comments look at sch_sfq.c. ++ The difference is that you can change limit, depth, ++ hash table size and choose alternate hash types. ++ ++ classic: same as in sch_sfq.c ++ dst: destination IP address ++ src: source IP address ++ fwmark: netfilter mark value ++ ctorigdst: original destination IP address ++ ctorigsrc: original source IP address ++ ctrepldst: reply destination IP address ++ ctreplsrc: reply source IP ++ ++*/ ++ ++#define ESFQ_HEAD 0 ++#define ESFQ_TAIL 1 ++ ++/* This type should contain at least SFQ_DEPTH*2 values */ ++typedef unsigned int esfq_index; ++ ++struct esfq_head ++{ ++ esfq_index next; ++ esfq_index prev; ++}; ++ ++struct esfq_sched_data ++{ ++/* Parameters */ ++ int perturb_period; ++ unsigned quantum; /* Allotment per round: MUST BE >= MTU */ ++ int limit; ++ unsigned depth; ++ unsigned hash_divisor; ++ unsigned hash_kind; ++/* Variables */ ++ struct timer_list perturb_timer; ++ int perturbation; ++ esfq_index tail; /* Index of current slot in round */ ++ esfq_index max_depth; /* Maximal depth */ ++ ++ esfq_index *ht; /* Hash table */ ++ esfq_index *next; /* Active slots link */ ++ short *allot; /* Current allotment per slot */ ++ unsigned short *hash; /* Hash value indexed by slots */ ++ struct sk_buff_head *qs; /* Slot queue */ ++ struct esfq_head *dep; /* Linked list of slots, indexed by depth */ ++}; ++ ++/* This contains the info we will hash. */ ++struct esfq_packet_info ++{ ++ u32 proto; /* protocol or port */ ++ u32 src; /* source from packet header */ ++ u32 dst; /* destination from packet header */ ++ u32 ctorigsrc; /* original source from conntrack */ ++ u32 ctorigdst; /* original destination from conntrack */ ++ u32 ctreplsrc; /* reply source from conntrack */ ++ u32 ctrepldst; /* reply destination from conntrack */ ++ u32 mark; /* netfilter mark (fwmark) */ ++}; ++ ++static __inline__ unsigned esfq_jhash_1word(struct esfq_sched_data *q,u32 a) ++{ ++ return jhash_1word(a, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static __inline__ unsigned esfq_jhash_2words(struct esfq_sched_data *q, u32 a, u32 b) ++{ ++ return jhash_2words(a, b, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static __inline__ unsigned esfq_jhash_3words(struct esfq_sched_data *q, u32 a, u32 b, u32 c) ++{ ++ return jhash_3words(a, b, c, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static unsigned esfq_hash(struct esfq_sched_data *q, struct sk_buff *skb) ++{ ++ struct esfq_packet_info info; ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ enum ip_conntrack_info ctinfo; ++ struct nf_conn *ct = nf_ct_get(skb, &ctinfo); ++#endif ++ ++ switch (skb->protocol) { ++ case __constant_htons(ETH_P_IP): ++ { ++ struct iphdr *iph = ip_hdr(skb); ++ info.dst = iph->daddr; ++ info.src = iph->saddr; ++ if (!(iph->frag_off&htons(IP_MF|IP_OFFSET)) && ++ (iph->protocol == IPPROTO_TCP || ++ iph->protocol == IPPROTO_UDP || ++ iph->protocol == IPPROTO_SCTP || ++ iph->protocol == IPPROTO_DCCP || ++ iph->protocol == IPPROTO_ESP)) ++ info.proto = *(((u32*)iph) + iph->ihl); ++ else ++ info.proto = iph->protocol; ++ break; ++ } ++ case __constant_htons(ETH_P_IPV6): ++ { ++ struct ipv6hdr *iph = ipv6_hdr(skb); ++ /* Hash ipv6 addresses into a u32. This isn't ideal, ++ * but the code is simple. */ ++ info.dst = jhash2(iph->daddr.s6_addr32, 4, q->perturbation); ++ info.src = jhash2(iph->saddr.s6_addr32, 4, q->perturbation); ++ if (iph->nexthdr == IPPROTO_TCP || ++ iph->nexthdr == IPPROTO_UDP || ++ iph->nexthdr == IPPROTO_SCTP || ++ iph->nexthdr == IPPROTO_DCCP || ++ iph->nexthdr == IPPROTO_ESP) ++ info.proto = *(u32*)&iph[1]; ++ else ++ info.proto = iph->nexthdr; ++ break; ++ } ++ default: ++ info.dst = (u32)(unsigned long)skb_dst(skb); ++ info.src = (u32)(unsigned long)skb->sk; ++ info.proto = skb->protocol; ++ } ++ ++ info.mark = skb->mark; ++ ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ /* defaults if there is no conntrack info */ ++ info.ctorigsrc = info.src; ++ info.ctorigdst = info.dst; ++ info.ctreplsrc = info.dst; ++ info.ctrepldst = info.src; ++ /* collect conntrack info */ ++ if (ct && ct != &nf_conntrack_untracked) { ++ if (skb->protocol == __constant_htons(ETH_P_IP)) { ++ info.ctorigsrc = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip; ++ info.ctorigdst = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.u3.ip; ++ info.ctreplsrc = ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip; ++ info.ctrepldst = ct->tuplehash[IP_CT_DIR_REPLY].tuple.dst.u3.ip; ++ } ++ else if (skb->protocol == __constant_htons(ETH_P_IPV6)) { ++ /* Again, hash ipv6 addresses into a single u32. */ ++ info.ctorigsrc = jhash2(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip6, 4, q->perturbation); ++ info.ctorigdst = jhash2(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.u3.ip6, 4, q->perturbation); ++ info.ctreplsrc = jhash2(ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip6, 4, q->perturbation); ++ info.ctrepldst = jhash2(ct->tuplehash[IP_CT_DIR_REPLY].tuple.dst.u3.ip6, 4, q->perturbation); ++ } ++ ++ } ++#endif ++ ++ switch(q->hash_kind) { ++ case TCA_SFQ_HASH_CLASSIC: ++ return esfq_jhash_3words(q, info.dst, info.src, info.proto); ++ case TCA_SFQ_HASH_DST: ++ return esfq_jhash_1word(q, info.dst); ++ case TCA_SFQ_HASH_SRC: ++ return esfq_jhash_1word(q, info.src); ++ case TCA_SFQ_HASH_FWMARK: ++ return esfq_jhash_1word(q, info.mark); ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ case TCA_SFQ_HASH_CTORIGDST: ++ return esfq_jhash_1word(q, info.ctorigdst); ++ case TCA_SFQ_HASH_CTORIGSRC: ++ return esfq_jhash_1word(q, info.ctorigsrc); ++ case TCA_SFQ_HASH_CTREPLDST: ++ return esfq_jhash_1word(q, info.ctrepldst); ++ case TCA_SFQ_HASH_CTREPLSRC: ++ return esfq_jhash_1word(q, info.ctreplsrc); ++ case TCA_SFQ_HASH_CTNATCHG: ++ { ++ if (info.ctorigdst == info.ctreplsrc) ++ return esfq_jhash_1word(q, info.ctorigsrc); ++ return esfq_jhash_1word(q, info.ctreplsrc); ++ } ++#endif ++ default: ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Unknown hash method. Falling back to classic.\n"); ++ } ++ return esfq_jhash_3words(q, info.dst, info.src, info.proto); ++} ++ ++static inline void esfq_link(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ int d = q->qs[x].qlen + q->depth; ++ ++ p = d; ++ n = q->dep[d].next; ++ q->dep[x].next = n; ++ q->dep[x].prev = p; ++ q->dep[p].next = q->dep[n].prev = x; ++} ++ ++static inline void esfq_dec(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ ++ n = q->dep[x].next; ++ p = q->dep[x].prev; ++ q->dep[p].next = n; ++ q->dep[n].prev = p; ++ ++ if (n == p && q->max_depth == q->qs[x].qlen + 1) ++ q->max_depth--; ++ ++ esfq_link(q, x); ++} ++ ++static inline void esfq_inc(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ int d; ++ ++ n = q->dep[x].next; ++ p = q->dep[x].prev; ++ q->dep[p].next = n; ++ q->dep[n].prev = p; ++ d = q->qs[x].qlen; ++ if (q->max_depth < d) ++ q->max_depth = d; ++ ++ esfq_link(q, x); ++} ++ ++static unsigned int esfq_drop(struct Qdisc *sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_index d = q->max_depth; ++ struct sk_buff *skb; ++ unsigned int len; ++ ++ /* Queue is full! Find the longest slot and ++ drop a packet from it */ ++ ++ if (d > 1) { ++ esfq_index x = q->dep[d+q->depth].next; ++ skb = q->qs[x].prev; ++ len = skb->len; ++ __skb_unlink(skb, &q->qs[x]); ++ kfree_skb(skb); ++ esfq_dec(q, x); ++ sch->q.qlen--; ++ sch->qstats.drops++; ++ sch->qstats.backlog -= len; ++ return len; ++ } ++ ++ if (d == 1) { ++ /* It is difficult to believe, but ALL THE SLOTS HAVE LENGTH 1. */ ++ d = q->next[q->tail]; ++ q->next[q->tail] = q->next[d]; ++ q->allot[q->next[d]] += q->quantum; ++ skb = q->qs[d].prev; ++ len = skb->len; ++ __skb_unlink(skb, &q->qs[d]); ++ kfree_skb(skb); ++ esfq_dec(q, d); ++ sch->q.qlen--; ++ q->ht[q->hash[d]] = q->depth; ++ sch->qstats.drops++; ++ sch->qstats.backlog -= len; ++ return len; ++ } ++ ++ return 0; ++} ++ ++static void esfq_q_enqueue(struct sk_buff *skb, struct esfq_sched_data *q, unsigned int end) ++{ ++ unsigned hash = esfq_hash(q, skb); ++ unsigned depth = q->depth; ++ esfq_index x; ++ ++ x = q->ht[hash]; ++ if (x == depth) { ++ q->ht[hash] = x = q->dep[depth].next; ++ q->hash[x] = hash; ++ } ++ ++ if (end == ESFQ_TAIL) ++ __skb_queue_tail(&q->qs[x], skb); ++ else ++ __skb_queue_head(&q->qs[x], skb); ++ ++ esfq_inc(q, x); ++ if (q->qs[x].qlen == 1) { /* The flow is new */ ++ if (q->tail == depth) { /* It is the first flow */ ++ q->tail = x; ++ q->next[x] = x; ++ q->allot[x] = q->quantum; ++ } else { ++ q->next[x] = q->next[q->tail]; ++ q->next[q->tail] = x; ++ q->tail = x; ++ } ++ } ++} ++ ++static int esfq_enqueue(struct sk_buff *skb, struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_q_enqueue(skb, q, ESFQ_TAIL); ++ sch->qstats.backlog += skb->len; ++ if (++sch->q.qlen < q->limit-1) { ++ sch->bstats.bytes += skb->len; ++ sch->bstats.packets++; ++ return 0; ++ } ++ ++ sch->qstats.drops++; ++ esfq_drop(sch); ++ return NET_XMIT_CN; ++} ++ ++static struct sk_buff *esfq_peek(struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_index a; ++ ++ /* No active slots */ ++ if (q->tail == q->depth) ++ return NULL; ++ ++ a = q->next[q->tail]; ++ return skb_peek(&q->qs[a]); ++} ++ ++static struct sk_buff *esfq_q_dequeue(struct esfq_sched_data *q) ++{ ++ struct sk_buff *skb; ++ unsigned depth = q->depth; ++ esfq_index a, old_a; ++ ++ /* No active slots */ ++ if (q->tail == depth) ++ return NULL; ++ ++ a = old_a = q->next[q->tail]; ++ ++ /* Grab packet */ ++ skb = __skb_dequeue(&q->qs[a]); ++ esfq_dec(q, a); ++ ++ /* Is the slot empty? */ ++ if (q->qs[a].qlen == 0) { ++ q->ht[q->hash[a]] = depth; ++ a = q->next[a]; ++ if (a == old_a) { ++ q->tail = depth; ++ return skb; ++ } ++ q->next[q->tail] = a; ++ q->allot[a] += q->quantum; ++ } else if ((q->allot[a] -= skb->len) <= 0) { ++ q->tail = a; ++ a = q->next[a]; ++ q->allot[a] += q->quantum; ++ } ++ ++ return skb; ++} ++ ++static struct sk_buff *esfq_dequeue(struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ struct sk_buff *skb; ++ ++ skb = esfq_q_dequeue(q); ++ if (skb == NULL) ++ return NULL; ++ sch->q.qlen--; ++ sch->qstats.backlog -= skb->len; ++ return skb; ++} ++ ++static void esfq_q_destroy(struct esfq_sched_data *q) ++{ ++ del_timer(&q->perturb_timer); ++ if(q->ht) ++ kfree(q->ht); ++ if(q->dep) ++ kfree(q->dep); ++ if(q->next) ++ kfree(q->next); ++ if(q->allot) ++ kfree(q->allot); ++ if(q->hash) ++ kfree(q->hash); ++ if(q->qs) ++ kfree(q->qs); ++} ++ ++static void esfq_destroy(struct Qdisc *sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_q_destroy(q); ++} ++ ++ ++static void esfq_reset(struct Qdisc* sch) ++{ ++ struct sk_buff *skb; ++ ++ while ((skb = esfq_dequeue(sch)) != NULL) ++ kfree_skb(skb); ++} ++ ++static void esfq_perturbation(unsigned long arg) ++{ ++ struct Qdisc *sch = (struct Qdisc*)arg; ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ ++ q->perturbation = prandom_u32()&0x1F; ++ ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } ++} ++ ++static unsigned int esfq_check_hash(unsigned int kind) ++{ ++ switch (kind) { ++ case TCA_SFQ_HASH_CTORIGDST: ++ case TCA_SFQ_HASH_CTORIGSRC: ++ case TCA_SFQ_HASH_CTREPLDST: ++ case TCA_SFQ_HASH_CTREPLSRC: ++ case TCA_SFQ_HASH_CTNATCHG: ++#ifndef CONFIG_NET_SCH_ESFQ_NFCT ++ { ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Conntrack hash types disabled in kernel config. Falling back to classic.\n"); ++ return TCA_SFQ_HASH_CLASSIC; ++ } ++#endif ++ case TCA_SFQ_HASH_CLASSIC: ++ case TCA_SFQ_HASH_DST: ++ case TCA_SFQ_HASH_SRC: ++ case TCA_SFQ_HASH_FWMARK: ++ return kind; ++ default: ++ { ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Unknown hash type. Falling back to classic.\n"); ++ return TCA_SFQ_HASH_CLASSIC; ++ } ++ } ++} ++ ++static int esfq_q_init(struct esfq_sched_data *q, struct nlattr *opt) ++{ ++ struct tc_esfq_qopt *ctl = nla_data(opt); ++ esfq_index p = ~0U/2; ++ int i; ++ ++ if (opt && opt->nla_len < nla_attr_size(sizeof(*ctl))) ++ return -EINVAL; ++ ++ q->perturbation = 0; ++ q->hash_kind = TCA_SFQ_HASH_CLASSIC; ++ q->max_depth = 0; ++ if (opt == NULL) { ++ q->perturb_period = 0; ++ q->hash_divisor = 1024; ++ q->tail = q->limit = q->depth = 128; ++ ++ } else { ++ struct tc_esfq_qopt *ctl = nla_data(opt); ++ if (ctl->quantum) ++ q->quantum = ctl->quantum; ++ q->perturb_period = ctl->perturb_period*HZ; ++ q->hash_divisor = ctl->divisor ? : 1024; ++ q->tail = q->limit = q->depth = ctl->flows ? : 128; ++ ++ if ( q->depth > p - 1 ) ++ return -EINVAL; ++ ++ if (ctl->limit) ++ q->limit = min_t(u32, ctl->limit, q->depth); ++ ++ if (ctl->hash_kind) { ++ q->hash_kind = esfq_check_hash(ctl->hash_kind); ++ } ++ } ++ ++ q->ht = kmalloc(q->hash_divisor*sizeof(esfq_index), GFP_KERNEL); ++ if (!q->ht) ++ goto err_case; ++ q->dep = kmalloc((1+q->depth*2)*sizeof(struct esfq_head), GFP_KERNEL); ++ if (!q->dep) ++ goto err_case; ++ q->next = kmalloc(q->depth*sizeof(esfq_index), GFP_KERNEL); ++ if (!q->next) ++ goto err_case; ++ q->allot = kmalloc(q->depth*sizeof(short), GFP_KERNEL); ++ if (!q->allot) ++ goto err_case; ++ q->hash = kmalloc(q->depth*sizeof(unsigned short), GFP_KERNEL); ++ if (!q->hash) ++ goto err_case; ++ q->qs = kmalloc(q->depth*sizeof(struct sk_buff_head), GFP_KERNEL); ++ if (!q->qs) ++ goto err_case; ++ ++ for (i=0; i< q->hash_divisor; i++) ++ q->ht[i] = q->depth; ++ for (i=0; idepth; i++) { ++ skb_queue_head_init(&q->qs[i]); ++ q->dep[i+q->depth].next = i+q->depth; ++ q->dep[i+q->depth].prev = i+q->depth; ++ } ++ ++ for (i=0; idepth; i++) ++ esfq_link(q, i); ++ return 0; ++err_case: ++ esfq_q_destroy(q); ++ return -ENOBUFS; ++} ++ ++static int esfq_init(struct Qdisc *sch, struct nlattr *opt) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ int err; ++ ++ q->quantum = psched_mtu(qdisc_dev(sch)); /* default */ ++ if ((err = esfq_q_init(q, opt))) ++ return err; ++ ++ init_timer(&q->perturb_timer); ++ q->perturb_timer.data = (unsigned long)sch; ++ q->perturb_timer.function = esfq_perturbation; ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } ++ ++ return 0; ++} ++ ++static int esfq_change(struct Qdisc *sch, struct nlattr *opt) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ struct esfq_sched_data new; ++ struct sk_buff *skb; ++ int err; ++ ++ /* set up new queue */ ++ memset(&new, 0, sizeof(struct esfq_sched_data)); ++ new.quantum = psched_mtu(qdisc_dev(sch)); /* default */ ++ if ((err = esfq_q_init(&new, opt))) ++ return err; ++ ++ /* copy all packets from the old queue to the new queue */ ++ sch_tree_lock(sch); ++ while ((skb = esfq_q_dequeue(q)) != NULL) ++ esfq_q_enqueue(skb, &new, ESFQ_TAIL); ++ ++ /* clean up the old queue */ ++ esfq_q_destroy(q); ++ ++ /* copy elements of the new queue into the old queue */ ++ q->perturb_period = new.perturb_period; ++ q->quantum = new.quantum; ++ q->limit = new.limit; ++ q->depth = new.depth; ++ q->hash_divisor = new.hash_divisor; ++ q->hash_kind = new.hash_kind; ++ q->tail = new.tail; ++ q->max_depth = new.max_depth; ++ q->ht = new.ht; ++ q->dep = new.dep; ++ q->next = new.next; ++ q->allot = new.allot; ++ q->hash = new.hash; ++ q->qs = new.qs; ++ ++ /* finish up */ ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } else { ++ q->perturbation = 0; ++ } ++ sch_tree_unlock(sch); ++ return 0; ++} ++ ++static int esfq_dump(struct Qdisc *sch, struct sk_buff *skb) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ unsigned char *b = skb_tail_pointer(skb); ++ struct tc_esfq_qopt opt; ++ ++ opt.quantum = q->quantum; ++ opt.perturb_period = q->perturb_period/HZ; ++ ++ opt.limit = q->limit; ++ opt.divisor = q->hash_divisor; ++ opt.flows = q->depth; ++ opt.hash_kind = q->hash_kind; ++ ++ if (nla_put(skb, TCA_OPTIONS, sizeof(opt), &opt)) ++ goto nla_put_failure; ++ ++ return skb->len; ++ ++nla_put_failure: ++ nlmsg_trim(skb, b); ++ return -1; ++} ++ ++static struct Qdisc_ops esfq_qdisc_ops = ++{ ++ .next = NULL, ++ .cl_ops = NULL, ++ .id = "esfq", ++ .priv_size = sizeof(struct esfq_sched_data), ++ .enqueue = esfq_enqueue, ++ .dequeue = esfq_dequeue, ++ .peek = esfq_peek, ++ .drop = esfq_drop, ++ .init = esfq_init, ++ .reset = esfq_reset, ++ .destroy = esfq_destroy, ++ .change = esfq_change, ++ .dump = esfq_dump, ++ .owner = THIS_MODULE, ++}; ++ ++static int __init esfq_module_init(void) ++{ ++ return register_qdisc(&esfq_qdisc_ops); ++} ++static void __exit esfq_module_exit(void) ++{ ++ unregister_qdisc(&esfq_qdisc_ops); ++} ++module_init(esfq_module_init) ++module_exit(esfq_module_exit) ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-3.18/621-sched_act_connmark.patch b/target/linux/generic/patches-3.18/621-sched_act_connmark.patch new file mode 100644 index 0000000..9459749 --- /dev/null +++ b/target/linux/generic/patches-3.18/621-sched_act_connmark.patch @@ -0,0 +1,161 @@ +--- /dev/null ++++ b/net/sched/act_connmark.c +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (c) 2011 Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple ++ * Place - Suite 330, Boston, MA 02111-1307 USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define TCA_ACT_CONNMARK 20 ++ ++#define CONNMARK_TAB_MASK 3 ++ ++static int tcf_connmark(struct sk_buff *skb, const struct tc_action *a, ++ struct tcf_result *res) ++{ ++ struct nf_conn *c; ++ enum ip_conntrack_info ctinfo; ++ int proto; ++ int r; ++ ++ if (skb->protocol == htons(ETH_P_IP)) { ++ if (skb->len < sizeof(struct iphdr)) ++ goto out; ++ proto = PF_INET; ++ } else if (skb->protocol == htons(ETH_P_IPV6)) { ++ if (skb->len < sizeof(struct ipv6hdr)) ++ goto out; ++ proto = PF_INET6; ++ } else ++ goto out; ++ ++ r = nf_conntrack_in(dev_net(skb->dev), proto, NF_INET_PRE_ROUTING, skb); ++ if (r != NF_ACCEPT) ++ goto out; ++ ++ c = nf_ct_get(skb, &ctinfo); ++ if (!c) ++ goto out; ++ ++ skb->mark = c->mark; ++ nf_conntrack_put(skb->nfct); ++ skb->nfct = NULL; ++ ++out: ++ return TC_ACT_PIPE; ++} ++ ++static int tcf_connmark_init(struct net *net, struct nlattr *nla, ++ struct nlattr *est, struct tc_action *a, ++ int ovr, int bind) ++{ ++ int ret = 0; ++ ++ if (!tcf_hash_check(0, a, bind)) { ++ ret = tcf_hash_create(0, est, a, sizeof(struct tcf_common), bind); ++ if (ret) ++ return ret; ++ ++ tcf_hash_insert(a); ++ ret = ACT_P_CREATED; ++ } else { ++ if (!ovr) { ++ tcf_hash_release(a, bind); ++ return -EEXIST; ++ } ++ } ++ ++ return ret; ++} ++ ++static inline int tcf_connmark_dump(struct sk_buff *skb, struct tc_action *a, ++ int bind, int ref) ++{ ++ return skb->len; ++} ++ ++static struct tc_action_ops act_connmark_ops = { ++ .kind = "connmark", ++ .type = TCA_ACT_CONNMARK, ++ .owner = THIS_MODULE, ++ .act = tcf_connmark, ++ .dump = tcf_connmark_dump, ++ .init = tcf_connmark_init, ++}; ++ ++MODULE_AUTHOR("Felix Fietkau "); ++MODULE_DESCRIPTION("Connection tracking mark restoring"); ++MODULE_LICENSE("GPL"); ++ ++static int __init connmark_init_module(void) ++{ ++ ++ return tcf_register_action(&act_connmark_ops, CONNMARK_TAB_MASK); ++} ++ ++static void __exit connmark_cleanup_module(void) ++{ ++ tcf_unregister_action(&act_connmark_ops); ++} ++ ++module_init(connmark_init_module); ++module_exit(connmark_cleanup_module); +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -717,6 +717,19 @@ config NET_ACT_CSUM + To compile this code as a module, choose M here: the + module will be called act_csum. + ++config NET_ACT_CONNMARK ++ tristate "Connection Tracking Marking" ++ depends on NET_CLS_ACT ++ depends on NF_CONNTRACK ++ depends on NF_CONNTRACK_MARK ++ ---help--- ++ Say Y here to restore the connmark from a scheduler action ++ ++ If unsure, say N. ++ ++ To compile this code as a module, choose M here: the ++ module will be called act_connmark. ++ + config NET_CLS_IND + bool "Incoming device classification" + depends on NET_CLS_U32 || NET_CLS_FW +--- a/net/sched/Makefile ++++ b/net/sched/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_NET_ACT_PEDIT) += act_pedit + obj-$(CONFIG_NET_ACT_SIMP) += act_simple.o + obj-$(CONFIG_NET_ACT_SKBEDIT) += act_skbedit.o + obj-$(CONFIG_NET_ACT_CSUM) += act_csum.o ++obj-$(CONFIG_NET_ACT_CONNMARK) += act_connmark.o + obj-$(CONFIG_NET_SCH_FIFO) += sch_fifo.o + obj-$(CONFIG_NET_SCH_CBQ) += sch_cbq.o + obj-$(CONFIG_NET_SCH_HTB) += sch_htb.o diff --git a/target/linux/generic/patches-3.18/630-packet_socket_type.patch b/target/linux/generic/patches-3.18/630-packet_socket_type.patch new file mode 100644 index 0000000..31f4bca --- /dev/null +++ b/target/linux/generic/patches-3.18/630-packet_socket_type.patch @@ -0,0 +1,134 @@ +This patch allows the user to specify desired packet types (outgoing, +broadcast, unicast, etc.) on packet sockets via setsockopt. +This can reduce the load in situations where only a limited number +of packet types are necessary + +Signed-off-by: Felix Fietkau + +--- a/include/uapi/linux/if_packet.h ++++ b/include/uapi/linux/if_packet.h +@@ -31,6 +31,8 @@ struct sockaddr_ll { + #define PACKET_KERNEL 7 /* To kernel space */ + /* Unused, PACKET_FASTROUTE and PACKET_LOOPBACK are invisible to user space */ + #define PACKET_FASTROUTE 6 /* Fastrouted frame */ ++#define PACKET_MASK_ANY 0xffffffff /* mask for packet type bits */ ++ + + /* Packet socket options */ + +@@ -54,6 +56,7 @@ struct sockaddr_ll { + #define PACKET_FANOUT 18 + #define PACKET_TX_HAS_OFF 19 + #define PACKET_QDISC_BYPASS 20 ++#define PACKET_RECV_TYPE 21 + + #define PACKET_FANOUT_HASH 0 + #define PACKET_FANOUT_LB 1 +--- a/net/packet/af_packet.c ++++ b/net/packet/af_packet.c +@@ -1516,6 +1516,7 @@ static int packet_rcv_spkt(struct sk_buf + { + struct sock *sk; + struct sockaddr_pkt *spkt; ++ struct packet_sock *po; + + /* + * When we registered the protocol we saved the socket in the data +@@ -1523,6 +1524,7 @@ static int packet_rcv_spkt(struct sk_buf + */ + + sk = pt->af_packet_priv; ++ po = pkt_sk(sk); + + /* + * Yank back the headers [hope the device set this +@@ -1535,7 +1537,7 @@ static int packet_rcv_spkt(struct sk_buf + * so that this procedure is noop. + */ + +- if (skb->pkt_type == PACKET_LOOPBACK) ++ if (!(po->pkt_type & (1 << skb->pkt_type))) + goto out; + + if (!net_eq(dev_net(dev), sock_net(sk))) +@@ -1742,12 +1744,12 @@ static int packet_rcv(struct sk_buff *sk + int skb_len = skb->len; + unsigned int snaplen, res; + +- if (skb->pkt_type == PACKET_LOOPBACK) +- goto drop; +- + sk = pt->af_packet_priv; + po = pkt_sk(sk); + ++ if (!(po->pkt_type & (1 << skb->pkt_type))) ++ goto drop; ++ + if (!net_eq(dev_net(dev), sock_net(sk))) + goto drop; + +@@ -1867,12 +1869,12 @@ static int tpacket_rcv(struct sk_buff *s + BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32); + BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48); + +- if (skb->pkt_type == PACKET_LOOPBACK) +- goto drop; +- + sk = pt->af_packet_priv; + po = pkt_sk(sk); + ++ if (!(po->pkt_type & (1 << skb->pkt_type))) ++ goto drop; ++ + if (!net_eq(dev_net(dev), sock_net(sk))) + goto drop; + +@@ -2807,6 +2809,7 @@ static int packet_create(struct net *net + spin_lock_init(&po->bind_lock); + mutex_init(&po->pg_vec_lock); + po->prot_hook.func = packet_rcv; ++ po->pkt_type = PACKET_MASK_ANY & ~(1 << PACKET_LOOPBACK); + + if (sock->type == SOCK_PACKET) + po->prot_hook.func = packet_rcv_spkt; +@@ -3387,6 +3390,16 @@ packet_setsockopt(struct socket *sock, i + po->xmit = val ? packet_direct_xmit : dev_queue_xmit; + return 0; + } ++ case PACKET_RECV_TYPE: ++ { ++ unsigned int val; ++ if (optlen != sizeof(val)) ++ return -EINVAL; ++ if (copy_from_user(&val, optval, sizeof(val))) ++ return -EFAULT; ++ po->pkt_type = val & ~BIT(PACKET_LOOPBACK); ++ return 0; ++ } + default: + return -ENOPROTOOPT; + } +@@ -3438,6 +3451,13 @@ static int packet_getsockopt(struct sock + case PACKET_VNET_HDR: + val = po->has_vnet_hdr; + break; ++ case PACKET_RECV_TYPE: ++ if (len > sizeof(unsigned int)) ++ len = sizeof(unsigned int); ++ val = po->pkt_type; ++ ++ data = &val; ++ break; + case PACKET_VERSION: + val = po->tp_version; + break; +--- a/net/packet/internal.h ++++ b/net/packet/internal.h +@@ -117,6 +117,7 @@ struct packet_sock { + struct net_device __rcu *cached_dev; + int (*xmit)(struct sk_buff *skb); + struct packet_type prot_hook ____cacheline_aligned_in_smp; ++ unsigned int pkt_type; + }; + + static struct packet_sock *pkt_sk(struct sock *sk) diff --git a/target/linux/generic/patches-3.18/640-bridge_no_eap_forward.patch b/target/linux/generic/patches-3.18/640-bridge_no_eap_forward.patch new file mode 100644 index 0000000..7f38c4a --- /dev/null +++ b/target/linux/generic/patches-3.18/640-bridge_no_eap_forward.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: no EAP forward + +When bridging, do not forward EAP frames to other ports, only deliver +them locally. +Fixes WPA authentication issues with multiples APs that are connected to +each other via bridges. +--- +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -97,7 +97,11 @@ int br_handle_frame_finish(struct sk_buf + + dst = NULL; + +- if (is_broadcast_ether_addr(dest)) { ++ if (skb->protocol == htons(ETH_P_PAE)) { ++ skb2 = skb; ++ /* Do not forward 802.1x/EAP frames */ ++ skb = NULL; ++ } else if (is_broadcast_ether_addr(dest)) { + skb2 = skb; + unicast = false; + } else if (is_multicast_ether_addr(dest)) { diff --git a/target/linux/generic/patches-3.18/641-bridge_always_accept_eap.patch b/target/linux/generic/patches-3.18/641-bridge_always_accept_eap.patch new file mode 100644 index 0000000..7d314ad --- /dev/null +++ b/target/linux/generic/patches-3.18/641-bridge_always_accept_eap.patch @@ -0,0 +1,17 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: always accept EAP + +Allow EAP frames to pass through bridges even in learning state. Fixes +issues with WDS. +--- +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -84,7 +84,7 @@ int br_handle_frame_finish(struct sk_buf + br_multicast_rcv(br, p, skb, vid)) + goto drop; + +- if (p->state == BR_STATE_LEARNING) ++ if ((p->state == BR_STATE_LEARNING) && skb->protocol != htons(ETH_P_PAE)) + goto drop; + + BR_INPUT_SKB_CB(skb)->brdev = br->dev; diff --git a/target/linux/generic/patches-3.18/642-bridge_port_isolate.patch b/target/linux/generic/patches-3.18/642-bridge_port_isolate.patch new file mode 100644 index 0000000..df3a657 --- /dev/null +++ b/target/linux/generic/patches-3.18/642-bridge_port_isolate.patch @@ -0,0 +1,107 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: port isolate + +Isolating individual bridge ports +--- +--- a/net/bridge/br_private.h ++++ b/net/bridge/br_private.h +@@ -172,6 +172,7 @@ struct net_bridge_port + #define BR_FLOOD 0x00000040 + #define BR_AUTO_MASK (BR_FLOOD | BR_LEARNING) + #define BR_PROMISC 0x00000080 ++#define BR_ISOLATE_MODE 0x00000100 + + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + struct bridge_mcast_own_query ip4_own_query; +--- a/net/bridge/br_sysfs_if.c ++++ b/net/bridge/br_sysfs_if.c +@@ -171,6 +171,22 @@ BRPORT_ATTR_FLAG(root_block, BR_ROOT_BLO + BRPORT_ATTR_FLAG(learning, BR_LEARNING); + BRPORT_ATTR_FLAG(unicast_flood, BR_FLOOD); + ++static ssize_t show_isolate_mode(struct net_bridge_port *p, char *buf) ++{ ++ int isolate_mode = (p->flags & BR_ISOLATE_MODE) ? 1 : 0; ++ return sprintf(buf, "%d\n", isolate_mode); ++} ++static ssize_t store_isolate_mode(struct net_bridge_port *p, unsigned long v) ++{ ++ if (v) ++ p->flags |= BR_ISOLATE_MODE; ++ else ++ p->flags &= ~BR_ISOLATE_MODE; ++ return 0; ++} ++static BRPORT_ATTR(isolate_mode, S_IRUGO | S_IWUSR, ++ show_isolate_mode, store_isolate_mode); ++ + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf) + { +@@ -213,6 +229,7 @@ static const struct brport_attribute *br + &brport_attr_multicast_router, + &brport_attr_multicast_fast_leave, + #endif ++ &brport_attr_isolate_mode, + NULL + }; + +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -120,8 +120,8 @@ int br_handle_frame_finish(struct sk_buf + + unicast = false; + br->dev->stats.multicast++; +- } else if ((dst = __br_fdb_get(br, dest, vid)) && +- dst->is_local) { ++ } else if ((p->flags & BR_ISOLATE_MODE) || ++ ((dst = __br_fdb_get(br, dest, vid)) && dst->is_local)) { + skb2 = skb; + /* Do not forward the packet since it's local. */ + skb = NULL; +--- a/net/bridge/br_forward.c ++++ b/net/bridge/br_forward.c +@@ -117,7 +117,7 @@ EXPORT_SYMBOL_GPL(br_deliver); + /* called with rcu_read_lock */ + void br_forward(const struct net_bridge_port *to, struct sk_buff *skb, struct sk_buff *skb0) + { +- if (should_deliver(to, skb)) { ++ if (should_deliver(to, skb) && !(to->flags & BR_ISOLATE_MODE)) { + if (skb0) + deliver_clone(to, skb, __br_forward); + else +@@ -173,7 +173,7 @@ static void br_flood(struct net_bridge * + struct sk_buff *skb0, + void (*__packet_hook)(const struct net_bridge_port *p, + struct sk_buff *skb), +- bool unicast) ++ bool unicast, bool forward) + { + struct net_bridge_port *p; + struct net_bridge_port *prev; +@@ -181,6 +181,8 @@ static void br_flood(struct net_bridge * + prev = NULL; + + list_for_each_entry_rcu(p, &br->port_list, list) { ++ if (forward && (p->flags & BR_ISOLATE_MODE)) ++ continue; + /* Do not flood unicast traffic to ports that turn it off */ + if (unicast && !(p->flags & BR_FLOOD)) + continue; +@@ -207,14 +209,14 @@ out: + /* called with rcu_read_lock */ + void br_flood_deliver(struct net_bridge *br, struct sk_buff *skb, bool unicast) + { +- br_flood(br, skb, NULL, __br_deliver, unicast); ++ br_flood(br, skb, NULL, __br_deliver, unicast, false); + } + + /* called under bridge lock */ + void br_flood_forward(struct net_bridge *br, struct sk_buff *skb, + struct sk_buff *skb2, bool unicast) + { +- br_flood(br, skb, skb2, __br_forward, unicast); ++ br_flood(br, skb, skb2, __br_forward, unicast, true); + } + + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING diff --git a/target/linux/generic/patches-3.18/643-bridge_remove_ipv6_dependency.patch b/target/linux/generic/patches-3.18/643-bridge_remove_ipv6_dependency.patch new file mode 100644 index 0000000..25f49c0 --- /dev/null +++ b/target/linux/generic/patches-3.18/643-bridge_remove_ipv6_dependency.patch @@ -0,0 +1,123 @@ +From: Jonas Gorski +Subject: [PATCH] bridge: remove IPv6 depependency of bridge in 2.6.38+ + +Since 2.6.38 the bridge module has a dependency to IPv6 if IPv6 is +enabled. Since the IPv6 module isn't exactly lightweight and bridge also +only needs a single function from IPv6, it's rather easy to create a +common "lib" module with a RCU pointer to the actual implementation, if +the IPv6 module is loaded (although slightly hackish). + +The codepath seems to be only taken when using IPv6, so there should be +no negative side effects when IPv6 isn't loaded. I did not measure how +big the performance impact is. +--- +--- a/include/net/addrconf.h ++++ b/include/net/addrconf.h +@@ -88,6 +88,12 @@ int ipv6_rcv_saddr_equal(const struct so + void addrconf_join_solict(struct net_device *dev, const struct in6_addr *addr); + void addrconf_leave_solict(struct inet6_dev *idev, const struct in6_addr *addr); + ++extern int (*ipv6_dev_get_saddr_hook)(struct net *net, ++ const struct net_device *dev, ++ const struct in6_addr *daddr, ++ unsigned int prefs, ++ struct in6_addr *saddr); ++ + static inline unsigned long addrconf_timeout_fixup(u32 timeout, + unsigned int unit) + { +--- a/net/bridge/Kconfig ++++ b/net/bridge/Kconfig +@@ -6,7 +6,6 @@ config BRIDGE + tristate "802.1d Ethernet Bridging" + select LLC + select STP +- depends on IPV6 || IPV6=n + ---help--- + If you say Y here, then your Linux box will be able to act as an + Ethernet bridge, which means that the different Ethernet segments it +--- a/net/ipv6/Makefile ++++ b/net/ipv6/Makefile +@@ -45,6 +45,7 @@ obj-y += addrconf_core.o exthdrs_core.o + obj-$(CONFIG_INET) += output_core.o protocol.o $(ipv6-offload) + + obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_hashtables.o ++obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_stubs.o + + ifneq ($(CONFIG_IPV6),) + obj-$(CONFIG_NET_UDP_TUNNEL) += ip6_udp_tunnel.o +--- a/net/ipv6/addrconf.c ++++ b/net/ipv6/addrconf.c +@@ -1317,7 +1317,7 @@ out: + return ret; + } + +-int ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, ++static int __ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, + const struct in6_addr *daddr, unsigned int prefs, + struct in6_addr *saddr) + { +@@ -1442,7 +1442,6 @@ try_nextdev: + in6_ifa_put(hiscore->ifa); + return 0; + } +-EXPORT_SYMBOL(ipv6_dev_get_saddr); + + int __ipv6_get_lladdr(struct inet6_dev *idev, struct in6_addr *addr, + u32 banned_flags) +@@ -5451,6 +5450,9 @@ int __init addrconf_init(void) + + ipv6_addr_label_rtnl_register(); + ++ BUG_ON(ipv6_dev_get_saddr_hook != NULL); ++ rcu_assign_pointer(ipv6_dev_get_saddr_hook, __ipv6_dev_get_saddr); ++ + return 0; + errout: + rtnl_af_unregister(&inet6_ops); +@@ -5470,6 +5472,9 @@ void addrconf_cleanup(void) + struct net_device *dev; + int i; + ++ rcu_assign_pointer(ipv6_dev_get_saddr_hook, NULL); ++ synchronize_rcu(); ++ + unregister_netdevice_notifier(&ipv6_dev_notf); + unregister_pernet_subsys(&addrconf_ops); + ipv6_addr_label_cleanup(); +--- /dev/null ++++ b/net/ipv6/inet6_stubs.c +@@ -0,0 +1,33 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++ ++int (*ipv6_dev_get_saddr_hook)(struct net *net, const struct net_device *dev, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr); ++ ++EXPORT_SYMBOL(ipv6_dev_get_saddr_hook); ++ ++int ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr) ++{ ++ int ret = -EADDRNOTAVAIL; ++ typeof(ipv6_dev_get_saddr_hook) dev_get_saddr; ++ ++ rcu_read_lock(); ++ dev_get_saddr = rcu_dereference(ipv6_dev_get_saddr_hook); ++ ++ if (dev_get_saddr) ++ ret = dev_get_saddr(net, dst_dev, daddr, prefs, saddr); ++ ++ rcu_read_unlock(); ++ return ret; ++} ++EXPORT_SYMBOL(ipv6_dev_get_saddr); ++ diff --git a/target/linux/generic/patches-3.18/645-bridge_multicast_to_unicast.patch b/target/linux/generic/patches-3.18/645-bridge_multicast_to_unicast.patch new file mode 100644 index 0000000..e23a6c4 --- /dev/null +++ b/target/linux/generic/patches-3.18/645-bridge_multicast_to_unicast.patch @@ -0,0 +1,390 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: multicast to unicast + +Implement optinal multicast->unicast conversion for igmp snooping +--- +--- a/net/bridge/br_multicast.c ++++ b/net/bridge/br_multicast.c +@@ -635,7 +635,8 @@ struct net_bridge_port_group *br_multica + struct net_bridge_port *port, + struct br_ip *group, + struct net_bridge_port_group __rcu *next, +- unsigned char state) ++ unsigned char state, ++ const unsigned char *src) + { + struct net_bridge_port_group *p; + +@@ -650,12 +651,33 @@ struct net_bridge_port_group *br_multica + hlist_add_head(&p->mglist, &port->mglist); + setup_timer(&p->timer, br_multicast_port_group_expired, + (unsigned long)p); ++ if ((port->flags & BR_MULTICAST_TO_UCAST) && src) { ++ memcpy(p->eth_addr, src, ETH_ALEN); ++ p->unicast = true; ++ } + return p; + } + ++static bool br_port_group_equal(struct net_bridge_port_group *p, ++ struct net_bridge_port *port, ++ const unsigned char *src) ++{ ++ if (p->port != port) ++ return false; ++ ++ if (!p->unicast) ++ return true; ++ ++ if (!src) ++ return false; ++ ++ return ether_addr_equal(src, p->eth_addr); ++} ++ + static int br_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, +- struct br_ip *group) ++ struct br_ip *group, ++ const unsigned char *src) + { + struct net_bridge_mdb_entry *mp; + struct net_bridge_port_group *p; +@@ -682,13 +704,13 @@ static int br_multicast_add_group(struct + for (pp = &mp->ports; + (p = mlock_dereference(*pp, br)) != NULL; + pp = &p->next) { +- if (p->port == port) ++ if (br_port_group_equal(p, port, src)) + goto found; + if ((unsigned long)p->port < (unsigned long)port) + break; + } + +- p = br_multicast_new_port_group(port, group, *pp, MDB_TEMPORARY); ++ p = br_multicast_new_port_group(port, group, *pp, MDB_TEMPORARY, src); + if (unlikely(!p)) + goto err; + rcu_assign_pointer(*pp, p); +@@ -707,7 +729,7 @@ err: + static int br_ip4_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, + __be32 group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + +@@ -718,14 +740,14 @@ static int br_ip4_multicast_add_group(st + br_group.proto = htons(ETH_P_IP); + br_group.vid = vid; + +- return br_multicast_add_group(br, port, &br_group); ++ return br_multicast_add_group(br, port, &br_group, src); + } + + #if IS_ENABLED(CONFIG_IPV6) + static int br_ip6_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + +@@ -736,7 +758,7 @@ static int br_ip6_multicast_add_group(st + br_group.proto = htons(ETH_P_IPV6); + br_group.vid = vid; + +- return br_multicast_add_group(br, port, &br_group); ++ return br_multicast_add_group(br, port, &br_group, src); + } + #endif + +@@ -965,6 +987,7 @@ static int br_ip4_multicast_igmp3_report + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct igmpv3_report *ih; + struct igmpv3_grec *grec; + int i; +@@ -1008,7 +1031,8 @@ static int br_ip4_multicast_igmp3_report + continue; + } + +- err = br_ip4_multicast_add_group(br, port, group, vid); ++ src = eth_hdr(skb)->h_source; ++ err = br_ip4_multicast_add_group(br, port, group, vid, src); + if (err) + break; + } +@@ -1022,6 +1046,7 @@ static int br_ip6_multicast_mld2_report( + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct icmp6hdr *icmp6h; + struct mld2_grec *grec; + int i; +@@ -1069,8 +1094,9 @@ static int br_ip6_multicast_mld2_report( + continue; + } + ++ src = eth_hdr(skb)->h_source; + err = br_ip6_multicast_add_group(br, port, &grec->grec_mca, +- vid); ++ vid, src); + if (err) + break; + } +@@ -1406,7 +1432,8 @@ br_multicast_leave_group(struct net_brid + struct net_bridge_port *port, + struct br_ip *group, + struct bridge_mcast_other_query *other_query, +- struct bridge_mcast_own_query *own_query) ++ struct bridge_mcast_own_query *own_query, ++ const unsigned char *src) + { + struct net_bridge_mdb_htable *mdb; + struct net_bridge_mdb_entry *mp; +@@ -1456,7 +1483,7 @@ br_multicast_leave_group(struct net_brid + for (pp = &mp->ports; + (p = mlock_dereference(*pp, br)) != NULL; + pp = &p->next) { +- if (p->port != port) ++ if (!br_port_group_equal(p, port, src)) + continue; + + rcu_assign_pointer(*pp, p->next); +@@ -1490,7 +1517,7 @@ br_multicast_leave_group(struct net_brid + for (p = mlock_dereference(mp->ports, br); + p != NULL; + p = mlock_dereference(p->next, br)) { +- if (p->port != port) ++ if (!br_port_group_equal(p, port, src)) + continue; + + if (!hlist_unhashed(&p->mglist) && +@@ -1508,8 +1535,8 @@ out: + + static void br_ip4_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, +- __be32 group, +- __u16 vid) ++ __be32 group, __u16 vid, ++ const unsigned char *src) + { + struct br_ip br_group; + struct bridge_mcast_own_query *own_query; +@@ -1524,14 +1551,14 @@ static void br_ip4_multicast_leave_group + br_group.vid = vid; + + br_multicast_leave_group(br, port, &br_group, &br->ip4_other_query, +- own_query); ++ own_query, src); + } + + #if IS_ENABLED(CONFIG_IPV6) + static void br_ip6_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + struct bridge_mcast_own_query *own_query; +@@ -1546,7 +1573,7 @@ static void br_ip6_multicast_leave_group + br_group.vid = vid; + + br_multicast_leave_group(br, port, &br_group, &br->ip6_other_query, +- own_query); ++ own_query, src); + } + #endif + +@@ -1555,6 +1582,7 @@ static int br_multicast_ipv4_rcv(struct + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct sk_buff *skb2 = skb; + const struct iphdr *iph; + struct igmphdr *ih; +@@ -1628,7 +1656,8 @@ static int br_multicast_ipv4_rcv(struct + case IGMP_HOST_MEMBERSHIP_REPORT: + case IGMPV2_HOST_MEMBERSHIP_REPORT: + BR_INPUT_SKB_CB(skb)->mrouters_only = 1; +- err = br_ip4_multicast_add_group(br, port, ih->group, vid); ++ src = eth_hdr(skb)->h_source; ++ err = br_ip4_multicast_add_group(br, port, ih->group, vid, src); + break; + case IGMPV3_HOST_MEMBERSHIP_REPORT: + err = br_ip4_multicast_igmp3_report(br, port, skb2, vid); +@@ -1637,7 +1666,8 @@ static int br_multicast_ipv4_rcv(struct + err = br_ip4_multicast_query(br, port, skb2, vid); + break; + case IGMP_HOST_LEAVE_MESSAGE: +- br_ip4_multicast_leave_group(br, port, ih->group, vid); ++ src = eth_hdr(skb)->h_source; ++ br_ip4_multicast_leave_group(br, port, ih->group, vid, src); + break; + } + +@@ -1655,6 +1685,7 @@ static int br_multicast_ipv6_rcv(struct + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct sk_buff *skb2; + const struct ipv6hdr *ip6h; + u8 icmp6_type; +@@ -1764,7 +1795,9 @@ static int br_multicast_ipv6_rcv(struct + } + mld = (struct mld_msg *)skb_transport_header(skb2); + BR_INPUT_SKB_CB(skb)->mrouters_only = 1; +- err = br_ip6_multicast_add_group(br, port, &mld->mld_mca, vid); ++ src = eth_hdr(skb)->h_source; ++ err = br_ip6_multicast_add_group(br, port, &mld->mld_mca, vid, ++ src); + break; + } + case ICMPV6_MLD2_REPORT: +@@ -1781,7 +1814,8 @@ static int br_multicast_ipv6_rcv(struct + goto out; + } + mld = (struct mld_msg *)skb_transport_header(skb2); +- br_ip6_multicast_leave_group(br, port, &mld->mld_mca, vid); ++ src = eth_hdr(skb)->h_source; ++ br_ip6_multicast_leave_group(br, port, &mld->mld_mca, vid, src); + } + } + +--- a/net/bridge/br_private.h ++++ b/net/bridge/br_private.h +@@ -112,6 +112,9 @@ struct net_bridge_port_group { + struct timer_list timer; + struct br_ip addr; + unsigned char state; ++ ++ unsigned char eth_addr[ETH_ALEN]; ++ bool unicast; + }; + + struct net_bridge_mdb_entry +@@ -173,6 +176,7 @@ struct net_bridge_port + #define BR_AUTO_MASK (BR_FLOOD | BR_LEARNING) + #define BR_PROMISC 0x00000080 + #define BR_ISOLATE_MODE 0x00000100 ++#define BR_MULTICAST_TO_UCAST 0x00000200 + + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + struct bridge_mcast_own_query ip4_own_query; +@@ -485,7 +489,8 @@ void br_multicast_free_pg(struct rcu_hea + struct net_bridge_port_group * + br_multicast_new_port_group(struct net_bridge_port *port, struct br_ip *group, + struct net_bridge_port_group __rcu *next, +- unsigned char state); ++ unsigned char state, ++ const unsigned char *src); + void br_mdb_init(void); + void br_mdb_uninit(void); + void br_mdb_notify(struct net_device *dev, struct net_bridge_port *port, +--- a/net/bridge/br_mdb.c ++++ b/net/bridge/br_mdb.c +@@ -342,7 +342,7 @@ static int br_mdb_add_group(struct net_b + break; + } + +- p = br_multicast_new_port_group(port, group, *pp, state); ++ p = br_multicast_new_port_group(port, group, *pp, state, NULL); + if (unlikely(!p)) + return -ENOMEM; + rcu_assign_pointer(*pp, p); +--- a/net/bridge/br_forward.c ++++ b/net/bridge/br_forward.c +@@ -168,6 +168,34 @@ out: + return p; + } + ++static struct net_bridge_port *maybe_deliver_addr( ++ struct net_bridge_port *prev, struct net_bridge_port *p, ++ struct sk_buff *skb, const unsigned char *addr, ++ void (*__packet_hook)(const struct net_bridge_port *p, ++ struct sk_buff *skb)) ++{ ++ struct net_device *dev = BR_INPUT_SKB_CB(skb)->brdev; ++ const unsigned char *src = eth_hdr(skb)->h_source; ++ ++ if (!should_deliver(p, skb)) ++ return prev; ++ ++ /* Even with hairpin, no soliloquies - prevent breaking IPv6 DAD */ ++ if (skb->dev == p->dev && ether_addr_equal(src, addr)) ++ return prev; ++ ++ skb = skb_copy(skb, GFP_ATOMIC); ++ if (!skb) { ++ dev->stats.tx_dropped++; ++ return prev; ++ } ++ ++ memcpy(eth_hdr(skb)->h_dest, addr, ETH_ALEN); ++ __packet_hook(p, skb); ++ ++ return prev; ++} ++ + /* called under bridge lock */ + static void br_flood(struct net_bridge *br, struct sk_buff *skb, + struct sk_buff *skb0, +@@ -232,6 +260,7 @@ static void br_multicast_flood(struct ne + struct net_bridge_port *prev = NULL; + struct net_bridge_port_group *p; + struct hlist_node *rp; ++ const unsigned char *addr; + + rp = rcu_dereference(hlist_first_rcu(&br->router_list)); + p = mdst ? rcu_dereference(mdst->ports) : NULL; +@@ -242,10 +271,19 @@ static void br_multicast_flood(struct ne + rport = rp ? hlist_entry(rp, struct net_bridge_port, rlist) : + NULL; + +- port = (unsigned long)lport > (unsigned long)rport ? +- lport : rport; +- +- prev = maybe_deliver(prev, port, skb, __packet_hook); ++ if ((unsigned long)lport > (unsigned long)rport) { ++ port = lport; ++ addr = p->unicast ? p->eth_addr : NULL; ++ } else { ++ port = rport; ++ addr = NULL; ++ } ++ ++ if (addr) ++ prev = maybe_deliver_addr(prev, port, skb, addr, ++ __packet_hook); ++ else ++ prev = maybe_deliver(prev, port, skb, __packet_hook); + if (IS_ERR(prev)) + goto out; + +--- a/net/bridge/br_sysfs_if.c ++++ b/net/bridge/br_sysfs_if.c +@@ -202,6 +202,7 @@ static BRPORT_ATTR(multicast_router, S_I + store_multicast_router); + + BRPORT_ATTR_FLAG(multicast_fast_leave, BR_MULTICAST_FAST_LEAVE); ++BRPORT_ATTR_FLAG(multicast_to_unicast, BR_MULTICAST_TO_UCAST); + #endif + + static const struct brport_attribute *brport_attrs[] = { +@@ -228,6 +229,7 @@ static const struct brport_attribute *br + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + &brport_attr_multicast_router, + &brport_attr_multicast_fast_leave, ++ &brport_attr_multicast_to_unicast, + #endif + &brport_attr_isolate_mode, + NULL diff --git a/target/linux/generic/patches-3.18/650-pppoe_header_pad.patch b/target/linux/generic/patches-3.18/650-pppoe_header_pad.patch new file mode 100644 index 0000000..4b623fa --- /dev/null +++ b/target/linux/generic/patches-3.18/650-pppoe_header_pad.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -868,7 +868,7 @@ static int pppoe_sendmsg(struct kiocb *i + goto end; + + +- skb = sock_wmalloc(sk, total_len + dev->hard_header_len + 32, ++ skb = sock_wmalloc(sk, total_len + dev->hard_header_len + 32 + NET_SKB_PAD, + 0, GFP_KERNEL); + if (!skb) { + error = -ENOMEM; +@@ -876,7 +876,7 @@ static int pppoe_sendmsg(struct kiocb *i + } + + /* Reserve space for headers. */ +- skb_reserve(skb, dev->hard_header_len); ++ skb_reserve(skb, dev->hard_header_len + NET_SKB_PAD); + skb_reset_network_header(skb); + + skb->dev = dev; diff --git a/target/linux/generic/patches-3.18/651-wireless_mesh_header.patch b/target/linux/generic/patches-3.18/651-wireless_mesh_header.patch new file mode 100644 index 0000000..16da5cd --- /dev/null +++ b/target/linux/generic/patches-3.18/651-wireless_mesh_header.patch @@ -0,0 +1,11 @@ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -130,7 +130,7 @@ static inline bool dev_xmit_complete(int + */ + + #if defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) +-# if defined(CONFIG_MAC80211_MESH) ++# if 1 || defined(CONFIG_MAC80211_MESH) + # define LL_MAX_HEADER 128 + # else + # define LL_MAX_HEADER 96 diff --git a/target/linux/generic/patches-3.18/653-disable_netlink_trim.patch b/target/linux/generic/patches-3.18/653-disable_netlink_trim.patch new file mode 100644 index 0000000..b38b87b --- /dev/null +++ b/target/linux/generic/patches-3.18/653-disable_netlink_trim.patch @@ -0,0 +1,30 @@ +--- a/net/netlink/af_netlink.c ++++ b/net/netlink/af_netlink.c +@@ -1721,27 +1721,7 @@ void netlink_detachskb(struct sock *sk, + + static struct sk_buff *netlink_trim(struct sk_buff *skb, gfp_t allocation) + { +- int delta; +- + WARN_ON(skb->sk != NULL); +- if (netlink_skb_is_mmaped(skb)) +- return skb; +- +- delta = skb->end - skb->tail; +- if (is_vmalloc_addr(skb->head) || delta * 2 < skb->truesize) +- return skb; +- +- if (skb_shared(skb)) { +- struct sk_buff *nskb = skb_clone(skb, allocation); +- if (!nskb) +- return skb; +- consume_skb(skb); +- skb = nskb; +- } +- +- if (!pskb_expand_head(skb, 0, -delta, allocation)) +- skb->truesize -= delta; +- + return skb; + } + diff --git a/target/linux/generic/patches-3.18/655-increase_skb_pad.patch b/target/linux/generic/patches-3.18/655-increase_skb_pad.patch new file mode 100644 index 0000000..19344cc --- /dev/null +++ b/target/linux/generic/patches-3.18/655-increase_skb_pad.patch @@ -0,0 +1,11 @@ +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2023,7 +2023,7 @@ static inline int pskb_network_may_pull( + * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8) + */ + #ifndef NET_SKB_PAD +-#define NET_SKB_PAD max(32, L1_CACHE_BYTES) ++#define NET_SKB_PAD max(64, L1_CACHE_BYTES) + #endif + + int ___pskb_trim(struct sk_buff *skb, unsigned int len); diff --git a/target/linux/generic/patches-3.18/656-skb_reduce_truesize-helper.patch b/target/linux/generic/patches-3.18/656-skb_reduce_truesize-helper.patch new file mode 100644 index 0000000..b326a8b --- /dev/null +++ b/target/linux/generic/patches-3.18/656-skb_reduce_truesize-helper.patch @@ -0,0 +1,41 @@ +From 4593a806e31119c5bd3faa00c7210ad862d515af Mon Sep 17 00:00:00 2001 +From: Dave Taht +Date: Mon, 31 Dec 2012 10:02:21 -0800 +Subject: [PATCH 3/7] skb_reduce_truesize: helper function for shrinking skbs + whenever needed + +On embedded devices in particular, large queues of small packets from the rx +path with a large truesize can exist. Reducing their size can reduce +memory pressure. skb_reduce_truesize is a helper function for doing this, +when needed. +--- + include/linux/skbuff.h | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2068,6 +2068,24 @@ static inline void pskb_trim_unique(stru + BUG_ON(err); + } + ++/* ++ * Caller wants to reduce memory needs before queueing skb ++ * The (expensive) copy should not be be done in fast path. ++ */ ++static inline struct sk_buff *skb_reduce_truesize(struct sk_buff *skb) ++{ ++ if (skb->truesize > 2 * SKB_TRUESIZE(skb->len)) { ++ struct sk_buff *nskb; ++ nskb = skb_copy_expand(skb, skb_headroom(skb), 0, ++ GFP_ATOMIC | __GFP_NOWARN); ++ if (nskb) { ++ __kfree_skb(skb); ++ skb = nskb; ++ } ++ } ++ return skb; ++} ++ + /** + * skb_orphan - orphan a buffer + * @skb: buffer to orphan diff --git a/target/linux/generic/patches-3.18/657-qdisc_reduce_truesize.patch b/target/linux/generic/patches-3.18/657-qdisc_reduce_truesize.patch new file mode 100644 index 0000000..6777eec --- /dev/null +++ b/target/linux/generic/patches-3.18/657-qdisc_reduce_truesize.patch @@ -0,0 +1,63 @@ +From bc9fec2f87d57bdbff30d296605e24504513f65c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Dave=20T=C3=A4ht?= +Date: Mon, 17 Sep 2012 19:20:22 -0700 +Subject: [PATCH 4/7] net: add skb_reduce_truesize support to common qdiscs + +Reduce skb size under load when queues begin to fill on the +commont qdiscs. +--- + net/sched/sch_codel.c | 2 ++ + net/sched/sch_fifo.c | 12 ++++++++---- + net/sched/sch_fq_codel.c | 2 ++ + 3 files changed, 12 insertions(+), 4 deletions(-) + +--- a/net/sched/sch_codel.c ++++ b/net/sched/sch_codel.c +@@ -96,6 +96,8 @@ static int codel_qdisc_enqueue(struct sk + struct codel_sched_data *q; + + if (likely(qdisc_qlen(sch) < sch->limit)) { ++ if(qdisc_qlen(sch) > 128) ++ skb = skb_reduce_truesize(skb); + codel_set_enqueue_time(skb); + return qdisc_enqueue_tail(skb, sch); + } +--- a/net/sched/sch_fifo.c ++++ b/net/sched/sch_fifo.c +@@ -29,17 +29,21 @@ static int bfifo_enqueue(struct sk_buff + + static int pfifo_enqueue(struct sk_buff *skb, struct Qdisc *sch) + { +- if (likely(skb_queue_len(&sch->q) < sch->limit)) ++ if (likely(skb_queue_len(&sch->q) < sch->limit)) { ++ if (skb_queue_len(&sch->q) > 128) ++ skb = skb_reduce_truesize(skb); + return qdisc_enqueue_tail(skb, sch); +- ++ } + return qdisc_reshape_fail(skb, sch); + } + + static int pfifo_tail_enqueue(struct sk_buff *skb, struct Qdisc *sch) + { +- if (likely(skb_queue_len(&sch->q) < sch->limit)) ++ if (likely(skb_queue_len(&sch->q) < sch->limit)) { ++ if (skb_queue_len(&sch->q) > 128) ++ skb = skb_reduce_truesize(skb); + return qdisc_enqueue_tail(skb, sch); +- ++ } + /* queue full, remove one skb to fulfill the limit */ + __qdisc_queue_drop_head(sch, &sch->q); + qdisc_qstats_drop(sch); +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -185,6 +185,8 @@ static int fq_codel_enqueue(struct sk_bu + return ret; + } + idx--; ++ if (sch->q.qlen > 128) ++ skb = skb_reduce_truesize(skb); + + codel_set_enqueue_time(skb); + flow = &q->flows[idx]; diff --git a/target/linux/generic/patches-3.18/660-fq_codel_defaults.patch b/target/linux/generic/patches-3.18/660-fq_codel_defaults.patch new file mode 100644 index 0000000..f7f4659 --- /dev/null +++ b/target/linux/generic/patches-3.18/660-fq_codel_defaults.patch @@ -0,0 +1,14 @@ +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -387,9 +387,9 @@ static int fq_codel_init(struct Qdisc *s + struct fq_codel_sched_data *q = qdisc_priv(sch); + int i; + +- sch->limit = 10*1024; ++ sch->limit = 1024; + q->flows_cnt = 1024; +- q->quantum = psched_mtu(qdisc_dev(sch)); ++ q->quantum = 300; + q->perturbation = prandom_u32(); + INIT_LIST_HEAD(&q->new_flows); + INIT_LIST_HEAD(&q->old_flows); diff --git a/target/linux/generic/patches-3.18/661-fq_codel_keep_dropped_stats.patch b/target/linux/generic/patches-3.18/661-fq_codel_keep_dropped_stats.patch new file mode 100644 index 0000000..45a8d68 --- /dev/null +++ b/target/linux/generic/patches-3.18/661-fq_codel_keep_dropped_stats.patch @@ -0,0 +1,10 @@ +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -198,7 +198,6 @@ static int fq_codel_enqueue(struct sk_bu + list_add_tail(&flow->flowchain, &q->new_flows); + q->new_flow_count++; + flow->deficit = q->quantum; +- flow->dropped = 0; + } + if (++sch->q.qlen <= sch->limit) + return NET_XMIT_SUCCESS; diff --git a/target/linux/generic/patches-3.18/662-use_fq_codel_by_default.patch b/target/linux/generic/patches-3.18/662-use_fq_codel_by_default.patch new file mode 100644 index 0000000..ba7c384 --- /dev/null +++ b/target/linux/generic/patches-3.18/662-use_fq_codel_by_default.patch @@ -0,0 +1,95 @@ +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -3,8 +3,9 @@ + # + + menuconfig NET_SCHED +- bool "QoS and/or fair queueing" ++ def_bool y + select NET_SCH_FIFO ++ select NET_SCH_FQ_CODEL + ---help--- + When the kernel has several packets to send out over a network + device, it has to decide which ones to send first, which ones to +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -592,7 +592,7 @@ static const struct Qdisc_class_ops fq_c + .walk = fq_codel_walk, + }; + +-static struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = { ++struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = { + .cl_ops = &fq_codel_class_ops, + .id = "fq_codel", + .priv_size = sizeof(struct fq_codel_sched_data), +@@ -608,6 +608,7 @@ static struct Qdisc_ops fq_codel_qdisc_o + .dump_stats = fq_codel_dump_stats, + .owner = THIS_MODULE, + }; ++EXPORT_SYMBOL(fq_codel_qdisc_ops); + + static int __init fq_codel_module_init(void) + { +--- a/include/net/sch_generic.h ++++ b/include/net/sch_generic.h +@@ -341,6 +341,7 @@ extern struct Qdisc noop_qdisc; + extern struct Qdisc_ops noop_qdisc_ops; + extern struct Qdisc_ops pfifo_fast_ops; + extern struct Qdisc_ops mq_qdisc_ops; ++extern struct Qdisc_ops fq_codel_qdisc_ops; + extern const struct Qdisc_ops *default_qdisc_ops; + + struct Qdisc_class_common { +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -31,7 +31,7 @@ + #include + + /* Qdisc to use by default */ +-const struct Qdisc_ops *default_qdisc_ops = &pfifo_fast_ops; ++const struct Qdisc_ops *default_qdisc_ops = &fq_codel_qdisc_ops; + EXPORT_SYMBOL(default_qdisc_ops); + + /* Main transmission queue. */ +@@ -737,7 +737,7 @@ static void attach_one_default_qdisc(str + + if (dev->tx_queue_len) { + qdisc = qdisc_create_dflt(dev_queue, +- default_qdisc_ops, TC_H_ROOT); ++ &fq_codel_qdisc_ops, TC_H_ROOT); + if (!qdisc) { + netdev_info(dev, "activation failed\n"); + return; +--- a/net/sched/sch_mq.c ++++ b/net/sched/sch_mq.c +@@ -57,7 +57,7 @@ static int mq_init(struct Qdisc *sch, st + + for (ntx = 0; ntx < dev->num_tx_queues; ntx++) { + dev_queue = netdev_get_tx_queue(dev, ntx); +- qdisc = qdisc_create_dflt(dev_queue, default_qdisc_ops, ++ qdisc = qdisc_create_dflt(dev_queue, &fq_codel_qdisc_ops, + TC_H_MAKE(TC_H_MAJ(sch->handle), + TC_H_MIN(ntx + 1))); + if (qdisc == NULL) +--- a/net/sched/sch_mqprio.c ++++ b/net/sched/sch_mqprio.c +@@ -124,7 +124,7 @@ static int mqprio_init(struct Qdisc *sch + + for (i = 0; i < dev->num_tx_queues; i++) { + dev_queue = netdev_get_tx_queue(dev, i); +- qdisc = qdisc_create_dflt(dev_queue, default_qdisc_ops, ++ qdisc = qdisc_create_dflt(dev_queue, &fq_codel_qdisc_ops, + TC_H_MAKE(TC_H_MAJ(sch->handle), + TC_H_MIN(i + 1))); + if (qdisc == NULL) { +--- a/net/sched/sch_api.c ++++ b/net/sched/sch_api.c +@@ -1947,7 +1947,7 @@ static int __init pktsched_init(void) + return err; + } + +- register_qdisc(&pfifo_fast_ops); ++ register_qdisc(&fq_codel_qdisc_ops); + register_qdisc(&pfifo_qdisc_ops); + register_qdisc(&bfifo_qdisc_ops); + register_qdisc(&pfifo_head_drop_qdisc_ops); diff --git a/target/linux/generic/patches-3.18/663-remove_pfifo_fast.patch b/target/linux/generic/patches-3.18/663-remove_pfifo_fast.patch new file mode 100644 index 0000000..5b26ca3 --- /dev/null +++ b/target/linux/generic/patches-3.18/663-remove_pfifo_fast.patch @@ -0,0 +1,143 @@ +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -442,140 +442,6 @@ static struct Qdisc noqueue_qdisc = { + .busylock = __SPIN_LOCK_UNLOCKED(noqueue_qdisc.busylock), + }; + +- +-static const u8 prio2band[TC_PRIO_MAX + 1] = { +- 1, 2, 2, 2, 1, 2, 0, 0 , 1, 1, 1, 1, 1, 1, 1, 1 +-}; +- +-/* 3-band FIFO queue: old style, but should be a bit faster than +- generic prio+fifo combination. +- */ +- +-#define PFIFO_FAST_BANDS 3 +- +-/* +- * Private data for a pfifo_fast scheduler containing: +- * - queues for the three band +- * - bitmap indicating which of the bands contain skbs +- */ +-struct pfifo_fast_priv { +- u32 bitmap; +- struct sk_buff_head q[PFIFO_FAST_BANDS]; +-}; +- +-/* +- * Convert a bitmap to the first band number where an skb is queued, where: +- * bitmap=0 means there are no skbs on any band. +- * bitmap=1 means there is an skb on band 0. +- * bitmap=7 means there are skbs on all 3 bands, etc. +- */ +-static const int bitmap2band[] = {-1, 0, 1, 0, 2, 0, 1, 0}; +- +-static inline struct sk_buff_head *band2list(struct pfifo_fast_priv *priv, +- int band) +-{ +- return priv->q + band; +-} +- +-static int pfifo_fast_enqueue(struct sk_buff *skb, struct Qdisc *qdisc) +-{ +- if (skb_queue_len(&qdisc->q) < qdisc_dev(qdisc)->tx_queue_len) { +- int band = prio2band[skb->priority & TC_PRIO_MAX]; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- struct sk_buff_head *list = band2list(priv, band); +- +- priv->bitmap |= (1 << band); +- qdisc->q.qlen++; +- return __qdisc_enqueue_tail(skb, qdisc, list); +- } +- +- return qdisc_drop(skb, qdisc); +-} +- +-static struct sk_buff *pfifo_fast_dequeue(struct Qdisc *qdisc) +-{ +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- int band = bitmap2band[priv->bitmap]; +- +- if (likely(band >= 0)) { +- struct sk_buff_head *list = band2list(priv, band); +- struct sk_buff *skb = __qdisc_dequeue_head(qdisc, list); +- +- qdisc->q.qlen--; +- if (skb_queue_empty(list)) +- priv->bitmap &= ~(1 << band); +- +- return skb; +- } +- +- return NULL; +-} +- +-static struct sk_buff *pfifo_fast_peek(struct Qdisc *qdisc) +-{ +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- int band = bitmap2band[priv->bitmap]; +- +- if (band >= 0) { +- struct sk_buff_head *list = band2list(priv, band); +- +- return skb_peek(list); +- } +- +- return NULL; +-} +- +-static void pfifo_fast_reset(struct Qdisc *qdisc) +-{ +- int prio; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- +- for (prio = 0; prio < PFIFO_FAST_BANDS; prio++) +- __qdisc_reset_queue(qdisc, band2list(priv, prio)); +- +- priv->bitmap = 0; +- qdisc->qstats.backlog = 0; +- qdisc->q.qlen = 0; +-} +- +-static int pfifo_fast_dump(struct Qdisc *qdisc, struct sk_buff *skb) +-{ +- struct tc_prio_qopt opt = { .bands = PFIFO_FAST_BANDS }; +- +- memcpy(&opt.priomap, prio2band, TC_PRIO_MAX + 1); +- if (nla_put(skb, TCA_OPTIONS, sizeof(opt), &opt)) +- goto nla_put_failure; +- return skb->len; +- +-nla_put_failure: +- return -1; +-} +- +-static int pfifo_fast_init(struct Qdisc *qdisc, struct nlattr *opt) +-{ +- int prio; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- +- for (prio = 0; prio < PFIFO_FAST_BANDS; prio++) +- __skb_queue_head_init(band2list(priv, prio)); +- +- /* Can by-pass the queue discipline */ +- qdisc->flags |= TCQ_F_CAN_BYPASS; +- return 0; +-} +- +-struct Qdisc_ops pfifo_fast_ops __read_mostly = { +- .id = "pfifo_fast", +- .priv_size = sizeof(struct pfifo_fast_priv), +- .enqueue = pfifo_fast_enqueue, +- .dequeue = pfifo_fast_dequeue, +- .peek = pfifo_fast_peek, +- .init = pfifo_fast_init, +- .reset = pfifo_fast_reset, +- .dump = pfifo_fast_dump, +- .owner = THIS_MODULE, +-}; +- + static struct lock_class_key qdisc_tx_busylock; + + struct Qdisc *qdisc_alloc(struct netdev_queue *dev_queue, diff --git a/target/linux/generic/patches-3.18/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/patches-3.18/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch new file mode 100644 index 0000000..000665f --- /dev/null +++ b/target/linux/generic/patches-3.18/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch @@ -0,0 +1,481 @@ +From 775d6fe74d1eaec2ba387535b068dde2dc89de9e Mon Sep 17 00:00:00 2001 +From: Steven Barth +Date: Thu, 22 May 2014 09:49:05 +0200 +Subject: [PATCH] Add support for MAP-E FMRs (mesh mode) + +MAP-E FMRs (draft-ietf-softwire-map-10) are rules for IPv4-communication +between MAP CEs (mesh mode) without the need to forward such data to a +border relay. This is similar to how 6rd works but for IPv4 over IPv6. + +Signed-off-by: Steven Barth +--- + include/net/ip6_tunnel.h | 13 ++ + include/uapi/linux/if_tunnel.h | 13 ++ + net/ipv6/ip6_tunnel.c | 276 +++++++++++++++++++++++++++++++++++++++-- + 3 files changed, 291 insertions(+), 11 deletions(-) + +--- a/include/net/ip6_tunnel.h ++++ b/include/net/ip6_tunnel.h +@@ -15,6 +15,18 @@ + /* determine capability on a per-packet basis */ + #define IP6_TNL_F_CAP_PER_PACKET 0x40000 + ++/* IPv6 tunnel FMR */ ++struct __ip6_tnl_fmr { ++ struct __ip6_tnl_fmr *next; /* next fmr in list */ ++ struct in6_addr ip6_prefix; ++ struct in_addr ip4_prefix; ++ ++ __u8 ip6_prefix_len; ++ __u8 ip4_prefix_len; ++ __u8 ea_len; ++ __u8 offset; ++}; ++ + struct __ip6_tnl_parm { + char name[IFNAMSIZ]; /* name of tunnel device */ + int link; /* ifindex of underlying L2 interface */ +@@ -25,6 +37,7 @@ struct __ip6_tnl_parm { + __u32 flags; /* tunnel flags */ + struct in6_addr laddr; /* local tunnel end-point address */ + struct in6_addr raddr; /* remote tunnel end-point address */ ++ struct __ip6_tnl_fmr *fmrs; /* FMRs */ + + __be16 i_flags; + __be16 o_flags; +--- a/include/uapi/linux/if_tunnel.h ++++ b/include/uapi/linux/if_tunnel.h +@@ -57,10 +57,23 @@ enum { + IFLA_IPTUN_ENCAP_FLAGS, + IFLA_IPTUN_ENCAP_SPORT, + IFLA_IPTUN_ENCAP_DPORT, ++ IFLA_IPTUN_FMRS, + __IFLA_IPTUN_MAX, + }; + #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) + ++enum { ++ IFLA_IPTUN_FMR_UNSPEC, ++ IFLA_IPTUN_FMR_IP6_PREFIX, ++ IFLA_IPTUN_FMR_IP4_PREFIX, ++ IFLA_IPTUN_FMR_IP6_PREFIX_LEN, ++ IFLA_IPTUN_FMR_IP4_PREFIX_LEN, ++ IFLA_IPTUN_FMR_EA_LEN, ++ IFLA_IPTUN_FMR_OFFSET, ++ __IFLA_IPTUN_FMR_MAX, ++}; ++#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1) ++ + enum tunnel_encap_types { + TUNNEL_ENCAP_NONE, + TUNNEL_ENCAP_FOU, +--- a/net/ipv6/ip6_tunnel.c ++++ b/net/ipv6/ip6_tunnel.c +@@ -16,6 +16,8 @@ + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * ++ * Changes: ++ * Steven Barth : MAP-E FMR support + */ + + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +@@ -77,11 +79,9 @@ static bool log_ecn_error = true; + module_param(log_ecn_error, bool, 0644); + MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN"); + +-static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2) ++static u32 HASH(const struct in6_addr *addr) + { +- u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2); +- +- return hash_32(hash, HASH_SIZE_SHIFT); ++ return hash_32(ipv6_addr_hash(addr), HASH_SIZE_SHIFT); + } + + static int ip6_tnl_dev_init(struct net_device *dev); +@@ -180,15 +180,24 @@ EXPORT_SYMBOL_GPL(ip6_tnl_dst_store); + static struct ip6_tnl * + ip6_tnl_lookup(struct net *net, const struct in6_addr *remote, const struct in6_addr *local) + { +- unsigned int hash = HASH(remote, local); ++ unsigned int hash = HASH(local); + struct ip6_tnl *t; + struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); ++ struct __ip6_tnl_fmr *fmr; + + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { +- if (ipv6_addr_equal(local, &t->parms.laddr) && +- ipv6_addr_equal(remote, &t->parms.raddr) && +- (t->dev->flags & IFF_UP)) ++ if (!ipv6_addr_equal(local, &t->parms.laddr) || ++ !(t->dev->flags & IFF_UP)) ++ continue; ++ ++ if (ipv6_addr_equal(remote, &t->parms.raddr)) + return t; ++ ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { ++ if (ipv6_prefix_equal(remote, &fmr->ip6_prefix, ++ fmr->ip6_prefix_len)) ++ return t; ++ } + } + t = rcu_dereference(ip6n->tnls_wc[0]); + if (t && (t->dev->flags & IFF_UP)) +@@ -218,7 +227,7 @@ ip6_tnl_bucket(struct ip6_tnl_net *ip6n, + + if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) { + prio = 1; +- h = HASH(remote, local); ++ h = HASH(local); + } + return &ip6n->tnls[prio][h]; + } +@@ -388,6 +397,12 @@ ip6_tnl_dev_uninit(struct net_device *de + struct net *net = t->net; + struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + ++ while (t->parms.fmrs) { ++ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; ++ kfree(t->parms.fmrs); ++ t->parms.fmrs = next; ++ } ++ + if (dev == ip6n->fb_tnl_dev) + RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL); + else +@@ -771,6 +786,108 @@ int ip6_tnl_rcv_ctl(struct ip6_tnl *t, + } + EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl); + ++ ++/** ++ * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR ++ * @dest: destination IPv6 address buffer ++ * @skb: received socket buffer ++ * @fmr: MAP FMR ++ * @xmit: Calculate for xmit or rcv ++ **/ ++static void ip4ip6_fmr_calc(struct in6_addr *dest, ++ const struct iphdr *iph, const uint8_t *end, ++ const struct __ip6_tnl_fmr *fmr, bool xmit) ++{ ++ int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len); ++ u8 *portp = NULL; ++ bool use_dest_addr; ++ const struct iphdr *dsth = iph; ++ ++ if ((u8*)dsth >= end) ++ return; ++ ++ /* find significant IP header */ ++ if (iph->protocol == IPPROTO_ICMP) { ++ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); ++ if (ih && ((u8*)&ih[1]) <= end && ( ++ ih->type == ICMP_DEST_UNREACH || ++ ih->type == ICMP_SOURCE_QUENCH || ++ ih->type == ICMP_TIME_EXCEEDED || ++ ih->type == ICMP_PARAMETERPROB || ++ ih->type == ICMP_REDIRECT)) ++ dsth = (const struct iphdr*)&ih[1]; ++ } ++ ++ /* in xmit-path use dest port by default and source port only if ++ this is an ICMP reply to something else; vice versa in rcv-path */ ++ use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph); ++ ++ /* get dst port */ ++ if (((u8*)&dsth[1]) <= end && ( ++ dsth->protocol == IPPROTO_UDP || ++ dsth->protocol == IPPROTO_TCP || ++ dsth->protocol == IPPROTO_SCTP || ++ dsth->protocol == IPPROTO_DCCP)) { ++ /* for UDP, TCP, SCTP and DCCP source and dest port ++ follow IPv4 header directly */ ++ portp = ((u8*)dsth) + dsth->ihl * 4; ++ ++ if (use_dest_addr) ++ portp += sizeof(u16); ++ } else if (iph->protocol == IPPROTO_ICMP) { ++ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); ++ ++ /* use icmp identifier as port */ ++ if (((u8*)&ih) <= end && ( ++ (use_dest_addr && ( ++ ih->type == ICMP_ECHOREPLY || ++ ih->type == ICMP_TIMESTAMPREPLY || ++ ih->type == ICMP_INFO_REPLY || ++ ih->type == ICMP_ADDRESSREPLY)) || ++ (!use_dest_addr && ( ++ ih->type == ICMP_ECHO || ++ ih->type == ICMP_TIMESTAMP || ++ ih->type == ICMP_INFO_REQUEST || ++ ih->type == ICMP_ADDRESS) ++ ))) ++ portp = (u8*)&ih->un.echo.id; ++ } ++ ++ if ((portp && &portp[2] <= end) || psidlen == 0) { ++ int frombyte = fmr->ip6_prefix_len / 8; ++ int fromrem = fmr->ip6_prefix_len % 8; ++ int bytes = sizeof(struct in6_addr) - frombyte; ++ const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr; ++ u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len); ++ u64 t = 0; ++ ++ /* extract PSID from port and add it to eabits */ ++ u16 psidbits = 0; ++ if (psidlen > 0) { ++ psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]); ++ psidbits >>= 16 - psidlen - fmr->offset; ++ psidbits = (u16)(psidbits << (16 - psidlen)); ++ eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen)); ++ } ++ ++ /* rewrite destination address */ ++ *dest = fmr->ip6_prefix; ++ memcpy(&dest->s6_addr[10], addr, sizeof(*addr)); ++ dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen)); ++ ++ if (bytes > sizeof(u64)) ++ bytes = sizeof(u64); ++ ++ /* insert eabits */ ++ memcpy(&t, &dest->s6_addr[frombyte], bytes); ++ t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1) ++ << (64 - fmr->ea_len - fromrem)); ++ t = cpu_to_be64(t | (eabits >> fromrem)); ++ memcpy(&dest->s6_addr[frombyte], &t, bytes); ++ } ++} ++ ++ + /** + * ip6_tnl_rcv - decapsulate IPv6 packet and retransmit it locally + * @skb: received socket buffer +@@ -815,6 +932,26 @@ static int ip6_tnl_rcv(struct sk_buff *s + skb_reset_network_header(skb); + skb->protocol = htons(protocol); + memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); ++ if (protocol == ETH_P_IP && ++ !ipv6_addr_equal(&ipv6h->saddr, &t->parms.raddr)) { ++ /* Packet didn't come from BR, so lookup FMR */ ++ struct __ip6_tnl_fmr *fmr; ++ struct in6_addr expected = t->parms.raddr; ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) ++ if (ipv6_prefix_equal(&ipv6h->saddr, ++ &fmr->ip6_prefix, fmr->ip6_prefix_len)) ++ break; ++ ++ /* Check that IPv6 matches IPv4 source to prevent spoofing */ ++ if (fmr) ++ ip4ip6_fmr_calc(&expected, ip_hdr(skb), ++ skb_tail_pointer(skb), fmr, false); ++ ++ if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) { ++ rcu_read_unlock(); ++ goto discard; ++ } ++ } + + __skb_tunnel_rx(skb, t->dev, t->net); + +@@ -1076,6 +1213,7 @@ ip4ip6_tnl_xmit(struct sk_buff *skb, str + __u8 dsfield; + __u32 mtu; + int err; ++ struct __ip6_tnl_fmr *fmr; + + if ((t->parms.proto != IPPROTO_IPIP && t->parms.proto != 0) || + !ip6_tnl_xmit_ctl(t)) +@@ -1095,6 +1233,18 @@ ip4ip6_tnl_xmit(struct sk_buff *skb, str + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK) + fl6.flowi6_mark = skb->mark; + ++ /* try to find matching FMR */ ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { ++ unsigned mshift = 32 - fmr->ip4_prefix_len; ++ if (ntohl(fmr->ip4_prefix.s_addr) >> mshift == ++ ntohl(iph->daddr) >> mshift) ++ break; ++ } ++ ++ /* change dstaddr according to FMR */ ++ if (fmr) ++ ip4ip6_fmr_calc(&fl6.daddr, iph, skb_tail_pointer(skb), fmr, true); ++ + err = ip6_tnl_xmit2(skb, dev, dsfield, &fl6, encap_limit, &mtu); + if (err != 0) { + /* XXX: send ICMP error even if DF is not set. */ +@@ -1263,6 +1413,14 @@ ip6_tnl_change(struct ip6_tnl *t, const + t->parms.flowinfo = p->flowinfo; + t->parms.link = p->link; + t->parms.proto = p->proto; ++ ++ while (t->parms.fmrs) { ++ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; ++ kfree(t->parms.fmrs); ++ t->parms.fmrs = next; ++ } ++ t->parms.fmrs = p->fmrs; ++ + ip6_tnl_dst_reset(t); + ip6_tnl_link_config(t); + return 0; +@@ -1293,6 +1451,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_ + p->flowinfo = u->flowinfo; + p->link = u->link; + p->proto = u->proto; ++ p->fmrs = NULL; + memcpy(p->name, u->name, sizeof(u->name)); + } + +@@ -1568,6 +1727,15 @@ static int ip6_tnl_validate(struct nlatt + return 0; + } + ++static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = { ++ [IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) }, ++ [IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) }, ++ [IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 } ++}; ++ + static void ip6_tnl_netlink_parms(struct nlattr *data[], + struct __ip6_tnl_parm *parms) + { +@@ -1601,6 +1769,46 @@ static void ip6_tnl_netlink_parms(struct + + if (data[IFLA_IPTUN_PROTO]) + parms->proto = nla_get_u8(data[IFLA_IPTUN_PROTO]); ++ ++ if (data[IFLA_IPTUN_FMRS]) { ++ unsigned rem; ++ struct nlattr *fmr; ++ nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) { ++ struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c; ++ struct __ip6_tnl_fmr *nfmr; ++ ++ nla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX, ++ fmr, ip6_tnl_fmr_policy); ++ ++ if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL))) ++ continue; ++ ++ nfmr->offset = 6; ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX])) ++ nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX], ++ sizeof(nfmr->ip6_prefix)); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX])) ++ nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX], ++ sizeof(nfmr->ip4_prefix)); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN])) ++ nfmr->ip6_prefix_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN])) ++ nfmr->ip4_prefix_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN])) ++ nfmr->ea_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET])) ++ nfmr->offset = nla_get_u8(c); ++ ++ nfmr->next = parms->fmrs; ++ parms->fmrs = nfmr; ++ } ++ } + } + + static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev, +@@ -1653,6 +1861,12 @@ static void ip6_tnl_dellink(struct net_d + + static size_t ip6_tnl_get_size(const struct net_device *dev) + { ++ const struct ip6_tnl *t = netdev_priv(dev); ++ struct __ip6_tnl_fmr *c; ++ int fmrs = 0; ++ for (c = t->parms.fmrs; c; c = c->next) ++ ++fmrs; ++ + return + /* IFLA_IPTUN_LINK */ + nla_total_size(4) + +@@ -1670,6 +1884,24 @@ static size_t ip6_tnl_get_size(const str + nla_total_size(4) + + /* IFLA_IPTUN_PROTO */ + nla_total_size(1) + ++ /* IFLA_IPTUN_FMRS */ ++ nla_total_size(0) + ++ ( ++ /* nest */ ++ nla_total_size(0) + ++ /* IFLA_IPTUN_FMR_IP6_PREFIX */ ++ nla_total_size(sizeof(struct in6_addr)) + ++ /* IFLA_IPTUN_FMR_IP4_PREFIX */ ++ nla_total_size(sizeof(struct in_addr)) + ++ /* IFLA_IPTUN_FMR_EA_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_OFFSET */ ++ nla_total_size(1) ++ ) * fmrs + + 0; + } + +@@ -1677,6 +1909,9 @@ static int ip6_tnl_fill_info(struct sk_b + { + struct ip6_tnl *tunnel = netdev_priv(dev); + struct __ip6_tnl_parm *parm = &tunnel->parms; ++ struct __ip6_tnl_fmr *c; ++ int fmrcnt = 0; ++ struct nlattr *fmrs; + + if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || + nla_put(skb, IFLA_IPTUN_LOCAL, sizeof(struct in6_addr), +@@ -1687,8 +1922,27 @@ static int ip6_tnl_fill_info(struct sk_b + nla_put_u8(skb, IFLA_IPTUN_ENCAP_LIMIT, parm->encap_limit) || + nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || + nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || +- nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto)) ++ nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || ++ !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS))) + goto nla_put_failure; ++ ++ for (c = parm->fmrs; c; c = c->next) { ++ struct nlattr *fmr = nla_nest_start(skb, ++fmrcnt); ++ if (!fmr || ++ nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX, ++ sizeof(c->ip6_prefix), &c->ip6_prefix) || ++ nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX, ++ sizeof(c->ip4_prefix), &c->ip4_prefix) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset)) ++ goto nla_put_failure; ++ ++ nla_nest_end(skb, fmr); ++ } ++ nla_nest_end(skb, fmrs); ++ + return 0; + + nla_put_failure: +@@ -1704,6 +1958,7 @@ static const struct nla_policy ip6_tnl_p + [IFLA_IPTUN_FLOWINFO] = { .type = NLA_U32 }, + [IFLA_IPTUN_FLAGS] = { .type = NLA_U32 }, + [IFLA_IPTUN_PROTO] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMRS] = { .type = NLA_NESTED }, + }; + + static struct rtnl_link_ops ip6_link_ops __read_mostly = { diff --git a/target/linux/generic/patches-3.18/667-ipv6-Fixed-source-specific-default-route-handling.patch b/target/linux/generic/patches-3.18/667-ipv6-Fixed-source-specific-default-route-handling.patch new file mode 100644 index 0000000..d02e085 --- /dev/null +++ b/target/linux/generic/patches-3.18/667-ipv6-Fixed-source-specific-default-route-handling.patch @@ -0,0 +1,96 @@ +From e16e888b525503be05b3aea64190e8b3bdef44d0 Mon Sep 17 00:00:00 2001 +From: Markus Stenberg +Date: Tue, 5 May 2015 13:36:59 +0300 +Subject: [PATCH] ipv6: Fixed source specific default route handling. + +If there are only IPv6 source specific default routes present, the +host gets -ENETUNREACH on e.g. connect() because ip6_dst_lookup_tail +calls ip6_route_output first, and given source address any, it fails, +and ip6_route_get_saddr is never called. + +The change is to use the ip6_route_get_saddr, even if the initial +ip6_route_output fails, and then doing ip6_route_output _again_ after +we have appropriate source address available. + +Note that this is '99% fix' to the problem; a correct fix would be to +do route lookups only within addrconf.c when picking a source address, +and never call ip6_route_output before source address has been +populated. + +Signed-off-by: Markus Stenberg +Signed-off-by: David S. Miller +--- + net/ipv6/ip6_output.c | 39 +++++++++++++++++++++++++++++++-------- + net/ipv6/route.c | 5 +++-- + 2 files changed, 34 insertions(+), 10 deletions(-) + +--- a/net/ipv6/ip6_output.c ++++ b/net/ipv6/ip6_output.c +@@ -900,21 +900,45 @@ static int ip6_dst_lookup_tail(struct so + #endif + int err; + +- if (*dst == NULL) +- *dst = ip6_route_output(net, sk, fl6); +- +- if ((err = (*dst)->error)) +- goto out_err_release; ++ /* The correct way to handle this would be to do ++ * ip6_route_get_saddr, and then ip6_route_output; however, ++ * the route-specific preferred source forces the ++ * ip6_route_output call _before_ ip6_route_get_saddr. ++ * ++ * In source specific routing (no src=any default route), ++ * ip6_route_output will fail given src=any saddr, though, so ++ * that's why we try it again later. ++ */ ++ if (ipv6_addr_any(&fl6->saddr) && (!*dst || !(*dst)->error)) { ++ struct rt6_info *rt; ++ bool had_dst = *dst != NULL; + +- if (ipv6_addr_any(&fl6->saddr)) { +- struct rt6_info *rt = (struct rt6_info *) *dst; ++ if (!had_dst) ++ *dst = ip6_route_output(net, sk, fl6); ++ rt = (*dst)->error ? NULL : (struct rt6_info *)*dst; + err = ip6_route_get_saddr(net, rt, &fl6->daddr, + sk ? inet6_sk(sk)->srcprefs : 0, + &fl6->saddr); + if (err) + goto out_err_release; ++ ++ /* If we had an erroneous initial result, pretend it ++ * never existed and let the SA-enabled version take ++ * over. ++ */ ++ if (!had_dst && (*dst)->error) { ++ dst_release(*dst); ++ *dst = NULL; ++ } + } + ++ if (!*dst) ++ *dst = ip6_route_output(net, sk, fl6); ++ ++ err = (*dst)->error; ++ if (err) ++ goto out_err_release; ++ + #ifdef CONFIG_IPV6_OPTIMISTIC_DAD + /* + * Here if the dst entry we've looked up +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -2182,9 +2182,10 @@ int ip6_route_get_saddr(struct net *net, + unsigned int prefs, + struct in6_addr *saddr) + { +- struct inet6_dev *idev = ip6_dst_idev((struct dst_entry *)rt); ++ struct inet6_dev *idev = ++ rt ? ip6_dst_idev((struct dst_entry *)rt) : NULL; + int err = 0; +- if (rt->rt6i_prefsrc.plen) ++ if (rt && rt->rt6i_prefsrc.plen) + *saddr = rt->rt6i_prefsrc.addr; + else + err = ipv6_dev_get_saddr(net, idev ? idev->dev : NULL, diff --git a/target/linux/generic/patches-3.18/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/patches-3.18/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch new file mode 100644 index 0000000..1bf9dc9 --- /dev/null +++ b/target/linux/generic/patches-3.18/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -0,0 +1,249 @@ +From 1b5aaa4b16f6e6471ab1c07b38068197a1b4c395 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 24 May 2013 14:40:54 +0200 +Subject: [PATCH 1/2] ipv6: allow rejecting with "source address failed policy" + +RFC6204 L-14 requires rejecting traffic from invalid addresses with +ICMPv6 Destination Unreachable, Code 5 (Source address failed ingress/ +egress policy) on the LAN side, so add an appropriate rule for that. + +Signed-off-by: Jonas Gorski +--- + include/net/netns/ipv6.h | 1 + + include/uapi/linux/fib_rules.h | 4 +++ + include/uapi/linux/rtnetlink.h | 1 + + net/ipv4/fib_semantics.c | 4 +++ + net/ipv4/fib_trie.c | 1 + + net/ipv4/ipmr.c | 1 + + net/ipv6/fib6_rules.c | 4 +++ + net/ipv6/ip6mr.c | 2 ++ + net/ipv6/route.c | 58 +++++++++++++++++++++++++++++++++++++++++- + 9 files changed, 75 insertions(+), 1 deletion(-) + +--- a/include/net/netns/ipv6.h ++++ b/include/net/netns/ipv6.h +@@ -59,6 +59,7 @@ struct netns_ipv6 { + unsigned long ip6_rt_last_gc; + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + struct rt6_info *ip6_prohibit_entry; ++ struct rt6_info *ip6_policy_failed_entry; + struct rt6_info *ip6_blk_hole_entry; + struct fib6_table *fib6_local_tbl; + struct fib_rules_ops *fib6_rules_ops; +--- a/include/uapi/linux/fib_rules.h ++++ b/include/uapi/linux/fib_rules.h +@@ -64,6 +64,10 @@ enum { + FR_ACT_BLACKHOLE, /* Drop without notification */ + FR_ACT_UNREACHABLE, /* Drop with ENETUNREACH */ + FR_ACT_PROHIBIT, /* Drop with EACCES */ ++ FR_ACT_RES9, ++ FR_ACT_RES10, ++ FR_ACT_RES11, ++ FR_ACT_POLICY_FAILED, /* Drop with EACCES */ + __FR_ACT_MAX, + }; + +--- a/include/uapi/linux/rtnetlink.h ++++ b/include/uapi/linux/rtnetlink.h +@@ -203,6 +203,7 @@ enum { + RTN_THROW, /* Not in this table */ + RTN_NAT, /* Translate this address */ + RTN_XRESOLVE, /* Use external resolver */ ++ RTN_POLICY_FAILED, /* Failed ingress/egress policy */ + __RTN_MAX + }; + +--- a/net/ipv4/fib_semantics.c ++++ b/net/ipv4/fib_semantics.c +@@ -138,6 +138,10 @@ const struct fib_prop fib_props[RTN_MAX + .error = -EINVAL, + .scope = RT_SCOPE_NOWHERE, + }, ++ [RTN_POLICY_FAILED] = { ++ .error = -EACCES, ++ .scope = RT_SCOPE_UNIVERSE, ++ }, + }; + + static void rt_fibinfo_free(struct rtable __rcu **rtp) +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -2236,6 +2236,7 @@ static const char *const rtn_type_names[ + [RTN_THROW] = "THROW", + [RTN_NAT] = "NAT", + [RTN_XRESOLVE] = "XRESOLVE", ++ [RTN_POLICY_FAILED] = "POLICY_FAILED", + }; + + static inline const char *rtn_type(char *buf, size_t len, unsigned int t) +--- a/net/ipv4/ipmr.c ++++ b/net/ipv4/ipmr.c +@@ -184,6 +184,7 @@ static int ipmr_rule_action(struct fib_r + case FR_ACT_UNREACHABLE: + return -ENETUNREACH; + case FR_ACT_PROHIBIT: ++ case FR_ACT_POLICY_FAILED: + return -EACCES; + case FR_ACT_BLACKHOLE: + default: +--- a/net/ipv6/fib6_rules.c ++++ b/net/ipv6/fib6_rules.c +@@ -73,6 +73,10 @@ static int fib6_rule_action(struct fib_r + err = -EACCES; + rt = net->ipv6.ip6_prohibit_entry; + goto discard_pkt; ++ case FR_ACT_POLICY_FAILED: ++ err = -EACCES; ++ rt = net->ipv6.ip6_policy_failed_entry; ++ goto discard_pkt; + } + + table = fib6_get_table(net, rule->table); +--- a/net/ipv6/ip6mr.c ++++ b/net/ipv6/ip6mr.c +@@ -169,6 +169,8 @@ static int ip6mr_rule_action(struct fib_ + return -ENETUNREACH; + case FR_ACT_PROHIBIT: + return -EACCES; ++ case FR_ACT_POLICY_FAILED: ++ return -EACCES; + case FR_ACT_BLACKHOLE: + default: + return -EINVAL; +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -87,6 +87,8 @@ static int ip6_pkt_discard(struct sk_bu + static int ip6_pkt_discard_out(struct sock *sk, struct sk_buff *skb); + static int ip6_pkt_prohibit(struct sk_buff *skb); + static int ip6_pkt_prohibit_out(struct sock *sk, struct sk_buff *skb); ++static int ip6_pkt_policy_failed(struct sk_buff *skb); ++static int ip6_pkt_policy_failed_out(struct sock *sk, struct sk_buff *skb); + static void ip6_link_failure(struct sk_buff *skb); + static void ip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk, + struct sk_buff *skb, u32 mtu); +@@ -283,6 +285,21 @@ static const struct rt6_info ip6_prohibi + .rt6i_ref = ATOMIC_INIT(1), + }; + ++static const struct rt6_info ip6_policy_failed_entry_template = { ++ .dst = { ++ .__refcnt = ATOMIC_INIT(1), ++ .__use = 1, ++ .obsolete = DST_OBSOLETE_FORCE_CHK, ++ .error = -EACCES, ++ .input = ip6_pkt_policy_failed, ++ .output = ip6_pkt_policy_failed_out, ++ }, ++ .rt6i_flags = (RTF_REJECT | RTF_NONEXTHOP), ++ .rt6i_protocol = RTPROT_KERNEL, ++ .rt6i_metric = ~(u32) 0, ++ .rt6i_ref = ATOMIC_INIT(1), ++}; ++ + static const struct rt6_info ip6_blk_hole_entry_template = { + .dst = { + .__refcnt = ATOMIC_INIT(1), +@@ -1578,6 +1595,11 @@ int ip6_route_add(struct fib6_config *cf + rt->dst.output = ip6_pkt_prohibit_out; + rt->dst.input = ip6_pkt_prohibit; + break; ++ case RTN_POLICY_FAILED: ++ rt->dst.error = -EACCES; ++ rt->dst.output = ip6_pkt_policy_failed_out; ++ rt->dst.input = ip6_pkt_policy_failed; ++ break; + case RTN_THROW: + default: + rt->dst.error = (cfg->fc_type == RTN_THROW) ? -EAGAIN +@@ -2139,6 +2161,17 @@ static int ip6_pkt_prohibit_out(struct s + return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES); + } + ++static int ip6_pkt_policy_failed(struct sk_buff *skb) ++{ ++ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_INNOROUTES); ++} ++ ++static int ip6_pkt_policy_failed_out(struct sock *sk, struct sk_buff *skb) ++{ ++ skb->dev = skb_dst(skb)->dev; ++ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_OUTNOROUTES); ++} ++ + /* + * Allocate a dst for local (unicast / anycast) address. + */ +@@ -2363,7 +2396,8 @@ static int rtm_to_fib6_config(struct sk_ + if (rtm->rtm_type == RTN_UNREACHABLE || + rtm->rtm_type == RTN_BLACKHOLE || + rtm->rtm_type == RTN_PROHIBIT || +- rtm->rtm_type == RTN_THROW) ++ rtm->rtm_type == RTN_THROW || ++ rtm->rtm_type == RTN_POLICY_FAILED) + cfg->fc_flags |= RTF_REJECT; + + if (rtm->rtm_type == RTN_LOCAL) +@@ -2565,6 +2599,9 @@ static int rt6_fill_node(struct net *net + case -EACCES: + rtm->rtm_type = RTN_PROHIBIT; + break; ++ case -EPERM: ++ rtm->rtm_type = RTN_POLICY_FAILED; ++ break; + case -EAGAIN: + rtm->rtm_type = RTN_THROW; + break; +@@ -2818,6 +2855,8 @@ static int ip6_route_dev_notify(struct n + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + net->ipv6.ip6_prohibit_entry->dst.dev = dev; + net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev); ++ net->ipv6.ip6_policy_failed_entry->dst.dev = dev; ++ net->ipv6.ip6_policy_failed_entry->rt6i_idev = in6_dev_get(dev); + net->ipv6.ip6_blk_hole_entry->dst.dev = dev; + net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev); + #endif +@@ -3034,6 +3073,17 @@ static int __net_init ip6_route_net_init + net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops; + dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst, + ip6_template_metrics, true); ++ ++ net->ipv6.ip6_policy_failed_entry = ++ kmemdup(&ip6_policy_failed_entry_template, ++ sizeof(*net->ipv6.ip6_policy_failed_entry), GFP_KERNEL); ++ if (!net->ipv6.ip6_policy_failed_entry) ++ goto out_ip6_blk_hole_entry; ++ net->ipv6.ip6_policy_failed_entry->dst.path = ++ (struct dst_entry *)net->ipv6.ip6_policy_failed_entry; ++ net->ipv6.ip6_policy_failed_entry->dst.ops = &net->ipv6.ip6_dst_ops; ++ dst_init_metrics(&net->ipv6.ip6_policy_failed_entry->dst, ++ ip6_template_metrics, true); + #endif + + net->ipv6.sysctl.flush_delay = 0; +@@ -3052,6 +3102,8 @@ out: + return ret; + + #ifdef CONFIG_IPV6_MULTIPLE_TABLES ++out_ip6_blk_hole_entry: ++ kfree(net->ipv6.ip6_blk_hole_entry); + out_ip6_prohibit_entry: + kfree(net->ipv6.ip6_prohibit_entry); + out_ip6_null_entry: +@@ -3069,6 +3121,7 @@ static void __net_exit ip6_route_net_exi + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + kfree(net->ipv6.ip6_prohibit_entry); + kfree(net->ipv6.ip6_blk_hole_entry); ++ kfree(net->ipv6.ip6_policy_failed_entry); + #endif + dst_entries_destroy(&net->ipv6.ip6_dst_ops); + } +@@ -3165,6 +3218,9 @@ int __init ip6_route_init(void) + init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); + init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev; + init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); ++ init_net.ipv6.ip6_policy_failed_entry->dst.dev = init_net.loopback_dev; ++ init_net.ipv6.ip6_policy_failed_entry->rt6i_idev = ++ in6_dev_get(init_net.loopback_dev); + #endif + ret = fib6_init(); + if (ret) diff --git a/target/linux/generic/patches-3.18/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch b/target/linux/generic/patches-3.18/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch new file mode 100644 index 0000000..25a8639 --- /dev/null +++ b/target/linux/generic/patches-3.18/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch @@ -0,0 +1,53 @@ +From 7749b481ce5d7e232b1f7da5e6b2c44816f51681 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 19 Jan 2014 20:45:51 +0100 +Subject: [PATCH 2/2] net: provide defines for _POLICY_FAILED until all code is + updated + +Upstream introduced ICMPV6_POLICY_FAIL for code 5 of destination +unreachable, conflicting with our name. + +Add appropriate defines to allow our code to build with the new +name until we have updated our local patches for older kernels +and userspace packages. + +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/fib_rules.h | 2 ++ + include/uapi/linux/icmpv6.h | 2 ++ + include/uapi/linux/rtnetlink.h | 2 ++ + 3 files changed, 6 insertions(+) + +--- a/include/uapi/linux/fib_rules.h ++++ b/include/uapi/linux/fib_rules.h +@@ -71,6 +71,8 @@ enum { + __FR_ACT_MAX, + }; + ++#define FR_ACT_FAILED_POLICY FR_ACT_POLICY_FAILED ++ + #define FR_ACT_MAX (__FR_ACT_MAX - 1) + + #endif +--- a/include/uapi/linux/icmpv6.h ++++ b/include/uapi/linux/icmpv6.h +@@ -118,6 +118,8 @@ struct icmp6hdr { + #define ICMPV6_POLICY_FAIL 5 + #define ICMPV6_REJECT_ROUTE 6 + ++#define ICMPV6_FAILED_POLICY ICMPV6_POLICY_FAIL ++ + /* + * Codes for Time Exceeded + */ +--- a/include/uapi/linux/rtnetlink.h ++++ b/include/uapi/linux/rtnetlink.h +@@ -207,6 +207,8 @@ enum { + __RTN_MAX + }; + ++#define RTN_FAILED_POLICY RTN_POLICY_FAILED ++ + #define RTN_MAX (__RTN_MAX - 1) + + diff --git a/target/linux/generic/patches-3.18/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/patches-3.18/680-NET-skip-GRO-for-foreign-MAC-addresses.patch new file mode 100644 index 0000000..21199fe --- /dev/null +++ b/target/linux/generic/patches-3.18/680-NET-skip-GRO-for-foreign-MAC-addresses.patch @@ -0,0 +1,160 @@ +Subject: NET: skip GRO for foreign MAC addresses + +For network drivers using napi_gro_receive, packets are run through GRO, +even when the destination MAC address does not match, and they're supposed +to be delivered to another host behind a different bridge port. + +This can be very expensive, because for drivers without TSO or scatter- +gather, this can only be undone by copying the skb and checksumming it +again. + +To be able to track foreign MAC addresses in an inexpensive way, create +a mask of changed bits in MAC addresses of upper devices. This allows +handling VLANs and bridge devices with different addresses (as long as +they are not too different). + +Signed-off-by: Felix Fietkau + +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -4002,6 +4002,9 @@ static enum gro_result dev_gro_receive(s + enum gro_result ret; + int grow; + ++ if (skb->gro_skip) ++ goto normal; ++ + if (!(skb->dev->features & NETIF_F_GRO)) + goto normal; + +@@ -5067,6 +5070,48 @@ static void __netdev_adjacent_dev_unlink + &upper_dev->adj_list.lower); + } + ++static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr, ++ struct net_device *dev) ++{ ++ int i; ++ ++ for (i = 0; i < dev->addr_len; i++) ++ mask[i] |= addr[i] ^ dev->dev_addr[i]; ++} ++ ++static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev, ++ struct net_device *lower) ++{ ++ struct net_device *cur; ++ struct list_head *iter; ++ ++ netdev_for_each_upper_dev_rcu(dev, cur, iter) { ++ __netdev_addr_mask(mask, cur->dev_addr, lower); ++ __netdev_upper_mask(mask, cur, lower); ++ } ++} ++ ++static void __netdev_update_addr_mask(struct net_device *dev) ++{ ++ unsigned char mask[MAX_ADDR_LEN]; ++ struct net_device *cur; ++ struct list_head *iter; ++ ++ memset(mask, 0, sizeof(mask)); ++ __netdev_upper_mask(mask, dev, dev); ++ memcpy(dev->local_addr_mask, mask, dev->addr_len); ++ ++ netdev_for_each_lower_dev(dev, cur, iter) ++ __netdev_update_addr_mask(cur); ++} ++ ++static void netdev_update_addr_mask(struct net_device *dev) ++{ ++ rcu_read_lock(); ++ __netdev_update_addr_mask(dev); ++ rcu_read_unlock(); ++} ++ + static int __netdev_upper_dev_link(struct net_device *dev, + struct net_device *upper_dev, bool master, + void *private) +@@ -5127,6 +5172,7 @@ static int __netdev_upper_dev_link(struc + goto rollback_lower_mesh; + } + ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEUPPER, dev); + return 0; + +@@ -5244,6 +5290,7 @@ void netdev_upper_dev_unlink(struct net_ + list_for_each_entry(i, &upper_dev->all_adj_list.upper, list) + __netdev_adjacent_dev_unlink(dev, i->dev); + ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEUPPER, dev); + } + EXPORT_SYMBOL(netdev_upper_dev_unlink); +@@ -5763,6 +5810,7 @@ int dev_set_mac_address(struct net_devic + if (err) + return err; + dev->addr_assign_type = NET_ADDR_SET; ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEADDR, dev); + add_device_randomness(dev->dev_addr, dev->addr_len); + return 0; +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1556,6 +1556,8 @@ struct net_device { + struct netdev_hw_addr_list mc; + struct netdev_hw_addr_list dev_addrs; + ++ unsigned char local_addr_mask[MAX_ADDR_LEN]; ++ + #ifdef CONFIG_SYSFS + struct kset *queues_kset; + #endif +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -597,7 +597,8 @@ struct sk_buff { + #endif + __u8 ipvs_property:1; + __u8 inner_protocol_type:1; +- /* 4 or 6 bit hole */ ++ __u8 gro_skip:1; ++ /* 3 or 5 bit hole */ + + #ifdef CONFIG_NET_SCHED + __u16 tc_index; /* traffic control index */ +--- a/net/ethernet/eth.c ++++ b/net/ethernet/eth.c +@@ -172,6 +172,18 @@ u32 eth_get_headlen(void *data, unsigned + } + EXPORT_SYMBOL(eth_get_headlen); + ++static inline bool ++eth_check_local_mask(const void *addr1, const void *addr2, const void *mask) ++{ ++ const u16 *a1 = addr1; ++ const u16 *a2 = addr2; ++ const u16 *m = mask; ++ ++ return (((a1[0] ^ a2[0]) & ~m[0]) | ++ ((a1[1] ^ a2[1]) & ~m[1]) | ++ ((a1[2] ^ a2[2]) & ~m[2])); ++} ++ + /** + * eth_type_trans - determine the packet's protocol ID. + * @skb: received socket data +@@ -199,8 +211,12 @@ __be16 eth_type_trans(struct sk_buff *sk + skb->pkt_type = PACKET_MULTICAST; + } + else if (unlikely(!ether_addr_equal_64bits(eth->h_dest, +- dev->dev_addr))) ++ dev->dev_addr))) { + skb->pkt_type = PACKET_OTHERHOST; ++ if (eth_check_local_mask(eth->h_dest, dev->dev_addr, ++ dev->local_addr_mask)) ++ skb->gro_skip = 1; ++ } + + /* + * Some variants of DSA tagging don't have an ethertype field diff --git a/target/linux/generic/patches-3.18/681-NET-add-of_get_mac_address_mtd.patch b/target/linux/generic/patches-3.18/681-NET-add-of_get_mac_address_mtd.patch new file mode 100644 index 0000000..a836eed --- /dev/null +++ b/target/linux/generic/patches-3.18/681-NET-add-of_get_mac_address_mtd.patch @@ -0,0 +1,88 @@ +From: John Crispin +Date: Sun, 27 Jul 2014 09:40:01 +0100 +Subject: NET: add of_get_mac_address_mtd() + +Many embedded devices have information such as mac addresses stored inside mtd +devices. This patch allows us to add a property inside a node describing a +network interface. The new property points at a mtd partition with an offset +where the mac address can be found. + +Signed-off-by: John Crispin +--- + drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++ + include/linux/of_net.h | 1 + + 2 files changed, 38 insertions(+) + +--- a/drivers/of/of_net.c ++++ b/drivers/of/of_net.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + /** + * of_get_phy_mode - Get phy mode for given device_node +@@ -75,3 +76,45 @@ const void *of_get_mac_address(struct de + return NULL; + } + EXPORT_SYMBOL(of_get_mac_address); ++ ++#ifdef CONFIG_MTD ++int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac) ++{ ++ struct device_node *mtd_np = NULL; ++ size_t retlen; ++ int size, ret; ++ struct mtd_info *mtd; ++ const char *part; ++ const __be32 *list; ++ phandle phandle; ++ u32 mac_inc = 0; ++ ++ list = of_get_property(np, "mtd-mac-address", &size); ++ if (!list || (size != (2 * sizeof(*list)))) ++ return -ENOENT; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return -ENOENT; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ mtd = get_mtd_device_nm(part); ++ if (IS_ERR(mtd)) ++ return PTR_ERR(mtd); ++ ++ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, mac); ++ put_mtd_device(mtd); ++ ++ if (!of_property_read_u32(np, "mtd-mac-address-increment", &mac_inc)) ++ mac[5] += mac_inc; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(of_get_mac_address_mtd); ++#endif +--- a/include/linux/of_net.h ++++ b/include/linux/of_net.h +@@ -11,6 +11,14 @@ + #include + extern int of_get_phy_mode(struct device_node *np); + extern const void *of_get_mac_address(struct device_node *np); ++#ifdef CONFIG_MTD ++extern int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac); ++#else ++static inline int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac) ++{ ++ return -ENOENT; ++} ++#endif + #else + static inline int of_get_phy_mode(struct device_node *np) + { diff --git a/target/linux/generic/patches-3.18/700-swconfig.patch b/target/linux/generic/patches-3.18/700-swconfig.patch new file mode 100644 index 0000000..7cf525a --- /dev/null +++ b/target/linux/generic/patches-3.18/700-swconfig.patch @@ -0,0 +1,39 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -12,6 +12,16 @@ menuconfig PHYLIB + + if PHYLIB + ++config SWCONFIG ++ tristate "Switch configuration API" ++ ---help--- ++ Switch configuration API using netlink. This allows ++ you to configure the VLAN features of certain switches. ++ ++config SWCONFIG_LEDS ++ bool "Switch LED trigger support" ++ depends on (SWCONFIG && LEDS_TRIGGERS) ++ + comment "MII PHY device drivers" + + config AT803X_PHY +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -3,6 +3,7 @@ + libphy-objs := phy.o phy_device.o mdio_bus.o + + obj-$(CONFIG_PHYLIB) += libphy.o ++obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_DAVICOM_PHY) += davicom.o + obj-$(CONFIG_CICADA_PHY) += cicada.o +--- a/include/uapi/linux/Kbuild ++++ b/include/uapi/linux/Kbuild +@@ -374,6 +374,7 @@ header-y += stddef.h + header-y += string.h + header-y += suspend_ioctls.h + header-y += swab.h ++header-y += switch.h + header-y += synclink.h + header-y += sysctl.h + header-y += sysinfo.h diff --git a/target/linux/generic/patches-3.18/701-phy_extension.patch b/target/linux/generic/patches-3.18/701-phy_extension.patch new file mode 100644 index 0000000..5c63dbe --- /dev/null +++ b/target/linux/generic/patches-3.18/701-phy_extension.patch @@ -0,0 +1,63 @@ +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -357,6 +357,50 @@ int phy_ethtool_gset(struct phy_device * + } + EXPORT_SYMBOL(phy_ethtool_gset); + ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) ++{ ++ u32 cmd; ++ int tmp; ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (get_user(cmd, (u32 *) useraddr)) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case ETHTOOL_GSET: ++ phy_ethtool_gset(phydev, &ecmd); ++ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) ++ return -EFAULT; ++ return 0; ++ ++ case ETHTOOL_SSET: ++ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) ++ return -EFAULT; ++ return phy_ethtool_sset(phydev, &ecmd); ++ ++ case ETHTOOL_NWAY_RST: ++ /* if autoneg is off, it's an error */ ++ tmp = phy_read(phydev, MII_BMCR); ++ if (tmp & BMCR_ANENABLE) { ++ tmp |= (BMCR_ANRESTART); ++ phy_write(phydev, MII_BMCR, tmp); ++ return 0; ++ } ++ return -EINVAL; ++ ++ case ETHTOOL_GLINK: ++ edata.data = (phy_read(phydev, ++ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++ } ++ ++ return -EOPNOTSUPP; ++} ++EXPORT_SYMBOL(phy_ethtool_ioctl); ++ + /** + * phy_mii_ioctl - generic PHY MII ioctl interface + * @phydev: the phy_device struct +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -748,6 +748,7 @@ void phy_start_machine(struct phy_device + void phy_stop_machine(struct phy_device *phydev); + int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); + int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); + int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd); + int phy_start_interrupts(struct phy_device *phydev); + void phy_print_status(struct phy_device *phydev); diff --git a/target/linux/generic/patches-3.18/702-phy_add_aneg_done_function.patch b/target/linux/generic/patches-3.18/702-phy_add_aneg_done_function.patch new file mode 100644 index 0000000..d20fc04 --- /dev/null +++ b/target/linux/generic/patches-3.18/702-phy_add_aneg_done_function.patch @@ -0,0 +1,27 @@ +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -484,6 +484,12 @@ struct phy_driver { + /* Determines the negotiated speed and duplex */ + int (*read_status)(struct phy_device *phydev); + ++ /* ++ * Update the value in phydev->link to reflect the ++ * current link value ++ */ ++ int (*update_link)(struct phy_device *phydev); ++ + /* Clears any pending interrupts */ + int (*ack_interrupt)(struct phy_device *phydev); + +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -915,6 +915,9 @@ int genphy_update_link(struct phy_device + { + int status; + ++ if (phydev->drv->update_link) ++ return phydev->drv->update_link(phydev); ++ + /* Do a fake read */ + status = phy_read(phydev, MII_BMSR); + if (status < 0) diff --git a/target/linux/generic/patches-3.18/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/patches-3.18/703-phy-add-detach-callback-to-struct-phy_driver.patch new file mode 100644 index 0000000..061e40f --- /dev/null +++ b/target/linux/generic/patches-3.18/703-phy-add-detach-callback-to-struct-phy_driver.patch @@ -0,0 +1,27 @@ +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -674,6 +674,9 @@ void phy_detach(struct phy_device *phyde + { + int i; + ++ if (phydev->drv && phydev->drv->detach) ++ phydev->drv->detach(phydev); ++ + if (phydev->bus->dev.driver) + module_put(phydev->bus->dev.driver->owner); + +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -502,6 +502,12 @@ struct phy_driver { + */ + int (*did_interrupt)(struct phy_device *phydev); + ++ /* ++ * Called before an ethernet device is detached ++ * from the PHY. ++ */ ++ void (*detach)(struct phy_device *phydev); ++ + /* Clears up any memory if needed */ + void (*remove)(struct phy_device *phydev); + diff --git a/target/linux/generic/patches-3.18/704-phy-no-genphy-soft-reset.patch b/target/linux/generic/patches-3.18/704-phy-no-genphy-soft-reset.patch new file mode 100644 index 0000000..0350f9e --- /dev/null +++ b/target/linux/generic/patches-3.18/704-phy-no-genphy-soft-reset.patch @@ -0,0 +1,29 @@ +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -1133,7 +1133,7 @@ int genphy_config_init(struct phy_device + return 0; + } + +-static int gen10g_soft_reset(struct phy_device *phydev) ++static int no_soft_reset(struct phy_device *phydev) + { + /* Do nothing for now */ + return 0; +@@ -1347,7 +1347,7 @@ static struct phy_driver genphy_driver[] + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic PHY", +- .soft_reset = genphy_soft_reset, ++ .soft_reset = no_soft_reset, + .config_init = genphy_config_init, + .features = PHY_GBIT_FEATURES | SUPPORTED_MII | + SUPPORTED_AUI | SUPPORTED_FIBRE | +@@ -1362,7 +1362,7 @@ static struct phy_driver genphy_driver[] + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic 10G PHY", +- .soft_reset = gen10g_soft_reset, ++ .soft_reset = no_soft_reset, + .config_init = gen10g_config_init, + .features = 0, + .config_aneg = gen10g_config_aneg, diff --git a/target/linux/generic/patches-3.18/710-phy-add-mdio_register_board_info.patch b/target/linux/generic/patches-3.18/710-phy-add-mdio_register_board_info.patch new file mode 100644 index 0000000..cc3cb24 --- /dev/null +++ b/target/linux/generic/patches-3.18/710-phy-add-mdio_register_board_info.patch @@ -0,0 +1,192 @@ +--- a/drivers/net/phy/mdio_bus.c ++++ b/drivers/net/phy/mdio_bus.c +@@ -38,6 +38,8 @@ + + #include + ++#include "mdio-boardinfo.h" ++ + /** + * mdiobus_alloc_size - allocate a mii_bus structure + * @size: extra amount of memory to allocate for private storage. +@@ -335,9 +337,21 @@ void mdiobus_free(struct mii_bus *bus) + } + EXPORT_SYMBOL(mdiobus_free); + ++static void mdiobus_setup_phydev_from_boardinfo(struct mii_bus *bus, ++ struct phy_device *phydev, ++ struct mdio_board_info *bi) ++{ ++ if (strcmp(bus->id, bi->bus_id) || ++ bi->phy_addr != phydev->addr) ++ return; ++ ++ phydev->dev.platform_data = (void *) bi->platform_data; ++} ++ + struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr) + { + struct phy_device *phydev; ++ struct mdio_board_entry *be; + int err; + + phydev = get_phy_device(bus, addr, false); +@@ -350,6 +364,12 @@ struct phy_device *mdiobus_scan(struct m + */ + of_mdiobus_link_phydev(bus, phydev); + ++ mutex_lock(&__mdio_board_lock); ++ list_for_each_entry(be, &__mdio_board_list, list) ++ mdiobus_setup_phydev_from_boardinfo(bus, phydev, ++ &be->board_info); ++ mutex_unlock(&__mdio_board_lock); ++ + err = phy_device_register(phydev); + if (err) { + phy_device_free(phydev); +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -785,4 +785,22 @@ int __init mdio_bus_init(void); + void mdio_bus_exit(void); + + extern struct bus_type mdio_bus_type; ++ ++struct mdio_board_info { ++ const char *bus_id; ++ int phy_addr; ++ ++ const void *platform_data; ++}; ++ ++#ifdef CONFIG_MDIO_BOARDINFO ++int mdiobus_register_board_info(const struct mdio_board_info *info, unsigned n); ++#else ++static inline int ++mdiobus_register_board_info(const struct mdio_board_info *info, unsigned n) ++{ ++ return 0; ++} ++#endif ++ + #endif /* __PHY_H */ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -12,6 +12,10 @@ menuconfig PHYLIB + + if PHYLIB + ++config MDIO_BOARDINFO ++ bool ++ default y ++ + config SWCONFIG + tristate "Switch configuration API" + ---help--- +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -2,6 +2,8 @@ + + libphy-objs := phy.o phy_device.o mdio_bus.o + ++obj-$(CONFIG_MDIO_BOARDINFO) += mdio-boardinfo.o ++ + obj-$(CONFIG_PHYLIB) += libphy.o + obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_MARVELL_PHY) += marvell.o +--- /dev/null ++++ b/drivers/net/phy/mdio-boardinfo.c +@@ -0,0 +1,58 @@ ++/* ++ * mdio-boardinfo.c - collect pre-declarations of PHY devices ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdio-boardinfo.h" ++ ++/* ++ * These symbols are exported ONLY FOR the mdio_bus component. ++ * No other users will be supported. ++ */ ++ ++LIST_HEAD(__mdio_board_list); ++EXPORT_SYMBOL_GPL(__mdio_board_list); ++ ++DEFINE_MUTEX(__mdio_board_lock); ++EXPORT_SYMBOL_GPL(__mdio_board_lock); ++ ++/** ++ * mdio_register_board_info - register PHY devices for a given board ++ * @info: array of chip descriptors ++ * @n: how many descriptors are provided ++ * Context: can sleep ++ * ++ * The board info passed can safely be __initdata ... but be careful of ++ * any embedded pointers (platform_data, etc), they're copied as-is. ++ */ ++int __init ++mdiobus_register_board_info(struct mdio_board_info const *info, unsigned n) ++{ ++ struct mdio_board_entry *be; ++ int i; ++ ++ be = kzalloc(n * sizeof(*be), GFP_KERNEL); ++ if (!be) ++ return -ENOMEM; ++ ++ for (i = 0; i < n; i++, be++, info++) { ++ memcpy(&be->board_info, info, sizeof(*info)); ++ mutex_lock(&__mdio_board_lock); ++ list_add_tail(&be->list, &__mdio_board_list); ++ mutex_unlock(&__mdio_board_lock); ++ } ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/net/phy/mdio-boardinfo.h +@@ -0,0 +1,22 @@ ++/* ++ * mdio-boardinfo.h - boardinfo interface internal to the mdio_bus component ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++ ++struct mdio_board_entry { ++ struct list_head list; ++ struct mdio_board_info board_info; ++}; ++ ++/* __mdio_board_lock protects __mdio_board_list ++ * only mdio_bus components are allowed to use these symbols. ++ */ ++extern struct mutex __mdio_board_lock; ++extern struct list_head __mdio_board_list; +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -15,7 +15,7 @@ obj-$(CONFIG_MII) += mii.o + obj-$(CONFIG_MDIO) += mdio.o + obj-$(CONFIG_NET) += Space.o loopback.o + obj-$(CONFIG_NETCONSOLE) += netconsole.o +-obj-$(CONFIG_PHYLIB) += phy/ ++obj-y += phy/ + obj-$(CONFIG_RIONET) += rionet.o + obj-$(CONFIG_NET_TEAM) += team/ + obj-$(CONFIG_TUN) += tun.o diff --git a/target/linux/generic/patches-3.18/720-phy_adm6996.patch b/target/linux/generic/patches-3.18/720-phy_adm6996.patch new file mode 100644 index 0000000..b0b8db4 --- /dev/null +++ b/target/linux/generic/patches-3.18/720-phy_adm6996.patch @@ -0,0 +1,26 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -132,6 +132,13 @@ config MICREL_PHY + ---help--- + Supports the KSZ9021, VSC8201, KS8001 PHYs. + ++config ADM6996_PHY ++ tristate "Driver for ADM6996 switches" ++ select SWCONFIG ++ ---help--- ++ Currently supports the ADM6996FC and ADM6996M switches. ++ Support for FC is very limited. ++ + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o + obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o ++obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed.o diff --git a/target/linux/generic/patches-3.18/721-phy_packets.patch b/target/linux/generic/patches-3.18/721-phy_packets.patch new file mode 100644 index 0000000..99811c6 --- /dev/null +++ b/target/linux/generic/patches-3.18/721-phy_packets.patch @@ -0,0 +1,161 @@ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1228,6 +1228,7 @@ enum netdev_priv_flags { + IFF_LIVE_ADDR_CHANGE = 1<<20, + IFF_MACVLAN = 1<<21, + IFF_XMIT_DST_RELEASE_PERM = 1<<22, ++ IFF_NO_IP_ALIGN = 1<<23, + }; + + #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN +@@ -1253,6 +1254,7 @@ enum netdev_priv_flags { + #define IFF_LIVE_ADDR_CHANGE IFF_LIVE_ADDR_CHANGE + #define IFF_MACVLAN IFF_MACVLAN + #define IFF_XMIT_DST_RELEASE_PERM IFF_XMIT_DST_RELEASE_PERM ++#define IFF_NO_IP_ALIGN IFF_NO_IP_ALIGN + + /** + * struct net_device - The DEVICE structure. +@@ -1523,6 +1525,11 @@ struct net_device { + const struct ethtool_ops *ethtool_ops; + const struct forwarding_accel_ops *fwd_ops; + ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ void (*eth_mangle_rx)(struct net_device *dev, struct sk_buff *skb); ++ struct sk_buff *(*eth_mangle_tx)(struct net_device *dev, struct sk_buff *skb); ++#endif ++ + const struct header_ops *header_ops; + + unsigned int flags; +@@ -1587,6 +1594,10 @@ struct net_device { + void *ax25_ptr; + struct wireless_dev *ieee80211_ptr; + ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ void *phy_ptr; /* PHY device specific data */ ++#endif ++ + /* + * Cache lines mostly used on receive path (including eth_type_trans()) + */ +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2054,6 +2054,10 @@ static inline int pskb_trim(struct sk_bu + return (len < skb->len) ? __pskb_trim(skb, len) : 0; + } + ++extern struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, ++ unsigned int length, gfp_t gfp); ++ ++ + /** + * pskb_trim_unique - remove end from a paged unique (not cloned) buffer + * @skb: buffer to alter +@@ -2180,16 +2184,6 @@ static inline struct sk_buff *dev_alloc_ + } + + +-static inline struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, +- unsigned int length, gfp_t gfp) +-{ +- struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); +- +- if (NET_IP_ALIGN && skb) +- skb_reserve(skb, NET_IP_ALIGN); +- return skb; +-} +- + static inline struct sk_buff *netdev_alloc_skb_ip_align(struct net_device *dev, + unsigned int length) + { +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -25,6 +25,12 @@ menuconfig NET + + if NET + ++config ETHERNET_PACKET_MANGLE ++ bool ++ help ++ This option can be selected by phy drivers that need to mangle ++ packets going in or out of an ethernet device. ++ + config WANT_COMPAT_NETLINK_MESSAGES + bool + help +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -2623,10 +2623,20 @@ static int xmit_one(struct sk_buff *skb, + if (!list_empty(&ptype_all)) + dev_queue_xmit_nit(skb, dev); + +- len = skb->len; +- trace_net_dev_start_xmit(skb, dev); +- rc = netdev_start_xmit(skb, dev, txq, more); +- trace_net_dev_xmit(skb, rc, dev, len); ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (!dev->eth_mangle_tx || ++ (skb = dev->eth_mangle_tx(dev, skb)) != NULL) ++#else ++ if (1) ++#endif ++ { ++ len = skb->len; ++ trace_net_dev_start_xmit(skb, dev); ++ rc = netdev_start_xmit(skb, dev, txq, more); ++ trace_net_dev_xmit(skb, rc, dev, len); ++ } else { ++ rc = NETDEV_TX_OK; ++ } + + return rc; + } +--- a/net/core/skbuff.c ++++ b/net/core/skbuff.c +@@ -63,6 +63,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -469,6 +470,22 @@ struct sk_buff *__netdev_alloc_skb(struc + } + EXPORT_SYMBOL(__netdev_alloc_skb); + ++struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, ++ unsigned int length, gfp_t gfp) ++{ ++ struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); ++ ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (dev && (dev->priv_flags & IFF_NO_IP_ALIGN)) ++ return skb; ++#endif ++ ++ if (NET_IP_ALIGN && skb) ++ skb_reserve(skb, NET_IP_ALIGN); ++ return skb; ++} ++EXPORT_SYMBOL(__netdev_alloc_skb_ip_align); ++ + void skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page, int off, + int size, unsigned int truesize) + { +--- a/net/ethernet/eth.c ++++ b/net/ethernet/eth.c +@@ -200,6 +200,12 @@ __be16 eth_type_trans(struct sk_buff *sk + const struct ethhdr *eth; + + skb->dev = dev; ++ ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (dev->eth_mangle_rx) ++ dev->eth_mangle_rx(dev, skb); ++#endif ++ + skb_reset_mac_header(skb); + skb_pull_inline(skb, ETH_HLEN); + eth = eth_hdr(skb); diff --git a/target/linux/generic/patches-3.18/722-phy_mvswitch.patch b/target/linux/generic/patches-3.18/722-phy_mvswitch.patch new file mode 100644 index 0000000..f577a9f --- /dev/null +++ b/target/linux/generic/patches-3.18/722-phy_mvswitch.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -139,6 +139,10 @@ config ADM6996_PHY + Currently supports the ADM6996FC and ADM6996M switches. + Support for FC is very limited. + ++config MVSWITCH_PHY ++ tristate "Driver for Marvell 88E6060 switches" ++ select ETHERNET_PACKET_MANGLE ++ + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o ++obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed.o diff --git a/target/linux/generic/patches-3.18/723-phy_ip175c.patch b/target/linux/generic/patches-3.18/723-phy_ip175c.patch new file mode 100644 index 0000000..c7c4f99 --- /dev/null +++ b/target/linux/generic/patches-3.18/723-phy_ip175c.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -143,6 +143,10 @@ config MVSWITCH_PHY + tristate "Driver for Marvell 88E6060 switches" + select ETHERNET_PACKET_MANGLE + ++config IP17XX_PHY ++ tristate "Driver for IC+ IP17xx switches" ++ select SWCONFIG ++ + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o ++obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed.o diff --git a/target/linux/generic/patches-3.18/724-phy_ar8216.patch b/target/linux/generic/patches-3.18/724-phy_ar8216.patch new file mode 100644 index 0000000..acb2df8 --- /dev/null +++ b/target/linux/generic/patches-3.18/724-phy_ar8216.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -147,6 +147,11 @@ config IP17XX_PHY + tristate "Driver for IC+ IP17xx switches" + select SWCONFIG + ++config AR8216_PHY ++ tristate "Driver for Atheros AR8216 switches" ++ select ETHERNET_PACKET_MANGLE ++ select SWCONFIG ++ + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o ++obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-3.18/725-phy_rtl8306.patch b/target/linux/generic/patches-3.18/725-phy_rtl8306.patch new file mode 100644 index 0000000..78ac6ce --- /dev/null +++ b/target/linux/generic/patches-3.18/725-phy_rtl8306.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -152,6 +152,10 @@ config AR8216_PHY + select ETHERNET_PACKET_MANGLE + select SWCONFIG + ++config RTL8306_PHY ++ tristate "Driver for Realtek RTL8306S switches" ++ select SWCONFIG ++ + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -23,6 +23,7 @@ obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o ++obj-$(CONFIG_RTL8306_PHY) += rtl8306.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-3.18/726-phy_rtl8366.patch b/target/linux/generic/patches-3.18/726-phy_rtl8366.patch new file mode 100644 index 0000000..4a4a4ac --- /dev/null +++ b/target/linux/generic/patches-3.18/726-phy_rtl8366.patch @@ -0,0 +1,45 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -250,6 +250,30 @@ config MDIO_BCM_UNIMAC + controllers as well as some Broadcom Ethernet switches such as the + Starfighter 2 switches. + ++config RTL8366_SMI ++ tristate "Driver for the RTL8366 SMI interface" ++ depends on GPIOLIB ++ ---help--- ++ This module implements the SMI interface protocol which is used ++ by some RTL8366 ethernet switch devices via the generic GPIO API. ++ ++if RTL8366_SMI ++ ++config RTL8366_SMI_DEBUG_FS ++ bool "RTL8366 SMI interface debugfs support" ++ depends on DEBUG_FS ++ default n ++ ++config RTL8366S_PHY ++ tristate "Driver for the Realtek RTL8366S switch" ++ select SWCONFIG ++ ++config RTL8366RB_PHY ++ tristate "Driver for the Realtek RTL8366RB switch" ++ select SWCONFIG ++ ++endif # RTL8366_SMI ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -24,6 +24,9 @@ obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o + obj-$(CONFIG_RTL8306_PHY) += rtl8306.o ++obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o ++obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o ++obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-3.18/727-phy-rtl8367.patch b/target/linux/generic/patches-3.18/727-phy-rtl8367.patch new file mode 100644 index 0000000..8481b58 --- /dev/null +++ b/target/linux/generic/patches-3.18/727-phy-rtl8367.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -272,6 +272,10 @@ config RTL8366RB_PHY + tristate "Driver for the Realtek RTL8366RB switch" + select SWCONFIG + ++config RTL8367_PHY ++ tristate "Driver for the Realtek RTL8367R/M switches" ++ select SWCONFIG ++ + endif # RTL8366_SMI + + endif # PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_RTL8306_PHY) += rtl8306.o + obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o + obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o + obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o ++obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-3.18/728-phy-rtl8367b.patch b/target/linux/generic/patches-3.18/728-phy-rtl8367b.patch new file mode 100644 index 0000000..958ff58 --- /dev/null +++ b/target/linux/generic/patches-3.18/728-phy-rtl8367b.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -276,6 +276,10 @@ config RTL8367_PHY + tristate "Driver for the Realtek RTL8367R/M switches" + select SWCONFIG + ++config RTL8367B_PHY ++ tristate "Driver fot the Realtek RTL8367R-VB switch" ++ select SWCONFIG ++ + endif # RTL8366_SMI + + endif # PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -28,6 +28,7 @@ obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi + obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o + obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o ++obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-3.18/729-phy-tantos.patch b/target/linux/generic/patches-3.18/729-phy-tantos.patch new file mode 100644 index 0000000..019f919 --- /dev/null +++ b/target/linux/generic/patches-3.18/729-phy-tantos.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -287,3 +287,8 @@ endif # PHYLIB + config MICREL_KS8995MA + tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch" + depends on SPI ++ ++config PSB6970_PHY ++ tristate "Lantiq XWAY Tantos (PSB6970) Ethernet switch" ++ select SWCONFIG ++ select ETHERNET_PACKET_MANGLE +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -30,6 +30,7 @@ obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o ++obj-$(CONFIG_PSB6970_PHY) += psb6970.o + obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/generic/patches-3.18/730-phy_b53.patch b/target/linux/generic/patches-3.18/730-phy_b53.patch new file mode 100644 index 0000000..c2dfcfa --- /dev/null +++ b/target/linux/generic/patches-3.18/730-phy_b53.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -282,6 +282,8 @@ config RTL8367B_PHY + + endif # RTL8366_SMI + ++source "drivers/net/phy/b53/Kconfig" ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -31,6 +31,7 @@ obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_PSB6970_PHY) += psb6970.o ++obj-$(CONFIG_B53) += b53/ + obj-$(CONFIG_FIXED_PHY) += fixed.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/generic/patches-3.18/731-phy_mvswitch_3.10_compilation.patch b/target/linux/generic/patches-3.18/731-phy_mvswitch_3.10_compilation.patch new file mode 100644 index 0000000..2053bd2 --- /dev/null +++ b/target/linux/generic/patches-3.18/731-phy_mvswitch_3.10_compilation.patch @@ -0,0 +1,35 @@ +From e6a5abb9a02be0bceb4782d9f736bfb4ae217505 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Sep 2013 13:56:51 +0200 +Subject: [PATCH] phy: mvswitch: fix 3.10 compilation + +Update to API changes in 3.10. + +Signed-off-by: Jonas Gorsi +--- + target/linux/generic/files/drivers/net/phy/mvswitch.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mvswitch.c ++++ b/drivers/net/phy/mvswitch.c +@@ -173,7 +173,7 @@ mvswitch_mangle_rx(struct net_device *de + if (vlan == -1) + return; + +- __vlan_hwaccel_put_tag(skb, vlan); ++ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan); + } + + +@@ -307,9 +307,9 @@ mvswitch_config_init(struct phy_device * + + #ifdef HEADER_MODE + dev->priv_flags |= IFF_NO_IP_ALIGN; +- dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; + #else +- dev->features |= NETIF_F_HW_VLAN_RX; ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX; + #endif + + return 0; diff --git a/target/linux/generic/patches-3.18/732-phy-ar8216-led-support.patch b/target/linux/generic/patches-3.18/732-phy-ar8216-led-support.patch new file mode 100644 index 0000000..c753967 --- /dev/null +++ b/target/linux/generic/patches-3.18/732-phy-ar8216-led-support.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -152,6 +152,10 @@ config AR8216_PHY + select ETHERNET_PACKET_MANGLE + select SWCONFIG + ++config AR8216_PHY_LEDS ++ bool "Atheros AR8216 switch LED support" ++ depends on (AR8216_PHY && LEDS_CLASS) ++ + config RTL8306_PHY + tristate "Driver for Realtek RTL8306S switches" + select SWCONFIG diff --git a/target/linux/generic/patches-3.18/733-phy_mvsw61xx.patch b/target/linux/generic/patches-3.18/733-phy_mvsw61xx.patch new file mode 100644 index 0000000..041d168 --- /dev/null +++ b/target/linux/generic/patches-3.18/733-phy_mvsw61xx.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -143,6 +143,10 @@ config MVSWITCH_PHY + tristate "Driver for Marvell 88E6060 switches" + select ETHERNET_PACKET_MANGLE + ++config MVSW61XX_PHY ++ tristate "Driver for Marvell 88E6171/6172 switches" ++ select SWCONFIG ++ + config IP17XX_PHY + tristate "Driver for IC+ IP17xx switches" + select SWCONFIG +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o ++obj-$(CONFIG_MVSW61XX_PHY) += mvsw61xx.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o diff --git a/target/linux/generic/patches-3.18/750-hostap_txpower.patch b/target/linux/generic/patches-3.18/750-hostap_txpower.patch new file mode 100644 index 0000000..768c80f --- /dev/null +++ b/target/linux/generic/patches-3.18/750-hostap_txpower.patch @@ -0,0 +1,154 @@ +--- a/drivers/net/wireless/hostap/hostap_ap.c ++++ b/drivers/net/wireless/hostap/hostap_ap.c +@@ -2403,13 +2403,13 @@ int prism2_ap_get_sta_qual(local_info_t + addr[count].sa_family = ARPHRD_ETHER; + memcpy(addr[count].sa_data, sta->addr, ETH_ALEN); + if (sta->last_rx_silence == 0) +- qual[count].qual = sta->last_rx_signal < 27 ? +- 0 : (sta->last_rx_signal - 27) * 92 / 127; ++ qual[count].qual = (sta->last_rx_signal - 156) == 0 ? ++ 0 : (sta->last_rx_signal - 156) * 92 / 64; + else +- qual[count].qual = sta->last_rx_signal - +- sta->last_rx_silence - 35; +- qual[count].level = HFA384X_LEVEL_TO_dBm(sta->last_rx_signal); +- qual[count].noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); ++ qual[count].qual = (sta->last_rx_signal - ++ sta->last_rx_silence) * 92 / 64; ++ qual[count].level = sta->last_rx_signal; ++ qual[count].noise = sta->last_rx_silence; + qual[count].updated = sta->last_rx_updated; + + sta->last_rx_updated = IW_QUAL_DBM; +@@ -2475,13 +2475,13 @@ int prism2_ap_translate_scan(struct net_ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + if (sta->last_rx_silence == 0) +- iwe.u.qual.qual = sta->last_rx_signal < 27 ? +- 0 : (sta->last_rx_signal - 27) * 92 / 127; ++ iwe.u.qual.qual = (sta->last_rx_signal -156) == 0 ? ++ 0 : (sta->last_rx_signal - 156) * 92 / 64; + else +- iwe.u.qual.qual = sta->last_rx_signal - +- sta->last_rx_silence - 35; +- iwe.u.qual.level = HFA384X_LEVEL_TO_dBm(sta->last_rx_signal); +- iwe.u.qual.noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); ++ iwe.u.qual.qual = (sta->last_rx_signal - ++ sta->last_rx_silence) * 92 / 64; ++ iwe.u.qual.level = sta->last_rx_signal; ++ iwe.u.qual.noise = sta->last_rx_silence; + iwe.u.qual.updated = sta->last_rx_updated; + iwe.len = IW_EV_QUAL_LEN; + current_ev = iwe_stream_add_event(info, current_ev, end_buf, +--- a/drivers/net/wireless/hostap/hostap_config.h ++++ b/drivers/net/wireless/hostap/hostap_config.h +@@ -45,4 +45,9 @@ + */ + /* #define PRISM2_NO_STATION_MODES */ + ++/* Enable TX power Setting functions ++ * (min att = -128 , max att = 127) ++ */ ++#define RAW_TXPOWER_SETTING ++ + #endif /* HOSTAP_CONFIG_H */ +--- a/drivers/net/wireless/hostap/hostap.h ++++ b/drivers/net/wireless/hostap/hostap.h +@@ -90,6 +90,7 @@ extern const struct iw_handler_def hosta + extern const struct ethtool_ops prism2_ethtool_ops; + + int hostap_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); ++int hostap_restore_power(struct net_device *dev); + + + #endif /* HOSTAP_H */ +--- a/drivers/net/wireless/hostap/hostap_hw.c ++++ b/drivers/net/wireless/hostap/hostap_hw.c +@@ -928,6 +928,7 @@ static int hfa384x_set_rid(struct net_de + prism2_hw_reset(dev); + } + ++ hostap_restore_power(dev); + return res; + } + +--- a/drivers/net/wireless/hostap/hostap_info.c ++++ b/drivers/net/wireless/hostap/hostap_info.c +@@ -435,6 +435,11 @@ static void handle_info_queue_linkstatus + } + + /* Get BSSID if we have a valid AP address */ ++ ++ if ( val == HFA384X_LINKSTATUS_CONNECTED || ++ val == HFA384X_LINKSTATUS_DISCONNECTED ) ++ hostap_restore_power(local->dev); ++ + if (connected) { + netif_carrier_on(local->dev); + netif_carrier_on(local->ddev); +--- a/drivers/net/wireless/hostap/hostap_ioctl.c ++++ b/drivers/net/wireless/hostap/hostap_ioctl.c +@@ -1479,23 +1479,20 @@ static int prism2_txpower_hfa386x_to_dBm + val = 255; + + tmp = val; +- tmp >>= 2; + +- return -12 - tmp; ++ return tmp; + } + + static u16 prism2_txpower_dBm_to_hfa386x(int val) + { + signed char tmp; + +- if (val > 20) +- return 128; +- else if (val < -43) ++ if (val > 127) + return 127; ++ else if (val < -128) ++ return 128; + + tmp = val; +- tmp = -12 - tmp; +- tmp <<= 2; + + return (unsigned char) tmp; + } +@@ -4052,3 +4049,35 @@ int hostap_ioctl(struct net_device *dev, + + return ret; + } ++ ++/* BUG FIX: Restore power setting value when lost due to F/W bug */ ++ ++int hostap_restore_power(struct net_device *dev) ++{ ++ struct hostap_interface *iface = netdev_priv(dev); ++ local_info_t *local = iface->local; ++ ++ u16 val; ++ int ret = 0; ++ ++ if (local->txpower_type == PRISM2_TXPOWER_OFF) { ++ val = 0xff; /* use all standby and sleep modes */ ++ ret = local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, ++ HFA386X_CR_A_D_TEST_MODES2, ++ &val, NULL); ++ } ++ ++#ifdef RAW_TXPOWER_SETTING ++ if (local->txpower_type == PRISM2_TXPOWER_FIXED) { ++ val = HFA384X_TEST_CFG_BIT_ALC; ++ local->func->cmd(dev, HFA384X_CMDCODE_TEST | ++ (HFA384X_TEST_CFG_BITS << 8), 0, &val, NULL); ++ val = prism2_txpower_dBm_to_hfa386x(local->txpower); ++ ret = (local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, ++ HFA386X_CR_MANUAL_TX_POWER, &val, NULL)); ++ } ++#endif /* RAW_TXPOWER_SETTING */ ++ return (ret ? -EOPNOTSUPP : 0); ++} ++ ++EXPORT_SYMBOL(hostap_restore_power); diff --git a/target/linux/generic/patches-3.18/760-8139cp-fixes-from-4.3.patch b/target/linux/generic/patches-3.18/760-8139cp-fixes-from-4.3.patch new file mode 100644 index 0000000..7051843 --- /dev/null +++ b/target/linux/generic/patches-3.18/760-8139cp-fixes-from-4.3.patch @@ -0,0 +1,365 @@ +commit 41b976414c88016e2c9d9b2f6667ee67a998d388 +Author: David Woodhouse +Date: Wed Sep 23 09:45:31 2015 +0100 + + 8139cp: Dump contents of descriptor ring on TX timeout + + We are seeing unexplained TX timeouts under heavy load. Let's try to get + a better idea of what's going on. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 7f4c685633e2df9ba10d49a31dda13715745db37 +Author: David Woodhouse +Date: Wed Sep 23 09:45:16 2015 +0100 + + 8139cp: Fix DMA unmapping of transmitted buffers + + The low 16 bits of the 'opts1' field in the TX descriptor are supposed + to still contain the buffer length when the descriptor is handed back to + us. In practice, at least on my hardware, they don't. So stash the + original value of the opts1 field and get the length to unmap from + there. + + There are other ways we could have worked out the length, but I actually + want a stash of the opts1 field anyway so that I can dump it alongside + the contents of the descriptor ring when we suffer a TX timeout. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 0a5aeee0b79fa99d8e04c98dd4e87d4f52aa497b +Author: David Woodhouse +Date: Wed Sep 23 09:44:57 2015 +0100 + + 8139cp: Reduce duplicate csum/tso code in cp_start_xmit() + + We calculate the value of the opts1 descriptor field in three different + places. With two different behaviours when given an invalid packet to + be checksummed — none of them correct. Sort that out. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit a3b804043f490aeec57d8ca5baccdd35e6250857 +Author: David Woodhouse +Date: Wed Sep 23 09:44:38 2015 +0100 + + 8139cp: Fix TSO/scatter-gather descriptor setup + + When sending a TSO frame in multiple buffers, we were neglecting to set + the first descriptor up in TSO mode. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 26b0bad6ac3a0167792dc4ffb276c29bc597d239 +Author: David Woodhouse +Date: Wed Sep 23 09:44:06 2015 +0100 + + 8139cp: Fix tx_queued debug message to print correct slot numbers + + After a certain amount of staring at the debug output of this driver, I + realised it was lying to me. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit aaa0062ecf4877a26dea66bee1039c6eaf906c94 +Author: David Woodhouse +Date: Wed Sep 23 09:43:41 2015 +0100 + + 8139cp: Do not re-enable RX interrupts in cp_tx_timeout() + + If an RX interrupt was already received but NAPI has not yet run when + the RX timeout happens, we end up in cp_tx_timeout() with RX interrupts + already disabled. Blindly re-enabling them will cause an IRQ storm. + + (This is made particularly horrid by the fact that cp_interrupt() always + returns that it's handled the interrupt, even when it hasn't actually + done anything. If it didn't do that, the core IRQ code would have + detected the storm and handled it, I'd have had a clear smoking gun + backtrace instead of just a spontaneously resetting router, and I'd have + at *least* two days of my life back. Changing the return value of + cp_interrupt() will be argued about under separate cover.) + + Unconditionally leave RX interrupts disabled after the reset, and + schedule NAPI to check the receive ring and re-enable them. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 7a8a8e75d505147358b225173e890ada43a267e2 +Author: David Woodhouse +Date: Fri Sep 18 00:21:54 2015 +0100 + + 8139cp: Call __cp_set_rx_mode() from cp_tx_timeout() + + Unless we reset the RX config, on real hardware I don't seem to receive + any packets after a TX timeout. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit fc27bd115b334e3ebdc682a42a47c3aea2566dcc +Author: David Woodhouse +Date: Fri Sep 18 00:19:08 2015 +0100 + + 8139cp: Use dev_kfree_skb_any() instead of dev_kfree_skb() in cp_clean_rings() + + This can be called from cp_tx_timeout() with interrupts disabled. + Spotted by Francois Romieu + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller +--- a/drivers/net/ethernet/realtek/8139cp.c ++++ b/drivers/net/ethernet/realtek/8139cp.c +@@ -157,6 +157,7 @@ enum { + NWayAdvert = 0x66, /* MII ADVERTISE */ + NWayLPAR = 0x68, /* MII LPA */ + NWayExpansion = 0x6A, /* MII Expansion */ ++ TxDmaOkLowDesc = 0x82, /* Low 16 bit address of a Tx descriptor. */ + Config5 = 0xD8, /* Config5 */ + TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ + RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ +@@ -341,6 +342,7 @@ struct cp_private { + unsigned tx_tail; + struct cp_desc *tx_ring; + struct sk_buff *tx_skb[CP_TX_RING_SIZE]; ++ u32 tx_opts[CP_TX_RING_SIZE]; + + unsigned rx_buf_sz; + unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */ +@@ -665,7 +667,7 @@ static void cp_tx (struct cp_private *cp + BUG_ON(!skb); + + dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr), +- le32_to_cpu(txd->opts1) & 0xffff, ++ cp->tx_opts[tx_tail] & 0xffff, + PCI_DMA_TODEVICE); + + if (status & LastFrag) { +@@ -733,7 +735,7 @@ static netdev_tx_t cp_start_xmit (struct + { + struct cp_private *cp = netdev_priv(dev); + unsigned entry; +- u32 eor, flags; ++ u32 eor, opts1; + unsigned long intr_flags; + __le32 opts2; + int mss = 0; +@@ -753,6 +755,21 @@ static netdev_tx_t cp_start_xmit (struct + mss = skb_shinfo(skb)->gso_size; + + opts2 = cpu_to_le32(cp_tx_vlan_tag(skb)); ++ opts1 = DescOwn; ++ if (mss) ++ opts1 |= LargeSend | ((mss & MSSMask) << MSSShift); ++ else if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ const struct iphdr *ip = ip_hdr(skb); ++ if (ip->protocol == IPPROTO_TCP) ++ opts1 |= IPCS | TCPCS; ++ else if (ip->protocol == IPPROTO_UDP) ++ opts1 |= IPCS | UDPCS; ++ else { ++ WARN_ONCE(1, ++ "Net bug: asked to checksum invalid Legacy IP packet\n"); ++ goto out_dma_error; ++ } ++ } + + if (skb_shinfo(skb)->nr_frags == 0) { + struct cp_desc *txd = &cp->tx_ring[entry]; +@@ -768,31 +785,20 @@ static netdev_tx_t cp_start_xmit (struct + txd->addr = cpu_to_le64(mapping); + wmb(); + +- flags = eor | len | DescOwn | FirstFrag | LastFrag; +- +- if (mss) +- flags |= LargeSend | ((mss & MSSMask) << MSSShift); +- else if (skb->ip_summed == CHECKSUM_PARTIAL) { +- const struct iphdr *ip = ip_hdr(skb); +- if (ip->protocol == IPPROTO_TCP) +- flags |= IPCS | TCPCS; +- else if (ip->protocol == IPPROTO_UDP) +- flags |= IPCS | UDPCS; +- else +- WARN_ON(1); /* we need a WARN() */ +- } ++ opts1 |= eor | len | FirstFrag | LastFrag; + +- txd->opts1 = cpu_to_le32(flags); ++ txd->opts1 = cpu_to_le32(opts1); + wmb(); + + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); ++ cp->tx_opts[entry] = opts1; ++ netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n", ++ entry, skb->len); + } else { + struct cp_desc *txd; +- u32 first_len, first_eor; ++ u32 first_len, first_eor, ctrl; + dma_addr_t first_mapping; + int frag, first_entry = entry; +- const struct iphdr *ip = ip_hdr(skb); + + /* We must give this initial chunk to the device last. + * Otherwise we could race with the device. +@@ -805,14 +811,14 @@ static netdev_tx_t cp_start_xmit (struct + goto out_dma_error; + + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); + + for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { + const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; + u32 len; +- u32 ctrl; + dma_addr_t mapping; + ++ entry = NEXT_TX(entry); ++ + len = skb_frag_size(this_frag); + mapping = dma_map_single(&cp->pdev->dev, + skb_frag_address(this_frag), +@@ -824,19 +830,7 @@ static netdev_tx_t cp_start_xmit (struct + + eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; + +- ctrl = eor | len | DescOwn; +- +- if (mss) +- ctrl |= LargeSend | +- ((mss & MSSMask) << MSSShift); +- else if (skb->ip_summed == CHECKSUM_PARTIAL) { +- if (ip->protocol == IPPROTO_TCP) +- ctrl |= IPCS | TCPCS; +- else if (ip->protocol == IPPROTO_UDP) +- ctrl |= IPCS | UDPCS; +- else +- BUG(); +- } ++ ctrl = opts1 | eor | len; + + if (frag == skb_shinfo(skb)->nr_frags - 1) + ctrl |= LastFrag; +@@ -849,8 +843,8 @@ static netdev_tx_t cp_start_xmit (struct + txd->opts1 = cpu_to_le32(ctrl); + wmb(); + ++ cp->tx_opts[entry] = ctrl; + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); + } + + txd = &cp->tx_ring[first_entry]; +@@ -858,27 +852,17 @@ static netdev_tx_t cp_start_xmit (struct + txd->addr = cpu_to_le64(first_mapping); + wmb(); + +- if (skb->ip_summed == CHECKSUM_PARTIAL) { +- if (ip->protocol == IPPROTO_TCP) +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn | +- IPCS | TCPCS); +- else if (ip->protocol == IPPROTO_UDP) +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn | +- IPCS | UDPCS); +- else +- BUG(); +- } else +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn); ++ ctrl = opts1 | first_eor | first_len | FirstFrag; ++ txd->opts1 = cpu_to_le32(ctrl); + wmb(); ++ ++ cp->tx_opts[first_entry] = ctrl; ++ netif_dbg(cp, tx_queued, cp->dev, "tx queued, slots %d-%d, skblen %d\n", ++ first_entry, entry, skb->len); + } +- cp->tx_head = entry; ++ cp->tx_head = NEXT_TX(entry); + + netdev_sent_queue(dev, skb->len); +- netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n", +- entry, skb->len); + if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1)) + netif_stop_queue(dev); + +@@ -1115,6 +1099,7 @@ static int cp_init_rings (struct cp_priv + { + memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); + cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd); ++ memset(cp->tx_opts, 0, sizeof(cp->tx_opts)); + + cp_init_rings_index(cp); + +@@ -1151,7 +1136,7 @@ static void cp_clean_rings (struct cp_pr + desc = cp->rx_ring + i; + dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr), + cp->rx_buf_sz, PCI_DMA_FROMDEVICE); +- dev_kfree_skb(cp->rx_skb[i]); ++ dev_kfree_skb_any(cp->rx_skb[i]); + } + } + +@@ -1164,7 +1149,7 @@ static void cp_clean_rings (struct cp_pr + le32_to_cpu(desc->opts1) & 0xffff, + PCI_DMA_TODEVICE); + if (le32_to_cpu(desc->opts1) & LastFrag) +- dev_kfree_skb(skb); ++ dev_kfree_skb_any(skb); + cp->dev->stats.tx_dropped++; + } + } +@@ -1172,6 +1157,7 @@ static void cp_clean_rings (struct cp_pr + + memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE); + memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); ++ memset(cp->tx_opts, 0, sizeof(cp->tx_opts)); + + memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE); + memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE); +@@ -1249,7 +1235,7 @@ static void cp_tx_timeout(struct net_dev + { + struct cp_private *cp = netdev_priv(dev); + unsigned long flags; +- int rc; ++ int rc, i; + + netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n", + cpr8(Cmd), cpr16(CpCmd), +@@ -1257,13 +1243,26 @@ static void cp_tx_timeout(struct net_dev + + spin_lock_irqsave(&cp->lock, flags); + ++ netif_dbg(cp, tx_err, cp->dev, "TX ring head %d tail %d desc %x\n", ++ cp->tx_head, cp->tx_tail, cpr16(TxDmaOkLowDesc)); ++ for (i = 0; i < CP_TX_RING_SIZE; i++) { ++ netif_dbg(cp, tx_err, cp->dev, ++ "TX slot %d @%p: %08x (%08x) %08x %llx %p\n", ++ i, &cp->tx_ring[i], le32_to_cpu(cp->tx_ring[i].opts1), ++ cp->tx_opts[i], le32_to_cpu(cp->tx_ring[i].opts2), ++ le64_to_cpu(cp->tx_ring[i].addr), ++ cp->tx_skb[i]); ++ } ++ + cp_stop_hw(cp); + cp_clean_rings(cp); + rc = cp_init_rings(cp); + cp_start_hw(cp); +- cp_enable_irq(cp); ++ __cp_set_rx_mode(dev); ++ cpw16_f(IntrMask, cp_norx_intr_mask); + + netif_wake_queue(dev); ++ napi_schedule(&cp->napi); + + spin_unlock_irqrestore(&cp->lock, flags); + } diff --git a/target/linux/generic/patches-3.18/773-bgmac-add-srab-switch.patch b/target/linux/generic/patches-3.18/773-bgmac-add-srab-switch.patch new file mode 100644 index 0000000..b883d73 --- /dev/null +++ b/target/linux/generic/patches-3.18/773-bgmac-add-srab-switch.patch @@ -0,0 +1,72 @@ +Register switch connected to srab + +Signed-off-by: Hauke Mehrtens + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + static const struct bcma_device_id bgmac_bcma_tbl[] = { +@@ -1538,6 +1539,17 @@ static void bgmac_mii_unregister(struct + mdiobus_free(mii_bus); + } + ++static struct b53_platform_data bgmac_b53_pdata = { ++}; ++ ++static struct platform_device bgmac_b53_dev = { ++ .name = "b53-srab-switch", ++ .id = -1, ++ .dev = { ++ .platform_data = &bgmac_b53_pdata, ++ }, ++}; ++ + /************************************************** + * BCMA bus ops + **************************************************/ +@@ -1664,6 +1676,16 @@ static int bgmac_probe(struct bcma_devic + net_dev->hw_features = net_dev->features; + net_dev->vlan_features = net_dev->features; + ++ if ((ci->id == BCMA_CHIP_ID_BCM4707 || ++ ci->id == BCMA_CHIP_ID_BCM53018) && ++ !bgmac_b53_pdata.regs) { ++ bgmac_b53_pdata.regs = ioremap_nocache(0x18007000, 0x1000); ++ ++ err = platform_device_register(&bgmac_b53_dev); ++ if (!err) ++ bgmac->b53_device = &bgmac_b53_dev; ++ } ++ + err = register_netdev(bgmac->net_dev); + if (err) { + bgmac_err(bgmac, "Cannot register net device\n"); +@@ -1690,6 +1712,10 @@ static void bgmac_remove(struct bcma_dev + { + struct bgmac *bgmac = bcma_get_drvdata(core); + ++ if (bgmac->b53_device) ++ platform_device_unregister(&bgmac_b53_dev); ++ bgmac->b53_device = NULL; ++ + unregister_netdev(bgmac->net_dev); + bgmac_mii_unregister(bgmac); + netif_napi_del(&bgmac->napi); +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -462,6 +462,9 @@ struct bgmac { + bool has_robosw; + + bool loopback; ++ ++ /* platform device for associated switch */ ++ struct platform_device *b53_device; + }; + + static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset) diff --git a/target/linux/generic/patches-3.18/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch b/target/linux/generic/patches-3.18/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch new file mode 100644 index 0000000..e541b2c --- /dev/null +++ b/target/linux/generic/patches-3.18/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch @@ -0,0 +1,40 @@ +From cb06d102327eadcd1bdc480bfd9f8876251d1007 Mon Sep 17 00:00:00 2001 +From: Christoph Paasch +Date: Fri, 21 Mar 2014 03:48:19 -0700 +Subject: [PATCH] igb: Fix Null-pointer dereference in igb_reset_q_vector + +When igb_set_interrupt_capability() calls +igb_reset_interrupt_capability() (e.g., because CONFIG_PCI_MSI is unset), +num_q_vectors has been set but no vector has yet been allocated. + +igb_reset_interrupt_capability() will then call igb_reset_q_vector, +which assumes that the vector is allocated. As this is not the case, we +are accessing a NULL-pointer. + +This patch fixes it by checking that q_vector is indeed different from +NULL. + +Fixes: 02ef6e1d0b0023 (igb: Fix queue allocation method to accommodate changing during runtime) +Cc: Carolyn Wyborny +Signed-off-by: Christoph Paasch +Tested-by: Jeff Pieper +Signed-off-by: Jeff Kirsher +--- + drivers/net/ethernet/intel/igb/igb_main.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/ethernet/intel/igb/igb_main.c ++++ b/drivers/net/ethernet/intel/igb/igb_main.c +@@ -1034,6 +1034,12 @@ static void igb_reset_q_vector(struct ig + if (!q_vector) + return; + ++ /* Coming from igb_set_interrupt_capability, the vectors are not yet ++ * allocated. So, q_vector is NULL so we should stop here. ++ */ ++ if (!q_vector) ++ return; ++ + if (q_vector->tx.ring) + adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; + diff --git a/target/linux/generic/patches-3.18/785-hso-support-0af0-9300.patch b/target/linux/generic/patches-3.18/785-hso-support-0af0-9300.patch new file mode 100644 index 0000000..50bccc4 --- /dev/null +++ b/target/linux/generic/patches-3.18/785-hso-support-0af0-9300.patch @@ -0,0 +1,25 @@ +--- a/drivers/net/usb/hso.c ++++ b/drivers/net/usb/hso.c +@@ -468,6 +468,7 @@ static const struct usb_device_id hso_id + {USB_DEVICE(0x0af0, 0x8900)}, + {USB_DEVICE(0x0af0, 0x9000)}, + {USB_DEVICE(0x0af0, 0x9200)}, /* Option GTM671WFS */ ++ {USB_DEVICE(0x0af0, 0x9300)}, /* GTM 66xxWFS */ + {USB_DEVICE(0x0af0, 0xd035)}, + {USB_DEVICE(0x0af0, 0xd055)}, + {USB_DEVICE(0x0af0, 0xd155)}, +--- a/drivers/usb/storage/unusual_devs.h ++++ b/drivers/usb/storage/unusual_devs.h +@@ -1330,6 +1330,12 @@ UNUSUAL_DEV( 0x0af0, 0x8304, 0x0000, 0x0 + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + 0 ), + ++UNUSUAL_DEV( 0x0af0, 0x9300, 0x0000, 0x0000, ++ "Option", ++ "Globetrotter 66xxWFS SD-Card", ++ USB_SC_DEVICE, USB_PR_DEVICE, NULL, ++ 0 ), ++ + UNUSUAL_DEV( 0x0af0, 0xc100, 0x0000, 0x0000, + "Option", + "GI 070x SD-Card", diff --git a/target/linux/generic/patches-3.18/810-pci_disable_common_quirks.patch b/target/linux/generic/patches-3.18/810-pci_disable_common_quirks.patch new file mode 100644 index 0000000..b9b3e0a --- /dev/null +++ b/target/linux/generic/patches-3.18/810-pci_disable_common_quirks.patch @@ -0,0 +1,51 @@ +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -58,6 +58,12 @@ config XEN_PCIDEV_FRONTEND + The PCI device frontend driver allows the kernel to import arbitrary + PCI devices from a PCI backend to support PCI driver domains. + ++config PCI_DISABLE_COMMON_QUIRKS ++ bool "PCI disable common quirks" ++ depends on PCI ++ help ++ If you don't know what to do here, say N. ++ + config HT_IRQ + bool "Interrupts on hypertransport devices" + default y +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -41,6 +41,7 @@ static void quirk_mmio_always_on(struct + DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS + /* The Mellanox Tavor device gives false positive parity errors + * Mark this device with a broken_parity_status, to allow + * PCI scanning code to "skip" this now blacklisted device. +@@ -2908,6 +2909,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); + ++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ + + /* + * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To +@@ -2964,6 +2966,8 @@ static void fixup_debug_report(struct pc + } + } + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + /* + * Some BIOS implementations leave the Intel GPU interrupts enabled, + * even though no one is handling them (f.e. i915 driver is never loaded). +@@ -2998,6 +3002,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); + ++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ ++ + /* + * PCI devices which are on Intel chips can skip the 10ms delay + * before entering D3 mode. diff --git a/target/linux/generic/patches-3.18/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/patches-3.18/811-pci_disable_usb_common_quirks.patch new file mode 100644 index 0000000..b54d150 --- /dev/null +++ b/target/linux/generic/patches-3.18/811-pci_disable_usb_common_quirks.patch @@ -0,0 +1,101 @@ + +--- a/drivers/usb/host/pci-quirks.c ++++ b/drivers/usb/host/pci-quirks.c +@@ -97,6 +97,8 @@ struct amd_chipset_type { + u8 rev; + }; + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + static struct amd_chipset_info { + struct pci_dev *nb_dev; + struct pci_dev *smbus_dev; +@@ -454,6 +456,10 @@ void usb_amd_dev_put(void) + } + EXPORT_SYMBOL_GPL(usb_amd_dev_put); + ++#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */ ++ ++#if IS_ENABLED(CONFIG_USB_UHCI_HCD) ++ + /* + * Make sure the controller is completely inactive, unable to + * generate interrupts or do DMA. +@@ -533,8 +539,17 @@ reset_needed: + uhci_reset_hc(pdev, base); + return 1; + } ++#else ++int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) ++{ ++ return 0; ++} ++ ++#endif + EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) + { + u16 cmd; +@@ -1095,3 +1110,4 @@ static void quirk_usb_early_handoff(stru + } + DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); ++#endif +--- a/drivers/usb/host/pci-quirks.h ++++ b/drivers/usb/host/pci-quirks.h +@@ -4,6 +4,9 @@ + #ifdef CONFIG_PCI + void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); + int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); ++#endif /* CONFIG_PCI */ ++ ++#if defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_COMMON_QUIRKS) + int usb_amd_find_chipset_info(void); + int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev); + bool usb_amd_hang_symptom_quirk(void); +@@ -16,11 +19,24 @@ void usb_disable_xhci_ports(struct pci_d + void sb800_prefetch(struct device *dev, int on); + #else + struct pci_dev; ++static inline int usb_amd_find_chipset_info(void) ++{ ++ return 0; ++} ++static inline bool usb_amd_hang_symptom_quirk(void) ++{ ++ return false; ++} ++static inline bool usb_amd_prefetch_quirk(void) ++{ ++ return false; ++} + static inline void usb_amd_quirk_pll_disable(void) {} + static inline void usb_amd_quirk_pll_enable(void) {} + static inline void usb_amd_dev_put(void) {} + static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {} + static inline void sb800_prefetch(struct device *dev, int on) {} +-#endif /* CONFIG_PCI */ ++static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {} ++#endif + + #endif /* __LINUX_USB_PCI_QUIRKS_H */ +--- a/include/linux/usb/hcd.h ++++ b/include/linux/usb/hcd.h +@@ -444,7 +444,14 @@ extern int usb_hcd_pci_probe(struct pci_ + extern void usb_hcd_pci_remove(struct pci_dev *dev); + extern void usb_hcd_pci_shutdown(struct pci_dev *dev); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS + extern int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev); ++#else ++static inline int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev) ++{ ++ return 0; ++} ++#endif + + #ifdef CONFIG_PM + extern const struct dev_pm_ops usb_hcd_pci_pm_ops; diff --git a/target/linux/generic/patches-3.18/820-usb_add_usb_find_device_by_name.patch b/target/linux/generic/patches-3.18/820-usb_add_usb_find_device_by_name.patch new file mode 100644 index 0000000..e381cc9 --- /dev/null +++ b/target/linux/generic/patches-3.18/820-usb_add_usb_find_device_by_name.patch @@ -0,0 +1,84 @@ +--- a/drivers/usb/core/usb.c ++++ b/drivers/usb/core/usb.c +@@ -690,6 +690,71 @@ int __usb_get_extra_descriptor(char *buf + } + EXPORT_SYMBOL_GPL(__usb_get_extra_descriptor); + ++static struct usb_device *match_device_name(struct usb_device *dev, ++ const char *name) ++{ ++ struct usb_device *ret_dev = NULL; ++ struct usb_device *childdev = NULL; ++ int child; ++ ++ dev_dbg(&dev->dev, "check for name %s ...\n", name); ++ ++ /* see if this device matches */ ++ if (strcmp(dev_name(&dev->dev), name) == 0 ) { ++ dev_dbg(&dev->dev, "matched this device!\n"); ++ ret_dev = usb_get_dev(dev); ++ goto exit; ++ } ++ /* look through all of the children of this device */ ++ usb_hub_for_each_child(dev, child, childdev) { ++ if (childdev) { ++ usb_lock_device(childdev); ++ ret_dev = match_device_name(childdev, name); ++ usb_unlock_device(childdev); ++ if (ret_dev) ++ goto exit; ++ } ++ } ++exit: ++ return ret_dev; ++} ++ ++/** ++ * usb_find_device_by_name - find a specific usb device in the system ++ * @name: the name of the device to find ++ * ++ * Returns a pointer to a struct usb_device if such a specified usb ++ * device is present in the system currently. The usage count of the ++ * device will be incremented if a device is found. Make sure to call ++ * usb_put_dev() when the caller is finished with the device. ++ * ++ * If a device with the specified bus id is not found, NULL is returned. ++ */ ++struct usb_device *usb_find_device_by_name(const char *name) ++{ ++ struct list_head *buslist; ++ struct usb_bus *bus; ++ struct usb_device *dev = NULL; ++ ++ mutex_lock(&usb_bus_list_lock); ++ for (buslist = usb_bus_list.next; ++ buslist != &usb_bus_list; ++ buslist = buslist->next) { ++ bus = container_of(buslist, struct usb_bus, bus_list); ++ if (!bus->root_hub) ++ continue; ++ usb_lock_device(bus->root_hub); ++ dev = match_device_name(bus->root_hub, name); ++ usb_unlock_device(bus->root_hub); ++ if (dev) ++ goto exit; ++ } ++exit: ++ mutex_unlock(&usb_bus_list_lock); ++ return dev; ++} ++EXPORT_SYMBOL_GPL(usb_find_device_by_name); ++ + /** + * usb_alloc_coherent - allocate dma-consistent buffer for URB_NO_xxx_DMA_MAP + * @dev: device the buffer will be used with +--- a/include/linux/usb.h ++++ b/include/linux/usb.h +@@ -721,6 +721,7 @@ static inline bool usb_device_no_sg_cons + return udev && udev->bus && udev->bus->no_sg_constraint; + } + ++extern struct usb_device *usb_find_device_by_name(const char *name); + + /*-------------------------------------------------------------------------*/ + diff --git a/target/linux/generic/patches-3.18/821-usb-dwc2-dualrole.patch b/target/linux/generic/patches-3.18/821-usb-dwc2-dualrole.patch new file mode 100644 index 0000000..9e841cb --- /dev/null +++ b/target/linux/generic/patches-3.18/821-usb-dwc2-dualrole.patch @@ -0,0 +1,146 @@ +--- a/drivers/usb/dwc2/Kconfig ++++ b/drivers/usb/dwc2/Kconfig +@@ -1,6 +1,6 @@ + config USB_DWC2 +- bool "DesignWare USB2 DRD Core Support" +- depends on USB ++ tristate "DesignWare USB2 DRD Core Support" ++ depends on USB || USB_GADGET + help + Say Y here if your system has a Dual Role Hi-Speed USB + controller based on the DesignWare HSOTG IP Core. +@@ -10,49 +10,61 @@ config USB_DWC2 + bus interface module (if you have a PCI bus system) will be + called dwc2_pci.ko, and the platform interface module (for + controllers directly connected to the CPU) will be called +- dwc2_platform.ko. For gadget mode, there will be a single +- module called dwc2_gadget.ko. +- +- NOTE: The s3c-hsotg driver is now renamed to dwc2_gadget. The +- host and gadget drivers are still currently separate drivers. +- There are plans to merge the dwc2_gadget driver with the dwc2 +- host driver in the near future to create a dual-role driver. ++ dwc2_platform.ko. For all modes(host, gadget and dual-role), there ++ will be an additional module named dwc2.ko. + + if USB_DWC2 + ++choice ++ bool "DWC2 Mode Selection" ++ default USB_DWC2_DUAL_ROLE if (USB && USB_GADGET) ++ default USB_DWC2_HOST if (USB && !USB_GADGET) ++ default USB_DWC2_PERIPHERAL if (!USB && USB_GADGET) ++ + config USB_DWC2_HOST +- tristate "Host only mode" ++ bool "Host only mode" + depends on USB + help + The Designware USB2.0 high-speed host controller +- integrated into many SoCs. ++ integrated into many SoCs. Select this option if you want the ++ driver to operate in Host-only mode. + +-config USB_DWC2_PLATFORM +- bool "DWC2 Platform" +- depends on USB_DWC2_HOST +- default USB_DWC2_HOST ++comment "Gadget/Dual-role mode requires USB Gadget support to be enabled" ++ ++config USB_DWC2_PERIPHERAL ++ bool "Gadget only mode" ++ depends on USB_GADGET=y || USB_GADGET=USB_DWC2 ++ help ++ The Designware USB2.0 high-speed gadget controller ++ integrated into many SoCs. Select this option if you want the ++ driver to operate in Peripheral-only mode. This option requires ++ USB_GADGET to be enabled. ++ ++config USB_DWC2_DUAL_ROLE ++ bool "Dual Role mode" ++ depends on (USB=y || USB=USB_DWC2) && (USB_GADGET=y || USB_GADGET=USB_DWC2) + help +- The Designware USB2.0 platform interface module for +- controllers directly connected to the CPU. This is only +- used for host mode. ++ Select this option if you want the driver to work in a dual-role ++ mode. In this mode both host and gadget features are enabled, and ++ the role will be determined by the cable that gets plugged-in. This ++ option requires USB_GADGET to be enabled. ++endchoice ++ ++config USB_DWC2_PLATFORM ++ tristate "DWC2 Platform" ++ default USB_DWC2_HOST || USB_DWC2_PERIPHERAL ++ help ++ The Designware USB2.0 platform interface module for ++ controllers directly connected to the CPU. + + config USB_DWC2_PCI +- bool "DWC2 PCI" ++ tristate "DWC2 PCI" + depends on USB_DWC2_HOST && PCI + default USB_DWC2_HOST + help + The Designware USB2.0 PCI interface module for controllers + connected to a PCI bus. This is only used for host mode. + +-comment "Gadget mode requires USB Gadget support to be enabled" +- +-config USB_DWC2_PERIPHERAL +- tristate "Gadget only mode" +- depends on USB_GADGET +- help +- The Designware USB2.0 high-speed gadget controller +- integrated into many SoCs. +- + config USB_DWC2_DEBUG + bool "Enable Debugging Messages" + help +--- a/drivers/usb/dwc2/Makefile ++++ b/drivers/usb/dwc2/Makefile +@@ -1,28 +1,28 @@ + ccflags-$(CONFIG_USB_DWC2_DEBUG) += -DDEBUG + ccflags-$(CONFIG_USB_DWC2_VERBOSE) += -DVERBOSE_DEBUG + +-obj-$(CONFIG_USB_DWC2_HOST) += dwc2.o ++obj-$(CONFIG_USB_DWC2) += dwc2.o + dwc2-y := core.o core_intr.o +-dwc2-y += hcd.o hcd_intr.o +-dwc2-y += hcd_queue.o hcd_ddma.o ++ ++ifneq ($(filter y,$(CONFIG_USB_DWC2_HOST) $(CONFIG_USB_DWC2_DUAL_ROLE)),) ++ dwc2-y += hcd.o hcd_intr.o ++ dwc2-y += hcd_queue.o hcd_ddma.o ++endif ++ ++ifneq ($(filter y,$(CONFIG_USB_DWC2_PERIPHERAL) $(CONFIG_USB_DWC2_DUAL_ROLE)),) ++ dwc2-y += gadget.o ++endif + + # NOTE: The previous s3c-hsotg peripheral mode only driver has been moved to + # this location and renamed gadget.c. When building for dynamically linked +-# modules, dwc2_gadget.ko will get built for peripheral mode. For host mode, +-# the core module will be dwc2.ko, the PCI bus interface module will called +-# dwc2_pci.ko and the platform interface module will be called dwc2_platform.ko. +-# At present the host and gadget driver will be separate drivers, but there +-# are plans in the near future to create a dual-role driver. ++# modules, dwc2.ko will get built for host mode, peripheral mode, and dual-role ++# mode. The PCI bus interface module will called dwc2_pci.ko and the platform ++# interface module will be called dwc2_platform.ko. + + ifneq ($(CONFIG_USB_DWC2_PCI),) +- obj-$(CONFIG_USB_DWC2_HOST) += dwc2_pci.o ++ obj-$(CONFIG_USB_DWC2) += dwc2_pci.o + dwc2_pci-y := pci.o + endif + +-ifneq ($(CONFIG_USB_DWC2_PLATFORM),) +- obj-$(CONFIG_USB_DWC2_HOST) += dwc2_platform.o +- dwc2_platform-y := platform.o +-endif +- +-obj-$(CONFIG_USB_DWC2_PERIPHERAL) += dwc2_gadget.o +-dwc2_gadget-y := gadget.o ++obj-$(CONFIG_USB_DWC2_PLATFORM) += dwc2_platform.o ++dwc2_platform-y := platform.o diff --git a/target/linux/generic/patches-3.18/830-ledtrig_morse.patch b/target/linux/generic/patches-3.18/830-ledtrig_morse.patch new file mode 100644 index 0000000..a41facc --- /dev/null +++ b/target/linux/generic/patches-3.18/830-ledtrig_morse.patch @@ -0,0 +1,28 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -108,4 +108,8 @@ config LEDS_TRIGGER_CAMERA + This enables direct flash/torch on/off by the driver, kernel space. + If unsure, say Y. + ++config LEDS_TRIGGER_MORSE ++ tristate "LED Morse Trigger" ++ depends on LEDS_TRIGGERS ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -62,3 +62,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ ++obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o +--- a/drivers/leds/ledtrig-morse.c ++++ b/drivers/leds/ledtrig-morse.c +@@ -26,7 +26,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/generic/patches-3.18/831-ledtrig_netdev.patch b/target/linux/generic/patches-3.18/831-ledtrig_netdev.patch new file mode 100644 index 0000000..3f39fb6 --- /dev/null +++ b/target/linux/generic/patches-3.18/831-ledtrig_netdev.patch @@ -0,0 +1,60 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -112,4 +112,11 @@ config LEDS_TRIGGER_MORSE + tristate "LED Morse Trigger" + depends on LEDS_TRIGGERS + ++config LEDS_TRIGGER_NETDEV ++ tristate "LED Netdev Trigger" ++ depends on NET && LEDS_TRIGGERS ++ help ++ This allows LEDs to be controlled by network device activity. ++ If unsure, say Y. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -63,3 +63,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o ++obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o +--- a/drivers/leds/ledtrig-netdev.c ++++ b/drivers/leds/ledtrig-netdev.c +@@ -22,7 +22,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -254,7 +253,7 @@ static int netdev_trig_notify(struct not + unsigned long evt, + void *dv) + { +- struct net_device *dev = dv; ++ struct net_device *dev = netdev_notifier_info_to_dev((struct netdev_notifier_info *) dv); + struct led_netdev_data *trigger_data = container_of(nb, struct led_netdev_data, notifier); + + if (evt != NETDEV_UP && evt != NETDEV_DOWN && evt != NETDEV_CHANGE && evt != NETDEV_REGISTER && evt != NETDEV_UNREGISTER) +@@ -294,8 +293,9 @@ done: + static void netdev_trig_timer(unsigned long arg) + { + struct led_netdev_data *trigger_data = (struct led_netdev_data *)arg; +- const struct net_device_stats *dev_stats; ++ struct rtnl_link_stats64 *dev_stats; + unsigned new_activity; ++ struct rtnl_link_stats64 temp; + + write_lock(&trigger_data->lock); + +@@ -305,7 +305,7 @@ static void netdev_trig_timer(unsigned l + goto no_restart; + } + +- dev_stats = dev_get_stats(trigger_data->net_dev); ++ dev_stats = dev_get_stats(trigger_data->net_dev, &temp); + new_activity = + ((trigger_data->mode & MODE_TX) ? dev_stats->tx_packets : 0) + + ((trigger_data->mode & MODE_RX) ? dev_stats->rx_packets : 0); diff --git a/target/linux/generic/patches-3.18/832-ledtrig_usbdev.patch b/target/linux/generic/patches-3.18/832-ledtrig_usbdev.patch new file mode 100644 index 0000000..d8c9492 --- /dev/null +++ b/target/linux/generic/patches-3.18/832-ledtrig_usbdev.patch @@ -0,0 +1,31 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -119,4 +119,11 @@ config LEDS_TRIGGER_NETDEV + This allows LEDs to be controlled by network device activity. + If unsure, say Y. + ++config LEDS_TRIGGER_USBDEV ++ tristate "LED USB device Trigger" ++ depends on USB && LEDS_TRIGGERS ++ help ++ This allows LEDs to be controlled by the presence/activity of ++ an USB device. If unsure, say N. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -64,3 +64,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o + obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o ++obj-$(CONFIG_LEDS_TRIGGER_USBDEV) += ledtrig-usbdev.o +--- a/drivers/leds/ledtrig-usbdev.c ++++ b/drivers/leds/ledtrig-usbdev.c +@@ -24,7 +24,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/generic/patches-3.18/834-ledtrig-libata.patch b/target/linux/generic/patches-3.18/834-ledtrig-libata.patch new file mode 100644 index 0000000..d0aee1c --- /dev/null +++ b/target/linux/generic/patches-3.18/834-ledtrig-libata.patch @@ -0,0 +1,153 @@ +From 52cfd51cdf6a6e14d4fb270c6343abac3bac00f4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 12 Dec 2014 13:38:33 +0100 +Subject: [PATCH] libata: add ledtrig support +To: linux-ide@vger.kernel.org, + Tejun Heo + +This adds a LED trigger for each ATA port indicating disk activity. + +As this is needed only on specific platforms (NAS SoCs and such), +these platforms should define ARCH_WANTS_LIBATA_LEDS if there +are boards with LED(s) intended to indicate ATA disk activity and +need the OS to take care of that. +In that way, if not selected, LED trigger support not will be +included in libata-core and both, codepaths and structures remain +untouched. + +Signed-off-by: Daniel Golle +--- + drivers/ata/Kconfig | 16 ++++++++++++++++ + drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++ + include/linux/libata.h | 9 +++++++++ + 3 files changed, 66 insertions(+) + +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -46,6 +46,22 @@ config ATA_VERBOSE_ERROR + + If unsure, say Y. + ++config ARCH_WANT_LIBATA_LEDS ++ bool ++ ++config ATA_LEDS ++ bool "support ATA port LED triggers" ++ depends on ARCH_WANT_LIBATA_LEDS ++ select NEW_LEDS ++ select LEDS_CLASS ++ select LEDS_TRIGGERS ++ default y ++ help ++ This option adds a LED trigger for each registered ATA port. ++ It is used to drive disk activity leds connected via GPIO. ++ ++ If unsure, say N. ++ + config ATA_ACPI + bool "ATA ACPI Support" + depends on ACPI && PCI +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -725,6 +725,19 @@ u64 ata_tf_read_block(struct ata_taskfil + return block; + } + ++#ifdef CONFIG_ATA_LEDS ++#define LIBATA_BLINK_DELAY 20 /* ms */ ++static inline void ata_led_act(struct ata_port *ap) ++{ ++ unsigned long led_delay = LIBATA_BLINK_DELAY; ++ ++ if (unlikely(!ap->ledtrig)) ++ return; ++ ++ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0); ++} ++#endif ++ + /** + * ata_build_rw_tf - Build ATA taskfile for given read/write request + * @tf: Target ATA taskfile +@@ -4800,6 +4813,9 @@ static struct ata_queued_cmd *ata_qc_new + break; + } + } ++#ifdef CONFIG_ATA_LEDS ++ ata_led_act(ap); ++#endif + + return qc; + } +@@ -5710,6 +5726,9 @@ struct ata_port *ata_port_alloc(struct a + ap->stats.unhandled_irq = 1; + ap->stats.idle_irq = 1; + #endif ++#ifdef CONFIG_ATA_LEDS ++ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL); ++#endif + ata_sff_port_init(ap); + + return ap; +@@ -5731,6 +5750,12 @@ static void ata_host_release(struct devi + + kfree(ap->pmp_link); + kfree(ap->slave_link); ++#ifdef CONFIG_ATA_LEDS ++ if (ap->ledtrig) { ++ led_trigger_unregister(ap->ledtrig); ++ kfree(ap->ledtrig); ++ }; ++#endif + kfree(ap); + host->ports[i] = NULL; + } +@@ -6177,7 +6202,23 @@ int ata_host_register(struct ata_host *h + host->ports[i]->print_id = atomic_inc_return(&ata_print_id); + host->ports[i]->local_port_no = i + 1; + } ++#ifdef CONFIG_ATA_LEDS ++ for (i = 0; i < host->n_ports; i++) { ++ if (unlikely(!host->ports[i]->ledtrig)) ++ continue; + ++ snprintf(host->ports[i]->ledtrig_name, ++ sizeof(host->ports[i]->ledtrig_name), "ata%u", ++ host->ports[i]->print_id); ++ ++ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name; ++ ++ if (led_trigger_register(host->ports[i]->ledtrig)) { ++ kfree(host->ports[i]->ledtrig); ++ host->ports[i]->ledtrig = NULL; ++ } ++ } ++#endif + /* Create associated sysfs transport objects */ + for (i = 0; i < host->n_ports; i++) { + rc = ata_tport_add(host->dev,host->ports[i]); +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -38,6 +38,9 @@ + #include + #include + #include ++#ifdef CONFIG_ATA_LEDS ++#include ++#endif + + /* + * Define if arch has non-standard setup. This is a _PCI_ standard +@@ -874,6 +877,12 @@ struct ata_port { + #ifdef CONFIG_ATA_ACPI + struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ + #endif ++ ++#ifdef CONFIG_ATA_LEDS ++ struct led_trigger *ledtrig; ++ char ledtrig_name[8]; ++#endif ++ + /* owned by EH */ + u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; + }; diff --git a/target/linux/generic/patches-3.18/840-rtc7301.patch b/target/linux/generic/patches-3.18/840-rtc7301.patch new file mode 100644 index 0000000..2134d87 --- /dev/null +++ b/target/linux/generic/patches-3.18/840-rtc7301.patch @@ -0,0 +1,250 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -979,6 +979,15 @@ config RTC_DRV_NUC900 + If you say yes here you get support for the RTC subsystem of the + NUC910/NUC920 used in embedded systems. + ++config RTC_DRV_RTC7301 ++ tristate "Epson RTC-7301 SF/DG" ++ help ++ If you say Y here you will get support for the ++ Epson RTC-7301 SF/DG RTC chips. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-7301. ++ + comment "on-CPU RTC drivers" + + config RTC_DRV_DAVINCI +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -115,6 +115,7 @@ obj-$(CONFIG_RTC_DRV_RP5C01) += rtc-rp5c + obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o + obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o + obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o ++obj-$(CONFIG_RTC_DRV_RTC7301) += rtc-rtc7301.o + obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o + obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o + obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o +--- /dev/null ++++ b/drivers/rtc/rtc-rtc7301.c +@@ -0,0 +1,219 @@ ++/* ++ * Driver for Epson RTC-7301SF/DG ++ * ++ * Copyright (C) 2009 Jose Vasconcellos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RTC_NAME "rtc7301" ++#define RTC_VERSION "0.1" ++ ++/* Epson RTC-7301 register addresses */ ++#define RTC7301_SEC 0x00 ++#define RTC7301_SEC10 0x01 ++#define RTC7301_MIN 0x02 ++#define RTC7301_MIN10 0x03 ++#define RTC7301_HOUR 0x04 ++#define RTC7301_HOUR10 0x05 ++#define RTC7301_WEEKDAY 0x06 ++#define RTC7301_DAY 0x07 ++#define RTC7301_DAY10 0x08 ++#define RTC7301_MON 0x09 ++#define RTC7301_MON10 0x0A ++#define RTC7301_YEAR 0x0B ++#define RTC7301_YEAR10 0x0C ++#define RTC7301_YEAR100 0x0D ++#define RTC7301_YEAR1000 0x0E ++#define RTC7301_CTRLREG 0x0F ++ ++static uint8_t __iomem *rtc7301_base; ++ ++#define read_reg(offset) (readb(rtc7301_base + offset) & 0xf) ++#define write_reg(offset, data) writeb(data, rtc7301_base + (offset)) ++ ++#define rtc7301_isbusy() (read_reg(RTC7301_CTRLREG) & 1) ++ ++static void rtc7301_init_settings(void) ++{ ++ int i; ++ ++ write_reg(RTC7301_CTRLREG, 2); ++ write_reg(RTC7301_YEAR1000, 2); ++ udelay(122); ++ ++ /* bank 1 */ ++ write_reg(RTC7301_CTRLREG, 6); ++ for (i=0; i<15; i++) ++ write_reg(i, 0); ++ ++ /* bank 2 */ ++ write_reg(RTC7301_CTRLREG, 14); ++ for (i=0; i<15; i++) ++ write_reg(i, 0); ++ write_reg(RTC7301_CTRLREG, 0); ++} ++ ++static int rtc7301_get_datetime(struct device *dev, struct rtc_time *dt) ++{ ++ int cnt; ++ uint8_t buf[16]; ++ ++ cnt = 0; ++ while (rtc7301_isbusy()) { ++ udelay(244); ++ if (cnt++ > 100) { ++ dev_err(dev, "%s: timeout error %x\n", __func__, rtc7301_base[RTC7301_CTRLREG]); ++ return -EIO; ++ } ++ } ++ ++ for (cnt=0; cnt<16; cnt++) ++ buf[cnt] = read_reg(cnt); ++ ++ if (buf[RTC7301_SEC10] & 8) { ++ dev_err(dev, "%s: RTC not set\n", __func__); ++ return -EINVAL; ++ } ++ ++ memset(dt, 0, sizeof(*dt)); ++ ++ dt->tm_sec = buf[RTC7301_SEC] + buf[RTC7301_SEC10]*10; ++ dt->tm_min = buf[RTC7301_MIN] + buf[RTC7301_MIN10]*10; ++ dt->tm_hour = buf[RTC7301_HOUR] + buf[RTC7301_HOUR10]*10; ++ ++ dt->tm_mday = buf[RTC7301_DAY] + buf[RTC7301_DAY10]*10; ++ dt->tm_mon = buf[RTC7301_MON] + buf[RTC7301_MON10]*10 - 1; ++ dt->tm_year = buf[RTC7301_YEAR] + buf[RTC7301_YEAR10]*10 + ++ buf[RTC7301_YEAR100]*100 + ++ ((buf[RTC7301_YEAR1000] & 3)*1000) - 1900; ++ ++ /* the rtc device may contain illegal values on power up ++ * according to the data sheet. make sure they are valid. ++ */ ++ ++ return rtc_valid_tm(dt); ++} ++ ++static int rtc7301_set_datetime(struct device *dev, struct rtc_time *dt) ++{ ++ int data; ++ ++ data = dt->tm_year + 1900; ++ if (data >= 2100 || data < 1900) ++ return -EINVAL; ++ ++ write_reg(RTC7301_CTRLREG, 2); ++ udelay(122); ++ ++ data = bin2bcd(dt->tm_sec); ++ write_reg(RTC7301_SEC, data); ++ write_reg(RTC7301_SEC10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_min); ++ write_reg(RTC7301_MIN, data ); ++ write_reg(RTC7301_MIN10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_hour); ++ write_reg(RTC7301_HOUR, data); ++ write_reg(RTC7301_HOUR10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_mday); ++ write_reg(RTC7301_DAY, data); ++ write_reg(RTC7301_DAY10, (data>> 4)); ++ ++ data = bin2bcd(dt->tm_mon + 1); ++ write_reg(RTC7301_MON, data); ++ write_reg(RTC7301_MON10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_year % 100); ++ write_reg(RTC7301_YEAR, data); ++ write_reg(RTC7301_YEAR10, (data >> 4)); ++ data = bin2bcd((1900 + dt->tm_year) / 100); ++ write_reg(RTC7301_YEAR100, data); ++ ++ data = bin2bcd(dt->tm_wday); ++ write_reg(RTC7301_WEEKDAY, data); ++ ++ write_reg(RTC7301_CTRLREG, 0); ++ ++ return 0; ++} ++ ++static const struct rtc_class_ops rtc7301_rtc_ops = { ++ .read_time = rtc7301_get_datetime, ++ .set_time = rtc7301_set_datetime, ++}; ++ ++static int rtc7301_probe(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc; ++ struct resource *res; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return -ENOENT; ++ ++ rtc7301_base = ioremap_nocache(res->start, 0x1000 /*res->end - res->start + 1*/); ++ if (!rtc7301_base) ++ return -EINVAL; ++ ++ rtc = rtc_device_register(RTC_NAME, &pdev->dev, ++ &rtc7301_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtc)) { ++ iounmap(rtc7301_base); ++ return PTR_ERR(rtc); ++ } ++ ++ platform_set_drvdata(pdev, rtc); ++ ++ rtc7301_init_settings(); ++ return 0; ++} ++ ++static int rtc7301_remove(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc = platform_get_drvdata(pdev); ++ ++ if (rtc) ++ rtc_device_unregister(rtc); ++ if (rtc7301_base) ++ iounmap(rtc7301_base); ++ return 0; ++} ++ ++static struct platform_driver rtc7301_driver = { ++ .driver = { ++ .name = RTC_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = rtc7301_probe, ++ .remove = rtc7301_remove, ++}; ++ ++static __init int rtc7301_init(void) ++{ ++ return platform_driver_register(&rtc7301_driver); ++} ++module_init(rtc7301_init); ++ ++static __exit void rtc7301_exit(void) ++{ ++ platform_driver_unregister(&rtc7301_driver); ++} ++module_exit(rtc7301_exit); ++ ++MODULE_DESCRIPTION("Epson 7301 RTC driver"); ++MODULE_AUTHOR("Jose Vasconcellos "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" RTC_NAME); ++MODULE_VERSION(RTC_VERSION); diff --git a/target/linux/generic/patches-3.18/841-rtc_pt7c4338.patch b/target/linux/generic/patches-3.18/841-rtc_pt7c4338.patch new file mode 100644 index 0000000..83b0232 --- /dev/null +++ b/target/linux/generic/patches-3.18/841-rtc_pt7c4338.patch @@ -0,0 +1,247 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -567,6 +567,15 @@ config RTC_DRV_S5M + This driver can also be built as a module. If so, the module + will be called rtc-s5m. + ++config RTC_DRV_PT7C4338 ++ tristate "Pericom Technology Inc. PT7C4338 RTC" ++ help ++ If you say yes here you get support for the Pericom Technology ++ Inc. PT7C4338 RTC chip. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-pt7c4338. ++ + endif # I2C + + comment "SPI RTC drivers" +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -106,6 +106,7 @@ obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030 + obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o + obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o + obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o ++obj-$(CONFIG_RTC_DRV_PT7C4338) += rtc-pt7c4338.o + obj-$(CONFIG_RTC_DRV_PUV3) += rtc-puv3.o + obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o + obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o +--- /dev/null ++++ b/drivers/rtc/rtc-pt7c4338.c +@@ -0,0 +1,216 @@ ++/* ++ * Copyright 2010 Freescale Semiconductor, Inc. ++ * ++ * Author: Priyanka Jain ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * This file provides Date & Time support (no alarms) for PT7C4338 chip. ++ * ++ * This file is based on drivers/rtc/rtc-ds1307.c ++ * ++ * PT7C4338 chip is manufactured by Pericom Technology Inc. ++ * It is a serial real-time clock which provides ++ * 1)Low-power clock/calendar. ++ * 2)Programmable square-wave output. ++ * It has 56 bytes of nonvolatile RAM. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* RTC register addresses */ ++#define PT7C4338_REG_SECONDS 0x00 ++#define PT7C4338_REG_MINUTES 0x01 ++#define PT7C4338_REG_HOURS 0x02 ++#define PT7C4338_REG_AMPM 0x02 ++#define PT7C4338_REG_DAY 0x03 ++#define PT7C4338_REG_DATE 0x04 ++#define PT7C4338_REG_MONTH 0x05 ++#define PT7C4338_REG_YEAR 0x06 ++#define PT7C4338_REG_CTRL_STAT 0x07 ++ ++/* RTC second register address bit */ ++#define PT7C4338_SEC_BIT_CH 0x80 /*Clock Halt (in Register 0)*/ ++ ++/* RTC control and status register bits */ ++#define PT7C4338_CTRL_STAT_BIT_RS0 0x1 /*Rate select 0*/ ++#define PT7C4338_CTRL_STAT_BIT_RS1 0x2 /*Rate select 1*/ ++#define PT7C4338_CTRL_STAT_BIT_SQWE 0x10 /*Square Wave Enable*/ ++#define PT7C4338_CTRL_STAT_BIT_OSF 0x20 /*Oscillator Stop Flag*/ ++#define PT7C4338_CTRL_STAT_BIT_OUT 0x80 /*Output Level Control*/ ++ ++static const struct i2c_device_id pt7c4338_id[] = { ++ { "pt7c4338", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, pt7c4338_id); ++ ++struct pt7c4338{ ++ struct i2c_client *client; ++ struct rtc_device *rtc; ++}; ++ ++static int pt7c4338_read_time(struct device *dev, struct rtc_time *time) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ int ret; ++ u8 buf[7]; ++ u8 year, month, day, hour, minute, second; ++ u8 week, twelve_hr, am_pm; ++ ++ ret = i2c_smbus_read_i2c_block_data(client, ++ PT7C4338_REG_SECONDS, 7, buf); ++ if (ret < 0) ++ return ret; ++ if (ret < 7) ++ return -EIO; ++ ++ second = buf[0]; ++ minute = buf[1]; ++ hour = buf[2]; ++ week = buf[3]; ++ day = buf[4]; ++ month = buf[5]; ++ year = buf[6]; ++ ++ /* Extract additional information for AM/PM */ ++ twelve_hr = hour & 0x40; ++ am_pm = hour & 0x20; ++ ++ /* Write to rtc_time structure */ ++ time->tm_sec = bcd2bin(second & 0x7f); ++ time->tm_min = bcd2bin(minute & 0x7f); ++ if (twelve_hr) { ++ /* Convert to 24 hr */ ++ if (am_pm) ++ time->tm_hour = bcd2bin(hour & 0x10) + 12; ++ else ++ time->tm_hour = bcd2bin(hour & 0xBF); ++ } else { ++ time->tm_hour = bcd2bin(hour); ++ } ++ ++ time->tm_wday = bcd2bin(week & 0x07) - 1; ++ time->tm_mday = bcd2bin(day & 0x3f); ++ time->tm_mon = bcd2bin(month & 0x1F) - 1; ++ /* assume 20YY not 19YY */ ++ time->tm_year = bcd2bin(year) + 100; ++ ++ return 0; ++} ++ ++static int pt7c4338_set_time(struct device *dev, struct rtc_time *time) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ u8 buf[7]; ++ ++ /* Extract time from rtc_time and load into pt7c4338*/ ++ buf[0] = bin2bcd(time->tm_sec); ++ buf[1] = bin2bcd(time->tm_min); ++ buf[2] = bin2bcd(time->tm_hour); ++ buf[3] = bin2bcd(time->tm_wday + 1); /* Day of the week */ ++ buf[4] = bin2bcd(time->tm_mday); /* Date */ ++ buf[5] = bin2bcd(time->tm_mon + 1); ++ ++ /* assume 20YY not 19YY */ ++ if (time->tm_year >= 100) ++ buf[6] = bin2bcd(time->tm_year - 100); ++ else ++ buf[6] = bin2bcd(time->tm_year); ++ ++ return i2c_smbus_write_i2c_block_data(client, ++ PT7C4338_REG_SECONDS, 7, buf); ++} ++ ++static const struct rtc_class_ops pt7c4338_rtc_ops = { ++ .read_time = pt7c4338_read_time, ++ .set_time = pt7c4338_set_time, ++}; ++ ++static int pt7c4338_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct pt7c4338 *pt7c4338; ++ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); ++ int ret; ++ ++ pt7c4338 = kzalloc(sizeof(struct pt7c4338), GFP_KERNEL); ++ if (!pt7c4338) ++ return -ENOMEM; ++ ++ pt7c4338->client = client; ++ i2c_set_clientdata(client, pt7c4338); ++ pt7c4338->rtc = rtc_device_register(client->name, &client->dev, ++ &pt7c4338_rtc_ops, THIS_MODULE); ++ if (IS_ERR(pt7c4338->rtc)) { ++ ret = PTR_ERR(pt7c4338->rtc); ++ dev_err(&client->dev, "unable to register the class device\n"); ++ goto out_free; ++ } ++ ++ return 0; ++out_free: ++ i2c_set_clientdata(client, NULL); ++ kfree(pt7c4338); ++ return ret; ++} ++ ++static int pt7c4338_remove(struct i2c_client *client) ++{ ++ struct pt7c4338 *pt7c4338 = i2c_get_clientdata(client); ++ ++ rtc_device_unregister(pt7c4338->rtc); ++ i2c_set_clientdata(client, NULL); ++ kfree(pt7c4338); ++ return 0; ++} ++ ++static struct i2c_driver pt7c4338_driver = { ++ .driver = { ++ .name = "rtc-pt7c4338", ++ .owner = THIS_MODULE, ++ }, ++ .probe = pt7c4338_probe, ++ .remove = pt7c4338_remove, ++ .id_table = pt7c4338_id, ++}; ++ ++static int __init pt7c4338_init(void) ++{ ++ return i2c_add_driver(&pt7c4338_driver); ++} ++ ++static void __exit pt7c4338_exit(void) ++{ ++ i2c_del_driver(&pt7c4338_driver); ++} ++ ++module_init(pt7c4338_init); ++module_exit(pt7c4338_exit); ++ ++MODULE_AUTHOR("Priyanka Jain "); ++MODULE_DESCRIPTION("pericom Technology Inc. PT7C4338 RTC Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-3.18/861-04_spi_gpio_implement_spi_delay.patch b/target/linux/generic/patches-3.18/861-04_spi_gpio_implement_spi_delay.patch new file mode 100644 index 0000000..e7b32a5 --- /dev/null +++ b/target/linux/generic/patches-3.18/861-04_spi_gpio_implement_spi_delay.patch @@ -0,0 +1,58 @@ +Implement the SPI-GPIO delay function for busses that need speed limitation. + +--mb + + + +--- a/drivers/spi/spi-gpio.c ++++ b/drivers/spi/spi-gpio.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -73,6 +74,7 @@ struct spi_gpio { + * #define SPI_MOSI_GPIO 120 + * #define SPI_SCK_GPIO 121 + * #define SPI_N_CHIPSEL 4 ++ * #undef NEED_SPIDELAY + * #include "spi-gpio.c" + */ + +@@ -80,6 +82,7 @@ struct spi_gpio { + #define DRIVER_NAME "spi_gpio" + + #define GENERIC_BITBANG /* vs tight inlines */ ++#define NEED_SPIDELAY 1 + + /* all functions referencing these symbols must define pdata */ + #define SPI_MISO_GPIO ((pdata)->miso) +@@ -130,12 +133,20 @@ static inline int getmiso(const struct s + #undef pdata + + /* +- * NOTE: this clocks "as fast as we can". It "should" be a function of the +- * requested device clock. Software overhead means we usually have trouble +- * reaching even one Mbit/sec (except when we can inline bitops), so for now +- * we'll just assume we never need additional per-bit slowdowns. ++ * NOTE: to clock "as fast as we can", set spi_device.max_speed_hz ++ * and spi_transfer.speed_hz to 0. ++ * Otherwise this is a function of the requested device clock. ++ * Software overhead means we usually have trouble ++ * reaching even one Mbit/sec (except when we can inline bitops). So on small ++ * embedded devices with fast SPI slaves you usually don't need a delay. + */ +-#define spidelay(nsecs) do {} while (0) ++static inline void spidelay(unsigned nsecs) ++{ ++#ifdef NEED_SPIDELAY ++ if (unlikely(nsecs)) ++ ndelay(nsecs); ++#endif /* NEED_SPIDELAY */ ++} + + #include "spi-bitbang-txrx.h" + diff --git a/target/linux/generic/patches-3.18/862-gpio_spi_driver.patch b/target/linux/generic/patches-3.18/862-gpio_spi_driver.patch new file mode 100644 index 0000000..70bf11f --- /dev/null +++ b/target/linux/generic/patches-3.18/862-gpio_spi_driver.patch @@ -0,0 +1,373 @@ +THIS CODE IS DEPRECATED. + +Please use the new mainline SPI-GPIO driver, as of 2.6.29. + +--mb + + + +--- + drivers/spi/Kconfig | 9 + + drivers/spi/Makefile | 1 + drivers/spi/spi_gpio_old.c | 251 +++++++++++++++++++++++++++++++++++++++ + include/linux/spi/spi_gpio_old.h | 73 +++++++++++ + 4 files changed, 334 insertions(+) + +--- /dev/null ++++ b/include/linux/spi/spi_gpio_old.h +@@ -0,0 +1,73 @@ ++/* ++ * spi_gpio interface to platform code ++ * ++ * Copyright (c) 2008 Piotr Skamruk ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef _LINUX_SPI_SPI_GPIO ++#define _LINUX_SPI_SPI_GPIO ++ ++#include ++#include ++ ++ ++/** ++ * struct spi_gpio_platform_data - Data definitions for a SPI-GPIO device. ++ * ++ * This structure holds information about a GPIO-based SPI device. ++ * ++ * @pin_clk: The GPIO pin number of the CLOCK pin. ++ * ++ * @pin_miso: The GPIO pin number of the MISO pin. ++ * ++ * @pin_mosi: The GPIO pin number of the MOSI pin. ++ * ++ * @pin_cs: The GPIO pin number of the CHIPSELECT pin. ++ * ++ * @cs_activelow: If true, the chip is selected when the CS line is low. ++ * ++ * @no_spi_delay: If true, no delay is done in the lowlevel bitbanging. ++ * Note that doing no delay is not standards compliant, ++ * but it might be needed to speed up transfers on some ++ * slow embedded machines. ++ * ++ * @boardinfo_setup: This callback is called after the ++ * SPI master device was registered, but before the ++ * device is registered. ++ * @boardinfo_setup_data: Data argument passed to boardinfo_setup(). ++ */ ++struct spi_gpio_platform_data { ++ unsigned int pin_clk; ++ unsigned int pin_miso; ++ unsigned int pin_mosi; ++ unsigned int pin_cs; ++ bool cs_activelow; ++ bool no_spi_delay; ++ int (*boardinfo_setup)(struct spi_board_info *bi, ++ struct spi_master *master, ++ void *data); ++ void *boardinfo_setup_data; ++}; ++ ++/** ++ * SPI_GPIO_PLATDEV_NAME - The platform device name string. ++ * ++ * The name string that has to be used for platform_device_alloc ++ * when allocating a spi-gpio device. ++ */ ++#define SPI_GPIO_PLATDEV_NAME "spi-gpio" ++ ++/** ++ * spi_gpio_next_id - Get another platform device ID number. ++ * ++ * This returns the next platform device ID number that has to be used ++ * for platform_device_alloc. The ID is opaque and should not be used for ++ * anything else. ++ */ ++int spi_gpio_next_id(void); ++ ++#endif /* _LINUX_SPI_SPI_GPIO */ +--- /dev/null ++++ b/drivers/spi/spi_gpio_old.c +@@ -0,0 +1,251 @@ ++/* ++ * Bitbanging SPI bus driver using GPIO API ++ * ++ * Copyright (c) 2008 Piotr Skamruk ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * based on spi_s3c2410_gpio.c ++ * Copyright (c) 2006 Ben Dooks ++ * Copyright (c) 2006 Simtec Electronics ++ * and on i2c-gpio.c ++ * Copyright (C) 2007 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++struct spi_gpio { ++ struct spi_bitbang bitbang; ++ struct spi_gpio_platform_data *info; ++ struct platform_device *pdev; ++ struct spi_board_info bi; ++}; ++ ++ ++static inline struct spi_gpio *spidev_to_sg(struct spi_device *dev) ++{ ++ return dev->controller_data; ++} ++ ++static inline void setsck(struct spi_device *dev, int val) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ gpio_set_value(sp->info->pin_clk, val ? 1 : 0); ++} ++ ++static inline void setmosi(struct spi_device *dev, int val) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ gpio_set_value(sp->info->pin_mosi, val ? 1 : 0); ++} ++ ++static inline u32 getmiso(struct spi_device *dev) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ return gpio_get_value(sp->info->pin_miso) ? 1 : 0; ++} ++ ++static inline void do_spidelay(struct spi_device *dev, unsigned nsecs) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ ++ if (!sp->info->no_spi_delay) ++ ndelay(nsecs); ++} ++ ++#define spidelay(nsecs) do { \ ++ /* Steal the spi_device pointer from our caller. \ ++ * The bitbang-API should probably get fixed here... */ \ ++ do_spidelay(spi, nsecs); \ ++ } while (0) ++ ++#define EXPAND_BITBANG_TXRX ++#include "spi-bitbang-txrx.h" ++ ++static u32 spi_gpio_txrx_mode0(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode1(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode2(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode3(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); ++} ++ ++static void spi_gpio_chipselect(struct spi_device *dev, int on) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ ++ if (sp->info->cs_activelow) ++ on = !on; ++ gpio_set_value(sp->info->pin_cs, on ? 1 : 0); ++} ++ ++static int spi_gpio_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct spi_gpio_platform_data *pdata; ++ struct spi_gpio *sp; ++ struct spi_device *spidev; ++ int err; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -ENXIO; ++ ++ err = -ENOMEM; ++ master = spi_alloc_master(&pdev->dev, sizeof(struct spi_gpio)); ++ if (!master) ++ goto err_alloc_master; ++ ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); ++ sp->info = pdata; ++ ++ err = gpio_request(pdata->pin_clk, "spi_clock"); ++ if (err) ++ goto err_request_clk; ++ err = gpio_request(pdata->pin_mosi, "spi_mosi"); ++ if (err) ++ goto err_request_mosi; ++ err = gpio_request(pdata->pin_miso, "spi_miso"); ++ if (err) ++ goto err_request_miso; ++ err = gpio_request(pdata->pin_cs, "spi_cs"); ++ if (err) ++ goto err_request_cs; ++ ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.master->bus_num = -1; ++ sp->bitbang.master->num_chipselect = 1; ++ sp->bitbang.chipselect = spi_gpio_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_txrx_mode0; ++ sp->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_txrx_mode1; ++ sp->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_txrx_mode2; ++ sp->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_txrx_mode3; ++ ++ gpio_direction_output(pdata->pin_clk, 0); ++ gpio_direction_output(pdata->pin_mosi, 0); ++ gpio_direction_output(pdata->pin_cs, ++ pdata->cs_activelow ? 1 : 0); ++ gpio_direction_input(pdata->pin_miso); ++ ++ err = spi_bitbang_start(&sp->bitbang); ++ if (err) ++ goto err_no_bitbang; ++ err = pdata->boardinfo_setup(&sp->bi, master, ++ pdata->boardinfo_setup_data); ++ if (err) ++ goto err_bi_setup; ++ sp->bi.controller_data = sp; ++ spidev = spi_new_device(master, &sp->bi); ++ if (!spidev) ++ goto err_new_dev; ++ ++ return 0; ++ ++err_new_dev: ++err_bi_setup: ++ spi_bitbang_stop(&sp->bitbang); ++err_no_bitbang: ++ spi_master_put(sp->bitbang.master); ++ gpio_free(pdata->pin_cs); ++err_request_cs: ++ gpio_free(pdata->pin_miso); ++err_request_miso: ++ gpio_free(pdata->pin_mosi); ++err_request_mosi: ++ gpio_free(pdata->pin_clk); ++err_request_clk: ++ kfree(master); ++ ++err_alloc_master: ++ return err; ++} ++ ++static int spi_gpio_remove(struct platform_device *pdev) ++{ ++ struct spi_gpio *sp; ++ struct spi_gpio_platform_data *pdata; ++ ++ pdata = pdev->dev.platform_data; ++ sp = platform_get_drvdata(pdev); ++ ++ gpio_free(pdata->pin_clk); ++ gpio_free(pdata->pin_mosi); ++ gpio_free(pdata->pin_miso); ++ gpio_free(pdata->pin_cs); ++ spi_bitbang_stop(&sp->bitbang); ++ spi_master_put(sp->bitbang.master); ++ ++ return 0; ++} ++ ++static struct platform_driver spi_gpio_driver = { ++ .driver = { ++ .name = SPI_GPIO_PLATDEV_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = spi_gpio_probe, ++ .remove = spi_gpio_remove, ++}; ++ ++int spi_gpio_next_id(void) ++{ ++ static atomic_t counter = ATOMIC_INIT(-1); ++ ++ return atomic_inc_return(&counter); ++} ++EXPORT_SYMBOL(spi_gpio_next_id); ++ ++static int __init spi_gpio_init(void) ++{ ++ int err; ++ ++ err = platform_driver_register(&spi_gpio_driver); ++ if (err) ++ printk(KERN_ERR "spi-gpio: register failed: %d\n", err); ++ ++ return err; ++} ++module_init(spi_gpio_init); ++ ++static void __exit spi_gpio_exit(void) ++{ ++ platform_driver_unregister(&spi_gpio_driver); ++} ++module_exit(spi_gpio_exit); ++ ++MODULE_AUTHOR("Piot Skamruk "); ++MODULE_AUTHOR("Michael Buesch"); ++MODULE_DESCRIPTION("Platform independent GPIO bitbanging SPI driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -225,6 +225,15 @@ config SPI_GPIO + GPIO operations, you should be able to leverage that for better + speed with a custom version of this driver; see the source code. + ++config SPI_GPIO_OLD ++ tristate "Old GPIO API based bitbanging SPI controller (DEPRECATED)" ++ depends on SPI_MASTER && GPIOLIB ++ select SPI_BITBANG ++ help ++ This code is deprecated. Please use the new mainline SPI-GPIO driver. ++ ++ If unsure, say N. ++ + config SPI_IMX + tristate "Freescale i.MX SPI controllers" + depends on ARCH_MXC || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -40,6 +40,7 @@ obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-li + obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o + obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o + obj-$(CONFIG_SPI_GPIO) += spi-gpio.o ++obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o + obj-$(CONFIG_SPI_IMX) += spi-imx.o + obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o + obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o diff --git a/target/linux/generic/patches-3.18/863-gpiommc.patch b/target/linux/generic/patches-3.18/863-gpiommc.patch new file mode 100644 index 0000000..2929333 --- /dev/null +++ b/target/linux/generic/patches-3.18/863-gpiommc.patch @@ -0,0 +1,844 @@ +--- /dev/null ++++ b/drivers/mmc/host/gpiommc.c +@@ -0,0 +1,609 @@ ++/* ++ * Driver an MMC/SD card on a bitbanging GPIO SPI bus. ++ * This module hooks up the mmc_spi and spi_gpio modules and also ++ * provides a configfs interface. ++ * ++ * Copyright 2008 Michael Buesch ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#define PFX "gpio-mmc: " ++ ++ ++struct gpiommc_device { ++ struct platform_device *pdev; ++ struct platform_device *spi_pdev; ++ struct spi_board_info boardinfo; ++}; ++ ++ ++MODULE_DESCRIPTION("GPIO based MMC driver"); ++MODULE_AUTHOR("Michael Buesch"); ++MODULE_LICENSE("GPL"); ++ ++ ++static int gpiommc_boardinfo_setup(struct spi_board_info *bi, ++ struct spi_master *master, ++ void *data) ++{ ++ struct gpiommc_device *d = data; ++ struct gpiommc_platform_data *pdata = d->pdev->dev.platform_data; ++ ++ /* Bind the SPI master to the MMC-SPI host driver. */ ++ strlcpy(bi->modalias, "mmc_spi", sizeof(bi->modalias)); ++ ++ bi->max_speed_hz = pdata->max_bus_speed; ++ bi->bus_num = master->bus_num; ++ bi->mode = pdata->mode; ++ ++ return 0; ++} ++ ++static int gpiommc_probe(struct platform_device *pdev) ++{ ++ struct gpiommc_platform_data *mmc_pdata = pdev->dev.platform_data; ++ struct spi_gpio_platform_data spi_pdata; ++ struct gpiommc_device *d; ++ int err; ++ ++ err = -ENXIO; ++ if (!mmc_pdata) ++ goto error; ++ ++#ifdef CONFIG_MMC_SPI_MODULE ++ err = request_module("mmc_spi"); ++ if (err) { ++ printk(KERN_WARNING PFX ++ "Failed to request mmc_spi module.\n"); ++ } ++#endif /* CONFIG_MMC_SPI_MODULE */ ++ ++ /* Allocate the GPIO-MMC device */ ++ err = -ENOMEM; ++ d = kzalloc(sizeof(*d), GFP_KERNEL); ++ if (!d) ++ goto error; ++ d->pdev = pdev; ++ ++ /* Create the SPI-GPIO device */ ++ d->spi_pdev = platform_device_alloc(SPI_GPIO_PLATDEV_NAME, ++ spi_gpio_next_id()); ++ if (!d->spi_pdev) ++ goto err_free_d; ++ ++ memset(&spi_pdata, 0, sizeof(spi_pdata)); ++ spi_pdata.pin_clk = mmc_pdata->pins.gpio_clk; ++ spi_pdata.pin_miso = mmc_pdata->pins.gpio_do; ++ spi_pdata.pin_mosi = mmc_pdata->pins.gpio_di; ++ spi_pdata.pin_cs = mmc_pdata->pins.gpio_cs; ++ spi_pdata.cs_activelow = mmc_pdata->pins.cs_activelow; ++ spi_pdata.no_spi_delay = mmc_pdata->no_spi_delay; ++ spi_pdata.boardinfo_setup = gpiommc_boardinfo_setup; ++ spi_pdata.boardinfo_setup_data = d; ++ ++ err = platform_device_add_data(d->spi_pdev, &spi_pdata, ++ sizeof(spi_pdata)); ++ if (err) ++ goto err_free_pdev; ++ err = platform_device_add(d->spi_pdev); ++ if (err) ++ goto err_free_pdata; ++ platform_set_drvdata(pdev, d); ++ ++ printk(KERN_INFO PFX "MMC-Card \"%s\" " ++ "attached to GPIO pins di=%u, do=%u, clk=%u, cs=%u\n", ++ mmc_pdata->name, mmc_pdata->pins.gpio_di, ++ mmc_pdata->pins.gpio_do, ++ mmc_pdata->pins.gpio_clk, ++ mmc_pdata->pins.gpio_cs); ++ ++ return 0; ++ ++err_free_pdata: ++ kfree(d->spi_pdev->dev.platform_data); ++ d->spi_pdev->dev.platform_data = NULL; ++err_free_pdev: ++ platform_device_put(d->spi_pdev); ++err_free_d: ++ kfree(d); ++error: ++ return err; ++} ++ ++static int gpiommc_remove(struct platform_device *pdev) ++{ ++ struct gpiommc_device *d = platform_get_drvdata(pdev); ++ struct gpiommc_platform_data *pdata = d->pdev->dev.platform_data; ++ ++ platform_device_unregister(d->spi_pdev); ++ printk(KERN_INFO PFX "GPIO based MMC-Card \"%s\" removed\n", ++ pdata->name); ++ platform_device_put(d->spi_pdev); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ ++/* A device that was created through configfs */ ++struct gpiommc_configfs_device { ++ struct config_item item; ++ /* The platform device, after registration. */ ++ struct platform_device *pdev; ++ /* The configuration */ ++ struct gpiommc_platform_data pdata; ++}; ++ ++#define GPIO_INVALID -1 ++ ++static inline bool gpiommc_is_registered(struct gpiommc_configfs_device *dev) ++{ ++ return (dev->pdev != NULL); ++} ++ ++static inline struct gpiommc_configfs_device *ci_to_gpiommc(struct config_item *item) ++{ ++ return item ? container_of(item, struct gpiommc_configfs_device, item) : NULL; ++} ++ ++static struct configfs_attribute gpiommc_attr_DI = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_data_in", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_DO = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_data_out", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CLK = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_clock", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CS = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_chipselect", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CS_activelow = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_chipselect_activelow", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_spimode = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "spi_mode", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_spidelay = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "spi_delay", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_max_bus_speed = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "max_bus_speed", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_register = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "register", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute *gpiommc_config_attrs[] = { ++ &gpiommc_attr_DI, ++ &gpiommc_attr_DO, ++ &gpiommc_attr_CLK, ++ &gpiommc_attr_CS, ++ &gpiommc_attr_CS_activelow, ++ &gpiommc_attr_spimode, ++ &gpiommc_attr_spidelay, ++ &gpiommc_attr_max_bus_speed, ++ &gpiommc_attr_register, ++ NULL, ++}; ++ ++static ssize_t gpiommc_config_attr_show(struct config_item *item, ++ struct configfs_attribute *attr, ++ char *page) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ssize_t count = 0; ++ unsigned int gpio; ++ int err = 0; ++ ++ if (attr == &gpiommc_attr_DI) { ++ gpio = dev->pdata.pins.gpio_di; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_DO) { ++ gpio = dev->pdata.pins.gpio_do; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CLK) { ++ gpio = dev->pdata.pins.gpio_clk; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS) { ++ gpio = dev->pdata.pins.gpio_cs; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS_activelow) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.pins.cs_activelow); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spimode) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.mode); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spidelay) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ !dev->pdata.no_spi_delay); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_max_bus_speed) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.max_bus_speed); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_register) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ gpiommc_is_registered(dev)); ++ goto out; ++ } ++ WARN_ON(1); ++ err = -ENOSYS; ++out: ++ return err ? err : count; ++} ++ ++static int gpiommc_do_register(struct gpiommc_configfs_device *dev, ++ const char *name) ++{ ++ int err; ++ ++ if (gpiommc_is_registered(dev)) ++ return 0; ++ ++ if (!gpio_is_valid(dev->pdata.pins.gpio_di) || ++ !gpio_is_valid(dev->pdata.pins.gpio_do) || ++ !gpio_is_valid(dev->pdata.pins.gpio_clk) || ++ !gpio_is_valid(dev->pdata.pins.gpio_cs)) { ++ printk(KERN_ERR PFX ++ "configfs: Invalid GPIO pin number(s)\n"); ++ return -EINVAL; ++ } ++ ++ strlcpy(dev->pdata.name, name, ++ sizeof(dev->pdata.name)); ++ ++ dev->pdev = platform_device_alloc(GPIOMMC_PLATDEV_NAME, ++ gpiommc_next_id()); ++ if (!dev->pdev) ++ return -ENOMEM; ++ err = platform_device_add_data(dev->pdev, &dev->pdata, ++ sizeof(dev->pdata)); ++ if (err) { ++ platform_device_put(dev->pdev); ++ return err; ++ } ++ err = platform_device_add(dev->pdev); ++ if (err) { ++ platform_device_put(dev->pdev); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void gpiommc_do_unregister(struct gpiommc_configfs_device *dev) ++{ ++ if (!gpiommc_is_registered(dev)) ++ return; ++ ++ platform_device_unregister(dev->pdev); ++ dev->pdev = NULL; ++} ++ ++static ssize_t gpiommc_config_attr_store(struct config_item *item, ++ struct configfs_attribute *attr, ++ const char *page, size_t count) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ int err = -EINVAL; ++ unsigned long data; ++ ++ if (attr == &gpiommc_attr_register) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data == 1) ++ err = gpiommc_do_register(dev, item->ci_name); ++ if (data == 0) { ++ gpiommc_do_unregister(dev); ++ err = 0; ++ } ++ goto out; ++ } ++ ++ if (gpiommc_is_registered(dev)) { ++ /* The rest of the config parameters can only be set ++ * as long as the device is not registered, yet. */ ++ err = -EBUSY; ++ goto out; ++ } ++ ++ if (attr == &gpiommc_attr_DI) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_di = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_DO) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_do = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CLK) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_clk = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_cs = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS_activelow) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data != 0 && data != 1) ++ goto out; ++ dev->pdata.pins.cs_activelow = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spimode) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ switch (data) { ++ case 0: ++ dev->pdata.mode = SPI_MODE_0; ++ break; ++ case 1: ++ dev->pdata.mode = SPI_MODE_1; ++ break; ++ case 2: ++ dev->pdata.mode = SPI_MODE_2; ++ break; ++ case 3: ++ dev->pdata.mode = SPI_MODE_3; ++ break; ++ default: ++ goto out; ++ } ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spidelay) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data != 0 && data != 1) ++ goto out; ++ dev->pdata.no_spi_delay = !data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_max_bus_speed) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data > UINT_MAX) ++ goto out; ++ dev->pdata.max_bus_speed = data; ++ err = 0; ++ goto out; ++ } ++ WARN_ON(1); ++ err = -ENOSYS; ++out: ++ return err ? err : count; ++} ++ ++static void gpiommc_config_item_release(struct config_item *item) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ++ kfree(dev); ++} ++ ++static struct configfs_item_operations gpiommc_config_item_ops = { ++ .release = gpiommc_config_item_release, ++ .show_attribute = gpiommc_config_attr_show, ++ .store_attribute = gpiommc_config_attr_store, ++}; ++ ++static struct config_item_type gpiommc_dev_ci_type = { ++ .ct_item_ops = &gpiommc_config_item_ops, ++ .ct_attrs = gpiommc_config_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *gpiommc_make_item(struct config_group *group, ++ const char *name) ++{ ++ struct gpiommc_configfs_device *dev; ++ ++ if (strlen(name) > GPIOMMC_MAX_NAMELEN) { ++ printk(KERN_ERR PFX "configfs: device name too long\n"); ++ return NULL; ++ } ++ ++ dev = kzalloc(sizeof(*dev), GFP_KERNEL); ++ if (!dev) ++ return NULL; ++ ++ config_item_init_type_name(&dev->item, name, ++ &gpiommc_dev_ci_type); ++ ++ /* Assign default configuration */ ++ dev->pdata.pins.gpio_di = GPIO_INVALID; ++ dev->pdata.pins.gpio_do = GPIO_INVALID; ++ dev->pdata.pins.gpio_clk = GPIO_INVALID; ++ dev->pdata.pins.gpio_cs = GPIO_INVALID; ++ dev->pdata.pins.cs_activelow = 1; ++ dev->pdata.mode = SPI_MODE_0; ++ dev->pdata.no_spi_delay = 0; ++ dev->pdata.max_bus_speed = 5000000; /* 5 MHz */ ++ ++ return &(dev->item); ++} ++ ++static void gpiommc_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ++ gpiommc_do_unregister(dev); ++ kfree(dev); ++} ++ ++static struct configfs_group_operations gpiommc_ct_group_ops = { ++ .make_item = gpiommc_make_item, ++ .drop_item = gpiommc_drop_item, ++}; ++ ++static struct config_item_type gpiommc_ci_type = { ++ .ct_group_ops = &gpiommc_ct_group_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_subsystem gpiommc_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = GPIOMMC_PLATDEV_NAME, ++ .ci_type = &gpiommc_ci_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(gpiommc_subsys.su_mutex), ++}; ++ ++#endif /* CONFIG_GPIOMMC_CONFIGFS */ ++ ++static struct platform_driver gpiommc_plat_driver = { ++ .probe = gpiommc_probe, ++ .remove = gpiommc_remove, ++ .driver = { ++ .name = GPIOMMC_PLATDEV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int gpiommc_next_id(void) ++{ ++ static atomic_t counter = ATOMIC_INIT(-1); ++ ++ return atomic_inc_return(&counter); ++} ++EXPORT_SYMBOL(gpiommc_next_id); ++ ++static int __init gpiommc_modinit(void) ++{ ++ int err; ++ ++ err = platform_driver_register(&gpiommc_plat_driver); ++ if (err) ++ return err; ++ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ config_group_init(&gpiommc_subsys.su_group); ++ err = configfs_register_subsystem(&gpiommc_subsys); ++ if (err) { ++ platform_driver_unregister(&gpiommc_plat_driver); ++ return err; ++ } ++#endif /* CONFIG_GPIOMMC_CONFIGFS */ ++ ++ return 0; ++} ++module_init(gpiommc_modinit); ++ ++static void __exit gpiommc_modexit(void) ++{ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ configfs_unregister_subsystem(&gpiommc_subsys); ++#endif ++ platform_driver_unregister(&gpiommc_plat_driver); ++} ++module_exit(gpiommc_modexit); +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -534,6 +534,31 @@ config MMC_SDHI + This provides support for the SDHI SD/SDIO controller found in + SuperH and ARM SH-Mobile SoCs + ++config GPIOMMC ++ tristate "MMC/SD over GPIO-based SPI" ++ depends on MMC && MMC_SPI && SPI_GPIO_OLD ++ help ++ This driver hooks up the mmc_spi and spi_gpio modules so that ++ MMC/SD cards can be used on a GPIO based bus by bitbanging ++ the SPI protocol in software. ++ ++ This driver provides a configfs interface to dynamically create ++ and destroy GPIO-based MMC/SD card devices. It also provides ++ a platform device interface API. ++ See Documentation/gpiommc.txt for details. ++ ++ The module will be called gpiommc. ++ ++ If unsure, say N. ++ ++config GPIOMMC_CONFIGFS ++ bool ++ depends on GPIOMMC && CONFIGFS_FS ++ default y ++ help ++ This option automatically enables configfs support for gpiommc ++ if configfs is available. ++ + config MMC_CB710 + tristate "ENE CB710 MMC/SD Interface support" + depends on PCI +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -40,6 +40,7 @@ tmio_mmc_core-$(subst m,y,$(CONFIG_MMC_S + obj-$(CONFIG_MMC_SDHI) += sh_mobile_sdhi.o + obj-$(CONFIG_MMC_CB710) += cb710-mmc.o + obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o ++obj-$(CONFIG_GPIOMMC) += gpiommc.o + obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o + obj-$(CONFIG_MMC_DW) += dw_mmc.o + obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o +--- /dev/null ++++ b/include/linux/mmc/gpiommc.h +@@ -0,0 +1,71 @@ ++/* ++ * Device driver for MMC/SD cards driven over a GPIO bus. ++ * ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * Licensed under the GNU/GPL version 2. ++ */ ++#ifndef LINUX_GPIOMMC_H_ ++#define LINUX_GPIOMMC_H_ ++ ++#include ++ ++ ++#define GPIOMMC_MAX_NAMELEN 15 ++#define GPIOMMC_MAX_NAMELEN_STR __stringify(GPIOMMC_MAX_NAMELEN) ++ ++/** ++ * struct gpiommc_pins - Hardware pin assignments ++ * ++ * @gpio_di: The GPIO number of the DATA IN pin ++ * @gpio_do: The GPIO number of the DATA OUT pin ++ * @gpio_clk: The GPIO number of the CLOCK pin ++ * @gpio_cs: The GPIO number of the CHIPSELECT pin ++ * @cs_activelow: If true, the chip is considered selected if @gpio_cs is low. ++ */ ++struct gpiommc_pins { ++ unsigned int gpio_di; ++ unsigned int gpio_do; ++ unsigned int gpio_clk; ++ unsigned int gpio_cs; ++ bool cs_activelow; ++}; ++ ++/** ++ * struct gpiommc_platform_data - Platform data for a MMC-over-SPI-GPIO device. ++ * ++ * @name: The unique name string of the device. ++ * @pins: The hardware pin assignments. ++ * @mode: The hardware mode. This is either SPI_MODE_0, ++ * SPI_MODE_1, SPI_MODE_2 or SPI_MODE_3. See the SPI documentation. ++ * @no_spi_delay: Do not use delays in the lowlevel SPI bitbanging code. ++ * This is not standards compliant, but may be required for some ++ * embedded machines to gain reasonable speed. ++ * @max_bus_speed: The maximum speed of the SPI bus, in Hertz. ++ */ ++struct gpiommc_platform_data { ++ char name[GPIOMMC_MAX_NAMELEN + 1]; ++ struct gpiommc_pins pins; ++ u8 mode; ++ bool no_spi_delay; ++ unsigned int max_bus_speed; ++}; ++ ++/** ++ * GPIOMMC_PLATDEV_NAME - The platform device name string. ++ * ++ * The name string that has to be used for platform_device_alloc ++ * when allocating a gpiommc device. ++ */ ++#define GPIOMMC_PLATDEV_NAME "gpiommc" ++ ++/** ++ * gpiommc_next_id - Get another platform device ID number. ++ * ++ * This returns the next platform device ID number that has to be used ++ * for platform_device_alloc. The ID is opaque and should not be used for ++ * anything else. ++ */ ++int gpiommc_next_id(void); ++ ++#endif /* LINUX_GPIOMMC_H_ */ +--- /dev/null ++++ b/Documentation/gpiommc.txt +@@ -0,0 +1,97 @@ ++GPIOMMC - Driver for an MMC/SD card on a bitbanging GPIO SPI bus ++================================================================ ++ ++The gpiommc module hooks up the mmc_spi and spi_gpio modules for running an ++MMC or SD card on GPIO pins. ++ ++Two interfaces for registering a new MMC/SD card device are provided: ++A static platform-device based mechanism and a dynamic configfs based interface. ++ ++ ++Registering devices via platform-device ++======================================= ++ ++The platform-device interface is used for registering MMC/SD devices that are ++part of the hardware platform. This is most useful only for embedded machines ++with MMC/SD devices statically connected to the platform GPIO bus. ++ ++The data structures are declared in . ++ ++To register a new device, define an instance of struct gpiommc_platform_data. ++This structure holds any information about how the device is hooked up to the ++GPIO pins and what hardware modes the device supports. See the docbook-style ++documentation in the header file for more information on the struct fields. ++ ++Then allocate a new instance of a platform device by doing: ++ ++ pdev = platform_device_alloc(GPIOMMC_PLATDEV_NAME, gpiommc_next_id()); ++ ++This will allocate the platform device data structures and hook it up to the ++gpiommc driver. ++Then add the gpiommc_platform_data to the platform device. ++ ++ err = platform_device_add_data(pdev, pdata, sizeof(struct gpiommc_platform_data)); ++ ++You may free the local instance of struct gpiommc_platform_data now. (So the ++struct may be allocated on the stack, too). ++Now simply register the platform device. ++ ++ err = platform_device_add(pdev); ++ ++Done. The gpiommc probe routine will be invoked now and you should see a kernel ++log message for the added device. ++ ++ ++Registering devices via configfs ++================================ ++ ++MMC/SD cards connected via GPIO often are a pretty dynamic thing, as for example ++selfmade hacks for soldering an MMC/SD card to standard GPIO pins on embedded ++hardware are a common situation. ++So we provide a dynamic interface to conveniently handle adding and removing ++devices from userspace, without the need to recompile the kernel. ++ ++The "gpiommc" subdirectory at the configfs mountpoint is used for handling ++the dynamic configuration. ++ ++To create a new device, it must first be allocated with mkdir. ++The following command will allocate a device named "my_mmc": ++ mkdir /config/gpiommc/my_mmc ++ ++There are several configuration files available in the new ++/config/gpiommc/my_mmc/ directory: ++ ++gpio_data_in = The SPI data-IN GPIO pin number. ++gpio_data_out = The SPI data-OUT GPIO pin number. ++gpio_clock = The SPI Clock GPIO pin number. ++gpio_chipselect = The SPI Chipselect GPIO pin number. ++gpio_chipselect_activelow = Boolean. If 0, Chipselect is active-HIGH. ++ If 1, Chipselect is active-LOW. ++spi_mode = The SPI data mode. Can be 0-3. ++spi_delay = Enable all delays in the lowlevel bitbanging. ++max_bus_speed = The maximum SPI bus speed. In Hertz. ++ ++register = Not a configuration parameter. ++ Used to register the configured card ++ with the kernel. ++ ++The device must first get configured and then registered by writing "1" to ++the "register" file. ++The configuration parameters "gpio_data_in", "gpio_data_out", "gpio_clock" ++and "gpio_chipselect" are essential and _must_ be configured before writing ++"1" to the "register" file. The registration will fail, otherwise. ++ ++The default values for the other parameters are: ++gpio_chipselect_activelow = 1 (CS active-LOW) ++spi_mode = 0 (SPI_MODE_0) ++spi_delay = 1 (enabled) ++max_bus_speed = 5000000 (5 Mhz) ++ ++Configuration values can not be changed after registration. To unregister ++the device, write a "0" to the "register" file. The configuration can be ++changed again after unregistering. ++ ++To completely remove the device, simply rmdir the directory ++(/config/gpiommc/my_mmc in this example). ++There's no need to first unregister the device before removing it. That will ++be done automatically. +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -4279,6 +4279,11 @@ T: git git://linuxtv.org/anttip/media_tr + S: Maintained + F: drivers/media/usb/hackrf/ + ++GPIOMMC DRIVER ++P: Michael Buesch ++M: mb@bu3sch.de ++S: Maintained ++ + HARDWARE MONITORING + M: Jean Delvare + M: Guenter Roeck diff --git a/target/linux/generic/patches-3.18/864-gpiommc_configfs_locking.patch b/target/linux/generic/patches-3.18/864-gpiommc_configfs_locking.patch new file mode 100644 index 0000000..92815d9 --- /dev/null +++ b/target/linux/generic/patches-3.18/864-gpiommc_configfs_locking.patch @@ -0,0 +1,58 @@ +The gpiommc configfs context structure needs locking, as configfs +does not lock access between files. + +--- a/drivers/mmc/host/gpiommc.c ++++ b/drivers/mmc/host/gpiommc.c +@@ -144,6 +144,8 @@ struct gpiommc_configfs_device { + struct platform_device *pdev; + /* The configuration */ + struct gpiommc_platform_data pdata; ++ /* Mutex to protect this structure */ ++ struct mutex mutex; + }; + + #define GPIO_INVALID -1 +@@ -234,6 +236,8 @@ static ssize_t gpiommc_config_attr_show( + unsigned int gpio; + int err = 0; + ++ mutex_lock(&dev->mutex); ++ + if (attr == &gpiommc_attr_DI) { + gpio = dev->pdata.pins.gpio_di; + if (gpio == GPIO_INVALID) +@@ -294,6 +298,8 @@ static ssize_t gpiommc_config_attr_show( + WARN_ON(1); + err = -ENOSYS; + out: ++ mutex_unlock(&dev->mutex); ++ + return err ? err : count; + } + +@@ -353,6 +359,8 @@ static ssize_t gpiommc_config_attr_store + int err = -EINVAL; + unsigned long data; + ++ mutex_lock(&dev->mutex); ++ + if (attr == &gpiommc_attr_register) { + err = kstrtoul(page, 10, &data); + if (err) +@@ -478,6 +486,8 @@ static ssize_t gpiommc_config_attr_store + WARN_ON(1); + err = -ENOSYS; + out: ++ mutex_unlock(&dev->mutex); ++ + return err ? err : count; + } + +@@ -514,6 +524,7 @@ static struct config_item *gpiommc_make_ + if (!dev) + return NULL; + ++ mutex_init(&dev->mutex); + config_item_init_type_name(&dev->item, name, + &gpiommc_dev_ci_type); + diff --git a/target/linux/generic/patches-3.18/870-hifn795x_byteswap.patch b/target/linux/generic/patches-3.18/870-hifn795x_byteswap.patch new file mode 100644 index 0000000..3a37c95 --- /dev/null +++ b/target/linux/generic/patches-3.18/870-hifn795x_byteswap.patch @@ -0,0 +1,17 @@ +--- a/drivers/crypto/hifn_795x.c ++++ b/drivers/crypto/hifn_795x.c +@@ -682,12 +682,12 @@ static inline u32 hifn_read_1(struct hif + + static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) + { +- writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); ++ writel(val, dev->bar[0] + reg); + } + + static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) + { +- writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); ++ writel(val, dev->bar[1] + reg); + } + + static void hifn_wait_puc(struct hifn_device *dev) diff --git a/target/linux/generic/patches-3.18/880-gateworks_system_controller.patch b/target/linux/generic/patches-3.18/880-gateworks_system_controller.patch new file mode 100644 index 0000000..55e95be --- /dev/null +++ b/target/linux/generic/patches-3.18/880-gateworks_system_controller.patch @@ -0,0 +1,339 @@ +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -507,6 +507,15 @@ config SENSORS_G762 + This driver can also be built as a module. If so, the module + will be called g762. + ++config SENSORS_GSC ++ tristate "Gateworks System Controller" ++ depends on I2C ++ help ++ If you say yes here you get support for the Gateworks System Controller. ++ ++ This driver can also be built as a module. If so, the module ++ will be called gsc. ++ + config SENSORS_GPIO_FAN + tristate "GPIO fan" + depends on GPIOLIB +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -153,6 +153,7 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l7 + obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o + obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o + obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o ++obj-$(CONFIG_SENSORS_GSC) += gsc.o + + obj-$(CONFIG_PMBUS) += pmbus/ + +--- /dev/null ++++ b/drivers/hwmon/gsc.c +@@ -0,0 +1,308 @@ ++/* ++ * A hwmon driver for the Gateworks System Controller ++ * Copyright (C) 2009 Gateworks Corporation ++ * ++ * Author: Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License, ++ * as published by the Free Software Foundation - version 2. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRV_VERSION "0.2" ++ ++enum chips { gsp }; ++ ++/* AD7418 registers */ ++#define GSP_REG_TEMP_IN 0x00 ++#define GSP_REG_VIN 0x02 ++#define GSP_REG_3P3 0x05 ++#define GSP_REG_BAT 0x08 ++#define GSP_REG_5P0 0x0b ++#define GSP_REG_CORE 0x0e ++#define GSP_REG_CPU1 0x11 ++#define GSP_REG_CPU2 0x14 ++#define GSP_REG_DRAM 0x17 ++#define GSP_REG_EXT_BAT 0x1a ++#define GSP_REG_IO1 0x1d ++#define GSP_REG_IO2 0x20 ++#define GSP_REG_PCIE 0x23 ++#define GSP_REG_CURRENT 0x26 ++#define GSP_FAN_0 0x2C ++#define GSP_FAN_1 0x2E ++#define GSP_FAN_2 0x30 ++#define GSP_FAN_3 0x32 ++#define GSP_FAN_4 0x34 ++#define GSP_FAN_5 0x36 ++ ++struct gsp_sensor_info { ++ const char* name; ++ int reg; ++}; ++ ++static const struct gsp_sensor_info gsp_sensors[] = { ++ {"temp", GSP_REG_TEMP_IN}, ++ {"vin", GSP_REG_VIN}, ++ {"3p3", GSP_REG_3P3}, ++ {"bat", GSP_REG_BAT}, ++ {"5p0", GSP_REG_5P0}, ++ {"core", GSP_REG_CORE}, ++ {"cpu1", GSP_REG_CPU1}, ++ {"cpu2", GSP_REG_CPU2}, ++ {"dram", GSP_REG_DRAM}, ++ {"ext_bat", GSP_REG_EXT_BAT}, ++ {"io1", GSP_REG_IO1}, ++ {"io2", GSP_REG_IO2}, ++ {"pci2", GSP_REG_PCIE}, ++ {"current", GSP_REG_CURRENT}, ++ {"fan_point0", GSP_FAN_0}, ++ {"fan_point1", GSP_FAN_1}, ++ {"fan_point2", GSP_FAN_2}, ++ {"fan_point3", GSP_FAN_3}, ++ {"fan_point4", GSP_FAN_4}, ++ {"fan_point5", GSP_FAN_5}, ++}; ++ ++struct gsp_data { ++ struct device *hwmon_dev; ++ struct attribute_group attrs; ++ enum chips type; ++}; ++ ++static int gsp_probe(struct i2c_client *client, ++ const struct i2c_device_id *id); ++static int gsp_remove(struct i2c_client *client); ++ ++static const struct i2c_device_id gsp_id[] = { ++ { "gsp", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, gsp_id); ++ ++static struct i2c_driver gsp_driver = { ++ .driver = { ++ .name = "gsp", ++ }, ++ .probe = gsp_probe, ++ .remove = gsp_remove, ++ .id_table = gsp_id, ++}; ++ ++/* All registers are word-sized, except for the configuration registers. ++ * AD7418 uses a high-byte first convention. Do NOT use those functions to ++ * access the configuration registers CONF and CONF2, as they are byte-sized. ++ */ ++static inline int gsp_read(struct i2c_client *client, u8 reg) ++{ ++ unsigned int adc = 0; ++ if (reg == GSP_REG_TEMP_IN || reg > GSP_REG_CURRENT) ++ { ++ adc |= i2c_smbus_read_byte_data(client, reg); ++ adc |= i2c_smbus_read_byte_data(client, reg + 1) << 8; ++ return adc; ++ } ++ else ++ { ++ adc |= i2c_smbus_read_byte_data(client, reg); ++ adc |= i2c_smbus_read_byte_data(client, reg + 1) << 8; ++ adc |= i2c_smbus_read_byte_data(client, reg + 2) << 16; ++ return adc; ++ } ++} ++ ++static inline int gsp_write(struct i2c_client *client, u8 reg, u16 value) ++{ ++ i2c_smbus_write_byte_data(client, reg, value & 0xff); ++ i2c_smbus_write_byte_data(client, reg + 1, ((value >> 8) & 0xff)); ++ return 1; ++} ++ ++static ssize_t show_adc(struct device *dev, struct device_attribute *devattr, ++ char *buf) ++{ ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ struct i2c_client *client = to_i2c_client(dev); ++ return sprintf(buf, "%d\n", gsp_read(client, gsp_sensors[attr->index].reg)); ++} ++ ++static ssize_t show_label(struct device *dev, ++ struct device_attribute *devattr, char *buf) ++{ ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ ++ return sprintf(buf, "%s\n", gsp_sensors[attr->index].name); ++} ++ ++static ssize_t store_fan(struct device *dev, ++ struct device_attribute *devattr, const char *buf, size_t count) ++{ ++ u16 val; ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ struct i2c_client *client = to_i2c_client(dev); ++ val = simple_strtoul(buf, NULL, 10); ++ gsp_write(client, gsp_sensors[attr->index].reg, val); ++ return count; ++} ++ ++static SENSOR_DEVICE_ATTR(temp0_input, S_IRUGO, show_adc, NULL, 0); ++static SENSOR_DEVICE_ATTR(temp0_label, S_IRUGO, show_label, NULL, 0); ++ ++static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, show_adc, NULL, 1); ++static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, show_label, NULL, 1); ++static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, show_adc, NULL, 2); ++static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, show_label, NULL, 2); ++static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, show_adc, NULL, 3); ++static SENSOR_DEVICE_ATTR(in2_label, S_IRUGO, show_label, NULL, 3); ++static SENSOR_DEVICE_ATTR(in3_input, S_IRUGO, show_adc, NULL, 4); ++static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 4); ++static SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, show_adc, NULL, 5); ++static SENSOR_DEVICE_ATTR(in4_label, S_IRUGO, show_label, NULL, 5); ++static SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, show_adc, NULL, 6); ++static SENSOR_DEVICE_ATTR(in5_label, S_IRUGO, show_label, NULL, 6); ++static SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, show_adc, NULL, 7); ++static SENSOR_DEVICE_ATTR(in6_label, S_IRUGO, show_label, NULL, 7); ++static SENSOR_DEVICE_ATTR(in7_input, S_IRUGO, show_adc, NULL, 8); ++static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 8); ++static SENSOR_DEVICE_ATTR(in8_input, S_IRUGO, show_adc, NULL, 9); ++static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 9); ++static SENSOR_DEVICE_ATTR(in9_input, S_IRUGO, show_adc, NULL, 10); ++static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 10); ++static SENSOR_DEVICE_ATTR(in10_input, S_IRUGO, show_adc, NULL, 11); ++static SENSOR_DEVICE_ATTR(in10_label, S_IRUGO, show_label, NULL, 11); ++static SENSOR_DEVICE_ATTR(in11_input, S_IRUGO, show_adc, NULL, 12); ++static SENSOR_DEVICE_ATTR(in11_label, S_IRUGO, show_label, NULL, 12); ++static SENSOR_DEVICE_ATTR(in12_input, S_IRUGO, show_adc, NULL, 13); ++static SENSOR_DEVICE_ATTR(in12_label, S_IRUGO, show_label, NULL, 13); ++ ++static SENSOR_DEVICE_ATTR(fan0_point0, S_IRUGO | S_IWUSR, show_adc, store_fan, 14); ++static SENSOR_DEVICE_ATTR(fan0_point1, S_IRUGO | S_IWUSR, show_adc, store_fan, 15); ++static SENSOR_DEVICE_ATTR(fan0_point2, S_IRUGO | S_IWUSR, show_adc, store_fan, 16); ++static SENSOR_DEVICE_ATTR(fan0_point3, S_IRUGO | S_IWUSR, show_adc, store_fan, 17); ++static SENSOR_DEVICE_ATTR(fan0_point4, S_IRUGO | S_IWUSR, show_adc, store_fan, 18); ++static SENSOR_DEVICE_ATTR(fan0_point5, S_IRUGO | S_IWUSR, show_adc, store_fan, 19); ++ ++static struct attribute *gsp_attributes[] = { ++ &sensor_dev_attr_temp0_input.dev_attr.attr, ++ &sensor_dev_attr_in0_input.dev_attr.attr, ++ &sensor_dev_attr_in1_input.dev_attr.attr, ++ &sensor_dev_attr_in2_input.dev_attr.attr, ++ &sensor_dev_attr_in3_input.dev_attr.attr, ++ &sensor_dev_attr_in4_input.dev_attr.attr, ++ &sensor_dev_attr_in5_input.dev_attr.attr, ++ &sensor_dev_attr_in6_input.dev_attr.attr, ++ &sensor_dev_attr_in7_input.dev_attr.attr, ++ &sensor_dev_attr_in8_input.dev_attr.attr, ++ &sensor_dev_attr_in9_input.dev_attr.attr, ++ &sensor_dev_attr_in10_input.dev_attr.attr, ++ &sensor_dev_attr_in11_input.dev_attr.attr, ++ &sensor_dev_attr_in12_input.dev_attr.attr, ++ ++ &sensor_dev_attr_temp0_label.dev_attr.attr, ++ &sensor_dev_attr_in0_label.dev_attr.attr, ++ &sensor_dev_attr_in1_label.dev_attr.attr, ++ &sensor_dev_attr_in2_label.dev_attr.attr, ++ &sensor_dev_attr_in3_label.dev_attr.attr, ++ &sensor_dev_attr_in4_label.dev_attr.attr, ++ &sensor_dev_attr_in5_label.dev_attr.attr, ++ &sensor_dev_attr_in6_label.dev_attr.attr, ++ &sensor_dev_attr_in7_label.dev_attr.attr, ++ &sensor_dev_attr_in8_label.dev_attr.attr, ++ &sensor_dev_attr_in9_label.dev_attr.attr, ++ &sensor_dev_attr_in10_label.dev_attr.attr, ++ &sensor_dev_attr_in11_label.dev_attr.attr, ++ &sensor_dev_attr_in12_label.dev_attr.attr, ++ ++ &sensor_dev_attr_fan0_point0.dev_attr.attr, ++ &sensor_dev_attr_fan0_point1.dev_attr.attr, ++ &sensor_dev_attr_fan0_point2.dev_attr.attr, ++ &sensor_dev_attr_fan0_point3.dev_attr.attr, ++ &sensor_dev_attr_fan0_point4.dev_attr.attr, ++ &sensor_dev_attr_fan0_point5.dev_attr.attr, ++ NULL ++}; ++ ++ ++static int gsp_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct i2c_adapter *adapter = client->adapter; ++ struct gsp_data *data; ++ int err; ++ ++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | ++ I2C_FUNC_SMBUS_WORD_DATA)) { ++ err = -EOPNOTSUPP; ++ goto exit; ++ } ++ ++ if (!(data = kzalloc(sizeof(struct gsp_data), GFP_KERNEL))) { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ++ i2c_set_clientdata(client, data); ++ ++ data->type = id->driver_data; ++ ++ switch (data->type) { ++ case 0: ++ data->attrs.attrs = gsp_attributes; ++ break; ++ } ++ ++ dev_info(&client->dev, "%s chip found\n", client->name); ++ ++ /* Register sysfs hooks */ ++ if ((err = sysfs_create_group(&client->dev.kobj, &data->attrs))) ++ goto exit_free; ++ ++ data->hwmon_dev = hwmon_device_register(&client->dev); ++ if (IS_ERR(data->hwmon_dev)) { ++ err = PTR_ERR(data->hwmon_dev); ++ goto exit_remove; ++ } ++ ++ return 0; ++ ++exit_remove: ++ sysfs_remove_group(&client->dev.kobj, &data->attrs); ++exit_free: ++ kfree(data); ++exit: ++ return err; ++} ++ ++static int gsp_remove(struct i2c_client *client) ++{ ++ struct gsp_data *data = i2c_get_clientdata(client); ++ hwmon_device_unregister(data->hwmon_dev); ++ sysfs_remove_group(&client->dev.kobj, &data->attrs); ++ kfree(data); ++ return 0; ++} ++ ++static int __init gsp_init(void) ++{ ++ return i2c_add_driver(&gsp_driver); ++} ++ ++static void __exit gsp_exit(void) ++{ ++ i2c_del_driver(&gsp_driver); ++} ++ ++module_init(gsp_init); ++module_exit(gsp_exit); ++ ++MODULE_AUTHOR("Chris Lang "); ++MODULE_DESCRIPTION("GSC HWMON driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); ++ diff --git a/target/linux/generic/patches-3.18/890-8250_optional_sysrq.patch b/target/linux/generic/patches-3.18/890-8250_optional_sysrq.patch new file mode 100644 index 0000000..8815e4c --- /dev/null +++ b/target/linux/generic/patches-3.18/890-8250_optional_sysrq.patch @@ -0,0 +1,24 @@ +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -16,7 +16,7 @@ + * membase is an 'ioremapped' cookie. + */ + +-#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) ++#if defined(CONFIG_SERIAL_8250_SYSRQ) && defined(CONFIG_MAGIC_SYSRQ) + #define SUPPORT_SYSRQ + #endif + +--- a/drivers/tty/serial/8250/Kconfig ++++ b/drivers/tty/serial/8250/Kconfig +@@ -91,6 +91,10 @@ config SERIAL_8250_CONSOLE + + If unsure, say N. + ++config SERIAL_8250_SYSRQ ++ bool "Magic sysrq support on 8250/16550 devices" ++ depends on SERIAL_8250_CONSOLE ++ + config SERIAL_8250_GSC + tristate + depends on SERIAL_8250 && GSC diff --git a/target/linux/generic/patches-3.18/900-slab_maxsize.patch b/target/linux/generic/patches-3.18/900-slab_maxsize.patch new file mode 100644 index 0000000..9375305 --- /dev/null +++ b/target/linux/generic/patches-3.18/900-slab_maxsize.patch @@ -0,0 +1,13 @@ +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -172,8 +172,8 @@ size_t ksize(const void *); + * to do various tricks to work around compiler limitations in order to + * ensure proper constant folding. + */ +-#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 25 ? \ +- (MAX_ORDER + PAGE_SHIFT - 1) : 25) ++#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 17 ? \ ++ (MAX_ORDER + PAGE_SHIFT - 1) : 17) + #define KMALLOC_SHIFT_MAX KMALLOC_SHIFT_HIGH + #ifndef KMALLOC_SHIFT_LOW + #define KMALLOC_SHIFT_LOW 5 diff --git a/target/linux/generic/patches-3.18/901-debloat_sock_diag.patch b/target/linux/generic/patches-3.18/901-debloat_sock_diag.patch new file mode 100644 index 0000000..99f23a0 --- /dev/null +++ b/target/linux/generic/patches-3.18/901-debloat_sock_diag.patch @@ -0,0 +1,65 @@ +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -89,6 +89,9 @@ source "net/netlabel/Kconfig" + + endif # if INET + ++config SOCK_DIAG ++ bool ++ + config NETWORK_SECMARK + bool "Security Marking" + help +--- a/net/core/Makefile ++++ b/net/core/Makefile +@@ -9,8 +9,9 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core. + + obj-y += dev.o ethtool.o dev_addr_lists.o dst.o netevent.o \ + neighbour.o rtnetlink.o utils.o link_watch.o filter.o \ +- sock_diag.o dev_ioctl.o tso.o ++ dev_ioctl.o tso.o + ++obj-$(CONFIG_SOCK_DIAG) += sock_diag.o + obj-$(CONFIG_XFRM) += flow.o + obj-y += net-sysfs.o + obj-$(CONFIG_PROC_FS) += net-procfs.o +--- a/net/ipv4/Kconfig ++++ b/net/ipv4/Kconfig +@@ -419,6 +419,7 @@ config INET_LRO + + config INET_DIAG + tristate "INET: socket monitoring interface" ++ select SOCK_DIAG + default y + ---help--- + Support for INET (TCP, DCCP, etc) socket monitoring interface used by +--- a/net/unix/Kconfig ++++ b/net/unix/Kconfig +@@ -22,6 +22,7 @@ config UNIX + config UNIX_DIAG + tristate "UNIX: socket monitoring interface" + depends on UNIX ++ select SOCK_DIAG + default n + ---help--- + Support for UNIX socket monitoring interface used by the ss tool. +--- a/net/netlink/Kconfig ++++ b/net/netlink/Kconfig +@@ -13,6 +13,7 @@ config NETLINK_MMAP + + config NETLINK_DIAG + tristate "NETLINK: socket monitoring interface" ++ select SOCK_DIAG + default n + ---help--- + Support for NETLINK socket monitoring interface used by the ss tool. +--- a/net/packet/Kconfig ++++ b/net/packet/Kconfig +@@ -18,6 +18,7 @@ config PACKET + config PACKET_DIAG + tristate "Packet: sockets monitoring interface" + depends on PACKET ++ select SOCK_DIAG + default n + ---help--- + Support for PF_PACKET sockets monitoring interface used by the ss tool. diff --git a/target/linux/generic/patches-3.18/902-debloat_proc.patch b/target/linux/generic/patches-3.18/902-debloat_proc.patch new file mode 100644 index 0000000..5cecd1e --- /dev/null +++ b/target/linux/generic/patches-3.18/902-debloat_proc.patch @@ -0,0 +1,341 @@ +--- a/fs/locks.c ++++ b/fs/locks.c +@@ -2611,6 +2611,8 @@ static const struct file_operations proc + + static int __init proc_locks_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("locks", 0, NULL, &proc_locks_operations); + return 0; + } +--- a/fs/proc/Kconfig ++++ b/fs/proc/Kconfig +@@ -71,3 +71,8 @@ config PROC_PAGE_MONITOR + /proc/pid/smaps, /proc/pid/clear_refs, /proc/pid/pagemap, + /proc/kpagecount, and /proc/kpageflags. Disabling these + interfaces will reduce the size of the kernel by approximately 4kb. ++ ++config PROC_STRIPPED ++ default n ++ depends on EXPERT ++ bool "Strip non-essential /proc functionality to reduce code size" +--- a/fs/proc/consoles.c ++++ b/fs/proc/consoles.c +@@ -106,6 +106,9 @@ static const struct file_operations proc + + static int __init proc_consoles_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + proc_create("consoles", 0, NULL, &proc_consoles_operations); + return 0; + } +--- a/fs/proc/proc_tty.c ++++ b/fs/proc/proc_tty.c +@@ -143,7 +143,10 @@ static const struct file_operations proc + void proc_tty_register_driver(struct tty_driver *driver) + { + struct proc_dir_entry *ent; +- ++ ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (!driver->driver_name || driver->proc_entry || + !driver->ops->proc_fops) + return; +@@ -160,6 +163,9 @@ void proc_tty_unregister_driver(struct t + { + struct proc_dir_entry *ent; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + ent = driver->proc_entry; + if (!ent) + return; +@@ -174,6 +180,9 @@ void proc_tty_unregister_driver(struct t + */ + void __init proc_tty_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (!proc_mkdir("tty", NULL)) + return; + proc_mkdir("tty/ldisc", NULL); /* Preserved: it's userspace visible */ +--- a/kernel/exec_domain.c ++++ b/kernel/exec_domain.c +@@ -176,6 +176,8 @@ static const struct file_operations exec + + static int __init proc_execdomains_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("execdomains", 0, NULL, &execdomains_proc_fops); + return 0; + } +--- a/kernel/irq/proc.c ++++ b/kernel/irq/proc.c +@@ -330,6 +330,9 @@ void register_irq_proc(unsigned int irq, + static DEFINE_MUTEX(register_lock); + char name [MAX_NAMELEN]; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + if (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip)) + return; + +@@ -379,6 +382,9 @@ void unregister_irq_proc(unsigned int ir + { + char name [MAX_NAMELEN]; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + if (!root_irq_dir || !desc->dir) + return; + #ifdef CONFIG_SMP +@@ -414,6 +420,9 @@ void init_irq_proc(void) + unsigned int irq; + struct irq_desc *desc; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + /* create /proc/irq */ + root_irq_dir = proc_mkdir("irq", NULL); + if (!root_irq_dir) +--- a/kernel/time/timer_list.c ++++ b/kernel/time/timer_list.c +@@ -362,6 +362,8 @@ static int __init init_timer_list_procfs + { + struct proc_dir_entry *pe; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + pe = proc_create("timer_list", 0444, NULL, &timer_list_fops); + if (!pe) + return -ENOMEM; +--- a/mm/vmalloc.c ++++ b/mm/vmalloc.c +@@ -2662,6 +2662,8 @@ static const struct file_operations proc + + static int __init proc_vmalloc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("vmallocinfo", S_IRUSR, NULL, &proc_vmalloc_operations); + return 0; + } +--- a/mm/vmstat.c ++++ b/mm/vmstat.c +@@ -1424,10 +1424,12 @@ static int __init setup_vmstat(void) + cpu_notifier_register_done(); + #endif + #ifdef CONFIG_PROC_FS +- proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations); +- proc_create("pagetypeinfo", S_IRUGO, NULL, &pagetypeinfo_file_ops); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations); ++ proc_create("pagetypeinfo", S_IRUGO, NULL, &pagetypeinfo_file_ops); ++ proc_create("zoneinfo", S_IRUGO, NULL, &proc_zoneinfo_file_operations); ++ } + proc_create("vmstat", S_IRUGO, NULL, &proc_vmstat_file_operations); +- proc_create("zoneinfo", S_IRUGO, NULL, &proc_zoneinfo_file_operations); + #endif + return 0; + } +--- a/net/8021q/vlanproc.c ++++ b/net/8021q/vlanproc.c +@@ -127,6 +127,9 @@ void vlan_proc_cleanup(struct net *net) + { + struct vlan_net *vn = net_generic(net, vlan_net_id); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (vn->proc_vlan_conf) + remove_proc_entry(name_conf, vn->proc_vlan_dir); + +@@ -146,6 +149,9 @@ int __net_init vlan_proc_init(struct net + { + struct vlan_net *vn = net_generic(net, vlan_net_id); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + vn->proc_vlan_dir = proc_net_mkdir(net, name_root, net->proc_net); + if (!vn->proc_vlan_dir) + goto err; +--- a/net/core/sock.c ++++ b/net/core/sock.c +@@ -2934,6 +2934,8 @@ static __net_initdata struct pernet_oper + + static int __init proto_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + return register_pernet_subsys(&proto_net_ops); + } + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -2490,10 +2490,12 @@ static const struct file_operations fib_ + + int __net_init fib_proc_init(struct net *net) + { +- if (!proc_create("fib_trie", S_IRUGO, net->proc_net, &fib_trie_fops)) ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("fib_trie", S_IRUGO, net->proc_net, &fib_trie_fops)) + goto out1; + +- if (!proc_create("fib_triestat", S_IRUGO, net->proc_net, ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("fib_triestat", S_IRUGO, net->proc_net, + &fib_triestat_fops)) + goto out2; + +@@ -2503,17 +2505,21 @@ int __net_init fib_proc_init(struct net + return 0; + + out3: +- remove_proc_entry("fib_triestat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("fib_triestat", net->proc_net); + out2: +- remove_proc_entry("fib_trie", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("fib_trie", net->proc_net); + out1: + return -ENOMEM; + } + + void __net_exit fib_proc_exit(struct net *net) + { +- remove_proc_entry("fib_trie", net->proc_net); +- remove_proc_entry("fib_triestat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ remove_proc_entry("fib_trie", net->proc_net); ++ remove_proc_entry("fib_triestat", net->proc_net); ++ } + remove_proc_entry("route", net->proc_net); + } + +--- a/net/ipv4/proc.c ++++ b/net/ipv4/proc.c +@@ -524,6 +524,9 @@ static __net_initdata struct pernet_oper + + int __init ip_misc_proc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + return register_pernet_subsys(&ip_proc_ops); + } + +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -416,6 +416,9 @@ static struct pernet_operations ip_rt_pr + + static int __init ip_rt_proc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + return register_pernet_subsys(&ip_rt_proc_ops); + } + +--- a/ipc/msg.c ++++ b/ipc/msg.c +@@ -1072,6 +1072,9 @@ void __init msg_init(void) + printk(KERN_INFO "msgmni has been set to %d\n", + init_ipc_ns.msg_ctlmni); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + ipc_init_proc_interface("sysvipc/msg", + " key msqid perms cbytes qnum lspid lrpid uid gid cuid cgid stime rtime ctime\n", + IPC_MSG_IDS, sysvipc_msg_proc_show); +--- a/ipc/sem.c ++++ b/ipc/sem.c +@@ -191,6 +191,8 @@ void sem_exit_ns(struct ipc_namespace *n + void __init sem_init(void) + { + sem_init_ns(&init_ipc_ns); ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; + ipc_init_proc_interface("sysvipc/sem", + " key semid perms nsems uid gid cuid cgid otime ctime\n", + IPC_SEM_IDS, sysvipc_sem_proc_show); +--- a/ipc/shm.c ++++ b/ipc/shm.c +@@ -118,6 +118,8 @@ pure_initcall(ipc_ns_init); + + void __init shm_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; + ipc_init_proc_interface("sysvipc/shm", + #if BITS_PER_LONG <= 32 + " key shmid perms size cpid lpid nattch uid gid cuid cgid atime dtime ctime rss swap\n", +--- a/ipc/util.c ++++ b/ipc/util.c +@@ -161,6 +161,9 @@ void __init ipc_init_proc_interface(cons + struct proc_dir_entry *pde; + struct ipc_proc_iface *iface; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + iface = kmalloc(sizeof(*iface), GFP_KERNEL); + if (!iface) + return; +--- a/net/core/net-procfs.c ++++ b/net/core/net-procfs.c +@@ -318,10 +318,12 @@ static int __net_init dev_proc_net_init( + + if (!proc_create("dev", S_IRUGO, net->proc_net, &dev_seq_fops)) + goto out; +- if (!proc_create("softnet_stat", S_IRUGO, net->proc_net, ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("softnet_stat", S_IRUGO, net->proc_net, + &softnet_seq_fops)) + goto out_dev; +- if (!proc_create("ptype", S_IRUGO, net->proc_net, &ptype_seq_fops)) ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("ptype", S_IRUGO, net->proc_net, &ptype_seq_fops)) + goto out_softnet; + + if (wext_proc_init(net)) +@@ -330,9 +332,11 @@ static int __net_init dev_proc_net_init( + out: + return rc; + out_ptype: +- remove_proc_entry("ptype", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("ptype", net->proc_net); + out_softnet: +- remove_proc_entry("softnet_stat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("softnet_stat", net->proc_net); + out_dev: + remove_proc_entry("dev", net->proc_net); + goto out; +@@ -342,8 +346,10 @@ static void __net_exit dev_proc_net_exit + { + wext_proc_exit(net); + +- remove_proc_entry("ptype", net->proc_net); +- remove_proc_entry("softnet_stat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ remove_proc_entry("ptype", net->proc_net); ++ remove_proc_entry("softnet_stat", net->proc_net); ++ } + remove_proc_entry("dev", net->proc_net); + } + diff --git a/target/linux/generic/patches-3.18/903-debloat_direct_io.patch b/target/linux/generic/patches-3.18/903-debloat_direct_io.patch new file mode 100644 index 0000000..92190e4 --- /dev/null +++ b/target/linux/generic/patches-3.18/903-debloat_direct_io.patch @@ -0,0 +1,83 @@ +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -62,6 +62,11 @@ config FILE_LOCKING + for filesystems like NFS and for the flock() system + call. Disabling this option saves about 11k. + ++config DIRECT_IO ++ bool "Enable O_DIRECT support" if EXPERT ++ depends on BLOCK ++ default y ++ + source "fs/notify/Kconfig" + + source "fs/quota/Kconfig" +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -14,7 +14,8 @@ obj-y := open.o read_write.o file_table. + stack.o fs_struct.o statfs.o fs_pin.o + + ifeq ($(CONFIG_BLOCK),y) +-obj-y += buffer.o block_dev.o direct-io.o mpage.o ++obj-y += buffer.o block_dev.o mpage.o ++obj-$(CONFIG_DIRECT_IO) += direct-io.o + else + obj-y += no-block.o + endif +--- a/include/linux/fs.h ++++ b/include/linux/fs.h +@@ -2528,12 +2528,25 @@ enum { + DIO_ASYNC_EXTEND = 0x04, + }; + ++#ifdef CONFIG_DIRECT_IO + void dio_end_io(struct bio *bio, int error); + + ssize_t __blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, + struct block_device *bdev, struct iov_iter *iter, loff_t offset, + get_block_t get_block, dio_iodone_t end_io, + dio_submit_t submit_io, int flags); ++#else ++static inline void dio_end_io(struct bio *bio, int error) ++{ ++} ++static inline ssize_t __blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, ++ struct block_device *bdev, struct iov_iter *iter, loff_t offset, ++ get_block_t get_block, dio_iodone_t end_io, ++ dio_submit_t submit_io, int flags) ++{ ++ return -EOPNOTSUPP; ++} ++#endif + + static inline ssize_t blockdev_direct_IO(int rw, struct kiocb *iocb, + struct inode *inode, struct iov_iter *iter, loff_t offset, +--- a/fs/fcntl.c ++++ b/fs/fcntl.c +@@ -52,8 +52,10 @@ static int setfl(int fd, struct file * f + arg |= O_NONBLOCK; + + if (arg & O_DIRECT) { ++#ifdef CONFIG_DIRECT_IO + if (!filp->f_mapping || !filp->f_mapping->a_ops || + !filp->f_mapping->a_ops->direct_IO) ++#endif + return -EINVAL; + } + +--- a/fs/open.c ++++ b/fs/open.c +@@ -655,9 +655,12 @@ int open_check_o_direct(struct file *f) + { + /* NB: we're sure to have correct a_ops only after f_op->open */ + if (f->f_flags & O_DIRECT) { ++#ifdef CONFIG_DIRECT_IO + if (!f->f_mapping->a_ops || + ((!f->f_mapping->a_ops->direct_IO) && +- (!f->f_mapping->a_ops->get_xip_mem))) { ++ (!f->f_mapping->a_ops->get_xip_mem))) ++#endif ++ { + return -EINVAL; + } + } diff --git a/target/linux/generic/patches-3.18/910-kobject_uevent.patch b/target/linux/generic/patches-3.18/910-kobject_uevent.patch new file mode 100644 index 0000000..f69294b --- /dev/null +++ b/target/linux/generic/patches-3.18/910-kobject_uevent.patch @@ -0,0 +1,21 @@ +--- a/lib/kobject_uevent.c ++++ b/lib/kobject_uevent.c +@@ -53,6 +53,18 @@ static const char *kobject_actions[] = { + [KOBJ_OFFLINE] = "offline", + }; + ++u64 uevent_next_seqnum(void) ++{ ++ u64 seq; ++ ++ mutex_lock(&uevent_sock_mutex); ++ seq = ++uevent_seqnum; ++ mutex_unlock(&uevent_sock_mutex); ++ ++ return seq; ++} ++EXPORT_SYMBOL_GPL(uevent_next_seqnum); ++ + /** + * kobject_action_type - translate action string to numeric type + * diff --git a/target/linux/generic/patches-3.18/911-kobject_add_broadcast_uevent.patch b/target/linux/generic/patches-3.18/911-kobject_add_broadcast_uevent.patch new file mode 100644 index 0000000..6e4c140 --- /dev/null +++ b/target/linux/generic/patches-3.18/911-kobject_add_broadcast_uevent.patch @@ -0,0 +1,65 @@ +--- a/include/linux/kobject.h ++++ b/include/linux/kobject.h +@@ -32,6 +32,8 @@ + #define UEVENT_NUM_ENVP 32 /* number of env pointers */ + #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */ + ++struct sk_buff; ++ + #ifdef CONFIG_UEVENT_HELPER + /* path to the userspace helper executed on an event */ + extern char uevent_helper[]; +@@ -221,4 +223,7 @@ int add_uevent_var(struct kobj_uevent_en + int kobject_action_type(const char *buf, size_t count, + enum kobject_action *type); + ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation); ++ + #endif /* _KOBJECT_H_ */ +--- a/lib/kobject_uevent.c ++++ b/lib/kobject_uevent.c +@@ -424,6 +424,43 @@ int add_uevent_var(struct kobj_uevent_en + EXPORT_SYMBOL_GPL(add_uevent_var); + + #if defined(CONFIG_NET) ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation) ++{ ++ struct uevent_sock *ue_sk; ++ int err = 0; ++ ++ /* send netlink message */ ++ mutex_lock(&uevent_sock_mutex); ++ list_for_each_entry(ue_sk, &uevent_sock_list, list) { ++ struct sock *uevent_sock = ue_sk->sk; ++ struct sk_buff *skb2; ++ ++ skb2 = skb_clone(skb, allocation); ++ if (!skb2) ++ break; ++ ++ err = netlink_broadcast(uevent_sock, skb2, pid, group, ++ allocation); ++ if (err) ++ break; ++ } ++ mutex_unlock(&uevent_sock_mutex); ++ ++ kfree_skb(skb); ++ return err; ++} ++#else ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation) ++{ ++ kfree_skb(skb); ++ return 0; ++} ++#endif ++EXPORT_SYMBOL_GPL(broadcast_uevent); ++ ++#if defined(CONFIG_NET) + static int uevent_net_init(struct net *net) + { + struct uevent_sock *ue_sk; diff --git a/target/linux/generic/patches-3.18/921-use_preinit_as_init.patch b/target/linux/generic/patches-3.18/921-use_preinit_as_init.patch new file mode 100644 index 0000000..57c2fe2 --- /dev/null +++ b/target/linux/generic/patches-3.18/921-use_preinit_as_init.patch @@ -0,0 +1,12 @@ +--- a/init/main.c ++++ b/init/main.c +@@ -963,7 +963,8 @@ static int __ref kernel_init(void *unuse + pr_err("Failed to execute %s (error %d). Attempting defaults...\n", + execute_command, ret); + } +- if (!try_to_run_init_process("/sbin/init") || ++ if (!try_to_run_init_process("/etc/preinit") || ++ !try_to_run_init_process("/sbin/init") || + !try_to_run_init_process("/etc/init") || + !try_to_run_init_process("/bin/init") || + !try_to_run_init_process("/bin/sh")) diff --git a/target/linux/generic/patches-3.18/922-always-create-console-node-in-initramfs.patch b/target/linux/generic/patches-3.18/922-always-create-console-node-in-initramfs.patch new file mode 100644 index 0000000..988de35 --- /dev/null +++ b/target/linux/generic/patches-3.18/922-always-create-console-node-in-initramfs.patch @@ -0,0 +1,30 @@ +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -59,6 +59,18 @@ default_initramfs() { + EOF + } + ++list_openwrt_initramfs() { ++ : ++} ++ ++openwrt_initramfs() { ++ # make sure that /dev/console exists ++ cat <<-EOF >> ${output} ++ dir /dev 0755 0 0 ++ nod /dev/console 0600 0 0 c 5 1 ++ EOF ++} ++ + filetype() { + local argv1="$1" + +@@ -177,6 +189,8 @@ dir_filelist() { + if [ "$(echo "${dirlist}" | wc -l)" -gt 1 ]; then + ${dep_list}print_mtime "$1" + ++ ${dep_list}openwrt_initramfs ++ + echo "${dirlist}" | \ + while read x; do + ${dep_list}parse ${x} diff --git a/target/linux/generic/patches-3.18/930-crashlog.patch b/target/linux/generic/patches-3.18/930-crashlog.patch new file mode 100644 index 0000000..b1c38a7 --- /dev/null +++ b/target/linux/generic/patches-3.18/930-crashlog.patch @@ -0,0 +1,276 @@ +--- /dev/null ++++ b/include/linux/crashlog.h +@@ -0,0 +1,17 @@ ++#ifndef __CRASHLOG_H ++#define __CRASHLOG_H ++ ++#ifdef CONFIG_CRASHLOG ++void crashlog_init_bootmem(struct bootmem_data *bdata); ++void crashlog_init_memblock(phys_addr_t addr, phys_addr_t size); ++#else ++static inline void crashlog_init_bootmem(struct bootmem_data *bdata) ++{ ++} ++ ++static inline void crashlog_init_memblock(phys_addr_t addr, phys_addr_t size) ++{ ++} ++#endif ++ ++#endif +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1279,6 +1279,10 @@ config RELAY + + If unsure, say N. + ++config CRASHLOG ++ bool "Crash logging" ++ depends on (!NO_BOOTMEM || HAVE_MEMBLOCK) && !(ARM || SPARC || PPC) ++ + config BLK_DEV_INITRD + bool "Initial RAM filesystem and RAM disk (initramfs/initrd) support" + depends on BROKEN || !FRV +--- a/kernel/Makefile ++++ b/kernel/Makefile +@@ -96,6 +96,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o + obj-$(CONFIG_JUMP_LABEL) += jump_label.o + obj-$(CONFIG_CONTEXT_TRACKING) += context_tracking.o + obj-$(CONFIG_TORTURE_TEST) += torture.o ++obj-$(CONFIG_CRASHLOG) += crashlog.o + + $(obj)/configs.o: $(obj)/config_data.h + +--- /dev/null ++++ b/kernel/crashlog.c +@@ -0,0 +1,181 @@ ++/* ++ * Crash information logger ++ * Copyright (C) 2010 Felix Fietkau ++ * ++ * Based on ramoops.c ++ * Copyright (C) 2010 Marco Stornelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CRASHLOG_PAGES 4 ++#define CRASHLOG_SIZE (CRASHLOG_PAGES * PAGE_SIZE) ++#define CRASHLOG_MAGIC 0xa1eedead ++ ++/* ++ * Start the log at 1M before the end of RAM, as some boot loaders like ++ * to use the end of the RAM for stack usage and other things ++ * If this fails, fall back to using the last part. ++ */ ++#define CRASHLOG_OFFSET (1024 * 1024) ++ ++struct crashlog_data { ++ u32 magic; ++ u32 len; ++ u8 data[]; ++}; ++ ++static struct debugfs_blob_wrapper crashlog_blob; ++static unsigned long crashlog_addr = 0; ++static struct crashlog_data *crashlog_buf; ++static struct kmsg_dumper dump; ++static bool first = true; ++ ++extern struct list_head *crashlog_modules; ++ ++#ifndef CONFIG_NO_BOOTMEM ++void __init crashlog_init_bootmem(bootmem_data_t *bdata) ++{ ++ unsigned long addr; ++ ++ if (crashlog_addr) ++ return; ++ ++ addr = PFN_PHYS(bdata->node_low_pfn) - CRASHLOG_OFFSET; ++ if (reserve_bootmem(addr, CRASHLOG_SIZE, BOOTMEM_EXCLUSIVE) < 0) { ++ printk("Crashlog failed to allocate RAM at address 0x%lx\n", addr); ++ bdata->node_low_pfn -= CRASHLOG_PAGES; ++ addr = PFN_PHYS(bdata->node_low_pfn); ++ } ++ crashlog_addr = addr; ++} ++#endif ++ ++#ifdef CONFIG_HAVE_MEMBLOCK ++void __meminit crashlog_init_memblock(phys_addr_t addr, phys_addr_t size) ++{ ++ if (crashlog_addr) ++ return; ++ ++ addr += size - CRASHLOG_OFFSET; ++ if (memblock_reserve(addr, CRASHLOG_SIZE)) { ++ printk("Crashlog failed to allocate RAM at address 0x%lx\n", (unsigned long) addr); ++ return; ++ } ++ ++ crashlog_addr = addr; ++} ++#endif ++ ++static void __init crashlog_copy(void) ++{ ++ if (crashlog_buf->magic != CRASHLOG_MAGIC) ++ return; ++ ++ if (!crashlog_buf->len || crashlog_buf->len > ++ CRASHLOG_SIZE - sizeof(*crashlog_buf)) ++ return; ++ ++ crashlog_blob.size = crashlog_buf->len; ++ crashlog_blob.data = kmemdup(crashlog_buf->data, ++ crashlog_buf->len, GFP_KERNEL); ++ ++ debugfs_create_blob("crashlog", 0700, NULL, &crashlog_blob); ++} ++ ++static int get_maxlen(void) ++{ ++ return CRASHLOG_SIZE - sizeof(*crashlog_buf) - crashlog_buf->len; ++} ++ ++static void crashlog_printf(const char *fmt, ...) ++{ ++ va_list args; ++ int len = get_maxlen(); ++ ++ if (!len) ++ return; ++ ++ va_start(args, fmt); ++ crashlog_buf->len += vscnprintf( ++ &crashlog_buf->data[crashlog_buf->len], ++ len, fmt, args); ++ va_end(args); ++} ++ ++static void crashlog_do_dump(struct kmsg_dumper *dumper, ++ enum kmsg_dump_reason reason) ++{ ++ struct timeval tv; ++ struct module *m; ++ char *buf; ++ size_t len; ++ ++ if (!first) ++ crashlog_printf("\n===================================\n"); ++ ++ do_gettimeofday(&tv); ++ crashlog_printf("Time: %lu.%lu\n", ++ (long)tv.tv_sec, (long)tv.tv_usec); ++ ++ if (first) { ++ crashlog_printf("Modules:"); ++ list_for_each_entry(m, crashlog_modules, list) { ++ crashlog_printf("\t%s@%p+%x", m->name, ++ m->module_core, m->core_size, ++ m->module_init, m->init_size); ++ } ++ crashlog_printf("\n"); ++ first = false; ++ } ++ ++ buf = (char *)&crashlog_buf->data[crashlog_buf->len]; ++ ++ kmsg_dump_get_buffer(dumper, true, buf, get_maxlen(), &len); ++ ++ crashlog_buf->len += len; ++} ++ ++ ++int __init crashlog_init_fs(void) ++{ ++ if (!crashlog_addr) ++ return -ENOMEM; ++ ++ crashlog_buf = ioremap(crashlog_addr, CRASHLOG_SIZE); ++ ++ crashlog_copy(); ++ ++ crashlog_buf->magic = CRASHLOG_MAGIC; ++ crashlog_buf->len = 0; ++ ++ dump.max_reason = KMSG_DUMP_OOPS; ++ dump.dump = crashlog_do_dump; ++ kmsg_dump_register(&dump); ++ ++ return 0; ++} ++module_init(crashlog_init_fs); +--- a/mm/bootmem.c ++++ b/mm/bootmem.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -177,6 +178,7 @@ static unsigned long __init free_all_boo + if (!bdata->node_bootmem_map) + return 0; + ++ crashlog_init_bootmem(bdata); + map = bdata->node_bootmem_map; + start = bdata->node_min_pfn; + end = bdata->node_low_pfn; +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -105,6 +105,9 @@ static LIST_HEAD(modules); + #ifdef CONFIG_KGDB_KDB + struct list_head *kdb_modules = &modules; /* kdb needs the list of modules */ + #endif /* CONFIG_KGDB_KDB */ ++#ifdef CONFIG_CRASHLOG ++struct list_head *crashlog_modules = &modules; ++#endif + + #ifdef CONFIG_MODULE_SIG + #ifdef CONFIG_MODULE_SIG_FORCE +--- a/mm/memblock.c ++++ b/mm/memblock.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -477,6 +478,8 @@ static void __init_memblock memblock_ins + memblock_set_region_node(rgn, nid); + type->cnt++; + type->total_size += size; ++ if (type == &memblock.memory && idx == 0) ++ crashlog_init_memblock(base, size); + } + + /** diff --git a/target/linux/generic/patches-3.18/940-ocf_kbuild_integration.patch b/target/linux/generic/patches-3.18/940-ocf_kbuild_integration.patch new file mode 100644 index 0000000..240f15e --- /dev/null +++ b/target/linux/generic/patches-3.18/940-ocf_kbuild_integration.patch @@ -0,0 +1,20 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -1519,3 +1519,6 @@ source "drivers/crypto/Kconfig" + source crypto/asymmetric_keys/Kconfig + + endif # if CRYPTO ++ ++source "crypto/ocf/Kconfig" ++ +--- a/crypto/Makefile ++++ b/crypto/Makefile +@@ -101,6 +101,8 @@ obj-$(CONFIG_CRYPTO_USER_API) += af_alg. + obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o + obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o + ++obj-$(CONFIG_OCF_OCF) += ocf/ ++ + # + # generic algorithms and the async_tx api + # diff --git a/target/linux/generic/patches-3.18/941-ocf_20120127.patch b/target/linux/generic/patches-3.18/941-ocf_20120127.patch new file mode 100644 index 0000000..ee36f1e --- /dev/null +++ b/target/linux/generic/patches-3.18/941-ocf_20120127.patch @@ -0,0 +1,166 @@ +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -139,6 +139,9 @@ + * that might otherwise be identical and have very little entropy + * available to them (particularly common in the embedded world). + * ++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++ * int random_input_wait(void); ++ * + * add_input_randomness() uses the input layer interrupt timing, as well as + * the event type information from the hardware. + * +@@ -152,6 +155,13 @@ + * seek times do not make for good sources of entropy, as their seek + * times are usually fairly consistent. + * ++ * random_input_words() just provides a raw block of entropy to the input ++ * pool, such as from a hardware entropy generator. ++ * ++ * random_input_wait() suspends the caller until such time as the ++ * entropy pool falls below the write threshold, and returns a count of how ++ * much entropy (in bits) is needed to sustain the pool. ++ * + * All of these routines try to estimate how many bits of randomness a + * particular randomness source. They do this by keeping track of the + * first and second order deltas of the event timings. +@@ -938,6 +948,63 @@ void add_disk_randomness(struct gendisk + EXPORT_SYMBOL_GPL(add_disk_randomness); + #endif + ++/* ++ * random_input_words - add bulk entropy to pool ++ * ++ * @buf: buffer to add ++ * @wordcount: number of __u32 words to add ++ * @ent_count: total amount of entropy (in bits) to credit ++ * ++ * this provides bulk input of entropy to the input pool ++ * ++ */ ++void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++{ ++ mix_pool_bytes(&input_pool, buf, wordcount*4); ++ ++ credit_entropy_bits(&input_pool, ent_count); ++ ++ pr_notice("crediting %d bits => %d\n", ++ ent_count, input_pool.entropy_count); ++ /* ++ * Wake up waiting processes if we have enough ++ * entropy. ++ */ ++ if (input_pool.entropy_count >= random_read_wakeup_bits) ++ wake_up_interruptible(&random_read_wait); ++} ++EXPORT_SYMBOL(random_input_words); ++ ++/* ++ * random_input_wait - wait until random needs entropy ++ * ++ * this function sleeps until the /dev/random subsystem actually ++ * needs more entropy, and then return the amount of entropy ++ * that it would be nice to have added to the system. ++ */ ++int random_input_wait(void) ++{ ++ int count; ++ ++ wait_event_interruptible(random_write_wait, ++ input_pool.entropy_count < random_write_wakeup_bits); ++ ++ count = random_write_wakeup_bits - input_pool.entropy_count; ++ ++ /* likely we got woken up due to a signal */ ++ if (count <= 0) count = random_read_wakeup_bits; ++ ++ pr_notice("requesting %d bits from input_wait()er %d<%d\n", ++ count, ++ input_pool.entropy_count, random_write_wakeup_bits); ++ ++ return count; ++} ++EXPORT_SYMBOL(random_input_wait); ++ ++ ++#define EXTRACT_SIZE 10 ++ + /********************************************************************* + * + * Entropy extraction routines +--- a/fs/fcntl.c ++++ b/fs/fcntl.c +@@ -140,6 +140,7 @@ pid_t f_getown(struct file *filp) + read_unlock(&filp->f_owner.lock); + return pid; + } ++EXPORT_SYMBOL(sys_dup); + + static int f_setown_ex(struct file *filp, unsigned long arg) + { +--- a/include/linux/miscdevice.h ++++ b/include/linux/miscdevice.h +@@ -19,6 +19,7 @@ + #define APOLLO_MOUSE_MINOR 7 /* unused */ + #define PC110PAD_MINOR 9 /* unused */ + /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ ++#define CRYPTODEV_MINOR 70 /* /dev/crypto */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +--- a/include/uapi/linux/random.h ++++ b/include/uapi/linux/random.h +@@ -34,6 +34,30 @@ + /* Clear the entropy pool and associated counters. (Superuser only.) */ + #define RNDCLEARPOOL _IO( 'R', 0x06 ) + ++#ifdef CONFIG_FIPS_RNG ++ ++/* Size of seed value - equal to AES blocksize */ ++#define AES_BLOCK_SIZE_BYTES 16 ++#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES ++/* Size of AES key */ ++#define KEY_SIZE_BYTES 16 ++ ++/* ioctl() structure used by FIPS 140-2 Tests */ ++struct rand_fips_test { ++ unsigned char key[KEY_SIZE_BYTES]; /* Input */ ++ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char result[SEED_SIZE_BYTES]; /* Output */ ++}; ++ ++/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ ++#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) ++ ++/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ ++#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) ++ ++#endif /* #ifdef CONFIG_FIPS_RNG */ ++ + struct rand_pool_info { + int entropy_count; + int buf_size; +--- a/include/linux/random.h ++++ b/include/linux/random.h +@@ -13,6 +13,10 @@ extern void add_input_randomness(unsigne + unsigned int value); + extern void add_interrupt_randomness(int irq, int irq_flags); + ++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); ++extern int random_input_wait(void); ++#define HAS_RANDOM_INPUT_WAIT 1 ++ + extern void get_random_bytes(void *buf, int nbytes); + extern void get_random_bytes_arch(void *buf, int nbytes); + void generate_random_uuid(unsigned char uuid_out[16]); +--- a/kernel/pid.c ++++ b/kernel/pid.c +@@ -427,6 +427,7 @@ void transfer_pid(struct task_struct *ol + new->pids[type].pid = old->pids[type].pid; + hlist_replace_rcu(&old->pids[type].node, &new->pids[type].node); + } ++EXPORT_SYMBOL(find_task_by_vpid); + + struct task_struct *pid_task(struct pid *pid, enum pid_type type) + { diff --git a/target/linux/generic/patches-3.18/960-decompress_unlzo_fix.patch b/target/linux/generic/patches-3.18/960-decompress_unlzo_fix.patch new file mode 100644 index 0000000..ee7c118 --- /dev/null +++ b/target/linux/generic/patches-3.18/960-decompress_unlzo_fix.patch @@ -0,0 +1,23 @@ +--- /dev/null ++++ b/include/linux/decompress/unlzo_mm.h +@@ -0,0 +1,10 @@ ++#ifndef UNLZO_MM_H ++#define UNLZO_MM_H ++ ++#ifdef STATIC ++#define INIT ++#else ++#define INIT __init ++#endif ++ ++#endif +--- a/lib/decompress_unlzo.c ++++ b/lib/decompress_unlzo.c +@@ -38,6 +38,7 @@ + + #include + #include ++#include + #include + + #include diff --git a/target/linux/generic/patches-3.18/970-remove-unsane-filenames-from-deps_initramfs-list.patch b/target/linux/generic/patches-3.18/970-remove-unsane-filenames-from-deps_initramfs-list.patch new file mode 100644 index 0000000..ac13c9e --- /dev/null +++ b/target/linux/generic/patches-3.18/970-remove-unsane-filenames-from-deps_initramfs-list.patch @@ -0,0 +1,29 @@ +--- a/usr/Makefile ++++ b/usr/Makefile +@@ -53,6 +53,8 @@ ifneq ($(wildcard $(obj)/.initramfs_data + include $(obj)/.initramfs_data.cpio.d + endif + ++deps_initramfs_sane := $(foreach v,$(deps_initramfs),$(if $(findstring :,$(v)),,$(v))) ++ + quiet_cmd_initfs = GEN $@ + cmd_initfs = $(initramfs) -o $@ $(ramfs-args) $(ramfs-input) + +@@ -61,14 +63,14 @@ targets := initramfs_data.cpio.gz initra + initramfs_data.cpio.lzo initramfs_data.cpio.lz4 \ + initramfs_data.cpio + # do not try to update files included in initramfs +-$(deps_initramfs): ; ++$(deps_initramfs_sane): ; + +-$(deps_initramfs): klibcdirs ++$(deps_initramfs_sane): klibcdirs + # We rebuild initramfs_data.cpio if: + # 1) Any included file is newer then initramfs_data.cpio + # 2) There are changes in which files are included (added or deleted) + # 3) If gen_init_cpio are newer than initramfs_data.cpio + # 4) arguments to gen_initramfs.sh changes +-$(obj)/initramfs_data.cpio$(suffix_y): $(obj)/gen_init_cpio $(deps_initramfs) klibcdirs ++$(obj)/initramfs_data.cpio$(suffix_y): $(obj)/gen_init_cpio $(deps_initramfs_sane) klibcdirs + $(Q)$(initramfs) -l $(ramfs-input) > $(obj)/.initramfs_data.cpio.d + $(call if_changed,initfs) diff --git a/target/linux/generic/patches-3.18/980-arm_openwrt_machtypes.patch b/target/linux/generic/patches-3.18/980-arm_openwrt_machtypes.patch new file mode 100644 index 0000000..5e9718b --- /dev/null +++ b/target/linux/generic/patches-3.18/980-arm_openwrt_machtypes.patch @@ -0,0 +1,32 @@ +--- a/arch/arm/tools/mach-types ++++ b/arch/arm/tools/mach-types +@@ -1007,3 +1007,29 @@ eco5_bx2 MACH_ECO5_BX2 ECO5_BX2 4572 + eukrea_cpuimx28sd MACH_EUKREA_CPUIMX28SD EUKREA_CPUIMX28SD 4573 + domotab MACH_DOMOTAB DOMOTAB 4574 + pfla03 MACH_PFLA03 PFLA03 4575 ++# ++# Additional mach-types supported by OpenWrt ++# ++wg302v1 MACH_WG302V1 WG302V1 889 ++pronghorn MACH_PRONGHORN PRONGHORN 928 ++pronghorn_metro MACH_PRONGHORNMETRO PRONGHORNMETRO 1040 ++sidewinder MACH_SIDEWINDER SIDEWINDER 1041 ++wrt300nv2 MACH_WRT300NV2 WRT300NV2 1077 ++compex42x MACH_COMPEXWP18 COMPEXWP18 1273 ++goldfish MACH_GOLDFISH GOLDFISH 1441 ++cambria MACH_CAMBRIA CAMBRIA 1468 ++dt2 MACH_DT2 DT2 1514 ++ap1000 MACH_AP1000 AP1000 1543 ++tw2662 MACH_TW2662 TW2662 1658 ++tw5334 MACH_TW5334 TW5334 1664 ++usr8200 MACH_USR8200 USR8200 1762 ++mi424wr MACH_MI424WR MI424WR 1778 ++gw2388 MACH_GW2388 GW2388 2635 ++iconnect MACH_ICONNECT ICONNECT 2870 ++nsb3ast MACH_NSB3AST NSB3AST 2917 ++goflexnet MACH_GOFLEXNET GOFLEXNET 3089 ++nas6210 MACH_NAS6210 NAS6210 3104 ++ns_k330 MACH_NS_K330 NS_K330 3108 ++bcm2708 MACH_BCM2708 BCM2708 3138 ++wn802t MACH_WN802T WN802T 3306 ++nsa310 MACH_NSA310 NSA310 4022 diff --git a/target/linux/generic/patches-3.18/990-gpio_wdt.patch b/target/linux/generic/patches-3.18/990-gpio_wdt.patch new file mode 100644 index 0000000..4742273 --- /dev/null +++ b/target/linux/generic/patches-3.18/990-gpio_wdt.patch @@ -0,0 +1,360 @@ +This generic GPIO watchdog is used on Huawei E970 (brcm47xx) + +Signed-off-by: Mathias Adam + +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1139,6 +1139,15 @@ config WDT_MTX1 + Hardware driver for the MTX-1 boards. This is a watchdog timer that + will reboot the machine after a 100 seconds timer expired. + ++config GPIO_WDT ++ tristate "GPIO Hardware Watchdog" ++ help ++ Hardware driver for GPIO-controlled watchdogs. GPIO pin and ++ toggle interval settings are platform-specific. The driver ++ will stop toggling the GPIO (i.e. machine reboots) after a ++ 100 second timer expired and no process has written to ++ /dev/watchdog during that time. ++ + config PNX833X_WDT + tristate "PNX833x Hardware Watchdog" + depends on SOC_PNX8335 +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -134,6 +134,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt + obj-$(CONFIG_INDYDOG) += indydog.o + obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o + obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o ++obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o +--- /dev/null ++++ b/drivers/watchdog/old_gpio_wdt.c +@@ -0,0 +1,301 @@ ++/* ++ * Driver for GPIO-controlled Hardware Watchdogs. ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * Replaces mtx1_wdt (driver for the MTX-1 Watchdog): ++ * ++ * (C) Copyright 2005 4G Systems , ++ * All Rights Reserved. ++ * http://www.4g-systems.biz ++ * ++ * (C) Copyright 2007 OpenWrt.org, Florian Fainelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Neither Michael Stickel nor 4G Systems admit liability nor provide ++ * warranty for any of this software. This material is provided ++ * "AS-IS" and at no charge. ++ * ++ * (c) Copyright 2005 4G Systems ++ * ++ * Release 0.01. ++ * Author: Michael Stickel michael.stickel@4g-systems.biz ++ * ++ * Release 0.02. ++ * Author: Florian Fainelli florian@openwrt.org ++ * use the Linux watchdog/timer APIs ++ * ++ * Release 0.03. ++ * Author: Mathias Adam ++ * make it a generic gpio watchdog driver ++ * ++ * The Watchdog is configured to reset the MTX-1 ++ * if it is not triggered for 100 seconds. ++ * It should not be triggered more often than 1.6 seconds. ++ * ++ * A timer triggers the watchdog every 5 seconds, until ++ * it is opened for the first time. After the first open ++ * it MUST be triggered every 2..95 seconds. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ticks = 100 * HZ; ++ ++static struct { ++ struct completion stop; ++ spinlock_t lock; ++ int running; ++ struct timer_list timer; ++ int queue; ++ int default_ticks; ++ unsigned long inuse; ++ unsigned gpio; ++ unsigned int gstate; ++ int interval; ++ int first_interval; ++} gpio_wdt_device; ++ ++static void gpio_wdt_trigger(unsigned long unused) ++{ ++ spin_lock(&gpio_wdt_device.lock); ++ if (gpio_wdt_device.running && ticks > 0) ++ ticks -= gpio_wdt_device.interval; ++ ++ /* toggle wdt gpio */ ++ gpio_wdt_device.gstate = !gpio_wdt_device.gstate; ++ gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate); ++ ++ if (gpio_wdt_device.queue && ticks > 0) ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval); ++ else ++ complete(&gpio_wdt_device.stop); ++ spin_unlock(&gpio_wdt_device.lock); ++} ++ ++static void gpio_wdt_reset(void) ++{ ++ ticks = gpio_wdt_device.default_ticks; ++} ++ ++ ++static void gpio_wdt_start(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (!gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 1; ++ gpio_wdt_device.gstate = 1; ++ gpio_set_value(gpio_wdt_device.gpio, 1); ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval); ++ } ++ gpio_wdt_device.running++; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++} ++ ++static int gpio_wdt_stop(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ gpio_wdt_device.gstate = 0; ++ gpio_set_value(gpio_wdt_device.gpio, 0); ++ } ++ ticks = gpio_wdt_device.default_ticks; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++ return 0; ++} ++ ++/* Filesystem functions */ ++ ++static int gpio_wdt_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(0, &gpio_wdt_device.inuse)) ++ return -EBUSY; ++ return nonseekable_open(inode, file); ++} ++ ++ ++static int gpio_wdt_release(struct inode *inode, struct file *file) ++{ ++ clear_bit(0, &gpio_wdt_device.inuse); ++ return 0; ++} ++ ++static long gpio_wdt_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ void __user *argp = (void __user *)arg; ++ int __user *p = (int __user *)argp; ++ unsigned int value; ++ static const struct watchdog_info ident = { ++ .options = WDIOF_CARDRESET, ++ .identity = "GPIO WDT", ++ }; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ if (copy_to_user(argp, &ident, sizeof(ident))) ++ return -EFAULT; ++ break; ++ case WDIOC_GETSTATUS: ++ case WDIOC_GETBOOTSTATUS: ++ put_user(0, p); ++ break; ++ case WDIOC_SETOPTIONS: ++ if (get_user(value, p)) ++ return -EFAULT; ++ if (value & WDIOS_ENABLECARD) ++ gpio_wdt_start(); ++ else if (value & WDIOS_DISABLECARD) ++ gpio_wdt_stop(); ++ else ++ return -EINVAL; ++ return 0; ++ case WDIOC_KEEPALIVE: ++ gpio_wdt_reset(); ++ break; ++ default: ++ return -ENOTTY; ++ } ++ return 0; ++} ++ ++ ++static ssize_t gpio_wdt_write(struct file *file, const char *buf, ++ size_t count, loff_t *ppos) ++{ ++ if (!count) ++ return -EIO; ++ gpio_wdt_reset(); ++ return count; ++} ++ ++static const struct file_operations gpio_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .unlocked_ioctl = gpio_wdt_ioctl, ++ .open = gpio_wdt_open, ++ .write = gpio_wdt_write, ++ .release = gpio_wdt_release, ++}; ++ ++ ++static struct miscdevice gpio_wdt_misc = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &gpio_wdt_fops, ++}; ++ ++ ++static int gpio_wdt_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data; ++ ++ gpio_wdt_device.gpio = gpio_wdt_data->gpio; ++ gpio_wdt_device.interval = gpio_wdt_data->interval; ++ gpio_wdt_device.first_interval = gpio_wdt_data->first_interval; ++ if (gpio_wdt_device.first_interval <= 0) { ++ gpio_wdt_device.first_interval = gpio_wdt_device.interval; ++ } ++ ++ ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt"); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to request gpio"); ++ return ret; ++ } ++ ++ spin_lock_init(&gpio_wdt_device.lock); ++ init_completion(&gpio_wdt_device.stop); ++ gpio_wdt_device.queue = 0; ++ clear_bit(0, &gpio_wdt_device.inuse); ++ setup_timer(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L); ++ gpio_wdt_device.default_ticks = ticks; ++ ++ gpio_wdt_start(); ++ dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n", ++ gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval); ++ return 0; ++} ++ ++static int gpio_wdt_remove(struct platform_device *pdev) ++{ ++ /* FIXME: do we need to lock this test ? */ ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ wait_for_completion(&gpio_wdt_device.stop); ++ } ++ ++ gpio_free(gpio_wdt_device.gpio); ++ misc_deregister(&gpio_wdt_misc); ++ return 0; ++} ++ ++static struct platform_driver gpio_wdt_driver = { ++ .probe = gpio_wdt_probe, ++ .remove = gpio_wdt_remove, ++ .driver.name = "gpio-wdt", ++ .driver.owner = THIS_MODULE, ++}; ++ ++static int __init gpio_wdt_init(void) ++{ ++ return platform_driver_register(&gpio_wdt_driver); ++} ++arch_initcall(gpio_wdt_init); ++ ++/* ++ * We do wdt initialization in two steps: arch_initcall probes the wdt ++ * very early to start pinging the watchdog (misc devices are not yet ++ * available), and later module_init() just registers the misc device. ++ */ ++static int gpio_wdt_init_late(void) ++{ ++ int ret; ++ ++ ret = misc_register(&gpio_wdt_misc); ++ if (ret < 0) { ++ pr_err("GPIO_WDT: failed to register misc device\n"); ++ return ret; ++ } ++ return 0; ++} ++#ifndef MODULE ++module_init(gpio_wdt_init_late); ++#endif ++ ++static void __exit gpio_wdt_exit(void) ++{ ++ platform_driver_unregister(&gpio_wdt_driver); ++} ++module_exit(gpio_wdt_exit); ++ ++MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam"); ++MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:gpio-wdt"); +--- /dev/null ++++ b/include/linux/old_gpio_wdt.h +@@ -0,0 +1,21 @@ ++/* ++ * Definitions for the GPIO watchdog driver ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef _GPIO_WDT_H_ ++#define _GPIO_WDT_H_ ++ ++struct gpio_wdt_platform_data { ++ int gpio; /* GPIO line number */ ++ int interval; /* watchdog reset interval in system ticks */ ++ int first_interval; /* first wd reset interval in system ticks */ ++}; ++ ++#endif /* _GPIO_WDT_H_ */ diff --git a/target/linux/generic/patches-3.18/995-mangle_bootargs.patch b/target/linux/generic/patches-3.18/995-mangle_bootargs.patch new file mode 100644 index 0000000..0029e90 --- /dev/null +++ b/target/linux/generic/patches-3.18/995-mangle_bootargs.patch @@ -0,0 +1,58 @@ +--- a/init/main.c ++++ b/init/main.c +@@ -362,6 +362,29 @@ static inline void setup_nr_cpu_ids(void + static inline void smp_prepare_cpus(unsigned int maxcpus) { } + #endif + ++#ifdef CONFIG_MANGLE_BOOTARGS ++static void __init mangle_bootargs(char *command_line) ++{ ++ char *rootdev; ++ char *rootfs; ++ ++ rootdev = strstr(command_line, "root=/dev/mtdblock"); ++ ++ if (rootdev) ++ strncpy(rootdev, "mangled_rootblock=", 18); ++ ++ rootfs = strstr(command_line, "rootfstype"); ++ ++ if (rootfs) ++ strncpy(rootfs, "mangled_fs", 10); ++ ++} ++#else ++static void __init mangle_bootargs(char *command_line) ++{ ++} ++#endif ++ + /* + * We need to store the untouched command line for future reference. + * We also need to store the touched command line since the parameter +@@ -530,6 +553,7 @@ asmlinkage __visible void __init start_k + pr_notice("%s", linux_banner); + setup_arch(&command_line); + mm_init_cpumask(&init_mm); ++ mangle_bootargs(command_line); + setup_command_line(command_line); + setup_nr_cpu_ids(); + setup_per_cpu_areas(); +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1597,6 +1597,15 @@ config EMBEDDED + an embedded system so certain expert options are available + for configuration. + ++config MANGLE_BOOTARGS ++ bool "Rename offending bootargs" ++ depends on EXPERT ++ help ++ Sometimes the bootloader passed bogus root= and rootfstype= ++ parameters to the kernel, and while you want to ignore them, ++ you need to know the values f.e. to support dual firmware ++ layouts on the flash. ++ + config HAVE_PERF_EVENTS + bool + help diff --git a/target/linux/generic/patches-3.18/997-device_tree_cmdline.patch b/target/linux/generic/patches-3.18/997-device_tree_cmdline.patch new file mode 100644 index 0000000..dd725b0 --- /dev/null +++ b/target/linux/generic/patches-3.18/997-device_tree_cmdline.patch @@ -0,0 +1,24 @@ +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -903,6 +903,9 @@ int __init early_init_dt_scan_chosen(uns + p = of_get_flat_dt_prop(node, "bootargs", &l); + if (p != NULL && l > 0) + strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); ++ p = of_get_flat_dt_prop(node, "bootargs-append", &l); ++ if (p != NULL && l > 0) ++ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else +--- a/arch/mips/kernel/prom.c ++++ b/arch/mips/kernel/prom.c +@@ -49,6 +49,9 @@ void * __init early_init_dt_alloc_memory + + void __init __dt_setup_arch(void *bph) + { ++ if (boot_command_line[0] == '\0') ++ strcpy(boot_command_line, arcs_cmdline); ++ + if (!early_init_dt_scan(bph)) + return; + diff --git a/target/linux/generic/patches-3.18/998-enable_wilink_platform_without_drivers.patch b/target/linux/generic/patches-3.18/998-enable_wilink_platform_without_drivers.patch new file mode 100644 index 0000000..d317de1 --- /dev/null +++ b/target/linux/generic/patches-3.18/998-enable_wilink_platform_without_drivers.patch @@ -0,0 +1,15 @@ +We use backports for driver updates - make sure we can compile in the glue code regardless + +Signed-off-by: Imre Kaloz + +--- a/drivers/net/wireless/ti/Kconfig ++++ b/drivers/net/wireless/ti/Kconfig +@@ -15,7 +15,7 @@ source "drivers/net/wireless/ti/wlcore/K + + config WILINK_PLATFORM_DATA + bool "TI WiLink platform data" +- depends on WLCORE_SDIO || WL1251_SDIO ++ depends on WLCORE_SDIO || WL1251_SDIO || ARCH_OMAP2PLUS + default y + ---help--- + Small platform data bit needed to pass data to the sdio modules. diff --git a/target/linux/generic/patches-3.18/999-seccomp_log.patch b/target/linux/generic/patches-3.18/999-seccomp_log.patch new file mode 100644 index 0000000..1db6b18 --- /dev/null +++ b/target/linux/generic/patches-3.18/999-seccomp_log.patch @@ -0,0 +1,34 @@ +--- a/kernel/seccomp.c ++++ b/kernel/seccomp.c +@@ -614,6 +614,7 @@ int __secure_computing(void) + #ifdef CONFIG_SECCOMP_FILTER + static u32 __seccomp_phase1_filter(int this_syscall, struct seccomp_data *sd) + { ++ char name[sizeof(current->comm)]; + u32 filter_ret, action; + int data; + +@@ -644,6 +645,13 @@ static u32 __seccomp_phase1_filter(int t + case SECCOMP_RET_TRACE: + return filter_ret; /* Save the rest for phase 2. */ + ++ case SECCOMP_RET_LOG: ++ get_task_comm(name, current); ++ pr_err_ratelimited("seccomp: %s [%u] tried to call non-whitelisted syscall: %d\n", name, current->pid, this_syscall); ++ syscall_set_return_value(current, task_pt_regs(current), ++ -data, 0); ++ goto skip; ++ + case SECCOMP_RET_ALLOW: + return SECCOMP_PHASE1_OK; + +--- a/include/uapi/linux/seccomp.h ++++ b/include/uapi/linux/seccomp.h +@@ -28,6 +28,7 @@ + #define SECCOMP_RET_KILL 0x00000000U /* kill the task immediately */ + #define SECCOMP_RET_TRAP 0x00030000U /* disallow and force a SIGSYS */ + #define SECCOMP_RET_ERRNO 0x00050000U /* returns an errno */ ++#define SECCOMP_RET_LOG 0x00070000U /* allow + logline */ + #define SECCOMP_RET_TRACE 0x7ff00000U /* pass to a tracer or disallow */ + #define SECCOMP_RET_ALLOW 0x7fff0000U /* allow */ + diff --git a/target/linux/generic/patches-4.0/000-keep_initrafs_the_default.patch b/target/linux/generic/patches-4.0/000-keep_initrafs_the_default.patch new file mode 100644 index 0000000..7d28e02 --- /dev/null +++ b/target/linux/generic/patches-4.0/000-keep_initrafs_the_default.patch @@ -0,0 +1,25 @@ +Upstream changed the default rootfs to tmpfs when none has been passed +to the kernel - this doesn't fit our purposes, so change it back. + +Signed-off-by: Imre Kaloz + +--- a/init/do_mounts.c ++++ b/init/do_mounts.c +@@ -625,6 +625,7 @@ int __init init_rootfs(void) + if (err) + return err; + ++#if 0 + if (IS_ENABLED(CONFIG_TMPFS) && !saved_root_name[0] && + (!root_fs_names || strstr(root_fs_names, "tmpfs"))) { + err = shmem_init(); +@@ -632,6 +633,9 @@ int __init init_rootfs(void) + } else { + err = init_ramfs_fs(); + } ++#else ++ err = init_ramfs_fs(); ++#endif + + if (err) + unregister_filesystem(&rootfs_fs_type); diff --git a/target/linux/generic/patches-4.0/020-ssb_update.patch b/target/linux/generic/patches-4.0/020-ssb_update.patch new file mode 100644 index 0000000..d7e15ae --- /dev/null +++ b/target/linux/generic/patches-4.0/020-ssb_update.patch @@ -0,0 +1,30 @@ +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -357,6 +357,16 @@ static void ssb_pcicore_init_hostmode(st + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, + SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); + ++ /* ++ * Accessing PCI config without a proper delay after devices reset (not ++ * GPIO reset) was causing reboots on WRT300N v1.0 (BCM4704). ++ * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it ++ * completely. Flushing all writes was also tested but with no luck. ++ * The same problem was reported for WRT350N v1 (BCM4705), so we just ++ * sleep here unconditionally. ++ */ ++ usleep_range(1000, 2000); ++ + /* Enable PCI bridge BAR0 prefetch and burst */ + val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); +--- a/drivers/ssb/main.c ++++ b/drivers/ssb/main.c +@@ -1135,6 +1135,8 @@ static u32 ssb_tmslow_reject_bitmask(str + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ + case SSB_IDLOW_SSBREV_27: /* same here */ + return SSB_TMSLOW_REJECT; /* this is a guess */ ++ case SSB_IDLOW_SSBREV: ++ break; + default: + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); + } diff --git a/target/linux/generic/patches-4.0/021-bcma-from-4.1.patch b/target/linux/generic/patches-4.0/021-bcma-from-4.1.patch new file mode 100644 index 0000000..8f3e167 --- /dev/null +++ b/target/linux/generic/patches-4.0/021-bcma-from-4.1.patch @@ -0,0 +1,680 @@ +--- a/drivers/bcma/bcma_private.h ++++ b/drivers/bcma/bcma_private.h +@@ -26,6 +26,7 @@ bool bcma_wait_value(struct bcma_device + int timeout); + void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core); + void bcma_init_bus(struct bcma_bus *bus); ++void bcma_unregister_cores(struct bcma_bus *bus); + int bcma_bus_register(struct bcma_bus *bus); + void bcma_bus_unregister(struct bcma_bus *bus); + int __init bcma_bus_early_register(struct bcma_bus *bus); +@@ -42,6 +43,9 @@ int bcma_bus_scan(struct bcma_bus *bus); + int bcma_sprom_get(struct bcma_bus *bus); + + /* driver_chipcommon.c */ ++void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); ++void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); ++void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); + #ifdef CONFIG_BCMA_DRIVER_MIPS + void bcma_chipco_serial_init(struct bcma_drv_cc *cc); + extern struct platform_device bcma_pflash_dev; +@@ -52,6 +56,8 @@ int bcma_core_chipcommon_b_init(struct b + void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb); + + /* driver_chipcommon_pmu.c */ ++void bcma_pmu_early_init(struct bcma_drv_cc *cc); ++void bcma_pmu_init(struct bcma_drv_cc *cc); + u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc); + u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc); + +@@ -100,7 +106,35 @@ static inline void __exit bcma_host_soc_ + #endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */ + + /* driver_pci.c */ ++#ifdef CONFIG_BCMA_DRIVER_PCI + u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address); ++void bcma_core_pci_early_init(struct bcma_drv_pci *pc); ++void bcma_core_pci_init(struct bcma_drv_pci *pc); ++void bcma_core_pci_up(struct bcma_drv_pci *pc); ++void bcma_core_pci_down(struct bcma_drv_pci *pc); ++#else ++static inline void bcma_core_pci_early_init(struct bcma_drv_pci *pc) ++{ ++ WARN_ON(pc->core->bus->hosttype == BCMA_HOSTTYPE_PCI); ++} ++static inline void bcma_core_pci_init(struct bcma_drv_pci *pc) ++{ ++ /* Initialization is required for PCI hosted bus */ ++ WARN_ON(pc->core->bus->hosttype == BCMA_HOSTTYPE_PCI); ++} ++#endif ++ ++/* driver_pcie2.c */ ++#ifdef CONFIG_BCMA_DRIVER_PCI ++void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2); ++void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2); ++#else ++static inline void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2) ++{ ++ /* Initialization is required for PCI hosted bus */ ++ WARN_ON(pcie2->core->bus->hosttype == BCMA_HOSTTYPE_PCI); ++} ++#endif + + extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc); + +@@ -117,6 +151,39 @@ static inline void bcma_core_pci_hostmod + } + #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ + ++/************************************************** ++ * driver_mips.c ++ **************************************************/ ++ ++#ifdef CONFIG_BCMA_DRIVER_MIPS ++unsigned int bcma_core_mips_irq(struct bcma_device *dev); ++void bcma_core_mips_early_init(struct bcma_drv_mips *mcore); ++void bcma_core_mips_init(struct bcma_drv_mips *mcore); ++#else ++static inline unsigned int bcma_core_mips_irq(struct bcma_device *dev) ++{ ++ return 0; ++} ++static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) ++{ ++} ++static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) ++{ ++} ++#endif ++ ++/************************************************** ++ * driver_gmac_cmn.c ++ **************************************************/ ++ ++#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN ++void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc); ++#else ++static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) ++{ ++} ++#endif ++ + #ifdef CONFIG_BCMA_DRIVER_GPIO + /* driver_gpio.c */ + int bcma_gpio_init(struct bcma_drv_cc *cc); +--- a/drivers/bcma/driver_gpio.c ++++ b/drivers/bcma/driver_gpio.c +@@ -17,6 +17,8 @@ + + #include "bcma_private.h" + ++#define BCMA_GPIO_MAX_PINS 32 ++ + static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip) + { + return container_of(chip, struct bcma_drv_cc, gpio); +@@ -76,7 +78,7 @@ static void bcma_gpio_free(struct gpio_c + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); + } + +-#if IS_BUILTIN(CONFIG_BCM47XX) ++#if IS_BUILTIN(CONFIG_BCM47XX) || IS_BUILTIN(CONFIG_ARCH_BCM_5301X) + static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) + { + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); +@@ -204,6 +206,7 @@ static void bcma_gpio_irq_domain_exit(st + + int bcma_gpio_init(struct bcma_drv_cc *cc) + { ++ struct bcma_bus *bus = cc->core->bus; + struct gpio_chip *chip = &cc->gpio; + int err; + +@@ -215,14 +218,14 @@ int bcma_gpio_init(struct bcma_drv_cc *c + chip->set = bcma_gpio_set_value; + chip->direction_input = bcma_gpio_direction_input; + chip->direction_output = bcma_gpio_direction_output; +-#if IS_BUILTIN(CONFIG_BCM47XX) ++#if IS_BUILTIN(CONFIG_BCM47XX) || IS_BUILTIN(CONFIG_ARCH_BCM_5301X) + chip->to_irq = bcma_gpio_to_irq; + #endif + #if IS_BUILTIN(CONFIG_OF) + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) + chip->of_node = cc->core->dev.of_node; + #endif +- switch (cc->core->bus->chipinfo.id) { ++ switch (bus->chipinfo.id) { + case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: + chip->ngpio = 32; +@@ -231,13 +234,17 @@ int bcma_gpio_init(struct bcma_drv_cc *c + chip->ngpio = 16; + } + +- /* There is just one SoC in one device and its GPIO addresses should be +- * deterministic to address them more easily. The other buses could get +- * a random base number. */ +- if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) +- chip->base = 0; +- else +- chip->base = -1; ++ /* ++ * On MIPS we register GPIO devices (LEDs, buttons) using absolute GPIO ++ * pin numbers. We don't have Device Tree there and we can't really use ++ * relative (per chip) numbers. ++ * So let's use predictable base for BCM47XX and "random" for all other. ++ */ ++#if IS_BUILTIN(CONFIG_BCM47XX) ++ chip->base = bus->num * BCMA_GPIO_MAX_PINS; ++#else ++ chip->base = -1; ++#endif + + err = bcma_gpio_irq_domain_init(cc); + if (err) +--- a/drivers/bcma/driver_pci.c ++++ b/drivers/bcma/driver_pci.c +@@ -282,39 +282,6 @@ void bcma_core_pci_power_save(struct bcm + } + EXPORT_SYMBOL_GPL(bcma_core_pci_power_save); + +-int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, +- bool enable) +-{ +- struct pci_dev *pdev; +- u32 coremask, tmp; +- int err = 0; +- +- if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) { +- /* This bcma device is not on a PCI host-bus. So the IRQs are +- * not routed through the PCI core. +- * So we must not enable routing through the PCI core. */ +- goto out; +- } +- +- pdev = pc->core->bus->host_pci; +- +- err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); +- if (err) +- goto out; +- +- coremask = BIT(core->core_index) << 8; +- if (enable) +- tmp |= coremask; +- else +- tmp &= ~coremask; +- +- err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp); +- +-out: +- return err; +-} +-EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); +- + static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend) + { + u32 w; +@@ -328,28 +295,12 @@ static void bcma_core_pci_extend_L1timer + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); + } + +-void bcma_core_pci_up(struct bcma_bus *bus) ++void bcma_core_pci_up(struct bcma_drv_pci *pc) + { +- struct bcma_drv_pci *pc; +- +- if (bus->hosttype != BCMA_HOSTTYPE_PCI) +- return; +- +- pc = &bus->drv_pci[0]; +- + bcma_core_pci_extend_L1timer(pc, true); + } +-EXPORT_SYMBOL_GPL(bcma_core_pci_up); + +-void bcma_core_pci_down(struct bcma_bus *bus) ++void bcma_core_pci_down(struct bcma_drv_pci *pc) + { +- struct bcma_drv_pci *pc; +- +- if (bus->hosttype != BCMA_HOSTTYPE_PCI) +- return; +- +- pc = &bus->drv_pci[0]; +- + bcma_core_pci_extend_L1timer(pc, false); + } +-EXPORT_SYMBOL_GPL(bcma_core_pci_down); +--- a/drivers/bcma/driver_pci_host.c ++++ b/drivers/bcma/driver_pci_host.c +@@ -11,6 +11,7 @@ + + #include "bcma_private.h" + #include ++#include + #include + #include + #include +--- a/drivers/bcma/driver_pcie2.c ++++ b/drivers/bcma/driver_pcie2.c +@@ -10,6 +10,7 @@ + + #include "bcma_private.h" + #include ++#include + + /************************************************** + * R/W ops. +@@ -156,14 +157,23 @@ static void pciedev_reg_pm_clk_period(st + + void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2) + { +- struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo; ++ struct bcma_bus *bus = pcie2->core->bus; ++ struct bcma_chipinfo *ci = &bus->chipinfo; + u32 tmp; + + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54)); + if ((tmp & 0xe) >> 1 == 2) + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17); + +- /* TODO: Do we need pcie_reqsize? */ ++ switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4360: ++ case BCMA_CHIP_ID_BCM4352: ++ pcie2->reqsize = 1024; ++ break; ++ default: ++ pcie2->reqsize = 128; ++ break; ++ } + + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3) + bcma_core_pcie2_war_delay_perst_enab(pcie2, true); +@@ -173,3 +183,18 @@ void bcma_core_pcie2_init(struct bcma_dr + pciedev_crwlpciegen2_180(pcie2); + pciedev_crwlpciegen2_182(pcie2); + } ++ ++/************************************************** ++ * Runtime ops. ++ **************************************************/ ++ ++void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2) ++{ ++ struct bcma_bus *bus = pcie2->core->bus; ++ struct pci_dev *dev = bus->host_pci; ++ int err; ++ ++ err = pcie_set_readrq(dev, pcie2->reqsize); ++ if (err) ++ bcma_err(bus, "Error setting PCI_EXP_DEVCTL_READRQ: %d\n", err); ++} +--- a/drivers/bcma/host_pci.c ++++ b/drivers/bcma/host_pci.c +@@ -213,16 +213,26 @@ static int bcma_host_pci_probe(struct pc + /* Initialize struct, detect chip */ + bcma_init_bus(bus); + ++ /* Scan bus to find out generation of PCIe core */ ++ err = bcma_bus_scan(bus); ++ if (err) ++ goto err_pci_unmap_mmio; ++ ++ if (bcma_find_core(bus, BCMA_CORE_PCIE2)) ++ bus->host_is_pcie2 = true; ++ + /* Register */ + err = bcma_bus_register(bus); + if (err) +- goto err_pci_unmap_mmio; ++ goto err_unregister_cores; + + pci_set_drvdata(dev, bus); + + out: + return err; + ++err_unregister_cores: ++ bcma_unregister_cores(bus); + err_pci_unmap_mmio: + pci_iounmap(dev, bus->mmio); + err_pci_release_regions: +@@ -283,9 +293,12 @@ static const struct pci_device_id bcma_p + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) }, ++ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43b1) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) }, + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xa8db, BCM43217 (sic!) */ + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43228) }, /* 0xa8dc */ +@@ -310,3 +323,65 @@ void __exit bcma_host_pci_exit(void) + { + pci_unregister_driver(&bcma_pci_bridge_driver); + } ++ ++/************************************************** ++ * Runtime ops for drivers. ++ **************************************************/ ++ ++/* See also pcicore_up */ ++void bcma_host_pci_up(struct bcma_bus *bus) ++{ ++ if (bus->hosttype != BCMA_HOSTTYPE_PCI) ++ return; ++ ++ if (bus->host_is_pcie2) ++ bcma_core_pcie2_up(&bus->drv_pcie2); ++ else ++ bcma_core_pci_up(&bus->drv_pci[0]); ++} ++EXPORT_SYMBOL_GPL(bcma_host_pci_up); ++ ++/* See also pcicore_down */ ++void bcma_host_pci_down(struct bcma_bus *bus) ++{ ++ if (bus->hosttype != BCMA_HOSTTYPE_PCI) ++ return; ++ ++ if (!bus->host_is_pcie2) ++ bcma_core_pci_down(&bus->drv_pci[0]); ++} ++EXPORT_SYMBOL_GPL(bcma_host_pci_down); ++ ++/* See also si_pci_setup */ ++int bcma_host_pci_irq_ctl(struct bcma_bus *bus, struct bcma_device *core, ++ bool enable) ++{ ++ struct pci_dev *pdev; ++ u32 coremask, tmp; ++ int err = 0; ++ ++ if (bus->hosttype != BCMA_HOSTTYPE_PCI) { ++ /* This bcma device is not on a PCI host-bus. So the IRQs are ++ * not routed through the PCI core. ++ * So we must not enable routing through the PCI core. */ ++ goto out; ++ } ++ ++ pdev = bus->host_pci; ++ ++ err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); ++ if (err) ++ goto out; ++ ++ coremask = BIT(core->core_index) << 8; ++ if (enable) ++ tmp |= coremask; ++ else ++ tmp &= ~coremask; ++ ++ err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp); ++ ++out: ++ return err; ++} ++EXPORT_SYMBOL_GPL(bcma_host_pci_irq_ctl); +--- a/drivers/bcma/main.c ++++ b/drivers/bcma/main.c +@@ -363,7 +363,7 @@ static int bcma_register_devices(struct + return 0; + } + +-static void bcma_unregister_cores(struct bcma_bus *bus) ++void bcma_unregister_cores(struct bcma_bus *bus) + { + struct bcma_device *core, *tmp; + +--- a/drivers/net/wireless/b43/main.c ++++ b/drivers/net/wireless/b43/main.c +@@ -4819,7 +4819,7 @@ static void b43_wireless_core_exit(struc + switch (dev->dev->bus_type) { + #ifdef CONFIG_B43_BCMA + case B43_BUS_BCMA: +- bcma_core_pci_down(dev->dev->bdev->bus); ++ bcma_host_pci_down(dev->dev->bdev->bus); + break; + #endif + #ifdef CONFIG_B43_SSB +@@ -4866,9 +4866,9 @@ static int b43_wireless_core_init(struct + switch (dev->dev->bus_type) { + #ifdef CONFIG_B43_BCMA + case B43_BUS_BCMA: +- bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0], ++ bcma_host_pci_irq_ctl(dev->dev->bdev->bus, + dev->dev->bdev, true); +- bcma_core_pci_up(dev->dev->bdev->bus); ++ bcma_host_pci_up(dev->dev->bdev->bus); + break; + #endif + #ifdef CONFIG_B43_SSB +--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c ++++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c +@@ -4668,7 +4668,7 @@ static int brcms_b_attach(struct brcms_c + brcms_c_coredisable(wlc_hw); + + /* Match driver "down" state */ +- bcma_core_pci_down(wlc_hw->d11core->bus); ++ bcma_host_pci_down(wlc_hw->d11core->bus); + + /* turn off pll and xtal to match driver "down" state */ + brcms_b_xtal(wlc_hw, OFF); +@@ -4959,7 +4959,7 @@ static int brcms_b_up_prep(struct brcms_ + * Configure pci/pcmcia here instead of in brcms_c_attach() + * to allow mfg hotswap: down, hotswap (chip power cycle), up. + */ +- bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core, ++ bcma_host_pci_irq_ctl(wlc_hw->d11core->bus, wlc_hw->d11core, + true); + + /* +@@ -4969,12 +4969,12 @@ static int brcms_b_up_prep(struct brcms_ + */ + if (brcms_b_radio_read_hwdisabled(wlc_hw)) { + /* put SB PCI in down state again */ +- bcma_core_pci_down(wlc_hw->d11core->bus); ++ bcma_host_pci_down(wlc_hw->d11core->bus); + brcms_b_xtal(wlc_hw, OFF); + return -ENOMEDIUM; + } + +- bcma_core_pci_up(wlc_hw->d11core->bus); ++ bcma_host_pci_up(wlc_hw->d11core->bus); + + /* reset the d11 core */ + brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); +@@ -5171,7 +5171,7 @@ static int brcms_b_down_finish(struct br + + /* turn off primary xtal and pll */ + if (!wlc_hw->noreset) { +- bcma_core_pci_down(wlc_hw->d11core->bus); ++ bcma_host_pci_down(wlc_hw->d11core->bus); + brcms_b_xtal(wlc_hw, OFF); + } + } +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -434,6 +434,27 @@ static inline struct bcma_device *bcma_f + return bcma_find_core_unit(bus, coreid, 0); + } + ++#ifdef CONFIG_BCMA_HOST_PCI ++extern void bcma_host_pci_up(struct bcma_bus *bus); ++extern void bcma_host_pci_down(struct bcma_bus *bus); ++extern int bcma_host_pci_irq_ctl(struct bcma_bus *bus, ++ struct bcma_device *core, bool enable); ++#else ++static inline void bcma_host_pci_up(struct bcma_bus *bus) ++{ ++} ++static inline void bcma_host_pci_down(struct bcma_bus *bus) ++{ ++} ++static inline int bcma_host_pci_irq_ctl(struct bcma_bus *bus, ++ struct bcma_device *core, bool enable) ++{ ++ if (bus->hosttype == BCMA_HOSTTYPE_PCI) ++ return -ENOTSUPP; ++ return 0; ++} ++#endif ++ + extern bool bcma_core_is_enabled(struct bcma_device *core); + extern void bcma_core_disable(struct bcma_device *core, u32 flags); + extern int bcma_core_enable(struct bcma_device *core, u32 flags); +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -238,13 +238,13 @@ struct bcma_drv_pci { + #define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val) + #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val) + +-extern void bcma_core_pci_early_init(struct bcma_drv_pci *pc); +-extern void bcma_core_pci_init(struct bcma_drv_pci *pc); +-extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, +- struct bcma_device *core, bool enable); +-extern void bcma_core_pci_up(struct bcma_bus *bus); +-extern void bcma_core_pci_down(struct bcma_bus *bus); ++#ifdef CONFIG_BCMA_DRIVER_PCI + extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up); ++#else ++static inline void bcma_core_pci_power_save(struct bcma_bus *bus, bool up) ++{ ++} ++#endif + + extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); + extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); +--- a/include/linux/bcma/bcma_driver_pcie2.h ++++ b/include/linux/bcma/bcma_driver_pcie2.h +@@ -143,6 +143,8 @@ + + struct bcma_drv_pcie2 { + struct bcma_device *core; ++ ++ u16 reqsize; + }; + + #define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset) +@@ -153,6 +155,4 @@ struct bcma_drv_pcie2 { + #define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set) + #define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask) + +-void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2); +- + #endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */ +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE + config BCMA_HOST_PCI + bool "Support for BCMA on PCI-host bus" + depends on BCMA_HOST_PCI_POSSIBLE ++ select BCMA_DRIVER_PCI + default y + + config BCMA_DRIVER_PCI_HOSTMODE +@@ -44,6 +45,22 @@ config BCMA_HOST_SOC + + If unsure, say N + ++config BCMA_DRIVER_PCI ++ bool "BCMA Broadcom PCI core driver" ++ depends on BCMA && PCI ++ default y ++ help ++ BCMA bus may have many versions of PCIe core. This driver ++ supports: ++ 1) PCIe core working in clientmode ++ 2) PCIe Gen 2 clientmode core ++ ++ In general PCIe (Gen 2) clientmode core is required on PCIe ++ hosted buses. It's responsible for initialization and basic ++ hardware management. ++ This driver is also prerequisite for a hostmode PCIe core ++ support. ++ + config BCMA_DRIVER_MIPS + bool "BCMA Broadcom MIPS core driver" + depends on BCMA && MIPS +--- a/drivers/bcma/Makefile ++++ b/drivers/bcma/Makefile +@@ -3,8 +3,8 @@ bcma-y += driver_chipcommon.o driver + bcma-y += driver_chipcommon_b.o + bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o + bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o +-bcma-y += driver_pci.o +-bcma-y += driver_pcie2.o ++bcma-$(CONFIG_BCMA_DRIVER_PCI) += driver_pci.o ++bcma-$(CONFIG_BCMA_DRIVER_PCI) += driver_pcie2.o + bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o + bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o + bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o +--- a/include/linux/bcma/bcma_driver_chipcommon.h ++++ b/include/linux/bcma/bcma_driver_chipcommon.h +@@ -663,14 +663,6 @@ struct bcma_drv_cc_b { + #define bcma_cc_maskset32(cc, offset, mask, set) \ + bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) + +-extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); +-extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); +- +-extern void bcma_chipco_suspend(struct bcma_drv_cc *cc); +-extern void bcma_chipco_resume(struct bcma_drv_cc *cc); +- +-void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); +- + extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); + + extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); +@@ -690,9 +682,6 @@ u32 bcma_chipco_gpio_pullup(struct bcma_ + u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); + + /* PMU support */ +-extern void bcma_pmu_init(struct bcma_drv_cc *cc); +-extern void bcma_pmu_early_init(struct bcma_drv_cc *cc); +- + extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, + u32 value); + extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, +--- a/include/linux/bcma/bcma_driver_gmac_cmn.h ++++ b/include/linux/bcma/bcma_driver_gmac_cmn.h +@@ -91,10 +91,4 @@ struct bcma_drv_gmac_cmn { + #define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val) + #define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val) + +-#ifdef CONFIG_BCMA_DRIVER_GMAC_CMN +-extern void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc); +-#else +-static inline void bcma_core_gmac_cmn_init(struct bcma_drv_gmac_cmn *gc) { } +-#endif +- + #endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */ +--- a/include/linux/bcma/bcma_driver_mips.h ++++ b/include/linux/bcma/bcma_driver_mips.h +@@ -39,21 +39,6 @@ struct bcma_drv_mips { + u8 early_setup_done:1; + }; + +-#ifdef CONFIG_BCMA_DRIVER_MIPS +-extern void bcma_core_mips_init(struct bcma_drv_mips *mcore); +-extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore); +- +-extern unsigned int bcma_core_mips_irq(struct bcma_device *dev); +-#else +-static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { } +-static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { } +- +-static inline unsigned int bcma_core_mips_irq(struct bcma_device *dev) +-{ +- return 0; +-} +-#endif +- + extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore); + + #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */ diff --git a/target/linux/generic/patches-4.0/021-ssb_sprom.patch b/target/linux/generic/patches-4.0/021-ssb_sprom.patch new file mode 100644 index 0000000..52d8080 --- /dev/null +++ b/target/linux/generic/patches-4.0/021-ssb_sprom.patch @@ -0,0 +1,32 @@ +--- a/include/linux/ssb/ssb.h ++++ b/include/linux/ssb/ssb.h +@@ -29,10 +29,13 @@ struct ssb_sprom { + u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */ + u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */ + u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */ ++ u8 et2mac[6] __aligned(sizeof(u16)); /* MAC address for extra Ethernet */ + u8 et0phyaddr; /* MII address for enet0 */ + u8 et1phyaddr; /* MII address for enet1 */ ++ u8 et2phyaddr; /* MII address for enet2 */ + u8 et0mdcport; /* MDIO for enet0 */ + u8 et1mdcport; /* MDIO for enet1 */ ++ u8 et2mdcport; /* MDIO for enet2 */ + u16 dev_id; /* Device ID overriding e.g. PCI ID */ + u16 board_rev; /* Board revision number from SPROM. */ + u16 board_num; /* Board number from SPROM. */ +@@ -88,11 +91,14 @@ struct ssb_sprom { + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */ + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */ + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */ ++ u32 boardflags; ++ u32 boardflags2; ++ u32 boardflags3; ++ /* TODO: Switch all drivers to new u32 fields and drop below ones */ + u16 boardflags_lo; /* Board flags (bits 0-15) */ + u16 boardflags_hi; /* Board flags (bits 16-31) */ + u16 boardflags2_lo; /* Board flags (bits 32-47) */ + u16 boardflags2_hi; /* Board flags (bits 48-63) */ +- /* TODO store board flags in a single u64 */ + + struct ssb_sprom_core_pwr_info core_pwr_info[4]; + diff --git a/target/linux/generic/patches-4.0/022-bcma-from-4.2.patch b/target/linux/generic/patches-4.0/022-bcma-from-4.2.patch new file mode 100644 index 0000000..ba3df18 --- /dev/null +++ b/target/linux/generic/patches-4.0/022-bcma-from-4.2.patch @@ -0,0 +1,86 @@ +--- a/drivers/bcma/driver_gpio.c ++++ b/drivers/bcma/driver_gpio.c +@@ -226,6 +226,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c + chip->of_node = cc->core->dev.of_node; + #endif + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4707: + case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: + chip->ngpio = 32; +@@ -235,16 +236,17 @@ int bcma_gpio_init(struct bcma_drv_cc *c + } + + /* +- * On MIPS we register GPIO devices (LEDs, buttons) using absolute GPIO +- * pin numbers. We don't have Device Tree there and we can't really use +- * relative (per chip) numbers. +- * So let's use predictable base for BCM47XX and "random" for all other. ++ * Register SoC GPIO devices with absolute GPIO pin base. ++ * On MIPS, we don't have Device Tree and we can't use relative (per chip) ++ * GPIO numbers. ++ * On some ARM devices, user space may want to access some system GPIO ++ * pins directly, which is easier to do with a predictable GPIO base. + */ +-#if IS_BUILTIN(CONFIG_BCM47XX) +- chip->base = bus->num * BCMA_GPIO_MAX_PINS; +-#else +- chip->base = -1; +-#endif ++ if (IS_BUILTIN(CONFIG_BCM47XX) || ++ cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) ++ chip->base = bus->num * BCMA_GPIO_MAX_PINS; ++ else ++ chip->base = -1; + + err = bcma_gpio_irq_domain_init(cc); + if (err) +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -29,12 +29,6 @@ config BCMA_HOST_PCI + select BCMA_DRIVER_PCI + default y + +-config BCMA_DRIVER_PCI_HOSTMODE +- bool "Driver for PCI core working in hostmode" +- depends on BCMA && MIPS && BCMA_HOST_PCI +- help +- PCI core hostmode operation (external PCI bus). +- + config BCMA_HOST_SOC + bool "Support for BCMA in a SoC" + depends on BCMA +@@ -61,6 +55,12 @@ config BCMA_DRIVER_PCI + This driver is also prerequisite for a hostmode PCIe core + support. + ++config BCMA_DRIVER_PCI_HOSTMODE ++ bool "Driver for PCI core working in hostmode" ++ depends on BCMA && MIPS && BCMA_DRIVER_PCI ++ help ++ PCI core hostmode operation (external PCI bus). ++ + config BCMA_DRIVER_MIPS + bool "BCMA Broadcom MIPS core driver" + depends on BCMA && MIPS +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -246,7 +246,18 @@ static inline void bcma_core_pci_power_s + } + #endif + ++#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE + extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); + extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); ++#else ++static inline int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) ++{ ++ return -ENOTSUPP; ++} ++static inline int bcma_core_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ return -ENOTSUPP; ++} ++#endif + + #endif /* LINUX_BCMA_DRIVER_PCI_H_ */ diff --git a/target/linux/generic/patches-4.0/050-backport_netfilter_rtcache.patch b/target/linux/generic/patches-4.0/050-backport_netfilter_rtcache.patch new file mode 100644 index 0000000..f4783fd --- /dev/null +++ b/target/linux/generic/patches-4.0/050-backport_netfilter_rtcache.patch @@ -0,0 +1,509 @@ +Subject: netfilter: conntrack: cache route for forwarded connections + +... to avoid per-packet FIB lookup if possible. + +The cached dst is re-used provided the input interface +is the same as that of the previous packet in the same direction. + +If not, the cached dst is invalidated. + +For ipv6 we also need to store sernum, else dst_check doesn't work, +pointed out by Eric Dumazet. + +This should speed up forwarding when conntrack is already in use +anyway, especially when using reverse path filtering -- active RPF +enforces two FIB lookups for each packet. + +Before the routing cache removal this didn't matter since RPF was performed +only when route cache didn't yield a result; but without route cache it +comes at higher price. + +Julian Anastasov suggested to add NETDEV_UNREGISTER handler to +avoid holding on to dsts of 'frozen' conntracks. + +Signed-off-by: Florian Westphal + +--- a/include/net/netfilter/nf_conntrack_extend.h ++++ b/include/net/netfilter/nf_conntrack_extend.h +@@ -30,6 +30,9 @@ enum nf_ct_ext_id { + #if IS_ENABLED(CONFIG_NETFILTER_SYNPROXY) + NF_CT_EXT_SYNPROXY, + #endif ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_RTCACHE) ++ NF_CT_EXT_RTCACHE, ++#endif + NF_CT_EXT_NUM, + }; + +@@ -43,6 +46,7 @@ enum nf_ct_ext_id { + #define NF_CT_EXT_TIMEOUT_TYPE struct nf_conn_timeout + #define NF_CT_EXT_LABELS_TYPE struct nf_conn_labels + #define NF_CT_EXT_SYNPROXY_TYPE struct nf_conn_synproxy ++#define NF_CT_EXT_RTCACHE_TYPE struct nf_conn_rtcache + + /* Extensions: optional stuff which isn't permanently in struct. */ + struct nf_ct_ext { +--- /dev/null ++++ b/include/net/netfilter/nf_conntrack_rtcache.h +@@ -0,0 +1,34 @@ ++#include ++#include ++#include ++ ++struct dst_entry; ++ ++struct nf_conn_dst_cache { ++ struct dst_entry *dst; ++ int iif; ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ u32 cookie; ++#endif ++ ++}; ++ ++struct nf_conn_rtcache { ++ struct nf_conn_dst_cache cached_dst[IP_CT_DIR_MAX]; ++}; ++ ++static inline ++struct nf_conn_rtcache *nf_ct_rtcache_find(const struct nf_conn *ct) ++{ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_RTCACHE) ++ return nf_ct_ext_find(ct, NF_CT_EXT_RTCACHE); ++#else ++ return NULL; ++#endif ++} ++ ++static inline int nf_conn_rtcache_iif_get(const struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ return rtc->cached_dst[dir].iif; ++} +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -106,6 +106,18 @@ config NF_CONNTRACK_EVENTS + + If unsure, say `N'. + ++config NF_CONNTRACK_RTCACHE ++ tristate "Cache route entries in conntrack objects" ++ depends on NETFILTER_ADVANCED ++ depends on NF_CONNTRACK ++ help ++ If this option is enabled, the connection tracking code will ++ cache routing information for each connection that is being ++ forwarded, at a cost of 32 bytes per conntrack object. ++ ++ To compile it as a module, choose M here. If unsure, say N. ++ The module will be called nf_conntrack_rtcache. ++ + config NF_CONNTRACK_TIMEOUT + bool 'Connection tracking timeout' + depends on NETFILTER_ADVANCED +--- a/net/netfilter/Makefile ++++ b/net/netfilter/Makefile +@@ -18,6 +18,9 @@ obj-$(CONFIG_NETFILTER_NETLINK_LOG) += n + # connection tracking + obj-$(CONFIG_NF_CONNTRACK) += nf_conntrack.o + ++# optional conntrack route cache extension ++obj-$(CONFIG_NF_CONNTRACK_RTCACHE) += nf_conntrack_rtcache.o ++ + # SCTP protocol connection tracking + obj-$(CONFIG_NF_CT_PROTO_DCCP) += nf_conntrack_proto_dccp.o + obj-$(CONFIG_NF_CT_PROTO_GRE) += nf_conntrack_proto_gre.o +--- /dev/null ++++ b/net/netfilter/nf_conntrack_rtcache.c +@@ -0,0 +1,391 @@ ++/* route cache for netfilter. ++ * ++ * (C) 2014 Red Hat GmbH ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++#include ++#endif ++ ++static void __nf_conn_rtcache_destroy(struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ struct dst_entry *dst = rtc->cached_dst[dir].dst; ++ ++ dst_release(dst); ++} ++ ++static void nf_conn_rtcache_destroy(struct nf_conn *ct) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ ++ if (!rtc) ++ return; ++ ++ __nf_conn_rtcache_destroy(rtc, IP_CT_DIR_ORIGINAL); ++ __nf_conn_rtcache_destroy(rtc, IP_CT_DIR_REPLY); ++} ++ ++static void nf_ct_rtcache_ext_add(struct nf_conn *ct) ++{ ++ struct nf_conn_rtcache *rtc; ++ ++ rtc = nf_ct_ext_add(ct, NF_CT_EXT_RTCACHE, GFP_ATOMIC); ++ if (rtc) { ++ rtc->cached_dst[IP_CT_DIR_ORIGINAL].iif = -1; ++ rtc->cached_dst[IP_CT_DIR_ORIGINAL].dst = NULL; ++ rtc->cached_dst[IP_CT_DIR_REPLY].iif = -1; ++ rtc->cached_dst[IP_CT_DIR_REPLY].dst = NULL; ++ } ++} ++ ++static struct nf_conn_rtcache *nf_ct_rtcache_find_usable(struct nf_conn *ct) ++{ ++ if (nf_ct_is_untracked(ct)) ++ return NULL; ++ return nf_ct_rtcache_find(ct); ++} ++ ++static struct dst_entry * ++nf_conn_rtcache_dst_get(const struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ return rtc->cached_dst[dir].dst; ++} ++ ++static u32 nf_rtcache_get_cookie(int pf, const struct dst_entry *dst) ++{ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ if (pf == NFPROTO_IPV6) { ++ const struct rt6_info *rt = (const struct rt6_info *)dst; ++ ++ if (rt->rt6i_node) ++ return (u32)rt->rt6i_node->fn_sernum; ++ } ++#endif ++ return 0; ++} ++ ++static void nf_conn_rtcache_dst_set(int pf, ++ struct nf_conn_rtcache *rtc, ++ struct dst_entry *dst, ++ enum ip_conntrack_dir dir, int iif) ++{ ++ if (rtc->cached_dst[dir].iif != iif) ++ rtc->cached_dst[dir].iif = iif; ++ ++ if (rtc->cached_dst[dir].dst != dst) { ++ struct dst_entry *old; ++ ++ dst_hold(dst); ++ ++ old = xchg(&rtc->cached_dst[dir].dst, dst); ++ dst_release(old); ++ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ if (pf == NFPROTO_IPV6) ++ rtc->cached_dst[dir].cookie = ++ nf_rtcache_get_cookie(pf, dst); ++#endif ++ } ++} ++ ++static void nf_conn_rtcache_dst_obsolete(struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ struct dst_entry *old; ++ ++ pr_debug("Invalidate iif %d for dir %d on cache %p\n", ++ rtc->cached_dst[dir].iif, dir, rtc); ++ ++ old = xchg(&rtc->cached_dst[dir].dst, NULL); ++ dst_release(old); ++ rtc->cached_dst[dir].iif = -1; ++} ++ ++static unsigned int nf_rtcache_in(const struct nf_hook_ops *ops, ++ struct sk_buff *skb, ++ const struct net_device *in, ++ const struct net_device *out, ++ int (*okfn)(struct sk_buff *)) ++{ ++ struct nf_conn_rtcache *rtc; ++ enum ip_conntrack_info ctinfo; ++ enum ip_conntrack_dir dir; ++ struct dst_entry *dst; ++ struct nf_conn *ct; ++ int iif; ++ u32 cookie; ++ ++ if (skb_dst(skb) || skb->sk) ++ return NF_ACCEPT; ++ ++ ct = nf_ct_get(skb, &ctinfo); ++ if (!ct) ++ return NF_ACCEPT; ++ ++ rtc = nf_ct_rtcache_find_usable(ct); ++ if (!rtc) ++ return NF_ACCEPT; ++ ++ /* if iif changes, don't use cache and let ip stack ++ * do route lookup. ++ * ++ * If rp_filter is enabled it might toss skb, so ++ * we don't want to avoid these checks. ++ */ ++ dir = CTINFO2DIR(ctinfo); ++ iif = nf_conn_rtcache_iif_get(rtc, dir); ++ if (in->ifindex != iif) { ++ pr_debug("ct %p, iif %d, cached iif %d, skip cached entry\n", ++ ct, iif, in->ifindex); ++ return NF_ACCEPT; ++ } ++ dst = nf_conn_rtcache_dst_get(rtc, dir); ++ if (dst == NULL) ++ return NF_ACCEPT; ++ ++ cookie = nf_rtcache_get_cookie(ops->pf, dst); ++ ++ dst = dst_check(dst, cookie); ++ pr_debug("obtained dst %p for skb %p, cookie %d\n", dst, skb, cookie); ++ if (likely(dst)) ++ skb_dst_set_noref(skb, dst); ++ else ++ nf_conn_rtcache_dst_obsolete(rtc, dir); ++ ++ return NF_ACCEPT; ++} ++ ++static unsigned int nf_rtcache_forward(const struct nf_hook_ops *ops, ++ struct sk_buff *skb, ++ const struct net_device *in, ++ const struct net_device *out, ++ int (*okfn)(struct sk_buff *)) ++{ ++ struct nf_conn_rtcache *rtc; ++ enum ip_conntrack_info ctinfo; ++ enum ip_conntrack_dir dir; ++ struct nf_conn *ct; ++ struct dst_entry *dst = skb_dst(skb); ++ int iif; ++ ++ ct = nf_ct_get(skb, &ctinfo); ++ if (!ct) ++ return NF_ACCEPT; ++ ++ if (dst && dst_xfrm(dst)) ++ return NF_ACCEPT; ++ ++ if (!nf_ct_is_confirmed(ct)) { ++ if (WARN_ON(nf_ct_rtcache_find(ct))) ++ return NF_ACCEPT; ++ nf_ct_rtcache_ext_add(ct); ++ return NF_ACCEPT; ++ } ++ ++ rtc = nf_ct_rtcache_find_usable(ct); ++ if (!rtc) ++ return NF_ACCEPT; ++ ++ dir = CTINFO2DIR(ctinfo); ++ iif = nf_conn_rtcache_iif_get(rtc, dir); ++ pr_debug("ct %p, skb %p, dir %d, iif %d, cached iif %d\n", ++ ct, skb, dir, iif, in->ifindex); ++ if (likely(in->ifindex == iif)) ++ return NF_ACCEPT; ++ ++ nf_conn_rtcache_dst_set(ops->pf, rtc, skb_dst(skb), dir, in->ifindex); ++ return NF_ACCEPT; ++} ++ ++static int nf_rtcache_dst_remove(struct nf_conn *ct, void *data) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ struct net_device *dev = data; ++ ++ if (!rtc) ++ return 0; ++ ++ if (dev->ifindex == rtc->cached_dst[IP_CT_DIR_ORIGINAL].iif || ++ dev->ifindex == rtc->cached_dst[IP_CT_DIR_REPLY].iif) { ++ nf_conn_rtcache_dst_obsolete(rtc, IP_CT_DIR_ORIGINAL); ++ nf_conn_rtcache_dst_obsolete(rtc, IP_CT_DIR_REPLY); ++ } ++ ++ return 0; ++} ++ ++static int nf_rtcache_netdev_event(struct notifier_block *this, ++ unsigned long event, void *ptr) ++{ ++ struct net_device *dev = netdev_notifier_info_to_dev(ptr); ++ struct net *net = dev_net(dev); ++ ++ if (event == NETDEV_DOWN) ++ nf_ct_iterate_cleanup(net, nf_rtcache_dst_remove, dev, 0, 0); ++ ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block nf_rtcache_notifier = { ++ .notifier_call = nf_rtcache_netdev_event, ++}; ++ ++static struct nf_hook_ops rtcache_ops[] = { ++ { ++ .hook = nf_rtcache_in, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV4, ++ .hooknum = NF_INET_PRE_ROUTING, ++ .priority = NF_IP_PRI_LAST, ++ }, ++ { ++ .hook = nf_rtcache_forward, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV4, ++ .hooknum = NF_INET_FORWARD, ++ .priority = NF_IP_PRI_LAST, ++ }, ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ { ++ .hook = nf_rtcache_in, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV6, ++ .hooknum = NF_INET_PRE_ROUTING, ++ .priority = NF_IP_PRI_LAST, ++ }, ++ { ++ .hook = nf_rtcache_forward, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV6, ++ .hooknum = NF_INET_FORWARD, ++ .priority = NF_IP_PRI_LAST, ++ }, ++#endif ++}; ++ ++static struct nf_ct_ext_type rtcache_extend __read_mostly = { ++ .len = sizeof(struct nf_conn_rtcache), ++ .align = __alignof__(struct nf_conn_rtcache), ++ .id = NF_CT_EXT_RTCACHE, ++ .destroy = nf_conn_rtcache_destroy, ++}; ++ ++static int __init nf_conntrack_rtcache_init(void) ++{ ++ int ret = nf_ct_extend_register(&rtcache_extend); ++ ++ if (ret < 0) { ++ pr_err("nf_conntrack_rtcache: Unable to register extension\n"); ++ return ret; ++ } ++ ++ ret = nf_register_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ if (ret < 0) { ++ nf_ct_extend_unregister(&rtcache_extend); ++ return ret; ++ } ++ ++ ret = register_netdevice_notifier(&nf_rtcache_notifier); ++ if (ret) { ++ nf_unregister_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ nf_ct_extend_unregister(&rtcache_extend); ++ } ++ ++ return ret; ++} ++ ++static int nf_rtcache_ext_remove(struct nf_conn *ct, void *data) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ ++ return rtc != NULL; ++} ++ ++static bool __exit nf_conntrack_rtcache_wait_for_dying(struct net *net) ++{ ++ bool wait = false; ++ int cpu; ++ ++ for_each_possible_cpu(cpu) { ++ struct nf_conntrack_tuple_hash *h; ++ struct hlist_nulls_node *n; ++ struct nf_conn *ct; ++ struct ct_pcpu *pcpu = per_cpu_ptr(net->ct.pcpu_lists, cpu); ++ ++ rcu_read_lock(); ++ spin_lock_bh(&pcpu->lock); ++ ++ hlist_nulls_for_each_entry(h, n, &pcpu->dying, hnnode) { ++ ct = nf_ct_tuplehash_to_ctrack(h); ++ if (nf_ct_rtcache_find(ct) != NULL) { ++ wait = true; ++ break; ++ } ++ } ++ spin_unlock_bh(&pcpu->lock); ++ rcu_read_unlock(); ++ } ++ ++ return wait; ++} ++ ++static void __exit nf_conntrack_rtcache_fini(void) ++{ ++ struct net *net; ++ int count = 0; ++ ++ /* remove hooks so no new connections get rtcache extension */ ++ nf_unregister_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ ++ synchronize_net(); ++ ++ unregister_netdevice_notifier(&nf_rtcache_notifier); ++ ++ rtnl_lock(); ++ ++ /* zap all conntracks with rtcache extension */ ++ for_each_net(net) ++ nf_ct_iterate_cleanup(net, nf_rtcache_ext_remove, NULL, 0, 0); ++ ++ for_each_net(net) { ++ /* .. and make sure they're gone from dying list, too */ ++ while (nf_conntrack_rtcache_wait_for_dying(net)) { ++ msleep(200); ++ WARN_ONCE(++count > 25, "Waiting for all rtcache conntracks to go away\n"); ++ } ++ } ++ ++ rtnl_unlock(); ++ synchronize_net(); ++ nf_ct_extend_unregister(&rtcache_extend); ++} ++module_init(nf_conntrack_rtcache_init); ++module_exit(nf_conntrack_rtcache_fini); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Florian Westphal "); ++MODULE_DESCRIPTION("Conntrack route cache extension"); diff --git a/target/linux/generic/patches-4.0/060-mips_decompressor_memmove.patch b/target/linux/generic/patches-4.0/060-mips_decompressor_memmove.patch new file mode 100644 index 0000000..d215b80 --- /dev/null +++ b/target/linux/generic/patches-4.0/060-mips_decompressor_memmove.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/boot/compressed/string.c ++++ b/arch/mips/boot/compressed/string.c +@@ -26,3 +26,19 @@ void *memset(void *s, int c, size_t n) + ss[i] = c; + return s; + } ++ ++void *memmove(void *__dest, __const void *__src, size_t count) ++{ ++ unsigned char *d = __dest; ++ const unsigned char *s = __src; ++ ++ if (__dest == __src) ++ return __dest; ++ ++ if (__dest < __src) ++ return memcpy(__dest, __src, count); ++ ++ while (count--) ++ d[count] = s[count]; ++ return __dest; ++} diff --git a/target/linux/generic/patches-4.0/070-bgmac-register-fixed-PHY-for-ARM-BCM470X-BCM5301X-ch.patch b/target/linux/generic/patches-4.0/070-bgmac-register-fixed-PHY-for-ARM-BCM470X-BCM5301X-ch.patch new file mode 100644 index 0000000..9f0baff --- /dev/null +++ b/target/linux/generic/patches-4.0/070-bgmac-register-fixed-PHY-for-ARM-BCM470X-BCM5301X-ch.patch @@ -0,0 +1,76 @@ +From c25b23b8a387e7d31f7a74af8e37b61e9e6ebb21 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 20 Mar 2015 23:14:31 +0100 +Subject: [PATCH] bgmac: register fixed PHY for ARM BCM470X / BCM5301X chipsets +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +On ARM SoCs with bgmac Ethernet hardware we don't have any normal PHY. +There is always a switch attached but it's not even controlled over MDIO +like in case of MIPS devices. +We need a fixed PHY to be able to send/receive packets from the switch. + +Signed-off-by: Rafał Miłecki +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/bgmac.c | 34 ++++++++++++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -1330,13 +1331,46 @@ static void bgmac_adjust_link(struct net + } + } + ++static int bgmac_fixed_phy_register(struct bgmac *bgmac) ++{ ++ struct fixed_phy_status fphy_status = { ++ .link = 1, ++ .speed = SPEED_1000, ++ .duplex = DUPLEX_FULL, ++ }; ++ struct phy_device *phy_dev; ++ int err; ++ ++ phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); ++ if (!phy_dev || IS_ERR(phy_dev)) { ++ bgmac_err(bgmac, "Failed to register fixed PHY device\n"); ++ return -ENODEV; ++ } ++ ++ err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, ++ PHY_INTERFACE_MODE_MII); ++ if (err) { ++ bgmac_err(bgmac, "Connecting PHY failed\n"); ++ return err; ++ } ++ ++ bgmac->phy_dev = phy_dev; ++ ++ return err; ++} ++ + static int bgmac_mii_register(struct bgmac *bgmac) + { ++ struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo; + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + char bus_id[MII_BUS_ID_SIZE + 3]; + int i, err = 0; + ++ if (ci->id == BCMA_CHIP_ID_BCM4707 || ++ ci->id == BCMA_CHIP_ID_BCM53018) ++ return bgmac_fixed_phy_register(bgmac); ++ + mii_bus = mdiobus_alloc(); + if (!mii_bus) + return -ENOMEM; diff --git a/target/linux/generic/patches-4.0/071-bgmac-allow-enabling-on-ARCH_BCM_5301X.patch b/target/linux/generic/patches-4.0/071-bgmac-allow-enabling-on-ARCH_BCM_5301X.patch new file mode 100644 index 0000000..3c5b79d --- /dev/null +++ b/target/linux/generic/patches-4.0/071-bgmac-allow-enabling-on-ARCH_BCM_5301X.patch @@ -0,0 +1,28 @@ +From fc300dc3733fdc328e6e10c7b8379b60c26cd648 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Fri, 20 Mar 2015 23:14:32 +0100 +Subject: [PATCH] bgmac: allow enabling on ARCH_BCM_5301X +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Home routers based on ARM SoCs like BCM4708 also have bcma bus with core +supported by bgmac. + +Signed-off-by: Rafał Miłecki +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/broadcom/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/broadcom/Kconfig ++++ b/drivers/net/ethernet/broadcom/Kconfig +@@ -142,7 +142,7 @@ config BNX2X_SRIOV + + config BGMAC + tristate "BCMA bus GBit core support" +- depends on BCMA_HOST_SOC && HAS_DMA && BCM47XX ++ depends on BCMA_HOST_SOC && HAS_DMA && (BCM47XX || ARCH_BCM_5301X) + select PHYLIB + ---help--- + This driver supports GBit MAC and BCM4706 GBit MAC cores on BCMA bus. diff --git a/target/linux/generic/patches-4.0/072-01-bgmac-fix-descriptor-frame-start-end-definitions.patch b/target/linux/generic/patches-4.0/072-01-bgmac-fix-descriptor-frame-start-end-definitions.patch new file mode 100644 index 0000000..fdfae3a --- /dev/null +++ b/target/linux/generic/patches-4.0/072-01-bgmac-fix-descriptor-frame-start-end-definitions.patch @@ -0,0 +1,24 @@ +From: Felix Fietkau +Date: Mon, 23 Mar 2015 02:40:06 +0100 +Subject: [PATCH] bgmac: fix descriptor frame start/end definitions + +The start-of-frame and end-of-frame bits were accidentally swapped. +In the current code it does not make any difference, since they are +always used together. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -345,8 +345,8 @@ + + #define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */ + #define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */ +-#define BGMAC_DESC_CTL0_SOF 0x40000000 /* Start of frame */ +-#define BGMAC_DESC_CTL0_EOF 0x80000000 /* End of frame */ ++#define BGMAC_DESC_CTL0_EOF 0x40000000 /* End of frame */ ++#define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */ + #define BGMAC_DESC_CTL1_LEN 0x00001FFF + + #define BGMAC_PHY_NOREGS 0x1E diff --git a/target/linux/generic/patches-4.0/072-02-bgmac-implement-GRO-and-use-build_skb.patch b/target/linux/generic/patches-4.0/072-02-bgmac-implement-GRO-and-use-build_skb.patch new file mode 100644 index 0000000..2a2df60 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-02-bgmac-implement-GRO-and-use-build_skb.patch @@ -0,0 +1,189 @@ +From: Felix Fietkau +Date: Mon, 23 Mar 2015 02:41:25 +0100 +Subject: [PATCH] bgmac: implement GRO and use build_skb + +This improves performance for routing and local rx + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -276,31 +276,31 @@ static int bgmac_dma_rx_skb_for_slot(str + struct bgmac_slot_info *slot) + { + struct device *dma_dev = bgmac->core->dma_dev; +- struct sk_buff *skb; + dma_addr_t dma_addr; + struct bgmac_rx_header *rx; ++ void *buf; + + /* Alloc skb */ +- skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE); +- if (!skb) ++ buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); ++ if (!buf) + return -ENOMEM; + + /* Poison - if everything goes fine, hardware will overwrite it */ +- rx = (struct bgmac_rx_header *)skb->data; ++ rx = buf; + rx->len = cpu_to_le16(0xdead); + rx->flags = cpu_to_le16(0xbeef); + + /* Map skb for the DMA */ +- dma_addr = dma_map_single(dma_dev, skb->data, +- BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); ++ dma_addr = dma_map_single(dma_dev, buf, BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); + if (dma_mapping_error(dma_dev, dma_addr)) { + bgmac_err(bgmac, "DMA mapping error\n"); +- dev_kfree_skb(skb); ++ put_page(virt_to_head_page(buf)); + return -ENOMEM; + } + + /* Update the slot */ +- slot->skb = skb; ++ slot->buf = buf; + slot->dma_addr = dma_addr; + + return 0; +@@ -343,8 +343,9 @@ static int bgmac_dma_rx_read(struct bgma + while (ring->start != ring->end) { + struct device *dma_dev = bgmac->core->dma_dev; + struct bgmac_slot_info *slot = &ring->slots[ring->start]; +- struct sk_buff *skb = slot->skb; +- struct bgmac_rx_header *rx; ++ struct bgmac_rx_header *rx = slot->buf; ++ struct sk_buff *skb; ++ void *buf = slot->buf; + u16 len, flags; + + /* Unmap buffer to make it accessible to the CPU */ +@@ -352,7 +353,6 @@ static int bgmac_dma_rx_read(struct bgma + BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); + + /* Get info from the header */ +- rx = (struct bgmac_rx_header *)skb->data; + len = le16_to_cpu(rx->len); + flags = le16_to_cpu(rx->flags); + +@@ -393,12 +393,13 @@ static int bgmac_dma_rx_read(struct bgma + dma_unmap_single(dma_dev, old_dma_addr, + BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); + ++ skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); + skb_put(skb, BGMAC_RX_FRAME_OFFSET + len); + skb_pull(skb, BGMAC_RX_FRAME_OFFSET); + + skb_checksum_none_assert(skb); + skb->protocol = eth_type_trans(skb, bgmac->net_dev); +- netif_receive_skb(skb); ++ napi_gro_receive(&bgmac->napi, skb); + handled++; + } while (0); + +@@ -434,12 +435,11 @@ static bool bgmac_dma_unaligned(struct b + return false; + } + +-static void bgmac_dma_ring_free(struct bgmac *bgmac, +- struct bgmac_dma_ring *ring) ++static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) + { + struct device *dma_dev = bgmac->core->dma_dev; + struct bgmac_slot_info *slot; +- int size; + int i; + + for (i = 0; i < ring->num_slots; i++) { +@@ -451,23 +451,55 @@ static void bgmac_dma_ring_free(struct b + dev_kfree_skb(slot->skb); + } + } ++} ++ ++static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_slot_info *slot; ++ int i; ++ ++ for (i = 0; i < ring->num_slots; i++) { ++ slot = &ring->slots[i]; ++ if (!slot->buf) ++ continue; + +- if (ring->cpu_base) { +- /* Free ring of descriptors */ +- size = ring->num_slots * sizeof(struct bgmac_dma_desc); +- dma_free_coherent(dma_dev, size, ring->cpu_base, +- ring->dma_base); ++ if (slot->dma_addr) ++ dma_unmap_single(dma_dev, slot->dma_addr, ++ BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++ put_page(virt_to_head_page(slot->buf)); + } + } + ++static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ struct device *dma_dev = bgmac->core->dma_dev; ++ int size; ++ ++ if (!ring->cpu_base) ++ return; ++ ++ /* Free ring of descriptors */ ++ size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ dma_free_coherent(dma_dev, size, ring->cpu_base, ++ ring->dma_base); ++} ++ + static void bgmac_dma_free(struct bgmac *bgmac) + { + int i; + +- for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) +- bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]); +- for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) +- bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]); ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { ++ bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); ++ } ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { ++ bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); ++ } + } + + static int bgmac_dma_alloc(struct bgmac *bgmac) +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -362,6 +362,8 @@ + #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ + #define BGMAC_RX_MAX_FRAME_SIZE 1536 /* Copied from b44/tg3 */ + #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) ++#define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE) + \ ++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) + + #define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */ + #define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */ +@@ -383,7 +385,10 @@ + #define ETHER_MAX_LEN 1518 + + struct bgmac_slot_info { +- struct sk_buff *skb; ++ union { ++ struct sk_buff *skb; ++ void *buf; ++ }; + dma_addr_t dma_addr; + }; + diff --git a/target/linux/generic/patches-4.0/072-03-bgmac-implement-scatter-gather-support.patch b/target/linux/generic/patches-4.0/072-03-bgmac-implement-scatter-gather-support.patch new file mode 100644 index 0000000..5cb21a5 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-03-bgmac-implement-scatter-gather-support.patch @@ -0,0 +1,267 @@ +From: Felix Fietkau +Date: Mon, 23 Mar 2015 02:42:26 +0100 +Subject: [PATCH] bgmac: implement scatter/gather support + +Always use software checksumming, since the hardware does not have any +checksum offload support. +This significantly improves local TCP tx performance. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -115,53 +115,91 @@ static void bgmac_dma_tx_enable(struct b + bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); + } + ++static void ++bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, ++ int i, int len, u32 ctl0) ++{ ++ struct bgmac_slot_info *slot; ++ struct bgmac_dma_desc *dma_desc; ++ u32 ctl1; ++ ++ if (i == ring->num_slots - 1) ++ ctl0 |= BGMAC_DESC_CTL0_EOT; ++ ++ ctl1 = len & BGMAC_DESC_CTL1_LEN; ++ ++ slot = &ring->slots[i]; ++ dma_desc = &ring->cpu_base[i]; ++ dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); ++ dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); ++ dma_desc->ctl0 = cpu_to_le32(ctl0); ++ dma_desc->ctl1 = cpu_to_le32(ctl1); ++} ++ + static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, + struct bgmac_dma_ring *ring, + struct sk_buff *skb) + { + struct device *dma_dev = bgmac->core->dma_dev; + struct net_device *net_dev = bgmac->net_dev; +- struct bgmac_dma_desc *dma_desc; +- struct bgmac_slot_info *slot; +- u32 ctl0, ctl1; ++ struct bgmac_slot_info *slot = &ring->slots[ring->end]; + int free_slots; ++ int nr_frags; ++ u32 flags; ++ int index = ring->end; ++ int i; + + if (skb->len > BGMAC_DESC_CTL1_LEN) { + bgmac_err(bgmac, "Too long skb (%d)\n", skb->len); +- goto err_stop_drop; ++ goto err_drop; + } + ++ if (skb->ip_summed == CHECKSUM_PARTIAL) ++ skb_checksum_help(skb); ++ ++ nr_frags = skb_shinfo(skb)->nr_frags; ++ + if (ring->start <= ring->end) + free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS; + else + free_slots = ring->start - ring->end; +- if (free_slots == 1) { ++ ++ if (free_slots <= nr_frags + 1) { + bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); + netif_stop_queue(net_dev); + return NETDEV_TX_BUSY; + } + +- slot = &ring->slots[ring->end]; +- slot->skb = skb; +- slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len, ++ slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), + DMA_TO_DEVICE); +- if (dma_mapping_error(dma_dev, slot->dma_addr)) { +- bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", +- ring->mmio_base); +- goto err_stop_drop; +- } ++ if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) ++ goto err_dma_head; + +- ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF; +- if (ring->end == ring->num_slots - 1) +- ctl0 |= BGMAC_DESC_CTL0_EOT; +- ctl1 = skb->len & BGMAC_DESC_CTL1_LEN; ++ flags = BGMAC_DESC_CTL0_SOF; ++ if (!nr_frags) ++ flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; ++ ++ bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); ++ flags = 0; ++ ++ for (i = 0; i < nr_frags; i++) { ++ struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; ++ int len = skb_frag_size(frag); ++ ++ index = (index + 1) % BGMAC_TX_RING_SLOTS; ++ slot = &ring->slots[index]; ++ slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, ++ len, DMA_TO_DEVICE); ++ if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) ++ goto err_dma; + +- dma_desc = ring->cpu_base; +- dma_desc += ring->end; +- dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); +- dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); +- dma_desc->ctl0 = cpu_to_le32(ctl0); +- dma_desc->ctl1 = cpu_to_le32(ctl1); ++ if (i == nr_frags - 1) ++ flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; ++ ++ bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); ++ } ++ ++ slot->skb = skb; + + netdev_sent_queue(net_dev, skb->len); + +@@ -170,20 +208,35 @@ static netdev_tx_t bgmac_dma_tx_add(stru + /* Increase ring->end to point empty slot. We tell hardware the first + * slot it should *not* read. + */ +- if (++ring->end >= BGMAC_TX_RING_SLOTS) +- ring->end = 0; ++ ring->end = (index + 1) % BGMAC_TX_RING_SLOTS; + bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, + ring->index_base + + ring->end * sizeof(struct bgmac_dma_desc)); + +- /* Always keep one slot free to allow detecting bugged calls. */ +- if (--free_slots == 1) ++ free_slots -= nr_frags + 1; ++ if (free_slots < 8) + netif_stop_queue(net_dev); + + return NETDEV_TX_OK; + +-err_stop_drop: +- netif_stop_queue(net_dev); ++err_dma: ++ dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), ++ DMA_TO_DEVICE); ++ ++ while (i > 0) { ++ int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; ++ struct bgmac_slot_info *slot = &ring->slots[index]; ++ u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); ++ int len = ctl1 & BGMAC_DESC_CTL1_LEN; ++ ++ dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); ++ } ++ ++err_dma_head: ++ bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n", ++ ring->mmio_base); ++ ++err_drop: + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } +@@ -205,32 +258,45 @@ static void bgmac_dma_tx_free(struct bgm + + while (ring->start != empty_slot) { + struct bgmac_slot_info *slot = &ring->slots[ring->start]; ++ u32 ctl1 = le32_to_cpu(ring->cpu_base[ring->start].ctl1); ++ int len = ctl1 & BGMAC_DESC_CTL1_LEN; + +- if (slot->skb) { ++ if (!slot->dma_addr) { ++ bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", ++ ring->start, ring->end); ++ goto next; ++ } ++ ++ if (ctl1 & BGMAC_DESC_CTL0_SOF) + /* Unmap no longer used buffer */ +- dma_unmap_single(dma_dev, slot->dma_addr, +- slot->skb->len, DMA_TO_DEVICE); +- slot->dma_addr = 0; ++ dma_unmap_single(dma_dev, slot->dma_addr, len, ++ DMA_TO_DEVICE); ++ else ++ dma_unmap_page(dma_dev, slot->dma_addr, len, ++ DMA_TO_DEVICE); + ++ if (slot->skb) { + bytes_compl += slot->skb->len; + pkts_compl++; + + /* Free memory! :) */ + dev_kfree_skb(slot->skb); + slot->skb = NULL; +- } else { +- bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", +- ring->start, ring->end); + } + ++next: ++ slot->dma_addr = 0; + if (++ring->start >= BGMAC_TX_RING_SLOTS) + ring->start = 0; + freed = true; + } + ++ if (!pkts_compl) ++ return; ++ + netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); + +- if (freed && netif_queue_stopped(bgmac->net_dev)) ++ if (netif_queue_stopped(bgmac->net_dev)) + netif_wake_queue(bgmac->net_dev); + } + +@@ -439,17 +505,25 @@ static void bgmac_dma_tx_ring_free(struc + struct bgmac_dma_ring *ring) + { + struct device *dma_dev = bgmac->core->dma_dev; ++ struct bgmac_dma_desc *dma_desc = ring->cpu_base; + struct bgmac_slot_info *slot; + int i; + + for (i = 0; i < ring->num_slots; i++) { ++ int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; ++ + slot = &ring->slots[i]; +- if (slot->skb) { +- if (slot->dma_addr) +- dma_unmap_single(dma_dev, slot->dma_addr, +- slot->skb->len, DMA_TO_DEVICE); +- dev_kfree_skb(slot->skb); +- } ++ dev_kfree_skb(slot->skb); ++ ++ if (!slot->dma_addr) ++ continue; ++ ++ if (slot->skb) ++ dma_unmap_single(dma_dev, slot->dma_addr, ++ len, DMA_TO_DEVICE); ++ else ++ dma_unmap_page(dma_dev, slot->dma_addr, ++ len, DMA_TO_DEVICE); + } + } + +@@ -1583,6 +1657,10 @@ static int bgmac_probe(struct bcma_devic + goto err_dma_free; + } + ++ net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; ++ net_dev->hw_features = net_dev->features; ++ net_dev->vlan_features = net_dev->features; ++ + err = register_netdev(bgmac->net_dev); + if (err) { + bgmac_err(bgmac, "Cannot register net device\n"); diff --git a/target/linux/generic/patches-4.0/072-04-bgmac-simplify-tx-ring-index-handling.patch b/target/linux/generic/patches-4.0/072-04-bgmac-simplify-tx-ring-index-handling.patch new file mode 100644 index 0000000..241a308 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-04-bgmac-simplify-tx-ring-index-handling.patch @@ -0,0 +1,125 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 09:58:56 +0200 +Subject: [PATCH] bgmac: simplify tx ring index handling + +Keep incrementing ring->start and ring->end instead of pointing it to +the actual ring slot entry. This simplifies the calculation of the +number of free slots. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -142,11 +142,10 @@ static netdev_tx_t bgmac_dma_tx_add(stru + { + struct device *dma_dev = bgmac->core->dma_dev; + struct net_device *net_dev = bgmac->net_dev; +- struct bgmac_slot_info *slot = &ring->slots[ring->end]; +- int free_slots; ++ int index = ring->end % BGMAC_TX_RING_SLOTS; ++ struct bgmac_slot_info *slot = &ring->slots[index]; + int nr_frags; + u32 flags; +- int index = ring->end; + int i; + + if (skb->len > BGMAC_DESC_CTL1_LEN) { +@@ -159,12 +158,10 @@ static netdev_tx_t bgmac_dma_tx_add(stru + + nr_frags = skb_shinfo(skb)->nr_frags; + +- if (ring->start <= ring->end) +- free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS; +- else +- free_slots = ring->start - ring->end; +- +- if (free_slots <= nr_frags + 1) { ++ /* ring->end - ring->start will return the number of valid slots, ++ * even when ring->end overflows ++ */ ++ if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { + bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n"); + netif_stop_queue(net_dev); + return NETDEV_TX_BUSY; +@@ -200,7 +197,7 @@ static netdev_tx_t bgmac_dma_tx_add(stru + } + + slot->skb = skb; +- ++ ring->end += nr_frags + 1; + netdev_sent_queue(net_dev, skb->len); + + wmb(); +@@ -208,13 +205,12 @@ static netdev_tx_t bgmac_dma_tx_add(stru + /* Increase ring->end to point empty slot. We tell hardware the first + * slot it should *not* read. + */ +- ring->end = (index + 1) % BGMAC_TX_RING_SLOTS; + bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, + ring->index_base + +- ring->end * sizeof(struct bgmac_dma_desc)); ++ (ring->end % BGMAC_TX_RING_SLOTS) * ++ sizeof(struct bgmac_dma_desc)); + +- free_slots -= nr_frags + 1; +- if (free_slots < 8) ++ if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) + netif_stop_queue(net_dev); + + return NETDEV_TX_OK; +@@ -256,17 +252,17 @@ static void bgmac_dma_tx_free(struct bgm + empty_slot &= BGMAC_DMA_TX_STATDPTR; + empty_slot /= sizeof(struct bgmac_dma_desc); + +- while (ring->start != empty_slot) { +- struct bgmac_slot_info *slot = &ring->slots[ring->start]; +- u32 ctl1 = le32_to_cpu(ring->cpu_base[ring->start].ctl1); +- int len = ctl1 & BGMAC_DESC_CTL1_LEN; ++ while (ring->start != ring->end) { ++ int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; ++ struct bgmac_slot_info *slot = &ring->slots[slot_idx]; ++ u32 ctl1; ++ int len; + +- if (!slot->dma_addr) { +- bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n", +- ring->start, ring->end); +- goto next; +- } ++ if (slot_idx == empty_slot) ++ break; + ++ ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); ++ len = ctl1 & BGMAC_DESC_CTL1_LEN; + if (ctl1 & BGMAC_DESC_CTL0_SOF) + /* Unmap no longer used buffer */ + dma_unmap_single(dma_dev, slot->dma_addr, len, +@@ -284,10 +280,8 @@ static void bgmac_dma_tx_free(struct bgm + slot->skb = NULL; + } + +-next: + slot->dma_addr = 0; +- if (++ring->start >= BGMAC_TX_RING_SLOTS) +- ring->start = 0; ++ ring->start++; + freed = true; + } + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -414,10 +414,10 @@ enum bgmac_dma_ring_type { + * empty. + */ + struct bgmac_dma_ring { +- u16 num_slots; +- u16 start; +- u16 end; ++ u32 start; ++ u32 end; + ++ u16 num_slots; + u16 mmio_base; + struct bgmac_dma_desc *cpu_base; + dma_addr_t dma_base; diff --git a/target/linux/generic/patches-4.0/072-05-bgmac-leave-interrupts-disabled-as-long-as-there-is-.patch b/target/linux/generic/patches-4.0/072-05-bgmac-leave-interrupts-disabled-as-long-as-there-is-.patch new file mode 100644 index 0000000..3bbe9ea --- /dev/null +++ b/target/linux/generic/patches-4.0/072-05-bgmac-leave-interrupts-disabled-as-long-as-there-is-.patch @@ -0,0 +1,87 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 10:08:04 +0200 +Subject: [PATCH] bgmac: leave interrupts disabled as long as there is work + to do + +Always poll rx and tx during NAPI poll instead of relying on the status +of the first interrupt. This prevents bgmac_poll from leaving unfinished +work around until the next IRQ. +In my tests this makes bridging/routing throughput under heavy load more +stable and ensures that no new IRQs arrive as long as bgmac_poll uses up +the entire budget. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1109,8 +1109,6 @@ static void bgmac_chip_reset(struct bgma + bgmac_phy_init(bgmac); + + netdev_reset_queue(bgmac->net_dev); +- +- bgmac->int_status = 0; + } + + static void bgmac_chip_intrs_on(struct bgmac *bgmac) +@@ -1225,14 +1223,13 @@ static irqreturn_t bgmac_interrupt(int i + if (!int_status) + return IRQ_NONE; + +- /* Ack */ +- bgmac_write(bgmac, BGMAC_INT_STATUS, int_status); ++ int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); ++ if (int_status) ++ bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status); + + /* Disable new interrupts until handling existing ones */ + bgmac_chip_intrs_off(bgmac); + +- bgmac->int_status = int_status; +- + napi_schedule(&bgmac->napi); + + return IRQ_HANDLED; +@@ -1241,25 +1238,17 @@ static irqreturn_t bgmac_interrupt(int i + static int bgmac_poll(struct napi_struct *napi, int weight) + { + struct bgmac *bgmac = container_of(napi, struct bgmac, napi); +- struct bgmac_dma_ring *ring; + int handled = 0; + +- if (bgmac->int_status & BGMAC_IS_TX0) { +- ring = &bgmac->tx_ring[0]; +- bgmac_dma_tx_free(bgmac, ring); +- bgmac->int_status &= ~BGMAC_IS_TX0; +- } ++ /* Ack */ ++ bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); + +- if (bgmac->int_status & BGMAC_IS_RX) { +- ring = &bgmac->rx_ring[0]; +- handled += bgmac_dma_rx_read(bgmac, ring, weight); +- bgmac->int_status &= ~BGMAC_IS_RX; +- } ++ bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); ++ handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); + +- if (bgmac->int_status) { +- bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status); +- bgmac->int_status = 0; +- } ++ /* Poll again if more events arrived in the meantime */ ++ if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) ++ return handled; + + if (handled < weight) { + napi_complete(napi); +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -452,7 +452,6 @@ struct bgmac { + + /* Int */ + u32 int_mask; +- u32 int_status; + + /* Current MAC state */ + int mac_speed; diff --git a/target/linux/generic/patches-4.0/072-06-bgmac-set-received-skb-headroom-to-NET_SKB_PAD.patch b/target/linux/generic/patches-4.0/072-06-bgmac-set-received-skb-headroom-to-NET_SKB_PAD.patch new file mode 100644 index 0000000..2c490ef --- /dev/null +++ b/target/linux/generic/patches-4.0/072-06-bgmac-set-received-skb-headroom-to-NET_SKB_PAD.patch @@ -0,0 +1,66 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 10:13:28 +0200 +Subject: [PATCH] bgmac: set received skb headroom to NET_SKB_PAD + +A packet buffer offset of 30 bytes is inefficient, because the first 2 +bytes end up in a different cacheline. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -346,13 +346,13 @@ static int bgmac_dma_rx_skb_for_slot(str + return -ENOMEM; + + /* Poison - if everything goes fine, hardware will overwrite it */ +- rx = buf; ++ rx = buf + BGMAC_RX_BUF_OFFSET; + rx->len = cpu_to_le16(0xdead); + rx->flags = cpu_to_le16(0xbeef); + + /* Map skb for the DMA */ +- dma_addr = dma_map_single(dma_dev, buf, BGMAC_RX_BUF_SIZE, +- DMA_FROM_DEVICE); ++ dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, ++ BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(dma_dev, dma_addr)) { + bgmac_err(bgmac, "DMA mapping error\n"); + put_page(virt_to_head_page(buf)); +@@ -403,7 +403,7 @@ static int bgmac_dma_rx_read(struct bgma + while (ring->start != ring->end) { + struct device *dma_dev = bgmac->core->dma_dev; + struct bgmac_slot_info *slot = &ring->slots[ring->start]; +- struct bgmac_rx_header *rx = slot->buf; ++ struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; + struct sk_buff *skb; + void *buf = slot->buf; + u16 len, flags; +@@ -454,8 +454,10 @@ static int bgmac_dma_rx_read(struct bgma + BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); + + skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); +- skb_put(skb, BGMAC_RX_FRAME_OFFSET + len); +- skb_pull(skb, BGMAC_RX_FRAME_OFFSET); ++ skb_put(skb, BGMAC_RX_FRAME_OFFSET + ++ BGMAC_RX_BUF_OFFSET + len); ++ skb_pull(skb, BGMAC_RX_FRAME_OFFSET + ++ BGMAC_RX_BUF_OFFSET); + + skb_checksum_none_assert(skb); + skb->protocol = eth_type_trans(skb, bgmac->net_dev); +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -360,9 +360,11 @@ + + #define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */ + #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ ++#define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ ++ BGMAC_RX_FRAME_OFFSET) + #define BGMAC_RX_MAX_FRAME_SIZE 1536 /* Copied from b44/tg3 */ + #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) +-#define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE) + \ ++#define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) + + #define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */ diff --git a/target/linux/generic/patches-4.0/072-07-bgmac-simplify-rx-DMA-error-handling.patch b/target/linux/generic/patches-4.0/072-07-bgmac-simplify-rx-DMA-error-handling.patch new file mode 100644 index 0000000..2ca9d10 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-07-bgmac-simplify-rx-DMA-error-handling.patch @@ -0,0 +1,130 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 22:23:07 +0200 +Subject: [PATCH] bgmac: simplify/optimize rx DMA error handling + +Allocate a new buffer before processing the completed one. If allocation +fails, reuse the old buffer. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -386,6 +386,19 @@ static void bgmac_dma_rx_setup_desc(stru + dma_desc->ctl1 = cpu_to_le32(ctl1); + } + ++static void bgmac_dma_rx_poison_buf(struct device *dma_dev, ++ struct bgmac_slot_info *slot) ++{ ++ struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; ++ ++ dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++ rx->len = cpu_to_le16(0xdead); ++ rx->flags = cpu_to_le16(0xbeef); ++ dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); ++} ++ + static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, + int weight) + { +@@ -406,53 +419,35 @@ static int bgmac_dma_rx_read(struct bgma + struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; + struct sk_buff *skb; + void *buf = slot->buf; ++ dma_addr_t dma_addr = slot->dma_addr; + u16 len, flags; + +- /* Unmap buffer to make it accessible to the CPU */ +- dma_sync_single_for_cpu(dma_dev, slot->dma_addr, +- BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); +- +- /* Get info from the header */ +- len = le16_to_cpu(rx->len); +- flags = le16_to_cpu(rx->flags); +- + do { +- dma_addr_t old_dma_addr = slot->dma_addr; +- int err; ++ /* Prepare new skb as replacement */ ++ if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { ++ bgmac_dma_rx_poison_buf(dma_dev, slot); ++ break; ++ } ++ ++ /* Unmap buffer to make it accessible to the CPU */ ++ dma_unmap_single(dma_dev, dma_addr, ++ BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); ++ ++ /* Get info from the header */ ++ len = le16_to_cpu(rx->len); ++ flags = le16_to_cpu(rx->flags); + + /* Check for poison and drop or pass the packet */ + if (len == 0xdead && flags == 0xbeef) { + bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n", + ring->start); +- dma_sync_single_for_device(dma_dev, +- slot->dma_addr, +- BGMAC_RX_BUF_SIZE, +- DMA_FROM_DEVICE); ++ put_page(virt_to_head_page(buf)); + break; + } + + /* Omit CRC. */ + len -= ETH_FCS_LEN; + +- /* Prepare new skb as replacement */ +- err = bgmac_dma_rx_skb_for_slot(bgmac, slot); +- if (err) { +- /* Poison the old skb */ +- rx->len = cpu_to_le16(0xdead); +- rx->flags = cpu_to_le16(0xbeef); +- +- dma_sync_single_for_device(dma_dev, +- slot->dma_addr, +- BGMAC_RX_BUF_SIZE, +- DMA_FROM_DEVICE); +- break; +- } +- bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); +- +- /* Unmap old skb, we'll pass it to the netfif */ +- dma_unmap_single(dma_dev, old_dma_addr, +- BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); +- + skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); + skb_put(skb, BGMAC_RX_FRAME_OFFSET + + BGMAC_RX_BUF_OFFSET + len); +@@ -465,6 +460,8 @@ static int bgmac_dma_rx_read(struct bgma + handled++; + } while (0); + ++ bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); ++ + if (++ring->start >= BGMAC_RX_RING_SLOTS) + ring->start = 0; + +@@ -532,14 +529,14 @@ static void bgmac_dma_rx_ring_free(struc + + for (i = 0; i < ring->num_slots; i++) { + slot = &ring->slots[i]; +- if (!slot->buf) ++ if (!slot->dma_addr) + continue; + +- if (slot->dma_addr) +- dma_unmap_single(dma_dev, slot->dma_addr, +- BGMAC_RX_BUF_SIZE, +- DMA_FROM_DEVICE); ++ dma_unmap_single(dma_dev, slot->dma_addr, ++ BGMAC_RX_BUF_SIZE, ++ DMA_FROM_DEVICE); + put_page(virt_to_head_page(slot->buf)); ++ slot->dma_addr = 0; + } + } + diff --git a/target/linux/generic/patches-4.0/072-08-bgmac-add-check-for-oversized-packets.patch b/target/linux/generic/patches-4.0/072-08-bgmac-add-check-for-oversized-packets.patch new file mode 100644 index 0000000..705aa2d --- /dev/null +++ b/target/linux/generic/patches-4.0/072-08-bgmac-add-check-for-oversized-packets.patch @@ -0,0 +1,27 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 22:28:20 +0200 +Subject: [PATCH] bgmac: add check for oversized packets + +In very rare cases, the MAC can catch an internal buffer that is bigger +than it's supposed to be. Instead of crashing the kernel, simply pass +the buffer back to the hardware + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -445,6 +445,13 @@ static int bgmac_dma_rx_read(struct bgma + break; + } + ++ if (len > BGMAC_RX_ALLOC_SIZE) { ++ bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n", ++ ring->start); ++ put_page(virt_to_head_page(buf)); ++ break; ++ } ++ + /* Omit CRC. */ + len -= ETH_FCS_LEN; + diff --git a/target/linux/generic/patches-4.0/072-09-bgmac-increase-rx-ring-size-from-511-to-512.patch b/target/linux/generic/patches-4.0/072-09-bgmac-increase-rx-ring-size-from-511-to-512.patch new file mode 100644 index 0000000..4888cc3 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-09-bgmac-increase-rx-ring-size-from-511-to-512.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 22:36:16 +0200 +Subject: [PATCH] bgmac: increase rx ring size from 511 to 512 + +Limiting it to 511 looks like a failed attempt at leaving one descriptor +empty to allow the hardware to stop processing a buffer that has not +been prepared yet. However, this doesn't work because this affects the +total ring size as well + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -356,7 +356,7 @@ + #define BGMAC_MAX_RX_RINGS 1 + + #define BGMAC_TX_RING_SLOTS 128 +-#define BGMAC_RX_RING_SLOTS 512 - 1 /* Why -1? Well, Broadcom does that... */ ++#define BGMAC_RX_RING_SLOTS 512 + + #define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */ + #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ diff --git a/target/linux/generic/patches-4.0/072-10-bgmac-simplify-dma-init-cleanup.patch b/target/linux/generic/patches-4.0/072-10-bgmac-simplify-dma-init-cleanup.patch new file mode 100644 index 0000000..f8d7921 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-10-bgmac-simplify-dma-init-cleanup.patch @@ -0,0 +1,184 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 23:19:32 +0200 +Subject: [PATCH] bgmac: simplify dma init/cleanup + +Instead of allocating buffers at device init time and initializing +descriptors at device open, do both at the same time (during open). +Free all buffers when closing the device. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -562,18 +562,26 @@ static void bgmac_dma_ring_desc_free(str + ring->dma_base); + } + +-static void bgmac_dma_free(struct bgmac *bgmac) ++static void bgmac_dma_cleanup(struct bgmac *bgmac) + { + int i; + +- for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) + bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); +- bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); +- } +- for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { ++ ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) + bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); ++} ++ ++static void bgmac_dma_free(struct bgmac *bgmac) ++{ ++ int i; ++ ++ for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); ++ ++ for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) + bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); +- } + } + + static int bgmac_dma_alloc(struct bgmac *bgmac) +@@ -621,8 +629,6 @@ static int bgmac_dma_alloc(struct bgmac + } + + for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { +- int j; +- + ring = &bgmac->rx_ring[i]; + ring->num_slots = BGMAC_RX_RING_SLOTS; + ring->mmio_base = ring_base[i]; +@@ -645,15 +651,6 @@ static int bgmac_dma_alloc(struct bgmac + ring->index_base = lower_32_bits(ring->dma_base); + else + ring->index_base = 0; +- +- /* Alloc RX slots */ +- for (j = 0; j < ring->num_slots; j++) { +- err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); +- if (err) { +- bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n"); +- goto err_dma_free; +- } +- } + } + + return 0; +@@ -663,10 +660,10 @@ err_dma_free: + return -ENOMEM; + } + +-static void bgmac_dma_init(struct bgmac *bgmac) ++static int bgmac_dma_init(struct bgmac *bgmac) + { + struct bgmac_dma_ring *ring; +- int i; ++ int i, err; + + for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { + ring = &bgmac->tx_ring[i]; +@@ -698,8 +695,13 @@ static void bgmac_dma_init(struct bgmac + if (ring->unaligned) + bgmac_dma_rx_enable(bgmac, ring); + +- for (j = 0; j < ring->num_slots; j++) ++ for (j = 0; j < ring->num_slots; j++) { ++ err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); ++ if (err) ++ goto error; ++ + bgmac_dma_rx_setup_desc(bgmac, ring, j); ++ } + + bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, + ring->index_base + +@@ -708,6 +710,12 @@ static void bgmac_dma_init(struct bgmac + ring->start = 0; + ring->end = 0; + } ++ ++ return 0; ++ ++error: ++ bgmac_dma_cleanup(bgmac); ++ return err; + } + + /************************************************** +@@ -1183,11 +1191,8 @@ static void bgmac_enable(struct bgmac *b + } + + /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ +-static void bgmac_chip_init(struct bgmac *bgmac, bool full_init) ++static void bgmac_chip_init(struct bgmac *bgmac) + { +- struct bgmac_dma_ring *ring; +- int i; +- + /* 1 interrupt per received frame */ + bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); + +@@ -1205,16 +1210,7 @@ static void bgmac_chip_init(struct bgmac + + bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); + +- if (full_init) { +- bgmac_dma_init(bgmac); +- if (1) /* FIXME: is there any case we don't want IRQs? */ +- bgmac_chip_intrs_on(bgmac); +- } else { +- for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { +- ring = &bgmac->rx_ring[i]; +- bgmac_dma_rx_enable(bgmac, ring); +- } +- } ++ bgmac_chip_intrs_on(bgmac); + + bgmac_enable(bgmac); + } +@@ -1274,23 +1270,27 @@ static int bgmac_open(struct net_device + int err = 0; + + bgmac_chip_reset(bgmac); ++ ++ err = bgmac_dma_init(bgmac); ++ if (err) ++ return err; ++ + /* Specs say about reclaiming rings here, but we do that in DMA init */ +- bgmac_chip_init(bgmac, true); ++ bgmac_chip_init(bgmac); + + err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED, + KBUILD_MODNAME, net_dev); + if (err < 0) { + bgmac_err(bgmac, "IRQ request error: %d!\n", err); +- goto err_out; ++ bgmac_dma_cleanup(bgmac); ++ return err; + } + napi_enable(&bgmac->napi); + + phy_start(bgmac->phy_dev); + + netif_carrier_on(net_dev); +- +-err_out: +- return err; ++ return 0; + } + + static int bgmac_stop(struct net_device *net_dev) +@@ -1306,6 +1306,7 @@ static int bgmac_stop(struct net_device + free_irq(bgmac->core->irq, net_dev); + + bgmac_chip_reset(bgmac); ++ bgmac_dma_cleanup(bgmac); + + return 0; + } diff --git a/target/linux/generic/patches-4.0/072-11-bgmac-fix-DMA-rx-corruption.patch b/target/linux/generic/patches-4.0/072-11-bgmac-fix-DMA-rx-corruption.patch new file mode 100644 index 0000000..2e670d8 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-11-bgmac-fix-DMA-rx-corruption.patch @@ -0,0 +1,88 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 11:59:47 +0200 +Subject: [PATCH] bgmac: fix DMA rx corruption + +The driver needs to inform the hardware about the first invalid (not yet +filled) rx slot, by writing its DMA descriptor pointer offset to the +BGMAC_DMA_RX_INDEX register. + +This register was set to a value exceeding the rx ring size, effectively +allowing the hardware constant access to the full ring, regardless of +which slots are initialized. + +To fix this issue, always mark the last filled rx slot as invalid. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -366,6 +366,16 @@ static int bgmac_dma_rx_skb_for_slot(str + return 0; + } + ++static void bgmac_dma_rx_update_index(struct bgmac *bgmac, ++ struct bgmac_dma_ring *ring) ++{ ++ wmb(); ++ ++ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, ++ ring->index_base + ++ ring->end * sizeof(struct bgmac_dma_desc)); ++} ++ + static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, + struct bgmac_dma_ring *ring, int desc_idx) + { +@@ -384,6 +394,8 @@ static void bgmac_dma_rx_setup_desc(stru + dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); + dma_desc->ctl0 = cpu_to_le32(ctl0); + dma_desc->ctl1 = cpu_to_le32(ctl1); ++ ++ ring->end = desc_idx; + } + + static void bgmac_dma_rx_poison_buf(struct device *dma_dev, +@@ -411,9 +423,7 @@ static int bgmac_dma_rx_read(struct bgma + end_slot &= BGMAC_DMA_RX_STATDPTR; + end_slot /= sizeof(struct bgmac_dma_desc); + +- ring->end = end_slot; +- +- while (ring->start != ring->end) { ++ while (ring->start != end_slot) { + struct device *dma_dev = bgmac->core->dma_dev; + struct bgmac_slot_info *slot = &ring->slots[ring->start]; + struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; +@@ -476,6 +486,8 @@ static int bgmac_dma_rx_read(struct bgma + break; + } + ++ bgmac_dma_rx_update_index(bgmac, ring); ++ + return handled; + } + +@@ -695,6 +707,8 @@ static int bgmac_dma_init(struct bgmac * + if (ring->unaligned) + bgmac_dma_rx_enable(bgmac, ring); + ++ ring->start = 0; ++ ring->end = 0; + for (j = 0; j < ring->num_slots; j++) { + err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); + if (err) +@@ -703,12 +717,7 @@ static int bgmac_dma_init(struct bgmac * + bgmac_dma_rx_setup_desc(bgmac, ring, j); + } + +- bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, +- ring->index_base + +- ring->num_slots * sizeof(struct bgmac_dma_desc)); +- +- ring->start = 0; +- ring->end = 0; ++ bgmac_dma_rx_update_index(bgmac, ring); + } + + return 0; diff --git a/target/linux/generic/patches-4.0/072-12-bgmac-drop-ring-num_slots.patch b/target/linux/generic/patches-4.0/072-12-bgmac-drop-ring-num_slots.patch new file mode 100644 index 0000000..4cd2e3f --- /dev/null +++ b/target/linux/generic/patches-4.0/072-12-bgmac-drop-ring-num_slots.patch @@ -0,0 +1,132 @@ +From: Felix Fietkau +Date: Sun, 12 Apr 2015 23:28:38 +0200 +Subject: [PATCH] bgmac: drop ring->num_slots + +The ring size is always known at compile time, so make the code a bit +more efficient + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -123,7 +123,7 @@ bgmac_dma_tx_add_buf(struct bgmac *bgmac + struct bgmac_dma_desc *dma_desc; + u32 ctl1; + +- if (i == ring->num_slots - 1) ++ if (i == BGMAC_TX_RING_SLOTS - 1) + ctl0 |= BGMAC_DESC_CTL0_EOT; + + ctl1 = len & BGMAC_DESC_CTL1_LEN; +@@ -382,7 +382,7 @@ static void bgmac_dma_rx_setup_desc(stru + struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; + u32 ctl0 = 0, ctl1 = 0; + +- if (desc_idx == ring->num_slots - 1) ++ if (desc_idx == BGMAC_RX_RING_SLOTS - 1) + ctl0 |= BGMAC_DESC_CTL0_EOT; + ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; + /* Is there any BGMAC device that requires extension? */ +@@ -521,7 +521,7 @@ static void bgmac_dma_tx_ring_free(struc + struct bgmac_slot_info *slot; + int i; + +- for (i = 0; i < ring->num_slots; i++) { ++ for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) { + int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; + + slot = &ring->slots[i]; +@@ -546,7 +546,7 @@ static void bgmac_dma_rx_ring_free(struc + struct bgmac_slot_info *slot; + int i; + +- for (i = 0; i < ring->num_slots; i++) { ++ for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) { + slot = &ring->slots[i]; + if (!slot->dma_addr) + continue; +@@ -560,7 +560,8 @@ static void bgmac_dma_rx_ring_free(struc + } + + static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, +- struct bgmac_dma_ring *ring) ++ struct bgmac_dma_ring *ring, ++ int num_slots) + { + struct device *dma_dev = bgmac->core->dma_dev; + int size; +@@ -569,7 +570,7 @@ static void bgmac_dma_ring_desc_free(str + return; + + /* Free ring of descriptors */ +- size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ size = num_slots * sizeof(struct bgmac_dma_desc); + dma_free_coherent(dma_dev, size, ring->cpu_base, + ring->dma_base); + } +@@ -590,10 +591,12 @@ static void bgmac_dma_free(struct bgmac + int i; + + for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) +- bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i]); ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i], ++ BGMAC_TX_RING_SLOTS); + + for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) +- bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i]); ++ bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i], ++ BGMAC_RX_RING_SLOTS); + } + + static int bgmac_dma_alloc(struct bgmac *bgmac) +@@ -616,11 +619,10 @@ static int bgmac_dma_alloc(struct bgmac + + for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { + ring = &bgmac->tx_ring[i]; +- ring->num_slots = BGMAC_TX_RING_SLOTS; + ring->mmio_base = ring_base[i]; + + /* Alloc ring of descriptors */ +- size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc); + ring->cpu_base = dma_zalloc_coherent(dma_dev, size, + &ring->dma_base, + GFP_KERNEL); +@@ -642,11 +644,10 @@ static int bgmac_dma_alloc(struct bgmac + + for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { + ring = &bgmac->rx_ring[i]; +- ring->num_slots = BGMAC_RX_RING_SLOTS; + ring->mmio_base = ring_base[i]; + + /* Alloc ring of descriptors */ +- size = ring->num_slots * sizeof(struct bgmac_dma_desc); ++ size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc); + ring->cpu_base = dma_zalloc_coherent(dma_dev, size, + &ring->dma_base, + GFP_KERNEL); +@@ -709,7 +710,7 @@ static int bgmac_dma_init(struct bgmac * + + ring->start = 0; + ring->end = 0; +- for (j = 0; j < ring->num_slots; j++) { ++ for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) { + err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); + if (err) + goto error; +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -419,11 +419,10 @@ struct bgmac_dma_ring { + u32 start; + u32 end; + +- u16 num_slots; +- u16 mmio_base; + struct bgmac_dma_desc *cpu_base; + dma_addr_t dma_base; + u32 index_base; /* Used for unaligned rings only, otherwise 0 */ ++ u16 mmio_base; + bool unaligned; + + struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS]; diff --git a/target/linux/generic/patches-4.0/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch b/target/linux/generic/patches-4.0/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch new file mode 100644 index 0000000..a3d9fd6 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch @@ -0,0 +1,24 @@ +From: Felix Fietkau +Date: Mon, 13 Apr 2015 15:54:04 +0200 +Subject: [PATCH] bgmac: fix MAC soft-reset bit for corerev > 4 + +Only core revisions older than 4 use BGMAC_CMDCFG_SR_REV0 + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -198,9 +198,9 @@ + #define BGMAC_CMDCFG_TAI 0x00000200 + #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ + #define BGMAC_CMDCFG_HD_SHIFT 10 +-#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */ +-#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */ +-#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) ++#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */ ++#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */ ++#define BGMAC_CMDCFG_SR(rev) ((rev >= 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) + #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ + #define BGMAC_CMDCFG_AE 0x00400000 + #define BGMAC_CMDCFG_CFE 0x00800000 diff --git a/target/linux/generic/patches-4.0/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch b/target/linux/generic/patches-4.0/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch new file mode 100644 index 0000000..2a913a6 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch @@ -0,0 +1,28 @@ +From: Felix Fietkau +Date: Mon, 13 Apr 2015 15:56:26 +0200 +Subject: [PATCH] bgmac: reset all 4 GMAC cores on init + +On a BCM4709 based device, I found that GMAC cores may be enabled at +probe time, but only become usable after a full reset. +Disable cores before re-enabling them to ensure that they are properly +reset. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1623,8 +1623,11 @@ static int bgmac_probe(struct bcma_devic + ns_core = bcma_find_core_unit(core->bus, + BCMA_CORE_MAC_GBIT, + ns_gmac); +- if (ns_core && !bcma_core_is_enabled(ns_core)) +- bcma_core_enable(ns_core, 0); ++ if (!ns_core) ++ continue; ++ ++ bcma_core_disable(ns_core, 0); ++ bcma_core_enable(ns_core, 0); + } + } + diff --git a/target/linux/generic/patches-4.0/072-15-bgmac-fix-requests-for-extra-polling-calls-from-NAPI.patch b/target/linux/generic/patches-4.0/072-15-bgmac-fix-requests-for-extra-polling-calls-from-NAPI.patch new file mode 100644 index 0000000..62e9379 --- /dev/null +++ b/target/linux/generic/patches-4.0/072-15-bgmac-fix-requests-for-extra-polling-calls-from-NAPI.patch @@ -0,0 +1,30 @@ +From 047f89922c6381432501f248d08226ff9adc4ee3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Thu, 23 Apr 2015 20:45:25 +0200 +Subject: [PATCH][FIX 4.1] bgmac: fix requests for extra polling calls from + NAPI +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +After d75b1ade567f ("net: less interrupt masking in NAPI") polling +function has to return whole budget when it wants NAPI to call it again. + +Signed-off-by: Rafał Miłecki +Cc: Felix Fietkau +Fixes: eb64e2923a886 ("bgmac: leave interrupts disabled as long as there is work to do") +--- + drivers/net/ethernet/broadcom/bgmac.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1260,7 +1260,7 @@ static int bgmac_poll(struct napi_struct + + /* Poll again if more events arrived in the meantime */ + if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) +- return handled; ++ return weight; + + if (handled < weight) { + napi_complete(napi); diff --git a/target/linux/generic/patches-4.0/073-pppoe-Use-workqueue-to-die-properly-when-a-PADT-is-r.patch b/target/linux/generic/patches-4.0/073-pppoe-Use-workqueue-to-die-properly-when-a-PADT-is-r.patch new file mode 100644 index 0000000..de85830 --- /dev/null +++ b/target/linux/generic/patches-4.0/073-pppoe-Use-workqueue-to-die-properly-when-a-PADT-is-r.patch @@ -0,0 +1,89 @@ +From: Simon Farnsworth +Date: Sun, 1 Mar 2015 10:54:39 +0000 +Subject: [PATCH] pppoe: Use workqueue to die properly when a PADT is received + +When a PADT frame is received, the socket may not be in a good state to +close down the PPP interface. The current implementation handles this by +simply blocking all further PPP traffic, and hoping that the lack of traffic +will trigger the user to investigate. + +Use schedule_work to get to a process context from which we clear down the +PPP interface, in a fashion analogous to hangup on a TTY-based PPP +interface. This causes pppd to disconnect immediately, and allows tools to +take immediate corrective action. + +Note that pppd's rp_pppoe.so plugin has code in it to disable the session +when it disconnects; however, as a consequence of this patch, the session is +already disabled before rp_pppoe.so is asked to disable the session. The +result is a harmless error message: + +Failed to disconnect PPPoE socket: 114 Operation already in progress + +This message is safe to ignore, as long as the error is 114 Operation +already in progress; in that specific case, it means that the PPPoE session +has already been disabled before pppd tried to disable it. + +Signed-off-by: Simon Farnsworth +Tested-by: Dan Williams +Tested-by: Christoph Schulz +Signed-off-by: David S. Miller +--- + +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -455,6 +455,18 @@ out: + return NET_RX_DROP; + } + ++static void pppoe_unbind_sock_work(struct work_struct *work) ++{ ++ struct pppox_sock *po = container_of(work, struct pppox_sock, ++ proto.pppoe.padt_work); ++ struct sock *sk = sk_pppox(po); ++ ++ lock_sock(sk); ++ pppox_unbind_sock(sk); ++ release_sock(sk); ++ sock_put(sk); ++} ++ + /************************************************************************ + * + * Receive a PPPoE Discovery frame. +@@ -500,7 +512,8 @@ static int pppoe_disc_rcv(struct sk_buff + } + + bh_unlock_sock(sk); +- sock_put(sk); ++ if (!schedule_work(&po->proto.pppoe.padt_work)) ++ sock_put(sk); + } + + abort: +@@ -613,6 +626,8 @@ static int pppoe_connect(struct socket * + + lock_sock(sk); + ++ INIT_WORK(&po->proto.pppoe.padt_work, pppoe_unbind_sock_work); ++ + error = -EINVAL; + if (sp->sa_protocol != PX_PROTO_OE) + goto end; +--- a/include/linux/if_pppox.h ++++ b/include/linux/if_pppox.h +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + + static inline struct pppoe_hdr *pppoe_hdr(const struct sk_buff *skb) +@@ -32,6 +33,7 @@ struct pppoe_opt { + struct pppoe_addr pa; /* what this socket is bound to*/ + struct sockaddr_pppox relay; /* what socket data will be + relayed to (PPPoE relaying) */ ++ struct work_struct padt_work;/* Work item for handling PADT */ + }; + + struct pptp_opt { diff --git a/target/linux/generic/patches-4.0/091-mtd-spi-nor-add-support-Spansion_S25FL164K b/target/linux/generic/patches-4.0/091-mtd-spi-nor-add-support-Spansion_S25FL164K new file mode 100644 index 0000000..51d93de --- /dev/null +++ b/target/linux/generic/patches-4.0/091-mtd-spi-nor-add-support-Spansion_S25FL164K @@ -0,0 +1,10 @@ +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -598,6 +598,7 @@ static const struct spi_device_id spi_no + { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, + { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, + { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, 0) }, ++ { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, + + /* SST -- large erase sizes are "overlays", "sectors" are 4K */ + { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, diff --git a/target/linux/generic/patches-4.0/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch b/target/linux/generic/patches-4.0/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch new file mode 100644 index 0000000..d0bea94 --- /dev/null +++ b/target/linux/generic/patches-4.0/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch @@ -0,0 +1,146 @@ +From 279c6c7fa64f5763e6b9f05e7ab3840092e702e7 Mon Sep 17 00:00:00 2001 +From: Stephen Hemminger +Date: Mon, 29 Jun 2015 14:57:48 -1000 +Subject: [PATCH] api: fix compatibility of linux/in.h with netinet/in.h + +u +This fixes breakage to iproute2 build with recent kernel headers +caused by: + commit a263653ed798216c0069922d7b5237ca49436007 + Author: Pablo Neira Ayuso + Date: Wed Jun 17 10:28:27 2015 -0500 + + netfilter: don't pull include/linux/netfilter.h from netns headers + +The issue is that definitions in linux/in.h overlap with those +in netinet/in.h. This patch solves this by introducing the same +mechanism as was used to solve the same problem with linux/in6.h + +Signed-off-by: Stephen Hemminger +Signed-off-by: David S. Miller +--- + include/uapi/linux/in.h | 16 +++++++++++++--- + include/uapi/linux/libc-compat.h | 22 ++++++++++++++++++++++ + 2 files changed, 35 insertions(+), 3 deletions(-) + +--- a/include/uapi/linux/in.h ++++ b/include/uapi/linux/in.h +@@ -19,8 +19,10 @@ + #define _UAPI_LINUX_IN_H + + #include ++#include + #include + ++#if __UAPI_DEF_IN_IPPROTO + /* Standard well-defined IP protocols. */ + enum { + IPPROTO_IP = 0, /* Dummy protocol for TCP */ +@@ -73,12 +75,14 @@ enum { + #define IPPROTO_RAW IPPROTO_RAW + IPPROTO_MAX + }; ++#endif + +- ++#if __UAPI_DEF_IN_ADDR + /* Internet address. */ + struct in_addr { + __be32 s_addr; + }; ++#endif + + #define IP_TOS 1 + #define IP_TTL 2 +@@ -155,6 +159,7 @@ struct in_addr { + + /* Request struct for multicast socket ops */ + ++#if __UAPI_DEF_IP_MREQ + struct ip_mreq { + struct in_addr imr_multiaddr; /* IP multicast address of group */ + struct in_addr imr_interface; /* local IP address of interface */ +@@ -206,14 +211,18 @@ struct group_filter { + #define GROUP_FILTER_SIZE(numsrc) \ + (sizeof(struct group_filter) - sizeof(struct __kernel_sockaddr_storage) \ + + (numsrc) * sizeof(struct __kernel_sockaddr_storage)) ++#endif + ++#if __UAPI_DEF_IN_PKTINFO + struct in_pktinfo { + int ipi_ifindex; + struct in_addr ipi_spec_dst; + struct in_addr ipi_addr; + }; ++#endif + + /* Structure describing an Internet (IP) socket address. */ ++#if __UAPI_DEF_SOCKADDR_IN + #define __SOCK_SIZE__ 16 /* sizeof(struct sockaddr) */ + struct sockaddr_in { + __kernel_sa_family_t sin_family; /* Address family */ +@@ -225,8 +234,9 @@ struct sockaddr_in { + sizeof(unsigned short int) - sizeof(struct in_addr)]; + }; + #define sin_zero __pad /* for BSD UNIX comp. -FvK */ ++#endif + +- ++#if __UAPI_DEF_IN_CLASS + /* + * Definitions of the bits in an Internet address integer. + * On subnets, host and network parts are found according +@@ -277,7 +287,7 @@ struct sockaddr_in { + #define INADDR_ALLHOSTS_GROUP 0xe0000001U /* 224.0.0.1 */ + #define INADDR_ALLRTRS_GROUP 0xe0000002U /* 224.0.0.2 */ + #define INADDR_MAX_LOCAL_GROUP 0xe00000ffU /* 224.0.0.255 */ +- ++#endif + + /* contains the htonl type stuff.. */ + #include +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -56,6 +56,13 @@ + + /* GLIBC headers included first so don't define anything + * that would already be defined. */ ++#define __UAPI_DEF_IN_ADDR 0 ++#define __UAPI_DEF_IN_IPPROTO 0 ++#define __UAPI_DEF_IN_PKTINFO 0 ++#define __UAPI_DEF_IP_MREQ 0 ++#define __UAPI_DEF_SOCKADDR_IN 0 ++#define __UAPI_DEF_IN_CLASS 0 ++ + #define __UAPI_DEF_IN6_ADDR 0 + /* The exception is the in6_addr macros which must be defined + * if the glibc code didn't define them. This guard matches +@@ -78,6 +85,13 @@ + /* Linux headers included first, and we must define everything + * we need. The expectation is that glibc will check the + * __UAPI_DEF_* defines and adjust appropriately. */ ++#define __UAPI_DEF_IN_ADDR 1 ++#define __UAPI_DEF_IN_IPPROTO 1 ++#define __UAPI_DEF_IN_PKTINFO 1 ++#define __UAPI_DEF_IP_MREQ 1 ++#define __UAPI_DEF_SOCKADDR_IN 1 ++#define __UAPI_DEF_IN_CLASS 1 ++ + #define __UAPI_DEF_IN6_ADDR 1 + /* We unconditionally define the in6_addr macros and glibc must + * coordinate. */ +@@ -103,6 +117,14 @@ + * that we need. */ + #else /* !defined(__GLIBC__) */ + ++/* Definitions for in.h */ ++#define __UAPI_DEF_IN_ADDR 1 ++#define __UAPI_DEF_IN_IPPROTO 1 ++#define __UAPI_DEF_IN_PKTINFO 1 ++#define __UAPI_DEF_IP_MREQ 1 ++#define __UAPI_DEF_SOCKADDR_IN 1 ++#define __UAPI_DEF_IN_CLASS 1 ++ + /* Definitions for in6.h */ + #define __UAPI_DEF_IN6_ADDR 1 + #define __UAPI_DEF_IN6_ADDR_ALT 1 diff --git a/target/linux/generic/patches-4.0/100-pppoe-drop-pppoe-device-in-pppoe_unbind_sock_work.patch b/target/linux/generic/patches-4.0/100-pppoe-drop-pppoe-device-in-pppoe_unbind_sock_work.patch new file mode 100644 index 0000000..c461b3e --- /dev/null +++ b/target/linux/generic/patches-4.0/100-pppoe-drop-pppoe-device-in-pppoe_unbind_sock_work.patch @@ -0,0 +1,27 @@ +From: Felix Fietkau +Date: Sat, 9 May 2015 23:03:47 +0200 +Subject: [PATCH] pppoe: drop pppoe device in pppoe_unbind_sock_work + +After receiving a PADT and the socket is closed, user space will no +longer drop the reference to the pppoe device. +This leads to errors like this: + +[ 488.570000] unregister_netdevice: waiting for eth0.2 to become free. Usage count = 2 + +Fixes: 287f3a943fe ("pppoe: Use workqueue to die properly when a PADT is received") +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -462,6 +462,10 @@ static void pppoe_unbind_sock_work(struc + struct sock *sk = sk_pppox(po); + + lock_sock(sk); ++ if (po->pppoe_dev) { ++ dev_put(po->pppoe_dev); ++ po->pppoe_dev = NULL; ++ } + pppox_unbind_sock(sk); + release_sock(sk); + sock_put(sk); diff --git a/target/linux/generic/patches-4.0/102-ehci_hcd_ignore_oc.patch b/target/linux/generic/patches-4.0/102-ehci_hcd_ignore_oc.patch new file mode 100644 index 0000000..4da579c --- /dev/null +++ b/target/linux/generic/patches-4.0/102-ehci_hcd_ignore_oc.patch @@ -0,0 +1,82 @@ +From 1e311820ec3055e3f08e687de6564692a7cec675 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:29 +0100 +Subject: [PATCH 11/12] USB: EHCI: add ignore_oc flag to disable overcurrent + checking + +This patch adds an ignore_oc flag which can be set by EHCI controller +not supporting or wanting to disable overcurrent checking. The EHCI +platform data in include/linux/usb/ehci_pdriver.h is also augmented to +take advantage of this new flag. + +Signed-off-by: Florian Fainelli +--- + drivers/usb/host/ehci-hcd.c | 2 +- + drivers/usb/host/ehci-hub.c | 4 ++-- + drivers/usb/host/ehci-platform.c | 1 + + drivers/usb/host/ehci.h | 1 + + include/linux/usb/ehci_pdriver.h | 1 + + 5 files changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -638,7 +638,7 @@ static int ehci_run (struct usb_hcd *hcd + "USB %x.%x started, EHCI %x.%02x%s\n", + ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), + temp >> 8, temp & 0xff, +- ignore_oc ? ", overcurrent ignored" : ""); ++ (ignore_oc || ehci->ignore_oc) ? ", overcurrent ignored" : ""); + + ehci_writel(ehci, INTR_MASK, + &ehci->regs->intr_enable); /* Turn On Interrupts */ +--- a/drivers/usb/host/ehci-hub.c ++++ b/drivers/usb/host/ehci-hub.c +@@ -633,7 +633,7 @@ ehci_hub_status_data (struct usb_hcd *hc + * always set, seem to clear PORT_OCC and PORT_CSC when writing to + * PORT_POWER; that's surprising, but maybe within-spec. + */ +- if (!ignore_oc) ++ if (!ignore_oc && !ehci->ignore_oc) + mask = PORT_CSC | PORT_PEC | PORT_OCC; + else + mask = PORT_CSC | PORT_PEC; +@@ -995,7 +995,7 @@ int ehci_hub_control( + if (temp & PORT_PEC) + status |= USB_PORT_STAT_C_ENABLE << 16; + +- if ((temp & PORT_OCC) && !ignore_oc){ ++ if ((temp & PORT_OCC) && (!ignore_oc && !ehci->ignore_oc)){ + status |= USB_PORT_STAT_C_OVERCURRENT << 16; + + /* +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -264,6 +264,8 @@ static int ehci_platform_probe(struct pl + ehci->big_endian_desc = 1; + if (pdata->big_endian_mmio) + ehci->big_endian_mmio = 1; ++ if (pdata->ignore_oc) ++ ehci->ignore_oc = 1; + + #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO + if (ehci->big_endian_mmio) { +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -226,6 +226,7 @@ struct ehci_hcd { /* one per controlle + unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ + unsigned need_oc_pp_cycle:1; /* MPC834X port power */ + unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ ++ unsigned ignore_oc:1; + + /* required for usb32 quirk */ + #define OHCI_CTRL_HCFS (3 << 6) +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -49,6 +49,7 @@ struct usb_ehci_pdata { + unsigned no_io_watchdog:1; + unsigned reset_on_resume:1; + unsigned dma_mask_64:1; ++ unsigned ignore_oc:1; + + /* Turn on all power and clocks */ + int (*power_on)(struct platform_device *pdev); diff --git a/target/linux/generic/patches-4.0/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch b/target/linux/generic/patches-4.0/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch new file mode 100644 index 0000000..9d32777 --- /dev/null +++ b/target/linux/generic/patches-4.0/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch @@ -0,0 +1,86 @@ +From: Felix Fietkau +Date: Fri, 10 Apr 2015 13:35:29 +0200 +Subject: [PATCH] jffs2: use .rename2 and add RENAME_WHITEOUT support + +It is required for renames on overlayfs + +Signed-off-by: Felix Fietkau +--- + +--- a/fs/jffs2/dir.c ++++ b/fs/jffs2/dir.c +@@ -35,7 +35,7 @@ static int jffs2_mkdir (struct inode *,s + static int jffs2_rmdir (struct inode *,struct dentry *); + static int jffs2_mknod (struct inode *,struct dentry *,umode_t,dev_t); + static int jffs2_rename (struct inode *, struct dentry *, +- struct inode *, struct dentry *); ++ struct inode *, struct dentry *, unsigned int); + + const struct file_operations jffs2_dir_operations = + { +@@ -57,7 +57,7 @@ const struct inode_operations jffs2_dir_ + .mkdir = jffs2_mkdir, + .rmdir = jffs2_rmdir, + .mknod = jffs2_mknod, +- .rename = jffs2_rename, ++ .rename2 = jffs2_rename, + .get_acl = jffs2_get_acl, + .set_acl = jffs2_set_acl, + .setattr = jffs2_setattr, +@@ -756,8 +756,27 @@ static int jffs2_mknod (struct inode *di + return ret; + } + ++static int jffs2_whiteout(struct inode *old_dir, struct dentry *old_dentry) ++{ ++ struct dentry *wh; ++ int err; ++ ++ wh = d_alloc(old_dentry->d_parent, &old_dentry->d_name); ++ if (!wh) ++ return -ENOMEM; ++ ++ err = jffs2_mknod(old_dir, wh, S_IFCHR | WHITEOUT_MODE, ++ WHITEOUT_DEV); ++ if (err) ++ return err; ++ ++ d_rehash(wh); ++ return 0; ++} ++ + static int jffs2_rename (struct inode *old_dir_i, struct dentry *old_dentry, +- struct inode *new_dir_i, struct dentry *new_dentry) ++ struct inode *new_dir_i, struct dentry *new_dentry, ++ unsigned int flags) + { + int ret; + struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb); +@@ -765,6 +784,9 @@ static int jffs2_rename (struct inode *o + uint8_t type; + uint32_t now; + ++ if (flags & ~RENAME_WHITEOUT) ++ return -EINVAL; ++ + /* The VFS will check for us and prevent trying to rename a + * file over a directory and vice versa, but if it's a directory, + * the VFS can't check whether the victim is empty. The filesystem +@@ -828,9 +850,14 @@ static int jffs2_rename (struct inode *o + if (d_is_dir(old_dentry) && !victim_f) + inc_nlink(new_dir_i); + +- /* Unlink the original */ +- ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), +- old_dentry->d_name.name, old_dentry->d_name.len, NULL, now); ++ if (flags & RENAME_WHITEOUT) ++ /* Replace with whiteout */ ++ ret = jffs2_whiteout(old_dir_i, old_dentry); ++ else ++ /* Unlink the original */ ++ ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), ++ old_dentry->d_name.name, ++ old_dentry->d_name.len, NULL, now); + + /* We don't touch inode->i_nlink */ + diff --git a/target/linux/generic/patches-4.0/111-jffs2-add-RENAME_EXCHANGE-support.patch b/target/linux/generic/patches-4.0/111-jffs2-add-RENAME_EXCHANGE-support.patch new file mode 100644 index 0000000..5e4722d --- /dev/null +++ b/target/linux/generic/patches-4.0/111-jffs2-add-RENAME_EXCHANGE-support.patch @@ -0,0 +1,58 @@ +From: Felix Fietkau +Date: Sat, 25 Apr 2015 12:41:32 +0200 +Subject: [PATCH] jffs2: add RENAME_EXCHANGE support + +Signed-off-by: Felix Fietkau +--- + +--- a/fs/jffs2/dir.c ++++ b/fs/jffs2/dir.c +@@ -784,7 +784,7 @@ static int jffs2_rename (struct inode *o + uint8_t type; + uint32_t now; + +- if (flags & ~RENAME_WHITEOUT) ++ if (flags & ~(RENAME_WHITEOUT | RENAME_EXCHANGE)) + return -EINVAL; + + /* The VFS will check for us and prevent trying to rename a +@@ -792,7 +792,7 @@ static int jffs2_rename (struct inode *o + * the VFS can't check whether the victim is empty. The filesystem + * needs to do that for itself. + */ +- if (new_dentry->d_inode) { ++ if (new_dentry->d_inode && !(flags & RENAME_EXCHANGE)) { + victim_f = JFFS2_INODE_INFO(new_dentry->d_inode); + if (d_is_dir(new_dentry)) { + struct jffs2_full_dirent *fd; +@@ -827,7 +827,7 @@ static int jffs2_rename (struct inode *o + if (ret) + return ret; + +- if (victim_f) { ++ if (victim_f && !(flags & RENAME_EXCHANGE)) { + /* There was a victim. Kill it off nicely */ + if (d_is_dir(new_dentry)) + clear_nlink(new_dentry->d_inode); +@@ -853,6 +853,12 @@ static int jffs2_rename (struct inode *o + if (flags & RENAME_WHITEOUT) + /* Replace with whiteout */ + ret = jffs2_whiteout(old_dir_i, old_dentry); ++ else if (flags & RENAME_EXCHANGE) ++ /* Replace the original */ ++ ret = jffs2_do_link(c, JFFS2_INODE_INFO(old_dir_i), ++ new_dentry->d_inode->i_ino, type, ++ old_dentry->d_name.name, old_dentry->d_name.len, ++ now); + else + /* Unlink the original */ + ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), +@@ -879,7 +885,7 @@ static int jffs2_rename (struct inode *o + return ret; + } + +- if (d_is_dir(old_dentry)) ++ if (d_is_dir(old_dentry) && !(flags & RENAME_EXCHANGE)) + drop_nlink(old_dir_i); + + new_dir_i->i_mtime = new_dir_i->i_ctime = old_dir_i->i_mtime = old_dir_i->i_ctime = ITIME(now); diff --git a/target/linux/generic/patches-4.0/120-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/patches-4.0/120-bridge_allow_receiption_on_disabled_port.patch new file mode 100644 index 0000000..bd24fdb --- /dev/null +++ b/target/linux/generic/patches-4.0/120-bridge_allow_receiption_on_disabled_port.patch @@ -0,0 +1,54 @@ +From: Stephen Hemminger +Subject: bridge: allow receiption on disabled port + +When an ethernet device is enslaved to a bridge, and the bridge STP +detects loss of carrier (or operational state down), then normally +packet receiption is blocked. + +This breaks control applications like WPA which maybe expecting to +receive packets to negotiate to bring link up. The bridge needs to +block forwarding packets from these disabled ports, but there is no +hard requirement to not allow local packet delivery. + +Signed-off-by: Stephen Hemminger +Signed-off-by: Felix Fietkau + +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -207,11 +207,13 @@ EXPORT_SYMBOL_GPL(br_handle_frame_finish + static int br_handle_local_finish(struct sk_buff *skb) + { + struct net_bridge_port *p = br_port_get_rcu(skb->dev); +- u16 vid = 0; ++ if (p->state != BR_STATE_DISABLED) { ++ u16 vid = 0; + +- /* check if vlan is allowed, to avoid spoofing */ +- if (p->flags & BR_LEARNING && br_should_learn(p, skb, &vid)) +- br_fdb_update(p->br, p, eth_hdr(skb)->h_source, vid, false); ++ /* check if vlan is allowed, to avoid spoofing */ ++ if (p->flags & BR_LEARNING && br_should_learn(p, skb, &vid)) ++ br_fdb_update(p->br, p, eth_hdr(skb)->h_source, vid, false); ++ } + return 0; /* process further */ + } + +@@ -285,6 +287,18 @@ rx_handler_result_t br_handle_frame(stru + + forward: + switch (p->state) { ++ case BR_STATE_DISABLED: ++ if (ether_addr_equal(p->br->dev->dev_addr, dest)) ++ skb->pkt_type = PACKET_HOST; ++ ++ if (NF_HOOK(NFPROTO_BRIDGE, NF_BR_PRE_ROUTING, skb, skb->dev, NULL, ++ br_handle_local_finish)) ++ break; ++ ++ BR_INPUT_SKB_CB(skb)->brdev = p->br->dev; ++ br_pass_frame_up(skb); ++ break; ++ + case BR_STATE_FORWARDING: + rhook = rcu_dereference(br_should_route_hook); + if (rhook) { diff --git a/target/linux/generic/patches-4.0/130-MIPS-kernel-fix-sched_getaffinity-with-MT-FPAFF-enab.patch b/target/linux/generic/patches-4.0/130-MIPS-kernel-fix-sched_getaffinity-with-MT-FPAFF-enab.patch new file mode 100644 index 0000000..a7bfef3 --- /dev/null +++ b/target/linux/generic/patches-4.0/130-MIPS-kernel-fix-sched_getaffinity-with-MT-FPAFF-enab.patch @@ -0,0 +1,35 @@ +From: Felix Fietkau +Date: Sun, 19 Jul 2015 00:21:57 +0200 +Subject: [PATCH] MIPS: kernel: fix sched_getaffinity with MT FPAFF enabled + +p->thread.user_cpus_allowed is zero-initialized and is only filled on +the first sched_setaffinity call. + +To avoid adding overhead in the task initialization codepath, simply OR +the returned mask in sched_getaffinity with p->cpus_allowed. + +Cc: stable@vger.kernel.org +Signed-off-by: Felix Fietkau +--- + +--- a/arch/mips/kernel/mips-mt-fpaff.c ++++ b/arch/mips/kernel/mips-mt-fpaff.c +@@ -154,7 +154,7 @@ asmlinkage long mipsmt_sys_sched_getaffi + unsigned long __user *user_mask_ptr) + { + unsigned int real_len; +- cpumask_t mask; ++ cpumask_t allowed, mask; + int retval; + struct task_struct *p; + +@@ -173,7 +173,8 @@ asmlinkage long mipsmt_sys_sched_getaffi + if (retval) + goto out_unlock; + +- cpumask_and(&mask, &p->thread.user_cpus_allowed, cpu_possible_mask); ++ cpumask_or(&allowed, &p->thread.user_cpus_allowed, &p->cpus_allowed); ++ cpumask_and(&mask, &allowed, cpu_active_mask); + + out_unlock: + read_unlock(&tasklist_lock); diff --git a/target/linux/generic/patches-4.0/132-mips_inline_dma_ops.patch b/target/linux/generic/patches-4.0/132-mips_inline_dma_ops.patch new file mode 100644 index 0000000..eb12a28 --- /dev/null +++ b/target/linux/generic/patches-4.0/132-mips_inline_dma_ops.patch @@ -0,0 +1,693 @@ +From 2c58080407554e1bac8fd50d23cb02420524caed Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Mon, 12 Aug 2013 12:50:22 +0200 +Subject: [PATCH] MIPS: partially inline dma ops + +Several DMA ops are no-op on many platforms, and the indirection through +the mips_dma_map_ops function table is causing the compiler to emit +unnecessary code. + +Inlining visibly improves network performance in my tests (on a 24Kc +based system), and also slightly reduces code size of a few drivers. + +Signed-off-by: Felix Fietkau +--- + arch/mips/Kconfig | 4 + + arch/mips/include/asm/dma-mapping.h | 360 +++++++++++++++++++++++++++++++++++- + arch/mips/mm/dma-default.c | 163 ++-------------- + 3 files changed, 373 insertions(+), 154 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1526,6 +1526,7 @@ config CPU_CAVIUM_OCTEON + select CPU_SUPPORTS_HUGEPAGES + select USB_EHCI_BIG_ENDIAN_MMIO + select MIPS_L1_CACHE_SHIFT_7 ++ select SYS_HAS_DMA_OPS + help + The Cavium Octeon processor is a highly integrated chip containing + many ethernet hardware widgets for networking tasks. The processor +@@ -1790,6 +1791,9 @@ config MIPS_MALTA_PM + bool + default y + ++config SYS_HAS_DMA_OPS ++ bool ++ + # + # CPU may reorder R->R, R->W, W->R, W->W + # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC +--- a/arch/mips/include/asm/dma-mapping.h ++++ b/arch/mips/include/asm/dma-mapping.h +@@ -1,9 +1,16 @@ + #ifndef _ASM_DMA_MAPPING_H + #define _ASM_DMA_MAPPING_H + ++#include ++#include ++#include ++#include ++#include ++ + #include + #include + #include ++#include + #include + + #ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */ +@@ -12,12 +19,48 @@ + + extern struct dma_map_ops *mips_dma_map_ops; + ++void __dma_sync(struct page *page, unsigned long offset, size_t size, ++ enum dma_data_direction direction); ++void *mips_dma_alloc_coherent(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp, ++ struct dma_attrs *attrs); ++void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, ++ dma_addr_t dma_handle, struct dma_attrs *attrs); ++ + static inline struct dma_map_ops *get_dma_ops(struct device *dev) + { ++#ifdef CONFIG_SYS_HAS_DMA_OPS + if (dev && dev->archdata.dma_ops) + return dev->archdata.dma_ops; + else + return mips_dma_map_ops; ++#else ++ return NULL; ++#endif ++} ++ ++/* ++ * Warning on the terminology - Linux calls an uncached area coherent; ++ * MIPS terminology calls memory areas with hardware maintained coherency ++ * coherent. ++ */ ++ ++static inline int cpu_needs_post_dma_flush(struct device *dev) ++{ ++#ifndef CONFIG_SYS_HAS_CPU_R10000 ++ return 0; ++#endif ++ return !plat_device_is_coherent(dev) && ++ (boot_cpu_type() == CPU_R10000 || ++ boot_cpu_type() == CPU_R12000 || ++ boot_cpu_type() == CPU_BMIPS5000); ++} ++ ++static inline struct page *dma_addr_to_page(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return pfn_to_page( ++ plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); + } + + static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) +@@ -30,12 +73,304 @@ static inline bool dma_capable(struct de + + static inline void dma_mark_clean(void *addr, size_t size) {} + +-#include ++static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr, ++ size_t size, ++ enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ unsigned long offset = (unsigned long)ptr & ~PAGE_MASK; ++ struct page *page = virt_to_page(ptr); ++ dma_addr_t addr; ++ ++ kmemcheck_mark_initialized(ptr, size); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ addr = ops->map_page(dev, page, offset, size, dir, attrs); ++ } else { ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, offset, size, dir); ++ ++ addr = plat_map_dma_mem_page(dev, page) + offset; ++ } ++ debug_dma_map_page(dev, page, offset, size, dir, addr, true); ++ return addr; ++} ++ ++static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr, ++ size_t size, ++ enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->unmap_page(dev, addr, size, dir, attrs); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ ++ plat_unmap_dma_mem(dev, addr, size, dir); ++ } ++ debug_dma_unmap_page(dev, addr, size, dir, true); ++} ++ ++static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, ++ int nents, enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ int i, ents; ++ struct scatterlist *s; ++ ++ for_each_sg(sg, s, nents, i) ++ kmemcheck_mark_initialized(sg_virt(s), s->length); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ents = ops->map_sg(dev, sg, nents, dir, attrs); ++ } else { ++ for_each_sg(sg, s, nents, i) { ++ struct page *page = sg_page(s); ++ ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, s->offset, s->length, dir); ++#ifdef CONFIG_NEED_SG_DMA_LENGTH ++ s->dma_length = s->length; ++#endif ++ s->dma_address = ++ plat_map_dma_mem_page(dev, page) + s->offset; ++ } ++ ents = nents; ++ } ++ debug_dma_map_sg(dev, sg, nents, ents, dir); ++ ++ return ents; ++} ++ ++static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, ++ int nents, enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ debug_dma_unmap_sg(dev, sg, nents, dir); ++ if (ops) { ++ ops->unmap_sg(dev, sg, nents, dir, attrs); ++ return; ++ } ++ ++ for_each_sg(sg, s, nents, i) { ++ if (!plat_device_is_coherent(dev) && dir != DMA_TO_DEVICE) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ plat_unmap_dma_mem(dev, s->dma_address, s->length, dir); ++ } ++} ++ ++static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, ++ size_t offset, size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ dma_addr_t addr; ++ ++ kmemcheck_mark_initialized(page_address(page) + offset, size); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ addr = ops->map_page(dev, page, offset, size, dir, NULL); ++ } else { ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, offset, size, dir); ++ ++ addr = plat_map_dma_mem_page(dev, page) + offset; ++ } ++ debug_dma_map_page(dev, page, offset, size, dir, addr, false); ++ ++ return addr; ++} ++ ++static inline void dma_unmap_page(struct device *dev, dma_addr_t addr, ++ size_t size, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->unmap_page(dev, addr, size, dir, NULL); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ ++ plat_unmap_dma_mem(dev, addr, size, dir); ++ } ++ debug_dma_unmap_page(dev, addr, size, dir, false); ++} ++ ++static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_cpu(dev, addr, size, dir); ++ else if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_for_cpu(dev, addr, size, dir); ++} ++ ++static inline void dma_sync_single_for_device(struct device *dev, ++ dma_addr_t addr, size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_device(dev, addr, size, dir); ++ else if (!plat_device_is_coherent(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_for_device(dev, addr, size, dir); ++} ++ ++static inline void dma_sync_single_range_for_cpu(struct device *dev, ++ dma_addr_t addr, ++ unsigned long offset, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ const struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_cpu(dev, addr + offset, size, dir); ++ else if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr + offset), ++ (addr + offset) & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_range_for_cpu(dev, addr, offset, size, dir); ++} ++ ++static inline void dma_sync_single_range_for_device(struct device *dev, ++ dma_addr_t addr, ++ unsigned long offset, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ const struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_device(dev, addr + offset, size, dir); ++ else if (!plat_device_is_coherent(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr + offset), ++ (addr + offset) & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_range_for_device(dev, addr, offset, size, dir); ++} ++ ++static inline void ++dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, ++ int nelems, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_sg_for_cpu(dev, sg, nelems, dir); ++ else if (cpu_needs_post_dma_flush(dev)) { ++ for_each_sg(sg, s, nelems, i) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ } ++ debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); ++} ++ ++static inline void ++dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, ++ int nelems, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_sg_for_device(dev, sg, nelems, dir); ++ else if (!plat_device_is_coherent(dev)) { ++ for_each_sg(sg, s, nelems, i) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ } ++ debug_dma_sync_sg_for_device(dev, sg, nelems, dir); ++ ++} ++ ++#define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, NULL) ++#define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, NULL) ++#define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, NULL) ++#define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, NULL) ++ ++extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, ++ void *cpu_addr, dma_addr_t dma_addr, size_t size); ++ ++/** ++ * dma_mmap_attrs - map a coherent DMA allocation into user space ++ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices ++ * @vma: vm_area_struct describing requested user mapping ++ * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs ++ * @handle: device-view address returned from dma_alloc_attrs ++ * @size: size of memory originally requested in dma_alloc_attrs ++ * @attrs: attributes of mapping properties requested in dma_alloc_attrs ++ * ++ * Map a coherent DMA buffer previously allocated by dma_alloc_attrs ++ * into user space. The coherent DMA buffer must not be freed by the ++ * driver until the user space mapping has been released. ++ */ ++static inline int ++dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, ++ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ BUG_ON(!ops); ++ if (ops && ops->mmap) ++ return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); ++ return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size); ++} ++ ++#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL) ++ ++int ++dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, ++ void *cpu_addr, dma_addr_t dma_addr, size_t size); ++ ++static inline int ++dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, ++ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ BUG_ON(!ops); ++ if (ops && ops->get_sgtable) ++ return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, ++ attrs); ++ return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size); ++} ++ ++#define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, NULL) ++ + + static inline int dma_supported(struct device *dev, u64 mask) + { + struct dma_map_ops *ops = get_dma_ops(dev); +- return ops->dma_supported(dev, mask); ++ if (ops) ++ return ops->dma_supported(dev, mask); ++ return plat_dma_supported(dev, mask); + } + + static inline int dma_mapping_error(struct device *dev, u64 mask) +@@ -43,7 +378,9 @@ static inline int dma_mapping_error(stru + struct dma_map_ops *ops = get_dma_ops(dev); + + debug_dma_mapping_error(dev, mask); +- return ops->mapping_error(dev, mask); ++ if (ops) ++ return ops->mapping_error(dev, mask); ++ return 0; + } + + static inline int +@@ -54,7 +391,7 @@ dma_set_mask(struct device *dev, u64 mas + if(!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + +- if (ops->set_dma_mask) ++ if (ops && ops->set_dma_mask) + return ops->set_dma_mask(dev, mask); + + *dev->dma_mask = mask; +@@ -74,7 +411,11 @@ static inline void *dma_alloc_attrs(stru + void *ret; + struct dma_map_ops *ops = get_dma_ops(dev); + +- ret = ops->alloc(dev, size, dma_handle, gfp, attrs); ++ if (ops) ++ ret = ops->alloc(dev, size, dma_handle, gfp, attrs); ++ else ++ ret = mips_dma_alloc_coherent(dev, size, dma_handle, gfp, ++ attrs); + + debug_dma_alloc_coherent(dev, size, *dma_handle, ret); + +@@ -89,7 +430,10 @@ static inline void dma_free_attrs(struct + { + struct dma_map_ops *ops = get_dma_ops(dev); + +- ops->free(dev, size, vaddr, dma_handle, attrs); ++ if (ops) ++ ops->free(dev, size, vaddr, dma_handle, attrs); ++ else ++ mips_dma_free_coherent(dev, size, vaddr, dma_handle, attrs); + + debug_dma_free_coherent(dev, size, vaddr, dma_handle); + } +--- a/arch/mips/mm/dma-default.c ++++ b/arch/mips/mm/dma-default.c +@@ -26,7 +26,7 @@ + + #ifdef CONFIG_DMA_MAYBE_COHERENT + int coherentio = 0; /* User defined DMA coherency from command line. */ +-EXPORT_SYMBOL_GPL(coherentio); ++EXPORT_SYMBOL(coherentio); + int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ + + static int __init setcoherentio(char *str) +@@ -46,35 +46,6 @@ static int __init setnocoherentio(char * + early_param("nocoherentio", setnocoherentio); + #endif + +-static inline struct page *dma_addr_to_page(struct device *dev, +- dma_addr_t dma_addr) +-{ +- return pfn_to_page( +- plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); +-} +- +-/* +- * The affected CPUs below in 'cpu_needs_post_dma_flush()' can +- * speculatively fill random cachelines with stale data at any time, +- * requiring an extra flush post-DMA. +- * +- * Warning on the terminology - Linux calls an uncached area coherent; +- * MIPS terminology calls memory areas with hardware maintained coherency +- * coherent. +- * +- * Note that the R14000 and R16000 should also be checked for in this +- * condition. However this function is only called on non-I/O-coherent +- * systems and only the R10000 and R12000 are used in such systems, the +- * SGI IP28 Indigo² rsp. SGI IP32 aka O2. +- */ +-static inline int cpu_needs_post_dma_flush(struct device *dev) +-{ +- return !plat_device_is_coherent(dev) && +- (boot_cpu_type() == CPU_R10000 || +- boot_cpu_type() == CPU_R12000 || +- boot_cpu_type() == CPU_BMIPS5000); +-} +- + static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) + { + gfp_t dma_flag; +@@ -130,8 +101,9 @@ void *dma_alloc_noncoherent(struct devic + } + EXPORT_SYMBOL(dma_alloc_noncoherent); + +-static void *mips_dma_alloc_coherent(struct device *dev, size_t size, +- dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) ++void *mips_dma_alloc_coherent(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp, ++ struct dma_attrs *attrs) + { + void *ret; + struct page *page = NULL; +@@ -162,6 +134,7 @@ static void *mips_dma_alloc_coherent(str + + return ret; + } ++EXPORT_SYMBOL(mips_dma_alloc_coherent); + + + void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, +@@ -172,8 +145,8 @@ void dma_free_noncoherent(struct device + } + EXPORT_SYMBOL(dma_free_noncoherent); + +-static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, +- dma_addr_t dma_handle, struct dma_attrs *attrs) ++void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, ++ dma_addr_t dma_handle, struct dma_attrs *attrs) + { + unsigned long addr = (unsigned long) vaddr; + int order = get_order(size); +@@ -193,6 +166,7 @@ static void mips_dma_free_coherent(struc + if (!dma_release_from_contiguous(dev, page, count)) + __free_pages(page, get_order(size)); + } ++EXPORT_SYMBOL(mips_dma_free_coherent); + + static inline void __dma_sync_virtual(void *addr, size_t size, + enum dma_data_direction direction) +@@ -221,8 +195,8 @@ static inline void __dma_sync_virtual(vo + * If highmem is not configured then the bulk of this loop gets + * optimized out. + */ +-static inline void __dma_sync(struct page *page, +- unsigned long offset, size_t size, enum dma_data_direction direction) ++void __dma_sync(struct page *page, unsigned long offset, size_t size, ++ enum dma_data_direction direction) + { + size_t left = size; + +@@ -251,108 +225,7 @@ static inline void __dma_sync(struct pag + left -= len; + } while (left); + } +- +-static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, +- size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) +-{ +- if (cpu_needs_post_dma_flush(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_addr), +- dma_addr & ~PAGE_MASK, size, direction); +- +- plat_unmap_dma_mem(dev, dma_addr, size, direction); +-} +- +-static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg, +- int nents, enum dma_data_direction direction, struct dma_attrs *attrs) +-{ +- int i; +- +- for (i = 0; i < nents; i++, sg++) { +- if (!plat_device_is_coherent(dev)) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-#ifdef CONFIG_NEED_SG_DMA_LENGTH +- sg->dma_length = sg->length; +-#endif +- sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + +- sg->offset; +- } +- +- return nents; +-} +- +-static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page, +- unsigned long offset, size_t size, enum dma_data_direction direction, +- struct dma_attrs *attrs) +-{ +- if (!plat_device_is_coherent(dev)) +- __dma_sync(page, offset, size, direction); +- +- return plat_map_dma_mem_page(dev, page) + offset; +-} +- +-static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg, +- int nhwentries, enum dma_data_direction direction, +- struct dma_attrs *attrs) +-{ +- int i; +- +- for (i = 0; i < nhwentries; i++, sg++) { +- if (!plat_device_is_coherent(dev) && +- direction != DMA_TO_DEVICE) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +- plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction); +- } +-} +- +-static void mips_dma_sync_single_for_cpu(struct device *dev, +- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +-{ +- if (cpu_needs_post_dma_flush(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_handle), +- dma_handle & ~PAGE_MASK, size, direction); +-} +- +-static void mips_dma_sync_single_for_device(struct device *dev, +- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +-{ +- if (!plat_device_is_coherent(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_handle), +- dma_handle & ~PAGE_MASK, size, direction); +-} +- +-static void mips_dma_sync_sg_for_cpu(struct device *dev, +- struct scatterlist *sg, int nelems, enum dma_data_direction direction) +-{ +- int i; +- +- if (cpu_needs_post_dma_flush(dev)) +- for (i = 0; i < nelems; i++, sg++) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-} +- +-static void mips_dma_sync_sg_for_device(struct device *dev, +- struct scatterlist *sg, int nelems, enum dma_data_direction direction) +-{ +- int i; +- +- if (!plat_device_is_coherent(dev)) +- for (i = 0; i < nelems; i++, sg++) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-} +- +-int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +-{ +- return 0; +-} +- +-int mips_dma_supported(struct device *dev, u64 mask) +-{ +- return plat_dma_supported(dev, mask); +-} ++EXPORT_SYMBOL(__dma_sync); + + void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) +@@ -365,23 +238,10 @@ void dma_cache_sync(struct device *dev, + + EXPORT_SYMBOL(dma_cache_sync); + +-static struct dma_map_ops mips_default_dma_map_ops = { +- .alloc = mips_dma_alloc_coherent, +- .free = mips_dma_free_coherent, +- .map_page = mips_dma_map_page, +- .unmap_page = mips_dma_unmap_page, +- .map_sg = mips_dma_map_sg, +- .unmap_sg = mips_dma_unmap_sg, +- .sync_single_for_cpu = mips_dma_sync_single_for_cpu, +- .sync_single_for_device = mips_dma_sync_single_for_device, +- .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu, +- .sync_sg_for_device = mips_dma_sync_sg_for_device, +- .mapping_error = mips_dma_mapping_error, +- .dma_supported = mips_dma_supported +-}; +- +-struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops; ++#ifdef CONFIG_SYS_HAS_DMA_OPS ++struct dma_map_ops *mips_dma_map_ops = NULL; + EXPORT_SYMBOL(mips_dma_map_ops); ++#endif + + #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) + diff --git a/target/linux/generic/patches-4.0/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch b/target/linux/generic/patches-4.0/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch new file mode 100644 index 0000000..d8f25ac --- /dev/null +++ b/target/linux/generic/patches-4.0/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch @@ -0,0 +1,58 @@ +From 71a0a72456b48de972d7ed613b06a22a3aa9057f Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 26 Sep 2015 13:41:43 +0800 +Subject: [PATCH] MIPS: UAPI: Ignore __arch_swab{16,32,64} when using MIPS16 + +Some GCC versions (e.g. 4.8.3) can incorrectly inline a function with +MIPS32 instructions into another function with MIPS16 code [1], causing +the assembler to genereate incorrect binary code or fail right away +complaining about unrecognized opcode. + +In the case of __arch_swab{16,32}, when inlined by the compiler with +flags `-mips32r2 -mips16 -Os', the assembler can fail with the following +error. + + {standard input}:79: Error: unrecognized opcode `wsbh $2,$2' + +For performance concerns and to workaround the issue already existing in +older compilers, just ignore these 2 functions when compiling with +mips16 enabled. + + [1] Inlining nomips16 function into mips16 function can result in + undefined builtins, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55777 + +Signed-off-by: Yousong Zhou +Cc: Maciej W. Rozycki +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/11241/ +Signed-off-by: Ralf Baechle +--- + arch/mips/include/uapi/asm/swab.h | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h +index 8f2d184..23cd9b1 100644 +--- a/arch/mips/include/uapi/asm/swab.h ++++ b/arch/mips/include/uapi/asm/swab.h +@@ -13,8 +13,9 @@ + + #define __SWAB_64_THRU_32__ + +-#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ +- defined(_MIPS_ARCH_LOONGSON3A) ++#if !defined(__mips16) && \ ++ ((defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ ++ defined(_MIPS_ARCH_LOONGSON3A)) + + static inline __attribute_const__ __u16 __arch_swab16(__u16 x) + { +@@ -65,5 +66,5 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x) + } + #define __arch_swab64 __arch_swab64 + #endif /* __mips64 */ +-#endif /* MIPS R2 or newer or Loongson 3A */ ++#endif /* (not __mips16) and (MIPS R2 or newer or Loongson 3A) */ + #endif /* _ASM_SWAB_H */ +-- +1.7.10.4 + diff --git a/target/linux/generic/patches-4.0/140-overlayfs_readdir_locking_fix.patch b/target/linux/generic/patches-4.0/140-overlayfs_readdir_locking_fix.patch new file mode 100644 index 0000000..67dff98 --- /dev/null +++ b/target/linux/generic/patches-4.0/140-overlayfs_readdir_locking_fix.patch @@ -0,0 +1,148 @@ +Patch by: Miklos Szeredi + +Some filesystems (e.g. jffs2) lock the same resources for both readdir +and lookup, leading to a deadlock in ovl_cache_entry_new, which is called +from the filldir, and calls lookup itself. + +--- a/fs/overlayfs/readdir.c ++++ b/fs/overlayfs/readdir.c +@@ -23,6 +23,7 @@ struct ovl_cache_entry { + u64 ino; + struct list_head l_node; + struct rb_node node; ++ struct ovl_cache_entry *next_maybe_whiteout; + bool is_whiteout; + char name[]; + }; +@@ -39,7 +40,7 @@ struct ovl_readdir_data { + struct rb_root root; + struct list_head *list; + struct list_head middle; +- struct dentry *dir; ++ struct ovl_cache_entry *first_maybe_whiteout; + int count; + int err; + }; +@@ -79,7 +80,7 @@ static struct ovl_cache_entry *ovl_cache + return NULL; + } + +-static struct ovl_cache_entry *ovl_cache_entry_new(struct dentry *dir, ++static struct ovl_cache_entry *ovl_cache_entry_new(struct ovl_readdir_data *rdd, + const char *name, int len, + u64 ino, unsigned int d_type) + { +@@ -98,29 +99,8 @@ static struct ovl_cache_entry *ovl_cache + p->is_whiteout = false; + + if (d_type == DT_CHR) { +- struct dentry *dentry; +- const struct cred *old_cred; +- struct cred *override_cred; +- +- override_cred = prepare_creds(); +- if (!override_cred) { +- kfree(p); +- return NULL; +- } +- +- /* +- * CAP_DAC_OVERRIDE for lookup +- */ +- cap_raise(override_cred->cap_effective, CAP_DAC_OVERRIDE); +- old_cred = override_creds(override_cred); +- +- dentry = lookup_one_len(name, dir, len); +- if (!IS_ERR(dentry)) { +- p->is_whiteout = ovl_is_whiteout(dentry); +- dput(dentry); +- } +- revert_creds(old_cred); +- put_cred(override_cred); ++ p->next_maybe_whiteout = rdd->first_maybe_whiteout; ++ rdd->first_maybe_whiteout = p; + } + return p; + } +@@ -148,7 +128,7 @@ static int ovl_cache_entry_add_rb(struct + return 0; + } + +- p = ovl_cache_entry_new(rdd->dir, name, len, ino, d_type); ++ p = ovl_cache_entry_new(rdd, name, len, ino, d_type); + if (p == NULL) + return -ENOMEM; + +@@ -169,7 +149,7 @@ static int ovl_fill_lower(struct ovl_rea + if (p) { + list_move_tail(&p->l_node, &rdd->middle); + } else { +- p = ovl_cache_entry_new(rdd->dir, name, namelen, ino, d_type); ++ p = ovl_cache_entry_new(rdd, name, namelen, ino, d_type); + if (p == NULL) + rdd->err = -ENOMEM; + else +@@ -219,6 +199,43 @@ static int ovl_fill_merge(struct dir_con + return ovl_fill_lower(rdd, name, namelen, offset, ino, d_type); + } + ++static int ovl_check_whiteouts(struct dentry *dir, struct ovl_readdir_data *rdd) ++{ ++ int err = 0; ++ ++ mutex_lock(&dir->d_inode->i_mutex); ++ while (rdd->first_maybe_whiteout) { ++ struct dentry *dentry; ++ const struct cred *old_cred; ++ struct cred *override_cred; ++ struct ovl_cache_entry *p = rdd->first_maybe_whiteout; ++ ++ rdd->first_maybe_whiteout = p->next_maybe_whiteout; ++ ++ override_cred = prepare_creds(); ++ if (!override_cred) { ++ err = -ENOMEM; ++ break; ++ } ++ /* ++ * CAP_DAC_OVERRIDE for lookup ++ */ ++ cap_raise(override_cred->cap_effective, CAP_DAC_OVERRIDE); ++ old_cred = override_creds(override_cred); ++ ++ dentry = lookup_one_len(p->name, dir, p->len); ++ if (!IS_ERR(dentry)) { ++ p->is_whiteout = ovl_is_whiteout(dentry); ++ dput(dentry); ++ } ++ revert_creds(old_cred); ++ put_cred(override_cred); ++ } ++ mutex_unlock(&dir->d_inode->i_mutex); ++ ++ return err; ++} ++ + static inline int ovl_dir_read(struct path *realpath, + struct ovl_readdir_data *rdd) + { +@@ -229,7 +246,7 @@ static inline int ovl_dir_read(struct pa + if (IS_ERR(realfile)) + return PTR_ERR(realfile); + +- rdd->dir = realpath->dentry; ++ rdd->first_maybe_whiteout = NULL; + rdd->ctx.pos = 0; + do { + rdd->count = 0; +@@ -238,6 +255,10 @@ static inline int ovl_dir_read(struct pa + if (err >= 0) + err = rdd->err; + } while (!err && rdd->count); ++ ++ if (!err && rdd->first_maybe_whiteout) ++ err = ovl_check_whiteouts(realpath->dentry, rdd); ++ + fput(realfile); + + return err; diff --git a/target/linux/generic/patches-4.0/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch b/target/linux/generic/patches-4.0/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch new file mode 100644 index 0000000..a17e398 --- /dev/null +++ b/target/linux/generic/patches-4.0/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch @@ -0,0 +1,41 @@ +From 9612e686b235dc9e33c8dfb5e6d2ff2b2140fb9d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 21:01:30 +0200 +Subject: [PATCH V2] usb: xhci: make USB_XHCI_PLATFORM selectable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Right now xhci-plat-hcd can be built when using one of platform specific +drivers only (mvebu/rcar). There shouldn't be such limitation as some +platforms may not require any quirks and may want to just use a generic +driver ("generic-xhci" / "xhci-hcd"). + +Signed-off-by: Rafał Miłecki +--- +Greg/Mathias: I'm not sure if it's more like USB subsystem stuff or xHCI +Could you decide which one of you could pick that, please? + +V2: Drop useless "default n", thanks Sergei :) +--- + drivers/usb/host/Kconfig | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -32,7 +32,14 @@ config USB_XHCI_PCI + default y + + config USB_XHCI_PLATFORM +- tristate ++ tristate "Generic xHCI driver for a platform device" ++ ---help--- ++ Adds an xHCI host driver for a generic platform device, which ++ provides a memory space and an irq. ++ It is also a prerequisite for platform specific drivers that ++ implement some extra quirks. ++ ++ If unsure, say N. + + config USB_XHCI_MVEBU + tristate "xHCI support for Marvell Armada 375/38x" diff --git a/target/linux/generic/patches-4.0/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch b/target/linux/generic/patches-4.0/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch new file mode 100644 index 0000000..09cbe0c --- /dev/null +++ b/target/linux/generic/patches-4.0/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch @@ -0,0 +1,228 @@ +From 4a0e3e989d66bb7204b163d9cfaa7fa96d0f2023 Mon Sep 17 00:00:00 2001 +From: Enrico Mioso +Date: Wed, 8 Jul 2015 13:05:57 +0200 +Subject: [PATCH] cdc_ncm: Add support for moving NDP to end of NCM frame + +NCM specs are not actually mandating a specific position in the frame for +the NDP (Network Datagram Pointer). However, some Huawei devices will +ignore our aggregates if it is not placed after the datagrams it points +to. Add support for doing just this, in a per-device configurable way. +While at it, update NCM subdrivers, disabling this functionality in all of +them, except in huawei_cdc_ncm where it is enabled instead. +We aren't making any distinction between different Huawei NCM devices, +based on what the vendor driver does. Standard NCM devices are left +unaffected: if they are compliant, they should be always usable, still +stay on the safe side. + +This change has been tested and working with a Huawei E3131 device (which +works regardless of NDP position), a Huawei E3531 (also working both +ways) and an E3372 (which mandates NDP to be after indexed datagrams). + +V1->V2: +- corrected wrong NDP acronym definition +- fixed possible NULL pointer dereference +- patch cleanup +V2->V3: +- Properly account for the NDP size when writing new packets to SKB + +Signed-off-by: Enrico Mioso +Signed-off-by: David S. Miller +--- + drivers/net/usb/cdc_mbim.c | 2 +- + drivers/net/usb/cdc_ncm.c | 61 ++++++++++++++++++++++++++++++++++++---- + drivers/net/usb/huawei_cdc_ncm.c | 7 +++-- + include/linux/usb/cdc_ncm.h | 7 ++++- + 4 files changed, 67 insertions(+), 10 deletions(-) + +--- a/drivers/net/usb/cdc_mbim.c ++++ b/drivers/net/usb/cdc_mbim.c +@@ -158,7 +158,7 @@ static int cdc_mbim_bind(struct usbnet * + if (!cdc_ncm_comm_intf_is_mbim(intf->cur_altsetting)) + goto err; + +- ret = cdc_ncm_bind_common(dev, intf, data_altsetting); ++ ret = cdc_ncm_bind_common(dev, intf, data_altsetting, 0); + if (ret) + goto err; + +--- a/drivers/net/usb/cdc_ncm.c ++++ b/drivers/net/usb/cdc_ncm.c +@@ -684,10 +684,12 @@ static void cdc_ncm_free(struct cdc_ncm_ + ctx->tx_curr_skb = NULL; + } + ++ kfree(ctx->delayed_ndp16); ++ + kfree(ctx); + } + +-int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting) ++int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting, int drvflags) + { + const struct usb_cdc_union_desc *union_desc = NULL; + struct cdc_ncm_ctx *ctx; +@@ -855,6 +857,17 @@ advance: + /* finish setting up the device specific data */ + cdc_ncm_setup(dev); + ++ /* Device-specific flags */ ++ ctx->drvflags = drvflags; ++ ++ /* Allocate the delayed NDP if needed. */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { ++ ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); ++ if (!ctx->delayed_ndp16) ++ goto error2; ++ dev_info(&intf->dev, "NDP will be placed at end of frame for this device."); ++ } ++ + /* override ethtool_ops */ + dev->net->ethtool_ops = &cdc_ncm_ethtool_ops; + +@@ -954,8 +967,11 @@ static int cdc_ncm_bind(struct usbnet *d + if (cdc_ncm_select_altsetting(intf) != CDC_NCM_COMM_ALTSETTING_NCM) + return -ENODEV; + +- /* The NCM data altsetting is fixed */ +- ret = cdc_ncm_bind_common(dev, intf, CDC_NCM_DATA_ALTSETTING_NCM); ++ /* The NCM data altsetting is fixed, so we hard-coded it. ++ * Additionally, generic NCM devices are assumed to accept arbitrarily ++ * placed NDP. ++ */ ++ ret = cdc_ncm_bind_common(dev, intf, CDC_NCM_DATA_ALTSETTING_NCM, 0); + + /* + * We should get an event when network connection is "connected" or +@@ -986,6 +1002,14 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + struct usb_cdc_ncm_nth16 *nth16 = (void *)skb->data; + size_t ndpoffset = le16_to_cpu(nth16->wNdpIndex); + ++ /* If NDP should be moved to the end of the NCM package, we can't follow the ++ * NTH16 header as we would normally do. NDP isn't written to the SKB yet, and ++ * the wNdpIndex field in the header is actually not consistent with reality. It will be later. ++ */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) ++ if (ctx->delayed_ndp16->dwSignature == sign) ++ return ctx->delayed_ndp16; ++ + /* follow the chain of NDPs, looking for a match */ + while (ndpoffset) { + ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb->data + ndpoffset); +@@ -995,7 +1019,8 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + } + + /* align new NDP */ +- cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_max); ++ if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) ++ cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_max); + + /* verify that there is room for the NDP and the datagram (reserve) */ + if ((ctx->tx_max - skb->len - reserve) < ctx->max_ndp_size) +@@ -1008,7 +1033,11 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + nth16->wNdpIndex = cpu_to_le16(skb->len); + + /* push a new empty NDP */ +- ndp16 = (struct usb_cdc_ncm_ndp16 *)memset(skb_put(skb, ctx->max_ndp_size), 0, ctx->max_ndp_size); ++ if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) ++ ndp16 = (struct usb_cdc_ncm_ndp16 *)memset(skb_put(skb, ctx->max_ndp_size), 0, ctx->max_ndp_size); ++ else ++ ndp16 = ctx->delayed_ndp16; ++ + ndp16->dwSignature = sign; + ndp16->wLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_ndp16) + sizeof(struct usb_cdc_ncm_dpe16)); + return ndp16; +@@ -1023,6 +1052,15 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + struct sk_buff *skb_out; + u16 n = 0, index, ndplen; + u8 ready2send = 0; ++ u32 delayed_ndp_size; ++ ++ /* When our NDP gets written in cdc_ncm_ndp(), then skb_out->len gets updated ++ * accordingly. Otherwise, we should check here. ++ */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) ++ delayed_ndp_size = ctx->max_ndp_size; ++ else ++ delayed_ndp_size = 0; + + /* if there is a remaining skb, it gets priority */ + if (skb != NULL) { +@@ -1077,7 +1115,7 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + cdc_ncm_align_tail(skb_out, ctx->tx_modulus, ctx->tx_remainder, ctx->tx_max); + + /* check if we had enough room left for both NDP and frame */ +- if (!ndp16 || skb_out->len + skb->len > ctx->tx_max) { ++ if (!ndp16 || skb_out->len + skb->len + delayed_ndp_size > ctx->tx_max) { + if (n == 0) { + /* won't fit, MTU problem? */ + dev_kfree_skb_any(skb); +@@ -1150,6 +1188,17 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + /* variables will be reset at next call */ + } + ++ /* If requested, put NDP at end of frame. */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { ++ nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; ++ cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_max); ++ nth16->wNdpIndex = cpu_to_le16(skb_out->len); ++ memcpy(skb_put(skb_out, ctx->max_ndp_size), ctx->delayed_ndp16, ctx->max_ndp_size); ++ ++ /* Zero out delayed NDP - signature checking will naturally fail. */ ++ ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); ++ } ++ + /* If collected data size is less or equal ctx->min_tx_pkt + * bytes, we send buffers as it is. If we get more data, it + * would be more efficient for USB HS mobile device with DMA +--- a/drivers/net/usb/huawei_cdc_ncm.c ++++ b/drivers/net/usb/huawei_cdc_ncm.c +@@ -73,11 +73,14 @@ static int huawei_cdc_ncm_bind(struct us + struct usb_driver *subdriver = ERR_PTR(-ENODEV); + int ret = -ENODEV; + struct huawei_cdc_ncm_state *drvstate = (void *)&usbnet_dev->data; ++ int drvflags = 0; + + /* altsetting should always be 1 for NCM devices - so we hard-coded +- * it here ++ * it here. Some huawei devices will need the NDP part of the NCM package to ++ * be at the end of the frame. + */ +- ret = cdc_ncm_bind_common(usbnet_dev, intf, 1); ++ drvflags |= CDC_NCM_FLAG_NDP_TO_END; ++ ret = cdc_ncm_bind_common(usbnet_dev, intf, 1, drvflags); + if (ret) + goto err; + +--- a/include/linux/usb/cdc_ncm.h ++++ b/include/linux/usb/cdc_ncm.h +@@ -80,6 +80,9 @@ + #define CDC_NCM_TIMER_INTERVAL_MIN 5UL + #define CDC_NCM_TIMER_INTERVAL_MAX (U32_MAX / NSEC_PER_USEC) + ++/* Driver flags */ ++#define CDC_NCM_FLAG_NDP_TO_END 0x02 /* NDP is placed at end of frame */ ++ + #define cdc_ncm_comm_intf_is_mbim(x) ((x)->desc.bInterfaceSubClass == USB_CDC_SUBCLASS_MBIM && \ + (x)->desc.bInterfaceProtocol == USB_CDC_PROTO_NONE) + #define cdc_ncm_data_intf_is_mbim(x) ((x)->desc.bInterfaceProtocol == USB_CDC_MBIM_PROTO_NTB) +@@ -103,9 +106,11 @@ struct cdc_ncm_ctx { + + spinlock_t mtx; + atomic_t stop; ++ int drvflags; + + u32 timer_interval; + u32 max_ndp_size; ++ struct usb_cdc_ncm_ndp16 *delayed_ndp16; + + u32 tx_timer_pending; + u32 tx_curr_frame_num; +@@ -133,7 +138,7 @@ struct cdc_ncm_ctx { + }; + + u8 cdc_ncm_select_altsetting(struct usb_interface *intf); +-int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting); ++int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting, int drvflags); + void cdc_ncm_unbind(struct usbnet *dev, struct usb_interface *intf); + struct sk_buff *cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign); + int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); diff --git a/target/linux/generic/patches-4.0/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch b/target/linux/generic/patches-4.0/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch new file mode 100644 index 0000000..cda4ca0 --- /dev/null +++ b/target/linux/generic/patches-4.0/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch @@ -0,0 +1,35 @@ +From a95f03e51471dbdbafd3391991d867ac2358ed02 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 23 Aug 2015 14:23:29 +0200 +Subject: [PATCH] usb: ehci-orion: fix probe for !GENERIC_PHY + +Commit d445913ce0ab7f ("usb: ehci-orion: add optional PHY support") +added support for optional phys, but devm_phy_optional_get returns +-ENOSYS if GENERIC_PHY is not enabled. + +This causes probe failures, even when there are no phys specified: + +[ 1.443365] orion-ehci f1058000.usb: init f1058000.usb fail, -38 +[ 1.449403] orion-ehci: probe of f1058000.usb failed with error -38 + +Similar to dwc3, treat -ENOSYS as no phy. + +Fixes: d445913ce0ab7f ("usb: ehci-orion: add optional PHY support") + +Signed-off-by: Jonas Gorski +--- + drivers/usb/host/ehci-orion.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/ehci-orion.c ++++ b/drivers/usb/host/ehci-orion.c +@@ -218,7 +218,8 @@ static int ehci_orion_drv_probe(struct p + priv->phy = devm_phy_optional_get(&pdev->dev, "usb"); + if (IS_ERR(priv->phy)) { + err = PTR_ERR(priv->phy); +- goto err_phy_get; ++ if (err != -ENOSYS) ++ goto err_phy_get; + } else { + err = phy_init(priv->phy); + if (err) diff --git a/target/linux/generic/patches-4.0/200-fix_localversion.patch b/target/linux/generic/patches-4.0/200-fix_localversion.patch new file mode 100644 index 0000000..70228bb --- /dev/null +++ b/target/linux/generic/patches-4.0/200-fix_localversion.patch @@ -0,0 +1,11 @@ +--- a/scripts/setlocalversion ++++ b/scripts/setlocalversion +@@ -165,7 +165,7 @@ else + # annotated or signed tagged state (as git describe only + # looks at signed or annotated tags - git tag -a/-s) and + # LOCALVERSION= is not specified +- if test "${LOCALVERSION+set}" != "set"; then ++ if test "${CONFIG_LOCALVERSION+set}" != "set"; then + scm=$(scm_version --short) + res="$res${scm:++}" + fi diff --git a/target/linux/generic/patches-4.0/201-extra_optimization.patch b/target/linux/generic/patches-4.0/201-extra_optimization.patch new file mode 100644 index 0000000..a339826 --- /dev/null +++ b/target/linux/generic/patches-4.0/201-extra_optimization.patch @@ -0,0 +1,14 @@ +--- a/Makefile ++++ b/Makefile +@@ -614,9 +614,9 @@ include $(srctree)/arch/$(SRCARCH)/Makef + KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,) + + ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE +-KBUILD_CFLAGS += -Os $(call cc-disable-warning,maybe-uninitialized,) ++KBUILD_CFLAGS += -Os $(EXTRA_OPTIMIZATION) $(call cc-disable-warning,maybe-uninitialized,) + else +-KBUILD_CFLAGS += -O2 ++KBUILD_CFLAGS += -O2 -fno-reorder-blocks -fno-tree-ch $(EXTRA_OPTIMIZATION) + endif + + # Tell gcc to never replace conditional load with a non-conditional one diff --git a/target/linux/generic/patches-4.0/202-reduce_module_size.patch b/target/linux/generic/patches-4.0/202-reduce_module_size.patch new file mode 100644 index 0000000..3f36af8 --- /dev/null +++ b/target/linux/generic/patches-4.0/202-reduce_module_size.patch @@ -0,0 +1,11 @@ +--- a/Makefile ++++ b/Makefile +@@ -410,7 +410,7 @@ KBUILD_CFLAGS_KERNEL := + KBUILD_AFLAGS := -D__ASSEMBLY__ + KBUILD_AFLAGS_MODULE := -DMODULE + KBUILD_CFLAGS_MODULE := -DMODULE +-KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds ++KBUILD_LDFLAGS_MODULE = -T $(srctree)/scripts/module-common.lds $(if $(CONFIG_PROFILING),,-s) + + # Read KERNELRELEASE from include/config/kernel.release (if it exists) + KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) diff --git a/target/linux/generic/patches-4.0/203-kallsyms_uncompressed.patch b/target/linux/generic/patches-4.0/203-kallsyms_uncompressed.patch new file mode 100644 index 0000000..99f0ad2 --- /dev/null +++ b/target/linux/generic/patches-4.0/203-kallsyms_uncompressed.patch @@ -0,0 +1,108 @@ +--- a/scripts/kallsyms.c ++++ b/scripts/kallsyms.c +@@ -58,6 +58,7 @@ static struct addr_range percpu_range = + static struct sym_entry *table; + static unsigned int table_size, table_cnt; + static int all_symbols = 0; ++static int uncompressed = 0; + static int absolute_percpu = 0; + static char symbol_prefix_char = '\0'; + static unsigned long long kernel_start_addr = 0; +@@ -392,6 +393,9 @@ static void write_src(void) + + free(markers); + ++ if (uncompressed) ++ return; ++ + output_label("kallsyms_token_table"); + off = 0; + for (i = 0; i < 256; i++) { +@@ -450,6 +454,9 @@ static void *find_token(unsigned char *s + { + int i; + ++ if (uncompressed) ++ return NULL; ++ + for (i = 0; i < len - 1; i++) { + if (str[i] == token[0] && str[i+1] == token[1]) + return &str[i]; +@@ -522,6 +529,9 @@ static void optimize_result(void) + { + int i, best; + ++ if (uncompressed) ++ return; ++ + /* using the '\0' symbol last allows compress_symbols to use standard + * fast string functions */ + for (i = 255; i >= 0; i--) { +@@ -692,7 +702,9 @@ int main(int argc, char **argv) + } else if (strncmp(argv[i], "--page-offset=", 14) == 0) { + const char *p = &argv[i][14]; + kernel_start_addr = strtoull(p, NULL, 16); +- } else ++ } else if (strcmp(argv[i], "--uncompressed") == 0) ++ uncompressed = 1; ++ else + usage(); + } + } else if (argc != 1) +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1324,6 +1324,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW + the unaligned access emulation. + see arch/parisc/kernel/unaligned.c for reference + ++config KALLSYMS_UNCOMPRESSED ++ bool "Keep kallsyms uncompressed" ++ depends on KALLSYMS ++ help ++ Normally kallsyms contains compressed symbols (using a token table), ++ reducing the uncompressed kernel image size. Keeping the symbol table ++ uncompressed significantly improves the size of this part in compressed ++ kernel images. ++ ++ Say N unless you need compressed kernel images to be small. ++ + config HAVE_PCSPKR_PLATFORM + bool + +--- a/scripts/link-vmlinux.sh ++++ b/scripts/link-vmlinux.sh +@@ -90,6 +90,10 @@ kallsyms() + kallsymopt="${kallsymopt} --absolute-percpu" + fi + ++ if [ -n "${CONFIG_KALLSYMS_UNCOMPRESSED}" ]; then ++ kallsymopt="${kallsymopt} --uncompressed" ++ fi ++ + local aflags="${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL} \ + ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" + +--- a/kernel/kallsyms.c ++++ b/kernel/kallsyms.c +@@ -109,6 +109,11 @@ static unsigned int kallsyms_expand_symb + * For every byte on the compressed symbol data, copy the table + * entry for that byte. + */ ++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED ++ memcpy(result, data + 1, len - 1); ++ result += len - 1; ++ len = 0; ++#endif + while (len) { + tptr = &kallsyms_token_table[kallsyms_token_index[*data]]; + data++; +@@ -141,6 +146,9 @@ tail: + */ + static char kallsyms_get_symbol_type(unsigned int off) + { ++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED ++ return kallsyms_names[off + 1]; ++#endif + /* + * Get just the first code, look it up in the token table, + * and return the first char from this token. diff --git a/target/linux/generic/patches-4.0/204-module_strip.patch b/target/linux/generic/patches-4.0/204-module_strip.patch new file mode 100644 index 0000000..584839a --- /dev/null +++ b/target/linux/generic/patches-4.0/204-module_strip.patch @@ -0,0 +1,194 @@ +From: Felix Fietkau +Subject: [PATCH] build: add a hack for removing non-essential module info + +Signed-off-by: Felix Fietkau +--- +--- a/include/linux/module.h ++++ b/include/linux/module.h +@@ -84,9 +84,10 @@ void trim_init_extable(struct module *m) + + /* Generic info of form tag = "info" */ + #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info) ++#define MODULE_INFO_STRIP(tag, info) __MODULE_INFO_STRIP(tag, tag, info) + + /* For userspace: you can also call me... */ +-#define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias) ++#define MODULE_ALIAS(_alias) MODULE_INFO_STRIP(alias, _alias) + + /* Soft module dependencies. See man modprobe.d for details. + * Example: MODULE_SOFTDEP("pre: module-foo module-bar post: module-baz") +@@ -127,12 +128,12 @@ void trim_init_extable(struct module *m) + * Author(s), use "Name " or just "Name", for multiple + * authors use multiple MODULE_AUTHOR() statements/lines. + */ +-#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author) ++#define MODULE_AUTHOR(_author) MODULE_INFO_STRIP(author, _author) + + /* What your module does. */ +-#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description) ++#define MODULE_DESCRIPTION(_description) MODULE_INFO_STRIP(description, _description) + +-#ifdef MODULE ++#if defined(MODULE) && !defined(CONFIG_MODULE_STRIPPED) + /* Creates an alias so file2alias.c can find device table. */ + #define MODULE_DEVICE_TABLE(type, name) \ + extern const typeof(name) __mod_##type##__##name##_device_table \ +@@ -159,7 +160,9 @@ extern const typeof(name) __mod_##type## + */ + + #if defined(MODULE) || !defined(CONFIG_SYSFS) +-#define MODULE_VERSION(_version) MODULE_INFO(version, _version) ++#define MODULE_VERSION(_version) MODULE_INFO_STRIP(version, _version) ++#elif defined(CONFIG_MODULE_STRIPPED) ++#define MODULE_VERSION(_version) __MODULE_INFO_DISABLED(version) + #else + #define MODULE_VERSION(_version) \ + static struct module_version_attribute ___modver_attr = { \ +@@ -181,7 +184,7 @@ extern const typeof(name) __mod_##type## + /* Optional firmware file (or files) needed by the module + * format is simply firmware file name. Multiple firmware + * files require multiple MODULE_FIRMWARE() specifiers */ +-#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware) ++#define MODULE_FIRMWARE(_firmware) MODULE_INFO_STRIP(firmware, _firmware) + + /* Given an address, look for it in the exception tables */ + const struct exception_table_entry *search_exception_tables(unsigned long add); +--- a/include/linux/moduleparam.h ++++ b/include/linux/moduleparam.h +@@ -16,6 +16,16 @@ + /* Chosen so that structs with an unsigned long line up. */ + #define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long)) + ++/* This struct is here for syntactic coherency, it is not used */ ++#define __MODULE_INFO_DISABLED(name) \ ++ struct __UNIQUE_ID(name) {} ++ ++#ifdef CONFIG_MODULE_STRIPPED ++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO_DISABLED(name) ++#else ++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO(tag, name, info) ++#endif ++ + #ifdef MODULE + #define __MODULE_INFO(tag, name, info) \ + static const char __UNIQUE_ID(name)[] \ +@@ -23,8 +33,7 @@ static const char __UNIQUE_ID(name)[] + = __stringify(tag) "=" info + #else /* !MODULE */ + /* This struct is here for syntactic coherency, it is not used */ +-#define __MODULE_INFO(tag, name, info) \ +- struct __UNIQUE_ID(name) {} ++#define __MODULE_INFO(tag, name, info) __MODULE_INFO_DISABLED(name) + #endif + #define __MODULE_PARM_TYPE(name, _type) \ + __MODULE_INFO(parmtype, name##type, #name ":" _type) +@@ -32,7 +41,7 @@ static const char __UNIQUE_ID(name)[] + /* One for each parameter, describing how to use it. Some files do + multiple of these per line, so can't just use MODULE_INFO. */ + #define MODULE_PARM_DESC(_parm, desc) \ +- __MODULE_INFO(parm, _parm, #_parm ":" desc) ++ __MODULE_INFO_STRIP(parm, _parm, #_parm ":" desc) + + struct kernel_param; + +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1974,6 +1974,13 @@ config MODULE_COMPRESS_XZ + + endchoice + ++config MODULE_STRIPPED ++ bool "Reduce module size" ++ depends on MODULES ++ help ++ Remove module parameter descriptions, author info, version, aliases, ++ device tables, etc. ++ + endif # MODULES + + config INIT_ALL_POSSIBLE +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -2680,6 +2680,7 @@ static struct module *setup_load_info(st + + static int check_modinfo(struct module *mod, struct load_info *info, int flags) + { ++#ifndef CONFIG_MODULE_STRIPPED + const char *modmagic = get_modinfo(info, "vermagic"); + int err; + +@@ -2705,6 +2706,7 @@ static int check_modinfo(struct module * + pr_warn("%s: module is from the staging directory, the quality " + "is unknown, you have been warned.\n", mod->name); + } ++#endif + + /* Set up license info based on the info section */ + set_license(mod, get_modinfo(info, "license")); +--- a/scripts/mod/modpost.c ++++ b/scripts/mod/modpost.c +@@ -1726,7 +1726,9 @@ static void read_symbols(char *modname) + symname = remove_dot(info.strtab + sym->st_name); + + handle_modversions(mod, &info, sym, symname); ++#ifndef CONFIG_MODULE_STRIPPED + handle_moddevtable(mod, &info, sym, symname); ++#endif + } + if (!is_vmlinux(modname) || + (is_vmlinux(modname) && vmlinux_section_warnings)) +@@ -1870,7 +1872,9 @@ static void add_header(struct buffer *b, + buf_printf(b, "#include \n"); + buf_printf(b, "#include \n"); + buf_printf(b, "\n"); ++#ifndef CONFIG_MODULE_STRIPPED + buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n"); ++#endif + buf_printf(b, "\n"); + buf_printf(b, "__visible struct module __this_module\n"); + buf_printf(b, "__attribute__((section(\".gnu.linkonce.this_module\"))) = {\n"); +@@ -1887,16 +1891,20 @@ static void add_header(struct buffer *b, + + static void add_intree_flag(struct buffer *b, int is_intree) + { ++#ifndef CONFIG_MODULE_STRIPPED + if (is_intree) + buf_printf(b, "\nMODULE_INFO(intree, \"Y\");\n"); ++#endif + } + + static void add_staging_flag(struct buffer *b, const char *name) + { ++#ifndef CONFIG_MODULE_STRIPPED + static const char *staging_dir = "drivers/staging"; + + if (strncmp(staging_dir, name, strlen(staging_dir)) == 0) + buf_printf(b, "\nMODULE_INFO(staging, \"Y\");\n"); ++#endif + } + + /** +@@ -1989,11 +1997,13 @@ static void add_depends(struct buffer *b + + static void add_srcversion(struct buffer *b, struct module *mod) + { ++#ifndef CONFIG_MODULE_STRIPPED + if (mod->srcversion[0]) { + buf_printf(b, "\n"); + buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n", + mod->srcversion); + } ++#endif + } + + static void write_if_changed(struct buffer *b, const char *fname) +@@ -2224,7 +2234,9 @@ int main(int argc, char **argv) + add_staging_flag(&buf, mod->name); + err |= add_versions(&buf, mod); + add_depends(&buf, mod, modules); ++#ifndef CONFIG_MODULE_STRIPPED + add_moddevtable(&buf, mod); ++#endif + add_srcversion(&buf, mod); + + sprintf(fname, "%s.mod.c", mod->name); diff --git a/target/linux/generic/patches-4.0/205-backtrace_module_info.patch b/target/linux/generic/patches-4.0/205-backtrace_module_info.patch new file mode 100644 index 0000000..2d0cc5a --- /dev/null +++ b/target/linux/generic/patches-4.0/205-backtrace_module_info.patch @@ -0,0 +1,36 @@ +--- a/lib/vsprintf.c ++++ b/lib/vsprintf.c +@@ -615,8 +615,10 @@ char *symbol_string(char *buf, char *end + struct printf_spec spec, const char *fmt) + { + unsigned long value; +-#ifdef CONFIG_KALLSYMS + char sym[KSYM_SYMBOL_LEN]; ++#ifndef CONFIG_KALLSYMS ++ struct module *mod; ++ int len; + #endif + + if (fmt[1] == 'R') +@@ -630,15 +632,15 @@ char *symbol_string(char *buf, char *end + sprint_symbol(sym, value); + else + sprint_symbol_no_offset(sym, value); +- +- return string(buf, end, sym, spec); + #else +- spec.field_width = 2 * sizeof(void *); +- spec.flags |= SPECIAL | SMALL | ZEROPAD; +- spec.base = 16; ++ len = snprintf(sym, sizeof(sym), "0x%lx", value); + +- return number(buf, end, value, spec); ++ mod = __module_address(value); ++ if (mod) ++ snprintf(sym + len, sizeof(sym) - len, " [%s@%p+0x%x]", ++ mod->name, mod->module_core, mod->core_size); + #endif ++ return string(buf, end, sym, spec); + } + + static noinline_for_stack diff --git a/target/linux/generic/patches-4.0/210-darwin_scripts_include.patch b/target/linux/generic/patches-4.0/210-darwin_scripts_include.patch new file mode 100644 index 0000000..dc554de --- /dev/null +++ b/target/linux/generic/patches-4.0/210-darwin_scripts_include.patch @@ -0,0 +1,3088 @@ +--- a/scripts/kallsyms.c ++++ b/scripts/kallsyms.c +@@ -22,6 +22,35 @@ + #include + #include + #include ++#ifdef __APPLE__ ++/* Darwin has no memmem implementation, this one is ripped of the uClibc-0.9.28 source */ ++void *memmem (const void *haystack, size_t haystack_len, ++ const void *needle, size_t needle_len) ++{ ++ const char *begin; ++ const char *const last_possible ++ = (const char *) haystack + haystack_len - needle_len; ++ ++ if (needle_len == 0) ++ /* The first occurrence of the empty string is deemed to occur at ++ the beginning of the string. */ ++ return (void *) haystack; ++ ++ /* Sanity check, otherwise the loop might search through the whole ++ memory. */ ++ if (__builtin_expect (haystack_len < needle_len, 0)) ++ return NULL; ++ ++ for (begin = (const char *) haystack; begin <= last_possible; ++begin) ++ if (begin[0] == ((const char *) needle)[0] && ++ !memcmp ((const void *) &begin[1], ++ (const void *) ((const char *) needle + 1), ++ needle_len - 1)) ++ return (void *) begin; ++ ++ return NULL; ++} ++#endif + + #ifndef ARRAY_SIZE + #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) +--- a/scripts/kconfig/Makefile ++++ b/scripts/kconfig/Makefile +@@ -151,6 +151,9 @@ check-lxdialog := $(srctree)/$(src)/lxd + # we really need to do so. (Do not call gcc as part of make mrproper) + HOST_EXTRACFLAGS += $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags) \ + -DLOCALE ++ifeq ($(shell uname -s),Darwin) ++HOST_LOADLIBES += -lncurses ++endif + + # =========================================================================== + # Shared Makefile for the various kconfig executables: +--- a/scripts/mod/mk_elfconfig.c ++++ b/scripts/mod/mk_elfconfig.c +@@ -1,7 +1,11 @@ + #include + #include + #include ++#ifndef __APPLE__ + #include ++#else ++#include "elf.h" ++#endif + + int + main(int argc, char **argv) +--- a/scripts/mod/modpost.h ++++ b/scripts/mod/modpost.h +@@ -7,7 +7,11 @@ + #include + #include + #include ++#if !(defined(__APPLE__) || defined(__CYGWIN__)) + #include ++#else ++#include "elf.h" ++#endif + + #include "elfconfig.h" + +--- /dev/null ++++ b/scripts/mod/elf.h +@@ -0,0 +1,3007 @@ ++/* This file defines standard ELF types, structures, and macros. ++ Copyright (C) 1995-2012 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, see ++ . */ ++ ++#ifndef _ELF_H ++#define _ELF_H 1 ++ ++/* Standard ELF types. */ ++ ++#include ++ ++/* Type for a 16-bit quantity. */ ++typedef uint16_t Elf32_Half; ++typedef uint16_t Elf64_Half; ++ ++/* Types for signed and unsigned 32-bit quantities. */ ++typedef uint32_t Elf32_Word; ++typedef int32_t Elf32_Sword; ++typedef uint32_t Elf64_Word; ++typedef int32_t Elf64_Sword; ++ ++/* Types for signed and unsigned 64-bit quantities. */ ++typedef uint64_t Elf32_Xword; ++typedef int64_t Elf32_Sxword; ++typedef uint64_t Elf64_Xword; ++typedef int64_t Elf64_Sxword; ++ ++/* Type of addresses. */ ++typedef uint32_t Elf32_Addr; ++typedef uint64_t Elf64_Addr; ++ ++/* Type of file offsets. */ ++typedef uint32_t Elf32_Off; ++typedef uint64_t Elf64_Off; ++ ++/* Type for section indices, which are 16-bit quantities. */ ++typedef uint16_t Elf32_Section; ++typedef uint16_t Elf64_Section; ++ ++/* Type for version symbol information. */ ++typedef Elf32_Half Elf32_Versym; ++typedef Elf64_Half Elf64_Versym; ++ ++ ++/* The ELF file header. This appears at the start of every ELF file. */ ++ ++#define EI_NIDENT (16) ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf32_Half e_type; /* Object file type */ ++ Elf32_Half e_machine; /* Architecture */ ++ Elf32_Word e_version; /* Object file version */ ++ Elf32_Addr e_entry; /* Entry point virtual address */ ++ Elf32_Off e_phoff; /* Program header table file offset */ ++ Elf32_Off e_shoff; /* Section header table file offset */ ++ Elf32_Word e_flags; /* Processor-specific flags */ ++ Elf32_Half e_ehsize; /* ELF header size in bytes */ ++ Elf32_Half e_phentsize; /* Program header table entry size */ ++ Elf32_Half e_phnum; /* Program header table entry count */ ++ Elf32_Half e_shentsize; /* Section header table entry size */ ++ Elf32_Half e_shnum; /* Section header table entry count */ ++ Elf32_Half e_shstrndx; /* Section header string table index */ ++} Elf32_Ehdr; ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf64_Half e_type; /* Object file type */ ++ Elf64_Half e_machine; /* Architecture */ ++ Elf64_Word e_version; /* Object file version */ ++ Elf64_Addr e_entry; /* Entry point virtual address */ ++ Elf64_Off e_phoff; /* Program header table file offset */ ++ Elf64_Off e_shoff; /* Section header table file offset */ ++ Elf64_Word e_flags; /* Processor-specific flags */ ++ Elf64_Half e_ehsize; /* ELF header size in bytes */ ++ Elf64_Half e_phentsize; /* Program header table entry size */ ++ Elf64_Half e_phnum; /* Program header table entry count */ ++ Elf64_Half e_shentsize; /* Section header table entry size */ ++ Elf64_Half e_shnum; /* Section header table entry count */ ++ Elf64_Half e_shstrndx; /* Section header string table index */ ++} Elf64_Ehdr; ++ ++/* Fields in the e_ident array. The EI_* macros are indices into the ++ array. The macros under each EI_* macro are the values the byte ++ may have. */ ++ ++#define EI_MAG0 0 /* File identification byte 0 index */ ++#define ELFMAG0 0x7f /* Magic number byte 0 */ ++ ++#define EI_MAG1 1 /* File identification byte 1 index */ ++#define ELFMAG1 'E' /* Magic number byte 1 */ ++ ++#define EI_MAG2 2 /* File identification byte 2 index */ ++#define ELFMAG2 'L' /* Magic number byte 2 */ ++ ++#define EI_MAG3 3 /* File identification byte 3 index */ ++#define ELFMAG3 'F' /* Magic number byte 3 */ ++ ++/* Conglomeration of the identification bytes, for easy testing as a word. */ ++#define ELFMAG "\177ELF" ++#define SELFMAG 4 ++ ++#define EI_CLASS 4 /* File class byte index */ ++#define ELFCLASSNONE 0 /* Invalid class */ ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++#define ELFCLASSNUM 3 ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATANONE 0 /* Invalid data encoding */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ ++#define ELFDATANUM 3 ++ ++#define EI_VERSION 6 /* File version byte index */ ++ /* Value must be EV_CURRENT */ ++ ++#define EI_OSABI 7 /* OS ABI identification */ ++#define ELFOSABI_NONE 0 /* UNIX System V ABI */ ++#define ELFOSABI_SYSV 0 /* Alias. */ ++#define ELFOSABI_HPUX 1 /* HP-UX */ ++#define ELFOSABI_NETBSD 2 /* NetBSD. */ ++#define ELFOSABI_GNU 3 /* Object uses GNU ELF extensions. */ ++#define ELFOSABI_LINUX ELFOSABI_GNU /* Compatibility alias. */ ++#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ ++#define ELFOSABI_AIX 7 /* IBM AIX. */ ++#define ELFOSABI_IRIX 8 /* SGI Irix. */ ++#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ ++#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ ++#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ ++#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ ++#define ELFOSABI_ARM_AEABI 64 /* ARM EABI */ ++#define ELFOSABI_ARM 97 /* ARM */ ++#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ ++ ++#define EI_ABIVERSION 8 /* ABI version */ ++ ++#define EI_PAD 9 /* Byte index of padding bytes */ ++ ++/* Legal values for e_type (object file type). */ ++ ++#define ET_NONE 0 /* No file type */ ++#define ET_REL 1 /* Relocatable file */ ++#define ET_EXEC 2 /* Executable file */ ++#define ET_DYN 3 /* Shared object file */ ++#define ET_CORE 4 /* Core file */ ++#define ET_NUM 5 /* Number of defined types */ ++#define ET_LOOS 0xfe00 /* OS-specific range start */ ++#define ET_HIOS 0xfeff /* OS-specific range end */ ++#define ET_LOPROC 0xff00 /* Processor-specific range start */ ++#define ET_HIPROC 0xffff /* Processor-specific range end */ ++ ++/* Legal values for e_machine (architecture). */ ++ ++#define EM_NONE 0 /* No machine */ ++#define EM_M32 1 /* AT&T WE 32100 */ ++#define EM_SPARC 2 /* SUN SPARC */ ++#define EM_386 3 /* Intel 80386 */ ++#define EM_68K 4 /* Motorola m68k family */ ++#define EM_88K 5 /* Motorola m88k family */ ++#define EM_860 7 /* Intel 80860 */ ++#define EM_MIPS 8 /* MIPS R3000 big-endian */ ++#define EM_S370 9 /* IBM System/370 */ ++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ ++ ++#define EM_PARISC 15 /* HPPA */ ++#define EM_VPP500 17 /* Fujitsu VPP500 */ ++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ ++#define EM_960 19 /* Intel 80960 */ ++#define EM_PPC 20 /* PowerPC */ ++#define EM_PPC64 21 /* PowerPC 64-bit */ ++#define EM_S390 22 /* IBM S390 */ ++ ++#define EM_V800 36 /* NEC V800 series */ ++#define EM_FR20 37 /* Fujitsu FR20 */ ++#define EM_RH32 38 /* TRW RH-32 */ ++#define EM_RCE 39 /* Motorola RCE */ ++#define EM_ARM 40 /* ARM */ ++#define EM_FAKE_ALPHA 41 /* Digital Alpha */ ++#define EM_SH 42 /* Hitachi SH */ ++#define EM_SPARCV9 43 /* SPARC v9 64-bit */ ++#define EM_TRICORE 44 /* Siemens Tricore */ ++#define EM_ARC 45 /* Argonaut RISC Core */ ++#define EM_H8_300 46 /* Hitachi H8/300 */ ++#define EM_H8_300H 47 /* Hitachi H8/300H */ ++#define EM_H8S 48 /* Hitachi H8S */ ++#define EM_H8_500 49 /* Hitachi H8/500 */ ++#define EM_IA_64 50 /* Intel Merced */ ++#define EM_MIPS_X 51 /* Stanford MIPS-X */ ++#define EM_COLDFIRE 52 /* Motorola Coldfire */ ++#define EM_68HC12 53 /* Motorola M68HC12 */ ++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ ++#define EM_PCP 55 /* Siemens PCP */ ++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ ++#define EM_NDR1 57 /* Denso NDR1 microprocessor */ ++#define EM_STARCORE 58 /* Motorola Start*Core processor */ ++#define EM_ME16 59 /* Toyota ME16 processor */ ++#define EM_ST100 60 /* STMicroelectronic ST100 processor */ ++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ ++#define EM_X86_64 62 /* AMD x86-64 architecture */ ++#define EM_PDSP 63 /* Sony DSP Processor */ ++ ++#define EM_FX66 66 /* Siemens FX66 microcontroller */ ++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ ++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ ++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ ++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ ++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ ++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ ++#define EM_SVX 73 /* Silicon Graphics SVx */ ++#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ ++#define EM_VAX 75 /* Digital VAX */ ++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ ++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ ++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ ++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ ++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ ++#define EM_HUANY 81 /* Harvard University machine-independent object files */ ++#define EM_PRISM 82 /* SiTera Prism */ ++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ ++#define EM_FR30 84 /* Fujitsu FR30 */ ++#define EM_D10V 85 /* Mitsubishi D10V */ ++#define EM_D30V 86 /* Mitsubishi D30V */ ++#define EM_V850 87 /* NEC v850 */ ++#define EM_M32R 88 /* Mitsubishi M32R */ ++#define EM_MN10300 89 /* Matsushita MN10300 */ ++#define EM_MN10200 90 /* Matsushita MN10200 */ ++#define EM_PJ 91 /* picoJava */ ++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ ++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ ++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ ++#define EM_TILEPRO 188 /* Tilera TILEPro */ ++#define EM_TILEGX 191 /* Tilera TILE-Gx */ ++#define EM_NUM 192 ++ ++/* If it is necessary to assign new unofficial EM_* values, please ++ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the ++ chances of collision with official or non-GNU unofficial values. */ ++ ++#define EM_ALPHA 0x9026 ++ ++/* Legal values for e_version (version). */ ++ ++#define EV_NONE 0 /* Invalid ELF version */ ++#define EV_CURRENT 1 /* Current version */ ++#define EV_NUM 2 ++ ++/* Section header. */ ++ ++typedef struct ++{ ++ Elf32_Word sh_name; /* Section name (string tbl index) */ ++ Elf32_Word sh_type; /* Section type */ ++ Elf32_Word sh_flags; /* Section flags */ ++ Elf32_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf32_Off sh_offset; /* Section file offset */ ++ Elf32_Word sh_size; /* Section size in bytes */ ++ Elf32_Word sh_link; /* Link to another section */ ++ Elf32_Word sh_info; /* Additional section information */ ++ Elf32_Word sh_addralign; /* Section alignment */ ++ Elf32_Word sh_entsize; /* Entry size if section holds table */ ++} Elf32_Shdr; ++ ++typedef struct ++{ ++ Elf64_Word sh_name; /* Section name (string tbl index) */ ++ Elf64_Word sh_type; /* Section type */ ++ Elf64_Xword sh_flags; /* Section flags */ ++ Elf64_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf64_Off sh_offset; /* Section file offset */ ++ Elf64_Xword sh_size; /* Section size in bytes */ ++ Elf64_Word sh_link; /* Link to another section */ ++ Elf64_Word sh_info; /* Additional section information */ ++ Elf64_Xword sh_addralign; /* Section alignment */ ++ Elf64_Xword sh_entsize; /* Entry size if section holds table */ ++} Elf64_Shdr; ++ ++/* Special section indices. */ ++ ++#define SHN_UNDEF 0 /* Undefined section */ ++#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ ++#define SHN_LOPROC 0xff00 /* Start of processor-specific */ ++#define SHN_BEFORE 0xff00 /* Order section before all others ++ (Solaris). */ ++#define SHN_AFTER 0xff01 /* Order section after all others ++ (Solaris). */ ++#define SHN_HIPROC 0xff1f /* End of processor-specific */ ++#define SHN_LOOS 0xff20 /* Start of OS-specific */ ++#define SHN_HIOS 0xff3f /* End of OS-specific */ ++#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ ++#define SHN_COMMON 0xfff2 /* Associated symbol is common */ ++#define SHN_XINDEX 0xffff /* Index is in extra table. */ ++#define SHN_HIRESERVE 0xffff /* End of reserved indices */ ++ ++/* Legal values for sh_type (section type). */ ++ ++#define SHT_NULL 0 /* Section header table entry unused */ ++#define SHT_PROGBITS 1 /* Program data */ ++#define SHT_SYMTAB 2 /* Symbol table */ ++#define SHT_STRTAB 3 /* String table */ ++#define SHT_RELA 4 /* Relocation entries with addends */ ++#define SHT_HASH 5 /* Symbol hash table */ ++#define SHT_DYNAMIC 6 /* Dynamic linking information */ ++#define SHT_NOTE 7 /* Notes */ ++#define SHT_NOBITS 8 /* Program space with no data (bss) */ ++#define SHT_REL 9 /* Relocation entries, no addends */ ++#define SHT_SHLIB 10 /* Reserved */ ++#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ ++#define SHT_INIT_ARRAY 14 /* Array of constructors */ ++#define SHT_FINI_ARRAY 15 /* Array of destructors */ ++#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ ++#define SHT_GROUP 17 /* Section group */ ++#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ ++#define SHT_NUM 19 /* Number of defined types. */ ++#define SHT_LOOS 0x60000000 /* Start OS-specific. */ ++#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes. */ ++#define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ ++#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ ++#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ ++#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ ++#define SHT_SUNW_move 0x6ffffffa ++#define SHT_SUNW_COMDAT 0x6ffffffb ++#define SHT_SUNW_syminfo 0x6ffffffc ++#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ ++#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ ++#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ ++#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ ++#define SHT_HIOS 0x6fffffff /* End OS-specific type */ ++#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define SHT_LOUSER 0x80000000 /* Start of application-specific */ ++#define SHT_HIUSER 0x8fffffff /* End of application-specific */ ++ ++/* Legal values for sh_flags (section flags). */ ++ ++#define SHF_WRITE (1 << 0) /* Writable */ ++#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ ++#define SHF_EXECINSTR (1 << 2) /* Executable */ ++#define SHF_MERGE (1 << 4) /* Might be merged */ ++#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ ++#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ ++#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ ++#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling ++ required */ ++#define SHF_GROUP (1 << 9) /* Section is member of a group. */ ++#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ ++#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ ++#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ ++#define SHF_ORDERED (1 << 30) /* Special ordering requirement ++ (Solaris). */ ++#define SHF_EXCLUDE (1 << 31) /* Section is excluded unless ++ referenced or allocated (Solaris).*/ ++ ++/* Section group handling. */ ++#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ ++ ++/* Symbol table entry. */ ++ ++typedef struct ++{ ++ Elf32_Word st_name; /* Symbol name (string tbl index) */ ++ Elf32_Addr st_value; /* Symbol value */ ++ Elf32_Word st_size; /* Symbol size */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf32_Section st_shndx; /* Section index */ ++} Elf32_Sym; ++ ++typedef struct ++{ ++ Elf64_Word st_name; /* Symbol name (string tbl index) */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf64_Section st_shndx; /* Section index */ ++ Elf64_Addr st_value; /* Symbol value */ ++ Elf64_Xword st_size; /* Symbol size */ ++} Elf64_Sym; ++ ++/* The syminfo section if available contains additional information about ++ every dynamic symbol. */ ++ ++typedef struct ++{ ++ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf32_Half si_flags; /* Per symbol flags */ ++} Elf32_Syminfo; ++ ++typedef struct ++{ ++ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf64_Half si_flags; /* Per symbol flags */ ++} Elf64_Syminfo; ++ ++/* Possible values for si_boundto. */ ++#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ ++#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ ++#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ ++ ++/* Possible bitmasks for si_flags. */ ++#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ ++#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ ++#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ ++#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy ++ loaded */ ++/* Syminfo version values. */ ++#define SYMINFO_NONE 0 ++#define SYMINFO_CURRENT 1 ++#define SYMINFO_NUM 2 ++ ++ ++/* How to extract and insert information held in the st_info field. */ ++ ++#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) ++#define ELF32_ST_TYPE(val) ((val) & 0xf) ++#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) ++ ++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ ++#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) ++#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) ++#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) ++ ++/* Legal values for ST_BIND subfield of st_info (symbol binding). */ ++ ++#define STB_LOCAL 0 /* Local symbol */ ++#define STB_GLOBAL 1 /* Global symbol */ ++#define STB_WEAK 2 /* Weak symbol */ ++#define STB_NUM 3 /* Number of defined types. */ ++#define STB_LOOS 10 /* Start of OS-specific */ ++#define STB_GNU_UNIQUE 10 /* Unique symbol. */ ++#define STB_HIOS 12 /* End of OS-specific */ ++#define STB_LOPROC 13 /* Start of processor-specific */ ++#define STB_HIPROC 15 /* End of processor-specific */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_NOTYPE 0 /* Symbol type is unspecified */ ++#define STT_OBJECT 1 /* Symbol is a data object */ ++#define STT_FUNC 2 /* Symbol is a code object */ ++#define STT_SECTION 3 /* Symbol associated with a section */ ++#define STT_FILE 4 /* Symbol's name is file name */ ++#define STT_COMMON 5 /* Symbol is a common data object */ ++#define STT_TLS 6 /* Symbol is thread-local data object*/ ++#define STT_NUM 7 /* Number of defined types. */ ++#define STT_LOOS 10 /* Start of OS-specific */ ++#define STT_GNU_IFUNC 10 /* Symbol is indirect code object */ ++#define STT_HIOS 12 /* End of OS-specific */ ++#define STT_LOPROC 13 /* Start of processor-specific */ ++#define STT_HIPROC 15 /* End of processor-specific */ ++ ++ ++/* Symbol table indices are found in the hash buckets and chain table ++ of a symbol hash table section. This special index value indicates ++ the end of a chain, meaning no further symbols are found in that bucket. */ ++ ++#define STN_UNDEF 0 /* End of a chain. */ ++ ++ ++/* How to extract and insert information held in the st_other field. */ ++ ++#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) ++ ++/* For ELF64 the definitions are the same. */ ++#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) ++ ++/* Symbol visibility specification encoded in the st_other field. */ ++#define STV_DEFAULT 0 /* Default symbol visibility rules */ ++#define STV_INTERNAL 1 /* Processor specific hidden class */ ++#define STV_HIDDEN 2 /* Sym unavailable in other modules */ ++#define STV_PROTECTED 3 /* Not preemptible, not exported */ ++ ++ ++/* Relocation table entry without addend (in section of type SHT_REL). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++} Elf32_Rel; ++ ++/* I have seen two different definitions of the Elf64_Rel and ++ Elf64_Rela structures, so we'll leave them out until Novell (or ++ whoever) gets their act together. */ ++/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++} Elf64_Rel; ++ ++/* Relocation table entry with addend (in section of type SHT_RELA). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++ Elf32_Sword r_addend; /* Addend */ ++} Elf32_Rela; ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++ Elf64_Sxword r_addend; /* Addend */ ++} Elf64_Rela; ++ ++/* How to extract and insert information held in the r_info field. */ ++ ++#define ELF32_R_SYM(val) ((val) >> 8) ++#define ELF32_R_TYPE(val) ((val) & 0xff) ++#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) ++ ++#define ELF64_R_SYM(i) ((i) >> 32) ++#define ELF64_R_TYPE(i) ((i) & 0xffffffff) ++#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) ++ ++/* Program segment header. */ ++ ++typedef struct ++{ ++ Elf32_Word p_type; /* Segment type */ ++ Elf32_Off p_offset; /* Segment file offset */ ++ Elf32_Addr p_vaddr; /* Segment virtual address */ ++ Elf32_Addr p_paddr; /* Segment physical address */ ++ Elf32_Word p_filesz; /* Segment size in file */ ++ Elf32_Word p_memsz; /* Segment size in memory */ ++ Elf32_Word p_flags; /* Segment flags */ ++ Elf32_Word p_align; /* Segment alignment */ ++} Elf32_Phdr; ++ ++typedef struct ++{ ++ Elf64_Word p_type; /* Segment type */ ++ Elf64_Word p_flags; /* Segment flags */ ++ Elf64_Off p_offset; /* Segment file offset */ ++ Elf64_Addr p_vaddr; /* Segment virtual address */ ++ Elf64_Addr p_paddr; /* Segment physical address */ ++ Elf64_Xword p_filesz; /* Segment size in file */ ++ Elf64_Xword p_memsz; /* Segment size in memory */ ++ Elf64_Xword p_align; /* Segment alignment */ ++} Elf64_Phdr; ++ ++/* Special value for e_phnum. This indicates that the real number of ++ program headers is too large to fit into e_phnum. Instead the real ++ value is in the field sh_info of section 0. */ ++ ++#define PN_XNUM 0xffff ++ ++/* Legal values for p_type (segment type). */ ++ ++#define PT_NULL 0 /* Program header table entry unused */ ++#define PT_LOAD 1 /* Loadable program segment */ ++#define PT_DYNAMIC 2 /* Dynamic linking information */ ++#define PT_INTERP 3 /* Program interpreter */ ++#define PT_NOTE 4 /* Auxiliary information */ ++#define PT_SHLIB 5 /* Reserved */ ++#define PT_PHDR 6 /* Entry for header table itself */ ++#define PT_TLS 7 /* Thread-local storage segment */ ++#define PT_NUM 8 /* Number of defined types */ ++#define PT_LOOS 0x60000000 /* Start of OS-specific */ ++#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ ++#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ ++#define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ ++#define PT_LOSUNW 0x6ffffffa ++#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ ++#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ ++#define PT_HISUNW 0x6fffffff ++#define PT_HIOS 0x6fffffff /* End of OS-specific */ ++#define PT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define PT_HIPROC 0x7fffffff /* End of processor-specific */ ++ ++/* Legal values for p_flags (segment flags). */ ++ ++#define PF_X (1 << 0) /* Segment is executable */ ++#define PF_W (1 << 1) /* Segment is writable */ ++#define PF_R (1 << 2) /* Segment is readable */ ++#define PF_MASKOS 0x0ff00000 /* OS-specific */ ++#define PF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Legal values for note segment descriptor types for core files. */ ++ ++#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ ++#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ ++#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ ++#define NT_PRXREG 4 /* Contains copy of prxregset struct */ ++#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ ++#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ ++#define NT_AUXV 6 /* Contains copy of auxv array */ ++#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ ++#define NT_ASRS 8 /* Contains copy of asrset struct */ ++#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ ++#define NT_PSINFO 13 /* Contains copy of psinfo struct */ ++#define NT_PRCRED 14 /* Contains copy of prcred struct */ ++#define NT_UTSNAME 15 /* Contains copy of utsname struct */ ++#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ ++#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ ++#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ ++#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ ++#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ ++#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ ++#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ ++#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ ++#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ ++#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ ++ ++/* Legal values for the note segment descriptor types for object files. */ ++ ++#define NT_VERSION 1 /* Contains a version string. */ ++ ++ ++/* Dynamic section entry. */ ++ ++typedef struct ++{ ++ Elf32_Sword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf32_Word d_val; /* Integer value */ ++ Elf32_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf32_Dyn; ++ ++typedef struct ++{ ++ Elf64_Sxword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf64_Xword d_val; /* Integer value */ ++ Elf64_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf64_Dyn; ++ ++/* Legal values for d_tag (dynamic entry type). */ ++ ++#define DT_NULL 0 /* Marks end of dynamic section */ ++#define DT_NEEDED 1 /* Name of needed library */ ++#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ ++#define DT_PLTGOT 3 /* Processor defined value */ ++#define DT_HASH 4 /* Address of symbol hash table */ ++#define DT_STRTAB 5 /* Address of string table */ ++#define DT_SYMTAB 6 /* Address of symbol table */ ++#define DT_RELA 7 /* Address of Rela relocs */ ++#define DT_RELASZ 8 /* Total size of Rela relocs */ ++#define DT_RELAENT 9 /* Size of one Rela reloc */ ++#define DT_STRSZ 10 /* Size of string table */ ++#define DT_SYMENT 11 /* Size of one symbol table entry */ ++#define DT_INIT 12 /* Address of init function */ ++#define DT_FINI 13 /* Address of termination function */ ++#define DT_SONAME 14 /* Name of shared object */ ++#define DT_RPATH 15 /* Library search path (deprecated) */ ++#define DT_SYMBOLIC 16 /* Start symbol search here */ ++#define DT_REL 17 /* Address of Rel relocs */ ++#define DT_RELSZ 18 /* Total size of Rel relocs */ ++#define DT_RELENT 19 /* Size of one Rel reloc */ ++#define DT_PLTREL 20 /* Type of reloc in PLT */ ++#define DT_DEBUG 21 /* For debugging; unspecified */ ++#define DT_TEXTREL 22 /* Reloc might modify .text */ ++#define DT_JMPREL 23 /* Address of PLT relocs */ ++#define DT_BIND_NOW 24 /* Process relocations of object */ ++#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ ++#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ ++#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ ++#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ ++#define DT_RUNPATH 29 /* Library search path */ ++#define DT_FLAGS 30 /* Flags for the object being loaded */ ++#define DT_ENCODING 32 /* Start of encoded range */ ++#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ ++#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ ++#define DT_NUM 34 /* Number used */ ++#define DT_LOOS 0x6000000d /* Start of OS-specific */ ++#define DT_HIOS 0x6ffff000 /* End of OS-specific */ ++#define DT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define DT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ ++ ++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the ++ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's ++ approach. */ ++#define DT_VALRNGLO 0x6ffffd00 ++#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ ++#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ ++#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ ++#define DT_CHECKSUM 0x6ffffdf8 ++#define DT_PLTPADSZ 0x6ffffdf9 ++#define DT_MOVEENT 0x6ffffdfa ++#define DT_MOVESZ 0x6ffffdfb ++#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ ++#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting ++ the following DT_* entry. */ ++#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ ++#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ ++#define DT_VALRNGHI 0x6ffffdff ++#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ ++#define DT_VALNUM 12 ++ ++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the ++ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. ++ ++ If any adjustment is made to the ELF object after it has been ++ built these entries will need to be adjusted. */ ++#define DT_ADDRRNGLO 0x6ffffe00 ++#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ ++#define DT_TLSDESC_PLT 0x6ffffef6 ++#define DT_TLSDESC_GOT 0x6ffffef7 ++#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ ++#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ ++#define DT_CONFIG 0x6ffffefa /* Configuration information. */ ++#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ ++#define DT_AUDIT 0x6ffffefc /* Object auditing. */ ++#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ ++#define DT_MOVETAB 0x6ffffefe /* Move table. */ ++#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ ++#define DT_ADDRRNGHI 0x6ffffeff ++#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ ++#define DT_ADDRNUM 11 ++ ++/* The versioning entry types. The next are defined as part of the ++ GNU extension. */ ++#define DT_VERSYM 0x6ffffff0 ++ ++#define DT_RELACOUNT 0x6ffffff9 ++#define DT_RELCOUNT 0x6ffffffa ++ ++/* These were chosen by Sun. */ ++#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ ++#define DT_VERDEF 0x6ffffffc /* Address of version definition ++ table */ ++#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ ++#define DT_VERNEED 0x6ffffffe /* Address of table with needed ++ versions */ ++#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ ++#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ ++#define DT_VERSIONTAGNUM 16 ++ ++/* Sun added these machine-independent extensions in the "processor-specific" ++ range. Be compatible. */ ++#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ ++#define DT_FILTER 0x7fffffff /* Shared object to get values from */ ++#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) ++#define DT_EXTRANUM 3 ++ ++/* Values of `d_un.d_val' in the DT_FLAGS entry. */ ++#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ ++#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ ++#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ ++#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ ++#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ ++ ++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 ++ entry in the dynamic section. */ ++#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ ++#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ ++#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ ++#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ ++#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ ++#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ ++#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ ++#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ ++#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ ++#define DF_1_TRANS 0x00000200 ++#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ ++#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ ++#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ ++#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ ++#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ ++#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ ++#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ ++ ++/* Flags for the feature selection in DT_FEATURE_1. */ ++#define DTF_1_PARINIT 0x00000001 ++#define DTF_1_CONFEXP 0x00000002 ++ ++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ ++#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ ++#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not ++ generally available. */ ++ ++/* Version definition sections. */ ++ ++typedef struct ++{ ++ Elf32_Half vd_version; /* Version revision */ ++ Elf32_Half vd_flags; /* Version information */ ++ Elf32_Half vd_ndx; /* Version Index */ ++ Elf32_Half vd_cnt; /* Number of associated aux entries */ ++ Elf32_Word vd_hash; /* Version name hash value */ ++ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf32_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf32_Verdef; ++ ++typedef struct ++{ ++ Elf64_Half vd_version; /* Version revision */ ++ Elf64_Half vd_flags; /* Version information */ ++ Elf64_Half vd_ndx; /* Version Index */ ++ Elf64_Half vd_cnt; /* Number of associated aux entries */ ++ Elf64_Word vd_hash; /* Version name hash value */ ++ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf64_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf64_Verdef; ++ ++ ++/* Legal values for vd_version (version revision). */ ++#define VER_DEF_NONE 0 /* No version */ ++#define VER_DEF_CURRENT 1 /* Current version */ ++#define VER_DEF_NUM 2 /* Given version number */ ++ ++/* Legal values for vd_flags (version information flags). */ ++#define VER_FLG_BASE 0x1 /* Version definition of file itself */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++/* Versym symbol index values. */ ++#define VER_NDX_LOCAL 0 /* Symbol is local. */ ++#define VER_NDX_GLOBAL 1 /* Symbol is global. */ ++#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ ++#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ ++ ++/* Auxialiary version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vda_name; /* Version or dependency names */ ++ Elf32_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf32_Verdaux; ++ ++typedef struct ++{ ++ Elf64_Word vda_name; /* Version or dependency names */ ++ Elf64_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf64_Verdaux; ++ ++ ++/* Version dependency section. */ ++ ++typedef struct ++{ ++ Elf32_Half vn_version; /* Version of structure */ ++ Elf32_Half vn_cnt; /* Number of associated aux entries */ ++ Elf32_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf32_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf32_Verneed; ++ ++typedef struct ++{ ++ Elf64_Half vn_version; /* Version of structure */ ++ Elf64_Half vn_cnt; /* Number of associated aux entries */ ++ Elf64_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf64_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf64_Verneed; ++ ++ ++/* Legal values for vn_version (version revision). */ ++#define VER_NEED_NONE 0 /* No version */ ++#define VER_NEED_CURRENT 1 /* Current version */ ++#define VER_NEED_NUM 2 /* Given version number */ ++ ++/* Auxiliary needed version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vna_hash; /* Hash value of dependency name */ ++ Elf32_Half vna_flags; /* Dependency specific information */ ++ Elf32_Half vna_other; /* Unused */ ++ Elf32_Word vna_name; /* Dependency name string offset */ ++ Elf32_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf32_Vernaux; ++ ++typedef struct ++{ ++ Elf64_Word vna_hash; /* Hash value of dependency name */ ++ Elf64_Half vna_flags; /* Dependency specific information */ ++ Elf64_Half vna_other; /* Unused */ ++ Elf64_Word vna_name; /* Dependency name string offset */ ++ Elf64_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf64_Vernaux; ++ ++ ++/* Legal values for vna_flags. */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++ ++/* Auxiliary vector. */ ++ ++/* This vector is normally only used by the program interpreter. The ++ usual definition in an ABI supplement uses the name auxv_t. The ++ vector is not usually defined in a standard file, but it ++ can't hurt. We rename it to avoid conflicts. The sizes of these ++ types are an arrangement between the exec server and the program ++ interpreter, so we don't fully specify them here. */ ++ ++typedef struct ++{ ++ uint32_t a_type; /* Entry type */ ++ union ++ { ++ uint32_t a_val; /* Integer value */ ++ /* We use to have pointer elements added here. We cannot do that, ++ though, since it does not work when using 32-bit definitions ++ on 64-bit platforms and vice versa. */ ++ } a_un; ++} Elf32_auxv_t; ++ ++typedef struct ++{ ++ uint64_t a_type; /* Entry type */ ++ union ++ { ++ uint64_t a_val; /* Integer value */ ++ /* We use to have pointer elements added here. We cannot do that, ++ though, since it does not work when using 32-bit definitions ++ on 64-bit platforms and vice versa. */ ++ } a_un; ++} Elf64_auxv_t; ++ ++/* Legal values for a_type (entry type). */ ++ ++#define AT_NULL 0 /* End of vector */ ++#define AT_IGNORE 1 /* Entry should be ignored */ ++#define AT_EXECFD 2 /* File descriptor of program */ ++#define AT_PHDR 3 /* Program headers for program */ ++#define AT_PHENT 4 /* Size of program header entry */ ++#define AT_PHNUM 5 /* Number of program headers */ ++#define AT_PAGESZ 6 /* System page size */ ++#define AT_BASE 7 /* Base address of interpreter */ ++#define AT_FLAGS 8 /* Flags */ ++#define AT_ENTRY 9 /* Entry point of program */ ++#define AT_NOTELF 10 /* Program is not ELF */ ++#define AT_UID 11 /* Real uid */ ++#define AT_EUID 12 /* Effective uid */ ++#define AT_GID 13 /* Real gid */ ++#define AT_EGID 14 /* Effective gid */ ++#define AT_CLKTCK 17 /* Frequency of times() */ ++ ++/* Some more special a_type values describing the hardware. */ ++#define AT_PLATFORM 15 /* String identifying platform. */ ++#define AT_HWCAP 16 /* Machine dependent hints about ++ processor capabilities. */ ++ ++/* This entry gives some information about the FPU initialization ++ performed by the kernel. */ ++#define AT_FPUCW 18 /* Used FPU control word. */ ++ ++/* Cache block sizes. */ ++#define AT_DCACHEBSIZE 19 /* Data cache block size. */ ++#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ ++#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ ++ ++/* A special ignored value for PPC, used by the kernel to control the ++ interpretation of the AUXV. Must be > 16. */ ++#define AT_IGNOREPPC 22 /* Entry should be ignored. */ ++ ++#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ ++ ++#define AT_BASE_PLATFORM 24 /* String identifying real platforms.*/ ++ ++#define AT_RANDOM 25 /* Address of 16 random bytes. */ ++ ++#define AT_EXECFN 31 /* Filename of executable. */ ++ ++/* Pointer to the global system page used for system calls and other ++ nice things. */ ++#define AT_SYSINFO 32 ++#define AT_SYSINFO_EHDR 33 ++ ++/* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains ++ log2 of line size; mask those to get cache size. */ ++#define AT_L1I_CACHESHAPE 34 ++#define AT_L1D_CACHESHAPE 35 ++#define AT_L2_CACHESHAPE 36 ++#define AT_L3_CACHESHAPE 37 ++ ++/* Note section contents. Each entry in the note section begins with ++ a header of a fixed form. */ ++ ++typedef struct ++{ ++ Elf32_Word n_namesz; /* Length of the note's name. */ ++ Elf32_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf32_Word n_type; /* Type of the note. */ ++} Elf32_Nhdr; ++ ++typedef struct ++{ ++ Elf64_Word n_namesz; /* Length of the note's name. */ ++ Elf64_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf64_Word n_type; /* Type of the note. */ ++} Elf64_Nhdr; ++ ++/* Known names of notes. */ ++ ++/* Solaris entries in the note section have this name. */ ++#define ELF_NOTE_SOLARIS "SUNW Solaris" ++ ++/* Note entries for GNU systems have this name. */ ++#define ELF_NOTE_GNU "GNU" ++ ++ ++/* Defined types of notes for Solaris. */ ++ ++/* Value of descriptor (one word) is desired pagesize for the binary. */ ++#define ELF_NOTE_PAGESIZE_HINT 1 ++ ++ ++/* Defined note types for GNU systems. */ ++ ++/* ABI information. The descriptor consists of words: ++ word 0: OS descriptor ++ word 1: major version of the ABI ++ word 2: minor version of the ABI ++ word 3: subminor version of the ABI ++*/ ++#define NT_GNU_ABI_TAG 1 ++#define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ ++ ++/* Known OSes. These values can appear in word 0 of an ++ NT_GNU_ABI_TAG note section entry. */ ++#define ELF_NOTE_OS_LINUX 0 ++#define ELF_NOTE_OS_GNU 1 ++#define ELF_NOTE_OS_SOLARIS2 2 ++#define ELF_NOTE_OS_FREEBSD 3 ++ ++/* Synthetic hwcap information. The descriptor begins with two words: ++ word 0: number of entries ++ word 1: bitmask of enabled entries ++ Then follow variable-length entries, one byte followed by a ++ '\0'-terminated hwcap name string. The byte gives the bit ++ number to test if enabled, (1U << bit) & bitmask. */ ++#define NT_GNU_HWCAP 2 ++ ++/* Build ID bits as generated by ld --build-id. ++ The descriptor consists of any nonzero number of bytes. */ ++#define NT_GNU_BUILD_ID 3 ++ ++/* Version note generated by GNU gold containing a version string. */ ++#define NT_GNU_GOLD_VERSION 4 ++ ++ ++/* Move records. */ ++typedef struct ++{ ++ Elf32_Xword m_value; /* Symbol value. */ ++ Elf32_Word m_info; /* Size and index. */ ++ Elf32_Word m_poffset; /* Symbol offset. */ ++ Elf32_Half m_repeat; /* Repeat count. */ ++ Elf32_Half m_stride; /* Stride info. */ ++} Elf32_Move; ++ ++typedef struct ++{ ++ Elf64_Xword m_value; /* Symbol value. */ ++ Elf64_Xword m_info; /* Size and index. */ ++ Elf64_Xword m_poffset; /* Symbol offset. */ ++ Elf64_Half m_repeat; /* Repeat count. */ ++ Elf64_Half m_stride; /* Stride info. */ ++} Elf64_Move; ++ ++/* Macro to construct move records. */ ++#define ELF32_M_SYM(info) ((info) >> 8) ++#define ELF32_M_SIZE(info) ((unsigned char) (info)) ++#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) ++ ++#define ELF64_M_SYM(info) ELF32_M_SYM (info) ++#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) ++#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) ++ ++ ++/* Motorola 68k specific definitions. */ ++ ++/* Values for Elf32_Ehdr.e_flags. */ ++#define EF_CPU32 0x00810000 ++ ++/* m68k relocs. */ ++ ++#define R_68K_NONE 0 /* No reloc */ ++#define R_68K_32 1 /* Direct 32 bit */ ++#define R_68K_16 2 /* Direct 16 bit */ ++#define R_68K_8 3 /* Direct 8 bit */ ++#define R_68K_PC32 4 /* PC relative 32 bit */ ++#define R_68K_PC16 5 /* PC relative 16 bit */ ++#define R_68K_PC8 6 /* PC relative 8 bit */ ++#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ ++#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ ++#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ ++#define R_68K_GOT32O 10 /* 32 bit GOT offset */ ++#define R_68K_GOT16O 11 /* 16 bit GOT offset */ ++#define R_68K_GOT8O 12 /* 8 bit GOT offset */ ++#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ ++#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ ++#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ ++#define R_68K_PLT32O 16 /* 32 bit PLT offset */ ++#define R_68K_PLT16O 17 /* 16 bit PLT offset */ ++#define R_68K_PLT8O 18 /* 8 bit PLT offset */ ++#define R_68K_COPY 19 /* Copy symbol at runtime */ ++#define R_68K_GLOB_DAT 20 /* Create GOT entry */ ++#define R_68K_JMP_SLOT 21 /* Create PLT entry */ ++#define R_68K_RELATIVE 22 /* Adjust by program base */ ++#define R_68K_TLS_GD32 25 /* 32 bit GOT offset for GD */ ++#define R_68K_TLS_GD16 26 /* 16 bit GOT offset for GD */ ++#define R_68K_TLS_GD8 27 /* 8 bit GOT offset for GD */ ++#define R_68K_TLS_LDM32 28 /* 32 bit GOT offset for LDM */ ++#define R_68K_TLS_LDM16 29 /* 16 bit GOT offset for LDM */ ++#define R_68K_TLS_LDM8 30 /* 8 bit GOT offset for LDM */ ++#define R_68K_TLS_LDO32 31 /* 32 bit module-relative offset */ ++#define R_68K_TLS_LDO16 32 /* 16 bit module-relative offset */ ++#define R_68K_TLS_LDO8 33 /* 8 bit module-relative offset */ ++#define R_68K_TLS_IE32 34 /* 32 bit GOT offset for IE */ ++#define R_68K_TLS_IE16 35 /* 16 bit GOT offset for IE */ ++#define R_68K_TLS_IE8 36 /* 8 bit GOT offset for IE */ ++#define R_68K_TLS_LE32 37 /* 32 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_LE16 38 /* 16 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_LE8 39 /* 8 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_DTPMOD32 40 /* 32 bit module number */ ++#define R_68K_TLS_DTPREL32 41 /* 32 bit module-relative offset */ ++#define R_68K_TLS_TPREL32 42 /* 32 bit TP-relative offset */ ++/* Keep this the last entry. */ ++#define R_68K_NUM 43 ++ ++/* Intel 80386 specific definitions. */ ++ ++/* i386 relocs. */ ++ ++#define R_386_NONE 0 /* No reloc */ ++#define R_386_32 1 /* Direct 32 bit */ ++#define R_386_PC32 2 /* PC relative 32 bit */ ++#define R_386_GOT32 3 /* 32 bit GOT entry */ ++#define R_386_PLT32 4 /* 32 bit PLT address */ ++#define R_386_COPY 5 /* Copy symbol at runtime */ ++#define R_386_GLOB_DAT 6 /* Create GOT entry */ ++#define R_386_JMP_SLOT 7 /* Create PLT entry */ ++#define R_386_RELATIVE 8 /* Adjust by program base */ ++#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ ++#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ ++#define R_386_32PLT 11 ++#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ ++#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS ++ block offset */ ++#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block ++ offset */ ++#define R_386_TLS_LE 17 /* Offset relative to static TLS ++ block */ ++#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of ++ general dynamic thread local data */ ++#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of ++ local dynamic thread local data ++ in LE code */ ++#define R_386_16 20 ++#define R_386_PC16 21 ++#define R_386_8 22 ++#define R_386_PC8 23 ++#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic ++ thread local data */ ++#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ ++#define R_386_TLS_GD_CALL 26 /* Relocation for call to ++ __tls_get_addr() */ ++#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ ++#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic ++ thread local data in LE code */ ++#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ ++#define R_386_TLS_LDM_CALL 30 /* Relocation for call to ++ __tls_get_addr() in LDM code */ ++#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ ++#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ ++#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS ++ block offset */ ++#define R_386_TLS_LE_32 34 /* Negated offset relative to static ++ TLS block */ ++#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ ++#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ ++#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ ++/* 38? */ ++#define R_386_TLS_GOTDESC 39 /* GOT offset for TLS descriptor. */ ++#define R_386_TLS_DESC_CALL 40 /* Marker of call through TLS ++ descriptor for ++ relaxation. */ ++#define R_386_TLS_DESC 41 /* TLS descriptor containing ++ pointer to code and to ++ argument, returning the TLS ++ offset for the symbol. */ ++#define R_386_IRELATIVE 42 /* Adjust indirectly by program base */ ++/* Keep this the last entry. */ ++#define R_386_NUM 43 ++ ++/* SUN SPARC specific definitions. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ ++ ++/* Values for Elf64_Ehdr.e_flags. */ ++ ++#define EF_SPARCV9_MM 3 ++#define EF_SPARCV9_TSO 0 ++#define EF_SPARCV9_PSO 1 ++#define EF_SPARCV9_RMO 2 ++#define EF_SPARC_LEDATA 0x800000 /* little endian data */ ++#define EF_SPARC_EXT_MASK 0xFFFF00 ++#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ ++#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ ++#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ ++#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ ++ ++/* SPARC relocs. */ ++ ++#define R_SPARC_NONE 0 /* No reloc */ ++#define R_SPARC_8 1 /* Direct 8 bit */ ++#define R_SPARC_16 2 /* Direct 16 bit */ ++#define R_SPARC_32 3 /* Direct 32 bit */ ++#define R_SPARC_DISP8 4 /* PC relative 8 bit */ ++#define R_SPARC_DISP16 5 /* PC relative 16 bit */ ++#define R_SPARC_DISP32 6 /* PC relative 32 bit */ ++#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ ++#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ ++#define R_SPARC_HI22 9 /* High 22 bit */ ++#define R_SPARC_22 10 /* Direct 22 bit */ ++#define R_SPARC_13 11 /* Direct 13 bit */ ++#define R_SPARC_LO10 12 /* Truncated 10 bit */ ++#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ ++#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ ++#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ ++#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ ++#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ ++#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ ++#define R_SPARC_COPY 19 /* Copy symbol at runtime */ ++#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ ++#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ ++#define R_SPARC_RELATIVE 22 /* Adjust by program base */ ++#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ ++ ++/* Additional Sparc64 relocs. */ ++ ++#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ ++#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ ++#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ ++#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ ++#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ ++#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ ++#define R_SPARC_10 30 /* Direct 10 bit */ ++#define R_SPARC_11 31 /* Direct 11 bit */ ++#define R_SPARC_64 32 /* Direct 64 bit */ ++#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ ++#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ ++#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ ++#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ ++#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ ++#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ ++#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ ++#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ ++#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ ++#define R_SPARC_GLOB_JMP 42 /* was part of v9 ABI but was removed */ ++#define R_SPARC_7 43 /* Direct 7 bit */ ++#define R_SPARC_5 44 /* Direct 5 bit */ ++#define R_SPARC_6 45 /* Direct 6 bit */ ++#define R_SPARC_DISP64 46 /* PC relative 64 bit */ ++#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ ++#define R_SPARC_HIX22 48 /* High 22 bit complemented */ ++#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ ++#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ ++#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ ++#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ ++#define R_SPARC_REGISTER 53 /* Global register usage */ ++#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ ++#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ ++#define R_SPARC_TLS_GD_HI22 56 ++#define R_SPARC_TLS_GD_LO10 57 ++#define R_SPARC_TLS_GD_ADD 58 ++#define R_SPARC_TLS_GD_CALL 59 ++#define R_SPARC_TLS_LDM_HI22 60 ++#define R_SPARC_TLS_LDM_LO10 61 ++#define R_SPARC_TLS_LDM_ADD 62 ++#define R_SPARC_TLS_LDM_CALL 63 ++#define R_SPARC_TLS_LDO_HIX22 64 ++#define R_SPARC_TLS_LDO_LOX10 65 ++#define R_SPARC_TLS_LDO_ADD 66 ++#define R_SPARC_TLS_IE_HI22 67 ++#define R_SPARC_TLS_IE_LO10 68 ++#define R_SPARC_TLS_IE_LD 69 ++#define R_SPARC_TLS_IE_LDX 70 ++#define R_SPARC_TLS_IE_ADD 71 ++#define R_SPARC_TLS_LE_HIX22 72 ++#define R_SPARC_TLS_LE_LOX10 73 ++#define R_SPARC_TLS_DTPMOD32 74 ++#define R_SPARC_TLS_DTPMOD64 75 ++#define R_SPARC_TLS_DTPOFF32 76 ++#define R_SPARC_TLS_DTPOFF64 77 ++#define R_SPARC_TLS_TPOFF32 78 ++#define R_SPARC_TLS_TPOFF64 79 ++#define R_SPARC_GOTDATA_HIX22 80 ++#define R_SPARC_GOTDATA_LOX10 81 ++#define R_SPARC_GOTDATA_OP_HIX22 82 ++#define R_SPARC_GOTDATA_OP_LOX10 83 ++#define R_SPARC_GOTDATA_OP 84 ++#define R_SPARC_H34 85 ++#define R_SPARC_SIZE32 86 ++#define R_SPARC_SIZE64 87 ++#define R_SPARC_WDISP10 88 ++#define R_SPARC_JMP_IREL 248 ++#define R_SPARC_IRELATIVE 249 ++#define R_SPARC_GNU_VTINHERIT 250 ++#define R_SPARC_GNU_VTENTRY 251 ++#define R_SPARC_REV32 252 ++/* Keep this the last entry. */ ++#define R_SPARC_NUM 253 ++ ++/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ ++ ++#define DT_SPARC_REGISTER 0x70000001 ++#define DT_SPARC_NUM 2 ++ ++/* MIPS R3000 specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ ++#define EF_MIPS_PIC 2 /* Contains PIC code */ ++#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ ++#define EF_MIPS_XGOT 8 ++#define EF_MIPS_64BIT_WHIRL 16 ++#define EF_MIPS_ABI2 32 ++#define EF_MIPS_ABI_ON32 64 ++#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ ++ ++/* Legal values for MIPS architecture level. */ ++ ++#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* The following are non-official names and should not be used. */ ++ ++#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* Special section indices. */ ++ ++#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ ++#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ ++#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ ++#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ ++#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ ++#define SHT_MIPS_MSYM 0x70000001 ++#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ ++#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ ++#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ ++#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ ++#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ ++#define SHT_MIPS_PACKAGE 0x70000007 ++#define SHT_MIPS_PACKSYM 0x70000008 ++#define SHT_MIPS_RELD 0x70000009 ++#define SHT_MIPS_IFACE 0x7000000b ++#define SHT_MIPS_CONTENT 0x7000000c ++#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ ++#define SHT_MIPS_SHDR 0x70000010 ++#define SHT_MIPS_FDESC 0x70000011 ++#define SHT_MIPS_EXTSYM 0x70000012 ++#define SHT_MIPS_DENSE 0x70000013 ++#define SHT_MIPS_PDESC 0x70000014 ++#define SHT_MIPS_LOCSYM 0x70000015 ++#define SHT_MIPS_AUXSYM 0x70000016 ++#define SHT_MIPS_OPTSYM 0x70000017 ++#define SHT_MIPS_LOCSTR 0x70000018 ++#define SHT_MIPS_LINE 0x70000019 ++#define SHT_MIPS_RFDESC 0x7000001a ++#define SHT_MIPS_DELTASYM 0x7000001b ++#define SHT_MIPS_DELTAINST 0x7000001c ++#define SHT_MIPS_DELTACLASS 0x7000001d ++#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ ++#define SHT_MIPS_DELTADECL 0x7000001f ++#define SHT_MIPS_SYMBOL_LIB 0x70000020 ++#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ ++#define SHT_MIPS_TRANSLATE 0x70000022 ++#define SHT_MIPS_PIXIE 0x70000023 ++#define SHT_MIPS_XLATE 0x70000024 ++#define SHT_MIPS_XLATE_DEBUG 0x70000025 ++#define SHT_MIPS_WHIRL 0x70000026 ++#define SHT_MIPS_EH_REGION 0x70000027 ++#define SHT_MIPS_XLATE_OLD 0x70000028 ++#define SHT_MIPS_PDR_EXCEPTION 0x70000029 ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ ++#define SHF_MIPS_MERGE 0x20000000 ++#define SHF_MIPS_ADDR 0x40000000 ++#define SHF_MIPS_STRINGS 0x80000000 ++#define SHF_MIPS_NOSTRIP 0x08000000 ++#define SHF_MIPS_LOCAL 0x04000000 ++#define SHF_MIPS_NAMES 0x02000000 ++#define SHF_MIPS_NODUPE 0x01000000 ++ ++ ++/* Symbol tables. */ ++ ++/* MIPS specific values for `st_other'. */ ++#define STO_MIPS_DEFAULT 0x0 ++#define STO_MIPS_INTERNAL 0x1 ++#define STO_MIPS_HIDDEN 0x2 ++#define STO_MIPS_PROTECTED 0x3 ++#define STO_MIPS_PLT 0x8 ++#define STO_MIPS_SC_ALIGN_UNUSED 0xff ++ ++/* MIPS specific values for `st_info'. */ ++#define STB_MIPS_SPLIT_COMMON 13 ++ ++/* Entries found in sections of type SHT_MIPS_GPTAB. */ ++ ++typedef union ++{ ++ struct ++ { ++ Elf32_Word gt_current_g_value; /* -G value used for compilation */ ++ Elf32_Word gt_unused; /* Not used */ ++ } gt_header; /* First entry in section */ ++ struct ++ { ++ Elf32_Word gt_g_value; /* If this value were used for -G */ ++ Elf32_Word gt_bytes; /* This many bytes would be used */ ++ } gt_entry; /* Subsequent entries in section */ ++} Elf32_gptab; ++ ++/* Entry found in sections of type SHT_MIPS_REGINFO. */ ++ ++typedef struct ++{ ++ Elf32_Word ri_gprmask; /* General registers used */ ++ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ ++ Elf32_Sword ri_gp_value; /* $gp register value */ ++} Elf32_RegInfo; ++ ++/* Entries found in sections of type SHT_MIPS_OPTIONS. */ ++ ++typedef struct ++{ ++ unsigned char kind; /* Determines interpretation of the ++ variable part of descriptor. */ ++ unsigned char size; /* Size of descriptor, including header. */ ++ Elf32_Section section; /* Section header index of section affected, ++ 0 for global options. */ ++ Elf32_Word info; /* Kind-specific information. */ ++} Elf_Options; ++ ++/* Values for `kind' field in Elf_Options. */ ++ ++#define ODK_NULL 0 /* Undefined. */ ++#define ODK_REGINFO 1 /* Register usage information. */ ++#define ODK_EXCEPTIONS 2 /* Exception processing options. */ ++#define ODK_PAD 3 /* Section padding options. */ ++#define ODK_HWPATCH 4 /* Hardware workarounds performed */ ++#define ODK_FILL 5 /* record the fill value used by the linker. */ ++#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ ++#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ ++#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ ++ ++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ ++ ++#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ ++#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ ++#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ ++#define OEX_SMM 0x20000 /* Force sequential memory mode? */ ++#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ ++#define OEX_PRECISEFP OEX_FPDBUG ++#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ ++ ++#define OEX_FPU_INVAL 0x10 ++#define OEX_FPU_DIV0 0x08 ++#define OEX_FPU_OFLO 0x04 ++#define OEX_FPU_UFLO 0x02 ++#define OEX_FPU_INEX 0x01 ++ ++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ ++ ++#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ ++#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ ++#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ ++#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ ++ ++#define OPAD_PREFIX 0x1 ++#define OPAD_POSTFIX 0x2 ++#define OPAD_SYMBOL 0x4 ++ ++/* Entry found in `.options' section. */ ++ ++typedef struct ++{ ++ Elf32_Word hwp_flags1; /* Extra flags. */ ++ Elf32_Word hwp_flags2; /* Extra flags. */ ++} Elf_Options_Hw; ++ ++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ ++ ++#define OHWA0_R4KEOP_CHECKED 0x00000001 ++#define OHWA1_R4KEOP_CLEAN 0x00000002 ++ ++/* MIPS relocs. */ ++ ++#define R_MIPS_NONE 0 /* No reloc */ ++#define R_MIPS_16 1 /* Direct 16 bit */ ++#define R_MIPS_32 2 /* Direct 32 bit */ ++#define R_MIPS_REL32 3 /* PC relative 32 bit */ ++#define R_MIPS_26 4 /* Direct 26 bit shifted */ ++#define R_MIPS_HI16 5 /* High 16 bit */ ++#define R_MIPS_LO16 6 /* Low 16 bit */ ++#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ ++#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ ++#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ ++#define R_MIPS_PC16 10 /* PC relative 16 bit */ ++#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ ++#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ ++ ++#define R_MIPS_SHIFT5 16 ++#define R_MIPS_SHIFT6 17 ++#define R_MIPS_64 18 ++#define R_MIPS_GOT_DISP 19 ++#define R_MIPS_GOT_PAGE 20 ++#define R_MIPS_GOT_OFST 21 ++#define R_MIPS_GOT_HI16 22 ++#define R_MIPS_GOT_LO16 23 ++#define R_MIPS_SUB 24 ++#define R_MIPS_INSERT_A 25 ++#define R_MIPS_INSERT_B 26 ++#define R_MIPS_DELETE 27 ++#define R_MIPS_HIGHER 28 ++#define R_MIPS_HIGHEST 29 ++#define R_MIPS_CALL_HI16 30 ++#define R_MIPS_CALL_LO16 31 ++#define R_MIPS_SCN_DISP 32 ++#define R_MIPS_REL16 33 ++#define R_MIPS_ADD_IMMEDIATE 34 ++#define R_MIPS_PJUMP 35 ++#define R_MIPS_RELGOT 36 ++#define R_MIPS_JALR 37 ++#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ ++#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ ++#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ ++#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ ++#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ ++#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ ++#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ ++#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ ++#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ ++#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ ++#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ ++#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ ++#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ ++#define R_MIPS_GLOB_DAT 51 ++#define R_MIPS_COPY 126 ++#define R_MIPS_JUMP_SLOT 127 ++/* Keep this the last entry. */ ++#define R_MIPS_NUM 128 ++ ++/* Legal values for p_type field of Elf32_Phdr. */ ++ ++#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ ++#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ ++#define PT_MIPS_OPTIONS 0x70000002 ++ ++/* Special program header types. */ ++ ++#define PF_MIPS_LOCAL 0x10000000 ++ ++/* Legal values for d_tag field of Elf32_Dyn. */ ++ ++#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ ++#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ ++#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ ++#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ ++#define DT_MIPS_FLAGS 0x70000005 /* Flags */ ++#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ ++#define DT_MIPS_MSYM 0x70000007 ++#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ ++#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ ++#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ ++#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ ++#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ ++#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ ++#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ ++#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ ++#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ ++#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ ++#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ ++#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in ++ DT_MIPS_DELTA_CLASS. */ ++#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ ++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in ++ DT_MIPS_DELTA_INSTANCE. */ ++#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ ++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in ++ DT_MIPS_DELTA_RELOC. */ ++#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta ++ relocations refer to. */ ++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in ++ DT_MIPS_DELTA_SYM. */ ++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the ++ class declaration. */ ++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in ++ DT_MIPS_DELTA_CLASSSYM. */ ++#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ ++#define DT_MIPS_PIXIE_INIT 0x70000023 ++#define DT_MIPS_SYMBOL_LIB 0x70000024 ++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 ++#define DT_MIPS_LOCAL_GOTIDX 0x70000026 ++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 ++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 ++#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ ++#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ ++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b ++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ ++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve ++ function stored in GOT. */ ++#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added ++ by rld on dlopen() calls. */ ++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ ++#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ ++#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ ++/* The address of .got.plt in an executable using the new non-PIC ABI. */ ++#define DT_MIPS_PLTGOT 0x70000032 ++/* The base of the PLT in an executable using the new non-PIC ABI if that ++ PLT is writable. For a non-writable PLT, this is omitted or has a zero ++ value. */ ++#define DT_MIPS_RWPLT 0x70000034 ++#define DT_MIPS_NUM 0x35 ++ ++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ ++ ++#define RHF_NONE 0 /* No flags */ ++#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ ++#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ ++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ ++#define RHF_NO_MOVE (1 << 3) ++#define RHF_SGI_ONLY (1 << 4) ++#define RHF_GUARANTEE_INIT (1 << 5) ++#define RHF_DELTA_C_PLUS_PLUS (1 << 6) ++#define RHF_GUARANTEE_START_INIT (1 << 7) ++#define RHF_PIXIE (1 << 8) ++#define RHF_DEFAULT_DELAY_LOAD (1 << 9) ++#define RHF_REQUICKSTART (1 << 10) ++#define RHF_REQUICKSTARTED (1 << 11) ++#define RHF_CORD (1 << 12) ++#define RHF_NO_UNRES_UNDEF (1 << 13) ++#define RHF_RLD_ORDER_SAFE (1 << 14) ++ ++/* Entries found in sections of type SHT_MIPS_LIBLIST. */ ++ ++typedef struct ++{ ++ Elf32_Word l_name; /* Name (string table index) */ ++ Elf32_Word l_time_stamp; /* Timestamp */ ++ Elf32_Word l_checksum; /* Checksum */ ++ Elf32_Word l_version; /* Interface version */ ++ Elf32_Word l_flags; /* Flags */ ++} Elf32_Lib; ++ ++typedef struct ++{ ++ Elf64_Word l_name; /* Name (string table index) */ ++ Elf64_Word l_time_stamp; /* Timestamp */ ++ Elf64_Word l_checksum; /* Checksum */ ++ Elf64_Word l_version; /* Interface version */ ++ Elf64_Word l_flags; /* Flags */ ++} Elf64_Lib; ++ ++ ++/* Legal values for l_flags. */ ++ ++#define LL_NONE 0 ++#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ ++#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ ++#define LL_REQUIRE_MINOR (1 << 2) ++#define LL_EXPORTS (1 << 3) ++#define LL_DELAY_LOAD (1 << 4) ++#define LL_DELTA (1 << 5) ++ ++/* Entries found in sections of type SHT_MIPS_CONFLICT. */ ++ ++typedef Elf32_Addr Elf32_Conflict; ++ ++ ++/* HPPA specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ ++#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ ++#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ ++#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ ++#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch ++ prediction. */ ++#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ ++#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ ++ ++/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ ++ ++#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ ++#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ ++#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ ++ ++/* Additional section indeces. */ ++ ++#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared ++ symbols in ANSI C. */ ++#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ ++#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ ++#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ ++#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ ++#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ ++ ++#define STT_HP_OPAQUE (STT_LOOS + 0x1) ++#define STT_HP_STUB (STT_LOOS + 0x2) ++ ++/* HPPA relocs. */ ++ ++#define R_PARISC_NONE 0 /* No reloc. */ ++#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ ++#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ ++#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ ++#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ ++#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ ++#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ ++#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ ++#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ ++#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ ++#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ ++#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ ++#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ ++#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ ++#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ ++#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ ++#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ ++#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ ++#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ ++#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ ++#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ ++#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ ++#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ ++#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ ++#define R_PARISC_FPTR64 64 /* 64 bits function address. */ ++#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ ++#define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ ++#define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ ++#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ ++#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ ++#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ ++#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ ++#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ ++#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ ++#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ ++#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ ++#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ ++#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ ++#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ ++#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ ++#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ ++#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ ++#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LORESERVE 128 ++#define R_PARISC_COPY 128 /* Copy relocation. */ ++#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ ++#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ ++#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ ++#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ ++#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ ++#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ ++#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ ++#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ ++#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_GNU_VTENTRY 232 ++#define R_PARISC_GNU_VTINHERIT 233 ++#define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ ++#define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ ++#define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ ++#define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ ++#define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ ++#define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ ++#define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ ++#define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ ++#define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ ++#define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ ++#define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ ++#define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ ++#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L ++#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R ++#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L ++#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R ++#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 ++#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 ++#define R_PARISC_HIRESERVE 255 ++ ++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PT_HP_TLS (PT_LOOS + 0x0) ++#define PT_HP_CORE_NONE (PT_LOOS + 0x1) ++#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) ++#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) ++#define PT_HP_CORE_COMM (PT_LOOS + 0x4) ++#define PT_HP_CORE_PROC (PT_LOOS + 0x5) ++#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) ++#define PT_HP_CORE_STACK (PT_LOOS + 0x7) ++#define PT_HP_CORE_SHM (PT_LOOS + 0x8) ++#define PT_HP_CORE_MMF (PT_LOOS + 0x9) ++#define PT_HP_PARALLEL (PT_LOOS + 0x10) ++#define PT_HP_FASTBIND (PT_LOOS + 0x11) ++#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) ++#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) ++#define PT_HP_STACK (PT_LOOS + 0x14) ++ ++#define PT_PARISC_ARCHEXT 0x70000000 ++#define PT_PARISC_UNWIND 0x70000001 ++ ++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PF_PARISC_SBP 0x08000000 ++ ++#define PF_HP_PAGE_SIZE 0x00100000 ++#define PF_HP_FAR_SHARED 0x00200000 ++#define PF_HP_NEAR_SHARED 0x00400000 ++#define PF_HP_CODE 0x01000000 ++#define PF_HP_MODIFY 0x02000000 ++#define PF_HP_LAZYSWAP 0x04000000 ++#define PF_HP_SBP 0x08000000 ++ ++ ++/* Alpha specific definitions. */ ++ ++/* Legal values for e_flags field of Elf64_Ehdr. */ ++ ++#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ ++#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ ++ ++/* Legal values for sh_type field of Elf64_Shdr. */ ++ ++/* These two are primerily concerned with ECOFF debugging info. */ ++#define SHT_ALPHA_DEBUG 0x70000001 ++#define SHT_ALPHA_REGINFO 0x70000002 ++ ++/* Legal values for sh_flags field of Elf64_Shdr. */ ++ ++#define SHF_ALPHA_GPREL 0x10000000 ++ ++/* Legal values for st_other field of Elf64_Sym. */ ++#define STO_ALPHA_NOPV 0x80 /* No PV required. */ ++#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ ++ ++/* Alpha relocs. */ ++ ++#define R_ALPHA_NONE 0 /* No reloc */ ++#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ ++#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ ++#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ ++#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ ++#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ ++#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ ++#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ ++#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ ++#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ ++#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ ++#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ ++#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ ++#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ ++#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ ++#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ ++#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ ++#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ ++#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ ++#define R_ALPHA_TLS_GD_HI 28 ++#define R_ALPHA_TLSGD 29 ++#define R_ALPHA_TLS_LDM 30 ++#define R_ALPHA_DTPMOD64 31 ++#define R_ALPHA_GOTDTPREL 32 ++#define R_ALPHA_DTPREL64 33 ++#define R_ALPHA_DTPRELHI 34 ++#define R_ALPHA_DTPRELLO 35 ++#define R_ALPHA_DTPREL16 36 ++#define R_ALPHA_GOTTPREL 37 ++#define R_ALPHA_TPREL64 38 ++#define R_ALPHA_TPRELHI 39 ++#define R_ALPHA_TPRELLO 40 ++#define R_ALPHA_TPREL16 41 ++/* Keep this the last entry. */ ++#define R_ALPHA_NUM 46 ++ ++/* Magic values of the LITUSE relocation addend. */ ++#define LITUSE_ALPHA_ADDR 0 ++#define LITUSE_ALPHA_BASE 1 ++#define LITUSE_ALPHA_BYTOFF 2 ++#define LITUSE_ALPHA_JSR 3 ++#define LITUSE_ALPHA_TLS_GD 4 ++#define LITUSE_ALPHA_TLS_LDM 5 ++ ++/* Legal values for d_tag of Elf64_Dyn. */ ++#define DT_ALPHA_PLTRO (DT_LOPROC + 0) ++#define DT_ALPHA_NUM 1 ++ ++/* PowerPC specific declarations */ ++ ++/* Values for Elf32/64_Ehdr.e_flags. */ ++#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ ++ ++/* Cygnus local bits below */ ++#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ ++#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib ++ flag */ ++ ++/* PowerPC relocations defined by the ABIs */ ++#define R_PPC_NONE 0 ++#define R_PPC_ADDR32 1 /* 32bit absolute address */ ++#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ ++#define R_PPC_ADDR16 3 /* 16bit absolute address */ ++#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ ++#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ ++#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ ++#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ ++#define R_PPC_ADDR14_BRTAKEN 8 ++#define R_PPC_ADDR14_BRNTAKEN 9 ++#define R_PPC_REL24 10 /* PC relative 26 bit */ ++#define R_PPC_REL14 11 /* PC relative 16 bit */ ++#define R_PPC_REL14_BRTAKEN 12 ++#define R_PPC_REL14_BRNTAKEN 13 ++#define R_PPC_GOT16 14 ++#define R_PPC_GOT16_LO 15 ++#define R_PPC_GOT16_HI 16 ++#define R_PPC_GOT16_HA 17 ++#define R_PPC_PLTREL24 18 ++#define R_PPC_COPY 19 ++#define R_PPC_GLOB_DAT 20 ++#define R_PPC_JMP_SLOT 21 ++#define R_PPC_RELATIVE 22 ++#define R_PPC_LOCAL24PC 23 ++#define R_PPC_UADDR32 24 ++#define R_PPC_UADDR16 25 ++#define R_PPC_REL32 26 ++#define R_PPC_PLT32 27 ++#define R_PPC_PLTREL32 28 ++#define R_PPC_PLT16_LO 29 ++#define R_PPC_PLT16_HI 30 ++#define R_PPC_PLT16_HA 31 ++#define R_PPC_SDAREL16 32 ++#define R_PPC_SECTOFF 33 ++#define R_PPC_SECTOFF_LO 34 ++#define R_PPC_SECTOFF_HI 35 ++#define R_PPC_SECTOFF_HA 36 ++ ++/* PowerPC relocations defined for the TLS access ABI. */ ++#define R_PPC_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ ++#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ ++#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ ++#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ ++#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ ++#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ ++#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ ++#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ ++#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ ++ ++/* The remaining relocs are from the Embedded ELF ABI, and are not ++ in the SVR4 ELF ABI. */ ++#define R_PPC_EMB_NADDR32 101 ++#define R_PPC_EMB_NADDR16 102 ++#define R_PPC_EMB_NADDR16_LO 103 ++#define R_PPC_EMB_NADDR16_HI 104 ++#define R_PPC_EMB_NADDR16_HA 105 ++#define R_PPC_EMB_SDAI16 106 ++#define R_PPC_EMB_SDA2I16 107 ++#define R_PPC_EMB_SDA2REL 108 ++#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ ++#define R_PPC_EMB_MRKREF 110 ++#define R_PPC_EMB_RELSEC16 111 ++#define R_PPC_EMB_RELST_LO 112 ++#define R_PPC_EMB_RELST_HI 113 ++#define R_PPC_EMB_RELST_HA 114 ++#define R_PPC_EMB_BIT_FLD 115 ++#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ ++ ++/* Diab tool relocations. */ ++#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ ++#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ ++#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ ++#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ ++#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ ++#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ ++ ++/* GNU extension to support local ifunc. */ ++#define R_PPC_IRELATIVE 248 ++ ++/* GNU relocs used in PIC code sequences. */ ++#define R_PPC_REL16 249 /* half16 (sym+add-.) */ ++#define R_PPC_REL16_LO 250 /* half16 (sym+add-.)@l */ ++#define R_PPC_REL16_HI 251 /* half16 (sym+add-.)@h */ ++#define R_PPC_REL16_HA 252 /* half16 (sym+add-.)@ha */ ++ ++/* This is a phony reloc to handle any old fashioned TOC16 references ++ that may still be in object files. */ ++#define R_PPC_TOC16 255 ++ ++/* PowerPC specific values for the Dyn d_tag field. */ ++#define DT_PPC_GOT (DT_LOPROC + 0) ++#define DT_PPC_NUM 1 ++ ++/* PowerPC64 relocations defined by the ABIs */ ++#define R_PPC64_NONE R_PPC_NONE ++#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ ++#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ ++#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ ++#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ ++#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ ++#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ ++#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ ++#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN ++#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN ++#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ ++#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ ++#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN ++#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN ++#define R_PPC64_GOT16 R_PPC_GOT16 ++#define R_PPC64_GOT16_LO R_PPC_GOT16_LO ++#define R_PPC64_GOT16_HI R_PPC_GOT16_HI ++#define R_PPC64_GOT16_HA R_PPC_GOT16_HA ++ ++#define R_PPC64_COPY R_PPC_COPY ++#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT ++#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT ++#define R_PPC64_RELATIVE R_PPC_RELATIVE ++ ++#define R_PPC64_UADDR32 R_PPC_UADDR32 ++#define R_PPC64_UADDR16 R_PPC_UADDR16 ++#define R_PPC64_REL32 R_PPC_REL32 ++#define R_PPC64_PLT32 R_PPC_PLT32 ++#define R_PPC64_PLTREL32 R_PPC_PLTREL32 ++#define R_PPC64_PLT16_LO R_PPC_PLT16_LO ++#define R_PPC64_PLT16_HI R_PPC_PLT16_HI ++#define R_PPC64_PLT16_HA R_PPC_PLT16_HA ++ ++#define R_PPC64_SECTOFF R_PPC_SECTOFF ++#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO ++#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ++#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA ++#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ ++#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ ++#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ ++#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ ++#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ ++#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ ++#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ ++#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ ++#define R_PPC64_PLT64 45 /* doubleword64 L + A */ ++#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ ++#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ ++#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ ++#define R_PPC64_TOC 51 /* doubleword64 .TOC */ ++#define R_PPC64_PLTGOT16 52 /* half16* M + A */ ++#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ ++#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ ++#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ ++ ++#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ ++#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ ++#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ ++#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ ++#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ ++#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ ++#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ ++#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ ++#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ ++#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ ++#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ ++ ++/* PowerPC64 relocations defined for the TLS access ABI. */ ++#define R_PPC64_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ ++#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ ++#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ ++#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ ++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ ++#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ ++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ ++#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ ++#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ ++#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ ++#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ ++#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ ++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ ++#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ ++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ ++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ ++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ ++ ++/* GNU extension to support local ifunc. */ ++#define R_PPC64_JMP_IREL 247 ++#define R_PPC64_IRELATIVE 248 ++#define R_PPC64_REL16 249 /* half16 (sym+add-.) */ ++#define R_PPC64_REL16_LO 250 /* half16 (sym+add-.)@l */ ++#define R_PPC64_REL16_HI 251 /* half16 (sym+add-.)@h */ ++#define R_PPC64_REL16_HA 252 /* half16 (sym+add-.)@ha */ ++ ++/* PowerPC64 specific values for the Dyn d_tag field. */ ++#define DT_PPC64_GLINK (DT_LOPROC + 0) ++#define DT_PPC64_OPD (DT_LOPROC + 1) ++#define DT_PPC64_OPDSZ (DT_LOPROC + 2) ++#define DT_PPC64_NUM 3 ++ ++ ++/* ARM specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_ARM_RELEXEC 0x01 ++#define EF_ARM_HASENTRY 0x02 ++#define EF_ARM_INTERWORK 0x04 ++#define EF_ARM_APCS_26 0x08 ++#define EF_ARM_APCS_FLOAT 0x10 ++#define EF_ARM_PIC 0x20 ++#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ ++#define EF_ARM_NEW_ABI 0x80 ++#define EF_ARM_OLD_ABI 0x100 ++#define EF_ARM_SOFT_FLOAT 0x200 ++#define EF_ARM_VFP_FLOAT 0x400 ++#define EF_ARM_MAVERICK_FLOAT 0x800 ++ ++ ++/* Other constants defined in the ARM ELF spec. version B-01. */ ++/* NB. These conflict with values defined above. */ ++#define EF_ARM_SYMSARESORTED 0x04 ++#define EF_ARM_DYNSYMSUSESEGIDX 0x08 ++#define EF_ARM_MAPSYMSFIRST 0x10 ++#define EF_ARM_EABIMASK 0XFF000000 ++ ++/* Constants defined in AAELF. */ ++#define EF_ARM_BE8 0x00800000 ++#define EF_ARM_LE8 0x00400000 ++ ++#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) ++#define EF_ARM_EABI_UNKNOWN 0x00000000 ++#define EF_ARM_EABI_VER1 0x01000000 ++#define EF_ARM_EABI_VER2 0x02000000 ++#define EF_ARM_EABI_VER3 0x03000000 ++#define EF_ARM_EABI_VER4 0x04000000 ++#define EF_ARM_EABI_VER5 0x05000000 ++ ++/* Additional symbol types for Thumb. */ ++#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ ++#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ ++ ++/* ARM-specific values for sh_flags */ ++#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ ++#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined ++ in the input to a link step. */ ++ ++/* ARM-specific program header flags */ ++#define PF_ARM_SB 0x10000000 /* Segment contains the location ++ addressed by the static base. */ ++#define PF_ARM_PI 0x20000000 /* Position-independent segment. */ ++#define PF_ARM_ABS 0x40000000 /* Absolute segment. */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */ ++#define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */ ++#define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */ ++ ++ ++/* ARM relocs. */ ++ ++#define R_ARM_NONE 0 /* No reloc */ ++#define R_ARM_PC24 1 /* PC relative 26 bit branch */ ++#define R_ARM_ABS32 2 /* Direct 32 bit */ ++#define R_ARM_REL32 3 /* PC relative 32 bit */ ++#define R_ARM_PC13 4 ++#define R_ARM_ABS16 5 /* Direct 16 bit */ ++#define R_ARM_ABS12 6 /* Direct 12 bit */ ++#define R_ARM_THM_ABS5 7 ++#define R_ARM_ABS8 8 /* Direct 8 bit */ ++#define R_ARM_SBREL32 9 ++#define R_ARM_THM_PC22 10 ++#define R_ARM_THM_PC8 11 ++#define R_ARM_AMP_VCALL9 12 ++#define R_ARM_SWI24 13 /* Obsolete static relocation. */ ++#define R_ARM_TLS_DESC 13 /* Dynamic relocation. */ ++#define R_ARM_THM_SWI8 14 ++#define R_ARM_XPC25 15 ++#define R_ARM_THM_XPC22 16 ++#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ ++#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ ++#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ ++#define R_ARM_COPY 20 /* Copy symbol at runtime */ ++#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ ++#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ ++#define R_ARM_RELATIVE 23 /* Adjust by program base */ ++#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ ++#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ ++#define R_ARM_GOT32 26 /* 32 bit GOT entry */ ++#define R_ARM_PLT32 27 /* 32 bit PLT address */ ++#define R_ARM_ALU_PCREL_7_0 32 ++#define R_ARM_ALU_PCREL_15_8 33 ++#define R_ARM_ALU_PCREL_23_15 34 ++#define R_ARM_LDR_SBREL_11_0 35 ++#define R_ARM_ALU_SBREL_19_12 36 ++#define R_ARM_ALU_SBREL_27_20 37 ++#define R_ARM_TLS_GOTDESC 90 ++#define R_ARM_TLS_CALL 91 ++#define R_ARM_TLS_DESCSEQ 92 ++#define R_ARM_THM_TLS_CALL 93 ++#define R_ARM_GNU_VTENTRY 100 ++#define R_ARM_GNU_VTINHERIT 101 ++#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ ++#define R_ARM_THM_PC9 103 /* thumb conditional branch */ ++#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic ++ thread local data */ ++#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic ++ thread local data */ ++#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS ++ block */ ++#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of ++ static TLS block offset */ ++#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static ++ TLS block */ ++#define R_ARM_THM_TLS_DESCSEQ 129 ++#define R_ARM_IRELATIVE 160 ++#define R_ARM_RXPC25 249 ++#define R_ARM_RSBREL32 250 ++#define R_ARM_THM_RPC22 251 ++#define R_ARM_RREL32 252 ++#define R_ARM_RABS22 253 ++#define R_ARM_RPC24 254 ++#define R_ARM_RBASE 255 ++/* Keep this the last entry. */ ++#define R_ARM_NUM 256 ++ ++/* IA-64 specific declarations. */ ++ ++/* Processor specific flags for the Ehdr e_flags field. */ ++#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ ++#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ ++#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ ++#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ ++#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) ++#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) ++#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) ++ ++/* Processor specific flags for the Phdr p_flags field. */ ++#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ ++#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ ++ ++/* Processor specific flags for the Shdr sh_flags field. */ ++#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ ++#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Dyn d_tag field. */ ++#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) ++#define DT_IA_64_NUM 1 ++ ++/* IA-64 relocations. */ ++#define R_IA64_NONE 0x00 /* none */ ++#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ ++#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ ++#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ ++#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ ++#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ ++#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ ++#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ ++#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ ++#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ ++#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ ++#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ ++#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ ++#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ ++#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ ++#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ ++#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ ++#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ ++#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ ++#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ ++#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ ++#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ ++#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ ++#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ ++#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ ++#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ ++#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ ++#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ ++#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ ++#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ ++#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ ++#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ ++#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ ++#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ ++#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ ++#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ ++#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ ++#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ ++#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ ++#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ ++#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ ++#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ ++#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ ++#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ ++#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ ++#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ ++#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ ++#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ ++#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ ++#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ ++#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ ++#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ ++#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ ++#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ ++#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ ++#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ ++#define R_IA64_COPY 0x84 /* copy relocation */ ++#define R_IA64_SUB 0x85 /* Addend and symbol difference */ ++#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ ++#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ ++#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ ++#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ ++#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ ++#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ ++#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ ++#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ ++#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ ++#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ ++#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ ++#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ ++#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ ++#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ ++#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ ++#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ ++ ++/* SH specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_SH_MACH_MASK 0x1f ++#define EF_SH_UNKNOWN 0x0 ++#define EF_SH1 0x1 ++#define EF_SH2 0x2 ++#define EF_SH3 0x3 ++#define EF_SH_DSP 0x4 ++#define EF_SH3_DSP 0x5 ++#define EF_SH4AL_DSP 0x6 ++#define EF_SH3E 0x8 ++#define EF_SH4 0x9 ++#define EF_SH2E 0xb ++#define EF_SH4A 0xc ++#define EF_SH2A 0xd ++#define EF_SH4_NOFPU 0x10 ++#define EF_SH4A_NOFPU 0x11 ++#define EF_SH4_NOMMU_NOFPU 0x12 ++#define EF_SH2A_NOFPU 0x13 ++#define EF_SH3_NOMMU 0x14 ++#define EF_SH2A_SH4_NOFPU 0x15 ++#define EF_SH2A_SH3_NOFPU 0x16 ++#define EF_SH2A_SH4 0x17 ++#define EF_SH2A_SH3E 0x18 ++ ++/* SH relocs. */ ++#define R_SH_NONE 0 ++#define R_SH_DIR32 1 ++#define R_SH_REL32 2 ++#define R_SH_DIR8WPN 3 ++#define R_SH_IND12W 4 ++#define R_SH_DIR8WPL 5 ++#define R_SH_DIR8WPZ 6 ++#define R_SH_DIR8BP 7 ++#define R_SH_DIR8W 8 ++#define R_SH_DIR8L 9 ++#define R_SH_SWITCH16 25 ++#define R_SH_SWITCH32 26 ++#define R_SH_USES 27 ++#define R_SH_COUNT 28 ++#define R_SH_ALIGN 29 ++#define R_SH_CODE 30 ++#define R_SH_DATA 31 ++#define R_SH_LABEL 32 ++#define R_SH_SWITCH8 33 ++#define R_SH_GNU_VTINHERIT 34 ++#define R_SH_GNU_VTENTRY 35 ++#define R_SH_TLS_GD_32 144 ++#define R_SH_TLS_LD_32 145 ++#define R_SH_TLS_LDO_32 146 ++#define R_SH_TLS_IE_32 147 ++#define R_SH_TLS_LE_32 148 ++#define R_SH_TLS_DTPMOD32 149 ++#define R_SH_TLS_DTPOFF32 150 ++#define R_SH_TLS_TPOFF32 151 ++#define R_SH_GOT32 160 ++#define R_SH_PLT32 161 ++#define R_SH_COPY 162 ++#define R_SH_GLOB_DAT 163 ++#define R_SH_JMP_SLOT 164 ++#define R_SH_RELATIVE 165 ++#define R_SH_GOTOFF 166 ++#define R_SH_GOTPC 167 ++/* Keep this the last entry. */ ++#define R_SH_NUM 256 ++ ++/* S/390 specific definitions. */ ++ ++/* Valid values for the e_flags field. */ ++ ++#define EF_S390_HIGH_GPRS 0x00000001 /* High GPRs kernel facility needed. */ ++ ++/* Additional s390 relocs */ ++ ++#define R_390_NONE 0 /* No reloc. */ ++#define R_390_8 1 /* Direct 8 bit. */ ++#define R_390_12 2 /* Direct 12 bit. */ ++#define R_390_16 3 /* Direct 16 bit. */ ++#define R_390_32 4 /* Direct 32 bit. */ ++#define R_390_PC32 5 /* PC relative 32 bit. */ ++#define R_390_GOT12 6 /* 12 bit GOT offset. */ ++#define R_390_GOT32 7 /* 32 bit GOT offset. */ ++#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ ++#define R_390_COPY 9 /* Copy symbol at runtime. */ ++#define R_390_GLOB_DAT 10 /* Create GOT entry. */ ++#define R_390_JMP_SLOT 11 /* Create PLT entry. */ ++#define R_390_RELATIVE 12 /* Adjust by program base. */ ++#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ ++#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ ++#define R_390_GOT16 15 /* 16 bit GOT offset. */ ++#define R_390_PC16 16 /* PC relative 16 bit. */ ++#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ ++#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ ++#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ ++#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ ++#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ ++#define R_390_64 22 /* Direct 64 bit. */ ++#define R_390_PC64 23 /* PC relative 64 bit. */ ++#define R_390_GOT64 24 /* 64 bit GOT offset. */ ++#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ ++#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ ++#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ ++#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ ++#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ ++#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ ++#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ ++#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ ++#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ ++#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ ++#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ ++#define R_390_TLS_GDCALL 38 /* Tag for function call in general ++ dynamic TLS code. */ ++#define R_390_TLS_LDCALL 39 /* Tag for function call in local ++ dynamic TLS code. */ ++#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ ++#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ ++#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS ++ block. */ ++#define R_390_20 57 /* Direct 20 bit. */ ++#define R_390_GOT20 58 /* 20 bit GOT offset. */ ++#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ ++#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_IRELATIVE 61 /* STT_GNU_IFUNC relocation. */ ++/* Keep this the last entry. */ ++#define R_390_NUM 62 ++ ++ ++/* CRIS relocations. */ ++#define R_CRIS_NONE 0 ++#define R_CRIS_8 1 ++#define R_CRIS_16 2 ++#define R_CRIS_32 3 ++#define R_CRIS_8_PCREL 4 ++#define R_CRIS_16_PCREL 5 ++#define R_CRIS_32_PCREL 6 ++#define R_CRIS_GNU_VTINHERIT 7 ++#define R_CRIS_GNU_VTENTRY 8 ++#define R_CRIS_COPY 9 ++#define R_CRIS_GLOB_DAT 10 ++#define R_CRIS_JUMP_SLOT 11 ++#define R_CRIS_RELATIVE 12 ++#define R_CRIS_16_GOT 13 ++#define R_CRIS_32_GOT 14 ++#define R_CRIS_16_GOTPLT 15 ++#define R_CRIS_32_GOTPLT 16 ++#define R_CRIS_32_GOTREL 17 ++#define R_CRIS_32_PLT_GOTREL 18 ++#define R_CRIS_32_PLT_PCREL 19 ++ ++#define R_CRIS_NUM 20 ++ ++ ++/* AMD x86-64 relocations. */ ++#define R_X86_64_NONE 0 /* No reloc */ ++#define R_X86_64_64 1 /* Direct 64 bit */ ++#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ ++#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ ++#define R_X86_64_PLT32 4 /* 32 bit PLT address */ ++#define R_X86_64_COPY 5 /* Copy symbol at runtime */ ++#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ ++#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ ++#define R_X86_64_RELATIVE 8 /* Adjust by program base */ ++#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative ++ offset to GOT */ ++#define R_X86_64_32 10 /* Direct 32 bit zero extended */ ++#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ ++#define R_X86_64_16 12 /* Direct 16 bit zero extended */ ++#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ ++#define R_X86_64_8 14 /* Direct 8 bit sign extended */ ++#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ ++#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ ++#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ ++#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ ++#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset ++ to two GOT entries for GD symbol */ ++#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset ++ to two GOT entries for LD symbol */ ++#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ ++#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset ++ to GOT entry for IE symbol */ ++#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ ++#define R_X86_64_PC64 24 /* PC relative 64 bit */ ++#define R_X86_64_GOTOFF64 25 /* 64 bit offset to GOT */ ++#define R_X86_64_GOTPC32 26 /* 32 bit signed pc relative ++ offset to GOT */ ++#define R_X86_64_GOT64 27 /* 64-bit GOT entry offset */ ++#define R_X86_64_GOTPCREL64 28 /* 64-bit PC relative offset ++ to GOT entry */ ++#define R_X86_64_GOTPC64 29 /* 64-bit PC relative offset to GOT */ ++#define R_X86_64_GOTPLT64 30 /* like GOT64, says PLT entry needed */ ++#define R_X86_64_PLTOFF64 31 /* 64-bit GOT relative offset ++ to PLT entry */ ++#define R_X86_64_SIZE32 32 /* Size of symbol plus 32-bit addend */ ++#define R_X86_64_SIZE64 33 /* Size of symbol plus 64-bit addend */ ++#define R_X86_64_GOTPC32_TLSDESC 34 /* GOT offset for TLS descriptor. */ ++#define R_X86_64_TLSDESC_CALL 35 /* Marker for call through TLS ++ descriptor. */ ++#define R_X86_64_TLSDESC 36 /* TLS descriptor. */ ++#define R_X86_64_IRELATIVE 37 /* Adjust indirectly by program base */ ++#define R_X86_64_RELATIVE64 38 /* 64-bit adjust by program base */ ++ ++#define R_X86_64_NUM 39 ++ ++ ++/* AM33 relocations. */ ++#define R_MN10300_NONE 0 /* No reloc. */ ++#define R_MN10300_32 1 /* Direct 32 bit. */ ++#define R_MN10300_16 2 /* Direct 16 bit. */ ++#define R_MN10300_8 3 /* Direct 8 bit. */ ++#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ ++#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ ++#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ ++#define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ ++#define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ ++#define R_MN10300_24 9 /* Direct 24 bit. */ ++#define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ ++#define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ ++#define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ ++#define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ ++#define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ ++#define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ ++#define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ ++#define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ ++#define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ ++#define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ ++#define R_MN10300_COPY 20 /* Copy symbol at runtime. */ ++#define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ ++#define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ ++#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ ++ ++#define R_MN10300_NUM 24 ++ ++ ++/* M32R relocs. */ ++#define R_M32R_NONE 0 /* No reloc. */ ++#define R_M32R_16 1 /* Direct 16 bit. */ ++#define R_M32R_32 2 /* Direct 32 bit. */ ++#define R_M32R_24 3 /* Direct 24 bit. */ ++#define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ ++#define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ ++#define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ ++#define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ ++#define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ ++#define R_M32R_LO16 9 /* Low 16 bit. */ ++#define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ ++#define R_M32R_GNU_VTINHERIT 11 ++#define R_M32R_GNU_VTENTRY 12 ++/* M32R relocs use SHT_RELA. */ ++#define R_M32R_16_RELA 33 /* Direct 16 bit. */ ++#define R_M32R_32_RELA 34 /* Direct 32 bit. */ ++#define R_M32R_24_RELA 35 /* Direct 24 bit. */ ++#define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ ++#define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ ++#define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ ++#define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ ++#define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ ++#define R_M32R_LO16_RELA 41 /* Low 16 bit */ ++#define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ ++#define R_M32R_RELA_GNU_VTINHERIT 43 ++#define R_M32R_RELA_GNU_VTENTRY 44 ++#define R_M32R_REL32 45 /* PC relative 32 bit. */ ++ ++#define R_M32R_GOT24 48 /* 24 bit GOT entry */ ++#define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ ++#define R_M32R_COPY 50 /* Copy symbol at runtime */ ++#define R_M32R_GLOB_DAT 51 /* Create GOT entry */ ++#define R_M32R_JMP_SLOT 52 /* Create PLT entry */ ++#define R_M32R_RELATIVE 53 /* Adjust by program base */ ++#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ ++#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ ++#define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned ++ low */ ++#define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed ++ low */ ++#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ ++#define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to ++ GOT with unsigned low */ ++#define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to ++ GOT with signed low */ ++#define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to ++ GOT */ ++#define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT ++ with unsigned low */ ++#define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT ++ with signed low */ ++#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ ++#define R_M32R_NUM 256 /* Keep this the last entry. */ ++ ++ ++/* TILEPro relocations. */ ++#define R_TILEPRO_NONE 0 /* No reloc */ ++#define R_TILEPRO_32 1 /* Direct 32 bit */ ++#define R_TILEPRO_16 2 /* Direct 16 bit */ ++#define R_TILEPRO_8 3 /* Direct 8 bit */ ++#define R_TILEPRO_32_PCREL 4 /* PC relative 32 bit */ ++#define R_TILEPRO_16_PCREL 5 /* PC relative 16 bit */ ++#define R_TILEPRO_8_PCREL 6 /* PC relative 8 bit */ ++#define R_TILEPRO_LO16 7 /* Low 16 bit */ ++#define R_TILEPRO_HI16 8 /* High 16 bit */ ++#define R_TILEPRO_HA16 9 /* High 16 bit, adjusted */ ++#define R_TILEPRO_COPY 10 /* Copy relocation */ ++#define R_TILEPRO_GLOB_DAT 11 /* Create GOT entry */ ++#define R_TILEPRO_JMP_SLOT 12 /* Create PLT entry */ ++#define R_TILEPRO_RELATIVE 13 /* Adjust by program base */ ++#define R_TILEPRO_BROFF_X1 14 /* X1 pipe branch offset */ ++#define R_TILEPRO_JOFFLONG_X1 15 /* X1 pipe jump offset */ ++#define R_TILEPRO_JOFFLONG_X1_PLT 16 /* X1 pipe jump offset to PLT */ ++#define R_TILEPRO_IMM8_X0 17 /* X0 pipe 8-bit */ ++#define R_TILEPRO_IMM8_Y0 18 /* Y0 pipe 8-bit */ ++#define R_TILEPRO_IMM8_X1 19 /* X1 pipe 8-bit */ ++#define R_TILEPRO_IMM8_Y1 20 /* Y1 pipe 8-bit */ ++#define R_TILEPRO_MT_IMM15_X1 21 /* X1 pipe mtspr */ ++#define R_TILEPRO_MF_IMM15_X1 22 /* X1 pipe mfspr */ ++#define R_TILEPRO_IMM16_X0 23 /* X0 pipe 16-bit */ ++#define R_TILEPRO_IMM16_X1 24 /* X1 pipe 16-bit */ ++#define R_TILEPRO_IMM16_X0_LO 25 /* X0 pipe low 16-bit */ ++#define R_TILEPRO_IMM16_X1_LO 26 /* X1 pipe low 16-bit */ ++#define R_TILEPRO_IMM16_X0_HI 27 /* X0 pipe high 16-bit */ ++#define R_TILEPRO_IMM16_X1_HI 28 /* X1 pipe high 16-bit */ ++#define R_TILEPRO_IMM16_X0_HA 29 /* X0 pipe high 16-bit, adjusted */ ++#define R_TILEPRO_IMM16_X1_HA 30 /* X1 pipe high 16-bit, adjusted */ ++#define R_TILEPRO_IMM16_X0_PCREL 31 /* X0 pipe PC relative 16 bit */ ++#define R_TILEPRO_IMM16_X1_PCREL 32 /* X1 pipe PC relative 16 bit */ ++#define R_TILEPRO_IMM16_X0_LO_PCREL 33 /* X0 pipe PC relative low 16 bit */ ++#define R_TILEPRO_IMM16_X1_LO_PCREL 34 /* X1 pipe PC relative low 16 bit */ ++#define R_TILEPRO_IMM16_X0_HI_PCREL 35 /* X0 pipe PC relative high 16 bit */ ++#define R_TILEPRO_IMM16_X1_HI_PCREL 36 /* X1 pipe PC relative high 16 bit */ ++#define R_TILEPRO_IMM16_X0_HA_PCREL 37 /* X0 pipe PC relative ha() 16 bit */ ++#define R_TILEPRO_IMM16_X1_HA_PCREL 38 /* X1 pipe PC relative ha() 16 bit */ ++#define R_TILEPRO_IMM16_X0_GOT 39 /* X0 pipe 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT 40 /* X1 pipe 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_LO 41 /* X0 pipe low 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_LO 42 /* X1 pipe low 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_HI 43 /* X0 pipe high 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_HI 44 /* X1 pipe high 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_HA 45 /* X0 pipe ha() 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_HA 46 /* X1 pipe ha() 16-bit GOT offset */ ++#define R_TILEPRO_MMSTART_X0 47 /* X0 pipe mm "start" */ ++#define R_TILEPRO_MMEND_X0 48 /* X0 pipe mm "end" */ ++#define R_TILEPRO_MMSTART_X1 49 /* X1 pipe mm "start" */ ++#define R_TILEPRO_MMEND_X1 50 /* X1 pipe mm "end" */ ++#define R_TILEPRO_SHAMT_X0 51 /* X0 pipe shift amount */ ++#define R_TILEPRO_SHAMT_X1 52 /* X1 pipe shift amount */ ++#define R_TILEPRO_SHAMT_Y0 53 /* Y0 pipe shift amount */ ++#define R_TILEPRO_SHAMT_Y1 54 /* Y1 pipe shift amount */ ++#define R_TILEPRO_DEST_IMM8_X1 55 /* X1 pipe destination 8-bit */ ++/* Relocs 56-59 are currently not defined. */ ++#define R_TILEPRO_TLS_GD_CALL 60 /* "jal" for TLS GD */ ++#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 /* X0 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 /* X1 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 /* Y0 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 /* Y1 pipe "addi" for TLS GD */ ++#define R_TILEPRO_TLS_IE_LOAD 65 /* "lw_tls" for TLS IE */ ++#define R_TILEPRO_IMM16_X0_TLS_GD 66 /* X0 pipe 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD 67 /* X1 pipe 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68 /* X0 pipe low 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69 /* X1 pipe low 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70 /* X0 pipe high 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71 /* X1 pipe high 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72 /* X0 pipe ha() 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73 /* X1 pipe ha() 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE 74 /* X0 pipe 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE 75 /* X1 pipe 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76 /* X0 pipe low 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77 /* X1 pipe low 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78 /* X0 pipe high 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79 /* X1 pipe high 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80 /* X0 pipe ha() 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81 /* X1 pipe ha() 16-bit TLS IE offset */ ++#define R_TILEPRO_TLS_DTPMOD32 82 /* ID of module containing symbol */ ++#define R_TILEPRO_TLS_DTPOFF32 83 /* Offset in TLS block */ ++#define R_TILEPRO_TLS_TPOFF32 84 /* Offset in static TLS block */ ++#define R_TILEPRO_IMM16_X0_TLS_LE 85 /* X0 pipe 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE 86 /* X1 pipe 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87 /* X0 pipe low 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88 /* X1 pipe low 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89 /* X0 pipe high 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90 /* X1 pipe high 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91 /* X0 pipe ha() 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92 /* X1 pipe ha() 16-bit TLS LE offset */ ++ ++#define R_TILEPRO_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ ++#define R_TILEPRO_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ ++ ++#define R_TILEPRO_NUM 130 ++ ++ ++/* TILE-Gx relocations. */ ++#define R_TILEGX_NONE 0 /* No reloc */ ++#define R_TILEGX_64 1 /* Direct 64 bit */ ++#define R_TILEGX_32 2 /* Direct 32 bit */ ++#define R_TILEGX_16 3 /* Direct 16 bit */ ++#define R_TILEGX_8 4 /* Direct 8 bit */ ++#define R_TILEGX_64_PCREL 5 /* PC relative 64 bit */ ++#define R_TILEGX_32_PCREL 6 /* PC relative 32 bit */ ++#define R_TILEGX_16_PCREL 7 /* PC relative 16 bit */ ++#define R_TILEGX_8_PCREL 8 /* PC relative 8 bit */ ++#define R_TILEGX_HW0 9 /* hword 0 16-bit */ ++#define R_TILEGX_HW1 10 /* hword 1 16-bit */ ++#define R_TILEGX_HW2 11 /* hword 2 16-bit */ ++#define R_TILEGX_HW3 12 /* hword 3 16-bit */ ++#define R_TILEGX_HW0_LAST 13 /* last hword 0 16-bit */ ++#define R_TILEGX_HW1_LAST 14 /* last hword 1 16-bit */ ++#define R_TILEGX_HW2_LAST 15 /* last hword 2 16-bit */ ++#define R_TILEGX_COPY 16 /* Copy relocation */ ++#define R_TILEGX_GLOB_DAT 17 /* Create GOT entry */ ++#define R_TILEGX_JMP_SLOT 18 /* Create PLT entry */ ++#define R_TILEGX_RELATIVE 19 /* Adjust by program base */ ++#define R_TILEGX_BROFF_X1 20 /* X1 pipe branch offset */ ++#define R_TILEGX_JUMPOFF_X1 21 /* X1 pipe jump offset */ ++#define R_TILEGX_JUMPOFF_X1_PLT 22 /* X1 pipe jump offset to PLT */ ++#define R_TILEGX_IMM8_X0 23 /* X0 pipe 8-bit */ ++#define R_TILEGX_IMM8_Y0 24 /* Y0 pipe 8-bit */ ++#define R_TILEGX_IMM8_X1 25 /* X1 pipe 8-bit */ ++#define R_TILEGX_IMM8_Y1 26 /* Y1 pipe 8-bit */ ++#define R_TILEGX_DEST_IMM8_X1 27 /* X1 pipe destination 8-bit */ ++#define R_TILEGX_MT_IMM14_X1 28 /* X1 pipe mtspr */ ++#define R_TILEGX_MF_IMM14_X1 29 /* X1 pipe mfspr */ ++#define R_TILEGX_MMSTART_X0 30 /* X0 pipe mm "start" */ ++#define R_TILEGX_MMEND_X0 31 /* X0 pipe mm "end" */ ++#define R_TILEGX_SHAMT_X0 32 /* X0 pipe shift amount */ ++#define R_TILEGX_SHAMT_X1 33 /* X1 pipe shift amount */ ++#define R_TILEGX_SHAMT_Y0 34 /* Y0 pipe shift amount */ ++#define R_TILEGX_SHAMT_Y1 35 /* Y1 pipe shift amount */ ++#define R_TILEGX_IMM16_X0_HW0 36 /* X0 pipe hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0 37 /* X1 pipe hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1 38 /* X0 pipe hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1 39 /* X1 pipe hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2 40 /* X0 pipe hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2 41 /* X1 pipe hword 2 */ ++#define R_TILEGX_IMM16_X0_HW3 42 /* X0 pipe hword 3 */ ++#define R_TILEGX_IMM16_X1_HW3 43 /* X1 pipe hword 3 */ ++#define R_TILEGX_IMM16_X0_HW0_LAST 44 /* X0 pipe last hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_LAST 45 /* X1 pipe last hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_LAST 46 /* X0 pipe last hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_LAST 47 /* X1 pipe last hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_LAST 48 /* X0 pipe last hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_LAST 49 /* X1 pipe last hword 2 */ ++#define R_TILEGX_IMM16_X0_HW0_PCREL 50 /* X0 pipe PC relative hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_PCREL 51 /* X1 pipe PC relative hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_PCREL 52 /* X0 pipe PC relative hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_PCREL 53 /* X1 pipe PC relative hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_PCREL 54 /* X0 pipe PC relative hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_PCREL 55 /* X1 pipe PC relative hword 2 */ ++#define R_TILEGX_IMM16_X0_HW3_PCREL 56 /* X0 pipe PC relative hword 3 */ ++#define R_TILEGX_IMM16_X1_HW3_PCREL 57 /* X1 pipe PC relative hword 3 */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */ ++#define R_TILEGX_IMM16_X0_HW0_GOT 64 /* X0 pipe hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW0_GOT 65 /* X1 pipe hword 0 GOT offset */ ++/* Relocs 66-71 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */ ++/* Relocs 76-77 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78 /* X0 pipe hword 0 TLS GD offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79 /* X1 pipe hword 0 TLS GD offset */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80 /* X0 pipe hword 0 TLS LE offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81 /* X1 pipe hword 0 TLS LE offset */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */ ++/* Relocs 90-91 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92 /* X0 pipe hword 0 TLS IE offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93 /* X1 pipe hword 0 TLS IE offset */ ++/* Relocs 94-99 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */ ++/* Relocs 104-105 are currently not defined. */ ++#define R_TILEGX_TLS_DTPMOD64 106 /* 64-bit ID of symbol's module */ ++#define R_TILEGX_TLS_DTPOFF64 107 /* 64-bit offset in TLS block */ ++#define R_TILEGX_TLS_TPOFF64 108 /* 64-bit offset in static TLS block */ ++#define R_TILEGX_TLS_DTPMOD32 109 /* 32-bit ID of symbol's module */ ++#define R_TILEGX_TLS_DTPOFF32 110 /* 32-bit offset in TLS block */ ++#define R_TILEGX_TLS_TPOFF32 111 /* 32-bit offset in static TLS block */ ++#define R_TILEGX_TLS_GD_CALL 112 /* "jal" for TLS GD */ ++#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113 /* X0 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114 /* X1 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 /* Y0 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 /* Y1 pipe "addi" for TLS GD */ ++#define R_TILEGX_TLS_IE_LOAD 117 /* "ld_tls" for TLS IE */ ++#define R_TILEGX_IMM8_X0_TLS_ADD 118 /* X0 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_X1_TLS_ADD 119 /* X1 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_Y0_TLS_ADD 120 /* Y0 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_Y1_TLS_ADD 121 /* Y1 pipe "addi" for TLS GD/IE */ ++ ++#define R_TILEGX_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ ++#define R_TILEGX_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ ++ ++#define R_TILEGX_NUM 130 ++ ++#endif /* elf.h */ diff --git a/target/linux/generic/patches-4.0/212-byteshift_portability.patch b/target/linux/generic/patches-4.0/212-byteshift_portability.patch new file mode 100644 index 0000000..0f23ba9 --- /dev/null +++ b/target/linux/generic/patches-4.0/212-byteshift_portability.patch @@ -0,0 +1,51 @@ +--- a/tools/include/tools/be_byteshift.h ++++ b/tools/include/tools/be_byteshift.h +@@ -1,6 +1,10 @@ + #ifndef _TOOLS_BE_BYTESHIFT_H + #define _TOOLS_BE_BYTESHIFT_H + ++#ifndef __linux__ ++#include "linux_types.h" ++#endif ++ + #include + + static inline uint16_t __get_unaligned_be16(const uint8_t *p) +--- a/tools/include/tools/le_byteshift.h ++++ b/tools/include/tools/le_byteshift.h +@@ -1,6 +1,10 @@ + #ifndef _TOOLS_LE_BYTESHIFT_H + #define _TOOLS_LE_BYTESHIFT_H + ++#ifndef __linux__ ++#include "linux_types.h" ++#endif ++ + #include + + static inline uint16_t __get_unaligned_le16(const uint8_t *p) +--- /dev/null ++++ b/tools/include/tools/linux_types.h +@@ -0,0 +1,22 @@ ++#ifndef __LINUX_TYPES_H ++#define __LINUX_TYPES_H ++ ++#include ++ ++typedef uint8_t __u8; ++typedef uint8_t __be8; ++typedef uint8_t __le8; ++ ++typedef uint16_t __u16; ++typedef uint16_t __be16; ++typedef uint16_t __le16; ++ ++typedef uint32_t __u32; ++typedef uint32_t __be32; ++typedef uint32_t __le32; ++ ++typedef uint64_t __u64; ++typedef uint64_t __be64; ++typedef uint64_t __le64; ++ ++#endif diff --git a/target/linux/generic/patches-4.0/214-spidev_h_portability.patch b/target/linux/generic/patches-4.0/214-spidev_h_portability.patch new file mode 100644 index 0000000..dbee090 --- /dev/null +++ b/target/linux/generic/patches-4.0/214-spidev_h_portability.patch @@ -0,0 +1,11 @@ +--- a/include/uapi/linux/spi/spidev.h ++++ b/include/uapi/linux/spi/spidev.h +@@ -111,7 +111,7 @@ struct spi_ioc_transfer { + + /* not all platforms use or _IOC_TYPECHECK() ... */ + #define SPI_MSGSIZE(N) \ +- ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ ++ ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << 13)) \ + ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) + #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + diff --git a/target/linux/generic/patches-4.0/220-gc_sections.patch b/target/linux/generic/patches-4.0/220-gc_sections.patch new file mode 100644 index 0000000..102c18f --- /dev/null +++ b/target/linux/generic/patches-4.0/220-gc_sections.patch @@ -0,0 +1,532 @@ +From: Felix Fietkau + +use -ffunction-sections, -fdata-sections and --gc-sections + +In combination with kernel symbol export stripping this significantly reduces +the kernel image size. Used on both ARM and MIPS architectures. + +Signed-off-by: Felix Fietkau +Signed-off-by: Jonas Gorski +Signed-off-by: Gabor Juhos +--- + +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -89,10 +89,14 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + # + cflags-y += -G 0 -mno-abicalls -fno-pic -pipe + cflags-y += -msoft-float +-LDFLAGS_vmlinux += -G 0 -static -n -nostdlib ++LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections + KBUILD_AFLAGS_MODULE += -mlong-calls + KBUILD_CFLAGS_MODULE += -mlong-calls + ++ifndef CONFIG_FUNCTION_TRACER ++KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections ++endif ++ + # + # pass -msoft-float to GAS if it supports it. However on newer binutils + # (specifically newer than 2.24.51.20140728) we then also need to explicitly +--- a/arch/mips/kernel/vmlinux.lds.S ++++ b/arch/mips/kernel/vmlinux.lds.S +@@ -67,7 +67,7 @@ SECTIONS + /* Exception table for data bus errors */ + __dbe_table : { + __start___dbe_table = .; +- *(__dbe_table) ++ KEEP(*(__dbe_table)) + __stop___dbe_table = .; + } + +@@ -112,7 +112,7 @@ SECTIONS + . = ALIGN(4); + .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) { + __mips_machines_start = .; +- *(.mips.machines.init) ++ KEEP(*(.mips.machines.init)) + __mips_machines_end = .; + } + +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -89,7 +89,7 @@ + #ifdef CONFIG_FTRACE_MCOUNT_RECORD + #define MCOUNT_REC() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_mcount_loc) = .; \ +- *(__mcount_loc) \ ++ KEEP(*(__mcount_loc)) \ + VMLINUX_SYMBOL(__stop_mcount_loc) = .; + #else + #define MCOUNT_REC() +@@ -97,7 +97,7 @@ + + #ifdef CONFIG_TRACE_BRANCH_PROFILING + #define LIKELY_PROFILE() VMLINUX_SYMBOL(__start_annotated_branch_profile) = .; \ +- *(_ftrace_annotated_branch) \ ++ KEEP(*(_ftrace_annotated_branch)) \ + VMLINUX_SYMBOL(__stop_annotated_branch_profile) = .; + #else + #define LIKELY_PROFILE() +@@ -105,7 +105,7 @@ + + #ifdef CONFIG_PROFILE_ALL_BRANCHES + #define BRANCH_PROFILE() VMLINUX_SYMBOL(__start_branch_profile) = .; \ +- *(_ftrace_branch) \ ++ KEEP(*(_ftrace_branch)) \ + VMLINUX_SYMBOL(__stop_branch_profile) = .; + #else + #define BRANCH_PROFILE() +@@ -114,7 +114,7 @@ + #ifdef CONFIG_KPROBES + #define KPROBE_BLACKLIST() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_kprobe_blacklist) = .; \ +- *(_kprobe_blacklist) \ ++ KEEP(*(_kprobe_blacklist)) \ + VMLINUX_SYMBOL(__stop_kprobe_blacklist) = .; + #else + #define KPROBE_BLACKLIST() +@@ -123,7 +123,7 @@ + #ifdef CONFIG_EVENT_TRACING + #define FTRACE_EVENTS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_ftrace_events) = .; \ +- *(_ftrace_events) \ ++ KEEP(*(_ftrace_events)) \ + VMLINUX_SYMBOL(__stop_ftrace_events) = .; + #else + #define FTRACE_EVENTS() +@@ -131,7 +131,7 @@ + + #ifdef CONFIG_TRACING + #define TRACE_PRINTKS() VMLINUX_SYMBOL(__start___trace_bprintk_fmt) = .; \ +- *(__trace_printk_fmt) /* Trace_printk fmt' pointer */ \ ++ KEEP(*(__trace_printk_fmt)) /* Trace_printk fmt' pointer */ \ + VMLINUX_SYMBOL(__stop___trace_bprintk_fmt) = .; + #define TRACEPOINT_STR() VMLINUX_SYMBOL(__start___tracepoint_str) = .; \ + *(__tracepoint_str) /* Trace_printk fmt' pointer */ \ +@@ -144,7 +144,7 @@ + #ifdef CONFIG_FTRACE_SYSCALLS + #define TRACE_SYSCALLS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_syscalls_metadata) = .; \ +- *(__syscalls_metadata) \ ++ KEEP(*(__syscalls_metadata)) \ + VMLINUX_SYMBOL(__stop_syscalls_metadata) = .; + #else + #define TRACE_SYSCALLS() +@@ -158,8 +158,8 @@ + #define _OF_TABLE_1(name) \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__##name##_of_table) = .; \ +- *(__##name##_of_table) \ +- *(__##name##_of_table_end) ++ KEEP(*(__##name##_of_table)) \ ++ KEEP(*(__##name##_of_table_end)) + + #define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc) + #define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip) +@@ -172,7 +172,7 @@ + #define KERNEL_DTB() \ + STRUCT_ALIGN(); \ + VMLINUX_SYMBOL(__dtb_start) = .; \ +- *(.dtb.init.rodata) \ ++ KEEP(*(.dtb.init.rodata)) \ + VMLINUX_SYMBOL(__dtb_end) = .; + + /* .data section */ +@@ -188,16 +188,17 @@ + /* implement dynamic printk debug */ \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__start___jump_table) = .; \ +- *(__jump_table) \ ++ KEEP(*(__jump_table)) \ + VMLINUX_SYMBOL(__stop___jump_table) = .; \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__start___verbose) = .; \ +- *(__verbose) \ ++ KEEP(*(__verbose)) \ + VMLINUX_SYMBOL(__stop___verbose) = .; \ + LIKELY_PROFILE() \ + BRANCH_PROFILE() \ + TRACE_PRINTKS() \ +- TRACEPOINT_STR() ++ TRACEPOINT_STR() \ ++ *(.data.[a-zA-Z_]*) + + /* + * Data section helpers +@@ -251,35 +252,35 @@ + /* PCI quirks */ \ + .pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \ +- *(.pci_fixup_early) \ ++ KEEP(*(.pci_fixup_early)) \ + VMLINUX_SYMBOL(__end_pci_fixups_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_header) = .; \ +- *(.pci_fixup_header) \ ++ KEEP(*(.pci_fixup_header)) \ + VMLINUX_SYMBOL(__end_pci_fixups_header) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_final) = .; \ +- *(.pci_fixup_final) \ ++ KEEP(*(.pci_fixup_final)) \ + VMLINUX_SYMBOL(__end_pci_fixups_final) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_enable) = .; \ +- *(.pci_fixup_enable) \ ++ KEEP(*(.pci_fixup_enable)) \ + VMLINUX_SYMBOL(__end_pci_fixups_enable) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume) = .; \ +- *(.pci_fixup_resume) \ ++ KEEP(*(.pci_fixup_resume)) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .; \ +- *(.pci_fixup_resume_early) \ ++ KEEP(*(.pci_fixup_resume_early)) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \ +- *(.pci_fixup_suspend) \ ++ KEEP(*(.pci_fixup_suspend)) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend_late) = .; \ +- *(.pci_fixup_suspend_late) \ ++ KEEP(*(.pci_fixup_suspend_late)) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \ + } \ + \ + /* Built-in firmware blobs */ \ + .builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_builtin_fw) = .; \ +- *(.builtin_fw) \ ++ KEEP(*(.builtin_fw)) \ + VMLINUX_SYMBOL(__end_builtin_fw) = .; \ + } \ + \ +@@ -288,49 +289,49 @@ + /* Kernel symbol table: Normal symbols */ \ + __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab) = .; \ +- *(SORT(___ksymtab+*)) \ ++ KEEP(*(SORT(___ksymtab+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \ +- *(SORT(___ksymtab_gpl+*)) \ ++ KEEP(*(SORT(___ksymtab_gpl+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \ + } \ + \ + /* Kernel symbol table: Normal unused symbols */ \ + __ksymtab_unused : AT(ADDR(__ksymtab_unused) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_unused) = .; \ +- *(SORT(___ksymtab_unused+*)) \ ++ KEEP(*(SORT(___ksymtab_unused+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_unused) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only unused symbols */ \ + __ksymtab_unused_gpl : AT(ADDR(__ksymtab_unused_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_unused_gpl) = .; \ +- *(SORT(___ksymtab_unused_gpl+*)) \ ++ KEEP(*(SORT(___ksymtab_unused_gpl+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_unused_gpl) = .; \ + } \ + \ + /* Kernel symbol table: GPL-future-only symbols */ \ + __ksymtab_gpl_future : AT(ADDR(__ksymtab_gpl_future) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl_future) = .; \ +- *(SORT(___ksymtab_gpl_future+*)) \ ++ KEEP(*(SORT(___ksymtab_gpl_future+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl_future) = .; \ + } \ + \ + /* Kernel symbol table: Normal symbols */ \ + __kcrctab : AT(ADDR(__kcrctab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab) = .; \ +- *(SORT(___kcrctab+*)) \ ++ KEEP(*(SORT(___kcrctab+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_gpl) = .; \ +- *(SORT(___kcrctab_gpl+*)) \ ++ KEEP(*(SORT(___kcrctab_gpl+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_gpl) = .; \ + } \ + \ +@@ -344,14 +345,14 @@ + /* Kernel symbol table: GPL-only unused symbols */ \ + __kcrctab_unused_gpl : AT(ADDR(__kcrctab_unused_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_unused_gpl) = .; \ +- *(SORT(___kcrctab_unused_gpl+*)) \ ++ KEEP(*(SORT(___kcrctab_unused_gpl+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_unused_gpl) = .; \ + } \ + \ + /* Kernel symbol table: GPL-future-only symbols */ \ + __kcrctab_gpl_future : AT(ADDR(__kcrctab_gpl_future) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_gpl_future) = .; \ +- *(SORT(___kcrctab_gpl_future+*)) \ ++ KEEP(*(SORT(___kcrctab_gpl_future+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_gpl_future) = .; \ + } \ + \ +@@ -370,14 +371,14 @@ + /* Built-in module parameters. */ \ + __param : AT(ADDR(__param) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___param) = .; \ +- *(__param) \ ++ KEEP(*(__param)) \ + VMLINUX_SYMBOL(__stop___param) = .; \ + } \ + \ + /* Built-in module versions. */ \ + __modver : AT(ADDR(__modver) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___modver) = .; \ +- *(__modver) \ ++ KEEP(*(__modver)) \ + VMLINUX_SYMBOL(__stop___modver) = .; \ + . = ALIGN((align)); \ + VMLINUX_SYMBOL(__end_rodata) = .; \ +@@ -433,7 +434,7 @@ + #define ENTRY_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__entry_text_start) = .; \ +- *(.entry.text) \ ++ KEEP(*(.entry.text)) \ + VMLINUX_SYMBOL(__entry_text_end) = .; + + #ifdef CONFIG_FUNCTION_GRAPH_TRACER +@@ -461,7 +462,7 @@ + . = ALIGN(align); \ + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ex_table) = .; \ +- *(__ex_table) \ ++ KEEP(*(__ex_table)) \ + VMLINUX_SYMBOL(__stop___ex_table) = .; \ + } + +@@ -477,9 +478,9 @@ + #ifdef CONFIG_CONSTRUCTORS + #define KERNEL_CTORS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__ctors_start) = .; \ +- *(.ctors) \ ++ KEEP(*(.ctors)) \ + *(SORT(.init_array.*)) \ +- *(.init_array) \ ++ KEEP(*(.init_array)) \ + VMLINUX_SYMBOL(__ctors_end) = .; + #else + #define KERNEL_CTORS() +@@ -528,7 +529,7 @@ + #define SBSS(sbss_align) \ + . = ALIGN(sbss_align); \ + .sbss : AT(ADDR(.sbss) - LOAD_OFFSET) { \ +- *(.sbss) \ ++ *(.sbss .sbss.*) \ + *(.scommon) \ + } + +@@ -546,7 +547,7 @@ + BSS_FIRST_SECTIONS \ + *(.bss..page_aligned) \ + *(.dynbss) \ +- *(.bss) \ ++ *(.bss .bss.*) \ + *(COMMON) \ + } + +@@ -595,7 +596,7 @@ + . = ALIGN(8); \ + __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___bug_table) = .; \ +- *(__bug_table) \ ++ KEEP(*(__bug_table)) \ + VMLINUX_SYMBOL(__stop___bug_table) = .; \ + } + #else +@@ -607,7 +608,7 @@ + . = ALIGN(4); \ + .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__tracedata_start) = .; \ +- *(.tracedata) \ ++ KEEP(*(.tracedata)) \ + VMLINUX_SYMBOL(__tracedata_end) = .; \ + } + #else +@@ -624,17 +625,17 @@ + #define INIT_SETUP(initsetup_align) \ + . = ALIGN(initsetup_align); \ + VMLINUX_SYMBOL(__setup_start) = .; \ +- *(.init.setup) \ ++ KEEP(*(.init.setup)) \ + VMLINUX_SYMBOL(__setup_end) = .; + + #define INIT_CALLS_LEVEL(level) \ + VMLINUX_SYMBOL(__initcall##level##_start) = .; \ +- *(.initcall##level##.init) \ +- *(.initcall##level##s.init) \ ++ KEEP(*(.initcall##level##.init)) \ ++ KEEP(*(.initcall##level##s.init)) \ + + #define INIT_CALLS \ + VMLINUX_SYMBOL(__initcall_start) = .; \ +- *(.initcallearly.init) \ ++ KEEP(*(.initcallearly.init)) \ + INIT_CALLS_LEVEL(0) \ + INIT_CALLS_LEVEL(1) \ + INIT_CALLS_LEVEL(2) \ +@@ -648,21 +649,21 @@ + + #define CON_INITCALL \ + VMLINUX_SYMBOL(__con_initcall_start) = .; \ +- *(.con_initcall.init) \ ++ KEEP(*(.con_initcall.init)) \ + VMLINUX_SYMBOL(__con_initcall_end) = .; + + #define SECURITY_INITCALL \ + VMLINUX_SYMBOL(__security_initcall_start) = .; \ +- *(.security_initcall.init) \ ++ KEEP(*(.security_initcall.init)) \ + VMLINUX_SYMBOL(__security_initcall_end) = .; + + #ifdef CONFIG_BLK_DEV_INITRD + #define INIT_RAM_FS \ + . = ALIGN(4); \ + VMLINUX_SYMBOL(__initramfs_start) = .; \ +- *(.init.ramfs) \ ++ KEEP(*(.init.ramfs)) \ + . = ALIGN(8); \ +- *(.init.ramfs.info) ++ KEEP(*(.init.ramfs.info)) + #else + #define INIT_RAM_FS + #endif +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -18,11 +18,16 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) + LDFLAGS_vmlinux += --be8 + LDFLAGS_MODULE += --be8 + endif ++LDFLAGS_vmlinux += --gc-sections + + OBJCOPYFLAGS :=-O binary -R .comment -S + GZFLAGS :=-9 + #KBUILD_CFLAGS +=-pipe + ++ifndef CONFIG_FUNCTION_TRACER ++KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections ++endif ++ + # Never generate .eh_frame + KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) + +--- a/arch/arm/kernel/vmlinux.lds.S ++++ b/arch/arm/kernel/vmlinux.lds.S +@@ -15,13 +15,13 @@ + #define PROC_INFO \ + . = ALIGN(4); \ + VMLINUX_SYMBOL(__proc_info_begin) = .; \ +- *(.proc.info.init) \ ++ KEEP(*(.proc.info.init)) \ + VMLINUX_SYMBOL(__proc_info_end) = .; + + #define IDMAP_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__idmap_text_start) = .; \ +- *(.idmap.text) \ ++ KEEP(*(.idmap.text)) \ + VMLINUX_SYMBOL(__idmap_text_end) = .; \ + . = ALIGN(32); \ + VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \ +@@ -101,7 +101,7 @@ SECTIONS + .text : { /* Real text segment */ + _stext = .; /* Text and read-only data */ + __exception_text_start = .; +- *(.exception.text) ++ KEEP(*(.exception.text)) + __exception_text_end = .; + IRQENTRY_TEXT + TEXT_TEXT +@@ -129,7 +129,7 @@ SECTIONS + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { + __start___ex_table = .; + #ifdef CONFIG_MMU +- *(__ex_table) ++ KEEP(*(__ex_table)) + #endif + __stop___ex_table = .; + } +@@ -141,12 +141,12 @@ SECTIONS + . = ALIGN(8); + .ARM.unwind_idx : { + __start_unwind_idx = .; +- *(.ARM.exidx*) ++ KEEP(*(.ARM.exidx*)) + __stop_unwind_idx = .; + } + .ARM.unwind_tab : { + __start_unwind_tab = .; +- *(.ARM.extab*) ++ KEEP(*(.ARM.extab*)) + __stop_unwind_tab = .; + } + #endif +@@ -169,14 +169,14 @@ SECTIONS + */ + __vectors_start = .; + .vectors 0 : AT(__vectors_start) { +- *(.vectors) ++ KEEP(*(.vectors)) + } + . = __vectors_start + SIZEOF(.vectors); + __vectors_end = .; + + __stubs_start = .; + .stubs 0x1000 : AT(__stubs_start) { +- *(.stubs) ++ KEEP(*(.stubs)) + } + . = __stubs_start + SIZEOF(.stubs); + __stubs_end = .; +@@ -190,24 +190,24 @@ SECTIONS + } + .init.arch.info : { + __arch_info_begin = .; +- *(.arch.info.init) ++ KEEP(*(.arch.info.init)) + __arch_info_end = .; + } + .init.tagtable : { + __tagtable_begin = .; +- *(.taglist.init) ++ KEEP(*(.taglist.init)) + __tagtable_end = .; + } + #ifdef CONFIG_SMP_ON_UP + .init.smpalt : { + __smpalt_begin = .; +- *(.alt.smp.init) ++ KEEP(*(.alt.smp.init)) + __smpalt_end = .; + } + #endif + .init.pv_table : { + __pv_table_begin = .; +- *(.pv_table) ++ KEEP(*(.pv_table)) + __pv_table_end = .; + } + .init.data : { +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -122,6 +122,7 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) + ORIG_CFLAGS := $(KBUILD_CFLAGS) + KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) + endif ++KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL)) + + ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) + asflags-y := -DZIMAGE diff --git a/target/linux/generic/patches-4.0/221-module_exports.patch b/target/linux/generic/patches-4.0/221-module_exports.patch new file mode 100644 index 0000000..daf50fb --- /dev/null +++ b/target/linux/generic/patches-4.0/221-module_exports.patch @@ -0,0 +1,88 @@ +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -54,6 +54,16 @@ + #define LOAD_OFFSET 0 + #endif + ++#ifndef SYMTAB_KEEP ++#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*))) ++#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*))) ++#endif ++ ++#ifndef SYMTAB_DISCARD ++#define SYMTAB_DISCARD ++#define SYMTAB_DISCARD_GPL ++#endif ++ + #include + + /* Align . to a 8 byte boundary equals to maximum function alignment. */ +@@ -289,14 +299,14 @@ + /* Kernel symbol table: Normal symbols */ \ + __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab) = .; \ +- KEEP(*(SORT(___ksymtab+*))) \ ++ SYMTAB_KEEP \ + VMLINUX_SYMBOL(__stop___ksymtab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \ +- KEEP(*(SORT(___ksymtab_gpl+*))) \ ++ SYMTAB_KEEP_GPL \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \ + } \ + \ +@@ -358,7 +368,7 @@ + \ + /* Kernel symbol table: strings */ \ + __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \ +- *(__ksymtab_strings) \ ++ *(__ksymtab_strings+*) \ + } \ + \ + /* __*init sections */ \ +@@ -682,6 +692,8 @@ + EXIT_TEXT \ + EXIT_DATA \ + EXIT_CALL \ ++ SYMTAB_DISCARD \ ++ SYMTAB_DISCARD_GPL \ + *(.discard) \ + *(.discard.*) \ + } +--- a/scripts/Makefile.build ++++ b/scripts/Makefile.build +@@ -299,7 +299,7 @@ targets += $(extra-y) $(MAKECMDGOALS) $( + # Linker scripts preprocessor (.lds.S -> .lds) + # --------------------------------------------------------------------------- + quiet_cmd_cpp_lds_S = LDS $@ +- cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \ ++ cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -C -U$(ARCH) \ + -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< + + $(obj)/%.lds: $(src)/%.lds.S FORCE +--- a/include/linux/export.h ++++ b/include/linux/export.h +@@ -52,12 +52,19 @@ extern struct module __this_module; + #define __CRC_SYMBOL(sym, sec) + #endif + ++#ifdef MODULE ++#define __EXPORT_SUFFIX(sym) ++#else ++#define __EXPORT_SUFFIX(sym) "+" #sym ++#endif ++ + /* For every exported symbol, place a struct in the __ksymtab section */ + #define __EXPORT_SYMBOL(sym, sec) \ + extern typeof(sym) sym; \ + __CRC_SYMBOL(sym, sec) \ + static const char __kstrtab_##sym[] \ +- __attribute__((section("__ksymtab_strings"), aligned(1))) \ ++ __attribute__((section("__ksymtab_strings" \ ++ __EXPORT_SUFFIX(sym)), aligned(1))) \ + = VMLINUX_SYMBOL_STR(sym); \ + extern const struct kernel_symbol __ksymtab_##sym; \ + __visible const struct kernel_symbol __ksymtab_##sym \ diff --git a/target/linux/generic/patches-4.0/230-openwrt_lzma_options.patch b/target/linux/generic/patches-4.0/230-openwrt_lzma_options.patch new file mode 100644 index 0000000..993fce4 --- /dev/null +++ b/target/linux/generic/patches-4.0/230-openwrt_lzma_options.patch @@ -0,0 +1,58 @@ +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -323,7 +323,7 @@ cmd_bzip2 = (cat $(filter-out FORCE,$^) + + quiet_cmd_lzma = LZMA $@ + cmd_lzma = (cat $(filter-out FORCE,$^) | \ +- lzma -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ ++ lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + + quiet_cmd_lzo = LZO $@ +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -226,7 +226,7 @@ cpio_list= + output="/dev/stdout" + output_file="" + is_cpio_compressed= +-compr="gzip -n -9 -f" ++compr="gzip -n -9 -f -" + + arg="$1" + case "$arg" in +@@ -242,13 +242,13 @@ case "$arg" in + output=${cpio_list} + echo "$output_file" | grep -q "\.gz$" \ + && [ -x "`which gzip 2> /dev/null`" ] \ +- && compr="gzip -n -9 -f" ++ && compr="gzip -n -9 -f -" + echo "$output_file" | grep -q "\.bz2$" \ + && [ -x "`which bzip2 2> /dev/null`" ] \ +- && compr="bzip2 -9 -f" ++ && compr="bzip2 -9 -f -" + echo "$output_file" | grep -q "\.lzma$" \ + && [ -x "`which lzma 2> /dev/null`" ] \ +- && compr="lzma -9 -f" ++ && compr="lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so" + echo "$output_file" | grep -q "\.xz$" \ + && [ -x "`which xz 2> /dev/null`" ] \ + && compr="xz --check=crc32 --lzma2=dict=1MiB" +@@ -315,7 +315,7 @@ if [ ! -z ${output_file} ]; then + if [ "${is_cpio_compressed}" = "compressed" ]; then + cat ${cpio_tfile} > ${output_file} + else +- (cat ${cpio_tfile} | ${compr} - > ${output_file}) \ ++ (cat ${cpio_tfile} | ${compr} > ${output_file}) \ + || (rm -f ${output_file} ; false) + fi + [ -z ${cpio_file} ] && rm ${cpio_tfile} +--- a/lib/decompress.c ++++ b/lib/decompress.c +@@ -48,6 +48,7 @@ static const struct compress_format comp + { {0x1f, 0x9e}, "gzip", gunzip }, + { {0x42, 0x5a}, "bzip2", bunzip2 }, + { {0x5d, 0x00}, "lzma", unlzma }, ++ { {0x6d, 0x00}, "lzma-openwrt", unlzma }, + { {0xfd, 0x37}, "xz", unxz }, + { {0x89, 0x4c}, "lzo", unlzo }, + { {0x02, 0x21}, "lz4", unlz4 }, diff --git a/target/linux/generic/patches-4.0/250-netfilter_depends.patch b/target/linux/generic/patches-4.0/250-netfilter_depends.patch new file mode 100644 index 0000000..d4b6d73 --- /dev/null +++ b/target/linux/generic/patches-4.0/250-netfilter_depends.patch @@ -0,0 +1,18 @@ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -210,7 +210,6 @@ config NF_CONNTRACK_FTP + + config NF_CONNTRACK_H323 + tristate "H.323 protocol support" +- depends on (IPV6 || IPV6=n) + depends on NETFILTER_ADVANCED + help + H.323 is a VoIP signalling protocol from ITU-T. As one of the most +@@ -924,7 +923,6 @@ config NETFILTER_XT_TARGET_SECMARK + + config NETFILTER_XT_TARGET_TCPMSS + tristate '"TCPMSS" target support' +- depends on (IPV6 || IPV6=n) + default m if NETFILTER_ADVANCED=n + ---help--- + This option adds a `TCPMSS' target, which allows you to alter the diff --git a/target/linux/generic/patches-4.0/251-sound_kconfig.patch b/target/linux/generic/patches-4.0/251-sound_kconfig.patch new file mode 100644 index 0000000..c2ebace --- /dev/null +++ b/target/linux/generic/patches-4.0/251-sound_kconfig.patch @@ -0,0 +1,18 @@ +--- a/sound/core/Kconfig ++++ b/sound/core/Kconfig +@@ -10,13 +10,13 @@ config SND_DMAENGINE_PCM + tristate + + config SND_HWDEP +- tristate ++ tristate "Sound hardware support" + + config SND_RAWMIDI + tristate + + config SND_COMPRESS_OFFLOAD +- tristate ++ tristate "Compression offloading support" + + # To be effective this also requires INPUT - users should say: + # select SND_JACK if INPUT=y || INPUT=SND diff --git a/target/linux/generic/patches-4.0/252-mv_cesa_depends.patch b/target/linux/generic/patches-4.0/252-mv_cesa_depends.patch new file mode 100644 index 0000000..fee28db --- /dev/null +++ b/target/linux/generic/patches-4.0/252-mv_cesa_depends.patch @@ -0,0 +1,10 @@ +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -164,6 +164,7 @@ config CRYPTO_DEV_MV_CESA + depends on PLAT_ORION + select CRYPTO_ALGAPI + select CRYPTO_AES ++ select CRYPTO_HASH2 + select CRYPTO_BLKCIPHER2 + select CRYPTO_HASH + help diff --git a/target/linux/generic/patches-4.0/253-ssb_b43_default_on.patch b/target/linux/generic/patches-4.0/253-ssb_b43_default_on.patch new file mode 100644 index 0000000..29d2a41 --- /dev/null +++ b/target/linux/generic/patches-4.0/253-ssb_b43_default_on.patch @@ -0,0 +1,29 @@ +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -29,6 +29,7 @@ config SSB_SPROM + config SSB_BLOCKIO + bool + depends on SSB ++ default y + + config SSB_PCIHOST_POSSIBLE + bool +@@ -49,7 +50,7 @@ config SSB_PCIHOST + config SSB_B43_PCI_BRIDGE + bool + depends on SSB_PCIHOST +- default n ++ default y + + config SSB_PCMCIAHOST_POSSIBLE + bool +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -17,6 +17,7 @@ config BCMA + config BCMA_BLOCKIO + bool + depends on BCMA ++ default y + + config BCMA_HOST_PCI_POSSIBLE + bool diff --git a/target/linux/generic/patches-4.0/254-textsearch_kconfig_hacks.patch b/target/linux/generic/patches-4.0/254-textsearch_kconfig_hacks.patch new file mode 100644 index 0000000..cf75400 --- /dev/null +++ b/target/linux/generic/patches-4.0/254-textsearch_kconfig_hacks.patch @@ -0,0 +1,23 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -329,16 +329,16 @@ config BCH_CONST_T + # Textsearch support is select'ed if needed + # + config TEXTSEARCH +- bool ++ boolean "Textsearch support" + + config TEXTSEARCH_KMP +- tristate ++ tristate "Textsearch KMP" + + config TEXTSEARCH_BM +- tristate ++ tristate "Textsearch BM" + + config TEXTSEARCH_FSM +- tristate ++ tristate "Textsearch FSM" + + config BTREE + bool diff --git a/target/linux/generic/patches-4.0/255-lib80211_kconfig_hacks.patch b/target/linux/generic/patches-4.0/255-lib80211_kconfig_hacks.patch new file mode 100644 index 0000000..d875235 --- /dev/null +++ b/target/linux/generic/patches-4.0/255-lib80211_kconfig_hacks.patch @@ -0,0 +1,31 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -183,7 +183,7 @@ config CFG80211_WEXT + extensions with cfg80211-based drivers. + + config LIB80211 +- tristate ++ tristate "LIB80211" + default n + help + This options enables a library of common routines used +@@ -192,13 +192,16 @@ config LIB80211 + Drivers should select this themselves if needed. + + config LIB80211_CRYPT_WEP +- tristate ++ tristate "LIB80211_CRYPT_WEP" ++ select LIB80211 + + config LIB80211_CRYPT_CCMP +- tristate ++ tristate "LIB80211_CRYPT_CCMP" ++ select LIB80211 + + config LIB80211_CRYPT_TKIP +- tristate ++ tristate "LIB80211_CRYPT_TKIP" ++ select LIB80211 + + config LIB80211_DEBUG + bool "lib80211 debugging messages" diff --git a/target/linux/generic/patches-4.0/256-crypto_add_kconfig_prompts.patch b/target/linux/generic/patches-4.0/256-crypto_add_kconfig_prompts.patch new file mode 100644 index 0000000..f9f6c0e --- /dev/null +++ b/target/linux/generic/patches-4.0/256-crypto_add_kconfig_prompts.patch @@ -0,0 +1,47 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -32,7 +32,7 @@ config CRYPTO_FIPS + this is. + + config CRYPTO_ALGAPI +- tristate ++ tristate "ALGAPI" + select CRYPTO_ALGAPI2 + help + This option provides the API for cryptographic algorithms. +@@ -41,7 +41,7 @@ config CRYPTO_ALGAPI2 + tristate + + config CRYPTO_AEAD +- tristate ++ tristate "AEAD" + select CRYPTO_AEAD2 + select CRYPTO_ALGAPI + +@@ -50,7 +50,7 @@ config CRYPTO_AEAD2 + select CRYPTO_ALGAPI2 + + config CRYPTO_BLKCIPHER +- tristate ++ tristate "BLKCIPHER" + select CRYPTO_BLKCIPHER2 + select CRYPTO_ALGAPI + +@@ -61,7 +61,7 @@ config CRYPTO_BLKCIPHER2 + select CRYPTO_WORKQUEUE + + config CRYPTO_HASH +- tristate ++ tristate "HASH" + select CRYPTO_HASH2 + select CRYPTO_ALGAPI + +@@ -70,7 +70,7 @@ config CRYPTO_HASH2 + select CRYPTO_ALGAPI2 + + config CRYPTO_RNG +- tristate ++ tristate "RNG" + select CRYPTO_RNG2 + select CRYPTO_ALGAPI + diff --git a/target/linux/generic/patches-4.0/257-wireless_ext_kconfig_hack.patch b/target/linux/generic/patches-4.0/257-wireless_ext_kconfig_hack.patch new file mode 100644 index 0000000..daac589 --- /dev/null +++ b/target/linux/generic/patches-4.0/257-wireless_ext_kconfig_hack.patch @@ -0,0 +1,22 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -1,5 +1,5 @@ + config WIRELESS_EXT +- bool ++ bool "Wireless extensions" + + config WEXT_CORE + def_bool y +@@ -11,10 +11,10 @@ config WEXT_PROC + depends on WEXT_CORE + + config WEXT_SPY +- bool ++ bool "WEXT_SPY" + + config WEXT_PRIV +- bool ++ bool "WEXT_PRIV" + + config CFG80211 + tristate "cfg80211 - wireless configuration API" diff --git a/target/linux/generic/patches-4.0/258-netfilter_netlink_kconfig_hack.patch b/target/linux/generic/patches-4.0/258-netfilter_netlink_kconfig_hack.patch new file mode 100644 index 0000000..9d827c2 --- /dev/null +++ b/target/linux/generic/patches-4.0/258-netfilter_netlink_kconfig_hack.patch @@ -0,0 +1,11 @@ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -2,7 +2,7 @@ menu "Core Netfilter Configuration" + depends on NET && INET && NETFILTER + + config NETFILTER_NETLINK +- tristate ++ tristate "Netfilter NFNETLINK interface" + + config NETFILTER_NETLINK_ACCT + tristate "Netfilter NFACCT over NFNETLINK interface" diff --git a/target/linux/generic/patches-4.0/259-regmap_dynamic.patch b/target/linux/generic/patches-4.0/259-regmap_dynamic.patch new file mode 100644 index 0000000..084b3b4 --- /dev/null +++ b/target/linux/generic/patches-4.0/259-regmap_dynamic.patch @@ -0,0 +1,84 @@ +--- a/drivers/base/regmap/Kconfig ++++ b/drivers/base/regmap/Kconfig +@@ -3,29 +3,35 @@ + # subsystems should select the appropriate symbols. + + config REGMAP +- default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ) + select LZO_COMPRESS + select LZO_DECOMPRESS + select IRQ_DOMAIN if REGMAP_IRQ +- bool ++ tristate "Regmap" + + config REGMAP_AC97 ++ select REGMAP + tristate + + config REGMAP_I2C +- tristate ++ tristate "Regmap I2C" ++ select REGMAP + depends on I2C + + config REGMAP_SPI +- tristate ++ tristate "Regmap SPI" ++ select REGMAP ++ depends on SPI_MASTER + depends on SPI + + config REGMAP_SPMI ++ select REGMAP + tristate + depends on SPMI + + config REGMAP_MMIO +- tristate ++ tristate "Regmap MMIO" ++ select REGMAP + + config REGMAP_IRQ ++ select REGMAP + bool +--- a/include/linux/regmap.h ++++ b/include/linux/regmap.h +@@ -50,7 +50,7 @@ struct reg_default { + unsigned int def; + }; + +-#ifdef CONFIG_REGMAP ++#if IS_ENABLED(CONFIG_REGMAP) + + enum regmap_endian { + /* Unspecified -> 0 -> Backwards compatible default */ +--- a/drivers/base/regmap/Makefile ++++ b/drivers/base/regmap/Makefile +@@ -1,6 +1,8 @@ +-obj-$(CONFIG_REGMAP) += regmap.o regcache.o +-obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-lzo.o regcache-flat.o +-obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o ++regmap-core-objs = regmap.o regcache.o regcache-rbtree.o regcache-lzo.o regcache-flat.o ++ifdef CONFIG_DEBUG_FS ++regmap-core-objs += regmap-debugfs.o ++endif ++obj-$(CONFIG_REGMAP) += regmap-core.o + obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o + obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o + obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o +--- a/drivers/base/regmap/regmap.c ++++ b/drivers/base/regmap/regmap.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -2631,3 +2632,5 @@ static int __init regmap_initcall(void) + return 0; + } + postcore_initcall(regmap_initcall); ++ ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.0/260-crypto_test_dependencies.patch b/target/linux/generic/patches-4.0/260-crypto_test_dependencies.patch new file mode 100644 index 0000000..8a96fd9 --- /dev/null +++ b/target/linux/generic/patches-4.0/260-crypto_test_dependencies.patch @@ -0,0 +1,37 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -96,10 +96,10 @@ config CRYPTO_MANAGER + + config CRYPTO_MANAGER2 + def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) +- select CRYPTO_AEAD2 +- select CRYPTO_HASH2 +- select CRYPTO_BLKCIPHER2 +- select CRYPTO_PCOMP2 ++ select CRYPTO_AEAD2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_HASH2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_BLKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_PCOMP2 if !CRYPTO_MANAGER_DISABLE_TESTS + + config CRYPTO_USER + tristate "Userspace cryptographic algorithm configuration" +--- a/crypto/algboss.c ++++ b/crypto/algboss.c +@@ -248,6 +248,9 @@ static int cryptomgr_schedule_test(struc + type = alg->cra_flags; + + /* This piece of crap needs to disappear into per-type test hooks. */ ++#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS ++ type |= CRYPTO_ALG_TESTED; ++#else + if ((!((type ^ CRYPTO_ALG_TYPE_BLKCIPHER) & + CRYPTO_ALG_TYPE_BLKCIPHER_MASK) && !(type & CRYPTO_ALG_GENIV) && + ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == +@@ -256,6 +259,7 @@ static int cryptomgr_schedule_test(struc + (!((type ^ CRYPTO_ALG_TYPE_AEAD) & CRYPTO_ALG_TYPE_MASK) && + alg->cra_type == &crypto_nivaead_type && alg->cra_aead.ivsize)) + type |= CRYPTO_ALG_TESTED; ++#endif + + param->type = type; + diff --git a/target/linux/generic/patches-4.0/262-compressor_kconfig_hack.patch b/target/linux/generic/patches-4.0/262-compressor_kconfig_hack.patch new file mode 100644 index 0000000..64db082 --- /dev/null +++ b/target/linux/generic/patches-4.0/262-compressor_kconfig_hack.patch @@ -0,0 +1,35 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -214,25 +214,25 @@ config RANDOM32_SELFTEST + # compression support is select'ed if needed + # + config ZLIB_INFLATE +- tristate ++ tristate "ZLIB inflate support" + + config ZLIB_DEFLATE +- tristate ++ tristate "ZLIB deflate support" + + config LZO_COMPRESS +- tristate ++ tristate "LZO compress support" + + config LZO_DECOMPRESS +- tristate ++ tristate "LZO decompress support" + + config LZ4_COMPRESS +- tristate ++ tristate "LZ4 compress support" + + config LZ4HC_COMPRESS +- tristate ++ tristate "LZ4HC compress support" + + config LZ4_DECOMPRESS +- tristate ++ tristate "LZ4 decompress support" + + source "lib/xz/Kconfig" + diff --git a/target/linux/generic/patches-4.0/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch b/target/linux/generic/patches-4.0/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch new file mode 100644 index 0000000..762f498 --- /dev/null +++ b/target/linux/generic/patches-4.0/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch @@ -0,0 +1,34 @@ +From 8b05e325824d3b38e52a7748b3b5dc34dc1c0f6d Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 14:37:54 +0200 +Subject: [PATCH 1/3] uapi/kernel.h: glibc specific inclusion of sysinfo.h + +including sysinfo.h from kernel.h makes no sense whatsoever, +but removing it breaks glibc's userspace header, +which includes kernel.h instead of sysinfo.h from their sys/sysinfo.h. +this seems to be a historical mistake. +on musl, including any header that uses kernel.h directly or indirectly +plus sys/sysinfo.h will produce a compile error due to redefinition of +struct sysinfo from sys/sysinfo.h. +so for now, only include it on glibc or when including from kernel +in order not to break their headers. + +Signed-off-by: John Spencer +Signed-off-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/kernel.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/include/uapi/linux/kernel.h ++++ b/include/uapi/linux/kernel.h +@@ -1,7 +1,9 @@ + #ifndef _UAPI_LINUX_KERNEL_H + #define _UAPI_LINUX_KERNEL_H + ++#if defined(__KERNEL__) || defined( __GLIBC__) + #include ++#endif + + /* + * 'kernel.h' contains some often-used function prototypes etc diff --git a/target/linux/generic/patches-4.0/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch b/target/linux/generic/patches-4.0/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch new file mode 100644 index 0000000..61d3873 --- /dev/null +++ b/target/linux/generic/patches-4.0/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch @@ -0,0 +1,81 @@ +From f972afc2509eebcb00d370256c55b112a3b5ffca Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 16:50:40 +0200 +Subject: [PATCH 2/3] uapi/libc-compat.h: do not rely on __GLIBC__ + +Musl provides the same structs as glibc, but does not provide a define to +allow its detection. Since the absence of __GLIBC__ also can mean that it +is included from the kernel, change the __GLIBC__ detection to +!__KERNEL__, which should always be true when included from userspace. + +Signed-off-by: John Spencer +Tested-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/libc-compat.h | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -48,13 +48,13 @@ + #ifndef _UAPI_LIBC_COMPAT_H + #define _UAPI_LIBC_COMPAT_H + +-/* We have included glibc headers... */ +-#if defined(__GLIBC__) ++/* We have included libc headers... */ ++#if !defined(__KERNEL__) + +-/* Coordinate with glibc netinet/in.h header. */ ++/* Coordinate with libc netinet/in.h header. */ + #if defined(_NETINET_IN_H) + +-/* GLIBC headers included first so don't define anything ++/* LIBC headers included first so don't define anything + * that would already be defined. */ + #define __UAPI_DEF_IN_ADDR 0 + #define __UAPI_DEF_IN_IPPROTO 0 +@@ -68,7 +68,7 @@ + * if the glibc code didn't define them. This guard matches + * the guard in glibc/inet/netinet/in.h which defines the + * additional in6_addr macros e.g. s6_addr16, and s6_addr32. */ +-#if defined(__USE_MISC) || defined (__USE_GNU) ++#if !defined(__GLIBC__) || defined(__USE_MISC) || defined (__USE_GNU) + #define __UAPI_DEF_IN6_ADDR_ALT 0 + #else + #define __UAPI_DEF_IN6_ADDR_ALT 1 +@@ -83,7 +83,7 @@ + #else + + /* Linux headers included first, and we must define everything +- * we need. The expectation is that glibc will check the ++ * we need. The expectation is that the libc will check the + * __UAPI_DEF_* defines and adjust appropriately. */ + #define __UAPI_DEF_IN_ADDR 1 + #define __UAPI_DEF_IN_IPPROTO 1 +@@ -93,7 +93,7 @@ + #define __UAPI_DEF_IN_CLASS 1 + + #define __UAPI_DEF_IN6_ADDR 1 +-/* We unconditionally define the in6_addr macros and glibc must ++/* We unconditionally define the in6_addr macros and the libc must + * coordinate. */ + #define __UAPI_DEF_IN6_ADDR_ALT 1 + #define __UAPI_DEF_SOCKADDR_IN6 1 +@@ -115,7 +115,7 @@ + /* If we did not see any headers from any supported C libraries, + * or we are being included in the kernel, then define everything + * that we need. */ +-#else /* !defined(__GLIBC__) */ ++#else /* defined(__KERNEL__) */ + + /* Definitions for in.h */ + #define __UAPI_DEF_IN_ADDR 1 +@@ -138,6 +138,6 @@ + /* Definitions for xattr.h */ + #define __UAPI_DEF_XATTR 1 + +-#endif /* __GLIBC__ */ ++#endif /* __KERNEL__ */ + + #endif /* _UAPI_LIBC_COMPAT_H */ diff --git a/target/linux/generic/patches-4.0/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch b/target/linux/generic/patches-4.0/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch new file mode 100644 index 0000000..257c9d7 --- /dev/null +++ b/target/linux/generic/patches-4.0/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch @@ -0,0 +1,67 @@ +From fcbb6fed85ea9ff4feb4f1ebd4f0f235fdaf06b6 Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 16:53:03 +0200 +Subject: [PATCH 3/3] uapi/if_ether.h: prevent redefinition of struct ethhdr + +Musl provides its own ethhdr struct definition. Add a guard to prevent +its definition of the appropriate musl header has already been included. + +Signed-off-by: John Spencer +Tested-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/if_ether.h | 3 +++ + include/uapi/linux/libc-compat.h | 11 +++++++++++ + 2 files changed, 14 insertions(+) + +--- a/include/uapi/linux/if_ether.h ++++ b/include/uapi/linux/if_ether.h +@@ -22,6 +22,7 @@ + #define _UAPI_LINUX_IF_ETHER_H + + #include ++#include + + /* + * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble +@@ -134,11 +135,13 @@ + * This is an Ethernet frame header. + */ + ++#if __UAPI_DEF_ETHHDR + struct ethhdr { + unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ + unsigned char h_source[ETH_ALEN]; /* source ether addr */ + __be16 h_proto; /* packet type ID field */ + } __attribute__((packed)); ++#endif + + + #endif /* _UAPI_LINUX_IF_ETHER_H */ +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -51,6 +51,14 @@ + /* We have included libc headers... */ + #if !defined(__KERNEL__) + ++/* musl defines the ethhdr struct itself in its netinet/if_ether.h. ++ * Glibc just includes the kernel header and uses a different guard. */ ++#if defined(_NETINET_IF_ETHER_H) ++#define __UAPI_DEF_ETHHDR 0 ++#else ++#define __UAPI_DEF_ETHHDR 1 ++#endif ++ + /* Coordinate with libc netinet/in.h header. */ + #if defined(_NETINET_IN_H) + +@@ -117,6 +125,9 @@ + * that we need. */ + #else /* defined(__KERNEL__) */ + ++/* Definitions for if_ether.h */ ++#define __UAPI_DEF_ETHHDR 1 ++ + /* Definitions for in.h */ + #define __UAPI_DEF_IN_ADDR 1 + #define __UAPI_DEF_IN_IPPROTO 1 diff --git a/target/linux/generic/patches-4.0/300-mips_expose_boot_raw.patch b/target/linux/generic/patches-4.0/300-mips_expose_boot_raw.patch new file mode 100644 index 0000000..a609450 --- /dev/null +++ b/target/linux/generic/patches-4.0/300-mips_expose_boot_raw.patch @@ -0,0 +1,39 @@ +From: Mark Miller + +This exposes the CONFIG_BOOT_RAW symbol in Kconfig. This is needed on +certain Broadcom chipsets running CFE in order to load the kernel. + +Signed-off-by: Mark Miller +Acked-by: Rob Landley +--- +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -941,9 +941,6 @@ config FW_ARC + config ARCH_MAY_HAVE_PC_FDC + bool + +-config BOOT_RAW +- bool +- + config CEVT_BCM1480 + bool + +@@ -2594,6 +2591,18 @@ config USE_OF + config BUILTIN_DTB + bool + ++config BOOT_RAW ++ bool "Enable the kernel to be executed from the load address" ++ default n ++ help ++ Allow the kernel to be executed from the load address for ++ bootloaders which cannot read the ELF format. This places ++ a jump to start_kernel at the load address. ++ ++ If unsure, say N. ++ ++ ++ + endmenu + + config LOCKDEP_SUPPORT diff --git a/target/linux/generic/patches-4.0/301-mips_image_cmdline_hack.patch b/target/linux/generic/patches-4.0/301-mips_image_cmdline_hack.patch new file mode 100644 index 0000000..b5032e2 --- /dev/null +++ b/target/linux/generic/patches-4.0/301-mips_image_cmdline_hack.patch @@ -0,0 +1,28 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1030,6 +1030,10 @@ config SYNC_R4K + config MIPS_MACHINE + def_bool n + ++config IMAGE_CMDLINE_HACK ++ bool "OpenWrt specific image command line hack" ++ default n ++ + config NO_IOPORT_MAP + def_bool n + +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -80,6 +80,12 @@ FEXPORT(__kernel_entry) + j kernel_entry + #endif + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++ .ascii "CMDLINE:" ++EXPORT(__image_cmdline) ++ .fill 0x400 ++#endif /* CONFIG_IMAGE_CMDLINE_HACK */ ++ + __REF + + NESTED(kernel_entry, 16, sp) # kernel entry point diff --git a/target/linux/generic/patches-4.0/302-mips_no_branch_likely.patch b/target/linux/generic/patches-4.0/302-mips_no_branch_likely.patch new file mode 100644 index 0000000..44c6b04 --- /dev/null +++ b/target/linux/generic/patches-4.0/302-mips_no_branch_likely.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -87,7 +87,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + # machines may also. Since BFD is incredibly buggy with respect to + # crossformat linking we rely on the elf2ecoff tool for format conversion. + # +-cflags-y += -G 0 -mno-abicalls -fno-pic -pipe ++cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely + cflags-y += -msoft-float + LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections + KBUILD_AFLAGS_MODULE += -mlong-calls diff --git a/target/linux/generic/patches-4.0/304-mips_disable_fpu.patch b/target/linux/generic/patches-4.0/304-mips_disable_fpu.patch new file mode 100644 index 0000000..080afa3 --- /dev/null +++ b/target/linux/generic/patches-4.0/304-mips_disable_fpu.patch @@ -0,0 +1,105 @@ +From: Manuel Lauss +Subject: [RFC PATCH v4 2/2] MIPS: make FPU emulator optional +Date: Mon, 7 Apr 2014 12:57:04 +0200 +Message-Id: <1396868224-252888-2-git-send-email-manuel.lauss@gmail.com> + +This small patch makes the MIPS FPU emulator optional. The kernel +kills float-users on systems without a hardware FPU by sending a SIGILL. + +Disabling the emulator shrinks vmlinux by about 54kBytes (32bit, +optimizing for size). + +Signed-off-by: Manuel Lauss +--- +v4: rediffed because of patch 1/2, should now work with micromips as well +v3: updated patch description with size savings. +v2: incorporated changes suggested by Jonas Gorski + force the fpu emulator on for micromips: relocating the parts + of the mmips code in the emulator to other areas would be a + much larger change; I went the cheap route instead with this. + + arch/mips/Kbuild | 2 +- + arch/mips/Kconfig | 14 ++++++++++++++ + arch/mips/include/asm/fpu.h | 5 +++-- + arch/mips/include/asm/fpu_emulator.h | 15 +++++++++++++++ + 4 files changed, 33 insertions(+), 3 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2586,6 +2586,20 @@ config MIPS_O32_FP64_SUPPORT + + If unsure, say N. + ++config MIPS_FPU_EMULATOR ++ bool "MIPS FPU Emulator" ++ default y ++ help ++ This option lets you disable the built-in MIPS FPU (Coprocessor 1) ++ emulator, which handles floating-point instructions on processors ++ without a hardware FPU. It is generally a good idea to keep the ++ emulator built-in, unless you are perfectly sure you have a ++ complete soft-float environment. With the emulator disabled, all ++ users of float operations will be killed with an illegal instr- ++ uction exception. ++ ++ Say Y, please. ++ + config USE_OF + bool + select OF +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -292,7 +292,7 @@ OBJCOPYFLAGS += --remove-section=.regin + head-y := arch/mips/kernel/head.o + + libs-y += arch/mips/lib/ +-libs-y += arch/mips/math-emu/ ++libs-$(CONFIG_MIPS_FPU_EMULATOR) += arch/mips/math-emu/ + + # See arch/mips/Kbuild for content of core part of the kernel + core-y += arch/mips/ +--- a/arch/mips/include/asm/fpu.h ++++ b/arch/mips/include/asm/fpu.h +@@ -212,8 +212,10 @@ static inline int init_fpu(void) + /* Restore FRE */ + write_c0_config5(config5); + enable_fpu_hazard(); +- } else ++ } else if (IS_ENABLED(CONFIG_MIPS_FPU_EMULATOR)) + fpu_emulator_init_fpu(); ++ else ++ ret = SIGILL; + + return ret; + } +--- a/arch/mips/include/asm/fpu_emulator.h ++++ b/arch/mips/include/asm/fpu_emulator.h +@@ -30,6 +30,7 @@ + #include + #include + ++#ifdef CONFIG_MIPS_FPU_EMULATOR + #ifdef CONFIG_DEBUG_FS + + struct mips_fpu_emulator_stats { +@@ -65,6 +66,20 @@ extern int do_dsemulret(struct pt_regs * + extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, + struct mips_fpu_struct *ctx, int has_fpu, + void *__user *fault_addr); ++#else /* no CONFIG_MIPS_FPU_EMULATOR */ ++static inline int do_dsemulret(struct pt_regs *xcp) ++{ ++ return 0; /* 0 means error, should never get here anyway */ ++} ++ ++static inline int fpu_emulator_cop1Handler(struct pt_regs *xcp, ++ struct mips_fpu_struct *ctx, int has_fpu, ++ void *__user *fault_addr) ++{ ++ return SIGILL; /* we don't speak MIPS FPU */ ++} ++#endif /* CONFIG_MIPS_FPU_EMULATOR */ ++ + int process_fpemu_return(int sig, void __user *fault_addr); + int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, + unsigned long *contpc); diff --git a/target/linux/generic/patches-4.0/305-mips_module_reloc.patch b/target/linux/generic/patches-4.0/305-mips_module_reloc.patch new file mode 100644 index 0000000..8b3975f --- /dev/null +++ b/target/linux/generic/patches-4.0/305-mips_module_reloc.patch @@ -0,0 +1,352 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -90,8 +90,13 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely + cflags-y += -msoft-float + LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections ++ifdef CONFIG_64BIT + KBUILD_AFLAGS_MODULE += -mlong-calls + KBUILD_CFLAGS_MODULE += -mlong-calls ++else ++KBUILD_AFLAGS_MODULE += -mno-long-calls ++KBUILD_CFLAGS_MODULE += -mno-long-calls ++endif + + ifndef CONFIG_FUNCTION_TRACER + KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections +--- a/arch/mips/include/asm/module.h ++++ b/arch/mips/include/asm/module.h +@@ -11,6 +11,11 @@ struct mod_arch_specific { + const struct exception_table_entry *dbe_start; + const struct exception_table_entry *dbe_end; + struct mips_hi16 *r_mips_hi16_list; ++ ++ void *phys_plt_tbl; ++ void *virt_plt_tbl; ++ unsigned int phys_plt_offset; ++ unsigned int virt_plt_offset; + }; + + typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ +--- a/arch/mips/kernel/module.c ++++ b/arch/mips/kernel/module.c +@@ -43,14 +43,221 @@ struct mips_hi16 { + static LIST_HEAD(dbe_list); + static DEFINE_SPINLOCK(dbe_lock); + +-#ifdef MODULE_START ++/* ++ * Get the potential max trampolines size required of the init and ++ * non-init sections. Only used if we cannot find enough contiguous ++ * physically mapped memory to put the module into. ++ */ ++static unsigned int ++get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, ++ const char *secstrings, unsigned int symindex, bool is_init) ++{ ++ unsigned long ret = 0; ++ unsigned int i, j; ++ Elf_Sym *syms; ++ ++ /* Everything marked ALLOC (this includes the exported symbols) */ ++ for (i = 1; i < hdr->e_shnum; ++i) { ++ unsigned int info = sechdrs[i].sh_info; ++ ++ if (sechdrs[i].sh_type != SHT_REL ++ && sechdrs[i].sh_type != SHT_RELA) ++ continue; ++ ++ /* Not a valid relocation section? */ ++ if (info >= hdr->e_shnum) ++ continue; ++ ++ /* Don't bother with non-allocated sections */ ++ if (!(sechdrs[info].sh_flags & SHF_ALLOC)) ++ continue; ++ ++ /* If it's called *.init*, and we're not init, we're ++ not interested */ ++ if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0) ++ != is_init) ++ continue; ++ ++ syms = (Elf_Sym *) sechdrs[symindex].sh_addr; ++ if (sechdrs[i].sh_type == SHT_REL) { ++ Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr; ++ unsigned int size = sechdrs[i].sh_size / sizeof(*rel); ++ ++ for (j = 0; j < size; ++j) { ++ Elf_Sym *sym; ++ ++ if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26) ++ continue; ++ ++ sym = syms + ELF_MIPS_R_SYM(rel[j]); ++ if (!is_init && sym->st_shndx != SHN_UNDEF) ++ continue; ++ ++ ret += 4 * sizeof(int); ++ } ++ } else { ++ Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr; ++ unsigned int size = sechdrs[i].sh_size / sizeof(*rela); ++ ++ for (j = 0; j < size; ++j) { ++ Elf_Sym *sym; ++ ++ if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26) ++ continue; ++ ++ sym = syms + ELF_MIPS_R_SYM(rela[j]); ++ if (!is_init && sym->st_shndx != SHN_UNDEF) ++ continue; ++ ++ ret += 4 * sizeof(int); ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++#ifndef MODULE_START ++static void *alloc_phys(unsigned long size) ++{ ++ unsigned order; ++ struct page *page; ++ struct page *p; ++ ++ size = PAGE_ALIGN(size); ++ order = get_order(size); ++ ++ page = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN | ++ __GFP_THISNODE, order); ++ if (!page) ++ return NULL; ++ ++ split_page(page, order); ++ ++ /* mark all pages except for the last one */ ++ for (p = page; p + 1 < page + (size >> PAGE_SHIFT); ++p) ++ set_bit(PG_owner_priv_1, &p->flags); ++ ++ for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p) ++ __free_page(p); ++ ++ return page_address(page); ++} ++#endif ++ ++static void free_phys(void *ptr) ++{ ++ struct page *page; ++ bool free; ++ ++ page = virt_to_page(ptr); ++ do { ++ free = test_and_clear_bit(PG_owner_priv_1, &page->flags); ++ __free_page(page); ++ page++; ++ } while (free); ++} ++ ++ + void *module_alloc(unsigned long size) + { ++#ifdef MODULE_START + return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, + GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, + __builtin_return_address(0)); ++#else ++ void *ptr; ++ ++ if (size == 0) ++ return NULL; ++ ++ ptr = alloc_phys(size); ++ ++ /* If we failed to allocate physically contiguous memory, ++ * fall back to regular vmalloc. The module loader code will ++ * create jump tables to handle long jumps */ ++ if (!ptr) ++ return vmalloc(size); ++ ++ return ptr; ++#endif + } ++ ++static inline bool is_phys_addr(void *ptr) ++{ ++#ifdef CONFIG_64BIT ++ return (KSEGX((unsigned long)ptr) == CKSEG0); ++#else ++ return (KSEGX(ptr) == KSEG0); + #endif ++} ++ ++/* Free memory returned from module_alloc */ ++void module_memfree(void *module_region) ++{ ++ if (is_phys_addr(module_region)) ++ free_phys(module_region); ++ else ++ vfree(module_region); ++} ++ ++static void *__module_alloc(int size, bool phys) ++{ ++ void *ptr; ++ ++ if (phys) ++ ptr = kmalloc(size, GFP_KERNEL); ++ else ++ ptr = vmalloc(size); ++ return ptr; ++} ++ ++static void __module_free(void *ptr) ++{ ++ if (is_phys_addr(ptr)) ++ kfree(ptr); ++ else ++ vfree(ptr); ++} ++ ++int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, ++ char *secstrings, struct module *mod) ++{ ++ unsigned int symindex = 0; ++ unsigned int core_size, init_size; ++ int i; ++ ++ mod->arch.phys_plt_offset = 0; ++ mod->arch.virt_plt_offset = 0; ++ mod->arch.phys_plt_tbl = NULL; ++ mod->arch.virt_plt_tbl = NULL; ++ ++ if (IS_ENABLED(CONFIG_64BIT)) ++ return 0; ++ ++ for (i = 1; i < hdr->e_shnum; i++) ++ if (sechdrs[i].sh_type == SHT_SYMTAB) ++ symindex = i; ++ ++ core_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false); ++ init_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true); ++ ++ if ((core_size + init_size) == 0) ++ return 0; ++ ++ mod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1); ++ if (!mod->arch.phys_plt_tbl) ++ return -ENOMEM; ++ ++ mod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0); ++ if (!mod->arch.virt_plt_tbl) { ++ __module_free(mod->arch.phys_plt_tbl); ++ mod->arch.phys_plt_tbl = NULL; ++ return -ENOMEM; ++ } ++ ++ return 0; ++} + + int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v) + { +@@ -64,8 +271,39 @@ static int apply_r_mips_32_rel(struct mo + return 0; + } + ++static Elf_Addr add_plt_entry_to(unsigned *plt_offset, ++ void *start, Elf_Addr v) ++{ ++ unsigned *tramp = start + *plt_offset; ++ *plt_offset += 4 * sizeof(int); ++ ++ /* adjust carry for addiu */ ++ if (v & 0x00008000) ++ v += 0x10000; ++ ++ tramp[0] = 0x3c190000 | (v >> 16); /* lui t9, hi16 */ ++ tramp[1] = 0x27390000 | (v & 0xffff); /* addiu t9, t9, lo16 */ ++ tramp[2] = 0x03200008; /* jr t9 */ ++ tramp[3] = 0x00000000; /* nop */ ++ ++ return (Elf_Addr) tramp; ++} ++ ++static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v) ++{ ++ if (is_phys_addr(location)) ++ return add_plt_entry_to(&me->arch.phys_plt_offset, ++ me->arch.phys_plt_tbl, v); ++ else ++ return add_plt_entry_to(&me->arch.virt_plt_offset, ++ me->arch.virt_plt_tbl, v); ++ ++} ++ + static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v) + { ++ u32 ofs = *location & 0x03ffffff; ++ + if (v % 4) { + pr_err("module %s: dangerous R_MIPS_26 REL relocation\n", + me->name); +@@ -73,14 +311,17 @@ static int apply_r_mips_26_rel(struct mo + } + + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { +- printk(KERN_ERR +- "module %s: relocation overflow\n", +- me->name); +- return -ENOEXEC; ++ v = add_plt_entry(me, location, v + (ofs << 2)); ++ if (!v) { ++ printk(KERN_ERR ++ "module %s: relocation overflow\n", me->name); ++ return -ENOEXEC; ++ } ++ ofs = 0; + } + + *location = (*location & ~0x03ffffff) | +- ((*location + (v >> 2)) & 0x03ffffff); ++ ((ofs + (v >> 2)) & 0x03ffffff); + + return 0; + } +@@ -287,9 +528,33 @@ int module_finalize(const Elf_Ehdr *hdr, + list_add(&me->arch.dbe_list, &dbe_list); + spin_unlock_irq(&dbe_lock); + } ++ ++ /* Get rid of the fixup trampoline if we're running the module ++ * from physically mapped address space */ ++ if (me->arch.phys_plt_offset == 0) { ++ __module_free(me->arch.phys_plt_tbl); ++ me->arch.phys_plt_tbl = NULL; ++ } ++ if (me->arch.virt_plt_offset == 0) { ++ __module_free(me->arch.virt_plt_tbl); ++ me->arch.virt_plt_tbl = NULL; ++ } ++ + return 0; + } + ++void module_arch_freeing_init(struct module *mod) ++{ ++ if (mod->arch.phys_plt_tbl) { ++ __module_free(mod->arch.phys_plt_tbl); ++ mod->arch.phys_plt_tbl = NULL; ++ } ++ if (mod->arch.virt_plt_tbl) { ++ __module_free(mod->arch.virt_plt_tbl); ++ mod->arch.virt_plt_tbl = NULL; ++ } ++} ++ + void module_arch_cleanup(struct module *mod) + { + spin_lock_irq(&dbe_lock); diff --git a/target/linux/generic/patches-4.0/306-mips_mem_functions_performance.patch b/target/linux/generic/patches-4.0/306-mips_mem_functions_performance.patch new file mode 100644 index 0000000..9818677 --- /dev/null +++ b/target/linux/generic/patches-4.0/306-mips_mem_functions_performance.patch @@ -0,0 +1,83 @@ +--- a/arch/mips/include/asm/string.h ++++ b/arch/mips/include/asm/string.h +@@ -133,11 +133,44 @@ strncmp(__const__ char *__cs, __const__ + + #define __HAVE_ARCH_MEMSET + extern void *memset(void *__s, int __c, size_t __count); ++#define memset(__s, __c, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memset((__s), (__c), __len); \ ++ else \ ++ __ret = __builtin_memset((__s), (__c), __len); \ ++ __ret; \ ++}) + + #define __HAVE_ARCH_MEMCPY + extern void *memcpy(void *__to, __const__ void *__from, size_t __n); ++#define memcpy(dst, src, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memcpy((dst), (src), __len); \ ++ else \ ++ __ret = __builtin_memcpy((dst), (src), __len); \ ++ __ret; \ ++}) + + #define __HAVE_ARCH_MEMMOVE + extern void *memmove(void *__dest, __const__ void *__src, size_t __n); ++#define memmove(dst, src, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memmove((dst), (src), __len); \ ++ else \ ++ __ret = __builtin_memmove((dst), (src), __len); \ ++ __ret; \ ++}) ++ ++#define __HAVE_ARCH_MEMCMP ++#define memcmp(src1, src2, len) __builtin_memcmp((src1), (src2), (len)) + + #endif /* _ASM_STRING_H */ +--- a/arch/mips/lib/Makefile ++++ b/arch/mips/lib/Makefile +@@ -4,7 +4,7 @@ + + lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ + mips-atomic.o strlen_user.o strncpy_user.o \ +- strnlen_user.o uncached.o ++ strnlen_user.o uncached.o memcmp.o + + obj-y += iomap.o + obj-$(CONFIG_PCI) += iomap-pci.o +--- /dev/null ++++ b/arch/mips/lib/memcmp.c +@@ -0,0 +1,22 @@ ++/* ++ * copied from linux/lib/string.c ++ * ++ * Copyright (C) 1991, 1992 Linus Torvalds ++ */ ++ ++#include ++#include ++ ++#undef memcmp ++int memcmp(const void *cs, const void *ct, size_t count) ++{ ++ const unsigned char *su1, *su2; ++ int res = 0; ++ ++ for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) ++ if ((res = *su1 - *su2) != 0) ++ break; ++ return res; ++} ++EXPORT_SYMBOL(memcmp); ++ diff --git a/target/linux/generic/patches-4.0/307-mips_highmem_offset.patch b/target/linux/generic/patches-4.0/307-mips_highmem_offset.patch new file mode 100644 index 0000000..c9f0c84 --- /dev/null +++ b/target/linux/generic/patches-4.0/307-mips_highmem_offset.patch @@ -0,0 +1,17 @@ +Adjust highmem offset to 0x10000000 to ensure that all kmalloc allocations +stay within the same 256M boundary. This ensures that -mlong-calls is not +needed on systems with more than 256M RAM. + +Signed-off-by: Felix Fietkau +--- +--- a/arch/mips/include/asm/mach-generic/spaces.h ++++ b/arch/mips/include/asm/mach-generic/spaces.h +@@ -44,7 +44,7 @@ + * Memory above this physical address will be considered highmem. + */ + #ifndef HIGHMEM_START +-#define HIGHMEM_START _AC(0x20000000, UL) ++#define HIGHMEM_START _AC(0x10000000, UL) + #endif + + #endif /* CONFIG_32BIT */ diff --git a/target/linux/generic/patches-4.0/309-mips_fuse_workaround.patch b/target/linux/generic/patches-4.0/309-mips_fuse_workaround.patch new file mode 100644 index 0000000..dc9d89f --- /dev/null +++ b/target/linux/generic/patches-4.0/309-mips_fuse_workaround.patch @@ -0,0 +1,32 @@ +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -38,6 +38,7 @@ void (*__flush_cache_vunmap)(void); + + void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size); + EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); ++EXPORT_SYMBOL(__flush_cache_all); + void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size); + + /* MIPS specific cache operations */ +--- a/fs/fuse/dev.c ++++ b/fs/fuse/dev.c +@@ -20,6 +20,9 @@ + #include + #include + #include ++#ifdef CONFIG_MIPS ++#include ++#endif + + MODULE_ALIAS_MISCDEV(FUSE_MINOR); + MODULE_ALIAS("devname:fuse"); +@@ -825,6 +828,9 @@ static int fuse_copy_fill(struct fuse_co + static int fuse_copy_do(struct fuse_copy_state *cs, void **val, unsigned *size) + { + unsigned ncpy = min(*size, cs->len); ++#ifdef CONFIG_MIPS ++ __flush_cache_all(); ++#endif + if (val) { + void *pgaddr = kmap_atomic(cs->pg); + void *buf = pgaddr + cs->offset; diff --git a/target/linux/generic/patches-4.0/310-arm_module_unresolved_weak_sym.patch b/target/linux/generic/patches-4.0/310-arm_module_unresolved_weak_sym.patch new file mode 100644 index 0000000..9210c1d --- /dev/null +++ b/target/linux/generic/patches-4.0/310-arm_module_unresolved_weak_sym.patch @@ -0,0 +1,13 @@ +--- a/arch/arm/kernel/module.c ++++ b/arch/arm/kernel/module.c +@@ -83,6 +83,10 @@ apply_relocate(Elf32_Shdr *sechdrs, cons + return -ENOEXEC; + } + ++ if ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) && ++ ELF_ST_BIND(sym->st_info) == STB_WEAK) ++ continue; ++ + loc = dstsec->sh_addr + rel->r_offset; + + switch (ELF32_R_TYPE(rel->r_info)) { diff --git a/target/linux/generic/patches-4.0/320-ppc4xx_optimization.patch b/target/linux/generic/patches-4.0/320-ppc4xx_optimization.patch new file mode 100644 index 0000000..8673de4 --- /dev/null +++ b/target/linux/generic/patches-4.0/320-ppc4xx_optimization.patch @@ -0,0 +1,31 @@ +Upstream doesn't optimize the kernel and bootwrappers for ppc44x because +they still want to support gcc 3.3 -- well, we don't. + +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -203,7 +203,8 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) + KBUILD_CFLAGS += -mno-sched-epilog + endif + +-cpu-as-$(CONFIG_4xx) += -Wa,-m405 ++cpu-as-$(CONFIG_40x) += -Wa,-m405 ++cpu-as-$(CONFIG_44x) += -Wa,-m440 + cpu-as-$(CONFIG_ALTIVEC) += -Wa,-maltivec + cpu-as-$(CONFIG_E200) += -Wa,-me200 + +--- a/arch/powerpc/boot/Makefile ++++ b/arch/powerpc/boot/Makefile +@@ -45,10 +45,10 @@ BOOTCFLAGS += -I$(obj) -I$(srctree)/$(ob + DTC_FLAGS ?= -p 1024 + + $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 ++$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440 + $(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 ++$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=440 ++$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440 + $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 + $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 + $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405 diff --git a/target/linux/generic/patches-4.0/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/patches-4.0/321-powerpc_crtsavres_prereq.patch new file mode 100644 index 0000000..ab6ea7b --- /dev/null +++ b/target/linux/generic/patches-4.0/321-powerpc_crtsavres_prereq.patch @@ -0,0 +1,10 @@ +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -165,7 +165,6 @@ CPP = $(CC) -E $(KBUILD_CFLAGS) + + CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__ + +-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o + + ifeq ($(CONFIG_476FPE_ERR46),y) + KBUILD_LDFLAGS_MODULE += --ppc476-workaround \ diff --git a/target/linux/generic/patches-4.0/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch b/target/linux/generic/patches-4.0/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch new file mode 100644 index 0000000..a69d197 --- /dev/null +++ b/target/linux/generic/patches-4.0/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch @@ -0,0 +1,298 @@ +From d8582dcf1ed66eee88a11e4760f42c0d6c8822be Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 31 Jan 2015 22:26:03 +0800 +Subject: [PATCH 331/331] MIPS: kexec: Accept command line parameters from + userspace. + +Signed-off-by: Yousong Zhou +--- + arch/mips/kernel/machine_kexec.c | 153 +++++++++++++++++++++++++++++++----- + arch/mips/kernel/machine_kexec.h | 20 +++++ + arch/mips/kernel/relocate_kernel.S | 21 +++-- + 3 files changed, 167 insertions(+), 27 deletions(-) + create mode 100644 arch/mips/kernel/machine_kexec.h + +--- a/arch/mips/kernel/machine_kexec.c ++++ b/arch/mips/kernel/machine_kexec.c +@@ -10,45 +10,145 @@ + #include + #include + ++#include + #include + #include +- +-extern const unsigned char relocate_new_kernel[]; +-extern const size_t relocate_new_kernel_size; +- +-extern unsigned long kexec_start_address; +-extern unsigned long kexec_indirection_page; ++#include ++#include "machine_kexec.h" + + int (*_machine_kexec_prepare)(struct kimage *) = NULL; + void (*_machine_kexec_shutdown)(void) = NULL; + void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL; ++ + #ifdef CONFIG_SMP + void (*relocated_kexec_smp_wait) (void *); + atomic_t kexec_ready_to_reboot = ATOMIC_INIT(0); + #endif + +-int +-machine_kexec_prepare(struct kimage *kimage) ++static void machine_kexec_print_args(void) + { ++ unsigned long argc = (int)kexec_args[0]; ++ int i; ++ ++ pr_info("kexec_args[0] (argc): %lu\n", argc); ++ pr_info("kexec_args[1] (argv): %p\n", (void *)kexec_args[1]); ++ pr_info("kexec_args[2] (env ): %p\n", (void *)kexec_args[2]); ++ pr_info("kexec_args[3] (desc): %p\n", (void *)kexec_args[3]); ++ ++ for (i = 0; i < argc; i++) { ++ pr_info("kexec_argv[%d] = %p, %s\n", ++ i, kexec_argv[i], kexec_argv[i]); ++ } ++} ++ ++static void machine_kexec_init_argv(struct kimage *image) ++{ ++ void __user *buf = NULL; ++ size_t bufsz; ++ size_t size; ++ int i; ++ ++ bufsz = 0; ++ for (i = 0; i < image->nr_segments; i++) { ++ struct kexec_segment *seg; ++ ++ seg = &image->segment[i]; ++ if (seg->bufsz < 6) ++ continue; ++ ++ if (strncmp((char *) seg->buf, "kexec ", 6)) ++ continue; ++ ++ buf = seg->buf; ++ bufsz = seg->bufsz; ++ break; ++ } ++ ++ if (!buf) ++ return; ++ ++ size = KEXEC_COMMAND_LINE_SIZE; ++ size = min(size, bufsz); ++ if (size < bufsz) ++ pr_warn("kexec command line truncated to %zd bytes\n", size); ++ ++ /* Copy to kernel space */ ++ copy_from_user(kexec_argv_buf, buf, size); ++ kexec_argv_buf[size - 1] = 0; ++} ++ ++static void machine_kexec_parse_argv(struct kimage *image) ++{ ++ char *reboot_code_buffer; ++ int reloc_delta; ++ char *ptr; ++ int argc; ++ int i; ++ ++ ptr = kexec_argv_buf; ++ argc = 0; ++ ++ /* ++ * convert command line string to array of parameters ++ * (as bootloader does). ++ */ ++ while (ptr && *ptr && (KEXEC_MAX_ARGC > argc)) { ++ if (*ptr == ' ') { ++ *ptr++ = '\0'; ++ continue; ++ } ++ ++ kexec_argv[argc++] = ptr; ++ ptr = strchr(ptr, ' '); ++ } ++ ++ if (!argc) ++ return; ++ ++ kexec_args[0] = argc; ++ kexec_args[1] = (unsigned long)kexec_argv; ++ kexec_args[2] = 0; ++ kexec_args[3] = 0; ++ ++ reboot_code_buffer = page_address(image->control_code_page); ++ reloc_delta = reboot_code_buffer - (char *)kexec_relocate_new_kernel; ++ ++ kexec_args[1] += reloc_delta; ++ for (i = 0; i < argc; i++) ++ kexec_argv[i] += reloc_delta; ++} ++ ++int machine_kexec_prepare(struct kimage *kimage) ++{ ++ /* ++ * Whenever arguments passed from kexec-tools, Init the arguments as ++ * the original ones to try avoiding booting failure. ++ */ ++ ++ kexec_args[0] = fw_arg0; ++ kexec_args[1] = fw_arg1; ++ kexec_args[2] = fw_arg2; ++ kexec_args[3] = fw_arg3; ++ ++ machine_kexec_init_argv(kimage); ++ machine_kexec_parse_argv(kimage); ++ + if (_machine_kexec_prepare) + return _machine_kexec_prepare(kimage); + return 0; + } + +-void +-machine_kexec_cleanup(struct kimage *kimage) ++void machine_kexec_cleanup(struct kimage *kimage) + { + } + +-void +-machine_shutdown(void) ++void machine_shutdown(void) + { + if (_machine_kexec_shutdown) + _machine_kexec_shutdown(); + } + +-void +-machine_crash_shutdown(struct pt_regs *regs) ++void machine_crash_shutdown(struct pt_regs *regs) + { + if (_machine_crash_shutdown) + _machine_crash_shutdown(regs); +@@ -66,10 +166,12 @@ machine_kexec(struct kimage *image) + unsigned long *ptr; + + reboot_code_buffer = +- (unsigned long)page_address(image->control_code_page); ++ (unsigned long)page_address(image->control_code_page); ++ pr_info("reboot_code_buffer = %p\n", (void *)reboot_code_buffer); + + kexec_start_address = + (unsigned long) phys_to_virt(image->start); ++ pr_info("kexec_start_address = %p\n", (void *)kexec_start_address); + + if (image->type == KEXEC_TYPE_DEFAULT) { + kexec_indirection_page = +@@ -77,9 +179,19 @@ machine_kexec(struct kimage *image) + } else { + kexec_indirection_page = (unsigned long)&image->head; + } ++ pr_info("kexec_indirection_page = %p\n", (void *)kexec_indirection_page); + +- memcpy((void*)reboot_code_buffer, relocate_new_kernel, +- relocate_new_kernel_size); ++ pr_info("Where is memcpy: %p\n", memcpy); ++ pr_info("kexec_relocate_new_kernel = %p, kexec_relocate_new_kernel_end = %p\n", ++ (void *)kexec_relocate_new_kernel, &kexec_relocate_new_kernel_end); ++ pr_info("Copy %lu bytes from %p to %p\n", KEXEC_RELOCATE_NEW_KERNEL_SIZE, ++ (void *)kexec_relocate_new_kernel, (void *)reboot_code_buffer); ++ memcpy((void*)reboot_code_buffer, kexec_relocate_new_kernel, ++ KEXEC_RELOCATE_NEW_KERNEL_SIZE); ++ ++ pr_info("Before _print_args().\n"); ++ machine_kexec_print_args(); ++ pr_info("Before eval loop.\n"); + + /* + * The generic kexec code builds a page list with physical +@@ -98,15 +210,16 @@ machine_kexec(struct kimage *image) + /* + * we do not want to be bothered. + */ ++ pr_info("Before irq_disable.\n"); + local_irq_disable(); + +- printk("Will call new kernel at %08lx\n", image->start); +- printk("Bye ...\n"); ++ pr_info("Will call new kernel at %08lx\n", image->start); ++ pr_info("Bye ...\n"); + __flush_cache_all(); + #ifdef CONFIG_SMP + /* All secondary cpus now may jump to kexec_wait cycle */ + relocated_kexec_smp_wait = reboot_code_buffer + +- (void *)(kexec_smp_wait - relocate_new_kernel); ++ (void *)(kexec_smp_wait - kexec_relocate_new_kernel); + smp_wmb(); + atomic_set(&kexec_ready_to_reboot, 1); + #endif +--- /dev/null ++++ b/arch/mips/kernel/machine_kexec.h +@@ -0,0 +1,20 @@ ++#ifndef _MACHINE_KEXEC_H ++#define _MACHINE_KEXEC_H ++ ++#ifndef __ASSEMBLY__ ++extern const unsigned char kexec_relocate_new_kernel[]; ++extern unsigned long kexec_relocate_new_kernel_end; ++extern unsigned long kexec_start_address; ++extern unsigned long kexec_indirection_page; ++ ++extern char kexec_argv_buf[]; ++extern char *kexec_argv[]; ++ ++#define KEXEC_RELOCATE_NEW_KERNEL_SIZE ((unsigned long)&kexec_relocate_new_kernel_end - (unsigned long)kexec_relocate_new_kernel) ++#endif /* !__ASSEMBLY__ */ ++ ++#define KEXEC_COMMAND_LINE_SIZE 256 ++#define KEXEC_ARGV_SIZE (KEXEC_COMMAND_LINE_SIZE / 16) ++#define KEXEC_MAX_ARGC (KEXEC_ARGV_SIZE / sizeof(long)) ++ ++#endif +--- a/arch/mips/kernel/relocate_kernel.S ++++ b/arch/mips/kernel/relocate_kernel.S +@@ -12,8 +12,9 @@ + #include + #include + #include ++#include "machine_kexec.h" + +-LEAF(relocate_new_kernel) ++LEAF(kexec_relocate_new_kernel) + PTR_L a0, arg0 + PTR_L a1, arg1 + PTR_L a2, arg2 +@@ -98,7 +99,7 @@ done: + #endif + /* jump to kexec_start_address */ + j s1 +- END(relocate_new_kernel) ++ END(kexec_relocate_new_kernel) + + #ifdef CONFIG_SMP + /* +@@ -184,9 +185,15 @@ kexec_indirection_page: + PTR 0 + .size kexec_indirection_page, PTRSIZE + +-relocate_new_kernel_end: ++kexec_argv_buf: ++ EXPORT(kexec_argv_buf) ++ .skip KEXEC_COMMAND_LINE_SIZE ++ .size kexec_argv_buf, KEXEC_COMMAND_LINE_SIZE ++ ++kexec_argv: ++ EXPORT(kexec_argv) ++ .skip KEXEC_ARGV_SIZE ++ .size kexec_argv, KEXEC_ARGV_SIZE + +-relocate_new_kernel_size: +- EXPORT(relocate_new_kernel_size) +- PTR relocate_new_kernel_end - relocate_new_kernel +- .size relocate_new_kernel_size, PTRSIZE ++kexec_relocate_new_kernel_end: ++ EXPORT(kexec_relocate_new_kernel_end) diff --git a/target/linux/generic/patches-4.0/400-mtd-add-rootfs-split-support.patch b/target/linux/generic/patches-4.0/400-mtd-add-rootfs-split-support.patch new file mode 100644 index 0000000..6cb31dc --- /dev/null +++ b/target/linux/generic/patches-4.0/400-mtd-add-rootfs-split-support.patch @@ -0,0 +1,171 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -12,6 +12,23 @@ menuconfig MTD + + if MTD + ++menu "OpenWrt specific MTD options" ++ ++config MTD_ROOTFS_ROOT_DEV ++ bool "Automatically set 'rootfs' partition to be root filesystem" ++ default y ++ ++config MTD_SPLIT_FIRMWARE ++ bool "Automatically split firmware partition for kernel+rootfs" ++ default y ++ ++config MTD_SPLIT_FIRMWARE_NAME ++ string "Firmware partition name" ++ depends on MTD_SPLIT_FIRMWARE ++ default "firmware" ++ ++endmenu ++ + config MTD_TESTS + tristate "MTD tests support (DANGEROUS)" + depends on m +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -29,9 +29,11 @@ + #include + #include + #include ++#include + #include + + #include "mtdcore.h" ++#include "mtdsplit/mtdsplit.h" + + /* Our partition linked list */ + static LIST_HEAD(mtd_partitions); +@@ -45,13 +47,14 @@ struct mtd_part { + struct list_head list; + }; + ++static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part); ++ + /* + * Given a pointer to the MTD object in the mtd_part structure, we can retrieve + * the pointer to that structure with this macro. + */ + #define PART(x) ((struct mtd_part *)(x)) + +- + /* + * MTD methods which simply translate the effective address and pass through + * to the _real_ device. +@@ -546,8 +549,10 @@ out_register: + return slave; + } + +-int mtd_add_partition(struct mtd_info *master, const char *name, +- long long offset, long long length) ++ ++static int ++__mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length, bool dup_check) + { + struct mtd_partition part; + struct mtd_part *p, *new; +@@ -579,21 +584,24 @@ int mtd_add_partition(struct mtd_info *m + end = offset + length; + + mutex_lock(&mtd_partitions_mutex); +- list_for_each_entry(p, &mtd_partitions, list) +- if (p->master == master) { +- if ((start >= p->offset) && +- (start < (p->offset + p->mtd.size))) +- goto err_inv; +- +- if ((end >= p->offset) && +- (end < (p->offset + p->mtd.size))) +- goto err_inv; +- } ++ if (dup_check) { ++ list_for_each_entry(p, &mtd_partitions, list) ++ if (p->master == master) { ++ if ((start >= p->offset) && ++ (start < (p->offset + p->mtd.size))) ++ goto err_inv; ++ ++ if ((end >= p->offset) && ++ (end < (p->offset + p->mtd.size))) ++ goto err_inv; ++ } ++ } + + list_add(&new->list, &mtd_partitions); + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&new->mtd); ++ mtd_partition_split(master, new); + + return ret; + err_inv: +@@ -603,6 +611,12 @@ err_inv: + } + EXPORT_SYMBOL_GPL(mtd_add_partition); + ++int mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length) ++{ ++ return __mtd_add_partition(master, name, offset, length, true); ++} ++ + int mtd_del_partition(struct mtd_info *master, int partno) + { + struct mtd_part *slave, *next; +@@ -626,6 +640,35 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME ++#define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME ++#else ++#define SPLIT_FIRMWARE_NAME "unused" ++#endif ++ ++static void split_firmware(struct mtd_info *master, struct mtd_part *part) ++{ ++} ++ ++void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++} ++ ++static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part) ++{ ++ static int rootfs_found = 0; ++ ++ if (rootfs_found) ++ return; ++ ++ if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && ++ config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) ++ split_firmware(master, part); ++ ++ arch_split_mtd_part(master, part->mtd.name, part->offset, ++ part->mtd.size); ++} + /* + * This function, given a master MTD object and a partition table, creates + * and registers slave MTD objects which are bound to the master according to +@@ -655,6 +698,7 @@ int add_mtd_partitions(struct mtd_info * + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&slave->mtd); ++ mtd_partition_split(master, slave); + + cur_offset = slave->offset + slave->mtd.size; + } +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -84,5 +84,7 @@ int mtd_add_partition(struct mtd_info *m + long long offset, long long length); + int mtd_del_partition(struct mtd_info *master, int partno); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); ++extern void __weak arch_split_mtd_part(struct mtd_info *master, ++ const char *name, int offset, int size); + + #endif diff --git a/target/linux/generic/patches-4.0/401-mtd-add-support-for-different-partition-parser-types.patch b/target/linux/generic/patches-4.0/401-mtd-add-support-for-different-partition-parser-types.patch new file mode 100644 index 0000000..7f28a25 --- /dev/null +++ b/target/linux/generic/patches-4.0/401-mtd-add-support-for-different-partition-parser-types.patch @@ -0,0 +1,113 @@ +From 02cff0ccaa6d364f5c1eeea83f47ac80ccc967d4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 3 Sep 2013 18:11:50 +0200 +Subject: [PATCH] mtd: add support for different partition parser types + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/mtdpart.c | 56 ++++++++++++++++++++++++++++++++++++++++ + include/linux/mtd/partitions.h | 11 ++++++++ + 2 files changed, 67 insertions(+) + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -728,6 +728,30 @@ static struct mtd_part_parser *get_parti + + #define put_partition_parser(p) do { module_put((p)->owner); } while (0) + ++static struct mtd_part_parser * ++get_partition_parser_by_type(enum mtd_parser_type type, ++ struct mtd_part_parser *start) ++{ ++ struct mtd_part_parser *p, *ret = NULL; ++ ++ spin_lock(&part_parser_lock); ++ ++ p = list_prepare_entry(start, &part_parsers, list); ++ if (start) ++ put_partition_parser(start); ++ ++ list_for_each_entry_continue(p, &part_parsers, list) { ++ if (p->type == type && try_module_get(p->owner)) { ++ ret = p; ++ break; ++ } ++ } ++ ++ spin_unlock(&part_parser_lock); ++ ++ return ret; ++} ++ + void register_mtd_parser(struct mtd_part_parser *p) + { + spin_lock(&part_parser_lock); +@@ -801,6 +825,38 @@ int parse_mtd_partitions(struct mtd_info + return ret; + } + ++int parse_mtd_partitions_by_type(struct mtd_info *master, ++ enum mtd_parser_type type, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct mtd_part_parser *prev = NULL; ++ int ret = 0; ++ ++ while (1) { ++ struct mtd_part_parser *parser; ++ ++ parser = get_partition_parser_by_type(type, prev); ++ if (!parser) ++ break; ++ ++ ret = (*parser->parse_fn)(master, pparts, data); ++ ++ if (ret > 0) { ++ put_partition_parser(parser); ++ printk(KERN_NOTICE ++ "%d %s partitions found on MTD device %s\n", ++ ret, parser->name, master->name); ++ break; ++ } ++ ++ prev = parser; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(parse_mtd_partitions_by_type); ++ + int mtd_is_partition(const struct mtd_info *mtd) + { + struct mtd_part *part; +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -68,12 +68,17 @@ struct mtd_part_parser_data { + * Functions dealing with the various ways of partitioning the space + */ + ++enum mtd_parser_type { ++ MTD_PARSER_TYPE_DEVICE = 0, ++}; ++ + struct mtd_part_parser { + struct list_head list; + struct module *owner; + const char *name; + int (*parse_fn)(struct mtd_info *, struct mtd_partition **, + struct mtd_part_parser_data *); ++ enum mtd_parser_type type; + }; + + extern void register_mtd_parser(struct mtd_part_parser *parser); +@@ -87,4 +92,9 @@ uint64_t mtd_get_device_size(const struc + extern void __weak arch_split_mtd_part(struct mtd_info *master, + const char *name, int offset, int size); + ++int parse_mtd_partitions_by_type(struct mtd_info *master, ++ enum mtd_parser_type type, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data); ++ + #endif diff --git a/target/linux/generic/patches-4.0/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch b/target/linux/generic/patches-4.0/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch new file mode 100644 index 0000000..ea881e1 --- /dev/null +++ b/target/linux/generic/patches-4.0/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch @@ -0,0 +1,72 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -640,6 +640,37 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++static int ++run_parsers_by_type(struct mtd_part *slave, enum mtd_parser_type type) ++{ ++ struct mtd_partition *parts; ++ int nr_parts; ++ int i; ++ ++ nr_parts = parse_mtd_partitions_by_type(&slave->mtd, type, &parts, ++ NULL); ++ if (nr_parts <= 0) ++ return nr_parts; ++ ++ if (WARN_ON(!parts)) ++ return 0; ++ ++ for (i = 0; i < nr_parts; i++) { ++ /* adjust partition offsets */ ++ parts[i].offset += slave->offset; ++ ++ __mtd_add_partition(slave->master, ++ parts[i].name, ++ parts[i].offset, ++ parts[i].size, ++ false); ++ } ++ ++ kfree(parts); ++ ++ return nr_parts; ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -648,6 +679,7 @@ EXPORT_SYMBOL_GPL(mtd_del_partition); + + static void split_firmware(struct mtd_info *master, struct mtd_part *part) + { ++ run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); + } + + void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, +@@ -662,6 +694,12 @@ static void mtd_partition_split(struct m + if (rootfs_found) + return; + ++ if (!strcmp(part->mtd.name, "rootfs")) { ++ run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); ++ ++ rootfs_found = 1; ++ } ++ + if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && + config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) + split_firmware(master, part); +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -70,6 +70,8 @@ struct mtd_part_parser_data { + + enum mtd_parser_type { + MTD_PARSER_TYPE_DEVICE = 0, ++ MTD_PARSER_TYPE_ROOTFS, ++ MTD_PARSER_TYPE_FIRMWARE, + }; + + struct mtd_part_parser { diff --git a/target/linux/generic/patches-4.0/403-mtd-hook-mtdsplit-to-Kbuild.patch b/target/linux/generic/patches-4.0/403-mtd-hook-mtdsplit-to-Kbuild.patch new file mode 100644 index 0000000..0cf1c38 --- /dev/null +++ b/target/linux/generic/patches-4.0/403-mtd-hook-mtdsplit-to-Kbuild.patch @@ -0,0 +1,22 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -27,6 +27,8 @@ config MTD_SPLIT_FIRMWARE_NAME + depends on MTD_SPLIT_FIRMWARE + default "firmware" + ++source "drivers/mtd/mtdsplit/Kconfig" ++ + endmenu + + config MTD_TESTS +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -6,6 +6,8 @@ + obj-$(CONFIG_MTD) += mtd.o + mtd-y := mtdcore.o mtdsuper.o mtdconcat.o mtdpart.o mtdchar.o + ++obj-$(CONFIG_MTD_SPLIT) += mtdsplit/ ++ + obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o diff --git a/target/linux/generic/patches-4.0/404-mtd-add-more-helper-functions.patch b/target/linux/generic/patches-4.0/404-mtd-add-more-helper-functions.patch new file mode 100644 index 0000000..3220391 --- /dev/null +++ b/target/linux/generic/patches-4.0/404-mtd-add-more-helper-functions.patch @@ -0,0 +1,101 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -444,14 +444,12 @@ static struct mtd_part *allocate_partiti + if (slave->offset == MTDPART_OFS_APPEND) + slave->offset = cur_offset; + if (slave->offset == MTDPART_OFS_NXTBLK) { +- slave->offset = cur_offset; +- if (mtd_mod_by_eb(cur_offset, master) != 0) { +- /* Round up to next erasesize */ +- slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize; ++ /* Round up to next erasesize */ ++ slave->offset = mtd_roundup_to_eb(cur_offset, master); ++ if (slave->offset != cur_offset) + printk(KERN_NOTICE "Moving partition %d: " + "0x%012llx -> 0x%012llx\n", partno, + (unsigned long long)cur_offset, (unsigned long long)slave->offset); +- } + } + if (slave->offset == MTDPART_OFS_RETAIN) { + slave->offset = cur_offset; +@@ -671,6 +669,17 @@ run_parsers_by_type(struct mtd_part *sla + return nr_parts; + } + ++static inline unsigned long ++mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len) ++{ ++ unsigned long mask = mtd->erasesize - 1; ++ ++ len += offset & mask; ++ len = (len + mask) & ~mask; ++ len -= offset & mask; ++ return len; ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -912,6 +921,24 @@ int mtd_is_partition(const struct mtd_in + } + EXPORT_SYMBOL_GPL(mtd_is_partition); + ++struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd) ++{ ++ if (!mtd_is_partition(mtd)) ++ return (struct mtd_info *)mtd; ++ ++ return PART(mtd)->master; ++} ++EXPORT_SYMBOL_GPL(mtdpart_get_master); ++ ++uint64_t mtdpart_get_offset(const struct mtd_info *mtd) ++{ ++ if (!mtd_is_partition(mtd)) ++ return 0; ++ ++ return PART(mtd)->offset; ++} ++EXPORT_SYMBOL_GPL(mtdpart_get_offset); ++ + /* Returns the size of the entire flash chip */ + uint64_t mtd_get_device_size(const struct mtd_info *mtd) + { +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -90,6 +90,8 @@ int mtd_is_partition(const struct mtd_in + int mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length); + int mtd_del_partition(struct mtd_info *master, int partno); ++struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd); ++uint64_t mtdpart_get_offset(const struct mtd_info *mtd); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); + extern void __weak arch_split_mtd_part(struct mtd_info *master, + const char *name, int offset, int size); +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -334,6 +334,24 @@ static inline uint32_t mtd_mod_by_eb(uin + return do_div(sz, mtd->erasesize); + } + ++static inline uint64_t mtd_roundup_to_eb(uint64_t sz, struct mtd_info *mtd) ++{ ++ if (mtd_mod_by_eb(sz, mtd) == 0) ++ return sz; ++ ++ /* Round up to next erase block */ ++ return (mtd_div_by_eb(sz, mtd) + 1) * mtd->erasesize; ++} ++ ++static inline uint64_t mtd_rounddown_to_eb(uint64_t sz, struct mtd_info *mtd) ++{ ++ if (mtd_mod_by_eb(sz, mtd) == 0) ++ return sz; ++ ++ /* Round down to the start of the current erase block */ ++ return (mtd_div_by_eb(sz, mtd)) * mtd->erasesize; ++} ++ + static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd) + { + if (mtd->writesize_shift) diff --git a/target/linux/generic/patches-4.0/405-mtd-old-firmware-uimage-splitter.patch b/target/linux/generic/patches-4.0/405-mtd-old-firmware-uimage-splitter.patch new file mode 100644 index 0000000..fa2fdc0 --- /dev/null +++ b/target/linux/generic/patches-4.0/405-mtd-old-firmware-uimage-splitter.patch @@ -0,0 +1,70 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -27,6 +27,11 @@ config MTD_SPLIT_FIRMWARE_NAME + depends on MTD_SPLIT_FIRMWARE + default "firmware" + ++config MTD_UIMAGE_SPLIT ++ bool "Enable split support for firmware partitions containing a uImage" ++ depends on MTD_SPLIT_FIRMWARE ++ default y ++ + source "drivers/mtd/mtdsplit/Kconfig" + + endmenu +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -680,6 +680,37 @@ mtd_pad_erasesize(struct mtd_info *mtd, + return len; + } + ++#define UBOOT_MAGIC 0x27051956 ++ ++static void split_uimage(struct mtd_info *master, struct mtd_part *part) ++{ ++ struct { ++ __be32 magic; ++ __be32 pad[2]; ++ __be32 size; ++ } hdr; ++ size_t len; ++ ++ if (mtd_read(master, part->offset, sizeof(hdr), &len, (void *) &hdr)) ++ return; ++ ++ if (len != sizeof(hdr) || hdr.magic != cpu_to_be32(UBOOT_MAGIC)) ++ return; ++ ++ len = be32_to_cpu(hdr.size) + 0x40; ++ len = mtd_pad_erasesize(master, part->offset, len); ++ if (len + master->erasesize > part->mtd.size) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_SPLIT_UIMAGE_FW)) ++ pr_err("Dedicated partitioner didn't split firmware partition, please fill a bug report!\n"); ++ else ++ pr_warn("Support for built-in firmware splitter will be removed, please use CONFIG_MTD_SPLIT_UIMAGE_FW\n"); ++ ++ __mtd_add_partition(master, "rootfs", part->offset + len, ++ part->mtd.size - len, false); ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -688,7 +719,14 @@ mtd_pad_erasesize(struct mtd_info *mtd, + + static void split_firmware(struct mtd_info *master, struct mtd_part *part) + { +- run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); ++ int ret; ++ ++ ret = run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); ++ if (ret > 0) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_UIMAGE_SPLIT)) ++ split_uimage(master, part); + } + + void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, diff --git a/target/linux/generic/patches-4.0/406-mtd-old-rootfs-squashfs-splitter.patch b/target/linux/generic/patches-4.0/406-mtd-old-rootfs-squashfs-splitter.patch new file mode 100644 index 0000000..3e72cd4 --- /dev/null +++ b/target/linux/generic/patches-4.0/406-mtd-old-rootfs-squashfs-splitter.patch @@ -0,0 +1,76 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -18,6 +18,11 @@ config MTD_ROOTFS_ROOT_DEV + bool "Automatically set 'rootfs' partition to be root filesystem" + default y + ++config MTD_ROOTFS_SPLIT ++ bool "Automatically split 'rootfs' partition for squashfs" ++ select MTD_SPLIT ++ default y ++ + config MTD_SPLIT_FIRMWARE + bool "Automatically split firmware partition for kernel+rootfs" + default y +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -680,6 +680,47 @@ mtd_pad_erasesize(struct mtd_info *mtd, + return len; + } + ++static int split_squashfs(struct mtd_info *master, int offset, int *split_offset) ++{ ++ size_t squashfs_len; ++ int len, ret; ++ ++ ret = mtd_get_squashfs_len(master, offset, &squashfs_len); ++ if (ret) ++ return ret; ++ ++ len = mtd_pad_erasesize(master, offset, squashfs_len); ++ *split_offset = offset + len; ++ ++ return 0; ++} ++ ++static void split_rootfs_data(struct mtd_info *master, struct mtd_part *part) ++{ ++ unsigned int split_offset = 0; ++ unsigned int split_size; ++ int ret; ++ ++ ret = split_squashfs(master, part->offset, &split_offset); ++ if (ret) ++ return; ++ ++ if (split_offset <= 0) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_SPLIT_SQUASHFS_ROOT)) ++ pr_err("Dedicated partitioner didn't create \"rootfs_data\" partition, please fill a bug report!\n"); ++ else ++ pr_warn("Support for built-in \"rootfs_data\" splitter will be removed, please use CONFIG_MTD_SPLIT_SQUASHFS_ROOT\n"); ++ ++ split_size = part->mtd.size - (split_offset - part->offset); ++ printk(KERN_INFO "mtd: partition \"%s\" created automatically, ofs=0x%x, len=0x%x\n", ++ ROOTFS_SPLIT_NAME, split_offset, split_size); ++ ++ __mtd_add_partition(master, ROOTFS_SPLIT_NAME, split_offset, ++ split_size, false); ++} ++ + #define UBOOT_MAGIC 0x27051956 + + static void split_uimage(struct mtd_info *master, struct mtd_part *part) +@@ -742,7 +783,10 @@ static void mtd_partition_split(struct m + return; + + if (!strcmp(part->mtd.name, "rootfs")) { +- run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); ++ int num = run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); ++ ++ if (num <= 0 && config_enabled(CONFIG_MTD_ROOTFS_SPLIT)) ++ split_rootfs_data(master, part); + + rootfs_found = 1; + } diff --git a/target/linux/generic/patches-4.0/410-mtd-move-forward-declaration-of-struct-mtd_info.patch b/target/linux/generic/patches-4.0/410-mtd-move-forward-declaration-of-struct-mtd_info.patch new file mode 100644 index 0000000..78ebbf8 --- /dev/null +++ b/target/linux/generic/patches-4.0/410-mtd-move-forward-declaration-of-struct-mtd_info.patch @@ -0,0 +1,18 @@ +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -35,6 +35,7 @@ + * Note: writeable partitions require their size and offset be + * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK). + */ ++struct mtd_info; + + struct mtd_partition { + const char *name; /* identifier string */ +@@ -50,7 +51,6 @@ struct mtd_partition { + #define MTDPART_SIZ_FULL (0) + + +-struct mtd_info; + struct device_node; + + /** diff --git a/target/linux/generic/patches-4.0/411-mtd-partial_eraseblock_write.patch b/target/linux/generic/patches-4.0/411-mtd-partial_eraseblock_write.patch new file mode 100644 index 0000000..ada7cc1 --- /dev/null +++ b/target/linux/generic/patches-4.0/411-mtd-partial_eraseblock_write.patch @@ -0,0 +1,142 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -35,6 +35,8 @@ + #include "mtdcore.h" + #include "mtdsplit/mtdsplit.h" + ++#define MTD_ERASE_PARTIAL 0x8000 /* partition only covers parts of an erase block */ ++ + /* Our partition linked list */ + static LIST_HEAD(mtd_partitions); + static DEFINE_MUTEX(mtd_partitions_mutex); +@@ -233,13 +235,61 @@ static int part_erase(struct mtd_info *m + struct mtd_part *part = PART(mtd); + int ret; + ++ ++ instr->partial_start = false; ++ if (mtd->flags & MTD_ERASE_PARTIAL) { ++ size_t readlen = 0; ++ u64 mtd_ofs; ++ ++ instr->erase_buf = kmalloc(part->master->erasesize, GFP_ATOMIC); ++ if (!instr->erase_buf) ++ return -ENOMEM; ++ ++ mtd_ofs = part->offset + instr->addr; ++ instr->erase_buf_ofs = do_div(mtd_ofs, part->master->erasesize); ++ ++ if (instr->erase_buf_ofs > 0) { ++ instr->addr -= instr->erase_buf_ofs; ++ ret = mtd_read(part->master, ++ instr->addr + part->offset, ++ part->master->erasesize, ++ &readlen, instr->erase_buf); ++ ++ instr->len += instr->erase_buf_ofs; ++ instr->partial_start = true; ++ } else { ++ mtd_ofs = part->offset + part->mtd.size; ++ instr->erase_buf_ofs = part->master->erasesize - ++ do_div(mtd_ofs, part->master->erasesize); ++ ++ if (instr->erase_buf_ofs > 0) { ++ instr->len += instr->erase_buf_ofs; ++ ret = mtd_read(part->master, ++ part->offset + instr->addr + ++ instr->len - part->master->erasesize, ++ part->master->erasesize, &readlen, ++ instr->erase_buf); ++ } else { ++ ret = 0; ++ } ++ } ++ if (ret < 0) { ++ kfree(instr->erase_buf); ++ return ret; ++ } ++ ++ } ++ + instr->addr += part->offset; + ret = part->master->_erase(part->master, instr); + if (ret) { + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; ++ if (mtd->flags & MTD_ERASE_PARTIAL) ++ kfree(instr->erase_buf); + } ++ + return ret; + } + +@@ -247,7 +297,25 @@ void mtd_erase_callback(struct erase_inf + { + if (instr->mtd->_erase == part_erase) { + struct mtd_part *part = PART(instr->mtd); ++ size_t wrlen = 0; + ++ if (instr->mtd->flags & MTD_ERASE_PARTIAL) { ++ if (instr->partial_start) { ++ part->master->_write(part->master, ++ instr->addr, instr->erase_buf_ofs, ++ &wrlen, instr->erase_buf); ++ instr->addr += instr->erase_buf_ofs; ++ } else { ++ instr->len -= instr->erase_buf_ofs; ++ part->master->_write(part->master, ++ instr->addr + instr->len, ++ instr->erase_buf_ofs, &wrlen, ++ instr->erase_buf + ++ part->master->erasesize - ++ instr->erase_buf_ofs); ++ } ++ kfree(instr->erase_buf); ++ } + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; +@@ -513,17 +581,20 @@ static struct mtd_part *allocate_partiti + if ((slave->mtd.flags & MTD_WRITEABLE) && + mtd_mod_by_eb(slave->offset, &slave->mtd)) { + /* Doesn't start on a boundary of major erase size */ +- /* FIXME: Let it be writable if it is on a boundary of +- * _minor_ erase size though */ +- slave->mtd.flags &= ~MTD_WRITEABLE; +- printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase block boundary -- force read-only\n", +- part->name); ++ slave->mtd.flags |= MTD_ERASE_PARTIAL; ++ if (((u32) slave->mtd.size) > master->erasesize) ++ slave->mtd.flags &= ~MTD_WRITEABLE; ++ else ++ slave->mtd.erasesize = slave->mtd.size; + } + if ((slave->mtd.flags & MTD_WRITEABLE) && +- mtd_mod_by_eb(slave->mtd.size, &slave->mtd)) { +- slave->mtd.flags &= ~MTD_WRITEABLE; +- printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase block -- force read-only\n", +- part->name); ++ mtd_mod_by_eb(slave->offset + slave->mtd.size, &slave->mtd)) { ++ slave->mtd.flags |= MTD_ERASE_PARTIAL; ++ ++ if ((u32) slave->mtd.size > master->erasesize) ++ slave->mtd.flags &= ~MTD_WRITEABLE; ++ else ++ slave->mtd.erasesize = slave->mtd.size; + } + + slave->mtd.ecclayout = master->ecclayout; +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -55,6 +55,10 @@ struct erase_info { + u_long priv; + u_char state; + struct erase_info *next; ++ ++ u8 *erase_buf; ++ u32 erase_buf_ofs; ++ bool partial_start; + }; + + struct mtd_erase_region_info { diff --git a/target/linux/generic/patches-4.0/412-mtd-partial_eraseblock_unlock.patch b/target/linux/generic/patches-4.0/412-mtd-partial_eraseblock_unlock.patch new file mode 100644 index 0000000..ba45acc --- /dev/null +++ b/target/linux/generic/patches-4.0/412-mtd-partial_eraseblock_unlock.patch @@ -0,0 +1,18 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -334,7 +334,14 @@ static int part_lock(struct mtd_info *mt + static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) + { + struct mtd_part *part = PART(mtd); +- return part->master->_unlock(part->master, ofs + part->offset, len); ++ ++ ofs += part->offset; ++ if (mtd->flags & MTD_ERASE_PARTIAL) { ++ /* round up len to next erasesize and round down offset to prev block */ ++ len = (mtd_div_by_eb(len, part->master) + 1) * part->master->erasesize; ++ ofs &= ~(part->master->erasesize - 1); ++ } ++ return part->master->_unlock(part->master, ofs, len); + } + + static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) diff --git a/target/linux/generic/patches-4.0/420-mtd-redboot_space.patch b/target/linux/generic/patches-4.0/420-mtd-redboot_space.patch new file mode 100644 index 0000000..f74affc --- /dev/null +++ b/target/linux/generic/patches-4.0/420-mtd-redboot_space.patch @@ -0,0 +1,30 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -265,14 +265,21 @@ static int parse_redboot_partitions(stru + #endif + names += strlen(names)+1; + +-#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + if(fl->next && fl->img->flash_base + fl->img->size + master->erasesize <= fl->next->img->flash_base) { +- i++; +- parts[i].offset = parts[i-1].size + parts[i-1].offset; +- parts[i].size = fl->next->img->flash_base - parts[i].offset; +- parts[i].name = nullname; +- } ++ if (!strcmp(parts[i].name, "rootfs")) { ++ parts[i].size = fl->next->img->flash_base; ++ parts[i].size &= ~(master->erasesize - 1); ++ parts[i].size -= parts[i].offset; ++#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED ++ nrparts--; ++ } else { ++ i++; ++ parts[i].offset = parts[i-1].size + parts[i-1].offset; ++ parts[i].size = fl->next->img->flash_base - parts[i].offset; ++ parts[i].name = nullname; + #endif ++ } ++ } + tmp_fl = fl; + fl = fl->next; + kfree(tmp_fl); diff --git a/target/linux/generic/patches-4.0/430-mtd-add-myloader-partition-parser.patch b/target/linux/generic/patches-4.0/430-mtd-add-myloader-partition-parser.patch new file mode 100644 index 0000000..25e0ecd --- /dev/null +++ b/target/linux/generic/patches-4.0/430-mtd-add-myloader-partition-parser.patch @@ -0,0 +1,35 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -184,6 +184,22 @@ config MTD_BCM47XX_PARTS + This provides partitions parser for devices based on BCM47xx + boards. + ++config MTD_MYLOADER_PARTS ++ tristate "MyLoader partition parsing" ++ depends on ADM5120 || ATH25 || ATH79 ++ ---help--- ++ MyLoader is a bootloader which allows the user to define partitions ++ in flash devices, by putting a table in the second erase block ++ on the device, similar to a partition table. This table gives the ++ offsets and lengths of the user defined partitions. ++ ++ If you need code which can detect and parse these tables, and ++ register MTD 'partitions' corresponding to each image detected, ++ enable this option. ++ ++ You will still need the parsing functions to be called by the driver ++ for your particular device. It won't happen automatically. ++ + comment "User Modules And Translation Layers" + + # +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o ++obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/generic/patches-4.0/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch b/target/linux/generic/patches-4.0/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch new file mode 100644 index 0000000..a30e698 --- /dev/null +++ b/target/linux/generic/patches-4.0/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch @@ -0,0 +1,34 @@ +From 841e59ba3e496d86ca5f069204d5e5c1ad43c01d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 27 Jan 2015 22:29:21 +0100 +Subject: [PATCH] mtd: bcm47xxpart: support for Xiaomi specific board_data + partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/bcm47xxpart.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -33,6 +33,7 @@ + /* Magics */ + #define BOARD_DATA_MAGIC 0x5246504D /* MPFR */ + #define BOARD_DATA_MAGIC2 0xBD0D0BBD ++#define BOARD_DATA_XIAOMI_MAGIC 0x474D4442 /* GMDB */ + #define CFE_MAGIC 0x43464531 /* 1EFC */ + #define FACTORY_MAGIC 0x59544346 /* FCTY */ + #define NVRAM_HEADER 0x48534C46 /* FLSH */ +@@ -262,7 +263,8 @@ static int bcm47xxpart_parse(struct mtd_ + } + + /* Some devices (ex. WNDR3700v3) don't have a standard 'MPFR' */ +- if (buf[0x000 / 4] == BOARD_DATA_MAGIC2) { ++ if (buf[0x000 / 4] == BOARD_DATA_MAGIC2 || ++ le32_to_cpu(buf[0x000 / 4]) == BOARD_DATA_XIAOMI_MAGIC) { + bcm47xxpart_add_part(&parts[curr_part++], "board_data", + offset, MTD_WRITEABLE); + continue; diff --git a/target/linux/generic/patches-4.0/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch b/target/linux/generic/patches-4.0/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch new file mode 100644 index 0000000..1edc995 --- /dev/null +++ b/target/linux/generic/patches-4.0/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch @@ -0,0 +1,42 @@ +From fd54aa583296f9adfb1f519affbc10ba521eb809 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 28 Jan 2015 22:14:41 +0100 +Subject: [PATCH] mtd: bcm47xxpart: detect T_Meter partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It can be found on many Netgear devices. It consists of many 0x30 blocks +starting with 4D 54. + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/bcm47xxpart.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -39,6 +39,7 @@ + #define NVRAM_HEADER 0x48534C46 /* FLSH */ + #define POT_MAGIC1 0x54544f50 /* POTT */ + #define POT_MAGIC2 0x504f /* OP */ ++#define T_METER_MAGIC 0x4D540000 /* MT */ + #define ML_MAGIC1 0x39685a42 + #define ML_MAGIC2 0x26594131 + #define TRX_MAGIC 0x30524448 +@@ -176,6 +177,15 @@ static int bcm47xxpart_parse(struct mtd_ + MTD_WRITEABLE); + continue; + } ++ ++ /* T_Meter */ ++ if ((le32_to_cpu(buf[0x000 / 4]) & 0xFFFF0000) == T_METER_MAGIC && ++ (le32_to_cpu(buf[0x030 / 4]) & 0xFFFF0000) == T_METER_MAGIC && ++ (le32_to_cpu(buf[0x060 / 4]) & 0xFFFF0000) == T_METER_MAGIC) { ++ bcm47xxpart_add_part(&parts[curr_part++], "T_Meter", offset, ++ MTD_WRITEABLE); ++ continue; ++ } + + /* TRX */ + if (buf[0x000 / 4] == TRX_MAGIC) { diff --git a/target/linux/generic/patches-4.0/440-block2mtd_init.patch b/target/linux/generic/patches-4.0/440-block2mtd_init.patch new file mode 100644 index 0000000..5ab6026 --- /dev/null +++ b/target/linux/generic/patches-4.0/440-block2mtd_init.patch @@ -0,0 +1,107 @@ +--- a/drivers/mtd/devices/block2mtd.c ++++ b/drivers/mtd/devices/block2mtd.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -209,11 +210,12 @@ static void block2mtd_free_device(struct + } + + +-static struct block2mtd_dev *add_device(char *devname, int erase_size) ++static struct block2mtd_dev *add_device(char *devname, int erase_size, const char *mtdname) + { + const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL; + struct block_device *bdev; + struct block2mtd_dev *dev; ++ struct mtd_partition *part; + char *name; + + if (!devname) +@@ -257,13 +259,16 @@ static struct block2mtd_dev *add_device( + + /* Setup the MTD structure */ + /* make the name contain the block device in */ +- name = kasprintf(GFP_KERNEL, "block2mtd: %s", devname); ++ if (!mtdname) ++ mtdname = devname; ++ name = kmalloc(strlen(mtdname) + 1, GFP_KERNEL); + if (!name) + goto err_destroy_mutex; + ++ strcpy(name, mtdname); + dev->mtd.name = name; + +- dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK; ++ dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK & ~(erase_size - 1); + dev->mtd.erasesize = erase_size; + dev->mtd.writesize = 1; + dev->mtd.writebufsize = PAGE_SIZE; +@@ -276,15 +281,18 @@ static struct block2mtd_dev *add_device( + dev->mtd.priv = dev; + dev->mtd.owner = THIS_MODULE; + +- if (mtd_device_register(&dev->mtd, NULL, 0)) { ++ part = kzalloc(sizeof(struct mtd_partition), GFP_KERNEL); ++ part->name = name; ++ part->offset = 0; ++ part->size = dev->mtd.size; ++ if (mtd_device_register(&dev->mtd, part, 1)) { + /* Device didn't get added, so free the entry */ + goto err_destroy_mutex; + } + list_add(&dev->list, &blkmtd_device_list); + pr_info("mtd%d: [%s] erase_size = %dKiB [%d]\n", + dev->mtd.index, +- dev->mtd.name + strlen("block2mtd: "), +- dev->mtd.erasesize >> 10, dev->mtd.erasesize); ++ mtdname, dev->mtd.erasesize >> 10, dev->mtd.erasesize); + return dev; + + err_destroy_mutex: +@@ -353,9 +361,9 @@ static char block2mtd_paramline[80 + 12] + + static int block2mtd_setup2(const char *val) + { +- char buf[80 + 12]; /* 80 for device, 12 for erase size */ ++ char buf[80 + 12 + 80]; /* 80 for device, 12 for erase size, 80 for name */ + char *str = buf; +- char *token[2]; ++ char *token[3]; + char *name; + size_t erase_size = PAGE_SIZE; + int i, ret; +@@ -368,7 +376,7 @@ static int block2mtd_setup2(const char * + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 2; i++) ++ for (i = 0; i < 3; i++) + token[i] = strsep(&str, ","); + + if (str) { +@@ -394,8 +402,10 @@ static int block2mtd_setup2(const char * + return 0; + } + } ++ if (token[2] && (strlen(token[2]) + 1 > 80)) ++ pr_err("mtd device name too long\n"); + +- add_device(name, erase_size); ++ add_device(name, erase_size, token[2]); + + return 0; + } +@@ -429,7 +439,7 @@ static int block2mtd_setup(const char *v + + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); +-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,]\""); ++MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); + + static int __init block2mtd_init(void) + { diff --git a/target/linux/generic/patches-4.0/441-block2mtd_probe.patch b/target/linux/generic/patches-4.0/441-block2mtd_probe.patch new file mode 100644 index 0000000..6836a48 --- /dev/null +++ b/target/linux/generic/patches-4.0/441-block2mtd_probe.patch @@ -0,0 +1,110 @@ +--- a/drivers/mtd/devices/block2mtd.c ++++ b/drivers/mtd/devices/block2mtd.c +@@ -10,6 +10,7 @@ + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + + #include ++#include + #include + #include + #include +@@ -210,13 +211,16 @@ static void block2mtd_free_device(struct + } + + +-static struct block2mtd_dev *add_device(char *devname, int erase_size, const char *mtdname) ++static struct block2mtd_dev *add_device(char *devname, int erase_size, const char *mtdname, int timeout) + { + const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL; +- struct block_device *bdev; ++ struct block_device *bdev = ERR_PTR(-ENODEV); + struct block2mtd_dev *dev; + struct mtd_partition *part; + char *name; ++#ifndef MODULE ++ int i; ++#endif + + if (!devname) + return NULL; +@@ -227,15 +231,20 @@ static struct block2mtd_dev *add_device( + + /* Get a handle on the device */ + bdev = blkdev_get_by_path(devname, mode, dev); ++ + #ifndef MODULE +- if (IS_ERR(bdev)) { ++ for (i = 0; IS_ERR(bdev) && i <= timeout; i++) { ++ dev_t devt; + +- /* We might not have rootfs mounted at this point. Try +- to resolve the device name by other means. */ ++ if (i) ++ msleep(1000); ++ wait_for_device_probe(); ++ ++ devt = name_to_dev_t(devname); ++ if (!devt) ++ continue; + +- dev_t devt = name_to_dev_t(devname); +- if (devt) +- bdev = blkdev_get_by_dev(devt, mode, dev); ++ bdev = blkdev_get_by_dev(devt, mode, dev); + } + #endif + +@@ -361,11 +370,12 @@ static char block2mtd_paramline[80 + 12] + + static int block2mtd_setup2(const char *val) + { +- char buf[80 + 12 + 80]; /* 80 for device, 12 for erase size, 80 for name */ ++ char buf[80 + 12 + 80 + 8]; /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ + char *str = buf; +- char *token[3]; ++ char *token[4]; + char *name; + size_t erase_size = PAGE_SIZE; ++ unsigned long timeout = 0; + int i, ret; + + if (strnlen(val, sizeof(buf)) >= sizeof(buf)) { +@@ -376,7 +386,7 @@ static int block2mtd_setup2(const char * + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 3; i++) ++ for (i = 0; i < 4; i++) + token[i] = strsep(&str, ","); + + if (str) { +@@ -405,7 +415,10 @@ static int block2mtd_setup2(const char * + if (token[2] && (strlen(token[2]) + 1 > 80)) + pr_err("mtd device name too long\n"); + +- add_device(name, erase_size, token[2]); ++ if (token[3] && kstrtoul(token[3], 0, &timeout)) ++ pr_err("invalid timeout\n"); ++ ++ add_device(name, erase_size, token[2], timeout); + + return 0; + } +@@ -439,7 +452,7 @@ static int block2mtd_setup(const char *v + + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); +-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); ++MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,[,]]]\""); + + static int __init block2mtd_init(void) + { +@@ -474,7 +487,7 @@ static void block2mtd_exit(void) + } + + +-module_init(block2mtd_init); ++late_initcall(block2mtd_init); + module_exit(block2mtd_exit); + + MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.0/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch b/target/linux/generic/patches-4.0/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch new file mode 100644 index 0000000..ffaf706 --- /dev/null +++ b/target/linux/generic/patches-4.0/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch @@ -0,0 +1,37 @@ +--- + drivers/mtd/nand/plat_nand.c | 13 ++++++++++++- + include/linux/mtd/nand.h | 1 + + 2 files changed, 13 insertions(+), 1 deletion(-) + +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -865,6 +865,7 @@ struct platform_nand_chip { + unsigned int options; + unsigned int bbt_options; + const char **part_probe_types; ++ int (*chip_fixup)(struct mtd_info *mtd); + }; + + /* Keep gcc happy */ +--- a/drivers/mtd/nand/plat_nand.c ++++ b/drivers/mtd/nand/plat_nand.c +@@ -90,7 +90,18 @@ static int plat_nand_probe(struct platfo + } + + /* Scan to find existence of the device */ +- if (nand_scan(&data->mtd, pdata->chip.nr_chips)) { ++ if (nand_scan_ident(&data->mtd, pdata->chip.nr_chips, NULL)) { ++ err = -ENXIO; ++ goto out; ++ } ++ ++ if (pdata->chip.chip_fixup) { ++ err = pdata->chip.chip_fixup(&data->mtd); ++ if (err) ++ goto out; ++ } ++ ++ if (nand_scan_tail(&data->mtd)) { + err = -ENXIO; + goto out; + } diff --git a/target/linux/generic/patches-4.0/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch b/target/linux/generic/patches-4.0/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch new file mode 100644 index 0000000..6a2092c --- /dev/null +++ b/target/linux/generic/patches-4.0/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/nand/nand_ecc.c ++++ b/drivers/mtd/nand/nand_ecc.c +@@ -507,7 +507,7 @@ int __nand_correct_data(unsigned char *b + return 1; /* error in ECC data; no action needed */ + + pr_err("%s: uncorrectable ECC error\n", __func__); +- return -1; ++ return -EBADMSG; + } + EXPORT_SYMBOL(__nand_correct_data); + diff --git a/target/linux/generic/patches-4.0/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch b/target/linux/generic/patches-4.0/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch new file mode 100644 index 0000000..68fbd12 --- /dev/null +++ b/target/linux/generic/patches-4.0/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -809,7 +809,7 @@ static int get_chip(struct map_info *map + return 0; + + case FL_ERASING: +- if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || ++ if (1 /* no suspend */ || !cfip || !(cfip->EraseSuspend & (0x1|0x2)) || + !(mode == FL_READY || mode == FL_POINT || + (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) + goto sleep; diff --git a/target/linux/generic/patches-4.0/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch b/target/linux/generic/patches-4.0/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch new file mode 100644 index 0000000..c437a14 --- /dev/null +++ b/target/linux/generic/patches-4.0/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch @@ -0,0 +1,18 @@ +From: George Kashperko + +Issue map read after Write Buffer Load command to ensure chip is ready +to receive data. +Signed-off-by: George Kashperko +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 1 + + 1 file changed, 1 insertion(+) +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1830,6 +1830,7 @@ static int __xipram do_write_buffer(stru + + /* Write Buffer Load */ + map_write(map, CMD(0x25), cmd_adr); ++ (void) map_read(map, cmd_adr); + + chip->state = FL_WRITING_TO_BUFFER; + diff --git a/target/linux/generic/patches-4.0/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch b/target/linux/generic/patches-4.0/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch new file mode 100644 index 0000000..37ecfb9 --- /dev/null +++ b/target/linux/generic/patches-4.0/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch @@ -0,0 +1,20 @@ +From eef9dfc4e821408af1af13aa0cc707fc496fb7c6 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 11 Dec 2013 19:05:59 +0100 +Subject: [PATCH] m25p80: add support for the Winbond W25X05 flash + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/devices/m25p80.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -649,6 +649,7 @@ static const struct spi_device_id spi_no + { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, + + /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ ++ { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, + { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, + { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, + { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, diff --git a/target/linux/generic/patches-4.0/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch b/target/linux/generic/patches-4.0/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch new file mode 100644 index 0000000..81ec0c5 --- /dev/null +++ b/target/linux/generic/patches-4.0/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch @@ -0,0 +1,21 @@ +From 0d7388de0911c1a4fc4a8a3898ef9d0ab818ca08 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 7 Apr 2015 18:35:15 +0200 +Subject: [PATCH] mtd: spi-nor: add support for the Macronix MX25L512E SPI + flash chip + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/spi-nor/spi-nor.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -546,6 +546,7 @@ static const struct spi_device_id spi_no + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, + + /* Macronix */ ++ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, + { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, + { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, diff --git a/target/linux/generic/patches-4.0/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch b/target/linux/generic/patches-4.0/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch new file mode 100644 index 0000000..eb082e0 --- /dev/null +++ b/target/linux/generic/patches-4.0/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch @@ -0,0 +1,22 @@ +From 34e2b403040a2f9d3ba071d95a7f42457e2950f9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 7 Apr 2015 18:35:15 +0200 +Subject: [PATCH] mtd: spi-nor: add support for the ISSI SI25CD512 SPI flash + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/spi-nor/spi-nor.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -545,6 +545,9 @@ static const struct spi_device_id spi_no + { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, + ++ /* ISSI */ ++ { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, ++ + /* Macronix */ + { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, diff --git a/target/linux/generic/patches-4.0/480-mtd-set-rootfs-to-be-root-dev.patch b/target/linux/generic/patches-4.0/480-mtd-set-rootfs-to-be-root-dev.patch new file mode 100644 index 0000000..4b89412 --- /dev/null +++ b/target/linux/generic/patches-4.0/480-mtd-set-rootfs-to-be-root-dev.patch @@ -0,0 +1,26 @@ +--- a/drivers/mtd/mtdcore.c ++++ b/drivers/mtd/mtdcore.c +@@ -38,6 +38,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -447,6 +448,15 @@ int add_mtd_device(struct mtd_info *mtd) + of this try_ nonsense, and no bitching about it + either. :) */ + __module_get(THIS_MODULE); ++ ++ if (!strcmp(mtd->name, "rootfs") && ++ config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ ROOT_DEV == 0) { ++ pr_notice("mtd: device %d (%s) set to be root filesystem\n", ++ mtd->index, mtd->name); ++ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index); ++ } ++ + return 0; + + fail_added: diff --git a/target/linux/generic/patches-4.0/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/patches-4.0/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch new file mode 100644 index 0000000..bb28538 --- /dev/null +++ b/target/linux/generic/patches-4.0/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch @@ -0,0 +1,76 @@ +From 8a52e4100d7c3a4a1dfddfa02b8864a9b0068c13 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 17 May 2014 03:36:18 +0200 +Subject: [PATCH 1/5] ubi: auto-attach mtd device named "ubi" or "data" on boot +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/drivers/mtd/ubi/build.c ++++ b/drivers/mtd/ubi/build.c +@@ -1213,6 +1213,49 @@ static struct mtd_info * __init open_mtd + return mtd; + } + ++/* ++ * This function tries attaching mtd partitions named either "ubi" or "data" ++ * during boot. ++ */ ++static void __init ubi_auto_attach(void) ++{ ++ int err; ++ struct mtd_info *mtd; ++ ++ /* try attaching mtd device named "ubi" or "data" */ ++ mtd = open_mtd_device("ubi"); ++ if (IS_ERR(mtd)) ++ mtd = open_mtd_device("data"); ++ ++ if (!IS_ERR(mtd)) { ++ size_t len; ++ char magic[4]; ++ ++ /* check for a valid ubi magic */ ++ err = mtd_read(mtd, 0, 4, &len, (void *) magic); ++ if (!err && len == 4 && strncmp(magic, "UBI#", 4)) { ++ pr_err("UBI error: no valid UBI magic found inside mtd%d", mtd->index); ++ put_mtd_device(mtd); ++ return; ++ } ++ ++ /* auto-add only media types where UBI makes sense */ ++ if (mtd->type == MTD_NANDFLASH || ++ mtd->type == MTD_NORFLASH || ++ mtd->type == MTD_DATAFLASH || ++ mtd->type == MTD_MLCNANDFLASH) { ++ mutex_lock(&ubi_devices_mutex); ++ pr_notice("UBI: auto-attach mtd%d", mtd->index); ++ err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0); ++ mutex_unlock(&ubi_devices_mutex); ++ if (err < 0) { ++ pr_err("UBI error: cannot attach mtd%d", mtd->index); ++ put_mtd_device(mtd); ++ } ++ } ++ } ++} ++ + static int __init ubi_init(void) + { + int err, i, k; +@@ -1305,6 +1348,12 @@ static int __init ubi_init(void) + } + } + ++ /* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd ++ * parameter was given */ ++ if (config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ !ubi_is_module() && !mtd_devs) ++ ubi_auto_attach(); ++ + err = ubiblock_init(); + if (err) { + pr_err("UBI error: block: cannot initialize, error %d", err); diff --git a/target/linux/generic/patches-4.0/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/patches-4.0/491-ubi-auto-create-ubiblock-device-for-rootfs.patch new file mode 100644 index 0000000..433d77b --- /dev/null +++ b/target/linux/generic/patches-4.0/491-ubi-auto-create-ubiblock-device-for-rootfs.patch @@ -0,0 +1,69 @@ +From 0f3966579815f889bb2fcb4846152c35f65e79c4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 15 May 2014 21:06:33 +0200 +Subject: [PATCH 2/5] ubi: auto-create ubiblock device for rootfs +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/block.c | 42 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -616,6 +616,44 @@ static void __init ubiblock_create_from_ + } + } + ++#define UBIFS_NODE_MAGIC 0x06101831 ++static inline int ubi_vol_is_ubifs(struct ubi_volume_desc *desc) ++{ ++ int ret; ++ uint32_t magic_of, magic; ++ ret = ubi_read(desc, 0, (char *)&magic_of, 0, 4); ++ if (ret) ++ return 0; ++ magic = le32_to_cpu(magic_of); ++ return magic == UBIFS_NODE_MAGIC; ++} ++ ++static void __init ubiblock_create_auto_rootfs(void) ++{ ++ int ubi_num, ret, is_ubifs; ++ struct ubi_volume_desc *desc; ++ struct ubi_volume_info vi; ++ ++ for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) { ++ desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY); ++ if (IS_ERR(desc)) ++ continue; ++ ++ ubi_get_volume_info(desc, &vi); ++ is_ubifs = ubi_vol_is_ubifs(desc); ++ ubi_close_volume(desc); ++ if (is_ubifs) ++ break; ++ ++ ret = ubiblock_create(&vi); ++ if (ret) ++ pr_err("UBI error: block: can't add '%s' volume, err=%d\n", ++ vi.name, ret); ++ /* always break if we get here */ ++ break; ++ } ++} ++ + static void ubiblock_remove_all(void) + { + struct ubiblock *next; +@@ -646,6 +684,10 @@ int __init ubiblock_init(void) + */ + ubiblock_create_from_param(); + ++ /* auto-attach "rootfs" volume if existing and non-ubifs */ ++ if (config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV)) ++ ubiblock_create_auto_rootfs(); ++ + /* + * Block devices are only created upon user requests, so we ignore + * existing volumes. diff --git a/target/linux/generic/patches-4.0/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch b/target/linux/generic/patches-4.0/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch new file mode 100644 index 0000000..406737e --- /dev/null +++ b/target/linux/generic/patches-4.0/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch @@ -0,0 +1,53 @@ +From eea9e1785e4c05c2a3444506aabafa0ae958538f Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 17 May 2014 03:35:02 +0200 +Subject: [PATCH 4/5] try auto-mounting ubi0:rootfs in init/do_mounts.c +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + init/do_mounts.c | 26 +++++++++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +--- a/init/do_mounts.c ++++ b/init/do_mounts.c +@@ -435,7 +435,27 @@ retry: + out: + put_page(page); + } +- ++ ++static int __init mount_ubi_rootfs(void) ++{ ++ int flags = MS_SILENT; ++ int err, tried = 0; ++ ++ while (tried < 2) { ++ err = do_mount_root("ubi0:rootfs", "ubifs", flags, \ ++ root_mount_data); ++ switch (err) { ++ case -EACCES: ++ flags |= MS_RDONLY; ++ tried++; ++ default: ++ return err; ++ } ++ } ++ ++ return -EINVAL; ++} ++ + #ifdef CONFIG_ROOT_NFS + + #define NFSROOT_TIMEOUT_MIN 5 +@@ -529,6 +549,10 @@ void __init mount_root(void) + change_floppy("root floppy"); + } + #endif ++#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV ++ if (!mount_ubi_rootfs()) ++ return; ++#endif + #ifdef CONFIG_BLOCK + create_dev("/dev/root", ROOT_DEV); + mount_block_root("/dev/root", root_mountflags); diff --git a/target/linux/generic/patches-4.0/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/patches-4.0/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch new file mode 100644 index 0000000..1873752 --- /dev/null +++ b/target/linux/generic/patches-4.0/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch @@ -0,0 +1,37 @@ +From cd68d1b12b5ea4c01a664c064179ada42bf55d3d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 15 May 2014 20:55:42 +0200 +Subject: [PATCH 5/5] ubi: set ROOT_DEV to ubiblock "rootfs" if unset +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/block.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -49,6 +49,7 @@ + #include + #include + #include ++#include + + #include "ubi-media.h" + #include "ubi.h" +@@ -439,6 +440,15 @@ int ubiblock_create(struct ubi_volume_in + add_disk(dev->gd); + dev_info(disk_to_dev(dev->gd), "created from ubi%d:%d(%s)", + dev->ubi_num, dev->vol_id, vi->name); ++ ++ if (!strcmp(vi->name, "rootfs") && ++ config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ ROOT_DEV == 0) { ++ pr_notice("ubiblock: device ubiblock%d_%d (%s) set to be root filesystem\n", ++ dev->ubi_num, dev->vol_id, vi->name); ++ ROOT_DEV = MKDEV(gd->major, gd->first_minor); ++ } ++ + return 0; + + out_free_queue: diff --git a/target/linux/generic/patches-4.0/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/patches-4.0/494-mtd-ubi-add-EOF-marker-support.patch new file mode 100644 index 0000000..3763c2f --- /dev/null +++ b/target/linux/generic/patches-4.0/494-mtd-ubi-add-EOF-marker-support.patch @@ -0,0 +1,51 @@ +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -803,6 +803,13 @@ out_unlock: + return err; + } + ++static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech) ++{ ++ return ech->padding1[0] == 'E' && ++ ech->padding1[1] == 'O' && ++ ech->padding1[2] == 'F'; ++} ++ + /** + * scan_peb - scan and process UBI headers of a PEB. + * @ubi: UBI device description object +@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u + return 0; + } + +- err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); +- if (err < 0) +- return err; ++ if (!ai->eof_found) { ++ err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); ++ if (err < 0) ++ return err; ++ ++ if (ec_hdr_has_eof(ech)) { ++ pr_notice("UBI: EOF marker found, PEBs from %d will be erased", ++ pnum); ++ ai->eof_found = true; ++ } ++ } ++ ++ if (ai->eof_found) ++ err = UBI_IO_FF_BITFLIPS; ++ + switch (err) { + case 0: + break; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -706,6 +706,7 @@ struct ubi_attach_info { + int mean_ec; + uint64_t ec_sum; + int ec_count; ++ bool eof_found; + struct kmem_cache *aeb_slab_cache; + }; + diff --git a/target/linux/generic/patches-4.0/500-yaffs-Kbuild-integration.patch b/target/linux/generic/patches-4.0/500-yaffs-Kbuild-integration.patch new file mode 100644 index 0000000..3f5b0cc --- /dev/null +++ b/target/linux/generic/patches-4.0/500-yaffs-Kbuild-integration.patch @@ -0,0 +1,18 @@ +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -32,6 +32,7 @@ source "fs/gfs2/Kconfig" + source "fs/ocfs2/Kconfig" + source "fs/btrfs/Kconfig" + source "fs/nilfs2/Kconfig" ++source "fs/yaffs2/Kconfig" + + config FS_DAX + bool "Direct Access (DAX) support" +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -126,3 +126,5 @@ obj-y += exofs/ # Multiple modules + obj-$(CONFIG_CEPH_FS) += ceph/ + obj-$(CONFIG_PSTORE) += pstore/ + obj-$(CONFIG_EFIVAR_FS) += efivarfs/ ++obj-$(CONFIG_YAFFS_FS) += yaffs2/ ++ diff --git a/target/linux/generic/patches-4.0/502-yaffs-fix-compat-tags-handling.patch b/target/linux/generic/patches-4.0/502-yaffs-fix-compat-tags-handling.patch new file mode 100644 index 0000000..a18cf6f --- /dev/null +++ b/target/linux/generic/patches-4.0/502-yaffs-fix-compat-tags-handling.patch @@ -0,0 +1,239 @@ +Subject: yaffs: fix compat tags handling + +Signed-off-by: Gabor Juhos +--- +--- a/fs/yaffs2/yaffs_tagscompat.c ++++ b/fs/yaffs2/yaffs_tagscompat.c +@@ -17,7 +17,9 @@ + #include "yaffs_getblockinfo.h" + #include "yaffs_trace.h" + ++#if 0 + static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk); ++#endif + + + /********** Tags ECC calculations *********/ +@@ -71,6 +73,7 @@ int yaffs_check_tags_ecc(struct yaffs_ta + return 0; + } + ++#if 0 + /********** Tags **********/ + + static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr, +@@ -379,3 +382,214 @@ void yaffs_tags_compat_install(struct ya + if(!dev->tagger.mark_bad_fn) + dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; + } ++#else ++ ++#include "yaffs_packedtags1.h" ++ ++static int yaffs_tags_compat_write(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *data, ++ const struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags1 pt1; ++ u8 tag_buf[9]; ++ int retval; ++ ++ /* we assume that yaffs_packed_tags1 and yaffs_tags are compatible */ ++ compile_time_assertion(sizeof(struct yaffs_packed_tags1) == 12); ++ compile_time_assertion(sizeof(struct yaffs_tags) == 8); ++ ++ yaffs_pack_tags1(&pt1, tags); ++ yaffs_calc_tags_ecc((struct yaffs_tags *)&pt1); ++ ++ /* When deleting a chunk, the upper layer provides only skeletal ++ * tags, one with is_deleted set. However, we need to update the ++ * tags, not erase them completely. So we use the NAND write property ++ * that only zeroed-bits stick and set tag bytes to all-ones and ++ * zero just the (not) deleted bit. ++ */ ++ if (!dev->param.tags_9bytes) { ++ if (tags->is_deleted) { ++ memset(&pt1, 0xff, 8); ++ /* clear delete status bit to indicate deleted */ ++ pt1.deleted = 0; ++ } ++ memcpy(tag_buf, &pt1, 8); ++ } else { ++ if (tags->is_deleted) { ++ memset(tag_buf, 0xff, 8); ++ tag_buf[8] = 0; ++ } else { ++ memcpy(tag_buf, &pt1, 8); ++ tag_buf[8] = 0xff; ++ } ++ } ++ ++ retval = dev->drv.drv_write_chunk_fn(dev, nand_chunk, ++ data, ++ (data) ? dev->data_bytes_per_chunk : 0, ++ tag_buf, ++ (dev->param.tags_9bytes) ? 9 : 8); ++ ++ return retval; ++} ++ ++/* Return with empty extended tags but add ecc_result. ++ */ ++static int return_empty_tags(struct yaffs_ext_tags *tags, ++ enum yaffs_ecc_result ecc_result, ++ int retval) ++{ ++ if (tags) { ++ memset(tags, 0, sizeof(*tags)); ++ tags->ecc_result = ecc_result; ++ } ++ ++ return retval; ++} ++ ++static int yaffs_tags_compat_read(struct yaffs_dev *dev, ++ int nand_chunk, ++ u8 *data, ++ struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags1 pt1; ++ enum yaffs_ecc_result ecc_result; ++ int retval; ++ int deleted; ++ u8 tag_buf[9]; ++ ++ retval = dev->drv.drv_read_chunk_fn(dev, nand_chunk, ++ data, dev->param.total_bytes_per_chunk, ++ tag_buf, ++ (dev->param.tags_9bytes) ? 9 : 8, ++ &ecc_result); ++ ++ switch (ecc_result) { ++ case YAFFS_ECC_RESULT_NO_ERROR: ++ case YAFFS_ECC_RESULT_FIXED: ++ break; ++ ++ case YAFFS_ECC_RESULT_UNFIXED: ++ default: ++ return_empty_tags(tags, YAFFS_ECC_RESULT_UNFIXED, 0); ++ tags->block_bad = dev->drv.drv_check_bad_fn(dev, nand_chunk); ++ return YAFFS_FAIL; ++ } ++ ++ /* Check for a blank/erased chunk. */ ++ if (yaffs_check_ff(tag_buf, 8)) { ++ /* when blank, upper layers want ecc_result to be <= NO_ERROR */ ++ return return_empty_tags(tags, YAFFS_ECC_RESULT_NO_ERROR, ++ YAFFS_OK); ++ } ++ ++ memcpy(&pt1, tag_buf, 8); ++ ++ if (!dev->param.tags_9bytes) { ++ /* Read deleted status (bit) then return it to it's non-deleted ++ * state before performing tags mini-ECC check. pt1.deleted is ++ * inverted. ++ */ ++ deleted = !pt1.deleted; ++ pt1.deleted = 1; ++ } else { ++ deleted = (hweight8(tag_buf[8]) < 7) ? 1 : 0; ++ } ++ ++ /* Check the packed tags mini-ECC and correct if necessary/possible. */ ++ retval = yaffs_check_tags_ecc((struct yaffs_tags *)&pt1); ++ switch (retval) { ++ case 0: ++ /* no tags error, use MTD result */ ++ break; ++ case 1: ++ /* recovered tags-ECC error */ ++ dev->n_tags_ecc_fixed++; ++ if (ecc_result == YAFFS_ECC_RESULT_NO_ERROR) ++ ecc_result = YAFFS_ECC_RESULT_FIXED; ++ break; ++ default: ++ /* unrecovered tags-ECC error */ ++ dev->n_tags_ecc_unfixed++; ++ return return_empty_tags(tags, YAFFS_ECC_RESULT_UNFIXED, ++ YAFFS_FAIL); ++ } ++ ++ /* Unpack the tags to extended form and set ECC result. ++ * [set should_be_ff just to keep yaffs_unpack_tags1 happy] ++ */ ++ pt1.should_be_ff = 0xffffffff; ++ yaffs_unpack_tags1(tags, &pt1); ++ tags->ecc_result = ecc_result; ++ ++ /* Set deleted state */ ++ tags->is_deleted = deleted; ++ return YAFFS_OK; ++} ++ ++static int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no) ++{ ++ return dev->drv.drv_mark_bad_fn(dev, block_no); ++} ++ ++static int yaffs_tags_compat_query_block(struct yaffs_dev *dev, ++ int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number) ++{ ++ struct yaffs_ext_tags tags; ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, "%s %d", __func__, block_no); ++ ++ *seq_number = 0; ++ ++ retval = dev->drv.drv_check_bad_fn(dev, block_no); ++ if (retval == YAFFS_FAIL) { ++ *state = YAFFS_BLOCK_STATE_DEAD; ++ goto out; ++ } ++ ++ yaffs_tags_compat_read(dev, block_no * dev->param.chunks_per_block, ++ NULL, &tags); ++ ++ if (tags.ecc_result != YAFFS_ECC_RESULT_NO_ERROR) { ++ yaffs_trace(YAFFS_TRACE_MTD, "block %d is marked bad", ++ block_no); ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else if (tags.chunk_used) { ++ *seq_number = tags.seq_number; ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else { ++ *state = YAFFS_BLOCK_STATE_EMPTY; ++ } ++ ++ retval = YAFFS_OK; ++ ++out: ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "block query returns seq %u state %d", ++ *seq_number, *state); ++ ++ return retval; ++} ++ ++void yaffs_tags_compat_install(struct yaffs_dev *dev) ++{ ++ if (dev->param.is_yaffs2) ++ return; ++ ++ if (!dev->tagger.write_chunk_tags_fn) ++ dev->tagger.write_chunk_tags_fn = yaffs_tags_compat_write; ++ ++ if (!dev->tagger.read_chunk_tags_fn) ++ dev->tagger.read_chunk_tags_fn = yaffs_tags_compat_read; ++ ++ if (!dev->tagger.query_block_fn) ++ dev->tagger.query_block_fn = yaffs_tags_compat_query_block; ++ ++ if (!dev->tagger.mark_bad_fn) ++ dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; ++} ++#endif diff --git a/target/linux/generic/patches-4.0/503-yaffs-add-tags-9bytes-mount-option.patch b/target/linux/generic/patches-4.0/503-yaffs-add-tags-9bytes-mount-option.patch new file mode 100644 index 0000000..3f51baf --- /dev/null +++ b/target/linux/generic/patches-4.0/503-yaffs-add-tags-9bytes-mount-option.patch @@ -0,0 +1,115 @@ +Subject: yaffs: add support for tags-9bytes mount option + +Signed-off-by: Gabor Juhos +--- +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -2644,6 +2644,7 @@ static const struct super_operations yaf + + struct yaffs_options { + int inband_tags; ++ int tags_9bytes; + int skip_checkpoint_read; + int skip_checkpoint_write; + int no_cache; +@@ -2683,6 +2684,8 @@ static int yaffs_parse_options(struct ya + + if (!strcmp(cur_opt, "inband-tags")) { + options->inband_tags = 1; ++ } else if (!strcmp(cur_opt, "tags-9bytes")) { ++ options->tags_9bytes = 1; + } else if (!strcmp(cur_opt, "tags-ecc-off")) { + options->tags_ecc_on = 0; + options->tags_ecc_overridden = 1; +@@ -2756,7 +2759,6 @@ static struct super_block *yaffs_interna + struct yaffs_param *param; + + int read_only = 0; +- int inband_tags = 0; + + struct yaffs_options options; + +@@ -2796,6 +2798,9 @@ static struct super_block *yaffs_interna + + memset(&options, 0, sizeof(options)); + ++ if (IS_ENABLED(CONFIG_YAFFS_9BYTE_TAGS)) ++ options.tags_9bytes = 1; ++ + if (yaffs_parse_options(&options, data_str)) { + /* Option parsing failed */ + return NULL; +@@ -2829,17 +2834,22 @@ static struct super_block *yaffs_interna + } + + /* Added NCB 26/5/2006 for completeness */ +- if (yaffs_version == 2 && !options.inband_tags +- && WRITE_SIZE(mtd) == 512) { ++ if (yaffs_version == 2 && ++ (!options.inband_tags || options.tags_9bytes) && ++ WRITE_SIZE(mtd) == 512) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting yaffs1"); + yaffs_version = 1; + } + +- if (mtd->oobavail < sizeof(struct yaffs_packed_tags2) || +- options.inband_tags) +- inband_tags = 1; ++ if (yaffs_version == 2 && ++ mtd->oobavail < sizeof(struct yaffs_packed_tags2)) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting inband tags"); ++ options.inband_tags = 1; ++ } + +- if(yaffs_verify_mtd(mtd, yaffs_version, inband_tags) < 0) ++ err = yaffs_verify_mtd(mtd, yaffs_version, options.inband_tags, ++ options.tags_9bytes); ++ if (err < 0) + return NULL; + + /* OK, so if we got here, we have an MTD that's NAND and looks +@@ -2896,7 +2906,8 @@ static struct super_block *yaffs_interna + + param->n_reserved_blocks = 5; + param->n_caches = (options.no_cache) ? 0 : 10; +- param->inband_tags = inband_tags; ++ param->inband_tags = options.inband_tags; ++ param->tags_9bytes = options.tags_9bytes; + + param->enable_xattr = 1; + if (options.lazy_loading_overridden) +--- a/fs/yaffs2/yaffs_mtdif.c ++++ b/fs/yaffs2/yaffs_mtdif.c +@@ -278,7 +278,8 @@ struct mtd_info * yaffs_get_mtd_device(d + return mtd; + } + +-int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags) ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags, ++ int tags_9bytes) + { + if (yaffs_version == 2) { + if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || +@@ -297,6 +298,12 @@ int yaffs_verify_mtd(struct mtd_info *mt + ); + return -1; + } ++ ++ if (tags_9bytes && mtd->oobavail < 9) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "MTD device does not support 9-byte tags"); ++ return -1; ++ } + } + + return 0; +--- a/fs/yaffs2/yaffs_mtdif.h ++++ b/fs/yaffs2/yaffs_mtdif.h +@@ -21,5 +21,6 @@ + void yaffs_mtd_drv_install(struct yaffs_dev *dev); + struct mtd_info * yaffs_get_mtd_device(dev_t sdev); + void yaffs_put_mtd_device(struct mtd_info *mtd); +-int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags); ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags, ++ int tags_9bytes); + #endif diff --git a/target/linux/generic/patches-4.0/504-yaffs-3.16-new-fops.patch b/target/linux/generic/patches-4.0/504-yaffs-3.16-new-fops.patch new file mode 100644 index 0000000..11c6da0 --- /dev/null +++ b/target/linux/generic/patches-4.0/504-yaffs-3.16-new-fops.patch @@ -0,0 +1,25 @@ +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -774,7 +774,21 @@ static int yaffs_sync_object(struct file + } + + +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) ++static const struct file_operations yaffs_file_operations = { ++ .read = new_sync_read, ++ .read_iter = generic_file_read_iter, ++ .write = new_sync_write, ++ .write_iter = generic_file_write_iter, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++ .splice_read = generic_file_splice_read, ++ .splice_write = iter_file_splice_write, ++ .llseek = generic_file_llseek, ++}; ++ ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) + static const struct file_operations yaffs_file_operations = { + .read = do_sync_read, + .write = do_sync_write, diff --git a/target/linux/generic/patches-4.0/505-yaffs-3.19-f_dentry-remove.patch b/target/linux/generic/patches-4.0/505-yaffs-3.19-f_dentry-remove.patch new file mode 100644 index 0000000..4dd2afe --- /dev/null +++ b/target/linux/generic/patches-4.0/505-yaffs-3.19-f_dentry-remove.patch @@ -0,0 +1,95 @@ +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -283,7 +283,7 @@ static int yaffs_readpage_nolock(struct + (long long)pos, + (unsigned)PAGE_CACHE_SIZE); + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -481,7 +481,7 @@ static ssize_t yaffs_hold_space(struct f + + int n_free_chunks; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -499,7 +499,7 @@ static void yaffs_release_space(struct f + struct yaffs_obj *obj; + struct yaffs_dev *dev; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -591,7 +591,7 @@ static ssize_t yaffs_file_write(struct f + struct inode *inode; + struct yaffs_dev *dev; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + if (!obj) { + yaffs_trace(YAFFS_TRACE_OS, +@@ -603,7 +603,7 @@ static ssize_t yaffs_file_write(struct f + + yaffs_gross_lock(dev); + +- inode = f->f_dentry->d_inode; ++ inode = f->f_path.dentry->d_inode; + + if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) + ipos = inode->i_size; +@@ -727,7 +727,7 @@ static int yaffs_file_flush(struct file + static int yaffs_file_flush(struct file *file) + #endif + { +- struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_dentry); ++ struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_path.dentry); + + struct yaffs_dev *dev = obj->my_dev; + +@@ -1730,7 +1730,7 @@ static int yaffs_iterate(struct file *f, + + char name[YAFFS_MAX_NAME_LENGTH + 1]; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + dev = obj->my_dev; + + yaffs_gross_lock(dev); +@@ -1794,14 +1794,14 @@ static int yaffs_readdir(struct file *f, + struct yaffs_obj *obj; + struct yaffs_dev *dev; + struct yaffs_search_context *sc; +- struct inode *inode = f->f_dentry->d_inode; ++ struct inode *inode = f->f_path.dentry->d_inode; + unsigned long offset, curoffs; + struct yaffs_obj *l; + int ret_val = 0; + + char name[YAFFS_MAX_NAME_LENGTH + 1]; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + dev = obj->my_dev; + + yaffs_gross_lock(dev); +@@ -1835,10 +1835,10 @@ static int yaffs_readdir(struct file *f, + if (offset == 1) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readdir: entry .. ino %d", +- (int)f->f_dentry->d_parent->d_inode->i_ino); ++ (int)f->f_path.dentry->d_parent->d_inode->i_ino); + yaffs_gross_unlock(dev); + if (filldir(dirent, "..", 2, offset, +- f->f_dentry->d_parent->d_inode->i_ino, ++ f->f_path.dentry->d_parent->d_inode->i_ino, + DT_DIR) < 0) { + yaffs_gross_lock(dev); + goto out; diff --git a/target/linux/generic/patches-4.0/520-squashfs_update_xz_comp_opts.patch b/target/linux/generic/patches-4.0/520-squashfs_update_xz_comp_opts.patch new file mode 100644 index 0000000..ad11b30 --- /dev/null +++ b/target/linux/generic/patches-4.0/520-squashfs_update_xz_comp_opts.patch @@ -0,0 +1,25 @@ +From f31b7c0efa255dd17a5f584022a319387f09b0d8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 12 Apr 2011 19:55:41 +0200 +Subject: [PATCH] squashfs: update xz compressor options struct. + +Update the xz compressor options struct to match the squashfs userspace +one. +--- + fs/squashfs/xz_wrapper.c | 4 +++- + 1 files changed, 3 insertions(+), 1 deletions(-) + +--- a/fs/squashfs/xz_wrapper.c ++++ b/fs/squashfs/xz_wrapper.c +@@ -40,8 +40,10 @@ struct squashfs_xz { + }; + + struct disk_comp_opts { +- __le32 dictionary_size; + __le32 flags; ++ __le16 bit_opts; ++ __le16 fb; ++ __le32 dictionary_size; + }; + + struct comp_opts { diff --git a/target/linux/generic/patches-4.0/530-jffs2_make_lzma_available.patch b/target/linux/generic/patches-4.0/530-jffs2_make_lzma_available.patch new file mode 100644 index 0000000..6a500cd --- /dev/null +++ b/target/linux/generic/patches-4.0/530-jffs2_make_lzma_available.patch @@ -0,0 +1,5142 @@ +--- a/fs/jffs2/Kconfig ++++ b/fs/jffs2/Kconfig +@@ -139,6 +139,15 @@ config JFFS2_LZO + This feature was added in July, 2007. Say 'N' if you need + compatibility with older bootloaders or kernels. + ++config JFFS2_LZMA ++ bool "JFFS2 LZMA compression support" if JFFS2_COMPRESSION_OPTIONS ++ select LZMA_COMPRESS ++ select LZMA_DECOMPRESS ++ depends on JFFS2_FS ++ default n ++ help ++ JFFS2 wrapper to the LZMA C SDK ++ + config JFFS2_RTIME + bool "JFFS2 RTIME compression support" if JFFS2_COMPRESSION_OPTIONS + depends on JFFS2_FS +--- a/fs/jffs2/Makefile ++++ b/fs/jffs2/Makefile +@@ -18,4 +18,7 @@ jffs2-$(CONFIG_JFFS2_RUBIN) += compr_rub + jffs2-$(CONFIG_JFFS2_RTIME) += compr_rtime.o + jffs2-$(CONFIG_JFFS2_ZLIB) += compr_zlib.o + jffs2-$(CONFIG_JFFS2_LZO) += compr_lzo.o ++jffs2-$(CONFIG_JFFS2_LZMA) += compr_lzma.o + jffs2-$(CONFIG_JFFS2_SUMMARY) += summary.o ++ ++CFLAGS_compr_lzma.o += -Iinclude/linux -Ilib/lzma +--- a/fs/jffs2/compr.c ++++ b/fs/jffs2/compr.c +@@ -378,6 +378,9 @@ int __init jffs2_compressors_init(void) + #ifdef CONFIG_JFFS2_LZO + jffs2_lzo_init(); + #endif ++#ifdef CONFIG_JFFS2_LZMA ++ jffs2_lzma_init(); ++#endif + /* Setting default compression mode */ + #ifdef CONFIG_JFFS2_CMODE_NONE + jffs2_compression_mode = JFFS2_COMPR_MODE_NONE; +@@ -401,6 +404,9 @@ int __init jffs2_compressors_init(void) + int jffs2_compressors_exit(void) + { + /* Unregistering compressors */ ++#ifdef CONFIG_JFFS2_LZMA ++ jffs2_lzma_exit(); ++#endif + #ifdef CONFIG_JFFS2_LZO + jffs2_lzo_exit(); + #endif +--- a/fs/jffs2/compr.h ++++ b/fs/jffs2/compr.h +@@ -29,9 +29,9 @@ + #define JFFS2_DYNRUBIN_PRIORITY 20 + #define JFFS2_LZARI_PRIORITY 30 + #define JFFS2_RTIME_PRIORITY 50 +-#define JFFS2_ZLIB_PRIORITY 60 +-#define JFFS2_LZO_PRIORITY 80 +- ++#define JFFS2_LZMA_PRIORITY 70 ++#define JFFS2_ZLIB_PRIORITY 80 ++#define JFFS2_LZO_PRIORITY 90 + + #define JFFS2_RUBINMIPS_DISABLED /* RUBINs will be used only */ + #define JFFS2_DYNRUBIN_DISABLED /* for decompression */ +@@ -101,5 +101,9 @@ void jffs2_zlib_exit(void); + int jffs2_lzo_init(void); + void jffs2_lzo_exit(void); + #endif ++#ifdef CONFIG_JFFS2_LZMA ++int jffs2_lzma_init(void); ++void jffs2_lzma_exit(void); ++#endif + + #endif /* __JFFS2_COMPR_H__ */ +--- /dev/null ++++ b/fs/jffs2/compr_lzma.c +@@ -0,0 +1,128 @@ ++/* ++ * JFFS2 -- Journalling Flash File System, Version 2. ++ * ++ * For licensing information, see the file 'LICENCE' in this directory. ++ * ++ * JFFS2 wrapper to the LZMA C SDK ++ * ++ */ ++ ++#include ++#include "compr.h" ++ ++#ifdef __KERNEL__ ++ static DEFINE_MUTEX(deflate_mutex); ++#endif ++ ++CLzmaEncHandle *p; ++Byte propsEncoded[LZMA_PROPS_SIZE]; ++SizeT propsSize = sizeof(propsEncoded); ++ ++STATIC void lzma_free_workspace(void) ++{ ++ LzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc); ++} ++ ++STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props) ++{ ++ if ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL) ++ { ++ PRINT_ERROR("Failed to allocate lzma deflate workspace\n"); ++ return -ENOMEM; ++ } ++ ++ if (LzmaEnc_SetProps(p, props) != SZ_OK) ++ { ++ lzma_free_workspace(); ++ return -1; ++ } ++ ++ if (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK) ++ { ++ lzma_free_workspace(); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out, ++ uint32_t *sourcelen, uint32_t *dstlen) ++{ ++ SizeT compress_size = (SizeT)(*dstlen); ++ int ret; ++ ++ #ifdef __KERNEL__ ++ mutex_lock(&deflate_mutex); ++ #endif ++ ++ ret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen, ++ 0, NULL, &lzma_alloc, &lzma_alloc); ++ ++ #ifdef __KERNEL__ ++ mutex_unlock(&deflate_mutex); ++ #endif ++ ++ if (ret != SZ_OK) ++ return -1; ++ ++ *dstlen = (uint32_t)compress_size; ++ ++ return 0; ++} ++ ++STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out, ++ uint32_t srclen, uint32_t destlen) ++{ ++ int ret; ++ SizeT dl = (SizeT)destlen; ++ SizeT sl = (SizeT)srclen; ++ ELzmaStatus status; ++ ++ ret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded, ++ propsSize, LZMA_FINISH_ANY, &status, &lzma_alloc); ++ ++ if (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen) ++ return -1; ++ ++ return 0; ++} ++ ++static struct jffs2_compressor jffs2_lzma_comp = { ++ .priority = JFFS2_LZMA_PRIORITY, ++ .name = "lzma", ++ .compr = JFFS2_COMPR_LZMA, ++ .compress = &jffs2_lzma_compress, ++ .decompress = &jffs2_lzma_decompress, ++ .disabled = 0, ++}; ++ ++int INIT jffs2_lzma_init(void) ++{ ++ int ret; ++ CLzmaEncProps props; ++ LzmaEncProps_Init(&props); ++ ++ props.dictSize = LZMA_BEST_DICT(0x2000); ++ props.level = LZMA_BEST_LEVEL; ++ props.lc = LZMA_BEST_LC; ++ props.lp = LZMA_BEST_LP; ++ props.pb = LZMA_BEST_PB; ++ props.fb = LZMA_BEST_FB; ++ ++ ret = lzma_alloc_workspace(&props); ++ if (ret < 0) ++ return ret; ++ ++ ret = jffs2_register_compressor(&jffs2_lzma_comp); ++ if (ret) ++ lzma_free_workspace(); ++ ++ return ret; ++} ++ ++void jffs2_lzma_exit(void) ++{ ++ jffs2_unregister_compressor(&jffs2_lzma_comp); ++ lzma_free_workspace(); ++} +--- a/fs/jffs2/super.c ++++ b/fs/jffs2/super.c +@@ -375,14 +375,41 @@ static int __init init_jffs2_fs(void) + BUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68); + BUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32); + +- pr_info("version 2.2." ++ pr_info("version 2.2" + #ifdef CONFIG_JFFS2_FS_WRITEBUFFER + " (NAND)" + #endif + #ifdef CONFIG_JFFS2_SUMMARY +- " (SUMMARY) " ++ " (SUMMARY)" + #endif +- " © 2001-2006 Red Hat, Inc.\n"); ++#ifdef CONFIG_JFFS2_ZLIB ++ " (ZLIB)" ++#endif ++#ifdef CONFIG_JFFS2_LZO ++ " (LZO)" ++#endif ++#ifdef CONFIG_JFFS2_LZMA ++ " (LZMA)" ++#endif ++#ifdef CONFIG_JFFS2_RTIME ++ " (RTIME)" ++#endif ++#ifdef CONFIG_JFFS2_RUBIN ++ " (RUBIN)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_NONE ++ " (CMODE_NONE)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_PRIORITY ++ " (CMODE_PRIORITY)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_SIZE ++ " (CMODE_SIZE)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_FAVOURLZO ++ " (CMODE_FAVOURLZO)" ++#endif ++ " (c) 2001-2006 Red Hat, Inc.\n"); + + jffs2_inode_cachep = kmem_cache_create("jffs2_i", + sizeof(struct jffs2_inode_info), +--- a/include/uapi/linux/jffs2.h ++++ b/include/uapi/linux/jffs2.h +@@ -46,6 +46,7 @@ + #define JFFS2_COMPR_DYNRUBIN 0x05 + #define JFFS2_COMPR_ZLIB 0x06 + #define JFFS2_COMPR_LZO 0x07 ++#define JFFS2_COMPR_LZMA 0x08 + /* Compatibility flags. */ + #define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ + #define JFFS2_NODE_ACCURATE 0x2000 +--- /dev/null ++++ b/include/linux/lzma.h +@@ -0,0 +1,62 @@ ++#ifndef __LZMA_H__ ++#define __LZMA_H__ ++ ++#ifdef __KERNEL__ ++ #include ++ #include ++ #include ++ #include ++ #include ++ #define LZMA_MALLOC vmalloc ++ #define LZMA_FREE vfree ++ #define PRINT_ERROR(msg) printk(KERN_WARNING #msg) ++ #define INIT __init ++ #define STATIC static ++#else ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #ifndef PAGE_SIZE ++ extern int page_size; ++ #define PAGE_SIZE page_size ++ #endif ++ #define LZMA_MALLOC malloc ++ #define LZMA_FREE free ++ #define PRINT_ERROR(msg) fprintf(stderr, msg) ++ #define INIT ++ #define STATIC ++#endif ++ ++#include "lzma/LzmaDec.h" ++#include "lzma/LzmaEnc.h" ++ ++#define LZMA_BEST_LEVEL (9) ++#define LZMA_BEST_LC (0) ++#define LZMA_BEST_LP (0) ++#define LZMA_BEST_PB (0) ++#define LZMA_BEST_FB (273) ++ ++#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2) ++ ++static void *p_lzma_malloc(void *p, size_t size) ++{ ++ if (size == 0) ++ return NULL; ++ ++ return LZMA_MALLOC(size); ++} ++ ++static void p_lzma_free(void *p, void *address) ++{ ++ if (address != NULL) ++ LZMA_FREE(address); ++} ++ ++static ISzAlloc lzma_alloc = {p_lzma_malloc, p_lzma_free}; ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzFind.h +@@ -0,0 +1,115 @@ ++/* LzFind.h -- Match finder for LZ algorithms ++2009-04-22 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZ_FIND_H ++#define __LZ_FIND_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef UInt32 CLzRef; ++ ++typedef struct _CMatchFinder ++{ ++ Byte *buffer; ++ UInt32 pos; ++ UInt32 posLimit; ++ UInt32 streamPos; ++ UInt32 lenLimit; ++ ++ UInt32 cyclicBufferPos; ++ UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */ ++ ++ UInt32 matchMaxLen; ++ CLzRef *hash; ++ CLzRef *son; ++ UInt32 hashMask; ++ UInt32 cutValue; ++ ++ Byte *bufferBase; ++ ISeqInStream *stream; ++ int streamEndWasReached; ++ ++ UInt32 blockSize; ++ UInt32 keepSizeBefore; ++ UInt32 keepSizeAfter; ++ ++ UInt32 numHashBytes; ++ int directInput; ++ size_t directInputRem; ++ int btMode; ++ int bigHash; ++ UInt32 historySize; ++ UInt32 fixedHashSize; ++ UInt32 hashSizeSum; ++ UInt32 numSons; ++ SRes result; ++ UInt32 crc[256]; ++} CMatchFinder; ++ ++#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer) ++#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)]) ++ ++#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) ++ ++int MatchFinder_NeedMove(CMatchFinder *p); ++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p); ++void MatchFinder_MoveBlock(CMatchFinder *p); ++void MatchFinder_ReadIfRequired(CMatchFinder *p); ++ ++void MatchFinder_Construct(CMatchFinder *p); ++ ++/* Conditions: ++ historySize <= 3 GB ++ keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB ++*/ ++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, ++ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, ++ ISzAlloc *alloc); ++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); ++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems); ++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue); ++ ++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, ++ UInt32 *distances, UInt32 maxLen); ++ ++/* ++Conditions: ++ Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func. ++ Mf_GetPointerToCurrentPos_Func's result must be used only before any other function ++*/ ++ ++typedef void (*Mf_Init_Func)(void *object); ++typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index); ++typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object); ++typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object); ++typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances); ++typedef void (*Mf_Skip_Func)(void *object, UInt32); ++ ++typedef struct _IMatchFinder ++{ ++ Mf_Init_Func Init; ++ Mf_GetIndexByte_Func GetIndexByte; ++ Mf_GetNumAvailableBytes_Func GetNumAvailableBytes; ++ Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos; ++ Mf_GetMatches_Func GetMatches; ++ Mf_Skip_Func Skip; ++} IMatchFinder; ++ ++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); ++ ++void MatchFinder_Init(CMatchFinder *p); ++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); ++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); ++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); ++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzHash.h +@@ -0,0 +1,54 @@ ++/* LzHash.h -- HASH functions for LZ algorithms ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZ_HASH_H ++#define __LZ_HASH_H ++ ++#define kHash2Size (1 << 10) ++#define kHash3Size (1 << 16) ++#define kHash4Size (1 << 20) ++ ++#define kFix3HashSize (kHash2Size) ++#define kFix4HashSize (kHash2Size + kHash3Size) ++#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size) ++ ++#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8); ++ ++#define HASH3_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; } ++ ++#define HASH4_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; } ++ ++#define HASH5_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \ ++ hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \ ++ hash4Value &= (kHash4Size - 1); } ++ ++/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */ ++#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF; ++ ++ ++#define MT_HASH2_CALC \ ++ hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1); ++ ++#define MT_HASH3_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); } ++ ++#define MT_HASH4_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); } ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzmaDec.h +@@ -0,0 +1,231 @@ ++/* LzmaDec.h -- LZMA Decoder ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZMA_DEC_H ++#define __LZMA_DEC_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* #define _LZMA_PROB32 */ ++/* _LZMA_PROB32 can increase the speed on some CPUs, ++ but memory usage for CLzmaDec::probs will be doubled in that case */ ++ ++#ifdef _LZMA_PROB32 ++#define CLzmaProb UInt32 ++#else ++#define CLzmaProb UInt16 ++#endif ++ ++ ++/* ---------- LZMA Properties ---------- */ ++ ++#define LZMA_PROPS_SIZE 5 ++ ++typedef struct _CLzmaProps ++{ ++ unsigned lc, lp, pb; ++ UInt32 dicSize; ++} CLzmaProps; ++ ++/* LzmaProps_Decode - decodes properties ++Returns: ++ SZ_OK ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++*/ ++ ++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); ++ ++ ++/* ---------- LZMA Decoder state ---------- */ ++ ++/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case. ++ Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */ ++ ++#define LZMA_REQUIRED_INPUT_MAX 20 ++ ++typedef struct ++{ ++ CLzmaProps prop; ++ CLzmaProb *probs; ++ Byte *dic; ++ const Byte *buf; ++ UInt32 range, code; ++ SizeT dicPos; ++ SizeT dicBufSize; ++ UInt32 processedPos; ++ UInt32 checkDicSize; ++ unsigned state; ++ UInt32 reps[4]; ++ unsigned remainLen; ++ int needFlush; ++ int needInitState; ++ UInt32 numProbs; ++ unsigned tempBufSize; ++ Byte tempBuf[LZMA_REQUIRED_INPUT_MAX]; ++} CLzmaDec; ++ ++#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } ++ ++void LzmaDec_Init(CLzmaDec *p); ++ ++/* There are two types of LZMA streams: ++ 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. ++ 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ ++ ++typedef enum ++{ ++ LZMA_FINISH_ANY, /* finish at any point */ ++ LZMA_FINISH_END /* block must be finished at the end */ ++} ELzmaFinishMode; ++ ++/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!! ++ ++ You must use LZMA_FINISH_END, when you know that current output buffer ++ covers last bytes of block. In other cases you must use LZMA_FINISH_ANY. ++ ++ If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK, ++ and output value of destLen will be less than output buffer size limit. ++ You can check status result also. ++ ++ You can use multiple checks to test data integrity after full decompression: ++ 1) Check Result and "status" variable. ++ 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize. ++ 3) Check that output(srcLen) = compressedSize, if you know real compressedSize. ++ You must use correct finish mode in that case. */ ++ ++typedef enum ++{ ++ LZMA_STATUS_NOT_SPECIFIED, /* use main error code instead */ ++ LZMA_STATUS_FINISHED_WITH_MARK, /* stream was finished with end mark. */ ++ LZMA_STATUS_NOT_FINISHED, /* stream was not finished */ ++ LZMA_STATUS_NEEDS_MORE_INPUT, /* you must provide more input bytes */ ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK /* there is probability that stream was finished without end mark */ ++} ELzmaStatus; ++ ++/* ELzmaStatus is used only as output value for function call */ ++ ++ ++/* ---------- Interfaces ---------- */ ++ ++/* There are 3 levels of interfaces: ++ 1) Dictionary Interface ++ 2) Buffer Interface ++ 3) One Call Interface ++ You can select any of these interfaces, but don't mix functions from different ++ groups for same object. */ ++ ++ ++/* There are two variants to allocate state for Dictionary Interface: ++ 1) LzmaDec_Allocate / LzmaDec_Free ++ 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs ++ You can use variant 2, if you set dictionary buffer manually. ++ For Buffer Interface you must always use variant 1. ++ ++LzmaDec_Allocate* can return: ++ SZ_OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++*/ ++ ++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); ++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); ++ ++SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); ++void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); ++ ++/* ---------- Dictionary Interface ---------- */ ++ ++/* You can use it, if you want to eliminate the overhead for data copying from ++ dictionary to some other external buffer. ++ You must work with CLzmaDec variables directly in this interface. ++ ++ STEPS: ++ LzmaDec_Constr() ++ LzmaDec_Allocate() ++ for (each new stream) ++ { ++ LzmaDec_Init() ++ while (it needs more decompression) ++ { ++ LzmaDec_DecodeToDic() ++ use data from CLzmaDec::dic and update CLzmaDec::dicPos ++ } ++ } ++ LzmaDec_Free() ++*/ ++ ++/* LzmaDec_DecodeToDic ++ ++ The decoding to internal dictionary buffer (CLzmaDec::dic). ++ You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (dicLimit). ++ LZMA_FINISH_ANY - Decode just dicLimit bytes. ++ LZMA_FINISH_END - Stream must be finished after dicLimit. ++ ++Returns: ++ SZ_OK ++ status: ++ LZMA_STATUS_FINISHED_WITH_MARK ++ LZMA_STATUS_NOT_FINISHED ++ LZMA_STATUS_NEEDS_MORE_INPUT ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK ++ SZ_ERROR_DATA - Data error ++*/ ++ ++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, ++ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); ++ ++ ++/* ---------- Buffer Interface ---------- */ ++ ++/* It's zlib-like interface. ++ See LzmaDec_DecodeToDic description for information about STEPS and return results, ++ but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need ++ to work with CLzmaDec variables manually. ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (*destLen). ++ LZMA_FINISH_ANY - Decode just destLen bytes. ++ LZMA_FINISH_END - Stream must be finished after (*destLen). ++*/ ++ ++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, ++ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); ++ ++ ++/* ---------- One Call Interface ---------- */ ++ ++/* LzmaDecode ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (*destLen). ++ LZMA_FINISH_ANY - Decode just destLen bytes. ++ LZMA_FINISH_END - Stream must be finished after (*destLen). ++ ++Returns: ++ SZ_OK ++ status: ++ LZMA_STATUS_FINISHED_WITH_MARK ++ LZMA_STATUS_NOT_FINISHED ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK ++ SZ_ERROR_DATA - Data error ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++ SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src). ++*/ ++ ++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ++ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, ++ ELzmaStatus *status, ISzAlloc *alloc); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzmaEnc.h +@@ -0,0 +1,80 @@ ++/* LzmaEnc.h -- LZMA Encoder ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZMA_ENC_H ++#define __LZMA_ENC_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define LZMA_PROPS_SIZE 5 ++ ++typedef struct _CLzmaEncProps ++{ ++ int level; /* 0 <= level <= 9 */ ++ UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version ++ (1 << 12) <= dictSize <= (1 << 30) for 64-bit version ++ default = (1 << 24) */ ++ int lc; /* 0 <= lc <= 8, default = 3 */ ++ int lp; /* 0 <= lp <= 4, default = 0 */ ++ int pb; /* 0 <= pb <= 4, default = 2 */ ++ int algo; /* 0 - fast, 1 - normal, default = 1 */ ++ int fb; /* 5 <= fb <= 273, default = 32 */ ++ int btMode; /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */ ++ int numHashBytes; /* 2, 3 or 4, default = 4 */ ++ UInt32 mc; /* 1 <= mc <= (1 << 30), default = 32 */ ++ unsigned writeEndMark; /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */ ++ int numThreads; /* 1 or 2, default = 2 */ ++} CLzmaEncProps; ++ ++void LzmaEncProps_Init(CLzmaEncProps *p); ++void LzmaEncProps_Normalize(CLzmaEncProps *p); ++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2); ++ ++ ++/* ---------- CLzmaEncHandle Interface ---------- */ ++ ++/* LzmaEnc_* functions can return the following exit codes: ++Returns: ++ SZ_OK - OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_PARAM - Incorrect paramater in props ++ SZ_ERROR_WRITE - Write callback error. ++ SZ_ERROR_PROGRESS - some break from progress callback ++ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) ++*/ ++ ++typedef void * CLzmaEncHandle; ++ ++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc); ++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); ++SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); ++SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); ++SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++ ++/* ---------- One Call Interface ---------- */ ++ ++/* LzmaEncode ++Return code: ++ SZ_OK - OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_PARAM - Incorrect paramater ++ SZ_ERROR_OUTPUT_EOF - output buffer overflow ++ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) ++*/ ++ ++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/Types.h +@@ -0,0 +1,226 @@ ++/* Types.h -- Basic types ++2009-11-23 : Igor Pavlov : Public domain */ ++ ++#ifndef __7Z_TYPES_H ++#define __7Z_TYPES_H ++ ++#include ++ ++#ifdef _WIN32 ++#include ++#endif ++ ++#ifndef EXTERN_C_BEGIN ++#ifdef __cplusplus ++#define EXTERN_C_BEGIN extern "C" { ++#define EXTERN_C_END } ++#else ++#define EXTERN_C_BEGIN ++#define EXTERN_C_END ++#endif ++#endif ++ ++EXTERN_C_BEGIN ++ ++#define SZ_OK 0 ++ ++#define SZ_ERROR_DATA 1 ++#define SZ_ERROR_MEM 2 ++#define SZ_ERROR_CRC 3 ++#define SZ_ERROR_UNSUPPORTED 4 ++#define SZ_ERROR_PARAM 5 ++#define SZ_ERROR_INPUT_EOF 6 ++#define SZ_ERROR_OUTPUT_EOF 7 ++#define SZ_ERROR_READ 8 ++#define SZ_ERROR_WRITE 9 ++#define SZ_ERROR_PROGRESS 10 ++#define SZ_ERROR_FAIL 11 ++#define SZ_ERROR_THREAD 12 ++ ++#define SZ_ERROR_ARCHIVE 16 ++#define SZ_ERROR_NO_ARCHIVE 17 ++ ++typedef int SRes; ++ ++#ifdef _WIN32 ++typedef DWORD WRes; ++#else ++typedef int WRes; ++#endif ++ ++#ifndef RINOK ++#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; } ++#endif ++ ++typedef unsigned char Byte; ++typedef short Int16; ++typedef unsigned short UInt16; ++ ++#ifdef _LZMA_UINT32_IS_ULONG ++typedef long Int32; ++typedef unsigned long UInt32; ++#else ++typedef int Int32; ++typedef unsigned int UInt32; ++#endif ++ ++#ifdef _SZ_NO_INT_64 ++ ++/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers. ++ NOTES: Some code will work incorrectly in that case! */ ++ ++typedef long Int64; ++typedef unsigned long UInt64; ++ ++#else ++ ++#if defined(_MSC_VER) || defined(__BORLANDC__) ++typedef __int64 Int64; ++typedef unsigned __int64 UInt64; ++#else ++typedef long long int Int64; ++typedef unsigned long long int UInt64; ++#endif ++ ++#endif ++ ++#ifdef _LZMA_NO_SYSTEM_SIZE_T ++typedef UInt32 SizeT; ++#else ++typedef size_t SizeT; ++#endif ++ ++typedef int Bool; ++#define True 1 ++#define False 0 ++ ++ ++#ifdef _WIN32 ++#define MY_STD_CALL __stdcall ++#else ++#define MY_STD_CALL ++#endif ++ ++#ifdef _MSC_VER ++ ++#if _MSC_VER >= 1300 ++#define MY_NO_INLINE __declspec(noinline) ++#else ++#define MY_NO_INLINE ++#endif ++ ++#define MY_CDECL __cdecl ++#define MY_FAST_CALL __fastcall ++ ++#else ++ ++#define MY_CDECL ++#define MY_FAST_CALL ++ ++#endif ++ ++ ++/* The following interfaces use first parameter as pointer to structure */ ++ ++typedef struct ++{ ++ SRes (*Read)(void *p, void *buf, size_t *size); ++ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. ++ (output(*size) < input(*size)) is allowed */ ++} ISeqInStream; ++ ++/* it can return SZ_ERROR_INPUT_EOF */ ++SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size); ++SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType); ++SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf); ++ ++typedef struct ++{ ++ size_t (*Write)(void *p, const void *buf, size_t size); ++ /* Returns: result - the number of actually written bytes. ++ (result < size) means error */ ++} ISeqOutStream; ++ ++typedef enum ++{ ++ SZ_SEEK_SET = 0, ++ SZ_SEEK_CUR = 1, ++ SZ_SEEK_END = 2 ++} ESzSeek; ++ ++typedef struct ++{ ++ SRes (*Read)(void *p, void *buf, size_t *size); /* same as ISeqInStream::Read */ ++ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); ++} ISeekInStream; ++ ++typedef struct ++{ ++ SRes (*Look)(void *p, void **buf, size_t *size); ++ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. ++ (output(*size) > input(*size)) is not allowed ++ (output(*size) < input(*size)) is allowed */ ++ SRes (*Skip)(void *p, size_t offset); ++ /* offset must be <= output(*size) of Look */ ++ ++ SRes (*Read)(void *p, void *buf, size_t *size); ++ /* reads directly (without buffer). It's same as ISeqInStream::Read */ ++ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); ++} ILookInStream; ++ ++SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size); ++SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset); ++ ++/* reads via ILookInStream::Read */ ++SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType); ++SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size); ++ ++#define LookToRead_BUF_SIZE (1 << 14) ++ ++typedef struct ++{ ++ ILookInStream s; ++ ISeekInStream *realStream; ++ size_t pos; ++ size_t size; ++ Byte buf[LookToRead_BUF_SIZE]; ++} CLookToRead; ++ ++void LookToRead_CreateVTable(CLookToRead *p, int lookahead); ++void LookToRead_Init(CLookToRead *p); ++ ++typedef struct ++{ ++ ISeqInStream s; ++ ILookInStream *realStream; ++} CSecToLook; ++ ++void SecToLook_CreateVTable(CSecToLook *p); ++ ++typedef struct ++{ ++ ISeqInStream s; ++ ILookInStream *realStream; ++} CSecToRead; ++ ++void SecToRead_CreateVTable(CSecToRead *p); ++ ++typedef struct ++{ ++ SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize); ++ /* Returns: result. (result != SZ_OK) means break. ++ Value (UInt64)(Int64)-1 for size means unknown value. */ ++} ICompressProgress; ++ ++typedef struct ++{ ++ void *(*Alloc)(void *p, size_t size); ++ void (*Free)(void *p, void *address); /* address can be 0 */ ++} ISzAlloc; ++ ++#define IAlloc_Alloc(p, size) (p)->Alloc((p), size) ++#define IAlloc_Free(p, a) (p)->Free((p), a) ++ ++EXTERN_C_END ++ ++#endif +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -236,6 +236,12 @@ config LZ4_DECOMPRESS + + source "lib/xz/Kconfig" + ++config LZMA_COMPRESS ++ tristate ++ ++config LZMA_DECOMPRESS ++ tristate ++ + # + # These all provide a common interface (hence the apparent duplication with + # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -2,6 +2,16 @@ + # Makefile for some libs needed in the kernel. + # + ++ifdef CONFIG_JFFS2_ZLIB ++ CONFIG_ZLIB_INFLATE:=y ++ CONFIG_ZLIB_DEFLATE:=y ++endif ++ ++ifdef CONFIG_JFFS2_LZMA ++ CONFIG_LZMA_DECOMPRESS:=y ++ CONFIG_LZMA_COMPRESS:=y ++endif ++ + ifdef CONFIG_FUNCTION_TRACER + ORIG_CFLAGS := $(KBUILD_CFLAGS) + KBUILD_CFLAGS = $(subst $(CC_FLAGS_FTRACE),,$(ORIG_CFLAGS)) +@@ -89,6 +99,8 @@ obj-$(CONFIG_LZ4HC_COMPRESS) += lz4/ + obj-$(CONFIG_LZ4_DECOMPRESS) += lz4/ + obj-$(CONFIG_XZ_DEC) += xz/ + obj-$(CONFIG_RAID6_PQ) += raid6/ ++obj-$(CONFIG_LZMA_COMPRESS) += lzma/ ++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ + + lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o + lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o +--- /dev/null ++++ b/lib/lzma/LzFind.c +@@ -0,0 +1,761 @@ ++/* LzFind.c -- Match finder for LZ algorithms ++2009-04-22 : Igor Pavlov : Public domain */ ++ ++#include ++ ++#include "LzFind.h" ++#include "LzHash.h" ++ ++#define kEmptyHashValue 0 ++#define kMaxValForNormalize ((UInt32)0xFFFFFFFF) ++#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */ ++#define kNormalizeMask (~(kNormalizeStepMin - 1)) ++#define kMaxHistorySize ((UInt32)3 << 30) ++ ++#define kStartMaxLen 3 ++ ++static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ if (!p->directInput) ++ { ++ alloc->Free(alloc, p->bufferBase); ++ p->bufferBase = 0; ++ } ++} ++ ++/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */ ++ ++static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) ++{ ++ UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; ++ if (p->directInput) ++ { ++ p->blockSize = blockSize; ++ return 1; ++ } ++ if (p->bufferBase == 0 || p->blockSize != blockSize) ++ { ++ LzInWindow_Free(p, alloc); ++ p->blockSize = blockSize; ++ p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize); ++ } ++ return (p->bufferBase != 0); ++} ++ ++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } ++Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } ++ ++UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } ++ ++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) ++{ ++ p->posLimit -= subValue; ++ p->pos -= subValue; ++ p->streamPos -= subValue; ++} ++ ++static void MatchFinder_ReadBlock(CMatchFinder *p) ++{ ++ if (p->streamEndWasReached || p->result != SZ_OK) ++ return; ++ if (p->directInput) ++ { ++ UInt32 curSize = 0xFFFFFFFF - p->streamPos; ++ if (curSize > p->directInputRem) ++ curSize = (UInt32)p->directInputRem; ++ p->directInputRem -= curSize; ++ p->streamPos += curSize; ++ if (p->directInputRem == 0) ++ p->streamEndWasReached = 1; ++ return; ++ } ++ for (;;) ++ { ++ Byte *dest = p->buffer + (p->streamPos - p->pos); ++ size_t size = (p->bufferBase + p->blockSize - dest); ++ if (size == 0) ++ return; ++ p->result = p->stream->Read(p->stream, dest, &size); ++ if (p->result != SZ_OK) ++ return; ++ if (size == 0) ++ { ++ p->streamEndWasReached = 1; ++ return; ++ } ++ p->streamPos += (UInt32)size; ++ if (p->streamPos - p->pos > p->keepSizeAfter) ++ return; ++ } ++} ++ ++void MatchFinder_MoveBlock(CMatchFinder *p) ++{ ++ memmove(p->bufferBase, ++ p->buffer - p->keepSizeBefore, ++ (size_t)(p->streamPos - p->pos + p->keepSizeBefore)); ++ p->buffer = p->bufferBase + p->keepSizeBefore; ++} ++ ++int MatchFinder_NeedMove(CMatchFinder *p) ++{ ++ if (p->directInput) ++ return 0; ++ /* if (p->streamEndWasReached) return 0; */ ++ return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); ++} ++ ++void MatchFinder_ReadIfRequired(CMatchFinder *p) ++{ ++ if (p->streamEndWasReached) ++ return; ++ if (p->keepSizeAfter >= p->streamPos - p->pos) ++ MatchFinder_ReadBlock(p); ++} ++ ++static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) ++{ ++ if (MatchFinder_NeedMove(p)) ++ MatchFinder_MoveBlock(p); ++ MatchFinder_ReadBlock(p); ++} ++ ++static void MatchFinder_SetDefaultSettings(CMatchFinder *p) ++{ ++ p->cutValue = 32; ++ p->btMode = 1; ++ p->numHashBytes = 4; ++ p->bigHash = 0; ++} ++ ++#define kCrcPoly 0xEDB88320 ++ ++void MatchFinder_Construct(CMatchFinder *p) ++{ ++ UInt32 i; ++ p->bufferBase = 0; ++ p->directInput = 0; ++ p->hash = 0; ++ MatchFinder_SetDefaultSettings(p); ++ ++ for (i = 0; i < 256; i++) ++ { ++ UInt32 r = i; ++ int j; ++ for (j = 0; j < 8; j++) ++ r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1)); ++ p->crc[i] = r; ++ } ++} ++ ++static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->hash); ++ p->hash = 0; ++} ++ ++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ MatchFinder_FreeThisClassMemory(p, alloc); ++ LzInWindow_Free(p, alloc); ++} ++ ++static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc) ++{ ++ size_t sizeInBytes = (size_t)num * sizeof(CLzRef); ++ if (sizeInBytes / sizeof(CLzRef) != num) ++ return 0; ++ return (CLzRef *)alloc->Alloc(alloc, sizeInBytes); ++} ++ ++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, ++ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, ++ ISzAlloc *alloc) ++{ ++ UInt32 sizeReserv; ++ if (historySize > kMaxHistorySize) ++ { ++ MatchFinder_Free(p, alloc); ++ return 0; ++ } ++ sizeReserv = historySize >> 1; ++ if (historySize > ((UInt32)2 << 30)) ++ sizeReserv = historySize >> 2; ++ sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19); ++ ++ p->keepSizeBefore = historySize + keepAddBufferBefore + 1; ++ p->keepSizeAfter = matchMaxLen + keepAddBufferAfter; ++ /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */ ++ if (LzInWindow_Create(p, sizeReserv, alloc)) ++ { ++ UInt32 newCyclicBufferSize = historySize + 1; ++ UInt32 hs; ++ p->matchMaxLen = matchMaxLen; ++ { ++ p->fixedHashSize = 0; ++ if (p->numHashBytes == 2) ++ hs = (1 << 16) - 1; ++ else ++ { ++ hs = historySize - 1; ++ hs |= (hs >> 1); ++ hs |= (hs >> 2); ++ hs |= (hs >> 4); ++ hs |= (hs >> 8); ++ hs >>= 1; ++ hs |= 0xFFFF; /* don't change it! It's required for Deflate */ ++ if (hs > (1 << 24)) ++ { ++ if (p->numHashBytes == 3) ++ hs = (1 << 24) - 1; ++ else ++ hs >>= 1; ++ } ++ } ++ p->hashMask = hs; ++ hs++; ++ if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size; ++ if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size; ++ if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size; ++ hs += p->fixedHashSize; ++ } ++ ++ { ++ UInt32 prevSize = p->hashSizeSum + p->numSons; ++ UInt32 newSize; ++ p->historySize = historySize; ++ p->hashSizeSum = hs; ++ p->cyclicBufferSize = newCyclicBufferSize; ++ p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize); ++ newSize = p->hashSizeSum + p->numSons; ++ if (p->hash != 0 && prevSize == newSize) ++ return 1; ++ MatchFinder_FreeThisClassMemory(p, alloc); ++ p->hash = AllocRefs(newSize, alloc); ++ if (p->hash != 0) ++ { ++ p->son = p->hash + p->hashSizeSum; ++ return 1; ++ } ++ } ++ } ++ MatchFinder_Free(p, alloc); ++ return 0; ++} ++ ++static void MatchFinder_SetLimits(CMatchFinder *p) ++{ ++ UInt32 limit = kMaxValForNormalize - p->pos; ++ UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos; ++ if (limit2 < limit) ++ limit = limit2; ++ limit2 = p->streamPos - p->pos; ++ if (limit2 <= p->keepSizeAfter) ++ { ++ if (limit2 > 0) ++ limit2 = 1; ++ } ++ else ++ limit2 -= p->keepSizeAfter; ++ if (limit2 < limit) ++ limit = limit2; ++ { ++ UInt32 lenLimit = p->streamPos - p->pos; ++ if (lenLimit > p->matchMaxLen) ++ lenLimit = p->matchMaxLen; ++ p->lenLimit = lenLimit; ++ } ++ p->posLimit = p->pos + limit; ++} ++ ++void MatchFinder_Init(CMatchFinder *p) ++{ ++ UInt32 i; ++ for (i = 0; i < p->hashSizeSum; i++) ++ p->hash[i] = kEmptyHashValue; ++ p->cyclicBufferPos = 0; ++ p->buffer = p->bufferBase; ++ p->pos = p->streamPos = p->cyclicBufferSize; ++ p->result = SZ_OK; ++ p->streamEndWasReached = 0; ++ MatchFinder_ReadBlock(p); ++ MatchFinder_SetLimits(p); ++} ++ ++static UInt32 MatchFinder_GetSubValue(CMatchFinder *p) ++{ ++ return (p->pos - p->historySize - 1) & kNormalizeMask; ++} ++ ++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) ++{ ++ UInt32 i; ++ for (i = 0; i < numItems; i++) ++ { ++ UInt32 value = items[i]; ++ if (value <= subValue) ++ value = kEmptyHashValue; ++ else ++ value -= subValue; ++ items[i] = value; ++ } ++} ++ ++static void MatchFinder_Normalize(CMatchFinder *p) ++{ ++ UInt32 subValue = MatchFinder_GetSubValue(p); ++ MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons); ++ MatchFinder_ReduceOffsets(p, subValue); ++} ++ ++static void MatchFinder_CheckLimits(CMatchFinder *p) ++{ ++ if (p->pos == kMaxValForNormalize) ++ MatchFinder_Normalize(p); ++ if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos) ++ MatchFinder_CheckAndMoveAndRead(p); ++ if (p->cyclicBufferPos == p->cyclicBufferSize) ++ p->cyclicBufferPos = 0; ++ MatchFinder_SetLimits(p); ++} ++ ++static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, ++ UInt32 *distances, UInt32 maxLen) ++{ ++ son[_cyclicBufferPos] = curMatch; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ return distances; ++ { ++ const Byte *pb = cur - delta; ++ curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)]; ++ if (pb[maxLen] == cur[maxLen] && *pb == *cur) ++ { ++ UInt32 len = 0; ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ if (maxLen < len) ++ { ++ *distances++ = maxLen = len; ++ *distances++ = delta - 1; ++ if (len == lenLimit) ++ return distances; ++ } ++ } ++ } ++ } ++} ++ ++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, ++ UInt32 *distances, UInt32 maxLen) ++{ ++ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; ++ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); ++ UInt32 len0 = 0, len1 = 0; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ { ++ *ptr0 = *ptr1 = kEmptyHashValue; ++ return distances; ++ } ++ { ++ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); ++ const Byte *pb = cur - delta; ++ UInt32 len = (len0 < len1 ? len0 : len1); ++ if (pb[len] == cur[len]) ++ { ++ if (++len != lenLimit && pb[len] == cur[len]) ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ if (maxLen < len) ++ { ++ *distances++ = maxLen = len; ++ *distances++ = delta - 1; ++ if (len == lenLimit) ++ { ++ *ptr1 = pair[0]; ++ *ptr0 = pair[1]; ++ return distances; ++ } ++ } ++ } ++ if (pb[len] < cur[len]) ++ { ++ *ptr1 = curMatch; ++ ptr1 = pair + 1; ++ curMatch = *ptr1; ++ len1 = len; ++ } ++ else ++ { ++ *ptr0 = curMatch; ++ ptr0 = pair; ++ curMatch = *ptr0; ++ len0 = len; ++ } ++ } ++ } ++} ++ ++static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue) ++{ ++ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; ++ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); ++ UInt32 len0 = 0, len1 = 0; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ { ++ *ptr0 = *ptr1 = kEmptyHashValue; ++ return; ++ } ++ { ++ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); ++ const Byte *pb = cur - delta; ++ UInt32 len = (len0 < len1 ? len0 : len1); ++ if (pb[len] == cur[len]) ++ { ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ { ++ if (len == lenLimit) ++ { ++ *ptr1 = pair[0]; ++ *ptr0 = pair[1]; ++ return; ++ } ++ } ++ } ++ if (pb[len] < cur[len]) ++ { ++ *ptr1 = curMatch; ++ ptr1 = pair + 1; ++ curMatch = *ptr1; ++ len1 = len; ++ } ++ else ++ { ++ *ptr0 = curMatch; ++ ptr0 = pair; ++ curMatch = *ptr0; ++ len0 = len; ++ } ++ } ++ } ++} ++ ++#define MOVE_POS \ ++ ++p->cyclicBufferPos; \ ++ p->buffer++; \ ++ if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); ++ ++#define MOVE_POS_RET MOVE_POS return offset; ++ ++static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } ++ ++#define GET_MATCHES_HEADER2(minLen, ret_op) \ ++ UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ ++ lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ ++ cur = p->buffer; ++ ++#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0) ++#define SKIP_HEADER(minLen) GET_MATCHES_HEADER2(minLen, continue) ++ ++#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue ++ ++#define GET_MATCHES_FOOTER(offset, maxLen) \ ++ offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \ ++ distances + offset, maxLen) - distances); MOVE_POS_RET; ++ ++#define SKIP_FOOTER \ ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS; ++ ++static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(2) ++ HASH2_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = 0; ++ GET_MATCHES_FOOTER(offset, 1) ++} ++ ++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = 0; ++ GET_MATCHES_FOOTER(offset, 2) ++} ++ ++static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, delta2, maxLen, offset; ++ GET_MATCHES_HEADER(3) ++ ++ HASH3_CALC; ++ ++ delta2 = p->pos - p->hash[hash2Value]; ++ curMatch = p->hash[kFix3HashSize + hashValue]; ++ ++ p->hash[hash2Value] = ++ p->hash[kFix3HashSize + hashValue] = p->pos; ++ ++ ++ maxLen = 2; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[0] = maxLen; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ if (maxLen == lenLimit) ++ { ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); ++ MOVE_POS_RET; ++ } ++ } ++ GET_MATCHES_FOOTER(offset, maxLen) ++} ++ ++static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; ++ GET_MATCHES_HEADER(4) ++ ++ HASH4_CALC; ++ ++ delta2 = p->pos - p->hash[ hash2Value]; ++ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ ++ maxLen = 1; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ distances[0] = maxLen = 2; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ } ++ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) ++ { ++ maxLen = 3; ++ distances[offset + 1] = delta3 - 1; ++ offset += 2; ++ delta2 = delta3; ++ } ++ if (offset != 0) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[offset - 2] = maxLen; ++ if (maxLen == lenLimit) ++ { ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); ++ MOVE_POS_RET; ++ } ++ } ++ if (maxLen < 3) ++ maxLen = 3; ++ GET_MATCHES_FOOTER(offset, maxLen) ++} ++ ++static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; ++ GET_MATCHES_HEADER(4) ++ ++ HASH4_CALC; ++ ++ delta2 = p->pos - p->hash[ hash2Value]; ++ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ ++ maxLen = 1; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ distances[0] = maxLen = 2; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ } ++ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) ++ { ++ maxLen = 3; ++ distances[offset + 1] = delta3 - 1; ++ offset += 2; ++ delta2 = delta3; ++ } ++ if (offset != 0) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[offset - 2] = maxLen; ++ if (maxLen == lenLimit) ++ { ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS_RET; ++ } ++ } ++ if (maxLen < 3) ++ maxLen = 3; ++ offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), ++ distances + offset, maxLen) - (distances)); ++ MOVE_POS_RET ++} ++ ++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), ++ distances, 2) - (distances)); ++ MOVE_POS_RET ++} ++ ++static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(2) ++ HASH2_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value; ++ SKIP_HEADER(3) ++ HASH3_CALC; ++ curMatch = p->hash[kFix3HashSize + hashValue]; ++ p->hash[hash2Value] = ++ p->hash[kFix3HashSize + hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value, hash3Value; ++ SKIP_HEADER(4) ++ HASH4_CALC; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = p->pos; ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value, hash3Value; ++ SKIP_HEADER(4) ++ HASH4_CALC; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS ++ } ++ while (--num != 0); ++} ++ ++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS ++ } ++ while (--num != 0); ++} ++ ++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) ++{ ++ vTable->Init = (Mf_Init_Func)MatchFinder_Init; ++ vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; ++ vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; ++ vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; ++ if (!p->btMode) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip; ++ } ++ else if (p->numHashBytes == 2) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip; ++ } ++ else if (p->numHashBytes == 3) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip; ++ } ++ else ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; ++ } ++} +--- /dev/null ++++ b/lib/lzma/LzmaDec.c +@@ -0,0 +1,999 @@ ++/* LzmaDec.c -- LZMA Decoder ++2009-09-20 : Igor Pavlov : Public domain */ ++ ++#include "LzmaDec.h" ++ ++#include ++ ++#define kNumTopBits 24 ++#define kTopValue ((UInt32)1 << kNumTopBits) ++ ++#define kNumBitModelTotalBits 11 ++#define kBitModelTotal (1 << kNumBitModelTotalBits) ++#define kNumMoveBits 5 ++ ++#define RC_INIT_SIZE 5 ++ ++#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); } ++ ++#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) ++#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits)); ++#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits)); ++#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \ ++ { UPDATE_0(p); i = (i + i); A0; } else \ ++ { UPDATE_1(p); i = (i + i) + 1; A1; } ++#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;) ++ ++#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); } ++#define TREE_DECODE(probs, limit, i) \ ++ { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; } ++ ++/* #define _LZMA_SIZE_OPT */ ++ ++#ifdef _LZMA_SIZE_OPT ++#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i) ++#else ++#define TREE_6_DECODE(probs, i) \ ++ { i = 1; \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ i -= 0x40; } ++#endif ++ ++#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); } ++ ++#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) ++#define UPDATE_0_CHECK range = bound; ++#define UPDATE_1_CHECK range -= bound; code -= bound; ++#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \ ++ { UPDATE_0_CHECK; i = (i + i); A0; } else \ ++ { UPDATE_1_CHECK; i = (i + i) + 1; A1; } ++#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;) ++#define TREE_DECODE_CHECK(probs, limit, i) \ ++ { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; } ++ ++ ++#define kNumPosBitsMax 4 ++#define kNumPosStatesMax (1 << kNumPosBitsMax) ++ ++#define kLenNumLowBits 3 ++#define kLenNumLowSymbols (1 << kLenNumLowBits) ++#define kLenNumMidBits 3 ++#define kLenNumMidSymbols (1 << kLenNumMidBits) ++#define kLenNumHighBits 8 ++#define kLenNumHighSymbols (1 << kLenNumHighBits) ++ ++#define LenChoice 0 ++#define LenChoice2 (LenChoice + 1) ++#define LenLow (LenChoice2 + 1) ++#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) ++#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) ++#define kNumLenProbs (LenHigh + kLenNumHighSymbols) ++ ++ ++#define kNumStates 12 ++#define kNumLitStates 7 ++ ++#define kStartPosModelIndex 4 ++#define kEndPosModelIndex 14 ++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) ++ ++#define kNumPosSlotBits 6 ++#define kNumLenToPosStates 4 ++ ++#define kNumAlignBits 4 ++#define kAlignTableSize (1 << kNumAlignBits) ++ ++#define kMatchMinLen 2 ++#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) ++ ++#define IsMatch 0 ++#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) ++#define IsRepG0 (IsRep + kNumStates) ++#define IsRepG1 (IsRepG0 + kNumStates) ++#define IsRepG2 (IsRepG1 + kNumStates) ++#define IsRep0Long (IsRepG2 + kNumStates) ++#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) ++#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) ++#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) ++#define LenCoder (Align + kAlignTableSize) ++#define RepLenCoder (LenCoder + kNumLenProbs) ++#define Literal (RepLenCoder + kNumLenProbs) ++ ++#define LZMA_BASE_SIZE 1846 ++#define LZMA_LIT_SIZE 768 ++ ++#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp))) ++ ++#if Literal != LZMA_BASE_SIZE ++StopCompilingDueBUG ++#endif ++ ++#define LZMA_DIC_MIN (1 << 12) ++ ++/* First LZMA-symbol is always decoded. ++And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization ++Out: ++ Result: ++ SZ_OK - OK ++ SZ_ERROR_DATA - Error ++ p->remainLen: ++ < kMatchSpecLenStart : normal remain ++ = kMatchSpecLenStart : finished ++ = kMatchSpecLenStart + 1 : Flush marker ++ = kMatchSpecLenStart + 2 : State Init Marker ++*/ ++ ++static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit) ++{ ++ CLzmaProb *probs = p->probs; ++ ++ unsigned state = p->state; ++ UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3]; ++ unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1; ++ unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1; ++ unsigned lc = p->prop.lc; ++ ++ Byte *dic = p->dic; ++ SizeT dicBufSize = p->dicBufSize; ++ SizeT dicPos = p->dicPos; ++ ++ UInt32 processedPos = p->processedPos; ++ UInt32 checkDicSize = p->checkDicSize; ++ unsigned len = 0; ++ ++ const Byte *buf = p->buf; ++ UInt32 range = p->range; ++ UInt32 code = p->code; ++ ++ do ++ { ++ CLzmaProb *prob; ++ UInt32 bound; ++ unsigned ttt; ++ unsigned posState = processedPos & pbMask; ++ ++ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0(prob) ++ { ++ unsigned symbol; ++ UPDATE_0(prob); ++ prob = probs + Literal; ++ if (checkDicSize != 0 || processedPos != 0) ++ prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + ++ (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc)))); ++ ++ if (state < kNumLitStates) ++ { ++ state -= (state < 4) ? state : 3; ++ symbol = 1; ++ do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100); ++ } ++ else ++ { ++ unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ unsigned offs = 0x100; ++ state -= (state < 10) ? 3 : 6; ++ symbol = 1; ++ do ++ { ++ unsigned bit; ++ CLzmaProb *probLit; ++ matchByte <<= 1; ++ bit = (matchByte & offs); ++ probLit = prob + offs + bit + symbol; ++ GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit) ++ } ++ while (symbol < 0x100); ++ } ++ dic[dicPos++] = (Byte)symbol; ++ processedPos++; ++ continue; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ prob = probs + IsRep + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ state += kNumStates; ++ prob = probs + LenCoder; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ if (checkDicSize == 0 && processedPos == 0) ++ return SZ_ERROR_DATA; ++ prob = probs + IsRepG0 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ dicPos++; ++ processedPos++; ++ state = state < kNumLitStates ? 9 : 11; ++ continue; ++ } ++ UPDATE_1(prob); ++ } ++ else ++ { ++ UInt32 distance; ++ UPDATE_1(prob); ++ prob = probs + IsRepG1 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ distance = rep1; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ prob = probs + IsRepG2 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ distance = rep2; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ distance = rep3; ++ rep3 = rep2; ++ } ++ rep2 = rep1; ++ } ++ rep1 = rep0; ++ rep0 = distance; ++ } ++ state = state < kNumLitStates ? 8 : 11; ++ prob = probs + RepLenCoder; ++ } ++ { ++ unsigned limit, offset; ++ CLzmaProb *probLen = prob + LenChoice; ++ IF_BIT_0(probLen) ++ { ++ UPDATE_0(probLen); ++ probLen = prob + LenLow + (posState << kLenNumLowBits); ++ offset = 0; ++ limit = (1 << kLenNumLowBits); ++ } ++ else ++ { ++ UPDATE_1(probLen); ++ probLen = prob + LenChoice2; ++ IF_BIT_0(probLen) ++ { ++ UPDATE_0(probLen); ++ probLen = prob + LenMid + (posState << kLenNumMidBits); ++ offset = kLenNumLowSymbols; ++ limit = (1 << kLenNumMidBits); ++ } ++ else ++ { ++ UPDATE_1(probLen); ++ probLen = prob + LenHigh; ++ offset = kLenNumLowSymbols + kLenNumMidSymbols; ++ limit = (1 << kLenNumHighBits); ++ } ++ } ++ TREE_DECODE(probLen, limit, len); ++ len += offset; ++ } ++ ++ if (state >= kNumStates) ++ { ++ UInt32 distance; ++ prob = probs + PosSlot + ++ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); ++ TREE_6_DECODE(prob, distance); ++ if (distance >= kStartPosModelIndex) ++ { ++ unsigned posSlot = (unsigned)distance; ++ int numDirectBits = (int)(((distance >> 1) - 1)); ++ distance = (2 | (distance & 1)); ++ if (posSlot < kEndPosModelIndex) ++ { ++ distance <<= numDirectBits; ++ prob = probs + SpecPos + distance - posSlot - 1; ++ { ++ UInt32 mask = 1; ++ unsigned i = 1; ++ do ++ { ++ GET_BIT2(prob + i, i, ; , distance |= mask); ++ mask <<= 1; ++ } ++ while (--numDirectBits != 0); ++ } ++ } ++ else ++ { ++ numDirectBits -= kNumAlignBits; ++ do ++ { ++ NORMALIZE ++ range >>= 1; ++ ++ { ++ UInt32 t; ++ code -= range; ++ t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */ ++ distance = (distance << 1) + (t + 1); ++ code += range & t; ++ } ++ /* ++ distance <<= 1; ++ if (code >= range) ++ { ++ code -= range; ++ distance |= 1; ++ } ++ */ ++ } ++ while (--numDirectBits != 0); ++ prob = probs + Align; ++ distance <<= kNumAlignBits; ++ { ++ unsigned i = 1; ++ GET_BIT2(prob + i, i, ; , distance |= 1); ++ GET_BIT2(prob + i, i, ; , distance |= 2); ++ GET_BIT2(prob + i, i, ; , distance |= 4); ++ GET_BIT2(prob + i, i, ; , distance |= 8); ++ } ++ if (distance == (UInt32)0xFFFFFFFF) ++ { ++ len += kMatchSpecLenStart; ++ state -= kNumStates; ++ break; ++ } ++ } ++ } ++ rep3 = rep2; ++ rep2 = rep1; ++ rep1 = rep0; ++ rep0 = distance + 1; ++ if (checkDicSize == 0) ++ { ++ if (distance >= processedPos) ++ return SZ_ERROR_DATA; ++ } ++ else if (distance >= checkDicSize) ++ return SZ_ERROR_DATA; ++ state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3; ++ } ++ ++ len += kMatchMinLen; ++ ++ if (limit == dicPos) ++ return SZ_ERROR_DATA; ++ { ++ SizeT rem = limit - dicPos; ++ unsigned curLen = ((rem < len) ? (unsigned)rem : len); ++ SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0); ++ ++ processedPos += curLen; ++ ++ len -= curLen; ++ if (pos + curLen <= dicBufSize) ++ { ++ Byte *dest = dic + dicPos; ++ ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos; ++ const Byte *lim = dest + curLen; ++ dicPos += curLen; ++ do ++ *(dest) = (Byte)*(dest + src); ++ while (++dest != lim); ++ } ++ else ++ { ++ do ++ { ++ dic[dicPos++] = dic[pos]; ++ if (++pos == dicBufSize) ++ pos = 0; ++ } ++ while (--curLen != 0); ++ } ++ } ++ } ++ } ++ while (dicPos < limit && buf < bufLimit); ++ NORMALIZE; ++ p->buf = buf; ++ p->range = range; ++ p->code = code; ++ p->remainLen = len; ++ p->dicPos = dicPos; ++ p->processedPos = processedPos; ++ p->reps[0] = rep0; ++ p->reps[1] = rep1; ++ p->reps[2] = rep2; ++ p->reps[3] = rep3; ++ p->state = state; ++ ++ return SZ_OK; ++} ++ ++static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit) ++{ ++ if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart) ++ { ++ Byte *dic = p->dic; ++ SizeT dicPos = p->dicPos; ++ SizeT dicBufSize = p->dicBufSize; ++ unsigned len = p->remainLen; ++ UInt32 rep0 = p->reps[0]; ++ if (limit - dicPos < len) ++ len = (unsigned)(limit - dicPos); ++ ++ if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len) ++ p->checkDicSize = p->prop.dicSize; ++ ++ p->processedPos += len; ++ p->remainLen -= len; ++ while (len-- != 0) ++ { ++ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ dicPos++; ++ } ++ p->dicPos = dicPos; ++ } ++} ++ ++static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit) ++{ ++ do ++ { ++ SizeT limit2 = limit; ++ if (p->checkDicSize == 0) ++ { ++ UInt32 rem = p->prop.dicSize - p->processedPos; ++ if (limit - p->dicPos > rem) ++ limit2 = p->dicPos + rem; ++ } ++ RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit)); ++ if (p->processedPos >= p->prop.dicSize) ++ p->checkDicSize = p->prop.dicSize; ++ LzmaDec_WriteRem(p, limit); ++ } ++ while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart); ++ ++ if (p->remainLen > kMatchSpecLenStart) ++ { ++ p->remainLen = kMatchSpecLenStart; ++ } ++ return 0; ++} ++ ++typedef enum ++{ ++ DUMMY_ERROR, /* unexpected end of input stream */ ++ DUMMY_LIT, ++ DUMMY_MATCH, ++ DUMMY_REP ++} ELzmaDummy; ++ ++static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize) ++{ ++ UInt32 range = p->range; ++ UInt32 code = p->code; ++ const Byte *bufLimit = buf + inSize; ++ CLzmaProb *probs = p->probs; ++ unsigned state = p->state; ++ ELzmaDummy res; ++ ++ { ++ CLzmaProb *prob; ++ UInt32 bound; ++ unsigned ttt; ++ unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1); ++ ++ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK ++ ++ /* if (bufLimit - buf >= 7) return DUMMY_LIT; */ ++ ++ prob = probs + Literal; ++ if (p->checkDicSize != 0 || p->processedPos != 0) ++ prob += (LZMA_LIT_SIZE * ++ ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + ++ (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc)))); ++ ++ if (state < kNumLitStates) ++ { ++ unsigned symbol = 1; ++ do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100); ++ } ++ else ++ { ++ unsigned matchByte = p->dic[p->dicPos - p->reps[0] + ++ ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)]; ++ unsigned offs = 0x100; ++ unsigned symbol = 1; ++ do ++ { ++ unsigned bit; ++ CLzmaProb *probLit; ++ matchByte <<= 1; ++ bit = (matchByte & offs); ++ probLit = prob + offs + bit + symbol; ++ GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit) ++ } ++ while (symbol < 0x100); ++ } ++ res = DUMMY_LIT; ++ } ++ else ++ { ++ unsigned len; ++ UPDATE_1_CHECK; ++ ++ prob = probs + IsRep + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ state = 0; ++ prob = probs + LenCoder; ++ res = DUMMY_MATCH; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ res = DUMMY_REP; ++ prob = probs + IsRepG0 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ NORMALIZE_CHECK; ++ return DUMMY_REP; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ } ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ prob = probs + IsRepG1 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ prob = probs + IsRepG2 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ } ++ } ++ } ++ state = kNumStates; ++ prob = probs + RepLenCoder; ++ } ++ { ++ unsigned limit, offset; ++ CLzmaProb *probLen = prob + LenChoice; ++ IF_BIT_0_CHECK(probLen) ++ { ++ UPDATE_0_CHECK; ++ probLen = prob + LenLow + (posState << kLenNumLowBits); ++ offset = 0; ++ limit = 1 << kLenNumLowBits; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ probLen = prob + LenChoice2; ++ IF_BIT_0_CHECK(probLen) ++ { ++ UPDATE_0_CHECK; ++ probLen = prob + LenMid + (posState << kLenNumMidBits); ++ offset = kLenNumLowSymbols; ++ limit = 1 << kLenNumMidBits; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ probLen = prob + LenHigh; ++ offset = kLenNumLowSymbols + kLenNumMidSymbols; ++ limit = 1 << kLenNumHighBits; ++ } ++ } ++ TREE_DECODE_CHECK(probLen, limit, len); ++ len += offset; ++ } ++ ++ if (state < 4) ++ { ++ unsigned posSlot; ++ prob = probs + PosSlot + ++ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << ++ kNumPosSlotBits); ++ TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot); ++ if (posSlot >= kStartPosModelIndex) ++ { ++ int numDirectBits = ((posSlot >> 1) - 1); ++ ++ /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */ ++ ++ if (posSlot < kEndPosModelIndex) ++ { ++ prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1; ++ } ++ else ++ { ++ numDirectBits -= kNumAlignBits; ++ do ++ { ++ NORMALIZE_CHECK ++ range >>= 1; ++ code -= range & (((code - range) >> 31) - 1); ++ /* if (code >= range) code -= range; */ ++ } ++ while (--numDirectBits != 0); ++ prob = probs + Align; ++ numDirectBits = kNumAlignBits; ++ } ++ { ++ unsigned i = 1; ++ do ++ { ++ GET_BIT_CHECK(prob + i, i); ++ } ++ while (--numDirectBits != 0); ++ } ++ } ++ } ++ } ++ } ++ NORMALIZE_CHECK; ++ return res; ++} ++ ++ ++static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data) ++{ ++ p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]); ++ p->range = 0xFFFFFFFF; ++ p->needFlush = 0; ++} ++ ++void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) ++{ ++ p->needFlush = 1; ++ p->remainLen = 0; ++ p->tempBufSize = 0; ++ ++ if (initDic) ++ { ++ p->processedPos = 0; ++ p->checkDicSize = 0; ++ p->needInitState = 1; ++ } ++ if (initState) ++ p->needInitState = 1; ++} ++ ++void LzmaDec_Init(CLzmaDec *p) ++{ ++ p->dicPos = 0; ++ LzmaDec_InitDicAndState(p, True, True); ++} ++ ++static void LzmaDec_InitStateReal(CLzmaDec *p) ++{ ++ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp)); ++ UInt32 i; ++ CLzmaProb *probs = p->probs; ++ for (i = 0; i < numProbs; i++) ++ probs[i] = kBitModelTotal >> 1; ++ p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1; ++ p->state = 0; ++ p->needInitState = 0; ++} ++ ++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, ++ ELzmaFinishMode finishMode, ELzmaStatus *status) ++{ ++ SizeT inSize = *srcLen; ++ (*srcLen) = 0; ++ LzmaDec_WriteRem(p, dicLimit); ++ ++ *status = LZMA_STATUS_NOT_SPECIFIED; ++ ++ while (p->remainLen != kMatchSpecLenStart) ++ { ++ int checkEndMarkNow; ++ ++ if (p->needFlush != 0) ++ { ++ for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--) ++ p->tempBuf[p->tempBufSize++] = *src++; ++ if (p->tempBufSize < RC_INIT_SIZE) ++ { ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (p->tempBuf[0] != 0) ++ return SZ_ERROR_DATA; ++ ++ LzmaDec_InitRc(p, p->tempBuf); ++ p->tempBufSize = 0; ++ } ++ ++ checkEndMarkNow = 0; ++ if (p->dicPos >= dicLimit) ++ { ++ if (p->remainLen == 0 && p->code == 0) ++ { ++ *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK; ++ return SZ_OK; ++ } ++ if (finishMode == LZMA_FINISH_ANY) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_OK; ++ } ++ if (p->remainLen != 0) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ checkEndMarkNow = 1; ++ } ++ ++ if (p->needInitState) ++ LzmaDec_InitStateReal(p); ++ ++ if (p->tempBufSize == 0) ++ { ++ SizeT processed; ++ const Byte *bufLimit; ++ if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) ++ { ++ int dummyRes = LzmaDec_TryDummy(p, src, inSize); ++ if (dummyRes == DUMMY_ERROR) ++ { ++ memcpy(p->tempBuf, src, inSize); ++ p->tempBufSize = (unsigned)inSize; ++ (*srcLen) += inSize; ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ bufLimit = src; ++ } ++ else ++ bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX; ++ p->buf = src; ++ if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0) ++ return SZ_ERROR_DATA; ++ processed = (SizeT)(p->buf - src); ++ (*srcLen) += processed; ++ src += processed; ++ inSize -= processed; ++ } ++ else ++ { ++ unsigned rem = p->tempBufSize, lookAhead = 0; ++ while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize) ++ p->tempBuf[rem++] = src[lookAhead++]; ++ p->tempBufSize = rem; ++ if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) ++ { ++ int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem); ++ if (dummyRes == DUMMY_ERROR) ++ { ++ (*srcLen) += lookAhead; ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ } ++ p->buf = p->tempBuf; ++ if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0) ++ return SZ_ERROR_DATA; ++ lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf)); ++ (*srcLen) += lookAhead; ++ src += lookAhead; ++ inSize -= lookAhead; ++ p->tempBufSize = 0; ++ } ++ } ++ if (p->code == 0) ++ *status = LZMA_STATUS_FINISHED_WITH_MARK; ++ return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; ++} ++ ++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) ++{ ++ SizeT outSize = *destLen; ++ SizeT inSize = *srcLen; ++ *srcLen = *destLen = 0; ++ for (;;) ++ { ++ SizeT inSizeCur = inSize, outSizeCur, dicPos; ++ ELzmaFinishMode curFinishMode; ++ SRes res; ++ if (p->dicPos == p->dicBufSize) ++ p->dicPos = 0; ++ dicPos = p->dicPos; ++ if (outSize > p->dicBufSize - dicPos) ++ { ++ outSizeCur = p->dicBufSize; ++ curFinishMode = LZMA_FINISH_ANY; ++ } ++ else ++ { ++ outSizeCur = dicPos + outSize; ++ curFinishMode = finishMode; ++ } ++ ++ res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); ++ src += inSizeCur; ++ inSize -= inSizeCur; ++ *srcLen += inSizeCur; ++ outSizeCur = p->dicPos - dicPos; ++ memcpy(dest, p->dic + dicPos, outSizeCur); ++ dest += outSizeCur; ++ outSize -= outSizeCur; ++ *destLen += outSizeCur; ++ if (res != 0) ++ return res; ++ if (outSizeCur == 0 || outSize == 0) ++ return SZ_OK; ++ } ++} ++ ++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->probs); ++ p->probs = 0; ++} ++ ++static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->dic); ++ p->dic = 0; ++} ++ ++void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ LzmaDec_FreeProbs(p, alloc); ++ LzmaDec_FreeDict(p, alloc); ++} ++ ++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) ++{ ++ UInt32 dicSize; ++ Byte d; ++ ++ if (size < LZMA_PROPS_SIZE) ++ return SZ_ERROR_UNSUPPORTED; ++ else ++ dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24); ++ ++ if (dicSize < LZMA_DIC_MIN) ++ dicSize = LZMA_DIC_MIN; ++ p->dicSize = dicSize; ++ ++ d = data[0]; ++ if (d >= (9 * 5 * 5)) ++ return SZ_ERROR_UNSUPPORTED; ++ ++ p->lc = d % 9; ++ d /= 9; ++ p->pb = d / 5; ++ p->lp = d % 5; ++ ++ return SZ_OK; ++} ++ ++static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc) ++{ ++ UInt32 numProbs = LzmaProps_GetNumProbs(propNew); ++ if (p->probs == 0 || numProbs != p->numProbs) ++ { ++ LzmaDec_FreeProbs(p, alloc); ++ p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb)); ++ p->numProbs = numProbs; ++ if (p->probs == 0) ++ return SZ_ERROR_MEM; ++ } ++ return SZ_OK; ++} ++ ++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++{ ++ CLzmaProps propNew; ++ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); ++ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); ++ p->prop = propNew; ++ return SZ_OK; ++} ++ ++SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++{ ++ CLzmaProps propNew; ++ SizeT dicBufSize; ++ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); ++ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); ++ dicBufSize = propNew.dicSize; ++ if (p->dic == 0 || dicBufSize != p->dicBufSize) ++ { ++ LzmaDec_FreeDict(p, alloc); ++ p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); ++ if (p->dic == 0) ++ { ++ LzmaDec_FreeProbs(p, alloc); ++ return SZ_ERROR_MEM; ++ } ++ } ++ p->dicBufSize = dicBufSize; ++ p->prop = propNew; ++ return SZ_OK; ++} ++ ++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ++ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, ++ ELzmaStatus *status, ISzAlloc *alloc) ++{ ++ CLzmaDec p; ++ SRes res; ++ SizeT inSize = *srcLen; ++ SizeT outSize = *destLen; ++ *srcLen = *destLen = 0; ++ if (inSize < RC_INIT_SIZE) ++ return SZ_ERROR_INPUT_EOF; ++ ++ LzmaDec_Construct(&p); ++ res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc); ++ if (res != 0) ++ return res; ++ p.dic = dest; ++ p.dicBufSize = outSize; ++ ++ LzmaDec_Init(&p); ++ ++ *srcLen = inSize; ++ res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status); ++ ++ if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT) ++ res = SZ_ERROR_INPUT_EOF; ++ ++ (*destLen) = p.dicPos; ++ LzmaDec_FreeProbs(&p, alloc); ++ return res; ++} +--- /dev/null ++++ b/lib/lzma/LzmaEnc.c +@@ -0,0 +1,2271 @@ ++/* LzmaEnc.c -- LZMA Encoder ++2009-11-24 : Igor Pavlov : Public domain */ ++ ++#include ++ ++/* #define SHOW_STAT */ ++/* #define SHOW_STAT2 */ ++ ++#if defined(SHOW_STAT) || defined(SHOW_STAT2) ++#include ++#endif ++ ++#include "LzmaEnc.h" ++ ++/* disable MT */ ++#define _7ZIP_ST ++ ++#include "LzFind.h" ++#ifndef _7ZIP_ST ++#include "LzFindMt.h" ++#endif ++ ++#ifdef SHOW_STAT ++static int ttt = 0; ++#endif ++ ++#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1) ++ ++#define kBlockSize (9 << 10) ++#define kUnpackBlockSize (1 << 18) ++#define kMatchArraySize (1 << 21) ++#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX) ++ ++#define kNumMaxDirectBits (31) ++ ++#define kNumTopBits 24 ++#define kTopValue ((UInt32)1 << kNumTopBits) ++ ++#define kNumBitModelTotalBits 11 ++#define kBitModelTotal (1 << kNumBitModelTotalBits) ++#define kNumMoveBits 5 ++#define kProbInitValue (kBitModelTotal >> 1) ++ ++#define kNumMoveReducingBits 4 ++#define kNumBitPriceShiftBits 4 ++#define kBitPrice (1 << kNumBitPriceShiftBits) ++ ++void LzmaEncProps_Init(CLzmaEncProps *p) ++{ ++ p->level = 5; ++ p->dictSize = p->mc = 0; ++ p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1; ++ p->writeEndMark = 0; ++} ++ ++void LzmaEncProps_Normalize(CLzmaEncProps *p) ++{ ++ int level = p->level; ++ if (level < 0) level = 5; ++ p->level = level; ++ if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26))); ++ if (p->lc < 0) p->lc = 3; ++ if (p->lp < 0) p->lp = 0; ++ if (p->pb < 0) p->pb = 2; ++ if (p->algo < 0) p->algo = (level < 5 ? 0 : 1); ++ if (p->fb < 0) p->fb = (level < 7 ? 32 : 64); ++ if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1); ++ if (p->numHashBytes < 0) p->numHashBytes = 4; ++ if (p->mc == 0) p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1); ++ if (p->numThreads < 0) ++ p->numThreads = ++ #ifndef _7ZIP_ST ++ ((p->btMode && p->algo) ? 2 : 1); ++ #else ++ 1; ++ #endif ++} ++ ++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) ++{ ++ CLzmaEncProps props = *props2; ++ LzmaEncProps_Normalize(&props); ++ return props.dictSize; ++} ++ ++/* #define LZMA_LOG_BSR */ ++/* Define it for Intel's CPU */ ++ ++ ++#ifdef LZMA_LOG_BSR ++ ++#define kDicLogSizeMaxCompress 30 ++ ++#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } ++ ++UInt32 GetPosSlot1(UInt32 pos) ++{ ++ UInt32 res; ++ BSR2_RET(pos, res); ++ return res; ++} ++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } ++#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); } ++ ++#else ++ ++#define kNumLogBits (9 + (int)sizeof(size_t) / 2) ++#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) ++ ++void LzmaEnc_FastPosInit(Byte *g_FastPos) ++{ ++ int c = 2, slotFast; ++ g_FastPos[0] = 0; ++ g_FastPos[1] = 1; ++ ++ for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++) ++ { ++ UInt32 k = (1 << ((slotFast >> 1) - 1)); ++ UInt32 j; ++ for (j = 0; j < k; j++, c++) ++ g_FastPos[c] = (Byte)slotFast; ++ } ++} ++ ++#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \ ++ (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \ ++ res = p->g_FastPos[pos >> i] + (i * 2); } ++/* ++#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \ ++ p->g_FastPos[pos >> 6] + 12 : \ ++ p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; } ++*/ ++ ++#define GetPosSlot1(pos) p->g_FastPos[pos] ++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } ++#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); } ++ ++#endif ++ ++ ++#define LZMA_NUM_REPS 4 ++ ++typedef unsigned CState; ++ ++typedef struct ++{ ++ UInt32 price; ++ ++ CState state; ++ int prev1IsChar; ++ int prev2; ++ ++ UInt32 posPrev2; ++ UInt32 backPrev2; ++ ++ UInt32 posPrev; ++ UInt32 backPrev; ++ UInt32 backs[LZMA_NUM_REPS]; ++} COptimal; ++ ++#define kNumOpts (1 << 12) ++ ++#define kNumLenToPosStates 4 ++#define kNumPosSlotBits 6 ++#define kDicLogSizeMin 0 ++#define kDicLogSizeMax 32 ++#define kDistTableSizeMax (kDicLogSizeMax * 2) ++ ++ ++#define kNumAlignBits 4 ++#define kAlignTableSize (1 << kNumAlignBits) ++#define kAlignMask (kAlignTableSize - 1) ++ ++#define kStartPosModelIndex 4 ++#define kEndPosModelIndex 14 ++#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex) ++ ++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) ++ ++#ifdef _LZMA_PROB32 ++#define CLzmaProb UInt32 ++#else ++#define CLzmaProb UInt16 ++#endif ++ ++#define LZMA_PB_MAX 4 ++#define LZMA_LC_MAX 8 ++#define LZMA_LP_MAX 4 ++ ++#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX) ++ ++ ++#define kLenNumLowBits 3 ++#define kLenNumLowSymbols (1 << kLenNumLowBits) ++#define kLenNumMidBits 3 ++#define kLenNumMidSymbols (1 << kLenNumMidBits) ++#define kLenNumHighBits 8 ++#define kLenNumHighSymbols (1 << kLenNumHighBits) ++ ++#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) ++ ++#define LZMA_MATCH_LEN_MIN 2 ++#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1) ++ ++#define kNumStates 12 ++ ++typedef struct ++{ ++ CLzmaProb choice; ++ CLzmaProb choice2; ++ CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits]; ++ CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits]; ++ CLzmaProb high[kLenNumHighSymbols]; ++} CLenEnc; ++ ++typedef struct ++{ ++ CLenEnc p; ++ UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal]; ++ UInt32 tableSize; ++ UInt32 counters[LZMA_NUM_PB_STATES_MAX]; ++} CLenPriceEnc; ++ ++typedef struct ++{ ++ UInt32 range; ++ Byte cache; ++ UInt64 low; ++ UInt64 cacheSize; ++ Byte *buf; ++ Byte *bufLim; ++ Byte *bufBase; ++ ISeqOutStream *outStream; ++ UInt64 processed; ++ SRes res; ++} CRangeEnc; ++ ++typedef struct ++{ ++ CLzmaProb *litProbs; ++ ++ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ CLzmaProb isRep[kNumStates]; ++ CLzmaProb isRepG0[kNumStates]; ++ CLzmaProb isRepG1[kNumStates]; ++ CLzmaProb isRepG2[kNumStates]; ++ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ ++ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; ++ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; ++ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; ++ ++ CLenPriceEnc lenEnc; ++ CLenPriceEnc repLenEnc; ++ ++ UInt32 reps[LZMA_NUM_REPS]; ++ UInt32 state; ++} CSaveState; ++ ++typedef struct ++{ ++ IMatchFinder matchFinder; ++ void *matchFinderObj; ++ ++ #ifndef _7ZIP_ST ++ Bool mtMode; ++ CMatchFinderMt matchFinderMt; ++ #endif ++ ++ CMatchFinder matchFinderBase; ++ ++ #ifndef _7ZIP_ST ++ Byte pad[128]; ++ #endif ++ ++ UInt32 optimumEndIndex; ++ UInt32 optimumCurrentIndex; ++ ++ UInt32 longestMatchLength; ++ UInt32 numPairs; ++ UInt32 numAvail; ++ COptimal opt[kNumOpts]; ++ ++ #ifndef LZMA_LOG_BSR ++ Byte g_FastPos[1 << kNumLogBits]; ++ #endif ++ ++ UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits]; ++ UInt32 matches[LZMA_MATCH_LEN_MAX * 2 + 2 + 1]; ++ UInt32 numFastBytes; ++ UInt32 additionalOffset; ++ UInt32 reps[LZMA_NUM_REPS]; ++ UInt32 state; ++ ++ UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax]; ++ UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances]; ++ UInt32 alignPrices[kAlignTableSize]; ++ UInt32 alignPriceCount; ++ ++ UInt32 distTableSize; ++ ++ unsigned lc, lp, pb; ++ unsigned lpMask, pbMask; ++ ++ CLzmaProb *litProbs; ++ ++ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ CLzmaProb isRep[kNumStates]; ++ CLzmaProb isRepG0[kNumStates]; ++ CLzmaProb isRepG1[kNumStates]; ++ CLzmaProb isRepG2[kNumStates]; ++ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ ++ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; ++ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; ++ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; ++ ++ CLenPriceEnc lenEnc; ++ CLenPriceEnc repLenEnc; ++ ++ unsigned lclp; ++ ++ Bool fastMode; ++ ++ CRangeEnc rc; ++ ++ Bool writeEndMark; ++ UInt64 nowPos64; ++ UInt32 matchPriceCount; ++ Bool finished; ++ Bool multiThread; ++ ++ SRes result; ++ UInt32 dictSize; ++ UInt32 matchFinderCycles; ++ ++ int needInit; ++ ++ CSaveState saveState; ++} CLzmaEnc; ++ ++void LzmaEnc_SaveState(CLzmaEncHandle pp) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ CSaveState *dest = &p->saveState; ++ int i; ++ dest->lenEnc = p->lenEnc; ++ dest->repLenEnc = p->repLenEnc; ++ dest->state = p->state; ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); ++ memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); ++ } ++ for (i = 0; i < kNumLenToPosStates; i++) ++ memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); ++ memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); ++ memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); ++ memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); ++ memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); ++ memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); ++ memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); ++ memcpy(dest->reps, p->reps, sizeof(p->reps)); ++ memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb)); ++} ++ ++void LzmaEnc_RestoreState(CLzmaEncHandle pp) ++{ ++ CLzmaEnc *dest = (CLzmaEnc *)pp; ++ const CSaveState *p = &dest->saveState; ++ int i; ++ dest->lenEnc = p->lenEnc; ++ dest->repLenEnc = p->repLenEnc; ++ dest->state = p->state; ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); ++ memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); ++ } ++ for (i = 0; i < kNumLenToPosStates; i++) ++ memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); ++ memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); ++ memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); ++ memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); ++ memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); ++ memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); ++ memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); ++ memcpy(dest->reps, p->reps, sizeof(p->reps)); ++ memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb)); ++} ++ ++SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ CLzmaEncProps props = *props2; ++ LzmaEncProps_Normalize(&props); ++ ++ if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX || ++ props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30)) ++ return SZ_ERROR_PARAM; ++ p->dictSize = props.dictSize; ++ p->matchFinderCycles = props.mc; ++ { ++ unsigned fb = props.fb; ++ if (fb < 5) ++ fb = 5; ++ if (fb > LZMA_MATCH_LEN_MAX) ++ fb = LZMA_MATCH_LEN_MAX; ++ p->numFastBytes = fb; ++ } ++ p->lc = props.lc; ++ p->lp = props.lp; ++ p->pb = props.pb; ++ p->fastMode = (props.algo == 0); ++ p->matchFinderBase.btMode = props.btMode; ++ { ++ UInt32 numHashBytes = 4; ++ if (props.btMode) ++ { ++ if (props.numHashBytes < 2) ++ numHashBytes = 2; ++ else if (props.numHashBytes < 4) ++ numHashBytes = props.numHashBytes; ++ } ++ p->matchFinderBase.numHashBytes = numHashBytes; ++ } ++ ++ p->matchFinderBase.cutValue = props.mc; ++ ++ p->writeEndMark = props.writeEndMark; ++ ++ #ifndef _7ZIP_ST ++ /* ++ if (newMultiThread != _multiThread) ++ { ++ ReleaseMatchFinder(); ++ _multiThread = newMultiThread; ++ } ++ */ ++ p->multiThread = (props.numThreads > 1); ++ #endif ++ ++ return SZ_OK; ++} ++ ++static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 4, 5}; ++static const int kMatchNextStates[kNumStates] = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10}; ++static const int kRepNextStates[kNumStates] = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11}; ++static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11}; ++ ++#define IsCharState(s) ((s) < 7) ++ ++#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1) ++ ++#define kInfinityPrice (1 << 30) ++ ++static void RangeEnc_Construct(CRangeEnc *p) ++{ ++ p->outStream = 0; ++ p->bufBase = 0; ++} ++ ++#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize) ++ ++#define RC_BUF_SIZE (1 << 16) ++static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc) ++{ ++ if (p->bufBase == 0) ++ { ++ p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE); ++ if (p->bufBase == 0) ++ return 0; ++ p->bufLim = p->bufBase + RC_BUF_SIZE; ++ } ++ return 1; ++} ++ ++static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->bufBase); ++ p->bufBase = 0; ++} ++ ++static void RangeEnc_Init(CRangeEnc *p) ++{ ++ /* Stream.Init(); */ ++ p->low = 0; ++ p->range = 0xFFFFFFFF; ++ p->cacheSize = 1; ++ p->cache = 0; ++ ++ p->buf = p->bufBase; ++ ++ p->processed = 0; ++ p->res = SZ_OK; ++} ++ ++static void RangeEnc_FlushStream(CRangeEnc *p) ++{ ++ size_t num; ++ if (p->res != SZ_OK) ++ return; ++ num = p->buf - p->bufBase; ++ if (num != p->outStream->Write(p->outStream, p->bufBase, num)) ++ p->res = SZ_ERROR_WRITE; ++ p->processed += num; ++ p->buf = p->bufBase; ++} ++ ++static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p) ++{ ++ if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0) ++ { ++ Byte temp = p->cache; ++ do ++ { ++ Byte *buf = p->buf; ++ *buf++ = (Byte)(temp + (Byte)(p->low >> 32)); ++ p->buf = buf; ++ if (buf == p->bufLim) ++ RangeEnc_FlushStream(p); ++ temp = 0xFF; ++ } ++ while (--p->cacheSize != 0); ++ p->cache = (Byte)((UInt32)p->low >> 24); ++ } ++ p->cacheSize++; ++ p->low = (UInt32)p->low << 8; ++} ++ ++static void RangeEnc_FlushData(CRangeEnc *p) ++{ ++ int i; ++ for (i = 0; i < 5; i++) ++ RangeEnc_ShiftLow(p); ++} ++ ++static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits) ++{ ++ do ++ { ++ p->range >>= 1; ++ p->low += p->range & (0 - ((value >> --numBits) & 1)); ++ if (p->range < kTopValue) ++ { ++ p->range <<= 8; ++ RangeEnc_ShiftLow(p); ++ } ++ } ++ while (numBits != 0); ++} ++ ++static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol) ++{ ++ UInt32 ttt = *prob; ++ UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt; ++ if (symbol == 0) ++ { ++ p->range = newBound; ++ ttt += (kBitModelTotal - ttt) >> kNumMoveBits; ++ } ++ else ++ { ++ p->low += newBound; ++ p->range -= newBound; ++ ttt -= ttt >> kNumMoveBits; ++ } ++ *prob = (CLzmaProb)ttt; ++ if (p->range < kTopValue) ++ { ++ p->range <<= 8; ++ RangeEnc_ShiftLow(p); ++ } ++} ++ ++static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol) ++{ ++ symbol |= 0x100; ++ do ++ { ++ RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1); ++ symbol <<= 1; ++ } ++ while (symbol < 0x10000); ++} ++ ++static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte) ++{ ++ UInt32 offs = 0x100; ++ symbol |= 0x100; ++ do ++ { ++ matchByte <<= 1; ++ RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1); ++ symbol <<= 1; ++ offs &= ~(matchByte ^ symbol); ++ } ++ while (symbol < 0x10000); ++} ++ ++void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) ++{ ++ UInt32 i; ++ for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) ++ { ++ const int kCyclesBits = kNumBitPriceShiftBits; ++ UInt32 w = i; ++ UInt32 bitCount = 0; ++ int j; ++ for (j = 0; j < kCyclesBits; j++) ++ { ++ w = w * w; ++ bitCount <<= 1; ++ while (w >= ((UInt32)1 << 16)) ++ { ++ w >>= 1; ++ bitCount++; ++ } ++ } ++ ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount); ++ } ++} ++ ++ ++#define GET_PRICE(prob, symbol) \ ++ p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; ++ ++#define GET_PRICEa(prob, symbol) \ ++ ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; ++ ++#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits] ++#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] ++ ++#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits] ++#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] ++ ++static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ symbol |= 0x100; ++ do ++ { ++ price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1); ++ symbol <<= 1; ++ } ++ while (symbol < 0x10000); ++ return price; ++} ++ ++static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ UInt32 offs = 0x100; ++ symbol |= 0x100; ++ do ++ { ++ matchByte <<= 1; ++ price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1); ++ symbol <<= 1; ++ offs &= ~(matchByte ^ symbol); ++ } ++ while (symbol < 0x10000); ++ return price; ++} ++ ++ ++static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) ++{ ++ UInt32 m = 1; ++ int i; ++ for (i = numBitLevels; i != 0;) ++ { ++ UInt32 bit; ++ i--; ++ bit = (symbol >> i) & 1; ++ RangeEnc_EncodeBit(rc, probs + m, bit); ++ m = (m << 1) | bit; ++ } ++} ++ ++static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) ++{ ++ UInt32 m = 1; ++ int i; ++ for (i = 0; i < numBitLevels; i++) ++ { ++ UInt32 bit = symbol & 1; ++ RangeEnc_EncodeBit(rc, probs + m, bit); ++ m = (m << 1) | bit; ++ symbol >>= 1; ++ } ++} ++ ++static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ symbol |= (1 << numBitLevels); ++ while (symbol != 1) ++ { ++ price += GET_PRICEa(probs[symbol >> 1], symbol & 1); ++ symbol >>= 1; ++ } ++ return price; ++} ++ ++static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ UInt32 m = 1; ++ int i; ++ for (i = numBitLevels; i != 0; i--) ++ { ++ UInt32 bit = symbol & 1; ++ symbol >>= 1; ++ price += GET_PRICEa(probs[m], bit); ++ m = (m << 1) | bit; ++ } ++ return price; ++} ++ ++ ++static void LenEnc_Init(CLenEnc *p) ++{ ++ unsigned i; ++ p->choice = p->choice2 = kProbInitValue; ++ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++) ++ p->low[i] = kProbInitValue; ++ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++) ++ p->mid[i] = kProbInitValue; ++ for (i = 0; i < kLenNumHighSymbols; i++) ++ p->high[i] = kProbInitValue; ++} ++ ++static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState) ++{ ++ if (symbol < kLenNumLowSymbols) ++ { ++ RangeEnc_EncodeBit(rc, &p->choice, 0); ++ RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol); ++ } ++ else ++ { ++ RangeEnc_EncodeBit(rc, &p->choice, 1); ++ if (symbol < kLenNumLowSymbols + kLenNumMidSymbols) ++ { ++ RangeEnc_EncodeBit(rc, &p->choice2, 0); ++ RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols); ++ } ++ else ++ { ++ RangeEnc_EncodeBit(rc, &p->choice2, 1); ++ RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols); ++ } ++ } ++} ++ ++static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices) ++{ ++ UInt32 a0 = GET_PRICE_0a(p->choice); ++ UInt32 a1 = GET_PRICE_1a(p->choice); ++ UInt32 b0 = a1 + GET_PRICE_0a(p->choice2); ++ UInt32 b1 = a1 + GET_PRICE_1a(p->choice2); ++ UInt32 i = 0; ++ for (i = 0; i < kLenNumLowSymbols; i++) ++ { ++ if (i >= numSymbols) ++ return; ++ prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices); ++ } ++ for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++) ++ { ++ if (i >= numSymbols) ++ return; ++ prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices); ++ } ++ for (; i < numSymbols; i++) ++ prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices); ++} ++ ++static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices) ++{ ++ LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices); ++ p->counters[posState] = p->tableSize; ++} ++ ++static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices) ++{ ++ UInt32 posState; ++ for (posState = 0; posState < numPosStates; posState++) ++ LenPriceEnc_UpdateTable(p, posState, ProbPrices); ++} ++ ++static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices) ++{ ++ LenEnc_Encode(&p->p, rc, symbol, posState); ++ if (updatePrice) ++ if (--p->counters[posState] == 0) ++ LenPriceEnc_UpdateTable(p, posState, ProbPrices); ++} ++ ++ ++ ++ ++static void MovePos(CLzmaEnc *p, UInt32 num) ++{ ++ #ifdef SHOW_STAT ++ ttt += num; ++ printf("\n MovePos %d", num); ++ #endif ++ if (num != 0) ++ { ++ p->additionalOffset += num; ++ p->matchFinder.Skip(p->matchFinderObj, num); ++ } ++} ++ ++static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes) ++{ ++ UInt32 lenRes = 0, numPairs; ++ p->numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); ++ numPairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matches); ++ #ifdef SHOW_STAT ++ printf("\n i = %d numPairs = %d ", ttt, numPairs / 2); ++ ttt++; ++ { ++ UInt32 i; ++ for (i = 0; i < numPairs; i += 2) ++ printf("%2d %6d | ", p->matches[i], p->matches[i + 1]); ++ } ++ #endif ++ if (numPairs > 0) ++ { ++ lenRes = p->matches[numPairs - 2]; ++ if (lenRes == p->numFastBytes) ++ { ++ const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ UInt32 distance = p->matches[numPairs - 1] + 1; ++ UInt32 numAvail = p->numAvail; ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ { ++ const Byte *pby2 = pby - distance; ++ for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++); ++ } ++ } ++ } ++ p->additionalOffset++; ++ *numDistancePairsRes = numPairs; ++ return lenRes; ++} ++ ++ ++#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False; ++#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False; ++#define IsShortRep(p) ((p)->backPrev == 0) ++ ++static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState) ++{ ++ return ++ GET_PRICE_0(p->isRepG0[state]) + ++ GET_PRICE_0(p->isRep0Long[state][posState]); ++} ++ ++static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState) ++{ ++ UInt32 price; ++ if (repIndex == 0) ++ { ++ price = GET_PRICE_0(p->isRepG0[state]); ++ price += GET_PRICE_1(p->isRep0Long[state][posState]); ++ } ++ else ++ { ++ price = GET_PRICE_1(p->isRepG0[state]); ++ if (repIndex == 1) ++ price += GET_PRICE_0(p->isRepG1[state]); ++ else ++ { ++ price += GET_PRICE_1(p->isRepG1[state]); ++ price += GET_PRICE(p->isRepG2[state], repIndex - 2); ++ } ++ } ++ return price; ++} ++ ++static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState) ++{ ++ return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] + ++ GetPureRepPrice(p, repIndex, state, posState); ++} ++ ++static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur) ++{ ++ UInt32 posMem = p->opt[cur].posPrev; ++ UInt32 backMem = p->opt[cur].backPrev; ++ p->optimumEndIndex = cur; ++ do ++ { ++ if (p->opt[cur].prev1IsChar) ++ { ++ MakeAsChar(&p->opt[posMem]) ++ p->opt[posMem].posPrev = posMem - 1; ++ if (p->opt[cur].prev2) ++ { ++ p->opt[posMem - 1].prev1IsChar = False; ++ p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2; ++ p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2; ++ } ++ } ++ { ++ UInt32 posPrev = posMem; ++ UInt32 backCur = backMem; ++ ++ backMem = p->opt[posPrev].backPrev; ++ posMem = p->opt[posPrev].posPrev; ++ ++ p->opt[posPrev].backPrev = backCur; ++ p->opt[posPrev].posPrev = cur; ++ cur = posPrev; ++ } ++ } ++ while (cur != 0); ++ *backRes = p->opt[0].backPrev; ++ p->optimumCurrentIndex = p->opt[0].posPrev; ++ return p->optimumCurrentIndex; ++} ++ ++#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300) ++ ++static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes) ++{ ++ UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur; ++ UInt32 matchPrice, repMatchPrice, normalMatchPrice; ++ UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS]; ++ UInt32 *matches; ++ const Byte *data; ++ Byte curByte, matchByte; ++ if (p->optimumEndIndex != p->optimumCurrentIndex) ++ { ++ const COptimal *opt = &p->opt[p->optimumCurrentIndex]; ++ UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex; ++ *backRes = opt->backPrev; ++ p->optimumCurrentIndex = opt->posPrev; ++ return lenRes; ++ } ++ p->optimumCurrentIndex = p->optimumEndIndex = 0; ++ ++ if (p->additionalOffset == 0) ++ mainLen = ReadMatchDistances(p, &numPairs); ++ else ++ { ++ mainLen = p->longestMatchLength; ++ numPairs = p->numPairs; ++ } ++ ++ numAvail = p->numAvail; ++ if (numAvail < 2) ++ { ++ *backRes = (UInt32)(-1); ++ return 1; ++ } ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ repMaxIndex = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 lenTest; ++ const Byte *data2; ++ reps[i] = p->reps[i]; ++ data2 = data - (reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ { ++ repLens[i] = 0; ++ continue; ++ } ++ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); ++ repLens[i] = lenTest; ++ if (lenTest > repLens[repMaxIndex]) ++ repMaxIndex = i; ++ } ++ if (repLens[repMaxIndex] >= p->numFastBytes) ++ { ++ UInt32 lenRes; ++ *backRes = repMaxIndex; ++ lenRes = repLens[repMaxIndex]; ++ MovePos(p, lenRes - 1); ++ return lenRes; ++ } ++ ++ matches = p->matches; ++ if (mainLen >= p->numFastBytes) ++ { ++ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 1); ++ return mainLen; ++ } ++ curByte = *data; ++ matchByte = *(data - (reps[0] + 1)); ++ ++ if (mainLen < 2 && curByte != matchByte && repLens[repMaxIndex] < 2) ++ { ++ *backRes = (UInt32)-1; ++ return 1; ++ } ++ ++ p->opt[0].state = (CState)p->state; ++ ++ posState = (position & p->pbMask); ++ ++ { ++ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); ++ p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) + ++ (!IsCharState(p->state) ? ++ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : ++ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); ++ } ++ ++ MakeAsChar(&p->opt[1]); ++ ++ matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]); ++ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]); ++ ++ if (matchByte == curByte) ++ { ++ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState); ++ if (shortRepPrice < p->opt[1].price) ++ { ++ p->opt[1].price = shortRepPrice; ++ MakeAsShortRep(&p->opt[1]); ++ } ++ } ++ lenEnd = ((mainLen >= repLens[repMaxIndex]) ? mainLen : repLens[repMaxIndex]); ++ ++ if (lenEnd < 2) ++ { ++ *backRes = p->opt[1].backPrev; ++ return 1; ++ } ++ ++ p->opt[1].posPrev = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ p->opt[0].backs[i] = reps[i]; ++ ++ len = lenEnd; ++ do ++ p->opt[len--].price = kInfinityPrice; ++ while (len >= 2); ++ ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 repLen = repLens[i]; ++ UInt32 price; ++ if (repLen < 2) ++ continue; ++ price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState); ++ do ++ { ++ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2]; ++ COptimal *opt = &p->opt[repLen]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = 0; ++ opt->backPrev = i; ++ opt->prev1IsChar = False; ++ } ++ } ++ while (--repLen >= 2); ++ } ++ ++ normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]); ++ ++ len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2); ++ if (len <= mainLen) ++ { ++ UInt32 offs = 0; ++ while (len > matches[offs]) ++ offs += 2; ++ for (; ; len++) ++ { ++ COptimal *opt; ++ UInt32 distance = matches[offs + 1]; ++ ++ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN]; ++ UInt32 lenToPosState = GetLenToPosState(len); ++ if (distance < kNumFullDistances) ++ curAndLenPrice += p->distancesPrices[lenToPosState][distance]; ++ else ++ { ++ UInt32 slot; ++ GetPosSlot2(distance, slot); ++ curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot]; ++ } ++ opt = &p->opt[len]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = 0; ++ opt->backPrev = distance + LZMA_NUM_REPS; ++ opt->prev1IsChar = False; ++ } ++ if (len == matches[offs]) ++ { ++ offs += 2; ++ if (offs == numPairs) ++ break; ++ } ++ } ++ } ++ ++ cur = 0; ++ ++ #ifdef SHOW_STAT2 ++ if (position >= 0) ++ { ++ unsigned i; ++ printf("\n pos = %4X", position); ++ for (i = cur; i <= lenEnd; i++) ++ printf("\nprice[%4X] = %d", position - cur + i, p->opt[i].price); ++ } ++ #endif ++ ++ for (;;) ++ { ++ UInt32 numAvailFull, newLen, numPairs, posPrev, state, posState, startLen; ++ UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice; ++ Bool nextIsChar; ++ Byte curByte, matchByte; ++ const Byte *data; ++ COptimal *curOpt; ++ COptimal *nextOpt; ++ ++ cur++; ++ if (cur == lenEnd) ++ return Backward(p, backRes, cur); ++ ++ newLen = ReadMatchDistances(p, &numPairs); ++ if (newLen >= p->numFastBytes) ++ { ++ p->numPairs = numPairs; ++ p->longestMatchLength = newLen; ++ return Backward(p, backRes, cur); ++ } ++ position++; ++ curOpt = &p->opt[cur]; ++ posPrev = curOpt->posPrev; ++ if (curOpt->prev1IsChar) ++ { ++ posPrev--; ++ if (curOpt->prev2) ++ { ++ state = p->opt[curOpt->posPrev2].state; ++ if (curOpt->backPrev2 < LZMA_NUM_REPS) ++ state = kRepNextStates[state]; ++ else ++ state = kMatchNextStates[state]; ++ } ++ else ++ state = p->opt[posPrev].state; ++ state = kLiteralNextStates[state]; ++ } ++ else ++ state = p->opt[posPrev].state; ++ if (posPrev == cur - 1) ++ { ++ if (IsShortRep(curOpt)) ++ state = kShortRepNextStates[state]; ++ else ++ state = kLiteralNextStates[state]; ++ } ++ else ++ { ++ UInt32 pos; ++ const COptimal *prevOpt; ++ if (curOpt->prev1IsChar && curOpt->prev2) ++ { ++ posPrev = curOpt->posPrev2; ++ pos = curOpt->backPrev2; ++ state = kRepNextStates[state]; ++ } ++ else ++ { ++ pos = curOpt->backPrev; ++ if (pos < LZMA_NUM_REPS) ++ state = kRepNextStates[state]; ++ else ++ state = kMatchNextStates[state]; ++ } ++ prevOpt = &p->opt[posPrev]; ++ if (pos < LZMA_NUM_REPS) ++ { ++ UInt32 i; ++ reps[0] = prevOpt->backs[pos]; ++ for (i = 1; i <= pos; i++) ++ reps[i] = prevOpt->backs[i - 1]; ++ for (; i < LZMA_NUM_REPS; i++) ++ reps[i] = prevOpt->backs[i]; ++ } ++ else ++ { ++ UInt32 i; ++ reps[0] = (pos - LZMA_NUM_REPS); ++ for (i = 1; i < LZMA_NUM_REPS; i++) ++ reps[i] = prevOpt->backs[i - 1]; ++ } ++ } ++ curOpt->state = (CState)state; ++ ++ curOpt->backs[0] = reps[0]; ++ curOpt->backs[1] = reps[1]; ++ curOpt->backs[2] = reps[2]; ++ curOpt->backs[3] = reps[3]; ++ ++ curPrice = curOpt->price; ++ nextIsChar = False; ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ curByte = *data; ++ matchByte = *(data - (reps[0] + 1)); ++ ++ posState = (position & p->pbMask); ++ ++ curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]); ++ { ++ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); ++ curAnd1Price += ++ (!IsCharState(state) ? ++ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : ++ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); ++ } ++ ++ nextOpt = &p->opt[cur + 1]; ++ ++ if (curAnd1Price < nextOpt->price) ++ { ++ nextOpt->price = curAnd1Price; ++ nextOpt->posPrev = cur; ++ MakeAsChar(nextOpt); ++ nextIsChar = True; ++ } ++ ++ matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]); ++ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]); ++ ++ if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0)) ++ { ++ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState); ++ if (shortRepPrice <= nextOpt->price) ++ { ++ nextOpt->price = shortRepPrice; ++ nextOpt->posPrev = cur; ++ MakeAsShortRep(nextOpt); ++ nextIsChar = True; ++ } ++ } ++ numAvailFull = p->numAvail; ++ { ++ UInt32 temp = kNumOpts - 1 - cur; ++ if (temp < numAvailFull) ++ numAvailFull = temp; ++ } ++ ++ if (numAvailFull < 2) ++ continue; ++ numAvail = (numAvailFull <= p->numFastBytes ? numAvailFull : p->numFastBytes); ++ ++ if (!nextIsChar && matchByte != curByte) /* speed optimization */ ++ { ++ /* try Literal + rep0 */ ++ UInt32 temp; ++ UInt32 lenTest2; ++ const Byte *data2 = data - (reps[0] + 1); ++ UInt32 limit = p->numFastBytes + 1; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ ++ for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++); ++ lenTest2 = temp - 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kLiteralNextStates[state]; ++ UInt32 posStateNext = (position + 1) & p->pbMask; ++ UInt32 nextRepMatchPrice = curAnd1Price + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ UInt32 offset = cur + 1 + lenTest2; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = False; ++ } ++ } ++ } ++ } ++ ++ startLen = 2; /* speed optimization */ ++ { ++ UInt32 repIndex; ++ for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++) ++ { ++ UInt32 lenTest; ++ UInt32 lenTestTemp; ++ UInt32 price; ++ const Byte *data2 = data - (reps[repIndex] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); ++ while (lenEnd < cur + lenTest) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ lenTestTemp = lenTest; ++ price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState); ++ do ++ { ++ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2]; ++ COptimal *opt = &p->opt[cur + lenTest]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur; ++ opt->backPrev = repIndex; ++ opt->prev1IsChar = False; ++ } ++ } ++ while (--lenTest >= 2); ++ lenTest = lenTestTemp; ++ ++ if (repIndex == 0) ++ startLen = lenTest + 1; ++ ++ /* if (_maxMode) */ ++ { ++ UInt32 lenTest2 = lenTest + 1; ++ UInt32 limit = lenTest2 + p->numFastBytes; ++ UInt32 nextRepMatchPrice; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); ++ lenTest2 -= lenTest + 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kRepNextStates[state]; ++ UInt32 posStateNext = (position + lenTest) & p->pbMask; ++ UInt32 curAndLenCharPrice = ++ price + p->repLenEnc.prices[posState][lenTest - 2] + ++ GET_PRICE_0(p->isMatch[state2][posStateNext]) + ++ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), ++ data[lenTest], data2[lenTest], p->ProbPrices); ++ state2 = kLiteralNextStates[state2]; ++ posStateNext = (position + lenTest + 1) & p->pbMask; ++ nextRepMatchPrice = curAndLenCharPrice + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ UInt32 offset = cur + lenTest + 1 + lenTest2; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + lenTest + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = True; ++ opt->posPrev2 = cur; ++ opt->backPrev2 = repIndex; ++ } ++ } ++ } ++ } ++ } ++ } ++ /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */ ++ if (newLen > numAvail) ++ { ++ newLen = numAvail; ++ for (numPairs = 0; newLen > matches[numPairs]; numPairs += 2); ++ matches[numPairs] = newLen; ++ numPairs += 2; ++ } ++ if (newLen >= startLen) ++ { ++ UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]); ++ UInt32 offs, curBack, posSlot; ++ UInt32 lenTest; ++ while (lenEnd < cur + newLen) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ ++ offs = 0; ++ while (startLen > matches[offs]) ++ offs += 2; ++ curBack = matches[offs + 1]; ++ GetPosSlot2(curBack, posSlot); ++ for (lenTest = /*2*/ startLen; ; lenTest++) ++ { ++ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN]; ++ UInt32 lenToPosState = GetLenToPosState(lenTest); ++ COptimal *opt; ++ if (curBack < kNumFullDistances) ++ curAndLenPrice += p->distancesPrices[lenToPosState][curBack]; ++ else ++ curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask]; ++ ++ opt = &p->opt[cur + lenTest]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur; ++ opt->backPrev = curBack + LZMA_NUM_REPS; ++ opt->prev1IsChar = False; ++ } ++ ++ if (/*_maxMode && */lenTest == matches[offs]) ++ { ++ /* Try Match + Literal + Rep0 */ ++ const Byte *data2 = data - (curBack + 1); ++ UInt32 lenTest2 = lenTest + 1; ++ UInt32 limit = lenTest2 + p->numFastBytes; ++ UInt32 nextRepMatchPrice; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); ++ lenTest2 -= lenTest + 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kMatchNextStates[state]; ++ UInt32 posStateNext = (position + lenTest) & p->pbMask; ++ UInt32 curAndLenCharPrice = curAndLenPrice + ++ GET_PRICE_0(p->isMatch[state2][posStateNext]) + ++ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), ++ data[lenTest], data2[lenTest], p->ProbPrices); ++ state2 = kLiteralNextStates[state2]; ++ posStateNext = (posStateNext + 1) & p->pbMask; ++ nextRepMatchPrice = curAndLenCharPrice + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 offset = cur + lenTest + 1 + lenTest2; ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + lenTest + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = True; ++ opt->posPrev2 = cur; ++ opt->backPrev2 = curBack + LZMA_NUM_REPS; ++ } ++ } ++ } ++ offs += 2; ++ if (offs == numPairs) ++ break; ++ curBack = matches[offs + 1]; ++ if (curBack >= kNumFullDistances) ++ GetPosSlot2(curBack, posSlot); ++ } ++ } ++ } ++ } ++} ++ ++#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist)) ++ ++static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes) ++{ ++ UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i; ++ const Byte *data; ++ const UInt32 *matches; ++ ++ if (p->additionalOffset == 0) ++ mainLen = ReadMatchDistances(p, &numPairs); ++ else ++ { ++ mainLen = p->longestMatchLength; ++ numPairs = p->numPairs; ++ } ++ ++ numAvail = p->numAvail; ++ *backRes = (UInt32)-1; ++ if (numAvail < 2) ++ return 1; ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ ++ repLen = repIndex = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 len; ++ const Byte *data2 = data - (p->reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ for (len = 2; len < numAvail && data[len] == data2[len]; len++); ++ if (len >= p->numFastBytes) ++ { ++ *backRes = i; ++ MovePos(p, len - 1); ++ return len; ++ } ++ if (len > repLen) ++ { ++ repIndex = i; ++ repLen = len; ++ } ++ } ++ ++ matches = p->matches; ++ if (mainLen >= p->numFastBytes) ++ { ++ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 1); ++ return mainLen; ++ } ++ ++ mainDist = 0; /* for GCC */ ++ if (mainLen >= 2) ++ { ++ mainDist = matches[numPairs - 1]; ++ while (numPairs > 2 && mainLen == matches[numPairs - 4] + 1) ++ { ++ if (!ChangePair(matches[numPairs - 3], mainDist)) ++ break; ++ numPairs -= 2; ++ mainLen = matches[numPairs - 2]; ++ mainDist = matches[numPairs - 1]; ++ } ++ if (mainLen == 2 && mainDist >= 0x80) ++ mainLen = 1; ++ } ++ ++ if (repLen >= 2 && ( ++ (repLen + 1 >= mainLen) || ++ (repLen + 2 >= mainLen && mainDist >= (1 << 9)) || ++ (repLen + 3 >= mainLen && mainDist >= (1 << 15)))) ++ { ++ *backRes = repIndex; ++ MovePos(p, repLen - 1); ++ return repLen; ++ } ++ ++ if (mainLen < 2 || numAvail <= 2) ++ return 1; ++ ++ p->longestMatchLength = ReadMatchDistances(p, &p->numPairs); ++ if (p->longestMatchLength >= 2) ++ { ++ UInt32 newDistance = matches[p->numPairs - 1]; ++ if ((p->longestMatchLength >= mainLen && newDistance < mainDist) || ++ (p->longestMatchLength == mainLen + 1 && !ChangePair(mainDist, newDistance)) || ++ (p->longestMatchLength > mainLen + 1) || ++ (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist))) ++ return 1; ++ } ++ ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 len, limit; ++ const Byte *data2 = data - (p->reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ limit = mainLen - 1; ++ for (len = 2; len < limit && data[len] == data2[len]; len++); ++ if (len >= limit) ++ return 1; ++ } ++ *backRes = mainDist + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 2); ++ return mainLen; ++} ++ ++static void WriteEndMarker(CLzmaEnc *p, UInt32 posState) ++{ ++ UInt32 len; ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); ++ p->state = kMatchNextStates[p->state]; ++ len = LZMA_MATCH_LEN_MIN; ++ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1); ++ RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits); ++ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask); ++} ++ ++static SRes CheckErrors(CLzmaEnc *p) ++{ ++ if (p->result != SZ_OK) ++ return p->result; ++ if (p->rc.res != SZ_OK) ++ p->result = SZ_ERROR_WRITE; ++ if (p->matchFinderBase.result != SZ_OK) ++ p->result = SZ_ERROR_READ; ++ if (p->result != SZ_OK) ++ p->finished = True; ++ return p->result; ++} ++ ++static SRes Flush(CLzmaEnc *p, UInt32 nowPos) ++{ ++ /* ReleaseMFStream(); */ ++ p->finished = True; ++ if (p->writeEndMark) ++ WriteEndMarker(p, nowPos & p->pbMask); ++ RangeEnc_FlushData(&p->rc); ++ RangeEnc_FlushStream(&p->rc); ++ return CheckErrors(p); ++} ++ ++static void FillAlignPrices(CLzmaEnc *p) ++{ ++ UInt32 i; ++ for (i = 0; i < kAlignTableSize; i++) ++ p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices); ++ p->alignPriceCount = 0; ++} ++ ++static void FillDistancesPrices(CLzmaEnc *p) ++{ ++ UInt32 tempPrices[kNumFullDistances]; ++ UInt32 i, lenToPosState; ++ for (i = kStartPosModelIndex; i < kNumFullDistances; i++) ++ { ++ UInt32 posSlot = GetPosSlot1(i); ++ UInt32 footerBits = ((posSlot >> 1) - 1); ++ UInt32 base = ((2 | (posSlot & 1)) << footerBits); ++ tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices); ++ } ++ ++ for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++) ++ { ++ UInt32 posSlot; ++ const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState]; ++ UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState]; ++ for (posSlot = 0; posSlot < p->distTableSize; posSlot++) ++ posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices); ++ for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++) ++ posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits); ++ ++ { ++ UInt32 *distancesPrices = p->distancesPrices[lenToPosState]; ++ UInt32 i; ++ for (i = 0; i < kStartPosModelIndex; i++) ++ distancesPrices[i] = posSlotPrices[i]; ++ for (; i < kNumFullDistances; i++) ++ distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i]; ++ } ++ } ++ p->matchPriceCount = 0; ++} ++ ++void LzmaEnc_Construct(CLzmaEnc *p) ++{ ++ RangeEnc_Construct(&p->rc); ++ MatchFinder_Construct(&p->matchFinderBase); ++ #ifndef _7ZIP_ST ++ MatchFinderMt_Construct(&p->matchFinderMt); ++ p->matchFinderMt.MatchFinder = &p->matchFinderBase; ++ #endif ++ ++ { ++ CLzmaEncProps props; ++ LzmaEncProps_Init(&props); ++ LzmaEnc_SetProps(p, &props); ++ } ++ ++ #ifndef LZMA_LOG_BSR ++ LzmaEnc_FastPosInit(p->g_FastPos); ++ #endif ++ ++ LzmaEnc_InitPriceTables(p->ProbPrices); ++ p->litProbs = 0; ++ p->saveState.litProbs = 0; ++} ++ ++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc) ++{ ++ void *p; ++ p = alloc->Alloc(alloc, sizeof(CLzmaEnc)); ++ if (p != 0) ++ LzmaEnc_Construct((CLzmaEnc *)p); ++ return p; ++} ++ ++void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->litProbs); ++ alloc->Free(alloc, p->saveState.litProbs); ++ p->litProbs = 0; ++ p->saveState.litProbs = 0; ++} ++ ++void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ #ifndef _7ZIP_ST ++ MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); ++ #endif ++ MatchFinder_Free(&p->matchFinderBase, allocBig); ++ LzmaEnc_FreeLits(p, alloc); ++ RangeEnc_Free(&p->rc, alloc); ++} ++ ++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig); ++ alloc->Free(alloc, p); ++} ++ ++static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize) ++{ ++ UInt32 nowPos32, startPos32; ++ if (p->needInit) ++ { ++ p->matchFinder.Init(p->matchFinderObj); ++ p->needInit = 0; ++ } ++ ++ if (p->finished) ++ return p->result; ++ RINOK(CheckErrors(p)); ++ ++ nowPos32 = (UInt32)p->nowPos64; ++ startPos32 = nowPos32; ++ ++ if (p->nowPos64 == 0) ++ { ++ UInt32 numPairs; ++ Byte curByte; ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) ++ return Flush(p, nowPos32); ++ ReadMatchDistances(p, &numPairs); ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0); ++ p->state = kLiteralNextStates[p->state]; ++ curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset); ++ LitEnc_Encode(&p->rc, p->litProbs, curByte); ++ p->additionalOffset--; ++ nowPos32++; ++ } ++ ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0) ++ for (;;) ++ { ++ UInt32 pos, len, posState; ++ ++ if (p->fastMode) ++ len = GetOptimumFast(p, &pos); ++ else ++ len = GetOptimum(p, nowPos32, &pos); ++ ++ #ifdef SHOW_STAT2 ++ printf("\n pos = %4X, len = %d pos = %d", nowPos32, len, pos); ++ #endif ++ ++ posState = nowPos32 & p->pbMask; ++ if (len == 1 && pos == (UInt32)-1) ++ { ++ Byte curByte; ++ CLzmaProb *probs; ++ const Byte *data; ++ ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0); ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; ++ curByte = *data; ++ probs = LIT_PROBS(nowPos32, *(data - 1)); ++ if (IsCharState(p->state)) ++ LitEnc_Encode(&p->rc, probs, curByte); ++ else ++ LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1)); ++ p->state = kLiteralNextStates[p->state]; ++ } ++ else ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); ++ if (pos < LZMA_NUM_REPS) ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1); ++ if (pos == 0) ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0); ++ RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1)); ++ } ++ else ++ { ++ UInt32 distance = p->reps[pos]; ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1); ++ if (pos == 1) ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0); ++ else ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1); ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2); ++ if (pos == 3) ++ p->reps[3] = p->reps[2]; ++ p->reps[2] = p->reps[1]; ++ } ++ p->reps[1] = p->reps[0]; ++ p->reps[0] = distance; ++ } ++ if (len == 1) ++ p->state = kShortRepNextStates[p->state]; ++ else ++ { ++ LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ p->state = kRepNextStates[p->state]; ++ } ++ } ++ else ++ { ++ UInt32 posSlot; ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); ++ p->state = kMatchNextStates[p->state]; ++ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ pos -= LZMA_NUM_REPS; ++ GetPosSlot(pos, posSlot); ++ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot); ++ ++ if (posSlot >= kStartPosModelIndex) ++ { ++ UInt32 footerBits = ((posSlot >> 1) - 1); ++ UInt32 base = ((2 | (posSlot & 1)) << footerBits); ++ UInt32 posReduced = pos - base; ++ ++ if (posSlot < kEndPosModelIndex) ++ RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced); ++ else ++ { ++ RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits); ++ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask); ++ p->alignPriceCount++; ++ } ++ } ++ p->reps[3] = p->reps[2]; ++ p->reps[2] = p->reps[1]; ++ p->reps[1] = p->reps[0]; ++ p->reps[0] = pos; ++ p->matchPriceCount++; ++ } ++ } ++ p->additionalOffset -= len; ++ nowPos32 += len; ++ if (p->additionalOffset == 0) ++ { ++ UInt32 processed; ++ if (!p->fastMode) ++ { ++ if (p->matchPriceCount >= (1 << 7)) ++ FillDistancesPrices(p); ++ if (p->alignPriceCount >= kAlignTableSize) ++ FillAlignPrices(p); ++ } ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) ++ break; ++ processed = nowPos32 - startPos32; ++ if (useLimits) ++ { ++ if (processed + kNumOpts + 300 >= maxUnpackSize || ++ RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize) ++ break; ++ } ++ else if (processed >= (1 << 15)) ++ { ++ p->nowPos64 += nowPos32 - startPos32; ++ return CheckErrors(p); ++ } ++ } ++ } ++ p->nowPos64 += nowPos32 - startPos32; ++ return Flush(p, nowPos32); ++} ++ ++#define kBigHashDicLimit ((UInt32)1 << 24) ++ ++static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ UInt32 beforeSize = kNumOpts; ++ Bool btMode; ++ if (!RangeEnc_Alloc(&p->rc, alloc)) ++ return SZ_ERROR_MEM; ++ btMode = (p->matchFinderBase.btMode != 0); ++ #ifndef _7ZIP_ST ++ p->mtMode = (p->multiThread && !p->fastMode && btMode); ++ #endif ++ ++ { ++ unsigned lclp = p->lc + p->lp; ++ if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp) ++ { ++ LzmaEnc_FreeLits(p, alloc); ++ p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); ++ p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); ++ if (p->litProbs == 0 || p->saveState.litProbs == 0) ++ { ++ LzmaEnc_FreeLits(p, alloc); ++ return SZ_ERROR_MEM; ++ } ++ p->lclp = lclp; ++ } ++ } ++ ++ p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit); ++ ++ if (beforeSize + p->dictSize < keepWindowSize) ++ beforeSize = keepWindowSize - p->dictSize; ++ ++ #ifndef _7ZIP_ST ++ if (p->mtMode) ++ { ++ RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)); ++ p->matchFinderObj = &p->matchFinderMt; ++ MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder); ++ } ++ else ++ #endif ++ { ++ if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)) ++ return SZ_ERROR_MEM; ++ p->matchFinderObj = &p->matchFinderBase; ++ MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder); ++ } ++ return SZ_OK; ++} ++ ++void LzmaEnc_Init(CLzmaEnc *p) ++{ ++ UInt32 i; ++ p->state = 0; ++ for (i = 0 ; i < LZMA_NUM_REPS; i++) ++ p->reps[i] = 0; ++ ++ RangeEnc_Init(&p->rc); ++ ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ UInt32 j; ++ for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++) ++ { ++ p->isMatch[i][j] = kProbInitValue; ++ p->isRep0Long[i][j] = kProbInitValue; ++ } ++ p->isRep[i] = kProbInitValue; ++ p->isRepG0[i] = kProbInitValue; ++ p->isRepG1[i] = kProbInitValue; ++ p->isRepG2[i] = kProbInitValue; ++ } ++ ++ { ++ UInt32 num = 0x300 << (p->lp + p->lc); ++ for (i = 0; i < num; i++) ++ p->litProbs[i] = kProbInitValue; ++ } ++ ++ { ++ for (i = 0; i < kNumLenToPosStates; i++) ++ { ++ CLzmaProb *probs = p->posSlotEncoder[i]; ++ UInt32 j; ++ for (j = 0; j < (1 << kNumPosSlotBits); j++) ++ probs[j] = kProbInitValue; ++ } ++ } ++ { ++ for (i = 0; i < kNumFullDistances - kEndPosModelIndex; i++) ++ p->posEncoders[i] = kProbInitValue; ++ } ++ ++ LenEnc_Init(&p->lenEnc.p); ++ LenEnc_Init(&p->repLenEnc.p); ++ ++ for (i = 0; i < (1 << kNumAlignBits); i++) ++ p->posAlignEncoder[i] = kProbInitValue; ++ ++ p->optimumEndIndex = 0; ++ p->optimumCurrentIndex = 0; ++ p->additionalOffset = 0; ++ ++ p->pbMask = (1 << p->pb) - 1; ++ p->lpMask = (1 << p->lp) - 1; ++} ++ ++void LzmaEnc_InitPrices(CLzmaEnc *p) ++{ ++ if (!p->fastMode) ++ { ++ FillDistancesPrices(p); ++ FillAlignPrices(p); ++ } ++ ++ p->lenEnc.tableSize = ++ p->repLenEnc.tableSize = ++ p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN; ++ LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices); ++ LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices); ++} ++ ++static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ UInt32 i; ++ for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++) ++ if (p->dictSize <= ((UInt32)1 << i)) ++ break; ++ p->distTableSize = i * 2; ++ ++ p->finished = False; ++ p->result = SZ_OK; ++ RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig)); ++ LzmaEnc_Init(p); ++ LzmaEnc_InitPrices(p); ++ p->nowPos64 = 0; ++ return SZ_OK; ++} ++ ++static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ p->matchFinderBase.stream = inStream; ++ p->needInit = 1; ++ p->rc.outStream = outStream; ++ return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig); ++} ++ ++SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, ++ ISeqInStream *inStream, UInt32 keepWindowSize, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ p->matchFinderBase.stream = inStream; ++ p->needInit = 1; ++ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); ++} ++ ++static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) ++{ ++ p->matchFinderBase.directInput = 1; ++ p->matchFinderBase.bufferBase = (Byte *)src; ++ p->matchFinderBase.directInputRem = srcLen; ++} ++ ++SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, ++ UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ LzmaEnc_SetInputBuf(p, src, srcLen); ++ p->needInit = 1; ++ ++ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); ++} ++ ++void LzmaEnc_Finish(CLzmaEncHandle pp) ++{ ++ #ifndef _7ZIP_ST ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ if (p->mtMode) ++ MatchFinderMt_ReleaseStream(&p->matchFinderMt); ++ #else ++ pp = pp; ++ #endif ++} ++ ++typedef struct ++{ ++ ISeqOutStream funcTable; ++ Byte *data; ++ SizeT rem; ++ Bool overflow; ++} CSeqOutStreamBuf; ++ ++static size_t MyWrite(void *pp, const void *data, size_t size) ++{ ++ CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp; ++ if (p->rem < size) ++ { ++ size = p->rem; ++ p->overflow = True; ++ } ++ memcpy(p->data, data, size); ++ p->rem -= size; ++ p->data += size; ++ return size; ++} ++ ++ ++UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp) ++{ ++ const CLzmaEnc *p = (CLzmaEnc *)pp; ++ return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); ++} ++ ++const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp) ++{ ++ const CLzmaEnc *p = (CLzmaEnc *)pp; ++ return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; ++} ++ ++SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, ++ Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ UInt64 nowPos64; ++ SRes res; ++ CSeqOutStreamBuf outStream; ++ ++ outStream.funcTable.Write = MyWrite; ++ outStream.data = dest; ++ outStream.rem = *destLen; ++ outStream.overflow = False; ++ ++ p->writeEndMark = False; ++ p->finished = False; ++ p->result = SZ_OK; ++ ++ if (reInit) ++ LzmaEnc_Init(p); ++ LzmaEnc_InitPrices(p); ++ nowPos64 = p->nowPos64; ++ RangeEnc_Init(&p->rc); ++ p->rc.outStream = &outStream.funcTable; ++ ++ res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize); ++ ++ *unpackSize = (UInt32)(p->nowPos64 - nowPos64); ++ *destLen -= outStream.rem; ++ if (outStream.overflow) ++ return SZ_ERROR_OUTPUT_EOF; ++ ++ return res; ++} ++ ++static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) ++{ ++ SRes res = SZ_OK; ++ ++ #ifndef _7ZIP_ST ++ Byte allocaDummy[0x300]; ++ int i = 0; ++ for (i = 0; i < 16; i++) ++ allocaDummy[i] = (Byte)i; ++ #endif ++ ++ for (;;) ++ { ++ res = LzmaEnc_CodeOneBlock(p, False, 0, 0); ++ if (res != SZ_OK || p->finished != 0) ++ break; ++ if (progress != 0) ++ { ++ res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc)); ++ if (res != SZ_OK) ++ { ++ res = SZ_ERROR_PROGRESS; ++ break; ++ } ++ } ++ } ++ LzmaEnc_Finish(p); ++ return res; ++} ++ ++SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig)); ++ return LzmaEnc_Encode2((CLzmaEnc *)pp, progress); ++} ++ ++SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ int i; ++ UInt32 dictSize = p->dictSize; ++ if (*size < LZMA_PROPS_SIZE) ++ return SZ_ERROR_PARAM; ++ *size = LZMA_PROPS_SIZE; ++ props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc); ++ ++ for (i = 11; i <= 30; i++) ++ { ++ if (dictSize <= ((UInt32)2 << i)) ++ { ++ dictSize = (2 << i); ++ break; ++ } ++ if (dictSize <= ((UInt32)3 << i)) ++ { ++ dictSize = (3 << i); ++ break; ++ } ++ } ++ ++ for (i = 0; i < 4; i++) ++ props[1 + i] = (Byte)(dictSize >> (8 * i)); ++ return SZ_OK; ++} ++ ++SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ SRes res; ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ ++ CSeqOutStreamBuf outStream; ++ ++ LzmaEnc_SetInputBuf(p, src, srcLen); ++ ++ outStream.funcTable.Write = MyWrite; ++ outStream.data = dest; ++ outStream.rem = *destLen; ++ outStream.overflow = False; ++ ++ p->writeEndMark = writeEndMark; ++ ++ p->rc.outStream = &outStream.funcTable; ++ res = LzmaEnc_MemPrepare(pp, src, srcLen, 0, alloc, allocBig); ++ if (res == SZ_OK) ++ res = LzmaEnc_Encode2(p, progress); ++ ++ *destLen -= outStream.rem; ++ if (outStream.overflow) ++ return SZ_ERROR_OUTPUT_EOF; ++ return res; ++} ++ ++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc); ++ SRes res; ++ if (p == 0) ++ return SZ_ERROR_MEM; ++ ++ res = LzmaEnc_SetProps(p, props); ++ if (res == SZ_OK) ++ { ++ res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize); ++ if (res == SZ_OK) ++ res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen, ++ writeEndMark, progress, alloc, allocBig); ++ } ++ ++ LzmaEnc_Destroy(p, alloc, allocBig); ++ return res; ++} +--- /dev/null ++++ b/lib/lzma/Makefile +@@ -0,0 +1,7 @@ ++lzma_compress-objs := LzFind.o LzmaEnc.o ++lzma_decompress-objs := LzmaDec.o ++ ++obj-$(CONFIG_LZMA_COMPRESS) += lzma_compress.o ++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma_decompress.o ++ ++EXTRA_CFLAGS += -Iinclude/linux -Iinclude/linux/lzma -include types.h diff --git a/target/linux/generic/patches-4.0/531-debloat_lzma.patch b/target/linux/generic/patches-4.0/531-debloat_lzma.patch new file mode 100644 index 0000000..aa3c498 --- /dev/null +++ b/target/linux/generic/patches-4.0/531-debloat_lzma.patch @@ -0,0 +1,1024 @@ +--- a/include/linux/lzma/LzmaDec.h ++++ b/include/linux/lzma/LzmaDec.h +@@ -31,14 +31,6 @@ typedef struct _CLzmaProps + UInt32 dicSize; + } CLzmaProps; + +-/* LzmaProps_Decode - decodes properties +-Returns: +- SZ_OK +- SZ_ERROR_UNSUPPORTED - Unsupported properties +-*/ +- +-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); +- + + /* ---------- LZMA Decoder state ---------- */ + +@@ -70,8 +62,6 @@ typedef struct + + #define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } + +-void LzmaDec_Init(CLzmaDec *p); +- + /* There are two types of LZMA streams: + 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. + 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ +@@ -108,97 +98,6 @@ typedef enum + + /* ELzmaStatus is used only as output value for function call */ + +- +-/* ---------- Interfaces ---------- */ +- +-/* There are 3 levels of interfaces: +- 1) Dictionary Interface +- 2) Buffer Interface +- 3) One Call Interface +- You can select any of these interfaces, but don't mix functions from different +- groups for same object. */ +- +- +-/* There are two variants to allocate state for Dictionary Interface: +- 1) LzmaDec_Allocate / LzmaDec_Free +- 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs +- You can use variant 2, if you set dictionary buffer manually. +- For Buffer Interface you must always use variant 1. +- +-LzmaDec_Allocate* can return: +- SZ_OK +- SZ_ERROR_MEM - Memory allocation error +- SZ_ERROR_UNSUPPORTED - Unsupported properties +-*/ +- +-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); +-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); +- +-SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); +-void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); +- +-/* ---------- Dictionary Interface ---------- */ +- +-/* You can use it, if you want to eliminate the overhead for data copying from +- dictionary to some other external buffer. +- You must work with CLzmaDec variables directly in this interface. +- +- STEPS: +- LzmaDec_Constr() +- LzmaDec_Allocate() +- for (each new stream) +- { +- LzmaDec_Init() +- while (it needs more decompression) +- { +- LzmaDec_DecodeToDic() +- use data from CLzmaDec::dic and update CLzmaDec::dicPos +- } +- } +- LzmaDec_Free() +-*/ +- +-/* LzmaDec_DecodeToDic +- +- The decoding to internal dictionary buffer (CLzmaDec::dic). +- You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! +- +-finishMode: +- It has meaning only if the decoding reaches output limit (dicLimit). +- LZMA_FINISH_ANY - Decode just dicLimit bytes. +- LZMA_FINISH_END - Stream must be finished after dicLimit. +- +-Returns: +- SZ_OK +- status: +- LZMA_STATUS_FINISHED_WITH_MARK +- LZMA_STATUS_NOT_FINISHED +- LZMA_STATUS_NEEDS_MORE_INPUT +- LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK +- SZ_ERROR_DATA - Data error +-*/ +- +-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, +- const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); +- +- +-/* ---------- Buffer Interface ---------- */ +- +-/* It's zlib-like interface. +- See LzmaDec_DecodeToDic description for information about STEPS and return results, +- but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need +- to work with CLzmaDec variables manually. +- +-finishMode: +- It has meaning only if the decoding reaches output limit (*destLen). +- LZMA_FINISH_ANY - Decode just destLen bytes. +- LZMA_FINISH_END - Stream must be finished after (*destLen). +-*/ +- +-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, +- const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); +- +- + /* ---------- One Call Interface ---------- */ + + /* LzmaDecode +--- a/lib/lzma/LzmaDec.c ++++ b/lib/lzma/LzmaDec.c +@@ -682,7 +682,7 @@ static void LzmaDec_InitRc(CLzmaDec *p, + p->needFlush = 0; + } + +-void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) ++static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) + { + p->needFlush = 1; + p->remainLen = 0; +@@ -698,7 +698,7 @@ void LzmaDec_InitDicAndState(CLzmaDec *p + p->needInitState = 1; + } + +-void LzmaDec_Init(CLzmaDec *p) ++static void LzmaDec_Init(CLzmaDec *p) + { + p->dicPos = 0; + LzmaDec_InitDicAndState(p, True, True); +@@ -716,7 +716,7 @@ static void LzmaDec_InitStateReal(CLzmaD + p->needInitState = 0; + } + +-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, ++static SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, + ELzmaFinishMode finishMode, ELzmaStatus *status) + { + SizeT inSize = *srcLen; +@@ -837,65 +837,13 @@ SRes LzmaDec_DecodeToDic(CLzmaDec *p, Si + return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; + } + +-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) +-{ +- SizeT outSize = *destLen; +- SizeT inSize = *srcLen; +- *srcLen = *destLen = 0; +- for (;;) +- { +- SizeT inSizeCur = inSize, outSizeCur, dicPos; +- ELzmaFinishMode curFinishMode; +- SRes res; +- if (p->dicPos == p->dicBufSize) +- p->dicPos = 0; +- dicPos = p->dicPos; +- if (outSize > p->dicBufSize - dicPos) +- { +- outSizeCur = p->dicBufSize; +- curFinishMode = LZMA_FINISH_ANY; +- } +- else +- { +- outSizeCur = dicPos + outSize; +- curFinishMode = finishMode; +- } +- +- res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); +- src += inSizeCur; +- inSize -= inSizeCur; +- *srcLen += inSizeCur; +- outSizeCur = p->dicPos - dicPos; +- memcpy(dest, p->dic + dicPos, outSizeCur); +- dest += outSizeCur; +- outSize -= outSizeCur; +- *destLen += outSizeCur; +- if (res != 0) +- return res; +- if (outSizeCur == 0 || outSize == 0) +- return SZ_OK; +- } +-} +- +-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) ++static void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) + { + alloc->Free(alloc, p->probs); + p->probs = 0; + } + +-static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) +-{ +- alloc->Free(alloc, p->dic); +- p->dic = 0; +-} +- +-void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) +-{ +- LzmaDec_FreeProbs(p, alloc); +- LzmaDec_FreeDict(p, alloc); +-} +- +-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) ++static SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) + { + UInt32 dicSize; + Byte d; +@@ -935,7 +883,7 @@ static SRes LzmaDec_AllocateProbs2(CLzma + return SZ_OK; + } + +-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++static SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) + { + CLzmaProps propNew; + RINOK(LzmaProps_Decode(&propNew, props, propsSize)); +@@ -943,28 +891,6 @@ SRes LzmaDec_AllocateProbs(CLzmaDec *p, + p->prop = propNew; + return SZ_OK; + } +- +-SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) +-{ +- CLzmaProps propNew; +- SizeT dicBufSize; +- RINOK(LzmaProps_Decode(&propNew, props, propsSize)); +- RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); +- dicBufSize = propNew.dicSize; +- if (p->dic == 0 || dicBufSize != p->dicBufSize) +- { +- LzmaDec_FreeDict(p, alloc); +- p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); +- if (p->dic == 0) +- { +- LzmaDec_FreeProbs(p, alloc); +- return SZ_ERROR_MEM; +- } +- } +- p->dicBufSize = dicBufSize; +- p->prop = propNew; +- return SZ_OK; +-} + + SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, + const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, +--- a/include/linux/lzma/LzmaEnc.h ++++ b/include/linux/lzma/LzmaEnc.h +@@ -31,9 +31,6 @@ typedef struct _CLzmaEncProps + } CLzmaEncProps; + + void LzmaEncProps_Init(CLzmaEncProps *p); +-void LzmaEncProps_Normalize(CLzmaEncProps *p); +-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2); +- + + /* ---------- CLzmaEncHandle Interface ---------- */ + +@@ -53,26 +50,9 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc * + void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); + SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); + SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); +-SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); + SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, + int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); + +-/* ---------- One Call Interface ---------- */ +- +-/* LzmaEncode +-Return code: +- SZ_OK - OK +- SZ_ERROR_MEM - Memory allocation error +- SZ_ERROR_PARAM - Incorrect paramater +- SZ_ERROR_OUTPUT_EOF - output buffer overflow +- SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) +-*/ +- +-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, +- const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); +- + #ifdef __cplusplus + } + #endif +--- a/lib/lzma/LzmaEnc.c ++++ b/lib/lzma/LzmaEnc.c +@@ -53,7 +53,7 @@ void LzmaEncProps_Init(CLzmaEncProps *p) + p->writeEndMark = 0; + } + +-void LzmaEncProps_Normalize(CLzmaEncProps *p) ++static void LzmaEncProps_Normalize(CLzmaEncProps *p) + { + int level = p->level; + if (level < 0) level = 5; +@@ -76,7 +76,7 @@ void LzmaEncProps_Normalize(CLzmaEncProp + #endif + } + +-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) ++static UInt32 __maybe_unused LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) + { + CLzmaEncProps props = *props2; + LzmaEncProps_Normalize(&props); +@@ -93,7 +93,7 @@ UInt32 LzmaEncProps_GetDictSize(const CL + + #define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } + +-UInt32 GetPosSlot1(UInt32 pos) ++static UInt32 GetPosSlot1(UInt32 pos) + { + UInt32 res; + BSR2_RET(pos, res); +@@ -107,7 +107,7 @@ UInt32 GetPosSlot1(UInt32 pos) + #define kNumLogBits (9 + (int)sizeof(size_t) / 2) + #define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) + +-void LzmaEnc_FastPosInit(Byte *g_FastPos) ++static void LzmaEnc_FastPosInit(Byte *g_FastPos) + { + int c = 2, slotFast; + g_FastPos[0] = 0; +@@ -339,58 +339,6 @@ typedef struct + CSaveState saveState; + } CLzmaEnc; + +-void LzmaEnc_SaveState(CLzmaEncHandle pp) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- CSaveState *dest = &p->saveState; +- int i; +- dest->lenEnc = p->lenEnc; +- dest->repLenEnc = p->repLenEnc; +- dest->state = p->state; +- +- for (i = 0; i < kNumStates; i++) +- { +- memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); +- memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); +- } +- for (i = 0; i < kNumLenToPosStates; i++) +- memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); +- memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); +- memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); +- memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); +- memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); +- memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); +- memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); +- memcpy(dest->reps, p->reps, sizeof(p->reps)); +- memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb)); +-} +- +-void LzmaEnc_RestoreState(CLzmaEncHandle pp) +-{ +- CLzmaEnc *dest = (CLzmaEnc *)pp; +- const CSaveState *p = &dest->saveState; +- int i; +- dest->lenEnc = p->lenEnc; +- dest->repLenEnc = p->repLenEnc; +- dest->state = p->state; +- +- for (i = 0; i < kNumStates; i++) +- { +- memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); +- memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); +- } +- for (i = 0; i < kNumLenToPosStates; i++) +- memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); +- memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); +- memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); +- memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); +- memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); +- memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); +- memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); +- memcpy(dest->reps, p->reps, sizeof(p->reps)); +- memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb)); +-} +- + SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -600,7 +548,7 @@ static void LitEnc_EncodeMatched(CRangeE + while (symbol < 0x10000); + } + +-void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) ++static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) + { + UInt32 i; + for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) +@@ -1676,7 +1624,7 @@ static void FillDistancesPrices(CLzmaEnc + p->matchPriceCount = 0; + } + +-void LzmaEnc_Construct(CLzmaEnc *p) ++static void LzmaEnc_Construct(CLzmaEnc *p) + { + RangeEnc_Construct(&p->rc); + MatchFinder_Construct(&p->matchFinderBase); +@@ -1709,7 +1657,7 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc * + return p; + } + +-void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) ++static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) + { + alloc->Free(alloc, p->litProbs); + alloc->Free(alloc, p->saveState.litProbs); +@@ -1717,7 +1665,7 @@ void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAl + p->saveState.litProbs = 0; + } + +-void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) ++static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) + { + #ifndef _7ZIP_ST + MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); +@@ -1947,7 +1895,7 @@ static SRes LzmaEnc_Alloc(CLzmaEnc *p, U + return SZ_OK; + } + +-void LzmaEnc_Init(CLzmaEnc *p) ++static void LzmaEnc_Init(CLzmaEnc *p) + { + UInt32 i; + p->state = 0; +@@ -2005,7 +1953,7 @@ void LzmaEnc_Init(CLzmaEnc *p) + p->lpMask = (1 << p->lp) - 1; + } + +-void LzmaEnc_InitPrices(CLzmaEnc *p) ++static void LzmaEnc_InitPrices(CLzmaEnc *p) + { + if (!p->fastMode) + { +@@ -2037,26 +1985,6 @@ static SRes LzmaEnc_AllocAndInit(CLzmaEn + return SZ_OK; + } + +-static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- p->matchFinderBase.stream = inStream; +- p->needInit = 1; +- p->rc.outStream = outStream; +- return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig); +-} +- +-SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, +- ISeqInStream *inStream, UInt32 keepWindowSize, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- p->matchFinderBase.stream = inStream; +- p->needInit = 1; +- return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); +-} +- + static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) + { + p->matchFinderBase.directInput = 1; +@@ -2064,7 +1992,7 @@ static void LzmaEnc_SetInputBuf(CLzmaEnc + p->matchFinderBase.directInputRem = srcLen; + } + +-SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, ++static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, + UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2074,7 +2002,7 @@ SRes LzmaEnc_MemPrepare(CLzmaEncHandle p + return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); + } + +-void LzmaEnc_Finish(CLzmaEncHandle pp) ++static void LzmaEnc_Finish(CLzmaEncHandle pp) + { + #ifndef _7ZIP_ST + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2107,53 +2035,6 @@ static size_t MyWrite(void *pp, const vo + return size; + } + +- +-UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp) +-{ +- const CLzmaEnc *p = (CLzmaEnc *)pp; +- return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); +-} +- +-const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp) +-{ +- const CLzmaEnc *p = (CLzmaEnc *)pp; +- return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; +-} +- +-SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, +- Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- UInt64 nowPos64; +- SRes res; +- CSeqOutStreamBuf outStream; +- +- outStream.funcTable.Write = MyWrite; +- outStream.data = dest; +- outStream.rem = *destLen; +- outStream.overflow = False; +- +- p->writeEndMark = False; +- p->finished = False; +- p->result = SZ_OK; +- +- if (reInit) +- LzmaEnc_Init(p); +- LzmaEnc_InitPrices(p); +- nowPos64 = p->nowPos64; +- RangeEnc_Init(&p->rc); +- p->rc.outStream = &outStream.funcTable; +- +- res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize); +- +- *unpackSize = (UInt32)(p->nowPos64 - nowPos64); +- *destLen -= outStream.rem; +- if (outStream.overflow) +- return SZ_ERROR_OUTPUT_EOF; +- +- return res; +-} +- + static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) + { + SRes res = SZ_OK; +@@ -2184,13 +2065,6 @@ static SRes LzmaEnc_Encode2(CLzmaEnc *p, + return res; + } + +-SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig)); +- return LzmaEnc_Encode2((CLzmaEnc *)pp, progress); +-} +- + SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2247,25 +2121,3 @@ SRes LzmaEnc_MemEncode(CLzmaEncHandle pp + return SZ_ERROR_OUTPUT_EOF; + return res; + } +- +-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, +- const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc); +- SRes res; +- if (p == 0) +- return SZ_ERROR_MEM; +- +- res = LzmaEnc_SetProps(p, props); +- if (res == SZ_OK) +- { +- res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize); +- if (res == SZ_OK) +- res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen, +- writeEndMark, progress, alloc, allocBig); +- } +- +- LzmaEnc_Destroy(p, alloc, allocBig); +- return res; +-} +--- a/include/linux/lzma/LzFind.h ++++ b/include/linux/lzma/LzFind.h +@@ -55,11 +55,6 @@ typedef struct _CMatchFinder + + #define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) + +-int MatchFinder_NeedMove(CMatchFinder *p); +-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p); +-void MatchFinder_MoveBlock(CMatchFinder *p); +-void MatchFinder_ReadIfRequired(CMatchFinder *p); +- + void MatchFinder_Construct(CMatchFinder *p); + + /* Conditions: +@@ -70,12 +65,6 @@ int MatchFinder_Create(CMatchFinder *p, + UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, + ISzAlloc *alloc); + void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); +-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems); +-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue); +- +-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, +- UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, +- UInt32 *distances, UInt32 maxLen); + + /* + Conditions: +@@ -102,12 +91,6 @@ typedef struct _IMatchFinder + + void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); + +-void MatchFinder_Init(CMatchFinder *p); +-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); +-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); +-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); +-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); +- + #ifdef __cplusplus + } + #endif +--- a/lib/lzma/LzFind.c ++++ b/lib/lzma/LzFind.c +@@ -14,9 +14,15 @@ + + #define kStartMaxLen 3 + ++#if 0 ++#define DIRECT_INPUT p->directInput ++#else ++#define DIRECT_INPUT 1 ++#endif ++ + static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) + { +- if (!p->directInput) ++ if (!DIRECT_INPUT) + { + alloc->Free(alloc, p->bufferBase); + p->bufferBase = 0; +@@ -28,7 +34,7 @@ static void LzInWindow_Free(CMatchFinder + static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) + { + UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; +- if (p->directInput) ++ if (DIRECT_INPUT) + { + p->blockSize = blockSize; + return 1; +@@ -42,12 +48,12 @@ static int LzInWindow_Create(CMatchFinde + return (p->bufferBase != 0); + } + +-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } +-Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } ++static Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } ++static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } + +-UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } ++static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } + +-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) ++static void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) + { + p->posLimit -= subValue; + p->pos -= subValue; +@@ -58,7 +64,7 @@ static void MatchFinder_ReadBlock(CMatch + { + if (p->streamEndWasReached || p->result != SZ_OK) + return; +- if (p->directInput) ++ if (DIRECT_INPUT) + { + UInt32 curSize = 0xFFFFFFFF - p->streamPos; + if (curSize > p->directInputRem) +@@ -89,7 +95,7 @@ static void MatchFinder_ReadBlock(CMatch + } + } + +-void MatchFinder_MoveBlock(CMatchFinder *p) ++static void MatchFinder_MoveBlock(CMatchFinder *p) + { + memmove(p->bufferBase, + p->buffer - p->keepSizeBefore, +@@ -97,22 +103,14 @@ void MatchFinder_MoveBlock(CMatchFinder + p->buffer = p->bufferBase + p->keepSizeBefore; + } + +-int MatchFinder_NeedMove(CMatchFinder *p) ++static int MatchFinder_NeedMove(CMatchFinder *p) + { +- if (p->directInput) ++ if (DIRECT_INPUT) + return 0; + /* if (p->streamEndWasReached) return 0; */ + return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); + } + +-void MatchFinder_ReadIfRequired(CMatchFinder *p) +-{ +- if (p->streamEndWasReached) +- return; +- if (p->keepSizeAfter >= p->streamPos - p->pos) +- MatchFinder_ReadBlock(p); +-} +- + static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) + { + if (MatchFinder_NeedMove(p)) +@@ -268,7 +266,7 @@ static void MatchFinder_SetLimits(CMatch + p->posLimit = p->pos + limit; + } + +-void MatchFinder_Init(CMatchFinder *p) ++static void MatchFinder_Init(CMatchFinder *p) + { + UInt32 i; + for (i = 0; i < p->hashSizeSum; i++) +@@ -287,7 +285,7 @@ static UInt32 MatchFinder_GetSubValue(CM + return (p->pos - p->historySize - 1) & kNormalizeMask; + } + +-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) ++static void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) + { + UInt32 i; + for (i = 0; i < numItems; i++) +@@ -319,38 +317,7 @@ static void MatchFinder_CheckLimits(CMat + MatchFinder_SetLimits(p); + } + +-static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, +- UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, +- UInt32 *distances, UInt32 maxLen) +-{ +- son[_cyclicBufferPos] = curMatch; +- for (;;) +- { +- UInt32 delta = pos - curMatch; +- if (cutValue-- == 0 || delta >= _cyclicBufferSize) +- return distances; +- { +- const Byte *pb = cur - delta; +- curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)]; +- if (pb[maxLen] == cur[maxLen] && *pb == *cur) +- { +- UInt32 len = 0; +- while (++len != lenLimit) +- if (pb[len] != cur[len]) +- break; +- if (maxLen < len) +- { +- *distances++ = maxLen = len; +- *distances++ = delta - 1; +- if (len == lenLimit) +- return distances; +- } +- } +- } +- } +-} +- +-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++static UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, + UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, + UInt32 *distances, UInt32 maxLen) + { +@@ -460,10 +427,10 @@ static void SkipMatchesSpec(UInt32 lenLi + p->buffer++; \ + if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); + +-#define MOVE_POS_RET MOVE_POS return offset; +- + static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } + ++#define MOVE_POS_RET MatchFinder_MovePos(p); return offset; ++ + #define GET_MATCHES_HEADER2(minLen, ret_op) \ + UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ + lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ +@@ -479,62 +446,7 @@ static void MatchFinder_MovePos(CMatchFi + distances + offset, maxLen) - distances); MOVE_POS_RET; + + #define SKIP_FOOTER \ +- SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS; +- +-static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(2) +- HASH2_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = 0; +- GET_MATCHES_FOOTER(offset, 1) +-} +- +-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = 0; +- GET_MATCHES_FOOTER(offset, 2) +-} +- +-static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 hash2Value, delta2, maxLen, offset; +- GET_MATCHES_HEADER(3) +- +- HASH3_CALC; +- +- delta2 = p->pos - p->hash[hash2Value]; +- curMatch = p->hash[kFix3HashSize + hashValue]; +- +- p->hash[hash2Value] = +- p->hash[kFix3HashSize + hashValue] = p->pos; +- +- +- maxLen = 2; +- offset = 0; +- if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) +- { +- for (; maxLen != lenLimit; maxLen++) +- if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) +- break; +- distances[0] = maxLen; +- distances[1] = delta2 - 1; +- offset = 2; +- if (maxLen == lenLimit) +- { +- SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); +- MOVE_POS_RET; +- } +- } +- GET_MATCHES_FOOTER(offset, maxLen) +-} ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MatchFinder_MovePos(p); + + static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) + { +@@ -583,108 +495,6 @@ static UInt32 Bt4_MatchFinder_GetMatches + GET_MATCHES_FOOTER(offset, maxLen) + } + +-static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; +- GET_MATCHES_HEADER(4) +- +- HASH4_CALC; +- +- delta2 = p->pos - p->hash[ hash2Value]; +- delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; +- curMatch = p->hash[kFix4HashSize + hashValue]; +- +- p->hash[ hash2Value] = +- p->hash[kFix3HashSize + hash3Value] = +- p->hash[kFix4HashSize + hashValue] = p->pos; +- +- maxLen = 1; +- offset = 0; +- if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) +- { +- distances[0] = maxLen = 2; +- distances[1] = delta2 - 1; +- offset = 2; +- } +- if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) +- { +- maxLen = 3; +- distances[offset + 1] = delta3 - 1; +- offset += 2; +- delta2 = delta3; +- } +- if (offset != 0) +- { +- for (; maxLen != lenLimit; maxLen++) +- if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) +- break; +- distances[offset - 2] = maxLen; +- if (maxLen == lenLimit) +- { +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS_RET; +- } +- } +- if (maxLen < 3) +- maxLen = 3; +- offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), +- distances + offset, maxLen) - (distances)); +- MOVE_POS_RET +-} +- +-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), +- distances, 2) - (distances)); +- MOVE_POS_RET +-} +- +-static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(2) +- HASH2_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- +-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- +-static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- UInt32 hash2Value; +- SKIP_HEADER(3) +- HASH3_CALC; +- curMatch = p->hash[kFix3HashSize + hashValue]; +- p->hash[hash2Value] = +- p->hash[kFix3HashSize + hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- + static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) + { + do +@@ -701,61 +511,12 @@ static void Bt4_MatchFinder_Skip(CMatchF + while (--num != 0); + } + +-static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- UInt32 hash2Value, hash3Value; +- SKIP_HEADER(4) +- HASH4_CALC; +- curMatch = p->hash[kFix4HashSize + hashValue]; +- p->hash[ hash2Value] = +- p->hash[kFix3HashSize + hash3Value] = +- p->hash[kFix4HashSize + hashValue] = p->pos; +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS +- } +- while (--num != 0); +-} +- +-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS +- } +- while (--num != 0); +-} +- + void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) + { + vTable->Init = (Mf_Init_Func)MatchFinder_Init; + vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; + vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; + vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; +- if (!p->btMode) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip; +- } +- else if (p->numHashBytes == 2) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip; +- } +- else if (p->numHashBytes == 3) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip; +- } +- else +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; +- } ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; + } diff --git a/target/linux/generic/patches-4.0/532-jffs2_eofdetect.patch b/target/linux/generic/patches-4.0/532-jffs2_eofdetect.patch new file mode 100644 index 0000000..9cbe183 --- /dev/null +++ b/target/linux/generic/patches-4.0/532-jffs2_eofdetect.patch @@ -0,0 +1,56 @@ +--- a/fs/jffs2/build.c ++++ b/fs/jffs2/build.c +@@ -114,6 +114,16 @@ static int jffs2_build_filesystem(struct + dbg_fsbuild("scanned flash completely\n"); + jffs2_dbg_dump_block_lists_nolock(c); + ++ if (c->flags & (1 << 7)) { ++ printk("%s(): unlocking the mtd device... ", __func__); ++ mtd_unlock(c->mtd, 0, c->mtd->size); ++ printk("done.\n"); ++ ++ printk("%s(): erasing all blocks after the end marker... ", __func__); ++ jffs2_erase_pending_blocks(c, -1); ++ printk("done.\n"); ++ } ++ + dbg_fsbuild("pass 1 starting\n"); + c->flags |= JFFS2_SB_FLAG_BUILDING; + /* Now scan the directory tree, increasing nlink according to every dirent found. */ +--- a/fs/jffs2/scan.c ++++ b/fs/jffs2/scan.c +@@ -148,8 +148,14 @@ int jffs2_scan_medium(struct jffs2_sb_in + /* reset summary info for next eraseblock scan */ + jffs2_sum_reset_collected(s); + +- ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), +- buf_size, s); ++ if (c->flags & (1 << 7)) { ++ if (mtd_block_isbad(c->mtd, jeb->offset)) ++ ret = BLK_STATE_BADBLOCK; ++ else ++ ret = BLK_STATE_ALLFF; ++ } else ++ ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), ++ buf_size, s); + + if (ret < 0) + goto out; +@@ -561,6 +567,17 @@ full_scan: + return err; + } + ++ if ((buf[0] == 0xde) && ++ (buf[1] == 0xad) && ++ (buf[2] == 0xc0) && ++ (buf[3] == 0xde)) { ++ /* end of filesystem. erase everything after this point */ ++ printk("%s(): End of filesystem marker found at 0x%x\n", __func__, jeb->offset); ++ c->flags |= (1 << 7); ++ ++ return BLK_STATE_ALLFF; ++ } ++ + /* We temporarily use 'ofs' as a pointer into the buffer/jeb */ + ofs = 0; + max_ofs = EMPTY_SCAN_SIZE(c->sector_size); diff --git a/target/linux/generic/patches-4.0/540-crypto-xz-decompression-support.patch b/target/linux/generic/patches-4.0/540-crypto-xz-decompression-support.patch new file mode 100644 index 0000000..97c5a89 --- /dev/null +++ b/target/linux/generic/patches-4.0/540-crypto-xz-decompression-support.patch @@ -0,0 +1,146 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -1446,6 +1446,13 @@ config CRYPTO_LZ4HC + help + This is the LZ4 high compression mode algorithm. + ++config CRYPTO_XZ ++ tristate "XZ compression algorithm" ++ select CRYPTO_ALGAPI ++ select XZ_DEC ++ help ++ This is the XZ algorithm. Only decompression is supported for now. ++ + comment "Random Number Generation" + + config CRYPTO_ANSI_CPRNG +--- a/crypto/Makefile ++++ b/crypto/Makefile +@@ -89,6 +89,7 @@ obj-$(CONFIG_CRYPTO_AUTHENC) += authenc. + obj-$(CONFIG_CRYPTO_LZO) += lzo.o + obj-$(CONFIG_CRYPTO_LZ4) += lz4.o + obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o ++obj-$(CONFIG_CRYPTO_XZ) += xz.o + obj-$(CONFIG_CRYPTO_842) += 842.o + obj-$(CONFIG_CRYPTO_RNG2) += rng.o + obj-$(CONFIG_CRYPTO_RNG2) += krng.o +--- /dev/null ++++ b/crypto/xz.c +@@ -0,0 +1,117 @@ ++/* ++ * Cryptographic API. ++ * ++ * XZ decompression support. ++ * ++ * Copyright (c) 2012 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct xz_comp_ctx { ++ struct xz_dec *decomp_state; ++ struct xz_buf decomp_buf; ++}; ++ ++static int crypto_xz_decomp_init(struct xz_comp_ctx *ctx) ++{ ++ ctx->decomp_state = xz_dec_init(XZ_SINGLE, 0); ++ if (!ctx->decomp_state) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static void crypto_xz_decomp_exit(struct xz_comp_ctx *ctx) ++{ ++ xz_dec_end(ctx->decomp_state); ++} ++ ++static int crypto_xz_init(struct crypto_tfm *tfm) ++{ ++ struct xz_comp_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ return crypto_xz_decomp_init(ctx); ++} ++ ++static void crypto_xz_exit(struct crypto_tfm *tfm) ++{ ++ struct xz_comp_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ crypto_xz_decomp_exit(ctx); ++} ++ ++static int crypto_xz_compress(struct crypto_tfm *tfm, const u8 *src, ++ unsigned int slen, u8 *dst, unsigned int *dlen) ++{ ++ return -EOPNOTSUPP; ++} ++ ++static int crypto_xz_decompress(struct crypto_tfm *tfm, const u8 *src, ++ unsigned int slen, u8 *dst, unsigned int *dlen) ++{ ++ struct xz_comp_ctx *dctx = crypto_tfm_ctx(tfm); ++ struct xz_buf *xz_buf = &dctx->decomp_buf; ++ int ret; ++ ++ memset(xz_buf, '\0', sizeof(struct xz_buf)); ++ ++ xz_buf->in = (u8 *) src; ++ xz_buf->in_pos = 0; ++ xz_buf->in_size = slen; ++ xz_buf->out = (u8 *) dst; ++ xz_buf->out_pos = 0; ++ xz_buf->out_size = *dlen; ++ ++ ret = xz_dec_run(dctx->decomp_state, xz_buf); ++ if (ret != XZ_STREAM_END) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ *dlen = xz_buf->out_pos; ++ ret = 0; ++ ++out: ++ return ret; ++} ++ ++static struct crypto_alg crypto_xz_alg = { ++ .cra_name = "xz", ++ .cra_flags = CRYPTO_ALG_TYPE_COMPRESS, ++ .cra_ctxsize = sizeof(struct xz_comp_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_list = LIST_HEAD_INIT(crypto_xz_alg.cra_list), ++ .cra_init = crypto_xz_init, ++ .cra_exit = crypto_xz_exit, ++ .cra_u = { .compress = { ++ .coa_compress = crypto_xz_compress, ++ .coa_decompress = crypto_xz_decompress } } ++}; ++ ++static int __init crypto_xz_mod_init(void) ++{ ++ return crypto_register_alg(&crypto_xz_alg); ++} ++ ++static void __exit crypto_xz_mod_exit(void) ++{ ++ crypto_unregister_alg(&crypto_xz_alg); ++} ++ ++module_init(crypto_xz_mod_init); ++module_exit(crypto_xz_mod_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Crypto XZ decompression support"); ++MODULE_AUTHOR("Gabor Juhos "); diff --git a/target/linux/generic/patches-4.0/541-ubifs-xz-decompression-support.patch b/target/linux/generic/patches-4.0/541-ubifs-xz-decompression-support.patch new file mode 100644 index 0000000..f85689c --- /dev/null +++ b/target/linux/generic/patches-4.0/541-ubifs-xz-decompression-support.patch @@ -0,0 +1,92 @@ +--- a/fs/ubifs/Kconfig ++++ b/fs/ubifs/Kconfig +@@ -5,8 +5,10 @@ config UBIFS_FS + select CRYPTO if UBIFS_FS_ADVANCED_COMPR + select CRYPTO if UBIFS_FS_LZO + select CRYPTO if UBIFS_FS_ZLIB ++ select CRYPTO if UBIFS_FS_XZ + select CRYPTO_LZO if UBIFS_FS_LZO + select CRYPTO_DEFLATE if UBIFS_FS_ZLIB ++ select CRYPTO_XZ if UBIFS_FS_XZ + depends on MTD_UBI + help + UBIFS is a file system for flash devices which works on top of UBI. +@@ -35,3 +37,12 @@ config UBIFS_FS_ZLIB + default y + help + Zlib compresses better than LZO but it is slower. Say 'Y' if unsure. ++ ++config UBIFS_FS_XZ ++ bool "XZ decompression support" if UBIFS_FS_ADVANCED_COMPR ++ depends on UBIFS_FS ++ default y ++ help ++ XZ compresses better the ZLIB but it is slower.. ++ Say 'Y' if unsure. ++ +--- a/fs/ubifs/compress.c ++++ b/fs/ubifs/compress.c +@@ -71,6 +71,24 @@ static struct ubifs_compressor zlib_comp + }; + #endif + ++#ifdef CONFIG_UBIFS_FS_XZ ++static DEFINE_MUTEX(xz_enc_mutex); ++static DEFINE_MUTEX(xz_dec_mutex); ++ ++static struct ubifs_compressor xz_compr = { ++ .compr_type = UBIFS_COMPR_XZ, ++ .comp_mutex = &xz_enc_mutex, ++ .decomp_mutex = &xz_dec_mutex, ++ .name = "xz", ++ .capi_name = "xz", ++}; ++#else ++static struct ubifs_compressor xz_compr = { ++ .compr_type = UBIFS_COMPR_XZ, ++ .name = "xz", ++}; ++#endif ++ + /* All UBIFS compressors */ + struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT]; + +@@ -232,9 +250,15 @@ int __init ubifs_compressors_init(void) + if (err) + goto out_lzo; + ++ err = compr_init(&xz_compr); ++ if (err) ++ goto out_zlib; ++ + ubifs_compressors[UBIFS_COMPR_NONE] = &none_compr; + return 0; + ++out_zlib: ++ compr_exit(&zlib_compr); + out_lzo: + compr_exit(&lzo_compr); + return err; +@@ -247,4 +271,5 @@ void ubifs_compressors_exit(void) + { + compr_exit(&lzo_compr); + compr_exit(&zlib_compr); ++ compr_exit(&xz_compr); + } +--- a/fs/ubifs/ubifs-media.h ++++ b/fs/ubifs/ubifs-media.h +@@ -332,12 +332,14 @@ enum { + * UBIFS_COMPR_NONE: no compression + * UBIFS_COMPR_LZO: LZO compression + * UBIFS_COMPR_ZLIB: ZLIB compression ++ * UBIFS_COMPR_XZ: XZ compression + * UBIFS_COMPR_TYPES_CNT: count of supported compression types + */ + enum { + UBIFS_COMPR_NONE, + UBIFS_COMPR_LZO, + UBIFS_COMPR_ZLIB, ++ UBIFS_COMPR_XZ, + UBIFS_COMPR_TYPES_CNT, + }; + diff --git a/target/linux/generic/patches-4.0/551-ubifs-fix-default-compression-selection.patch b/target/linux/generic/patches-4.0/551-ubifs-fix-default-compression-selection.patch new file mode 100644 index 0000000..1b0f307 --- /dev/null +++ b/target/linux/generic/patches-4.0/551-ubifs-fix-default-compression-selection.patch @@ -0,0 +1,29 @@ +--- a/fs/ubifs/sb.c ++++ b/fs/ubifs/sb.c +@@ -63,6 +63,17 @@ + /* Default time granularity in nanoseconds */ + #define DEFAULT_TIME_GRAN 1000000000 + ++static int get_default_compressor(void) ++{ ++ if (ubifs_compr_present(UBIFS_COMPR_LZO)) ++ return UBIFS_COMPR_LZO; ++ ++ if (ubifs_compr_present(UBIFS_COMPR_ZLIB)) ++ return UBIFS_COMPR_ZLIB; ++ ++ return UBIFS_COMPR_NONE; ++} ++ + /** + * create_default_filesystem - format empty UBI volume. + * @c: UBIFS file-system description object +@@ -183,7 +194,7 @@ static int create_default_filesystem(str + if (c->mount_opts.override_compr) + sup->default_compr = cpu_to_le16(c->mount_opts.compr_type); + else +- sup->default_compr = cpu_to_le16(UBIFS_COMPR_LZO); ++ sup->default_compr = cpu_to_le16(get_default_compressor()); + + generate_random_uuid(sup->uuid); + diff --git a/target/linux/generic/patches-4.0/600-netfilter_conntrack_flush.patch b/target/linux/generic/patches-4.0/600-netfilter_conntrack_flush.patch new file mode 100644 index 0000000..bd7a7ff --- /dev/null +++ b/target/linux/generic/patches-4.0/600-netfilter_conntrack_flush.patch @@ -0,0 +1,86 @@ +--- a/net/netfilter/nf_conntrack_standalone.c ++++ b/net/netfilter/nf_conntrack_standalone.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #ifdef CONFIG_SYSCTL + #include +@@ -259,10 +260,66 @@ static int ct_open(struct inode *inode, + sizeof(struct ct_iter_state)); + } + ++struct kill_request { ++ u16 family; ++ union nf_inet_addr addr; ++}; ++ ++static int kill_matching(struct nf_conn *i, void *data) ++{ ++ struct kill_request *kr = data; ++ struct nf_conntrack_tuple *t1 = &i->tuplehash[IP_CT_DIR_ORIGINAL].tuple; ++ struct nf_conntrack_tuple *t2 = &i->tuplehash[IP_CT_DIR_REPLY].tuple; ++ ++ if (!kr->family) ++ return 1; ++ ++ if (t1->src.l3num != kr->family) ++ return 0; ++ ++ return (nf_inet_addr_cmp(&kr->addr, &t1->src.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t1->dst.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t2->src.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t2->dst.u3)); ++} ++ ++static ssize_t ct_file_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *seq = file->private_data; ++ struct net *net = seq_file_net(seq); ++ struct kill_request kr = { }; ++ char req[INET6_ADDRSTRLEN] = { }; ++ ++ if (count == 0) ++ return 0; ++ ++ if (count >= INET6_ADDRSTRLEN) ++ count = INET6_ADDRSTRLEN - 1; ++ ++ if (copy_from_user(req, buf, count)) ++ return -EFAULT; ++ ++ if (strnchr(req, count, ':')) { ++ kr.family = AF_INET6; ++ if (!in6_pton(req, count, (void *)&kr.addr, '\n', NULL)) ++ return -EINVAL; ++ } else if (strnchr(req, count, '.')) { ++ kr.family = AF_INET; ++ if (!in4_pton(req, count, (void *)&kr.addr, '\n', NULL)) ++ return -EINVAL; ++ } ++ ++ nf_ct_iterate_cleanup(net, kill_matching, &kr, 0, 0); ++ ++ return count; ++} ++ + static const struct file_operations ct_file_ops = { + .owner = THIS_MODULE, + .open = ct_open, + .read = seq_read, ++ .write = ct_file_write, + .llseek = seq_lseek, + .release = seq_release_net, + }; +@@ -364,7 +421,7 @@ static int nf_conntrack_standalone_init_ + { + struct proc_dir_entry *pde; + +- pde = proc_create("nf_conntrack", 0440, net->proc_net, &ct_file_ops); ++ pde = proc_create("nf_conntrack", 0660, net->proc_net, &ct_file_ops); + if (!pde) + goto out_nf_conntrack; + diff --git a/target/linux/generic/patches-4.0/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/patches-4.0/610-netfilter_match_bypass_default_checks.patch new file mode 100644 index 0000000..358d64b --- /dev/null +++ b/target/linux/generic/patches-4.0/610-netfilter_match_bypass_default_checks.patch @@ -0,0 +1,93 @@ +--- a/include/uapi/linux/netfilter_ipv4/ip_tables.h ++++ b/include/uapi/linux/netfilter_ipv4/ip_tables.h +@@ -87,6 +87,7 @@ struct ipt_ip { + #define IPT_F_FRAG 0x01 /* Set if rule is a fragment rule */ + #define IPT_F_GOTO 0x02 /* Set if jump is a goto */ + #define IPT_F_MASK 0x03 /* All possible flag bits mask. */ ++#define IPT_F_NO_DEF_MATCH 0x80 /* Internal: no default match rules present */ + + /* Values for "inv" field in struct ipt_ip. */ + #define IPT_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -82,6 +82,9 @@ ip_packet_match(const struct iphdr *ip, + + #define FWINV(bool, invflg) ((bool) ^ !!(ipinfo->invflags & (invflg))) + ++ if (ipinfo->flags & IPT_F_NO_DEF_MATCH) ++ return true; ++ + if (FWINV((ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, + IPT_INV_SRCIP) || + FWINV((ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, +@@ -135,6 +138,29 @@ ip_packet_match(const struct iphdr *ip, + return true; + } + ++static void ++ip_checkdefault(struct ipt_ip *ip) ++{ ++ static const char iface_mask[IFNAMSIZ] = {}; ++ ++ if (ip->invflags || ip->flags & IPT_F_FRAG) ++ return; ++ ++ if (memcmp(ip->iniface_mask, iface_mask, IFNAMSIZ) != 0) ++ return; ++ ++ if (memcmp(ip->outiface_mask, iface_mask, IFNAMSIZ) != 0) ++ return; ++ ++ if (ip->smsk.s_addr || ip->dmsk.s_addr) ++ return; ++ ++ if (ip->proto) ++ return; ++ ++ ip->flags |= IPT_F_NO_DEF_MATCH; ++} ++ + static bool + ip_checkentry(const struct ipt_ip *ip) + { +@@ -565,7 +591,7 @@ static void cleanup_match(struct xt_entr + } + + static int +-check_entry(const struct ipt_entry *e, const char *name) ++check_entry(struct ipt_entry *e, const char *name) + { + const struct xt_entry_target *t; + +@@ -574,6 +600,8 @@ check_entry(const struct ipt_entry *e, c + return -EINVAL; + } + ++ ip_checkdefault(&e->ip); ++ + if (e->target_offset + sizeof(struct xt_entry_target) > + e->next_offset) + return -EINVAL; +@@ -935,6 +963,7 @@ copy_entries_to_user(unsigned int total_ + const struct xt_table_info *private = table->private; + int ret = 0; + const void *loc_cpu_entry; ++ u8 flags; + + counters = alloc_counters(table); + if (IS_ERR(counters)) +@@ -965,6 +994,14 @@ copy_entries_to_user(unsigned int total_ + ret = -EFAULT; + goto free_counters; + } ++ ++ flags = e->ip.flags & IPT_F_MASK; ++ if (copy_to_user(userptr + off ++ + offsetof(struct ipt_entry, ip.flags), ++ &flags, sizeof(flags)) != 0) { ++ ret = -EFAULT; ++ goto free_counters; ++ } + + for (i = sizeof(struct ipt_entry); + i < e->target_offset; diff --git a/target/linux/generic/patches-4.0/611-netfilter_match_bypass_default_table.patch b/target/linux/generic/patches-4.0/611-netfilter_match_bypass_default_table.patch new file mode 100644 index 0000000..ef993c8 --- /dev/null +++ b/target/linux/generic/patches-4.0/611-netfilter_match_bypass_default_table.patch @@ -0,0 +1,94 @@ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -310,6 +310,33 @@ struct ipt_entry *ipt_next_entry(const s + return (void *)entry + entry->next_offset; + } + ++static bool ++ipt_handle_default_rule(struct ipt_entry *e, unsigned int *verdict) ++{ ++ struct xt_entry_target *t; ++ struct xt_standard_target *st; ++ ++ if (e->target_offset != sizeof(struct ipt_entry)) ++ return false; ++ ++ if (!(e->ip.flags & IPT_F_NO_DEF_MATCH)) ++ return false; ++ ++ t = ipt_get_target(e); ++ if (t->u.kernel.target->target) ++ return false; ++ ++ st = (struct xt_standard_target *) t; ++ if (st->verdict == XT_RETURN) ++ return false; ++ ++ if (st->verdict >= 0) ++ return false; ++ ++ *verdict = (unsigned)(-st->verdict) - 1; ++ return true; ++} ++ + /* Returns one of the generic firewall policies, like NF_ACCEPT. */ + unsigned int + ipt_do_table(struct sk_buff *skb, +@@ -331,9 +358,33 @@ ipt_do_table(struct sk_buff *skb, + unsigned int addend; + + /* Initialization */ ++ IP_NF_ASSERT(table->valid_hooks & (1 << hook)); ++ local_bh_disable(); ++ private = table->private; ++ cpu = smp_processor_id(); ++ /* ++ * Ensure we load private-> members after we've fetched the base ++ * pointer. ++ */ ++ smp_read_barrier_depends(); ++ table_base = private->entries[cpu]; ++ ++ e = get_entry(table_base, private->hook_entry[hook]); ++ if (ipt_handle_default_rule(e, &verdict)) { ++ ADD_COUNTER(e->counters, skb->len, 1); ++ local_bh_enable(); ++ return verdict; ++ } ++ + ip = ip_hdr(skb); + indev = in ? in->name : nulldevname; + outdev = out ? out->name : nulldevname; ++ ++ addend = xt_write_recseq_begin(); ++ jumpstack = (struct ipt_entry **)private->jumpstack[cpu]; ++ stackptr = per_cpu_ptr(private->stackptr, cpu); ++ origptr = *stackptr; ++ + /* We handle fragments by dealing with the first fragment as + * if it was a normal packet. All other fragments are treated + * normally, except that they will NEVER match rules that ask +@@ -348,23 +399,6 @@ ipt_do_table(struct sk_buff *skb, + acpar.family = NFPROTO_IPV4; + acpar.hooknum = hook; + +- IP_NF_ASSERT(table->valid_hooks & (1 << hook)); +- local_bh_disable(); +- addend = xt_write_recseq_begin(); +- private = table->private; +- cpu = smp_processor_id(); +- /* +- * Ensure we load private-> members after we've fetched the base +- * pointer. +- */ +- smp_read_barrier_depends(); +- table_base = private->entries[cpu]; +- jumpstack = (struct ipt_entry **)private->jumpstack[cpu]; +- stackptr = per_cpu_ptr(private->stackptr, cpu); +- origptr = *stackptr; +- +- e = get_entry(table_base, private->hook_entry[hook]); +- + pr_debug("Entering %s(hook %u); sp at %u (UF %p)\n", + table->name, hook, origptr, + get_entry(table_base, private->underflow[hook])); diff --git a/target/linux/generic/patches-4.0/612-netfilter_match_reduce_memory_access.patch b/target/linux/generic/patches-4.0/612-netfilter_match_reduce_memory_access.patch new file mode 100644 index 0000000..72172d8 --- /dev/null +++ b/target/linux/generic/patches-4.0/612-netfilter_match_reduce_memory_access.patch @@ -0,0 +1,16 @@ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -85,9 +85,11 @@ ip_packet_match(const struct iphdr *ip, + if (ipinfo->flags & IPT_F_NO_DEF_MATCH) + return true; + +- if (FWINV((ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, ++ if (FWINV(ipinfo->smsk.s_addr && ++ (ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, + IPT_INV_SRCIP) || +- FWINV((ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, ++ FWINV(ipinfo->dmsk.s_addr && ++ (ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, + IPT_INV_DSTIP)) { + dprintf("Source or dest mismatch.\n"); + diff --git a/target/linux/generic/patches-4.0/613-netfilter_optional_tcp_window_check.patch b/target/linux/generic/patches-4.0/613-netfilter_optional_tcp_window_check.patch new file mode 100644 index 0000000..1d3b37c --- /dev/null +++ b/target/linux/generic/patches-4.0/613-netfilter_optional_tcp_window_check.patch @@ -0,0 +1,36 @@ +--- a/net/netfilter/nf_conntrack_proto_tcp.c ++++ b/net/netfilter/nf_conntrack_proto_tcp.c +@@ -33,6 +33,9 @@ + #include + #include + ++/* Do not check the TCP window for incoming packets */ ++static int nf_ct_tcp_no_window_check __read_mostly = 1; ++ + /* "Be conservative in what you do, + be liberal in what you accept from others." + If it's non-zero, we mark only out of window RST segments as INVALID. */ +@@ -515,6 +518,9 @@ static bool tcp_in_window(const struct n + s32 receiver_offset; + bool res, in_recv_win; + ++ if (nf_ct_tcp_no_window_check) ++ return true; ++ + /* + * Get the required data from the packet. + */ +@@ -1452,6 +1458,13 @@ static struct ctl_table tcp_sysctl_table + .mode = 0644, + .proc_handler = proc_dointvec, + }, ++ { ++ .procname = "nf_conntrack_tcp_no_window_check", ++ .data = &nf_ct_tcp_no_window_check, ++ .maxlen = sizeof(unsigned int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec, ++ }, + { } + }; + diff --git a/target/linux/generic/patches-4.0/615-netfilter_add_xt_id_match.patch b/target/linux/generic/patches-4.0/615-netfilter_add_xt_id_match.patch new file mode 100644 index 0000000..50607ca --- /dev/null +++ b/target/linux/generic/patches-4.0/615-netfilter_add_xt_id_match.patch @@ -0,0 +1,95 @@ +--- a/include/uapi/linux/netfilter/Kbuild ++++ b/include/uapi/linux/netfilter/Kbuild +@@ -55,6 +55,7 @@ header-y += xt_ecn.h + header-y += xt_esp.h + header-y += xt_hashlimit.h + header-y += xt_helper.h ++header-y += xt_id.h + header-y += xt_ipcomp.h + header-y += xt_iprange.h + header-y += xt_ipvs.h +--- /dev/null ++++ b/include/uapi/linux/netfilter/xt_id.h +@@ -0,0 +1,8 @@ ++#ifndef _XT_ID_H ++#define _XT_ID_H ++ ++struct xt_id_info { ++ u32 id; ++}; ++ ++#endif /* XT_ID_H */ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -1174,6 +1174,13 @@ config NETFILTER_XT_MATCH_IPCOMP + + To compile it as a module, choose M here. If unsure, say N. + ++config NETFILTER_XT_MATCH_ID ++ tristate '"id" match support' ++ depends on NETFILTER_ADVANCED ++ ---help--- ++ This option adds a `id' dummy-match, which allows you to put ++ numeric IDs into your iptables ruleset. ++ + config NETFILTER_XT_MATCH_IPRANGE + tristate '"iprange" address range match support' + depends on NETFILTER_ADVANCED +--- a/net/netfilter/Makefile ++++ b/net/netfilter/Makefile +@@ -145,6 +145,7 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_ESP) += + obj-$(CONFIG_NETFILTER_XT_MATCH_HASHLIMIT) += xt_hashlimit.o + obj-$(CONFIG_NETFILTER_XT_MATCH_HELPER) += xt_helper.o + obj-$(CONFIG_NETFILTER_XT_MATCH_HL) += xt_hl.o ++obj-$(CONFIG_NETFILTER_XT_MATCH_ID) += xt_id.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPCOMP) += xt_ipcomp.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPRANGE) += xt_iprange.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPVS) += xt_ipvs.o +--- /dev/null ++++ b/net/netfilter/xt_id.c +@@ -0,0 +1,45 @@ ++/* ++ * Implements a dummy match to allow attaching IDs to rules ++ * ++ * 2014-08-01 Jo-Philipp Wich ++ */ ++ ++#include ++#include ++#include ++#include ++ ++MODULE_AUTHOR("Jo-Philipp Wich "); ++MODULE_DESCRIPTION("Xtables: No-op match which can be tagged with a 32bit ID"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("ipt_id"); ++MODULE_ALIAS("ip6t_id"); ++ ++static bool ++id_mt(const struct sk_buff *skb, struct xt_action_param *par) ++{ ++ /* We always match */ ++ return true; ++} ++ ++static struct xt_match id_mt_reg __read_mostly = { ++ .name = "id", ++ .revision = 0, ++ .family = NFPROTO_UNSPEC, ++ .match = id_mt, ++ .matchsize = sizeof(struct xt_id_info), ++ .me = THIS_MODULE, ++}; ++ ++static int __init id_mt_init(void) ++{ ++ return xt_register_match(&id_mt_reg); ++} ++ ++static void __exit id_mt_exit(void) ++{ ++ xt_unregister_match(&id_mt_reg); ++} ++ ++module_init(id_mt_init); ++module_exit(id_mt_exit); diff --git a/target/linux/generic/patches-4.0/616-net_optimize_xfrm_calls.patch b/target/linux/generic/patches-4.0/616-net_optimize_xfrm_calls.patch new file mode 100644 index 0000000..2a64d54 --- /dev/null +++ b/target/linux/generic/patches-4.0/616-net_optimize_xfrm_calls.patch @@ -0,0 +1,12 @@ +--- a/net/netfilter/nf_nat_core.c ++++ b/net/netfilter/nf_nat_core.c +@@ -90,6 +90,9 @@ int nf_xfrm_me_harder(struct sk_buff *sk + struct dst_entry *dst; + int err; + ++ if (skb->dev && !dev_net(skb->dev)->xfrm.policy_count[XFRM_POLICY_OUT]) ++ return 0; ++ + err = xfrm_decode_session(skb, &fl, family); + if (err < 0) + return err; diff --git a/target/linux/generic/patches-4.0/620-sched_esfq.patch b/target/linux/generic/patches-4.0/620-sched_esfq.patch new file mode 100644 index 0000000..e1b473b --- /dev/null +++ b/target/linux/generic/patches-4.0/620-sched_esfq.patch @@ -0,0 +1,791 @@ +--- a/include/uapi/linux/pkt_sched.h ++++ b/include/uapi/linux/pkt_sched.h +@@ -226,6 +226,33 @@ struct tc_sfq_xstats { + __s32 allot; + }; + ++/* ESFQ section */ ++ ++enum ++{ ++ /* traditional */ ++ TCA_SFQ_HASH_CLASSIC, ++ TCA_SFQ_HASH_DST, ++ TCA_SFQ_HASH_SRC, ++ TCA_SFQ_HASH_FWMARK, ++ /* conntrack */ ++ TCA_SFQ_HASH_CTORIGDST, ++ TCA_SFQ_HASH_CTORIGSRC, ++ TCA_SFQ_HASH_CTREPLDST, ++ TCA_SFQ_HASH_CTREPLSRC, ++ TCA_SFQ_HASH_CTNATCHG, ++}; ++ ++struct tc_esfq_qopt ++{ ++ unsigned quantum; /* Bytes per round allocated to flow */ ++ int perturb_period; /* Period of hash perturbation */ ++ __u32 limit; /* Maximal packets in queue */ ++ unsigned divisor; /* Hash divisor */ ++ unsigned flows; /* Maximal number of flows */ ++ unsigned hash_kind; /* Hash function to use for flow identification */ ++}; ++ + /* RED section */ + + enum { +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -149,6 +149,37 @@ config NET_SCH_SFQ + To compile this code as a module, choose M here: the + module will be called sch_sfq. + ++config NET_SCH_ESFQ ++ tristate "Enhanced Stochastic Fairness Queueing (ESFQ)" ++ ---help--- ++ Say Y here if you want to use the Enhanced Stochastic Fairness ++ Queueing (ESFQ) packet scheduling algorithm for some of your network ++ devices or as a leaf discipline for a classful qdisc such as HTB or ++ CBQ (see the top of for details and ++ references to the SFQ algorithm). ++ ++ This is an enchanced SFQ version which allows you to control some ++ hardcoded values in the SFQ scheduler. ++ ++ ESFQ also adds control of the hash function used to identify packet ++ flows. The original SFQ discipline hashes by connection; ESFQ add ++ several other hashing methods, such as by src IP or by dst IP, which ++ can be more fair to users in some networking situations. ++ ++ To compile this code as a module, choose M here: the ++ module will be called sch_esfq. ++ ++config NET_SCH_ESFQ_NFCT ++ bool "Connection Tracking Hash Types" ++ depends on NET_SCH_ESFQ && NF_CONNTRACK ++ ---help--- ++ Say Y here to enable support for hashing based on netfilter connection ++ tracking information. This is useful for a router that is also using ++ NAT to connect privately-addressed hosts to the Internet. If you want ++ to provide fair distribution of upstream bandwidth, ESFQ must use ++ connection tracking information, since all outgoing packets will share ++ the same source address. ++ + config NET_SCH_TEQL + tristate "True Link Equalizer (TEQL)" + ---help--- +--- a/net/sched/Makefile ++++ b/net/sched/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_NET_SCH_INGRESS) += sch_ing + obj-$(CONFIG_NET_SCH_DSMARK) += sch_dsmark.o + obj-$(CONFIG_NET_SCH_SFB) += sch_sfb.o + obj-$(CONFIG_NET_SCH_SFQ) += sch_sfq.o ++obj-$(CONFIG_NET_SCH_ESFQ) += sch_esfq.o + obj-$(CONFIG_NET_SCH_TBF) += sch_tbf.o + obj-$(CONFIG_NET_SCH_TEQL) += sch_teql.o + obj-$(CONFIG_NET_SCH_PRIO) += sch_prio.o +--- /dev/null ++++ b/net/sched/sch_esfq.c +@@ -0,0 +1,702 @@ ++/* ++ * net/sched/sch_esfq.c Extended Stochastic Fairness Queueing discipline. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Authors: Alexey Kuznetsov, ++ * ++ * Changes: Alexander Atanasov, ++ * Added dynamic depth,limit,divisor,hash_kind options. ++ * Added dst and src hashes. ++ * ++ * Alexander Clouter, ++ * Ported ESFQ to Linux 2.6. ++ * ++ * Corey Hickey, ++ * Maintenance of the Linux 2.6 port. ++ * Added fwmark hash (thanks to Robert Kurjata). ++ * Added usage of jhash. ++ * Added conntrack support. ++ * Added ctnatchg hash (thanks to Ben Pfountz). ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++#include ++#endif ++ ++/* Stochastic Fairness Queuing algorithm. ++ For more comments look at sch_sfq.c. ++ The difference is that you can change limit, depth, ++ hash table size and choose alternate hash types. ++ ++ classic: same as in sch_sfq.c ++ dst: destination IP address ++ src: source IP address ++ fwmark: netfilter mark value ++ ctorigdst: original destination IP address ++ ctorigsrc: original source IP address ++ ctrepldst: reply destination IP address ++ ctreplsrc: reply source IP ++ ++*/ ++ ++#define ESFQ_HEAD 0 ++#define ESFQ_TAIL 1 ++ ++/* This type should contain at least SFQ_DEPTH*2 values */ ++typedef unsigned int esfq_index; ++ ++struct esfq_head ++{ ++ esfq_index next; ++ esfq_index prev; ++}; ++ ++struct esfq_sched_data ++{ ++/* Parameters */ ++ int perturb_period; ++ unsigned quantum; /* Allotment per round: MUST BE >= MTU */ ++ int limit; ++ unsigned depth; ++ unsigned hash_divisor; ++ unsigned hash_kind; ++/* Variables */ ++ struct timer_list perturb_timer; ++ int perturbation; ++ esfq_index tail; /* Index of current slot in round */ ++ esfq_index max_depth; /* Maximal depth */ ++ ++ esfq_index *ht; /* Hash table */ ++ esfq_index *next; /* Active slots link */ ++ short *allot; /* Current allotment per slot */ ++ unsigned short *hash; /* Hash value indexed by slots */ ++ struct sk_buff_head *qs; /* Slot queue */ ++ struct esfq_head *dep; /* Linked list of slots, indexed by depth */ ++}; ++ ++/* This contains the info we will hash. */ ++struct esfq_packet_info ++{ ++ u32 proto; /* protocol or port */ ++ u32 src; /* source from packet header */ ++ u32 dst; /* destination from packet header */ ++ u32 ctorigsrc; /* original source from conntrack */ ++ u32 ctorigdst; /* original destination from conntrack */ ++ u32 ctreplsrc; /* reply source from conntrack */ ++ u32 ctrepldst; /* reply destination from conntrack */ ++ u32 mark; /* netfilter mark (fwmark) */ ++}; ++ ++static __inline__ unsigned esfq_jhash_1word(struct esfq_sched_data *q,u32 a) ++{ ++ return jhash_1word(a, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static __inline__ unsigned esfq_jhash_2words(struct esfq_sched_data *q, u32 a, u32 b) ++{ ++ return jhash_2words(a, b, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static __inline__ unsigned esfq_jhash_3words(struct esfq_sched_data *q, u32 a, u32 b, u32 c) ++{ ++ return jhash_3words(a, b, c, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static unsigned esfq_hash(struct esfq_sched_data *q, struct sk_buff *skb) ++{ ++ struct esfq_packet_info info; ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ enum ip_conntrack_info ctinfo; ++ struct nf_conn *ct = nf_ct_get(skb, &ctinfo); ++#endif ++ ++ switch (skb->protocol) { ++ case __constant_htons(ETH_P_IP): ++ { ++ struct iphdr *iph = ip_hdr(skb); ++ info.dst = iph->daddr; ++ info.src = iph->saddr; ++ if (!(iph->frag_off&htons(IP_MF|IP_OFFSET)) && ++ (iph->protocol == IPPROTO_TCP || ++ iph->protocol == IPPROTO_UDP || ++ iph->protocol == IPPROTO_SCTP || ++ iph->protocol == IPPROTO_DCCP || ++ iph->protocol == IPPROTO_ESP)) ++ info.proto = *(((u32*)iph) + iph->ihl); ++ else ++ info.proto = iph->protocol; ++ break; ++ } ++ case __constant_htons(ETH_P_IPV6): ++ { ++ struct ipv6hdr *iph = ipv6_hdr(skb); ++ /* Hash ipv6 addresses into a u32. This isn't ideal, ++ * but the code is simple. */ ++ info.dst = jhash2(iph->daddr.s6_addr32, 4, q->perturbation); ++ info.src = jhash2(iph->saddr.s6_addr32, 4, q->perturbation); ++ if (iph->nexthdr == IPPROTO_TCP || ++ iph->nexthdr == IPPROTO_UDP || ++ iph->nexthdr == IPPROTO_SCTP || ++ iph->nexthdr == IPPROTO_DCCP || ++ iph->nexthdr == IPPROTO_ESP) ++ info.proto = *(u32*)&iph[1]; ++ else ++ info.proto = iph->nexthdr; ++ break; ++ } ++ default: ++ info.dst = (u32)(unsigned long)skb_dst(skb); ++ info.src = (u32)(unsigned long)skb->sk; ++ info.proto = skb->protocol; ++ } ++ ++ info.mark = skb->mark; ++ ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ /* defaults if there is no conntrack info */ ++ info.ctorigsrc = info.src; ++ info.ctorigdst = info.dst; ++ info.ctreplsrc = info.dst; ++ info.ctrepldst = info.src; ++ /* collect conntrack info */ ++ if (ct && ct != &nf_conntrack_untracked) { ++ if (skb->protocol == __constant_htons(ETH_P_IP)) { ++ info.ctorigsrc = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip; ++ info.ctorigdst = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.u3.ip; ++ info.ctreplsrc = ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip; ++ info.ctrepldst = ct->tuplehash[IP_CT_DIR_REPLY].tuple.dst.u3.ip; ++ } ++ else if (skb->protocol == __constant_htons(ETH_P_IPV6)) { ++ /* Again, hash ipv6 addresses into a single u32. */ ++ info.ctorigsrc = jhash2(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip6, 4, q->perturbation); ++ info.ctorigdst = jhash2(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.u3.ip6, 4, q->perturbation); ++ info.ctreplsrc = jhash2(ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip6, 4, q->perturbation); ++ info.ctrepldst = jhash2(ct->tuplehash[IP_CT_DIR_REPLY].tuple.dst.u3.ip6, 4, q->perturbation); ++ } ++ ++ } ++#endif ++ ++ switch(q->hash_kind) { ++ case TCA_SFQ_HASH_CLASSIC: ++ return esfq_jhash_3words(q, info.dst, info.src, info.proto); ++ case TCA_SFQ_HASH_DST: ++ return esfq_jhash_1word(q, info.dst); ++ case TCA_SFQ_HASH_SRC: ++ return esfq_jhash_1word(q, info.src); ++ case TCA_SFQ_HASH_FWMARK: ++ return esfq_jhash_1word(q, info.mark); ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ case TCA_SFQ_HASH_CTORIGDST: ++ return esfq_jhash_1word(q, info.ctorigdst); ++ case TCA_SFQ_HASH_CTORIGSRC: ++ return esfq_jhash_1word(q, info.ctorigsrc); ++ case TCA_SFQ_HASH_CTREPLDST: ++ return esfq_jhash_1word(q, info.ctrepldst); ++ case TCA_SFQ_HASH_CTREPLSRC: ++ return esfq_jhash_1word(q, info.ctreplsrc); ++ case TCA_SFQ_HASH_CTNATCHG: ++ { ++ if (info.ctorigdst == info.ctreplsrc) ++ return esfq_jhash_1word(q, info.ctorigsrc); ++ return esfq_jhash_1word(q, info.ctreplsrc); ++ } ++#endif ++ default: ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Unknown hash method. Falling back to classic.\n"); ++ } ++ return esfq_jhash_3words(q, info.dst, info.src, info.proto); ++} ++ ++static inline void esfq_link(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ int d = q->qs[x].qlen + q->depth; ++ ++ p = d; ++ n = q->dep[d].next; ++ q->dep[x].next = n; ++ q->dep[x].prev = p; ++ q->dep[p].next = q->dep[n].prev = x; ++} ++ ++static inline void esfq_dec(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ ++ n = q->dep[x].next; ++ p = q->dep[x].prev; ++ q->dep[p].next = n; ++ q->dep[n].prev = p; ++ ++ if (n == p && q->max_depth == q->qs[x].qlen + 1) ++ q->max_depth--; ++ ++ esfq_link(q, x); ++} ++ ++static inline void esfq_inc(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ int d; ++ ++ n = q->dep[x].next; ++ p = q->dep[x].prev; ++ q->dep[p].next = n; ++ q->dep[n].prev = p; ++ d = q->qs[x].qlen; ++ if (q->max_depth < d) ++ q->max_depth = d; ++ ++ esfq_link(q, x); ++} ++ ++static unsigned int esfq_drop(struct Qdisc *sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_index d = q->max_depth; ++ struct sk_buff *skb; ++ unsigned int len; ++ ++ /* Queue is full! Find the longest slot and ++ drop a packet from it */ ++ ++ if (d > 1) { ++ esfq_index x = q->dep[d+q->depth].next; ++ skb = q->qs[x].prev; ++ len = skb->len; ++ __skb_unlink(skb, &q->qs[x]); ++ kfree_skb(skb); ++ esfq_dec(q, x); ++ sch->q.qlen--; ++ sch->qstats.drops++; ++ sch->qstats.backlog -= len; ++ return len; ++ } ++ ++ if (d == 1) { ++ /* It is difficult to believe, but ALL THE SLOTS HAVE LENGTH 1. */ ++ d = q->next[q->tail]; ++ q->next[q->tail] = q->next[d]; ++ q->allot[q->next[d]] += q->quantum; ++ skb = q->qs[d].prev; ++ len = skb->len; ++ __skb_unlink(skb, &q->qs[d]); ++ kfree_skb(skb); ++ esfq_dec(q, d); ++ sch->q.qlen--; ++ q->ht[q->hash[d]] = q->depth; ++ sch->qstats.drops++; ++ sch->qstats.backlog -= len; ++ return len; ++ } ++ ++ return 0; ++} ++ ++static void esfq_q_enqueue(struct sk_buff *skb, struct esfq_sched_data *q, unsigned int end) ++{ ++ unsigned hash = esfq_hash(q, skb); ++ unsigned depth = q->depth; ++ esfq_index x; ++ ++ x = q->ht[hash]; ++ if (x == depth) { ++ q->ht[hash] = x = q->dep[depth].next; ++ q->hash[x] = hash; ++ } ++ ++ if (end == ESFQ_TAIL) ++ __skb_queue_tail(&q->qs[x], skb); ++ else ++ __skb_queue_head(&q->qs[x], skb); ++ ++ esfq_inc(q, x); ++ if (q->qs[x].qlen == 1) { /* The flow is new */ ++ if (q->tail == depth) { /* It is the first flow */ ++ q->tail = x; ++ q->next[x] = x; ++ q->allot[x] = q->quantum; ++ } else { ++ q->next[x] = q->next[q->tail]; ++ q->next[q->tail] = x; ++ q->tail = x; ++ } ++ } ++} ++ ++static int esfq_enqueue(struct sk_buff *skb, struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_q_enqueue(skb, q, ESFQ_TAIL); ++ sch->qstats.backlog += skb->len; ++ if (++sch->q.qlen < q->limit-1) { ++ sch->bstats.bytes += skb->len; ++ sch->bstats.packets++; ++ return 0; ++ } ++ ++ sch->qstats.drops++; ++ esfq_drop(sch); ++ return NET_XMIT_CN; ++} ++ ++static struct sk_buff *esfq_peek(struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_index a; ++ ++ /* No active slots */ ++ if (q->tail == q->depth) ++ return NULL; ++ ++ a = q->next[q->tail]; ++ return skb_peek(&q->qs[a]); ++} ++ ++static struct sk_buff *esfq_q_dequeue(struct esfq_sched_data *q) ++{ ++ struct sk_buff *skb; ++ unsigned depth = q->depth; ++ esfq_index a, old_a; ++ ++ /* No active slots */ ++ if (q->tail == depth) ++ return NULL; ++ ++ a = old_a = q->next[q->tail]; ++ ++ /* Grab packet */ ++ skb = __skb_dequeue(&q->qs[a]); ++ esfq_dec(q, a); ++ ++ /* Is the slot empty? */ ++ if (q->qs[a].qlen == 0) { ++ q->ht[q->hash[a]] = depth; ++ a = q->next[a]; ++ if (a == old_a) { ++ q->tail = depth; ++ return skb; ++ } ++ q->next[q->tail] = a; ++ q->allot[a] += q->quantum; ++ } else if ((q->allot[a] -= skb->len) <= 0) { ++ q->tail = a; ++ a = q->next[a]; ++ q->allot[a] += q->quantum; ++ } ++ ++ return skb; ++} ++ ++static struct sk_buff *esfq_dequeue(struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ struct sk_buff *skb; ++ ++ skb = esfq_q_dequeue(q); ++ if (skb == NULL) ++ return NULL; ++ sch->q.qlen--; ++ sch->qstats.backlog -= skb->len; ++ return skb; ++} ++ ++static void esfq_q_destroy(struct esfq_sched_data *q) ++{ ++ del_timer(&q->perturb_timer); ++ if(q->ht) ++ kfree(q->ht); ++ if(q->dep) ++ kfree(q->dep); ++ if(q->next) ++ kfree(q->next); ++ if(q->allot) ++ kfree(q->allot); ++ if(q->hash) ++ kfree(q->hash); ++ if(q->qs) ++ kfree(q->qs); ++} ++ ++static void esfq_destroy(struct Qdisc *sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_q_destroy(q); ++} ++ ++ ++static void esfq_reset(struct Qdisc* sch) ++{ ++ struct sk_buff *skb; ++ ++ while ((skb = esfq_dequeue(sch)) != NULL) ++ kfree_skb(skb); ++} ++ ++static void esfq_perturbation(unsigned long arg) ++{ ++ struct Qdisc *sch = (struct Qdisc*)arg; ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ ++ q->perturbation = prandom_u32()&0x1F; ++ ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } ++} ++ ++static unsigned int esfq_check_hash(unsigned int kind) ++{ ++ switch (kind) { ++ case TCA_SFQ_HASH_CTORIGDST: ++ case TCA_SFQ_HASH_CTORIGSRC: ++ case TCA_SFQ_HASH_CTREPLDST: ++ case TCA_SFQ_HASH_CTREPLSRC: ++ case TCA_SFQ_HASH_CTNATCHG: ++#ifndef CONFIG_NET_SCH_ESFQ_NFCT ++ { ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Conntrack hash types disabled in kernel config. Falling back to classic.\n"); ++ return TCA_SFQ_HASH_CLASSIC; ++ } ++#endif ++ case TCA_SFQ_HASH_CLASSIC: ++ case TCA_SFQ_HASH_DST: ++ case TCA_SFQ_HASH_SRC: ++ case TCA_SFQ_HASH_FWMARK: ++ return kind; ++ default: ++ { ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Unknown hash type. Falling back to classic.\n"); ++ return TCA_SFQ_HASH_CLASSIC; ++ } ++ } ++} ++ ++static int esfq_q_init(struct esfq_sched_data *q, struct nlattr *opt) ++{ ++ struct tc_esfq_qopt *ctl = nla_data(opt); ++ esfq_index p = ~0U/2; ++ int i; ++ ++ if (opt && opt->nla_len < nla_attr_size(sizeof(*ctl))) ++ return -EINVAL; ++ ++ q->perturbation = 0; ++ q->hash_kind = TCA_SFQ_HASH_CLASSIC; ++ q->max_depth = 0; ++ if (opt == NULL) { ++ q->perturb_period = 0; ++ q->hash_divisor = 1024; ++ q->tail = q->limit = q->depth = 128; ++ ++ } else { ++ struct tc_esfq_qopt *ctl = nla_data(opt); ++ if (ctl->quantum) ++ q->quantum = ctl->quantum; ++ q->perturb_period = ctl->perturb_period*HZ; ++ q->hash_divisor = ctl->divisor ? : 1024; ++ q->tail = q->limit = q->depth = ctl->flows ? : 128; ++ ++ if ( q->depth > p - 1 ) ++ return -EINVAL; ++ ++ if (ctl->limit) ++ q->limit = min_t(u32, ctl->limit, q->depth); ++ ++ if (ctl->hash_kind) { ++ q->hash_kind = esfq_check_hash(ctl->hash_kind); ++ } ++ } ++ ++ q->ht = kmalloc(q->hash_divisor*sizeof(esfq_index), GFP_KERNEL); ++ if (!q->ht) ++ goto err_case; ++ q->dep = kmalloc((1+q->depth*2)*sizeof(struct esfq_head), GFP_KERNEL); ++ if (!q->dep) ++ goto err_case; ++ q->next = kmalloc(q->depth*sizeof(esfq_index), GFP_KERNEL); ++ if (!q->next) ++ goto err_case; ++ q->allot = kmalloc(q->depth*sizeof(short), GFP_KERNEL); ++ if (!q->allot) ++ goto err_case; ++ q->hash = kmalloc(q->depth*sizeof(unsigned short), GFP_KERNEL); ++ if (!q->hash) ++ goto err_case; ++ q->qs = kmalloc(q->depth*sizeof(struct sk_buff_head), GFP_KERNEL); ++ if (!q->qs) ++ goto err_case; ++ ++ for (i=0; i< q->hash_divisor; i++) ++ q->ht[i] = q->depth; ++ for (i=0; idepth; i++) { ++ skb_queue_head_init(&q->qs[i]); ++ q->dep[i+q->depth].next = i+q->depth; ++ q->dep[i+q->depth].prev = i+q->depth; ++ } ++ ++ for (i=0; idepth; i++) ++ esfq_link(q, i); ++ return 0; ++err_case: ++ esfq_q_destroy(q); ++ return -ENOBUFS; ++} ++ ++static int esfq_init(struct Qdisc *sch, struct nlattr *opt) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ int err; ++ ++ q->quantum = psched_mtu(qdisc_dev(sch)); /* default */ ++ if ((err = esfq_q_init(q, opt))) ++ return err; ++ ++ init_timer(&q->perturb_timer); ++ q->perturb_timer.data = (unsigned long)sch; ++ q->perturb_timer.function = esfq_perturbation; ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } ++ ++ return 0; ++} ++ ++static int esfq_change(struct Qdisc *sch, struct nlattr *opt) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ struct esfq_sched_data new; ++ struct sk_buff *skb; ++ int err; ++ ++ /* set up new queue */ ++ memset(&new, 0, sizeof(struct esfq_sched_data)); ++ new.quantum = psched_mtu(qdisc_dev(sch)); /* default */ ++ if ((err = esfq_q_init(&new, opt))) ++ return err; ++ ++ /* copy all packets from the old queue to the new queue */ ++ sch_tree_lock(sch); ++ while ((skb = esfq_q_dequeue(q)) != NULL) ++ esfq_q_enqueue(skb, &new, ESFQ_TAIL); ++ ++ /* clean up the old queue */ ++ esfq_q_destroy(q); ++ ++ /* copy elements of the new queue into the old queue */ ++ q->perturb_period = new.perturb_period; ++ q->quantum = new.quantum; ++ q->limit = new.limit; ++ q->depth = new.depth; ++ q->hash_divisor = new.hash_divisor; ++ q->hash_kind = new.hash_kind; ++ q->tail = new.tail; ++ q->max_depth = new.max_depth; ++ q->ht = new.ht; ++ q->dep = new.dep; ++ q->next = new.next; ++ q->allot = new.allot; ++ q->hash = new.hash; ++ q->qs = new.qs; ++ ++ /* finish up */ ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } else { ++ q->perturbation = 0; ++ } ++ sch_tree_unlock(sch); ++ return 0; ++} ++ ++static int esfq_dump(struct Qdisc *sch, struct sk_buff *skb) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ unsigned char *b = skb_tail_pointer(skb); ++ struct tc_esfq_qopt opt; ++ ++ opt.quantum = q->quantum; ++ opt.perturb_period = q->perturb_period/HZ; ++ ++ opt.limit = q->limit; ++ opt.divisor = q->hash_divisor; ++ opt.flows = q->depth; ++ opt.hash_kind = q->hash_kind; ++ ++ if (nla_put(skb, TCA_OPTIONS, sizeof(opt), &opt)) ++ goto nla_put_failure; ++ ++ return skb->len; ++ ++nla_put_failure: ++ nlmsg_trim(skb, b); ++ return -1; ++} ++ ++static struct Qdisc_ops esfq_qdisc_ops = ++{ ++ .next = NULL, ++ .cl_ops = NULL, ++ .id = "esfq", ++ .priv_size = sizeof(struct esfq_sched_data), ++ .enqueue = esfq_enqueue, ++ .dequeue = esfq_dequeue, ++ .peek = esfq_peek, ++ .drop = esfq_drop, ++ .init = esfq_init, ++ .reset = esfq_reset, ++ .destroy = esfq_destroy, ++ .change = esfq_change, ++ .dump = esfq_dump, ++ .owner = THIS_MODULE, ++}; ++ ++static int __init esfq_module_init(void) ++{ ++ return register_qdisc(&esfq_qdisc_ops); ++} ++static void __exit esfq_module_exit(void) ++{ ++ unregister_qdisc(&esfq_qdisc_ops); ++} ++module_init(esfq_module_init) ++module_exit(esfq_module_exit) ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.0/630-packet_socket_type.patch b/target/linux/generic/patches-4.0/630-packet_socket_type.patch new file mode 100644 index 0000000..3a39f2a --- /dev/null +++ b/target/linux/generic/patches-4.0/630-packet_socket_type.patch @@ -0,0 +1,134 @@ +This patch allows the user to specify desired packet types (outgoing, +broadcast, unicast, etc.) on packet sockets via setsockopt. +This can reduce the load in situations where only a limited number +of packet types are necessary + +Signed-off-by: Felix Fietkau + +--- a/include/uapi/linux/if_packet.h ++++ b/include/uapi/linux/if_packet.h +@@ -31,6 +31,8 @@ struct sockaddr_ll { + #define PACKET_KERNEL 7 /* To kernel space */ + /* Unused, PACKET_FASTROUTE and PACKET_LOOPBACK are invisible to user space */ + #define PACKET_FASTROUTE 6 /* Fastrouted frame */ ++#define PACKET_MASK_ANY 0xffffffff /* mask for packet type bits */ ++ + + /* Packet socket options */ + +@@ -54,6 +56,7 @@ struct sockaddr_ll { + #define PACKET_FANOUT 18 + #define PACKET_TX_HAS_OFF 19 + #define PACKET_QDISC_BYPASS 20 ++#define PACKET_RECV_TYPE 21 + + #define PACKET_FANOUT_HASH 0 + #define PACKET_FANOUT_LB 1 +--- a/net/packet/af_packet.c ++++ b/net/packet/af_packet.c +@@ -1527,6 +1527,7 @@ static int packet_rcv_spkt(struct sk_buf + { + struct sock *sk; + struct sockaddr_pkt *spkt; ++ struct packet_sock *po; + + /* + * When we registered the protocol we saved the socket in the data +@@ -1534,6 +1535,7 @@ static int packet_rcv_spkt(struct sk_buf + */ + + sk = pt->af_packet_priv; ++ po = pkt_sk(sk); + + /* + * Yank back the headers [hope the device set this +@@ -1546,7 +1548,7 @@ static int packet_rcv_spkt(struct sk_buf + * so that this procedure is noop. + */ + +- if (skb->pkt_type == PACKET_LOOPBACK) ++ if (!(po->pkt_type & (1 << skb->pkt_type))) + goto out; + + if (!net_eq(dev_net(dev), sock_net(sk))) +@@ -1753,12 +1755,12 @@ static int packet_rcv(struct sk_buff *sk + int skb_len = skb->len; + unsigned int snaplen, res; + +- if (skb->pkt_type == PACKET_LOOPBACK) +- goto drop; +- + sk = pt->af_packet_priv; + po = pkt_sk(sk); + ++ if (!(po->pkt_type & (1 << skb->pkt_type))) ++ goto drop; ++ + if (!net_eq(dev_net(dev), sock_net(sk))) + goto drop; + +@@ -1878,12 +1880,12 @@ static int tpacket_rcv(struct sk_buff *s + BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32); + BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48); + +- if (skb->pkt_type == PACKET_LOOPBACK) +- goto drop; +- + sk = pt->af_packet_priv; + po = pkt_sk(sk); + ++ if (!(po->pkt_type & (1 << skb->pkt_type))) ++ goto drop; ++ + if (!net_eq(dev_net(dev), sock_net(sk))) + goto drop; + +@@ -2839,6 +2841,7 @@ static int packet_create(struct net *net + spin_lock_init(&po->bind_lock); + mutex_init(&po->pg_vec_lock); + po->prot_hook.func = packet_rcv; ++ po->pkt_type = PACKET_MASK_ANY & ~(1 << PACKET_LOOPBACK); + + if (sock->type == SOCK_PACKET) + po->prot_hook.func = packet_rcv_spkt; +@@ -3428,6 +3431,16 @@ packet_setsockopt(struct socket *sock, i + po->xmit = val ? packet_direct_xmit : dev_queue_xmit; + return 0; + } ++ case PACKET_RECV_TYPE: ++ { ++ unsigned int val; ++ if (optlen != sizeof(val)) ++ return -EINVAL; ++ if (copy_from_user(&val, optval, sizeof(val))) ++ return -EFAULT; ++ po->pkt_type = val & ~BIT(PACKET_LOOPBACK); ++ return 0; ++ } + default: + return -ENOPROTOOPT; + } +@@ -3479,6 +3492,13 @@ static int packet_getsockopt(struct sock + case PACKET_VNET_HDR: + val = po->has_vnet_hdr; + break; ++ case PACKET_RECV_TYPE: ++ if (len > sizeof(unsigned int)) ++ len = sizeof(unsigned int); ++ val = po->pkt_type; ++ ++ data = &val; ++ break; + case PACKET_VERSION: + val = po->tp_version; + break; +--- a/net/packet/internal.h ++++ b/net/packet/internal.h +@@ -117,6 +117,7 @@ struct packet_sock { + struct net_device __rcu *cached_dev; + int (*xmit)(struct sk_buff *skb); + struct packet_type prot_hook ____cacheline_aligned_in_smp; ++ unsigned int pkt_type; + }; + + static struct packet_sock *pkt_sk(struct sock *sk) diff --git a/target/linux/generic/patches-4.0/640-bridge_no_eap_forward.patch b/target/linux/generic/patches-4.0/640-bridge_no_eap_forward.patch new file mode 100644 index 0000000..fadb645 --- /dev/null +++ b/target/linux/generic/patches-4.0/640-bridge_no_eap_forward.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: no EAP forward + +When bridging, do not forward EAP frames to other ports, only deliver +them locally. +Fixes WPA authentication issues with multiples APs that are connected to +each other via bridges. +--- +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -153,7 +153,11 @@ int br_handle_frame_finish(struct sk_buf + + dst = NULL; + +- if (is_broadcast_ether_addr(dest)) { ++ if (skb->protocol == htons(ETH_P_PAE)) { ++ skb2 = skb; ++ /* Do not forward 802.1x/EAP frames */ ++ skb = NULL; ++ } else if (is_broadcast_ether_addr(dest)) { + if (IS_ENABLED(CONFIG_INET) && + p->flags & BR_PROXYARP && + skb->protocol == htons(ETH_P_ARP)) diff --git a/target/linux/generic/patches-4.0/641-bridge_always_accept_eap.patch b/target/linux/generic/patches-4.0/641-bridge_always_accept_eap.patch new file mode 100644 index 0000000..16deda4 --- /dev/null +++ b/target/linux/generic/patches-4.0/641-bridge_always_accept_eap.patch @@ -0,0 +1,17 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: always accept EAP + +Allow EAP frames to pass through bridges even in learning state. Fixes +issues with WDS. +--- +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -140,7 +140,7 @@ int br_handle_frame_finish(struct sk_buf + br_multicast_rcv(br, p, skb, vid)) + goto drop; + +- if (p->state == BR_STATE_LEARNING) ++ if ((p->state == BR_STATE_LEARNING) && skb->protocol != htons(ETH_P_PAE)) + goto drop; + + BR_INPUT_SKB_CB(skb)->brdev = br->dev; diff --git a/target/linux/generic/patches-4.0/642-bridge_port_isolate.patch b/target/linux/generic/patches-4.0/642-bridge_port_isolate.patch new file mode 100644 index 0000000..aacce56 --- /dev/null +++ b/target/linux/generic/patches-4.0/642-bridge_port_isolate.patch @@ -0,0 +1,107 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: port isolate + +Isolating individual bridge ports +--- +--- a/include/linux/if_bridge.h ++++ b/include/linux/if_bridge.h +@@ -44,6 +44,7 @@ struct br_ip_list { + #define BR_PROMISC BIT(7) + #define BR_PROXYARP BIT(8) + #define BR_LEARNING_SYNC BIT(9) ++#define BR_ISOLATE_MODE BIT(10) + + extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *)); + +--- a/net/bridge/br_sysfs_if.c ++++ b/net/bridge/br_sysfs_if.c +@@ -172,6 +172,22 @@ BRPORT_ATTR_FLAG(learning, BR_LEARNING); + BRPORT_ATTR_FLAG(unicast_flood, BR_FLOOD); + BRPORT_ATTR_FLAG(proxyarp, BR_PROXYARP); + ++static ssize_t show_isolate_mode(struct net_bridge_port *p, char *buf) ++{ ++ int isolate_mode = (p->flags & BR_ISOLATE_MODE) ? 1 : 0; ++ return sprintf(buf, "%d\n", isolate_mode); ++} ++static ssize_t store_isolate_mode(struct net_bridge_port *p, unsigned long v) ++{ ++ if (v) ++ p->flags |= BR_ISOLATE_MODE; ++ else ++ p->flags &= ~BR_ISOLATE_MODE; ++ return 0; ++} ++static BRPORT_ATTR(isolate_mode, S_IRUGO | S_IWUSR, ++ show_isolate_mode, store_isolate_mode); ++ + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf) + { +@@ -215,6 +231,7 @@ static const struct brport_attribute *br + &brport_attr_multicast_fast_leave, + #endif + &brport_attr_proxyarp, ++ &brport_attr_isolate_mode, + NULL + }; + +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -181,8 +181,8 @@ int br_handle_frame_finish(struct sk_buf + + unicast = false; + br->dev->stats.multicast++; +- } else if ((dst = __br_fdb_get(br, dest, vid)) && +- dst->is_local) { ++ } else if ((p->flags & BR_ISOLATE_MODE) || ++ ((dst = __br_fdb_get(br, dest, vid)) && dst->is_local)) { + skb2 = skb; + /* Do not forward the packet since it's local. */ + skb = NULL; +--- a/net/bridge/br_forward.c ++++ b/net/bridge/br_forward.c +@@ -117,7 +117,7 @@ EXPORT_SYMBOL_GPL(br_deliver); + /* called with rcu_read_lock */ + void br_forward(const struct net_bridge_port *to, struct sk_buff *skb, struct sk_buff *skb0) + { +- if (should_deliver(to, skb)) { ++ if (should_deliver(to, skb) && !(to->flags & BR_ISOLATE_MODE)) { + if (skb0) + deliver_clone(to, skb, __br_forward); + else +@@ -173,7 +173,7 @@ static void br_flood(struct net_bridge * + struct sk_buff *skb0, + void (*__packet_hook)(const struct net_bridge_port *p, + struct sk_buff *skb), +- bool unicast) ++ bool unicast, bool forward) + { + struct net_bridge_port *p; + struct net_bridge_port *prev; +@@ -181,6 +181,8 @@ static void br_flood(struct net_bridge * + prev = NULL; + + list_for_each_entry_rcu(p, &br->port_list, list) { ++ if (forward && (p->flags & BR_ISOLATE_MODE)) ++ continue; + /* Do not flood unicast traffic to ports that turn it off */ + if (unicast && !(p->flags & BR_FLOOD)) + continue; +@@ -212,14 +214,14 @@ out: + /* called with rcu_read_lock */ + void br_flood_deliver(struct net_bridge *br, struct sk_buff *skb, bool unicast) + { +- br_flood(br, skb, NULL, __br_deliver, unicast); ++ br_flood(br, skb, NULL, __br_deliver, unicast, false); + } + + /* called under bridge lock */ + void br_flood_forward(struct net_bridge *br, struct sk_buff *skb, + struct sk_buff *skb2, bool unicast) + { +- br_flood(br, skb, skb2, __br_forward, unicast); ++ br_flood(br, skb, skb2, __br_forward, unicast, true); + } + + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING diff --git a/target/linux/generic/patches-4.0/643-bridge_remove_ipv6_dependency.patch b/target/linux/generic/patches-4.0/643-bridge_remove_ipv6_dependency.patch new file mode 100644 index 0000000..6842d97 --- /dev/null +++ b/target/linux/generic/patches-4.0/643-bridge_remove_ipv6_dependency.patch @@ -0,0 +1,123 @@ +From: Jonas Gorski +Subject: [PATCH] bridge: remove IPv6 depependency of bridge in 2.6.38+ + +Since 2.6.38 the bridge module has a dependency to IPv6 if IPv6 is +enabled. Since the IPv6 module isn't exactly lightweight and bridge also +only needs a single function from IPv6, it's rather easy to create a +common "lib" module with a RCU pointer to the actual implementation, if +the IPv6 module is loaded (although slightly hackish). + +The codepath seems to be only taken when using IPv6, so there should be +no negative side effects when IPv6 isn't loaded. I did not measure how +big the performance impact is. +--- +--- a/include/net/addrconf.h ++++ b/include/net/addrconf.h +@@ -91,6 +91,12 @@ int ipv6_rcv_saddr_equal(const struct so + void addrconf_join_solict(struct net_device *dev, const struct in6_addr *addr); + void addrconf_leave_solict(struct inet6_dev *idev, const struct in6_addr *addr); + ++extern int (*ipv6_dev_get_saddr_hook)(struct net *net, ++ const struct net_device *dev, ++ const struct in6_addr *daddr, ++ unsigned int prefs, ++ struct in6_addr *saddr); ++ + static inline unsigned long addrconf_timeout_fixup(u32 timeout, + unsigned int unit) + { +--- a/net/bridge/Kconfig ++++ b/net/bridge/Kconfig +@@ -6,7 +6,6 @@ config BRIDGE + tristate "802.1d Ethernet Bridging" + select LLC + select STP +- depends on IPV6 || IPV6=n + ---help--- + If you say Y here, then your Linux box will be able to act as an + Ethernet bridge, which means that the different Ethernet segments it +--- a/net/ipv6/Makefile ++++ b/net/ipv6/Makefile +@@ -45,6 +45,7 @@ obj-y += addrconf_core.o exthdrs_core.o + obj-$(CONFIG_INET) += output_core.o protocol.o $(ipv6-offload) + + obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_hashtables.o ++obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_stubs.o + + ifneq ($(CONFIG_IPV6),) + obj-$(CONFIG_NET_UDP_TUNNEL) += ip6_udp_tunnel.o +--- a/net/ipv6/addrconf.c ++++ b/net/ipv6/addrconf.c +@@ -1346,7 +1346,7 @@ out: + return ret; + } + +-int ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, ++static int __ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, + const struct in6_addr *daddr, unsigned int prefs, + struct in6_addr *saddr) + { +@@ -1469,7 +1469,6 @@ try_nextdev: + in6_ifa_put(hiscore->ifa); + return 0; + } +-EXPORT_SYMBOL(ipv6_dev_get_saddr); + + int __ipv6_get_lladdr(struct inet6_dev *idev, struct in6_addr *addr, + u32 banned_flags) +@@ -5539,6 +5538,9 @@ int __init addrconf_init(void) + + ipv6_addr_label_rtnl_register(); + ++ BUG_ON(ipv6_dev_get_saddr_hook != NULL); ++ rcu_assign_pointer(ipv6_dev_get_saddr_hook, __ipv6_dev_get_saddr); ++ + return 0; + errout: + rtnl_af_unregister(&inet6_ops); +@@ -5558,6 +5560,9 @@ void addrconf_cleanup(void) + struct net_device *dev; + int i; + ++ rcu_assign_pointer(ipv6_dev_get_saddr_hook, NULL); ++ synchronize_rcu(); ++ + unregister_netdevice_notifier(&ipv6_dev_notf); + unregister_pernet_subsys(&addrconf_ops); + ipv6_addr_label_cleanup(); +--- /dev/null ++++ b/net/ipv6/inet6_stubs.c +@@ -0,0 +1,33 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++ ++int (*ipv6_dev_get_saddr_hook)(struct net *net, const struct net_device *dev, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr); ++ ++EXPORT_SYMBOL(ipv6_dev_get_saddr_hook); ++ ++int ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr) ++{ ++ int ret = -EADDRNOTAVAIL; ++ typeof(ipv6_dev_get_saddr_hook) dev_get_saddr; ++ ++ rcu_read_lock(); ++ dev_get_saddr = rcu_dereference(ipv6_dev_get_saddr_hook); ++ ++ if (dev_get_saddr) ++ ret = dev_get_saddr(net, dst_dev, daddr, prefs, saddr); ++ ++ rcu_read_unlock(); ++ return ret; ++} ++EXPORT_SYMBOL(ipv6_dev_get_saddr); ++ diff --git a/target/linux/generic/patches-4.0/645-bridge_multicast_to_unicast.patch b/target/linux/generic/patches-4.0/645-bridge_multicast_to_unicast.patch new file mode 100644 index 0000000..a8e22c4 --- /dev/null +++ b/target/linux/generic/patches-4.0/645-bridge_multicast_to_unicast.patch @@ -0,0 +1,383 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: multicast to unicast + +Implement optinal multicast->unicast conversion for igmp snooping +--- +--- a/include/linux/if_bridge.h ++++ b/include/linux/if_bridge.h +@@ -45,6 +45,7 @@ struct br_ip_list { + #define BR_PROXYARP BIT(8) + #define BR_LEARNING_SYNC BIT(9) + #define BR_ISOLATE_MODE BIT(10) ++#define BR_MULTICAST_TO_UCAST BIT(11) + + extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *)); + +--- a/net/bridge/br_multicast.c ++++ b/net/bridge/br_multicast.c +@@ -635,7 +635,8 @@ struct net_bridge_port_group *br_multica + struct net_bridge_port *port, + struct br_ip *group, + struct net_bridge_port_group __rcu *next, +- unsigned char state) ++ unsigned char state, ++ const unsigned char *src) + { + struct net_bridge_port_group *p; + +@@ -650,12 +651,33 @@ struct net_bridge_port_group *br_multica + hlist_add_head(&p->mglist, &port->mglist); + setup_timer(&p->timer, br_multicast_port_group_expired, + (unsigned long)p); ++ if ((port->flags & BR_MULTICAST_TO_UCAST) && src) { ++ memcpy(p->eth_addr, src, ETH_ALEN); ++ p->unicast = true; ++ } + return p; + } + ++static bool br_port_group_equal(struct net_bridge_port_group *p, ++ struct net_bridge_port *port, ++ const unsigned char *src) ++{ ++ if (p->port != port) ++ return false; ++ ++ if (!p->unicast) ++ return true; ++ ++ if (!src) ++ return false; ++ ++ return ether_addr_equal(src, p->eth_addr); ++} ++ + static int br_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, +- struct br_ip *group) ++ struct br_ip *group, ++ const unsigned char *src) + { + struct net_bridge_mdb_entry *mp; + struct net_bridge_port_group *p; +@@ -682,13 +704,13 @@ static int br_multicast_add_group(struct + for (pp = &mp->ports; + (p = mlock_dereference(*pp, br)) != NULL; + pp = &p->next) { +- if (p->port == port) ++ if (br_port_group_equal(p, port, src)) + goto found; + if ((unsigned long)p->port < (unsigned long)port) + break; + } + +- p = br_multicast_new_port_group(port, group, *pp, MDB_TEMPORARY); ++ p = br_multicast_new_port_group(port, group, *pp, MDB_TEMPORARY, src); + if (unlikely(!p)) + goto err; + rcu_assign_pointer(*pp, p); +@@ -707,7 +729,7 @@ err: + static int br_ip4_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, + __be32 group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + +@@ -718,14 +740,14 @@ static int br_ip4_multicast_add_group(st + br_group.proto = htons(ETH_P_IP); + br_group.vid = vid; + +- return br_multicast_add_group(br, port, &br_group); ++ return br_multicast_add_group(br, port, &br_group, src); + } + + #if IS_ENABLED(CONFIG_IPV6) + static int br_ip6_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + +@@ -736,7 +758,10 @@ static int br_ip6_multicast_add_group(st + br_group.proto = htons(ETH_P_IPV6); + br_group.vid = vid; + +- return br_multicast_add_group(br, port, &br_group); ++ if (ipv6_addr_is_solict_mult(group)) ++ src = NULL; ++ ++ return br_multicast_add_group(br, port, &br_group, src); + } + #endif + +@@ -965,6 +990,7 @@ static int br_ip4_multicast_igmp3_report + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src = eth_hdr(skb)->h_source; + struct igmpv3_report *ih; + struct igmpv3_grec *grec; + int i; +@@ -1008,7 +1034,7 @@ static int br_ip4_multicast_igmp3_report + continue; + } + +- err = br_ip4_multicast_add_group(br, port, group, vid); ++ err = br_ip4_multicast_add_group(br, port, group, vid, src); + if (err) + break; + } +@@ -1022,6 +1048,7 @@ static int br_ip6_multicast_mld2_report( + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src = eth_hdr(skb)->h_source; + struct icmp6hdr *icmp6h; + struct mld2_grec *grec; + int i; +@@ -1070,7 +1097,7 @@ static int br_ip6_multicast_mld2_report( + } + + err = br_ip6_multicast_add_group(br, port, &grec->grec_mca, +- vid); ++ vid, src); + if (err) + break; + } +@@ -1406,7 +1433,8 @@ br_multicast_leave_group(struct net_brid + struct net_bridge_port *port, + struct br_ip *group, + struct bridge_mcast_other_query *other_query, +- struct bridge_mcast_own_query *own_query) ++ struct bridge_mcast_own_query *own_query, ++ const unsigned char *src) + { + struct net_bridge_mdb_htable *mdb; + struct net_bridge_mdb_entry *mp; +@@ -1456,7 +1484,7 @@ br_multicast_leave_group(struct net_brid + for (pp = &mp->ports; + (p = mlock_dereference(*pp, br)) != NULL; + pp = &p->next) { +- if (p->port != port) ++ if (!br_port_group_equal(p, port, src)) + continue; + + rcu_assign_pointer(*pp, p->next); +@@ -1490,7 +1518,7 @@ br_multicast_leave_group(struct net_brid + for (p = mlock_dereference(mp->ports, br); + p != NULL; + p = mlock_dereference(p->next, br)) { +- if (p->port != port) ++ if (!br_port_group_equal(p, port, src)) + continue; + + if (!hlist_unhashed(&p->mglist) && +@@ -1508,8 +1536,8 @@ out: + + static void br_ip4_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, +- __be32 group, +- __u16 vid) ++ __be32 group, __u16 vid, ++ const unsigned char *src) + { + struct br_ip br_group; + struct bridge_mcast_own_query *own_query; +@@ -1524,14 +1552,14 @@ static void br_ip4_multicast_leave_group + br_group.vid = vid; + + br_multicast_leave_group(br, port, &br_group, &br->ip4_other_query, +- own_query); ++ own_query, src); + } + + #if IS_ENABLED(CONFIG_IPV6) + static void br_ip6_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + struct bridge_mcast_own_query *own_query; +@@ -1546,7 +1574,7 @@ static void br_ip6_multicast_leave_group + br_group.vid = vid; + + br_multicast_leave_group(br, port, &br_group, &br->ip6_other_query, +- own_query); ++ own_query, src); + } + #endif + +@@ -1555,6 +1583,7 @@ static int br_multicast_ipv4_rcv(struct + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src = eth_hdr(skb)->h_source; + struct sk_buff *skb2 = skb; + const struct iphdr *iph; + struct igmphdr *ih; +@@ -1628,7 +1657,7 @@ static int br_multicast_ipv4_rcv(struct + case IGMP_HOST_MEMBERSHIP_REPORT: + case IGMPV2_HOST_MEMBERSHIP_REPORT: + BR_INPUT_SKB_CB(skb)->mrouters_only = 1; +- err = br_ip4_multicast_add_group(br, port, ih->group, vid); ++ err = br_ip4_multicast_add_group(br, port, ih->group, vid, src); + break; + case IGMPV3_HOST_MEMBERSHIP_REPORT: + err = br_ip4_multicast_igmp3_report(br, port, skb2, vid); +@@ -1637,7 +1666,7 @@ static int br_multicast_ipv4_rcv(struct + err = br_ip4_multicast_query(br, port, skb2, vid); + break; + case IGMP_HOST_LEAVE_MESSAGE: +- br_ip4_multicast_leave_group(br, port, ih->group, vid); ++ br_ip4_multicast_leave_group(br, port, ih->group, vid, src); + break; + } + +@@ -1655,6 +1684,7 @@ static int br_multicast_ipv6_rcv(struct + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src = eth_hdr(skb)->h_source; + struct sk_buff *skb2; + const struct ipv6hdr *ip6h; + u8 icmp6_type; +@@ -1764,7 +1794,8 @@ static int br_multicast_ipv6_rcv(struct + } + mld = (struct mld_msg *)skb_transport_header(skb2); + BR_INPUT_SKB_CB(skb)->mrouters_only = 1; +- err = br_ip6_multicast_add_group(br, port, &mld->mld_mca, vid); ++ err = br_ip6_multicast_add_group(br, port, &mld->mld_mca, vid, ++ src); + break; + } + case ICMPV6_MLD2_REPORT: +@@ -1781,7 +1812,7 @@ static int br_multicast_ipv6_rcv(struct + goto out; + } + mld = (struct mld_msg *)skb_transport_header(skb2); +- br_ip6_multicast_leave_group(br, port, &mld->mld_mca, vid); ++ br_ip6_multicast_leave_group(br, port, &mld->mld_mca, vid, src); + } + } + +--- a/net/bridge/br_private.h ++++ b/net/bridge/br_private.h +@@ -113,6 +113,9 @@ struct net_bridge_port_group { + struct timer_list timer; + struct br_ip addr; + unsigned char state; ++ ++ unsigned char eth_addr[ETH_ALEN]; ++ bool unicast; + }; + + struct net_bridge_mdb_entry +@@ -480,7 +483,8 @@ void br_multicast_free_pg(struct rcu_hea + struct net_bridge_port_group * + br_multicast_new_port_group(struct net_bridge_port *port, struct br_ip *group, + struct net_bridge_port_group __rcu *next, +- unsigned char state); ++ unsigned char state, ++ const unsigned char *src); + void br_mdb_init(void); + void br_mdb_uninit(void); + void br_mdb_notify(struct net_device *dev, struct net_bridge_port *port, +--- a/net/bridge/br_mdb.c ++++ b/net/bridge/br_mdb.c +@@ -343,7 +343,7 @@ static int br_mdb_add_group(struct net_b + break; + } + +- p = br_multicast_new_port_group(port, group, *pp, state); ++ p = br_multicast_new_port_group(port, group, *pp, state, NULL); + if (unlikely(!p)) + return -ENOMEM; + rcu_assign_pointer(*pp, p); +--- a/net/bridge/br_forward.c ++++ b/net/bridge/br_forward.c +@@ -168,6 +168,29 @@ out: + return p; + } + ++static struct net_bridge_port *maybe_deliver_addr( ++ struct net_bridge_port *prev, struct net_bridge_port *p, ++ struct sk_buff *skb, const unsigned char *addr, ++ void (*__packet_hook)(const struct net_bridge_port *p, ++ struct sk_buff *skb)) ++{ ++ struct net_device *dev = BR_INPUT_SKB_CB(skb)->brdev; ++ ++ if (!should_deliver(p, skb)) ++ return prev; ++ ++ skb = skb_copy(skb, GFP_ATOMIC); ++ if (!skb) { ++ dev->stats.tx_dropped++; ++ return prev; ++ } ++ ++ memcpy(eth_hdr(skb)->h_dest, addr, ETH_ALEN); ++ __packet_hook(p, skb); ++ ++ return prev; ++} ++ + /* called under bridge lock */ + static void br_flood(struct net_bridge *br, struct sk_buff *skb, + struct sk_buff *skb0, +@@ -237,6 +260,7 @@ static void br_multicast_flood(struct ne + struct net_bridge_port *prev = NULL; + struct net_bridge_port_group *p; + struct hlist_node *rp; ++ const unsigned char *addr; + + rp = rcu_dereference(hlist_first_rcu(&br->router_list)); + p = mdst ? rcu_dereference(mdst->ports) : NULL; +@@ -247,10 +271,19 @@ static void br_multicast_flood(struct ne + rport = rp ? hlist_entry(rp, struct net_bridge_port, rlist) : + NULL; + +- port = (unsigned long)lport > (unsigned long)rport ? +- lport : rport; +- +- prev = maybe_deliver(prev, port, skb, __packet_hook); ++ if ((unsigned long)lport > (unsigned long)rport) { ++ port = lport; ++ addr = p->unicast ? p->eth_addr : NULL; ++ } else { ++ port = rport; ++ addr = NULL; ++ } ++ ++ if (addr) ++ prev = maybe_deliver_addr(prev, port, skb, addr, ++ __packet_hook); ++ else ++ prev = maybe_deliver(prev, port, skb, __packet_hook); + if (IS_ERR(prev)) + goto out; + +--- a/net/bridge/br_sysfs_if.c ++++ b/net/bridge/br_sysfs_if.c +@@ -203,6 +203,7 @@ static BRPORT_ATTR(multicast_router, S_I + store_multicast_router); + + BRPORT_ATTR_FLAG(multicast_fast_leave, BR_MULTICAST_FAST_LEAVE); ++BRPORT_ATTR_FLAG(multicast_to_unicast, BR_MULTICAST_TO_UCAST); + #endif + + static const struct brport_attribute *brport_attrs[] = { +@@ -229,6 +230,7 @@ static const struct brport_attribute *br + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + &brport_attr_multicast_router, + &brport_attr_multicast_fast_leave, ++ &brport_attr_multicast_to_unicast, + #endif + &brport_attr_proxyarp, + &brport_attr_isolate_mode, diff --git a/target/linux/generic/patches-4.0/650-pppoe_header_pad.patch b/target/linux/generic/patches-4.0/650-pppoe_header_pad.patch new file mode 100644 index 0000000..3b4978b --- /dev/null +++ b/target/linux/generic/patches-4.0/650-pppoe_header_pad.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -869,7 +869,7 @@ static int pppoe_sendmsg(struct kiocb *i + goto end; + + +- skb = sock_wmalloc(sk, total_len + dev->hard_header_len + 32, ++ skb = sock_wmalloc(sk, total_len + dev->hard_header_len + 32 + NET_SKB_PAD, + 0, GFP_KERNEL); + if (!skb) { + error = -ENOMEM; +@@ -877,7 +877,7 @@ static int pppoe_sendmsg(struct kiocb *i + } + + /* Reserve space for headers. */ +- skb_reserve(skb, dev->hard_header_len); ++ skb_reserve(skb, dev->hard_header_len + NET_SKB_PAD); + skb_reset_network_header(skb); + + skb->dev = dev; diff --git a/target/linux/generic/patches-4.0/651-wireless_mesh_header.patch b/target/linux/generic/patches-4.0/651-wireless_mesh_header.patch new file mode 100644 index 0000000..17bcb6d --- /dev/null +++ b/target/linux/generic/patches-4.0/651-wireless_mesh_header.patch @@ -0,0 +1,11 @@ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -133,7 +133,7 @@ static inline bool dev_xmit_complete(int + */ + + #if defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) +-# if defined(CONFIG_MAC80211_MESH) ++# if 1 || defined(CONFIG_MAC80211_MESH) + # define LL_MAX_HEADER 128 + # else + # define LL_MAX_HEADER 96 diff --git a/target/linux/generic/patches-4.0/653-disable_netlink_trim.patch b/target/linux/generic/patches-4.0/653-disable_netlink_trim.patch new file mode 100644 index 0000000..02ab826 --- /dev/null +++ b/target/linux/generic/patches-4.0/653-disable_netlink_trim.patch @@ -0,0 +1,30 @@ +--- a/net/netlink/af_netlink.c ++++ b/net/netlink/af_netlink.c +@@ -1713,27 +1713,7 @@ void netlink_detachskb(struct sock *sk, + + static struct sk_buff *netlink_trim(struct sk_buff *skb, gfp_t allocation) + { +- int delta; +- + WARN_ON(skb->sk != NULL); +- if (netlink_skb_is_mmaped(skb)) +- return skb; +- +- delta = skb->end - skb->tail; +- if (is_vmalloc_addr(skb->head) || delta * 2 < skb->truesize) +- return skb; +- +- if (skb_shared(skb)) { +- struct sk_buff *nskb = skb_clone(skb, allocation); +- if (!nskb) +- return skb; +- consume_skb(skb); +- skb = nskb; +- } +- +- if (!pskb_expand_head(skb, 0, -delta, allocation)) +- skb->truesize -= delta; +- + return skb; + } + diff --git a/target/linux/generic/patches-4.0/655-increase_skb_pad.patch b/target/linux/generic/patches-4.0/655-increase_skb_pad.patch new file mode 100644 index 0000000..c4aee07 --- /dev/null +++ b/target/linux/generic/patches-4.0/655-increase_skb_pad.patch @@ -0,0 +1,11 @@ +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2027,7 +2027,7 @@ static inline int pskb_network_may_pull( + * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8) + */ + #ifndef NET_SKB_PAD +-#define NET_SKB_PAD max(32, L1_CACHE_BYTES) ++#define NET_SKB_PAD max(64, L1_CACHE_BYTES) + #endif + + int ___pskb_trim(struct sk_buff *skb, unsigned int len); diff --git a/target/linux/generic/patches-4.0/656-skb_reduce_truesize-helper.patch b/target/linux/generic/patches-4.0/656-skb_reduce_truesize-helper.patch new file mode 100644 index 0000000..72e5c26 --- /dev/null +++ b/target/linux/generic/patches-4.0/656-skb_reduce_truesize-helper.patch @@ -0,0 +1,41 @@ +From 4593a806e31119c5bd3faa00c7210ad862d515af Mon Sep 17 00:00:00 2001 +From: Dave Taht +Date: Mon, 31 Dec 2012 10:02:21 -0800 +Subject: [PATCH 3/7] skb_reduce_truesize: helper function for shrinking skbs + whenever needed + +On embedded devices in particular, large queues of small packets from the rx +path with a large truesize can exist. Reducing their size can reduce +memory pressure. skb_reduce_truesize is a helper function for doing this, +when needed. +--- + include/linux/skbuff.h | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2072,6 +2072,24 @@ static inline void pskb_trim_unique(stru + BUG_ON(err); + } + ++/* ++ * Caller wants to reduce memory needs before queueing skb ++ * The (expensive) copy should not be be done in fast path. ++ */ ++static inline struct sk_buff *skb_reduce_truesize(struct sk_buff *skb) ++{ ++ if (skb->truesize > 2 * SKB_TRUESIZE(skb->len)) { ++ struct sk_buff *nskb; ++ nskb = skb_copy_expand(skb, skb_headroom(skb), 0, ++ GFP_ATOMIC | __GFP_NOWARN); ++ if (nskb) { ++ __kfree_skb(skb); ++ skb = nskb; ++ } ++ } ++ return skb; ++} ++ + /** + * skb_orphan - orphan a buffer + * @skb: buffer to orphan diff --git a/target/linux/generic/patches-4.0/657-qdisc_reduce_truesize.patch b/target/linux/generic/patches-4.0/657-qdisc_reduce_truesize.patch new file mode 100644 index 0000000..6777eec --- /dev/null +++ b/target/linux/generic/patches-4.0/657-qdisc_reduce_truesize.patch @@ -0,0 +1,63 @@ +From bc9fec2f87d57bdbff30d296605e24504513f65c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Dave=20T=C3=A4ht?= +Date: Mon, 17 Sep 2012 19:20:22 -0700 +Subject: [PATCH 4/7] net: add skb_reduce_truesize support to common qdiscs + +Reduce skb size under load when queues begin to fill on the +commont qdiscs. +--- + net/sched/sch_codel.c | 2 ++ + net/sched/sch_fifo.c | 12 ++++++++---- + net/sched/sch_fq_codel.c | 2 ++ + 3 files changed, 12 insertions(+), 4 deletions(-) + +--- a/net/sched/sch_codel.c ++++ b/net/sched/sch_codel.c +@@ -96,6 +96,8 @@ static int codel_qdisc_enqueue(struct sk + struct codel_sched_data *q; + + if (likely(qdisc_qlen(sch) < sch->limit)) { ++ if(qdisc_qlen(sch) > 128) ++ skb = skb_reduce_truesize(skb); + codel_set_enqueue_time(skb); + return qdisc_enqueue_tail(skb, sch); + } +--- a/net/sched/sch_fifo.c ++++ b/net/sched/sch_fifo.c +@@ -29,17 +29,21 @@ static int bfifo_enqueue(struct sk_buff + + static int pfifo_enqueue(struct sk_buff *skb, struct Qdisc *sch) + { +- if (likely(skb_queue_len(&sch->q) < sch->limit)) ++ if (likely(skb_queue_len(&sch->q) < sch->limit)) { ++ if (skb_queue_len(&sch->q) > 128) ++ skb = skb_reduce_truesize(skb); + return qdisc_enqueue_tail(skb, sch); +- ++ } + return qdisc_reshape_fail(skb, sch); + } + + static int pfifo_tail_enqueue(struct sk_buff *skb, struct Qdisc *sch) + { +- if (likely(skb_queue_len(&sch->q) < sch->limit)) ++ if (likely(skb_queue_len(&sch->q) < sch->limit)) { ++ if (skb_queue_len(&sch->q) > 128) ++ skb = skb_reduce_truesize(skb); + return qdisc_enqueue_tail(skb, sch); +- ++ } + /* queue full, remove one skb to fulfill the limit */ + __qdisc_queue_drop_head(sch, &sch->q); + qdisc_qstats_drop(sch); +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -185,6 +185,8 @@ static int fq_codel_enqueue(struct sk_bu + return ret; + } + idx--; ++ if (sch->q.qlen > 128) ++ skb = skb_reduce_truesize(skb); + + codel_set_enqueue_time(skb); + flow = &q->flows[idx]; diff --git a/target/linux/generic/patches-4.0/660-fq_codel_defaults.patch b/target/linux/generic/patches-4.0/660-fq_codel_defaults.patch new file mode 100644 index 0000000..f7f4659 --- /dev/null +++ b/target/linux/generic/patches-4.0/660-fq_codel_defaults.patch @@ -0,0 +1,14 @@ +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -387,9 +387,9 @@ static int fq_codel_init(struct Qdisc *s + struct fq_codel_sched_data *q = qdisc_priv(sch); + int i; + +- sch->limit = 10*1024; ++ sch->limit = 1024; + q->flows_cnt = 1024; +- q->quantum = psched_mtu(qdisc_dev(sch)); ++ q->quantum = 300; + q->perturbation = prandom_u32(); + INIT_LIST_HEAD(&q->new_flows); + INIT_LIST_HEAD(&q->old_flows); diff --git a/target/linux/generic/patches-4.0/661-fq_codel_keep_dropped_stats.patch b/target/linux/generic/patches-4.0/661-fq_codel_keep_dropped_stats.patch new file mode 100644 index 0000000..45a8d68 --- /dev/null +++ b/target/linux/generic/patches-4.0/661-fq_codel_keep_dropped_stats.patch @@ -0,0 +1,10 @@ +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -198,7 +198,6 @@ static int fq_codel_enqueue(struct sk_bu + list_add_tail(&flow->flowchain, &q->new_flows); + q->new_flow_count++; + flow->deficit = q->quantum; +- flow->dropped = 0; + } + if (++sch->q.qlen <= sch->limit) + return NET_XMIT_SUCCESS; diff --git a/target/linux/generic/patches-4.0/662-use_fq_codel_by_default.patch b/target/linux/generic/patches-4.0/662-use_fq_codel_by_default.patch new file mode 100644 index 0000000..e7b781b --- /dev/null +++ b/target/linux/generic/patches-4.0/662-use_fq_codel_by_default.patch @@ -0,0 +1,75 @@ +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -3,8 +3,9 @@ + # + + menuconfig NET_SCHED +- bool "QoS and/or fair queueing" ++ def_bool y + select NET_SCH_FIFO ++ select NET_SCH_FQ_CODEL + ---help--- + When the kernel has several packets to send out over a network + device, it has to decide which ones to send first, which ones to +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -592,7 +592,7 @@ static const struct Qdisc_class_ops fq_c + .walk = fq_codel_walk, + }; + +-static struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = { ++struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = { + .cl_ops = &fq_codel_class_ops, + .id = "fq_codel", + .priv_size = sizeof(struct fq_codel_sched_data), +@@ -608,6 +608,7 @@ static struct Qdisc_ops fq_codel_qdisc_o + .dump_stats = fq_codel_dump_stats, + .owner = THIS_MODULE, + }; ++EXPORT_SYMBOL(fq_codel_qdisc_ops); + + static int __init fq_codel_module_init(void) + { +--- a/include/net/sch_generic.h ++++ b/include/net/sch_generic.h +@@ -340,6 +340,7 @@ extern struct Qdisc noop_qdisc; + extern struct Qdisc_ops noop_qdisc_ops; + extern struct Qdisc_ops pfifo_fast_ops; + extern struct Qdisc_ops mq_qdisc_ops; ++extern struct Qdisc_ops fq_codel_qdisc_ops; + extern const struct Qdisc_ops *default_qdisc_ops; + + struct Qdisc_class_common { +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -737,7 +737,7 @@ static void attach_one_default_qdisc(str + + if (dev->tx_queue_len) { + qdisc = qdisc_create_dflt(dev_queue, +- default_qdisc_ops, TC_H_ROOT); ++ &fq_codel_qdisc_ops, TC_H_ROOT); + if (!qdisc) { + netdev_info(dev, "activation failed\n"); + return; +--- a/net/sched/sch_mq.c ++++ b/net/sched/sch_mq.c +@@ -57,7 +57,7 @@ static int mq_init(struct Qdisc *sch, st + + for (ntx = 0; ntx < dev->num_tx_queues; ntx++) { + dev_queue = netdev_get_tx_queue(dev, ntx); +- qdisc = qdisc_create_dflt(dev_queue, default_qdisc_ops, ++ qdisc = qdisc_create_dflt(dev_queue, &fq_codel_qdisc_ops, + TC_H_MAKE(TC_H_MAJ(sch->handle), + TC_H_MIN(ntx + 1))); + if (qdisc == NULL) +--- a/net/sched/sch_mqprio.c ++++ b/net/sched/sch_mqprio.c +@@ -124,7 +124,7 @@ static int mqprio_init(struct Qdisc *sch + + for (i = 0; i < dev->num_tx_queues; i++) { + dev_queue = netdev_get_tx_queue(dev, i); +- qdisc = qdisc_create_dflt(dev_queue, default_qdisc_ops, ++ qdisc = qdisc_create_dflt(dev_queue, &fq_codel_qdisc_ops, + TC_H_MAKE(TC_H_MAJ(sch->handle), + TC_H_MIN(i + 1))); + if (qdisc == NULL) { diff --git a/target/linux/generic/patches-4.0/663-remove_pfifo_fast.patch b/target/linux/generic/patches-4.0/663-remove_pfifo_fast.patch new file mode 100644 index 0000000..5b26ca3 --- /dev/null +++ b/target/linux/generic/patches-4.0/663-remove_pfifo_fast.patch @@ -0,0 +1,143 @@ +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -442,140 +442,6 @@ static struct Qdisc noqueue_qdisc = { + .busylock = __SPIN_LOCK_UNLOCKED(noqueue_qdisc.busylock), + }; + +- +-static const u8 prio2band[TC_PRIO_MAX + 1] = { +- 1, 2, 2, 2, 1, 2, 0, 0 , 1, 1, 1, 1, 1, 1, 1, 1 +-}; +- +-/* 3-band FIFO queue: old style, but should be a bit faster than +- generic prio+fifo combination. +- */ +- +-#define PFIFO_FAST_BANDS 3 +- +-/* +- * Private data for a pfifo_fast scheduler containing: +- * - queues for the three band +- * - bitmap indicating which of the bands contain skbs +- */ +-struct pfifo_fast_priv { +- u32 bitmap; +- struct sk_buff_head q[PFIFO_FAST_BANDS]; +-}; +- +-/* +- * Convert a bitmap to the first band number where an skb is queued, where: +- * bitmap=0 means there are no skbs on any band. +- * bitmap=1 means there is an skb on band 0. +- * bitmap=7 means there are skbs on all 3 bands, etc. +- */ +-static const int bitmap2band[] = {-1, 0, 1, 0, 2, 0, 1, 0}; +- +-static inline struct sk_buff_head *band2list(struct pfifo_fast_priv *priv, +- int band) +-{ +- return priv->q + band; +-} +- +-static int pfifo_fast_enqueue(struct sk_buff *skb, struct Qdisc *qdisc) +-{ +- if (skb_queue_len(&qdisc->q) < qdisc_dev(qdisc)->tx_queue_len) { +- int band = prio2band[skb->priority & TC_PRIO_MAX]; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- struct sk_buff_head *list = band2list(priv, band); +- +- priv->bitmap |= (1 << band); +- qdisc->q.qlen++; +- return __qdisc_enqueue_tail(skb, qdisc, list); +- } +- +- return qdisc_drop(skb, qdisc); +-} +- +-static struct sk_buff *pfifo_fast_dequeue(struct Qdisc *qdisc) +-{ +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- int band = bitmap2band[priv->bitmap]; +- +- if (likely(band >= 0)) { +- struct sk_buff_head *list = band2list(priv, band); +- struct sk_buff *skb = __qdisc_dequeue_head(qdisc, list); +- +- qdisc->q.qlen--; +- if (skb_queue_empty(list)) +- priv->bitmap &= ~(1 << band); +- +- return skb; +- } +- +- return NULL; +-} +- +-static struct sk_buff *pfifo_fast_peek(struct Qdisc *qdisc) +-{ +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- int band = bitmap2band[priv->bitmap]; +- +- if (band >= 0) { +- struct sk_buff_head *list = band2list(priv, band); +- +- return skb_peek(list); +- } +- +- return NULL; +-} +- +-static void pfifo_fast_reset(struct Qdisc *qdisc) +-{ +- int prio; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- +- for (prio = 0; prio < PFIFO_FAST_BANDS; prio++) +- __qdisc_reset_queue(qdisc, band2list(priv, prio)); +- +- priv->bitmap = 0; +- qdisc->qstats.backlog = 0; +- qdisc->q.qlen = 0; +-} +- +-static int pfifo_fast_dump(struct Qdisc *qdisc, struct sk_buff *skb) +-{ +- struct tc_prio_qopt opt = { .bands = PFIFO_FAST_BANDS }; +- +- memcpy(&opt.priomap, prio2band, TC_PRIO_MAX + 1); +- if (nla_put(skb, TCA_OPTIONS, sizeof(opt), &opt)) +- goto nla_put_failure; +- return skb->len; +- +-nla_put_failure: +- return -1; +-} +- +-static int pfifo_fast_init(struct Qdisc *qdisc, struct nlattr *opt) +-{ +- int prio; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- +- for (prio = 0; prio < PFIFO_FAST_BANDS; prio++) +- __skb_queue_head_init(band2list(priv, prio)); +- +- /* Can by-pass the queue discipline */ +- qdisc->flags |= TCQ_F_CAN_BYPASS; +- return 0; +-} +- +-struct Qdisc_ops pfifo_fast_ops __read_mostly = { +- .id = "pfifo_fast", +- .priv_size = sizeof(struct pfifo_fast_priv), +- .enqueue = pfifo_fast_enqueue, +- .dequeue = pfifo_fast_dequeue, +- .peek = pfifo_fast_peek, +- .init = pfifo_fast_init, +- .reset = pfifo_fast_reset, +- .dump = pfifo_fast_dump, +- .owner = THIS_MODULE, +-}; +- + static struct lock_class_key qdisc_tx_busylock; + + struct Qdisc *qdisc_alloc(struct netdev_queue *dev_queue, diff --git a/target/linux/generic/patches-4.0/664-codel_fix_3_12.patch b/target/linux/generic/patches-4.0/664-codel_fix_3_12.patch new file mode 100644 index 0000000..726c428 --- /dev/null +++ b/target/linux/generic/patches-4.0/664-codel_fix_3_12.patch @@ -0,0 +1,22 @@ +--- a/net/sched/sch_api.c ++++ b/net/sched/sch_api.c +@@ -1947,7 +1947,7 @@ static int __init pktsched_init(void) + return err; + } + +- register_qdisc(&pfifo_fast_ops); ++ register_qdisc(&fq_codel_qdisc_ops); + register_qdisc(&pfifo_qdisc_ops); + register_qdisc(&bfifo_qdisc_ops); + register_qdisc(&pfifo_head_drop_qdisc_ops); +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -31,7 +31,7 @@ + #include + + /* Qdisc to use by default */ +-const struct Qdisc_ops *default_qdisc_ops = &pfifo_fast_ops; ++const struct Qdisc_ops *default_qdisc_ops = &fq_codel_qdisc_ops; + EXPORT_SYMBOL(default_qdisc_ops); + + /* Main transmission queue. */ diff --git a/target/linux/generic/patches-4.0/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/patches-4.0/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch new file mode 100644 index 0000000..41454c9 --- /dev/null +++ b/target/linux/generic/patches-4.0/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch @@ -0,0 +1,495 @@ +From 775d6fe74d1eaec2ba387535b068dde2dc89de9e Mon Sep 17 00:00:00 2001 +From: Steven Barth +Date: Thu, 22 May 2014 09:49:05 +0200 +Subject: [PATCH] Add support for MAP-E FMRs (mesh mode) + +MAP-E FMRs (draft-ietf-softwire-map-10) are rules for IPv4-communication +between MAP CEs (mesh mode) without the need to forward such data to a +border relay. This is similar to how 6rd works but for IPv4 over IPv6. + +Signed-off-by: Steven Barth +--- + include/net/ip6_tunnel.h | 13 ++ + include/uapi/linux/if_tunnel.h | 13 ++ + net/ipv6/ip6_tunnel.c | 276 +++++++++++++++++++++++++++++++++++++++-- + 3 files changed, 291 insertions(+), 11 deletions(-) + +--- a/include/net/ip6_tunnel.h ++++ b/include/net/ip6_tunnel.h +@@ -15,6 +15,18 @@ + /* determine capability on a per-packet basis */ + #define IP6_TNL_F_CAP_PER_PACKET 0x40000 + ++/* IPv6 tunnel FMR */ ++struct __ip6_tnl_fmr { ++ struct __ip6_tnl_fmr *next; /* next fmr in list */ ++ struct in6_addr ip6_prefix; ++ struct in_addr ip4_prefix; ++ ++ __u8 ip6_prefix_len; ++ __u8 ip4_prefix_len; ++ __u8 ea_len; ++ __u8 offset; ++}; ++ + struct __ip6_tnl_parm { + char name[IFNAMSIZ]; /* name of tunnel device */ + int link; /* ifindex of underlying L2 interface */ +@@ -25,6 +37,7 @@ struct __ip6_tnl_parm { + __u32 flags; /* tunnel flags */ + struct in6_addr laddr; /* local tunnel end-point address */ + struct in6_addr raddr; /* remote tunnel end-point address */ ++ struct __ip6_tnl_fmr *fmrs; /* FMRs */ + + __be16 i_flags; + __be16 o_flags; +--- a/include/uapi/linux/if_tunnel.h ++++ b/include/uapi/linux/if_tunnel.h +@@ -57,10 +57,23 @@ enum { + IFLA_IPTUN_ENCAP_FLAGS, + IFLA_IPTUN_ENCAP_SPORT, + IFLA_IPTUN_ENCAP_DPORT, ++ IFLA_IPTUN_FMRS, + __IFLA_IPTUN_MAX, + }; + #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) + ++enum { ++ IFLA_IPTUN_FMR_UNSPEC, ++ IFLA_IPTUN_FMR_IP6_PREFIX, ++ IFLA_IPTUN_FMR_IP4_PREFIX, ++ IFLA_IPTUN_FMR_IP6_PREFIX_LEN, ++ IFLA_IPTUN_FMR_IP4_PREFIX_LEN, ++ IFLA_IPTUN_FMR_EA_LEN, ++ IFLA_IPTUN_FMR_OFFSET, ++ __IFLA_IPTUN_FMR_MAX, ++}; ++#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1) ++ + enum tunnel_encap_types { + TUNNEL_ENCAP_NONE, + TUNNEL_ENCAP_FOU, +--- a/net/ipv6/ip6_tunnel.c ++++ b/net/ipv6/ip6_tunnel.c +@@ -16,6 +16,8 @@ + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * ++ * Changes: ++ * Steven Barth : MAP-E FMR support + */ + + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +@@ -77,11 +79,9 @@ static bool log_ecn_error = true; + module_param(log_ecn_error, bool, 0644); + MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN"); + +-static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2) ++static u32 HASH(const struct in6_addr *addr) + { +- u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2); +- +- return hash_32(hash, HASH_SIZE_SHIFT); ++ return hash_32(ipv6_addr_hash(addr), HASH_SIZE_SHIFT); + } + + static int ip6_tnl_dev_init(struct net_device *dev); +@@ -180,27 +180,36 @@ EXPORT_SYMBOL_GPL(ip6_tnl_dst_store); + static struct ip6_tnl * + ip6_tnl_lookup(struct net *net, const struct in6_addr *remote, const struct in6_addr *local) + { +- unsigned int hash = HASH(remote, local); ++ unsigned int hash = HASH(local); + struct ip6_tnl *t; + struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + struct in6_addr any; ++ struct __ip6_tnl_fmr *fmr; + + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { +- if (ipv6_addr_equal(local, &t->parms.laddr) && +- ipv6_addr_equal(remote, &t->parms.raddr) && +- (t->dev->flags & IFF_UP)) ++ if (!ipv6_addr_equal(local, &t->parms.laddr) || ++ !(t->dev->flags & IFF_UP)) ++ continue; ++ ++ if (ipv6_addr_equal(remote, &t->parms.raddr)) + return t; ++ ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { ++ if (ipv6_prefix_equal(remote, &fmr->ip6_prefix, ++ fmr->ip6_prefix_len)) ++ return t; ++ } + } + + memset(&any, 0, sizeof(any)); +- hash = HASH(&any, local); ++ hash = HASH(local); + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { + if (ipv6_addr_equal(local, &t->parms.laddr) && + (t->dev->flags & IFF_UP)) + return t; + } + +- hash = HASH(remote, &any); ++ hash = HASH(&any); + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { + if (ipv6_addr_equal(remote, &t->parms.raddr) && + (t->dev->flags & IFF_UP)) +@@ -235,7 +244,7 @@ ip6_tnl_bucket(struct ip6_tnl_net *ip6n, + + if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) { + prio = 1; +- h = HASH(remote, local); ++ h = HASH(local); + } + return &ip6n->tnls[prio][h]; + } +@@ -405,6 +414,12 @@ ip6_tnl_dev_uninit(struct net_device *de + struct net *net = t->net; + struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + ++ while (t->parms.fmrs) { ++ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; ++ kfree(t->parms.fmrs); ++ t->parms.fmrs = next; ++ } ++ + if (dev == ip6n->fb_tnl_dev) + RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL); + else +@@ -791,6 +806,108 @@ int ip6_tnl_rcv_ctl(struct ip6_tnl *t, + } + EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl); + ++ ++/** ++ * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR ++ * @dest: destination IPv6 address buffer ++ * @skb: received socket buffer ++ * @fmr: MAP FMR ++ * @xmit: Calculate for xmit or rcv ++ **/ ++static void ip4ip6_fmr_calc(struct in6_addr *dest, ++ const struct iphdr *iph, const uint8_t *end, ++ const struct __ip6_tnl_fmr *fmr, bool xmit) ++{ ++ int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len); ++ u8 *portp = NULL; ++ bool use_dest_addr; ++ const struct iphdr *dsth = iph; ++ ++ if ((u8*)dsth >= end) ++ return; ++ ++ /* find significant IP header */ ++ if (iph->protocol == IPPROTO_ICMP) { ++ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); ++ if (ih && ((u8*)&ih[1]) <= end && ( ++ ih->type == ICMP_DEST_UNREACH || ++ ih->type == ICMP_SOURCE_QUENCH || ++ ih->type == ICMP_TIME_EXCEEDED || ++ ih->type == ICMP_PARAMETERPROB || ++ ih->type == ICMP_REDIRECT)) ++ dsth = (const struct iphdr*)&ih[1]; ++ } ++ ++ /* in xmit-path use dest port by default and source port only if ++ this is an ICMP reply to something else; vice versa in rcv-path */ ++ use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph); ++ ++ /* get dst port */ ++ if (((u8*)&dsth[1]) <= end && ( ++ dsth->protocol == IPPROTO_UDP || ++ dsth->protocol == IPPROTO_TCP || ++ dsth->protocol == IPPROTO_SCTP || ++ dsth->protocol == IPPROTO_DCCP)) { ++ /* for UDP, TCP, SCTP and DCCP source and dest port ++ follow IPv4 header directly */ ++ portp = ((u8*)dsth) + dsth->ihl * 4; ++ ++ if (use_dest_addr) ++ portp += sizeof(u16); ++ } else if (iph->protocol == IPPROTO_ICMP) { ++ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); ++ ++ /* use icmp identifier as port */ ++ if (((u8*)&ih) <= end && ( ++ (use_dest_addr && ( ++ ih->type == ICMP_ECHOREPLY || ++ ih->type == ICMP_TIMESTAMPREPLY || ++ ih->type == ICMP_INFO_REPLY || ++ ih->type == ICMP_ADDRESSREPLY)) || ++ (!use_dest_addr && ( ++ ih->type == ICMP_ECHO || ++ ih->type == ICMP_TIMESTAMP || ++ ih->type == ICMP_INFO_REQUEST || ++ ih->type == ICMP_ADDRESS) ++ ))) ++ portp = (u8*)&ih->un.echo.id; ++ } ++ ++ if ((portp && &portp[2] <= end) || psidlen == 0) { ++ int frombyte = fmr->ip6_prefix_len / 8; ++ int fromrem = fmr->ip6_prefix_len % 8; ++ int bytes = sizeof(struct in6_addr) - frombyte; ++ const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr; ++ u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len); ++ u64 t = 0; ++ ++ /* extract PSID from port and add it to eabits */ ++ u16 psidbits = 0; ++ if (psidlen > 0) { ++ psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]); ++ psidbits >>= 16 - psidlen - fmr->offset; ++ psidbits = (u16)(psidbits << (16 - psidlen)); ++ eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen)); ++ } ++ ++ /* rewrite destination address */ ++ *dest = fmr->ip6_prefix; ++ memcpy(&dest->s6_addr[10], addr, sizeof(*addr)); ++ dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen)); ++ ++ if (bytes > sizeof(u64)) ++ bytes = sizeof(u64); ++ ++ /* insert eabits */ ++ memcpy(&t, &dest->s6_addr[frombyte], bytes); ++ t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1) ++ << (64 - fmr->ea_len - fromrem)); ++ t = cpu_to_be64(t | (eabits >> fromrem)); ++ memcpy(&dest->s6_addr[frombyte], &t, bytes); ++ } ++} ++ ++ + /** + * ip6_tnl_rcv - decapsulate IPv6 packet and retransmit it locally + * @skb: received socket buffer +@@ -836,6 +953,26 @@ static int ip6_tnl_rcv(struct sk_buff *s + skb_reset_network_header(skb); + skb->protocol = htons(protocol); + memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); ++ if (protocol == ETH_P_IP && ++ !ipv6_addr_equal(&ipv6h->saddr, &t->parms.raddr)) { ++ /* Packet didn't come from BR, so lookup FMR */ ++ struct __ip6_tnl_fmr *fmr; ++ struct in6_addr expected = t->parms.raddr; ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) ++ if (ipv6_prefix_equal(&ipv6h->saddr, ++ &fmr->ip6_prefix, fmr->ip6_prefix_len)) ++ break; ++ ++ /* Check that IPv6 matches IPv4 source to prevent spoofing */ ++ if (fmr) ++ ip4ip6_fmr_calc(&expected, ip_hdr(skb), ++ skb_tail_pointer(skb), fmr, false); ++ ++ if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) { ++ rcu_read_unlock(); ++ goto discard; ++ } ++ } + + __skb_tunnel_rx(skb, t->dev, t->net); + +@@ -1129,6 +1266,7 @@ ip4ip6_tnl_xmit(struct sk_buff *skb, str + __u32 mtu; + u8 tproto; + int err; ++ struct __ip6_tnl_fmr *fmr; + + tproto = ACCESS_ONCE(t->parms.proto); + if (tproto != IPPROTO_IPIP && tproto != 0) +@@ -1148,6 +1286,18 @@ ip4ip6_tnl_xmit(struct sk_buff *skb, str + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK) + fl6.flowi6_mark = skb->mark; + ++ /* try to find matching FMR */ ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { ++ unsigned mshift = 32 - fmr->ip4_prefix_len; ++ if (ntohl(fmr->ip4_prefix.s_addr) >> mshift == ++ ntohl(iph->daddr) >> mshift) ++ break; ++ } ++ ++ /* change dstaddr according to FMR */ ++ if (fmr) ++ ip4ip6_fmr_calc(&fl6.daddr, iph, skb_tail_pointer(skb), fmr, true); ++ + err = ip6_tnl_xmit2(skb, dev, dsfield, &fl6, encap_limit, &mtu); + if (err != 0) { + /* XXX: send ICMP error even if DF is not set. */ +@@ -1318,6 +1468,14 @@ ip6_tnl_change(struct ip6_tnl *t, const + t->parms.flowinfo = p->flowinfo; + t->parms.link = p->link; + t->parms.proto = p->proto; ++ ++ while (t->parms.fmrs) { ++ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; ++ kfree(t->parms.fmrs); ++ t->parms.fmrs = next; ++ } ++ t->parms.fmrs = p->fmrs; ++ + ip6_tnl_dst_reset(t); + ip6_tnl_link_config(t); + return 0; +@@ -1356,6 +1514,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_ + p->flowinfo = u->flowinfo; + p->link = u->link; + p->proto = u->proto; ++ p->fmrs = NULL; + memcpy(p->name, u->name, sizeof(u->name)); + } + +@@ -1634,6 +1793,15 @@ static int ip6_tnl_validate(struct nlatt + return 0; + } + ++static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = { ++ [IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) }, ++ [IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) }, ++ [IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 } ++}; ++ + static void ip6_tnl_netlink_parms(struct nlattr *data[], + struct __ip6_tnl_parm *parms) + { +@@ -1667,6 +1835,46 @@ static void ip6_tnl_netlink_parms(struct + + if (data[IFLA_IPTUN_PROTO]) + parms->proto = nla_get_u8(data[IFLA_IPTUN_PROTO]); ++ ++ if (data[IFLA_IPTUN_FMRS]) { ++ unsigned rem; ++ struct nlattr *fmr; ++ nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) { ++ struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c; ++ struct __ip6_tnl_fmr *nfmr; ++ ++ nla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX, ++ fmr, ip6_tnl_fmr_policy); ++ ++ if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL))) ++ continue; ++ ++ nfmr->offset = 6; ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX])) ++ nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX], ++ sizeof(nfmr->ip6_prefix)); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX])) ++ nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX], ++ sizeof(nfmr->ip4_prefix)); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN])) ++ nfmr->ip6_prefix_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN])) ++ nfmr->ip4_prefix_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN])) ++ nfmr->ea_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET])) ++ nfmr->offset = nla_get_u8(c); ++ ++ nfmr->next = parms->fmrs; ++ parms->fmrs = nfmr; ++ } ++ } + } + + static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev, +@@ -1719,6 +1927,12 @@ static void ip6_tnl_dellink(struct net_d + + static size_t ip6_tnl_get_size(const struct net_device *dev) + { ++ const struct ip6_tnl *t = netdev_priv(dev); ++ struct __ip6_tnl_fmr *c; ++ int fmrs = 0; ++ for (c = t->parms.fmrs; c; c = c->next) ++ ++fmrs; ++ + return + /* IFLA_IPTUN_LINK */ + nla_total_size(4) + +@@ -1736,6 +1950,24 @@ static size_t ip6_tnl_get_size(const str + nla_total_size(4) + + /* IFLA_IPTUN_PROTO */ + nla_total_size(1) + ++ /* IFLA_IPTUN_FMRS */ ++ nla_total_size(0) + ++ ( ++ /* nest */ ++ nla_total_size(0) + ++ /* IFLA_IPTUN_FMR_IP6_PREFIX */ ++ nla_total_size(sizeof(struct in6_addr)) + ++ /* IFLA_IPTUN_FMR_IP4_PREFIX */ ++ nla_total_size(sizeof(struct in_addr)) + ++ /* IFLA_IPTUN_FMR_EA_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_OFFSET */ ++ nla_total_size(1) ++ ) * fmrs + + 0; + } + +@@ -1743,6 +1975,9 @@ static int ip6_tnl_fill_info(struct sk_b + { + struct ip6_tnl *tunnel = netdev_priv(dev); + struct __ip6_tnl_parm *parm = &tunnel->parms; ++ struct __ip6_tnl_fmr *c; ++ int fmrcnt = 0; ++ struct nlattr *fmrs; + + if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || + nla_put(skb, IFLA_IPTUN_LOCAL, sizeof(struct in6_addr), +@@ -1753,8 +1988,27 @@ static int ip6_tnl_fill_info(struct sk_b + nla_put_u8(skb, IFLA_IPTUN_ENCAP_LIMIT, parm->encap_limit) || + nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || + nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || +- nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto)) ++ nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || ++ !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS))) + goto nla_put_failure; ++ ++ for (c = parm->fmrs; c; c = c->next) { ++ struct nlattr *fmr = nla_nest_start(skb, ++fmrcnt); ++ if (!fmr || ++ nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX, ++ sizeof(c->ip6_prefix), &c->ip6_prefix) || ++ nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX, ++ sizeof(c->ip4_prefix), &c->ip4_prefix) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset)) ++ goto nla_put_failure; ++ ++ nla_nest_end(skb, fmr); ++ } ++ nla_nest_end(skb, fmrs); ++ + return 0; + + nla_put_failure: +@@ -1778,6 +2032,7 @@ static const struct nla_policy ip6_tnl_p + [IFLA_IPTUN_FLOWINFO] = { .type = NLA_U32 }, + [IFLA_IPTUN_FLAGS] = { .type = NLA_U32 }, + [IFLA_IPTUN_PROTO] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMRS] = { .type = NLA_NESTED }, + }; + + static struct rtnl_link_ops ip6_link_ops __read_mostly = { diff --git a/target/linux/generic/patches-4.0/667-ipv6-Fixed-source-specific-default-route-handling.patch b/target/linux/generic/patches-4.0/667-ipv6-Fixed-source-specific-default-route-handling.patch new file mode 100644 index 0000000..50ac1db --- /dev/null +++ b/target/linux/generic/patches-4.0/667-ipv6-Fixed-source-specific-default-route-handling.patch @@ -0,0 +1,97 @@ +From e16e888b525503be05b3aea64190e8b3bdef44d0 Mon Sep 17 00:00:00 2001 +From: Markus Stenberg +Date: Tue, 5 May 2015 13:36:59 +0300 +Subject: [PATCH] ipv6: Fixed source specific default route handling. + +If there are only IPv6 source specific default routes present, the +host gets -ENETUNREACH on e.g. connect() because ip6_dst_lookup_tail +calls ip6_route_output first, and given source address any, it fails, +and ip6_route_get_saddr is never called. + +The change is to use the ip6_route_get_saddr, even if the initial +ip6_route_output fails, and then doing ip6_route_output _again_ after +we have appropriate source address available. + +Note that this is '99% fix' to the problem; a correct fix would be to +do route lookups only within addrconf.c when picking a source address, +and never call ip6_route_output before source address has been +populated. + +Signed-off-by: Markus Stenberg +Signed-off-by: David S. Miller +--- + net/ipv6/ip6_output.c | 39 +++++++++++++++++++++++++++++++-------- + net/ipv6/route.c | 5 +++-- + 2 files changed, 34 insertions(+), 10 deletions(-) + +--- a/net/ipv6/ip6_output.c ++++ b/net/ipv6/ip6_output.c +@@ -883,22 +883,45 @@ static int ip6_dst_lookup_tail(struct so + #endif + int err; + +- if (*dst == NULL) +- *dst = ip6_route_output(net, sk, fl6); +- +- err = (*dst)->error; +- if (err) +- goto out_err_release; ++ /* The correct way to handle this would be to do ++ * ip6_route_get_saddr, and then ip6_route_output; however, ++ * the route-specific preferred source forces the ++ * ip6_route_output call _before_ ip6_route_get_saddr. ++ * ++ * In source specific routing (no src=any default route), ++ * ip6_route_output will fail given src=any saddr, though, so ++ * that's why we try it again later. ++ */ ++ if (ipv6_addr_any(&fl6->saddr) && (!*dst || !(*dst)->error)) { ++ struct rt6_info *rt; ++ bool had_dst = *dst != NULL; + +- if (ipv6_addr_any(&fl6->saddr)) { +- struct rt6_info *rt = (struct rt6_info *) *dst; ++ if (!had_dst) ++ *dst = ip6_route_output(net, sk, fl6); ++ rt = (*dst)->error ? NULL : (struct rt6_info *)*dst; + err = ip6_route_get_saddr(net, rt, &fl6->daddr, + sk ? inet6_sk(sk)->srcprefs : 0, + &fl6->saddr); + if (err) + goto out_err_release; ++ ++ /* If we had an erroneous initial result, pretend it ++ * never existed and let the SA-enabled version take ++ * over. ++ */ ++ if (!had_dst && (*dst)->error) { ++ dst_release(*dst); ++ *dst = NULL; ++ } + } + ++ if (!*dst) ++ *dst = ip6_route_output(net, sk, fl6); ++ ++ err = (*dst)->error; ++ if (err) ++ goto out_err_release; ++ + #ifdef CONFIG_IPV6_OPTIMISTIC_DAD + /* + * Here if the dst entry we've looked up +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -2247,9 +2247,10 @@ int ip6_route_get_saddr(struct net *net, + unsigned int prefs, + struct in6_addr *saddr) + { +- struct inet6_dev *idev = ip6_dst_idev((struct dst_entry *)rt); ++ struct inet6_dev *idev = ++ rt ? ip6_dst_idev((struct dst_entry *)rt) : NULL; + int err = 0; +- if (rt->rt6i_prefsrc.plen) ++ if (rt && rt->rt6i_prefsrc.plen) + *saddr = rt->rt6i_prefsrc.addr; + else + err = ipv6_dev_get_saddr(net, idev ? idev->dev : NULL, diff --git a/target/linux/generic/patches-4.0/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/patches-4.0/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch new file mode 100644 index 0000000..7447760 --- /dev/null +++ b/target/linux/generic/patches-4.0/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -0,0 +1,249 @@ +From 1b5aaa4b16f6e6471ab1c07b38068197a1b4c395 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 24 May 2013 14:40:54 +0200 +Subject: [PATCH 1/2] ipv6: allow rejecting with "source address failed policy" + +RFC6204 L-14 requires rejecting traffic from invalid addresses with +ICMPv6 Destination Unreachable, Code 5 (Source address failed ingress/ +egress policy) on the LAN side, so add an appropriate rule for that. + +Signed-off-by: Jonas Gorski +--- + include/net/netns/ipv6.h | 1 + + include/uapi/linux/fib_rules.h | 4 +++ + include/uapi/linux/rtnetlink.h | 1 + + net/ipv4/fib_semantics.c | 4 +++ + net/ipv4/fib_trie.c | 1 + + net/ipv4/ipmr.c | 1 + + net/ipv6/fib6_rules.c | 4 +++ + net/ipv6/ip6mr.c | 2 ++ + net/ipv6/route.c | 58 +++++++++++++++++++++++++++++++++++++++++- + 9 files changed, 75 insertions(+), 1 deletion(-) + +--- a/include/net/netns/ipv6.h ++++ b/include/net/netns/ipv6.h +@@ -59,6 +59,7 @@ struct netns_ipv6 { + unsigned long ip6_rt_last_gc; + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + struct rt6_info *ip6_prohibit_entry; ++ struct rt6_info *ip6_policy_failed_entry; + struct rt6_info *ip6_blk_hole_entry; + struct fib6_table *fib6_local_tbl; + struct fib_rules_ops *fib6_rules_ops; +--- a/include/uapi/linux/fib_rules.h ++++ b/include/uapi/linux/fib_rules.h +@@ -64,6 +64,10 @@ enum { + FR_ACT_BLACKHOLE, /* Drop without notification */ + FR_ACT_UNREACHABLE, /* Drop with ENETUNREACH */ + FR_ACT_PROHIBIT, /* Drop with EACCES */ ++ FR_ACT_RES9, ++ FR_ACT_RES10, ++ FR_ACT_RES11, ++ FR_ACT_POLICY_FAILED, /* Drop with EACCES */ + __FR_ACT_MAX, + }; + +--- a/include/uapi/linux/rtnetlink.h ++++ b/include/uapi/linux/rtnetlink.h +@@ -208,6 +208,7 @@ enum { + RTN_THROW, /* Not in this table */ + RTN_NAT, /* Translate this address */ + RTN_XRESOLVE, /* Use external resolver */ ++ RTN_POLICY_FAILED, /* Failed ingress/egress policy */ + __RTN_MAX + }; + +--- a/net/ipv4/fib_semantics.c ++++ b/net/ipv4/fib_semantics.c +@@ -138,6 +138,10 @@ const struct fib_prop fib_props[RTN_MAX + .error = -EINVAL, + .scope = RT_SCOPE_NOWHERE, + }, ++ [RTN_POLICY_FAILED] = { ++ .error = -EACCES, ++ .scope = RT_SCOPE_UNIVERSE, ++ }, + }; + + static void rt_fibinfo_free(struct rtable __rcu **rtp) +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -2236,6 +2236,7 @@ static const char *const rtn_type_names[ + [RTN_THROW] = "THROW", + [RTN_NAT] = "NAT", + [RTN_XRESOLVE] = "XRESOLVE", ++ [RTN_POLICY_FAILED] = "POLICY_FAILED", + }; + + static inline const char *rtn_type(char *buf, size_t len, unsigned int t) +--- a/net/ipv4/ipmr.c ++++ b/net/ipv4/ipmr.c +@@ -184,6 +184,7 @@ static int ipmr_rule_action(struct fib_r + case FR_ACT_UNREACHABLE: + return -ENETUNREACH; + case FR_ACT_PROHIBIT: ++ case FR_ACT_POLICY_FAILED: + return -EACCES; + case FR_ACT_BLACKHOLE: + default: +--- a/net/ipv6/fib6_rules.c ++++ b/net/ipv6/fib6_rules.c +@@ -73,6 +73,10 @@ static int fib6_rule_action(struct fib_r + err = -EACCES; + rt = net->ipv6.ip6_prohibit_entry; + goto discard_pkt; ++ case FR_ACT_POLICY_FAILED: ++ err = -EACCES; ++ rt = net->ipv6.ip6_policy_failed_entry; ++ goto discard_pkt; + } + + table = fib6_get_table(net, rule->table); +--- a/net/ipv6/ip6mr.c ++++ b/net/ipv6/ip6mr.c +@@ -169,6 +169,8 @@ static int ip6mr_rule_action(struct fib_ + return -ENETUNREACH; + case FR_ACT_PROHIBIT: + return -EACCES; ++ case FR_ACT_POLICY_FAILED: ++ return -EACCES; + case FR_ACT_BLACKHOLE: + default: + return -EINVAL; +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -87,6 +87,8 @@ static int ip6_pkt_discard(struct sk_bu + static int ip6_pkt_discard_out(struct sock *sk, struct sk_buff *skb); + static int ip6_pkt_prohibit(struct sk_buff *skb); + static int ip6_pkt_prohibit_out(struct sock *sk, struct sk_buff *skb); ++static int ip6_pkt_policy_failed(struct sk_buff *skb); ++static int ip6_pkt_policy_failed_out(struct sock *sk, struct sk_buff *skb); + static void ip6_link_failure(struct sk_buff *skb); + static void ip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk, + struct sk_buff *skb, u32 mtu); +@@ -283,6 +285,21 @@ static const struct rt6_info ip6_prohibi + .rt6i_ref = ATOMIC_INIT(1), + }; + ++static const struct rt6_info ip6_policy_failed_entry_template = { ++ .dst = { ++ .__refcnt = ATOMIC_INIT(1), ++ .__use = 1, ++ .obsolete = DST_OBSOLETE_FORCE_CHK, ++ .error = -EACCES, ++ .input = ip6_pkt_policy_failed, ++ .output = ip6_pkt_policy_failed_out, ++ }, ++ .rt6i_flags = (RTF_REJECT | RTF_NONEXTHOP), ++ .rt6i_protocol = RTPROT_KERNEL, ++ .rt6i_metric = ~(u32) 0, ++ .rt6i_ref = ATOMIC_INIT(1), ++}; ++ + static const struct rt6_info ip6_blk_hole_entry_template = { + .dst = { + .__refcnt = ATOMIC_INIT(1), +@@ -1637,6 +1654,11 @@ int ip6_route_add(struct fib6_config *cf + rt->dst.output = ip6_pkt_prohibit_out; + rt->dst.input = ip6_pkt_prohibit; + break; ++ case RTN_POLICY_FAILED: ++ rt->dst.error = -EACCES; ++ rt->dst.output = ip6_pkt_policy_failed_out; ++ rt->dst.input = ip6_pkt_policy_failed; ++ break; + case RTN_THROW: + default: + rt->dst.error = (cfg->fc_type == RTN_THROW) ? -EAGAIN +@@ -2204,6 +2226,17 @@ static int ip6_pkt_prohibit_out(struct s + return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES); + } + ++static int ip6_pkt_policy_failed(struct sk_buff *skb) ++{ ++ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_INNOROUTES); ++} ++ ++static int ip6_pkt_policy_failed_out(struct sock *sk, struct sk_buff *skb) ++{ ++ skb->dev = skb_dst(skb)->dev; ++ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_OUTNOROUTES); ++} ++ + /* + * Allocate a dst for local (unicast / anycast) address. + */ +@@ -2428,7 +2461,8 @@ static int rtm_to_fib6_config(struct sk_ + if (rtm->rtm_type == RTN_UNREACHABLE || + rtm->rtm_type == RTN_BLACKHOLE || + rtm->rtm_type == RTN_PROHIBIT || +- rtm->rtm_type == RTN_THROW) ++ rtm->rtm_type == RTN_THROW || ++ rtm->rtm_type == RTN_POLICY_FAILED) + cfg->fc_flags |= RTF_REJECT; + + if (rtm->rtm_type == RTN_LOCAL) +@@ -2631,6 +2665,9 @@ static int rt6_fill_node(struct net *net + case -EACCES: + rtm->rtm_type = RTN_PROHIBIT; + break; ++ case -EPERM: ++ rtm->rtm_type = RTN_POLICY_FAILED; ++ break; + case -EAGAIN: + rtm->rtm_type = RTN_THROW; + break; +@@ -2885,6 +2922,8 @@ static int ip6_route_dev_notify(struct n + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + net->ipv6.ip6_prohibit_entry->dst.dev = dev; + net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev); ++ net->ipv6.ip6_policy_failed_entry->dst.dev = dev; ++ net->ipv6.ip6_policy_failed_entry->rt6i_idev = in6_dev_get(dev); + net->ipv6.ip6_blk_hole_entry->dst.dev = dev; + net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev); + #endif +@@ -3101,6 +3140,17 @@ static int __net_init ip6_route_net_init + net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops; + dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst, + ip6_template_metrics, true); ++ ++ net->ipv6.ip6_policy_failed_entry = ++ kmemdup(&ip6_policy_failed_entry_template, ++ sizeof(*net->ipv6.ip6_policy_failed_entry), GFP_KERNEL); ++ if (!net->ipv6.ip6_policy_failed_entry) ++ goto out_ip6_blk_hole_entry; ++ net->ipv6.ip6_policy_failed_entry->dst.path = ++ (struct dst_entry *)net->ipv6.ip6_policy_failed_entry; ++ net->ipv6.ip6_policy_failed_entry->dst.ops = &net->ipv6.ip6_dst_ops; ++ dst_init_metrics(&net->ipv6.ip6_policy_failed_entry->dst, ++ ip6_template_metrics, true); + #endif + + net->ipv6.sysctl.flush_delay = 0; +@@ -3119,6 +3169,8 @@ out: + return ret; + + #ifdef CONFIG_IPV6_MULTIPLE_TABLES ++out_ip6_blk_hole_entry: ++ kfree(net->ipv6.ip6_blk_hole_entry); + out_ip6_prohibit_entry: + kfree(net->ipv6.ip6_prohibit_entry); + out_ip6_null_entry: +@@ -3136,6 +3188,7 @@ static void __net_exit ip6_route_net_exi + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + kfree(net->ipv6.ip6_prohibit_entry); + kfree(net->ipv6.ip6_blk_hole_entry); ++ kfree(net->ipv6.ip6_policy_failed_entry); + #endif + dst_entries_destroy(&net->ipv6.ip6_dst_ops); + } +@@ -3232,6 +3285,9 @@ int __init ip6_route_init(void) + init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); + init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev; + init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); ++ init_net.ipv6.ip6_policy_failed_entry->dst.dev = init_net.loopback_dev; ++ init_net.ipv6.ip6_policy_failed_entry->rt6i_idev = ++ in6_dev_get(init_net.loopback_dev); + #endif + ret = fib6_init(); + if (ret) diff --git a/target/linux/generic/patches-4.0/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch b/target/linux/generic/patches-4.0/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch new file mode 100644 index 0000000..6866f78 --- /dev/null +++ b/target/linux/generic/patches-4.0/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch @@ -0,0 +1,53 @@ +From 7749b481ce5d7e232b1f7da5e6b2c44816f51681 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 19 Jan 2014 20:45:51 +0100 +Subject: [PATCH 2/2] net: provide defines for _POLICY_FAILED until all code is + updated + +Upstream introduced ICMPV6_POLICY_FAIL for code 5 of destination +unreachable, conflicting with our name. + +Add appropriate defines to allow our code to build with the new +name until we have updated our local patches for older kernels +and userspace packages. + +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/fib_rules.h | 2 ++ + include/uapi/linux/icmpv6.h | 2 ++ + include/uapi/linux/rtnetlink.h | 2 ++ + 3 files changed, 6 insertions(+) + +--- a/include/uapi/linux/fib_rules.h ++++ b/include/uapi/linux/fib_rules.h +@@ -71,6 +71,8 @@ enum { + __FR_ACT_MAX, + }; + ++#define FR_ACT_FAILED_POLICY FR_ACT_POLICY_FAILED ++ + #define FR_ACT_MAX (__FR_ACT_MAX - 1) + + #endif +--- a/include/uapi/linux/icmpv6.h ++++ b/include/uapi/linux/icmpv6.h +@@ -118,6 +118,8 @@ struct icmp6hdr { + #define ICMPV6_POLICY_FAIL 5 + #define ICMPV6_REJECT_ROUTE 6 + ++#define ICMPV6_FAILED_POLICY ICMPV6_POLICY_FAIL ++ + /* + * Codes for Time Exceeded + */ +--- a/include/uapi/linux/rtnetlink.h ++++ b/include/uapi/linux/rtnetlink.h +@@ -212,6 +212,8 @@ enum { + __RTN_MAX + }; + ++#define RTN_FAILED_POLICY RTN_POLICY_FAILED ++ + #define RTN_MAX (__RTN_MAX - 1) + + diff --git a/target/linux/generic/patches-4.0/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/patches-4.0/680-NET-skip-GRO-for-foreign-MAC-addresses.patch new file mode 100644 index 0000000..f0d5b47 --- /dev/null +++ b/target/linux/generic/patches-4.0/680-NET-skip-GRO-for-foreign-MAC-addresses.patch @@ -0,0 +1,160 @@ +Subject: NET: skip GRO for foreign MAC addresses + +For network drivers using napi_gro_receive, packets are run through GRO, +even when the destination MAC address does not match, and they're supposed +to be delivered to another host behind a different bridge port. + +This can be very expensive, because for drivers without TSO or scatter- +gather, this can only be undone by copying the skb and checksumming it +again. + +To be able to track foreign MAC addresses in an inexpensive way, create +a mask of changed bits in MAC addresses of upper devices. This allows +handling VLANs and bridge devices with different addresses (as long as +they are not too different). + +Signed-off-by: Felix Fietkau + +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -4007,6 +4007,9 @@ static enum gro_result dev_gro_receive(s + enum gro_result ret; + int grow; + ++ if (skb->gro_skip) ++ goto normal; ++ + if (!(skb->dev->features & NETIF_F_GRO)) + goto normal; + +@@ -5154,6 +5157,48 @@ static void __netdev_adjacent_dev_unlink + &upper_dev->adj_list.lower); + } + ++static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr, ++ struct net_device *dev) ++{ ++ int i; ++ ++ for (i = 0; i < dev->addr_len; i++) ++ mask[i] |= addr[i] ^ dev->dev_addr[i]; ++} ++ ++static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev, ++ struct net_device *lower) ++{ ++ struct net_device *cur; ++ struct list_head *iter; ++ ++ netdev_for_each_upper_dev_rcu(dev, cur, iter) { ++ __netdev_addr_mask(mask, cur->dev_addr, lower); ++ __netdev_upper_mask(mask, cur, lower); ++ } ++} ++ ++static void __netdev_update_addr_mask(struct net_device *dev) ++{ ++ unsigned char mask[MAX_ADDR_LEN]; ++ struct net_device *cur; ++ struct list_head *iter; ++ ++ memset(mask, 0, sizeof(mask)); ++ __netdev_upper_mask(mask, dev, dev); ++ memcpy(dev->local_addr_mask, mask, dev->addr_len); ++ ++ netdev_for_each_lower_dev(dev, cur, iter) ++ __netdev_update_addr_mask(cur); ++} ++ ++static void netdev_update_addr_mask(struct net_device *dev) ++{ ++ rcu_read_lock(); ++ __netdev_update_addr_mask(dev); ++ rcu_read_unlock(); ++} ++ + static int __netdev_upper_dev_link(struct net_device *dev, + struct net_device *upper_dev, bool master, + void *private) +@@ -5214,6 +5259,7 @@ static int __netdev_upper_dev_link(struc + goto rollback_lower_mesh; + } + ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEUPPER, dev); + return 0; + +@@ -5331,6 +5377,7 @@ void netdev_upper_dev_unlink(struct net_ + list_for_each_entry(i, &upper_dev->all_adj_list.upper, list) + __netdev_adjacent_dev_unlink(dev, i->dev); + ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEUPPER, dev); + } + EXPORT_SYMBOL(netdev_upper_dev_unlink); +@@ -5870,6 +5917,7 @@ int dev_set_mac_address(struct net_devic + if (err) + return err; + dev->addr_assign_type = NET_ADDR_SET; ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEADDR, dev); + add_device_randomness(dev->dev_addr, dev->addr_len); + return 0; +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1592,6 +1592,8 @@ struct net_device { + struct netdev_hw_addr_list mc; + struct netdev_hw_addr_list dev_addrs; + ++ unsigned char local_addr_mask[MAX_ADDR_LEN]; ++ + #ifdef CONFIG_SYSFS + struct kset *queues_kset; + #endif +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -609,7 +609,8 @@ struct sk_buff { + __u8 ipvs_property:1; + __u8 inner_protocol_type:1; + __u8 remcsum_offload:1; +- /* 3 or 5 bit hole */ ++ __u8 gro_skip:1; ++ /* 2 or 4 bit hole */ + + #ifdef CONFIG_NET_SCHED + __u16 tc_index; /* traffic control index */ +--- a/net/ethernet/eth.c ++++ b/net/ethernet/eth.c +@@ -172,6 +172,18 @@ u32 eth_get_headlen(void *data, unsigned + } + EXPORT_SYMBOL(eth_get_headlen); + ++static inline bool ++eth_check_local_mask(const void *addr1, const void *addr2, const void *mask) ++{ ++ const u16 *a1 = addr1; ++ const u16 *a2 = addr2; ++ const u16 *m = mask; ++ ++ return (((a1[0] ^ a2[0]) & ~m[0]) | ++ ((a1[1] ^ a2[1]) & ~m[1]) | ++ ((a1[2] ^ a2[2]) & ~m[2])); ++} ++ + /** + * eth_type_trans - determine the packet's protocol ID. + * @skb: received socket data +@@ -199,8 +211,12 @@ __be16 eth_type_trans(struct sk_buff *sk + skb->pkt_type = PACKET_MULTICAST; + } + else if (unlikely(!ether_addr_equal_64bits(eth->h_dest, +- dev->dev_addr))) ++ dev->dev_addr))) { + skb->pkt_type = PACKET_OTHERHOST; ++ if (eth_check_local_mask(eth->h_dest, dev->dev_addr, ++ dev->local_addr_mask)) ++ skb->gro_skip = 1; ++ } + + /* + * Some variants of DSA tagging don't have an ethertype field diff --git a/target/linux/generic/patches-4.0/681-NET-add-of_get_mac_address_mtd.patch b/target/linux/generic/patches-4.0/681-NET-add-of_get_mac_address_mtd.patch new file mode 100644 index 0000000..a836eed --- /dev/null +++ b/target/linux/generic/patches-4.0/681-NET-add-of_get_mac_address_mtd.patch @@ -0,0 +1,88 @@ +From: John Crispin +Date: Sun, 27 Jul 2014 09:40:01 +0100 +Subject: NET: add of_get_mac_address_mtd() + +Many embedded devices have information such as mac addresses stored inside mtd +devices. This patch allows us to add a property inside a node describing a +network interface. The new property points at a mtd partition with an offset +where the mac address can be found. + +Signed-off-by: John Crispin +--- + drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++ + include/linux/of_net.h | 1 + + 2 files changed, 38 insertions(+) + +--- a/drivers/of/of_net.c ++++ b/drivers/of/of_net.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + /** + * of_get_phy_mode - Get phy mode for given device_node +@@ -75,3 +76,45 @@ const void *of_get_mac_address(struct de + return NULL; + } + EXPORT_SYMBOL(of_get_mac_address); ++ ++#ifdef CONFIG_MTD ++int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac) ++{ ++ struct device_node *mtd_np = NULL; ++ size_t retlen; ++ int size, ret; ++ struct mtd_info *mtd; ++ const char *part; ++ const __be32 *list; ++ phandle phandle; ++ u32 mac_inc = 0; ++ ++ list = of_get_property(np, "mtd-mac-address", &size); ++ if (!list || (size != (2 * sizeof(*list)))) ++ return -ENOENT; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return -ENOENT; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ mtd = get_mtd_device_nm(part); ++ if (IS_ERR(mtd)) ++ return PTR_ERR(mtd); ++ ++ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, mac); ++ put_mtd_device(mtd); ++ ++ if (!of_property_read_u32(np, "mtd-mac-address-increment", &mac_inc)) ++ mac[5] += mac_inc; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(of_get_mac_address_mtd); ++#endif +--- a/include/linux/of_net.h ++++ b/include/linux/of_net.h +@@ -11,6 +11,14 @@ + #include + extern int of_get_phy_mode(struct device_node *np); + extern const void *of_get_mac_address(struct device_node *np); ++#ifdef CONFIG_MTD ++extern int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac); ++#else ++static inline int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac) ++{ ++ return -ENOENT; ++} ++#endif + #else + static inline int of_get_phy_mode(struct device_node *np) + { diff --git a/target/linux/generic/patches-4.0/700-swconfig.patch b/target/linux/generic/patches-4.0/700-swconfig.patch new file mode 100644 index 0000000..bf62025 --- /dev/null +++ b/target/linux/generic/patches-4.0/700-swconfig.patch @@ -0,0 +1,39 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -12,6 +12,16 @@ menuconfig PHYLIB + + if PHYLIB + ++config SWCONFIG ++ tristate "Switch configuration API" ++ ---help--- ++ Switch configuration API using netlink. This allows ++ you to configure the VLAN features of certain switches. ++ ++config SWCONFIG_LEDS ++ bool "Switch LED trigger support" ++ depends on (SWCONFIG && LEDS_TRIGGERS) ++ + comment "MII PHY device drivers" + + config AT803X_PHY +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -3,6 +3,7 @@ + libphy-objs := phy.o phy_device.o mdio_bus.o + + obj-$(CONFIG_PHYLIB) += libphy.o ++obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_DAVICOM_PHY) += davicom.o + obj-$(CONFIG_CICADA_PHY) += cicada.o +--- a/include/uapi/linux/Kbuild ++++ b/include/uapi/linux/Kbuild +@@ -379,6 +379,7 @@ header-y += stddef.h + header-y += string.h + header-y += suspend_ioctls.h + header-y += swab.h ++header-y += switch.h + header-y += synclink.h + header-y += sysctl.h + header-y += sysinfo.h diff --git a/target/linux/generic/patches-4.0/701-phy_extension.patch b/target/linux/generic/patches-4.0/701-phy_extension.patch new file mode 100644 index 0000000..55b37ba --- /dev/null +++ b/target/linux/generic/patches-4.0/701-phy_extension.patch @@ -0,0 +1,63 @@ +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -357,6 +357,50 @@ int phy_ethtool_gset(struct phy_device * + } + EXPORT_SYMBOL(phy_ethtool_gset); + ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) ++{ ++ u32 cmd; ++ int tmp; ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (get_user(cmd, (u32 *) useraddr)) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case ETHTOOL_GSET: ++ phy_ethtool_gset(phydev, &ecmd); ++ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) ++ return -EFAULT; ++ return 0; ++ ++ case ETHTOOL_SSET: ++ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) ++ return -EFAULT; ++ return phy_ethtool_sset(phydev, &ecmd); ++ ++ case ETHTOOL_NWAY_RST: ++ /* if autoneg is off, it's an error */ ++ tmp = phy_read(phydev, MII_BMCR); ++ if (tmp & BMCR_ANENABLE) { ++ tmp |= (BMCR_ANRESTART); ++ phy_write(phydev, MII_BMCR, tmp); ++ return 0; ++ } ++ return -EINVAL; ++ ++ case ETHTOOL_GLINK: ++ edata.data = (phy_read(phydev, ++ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++ } ++ ++ return -EOPNOTSUPP; ++} ++EXPORT_SYMBOL(phy_ethtool_ioctl); ++ + /** + * phy_mii_ioctl - generic PHY MII ioctl interface + * @phydev: the phy_device struct +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -762,6 +762,7 @@ void phy_start_machine(struct phy_device + void phy_stop_machine(struct phy_device *phydev); + int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); + int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); + int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd); + int phy_start_interrupts(struct phy_device *phydev); + void phy_print_status(struct phy_device *phydev); diff --git a/target/linux/generic/patches-4.0/702-phy_add_aneg_done_function.patch b/target/linux/generic/patches-4.0/702-phy_add_aneg_done_function.patch new file mode 100644 index 0000000..c743cef --- /dev/null +++ b/target/linux/generic/patches-4.0/702-phy_add_aneg_done_function.patch @@ -0,0 +1,27 @@ +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -489,6 +489,12 @@ struct phy_driver { + /* Determines the negotiated speed and duplex */ + int (*read_status)(struct phy_device *phydev); + ++ /* ++ * Update the value in phydev->link to reflect the ++ * current link value ++ */ ++ int (*update_link)(struct phy_device *phydev); ++ + /* Clears any pending interrupts */ + int (*ack_interrupt)(struct phy_device *phydev); + +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -929,6 +929,9 @@ int genphy_update_link(struct phy_device + { + int status; + ++ if (phydev->drv->update_link) ++ return phydev->drv->update_link(phydev); ++ + /* Do a fake read */ + status = phy_read(phydev, MII_BMSR); + if (status < 0) diff --git a/target/linux/generic/patches-4.0/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/patches-4.0/703-phy-add-detach-callback-to-struct-phy_driver.patch new file mode 100644 index 0000000..85888f7 --- /dev/null +++ b/target/linux/generic/patches-4.0/703-phy-add-detach-callback-to-struct-phy_driver.patch @@ -0,0 +1,27 @@ +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -674,6 +674,9 @@ void phy_detach(struct phy_device *phyde + { + int i; + ++ if (phydev->drv && phydev->drv->detach) ++ phydev->drv->detach(phydev); ++ + if (phydev->bus->dev.driver) + module_put(phydev->bus->dev.driver->owner); + +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -507,6 +507,12 @@ struct phy_driver { + */ + int (*did_interrupt)(struct phy_device *phydev); + ++ /* ++ * Called before an ethernet device is detached ++ * from the PHY. ++ */ ++ void (*detach)(struct phy_device *phydev); ++ + /* Clears up any memory if needed */ + void (*remove)(struct phy_device *phydev); + diff --git a/target/linux/generic/patches-4.0/704-phy-no-genphy-soft-reset.patch b/target/linux/generic/patches-4.0/704-phy-no-genphy-soft-reset.patch new file mode 100644 index 0000000..41a6d91 --- /dev/null +++ b/target/linux/generic/patches-4.0/704-phy-no-genphy-soft-reset.patch @@ -0,0 +1,29 @@ +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -1147,7 +1147,7 @@ int genphy_config_init(struct phy_device + return 0; + } + +-static int gen10g_soft_reset(struct phy_device *phydev) ++static int no_soft_reset(struct phy_device *phydev) + { + /* Do nothing for now */ + return 0; +@@ -1361,7 +1361,7 @@ static struct phy_driver genphy_driver[] + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic PHY", +- .soft_reset = genphy_soft_reset, ++ .soft_reset = no_soft_reset, + .config_init = genphy_config_init, + .features = PHY_GBIT_FEATURES | SUPPORTED_MII | + SUPPORTED_AUI | SUPPORTED_FIBRE | +@@ -1376,7 +1376,7 @@ static struct phy_driver genphy_driver[] + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic 10G PHY", +- .soft_reset = gen10g_soft_reset, ++ .soft_reset = no_soft_reset, + .config_init = gen10g_config_init, + .features = 0, + .config_aneg = gen10g_config_aneg, diff --git a/target/linux/generic/patches-4.0/710-phy-add-mdio_register_board_info.patch b/target/linux/generic/patches-4.0/710-phy-add-mdio_register_board_info.patch new file mode 100644 index 0000000..2bc91d5 --- /dev/null +++ b/target/linux/generic/patches-4.0/710-phy-add-mdio_register_board_info.patch @@ -0,0 +1,193 @@ +--- a/drivers/net/phy/mdio_bus.c ++++ b/drivers/net/phy/mdio_bus.c +@@ -38,6 +38,8 @@ + + #include + ++#include "mdio-boardinfo.h" ++ + /** + * mdiobus_alloc_size - allocate a mii_bus structure + * @size: extra amount of memory to allocate for private storage. +@@ -335,9 +337,21 @@ void mdiobus_free(struct mii_bus *bus) + } + EXPORT_SYMBOL(mdiobus_free); + ++static void mdiobus_setup_phydev_from_boardinfo(struct mii_bus *bus, ++ struct phy_device *phydev, ++ struct mdio_board_info *bi) ++{ ++ if (strcmp(bus->id, bi->bus_id) || ++ bi->phy_addr != phydev->addr) ++ return; ++ ++ phydev->dev.platform_data = (void *) bi->platform_data; ++} ++ + struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr) + { + struct phy_device *phydev; ++ struct mdio_board_entry *be; + int err; + + phydev = get_phy_device(bus, addr, false); +@@ -350,6 +364,12 @@ struct phy_device *mdiobus_scan(struct m + */ + of_mdiobus_link_phydev(bus, phydev); + ++ mutex_lock(&__mdio_board_lock); ++ list_for_each_entry(be, &__mdio_board_list, list) ++ mdiobus_setup_phydev_from_boardinfo(bus, phydev, ++ &be->board_info); ++ mutex_unlock(&__mdio_board_lock); ++ + err = phy_device_register(phydev); + if (err) { + phy_device_free(phydev); +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -800,6 +800,23 @@ void mdio_bus_exit(void); + + extern struct bus_type mdio_bus_type; + ++struct mdio_board_info { ++ const char *bus_id; ++ int phy_addr; ++ ++ const void *platform_data; ++}; ++ ++#ifdef CONFIG_MDIO_BOARDINFO ++int mdiobus_register_board_info(const struct mdio_board_info *info, unsigned n); ++#else ++static inline int ++mdiobus_register_board_info(const struct mdio_board_info *info, unsigned n) ++{ ++ return 0; ++} ++#endif ++ + /** + * module_phy_driver() - Helper macro for registering PHY drivers + * @__phy_drivers: array of PHY drivers to register +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -12,6 +12,10 @@ menuconfig PHYLIB + + if PHYLIB + ++config MDIO_BOARDINFO ++ bool ++ default y ++ + config SWCONFIG + tristate "Switch configuration API" + ---help--- +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -2,6 +2,8 @@ + + libphy-objs := phy.o phy_device.o mdio_bus.o + ++obj-$(CONFIG_MDIO_BOARDINFO) += mdio-boardinfo.o ++ + obj-$(CONFIG_PHYLIB) += libphy.o + obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_MARVELL_PHY) += marvell.o +--- /dev/null ++++ b/drivers/net/phy/mdio-boardinfo.c +@@ -0,0 +1,58 @@ ++/* ++ * mdio-boardinfo.c - collect pre-declarations of PHY devices ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdio-boardinfo.h" ++ ++/* ++ * These symbols are exported ONLY FOR the mdio_bus component. ++ * No other users will be supported. ++ */ ++ ++LIST_HEAD(__mdio_board_list); ++EXPORT_SYMBOL_GPL(__mdio_board_list); ++ ++DEFINE_MUTEX(__mdio_board_lock); ++EXPORT_SYMBOL_GPL(__mdio_board_lock); ++ ++/** ++ * mdio_register_board_info - register PHY devices for a given board ++ * @info: array of chip descriptors ++ * @n: how many descriptors are provided ++ * Context: can sleep ++ * ++ * The board info passed can safely be __initdata ... but be careful of ++ * any embedded pointers (platform_data, etc), they're copied as-is. ++ */ ++int __init ++mdiobus_register_board_info(struct mdio_board_info const *info, unsigned n) ++{ ++ struct mdio_board_entry *be; ++ int i; ++ ++ be = kzalloc(n * sizeof(*be), GFP_KERNEL); ++ if (!be) ++ return -ENOMEM; ++ ++ for (i = 0; i < n; i++, be++, info++) { ++ memcpy(&be->board_info, info, sizeof(*info)); ++ mutex_lock(&__mdio_board_lock); ++ list_add_tail(&be->list, &__mdio_board_list); ++ mutex_unlock(&__mdio_board_lock); ++ } ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/net/phy/mdio-boardinfo.h +@@ -0,0 +1,22 @@ ++/* ++ * mdio-boardinfo.h - boardinfo interface internal to the mdio_bus component ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++ ++struct mdio_board_entry { ++ struct list_head list; ++ struct mdio_board_info board_info; ++}; ++ ++/* __mdio_board_lock protects __mdio_board_list ++ * only mdio_bus components are allowed to use these symbols. ++ */ ++extern struct mutex __mdio_board_lock; ++extern struct list_head __mdio_board_list; +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -16,7 +16,7 @@ obj-$(CONFIG_MII) += mii.o + obj-$(CONFIG_MDIO) += mdio.o + obj-$(CONFIG_NET) += Space.o loopback.o + obj-$(CONFIG_NETCONSOLE) += netconsole.o +-obj-$(CONFIG_PHYLIB) += phy/ ++obj-y += phy/ + obj-$(CONFIG_RIONET) += rionet.o + obj-$(CONFIG_NET_TEAM) += team/ + obj-$(CONFIG_TUN) += tun.o diff --git a/target/linux/generic/patches-4.0/720-phy_adm6996.patch b/target/linux/generic/patches-4.0/720-phy_adm6996.patch new file mode 100644 index 0000000..0f8b261 --- /dev/null +++ b/target/linux/generic/patches-4.0/720-phy_adm6996.patch @@ -0,0 +1,26 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -132,6 +132,13 @@ config MICREL_PHY + ---help--- + Supports the KSZ9021, VSC8201, KS8001 PHYs. + ++config ADM6996_PHY ++ tristate "Driver for ADM6996 switches" ++ select SWCONFIG ++ ---help--- ++ Currently supports the ADM6996FC and ADM6996M switches. ++ Support for FC is very limited. ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o + obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o ++obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.0/721-phy_packets.patch b/target/linux/generic/patches-4.0/721-phy_packets.patch new file mode 100644 index 0000000..f3ee626 --- /dev/null +++ b/target/linux/generic/patches-4.0/721-phy_packets.patch @@ -0,0 +1,161 @@ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1260,6 +1260,7 @@ enum netdev_priv_flags { + IFF_XMIT_DST_RELEASE_PERM = 1<<22, + IFF_IPVLAN_MASTER = 1<<23, + IFF_IPVLAN_SLAVE = 1<<24, ++ IFF_NO_IP_ALIGN = 1<<25, + }; + + #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN +@@ -1287,6 +1288,7 @@ enum netdev_priv_flags { + #define IFF_XMIT_DST_RELEASE_PERM IFF_XMIT_DST_RELEASE_PERM + #define IFF_IPVLAN_MASTER IFF_IPVLAN_MASTER + #define IFF_IPVLAN_SLAVE IFF_IPVLAN_SLAVE ++#define IFF_NO_IP_ALIGN IFF_NO_IP_ALIGN + + /** + * struct net_device - The DEVICE structure. +@@ -1559,6 +1561,11 @@ struct net_device { + const struct ethtool_ops *ethtool_ops; + const struct forwarding_accel_ops *fwd_ops; + ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ void (*eth_mangle_rx)(struct net_device *dev, struct sk_buff *skb); ++ struct sk_buff *(*eth_mangle_tx)(struct net_device *dev, struct sk_buff *skb); ++#endif ++ + const struct header_ops *header_ops; + + unsigned int flags; +@@ -1624,6 +1631,10 @@ struct net_device { + struct wireless_dev *ieee80211_ptr; + struct wpan_dev *ieee802154_ptr; + ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ void *phy_ptr; /* PHY device specific data */ ++#endif ++ + /* + * Cache lines mostly used on receive path (including eth_type_trans()) + */ +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2058,6 +2058,10 @@ static inline int pskb_trim(struct sk_bu + return (len < skb->len) ? __pskb_trim(skb, len) : 0; + } + ++extern struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, ++ unsigned int length, gfp_t gfp); ++ ++ + /** + * pskb_trim_unique - remove end from a paged unique (not cloned) buffer + * @skb: buffer to alter +@@ -2184,16 +2188,6 @@ static inline struct sk_buff *dev_alloc_ + } + + +-static inline struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, +- unsigned int length, gfp_t gfp) +-{ +- struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); +- +- if (NET_IP_ALIGN && skb) +- skb_reserve(skb, NET_IP_ALIGN); +- return skb; +-} +- + static inline struct sk_buff *netdev_alloc_skb_ip_align(struct net_device *dev, + unsigned int length) + { +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -25,6 +25,12 @@ menuconfig NET + + if NET + ++config ETHERNET_PACKET_MANGLE ++ bool ++ help ++ This option can be selected by phy drivers that need to mangle ++ packets going in or out of an ethernet device. ++ + config WANT_COMPAT_NETLINK_MESSAGES + bool + help +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -2618,10 +2618,20 @@ static int xmit_one(struct sk_buff *skb, + if (!list_empty(&ptype_all) || !list_empty(&dev->ptype_all)) + dev_queue_xmit_nit(skb, dev); + +- len = skb->len; +- trace_net_dev_start_xmit(skb, dev); +- rc = netdev_start_xmit(skb, dev, txq, more); +- trace_net_dev_xmit(skb, rc, dev, len); ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (!dev->eth_mangle_tx || ++ (skb = dev->eth_mangle_tx(dev, skb)) != NULL) ++#else ++ if (1) ++#endif ++ { ++ len = skb->len; ++ trace_net_dev_start_xmit(skb, dev); ++ rc = netdev_start_xmit(skb, dev, txq, more); ++ trace_net_dev_xmit(skb, rc, dev, len); ++ } else { ++ rc = NETDEV_TX_OK; ++ } + + return rc; + } +--- a/net/core/skbuff.c ++++ b/net/core/skbuff.c +@@ -63,6 +63,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -568,6 +569,22 @@ struct sk_buff *__napi_alloc_skb(struct + } + EXPORT_SYMBOL(__napi_alloc_skb); + ++struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, ++ unsigned int length, gfp_t gfp) ++{ ++ struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); ++ ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (dev && (dev->priv_flags & IFF_NO_IP_ALIGN)) ++ return skb; ++#endif ++ ++ if (NET_IP_ALIGN && skb) ++ skb_reserve(skb, NET_IP_ALIGN); ++ return skb; ++} ++EXPORT_SYMBOL(__netdev_alloc_skb_ip_align); ++ + void skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page, int off, + int size, unsigned int truesize) + { +--- a/net/ethernet/eth.c ++++ b/net/ethernet/eth.c +@@ -200,6 +200,12 @@ __be16 eth_type_trans(struct sk_buff *sk + const struct ethhdr *eth; + + skb->dev = dev; ++ ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (dev->eth_mangle_rx) ++ dev->eth_mangle_rx(dev, skb); ++#endif ++ + skb_reset_mac_header(skb); + skb_pull_inline(skb, ETH_HLEN); + eth = eth_hdr(skb); diff --git a/target/linux/generic/patches-4.0/722-phy_mvswitch.patch b/target/linux/generic/patches-4.0/722-phy_mvswitch.patch new file mode 100644 index 0000000..27faa7c --- /dev/null +++ b/target/linux/generic/patches-4.0/722-phy_mvswitch.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -139,6 +139,10 @@ config ADM6996_PHY + Currently supports the ADM6996FC and ADM6996M switches. + Support for FC is very limited. + ++config MVSWITCH_PHY ++ tristate "Driver for Marvell 88E6060 switches" ++ select ETHERNET_PACKET_MANGLE ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o ++obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.0/723-phy_ip175c.patch b/target/linux/generic/patches-4.0/723-phy_ip175c.patch new file mode 100644 index 0000000..c8e1dcb --- /dev/null +++ b/target/linux/generic/patches-4.0/723-phy_ip175c.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -143,6 +143,10 @@ config MVSWITCH_PHY + tristate "Driver for Marvell 88E6060 switches" + select ETHERNET_PACKET_MANGLE + ++config IP17XX_PHY ++ tristate "Driver for IC+ IP17xx switches" ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o ++obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.0/724-phy_ar8216.patch b/target/linux/generic/patches-4.0/724-phy_ar8216.patch new file mode 100644 index 0000000..37602fa --- /dev/null +++ b/target/linux/generic/patches-4.0/724-phy_ar8216.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -147,6 +147,11 @@ config IP17XX_PHY + tristate "Driver for IC+ IP17xx switches" + select SWCONFIG + ++config AR8216_PHY ++ tristate "Driver for Atheros AR8216 switches" ++ select ETHERNET_PACKET_MANGLE ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o ++obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.0/725-phy_rtl8306.patch b/target/linux/generic/patches-4.0/725-phy_rtl8306.patch new file mode 100644 index 0000000..af6083b --- /dev/null +++ b/target/linux/generic/patches-4.0/725-phy_rtl8306.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -152,6 +152,10 @@ config AR8216_PHY + select ETHERNET_PACKET_MANGLE + select SWCONFIG + ++config RTL8306_PHY ++ tristate "Driver for Realtek RTL8306S switches" ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -23,6 +23,7 @@ obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o ++obj-$(CONFIG_RTL8306_PHY) += rtl8306.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.0/726-phy_rtl8366.patch b/target/linux/generic/patches-4.0/726-phy_rtl8366.patch new file mode 100644 index 0000000..3213f1e --- /dev/null +++ b/target/linux/generic/patches-4.0/726-phy_rtl8366.patch @@ -0,0 +1,45 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -250,6 +250,30 @@ config MDIO_BCM_UNIMAC + controllers as well as some Broadcom Ethernet switches such as the + Starfighter 2 switches. + ++config RTL8366_SMI ++ tristate "Driver for the RTL8366 SMI interface" ++ depends on GPIOLIB ++ ---help--- ++ This module implements the SMI interface protocol which is used ++ by some RTL8366 ethernet switch devices via the generic GPIO API. ++ ++if RTL8366_SMI ++ ++config RTL8366_SMI_DEBUG_FS ++ bool "RTL8366 SMI interface debugfs support" ++ depends on DEBUG_FS ++ default n ++ ++config RTL8366S_PHY ++ tristate "Driver for the Realtek RTL8366S switch" ++ select SWCONFIG ++ ++config RTL8366RB_PHY ++ tristate "Driver for the Realtek RTL8366RB switch" ++ select SWCONFIG ++ ++endif # RTL8366_SMI ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -24,6 +24,9 @@ obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o + obj-$(CONFIG_RTL8306_PHY) += rtl8306.o ++obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o ++obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o ++obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.0/727-phy-rtl8367.patch b/target/linux/generic/patches-4.0/727-phy-rtl8367.patch new file mode 100644 index 0000000..6fbe34c --- /dev/null +++ b/target/linux/generic/patches-4.0/727-phy-rtl8367.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -272,6 +272,10 @@ config RTL8366RB_PHY + tristate "Driver for the Realtek RTL8366RB switch" + select SWCONFIG + ++config RTL8367_PHY ++ tristate "Driver for the Realtek RTL8367R/M switches" ++ select SWCONFIG ++ + endif # RTL8366_SMI + + endif # PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_RTL8306_PHY) += rtl8306.o + obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o + obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o + obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o ++obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.0/728-phy-rtl8367b.patch b/target/linux/generic/patches-4.0/728-phy-rtl8367b.patch new file mode 100644 index 0000000..2053b52 --- /dev/null +++ b/target/linux/generic/patches-4.0/728-phy-rtl8367b.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -276,6 +276,10 @@ config RTL8367_PHY + tristate "Driver for the Realtek RTL8367R/M switches" + select SWCONFIG + ++config RTL8367B_PHY ++ tristate "Driver fot the Realtek RTL8367R-VB switch" ++ select SWCONFIG ++ + endif # RTL8366_SMI + + endif # PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -28,6 +28,7 @@ obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi + obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o + obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o ++obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.0/729-phy-tantos.patch b/target/linux/generic/patches-4.0/729-phy-tantos.patch new file mode 100644 index 0000000..fca3ceb --- /dev/null +++ b/target/linux/generic/patches-4.0/729-phy-tantos.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -287,3 +287,8 @@ endif # PHYLIB + config MICREL_KS8995MA + tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch" + depends on SPI ++ ++config PSB6970_PHY ++ tristate "Lantiq XWAY Tantos (PSB6970) Ethernet switch" ++ select SWCONFIG ++ select ETHERNET_PACKET_MANGLE +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -30,6 +30,7 @@ obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o ++obj-$(CONFIG_PSB6970_PHY) += psb6970.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/generic/patches-4.0/730-phy_b53.patch b/target/linux/generic/patches-4.0/730-phy_b53.patch new file mode 100644 index 0000000..7e3a117 --- /dev/null +++ b/target/linux/generic/patches-4.0/730-phy_b53.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -282,6 +282,8 @@ config RTL8367B_PHY + + endif # RTL8366_SMI + ++source "drivers/net/phy/b53/Kconfig" ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -31,6 +31,7 @@ obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_PSB6970_PHY) += psb6970.o ++obj-$(CONFIG_B53) += b53/ + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/generic/patches-4.0/731-phy_mvswitch_3.10_compilation.patch b/target/linux/generic/patches-4.0/731-phy_mvswitch_3.10_compilation.patch new file mode 100644 index 0000000..2053bd2 --- /dev/null +++ b/target/linux/generic/patches-4.0/731-phy_mvswitch_3.10_compilation.patch @@ -0,0 +1,35 @@ +From e6a5abb9a02be0bceb4782d9f736bfb4ae217505 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Sep 2013 13:56:51 +0200 +Subject: [PATCH] phy: mvswitch: fix 3.10 compilation + +Update to API changes in 3.10. + +Signed-off-by: Jonas Gorsi +--- + target/linux/generic/files/drivers/net/phy/mvswitch.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mvswitch.c ++++ b/drivers/net/phy/mvswitch.c +@@ -173,7 +173,7 @@ mvswitch_mangle_rx(struct net_device *de + if (vlan == -1) + return; + +- __vlan_hwaccel_put_tag(skb, vlan); ++ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan); + } + + +@@ -307,9 +307,9 @@ mvswitch_config_init(struct phy_device * + + #ifdef HEADER_MODE + dev->priv_flags |= IFF_NO_IP_ALIGN; +- dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; + #else +- dev->features |= NETIF_F_HW_VLAN_RX; ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX; + #endif + + return 0; diff --git a/target/linux/generic/patches-4.0/732-phy-ar8216-led-support.patch b/target/linux/generic/patches-4.0/732-phy-ar8216-led-support.patch new file mode 100644 index 0000000..c753967 --- /dev/null +++ b/target/linux/generic/patches-4.0/732-phy-ar8216-led-support.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -152,6 +152,10 @@ config AR8216_PHY + select ETHERNET_PACKET_MANGLE + select SWCONFIG + ++config AR8216_PHY_LEDS ++ bool "Atheros AR8216 switch LED support" ++ depends on (AR8216_PHY && LEDS_CLASS) ++ + config RTL8306_PHY + tristate "Driver for Realtek RTL8306S switches" + select SWCONFIG diff --git a/target/linux/generic/patches-4.0/733-phy_mvsw61xx.patch b/target/linux/generic/patches-4.0/733-phy_mvsw61xx.patch new file mode 100644 index 0000000..041d168 --- /dev/null +++ b/target/linux/generic/patches-4.0/733-phy_mvsw61xx.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -143,6 +143,10 @@ config MVSWITCH_PHY + tristate "Driver for Marvell 88E6060 switches" + select ETHERNET_PACKET_MANGLE + ++config MVSW61XX_PHY ++ tristate "Driver for Marvell 88E6171/6172 switches" ++ select SWCONFIG ++ + config IP17XX_PHY + tristate "Driver for IC+ IP17xx switches" + select SWCONFIG +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o ++obj-$(CONFIG_MVSW61XX_PHY) += mvsw61xx.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o diff --git a/target/linux/generic/patches-4.0/750-hostap_txpower.patch b/target/linux/generic/patches-4.0/750-hostap_txpower.patch new file mode 100644 index 0000000..768c80f --- /dev/null +++ b/target/linux/generic/patches-4.0/750-hostap_txpower.patch @@ -0,0 +1,154 @@ +--- a/drivers/net/wireless/hostap/hostap_ap.c ++++ b/drivers/net/wireless/hostap/hostap_ap.c +@@ -2403,13 +2403,13 @@ int prism2_ap_get_sta_qual(local_info_t + addr[count].sa_family = ARPHRD_ETHER; + memcpy(addr[count].sa_data, sta->addr, ETH_ALEN); + if (sta->last_rx_silence == 0) +- qual[count].qual = sta->last_rx_signal < 27 ? +- 0 : (sta->last_rx_signal - 27) * 92 / 127; ++ qual[count].qual = (sta->last_rx_signal - 156) == 0 ? ++ 0 : (sta->last_rx_signal - 156) * 92 / 64; + else +- qual[count].qual = sta->last_rx_signal - +- sta->last_rx_silence - 35; +- qual[count].level = HFA384X_LEVEL_TO_dBm(sta->last_rx_signal); +- qual[count].noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); ++ qual[count].qual = (sta->last_rx_signal - ++ sta->last_rx_silence) * 92 / 64; ++ qual[count].level = sta->last_rx_signal; ++ qual[count].noise = sta->last_rx_silence; + qual[count].updated = sta->last_rx_updated; + + sta->last_rx_updated = IW_QUAL_DBM; +@@ -2475,13 +2475,13 @@ int prism2_ap_translate_scan(struct net_ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + if (sta->last_rx_silence == 0) +- iwe.u.qual.qual = sta->last_rx_signal < 27 ? +- 0 : (sta->last_rx_signal - 27) * 92 / 127; ++ iwe.u.qual.qual = (sta->last_rx_signal -156) == 0 ? ++ 0 : (sta->last_rx_signal - 156) * 92 / 64; + else +- iwe.u.qual.qual = sta->last_rx_signal - +- sta->last_rx_silence - 35; +- iwe.u.qual.level = HFA384X_LEVEL_TO_dBm(sta->last_rx_signal); +- iwe.u.qual.noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); ++ iwe.u.qual.qual = (sta->last_rx_signal - ++ sta->last_rx_silence) * 92 / 64; ++ iwe.u.qual.level = sta->last_rx_signal; ++ iwe.u.qual.noise = sta->last_rx_silence; + iwe.u.qual.updated = sta->last_rx_updated; + iwe.len = IW_EV_QUAL_LEN; + current_ev = iwe_stream_add_event(info, current_ev, end_buf, +--- a/drivers/net/wireless/hostap/hostap_config.h ++++ b/drivers/net/wireless/hostap/hostap_config.h +@@ -45,4 +45,9 @@ + */ + /* #define PRISM2_NO_STATION_MODES */ + ++/* Enable TX power Setting functions ++ * (min att = -128 , max att = 127) ++ */ ++#define RAW_TXPOWER_SETTING ++ + #endif /* HOSTAP_CONFIG_H */ +--- a/drivers/net/wireless/hostap/hostap.h ++++ b/drivers/net/wireless/hostap/hostap.h +@@ -90,6 +90,7 @@ extern const struct iw_handler_def hosta + extern const struct ethtool_ops prism2_ethtool_ops; + + int hostap_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); ++int hostap_restore_power(struct net_device *dev); + + + #endif /* HOSTAP_H */ +--- a/drivers/net/wireless/hostap/hostap_hw.c ++++ b/drivers/net/wireless/hostap/hostap_hw.c +@@ -928,6 +928,7 @@ static int hfa384x_set_rid(struct net_de + prism2_hw_reset(dev); + } + ++ hostap_restore_power(dev); + return res; + } + +--- a/drivers/net/wireless/hostap/hostap_info.c ++++ b/drivers/net/wireless/hostap/hostap_info.c +@@ -435,6 +435,11 @@ static void handle_info_queue_linkstatus + } + + /* Get BSSID if we have a valid AP address */ ++ ++ if ( val == HFA384X_LINKSTATUS_CONNECTED || ++ val == HFA384X_LINKSTATUS_DISCONNECTED ) ++ hostap_restore_power(local->dev); ++ + if (connected) { + netif_carrier_on(local->dev); + netif_carrier_on(local->ddev); +--- a/drivers/net/wireless/hostap/hostap_ioctl.c ++++ b/drivers/net/wireless/hostap/hostap_ioctl.c +@@ -1479,23 +1479,20 @@ static int prism2_txpower_hfa386x_to_dBm + val = 255; + + tmp = val; +- tmp >>= 2; + +- return -12 - tmp; ++ return tmp; + } + + static u16 prism2_txpower_dBm_to_hfa386x(int val) + { + signed char tmp; + +- if (val > 20) +- return 128; +- else if (val < -43) ++ if (val > 127) + return 127; ++ else if (val < -128) ++ return 128; + + tmp = val; +- tmp = -12 - tmp; +- tmp <<= 2; + + return (unsigned char) tmp; + } +@@ -4052,3 +4049,35 @@ int hostap_ioctl(struct net_device *dev, + + return ret; + } ++ ++/* BUG FIX: Restore power setting value when lost due to F/W bug */ ++ ++int hostap_restore_power(struct net_device *dev) ++{ ++ struct hostap_interface *iface = netdev_priv(dev); ++ local_info_t *local = iface->local; ++ ++ u16 val; ++ int ret = 0; ++ ++ if (local->txpower_type == PRISM2_TXPOWER_OFF) { ++ val = 0xff; /* use all standby and sleep modes */ ++ ret = local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, ++ HFA386X_CR_A_D_TEST_MODES2, ++ &val, NULL); ++ } ++ ++#ifdef RAW_TXPOWER_SETTING ++ if (local->txpower_type == PRISM2_TXPOWER_FIXED) { ++ val = HFA384X_TEST_CFG_BIT_ALC; ++ local->func->cmd(dev, HFA384X_CMDCODE_TEST | ++ (HFA384X_TEST_CFG_BITS << 8), 0, &val, NULL); ++ val = prism2_txpower_dBm_to_hfa386x(local->txpower); ++ ret = (local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, ++ HFA386X_CR_MANUAL_TX_POWER, &val, NULL)); ++ } ++#endif /* RAW_TXPOWER_SETTING */ ++ return (ret ? -EOPNOTSUPP : 0); ++} ++ ++EXPORT_SYMBOL(hostap_restore_power); diff --git a/target/linux/generic/patches-4.0/760-8139cp-fixes-from-4.3.patch b/target/linux/generic/patches-4.0/760-8139cp-fixes-from-4.3.patch new file mode 100644 index 0000000..6cbcf2e --- /dev/null +++ b/target/linux/generic/patches-4.0/760-8139cp-fixes-from-4.3.patch @@ -0,0 +1,367 @@ +commit 41b976414c88016e2c9d9b2f6667ee67a998d388 +Author: David Woodhouse +Date: Wed Sep 23 09:45:31 2015 +0100 + + 8139cp: Dump contents of descriptor ring on TX timeout + + We are seeing unexplained TX timeouts under heavy load. Let's try to get + a better idea of what's going on. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 7f4c685633e2df9ba10d49a31dda13715745db37 +Author: David Woodhouse +Date: Wed Sep 23 09:45:16 2015 +0100 + + 8139cp: Fix DMA unmapping of transmitted buffers + + The low 16 bits of the 'opts1' field in the TX descriptor are supposed + to still contain the buffer length when the descriptor is handed back to + us. In practice, at least on my hardware, they don't. So stash the + original value of the opts1 field and get the length to unmap from + there. + + There are other ways we could have worked out the length, but I actually + want a stash of the opts1 field anyway so that I can dump it alongside + the contents of the descriptor ring when we suffer a TX timeout. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 0a5aeee0b79fa99d8e04c98dd4e87d4f52aa497b +Author: David Woodhouse +Date: Wed Sep 23 09:44:57 2015 +0100 + + 8139cp: Reduce duplicate csum/tso code in cp_start_xmit() + + We calculate the value of the opts1 descriptor field in three different + places. With two different behaviours when given an invalid packet to + be checksummed — none of them correct. Sort that out. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit a3b804043f490aeec57d8ca5baccdd35e6250857 +Author: David Woodhouse +Date: Wed Sep 23 09:44:38 2015 +0100 + + 8139cp: Fix TSO/scatter-gather descriptor setup + + When sending a TSO frame in multiple buffers, we were neglecting to set + the first descriptor up in TSO mode. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 26b0bad6ac3a0167792dc4ffb276c29bc597d239 +Author: David Woodhouse +Date: Wed Sep 23 09:44:06 2015 +0100 + + 8139cp: Fix tx_queued debug message to print correct slot numbers + + After a certain amount of staring at the debug output of this driver, I + realised it was lying to me. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit aaa0062ecf4877a26dea66bee1039c6eaf906c94 +Author: David Woodhouse +Date: Wed Sep 23 09:43:41 2015 +0100 + + 8139cp: Do not re-enable RX interrupts in cp_tx_timeout() + + If an RX interrupt was already received but NAPI has not yet run when + the RX timeout happens, we end up in cp_tx_timeout() with RX interrupts + already disabled. Blindly re-enabling them will cause an IRQ storm. + + (This is made particularly horrid by the fact that cp_interrupt() always + returns that it's handled the interrupt, even when it hasn't actually + done anything. If it didn't do that, the core IRQ code would have + detected the storm and handled it, I'd have had a clear smoking gun + backtrace instead of just a spontaneously resetting router, and I'd have + at *least* two days of my life back. Changing the return value of + cp_interrupt() will be argued about under separate cover.) + + Unconditionally leave RX interrupts disabled after the reset, and + schedule NAPI to check the receive ring and re-enable them. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 7a8a8e75d505147358b225173e890ada43a267e2 +Author: David Woodhouse +Date: Fri Sep 18 00:21:54 2015 +0100 + + 8139cp: Call __cp_set_rx_mode() from cp_tx_timeout() + + Unless we reset the RX config, on real hardware I don't seem to receive + any packets after a TX timeout. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit fc27bd115b334e3ebdc682a42a47c3aea2566dcc +Author: David Woodhouse +Date: Fri Sep 18 00:19:08 2015 +0100 + + 8139cp: Use dev_kfree_skb_any() instead of dev_kfree_skb() in cp_clean_rings() + + This can be called from cp_tx_timeout() with interrupts disabled. + Spotted by Francois Romieu + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller +diff --git a/drivers/net/ethernet/realtek/8139cp.c b/drivers/net/ethernet/realtek/8139cp.c +index d79e33b..686334f 100644 +--- a/drivers/net/ethernet/realtek/8139cp.c ++++ b/drivers/net/ethernet/realtek/8139cp.c +@@ -157,6 +157,7 @@ enum { + NWayAdvert = 0x66, /* MII ADVERTISE */ + NWayLPAR = 0x68, /* MII LPA */ + NWayExpansion = 0x6A, /* MII Expansion */ ++ TxDmaOkLowDesc = 0x82, /* Low 16 bit address of a Tx descriptor. */ + Config5 = 0xD8, /* Config5 */ + TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ + RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ +@@ -341,6 +342,7 @@ struct cp_private { + unsigned tx_tail; + struct cp_desc *tx_ring; + struct sk_buff *tx_skb[CP_TX_RING_SIZE]; ++ u32 tx_opts[CP_TX_RING_SIZE]; + + unsigned rx_buf_sz; + unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */ +@@ -665,7 +667,7 @@ static void cp_tx (struct cp_private *cp) + BUG_ON(!skb); + + dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr), +- le32_to_cpu(txd->opts1) & 0xffff, ++ cp->tx_opts[tx_tail] & 0xffff, + PCI_DMA_TODEVICE); + + if (status & LastFrag) { +@@ -733,7 +735,7 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb, + { + struct cp_private *cp = netdev_priv(dev); + unsigned entry; +- u32 eor, flags; ++ u32 eor, opts1; + unsigned long intr_flags; + __le32 opts2; + int mss = 0; +@@ -753,6 +755,21 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb, + mss = skb_shinfo(skb)->gso_size; + + opts2 = cpu_to_le32(cp_tx_vlan_tag(skb)); ++ opts1 = DescOwn; ++ if (mss) ++ opts1 |= LargeSend | ((mss & MSSMask) << MSSShift); ++ else if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ const struct iphdr *ip = ip_hdr(skb); ++ if (ip->protocol == IPPROTO_TCP) ++ opts1 |= IPCS | TCPCS; ++ else if (ip->protocol == IPPROTO_UDP) ++ opts1 |= IPCS | UDPCS; ++ else { ++ WARN_ONCE(1, ++ "Net bug: asked to checksum invalid Legacy IP packet\n"); ++ goto out_dma_error; ++ } ++ } + + if (skb_shinfo(skb)->nr_frags == 0) { + struct cp_desc *txd = &cp->tx_ring[entry]; +@@ -768,31 +785,20 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb, + txd->addr = cpu_to_le64(mapping); + wmb(); + +- flags = eor | len | DescOwn | FirstFrag | LastFrag; +- +- if (mss) +- flags |= LargeSend | ((mss & MSSMask) << MSSShift); +- else if (skb->ip_summed == CHECKSUM_PARTIAL) { +- const struct iphdr *ip = ip_hdr(skb); +- if (ip->protocol == IPPROTO_TCP) +- flags |= IPCS | TCPCS; +- else if (ip->protocol == IPPROTO_UDP) +- flags |= IPCS | UDPCS; +- else +- WARN_ON(1); /* we need a WARN() */ +- } ++ opts1 |= eor | len | FirstFrag | LastFrag; + +- txd->opts1 = cpu_to_le32(flags); ++ txd->opts1 = cpu_to_le32(opts1); + wmb(); + + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); ++ cp->tx_opts[entry] = opts1; ++ netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n", ++ entry, skb->len); + } else { + struct cp_desc *txd; +- u32 first_len, first_eor; ++ u32 first_len, first_eor, ctrl; + dma_addr_t first_mapping; + int frag, first_entry = entry; +- const struct iphdr *ip = ip_hdr(skb); + + /* We must give this initial chunk to the device last. + * Otherwise we could race with the device. +@@ -805,14 +811,14 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb, + goto out_dma_error; + + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); + + for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { + const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; + u32 len; +- u32 ctrl; + dma_addr_t mapping; + ++ entry = NEXT_TX(entry); ++ + len = skb_frag_size(this_frag); + mapping = dma_map_single(&cp->pdev->dev, + skb_frag_address(this_frag), +@@ -824,19 +830,7 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb, + + eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; + +- ctrl = eor | len | DescOwn; +- +- if (mss) +- ctrl |= LargeSend | +- ((mss & MSSMask) << MSSShift); +- else if (skb->ip_summed == CHECKSUM_PARTIAL) { +- if (ip->protocol == IPPROTO_TCP) +- ctrl |= IPCS | TCPCS; +- else if (ip->protocol == IPPROTO_UDP) +- ctrl |= IPCS | UDPCS; +- else +- BUG(); +- } ++ ctrl = opts1 | eor | len; + + if (frag == skb_shinfo(skb)->nr_frags - 1) + ctrl |= LastFrag; +@@ -849,8 +843,8 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb, + txd->opts1 = cpu_to_le32(ctrl); + wmb(); + ++ cp->tx_opts[entry] = ctrl; + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); + } + + txd = &cp->tx_ring[first_entry]; +@@ -858,27 +852,17 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb, + txd->addr = cpu_to_le64(first_mapping); + wmb(); + +- if (skb->ip_summed == CHECKSUM_PARTIAL) { +- if (ip->protocol == IPPROTO_TCP) +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn | +- IPCS | TCPCS); +- else if (ip->protocol == IPPROTO_UDP) +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn | +- IPCS | UDPCS); +- else +- BUG(); +- } else +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn); ++ ctrl = opts1 | first_eor | first_len | FirstFrag; ++ txd->opts1 = cpu_to_le32(ctrl); + wmb(); ++ ++ cp->tx_opts[first_entry] = ctrl; ++ netif_dbg(cp, tx_queued, cp->dev, "tx queued, slots %d-%d, skblen %d\n", ++ first_entry, entry, skb->len); + } +- cp->tx_head = entry; ++ cp->tx_head = NEXT_TX(entry); + + netdev_sent_queue(dev, skb->len); +- netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n", +- entry, skb->len); + if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1)) + netif_stop_queue(dev); + +@@ -1115,6 +1099,7 @@ static int cp_init_rings (struct cp_private *cp) + { + memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); + cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd); ++ memset(cp->tx_opts, 0, sizeof(cp->tx_opts)); + + cp_init_rings_index(cp); + +@@ -1151,7 +1136,7 @@ static void cp_clean_rings (struct cp_private *cp) + desc = cp->rx_ring + i; + dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr), + cp->rx_buf_sz, PCI_DMA_FROMDEVICE); +- dev_kfree_skb(cp->rx_skb[i]); ++ dev_kfree_skb_any(cp->rx_skb[i]); + } + } + +@@ -1164,7 +1149,7 @@ static void cp_clean_rings (struct cp_private *cp) + le32_to_cpu(desc->opts1) & 0xffff, + PCI_DMA_TODEVICE); + if (le32_to_cpu(desc->opts1) & LastFrag) +- dev_kfree_skb(skb); ++ dev_kfree_skb_any(skb); + cp->dev->stats.tx_dropped++; + } + } +@@ -1172,6 +1157,7 @@ static void cp_clean_rings (struct cp_private *cp) + + memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE); + memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); ++ memset(cp->tx_opts, 0, sizeof(cp->tx_opts)); + + memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE); + memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE); +@@ -1249,7 +1235,7 @@ static void cp_tx_timeout(struct net_device *dev) + { + struct cp_private *cp = netdev_priv(dev); + unsigned long flags; +- int rc; ++ int rc, i; + + netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n", + cpr8(Cmd), cpr16(CpCmd), +@@ -1257,13 +1243,26 @@ static void cp_tx_timeout(struct net_device *dev) + + spin_lock_irqsave(&cp->lock, flags); + ++ netif_dbg(cp, tx_err, cp->dev, "TX ring head %d tail %d desc %x\n", ++ cp->tx_head, cp->tx_tail, cpr16(TxDmaOkLowDesc)); ++ for (i = 0; i < CP_TX_RING_SIZE; i++) { ++ netif_dbg(cp, tx_err, cp->dev, ++ "TX slot %d @%p: %08x (%08x) %08x %llx %p\n", ++ i, &cp->tx_ring[i], le32_to_cpu(cp->tx_ring[i].opts1), ++ cp->tx_opts[i], le32_to_cpu(cp->tx_ring[i].opts2), ++ le64_to_cpu(cp->tx_ring[i].addr), ++ cp->tx_skb[i]); ++ } ++ + cp_stop_hw(cp); + cp_clean_rings(cp); + rc = cp_init_rings(cp); + cp_start_hw(cp); +- cp_enable_irq(cp); ++ __cp_set_rx_mode(dev); ++ cpw16_f(IntrMask, cp_norx_intr_mask); + + netif_wake_queue(dev); ++ napi_schedule_irqoff(&cp->napi); + + spin_unlock_irqrestore(&cp->lock, flags); + } diff --git a/target/linux/generic/patches-4.0/761-8139cp-fixes-from-4.4.patch b/target/linux/generic/patches-4.0/761-8139cp-fixes-from-4.4.patch new file mode 100644 index 0000000..cb605e5 --- /dev/null +++ b/target/linux/generic/patches-4.0/761-8139cp-fixes-from-4.4.patch @@ -0,0 +1,105 @@ +commit 8b7a7048220f86547db31de0abe1ea6dd2cfa892 +Author: David Woodhouse +Date: Thu Sep 24 11:38:22 2015 +0100 + + 8139cp: Fix GSO MSS handling + + When fixing the TSO support I noticed we just mask ->gso_size with the + MSSMask value and don't care about the consequences. + + Provide a .ndo_features_check() method which drops the NETIF_F_TSO + feature for any skb which would exceed the maximum, and thus forces it + to be segmented by software. + + Then we can stop the masking in cp_start_xmit(), and just WARN if the + maximum is exceeded, which should now never happen. + + Finally, Francois Romieu noticed that we didn't even have the right + value for MSSMask anyway; it should be 0x7ff (11 bits) not 0xfff. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 5a58f227790faded5a3ef6075f3ddd65093e0f86 +Author: David Woodhouse +Date: Wed Sep 23 09:46:09 2015 +0100 + + 8139cp: Enable offload features by default + + I fixed TSO. Hardware checksum and scatter/gather also appear to be + working correctly both on real hardware and in QEMU's emulation. + + Let's enable them by default and see if anyone screams... + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller +diff --git a/drivers/net/ethernet/realtek/8139cp.c b/drivers/net/ethernet/realtek/8139cp.c +index 686334f..deae10d 100644 +--- a/drivers/net/ethernet/realtek/8139cp.c ++++ b/drivers/net/ethernet/realtek/8139cp.c +@@ -175,7 +175,7 @@ enum { + LastFrag = (1 << 28), /* Final segment of a packet */ + LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ + MSSShift = 16, /* MSS value position */ +- MSSMask = 0xfff, /* MSS value: 11 bits */ ++ MSSMask = 0x7ff, /* MSS value: 11 bits */ + TxError = (1 << 23), /* Tx error summary */ + RxError = (1 << 20), /* Rx error summary */ + IPCS = (1 << 18), /* Calculate IP checksum */ +@@ -754,10 +754,16 @@ static netdev_tx_t cp_start_xmit (struct sk_buff *skb, + eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; + mss = skb_shinfo(skb)->gso_size; + ++ if (mss > MSSMask) { ++ WARN_ONCE(1, "Net bug: GSO size %d too large for 8139CP\n", ++ mss); ++ goto out_dma_error; ++ } ++ + opts2 = cpu_to_le32(cp_tx_vlan_tag(skb)); + opts1 = DescOwn; + if (mss) +- opts1 |= LargeSend | ((mss & MSSMask) << MSSShift); ++ opts1 |= LargeSend | (mss << MSSShift); + else if (skb->ip_summed == CHECKSUM_PARTIAL) { + const struct iphdr *ip = ip_hdr(skb); + if (ip->protocol == IPPROTO_TCP) +@@ -1852,6 +1858,15 @@ static void cp_set_d3_state (struct cp_private *cp) + pci_set_power_state (cp->pdev, PCI_D3hot); + } + ++static netdev_features_t cp_features_check(struct sk_buff *skb, ++ struct net_device *dev, ++ netdev_features_t features) ++{ ++ if (skb_shinfo(skb)->gso_size > MSSMask) ++ features &= ~NETIF_F_TSO; ++ ++ return vlan_features_check(skb, features); ++} + static const struct net_device_ops cp_netdev_ops = { + .ndo_open = cp_open, + .ndo_stop = cp_close, +@@ -1864,6 +1879,7 @@ static const struct net_device_ops cp_netdev_ops = { + .ndo_tx_timeout = cp_tx_timeout, + .ndo_set_features = cp_set_features, + .ndo_change_mtu = cp_change_mtu, ++ .ndo_features_check = cp_features_check, + + #ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = cp_poll_controller, +@@ -1983,12 +1999,12 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) + dev->ethtool_ops = &cp_ethtool_ops; + dev->watchdog_timeo = TX_TIMEOUT; + +- dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; ++ dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | ++ NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; + + if (pci_using_dac) + dev->features |= NETIF_F_HIGHDMA; + +- /* disabled by default until verified */ + dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | + NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; + dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | diff --git a/target/linux/generic/patches-4.0/773-bgmac-add-srab-switch.patch b/target/linux/generic/patches-4.0/773-bgmac-add-srab-switch.patch new file mode 100644 index 0000000..b883d73 --- /dev/null +++ b/target/linux/generic/patches-4.0/773-bgmac-add-srab-switch.patch @@ -0,0 +1,72 @@ +Register switch connected to srab + +Signed-off-by: Hauke Mehrtens + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + static const struct bcma_device_id bgmac_bcma_tbl[] = { +@@ -1538,6 +1539,17 @@ static void bgmac_mii_unregister(struct + mdiobus_free(mii_bus); + } + ++static struct b53_platform_data bgmac_b53_pdata = { ++}; ++ ++static struct platform_device bgmac_b53_dev = { ++ .name = "b53-srab-switch", ++ .id = -1, ++ .dev = { ++ .platform_data = &bgmac_b53_pdata, ++ }, ++}; ++ + /************************************************** + * BCMA bus ops + **************************************************/ +@@ -1664,6 +1676,16 @@ static int bgmac_probe(struct bcma_devic + net_dev->hw_features = net_dev->features; + net_dev->vlan_features = net_dev->features; + ++ if ((ci->id == BCMA_CHIP_ID_BCM4707 || ++ ci->id == BCMA_CHIP_ID_BCM53018) && ++ !bgmac_b53_pdata.regs) { ++ bgmac_b53_pdata.regs = ioremap_nocache(0x18007000, 0x1000); ++ ++ err = platform_device_register(&bgmac_b53_dev); ++ if (!err) ++ bgmac->b53_device = &bgmac_b53_dev; ++ } ++ + err = register_netdev(bgmac->net_dev); + if (err) { + bgmac_err(bgmac, "Cannot register net device\n"); +@@ -1690,6 +1712,10 @@ static void bgmac_remove(struct bcma_dev + { + struct bgmac *bgmac = bcma_get_drvdata(core); + ++ if (bgmac->b53_device) ++ platform_device_unregister(&bgmac_b53_dev); ++ bgmac->b53_device = NULL; ++ + unregister_netdev(bgmac->net_dev); + bgmac_mii_unregister(bgmac); + netif_napi_del(&bgmac->napi); +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -462,6 +462,9 @@ struct bgmac { + bool has_robosw; + + bool loopback; ++ ++ /* platform device for associated switch */ ++ struct platform_device *b53_device; + }; + + static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset) diff --git a/target/linux/generic/patches-4.0/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch b/target/linux/generic/patches-4.0/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch new file mode 100644 index 0000000..2603d6c --- /dev/null +++ b/target/linux/generic/patches-4.0/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch @@ -0,0 +1,40 @@ +From cb06d102327eadcd1bdc480bfd9f8876251d1007 Mon Sep 17 00:00:00 2001 +From: Christoph Paasch +Date: Fri, 21 Mar 2014 03:48:19 -0700 +Subject: [PATCH] igb: Fix Null-pointer dereference in igb_reset_q_vector + +When igb_set_interrupt_capability() calls +igb_reset_interrupt_capability() (e.g., because CONFIG_PCI_MSI is unset), +num_q_vectors has been set but no vector has yet been allocated. + +igb_reset_interrupt_capability() will then call igb_reset_q_vector, +which assumes that the vector is allocated. As this is not the case, we +are accessing a NULL-pointer. + +This patch fixes it by checking that q_vector is indeed different from +NULL. + +Fixes: 02ef6e1d0b0023 (igb: Fix queue allocation method to accommodate changing during runtime) +Cc: Carolyn Wyborny +Signed-off-by: Christoph Paasch +Tested-by: Jeff Pieper +Signed-off-by: Jeff Kirsher +--- + drivers/net/ethernet/intel/igb/igb_main.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/ethernet/intel/igb/igb_main.c ++++ b/drivers/net/ethernet/intel/igb/igb_main.c +@@ -1032,6 +1032,12 @@ static void igb_reset_q_vector(struct ig + if (!q_vector) + return; + ++ /* Coming from igb_set_interrupt_capability, the vectors are not yet ++ * allocated. So, q_vector is NULL so we should stop here. ++ */ ++ if (!q_vector) ++ return; ++ + if (q_vector->tx.ring) + adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; + diff --git a/target/linux/generic/patches-4.0/785-hso-support-0af0-9300.patch b/target/linux/generic/patches-4.0/785-hso-support-0af0-9300.patch new file mode 100644 index 0000000..621d08f --- /dev/null +++ b/target/linux/generic/patches-4.0/785-hso-support-0af0-9300.patch @@ -0,0 +1,25 @@ +--- a/drivers/net/usb/hso.c ++++ b/drivers/net/usb/hso.c +@@ -466,6 +466,7 @@ static const struct usb_device_id hso_id + {USB_DEVICE(0x0af0, 0x8900)}, + {USB_DEVICE(0x0af0, 0x9000)}, + {USB_DEVICE(0x0af0, 0x9200)}, /* Option GTM671WFS */ ++ {USB_DEVICE(0x0af0, 0x9300)}, /* GTM 66xxWFS */ + {USB_DEVICE(0x0af0, 0xd035)}, + {USB_DEVICE(0x0af0, 0xd055)}, + {USB_DEVICE(0x0af0, 0xd155)}, +--- a/drivers/usb/storage/unusual_devs.h ++++ b/drivers/usb/storage/unusual_devs.h +@@ -1330,6 +1330,12 @@ UNUSUAL_DEV( 0x0af0, 0x8304, 0x0000, 0x0 + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + 0 ), + ++UNUSUAL_DEV( 0x0af0, 0x9300, 0x0000, 0x0000, ++ "Option", ++ "Globetrotter 66xxWFS SD-Card", ++ USB_SC_DEVICE, USB_PR_DEVICE, NULL, ++ 0 ), ++ + UNUSUAL_DEV( 0x0af0, 0xc100, 0x0000, 0x0000, + "Option", + "GI 070x SD-Card", diff --git a/target/linux/generic/patches-4.0/810-pci_disable_common_quirks.patch b/target/linux/generic/patches-4.0/810-pci_disable_common_quirks.patch new file mode 100644 index 0000000..8f72637 --- /dev/null +++ b/target/linux/generic/patches-4.0/810-pci_disable_common_quirks.patch @@ -0,0 +1,51 @@ +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -68,6 +68,12 @@ config XEN_PCIDEV_FRONTEND + The PCI device frontend driver allows the kernel to import arbitrary + PCI devices from a PCI backend to support PCI driver domains. + ++config PCI_DISABLE_COMMON_QUIRKS ++ bool "PCI disable common quirks" ++ depends on PCI ++ help ++ If you don't know what to do here, say N. ++ + config HT_IRQ + bool "Interrupts on hypertransport devices" + default y +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -41,6 +41,7 @@ static void quirk_mmio_always_on(struct + DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS + /* The Mellanox Tavor device gives false positive parity errors + * Mark this device with a broken_parity_status, to allow + * PCI scanning code to "skip" this now blacklisted device. +@@ -2925,6 +2926,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); + ++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ + + /* + * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To +@@ -2981,6 +2983,8 @@ static void fixup_debug_report(struct pc + } + } + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + /* + * Some BIOS implementations leave the Intel GPU interrupts enabled, + * even though no one is handling them (f.e. i915 driver is never loaded). +@@ -3015,6 +3019,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); + ++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ ++ + /* + * PCI devices which are on Intel chips can skip the 10ms delay + * before entering D3 mode. diff --git a/target/linux/generic/patches-4.0/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/patches-4.0/811-pci_disable_usb_common_quirks.patch new file mode 100644 index 0000000..6de4f6b --- /dev/null +++ b/target/linux/generic/patches-4.0/811-pci_disable_usb_common_quirks.patch @@ -0,0 +1,101 @@ + +--- a/drivers/usb/host/pci-quirks.c ++++ b/drivers/usb/host/pci-quirks.c +@@ -97,6 +97,8 @@ struct amd_chipset_type { + u8 rev; + }; + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + static struct amd_chipset_info { + struct pci_dev *nb_dev; + struct pci_dev *smbus_dev; +@@ -450,6 +452,10 @@ void usb_amd_dev_put(void) + } + EXPORT_SYMBOL_GPL(usb_amd_dev_put); + ++#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */ ++ ++#if IS_ENABLED(CONFIG_USB_UHCI_HCD) ++ + /* + * Make sure the controller is completely inactive, unable to + * generate interrupts or do DMA. +@@ -529,8 +535,17 @@ reset_needed: + uhci_reset_hc(pdev, base); + return 1; + } ++#else ++int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) ++{ ++ return 0; ++} ++ ++#endif + EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) + { + u16 cmd; +@@ -1095,3 +1110,4 @@ static void quirk_usb_early_handoff(stru + } + DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); ++#endif +--- a/drivers/usb/host/pci-quirks.h ++++ b/drivers/usb/host/pci-quirks.h +@@ -4,6 +4,9 @@ + #ifdef CONFIG_PCI + void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); + int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); ++#endif /* CONFIG_PCI */ ++ ++#if defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_COMMON_QUIRKS) + int usb_amd_find_chipset_info(void); + int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev); + bool usb_amd_hang_symptom_quirk(void); +@@ -16,11 +19,24 @@ void usb_disable_xhci_ports(struct pci_d + void sb800_prefetch(struct device *dev, int on); + #else + struct pci_dev; ++static inline int usb_amd_find_chipset_info(void) ++{ ++ return 0; ++} ++static inline bool usb_amd_hang_symptom_quirk(void) ++{ ++ return false; ++} ++static inline bool usb_amd_prefetch_quirk(void) ++{ ++ return false; ++} + static inline void usb_amd_quirk_pll_disable(void) {} + static inline void usb_amd_quirk_pll_enable(void) {} + static inline void usb_amd_dev_put(void) {} + static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {} + static inline void sb800_prefetch(struct device *dev, int on) {} +-#endif /* CONFIG_PCI */ ++static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {} ++#endif + + #endif /* __LINUX_USB_PCI_QUIRKS_H */ +--- a/include/linux/usb/hcd.h ++++ b/include/linux/usb/hcd.h +@@ -447,7 +447,14 @@ extern int usb_hcd_pci_probe(struct pci_ + extern void usb_hcd_pci_remove(struct pci_dev *dev); + extern void usb_hcd_pci_shutdown(struct pci_dev *dev); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS + extern int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev); ++#else ++static inline int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev) ++{ ++ return 0; ++} ++#endif + + #ifdef CONFIG_PM + extern const struct dev_pm_ops usb_hcd_pci_pm_ops; diff --git a/target/linux/generic/patches-4.0/820-usb_add_usb_find_device_by_name.patch b/target/linux/generic/patches-4.0/820-usb_add_usb_find_device_by_name.patch new file mode 100644 index 0000000..96cadf3 --- /dev/null +++ b/target/linux/generic/patches-4.0/820-usb_add_usb_find_device_by_name.patch @@ -0,0 +1,84 @@ +--- a/drivers/usb/core/usb.c ++++ b/drivers/usb/core/usb.c +@@ -688,6 +688,71 @@ int __usb_get_extra_descriptor(char *buf + } + EXPORT_SYMBOL_GPL(__usb_get_extra_descriptor); + ++static struct usb_device *match_device_name(struct usb_device *dev, ++ const char *name) ++{ ++ struct usb_device *ret_dev = NULL; ++ struct usb_device *childdev = NULL; ++ int child; ++ ++ dev_dbg(&dev->dev, "check for name %s ...\n", name); ++ ++ /* see if this device matches */ ++ if (strcmp(dev_name(&dev->dev), name) == 0 ) { ++ dev_dbg(&dev->dev, "matched this device!\n"); ++ ret_dev = usb_get_dev(dev); ++ goto exit; ++ } ++ /* look through all of the children of this device */ ++ usb_hub_for_each_child(dev, child, childdev) { ++ if (childdev) { ++ usb_lock_device(childdev); ++ ret_dev = match_device_name(childdev, name); ++ usb_unlock_device(childdev); ++ if (ret_dev) ++ goto exit; ++ } ++ } ++exit: ++ return ret_dev; ++} ++ ++/** ++ * usb_find_device_by_name - find a specific usb device in the system ++ * @name: the name of the device to find ++ * ++ * Returns a pointer to a struct usb_device if such a specified usb ++ * device is present in the system currently. The usage count of the ++ * device will be incremented if a device is found. Make sure to call ++ * usb_put_dev() when the caller is finished with the device. ++ * ++ * If a device with the specified bus id is not found, NULL is returned. ++ */ ++struct usb_device *usb_find_device_by_name(const char *name) ++{ ++ struct list_head *buslist; ++ struct usb_bus *bus; ++ struct usb_device *dev = NULL; ++ ++ mutex_lock(&usb_bus_list_lock); ++ for (buslist = usb_bus_list.next; ++ buslist != &usb_bus_list; ++ buslist = buslist->next) { ++ bus = container_of(buslist, struct usb_bus, bus_list); ++ if (!bus->root_hub) ++ continue; ++ usb_lock_device(bus->root_hub); ++ dev = match_device_name(bus->root_hub, name); ++ usb_unlock_device(bus->root_hub); ++ if (dev) ++ goto exit; ++ } ++exit: ++ mutex_unlock(&usb_bus_list_lock); ++ return dev; ++} ++EXPORT_SYMBOL_GPL(usb_find_device_by_name); ++ + /** + * usb_alloc_coherent - allocate dma-consistent buffer for URB_NO_xxx_DMA_MAP + * @dev: device the buffer will be used with +--- a/include/linux/usb.h ++++ b/include/linux/usb.h +@@ -721,6 +721,7 @@ static inline bool usb_device_no_sg_cons + return udev && udev->bus && udev->bus->no_sg_constraint; + } + ++extern struct usb_device *usb_find_device_by_name(const char *name); + + /*-------------------------------------------------------------------------*/ + diff --git a/target/linux/generic/patches-4.0/830-ledtrig_morse.patch b/target/linux/generic/patches-4.0/830-ledtrig_morse.patch new file mode 100644 index 0000000..97cc33c --- /dev/null +++ b/target/linux/generic/patches-4.0/830-ledtrig_morse.patch @@ -0,0 +1,28 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -108,4 +108,8 @@ config LEDS_TRIGGER_CAMERA + This enables direct flash/torch on/off by the driver, kernel space. + If unsure, say Y. + ++config LEDS_TRIGGER_MORSE ++ tristate "LED Morse Trigger" ++ depends on LEDS_TRIGGERS ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -64,3 +64,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ ++obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o +--- a/drivers/leds/ledtrig-morse.c ++++ b/drivers/leds/ledtrig-morse.c +@@ -26,7 +26,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/generic/patches-4.0/831-ledtrig_netdev.patch b/target/linux/generic/patches-4.0/831-ledtrig_netdev.patch new file mode 100644 index 0000000..29a2cca --- /dev/null +++ b/target/linux/generic/patches-4.0/831-ledtrig_netdev.patch @@ -0,0 +1,60 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -112,4 +112,11 @@ config LEDS_TRIGGER_MORSE + tristate "LED Morse Trigger" + depends on LEDS_TRIGGERS + ++config LEDS_TRIGGER_NETDEV ++ tristate "LED Netdev Trigger" ++ depends on NET && LEDS_TRIGGERS ++ help ++ This allows LEDs to be controlled by network device activity. ++ If unsure, say Y. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -65,3 +65,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o ++obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o +--- a/drivers/leds/ledtrig-netdev.c ++++ b/drivers/leds/ledtrig-netdev.c +@@ -22,7 +22,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -254,7 +253,7 @@ static int netdev_trig_notify(struct not + unsigned long evt, + void *dv) + { +- struct net_device *dev = dv; ++ struct net_device *dev = netdev_notifier_info_to_dev((struct netdev_notifier_info *) dv); + struct led_netdev_data *trigger_data = container_of(nb, struct led_netdev_data, notifier); + + if (evt != NETDEV_UP && evt != NETDEV_DOWN && evt != NETDEV_CHANGE && evt != NETDEV_REGISTER && evt != NETDEV_UNREGISTER) +@@ -294,8 +293,9 @@ done: + static void netdev_trig_timer(unsigned long arg) + { + struct led_netdev_data *trigger_data = (struct led_netdev_data *)arg; +- const struct net_device_stats *dev_stats; ++ struct rtnl_link_stats64 *dev_stats; + unsigned new_activity; ++ struct rtnl_link_stats64 temp; + + write_lock(&trigger_data->lock); + +@@ -305,7 +305,7 @@ static void netdev_trig_timer(unsigned l + goto no_restart; + } + +- dev_stats = dev_get_stats(trigger_data->net_dev); ++ dev_stats = dev_get_stats(trigger_data->net_dev, &temp); + new_activity = + ((trigger_data->mode & MODE_TX) ? dev_stats->tx_packets : 0) + + ((trigger_data->mode & MODE_RX) ? dev_stats->rx_packets : 0); diff --git a/target/linux/generic/patches-4.0/832-ledtrig_usbdev.patch b/target/linux/generic/patches-4.0/832-ledtrig_usbdev.patch new file mode 100644 index 0000000..25593fd --- /dev/null +++ b/target/linux/generic/patches-4.0/832-ledtrig_usbdev.patch @@ -0,0 +1,31 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -119,4 +119,11 @@ config LEDS_TRIGGER_NETDEV + This allows LEDs to be controlled by network device activity. + If unsure, say Y. + ++config LEDS_TRIGGER_USBDEV ++ tristate "LED USB device Trigger" ++ depends on USB && LEDS_TRIGGERS ++ help ++ This allows LEDs to be controlled by the presence/activity of ++ an USB device. If unsure, say N. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -66,3 +66,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o + obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o ++obj-$(CONFIG_LEDS_TRIGGER_USBDEV) += ledtrig-usbdev.o +--- a/drivers/leds/ledtrig-usbdev.c ++++ b/drivers/leds/ledtrig-usbdev.c +@@ -24,7 +24,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/generic/patches-4.0/834-ledtrig-libata.patch b/target/linux/generic/patches-4.0/834-ledtrig-libata.patch new file mode 100644 index 0000000..dcb80c8 --- /dev/null +++ b/target/linux/generic/patches-4.0/834-ledtrig-libata.patch @@ -0,0 +1,153 @@ +From 52cfd51cdf6a6e14d4fb270c6343abac3bac00f4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 12 Dec 2014 13:38:33 +0100 +Subject: [PATCH] libata: add ledtrig support +To: linux-ide@vger.kernel.org, + Tejun Heo + +This adds a LED trigger for each ATA port indicating disk activity. + +As this is needed only on specific platforms (NAS SoCs and such), +these platforms should define ARCH_WANTS_LIBATA_LEDS if there +are boards with LED(s) intended to indicate ATA disk activity and +need the OS to take care of that. +In that way, if not selected, LED trigger support not will be +included in libata-core and both, codepaths and structures remain +untouched. + +Signed-off-by: Daniel Golle +--- + drivers/ata/Kconfig | 16 ++++++++++++++++ + drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++ + include/linux/libata.h | 9 +++++++++ + 3 files changed, 66 insertions(+) + +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -46,6 +46,22 @@ config ATA_VERBOSE_ERROR + + If unsure, say Y. + ++config ARCH_WANT_LIBATA_LEDS ++ bool ++ ++config ATA_LEDS ++ bool "support ATA port LED triggers" ++ depends on ARCH_WANT_LIBATA_LEDS ++ select NEW_LEDS ++ select LEDS_CLASS ++ select LEDS_TRIGGERS ++ default y ++ help ++ This option adds a LED trigger for each registered ATA port. ++ It is used to drive disk activity leds connected via GPIO. ++ ++ If unsure, say N. ++ + config ATA_ACPI + bool "ATA ACPI Support" + depends on ACPI && PCI +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -725,6 +725,19 @@ u64 ata_tf_read_block(struct ata_taskfil + return block; + } + ++#ifdef CONFIG_ATA_LEDS ++#define LIBATA_BLINK_DELAY 20 /* ms */ ++static inline void ata_led_act(struct ata_port *ap) ++{ ++ unsigned long led_delay = LIBATA_BLINK_DELAY; ++ ++ if (unlikely(!ap->ledtrig)) ++ return; ++ ++ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0); ++} ++#endif ++ + /** + * ata_build_rw_tf - Build ATA taskfile for given read/write request + * @tf: Target ATA taskfile +@@ -4753,6 +4766,9 @@ struct ata_queued_cmd *ata_qc_new_init(s + if (tag < 0) + return NULL; + } ++#ifdef CONFIG_ATA_LEDS ++ ata_led_act(ap); ++#endif + + qc = __ata_qc_from_tag(ap, tag); + qc->tag = tag; +@@ -5647,6 +5663,9 @@ struct ata_port *ata_port_alloc(struct a + ap->stats.unhandled_irq = 1; + ap->stats.idle_irq = 1; + #endif ++#ifdef CONFIG_ATA_LEDS ++ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL); ++#endif + ata_sff_port_init(ap); + + return ap; +@@ -5668,6 +5687,12 @@ static void ata_host_release(struct devi + + kfree(ap->pmp_link); + kfree(ap->slave_link); ++#ifdef CONFIG_ATA_LEDS ++ if (ap->ledtrig) { ++ led_trigger_unregister(ap->ledtrig); ++ kfree(ap->ledtrig); ++ }; ++#endif + kfree(ap); + host->ports[i] = NULL; + } +@@ -6114,7 +6139,23 @@ int ata_host_register(struct ata_host *h + host->ports[i]->print_id = atomic_inc_return(&ata_print_id); + host->ports[i]->local_port_no = i + 1; + } ++#ifdef CONFIG_ATA_LEDS ++ for (i = 0; i < host->n_ports; i++) { ++ if (unlikely(!host->ports[i]->ledtrig)) ++ continue; + ++ snprintf(host->ports[i]->ledtrig_name, ++ sizeof(host->ports[i]->ledtrig_name), "ata%u", ++ host->ports[i]->print_id); ++ ++ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name; ++ ++ if (led_trigger_register(host->ports[i]->ledtrig)) { ++ kfree(host->ports[i]->ledtrig); ++ host->ports[i]->ledtrig = NULL; ++ } ++ } ++#endif + /* Create associated sysfs transport objects */ + for (i = 0; i < host->n_ports; i++) { + rc = ata_tport_add(host->dev,host->ports[i]); +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -38,6 +38,9 @@ + #include + #include + #include ++#ifdef CONFIG_ATA_LEDS ++#include ++#endif + + /* + * Define if arch has non-standard setup. This is a _PCI_ standard +@@ -874,6 +877,12 @@ struct ata_port { + #ifdef CONFIG_ATA_ACPI + struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ + #endif ++ ++#ifdef CONFIG_ATA_LEDS ++ struct led_trigger *ledtrig; ++ char ledtrig_name[8]; ++#endif ++ + /* owned by EH */ + u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; + }; diff --git a/target/linux/generic/patches-4.0/840-rtc7301.patch b/target/linux/generic/patches-4.0/840-rtc7301.patch new file mode 100644 index 0000000..252a0c2 --- /dev/null +++ b/target/linux/generic/patches-4.0/840-rtc7301.patch @@ -0,0 +1,250 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1099,6 +1099,15 @@ config RTC_DRV_OPAL + This driver can also be built as a module. If so, the module + will be called rtc-opal. + ++config RTC_DRV_RTC7301 ++ tristate "Epson RTC-7301 SF/DG" ++ help ++ If you say Y here you will get support for the ++ Epson RTC-7301 SF/DG RTC chips. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-7301. ++ + comment "on-CPU RTC drivers" + + config RTC_DRV_DAVINCI +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -119,6 +119,7 @@ obj-$(CONFIG_RTC_DRV_RP5C01) += rtc-rp5c + obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o + obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o + obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o ++obj-$(CONFIG_RTC_DRV_RTC7301) += rtc-rtc7301.o + obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o + obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o + obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o +--- /dev/null ++++ b/drivers/rtc/rtc-rtc7301.c +@@ -0,0 +1,219 @@ ++/* ++ * Driver for Epson RTC-7301SF/DG ++ * ++ * Copyright (C) 2009 Jose Vasconcellos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RTC_NAME "rtc7301" ++#define RTC_VERSION "0.1" ++ ++/* Epson RTC-7301 register addresses */ ++#define RTC7301_SEC 0x00 ++#define RTC7301_SEC10 0x01 ++#define RTC7301_MIN 0x02 ++#define RTC7301_MIN10 0x03 ++#define RTC7301_HOUR 0x04 ++#define RTC7301_HOUR10 0x05 ++#define RTC7301_WEEKDAY 0x06 ++#define RTC7301_DAY 0x07 ++#define RTC7301_DAY10 0x08 ++#define RTC7301_MON 0x09 ++#define RTC7301_MON10 0x0A ++#define RTC7301_YEAR 0x0B ++#define RTC7301_YEAR10 0x0C ++#define RTC7301_YEAR100 0x0D ++#define RTC7301_YEAR1000 0x0E ++#define RTC7301_CTRLREG 0x0F ++ ++static uint8_t __iomem *rtc7301_base; ++ ++#define read_reg(offset) (readb(rtc7301_base + offset) & 0xf) ++#define write_reg(offset, data) writeb(data, rtc7301_base + (offset)) ++ ++#define rtc7301_isbusy() (read_reg(RTC7301_CTRLREG) & 1) ++ ++static void rtc7301_init_settings(void) ++{ ++ int i; ++ ++ write_reg(RTC7301_CTRLREG, 2); ++ write_reg(RTC7301_YEAR1000, 2); ++ udelay(122); ++ ++ /* bank 1 */ ++ write_reg(RTC7301_CTRLREG, 6); ++ for (i=0; i<15; i++) ++ write_reg(i, 0); ++ ++ /* bank 2 */ ++ write_reg(RTC7301_CTRLREG, 14); ++ for (i=0; i<15; i++) ++ write_reg(i, 0); ++ write_reg(RTC7301_CTRLREG, 0); ++} ++ ++static int rtc7301_get_datetime(struct device *dev, struct rtc_time *dt) ++{ ++ int cnt; ++ uint8_t buf[16]; ++ ++ cnt = 0; ++ while (rtc7301_isbusy()) { ++ udelay(244); ++ if (cnt++ > 100) { ++ dev_err(dev, "%s: timeout error %x\n", __func__, rtc7301_base[RTC7301_CTRLREG]); ++ return -EIO; ++ } ++ } ++ ++ for (cnt=0; cnt<16; cnt++) ++ buf[cnt] = read_reg(cnt); ++ ++ if (buf[RTC7301_SEC10] & 8) { ++ dev_err(dev, "%s: RTC not set\n", __func__); ++ return -EINVAL; ++ } ++ ++ memset(dt, 0, sizeof(*dt)); ++ ++ dt->tm_sec = buf[RTC7301_SEC] + buf[RTC7301_SEC10]*10; ++ dt->tm_min = buf[RTC7301_MIN] + buf[RTC7301_MIN10]*10; ++ dt->tm_hour = buf[RTC7301_HOUR] + buf[RTC7301_HOUR10]*10; ++ ++ dt->tm_mday = buf[RTC7301_DAY] + buf[RTC7301_DAY10]*10; ++ dt->tm_mon = buf[RTC7301_MON] + buf[RTC7301_MON10]*10 - 1; ++ dt->tm_year = buf[RTC7301_YEAR] + buf[RTC7301_YEAR10]*10 + ++ buf[RTC7301_YEAR100]*100 + ++ ((buf[RTC7301_YEAR1000] & 3)*1000) - 1900; ++ ++ /* the rtc device may contain illegal values on power up ++ * according to the data sheet. make sure they are valid. ++ */ ++ ++ return rtc_valid_tm(dt); ++} ++ ++static int rtc7301_set_datetime(struct device *dev, struct rtc_time *dt) ++{ ++ int data; ++ ++ data = dt->tm_year + 1900; ++ if (data >= 2100 || data < 1900) ++ return -EINVAL; ++ ++ write_reg(RTC7301_CTRLREG, 2); ++ udelay(122); ++ ++ data = bin2bcd(dt->tm_sec); ++ write_reg(RTC7301_SEC, data); ++ write_reg(RTC7301_SEC10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_min); ++ write_reg(RTC7301_MIN, data ); ++ write_reg(RTC7301_MIN10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_hour); ++ write_reg(RTC7301_HOUR, data); ++ write_reg(RTC7301_HOUR10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_mday); ++ write_reg(RTC7301_DAY, data); ++ write_reg(RTC7301_DAY10, (data>> 4)); ++ ++ data = bin2bcd(dt->tm_mon + 1); ++ write_reg(RTC7301_MON, data); ++ write_reg(RTC7301_MON10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_year % 100); ++ write_reg(RTC7301_YEAR, data); ++ write_reg(RTC7301_YEAR10, (data >> 4)); ++ data = bin2bcd((1900 + dt->tm_year) / 100); ++ write_reg(RTC7301_YEAR100, data); ++ ++ data = bin2bcd(dt->tm_wday); ++ write_reg(RTC7301_WEEKDAY, data); ++ ++ write_reg(RTC7301_CTRLREG, 0); ++ ++ return 0; ++} ++ ++static const struct rtc_class_ops rtc7301_rtc_ops = { ++ .read_time = rtc7301_get_datetime, ++ .set_time = rtc7301_set_datetime, ++}; ++ ++static int rtc7301_probe(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc; ++ struct resource *res; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return -ENOENT; ++ ++ rtc7301_base = ioremap_nocache(res->start, 0x1000 /*res->end - res->start + 1*/); ++ if (!rtc7301_base) ++ return -EINVAL; ++ ++ rtc = rtc_device_register(RTC_NAME, &pdev->dev, ++ &rtc7301_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtc)) { ++ iounmap(rtc7301_base); ++ return PTR_ERR(rtc); ++ } ++ ++ platform_set_drvdata(pdev, rtc); ++ ++ rtc7301_init_settings(); ++ return 0; ++} ++ ++static int rtc7301_remove(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc = platform_get_drvdata(pdev); ++ ++ if (rtc) ++ rtc_device_unregister(rtc); ++ if (rtc7301_base) ++ iounmap(rtc7301_base); ++ return 0; ++} ++ ++static struct platform_driver rtc7301_driver = { ++ .driver = { ++ .name = RTC_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = rtc7301_probe, ++ .remove = rtc7301_remove, ++}; ++ ++static __init int rtc7301_init(void) ++{ ++ return platform_driver_register(&rtc7301_driver); ++} ++module_init(rtc7301_init); ++ ++static __exit void rtc7301_exit(void) ++{ ++ platform_driver_unregister(&rtc7301_driver); ++} ++module_exit(rtc7301_exit); ++ ++MODULE_DESCRIPTION("Epson 7301 RTC driver"); ++MODULE_AUTHOR("Jose Vasconcellos "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" RTC_NAME); ++MODULE_VERSION(RTC_VERSION); diff --git a/target/linux/generic/patches-4.0/841-rtc_pt7c4338.patch b/target/linux/generic/patches-4.0/841-rtc_pt7c4338.patch new file mode 100644 index 0000000..83ce771 --- /dev/null +++ b/target/linux/generic/patches-4.0/841-rtc_pt7c4338.patch @@ -0,0 +1,247 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -586,6 +586,15 @@ config RTC_DRV_S5M + This driver can also be built as a module. If so, the module + will be called rtc-s5m. + ++config RTC_DRV_PT7C4338 ++ tristate "Pericom Technology Inc. PT7C4338 RTC" ++ help ++ If you say yes here you get support for the Pericom Technology ++ Inc. PT7C4338 RTC chip. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-pt7c4338. ++ + endif # I2C + + comment "SPI RTC drivers" +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -110,6 +110,7 @@ obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030 + obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o + obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o + obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o ++obj-$(CONFIG_RTC_DRV_PT7C4338) += rtc-pt7c4338.o + obj-$(CONFIG_RTC_DRV_PUV3) += rtc-puv3.o + obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o + obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o +--- /dev/null ++++ b/drivers/rtc/rtc-pt7c4338.c +@@ -0,0 +1,216 @@ ++/* ++ * Copyright 2010 Freescale Semiconductor, Inc. ++ * ++ * Author: Priyanka Jain ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * This file provides Date & Time support (no alarms) for PT7C4338 chip. ++ * ++ * This file is based on drivers/rtc/rtc-ds1307.c ++ * ++ * PT7C4338 chip is manufactured by Pericom Technology Inc. ++ * It is a serial real-time clock which provides ++ * 1)Low-power clock/calendar. ++ * 2)Programmable square-wave output. ++ * It has 56 bytes of nonvolatile RAM. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* RTC register addresses */ ++#define PT7C4338_REG_SECONDS 0x00 ++#define PT7C4338_REG_MINUTES 0x01 ++#define PT7C4338_REG_HOURS 0x02 ++#define PT7C4338_REG_AMPM 0x02 ++#define PT7C4338_REG_DAY 0x03 ++#define PT7C4338_REG_DATE 0x04 ++#define PT7C4338_REG_MONTH 0x05 ++#define PT7C4338_REG_YEAR 0x06 ++#define PT7C4338_REG_CTRL_STAT 0x07 ++ ++/* RTC second register address bit */ ++#define PT7C4338_SEC_BIT_CH 0x80 /*Clock Halt (in Register 0)*/ ++ ++/* RTC control and status register bits */ ++#define PT7C4338_CTRL_STAT_BIT_RS0 0x1 /*Rate select 0*/ ++#define PT7C4338_CTRL_STAT_BIT_RS1 0x2 /*Rate select 1*/ ++#define PT7C4338_CTRL_STAT_BIT_SQWE 0x10 /*Square Wave Enable*/ ++#define PT7C4338_CTRL_STAT_BIT_OSF 0x20 /*Oscillator Stop Flag*/ ++#define PT7C4338_CTRL_STAT_BIT_OUT 0x80 /*Output Level Control*/ ++ ++static const struct i2c_device_id pt7c4338_id[] = { ++ { "pt7c4338", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, pt7c4338_id); ++ ++struct pt7c4338{ ++ struct i2c_client *client; ++ struct rtc_device *rtc; ++}; ++ ++static int pt7c4338_read_time(struct device *dev, struct rtc_time *time) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ int ret; ++ u8 buf[7]; ++ u8 year, month, day, hour, minute, second; ++ u8 week, twelve_hr, am_pm; ++ ++ ret = i2c_smbus_read_i2c_block_data(client, ++ PT7C4338_REG_SECONDS, 7, buf); ++ if (ret < 0) ++ return ret; ++ if (ret < 7) ++ return -EIO; ++ ++ second = buf[0]; ++ minute = buf[1]; ++ hour = buf[2]; ++ week = buf[3]; ++ day = buf[4]; ++ month = buf[5]; ++ year = buf[6]; ++ ++ /* Extract additional information for AM/PM */ ++ twelve_hr = hour & 0x40; ++ am_pm = hour & 0x20; ++ ++ /* Write to rtc_time structure */ ++ time->tm_sec = bcd2bin(second & 0x7f); ++ time->tm_min = bcd2bin(minute & 0x7f); ++ if (twelve_hr) { ++ /* Convert to 24 hr */ ++ if (am_pm) ++ time->tm_hour = bcd2bin(hour & 0x10) + 12; ++ else ++ time->tm_hour = bcd2bin(hour & 0xBF); ++ } else { ++ time->tm_hour = bcd2bin(hour); ++ } ++ ++ time->tm_wday = bcd2bin(week & 0x07) - 1; ++ time->tm_mday = bcd2bin(day & 0x3f); ++ time->tm_mon = bcd2bin(month & 0x1F) - 1; ++ /* assume 20YY not 19YY */ ++ time->tm_year = bcd2bin(year) + 100; ++ ++ return 0; ++} ++ ++static int pt7c4338_set_time(struct device *dev, struct rtc_time *time) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ u8 buf[7]; ++ ++ /* Extract time from rtc_time and load into pt7c4338*/ ++ buf[0] = bin2bcd(time->tm_sec); ++ buf[1] = bin2bcd(time->tm_min); ++ buf[2] = bin2bcd(time->tm_hour); ++ buf[3] = bin2bcd(time->tm_wday + 1); /* Day of the week */ ++ buf[4] = bin2bcd(time->tm_mday); /* Date */ ++ buf[5] = bin2bcd(time->tm_mon + 1); ++ ++ /* assume 20YY not 19YY */ ++ if (time->tm_year >= 100) ++ buf[6] = bin2bcd(time->tm_year - 100); ++ else ++ buf[6] = bin2bcd(time->tm_year); ++ ++ return i2c_smbus_write_i2c_block_data(client, ++ PT7C4338_REG_SECONDS, 7, buf); ++} ++ ++static const struct rtc_class_ops pt7c4338_rtc_ops = { ++ .read_time = pt7c4338_read_time, ++ .set_time = pt7c4338_set_time, ++}; ++ ++static int pt7c4338_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct pt7c4338 *pt7c4338; ++ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); ++ int ret; ++ ++ pt7c4338 = kzalloc(sizeof(struct pt7c4338), GFP_KERNEL); ++ if (!pt7c4338) ++ return -ENOMEM; ++ ++ pt7c4338->client = client; ++ i2c_set_clientdata(client, pt7c4338); ++ pt7c4338->rtc = rtc_device_register(client->name, &client->dev, ++ &pt7c4338_rtc_ops, THIS_MODULE); ++ if (IS_ERR(pt7c4338->rtc)) { ++ ret = PTR_ERR(pt7c4338->rtc); ++ dev_err(&client->dev, "unable to register the class device\n"); ++ goto out_free; ++ } ++ ++ return 0; ++out_free: ++ i2c_set_clientdata(client, NULL); ++ kfree(pt7c4338); ++ return ret; ++} ++ ++static int pt7c4338_remove(struct i2c_client *client) ++{ ++ struct pt7c4338 *pt7c4338 = i2c_get_clientdata(client); ++ ++ rtc_device_unregister(pt7c4338->rtc); ++ i2c_set_clientdata(client, NULL); ++ kfree(pt7c4338); ++ return 0; ++} ++ ++static struct i2c_driver pt7c4338_driver = { ++ .driver = { ++ .name = "rtc-pt7c4338", ++ .owner = THIS_MODULE, ++ }, ++ .probe = pt7c4338_probe, ++ .remove = pt7c4338_remove, ++ .id_table = pt7c4338_id, ++}; ++ ++static int __init pt7c4338_init(void) ++{ ++ return i2c_add_driver(&pt7c4338_driver); ++} ++ ++static void __exit pt7c4338_exit(void) ++{ ++ i2c_del_driver(&pt7c4338_driver); ++} ++ ++module_init(pt7c4338_init); ++module_exit(pt7c4338_exit); ++ ++MODULE_AUTHOR("Priyanka Jain "); ++MODULE_DESCRIPTION("pericom Technology Inc. PT7C4338 RTC Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.0/861-04_spi_gpio_implement_spi_delay.patch b/target/linux/generic/patches-4.0/861-04_spi_gpio_implement_spi_delay.patch new file mode 100644 index 0000000..fc1b40c --- /dev/null +++ b/target/linux/generic/patches-4.0/861-04_spi_gpio_implement_spi_delay.patch @@ -0,0 +1,58 @@ +Implement the SPI-GPIO delay function for busses that need speed limitation. + +--mb + + + +--- a/drivers/spi/spi-gpio.c ++++ b/drivers/spi/spi-gpio.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -69,6 +70,7 @@ struct spi_gpio { + * #define SPI_MOSI_GPIO 120 + * #define SPI_SCK_GPIO 121 + * #define SPI_N_CHIPSEL 4 ++ * #undef NEED_SPIDELAY + * #include "spi-gpio.c" + */ + +@@ -76,6 +78,7 @@ struct spi_gpio { + #define DRIVER_NAME "spi_gpio" + + #define GENERIC_BITBANG /* vs tight inlines */ ++#define NEED_SPIDELAY 1 + + /* all functions referencing these symbols must define pdata */ + #define SPI_MISO_GPIO ((pdata)->miso) +@@ -126,12 +129,20 @@ static inline int getmiso(const struct s + #undef pdata + + /* +- * NOTE: this clocks "as fast as we can". It "should" be a function of the +- * requested device clock. Software overhead means we usually have trouble +- * reaching even one Mbit/sec (except when we can inline bitops), so for now +- * we'll just assume we never need additional per-bit slowdowns. ++ * NOTE: to clock "as fast as we can", set spi_device.max_speed_hz ++ * and spi_transfer.speed_hz to 0. ++ * Otherwise this is a function of the requested device clock. ++ * Software overhead means we usually have trouble ++ * reaching even one Mbit/sec (except when we can inline bitops). So on small ++ * embedded devices with fast SPI slaves you usually don't need a delay. + */ +-#define spidelay(nsecs) do {} while (0) ++static inline void spidelay(unsigned nsecs) ++{ ++#ifdef NEED_SPIDELAY ++ if (unlikely(nsecs)) ++ ndelay(nsecs); ++#endif /* NEED_SPIDELAY */ ++} + + #include "spi-bitbang-txrx.h" + diff --git a/target/linux/generic/patches-4.0/862-gpio_spi_driver.patch b/target/linux/generic/patches-4.0/862-gpio_spi_driver.patch new file mode 100644 index 0000000..be05938 --- /dev/null +++ b/target/linux/generic/patches-4.0/862-gpio_spi_driver.patch @@ -0,0 +1,373 @@ +THIS CODE IS DEPRECATED. + +Please use the new mainline SPI-GPIO driver, as of 2.6.29. + +--mb + + + +--- + drivers/spi/Kconfig | 9 + + drivers/spi/Makefile | 1 + drivers/spi/spi_gpio_old.c | 251 +++++++++++++++++++++++++++++++++++++++ + include/linux/spi/spi_gpio_old.h | 73 +++++++++++ + 4 files changed, 334 insertions(+) + +--- /dev/null ++++ b/include/linux/spi/spi_gpio_old.h +@@ -0,0 +1,73 @@ ++/* ++ * spi_gpio interface to platform code ++ * ++ * Copyright (c) 2008 Piotr Skamruk ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef _LINUX_SPI_SPI_GPIO ++#define _LINUX_SPI_SPI_GPIO ++ ++#include ++#include ++ ++ ++/** ++ * struct spi_gpio_platform_data - Data definitions for a SPI-GPIO device. ++ * ++ * This structure holds information about a GPIO-based SPI device. ++ * ++ * @pin_clk: The GPIO pin number of the CLOCK pin. ++ * ++ * @pin_miso: The GPIO pin number of the MISO pin. ++ * ++ * @pin_mosi: The GPIO pin number of the MOSI pin. ++ * ++ * @pin_cs: The GPIO pin number of the CHIPSELECT pin. ++ * ++ * @cs_activelow: If true, the chip is selected when the CS line is low. ++ * ++ * @no_spi_delay: If true, no delay is done in the lowlevel bitbanging. ++ * Note that doing no delay is not standards compliant, ++ * but it might be needed to speed up transfers on some ++ * slow embedded machines. ++ * ++ * @boardinfo_setup: This callback is called after the ++ * SPI master device was registered, but before the ++ * device is registered. ++ * @boardinfo_setup_data: Data argument passed to boardinfo_setup(). ++ */ ++struct spi_gpio_platform_data { ++ unsigned int pin_clk; ++ unsigned int pin_miso; ++ unsigned int pin_mosi; ++ unsigned int pin_cs; ++ bool cs_activelow; ++ bool no_spi_delay; ++ int (*boardinfo_setup)(struct spi_board_info *bi, ++ struct spi_master *master, ++ void *data); ++ void *boardinfo_setup_data; ++}; ++ ++/** ++ * SPI_GPIO_PLATDEV_NAME - The platform device name string. ++ * ++ * The name string that has to be used for platform_device_alloc ++ * when allocating a spi-gpio device. ++ */ ++#define SPI_GPIO_PLATDEV_NAME "spi-gpio" ++ ++/** ++ * spi_gpio_next_id - Get another platform device ID number. ++ * ++ * This returns the next platform device ID number that has to be used ++ * for platform_device_alloc. The ID is opaque and should not be used for ++ * anything else. ++ */ ++int spi_gpio_next_id(void); ++ ++#endif /* _LINUX_SPI_SPI_GPIO */ +--- /dev/null ++++ b/drivers/spi/spi_gpio_old.c +@@ -0,0 +1,251 @@ ++/* ++ * Bitbanging SPI bus driver using GPIO API ++ * ++ * Copyright (c) 2008 Piotr Skamruk ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * based on spi_s3c2410_gpio.c ++ * Copyright (c) 2006 Ben Dooks ++ * Copyright (c) 2006 Simtec Electronics ++ * and on i2c-gpio.c ++ * Copyright (C) 2007 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++struct spi_gpio { ++ struct spi_bitbang bitbang; ++ struct spi_gpio_platform_data *info; ++ struct platform_device *pdev; ++ struct spi_board_info bi; ++}; ++ ++ ++static inline struct spi_gpio *spidev_to_sg(struct spi_device *dev) ++{ ++ return dev->controller_data; ++} ++ ++static inline void setsck(struct spi_device *dev, int val) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ gpio_set_value(sp->info->pin_clk, val ? 1 : 0); ++} ++ ++static inline void setmosi(struct spi_device *dev, int val) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ gpio_set_value(sp->info->pin_mosi, val ? 1 : 0); ++} ++ ++static inline u32 getmiso(struct spi_device *dev) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ return gpio_get_value(sp->info->pin_miso) ? 1 : 0; ++} ++ ++static inline void do_spidelay(struct spi_device *dev, unsigned nsecs) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ ++ if (!sp->info->no_spi_delay) ++ ndelay(nsecs); ++} ++ ++#define spidelay(nsecs) do { \ ++ /* Steal the spi_device pointer from our caller. \ ++ * The bitbang-API should probably get fixed here... */ \ ++ do_spidelay(spi, nsecs); \ ++ } while (0) ++ ++#define EXPAND_BITBANG_TXRX ++#include "spi-bitbang-txrx.h" ++ ++static u32 spi_gpio_txrx_mode0(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode1(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode2(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode3(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); ++} ++ ++static void spi_gpio_chipselect(struct spi_device *dev, int on) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ ++ if (sp->info->cs_activelow) ++ on = !on; ++ gpio_set_value(sp->info->pin_cs, on ? 1 : 0); ++} ++ ++static int spi_gpio_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct spi_gpio_platform_data *pdata; ++ struct spi_gpio *sp; ++ struct spi_device *spidev; ++ int err; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -ENXIO; ++ ++ err = -ENOMEM; ++ master = spi_alloc_master(&pdev->dev, sizeof(struct spi_gpio)); ++ if (!master) ++ goto err_alloc_master; ++ ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); ++ sp->info = pdata; ++ ++ err = gpio_request(pdata->pin_clk, "spi_clock"); ++ if (err) ++ goto err_request_clk; ++ err = gpio_request(pdata->pin_mosi, "spi_mosi"); ++ if (err) ++ goto err_request_mosi; ++ err = gpio_request(pdata->pin_miso, "spi_miso"); ++ if (err) ++ goto err_request_miso; ++ err = gpio_request(pdata->pin_cs, "spi_cs"); ++ if (err) ++ goto err_request_cs; ++ ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.master->bus_num = -1; ++ sp->bitbang.master->num_chipselect = 1; ++ sp->bitbang.chipselect = spi_gpio_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_txrx_mode0; ++ sp->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_txrx_mode1; ++ sp->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_txrx_mode2; ++ sp->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_txrx_mode3; ++ ++ gpio_direction_output(pdata->pin_clk, 0); ++ gpio_direction_output(pdata->pin_mosi, 0); ++ gpio_direction_output(pdata->pin_cs, ++ pdata->cs_activelow ? 1 : 0); ++ gpio_direction_input(pdata->pin_miso); ++ ++ err = spi_bitbang_start(&sp->bitbang); ++ if (err) ++ goto err_no_bitbang; ++ err = pdata->boardinfo_setup(&sp->bi, master, ++ pdata->boardinfo_setup_data); ++ if (err) ++ goto err_bi_setup; ++ sp->bi.controller_data = sp; ++ spidev = spi_new_device(master, &sp->bi); ++ if (!spidev) ++ goto err_new_dev; ++ ++ return 0; ++ ++err_new_dev: ++err_bi_setup: ++ spi_bitbang_stop(&sp->bitbang); ++err_no_bitbang: ++ spi_master_put(sp->bitbang.master); ++ gpio_free(pdata->pin_cs); ++err_request_cs: ++ gpio_free(pdata->pin_miso); ++err_request_miso: ++ gpio_free(pdata->pin_mosi); ++err_request_mosi: ++ gpio_free(pdata->pin_clk); ++err_request_clk: ++ kfree(master); ++ ++err_alloc_master: ++ return err; ++} ++ ++static int spi_gpio_remove(struct platform_device *pdev) ++{ ++ struct spi_gpio *sp; ++ struct spi_gpio_platform_data *pdata; ++ ++ pdata = pdev->dev.platform_data; ++ sp = platform_get_drvdata(pdev); ++ ++ gpio_free(pdata->pin_clk); ++ gpio_free(pdata->pin_mosi); ++ gpio_free(pdata->pin_miso); ++ gpio_free(pdata->pin_cs); ++ spi_bitbang_stop(&sp->bitbang); ++ spi_master_put(sp->bitbang.master); ++ ++ return 0; ++} ++ ++static struct platform_driver spi_gpio_driver = { ++ .driver = { ++ .name = SPI_GPIO_PLATDEV_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = spi_gpio_probe, ++ .remove = spi_gpio_remove, ++}; ++ ++int spi_gpio_next_id(void) ++{ ++ static atomic_t counter = ATOMIC_INIT(-1); ++ ++ return atomic_inc_return(&counter); ++} ++EXPORT_SYMBOL(spi_gpio_next_id); ++ ++static int __init spi_gpio_init(void) ++{ ++ int err; ++ ++ err = platform_driver_register(&spi_gpio_driver); ++ if (err) ++ printk(KERN_ERR "spi-gpio: register failed: %d\n", err); ++ ++ return err; ++} ++module_init(spi_gpio_init); ++ ++static void __exit spi_gpio_exit(void) ++{ ++ platform_driver_unregister(&spi_gpio_driver); ++} ++module_exit(spi_gpio_exit); ++ ++MODULE_AUTHOR("Piot Skamruk "); ++MODULE_AUTHOR("Michael Buesch"); ++MODULE_DESCRIPTION("Platform independent GPIO bitbanging SPI driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -242,6 +242,15 @@ config SPI_IMG_SPFI + This enables support for the SPFI master controller found on + IMG SoCs. + ++config SPI_GPIO_OLD ++ tristate "Old GPIO API based bitbanging SPI controller (DEPRECATED)" ++ depends on SPI_MASTER && GPIOLIB ++ select SPI_BITBANG ++ help ++ This code is deprecated. Please use the new mainline SPI-GPIO driver. ++ ++ If unsure, say N. ++ + config SPI_IMX + tristate "Freescale i.MX SPI controllers" + depends on ARCH_MXC || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -41,6 +41,7 @@ obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-li + obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o + obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o + obj-$(CONFIG_SPI_GPIO) += spi-gpio.o ++obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o + obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o + obj-$(CONFIG_SPI_IMX) += spi-imx.o + obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o diff --git a/target/linux/generic/patches-4.0/863-gpiommc.patch b/target/linux/generic/patches-4.0/863-gpiommc.patch new file mode 100644 index 0000000..3433e20 --- /dev/null +++ b/target/linux/generic/patches-4.0/863-gpiommc.patch @@ -0,0 +1,844 @@ +--- /dev/null ++++ b/drivers/mmc/host/gpiommc.c +@@ -0,0 +1,609 @@ ++/* ++ * Driver an MMC/SD card on a bitbanging GPIO SPI bus. ++ * This module hooks up the mmc_spi and spi_gpio modules and also ++ * provides a configfs interface. ++ * ++ * Copyright 2008 Michael Buesch ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#define PFX "gpio-mmc: " ++ ++ ++struct gpiommc_device { ++ struct platform_device *pdev; ++ struct platform_device *spi_pdev; ++ struct spi_board_info boardinfo; ++}; ++ ++ ++MODULE_DESCRIPTION("GPIO based MMC driver"); ++MODULE_AUTHOR("Michael Buesch"); ++MODULE_LICENSE("GPL"); ++ ++ ++static int gpiommc_boardinfo_setup(struct spi_board_info *bi, ++ struct spi_master *master, ++ void *data) ++{ ++ struct gpiommc_device *d = data; ++ struct gpiommc_platform_data *pdata = d->pdev->dev.platform_data; ++ ++ /* Bind the SPI master to the MMC-SPI host driver. */ ++ strlcpy(bi->modalias, "mmc_spi", sizeof(bi->modalias)); ++ ++ bi->max_speed_hz = pdata->max_bus_speed; ++ bi->bus_num = master->bus_num; ++ bi->mode = pdata->mode; ++ ++ return 0; ++} ++ ++static int gpiommc_probe(struct platform_device *pdev) ++{ ++ struct gpiommc_platform_data *mmc_pdata = pdev->dev.platform_data; ++ struct spi_gpio_platform_data spi_pdata; ++ struct gpiommc_device *d; ++ int err; ++ ++ err = -ENXIO; ++ if (!mmc_pdata) ++ goto error; ++ ++#ifdef CONFIG_MMC_SPI_MODULE ++ err = request_module("mmc_spi"); ++ if (err) { ++ printk(KERN_WARNING PFX ++ "Failed to request mmc_spi module.\n"); ++ } ++#endif /* CONFIG_MMC_SPI_MODULE */ ++ ++ /* Allocate the GPIO-MMC device */ ++ err = -ENOMEM; ++ d = kzalloc(sizeof(*d), GFP_KERNEL); ++ if (!d) ++ goto error; ++ d->pdev = pdev; ++ ++ /* Create the SPI-GPIO device */ ++ d->spi_pdev = platform_device_alloc(SPI_GPIO_PLATDEV_NAME, ++ spi_gpio_next_id()); ++ if (!d->spi_pdev) ++ goto err_free_d; ++ ++ memset(&spi_pdata, 0, sizeof(spi_pdata)); ++ spi_pdata.pin_clk = mmc_pdata->pins.gpio_clk; ++ spi_pdata.pin_miso = mmc_pdata->pins.gpio_do; ++ spi_pdata.pin_mosi = mmc_pdata->pins.gpio_di; ++ spi_pdata.pin_cs = mmc_pdata->pins.gpio_cs; ++ spi_pdata.cs_activelow = mmc_pdata->pins.cs_activelow; ++ spi_pdata.no_spi_delay = mmc_pdata->no_spi_delay; ++ spi_pdata.boardinfo_setup = gpiommc_boardinfo_setup; ++ spi_pdata.boardinfo_setup_data = d; ++ ++ err = platform_device_add_data(d->spi_pdev, &spi_pdata, ++ sizeof(spi_pdata)); ++ if (err) ++ goto err_free_pdev; ++ err = platform_device_add(d->spi_pdev); ++ if (err) ++ goto err_free_pdata; ++ platform_set_drvdata(pdev, d); ++ ++ printk(KERN_INFO PFX "MMC-Card \"%s\" " ++ "attached to GPIO pins di=%u, do=%u, clk=%u, cs=%u\n", ++ mmc_pdata->name, mmc_pdata->pins.gpio_di, ++ mmc_pdata->pins.gpio_do, ++ mmc_pdata->pins.gpio_clk, ++ mmc_pdata->pins.gpio_cs); ++ ++ return 0; ++ ++err_free_pdata: ++ kfree(d->spi_pdev->dev.platform_data); ++ d->spi_pdev->dev.platform_data = NULL; ++err_free_pdev: ++ platform_device_put(d->spi_pdev); ++err_free_d: ++ kfree(d); ++error: ++ return err; ++} ++ ++static int gpiommc_remove(struct platform_device *pdev) ++{ ++ struct gpiommc_device *d = platform_get_drvdata(pdev); ++ struct gpiommc_platform_data *pdata = d->pdev->dev.platform_data; ++ ++ platform_device_unregister(d->spi_pdev); ++ printk(KERN_INFO PFX "GPIO based MMC-Card \"%s\" removed\n", ++ pdata->name); ++ platform_device_put(d->spi_pdev); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ ++/* A device that was created through configfs */ ++struct gpiommc_configfs_device { ++ struct config_item item; ++ /* The platform device, after registration. */ ++ struct platform_device *pdev; ++ /* The configuration */ ++ struct gpiommc_platform_data pdata; ++}; ++ ++#define GPIO_INVALID -1 ++ ++static inline bool gpiommc_is_registered(struct gpiommc_configfs_device *dev) ++{ ++ return (dev->pdev != NULL); ++} ++ ++static inline struct gpiommc_configfs_device *ci_to_gpiommc(struct config_item *item) ++{ ++ return item ? container_of(item, struct gpiommc_configfs_device, item) : NULL; ++} ++ ++static struct configfs_attribute gpiommc_attr_DI = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_data_in", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_DO = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_data_out", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CLK = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_clock", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CS = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_chipselect", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CS_activelow = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_chipselect_activelow", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_spimode = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "spi_mode", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_spidelay = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "spi_delay", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_max_bus_speed = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "max_bus_speed", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_register = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "register", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute *gpiommc_config_attrs[] = { ++ &gpiommc_attr_DI, ++ &gpiommc_attr_DO, ++ &gpiommc_attr_CLK, ++ &gpiommc_attr_CS, ++ &gpiommc_attr_CS_activelow, ++ &gpiommc_attr_spimode, ++ &gpiommc_attr_spidelay, ++ &gpiommc_attr_max_bus_speed, ++ &gpiommc_attr_register, ++ NULL, ++}; ++ ++static ssize_t gpiommc_config_attr_show(struct config_item *item, ++ struct configfs_attribute *attr, ++ char *page) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ssize_t count = 0; ++ unsigned int gpio; ++ int err = 0; ++ ++ if (attr == &gpiommc_attr_DI) { ++ gpio = dev->pdata.pins.gpio_di; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_DO) { ++ gpio = dev->pdata.pins.gpio_do; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CLK) { ++ gpio = dev->pdata.pins.gpio_clk; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS) { ++ gpio = dev->pdata.pins.gpio_cs; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS_activelow) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.pins.cs_activelow); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spimode) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.mode); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spidelay) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ !dev->pdata.no_spi_delay); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_max_bus_speed) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.max_bus_speed); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_register) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ gpiommc_is_registered(dev)); ++ goto out; ++ } ++ WARN_ON(1); ++ err = -ENOSYS; ++out: ++ return err ? err : count; ++} ++ ++static int gpiommc_do_register(struct gpiommc_configfs_device *dev, ++ const char *name) ++{ ++ int err; ++ ++ if (gpiommc_is_registered(dev)) ++ return 0; ++ ++ if (!gpio_is_valid(dev->pdata.pins.gpio_di) || ++ !gpio_is_valid(dev->pdata.pins.gpio_do) || ++ !gpio_is_valid(dev->pdata.pins.gpio_clk) || ++ !gpio_is_valid(dev->pdata.pins.gpio_cs)) { ++ printk(KERN_ERR PFX ++ "configfs: Invalid GPIO pin number(s)\n"); ++ return -EINVAL; ++ } ++ ++ strlcpy(dev->pdata.name, name, ++ sizeof(dev->pdata.name)); ++ ++ dev->pdev = platform_device_alloc(GPIOMMC_PLATDEV_NAME, ++ gpiommc_next_id()); ++ if (!dev->pdev) ++ return -ENOMEM; ++ err = platform_device_add_data(dev->pdev, &dev->pdata, ++ sizeof(dev->pdata)); ++ if (err) { ++ platform_device_put(dev->pdev); ++ return err; ++ } ++ err = platform_device_add(dev->pdev); ++ if (err) { ++ platform_device_put(dev->pdev); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void gpiommc_do_unregister(struct gpiommc_configfs_device *dev) ++{ ++ if (!gpiommc_is_registered(dev)) ++ return; ++ ++ platform_device_unregister(dev->pdev); ++ dev->pdev = NULL; ++} ++ ++static ssize_t gpiommc_config_attr_store(struct config_item *item, ++ struct configfs_attribute *attr, ++ const char *page, size_t count) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ int err = -EINVAL; ++ unsigned long data; ++ ++ if (attr == &gpiommc_attr_register) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data == 1) ++ err = gpiommc_do_register(dev, item->ci_name); ++ if (data == 0) { ++ gpiommc_do_unregister(dev); ++ err = 0; ++ } ++ goto out; ++ } ++ ++ if (gpiommc_is_registered(dev)) { ++ /* The rest of the config parameters can only be set ++ * as long as the device is not registered, yet. */ ++ err = -EBUSY; ++ goto out; ++ } ++ ++ if (attr == &gpiommc_attr_DI) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_di = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_DO) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_do = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CLK) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_clk = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_cs = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS_activelow) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data != 0 && data != 1) ++ goto out; ++ dev->pdata.pins.cs_activelow = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spimode) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ switch (data) { ++ case 0: ++ dev->pdata.mode = SPI_MODE_0; ++ break; ++ case 1: ++ dev->pdata.mode = SPI_MODE_1; ++ break; ++ case 2: ++ dev->pdata.mode = SPI_MODE_2; ++ break; ++ case 3: ++ dev->pdata.mode = SPI_MODE_3; ++ break; ++ default: ++ goto out; ++ } ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spidelay) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data != 0 && data != 1) ++ goto out; ++ dev->pdata.no_spi_delay = !data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_max_bus_speed) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data > UINT_MAX) ++ goto out; ++ dev->pdata.max_bus_speed = data; ++ err = 0; ++ goto out; ++ } ++ WARN_ON(1); ++ err = -ENOSYS; ++out: ++ return err ? err : count; ++} ++ ++static void gpiommc_config_item_release(struct config_item *item) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ++ kfree(dev); ++} ++ ++static struct configfs_item_operations gpiommc_config_item_ops = { ++ .release = gpiommc_config_item_release, ++ .show_attribute = gpiommc_config_attr_show, ++ .store_attribute = gpiommc_config_attr_store, ++}; ++ ++static struct config_item_type gpiommc_dev_ci_type = { ++ .ct_item_ops = &gpiommc_config_item_ops, ++ .ct_attrs = gpiommc_config_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *gpiommc_make_item(struct config_group *group, ++ const char *name) ++{ ++ struct gpiommc_configfs_device *dev; ++ ++ if (strlen(name) > GPIOMMC_MAX_NAMELEN) { ++ printk(KERN_ERR PFX "configfs: device name too long\n"); ++ return NULL; ++ } ++ ++ dev = kzalloc(sizeof(*dev), GFP_KERNEL); ++ if (!dev) ++ return NULL; ++ ++ config_item_init_type_name(&dev->item, name, ++ &gpiommc_dev_ci_type); ++ ++ /* Assign default configuration */ ++ dev->pdata.pins.gpio_di = GPIO_INVALID; ++ dev->pdata.pins.gpio_do = GPIO_INVALID; ++ dev->pdata.pins.gpio_clk = GPIO_INVALID; ++ dev->pdata.pins.gpio_cs = GPIO_INVALID; ++ dev->pdata.pins.cs_activelow = 1; ++ dev->pdata.mode = SPI_MODE_0; ++ dev->pdata.no_spi_delay = 0; ++ dev->pdata.max_bus_speed = 5000000; /* 5 MHz */ ++ ++ return &(dev->item); ++} ++ ++static void gpiommc_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ++ gpiommc_do_unregister(dev); ++ kfree(dev); ++} ++ ++static struct configfs_group_operations gpiommc_ct_group_ops = { ++ .make_item = gpiommc_make_item, ++ .drop_item = gpiommc_drop_item, ++}; ++ ++static struct config_item_type gpiommc_ci_type = { ++ .ct_group_ops = &gpiommc_ct_group_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_subsystem gpiommc_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = GPIOMMC_PLATDEV_NAME, ++ .ci_type = &gpiommc_ci_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(gpiommc_subsys.su_mutex), ++}; ++ ++#endif /* CONFIG_GPIOMMC_CONFIGFS */ ++ ++static struct platform_driver gpiommc_plat_driver = { ++ .probe = gpiommc_probe, ++ .remove = gpiommc_remove, ++ .driver = { ++ .name = GPIOMMC_PLATDEV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int gpiommc_next_id(void) ++{ ++ static atomic_t counter = ATOMIC_INIT(-1); ++ ++ return atomic_inc_return(&counter); ++} ++EXPORT_SYMBOL(gpiommc_next_id); ++ ++static int __init gpiommc_modinit(void) ++{ ++ int err; ++ ++ err = platform_driver_register(&gpiommc_plat_driver); ++ if (err) ++ return err; ++ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ config_group_init(&gpiommc_subsys.su_group); ++ err = configfs_register_subsystem(&gpiommc_subsys); ++ if (err) { ++ platform_driver_unregister(&gpiommc_plat_driver); ++ return err; ++ } ++#endif /* CONFIG_GPIOMMC_CONFIGFS */ ++ ++ return 0; ++} ++module_init(gpiommc_modinit); ++ ++static void __exit gpiommc_modexit(void) ++{ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ configfs_unregister_subsystem(&gpiommc_subsys); ++#endif ++ platform_driver_unregister(&gpiommc_plat_driver); ++} ++module_exit(gpiommc_modexit); +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -549,6 +549,31 @@ config MMC_SDHI + This provides support for the SDHI SD/SDIO controller found in + SuperH and ARM SH-Mobile SoCs + ++config GPIOMMC ++ tristate "MMC/SD over GPIO-based SPI" ++ depends on MMC && MMC_SPI && SPI_GPIO_OLD ++ help ++ This driver hooks up the mmc_spi and spi_gpio modules so that ++ MMC/SD cards can be used on a GPIO based bus by bitbanging ++ the SPI protocol in software. ++ ++ This driver provides a configfs interface to dynamically create ++ and destroy GPIO-based MMC/SD card devices. It also provides ++ a platform device interface API. ++ See Documentation/gpiommc.txt for details. ++ ++ The module will be called gpiommc. ++ ++ If unsure, say N. ++ ++config GPIOMMC_CONFIGFS ++ bool ++ depends on GPIOMMC && CONFIGFS_FS ++ default y ++ help ++ This option automatically enables configfs support for gpiommc ++ if configfs is available. ++ + config MMC_CB710 + tristate "ENE CB710 MMC/SD Interface support" + depends on PCI +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -41,6 +41,7 @@ tmio_mmc_core-$(subst m,y,$(CONFIG_MMC_S + obj-$(CONFIG_MMC_SDHI) += sh_mobile_sdhi.o + obj-$(CONFIG_MMC_CB710) += cb710-mmc.o + obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o ++obj-$(CONFIG_GPIOMMC) += gpiommc.o + obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o + obj-$(CONFIG_MMC_DW) += dw_mmc.o + obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o +--- /dev/null ++++ b/include/linux/mmc/gpiommc.h +@@ -0,0 +1,71 @@ ++/* ++ * Device driver for MMC/SD cards driven over a GPIO bus. ++ * ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * Licensed under the GNU/GPL version 2. ++ */ ++#ifndef LINUX_GPIOMMC_H_ ++#define LINUX_GPIOMMC_H_ ++ ++#include ++ ++ ++#define GPIOMMC_MAX_NAMELEN 15 ++#define GPIOMMC_MAX_NAMELEN_STR __stringify(GPIOMMC_MAX_NAMELEN) ++ ++/** ++ * struct gpiommc_pins - Hardware pin assignments ++ * ++ * @gpio_di: The GPIO number of the DATA IN pin ++ * @gpio_do: The GPIO number of the DATA OUT pin ++ * @gpio_clk: The GPIO number of the CLOCK pin ++ * @gpio_cs: The GPIO number of the CHIPSELECT pin ++ * @cs_activelow: If true, the chip is considered selected if @gpio_cs is low. ++ */ ++struct gpiommc_pins { ++ unsigned int gpio_di; ++ unsigned int gpio_do; ++ unsigned int gpio_clk; ++ unsigned int gpio_cs; ++ bool cs_activelow; ++}; ++ ++/** ++ * struct gpiommc_platform_data - Platform data for a MMC-over-SPI-GPIO device. ++ * ++ * @name: The unique name string of the device. ++ * @pins: The hardware pin assignments. ++ * @mode: The hardware mode. This is either SPI_MODE_0, ++ * SPI_MODE_1, SPI_MODE_2 or SPI_MODE_3. See the SPI documentation. ++ * @no_spi_delay: Do not use delays in the lowlevel SPI bitbanging code. ++ * This is not standards compliant, but may be required for some ++ * embedded machines to gain reasonable speed. ++ * @max_bus_speed: The maximum speed of the SPI bus, in Hertz. ++ */ ++struct gpiommc_platform_data { ++ char name[GPIOMMC_MAX_NAMELEN + 1]; ++ struct gpiommc_pins pins; ++ u8 mode; ++ bool no_spi_delay; ++ unsigned int max_bus_speed; ++}; ++ ++/** ++ * GPIOMMC_PLATDEV_NAME - The platform device name string. ++ * ++ * The name string that has to be used for platform_device_alloc ++ * when allocating a gpiommc device. ++ */ ++#define GPIOMMC_PLATDEV_NAME "gpiommc" ++ ++/** ++ * gpiommc_next_id - Get another platform device ID number. ++ * ++ * This returns the next platform device ID number that has to be used ++ * for platform_device_alloc. The ID is opaque and should not be used for ++ * anything else. ++ */ ++int gpiommc_next_id(void); ++ ++#endif /* LINUX_GPIOMMC_H_ */ +--- /dev/null ++++ b/Documentation/gpiommc.txt +@@ -0,0 +1,97 @@ ++GPIOMMC - Driver for an MMC/SD card on a bitbanging GPIO SPI bus ++================================================================ ++ ++The gpiommc module hooks up the mmc_spi and spi_gpio modules for running an ++MMC or SD card on GPIO pins. ++ ++Two interfaces for registering a new MMC/SD card device are provided: ++A static platform-device based mechanism and a dynamic configfs based interface. ++ ++ ++Registering devices via platform-device ++======================================= ++ ++The platform-device interface is used for registering MMC/SD devices that are ++part of the hardware platform. This is most useful only for embedded machines ++with MMC/SD devices statically connected to the platform GPIO bus. ++ ++The data structures are declared in . ++ ++To register a new device, define an instance of struct gpiommc_platform_data. ++This structure holds any information about how the device is hooked up to the ++GPIO pins and what hardware modes the device supports. See the docbook-style ++documentation in the header file for more information on the struct fields. ++ ++Then allocate a new instance of a platform device by doing: ++ ++ pdev = platform_device_alloc(GPIOMMC_PLATDEV_NAME, gpiommc_next_id()); ++ ++This will allocate the platform device data structures and hook it up to the ++gpiommc driver. ++Then add the gpiommc_platform_data to the platform device. ++ ++ err = platform_device_add_data(pdev, pdata, sizeof(struct gpiommc_platform_data)); ++ ++You may free the local instance of struct gpiommc_platform_data now. (So the ++struct may be allocated on the stack, too). ++Now simply register the platform device. ++ ++ err = platform_device_add(pdev); ++ ++Done. The gpiommc probe routine will be invoked now and you should see a kernel ++log message for the added device. ++ ++ ++Registering devices via configfs ++================================ ++ ++MMC/SD cards connected via GPIO often are a pretty dynamic thing, as for example ++selfmade hacks for soldering an MMC/SD card to standard GPIO pins on embedded ++hardware are a common situation. ++So we provide a dynamic interface to conveniently handle adding and removing ++devices from userspace, without the need to recompile the kernel. ++ ++The "gpiommc" subdirectory at the configfs mountpoint is used for handling ++the dynamic configuration. ++ ++To create a new device, it must first be allocated with mkdir. ++The following command will allocate a device named "my_mmc": ++ mkdir /config/gpiommc/my_mmc ++ ++There are several configuration files available in the new ++/config/gpiommc/my_mmc/ directory: ++ ++gpio_data_in = The SPI data-IN GPIO pin number. ++gpio_data_out = The SPI data-OUT GPIO pin number. ++gpio_clock = The SPI Clock GPIO pin number. ++gpio_chipselect = The SPI Chipselect GPIO pin number. ++gpio_chipselect_activelow = Boolean. If 0, Chipselect is active-HIGH. ++ If 1, Chipselect is active-LOW. ++spi_mode = The SPI data mode. Can be 0-3. ++spi_delay = Enable all delays in the lowlevel bitbanging. ++max_bus_speed = The maximum SPI bus speed. In Hertz. ++ ++register = Not a configuration parameter. ++ Used to register the configured card ++ with the kernel. ++ ++The device must first get configured and then registered by writing "1" to ++the "register" file. ++The configuration parameters "gpio_data_in", "gpio_data_out", "gpio_clock" ++and "gpio_chipselect" are essential and _must_ be configured before writing ++"1" to the "register" file. The registration will fail, otherwise. ++ ++The default values for the other parameters are: ++gpio_chipselect_activelow = 1 (CS active-LOW) ++spi_mode = 0 (SPI_MODE_0) ++spi_delay = 1 (enabled) ++max_bus_speed = 5000000 (5 Mhz) ++ ++Configuration values can not be changed after registration. To unregister ++the device, write a "0" to the "register" file. The configuration can be ++changed again after unregistering. ++ ++To completely remove the device, simply rmdir the directory ++(/config/gpiommc/my_mmc in this example). ++There's no need to first unregister the device before removing it. That will ++be done automatically. +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -4481,6 +4481,11 @@ T: git git://linuxtv.org/anttip/media_tr + S: Maintained + F: drivers/media/usb/hackrf/ + ++GPIOMMC DRIVER ++P: Michael Buesch ++M: mb@bu3sch.de ++S: Maintained ++ + HARDWARE MONITORING + M: Jean Delvare + M: Guenter Roeck diff --git a/target/linux/generic/patches-4.0/864-gpiommc_configfs_locking.patch b/target/linux/generic/patches-4.0/864-gpiommc_configfs_locking.patch new file mode 100644 index 0000000..92815d9 --- /dev/null +++ b/target/linux/generic/patches-4.0/864-gpiommc_configfs_locking.patch @@ -0,0 +1,58 @@ +The gpiommc configfs context structure needs locking, as configfs +does not lock access between files. + +--- a/drivers/mmc/host/gpiommc.c ++++ b/drivers/mmc/host/gpiommc.c +@@ -144,6 +144,8 @@ struct gpiommc_configfs_device { + struct platform_device *pdev; + /* The configuration */ + struct gpiommc_platform_data pdata; ++ /* Mutex to protect this structure */ ++ struct mutex mutex; + }; + + #define GPIO_INVALID -1 +@@ -234,6 +236,8 @@ static ssize_t gpiommc_config_attr_show( + unsigned int gpio; + int err = 0; + ++ mutex_lock(&dev->mutex); ++ + if (attr == &gpiommc_attr_DI) { + gpio = dev->pdata.pins.gpio_di; + if (gpio == GPIO_INVALID) +@@ -294,6 +298,8 @@ static ssize_t gpiommc_config_attr_show( + WARN_ON(1); + err = -ENOSYS; + out: ++ mutex_unlock(&dev->mutex); ++ + return err ? err : count; + } + +@@ -353,6 +359,8 @@ static ssize_t gpiommc_config_attr_store + int err = -EINVAL; + unsigned long data; + ++ mutex_lock(&dev->mutex); ++ + if (attr == &gpiommc_attr_register) { + err = kstrtoul(page, 10, &data); + if (err) +@@ -478,6 +486,8 @@ static ssize_t gpiommc_config_attr_store + WARN_ON(1); + err = -ENOSYS; + out: ++ mutex_unlock(&dev->mutex); ++ + return err ? err : count; + } + +@@ -514,6 +524,7 @@ static struct config_item *gpiommc_make_ + if (!dev) + return NULL; + ++ mutex_init(&dev->mutex); + config_item_init_type_name(&dev->item, name, + &gpiommc_dev_ci_type); + diff --git a/target/linux/generic/patches-4.0/870-hifn795x_byteswap.patch b/target/linux/generic/patches-4.0/870-hifn795x_byteswap.patch new file mode 100644 index 0000000..3a37c95 --- /dev/null +++ b/target/linux/generic/patches-4.0/870-hifn795x_byteswap.patch @@ -0,0 +1,17 @@ +--- a/drivers/crypto/hifn_795x.c ++++ b/drivers/crypto/hifn_795x.c +@@ -682,12 +682,12 @@ static inline u32 hifn_read_1(struct hif + + static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) + { +- writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); ++ writel(val, dev->bar[0] + reg); + } + + static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) + { +- writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); ++ writel(val, dev->bar[1] + reg); + } + + static void hifn_wait_puc(struct hifn_device *dev) diff --git a/target/linux/generic/patches-4.0/880-gateworks_system_controller.patch b/target/linux/generic/patches-4.0/880-gateworks_system_controller.patch new file mode 100644 index 0000000..32796d5 --- /dev/null +++ b/target/linux/generic/patches-4.0/880-gateworks_system_controller.patch @@ -0,0 +1,339 @@ +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -507,6 +507,15 @@ config SENSORS_G762 + This driver can also be built as a module. If so, the module + will be called g762. + ++config SENSORS_GSC ++ tristate "Gateworks System Controller" ++ depends on I2C ++ help ++ If you say yes here you get support for the Gateworks System Controller. ++ ++ This driver can also be built as a module. If so, the module ++ will be called gsc. ++ + config SENSORS_GPIO_FAN + tristate "GPIO fan" + depends on GPIOLIB +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -155,6 +155,7 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l7 + obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o + obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o + obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o ++obj-$(CONFIG_SENSORS_GSC) += gsc.o + + obj-$(CONFIG_PMBUS) += pmbus/ + +--- /dev/null ++++ b/drivers/hwmon/gsc.c +@@ -0,0 +1,308 @@ ++/* ++ * A hwmon driver for the Gateworks System Controller ++ * Copyright (C) 2009 Gateworks Corporation ++ * ++ * Author: Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License, ++ * as published by the Free Software Foundation - version 2. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRV_VERSION "0.2" ++ ++enum chips { gsp }; ++ ++/* AD7418 registers */ ++#define GSP_REG_TEMP_IN 0x00 ++#define GSP_REG_VIN 0x02 ++#define GSP_REG_3P3 0x05 ++#define GSP_REG_BAT 0x08 ++#define GSP_REG_5P0 0x0b ++#define GSP_REG_CORE 0x0e ++#define GSP_REG_CPU1 0x11 ++#define GSP_REG_CPU2 0x14 ++#define GSP_REG_DRAM 0x17 ++#define GSP_REG_EXT_BAT 0x1a ++#define GSP_REG_IO1 0x1d ++#define GSP_REG_IO2 0x20 ++#define GSP_REG_PCIE 0x23 ++#define GSP_REG_CURRENT 0x26 ++#define GSP_FAN_0 0x2C ++#define GSP_FAN_1 0x2E ++#define GSP_FAN_2 0x30 ++#define GSP_FAN_3 0x32 ++#define GSP_FAN_4 0x34 ++#define GSP_FAN_5 0x36 ++ ++struct gsp_sensor_info { ++ const char* name; ++ int reg; ++}; ++ ++static const struct gsp_sensor_info gsp_sensors[] = { ++ {"temp", GSP_REG_TEMP_IN}, ++ {"vin", GSP_REG_VIN}, ++ {"3p3", GSP_REG_3P3}, ++ {"bat", GSP_REG_BAT}, ++ {"5p0", GSP_REG_5P0}, ++ {"core", GSP_REG_CORE}, ++ {"cpu1", GSP_REG_CPU1}, ++ {"cpu2", GSP_REG_CPU2}, ++ {"dram", GSP_REG_DRAM}, ++ {"ext_bat", GSP_REG_EXT_BAT}, ++ {"io1", GSP_REG_IO1}, ++ {"io2", GSP_REG_IO2}, ++ {"pci2", GSP_REG_PCIE}, ++ {"current", GSP_REG_CURRENT}, ++ {"fan_point0", GSP_FAN_0}, ++ {"fan_point1", GSP_FAN_1}, ++ {"fan_point2", GSP_FAN_2}, ++ {"fan_point3", GSP_FAN_3}, ++ {"fan_point4", GSP_FAN_4}, ++ {"fan_point5", GSP_FAN_5}, ++}; ++ ++struct gsp_data { ++ struct device *hwmon_dev; ++ struct attribute_group attrs; ++ enum chips type; ++}; ++ ++static int gsp_probe(struct i2c_client *client, ++ const struct i2c_device_id *id); ++static int gsp_remove(struct i2c_client *client); ++ ++static const struct i2c_device_id gsp_id[] = { ++ { "gsp", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, gsp_id); ++ ++static struct i2c_driver gsp_driver = { ++ .driver = { ++ .name = "gsp", ++ }, ++ .probe = gsp_probe, ++ .remove = gsp_remove, ++ .id_table = gsp_id, ++}; ++ ++/* All registers are word-sized, except for the configuration registers. ++ * AD7418 uses a high-byte first convention. Do NOT use those functions to ++ * access the configuration registers CONF and CONF2, as they are byte-sized. ++ */ ++static inline int gsp_read(struct i2c_client *client, u8 reg) ++{ ++ unsigned int adc = 0; ++ if (reg == GSP_REG_TEMP_IN || reg > GSP_REG_CURRENT) ++ { ++ adc |= i2c_smbus_read_byte_data(client, reg); ++ adc |= i2c_smbus_read_byte_data(client, reg + 1) << 8; ++ return adc; ++ } ++ else ++ { ++ adc |= i2c_smbus_read_byte_data(client, reg); ++ adc |= i2c_smbus_read_byte_data(client, reg + 1) << 8; ++ adc |= i2c_smbus_read_byte_data(client, reg + 2) << 16; ++ return adc; ++ } ++} ++ ++static inline int gsp_write(struct i2c_client *client, u8 reg, u16 value) ++{ ++ i2c_smbus_write_byte_data(client, reg, value & 0xff); ++ i2c_smbus_write_byte_data(client, reg + 1, ((value >> 8) & 0xff)); ++ return 1; ++} ++ ++static ssize_t show_adc(struct device *dev, struct device_attribute *devattr, ++ char *buf) ++{ ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ struct i2c_client *client = to_i2c_client(dev); ++ return sprintf(buf, "%d\n", gsp_read(client, gsp_sensors[attr->index].reg)); ++} ++ ++static ssize_t show_label(struct device *dev, ++ struct device_attribute *devattr, char *buf) ++{ ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ ++ return sprintf(buf, "%s\n", gsp_sensors[attr->index].name); ++} ++ ++static ssize_t store_fan(struct device *dev, ++ struct device_attribute *devattr, const char *buf, size_t count) ++{ ++ u16 val; ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ struct i2c_client *client = to_i2c_client(dev); ++ val = simple_strtoul(buf, NULL, 10); ++ gsp_write(client, gsp_sensors[attr->index].reg, val); ++ return count; ++} ++ ++static SENSOR_DEVICE_ATTR(temp0_input, S_IRUGO, show_adc, NULL, 0); ++static SENSOR_DEVICE_ATTR(temp0_label, S_IRUGO, show_label, NULL, 0); ++ ++static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, show_adc, NULL, 1); ++static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, show_label, NULL, 1); ++static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, show_adc, NULL, 2); ++static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, show_label, NULL, 2); ++static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, show_adc, NULL, 3); ++static SENSOR_DEVICE_ATTR(in2_label, S_IRUGO, show_label, NULL, 3); ++static SENSOR_DEVICE_ATTR(in3_input, S_IRUGO, show_adc, NULL, 4); ++static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 4); ++static SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, show_adc, NULL, 5); ++static SENSOR_DEVICE_ATTR(in4_label, S_IRUGO, show_label, NULL, 5); ++static SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, show_adc, NULL, 6); ++static SENSOR_DEVICE_ATTR(in5_label, S_IRUGO, show_label, NULL, 6); ++static SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, show_adc, NULL, 7); ++static SENSOR_DEVICE_ATTR(in6_label, S_IRUGO, show_label, NULL, 7); ++static SENSOR_DEVICE_ATTR(in7_input, S_IRUGO, show_adc, NULL, 8); ++static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 8); ++static SENSOR_DEVICE_ATTR(in8_input, S_IRUGO, show_adc, NULL, 9); ++static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 9); ++static SENSOR_DEVICE_ATTR(in9_input, S_IRUGO, show_adc, NULL, 10); ++static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 10); ++static SENSOR_DEVICE_ATTR(in10_input, S_IRUGO, show_adc, NULL, 11); ++static SENSOR_DEVICE_ATTR(in10_label, S_IRUGO, show_label, NULL, 11); ++static SENSOR_DEVICE_ATTR(in11_input, S_IRUGO, show_adc, NULL, 12); ++static SENSOR_DEVICE_ATTR(in11_label, S_IRUGO, show_label, NULL, 12); ++static SENSOR_DEVICE_ATTR(in12_input, S_IRUGO, show_adc, NULL, 13); ++static SENSOR_DEVICE_ATTR(in12_label, S_IRUGO, show_label, NULL, 13); ++ ++static SENSOR_DEVICE_ATTR(fan0_point0, S_IRUGO | S_IWUSR, show_adc, store_fan, 14); ++static SENSOR_DEVICE_ATTR(fan0_point1, S_IRUGO | S_IWUSR, show_adc, store_fan, 15); ++static SENSOR_DEVICE_ATTR(fan0_point2, S_IRUGO | S_IWUSR, show_adc, store_fan, 16); ++static SENSOR_DEVICE_ATTR(fan0_point3, S_IRUGO | S_IWUSR, show_adc, store_fan, 17); ++static SENSOR_DEVICE_ATTR(fan0_point4, S_IRUGO | S_IWUSR, show_adc, store_fan, 18); ++static SENSOR_DEVICE_ATTR(fan0_point5, S_IRUGO | S_IWUSR, show_adc, store_fan, 19); ++ ++static struct attribute *gsp_attributes[] = { ++ &sensor_dev_attr_temp0_input.dev_attr.attr, ++ &sensor_dev_attr_in0_input.dev_attr.attr, ++ &sensor_dev_attr_in1_input.dev_attr.attr, ++ &sensor_dev_attr_in2_input.dev_attr.attr, ++ &sensor_dev_attr_in3_input.dev_attr.attr, ++ &sensor_dev_attr_in4_input.dev_attr.attr, ++ &sensor_dev_attr_in5_input.dev_attr.attr, ++ &sensor_dev_attr_in6_input.dev_attr.attr, ++ &sensor_dev_attr_in7_input.dev_attr.attr, ++ &sensor_dev_attr_in8_input.dev_attr.attr, ++ &sensor_dev_attr_in9_input.dev_attr.attr, ++ &sensor_dev_attr_in10_input.dev_attr.attr, ++ &sensor_dev_attr_in11_input.dev_attr.attr, ++ &sensor_dev_attr_in12_input.dev_attr.attr, ++ ++ &sensor_dev_attr_temp0_label.dev_attr.attr, ++ &sensor_dev_attr_in0_label.dev_attr.attr, ++ &sensor_dev_attr_in1_label.dev_attr.attr, ++ &sensor_dev_attr_in2_label.dev_attr.attr, ++ &sensor_dev_attr_in3_label.dev_attr.attr, ++ &sensor_dev_attr_in4_label.dev_attr.attr, ++ &sensor_dev_attr_in5_label.dev_attr.attr, ++ &sensor_dev_attr_in6_label.dev_attr.attr, ++ &sensor_dev_attr_in7_label.dev_attr.attr, ++ &sensor_dev_attr_in8_label.dev_attr.attr, ++ &sensor_dev_attr_in9_label.dev_attr.attr, ++ &sensor_dev_attr_in10_label.dev_attr.attr, ++ &sensor_dev_attr_in11_label.dev_attr.attr, ++ &sensor_dev_attr_in12_label.dev_attr.attr, ++ ++ &sensor_dev_attr_fan0_point0.dev_attr.attr, ++ &sensor_dev_attr_fan0_point1.dev_attr.attr, ++ &sensor_dev_attr_fan0_point2.dev_attr.attr, ++ &sensor_dev_attr_fan0_point3.dev_attr.attr, ++ &sensor_dev_attr_fan0_point4.dev_attr.attr, ++ &sensor_dev_attr_fan0_point5.dev_attr.attr, ++ NULL ++}; ++ ++ ++static int gsp_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct i2c_adapter *adapter = client->adapter; ++ struct gsp_data *data; ++ int err; ++ ++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | ++ I2C_FUNC_SMBUS_WORD_DATA)) { ++ err = -EOPNOTSUPP; ++ goto exit; ++ } ++ ++ if (!(data = kzalloc(sizeof(struct gsp_data), GFP_KERNEL))) { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ++ i2c_set_clientdata(client, data); ++ ++ data->type = id->driver_data; ++ ++ switch (data->type) { ++ case 0: ++ data->attrs.attrs = gsp_attributes; ++ break; ++ } ++ ++ dev_info(&client->dev, "%s chip found\n", client->name); ++ ++ /* Register sysfs hooks */ ++ if ((err = sysfs_create_group(&client->dev.kobj, &data->attrs))) ++ goto exit_free; ++ ++ data->hwmon_dev = hwmon_device_register(&client->dev); ++ if (IS_ERR(data->hwmon_dev)) { ++ err = PTR_ERR(data->hwmon_dev); ++ goto exit_remove; ++ } ++ ++ return 0; ++ ++exit_remove: ++ sysfs_remove_group(&client->dev.kobj, &data->attrs); ++exit_free: ++ kfree(data); ++exit: ++ return err; ++} ++ ++static int gsp_remove(struct i2c_client *client) ++{ ++ struct gsp_data *data = i2c_get_clientdata(client); ++ hwmon_device_unregister(data->hwmon_dev); ++ sysfs_remove_group(&client->dev.kobj, &data->attrs); ++ kfree(data); ++ return 0; ++} ++ ++static int __init gsp_init(void) ++{ ++ return i2c_add_driver(&gsp_driver); ++} ++ ++static void __exit gsp_exit(void) ++{ ++ i2c_del_driver(&gsp_driver); ++} ++ ++module_init(gsp_init); ++module_exit(gsp_exit); ++ ++MODULE_AUTHOR("Chris Lang "); ++MODULE_DESCRIPTION("GSC HWMON driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); ++ diff --git a/target/linux/generic/patches-4.0/890-8250_optional_sysrq.patch b/target/linux/generic/patches-4.0/890-8250_optional_sysrq.patch new file mode 100644 index 0000000..8815e4c --- /dev/null +++ b/target/linux/generic/patches-4.0/890-8250_optional_sysrq.patch @@ -0,0 +1,24 @@ +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -16,7 +16,7 @@ + * membase is an 'ioremapped' cookie. + */ + +-#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) ++#if defined(CONFIG_SERIAL_8250_SYSRQ) && defined(CONFIG_MAGIC_SYSRQ) + #define SUPPORT_SYSRQ + #endif + +--- a/drivers/tty/serial/8250/Kconfig ++++ b/drivers/tty/serial/8250/Kconfig +@@ -91,6 +91,10 @@ config SERIAL_8250_CONSOLE + + If unsure, say N. + ++config SERIAL_8250_SYSRQ ++ bool "Magic sysrq support on 8250/16550 devices" ++ depends on SERIAL_8250_CONSOLE ++ + config SERIAL_8250_GSC + tristate + depends on SERIAL_8250 && GSC diff --git a/target/linux/generic/patches-4.0/900-slab_maxsize.patch b/target/linux/generic/patches-4.0/900-slab_maxsize.patch new file mode 100644 index 0000000..10133f2 --- /dev/null +++ b/target/linux/generic/patches-4.0/900-slab_maxsize.patch @@ -0,0 +1,13 @@ +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -171,8 +171,8 @@ size_t ksize(const void *); + * to do various tricks to work around compiler limitations in order to + * ensure proper constant folding. + */ +-#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 25 ? \ +- (MAX_ORDER + PAGE_SHIFT - 1) : 25) ++#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 17 ? \ ++ (MAX_ORDER + PAGE_SHIFT - 1) : 17) + #define KMALLOC_SHIFT_MAX KMALLOC_SHIFT_HIGH + #ifndef KMALLOC_SHIFT_LOW + #define KMALLOC_SHIFT_LOW 5 diff --git a/target/linux/generic/patches-4.0/901-debloat_sock_diag.patch b/target/linux/generic/patches-4.0/901-debloat_sock_diag.patch new file mode 100644 index 0000000..9208d6b --- /dev/null +++ b/target/linux/generic/patches-4.0/901-debloat_sock_diag.patch @@ -0,0 +1,45 @@ +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -89,6 +89,9 @@ source "net/netlabel/Kconfig" + + endif # if INET + ++config SOCK_DIAG ++ bool ++ + config NETWORK_SECMARK + bool "Security Marking" + help +--- a/net/core/Makefile ++++ b/net/core/Makefile +@@ -9,8 +9,9 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core. + + obj-y += dev.o ethtool.o dev_addr_lists.o dst.o netevent.o \ + neighbour.o rtnetlink.o utils.o link_watch.o filter.o \ +- sock_diag.o dev_ioctl.o tso.o ++ dev_ioctl.o tso.o + ++obj-$(CONFIG_SOCK_DIAG) += sock_diag.o + obj-$(CONFIG_XFRM) += flow.o + obj-y += net-sysfs.o + obj-$(CONFIG_PROC_FS) += net-procfs.o +--- a/net/ipv4/Kconfig ++++ b/net/ipv4/Kconfig +@@ -428,6 +428,7 @@ config INET_LRO + + config INET_DIAG + tristate "INET: socket monitoring interface" ++ select SOCK_DIAG + default y + ---help--- + Support for INET (TCP, DCCP, etc) socket monitoring interface used by +--- a/net/unix/Kconfig ++++ b/net/unix/Kconfig +@@ -22,6 +22,7 @@ config UNIX + config UNIX_DIAG + tristate "UNIX: socket monitoring interface" + depends on UNIX ++ select SOCK_DIAG + default n + ---help--- + Support for UNIX socket monitoring interface used by the ss tool. diff --git a/target/linux/generic/patches-4.0/902-debloat_proc.patch b/target/linux/generic/patches-4.0/902-debloat_proc.patch new file mode 100644 index 0000000..ca9fd91 --- /dev/null +++ b/target/linux/generic/patches-4.0/902-debloat_proc.patch @@ -0,0 +1,341 @@ +--- a/fs/locks.c ++++ b/fs/locks.c +@@ -2640,6 +2640,8 @@ static const struct file_operations proc + + static int __init proc_locks_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("locks", 0, NULL, &proc_locks_operations); + return 0; + } +--- a/fs/proc/Kconfig ++++ b/fs/proc/Kconfig +@@ -71,3 +71,8 @@ config PROC_PAGE_MONITOR + /proc/pid/smaps, /proc/pid/clear_refs, /proc/pid/pagemap, + /proc/kpagecount, and /proc/kpageflags. Disabling these + interfaces will reduce the size of the kernel by approximately 4kb. ++ ++config PROC_STRIPPED ++ default n ++ depends on EXPERT ++ bool "Strip non-essential /proc functionality to reduce code size" +--- a/fs/proc/consoles.c ++++ b/fs/proc/consoles.c +@@ -106,6 +106,9 @@ static const struct file_operations proc + + static int __init proc_consoles_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + proc_create("consoles", 0, NULL, &proc_consoles_operations); + return 0; + } +--- a/fs/proc/proc_tty.c ++++ b/fs/proc/proc_tty.c +@@ -143,7 +143,10 @@ static const struct file_operations proc + void proc_tty_register_driver(struct tty_driver *driver) + { + struct proc_dir_entry *ent; +- ++ ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (!driver->driver_name || driver->proc_entry || + !driver->ops->proc_fops) + return; +@@ -160,6 +163,9 @@ void proc_tty_unregister_driver(struct t + { + struct proc_dir_entry *ent; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + ent = driver->proc_entry; + if (!ent) + return; +@@ -174,6 +180,9 @@ void proc_tty_unregister_driver(struct t + */ + void __init proc_tty_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (!proc_mkdir("tty", NULL)) + return; + proc_mkdir("tty/ldisc", NULL); /* Preserved: it's userspace visible */ +--- a/kernel/exec_domain.c ++++ b/kernel/exec_domain.c +@@ -176,6 +176,8 @@ static const struct file_operations exec + + static int __init proc_execdomains_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("execdomains", 0, NULL, &execdomains_proc_fops); + return 0; + } +--- a/kernel/irq/proc.c ++++ b/kernel/irq/proc.c +@@ -325,6 +325,9 @@ void register_irq_proc(unsigned int irq, + { + char name [MAX_NAMELEN]; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + if (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip) || desc->dir) + return; + +@@ -361,6 +364,9 @@ void unregister_irq_proc(unsigned int ir + { + char name [MAX_NAMELEN]; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + if (!root_irq_dir || !desc->dir) + return; + #ifdef CONFIG_SMP +@@ -396,6 +402,9 @@ void init_irq_proc(void) + unsigned int irq; + struct irq_desc *desc; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + /* create /proc/irq */ + root_irq_dir = proc_mkdir("irq", NULL); + if (!root_irq_dir) +--- a/kernel/time/timer_list.c ++++ b/kernel/time/timer_list.c +@@ -362,6 +362,8 @@ static int __init init_timer_list_procfs + { + struct proc_dir_entry *pe; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + pe = proc_create("timer_list", 0444, NULL, &timer_list_fops); + if (!pe) + return -ENOMEM; +--- a/mm/vmalloc.c ++++ b/mm/vmalloc.c +@@ -2662,6 +2662,8 @@ static const struct file_operations proc + + static int __init proc_vmalloc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("vmallocinfo", S_IRUSR, NULL, &proc_vmalloc_operations); + return 0; + } +--- a/mm/vmstat.c ++++ b/mm/vmstat.c +@@ -1528,10 +1528,12 @@ static int __init setup_vmstat(void) + cpu_notifier_register_done(); + #endif + #ifdef CONFIG_PROC_FS +- proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations); +- proc_create("pagetypeinfo", S_IRUGO, NULL, &pagetypeinfo_file_ops); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations); ++ proc_create("pagetypeinfo", S_IRUGO, NULL, &pagetypeinfo_file_ops); ++ proc_create("zoneinfo", S_IRUGO, NULL, &proc_zoneinfo_file_operations); ++ } + proc_create("vmstat", S_IRUGO, NULL, &proc_vmstat_file_operations); +- proc_create("zoneinfo", S_IRUGO, NULL, &proc_zoneinfo_file_operations); + #endif + return 0; + } +--- a/net/8021q/vlanproc.c ++++ b/net/8021q/vlanproc.c +@@ -127,6 +127,9 @@ void vlan_proc_cleanup(struct net *net) + { + struct vlan_net *vn = net_generic(net, vlan_net_id); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (vn->proc_vlan_conf) + remove_proc_entry(name_conf, vn->proc_vlan_dir); + +@@ -146,6 +149,9 @@ int __net_init vlan_proc_init(struct net + { + struct vlan_net *vn = net_generic(net, vlan_net_id); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + vn->proc_vlan_dir = proc_net_mkdir(net, name_root, net->proc_net); + if (!vn->proc_vlan_dir) + goto err; +--- a/net/core/sock.c ++++ b/net/core/sock.c +@@ -2975,6 +2975,8 @@ static __net_initdata struct pernet_oper + + static int __init proto_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + return register_pernet_subsys(&proto_net_ops); + } + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -2490,10 +2490,12 @@ static const struct file_operations fib_ + + int __net_init fib_proc_init(struct net *net) + { +- if (!proc_create("fib_trie", S_IRUGO, net->proc_net, &fib_trie_fops)) ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("fib_trie", S_IRUGO, net->proc_net, &fib_trie_fops)) + goto out1; + +- if (!proc_create("fib_triestat", S_IRUGO, net->proc_net, ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("fib_triestat", S_IRUGO, net->proc_net, + &fib_triestat_fops)) + goto out2; + +@@ -2503,17 +2505,21 @@ int __net_init fib_proc_init(struct net + return 0; + + out3: +- remove_proc_entry("fib_triestat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("fib_triestat", net->proc_net); + out2: +- remove_proc_entry("fib_trie", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("fib_trie", net->proc_net); + out1: + return -ENOMEM; + } + + void __net_exit fib_proc_exit(struct net *net) + { +- remove_proc_entry("fib_trie", net->proc_net); +- remove_proc_entry("fib_triestat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ remove_proc_entry("fib_trie", net->proc_net); ++ remove_proc_entry("fib_triestat", net->proc_net); ++ } + remove_proc_entry("route", net->proc_net); + } + +--- a/net/ipv4/proc.c ++++ b/net/ipv4/proc.c +@@ -535,6 +535,9 @@ static __net_initdata struct pernet_oper + + int __init ip_misc_proc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + return register_pernet_subsys(&ip_proc_ops); + } + +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -416,6 +416,9 @@ static struct pernet_operations ip_rt_pr + + static int __init ip_rt_proc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + return register_pernet_subsys(&ip_rt_proc_ops); + } + +--- a/ipc/msg.c ++++ b/ipc/msg.c +@@ -1038,6 +1038,9 @@ void __init msg_init(void) + { + msg_init_ns(&init_ipc_ns); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + ipc_init_proc_interface("sysvipc/msg", + " key msqid perms cbytes qnum lspid lrpid uid gid cuid cgid stime rtime ctime\n", + IPC_MSG_IDS, sysvipc_msg_proc_show); +--- a/ipc/sem.c ++++ b/ipc/sem.c +@@ -191,6 +191,8 @@ void sem_exit_ns(struct ipc_namespace *n + void __init sem_init(void) + { + sem_init_ns(&init_ipc_ns); ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; + ipc_init_proc_interface("sysvipc/sem", + " key semid perms nsems uid gid cuid cgid otime ctime\n", + IPC_SEM_IDS, sysvipc_sem_proc_show); +--- a/ipc/shm.c ++++ b/ipc/shm.c +@@ -118,6 +118,8 @@ pure_initcall(ipc_ns_init); + + void __init shm_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; + ipc_init_proc_interface("sysvipc/shm", + #if BITS_PER_LONG <= 32 + " key shmid perms size cpid lpid nattch uid gid cuid cgid atime dtime ctime rss swap\n", +--- a/ipc/util.c ++++ b/ipc/util.c +@@ -121,6 +121,9 @@ void __init ipc_init_proc_interface(cons + struct proc_dir_entry *pde; + struct ipc_proc_iface *iface; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + iface = kmalloc(sizeof(*iface), GFP_KERNEL); + if (!iface) + return; +--- a/net/core/net-procfs.c ++++ b/net/core/net-procfs.c +@@ -318,10 +318,12 @@ static int __net_init dev_proc_net_init( + + if (!proc_create("dev", S_IRUGO, net->proc_net, &dev_seq_fops)) + goto out; +- if (!proc_create("softnet_stat", S_IRUGO, net->proc_net, ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("softnet_stat", S_IRUGO, net->proc_net, + &softnet_seq_fops)) + goto out_dev; +- if (!proc_create("ptype", S_IRUGO, net->proc_net, &ptype_seq_fops)) ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("ptype", S_IRUGO, net->proc_net, &ptype_seq_fops)) + goto out_softnet; + + if (wext_proc_init(net)) +@@ -330,9 +332,11 @@ static int __net_init dev_proc_net_init( + out: + return rc; + out_ptype: +- remove_proc_entry("ptype", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("ptype", net->proc_net); + out_softnet: +- remove_proc_entry("softnet_stat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("softnet_stat", net->proc_net); + out_dev: + remove_proc_entry("dev", net->proc_net); + goto out; +@@ -342,8 +346,10 @@ static void __net_exit dev_proc_net_exit + { + wext_proc_exit(net); + +- remove_proc_entry("ptype", net->proc_net); +- remove_proc_entry("softnet_stat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ remove_proc_entry("ptype", net->proc_net); ++ remove_proc_entry("softnet_stat", net->proc_net); ++ } + remove_proc_entry("dev", net->proc_net); + } + diff --git a/target/linux/generic/patches-4.0/903-debloat_direct_io.patch b/target/linux/generic/patches-4.0/903-debloat_direct_io.patch new file mode 100644 index 0000000..1b5453b --- /dev/null +++ b/target/linux/generic/patches-4.0/903-debloat_direct_io.patch @@ -0,0 +1,79 @@ +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -70,6 +70,11 @@ config FILE_LOCKING + for filesystems like NFS and for the flock() system + call. Disabling this option saves about 11k. + ++config DIRECT_IO ++ bool "Enable O_DIRECT support" if EXPERT ++ depends on BLOCK ++ default y ++ + source "fs/notify/Kconfig" + + source "fs/quota/Kconfig" +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -14,7 +14,8 @@ obj-y := open.o read_write.o file_table. + stack.o fs_struct.o statfs.o fs_pin.o nsfs.o + + ifeq ($(CONFIG_BLOCK),y) +-obj-y += buffer.o block_dev.o direct-io.o mpage.o ++obj-y += buffer.o block_dev.o mpage.o ++obj-$(CONFIG_DIRECT_IO) += direct-io.o + else + obj-y += no-block.o + endif +--- a/include/linux/fs.h ++++ b/include/linux/fs.h +@@ -2615,12 +2615,25 @@ enum { + DIO_ASYNC_EXTEND = 0x04, + }; + ++#ifdef CONFIG_DIRECT_IO + void dio_end_io(struct bio *bio, int error); + + ssize_t __blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, + struct block_device *bdev, struct iov_iter *iter, loff_t offset, + get_block_t get_block, dio_iodone_t end_io, + dio_submit_t submit_io, int flags); ++#else ++static inline void dio_end_io(struct bio *bio, int error) ++{ ++} ++static inline ssize_t __blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode, ++ struct block_device *bdev, struct iov_iter *iter, loff_t offset, ++ get_block_t get_block, dio_iodone_t end_io, ++ dio_submit_t submit_io, int flags) ++{ ++ return -EOPNOTSUPP; ++} ++#endif + + static inline ssize_t blockdev_direct_IO(int rw, struct kiocb *iocb, + struct inode *inode, struct iov_iter *iter, loff_t offset, +--- a/fs/fcntl.c ++++ b/fs/fcntl.c +@@ -52,8 +52,10 @@ static int setfl(int fd, struct file * f + arg |= O_NONBLOCK; + + if (arg & O_DIRECT) { ++#ifdef CONFIG_DIRECT_IO + if (!filp->f_mapping || !filp->f_mapping->a_ops || + !filp->f_mapping->a_ops->direct_IO) ++#endif + return -EINVAL; + } + +--- a/fs/open.c ++++ b/fs/open.c +@@ -667,7 +667,9 @@ int open_check_o_direct(struct file *f) + { + /* NB: we're sure to have correct a_ops only after f_op->open */ + if (f->f_flags & O_DIRECT) { ++#ifdef CONFIG_DIRECT_IO + if (!f->f_mapping->a_ops || !f->f_mapping->a_ops->direct_IO) ++#endif + return -EINVAL; + } + return 0; diff --git a/target/linux/generic/patches-4.0/910-kobject_uevent.patch b/target/linux/generic/patches-4.0/910-kobject_uevent.patch new file mode 100644 index 0000000..a2c935f --- /dev/null +++ b/target/linux/generic/patches-4.0/910-kobject_uevent.patch @@ -0,0 +1,21 @@ +--- a/lib/kobject_uevent.c ++++ b/lib/kobject_uevent.c +@@ -52,6 +52,18 @@ static const char *kobject_actions[] = { + [KOBJ_OFFLINE] = "offline", + }; + ++u64 uevent_next_seqnum(void) ++{ ++ u64 seq; ++ ++ mutex_lock(&uevent_sock_mutex); ++ seq = ++uevent_seqnum; ++ mutex_unlock(&uevent_sock_mutex); ++ ++ return seq; ++} ++EXPORT_SYMBOL_GPL(uevent_next_seqnum); ++ + /** + * kobject_action_type - translate action string to numeric type + * diff --git a/target/linux/generic/patches-4.0/911-kobject_add_broadcast_uevent.patch b/target/linux/generic/patches-4.0/911-kobject_add_broadcast_uevent.patch new file mode 100644 index 0000000..3afaac1 --- /dev/null +++ b/target/linux/generic/patches-4.0/911-kobject_add_broadcast_uevent.patch @@ -0,0 +1,65 @@ +--- a/include/linux/kobject.h ++++ b/include/linux/kobject.h +@@ -32,6 +32,8 @@ + #define UEVENT_NUM_ENVP 32 /* number of env pointers */ + #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */ + ++struct sk_buff; ++ + #ifdef CONFIG_UEVENT_HELPER + /* path to the userspace helper executed on an event */ + extern char uevent_helper[]; +@@ -221,4 +223,7 @@ int add_uevent_var(struct kobj_uevent_en + int kobject_action_type(const char *buf, size_t count, + enum kobject_action *type); + ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation); ++ + #endif /* _KOBJECT_H_ */ +--- a/lib/kobject_uevent.c ++++ b/lib/kobject_uevent.c +@@ -423,6 +423,43 @@ int add_uevent_var(struct kobj_uevent_en + EXPORT_SYMBOL_GPL(add_uevent_var); + + #if defined(CONFIG_NET) ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation) ++{ ++ struct uevent_sock *ue_sk; ++ int err = 0; ++ ++ /* send netlink message */ ++ mutex_lock(&uevent_sock_mutex); ++ list_for_each_entry(ue_sk, &uevent_sock_list, list) { ++ struct sock *uevent_sock = ue_sk->sk; ++ struct sk_buff *skb2; ++ ++ skb2 = skb_clone(skb, allocation); ++ if (!skb2) ++ break; ++ ++ err = netlink_broadcast(uevent_sock, skb2, pid, group, ++ allocation); ++ if (err) ++ break; ++ } ++ mutex_unlock(&uevent_sock_mutex); ++ ++ kfree_skb(skb); ++ return err; ++} ++#else ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation) ++{ ++ kfree_skb(skb); ++ return 0; ++} ++#endif ++EXPORT_SYMBOL_GPL(broadcast_uevent); ++ ++#if defined(CONFIG_NET) + static int uevent_net_init(struct net *net) + { + struct uevent_sock *ue_sk; diff --git a/target/linux/generic/patches-4.0/921-use_preinit_as_init.patch b/target/linux/generic/patches-4.0/921-use_preinit_as_init.patch new file mode 100644 index 0000000..d0aa29f --- /dev/null +++ b/target/linux/generic/patches-4.0/921-use_preinit_as_init.patch @@ -0,0 +1,12 @@ +--- a/init/main.c ++++ b/init/main.c +@@ -957,7 +957,8 @@ static int __ref kernel_init(void *unuse + panic("Requested init %s failed (error %d).", + execute_command, ret); + } +- if (!try_to_run_init_process("/sbin/init") || ++ if (!try_to_run_init_process("/etc/preinit") || ++ !try_to_run_init_process("/sbin/init") || + !try_to_run_init_process("/etc/init") || + !try_to_run_init_process("/bin/init") || + !try_to_run_init_process("/bin/sh")) diff --git a/target/linux/generic/patches-4.0/922-always-create-console-node-in-initramfs.patch b/target/linux/generic/patches-4.0/922-always-create-console-node-in-initramfs.patch new file mode 100644 index 0000000..988de35 --- /dev/null +++ b/target/linux/generic/patches-4.0/922-always-create-console-node-in-initramfs.patch @@ -0,0 +1,30 @@ +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -59,6 +59,18 @@ default_initramfs() { + EOF + } + ++list_openwrt_initramfs() { ++ : ++} ++ ++openwrt_initramfs() { ++ # make sure that /dev/console exists ++ cat <<-EOF >> ${output} ++ dir /dev 0755 0 0 ++ nod /dev/console 0600 0 0 c 5 1 ++ EOF ++} ++ + filetype() { + local argv1="$1" + +@@ -177,6 +189,8 @@ dir_filelist() { + if [ "$(echo "${dirlist}" | wc -l)" -gt 1 ]; then + ${dep_list}print_mtime "$1" + ++ ${dep_list}openwrt_initramfs ++ + echo "${dirlist}" | \ + while read x; do + ${dep_list}parse ${x} diff --git a/target/linux/generic/patches-4.0/930-crashlog.patch b/target/linux/generic/patches-4.0/930-crashlog.patch new file mode 100644 index 0000000..d9c5ecd --- /dev/null +++ b/target/linux/generic/patches-4.0/930-crashlog.patch @@ -0,0 +1,276 @@ +--- /dev/null ++++ b/include/linux/crashlog.h +@@ -0,0 +1,17 @@ ++#ifndef __CRASHLOG_H ++#define __CRASHLOG_H ++ ++#ifdef CONFIG_CRASHLOG ++void crashlog_init_bootmem(struct bootmem_data *bdata); ++void crashlog_init_memblock(phys_addr_t addr, phys_addr_t size); ++#else ++static inline void crashlog_init_bootmem(struct bootmem_data *bdata) ++{ ++} ++ ++static inline void crashlog_init_memblock(phys_addr_t addr, phys_addr_t size) ++{ ++} ++#endif ++ ++#endif +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1265,6 +1265,10 @@ config RELAY + + If unsure, say N. + ++config CRASHLOG ++ bool "Crash logging" ++ depends on (!NO_BOOTMEM || HAVE_MEMBLOCK) && !(ARM || SPARC || PPC) ++ + config BLK_DEV_INITRD + bool "Initial RAM filesystem and RAM disk (initramfs/initrd) support" + depends on BROKEN || !FRV +--- a/kernel/Makefile ++++ b/kernel/Makefile +@@ -96,6 +96,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o + obj-$(CONFIG_JUMP_LABEL) += jump_label.o + obj-$(CONFIG_CONTEXT_TRACKING) += context_tracking.o + obj-$(CONFIG_TORTURE_TEST) += torture.o ++obj-$(CONFIG_CRASHLOG) += crashlog.o + + $(obj)/configs.o: $(obj)/config_data.h + +--- /dev/null ++++ b/kernel/crashlog.c +@@ -0,0 +1,181 @@ ++/* ++ * Crash information logger ++ * Copyright (C) 2010 Felix Fietkau ++ * ++ * Based on ramoops.c ++ * Copyright (C) 2010 Marco Stornelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CRASHLOG_PAGES 4 ++#define CRASHLOG_SIZE (CRASHLOG_PAGES * PAGE_SIZE) ++#define CRASHLOG_MAGIC 0xa1eedead ++ ++/* ++ * Start the log at 1M before the end of RAM, as some boot loaders like ++ * to use the end of the RAM for stack usage and other things ++ * If this fails, fall back to using the last part. ++ */ ++#define CRASHLOG_OFFSET (1024 * 1024) ++ ++struct crashlog_data { ++ u32 magic; ++ u32 len; ++ u8 data[]; ++}; ++ ++static struct debugfs_blob_wrapper crashlog_blob; ++static unsigned long crashlog_addr = 0; ++static struct crashlog_data *crashlog_buf; ++static struct kmsg_dumper dump; ++static bool first = true; ++ ++extern struct list_head *crashlog_modules; ++ ++#ifndef CONFIG_NO_BOOTMEM ++void __init crashlog_init_bootmem(bootmem_data_t *bdata) ++{ ++ unsigned long addr; ++ ++ if (crashlog_addr) ++ return; ++ ++ addr = PFN_PHYS(bdata->node_low_pfn) - CRASHLOG_OFFSET; ++ if (reserve_bootmem(addr, CRASHLOG_SIZE, BOOTMEM_EXCLUSIVE) < 0) { ++ printk("Crashlog failed to allocate RAM at address 0x%lx\n", addr); ++ bdata->node_low_pfn -= CRASHLOG_PAGES; ++ addr = PFN_PHYS(bdata->node_low_pfn); ++ } ++ crashlog_addr = addr; ++} ++#endif ++ ++#ifdef CONFIG_HAVE_MEMBLOCK ++void __meminit crashlog_init_memblock(phys_addr_t addr, phys_addr_t size) ++{ ++ if (crashlog_addr) ++ return; ++ ++ addr += size - CRASHLOG_OFFSET; ++ if (memblock_reserve(addr, CRASHLOG_SIZE)) { ++ printk("Crashlog failed to allocate RAM at address 0x%lx\n", (unsigned long) addr); ++ return; ++ } ++ ++ crashlog_addr = addr; ++} ++#endif ++ ++static void __init crashlog_copy(void) ++{ ++ if (crashlog_buf->magic != CRASHLOG_MAGIC) ++ return; ++ ++ if (!crashlog_buf->len || crashlog_buf->len > ++ CRASHLOG_SIZE - sizeof(*crashlog_buf)) ++ return; ++ ++ crashlog_blob.size = crashlog_buf->len; ++ crashlog_blob.data = kmemdup(crashlog_buf->data, ++ crashlog_buf->len, GFP_KERNEL); ++ ++ debugfs_create_blob("crashlog", 0700, NULL, &crashlog_blob); ++} ++ ++static int get_maxlen(void) ++{ ++ return CRASHLOG_SIZE - sizeof(*crashlog_buf) - crashlog_buf->len; ++} ++ ++static void crashlog_printf(const char *fmt, ...) ++{ ++ va_list args; ++ int len = get_maxlen(); ++ ++ if (!len) ++ return; ++ ++ va_start(args, fmt); ++ crashlog_buf->len += vscnprintf( ++ &crashlog_buf->data[crashlog_buf->len], ++ len, fmt, args); ++ va_end(args); ++} ++ ++static void crashlog_do_dump(struct kmsg_dumper *dumper, ++ enum kmsg_dump_reason reason) ++{ ++ struct timeval tv; ++ struct module *m; ++ char *buf; ++ size_t len; ++ ++ if (!first) ++ crashlog_printf("\n===================================\n"); ++ ++ do_gettimeofday(&tv); ++ crashlog_printf("Time: %lu.%lu\n", ++ (long)tv.tv_sec, (long)tv.tv_usec); ++ ++ if (first) { ++ crashlog_printf("Modules:"); ++ list_for_each_entry(m, crashlog_modules, list) { ++ crashlog_printf("\t%s@%p+%x", m->name, ++ m->module_core, m->core_size, ++ m->module_init, m->init_size); ++ } ++ crashlog_printf("\n"); ++ first = false; ++ } ++ ++ buf = (char *)&crashlog_buf->data[crashlog_buf->len]; ++ ++ kmsg_dump_get_buffer(dumper, true, buf, get_maxlen(), &len); ++ ++ crashlog_buf->len += len; ++} ++ ++ ++int __init crashlog_init_fs(void) ++{ ++ if (!crashlog_addr) ++ return -ENOMEM; ++ ++ crashlog_buf = ioremap(crashlog_addr, CRASHLOG_SIZE); ++ ++ crashlog_copy(); ++ ++ crashlog_buf->magic = CRASHLOG_MAGIC; ++ crashlog_buf->len = 0; ++ ++ dump.max_reason = KMSG_DUMP_OOPS; ++ dump.dump = crashlog_do_dump; ++ kmsg_dump_register(&dump); ++ ++ return 0; ++} ++module_init(crashlog_init_fs); +--- a/mm/bootmem.c ++++ b/mm/bootmem.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -177,6 +178,7 @@ static unsigned long __init free_all_boo + if (!bdata->node_bootmem_map) + return 0; + ++ crashlog_init_bootmem(bdata); + map = bdata->node_bootmem_map; + start = bdata->node_min_pfn; + end = bdata->node_low_pfn; +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -104,6 +104,9 @@ static LIST_HEAD(modules); + #ifdef CONFIG_KGDB_KDB + struct list_head *kdb_modules = &modules; /* kdb needs the list of modules */ + #endif /* CONFIG_KGDB_KDB */ ++#ifdef CONFIG_CRASHLOG ++struct list_head *crashlog_modules = &modules; ++#endif + + #ifdef CONFIG_MODULE_SIG + #ifdef CONFIG_MODULE_SIG_FORCE +--- a/mm/memblock.c ++++ b/mm/memblock.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -477,6 +478,8 @@ static void __init_memblock memblock_ins + memblock_set_region_node(rgn, nid); + type->cnt++; + type->total_size += size; ++ if (type == &memblock.memory && idx == 0) ++ crashlog_init_memblock(base, size); + } + + /** diff --git a/target/linux/generic/patches-4.0/940-ocf_kbuild_integration.patch b/target/linux/generic/patches-4.0/940-ocf_kbuild_integration.patch new file mode 100644 index 0000000..36776a9 --- /dev/null +++ b/target/linux/generic/patches-4.0/940-ocf_kbuild_integration.patch @@ -0,0 +1,20 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -1537,3 +1537,6 @@ source "drivers/crypto/Kconfig" + source crypto/asymmetric_keys/Kconfig + + endif # if CRYPTO ++ ++source "crypto/ocf/Kconfig" ++ +--- a/crypto/Makefile ++++ b/crypto/Makefile +@@ -102,6 +102,8 @@ obj-$(CONFIG_CRYPTO_USER_API_HASH) += al + obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o + obj-$(CONFIG_CRYPTO_USER_API_RNG) += algif_rng.o + ++obj-$(CONFIG_OCF_OCF) += ocf/ ++ + # + # generic algorithms and the async_tx api + # diff --git a/target/linux/generic/patches-4.0/941-ocf_20120127.patch b/target/linux/generic/patches-4.0/941-ocf_20120127.patch new file mode 100644 index 0000000..fad7acf --- /dev/null +++ b/target/linux/generic/patches-4.0/941-ocf_20120127.patch @@ -0,0 +1,166 @@ +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -139,6 +139,9 @@ + * that might otherwise be identical and have very little entropy + * available to them (particularly common in the embedded world). + * ++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++ * int random_input_wait(void); ++ * + * add_input_randomness() uses the input layer interrupt timing, as well as + * the event type information from the hardware. + * +@@ -152,6 +155,13 @@ + * seek times do not make for good sources of entropy, as their seek + * times are usually fairly consistent. + * ++ * random_input_words() just provides a raw block of entropy to the input ++ * pool, such as from a hardware entropy generator. ++ * ++ * random_input_wait() suspends the caller until such time as the ++ * entropy pool falls below the write threshold, and returns a count of how ++ * much entropy (in bits) is needed to sustain the pool. ++ * + * All of these routines try to estimate how many bits of randomness a + * particular randomness source. They do this by keeping track of the + * first and second order deltas of the event timings. +@@ -938,6 +948,63 @@ void add_disk_randomness(struct gendisk + EXPORT_SYMBOL_GPL(add_disk_randomness); + #endif + ++/* ++ * random_input_words - add bulk entropy to pool ++ * ++ * @buf: buffer to add ++ * @wordcount: number of __u32 words to add ++ * @ent_count: total amount of entropy (in bits) to credit ++ * ++ * this provides bulk input of entropy to the input pool ++ * ++ */ ++void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++{ ++ mix_pool_bytes(&input_pool, buf, wordcount*4); ++ ++ credit_entropy_bits(&input_pool, ent_count); ++ ++ pr_notice("crediting %d bits => %d\n", ++ ent_count, input_pool.entropy_count); ++ /* ++ * Wake up waiting processes if we have enough ++ * entropy. ++ */ ++ if (input_pool.entropy_count >= random_read_wakeup_bits) ++ wake_up_interruptible(&random_read_wait); ++} ++EXPORT_SYMBOL(random_input_words); ++ ++/* ++ * random_input_wait - wait until random needs entropy ++ * ++ * this function sleeps until the /dev/random subsystem actually ++ * needs more entropy, and then return the amount of entropy ++ * that it would be nice to have added to the system. ++ */ ++int random_input_wait(void) ++{ ++ int count; ++ ++ wait_event_interruptible(random_write_wait, ++ input_pool.entropy_count < random_write_wakeup_bits); ++ ++ count = random_write_wakeup_bits - input_pool.entropy_count; ++ ++ /* likely we got woken up due to a signal */ ++ if (count <= 0) count = random_read_wakeup_bits; ++ ++ pr_notice("requesting %d bits from input_wait()er %d<%d\n", ++ count, ++ input_pool.entropy_count, random_write_wakeup_bits); ++ ++ return count; ++} ++EXPORT_SYMBOL(random_input_wait); ++ ++ ++#define EXTRACT_SIZE 10 ++ + /********************************************************************* + * + * Entropy extraction routines +--- a/fs/fcntl.c ++++ b/fs/fcntl.c +@@ -140,6 +140,7 @@ pid_t f_getown(struct file *filp) + read_unlock(&filp->f_owner.lock); + return pid; + } ++EXPORT_SYMBOL(sys_dup); + + static int f_setown_ex(struct file *filp, unsigned long arg) + { +--- a/include/linux/miscdevice.h ++++ b/include/linux/miscdevice.h +@@ -19,6 +19,7 @@ + #define APOLLO_MOUSE_MINOR 7 /* unused */ + #define PC110PAD_MINOR 9 /* unused */ + /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ ++#define CRYPTODEV_MINOR 70 /* /dev/crypto */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +--- a/include/uapi/linux/random.h ++++ b/include/uapi/linux/random.h +@@ -34,6 +34,30 @@ + /* Clear the entropy pool and associated counters. (Superuser only.) */ + #define RNDCLEARPOOL _IO( 'R', 0x06 ) + ++#ifdef CONFIG_FIPS_RNG ++ ++/* Size of seed value - equal to AES blocksize */ ++#define AES_BLOCK_SIZE_BYTES 16 ++#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES ++/* Size of AES key */ ++#define KEY_SIZE_BYTES 16 ++ ++/* ioctl() structure used by FIPS 140-2 Tests */ ++struct rand_fips_test { ++ unsigned char key[KEY_SIZE_BYTES]; /* Input */ ++ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char result[SEED_SIZE_BYTES]; /* Output */ ++}; ++ ++/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ ++#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) ++ ++/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ ++#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) ++ ++#endif /* #ifdef CONFIG_FIPS_RNG */ ++ + struct rand_pool_info { + int entropy_count; + int buf_size; +--- a/include/linux/random.h ++++ b/include/linux/random.h +@@ -13,6 +13,10 @@ extern void add_input_randomness(unsigne + unsigned int value); + extern void add_interrupt_randomness(int irq, int irq_flags); + ++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); ++extern int random_input_wait(void); ++#define HAS_RANDOM_INPUT_WAIT 1 ++ + extern void get_random_bytes(void *buf, int nbytes); + extern void get_random_bytes_arch(void *buf, int nbytes); + void generate_random_uuid(unsigned char uuid_out[16]); +--- a/kernel/pid.c ++++ b/kernel/pid.c +@@ -430,6 +430,7 @@ void transfer_pid(struct task_struct *ol + new->pids[type].pid = old->pids[type].pid; + hlist_replace_rcu(&old->pids[type].node, &new->pids[type].node); + } ++EXPORT_SYMBOL(find_task_by_vpid); + + struct task_struct *pid_task(struct pid *pid, enum pid_type type) + { diff --git a/target/linux/generic/patches-4.0/960-decompress_unlzo_fix.patch b/target/linux/generic/patches-4.0/960-decompress_unlzo_fix.patch new file mode 100644 index 0000000..ee7c118 --- /dev/null +++ b/target/linux/generic/patches-4.0/960-decompress_unlzo_fix.patch @@ -0,0 +1,23 @@ +--- /dev/null ++++ b/include/linux/decompress/unlzo_mm.h +@@ -0,0 +1,10 @@ ++#ifndef UNLZO_MM_H ++#define UNLZO_MM_H ++ ++#ifdef STATIC ++#define INIT ++#else ++#define INIT __init ++#endif ++ ++#endif +--- a/lib/decompress_unlzo.c ++++ b/lib/decompress_unlzo.c +@@ -38,6 +38,7 @@ + + #include + #include ++#include + #include + + #include diff --git a/target/linux/generic/patches-4.0/970-remove-unsane-filenames-from-deps_initramfs-list.patch b/target/linux/generic/patches-4.0/970-remove-unsane-filenames-from-deps_initramfs-list.patch new file mode 100644 index 0000000..ac13c9e --- /dev/null +++ b/target/linux/generic/patches-4.0/970-remove-unsane-filenames-from-deps_initramfs-list.patch @@ -0,0 +1,29 @@ +--- a/usr/Makefile ++++ b/usr/Makefile +@@ -53,6 +53,8 @@ ifneq ($(wildcard $(obj)/.initramfs_data + include $(obj)/.initramfs_data.cpio.d + endif + ++deps_initramfs_sane := $(foreach v,$(deps_initramfs),$(if $(findstring :,$(v)),,$(v))) ++ + quiet_cmd_initfs = GEN $@ + cmd_initfs = $(initramfs) -o $@ $(ramfs-args) $(ramfs-input) + +@@ -61,14 +63,14 @@ targets := initramfs_data.cpio.gz initra + initramfs_data.cpio.lzo initramfs_data.cpio.lz4 \ + initramfs_data.cpio + # do not try to update files included in initramfs +-$(deps_initramfs): ; ++$(deps_initramfs_sane): ; + +-$(deps_initramfs): klibcdirs ++$(deps_initramfs_sane): klibcdirs + # We rebuild initramfs_data.cpio if: + # 1) Any included file is newer then initramfs_data.cpio + # 2) There are changes in which files are included (added or deleted) + # 3) If gen_init_cpio are newer than initramfs_data.cpio + # 4) arguments to gen_initramfs.sh changes +-$(obj)/initramfs_data.cpio$(suffix_y): $(obj)/gen_init_cpio $(deps_initramfs) klibcdirs ++$(obj)/initramfs_data.cpio$(suffix_y): $(obj)/gen_init_cpio $(deps_initramfs_sane) klibcdirs + $(Q)$(initramfs) -l $(ramfs-input) > $(obj)/.initramfs_data.cpio.d + $(call if_changed,initfs) diff --git a/target/linux/generic/patches-4.0/980-arm_openwrt_machtypes.patch b/target/linux/generic/patches-4.0/980-arm_openwrt_machtypes.patch new file mode 100644 index 0000000..5e9718b --- /dev/null +++ b/target/linux/generic/patches-4.0/980-arm_openwrt_machtypes.patch @@ -0,0 +1,32 @@ +--- a/arch/arm/tools/mach-types ++++ b/arch/arm/tools/mach-types +@@ -1007,3 +1007,29 @@ eco5_bx2 MACH_ECO5_BX2 ECO5_BX2 4572 + eukrea_cpuimx28sd MACH_EUKREA_CPUIMX28SD EUKREA_CPUIMX28SD 4573 + domotab MACH_DOMOTAB DOMOTAB 4574 + pfla03 MACH_PFLA03 PFLA03 4575 ++# ++# Additional mach-types supported by OpenWrt ++# ++wg302v1 MACH_WG302V1 WG302V1 889 ++pronghorn MACH_PRONGHORN PRONGHORN 928 ++pronghorn_metro MACH_PRONGHORNMETRO PRONGHORNMETRO 1040 ++sidewinder MACH_SIDEWINDER SIDEWINDER 1041 ++wrt300nv2 MACH_WRT300NV2 WRT300NV2 1077 ++compex42x MACH_COMPEXWP18 COMPEXWP18 1273 ++goldfish MACH_GOLDFISH GOLDFISH 1441 ++cambria MACH_CAMBRIA CAMBRIA 1468 ++dt2 MACH_DT2 DT2 1514 ++ap1000 MACH_AP1000 AP1000 1543 ++tw2662 MACH_TW2662 TW2662 1658 ++tw5334 MACH_TW5334 TW5334 1664 ++usr8200 MACH_USR8200 USR8200 1762 ++mi424wr MACH_MI424WR MI424WR 1778 ++gw2388 MACH_GW2388 GW2388 2635 ++iconnect MACH_ICONNECT ICONNECT 2870 ++nsb3ast MACH_NSB3AST NSB3AST 2917 ++goflexnet MACH_GOFLEXNET GOFLEXNET 3089 ++nas6210 MACH_NAS6210 NAS6210 3104 ++ns_k330 MACH_NS_K330 NS_K330 3108 ++bcm2708 MACH_BCM2708 BCM2708 3138 ++wn802t MACH_WN802T WN802T 3306 ++nsa310 MACH_NSA310 NSA310 4022 diff --git a/target/linux/generic/patches-4.0/990-gpio_wdt.patch b/target/linux/generic/patches-4.0/990-gpio_wdt.patch new file mode 100644 index 0000000..cc1906a --- /dev/null +++ b/target/linux/generic/patches-4.0/990-gpio_wdt.patch @@ -0,0 +1,360 @@ +This generic GPIO watchdog is used on Huawei E970 (brcm47xx) + +Signed-off-by: Mathias Adam + +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1151,6 +1151,15 @@ config WDT_MTX1 + Hardware driver for the MTX-1 boards. This is a watchdog timer that + will reboot the machine after a 100 seconds timer expired. + ++config GPIO_WDT ++ tristate "GPIO Hardware Watchdog" ++ help ++ Hardware driver for GPIO-controlled watchdogs. GPIO pin and ++ toggle interval settings are platform-specific. The driver ++ will stop toggling the GPIO (i.e. machine reboots) after a ++ 100 second timer expired and no process has written to ++ /dev/watchdog during that time. ++ + config PNX833X_WDT + tristate "PNX833x Hardware Watchdog" + depends on SOC_PNX8335 +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -135,6 +135,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt + obj-$(CONFIG_INDYDOG) += indydog.o + obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o + obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o ++obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o +--- /dev/null ++++ b/drivers/watchdog/old_gpio_wdt.c +@@ -0,0 +1,301 @@ ++/* ++ * Driver for GPIO-controlled Hardware Watchdogs. ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * Replaces mtx1_wdt (driver for the MTX-1 Watchdog): ++ * ++ * (C) Copyright 2005 4G Systems , ++ * All Rights Reserved. ++ * http://www.4g-systems.biz ++ * ++ * (C) Copyright 2007 OpenWrt.org, Florian Fainelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Neither Michael Stickel nor 4G Systems admit liability nor provide ++ * warranty for any of this software. This material is provided ++ * "AS-IS" and at no charge. ++ * ++ * (c) Copyright 2005 4G Systems ++ * ++ * Release 0.01. ++ * Author: Michael Stickel michael.stickel@4g-systems.biz ++ * ++ * Release 0.02. ++ * Author: Florian Fainelli florian@openwrt.org ++ * use the Linux watchdog/timer APIs ++ * ++ * Release 0.03. ++ * Author: Mathias Adam ++ * make it a generic gpio watchdog driver ++ * ++ * The Watchdog is configured to reset the MTX-1 ++ * if it is not triggered for 100 seconds. ++ * It should not be triggered more often than 1.6 seconds. ++ * ++ * A timer triggers the watchdog every 5 seconds, until ++ * it is opened for the first time. After the first open ++ * it MUST be triggered every 2..95 seconds. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ticks = 100 * HZ; ++ ++static struct { ++ struct completion stop; ++ spinlock_t lock; ++ int running; ++ struct timer_list timer; ++ int queue; ++ int default_ticks; ++ unsigned long inuse; ++ unsigned gpio; ++ unsigned int gstate; ++ int interval; ++ int first_interval; ++} gpio_wdt_device; ++ ++static void gpio_wdt_trigger(unsigned long unused) ++{ ++ spin_lock(&gpio_wdt_device.lock); ++ if (gpio_wdt_device.running && ticks > 0) ++ ticks -= gpio_wdt_device.interval; ++ ++ /* toggle wdt gpio */ ++ gpio_wdt_device.gstate = !gpio_wdt_device.gstate; ++ gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate); ++ ++ if (gpio_wdt_device.queue && ticks > 0) ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval); ++ else ++ complete(&gpio_wdt_device.stop); ++ spin_unlock(&gpio_wdt_device.lock); ++} ++ ++static void gpio_wdt_reset(void) ++{ ++ ticks = gpio_wdt_device.default_ticks; ++} ++ ++ ++static void gpio_wdt_start(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (!gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 1; ++ gpio_wdt_device.gstate = 1; ++ gpio_set_value(gpio_wdt_device.gpio, 1); ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval); ++ } ++ gpio_wdt_device.running++; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++} ++ ++static int gpio_wdt_stop(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ gpio_wdt_device.gstate = 0; ++ gpio_set_value(gpio_wdt_device.gpio, 0); ++ } ++ ticks = gpio_wdt_device.default_ticks; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++ return 0; ++} ++ ++/* Filesystem functions */ ++ ++static int gpio_wdt_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(0, &gpio_wdt_device.inuse)) ++ return -EBUSY; ++ return nonseekable_open(inode, file); ++} ++ ++ ++static int gpio_wdt_release(struct inode *inode, struct file *file) ++{ ++ clear_bit(0, &gpio_wdt_device.inuse); ++ return 0; ++} ++ ++static long gpio_wdt_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ void __user *argp = (void __user *)arg; ++ int __user *p = (int __user *)argp; ++ unsigned int value; ++ static const struct watchdog_info ident = { ++ .options = WDIOF_CARDRESET, ++ .identity = "GPIO WDT", ++ }; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ if (copy_to_user(argp, &ident, sizeof(ident))) ++ return -EFAULT; ++ break; ++ case WDIOC_GETSTATUS: ++ case WDIOC_GETBOOTSTATUS: ++ put_user(0, p); ++ break; ++ case WDIOC_SETOPTIONS: ++ if (get_user(value, p)) ++ return -EFAULT; ++ if (value & WDIOS_ENABLECARD) ++ gpio_wdt_start(); ++ else if (value & WDIOS_DISABLECARD) ++ gpio_wdt_stop(); ++ else ++ return -EINVAL; ++ return 0; ++ case WDIOC_KEEPALIVE: ++ gpio_wdt_reset(); ++ break; ++ default: ++ return -ENOTTY; ++ } ++ return 0; ++} ++ ++ ++static ssize_t gpio_wdt_write(struct file *file, const char *buf, ++ size_t count, loff_t *ppos) ++{ ++ if (!count) ++ return -EIO; ++ gpio_wdt_reset(); ++ return count; ++} ++ ++static const struct file_operations gpio_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .unlocked_ioctl = gpio_wdt_ioctl, ++ .open = gpio_wdt_open, ++ .write = gpio_wdt_write, ++ .release = gpio_wdt_release, ++}; ++ ++ ++static struct miscdevice gpio_wdt_misc = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &gpio_wdt_fops, ++}; ++ ++ ++static int gpio_wdt_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data; ++ ++ gpio_wdt_device.gpio = gpio_wdt_data->gpio; ++ gpio_wdt_device.interval = gpio_wdt_data->interval; ++ gpio_wdt_device.first_interval = gpio_wdt_data->first_interval; ++ if (gpio_wdt_device.first_interval <= 0) { ++ gpio_wdt_device.first_interval = gpio_wdt_device.interval; ++ } ++ ++ ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt"); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to request gpio"); ++ return ret; ++ } ++ ++ spin_lock_init(&gpio_wdt_device.lock); ++ init_completion(&gpio_wdt_device.stop); ++ gpio_wdt_device.queue = 0; ++ clear_bit(0, &gpio_wdt_device.inuse); ++ setup_timer(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L); ++ gpio_wdt_device.default_ticks = ticks; ++ ++ gpio_wdt_start(); ++ dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n", ++ gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval); ++ return 0; ++} ++ ++static int gpio_wdt_remove(struct platform_device *pdev) ++{ ++ /* FIXME: do we need to lock this test ? */ ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ wait_for_completion(&gpio_wdt_device.stop); ++ } ++ ++ gpio_free(gpio_wdt_device.gpio); ++ misc_deregister(&gpio_wdt_misc); ++ return 0; ++} ++ ++static struct platform_driver gpio_wdt_driver = { ++ .probe = gpio_wdt_probe, ++ .remove = gpio_wdt_remove, ++ .driver.name = "gpio-wdt", ++ .driver.owner = THIS_MODULE, ++}; ++ ++static int __init gpio_wdt_init(void) ++{ ++ return platform_driver_register(&gpio_wdt_driver); ++} ++arch_initcall(gpio_wdt_init); ++ ++/* ++ * We do wdt initialization in two steps: arch_initcall probes the wdt ++ * very early to start pinging the watchdog (misc devices are not yet ++ * available), and later module_init() just registers the misc device. ++ */ ++static int gpio_wdt_init_late(void) ++{ ++ int ret; ++ ++ ret = misc_register(&gpio_wdt_misc); ++ if (ret < 0) { ++ pr_err("GPIO_WDT: failed to register misc device\n"); ++ return ret; ++ } ++ return 0; ++} ++#ifndef MODULE ++module_init(gpio_wdt_init_late); ++#endif ++ ++static void __exit gpio_wdt_exit(void) ++{ ++ platform_driver_unregister(&gpio_wdt_driver); ++} ++module_exit(gpio_wdt_exit); ++ ++MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam"); ++MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:gpio-wdt"); +--- /dev/null ++++ b/include/linux/old_gpio_wdt.h +@@ -0,0 +1,21 @@ ++/* ++ * Definitions for the GPIO watchdog driver ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef _GPIO_WDT_H_ ++#define _GPIO_WDT_H_ ++ ++struct gpio_wdt_platform_data { ++ int gpio; /* GPIO line number */ ++ int interval; /* watchdog reset interval in system ticks */ ++ int first_interval; /* first wd reset interval in system ticks */ ++}; ++ ++#endif /* _GPIO_WDT_H_ */ diff --git a/target/linux/generic/patches-4.0/995-mangle_bootargs.patch b/target/linux/generic/patches-4.0/995-mangle_bootargs.patch new file mode 100644 index 0000000..ebfc6d8 --- /dev/null +++ b/target/linux/generic/patches-4.0/995-mangle_bootargs.patch @@ -0,0 +1,58 @@ +--- a/init/main.c ++++ b/init/main.c +@@ -351,6 +351,29 @@ static inline void setup_nr_cpu_ids(void + static inline void smp_prepare_cpus(unsigned int maxcpus) { } + #endif + ++#ifdef CONFIG_MANGLE_BOOTARGS ++static void __init mangle_bootargs(char *command_line) ++{ ++ char *rootdev; ++ char *rootfs; ++ ++ rootdev = strstr(command_line, "root=/dev/mtdblock"); ++ ++ if (rootdev) ++ strncpy(rootdev, "mangled_rootblock=", 18); ++ ++ rootfs = strstr(command_line, "rootfstype"); ++ ++ if (rootfs) ++ strncpy(rootfs, "mangled_fs", 10); ++ ++} ++#else ++static void __init mangle_bootargs(char *command_line) ++{ ++} ++#endif ++ + /* + * We need to store the untouched command line for future reference. + * We also need to store the touched command line since the parameter +@@ -519,6 +542,7 @@ asmlinkage __visible void __init start_k + pr_notice("%s", linux_banner); + setup_arch(&command_line); + mm_init_cpumask(&init_mm); ++ mangle_bootargs(command_line); + setup_command_line(command_line); + setup_nr_cpu_ids(); + setup_per_cpu_areas(); +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1583,6 +1583,15 @@ config EMBEDDED + an embedded system so certain expert options are available + for configuration. + ++config MANGLE_BOOTARGS ++ bool "Rename offending bootargs" ++ depends on EXPERT ++ help ++ Sometimes the bootloader passed bogus root= and rootfstype= ++ parameters to the kernel, and while you want to ignore them, ++ you need to know the values f.e. to support dual firmware ++ layouts on the flash. ++ + config HAVE_PERF_EVENTS + bool + help diff --git a/target/linux/generic/patches-4.0/997-device_tree_cmdline.patch b/target/linux/generic/patches-4.0/997-device_tree_cmdline.patch new file mode 100644 index 0000000..8063809 --- /dev/null +++ b/target/linux/generic/patches-4.0/997-device_tree_cmdline.patch @@ -0,0 +1,24 @@ +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -917,6 +917,9 @@ int __init early_init_dt_scan_chosen(uns + p = of_get_flat_dt_prop(node, "bootargs", &l); + if (p != NULL && l > 0) + strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); ++ p = of_get_flat_dt_prop(node, "bootargs-append", &l); ++ if (p != NULL && l > 0) ++ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else +--- a/arch/mips/kernel/prom.c ++++ b/arch/mips/kernel/prom.c +@@ -50,6 +50,9 @@ void * __init early_init_dt_alloc_memory + + void __init __dt_setup_arch(void *bph) + { ++ if (boot_command_line[0] == '\0') ++ strcpy(boot_command_line, arcs_cmdline); ++ + if (!early_init_dt_scan(bph)) + return; + diff --git a/target/linux/generic/patches-4.0/998-enable_wilink_platform_without_drivers.patch b/target/linux/generic/patches-4.0/998-enable_wilink_platform_without_drivers.patch new file mode 100644 index 0000000..d317de1 --- /dev/null +++ b/target/linux/generic/patches-4.0/998-enable_wilink_platform_without_drivers.patch @@ -0,0 +1,15 @@ +We use backports for driver updates - make sure we can compile in the glue code regardless + +Signed-off-by: Imre Kaloz + +--- a/drivers/net/wireless/ti/Kconfig ++++ b/drivers/net/wireless/ti/Kconfig +@@ -15,7 +15,7 @@ source "drivers/net/wireless/ti/wlcore/K + + config WILINK_PLATFORM_DATA + bool "TI WiLink platform data" +- depends on WLCORE_SDIO || WL1251_SDIO ++ depends on WLCORE_SDIO || WL1251_SDIO || ARCH_OMAP2PLUS + default y + ---help--- + Small platform data bit needed to pass data to the sdio modules. diff --git a/target/linux/generic/patches-4.1/000-keep_initrafs_the_default.patch b/target/linux/generic/patches-4.1/000-keep_initrafs_the_default.patch new file mode 100644 index 0000000..5e56d44 --- /dev/null +++ b/target/linux/generic/patches-4.1/000-keep_initrafs_the_default.patch @@ -0,0 +1,25 @@ +Upstream changed the default rootfs to tmpfs when none has been passed +to the kernel - this doesn't fit our purposes, so change it back. + +Signed-off-by: Imre Kaloz + +--- a/init/do_mounts.c ++++ b/init/do_mounts.c +@@ -628,6 +628,7 @@ int __init init_rootfs(void) + if (err) + return err; + ++#if 0 + if (IS_ENABLED(CONFIG_TMPFS) && !saved_root_name[0] && + (!root_fs_names || strstr(root_fs_names, "tmpfs"))) { + err = shmem_init(); +@@ -635,6 +636,9 @@ int __init init_rootfs(void) + } else { + err = init_ramfs_fs(); + } ++#else ++ err = init_ramfs_fs(); ++#endif + + if (err) + unregister_filesystem(&rootfs_fs_type); diff --git a/target/linux/generic/patches-4.1/021-ssb_sprom.patch b/target/linux/generic/patches-4.1/021-ssb_sprom.patch new file mode 100644 index 0000000..52d8080 --- /dev/null +++ b/target/linux/generic/patches-4.1/021-ssb_sprom.patch @@ -0,0 +1,32 @@ +--- a/include/linux/ssb/ssb.h ++++ b/include/linux/ssb/ssb.h +@@ -29,10 +29,13 @@ struct ssb_sprom { + u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */ + u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */ + u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */ ++ u8 et2mac[6] __aligned(sizeof(u16)); /* MAC address for extra Ethernet */ + u8 et0phyaddr; /* MII address for enet0 */ + u8 et1phyaddr; /* MII address for enet1 */ ++ u8 et2phyaddr; /* MII address for enet2 */ + u8 et0mdcport; /* MDIO for enet0 */ + u8 et1mdcport; /* MDIO for enet1 */ ++ u8 et2mdcport; /* MDIO for enet2 */ + u16 dev_id; /* Device ID overriding e.g. PCI ID */ + u16 board_rev; /* Board revision number from SPROM. */ + u16 board_num; /* Board number from SPROM. */ +@@ -88,11 +91,14 @@ struct ssb_sprom { + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */ + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */ + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */ ++ u32 boardflags; ++ u32 boardflags2; ++ u32 boardflags3; ++ /* TODO: Switch all drivers to new u32 fields and drop below ones */ + u16 boardflags_lo; /* Board flags (bits 0-15) */ + u16 boardflags_hi; /* Board flags (bits 16-31) */ + u16 boardflags2_lo; /* Board flags (bits 32-47) */ + u16 boardflags2_hi; /* Board flags (bits 48-63) */ +- /* TODO store board flags in a single u64 */ + + struct ssb_sprom_core_pwr_info core_pwr_info[4]; + diff --git a/target/linux/generic/patches-4.1/022-bcma-from-4.2.patch b/target/linux/generic/patches-4.1/022-bcma-from-4.2.patch new file mode 100644 index 0000000..ba3df18 --- /dev/null +++ b/target/linux/generic/patches-4.1/022-bcma-from-4.2.patch @@ -0,0 +1,86 @@ +--- a/drivers/bcma/driver_gpio.c ++++ b/drivers/bcma/driver_gpio.c +@@ -226,6 +226,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c + chip->of_node = cc->core->dev.of_node; + #endif + switch (bus->chipinfo.id) { ++ case BCMA_CHIP_ID_BCM4707: + case BCMA_CHIP_ID_BCM5357: + case BCMA_CHIP_ID_BCM53572: + chip->ngpio = 32; +@@ -235,16 +236,17 @@ int bcma_gpio_init(struct bcma_drv_cc *c + } + + /* +- * On MIPS we register GPIO devices (LEDs, buttons) using absolute GPIO +- * pin numbers. We don't have Device Tree there and we can't really use +- * relative (per chip) numbers. +- * So let's use predictable base for BCM47XX and "random" for all other. ++ * Register SoC GPIO devices with absolute GPIO pin base. ++ * On MIPS, we don't have Device Tree and we can't use relative (per chip) ++ * GPIO numbers. ++ * On some ARM devices, user space may want to access some system GPIO ++ * pins directly, which is easier to do with a predictable GPIO base. + */ +-#if IS_BUILTIN(CONFIG_BCM47XX) +- chip->base = bus->num * BCMA_GPIO_MAX_PINS; +-#else +- chip->base = -1; +-#endif ++ if (IS_BUILTIN(CONFIG_BCM47XX) || ++ cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) ++ chip->base = bus->num * BCMA_GPIO_MAX_PINS; ++ else ++ chip->base = -1; + + err = bcma_gpio_irq_domain_init(cc); + if (err) +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -29,12 +29,6 @@ config BCMA_HOST_PCI + select BCMA_DRIVER_PCI + default y + +-config BCMA_DRIVER_PCI_HOSTMODE +- bool "Driver for PCI core working in hostmode" +- depends on BCMA && MIPS && BCMA_HOST_PCI +- help +- PCI core hostmode operation (external PCI bus). +- + config BCMA_HOST_SOC + bool "Support for BCMA in a SoC" + depends on BCMA +@@ -61,6 +55,12 @@ config BCMA_DRIVER_PCI + This driver is also prerequisite for a hostmode PCIe core + support. + ++config BCMA_DRIVER_PCI_HOSTMODE ++ bool "Driver for PCI core working in hostmode" ++ depends on BCMA && MIPS && BCMA_DRIVER_PCI ++ help ++ PCI core hostmode operation (external PCI bus). ++ + config BCMA_DRIVER_MIPS + bool "BCMA Broadcom MIPS core driver" + depends on BCMA && MIPS +--- a/include/linux/bcma/bcma_driver_pci.h ++++ b/include/linux/bcma/bcma_driver_pci.h +@@ -246,7 +246,18 @@ static inline void bcma_core_pci_power_s + } + #endif + ++#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE + extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev); + extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev); ++#else ++static inline int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev) ++{ ++ return -ENOTSUPP; ++} ++static inline int bcma_core_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ return -ENOTSUPP; ++} ++#endif + + #endif /* LINUX_BCMA_DRIVER_PCI_H_ */ diff --git a/target/linux/generic/patches-4.1/023-bcma-from-4.4.patch b/target/linux/generic/patches-4.1/023-bcma-from-4.4.patch new file mode 100644 index 0000000..5704081 --- /dev/null +++ b/target/linux/generic/patches-4.1/023-bcma-from-4.4.patch @@ -0,0 +1,26 @@ +commit 55acca90da52b85299c033354e51ddaa7b73e019 +Author: Hante Meuleman +Date: Fri Sep 18 22:08:17 2015 +0200 + + brcmfmac: Add support for the BCM4365 and BCM4366 PCIE devices. + + This patch adds support for the BCM4365 and BCM4366 11ac Wave2 + PCIE devices. + + Reviewed-by: Arend Van Spriel + Reviewed-by: Pieter-Paul Giesberts + Signed-off-by: Hante Meuleman + Signed-off-by: Arend van Spriel + Signed-off-by: Kalle Valo + +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -151,6 +151,8 @@ struct bcma_host_ops { + #define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */ + #define BCMA_CORE_USB30_DEV 0x83D + #define BCMA_CORE_ARM_CR4 0x83E ++#define BCMA_CORE_ARM_CA7 0x847 ++#define BCMA_CORE_SYS_MEM 0x849 + #define BCMA_CORE_DEFAULT 0xFFF + + #define BCMA_MAX_NR_CORES 16 diff --git a/target/linux/generic/patches-4.1/050-backport_netfilter_rtcache.patch b/target/linux/generic/patches-4.1/050-backport_netfilter_rtcache.patch new file mode 100644 index 0000000..9a6d837 --- /dev/null +++ b/target/linux/generic/patches-4.1/050-backport_netfilter_rtcache.patch @@ -0,0 +1,505 @@ +Subject: netfilter: conntrack: cache route for forwarded connections + +... to avoid per-packet FIB lookup if possible. + +The cached dst is re-used provided the input interface +is the same as that of the previous packet in the same direction. + +If not, the cached dst is invalidated. + +For ipv6 we also need to store sernum, else dst_check doesn't work, +pointed out by Eric Dumazet. + +This should speed up forwarding when conntrack is already in use +anyway, especially when using reverse path filtering -- active RPF +enforces two FIB lookups for each packet. + +Before the routing cache removal this didn't matter since RPF was performed +only when route cache didn't yield a result; but without route cache it +comes at higher price. + +Julian Anastasov suggested to add NETDEV_UNREGISTER handler to +avoid holding on to dsts of 'frozen' conntracks. + +Signed-off-by: Florian Westphal + +--- a/include/net/netfilter/nf_conntrack_extend.h ++++ b/include/net/netfilter/nf_conntrack_extend.h +@@ -30,6 +30,9 @@ enum nf_ct_ext_id { + #if IS_ENABLED(CONFIG_NETFILTER_SYNPROXY) + NF_CT_EXT_SYNPROXY, + #endif ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_RTCACHE) ++ NF_CT_EXT_RTCACHE, ++#endif + NF_CT_EXT_NUM, + }; + +@@ -43,6 +46,7 @@ enum nf_ct_ext_id { + #define NF_CT_EXT_TIMEOUT_TYPE struct nf_conn_timeout + #define NF_CT_EXT_LABELS_TYPE struct nf_conn_labels + #define NF_CT_EXT_SYNPROXY_TYPE struct nf_conn_synproxy ++#define NF_CT_EXT_RTCACHE_TYPE struct nf_conn_rtcache + + /* Extensions: optional stuff which isn't permanently in struct. */ + struct nf_ct_ext { +--- /dev/null ++++ b/include/net/netfilter/nf_conntrack_rtcache.h +@@ -0,0 +1,34 @@ ++#include ++#include ++#include ++ ++struct dst_entry; ++ ++struct nf_conn_dst_cache { ++ struct dst_entry *dst; ++ int iif; ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ u32 cookie; ++#endif ++ ++}; ++ ++struct nf_conn_rtcache { ++ struct nf_conn_dst_cache cached_dst[IP_CT_DIR_MAX]; ++}; ++ ++static inline ++struct nf_conn_rtcache *nf_ct_rtcache_find(const struct nf_conn *ct) ++{ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_RTCACHE) ++ return nf_ct_ext_find(ct, NF_CT_EXT_RTCACHE); ++#else ++ return NULL; ++#endif ++} ++ ++static inline int nf_conn_rtcache_iif_get(const struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ return rtc->cached_dst[dir].iif; ++} +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -106,6 +106,18 @@ config NF_CONNTRACK_EVENTS + + If unsure, say `N'. + ++config NF_CONNTRACK_RTCACHE ++ tristate "Cache route entries in conntrack objects" ++ depends on NETFILTER_ADVANCED ++ depends on NF_CONNTRACK ++ help ++ If this option is enabled, the connection tracking code will ++ cache routing information for each connection that is being ++ forwarded, at a cost of 32 bytes per conntrack object. ++ ++ To compile it as a module, choose M here. If unsure, say N. ++ The module will be called nf_conntrack_rtcache. ++ + config NF_CONNTRACK_TIMEOUT + bool 'Connection tracking timeout' + depends on NETFILTER_ADVANCED +--- a/net/netfilter/Makefile ++++ b/net/netfilter/Makefile +@@ -18,6 +18,9 @@ obj-$(CONFIG_NETFILTER_NETLINK_LOG) += n + # connection tracking + obj-$(CONFIG_NF_CONNTRACK) += nf_conntrack.o + ++# optional conntrack route cache extension ++obj-$(CONFIG_NF_CONNTRACK_RTCACHE) += nf_conntrack_rtcache.o ++ + # SCTP protocol connection tracking + obj-$(CONFIG_NF_CT_PROTO_DCCP) += nf_conntrack_proto_dccp.o + obj-$(CONFIG_NF_CT_PROTO_GRE) += nf_conntrack_proto_gre.o +--- /dev/null ++++ b/net/netfilter/nf_conntrack_rtcache.c +@@ -0,0 +1,387 @@ ++/* route cache for netfilter. ++ * ++ * (C) 2014 Red Hat GmbH ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++#include ++#endif ++ ++static void __nf_conn_rtcache_destroy(struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ struct dst_entry *dst = rtc->cached_dst[dir].dst; ++ ++ dst_release(dst); ++} ++ ++static void nf_conn_rtcache_destroy(struct nf_conn *ct) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ ++ if (!rtc) ++ return; ++ ++ __nf_conn_rtcache_destroy(rtc, IP_CT_DIR_ORIGINAL); ++ __nf_conn_rtcache_destroy(rtc, IP_CT_DIR_REPLY); ++} ++ ++static void nf_ct_rtcache_ext_add(struct nf_conn *ct) ++{ ++ struct nf_conn_rtcache *rtc; ++ ++ rtc = nf_ct_ext_add(ct, NF_CT_EXT_RTCACHE, GFP_ATOMIC); ++ if (rtc) { ++ rtc->cached_dst[IP_CT_DIR_ORIGINAL].iif = -1; ++ rtc->cached_dst[IP_CT_DIR_ORIGINAL].dst = NULL; ++ rtc->cached_dst[IP_CT_DIR_REPLY].iif = -1; ++ rtc->cached_dst[IP_CT_DIR_REPLY].dst = NULL; ++ } ++} ++ ++static struct nf_conn_rtcache *nf_ct_rtcache_find_usable(struct nf_conn *ct) ++{ ++ if (nf_ct_is_untracked(ct)) ++ return NULL; ++ return nf_ct_rtcache_find(ct); ++} ++ ++static struct dst_entry * ++nf_conn_rtcache_dst_get(const struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ return rtc->cached_dst[dir].dst; ++} ++ ++static u32 nf_rtcache_get_cookie(int pf, const struct dst_entry *dst) ++{ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ if (pf == NFPROTO_IPV6) { ++ const struct rt6_info *rt = (const struct rt6_info *)dst; ++ ++ if (rt->rt6i_node) ++ return (u32)rt->rt6i_node->fn_sernum; ++ } ++#endif ++ return 0; ++} ++ ++static void nf_conn_rtcache_dst_set(int pf, ++ struct nf_conn_rtcache *rtc, ++ struct dst_entry *dst, ++ enum ip_conntrack_dir dir, int iif) ++{ ++ if (rtc->cached_dst[dir].iif != iif) ++ rtc->cached_dst[dir].iif = iif; ++ ++ if (rtc->cached_dst[dir].dst != dst) { ++ struct dst_entry *old; ++ ++ dst_hold(dst); ++ ++ old = xchg(&rtc->cached_dst[dir].dst, dst); ++ dst_release(old); ++ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ if (pf == NFPROTO_IPV6) ++ rtc->cached_dst[dir].cookie = ++ nf_rtcache_get_cookie(pf, dst); ++#endif ++ } ++} ++ ++static void nf_conn_rtcache_dst_obsolete(struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ struct dst_entry *old; ++ ++ pr_debug("Invalidate iif %d for dir %d on cache %p\n", ++ rtc->cached_dst[dir].iif, dir, rtc); ++ ++ old = xchg(&rtc->cached_dst[dir].dst, NULL); ++ dst_release(old); ++ rtc->cached_dst[dir].iif = -1; ++} ++ ++static unsigned int nf_rtcache_in(const struct nf_hook_ops *ops, ++ struct sk_buff *skb, ++ const struct nf_hook_state *state) ++{ ++ struct nf_conn_rtcache *rtc; ++ enum ip_conntrack_info ctinfo; ++ enum ip_conntrack_dir dir; ++ struct dst_entry *dst; ++ struct nf_conn *ct; ++ int iif; ++ u32 cookie; ++ ++ if (skb_dst(skb) || skb->sk) ++ return NF_ACCEPT; ++ ++ ct = nf_ct_get(skb, &ctinfo); ++ if (!ct) ++ return NF_ACCEPT; ++ ++ rtc = nf_ct_rtcache_find_usable(ct); ++ if (!rtc) ++ return NF_ACCEPT; ++ ++ /* if iif changes, don't use cache and let ip stack ++ * do route lookup. ++ * ++ * If rp_filter is enabled it might toss skb, so ++ * we don't want to avoid these checks. ++ */ ++ dir = CTINFO2DIR(ctinfo); ++ iif = nf_conn_rtcache_iif_get(rtc, dir); ++ if (state->in->ifindex != iif) { ++ pr_debug("ct %p, iif %d, cached iif %d, skip cached entry\n", ++ ct, iif, state->in->ifindex); ++ return NF_ACCEPT; ++ } ++ dst = nf_conn_rtcache_dst_get(rtc, dir); ++ if (dst == NULL) ++ return NF_ACCEPT; ++ ++ cookie = nf_rtcache_get_cookie(ops->pf, dst); ++ ++ dst = dst_check(dst, cookie); ++ pr_debug("obtained dst %p for skb %p, cookie %d\n", dst, skb, cookie); ++ if (likely(dst)) ++ skb_dst_set_noref(skb, dst); ++ else ++ nf_conn_rtcache_dst_obsolete(rtc, dir); ++ ++ return NF_ACCEPT; ++} ++ ++static unsigned int nf_rtcache_forward(const struct nf_hook_ops *ops, ++ struct sk_buff *skb, ++ const struct nf_hook_state *state) ++{ ++ struct nf_conn_rtcache *rtc; ++ enum ip_conntrack_info ctinfo; ++ enum ip_conntrack_dir dir; ++ struct nf_conn *ct; ++ struct dst_entry *dst = skb_dst(skb); ++ int iif; ++ ++ ct = nf_ct_get(skb, &ctinfo); ++ if (!ct) ++ return NF_ACCEPT; ++ ++ if (dst && dst_xfrm(dst)) ++ return NF_ACCEPT; ++ ++ if (!nf_ct_is_confirmed(ct)) { ++ if (WARN_ON(nf_ct_rtcache_find(ct))) ++ return NF_ACCEPT; ++ nf_ct_rtcache_ext_add(ct); ++ return NF_ACCEPT; ++ } ++ ++ rtc = nf_ct_rtcache_find_usable(ct); ++ if (!rtc) ++ return NF_ACCEPT; ++ ++ dir = CTINFO2DIR(ctinfo); ++ iif = nf_conn_rtcache_iif_get(rtc, dir); ++ pr_debug("ct %p, skb %p, dir %d, iif %d, cached iif %d\n", ++ ct, skb, dir, iif, state->in->ifindex); ++ if (likely(state->in->ifindex == iif)) ++ return NF_ACCEPT; ++ ++ nf_conn_rtcache_dst_set(ops->pf, rtc, skb_dst(skb), dir, state->in->ifindex); ++ return NF_ACCEPT; ++} ++ ++static int nf_rtcache_dst_remove(struct nf_conn *ct, void *data) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ struct net_device *dev = data; ++ ++ if (!rtc) ++ return 0; ++ ++ if (dev->ifindex == rtc->cached_dst[IP_CT_DIR_ORIGINAL].iif || ++ dev->ifindex == rtc->cached_dst[IP_CT_DIR_REPLY].iif) { ++ nf_conn_rtcache_dst_obsolete(rtc, IP_CT_DIR_ORIGINAL); ++ nf_conn_rtcache_dst_obsolete(rtc, IP_CT_DIR_REPLY); ++ } ++ ++ return 0; ++} ++ ++static int nf_rtcache_netdev_event(struct notifier_block *this, ++ unsigned long event, void *ptr) ++{ ++ struct net_device *dev = netdev_notifier_info_to_dev(ptr); ++ struct net *net = dev_net(dev); ++ ++ if (event == NETDEV_DOWN) ++ nf_ct_iterate_cleanup(net, nf_rtcache_dst_remove, dev, 0, 0); ++ ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block nf_rtcache_notifier = { ++ .notifier_call = nf_rtcache_netdev_event, ++}; ++ ++static struct nf_hook_ops rtcache_ops[] = { ++ { ++ .hook = nf_rtcache_in, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV4, ++ .hooknum = NF_INET_PRE_ROUTING, ++ .priority = NF_IP_PRI_LAST, ++ }, ++ { ++ .hook = nf_rtcache_forward, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV4, ++ .hooknum = NF_INET_FORWARD, ++ .priority = NF_IP_PRI_LAST, ++ }, ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ { ++ .hook = nf_rtcache_in, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV6, ++ .hooknum = NF_INET_PRE_ROUTING, ++ .priority = NF_IP_PRI_LAST, ++ }, ++ { ++ .hook = nf_rtcache_forward, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV6, ++ .hooknum = NF_INET_FORWARD, ++ .priority = NF_IP_PRI_LAST, ++ }, ++#endif ++}; ++ ++static struct nf_ct_ext_type rtcache_extend __read_mostly = { ++ .len = sizeof(struct nf_conn_rtcache), ++ .align = __alignof__(struct nf_conn_rtcache), ++ .id = NF_CT_EXT_RTCACHE, ++ .destroy = nf_conn_rtcache_destroy, ++}; ++ ++static int __init nf_conntrack_rtcache_init(void) ++{ ++ int ret = nf_ct_extend_register(&rtcache_extend); ++ ++ if (ret < 0) { ++ pr_err("nf_conntrack_rtcache: Unable to register extension\n"); ++ return ret; ++ } ++ ++ ret = nf_register_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ if (ret < 0) { ++ nf_ct_extend_unregister(&rtcache_extend); ++ return ret; ++ } ++ ++ ret = register_netdevice_notifier(&nf_rtcache_notifier); ++ if (ret) { ++ nf_unregister_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ nf_ct_extend_unregister(&rtcache_extend); ++ } ++ ++ return ret; ++} ++ ++static int nf_rtcache_ext_remove(struct nf_conn *ct, void *data) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ ++ return rtc != NULL; ++} ++ ++static bool __exit nf_conntrack_rtcache_wait_for_dying(struct net *net) ++{ ++ bool wait = false; ++ int cpu; ++ ++ for_each_possible_cpu(cpu) { ++ struct nf_conntrack_tuple_hash *h; ++ struct hlist_nulls_node *n; ++ struct nf_conn *ct; ++ struct ct_pcpu *pcpu = per_cpu_ptr(net->ct.pcpu_lists, cpu); ++ ++ rcu_read_lock(); ++ spin_lock_bh(&pcpu->lock); ++ ++ hlist_nulls_for_each_entry(h, n, &pcpu->dying, hnnode) { ++ ct = nf_ct_tuplehash_to_ctrack(h); ++ if (nf_ct_rtcache_find(ct) != NULL) { ++ wait = true; ++ break; ++ } ++ } ++ spin_unlock_bh(&pcpu->lock); ++ rcu_read_unlock(); ++ } ++ ++ return wait; ++} ++ ++static void __exit nf_conntrack_rtcache_fini(void) ++{ ++ struct net *net; ++ int count = 0; ++ ++ /* remove hooks so no new connections get rtcache extension */ ++ nf_unregister_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ ++ synchronize_net(); ++ ++ unregister_netdevice_notifier(&nf_rtcache_notifier); ++ ++ rtnl_lock(); ++ ++ /* zap all conntracks with rtcache extension */ ++ for_each_net(net) ++ nf_ct_iterate_cleanup(net, nf_rtcache_ext_remove, NULL, 0, 0); ++ ++ for_each_net(net) { ++ /* .. and make sure they're gone from dying list, too */ ++ while (nf_conntrack_rtcache_wait_for_dying(net)) { ++ msleep(200); ++ WARN_ONCE(++count > 25, "Waiting for all rtcache conntracks to go away\n"); ++ } ++ } ++ ++ rtnl_unlock(); ++ synchronize_net(); ++ nf_ct_extend_unregister(&rtcache_extend); ++} ++module_init(nf_conntrack_rtcache_init); ++module_exit(nf_conntrack_rtcache_fini); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Florian Westphal "); ++MODULE_DESCRIPTION("Conntrack route cache extension"); diff --git a/target/linux/generic/patches-4.1/060-mips_decompressor_memmove.patch b/target/linux/generic/patches-4.1/060-mips_decompressor_memmove.patch new file mode 100644 index 0000000..d215b80 --- /dev/null +++ b/target/linux/generic/patches-4.1/060-mips_decompressor_memmove.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/boot/compressed/string.c ++++ b/arch/mips/boot/compressed/string.c +@@ -26,3 +26,19 @@ void *memset(void *s, int c, size_t n) + ss[i] = c; + return s; + } ++ ++void *memmove(void *__dest, __const void *__src, size_t count) ++{ ++ unsigned char *d = __dest; ++ const unsigned char *s = __src; ++ ++ if (__dest == __src) ++ return __dest; ++ ++ if (__dest < __src) ++ return memcpy(__dest, __src, count); ++ ++ while (count--) ++ d[count] = s[count]; ++ return __dest; ++} diff --git a/target/linux/generic/patches-4.1/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch b/target/linux/generic/patches-4.1/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch new file mode 100644 index 0000000..a3d9fd6 --- /dev/null +++ b/target/linux/generic/patches-4.1/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch @@ -0,0 +1,24 @@ +From: Felix Fietkau +Date: Mon, 13 Apr 2015 15:54:04 +0200 +Subject: [PATCH] bgmac: fix MAC soft-reset bit for corerev > 4 + +Only core revisions older than 4 use BGMAC_CMDCFG_SR_REV0 + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -198,9 +198,9 @@ + #define BGMAC_CMDCFG_TAI 0x00000200 + #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ + #define BGMAC_CMDCFG_HD_SHIFT 10 +-#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */ +-#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */ +-#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) ++#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */ ++#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */ ++#define BGMAC_CMDCFG_SR(rev) ((rev >= 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) + #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ + #define BGMAC_CMDCFG_AE 0x00400000 + #define BGMAC_CMDCFG_CFE 0x00800000 diff --git a/target/linux/generic/patches-4.1/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch b/target/linux/generic/patches-4.1/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch new file mode 100644 index 0000000..2a913a6 --- /dev/null +++ b/target/linux/generic/patches-4.1/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch @@ -0,0 +1,28 @@ +From: Felix Fietkau +Date: Mon, 13 Apr 2015 15:56:26 +0200 +Subject: [PATCH] bgmac: reset all 4 GMAC cores on init + +On a BCM4709 based device, I found that GMAC cores may be enabled at +probe time, but only become usable after a full reset. +Disable cores before re-enabling them to ensure that they are properly +reset. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1623,8 +1623,11 @@ static int bgmac_probe(struct bcma_devic + ns_core = bcma_find_core_unit(core->bus, + BCMA_CORE_MAC_GBIT, + ns_gmac); +- if (ns_core && !bcma_core_is_enabled(ns_core)) +- bcma_core_enable(ns_core, 0); ++ if (!ns_core) ++ continue; ++ ++ bcma_core_disable(ns_core, 0); ++ bcma_core_enable(ns_core, 0); + } + } + diff --git a/target/linux/generic/patches-4.1/080-ipv6-ip6_fragment-fix-headroom-tests-and-skb-leak.patch b/target/linux/generic/patches-4.1/080-ipv6-ip6_fragment-fix-headroom-tests-and-skb-leak.patch new file mode 100644 index 0000000..7de8987 --- /dev/null +++ b/target/linux/generic/patches-4.1/080-ipv6-ip6_fragment-fix-headroom-tests-and-skb-leak.patch @@ -0,0 +1,101 @@ +From: Florian Westphal +Date: Thu, 17 Sep 2015 11:24:48 +0100 +Subject: [PATCH] ipv6: ip6_fragment: fix headroom tests and skb leak + +David Woodhouse reports skb_under_panic when we try to push ethernet +header to fragmented ipv6 skbs: + + skbuff: skb_under_panic: text:c1277f1e len:1294 put:14 head:dec98000 + data:dec97ffc tail:0xdec9850a end:0xdec98f40 dev:br-lan +[..] +ip6_finish_output2+0x196/0x4da + +David further debugged this: + [..] offending fragments were arriving here with skb_headroom(skb)==10. + Which is reasonable, being the Solos ADSL card's header of 8 bytes + followed by 2 bytes of PPP frame type. + +The problem is that if netfilter ipv6 defragmentation is used, skb_cow() +in ip6_forward will only see reassembled skb. + +Therefore, headroom is overestimated by 8 bytes (we pulled fragment +header) and we don't check the skbs in the frag_list either. + +We can't do these checks in netfilter defrag since outdev isn't known yet. + +Furthermore, existing tests in ip6_fragment did not consider the fragment +or ipv6 header size when checking headroom of the fraglist skbs. + +While at it, also fix a skb leak on memory allocation -- ip6_fragment +must consume the skb. + +I tested this e1000 driver hacked to not allocate additional headroom +(we end up in slowpath, since LL_RESERVED_SPACE is 16). + +If 2 bytes of headroom are allocated, fastpath is taken (14 byte +ethernet header was pulled, so 16 byte headroom available in all +fragments). + +Reported-by: David Woodhouse +Diagnosed-by: David Woodhouse +Signed-off-by: Florian Westphal +Closes 20532 +--- + +--- a/net/ipv6/ip6_output.c ++++ b/net/ipv6/ip6_output.c +@@ -584,20 +584,22 @@ int ip6_fragment(struct sock *sk, struct + } + mtu -= hlen + sizeof(struct frag_hdr); + ++ hroom = LL_RESERVED_SPACE(rt->dst.dev); + if (skb_has_frag_list(skb)) { + int first_len = skb_pagelen(skb); + struct sk_buff *frag2; + + if (first_len - hlen > mtu || + ((first_len - hlen) & 7) || +- skb_cloned(skb)) ++ skb_cloned(skb) || ++ skb_headroom(skb) < (hroom + sizeof(struct frag_hdr))) + goto slow_path; + + skb_walk_frags(skb, frag) { + /* Correct geometry. */ + if (frag->len > mtu || + ((frag->len & 7) && frag->next) || +- skb_headroom(frag) < hlen) ++ skb_headroom(frag) < (hlen + hroom + sizeof(struct frag_hdr))) + goto slow_path_clean; + + /* Partially cloned skb? */ +@@ -614,8 +616,6 @@ int ip6_fragment(struct sock *sk, struct + + err = 0; + offset = 0; +- frag = skb_shinfo(skb)->frag_list; +- skb_frag_list_init(skb); + /* BUILD HEADER */ + + *prevhdr = NEXTHDR_FRAGMENT; +@@ -623,8 +623,11 @@ int ip6_fragment(struct sock *sk, struct + if (!tmp_hdr) { + IP6_INC_STATS(net, ip6_dst_idev(skb_dst(skb)), + IPSTATS_MIB_FRAGFAILS); +- return -ENOMEM; ++ err = -ENOMEM; ++ goto fail; + } ++ frag = skb_shinfo(skb)->frag_list; ++ skb_frag_list_init(skb); + + __skb_pull(skb, hlen); + fh = (struct frag_hdr *)__skb_push(skb, sizeof(struct frag_hdr)); +@@ -722,7 +725,6 @@ slow_path: + */ + + *prevhdr = NEXTHDR_FRAGMENT; +- hroom = LL_RESERVED_SPACE(rt->dst.dev); + troom = rt->dst.dev->needed_tailroom; + + /* diff --git a/target/linux/generic/patches-4.1/081-solos-pci-Increase-headroom-on-received-packets.patch b/target/linux/generic/patches-4.1/081-solos-pci-Increase-headroom-on-received-packets.patch new file mode 100644 index 0000000..605f57a --- /dev/null +++ b/target/linux/generic/patches-4.1/081-solos-pci-Increase-headroom-on-received-packets.patch @@ -0,0 +1,54 @@ +From: David Woodhouse +Date: Thu, 17 Sep 2015 11:19:53 +0100 +Subject: [PATCH] solos-pci: Increase headroom on received packets +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +A comment in include/linux/skbuff.h says that: + + * Various parts of the networking layer expect at least 32 bytes of + * headroom, you should not reduce this. + +This was demonstrated by a panic when handling fragmented IPv6 packets: +http://marc.info/?l=linux-netdev&m=144236093519172&w=2 + +It's not entirely clear if that comment is still valid — and if it is, +perhaps netif_rx() ought to be enforcing it with a warning. + +But either way, it is rather stupid from a performance point of view +for us to be receiving packets into a buffer which doesn't have enough +room to prepend an Ethernet header — it means that *every* incoming +packet is going to be need to be reallocated. So let's fix that. + +Signed-off-by: David Woodhouse +--- + +--- a/drivers/atm/solos-pci.c ++++ b/drivers/atm/solos-pci.c +@@ -805,7 +805,12 @@ static void solos_bh(unsigned long card_ + continue; + } + +- skb = alloc_skb(size + 1, GFP_ATOMIC); ++ /* Use netdev_alloc_skb() because it adds NET_SKB_PAD of ++ * headroom, and ensures we can route packets back out an ++ * Ethernet interface (for example) without having to ++ * reallocate. Adding NET_IP_ALIGN also ensures that both ++ * PPPoATM and PPPoEoBR2684 packets end up aligned. */ ++ skb = netdev_alloc_skb_ip_align(NULL, size + 1); + if (!skb) { + if (net_ratelimit()) + dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n"); +@@ -869,7 +874,10 @@ static void solos_bh(unsigned long card_ + /* Allocate RX skbs for any ports which need them */ + if (card->using_dma && card->atmdev[port] && + !card->rx_skb[port]) { +- struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC); ++ /* Unlike the MMIO case (qv) we can't add NET_IP_ALIGN ++ * here; the FPGA can only DMA to addresses which are ++ * aligned to 4 bytes. */ ++ struct sk_buff *skb = dev_alloc_skb(RX_DMA_SIZE); + if (skb) { + SKB_CB(skb)->dma_addr = + dma_map_single(&card->dev->dev, skb->data, diff --git a/target/linux/generic/patches-4.1/091-mtd-spi-nor-add-support-Spansion_S25FL164K b/target/linux/generic/patches-4.1/091-mtd-spi-nor-add-support-Spansion_S25FL164K new file mode 100644 index 0000000..c8aa336 --- /dev/null +++ b/target/linux/generic/patches-4.1/091-mtd-spi-nor-add-support-Spansion_S25FL164K @@ -0,0 +1,10 @@ +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -614,6 +614,7 @@ static const struct spi_device_id spi_no + { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, + { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, + { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, 0) }, ++ { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, + + /* SST -- large erase sizes are "overlays", "sectors" are 4K */ + { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, diff --git a/target/linux/generic/patches-4.1/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch b/target/linux/generic/patches-4.1/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch new file mode 100644 index 0000000..d0bea94 --- /dev/null +++ b/target/linux/generic/patches-4.1/095-api-fix-compatibility-of-linux-in.h-with-netinet-in..patch @@ -0,0 +1,146 @@ +From 279c6c7fa64f5763e6b9f05e7ab3840092e702e7 Mon Sep 17 00:00:00 2001 +From: Stephen Hemminger +Date: Mon, 29 Jun 2015 14:57:48 -1000 +Subject: [PATCH] api: fix compatibility of linux/in.h with netinet/in.h + +u +This fixes breakage to iproute2 build with recent kernel headers +caused by: + commit a263653ed798216c0069922d7b5237ca49436007 + Author: Pablo Neira Ayuso + Date: Wed Jun 17 10:28:27 2015 -0500 + + netfilter: don't pull include/linux/netfilter.h from netns headers + +The issue is that definitions in linux/in.h overlap with those +in netinet/in.h. This patch solves this by introducing the same +mechanism as was used to solve the same problem with linux/in6.h + +Signed-off-by: Stephen Hemminger +Signed-off-by: David S. Miller +--- + include/uapi/linux/in.h | 16 +++++++++++++--- + include/uapi/linux/libc-compat.h | 22 ++++++++++++++++++++++ + 2 files changed, 35 insertions(+), 3 deletions(-) + +--- a/include/uapi/linux/in.h ++++ b/include/uapi/linux/in.h +@@ -19,8 +19,10 @@ + #define _UAPI_LINUX_IN_H + + #include ++#include + #include + ++#if __UAPI_DEF_IN_IPPROTO + /* Standard well-defined IP protocols. */ + enum { + IPPROTO_IP = 0, /* Dummy protocol for TCP */ +@@ -73,12 +75,14 @@ enum { + #define IPPROTO_RAW IPPROTO_RAW + IPPROTO_MAX + }; ++#endif + +- ++#if __UAPI_DEF_IN_ADDR + /* Internet address. */ + struct in_addr { + __be32 s_addr; + }; ++#endif + + #define IP_TOS 1 + #define IP_TTL 2 +@@ -155,6 +159,7 @@ struct in_addr { + + /* Request struct for multicast socket ops */ + ++#if __UAPI_DEF_IP_MREQ + struct ip_mreq { + struct in_addr imr_multiaddr; /* IP multicast address of group */ + struct in_addr imr_interface; /* local IP address of interface */ +@@ -206,14 +211,18 @@ struct group_filter { + #define GROUP_FILTER_SIZE(numsrc) \ + (sizeof(struct group_filter) - sizeof(struct __kernel_sockaddr_storage) \ + + (numsrc) * sizeof(struct __kernel_sockaddr_storage)) ++#endif + ++#if __UAPI_DEF_IN_PKTINFO + struct in_pktinfo { + int ipi_ifindex; + struct in_addr ipi_spec_dst; + struct in_addr ipi_addr; + }; ++#endif + + /* Structure describing an Internet (IP) socket address. */ ++#if __UAPI_DEF_SOCKADDR_IN + #define __SOCK_SIZE__ 16 /* sizeof(struct sockaddr) */ + struct sockaddr_in { + __kernel_sa_family_t sin_family; /* Address family */ +@@ -225,8 +234,9 @@ struct sockaddr_in { + sizeof(unsigned short int) - sizeof(struct in_addr)]; + }; + #define sin_zero __pad /* for BSD UNIX comp. -FvK */ ++#endif + +- ++#if __UAPI_DEF_IN_CLASS + /* + * Definitions of the bits in an Internet address integer. + * On subnets, host and network parts are found according +@@ -277,7 +287,7 @@ struct sockaddr_in { + #define INADDR_ALLHOSTS_GROUP 0xe0000001U /* 224.0.0.1 */ + #define INADDR_ALLRTRS_GROUP 0xe0000002U /* 224.0.0.2 */ + #define INADDR_MAX_LOCAL_GROUP 0xe00000ffU /* 224.0.0.255 */ +- ++#endif + + /* contains the htonl type stuff.. */ + #include +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -56,6 +56,13 @@ + + /* GLIBC headers included first so don't define anything + * that would already be defined. */ ++#define __UAPI_DEF_IN_ADDR 0 ++#define __UAPI_DEF_IN_IPPROTO 0 ++#define __UAPI_DEF_IN_PKTINFO 0 ++#define __UAPI_DEF_IP_MREQ 0 ++#define __UAPI_DEF_SOCKADDR_IN 0 ++#define __UAPI_DEF_IN_CLASS 0 ++ + #define __UAPI_DEF_IN6_ADDR 0 + /* The exception is the in6_addr macros which must be defined + * if the glibc code didn't define them. This guard matches +@@ -78,6 +85,13 @@ + /* Linux headers included first, and we must define everything + * we need. The expectation is that glibc will check the + * __UAPI_DEF_* defines and adjust appropriately. */ ++#define __UAPI_DEF_IN_ADDR 1 ++#define __UAPI_DEF_IN_IPPROTO 1 ++#define __UAPI_DEF_IN_PKTINFO 1 ++#define __UAPI_DEF_IP_MREQ 1 ++#define __UAPI_DEF_SOCKADDR_IN 1 ++#define __UAPI_DEF_IN_CLASS 1 ++ + #define __UAPI_DEF_IN6_ADDR 1 + /* We unconditionally define the in6_addr macros and glibc must + * coordinate. */ +@@ -103,6 +117,14 @@ + * that we need. */ + #else /* !defined(__GLIBC__) */ + ++/* Definitions for in.h */ ++#define __UAPI_DEF_IN_ADDR 1 ++#define __UAPI_DEF_IN_IPPROTO 1 ++#define __UAPI_DEF_IN_PKTINFO 1 ++#define __UAPI_DEF_IP_MREQ 1 ++#define __UAPI_DEF_SOCKADDR_IN 1 ++#define __UAPI_DEF_IN_CLASS 1 ++ + /* Definitions for in6.h */ + #define __UAPI_DEF_IN6_ADDR 1 + #define __UAPI_DEF_IN6_ADDR_ALT 1 diff --git a/target/linux/generic/patches-4.1/101-pppoe-fix-disconnect-crash.patch b/target/linux/generic/patches-4.1/101-pppoe-fix-disconnect-crash.patch new file mode 100644 index 0000000..f2e6e45 --- /dev/null +++ b/target/linux/generic/patches-4.1/101-pppoe-fix-disconnect-crash.patch @@ -0,0 +1,16 @@ +Fix crash with actions performed on the underlying interface (MAC address, +MTU or link state update). This triggers pppoe_flush_dev(), which cleans up +the device without announcing it in sk->sk_state. + +Patch by Guillaume Nault (pulled from netdev@vger) + +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -313,7 +313,6 @@ static void pppoe_flush_dev(struct net_d + if (po->pppoe_dev == dev && + sk->sk_state & (PPPOX_CONNECTED | PPPOX_BOUND | PPPOX_ZOMBIE)) { + pppox_unbind_sock(sk); +- sk->sk_state = PPPOX_ZOMBIE; + sk->sk_state_change(sk); + po->pppoe_dev = NULL; + dev_put(dev); diff --git a/target/linux/generic/patches-4.1/102-ehci_hcd_ignore_oc.patch b/target/linux/generic/patches-4.1/102-ehci_hcd_ignore_oc.patch new file mode 100644 index 0000000..4da579c --- /dev/null +++ b/target/linux/generic/patches-4.1/102-ehci_hcd_ignore_oc.patch @@ -0,0 +1,82 @@ +From 1e311820ec3055e3f08e687de6564692a7cec675 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:29 +0100 +Subject: [PATCH 11/12] USB: EHCI: add ignore_oc flag to disable overcurrent + checking + +This patch adds an ignore_oc flag which can be set by EHCI controller +not supporting or wanting to disable overcurrent checking. The EHCI +platform data in include/linux/usb/ehci_pdriver.h is also augmented to +take advantage of this new flag. + +Signed-off-by: Florian Fainelli +--- + drivers/usb/host/ehci-hcd.c | 2 +- + drivers/usb/host/ehci-hub.c | 4 ++-- + drivers/usb/host/ehci-platform.c | 1 + + drivers/usb/host/ehci.h | 1 + + include/linux/usb/ehci_pdriver.h | 1 + + 5 files changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -638,7 +638,7 @@ static int ehci_run (struct usb_hcd *hcd + "USB %x.%x started, EHCI %x.%02x%s\n", + ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), + temp >> 8, temp & 0xff, +- ignore_oc ? ", overcurrent ignored" : ""); ++ (ignore_oc || ehci->ignore_oc) ? ", overcurrent ignored" : ""); + + ehci_writel(ehci, INTR_MASK, + &ehci->regs->intr_enable); /* Turn On Interrupts */ +--- a/drivers/usb/host/ehci-hub.c ++++ b/drivers/usb/host/ehci-hub.c +@@ -633,7 +633,7 @@ ehci_hub_status_data (struct usb_hcd *hc + * always set, seem to clear PORT_OCC and PORT_CSC when writing to + * PORT_POWER; that's surprising, but maybe within-spec. + */ +- if (!ignore_oc) ++ if (!ignore_oc && !ehci->ignore_oc) + mask = PORT_CSC | PORT_PEC | PORT_OCC; + else + mask = PORT_CSC | PORT_PEC; +@@ -995,7 +995,7 @@ int ehci_hub_control( + if (temp & PORT_PEC) + status |= USB_PORT_STAT_C_ENABLE << 16; + +- if ((temp & PORT_OCC) && !ignore_oc){ ++ if ((temp & PORT_OCC) && (!ignore_oc && !ehci->ignore_oc)){ + status |= USB_PORT_STAT_C_OVERCURRENT << 16; + + /* +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -264,6 +264,8 @@ static int ehci_platform_probe(struct pl + ehci->big_endian_desc = 1; + if (pdata->big_endian_mmio) + ehci->big_endian_mmio = 1; ++ if (pdata->ignore_oc) ++ ehci->ignore_oc = 1; + + #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO + if (ehci->big_endian_mmio) { +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -226,6 +226,7 @@ struct ehci_hcd { /* one per controlle + unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ + unsigned need_oc_pp_cycle:1; /* MPC834X port power */ + unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ ++ unsigned ignore_oc:1; + + /* required for usb32 quirk */ + #define OHCI_CTRL_HCFS (3 << 6) +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -49,6 +49,7 @@ struct usb_ehci_pdata { + unsigned no_io_watchdog:1; + unsigned reset_on_resume:1; + unsigned dma_mask_64:1; ++ unsigned ignore_oc:1; + + /* Turn on all power and clocks */ + int (*power_on)(struct platform_device *pdev); diff --git a/target/linux/generic/patches-4.1/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch b/target/linux/generic/patches-4.1/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch new file mode 100644 index 0000000..9d32777 --- /dev/null +++ b/target/linux/generic/patches-4.1/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch @@ -0,0 +1,86 @@ +From: Felix Fietkau +Date: Fri, 10 Apr 2015 13:35:29 +0200 +Subject: [PATCH] jffs2: use .rename2 and add RENAME_WHITEOUT support + +It is required for renames on overlayfs + +Signed-off-by: Felix Fietkau +--- + +--- a/fs/jffs2/dir.c ++++ b/fs/jffs2/dir.c +@@ -35,7 +35,7 @@ static int jffs2_mkdir (struct inode *,s + static int jffs2_rmdir (struct inode *,struct dentry *); + static int jffs2_mknod (struct inode *,struct dentry *,umode_t,dev_t); + static int jffs2_rename (struct inode *, struct dentry *, +- struct inode *, struct dentry *); ++ struct inode *, struct dentry *, unsigned int); + + const struct file_operations jffs2_dir_operations = + { +@@ -57,7 +57,7 @@ const struct inode_operations jffs2_dir_ + .mkdir = jffs2_mkdir, + .rmdir = jffs2_rmdir, + .mknod = jffs2_mknod, +- .rename = jffs2_rename, ++ .rename2 = jffs2_rename, + .get_acl = jffs2_get_acl, + .set_acl = jffs2_set_acl, + .setattr = jffs2_setattr, +@@ -756,8 +756,27 @@ static int jffs2_mknod (struct inode *di + return ret; + } + ++static int jffs2_whiteout(struct inode *old_dir, struct dentry *old_dentry) ++{ ++ struct dentry *wh; ++ int err; ++ ++ wh = d_alloc(old_dentry->d_parent, &old_dentry->d_name); ++ if (!wh) ++ return -ENOMEM; ++ ++ err = jffs2_mknod(old_dir, wh, S_IFCHR | WHITEOUT_MODE, ++ WHITEOUT_DEV); ++ if (err) ++ return err; ++ ++ d_rehash(wh); ++ return 0; ++} ++ + static int jffs2_rename (struct inode *old_dir_i, struct dentry *old_dentry, +- struct inode *new_dir_i, struct dentry *new_dentry) ++ struct inode *new_dir_i, struct dentry *new_dentry, ++ unsigned int flags) + { + int ret; + struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb); +@@ -765,6 +784,9 @@ static int jffs2_rename (struct inode *o + uint8_t type; + uint32_t now; + ++ if (flags & ~RENAME_WHITEOUT) ++ return -EINVAL; ++ + /* The VFS will check for us and prevent trying to rename a + * file over a directory and vice versa, but if it's a directory, + * the VFS can't check whether the victim is empty. The filesystem +@@ -828,9 +850,14 @@ static int jffs2_rename (struct inode *o + if (d_is_dir(old_dentry) && !victim_f) + inc_nlink(new_dir_i); + +- /* Unlink the original */ +- ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), +- old_dentry->d_name.name, old_dentry->d_name.len, NULL, now); ++ if (flags & RENAME_WHITEOUT) ++ /* Replace with whiteout */ ++ ret = jffs2_whiteout(old_dir_i, old_dentry); ++ else ++ /* Unlink the original */ ++ ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), ++ old_dentry->d_name.name, ++ old_dentry->d_name.len, NULL, now); + + /* We don't touch inode->i_nlink */ + diff --git a/target/linux/generic/patches-4.1/111-jffs2-add-RENAME_EXCHANGE-support.patch b/target/linux/generic/patches-4.1/111-jffs2-add-RENAME_EXCHANGE-support.patch new file mode 100644 index 0000000..3cc7b90 --- /dev/null +++ b/target/linux/generic/patches-4.1/111-jffs2-add-RENAME_EXCHANGE-support.patch @@ -0,0 +1,58 @@ +From: Felix Fietkau +Date: Sat, 25 Apr 2015 12:41:32 +0200 +Subject: [PATCH] jffs2: add RENAME_EXCHANGE support + +Signed-off-by: Felix Fietkau +--- + +--- a/fs/jffs2/dir.c ++++ b/fs/jffs2/dir.c +@@ -784,7 +784,7 @@ static int jffs2_rename (struct inode *o + uint8_t type; + uint32_t now; + +- if (flags & ~RENAME_WHITEOUT) ++ if (flags & ~(RENAME_WHITEOUT | RENAME_EXCHANGE)) + return -EINVAL; + + /* The VFS will check for us and prevent trying to rename a +@@ -792,7 +792,7 @@ static int jffs2_rename (struct inode *o + * the VFS can't check whether the victim is empty. The filesystem + * needs to do that for itself. + */ +- if (d_really_is_positive(new_dentry)) { ++ if (d_really_is_positive(new_dentry) && !(flags & RENAME_EXCHANGE)) { + victim_f = JFFS2_INODE_INFO(d_inode(new_dentry)); + if (d_is_dir(new_dentry)) { + struct jffs2_full_dirent *fd; +@@ -827,7 +827,7 @@ static int jffs2_rename (struct inode *o + if (ret) + return ret; + +- if (victim_f) { ++ if (victim_f && !(flags & RENAME_EXCHANGE)) { + /* There was a victim. Kill it off nicely */ + if (d_is_dir(new_dentry)) + clear_nlink(d_inode(new_dentry)); +@@ -853,6 +853,12 @@ static int jffs2_rename (struct inode *o + if (flags & RENAME_WHITEOUT) + /* Replace with whiteout */ + ret = jffs2_whiteout(old_dir_i, old_dentry); ++ else if (flags & RENAME_EXCHANGE) ++ /* Replace the original */ ++ ret = jffs2_do_link(c, JFFS2_INODE_INFO(old_dir_i), ++ d_inode(new_dentry)->i_ino, type, ++ old_dentry->d_name.name, old_dentry->d_name.len, ++ now); + else + /* Unlink the original */ + ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), +@@ -879,7 +885,7 @@ static int jffs2_rename (struct inode *o + return ret; + } + +- if (d_is_dir(old_dentry)) ++ if (d_is_dir(old_dentry) && !(flags & RENAME_EXCHANGE)) + drop_nlink(old_dir_i); + + new_dir_i->i_mtime = new_dir_i->i_ctime = old_dir_i->i_mtime = old_dir_i->i_ctime = ITIME(now); diff --git a/target/linux/generic/patches-4.1/120-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/patches-4.1/120-bridge_allow_receiption_on_disabled_port.patch new file mode 100644 index 0000000..5cd2f57 --- /dev/null +++ b/target/linux/generic/patches-4.1/120-bridge_allow_receiption_on_disabled_port.patch @@ -0,0 +1,54 @@ +From: Stephen Hemminger +Subject: bridge: allow receiption on disabled port + +When an ethernet device is enslaved to a bridge, and the bridge STP +detects loss of carrier (or operational state down), then normally +packet receiption is blocked. + +This breaks control applications like WPA which maybe expecting to +receive packets to negotiate to bring link up. The bridge needs to +block forwarding packets from these disabled ports, but there is no +hard requirement to not allow local packet delivery. + +Signed-off-by: Stephen Hemminger +Signed-off-by: Felix Fietkau + +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -211,11 +211,13 @@ EXPORT_SYMBOL_GPL(br_handle_frame_finish + static int br_handle_local_finish(struct sock *sk, struct sk_buff *skb) + { + struct net_bridge_port *p = br_port_get_rcu(skb->dev); +- u16 vid = 0; ++ if (p->state != BR_STATE_DISABLED) { ++ u16 vid = 0; + +- /* check if vlan is allowed, to avoid spoofing */ +- if (p->flags & BR_LEARNING && br_should_learn(p, skb, &vid)) +- br_fdb_update(p->br, p, eth_hdr(skb)->h_source, vid, false); ++ /* check if vlan is allowed, to avoid spoofing */ ++ if (p->flags & BR_LEARNING && br_should_learn(p, skb, &vid)) ++ br_fdb_update(p->br, p, eth_hdr(skb)->h_source, vid, false); ++ } + return 0; /* process further */ + } + +@@ -289,6 +291,18 @@ rx_handler_result_t br_handle_frame(stru + + forward: + switch (p->state) { ++ case BR_STATE_DISABLED: ++ if (ether_addr_equal(p->br->dev->dev_addr, dest)) ++ skb->pkt_type = PACKET_HOST; ++ ++ if (NF_HOOK(NFPROTO_BRIDGE, NF_BR_PRE_ROUTING, NULL, skb, skb->dev, NULL, ++ br_handle_local_finish)) ++ break; ++ ++ BR_INPUT_SKB_CB(skb)->brdev = p->br->dev; ++ br_pass_frame_up(skb); ++ break; ++ + case BR_STATE_FORWARDING: + rhook = rcu_dereference(br_should_route_hook); + if (rhook) { diff --git a/target/linux/generic/patches-4.1/132-mips_inline_dma_ops.patch b/target/linux/generic/patches-4.1/132-mips_inline_dma_ops.patch new file mode 100644 index 0000000..f7543cc --- /dev/null +++ b/target/linux/generic/patches-4.1/132-mips_inline_dma_ops.patch @@ -0,0 +1,697 @@ +From 2c58080407554e1bac8fd50d23cb02420524caed Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Mon, 12 Aug 2013 12:50:22 +0200 +Subject: [PATCH] MIPS: partially inline dma ops + +Several DMA ops are no-op on many platforms, and the indirection through +the mips_dma_map_ops function table is causing the compiler to emit +unnecessary code. + +Inlining visibly improves network performance in my tests (on a 24Kc +based system), and also slightly reduces code size of a few drivers. + +Signed-off-by: Felix Fietkau +--- + arch/mips/Kconfig | 4 + + arch/mips/include/asm/dma-mapping.h | 360 +++++++++++++++++++++++++++++++++++- + arch/mips/mm/dma-default.c | 163 ++-------------- + 3 files changed, 373 insertions(+), 154 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1571,6 +1571,7 @@ config CPU_CAVIUM_OCTEON + select CPU_SUPPORTS_HUGEPAGES + select USB_EHCI_BIG_ENDIAN_MMIO + select MIPS_L1_CACHE_SHIFT_7 ++ select SYS_HAS_DMA_OPS + help + The Cavium Octeon processor is a highly integrated chip containing + many ethernet hardware widgets for networking tasks. The processor +@@ -1866,6 +1867,9 @@ config MIPS_MALTA_PM + bool + default y + ++config SYS_HAS_DMA_OPS ++ bool ++ + # + # CPU may reorder R->R, R->W, W->R, W->W + # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC +--- a/arch/mips/include/asm/dma-mapping.h ++++ b/arch/mips/include/asm/dma-mapping.h +@@ -1,9 +1,16 @@ + #ifndef _ASM_DMA_MAPPING_H + #define _ASM_DMA_MAPPING_H + ++#include ++#include ++#include ++#include ++#include ++ + #include + #include + #include ++#include + #include + + #ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */ +@@ -12,12 +19,48 @@ + + extern struct dma_map_ops *mips_dma_map_ops; + ++void __dma_sync(struct page *page, unsigned long offset, size_t size, ++ enum dma_data_direction direction); ++void *mips_dma_alloc_coherent(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp, ++ struct dma_attrs *attrs); ++void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, ++ dma_addr_t dma_handle, struct dma_attrs *attrs); ++ + static inline struct dma_map_ops *get_dma_ops(struct device *dev) + { ++#ifdef CONFIG_SYS_HAS_DMA_OPS + if (dev && dev->archdata.dma_ops) + return dev->archdata.dma_ops; + else + return mips_dma_map_ops; ++#else ++ return NULL; ++#endif ++} ++ ++/* ++ * Warning on the terminology - Linux calls an uncached area coherent; ++ * MIPS terminology calls memory areas with hardware maintained coherency ++ * coherent. ++ */ ++ ++static inline int cpu_needs_post_dma_flush(struct device *dev) ++{ ++#ifndef CONFIG_SYS_HAS_CPU_R10000 ++ return 0; ++#endif ++ return !plat_device_is_coherent(dev) && ++ (boot_cpu_type() == CPU_R10000 || ++ boot_cpu_type() == CPU_R12000 || ++ boot_cpu_type() == CPU_BMIPS5000); ++} ++ ++static inline struct page *dma_addr_to_page(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return pfn_to_page( ++ plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); + } + + static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) +@@ -30,12 +73,306 @@ static inline bool dma_capable(struct de + + static inline void dma_mark_clean(void *addr, size_t size) {} + +-#include ++static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr, ++ size_t size, ++ enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ unsigned long offset = (unsigned long)ptr & ~PAGE_MASK; ++ struct page *page = virt_to_page(ptr); ++ dma_addr_t addr; ++ ++ kmemcheck_mark_initialized(ptr, size); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ addr = ops->map_page(dev, page, offset, size, dir, attrs); ++ } else { ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, offset, size, dir); ++ ++ addr = plat_map_dma_mem_page(dev, page) + offset; ++ } ++ debug_dma_map_page(dev, page, offset, size, dir, addr, true); ++ return addr; ++} ++ ++static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr, ++ size_t size, ++ enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->unmap_page(dev, addr, size, dir, attrs); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ ++ plat_unmap_dma_mem(dev, addr, size, dir); ++ } ++ debug_dma_unmap_page(dev, addr, size, dir, true); ++} ++ ++static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, ++ int nents, enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ int i, ents; ++ struct scatterlist *s; ++ ++ for_each_sg(sg, s, nents, i) ++ kmemcheck_mark_initialized(sg_virt(s), s->length); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ents = ops->map_sg(dev, sg, nents, dir, attrs); ++ } else { ++ for_each_sg(sg, s, nents, i) { ++ struct page *page = sg_page(s); ++ ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, s->offset, s->length, dir); ++#ifdef CONFIG_NEED_SG_DMA_LENGTH ++ s->dma_length = s->length; ++#endif ++ s->dma_address = ++ plat_map_dma_mem_page(dev, page) + s->offset; ++ } ++ ents = nents; ++ } ++ debug_dma_map_sg(dev, sg, nents, ents, dir); ++ ++ return ents; ++} ++ ++static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, ++ int nents, enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ debug_dma_unmap_sg(dev, sg, nents, dir); ++ if (ops) { ++ ops->unmap_sg(dev, sg, nents, dir, attrs); ++ return; ++ } ++ ++ for_each_sg(sg, s, nents, i) { ++ if (!plat_device_is_coherent(dev) && dir != DMA_TO_DEVICE) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ plat_unmap_dma_mem(dev, s->dma_address, s->length, dir); ++ } ++} ++ ++static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, ++ size_t offset, size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ dma_addr_t addr; ++ ++ kmemcheck_mark_initialized(page_address(page) + offset, size); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ addr = ops->map_page(dev, page, offset, size, dir, NULL); ++ } else { ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, offset, size, dir); ++ ++ addr = plat_map_dma_mem_page(dev, page) + offset; ++ } ++ debug_dma_map_page(dev, page, offset, size, dir, addr, false); ++ ++ return addr; ++} ++ ++static inline void dma_unmap_page(struct device *dev, dma_addr_t addr, ++ size_t size, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->unmap_page(dev, addr, size, dir, NULL); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ plat_post_dma_flush(dev); ++ plat_unmap_dma_mem(dev, addr, size, dir); ++ } ++ debug_dma_unmap_page(dev, addr, size, dir, false); ++} ++ ++static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_cpu(dev, addr, size, dir); ++ else if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ plat_post_dma_flush(dev); ++ debug_dma_sync_single_for_cpu(dev, addr, size, dir); ++} ++ ++static inline void dma_sync_single_for_device(struct device *dev, ++ dma_addr_t addr, size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_device(dev, addr, size, dir); ++ else if (!plat_device_is_coherent(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_for_device(dev, addr, size, dir); ++} ++ ++static inline void dma_sync_single_range_for_cpu(struct device *dev, ++ dma_addr_t addr, ++ unsigned long offset, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ const struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_cpu(dev, addr + offset, size, dir); ++ else if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr + offset), ++ (addr + offset) & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_range_for_cpu(dev, addr, offset, size, dir); ++} ++ ++static inline void dma_sync_single_range_for_device(struct device *dev, ++ dma_addr_t addr, ++ unsigned long offset, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ const struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_device(dev, addr + offset, size, dir); ++ else if (!plat_device_is_coherent(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr + offset), ++ (addr + offset) & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_range_for_device(dev, addr, offset, size, dir); ++} ++ ++static inline void ++dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, ++ int nelems, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_sg_for_cpu(dev, sg, nelems, dir); ++ else if (cpu_needs_post_dma_flush(dev)) { ++ for_each_sg(sg, s, nelems, i) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ } ++ plat_post_dma_flush(dev); ++ debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); ++} ++ ++static inline void ++dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, ++ int nelems, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_sg_for_device(dev, sg, nelems, dir); ++ else if (!plat_device_is_coherent(dev)) { ++ for_each_sg(sg, s, nelems, i) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ } ++ debug_dma_sync_sg_for_device(dev, sg, nelems, dir); ++ ++} ++ ++#define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, NULL) ++#define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, NULL) ++#define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, NULL) ++#define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, NULL) ++ ++extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, ++ void *cpu_addr, dma_addr_t dma_addr, size_t size); ++ ++/** ++ * dma_mmap_attrs - map a coherent DMA allocation into user space ++ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices ++ * @vma: vm_area_struct describing requested user mapping ++ * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs ++ * @handle: device-view address returned from dma_alloc_attrs ++ * @size: size of memory originally requested in dma_alloc_attrs ++ * @attrs: attributes of mapping properties requested in dma_alloc_attrs ++ * ++ * Map a coherent DMA buffer previously allocated by dma_alloc_attrs ++ * into user space. The coherent DMA buffer must not be freed by the ++ * driver until the user space mapping has been released. ++ */ ++static inline int ++dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, ++ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ BUG_ON(!ops); ++ if (ops && ops->mmap) ++ return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); ++ return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size); ++} ++ ++#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL) ++ ++int ++dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, ++ void *cpu_addr, dma_addr_t dma_addr, size_t size); ++ ++static inline int ++dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, ++ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ BUG_ON(!ops); ++ if (ops && ops->get_sgtable) ++ return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, ++ attrs); ++ return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size); ++} ++ ++#define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, NULL) ++ + + static inline int dma_supported(struct device *dev, u64 mask) + { + struct dma_map_ops *ops = get_dma_ops(dev); +- return ops->dma_supported(dev, mask); ++ if (ops) ++ return ops->dma_supported(dev, mask); ++ return plat_dma_supported(dev, mask); + } + + static inline int dma_mapping_error(struct device *dev, u64 mask) +@@ -43,7 +380,9 @@ static inline int dma_mapping_error(stru + struct dma_map_ops *ops = get_dma_ops(dev); + + debug_dma_mapping_error(dev, mask); +- return ops->mapping_error(dev, mask); ++ if (ops) ++ return ops->mapping_error(dev, mask); ++ return 0; + } + + static inline int +@@ -54,7 +393,7 @@ dma_set_mask(struct device *dev, u64 mas + if(!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + +- if (ops->set_dma_mask) ++ if (ops && ops->set_dma_mask) + return ops->set_dma_mask(dev, mask); + + *dev->dma_mask = mask; +@@ -74,7 +413,11 @@ static inline void *dma_alloc_attrs(stru + void *ret; + struct dma_map_ops *ops = get_dma_ops(dev); + +- ret = ops->alloc(dev, size, dma_handle, gfp, attrs); ++ if (ops) ++ ret = ops->alloc(dev, size, dma_handle, gfp, attrs); ++ else ++ ret = mips_dma_alloc_coherent(dev, size, dma_handle, gfp, ++ attrs); + + debug_dma_alloc_coherent(dev, size, *dma_handle, ret); + +@@ -89,7 +432,10 @@ static inline void dma_free_attrs(struct + { + struct dma_map_ops *ops = get_dma_ops(dev); + +- ops->free(dev, size, vaddr, dma_handle, attrs); ++ if (ops) ++ ops->free(dev, size, vaddr, dma_handle, attrs); ++ else ++ mips_dma_free_coherent(dev, size, vaddr, dma_handle, attrs); + + debug_dma_free_coherent(dev, size, vaddr, dma_handle); + } +--- a/arch/mips/mm/dma-default.c ++++ b/arch/mips/mm/dma-default.c +@@ -26,7 +26,7 @@ + + #ifdef CONFIG_DMA_MAYBE_COHERENT + int coherentio = 0; /* User defined DMA coherency from command line. */ +-EXPORT_SYMBOL_GPL(coherentio); ++EXPORT_SYMBOL(coherentio); + int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ + + static int __init setcoherentio(char *str) +@@ -46,35 +46,6 @@ static int __init setnocoherentio(char * + early_param("nocoherentio", setnocoherentio); + #endif + +-static inline struct page *dma_addr_to_page(struct device *dev, +- dma_addr_t dma_addr) +-{ +- return pfn_to_page( +- plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); +-} +- +-/* +- * The affected CPUs below in 'cpu_needs_post_dma_flush()' can +- * speculatively fill random cachelines with stale data at any time, +- * requiring an extra flush post-DMA. +- * +- * Warning on the terminology - Linux calls an uncached area coherent; +- * MIPS terminology calls memory areas with hardware maintained coherency +- * coherent. +- * +- * Note that the R14000 and R16000 should also be checked for in this +- * condition. However this function is only called on non-I/O-coherent +- * systems and only the R10000 and R12000 are used in such systems, the +- * SGI IP28 Indigo² rsp. SGI IP32 aka O2. +- */ +-static inline int cpu_needs_post_dma_flush(struct device *dev) +-{ +- return !plat_device_is_coherent(dev) && +- (boot_cpu_type() == CPU_R10000 || +- boot_cpu_type() == CPU_R12000 || +- boot_cpu_type() == CPU_BMIPS5000); +-} +- + static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) + { + gfp_t dma_flag; +@@ -130,8 +101,9 @@ void *dma_alloc_noncoherent(struct devic + } + EXPORT_SYMBOL(dma_alloc_noncoherent); + +-static void *mips_dma_alloc_coherent(struct device *dev, size_t size, +- dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) ++void *mips_dma_alloc_coherent(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp, ++ struct dma_attrs *attrs) + { + void *ret; + struct page *page = NULL; +@@ -162,6 +134,7 @@ static void *mips_dma_alloc_coherent(str + + return ret; + } ++EXPORT_SYMBOL(mips_dma_alloc_coherent); + + + void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, +@@ -172,8 +145,8 @@ void dma_free_noncoherent(struct device + } + EXPORT_SYMBOL(dma_free_noncoherent); + +-static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, +- dma_addr_t dma_handle, struct dma_attrs *attrs) ++void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, ++ dma_addr_t dma_handle, struct dma_attrs *attrs) + { + unsigned long addr = (unsigned long) vaddr; + int order = get_order(size); +@@ -193,6 +166,7 @@ static void mips_dma_free_coherent(struc + if (!dma_release_from_contiguous(dev, page, count)) + __free_pages(page, get_order(size)); + } ++EXPORT_SYMBOL(mips_dma_free_coherent); + + static inline void __dma_sync_virtual(void *addr, size_t size, + enum dma_data_direction direction) +@@ -221,8 +195,8 @@ static inline void __dma_sync_virtual(vo + * If highmem is not configured then the bulk of this loop gets + * optimized out. + */ +-static inline void __dma_sync(struct page *page, +- unsigned long offset, size_t size, enum dma_data_direction direction) ++void __dma_sync(struct page *page, unsigned long offset, size_t size, ++ enum dma_data_direction direction) + { + size_t left = size; + +@@ -251,110 +225,7 @@ static inline void __dma_sync(struct pag + left -= len; + } while (left); + } +- +-static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, +- size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) +-{ +- if (cpu_needs_post_dma_flush(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_addr), +- dma_addr & ~PAGE_MASK, size, direction); +- plat_post_dma_flush(dev); +- plat_unmap_dma_mem(dev, dma_addr, size, direction); +-} +- +-static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg, +- int nents, enum dma_data_direction direction, struct dma_attrs *attrs) +-{ +- int i; +- +- for (i = 0; i < nents; i++, sg++) { +- if (!plat_device_is_coherent(dev)) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-#ifdef CONFIG_NEED_SG_DMA_LENGTH +- sg->dma_length = sg->length; +-#endif +- sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + +- sg->offset; +- } +- +- return nents; +-} +- +-static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page, +- unsigned long offset, size_t size, enum dma_data_direction direction, +- struct dma_attrs *attrs) +-{ +- if (!plat_device_is_coherent(dev)) +- __dma_sync(page, offset, size, direction); +- +- return plat_map_dma_mem_page(dev, page) + offset; +-} +- +-static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg, +- int nhwentries, enum dma_data_direction direction, +- struct dma_attrs *attrs) +-{ +- int i; +- +- for (i = 0; i < nhwentries; i++, sg++) { +- if (!plat_device_is_coherent(dev) && +- direction != DMA_TO_DEVICE) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +- plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction); +- } +-} +- +-static void mips_dma_sync_single_for_cpu(struct device *dev, +- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +-{ +- if (cpu_needs_post_dma_flush(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_handle), +- dma_handle & ~PAGE_MASK, size, direction); +- plat_post_dma_flush(dev); +-} +- +-static void mips_dma_sync_single_for_device(struct device *dev, +- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +-{ +- if (!plat_device_is_coherent(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_handle), +- dma_handle & ~PAGE_MASK, size, direction); +-} +- +-static void mips_dma_sync_sg_for_cpu(struct device *dev, +- struct scatterlist *sg, int nelems, enum dma_data_direction direction) +-{ +- int i; +- +- if (cpu_needs_post_dma_flush(dev)) +- for (i = 0; i < nelems; i++, sg++) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +- plat_post_dma_flush(dev); +-} +- +-static void mips_dma_sync_sg_for_device(struct device *dev, +- struct scatterlist *sg, int nelems, enum dma_data_direction direction) +-{ +- int i; +- +- if (!plat_device_is_coherent(dev)) +- for (i = 0; i < nelems; i++, sg++) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-} +- +-int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +-{ +- return 0; +-} +- +-int mips_dma_supported(struct device *dev, u64 mask) +-{ +- return plat_dma_supported(dev, mask); +-} ++EXPORT_SYMBOL(__dma_sync); + + void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) +@@ -367,23 +238,10 @@ void dma_cache_sync(struct device *dev, + + EXPORT_SYMBOL(dma_cache_sync); + +-static struct dma_map_ops mips_default_dma_map_ops = { +- .alloc = mips_dma_alloc_coherent, +- .free = mips_dma_free_coherent, +- .map_page = mips_dma_map_page, +- .unmap_page = mips_dma_unmap_page, +- .map_sg = mips_dma_map_sg, +- .unmap_sg = mips_dma_unmap_sg, +- .sync_single_for_cpu = mips_dma_sync_single_for_cpu, +- .sync_single_for_device = mips_dma_sync_single_for_device, +- .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu, +- .sync_sg_for_device = mips_dma_sync_sg_for_device, +- .mapping_error = mips_dma_mapping_error, +- .dma_supported = mips_dma_supported +-}; +- +-struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops; ++#ifdef CONFIG_SYS_HAS_DMA_OPS ++struct dma_map_ops *mips_dma_map_ops = NULL; + EXPORT_SYMBOL(mips_dma_map_ops); ++#endif + + #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) + diff --git a/target/linux/generic/patches-4.1/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch b/target/linux/generic/patches-4.1/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch new file mode 100644 index 0000000..d8f25ac --- /dev/null +++ b/target/linux/generic/patches-4.1/133-MIPS-UAPI-Ignore-__arch_swab-16-32-64-when-using-MIP.patch @@ -0,0 +1,58 @@ +From 71a0a72456b48de972d7ed613b06a22a3aa9057f Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 26 Sep 2015 13:41:43 +0800 +Subject: [PATCH] MIPS: UAPI: Ignore __arch_swab{16,32,64} when using MIPS16 + +Some GCC versions (e.g. 4.8.3) can incorrectly inline a function with +MIPS32 instructions into another function with MIPS16 code [1], causing +the assembler to genereate incorrect binary code or fail right away +complaining about unrecognized opcode. + +In the case of __arch_swab{16,32}, when inlined by the compiler with +flags `-mips32r2 -mips16 -Os', the assembler can fail with the following +error. + + {standard input}:79: Error: unrecognized opcode `wsbh $2,$2' + +For performance concerns and to workaround the issue already existing in +older compilers, just ignore these 2 functions when compiling with +mips16 enabled. + + [1] Inlining nomips16 function into mips16 function can result in + undefined builtins, https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55777 + +Signed-off-by: Yousong Zhou +Cc: Maciej W. Rozycki +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/11241/ +Signed-off-by: Ralf Baechle +--- + arch/mips/include/uapi/asm/swab.h | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/arch/mips/include/uapi/asm/swab.h b/arch/mips/include/uapi/asm/swab.h +index 8f2d184..23cd9b1 100644 +--- a/arch/mips/include/uapi/asm/swab.h ++++ b/arch/mips/include/uapi/asm/swab.h +@@ -13,8 +13,9 @@ + + #define __SWAB_64_THRU_32__ + +-#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ +- defined(_MIPS_ARCH_LOONGSON3A) ++#if !defined(__mips16) && \ ++ ((defined(__mips_isa_rev) && (__mips_isa_rev >= 2)) || \ ++ defined(_MIPS_ARCH_LOONGSON3A)) + + static inline __attribute_const__ __u16 __arch_swab16(__u16 x) + { +@@ -65,5 +66,5 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 x) + } + #define __arch_swab64 __arch_swab64 + #endif /* __mips64 */ +-#endif /* MIPS R2 or newer or Loongson 3A */ ++#endif /* (not __mips16) and (MIPS R2 or newer or Loongson 3A) */ + #endif /* _ASM_SWAB_H */ +-- +1.7.10.4 + diff --git a/target/linux/generic/patches-4.1/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch b/target/linux/generic/patches-4.1/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch new file mode 100644 index 0000000..18ec833 --- /dev/null +++ b/target/linux/generic/patches-4.1/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch @@ -0,0 +1,175 @@ +From 173b0add0cff6558f950c0cb1eacfb729d482711 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 17 May 2015 18:48:38 +0200 +Subject: [PATCH 4/8] mtd: part: add generic parsing of linux,part-probe + +This moves the linux,part-probe device tree parsing code from +physmap_of.c to mtdpart.c. Now all drivers can use this feature by just +providing a reference to their device tree node in struct +mtd_part_parser_data. + +Signed-off-by: Hauke Mehrtens +--- + Documentation/devicetree/bindings/mtd/nand.txt | 16 ++++++++++ + drivers/mtd/maps/physmap_of.c | 40 +----------------------- + drivers/mtd/mtdpart.c | 43 ++++++++++++++++++++++++++ + 3 files changed, 60 insertions(+), 39 deletions(-) + +--- a/Documentation/devicetree/bindings/mtd/nand.txt ++++ b/Documentation/devicetree/bindings/mtd/nand.txt +@@ -12,6 +12,22 @@ + - nand-ecc-step-size: integer representing the number of data bytes + that are covered by a single ECC step. + ++- linux,part-probe: list of name as strings of the partition parser ++ which should be used to parse the partition table. ++ They will be tried in the specified ordering and ++ the next one will be used if the previous one ++ failed. ++ ++ Example: linux,part-probe = "cmdlinepart", "ofpart"; ++ ++ This is also the default value, which will be used ++ if this attribute is not specified. It could be ++ that the flash driver in use overwrote the default ++ value and uses some other default. ++ ++ Possible values are: bcm47xxpart, afs, ar7part, ++ ofoldpart, ofpart, bcm63xxpart, RedBoot, cmdlinepart ++ + The ECC strength and ECC step size properties define the correction capability + of a controller. Together, they say a controller can correct "{strength} bit + errors per {size} bytes". +--- a/drivers/mtd/maps/physmap_of.c ++++ b/drivers/mtd/maps/physmap_of.c +@@ -112,45 +112,9 @@ static struct mtd_info *obsolete_probe(s + static const char * const part_probe_types_def[] = { + "cmdlinepart", "RedBoot", "ofpart", "ofoldpart", NULL }; + +-static const char * const *of_get_probes(struct device_node *dp) +-{ +- const char *cp; +- int cplen; +- unsigned int l; +- unsigned int count; +- const char **res; +- +- cp = of_get_property(dp, "linux,part-probe", &cplen); +- if (cp == NULL) +- return part_probe_types_def; +- +- count = 0; +- for (l = 0; l != cplen; l++) +- if (cp[l] == 0) +- count++; +- +- res = kzalloc((count + 1)*sizeof(*res), GFP_KERNEL); +- count = 0; +- while (cplen > 0) { +- res[count] = cp; +- l = strlen(cp) + 1; +- cp += l; +- cplen -= l; +- count++; +- } +- return res; +-} +- +-static void of_free_probes(const char * const *probes) +-{ +- if (probes != part_probe_types_def) +- kfree(probes); +-} +- + static struct of_device_id of_flash_match[]; + static int of_flash_probe(struct platform_device *dev) + { +- const char * const *part_probe_types; + const struct of_device_id *match; + struct device_node *dp = dev->dev.of_node; + struct resource res; +@@ -310,10 +274,8 @@ static int of_flash_probe(struct platfor + goto err_out; + + ppdata.of_node = dp; +- part_probe_types = of_get_probes(dp); +- mtd_device_parse_register(info->cmtd, part_probe_types, &ppdata, ++ mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata, + NULL, 0); +- of_free_probes(part_probe_types); + + kfree(mtd_list); + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -719,6 +720,40 @@ void deregister_mtd_parser(struct mtd_pa + EXPORT_SYMBOL_GPL(deregister_mtd_parser); + + /* ++ * Parses the linux,part-probe device tree property. ++ * When a non null value is returned it has to be freed with kfree() by ++ * the caller. ++ */ ++static const char * const *of_get_probes(struct device_node *dp) ++{ ++ const char *cp; ++ int cplen; ++ unsigned int l; ++ unsigned int count; ++ const char **res; ++ ++ cp = of_get_property(dp, "linux,part-probe", &cplen); ++ if (cp == NULL) ++ return NULL; ++ ++ count = 0; ++ for (l = 0; l != cplen; l++) ++ if (cp[l] == 0) ++ count++; ++ ++ res = kzalloc((count + 1) * sizeof(*res), GFP_KERNEL); ++ count = 0; ++ while (cplen > 0) { ++ res[count] = cp; ++ l = strlen(cp) + 1; ++ cp += l; ++ cplen -= l; ++ count++; ++ } ++ return res; ++} ++ ++/* + * Do not forget to update 'parse_mtd_partitions()' kerneldoc comment if you + * are changing this array! + */ +@@ -754,6 +789,13 @@ int parse_mtd_partitions(struct mtd_info + { + struct mtd_part_parser *parser; + int ret = 0; ++ const char *const *types_of = NULL; ++ ++ if (data && data->of_node) { ++ types_of = of_get_probes(data->of_node); ++ if (types_of != NULL) ++ types = types_of; ++ } + + if (!types) + types = default_mtd_part_types; +@@ -772,6 +814,7 @@ int parse_mtd_partitions(struct mtd_info + break; + } + } ++ kfree(types_of); + return ret; + } + diff --git a/target/linux/generic/patches-4.1/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch b/target/linux/generic/patches-4.1/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch new file mode 100644 index 0000000..a17e398 --- /dev/null +++ b/target/linux/generic/patches-4.1/180-usb-xhci-make-USB_XHCI_PLATFORM-selectable.patch @@ -0,0 +1,41 @@ +From 9612e686b235dc9e33c8dfb5e6d2ff2b2140fb9d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 16 Jun 2015 21:01:30 +0200 +Subject: [PATCH V2] usb: xhci: make USB_XHCI_PLATFORM selectable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Right now xhci-plat-hcd can be built when using one of platform specific +drivers only (mvebu/rcar). There shouldn't be such limitation as some +platforms may not require any quirks and may want to just use a generic +driver ("generic-xhci" / "xhci-hcd"). + +Signed-off-by: Rafał Miłecki +--- +Greg/Mathias: I'm not sure if it's more like USB subsystem stuff or xHCI +Could you decide which one of you could pick that, please? + +V2: Drop useless "default n", thanks Sergei :) +--- + drivers/usb/host/Kconfig | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -32,7 +32,14 @@ config USB_XHCI_PCI + default y + + config USB_XHCI_PLATFORM +- tristate ++ tristate "Generic xHCI driver for a platform device" ++ ---help--- ++ Adds an xHCI host driver for a generic platform device, which ++ provides a memory space and an irq. ++ It is also a prerequisite for platform specific drivers that ++ implement some extra quirks. ++ ++ If unsure, say N. + + config USB_XHCI_MVEBU + tristate "xHCI support for Marvell Armada 375/38x" diff --git a/target/linux/generic/patches-4.1/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch b/target/linux/generic/patches-4.1/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch new file mode 100644 index 0000000..09cbe0c --- /dev/null +++ b/target/linux/generic/patches-4.1/190-cdc_ncm_add_support_for_moving_ndp_to_end_of_ncm_frame.patch @@ -0,0 +1,228 @@ +From 4a0e3e989d66bb7204b163d9cfaa7fa96d0f2023 Mon Sep 17 00:00:00 2001 +From: Enrico Mioso +Date: Wed, 8 Jul 2015 13:05:57 +0200 +Subject: [PATCH] cdc_ncm: Add support for moving NDP to end of NCM frame + +NCM specs are not actually mandating a specific position in the frame for +the NDP (Network Datagram Pointer). However, some Huawei devices will +ignore our aggregates if it is not placed after the datagrams it points +to. Add support for doing just this, in a per-device configurable way. +While at it, update NCM subdrivers, disabling this functionality in all of +them, except in huawei_cdc_ncm where it is enabled instead. +We aren't making any distinction between different Huawei NCM devices, +based on what the vendor driver does. Standard NCM devices are left +unaffected: if they are compliant, they should be always usable, still +stay on the safe side. + +This change has been tested and working with a Huawei E3131 device (which +works regardless of NDP position), a Huawei E3531 (also working both +ways) and an E3372 (which mandates NDP to be after indexed datagrams). + +V1->V2: +- corrected wrong NDP acronym definition +- fixed possible NULL pointer dereference +- patch cleanup +V2->V3: +- Properly account for the NDP size when writing new packets to SKB + +Signed-off-by: Enrico Mioso +Signed-off-by: David S. Miller +--- + drivers/net/usb/cdc_mbim.c | 2 +- + drivers/net/usb/cdc_ncm.c | 61 ++++++++++++++++++++++++++++++++++++---- + drivers/net/usb/huawei_cdc_ncm.c | 7 +++-- + include/linux/usb/cdc_ncm.h | 7 ++++- + 4 files changed, 67 insertions(+), 10 deletions(-) + +--- a/drivers/net/usb/cdc_mbim.c ++++ b/drivers/net/usb/cdc_mbim.c +@@ -158,7 +158,7 @@ static int cdc_mbim_bind(struct usbnet * + if (!cdc_ncm_comm_intf_is_mbim(intf->cur_altsetting)) + goto err; + +- ret = cdc_ncm_bind_common(dev, intf, data_altsetting); ++ ret = cdc_ncm_bind_common(dev, intf, data_altsetting, 0); + if (ret) + goto err; + +--- a/drivers/net/usb/cdc_ncm.c ++++ b/drivers/net/usb/cdc_ncm.c +@@ -684,10 +684,12 @@ static void cdc_ncm_free(struct cdc_ncm_ + ctx->tx_curr_skb = NULL; + } + ++ kfree(ctx->delayed_ndp16); ++ + kfree(ctx); + } + +-int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting) ++int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting, int drvflags) + { + const struct usb_cdc_union_desc *union_desc = NULL; + struct cdc_ncm_ctx *ctx; +@@ -855,6 +857,17 @@ advance: + /* finish setting up the device specific data */ + cdc_ncm_setup(dev); + ++ /* Device-specific flags */ ++ ctx->drvflags = drvflags; ++ ++ /* Allocate the delayed NDP if needed. */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { ++ ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); ++ if (!ctx->delayed_ndp16) ++ goto error2; ++ dev_info(&intf->dev, "NDP will be placed at end of frame for this device."); ++ } ++ + /* override ethtool_ops */ + dev->net->ethtool_ops = &cdc_ncm_ethtool_ops; + +@@ -954,8 +967,11 @@ static int cdc_ncm_bind(struct usbnet *d + if (cdc_ncm_select_altsetting(intf) != CDC_NCM_COMM_ALTSETTING_NCM) + return -ENODEV; + +- /* The NCM data altsetting is fixed */ +- ret = cdc_ncm_bind_common(dev, intf, CDC_NCM_DATA_ALTSETTING_NCM); ++ /* The NCM data altsetting is fixed, so we hard-coded it. ++ * Additionally, generic NCM devices are assumed to accept arbitrarily ++ * placed NDP. ++ */ ++ ret = cdc_ncm_bind_common(dev, intf, CDC_NCM_DATA_ALTSETTING_NCM, 0); + + /* + * We should get an event when network connection is "connected" or +@@ -986,6 +1002,14 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + struct usb_cdc_ncm_nth16 *nth16 = (void *)skb->data; + size_t ndpoffset = le16_to_cpu(nth16->wNdpIndex); + ++ /* If NDP should be moved to the end of the NCM package, we can't follow the ++ * NTH16 header as we would normally do. NDP isn't written to the SKB yet, and ++ * the wNdpIndex field in the header is actually not consistent with reality. It will be later. ++ */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) ++ if (ctx->delayed_ndp16->dwSignature == sign) ++ return ctx->delayed_ndp16; ++ + /* follow the chain of NDPs, looking for a match */ + while (ndpoffset) { + ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb->data + ndpoffset); +@@ -995,7 +1019,8 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + } + + /* align new NDP */ +- cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_max); ++ if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) ++ cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_max); + + /* verify that there is room for the NDP and the datagram (reserve) */ + if ((ctx->tx_max - skb->len - reserve) < ctx->max_ndp_size) +@@ -1008,7 +1033,11 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm + nth16->wNdpIndex = cpu_to_le16(skb->len); + + /* push a new empty NDP */ +- ndp16 = (struct usb_cdc_ncm_ndp16 *)memset(skb_put(skb, ctx->max_ndp_size), 0, ctx->max_ndp_size); ++ if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) ++ ndp16 = (struct usb_cdc_ncm_ndp16 *)memset(skb_put(skb, ctx->max_ndp_size), 0, ctx->max_ndp_size); ++ else ++ ndp16 = ctx->delayed_ndp16; ++ + ndp16->dwSignature = sign; + ndp16->wLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_ndp16) + sizeof(struct usb_cdc_ncm_dpe16)); + return ndp16; +@@ -1023,6 +1052,15 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + struct sk_buff *skb_out; + u16 n = 0, index, ndplen; + u8 ready2send = 0; ++ u32 delayed_ndp_size; ++ ++ /* When our NDP gets written in cdc_ncm_ndp(), then skb_out->len gets updated ++ * accordingly. Otherwise, we should check here. ++ */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) ++ delayed_ndp_size = ctx->max_ndp_size; ++ else ++ delayed_ndp_size = 0; + + /* if there is a remaining skb, it gets priority */ + if (skb != NULL) { +@@ -1077,7 +1115,7 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + cdc_ncm_align_tail(skb_out, ctx->tx_modulus, ctx->tx_remainder, ctx->tx_max); + + /* check if we had enough room left for both NDP and frame */ +- if (!ndp16 || skb_out->len + skb->len > ctx->tx_max) { ++ if (!ndp16 || skb_out->len + skb->len + delayed_ndp_size > ctx->tx_max) { + if (n == 0) { + /* won't fit, MTU problem? */ + dev_kfree_skb_any(skb); +@@ -1150,6 +1188,17 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev + /* variables will be reset at next call */ + } + ++ /* If requested, put NDP at end of frame. */ ++ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { ++ nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; ++ cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_max); ++ nth16->wNdpIndex = cpu_to_le16(skb_out->len); ++ memcpy(skb_put(skb_out, ctx->max_ndp_size), ctx->delayed_ndp16, ctx->max_ndp_size); ++ ++ /* Zero out delayed NDP - signature checking will naturally fail. */ ++ ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); ++ } ++ + /* If collected data size is less or equal ctx->min_tx_pkt + * bytes, we send buffers as it is. If we get more data, it + * would be more efficient for USB HS mobile device with DMA +--- a/drivers/net/usb/huawei_cdc_ncm.c ++++ b/drivers/net/usb/huawei_cdc_ncm.c +@@ -73,11 +73,14 @@ static int huawei_cdc_ncm_bind(struct us + struct usb_driver *subdriver = ERR_PTR(-ENODEV); + int ret = -ENODEV; + struct huawei_cdc_ncm_state *drvstate = (void *)&usbnet_dev->data; ++ int drvflags = 0; + + /* altsetting should always be 1 for NCM devices - so we hard-coded +- * it here ++ * it here. Some huawei devices will need the NDP part of the NCM package to ++ * be at the end of the frame. + */ +- ret = cdc_ncm_bind_common(usbnet_dev, intf, 1); ++ drvflags |= CDC_NCM_FLAG_NDP_TO_END; ++ ret = cdc_ncm_bind_common(usbnet_dev, intf, 1, drvflags); + if (ret) + goto err; + +--- a/include/linux/usb/cdc_ncm.h ++++ b/include/linux/usb/cdc_ncm.h +@@ -80,6 +80,9 @@ + #define CDC_NCM_TIMER_INTERVAL_MIN 5UL + #define CDC_NCM_TIMER_INTERVAL_MAX (U32_MAX / NSEC_PER_USEC) + ++/* Driver flags */ ++#define CDC_NCM_FLAG_NDP_TO_END 0x02 /* NDP is placed at end of frame */ ++ + #define cdc_ncm_comm_intf_is_mbim(x) ((x)->desc.bInterfaceSubClass == USB_CDC_SUBCLASS_MBIM && \ + (x)->desc.bInterfaceProtocol == USB_CDC_PROTO_NONE) + #define cdc_ncm_data_intf_is_mbim(x) ((x)->desc.bInterfaceProtocol == USB_CDC_MBIM_PROTO_NTB) +@@ -103,9 +106,11 @@ struct cdc_ncm_ctx { + + spinlock_t mtx; + atomic_t stop; ++ int drvflags; + + u32 timer_interval; + u32 max_ndp_size; ++ struct usb_cdc_ncm_ndp16 *delayed_ndp16; + + u32 tx_timer_pending; + u32 tx_curr_frame_num; +@@ -133,7 +138,7 @@ struct cdc_ncm_ctx { + }; + + u8 cdc_ncm_select_altsetting(struct usb_interface *intf); +-int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting); ++int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_altsetting, int drvflags); + void cdc_ncm_unbind(struct usbnet *dev, struct usb_interface *intf); + struct sk_buff *cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign); + int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); diff --git a/target/linux/generic/patches-4.1/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch b/target/linux/generic/patches-4.1/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch new file mode 100644 index 0000000..fce5d29 --- /dev/null +++ b/target/linux/generic/patches-4.1/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch @@ -0,0 +1,35 @@ +From a95f03e51471dbdbafd3391991d867ac2358ed02 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 23 Aug 2015 14:23:29 +0200 +Subject: [PATCH] usb: ehci-orion: fix probe for !GENERIC_PHY + +Commit d445913ce0ab7f ("usb: ehci-orion: add optional PHY support") +added support for optional phys, but devm_phy_optional_get returns +-ENOSYS if GENERIC_PHY is not enabled. + +This causes probe failures, even when there are no phys specified: + +[ 1.443365] orion-ehci f1058000.usb: init f1058000.usb fail, -38 +[ 1.449403] orion-ehci: probe of f1058000.usb failed with error -38 + +Similar to dwc3, treat -ENOSYS as no phy. + +Fixes: d445913ce0ab7f ("usb: ehci-orion: add optional PHY support") + +Signed-off-by: Jonas Gorski +--- + drivers/usb/host/ehci-orion.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/ehci-orion.c ++++ b/drivers/usb/host/ehci-orion.c +@@ -224,7 +224,8 @@ static int ehci_orion_drv_probe(struct p + priv->phy = devm_phy_optional_get(&pdev->dev, "usb"); + if (IS_ERR(priv->phy)) { + err = PTR_ERR(priv->phy); +- goto err_phy_get; ++ if (err != -ENOSYS) ++ goto err_phy_get; + } else { + err = phy_init(priv->phy); + if (err) diff --git a/target/linux/generic/patches-4.1/200-fix_localversion.patch b/target/linux/generic/patches-4.1/200-fix_localversion.patch new file mode 100644 index 0000000..70228bb --- /dev/null +++ b/target/linux/generic/patches-4.1/200-fix_localversion.patch @@ -0,0 +1,11 @@ +--- a/scripts/setlocalversion ++++ b/scripts/setlocalversion +@@ -165,7 +165,7 @@ else + # annotated or signed tagged state (as git describe only + # looks at signed or annotated tags - git tag -a/-s) and + # LOCALVERSION= is not specified +- if test "${LOCALVERSION+set}" != "set"; then ++ if test "${CONFIG_LOCALVERSION+set}" != "set"; then + scm=$(scm_version --short) + res="$res${scm:++}" + fi diff --git a/target/linux/generic/patches-4.1/201-extra_optimization.patch b/target/linux/generic/patches-4.1/201-extra_optimization.patch new file mode 100644 index 0000000..34ded8c --- /dev/null +++ b/target/linux/generic/patches-4.1/201-extra_optimization.patch @@ -0,0 +1,14 @@ +--- a/Makefile ++++ b/Makefile +@@ -612,9 +612,9 @@ include arch/$(SRCARCH)/Makefile + KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,) + + ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE +-KBUILD_CFLAGS += -Os $(call cc-disable-warning,maybe-uninitialized,) ++KBUILD_CFLAGS += -Os $(EXTRA_OPTIMIZATION) $(call cc-disable-warning,maybe-uninitialized,) + else +-KBUILD_CFLAGS += -O2 ++KBUILD_CFLAGS += -O2 -fno-reorder-blocks -fno-tree-ch $(EXTRA_OPTIMIZATION) + endif + + # Tell gcc to never replace conditional load with a non-conditional one diff --git a/target/linux/generic/patches-4.1/202-reduce_module_size.patch b/target/linux/generic/patches-4.1/202-reduce_module_size.patch new file mode 100644 index 0000000..60ea5c2 --- /dev/null +++ b/target/linux/generic/patches-4.1/202-reduce_module_size.patch @@ -0,0 +1,11 @@ +--- a/Makefile ++++ b/Makefile +@@ -408,7 +408,7 @@ KBUILD_CFLAGS_KERNEL := + KBUILD_AFLAGS := -D__ASSEMBLY__ + KBUILD_AFLAGS_MODULE := -DMODULE + KBUILD_CFLAGS_MODULE := -DMODULE +-KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds ++KBUILD_LDFLAGS_MODULE = -T $(srctree)/scripts/module-common.lds $(if $(CONFIG_PROFILING),,-s) + + # Read KERNELRELEASE from include/config/kernel.release (if it exists) + KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) diff --git a/target/linux/generic/patches-4.1/203-kallsyms_uncompressed.patch b/target/linux/generic/patches-4.1/203-kallsyms_uncompressed.patch new file mode 100644 index 0000000..10cfc83 --- /dev/null +++ b/target/linux/generic/patches-4.1/203-kallsyms_uncompressed.patch @@ -0,0 +1,108 @@ +--- a/scripts/kallsyms.c ++++ b/scripts/kallsyms.c +@@ -58,6 +58,7 @@ static struct addr_range percpu_range = + static struct sym_entry *table; + static unsigned int table_size, table_cnt; + static int all_symbols = 0; ++static int uncompressed = 0; + static int absolute_percpu = 0; + static char symbol_prefix_char = '\0'; + static unsigned long long kernel_start_addr = 0; +@@ -403,6 +404,9 @@ static void write_src(void) + + free(markers); + ++ if (uncompressed) ++ return; ++ + output_label("kallsyms_token_table"); + off = 0; + for (i = 0; i < 256; i++) { +@@ -461,6 +465,9 @@ static void *find_token(unsigned char *s + { + int i; + ++ if (uncompressed) ++ return NULL; ++ + for (i = 0; i < len - 1; i++) { + if (str[i] == token[0] && str[i+1] == token[1]) + return &str[i]; +@@ -533,6 +540,9 @@ static void optimize_result(void) + { + int i, best; + ++ if (uncompressed) ++ return; ++ + /* using the '\0' symbol last allows compress_symbols to use standard + * fast string functions */ + for (i = 255; i >= 0; i--) { +@@ -703,7 +713,9 @@ int main(int argc, char **argv) + } else if (strncmp(argv[i], "--page-offset=", 14) == 0) { + const char *p = &argv[i][14]; + kernel_start_addr = strtoull(p, NULL, 16); +- } else ++ } else if (strcmp(argv[i], "--uncompressed") == 0) ++ uncompressed = 1; ++ else + usage(); + } + } else if (argc != 1) +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1334,6 +1334,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW + the unaligned access emulation. + see arch/parisc/kernel/unaligned.c for reference + ++config KALLSYMS_UNCOMPRESSED ++ bool "Keep kallsyms uncompressed" ++ depends on KALLSYMS ++ help ++ Normally kallsyms contains compressed symbols (using a token table), ++ reducing the uncompressed kernel image size. Keeping the symbol table ++ uncompressed significantly improves the size of this part in compressed ++ kernel images. ++ ++ Say N unless you need compressed kernel images to be small. ++ + config HAVE_PCSPKR_PLATFORM + bool + +--- a/scripts/link-vmlinux.sh ++++ b/scripts/link-vmlinux.sh +@@ -90,6 +90,10 @@ kallsyms() + kallsymopt="${kallsymopt} --absolute-percpu" + fi + ++ if [ -n "${CONFIG_KALLSYMS_UNCOMPRESSED}" ]; then ++ kallsymopt="${kallsymopt} --uncompressed" ++ fi ++ + local aflags="${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL} \ + ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" + +--- a/kernel/kallsyms.c ++++ b/kernel/kallsyms.c +@@ -109,6 +109,11 @@ static unsigned int kallsyms_expand_symb + * For every byte on the compressed symbol data, copy the table + * entry for that byte. + */ ++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED ++ memcpy(result, data + 1, len - 1); ++ result += len - 1; ++ len = 0; ++#endif + while (len) { + tptr = &kallsyms_token_table[kallsyms_token_index[*data]]; + data++; +@@ -141,6 +146,9 @@ tail: + */ + static char kallsyms_get_symbol_type(unsigned int off) + { ++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED ++ return kallsyms_names[off + 1]; ++#endif + /* + * Get just the first code, look it up in the token table, + * and return the first char from this token. diff --git a/target/linux/generic/patches-4.1/204-module_strip.patch b/target/linux/generic/patches-4.1/204-module_strip.patch new file mode 100644 index 0000000..0fdc8e1 --- /dev/null +++ b/target/linux/generic/patches-4.1/204-module_strip.patch @@ -0,0 +1,194 @@ +From: Felix Fietkau +Subject: [PATCH] build: add a hack for removing non-essential module info + +Signed-off-by: Felix Fietkau +--- +--- a/include/linux/module.h ++++ b/include/linux/module.h +@@ -84,9 +84,10 @@ void trim_init_extable(struct module *m) + + /* Generic info of form tag = "info" */ + #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info) ++#define MODULE_INFO_STRIP(tag, info) __MODULE_INFO_STRIP(tag, tag, info) + + /* For userspace: you can also call me... */ +-#define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias) ++#define MODULE_ALIAS(_alias) MODULE_INFO_STRIP(alias, _alias) + + /* Soft module dependencies. See man modprobe.d for details. + * Example: MODULE_SOFTDEP("pre: module-foo module-bar post: module-baz") +@@ -127,12 +128,12 @@ void trim_init_extable(struct module *m) + * Author(s), use "Name " or just "Name", for multiple + * authors use multiple MODULE_AUTHOR() statements/lines. + */ +-#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author) ++#define MODULE_AUTHOR(_author) MODULE_INFO_STRIP(author, _author) + + /* What your module does. */ +-#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description) ++#define MODULE_DESCRIPTION(_description) MODULE_INFO_STRIP(description, _description) + +-#ifdef MODULE ++#if defined(MODULE) && !defined(CONFIG_MODULE_STRIPPED) + /* Creates an alias so file2alias.c can find device table. */ + #define MODULE_DEVICE_TABLE(type, name) \ + extern const typeof(name) __mod_##type##__##name##_device_table \ +@@ -159,7 +160,9 @@ extern const typeof(name) __mod_##type## + */ + + #if defined(MODULE) || !defined(CONFIG_SYSFS) +-#define MODULE_VERSION(_version) MODULE_INFO(version, _version) ++#define MODULE_VERSION(_version) MODULE_INFO_STRIP(version, _version) ++#elif defined(CONFIG_MODULE_STRIPPED) ++#define MODULE_VERSION(_version) __MODULE_INFO_DISABLED(version) + #else + #define MODULE_VERSION(_version) \ + static struct module_version_attribute ___modver_attr = { \ +@@ -181,7 +184,7 @@ extern const typeof(name) __mod_##type## + /* Optional firmware file (or files) needed by the module + * format is simply firmware file name. Multiple firmware + * files require multiple MODULE_FIRMWARE() specifiers */ +-#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware) ++#define MODULE_FIRMWARE(_firmware) MODULE_INFO_STRIP(firmware, _firmware) + + /* Given an address, look for it in the exception tables */ + const struct exception_table_entry *search_exception_tables(unsigned long add); +--- a/include/linux/moduleparam.h ++++ b/include/linux/moduleparam.h +@@ -16,6 +16,16 @@ + /* Chosen so that structs with an unsigned long line up. */ + #define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long)) + ++/* This struct is here for syntactic coherency, it is not used */ ++#define __MODULE_INFO_DISABLED(name) \ ++ struct __UNIQUE_ID(name) {} ++ ++#ifdef CONFIG_MODULE_STRIPPED ++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO_DISABLED(name) ++#else ++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO(tag, name, info) ++#endif ++ + #ifdef MODULE + #define __MODULE_INFO(tag, name, info) \ + static const char __UNIQUE_ID(name)[] \ +@@ -23,8 +33,7 @@ static const char __UNIQUE_ID(name)[] + = __stringify(tag) "=" info + #else /* !MODULE */ + /* This struct is here for syntactic coherency, it is not used */ +-#define __MODULE_INFO(tag, name, info) \ +- struct __UNIQUE_ID(name) {} ++#define __MODULE_INFO(tag, name, info) __MODULE_INFO_DISABLED(name) + #endif + #define __MODULE_PARM_TYPE(name, _type) \ + __MODULE_INFO(parmtype, name##type, #name ":" _type) +@@ -32,7 +41,7 @@ static const char __UNIQUE_ID(name)[] + /* One for each parameter, describing how to use it. Some files do + multiple of these per line, so can't just use MODULE_INFO. */ + #define MODULE_PARM_DESC(_parm, desc) \ +- __MODULE_INFO(parm, _parm, #_parm ":" desc) ++ __MODULE_INFO_STRIP(parm, _parm, #_parm ":" desc) + + struct kernel_param; + +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1998,6 +1998,13 @@ config MODULE_COMPRESS_XZ + + endchoice + ++config MODULE_STRIPPED ++ bool "Reduce module size" ++ depends on MODULES ++ help ++ Remove module parameter descriptions, author info, version, aliases, ++ device tables, etc. ++ + endif # MODULES + + config INIT_ALL_POSSIBLE +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -2681,6 +2681,7 @@ static struct module *setup_load_info(st + + static int check_modinfo(struct module *mod, struct load_info *info, int flags) + { ++#ifndef CONFIG_MODULE_STRIPPED + const char *modmagic = get_modinfo(info, "vermagic"); + int err; + +@@ -2706,6 +2707,7 @@ static int check_modinfo(struct module * + pr_warn("%s: module is from the staging directory, the quality " + "is unknown, you have been warned.\n", mod->name); + } ++#endif + + /* Set up license info based on the info section */ + set_license(mod, get_modinfo(info, "license")); +--- a/scripts/mod/modpost.c ++++ b/scripts/mod/modpost.c +@@ -1959,7 +1959,9 @@ static void read_symbols(char *modname) + symname = remove_dot(info.strtab + sym->st_name); + + handle_modversions(mod, &info, sym, symname); ++#ifndef CONFIG_MODULE_STRIPPED + handle_moddevtable(mod, &info, sym, symname); ++#endif + } + if (!is_vmlinux(modname) || + (is_vmlinux(modname) && vmlinux_section_warnings)) +@@ -2103,7 +2105,9 @@ static void add_header(struct buffer *b, + buf_printf(b, "#include \n"); + buf_printf(b, "#include \n"); + buf_printf(b, "\n"); ++#ifndef CONFIG_MODULE_STRIPPED + buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n"); ++#endif + buf_printf(b, "\n"); + buf_printf(b, "__visible struct module __this_module\n"); + buf_printf(b, "__attribute__((section(\".gnu.linkonce.this_module\"))) = {\n"); +@@ -2120,16 +2124,20 @@ static void add_header(struct buffer *b, + + static void add_intree_flag(struct buffer *b, int is_intree) + { ++#ifndef CONFIG_MODULE_STRIPPED + if (is_intree) + buf_printf(b, "\nMODULE_INFO(intree, \"Y\");\n"); ++#endif + } + + static void add_staging_flag(struct buffer *b, const char *name) + { ++#ifndef CONFIG_MODULE_STRIPPED + static const char *staging_dir = "drivers/staging"; + + if (strncmp(staging_dir, name, strlen(staging_dir)) == 0) + buf_printf(b, "\nMODULE_INFO(staging, \"Y\");\n"); ++#endif + } + + /** +@@ -2222,11 +2230,13 @@ static void add_depends(struct buffer *b + + static void add_srcversion(struct buffer *b, struct module *mod) + { ++#ifndef CONFIG_MODULE_STRIPPED + if (mod->srcversion[0]) { + buf_printf(b, "\n"); + buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n", + mod->srcversion); + } ++#endif + } + + static void write_if_changed(struct buffer *b, const char *fname) +@@ -2457,7 +2467,9 @@ int main(int argc, char **argv) + add_staging_flag(&buf, mod->name); + err |= add_versions(&buf, mod); + add_depends(&buf, mod, modules); ++#ifndef CONFIG_MODULE_STRIPPED + add_moddevtable(&buf, mod); ++#endif + add_srcversion(&buf, mod); + + sprintf(fname, "%s.mod.c", mod->name); diff --git a/target/linux/generic/patches-4.1/205-backtrace_module_info.patch b/target/linux/generic/patches-4.1/205-backtrace_module_info.patch new file mode 100644 index 0000000..48b2204 --- /dev/null +++ b/target/linux/generic/patches-4.1/205-backtrace_module_info.patch @@ -0,0 +1,36 @@ +--- a/lib/vsprintf.c ++++ b/lib/vsprintf.c +@@ -617,8 +617,10 @@ char *symbol_string(char *buf, char *end + struct printf_spec spec, const char *fmt) + { + unsigned long value; +-#ifdef CONFIG_KALLSYMS + char sym[KSYM_SYMBOL_LEN]; ++#ifndef CONFIG_KALLSYMS ++ struct module *mod; ++ int len; + #endif + + if (fmt[1] == 'R') +@@ -632,15 +634,15 @@ char *symbol_string(char *buf, char *end + sprint_symbol(sym, value); + else + sprint_symbol_no_offset(sym, value); +- +- return string(buf, end, sym, spec); + #else +- spec.field_width = 2 * sizeof(void *); +- spec.flags |= SPECIAL | SMALL | ZEROPAD; +- spec.base = 16; ++ len = snprintf(sym, sizeof(sym), "0x%lx", value); + +- return number(buf, end, value, spec); ++ mod = __module_address(value); ++ if (mod) ++ snprintf(sym + len, sizeof(sym) - len, " [%s@%p+0x%x]", ++ mod->name, mod->module_core, mod->core_size); + #endif ++ return string(buf, end, sym, spec); + } + + static noinline_for_stack diff --git a/target/linux/generic/patches-4.1/210-darwin_scripts_include.patch b/target/linux/generic/patches-4.1/210-darwin_scripts_include.patch new file mode 100644 index 0000000..ef548c7 --- /dev/null +++ b/target/linux/generic/patches-4.1/210-darwin_scripts_include.patch @@ -0,0 +1,3088 @@ +--- a/scripts/kallsyms.c ++++ b/scripts/kallsyms.c +@@ -22,6 +22,35 @@ + #include + #include + #include ++#ifdef __APPLE__ ++/* Darwin has no memmem implementation, this one is ripped of the uClibc-0.9.28 source */ ++void *memmem (const void *haystack, size_t haystack_len, ++ const void *needle, size_t needle_len) ++{ ++ const char *begin; ++ const char *const last_possible ++ = (const char *) haystack + haystack_len - needle_len; ++ ++ if (needle_len == 0) ++ /* The first occurrence of the empty string is deemed to occur at ++ the beginning of the string. */ ++ return (void *) haystack; ++ ++ /* Sanity check, otherwise the loop might search through the whole ++ memory. */ ++ if (__builtin_expect (haystack_len < needle_len, 0)) ++ return NULL; ++ ++ for (begin = (const char *) haystack; begin <= last_possible; ++begin) ++ if (begin[0] == ((const char *) needle)[0] && ++ !memcmp ((const void *) &begin[1], ++ (const void *) ((const char *) needle + 1), ++ needle_len - 1)) ++ return (void *) begin; ++ ++ return NULL; ++} ++#endif + + #ifndef ARRAY_SIZE + #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) +--- a/scripts/kconfig/Makefile ++++ b/scripts/kconfig/Makefile +@@ -149,6 +149,9 @@ check-lxdialog := $(srctree)/$(src)/lxd + # we really need to do so. (Do not call gcc as part of make mrproper) + HOST_EXTRACFLAGS += $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags) \ + -DLOCALE ++ifeq ($(shell uname -s),Darwin) ++HOST_LOADLIBES += -lncurses ++endif + + # =========================================================================== + # Shared Makefile for the various kconfig executables: +--- a/scripts/mod/mk_elfconfig.c ++++ b/scripts/mod/mk_elfconfig.c +@@ -1,7 +1,11 @@ + #include + #include + #include ++#ifndef __APPLE__ + #include ++#else ++#include "elf.h" ++#endif + + int + main(int argc, char **argv) +--- a/scripts/mod/modpost.h ++++ b/scripts/mod/modpost.h +@@ -7,7 +7,11 @@ + #include + #include + #include ++#if !(defined(__APPLE__) || defined(__CYGWIN__)) + #include ++#else ++#include "elf.h" ++#endif + + #include "elfconfig.h" + +--- /dev/null ++++ b/scripts/mod/elf.h +@@ -0,0 +1,3007 @@ ++/* This file defines standard ELF types, structures, and macros. ++ Copyright (C) 1995-2012 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, see ++ . */ ++ ++#ifndef _ELF_H ++#define _ELF_H 1 ++ ++/* Standard ELF types. */ ++ ++#include ++ ++/* Type for a 16-bit quantity. */ ++typedef uint16_t Elf32_Half; ++typedef uint16_t Elf64_Half; ++ ++/* Types for signed and unsigned 32-bit quantities. */ ++typedef uint32_t Elf32_Word; ++typedef int32_t Elf32_Sword; ++typedef uint32_t Elf64_Word; ++typedef int32_t Elf64_Sword; ++ ++/* Types for signed and unsigned 64-bit quantities. */ ++typedef uint64_t Elf32_Xword; ++typedef int64_t Elf32_Sxword; ++typedef uint64_t Elf64_Xword; ++typedef int64_t Elf64_Sxword; ++ ++/* Type of addresses. */ ++typedef uint32_t Elf32_Addr; ++typedef uint64_t Elf64_Addr; ++ ++/* Type of file offsets. */ ++typedef uint32_t Elf32_Off; ++typedef uint64_t Elf64_Off; ++ ++/* Type for section indices, which are 16-bit quantities. */ ++typedef uint16_t Elf32_Section; ++typedef uint16_t Elf64_Section; ++ ++/* Type for version symbol information. */ ++typedef Elf32_Half Elf32_Versym; ++typedef Elf64_Half Elf64_Versym; ++ ++ ++/* The ELF file header. This appears at the start of every ELF file. */ ++ ++#define EI_NIDENT (16) ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf32_Half e_type; /* Object file type */ ++ Elf32_Half e_machine; /* Architecture */ ++ Elf32_Word e_version; /* Object file version */ ++ Elf32_Addr e_entry; /* Entry point virtual address */ ++ Elf32_Off e_phoff; /* Program header table file offset */ ++ Elf32_Off e_shoff; /* Section header table file offset */ ++ Elf32_Word e_flags; /* Processor-specific flags */ ++ Elf32_Half e_ehsize; /* ELF header size in bytes */ ++ Elf32_Half e_phentsize; /* Program header table entry size */ ++ Elf32_Half e_phnum; /* Program header table entry count */ ++ Elf32_Half e_shentsize; /* Section header table entry size */ ++ Elf32_Half e_shnum; /* Section header table entry count */ ++ Elf32_Half e_shstrndx; /* Section header string table index */ ++} Elf32_Ehdr; ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf64_Half e_type; /* Object file type */ ++ Elf64_Half e_machine; /* Architecture */ ++ Elf64_Word e_version; /* Object file version */ ++ Elf64_Addr e_entry; /* Entry point virtual address */ ++ Elf64_Off e_phoff; /* Program header table file offset */ ++ Elf64_Off e_shoff; /* Section header table file offset */ ++ Elf64_Word e_flags; /* Processor-specific flags */ ++ Elf64_Half e_ehsize; /* ELF header size in bytes */ ++ Elf64_Half e_phentsize; /* Program header table entry size */ ++ Elf64_Half e_phnum; /* Program header table entry count */ ++ Elf64_Half e_shentsize; /* Section header table entry size */ ++ Elf64_Half e_shnum; /* Section header table entry count */ ++ Elf64_Half e_shstrndx; /* Section header string table index */ ++} Elf64_Ehdr; ++ ++/* Fields in the e_ident array. The EI_* macros are indices into the ++ array. The macros under each EI_* macro are the values the byte ++ may have. */ ++ ++#define EI_MAG0 0 /* File identification byte 0 index */ ++#define ELFMAG0 0x7f /* Magic number byte 0 */ ++ ++#define EI_MAG1 1 /* File identification byte 1 index */ ++#define ELFMAG1 'E' /* Magic number byte 1 */ ++ ++#define EI_MAG2 2 /* File identification byte 2 index */ ++#define ELFMAG2 'L' /* Magic number byte 2 */ ++ ++#define EI_MAG3 3 /* File identification byte 3 index */ ++#define ELFMAG3 'F' /* Magic number byte 3 */ ++ ++/* Conglomeration of the identification bytes, for easy testing as a word. */ ++#define ELFMAG "\177ELF" ++#define SELFMAG 4 ++ ++#define EI_CLASS 4 /* File class byte index */ ++#define ELFCLASSNONE 0 /* Invalid class */ ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++#define ELFCLASSNUM 3 ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATANONE 0 /* Invalid data encoding */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ ++#define ELFDATANUM 3 ++ ++#define EI_VERSION 6 /* File version byte index */ ++ /* Value must be EV_CURRENT */ ++ ++#define EI_OSABI 7 /* OS ABI identification */ ++#define ELFOSABI_NONE 0 /* UNIX System V ABI */ ++#define ELFOSABI_SYSV 0 /* Alias. */ ++#define ELFOSABI_HPUX 1 /* HP-UX */ ++#define ELFOSABI_NETBSD 2 /* NetBSD. */ ++#define ELFOSABI_GNU 3 /* Object uses GNU ELF extensions. */ ++#define ELFOSABI_LINUX ELFOSABI_GNU /* Compatibility alias. */ ++#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ ++#define ELFOSABI_AIX 7 /* IBM AIX. */ ++#define ELFOSABI_IRIX 8 /* SGI Irix. */ ++#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ ++#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ ++#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ ++#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ ++#define ELFOSABI_ARM_AEABI 64 /* ARM EABI */ ++#define ELFOSABI_ARM 97 /* ARM */ ++#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ ++ ++#define EI_ABIVERSION 8 /* ABI version */ ++ ++#define EI_PAD 9 /* Byte index of padding bytes */ ++ ++/* Legal values for e_type (object file type). */ ++ ++#define ET_NONE 0 /* No file type */ ++#define ET_REL 1 /* Relocatable file */ ++#define ET_EXEC 2 /* Executable file */ ++#define ET_DYN 3 /* Shared object file */ ++#define ET_CORE 4 /* Core file */ ++#define ET_NUM 5 /* Number of defined types */ ++#define ET_LOOS 0xfe00 /* OS-specific range start */ ++#define ET_HIOS 0xfeff /* OS-specific range end */ ++#define ET_LOPROC 0xff00 /* Processor-specific range start */ ++#define ET_HIPROC 0xffff /* Processor-specific range end */ ++ ++/* Legal values for e_machine (architecture). */ ++ ++#define EM_NONE 0 /* No machine */ ++#define EM_M32 1 /* AT&T WE 32100 */ ++#define EM_SPARC 2 /* SUN SPARC */ ++#define EM_386 3 /* Intel 80386 */ ++#define EM_68K 4 /* Motorola m68k family */ ++#define EM_88K 5 /* Motorola m88k family */ ++#define EM_860 7 /* Intel 80860 */ ++#define EM_MIPS 8 /* MIPS R3000 big-endian */ ++#define EM_S370 9 /* IBM System/370 */ ++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ ++ ++#define EM_PARISC 15 /* HPPA */ ++#define EM_VPP500 17 /* Fujitsu VPP500 */ ++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ ++#define EM_960 19 /* Intel 80960 */ ++#define EM_PPC 20 /* PowerPC */ ++#define EM_PPC64 21 /* PowerPC 64-bit */ ++#define EM_S390 22 /* IBM S390 */ ++ ++#define EM_V800 36 /* NEC V800 series */ ++#define EM_FR20 37 /* Fujitsu FR20 */ ++#define EM_RH32 38 /* TRW RH-32 */ ++#define EM_RCE 39 /* Motorola RCE */ ++#define EM_ARM 40 /* ARM */ ++#define EM_FAKE_ALPHA 41 /* Digital Alpha */ ++#define EM_SH 42 /* Hitachi SH */ ++#define EM_SPARCV9 43 /* SPARC v9 64-bit */ ++#define EM_TRICORE 44 /* Siemens Tricore */ ++#define EM_ARC 45 /* Argonaut RISC Core */ ++#define EM_H8_300 46 /* Hitachi H8/300 */ ++#define EM_H8_300H 47 /* Hitachi H8/300H */ ++#define EM_H8S 48 /* Hitachi H8S */ ++#define EM_H8_500 49 /* Hitachi H8/500 */ ++#define EM_IA_64 50 /* Intel Merced */ ++#define EM_MIPS_X 51 /* Stanford MIPS-X */ ++#define EM_COLDFIRE 52 /* Motorola Coldfire */ ++#define EM_68HC12 53 /* Motorola M68HC12 */ ++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ ++#define EM_PCP 55 /* Siemens PCP */ ++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ ++#define EM_NDR1 57 /* Denso NDR1 microprocessor */ ++#define EM_STARCORE 58 /* Motorola Start*Core processor */ ++#define EM_ME16 59 /* Toyota ME16 processor */ ++#define EM_ST100 60 /* STMicroelectronic ST100 processor */ ++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ ++#define EM_X86_64 62 /* AMD x86-64 architecture */ ++#define EM_PDSP 63 /* Sony DSP Processor */ ++ ++#define EM_FX66 66 /* Siemens FX66 microcontroller */ ++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ ++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ ++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ ++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ ++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ ++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ ++#define EM_SVX 73 /* Silicon Graphics SVx */ ++#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ ++#define EM_VAX 75 /* Digital VAX */ ++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ ++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ ++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ ++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ ++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ ++#define EM_HUANY 81 /* Harvard University machine-independent object files */ ++#define EM_PRISM 82 /* SiTera Prism */ ++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ ++#define EM_FR30 84 /* Fujitsu FR30 */ ++#define EM_D10V 85 /* Mitsubishi D10V */ ++#define EM_D30V 86 /* Mitsubishi D30V */ ++#define EM_V850 87 /* NEC v850 */ ++#define EM_M32R 88 /* Mitsubishi M32R */ ++#define EM_MN10300 89 /* Matsushita MN10300 */ ++#define EM_MN10200 90 /* Matsushita MN10200 */ ++#define EM_PJ 91 /* picoJava */ ++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ ++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ ++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ ++#define EM_TILEPRO 188 /* Tilera TILEPro */ ++#define EM_TILEGX 191 /* Tilera TILE-Gx */ ++#define EM_NUM 192 ++ ++/* If it is necessary to assign new unofficial EM_* values, please ++ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the ++ chances of collision with official or non-GNU unofficial values. */ ++ ++#define EM_ALPHA 0x9026 ++ ++/* Legal values for e_version (version). */ ++ ++#define EV_NONE 0 /* Invalid ELF version */ ++#define EV_CURRENT 1 /* Current version */ ++#define EV_NUM 2 ++ ++/* Section header. */ ++ ++typedef struct ++{ ++ Elf32_Word sh_name; /* Section name (string tbl index) */ ++ Elf32_Word sh_type; /* Section type */ ++ Elf32_Word sh_flags; /* Section flags */ ++ Elf32_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf32_Off sh_offset; /* Section file offset */ ++ Elf32_Word sh_size; /* Section size in bytes */ ++ Elf32_Word sh_link; /* Link to another section */ ++ Elf32_Word sh_info; /* Additional section information */ ++ Elf32_Word sh_addralign; /* Section alignment */ ++ Elf32_Word sh_entsize; /* Entry size if section holds table */ ++} Elf32_Shdr; ++ ++typedef struct ++{ ++ Elf64_Word sh_name; /* Section name (string tbl index) */ ++ Elf64_Word sh_type; /* Section type */ ++ Elf64_Xword sh_flags; /* Section flags */ ++ Elf64_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf64_Off sh_offset; /* Section file offset */ ++ Elf64_Xword sh_size; /* Section size in bytes */ ++ Elf64_Word sh_link; /* Link to another section */ ++ Elf64_Word sh_info; /* Additional section information */ ++ Elf64_Xword sh_addralign; /* Section alignment */ ++ Elf64_Xword sh_entsize; /* Entry size if section holds table */ ++} Elf64_Shdr; ++ ++/* Special section indices. */ ++ ++#define SHN_UNDEF 0 /* Undefined section */ ++#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ ++#define SHN_LOPROC 0xff00 /* Start of processor-specific */ ++#define SHN_BEFORE 0xff00 /* Order section before all others ++ (Solaris). */ ++#define SHN_AFTER 0xff01 /* Order section after all others ++ (Solaris). */ ++#define SHN_HIPROC 0xff1f /* End of processor-specific */ ++#define SHN_LOOS 0xff20 /* Start of OS-specific */ ++#define SHN_HIOS 0xff3f /* End of OS-specific */ ++#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ ++#define SHN_COMMON 0xfff2 /* Associated symbol is common */ ++#define SHN_XINDEX 0xffff /* Index is in extra table. */ ++#define SHN_HIRESERVE 0xffff /* End of reserved indices */ ++ ++/* Legal values for sh_type (section type). */ ++ ++#define SHT_NULL 0 /* Section header table entry unused */ ++#define SHT_PROGBITS 1 /* Program data */ ++#define SHT_SYMTAB 2 /* Symbol table */ ++#define SHT_STRTAB 3 /* String table */ ++#define SHT_RELA 4 /* Relocation entries with addends */ ++#define SHT_HASH 5 /* Symbol hash table */ ++#define SHT_DYNAMIC 6 /* Dynamic linking information */ ++#define SHT_NOTE 7 /* Notes */ ++#define SHT_NOBITS 8 /* Program space with no data (bss) */ ++#define SHT_REL 9 /* Relocation entries, no addends */ ++#define SHT_SHLIB 10 /* Reserved */ ++#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ ++#define SHT_INIT_ARRAY 14 /* Array of constructors */ ++#define SHT_FINI_ARRAY 15 /* Array of destructors */ ++#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ ++#define SHT_GROUP 17 /* Section group */ ++#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ ++#define SHT_NUM 19 /* Number of defined types. */ ++#define SHT_LOOS 0x60000000 /* Start OS-specific. */ ++#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes. */ ++#define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ ++#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ ++#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ ++#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ ++#define SHT_SUNW_move 0x6ffffffa ++#define SHT_SUNW_COMDAT 0x6ffffffb ++#define SHT_SUNW_syminfo 0x6ffffffc ++#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ ++#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ ++#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ ++#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ ++#define SHT_HIOS 0x6fffffff /* End OS-specific type */ ++#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define SHT_LOUSER 0x80000000 /* Start of application-specific */ ++#define SHT_HIUSER 0x8fffffff /* End of application-specific */ ++ ++/* Legal values for sh_flags (section flags). */ ++ ++#define SHF_WRITE (1 << 0) /* Writable */ ++#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ ++#define SHF_EXECINSTR (1 << 2) /* Executable */ ++#define SHF_MERGE (1 << 4) /* Might be merged */ ++#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ ++#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ ++#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ ++#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling ++ required */ ++#define SHF_GROUP (1 << 9) /* Section is member of a group. */ ++#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ ++#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ ++#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ ++#define SHF_ORDERED (1 << 30) /* Special ordering requirement ++ (Solaris). */ ++#define SHF_EXCLUDE (1 << 31) /* Section is excluded unless ++ referenced or allocated (Solaris).*/ ++ ++/* Section group handling. */ ++#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ ++ ++/* Symbol table entry. */ ++ ++typedef struct ++{ ++ Elf32_Word st_name; /* Symbol name (string tbl index) */ ++ Elf32_Addr st_value; /* Symbol value */ ++ Elf32_Word st_size; /* Symbol size */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf32_Section st_shndx; /* Section index */ ++} Elf32_Sym; ++ ++typedef struct ++{ ++ Elf64_Word st_name; /* Symbol name (string tbl index) */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf64_Section st_shndx; /* Section index */ ++ Elf64_Addr st_value; /* Symbol value */ ++ Elf64_Xword st_size; /* Symbol size */ ++} Elf64_Sym; ++ ++/* The syminfo section if available contains additional information about ++ every dynamic symbol. */ ++ ++typedef struct ++{ ++ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf32_Half si_flags; /* Per symbol flags */ ++} Elf32_Syminfo; ++ ++typedef struct ++{ ++ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf64_Half si_flags; /* Per symbol flags */ ++} Elf64_Syminfo; ++ ++/* Possible values for si_boundto. */ ++#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ ++#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ ++#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ ++ ++/* Possible bitmasks for si_flags. */ ++#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ ++#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ ++#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ ++#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy ++ loaded */ ++/* Syminfo version values. */ ++#define SYMINFO_NONE 0 ++#define SYMINFO_CURRENT 1 ++#define SYMINFO_NUM 2 ++ ++ ++/* How to extract and insert information held in the st_info field. */ ++ ++#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) ++#define ELF32_ST_TYPE(val) ((val) & 0xf) ++#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) ++ ++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ ++#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) ++#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) ++#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) ++ ++/* Legal values for ST_BIND subfield of st_info (symbol binding). */ ++ ++#define STB_LOCAL 0 /* Local symbol */ ++#define STB_GLOBAL 1 /* Global symbol */ ++#define STB_WEAK 2 /* Weak symbol */ ++#define STB_NUM 3 /* Number of defined types. */ ++#define STB_LOOS 10 /* Start of OS-specific */ ++#define STB_GNU_UNIQUE 10 /* Unique symbol. */ ++#define STB_HIOS 12 /* End of OS-specific */ ++#define STB_LOPROC 13 /* Start of processor-specific */ ++#define STB_HIPROC 15 /* End of processor-specific */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_NOTYPE 0 /* Symbol type is unspecified */ ++#define STT_OBJECT 1 /* Symbol is a data object */ ++#define STT_FUNC 2 /* Symbol is a code object */ ++#define STT_SECTION 3 /* Symbol associated with a section */ ++#define STT_FILE 4 /* Symbol's name is file name */ ++#define STT_COMMON 5 /* Symbol is a common data object */ ++#define STT_TLS 6 /* Symbol is thread-local data object*/ ++#define STT_NUM 7 /* Number of defined types. */ ++#define STT_LOOS 10 /* Start of OS-specific */ ++#define STT_GNU_IFUNC 10 /* Symbol is indirect code object */ ++#define STT_HIOS 12 /* End of OS-specific */ ++#define STT_LOPROC 13 /* Start of processor-specific */ ++#define STT_HIPROC 15 /* End of processor-specific */ ++ ++ ++/* Symbol table indices are found in the hash buckets and chain table ++ of a symbol hash table section. This special index value indicates ++ the end of a chain, meaning no further symbols are found in that bucket. */ ++ ++#define STN_UNDEF 0 /* End of a chain. */ ++ ++ ++/* How to extract and insert information held in the st_other field. */ ++ ++#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) ++ ++/* For ELF64 the definitions are the same. */ ++#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) ++ ++/* Symbol visibility specification encoded in the st_other field. */ ++#define STV_DEFAULT 0 /* Default symbol visibility rules */ ++#define STV_INTERNAL 1 /* Processor specific hidden class */ ++#define STV_HIDDEN 2 /* Sym unavailable in other modules */ ++#define STV_PROTECTED 3 /* Not preemptible, not exported */ ++ ++ ++/* Relocation table entry without addend (in section of type SHT_REL). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++} Elf32_Rel; ++ ++/* I have seen two different definitions of the Elf64_Rel and ++ Elf64_Rela structures, so we'll leave them out until Novell (or ++ whoever) gets their act together. */ ++/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++} Elf64_Rel; ++ ++/* Relocation table entry with addend (in section of type SHT_RELA). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++ Elf32_Sword r_addend; /* Addend */ ++} Elf32_Rela; ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++ Elf64_Sxword r_addend; /* Addend */ ++} Elf64_Rela; ++ ++/* How to extract and insert information held in the r_info field. */ ++ ++#define ELF32_R_SYM(val) ((val) >> 8) ++#define ELF32_R_TYPE(val) ((val) & 0xff) ++#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) ++ ++#define ELF64_R_SYM(i) ((i) >> 32) ++#define ELF64_R_TYPE(i) ((i) & 0xffffffff) ++#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) ++ ++/* Program segment header. */ ++ ++typedef struct ++{ ++ Elf32_Word p_type; /* Segment type */ ++ Elf32_Off p_offset; /* Segment file offset */ ++ Elf32_Addr p_vaddr; /* Segment virtual address */ ++ Elf32_Addr p_paddr; /* Segment physical address */ ++ Elf32_Word p_filesz; /* Segment size in file */ ++ Elf32_Word p_memsz; /* Segment size in memory */ ++ Elf32_Word p_flags; /* Segment flags */ ++ Elf32_Word p_align; /* Segment alignment */ ++} Elf32_Phdr; ++ ++typedef struct ++{ ++ Elf64_Word p_type; /* Segment type */ ++ Elf64_Word p_flags; /* Segment flags */ ++ Elf64_Off p_offset; /* Segment file offset */ ++ Elf64_Addr p_vaddr; /* Segment virtual address */ ++ Elf64_Addr p_paddr; /* Segment physical address */ ++ Elf64_Xword p_filesz; /* Segment size in file */ ++ Elf64_Xword p_memsz; /* Segment size in memory */ ++ Elf64_Xword p_align; /* Segment alignment */ ++} Elf64_Phdr; ++ ++/* Special value for e_phnum. This indicates that the real number of ++ program headers is too large to fit into e_phnum. Instead the real ++ value is in the field sh_info of section 0. */ ++ ++#define PN_XNUM 0xffff ++ ++/* Legal values for p_type (segment type). */ ++ ++#define PT_NULL 0 /* Program header table entry unused */ ++#define PT_LOAD 1 /* Loadable program segment */ ++#define PT_DYNAMIC 2 /* Dynamic linking information */ ++#define PT_INTERP 3 /* Program interpreter */ ++#define PT_NOTE 4 /* Auxiliary information */ ++#define PT_SHLIB 5 /* Reserved */ ++#define PT_PHDR 6 /* Entry for header table itself */ ++#define PT_TLS 7 /* Thread-local storage segment */ ++#define PT_NUM 8 /* Number of defined types */ ++#define PT_LOOS 0x60000000 /* Start of OS-specific */ ++#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ ++#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ ++#define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ ++#define PT_LOSUNW 0x6ffffffa ++#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ ++#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ ++#define PT_HISUNW 0x6fffffff ++#define PT_HIOS 0x6fffffff /* End of OS-specific */ ++#define PT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define PT_HIPROC 0x7fffffff /* End of processor-specific */ ++ ++/* Legal values for p_flags (segment flags). */ ++ ++#define PF_X (1 << 0) /* Segment is executable */ ++#define PF_W (1 << 1) /* Segment is writable */ ++#define PF_R (1 << 2) /* Segment is readable */ ++#define PF_MASKOS 0x0ff00000 /* OS-specific */ ++#define PF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Legal values for note segment descriptor types for core files. */ ++ ++#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ ++#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ ++#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ ++#define NT_PRXREG 4 /* Contains copy of prxregset struct */ ++#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ ++#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ ++#define NT_AUXV 6 /* Contains copy of auxv array */ ++#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ ++#define NT_ASRS 8 /* Contains copy of asrset struct */ ++#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ ++#define NT_PSINFO 13 /* Contains copy of psinfo struct */ ++#define NT_PRCRED 14 /* Contains copy of prcred struct */ ++#define NT_UTSNAME 15 /* Contains copy of utsname struct */ ++#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ ++#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ ++#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ ++#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ ++#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ ++#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ ++#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ ++#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ ++#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ ++#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ ++ ++/* Legal values for the note segment descriptor types for object files. */ ++ ++#define NT_VERSION 1 /* Contains a version string. */ ++ ++ ++/* Dynamic section entry. */ ++ ++typedef struct ++{ ++ Elf32_Sword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf32_Word d_val; /* Integer value */ ++ Elf32_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf32_Dyn; ++ ++typedef struct ++{ ++ Elf64_Sxword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf64_Xword d_val; /* Integer value */ ++ Elf64_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf64_Dyn; ++ ++/* Legal values for d_tag (dynamic entry type). */ ++ ++#define DT_NULL 0 /* Marks end of dynamic section */ ++#define DT_NEEDED 1 /* Name of needed library */ ++#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ ++#define DT_PLTGOT 3 /* Processor defined value */ ++#define DT_HASH 4 /* Address of symbol hash table */ ++#define DT_STRTAB 5 /* Address of string table */ ++#define DT_SYMTAB 6 /* Address of symbol table */ ++#define DT_RELA 7 /* Address of Rela relocs */ ++#define DT_RELASZ 8 /* Total size of Rela relocs */ ++#define DT_RELAENT 9 /* Size of one Rela reloc */ ++#define DT_STRSZ 10 /* Size of string table */ ++#define DT_SYMENT 11 /* Size of one symbol table entry */ ++#define DT_INIT 12 /* Address of init function */ ++#define DT_FINI 13 /* Address of termination function */ ++#define DT_SONAME 14 /* Name of shared object */ ++#define DT_RPATH 15 /* Library search path (deprecated) */ ++#define DT_SYMBOLIC 16 /* Start symbol search here */ ++#define DT_REL 17 /* Address of Rel relocs */ ++#define DT_RELSZ 18 /* Total size of Rel relocs */ ++#define DT_RELENT 19 /* Size of one Rel reloc */ ++#define DT_PLTREL 20 /* Type of reloc in PLT */ ++#define DT_DEBUG 21 /* For debugging; unspecified */ ++#define DT_TEXTREL 22 /* Reloc might modify .text */ ++#define DT_JMPREL 23 /* Address of PLT relocs */ ++#define DT_BIND_NOW 24 /* Process relocations of object */ ++#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ ++#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ ++#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ ++#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ ++#define DT_RUNPATH 29 /* Library search path */ ++#define DT_FLAGS 30 /* Flags for the object being loaded */ ++#define DT_ENCODING 32 /* Start of encoded range */ ++#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ ++#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ ++#define DT_NUM 34 /* Number used */ ++#define DT_LOOS 0x6000000d /* Start of OS-specific */ ++#define DT_HIOS 0x6ffff000 /* End of OS-specific */ ++#define DT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define DT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ ++ ++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the ++ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's ++ approach. */ ++#define DT_VALRNGLO 0x6ffffd00 ++#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ ++#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ ++#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ ++#define DT_CHECKSUM 0x6ffffdf8 ++#define DT_PLTPADSZ 0x6ffffdf9 ++#define DT_MOVEENT 0x6ffffdfa ++#define DT_MOVESZ 0x6ffffdfb ++#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ ++#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting ++ the following DT_* entry. */ ++#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ ++#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ ++#define DT_VALRNGHI 0x6ffffdff ++#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ ++#define DT_VALNUM 12 ++ ++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the ++ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. ++ ++ If any adjustment is made to the ELF object after it has been ++ built these entries will need to be adjusted. */ ++#define DT_ADDRRNGLO 0x6ffffe00 ++#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ ++#define DT_TLSDESC_PLT 0x6ffffef6 ++#define DT_TLSDESC_GOT 0x6ffffef7 ++#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ ++#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ ++#define DT_CONFIG 0x6ffffefa /* Configuration information. */ ++#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ ++#define DT_AUDIT 0x6ffffefc /* Object auditing. */ ++#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ ++#define DT_MOVETAB 0x6ffffefe /* Move table. */ ++#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ ++#define DT_ADDRRNGHI 0x6ffffeff ++#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ ++#define DT_ADDRNUM 11 ++ ++/* The versioning entry types. The next are defined as part of the ++ GNU extension. */ ++#define DT_VERSYM 0x6ffffff0 ++ ++#define DT_RELACOUNT 0x6ffffff9 ++#define DT_RELCOUNT 0x6ffffffa ++ ++/* These were chosen by Sun. */ ++#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ ++#define DT_VERDEF 0x6ffffffc /* Address of version definition ++ table */ ++#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ ++#define DT_VERNEED 0x6ffffffe /* Address of table with needed ++ versions */ ++#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ ++#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ ++#define DT_VERSIONTAGNUM 16 ++ ++/* Sun added these machine-independent extensions in the "processor-specific" ++ range. Be compatible. */ ++#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ ++#define DT_FILTER 0x7fffffff /* Shared object to get values from */ ++#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) ++#define DT_EXTRANUM 3 ++ ++/* Values of `d_un.d_val' in the DT_FLAGS entry. */ ++#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ ++#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ ++#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ ++#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ ++#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ ++ ++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 ++ entry in the dynamic section. */ ++#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ ++#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ ++#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ ++#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ ++#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ ++#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ ++#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ ++#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ ++#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ ++#define DF_1_TRANS 0x00000200 ++#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ ++#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ ++#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ ++#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ ++#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ ++#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ ++#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ ++ ++/* Flags for the feature selection in DT_FEATURE_1. */ ++#define DTF_1_PARINIT 0x00000001 ++#define DTF_1_CONFEXP 0x00000002 ++ ++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ ++#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ ++#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not ++ generally available. */ ++ ++/* Version definition sections. */ ++ ++typedef struct ++{ ++ Elf32_Half vd_version; /* Version revision */ ++ Elf32_Half vd_flags; /* Version information */ ++ Elf32_Half vd_ndx; /* Version Index */ ++ Elf32_Half vd_cnt; /* Number of associated aux entries */ ++ Elf32_Word vd_hash; /* Version name hash value */ ++ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf32_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf32_Verdef; ++ ++typedef struct ++{ ++ Elf64_Half vd_version; /* Version revision */ ++ Elf64_Half vd_flags; /* Version information */ ++ Elf64_Half vd_ndx; /* Version Index */ ++ Elf64_Half vd_cnt; /* Number of associated aux entries */ ++ Elf64_Word vd_hash; /* Version name hash value */ ++ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf64_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf64_Verdef; ++ ++ ++/* Legal values for vd_version (version revision). */ ++#define VER_DEF_NONE 0 /* No version */ ++#define VER_DEF_CURRENT 1 /* Current version */ ++#define VER_DEF_NUM 2 /* Given version number */ ++ ++/* Legal values for vd_flags (version information flags). */ ++#define VER_FLG_BASE 0x1 /* Version definition of file itself */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++/* Versym symbol index values. */ ++#define VER_NDX_LOCAL 0 /* Symbol is local. */ ++#define VER_NDX_GLOBAL 1 /* Symbol is global. */ ++#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ ++#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ ++ ++/* Auxialiary version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vda_name; /* Version or dependency names */ ++ Elf32_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf32_Verdaux; ++ ++typedef struct ++{ ++ Elf64_Word vda_name; /* Version or dependency names */ ++ Elf64_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf64_Verdaux; ++ ++ ++/* Version dependency section. */ ++ ++typedef struct ++{ ++ Elf32_Half vn_version; /* Version of structure */ ++ Elf32_Half vn_cnt; /* Number of associated aux entries */ ++ Elf32_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf32_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf32_Verneed; ++ ++typedef struct ++{ ++ Elf64_Half vn_version; /* Version of structure */ ++ Elf64_Half vn_cnt; /* Number of associated aux entries */ ++ Elf64_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf64_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf64_Verneed; ++ ++ ++/* Legal values for vn_version (version revision). */ ++#define VER_NEED_NONE 0 /* No version */ ++#define VER_NEED_CURRENT 1 /* Current version */ ++#define VER_NEED_NUM 2 /* Given version number */ ++ ++/* Auxiliary needed version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vna_hash; /* Hash value of dependency name */ ++ Elf32_Half vna_flags; /* Dependency specific information */ ++ Elf32_Half vna_other; /* Unused */ ++ Elf32_Word vna_name; /* Dependency name string offset */ ++ Elf32_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf32_Vernaux; ++ ++typedef struct ++{ ++ Elf64_Word vna_hash; /* Hash value of dependency name */ ++ Elf64_Half vna_flags; /* Dependency specific information */ ++ Elf64_Half vna_other; /* Unused */ ++ Elf64_Word vna_name; /* Dependency name string offset */ ++ Elf64_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf64_Vernaux; ++ ++ ++/* Legal values for vna_flags. */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++ ++/* Auxiliary vector. */ ++ ++/* This vector is normally only used by the program interpreter. The ++ usual definition in an ABI supplement uses the name auxv_t. The ++ vector is not usually defined in a standard file, but it ++ can't hurt. We rename it to avoid conflicts. The sizes of these ++ types are an arrangement between the exec server and the program ++ interpreter, so we don't fully specify them here. */ ++ ++typedef struct ++{ ++ uint32_t a_type; /* Entry type */ ++ union ++ { ++ uint32_t a_val; /* Integer value */ ++ /* We use to have pointer elements added here. We cannot do that, ++ though, since it does not work when using 32-bit definitions ++ on 64-bit platforms and vice versa. */ ++ } a_un; ++} Elf32_auxv_t; ++ ++typedef struct ++{ ++ uint64_t a_type; /* Entry type */ ++ union ++ { ++ uint64_t a_val; /* Integer value */ ++ /* We use to have pointer elements added here. We cannot do that, ++ though, since it does not work when using 32-bit definitions ++ on 64-bit platforms and vice versa. */ ++ } a_un; ++} Elf64_auxv_t; ++ ++/* Legal values for a_type (entry type). */ ++ ++#define AT_NULL 0 /* End of vector */ ++#define AT_IGNORE 1 /* Entry should be ignored */ ++#define AT_EXECFD 2 /* File descriptor of program */ ++#define AT_PHDR 3 /* Program headers for program */ ++#define AT_PHENT 4 /* Size of program header entry */ ++#define AT_PHNUM 5 /* Number of program headers */ ++#define AT_PAGESZ 6 /* System page size */ ++#define AT_BASE 7 /* Base address of interpreter */ ++#define AT_FLAGS 8 /* Flags */ ++#define AT_ENTRY 9 /* Entry point of program */ ++#define AT_NOTELF 10 /* Program is not ELF */ ++#define AT_UID 11 /* Real uid */ ++#define AT_EUID 12 /* Effective uid */ ++#define AT_GID 13 /* Real gid */ ++#define AT_EGID 14 /* Effective gid */ ++#define AT_CLKTCK 17 /* Frequency of times() */ ++ ++/* Some more special a_type values describing the hardware. */ ++#define AT_PLATFORM 15 /* String identifying platform. */ ++#define AT_HWCAP 16 /* Machine dependent hints about ++ processor capabilities. */ ++ ++/* This entry gives some information about the FPU initialization ++ performed by the kernel. */ ++#define AT_FPUCW 18 /* Used FPU control word. */ ++ ++/* Cache block sizes. */ ++#define AT_DCACHEBSIZE 19 /* Data cache block size. */ ++#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ ++#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ ++ ++/* A special ignored value for PPC, used by the kernel to control the ++ interpretation of the AUXV. Must be > 16. */ ++#define AT_IGNOREPPC 22 /* Entry should be ignored. */ ++ ++#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ ++ ++#define AT_BASE_PLATFORM 24 /* String identifying real platforms.*/ ++ ++#define AT_RANDOM 25 /* Address of 16 random bytes. */ ++ ++#define AT_EXECFN 31 /* Filename of executable. */ ++ ++/* Pointer to the global system page used for system calls and other ++ nice things. */ ++#define AT_SYSINFO 32 ++#define AT_SYSINFO_EHDR 33 ++ ++/* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains ++ log2 of line size; mask those to get cache size. */ ++#define AT_L1I_CACHESHAPE 34 ++#define AT_L1D_CACHESHAPE 35 ++#define AT_L2_CACHESHAPE 36 ++#define AT_L3_CACHESHAPE 37 ++ ++/* Note section contents. Each entry in the note section begins with ++ a header of a fixed form. */ ++ ++typedef struct ++{ ++ Elf32_Word n_namesz; /* Length of the note's name. */ ++ Elf32_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf32_Word n_type; /* Type of the note. */ ++} Elf32_Nhdr; ++ ++typedef struct ++{ ++ Elf64_Word n_namesz; /* Length of the note's name. */ ++ Elf64_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf64_Word n_type; /* Type of the note. */ ++} Elf64_Nhdr; ++ ++/* Known names of notes. */ ++ ++/* Solaris entries in the note section have this name. */ ++#define ELF_NOTE_SOLARIS "SUNW Solaris" ++ ++/* Note entries for GNU systems have this name. */ ++#define ELF_NOTE_GNU "GNU" ++ ++ ++/* Defined types of notes for Solaris. */ ++ ++/* Value of descriptor (one word) is desired pagesize for the binary. */ ++#define ELF_NOTE_PAGESIZE_HINT 1 ++ ++ ++/* Defined note types for GNU systems. */ ++ ++/* ABI information. The descriptor consists of words: ++ word 0: OS descriptor ++ word 1: major version of the ABI ++ word 2: minor version of the ABI ++ word 3: subminor version of the ABI ++*/ ++#define NT_GNU_ABI_TAG 1 ++#define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ ++ ++/* Known OSes. These values can appear in word 0 of an ++ NT_GNU_ABI_TAG note section entry. */ ++#define ELF_NOTE_OS_LINUX 0 ++#define ELF_NOTE_OS_GNU 1 ++#define ELF_NOTE_OS_SOLARIS2 2 ++#define ELF_NOTE_OS_FREEBSD 3 ++ ++/* Synthetic hwcap information. The descriptor begins with two words: ++ word 0: number of entries ++ word 1: bitmask of enabled entries ++ Then follow variable-length entries, one byte followed by a ++ '\0'-terminated hwcap name string. The byte gives the bit ++ number to test if enabled, (1U << bit) & bitmask. */ ++#define NT_GNU_HWCAP 2 ++ ++/* Build ID bits as generated by ld --build-id. ++ The descriptor consists of any nonzero number of bytes. */ ++#define NT_GNU_BUILD_ID 3 ++ ++/* Version note generated by GNU gold containing a version string. */ ++#define NT_GNU_GOLD_VERSION 4 ++ ++ ++/* Move records. */ ++typedef struct ++{ ++ Elf32_Xword m_value; /* Symbol value. */ ++ Elf32_Word m_info; /* Size and index. */ ++ Elf32_Word m_poffset; /* Symbol offset. */ ++ Elf32_Half m_repeat; /* Repeat count. */ ++ Elf32_Half m_stride; /* Stride info. */ ++} Elf32_Move; ++ ++typedef struct ++{ ++ Elf64_Xword m_value; /* Symbol value. */ ++ Elf64_Xword m_info; /* Size and index. */ ++ Elf64_Xword m_poffset; /* Symbol offset. */ ++ Elf64_Half m_repeat; /* Repeat count. */ ++ Elf64_Half m_stride; /* Stride info. */ ++} Elf64_Move; ++ ++/* Macro to construct move records. */ ++#define ELF32_M_SYM(info) ((info) >> 8) ++#define ELF32_M_SIZE(info) ((unsigned char) (info)) ++#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) ++ ++#define ELF64_M_SYM(info) ELF32_M_SYM (info) ++#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) ++#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) ++ ++ ++/* Motorola 68k specific definitions. */ ++ ++/* Values for Elf32_Ehdr.e_flags. */ ++#define EF_CPU32 0x00810000 ++ ++/* m68k relocs. */ ++ ++#define R_68K_NONE 0 /* No reloc */ ++#define R_68K_32 1 /* Direct 32 bit */ ++#define R_68K_16 2 /* Direct 16 bit */ ++#define R_68K_8 3 /* Direct 8 bit */ ++#define R_68K_PC32 4 /* PC relative 32 bit */ ++#define R_68K_PC16 5 /* PC relative 16 bit */ ++#define R_68K_PC8 6 /* PC relative 8 bit */ ++#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ ++#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ ++#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ ++#define R_68K_GOT32O 10 /* 32 bit GOT offset */ ++#define R_68K_GOT16O 11 /* 16 bit GOT offset */ ++#define R_68K_GOT8O 12 /* 8 bit GOT offset */ ++#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ ++#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ ++#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ ++#define R_68K_PLT32O 16 /* 32 bit PLT offset */ ++#define R_68K_PLT16O 17 /* 16 bit PLT offset */ ++#define R_68K_PLT8O 18 /* 8 bit PLT offset */ ++#define R_68K_COPY 19 /* Copy symbol at runtime */ ++#define R_68K_GLOB_DAT 20 /* Create GOT entry */ ++#define R_68K_JMP_SLOT 21 /* Create PLT entry */ ++#define R_68K_RELATIVE 22 /* Adjust by program base */ ++#define R_68K_TLS_GD32 25 /* 32 bit GOT offset for GD */ ++#define R_68K_TLS_GD16 26 /* 16 bit GOT offset for GD */ ++#define R_68K_TLS_GD8 27 /* 8 bit GOT offset for GD */ ++#define R_68K_TLS_LDM32 28 /* 32 bit GOT offset for LDM */ ++#define R_68K_TLS_LDM16 29 /* 16 bit GOT offset for LDM */ ++#define R_68K_TLS_LDM8 30 /* 8 bit GOT offset for LDM */ ++#define R_68K_TLS_LDO32 31 /* 32 bit module-relative offset */ ++#define R_68K_TLS_LDO16 32 /* 16 bit module-relative offset */ ++#define R_68K_TLS_LDO8 33 /* 8 bit module-relative offset */ ++#define R_68K_TLS_IE32 34 /* 32 bit GOT offset for IE */ ++#define R_68K_TLS_IE16 35 /* 16 bit GOT offset for IE */ ++#define R_68K_TLS_IE8 36 /* 8 bit GOT offset for IE */ ++#define R_68K_TLS_LE32 37 /* 32 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_LE16 38 /* 16 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_LE8 39 /* 8 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_DTPMOD32 40 /* 32 bit module number */ ++#define R_68K_TLS_DTPREL32 41 /* 32 bit module-relative offset */ ++#define R_68K_TLS_TPREL32 42 /* 32 bit TP-relative offset */ ++/* Keep this the last entry. */ ++#define R_68K_NUM 43 ++ ++/* Intel 80386 specific definitions. */ ++ ++/* i386 relocs. */ ++ ++#define R_386_NONE 0 /* No reloc */ ++#define R_386_32 1 /* Direct 32 bit */ ++#define R_386_PC32 2 /* PC relative 32 bit */ ++#define R_386_GOT32 3 /* 32 bit GOT entry */ ++#define R_386_PLT32 4 /* 32 bit PLT address */ ++#define R_386_COPY 5 /* Copy symbol at runtime */ ++#define R_386_GLOB_DAT 6 /* Create GOT entry */ ++#define R_386_JMP_SLOT 7 /* Create PLT entry */ ++#define R_386_RELATIVE 8 /* Adjust by program base */ ++#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ ++#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ ++#define R_386_32PLT 11 ++#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ ++#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS ++ block offset */ ++#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block ++ offset */ ++#define R_386_TLS_LE 17 /* Offset relative to static TLS ++ block */ ++#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of ++ general dynamic thread local data */ ++#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of ++ local dynamic thread local data ++ in LE code */ ++#define R_386_16 20 ++#define R_386_PC16 21 ++#define R_386_8 22 ++#define R_386_PC8 23 ++#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic ++ thread local data */ ++#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ ++#define R_386_TLS_GD_CALL 26 /* Relocation for call to ++ __tls_get_addr() */ ++#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ ++#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic ++ thread local data in LE code */ ++#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ ++#define R_386_TLS_LDM_CALL 30 /* Relocation for call to ++ __tls_get_addr() in LDM code */ ++#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ ++#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ ++#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS ++ block offset */ ++#define R_386_TLS_LE_32 34 /* Negated offset relative to static ++ TLS block */ ++#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ ++#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ ++#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ ++/* 38? */ ++#define R_386_TLS_GOTDESC 39 /* GOT offset for TLS descriptor. */ ++#define R_386_TLS_DESC_CALL 40 /* Marker of call through TLS ++ descriptor for ++ relaxation. */ ++#define R_386_TLS_DESC 41 /* TLS descriptor containing ++ pointer to code and to ++ argument, returning the TLS ++ offset for the symbol. */ ++#define R_386_IRELATIVE 42 /* Adjust indirectly by program base */ ++/* Keep this the last entry. */ ++#define R_386_NUM 43 ++ ++/* SUN SPARC specific definitions. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ ++ ++/* Values for Elf64_Ehdr.e_flags. */ ++ ++#define EF_SPARCV9_MM 3 ++#define EF_SPARCV9_TSO 0 ++#define EF_SPARCV9_PSO 1 ++#define EF_SPARCV9_RMO 2 ++#define EF_SPARC_LEDATA 0x800000 /* little endian data */ ++#define EF_SPARC_EXT_MASK 0xFFFF00 ++#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ ++#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ ++#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ ++#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ ++ ++/* SPARC relocs. */ ++ ++#define R_SPARC_NONE 0 /* No reloc */ ++#define R_SPARC_8 1 /* Direct 8 bit */ ++#define R_SPARC_16 2 /* Direct 16 bit */ ++#define R_SPARC_32 3 /* Direct 32 bit */ ++#define R_SPARC_DISP8 4 /* PC relative 8 bit */ ++#define R_SPARC_DISP16 5 /* PC relative 16 bit */ ++#define R_SPARC_DISP32 6 /* PC relative 32 bit */ ++#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ ++#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ ++#define R_SPARC_HI22 9 /* High 22 bit */ ++#define R_SPARC_22 10 /* Direct 22 bit */ ++#define R_SPARC_13 11 /* Direct 13 bit */ ++#define R_SPARC_LO10 12 /* Truncated 10 bit */ ++#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ ++#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ ++#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ ++#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ ++#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ ++#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ ++#define R_SPARC_COPY 19 /* Copy symbol at runtime */ ++#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ ++#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ ++#define R_SPARC_RELATIVE 22 /* Adjust by program base */ ++#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ ++ ++/* Additional Sparc64 relocs. */ ++ ++#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ ++#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ ++#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ ++#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ ++#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ ++#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ ++#define R_SPARC_10 30 /* Direct 10 bit */ ++#define R_SPARC_11 31 /* Direct 11 bit */ ++#define R_SPARC_64 32 /* Direct 64 bit */ ++#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ ++#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ ++#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ ++#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ ++#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ ++#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ ++#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ ++#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ ++#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ ++#define R_SPARC_GLOB_JMP 42 /* was part of v9 ABI but was removed */ ++#define R_SPARC_7 43 /* Direct 7 bit */ ++#define R_SPARC_5 44 /* Direct 5 bit */ ++#define R_SPARC_6 45 /* Direct 6 bit */ ++#define R_SPARC_DISP64 46 /* PC relative 64 bit */ ++#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ ++#define R_SPARC_HIX22 48 /* High 22 bit complemented */ ++#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ ++#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ ++#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ ++#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ ++#define R_SPARC_REGISTER 53 /* Global register usage */ ++#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ ++#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ ++#define R_SPARC_TLS_GD_HI22 56 ++#define R_SPARC_TLS_GD_LO10 57 ++#define R_SPARC_TLS_GD_ADD 58 ++#define R_SPARC_TLS_GD_CALL 59 ++#define R_SPARC_TLS_LDM_HI22 60 ++#define R_SPARC_TLS_LDM_LO10 61 ++#define R_SPARC_TLS_LDM_ADD 62 ++#define R_SPARC_TLS_LDM_CALL 63 ++#define R_SPARC_TLS_LDO_HIX22 64 ++#define R_SPARC_TLS_LDO_LOX10 65 ++#define R_SPARC_TLS_LDO_ADD 66 ++#define R_SPARC_TLS_IE_HI22 67 ++#define R_SPARC_TLS_IE_LO10 68 ++#define R_SPARC_TLS_IE_LD 69 ++#define R_SPARC_TLS_IE_LDX 70 ++#define R_SPARC_TLS_IE_ADD 71 ++#define R_SPARC_TLS_LE_HIX22 72 ++#define R_SPARC_TLS_LE_LOX10 73 ++#define R_SPARC_TLS_DTPMOD32 74 ++#define R_SPARC_TLS_DTPMOD64 75 ++#define R_SPARC_TLS_DTPOFF32 76 ++#define R_SPARC_TLS_DTPOFF64 77 ++#define R_SPARC_TLS_TPOFF32 78 ++#define R_SPARC_TLS_TPOFF64 79 ++#define R_SPARC_GOTDATA_HIX22 80 ++#define R_SPARC_GOTDATA_LOX10 81 ++#define R_SPARC_GOTDATA_OP_HIX22 82 ++#define R_SPARC_GOTDATA_OP_LOX10 83 ++#define R_SPARC_GOTDATA_OP 84 ++#define R_SPARC_H34 85 ++#define R_SPARC_SIZE32 86 ++#define R_SPARC_SIZE64 87 ++#define R_SPARC_WDISP10 88 ++#define R_SPARC_JMP_IREL 248 ++#define R_SPARC_IRELATIVE 249 ++#define R_SPARC_GNU_VTINHERIT 250 ++#define R_SPARC_GNU_VTENTRY 251 ++#define R_SPARC_REV32 252 ++/* Keep this the last entry. */ ++#define R_SPARC_NUM 253 ++ ++/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ ++ ++#define DT_SPARC_REGISTER 0x70000001 ++#define DT_SPARC_NUM 2 ++ ++/* MIPS R3000 specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ ++#define EF_MIPS_PIC 2 /* Contains PIC code */ ++#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ ++#define EF_MIPS_XGOT 8 ++#define EF_MIPS_64BIT_WHIRL 16 ++#define EF_MIPS_ABI2 32 ++#define EF_MIPS_ABI_ON32 64 ++#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ ++ ++/* Legal values for MIPS architecture level. */ ++ ++#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* The following are non-official names and should not be used. */ ++ ++#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* Special section indices. */ ++ ++#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ ++#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ ++#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ ++#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ ++#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ ++#define SHT_MIPS_MSYM 0x70000001 ++#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ ++#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ ++#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ ++#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ ++#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ ++#define SHT_MIPS_PACKAGE 0x70000007 ++#define SHT_MIPS_PACKSYM 0x70000008 ++#define SHT_MIPS_RELD 0x70000009 ++#define SHT_MIPS_IFACE 0x7000000b ++#define SHT_MIPS_CONTENT 0x7000000c ++#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ ++#define SHT_MIPS_SHDR 0x70000010 ++#define SHT_MIPS_FDESC 0x70000011 ++#define SHT_MIPS_EXTSYM 0x70000012 ++#define SHT_MIPS_DENSE 0x70000013 ++#define SHT_MIPS_PDESC 0x70000014 ++#define SHT_MIPS_LOCSYM 0x70000015 ++#define SHT_MIPS_AUXSYM 0x70000016 ++#define SHT_MIPS_OPTSYM 0x70000017 ++#define SHT_MIPS_LOCSTR 0x70000018 ++#define SHT_MIPS_LINE 0x70000019 ++#define SHT_MIPS_RFDESC 0x7000001a ++#define SHT_MIPS_DELTASYM 0x7000001b ++#define SHT_MIPS_DELTAINST 0x7000001c ++#define SHT_MIPS_DELTACLASS 0x7000001d ++#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ ++#define SHT_MIPS_DELTADECL 0x7000001f ++#define SHT_MIPS_SYMBOL_LIB 0x70000020 ++#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ ++#define SHT_MIPS_TRANSLATE 0x70000022 ++#define SHT_MIPS_PIXIE 0x70000023 ++#define SHT_MIPS_XLATE 0x70000024 ++#define SHT_MIPS_XLATE_DEBUG 0x70000025 ++#define SHT_MIPS_WHIRL 0x70000026 ++#define SHT_MIPS_EH_REGION 0x70000027 ++#define SHT_MIPS_XLATE_OLD 0x70000028 ++#define SHT_MIPS_PDR_EXCEPTION 0x70000029 ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ ++#define SHF_MIPS_MERGE 0x20000000 ++#define SHF_MIPS_ADDR 0x40000000 ++#define SHF_MIPS_STRINGS 0x80000000 ++#define SHF_MIPS_NOSTRIP 0x08000000 ++#define SHF_MIPS_LOCAL 0x04000000 ++#define SHF_MIPS_NAMES 0x02000000 ++#define SHF_MIPS_NODUPE 0x01000000 ++ ++ ++/* Symbol tables. */ ++ ++/* MIPS specific values for `st_other'. */ ++#define STO_MIPS_DEFAULT 0x0 ++#define STO_MIPS_INTERNAL 0x1 ++#define STO_MIPS_HIDDEN 0x2 ++#define STO_MIPS_PROTECTED 0x3 ++#define STO_MIPS_PLT 0x8 ++#define STO_MIPS_SC_ALIGN_UNUSED 0xff ++ ++/* MIPS specific values for `st_info'. */ ++#define STB_MIPS_SPLIT_COMMON 13 ++ ++/* Entries found in sections of type SHT_MIPS_GPTAB. */ ++ ++typedef union ++{ ++ struct ++ { ++ Elf32_Word gt_current_g_value; /* -G value used for compilation */ ++ Elf32_Word gt_unused; /* Not used */ ++ } gt_header; /* First entry in section */ ++ struct ++ { ++ Elf32_Word gt_g_value; /* If this value were used for -G */ ++ Elf32_Word gt_bytes; /* This many bytes would be used */ ++ } gt_entry; /* Subsequent entries in section */ ++} Elf32_gptab; ++ ++/* Entry found in sections of type SHT_MIPS_REGINFO. */ ++ ++typedef struct ++{ ++ Elf32_Word ri_gprmask; /* General registers used */ ++ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ ++ Elf32_Sword ri_gp_value; /* $gp register value */ ++} Elf32_RegInfo; ++ ++/* Entries found in sections of type SHT_MIPS_OPTIONS. */ ++ ++typedef struct ++{ ++ unsigned char kind; /* Determines interpretation of the ++ variable part of descriptor. */ ++ unsigned char size; /* Size of descriptor, including header. */ ++ Elf32_Section section; /* Section header index of section affected, ++ 0 for global options. */ ++ Elf32_Word info; /* Kind-specific information. */ ++} Elf_Options; ++ ++/* Values for `kind' field in Elf_Options. */ ++ ++#define ODK_NULL 0 /* Undefined. */ ++#define ODK_REGINFO 1 /* Register usage information. */ ++#define ODK_EXCEPTIONS 2 /* Exception processing options. */ ++#define ODK_PAD 3 /* Section padding options. */ ++#define ODK_HWPATCH 4 /* Hardware workarounds performed */ ++#define ODK_FILL 5 /* record the fill value used by the linker. */ ++#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ ++#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ ++#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ ++ ++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ ++ ++#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ ++#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ ++#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ ++#define OEX_SMM 0x20000 /* Force sequential memory mode? */ ++#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ ++#define OEX_PRECISEFP OEX_FPDBUG ++#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ ++ ++#define OEX_FPU_INVAL 0x10 ++#define OEX_FPU_DIV0 0x08 ++#define OEX_FPU_OFLO 0x04 ++#define OEX_FPU_UFLO 0x02 ++#define OEX_FPU_INEX 0x01 ++ ++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ ++ ++#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ ++#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ ++#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ ++#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ ++ ++#define OPAD_PREFIX 0x1 ++#define OPAD_POSTFIX 0x2 ++#define OPAD_SYMBOL 0x4 ++ ++/* Entry found in `.options' section. */ ++ ++typedef struct ++{ ++ Elf32_Word hwp_flags1; /* Extra flags. */ ++ Elf32_Word hwp_flags2; /* Extra flags. */ ++} Elf_Options_Hw; ++ ++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ ++ ++#define OHWA0_R4KEOP_CHECKED 0x00000001 ++#define OHWA1_R4KEOP_CLEAN 0x00000002 ++ ++/* MIPS relocs. */ ++ ++#define R_MIPS_NONE 0 /* No reloc */ ++#define R_MIPS_16 1 /* Direct 16 bit */ ++#define R_MIPS_32 2 /* Direct 32 bit */ ++#define R_MIPS_REL32 3 /* PC relative 32 bit */ ++#define R_MIPS_26 4 /* Direct 26 bit shifted */ ++#define R_MIPS_HI16 5 /* High 16 bit */ ++#define R_MIPS_LO16 6 /* Low 16 bit */ ++#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ ++#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ ++#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ ++#define R_MIPS_PC16 10 /* PC relative 16 bit */ ++#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ ++#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ ++ ++#define R_MIPS_SHIFT5 16 ++#define R_MIPS_SHIFT6 17 ++#define R_MIPS_64 18 ++#define R_MIPS_GOT_DISP 19 ++#define R_MIPS_GOT_PAGE 20 ++#define R_MIPS_GOT_OFST 21 ++#define R_MIPS_GOT_HI16 22 ++#define R_MIPS_GOT_LO16 23 ++#define R_MIPS_SUB 24 ++#define R_MIPS_INSERT_A 25 ++#define R_MIPS_INSERT_B 26 ++#define R_MIPS_DELETE 27 ++#define R_MIPS_HIGHER 28 ++#define R_MIPS_HIGHEST 29 ++#define R_MIPS_CALL_HI16 30 ++#define R_MIPS_CALL_LO16 31 ++#define R_MIPS_SCN_DISP 32 ++#define R_MIPS_REL16 33 ++#define R_MIPS_ADD_IMMEDIATE 34 ++#define R_MIPS_PJUMP 35 ++#define R_MIPS_RELGOT 36 ++#define R_MIPS_JALR 37 ++#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ ++#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ ++#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ ++#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ ++#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ ++#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ ++#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ ++#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ ++#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ ++#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ ++#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ ++#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ ++#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ ++#define R_MIPS_GLOB_DAT 51 ++#define R_MIPS_COPY 126 ++#define R_MIPS_JUMP_SLOT 127 ++/* Keep this the last entry. */ ++#define R_MIPS_NUM 128 ++ ++/* Legal values for p_type field of Elf32_Phdr. */ ++ ++#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ ++#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ ++#define PT_MIPS_OPTIONS 0x70000002 ++ ++/* Special program header types. */ ++ ++#define PF_MIPS_LOCAL 0x10000000 ++ ++/* Legal values for d_tag field of Elf32_Dyn. */ ++ ++#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ ++#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ ++#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ ++#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ ++#define DT_MIPS_FLAGS 0x70000005 /* Flags */ ++#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ ++#define DT_MIPS_MSYM 0x70000007 ++#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ ++#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ ++#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ ++#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ ++#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ ++#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ ++#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ ++#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ ++#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ ++#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ ++#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ ++#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in ++ DT_MIPS_DELTA_CLASS. */ ++#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ ++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in ++ DT_MIPS_DELTA_INSTANCE. */ ++#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ ++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in ++ DT_MIPS_DELTA_RELOC. */ ++#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta ++ relocations refer to. */ ++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in ++ DT_MIPS_DELTA_SYM. */ ++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the ++ class declaration. */ ++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in ++ DT_MIPS_DELTA_CLASSSYM. */ ++#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ ++#define DT_MIPS_PIXIE_INIT 0x70000023 ++#define DT_MIPS_SYMBOL_LIB 0x70000024 ++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 ++#define DT_MIPS_LOCAL_GOTIDX 0x70000026 ++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 ++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 ++#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ ++#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ ++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b ++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ ++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve ++ function stored in GOT. */ ++#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added ++ by rld on dlopen() calls. */ ++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ ++#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ ++#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ ++/* The address of .got.plt in an executable using the new non-PIC ABI. */ ++#define DT_MIPS_PLTGOT 0x70000032 ++/* The base of the PLT in an executable using the new non-PIC ABI if that ++ PLT is writable. For a non-writable PLT, this is omitted or has a zero ++ value. */ ++#define DT_MIPS_RWPLT 0x70000034 ++#define DT_MIPS_NUM 0x35 ++ ++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ ++ ++#define RHF_NONE 0 /* No flags */ ++#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ ++#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ ++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ ++#define RHF_NO_MOVE (1 << 3) ++#define RHF_SGI_ONLY (1 << 4) ++#define RHF_GUARANTEE_INIT (1 << 5) ++#define RHF_DELTA_C_PLUS_PLUS (1 << 6) ++#define RHF_GUARANTEE_START_INIT (1 << 7) ++#define RHF_PIXIE (1 << 8) ++#define RHF_DEFAULT_DELAY_LOAD (1 << 9) ++#define RHF_REQUICKSTART (1 << 10) ++#define RHF_REQUICKSTARTED (1 << 11) ++#define RHF_CORD (1 << 12) ++#define RHF_NO_UNRES_UNDEF (1 << 13) ++#define RHF_RLD_ORDER_SAFE (1 << 14) ++ ++/* Entries found in sections of type SHT_MIPS_LIBLIST. */ ++ ++typedef struct ++{ ++ Elf32_Word l_name; /* Name (string table index) */ ++ Elf32_Word l_time_stamp; /* Timestamp */ ++ Elf32_Word l_checksum; /* Checksum */ ++ Elf32_Word l_version; /* Interface version */ ++ Elf32_Word l_flags; /* Flags */ ++} Elf32_Lib; ++ ++typedef struct ++{ ++ Elf64_Word l_name; /* Name (string table index) */ ++ Elf64_Word l_time_stamp; /* Timestamp */ ++ Elf64_Word l_checksum; /* Checksum */ ++ Elf64_Word l_version; /* Interface version */ ++ Elf64_Word l_flags; /* Flags */ ++} Elf64_Lib; ++ ++ ++/* Legal values for l_flags. */ ++ ++#define LL_NONE 0 ++#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ ++#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ ++#define LL_REQUIRE_MINOR (1 << 2) ++#define LL_EXPORTS (1 << 3) ++#define LL_DELAY_LOAD (1 << 4) ++#define LL_DELTA (1 << 5) ++ ++/* Entries found in sections of type SHT_MIPS_CONFLICT. */ ++ ++typedef Elf32_Addr Elf32_Conflict; ++ ++ ++/* HPPA specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ ++#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ ++#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ ++#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ ++#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch ++ prediction. */ ++#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ ++#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ ++ ++/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ ++ ++#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ ++#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ ++#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ ++ ++/* Additional section indeces. */ ++ ++#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared ++ symbols in ANSI C. */ ++#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ ++#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ ++#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ ++#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ ++#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ ++ ++#define STT_HP_OPAQUE (STT_LOOS + 0x1) ++#define STT_HP_STUB (STT_LOOS + 0x2) ++ ++/* HPPA relocs. */ ++ ++#define R_PARISC_NONE 0 /* No reloc. */ ++#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ ++#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ ++#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ ++#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ ++#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ ++#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ ++#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ ++#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ ++#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ ++#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ ++#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ ++#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ ++#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ ++#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ ++#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ ++#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ ++#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ ++#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ ++#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ ++#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ ++#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ ++#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ ++#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ ++#define R_PARISC_FPTR64 64 /* 64 bits function address. */ ++#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ ++#define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ ++#define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ ++#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ ++#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ ++#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ ++#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ ++#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ ++#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ ++#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ ++#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ ++#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ ++#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ ++#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ ++#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ ++#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ ++#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ ++#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LORESERVE 128 ++#define R_PARISC_COPY 128 /* Copy relocation. */ ++#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ ++#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ ++#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ ++#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ ++#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ ++#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ ++#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ ++#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ ++#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_GNU_VTENTRY 232 ++#define R_PARISC_GNU_VTINHERIT 233 ++#define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ ++#define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ ++#define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ ++#define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ ++#define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ ++#define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ ++#define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ ++#define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ ++#define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ ++#define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ ++#define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ ++#define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ ++#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L ++#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R ++#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L ++#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R ++#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 ++#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 ++#define R_PARISC_HIRESERVE 255 ++ ++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PT_HP_TLS (PT_LOOS + 0x0) ++#define PT_HP_CORE_NONE (PT_LOOS + 0x1) ++#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) ++#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) ++#define PT_HP_CORE_COMM (PT_LOOS + 0x4) ++#define PT_HP_CORE_PROC (PT_LOOS + 0x5) ++#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) ++#define PT_HP_CORE_STACK (PT_LOOS + 0x7) ++#define PT_HP_CORE_SHM (PT_LOOS + 0x8) ++#define PT_HP_CORE_MMF (PT_LOOS + 0x9) ++#define PT_HP_PARALLEL (PT_LOOS + 0x10) ++#define PT_HP_FASTBIND (PT_LOOS + 0x11) ++#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) ++#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) ++#define PT_HP_STACK (PT_LOOS + 0x14) ++ ++#define PT_PARISC_ARCHEXT 0x70000000 ++#define PT_PARISC_UNWIND 0x70000001 ++ ++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PF_PARISC_SBP 0x08000000 ++ ++#define PF_HP_PAGE_SIZE 0x00100000 ++#define PF_HP_FAR_SHARED 0x00200000 ++#define PF_HP_NEAR_SHARED 0x00400000 ++#define PF_HP_CODE 0x01000000 ++#define PF_HP_MODIFY 0x02000000 ++#define PF_HP_LAZYSWAP 0x04000000 ++#define PF_HP_SBP 0x08000000 ++ ++ ++/* Alpha specific definitions. */ ++ ++/* Legal values for e_flags field of Elf64_Ehdr. */ ++ ++#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ ++#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ ++ ++/* Legal values for sh_type field of Elf64_Shdr. */ ++ ++/* These two are primerily concerned with ECOFF debugging info. */ ++#define SHT_ALPHA_DEBUG 0x70000001 ++#define SHT_ALPHA_REGINFO 0x70000002 ++ ++/* Legal values for sh_flags field of Elf64_Shdr. */ ++ ++#define SHF_ALPHA_GPREL 0x10000000 ++ ++/* Legal values for st_other field of Elf64_Sym. */ ++#define STO_ALPHA_NOPV 0x80 /* No PV required. */ ++#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ ++ ++/* Alpha relocs. */ ++ ++#define R_ALPHA_NONE 0 /* No reloc */ ++#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ ++#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ ++#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ ++#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ ++#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ ++#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ ++#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ ++#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ ++#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ ++#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ ++#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ ++#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ ++#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ ++#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ ++#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ ++#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ ++#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ ++#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ ++#define R_ALPHA_TLS_GD_HI 28 ++#define R_ALPHA_TLSGD 29 ++#define R_ALPHA_TLS_LDM 30 ++#define R_ALPHA_DTPMOD64 31 ++#define R_ALPHA_GOTDTPREL 32 ++#define R_ALPHA_DTPREL64 33 ++#define R_ALPHA_DTPRELHI 34 ++#define R_ALPHA_DTPRELLO 35 ++#define R_ALPHA_DTPREL16 36 ++#define R_ALPHA_GOTTPREL 37 ++#define R_ALPHA_TPREL64 38 ++#define R_ALPHA_TPRELHI 39 ++#define R_ALPHA_TPRELLO 40 ++#define R_ALPHA_TPREL16 41 ++/* Keep this the last entry. */ ++#define R_ALPHA_NUM 46 ++ ++/* Magic values of the LITUSE relocation addend. */ ++#define LITUSE_ALPHA_ADDR 0 ++#define LITUSE_ALPHA_BASE 1 ++#define LITUSE_ALPHA_BYTOFF 2 ++#define LITUSE_ALPHA_JSR 3 ++#define LITUSE_ALPHA_TLS_GD 4 ++#define LITUSE_ALPHA_TLS_LDM 5 ++ ++/* Legal values for d_tag of Elf64_Dyn. */ ++#define DT_ALPHA_PLTRO (DT_LOPROC + 0) ++#define DT_ALPHA_NUM 1 ++ ++/* PowerPC specific declarations */ ++ ++/* Values for Elf32/64_Ehdr.e_flags. */ ++#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ ++ ++/* Cygnus local bits below */ ++#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ ++#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib ++ flag */ ++ ++/* PowerPC relocations defined by the ABIs */ ++#define R_PPC_NONE 0 ++#define R_PPC_ADDR32 1 /* 32bit absolute address */ ++#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ ++#define R_PPC_ADDR16 3 /* 16bit absolute address */ ++#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ ++#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ ++#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ ++#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ ++#define R_PPC_ADDR14_BRTAKEN 8 ++#define R_PPC_ADDR14_BRNTAKEN 9 ++#define R_PPC_REL24 10 /* PC relative 26 bit */ ++#define R_PPC_REL14 11 /* PC relative 16 bit */ ++#define R_PPC_REL14_BRTAKEN 12 ++#define R_PPC_REL14_BRNTAKEN 13 ++#define R_PPC_GOT16 14 ++#define R_PPC_GOT16_LO 15 ++#define R_PPC_GOT16_HI 16 ++#define R_PPC_GOT16_HA 17 ++#define R_PPC_PLTREL24 18 ++#define R_PPC_COPY 19 ++#define R_PPC_GLOB_DAT 20 ++#define R_PPC_JMP_SLOT 21 ++#define R_PPC_RELATIVE 22 ++#define R_PPC_LOCAL24PC 23 ++#define R_PPC_UADDR32 24 ++#define R_PPC_UADDR16 25 ++#define R_PPC_REL32 26 ++#define R_PPC_PLT32 27 ++#define R_PPC_PLTREL32 28 ++#define R_PPC_PLT16_LO 29 ++#define R_PPC_PLT16_HI 30 ++#define R_PPC_PLT16_HA 31 ++#define R_PPC_SDAREL16 32 ++#define R_PPC_SECTOFF 33 ++#define R_PPC_SECTOFF_LO 34 ++#define R_PPC_SECTOFF_HI 35 ++#define R_PPC_SECTOFF_HA 36 ++ ++/* PowerPC relocations defined for the TLS access ABI. */ ++#define R_PPC_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ ++#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ ++#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ ++#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ ++#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ ++#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ ++#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ ++#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ ++#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ ++ ++/* The remaining relocs are from the Embedded ELF ABI, and are not ++ in the SVR4 ELF ABI. */ ++#define R_PPC_EMB_NADDR32 101 ++#define R_PPC_EMB_NADDR16 102 ++#define R_PPC_EMB_NADDR16_LO 103 ++#define R_PPC_EMB_NADDR16_HI 104 ++#define R_PPC_EMB_NADDR16_HA 105 ++#define R_PPC_EMB_SDAI16 106 ++#define R_PPC_EMB_SDA2I16 107 ++#define R_PPC_EMB_SDA2REL 108 ++#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ ++#define R_PPC_EMB_MRKREF 110 ++#define R_PPC_EMB_RELSEC16 111 ++#define R_PPC_EMB_RELST_LO 112 ++#define R_PPC_EMB_RELST_HI 113 ++#define R_PPC_EMB_RELST_HA 114 ++#define R_PPC_EMB_BIT_FLD 115 ++#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ ++ ++/* Diab tool relocations. */ ++#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ ++#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ ++#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ ++#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ ++#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ ++#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ ++ ++/* GNU extension to support local ifunc. */ ++#define R_PPC_IRELATIVE 248 ++ ++/* GNU relocs used in PIC code sequences. */ ++#define R_PPC_REL16 249 /* half16 (sym+add-.) */ ++#define R_PPC_REL16_LO 250 /* half16 (sym+add-.)@l */ ++#define R_PPC_REL16_HI 251 /* half16 (sym+add-.)@h */ ++#define R_PPC_REL16_HA 252 /* half16 (sym+add-.)@ha */ ++ ++/* This is a phony reloc to handle any old fashioned TOC16 references ++ that may still be in object files. */ ++#define R_PPC_TOC16 255 ++ ++/* PowerPC specific values for the Dyn d_tag field. */ ++#define DT_PPC_GOT (DT_LOPROC + 0) ++#define DT_PPC_NUM 1 ++ ++/* PowerPC64 relocations defined by the ABIs */ ++#define R_PPC64_NONE R_PPC_NONE ++#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ ++#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ ++#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ ++#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ ++#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ ++#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ ++#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ ++#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN ++#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN ++#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ ++#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ ++#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN ++#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN ++#define R_PPC64_GOT16 R_PPC_GOT16 ++#define R_PPC64_GOT16_LO R_PPC_GOT16_LO ++#define R_PPC64_GOT16_HI R_PPC_GOT16_HI ++#define R_PPC64_GOT16_HA R_PPC_GOT16_HA ++ ++#define R_PPC64_COPY R_PPC_COPY ++#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT ++#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT ++#define R_PPC64_RELATIVE R_PPC_RELATIVE ++ ++#define R_PPC64_UADDR32 R_PPC_UADDR32 ++#define R_PPC64_UADDR16 R_PPC_UADDR16 ++#define R_PPC64_REL32 R_PPC_REL32 ++#define R_PPC64_PLT32 R_PPC_PLT32 ++#define R_PPC64_PLTREL32 R_PPC_PLTREL32 ++#define R_PPC64_PLT16_LO R_PPC_PLT16_LO ++#define R_PPC64_PLT16_HI R_PPC_PLT16_HI ++#define R_PPC64_PLT16_HA R_PPC_PLT16_HA ++ ++#define R_PPC64_SECTOFF R_PPC_SECTOFF ++#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO ++#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ++#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA ++#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ ++#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ ++#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ ++#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ ++#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ ++#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ ++#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ ++#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ ++#define R_PPC64_PLT64 45 /* doubleword64 L + A */ ++#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ ++#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ ++#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ ++#define R_PPC64_TOC 51 /* doubleword64 .TOC */ ++#define R_PPC64_PLTGOT16 52 /* half16* M + A */ ++#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ ++#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ ++#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ ++ ++#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ ++#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ ++#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ ++#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ ++#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ ++#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ ++#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ ++#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ ++#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ ++#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ ++#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ ++ ++/* PowerPC64 relocations defined for the TLS access ABI. */ ++#define R_PPC64_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ ++#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ ++#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ ++#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ ++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ ++#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ ++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ ++#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ ++#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ ++#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ ++#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ ++#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ ++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ ++#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ ++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ ++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ ++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ ++ ++/* GNU extension to support local ifunc. */ ++#define R_PPC64_JMP_IREL 247 ++#define R_PPC64_IRELATIVE 248 ++#define R_PPC64_REL16 249 /* half16 (sym+add-.) */ ++#define R_PPC64_REL16_LO 250 /* half16 (sym+add-.)@l */ ++#define R_PPC64_REL16_HI 251 /* half16 (sym+add-.)@h */ ++#define R_PPC64_REL16_HA 252 /* half16 (sym+add-.)@ha */ ++ ++/* PowerPC64 specific values for the Dyn d_tag field. */ ++#define DT_PPC64_GLINK (DT_LOPROC + 0) ++#define DT_PPC64_OPD (DT_LOPROC + 1) ++#define DT_PPC64_OPDSZ (DT_LOPROC + 2) ++#define DT_PPC64_NUM 3 ++ ++ ++/* ARM specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_ARM_RELEXEC 0x01 ++#define EF_ARM_HASENTRY 0x02 ++#define EF_ARM_INTERWORK 0x04 ++#define EF_ARM_APCS_26 0x08 ++#define EF_ARM_APCS_FLOAT 0x10 ++#define EF_ARM_PIC 0x20 ++#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ ++#define EF_ARM_NEW_ABI 0x80 ++#define EF_ARM_OLD_ABI 0x100 ++#define EF_ARM_SOFT_FLOAT 0x200 ++#define EF_ARM_VFP_FLOAT 0x400 ++#define EF_ARM_MAVERICK_FLOAT 0x800 ++ ++ ++/* Other constants defined in the ARM ELF spec. version B-01. */ ++/* NB. These conflict with values defined above. */ ++#define EF_ARM_SYMSARESORTED 0x04 ++#define EF_ARM_DYNSYMSUSESEGIDX 0x08 ++#define EF_ARM_MAPSYMSFIRST 0x10 ++#define EF_ARM_EABIMASK 0XFF000000 ++ ++/* Constants defined in AAELF. */ ++#define EF_ARM_BE8 0x00800000 ++#define EF_ARM_LE8 0x00400000 ++ ++#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) ++#define EF_ARM_EABI_UNKNOWN 0x00000000 ++#define EF_ARM_EABI_VER1 0x01000000 ++#define EF_ARM_EABI_VER2 0x02000000 ++#define EF_ARM_EABI_VER3 0x03000000 ++#define EF_ARM_EABI_VER4 0x04000000 ++#define EF_ARM_EABI_VER5 0x05000000 ++ ++/* Additional symbol types for Thumb. */ ++#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ ++#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ ++ ++/* ARM-specific values for sh_flags */ ++#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ ++#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined ++ in the input to a link step. */ ++ ++/* ARM-specific program header flags */ ++#define PF_ARM_SB 0x10000000 /* Segment contains the location ++ addressed by the static base. */ ++#define PF_ARM_PI 0x20000000 /* Position-independent segment. */ ++#define PF_ARM_ABS 0x40000000 /* Absolute segment. */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */ ++#define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */ ++#define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */ ++ ++ ++/* ARM relocs. */ ++ ++#define R_ARM_NONE 0 /* No reloc */ ++#define R_ARM_PC24 1 /* PC relative 26 bit branch */ ++#define R_ARM_ABS32 2 /* Direct 32 bit */ ++#define R_ARM_REL32 3 /* PC relative 32 bit */ ++#define R_ARM_PC13 4 ++#define R_ARM_ABS16 5 /* Direct 16 bit */ ++#define R_ARM_ABS12 6 /* Direct 12 bit */ ++#define R_ARM_THM_ABS5 7 ++#define R_ARM_ABS8 8 /* Direct 8 bit */ ++#define R_ARM_SBREL32 9 ++#define R_ARM_THM_PC22 10 ++#define R_ARM_THM_PC8 11 ++#define R_ARM_AMP_VCALL9 12 ++#define R_ARM_SWI24 13 /* Obsolete static relocation. */ ++#define R_ARM_TLS_DESC 13 /* Dynamic relocation. */ ++#define R_ARM_THM_SWI8 14 ++#define R_ARM_XPC25 15 ++#define R_ARM_THM_XPC22 16 ++#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ ++#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ ++#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ ++#define R_ARM_COPY 20 /* Copy symbol at runtime */ ++#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ ++#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ ++#define R_ARM_RELATIVE 23 /* Adjust by program base */ ++#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ ++#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ ++#define R_ARM_GOT32 26 /* 32 bit GOT entry */ ++#define R_ARM_PLT32 27 /* 32 bit PLT address */ ++#define R_ARM_ALU_PCREL_7_0 32 ++#define R_ARM_ALU_PCREL_15_8 33 ++#define R_ARM_ALU_PCREL_23_15 34 ++#define R_ARM_LDR_SBREL_11_0 35 ++#define R_ARM_ALU_SBREL_19_12 36 ++#define R_ARM_ALU_SBREL_27_20 37 ++#define R_ARM_TLS_GOTDESC 90 ++#define R_ARM_TLS_CALL 91 ++#define R_ARM_TLS_DESCSEQ 92 ++#define R_ARM_THM_TLS_CALL 93 ++#define R_ARM_GNU_VTENTRY 100 ++#define R_ARM_GNU_VTINHERIT 101 ++#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ ++#define R_ARM_THM_PC9 103 /* thumb conditional branch */ ++#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic ++ thread local data */ ++#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic ++ thread local data */ ++#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS ++ block */ ++#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of ++ static TLS block offset */ ++#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static ++ TLS block */ ++#define R_ARM_THM_TLS_DESCSEQ 129 ++#define R_ARM_IRELATIVE 160 ++#define R_ARM_RXPC25 249 ++#define R_ARM_RSBREL32 250 ++#define R_ARM_THM_RPC22 251 ++#define R_ARM_RREL32 252 ++#define R_ARM_RABS22 253 ++#define R_ARM_RPC24 254 ++#define R_ARM_RBASE 255 ++/* Keep this the last entry. */ ++#define R_ARM_NUM 256 ++ ++/* IA-64 specific declarations. */ ++ ++/* Processor specific flags for the Ehdr e_flags field. */ ++#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ ++#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ ++#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ ++#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ ++#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) ++#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) ++#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) ++ ++/* Processor specific flags for the Phdr p_flags field. */ ++#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ ++#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ ++ ++/* Processor specific flags for the Shdr sh_flags field. */ ++#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ ++#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Dyn d_tag field. */ ++#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) ++#define DT_IA_64_NUM 1 ++ ++/* IA-64 relocations. */ ++#define R_IA64_NONE 0x00 /* none */ ++#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ ++#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ ++#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ ++#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ ++#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ ++#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ ++#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ ++#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ ++#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ ++#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ ++#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ ++#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ ++#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ ++#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ ++#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ ++#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ ++#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ ++#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ ++#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ ++#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ ++#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ ++#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ ++#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ ++#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ ++#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ ++#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ ++#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ ++#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ ++#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ ++#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ ++#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ ++#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ ++#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ ++#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ ++#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ ++#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ ++#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ ++#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ ++#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ ++#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ ++#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ ++#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ ++#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ ++#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ ++#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ ++#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ ++#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ ++#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ ++#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ ++#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ ++#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ ++#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ ++#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ ++#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ ++#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ ++#define R_IA64_COPY 0x84 /* copy relocation */ ++#define R_IA64_SUB 0x85 /* Addend and symbol difference */ ++#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ ++#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ ++#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ ++#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ ++#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ ++#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ ++#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ ++#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ ++#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ ++#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ ++#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ ++#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ ++#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ ++#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ ++#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ ++#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ ++ ++/* SH specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_SH_MACH_MASK 0x1f ++#define EF_SH_UNKNOWN 0x0 ++#define EF_SH1 0x1 ++#define EF_SH2 0x2 ++#define EF_SH3 0x3 ++#define EF_SH_DSP 0x4 ++#define EF_SH3_DSP 0x5 ++#define EF_SH4AL_DSP 0x6 ++#define EF_SH3E 0x8 ++#define EF_SH4 0x9 ++#define EF_SH2E 0xb ++#define EF_SH4A 0xc ++#define EF_SH2A 0xd ++#define EF_SH4_NOFPU 0x10 ++#define EF_SH4A_NOFPU 0x11 ++#define EF_SH4_NOMMU_NOFPU 0x12 ++#define EF_SH2A_NOFPU 0x13 ++#define EF_SH3_NOMMU 0x14 ++#define EF_SH2A_SH4_NOFPU 0x15 ++#define EF_SH2A_SH3_NOFPU 0x16 ++#define EF_SH2A_SH4 0x17 ++#define EF_SH2A_SH3E 0x18 ++ ++/* SH relocs. */ ++#define R_SH_NONE 0 ++#define R_SH_DIR32 1 ++#define R_SH_REL32 2 ++#define R_SH_DIR8WPN 3 ++#define R_SH_IND12W 4 ++#define R_SH_DIR8WPL 5 ++#define R_SH_DIR8WPZ 6 ++#define R_SH_DIR8BP 7 ++#define R_SH_DIR8W 8 ++#define R_SH_DIR8L 9 ++#define R_SH_SWITCH16 25 ++#define R_SH_SWITCH32 26 ++#define R_SH_USES 27 ++#define R_SH_COUNT 28 ++#define R_SH_ALIGN 29 ++#define R_SH_CODE 30 ++#define R_SH_DATA 31 ++#define R_SH_LABEL 32 ++#define R_SH_SWITCH8 33 ++#define R_SH_GNU_VTINHERIT 34 ++#define R_SH_GNU_VTENTRY 35 ++#define R_SH_TLS_GD_32 144 ++#define R_SH_TLS_LD_32 145 ++#define R_SH_TLS_LDO_32 146 ++#define R_SH_TLS_IE_32 147 ++#define R_SH_TLS_LE_32 148 ++#define R_SH_TLS_DTPMOD32 149 ++#define R_SH_TLS_DTPOFF32 150 ++#define R_SH_TLS_TPOFF32 151 ++#define R_SH_GOT32 160 ++#define R_SH_PLT32 161 ++#define R_SH_COPY 162 ++#define R_SH_GLOB_DAT 163 ++#define R_SH_JMP_SLOT 164 ++#define R_SH_RELATIVE 165 ++#define R_SH_GOTOFF 166 ++#define R_SH_GOTPC 167 ++/* Keep this the last entry. */ ++#define R_SH_NUM 256 ++ ++/* S/390 specific definitions. */ ++ ++/* Valid values for the e_flags field. */ ++ ++#define EF_S390_HIGH_GPRS 0x00000001 /* High GPRs kernel facility needed. */ ++ ++/* Additional s390 relocs */ ++ ++#define R_390_NONE 0 /* No reloc. */ ++#define R_390_8 1 /* Direct 8 bit. */ ++#define R_390_12 2 /* Direct 12 bit. */ ++#define R_390_16 3 /* Direct 16 bit. */ ++#define R_390_32 4 /* Direct 32 bit. */ ++#define R_390_PC32 5 /* PC relative 32 bit. */ ++#define R_390_GOT12 6 /* 12 bit GOT offset. */ ++#define R_390_GOT32 7 /* 32 bit GOT offset. */ ++#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ ++#define R_390_COPY 9 /* Copy symbol at runtime. */ ++#define R_390_GLOB_DAT 10 /* Create GOT entry. */ ++#define R_390_JMP_SLOT 11 /* Create PLT entry. */ ++#define R_390_RELATIVE 12 /* Adjust by program base. */ ++#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ ++#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ ++#define R_390_GOT16 15 /* 16 bit GOT offset. */ ++#define R_390_PC16 16 /* PC relative 16 bit. */ ++#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ ++#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ ++#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ ++#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ ++#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ ++#define R_390_64 22 /* Direct 64 bit. */ ++#define R_390_PC64 23 /* PC relative 64 bit. */ ++#define R_390_GOT64 24 /* 64 bit GOT offset. */ ++#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ ++#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ ++#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ ++#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ ++#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ ++#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ ++#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ ++#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ ++#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ ++#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ ++#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ ++#define R_390_TLS_GDCALL 38 /* Tag for function call in general ++ dynamic TLS code. */ ++#define R_390_TLS_LDCALL 39 /* Tag for function call in local ++ dynamic TLS code. */ ++#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ ++#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ ++#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS ++ block. */ ++#define R_390_20 57 /* Direct 20 bit. */ ++#define R_390_GOT20 58 /* 20 bit GOT offset. */ ++#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ ++#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_IRELATIVE 61 /* STT_GNU_IFUNC relocation. */ ++/* Keep this the last entry. */ ++#define R_390_NUM 62 ++ ++ ++/* CRIS relocations. */ ++#define R_CRIS_NONE 0 ++#define R_CRIS_8 1 ++#define R_CRIS_16 2 ++#define R_CRIS_32 3 ++#define R_CRIS_8_PCREL 4 ++#define R_CRIS_16_PCREL 5 ++#define R_CRIS_32_PCREL 6 ++#define R_CRIS_GNU_VTINHERIT 7 ++#define R_CRIS_GNU_VTENTRY 8 ++#define R_CRIS_COPY 9 ++#define R_CRIS_GLOB_DAT 10 ++#define R_CRIS_JUMP_SLOT 11 ++#define R_CRIS_RELATIVE 12 ++#define R_CRIS_16_GOT 13 ++#define R_CRIS_32_GOT 14 ++#define R_CRIS_16_GOTPLT 15 ++#define R_CRIS_32_GOTPLT 16 ++#define R_CRIS_32_GOTREL 17 ++#define R_CRIS_32_PLT_GOTREL 18 ++#define R_CRIS_32_PLT_PCREL 19 ++ ++#define R_CRIS_NUM 20 ++ ++ ++/* AMD x86-64 relocations. */ ++#define R_X86_64_NONE 0 /* No reloc */ ++#define R_X86_64_64 1 /* Direct 64 bit */ ++#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ ++#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ ++#define R_X86_64_PLT32 4 /* 32 bit PLT address */ ++#define R_X86_64_COPY 5 /* Copy symbol at runtime */ ++#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ ++#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ ++#define R_X86_64_RELATIVE 8 /* Adjust by program base */ ++#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative ++ offset to GOT */ ++#define R_X86_64_32 10 /* Direct 32 bit zero extended */ ++#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ ++#define R_X86_64_16 12 /* Direct 16 bit zero extended */ ++#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ ++#define R_X86_64_8 14 /* Direct 8 bit sign extended */ ++#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ ++#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ ++#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ ++#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ ++#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset ++ to two GOT entries for GD symbol */ ++#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset ++ to two GOT entries for LD symbol */ ++#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ ++#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset ++ to GOT entry for IE symbol */ ++#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ ++#define R_X86_64_PC64 24 /* PC relative 64 bit */ ++#define R_X86_64_GOTOFF64 25 /* 64 bit offset to GOT */ ++#define R_X86_64_GOTPC32 26 /* 32 bit signed pc relative ++ offset to GOT */ ++#define R_X86_64_GOT64 27 /* 64-bit GOT entry offset */ ++#define R_X86_64_GOTPCREL64 28 /* 64-bit PC relative offset ++ to GOT entry */ ++#define R_X86_64_GOTPC64 29 /* 64-bit PC relative offset to GOT */ ++#define R_X86_64_GOTPLT64 30 /* like GOT64, says PLT entry needed */ ++#define R_X86_64_PLTOFF64 31 /* 64-bit GOT relative offset ++ to PLT entry */ ++#define R_X86_64_SIZE32 32 /* Size of symbol plus 32-bit addend */ ++#define R_X86_64_SIZE64 33 /* Size of symbol plus 64-bit addend */ ++#define R_X86_64_GOTPC32_TLSDESC 34 /* GOT offset for TLS descriptor. */ ++#define R_X86_64_TLSDESC_CALL 35 /* Marker for call through TLS ++ descriptor. */ ++#define R_X86_64_TLSDESC 36 /* TLS descriptor. */ ++#define R_X86_64_IRELATIVE 37 /* Adjust indirectly by program base */ ++#define R_X86_64_RELATIVE64 38 /* 64-bit adjust by program base */ ++ ++#define R_X86_64_NUM 39 ++ ++ ++/* AM33 relocations. */ ++#define R_MN10300_NONE 0 /* No reloc. */ ++#define R_MN10300_32 1 /* Direct 32 bit. */ ++#define R_MN10300_16 2 /* Direct 16 bit. */ ++#define R_MN10300_8 3 /* Direct 8 bit. */ ++#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ ++#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ ++#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ ++#define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ ++#define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ ++#define R_MN10300_24 9 /* Direct 24 bit. */ ++#define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ ++#define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ ++#define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ ++#define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ ++#define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ ++#define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ ++#define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ ++#define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ ++#define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ ++#define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ ++#define R_MN10300_COPY 20 /* Copy symbol at runtime. */ ++#define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ ++#define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ ++#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ ++ ++#define R_MN10300_NUM 24 ++ ++ ++/* M32R relocs. */ ++#define R_M32R_NONE 0 /* No reloc. */ ++#define R_M32R_16 1 /* Direct 16 bit. */ ++#define R_M32R_32 2 /* Direct 32 bit. */ ++#define R_M32R_24 3 /* Direct 24 bit. */ ++#define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ ++#define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ ++#define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ ++#define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ ++#define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ ++#define R_M32R_LO16 9 /* Low 16 bit. */ ++#define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ ++#define R_M32R_GNU_VTINHERIT 11 ++#define R_M32R_GNU_VTENTRY 12 ++/* M32R relocs use SHT_RELA. */ ++#define R_M32R_16_RELA 33 /* Direct 16 bit. */ ++#define R_M32R_32_RELA 34 /* Direct 32 bit. */ ++#define R_M32R_24_RELA 35 /* Direct 24 bit. */ ++#define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ ++#define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ ++#define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ ++#define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ ++#define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ ++#define R_M32R_LO16_RELA 41 /* Low 16 bit */ ++#define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ ++#define R_M32R_RELA_GNU_VTINHERIT 43 ++#define R_M32R_RELA_GNU_VTENTRY 44 ++#define R_M32R_REL32 45 /* PC relative 32 bit. */ ++ ++#define R_M32R_GOT24 48 /* 24 bit GOT entry */ ++#define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ ++#define R_M32R_COPY 50 /* Copy symbol at runtime */ ++#define R_M32R_GLOB_DAT 51 /* Create GOT entry */ ++#define R_M32R_JMP_SLOT 52 /* Create PLT entry */ ++#define R_M32R_RELATIVE 53 /* Adjust by program base */ ++#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ ++#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ ++#define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned ++ low */ ++#define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed ++ low */ ++#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ ++#define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to ++ GOT with unsigned low */ ++#define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to ++ GOT with signed low */ ++#define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to ++ GOT */ ++#define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT ++ with unsigned low */ ++#define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT ++ with signed low */ ++#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ ++#define R_M32R_NUM 256 /* Keep this the last entry. */ ++ ++ ++/* TILEPro relocations. */ ++#define R_TILEPRO_NONE 0 /* No reloc */ ++#define R_TILEPRO_32 1 /* Direct 32 bit */ ++#define R_TILEPRO_16 2 /* Direct 16 bit */ ++#define R_TILEPRO_8 3 /* Direct 8 bit */ ++#define R_TILEPRO_32_PCREL 4 /* PC relative 32 bit */ ++#define R_TILEPRO_16_PCREL 5 /* PC relative 16 bit */ ++#define R_TILEPRO_8_PCREL 6 /* PC relative 8 bit */ ++#define R_TILEPRO_LO16 7 /* Low 16 bit */ ++#define R_TILEPRO_HI16 8 /* High 16 bit */ ++#define R_TILEPRO_HA16 9 /* High 16 bit, adjusted */ ++#define R_TILEPRO_COPY 10 /* Copy relocation */ ++#define R_TILEPRO_GLOB_DAT 11 /* Create GOT entry */ ++#define R_TILEPRO_JMP_SLOT 12 /* Create PLT entry */ ++#define R_TILEPRO_RELATIVE 13 /* Adjust by program base */ ++#define R_TILEPRO_BROFF_X1 14 /* X1 pipe branch offset */ ++#define R_TILEPRO_JOFFLONG_X1 15 /* X1 pipe jump offset */ ++#define R_TILEPRO_JOFFLONG_X1_PLT 16 /* X1 pipe jump offset to PLT */ ++#define R_TILEPRO_IMM8_X0 17 /* X0 pipe 8-bit */ ++#define R_TILEPRO_IMM8_Y0 18 /* Y0 pipe 8-bit */ ++#define R_TILEPRO_IMM8_X1 19 /* X1 pipe 8-bit */ ++#define R_TILEPRO_IMM8_Y1 20 /* Y1 pipe 8-bit */ ++#define R_TILEPRO_MT_IMM15_X1 21 /* X1 pipe mtspr */ ++#define R_TILEPRO_MF_IMM15_X1 22 /* X1 pipe mfspr */ ++#define R_TILEPRO_IMM16_X0 23 /* X0 pipe 16-bit */ ++#define R_TILEPRO_IMM16_X1 24 /* X1 pipe 16-bit */ ++#define R_TILEPRO_IMM16_X0_LO 25 /* X0 pipe low 16-bit */ ++#define R_TILEPRO_IMM16_X1_LO 26 /* X1 pipe low 16-bit */ ++#define R_TILEPRO_IMM16_X0_HI 27 /* X0 pipe high 16-bit */ ++#define R_TILEPRO_IMM16_X1_HI 28 /* X1 pipe high 16-bit */ ++#define R_TILEPRO_IMM16_X0_HA 29 /* X0 pipe high 16-bit, adjusted */ ++#define R_TILEPRO_IMM16_X1_HA 30 /* X1 pipe high 16-bit, adjusted */ ++#define R_TILEPRO_IMM16_X0_PCREL 31 /* X0 pipe PC relative 16 bit */ ++#define R_TILEPRO_IMM16_X1_PCREL 32 /* X1 pipe PC relative 16 bit */ ++#define R_TILEPRO_IMM16_X0_LO_PCREL 33 /* X0 pipe PC relative low 16 bit */ ++#define R_TILEPRO_IMM16_X1_LO_PCREL 34 /* X1 pipe PC relative low 16 bit */ ++#define R_TILEPRO_IMM16_X0_HI_PCREL 35 /* X0 pipe PC relative high 16 bit */ ++#define R_TILEPRO_IMM16_X1_HI_PCREL 36 /* X1 pipe PC relative high 16 bit */ ++#define R_TILEPRO_IMM16_X0_HA_PCREL 37 /* X0 pipe PC relative ha() 16 bit */ ++#define R_TILEPRO_IMM16_X1_HA_PCREL 38 /* X1 pipe PC relative ha() 16 bit */ ++#define R_TILEPRO_IMM16_X0_GOT 39 /* X0 pipe 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT 40 /* X1 pipe 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_LO 41 /* X0 pipe low 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_LO 42 /* X1 pipe low 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_HI 43 /* X0 pipe high 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_HI 44 /* X1 pipe high 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_HA 45 /* X0 pipe ha() 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_HA 46 /* X1 pipe ha() 16-bit GOT offset */ ++#define R_TILEPRO_MMSTART_X0 47 /* X0 pipe mm "start" */ ++#define R_TILEPRO_MMEND_X0 48 /* X0 pipe mm "end" */ ++#define R_TILEPRO_MMSTART_X1 49 /* X1 pipe mm "start" */ ++#define R_TILEPRO_MMEND_X1 50 /* X1 pipe mm "end" */ ++#define R_TILEPRO_SHAMT_X0 51 /* X0 pipe shift amount */ ++#define R_TILEPRO_SHAMT_X1 52 /* X1 pipe shift amount */ ++#define R_TILEPRO_SHAMT_Y0 53 /* Y0 pipe shift amount */ ++#define R_TILEPRO_SHAMT_Y1 54 /* Y1 pipe shift amount */ ++#define R_TILEPRO_DEST_IMM8_X1 55 /* X1 pipe destination 8-bit */ ++/* Relocs 56-59 are currently not defined. */ ++#define R_TILEPRO_TLS_GD_CALL 60 /* "jal" for TLS GD */ ++#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 /* X0 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 /* X1 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 /* Y0 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 /* Y1 pipe "addi" for TLS GD */ ++#define R_TILEPRO_TLS_IE_LOAD 65 /* "lw_tls" for TLS IE */ ++#define R_TILEPRO_IMM16_X0_TLS_GD 66 /* X0 pipe 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD 67 /* X1 pipe 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68 /* X0 pipe low 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69 /* X1 pipe low 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70 /* X0 pipe high 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71 /* X1 pipe high 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72 /* X0 pipe ha() 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73 /* X1 pipe ha() 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE 74 /* X0 pipe 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE 75 /* X1 pipe 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76 /* X0 pipe low 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77 /* X1 pipe low 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78 /* X0 pipe high 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79 /* X1 pipe high 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80 /* X0 pipe ha() 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81 /* X1 pipe ha() 16-bit TLS IE offset */ ++#define R_TILEPRO_TLS_DTPMOD32 82 /* ID of module containing symbol */ ++#define R_TILEPRO_TLS_DTPOFF32 83 /* Offset in TLS block */ ++#define R_TILEPRO_TLS_TPOFF32 84 /* Offset in static TLS block */ ++#define R_TILEPRO_IMM16_X0_TLS_LE 85 /* X0 pipe 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE 86 /* X1 pipe 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87 /* X0 pipe low 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88 /* X1 pipe low 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89 /* X0 pipe high 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90 /* X1 pipe high 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91 /* X0 pipe ha() 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92 /* X1 pipe ha() 16-bit TLS LE offset */ ++ ++#define R_TILEPRO_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ ++#define R_TILEPRO_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ ++ ++#define R_TILEPRO_NUM 130 ++ ++ ++/* TILE-Gx relocations. */ ++#define R_TILEGX_NONE 0 /* No reloc */ ++#define R_TILEGX_64 1 /* Direct 64 bit */ ++#define R_TILEGX_32 2 /* Direct 32 bit */ ++#define R_TILEGX_16 3 /* Direct 16 bit */ ++#define R_TILEGX_8 4 /* Direct 8 bit */ ++#define R_TILEGX_64_PCREL 5 /* PC relative 64 bit */ ++#define R_TILEGX_32_PCREL 6 /* PC relative 32 bit */ ++#define R_TILEGX_16_PCREL 7 /* PC relative 16 bit */ ++#define R_TILEGX_8_PCREL 8 /* PC relative 8 bit */ ++#define R_TILEGX_HW0 9 /* hword 0 16-bit */ ++#define R_TILEGX_HW1 10 /* hword 1 16-bit */ ++#define R_TILEGX_HW2 11 /* hword 2 16-bit */ ++#define R_TILEGX_HW3 12 /* hword 3 16-bit */ ++#define R_TILEGX_HW0_LAST 13 /* last hword 0 16-bit */ ++#define R_TILEGX_HW1_LAST 14 /* last hword 1 16-bit */ ++#define R_TILEGX_HW2_LAST 15 /* last hword 2 16-bit */ ++#define R_TILEGX_COPY 16 /* Copy relocation */ ++#define R_TILEGX_GLOB_DAT 17 /* Create GOT entry */ ++#define R_TILEGX_JMP_SLOT 18 /* Create PLT entry */ ++#define R_TILEGX_RELATIVE 19 /* Adjust by program base */ ++#define R_TILEGX_BROFF_X1 20 /* X1 pipe branch offset */ ++#define R_TILEGX_JUMPOFF_X1 21 /* X1 pipe jump offset */ ++#define R_TILEGX_JUMPOFF_X1_PLT 22 /* X1 pipe jump offset to PLT */ ++#define R_TILEGX_IMM8_X0 23 /* X0 pipe 8-bit */ ++#define R_TILEGX_IMM8_Y0 24 /* Y0 pipe 8-bit */ ++#define R_TILEGX_IMM8_X1 25 /* X1 pipe 8-bit */ ++#define R_TILEGX_IMM8_Y1 26 /* Y1 pipe 8-bit */ ++#define R_TILEGX_DEST_IMM8_X1 27 /* X1 pipe destination 8-bit */ ++#define R_TILEGX_MT_IMM14_X1 28 /* X1 pipe mtspr */ ++#define R_TILEGX_MF_IMM14_X1 29 /* X1 pipe mfspr */ ++#define R_TILEGX_MMSTART_X0 30 /* X0 pipe mm "start" */ ++#define R_TILEGX_MMEND_X0 31 /* X0 pipe mm "end" */ ++#define R_TILEGX_SHAMT_X0 32 /* X0 pipe shift amount */ ++#define R_TILEGX_SHAMT_X1 33 /* X1 pipe shift amount */ ++#define R_TILEGX_SHAMT_Y0 34 /* Y0 pipe shift amount */ ++#define R_TILEGX_SHAMT_Y1 35 /* Y1 pipe shift amount */ ++#define R_TILEGX_IMM16_X0_HW0 36 /* X0 pipe hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0 37 /* X1 pipe hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1 38 /* X0 pipe hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1 39 /* X1 pipe hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2 40 /* X0 pipe hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2 41 /* X1 pipe hword 2 */ ++#define R_TILEGX_IMM16_X0_HW3 42 /* X0 pipe hword 3 */ ++#define R_TILEGX_IMM16_X1_HW3 43 /* X1 pipe hword 3 */ ++#define R_TILEGX_IMM16_X0_HW0_LAST 44 /* X0 pipe last hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_LAST 45 /* X1 pipe last hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_LAST 46 /* X0 pipe last hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_LAST 47 /* X1 pipe last hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_LAST 48 /* X0 pipe last hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_LAST 49 /* X1 pipe last hword 2 */ ++#define R_TILEGX_IMM16_X0_HW0_PCREL 50 /* X0 pipe PC relative hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_PCREL 51 /* X1 pipe PC relative hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_PCREL 52 /* X0 pipe PC relative hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_PCREL 53 /* X1 pipe PC relative hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_PCREL 54 /* X0 pipe PC relative hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_PCREL 55 /* X1 pipe PC relative hword 2 */ ++#define R_TILEGX_IMM16_X0_HW3_PCREL 56 /* X0 pipe PC relative hword 3 */ ++#define R_TILEGX_IMM16_X1_HW3_PCREL 57 /* X1 pipe PC relative hword 3 */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */ ++#define R_TILEGX_IMM16_X0_HW0_GOT 64 /* X0 pipe hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW0_GOT 65 /* X1 pipe hword 0 GOT offset */ ++/* Relocs 66-71 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */ ++/* Relocs 76-77 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78 /* X0 pipe hword 0 TLS GD offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79 /* X1 pipe hword 0 TLS GD offset */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80 /* X0 pipe hword 0 TLS LE offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81 /* X1 pipe hword 0 TLS LE offset */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */ ++/* Relocs 90-91 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92 /* X0 pipe hword 0 TLS IE offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93 /* X1 pipe hword 0 TLS IE offset */ ++/* Relocs 94-99 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */ ++/* Relocs 104-105 are currently not defined. */ ++#define R_TILEGX_TLS_DTPMOD64 106 /* 64-bit ID of symbol's module */ ++#define R_TILEGX_TLS_DTPOFF64 107 /* 64-bit offset in TLS block */ ++#define R_TILEGX_TLS_TPOFF64 108 /* 64-bit offset in static TLS block */ ++#define R_TILEGX_TLS_DTPMOD32 109 /* 32-bit ID of symbol's module */ ++#define R_TILEGX_TLS_DTPOFF32 110 /* 32-bit offset in TLS block */ ++#define R_TILEGX_TLS_TPOFF32 111 /* 32-bit offset in static TLS block */ ++#define R_TILEGX_TLS_GD_CALL 112 /* "jal" for TLS GD */ ++#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113 /* X0 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114 /* X1 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 /* Y0 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 /* Y1 pipe "addi" for TLS GD */ ++#define R_TILEGX_TLS_IE_LOAD 117 /* "ld_tls" for TLS IE */ ++#define R_TILEGX_IMM8_X0_TLS_ADD 118 /* X0 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_X1_TLS_ADD 119 /* X1 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_Y0_TLS_ADD 120 /* Y0 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_Y1_TLS_ADD 121 /* Y1 pipe "addi" for TLS GD/IE */ ++ ++#define R_TILEGX_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ ++#define R_TILEGX_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ ++ ++#define R_TILEGX_NUM 130 ++ ++#endif /* elf.h */ diff --git a/target/linux/generic/patches-4.1/212-byteshift_portability.patch b/target/linux/generic/patches-4.1/212-byteshift_portability.patch new file mode 100644 index 0000000..0f23ba9 --- /dev/null +++ b/target/linux/generic/patches-4.1/212-byteshift_portability.patch @@ -0,0 +1,51 @@ +--- a/tools/include/tools/be_byteshift.h ++++ b/tools/include/tools/be_byteshift.h +@@ -1,6 +1,10 @@ + #ifndef _TOOLS_BE_BYTESHIFT_H + #define _TOOLS_BE_BYTESHIFT_H + ++#ifndef __linux__ ++#include "linux_types.h" ++#endif ++ + #include + + static inline uint16_t __get_unaligned_be16(const uint8_t *p) +--- a/tools/include/tools/le_byteshift.h ++++ b/tools/include/tools/le_byteshift.h +@@ -1,6 +1,10 @@ + #ifndef _TOOLS_LE_BYTESHIFT_H + #define _TOOLS_LE_BYTESHIFT_H + ++#ifndef __linux__ ++#include "linux_types.h" ++#endif ++ + #include + + static inline uint16_t __get_unaligned_le16(const uint8_t *p) +--- /dev/null ++++ b/tools/include/tools/linux_types.h +@@ -0,0 +1,22 @@ ++#ifndef __LINUX_TYPES_H ++#define __LINUX_TYPES_H ++ ++#include ++ ++typedef uint8_t __u8; ++typedef uint8_t __be8; ++typedef uint8_t __le8; ++ ++typedef uint16_t __u16; ++typedef uint16_t __be16; ++typedef uint16_t __le16; ++ ++typedef uint32_t __u32; ++typedef uint32_t __be32; ++typedef uint32_t __le32; ++ ++typedef uint64_t __u64; ++typedef uint64_t __be64; ++typedef uint64_t __le64; ++ ++#endif diff --git a/target/linux/generic/patches-4.1/214-spidev_h_portability.patch b/target/linux/generic/patches-4.1/214-spidev_h_portability.patch new file mode 100644 index 0000000..dbee090 --- /dev/null +++ b/target/linux/generic/patches-4.1/214-spidev_h_portability.patch @@ -0,0 +1,11 @@ +--- a/include/uapi/linux/spi/spidev.h ++++ b/include/uapi/linux/spi/spidev.h +@@ -111,7 +111,7 @@ struct spi_ioc_transfer { + + /* not all platforms use or _IOC_TYPECHECK() ... */ + #define SPI_MSGSIZE(N) \ +- ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ ++ ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << 13)) \ + ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) + #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + diff --git a/target/linux/generic/patches-4.1/220-gc_sections.patch b/target/linux/generic/patches-4.1/220-gc_sections.patch new file mode 100644 index 0000000..98e1193 --- /dev/null +++ b/target/linux/generic/patches-4.1/220-gc_sections.patch @@ -0,0 +1,536 @@ +From: Felix Fietkau + +use -ffunction-sections, -fdata-sections and --gc-sections + +In combination with kernel symbol export stripping this significantly reduces +the kernel image size. Used on both ARM and MIPS architectures. + +Signed-off-by: Felix Fietkau +Signed-off-by: Jonas Gorski +Signed-off-by: Gabor Juhos +--- + +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -89,10 +89,14 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + # + cflags-y += -G 0 -mno-abicalls -fno-pic -pipe + cflags-y += -msoft-float +-LDFLAGS_vmlinux += -G 0 -static -n -nostdlib ++LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections + KBUILD_AFLAGS_MODULE += -mlong-calls + KBUILD_CFLAGS_MODULE += -mlong-calls + ++ifndef CONFIG_FUNCTION_TRACER ++KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections ++endif ++ + # + # pass -msoft-float to GAS if it supports it. However on newer binutils + # (specifically newer than 2.24.51.20140728) we then also need to explicitly +--- a/arch/mips/kernel/vmlinux.lds.S ++++ b/arch/mips/kernel/vmlinux.lds.S +@@ -67,7 +67,7 @@ SECTIONS + /* Exception table for data bus errors */ + __dbe_table : { + __start___dbe_table = .; +- *(__dbe_table) ++ KEEP(*(__dbe_table)) + __stop___dbe_table = .; + } + +@@ -112,7 +112,7 @@ SECTIONS + . = ALIGN(4); + .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) { + __mips_machines_start = .; +- *(.mips.machines.init) ++ KEEP(*(.mips.machines.init)) + __mips_machines_end = .; + } + +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -89,7 +89,7 @@ + #ifdef CONFIG_FTRACE_MCOUNT_RECORD + #define MCOUNT_REC() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_mcount_loc) = .; \ +- *(__mcount_loc) \ ++ KEEP(*(__mcount_loc)) \ + VMLINUX_SYMBOL(__stop_mcount_loc) = .; + #else + #define MCOUNT_REC() +@@ -97,7 +97,7 @@ + + #ifdef CONFIG_TRACE_BRANCH_PROFILING + #define LIKELY_PROFILE() VMLINUX_SYMBOL(__start_annotated_branch_profile) = .; \ +- *(_ftrace_annotated_branch) \ ++ KEEP(*(_ftrace_annotated_branch)) \ + VMLINUX_SYMBOL(__stop_annotated_branch_profile) = .; + #else + #define LIKELY_PROFILE() +@@ -105,7 +105,7 @@ + + #ifdef CONFIG_PROFILE_ALL_BRANCHES + #define BRANCH_PROFILE() VMLINUX_SYMBOL(__start_branch_profile) = .; \ +- *(_ftrace_branch) \ ++ KEEP(*(_ftrace_branch)) \ + VMLINUX_SYMBOL(__stop_branch_profile) = .; + #else + #define BRANCH_PROFILE() +@@ -114,7 +114,7 @@ + #ifdef CONFIG_KPROBES + #define KPROBE_BLACKLIST() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_kprobe_blacklist) = .; \ +- *(_kprobe_blacklist) \ ++ KEEP(*(_kprobe_blacklist)) \ + VMLINUX_SYMBOL(__stop_kprobe_blacklist) = .; + #else + #define KPROBE_BLACKLIST() +@@ -123,10 +123,10 @@ + #ifdef CONFIG_EVENT_TRACING + #define FTRACE_EVENTS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_ftrace_events) = .; \ +- *(_ftrace_events) \ ++ KEEP(*(_ftrace_events)) \ + VMLINUX_SYMBOL(__stop_ftrace_events) = .; \ + VMLINUX_SYMBOL(__start_ftrace_enum_maps) = .; \ +- *(_ftrace_enum_map) \ ++ KEEP(*(_ftrace_enum_map)) \ + VMLINUX_SYMBOL(__stop_ftrace_enum_maps) = .; + #else + #define FTRACE_EVENTS() +@@ -134,7 +134,7 @@ + + #ifdef CONFIG_TRACING + #define TRACE_PRINTKS() VMLINUX_SYMBOL(__start___trace_bprintk_fmt) = .; \ +- *(__trace_printk_fmt) /* Trace_printk fmt' pointer */ \ ++ KEEP(*(__trace_printk_fmt)) /* Trace_printk fmt' pointer */ \ + VMLINUX_SYMBOL(__stop___trace_bprintk_fmt) = .; + #define TRACEPOINT_STR() VMLINUX_SYMBOL(__start___tracepoint_str) = .; \ + *(__tracepoint_str) /* Trace_printk fmt' pointer */ \ +@@ -147,7 +147,7 @@ + #ifdef CONFIG_FTRACE_SYSCALLS + #define TRACE_SYSCALLS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_syscalls_metadata) = .; \ +- *(__syscalls_metadata) \ ++ KEEP(*(__syscalls_metadata)) \ + VMLINUX_SYMBOL(__stop_syscalls_metadata) = .; + #else + #define TRACE_SYSCALLS() +@@ -169,8 +169,8 @@ + #define _OF_TABLE_1(name) \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__##name##_of_table) = .; \ +- *(__##name##_of_table) \ +- *(__##name##_of_table_end) ++ KEEP(*(__##name##_of_table)) \ ++ KEEP(*(__##name##_of_table_end)) + + #define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc) + #define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip) +@@ -184,7 +184,7 @@ + #define KERNEL_DTB() \ + STRUCT_ALIGN(); \ + VMLINUX_SYMBOL(__dtb_start) = .; \ +- *(.dtb.init.rodata) \ ++ KEEP(*(.dtb.init.rodata)) \ + VMLINUX_SYMBOL(__dtb_end) = .; + + /* .data section */ +@@ -200,16 +200,17 @@ + /* implement dynamic printk debug */ \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__start___jump_table) = .; \ +- *(__jump_table) \ ++ KEEP(*(__jump_table)) \ + VMLINUX_SYMBOL(__stop___jump_table) = .; \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__start___verbose) = .; \ +- *(__verbose) \ ++ KEEP(*(__verbose)) \ + VMLINUX_SYMBOL(__stop___verbose) = .; \ + LIKELY_PROFILE() \ + BRANCH_PROFILE() \ + TRACE_PRINTKS() \ +- TRACEPOINT_STR() ++ TRACEPOINT_STR() \ ++ *(.data.[a-zA-Z_]*) + + /* + * Data section helpers +@@ -263,35 +264,35 @@ + /* PCI quirks */ \ + .pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \ +- *(.pci_fixup_early) \ ++ KEEP(*(.pci_fixup_early)) \ + VMLINUX_SYMBOL(__end_pci_fixups_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_header) = .; \ +- *(.pci_fixup_header) \ ++ KEEP(*(.pci_fixup_header)) \ + VMLINUX_SYMBOL(__end_pci_fixups_header) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_final) = .; \ +- *(.pci_fixup_final) \ ++ KEEP(*(.pci_fixup_final)) \ + VMLINUX_SYMBOL(__end_pci_fixups_final) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_enable) = .; \ +- *(.pci_fixup_enable) \ ++ KEEP(*(.pci_fixup_enable)) \ + VMLINUX_SYMBOL(__end_pci_fixups_enable) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume) = .; \ +- *(.pci_fixup_resume) \ ++ KEEP(*(.pci_fixup_resume)) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .; \ +- *(.pci_fixup_resume_early) \ ++ KEEP(*(.pci_fixup_resume_early)) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \ +- *(.pci_fixup_suspend) \ ++ KEEP(*(.pci_fixup_suspend)) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend_late) = .; \ +- *(.pci_fixup_suspend_late) \ ++ KEEP(*(.pci_fixup_suspend_late)) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \ + } \ + \ + /* Built-in firmware blobs */ \ + .builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_builtin_fw) = .; \ +- *(.builtin_fw) \ ++ KEEP(*(.builtin_fw)) \ + VMLINUX_SYMBOL(__end_builtin_fw) = .; \ + } \ + \ +@@ -300,49 +301,49 @@ + /* Kernel symbol table: Normal symbols */ \ + __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab) = .; \ +- *(SORT(___ksymtab+*)) \ ++ KEEP(*(SORT(___ksymtab+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \ +- *(SORT(___ksymtab_gpl+*)) \ ++ KEEP(*(SORT(___ksymtab_gpl+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \ + } \ + \ + /* Kernel symbol table: Normal unused symbols */ \ + __ksymtab_unused : AT(ADDR(__ksymtab_unused) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_unused) = .; \ +- *(SORT(___ksymtab_unused+*)) \ ++ KEEP(*(SORT(___ksymtab_unused+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_unused) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only unused symbols */ \ + __ksymtab_unused_gpl : AT(ADDR(__ksymtab_unused_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_unused_gpl) = .; \ +- *(SORT(___ksymtab_unused_gpl+*)) \ ++ KEEP(*(SORT(___ksymtab_unused_gpl+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_unused_gpl) = .; \ + } \ + \ + /* Kernel symbol table: GPL-future-only symbols */ \ + __ksymtab_gpl_future : AT(ADDR(__ksymtab_gpl_future) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl_future) = .; \ +- *(SORT(___ksymtab_gpl_future+*)) \ ++ KEEP(*(SORT(___ksymtab_gpl_future+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl_future) = .; \ + } \ + \ + /* Kernel symbol table: Normal symbols */ \ + __kcrctab : AT(ADDR(__kcrctab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab) = .; \ +- *(SORT(___kcrctab+*)) \ ++ KEEP(*(SORT(___kcrctab+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_gpl) = .; \ +- *(SORT(___kcrctab_gpl+*)) \ ++ KEEP(*(SORT(___kcrctab_gpl+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_gpl) = .; \ + } \ + \ +@@ -356,14 +357,14 @@ + /* Kernel symbol table: GPL-only unused symbols */ \ + __kcrctab_unused_gpl : AT(ADDR(__kcrctab_unused_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_unused_gpl) = .; \ +- *(SORT(___kcrctab_unused_gpl+*)) \ ++ KEEP(*(SORT(___kcrctab_unused_gpl+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_unused_gpl) = .; \ + } \ + \ + /* Kernel symbol table: GPL-future-only symbols */ \ + __kcrctab_gpl_future : AT(ADDR(__kcrctab_gpl_future) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_gpl_future) = .; \ +- *(SORT(___kcrctab_gpl_future+*)) \ ++ KEEP(*(SORT(___kcrctab_gpl_future+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_gpl_future) = .; \ + } \ + \ +@@ -382,14 +383,14 @@ + /* Built-in module parameters. */ \ + __param : AT(ADDR(__param) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___param) = .; \ +- *(__param) \ ++ KEEP(*(__param)) \ + VMLINUX_SYMBOL(__stop___param) = .; \ + } \ + \ + /* Built-in module versions. */ \ + __modver : AT(ADDR(__modver) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___modver) = .; \ +- *(__modver) \ ++ KEEP(*(__modver)) \ + VMLINUX_SYMBOL(__stop___modver) = .; \ + . = ALIGN((align)); \ + VMLINUX_SYMBOL(__end_rodata) = .; \ +@@ -445,7 +446,7 @@ + #define ENTRY_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__entry_text_start) = .; \ +- *(.entry.text) \ ++ KEEP(*(.entry.text)) \ + VMLINUX_SYMBOL(__entry_text_end) = .; + + #ifdef CONFIG_FUNCTION_GRAPH_TRACER +@@ -473,7 +474,7 @@ + . = ALIGN(align); \ + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ex_table) = .; \ +- *(__ex_table) \ ++ KEEP(*(__ex_table)) \ + VMLINUX_SYMBOL(__stop___ex_table) = .; \ + } + +@@ -489,9 +490,9 @@ + #ifdef CONFIG_CONSTRUCTORS + #define KERNEL_CTORS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__ctors_start) = .; \ +- *(.ctors) \ ++ KEEP(*(.ctors)) \ + *(SORT(.init_array.*)) \ +- *(.init_array) \ ++ KEEP(*(.init_array)) \ + VMLINUX_SYMBOL(__ctors_end) = .; + #else + #define KERNEL_CTORS() +@@ -542,7 +543,7 @@ + #define SBSS(sbss_align) \ + . = ALIGN(sbss_align); \ + .sbss : AT(ADDR(.sbss) - LOAD_OFFSET) { \ +- *(.sbss) \ ++ *(.sbss .sbss.*) \ + *(.scommon) \ + } + +@@ -560,7 +561,7 @@ + BSS_FIRST_SECTIONS \ + *(.bss..page_aligned) \ + *(.dynbss) \ +- *(.bss) \ ++ *(.bss .bss.*) \ + *(COMMON) \ + } + +@@ -609,7 +610,7 @@ + . = ALIGN(8); \ + __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___bug_table) = .; \ +- *(__bug_table) \ ++ KEEP(*(__bug_table)) \ + VMLINUX_SYMBOL(__stop___bug_table) = .; \ + } + #else +@@ -621,7 +622,7 @@ + . = ALIGN(4); \ + .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__tracedata_start) = .; \ +- *(.tracedata) \ ++ KEEP(*(.tracedata)) \ + VMLINUX_SYMBOL(__tracedata_end) = .; \ + } + #else +@@ -638,17 +639,17 @@ + #define INIT_SETUP(initsetup_align) \ + . = ALIGN(initsetup_align); \ + VMLINUX_SYMBOL(__setup_start) = .; \ +- *(.init.setup) \ ++ KEEP(*(.init.setup)) \ + VMLINUX_SYMBOL(__setup_end) = .; + + #define INIT_CALLS_LEVEL(level) \ + VMLINUX_SYMBOL(__initcall##level##_start) = .; \ +- *(.initcall##level##.init) \ +- *(.initcall##level##s.init) \ ++ KEEP(*(.initcall##level##.init)) \ ++ KEEP(*(.initcall##level##s.init)) \ + + #define INIT_CALLS \ + VMLINUX_SYMBOL(__initcall_start) = .; \ +- *(.initcallearly.init) \ ++ KEEP(*(.initcallearly.init)) \ + INIT_CALLS_LEVEL(0) \ + INIT_CALLS_LEVEL(1) \ + INIT_CALLS_LEVEL(2) \ +@@ -662,21 +663,21 @@ + + #define CON_INITCALL \ + VMLINUX_SYMBOL(__con_initcall_start) = .; \ +- *(.con_initcall.init) \ ++ KEEP(*(.con_initcall.init)) \ + VMLINUX_SYMBOL(__con_initcall_end) = .; + + #define SECURITY_INITCALL \ + VMLINUX_SYMBOL(__security_initcall_start) = .; \ +- *(.security_initcall.init) \ ++ KEEP(*(.security_initcall.init)) \ + VMLINUX_SYMBOL(__security_initcall_end) = .; + + #ifdef CONFIG_BLK_DEV_INITRD + #define INIT_RAM_FS \ + . = ALIGN(4); \ + VMLINUX_SYMBOL(__initramfs_start) = .; \ +- *(.init.ramfs) \ ++ KEEP(*(.init.ramfs)) \ + . = ALIGN(8); \ +- *(.init.ramfs.info) ++ KEEP(*(.init.ramfs.info)) + #else + #define INIT_RAM_FS + #endif +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -18,11 +18,16 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) + LDFLAGS_vmlinux += --be8 + LDFLAGS_MODULE += --be8 + endif ++LDFLAGS_vmlinux += --gc-sections + + OBJCOPYFLAGS :=-O binary -R .comment -S + GZFLAGS :=-9 + #KBUILD_CFLAGS +=-pipe + ++ifndef CONFIG_FUNCTION_TRACER ++KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections ++endif ++ + # Never generate .eh_frame + KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) + +--- a/arch/arm/kernel/vmlinux.lds.S ++++ b/arch/arm/kernel/vmlinux.lds.S +@@ -15,13 +15,13 @@ + #define PROC_INFO \ + . = ALIGN(4); \ + VMLINUX_SYMBOL(__proc_info_begin) = .; \ +- *(.proc.info.init) \ ++ KEEP(*(.proc.info.init)) \ + VMLINUX_SYMBOL(__proc_info_end) = .; + + #define IDMAP_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__idmap_text_start) = .; \ +- *(.idmap.text) \ ++ KEEP(*(.idmap.text)) \ + VMLINUX_SYMBOL(__idmap_text_end) = .; \ + . = ALIGN(PAGE_SIZE); \ + VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \ +@@ -102,7 +102,7 @@ SECTIONS + _stext = .; /* Text and read-only data */ + IDMAP_TEXT + __exception_text_start = .; +- *(.exception.text) ++ KEEP(*(.exception.text)) + __exception_text_end = .; + IRQENTRY_TEXT + TEXT_TEXT +@@ -126,7 +126,7 @@ SECTIONS + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { + __start___ex_table = .; + #ifdef CONFIG_MMU +- *(__ex_table) ++ KEEP(*(__ex_table)) + #endif + __stop___ex_table = .; + } +@@ -138,12 +138,12 @@ SECTIONS + . = ALIGN(8); + .ARM.unwind_idx : { + __start_unwind_idx = .; +- *(.ARM.exidx*) ++ KEEP(*(.ARM.exidx*)) + __stop_unwind_idx = .; + } + .ARM.unwind_tab : { + __start_unwind_tab = .; +- *(.ARM.extab*) ++ KEEP(*(.ARM.extab*)) + __stop_unwind_tab = .; + } + #endif +@@ -166,14 +166,14 @@ SECTIONS + */ + __vectors_start = .; + .vectors 0 : AT(__vectors_start) { +- *(.vectors) ++ KEEP(*(.vectors)) + } + . = __vectors_start + SIZEOF(.vectors); + __vectors_end = .; + + __stubs_start = .; + .stubs 0x1000 : AT(__stubs_start) { +- *(.stubs) ++ KEEP(*(.stubs)) + } + . = __stubs_start + SIZEOF(.stubs); + __stubs_end = .; +@@ -187,24 +187,24 @@ SECTIONS + } + .init.arch.info : { + __arch_info_begin = .; +- *(.arch.info.init) ++ KEEP(*(.arch.info.init)) + __arch_info_end = .; + } + .init.tagtable : { + __tagtable_begin = .; +- *(.taglist.init) ++ KEEP(*(.taglist.init)) + __tagtable_end = .; + } + #ifdef CONFIG_SMP_ON_UP + .init.smpalt : { + __smpalt_begin = .; +- *(.alt.smp.init) ++ KEEP(*(.alt.smp.init)) + __smpalt_end = .; + } + #endif + .init.pv_table : { + __pv_table_begin = .; +- *(.pv_table) ++ KEEP(*(.pv_table)) + __pv_table_end = .; + } + .init.data : { +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -107,6 +107,7 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) + ORIG_CFLAGS := $(KBUILD_CFLAGS) + KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) + endif ++KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL)) + + ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) + asflags-y := -DZIMAGE diff --git a/target/linux/generic/patches-4.1/221-module_exports.patch b/target/linux/generic/patches-4.1/221-module_exports.patch new file mode 100644 index 0000000..57e2549 --- /dev/null +++ b/target/linux/generic/patches-4.1/221-module_exports.patch @@ -0,0 +1,88 @@ +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -54,6 +54,16 @@ + #define LOAD_OFFSET 0 + #endif + ++#ifndef SYMTAB_KEEP ++#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*))) ++#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*))) ++#endif ++ ++#ifndef SYMTAB_DISCARD ++#define SYMTAB_DISCARD ++#define SYMTAB_DISCARD_GPL ++#endif ++ + #include + + /* Align . to a 8 byte boundary equals to maximum function alignment. */ +@@ -301,14 +311,14 @@ + /* Kernel symbol table: Normal symbols */ \ + __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab) = .; \ +- KEEP(*(SORT(___ksymtab+*))) \ ++ SYMTAB_KEEP \ + VMLINUX_SYMBOL(__stop___ksymtab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \ +- KEEP(*(SORT(___ksymtab_gpl+*))) \ ++ SYMTAB_KEEP_GPL \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \ + } \ + \ +@@ -370,7 +380,7 @@ + \ + /* Kernel symbol table: strings */ \ + __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \ +- *(__ksymtab_strings) \ ++ *(__ksymtab_strings+*) \ + } \ + \ + /* __*init sections */ \ +@@ -696,6 +706,8 @@ + EXIT_TEXT \ + EXIT_DATA \ + EXIT_CALL \ ++ SYMTAB_DISCARD \ ++ SYMTAB_DISCARD_GPL \ + *(.discard) \ + *(.discard.*) \ + } +--- a/scripts/Makefile.build ++++ b/scripts/Makefile.build +@@ -299,7 +299,7 @@ targets += $(extra-y) $(MAKECMDGOALS) $( + # Linker scripts preprocessor (.lds.S -> .lds) + # --------------------------------------------------------------------------- + quiet_cmd_cpp_lds_S = LDS $@ +- cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \ ++ cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -C -U$(ARCH) \ + -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< + + $(obj)/%.lds: $(src)/%.lds.S FORCE +--- a/include/linux/export.h ++++ b/include/linux/export.h +@@ -52,12 +52,19 @@ extern struct module __this_module; + #define __CRC_SYMBOL(sym, sec) + #endif + ++#ifdef MODULE ++#define __EXPORT_SUFFIX(sym) ++#else ++#define __EXPORT_SUFFIX(sym) "+" #sym ++#endif ++ + /* For every exported symbol, place a struct in the __ksymtab section */ + #define __EXPORT_SYMBOL(sym, sec) \ + extern typeof(sym) sym; \ + __CRC_SYMBOL(sym, sec) \ + static const char __kstrtab_##sym[] \ +- __attribute__((section("__ksymtab_strings"), aligned(1))) \ ++ __attribute__((section("__ksymtab_strings" \ ++ __EXPORT_SUFFIX(sym)), aligned(1))) \ + = VMLINUX_SYMBOL_STR(sym); \ + extern const struct kernel_symbol __ksymtab_##sym; \ + __visible const struct kernel_symbol __ksymtab_##sym \ diff --git a/target/linux/generic/patches-4.1/222-perf-build-Do-not-fail-on-missing-Build-file.patch b/target/linux/generic/patches-4.1/222-perf-build-Do-not-fail-on-missing-Build-file.patch new file mode 100644 index 0000000..3fb2df6 --- /dev/null +++ b/target/linux/generic/patches-4.1/222-perf-build-Do-not-fail-on-missing-Build-file.patch @@ -0,0 +1,67 @@ +From d7a3d85e08477a979933a2bb3b525a8de99543c2 Mon Sep 17 00:00:00 2001 +From: Jiri Olsa +Date: Fri, 29 May 2015 17:42:58 +0200 +Subject: [PATCH] perf build: Do not fail on missing Build file + +Allow nesting into directories without Build file. Currently we force +include of the Build file, which fails the build when the Build file is +missing. + +We already support empty *-in.o' objects if there's nothing in the +directory to be compiled, so we can just use it for missing Build file +cases. + +Also adding this case under tests. + +Reported-by: Rabin Vincent +Signed-off-by: Jiri Olsa +Cc: David Ahern +Cc: Namhyung Kim +Cc: Paul Mackerras +Cc: Peter Zijlstra +Cc: Rabin Vincent +Link: http://lkml.kernel.org/r/1432914178-24086-1-git-send-email-jolsa@kernel.org +Signed-off-by: Arnaldo Carvalho de Melo +--- + tools/build/Makefile.build | 2 +- + tools/build/tests/ex/Build | 1 + + tools/build/tests/ex/empty2/README | 2 ++ + 3 files changed, 4 insertions(+), 1 deletion(-) + create mode 100644 tools/build/tests/ex/empty2/README + +diff --git a/tools/build/Makefile.build b/tools/build/Makefile.build +index 10df572..69c35cf 100644 +--- a/tools/build/Makefile.build ++++ b/tools/build/Makefile.build +@@ -37,7 +37,7 @@ subdir-obj-y := + + # Build definitions + build-file := $(dir)/Build +-include $(build-file) ++-include $(build-file) + + quiet_cmd_flex = FLEX $@ + quiet_cmd_bison = BISON $@ +diff --git a/tools/build/tests/ex/Build b/tools/build/tests/ex/Build +index 0e6c3e6..70d8762 100644 +--- a/tools/build/tests/ex/Build ++++ b/tools/build/tests/ex/Build +@@ -2,6 +2,7 @@ ex-y += ex.o + ex-y += a.o + ex-y += b.o + ex-y += empty/ ++ex-y += empty2/ + + libex-y += c.o + libex-y += d.o +diff --git a/tools/build/tests/ex/empty2/README b/tools/build/tests/ex/empty2/README +new file mode 100644 +index 0000000..2107cc5 +--- /dev/null ++++ b/tools/build/tests/ex/empty2/README +@@ -0,0 +1,2 @@ ++This directory is left intentionally without Build file ++to test proper nesting into Build-less directories. +-- +2.1.4 + diff --git a/target/linux/generic/patches-4.1/230-openwrt_lzma_options.patch b/target/linux/generic/patches-4.1/230-openwrt_lzma_options.patch new file mode 100644 index 0000000..d5bbb19 --- /dev/null +++ b/target/linux/generic/patches-4.1/230-openwrt_lzma_options.patch @@ -0,0 +1,58 @@ +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -324,7 +324,7 @@ cmd_bzip2 = (cat $(filter-out FORCE,$^) + + quiet_cmd_lzma = LZMA $@ + cmd_lzma = (cat $(filter-out FORCE,$^) | \ +- lzma -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ ++ lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + + quiet_cmd_lzo = LZO $@ +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -226,7 +226,7 @@ cpio_list= + output="/dev/stdout" + output_file="" + is_cpio_compressed= +-compr="gzip -n -9 -f" ++compr="gzip -n -9 -f -" + + arg="$1" + case "$arg" in +@@ -242,13 +242,13 @@ case "$arg" in + output=${cpio_list} + echo "$output_file" | grep -q "\.gz$" \ + && [ -x "`which gzip 2> /dev/null`" ] \ +- && compr="gzip -n -9 -f" ++ && compr="gzip -n -9 -f -" + echo "$output_file" | grep -q "\.bz2$" \ + && [ -x "`which bzip2 2> /dev/null`" ] \ +- && compr="bzip2 -9 -f" ++ && compr="bzip2 -9 -f -" + echo "$output_file" | grep -q "\.lzma$" \ + && [ -x "`which lzma 2> /dev/null`" ] \ +- && compr="lzma -9 -f" ++ && compr="lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so" + echo "$output_file" | grep -q "\.xz$" \ + && [ -x "`which xz 2> /dev/null`" ] \ + && compr="xz --check=crc32 --lzma2=dict=1MiB" +@@ -315,7 +315,7 @@ if [ ! -z ${output_file} ]; then + if [ "${is_cpio_compressed}" = "compressed" ]; then + cat ${cpio_tfile} > ${output_file} + else +- (cat ${cpio_tfile} | ${compr} - > ${output_file}) \ ++ (cat ${cpio_tfile} | ${compr} > ${output_file}) \ + || (rm -f ${output_file} ; false) + fi + [ -z ${cpio_file} ] && rm ${cpio_tfile} +--- a/lib/decompress.c ++++ b/lib/decompress.c +@@ -48,6 +48,7 @@ static const struct compress_format comp + { {0x1f, 0x9e}, "gzip", gunzip }, + { {0x42, 0x5a}, "bzip2", bunzip2 }, + { {0x5d, 0x00}, "lzma", unlzma }, ++ { {0x6d, 0x00}, "lzma-openwrt", unlzma }, + { {0xfd, 0x37}, "xz", unxz }, + { {0x89, 0x4c}, "lzo", unlzo }, + { {0x02, 0x21}, "lz4", unlz4 }, diff --git a/target/linux/generic/patches-4.1/250-netfilter_depends.patch b/target/linux/generic/patches-4.1/250-netfilter_depends.patch new file mode 100644 index 0000000..2b0815d --- /dev/null +++ b/target/linux/generic/patches-4.1/250-netfilter_depends.patch @@ -0,0 +1,18 @@ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -210,7 +210,6 @@ config NF_CONNTRACK_FTP + + config NF_CONNTRACK_H323 + tristate "H.323 protocol support" +- depends on (IPV6 || IPV6=n) + depends on NETFILTER_ADVANCED + help + H.323 is a VoIP signalling protocol from ITU-T. As one of the most +@@ -914,7 +913,6 @@ config NETFILTER_XT_TARGET_SECMARK + + config NETFILTER_XT_TARGET_TCPMSS + tristate '"TCPMSS" target support' +- depends on (IPV6 || IPV6=n) + default m if NETFILTER_ADVANCED=n + ---help--- + This option adds a `TCPMSS' target, which allows you to alter the diff --git a/target/linux/generic/patches-4.1/251-sound_kconfig.patch b/target/linux/generic/patches-4.1/251-sound_kconfig.patch new file mode 100644 index 0000000..c2ebace --- /dev/null +++ b/target/linux/generic/patches-4.1/251-sound_kconfig.patch @@ -0,0 +1,18 @@ +--- a/sound/core/Kconfig ++++ b/sound/core/Kconfig +@@ -10,13 +10,13 @@ config SND_DMAENGINE_PCM + tristate + + config SND_HWDEP +- tristate ++ tristate "Sound hardware support" + + config SND_RAWMIDI + tristate + + config SND_COMPRESS_OFFLOAD +- tristate ++ tristate "Compression offloading support" + + # To be effective this also requires INPUT - users should say: + # select SND_JACK if INPUT=y || INPUT=SND diff --git a/target/linux/generic/patches-4.1/252-mv_cesa_depends.patch b/target/linux/generic/patches-4.1/252-mv_cesa_depends.patch new file mode 100644 index 0000000..fee28db --- /dev/null +++ b/target/linux/generic/patches-4.1/252-mv_cesa_depends.patch @@ -0,0 +1,10 @@ +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -164,6 +164,7 @@ config CRYPTO_DEV_MV_CESA + depends on PLAT_ORION + select CRYPTO_ALGAPI + select CRYPTO_AES ++ select CRYPTO_HASH2 + select CRYPTO_BLKCIPHER2 + select CRYPTO_HASH + help diff --git a/target/linux/generic/patches-4.1/253-ssb_b43_default_on.patch b/target/linux/generic/patches-4.1/253-ssb_b43_default_on.patch new file mode 100644 index 0000000..29d2a41 --- /dev/null +++ b/target/linux/generic/patches-4.1/253-ssb_b43_default_on.patch @@ -0,0 +1,29 @@ +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -29,6 +29,7 @@ config SSB_SPROM + config SSB_BLOCKIO + bool + depends on SSB ++ default y + + config SSB_PCIHOST_POSSIBLE + bool +@@ -49,7 +50,7 @@ config SSB_PCIHOST + config SSB_B43_PCI_BRIDGE + bool + depends on SSB_PCIHOST +- default n ++ default y + + config SSB_PCMCIAHOST_POSSIBLE + bool +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -17,6 +17,7 @@ config BCMA + config BCMA_BLOCKIO + bool + depends on BCMA ++ default y + + config BCMA_HOST_PCI_POSSIBLE + bool diff --git a/target/linux/generic/patches-4.1/254-textsearch_kconfig_hacks.patch b/target/linux/generic/patches-4.1/254-textsearch_kconfig_hacks.patch new file mode 100644 index 0000000..d682d4e --- /dev/null +++ b/target/linux/generic/patches-4.1/254-textsearch_kconfig_hacks.patch @@ -0,0 +1,23 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -328,16 +328,16 @@ config BCH_CONST_T + # Textsearch support is select'ed if needed + # + config TEXTSEARCH +- bool ++ boolean "Textsearch support" + + config TEXTSEARCH_KMP +- tristate ++ tristate "Textsearch KMP" + + config TEXTSEARCH_BM +- tristate ++ tristate "Textsearch BM" + + config TEXTSEARCH_FSM +- tristate ++ tristate "Textsearch FSM" + + config BTREE + bool diff --git a/target/linux/generic/patches-4.1/255-lib80211_kconfig_hacks.patch b/target/linux/generic/patches-4.1/255-lib80211_kconfig_hacks.patch new file mode 100644 index 0000000..8064b02 --- /dev/null +++ b/target/linux/generic/patches-4.1/255-lib80211_kconfig_hacks.patch @@ -0,0 +1,31 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -191,7 +191,7 @@ config CFG80211_WEXT_EXPORT + wext compatibility symbols to be exported. + + config LIB80211 +- tristate ++ tristate "LIB80211" + default n + help + This options enables a library of common routines used +@@ -200,13 +200,16 @@ config LIB80211 + Drivers should select this themselves if needed. + + config LIB80211_CRYPT_WEP +- tristate ++ tristate "LIB80211_CRYPT_WEP" ++ select LIB80211 + + config LIB80211_CRYPT_CCMP +- tristate ++ tristate "LIB80211_CRYPT_CCMP" ++ select LIB80211 + + config LIB80211_CRYPT_TKIP +- tristate ++ tristate "LIB80211_CRYPT_TKIP" ++ select LIB80211 + + config LIB80211_DEBUG + bool "lib80211 debugging messages" diff --git a/target/linux/generic/patches-4.1/256-crypto_add_kconfig_prompts.patch b/target/linux/generic/patches-4.1/256-crypto_add_kconfig_prompts.patch new file mode 100644 index 0000000..f9f6c0e --- /dev/null +++ b/target/linux/generic/patches-4.1/256-crypto_add_kconfig_prompts.patch @@ -0,0 +1,47 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -32,7 +32,7 @@ config CRYPTO_FIPS + this is. + + config CRYPTO_ALGAPI +- tristate ++ tristate "ALGAPI" + select CRYPTO_ALGAPI2 + help + This option provides the API for cryptographic algorithms. +@@ -41,7 +41,7 @@ config CRYPTO_ALGAPI2 + tristate + + config CRYPTO_AEAD +- tristate ++ tristate "AEAD" + select CRYPTO_AEAD2 + select CRYPTO_ALGAPI + +@@ -50,7 +50,7 @@ config CRYPTO_AEAD2 + select CRYPTO_ALGAPI2 + + config CRYPTO_BLKCIPHER +- tristate ++ tristate "BLKCIPHER" + select CRYPTO_BLKCIPHER2 + select CRYPTO_ALGAPI + +@@ -61,7 +61,7 @@ config CRYPTO_BLKCIPHER2 + select CRYPTO_WORKQUEUE + + config CRYPTO_HASH +- tristate ++ tristate "HASH" + select CRYPTO_HASH2 + select CRYPTO_ALGAPI + +@@ -70,7 +70,7 @@ config CRYPTO_HASH2 + select CRYPTO_ALGAPI2 + + config CRYPTO_RNG +- tristate ++ tristate "RNG" + select CRYPTO_RNG2 + select CRYPTO_ALGAPI + diff --git a/target/linux/generic/patches-4.1/257-wireless_ext_kconfig_hack.patch b/target/linux/generic/patches-4.1/257-wireless_ext_kconfig_hack.patch new file mode 100644 index 0000000..daac589 --- /dev/null +++ b/target/linux/generic/patches-4.1/257-wireless_ext_kconfig_hack.patch @@ -0,0 +1,22 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -1,5 +1,5 @@ + config WIRELESS_EXT +- bool ++ bool "Wireless extensions" + + config WEXT_CORE + def_bool y +@@ -11,10 +11,10 @@ config WEXT_PROC + depends on WEXT_CORE + + config WEXT_SPY +- bool ++ bool "WEXT_SPY" + + config WEXT_PRIV +- bool ++ bool "WEXT_PRIV" + + config CFG80211 + tristate "cfg80211 - wireless configuration API" diff --git a/target/linux/generic/patches-4.1/258-netfilter_netlink_kconfig_hack.patch b/target/linux/generic/patches-4.1/258-netfilter_netlink_kconfig_hack.patch new file mode 100644 index 0000000..9d827c2 --- /dev/null +++ b/target/linux/generic/patches-4.1/258-netfilter_netlink_kconfig_hack.patch @@ -0,0 +1,11 @@ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -2,7 +2,7 @@ menu "Core Netfilter Configuration" + depends on NET && INET && NETFILTER + + config NETFILTER_NETLINK +- tristate ++ tristate "Netfilter NFNETLINK interface" + + config NETFILTER_NETLINK_ACCT + tristate "Netfilter NFACCT over NFNETLINK interface" diff --git a/target/linux/generic/patches-4.1/259-regmap_dynamic.patch b/target/linux/generic/patches-4.1/259-regmap_dynamic.patch new file mode 100644 index 0000000..a4bdae6 --- /dev/null +++ b/target/linux/generic/patches-4.1/259-regmap_dynamic.patch @@ -0,0 +1,87 @@ +--- a/drivers/base/regmap/Kconfig ++++ b/drivers/base/regmap/Kconfig +@@ -3,29 +3,35 @@ + # subsystems should select the appropriate symbols. + + config REGMAP +- default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ) + select LZO_COMPRESS + select LZO_DECOMPRESS + select IRQ_DOMAIN if REGMAP_IRQ +- bool ++ tristate "Regmap" + + config REGMAP_AC97 ++ select REGMAP + tristate + + config REGMAP_I2C +- tristate ++ tristate "Regmap I2C" ++ select REGMAP + depends on I2C + + config REGMAP_SPI +- tristate ++ tristate "Regmap SPI" ++ select REGMAP ++ depends on SPI_MASTER + depends on SPI + + config REGMAP_SPMI ++ select REGMAP + tristate + depends on SPMI + + config REGMAP_MMIO +- tristate ++ tristate "Regmap MMIO" ++ select REGMAP + + config REGMAP_IRQ ++ select REGMAP + bool +--- a/include/linux/regmap.h ++++ b/include/linux/regmap.h +@@ -50,7 +50,7 @@ struct reg_default { + unsigned int def; + }; + +-#ifdef CONFIG_REGMAP ++#if IS_ENABLED(CONFIG_REGMAP) + + enum regmap_endian { + /* Unspecified -> 0 -> Backwards compatible default */ +--- a/drivers/base/regmap/Makefile ++++ b/drivers/base/regmap/Makefile +@@ -1,9 +1,11 @@ + # For include/trace/define_trace.h to include trace.h + CFLAGS_regmap.o := -I$(src) + +-obj-$(CONFIG_REGMAP) += regmap.o regcache.o +-obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-lzo.o regcache-flat.o +-obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o ++regmap-core-objs = regmap.o regcache.o regcache-rbtree.o regcache-lzo.o regcache-flat.o ++ifdef CONFIG_DEBUG_FS ++regmap-core-objs += regmap-debugfs.o ++endif ++obj-$(CONFIG_REGMAP) += regmap-core.o + obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o + obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o + obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o +--- a/drivers/base/regmap/regmap.c ++++ b/drivers/base/regmap/regmap.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -2631,3 +2632,5 @@ static int __init regmap_initcall(void) + return 0; + } + postcore_initcall(regmap_initcall); ++ ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.1/260-crypto_test_dependencies.patch b/target/linux/generic/patches-4.1/260-crypto_test_dependencies.patch new file mode 100644 index 0000000..8a96fd9 --- /dev/null +++ b/target/linux/generic/patches-4.1/260-crypto_test_dependencies.patch @@ -0,0 +1,37 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -96,10 +96,10 @@ config CRYPTO_MANAGER + + config CRYPTO_MANAGER2 + def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) +- select CRYPTO_AEAD2 +- select CRYPTO_HASH2 +- select CRYPTO_BLKCIPHER2 +- select CRYPTO_PCOMP2 ++ select CRYPTO_AEAD2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_HASH2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_BLKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_PCOMP2 if !CRYPTO_MANAGER_DISABLE_TESTS + + config CRYPTO_USER + tristate "Userspace cryptographic algorithm configuration" +--- a/crypto/algboss.c ++++ b/crypto/algboss.c +@@ -248,6 +248,9 @@ static int cryptomgr_schedule_test(struc + type = alg->cra_flags; + + /* This piece of crap needs to disappear into per-type test hooks. */ ++#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS ++ type |= CRYPTO_ALG_TESTED; ++#else + if ((!((type ^ CRYPTO_ALG_TYPE_BLKCIPHER) & + CRYPTO_ALG_TYPE_BLKCIPHER_MASK) && !(type & CRYPTO_ALG_GENIV) && + ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == +@@ -256,6 +259,7 @@ static int cryptomgr_schedule_test(struc + (!((type ^ CRYPTO_ALG_TYPE_AEAD) & CRYPTO_ALG_TYPE_MASK) && + alg->cra_type == &crypto_nivaead_type && alg->cra_aead.ivsize)) + type |= CRYPTO_ALG_TESTED; ++#endif + + param->type = type; + diff --git a/target/linux/generic/patches-4.1/262-compressor_kconfig_hack.patch b/target/linux/generic/patches-4.1/262-compressor_kconfig_hack.patch new file mode 100644 index 0000000..771c167 --- /dev/null +++ b/target/linux/generic/patches-4.1/262-compressor_kconfig_hack.patch @@ -0,0 +1,35 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -213,25 +213,25 @@ config RANDOM32_SELFTEST + # compression support is select'ed if needed + # + config ZLIB_INFLATE +- tristate ++ tristate "ZLIB inflate support" + + config ZLIB_DEFLATE +- tristate ++ tristate "ZLIB deflate support" + + config LZO_COMPRESS +- tristate ++ tristate "LZO compress support" + + config LZO_DECOMPRESS +- tristate ++ tristate "LZO decompress support" + + config LZ4_COMPRESS +- tristate ++ tristate "LZ4 compress support" + + config LZ4HC_COMPRESS +- tristate ++ tristate "LZ4HC compress support" + + config LZ4_DECOMPRESS +- tristate ++ tristate "LZ4 decompress support" + + source "lib/xz/Kconfig" + diff --git a/target/linux/generic/patches-4.1/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch b/target/linux/generic/patches-4.1/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch new file mode 100644 index 0000000..762f498 --- /dev/null +++ b/target/linux/generic/patches-4.1/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch @@ -0,0 +1,34 @@ +From 8b05e325824d3b38e52a7748b3b5dc34dc1c0f6d Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 14:37:54 +0200 +Subject: [PATCH 1/3] uapi/kernel.h: glibc specific inclusion of sysinfo.h + +including sysinfo.h from kernel.h makes no sense whatsoever, +but removing it breaks glibc's userspace header, +which includes kernel.h instead of sysinfo.h from their sys/sysinfo.h. +this seems to be a historical mistake. +on musl, including any header that uses kernel.h directly or indirectly +plus sys/sysinfo.h will produce a compile error due to redefinition of +struct sysinfo from sys/sysinfo.h. +so for now, only include it on glibc or when including from kernel +in order not to break their headers. + +Signed-off-by: John Spencer +Signed-off-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/kernel.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/include/uapi/linux/kernel.h ++++ b/include/uapi/linux/kernel.h +@@ -1,7 +1,9 @@ + #ifndef _UAPI_LINUX_KERNEL_H + #define _UAPI_LINUX_KERNEL_H + ++#if defined(__KERNEL__) || defined( __GLIBC__) + #include ++#endif + + /* + * 'kernel.h' contains some often-used function prototypes etc diff --git a/target/linux/generic/patches-4.1/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch b/target/linux/generic/patches-4.1/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch new file mode 100644 index 0000000..61d3873 --- /dev/null +++ b/target/linux/generic/patches-4.1/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch @@ -0,0 +1,81 @@ +From f972afc2509eebcb00d370256c55b112a3b5ffca Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 16:50:40 +0200 +Subject: [PATCH 2/3] uapi/libc-compat.h: do not rely on __GLIBC__ + +Musl provides the same structs as glibc, but does not provide a define to +allow its detection. Since the absence of __GLIBC__ also can mean that it +is included from the kernel, change the __GLIBC__ detection to +!__KERNEL__, which should always be true when included from userspace. + +Signed-off-by: John Spencer +Tested-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/libc-compat.h | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -48,13 +48,13 @@ + #ifndef _UAPI_LIBC_COMPAT_H + #define _UAPI_LIBC_COMPAT_H + +-/* We have included glibc headers... */ +-#if defined(__GLIBC__) ++/* We have included libc headers... */ ++#if !defined(__KERNEL__) + +-/* Coordinate with glibc netinet/in.h header. */ ++/* Coordinate with libc netinet/in.h header. */ + #if defined(_NETINET_IN_H) + +-/* GLIBC headers included first so don't define anything ++/* LIBC headers included first so don't define anything + * that would already be defined. */ + #define __UAPI_DEF_IN_ADDR 0 + #define __UAPI_DEF_IN_IPPROTO 0 +@@ -68,7 +68,7 @@ + * if the glibc code didn't define them. This guard matches + * the guard in glibc/inet/netinet/in.h which defines the + * additional in6_addr macros e.g. s6_addr16, and s6_addr32. */ +-#if defined(__USE_MISC) || defined (__USE_GNU) ++#if !defined(__GLIBC__) || defined(__USE_MISC) || defined (__USE_GNU) + #define __UAPI_DEF_IN6_ADDR_ALT 0 + #else + #define __UAPI_DEF_IN6_ADDR_ALT 1 +@@ -83,7 +83,7 @@ + #else + + /* Linux headers included first, and we must define everything +- * we need. The expectation is that glibc will check the ++ * we need. The expectation is that the libc will check the + * __UAPI_DEF_* defines and adjust appropriately. */ + #define __UAPI_DEF_IN_ADDR 1 + #define __UAPI_DEF_IN_IPPROTO 1 +@@ -93,7 +93,7 @@ + #define __UAPI_DEF_IN_CLASS 1 + + #define __UAPI_DEF_IN6_ADDR 1 +-/* We unconditionally define the in6_addr macros and glibc must ++/* We unconditionally define the in6_addr macros and the libc must + * coordinate. */ + #define __UAPI_DEF_IN6_ADDR_ALT 1 + #define __UAPI_DEF_SOCKADDR_IN6 1 +@@ -115,7 +115,7 @@ + /* If we did not see any headers from any supported C libraries, + * or we are being included in the kernel, then define everything + * that we need. */ +-#else /* !defined(__GLIBC__) */ ++#else /* defined(__KERNEL__) */ + + /* Definitions for in.h */ + #define __UAPI_DEF_IN_ADDR 1 +@@ -138,6 +138,6 @@ + /* Definitions for xattr.h */ + #define __UAPI_DEF_XATTR 1 + +-#endif /* __GLIBC__ */ ++#endif /* __KERNEL__ */ + + #endif /* _UAPI_LIBC_COMPAT_H */ diff --git a/target/linux/generic/patches-4.1/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch b/target/linux/generic/patches-4.1/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch new file mode 100644 index 0000000..257c9d7 --- /dev/null +++ b/target/linux/generic/patches-4.1/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch @@ -0,0 +1,67 @@ +From fcbb6fed85ea9ff4feb4f1ebd4f0f235fdaf06b6 Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 16:53:03 +0200 +Subject: [PATCH 3/3] uapi/if_ether.h: prevent redefinition of struct ethhdr + +Musl provides its own ethhdr struct definition. Add a guard to prevent +its definition of the appropriate musl header has already been included. + +Signed-off-by: John Spencer +Tested-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/if_ether.h | 3 +++ + include/uapi/linux/libc-compat.h | 11 +++++++++++ + 2 files changed, 14 insertions(+) + +--- a/include/uapi/linux/if_ether.h ++++ b/include/uapi/linux/if_ether.h +@@ -22,6 +22,7 @@ + #define _UAPI_LINUX_IF_ETHER_H + + #include ++#include + + /* + * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble +@@ -134,11 +135,13 @@ + * This is an Ethernet frame header. + */ + ++#if __UAPI_DEF_ETHHDR + struct ethhdr { + unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ + unsigned char h_source[ETH_ALEN]; /* source ether addr */ + __be16 h_proto; /* packet type ID field */ + } __attribute__((packed)); ++#endif + + + #endif /* _UAPI_LINUX_IF_ETHER_H */ +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -51,6 +51,14 @@ + /* We have included libc headers... */ + #if !defined(__KERNEL__) + ++/* musl defines the ethhdr struct itself in its netinet/if_ether.h. ++ * Glibc just includes the kernel header and uses a different guard. */ ++#if defined(_NETINET_IF_ETHER_H) ++#define __UAPI_DEF_ETHHDR 0 ++#else ++#define __UAPI_DEF_ETHHDR 1 ++#endif ++ + /* Coordinate with libc netinet/in.h header. */ + #if defined(_NETINET_IN_H) + +@@ -117,6 +125,9 @@ + * that we need. */ + #else /* defined(__KERNEL__) */ + ++/* Definitions for if_ether.h */ ++#define __UAPI_DEF_ETHHDR 1 ++ + /* Definitions for in.h */ + #define __UAPI_DEF_IN_ADDR 1 + #define __UAPI_DEF_IN_IPPROTO 1 diff --git a/target/linux/generic/patches-4.1/300-mips_expose_boot_raw.patch b/target/linux/generic/patches-4.1/300-mips_expose_boot_raw.patch new file mode 100644 index 0000000..49f2ded --- /dev/null +++ b/target/linux/generic/patches-4.1/300-mips_expose_boot_raw.patch @@ -0,0 +1,39 @@ +From: Mark Miller + +This exposes the CONFIG_BOOT_RAW symbol in Kconfig. This is needed on +certain Broadcom chipsets running CFE in order to load the kernel. + +Signed-off-by: Mark Miller +Acked-by: Rob Landley +--- +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -984,9 +984,6 @@ config FW_ARC + config ARCH_MAY_HAVE_PC_FDC + bool + +-config BOOT_RAW +- bool +- + config CEVT_BCM1480 + bool + +@@ -2676,6 +2673,18 @@ config USE_OF + config BUILTIN_DTB + bool + ++config BOOT_RAW ++ bool "Enable the kernel to be executed from the load address" ++ default n ++ help ++ Allow the kernel to be executed from the load address for ++ bootloaders which cannot read the ELF format. This places ++ a jump to start_kernel at the load address. ++ ++ If unsure, say N. ++ ++ ++ + endmenu + + config LOCKDEP_SUPPORT diff --git a/target/linux/generic/patches-4.1/301-mips_image_cmdline_hack.patch b/target/linux/generic/patches-4.1/301-mips_image_cmdline_hack.patch new file mode 100644 index 0000000..f853104 --- /dev/null +++ b/target/linux/generic/patches-4.1/301-mips_image_cmdline_hack.patch @@ -0,0 +1,28 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1073,6 +1073,10 @@ config SYNC_R4K + config MIPS_MACHINE + def_bool n + ++config IMAGE_CMDLINE_HACK ++ bool "OpenWrt specific image command line hack" ++ default n ++ + config NO_IOPORT_MAP + def_bool n + +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -80,6 +80,12 @@ FEXPORT(__kernel_entry) + j kernel_entry + #endif + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++ .ascii "CMDLINE:" ++EXPORT(__image_cmdline) ++ .fill 0x400 ++#endif /* CONFIG_IMAGE_CMDLINE_HACK */ ++ + __REF + + NESTED(kernel_entry, 16, sp) # kernel entry point diff --git a/target/linux/generic/patches-4.1/302-mips_no_branch_likely.patch b/target/linux/generic/patches-4.1/302-mips_no_branch_likely.patch new file mode 100644 index 0000000..44c6b04 --- /dev/null +++ b/target/linux/generic/patches-4.1/302-mips_no_branch_likely.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -87,7 +87,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + # machines may also. Since BFD is incredibly buggy with respect to + # crossformat linking we rely on the elf2ecoff tool for format conversion. + # +-cflags-y += -G 0 -mno-abicalls -fno-pic -pipe ++cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely + cflags-y += -msoft-float + LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections + KBUILD_AFLAGS_MODULE += -mlong-calls diff --git a/target/linux/generic/patches-4.1/304-mips_disable_fpu.patch b/target/linux/generic/patches-4.1/304-mips_disable_fpu.patch new file mode 100644 index 0000000..7dc2ac9 --- /dev/null +++ b/target/linux/generic/patches-4.1/304-mips_disable_fpu.patch @@ -0,0 +1,106 @@ +From: Manuel Lauss +Subject: [RFC PATCH v4 2/2] MIPS: make FPU emulator optional +Date: Mon, 7 Apr 2014 12:57:04 +0200 +Message-Id: <1396868224-252888-2-git-send-email-manuel.lauss@gmail.com> + +This small patch makes the MIPS FPU emulator optional. The kernel +kills float-users on systems without a hardware FPU by sending a SIGILL. + +Disabling the emulator shrinks vmlinux by about 54kBytes (32bit, +optimizing for size). + +Signed-off-by: Manuel Lauss +--- +v4: rediffed because of patch 1/2, should now work with micromips as well +v3: updated patch description with size savings. +v2: incorporated changes suggested by Jonas Gorski + force the fpu emulator on for micromips: relocating the parts + of the mmips code in the emulator to other areas would be a + much larger change; I went the cheap route instead with this. + + arch/mips/Kbuild | 2 +- + arch/mips/Kconfig | 14 ++++++++++++++ + arch/mips/include/asm/fpu.h | 5 +++-- + arch/mips/include/asm/fpu_emulator.h | 15 +++++++++++++++ + 4 files changed, 33 insertions(+), 3 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2668,6 +2668,20 @@ config MIPS_O32_FP64_SUPPORT + + If unsure, say N. + ++config MIPS_FPU_EMULATOR ++ bool "MIPS FPU Emulator" ++ default y ++ help ++ This option lets you disable the built-in MIPS FPU (Coprocessor 1) ++ emulator, which handles floating-point instructions on processors ++ without a hardware FPU. It is generally a good idea to keep the ++ emulator built-in, unless you are perfectly sure you have a ++ complete soft-float environment. With the emulator disabled, all ++ users of float operations will be killed with an illegal instr- ++ uction exception. ++ ++ Say Y, please. ++ + config USE_OF + bool + select OF +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -292,7 +292,7 @@ OBJCOPYFLAGS += --remove-section=.regin + head-y := arch/mips/kernel/head.o + + libs-y += arch/mips/lib/ +-libs-y += arch/mips/math-emu/ ++libs-$(CONFIG_MIPS_FPU_EMULATOR) += arch/mips/math-emu/ + + # See arch/mips/Kbuild for content of core part of the kernel + core-y += arch/mips/ +--- a/arch/mips/include/asm/fpu.h ++++ b/arch/mips/include/asm/fpu.h +@@ -218,8 +218,10 @@ static inline int init_fpu(void) + /* Restore FRE */ + write_c0_config5(config5); + enable_fpu_hazard(); +- } else ++ } else if (IS_ENABLED(CONFIG_MIPS_FPU_EMULATOR)) + fpu_emulator_init_fpu(); ++ else ++ ret = SIGILL; + + return ret; + } +--- a/arch/mips/include/asm/fpu_emulator.h ++++ b/arch/mips/include/asm/fpu_emulator.h +@@ -30,6 +30,7 @@ + #include + #include + ++#ifdef CONFIG_MIPS_FPU_EMULATOR + #ifdef CONFIG_DEBUG_FS + + struct mips_fpu_emulator_stats { +@@ -66,6 +67,21 @@ extern int do_dsemulret(struct pt_regs * + extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, + struct mips_fpu_struct *ctx, int has_fpu, + void *__user *fault_addr); ++#else /* no CONFIG_MIPS_FPU_EMULATOR */ ++static inline int do_dsemulret(struct pt_regs *xcp) ++{ ++ return 0; /* 0 means error, should never get here anyway */ ++} ++ ++static inline int fpu_emulator_cop1Handler(struct pt_regs *xcp, ++ struct mips_fpu_struct *ctx, int has_fpu, ++ void *__user *fault_addr) ++{ ++ *fault_addr = NULL; ++ return SIGILL; /* we don't speak MIPS FPU */ ++} ++#endif /* CONFIG_MIPS_FPU_EMULATOR */ ++ + int process_fpemu_return(int sig, void __user *fault_addr, + unsigned long fcr31); + int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, diff --git a/target/linux/generic/patches-4.1/305-mips_module_reloc.patch b/target/linux/generic/patches-4.1/305-mips_module_reloc.patch new file mode 100644 index 0000000..8b3975f --- /dev/null +++ b/target/linux/generic/patches-4.1/305-mips_module_reloc.patch @@ -0,0 +1,352 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -90,8 +90,13 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely + cflags-y += -msoft-float + LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections ++ifdef CONFIG_64BIT + KBUILD_AFLAGS_MODULE += -mlong-calls + KBUILD_CFLAGS_MODULE += -mlong-calls ++else ++KBUILD_AFLAGS_MODULE += -mno-long-calls ++KBUILD_CFLAGS_MODULE += -mno-long-calls ++endif + + ifndef CONFIG_FUNCTION_TRACER + KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections +--- a/arch/mips/include/asm/module.h ++++ b/arch/mips/include/asm/module.h +@@ -11,6 +11,11 @@ struct mod_arch_specific { + const struct exception_table_entry *dbe_start; + const struct exception_table_entry *dbe_end; + struct mips_hi16 *r_mips_hi16_list; ++ ++ void *phys_plt_tbl; ++ void *virt_plt_tbl; ++ unsigned int phys_plt_offset; ++ unsigned int virt_plt_offset; + }; + + typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ +--- a/arch/mips/kernel/module.c ++++ b/arch/mips/kernel/module.c +@@ -43,14 +43,221 @@ struct mips_hi16 { + static LIST_HEAD(dbe_list); + static DEFINE_SPINLOCK(dbe_lock); + +-#ifdef MODULE_START ++/* ++ * Get the potential max trampolines size required of the init and ++ * non-init sections. Only used if we cannot find enough contiguous ++ * physically mapped memory to put the module into. ++ */ ++static unsigned int ++get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, ++ const char *secstrings, unsigned int symindex, bool is_init) ++{ ++ unsigned long ret = 0; ++ unsigned int i, j; ++ Elf_Sym *syms; ++ ++ /* Everything marked ALLOC (this includes the exported symbols) */ ++ for (i = 1; i < hdr->e_shnum; ++i) { ++ unsigned int info = sechdrs[i].sh_info; ++ ++ if (sechdrs[i].sh_type != SHT_REL ++ && sechdrs[i].sh_type != SHT_RELA) ++ continue; ++ ++ /* Not a valid relocation section? */ ++ if (info >= hdr->e_shnum) ++ continue; ++ ++ /* Don't bother with non-allocated sections */ ++ if (!(sechdrs[info].sh_flags & SHF_ALLOC)) ++ continue; ++ ++ /* If it's called *.init*, and we're not init, we're ++ not interested */ ++ if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0) ++ != is_init) ++ continue; ++ ++ syms = (Elf_Sym *) sechdrs[symindex].sh_addr; ++ if (sechdrs[i].sh_type == SHT_REL) { ++ Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr; ++ unsigned int size = sechdrs[i].sh_size / sizeof(*rel); ++ ++ for (j = 0; j < size; ++j) { ++ Elf_Sym *sym; ++ ++ if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26) ++ continue; ++ ++ sym = syms + ELF_MIPS_R_SYM(rel[j]); ++ if (!is_init && sym->st_shndx != SHN_UNDEF) ++ continue; ++ ++ ret += 4 * sizeof(int); ++ } ++ } else { ++ Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr; ++ unsigned int size = sechdrs[i].sh_size / sizeof(*rela); ++ ++ for (j = 0; j < size; ++j) { ++ Elf_Sym *sym; ++ ++ if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26) ++ continue; ++ ++ sym = syms + ELF_MIPS_R_SYM(rela[j]); ++ if (!is_init && sym->st_shndx != SHN_UNDEF) ++ continue; ++ ++ ret += 4 * sizeof(int); ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++#ifndef MODULE_START ++static void *alloc_phys(unsigned long size) ++{ ++ unsigned order; ++ struct page *page; ++ struct page *p; ++ ++ size = PAGE_ALIGN(size); ++ order = get_order(size); ++ ++ page = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN | ++ __GFP_THISNODE, order); ++ if (!page) ++ return NULL; ++ ++ split_page(page, order); ++ ++ /* mark all pages except for the last one */ ++ for (p = page; p + 1 < page + (size >> PAGE_SHIFT); ++p) ++ set_bit(PG_owner_priv_1, &p->flags); ++ ++ for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p) ++ __free_page(p); ++ ++ return page_address(page); ++} ++#endif ++ ++static void free_phys(void *ptr) ++{ ++ struct page *page; ++ bool free; ++ ++ page = virt_to_page(ptr); ++ do { ++ free = test_and_clear_bit(PG_owner_priv_1, &page->flags); ++ __free_page(page); ++ page++; ++ } while (free); ++} ++ ++ + void *module_alloc(unsigned long size) + { ++#ifdef MODULE_START + return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, + GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, + __builtin_return_address(0)); ++#else ++ void *ptr; ++ ++ if (size == 0) ++ return NULL; ++ ++ ptr = alloc_phys(size); ++ ++ /* If we failed to allocate physically contiguous memory, ++ * fall back to regular vmalloc. The module loader code will ++ * create jump tables to handle long jumps */ ++ if (!ptr) ++ return vmalloc(size); ++ ++ return ptr; ++#endif + } ++ ++static inline bool is_phys_addr(void *ptr) ++{ ++#ifdef CONFIG_64BIT ++ return (KSEGX((unsigned long)ptr) == CKSEG0); ++#else ++ return (KSEGX(ptr) == KSEG0); + #endif ++} ++ ++/* Free memory returned from module_alloc */ ++void module_memfree(void *module_region) ++{ ++ if (is_phys_addr(module_region)) ++ free_phys(module_region); ++ else ++ vfree(module_region); ++} ++ ++static void *__module_alloc(int size, bool phys) ++{ ++ void *ptr; ++ ++ if (phys) ++ ptr = kmalloc(size, GFP_KERNEL); ++ else ++ ptr = vmalloc(size); ++ return ptr; ++} ++ ++static void __module_free(void *ptr) ++{ ++ if (is_phys_addr(ptr)) ++ kfree(ptr); ++ else ++ vfree(ptr); ++} ++ ++int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, ++ char *secstrings, struct module *mod) ++{ ++ unsigned int symindex = 0; ++ unsigned int core_size, init_size; ++ int i; ++ ++ mod->arch.phys_plt_offset = 0; ++ mod->arch.virt_plt_offset = 0; ++ mod->arch.phys_plt_tbl = NULL; ++ mod->arch.virt_plt_tbl = NULL; ++ ++ if (IS_ENABLED(CONFIG_64BIT)) ++ return 0; ++ ++ for (i = 1; i < hdr->e_shnum; i++) ++ if (sechdrs[i].sh_type == SHT_SYMTAB) ++ symindex = i; ++ ++ core_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false); ++ init_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true); ++ ++ if ((core_size + init_size) == 0) ++ return 0; ++ ++ mod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1); ++ if (!mod->arch.phys_plt_tbl) ++ return -ENOMEM; ++ ++ mod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0); ++ if (!mod->arch.virt_plt_tbl) { ++ __module_free(mod->arch.phys_plt_tbl); ++ mod->arch.phys_plt_tbl = NULL; ++ return -ENOMEM; ++ } ++ ++ return 0; ++} + + int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v) + { +@@ -64,8 +271,39 @@ static int apply_r_mips_32_rel(struct mo + return 0; + } + ++static Elf_Addr add_plt_entry_to(unsigned *plt_offset, ++ void *start, Elf_Addr v) ++{ ++ unsigned *tramp = start + *plt_offset; ++ *plt_offset += 4 * sizeof(int); ++ ++ /* adjust carry for addiu */ ++ if (v & 0x00008000) ++ v += 0x10000; ++ ++ tramp[0] = 0x3c190000 | (v >> 16); /* lui t9, hi16 */ ++ tramp[1] = 0x27390000 | (v & 0xffff); /* addiu t9, t9, lo16 */ ++ tramp[2] = 0x03200008; /* jr t9 */ ++ tramp[3] = 0x00000000; /* nop */ ++ ++ return (Elf_Addr) tramp; ++} ++ ++static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v) ++{ ++ if (is_phys_addr(location)) ++ return add_plt_entry_to(&me->arch.phys_plt_offset, ++ me->arch.phys_plt_tbl, v); ++ else ++ return add_plt_entry_to(&me->arch.virt_plt_offset, ++ me->arch.virt_plt_tbl, v); ++ ++} ++ + static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v) + { ++ u32 ofs = *location & 0x03ffffff; ++ + if (v % 4) { + pr_err("module %s: dangerous R_MIPS_26 REL relocation\n", + me->name); +@@ -73,14 +311,17 @@ static int apply_r_mips_26_rel(struct mo + } + + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { +- printk(KERN_ERR +- "module %s: relocation overflow\n", +- me->name); +- return -ENOEXEC; ++ v = add_plt_entry(me, location, v + (ofs << 2)); ++ if (!v) { ++ printk(KERN_ERR ++ "module %s: relocation overflow\n", me->name); ++ return -ENOEXEC; ++ } ++ ofs = 0; + } + + *location = (*location & ~0x03ffffff) | +- ((*location + (v >> 2)) & 0x03ffffff); ++ ((ofs + (v >> 2)) & 0x03ffffff); + + return 0; + } +@@ -287,9 +528,33 @@ int module_finalize(const Elf_Ehdr *hdr, + list_add(&me->arch.dbe_list, &dbe_list); + spin_unlock_irq(&dbe_lock); + } ++ ++ /* Get rid of the fixup trampoline if we're running the module ++ * from physically mapped address space */ ++ if (me->arch.phys_plt_offset == 0) { ++ __module_free(me->arch.phys_plt_tbl); ++ me->arch.phys_plt_tbl = NULL; ++ } ++ if (me->arch.virt_plt_offset == 0) { ++ __module_free(me->arch.virt_plt_tbl); ++ me->arch.virt_plt_tbl = NULL; ++ } ++ + return 0; + } + ++void module_arch_freeing_init(struct module *mod) ++{ ++ if (mod->arch.phys_plt_tbl) { ++ __module_free(mod->arch.phys_plt_tbl); ++ mod->arch.phys_plt_tbl = NULL; ++ } ++ if (mod->arch.virt_plt_tbl) { ++ __module_free(mod->arch.virt_plt_tbl); ++ mod->arch.virt_plt_tbl = NULL; ++ } ++} ++ + void module_arch_cleanup(struct module *mod) + { + spin_lock_irq(&dbe_lock); diff --git a/target/linux/generic/patches-4.1/306-mips_mem_functions_performance.patch b/target/linux/generic/patches-4.1/306-mips_mem_functions_performance.patch new file mode 100644 index 0000000..9818677 --- /dev/null +++ b/target/linux/generic/patches-4.1/306-mips_mem_functions_performance.patch @@ -0,0 +1,83 @@ +--- a/arch/mips/include/asm/string.h ++++ b/arch/mips/include/asm/string.h +@@ -133,11 +133,44 @@ strncmp(__const__ char *__cs, __const__ + + #define __HAVE_ARCH_MEMSET + extern void *memset(void *__s, int __c, size_t __count); ++#define memset(__s, __c, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memset((__s), (__c), __len); \ ++ else \ ++ __ret = __builtin_memset((__s), (__c), __len); \ ++ __ret; \ ++}) + + #define __HAVE_ARCH_MEMCPY + extern void *memcpy(void *__to, __const__ void *__from, size_t __n); ++#define memcpy(dst, src, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memcpy((dst), (src), __len); \ ++ else \ ++ __ret = __builtin_memcpy((dst), (src), __len); \ ++ __ret; \ ++}) + + #define __HAVE_ARCH_MEMMOVE + extern void *memmove(void *__dest, __const__ void *__src, size_t __n); ++#define memmove(dst, src, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memmove((dst), (src), __len); \ ++ else \ ++ __ret = __builtin_memmove((dst), (src), __len); \ ++ __ret; \ ++}) ++ ++#define __HAVE_ARCH_MEMCMP ++#define memcmp(src1, src2, len) __builtin_memcmp((src1), (src2), (len)) + + #endif /* _ASM_STRING_H */ +--- a/arch/mips/lib/Makefile ++++ b/arch/mips/lib/Makefile +@@ -4,7 +4,7 @@ + + lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ + mips-atomic.o strlen_user.o strncpy_user.o \ +- strnlen_user.o uncached.o ++ strnlen_user.o uncached.o memcmp.o + + obj-y += iomap.o + obj-$(CONFIG_PCI) += iomap-pci.o +--- /dev/null ++++ b/arch/mips/lib/memcmp.c +@@ -0,0 +1,22 @@ ++/* ++ * copied from linux/lib/string.c ++ * ++ * Copyright (C) 1991, 1992 Linus Torvalds ++ */ ++ ++#include ++#include ++ ++#undef memcmp ++int memcmp(const void *cs, const void *ct, size_t count) ++{ ++ const unsigned char *su1, *su2; ++ int res = 0; ++ ++ for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) ++ if ((res = *su1 - *su2) != 0) ++ break; ++ return res; ++} ++EXPORT_SYMBOL(memcmp); ++ diff --git a/target/linux/generic/patches-4.1/307-mips_highmem_offset.patch b/target/linux/generic/patches-4.1/307-mips_highmem_offset.patch new file mode 100644 index 0000000..c9f0c84 --- /dev/null +++ b/target/linux/generic/patches-4.1/307-mips_highmem_offset.patch @@ -0,0 +1,17 @@ +Adjust highmem offset to 0x10000000 to ensure that all kmalloc allocations +stay within the same 256M boundary. This ensures that -mlong-calls is not +needed on systems with more than 256M RAM. + +Signed-off-by: Felix Fietkau +--- +--- a/arch/mips/include/asm/mach-generic/spaces.h ++++ b/arch/mips/include/asm/mach-generic/spaces.h +@@ -44,7 +44,7 @@ + * Memory above this physical address will be considered highmem. + */ + #ifndef HIGHMEM_START +-#define HIGHMEM_START _AC(0x20000000, UL) ++#define HIGHMEM_START _AC(0x10000000, UL) + #endif + + #endif /* CONFIG_32BIT */ diff --git a/target/linux/generic/patches-4.1/309-mips_fuse_workaround.patch b/target/linux/generic/patches-4.1/309-mips_fuse_workaround.patch new file mode 100644 index 0000000..7a3aa34 --- /dev/null +++ b/target/linux/generic/patches-4.1/309-mips_fuse_workaround.patch @@ -0,0 +1,32 @@ +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -38,6 +38,7 @@ void (*__flush_cache_vunmap)(void); + + void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size); + EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); ++EXPORT_SYMBOL(__flush_cache_all); + void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size); + + /* MIPS specific cache operations */ +--- a/fs/fuse/dev.c ++++ b/fs/fuse/dev.c +@@ -19,6 +19,9 @@ + #include + #include + #include ++#ifdef CONFIG_MIPS ++#include ++#endif + + MODULE_ALIAS_MISCDEV(FUSE_MINOR); + MODULE_ALIAS("devname:fuse"); +@@ -816,6 +819,9 @@ static int fuse_copy_fill(struct fuse_co + static int fuse_copy_do(struct fuse_copy_state *cs, void **val, unsigned *size) + { + unsigned ncpy = min(*size, cs->len); ++#ifdef CONFIG_MIPS ++ __flush_cache_all(); ++#endif + if (val) { + void *pgaddr = kmap_atomic(cs->pg); + void *buf = pgaddr + cs->offset; diff --git a/target/linux/generic/patches-4.1/310-arm_module_unresolved_weak_sym.patch b/target/linux/generic/patches-4.1/310-arm_module_unresolved_weak_sym.patch new file mode 100644 index 0000000..9210c1d --- /dev/null +++ b/target/linux/generic/patches-4.1/310-arm_module_unresolved_weak_sym.patch @@ -0,0 +1,13 @@ +--- a/arch/arm/kernel/module.c ++++ b/arch/arm/kernel/module.c +@@ -83,6 +83,10 @@ apply_relocate(Elf32_Shdr *sechdrs, cons + return -ENOEXEC; + } + ++ if ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) && ++ ELF_ST_BIND(sym->st_info) == STB_WEAK) ++ continue; ++ + loc = dstsec->sh_addr + rel->r_offset; + + switch (ELF32_R_TYPE(rel->r_info)) { diff --git a/target/linux/generic/patches-4.1/320-ppc4xx_optimization.patch b/target/linux/generic/patches-4.1/320-ppc4xx_optimization.patch new file mode 100644 index 0000000..7ea4479 --- /dev/null +++ b/target/linux/generic/patches-4.1/320-ppc4xx_optimization.patch @@ -0,0 +1,31 @@ +Upstream doesn't optimize the kernel and bootwrappers for ppc44x because +they still want to support gcc 3.3 -- well, we don't. + +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -203,7 +203,8 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) + KBUILD_CFLAGS += -mno-sched-epilog + endif + +-cpu-as-$(CONFIG_4xx) += -Wa,-m405 ++cpu-as-$(CONFIG_40x) += -Wa,-m405 ++cpu-as-$(CONFIG_44x) += -Wa,-m440 + cpu-as-$(CONFIG_ALTIVEC) += -Wa,-maltivec + cpu-as-$(CONFIG_E200) += -Wa,-me200 + +--- a/arch/powerpc/boot/Makefile ++++ b/arch/powerpc/boot/Makefile +@@ -48,10 +48,10 @@ BOOTCFLAGS += -I$(obj) -I$(srctree)/$(ob + DTC_FLAGS ?= -p 1024 + + $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 ++$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440 + $(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 ++$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=440 ++$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440 + $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 + $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 + $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405 diff --git a/target/linux/generic/patches-4.1/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/patches-4.1/321-powerpc_crtsavres_prereq.patch new file mode 100644 index 0000000..ab6ea7b --- /dev/null +++ b/target/linux/generic/patches-4.1/321-powerpc_crtsavres_prereq.patch @@ -0,0 +1,10 @@ +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -165,7 +165,6 @@ CPP = $(CC) -E $(KBUILD_CFLAGS) + + CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__ + +-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o + + ifeq ($(CONFIG_476FPE_ERR46),y) + KBUILD_LDFLAGS_MODULE += --ppc476-workaround \ diff --git a/target/linux/generic/patches-4.1/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch b/target/linux/generic/patches-4.1/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch new file mode 100644 index 0000000..a69d197 --- /dev/null +++ b/target/linux/generic/patches-4.1/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch @@ -0,0 +1,298 @@ +From d8582dcf1ed66eee88a11e4760f42c0d6c8822be Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 31 Jan 2015 22:26:03 +0800 +Subject: [PATCH 331/331] MIPS: kexec: Accept command line parameters from + userspace. + +Signed-off-by: Yousong Zhou +--- + arch/mips/kernel/machine_kexec.c | 153 +++++++++++++++++++++++++++++++----- + arch/mips/kernel/machine_kexec.h | 20 +++++ + arch/mips/kernel/relocate_kernel.S | 21 +++-- + 3 files changed, 167 insertions(+), 27 deletions(-) + create mode 100644 arch/mips/kernel/machine_kexec.h + +--- a/arch/mips/kernel/machine_kexec.c ++++ b/arch/mips/kernel/machine_kexec.c +@@ -10,45 +10,145 @@ + #include + #include + ++#include + #include + #include +- +-extern const unsigned char relocate_new_kernel[]; +-extern const size_t relocate_new_kernel_size; +- +-extern unsigned long kexec_start_address; +-extern unsigned long kexec_indirection_page; ++#include ++#include "machine_kexec.h" + + int (*_machine_kexec_prepare)(struct kimage *) = NULL; + void (*_machine_kexec_shutdown)(void) = NULL; + void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL; ++ + #ifdef CONFIG_SMP + void (*relocated_kexec_smp_wait) (void *); + atomic_t kexec_ready_to_reboot = ATOMIC_INIT(0); + #endif + +-int +-machine_kexec_prepare(struct kimage *kimage) ++static void machine_kexec_print_args(void) + { ++ unsigned long argc = (int)kexec_args[0]; ++ int i; ++ ++ pr_info("kexec_args[0] (argc): %lu\n", argc); ++ pr_info("kexec_args[1] (argv): %p\n", (void *)kexec_args[1]); ++ pr_info("kexec_args[2] (env ): %p\n", (void *)kexec_args[2]); ++ pr_info("kexec_args[3] (desc): %p\n", (void *)kexec_args[3]); ++ ++ for (i = 0; i < argc; i++) { ++ pr_info("kexec_argv[%d] = %p, %s\n", ++ i, kexec_argv[i], kexec_argv[i]); ++ } ++} ++ ++static void machine_kexec_init_argv(struct kimage *image) ++{ ++ void __user *buf = NULL; ++ size_t bufsz; ++ size_t size; ++ int i; ++ ++ bufsz = 0; ++ for (i = 0; i < image->nr_segments; i++) { ++ struct kexec_segment *seg; ++ ++ seg = &image->segment[i]; ++ if (seg->bufsz < 6) ++ continue; ++ ++ if (strncmp((char *) seg->buf, "kexec ", 6)) ++ continue; ++ ++ buf = seg->buf; ++ bufsz = seg->bufsz; ++ break; ++ } ++ ++ if (!buf) ++ return; ++ ++ size = KEXEC_COMMAND_LINE_SIZE; ++ size = min(size, bufsz); ++ if (size < bufsz) ++ pr_warn("kexec command line truncated to %zd bytes\n", size); ++ ++ /* Copy to kernel space */ ++ copy_from_user(kexec_argv_buf, buf, size); ++ kexec_argv_buf[size - 1] = 0; ++} ++ ++static void machine_kexec_parse_argv(struct kimage *image) ++{ ++ char *reboot_code_buffer; ++ int reloc_delta; ++ char *ptr; ++ int argc; ++ int i; ++ ++ ptr = kexec_argv_buf; ++ argc = 0; ++ ++ /* ++ * convert command line string to array of parameters ++ * (as bootloader does). ++ */ ++ while (ptr && *ptr && (KEXEC_MAX_ARGC > argc)) { ++ if (*ptr == ' ') { ++ *ptr++ = '\0'; ++ continue; ++ } ++ ++ kexec_argv[argc++] = ptr; ++ ptr = strchr(ptr, ' '); ++ } ++ ++ if (!argc) ++ return; ++ ++ kexec_args[0] = argc; ++ kexec_args[1] = (unsigned long)kexec_argv; ++ kexec_args[2] = 0; ++ kexec_args[3] = 0; ++ ++ reboot_code_buffer = page_address(image->control_code_page); ++ reloc_delta = reboot_code_buffer - (char *)kexec_relocate_new_kernel; ++ ++ kexec_args[1] += reloc_delta; ++ for (i = 0; i < argc; i++) ++ kexec_argv[i] += reloc_delta; ++} ++ ++int machine_kexec_prepare(struct kimage *kimage) ++{ ++ /* ++ * Whenever arguments passed from kexec-tools, Init the arguments as ++ * the original ones to try avoiding booting failure. ++ */ ++ ++ kexec_args[0] = fw_arg0; ++ kexec_args[1] = fw_arg1; ++ kexec_args[2] = fw_arg2; ++ kexec_args[3] = fw_arg3; ++ ++ machine_kexec_init_argv(kimage); ++ machine_kexec_parse_argv(kimage); ++ + if (_machine_kexec_prepare) + return _machine_kexec_prepare(kimage); + return 0; + } + +-void +-machine_kexec_cleanup(struct kimage *kimage) ++void machine_kexec_cleanup(struct kimage *kimage) + { + } + +-void +-machine_shutdown(void) ++void machine_shutdown(void) + { + if (_machine_kexec_shutdown) + _machine_kexec_shutdown(); + } + +-void +-machine_crash_shutdown(struct pt_regs *regs) ++void machine_crash_shutdown(struct pt_regs *regs) + { + if (_machine_crash_shutdown) + _machine_crash_shutdown(regs); +@@ -66,10 +166,12 @@ machine_kexec(struct kimage *image) + unsigned long *ptr; + + reboot_code_buffer = +- (unsigned long)page_address(image->control_code_page); ++ (unsigned long)page_address(image->control_code_page); ++ pr_info("reboot_code_buffer = %p\n", (void *)reboot_code_buffer); + + kexec_start_address = + (unsigned long) phys_to_virt(image->start); ++ pr_info("kexec_start_address = %p\n", (void *)kexec_start_address); + + if (image->type == KEXEC_TYPE_DEFAULT) { + kexec_indirection_page = +@@ -77,9 +179,19 @@ machine_kexec(struct kimage *image) + } else { + kexec_indirection_page = (unsigned long)&image->head; + } ++ pr_info("kexec_indirection_page = %p\n", (void *)kexec_indirection_page); + +- memcpy((void*)reboot_code_buffer, relocate_new_kernel, +- relocate_new_kernel_size); ++ pr_info("Where is memcpy: %p\n", memcpy); ++ pr_info("kexec_relocate_new_kernel = %p, kexec_relocate_new_kernel_end = %p\n", ++ (void *)kexec_relocate_new_kernel, &kexec_relocate_new_kernel_end); ++ pr_info("Copy %lu bytes from %p to %p\n", KEXEC_RELOCATE_NEW_KERNEL_SIZE, ++ (void *)kexec_relocate_new_kernel, (void *)reboot_code_buffer); ++ memcpy((void*)reboot_code_buffer, kexec_relocate_new_kernel, ++ KEXEC_RELOCATE_NEW_KERNEL_SIZE); ++ ++ pr_info("Before _print_args().\n"); ++ machine_kexec_print_args(); ++ pr_info("Before eval loop.\n"); + + /* + * The generic kexec code builds a page list with physical +@@ -98,15 +210,16 @@ machine_kexec(struct kimage *image) + /* + * we do not want to be bothered. + */ ++ pr_info("Before irq_disable.\n"); + local_irq_disable(); + +- printk("Will call new kernel at %08lx\n", image->start); +- printk("Bye ...\n"); ++ pr_info("Will call new kernel at %08lx\n", image->start); ++ pr_info("Bye ...\n"); + __flush_cache_all(); + #ifdef CONFIG_SMP + /* All secondary cpus now may jump to kexec_wait cycle */ + relocated_kexec_smp_wait = reboot_code_buffer + +- (void *)(kexec_smp_wait - relocate_new_kernel); ++ (void *)(kexec_smp_wait - kexec_relocate_new_kernel); + smp_wmb(); + atomic_set(&kexec_ready_to_reboot, 1); + #endif +--- /dev/null ++++ b/arch/mips/kernel/machine_kexec.h +@@ -0,0 +1,20 @@ ++#ifndef _MACHINE_KEXEC_H ++#define _MACHINE_KEXEC_H ++ ++#ifndef __ASSEMBLY__ ++extern const unsigned char kexec_relocate_new_kernel[]; ++extern unsigned long kexec_relocate_new_kernel_end; ++extern unsigned long kexec_start_address; ++extern unsigned long kexec_indirection_page; ++ ++extern char kexec_argv_buf[]; ++extern char *kexec_argv[]; ++ ++#define KEXEC_RELOCATE_NEW_KERNEL_SIZE ((unsigned long)&kexec_relocate_new_kernel_end - (unsigned long)kexec_relocate_new_kernel) ++#endif /* !__ASSEMBLY__ */ ++ ++#define KEXEC_COMMAND_LINE_SIZE 256 ++#define KEXEC_ARGV_SIZE (KEXEC_COMMAND_LINE_SIZE / 16) ++#define KEXEC_MAX_ARGC (KEXEC_ARGV_SIZE / sizeof(long)) ++ ++#endif +--- a/arch/mips/kernel/relocate_kernel.S ++++ b/arch/mips/kernel/relocate_kernel.S +@@ -12,8 +12,9 @@ + #include + #include + #include ++#include "machine_kexec.h" + +-LEAF(relocate_new_kernel) ++LEAF(kexec_relocate_new_kernel) + PTR_L a0, arg0 + PTR_L a1, arg1 + PTR_L a2, arg2 +@@ -98,7 +99,7 @@ done: + #endif + /* jump to kexec_start_address */ + j s1 +- END(relocate_new_kernel) ++ END(kexec_relocate_new_kernel) + + #ifdef CONFIG_SMP + /* +@@ -184,9 +185,15 @@ kexec_indirection_page: + PTR 0 + .size kexec_indirection_page, PTRSIZE + +-relocate_new_kernel_end: ++kexec_argv_buf: ++ EXPORT(kexec_argv_buf) ++ .skip KEXEC_COMMAND_LINE_SIZE ++ .size kexec_argv_buf, KEXEC_COMMAND_LINE_SIZE ++ ++kexec_argv: ++ EXPORT(kexec_argv) ++ .skip KEXEC_ARGV_SIZE ++ .size kexec_argv, KEXEC_ARGV_SIZE + +-relocate_new_kernel_size: +- EXPORT(relocate_new_kernel_size) +- PTR relocate_new_kernel_end - relocate_new_kernel +- .size relocate_new_kernel_size, PTRSIZE ++kexec_relocate_new_kernel_end: ++ EXPORT(kexec_relocate_new_kernel_end) diff --git a/target/linux/generic/patches-4.1/400-mtd-add-rootfs-split-support.patch b/target/linux/generic/patches-4.1/400-mtd-add-rootfs-split-support.patch new file mode 100644 index 0000000..ba64e09 --- /dev/null +++ b/target/linux/generic/patches-4.1/400-mtd-add-rootfs-split-support.patch @@ -0,0 +1,146 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -12,6 +12,23 @@ menuconfig MTD + + if MTD + ++menu "OpenWrt specific MTD options" ++ ++config MTD_ROOTFS_ROOT_DEV ++ bool "Automatically set 'rootfs' partition to be root filesystem" ++ default y ++ ++config MTD_SPLIT_FIRMWARE ++ bool "Automatically split firmware partition for kernel+rootfs" ++ default y ++ ++config MTD_SPLIT_FIRMWARE_NAME ++ string "Firmware partition name" ++ depends on MTD_SPLIT_FIRMWARE ++ default "firmware" ++ ++endmenu ++ + config MTD_TESTS + tristate "MTD tests support (DANGEROUS)" + depends on m +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -29,11 +29,13 @@ + #include + #include + #include ++#include + #include + #include + #include + + #include "mtdcore.h" ++#include "mtdsplit/mtdsplit.h" + + /* Our partition linked list */ + static LIST_HEAD(mtd_partitions); +@@ -47,13 +49,14 @@ struct mtd_part { + struct list_head list; + }; + ++static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part); ++ + /* + * Given a pointer to the MTD object in the mtd_part structure, we can retrieve + * the pointer to that structure with this macro. + */ + #define PART(x) ((struct mtd_part *)(x)) + +- + /* + * MTD methods which simply translate the effective address and pass through + * to the _real_ device. +@@ -579,8 +582,10 @@ static int mtd_add_partition_attrs(struc + return ret; + } + +-int mtd_add_partition(struct mtd_info *master, const char *name, +- long long offset, long long length) ++ ++static int ++__mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length, bool dup_check) + { + struct mtd_partition part; + struct mtd_part *new; +@@ -612,6 +617,7 @@ int mtd_add_partition(struct mtd_info *m + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&new->mtd); ++ mtd_partition_split(master, new); + + mtd_add_partition_attrs(new); + +@@ -619,6 +625,12 @@ int mtd_add_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_add_partition); + ++int mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length) ++{ ++ return __mtd_add_partition(master, name, offset, length, true); ++} ++ + int mtd_del_partition(struct mtd_info *master, int partno) + { + struct mtd_part *slave, *next; +@@ -644,6 +656,35 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME ++#define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME ++#else ++#define SPLIT_FIRMWARE_NAME "unused" ++#endif ++ ++static void split_firmware(struct mtd_info *master, struct mtd_part *part) ++{ ++} ++ ++void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++} ++ ++static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part) ++{ ++ static int rootfs_found = 0; ++ ++ if (rootfs_found) ++ return; ++ ++ if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && ++ config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) ++ split_firmware(master, part); ++ ++ arch_split_mtd_part(master, part->mtd.name, part->offset, ++ part->mtd.size); ++} + /* + * This function, given a master MTD object and a partition table, creates + * and registers slave MTD objects which are bound to the master according to +@@ -673,6 +714,7 @@ int add_mtd_partitions(struct mtd_info * + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&slave->mtd); ++ mtd_partition_split(master, slave); + mtd_add_partition_attrs(slave); + + cur_offset = slave->offset + slave->mtd.size; +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -84,5 +84,7 @@ int mtd_add_partition(struct mtd_info *m + long long offset, long long length); + int mtd_del_partition(struct mtd_info *master, int partno); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); ++extern void __weak arch_split_mtd_part(struct mtd_info *master, ++ const char *name, int offset, int size); + + #endif diff --git a/target/linux/generic/patches-4.1/401-mtd-add-support-for-different-partition-parser-types.patch b/target/linux/generic/patches-4.1/401-mtd-add-support-for-different-partition-parser-types.patch new file mode 100644 index 0000000..31dee98 --- /dev/null +++ b/target/linux/generic/patches-4.1/401-mtd-add-support-for-different-partition-parser-types.patch @@ -0,0 +1,113 @@ +From 02cff0ccaa6d364f5c1eeea83f47ac80ccc967d4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 3 Sep 2013 18:11:50 +0200 +Subject: [PATCH] mtd: add support for different partition parser types + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/mtdpart.c | 56 ++++++++++++++++++++++++++++++++++++++++ + include/linux/mtd/partitions.h | 11 ++++++++ + 2 files changed, 67 insertions(+) + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -745,6 +745,30 @@ static struct mtd_part_parser *get_parti + + #define put_partition_parser(p) do { module_put((p)->owner); } while (0) + ++static struct mtd_part_parser * ++get_partition_parser_by_type(enum mtd_parser_type type, ++ struct mtd_part_parser *start) ++{ ++ struct mtd_part_parser *p, *ret = NULL; ++ ++ spin_lock(&part_parser_lock); ++ ++ p = list_prepare_entry(start, &part_parsers, list); ++ if (start) ++ put_partition_parser(start); ++ ++ list_for_each_entry_continue(p, &part_parsers, list) { ++ if (p->type == type && try_module_get(p->owner)) { ++ ret = p; ++ break; ++ } ++ } ++ ++ spin_unlock(&part_parser_lock); ++ ++ return ret; ++} ++ + void register_mtd_parser(struct mtd_part_parser *p) + { + spin_lock(&part_parser_lock); +@@ -860,6 +884,38 @@ int parse_mtd_partitions(struct mtd_info + return ret; + } + ++int parse_mtd_partitions_by_type(struct mtd_info *master, ++ enum mtd_parser_type type, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct mtd_part_parser *prev = NULL; ++ int ret = 0; ++ ++ while (1) { ++ struct mtd_part_parser *parser; ++ ++ parser = get_partition_parser_by_type(type, prev); ++ if (!parser) ++ break; ++ ++ ret = (*parser->parse_fn)(master, pparts, data); ++ ++ if (ret > 0) { ++ put_partition_parser(parser); ++ printk(KERN_NOTICE ++ "%d %s partitions found on MTD device %s\n", ++ ret, parser->name, master->name); ++ break; ++ } ++ ++ prev = parser; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(parse_mtd_partitions_by_type); ++ + int mtd_is_partition(const struct mtd_info *mtd) + { + struct mtd_part *part; +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -68,12 +68,17 @@ struct mtd_part_parser_data { + * Functions dealing with the various ways of partitioning the space + */ + ++enum mtd_parser_type { ++ MTD_PARSER_TYPE_DEVICE = 0, ++}; ++ + struct mtd_part_parser { + struct list_head list; + struct module *owner; + const char *name; + int (*parse_fn)(struct mtd_info *, struct mtd_partition **, + struct mtd_part_parser_data *); ++ enum mtd_parser_type type; + }; + + extern void register_mtd_parser(struct mtd_part_parser *parser); +@@ -87,4 +92,9 @@ uint64_t mtd_get_device_size(const struc + extern void __weak arch_split_mtd_part(struct mtd_info *master, + const char *name, int offset, int size); + ++int parse_mtd_partitions_by_type(struct mtd_info *master, ++ enum mtd_parser_type type, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data); ++ + #endif diff --git a/target/linux/generic/patches-4.1/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch b/target/linux/generic/patches-4.1/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch new file mode 100644 index 0000000..725dbe8 --- /dev/null +++ b/target/linux/generic/patches-4.1/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch @@ -0,0 +1,72 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -656,6 +656,37 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++static int ++run_parsers_by_type(struct mtd_part *slave, enum mtd_parser_type type) ++{ ++ struct mtd_partition *parts; ++ int nr_parts; ++ int i; ++ ++ nr_parts = parse_mtd_partitions_by_type(&slave->mtd, type, &parts, ++ NULL); ++ if (nr_parts <= 0) ++ return nr_parts; ++ ++ if (WARN_ON(!parts)) ++ return 0; ++ ++ for (i = 0; i < nr_parts; i++) { ++ /* adjust partition offsets */ ++ parts[i].offset += slave->offset; ++ ++ __mtd_add_partition(slave->master, ++ parts[i].name, ++ parts[i].offset, ++ parts[i].size, ++ false); ++ } ++ ++ kfree(parts); ++ ++ return nr_parts; ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -664,6 +695,7 @@ EXPORT_SYMBOL_GPL(mtd_del_partition); + + static void split_firmware(struct mtd_info *master, struct mtd_part *part) + { ++ run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); + } + + void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, +@@ -678,6 +710,12 @@ static void mtd_partition_split(struct m + if (rootfs_found) + return; + ++ if (!strcmp(part->mtd.name, "rootfs")) { ++ run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); ++ ++ rootfs_found = 1; ++ } ++ + if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && + config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) + split_firmware(master, part); +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -70,6 +70,8 @@ struct mtd_part_parser_data { + + enum mtd_parser_type { + MTD_PARSER_TYPE_DEVICE = 0, ++ MTD_PARSER_TYPE_ROOTFS, ++ MTD_PARSER_TYPE_FIRMWARE, + }; + + struct mtd_part_parser { diff --git a/target/linux/generic/patches-4.1/403-mtd-hook-mtdsplit-to-Kbuild.patch b/target/linux/generic/patches-4.1/403-mtd-hook-mtdsplit-to-Kbuild.patch new file mode 100644 index 0000000..0cf1c38 --- /dev/null +++ b/target/linux/generic/patches-4.1/403-mtd-hook-mtdsplit-to-Kbuild.patch @@ -0,0 +1,22 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -27,6 +27,8 @@ config MTD_SPLIT_FIRMWARE_NAME + depends on MTD_SPLIT_FIRMWARE + default "firmware" + ++source "drivers/mtd/mtdsplit/Kconfig" ++ + endmenu + + config MTD_TESTS +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -6,6 +6,8 @@ + obj-$(CONFIG_MTD) += mtd.o + mtd-y := mtdcore.o mtdsuper.o mtdconcat.o mtdpart.o mtdchar.o + ++obj-$(CONFIG_MTD_SPLIT) += mtdsplit/ ++ + obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o diff --git a/target/linux/generic/patches-4.1/404-mtd-add-more-helper-functions.patch b/target/linux/generic/patches-4.1/404-mtd-add-more-helper-functions.patch new file mode 100644 index 0000000..42e5cfd --- /dev/null +++ b/target/linux/generic/patches-4.1/404-mtd-add-more-helper-functions.patch @@ -0,0 +1,101 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -453,14 +453,12 @@ static struct mtd_part *allocate_partiti + if (slave->offset == MTDPART_OFS_APPEND) + slave->offset = cur_offset; + if (slave->offset == MTDPART_OFS_NXTBLK) { +- slave->offset = cur_offset; +- if (mtd_mod_by_eb(cur_offset, master) != 0) { +- /* Round up to next erasesize */ +- slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize; ++ /* Round up to next erasesize */ ++ slave->offset = mtd_roundup_to_eb(cur_offset, master); ++ if (slave->offset != cur_offset) + printk(KERN_NOTICE "Moving partition %d: " + "0x%012llx -> 0x%012llx\n", partno, + (unsigned long long)cur_offset, (unsigned long long)slave->offset); +- } + } + if (slave->offset == MTDPART_OFS_RETAIN) { + slave->offset = cur_offset; +@@ -687,6 +685,17 @@ run_parsers_by_type(struct mtd_part *sla + return nr_parts; + } + ++static inline unsigned long ++mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len) ++{ ++ unsigned long mask = mtd->erasesize - 1; ++ ++ len += offset & mask; ++ len = (len + mask) & ~mask; ++ len -= offset & mask; ++ return len; ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -971,6 +980,24 @@ int mtd_is_partition(const struct mtd_in + } + EXPORT_SYMBOL_GPL(mtd_is_partition); + ++struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd) ++{ ++ if (!mtd_is_partition(mtd)) ++ return (struct mtd_info *)mtd; ++ ++ return PART(mtd)->master; ++} ++EXPORT_SYMBOL_GPL(mtdpart_get_master); ++ ++uint64_t mtdpart_get_offset(const struct mtd_info *mtd) ++{ ++ if (!mtd_is_partition(mtd)) ++ return 0; ++ ++ return PART(mtd)->offset; ++} ++EXPORT_SYMBOL_GPL(mtdpart_get_offset); ++ + /* Returns the size of the entire flash chip */ + uint64_t mtd_get_device_size(const struct mtd_info *mtd) + { +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -90,6 +90,8 @@ int mtd_is_partition(const struct mtd_in + int mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length); + int mtd_del_partition(struct mtd_info *master, int partno); ++struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd); ++uint64_t mtdpart_get_offset(const struct mtd_info *mtd); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); + extern void __weak arch_split_mtd_part(struct mtd_info *master, + const char *name, int offset, int size); +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -334,6 +334,24 @@ static inline uint32_t mtd_mod_by_eb(uin + return do_div(sz, mtd->erasesize); + } + ++static inline uint64_t mtd_roundup_to_eb(uint64_t sz, struct mtd_info *mtd) ++{ ++ if (mtd_mod_by_eb(sz, mtd) == 0) ++ return sz; ++ ++ /* Round up to next erase block */ ++ return (mtd_div_by_eb(sz, mtd) + 1) * mtd->erasesize; ++} ++ ++static inline uint64_t mtd_rounddown_to_eb(uint64_t sz, struct mtd_info *mtd) ++{ ++ if (mtd_mod_by_eb(sz, mtd) == 0) ++ return sz; ++ ++ /* Round down to the start of the current erase block */ ++ return (mtd_div_by_eb(sz, mtd)) * mtd->erasesize; ++} ++ + static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd) + { + if (mtd->writesize_shift) diff --git a/target/linux/generic/patches-4.1/405-mtd-old-firmware-uimage-splitter.patch b/target/linux/generic/patches-4.1/405-mtd-old-firmware-uimage-splitter.patch new file mode 100644 index 0000000..430fd6f --- /dev/null +++ b/target/linux/generic/patches-4.1/405-mtd-old-firmware-uimage-splitter.patch @@ -0,0 +1,70 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -27,6 +27,11 @@ config MTD_SPLIT_FIRMWARE_NAME + depends on MTD_SPLIT_FIRMWARE + default "firmware" + ++config MTD_UIMAGE_SPLIT ++ bool "Enable split support for firmware partitions containing a uImage" ++ depends on MTD_SPLIT_FIRMWARE ++ default y ++ + source "drivers/mtd/mtdsplit/Kconfig" + + endmenu +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -696,6 +696,37 @@ mtd_pad_erasesize(struct mtd_info *mtd, + return len; + } + ++#define UBOOT_MAGIC 0x27051956 ++ ++static void split_uimage(struct mtd_info *master, struct mtd_part *part) ++{ ++ struct { ++ __be32 magic; ++ __be32 pad[2]; ++ __be32 size; ++ } hdr; ++ size_t len; ++ ++ if (mtd_read(master, part->offset, sizeof(hdr), &len, (void *) &hdr)) ++ return; ++ ++ if (len != sizeof(hdr) || hdr.magic != cpu_to_be32(UBOOT_MAGIC)) ++ return; ++ ++ len = be32_to_cpu(hdr.size) + 0x40; ++ len = mtd_pad_erasesize(master, part->offset, len); ++ if (len + master->erasesize > part->mtd.size) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_SPLIT_UIMAGE_FW)) ++ pr_err("Dedicated partitioner didn't split firmware partition, please fill a bug report!\n"); ++ else ++ pr_warn("Support for built-in firmware splitter will be removed, please use CONFIG_MTD_SPLIT_UIMAGE_FW\n"); ++ ++ __mtd_add_partition(master, "rootfs", part->offset + len, ++ part->mtd.size - len, false); ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -704,7 +735,14 @@ mtd_pad_erasesize(struct mtd_info *mtd, + + static void split_firmware(struct mtd_info *master, struct mtd_part *part) + { +- run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); ++ int ret; ++ ++ ret = run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); ++ if (ret > 0) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_UIMAGE_SPLIT)) ++ split_uimage(master, part); + } + + void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, diff --git a/target/linux/generic/patches-4.1/410-mtd-move-forward-declaration-of-struct-mtd_info.patch b/target/linux/generic/patches-4.1/410-mtd-move-forward-declaration-of-struct-mtd_info.patch new file mode 100644 index 0000000..78ebbf8 --- /dev/null +++ b/target/linux/generic/patches-4.1/410-mtd-move-forward-declaration-of-struct-mtd_info.patch @@ -0,0 +1,18 @@ +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -35,6 +35,7 @@ + * Note: writeable partitions require their size and offset be + * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK). + */ ++struct mtd_info; + + struct mtd_partition { + const char *name; /* identifier string */ +@@ -50,7 +51,6 @@ struct mtd_partition { + #define MTDPART_SIZ_FULL (0) + + +-struct mtd_info; + struct device_node; + + /** diff --git a/target/linux/generic/patches-4.1/411-mtd-partial_eraseblock_write.patch b/target/linux/generic/patches-4.1/411-mtd-partial_eraseblock_write.patch new file mode 100644 index 0000000..e6e809c --- /dev/null +++ b/target/linux/generic/patches-4.1/411-mtd-partial_eraseblock_write.patch @@ -0,0 +1,142 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -37,6 +37,8 @@ + #include "mtdcore.h" + #include "mtdsplit/mtdsplit.h" + ++#define MTD_ERASE_PARTIAL 0x8000 /* partition only covers parts of an erase block */ ++ + /* Our partition linked list */ + static LIST_HEAD(mtd_partitions); + static DEFINE_MUTEX(mtd_partitions_mutex); +@@ -235,13 +237,61 @@ static int part_erase(struct mtd_info *m + struct mtd_part *part = PART(mtd); + int ret; + ++ ++ instr->partial_start = false; ++ if (mtd->flags & MTD_ERASE_PARTIAL) { ++ size_t readlen = 0; ++ u64 mtd_ofs; ++ ++ instr->erase_buf = kmalloc(part->master->erasesize, GFP_ATOMIC); ++ if (!instr->erase_buf) ++ return -ENOMEM; ++ ++ mtd_ofs = part->offset + instr->addr; ++ instr->erase_buf_ofs = do_div(mtd_ofs, part->master->erasesize); ++ ++ if (instr->erase_buf_ofs > 0) { ++ instr->addr -= instr->erase_buf_ofs; ++ ret = mtd_read(part->master, ++ instr->addr + part->offset, ++ part->master->erasesize, ++ &readlen, instr->erase_buf); ++ ++ instr->len += instr->erase_buf_ofs; ++ instr->partial_start = true; ++ } else { ++ mtd_ofs = part->offset + part->mtd.size; ++ instr->erase_buf_ofs = part->master->erasesize - ++ do_div(mtd_ofs, part->master->erasesize); ++ ++ if (instr->erase_buf_ofs > 0) { ++ instr->len += instr->erase_buf_ofs; ++ ret = mtd_read(part->master, ++ part->offset + instr->addr + ++ instr->len - part->master->erasesize, ++ part->master->erasesize, &readlen, ++ instr->erase_buf); ++ } else { ++ ret = 0; ++ } ++ } ++ if (ret < 0) { ++ kfree(instr->erase_buf); ++ return ret; ++ } ++ ++ } ++ + instr->addr += part->offset; + ret = part->master->_erase(part->master, instr); + if (ret) { + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; ++ if (mtd->flags & MTD_ERASE_PARTIAL) ++ kfree(instr->erase_buf); + } ++ + return ret; + } + +@@ -249,7 +299,25 @@ void mtd_erase_callback(struct erase_inf + { + if (instr->mtd->_erase == part_erase) { + struct mtd_part *part = PART(instr->mtd); ++ size_t wrlen = 0; + ++ if (instr->mtd->flags & MTD_ERASE_PARTIAL) { ++ if (instr->partial_start) { ++ part->master->_write(part->master, ++ instr->addr, instr->erase_buf_ofs, ++ &wrlen, instr->erase_buf); ++ instr->addr += instr->erase_buf_ofs; ++ } else { ++ instr->len -= instr->erase_buf_ofs; ++ part->master->_write(part->master, ++ instr->addr + instr->len, ++ instr->erase_buf_ofs, &wrlen, ++ instr->erase_buf + ++ part->master->erasesize - ++ instr->erase_buf_ofs); ++ } ++ kfree(instr->erase_buf); ++ } + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; +@@ -522,17 +590,20 @@ static struct mtd_part *allocate_partiti + if ((slave->mtd.flags & MTD_WRITEABLE) && + mtd_mod_by_eb(slave->offset, &slave->mtd)) { + /* Doesn't start on a boundary of major erase size */ +- /* FIXME: Let it be writable if it is on a boundary of +- * _minor_ erase size though */ +- slave->mtd.flags &= ~MTD_WRITEABLE; +- printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase block boundary -- force read-only\n", +- part->name); ++ slave->mtd.flags |= MTD_ERASE_PARTIAL; ++ if (((u32) slave->mtd.size) > master->erasesize) ++ slave->mtd.flags &= ~MTD_WRITEABLE; ++ else ++ slave->mtd.erasesize = slave->mtd.size; + } + if ((slave->mtd.flags & MTD_WRITEABLE) && +- mtd_mod_by_eb(slave->mtd.size, &slave->mtd)) { +- slave->mtd.flags &= ~MTD_WRITEABLE; +- printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase block -- force read-only\n", +- part->name); ++ mtd_mod_by_eb(slave->offset + slave->mtd.size, &slave->mtd)) { ++ slave->mtd.flags |= MTD_ERASE_PARTIAL; ++ ++ if ((u32) slave->mtd.size > master->erasesize) ++ slave->mtd.flags &= ~MTD_WRITEABLE; ++ else ++ slave->mtd.erasesize = slave->mtd.size; + } + + slave->mtd.ecclayout = master->ecclayout; +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -55,6 +55,10 @@ struct erase_info { + u_long priv; + u_char state; + struct erase_info *next; ++ ++ u8 *erase_buf; ++ u32 erase_buf_ofs; ++ bool partial_start; + }; + + struct mtd_erase_region_info { diff --git a/target/linux/generic/patches-4.1/412-mtd-partial_eraseblock_unlock.patch b/target/linux/generic/patches-4.1/412-mtd-partial_eraseblock_unlock.patch new file mode 100644 index 0000000..b7964e2 --- /dev/null +++ b/target/linux/generic/patches-4.1/412-mtd-partial_eraseblock_unlock.patch @@ -0,0 +1,18 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -336,7 +336,14 @@ static int part_lock(struct mtd_info *mt + static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) + { + struct mtd_part *part = PART(mtd); +- return part->master->_unlock(part->master, ofs + part->offset, len); ++ ++ ofs += part->offset; ++ if (mtd->flags & MTD_ERASE_PARTIAL) { ++ /* round up len to next erasesize and round down offset to prev block */ ++ len = (mtd_div_by_eb(len, part->master) + 1) * part->master->erasesize; ++ ofs &= ~(part->master->erasesize - 1); ++ } ++ return part->master->_unlock(part->master, ofs, len); + } + + static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) diff --git a/target/linux/generic/patches-4.1/420-mtd-redboot_space.patch b/target/linux/generic/patches-4.1/420-mtd-redboot_space.patch new file mode 100644 index 0000000..f74affc --- /dev/null +++ b/target/linux/generic/patches-4.1/420-mtd-redboot_space.patch @@ -0,0 +1,30 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -265,14 +265,21 @@ static int parse_redboot_partitions(stru + #endif + names += strlen(names)+1; + +-#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + if(fl->next && fl->img->flash_base + fl->img->size + master->erasesize <= fl->next->img->flash_base) { +- i++; +- parts[i].offset = parts[i-1].size + parts[i-1].offset; +- parts[i].size = fl->next->img->flash_base - parts[i].offset; +- parts[i].name = nullname; +- } ++ if (!strcmp(parts[i].name, "rootfs")) { ++ parts[i].size = fl->next->img->flash_base; ++ parts[i].size &= ~(master->erasesize - 1); ++ parts[i].size -= parts[i].offset; ++#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED ++ nrparts--; ++ } else { ++ i++; ++ parts[i].offset = parts[i-1].size + parts[i-1].offset; ++ parts[i].size = fl->next->img->flash_base - parts[i].offset; ++ parts[i].name = nullname; + #endif ++ } ++ } + tmp_fl = fl; + fl = fl->next; + kfree(tmp_fl); diff --git a/target/linux/generic/patches-4.1/430-mtd-add-myloader-partition-parser.patch b/target/linux/generic/patches-4.1/430-mtd-add-myloader-partition-parser.patch new file mode 100644 index 0000000..fe74ad5 --- /dev/null +++ b/target/linux/generic/patches-4.1/430-mtd-add-myloader-partition-parser.patch @@ -0,0 +1,35 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -179,6 +179,22 @@ config MTD_BCM47XX_PARTS + This provides partitions parser for devices based on BCM47xx + boards. + ++config MTD_MYLOADER_PARTS ++ tristate "MyLoader partition parsing" ++ depends on ADM5120 || ATH25 || ATH79 ++ ---help--- ++ MyLoader is a bootloader which allows the user to define partitions ++ in flash devices, by putting a table in the second erase block ++ on the device, similar to a partition table. This table gives the ++ offsets and lengths of the user defined partitions. ++ ++ If you need code which can detect and parse these tables, and ++ register MTD 'partitions' corresponding to each image detected, ++ enable this option. ++ ++ You will still need the parsing functions to be called by the driver ++ for your particular device. It won't happen automatically. ++ + comment "User Modules And Translation Layers" + + # +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o ++obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/generic/patches-4.1/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch b/target/linux/generic/patches-4.1/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch new file mode 100644 index 0000000..a30e698 --- /dev/null +++ b/target/linux/generic/patches-4.1/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch @@ -0,0 +1,34 @@ +From 841e59ba3e496d86ca5f069204d5e5c1ad43c01d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 27 Jan 2015 22:29:21 +0100 +Subject: [PATCH] mtd: bcm47xxpart: support for Xiaomi specific board_data + partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/bcm47xxpart.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -33,6 +33,7 @@ + /* Magics */ + #define BOARD_DATA_MAGIC 0x5246504D /* MPFR */ + #define BOARD_DATA_MAGIC2 0xBD0D0BBD ++#define BOARD_DATA_XIAOMI_MAGIC 0x474D4442 /* GMDB */ + #define CFE_MAGIC 0x43464531 /* 1EFC */ + #define FACTORY_MAGIC 0x59544346 /* FCTY */ + #define NVRAM_HEADER 0x48534C46 /* FLSH */ +@@ -262,7 +263,8 @@ static int bcm47xxpart_parse(struct mtd_ + } + + /* Some devices (ex. WNDR3700v3) don't have a standard 'MPFR' */ +- if (buf[0x000 / 4] == BOARD_DATA_MAGIC2) { ++ if (buf[0x000 / 4] == BOARD_DATA_MAGIC2 || ++ le32_to_cpu(buf[0x000 / 4]) == BOARD_DATA_XIAOMI_MAGIC) { + bcm47xxpart_add_part(&parts[curr_part++], "board_data", + offset, MTD_WRITEABLE); + continue; diff --git a/target/linux/generic/patches-4.1/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch b/target/linux/generic/patches-4.1/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch new file mode 100644 index 0000000..1edc995 --- /dev/null +++ b/target/linux/generic/patches-4.1/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch @@ -0,0 +1,42 @@ +From fd54aa583296f9adfb1f519affbc10ba521eb809 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 28 Jan 2015 22:14:41 +0100 +Subject: [PATCH] mtd: bcm47xxpart: detect T_Meter partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It can be found on many Netgear devices. It consists of many 0x30 blocks +starting with 4D 54. + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/bcm47xxpart.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -39,6 +39,7 @@ + #define NVRAM_HEADER 0x48534C46 /* FLSH */ + #define POT_MAGIC1 0x54544f50 /* POTT */ + #define POT_MAGIC2 0x504f /* OP */ ++#define T_METER_MAGIC 0x4D540000 /* MT */ + #define ML_MAGIC1 0x39685a42 + #define ML_MAGIC2 0x26594131 + #define TRX_MAGIC 0x30524448 +@@ -176,6 +177,15 @@ static int bcm47xxpart_parse(struct mtd_ + MTD_WRITEABLE); + continue; + } ++ ++ /* T_Meter */ ++ if ((le32_to_cpu(buf[0x000 / 4]) & 0xFFFF0000) == T_METER_MAGIC && ++ (le32_to_cpu(buf[0x030 / 4]) & 0xFFFF0000) == T_METER_MAGIC && ++ (le32_to_cpu(buf[0x060 / 4]) & 0xFFFF0000) == T_METER_MAGIC) { ++ bcm47xxpart_add_part(&parts[curr_part++], "T_Meter", offset, ++ MTD_WRITEABLE); ++ continue; ++ } + + /* TRX */ + if (buf[0x000 / 4] == TRX_MAGIC) { diff --git a/target/linux/generic/patches-4.1/440-block2mtd_init.patch b/target/linux/generic/patches-4.1/440-block2mtd_init.patch new file mode 100644 index 0000000..eddb593 --- /dev/null +++ b/target/linux/generic/patches-4.1/440-block2mtd_init.patch @@ -0,0 +1,108 @@ +--- a/drivers/mtd/devices/block2mtd.c ++++ b/drivers/mtd/devices/block2mtd.c +@@ -25,6 +25,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -218,7 +219,7 @@ static void block2mtd_free_device(struct + + + static struct block2mtd_dev *add_device(char *devname, int erase_size, +- int timeout) ++ const char *mtdname, int timeout) + { + #ifndef MODULE + int i; +@@ -226,6 +227,7 @@ static struct block2mtd_dev *add_device( + const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL; + struct block_device *bdev = ERR_PTR(-ENODEV); + struct block2mtd_dev *dev; ++ struct mtd_partition *part; + char *name; + + if (!devname) +@@ -282,13 +284,16 @@ static struct block2mtd_dev *add_device( + + /* Setup the MTD structure */ + /* make the name contain the block device in */ +- name = kasprintf(GFP_KERNEL, "block2mtd: %s", devname); ++ if (!mtdname) ++ mtdname = devname; ++ name = kmalloc(strlen(mtdname) + 1, GFP_KERNEL); + if (!name) + goto err_destroy_mutex; + ++ strcpy(name, mtdname); + dev->mtd.name = name; + +- dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK; ++ dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK & ~(erase_size - 1); + dev->mtd.erasesize = erase_size; + dev->mtd.writesize = 1; + dev->mtd.writebufsize = PAGE_SIZE; +@@ -301,7 +306,11 @@ static struct block2mtd_dev *add_device( + dev->mtd.priv = dev; + dev->mtd.owner = THIS_MODULE; + +- if (mtd_device_register(&dev->mtd, NULL, 0)) { ++ part = kzalloc(sizeof(struct mtd_partition), GFP_KERNEL); ++ part->name = name; ++ part->offset = 0; ++ part->size = dev->mtd.size; ++ if (mtd_device_register(&dev->mtd, part, 1)) { + /* Device didn't get added, so free the entry */ + goto err_destroy_mutex; + } +@@ -309,8 +318,7 @@ static struct block2mtd_dev *add_device( + list_add(&dev->list, &blkmtd_device_list); + pr_info("mtd%d: [%s] erase_size = %dKiB [%d]\n", + dev->mtd.index, +- dev->mtd.name + strlen("block2mtd: "), +- dev->mtd.erasesize >> 10, dev->mtd.erasesize); ++ mtdname, dev->mtd.erasesize >> 10, dev->mtd.erasesize); + return dev; + + err_destroy_mutex: +@@ -383,7 +391,7 @@ static int block2mtd_setup2(const char * + /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ + char buf[80 + 12 + 80 + 8]; + char *str = buf; +- char *token[2]; ++ char *token[3]; + char *name; + size_t erase_size = PAGE_SIZE; + unsigned long timeout = MTD_DEFAULT_TIMEOUT; +@@ -397,7 +405,7 @@ static int block2mtd_setup2(const char * + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 2; i++) ++ for (i = 0; i < 3; i++) + token[i] = strsep(&str, ","); + + if (str) { +@@ -423,8 +431,10 @@ static int block2mtd_setup2(const char * + return 0; + } + } ++ if (token[2] && (strlen(token[2]) + 1 > 80)) ++ pr_err("mtd device name too long\n"); + +- add_device(name, erase_size, timeout); ++ add_device(name, erase_size, token[2], timeout); + + return 0; + } +@@ -458,7 +468,7 @@ static int block2mtd_setup(const char *v + + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); +-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,]\""); ++MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); + + static int __init block2mtd_init(void) + { diff --git a/target/linux/generic/patches-4.1/441-block2mtd_probe.patch b/target/linux/generic/patches-4.1/441-block2mtd_probe.patch new file mode 100644 index 0000000..f78e80a --- /dev/null +++ b/target/linux/generic/patches-4.1/441-block2mtd_probe.patch @@ -0,0 +1,39 @@ +--- a/drivers/mtd/devices/block2mtd.c ++++ b/drivers/mtd/devices/block2mtd.c +@@ -391,7 +391,7 @@ static int block2mtd_setup2(const char * + /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ + char buf[80 + 12 + 80 + 8]; + char *str = buf; +- char *token[3]; ++ char *token[4]; + char *name; + size_t erase_size = PAGE_SIZE; + unsigned long timeout = MTD_DEFAULT_TIMEOUT; +@@ -405,7 +405,7 @@ static int block2mtd_setup2(const char * + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 3; i++) ++ for (i = 0; i < 4; i++) + token[i] = strsep(&str, ","); + + if (str) { +@@ -434,6 +434,9 @@ static int block2mtd_setup2(const char * + if (token[2] && (strlen(token[2]) + 1 > 80)) + pr_err("mtd device name too long\n"); + ++ if (token[3] && kstrtoul(token[3], 0, &timeout)) ++ pr_err("invalid timeout\n"); ++ + add_device(name, erase_size, token[2], timeout); + + return 0; +@@ -468,7 +471,7 @@ static int block2mtd_setup(const char *v + + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); +-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); ++MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,[,]]]\""); + + static int __init block2mtd_init(void) + { diff --git a/target/linux/generic/patches-4.1/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch b/target/linux/generic/patches-4.1/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch new file mode 100644 index 0000000..ffaf706 --- /dev/null +++ b/target/linux/generic/patches-4.1/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch @@ -0,0 +1,37 @@ +--- + drivers/mtd/nand/plat_nand.c | 13 ++++++++++++- + include/linux/mtd/nand.h | 1 + + 2 files changed, 13 insertions(+), 1 deletion(-) + +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -865,6 +865,7 @@ struct platform_nand_chip { + unsigned int options; + unsigned int bbt_options; + const char **part_probe_types; ++ int (*chip_fixup)(struct mtd_info *mtd); + }; + + /* Keep gcc happy */ +--- a/drivers/mtd/nand/plat_nand.c ++++ b/drivers/mtd/nand/plat_nand.c +@@ -90,7 +90,18 @@ static int plat_nand_probe(struct platfo + } + + /* Scan to find existence of the device */ +- if (nand_scan(&data->mtd, pdata->chip.nr_chips)) { ++ if (nand_scan_ident(&data->mtd, pdata->chip.nr_chips, NULL)) { ++ err = -ENXIO; ++ goto out; ++ } ++ ++ if (pdata->chip.chip_fixup) { ++ err = pdata->chip.chip_fixup(&data->mtd); ++ if (err) ++ goto out; ++ } ++ ++ if (nand_scan_tail(&data->mtd)) { + err = -ENXIO; + goto out; + } diff --git a/target/linux/generic/patches-4.1/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch b/target/linux/generic/patches-4.1/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch new file mode 100644 index 0000000..6a2092c --- /dev/null +++ b/target/linux/generic/patches-4.1/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/nand/nand_ecc.c ++++ b/drivers/mtd/nand/nand_ecc.c +@@ -507,7 +507,7 @@ int __nand_correct_data(unsigned char *b + return 1; /* error in ECC data; no action needed */ + + pr_err("%s: uncorrectable ECC error\n", __func__); +- return -1; ++ return -EBADMSG; + } + EXPORT_SYMBOL(__nand_correct_data); + diff --git a/target/linux/generic/patches-4.1/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch b/target/linux/generic/patches-4.1/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch new file mode 100644 index 0000000..68fbd12 --- /dev/null +++ b/target/linux/generic/patches-4.1/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -809,7 +809,7 @@ static int get_chip(struct map_info *map + return 0; + + case FL_ERASING: +- if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || ++ if (1 /* no suspend */ || !cfip || !(cfip->EraseSuspend & (0x1|0x2)) || + !(mode == FL_READY || mode == FL_POINT || + (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) + goto sleep; diff --git a/target/linux/generic/patches-4.1/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch b/target/linux/generic/patches-4.1/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch new file mode 100644 index 0000000..c437a14 --- /dev/null +++ b/target/linux/generic/patches-4.1/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch @@ -0,0 +1,18 @@ +From: George Kashperko + +Issue map read after Write Buffer Load command to ensure chip is ready +to receive data. +Signed-off-by: George Kashperko +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 1 + + 1 file changed, 1 insertion(+) +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1830,6 +1830,7 @@ static int __xipram do_write_buffer(stru + + /* Write Buffer Load */ + map_write(map, CMD(0x25), cmd_adr); ++ (void) map_read(map, cmd_adr); + + chip->state = FL_WRITING_TO_BUFFER; + diff --git a/target/linux/generic/patches-4.1/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch b/target/linux/generic/patches-4.1/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch new file mode 100644 index 0000000..a828b7d --- /dev/null +++ b/target/linux/generic/patches-4.1/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch @@ -0,0 +1,21 @@ +From 0d7388de0911c1a4fc4a8a3898ef9d0ab818ca08 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 7 Apr 2015 18:35:15 +0200 +Subject: [PATCH] mtd: spi-nor: add support for the Macronix MX25L512E SPI + flash chip + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/spi-nor/spi-nor.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -561,6 +561,7 @@ static const struct spi_device_id spi_no + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, + + /* Macronix */ ++ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, + { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, + { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, diff --git a/target/linux/generic/patches-4.1/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch b/target/linux/generic/patches-4.1/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch new file mode 100644 index 0000000..62e0ce8 --- /dev/null +++ b/target/linux/generic/patches-4.1/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch @@ -0,0 +1,22 @@ +From 34e2b403040a2f9d3ba071d95a7f42457e2950f9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 7 Apr 2015 18:35:15 +0200 +Subject: [PATCH] mtd: spi-nor: add support for the ISSI SI25CD512 SPI flash + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/spi-nor/spi-nor.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -560,6 +560,9 @@ static const struct spi_device_id spi_no + { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, + ++ /* ISSI */ ++ { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, ++ + /* Macronix */ + { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, diff --git a/target/linux/generic/patches-4.1/480-mtd-set-rootfs-to-be-root-dev.patch b/target/linux/generic/patches-4.1/480-mtd-set-rootfs-to-be-root-dev.patch new file mode 100644 index 0000000..8d3a1f4 --- /dev/null +++ b/target/linux/generic/patches-4.1/480-mtd-set-rootfs-to-be-root-dev.patch @@ -0,0 +1,26 @@ +--- a/drivers/mtd/mtdcore.c ++++ b/drivers/mtd/mtdcore.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -448,6 +449,15 @@ int add_mtd_device(struct mtd_info *mtd) + of this try_ nonsense, and no bitching about it + either. :) */ + __module_get(THIS_MODULE); ++ ++ if (!strcmp(mtd->name, "rootfs") && ++ config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ ROOT_DEV == 0) { ++ pr_notice("mtd: device %d (%s) set to be root filesystem\n", ++ mtd->index, mtd->name); ++ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index); ++ } ++ + return 0; + + fail_added: diff --git a/target/linux/generic/patches-4.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/patches-4.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch new file mode 100644 index 0000000..d2fb802 --- /dev/null +++ b/target/linux/generic/patches-4.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch @@ -0,0 +1,76 @@ +From 8a52e4100d7c3a4a1dfddfa02b8864a9b0068c13 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 17 May 2014 03:36:18 +0200 +Subject: [PATCH 1/5] ubi: auto-attach mtd device named "ubi" or "data" on boot +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/drivers/mtd/ubi/build.c ++++ b/drivers/mtd/ubi/build.c +@@ -1218,6 +1218,49 @@ static struct mtd_info * __init open_mtd + return mtd; + } + ++/* ++ * This function tries attaching mtd partitions named either "ubi" or "data" ++ * during boot. ++ */ ++static void __init ubi_auto_attach(void) ++{ ++ int err; ++ struct mtd_info *mtd; ++ ++ /* try attaching mtd device named "ubi" or "data" */ ++ mtd = open_mtd_device("ubi"); ++ if (IS_ERR(mtd)) ++ mtd = open_mtd_device("data"); ++ ++ if (!IS_ERR(mtd)) { ++ size_t len; ++ char magic[4]; ++ ++ /* check for a valid ubi magic */ ++ err = mtd_read(mtd, 0, 4, &len, (void *) magic); ++ if (!err && len == 4 && strncmp(magic, "UBI#", 4)) { ++ pr_err("UBI error: no valid UBI magic found inside mtd%d", mtd->index); ++ put_mtd_device(mtd); ++ return; ++ } ++ ++ /* auto-add only media types where UBI makes sense */ ++ if (mtd->type == MTD_NANDFLASH || ++ mtd->type == MTD_NORFLASH || ++ mtd->type == MTD_DATAFLASH || ++ mtd->type == MTD_MLCNANDFLASH) { ++ mutex_lock(&ubi_devices_mutex); ++ pr_notice("UBI: auto-attach mtd%d", mtd->index); ++ err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0); ++ mutex_unlock(&ubi_devices_mutex); ++ if (err < 0) { ++ pr_err("UBI error: cannot attach mtd%d", mtd->index); ++ put_mtd_device(mtd); ++ } ++ } ++ } ++} ++ + static int __init ubi_init(void) + { + int err, i, k; +@@ -1310,6 +1353,12 @@ static int __init ubi_init(void) + } + } + ++ /* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd ++ * parameter was given */ ++ if (config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ !ubi_is_module() && !mtd_devs) ++ ubi_auto_attach(); ++ + err = ubiblock_init(); + if (err) { + pr_err("UBI error: block: cannot initialize, error %d", err); diff --git a/target/linux/generic/patches-4.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/patches-4.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch new file mode 100644 index 0000000..433d77b --- /dev/null +++ b/target/linux/generic/patches-4.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch @@ -0,0 +1,69 @@ +From 0f3966579815f889bb2fcb4846152c35f65e79c4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 15 May 2014 21:06:33 +0200 +Subject: [PATCH 2/5] ubi: auto-create ubiblock device for rootfs +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/block.c | 42 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -616,6 +616,44 @@ static void __init ubiblock_create_from_ + } + } + ++#define UBIFS_NODE_MAGIC 0x06101831 ++static inline int ubi_vol_is_ubifs(struct ubi_volume_desc *desc) ++{ ++ int ret; ++ uint32_t magic_of, magic; ++ ret = ubi_read(desc, 0, (char *)&magic_of, 0, 4); ++ if (ret) ++ return 0; ++ magic = le32_to_cpu(magic_of); ++ return magic == UBIFS_NODE_MAGIC; ++} ++ ++static void __init ubiblock_create_auto_rootfs(void) ++{ ++ int ubi_num, ret, is_ubifs; ++ struct ubi_volume_desc *desc; ++ struct ubi_volume_info vi; ++ ++ for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) { ++ desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY); ++ if (IS_ERR(desc)) ++ continue; ++ ++ ubi_get_volume_info(desc, &vi); ++ is_ubifs = ubi_vol_is_ubifs(desc); ++ ubi_close_volume(desc); ++ if (is_ubifs) ++ break; ++ ++ ret = ubiblock_create(&vi); ++ if (ret) ++ pr_err("UBI error: block: can't add '%s' volume, err=%d\n", ++ vi.name, ret); ++ /* always break if we get here */ ++ break; ++ } ++} ++ + static void ubiblock_remove_all(void) + { + struct ubiblock *next; +@@ -646,6 +684,10 @@ int __init ubiblock_init(void) + */ + ubiblock_create_from_param(); + ++ /* auto-attach "rootfs" volume if existing and non-ubifs */ ++ if (config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV)) ++ ubiblock_create_auto_rootfs(); ++ + /* + * Block devices are only created upon user requests, so we ignore + * existing volumes. diff --git a/target/linux/generic/patches-4.1/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch b/target/linux/generic/patches-4.1/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch new file mode 100644 index 0000000..005de3f --- /dev/null +++ b/target/linux/generic/patches-4.1/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch @@ -0,0 +1,53 @@ +From eea9e1785e4c05c2a3444506aabafa0ae958538f Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 17 May 2014 03:35:02 +0200 +Subject: [PATCH 4/5] try auto-mounting ubi0:rootfs in init/do_mounts.c +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + init/do_mounts.c | 26 +++++++++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +--- a/init/do_mounts.c ++++ b/init/do_mounts.c +@@ -438,7 +438,27 @@ retry: + out: + put_page(page); + } +- ++ ++static int __init mount_ubi_rootfs(void) ++{ ++ int flags = MS_SILENT; ++ int err, tried = 0; ++ ++ while (tried < 2) { ++ err = do_mount_root("ubi0:rootfs", "ubifs", flags, \ ++ root_mount_data); ++ switch (err) { ++ case -EACCES: ++ flags |= MS_RDONLY; ++ tried++; ++ default: ++ return err; ++ } ++ } ++ ++ return -EINVAL; ++} ++ + #ifdef CONFIG_ROOT_NFS + + #define NFSROOT_TIMEOUT_MIN 5 +@@ -532,6 +552,10 @@ void __init mount_root(void) + change_floppy("root floppy"); + } + #endif ++#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV ++ if (!mount_ubi_rootfs()) ++ return; ++#endif + #ifdef CONFIG_BLOCK + create_dev("/dev/root", ROOT_DEV); + mount_block_root("/dev/root", root_mountflags); diff --git a/target/linux/generic/patches-4.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/patches-4.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch new file mode 100644 index 0000000..1873752 --- /dev/null +++ b/target/linux/generic/patches-4.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch @@ -0,0 +1,37 @@ +From cd68d1b12b5ea4c01a664c064179ada42bf55d3d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 15 May 2014 20:55:42 +0200 +Subject: [PATCH 5/5] ubi: set ROOT_DEV to ubiblock "rootfs" if unset +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/block.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -49,6 +49,7 @@ + #include + #include + #include ++#include + + #include "ubi-media.h" + #include "ubi.h" +@@ -439,6 +440,15 @@ int ubiblock_create(struct ubi_volume_in + add_disk(dev->gd); + dev_info(disk_to_dev(dev->gd), "created from ubi%d:%d(%s)", + dev->ubi_num, dev->vol_id, vi->name); ++ ++ if (!strcmp(vi->name, "rootfs") && ++ config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ ROOT_DEV == 0) { ++ pr_notice("ubiblock: device ubiblock%d_%d (%s) set to be root filesystem\n", ++ dev->ubi_num, dev->vol_id, vi->name); ++ ROOT_DEV = MKDEV(gd->major, gd->first_minor); ++ } ++ + return 0; + + out_free_queue: diff --git a/target/linux/generic/patches-4.1/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/patches-4.1/494-mtd-ubi-add-EOF-marker-support.patch new file mode 100644 index 0000000..14fae76 --- /dev/null +++ b/target/linux/generic/patches-4.1/494-mtd-ubi-add-EOF-marker-support.patch @@ -0,0 +1,51 @@ +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -803,6 +803,13 @@ out_unlock: + return err; + } + ++static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech) ++{ ++ return ech->padding1[0] == 'E' && ++ ech->padding1[1] == 'O' && ++ ech->padding1[2] == 'F'; ++} ++ + /** + * scan_peb - scan and process UBI headers of a PEB. + * @ubi: UBI device description object +@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u + return 0; + } + +- err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); +- if (err < 0) +- return err; ++ if (!ai->eof_found) { ++ err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); ++ if (err < 0) ++ return err; ++ ++ if (ec_hdr_has_eof(ech)) { ++ pr_notice("UBI: EOF marker found, PEBs from %d will be erased", ++ pnum); ++ ai->eof_found = true; ++ } ++ } ++ ++ if (ai->eof_found) ++ err = UBI_IO_FF_BITFLIPS; ++ + switch (err) { + case 0: + break; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -739,6 +739,7 @@ struct ubi_attach_info { + int mean_ec; + uint64_t ec_sum; + int ec_count; ++ bool eof_found; + struct kmem_cache *aeb_slab_cache; + }; + diff --git a/target/linux/generic/patches-4.1/500-yaffs-Kbuild-integration.patch b/target/linux/generic/patches-4.1/500-yaffs-Kbuild-integration.patch new file mode 100644 index 0000000..2754c1a --- /dev/null +++ b/target/linux/generic/patches-4.1/500-yaffs-Kbuild-integration.patch @@ -0,0 +1,18 @@ +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -33,6 +33,7 @@ source "fs/ocfs2/Kconfig" + source "fs/btrfs/Kconfig" + source "fs/nilfs2/Kconfig" + source "fs/f2fs/Kconfig" ++source "fs/yaffs2/Kconfig" + + config FS_DAX + bool "Direct Access (DAX) support" +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -127,3 +127,5 @@ obj-y += exofs/ # Multiple modules + obj-$(CONFIG_CEPH_FS) += ceph/ + obj-$(CONFIG_PSTORE) += pstore/ + obj-$(CONFIG_EFIVAR_FS) += efivarfs/ ++obj-$(CONFIG_YAFFS_FS) += yaffs2/ ++ diff --git a/target/linux/generic/patches-4.1/502-yaffs-fix-compat-tags-handling.patch b/target/linux/generic/patches-4.1/502-yaffs-fix-compat-tags-handling.patch new file mode 100644 index 0000000..a18cf6f --- /dev/null +++ b/target/linux/generic/patches-4.1/502-yaffs-fix-compat-tags-handling.patch @@ -0,0 +1,239 @@ +Subject: yaffs: fix compat tags handling + +Signed-off-by: Gabor Juhos +--- +--- a/fs/yaffs2/yaffs_tagscompat.c ++++ b/fs/yaffs2/yaffs_tagscompat.c +@@ -17,7 +17,9 @@ + #include "yaffs_getblockinfo.h" + #include "yaffs_trace.h" + ++#if 0 + static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk); ++#endif + + + /********** Tags ECC calculations *********/ +@@ -71,6 +73,7 @@ int yaffs_check_tags_ecc(struct yaffs_ta + return 0; + } + ++#if 0 + /********** Tags **********/ + + static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr, +@@ -379,3 +382,214 @@ void yaffs_tags_compat_install(struct ya + if(!dev->tagger.mark_bad_fn) + dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; + } ++#else ++ ++#include "yaffs_packedtags1.h" ++ ++static int yaffs_tags_compat_write(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *data, ++ const struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags1 pt1; ++ u8 tag_buf[9]; ++ int retval; ++ ++ /* we assume that yaffs_packed_tags1 and yaffs_tags are compatible */ ++ compile_time_assertion(sizeof(struct yaffs_packed_tags1) == 12); ++ compile_time_assertion(sizeof(struct yaffs_tags) == 8); ++ ++ yaffs_pack_tags1(&pt1, tags); ++ yaffs_calc_tags_ecc((struct yaffs_tags *)&pt1); ++ ++ /* When deleting a chunk, the upper layer provides only skeletal ++ * tags, one with is_deleted set. However, we need to update the ++ * tags, not erase them completely. So we use the NAND write property ++ * that only zeroed-bits stick and set tag bytes to all-ones and ++ * zero just the (not) deleted bit. ++ */ ++ if (!dev->param.tags_9bytes) { ++ if (tags->is_deleted) { ++ memset(&pt1, 0xff, 8); ++ /* clear delete status bit to indicate deleted */ ++ pt1.deleted = 0; ++ } ++ memcpy(tag_buf, &pt1, 8); ++ } else { ++ if (tags->is_deleted) { ++ memset(tag_buf, 0xff, 8); ++ tag_buf[8] = 0; ++ } else { ++ memcpy(tag_buf, &pt1, 8); ++ tag_buf[8] = 0xff; ++ } ++ } ++ ++ retval = dev->drv.drv_write_chunk_fn(dev, nand_chunk, ++ data, ++ (data) ? dev->data_bytes_per_chunk : 0, ++ tag_buf, ++ (dev->param.tags_9bytes) ? 9 : 8); ++ ++ return retval; ++} ++ ++/* Return with empty extended tags but add ecc_result. ++ */ ++static int return_empty_tags(struct yaffs_ext_tags *tags, ++ enum yaffs_ecc_result ecc_result, ++ int retval) ++{ ++ if (tags) { ++ memset(tags, 0, sizeof(*tags)); ++ tags->ecc_result = ecc_result; ++ } ++ ++ return retval; ++} ++ ++static int yaffs_tags_compat_read(struct yaffs_dev *dev, ++ int nand_chunk, ++ u8 *data, ++ struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags1 pt1; ++ enum yaffs_ecc_result ecc_result; ++ int retval; ++ int deleted; ++ u8 tag_buf[9]; ++ ++ retval = dev->drv.drv_read_chunk_fn(dev, nand_chunk, ++ data, dev->param.total_bytes_per_chunk, ++ tag_buf, ++ (dev->param.tags_9bytes) ? 9 : 8, ++ &ecc_result); ++ ++ switch (ecc_result) { ++ case YAFFS_ECC_RESULT_NO_ERROR: ++ case YAFFS_ECC_RESULT_FIXED: ++ break; ++ ++ case YAFFS_ECC_RESULT_UNFIXED: ++ default: ++ return_empty_tags(tags, YAFFS_ECC_RESULT_UNFIXED, 0); ++ tags->block_bad = dev->drv.drv_check_bad_fn(dev, nand_chunk); ++ return YAFFS_FAIL; ++ } ++ ++ /* Check for a blank/erased chunk. */ ++ if (yaffs_check_ff(tag_buf, 8)) { ++ /* when blank, upper layers want ecc_result to be <= NO_ERROR */ ++ return return_empty_tags(tags, YAFFS_ECC_RESULT_NO_ERROR, ++ YAFFS_OK); ++ } ++ ++ memcpy(&pt1, tag_buf, 8); ++ ++ if (!dev->param.tags_9bytes) { ++ /* Read deleted status (bit) then return it to it's non-deleted ++ * state before performing tags mini-ECC check. pt1.deleted is ++ * inverted. ++ */ ++ deleted = !pt1.deleted; ++ pt1.deleted = 1; ++ } else { ++ deleted = (hweight8(tag_buf[8]) < 7) ? 1 : 0; ++ } ++ ++ /* Check the packed tags mini-ECC and correct if necessary/possible. */ ++ retval = yaffs_check_tags_ecc((struct yaffs_tags *)&pt1); ++ switch (retval) { ++ case 0: ++ /* no tags error, use MTD result */ ++ break; ++ case 1: ++ /* recovered tags-ECC error */ ++ dev->n_tags_ecc_fixed++; ++ if (ecc_result == YAFFS_ECC_RESULT_NO_ERROR) ++ ecc_result = YAFFS_ECC_RESULT_FIXED; ++ break; ++ default: ++ /* unrecovered tags-ECC error */ ++ dev->n_tags_ecc_unfixed++; ++ return return_empty_tags(tags, YAFFS_ECC_RESULT_UNFIXED, ++ YAFFS_FAIL); ++ } ++ ++ /* Unpack the tags to extended form and set ECC result. ++ * [set should_be_ff just to keep yaffs_unpack_tags1 happy] ++ */ ++ pt1.should_be_ff = 0xffffffff; ++ yaffs_unpack_tags1(tags, &pt1); ++ tags->ecc_result = ecc_result; ++ ++ /* Set deleted state */ ++ tags->is_deleted = deleted; ++ return YAFFS_OK; ++} ++ ++static int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no) ++{ ++ return dev->drv.drv_mark_bad_fn(dev, block_no); ++} ++ ++static int yaffs_tags_compat_query_block(struct yaffs_dev *dev, ++ int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number) ++{ ++ struct yaffs_ext_tags tags; ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, "%s %d", __func__, block_no); ++ ++ *seq_number = 0; ++ ++ retval = dev->drv.drv_check_bad_fn(dev, block_no); ++ if (retval == YAFFS_FAIL) { ++ *state = YAFFS_BLOCK_STATE_DEAD; ++ goto out; ++ } ++ ++ yaffs_tags_compat_read(dev, block_no * dev->param.chunks_per_block, ++ NULL, &tags); ++ ++ if (tags.ecc_result != YAFFS_ECC_RESULT_NO_ERROR) { ++ yaffs_trace(YAFFS_TRACE_MTD, "block %d is marked bad", ++ block_no); ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else if (tags.chunk_used) { ++ *seq_number = tags.seq_number; ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else { ++ *state = YAFFS_BLOCK_STATE_EMPTY; ++ } ++ ++ retval = YAFFS_OK; ++ ++out: ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "block query returns seq %u state %d", ++ *seq_number, *state); ++ ++ return retval; ++} ++ ++void yaffs_tags_compat_install(struct yaffs_dev *dev) ++{ ++ if (dev->param.is_yaffs2) ++ return; ++ ++ if (!dev->tagger.write_chunk_tags_fn) ++ dev->tagger.write_chunk_tags_fn = yaffs_tags_compat_write; ++ ++ if (!dev->tagger.read_chunk_tags_fn) ++ dev->tagger.read_chunk_tags_fn = yaffs_tags_compat_read; ++ ++ if (!dev->tagger.query_block_fn) ++ dev->tagger.query_block_fn = yaffs_tags_compat_query_block; ++ ++ if (!dev->tagger.mark_bad_fn) ++ dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; ++} ++#endif diff --git a/target/linux/generic/patches-4.1/503-yaffs-add-tags-9bytes-mount-option.patch b/target/linux/generic/patches-4.1/503-yaffs-add-tags-9bytes-mount-option.patch new file mode 100644 index 0000000..3f51baf --- /dev/null +++ b/target/linux/generic/patches-4.1/503-yaffs-add-tags-9bytes-mount-option.patch @@ -0,0 +1,115 @@ +Subject: yaffs: add support for tags-9bytes mount option + +Signed-off-by: Gabor Juhos +--- +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -2644,6 +2644,7 @@ static const struct super_operations yaf + + struct yaffs_options { + int inband_tags; ++ int tags_9bytes; + int skip_checkpoint_read; + int skip_checkpoint_write; + int no_cache; +@@ -2683,6 +2684,8 @@ static int yaffs_parse_options(struct ya + + if (!strcmp(cur_opt, "inband-tags")) { + options->inband_tags = 1; ++ } else if (!strcmp(cur_opt, "tags-9bytes")) { ++ options->tags_9bytes = 1; + } else if (!strcmp(cur_opt, "tags-ecc-off")) { + options->tags_ecc_on = 0; + options->tags_ecc_overridden = 1; +@@ -2756,7 +2759,6 @@ static struct super_block *yaffs_interna + struct yaffs_param *param; + + int read_only = 0; +- int inband_tags = 0; + + struct yaffs_options options; + +@@ -2796,6 +2798,9 @@ static struct super_block *yaffs_interna + + memset(&options, 0, sizeof(options)); + ++ if (IS_ENABLED(CONFIG_YAFFS_9BYTE_TAGS)) ++ options.tags_9bytes = 1; ++ + if (yaffs_parse_options(&options, data_str)) { + /* Option parsing failed */ + return NULL; +@@ -2829,17 +2834,22 @@ static struct super_block *yaffs_interna + } + + /* Added NCB 26/5/2006 for completeness */ +- if (yaffs_version == 2 && !options.inband_tags +- && WRITE_SIZE(mtd) == 512) { ++ if (yaffs_version == 2 && ++ (!options.inband_tags || options.tags_9bytes) && ++ WRITE_SIZE(mtd) == 512) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting yaffs1"); + yaffs_version = 1; + } + +- if (mtd->oobavail < sizeof(struct yaffs_packed_tags2) || +- options.inband_tags) +- inband_tags = 1; ++ if (yaffs_version == 2 && ++ mtd->oobavail < sizeof(struct yaffs_packed_tags2)) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting inband tags"); ++ options.inband_tags = 1; ++ } + +- if(yaffs_verify_mtd(mtd, yaffs_version, inband_tags) < 0) ++ err = yaffs_verify_mtd(mtd, yaffs_version, options.inband_tags, ++ options.tags_9bytes); ++ if (err < 0) + return NULL; + + /* OK, so if we got here, we have an MTD that's NAND and looks +@@ -2896,7 +2906,8 @@ static struct super_block *yaffs_interna + + param->n_reserved_blocks = 5; + param->n_caches = (options.no_cache) ? 0 : 10; +- param->inband_tags = inband_tags; ++ param->inband_tags = options.inband_tags; ++ param->tags_9bytes = options.tags_9bytes; + + param->enable_xattr = 1; + if (options.lazy_loading_overridden) +--- a/fs/yaffs2/yaffs_mtdif.c ++++ b/fs/yaffs2/yaffs_mtdif.c +@@ -278,7 +278,8 @@ struct mtd_info * yaffs_get_mtd_device(d + return mtd; + } + +-int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags) ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags, ++ int tags_9bytes) + { + if (yaffs_version == 2) { + if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || +@@ -297,6 +298,12 @@ int yaffs_verify_mtd(struct mtd_info *mt + ); + return -1; + } ++ ++ if (tags_9bytes && mtd->oobavail < 9) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "MTD device does not support 9-byte tags"); ++ return -1; ++ } + } + + return 0; +--- a/fs/yaffs2/yaffs_mtdif.h ++++ b/fs/yaffs2/yaffs_mtdif.h +@@ -21,5 +21,6 @@ + void yaffs_mtd_drv_install(struct yaffs_dev *dev); + struct mtd_info * yaffs_get_mtd_device(dev_t sdev); + void yaffs_put_mtd_device(struct mtd_info *mtd); +-int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags); ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags, ++ int tags_9bytes); + #endif diff --git a/target/linux/generic/patches-4.1/504-yaffs-3.16-new-fops.patch b/target/linux/generic/patches-4.1/504-yaffs-3.16-new-fops.patch new file mode 100644 index 0000000..32b4fdf --- /dev/null +++ b/target/linux/generic/patches-4.1/504-yaffs-3.16-new-fops.patch @@ -0,0 +1,29 @@ +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -774,7 +774,25 @@ static int yaffs_sync_object(struct file + } + + +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) ++static const struct file_operations yaffs_file_operations = { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)) ++ .read = new_sync_read, ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0) */ ++ .read_iter = generic_file_read_iter, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)) ++ .write = new_sync_write, ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0) */ ++ .write_iter = generic_file_write_iter, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++ .splice_read = generic_file_splice_read, ++ .splice_write = iter_file_splice_write, ++ .llseek = generic_file_llseek, ++}; ++ ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) + static const struct file_operations yaffs_file_operations = { + .read = do_sync_read, + .write = do_sync_write, diff --git a/target/linux/generic/patches-4.1/505-yaffs-3.19-f_dentry-remove.patch b/target/linux/generic/patches-4.1/505-yaffs-3.19-f_dentry-remove.patch new file mode 100644 index 0000000..0d4b6bf --- /dev/null +++ b/target/linux/generic/patches-4.1/505-yaffs-3.19-f_dentry-remove.patch @@ -0,0 +1,95 @@ +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -283,7 +283,7 @@ static int yaffs_readpage_nolock(struct + (long long)pos, + (unsigned)PAGE_CACHE_SIZE); + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -481,7 +481,7 @@ static ssize_t yaffs_hold_space(struct f + + int n_free_chunks; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -499,7 +499,7 @@ static void yaffs_release_space(struct f + struct yaffs_obj *obj; + struct yaffs_dev *dev; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -591,7 +591,7 @@ static ssize_t yaffs_file_write(struct f + struct inode *inode; + struct yaffs_dev *dev; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + if (!obj) { + yaffs_trace(YAFFS_TRACE_OS, +@@ -603,7 +603,7 @@ static ssize_t yaffs_file_write(struct f + + yaffs_gross_lock(dev); + +- inode = f->f_dentry->d_inode; ++ inode = f->f_path.dentry->d_inode; + + if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) + ipos = inode->i_size; +@@ -727,7 +727,7 @@ static int yaffs_file_flush(struct file + static int yaffs_file_flush(struct file *file) + #endif + { +- struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_dentry); ++ struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_path.dentry); + + struct yaffs_dev *dev = obj->my_dev; + +@@ -1734,7 +1734,7 @@ static int yaffs_iterate(struct file *f, + + char name[YAFFS_MAX_NAME_LENGTH + 1]; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + dev = obj->my_dev; + + yaffs_gross_lock(dev); +@@ -1798,14 +1798,14 @@ static int yaffs_readdir(struct file *f, + struct yaffs_obj *obj; + struct yaffs_dev *dev; + struct yaffs_search_context *sc; +- struct inode *inode = f->f_dentry->d_inode; ++ struct inode *inode = f->f_path.dentry->d_inode; + unsigned long offset, curoffs; + struct yaffs_obj *l; + int ret_val = 0; + + char name[YAFFS_MAX_NAME_LENGTH + 1]; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + dev = obj->my_dev; + + yaffs_gross_lock(dev); +@@ -1839,10 +1839,10 @@ static int yaffs_readdir(struct file *f, + if (offset == 1) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readdir: entry .. ino %d", +- (int)f->f_dentry->d_parent->d_inode->i_ino); ++ (int)f->f_path.dentry->d_parent->d_inode->i_ino); + yaffs_gross_unlock(dev); + if (filldir(dirent, "..", 2, offset, +- f->f_dentry->d_parent->d_inode->i_ino, ++ f->f_path.dentry->d_parent->d_inode->i_ino, + DT_DIR) < 0) { + yaffs_gross_lock(dev); + goto out; diff --git a/target/linux/generic/patches-4.1/520-squashfs_update_xz_comp_opts.patch b/target/linux/generic/patches-4.1/520-squashfs_update_xz_comp_opts.patch new file mode 100644 index 0000000..ad11b30 --- /dev/null +++ b/target/linux/generic/patches-4.1/520-squashfs_update_xz_comp_opts.patch @@ -0,0 +1,25 @@ +From f31b7c0efa255dd17a5f584022a319387f09b0d8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 12 Apr 2011 19:55:41 +0200 +Subject: [PATCH] squashfs: update xz compressor options struct. + +Update the xz compressor options struct to match the squashfs userspace +one. +--- + fs/squashfs/xz_wrapper.c | 4 +++- + 1 files changed, 3 insertions(+), 1 deletions(-) + +--- a/fs/squashfs/xz_wrapper.c ++++ b/fs/squashfs/xz_wrapper.c +@@ -40,8 +40,10 @@ struct squashfs_xz { + }; + + struct disk_comp_opts { +- __le32 dictionary_size; + __le32 flags; ++ __le16 bit_opts; ++ __le16 fb; ++ __le32 dictionary_size; + }; + + struct comp_opts { diff --git a/target/linux/generic/patches-4.1/530-jffs2_make_lzma_available.patch b/target/linux/generic/patches-4.1/530-jffs2_make_lzma_available.patch new file mode 100644 index 0000000..c8301f0 --- /dev/null +++ b/target/linux/generic/patches-4.1/530-jffs2_make_lzma_available.patch @@ -0,0 +1,5142 @@ +--- a/fs/jffs2/Kconfig ++++ b/fs/jffs2/Kconfig +@@ -139,6 +139,15 @@ config JFFS2_LZO + This feature was added in July, 2007. Say 'N' if you need + compatibility with older bootloaders or kernels. + ++config JFFS2_LZMA ++ bool "JFFS2 LZMA compression support" if JFFS2_COMPRESSION_OPTIONS ++ select LZMA_COMPRESS ++ select LZMA_DECOMPRESS ++ depends on JFFS2_FS ++ default n ++ help ++ JFFS2 wrapper to the LZMA C SDK ++ + config JFFS2_RTIME + bool "JFFS2 RTIME compression support" if JFFS2_COMPRESSION_OPTIONS + depends on JFFS2_FS +--- a/fs/jffs2/Makefile ++++ b/fs/jffs2/Makefile +@@ -18,4 +18,7 @@ jffs2-$(CONFIG_JFFS2_RUBIN) += compr_rub + jffs2-$(CONFIG_JFFS2_RTIME) += compr_rtime.o + jffs2-$(CONFIG_JFFS2_ZLIB) += compr_zlib.o + jffs2-$(CONFIG_JFFS2_LZO) += compr_lzo.o ++jffs2-$(CONFIG_JFFS2_LZMA) += compr_lzma.o + jffs2-$(CONFIG_JFFS2_SUMMARY) += summary.o ++ ++CFLAGS_compr_lzma.o += -Iinclude/linux -Ilib/lzma +--- a/fs/jffs2/compr.c ++++ b/fs/jffs2/compr.c +@@ -378,6 +378,9 @@ int __init jffs2_compressors_init(void) + #ifdef CONFIG_JFFS2_LZO + jffs2_lzo_init(); + #endif ++#ifdef CONFIG_JFFS2_LZMA ++ jffs2_lzma_init(); ++#endif + /* Setting default compression mode */ + #ifdef CONFIG_JFFS2_CMODE_NONE + jffs2_compression_mode = JFFS2_COMPR_MODE_NONE; +@@ -401,6 +404,9 @@ int __init jffs2_compressors_init(void) + int jffs2_compressors_exit(void) + { + /* Unregistering compressors */ ++#ifdef CONFIG_JFFS2_LZMA ++ jffs2_lzma_exit(); ++#endif + #ifdef CONFIG_JFFS2_LZO + jffs2_lzo_exit(); + #endif +--- a/fs/jffs2/compr.h ++++ b/fs/jffs2/compr.h +@@ -29,9 +29,9 @@ + #define JFFS2_DYNRUBIN_PRIORITY 20 + #define JFFS2_LZARI_PRIORITY 30 + #define JFFS2_RTIME_PRIORITY 50 +-#define JFFS2_ZLIB_PRIORITY 60 +-#define JFFS2_LZO_PRIORITY 80 +- ++#define JFFS2_LZMA_PRIORITY 70 ++#define JFFS2_ZLIB_PRIORITY 80 ++#define JFFS2_LZO_PRIORITY 90 + + #define JFFS2_RUBINMIPS_DISABLED /* RUBINs will be used only */ + #define JFFS2_DYNRUBIN_DISABLED /* for decompression */ +@@ -101,5 +101,9 @@ void jffs2_zlib_exit(void); + int jffs2_lzo_init(void); + void jffs2_lzo_exit(void); + #endif ++#ifdef CONFIG_JFFS2_LZMA ++int jffs2_lzma_init(void); ++void jffs2_lzma_exit(void); ++#endif + + #endif /* __JFFS2_COMPR_H__ */ +--- /dev/null ++++ b/fs/jffs2/compr_lzma.c +@@ -0,0 +1,128 @@ ++/* ++ * JFFS2 -- Journalling Flash File System, Version 2. ++ * ++ * For licensing information, see the file 'LICENCE' in this directory. ++ * ++ * JFFS2 wrapper to the LZMA C SDK ++ * ++ */ ++ ++#include ++#include "compr.h" ++ ++#ifdef __KERNEL__ ++ static DEFINE_MUTEX(deflate_mutex); ++#endif ++ ++CLzmaEncHandle *p; ++Byte propsEncoded[LZMA_PROPS_SIZE]; ++SizeT propsSize = sizeof(propsEncoded); ++ ++STATIC void lzma_free_workspace(void) ++{ ++ LzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc); ++} ++ ++STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props) ++{ ++ if ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL) ++ { ++ PRINT_ERROR("Failed to allocate lzma deflate workspace\n"); ++ return -ENOMEM; ++ } ++ ++ if (LzmaEnc_SetProps(p, props) != SZ_OK) ++ { ++ lzma_free_workspace(); ++ return -1; ++ } ++ ++ if (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK) ++ { ++ lzma_free_workspace(); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out, ++ uint32_t *sourcelen, uint32_t *dstlen) ++{ ++ SizeT compress_size = (SizeT)(*dstlen); ++ int ret; ++ ++ #ifdef __KERNEL__ ++ mutex_lock(&deflate_mutex); ++ #endif ++ ++ ret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen, ++ 0, NULL, &lzma_alloc, &lzma_alloc); ++ ++ #ifdef __KERNEL__ ++ mutex_unlock(&deflate_mutex); ++ #endif ++ ++ if (ret != SZ_OK) ++ return -1; ++ ++ *dstlen = (uint32_t)compress_size; ++ ++ return 0; ++} ++ ++STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out, ++ uint32_t srclen, uint32_t destlen) ++{ ++ int ret; ++ SizeT dl = (SizeT)destlen; ++ SizeT sl = (SizeT)srclen; ++ ELzmaStatus status; ++ ++ ret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded, ++ propsSize, LZMA_FINISH_ANY, &status, &lzma_alloc); ++ ++ if (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen) ++ return -1; ++ ++ return 0; ++} ++ ++static struct jffs2_compressor jffs2_lzma_comp = { ++ .priority = JFFS2_LZMA_PRIORITY, ++ .name = "lzma", ++ .compr = JFFS2_COMPR_LZMA, ++ .compress = &jffs2_lzma_compress, ++ .decompress = &jffs2_lzma_decompress, ++ .disabled = 0, ++}; ++ ++int INIT jffs2_lzma_init(void) ++{ ++ int ret; ++ CLzmaEncProps props; ++ LzmaEncProps_Init(&props); ++ ++ props.dictSize = LZMA_BEST_DICT(0x2000); ++ props.level = LZMA_BEST_LEVEL; ++ props.lc = LZMA_BEST_LC; ++ props.lp = LZMA_BEST_LP; ++ props.pb = LZMA_BEST_PB; ++ props.fb = LZMA_BEST_FB; ++ ++ ret = lzma_alloc_workspace(&props); ++ if (ret < 0) ++ return ret; ++ ++ ret = jffs2_register_compressor(&jffs2_lzma_comp); ++ if (ret) ++ lzma_free_workspace(); ++ ++ return ret; ++} ++ ++void jffs2_lzma_exit(void) ++{ ++ jffs2_unregister_compressor(&jffs2_lzma_comp); ++ lzma_free_workspace(); ++} +--- a/fs/jffs2/super.c ++++ b/fs/jffs2/super.c +@@ -375,14 +375,41 @@ static int __init init_jffs2_fs(void) + BUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68); + BUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32); + +- pr_info("version 2.2." ++ pr_info("version 2.2" + #ifdef CONFIG_JFFS2_FS_WRITEBUFFER + " (NAND)" + #endif + #ifdef CONFIG_JFFS2_SUMMARY +- " (SUMMARY) " ++ " (SUMMARY)" + #endif +- " © 2001-2006 Red Hat, Inc.\n"); ++#ifdef CONFIG_JFFS2_ZLIB ++ " (ZLIB)" ++#endif ++#ifdef CONFIG_JFFS2_LZO ++ " (LZO)" ++#endif ++#ifdef CONFIG_JFFS2_LZMA ++ " (LZMA)" ++#endif ++#ifdef CONFIG_JFFS2_RTIME ++ " (RTIME)" ++#endif ++#ifdef CONFIG_JFFS2_RUBIN ++ " (RUBIN)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_NONE ++ " (CMODE_NONE)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_PRIORITY ++ " (CMODE_PRIORITY)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_SIZE ++ " (CMODE_SIZE)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_FAVOURLZO ++ " (CMODE_FAVOURLZO)" ++#endif ++ " (c) 2001-2006 Red Hat, Inc.\n"); + + jffs2_inode_cachep = kmem_cache_create("jffs2_i", + sizeof(struct jffs2_inode_info), +--- a/include/uapi/linux/jffs2.h ++++ b/include/uapi/linux/jffs2.h +@@ -46,6 +46,7 @@ + #define JFFS2_COMPR_DYNRUBIN 0x05 + #define JFFS2_COMPR_ZLIB 0x06 + #define JFFS2_COMPR_LZO 0x07 ++#define JFFS2_COMPR_LZMA 0x08 + /* Compatibility flags. */ + #define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ + #define JFFS2_NODE_ACCURATE 0x2000 +--- /dev/null ++++ b/include/linux/lzma.h +@@ -0,0 +1,62 @@ ++#ifndef __LZMA_H__ ++#define __LZMA_H__ ++ ++#ifdef __KERNEL__ ++ #include ++ #include ++ #include ++ #include ++ #include ++ #define LZMA_MALLOC vmalloc ++ #define LZMA_FREE vfree ++ #define PRINT_ERROR(msg) printk(KERN_WARNING #msg) ++ #define INIT __init ++ #define STATIC static ++#else ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #ifndef PAGE_SIZE ++ extern int page_size; ++ #define PAGE_SIZE page_size ++ #endif ++ #define LZMA_MALLOC malloc ++ #define LZMA_FREE free ++ #define PRINT_ERROR(msg) fprintf(stderr, msg) ++ #define INIT ++ #define STATIC ++#endif ++ ++#include "lzma/LzmaDec.h" ++#include "lzma/LzmaEnc.h" ++ ++#define LZMA_BEST_LEVEL (9) ++#define LZMA_BEST_LC (0) ++#define LZMA_BEST_LP (0) ++#define LZMA_BEST_PB (0) ++#define LZMA_BEST_FB (273) ++ ++#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2) ++ ++static void *p_lzma_malloc(void *p, size_t size) ++{ ++ if (size == 0) ++ return NULL; ++ ++ return LZMA_MALLOC(size); ++} ++ ++static void p_lzma_free(void *p, void *address) ++{ ++ if (address != NULL) ++ LZMA_FREE(address); ++} ++ ++static ISzAlloc lzma_alloc = {p_lzma_malloc, p_lzma_free}; ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzFind.h +@@ -0,0 +1,115 @@ ++/* LzFind.h -- Match finder for LZ algorithms ++2009-04-22 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZ_FIND_H ++#define __LZ_FIND_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef UInt32 CLzRef; ++ ++typedef struct _CMatchFinder ++{ ++ Byte *buffer; ++ UInt32 pos; ++ UInt32 posLimit; ++ UInt32 streamPos; ++ UInt32 lenLimit; ++ ++ UInt32 cyclicBufferPos; ++ UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */ ++ ++ UInt32 matchMaxLen; ++ CLzRef *hash; ++ CLzRef *son; ++ UInt32 hashMask; ++ UInt32 cutValue; ++ ++ Byte *bufferBase; ++ ISeqInStream *stream; ++ int streamEndWasReached; ++ ++ UInt32 blockSize; ++ UInt32 keepSizeBefore; ++ UInt32 keepSizeAfter; ++ ++ UInt32 numHashBytes; ++ int directInput; ++ size_t directInputRem; ++ int btMode; ++ int bigHash; ++ UInt32 historySize; ++ UInt32 fixedHashSize; ++ UInt32 hashSizeSum; ++ UInt32 numSons; ++ SRes result; ++ UInt32 crc[256]; ++} CMatchFinder; ++ ++#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer) ++#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)]) ++ ++#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) ++ ++int MatchFinder_NeedMove(CMatchFinder *p); ++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p); ++void MatchFinder_MoveBlock(CMatchFinder *p); ++void MatchFinder_ReadIfRequired(CMatchFinder *p); ++ ++void MatchFinder_Construct(CMatchFinder *p); ++ ++/* Conditions: ++ historySize <= 3 GB ++ keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB ++*/ ++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, ++ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, ++ ISzAlloc *alloc); ++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); ++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems); ++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue); ++ ++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, ++ UInt32 *distances, UInt32 maxLen); ++ ++/* ++Conditions: ++ Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func. ++ Mf_GetPointerToCurrentPos_Func's result must be used only before any other function ++*/ ++ ++typedef void (*Mf_Init_Func)(void *object); ++typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index); ++typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object); ++typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object); ++typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances); ++typedef void (*Mf_Skip_Func)(void *object, UInt32); ++ ++typedef struct _IMatchFinder ++{ ++ Mf_Init_Func Init; ++ Mf_GetIndexByte_Func GetIndexByte; ++ Mf_GetNumAvailableBytes_Func GetNumAvailableBytes; ++ Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos; ++ Mf_GetMatches_Func GetMatches; ++ Mf_Skip_Func Skip; ++} IMatchFinder; ++ ++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); ++ ++void MatchFinder_Init(CMatchFinder *p); ++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); ++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); ++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); ++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzHash.h +@@ -0,0 +1,54 @@ ++/* LzHash.h -- HASH functions for LZ algorithms ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZ_HASH_H ++#define __LZ_HASH_H ++ ++#define kHash2Size (1 << 10) ++#define kHash3Size (1 << 16) ++#define kHash4Size (1 << 20) ++ ++#define kFix3HashSize (kHash2Size) ++#define kFix4HashSize (kHash2Size + kHash3Size) ++#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size) ++ ++#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8); ++ ++#define HASH3_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; } ++ ++#define HASH4_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; } ++ ++#define HASH5_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \ ++ hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \ ++ hash4Value &= (kHash4Size - 1); } ++ ++/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */ ++#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF; ++ ++ ++#define MT_HASH2_CALC \ ++ hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1); ++ ++#define MT_HASH3_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); } ++ ++#define MT_HASH4_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); } ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzmaDec.h +@@ -0,0 +1,231 @@ ++/* LzmaDec.h -- LZMA Decoder ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZMA_DEC_H ++#define __LZMA_DEC_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* #define _LZMA_PROB32 */ ++/* _LZMA_PROB32 can increase the speed on some CPUs, ++ but memory usage for CLzmaDec::probs will be doubled in that case */ ++ ++#ifdef _LZMA_PROB32 ++#define CLzmaProb UInt32 ++#else ++#define CLzmaProb UInt16 ++#endif ++ ++ ++/* ---------- LZMA Properties ---------- */ ++ ++#define LZMA_PROPS_SIZE 5 ++ ++typedef struct _CLzmaProps ++{ ++ unsigned lc, lp, pb; ++ UInt32 dicSize; ++} CLzmaProps; ++ ++/* LzmaProps_Decode - decodes properties ++Returns: ++ SZ_OK ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++*/ ++ ++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); ++ ++ ++/* ---------- LZMA Decoder state ---------- */ ++ ++/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case. ++ Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */ ++ ++#define LZMA_REQUIRED_INPUT_MAX 20 ++ ++typedef struct ++{ ++ CLzmaProps prop; ++ CLzmaProb *probs; ++ Byte *dic; ++ const Byte *buf; ++ UInt32 range, code; ++ SizeT dicPos; ++ SizeT dicBufSize; ++ UInt32 processedPos; ++ UInt32 checkDicSize; ++ unsigned state; ++ UInt32 reps[4]; ++ unsigned remainLen; ++ int needFlush; ++ int needInitState; ++ UInt32 numProbs; ++ unsigned tempBufSize; ++ Byte tempBuf[LZMA_REQUIRED_INPUT_MAX]; ++} CLzmaDec; ++ ++#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } ++ ++void LzmaDec_Init(CLzmaDec *p); ++ ++/* There are two types of LZMA streams: ++ 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. ++ 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ ++ ++typedef enum ++{ ++ LZMA_FINISH_ANY, /* finish at any point */ ++ LZMA_FINISH_END /* block must be finished at the end */ ++} ELzmaFinishMode; ++ ++/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!! ++ ++ You must use LZMA_FINISH_END, when you know that current output buffer ++ covers last bytes of block. In other cases you must use LZMA_FINISH_ANY. ++ ++ If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK, ++ and output value of destLen will be less than output buffer size limit. ++ You can check status result also. ++ ++ You can use multiple checks to test data integrity after full decompression: ++ 1) Check Result and "status" variable. ++ 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize. ++ 3) Check that output(srcLen) = compressedSize, if you know real compressedSize. ++ You must use correct finish mode in that case. */ ++ ++typedef enum ++{ ++ LZMA_STATUS_NOT_SPECIFIED, /* use main error code instead */ ++ LZMA_STATUS_FINISHED_WITH_MARK, /* stream was finished with end mark. */ ++ LZMA_STATUS_NOT_FINISHED, /* stream was not finished */ ++ LZMA_STATUS_NEEDS_MORE_INPUT, /* you must provide more input bytes */ ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK /* there is probability that stream was finished without end mark */ ++} ELzmaStatus; ++ ++/* ELzmaStatus is used only as output value for function call */ ++ ++ ++/* ---------- Interfaces ---------- */ ++ ++/* There are 3 levels of interfaces: ++ 1) Dictionary Interface ++ 2) Buffer Interface ++ 3) One Call Interface ++ You can select any of these interfaces, but don't mix functions from different ++ groups for same object. */ ++ ++ ++/* There are two variants to allocate state for Dictionary Interface: ++ 1) LzmaDec_Allocate / LzmaDec_Free ++ 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs ++ You can use variant 2, if you set dictionary buffer manually. ++ For Buffer Interface you must always use variant 1. ++ ++LzmaDec_Allocate* can return: ++ SZ_OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++*/ ++ ++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); ++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); ++ ++SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); ++void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); ++ ++/* ---------- Dictionary Interface ---------- */ ++ ++/* You can use it, if you want to eliminate the overhead for data copying from ++ dictionary to some other external buffer. ++ You must work with CLzmaDec variables directly in this interface. ++ ++ STEPS: ++ LzmaDec_Constr() ++ LzmaDec_Allocate() ++ for (each new stream) ++ { ++ LzmaDec_Init() ++ while (it needs more decompression) ++ { ++ LzmaDec_DecodeToDic() ++ use data from CLzmaDec::dic and update CLzmaDec::dicPos ++ } ++ } ++ LzmaDec_Free() ++*/ ++ ++/* LzmaDec_DecodeToDic ++ ++ The decoding to internal dictionary buffer (CLzmaDec::dic). ++ You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (dicLimit). ++ LZMA_FINISH_ANY - Decode just dicLimit bytes. ++ LZMA_FINISH_END - Stream must be finished after dicLimit. ++ ++Returns: ++ SZ_OK ++ status: ++ LZMA_STATUS_FINISHED_WITH_MARK ++ LZMA_STATUS_NOT_FINISHED ++ LZMA_STATUS_NEEDS_MORE_INPUT ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK ++ SZ_ERROR_DATA - Data error ++*/ ++ ++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, ++ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); ++ ++ ++/* ---------- Buffer Interface ---------- */ ++ ++/* It's zlib-like interface. ++ See LzmaDec_DecodeToDic description for information about STEPS and return results, ++ but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need ++ to work with CLzmaDec variables manually. ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (*destLen). ++ LZMA_FINISH_ANY - Decode just destLen bytes. ++ LZMA_FINISH_END - Stream must be finished after (*destLen). ++*/ ++ ++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, ++ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); ++ ++ ++/* ---------- One Call Interface ---------- */ ++ ++/* LzmaDecode ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (*destLen). ++ LZMA_FINISH_ANY - Decode just destLen bytes. ++ LZMA_FINISH_END - Stream must be finished after (*destLen). ++ ++Returns: ++ SZ_OK ++ status: ++ LZMA_STATUS_FINISHED_WITH_MARK ++ LZMA_STATUS_NOT_FINISHED ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK ++ SZ_ERROR_DATA - Data error ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++ SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src). ++*/ ++ ++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ++ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, ++ ELzmaStatus *status, ISzAlloc *alloc); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzmaEnc.h +@@ -0,0 +1,80 @@ ++/* LzmaEnc.h -- LZMA Encoder ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZMA_ENC_H ++#define __LZMA_ENC_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define LZMA_PROPS_SIZE 5 ++ ++typedef struct _CLzmaEncProps ++{ ++ int level; /* 0 <= level <= 9 */ ++ UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version ++ (1 << 12) <= dictSize <= (1 << 30) for 64-bit version ++ default = (1 << 24) */ ++ int lc; /* 0 <= lc <= 8, default = 3 */ ++ int lp; /* 0 <= lp <= 4, default = 0 */ ++ int pb; /* 0 <= pb <= 4, default = 2 */ ++ int algo; /* 0 - fast, 1 - normal, default = 1 */ ++ int fb; /* 5 <= fb <= 273, default = 32 */ ++ int btMode; /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */ ++ int numHashBytes; /* 2, 3 or 4, default = 4 */ ++ UInt32 mc; /* 1 <= mc <= (1 << 30), default = 32 */ ++ unsigned writeEndMark; /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */ ++ int numThreads; /* 1 or 2, default = 2 */ ++} CLzmaEncProps; ++ ++void LzmaEncProps_Init(CLzmaEncProps *p); ++void LzmaEncProps_Normalize(CLzmaEncProps *p); ++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2); ++ ++ ++/* ---------- CLzmaEncHandle Interface ---------- */ ++ ++/* LzmaEnc_* functions can return the following exit codes: ++Returns: ++ SZ_OK - OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_PARAM - Incorrect paramater in props ++ SZ_ERROR_WRITE - Write callback error. ++ SZ_ERROR_PROGRESS - some break from progress callback ++ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) ++*/ ++ ++typedef void * CLzmaEncHandle; ++ ++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc); ++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); ++SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); ++SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); ++SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++ ++/* ---------- One Call Interface ---------- */ ++ ++/* LzmaEncode ++Return code: ++ SZ_OK - OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_PARAM - Incorrect paramater ++ SZ_ERROR_OUTPUT_EOF - output buffer overflow ++ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) ++*/ ++ ++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/Types.h +@@ -0,0 +1,226 @@ ++/* Types.h -- Basic types ++2009-11-23 : Igor Pavlov : Public domain */ ++ ++#ifndef __7Z_TYPES_H ++#define __7Z_TYPES_H ++ ++#include ++ ++#ifdef _WIN32 ++#include ++#endif ++ ++#ifndef EXTERN_C_BEGIN ++#ifdef __cplusplus ++#define EXTERN_C_BEGIN extern "C" { ++#define EXTERN_C_END } ++#else ++#define EXTERN_C_BEGIN ++#define EXTERN_C_END ++#endif ++#endif ++ ++EXTERN_C_BEGIN ++ ++#define SZ_OK 0 ++ ++#define SZ_ERROR_DATA 1 ++#define SZ_ERROR_MEM 2 ++#define SZ_ERROR_CRC 3 ++#define SZ_ERROR_UNSUPPORTED 4 ++#define SZ_ERROR_PARAM 5 ++#define SZ_ERROR_INPUT_EOF 6 ++#define SZ_ERROR_OUTPUT_EOF 7 ++#define SZ_ERROR_READ 8 ++#define SZ_ERROR_WRITE 9 ++#define SZ_ERROR_PROGRESS 10 ++#define SZ_ERROR_FAIL 11 ++#define SZ_ERROR_THREAD 12 ++ ++#define SZ_ERROR_ARCHIVE 16 ++#define SZ_ERROR_NO_ARCHIVE 17 ++ ++typedef int SRes; ++ ++#ifdef _WIN32 ++typedef DWORD WRes; ++#else ++typedef int WRes; ++#endif ++ ++#ifndef RINOK ++#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; } ++#endif ++ ++typedef unsigned char Byte; ++typedef short Int16; ++typedef unsigned short UInt16; ++ ++#ifdef _LZMA_UINT32_IS_ULONG ++typedef long Int32; ++typedef unsigned long UInt32; ++#else ++typedef int Int32; ++typedef unsigned int UInt32; ++#endif ++ ++#ifdef _SZ_NO_INT_64 ++ ++/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers. ++ NOTES: Some code will work incorrectly in that case! */ ++ ++typedef long Int64; ++typedef unsigned long UInt64; ++ ++#else ++ ++#if defined(_MSC_VER) || defined(__BORLANDC__) ++typedef __int64 Int64; ++typedef unsigned __int64 UInt64; ++#else ++typedef long long int Int64; ++typedef unsigned long long int UInt64; ++#endif ++ ++#endif ++ ++#ifdef _LZMA_NO_SYSTEM_SIZE_T ++typedef UInt32 SizeT; ++#else ++typedef size_t SizeT; ++#endif ++ ++typedef int Bool; ++#define True 1 ++#define False 0 ++ ++ ++#ifdef _WIN32 ++#define MY_STD_CALL __stdcall ++#else ++#define MY_STD_CALL ++#endif ++ ++#ifdef _MSC_VER ++ ++#if _MSC_VER >= 1300 ++#define MY_NO_INLINE __declspec(noinline) ++#else ++#define MY_NO_INLINE ++#endif ++ ++#define MY_CDECL __cdecl ++#define MY_FAST_CALL __fastcall ++ ++#else ++ ++#define MY_CDECL ++#define MY_FAST_CALL ++ ++#endif ++ ++ ++/* The following interfaces use first parameter as pointer to structure */ ++ ++typedef struct ++{ ++ SRes (*Read)(void *p, void *buf, size_t *size); ++ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. ++ (output(*size) < input(*size)) is allowed */ ++} ISeqInStream; ++ ++/* it can return SZ_ERROR_INPUT_EOF */ ++SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size); ++SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType); ++SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf); ++ ++typedef struct ++{ ++ size_t (*Write)(void *p, const void *buf, size_t size); ++ /* Returns: result - the number of actually written bytes. ++ (result < size) means error */ ++} ISeqOutStream; ++ ++typedef enum ++{ ++ SZ_SEEK_SET = 0, ++ SZ_SEEK_CUR = 1, ++ SZ_SEEK_END = 2 ++} ESzSeek; ++ ++typedef struct ++{ ++ SRes (*Read)(void *p, void *buf, size_t *size); /* same as ISeqInStream::Read */ ++ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); ++} ISeekInStream; ++ ++typedef struct ++{ ++ SRes (*Look)(void *p, void **buf, size_t *size); ++ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. ++ (output(*size) > input(*size)) is not allowed ++ (output(*size) < input(*size)) is allowed */ ++ SRes (*Skip)(void *p, size_t offset); ++ /* offset must be <= output(*size) of Look */ ++ ++ SRes (*Read)(void *p, void *buf, size_t *size); ++ /* reads directly (without buffer). It's same as ISeqInStream::Read */ ++ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); ++} ILookInStream; ++ ++SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size); ++SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset); ++ ++/* reads via ILookInStream::Read */ ++SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType); ++SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size); ++ ++#define LookToRead_BUF_SIZE (1 << 14) ++ ++typedef struct ++{ ++ ILookInStream s; ++ ISeekInStream *realStream; ++ size_t pos; ++ size_t size; ++ Byte buf[LookToRead_BUF_SIZE]; ++} CLookToRead; ++ ++void LookToRead_CreateVTable(CLookToRead *p, int lookahead); ++void LookToRead_Init(CLookToRead *p); ++ ++typedef struct ++{ ++ ISeqInStream s; ++ ILookInStream *realStream; ++} CSecToLook; ++ ++void SecToLook_CreateVTable(CSecToLook *p); ++ ++typedef struct ++{ ++ ISeqInStream s; ++ ILookInStream *realStream; ++} CSecToRead; ++ ++void SecToRead_CreateVTable(CSecToRead *p); ++ ++typedef struct ++{ ++ SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize); ++ /* Returns: result. (result != SZ_OK) means break. ++ Value (UInt64)(Int64)-1 for size means unknown value. */ ++} ICompressProgress; ++ ++typedef struct ++{ ++ void *(*Alloc)(void *p, size_t size); ++ void (*Free)(void *p, void *address); /* address can be 0 */ ++} ISzAlloc; ++ ++#define IAlloc_Alloc(p, size) (p)->Alloc((p), size) ++#define IAlloc_Free(p, a) (p)->Free((p), a) ++ ++EXTERN_C_END ++ ++#endif +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -235,6 +235,12 @@ config LZ4_DECOMPRESS + + source "lib/xz/Kconfig" + ++config LZMA_COMPRESS ++ tristate ++ ++config LZMA_DECOMPRESS ++ tristate ++ + # + # These all provide a common interface (hence the apparent duplication with + # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -2,6 +2,16 @@ + # Makefile for some libs needed in the kernel. + # + ++ifdef CONFIG_JFFS2_ZLIB ++ CONFIG_ZLIB_INFLATE:=y ++ CONFIG_ZLIB_DEFLATE:=y ++endif ++ ++ifdef CONFIG_JFFS2_LZMA ++ CONFIG_LZMA_DECOMPRESS:=y ++ CONFIG_LZMA_COMPRESS:=y ++endif ++ + ifdef CONFIG_FUNCTION_TRACER + ORIG_CFLAGS := $(KBUILD_CFLAGS) + KBUILD_CFLAGS = $(subst $(CC_FLAGS_FTRACE),,$(ORIG_CFLAGS)) +@@ -89,6 +99,8 @@ obj-$(CONFIG_LZ4HC_COMPRESS) += lz4/ + obj-$(CONFIG_LZ4_DECOMPRESS) += lz4/ + obj-$(CONFIG_XZ_DEC) += xz/ + obj-$(CONFIG_RAID6_PQ) += raid6/ ++obj-$(CONFIG_LZMA_COMPRESS) += lzma/ ++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ + + lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o + lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o +--- /dev/null ++++ b/lib/lzma/LzFind.c +@@ -0,0 +1,761 @@ ++/* LzFind.c -- Match finder for LZ algorithms ++2009-04-22 : Igor Pavlov : Public domain */ ++ ++#include ++ ++#include "LzFind.h" ++#include "LzHash.h" ++ ++#define kEmptyHashValue 0 ++#define kMaxValForNormalize ((UInt32)0xFFFFFFFF) ++#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */ ++#define kNormalizeMask (~(kNormalizeStepMin - 1)) ++#define kMaxHistorySize ((UInt32)3 << 30) ++ ++#define kStartMaxLen 3 ++ ++static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ if (!p->directInput) ++ { ++ alloc->Free(alloc, p->bufferBase); ++ p->bufferBase = 0; ++ } ++} ++ ++/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */ ++ ++static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) ++{ ++ UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; ++ if (p->directInput) ++ { ++ p->blockSize = blockSize; ++ return 1; ++ } ++ if (p->bufferBase == 0 || p->blockSize != blockSize) ++ { ++ LzInWindow_Free(p, alloc); ++ p->blockSize = blockSize; ++ p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize); ++ } ++ return (p->bufferBase != 0); ++} ++ ++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } ++Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } ++ ++UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } ++ ++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) ++{ ++ p->posLimit -= subValue; ++ p->pos -= subValue; ++ p->streamPos -= subValue; ++} ++ ++static void MatchFinder_ReadBlock(CMatchFinder *p) ++{ ++ if (p->streamEndWasReached || p->result != SZ_OK) ++ return; ++ if (p->directInput) ++ { ++ UInt32 curSize = 0xFFFFFFFF - p->streamPos; ++ if (curSize > p->directInputRem) ++ curSize = (UInt32)p->directInputRem; ++ p->directInputRem -= curSize; ++ p->streamPos += curSize; ++ if (p->directInputRem == 0) ++ p->streamEndWasReached = 1; ++ return; ++ } ++ for (;;) ++ { ++ Byte *dest = p->buffer + (p->streamPos - p->pos); ++ size_t size = (p->bufferBase + p->blockSize - dest); ++ if (size == 0) ++ return; ++ p->result = p->stream->Read(p->stream, dest, &size); ++ if (p->result != SZ_OK) ++ return; ++ if (size == 0) ++ { ++ p->streamEndWasReached = 1; ++ return; ++ } ++ p->streamPos += (UInt32)size; ++ if (p->streamPos - p->pos > p->keepSizeAfter) ++ return; ++ } ++} ++ ++void MatchFinder_MoveBlock(CMatchFinder *p) ++{ ++ memmove(p->bufferBase, ++ p->buffer - p->keepSizeBefore, ++ (size_t)(p->streamPos - p->pos + p->keepSizeBefore)); ++ p->buffer = p->bufferBase + p->keepSizeBefore; ++} ++ ++int MatchFinder_NeedMove(CMatchFinder *p) ++{ ++ if (p->directInput) ++ return 0; ++ /* if (p->streamEndWasReached) return 0; */ ++ return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); ++} ++ ++void MatchFinder_ReadIfRequired(CMatchFinder *p) ++{ ++ if (p->streamEndWasReached) ++ return; ++ if (p->keepSizeAfter >= p->streamPos - p->pos) ++ MatchFinder_ReadBlock(p); ++} ++ ++static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) ++{ ++ if (MatchFinder_NeedMove(p)) ++ MatchFinder_MoveBlock(p); ++ MatchFinder_ReadBlock(p); ++} ++ ++static void MatchFinder_SetDefaultSettings(CMatchFinder *p) ++{ ++ p->cutValue = 32; ++ p->btMode = 1; ++ p->numHashBytes = 4; ++ p->bigHash = 0; ++} ++ ++#define kCrcPoly 0xEDB88320 ++ ++void MatchFinder_Construct(CMatchFinder *p) ++{ ++ UInt32 i; ++ p->bufferBase = 0; ++ p->directInput = 0; ++ p->hash = 0; ++ MatchFinder_SetDefaultSettings(p); ++ ++ for (i = 0; i < 256; i++) ++ { ++ UInt32 r = i; ++ int j; ++ for (j = 0; j < 8; j++) ++ r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1)); ++ p->crc[i] = r; ++ } ++} ++ ++static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->hash); ++ p->hash = 0; ++} ++ ++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ MatchFinder_FreeThisClassMemory(p, alloc); ++ LzInWindow_Free(p, alloc); ++} ++ ++static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc) ++{ ++ size_t sizeInBytes = (size_t)num * sizeof(CLzRef); ++ if (sizeInBytes / sizeof(CLzRef) != num) ++ return 0; ++ return (CLzRef *)alloc->Alloc(alloc, sizeInBytes); ++} ++ ++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, ++ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, ++ ISzAlloc *alloc) ++{ ++ UInt32 sizeReserv; ++ if (historySize > kMaxHistorySize) ++ { ++ MatchFinder_Free(p, alloc); ++ return 0; ++ } ++ sizeReserv = historySize >> 1; ++ if (historySize > ((UInt32)2 << 30)) ++ sizeReserv = historySize >> 2; ++ sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19); ++ ++ p->keepSizeBefore = historySize + keepAddBufferBefore + 1; ++ p->keepSizeAfter = matchMaxLen + keepAddBufferAfter; ++ /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */ ++ if (LzInWindow_Create(p, sizeReserv, alloc)) ++ { ++ UInt32 newCyclicBufferSize = historySize + 1; ++ UInt32 hs; ++ p->matchMaxLen = matchMaxLen; ++ { ++ p->fixedHashSize = 0; ++ if (p->numHashBytes == 2) ++ hs = (1 << 16) - 1; ++ else ++ { ++ hs = historySize - 1; ++ hs |= (hs >> 1); ++ hs |= (hs >> 2); ++ hs |= (hs >> 4); ++ hs |= (hs >> 8); ++ hs >>= 1; ++ hs |= 0xFFFF; /* don't change it! It's required for Deflate */ ++ if (hs > (1 << 24)) ++ { ++ if (p->numHashBytes == 3) ++ hs = (1 << 24) - 1; ++ else ++ hs >>= 1; ++ } ++ } ++ p->hashMask = hs; ++ hs++; ++ if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size; ++ if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size; ++ if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size; ++ hs += p->fixedHashSize; ++ } ++ ++ { ++ UInt32 prevSize = p->hashSizeSum + p->numSons; ++ UInt32 newSize; ++ p->historySize = historySize; ++ p->hashSizeSum = hs; ++ p->cyclicBufferSize = newCyclicBufferSize; ++ p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize); ++ newSize = p->hashSizeSum + p->numSons; ++ if (p->hash != 0 && prevSize == newSize) ++ return 1; ++ MatchFinder_FreeThisClassMemory(p, alloc); ++ p->hash = AllocRefs(newSize, alloc); ++ if (p->hash != 0) ++ { ++ p->son = p->hash + p->hashSizeSum; ++ return 1; ++ } ++ } ++ } ++ MatchFinder_Free(p, alloc); ++ return 0; ++} ++ ++static void MatchFinder_SetLimits(CMatchFinder *p) ++{ ++ UInt32 limit = kMaxValForNormalize - p->pos; ++ UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos; ++ if (limit2 < limit) ++ limit = limit2; ++ limit2 = p->streamPos - p->pos; ++ if (limit2 <= p->keepSizeAfter) ++ { ++ if (limit2 > 0) ++ limit2 = 1; ++ } ++ else ++ limit2 -= p->keepSizeAfter; ++ if (limit2 < limit) ++ limit = limit2; ++ { ++ UInt32 lenLimit = p->streamPos - p->pos; ++ if (lenLimit > p->matchMaxLen) ++ lenLimit = p->matchMaxLen; ++ p->lenLimit = lenLimit; ++ } ++ p->posLimit = p->pos + limit; ++} ++ ++void MatchFinder_Init(CMatchFinder *p) ++{ ++ UInt32 i; ++ for (i = 0; i < p->hashSizeSum; i++) ++ p->hash[i] = kEmptyHashValue; ++ p->cyclicBufferPos = 0; ++ p->buffer = p->bufferBase; ++ p->pos = p->streamPos = p->cyclicBufferSize; ++ p->result = SZ_OK; ++ p->streamEndWasReached = 0; ++ MatchFinder_ReadBlock(p); ++ MatchFinder_SetLimits(p); ++} ++ ++static UInt32 MatchFinder_GetSubValue(CMatchFinder *p) ++{ ++ return (p->pos - p->historySize - 1) & kNormalizeMask; ++} ++ ++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) ++{ ++ UInt32 i; ++ for (i = 0; i < numItems; i++) ++ { ++ UInt32 value = items[i]; ++ if (value <= subValue) ++ value = kEmptyHashValue; ++ else ++ value -= subValue; ++ items[i] = value; ++ } ++} ++ ++static void MatchFinder_Normalize(CMatchFinder *p) ++{ ++ UInt32 subValue = MatchFinder_GetSubValue(p); ++ MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons); ++ MatchFinder_ReduceOffsets(p, subValue); ++} ++ ++static void MatchFinder_CheckLimits(CMatchFinder *p) ++{ ++ if (p->pos == kMaxValForNormalize) ++ MatchFinder_Normalize(p); ++ if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos) ++ MatchFinder_CheckAndMoveAndRead(p); ++ if (p->cyclicBufferPos == p->cyclicBufferSize) ++ p->cyclicBufferPos = 0; ++ MatchFinder_SetLimits(p); ++} ++ ++static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, ++ UInt32 *distances, UInt32 maxLen) ++{ ++ son[_cyclicBufferPos] = curMatch; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ return distances; ++ { ++ const Byte *pb = cur - delta; ++ curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)]; ++ if (pb[maxLen] == cur[maxLen] && *pb == *cur) ++ { ++ UInt32 len = 0; ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ if (maxLen < len) ++ { ++ *distances++ = maxLen = len; ++ *distances++ = delta - 1; ++ if (len == lenLimit) ++ return distances; ++ } ++ } ++ } ++ } ++} ++ ++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, ++ UInt32 *distances, UInt32 maxLen) ++{ ++ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; ++ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); ++ UInt32 len0 = 0, len1 = 0; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ { ++ *ptr0 = *ptr1 = kEmptyHashValue; ++ return distances; ++ } ++ { ++ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); ++ const Byte *pb = cur - delta; ++ UInt32 len = (len0 < len1 ? len0 : len1); ++ if (pb[len] == cur[len]) ++ { ++ if (++len != lenLimit && pb[len] == cur[len]) ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ if (maxLen < len) ++ { ++ *distances++ = maxLen = len; ++ *distances++ = delta - 1; ++ if (len == lenLimit) ++ { ++ *ptr1 = pair[0]; ++ *ptr0 = pair[1]; ++ return distances; ++ } ++ } ++ } ++ if (pb[len] < cur[len]) ++ { ++ *ptr1 = curMatch; ++ ptr1 = pair + 1; ++ curMatch = *ptr1; ++ len1 = len; ++ } ++ else ++ { ++ *ptr0 = curMatch; ++ ptr0 = pair; ++ curMatch = *ptr0; ++ len0 = len; ++ } ++ } ++ } ++} ++ ++static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue) ++{ ++ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; ++ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); ++ UInt32 len0 = 0, len1 = 0; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ { ++ *ptr0 = *ptr1 = kEmptyHashValue; ++ return; ++ } ++ { ++ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); ++ const Byte *pb = cur - delta; ++ UInt32 len = (len0 < len1 ? len0 : len1); ++ if (pb[len] == cur[len]) ++ { ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ { ++ if (len == lenLimit) ++ { ++ *ptr1 = pair[0]; ++ *ptr0 = pair[1]; ++ return; ++ } ++ } ++ } ++ if (pb[len] < cur[len]) ++ { ++ *ptr1 = curMatch; ++ ptr1 = pair + 1; ++ curMatch = *ptr1; ++ len1 = len; ++ } ++ else ++ { ++ *ptr0 = curMatch; ++ ptr0 = pair; ++ curMatch = *ptr0; ++ len0 = len; ++ } ++ } ++ } ++} ++ ++#define MOVE_POS \ ++ ++p->cyclicBufferPos; \ ++ p->buffer++; \ ++ if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); ++ ++#define MOVE_POS_RET MOVE_POS return offset; ++ ++static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } ++ ++#define GET_MATCHES_HEADER2(minLen, ret_op) \ ++ UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ ++ lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ ++ cur = p->buffer; ++ ++#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0) ++#define SKIP_HEADER(minLen) GET_MATCHES_HEADER2(minLen, continue) ++ ++#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue ++ ++#define GET_MATCHES_FOOTER(offset, maxLen) \ ++ offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \ ++ distances + offset, maxLen) - distances); MOVE_POS_RET; ++ ++#define SKIP_FOOTER \ ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS; ++ ++static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(2) ++ HASH2_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = 0; ++ GET_MATCHES_FOOTER(offset, 1) ++} ++ ++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = 0; ++ GET_MATCHES_FOOTER(offset, 2) ++} ++ ++static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, delta2, maxLen, offset; ++ GET_MATCHES_HEADER(3) ++ ++ HASH3_CALC; ++ ++ delta2 = p->pos - p->hash[hash2Value]; ++ curMatch = p->hash[kFix3HashSize + hashValue]; ++ ++ p->hash[hash2Value] = ++ p->hash[kFix3HashSize + hashValue] = p->pos; ++ ++ ++ maxLen = 2; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[0] = maxLen; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ if (maxLen == lenLimit) ++ { ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); ++ MOVE_POS_RET; ++ } ++ } ++ GET_MATCHES_FOOTER(offset, maxLen) ++} ++ ++static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; ++ GET_MATCHES_HEADER(4) ++ ++ HASH4_CALC; ++ ++ delta2 = p->pos - p->hash[ hash2Value]; ++ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ ++ maxLen = 1; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ distances[0] = maxLen = 2; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ } ++ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) ++ { ++ maxLen = 3; ++ distances[offset + 1] = delta3 - 1; ++ offset += 2; ++ delta2 = delta3; ++ } ++ if (offset != 0) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[offset - 2] = maxLen; ++ if (maxLen == lenLimit) ++ { ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); ++ MOVE_POS_RET; ++ } ++ } ++ if (maxLen < 3) ++ maxLen = 3; ++ GET_MATCHES_FOOTER(offset, maxLen) ++} ++ ++static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; ++ GET_MATCHES_HEADER(4) ++ ++ HASH4_CALC; ++ ++ delta2 = p->pos - p->hash[ hash2Value]; ++ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ ++ maxLen = 1; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ distances[0] = maxLen = 2; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ } ++ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) ++ { ++ maxLen = 3; ++ distances[offset + 1] = delta3 - 1; ++ offset += 2; ++ delta2 = delta3; ++ } ++ if (offset != 0) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[offset - 2] = maxLen; ++ if (maxLen == lenLimit) ++ { ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS_RET; ++ } ++ } ++ if (maxLen < 3) ++ maxLen = 3; ++ offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), ++ distances + offset, maxLen) - (distances)); ++ MOVE_POS_RET ++} ++ ++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), ++ distances, 2) - (distances)); ++ MOVE_POS_RET ++} ++ ++static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(2) ++ HASH2_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value; ++ SKIP_HEADER(3) ++ HASH3_CALC; ++ curMatch = p->hash[kFix3HashSize + hashValue]; ++ p->hash[hash2Value] = ++ p->hash[kFix3HashSize + hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value, hash3Value; ++ SKIP_HEADER(4) ++ HASH4_CALC; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = p->pos; ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value, hash3Value; ++ SKIP_HEADER(4) ++ HASH4_CALC; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS ++ } ++ while (--num != 0); ++} ++ ++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS ++ } ++ while (--num != 0); ++} ++ ++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) ++{ ++ vTable->Init = (Mf_Init_Func)MatchFinder_Init; ++ vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; ++ vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; ++ vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; ++ if (!p->btMode) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip; ++ } ++ else if (p->numHashBytes == 2) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip; ++ } ++ else if (p->numHashBytes == 3) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip; ++ } ++ else ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; ++ } ++} +--- /dev/null ++++ b/lib/lzma/LzmaDec.c +@@ -0,0 +1,999 @@ ++/* LzmaDec.c -- LZMA Decoder ++2009-09-20 : Igor Pavlov : Public domain */ ++ ++#include "LzmaDec.h" ++ ++#include ++ ++#define kNumTopBits 24 ++#define kTopValue ((UInt32)1 << kNumTopBits) ++ ++#define kNumBitModelTotalBits 11 ++#define kBitModelTotal (1 << kNumBitModelTotalBits) ++#define kNumMoveBits 5 ++ ++#define RC_INIT_SIZE 5 ++ ++#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); } ++ ++#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) ++#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits)); ++#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits)); ++#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \ ++ { UPDATE_0(p); i = (i + i); A0; } else \ ++ { UPDATE_1(p); i = (i + i) + 1; A1; } ++#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;) ++ ++#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); } ++#define TREE_DECODE(probs, limit, i) \ ++ { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; } ++ ++/* #define _LZMA_SIZE_OPT */ ++ ++#ifdef _LZMA_SIZE_OPT ++#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i) ++#else ++#define TREE_6_DECODE(probs, i) \ ++ { i = 1; \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ i -= 0x40; } ++#endif ++ ++#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); } ++ ++#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) ++#define UPDATE_0_CHECK range = bound; ++#define UPDATE_1_CHECK range -= bound; code -= bound; ++#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \ ++ { UPDATE_0_CHECK; i = (i + i); A0; } else \ ++ { UPDATE_1_CHECK; i = (i + i) + 1; A1; } ++#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;) ++#define TREE_DECODE_CHECK(probs, limit, i) \ ++ { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; } ++ ++ ++#define kNumPosBitsMax 4 ++#define kNumPosStatesMax (1 << kNumPosBitsMax) ++ ++#define kLenNumLowBits 3 ++#define kLenNumLowSymbols (1 << kLenNumLowBits) ++#define kLenNumMidBits 3 ++#define kLenNumMidSymbols (1 << kLenNumMidBits) ++#define kLenNumHighBits 8 ++#define kLenNumHighSymbols (1 << kLenNumHighBits) ++ ++#define LenChoice 0 ++#define LenChoice2 (LenChoice + 1) ++#define LenLow (LenChoice2 + 1) ++#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) ++#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) ++#define kNumLenProbs (LenHigh + kLenNumHighSymbols) ++ ++ ++#define kNumStates 12 ++#define kNumLitStates 7 ++ ++#define kStartPosModelIndex 4 ++#define kEndPosModelIndex 14 ++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) ++ ++#define kNumPosSlotBits 6 ++#define kNumLenToPosStates 4 ++ ++#define kNumAlignBits 4 ++#define kAlignTableSize (1 << kNumAlignBits) ++ ++#define kMatchMinLen 2 ++#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) ++ ++#define IsMatch 0 ++#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) ++#define IsRepG0 (IsRep + kNumStates) ++#define IsRepG1 (IsRepG0 + kNumStates) ++#define IsRepG2 (IsRepG1 + kNumStates) ++#define IsRep0Long (IsRepG2 + kNumStates) ++#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) ++#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) ++#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) ++#define LenCoder (Align + kAlignTableSize) ++#define RepLenCoder (LenCoder + kNumLenProbs) ++#define Literal (RepLenCoder + kNumLenProbs) ++ ++#define LZMA_BASE_SIZE 1846 ++#define LZMA_LIT_SIZE 768 ++ ++#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp))) ++ ++#if Literal != LZMA_BASE_SIZE ++StopCompilingDueBUG ++#endif ++ ++#define LZMA_DIC_MIN (1 << 12) ++ ++/* First LZMA-symbol is always decoded. ++And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization ++Out: ++ Result: ++ SZ_OK - OK ++ SZ_ERROR_DATA - Error ++ p->remainLen: ++ < kMatchSpecLenStart : normal remain ++ = kMatchSpecLenStart : finished ++ = kMatchSpecLenStart + 1 : Flush marker ++ = kMatchSpecLenStart + 2 : State Init Marker ++*/ ++ ++static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit) ++{ ++ CLzmaProb *probs = p->probs; ++ ++ unsigned state = p->state; ++ UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3]; ++ unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1; ++ unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1; ++ unsigned lc = p->prop.lc; ++ ++ Byte *dic = p->dic; ++ SizeT dicBufSize = p->dicBufSize; ++ SizeT dicPos = p->dicPos; ++ ++ UInt32 processedPos = p->processedPos; ++ UInt32 checkDicSize = p->checkDicSize; ++ unsigned len = 0; ++ ++ const Byte *buf = p->buf; ++ UInt32 range = p->range; ++ UInt32 code = p->code; ++ ++ do ++ { ++ CLzmaProb *prob; ++ UInt32 bound; ++ unsigned ttt; ++ unsigned posState = processedPos & pbMask; ++ ++ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0(prob) ++ { ++ unsigned symbol; ++ UPDATE_0(prob); ++ prob = probs + Literal; ++ if (checkDicSize != 0 || processedPos != 0) ++ prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + ++ (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc)))); ++ ++ if (state < kNumLitStates) ++ { ++ state -= (state < 4) ? state : 3; ++ symbol = 1; ++ do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100); ++ } ++ else ++ { ++ unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ unsigned offs = 0x100; ++ state -= (state < 10) ? 3 : 6; ++ symbol = 1; ++ do ++ { ++ unsigned bit; ++ CLzmaProb *probLit; ++ matchByte <<= 1; ++ bit = (matchByte & offs); ++ probLit = prob + offs + bit + symbol; ++ GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit) ++ } ++ while (symbol < 0x100); ++ } ++ dic[dicPos++] = (Byte)symbol; ++ processedPos++; ++ continue; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ prob = probs + IsRep + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ state += kNumStates; ++ prob = probs + LenCoder; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ if (checkDicSize == 0 && processedPos == 0) ++ return SZ_ERROR_DATA; ++ prob = probs + IsRepG0 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ dicPos++; ++ processedPos++; ++ state = state < kNumLitStates ? 9 : 11; ++ continue; ++ } ++ UPDATE_1(prob); ++ } ++ else ++ { ++ UInt32 distance; ++ UPDATE_1(prob); ++ prob = probs + IsRepG1 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ distance = rep1; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ prob = probs + IsRepG2 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ distance = rep2; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ distance = rep3; ++ rep3 = rep2; ++ } ++ rep2 = rep1; ++ } ++ rep1 = rep0; ++ rep0 = distance; ++ } ++ state = state < kNumLitStates ? 8 : 11; ++ prob = probs + RepLenCoder; ++ } ++ { ++ unsigned limit, offset; ++ CLzmaProb *probLen = prob + LenChoice; ++ IF_BIT_0(probLen) ++ { ++ UPDATE_0(probLen); ++ probLen = prob + LenLow + (posState << kLenNumLowBits); ++ offset = 0; ++ limit = (1 << kLenNumLowBits); ++ } ++ else ++ { ++ UPDATE_1(probLen); ++ probLen = prob + LenChoice2; ++ IF_BIT_0(probLen) ++ { ++ UPDATE_0(probLen); ++ probLen = prob + LenMid + (posState << kLenNumMidBits); ++ offset = kLenNumLowSymbols; ++ limit = (1 << kLenNumMidBits); ++ } ++ else ++ { ++ UPDATE_1(probLen); ++ probLen = prob + LenHigh; ++ offset = kLenNumLowSymbols + kLenNumMidSymbols; ++ limit = (1 << kLenNumHighBits); ++ } ++ } ++ TREE_DECODE(probLen, limit, len); ++ len += offset; ++ } ++ ++ if (state >= kNumStates) ++ { ++ UInt32 distance; ++ prob = probs + PosSlot + ++ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); ++ TREE_6_DECODE(prob, distance); ++ if (distance >= kStartPosModelIndex) ++ { ++ unsigned posSlot = (unsigned)distance; ++ int numDirectBits = (int)(((distance >> 1) - 1)); ++ distance = (2 | (distance & 1)); ++ if (posSlot < kEndPosModelIndex) ++ { ++ distance <<= numDirectBits; ++ prob = probs + SpecPos + distance - posSlot - 1; ++ { ++ UInt32 mask = 1; ++ unsigned i = 1; ++ do ++ { ++ GET_BIT2(prob + i, i, ; , distance |= mask); ++ mask <<= 1; ++ } ++ while (--numDirectBits != 0); ++ } ++ } ++ else ++ { ++ numDirectBits -= kNumAlignBits; ++ do ++ { ++ NORMALIZE ++ range >>= 1; ++ ++ { ++ UInt32 t; ++ code -= range; ++ t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */ ++ distance = (distance << 1) + (t + 1); ++ code += range & t; ++ } ++ /* ++ distance <<= 1; ++ if (code >= range) ++ { ++ code -= range; ++ distance |= 1; ++ } ++ */ ++ } ++ while (--numDirectBits != 0); ++ prob = probs + Align; ++ distance <<= kNumAlignBits; ++ { ++ unsigned i = 1; ++ GET_BIT2(prob + i, i, ; , distance |= 1); ++ GET_BIT2(prob + i, i, ; , distance |= 2); ++ GET_BIT2(prob + i, i, ; , distance |= 4); ++ GET_BIT2(prob + i, i, ; , distance |= 8); ++ } ++ if (distance == (UInt32)0xFFFFFFFF) ++ { ++ len += kMatchSpecLenStart; ++ state -= kNumStates; ++ break; ++ } ++ } ++ } ++ rep3 = rep2; ++ rep2 = rep1; ++ rep1 = rep0; ++ rep0 = distance + 1; ++ if (checkDicSize == 0) ++ { ++ if (distance >= processedPos) ++ return SZ_ERROR_DATA; ++ } ++ else if (distance >= checkDicSize) ++ return SZ_ERROR_DATA; ++ state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3; ++ } ++ ++ len += kMatchMinLen; ++ ++ if (limit == dicPos) ++ return SZ_ERROR_DATA; ++ { ++ SizeT rem = limit - dicPos; ++ unsigned curLen = ((rem < len) ? (unsigned)rem : len); ++ SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0); ++ ++ processedPos += curLen; ++ ++ len -= curLen; ++ if (pos + curLen <= dicBufSize) ++ { ++ Byte *dest = dic + dicPos; ++ ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos; ++ const Byte *lim = dest + curLen; ++ dicPos += curLen; ++ do ++ *(dest) = (Byte)*(dest + src); ++ while (++dest != lim); ++ } ++ else ++ { ++ do ++ { ++ dic[dicPos++] = dic[pos]; ++ if (++pos == dicBufSize) ++ pos = 0; ++ } ++ while (--curLen != 0); ++ } ++ } ++ } ++ } ++ while (dicPos < limit && buf < bufLimit); ++ NORMALIZE; ++ p->buf = buf; ++ p->range = range; ++ p->code = code; ++ p->remainLen = len; ++ p->dicPos = dicPos; ++ p->processedPos = processedPos; ++ p->reps[0] = rep0; ++ p->reps[1] = rep1; ++ p->reps[2] = rep2; ++ p->reps[3] = rep3; ++ p->state = state; ++ ++ return SZ_OK; ++} ++ ++static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit) ++{ ++ if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart) ++ { ++ Byte *dic = p->dic; ++ SizeT dicPos = p->dicPos; ++ SizeT dicBufSize = p->dicBufSize; ++ unsigned len = p->remainLen; ++ UInt32 rep0 = p->reps[0]; ++ if (limit - dicPos < len) ++ len = (unsigned)(limit - dicPos); ++ ++ if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len) ++ p->checkDicSize = p->prop.dicSize; ++ ++ p->processedPos += len; ++ p->remainLen -= len; ++ while (len-- != 0) ++ { ++ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ dicPos++; ++ } ++ p->dicPos = dicPos; ++ } ++} ++ ++static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit) ++{ ++ do ++ { ++ SizeT limit2 = limit; ++ if (p->checkDicSize == 0) ++ { ++ UInt32 rem = p->prop.dicSize - p->processedPos; ++ if (limit - p->dicPos > rem) ++ limit2 = p->dicPos + rem; ++ } ++ RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit)); ++ if (p->processedPos >= p->prop.dicSize) ++ p->checkDicSize = p->prop.dicSize; ++ LzmaDec_WriteRem(p, limit); ++ } ++ while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart); ++ ++ if (p->remainLen > kMatchSpecLenStart) ++ { ++ p->remainLen = kMatchSpecLenStart; ++ } ++ return 0; ++} ++ ++typedef enum ++{ ++ DUMMY_ERROR, /* unexpected end of input stream */ ++ DUMMY_LIT, ++ DUMMY_MATCH, ++ DUMMY_REP ++} ELzmaDummy; ++ ++static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize) ++{ ++ UInt32 range = p->range; ++ UInt32 code = p->code; ++ const Byte *bufLimit = buf + inSize; ++ CLzmaProb *probs = p->probs; ++ unsigned state = p->state; ++ ELzmaDummy res; ++ ++ { ++ CLzmaProb *prob; ++ UInt32 bound; ++ unsigned ttt; ++ unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1); ++ ++ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK ++ ++ /* if (bufLimit - buf >= 7) return DUMMY_LIT; */ ++ ++ prob = probs + Literal; ++ if (p->checkDicSize != 0 || p->processedPos != 0) ++ prob += (LZMA_LIT_SIZE * ++ ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + ++ (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc)))); ++ ++ if (state < kNumLitStates) ++ { ++ unsigned symbol = 1; ++ do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100); ++ } ++ else ++ { ++ unsigned matchByte = p->dic[p->dicPos - p->reps[0] + ++ ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)]; ++ unsigned offs = 0x100; ++ unsigned symbol = 1; ++ do ++ { ++ unsigned bit; ++ CLzmaProb *probLit; ++ matchByte <<= 1; ++ bit = (matchByte & offs); ++ probLit = prob + offs + bit + symbol; ++ GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit) ++ } ++ while (symbol < 0x100); ++ } ++ res = DUMMY_LIT; ++ } ++ else ++ { ++ unsigned len; ++ UPDATE_1_CHECK; ++ ++ prob = probs + IsRep + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ state = 0; ++ prob = probs + LenCoder; ++ res = DUMMY_MATCH; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ res = DUMMY_REP; ++ prob = probs + IsRepG0 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ NORMALIZE_CHECK; ++ return DUMMY_REP; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ } ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ prob = probs + IsRepG1 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ prob = probs + IsRepG2 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ } ++ } ++ } ++ state = kNumStates; ++ prob = probs + RepLenCoder; ++ } ++ { ++ unsigned limit, offset; ++ CLzmaProb *probLen = prob + LenChoice; ++ IF_BIT_0_CHECK(probLen) ++ { ++ UPDATE_0_CHECK; ++ probLen = prob + LenLow + (posState << kLenNumLowBits); ++ offset = 0; ++ limit = 1 << kLenNumLowBits; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ probLen = prob + LenChoice2; ++ IF_BIT_0_CHECK(probLen) ++ { ++ UPDATE_0_CHECK; ++ probLen = prob + LenMid + (posState << kLenNumMidBits); ++ offset = kLenNumLowSymbols; ++ limit = 1 << kLenNumMidBits; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ probLen = prob + LenHigh; ++ offset = kLenNumLowSymbols + kLenNumMidSymbols; ++ limit = 1 << kLenNumHighBits; ++ } ++ } ++ TREE_DECODE_CHECK(probLen, limit, len); ++ len += offset; ++ } ++ ++ if (state < 4) ++ { ++ unsigned posSlot; ++ prob = probs + PosSlot + ++ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << ++ kNumPosSlotBits); ++ TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot); ++ if (posSlot >= kStartPosModelIndex) ++ { ++ int numDirectBits = ((posSlot >> 1) - 1); ++ ++ /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */ ++ ++ if (posSlot < kEndPosModelIndex) ++ { ++ prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1; ++ } ++ else ++ { ++ numDirectBits -= kNumAlignBits; ++ do ++ { ++ NORMALIZE_CHECK ++ range >>= 1; ++ code -= range & (((code - range) >> 31) - 1); ++ /* if (code >= range) code -= range; */ ++ } ++ while (--numDirectBits != 0); ++ prob = probs + Align; ++ numDirectBits = kNumAlignBits; ++ } ++ { ++ unsigned i = 1; ++ do ++ { ++ GET_BIT_CHECK(prob + i, i); ++ } ++ while (--numDirectBits != 0); ++ } ++ } ++ } ++ } ++ } ++ NORMALIZE_CHECK; ++ return res; ++} ++ ++ ++static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data) ++{ ++ p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]); ++ p->range = 0xFFFFFFFF; ++ p->needFlush = 0; ++} ++ ++void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) ++{ ++ p->needFlush = 1; ++ p->remainLen = 0; ++ p->tempBufSize = 0; ++ ++ if (initDic) ++ { ++ p->processedPos = 0; ++ p->checkDicSize = 0; ++ p->needInitState = 1; ++ } ++ if (initState) ++ p->needInitState = 1; ++} ++ ++void LzmaDec_Init(CLzmaDec *p) ++{ ++ p->dicPos = 0; ++ LzmaDec_InitDicAndState(p, True, True); ++} ++ ++static void LzmaDec_InitStateReal(CLzmaDec *p) ++{ ++ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp)); ++ UInt32 i; ++ CLzmaProb *probs = p->probs; ++ for (i = 0; i < numProbs; i++) ++ probs[i] = kBitModelTotal >> 1; ++ p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1; ++ p->state = 0; ++ p->needInitState = 0; ++} ++ ++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, ++ ELzmaFinishMode finishMode, ELzmaStatus *status) ++{ ++ SizeT inSize = *srcLen; ++ (*srcLen) = 0; ++ LzmaDec_WriteRem(p, dicLimit); ++ ++ *status = LZMA_STATUS_NOT_SPECIFIED; ++ ++ while (p->remainLen != kMatchSpecLenStart) ++ { ++ int checkEndMarkNow; ++ ++ if (p->needFlush != 0) ++ { ++ for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--) ++ p->tempBuf[p->tempBufSize++] = *src++; ++ if (p->tempBufSize < RC_INIT_SIZE) ++ { ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (p->tempBuf[0] != 0) ++ return SZ_ERROR_DATA; ++ ++ LzmaDec_InitRc(p, p->tempBuf); ++ p->tempBufSize = 0; ++ } ++ ++ checkEndMarkNow = 0; ++ if (p->dicPos >= dicLimit) ++ { ++ if (p->remainLen == 0 && p->code == 0) ++ { ++ *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK; ++ return SZ_OK; ++ } ++ if (finishMode == LZMA_FINISH_ANY) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_OK; ++ } ++ if (p->remainLen != 0) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ checkEndMarkNow = 1; ++ } ++ ++ if (p->needInitState) ++ LzmaDec_InitStateReal(p); ++ ++ if (p->tempBufSize == 0) ++ { ++ SizeT processed; ++ const Byte *bufLimit; ++ if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) ++ { ++ int dummyRes = LzmaDec_TryDummy(p, src, inSize); ++ if (dummyRes == DUMMY_ERROR) ++ { ++ memcpy(p->tempBuf, src, inSize); ++ p->tempBufSize = (unsigned)inSize; ++ (*srcLen) += inSize; ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ bufLimit = src; ++ } ++ else ++ bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX; ++ p->buf = src; ++ if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0) ++ return SZ_ERROR_DATA; ++ processed = (SizeT)(p->buf - src); ++ (*srcLen) += processed; ++ src += processed; ++ inSize -= processed; ++ } ++ else ++ { ++ unsigned rem = p->tempBufSize, lookAhead = 0; ++ while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize) ++ p->tempBuf[rem++] = src[lookAhead++]; ++ p->tempBufSize = rem; ++ if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) ++ { ++ int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem); ++ if (dummyRes == DUMMY_ERROR) ++ { ++ (*srcLen) += lookAhead; ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ } ++ p->buf = p->tempBuf; ++ if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0) ++ return SZ_ERROR_DATA; ++ lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf)); ++ (*srcLen) += lookAhead; ++ src += lookAhead; ++ inSize -= lookAhead; ++ p->tempBufSize = 0; ++ } ++ } ++ if (p->code == 0) ++ *status = LZMA_STATUS_FINISHED_WITH_MARK; ++ return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; ++} ++ ++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) ++{ ++ SizeT outSize = *destLen; ++ SizeT inSize = *srcLen; ++ *srcLen = *destLen = 0; ++ for (;;) ++ { ++ SizeT inSizeCur = inSize, outSizeCur, dicPos; ++ ELzmaFinishMode curFinishMode; ++ SRes res; ++ if (p->dicPos == p->dicBufSize) ++ p->dicPos = 0; ++ dicPos = p->dicPos; ++ if (outSize > p->dicBufSize - dicPos) ++ { ++ outSizeCur = p->dicBufSize; ++ curFinishMode = LZMA_FINISH_ANY; ++ } ++ else ++ { ++ outSizeCur = dicPos + outSize; ++ curFinishMode = finishMode; ++ } ++ ++ res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); ++ src += inSizeCur; ++ inSize -= inSizeCur; ++ *srcLen += inSizeCur; ++ outSizeCur = p->dicPos - dicPos; ++ memcpy(dest, p->dic + dicPos, outSizeCur); ++ dest += outSizeCur; ++ outSize -= outSizeCur; ++ *destLen += outSizeCur; ++ if (res != 0) ++ return res; ++ if (outSizeCur == 0 || outSize == 0) ++ return SZ_OK; ++ } ++} ++ ++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->probs); ++ p->probs = 0; ++} ++ ++static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->dic); ++ p->dic = 0; ++} ++ ++void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ LzmaDec_FreeProbs(p, alloc); ++ LzmaDec_FreeDict(p, alloc); ++} ++ ++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) ++{ ++ UInt32 dicSize; ++ Byte d; ++ ++ if (size < LZMA_PROPS_SIZE) ++ return SZ_ERROR_UNSUPPORTED; ++ else ++ dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24); ++ ++ if (dicSize < LZMA_DIC_MIN) ++ dicSize = LZMA_DIC_MIN; ++ p->dicSize = dicSize; ++ ++ d = data[0]; ++ if (d >= (9 * 5 * 5)) ++ return SZ_ERROR_UNSUPPORTED; ++ ++ p->lc = d % 9; ++ d /= 9; ++ p->pb = d / 5; ++ p->lp = d % 5; ++ ++ return SZ_OK; ++} ++ ++static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc) ++{ ++ UInt32 numProbs = LzmaProps_GetNumProbs(propNew); ++ if (p->probs == 0 || numProbs != p->numProbs) ++ { ++ LzmaDec_FreeProbs(p, alloc); ++ p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb)); ++ p->numProbs = numProbs; ++ if (p->probs == 0) ++ return SZ_ERROR_MEM; ++ } ++ return SZ_OK; ++} ++ ++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++{ ++ CLzmaProps propNew; ++ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); ++ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); ++ p->prop = propNew; ++ return SZ_OK; ++} ++ ++SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++{ ++ CLzmaProps propNew; ++ SizeT dicBufSize; ++ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); ++ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); ++ dicBufSize = propNew.dicSize; ++ if (p->dic == 0 || dicBufSize != p->dicBufSize) ++ { ++ LzmaDec_FreeDict(p, alloc); ++ p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); ++ if (p->dic == 0) ++ { ++ LzmaDec_FreeProbs(p, alloc); ++ return SZ_ERROR_MEM; ++ } ++ } ++ p->dicBufSize = dicBufSize; ++ p->prop = propNew; ++ return SZ_OK; ++} ++ ++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ++ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, ++ ELzmaStatus *status, ISzAlloc *alloc) ++{ ++ CLzmaDec p; ++ SRes res; ++ SizeT inSize = *srcLen; ++ SizeT outSize = *destLen; ++ *srcLen = *destLen = 0; ++ if (inSize < RC_INIT_SIZE) ++ return SZ_ERROR_INPUT_EOF; ++ ++ LzmaDec_Construct(&p); ++ res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc); ++ if (res != 0) ++ return res; ++ p.dic = dest; ++ p.dicBufSize = outSize; ++ ++ LzmaDec_Init(&p); ++ ++ *srcLen = inSize; ++ res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status); ++ ++ if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT) ++ res = SZ_ERROR_INPUT_EOF; ++ ++ (*destLen) = p.dicPos; ++ LzmaDec_FreeProbs(&p, alloc); ++ return res; ++} +--- /dev/null ++++ b/lib/lzma/LzmaEnc.c +@@ -0,0 +1,2271 @@ ++/* LzmaEnc.c -- LZMA Encoder ++2009-11-24 : Igor Pavlov : Public domain */ ++ ++#include ++ ++/* #define SHOW_STAT */ ++/* #define SHOW_STAT2 */ ++ ++#if defined(SHOW_STAT) || defined(SHOW_STAT2) ++#include ++#endif ++ ++#include "LzmaEnc.h" ++ ++/* disable MT */ ++#define _7ZIP_ST ++ ++#include "LzFind.h" ++#ifndef _7ZIP_ST ++#include "LzFindMt.h" ++#endif ++ ++#ifdef SHOW_STAT ++static int ttt = 0; ++#endif ++ ++#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1) ++ ++#define kBlockSize (9 << 10) ++#define kUnpackBlockSize (1 << 18) ++#define kMatchArraySize (1 << 21) ++#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX) ++ ++#define kNumMaxDirectBits (31) ++ ++#define kNumTopBits 24 ++#define kTopValue ((UInt32)1 << kNumTopBits) ++ ++#define kNumBitModelTotalBits 11 ++#define kBitModelTotal (1 << kNumBitModelTotalBits) ++#define kNumMoveBits 5 ++#define kProbInitValue (kBitModelTotal >> 1) ++ ++#define kNumMoveReducingBits 4 ++#define kNumBitPriceShiftBits 4 ++#define kBitPrice (1 << kNumBitPriceShiftBits) ++ ++void LzmaEncProps_Init(CLzmaEncProps *p) ++{ ++ p->level = 5; ++ p->dictSize = p->mc = 0; ++ p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1; ++ p->writeEndMark = 0; ++} ++ ++void LzmaEncProps_Normalize(CLzmaEncProps *p) ++{ ++ int level = p->level; ++ if (level < 0) level = 5; ++ p->level = level; ++ if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26))); ++ if (p->lc < 0) p->lc = 3; ++ if (p->lp < 0) p->lp = 0; ++ if (p->pb < 0) p->pb = 2; ++ if (p->algo < 0) p->algo = (level < 5 ? 0 : 1); ++ if (p->fb < 0) p->fb = (level < 7 ? 32 : 64); ++ if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1); ++ if (p->numHashBytes < 0) p->numHashBytes = 4; ++ if (p->mc == 0) p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1); ++ if (p->numThreads < 0) ++ p->numThreads = ++ #ifndef _7ZIP_ST ++ ((p->btMode && p->algo) ? 2 : 1); ++ #else ++ 1; ++ #endif ++} ++ ++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) ++{ ++ CLzmaEncProps props = *props2; ++ LzmaEncProps_Normalize(&props); ++ return props.dictSize; ++} ++ ++/* #define LZMA_LOG_BSR */ ++/* Define it for Intel's CPU */ ++ ++ ++#ifdef LZMA_LOG_BSR ++ ++#define kDicLogSizeMaxCompress 30 ++ ++#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } ++ ++UInt32 GetPosSlot1(UInt32 pos) ++{ ++ UInt32 res; ++ BSR2_RET(pos, res); ++ return res; ++} ++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } ++#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); } ++ ++#else ++ ++#define kNumLogBits (9 + (int)sizeof(size_t) / 2) ++#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) ++ ++void LzmaEnc_FastPosInit(Byte *g_FastPos) ++{ ++ int c = 2, slotFast; ++ g_FastPos[0] = 0; ++ g_FastPos[1] = 1; ++ ++ for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++) ++ { ++ UInt32 k = (1 << ((slotFast >> 1) - 1)); ++ UInt32 j; ++ for (j = 0; j < k; j++, c++) ++ g_FastPos[c] = (Byte)slotFast; ++ } ++} ++ ++#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \ ++ (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \ ++ res = p->g_FastPos[pos >> i] + (i * 2); } ++/* ++#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \ ++ p->g_FastPos[pos >> 6] + 12 : \ ++ p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; } ++*/ ++ ++#define GetPosSlot1(pos) p->g_FastPos[pos] ++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } ++#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); } ++ ++#endif ++ ++ ++#define LZMA_NUM_REPS 4 ++ ++typedef unsigned CState; ++ ++typedef struct ++{ ++ UInt32 price; ++ ++ CState state; ++ int prev1IsChar; ++ int prev2; ++ ++ UInt32 posPrev2; ++ UInt32 backPrev2; ++ ++ UInt32 posPrev; ++ UInt32 backPrev; ++ UInt32 backs[LZMA_NUM_REPS]; ++} COptimal; ++ ++#define kNumOpts (1 << 12) ++ ++#define kNumLenToPosStates 4 ++#define kNumPosSlotBits 6 ++#define kDicLogSizeMin 0 ++#define kDicLogSizeMax 32 ++#define kDistTableSizeMax (kDicLogSizeMax * 2) ++ ++ ++#define kNumAlignBits 4 ++#define kAlignTableSize (1 << kNumAlignBits) ++#define kAlignMask (kAlignTableSize - 1) ++ ++#define kStartPosModelIndex 4 ++#define kEndPosModelIndex 14 ++#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex) ++ ++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) ++ ++#ifdef _LZMA_PROB32 ++#define CLzmaProb UInt32 ++#else ++#define CLzmaProb UInt16 ++#endif ++ ++#define LZMA_PB_MAX 4 ++#define LZMA_LC_MAX 8 ++#define LZMA_LP_MAX 4 ++ ++#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX) ++ ++ ++#define kLenNumLowBits 3 ++#define kLenNumLowSymbols (1 << kLenNumLowBits) ++#define kLenNumMidBits 3 ++#define kLenNumMidSymbols (1 << kLenNumMidBits) ++#define kLenNumHighBits 8 ++#define kLenNumHighSymbols (1 << kLenNumHighBits) ++ ++#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) ++ ++#define LZMA_MATCH_LEN_MIN 2 ++#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1) ++ ++#define kNumStates 12 ++ ++typedef struct ++{ ++ CLzmaProb choice; ++ CLzmaProb choice2; ++ CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits]; ++ CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits]; ++ CLzmaProb high[kLenNumHighSymbols]; ++} CLenEnc; ++ ++typedef struct ++{ ++ CLenEnc p; ++ UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal]; ++ UInt32 tableSize; ++ UInt32 counters[LZMA_NUM_PB_STATES_MAX]; ++} CLenPriceEnc; ++ ++typedef struct ++{ ++ UInt32 range; ++ Byte cache; ++ UInt64 low; ++ UInt64 cacheSize; ++ Byte *buf; ++ Byte *bufLim; ++ Byte *bufBase; ++ ISeqOutStream *outStream; ++ UInt64 processed; ++ SRes res; ++} CRangeEnc; ++ ++typedef struct ++{ ++ CLzmaProb *litProbs; ++ ++ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ CLzmaProb isRep[kNumStates]; ++ CLzmaProb isRepG0[kNumStates]; ++ CLzmaProb isRepG1[kNumStates]; ++ CLzmaProb isRepG2[kNumStates]; ++ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ ++ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; ++ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; ++ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; ++ ++ CLenPriceEnc lenEnc; ++ CLenPriceEnc repLenEnc; ++ ++ UInt32 reps[LZMA_NUM_REPS]; ++ UInt32 state; ++} CSaveState; ++ ++typedef struct ++{ ++ IMatchFinder matchFinder; ++ void *matchFinderObj; ++ ++ #ifndef _7ZIP_ST ++ Bool mtMode; ++ CMatchFinderMt matchFinderMt; ++ #endif ++ ++ CMatchFinder matchFinderBase; ++ ++ #ifndef _7ZIP_ST ++ Byte pad[128]; ++ #endif ++ ++ UInt32 optimumEndIndex; ++ UInt32 optimumCurrentIndex; ++ ++ UInt32 longestMatchLength; ++ UInt32 numPairs; ++ UInt32 numAvail; ++ COptimal opt[kNumOpts]; ++ ++ #ifndef LZMA_LOG_BSR ++ Byte g_FastPos[1 << kNumLogBits]; ++ #endif ++ ++ UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits]; ++ UInt32 matches[LZMA_MATCH_LEN_MAX * 2 + 2 + 1]; ++ UInt32 numFastBytes; ++ UInt32 additionalOffset; ++ UInt32 reps[LZMA_NUM_REPS]; ++ UInt32 state; ++ ++ UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax]; ++ UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances]; ++ UInt32 alignPrices[kAlignTableSize]; ++ UInt32 alignPriceCount; ++ ++ UInt32 distTableSize; ++ ++ unsigned lc, lp, pb; ++ unsigned lpMask, pbMask; ++ ++ CLzmaProb *litProbs; ++ ++ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ CLzmaProb isRep[kNumStates]; ++ CLzmaProb isRepG0[kNumStates]; ++ CLzmaProb isRepG1[kNumStates]; ++ CLzmaProb isRepG2[kNumStates]; ++ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ ++ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; ++ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; ++ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; ++ ++ CLenPriceEnc lenEnc; ++ CLenPriceEnc repLenEnc; ++ ++ unsigned lclp; ++ ++ Bool fastMode; ++ ++ CRangeEnc rc; ++ ++ Bool writeEndMark; ++ UInt64 nowPos64; ++ UInt32 matchPriceCount; ++ Bool finished; ++ Bool multiThread; ++ ++ SRes result; ++ UInt32 dictSize; ++ UInt32 matchFinderCycles; ++ ++ int needInit; ++ ++ CSaveState saveState; ++} CLzmaEnc; ++ ++void LzmaEnc_SaveState(CLzmaEncHandle pp) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ CSaveState *dest = &p->saveState; ++ int i; ++ dest->lenEnc = p->lenEnc; ++ dest->repLenEnc = p->repLenEnc; ++ dest->state = p->state; ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); ++ memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); ++ } ++ for (i = 0; i < kNumLenToPosStates; i++) ++ memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); ++ memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); ++ memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); ++ memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); ++ memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); ++ memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); ++ memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); ++ memcpy(dest->reps, p->reps, sizeof(p->reps)); ++ memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb)); ++} ++ ++void LzmaEnc_RestoreState(CLzmaEncHandle pp) ++{ ++ CLzmaEnc *dest = (CLzmaEnc *)pp; ++ const CSaveState *p = &dest->saveState; ++ int i; ++ dest->lenEnc = p->lenEnc; ++ dest->repLenEnc = p->repLenEnc; ++ dest->state = p->state; ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); ++ memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); ++ } ++ for (i = 0; i < kNumLenToPosStates; i++) ++ memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); ++ memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); ++ memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); ++ memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); ++ memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); ++ memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); ++ memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); ++ memcpy(dest->reps, p->reps, sizeof(p->reps)); ++ memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb)); ++} ++ ++SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ CLzmaEncProps props = *props2; ++ LzmaEncProps_Normalize(&props); ++ ++ if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX || ++ props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30)) ++ return SZ_ERROR_PARAM; ++ p->dictSize = props.dictSize; ++ p->matchFinderCycles = props.mc; ++ { ++ unsigned fb = props.fb; ++ if (fb < 5) ++ fb = 5; ++ if (fb > LZMA_MATCH_LEN_MAX) ++ fb = LZMA_MATCH_LEN_MAX; ++ p->numFastBytes = fb; ++ } ++ p->lc = props.lc; ++ p->lp = props.lp; ++ p->pb = props.pb; ++ p->fastMode = (props.algo == 0); ++ p->matchFinderBase.btMode = props.btMode; ++ { ++ UInt32 numHashBytes = 4; ++ if (props.btMode) ++ { ++ if (props.numHashBytes < 2) ++ numHashBytes = 2; ++ else if (props.numHashBytes < 4) ++ numHashBytes = props.numHashBytes; ++ } ++ p->matchFinderBase.numHashBytes = numHashBytes; ++ } ++ ++ p->matchFinderBase.cutValue = props.mc; ++ ++ p->writeEndMark = props.writeEndMark; ++ ++ #ifndef _7ZIP_ST ++ /* ++ if (newMultiThread != _multiThread) ++ { ++ ReleaseMatchFinder(); ++ _multiThread = newMultiThread; ++ } ++ */ ++ p->multiThread = (props.numThreads > 1); ++ #endif ++ ++ return SZ_OK; ++} ++ ++static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 4, 5}; ++static const int kMatchNextStates[kNumStates] = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10}; ++static const int kRepNextStates[kNumStates] = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11}; ++static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11}; ++ ++#define IsCharState(s) ((s) < 7) ++ ++#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1) ++ ++#define kInfinityPrice (1 << 30) ++ ++static void RangeEnc_Construct(CRangeEnc *p) ++{ ++ p->outStream = 0; ++ p->bufBase = 0; ++} ++ ++#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize) ++ ++#define RC_BUF_SIZE (1 << 16) ++static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc) ++{ ++ if (p->bufBase == 0) ++ { ++ p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE); ++ if (p->bufBase == 0) ++ return 0; ++ p->bufLim = p->bufBase + RC_BUF_SIZE; ++ } ++ return 1; ++} ++ ++static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->bufBase); ++ p->bufBase = 0; ++} ++ ++static void RangeEnc_Init(CRangeEnc *p) ++{ ++ /* Stream.Init(); */ ++ p->low = 0; ++ p->range = 0xFFFFFFFF; ++ p->cacheSize = 1; ++ p->cache = 0; ++ ++ p->buf = p->bufBase; ++ ++ p->processed = 0; ++ p->res = SZ_OK; ++} ++ ++static void RangeEnc_FlushStream(CRangeEnc *p) ++{ ++ size_t num; ++ if (p->res != SZ_OK) ++ return; ++ num = p->buf - p->bufBase; ++ if (num != p->outStream->Write(p->outStream, p->bufBase, num)) ++ p->res = SZ_ERROR_WRITE; ++ p->processed += num; ++ p->buf = p->bufBase; ++} ++ ++static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p) ++{ ++ if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0) ++ { ++ Byte temp = p->cache; ++ do ++ { ++ Byte *buf = p->buf; ++ *buf++ = (Byte)(temp + (Byte)(p->low >> 32)); ++ p->buf = buf; ++ if (buf == p->bufLim) ++ RangeEnc_FlushStream(p); ++ temp = 0xFF; ++ } ++ while (--p->cacheSize != 0); ++ p->cache = (Byte)((UInt32)p->low >> 24); ++ } ++ p->cacheSize++; ++ p->low = (UInt32)p->low << 8; ++} ++ ++static void RangeEnc_FlushData(CRangeEnc *p) ++{ ++ int i; ++ for (i = 0; i < 5; i++) ++ RangeEnc_ShiftLow(p); ++} ++ ++static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits) ++{ ++ do ++ { ++ p->range >>= 1; ++ p->low += p->range & (0 - ((value >> --numBits) & 1)); ++ if (p->range < kTopValue) ++ { ++ p->range <<= 8; ++ RangeEnc_ShiftLow(p); ++ } ++ } ++ while (numBits != 0); ++} ++ ++static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol) ++{ ++ UInt32 ttt = *prob; ++ UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt; ++ if (symbol == 0) ++ { ++ p->range = newBound; ++ ttt += (kBitModelTotal - ttt) >> kNumMoveBits; ++ } ++ else ++ { ++ p->low += newBound; ++ p->range -= newBound; ++ ttt -= ttt >> kNumMoveBits; ++ } ++ *prob = (CLzmaProb)ttt; ++ if (p->range < kTopValue) ++ { ++ p->range <<= 8; ++ RangeEnc_ShiftLow(p); ++ } ++} ++ ++static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol) ++{ ++ symbol |= 0x100; ++ do ++ { ++ RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1); ++ symbol <<= 1; ++ } ++ while (symbol < 0x10000); ++} ++ ++static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte) ++{ ++ UInt32 offs = 0x100; ++ symbol |= 0x100; ++ do ++ { ++ matchByte <<= 1; ++ RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1); ++ symbol <<= 1; ++ offs &= ~(matchByte ^ symbol); ++ } ++ while (symbol < 0x10000); ++} ++ ++void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) ++{ ++ UInt32 i; ++ for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) ++ { ++ const int kCyclesBits = kNumBitPriceShiftBits; ++ UInt32 w = i; ++ UInt32 bitCount = 0; ++ int j; ++ for (j = 0; j < kCyclesBits; j++) ++ { ++ w = w * w; ++ bitCount <<= 1; ++ while (w >= ((UInt32)1 << 16)) ++ { ++ w >>= 1; ++ bitCount++; ++ } ++ } ++ ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount); ++ } ++} ++ ++ ++#define GET_PRICE(prob, symbol) \ ++ p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; ++ ++#define GET_PRICEa(prob, symbol) \ ++ ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; ++ ++#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits] ++#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] ++ ++#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits] ++#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] ++ ++static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ symbol |= 0x100; ++ do ++ { ++ price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1); ++ symbol <<= 1; ++ } ++ while (symbol < 0x10000); ++ return price; ++} ++ ++static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ UInt32 offs = 0x100; ++ symbol |= 0x100; ++ do ++ { ++ matchByte <<= 1; ++ price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1); ++ symbol <<= 1; ++ offs &= ~(matchByte ^ symbol); ++ } ++ while (symbol < 0x10000); ++ return price; ++} ++ ++ ++static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) ++{ ++ UInt32 m = 1; ++ int i; ++ for (i = numBitLevels; i != 0;) ++ { ++ UInt32 bit; ++ i--; ++ bit = (symbol >> i) & 1; ++ RangeEnc_EncodeBit(rc, probs + m, bit); ++ m = (m << 1) | bit; ++ } ++} ++ ++static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) ++{ ++ UInt32 m = 1; ++ int i; ++ for (i = 0; i < numBitLevels; i++) ++ { ++ UInt32 bit = symbol & 1; ++ RangeEnc_EncodeBit(rc, probs + m, bit); ++ m = (m << 1) | bit; ++ symbol >>= 1; ++ } ++} ++ ++static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ symbol |= (1 << numBitLevels); ++ while (symbol != 1) ++ { ++ price += GET_PRICEa(probs[symbol >> 1], symbol & 1); ++ symbol >>= 1; ++ } ++ return price; ++} ++ ++static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ UInt32 m = 1; ++ int i; ++ for (i = numBitLevels; i != 0; i--) ++ { ++ UInt32 bit = symbol & 1; ++ symbol >>= 1; ++ price += GET_PRICEa(probs[m], bit); ++ m = (m << 1) | bit; ++ } ++ return price; ++} ++ ++ ++static void LenEnc_Init(CLenEnc *p) ++{ ++ unsigned i; ++ p->choice = p->choice2 = kProbInitValue; ++ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++) ++ p->low[i] = kProbInitValue; ++ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++) ++ p->mid[i] = kProbInitValue; ++ for (i = 0; i < kLenNumHighSymbols; i++) ++ p->high[i] = kProbInitValue; ++} ++ ++static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState) ++{ ++ if (symbol < kLenNumLowSymbols) ++ { ++ RangeEnc_EncodeBit(rc, &p->choice, 0); ++ RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol); ++ } ++ else ++ { ++ RangeEnc_EncodeBit(rc, &p->choice, 1); ++ if (symbol < kLenNumLowSymbols + kLenNumMidSymbols) ++ { ++ RangeEnc_EncodeBit(rc, &p->choice2, 0); ++ RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols); ++ } ++ else ++ { ++ RangeEnc_EncodeBit(rc, &p->choice2, 1); ++ RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols); ++ } ++ } ++} ++ ++static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices) ++{ ++ UInt32 a0 = GET_PRICE_0a(p->choice); ++ UInt32 a1 = GET_PRICE_1a(p->choice); ++ UInt32 b0 = a1 + GET_PRICE_0a(p->choice2); ++ UInt32 b1 = a1 + GET_PRICE_1a(p->choice2); ++ UInt32 i = 0; ++ for (i = 0; i < kLenNumLowSymbols; i++) ++ { ++ if (i >= numSymbols) ++ return; ++ prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices); ++ } ++ for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++) ++ { ++ if (i >= numSymbols) ++ return; ++ prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices); ++ } ++ for (; i < numSymbols; i++) ++ prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices); ++} ++ ++static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices) ++{ ++ LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices); ++ p->counters[posState] = p->tableSize; ++} ++ ++static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices) ++{ ++ UInt32 posState; ++ for (posState = 0; posState < numPosStates; posState++) ++ LenPriceEnc_UpdateTable(p, posState, ProbPrices); ++} ++ ++static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices) ++{ ++ LenEnc_Encode(&p->p, rc, symbol, posState); ++ if (updatePrice) ++ if (--p->counters[posState] == 0) ++ LenPriceEnc_UpdateTable(p, posState, ProbPrices); ++} ++ ++ ++ ++ ++static void MovePos(CLzmaEnc *p, UInt32 num) ++{ ++ #ifdef SHOW_STAT ++ ttt += num; ++ printf("\n MovePos %d", num); ++ #endif ++ if (num != 0) ++ { ++ p->additionalOffset += num; ++ p->matchFinder.Skip(p->matchFinderObj, num); ++ } ++} ++ ++static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes) ++{ ++ UInt32 lenRes = 0, numPairs; ++ p->numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); ++ numPairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matches); ++ #ifdef SHOW_STAT ++ printf("\n i = %d numPairs = %d ", ttt, numPairs / 2); ++ ttt++; ++ { ++ UInt32 i; ++ for (i = 0; i < numPairs; i += 2) ++ printf("%2d %6d | ", p->matches[i], p->matches[i + 1]); ++ } ++ #endif ++ if (numPairs > 0) ++ { ++ lenRes = p->matches[numPairs - 2]; ++ if (lenRes == p->numFastBytes) ++ { ++ const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ UInt32 distance = p->matches[numPairs - 1] + 1; ++ UInt32 numAvail = p->numAvail; ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ { ++ const Byte *pby2 = pby - distance; ++ for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++); ++ } ++ } ++ } ++ p->additionalOffset++; ++ *numDistancePairsRes = numPairs; ++ return lenRes; ++} ++ ++ ++#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False; ++#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False; ++#define IsShortRep(p) ((p)->backPrev == 0) ++ ++static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState) ++{ ++ return ++ GET_PRICE_0(p->isRepG0[state]) + ++ GET_PRICE_0(p->isRep0Long[state][posState]); ++} ++ ++static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState) ++{ ++ UInt32 price; ++ if (repIndex == 0) ++ { ++ price = GET_PRICE_0(p->isRepG0[state]); ++ price += GET_PRICE_1(p->isRep0Long[state][posState]); ++ } ++ else ++ { ++ price = GET_PRICE_1(p->isRepG0[state]); ++ if (repIndex == 1) ++ price += GET_PRICE_0(p->isRepG1[state]); ++ else ++ { ++ price += GET_PRICE_1(p->isRepG1[state]); ++ price += GET_PRICE(p->isRepG2[state], repIndex - 2); ++ } ++ } ++ return price; ++} ++ ++static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState) ++{ ++ return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] + ++ GetPureRepPrice(p, repIndex, state, posState); ++} ++ ++static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur) ++{ ++ UInt32 posMem = p->opt[cur].posPrev; ++ UInt32 backMem = p->opt[cur].backPrev; ++ p->optimumEndIndex = cur; ++ do ++ { ++ if (p->opt[cur].prev1IsChar) ++ { ++ MakeAsChar(&p->opt[posMem]) ++ p->opt[posMem].posPrev = posMem - 1; ++ if (p->opt[cur].prev2) ++ { ++ p->opt[posMem - 1].prev1IsChar = False; ++ p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2; ++ p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2; ++ } ++ } ++ { ++ UInt32 posPrev = posMem; ++ UInt32 backCur = backMem; ++ ++ backMem = p->opt[posPrev].backPrev; ++ posMem = p->opt[posPrev].posPrev; ++ ++ p->opt[posPrev].backPrev = backCur; ++ p->opt[posPrev].posPrev = cur; ++ cur = posPrev; ++ } ++ } ++ while (cur != 0); ++ *backRes = p->opt[0].backPrev; ++ p->optimumCurrentIndex = p->opt[0].posPrev; ++ return p->optimumCurrentIndex; ++} ++ ++#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300) ++ ++static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes) ++{ ++ UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur; ++ UInt32 matchPrice, repMatchPrice, normalMatchPrice; ++ UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS]; ++ UInt32 *matches; ++ const Byte *data; ++ Byte curByte, matchByte; ++ if (p->optimumEndIndex != p->optimumCurrentIndex) ++ { ++ const COptimal *opt = &p->opt[p->optimumCurrentIndex]; ++ UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex; ++ *backRes = opt->backPrev; ++ p->optimumCurrentIndex = opt->posPrev; ++ return lenRes; ++ } ++ p->optimumCurrentIndex = p->optimumEndIndex = 0; ++ ++ if (p->additionalOffset == 0) ++ mainLen = ReadMatchDistances(p, &numPairs); ++ else ++ { ++ mainLen = p->longestMatchLength; ++ numPairs = p->numPairs; ++ } ++ ++ numAvail = p->numAvail; ++ if (numAvail < 2) ++ { ++ *backRes = (UInt32)(-1); ++ return 1; ++ } ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ repMaxIndex = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 lenTest; ++ const Byte *data2; ++ reps[i] = p->reps[i]; ++ data2 = data - (reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ { ++ repLens[i] = 0; ++ continue; ++ } ++ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); ++ repLens[i] = lenTest; ++ if (lenTest > repLens[repMaxIndex]) ++ repMaxIndex = i; ++ } ++ if (repLens[repMaxIndex] >= p->numFastBytes) ++ { ++ UInt32 lenRes; ++ *backRes = repMaxIndex; ++ lenRes = repLens[repMaxIndex]; ++ MovePos(p, lenRes - 1); ++ return lenRes; ++ } ++ ++ matches = p->matches; ++ if (mainLen >= p->numFastBytes) ++ { ++ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 1); ++ return mainLen; ++ } ++ curByte = *data; ++ matchByte = *(data - (reps[0] + 1)); ++ ++ if (mainLen < 2 && curByte != matchByte && repLens[repMaxIndex] < 2) ++ { ++ *backRes = (UInt32)-1; ++ return 1; ++ } ++ ++ p->opt[0].state = (CState)p->state; ++ ++ posState = (position & p->pbMask); ++ ++ { ++ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); ++ p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) + ++ (!IsCharState(p->state) ? ++ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : ++ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); ++ } ++ ++ MakeAsChar(&p->opt[1]); ++ ++ matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]); ++ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]); ++ ++ if (matchByte == curByte) ++ { ++ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState); ++ if (shortRepPrice < p->opt[1].price) ++ { ++ p->opt[1].price = shortRepPrice; ++ MakeAsShortRep(&p->opt[1]); ++ } ++ } ++ lenEnd = ((mainLen >= repLens[repMaxIndex]) ? mainLen : repLens[repMaxIndex]); ++ ++ if (lenEnd < 2) ++ { ++ *backRes = p->opt[1].backPrev; ++ return 1; ++ } ++ ++ p->opt[1].posPrev = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ p->opt[0].backs[i] = reps[i]; ++ ++ len = lenEnd; ++ do ++ p->opt[len--].price = kInfinityPrice; ++ while (len >= 2); ++ ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 repLen = repLens[i]; ++ UInt32 price; ++ if (repLen < 2) ++ continue; ++ price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState); ++ do ++ { ++ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2]; ++ COptimal *opt = &p->opt[repLen]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = 0; ++ opt->backPrev = i; ++ opt->prev1IsChar = False; ++ } ++ } ++ while (--repLen >= 2); ++ } ++ ++ normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]); ++ ++ len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2); ++ if (len <= mainLen) ++ { ++ UInt32 offs = 0; ++ while (len > matches[offs]) ++ offs += 2; ++ for (; ; len++) ++ { ++ COptimal *opt; ++ UInt32 distance = matches[offs + 1]; ++ ++ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN]; ++ UInt32 lenToPosState = GetLenToPosState(len); ++ if (distance < kNumFullDistances) ++ curAndLenPrice += p->distancesPrices[lenToPosState][distance]; ++ else ++ { ++ UInt32 slot; ++ GetPosSlot2(distance, slot); ++ curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot]; ++ } ++ opt = &p->opt[len]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = 0; ++ opt->backPrev = distance + LZMA_NUM_REPS; ++ opt->prev1IsChar = False; ++ } ++ if (len == matches[offs]) ++ { ++ offs += 2; ++ if (offs == numPairs) ++ break; ++ } ++ } ++ } ++ ++ cur = 0; ++ ++ #ifdef SHOW_STAT2 ++ if (position >= 0) ++ { ++ unsigned i; ++ printf("\n pos = %4X", position); ++ for (i = cur; i <= lenEnd; i++) ++ printf("\nprice[%4X] = %d", position - cur + i, p->opt[i].price); ++ } ++ #endif ++ ++ for (;;) ++ { ++ UInt32 numAvailFull, newLen, numPairs, posPrev, state, posState, startLen; ++ UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice; ++ Bool nextIsChar; ++ Byte curByte, matchByte; ++ const Byte *data; ++ COptimal *curOpt; ++ COptimal *nextOpt; ++ ++ cur++; ++ if (cur == lenEnd) ++ return Backward(p, backRes, cur); ++ ++ newLen = ReadMatchDistances(p, &numPairs); ++ if (newLen >= p->numFastBytes) ++ { ++ p->numPairs = numPairs; ++ p->longestMatchLength = newLen; ++ return Backward(p, backRes, cur); ++ } ++ position++; ++ curOpt = &p->opt[cur]; ++ posPrev = curOpt->posPrev; ++ if (curOpt->prev1IsChar) ++ { ++ posPrev--; ++ if (curOpt->prev2) ++ { ++ state = p->opt[curOpt->posPrev2].state; ++ if (curOpt->backPrev2 < LZMA_NUM_REPS) ++ state = kRepNextStates[state]; ++ else ++ state = kMatchNextStates[state]; ++ } ++ else ++ state = p->opt[posPrev].state; ++ state = kLiteralNextStates[state]; ++ } ++ else ++ state = p->opt[posPrev].state; ++ if (posPrev == cur - 1) ++ { ++ if (IsShortRep(curOpt)) ++ state = kShortRepNextStates[state]; ++ else ++ state = kLiteralNextStates[state]; ++ } ++ else ++ { ++ UInt32 pos; ++ const COptimal *prevOpt; ++ if (curOpt->prev1IsChar && curOpt->prev2) ++ { ++ posPrev = curOpt->posPrev2; ++ pos = curOpt->backPrev2; ++ state = kRepNextStates[state]; ++ } ++ else ++ { ++ pos = curOpt->backPrev; ++ if (pos < LZMA_NUM_REPS) ++ state = kRepNextStates[state]; ++ else ++ state = kMatchNextStates[state]; ++ } ++ prevOpt = &p->opt[posPrev]; ++ if (pos < LZMA_NUM_REPS) ++ { ++ UInt32 i; ++ reps[0] = prevOpt->backs[pos]; ++ for (i = 1; i <= pos; i++) ++ reps[i] = prevOpt->backs[i - 1]; ++ for (; i < LZMA_NUM_REPS; i++) ++ reps[i] = prevOpt->backs[i]; ++ } ++ else ++ { ++ UInt32 i; ++ reps[0] = (pos - LZMA_NUM_REPS); ++ for (i = 1; i < LZMA_NUM_REPS; i++) ++ reps[i] = prevOpt->backs[i - 1]; ++ } ++ } ++ curOpt->state = (CState)state; ++ ++ curOpt->backs[0] = reps[0]; ++ curOpt->backs[1] = reps[1]; ++ curOpt->backs[2] = reps[2]; ++ curOpt->backs[3] = reps[3]; ++ ++ curPrice = curOpt->price; ++ nextIsChar = False; ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ curByte = *data; ++ matchByte = *(data - (reps[0] + 1)); ++ ++ posState = (position & p->pbMask); ++ ++ curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]); ++ { ++ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); ++ curAnd1Price += ++ (!IsCharState(state) ? ++ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : ++ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); ++ } ++ ++ nextOpt = &p->opt[cur + 1]; ++ ++ if (curAnd1Price < nextOpt->price) ++ { ++ nextOpt->price = curAnd1Price; ++ nextOpt->posPrev = cur; ++ MakeAsChar(nextOpt); ++ nextIsChar = True; ++ } ++ ++ matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]); ++ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]); ++ ++ if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0)) ++ { ++ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState); ++ if (shortRepPrice <= nextOpt->price) ++ { ++ nextOpt->price = shortRepPrice; ++ nextOpt->posPrev = cur; ++ MakeAsShortRep(nextOpt); ++ nextIsChar = True; ++ } ++ } ++ numAvailFull = p->numAvail; ++ { ++ UInt32 temp = kNumOpts - 1 - cur; ++ if (temp < numAvailFull) ++ numAvailFull = temp; ++ } ++ ++ if (numAvailFull < 2) ++ continue; ++ numAvail = (numAvailFull <= p->numFastBytes ? numAvailFull : p->numFastBytes); ++ ++ if (!nextIsChar && matchByte != curByte) /* speed optimization */ ++ { ++ /* try Literal + rep0 */ ++ UInt32 temp; ++ UInt32 lenTest2; ++ const Byte *data2 = data - (reps[0] + 1); ++ UInt32 limit = p->numFastBytes + 1; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ ++ for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++); ++ lenTest2 = temp - 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kLiteralNextStates[state]; ++ UInt32 posStateNext = (position + 1) & p->pbMask; ++ UInt32 nextRepMatchPrice = curAnd1Price + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ UInt32 offset = cur + 1 + lenTest2; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = False; ++ } ++ } ++ } ++ } ++ ++ startLen = 2; /* speed optimization */ ++ { ++ UInt32 repIndex; ++ for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++) ++ { ++ UInt32 lenTest; ++ UInt32 lenTestTemp; ++ UInt32 price; ++ const Byte *data2 = data - (reps[repIndex] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); ++ while (lenEnd < cur + lenTest) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ lenTestTemp = lenTest; ++ price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState); ++ do ++ { ++ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2]; ++ COptimal *opt = &p->opt[cur + lenTest]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur; ++ opt->backPrev = repIndex; ++ opt->prev1IsChar = False; ++ } ++ } ++ while (--lenTest >= 2); ++ lenTest = lenTestTemp; ++ ++ if (repIndex == 0) ++ startLen = lenTest + 1; ++ ++ /* if (_maxMode) */ ++ { ++ UInt32 lenTest2 = lenTest + 1; ++ UInt32 limit = lenTest2 + p->numFastBytes; ++ UInt32 nextRepMatchPrice; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); ++ lenTest2 -= lenTest + 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kRepNextStates[state]; ++ UInt32 posStateNext = (position + lenTest) & p->pbMask; ++ UInt32 curAndLenCharPrice = ++ price + p->repLenEnc.prices[posState][lenTest - 2] + ++ GET_PRICE_0(p->isMatch[state2][posStateNext]) + ++ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), ++ data[lenTest], data2[lenTest], p->ProbPrices); ++ state2 = kLiteralNextStates[state2]; ++ posStateNext = (position + lenTest + 1) & p->pbMask; ++ nextRepMatchPrice = curAndLenCharPrice + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ UInt32 offset = cur + lenTest + 1 + lenTest2; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + lenTest + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = True; ++ opt->posPrev2 = cur; ++ opt->backPrev2 = repIndex; ++ } ++ } ++ } ++ } ++ } ++ } ++ /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */ ++ if (newLen > numAvail) ++ { ++ newLen = numAvail; ++ for (numPairs = 0; newLen > matches[numPairs]; numPairs += 2); ++ matches[numPairs] = newLen; ++ numPairs += 2; ++ } ++ if (newLen >= startLen) ++ { ++ UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]); ++ UInt32 offs, curBack, posSlot; ++ UInt32 lenTest; ++ while (lenEnd < cur + newLen) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ ++ offs = 0; ++ while (startLen > matches[offs]) ++ offs += 2; ++ curBack = matches[offs + 1]; ++ GetPosSlot2(curBack, posSlot); ++ for (lenTest = /*2*/ startLen; ; lenTest++) ++ { ++ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN]; ++ UInt32 lenToPosState = GetLenToPosState(lenTest); ++ COptimal *opt; ++ if (curBack < kNumFullDistances) ++ curAndLenPrice += p->distancesPrices[lenToPosState][curBack]; ++ else ++ curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask]; ++ ++ opt = &p->opt[cur + lenTest]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur; ++ opt->backPrev = curBack + LZMA_NUM_REPS; ++ opt->prev1IsChar = False; ++ } ++ ++ if (/*_maxMode && */lenTest == matches[offs]) ++ { ++ /* Try Match + Literal + Rep0 */ ++ const Byte *data2 = data - (curBack + 1); ++ UInt32 lenTest2 = lenTest + 1; ++ UInt32 limit = lenTest2 + p->numFastBytes; ++ UInt32 nextRepMatchPrice; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); ++ lenTest2 -= lenTest + 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kMatchNextStates[state]; ++ UInt32 posStateNext = (position + lenTest) & p->pbMask; ++ UInt32 curAndLenCharPrice = curAndLenPrice + ++ GET_PRICE_0(p->isMatch[state2][posStateNext]) + ++ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), ++ data[lenTest], data2[lenTest], p->ProbPrices); ++ state2 = kLiteralNextStates[state2]; ++ posStateNext = (posStateNext + 1) & p->pbMask; ++ nextRepMatchPrice = curAndLenCharPrice + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 offset = cur + lenTest + 1 + lenTest2; ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + lenTest + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = True; ++ opt->posPrev2 = cur; ++ opt->backPrev2 = curBack + LZMA_NUM_REPS; ++ } ++ } ++ } ++ offs += 2; ++ if (offs == numPairs) ++ break; ++ curBack = matches[offs + 1]; ++ if (curBack >= kNumFullDistances) ++ GetPosSlot2(curBack, posSlot); ++ } ++ } ++ } ++ } ++} ++ ++#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist)) ++ ++static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes) ++{ ++ UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i; ++ const Byte *data; ++ const UInt32 *matches; ++ ++ if (p->additionalOffset == 0) ++ mainLen = ReadMatchDistances(p, &numPairs); ++ else ++ { ++ mainLen = p->longestMatchLength; ++ numPairs = p->numPairs; ++ } ++ ++ numAvail = p->numAvail; ++ *backRes = (UInt32)-1; ++ if (numAvail < 2) ++ return 1; ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ ++ repLen = repIndex = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 len; ++ const Byte *data2 = data - (p->reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ for (len = 2; len < numAvail && data[len] == data2[len]; len++); ++ if (len >= p->numFastBytes) ++ { ++ *backRes = i; ++ MovePos(p, len - 1); ++ return len; ++ } ++ if (len > repLen) ++ { ++ repIndex = i; ++ repLen = len; ++ } ++ } ++ ++ matches = p->matches; ++ if (mainLen >= p->numFastBytes) ++ { ++ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 1); ++ return mainLen; ++ } ++ ++ mainDist = 0; /* for GCC */ ++ if (mainLen >= 2) ++ { ++ mainDist = matches[numPairs - 1]; ++ while (numPairs > 2 && mainLen == matches[numPairs - 4] + 1) ++ { ++ if (!ChangePair(matches[numPairs - 3], mainDist)) ++ break; ++ numPairs -= 2; ++ mainLen = matches[numPairs - 2]; ++ mainDist = matches[numPairs - 1]; ++ } ++ if (mainLen == 2 && mainDist >= 0x80) ++ mainLen = 1; ++ } ++ ++ if (repLen >= 2 && ( ++ (repLen + 1 >= mainLen) || ++ (repLen + 2 >= mainLen && mainDist >= (1 << 9)) || ++ (repLen + 3 >= mainLen && mainDist >= (1 << 15)))) ++ { ++ *backRes = repIndex; ++ MovePos(p, repLen - 1); ++ return repLen; ++ } ++ ++ if (mainLen < 2 || numAvail <= 2) ++ return 1; ++ ++ p->longestMatchLength = ReadMatchDistances(p, &p->numPairs); ++ if (p->longestMatchLength >= 2) ++ { ++ UInt32 newDistance = matches[p->numPairs - 1]; ++ if ((p->longestMatchLength >= mainLen && newDistance < mainDist) || ++ (p->longestMatchLength == mainLen + 1 && !ChangePair(mainDist, newDistance)) || ++ (p->longestMatchLength > mainLen + 1) || ++ (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist))) ++ return 1; ++ } ++ ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 len, limit; ++ const Byte *data2 = data - (p->reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ limit = mainLen - 1; ++ for (len = 2; len < limit && data[len] == data2[len]; len++); ++ if (len >= limit) ++ return 1; ++ } ++ *backRes = mainDist + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 2); ++ return mainLen; ++} ++ ++static void WriteEndMarker(CLzmaEnc *p, UInt32 posState) ++{ ++ UInt32 len; ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); ++ p->state = kMatchNextStates[p->state]; ++ len = LZMA_MATCH_LEN_MIN; ++ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1); ++ RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits); ++ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask); ++} ++ ++static SRes CheckErrors(CLzmaEnc *p) ++{ ++ if (p->result != SZ_OK) ++ return p->result; ++ if (p->rc.res != SZ_OK) ++ p->result = SZ_ERROR_WRITE; ++ if (p->matchFinderBase.result != SZ_OK) ++ p->result = SZ_ERROR_READ; ++ if (p->result != SZ_OK) ++ p->finished = True; ++ return p->result; ++} ++ ++static SRes Flush(CLzmaEnc *p, UInt32 nowPos) ++{ ++ /* ReleaseMFStream(); */ ++ p->finished = True; ++ if (p->writeEndMark) ++ WriteEndMarker(p, nowPos & p->pbMask); ++ RangeEnc_FlushData(&p->rc); ++ RangeEnc_FlushStream(&p->rc); ++ return CheckErrors(p); ++} ++ ++static void FillAlignPrices(CLzmaEnc *p) ++{ ++ UInt32 i; ++ for (i = 0; i < kAlignTableSize; i++) ++ p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices); ++ p->alignPriceCount = 0; ++} ++ ++static void FillDistancesPrices(CLzmaEnc *p) ++{ ++ UInt32 tempPrices[kNumFullDistances]; ++ UInt32 i, lenToPosState; ++ for (i = kStartPosModelIndex; i < kNumFullDistances; i++) ++ { ++ UInt32 posSlot = GetPosSlot1(i); ++ UInt32 footerBits = ((posSlot >> 1) - 1); ++ UInt32 base = ((2 | (posSlot & 1)) << footerBits); ++ tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices); ++ } ++ ++ for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++) ++ { ++ UInt32 posSlot; ++ const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState]; ++ UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState]; ++ for (posSlot = 0; posSlot < p->distTableSize; posSlot++) ++ posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices); ++ for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++) ++ posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits); ++ ++ { ++ UInt32 *distancesPrices = p->distancesPrices[lenToPosState]; ++ UInt32 i; ++ for (i = 0; i < kStartPosModelIndex; i++) ++ distancesPrices[i] = posSlotPrices[i]; ++ for (; i < kNumFullDistances; i++) ++ distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i]; ++ } ++ } ++ p->matchPriceCount = 0; ++} ++ ++void LzmaEnc_Construct(CLzmaEnc *p) ++{ ++ RangeEnc_Construct(&p->rc); ++ MatchFinder_Construct(&p->matchFinderBase); ++ #ifndef _7ZIP_ST ++ MatchFinderMt_Construct(&p->matchFinderMt); ++ p->matchFinderMt.MatchFinder = &p->matchFinderBase; ++ #endif ++ ++ { ++ CLzmaEncProps props; ++ LzmaEncProps_Init(&props); ++ LzmaEnc_SetProps(p, &props); ++ } ++ ++ #ifndef LZMA_LOG_BSR ++ LzmaEnc_FastPosInit(p->g_FastPos); ++ #endif ++ ++ LzmaEnc_InitPriceTables(p->ProbPrices); ++ p->litProbs = 0; ++ p->saveState.litProbs = 0; ++} ++ ++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc) ++{ ++ void *p; ++ p = alloc->Alloc(alloc, sizeof(CLzmaEnc)); ++ if (p != 0) ++ LzmaEnc_Construct((CLzmaEnc *)p); ++ return p; ++} ++ ++void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->litProbs); ++ alloc->Free(alloc, p->saveState.litProbs); ++ p->litProbs = 0; ++ p->saveState.litProbs = 0; ++} ++ ++void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ #ifndef _7ZIP_ST ++ MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); ++ #endif ++ MatchFinder_Free(&p->matchFinderBase, allocBig); ++ LzmaEnc_FreeLits(p, alloc); ++ RangeEnc_Free(&p->rc, alloc); ++} ++ ++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig); ++ alloc->Free(alloc, p); ++} ++ ++static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize) ++{ ++ UInt32 nowPos32, startPos32; ++ if (p->needInit) ++ { ++ p->matchFinder.Init(p->matchFinderObj); ++ p->needInit = 0; ++ } ++ ++ if (p->finished) ++ return p->result; ++ RINOK(CheckErrors(p)); ++ ++ nowPos32 = (UInt32)p->nowPos64; ++ startPos32 = nowPos32; ++ ++ if (p->nowPos64 == 0) ++ { ++ UInt32 numPairs; ++ Byte curByte; ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) ++ return Flush(p, nowPos32); ++ ReadMatchDistances(p, &numPairs); ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0); ++ p->state = kLiteralNextStates[p->state]; ++ curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset); ++ LitEnc_Encode(&p->rc, p->litProbs, curByte); ++ p->additionalOffset--; ++ nowPos32++; ++ } ++ ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0) ++ for (;;) ++ { ++ UInt32 pos, len, posState; ++ ++ if (p->fastMode) ++ len = GetOptimumFast(p, &pos); ++ else ++ len = GetOptimum(p, nowPos32, &pos); ++ ++ #ifdef SHOW_STAT2 ++ printf("\n pos = %4X, len = %d pos = %d", nowPos32, len, pos); ++ #endif ++ ++ posState = nowPos32 & p->pbMask; ++ if (len == 1 && pos == (UInt32)-1) ++ { ++ Byte curByte; ++ CLzmaProb *probs; ++ const Byte *data; ++ ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0); ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; ++ curByte = *data; ++ probs = LIT_PROBS(nowPos32, *(data - 1)); ++ if (IsCharState(p->state)) ++ LitEnc_Encode(&p->rc, probs, curByte); ++ else ++ LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1)); ++ p->state = kLiteralNextStates[p->state]; ++ } ++ else ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); ++ if (pos < LZMA_NUM_REPS) ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1); ++ if (pos == 0) ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0); ++ RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1)); ++ } ++ else ++ { ++ UInt32 distance = p->reps[pos]; ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1); ++ if (pos == 1) ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0); ++ else ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1); ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2); ++ if (pos == 3) ++ p->reps[3] = p->reps[2]; ++ p->reps[2] = p->reps[1]; ++ } ++ p->reps[1] = p->reps[0]; ++ p->reps[0] = distance; ++ } ++ if (len == 1) ++ p->state = kShortRepNextStates[p->state]; ++ else ++ { ++ LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ p->state = kRepNextStates[p->state]; ++ } ++ } ++ else ++ { ++ UInt32 posSlot; ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); ++ p->state = kMatchNextStates[p->state]; ++ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ pos -= LZMA_NUM_REPS; ++ GetPosSlot(pos, posSlot); ++ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot); ++ ++ if (posSlot >= kStartPosModelIndex) ++ { ++ UInt32 footerBits = ((posSlot >> 1) - 1); ++ UInt32 base = ((2 | (posSlot & 1)) << footerBits); ++ UInt32 posReduced = pos - base; ++ ++ if (posSlot < kEndPosModelIndex) ++ RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced); ++ else ++ { ++ RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits); ++ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask); ++ p->alignPriceCount++; ++ } ++ } ++ p->reps[3] = p->reps[2]; ++ p->reps[2] = p->reps[1]; ++ p->reps[1] = p->reps[0]; ++ p->reps[0] = pos; ++ p->matchPriceCount++; ++ } ++ } ++ p->additionalOffset -= len; ++ nowPos32 += len; ++ if (p->additionalOffset == 0) ++ { ++ UInt32 processed; ++ if (!p->fastMode) ++ { ++ if (p->matchPriceCount >= (1 << 7)) ++ FillDistancesPrices(p); ++ if (p->alignPriceCount >= kAlignTableSize) ++ FillAlignPrices(p); ++ } ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) ++ break; ++ processed = nowPos32 - startPos32; ++ if (useLimits) ++ { ++ if (processed + kNumOpts + 300 >= maxUnpackSize || ++ RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize) ++ break; ++ } ++ else if (processed >= (1 << 15)) ++ { ++ p->nowPos64 += nowPos32 - startPos32; ++ return CheckErrors(p); ++ } ++ } ++ } ++ p->nowPos64 += nowPos32 - startPos32; ++ return Flush(p, nowPos32); ++} ++ ++#define kBigHashDicLimit ((UInt32)1 << 24) ++ ++static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ UInt32 beforeSize = kNumOpts; ++ Bool btMode; ++ if (!RangeEnc_Alloc(&p->rc, alloc)) ++ return SZ_ERROR_MEM; ++ btMode = (p->matchFinderBase.btMode != 0); ++ #ifndef _7ZIP_ST ++ p->mtMode = (p->multiThread && !p->fastMode && btMode); ++ #endif ++ ++ { ++ unsigned lclp = p->lc + p->lp; ++ if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp) ++ { ++ LzmaEnc_FreeLits(p, alloc); ++ p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); ++ p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); ++ if (p->litProbs == 0 || p->saveState.litProbs == 0) ++ { ++ LzmaEnc_FreeLits(p, alloc); ++ return SZ_ERROR_MEM; ++ } ++ p->lclp = lclp; ++ } ++ } ++ ++ p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit); ++ ++ if (beforeSize + p->dictSize < keepWindowSize) ++ beforeSize = keepWindowSize - p->dictSize; ++ ++ #ifndef _7ZIP_ST ++ if (p->mtMode) ++ { ++ RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)); ++ p->matchFinderObj = &p->matchFinderMt; ++ MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder); ++ } ++ else ++ #endif ++ { ++ if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)) ++ return SZ_ERROR_MEM; ++ p->matchFinderObj = &p->matchFinderBase; ++ MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder); ++ } ++ return SZ_OK; ++} ++ ++void LzmaEnc_Init(CLzmaEnc *p) ++{ ++ UInt32 i; ++ p->state = 0; ++ for (i = 0 ; i < LZMA_NUM_REPS; i++) ++ p->reps[i] = 0; ++ ++ RangeEnc_Init(&p->rc); ++ ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ UInt32 j; ++ for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++) ++ { ++ p->isMatch[i][j] = kProbInitValue; ++ p->isRep0Long[i][j] = kProbInitValue; ++ } ++ p->isRep[i] = kProbInitValue; ++ p->isRepG0[i] = kProbInitValue; ++ p->isRepG1[i] = kProbInitValue; ++ p->isRepG2[i] = kProbInitValue; ++ } ++ ++ { ++ UInt32 num = 0x300 << (p->lp + p->lc); ++ for (i = 0; i < num; i++) ++ p->litProbs[i] = kProbInitValue; ++ } ++ ++ { ++ for (i = 0; i < kNumLenToPosStates; i++) ++ { ++ CLzmaProb *probs = p->posSlotEncoder[i]; ++ UInt32 j; ++ for (j = 0; j < (1 << kNumPosSlotBits); j++) ++ probs[j] = kProbInitValue; ++ } ++ } ++ { ++ for (i = 0; i < kNumFullDistances - kEndPosModelIndex; i++) ++ p->posEncoders[i] = kProbInitValue; ++ } ++ ++ LenEnc_Init(&p->lenEnc.p); ++ LenEnc_Init(&p->repLenEnc.p); ++ ++ for (i = 0; i < (1 << kNumAlignBits); i++) ++ p->posAlignEncoder[i] = kProbInitValue; ++ ++ p->optimumEndIndex = 0; ++ p->optimumCurrentIndex = 0; ++ p->additionalOffset = 0; ++ ++ p->pbMask = (1 << p->pb) - 1; ++ p->lpMask = (1 << p->lp) - 1; ++} ++ ++void LzmaEnc_InitPrices(CLzmaEnc *p) ++{ ++ if (!p->fastMode) ++ { ++ FillDistancesPrices(p); ++ FillAlignPrices(p); ++ } ++ ++ p->lenEnc.tableSize = ++ p->repLenEnc.tableSize = ++ p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN; ++ LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices); ++ LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices); ++} ++ ++static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ UInt32 i; ++ for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++) ++ if (p->dictSize <= ((UInt32)1 << i)) ++ break; ++ p->distTableSize = i * 2; ++ ++ p->finished = False; ++ p->result = SZ_OK; ++ RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig)); ++ LzmaEnc_Init(p); ++ LzmaEnc_InitPrices(p); ++ p->nowPos64 = 0; ++ return SZ_OK; ++} ++ ++static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ p->matchFinderBase.stream = inStream; ++ p->needInit = 1; ++ p->rc.outStream = outStream; ++ return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig); ++} ++ ++SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, ++ ISeqInStream *inStream, UInt32 keepWindowSize, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ p->matchFinderBase.stream = inStream; ++ p->needInit = 1; ++ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); ++} ++ ++static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) ++{ ++ p->matchFinderBase.directInput = 1; ++ p->matchFinderBase.bufferBase = (Byte *)src; ++ p->matchFinderBase.directInputRem = srcLen; ++} ++ ++SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, ++ UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ LzmaEnc_SetInputBuf(p, src, srcLen); ++ p->needInit = 1; ++ ++ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); ++} ++ ++void LzmaEnc_Finish(CLzmaEncHandle pp) ++{ ++ #ifndef _7ZIP_ST ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ if (p->mtMode) ++ MatchFinderMt_ReleaseStream(&p->matchFinderMt); ++ #else ++ pp = pp; ++ #endif ++} ++ ++typedef struct ++{ ++ ISeqOutStream funcTable; ++ Byte *data; ++ SizeT rem; ++ Bool overflow; ++} CSeqOutStreamBuf; ++ ++static size_t MyWrite(void *pp, const void *data, size_t size) ++{ ++ CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp; ++ if (p->rem < size) ++ { ++ size = p->rem; ++ p->overflow = True; ++ } ++ memcpy(p->data, data, size); ++ p->rem -= size; ++ p->data += size; ++ return size; ++} ++ ++ ++UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp) ++{ ++ const CLzmaEnc *p = (CLzmaEnc *)pp; ++ return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); ++} ++ ++const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp) ++{ ++ const CLzmaEnc *p = (CLzmaEnc *)pp; ++ return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; ++} ++ ++SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, ++ Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ UInt64 nowPos64; ++ SRes res; ++ CSeqOutStreamBuf outStream; ++ ++ outStream.funcTable.Write = MyWrite; ++ outStream.data = dest; ++ outStream.rem = *destLen; ++ outStream.overflow = False; ++ ++ p->writeEndMark = False; ++ p->finished = False; ++ p->result = SZ_OK; ++ ++ if (reInit) ++ LzmaEnc_Init(p); ++ LzmaEnc_InitPrices(p); ++ nowPos64 = p->nowPos64; ++ RangeEnc_Init(&p->rc); ++ p->rc.outStream = &outStream.funcTable; ++ ++ res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize); ++ ++ *unpackSize = (UInt32)(p->nowPos64 - nowPos64); ++ *destLen -= outStream.rem; ++ if (outStream.overflow) ++ return SZ_ERROR_OUTPUT_EOF; ++ ++ return res; ++} ++ ++static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) ++{ ++ SRes res = SZ_OK; ++ ++ #ifndef _7ZIP_ST ++ Byte allocaDummy[0x300]; ++ int i = 0; ++ for (i = 0; i < 16; i++) ++ allocaDummy[i] = (Byte)i; ++ #endif ++ ++ for (;;) ++ { ++ res = LzmaEnc_CodeOneBlock(p, False, 0, 0); ++ if (res != SZ_OK || p->finished != 0) ++ break; ++ if (progress != 0) ++ { ++ res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc)); ++ if (res != SZ_OK) ++ { ++ res = SZ_ERROR_PROGRESS; ++ break; ++ } ++ } ++ } ++ LzmaEnc_Finish(p); ++ return res; ++} ++ ++SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig)); ++ return LzmaEnc_Encode2((CLzmaEnc *)pp, progress); ++} ++ ++SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ int i; ++ UInt32 dictSize = p->dictSize; ++ if (*size < LZMA_PROPS_SIZE) ++ return SZ_ERROR_PARAM; ++ *size = LZMA_PROPS_SIZE; ++ props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc); ++ ++ for (i = 11; i <= 30; i++) ++ { ++ if (dictSize <= ((UInt32)2 << i)) ++ { ++ dictSize = (2 << i); ++ break; ++ } ++ if (dictSize <= ((UInt32)3 << i)) ++ { ++ dictSize = (3 << i); ++ break; ++ } ++ } ++ ++ for (i = 0; i < 4; i++) ++ props[1 + i] = (Byte)(dictSize >> (8 * i)); ++ return SZ_OK; ++} ++ ++SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ SRes res; ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ ++ CSeqOutStreamBuf outStream; ++ ++ LzmaEnc_SetInputBuf(p, src, srcLen); ++ ++ outStream.funcTable.Write = MyWrite; ++ outStream.data = dest; ++ outStream.rem = *destLen; ++ outStream.overflow = False; ++ ++ p->writeEndMark = writeEndMark; ++ ++ p->rc.outStream = &outStream.funcTable; ++ res = LzmaEnc_MemPrepare(pp, src, srcLen, 0, alloc, allocBig); ++ if (res == SZ_OK) ++ res = LzmaEnc_Encode2(p, progress); ++ ++ *destLen -= outStream.rem; ++ if (outStream.overflow) ++ return SZ_ERROR_OUTPUT_EOF; ++ return res; ++} ++ ++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc); ++ SRes res; ++ if (p == 0) ++ return SZ_ERROR_MEM; ++ ++ res = LzmaEnc_SetProps(p, props); ++ if (res == SZ_OK) ++ { ++ res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize); ++ if (res == SZ_OK) ++ res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen, ++ writeEndMark, progress, alloc, allocBig); ++ } ++ ++ LzmaEnc_Destroy(p, alloc, allocBig); ++ return res; ++} +--- /dev/null ++++ b/lib/lzma/Makefile +@@ -0,0 +1,7 @@ ++lzma_compress-objs := LzFind.o LzmaEnc.o ++lzma_decompress-objs := LzmaDec.o ++ ++obj-$(CONFIG_LZMA_COMPRESS) += lzma_compress.o ++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma_decompress.o ++ ++EXTRA_CFLAGS += -Iinclude/linux -Iinclude/linux/lzma -include types.h diff --git a/target/linux/generic/patches-4.1/531-debloat_lzma.patch b/target/linux/generic/patches-4.1/531-debloat_lzma.patch new file mode 100644 index 0000000..aa3c498 --- /dev/null +++ b/target/linux/generic/patches-4.1/531-debloat_lzma.patch @@ -0,0 +1,1024 @@ +--- a/include/linux/lzma/LzmaDec.h ++++ b/include/linux/lzma/LzmaDec.h +@@ -31,14 +31,6 @@ typedef struct _CLzmaProps + UInt32 dicSize; + } CLzmaProps; + +-/* LzmaProps_Decode - decodes properties +-Returns: +- SZ_OK +- SZ_ERROR_UNSUPPORTED - Unsupported properties +-*/ +- +-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); +- + + /* ---------- LZMA Decoder state ---------- */ + +@@ -70,8 +62,6 @@ typedef struct + + #define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } + +-void LzmaDec_Init(CLzmaDec *p); +- + /* There are two types of LZMA streams: + 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. + 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ +@@ -108,97 +98,6 @@ typedef enum + + /* ELzmaStatus is used only as output value for function call */ + +- +-/* ---------- Interfaces ---------- */ +- +-/* There are 3 levels of interfaces: +- 1) Dictionary Interface +- 2) Buffer Interface +- 3) One Call Interface +- You can select any of these interfaces, but don't mix functions from different +- groups for same object. */ +- +- +-/* There are two variants to allocate state for Dictionary Interface: +- 1) LzmaDec_Allocate / LzmaDec_Free +- 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs +- You can use variant 2, if you set dictionary buffer manually. +- For Buffer Interface you must always use variant 1. +- +-LzmaDec_Allocate* can return: +- SZ_OK +- SZ_ERROR_MEM - Memory allocation error +- SZ_ERROR_UNSUPPORTED - Unsupported properties +-*/ +- +-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); +-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); +- +-SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); +-void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); +- +-/* ---------- Dictionary Interface ---------- */ +- +-/* You can use it, if you want to eliminate the overhead for data copying from +- dictionary to some other external buffer. +- You must work with CLzmaDec variables directly in this interface. +- +- STEPS: +- LzmaDec_Constr() +- LzmaDec_Allocate() +- for (each new stream) +- { +- LzmaDec_Init() +- while (it needs more decompression) +- { +- LzmaDec_DecodeToDic() +- use data from CLzmaDec::dic and update CLzmaDec::dicPos +- } +- } +- LzmaDec_Free() +-*/ +- +-/* LzmaDec_DecodeToDic +- +- The decoding to internal dictionary buffer (CLzmaDec::dic). +- You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! +- +-finishMode: +- It has meaning only if the decoding reaches output limit (dicLimit). +- LZMA_FINISH_ANY - Decode just dicLimit bytes. +- LZMA_FINISH_END - Stream must be finished after dicLimit. +- +-Returns: +- SZ_OK +- status: +- LZMA_STATUS_FINISHED_WITH_MARK +- LZMA_STATUS_NOT_FINISHED +- LZMA_STATUS_NEEDS_MORE_INPUT +- LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK +- SZ_ERROR_DATA - Data error +-*/ +- +-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, +- const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); +- +- +-/* ---------- Buffer Interface ---------- */ +- +-/* It's zlib-like interface. +- See LzmaDec_DecodeToDic description for information about STEPS and return results, +- but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need +- to work with CLzmaDec variables manually. +- +-finishMode: +- It has meaning only if the decoding reaches output limit (*destLen). +- LZMA_FINISH_ANY - Decode just destLen bytes. +- LZMA_FINISH_END - Stream must be finished after (*destLen). +-*/ +- +-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, +- const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); +- +- + /* ---------- One Call Interface ---------- */ + + /* LzmaDecode +--- a/lib/lzma/LzmaDec.c ++++ b/lib/lzma/LzmaDec.c +@@ -682,7 +682,7 @@ static void LzmaDec_InitRc(CLzmaDec *p, + p->needFlush = 0; + } + +-void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) ++static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) + { + p->needFlush = 1; + p->remainLen = 0; +@@ -698,7 +698,7 @@ void LzmaDec_InitDicAndState(CLzmaDec *p + p->needInitState = 1; + } + +-void LzmaDec_Init(CLzmaDec *p) ++static void LzmaDec_Init(CLzmaDec *p) + { + p->dicPos = 0; + LzmaDec_InitDicAndState(p, True, True); +@@ -716,7 +716,7 @@ static void LzmaDec_InitStateReal(CLzmaD + p->needInitState = 0; + } + +-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, ++static SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, + ELzmaFinishMode finishMode, ELzmaStatus *status) + { + SizeT inSize = *srcLen; +@@ -837,65 +837,13 @@ SRes LzmaDec_DecodeToDic(CLzmaDec *p, Si + return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; + } + +-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) +-{ +- SizeT outSize = *destLen; +- SizeT inSize = *srcLen; +- *srcLen = *destLen = 0; +- for (;;) +- { +- SizeT inSizeCur = inSize, outSizeCur, dicPos; +- ELzmaFinishMode curFinishMode; +- SRes res; +- if (p->dicPos == p->dicBufSize) +- p->dicPos = 0; +- dicPos = p->dicPos; +- if (outSize > p->dicBufSize - dicPos) +- { +- outSizeCur = p->dicBufSize; +- curFinishMode = LZMA_FINISH_ANY; +- } +- else +- { +- outSizeCur = dicPos + outSize; +- curFinishMode = finishMode; +- } +- +- res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); +- src += inSizeCur; +- inSize -= inSizeCur; +- *srcLen += inSizeCur; +- outSizeCur = p->dicPos - dicPos; +- memcpy(dest, p->dic + dicPos, outSizeCur); +- dest += outSizeCur; +- outSize -= outSizeCur; +- *destLen += outSizeCur; +- if (res != 0) +- return res; +- if (outSizeCur == 0 || outSize == 0) +- return SZ_OK; +- } +-} +- +-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) ++static void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) + { + alloc->Free(alloc, p->probs); + p->probs = 0; + } + +-static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) +-{ +- alloc->Free(alloc, p->dic); +- p->dic = 0; +-} +- +-void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) +-{ +- LzmaDec_FreeProbs(p, alloc); +- LzmaDec_FreeDict(p, alloc); +-} +- +-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) ++static SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) + { + UInt32 dicSize; + Byte d; +@@ -935,7 +883,7 @@ static SRes LzmaDec_AllocateProbs2(CLzma + return SZ_OK; + } + +-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++static SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) + { + CLzmaProps propNew; + RINOK(LzmaProps_Decode(&propNew, props, propsSize)); +@@ -943,28 +891,6 @@ SRes LzmaDec_AllocateProbs(CLzmaDec *p, + p->prop = propNew; + return SZ_OK; + } +- +-SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) +-{ +- CLzmaProps propNew; +- SizeT dicBufSize; +- RINOK(LzmaProps_Decode(&propNew, props, propsSize)); +- RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); +- dicBufSize = propNew.dicSize; +- if (p->dic == 0 || dicBufSize != p->dicBufSize) +- { +- LzmaDec_FreeDict(p, alloc); +- p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); +- if (p->dic == 0) +- { +- LzmaDec_FreeProbs(p, alloc); +- return SZ_ERROR_MEM; +- } +- } +- p->dicBufSize = dicBufSize; +- p->prop = propNew; +- return SZ_OK; +-} + + SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, + const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, +--- a/include/linux/lzma/LzmaEnc.h ++++ b/include/linux/lzma/LzmaEnc.h +@@ -31,9 +31,6 @@ typedef struct _CLzmaEncProps + } CLzmaEncProps; + + void LzmaEncProps_Init(CLzmaEncProps *p); +-void LzmaEncProps_Normalize(CLzmaEncProps *p); +-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2); +- + + /* ---------- CLzmaEncHandle Interface ---------- */ + +@@ -53,26 +50,9 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc * + void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); + SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); + SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); +-SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); + SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, + int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); + +-/* ---------- One Call Interface ---------- */ +- +-/* LzmaEncode +-Return code: +- SZ_OK - OK +- SZ_ERROR_MEM - Memory allocation error +- SZ_ERROR_PARAM - Incorrect paramater +- SZ_ERROR_OUTPUT_EOF - output buffer overflow +- SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) +-*/ +- +-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, +- const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); +- + #ifdef __cplusplus + } + #endif +--- a/lib/lzma/LzmaEnc.c ++++ b/lib/lzma/LzmaEnc.c +@@ -53,7 +53,7 @@ void LzmaEncProps_Init(CLzmaEncProps *p) + p->writeEndMark = 0; + } + +-void LzmaEncProps_Normalize(CLzmaEncProps *p) ++static void LzmaEncProps_Normalize(CLzmaEncProps *p) + { + int level = p->level; + if (level < 0) level = 5; +@@ -76,7 +76,7 @@ void LzmaEncProps_Normalize(CLzmaEncProp + #endif + } + +-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) ++static UInt32 __maybe_unused LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) + { + CLzmaEncProps props = *props2; + LzmaEncProps_Normalize(&props); +@@ -93,7 +93,7 @@ UInt32 LzmaEncProps_GetDictSize(const CL + + #define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } + +-UInt32 GetPosSlot1(UInt32 pos) ++static UInt32 GetPosSlot1(UInt32 pos) + { + UInt32 res; + BSR2_RET(pos, res); +@@ -107,7 +107,7 @@ UInt32 GetPosSlot1(UInt32 pos) + #define kNumLogBits (9 + (int)sizeof(size_t) / 2) + #define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) + +-void LzmaEnc_FastPosInit(Byte *g_FastPos) ++static void LzmaEnc_FastPosInit(Byte *g_FastPos) + { + int c = 2, slotFast; + g_FastPos[0] = 0; +@@ -339,58 +339,6 @@ typedef struct + CSaveState saveState; + } CLzmaEnc; + +-void LzmaEnc_SaveState(CLzmaEncHandle pp) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- CSaveState *dest = &p->saveState; +- int i; +- dest->lenEnc = p->lenEnc; +- dest->repLenEnc = p->repLenEnc; +- dest->state = p->state; +- +- for (i = 0; i < kNumStates; i++) +- { +- memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); +- memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); +- } +- for (i = 0; i < kNumLenToPosStates; i++) +- memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); +- memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); +- memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); +- memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); +- memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); +- memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); +- memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); +- memcpy(dest->reps, p->reps, sizeof(p->reps)); +- memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb)); +-} +- +-void LzmaEnc_RestoreState(CLzmaEncHandle pp) +-{ +- CLzmaEnc *dest = (CLzmaEnc *)pp; +- const CSaveState *p = &dest->saveState; +- int i; +- dest->lenEnc = p->lenEnc; +- dest->repLenEnc = p->repLenEnc; +- dest->state = p->state; +- +- for (i = 0; i < kNumStates; i++) +- { +- memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); +- memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); +- } +- for (i = 0; i < kNumLenToPosStates; i++) +- memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); +- memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); +- memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); +- memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); +- memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); +- memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); +- memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); +- memcpy(dest->reps, p->reps, sizeof(p->reps)); +- memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb)); +-} +- + SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -600,7 +548,7 @@ static void LitEnc_EncodeMatched(CRangeE + while (symbol < 0x10000); + } + +-void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) ++static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) + { + UInt32 i; + for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) +@@ -1676,7 +1624,7 @@ static void FillDistancesPrices(CLzmaEnc + p->matchPriceCount = 0; + } + +-void LzmaEnc_Construct(CLzmaEnc *p) ++static void LzmaEnc_Construct(CLzmaEnc *p) + { + RangeEnc_Construct(&p->rc); + MatchFinder_Construct(&p->matchFinderBase); +@@ -1709,7 +1657,7 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc * + return p; + } + +-void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) ++static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) + { + alloc->Free(alloc, p->litProbs); + alloc->Free(alloc, p->saveState.litProbs); +@@ -1717,7 +1665,7 @@ void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAl + p->saveState.litProbs = 0; + } + +-void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) ++static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) + { + #ifndef _7ZIP_ST + MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); +@@ -1947,7 +1895,7 @@ static SRes LzmaEnc_Alloc(CLzmaEnc *p, U + return SZ_OK; + } + +-void LzmaEnc_Init(CLzmaEnc *p) ++static void LzmaEnc_Init(CLzmaEnc *p) + { + UInt32 i; + p->state = 0; +@@ -2005,7 +1953,7 @@ void LzmaEnc_Init(CLzmaEnc *p) + p->lpMask = (1 << p->lp) - 1; + } + +-void LzmaEnc_InitPrices(CLzmaEnc *p) ++static void LzmaEnc_InitPrices(CLzmaEnc *p) + { + if (!p->fastMode) + { +@@ -2037,26 +1985,6 @@ static SRes LzmaEnc_AllocAndInit(CLzmaEn + return SZ_OK; + } + +-static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- p->matchFinderBase.stream = inStream; +- p->needInit = 1; +- p->rc.outStream = outStream; +- return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig); +-} +- +-SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, +- ISeqInStream *inStream, UInt32 keepWindowSize, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- p->matchFinderBase.stream = inStream; +- p->needInit = 1; +- return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); +-} +- + static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) + { + p->matchFinderBase.directInput = 1; +@@ -2064,7 +1992,7 @@ static void LzmaEnc_SetInputBuf(CLzmaEnc + p->matchFinderBase.directInputRem = srcLen; + } + +-SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, ++static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, + UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2074,7 +2002,7 @@ SRes LzmaEnc_MemPrepare(CLzmaEncHandle p + return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); + } + +-void LzmaEnc_Finish(CLzmaEncHandle pp) ++static void LzmaEnc_Finish(CLzmaEncHandle pp) + { + #ifndef _7ZIP_ST + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2107,53 +2035,6 @@ static size_t MyWrite(void *pp, const vo + return size; + } + +- +-UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp) +-{ +- const CLzmaEnc *p = (CLzmaEnc *)pp; +- return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); +-} +- +-const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp) +-{ +- const CLzmaEnc *p = (CLzmaEnc *)pp; +- return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; +-} +- +-SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, +- Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- UInt64 nowPos64; +- SRes res; +- CSeqOutStreamBuf outStream; +- +- outStream.funcTable.Write = MyWrite; +- outStream.data = dest; +- outStream.rem = *destLen; +- outStream.overflow = False; +- +- p->writeEndMark = False; +- p->finished = False; +- p->result = SZ_OK; +- +- if (reInit) +- LzmaEnc_Init(p); +- LzmaEnc_InitPrices(p); +- nowPos64 = p->nowPos64; +- RangeEnc_Init(&p->rc); +- p->rc.outStream = &outStream.funcTable; +- +- res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize); +- +- *unpackSize = (UInt32)(p->nowPos64 - nowPos64); +- *destLen -= outStream.rem; +- if (outStream.overflow) +- return SZ_ERROR_OUTPUT_EOF; +- +- return res; +-} +- + static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) + { + SRes res = SZ_OK; +@@ -2184,13 +2065,6 @@ static SRes LzmaEnc_Encode2(CLzmaEnc *p, + return res; + } + +-SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig)); +- return LzmaEnc_Encode2((CLzmaEnc *)pp, progress); +-} +- + SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2247,25 +2121,3 @@ SRes LzmaEnc_MemEncode(CLzmaEncHandle pp + return SZ_ERROR_OUTPUT_EOF; + return res; + } +- +-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, +- const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc); +- SRes res; +- if (p == 0) +- return SZ_ERROR_MEM; +- +- res = LzmaEnc_SetProps(p, props); +- if (res == SZ_OK) +- { +- res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize); +- if (res == SZ_OK) +- res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen, +- writeEndMark, progress, alloc, allocBig); +- } +- +- LzmaEnc_Destroy(p, alloc, allocBig); +- return res; +-} +--- a/include/linux/lzma/LzFind.h ++++ b/include/linux/lzma/LzFind.h +@@ -55,11 +55,6 @@ typedef struct _CMatchFinder + + #define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) + +-int MatchFinder_NeedMove(CMatchFinder *p); +-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p); +-void MatchFinder_MoveBlock(CMatchFinder *p); +-void MatchFinder_ReadIfRequired(CMatchFinder *p); +- + void MatchFinder_Construct(CMatchFinder *p); + + /* Conditions: +@@ -70,12 +65,6 @@ int MatchFinder_Create(CMatchFinder *p, + UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, + ISzAlloc *alloc); + void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); +-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems); +-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue); +- +-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, +- UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, +- UInt32 *distances, UInt32 maxLen); + + /* + Conditions: +@@ -102,12 +91,6 @@ typedef struct _IMatchFinder + + void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); + +-void MatchFinder_Init(CMatchFinder *p); +-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); +-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); +-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); +-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); +- + #ifdef __cplusplus + } + #endif +--- a/lib/lzma/LzFind.c ++++ b/lib/lzma/LzFind.c +@@ -14,9 +14,15 @@ + + #define kStartMaxLen 3 + ++#if 0 ++#define DIRECT_INPUT p->directInput ++#else ++#define DIRECT_INPUT 1 ++#endif ++ + static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) + { +- if (!p->directInput) ++ if (!DIRECT_INPUT) + { + alloc->Free(alloc, p->bufferBase); + p->bufferBase = 0; +@@ -28,7 +34,7 @@ static void LzInWindow_Free(CMatchFinder + static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) + { + UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; +- if (p->directInput) ++ if (DIRECT_INPUT) + { + p->blockSize = blockSize; + return 1; +@@ -42,12 +48,12 @@ static int LzInWindow_Create(CMatchFinde + return (p->bufferBase != 0); + } + +-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } +-Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } ++static Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } ++static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } + +-UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } ++static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } + +-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) ++static void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) + { + p->posLimit -= subValue; + p->pos -= subValue; +@@ -58,7 +64,7 @@ static void MatchFinder_ReadBlock(CMatch + { + if (p->streamEndWasReached || p->result != SZ_OK) + return; +- if (p->directInput) ++ if (DIRECT_INPUT) + { + UInt32 curSize = 0xFFFFFFFF - p->streamPos; + if (curSize > p->directInputRem) +@@ -89,7 +95,7 @@ static void MatchFinder_ReadBlock(CMatch + } + } + +-void MatchFinder_MoveBlock(CMatchFinder *p) ++static void MatchFinder_MoveBlock(CMatchFinder *p) + { + memmove(p->bufferBase, + p->buffer - p->keepSizeBefore, +@@ -97,22 +103,14 @@ void MatchFinder_MoveBlock(CMatchFinder + p->buffer = p->bufferBase + p->keepSizeBefore; + } + +-int MatchFinder_NeedMove(CMatchFinder *p) ++static int MatchFinder_NeedMove(CMatchFinder *p) + { +- if (p->directInput) ++ if (DIRECT_INPUT) + return 0; + /* if (p->streamEndWasReached) return 0; */ + return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); + } + +-void MatchFinder_ReadIfRequired(CMatchFinder *p) +-{ +- if (p->streamEndWasReached) +- return; +- if (p->keepSizeAfter >= p->streamPos - p->pos) +- MatchFinder_ReadBlock(p); +-} +- + static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) + { + if (MatchFinder_NeedMove(p)) +@@ -268,7 +266,7 @@ static void MatchFinder_SetLimits(CMatch + p->posLimit = p->pos + limit; + } + +-void MatchFinder_Init(CMatchFinder *p) ++static void MatchFinder_Init(CMatchFinder *p) + { + UInt32 i; + for (i = 0; i < p->hashSizeSum; i++) +@@ -287,7 +285,7 @@ static UInt32 MatchFinder_GetSubValue(CM + return (p->pos - p->historySize - 1) & kNormalizeMask; + } + +-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) ++static void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) + { + UInt32 i; + for (i = 0; i < numItems; i++) +@@ -319,38 +317,7 @@ static void MatchFinder_CheckLimits(CMat + MatchFinder_SetLimits(p); + } + +-static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, +- UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, +- UInt32 *distances, UInt32 maxLen) +-{ +- son[_cyclicBufferPos] = curMatch; +- for (;;) +- { +- UInt32 delta = pos - curMatch; +- if (cutValue-- == 0 || delta >= _cyclicBufferSize) +- return distances; +- { +- const Byte *pb = cur - delta; +- curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)]; +- if (pb[maxLen] == cur[maxLen] && *pb == *cur) +- { +- UInt32 len = 0; +- while (++len != lenLimit) +- if (pb[len] != cur[len]) +- break; +- if (maxLen < len) +- { +- *distances++ = maxLen = len; +- *distances++ = delta - 1; +- if (len == lenLimit) +- return distances; +- } +- } +- } +- } +-} +- +-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++static UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, + UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, + UInt32 *distances, UInt32 maxLen) + { +@@ -460,10 +427,10 @@ static void SkipMatchesSpec(UInt32 lenLi + p->buffer++; \ + if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); + +-#define MOVE_POS_RET MOVE_POS return offset; +- + static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } + ++#define MOVE_POS_RET MatchFinder_MovePos(p); return offset; ++ + #define GET_MATCHES_HEADER2(minLen, ret_op) \ + UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ + lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ +@@ -479,62 +446,7 @@ static void MatchFinder_MovePos(CMatchFi + distances + offset, maxLen) - distances); MOVE_POS_RET; + + #define SKIP_FOOTER \ +- SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS; +- +-static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(2) +- HASH2_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = 0; +- GET_MATCHES_FOOTER(offset, 1) +-} +- +-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = 0; +- GET_MATCHES_FOOTER(offset, 2) +-} +- +-static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 hash2Value, delta2, maxLen, offset; +- GET_MATCHES_HEADER(3) +- +- HASH3_CALC; +- +- delta2 = p->pos - p->hash[hash2Value]; +- curMatch = p->hash[kFix3HashSize + hashValue]; +- +- p->hash[hash2Value] = +- p->hash[kFix3HashSize + hashValue] = p->pos; +- +- +- maxLen = 2; +- offset = 0; +- if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) +- { +- for (; maxLen != lenLimit; maxLen++) +- if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) +- break; +- distances[0] = maxLen; +- distances[1] = delta2 - 1; +- offset = 2; +- if (maxLen == lenLimit) +- { +- SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); +- MOVE_POS_RET; +- } +- } +- GET_MATCHES_FOOTER(offset, maxLen) +-} ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MatchFinder_MovePos(p); + + static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) + { +@@ -583,108 +495,6 @@ static UInt32 Bt4_MatchFinder_GetMatches + GET_MATCHES_FOOTER(offset, maxLen) + } + +-static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; +- GET_MATCHES_HEADER(4) +- +- HASH4_CALC; +- +- delta2 = p->pos - p->hash[ hash2Value]; +- delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; +- curMatch = p->hash[kFix4HashSize + hashValue]; +- +- p->hash[ hash2Value] = +- p->hash[kFix3HashSize + hash3Value] = +- p->hash[kFix4HashSize + hashValue] = p->pos; +- +- maxLen = 1; +- offset = 0; +- if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) +- { +- distances[0] = maxLen = 2; +- distances[1] = delta2 - 1; +- offset = 2; +- } +- if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) +- { +- maxLen = 3; +- distances[offset + 1] = delta3 - 1; +- offset += 2; +- delta2 = delta3; +- } +- if (offset != 0) +- { +- for (; maxLen != lenLimit; maxLen++) +- if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) +- break; +- distances[offset - 2] = maxLen; +- if (maxLen == lenLimit) +- { +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS_RET; +- } +- } +- if (maxLen < 3) +- maxLen = 3; +- offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), +- distances + offset, maxLen) - (distances)); +- MOVE_POS_RET +-} +- +-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), +- distances, 2) - (distances)); +- MOVE_POS_RET +-} +- +-static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(2) +- HASH2_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- +-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- +-static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- UInt32 hash2Value; +- SKIP_HEADER(3) +- HASH3_CALC; +- curMatch = p->hash[kFix3HashSize + hashValue]; +- p->hash[hash2Value] = +- p->hash[kFix3HashSize + hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- + static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) + { + do +@@ -701,61 +511,12 @@ static void Bt4_MatchFinder_Skip(CMatchF + while (--num != 0); + } + +-static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- UInt32 hash2Value, hash3Value; +- SKIP_HEADER(4) +- HASH4_CALC; +- curMatch = p->hash[kFix4HashSize + hashValue]; +- p->hash[ hash2Value] = +- p->hash[kFix3HashSize + hash3Value] = +- p->hash[kFix4HashSize + hashValue] = p->pos; +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS +- } +- while (--num != 0); +-} +- +-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS +- } +- while (--num != 0); +-} +- + void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) + { + vTable->Init = (Mf_Init_Func)MatchFinder_Init; + vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; + vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; + vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; +- if (!p->btMode) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip; +- } +- else if (p->numHashBytes == 2) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip; +- } +- else if (p->numHashBytes == 3) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip; +- } +- else +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; +- } ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; + } diff --git a/target/linux/generic/patches-4.1/532-jffs2_eofdetect.patch b/target/linux/generic/patches-4.1/532-jffs2_eofdetect.patch new file mode 100644 index 0000000..9cbe183 --- /dev/null +++ b/target/linux/generic/patches-4.1/532-jffs2_eofdetect.patch @@ -0,0 +1,56 @@ +--- a/fs/jffs2/build.c ++++ b/fs/jffs2/build.c +@@ -114,6 +114,16 @@ static int jffs2_build_filesystem(struct + dbg_fsbuild("scanned flash completely\n"); + jffs2_dbg_dump_block_lists_nolock(c); + ++ if (c->flags & (1 << 7)) { ++ printk("%s(): unlocking the mtd device... ", __func__); ++ mtd_unlock(c->mtd, 0, c->mtd->size); ++ printk("done.\n"); ++ ++ printk("%s(): erasing all blocks after the end marker... ", __func__); ++ jffs2_erase_pending_blocks(c, -1); ++ printk("done.\n"); ++ } ++ + dbg_fsbuild("pass 1 starting\n"); + c->flags |= JFFS2_SB_FLAG_BUILDING; + /* Now scan the directory tree, increasing nlink according to every dirent found. */ +--- a/fs/jffs2/scan.c ++++ b/fs/jffs2/scan.c +@@ -148,8 +148,14 @@ int jffs2_scan_medium(struct jffs2_sb_in + /* reset summary info for next eraseblock scan */ + jffs2_sum_reset_collected(s); + +- ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), +- buf_size, s); ++ if (c->flags & (1 << 7)) { ++ if (mtd_block_isbad(c->mtd, jeb->offset)) ++ ret = BLK_STATE_BADBLOCK; ++ else ++ ret = BLK_STATE_ALLFF; ++ } else ++ ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), ++ buf_size, s); + + if (ret < 0) + goto out; +@@ -561,6 +567,17 @@ full_scan: + return err; + } + ++ if ((buf[0] == 0xde) && ++ (buf[1] == 0xad) && ++ (buf[2] == 0xc0) && ++ (buf[3] == 0xde)) { ++ /* end of filesystem. erase everything after this point */ ++ printk("%s(): End of filesystem marker found at 0x%x\n", __func__, jeb->offset); ++ c->flags |= (1 << 7); ++ ++ return BLK_STATE_ALLFF; ++ } ++ + /* We temporarily use 'ofs' as a pointer into the buffer/jeb */ + ofs = 0; + max_ofs = EMPTY_SCAN_SIZE(c->sector_size); diff --git a/target/linux/generic/patches-4.1/540-crypto-xz-decompression-support.patch b/target/linux/generic/patches-4.1/540-crypto-xz-decompression-support.patch new file mode 100644 index 0000000..c250e9f --- /dev/null +++ b/target/linux/generic/patches-4.1/540-crypto-xz-decompression-support.patch @@ -0,0 +1,146 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -1435,6 +1435,13 @@ config CRYPTO_LZ4HC + help + This is the LZ4 high compression mode algorithm. + ++config CRYPTO_XZ ++ tristate "XZ compression algorithm" ++ select CRYPTO_ALGAPI ++ select XZ_DEC ++ help ++ This is the XZ algorithm. Only decompression is supported for now. ++ + comment "Random Number Generation" + + config CRYPTO_ANSI_CPRNG +--- a/crypto/Makefile ++++ b/crypto/Makefile +@@ -89,6 +89,7 @@ obj-$(CONFIG_CRYPTO_AUTHENC) += authenc. + obj-$(CONFIG_CRYPTO_LZO) += lzo.o + obj-$(CONFIG_CRYPTO_LZ4) += lz4.o + obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o ++obj-$(CONFIG_CRYPTO_XZ) += xz.o + obj-$(CONFIG_CRYPTO_842) += 842.o + obj-$(CONFIG_CRYPTO_RNG2) += rng.o + obj-$(CONFIG_CRYPTO_RNG2) += krng.o +--- /dev/null ++++ b/crypto/xz.c +@@ -0,0 +1,117 @@ ++/* ++ * Cryptographic API. ++ * ++ * XZ decompression support. ++ * ++ * Copyright (c) 2012 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct xz_comp_ctx { ++ struct xz_dec *decomp_state; ++ struct xz_buf decomp_buf; ++}; ++ ++static int crypto_xz_decomp_init(struct xz_comp_ctx *ctx) ++{ ++ ctx->decomp_state = xz_dec_init(XZ_SINGLE, 0); ++ if (!ctx->decomp_state) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static void crypto_xz_decomp_exit(struct xz_comp_ctx *ctx) ++{ ++ xz_dec_end(ctx->decomp_state); ++} ++ ++static int crypto_xz_init(struct crypto_tfm *tfm) ++{ ++ struct xz_comp_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ return crypto_xz_decomp_init(ctx); ++} ++ ++static void crypto_xz_exit(struct crypto_tfm *tfm) ++{ ++ struct xz_comp_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ crypto_xz_decomp_exit(ctx); ++} ++ ++static int crypto_xz_compress(struct crypto_tfm *tfm, const u8 *src, ++ unsigned int slen, u8 *dst, unsigned int *dlen) ++{ ++ return -EOPNOTSUPP; ++} ++ ++static int crypto_xz_decompress(struct crypto_tfm *tfm, const u8 *src, ++ unsigned int slen, u8 *dst, unsigned int *dlen) ++{ ++ struct xz_comp_ctx *dctx = crypto_tfm_ctx(tfm); ++ struct xz_buf *xz_buf = &dctx->decomp_buf; ++ int ret; ++ ++ memset(xz_buf, '\0', sizeof(struct xz_buf)); ++ ++ xz_buf->in = (u8 *) src; ++ xz_buf->in_pos = 0; ++ xz_buf->in_size = slen; ++ xz_buf->out = (u8 *) dst; ++ xz_buf->out_pos = 0; ++ xz_buf->out_size = *dlen; ++ ++ ret = xz_dec_run(dctx->decomp_state, xz_buf); ++ if (ret != XZ_STREAM_END) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ *dlen = xz_buf->out_pos; ++ ret = 0; ++ ++out: ++ return ret; ++} ++ ++static struct crypto_alg crypto_xz_alg = { ++ .cra_name = "xz", ++ .cra_flags = CRYPTO_ALG_TYPE_COMPRESS, ++ .cra_ctxsize = sizeof(struct xz_comp_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_list = LIST_HEAD_INIT(crypto_xz_alg.cra_list), ++ .cra_init = crypto_xz_init, ++ .cra_exit = crypto_xz_exit, ++ .cra_u = { .compress = { ++ .coa_compress = crypto_xz_compress, ++ .coa_decompress = crypto_xz_decompress } } ++}; ++ ++static int __init crypto_xz_mod_init(void) ++{ ++ return crypto_register_alg(&crypto_xz_alg); ++} ++ ++static void __exit crypto_xz_mod_exit(void) ++{ ++ crypto_unregister_alg(&crypto_xz_alg); ++} ++ ++module_init(crypto_xz_mod_init); ++module_exit(crypto_xz_mod_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Crypto XZ decompression support"); ++MODULE_AUTHOR("Gabor Juhos "); diff --git a/target/linux/generic/patches-4.1/541-ubifs-xz-decompression-support.patch b/target/linux/generic/patches-4.1/541-ubifs-xz-decompression-support.patch new file mode 100644 index 0000000..f85689c --- /dev/null +++ b/target/linux/generic/patches-4.1/541-ubifs-xz-decompression-support.patch @@ -0,0 +1,92 @@ +--- a/fs/ubifs/Kconfig ++++ b/fs/ubifs/Kconfig +@@ -5,8 +5,10 @@ config UBIFS_FS + select CRYPTO if UBIFS_FS_ADVANCED_COMPR + select CRYPTO if UBIFS_FS_LZO + select CRYPTO if UBIFS_FS_ZLIB ++ select CRYPTO if UBIFS_FS_XZ + select CRYPTO_LZO if UBIFS_FS_LZO + select CRYPTO_DEFLATE if UBIFS_FS_ZLIB ++ select CRYPTO_XZ if UBIFS_FS_XZ + depends on MTD_UBI + help + UBIFS is a file system for flash devices which works on top of UBI. +@@ -35,3 +37,12 @@ config UBIFS_FS_ZLIB + default y + help + Zlib compresses better than LZO but it is slower. Say 'Y' if unsure. ++ ++config UBIFS_FS_XZ ++ bool "XZ decompression support" if UBIFS_FS_ADVANCED_COMPR ++ depends on UBIFS_FS ++ default y ++ help ++ XZ compresses better the ZLIB but it is slower.. ++ Say 'Y' if unsure. ++ +--- a/fs/ubifs/compress.c ++++ b/fs/ubifs/compress.c +@@ -71,6 +71,24 @@ static struct ubifs_compressor zlib_comp + }; + #endif + ++#ifdef CONFIG_UBIFS_FS_XZ ++static DEFINE_MUTEX(xz_enc_mutex); ++static DEFINE_MUTEX(xz_dec_mutex); ++ ++static struct ubifs_compressor xz_compr = { ++ .compr_type = UBIFS_COMPR_XZ, ++ .comp_mutex = &xz_enc_mutex, ++ .decomp_mutex = &xz_dec_mutex, ++ .name = "xz", ++ .capi_name = "xz", ++}; ++#else ++static struct ubifs_compressor xz_compr = { ++ .compr_type = UBIFS_COMPR_XZ, ++ .name = "xz", ++}; ++#endif ++ + /* All UBIFS compressors */ + struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT]; + +@@ -232,9 +250,15 @@ int __init ubifs_compressors_init(void) + if (err) + goto out_lzo; + ++ err = compr_init(&xz_compr); ++ if (err) ++ goto out_zlib; ++ + ubifs_compressors[UBIFS_COMPR_NONE] = &none_compr; + return 0; + ++out_zlib: ++ compr_exit(&zlib_compr); + out_lzo: + compr_exit(&lzo_compr); + return err; +@@ -247,4 +271,5 @@ void ubifs_compressors_exit(void) + { + compr_exit(&lzo_compr); + compr_exit(&zlib_compr); ++ compr_exit(&xz_compr); + } +--- a/fs/ubifs/ubifs-media.h ++++ b/fs/ubifs/ubifs-media.h +@@ -332,12 +332,14 @@ enum { + * UBIFS_COMPR_NONE: no compression + * UBIFS_COMPR_LZO: LZO compression + * UBIFS_COMPR_ZLIB: ZLIB compression ++ * UBIFS_COMPR_XZ: XZ compression + * UBIFS_COMPR_TYPES_CNT: count of supported compression types + */ + enum { + UBIFS_COMPR_NONE, + UBIFS_COMPR_LZO, + UBIFS_COMPR_ZLIB, ++ UBIFS_COMPR_XZ, + UBIFS_COMPR_TYPES_CNT, + }; + diff --git a/target/linux/generic/patches-4.1/551-ubifs-fix-default-compression-selection.patch b/target/linux/generic/patches-4.1/551-ubifs-fix-default-compression-selection.patch new file mode 100644 index 0000000..1b0f307 --- /dev/null +++ b/target/linux/generic/patches-4.1/551-ubifs-fix-default-compression-selection.patch @@ -0,0 +1,29 @@ +--- a/fs/ubifs/sb.c ++++ b/fs/ubifs/sb.c +@@ -63,6 +63,17 @@ + /* Default time granularity in nanoseconds */ + #define DEFAULT_TIME_GRAN 1000000000 + ++static int get_default_compressor(void) ++{ ++ if (ubifs_compr_present(UBIFS_COMPR_LZO)) ++ return UBIFS_COMPR_LZO; ++ ++ if (ubifs_compr_present(UBIFS_COMPR_ZLIB)) ++ return UBIFS_COMPR_ZLIB; ++ ++ return UBIFS_COMPR_NONE; ++} ++ + /** + * create_default_filesystem - format empty UBI volume. + * @c: UBIFS file-system description object +@@ -183,7 +194,7 @@ static int create_default_filesystem(str + if (c->mount_opts.override_compr) + sup->default_compr = cpu_to_le16(c->mount_opts.compr_type); + else +- sup->default_compr = cpu_to_le16(UBIFS_COMPR_LZO); ++ sup->default_compr = cpu_to_le16(get_default_compressor()); + + generate_random_uuid(sup->uuid); + diff --git a/target/linux/generic/patches-4.1/600-netfilter_conntrack_flush.patch b/target/linux/generic/patches-4.1/600-netfilter_conntrack_flush.patch new file mode 100644 index 0000000..bd7a7ff --- /dev/null +++ b/target/linux/generic/patches-4.1/600-netfilter_conntrack_flush.patch @@ -0,0 +1,86 @@ +--- a/net/netfilter/nf_conntrack_standalone.c ++++ b/net/netfilter/nf_conntrack_standalone.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #ifdef CONFIG_SYSCTL + #include +@@ -259,10 +260,66 @@ static int ct_open(struct inode *inode, + sizeof(struct ct_iter_state)); + } + ++struct kill_request { ++ u16 family; ++ union nf_inet_addr addr; ++}; ++ ++static int kill_matching(struct nf_conn *i, void *data) ++{ ++ struct kill_request *kr = data; ++ struct nf_conntrack_tuple *t1 = &i->tuplehash[IP_CT_DIR_ORIGINAL].tuple; ++ struct nf_conntrack_tuple *t2 = &i->tuplehash[IP_CT_DIR_REPLY].tuple; ++ ++ if (!kr->family) ++ return 1; ++ ++ if (t1->src.l3num != kr->family) ++ return 0; ++ ++ return (nf_inet_addr_cmp(&kr->addr, &t1->src.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t1->dst.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t2->src.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t2->dst.u3)); ++} ++ ++static ssize_t ct_file_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *seq = file->private_data; ++ struct net *net = seq_file_net(seq); ++ struct kill_request kr = { }; ++ char req[INET6_ADDRSTRLEN] = { }; ++ ++ if (count == 0) ++ return 0; ++ ++ if (count >= INET6_ADDRSTRLEN) ++ count = INET6_ADDRSTRLEN - 1; ++ ++ if (copy_from_user(req, buf, count)) ++ return -EFAULT; ++ ++ if (strnchr(req, count, ':')) { ++ kr.family = AF_INET6; ++ if (!in6_pton(req, count, (void *)&kr.addr, '\n', NULL)) ++ return -EINVAL; ++ } else if (strnchr(req, count, '.')) { ++ kr.family = AF_INET; ++ if (!in4_pton(req, count, (void *)&kr.addr, '\n', NULL)) ++ return -EINVAL; ++ } ++ ++ nf_ct_iterate_cleanup(net, kill_matching, &kr, 0, 0); ++ ++ return count; ++} ++ + static const struct file_operations ct_file_ops = { + .owner = THIS_MODULE, + .open = ct_open, + .read = seq_read, ++ .write = ct_file_write, + .llseek = seq_lseek, + .release = seq_release_net, + }; +@@ -364,7 +421,7 @@ static int nf_conntrack_standalone_init_ + { + struct proc_dir_entry *pde; + +- pde = proc_create("nf_conntrack", 0440, net->proc_net, &ct_file_ops); ++ pde = proc_create("nf_conntrack", 0660, net->proc_net, &ct_file_ops); + if (!pde) + goto out_nf_conntrack; + diff --git a/target/linux/generic/patches-4.1/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/patches-4.1/610-netfilter_match_bypass_default_checks.patch new file mode 100644 index 0000000..282cbdd --- /dev/null +++ b/target/linux/generic/patches-4.1/610-netfilter_match_bypass_default_checks.patch @@ -0,0 +1,93 @@ +--- a/include/uapi/linux/netfilter_ipv4/ip_tables.h ++++ b/include/uapi/linux/netfilter_ipv4/ip_tables.h +@@ -87,6 +87,7 @@ struct ipt_ip { + #define IPT_F_FRAG 0x01 /* Set if rule is a fragment rule */ + #define IPT_F_GOTO 0x02 /* Set if jump is a goto */ + #define IPT_F_MASK 0x03 /* All possible flag bits mask. */ ++#define IPT_F_NO_DEF_MATCH 0x80 /* Internal: no default match rules present */ + + /* Values for "inv" field in struct ipt_ip. */ + #define IPT_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -82,6 +82,9 @@ ip_packet_match(const struct iphdr *ip, + + #define FWINV(bool, invflg) ((bool) ^ !!(ipinfo->invflags & (invflg))) + ++ if (ipinfo->flags & IPT_F_NO_DEF_MATCH) ++ return true; ++ + if (FWINV((ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, + IPT_INV_SRCIP) || + FWINV((ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, +@@ -135,6 +138,29 @@ ip_packet_match(const struct iphdr *ip, + return true; + } + ++static void ++ip_checkdefault(struct ipt_ip *ip) ++{ ++ static const char iface_mask[IFNAMSIZ] = {}; ++ ++ if (ip->invflags || ip->flags & IPT_F_FRAG) ++ return; ++ ++ if (memcmp(ip->iniface_mask, iface_mask, IFNAMSIZ) != 0) ++ return; ++ ++ if (memcmp(ip->outiface_mask, iface_mask, IFNAMSIZ) != 0) ++ return; ++ ++ if (ip->smsk.s_addr || ip->dmsk.s_addr) ++ return; ++ ++ if (ip->proto) ++ return; ++ ++ ip->flags |= IPT_F_NO_DEF_MATCH; ++} ++ + static bool + ip_checkentry(const struct ipt_ip *ip) + { +@@ -564,7 +590,7 @@ static void cleanup_match(struct xt_entr + } + + static int +-check_entry(const struct ipt_entry *e, const char *name) ++check_entry(struct ipt_entry *e, const char *name) + { + const struct xt_entry_target *t; + +@@ -573,6 +599,8 @@ check_entry(const struct ipt_entry *e, c + return -EINVAL; + } + ++ ip_checkdefault(&e->ip); ++ + if (e->target_offset + sizeof(struct xt_entry_target) > + e->next_offset) + return -EINVAL; +@@ -934,6 +962,7 @@ copy_entries_to_user(unsigned int total_ + const struct xt_table_info *private = table->private; + int ret = 0; + const void *loc_cpu_entry; ++ u8 flags; + + counters = alloc_counters(table); + if (IS_ERR(counters)) +@@ -964,6 +993,14 @@ copy_entries_to_user(unsigned int total_ + ret = -EFAULT; + goto free_counters; + } ++ ++ flags = e->ip.flags & IPT_F_MASK; ++ if (copy_to_user(userptr + off ++ + offsetof(struct ipt_entry, ip.flags), ++ &flags, sizeof(flags)) != 0) { ++ ret = -EFAULT; ++ goto free_counters; ++ } + + for (i = sizeof(struct ipt_entry); + i < e->target_offset; diff --git a/target/linux/generic/patches-4.1/611-netfilter_match_bypass_default_table.patch b/target/linux/generic/patches-4.1/611-netfilter_match_bypass_default_table.patch new file mode 100644 index 0000000..9e2290d --- /dev/null +++ b/target/linux/generic/patches-4.1/611-netfilter_match_bypass_default_table.patch @@ -0,0 +1,94 @@ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -310,6 +310,33 @@ struct ipt_entry *ipt_next_entry(const s + return (void *)entry + entry->next_offset; + } + ++static bool ++ipt_handle_default_rule(struct ipt_entry *e, unsigned int *verdict) ++{ ++ struct xt_entry_target *t; ++ struct xt_standard_target *st; ++ ++ if (e->target_offset != sizeof(struct ipt_entry)) ++ return false; ++ ++ if (!(e->ip.flags & IPT_F_NO_DEF_MATCH)) ++ return false; ++ ++ t = ipt_get_target(e); ++ if (t->u.kernel.target->target) ++ return false; ++ ++ st = (struct xt_standard_target *) t; ++ if (st->verdict == XT_RETURN) ++ return false; ++ ++ if (st->verdict >= 0) ++ return false; ++ ++ *verdict = (unsigned)(-st->verdict) - 1; ++ return true; ++} ++ + /* Returns one of the generic firewall policies, like NF_ACCEPT. */ + unsigned int + ipt_do_table(struct sk_buff *skb, +@@ -330,9 +357,33 @@ ipt_do_table(struct sk_buff *skb, + unsigned int addend; + + /* Initialization */ ++ IP_NF_ASSERT(table->valid_hooks & (1 << hook)); ++ local_bh_disable(); ++ private = table->private; ++ cpu = smp_processor_id(); ++ /* ++ * Ensure we load private-> members after we've fetched the base ++ * pointer. ++ */ ++ smp_read_barrier_depends(); ++ table_base = private->entries[cpu]; ++ ++ e = get_entry(table_base, private->hook_entry[hook]); ++ if (ipt_handle_default_rule(e, &verdict)) { ++ ADD_COUNTER(e->counters, skb->len, 1); ++ local_bh_enable(); ++ return verdict; ++ } ++ + ip = ip_hdr(skb); + indev = state->in ? state->in->name : nulldevname; + outdev = state->out ? state->out->name : nulldevname; ++ ++ addend = xt_write_recseq_begin(); ++ jumpstack = (struct ipt_entry **)private->jumpstack[cpu]; ++ stackptr = per_cpu_ptr(private->stackptr, cpu); ++ origptr = *stackptr; ++ + /* We handle fragments by dealing with the first fragment as + * if it was a normal packet. All other fragments are treated + * normally, except that they will NEVER match rules that ask +@@ -347,23 +398,6 @@ ipt_do_table(struct sk_buff *skb, + acpar.family = NFPROTO_IPV4; + acpar.hooknum = hook; + +- IP_NF_ASSERT(table->valid_hooks & (1 << hook)); +- local_bh_disable(); +- addend = xt_write_recseq_begin(); +- private = table->private; +- cpu = smp_processor_id(); +- /* +- * Ensure we load private-> members after we've fetched the base +- * pointer. +- */ +- smp_read_barrier_depends(); +- table_base = private->entries[cpu]; +- jumpstack = (struct ipt_entry **)private->jumpstack[cpu]; +- stackptr = per_cpu_ptr(private->stackptr, cpu); +- origptr = *stackptr; +- +- e = get_entry(table_base, private->hook_entry[hook]); +- + pr_debug("Entering %s(hook %u); sp at %u (UF %p)\n", + table->name, hook, origptr, + get_entry(table_base, private->underflow[hook])); diff --git a/target/linux/generic/patches-4.1/612-netfilter_match_reduce_memory_access.patch b/target/linux/generic/patches-4.1/612-netfilter_match_reduce_memory_access.patch new file mode 100644 index 0000000..72172d8 --- /dev/null +++ b/target/linux/generic/patches-4.1/612-netfilter_match_reduce_memory_access.patch @@ -0,0 +1,16 @@ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -85,9 +85,11 @@ ip_packet_match(const struct iphdr *ip, + if (ipinfo->flags & IPT_F_NO_DEF_MATCH) + return true; + +- if (FWINV((ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, ++ if (FWINV(ipinfo->smsk.s_addr && ++ (ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, + IPT_INV_SRCIP) || +- FWINV((ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, ++ FWINV(ipinfo->dmsk.s_addr && ++ (ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, + IPT_INV_DSTIP)) { + dprintf("Source or dest mismatch.\n"); + diff --git a/target/linux/generic/patches-4.1/613-netfilter_optional_tcp_window_check.patch b/target/linux/generic/patches-4.1/613-netfilter_optional_tcp_window_check.patch new file mode 100644 index 0000000..3740dd7 --- /dev/null +++ b/target/linux/generic/patches-4.1/613-netfilter_optional_tcp_window_check.patch @@ -0,0 +1,36 @@ +--- a/net/netfilter/nf_conntrack_proto_tcp.c ++++ b/net/netfilter/nf_conntrack_proto_tcp.c +@@ -33,6 +33,9 @@ + #include + #include + ++/* Do not check the TCP window for incoming packets */ ++static int nf_ct_tcp_no_window_check __read_mostly = 1; ++ + /* "Be conservative in what you do, + be liberal in what you accept from others." + If it's non-zero, we mark only out of window RST segments as INVALID. */ +@@ -515,6 +518,9 @@ static bool tcp_in_window(const struct n + s32 receiver_offset; + bool res, in_recv_win; + ++ if (nf_ct_tcp_no_window_check) ++ return true; ++ + /* + * Get the required data from the packet. + */ +@@ -1481,6 +1487,13 @@ static struct ctl_table tcp_sysctl_table + .mode = 0644, + .proc_handler = proc_dointvec, + }, ++ { ++ .procname = "nf_conntrack_tcp_no_window_check", ++ .data = &nf_ct_tcp_no_window_check, ++ .maxlen = sizeof(unsigned int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec, ++ }, + { } + }; + diff --git a/target/linux/generic/patches-4.1/615-netfilter_add_xt_id_match.patch b/target/linux/generic/patches-4.1/615-netfilter_add_xt_id_match.patch new file mode 100644 index 0000000..ba21d78 --- /dev/null +++ b/target/linux/generic/patches-4.1/615-netfilter_add_xt_id_match.patch @@ -0,0 +1,95 @@ +--- a/include/uapi/linux/netfilter/Kbuild ++++ b/include/uapi/linux/netfilter/Kbuild +@@ -55,6 +55,7 @@ header-y += xt_ecn.h + header-y += xt_esp.h + header-y += xt_hashlimit.h + header-y += xt_helper.h ++header-y += xt_id.h + header-y += xt_ipcomp.h + header-y += xt_iprange.h + header-y += xt_ipvs.h +--- /dev/null ++++ b/include/uapi/linux/netfilter/xt_id.h +@@ -0,0 +1,8 @@ ++#ifndef _XT_ID_H ++#define _XT_ID_H ++ ++struct xt_id_info { ++ u32 id; ++}; ++ ++#endif /* XT_ID_H */ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -1164,6 +1164,13 @@ config NETFILTER_XT_MATCH_IPCOMP + + To compile it as a module, choose M here. If unsure, say N. + ++config NETFILTER_XT_MATCH_ID ++ tristate '"id" match support' ++ depends on NETFILTER_ADVANCED ++ ---help--- ++ This option adds a `id' dummy-match, which allows you to put ++ numeric IDs into your iptables ruleset. ++ + config NETFILTER_XT_MATCH_IPRANGE + tristate '"iprange" address range match support' + depends on NETFILTER_ADVANCED +--- a/net/netfilter/Makefile ++++ b/net/netfilter/Makefile +@@ -145,6 +145,7 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_ESP) += + obj-$(CONFIG_NETFILTER_XT_MATCH_HASHLIMIT) += xt_hashlimit.o + obj-$(CONFIG_NETFILTER_XT_MATCH_HELPER) += xt_helper.o + obj-$(CONFIG_NETFILTER_XT_MATCH_HL) += xt_hl.o ++obj-$(CONFIG_NETFILTER_XT_MATCH_ID) += xt_id.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPCOMP) += xt_ipcomp.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPRANGE) += xt_iprange.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPVS) += xt_ipvs.o +--- /dev/null ++++ b/net/netfilter/xt_id.c +@@ -0,0 +1,45 @@ ++/* ++ * Implements a dummy match to allow attaching IDs to rules ++ * ++ * 2014-08-01 Jo-Philipp Wich ++ */ ++ ++#include ++#include ++#include ++#include ++ ++MODULE_AUTHOR("Jo-Philipp Wich "); ++MODULE_DESCRIPTION("Xtables: No-op match which can be tagged with a 32bit ID"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("ipt_id"); ++MODULE_ALIAS("ip6t_id"); ++ ++static bool ++id_mt(const struct sk_buff *skb, struct xt_action_param *par) ++{ ++ /* We always match */ ++ return true; ++} ++ ++static struct xt_match id_mt_reg __read_mostly = { ++ .name = "id", ++ .revision = 0, ++ .family = NFPROTO_UNSPEC, ++ .match = id_mt, ++ .matchsize = sizeof(struct xt_id_info), ++ .me = THIS_MODULE, ++}; ++ ++static int __init id_mt_init(void) ++{ ++ return xt_register_match(&id_mt_reg); ++} ++ ++static void __exit id_mt_exit(void) ++{ ++ xt_unregister_match(&id_mt_reg); ++} ++ ++module_init(id_mt_init); ++module_exit(id_mt_exit); diff --git a/target/linux/generic/patches-4.1/616-net_optimize_xfrm_calls.patch b/target/linux/generic/patches-4.1/616-net_optimize_xfrm_calls.patch new file mode 100644 index 0000000..2a64d54 --- /dev/null +++ b/target/linux/generic/patches-4.1/616-net_optimize_xfrm_calls.patch @@ -0,0 +1,12 @@ +--- a/net/netfilter/nf_nat_core.c ++++ b/net/netfilter/nf_nat_core.c +@@ -90,6 +90,9 @@ int nf_xfrm_me_harder(struct sk_buff *sk + struct dst_entry *dst; + int err; + ++ if (skb->dev && !dev_net(skb->dev)->xfrm.policy_count[XFRM_POLICY_OUT]) ++ return 0; ++ + err = xfrm_decode_session(skb, &fl, family); + if (err < 0) + return err; diff --git a/target/linux/generic/patches-4.1/620-sched_esfq.patch b/target/linux/generic/patches-4.1/620-sched_esfq.patch new file mode 100644 index 0000000..e1b473b --- /dev/null +++ b/target/linux/generic/patches-4.1/620-sched_esfq.patch @@ -0,0 +1,791 @@ +--- a/include/uapi/linux/pkt_sched.h ++++ b/include/uapi/linux/pkt_sched.h +@@ -226,6 +226,33 @@ struct tc_sfq_xstats { + __s32 allot; + }; + ++/* ESFQ section */ ++ ++enum ++{ ++ /* traditional */ ++ TCA_SFQ_HASH_CLASSIC, ++ TCA_SFQ_HASH_DST, ++ TCA_SFQ_HASH_SRC, ++ TCA_SFQ_HASH_FWMARK, ++ /* conntrack */ ++ TCA_SFQ_HASH_CTORIGDST, ++ TCA_SFQ_HASH_CTORIGSRC, ++ TCA_SFQ_HASH_CTREPLDST, ++ TCA_SFQ_HASH_CTREPLSRC, ++ TCA_SFQ_HASH_CTNATCHG, ++}; ++ ++struct tc_esfq_qopt ++{ ++ unsigned quantum; /* Bytes per round allocated to flow */ ++ int perturb_period; /* Period of hash perturbation */ ++ __u32 limit; /* Maximal packets in queue */ ++ unsigned divisor; /* Hash divisor */ ++ unsigned flows; /* Maximal number of flows */ ++ unsigned hash_kind; /* Hash function to use for flow identification */ ++}; ++ + /* RED section */ + + enum { +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -149,6 +149,37 @@ config NET_SCH_SFQ + To compile this code as a module, choose M here: the + module will be called sch_sfq. + ++config NET_SCH_ESFQ ++ tristate "Enhanced Stochastic Fairness Queueing (ESFQ)" ++ ---help--- ++ Say Y here if you want to use the Enhanced Stochastic Fairness ++ Queueing (ESFQ) packet scheduling algorithm for some of your network ++ devices or as a leaf discipline for a classful qdisc such as HTB or ++ CBQ (see the top of for details and ++ references to the SFQ algorithm). ++ ++ This is an enchanced SFQ version which allows you to control some ++ hardcoded values in the SFQ scheduler. ++ ++ ESFQ also adds control of the hash function used to identify packet ++ flows. The original SFQ discipline hashes by connection; ESFQ add ++ several other hashing methods, such as by src IP or by dst IP, which ++ can be more fair to users in some networking situations. ++ ++ To compile this code as a module, choose M here: the ++ module will be called sch_esfq. ++ ++config NET_SCH_ESFQ_NFCT ++ bool "Connection Tracking Hash Types" ++ depends on NET_SCH_ESFQ && NF_CONNTRACK ++ ---help--- ++ Say Y here to enable support for hashing based on netfilter connection ++ tracking information. This is useful for a router that is also using ++ NAT to connect privately-addressed hosts to the Internet. If you want ++ to provide fair distribution of upstream bandwidth, ESFQ must use ++ connection tracking information, since all outgoing packets will share ++ the same source address. ++ + config NET_SCH_TEQL + tristate "True Link Equalizer (TEQL)" + ---help--- +--- a/net/sched/Makefile ++++ b/net/sched/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_NET_SCH_INGRESS) += sch_ing + obj-$(CONFIG_NET_SCH_DSMARK) += sch_dsmark.o + obj-$(CONFIG_NET_SCH_SFB) += sch_sfb.o + obj-$(CONFIG_NET_SCH_SFQ) += sch_sfq.o ++obj-$(CONFIG_NET_SCH_ESFQ) += sch_esfq.o + obj-$(CONFIG_NET_SCH_TBF) += sch_tbf.o + obj-$(CONFIG_NET_SCH_TEQL) += sch_teql.o + obj-$(CONFIG_NET_SCH_PRIO) += sch_prio.o +--- /dev/null ++++ b/net/sched/sch_esfq.c +@@ -0,0 +1,702 @@ ++/* ++ * net/sched/sch_esfq.c Extended Stochastic Fairness Queueing discipline. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Authors: Alexey Kuznetsov, ++ * ++ * Changes: Alexander Atanasov, ++ * Added dynamic depth,limit,divisor,hash_kind options. ++ * Added dst and src hashes. ++ * ++ * Alexander Clouter, ++ * Ported ESFQ to Linux 2.6. ++ * ++ * Corey Hickey, ++ * Maintenance of the Linux 2.6 port. ++ * Added fwmark hash (thanks to Robert Kurjata). ++ * Added usage of jhash. ++ * Added conntrack support. ++ * Added ctnatchg hash (thanks to Ben Pfountz). ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++#include ++#endif ++ ++/* Stochastic Fairness Queuing algorithm. ++ For more comments look at sch_sfq.c. ++ The difference is that you can change limit, depth, ++ hash table size and choose alternate hash types. ++ ++ classic: same as in sch_sfq.c ++ dst: destination IP address ++ src: source IP address ++ fwmark: netfilter mark value ++ ctorigdst: original destination IP address ++ ctorigsrc: original source IP address ++ ctrepldst: reply destination IP address ++ ctreplsrc: reply source IP ++ ++*/ ++ ++#define ESFQ_HEAD 0 ++#define ESFQ_TAIL 1 ++ ++/* This type should contain at least SFQ_DEPTH*2 values */ ++typedef unsigned int esfq_index; ++ ++struct esfq_head ++{ ++ esfq_index next; ++ esfq_index prev; ++}; ++ ++struct esfq_sched_data ++{ ++/* Parameters */ ++ int perturb_period; ++ unsigned quantum; /* Allotment per round: MUST BE >= MTU */ ++ int limit; ++ unsigned depth; ++ unsigned hash_divisor; ++ unsigned hash_kind; ++/* Variables */ ++ struct timer_list perturb_timer; ++ int perturbation; ++ esfq_index tail; /* Index of current slot in round */ ++ esfq_index max_depth; /* Maximal depth */ ++ ++ esfq_index *ht; /* Hash table */ ++ esfq_index *next; /* Active slots link */ ++ short *allot; /* Current allotment per slot */ ++ unsigned short *hash; /* Hash value indexed by slots */ ++ struct sk_buff_head *qs; /* Slot queue */ ++ struct esfq_head *dep; /* Linked list of slots, indexed by depth */ ++}; ++ ++/* This contains the info we will hash. */ ++struct esfq_packet_info ++{ ++ u32 proto; /* protocol or port */ ++ u32 src; /* source from packet header */ ++ u32 dst; /* destination from packet header */ ++ u32 ctorigsrc; /* original source from conntrack */ ++ u32 ctorigdst; /* original destination from conntrack */ ++ u32 ctreplsrc; /* reply source from conntrack */ ++ u32 ctrepldst; /* reply destination from conntrack */ ++ u32 mark; /* netfilter mark (fwmark) */ ++}; ++ ++static __inline__ unsigned esfq_jhash_1word(struct esfq_sched_data *q,u32 a) ++{ ++ return jhash_1word(a, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static __inline__ unsigned esfq_jhash_2words(struct esfq_sched_data *q, u32 a, u32 b) ++{ ++ return jhash_2words(a, b, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static __inline__ unsigned esfq_jhash_3words(struct esfq_sched_data *q, u32 a, u32 b, u32 c) ++{ ++ return jhash_3words(a, b, c, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static unsigned esfq_hash(struct esfq_sched_data *q, struct sk_buff *skb) ++{ ++ struct esfq_packet_info info; ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ enum ip_conntrack_info ctinfo; ++ struct nf_conn *ct = nf_ct_get(skb, &ctinfo); ++#endif ++ ++ switch (skb->protocol) { ++ case __constant_htons(ETH_P_IP): ++ { ++ struct iphdr *iph = ip_hdr(skb); ++ info.dst = iph->daddr; ++ info.src = iph->saddr; ++ if (!(iph->frag_off&htons(IP_MF|IP_OFFSET)) && ++ (iph->protocol == IPPROTO_TCP || ++ iph->protocol == IPPROTO_UDP || ++ iph->protocol == IPPROTO_SCTP || ++ iph->protocol == IPPROTO_DCCP || ++ iph->protocol == IPPROTO_ESP)) ++ info.proto = *(((u32*)iph) + iph->ihl); ++ else ++ info.proto = iph->protocol; ++ break; ++ } ++ case __constant_htons(ETH_P_IPV6): ++ { ++ struct ipv6hdr *iph = ipv6_hdr(skb); ++ /* Hash ipv6 addresses into a u32. This isn't ideal, ++ * but the code is simple. */ ++ info.dst = jhash2(iph->daddr.s6_addr32, 4, q->perturbation); ++ info.src = jhash2(iph->saddr.s6_addr32, 4, q->perturbation); ++ if (iph->nexthdr == IPPROTO_TCP || ++ iph->nexthdr == IPPROTO_UDP || ++ iph->nexthdr == IPPROTO_SCTP || ++ iph->nexthdr == IPPROTO_DCCP || ++ iph->nexthdr == IPPROTO_ESP) ++ info.proto = *(u32*)&iph[1]; ++ else ++ info.proto = iph->nexthdr; ++ break; ++ } ++ default: ++ info.dst = (u32)(unsigned long)skb_dst(skb); ++ info.src = (u32)(unsigned long)skb->sk; ++ info.proto = skb->protocol; ++ } ++ ++ info.mark = skb->mark; ++ ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ /* defaults if there is no conntrack info */ ++ info.ctorigsrc = info.src; ++ info.ctorigdst = info.dst; ++ info.ctreplsrc = info.dst; ++ info.ctrepldst = info.src; ++ /* collect conntrack info */ ++ if (ct && ct != &nf_conntrack_untracked) { ++ if (skb->protocol == __constant_htons(ETH_P_IP)) { ++ info.ctorigsrc = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip; ++ info.ctorigdst = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.u3.ip; ++ info.ctreplsrc = ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip; ++ info.ctrepldst = ct->tuplehash[IP_CT_DIR_REPLY].tuple.dst.u3.ip; ++ } ++ else if (skb->protocol == __constant_htons(ETH_P_IPV6)) { ++ /* Again, hash ipv6 addresses into a single u32. */ ++ info.ctorigsrc = jhash2(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip6, 4, q->perturbation); ++ info.ctorigdst = jhash2(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.u3.ip6, 4, q->perturbation); ++ info.ctreplsrc = jhash2(ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip6, 4, q->perturbation); ++ info.ctrepldst = jhash2(ct->tuplehash[IP_CT_DIR_REPLY].tuple.dst.u3.ip6, 4, q->perturbation); ++ } ++ ++ } ++#endif ++ ++ switch(q->hash_kind) { ++ case TCA_SFQ_HASH_CLASSIC: ++ return esfq_jhash_3words(q, info.dst, info.src, info.proto); ++ case TCA_SFQ_HASH_DST: ++ return esfq_jhash_1word(q, info.dst); ++ case TCA_SFQ_HASH_SRC: ++ return esfq_jhash_1word(q, info.src); ++ case TCA_SFQ_HASH_FWMARK: ++ return esfq_jhash_1word(q, info.mark); ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ case TCA_SFQ_HASH_CTORIGDST: ++ return esfq_jhash_1word(q, info.ctorigdst); ++ case TCA_SFQ_HASH_CTORIGSRC: ++ return esfq_jhash_1word(q, info.ctorigsrc); ++ case TCA_SFQ_HASH_CTREPLDST: ++ return esfq_jhash_1word(q, info.ctrepldst); ++ case TCA_SFQ_HASH_CTREPLSRC: ++ return esfq_jhash_1word(q, info.ctreplsrc); ++ case TCA_SFQ_HASH_CTNATCHG: ++ { ++ if (info.ctorigdst == info.ctreplsrc) ++ return esfq_jhash_1word(q, info.ctorigsrc); ++ return esfq_jhash_1word(q, info.ctreplsrc); ++ } ++#endif ++ default: ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Unknown hash method. Falling back to classic.\n"); ++ } ++ return esfq_jhash_3words(q, info.dst, info.src, info.proto); ++} ++ ++static inline void esfq_link(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ int d = q->qs[x].qlen + q->depth; ++ ++ p = d; ++ n = q->dep[d].next; ++ q->dep[x].next = n; ++ q->dep[x].prev = p; ++ q->dep[p].next = q->dep[n].prev = x; ++} ++ ++static inline void esfq_dec(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ ++ n = q->dep[x].next; ++ p = q->dep[x].prev; ++ q->dep[p].next = n; ++ q->dep[n].prev = p; ++ ++ if (n == p && q->max_depth == q->qs[x].qlen + 1) ++ q->max_depth--; ++ ++ esfq_link(q, x); ++} ++ ++static inline void esfq_inc(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ int d; ++ ++ n = q->dep[x].next; ++ p = q->dep[x].prev; ++ q->dep[p].next = n; ++ q->dep[n].prev = p; ++ d = q->qs[x].qlen; ++ if (q->max_depth < d) ++ q->max_depth = d; ++ ++ esfq_link(q, x); ++} ++ ++static unsigned int esfq_drop(struct Qdisc *sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_index d = q->max_depth; ++ struct sk_buff *skb; ++ unsigned int len; ++ ++ /* Queue is full! Find the longest slot and ++ drop a packet from it */ ++ ++ if (d > 1) { ++ esfq_index x = q->dep[d+q->depth].next; ++ skb = q->qs[x].prev; ++ len = skb->len; ++ __skb_unlink(skb, &q->qs[x]); ++ kfree_skb(skb); ++ esfq_dec(q, x); ++ sch->q.qlen--; ++ sch->qstats.drops++; ++ sch->qstats.backlog -= len; ++ return len; ++ } ++ ++ if (d == 1) { ++ /* It is difficult to believe, but ALL THE SLOTS HAVE LENGTH 1. */ ++ d = q->next[q->tail]; ++ q->next[q->tail] = q->next[d]; ++ q->allot[q->next[d]] += q->quantum; ++ skb = q->qs[d].prev; ++ len = skb->len; ++ __skb_unlink(skb, &q->qs[d]); ++ kfree_skb(skb); ++ esfq_dec(q, d); ++ sch->q.qlen--; ++ q->ht[q->hash[d]] = q->depth; ++ sch->qstats.drops++; ++ sch->qstats.backlog -= len; ++ return len; ++ } ++ ++ return 0; ++} ++ ++static void esfq_q_enqueue(struct sk_buff *skb, struct esfq_sched_data *q, unsigned int end) ++{ ++ unsigned hash = esfq_hash(q, skb); ++ unsigned depth = q->depth; ++ esfq_index x; ++ ++ x = q->ht[hash]; ++ if (x == depth) { ++ q->ht[hash] = x = q->dep[depth].next; ++ q->hash[x] = hash; ++ } ++ ++ if (end == ESFQ_TAIL) ++ __skb_queue_tail(&q->qs[x], skb); ++ else ++ __skb_queue_head(&q->qs[x], skb); ++ ++ esfq_inc(q, x); ++ if (q->qs[x].qlen == 1) { /* The flow is new */ ++ if (q->tail == depth) { /* It is the first flow */ ++ q->tail = x; ++ q->next[x] = x; ++ q->allot[x] = q->quantum; ++ } else { ++ q->next[x] = q->next[q->tail]; ++ q->next[q->tail] = x; ++ q->tail = x; ++ } ++ } ++} ++ ++static int esfq_enqueue(struct sk_buff *skb, struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_q_enqueue(skb, q, ESFQ_TAIL); ++ sch->qstats.backlog += skb->len; ++ if (++sch->q.qlen < q->limit-1) { ++ sch->bstats.bytes += skb->len; ++ sch->bstats.packets++; ++ return 0; ++ } ++ ++ sch->qstats.drops++; ++ esfq_drop(sch); ++ return NET_XMIT_CN; ++} ++ ++static struct sk_buff *esfq_peek(struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_index a; ++ ++ /* No active slots */ ++ if (q->tail == q->depth) ++ return NULL; ++ ++ a = q->next[q->tail]; ++ return skb_peek(&q->qs[a]); ++} ++ ++static struct sk_buff *esfq_q_dequeue(struct esfq_sched_data *q) ++{ ++ struct sk_buff *skb; ++ unsigned depth = q->depth; ++ esfq_index a, old_a; ++ ++ /* No active slots */ ++ if (q->tail == depth) ++ return NULL; ++ ++ a = old_a = q->next[q->tail]; ++ ++ /* Grab packet */ ++ skb = __skb_dequeue(&q->qs[a]); ++ esfq_dec(q, a); ++ ++ /* Is the slot empty? */ ++ if (q->qs[a].qlen == 0) { ++ q->ht[q->hash[a]] = depth; ++ a = q->next[a]; ++ if (a == old_a) { ++ q->tail = depth; ++ return skb; ++ } ++ q->next[q->tail] = a; ++ q->allot[a] += q->quantum; ++ } else if ((q->allot[a] -= skb->len) <= 0) { ++ q->tail = a; ++ a = q->next[a]; ++ q->allot[a] += q->quantum; ++ } ++ ++ return skb; ++} ++ ++static struct sk_buff *esfq_dequeue(struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ struct sk_buff *skb; ++ ++ skb = esfq_q_dequeue(q); ++ if (skb == NULL) ++ return NULL; ++ sch->q.qlen--; ++ sch->qstats.backlog -= skb->len; ++ return skb; ++} ++ ++static void esfq_q_destroy(struct esfq_sched_data *q) ++{ ++ del_timer(&q->perturb_timer); ++ if(q->ht) ++ kfree(q->ht); ++ if(q->dep) ++ kfree(q->dep); ++ if(q->next) ++ kfree(q->next); ++ if(q->allot) ++ kfree(q->allot); ++ if(q->hash) ++ kfree(q->hash); ++ if(q->qs) ++ kfree(q->qs); ++} ++ ++static void esfq_destroy(struct Qdisc *sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_q_destroy(q); ++} ++ ++ ++static void esfq_reset(struct Qdisc* sch) ++{ ++ struct sk_buff *skb; ++ ++ while ((skb = esfq_dequeue(sch)) != NULL) ++ kfree_skb(skb); ++} ++ ++static void esfq_perturbation(unsigned long arg) ++{ ++ struct Qdisc *sch = (struct Qdisc*)arg; ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ ++ q->perturbation = prandom_u32()&0x1F; ++ ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } ++} ++ ++static unsigned int esfq_check_hash(unsigned int kind) ++{ ++ switch (kind) { ++ case TCA_SFQ_HASH_CTORIGDST: ++ case TCA_SFQ_HASH_CTORIGSRC: ++ case TCA_SFQ_HASH_CTREPLDST: ++ case TCA_SFQ_HASH_CTREPLSRC: ++ case TCA_SFQ_HASH_CTNATCHG: ++#ifndef CONFIG_NET_SCH_ESFQ_NFCT ++ { ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Conntrack hash types disabled in kernel config. Falling back to classic.\n"); ++ return TCA_SFQ_HASH_CLASSIC; ++ } ++#endif ++ case TCA_SFQ_HASH_CLASSIC: ++ case TCA_SFQ_HASH_DST: ++ case TCA_SFQ_HASH_SRC: ++ case TCA_SFQ_HASH_FWMARK: ++ return kind; ++ default: ++ { ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Unknown hash type. Falling back to classic.\n"); ++ return TCA_SFQ_HASH_CLASSIC; ++ } ++ } ++} ++ ++static int esfq_q_init(struct esfq_sched_data *q, struct nlattr *opt) ++{ ++ struct tc_esfq_qopt *ctl = nla_data(opt); ++ esfq_index p = ~0U/2; ++ int i; ++ ++ if (opt && opt->nla_len < nla_attr_size(sizeof(*ctl))) ++ return -EINVAL; ++ ++ q->perturbation = 0; ++ q->hash_kind = TCA_SFQ_HASH_CLASSIC; ++ q->max_depth = 0; ++ if (opt == NULL) { ++ q->perturb_period = 0; ++ q->hash_divisor = 1024; ++ q->tail = q->limit = q->depth = 128; ++ ++ } else { ++ struct tc_esfq_qopt *ctl = nla_data(opt); ++ if (ctl->quantum) ++ q->quantum = ctl->quantum; ++ q->perturb_period = ctl->perturb_period*HZ; ++ q->hash_divisor = ctl->divisor ? : 1024; ++ q->tail = q->limit = q->depth = ctl->flows ? : 128; ++ ++ if ( q->depth > p - 1 ) ++ return -EINVAL; ++ ++ if (ctl->limit) ++ q->limit = min_t(u32, ctl->limit, q->depth); ++ ++ if (ctl->hash_kind) { ++ q->hash_kind = esfq_check_hash(ctl->hash_kind); ++ } ++ } ++ ++ q->ht = kmalloc(q->hash_divisor*sizeof(esfq_index), GFP_KERNEL); ++ if (!q->ht) ++ goto err_case; ++ q->dep = kmalloc((1+q->depth*2)*sizeof(struct esfq_head), GFP_KERNEL); ++ if (!q->dep) ++ goto err_case; ++ q->next = kmalloc(q->depth*sizeof(esfq_index), GFP_KERNEL); ++ if (!q->next) ++ goto err_case; ++ q->allot = kmalloc(q->depth*sizeof(short), GFP_KERNEL); ++ if (!q->allot) ++ goto err_case; ++ q->hash = kmalloc(q->depth*sizeof(unsigned short), GFP_KERNEL); ++ if (!q->hash) ++ goto err_case; ++ q->qs = kmalloc(q->depth*sizeof(struct sk_buff_head), GFP_KERNEL); ++ if (!q->qs) ++ goto err_case; ++ ++ for (i=0; i< q->hash_divisor; i++) ++ q->ht[i] = q->depth; ++ for (i=0; idepth; i++) { ++ skb_queue_head_init(&q->qs[i]); ++ q->dep[i+q->depth].next = i+q->depth; ++ q->dep[i+q->depth].prev = i+q->depth; ++ } ++ ++ for (i=0; idepth; i++) ++ esfq_link(q, i); ++ return 0; ++err_case: ++ esfq_q_destroy(q); ++ return -ENOBUFS; ++} ++ ++static int esfq_init(struct Qdisc *sch, struct nlattr *opt) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ int err; ++ ++ q->quantum = psched_mtu(qdisc_dev(sch)); /* default */ ++ if ((err = esfq_q_init(q, opt))) ++ return err; ++ ++ init_timer(&q->perturb_timer); ++ q->perturb_timer.data = (unsigned long)sch; ++ q->perturb_timer.function = esfq_perturbation; ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } ++ ++ return 0; ++} ++ ++static int esfq_change(struct Qdisc *sch, struct nlattr *opt) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ struct esfq_sched_data new; ++ struct sk_buff *skb; ++ int err; ++ ++ /* set up new queue */ ++ memset(&new, 0, sizeof(struct esfq_sched_data)); ++ new.quantum = psched_mtu(qdisc_dev(sch)); /* default */ ++ if ((err = esfq_q_init(&new, opt))) ++ return err; ++ ++ /* copy all packets from the old queue to the new queue */ ++ sch_tree_lock(sch); ++ while ((skb = esfq_q_dequeue(q)) != NULL) ++ esfq_q_enqueue(skb, &new, ESFQ_TAIL); ++ ++ /* clean up the old queue */ ++ esfq_q_destroy(q); ++ ++ /* copy elements of the new queue into the old queue */ ++ q->perturb_period = new.perturb_period; ++ q->quantum = new.quantum; ++ q->limit = new.limit; ++ q->depth = new.depth; ++ q->hash_divisor = new.hash_divisor; ++ q->hash_kind = new.hash_kind; ++ q->tail = new.tail; ++ q->max_depth = new.max_depth; ++ q->ht = new.ht; ++ q->dep = new.dep; ++ q->next = new.next; ++ q->allot = new.allot; ++ q->hash = new.hash; ++ q->qs = new.qs; ++ ++ /* finish up */ ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } else { ++ q->perturbation = 0; ++ } ++ sch_tree_unlock(sch); ++ return 0; ++} ++ ++static int esfq_dump(struct Qdisc *sch, struct sk_buff *skb) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ unsigned char *b = skb_tail_pointer(skb); ++ struct tc_esfq_qopt opt; ++ ++ opt.quantum = q->quantum; ++ opt.perturb_period = q->perturb_period/HZ; ++ ++ opt.limit = q->limit; ++ opt.divisor = q->hash_divisor; ++ opt.flows = q->depth; ++ opt.hash_kind = q->hash_kind; ++ ++ if (nla_put(skb, TCA_OPTIONS, sizeof(opt), &opt)) ++ goto nla_put_failure; ++ ++ return skb->len; ++ ++nla_put_failure: ++ nlmsg_trim(skb, b); ++ return -1; ++} ++ ++static struct Qdisc_ops esfq_qdisc_ops = ++{ ++ .next = NULL, ++ .cl_ops = NULL, ++ .id = "esfq", ++ .priv_size = sizeof(struct esfq_sched_data), ++ .enqueue = esfq_enqueue, ++ .dequeue = esfq_dequeue, ++ .peek = esfq_peek, ++ .drop = esfq_drop, ++ .init = esfq_init, ++ .reset = esfq_reset, ++ .destroy = esfq_destroy, ++ .change = esfq_change, ++ .dump = esfq_dump, ++ .owner = THIS_MODULE, ++}; ++ ++static int __init esfq_module_init(void) ++{ ++ return register_qdisc(&esfq_qdisc_ops); ++} ++static void __exit esfq_module_exit(void) ++{ ++ unregister_qdisc(&esfq_qdisc_ops); ++} ++module_init(esfq_module_init) ++module_exit(esfq_module_exit) ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.1/630-packet_socket_type.patch b/target/linux/generic/patches-4.1/630-packet_socket_type.patch new file mode 100644 index 0000000..ca6ce29 --- /dev/null +++ b/target/linux/generic/patches-4.1/630-packet_socket_type.patch @@ -0,0 +1,134 @@ +This patch allows the user to specify desired packet types (outgoing, +broadcast, unicast, etc.) on packet sockets via setsockopt. +This can reduce the load in situations where only a limited number +of packet types are necessary + +Signed-off-by: Felix Fietkau + +--- a/include/uapi/linux/if_packet.h ++++ b/include/uapi/linux/if_packet.h +@@ -31,6 +31,8 @@ struct sockaddr_ll { + #define PACKET_KERNEL 7 /* To kernel space */ + /* Unused, PACKET_FASTROUTE and PACKET_LOOPBACK are invisible to user space */ + #define PACKET_FASTROUTE 6 /* Fastrouted frame */ ++#define PACKET_MASK_ANY 0xffffffff /* mask for packet type bits */ ++ + + /* Packet socket options */ + +@@ -54,6 +56,7 @@ struct sockaddr_ll { + #define PACKET_FANOUT 18 + #define PACKET_TX_HAS_OFF 19 + #define PACKET_QDISC_BYPASS 20 ++#define PACKET_RECV_TYPE 21 + + #define PACKET_FANOUT_HASH 0 + #define PACKET_FANOUT_LB 1 +--- a/net/packet/af_packet.c ++++ b/net/packet/af_packet.c +@@ -1533,6 +1533,7 @@ static int packet_rcv_spkt(struct sk_buf + { + struct sock *sk; + struct sockaddr_pkt *spkt; ++ struct packet_sock *po; + + /* + * When we registered the protocol we saved the socket in the data +@@ -1540,6 +1541,7 @@ static int packet_rcv_spkt(struct sk_buf + */ + + sk = pt->af_packet_priv; ++ po = pkt_sk(sk); + + /* + * Yank back the headers [hope the device set this +@@ -1552,7 +1554,7 @@ static int packet_rcv_spkt(struct sk_buf + * so that this procedure is noop. + */ + +- if (skb->pkt_type == PACKET_LOOPBACK) ++ if (!(po->pkt_type & (1 << skb->pkt_type))) + goto out; + + if (!net_eq(dev_net(dev), sock_net(sk))) +@@ -1759,12 +1761,12 @@ static int packet_rcv(struct sk_buff *sk + int skb_len = skb->len; + unsigned int snaplen, res; + +- if (skb->pkt_type == PACKET_LOOPBACK) +- goto drop; +- + sk = pt->af_packet_priv; + po = pkt_sk(sk); + ++ if (!(po->pkt_type & (1 << skb->pkt_type))) ++ goto drop; ++ + if (!net_eq(dev_net(dev), sock_net(sk))) + goto drop; + +@@ -1884,12 +1886,12 @@ static int tpacket_rcv(struct sk_buff *s + BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32); + BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48); + +- if (skb->pkt_type == PACKET_LOOPBACK) +- goto drop; +- + sk = pt->af_packet_priv; + po = pkt_sk(sk); + ++ if (!(po->pkt_type & (1 << skb->pkt_type))) ++ goto drop; ++ + if (!net_eq(dev_net(dev), sock_net(sk))) + goto drop; + +@@ -2851,6 +2853,7 @@ static int packet_create(struct net *net + spin_lock_init(&po->bind_lock); + mutex_init(&po->pg_vec_lock); + po->prot_hook.func = packet_rcv; ++ po->pkt_type = PACKET_MASK_ANY & ~(1 << PACKET_LOOPBACK); + + if (sock->type == SOCK_PACKET) + po->prot_hook.func = packet_rcv_spkt; +@@ -3456,6 +3459,16 @@ packet_setsockopt(struct socket *sock, i + po->xmit = val ? packet_direct_xmit : dev_queue_xmit; + return 0; + } ++ case PACKET_RECV_TYPE: ++ { ++ unsigned int val; ++ if (optlen != sizeof(val)) ++ return -EINVAL; ++ if (copy_from_user(&val, optval, sizeof(val))) ++ return -EFAULT; ++ po->pkt_type = val & ~BIT(PACKET_LOOPBACK); ++ return 0; ++ } + default: + return -ENOPROTOOPT; + } +@@ -3507,6 +3520,13 @@ static int packet_getsockopt(struct sock + case PACKET_VNET_HDR: + val = po->has_vnet_hdr; + break; ++ case PACKET_RECV_TYPE: ++ if (len > sizeof(unsigned int)) ++ len = sizeof(unsigned int); ++ val = po->pkt_type; ++ ++ data = &val; ++ break; + case PACKET_VERSION: + val = po->tp_version; + break; +--- a/net/packet/internal.h ++++ b/net/packet/internal.h +@@ -115,6 +115,7 @@ struct packet_sock { + struct net_device __rcu *cached_dev; + int (*xmit)(struct sk_buff *skb); + struct packet_type prot_hook ____cacheline_aligned_in_smp; ++ unsigned int pkt_type; + }; + + static struct packet_sock *pkt_sk(struct sock *sk) diff --git a/target/linux/generic/patches-4.1/640-bridge_no_eap_forward.patch b/target/linux/generic/patches-4.1/640-bridge_no_eap_forward.patch new file mode 100644 index 0000000..de52c02 --- /dev/null +++ b/target/linux/generic/patches-4.1/640-bridge_no_eap_forward.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: no EAP forward + +When bridging, do not forward EAP frames to other ports, only deliver +them locally. +Fixes WPA authentication issues with multiples APs that are connected to +each other via bridges. +--- +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -162,7 +162,11 @@ int br_handle_frame_finish(struct sock * + if (IS_ENABLED(CONFIG_INET) && skb->protocol == htons(ETH_P_ARP)) + br_do_proxy_arp(skb, br, vid, p); + +- if (is_broadcast_ether_addr(dest)) { ++ if (skb->protocol == htons(ETH_P_PAE)) { ++ skb2 = skb; ++ /* Do not forward 802.1x/EAP frames */ ++ skb = NULL; ++ } else if (is_broadcast_ether_addr(dest)) { + skb2 = skb; + unicast = false; + } else if (is_multicast_ether_addr(dest)) { diff --git a/target/linux/generic/patches-4.1/641-bridge_always_accept_eap.patch b/target/linux/generic/patches-4.1/641-bridge_always_accept_eap.patch new file mode 100644 index 0000000..61f96e5 --- /dev/null +++ b/target/linux/generic/patches-4.1/641-bridge_always_accept_eap.patch @@ -0,0 +1,17 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: always accept EAP + +Allow EAP frames to pass through bridges even in learning state. Fixes +issues with WDS. +--- +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -146,7 +146,7 @@ int br_handle_frame_finish(struct sock * + br_multicast_rcv(br, p, skb, vid)) + goto drop; + +- if (p->state == BR_STATE_LEARNING) ++ if ((p->state == BR_STATE_LEARNING) && skb->protocol != htons(ETH_P_PAE)) + goto drop; + + BR_INPUT_SKB_CB(skb)->brdev = br->dev; diff --git a/target/linux/generic/patches-4.1/642-bridge_port_isolate.patch b/target/linux/generic/patches-4.1/642-bridge_port_isolate.patch new file mode 100644 index 0000000..13f84ae --- /dev/null +++ b/target/linux/generic/patches-4.1/642-bridge_port_isolate.patch @@ -0,0 +1,107 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: port isolate + +Isolating individual bridge ports +--- +--- a/include/linux/if_bridge.h ++++ b/include/linux/if_bridge.h +@@ -45,6 +45,7 @@ struct br_ip_list { + #define BR_PROXYARP BIT(8) + #define BR_LEARNING_SYNC BIT(9) + #define BR_PROXYARP_WIFI BIT(10) ++#define BR_ISOLATE_MODE BIT(11) + + extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *)); + +--- a/net/bridge/br_sysfs_if.c ++++ b/net/bridge/br_sysfs_if.c +@@ -173,6 +173,22 @@ BRPORT_ATTR_FLAG(unicast_flood, BR_FLOOD + BRPORT_ATTR_FLAG(proxyarp, BR_PROXYARP); + BRPORT_ATTR_FLAG(proxyarp_wifi, BR_PROXYARP_WIFI); + ++static ssize_t show_isolate_mode(struct net_bridge_port *p, char *buf) ++{ ++ int isolate_mode = (p->flags & BR_ISOLATE_MODE) ? 1 : 0; ++ return sprintf(buf, "%d\n", isolate_mode); ++} ++static ssize_t store_isolate_mode(struct net_bridge_port *p, unsigned long v) ++{ ++ if (v) ++ p->flags |= BR_ISOLATE_MODE; ++ else ++ p->flags &= ~BR_ISOLATE_MODE; ++ return 0; ++} ++static BRPORT_ATTR(isolate_mode, S_IRUGO | S_IWUSR, ++ show_isolate_mode, store_isolate_mode); ++ + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf) + { +@@ -217,6 +233,7 @@ static const struct brport_attribute *br + #endif + &brport_attr_proxyarp, + &brport_attr_proxyarp_wifi, ++ &brport_attr_isolate_mode, + NULL + }; + +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -185,8 +185,8 @@ int br_handle_frame_finish(struct sock * + + unicast = false; + br->dev->stats.multicast++; +- } else if ((dst = __br_fdb_get(br, dest, vid)) && +- dst->is_local) { ++ } else if ((p->flags & BR_ISOLATE_MODE) || ++ ((dst = __br_fdb_get(br, dest, vid)) && dst->is_local)) { + skb2 = skb; + /* Do not forward the packet since it's local. */ + skb = NULL; +--- a/net/bridge/br_forward.c ++++ b/net/bridge/br_forward.c +@@ -119,7 +119,7 @@ EXPORT_SYMBOL_GPL(br_deliver); + /* called with rcu_read_lock */ + void br_forward(const struct net_bridge_port *to, struct sk_buff *skb, struct sk_buff *skb0) + { +- if (should_deliver(to, skb)) { ++ if (should_deliver(to, skb) && !(to->flags & BR_ISOLATE_MODE)) { + if (skb0) + deliver_clone(to, skb, __br_forward); + else +@@ -175,7 +175,7 @@ static void br_flood(struct net_bridge * + struct sk_buff *skb0, + void (*__packet_hook)(const struct net_bridge_port *p, + struct sk_buff *skb), +- bool unicast) ++ bool unicast, bool forward) + { + struct net_bridge_port *p; + struct net_bridge_port *prev; +@@ -183,6 +183,8 @@ static void br_flood(struct net_bridge * + prev = NULL; + + list_for_each_entry_rcu(p, &br->port_list, list) { ++ if (forward && (p->flags & BR_ISOLATE_MODE)) ++ continue; + /* Do not flood unicast traffic to ports that turn it off */ + if (unicast && !(p->flags & BR_FLOOD)) + continue; +@@ -217,14 +219,14 @@ out: + /* called with rcu_read_lock */ + void br_flood_deliver(struct net_bridge *br, struct sk_buff *skb, bool unicast) + { +- br_flood(br, skb, NULL, __br_deliver, unicast); ++ br_flood(br, skb, NULL, __br_deliver, unicast, false); + } + + /* called under bridge lock */ + void br_flood_forward(struct net_bridge *br, struct sk_buff *skb, + struct sk_buff *skb2, bool unicast) + { +- br_flood(br, skb, skb2, __br_forward, unicast); ++ br_flood(br, skb, skb2, __br_forward, unicast, true); + } + + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING diff --git a/target/linux/generic/patches-4.1/643-bridge_remove_ipv6_dependency.patch b/target/linux/generic/patches-4.1/643-bridge_remove_ipv6_dependency.patch new file mode 100644 index 0000000..b18f33e --- /dev/null +++ b/target/linux/generic/patches-4.1/643-bridge_remove_ipv6_dependency.patch @@ -0,0 +1,123 @@ +From: Jonas Gorski +Subject: [PATCH] bridge: remove IPv6 depependency of bridge in 2.6.38+ + +Since 2.6.38 the bridge module has a dependency to IPv6 if IPv6 is +enabled. Since the IPv6 module isn't exactly lightweight and bridge also +only needs a single function from IPv6, it's rather easy to create a +common "lib" module with a RCU pointer to the actual implementation, if +the IPv6 module is loaded (although slightly hackish). + +The codepath seems to be only taken when using IPv6, so there should be +no negative side effects when IPv6 isn't loaded. I did not measure how +big the performance impact is. +--- +--- a/include/net/addrconf.h ++++ b/include/net/addrconf.h +@@ -91,6 +91,12 @@ int ipv6_rcv_saddr_equal(const struct so + void addrconf_join_solict(struct net_device *dev, const struct in6_addr *addr); + void addrconf_leave_solict(struct inet6_dev *idev, const struct in6_addr *addr); + ++extern int (*ipv6_dev_get_saddr_hook)(struct net *net, ++ const struct net_device *dev, ++ const struct in6_addr *daddr, ++ unsigned int prefs, ++ struct in6_addr *saddr); ++ + static inline unsigned long addrconf_timeout_fixup(u32 timeout, + unsigned int unit) + { +--- a/net/bridge/Kconfig ++++ b/net/bridge/Kconfig +@@ -6,7 +6,6 @@ config BRIDGE + tristate "802.1d Ethernet Bridging" + select LLC + select STP +- depends on IPV6 || IPV6=n + ---help--- + If you say Y here, then your Linux box will be able to act as an + Ethernet bridge, which means that the different Ethernet segments it +--- a/net/ipv6/Makefile ++++ b/net/ipv6/Makefile +@@ -45,6 +45,7 @@ obj-y += addrconf_core.o exthdrs_core.o + obj-$(CONFIG_INET) += output_core.o protocol.o $(ipv6-offload) + + obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_hashtables.o ++obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_stubs.o + + ifneq ($(CONFIG_IPV6),) + obj-$(CONFIG_NET_UDP_TUNNEL) += ip6_udp_tunnel.o +--- a/net/ipv6/addrconf.c ++++ b/net/ipv6/addrconf.c +@@ -1358,7 +1358,7 @@ out: + return ret; + } + +-int ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, ++static int __ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, + const struct in6_addr *daddr, unsigned int prefs, + struct in6_addr *saddr) + { +@@ -1481,7 +1481,6 @@ try_nextdev: + in6_ifa_put(hiscore->ifa); + return 0; + } +-EXPORT_SYMBOL(ipv6_dev_get_saddr); + + int __ipv6_get_lladdr(struct inet6_dev *idev, struct in6_addr *addr, + u32 banned_flags) +@@ -5810,6 +5809,9 @@ int __init addrconf_init(void) + + ipv6_addr_label_rtnl_register(); + ++ BUG_ON(ipv6_dev_get_saddr_hook != NULL); ++ rcu_assign_pointer(ipv6_dev_get_saddr_hook, __ipv6_dev_get_saddr); ++ + return 0; + errout: + rtnl_af_unregister(&inet6_ops); +@@ -5829,6 +5831,9 @@ void addrconf_cleanup(void) + struct net_device *dev; + int i; + ++ rcu_assign_pointer(ipv6_dev_get_saddr_hook, NULL); ++ synchronize_rcu(); ++ + unregister_netdevice_notifier(&ipv6_dev_notf); + unregister_pernet_subsys(&addrconf_ops); + ipv6_addr_label_cleanup(); +--- /dev/null ++++ b/net/ipv6/inet6_stubs.c +@@ -0,0 +1,33 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++ ++int (*ipv6_dev_get_saddr_hook)(struct net *net, const struct net_device *dev, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr); ++ ++EXPORT_SYMBOL(ipv6_dev_get_saddr_hook); ++ ++int ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr) ++{ ++ int ret = -EADDRNOTAVAIL; ++ typeof(ipv6_dev_get_saddr_hook) dev_get_saddr; ++ ++ rcu_read_lock(); ++ dev_get_saddr = rcu_dereference(ipv6_dev_get_saddr_hook); ++ ++ if (dev_get_saddr) ++ ret = dev_get_saddr(net, dst_dev, daddr, prefs, saddr); ++ ++ rcu_read_unlock(); ++ return ret; ++} ++EXPORT_SYMBOL(ipv6_dev_get_saddr); ++ diff --git a/target/linux/generic/patches-4.1/645-bridge_multicast_to_unicast.patch b/target/linux/generic/patches-4.1/645-bridge_multicast_to_unicast.patch new file mode 100644 index 0000000..1ea6fc6 --- /dev/null +++ b/target/linux/generic/patches-4.1/645-bridge_multicast_to_unicast.patch @@ -0,0 +1,397 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: multicast to unicast + +Implement optinal multicast->unicast conversion for igmp snooping +--- +--- a/include/linux/if_bridge.h ++++ b/include/linux/if_bridge.h +@@ -46,6 +46,7 @@ struct br_ip_list { + #define BR_LEARNING_SYNC BIT(9) + #define BR_PROXYARP_WIFI BIT(10) + #define BR_ISOLATE_MODE BIT(11) ++#define BR_MULTICAST_TO_UCAST BIT(12) + + extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *)); + +--- a/net/bridge/br_multicast.c ++++ b/net/bridge/br_multicast.c +@@ -635,7 +635,8 @@ struct net_bridge_port_group *br_multica + struct net_bridge_port *port, + struct br_ip *group, + struct net_bridge_port_group __rcu *next, +- unsigned char state) ++ unsigned char state, ++ const unsigned char *src) + { + struct net_bridge_port_group *p; + +@@ -650,12 +651,33 @@ struct net_bridge_port_group *br_multica + hlist_add_head(&p->mglist, &port->mglist); + setup_timer(&p->timer, br_multicast_port_group_expired, + (unsigned long)p); ++ if ((port->flags & BR_MULTICAST_TO_UCAST) && src) { ++ memcpy(p->eth_addr, src, ETH_ALEN); ++ p->unicast = true; ++ } + return p; + } + ++static bool br_port_group_equal(struct net_bridge_port_group *p, ++ struct net_bridge_port *port, ++ const unsigned char *src) ++{ ++ if (p->port != port) ++ return false; ++ ++ if (!p->unicast) ++ return true; ++ ++ if (!src) ++ return false; ++ ++ return ether_addr_equal(src, p->eth_addr); ++} ++ + static int br_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, +- struct br_ip *group) ++ struct br_ip *group, ++ const unsigned char *src) + { + struct net_bridge_mdb_entry *mp; + struct net_bridge_port_group *p; +@@ -682,13 +704,13 @@ static int br_multicast_add_group(struct + for (pp = &mp->ports; + (p = mlock_dereference(*pp, br)) != NULL; + pp = &p->next) { +- if (p->port == port) ++ if (br_port_group_equal(p, port, src)) + goto found; + if ((unsigned long)p->port < (unsigned long)port) + break; + } + +- p = br_multicast_new_port_group(port, group, *pp, MDB_TEMPORARY); ++ p = br_multicast_new_port_group(port, group, *pp, MDB_TEMPORARY, src); + if (unlikely(!p)) + goto err; + rcu_assign_pointer(*pp, p); +@@ -707,7 +729,7 @@ err: + static int br_ip4_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, + __be32 group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + +@@ -718,14 +740,14 @@ static int br_ip4_multicast_add_group(st + br_group.proto = htons(ETH_P_IP); + br_group.vid = vid; + +- return br_multicast_add_group(br, port, &br_group); ++ return br_multicast_add_group(br, port, &br_group, src); + } + + #if IS_ENABLED(CONFIG_IPV6) + static int br_ip6_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + +@@ -736,7 +758,7 @@ static int br_ip6_multicast_add_group(st + br_group.proto = htons(ETH_P_IPV6); + br_group.vid = vid; + +- return br_multicast_add_group(br, port, &br_group); ++ return br_multicast_add_group(br, port, &br_group, src); + } + #endif + +@@ -966,6 +988,7 @@ static int br_ip4_multicast_igmp3_report + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct igmpv3_report *ih; + struct igmpv3_grec *grec; + int i; +@@ -1009,7 +1032,8 @@ static int br_ip4_multicast_igmp3_report + continue; + } + +- err = br_ip4_multicast_add_group(br, port, group, vid); ++ src = eth_hdr(skb)->h_source; ++ err = br_ip4_multicast_add_group(br, port, group, vid, src); + if (err) + break; + } +@@ -1023,6 +1047,7 @@ static int br_ip6_multicast_mld2_report( + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src = eth_hdr(skb)->h_source; + struct icmp6hdr *icmp6h; + struct mld2_grec *grec; + int i; +@@ -1071,7 +1096,7 @@ static int br_ip6_multicast_mld2_report( + } + + err = br_ip6_multicast_add_group(br, port, &grec->grec_mca, +- vid); ++ vid, src); + if (err) + break; + } +@@ -1407,7 +1432,8 @@ br_multicast_leave_group(struct net_brid + struct net_bridge_port *port, + struct br_ip *group, + struct bridge_mcast_other_query *other_query, +- struct bridge_mcast_own_query *own_query) ++ struct bridge_mcast_own_query *own_query, ++ const unsigned char *src) + { + struct net_bridge_mdb_htable *mdb; + struct net_bridge_mdb_entry *mp; +@@ -1457,7 +1483,7 @@ br_multicast_leave_group(struct net_brid + for (pp = &mp->ports; + (p = mlock_dereference(*pp, br)) != NULL; + pp = &p->next) { +- if (p->port != port) ++ if (!br_port_group_equal(p, port, src)) + continue; + + rcu_assign_pointer(*pp, p->next); +@@ -1491,7 +1517,7 @@ br_multicast_leave_group(struct net_brid + for (p = mlock_dereference(mp->ports, br); + p != NULL; + p = mlock_dereference(p->next, br)) { +- if (p->port != port) ++ if (!br_port_group_equal(p, port, src)) + continue; + + if (!hlist_unhashed(&p->mglist) && +@@ -1509,8 +1535,8 @@ out: + + static void br_ip4_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, +- __be32 group, +- __u16 vid) ++ __be32 group, __u16 vid, ++ const unsigned char *src) + { + struct br_ip br_group; + struct bridge_mcast_own_query *own_query; +@@ -1525,14 +1551,14 @@ static void br_ip4_multicast_leave_group + br_group.vid = vid; + + br_multicast_leave_group(br, port, &br_group, &br->ip4_other_query, +- own_query); ++ own_query, src); + } + + #if IS_ENABLED(CONFIG_IPV6) + static void br_ip6_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + struct bridge_mcast_own_query *own_query; +@@ -1547,7 +1573,7 @@ static void br_ip6_multicast_leave_group + br_group.vid = vid; + + br_multicast_leave_group(br, port, &br_group, &br->ip6_other_query, +- own_query); ++ own_query, src); + } + #endif + +@@ -1556,6 +1582,7 @@ static int br_multicast_ipv4_rcv(struct + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct sk_buff *skb2 = skb; + const struct iphdr *iph; + struct igmphdr *ih; +@@ -1624,12 +1651,13 @@ static int br_multicast_ipv4_rcv(struct + + BR_INPUT_SKB_CB(skb)->igmp = 1; + ih = igmp_hdr(skb2); ++ src = eth_hdr(skb)->h_source; + + switch (ih->type) { + case IGMP_HOST_MEMBERSHIP_REPORT: + case IGMPV2_HOST_MEMBERSHIP_REPORT: + BR_INPUT_SKB_CB(skb)->mrouters_only = 1; +- err = br_ip4_multicast_add_group(br, port, ih->group, vid); ++ err = br_ip4_multicast_add_group(br, port, ih->group, vid, src); + break; + case IGMPV3_HOST_MEMBERSHIP_REPORT: + err = br_ip4_multicast_igmp3_report(br, port, skb2, vid); +@@ -1638,7 +1666,7 @@ static int br_multicast_ipv4_rcv(struct + err = br_ip4_multicast_query(br, port, skb2, vid); + break; + case IGMP_HOST_LEAVE_MESSAGE: +- br_ip4_multicast_leave_group(br, port, ih->group, vid); ++ br_ip4_multicast_leave_group(br, port, ih->group, vid, src); + break; + } + +@@ -1656,6 +1684,7 @@ static int br_multicast_ipv6_rcv(struct + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct sk_buff *skb2; + const struct ipv6hdr *ip6h; + u8 icmp6_type; +@@ -1763,9 +1792,11 @@ static int br_multicast_ipv6_rcv(struct + err = -EINVAL; + goto out; + } ++ src = eth_hdr(skb)->h_source; + mld = (struct mld_msg *)skb_transport_header(skb2); + BR_INPUT_SKB_CB(skb)->mrouters_only = 1; +- err = br_ip6_multicast_add_group(br, port, &mld->mld_mca, vid); ++ err = br_ip6_multicast_add_group(br, port, &mld->mld_mca, vid, ++ src); + break; + } + case ICMPV6_MLD2_REPORT: +@@ -1781,8 +1812,9 @@ static int br_multicast_ipv6_rcv(struct + err = -EINVAL; + goto out; + } ++ src = eth_hdr(skb)->h_source; + mld = (struct mld_msg *)skb_transport_header(skb2); +- br_ip6_multicast_leave_group(br, port, &mld->mld_mca, vid); ++ br_ip6_multicast_leave_group(br, port, &mld->mld_mca, vid, src); + } + } + +--- a/net/bridge/br_private.h ++++ b/net/bridge/br_private.h +@@ -113,6 +113,9 @@ struct net_bridge_port_group { + struct timer_list timer; + struct br_ip addr; + unsigned char state; ++ ++ unsigned char eth_addr[ETH_ALEN]; ++ bool unicast; + }; + + struct net_bridge_mdb_entry +@@ -481,7 +484,8 @@ void br_multicast_free_pg(struct rcu_hea + struct net_bridge_port_group * + br_multicast_new_port_group(struct net_bridge_port *port, struct br_ip *group, + struct net_bridge_port_group __rcu *next, +- unsigned char state); ++ unsigned char state, ++ const unsigned char *src); + void br_mdb_init(void); + void br_mdb_uninit(void); + void br_mdb_notify(struct net_device *dev, struct net_bridge_port *port, +--- a/net/bridge/br_mdb.c ++++ b/net/bridge/br_mdb.c +@@ -343,7 +343,7 @@ static int br_mdb_add_group(struct net_b + break; + } + +- p = br_multicast_new_port_group(port, group, *pp, state); ++ p = br_multicast_new_port_group(port, group, *pp, state, NULL); + if (unlikely(!p)) + return -ENOMEM; + rcu_assign_pointer(*pp, p); +--- a/net/bridge/br_forward.c ++++ b/net/bridge/br_forward.c +@@ -170,6 +170,34 @@ out: + return p; + } + ++static struct net_bridge_port *maybe_deliver_addr( ++ struct net_bridge_port *prev, struct net_bridge_port *p, ++ struct sk_buff *skb, const unsigned char *addr, ++ void (*__packet_hook)(const struct net_bridge_port *p, ++ struct sk_buff *skb)) ++{ ++ struct net_device *dev = BR_INPUT_SKB_CB(skb)->brdev; ++ const unsigned char *src = eth_hdr(skb)->h_source; ++ ++ if (!should_deliver(p, skb)) ++ return prev; ++ ++ /* Even with hairpin, no soliloquies - prevent breaking IPv6 DAD */ ++ if (skb->dev == p->dev && ether_addr_equal(src, addr)) ++ return prev; ++ ++ skb = skb_copy(skb, GFP_ATOMIC); ++ if (!skb) { ++ dev->stats.tx_dropped++; ++ return prev; ++ } ++ ++ memcpy(eth_hdr(skb)->h_dest, addr, ETH_ALEN); ++ __packet_hook(p, skb); ++ ++ return prev; ++} ++ + /* called under bridge lock */ + static void br_flood(struct net_bridge *br, struct sk_buff *skb, + struct sk_buff *skb0, +@@ -242,6 +270,7 @@ static void br_multicast_flood(struct ne + struct net_bridge_port *prev = NULL; + struct net_bridge_port_group *p; + struct hlist_node *rp; ++ const unsigned char *addr; + + rp = rcu_dereference(hlist_first_rcu(&br->router_list)); + p = mdst ? rcu_dereference(mdst->ports) : NULL; +@@ -252,10 +281,19 @@ static void br_multicast_flood(struct ne + rport = rp ? hlist_entry(rp, struct net_bridge_port, rlist) : + NULL; + +- port = (unsigned long)lport > (unsigned long)rport ? +- lport : rport; +- +- prev = maybe_deliver(prev, port, skb, __packet_hook); ++ if ((unsigned long)lport > (unsigned long)rport) { ++ port = lport; ++ addr = p->unicast ? p->eth_addr : NULL; ++ } else { ++ port = rport; ++ addr = NULL; ++ } ++ ++ if (addr) ++ prev = maybe_deliver_addr(prev, port, skb, addr, ++ __packet_hook); ++ else ++ prev = maybe_deliver(prev, port, skb, __packet_hook); + if (IS_ERR(prev)) + goto out; + +--- a/net/bridge/br_sysfs_if.c ++++ b/net/bridge/br_sysfs_if.c +@@ -204,6 +204,7 @@ static BRPORT_ATTR(multicast_router, S_I + store_multicast_router); + + BRPORT_ATTR_FLAG(multicast_fast_leave, BR_MULTICAST_FAST_LEAVE); ++BRPORT_ATTR_FLAG(multicast_to_unicast, BR_MULTICAST_TO_UCAST); + #endif + + static const struct brport_attribute *brport_attrs[] = { +@@ -230,6 +231,7 @@ static const struct brport_attribute *br + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + &brport_attr_multicast_router, + &brport_attr_multicast_fast_leave, ++ &brport_attr_multicast_to_unicast, + #endif + &brport_attr_proxyarp, + &brport_attr_proxyarp_wifi, diff --git a/target/linux/generic/patches-4.1/650-pppoe_header_pad.patch b/target/linux/generic/patches-4.1/650-pppoe_header_pad.patch new file mode 100644 index 0000000..2804469 --- /dev/null +++ b/target/linux/generic/patches-4.1/650-pppoe_header_pad.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -871,7 +871,7 @@ static int pppoe_sendmsg(struct socket * + goto end; + + +- skb = sock_wmalloc(sk, total_len + dev->hard_header_len + 32, ++ skb = sock_wmalloc(sk, total_len + dev->hard_header_len + 32 + NET_SKB_PAD, + 0, GFP_KERNEL); + if (!skb) { + error = -ENOMEM; +@@ -879,7 +879,7 @@ static int pppoe_sendmsg(struct socket * + } + + /* Reserve space for headers. */ +- skb_reserve(skb, dev->hard_header_len); ++ skb_reserve(skb, dev->hard_header_len + NET_SKB_PAD); + skb_reset_network_header(skb); + + skb->dev = dev; diff --git a/target/linux/generic/patches-4.1/651-wireless_mesh_header.patch b/target/linux/generic/patches-4.1/651-wireless_mesh_header.patch new file mode 100644 index 0000000..17bcb6d --- /dev/null +++ b/target/linux/generic/patches-4.1/651-wireless_mesh_header.patch @@ -0,0 +1,11 @@ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -133,7 +133,7 @@ static inline bool dev_xmit_complete(int + */ + + #if defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) +-# if defined(CONFIG_MAC80211_MESH) ++# if 1 || defined(CONFIG_MAC80211_MESH) + # define LL_MAX_HEADER 128 + # else + # define LL_MAX_HEADER 96 diff --git a/target/linux/generic/patches-4.1/653-disable_netlink_trim.patch b/target/linux/generic/patches-4.1/653-disable_netlink_trim.patch new file mode 100644 index 0000000..5df265b --- /dev/null +++ b/target/linux/generic/patches-4.1/653-disable_netlink_trim.patch @@ -0,0 +1,30 @@ +--- a/net/netlink/af_netlink.c ++++ b/net/netlink/af_netlink.c +@@ -1775,27 +1775,7 @@ void netlink_detachskb(struct sock *sk, + + static struct sk_buff *netlink_trim(struct sk_buff *skb, gfp_t allocation) + { +- int delta; +- + WARN_ON(skb->sk != NULL); +- if (netlink_skb_is_mmaped(skb)) +- return skb; +- +- delta = skb->end - skb->tail; +- if (is_vmalloc_addr(skb->head) || delta * 2 < skb->truesize) +- return skb; +- +- if (skb_shared(skb)) { +- struct sk_buff *nskb = skb_clone(skb, allocation); +- if (!nskb) +- return skb; +- consume_skb(skb); +- skb = nskb; +- } +- +- if (!pskb_expand_head(skb, 0, -delta, allocation)) +- skb->truesize -= delta; +- + return skb; + } + diff --git a/target/linux/generic/patches-4.1/655-increase_skb_pad.patch b/target/linux/generic/patches-4.1/655-increase_skb_pad.patch new file mode 100644 index 0000000..c4aee07 --- /dev/null +++ b/target/linux/generic/patches-4.1/655-increase_skb_pad.patch @@ -0,0 +1,11 @@ +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2027,7 +2027,7 @@ static inline int pskb_network_may_pull( + * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8) + */ + #ifndef NET_SKB_PAD +-#define NET_SKB_PAD max(32, L1_CACHE_BYTES) ++#define NET_SKB_PAD max(64, L1_CACHE_BYTES) + #endif + + int ___pskb_trim(struct sk_buff *skb, unsigned int len); diff --git a/target/linux/generic/patches-4.1/656-skb_reduce_truesize-helper.patch b/target/linux/generic/patches-4.1/656-skb_reduce_truesize-helper.patch new file mode 100644 index 0000000..72e5c26 --- /dev/null +++ b/target/linux/generic/patches-4.1/656-skb_reduce_truesize-helper.patch @@ -0,0 +1,41 @@ +From 4593a806e31119c5bd3faa00c7210ad862d515af Mon Sep 17 00:00:00 2001 +From: Dave Taht +Date: Mon, 31 Dec 2012 10:02:21 -0800 +Subject: [PATCH 3/7] skb_reduce_truesize: helper function for shrinking skbs + whenever needed + +On embedded devices in particular, large queues of small packets from the rx +path with a large truesize can exist. Reducing their size can reduce +memory pressure. skb_reduce_truesize is a helper function for doing this, +when needed. +--- + include/linux/skbuff.h | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2072,6 +2072,24 @@ static inline void pskb_trim_unique(stru + BUG_ON(err); + } + ++/* ++ * Caller wants to reduce memory needs before queueing skb ++ * The (expensive) copy should not be be done in fast path. ++ */ ++static inline struct sk_buff *skb_reduce_truesize(struct sk_buff *skb) ++{ ++ if (skb->truesize > 2 * SKB_TRUESIZE(skb->len)) { ++ struct sk_buff *nskb; ++ nskb = skb_copy_expand(skb, skb_headroom(skb), 0, ++ GFP_ATOMIC | __GFP_NOWARN); ++ if (nskb) { ++ __kfree_skb(skb); ++ skb = nskb; ++ } ++ } ++ return skb; ++} ++ + /** + * skb_orphan - orphan a buffer + * @skb: buffer to orphan diff --git a/target/linux/generic/patches-4.1/657-qdisc_reduce_truesize.patch b/target/linux/generic/patches-4.1/657-qdisc_reduce_truesize.patch new file mode 100644 index 0000000..6777eec --- /dev/null +++ b/target/linux/generic/patches-4.1/657-qdisc_reduce_truesize.patch @@ -0,0 +1,63 @@ +From bc9fec2f87d57bdbff30d296605e24504513f65c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Dave=20T=C3=A4ht?= +Date: Mon, 17 Sep 2012 19:20:22 -0700 +Subject: [PATCH 4/7] net: add skb_reduce_truesize support to common qdiscs + +Reduce skb size under load when queues begin to fill on the +commont qdiscs. +--- + net/sched/sch_codel.c | 2 ++ + net/sched/sch_fifo.c | 12 ++++++++---- + net/sched/sch_fq_codel.c | 2 ++ + 3 files changed, 12 insertions(+), 4 deletions(-) + +--- a/net/sched/sch_codel.c ++++ b/net/sched/sch_codel.c +@@ -96,6 +96,8 @@ static int codel_qdisc_enqueue(struct sk + struct codel_sched_data *q; + + if (likely(qdisc_qlen(sch) < sch->limit)) { ++ if(qdisc_qlen(sch) > 128) ++ skb = skb_reduce_truesize(skb); + codel_set_enqueue_time(skb); + return qdisc_enqueue_tail(skb, sch); + } +--- a/net/sched/sch_fifo.c ++++ b/net/sched/sch_fifo.c +@@ -29,17 +29,21 @@ static int bfifo_enqueue(struct sk_buff + + static int pfifo_enqueue(struct sk_buff *skb, struct Qdisc *sch) + { +- if (likely(skb_queue_len(&sch->q) < sch->limit)) ++ if (likely(skb_queue_len(&sch->q) < sch->limit)) { ++ if (skb_queue_len(&sch->q) > 128) ++ skb = skb_reduce_truesize(skb); + return qdisc_enqueue_tail(skb, sch); +- ++ } + return qdisc_reshape_fail(skb, sch); + } + + static int pfifo_tail_enqueue(struct sk_buff *skb, struct Qdisc *sch) + { +- if (likely(skb_queue_len(&sch->q) < sch->limit)) ++ if (likely(skb_queue_len(&sch->q) < sch->limit)) { ++ if (skb_queue_len(&sch->q) > 128) ++ skb = skb_reduce_truesize(skb); + return qdisc_enqueue_tail(skb, sch); +- ++ } + /* queue full, remove one skb to fulfill the limit */ + __qdisc_queue_drop_head(sch, &sch->q); + qdisc_qstats_drop(sch); +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -185,6 +185,8 @@ static int fq_codel_enqueue(struct sk_bu + return ret; + } + idx--; ++ if (sch->q.qlen > 128) ++ skb = skb_reduce_truesize(skb); + + codel_set_enqueue_time(skb); + flow = &q->flows[idx]; diff --git a/target/linux/generic/patches-4.1/660-fq_codel_defaults.patch b/target/linux/generic/patches-4.1/660-fq_codel_defaults.patch new file mode 100644 index 0000000..f7f4659 --- /dev/null +++ b/target/linux/generic/patches-4.1/660-fq_codel_defaults.patch @@ -0,0 +1,14 @@ +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -387,9 +387,9 @@ static int fq_codel_init(struct Qdisc *s + struct fq_codel_sched_data *q = qdisc_priv(sch); + int i; + +- sch->limit = 10*1024; ++ sch->limit = 1024; + q->flows_cnt = 1024; +- q->quantum = psched_mtu(qdisc_dev(sch)); ++ q->quantum = 300; + q->perturbation = prandom_u32(); + INIT_LIST_HEAD(&q->new_flows); + INIT_LIST_HEAD(&q->old_flows); diff --git a/target/linux/generic/patches-4.1/661-fq_codel_keep_dropped_stats.patch b/target/linux/generic/patches-4.1/661-fq_codel_keep_dropped_stats.patch new file mode 100644 index 0000000..45a8d68 --- /dev/null +++ b/target/linux/generic/patches-4.1/661-fq_codel_keep_dropped_stats.patch @@ -0,0 +1,10 @@ +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -198,7 +198,6 @@ static int fq_codel_enqueue(struct sk_bu + list_add_tail(&flow->flowchain, &q->new_flows); + q->new_flow_count++; + flow->deficit = q->quantum; +- flow->dropped = 0; + } + if (++sch->q.qlen <= sch->limit) + return NET_XMIT_SUCCESS; diff --git a/target/linux/generic/patches-4.1/662-use_fq_codel_by_default.patch b/target/linux/generic/patches-4.1/662-use_fq_codel_by_default.patch new file mode 100644 index 0000000..e7b781b --- /dev/null +++ b/target/linux/generic/patches-4.1/662-use_fq_codel_by_default.patch @@ -0,0 +1,75 @@ +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -3,8 +3,9 @@ + # + + menuconfig NET_SCHED +- bool "QoS and/or fair queueing" ++ def_bool y + select NET_SCH_FIFO ++ select NET_SCH_FQ_CODEL + ---help--- + When the kernel has several packets to send out over a network + device, it has to decide which ones to send first, which ones to +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -592,7 +592,7 @@ static const struct Qdisc_class_ops fq_c + .walk = fq_codel_walk, + }; + +-static struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = { ++struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = { + .cl_ops = &fq_codel_class_ops, + .id = "fq_codel", + .priv_size = sizeof(struct fq_codel_sched_data), +@@ -608,6 +608,7 @@ static struct Qdisc_ops fq_codel_qdisc_o + .dump_stats = fq_codel_dump_stats, + .owner = THIS_MODULE, + }; ++EXPORT_SYMBOL(fq_codel_qdisc_ops); + + static int __init fq_codel_module_init(void) + { +--- a/include/net/sch_generic.h ++++ b/include/net/sch_generic.h +@@ -340,6 +340,7 @@ extern struct Qdisc noop_qdisc; + extern struct Qdisc_ops noop_qdisc_ops; + extern struct Qdisc_ops pfifo_fast_ops; + extern struct Qdisc_ops mq_qdisc_ops; ++extern struct Qdisc_ops fq_codel_qdisc_ops; + extern const struct Qdisc_ops *default_qdisc_ops; + + struct Qdisc_class_common { +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -737,7 +737,7 @@ static void attach_one_default_qdisc(str + + if (dev->tx_queue_len) { + qdisc = qdisc_create_dflt(dev_queue, +- default_qdisc_ops, TC_H_ROOT); ++ &fq_codel_qdisc_ops, TC_H_ROOT); + if (!qdisc) { + netdev_info(dev, "activation failed\n"); + return; +--- a/net/sched/sch_mq.c ++++ b/net/sched/sch_mq.c +@@ -57,7 +57,7 @@ static int mq_init(struct Qdisc *sch, st + + for (ntx = 0; ntx < dev->num_tx_queues; ntx++) { + dev_queue = netdev_get_tx_queue(dev, ntx); +- qdisc = qdisc_create_dflt(dev_queue, default_qdisc_ops, ++ qdisc = qdisc_create_dflt(dev_queue, &fq_codel_qdisc_ops, + TC_H_MAKE(TC_H_MAJ(sch->handle), + TC_H_MIN(ntx + 1))); + if (qdisc == NULL) +--- a/net/sched/sch_mqprio.c ++++ b/net/sched/sch_mqprio.c +@@ -124,7 +124,7 @@ static int mqprio_init(struct Qdisc *sch + + for (i = 0; i < dev->num_tx_queues; i++) { + dev_queue = netdev_get_tx_queue(dev, i); +- qdisc = qdisc_create_dflt(dev_queue, default_qdisc_ops, ++ qdisc = qdisc_create_dflt(dev_queue, &fq_codel_qdisc_ops, + TC_H_MAKE(TC_H_MAJ(sch->handle), + TC_H_MIN(i + 1))); + if (qdisc == NULL) { diff --git a/target/linux/generic/patches-4.1/663-remove_pfifo_fast.patch b/target/linux/generic/patches-4.1/663-remove_pfifo_fast.patch new file mode 100644 index 0000000..5b26ca3 --- /dev/null +++ b/target/linux/generic/patches-4.1/663-remove_pfifo_fast.patch @@ -0,0 +1,143 @@ +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -442,140 +442,6 @@ static struct Qdisc noqueue_qdisc = { + .busylock = __SPIN_LOCK_UNLOCKED(noqueue_qdisc.busylock), + }; + +- +-static const u8 prio2band[TC_PRIO_MAX + 1] = { +- 1, 2, 2, 2, 1, 2, 0, 0 , 1, 1, 1, 1, 1, 1, 1, 1 +-}; +- +-/* 3-band FIFO queue: old style, but should be a bit faster than +- generic prio+fifo combination. +- */ +- +-#define PFIFO_FAST_BANDS 3 +- +-/* +- * Private data for a pfifo_fast scheduler containing: +- * - queues for the three band +- * - bitmap indicating which of the bands contain skbs +- */ +-struct pfifo_fast_priv { +- u32 bitmap; +- struct sk_buff_head q[PFIFO_FAST_BANDS]; +-}; +- +-/* +- * Convert a bitmap to the first band number where an skb is queued, where: +- * bitmap=0 means there are no skbs on any band. +- * bitmap=1 means there is an skb on band 0. +- * bitmap=7 means there are skbs on all 3 bands, etc. +- */ +-static const int bitmap2band[] = {-1, 0, 1, 0, 2, 0, 1, 0}; +- +-static inline struct sk_buff_head *band2list(struct pfifo_fast_priv *priv, +- int band) +-{ +- return priv->q + band; +-} +- +-static int pfifo_fast_enqueue(struct sk_buff *skb, struct Qdisc *qdisc) +-{ +- if (skb_queue_len(&qdisc->q) < qdisc_dev(qdisc)->tx_queue_len) { +- int band = prio2band[skb->priority & TC_PRIO_MAX]; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- struct sk_buff_head *list = band2list(priv, band); +- +- priv->bitmap |= (1 << band); +- qdisc->q.qlen++; +- return __qdisc_enqueue_tail(skb, qdisc, list); +- } +- +- return qdisc_drop(skb, qdisc); +-} +- +-static struct sk_buff *pfifo_fast_dequeue(struct Qdisc *qdisc) +-{ +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- int band = bitmap2band[priv->bitmap]; +- +- if (likely(band >= 0)) { +- struct sk_buff_head *list = band2list(priv, band); +- struct sk_buff *skb = __qdisc_dequeue_head(qdisc, list); +- +- qdisc->q.qlen--; +- if (skb_queue_empty(list)) +- priv->bitmap &= ~(1 << band); +- +- return skb; +- } +- +- return NULL; +-} +- +-static struct sk_buff *pfifo_fast_peek(struct Qdisc *qdisc) +-{ +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- int band = bitmap2band[priv->bitmap]; +- +- if (band >= 0) { +- struct sk_buff_head *list = band2list(priv, band); +- +- return skb_peek(list); +- } +- +- return NULL; +-} +- +-static void pfifo_fast_reset(struct Qdisc *qdisc) +-{ +- int prio; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- +- for (prio = 0; prio < PFIFO_FAST_BANDS; prio++) +- __qdisc_reset_queue(qdisc, band2list(priv, prio)); +- +- priv->bitmap = 0; +- qdisc->qstats.backlog = 0; +- qdisc->q.qlen = 0; +-} +- +-static int pfifo_fast_dump(struct Qdisc *qdisc, struct sk_buff *skb) +-{ +- struct tc_prio_qopt opt = { .bands = PFIFO_FAST_BANDS }; +- +- memcpy(&opt.priomap, prio2band, TC_PRIO_MAX + 1); +- if (nla_put(skb, TCA_OPTIONS, sizeof(opt), &opt)) +- goto nla_put_failure; +- return skb->len; +- +-nla_put_failure: +- return -1; +-} +- +-static int pfifo_fast_init(struct Qdisc *qdisc, struct nlattr *opt) +-{ +- int prio; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- +- for (prio = 0; prio < PFIFO_FAST_BANDS; prio++) +- __skb_queue_head_init(band2list(priv, prio)); +- +- /* Can by-pass the queue discipline */ +- qdisc->flags |= TCQ_F_CAN_BYPASS; +- return 0; +-} +- +-struct Qdisc_ops pfifo_fast_ops __read_mostly = { +- .id = "pfifo_fast", +- .priv_size = sizeof(struct pfifo_fast_priv), +- .enqueue = pfifo_fast_enqueue, +- .dequeue = pfifo_fast_dequeue, +- .peek = pfifo_fast_peek, +- .init = pfifo_fast_init, +- .reset = pfifo_fast_reset, +- .dump = pfifo_fast_dump, +- .owner = THIS_MODULE, +-}; +- + static struct lock_class_key qdisc_tx_busylock; + + struct Qdisc *qdisc_alloc(struct netdev_queue *dev_queue, diff --git a/target/linux/generic/patches-4.1/664-codel_fix_3_12.patch b/target/linux/generic/patches-4.1/664-codel_fix_3_12.patch new file mode 100644 index 0000000..6b2cbc5 --- /dev/null +++ b/target/linux/generic/patches-4.1/664-codel_fix_3_12.patch @@ -0,0 +1,22 @@ +--- a/net/sched/sch_api.c ++++ b/net/sched/sch_api.c +@@ -1951,7 +1951,7 @@ static int __init pktsched_init(void) + return err; + } + +- register_qdisc(&pfifo_fast_ops); ++ register_qdisc(&fq_codel_qdisc_ops); + register_qdisc(&pfifo_qdisc_ops); + register_qdisc(&bfifo_qdisc_ops); + register_qdisc(&pfifo_head_drop_qdisc_ops); +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -31,7 +31,7 @@ + #include + + /* Qdisc to use by default */ +-const struct Qdisc_ops *default_qdisc_ops = &pfifo_fast_ops; ++const struct Qdisc_ops *default_qdisc_ops = &fq_codel_qdisc_ops; + EXPORT_SYMBOL(default_qdisc_ops); + + /* Main transmission queue. */ diff --git a/target/linux/generic/patches-4.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/patches-4.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch new file mode 100644 index 0000000..f40fc38 --- /dev/null +++ b/target/linux/generic/patches-4.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch @@ -0,0 +1,495 @@ +From 775d6fe74d1eaec2ba387535b068dde2dc89de9e Mon Sep 17 00:00:00 2001 +From: Steven Barth +Date: Thu, 22 May 2014 09:49:05 +0200 +Subject: [PATCH] Add support for MAP-E FMRs (mesh mode) + +MAP-E FMRs (draft-ietf-softwire-map-10) are rules for IPv4-communication +between MAP CEs (mesh mode) without the need to forward such data to a +border relay. This is similar to how 6rd works but for IPv4 over IPv6. + +Signed-off-by: Steven Barth +--- + include/net/ip6_tunnel.h | 13 ++ + include/uapi/linux/if_tunnel.h | 13 ++ + net/ipv6/ip6_tunnel.c | 276 +++++++++++++++++++++++++++++++++++++++-- + 3 files changed, 291 insertions(+), 11 deletions(-) + +--- a/include/net/ip6_tunnel.h ++++ b/include/net/ip6_tunnel.h +@@ -15,6 +15,18 @@ + /* determine capability on a per-packet basis */ + #define IP6_TNL_F_CAP_PER_PACKET 0x40000 + ++/* IPv6 tunnel FMR */ ++struct __ip6_tnl_fmr { ++ struct __ip6_tnl_fmr *next; /* next fmr in list */ ++ struct in6_addr ip6_prefix; ++ struct in_addr ip4_prefix; ++ ++ __u8 ip6_prefix_len; ++ __u8 ip4_prefix_len; ++ __u8 ea_len; ++ __u8 offset; ++}; ++ + struct __ip6_tnl_parm { + char name[IFNAMSIZ]; /* name of tunnel device */ + int link; /* ifindex of underlying L2 interface */ +@@ -25,6 +37,7 @@ struct __ip6_tnl_parm { + __u32 flags; /* tunnel flags */ + struct in6_addr laddr; /* local tunnel end-point address */ + struct in6_addr raddr; /* remote tunnel end-point address */ ++ struct __ip6_tnl_fmr *fmrs; /* FMRs */ + + __be16 i_flags; + __be16 o_flags; +--- a/include/uapi/linux/if_tunnel.h ++++ b/include/uapi/linux/if_tunnel.h +@@ -57,10 +57,23 @@ enum { + IFLA_IPTUN_ENCAP_FLAGS, + IFLA_IPTUN_ENCAP_SPORT, + IFLA_IPTUN_ENCAP_DPORT, ++ IFLA_IPTUN_FMRS, + __IFLA_IPTUN_MAX, + }; + #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) + ++enum { ++ IFLA_IPTUN_FMR_UNSPEC, ++ IFLA_IPTUN_FMR_IP6_PREFIX, ++ IFLA_IPTUN_FMR_IP4_PREFIX, ++ IFLA_IPTUN_FMR_IP6_PREFIX_LEN, ++ IFLA_IPTUN_FMR_IP4_PREFIX_LEN, ++ IFLA_IPTUN_FMR_EA_LEN, ++ IFLA_IPTUN_FMR_OFFSET, ++ __IFLA_IPTUN_FMR_MAX, ++}; ++#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1) ++ + enum tunnel_encap_types { + TUNNEL_ENCAP_NONE, + TUNNEL_ENCAP_FOU, +--- a/net/ipv6/ip6_tunnel.c ++++ b/net/ipv6/ip6_tunnel.c +@@ -16,6 +16,8 @@ + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * ++ * Changes: ++ * Steven Barth : MAP-E FMR support + */ + + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +@@ -71,11 +73,9 @@ static bool log_ecn_error = true; + module_param(log_ecn_error, bool, 0644); + MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN"); + +-static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2) ++static u32 HASH(const struct in6_addr *addr) + { +- u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2); +- +- return hash_32(hash, HASH_SIZE_SHIFT); ++ return hash_32(ipv6_addr_hash(addr), HASH_SIZE_SHIFT); + } + + static int ip6_tnl_dev_init(struct net_device *dev); +@@ -174,27 +174,36 @@ EXPORT_SYMBOL_GPL(ip6_tnl_dst_store); + static struct ip6_tnl * + ip6_tnl_lookup(struct net *net, const struct in6_addr *remote, const struct in6_addr *local) + { +- unsigned int hash = HASH(remote, local); ++ unsigned int hash = HASH(local); + struct ip6_tnl *t; + struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + struct in6_addr any; ++ struct __ip6_tnl_fmr *fmr; + + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { +- if (ipv6_addr_equal(local, &t->parms.laddr) && +- ipv6_addr_equal(remote, &t->parms.raddr) && +- (t->dev->flags & IFF_UP)) ++ if (!ipv6_addr_equal(local, &t->parms.laddr) || ++ !(t->dev->flags & IFF_UP)) ++ continue; ++ ++ if (ipv6_addr_equal(remote, &t->parms.raddr)) + return t; ++ ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { ++ if (ipv6_prefix_equal(remote, &fmr->ip6_prefix, ++ fmr->ip6_prefix_len)) ++ return t; ++ } + } + + memset(&any, 0, sizeof(any)); +- hash = HASH(&any, local); ++ hash = HASH(local); + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { + if (ipv6_addr_equal(local, &t->parms.laddr) && + (t->dev->flags & IFF_UP)) + return t; + } + +- hash = HASH(remote, &any); ++ hash = HASH(&any); + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { + if (ipv6_addr_equal(remote, &t->parms.raddr) && + (t->dev->flags & IFF_UP)) +@@ -229,7 +238,7 @@ ip6_tnl_bucket(struct ip6_tnl_net *ip6n, + + if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) { + prio = 1; +- h = HASH(remote, local); ++ h = HASH(local); + } + return &ip6n->tnls[prio][h]; + } +@@ -399,6 +408,12 @@ ip6_tnl_dev_uninit(struct net_device *de + struct net *net = t->net; + struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + ++ while (t->parms.fmrs) { ++ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; ++ kfree(t->parms.fmrs); ++ t->parms.fmrs = next; ++ } ++ + if (dev == ip6n->fb_tnl_dev) + RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL); + else +@@ -785,6 +800,108 @@ int ip6_tnl_rcv_ctl(struct ip6_tnl *t, + } + EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl); + ++ ++/** ++ * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR ++ * @dest: destination IPv6 address buffer ++ * @skb: received socket buffer ++ * @fmr: MAP FMR ++ * @xmit: Calculate for xmit or rcv ++ **/ ++static void ip4ip6_fmr_calc(struct in6_addr *dest, ++ const struct iphdr *iph, const uint8_t *end, ++ const struct __ip6_tnl_fmr *fmr, bool xmit) ++{ ++ int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len); ++ u8 *portp = NULL; ++ bool use_dest_addr; ++ const struct iphdr *dsth = iph; ++ ++ if ((u8*)dsth >= end) ++ return; ++ ++ /* find significant IP header */ ++ if (iph->protocol == IPPROTO_ICMP) { ++ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); ++ if (ih && ((u8*)&ih[1]) <= end && ( ++ ih->type == ICMP_DEST_UNREACH || ++ ih->type == ICMP_SOURCE_QUENCH || ++ ih->type == ICMP_TIME_EXCEEDED || ++ ih->type == ICMP_PARAMETERPROB || ++ ih->type == ICMP_REDIRECT)) ++ dsth = (const struct iphdr*)&ih[1]; ++ } ++ ++ /* in xmit-path use dest port by default and source port only if ++ this is an ICMP reply to something else; vice versa in rcv-path */ ++ use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph); ++ ++ /* get dst port */ ++ if (((u8*)&dsth[1]) <= end && ( ++ dsth->protocol == IPPROTO_UDP || ++ dsth->protocol == IPPROTO_TCP || ++ dsth->protocol == IPPROTO_SCTP || ++ dsth->protocol == IPPROTO_DCCP)) { ++ /* for UDP, TCP, SCTP and DCCP source and dest port ++ follow IPv4 header directly */ ++ portp = ((u8*)dsth) + dsth->ihl * 4; ++ ++ if (use_dest_addr) ++ portp += sizeof(u16); ++ } else if (iph->protocol == IPPROTO_ICMP) { ++ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); ++ ++ /* use icmp identifier as port */ ++ if (((u8*)&ih) <= end && ( ++ (use_dest_addr && ( ++ ih->type == ICMP_ECHOREPLY || ++ ih->type == ICMP_TIMESTAMPREPLY || ++ ih->type == ICMP_INFO_REPLY || ++ ih->type == ICMP_ADDRESSREPLY)) || ++ (!use_dest_addr && ( ++ ih->type == ICMP_ECHO || ++ ih->type == ICMP_TIMESTAMP || ++ ih->type == ICMP_INFO_REQUEST || ++ ih->type == ICMP_ADDRESS) ++ ))) ++ portp = (u8*)&ih->un.echo.id; ++ } ++ ++ if ((portp && &portp[2] <= end) || psidlen == 0) { ++ int frombyte = fmr->ip6_prefix_len / 8; ++ int fromrem = fmr->ip6_prefix_len % 8; ++ int bytes = sizeof(struct in6_addr) - frombyte; ++ const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr; ++ u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len); ++ u64 t = 0; ++ ++ /* extract PSID from port and add it to eabits */ ++ u16 psidbits = 0; ++ if (psidlen > 0) { ++ psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]); ++ psidbits >>= 16 - psidlen - fmr->offset; ++ psidbits = (u16)(psidbits << (16 - psidlen)); ++ eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen)); ++ } ++ ++ /* rewrite destination address */ ++ *dest = fmr->ip6_prefix; ++ memcpy(&dest->s6_addr[10], addr, sizeof(*addr)); ++ dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen)); ++ ++ if (bytes > sizeof(u64)) ++ bytes = sizeof(u64); ++ ++ /* insert eabits */ ++ memcpy(&t, &dest->s6_addr[frombyte], bytes); ++ t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1) ++ << (64 - fmr->ea_len - fromrem)); ++ t = cpu_to_be64(t | (eabits >> fromrem)); ++ memcpy(&dest->s6_addr[frombyte], &t, bytes); ++ } ++} ++ ++ + /** + * ip6_tnl_rcv - decapsulate IPv6 packet and retransmit it locally + * @skb: received socket buffer +@@ -830,6 +947,26 @@ static int ip6_tnl_rcv(struct sk_buff *s + skb_reset_network_header(skb); + skb->protocol = htons(protocol); + memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); ++ if (protocol == ETH_P_IP && ++ !ipv6_addr_equal(&ipv6h->saddr, &t->parms.raddr)) { ++ /* Packet didn't come from BR, so lookup FMR */ ++ struct __ip6_tnl_fmr *fmr; ++ struct in6_addr expected = t->parms.raddr; ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) ++ if (ipv6_prefix_equal(&ipv6h->saddr, ++ &fmr->ip6_prefix, fmr->ip6_prefix_len)) ++ break; ++ ++ /* Check that IPv6 matches IPv4 source to prevent spoofing */ ++ if (fmr) ++ ip4ip6_fmr_calc(&expected, ip_hdr(skb), ++ skb_tail_pointer(skb), fmr, false); ++ ++ if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) { ++ rcu_read_unlock(); ++ goto discard; ++ } ++ } + + __skb_tunnel_rx(skb, t->dev, t->net); + +@@ -1123,6 +1260,7 @@ ip4ip6_tnl_xmit(struct sk_buff *skb, str + __u32 mtu; + u8 tproto; + int err; ++ struct __ip6_tnl_fmr *fmr; + + tproto = ACCESS_ONCE(t->parms.proto); + if (tproto != IPPROTO_IPIP && tproto != 0) +@@ -1142,6 +1280,18 @@ ip4ip6_tnl_xmit(struct sk_buff *skb, str + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK) + fl6.flowi6_mark = skb->mark; + ++ /* try to find matching FMR */ ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { ++ unsigned mshift = 32 - fmr->ip4_prefix_len; ++ if (ntohl(fmr->ip4_prefix.s_addr) >> mshift == ++ ntohl(iph->daddr) >> mshift) ++ break; ++ } ++ ++ /* change dstaddr according to FMR */ ++ if (fmr) ++ ip4ip6_fmr_calc(&fl6.daddr, iph, skb_tail_pointer(skb), fmr, true); ++ + err = ip6_tnl_xmit2(skb, dev, dsfield, &fl6, encap_limit, &mtu); + if (err != 0) { + /* XXX: send ICMP error even if DF is not set. */ +@@ -1310,6 +1460,14 @@ ip6_tnl_change(struct ip6_tnl *t, const + t->parms.flowinfo = p->flowinfo; + t->parms.link = p->link; + t->parms.proto = p->proto; ++ ++ while (t->parms.fmrs) { ++ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; ++ kfree(t->parms.fmrs); ++ t->parms.fmrs = next; ++ } ++ t->parms.fmrs = p->fmrs; ++ + ip6_tnl_dst_reset(t); + ip6_tnl_link_config(t); + return 0; +@@ -1348,6 +1506,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_ + p->flowinfo = u->flowinfo; + p->link = u->link; + p->proto = u->proto; ++ p->fmrs = NULL; + memcpy(p->name, u->name, sizeof(u->name)); + } + +@@ -1634,6 +1793,15 @@ static int ip6_tnl_validate(struct nlatt + return 0; + } + ++static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = { ++ [IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) }, ++ [IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) }, ++ [IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 } ++}; ++ + static void ip6_tnl_netlink_parms(struct nlattr *data[], + struct __ip6_tnl_parm *parms) + { +@@ -1665,6 +1833,46 @@ static void ip6_tnl_netlink_parms(struct + + if (data[IFLA_IPTUN_PROTO]) + parms->proto = nla_get_u8(data[IFLA_IPTUN_PROTO]); ++ ++ if (data[IFLA_IPTUN_FMRS]) { ++ unsigned rem; ++ struct nlattr *fmr; ++ nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) { ++ struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c; ++ struct __ip6_tnl_fmr *nfmr; ++ ++ nla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX, ++ fmr, ip6_tnl_fmr_policy); ++ ++ if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL))) ++ continue; ++ ++ nfmr->offset = 6; ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX])) ++ nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX], ++ sizeof(nfmr->ip6_prefix)); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX])) ++ nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX], ++ sizeof(nfmr->ip4_prefix)); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN])) ++ nfmr->ip6_prefix_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN])) ++ nfmr->ip4_prefix_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN])) ++ nfmr->ea_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET])) ++ nfmr->offset = nla_get_u8(c); ++ ++ nfmr->next = parms->fmrs; ++ parms->fmrs = nfmr; ++ } ++ } + } + + static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev, +@@ -1717,6 +1925,12 @@ static void ip6_tnl_dellink(struct net_d + + static size_t ip6_tnl_get_size(const struct net_device *dev) + { ++ const struct ip6_tnl *t = netdev_priv(dev); ++ struct __ip6_tnl_fmr *c; ++ int fmrs = 0; ++ for (c = t->parms.fmrs; c; c = c->next) ++ ++fmrs; ++ + return + /* IFLA_IPTUN_LINK */ + nla_total_size(4) + +@@ -1734,6 +1948,24 @@ static size_t ip6_tnl_get_size(const str + nla_total_size(4) + + /* IFLA_IPTUN_PROTO */ + nla_total_size(1) + ++ /* IFLA_IPTUN_FMRS */ ++ nla_total_size(0) + ++ ( ++ /* nest */ ++ nla_total_size(0) + ++ /* IFLA_IPTUN_FMR_IP6_PREFIX */ ++ nla_total_size(sizeof(struct in6_addr)) + ++ /* IFLA_IPTUN_FMR_IP4_PREFIX */ ++ nla_total_size(sizeof(struct in_addr)) + ++ /* IFLA_IPTUN_FMR_EA_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_OFFSET */ ++ nla_total_size(1) ++ ) * fmrs + + 0; + } + +@@ -1741,6 +1973,9 @@ static int ip6_tnl_fill_info(struct sk_b + { + struct ip6_tnl *tunnel = netdev_priv(dev); + struct __ip6_tnl_parm *parm = &tunnel->parms; ++ struct __ip6_tnl_fmr *c; ++ int fmrcnt = 0; ++ struct nlattr *fmrs; + + if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || + nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || +@@ -1749,8 +1984,27 @@ static int ip6_tnl_fill_info(struct sk_b + nla_put_u8(skb, IFLA_IPTUN_ENCAP_LIMIT, parm->encap_limit) || + nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || + nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || +- nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto)) ++ nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || ++ !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS))) + goto nla_put_failure; ++ ++ for (c = parm->fmrs; c; c = c->next) { ++ struct nlattr *fmr = nla_nest_start(skb, ++fmrcnt); ++ if (!fmr || ++ nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX, ++ sizeof(c->ip6_prefix), &c->ip6_prefix) || ++ nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX, ++ sizeof(c->ip4_prefix), &c->ip4_prefix) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset)) ++ goto nla_put_failure; ++ ++ nla_nest_end(skb, fmr); ++ } ++ nla_nest_end(skb, fmrs); ++ + return 0; + + nla_put_failure: +@@ -1774,6 +2028,7 @@ static const struct nla_policy ip6_tnl_p + [IFLA_IPTUN_FLOWINFO] = { .type = NLA_U32 }, + [IFLA_IPTUN_FLAGS] = { .type = NLA_U32 }, + [IFLA_IPTUN_PROTO] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMRS] = { .type = NLA_NESTED }, + }; + + static struct rtnl_link_ops ip6_link_ops __read_mostly = { diff --git a/target/linux/generic/patches-4.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/patches-4.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch new file mode 100644 index 0000000..0c453ff --- /dev/null +++ b/target/linux/generic/patches-4.1/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -0,0 +1,249 @@ +From 1b5aaa4b16f6e6471ab1c07b38068197a1b4c395 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 24 May 2013 14:40:54 +0200 +Subject: [PATCH 1/2] ipv6: allow rejecting with "source address failed policy" + +RFC6204 L-14 requires rejecting traffic from invalid addresses with +ICMPv6 Destination Unreachable, Code 5 (Source address failed ingress/ +egress policy) on the LAN side, so add an appropriate rule for that. + +Signed-off-by: Jonas Gorski +--- + include/net/netns/ipv6.h | 1 + + include/uapi/linux/fib_rules.h | 4 +++ + include/uapi/linux/rtnetlink.h | 1 + + net/ipv4/fib_semantics.c | 4 +++ + net/ipv4/fib_trie.c | 1 + + net/ipv4/ipmr.c | 1 + + net/ipv6/fib6_rules.c | 4 +++ + net/ipv6/ip6mr.c | 2 ++ + net/ipv6/route.c | 58 +++++++++++++++++++++++++++++++++++++++++- + 9 files changed, 75 insertions(+), 1 deletion(-) + +--- a/include/net/netns/ipv6.h ++++ b/include/net/netns/ipv6.h +@@ -61,6 +61,7 @@ struct netns_ipv6 { + unsigned long ip6_rt_last_gc; + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + struct rt6_info *ip6_prohibit_entry; ++ struct rt6_info *ip6_policy_failed_entry; + struct rt6_info *ip6_blk_hole_entry; + struct fib6_table *fib6_local_tbl; + struct fib_rules_ops *fib6_rules_ops; +--- a/include/uapi/linux/fib_rules.h ++++ b/include/uapi/linux/fib_rules.h +@@ -64,6 +64,10 @@ enum { + FR_ACT_BLACKHOLE, /* Drop without notification */ + FR_ACT_UNREACHABLE, /* Drop with ENETUNREACH */ + FR_ACT_PROHIBIT, /* Drop with EACCES */ ++ FR_ACT_RES9, ++ FR_ACT_RES10, ++ FR_ACT_RES11, ++ FR_ACT_POLICY_FAILED, /* Drop with EACCES */ + __FR_ACT_MAX, + }; + +--- a/include/uapi/linux/rtnetlink.h ++++ b/include/uapi/linux/rtnetlink.h +@@ -210,6 +210,7 @@ enum { + RTN_THROW, /* Not in this table */ + RTN_NAT, /* Translate this address */ + RTN_XRESOLVE, /* Use external resolver */ ++ RTN_POLICY_FAILED, /* Failed ingress/egress policy */ + __RTN_MAX + }; + +--- a/net/ipv4/fib_semantics.c ++++ b/net/ipv4/fib_semantics.c +@@ -138,6 +138,10 @@ const struct fib_prop fib_props[RTN_MAX + .error = -EINVAL, + .scope = RT_SCOPE_NOWHERE, + }, ++ [RTN_POLICY_FAILED] = { ++ .error = -EACCES, ++ .scope = RT_SCOPE_UNIVERSE, ++ }, + }; + + static void rt_fibinfo_free(struct rtable __rcu **rtp) +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -2348,6 +2348,7 @@ static const char *const rtn_type_names[ + [RTN_THROW] = "THROW", + [RTN_NAT] = "NAT", + [RTN_XRESOLVE] = "XRESOLVE", ++ [RTN_POLICY_FAILED] = "POLICY_FAILED", + }; + + static inline const char *rtn_type(char *buf, size_t len, unsigned int t) +--- a/net/ipv4/ipmr.c ++++ b/net/ipv4/ipmr.c +@@ -182,6 +182,7 @@ static int ipmr_rule_action(struct fib_r + case FR_ACT_UNREACHABLE: + return -ENETUNREACH; + case FR_ACT_PROHIBIT: ++ case FR_ACT_POLICY_FAILED: + return -EACCES; + case FR_ACT_BLACKHOLE: + default: +--- a/net/ipv6/fib6_rules.c ++++ b/net/ipv6/fib6_rules.c +@@ -73,6 +73,10 @@ static int fib6_rule_action(struct fib_r + err = -EACCES; + rt = net->ipv6.ip6_prohibit_entry; + goto discard_pkt; ++ case FR_ACT_POLICY_FAILED: ++ err = -EACCES; ++ rt = net->ipv6.ip6_policy_failed_entry; ++ goto discard_pkt; + } + + table = fib6_get_table(net, rule->table); +--- a/net/ipv6/ip6mr.c ++++ b/net/ipv6/ip6mr.c +@@ -167,6 +167,8 @@ static int ip6mr_rule_action(struct fib_ + return -ENETUNREACH; + case FR_ACT_PROHIBIT: + return -EACCES; ++ case FR_ACT_POLICY_FAILED: ++ return -EACCES; + case FR_ACT_BLACKHOLE: + default: + return -EINVAL; +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -87,6 +87,8 @@ static int ip6_pkt_discard(struct sk_bu + static int ip6_pkt_discard_out(struct sock *sk, struct sk_buff *skb); + static int ip6_pkt_prohibit(struct sk_buff *skb); + static int ip6_pkt_prohibit_out(struct sock *sk, struct sk_buff *skb); ++static int ip6_pkt_policy_failed(struct sk_buff *skb); ++static int ip6_pkt_policy_failed_out(struct sock *sk, struct sk_buff *skb); + static void ip6_link_failure(struct sk_buff *skb); + static void ip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk, + struct sk_buff *skb, u32 mtu); +@@ -281,6 +283,21 @@ static const struct rt6_info ip6_prohibi + .rt6i_ref = ATOMIC_INIT(1), + }; + ++static const struct rt6_info ip6_policy_failed_entry_template = { ++ .dst = { ++ .__refcnt = ATOMIC_INIT(1), ++ .__use = 1, ++ .obsolete = DST_OBSOLETE_FORCE_CHK, ++ .error = -EACCES, ++ .input = ip6_pkt_policy_failed, ++ .output = ip6_pkt_policy_failed_out, ++ }, ++ .rt6i_flags = (RTF_REJECT | RTF_NONEXTHOP), ++ .rt6i_protocol = RTPROT_KERNEL, ++ .rt6i_metric = ~(u32) 0, ++ .rt6i_ref = ATOMIC_INIT(1), ++}; ++ + static const struct rt6_info ip6_blk_hole_entry_template = { + .dst = { + .__refcnt = ATOMIC_INIT(1), +@@ -1634,6 +1651,11 @@ int ip6_route_info_create(struct fib6_co + rt->dst.output = ip6_pkt_prohibit_out; + rt->dst.input = ip6_pkt_prohibit; + break; ++ case RTN_POLICY_FAILED: ++ rt->dst.error = -EACCES; ++ rt->dst.output = ip6_pkt_policy_failed_out; ++ rt->dst.input = ip6_pkt_policy_failed; ++ break; + case RTN_THROW: + default: + rt->dst.error = (cfg->fc_type == RTN_THROW) ? -EAGAIN +@@ -2225,6 +2247,17 @@ static int ip6_pkt_prohibit_out(struct s + return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES); + } + ++static int ip6_pkt_policy_failed(struct sk_buff *skb) ++{ ++ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_INNOROUTES); ++} ++ ++static int ip6_pkt_policy_failed_out(struct sock *sk, struct sk_buff *skb) ++{ ++ skb->dev = skb_dst(skb)->dev; ++ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_OUTNOROUTES); ++} ++ + /* + * Allocate a dst for local (unicast / anycast) address. + */ +@@ -2451,7 +2484,8 @@ static int rtm_to_fib6_config(struct sk_ + if (rtm->rtm_type == RTN_UNREACHABLE || + rtm->rtm_type == RTN_BLACKHOLE || + rtm->rtm_type == RTN_PROHIBIT || +- rtm->rtm_type == RTN_THROW) ++ rtm->rtm_type == RTN_THROW || ++ rtm->rtm_type == RTN_POLICY_FAILED) + cfg->fc_flags |= RTF_REJECT; + + if (rtm->rtm_type == RTN_LOCAL) +@@ -2793,6 +2827,9 @@ static int rt6_fill_node(struct net *net + case -EACCES: + rtm->rtm_type = RTN_PROHIBIT; + break; ++ case -EPERM: ++ rtm->rtm_type = RTN_POLICY_FAILED; ++ break; + case -EAGAIN: + rtm->rtm_type = RTN_THROW; + break; +@@ -3050,6 +3087,8 @@ static int ip6_route_dev_notify(struct n + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + net->ipv6.ip6_prohibit_entry->dst.dev = dev; + net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev); ++ net->ipv6.ip6_policy_failed_entry->dst.dev = dev; ++ net->ipv6.ip6_policy_failed_entry->rt6i_idev = in6_dev_get(dev); + net->ipv6.ip6_blk_hole_entry->dst.dev = dev; + net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev); + #endif +@@ -3266,6 +3305,17 @@ static int __net_init ip6_route_net_init + net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops; + dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst, + ip6_template_metrics, true); ++ ++ net->ipv6.ip6_policy_failed_entry = ++ kmemdup(&ip6_policy_failed_entry_template, ++ sizeof(*net->ipv6.ip6_policy_failed_entry), GFP_KERNEL); ++ if (!net->ipv6.ip6_policy_failed_entry) ++ goto out_ip6_blk_hole_entry; ++ net->ipv6.ip6_policy_failed_entry->dst.path = ++ (struct dst_entry *)net->ipv6.ip6_policy_failed_entry; ++ net->ipv6.ip6_policy_failed_entry->dst.ops = &net->ipv6.ip6_dst_ops; ++ dst_init_metrics(&net->ipv6.ip6_policy_failed_entry->dst, ++ ip6_template_metrics, true); + #endif + + net->ipv6.sysctl.flush_delay = 0; +@@ -3284,6 +3334,8 @@ out: + return ret; + + #ifdef CONFIG_IPV6_MULTIPLE_TABLES ++out_ip6_blk_hole_entry: ++ kfree(net->ipv6.ip6_blk_hole_entry); + out_ip6_prohibit_entry: + kfree(net->ipv6.ip6_prohibit_entry); + out_ip6_null_entry: +@@ -3301,6 +3353,7 @@ static void __net_exit ip6_route_net_exi + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + kfree(net->ipv6.ip6_prohibit_entry); + kfree(net->ipv6.ip6_blk_hole_entry); ++ kfree(net->ipv6.ip6_policy_failed_entry); + #endif + dst_entries_destroy(&net->ipv6.ip6_dst_ops); + } +@@ -3397,6 +3450,9 @@ int __init ip6_route_init(void) + init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); + init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev; + init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); ++ init_net.ipv6.ip6_policy_failed_entry->dst.dev = init_net.loopback_dev; ++ init_net.ipv6.ip6_policy_failed_entry->rt6i_idev = ++ in6_dev_get(init_net.loopback_dev); + #endif + ret = fib6_init(); + if (ret) diff --git a/target/linux/generic/patches-4.1/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch b/target/linux/generic/patches-4.1/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch new file mode 100644 index 0000000..dafb56c --- /dev/null +++ b/target/linux/generic/patches-4.1/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch @@ -0,0 +1,53 @@ +From 7749b481ce5d7e232b1f7da5e6b2c44816f51681 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 19 Jan 2014 20:45:51 +0100 +Subject: [PATCH 2/2] net: provide defines for _POLICY_FAILED until all code is + updated + +Upstream introduced ICMPV6_POLICY_FAIL for code 5 of destination +unreachable, conflicting with our name. + +Add appropriate defines to allow our code to build with the new +name until we have updated our local patches for older kernels +and userspace packages. + +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/fib_rules.h | 2 ++ + include/uapi/linux/icmpv6.h | 2 ++ + include/uapi/linux/rtnetlink.h | 2 ++ + 3 files changed, 6 insertions(+) + +--- a/include/uapi/linux/fib_rules.h ++++ b/include/uapi/linux/fib_rules.h +@@ -71,6 +71,8 @@ enum { + __FR_ACT_MAX, + }; + ++#define FR_ACT_FAILED_POLICY FR_ACT_POLICY_FAILED ++ + #define FR_ACT_MAX (__FR_ACT_MAX - 1) + + #endif +--- a/include/uapi/linux/icmpv6.h ++++ b/include/uapi/linux/icmpv6.h +@@ -118,6 +118,8 @@ struct icmp6hdr { + #define ICMPV6_POLICY_FAIL 5 + #define ICMPV6_REJECT_ROUTE 6 + ++#define ICMPV6_FAILED_POLICY ICMPV6_POLICY_FAIL ++ + /* + * Codes for Time Exceeded + */ +--- a/include/uapi/linux/rtnetlink.h ++++ b/include/uapi/linux/rtnetlink.h +@@ -214,6 +214,8 @@ enum { + __RTN_MAX + }; + ++#define RTN_FAILED_POLICY RTN_POLICY_FAILED ++ + #define RTN_MAX (__RTN_MAX - 1) + + diff --git a/target/linux/generic/patches-4.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/patches-4.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch new file mode 100644 index 0000000..fb6a355 --- /dev/null +++ b/target/linux/generic/patches-4.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch @@ -0,0 +1,160 @@ +Subject: NET: skip GRO for foreign MAC addresses + +For network drivers using napi_gro_receive, packets are run through GRO, +even when the destination MAC address does not match, and they're supposed +to be delivered to another host behind a different bridge port. + +This can be very expensive, because for drivers without TSO or scatter- +gather, this can only be undone by copying the skb and checksumming it +again. + +To be able to track foreign MAC addresses in an inexpensive way, create +a mask of changed bits in MAC addresses of upper devices. This allows +handling VLANs and bridge devices with different addresses (as long as +they are not too different). + +Signed-off-by: Felix Fietkau + +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -4036,6 +4036,9 @@ static enum gro_result dev_gro_receive(s + enum gro_result ret; + int grow; + ++ if (skb->gro_skip) ++ goto normal; ++ + if (!(skb->dev->features & NETIF_F_GRO)) + goto normal; + +@@ -5185,6 +5188,48 @@ static void __netdev_adjacent_dev_unlink + &upper_dev->adj_list.lower); + } + ++static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr, ++ struct net_device *dev) ++{ ++ int i; ++ ++ for (i = 0; i < dev->addr_len; i++) ++ mask[i] |= addr[i] ^ dev->dev_addr[i]; ++} ++ ++static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev, ++ struct net_device *lower) ++{ ++ struct net_device *cur; ++ struct list_head *iter; ++ ++ netdev_for_each_upper_dev_rcu(dev, cur, iter) { ++ __netdev_addr_mask(mask, cur->dev_addr, lower); ++ __netdev_upper_mask(mask, cur, lower); ++ } ++} ++ ++static void __netdev_update_addr_mask(struct net_device *dev) ++{ ++ unsigned char mask[MAX_ADDR_LEN]; ++ struct net_device *cur; ++ struct list_head *iter; ++ ++ memset(mask, 0, sizeof(mask)); ++ __netdev_upper_mask(mask, dev, dev); ++ memcpy(dev->local_addr_mask, mask, dev->addr_len); ++ ++ netdev_for_each_lower_dev(dev, cur, iter) ++ __netdev_update_addr_mask(cur); ++} ++ ++static void netdev_update_addr_mask(struct net_device *dev) ++{ ++ rcu_read_lock(); ++ __netdev_update_addr_mask(dev); ++ rcu_read_unlock(); ++} ++ + static int __netdev_upper_dev_link(struct net_device *dev, + struct net_device *upper_dev, bool master, + void *private) +@@ -5245,6 +5290,7 @@ static int __netdev_upper_dev_link(struc + goto rollback_lower_mesh; + } + ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEUPPER, dev); + return 0; + +@@ -5362,6 +5408,7 @@ void netdev_upper_dev_unlink(struct net_ + list_for_each_entry(i, &upper_dev->all_adj_list.upper, list) + __netdev_adjacent_dev_unlink(dev, i->dev); + ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEUPPER, dev); + } + EXPORT_SYMBOL(netdev_upper_dev_unlink); +@@ -5901,6 +5948,7 @@ int dev_set_mac_address(struct net_devic + if (err) + return err; + dev->addr_assign_type = NET_ADDR_SET; ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEADDR, dev); + add_device_randomness(dev->dev_addr, dev->addr_len); + return 0; +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1602,6 +1602,8 @@ struct net_device { + struct netdev_hw_addr_list mc; + struct netdev_hw_addr_list dev_addrs; + ++ unsigned char local_addr_mask[MAX_ADDR_LEN]; ++ + #ifdef CONFIG_SYSFS + struct kset *queues_kset; + #endif +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -615,7 +615,8 @@ struct sk_buff { + __u8 ipvs_property:1; + __u8 inner_protocol_type:1; + __u8 remcsum_offload:1; +- /* 3 or 5 bit hole */ ++ __u8 gro_skip:1; ++ /* 2 or 4 bit hole */ + + #ifdef CONFIG_NET_SCHED + __u16 tc_index; /* traffic control index */ +--- a/net/ethernet/eth.c ++++ b/net/ethernet/eth.c +@@ -139,6 +139,18 @@ u32 eth_get_headlen(void *data, unsigned + } + EXPORT_SYMBOL(eth_get_headlen); + ++static inline bool ++eth_check_local_mask(const void *addr1, const void *addr2, const void *mask) ++{ ++ const u16 *a1 = addr1; ++ const u16 *a2 = addr2; ++ const u16 *m = mask; ++ ++ return (((a1[0] ^ a2[0]) & ~m[0]) | ++ ((a1[1] ^ a2[1]) & ~m[1]) | ++ ((a1[2] ^ a2[2]) & ~m[2])); ++} ++ + /** + * eth_type_trans - determine the packet's protocol ID. + * @skb: received socket data +@@ -166,8 +178,12 @@ __be16 eth_type_trans(struct sk_buff *sk + skb->pkt_type = PACKET_MULTICAST; + } + else if (unlikely(!ether_addr_equal_64bits(eth->h_dest, +- dev->dev_addr))) ++ dev->dev_addr))) { + skb->pkt_type = PACKET_OTHERHOST; ++ if (eth_check_local_mask(eth->h_dest, dev->dev_addr, ++ dev->local_addr_mask)) ++ skb->gro_skip = 1; ++ } + + /* + * Some variants of DSA tagging don't have an ethertype field diff --git a/target/linux/generic/patches-4.1/681-NET-add-of_get_mac_address_mtd.patch b/target/linux/generic/patches-4.1/681-NET-add-of_get_mac_address_mtd.patch new file mode 100644 index 0000000..688cf6e --- /dev/null +++ b/target/linux/generic/patches-4.1/681-NET-add-of_get_mac_address_mtd.patch @@ -0,0 +1,88 @@ +From: John Crispin +Date: Sun, 27 Jul 2014 09:40:01 +0100 +Subject: NET: add of_get_mac_address_mtd() + +Many embedded devices have information such as mac addresses stored inside mtd +devices. This patch allows us to add a property inside a node describing a +network interface. The new property points at a mtd partition with an offset +where the mac address can be found. + +Signed-off-by: John Crispin +--- + drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++ + include/linux/of_net.h | 1 + + 2 files changed, 38 insertions(+) + +--- a/drivers/of/of_net.c ++++ b/drivers/of/of_net.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + /** + * of_get_phy_mode - Get phy mode for given device_node +@@ -80,3 +81,45 @@ const void *of_get_mac_address(struct de + return of_get_mac_addr(np, "address"); + } + EXPORT_SYMBOL(of_get_mac_address); ++ ++#ifdef CONFIG_MTD ++int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac) ++{ ++ struct device_node *mtd_np = NULL; ++ size_t retlen; ++ int size, ret; ++ struct mtd_info *mtd; ++ const char *part; ++ const __be32 *list; ++ phandle phandle; ++ u32 mac_inc = 0; ++ ++ list = of_get_property(np, "mtd-mac-address", &size); ++ if (!list || (size != (2 * sizeof(*list)))) ++ return -ENOENT; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return -ENOENT; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ mtd = get_mtd_device_nm(part); ++ if (IS_ERR(mtd)) ++ return PTR_ERR(mtd); ++ ++ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, mac); ++ put_mtd_device(mtd); ++ ++ if (!of_property_read_u32(np, "mtd-mac-address-increment", &mac_inc)) ++ mac[5] += mac_inc; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(of_get_mac_address_mtd); ++#endif +--- a/include/linux/of_net.h ++++ b/include/linux/of_net.h +@@ -13,6 +13,14 @@ + struct net_device; + extern int of_get_phy_mode(struct device_node *np); + extern const void *of_get_mac_address(struct device_node *np); ++#ifdef CONFIG_MTD ++extern int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac); ++#else ++static inline int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac) ++{ ++ return -ENOENT; ++} ++#endif + extern struct net_device *of_find_net_device_by_node(struct device_node *np); + #else + static inline int of_get_phy_mode(struct device_node *np) diff --git a/target/linux/generic/patches-4.1/700-swconfig.patch b/target/linux/generic/patches-4.1/700-swconfig.patch new file mode 100644 index 0000000..cdce89e --- /dev/null +++ b/target/linux/generic/patches-4.1/700-swconfig.patch @@ -0,0 +1,39 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -12,6 +12,16 @@ menuconfig PHYLIB + + if PHYLIB + ++config SWCONFIG ++ tristate "Switch configuration API" ++ ---help--- ++ Switch configuration API using netlink. This allows ++ you to configure the VLAN features of certain switches. ++ ++config SWCONFIG_LEDS ++ bool "Switch LED trigger support" ++ depends on (SWCONFIG && LEDS_TRIGGERS) ++ + comment "MII PHY device drivers" + + config AT803X_PHY +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -3,6 +3,7 @@ + libphy-objs := phy.o phy_device.o mdio_bus.o + + obj-$(CONFIG_PHYLIB) += libphy.o ++obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_DAVICOM_PHY) += davicom.o + obj-$(CONFIG_CICADA_PHY) += cicada.o +--- a/include/uapi/linux/Kbuild ++++ b/include/uapi/linux/Kbuild +@@ -380,6 +380,7 @@ header-y += stddef.h + header-y += string.h + header-y += suspend_ioctls.h + header-y += swab.h ++header-y += switch.h + header-y += synclink.h + header-y += sysctl.h + header-y += sysinfo.h diff --git a/target/linux/generic/patches-4.1/701-phy_extension.patch b/target/linux/generic/patches-4.1/701-phy_extension.patch new file mode 100644 index 0000000..55b37ba --- /dev/null +++ b/target/linux/generic/patches-4.1/701-phy_extension.patch @@ -0,0 +1,63 @@ +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -357,6 +357,50 @@ int phy_ethtool_gset(struct phy_device * + } + EXPORT_SYMBOL(phy_ethtool_gset); + ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) ++{ ++ u32 cmd; ++ int tmp; ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (get_user(cmd, (u32 *) useraddr)) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case ETHTOOL_GSET: ++ phy_ethtool_gset(phydev, &ecmd); ++ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) ++ return -EFAULT; ++ return 0; ++ ++ case ETHTOOL_SSET: ++ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) ++ return -EFAULT; ++ return phy_ethtool_sset(phydev, &ecmd); ++ ++ case ETHTOOL_NWAY_RST: ++ /* if autoneg is off, it's an error */ ++ tmp = phy_read(phydev, MII_BMCR); ++ if (tmp & BMCR_ANENABLE) { ++ tmp |= (BMCR_ANRESTART); ++ phy_write(phydev, MII_BMCR, tmp); ++ return 0; ++ } ++ return -EINVAL; ++ ++ case ETHTOOL_GLINK: ++ edata.data = (phy_read(phydev, ++ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++ } ++ ++ return -EOPNOTSUPP; ++} ++EXPORT_SYMBOL(phy_ethtool_ioctl); ++ + /** + * phy_mii_ioctl - generic PHY MII ioctl interface + * @phydev: the phy_device struct +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -762,6 +762,7 @@ void phy_start_machine(struct phy_device + void phy_stop_machine(struct phy_device *phydev); + int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); + int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); + int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd); + int phy_start_interrupts(struct phy_device *phydev); + void phy_print_status(struct phy_device *phydev); diff --git a/target/linux/generic/patches-4.1/702-phy_add_aneg_done_function.patch b/target/linux/generic/patches-4.1/702-phy_add_aneg_done_function.patch new file mode 100644 index 0000000..c743cef --- /dev/null +++ b/target/linux/generic/patches-4.1/702-phy_add_aneg_done_function.patch @@ -0,0 +1,27 @@ +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -489,6 +489,12 @@ struct phy_driver { + /* Determines the negotiated speed and duplex */ + int (*read_status)(struct phy_device *phydev); + ++ /* ++ * Update the value in phydev->link to reflect the ++ * current link value ++ */ ++ int (*update_link)(struct phy_device *phydev); ++ + /* Clears any pending interrupts */ + int (*ack_interrupt)(struct phy_device *phydev); + +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -929,6 +929,9 @@ int genphy_update_link(struct phy_device + { + int status; + ++ if (phydev->drv->update_link) ++ return phydev->drv->update_link(phydev); ++ + /* Do a fake read */ + status = phy_read(phydev, MII_BMSR); + if (status < 0) diff --git a/target/linux/generic/patches-4.1/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/patches-4.1/703-phy-add-detach-callback-to-struct-phy_driver.patch new file mode 100644 index 0000000..85888f7 --- /dev/null +++ b/target/linux/generic/patches-4.1/703-phy-add-detach-callback-to-struct-phy_driver.patch @@ -0,0 +1,27 @@ +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -674,6 +674,9 @@ void phy_detach(struct phy_device *phyde + { + int i; + ++ if (phydev->drv && phydev->drv->detach) ++ phydev->drv->detach(phydev); ++ + if (phydev->bus->dev.driver) + module_put(phydev->bus->dev.driver->owner); + +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -507,6 +507,12 @@ struct phy_driver { + */ + int (*did_interrupt)(struct phy_device *phydev); + ++ /* ++ * Called before an ethernet device is detached ++ * from the PHY. ++ */ ++ void (*detach)(struct phy_device *phydev); ++ + /* Clears up any memory if needed */ + void (*remove)(struct phy_device *phydev); + diff --git a/target/linux/generic/patches-4.1/704-phy-no-genphy-soft-reset.patch b/target/linux/generic/patches-4.1/704-phy-no-genphy-soft-reset.patch new file mode 100644 index 0000000..41a6d91 --- /dev/null +++ b/target/linux/generic/patches-4.1/704-phy-no-genphy-soft-reset.patch @@ -0,0 +1,29 @@ +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -1147,7 +1147,7 @@ int genphy_config_init(struct phy_device + return 0; + } + +-static int gen10g_soft_reset(struct phy_device *phydev) ++static int no_soft_reset(struct phy_device *phydev) + { + /* Do nothing for now */ + return 0; +@@ -1361,7 +1361,7 @@ static struct phy_driver genphy_driver[] + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic PHY", +- .soft_reset = genphy_soft_reset, ++ .soft_reset = no_soft_reset, + .config_init = genphy_config_init, + .features = PHY_GBIT_FEATURES | SUPPORTED_MII | + SUPPORTED_AUI | SUPPORTED_FIBRE | +@@ -1376,7 +1376,7 @@ static struct phy_driver genphy_driver[] + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic 10G PHY", +- .soft_reset = gen10g_soft_reset, ++ .soft_reset = no_soft_reset, + .config_init = gen10g_config_init, + .features = 0, + .config_aneg = gen10g_config_aneg, diff --git a/target/linux/generic/patches-4.1/710-phy-add-mdio_register_board_info.patch b/target/linux/generic/patches-4.1/710-phy-add-mdio_register_board_info.patch new file mode 100644 index 0000000..2bc91d5 --- /dev/null +++ b/target/linux/generic/patches-4.1/710-phy-add-mdio_register_board_info.patch @@ -0,0 +1,193 @@ +--- a/drivers/net/phy/mdio_bus.c ++++ b/drivers/net/phy/mdio_bus.c +@@ -38,6 +38,8 @@ + + #include + ++#include "mdio-boardinfo.h" ++ + /** + * mdiobus_alloc_size - allocate a mii_bus structure + * @size: extra amount of memory to allocate for private storage. +@@ -335,9 +337,21 @@ void mdiobus_free(struct mii_bus *bus) + } + EXPORT_SYMBOL(mdiobus_free); + ++static void mdiobus_setup_phydev_from_boardinfo(struct mii_bus *bus, ++ struct phy_device *phydev, ++ struct mdio_board_info *bi) ++{ ++ if (strcmp(bus->id, bi->bus_id) || ++ bi->phy_addr != phydev->addr) ++ return; ++ ++ phydev->dev.platform_data = (void *) bi->platform_data; ++} ++ + struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr) + { + struct phy_device *phydev; ++ struct mdio_board_entry *be; + int err; + + phydev = get_phy_device(bus, addr, false); +@@ -350,6 +364,12 @@ struct phy_device *mdiobus_scan(struct m + */ + of_mdiobus_link_phydev(bus, phydev); + ++ mutex_lock(&__mdio_board_lock); ++ list_for_each_entry(be, &__mdio_board_list, list) ++ mdiobus_setup_phydev_from_boardinfo(bus, phydev, ++ &be->board_info); ++ mutex_unlock(&__mdio_board_lock); ++ + err = phy_device_register(phydev); + if (err) { + phy_device_free(phydev); +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -800,6 +800,23 @@ void mdio_bus_exit(void); + + extern struct bus_type mdio_bus_type; + ++struct mdio_board_info { ++ const char *bus_id; ++ int phy_addr; ++ ++ const void *platform_data; ++}; ++ ++#ifdef CONFIG_MDIO_BOARDINFO ++int mdiobus_register_board_info(const struct mdio_board_info *info, unsigned n); ++#else ++static inline int ++mdiobus_register_board_info(const struct mdio_board_info *info, unsigned n) ++{ ++ return 0; ++} ++#endif ++ + /** + * module_phy_driver() - Helper macro for registering PHY drivers + * @__phy_drivers: array of PHY drivers to register +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -12,6 +12,10 @@ menuconfig PHYLIB + + if PHYLIB + ++config MDIO_BOARDINFO ++ bool ++ default y ++ + config SWCONFIG + tristate "Switch configuration API" + ---help--- +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -2,6 +2,8 @@ + + libphy-objs := phy.o phy_device.o mdio_bus.o + ++obj-$(CONFIG_MDIO_BOARDINFO) += mdio-boardinfo.o ++ + obj-$(CONFIG_PHYLIB) += libphy.o + obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_MARVELL_PHY) += marvell.o +--- /dev/null ++++ b/drivers/net/phy/mdio-boardinfo.c +@@ -0,0 +1,58 @@ ++/* ++ * mdio-boardinfo.c - collect pre-declarations of PHY devices ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdio-boardinfo.h" ++ ++/* ++ * These symbols are exported ONLY FOR the mdio_bus component. ++ * No other users will be supported. ++ */ ++ ++LIST_HEAD(__mdio_board_list); ++EXPORT_SYMBOL_GPL(__mdio_board_list); ++ ++DEFINE_MUTEX(__mdio_board_lock); ++EXPORT_SYMBOL_GPL(__mdio_board_lock); ++ ++/** ++ * mdio_register_board_info - register PHY devices for a given board ++ * @info: array of chip descriptors ++ * @n: how many descriptors are provided ++ * Context: can sleep ++ * ++ * The board info passed can safely be __initdata ... but be careful of ++ * any embedded pointers (platform_data, etc), they're copied as-is. ++ */ ++int __init ++mdiobus_register_board_info(struct mdio_board_info const *info, unsigned n) ++{ ++ struct mdio_board_entry *be; ++ int i; ++ ++ be = kzalloc(n * sizeof(*be), GFP_KERNEL); ++ if (!be) ++ return -ENOMEM; ++ ++ for (i = 0; i < n; i++, be++, info++) { ++ memcpy(&be->board_info, info, sizeof(*info)); ++ mutex_lock(&__mdio_board_lock); ++ list_add_tail(&be->list, &__mdio_board_list); ++ mutex_unlock(&__mdio_board_lock); ++ } ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/net/phy/mdio-boardinfo.h +@@ -0,0 +1,22 @@ ++/* ++ * mdio-boardinfo.h - boardinfo interface internal to the mdio_bus component ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++ ++struct mdio_board_entry { ++ struct list_head list; ++ struct mdio_board_info board_info; ++}; ++ ++/* __mdio_board_lock protects __mdio_board_list ++ * only mdio_bus components are allowed to use these symbols. ++ */ ++extern struct mutex __mdio_board_lock; ++extern struct list_head __mdio_board_list; +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -16,7 +16,7 @@ obj-$(CONFIG_MII) += mii.o + obj-$(CONFIG_MDIO) += mdio.o + obj-$(CONFIG_NET) += Space.o loopback.o + obj-$(CONFIG_NETCONSOLE) += netconsole.o +-obj-$(CONFIG_PHYLIB) += phy/ ++obj-y += phy/ + obj-$(CONFIG_RIONET) += rionet.o + obj-$(CONFIG_NET_TEAM) += team/ + obj-$(CONFIG_TUN) += tun.o diff --git a/target/linux/generic/patches-4.1/720-phy_adm6996.patch b/target/linux/generic/patches-4.1/720-phy_adm6996.patch new file mode 100644 index 0000000..7107316 --- /dev/null +++ b/target/linux/generic/patches-4.1/720-phy_adm6996.patch @@ -0,0 +1,26 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -133,6 +133,13 @@ config MICREL_PHY + ---help--- + Supports the KSZ9021, VSC8201, KS8001 PHYs. + ++config ADM6996_PHY ++ tristate "Driver for ADM6996 switches" ++ select SWCONFIG ++ ---help--- ++ Currently supports the ADM6996FC and ADM6996M switches. ++ Support for FC is very limited. ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -18,6 +18,7 @@ obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o + obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o ++obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.1/721-phy_packets.patch b/target/linux/generic/patches-4.1/721-phy_packets.patch new file mode 100644 index 0000000..a511c66 --- /dev/null +++ b/target/linux/generic/patches-4.1/721-phy_packets.patch @@ -0,0 +1,161 @@ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1270,6 +1270,7 @@ enum netdev_priv_flags { + IFF_XMIT_DST_RELEASE_PERM = 1<<22, + IFF_IPVLAN_MASTER = 1<<23, + IFF_IPVLAN_SLAVE = 1<<24, ++ IFF_NO_IP_ALIGN = 1<<25, + }; + + #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN +@@ -1297,6 +1298,7 @@ enum netdev_priv_flags { + #define IFF_XMIT_DST_RELEASE_PERM IFF_XMIT_DST_RELEASE_PERM + #define IFF_IPVLAN_MASTER IFF_IPVLAN_MASTER + #define IFF_IPVLAN_SLAVE IFF_IPVLAN_SLAVE ++#define IFF_NO_IP_ALIGN IFF_NO_IP_ALIGN + + /** + * struct net_device - The DEVICE structure. +@@ -1567,6 +1569,11 @@ struct net_device { + const struct swdev_ops *swdev_ops; + #endif + ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ void (*eth_mangle_rx)(struct net_device *dev, struct sk_buff *skb); ++ struct sk_buff *(*eth_mangle_tx)(struct net_device *dev, struct sk_buff *skb); ++#endif ++ + const struct header_ops *header_ops; + + unsigned int flags; +@@ -1633,6 +1640,10 @@ struct net_device { + struct mpls_dev __rcu *mpls_ptr; + #endif + ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ void *phy_ptr; /* PHY device specific data */ ++#endif ++ + /* + * Cache lines mostly used on receive path (including eth_type_trans()) + */ +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2058,6 +2058,10 @@ static inline int pskb_trim(struct sk_bu + return (len < skb->len) ? __pskb_trim(skb, len) : 0; + } + ++extern struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, ++ unsigned int length, gfp_t gfp); ++ ++ + /** + * pskb_trim_unique - remove end from a paged unique (not cloned) buffer + * @skb: buffer to alter +@@ -2184,16 +2188,6 @@ static inline struct sk_buff *dev_alloc_ + } + + +-static inline struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, +- unsigned int length, gfp_t gfp) +-{ +- struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); +- +- if (NET_IP_ALIGN && skb) +- skb_reserve(skb, NET_IP_ALIGN); +- return skb; +-} +- + static inline struct sk_buff *netdev_alloc_skb_ip_align(struct net_device *dev, + unsigned int length) + { +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -25,6 +25,12 @@ menuconfig NET + + if NET + ++config ETHERNET_PACKET_MANGLE ++ bool ++ help ++ This option can be selected by phy drivers that need to mangle ++ packets going in or out of an ethernet device. ++ + config WANT_COMPAT_NETLINK_MESSAGES + bool + help +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -2645,10 +2645,20 @@ static int xmit_one(struct sk_buff *skb, + if (!list_empty(&ptype_all) || !list_empty(&dev->ptype_all)) + dev_queue_xmit_nit(skb, dev); + +- len = skb->len; +- trace_net_dev_start_xmit(skb, dev); +- rc = netdev_start_xmit(skb, dev, txq, more); +- trace_net_dev_xmit(skb, rc, dev, len); ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (!dev->eth_mangle_tx || ++ (skb = dev->eth_mangle_tx(dev, skb)) != NULL) ++#else ++ if (1) ++#endif ++ { ++ len = skb->len; ++ trace_net_dev_start_xmit(skb, dev); ++ rc = netdev_start_xmit(skb, dev, txq, more); ++ trace_net_dev_xmit(skb, rc, dev, len); ++ } else { ++ rc = NETDEV_TX_OK; ++ } + + return rc; + } +--- a/net/core/skbuff.c ++++ b/net/core/skbuff.c +@@ -63,6 +63,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -568,6 +569,22 @@ struct sk_buff *__napi_alloc_skb(struct + } + EXPORT_SYMBOL(__napi_alloc_skb); + ++struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, ++ unsigned int length, gfp_t gfp) ++{ ++ struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); ++ ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (dev && (dev->priv_flags & IFF_NO_IP_ALIGN)) ++ return skb; ++#endif ++ ++ if (NET_IP_ALIGN && skb) ++ skb_reserve(skb, NET_IP_ALIGN); ++ return skb; ++} ++EXPORT_SYMBOL(__netdev_alloc_skb_ip_align); ++ + void skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page, int off, + int size, unsigned int truesize) + { +--- a/net/ethernet/eth.c ++++ b/net/ethernet/eth.c +@@ -167,6 +167,12 @@ __be16 eth_type_trans(struct sk_buff *sk + const struct ethhdr *eth; + + skb->dev = dev; ++ ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (dev->eth_mangle_rx) ++ dev->eth_mangle_rx(dev, skb); ++#endif ++ + skb_reset_mac_header(skb); + skb_pull_inline(skb, ETH_HLEN); + eth = eth_hdr(skb); diff --git a/target/linux/generic/patches-4.1/722-phy_mvswitch.patch b/target/linux/generic/patches-4.1/722-phy_mvswitch.patch new file mode 100644 index 0000000..209c500 --- /dev/null +++ b/target/linux/generic/patches-4.1/722-phy_mvswitch.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -140,6 +140,10 @@ config ADM6996_PHY + Currently supports the ADM6996FC and ADM6996M switches. + Support for FC is very limited. + ++config MVSWITCH_PHY ++ tristate "Driver for Marvell 88E6060 switches" ++ select ETHERNET_PACKET_MANGLE ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o ++obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.1/723-phy_ip175c.patch b/target/linux/generic/patches-4.1/723-phy_ip175c.patch new file mode 100644 index 0000000..2293ca5 --- /dev/null +++ b/target/linux/generic/patches-4.1/723-phy_ip175c.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -144,6 +144,10 @@ config MVSWITCH_PHY + tristate "Driver for Marvell 88E6060 switches" + select ETHERNET_PACKET_MANGLE + ++config IP17XX_PHY ++ tristate "Driver for IC+ IP17xx switches" ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o ++obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.1/724-phy_ar8216.patch b/target/linux/generic/patches-4.1/724-phy_ar8216.patch new file mode 100644 index 0000000..3a669ba --- /dev/null +++ b/target/linux/generic/patches-4.1/724-phy_ar8216.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -148,6 +148,11 @@ config IP17XX_PHY + tristate "Driver for IC+ IP17xx switches" + select SWCONFIG + ++config AR8216_PHY ++ tristate "Driver for Atheros AR8216 switches" ++ select ETHERNET_PACKET_MANGLE ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o ++obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.1/725-phy_rtl8306.patch b/target/linux/generic/patches-4.1/725-phy_rtl8306.patch new file mode 100644 index 0000000..5d4ce7c --- /dev/null +++ b/target/linux/generic/patches-4.1/725-phy_rtl8306.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -153,6 +153,10 @@ config AR8216_PHY + select ETHERNET_PACKET_MANGLE + select SWCONFIG + ++config RTL8306_PHY ++ tristate "Driver for Realtek RTL8306S switches" ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -23,6 +23,7 @@ obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o ++obj-$(CONFIG_RTL8306_PHY) += rtl8306.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.1/726-phy_rtl8366.patch b/target/linux/generic/patches-4.1/726-phy_rtl8366.patch new file mode 100644 index 0000000..83c7c4e --- /dev/null +++ b/target/linux/generic/patches-4.1/726-phy_rtl8366.patch @@ -0,0 +1,45 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -251,6 +251,30 @@ config MDIO_BCM_UNIMAC + controllers as well as some Broadcom Ethernet switches such as the + Starfighter 2 switches. + ++config RTL8366_SMI ++ tristate "Driver for the RTL8366 SMI interface" ++ depends on GPIOLIB ++ ---help--- ++ This module implements the SMI interface protocol which is used ++ by some RTL8366 ethernet switch devices via the generic GPIO API. ++ ++if RTL8366_SMI ++ ++config RTL8366_SMI_DEBUG_FS ++ bool "RTL8366 SMI interface debugfs support" ++ depends on DEBUG_FS ++ default n ++ ++config RTL8366S_PHY ++ tristate "Driver for the Realtek RTL8366S switch" ++ select SWCONFIG ++ ++config RTL8366RB_PHY ++ tristate "Driver for the Realtek RTL8366RB switch" ++ select SWCONFIG ++ ++endif # RTL8366_SMI ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -24,6 +24,9 @@ obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o + obj-$(CONFIG_RTL8306_PHY) += rtl8306.o ++obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o ++obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o ++obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.1/727-phy-rtl8367.patch b/target/linux/generic/patches-4.1/727-phy-rtl8367.patch new file mode 100644 index 0000000..7e6b035 --- /dev/null +++ b/target/linux/generic/patches-4.1/727-phy-rtl8367.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -273,6 +273,10 @@ config RTL8366RB_PHY + tristate "Driver for the Realtek RTL8366RB switch" + select SWCONFIG + ++config RTL8367_PHY ++ tristate "Driver for the Realtek RTL8367R/M switches" ++ select SWCONFIG ++ + endif # RTL8366_SMI + + endif # PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_RTL8306_PHY) += rtl8306.o + obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o + obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o + obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o ++obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.1/728-phy-rtl8367b.patch b/target/linux/generic/patches-4.1/728-phy-rtl8367b.patch new file mode 100644 index 0000000..670168e --- /dev/null +++ b/target/linux/generic/patches-4.1/728-phy-rtl8367b.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -277,6 +277,10 @@ config RTL8367_PHY + tristate "Driver for the Realtek RTL8367R/M switches" + select SWCONFIG + ++config RTL8367B_PHY ++ tristate "Driver fot the Realtek RTL8367R-VB switch" ++ select SWCONFIG ++ + endif # RTL8366_SMI + + endif # PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -28,6 +28,7 @@ obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi + obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o + obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o ++obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.1/729-phy-tantos.patch b/target/linux/generic/patches-4.1/729-phy-tantos.patch new file mode 100644 index 0000000..67b879f --- /dev/null +++ b/target/linux/generic/patches-4.1/729-phy-tantos.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -288,3 +288,8 @@ endif # PHYLIB + config MICREL_KS8995MA + tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch" + depends on SPI ++ ++config PSB6970_PHY ++ tristate "Lantiq XWAY Tantos (PSB6970) Ethernet switch" ++ select SWCONFIG ++ select ETHERNET_PACKET_MANGLE +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -30,6 +30,7 @@ obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o ++obj-$(CONFIG_PSB6970_PHY) += psb6970.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/generic/patches-4.1/730-phy_b53.patch b/target/linux/generic/patches-4.1/730-phy_b53.patch new file mode 100644 index 0000000..bdcfba6 --- /dev/null +++ b/target/linux/generic/patches-4.1/730-phy_b53.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -283,6 +283,8 @@ config RTL8367B_PHY + + endif # RTL8366_SMI + ++source "drivers/net/phy/b53/Kconfig" ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -31,6 +31,7 @@ obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_PSB6970_PHY) += psb6970.o ++obj-$(CONFIG_B53) += b53/ + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/generic/patches-4.1/731-phy_mvswitch_3.10_compilation.patch b/target/linux/generic/patches-4.1/731-phy_mvswitch_3.10_compilation.patch new file mode 100644 index 0000000..2053bd2 --- /dev/null +++ b/target/linux/generic/patches-4.1/731-phy_mvswitch_3.10_compilation.patch @@ -0,0 +1,35 @@ +From e6a5abb9a02be0bceb4782d9f736bfb4ae217505 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Sep 2013 13:56:51 +0200 +Subject: [PATCH] phy: mvswitch: fix 3.10 compilation + +Update to API changes in 3.10. + +Signed-off-by: Jonas Gorsi +--- + target/linux/generic/files/drivers/net/phy/mvswitch.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mvswitch.c ++++ b/drivers/net/phy/mvswitch.c +@@ -173,7 +173,7 @@ mvswitch_mangle_rx(struct net_device *de + if (vlan == -1) + return; + +- __vlan_hwaccel_put_tag(skb, vlan); ++ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan); + } + + +@@ -307,9 +307,9 @@ mvswitch_config_init(struct phy_device * + + #ifdef HEADER_MODE + dev->priv_flags |= IFF_NO_IP_ALIGN; +- dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; + #else +- dev->features |= NETIF_F_HW_VLAN_RX; ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX; + #endif + + return 0; diff --git a/target/linux/generic/patches-4.1/732-phy-ar8216-led-support.patch b/target/linux/generic/patches-4.1/732-phy-ar8216-led-support.patch new file mode 100644 index 0000000..e38cf78 --- /dev/null +++ b/target/linux/generic/patches-4.1/732-phy-ar8216-led-support.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -153,6 +153,10 @@ config AR8216_PHY + select ETHERNET_PACKET_MANGLE + select SWCONFIG + ++config AR8216_PHY_LEDS ++ bool "Atheros AR8216 switch LED support" ++ depends on (AR8216_PHY && LEDS_CLASS) ++ + config RTL8306_PHY + tristate "Driver for Realtek RTL8306S switches" + select SWCONFIG diff --git a/target/linux/generic/patches-4.1/733-phy_mvsw61xx.patch b/target/linux/generic/patches-4.1/733-phy_mvsw61xx.patch new file mode 100644 index 0000000..b70326b --- /dev/null +++ b/target/linux/generic/patches-4.1/733-phy_mvsw61xx.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -144,6 +144,10 @@ config MVSWITCH_PHY + tristate "Driver for Marvell 88E6060 switches" + select ETHERNET_PACKET_MANGLE + ++config MVSW61XX_PHY ++ tristate "Driver for Marvell 88E6171/6172 switches" ++ select SWCONFIG ++ + config IP17XX_PHY + tristate "Driver for IC+ IP17xx switches" + select SWCONFIG +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o ++obj-$(CONFIG_MVSW61XX_PHY) += mvsw61xx.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o diff --git a/target/linux/generic/patches-4.1/750-hostap_txpower.patch b/target/linux/generic/patches-4.1/750-hostap_txpower.patch new file mode 100644 index 0000000..768c80f --- /dev/null +++ b/target/linux/generic/patches-4.1/750-hostap_txpower.patch @@ -0,0 +1,154 @@ +--- a/drivers/net/wireless/hostap/hostap_ap.c ++++ b/drivers/net/wireless/hostap/hostap_ap.c +@@ -2403,13 +2403,13 @@ int prism2_ap_get_sta_qual(local_info_t + addr[count].sa_family = ARPHRD_ETHER; + memcpy(addr[count].sa_data, sta->addr, ETH_ALEN); + if (sta->last_rx_silence == 0) +- qual[count].qual = sta->last_rx_signal < 27 ? +- 0 : (sta->last_rx_signal - 27) * 92 / 127; ++ qual[count].qual = (sta->last_rx_signal - 156) == 0 ? ++ 0 : (sta->last_rx_signal - 156) * 92 / 64; + else +- qual[count].qual = sta->last_rx_signal - +- sta->last_rx_silence - 35; +- qual[count].level = HFA384X_LEVEL_TO_dBm(sta->last_rx_signal); +- qual[count].noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); ++ qual[count].qual = (sta->last_rx_signal - ++ sta->last_rx_silence) * 92 / 64; ++ qual[count].level = sta->last_rx_signal; ++ qual[count].noise = sta->last_rx_silence; + qual[count].updated = sta->last_rx_updated; + + sta->last_rx_updated = IW_QUAL_DBM; +@@ -2475,13 +2475,13 @@ int prism2_ap_translate_scan(struct net_ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + if (sta->last_rx_silence == 0) +- iwe.u.qual.qual = sta->last_rx_signal < 27 ? +- 0 : (sta->last_rx_signal - 27) * 92 / 127; ++ iwe.u.qual.qual = (sta->last_rx_signal -156) == 0 ? ++ 0 : (sta->last_rx_signal - 156) * 92 / 64; + else +- iwe.u.qual.qual = sta->last_rx_signal - +- sta->last_rx_silence - 35; +- iwe.u.qual.level = HFA384X_LEVEL_TO_dBm(sta->last_rx_signal); +- iwe.u.qual.noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); ++ iwe.u.qual.qual = (sta->last_rx_signal - ++ sta->last_rx_silence) * 92 / 64; ++ iwe.u.qual.level = sta->last_rx_signal; ++ iwe.u.qual.noise = sta->last_rx_silence; + iwe.u.qual.updated = sta->last_rx_updated; + iwe.len = IW_EV_QUAL_LEN; + current_ev = iwe_stream_add_event(info, current_ev, end_buf, +--- a/drivers/net/wireless/hostap/hostap_config.h ++++ b/drivers/net/wireless/hostap/hostap_config.h +@@ -45,4 +45,9 @@ + */ + /* #define PRISM2_NO_STATION_MODES */ + ++/* Enable TX power Setting functions ++ * (min att = -128 , max att = 127) ++ */ ++#define RAW_TXPOWER_SETTING ++ + #endif /* HOSTAP_CONFIG_H */ +--- a/drivers/net/wireless/hostap/hostap.h ++++ b/drivers/net/wireless/hostap/hostap.h +@@ -90,6 +90,7 @@ extern const struct iw_handler_def hosta + extern const struct ethtool_ops prism2_ethtool_ops; + + int hostap_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); ++int hostap_restore_power(struct net_device *dev); + + + #endif /* HOSTAP_H */ +--- a/drivers/net/wireless/hostap/hostap_hw.c ++++ b/drivers/net/wireless/hostap/hostap_hw.c +@@ -928,6 +928,7 @@ static int hfa384x_set_rid(struct net_de + prism2_hw_reset(dev); + } + ++ hostap_restore_power(dev); + return res; + } + +--- a/drivers/net/wireless/hostap/hostap_info.c ++++ b/drivers/net/wireless/hostap/hostap_info.c +@@ -435,6 +435,11 @@ static void handle_info_queue_linkstatus + } + + /* Get BSSID if we have a valid AP address */ ++ ++ if ( val == HFA384X_LINKSTATUS_CONNECTED || ++ val == HFA384X_LINKSTATUS_DISCONNECTED ) ++ hostap_restore_power(local->dev); ++ + if (connected) { + netif_carrier_on(local->dev); + netif_carrier_on(local->ddev); +--- a/drivers/net/wireless/hostap/hostap_ioctl.c ++++ b/drivers/net/wireless/hostap/hostap_ioctl.c +@@ -1479,23 +1479,20 @@ static int prism2_txpower_hfa386x_to_dBm + val = 255; + + tmp = val; +- tmp >>= 2; + +- return -12 - tmp; ++ return tmp; + } + + static u16 prism2_txpower_dBm_to_hfa386x(int val) + { + signed char tmp; + +- if (val > 20) +- return 128; +- else if (val < -43) ++ if (val > 127) + return 127; ++ else if (val < -128) ++ return 128; + + tmp = val; +- tmp = -12 - tmp; +- tmp <<= 2; + + return (unsigned char) tmp; + } +@@ -4052,3 +4049,35 @@ int hostap_ioctl(struct net_device *dev, + + return ret; + } ++ ++/* BUG FIX: Restore power setting value when lost due to F/W bug */ ++ ++int hostap_restore_power(struct net_device *dev) ++{ ++ struct hostap_interface *iface = netdev_priv(dev); ++ local_info_t *local = iface->local; ++ ++ u16 val; ++ int ret = 0; ++ ++ if (local->txpower_type == PRISM2_TXPOWER_OFF) { ++ val = 0xff; /* use all standby and sleep modes */ ++ ret = local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, ++ HFA386X_CR_A_D_TEST_MODES2, ++ &val, NULL); ++ } ++ ++#ifdef RAW_TXPOWER_SETTING ++ if (local->txpower_type == PRISM2_TXPOWER_FIXED) { ++ val = HFA384X_TEST_CFG_BIT_ALC; ++ local->func->cmd(dev, HFA384X_CMDCODE_TEST | ++ (HFA384X_TEST_CFG_BITS << 8), 0, &val, NULL); ++ val = prism2_txpower_dBm_to_hfa386x(local->txpower); ++ ret = (local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, ++ HFA386X_CR_MANUAL_TX_POWER, &val, NULL)); ++ } ++#endif /* RAW_TXPOWER_SETTING */ ++ return (ret ? -EOPNOTSUPP : 0); ++} ++ ++EXPORT_SYMBOL(hostap_restore_power); diff --git a/target/linux/generic/patches-4.1/760-8139cp-fixes-from-4.3.patch b/target/linux/generic/patches-4.1/760-8139cp-fixes-from-4.3.patch new file mode 100644 index 0000000..832e425 --- /dev/null +++ b/target/linux/generic/patches-4.1/760-8139cp-fixes-from-4.3.patch @@ -0,0 +1,365 @@ +commit 41b976414c88016e2c9d9b2f6667ee67a998d388 +Author: David Woodhouse +Date: Wed Sep 23 09:45:31 2015 +0100 + + 8139cp: Dump contents of descriptor ring on TX timeout + + We are seeing unexplained TX timeouts under heavy load. Let's try to get + a better idea of what's going on. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 7f4c685633e2df9ba10d49a31dda13715745db37 +Author: David Woodhouse +Date: Wed Sep 23 09:45:16 2015 +0100 + + 8139cp: Fix DMA unmapping of transmitted buffers + + The low 16 bits of the 'opts1' field in the TX descriptor are supposed + to still contain the buffer length when the descriptor is handed back to + us. In practice, at least on my hardware, they don't. So stash the + original value of the opts1 field and get the length to unmap from + there. + + There are other ways we could have worked out the length, but I actually + want a stash of the opts1 field anyway so that I can dump it alongside + the contents of the descriptor ring when we suffer a TX timeout. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 0a5aeee0b79fa99d8e04c98dd4e87d4f52aa497b +Author: David Woodhouse +Date: Wed Sep 23 09:44:57 2015 +0100 + + 8139cp: Reduce duplicate csum/tso code in cp_start_xmit() + + We calculate the value of the opts1 descriptor field in three different + places. With two different behaviours when given an invalid packet to + be checksummed — none of them correct. Sort that out. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit a3b804043f490aeec57d8ca5baccdd35e6250857 +Author: David Woodhouse +Date: Wed Sep 23 09:44:38 2015 +0100 + + 8139cp: Fix TSO/scatter-gather descriptor setup + + When sending a TSO frame in multiple buffers, we were neglecting to set + the first descriptor up in TSO mode. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 26b0bad6ac3a0167792dc4ffb276c29bc597d239 +Author: David Woodhouse +Date: Wed Sep 23 09:44:06 2015 +0100 + + 8139cp: Fix tx_queued debug message to print correct slot numbers + + After a certain amount of staring at the debug output of this driver, I + realised it was lying to me. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit aaa0062ecf4877a26dea66bee1039c6eaf906c94 +Author: David Woodhouse +Date: Wed Sep 23 09:43:41 2015 +0100 + + 8139cp: Do not re-enable RX interrupts in cp_tx_timeout() + + If an RX interrupt was already received but NAPI has not yet run when + the RX timeout happens, we end up in cp_tx_timeout() with RX interrupts + already disabled. Blindly re-enabling them will cause an IRQ storm. + + (This is made particularly horrid by the fact that cp_interrupt() always + returns that it's handled the interrupt, even when it hasn't actually + done anything. If it didn't do that, the core IRQ code would have + detected the storm and handled it, I'd have had a clear smoking gun + backtrace instead of just a spontaneously resetting router, and I'd have + at *least* two days of my life back. Changing the return value of + cp_interrupt() will be argued about under separate cover.) + + Unconditionally leave RX interrupts disabled after the reset, and + schedule NAPI to check the receive ring and re-enable them. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 7a8a8e75d505147358b225173e890ada43a267e2 +Author: David Woodhouse +Date: Fri Sep 18 00:21:54 2015 +0100 + + 8139cp: Call __cp_set_rx_mode() from cp_tx_timeout() + + Unless we reset the RX config, on real hardware I don't seem to receive + any packets after a TX timeout. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit fc27bd115b334e3ebdc682a42a47c3aea2566dcc +Author: David Woodhouse +Date: Fri Sep 18 00:19:08 2015 +0100 + + 8139cp: Use dev_kfree_skb_any() instead of dev_kfree_skb() in cp_clean_rings() + + This can be called from cp_tx_timeout() with interrupts disabled. + Spotted by Francois Romieu + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller +--- a/drivers/net/ethernet/realtek/8139cp.c ++++ b/drivers/net/ethernet/realtek/8139cp.c +@@ -157,6 +157,7 @@ enum { + NWayAdvert = 0x66, /* MII ADVERTISE */ + NWayLPAR = 0x68, /* MII LPA */ + NWayExpansion = 0x6A, /* MII Expansion */ ++ TxDmaOkLowDesc = 0x82, /* Low 16 bit address of a Tx descriptor. */ + Config5 = 0xD8, /* Config5 */ + TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ + RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ +@@ -341,6 +342,7 @@ struct cp_private { + unsigned tx_tail; + struct cp_desc *tx_ring; + struct sk_buff *tx_skb[CP_TX_RING_SIZE]; ++ u32 tx_opts[CP_TX_RING_SIZE]; + + unsigned rx_buf_sz; + unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */ +@@ -665,7 +667,7 @@ static void cp_tx (struct cp_private *cp + BUG_ON(!skb); + + dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr), +- le32_to_cpu(txd->opts1) & 0xffff, ++ cp->tx_opts[tx_tail] & 0xffff, + PCI_DMA_TODEVICE); + + if (status & LastFrag) { +@@ -733,7 +735,7 @@ static netdev_tx_t cp_start_xmit (struct + { + struct cp_private *cp = netdev_priv(dev); + unsigned entry; +- u32 eor, flags; ++ u32 eor, opts1; + unsigned long intr_flags; + __le32 opts2; + int mss = 0; +@@ -753,6 +755,21 @@ static netdev_tx_t cp_start_xmit (struct + mss = skb_shinfo(skb)->gso_size; + + opts2 = cpu_to_le32(cp_tx_vlan_tag(skb)); ++ opts1 = DescOwn; ++ if (mss) ++ opts1 |= LargeSend | ((mss & MSSMask) << MSSShift); ++ else if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ const struct iphdr *ip = ip_hdr(skb); ++ if (ip->protocol == IPPROTO_TCP) ++ opts1 |= IPCS | TCPCS; ++ else if (ip->protocol == IPPROTO_UDP) ++ opts1 |= IPCS | UDPCS; ++ else { ++ WARN_ONCE(1, ++ "Net bug: asked to checksum invalid Legacy IP packet\n"); ++ goto out_dma_error; ++ } ++ } + + if (skb_shinfo(skb)->nr_frags == 0) { + struct cp_desc *txd = &cp->tx_ring[entry]; +@@ -768,31 +785,20 @@ static netdev_tx_t cp_start_xmit (struct + txd->addr = cpu_to_le64(mapping); + wmb(); + +- flags = eor | len | DescOwn | FirstFrag | LastFrag; +- +- if (mss) +- flags |= LargeSend | ((mss & MSSMask) << MSSShift); +- else if (skb->ip_summed == CHECKSUM_PARTIAL) { +- const struct iphdr *ip = ip_hdr(skb); +- if (ip->protocol == IPPROTO_TCP) +- flags |= IPCS | TCPCS; +- else if (ip->protocol == IPPROTO_UDP) +- flags |= IPCS | UDPCS; +- else +- WARN_ON(1); /* we need a WARN() */ +- } ++ opts1 |= eor | len | FirstFrag | LastFrag; + +- txd->opts1 = cpu_to_le32(flags); ++ txd->opts1 = cpu_to_le32(opts1); + wmb(); + + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); ++ cp->tx_opts[entry] = opts1; ++ netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n", ++ entry, skb->len); + } else { + struct cp_desc *txd; +- u32 first_len, first_eor; ++ u32 first_len, first_eor, ctrl; + dma_addr_t first_mapping; + int frag, first_entry = entry; +- const struct iphdr *ip = ip_hdr(skb); + + /* We must give this initial chunk to the device last. + * Otherwise we could race with the device. +@@ -805,14 +811,14 @@ static netdev_tx_t cp_start_xmit (struct + goto out_dma_error; + + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); + + for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { + const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; + u32 len; +- u32 ctrl; + dma_addr_t mapping; + ++ entry = NEXT_TX(entry); ++ + len = skb_frag_size(this_frag); + mapping = dma_map_single(&cp->pdev->dev, + skb_frag_address(this_frag), +@@ -824,19 +830,7 @@ static netdev_tx_t cp_start_xmit (struct + + eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; + +- ctrl = eor | len | DescOwn; +- +- if (mss) +- ctrl |= LargeSend | +- ((mss & MSSMask) << MSSShift); +- else if (skb->ip_summed == CHECKSUM_PARTIAL) { +- if (ip->protocol == IPPROTO_TCP) +- ctrl |= IPCS | TCPCS; +- else if (ip->protocol == IPPROTO_UDP) +- ctrl |= IPCS | UDPCS; +- else +- BUG(); +- } ++ ctrl = opts1 | eor | len; + + if (frag == skb_shinfo(skb)->nr_frags - 1) + ctrl |= LastFrag; +@@ -849,8 +843,8 @@ static netdev_tx_t cp_start_xmit (struct + txd->opts1 = cpu_to_le32(ctrl); + wmb(); + ++ cp->tx_opts[entry] = ctrl; + cp->tx_skb[entry] = skb; +- entry = NEXT_TX(entry); + } + + txd = &cp->tx_ring[first_entry]; +@@ -858,27 +852,17 @@ static netdev_tx_t cp_start_xmit (struct + txd->addr = cpu_to_le64(first_mapping); + wmb(); + +- if (skb->ip_summed == CHECKSUM_PARTIAL) { +- if (ip->protocol == IPPROTO_TCP) +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn | +- IPCS | TCPCS); +- else if (ip->protocol == IPPROTO_UDP) +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn | +- IPCS | UDPCS); +- else +- BUG(); +- } else +- txd->opts1 = cpu_to_le32(first_eor | first_len | +- FirstFrag | DescOwn); ++ ctrl = opts1 | first_eor | first_len | FirstFrag; ++ txd->opts1 = cpu_to_le32(ctrl); + wmb(); ++ ++ cp->tx_opts[first_entry] = ctrl; ++ netif_dbg(cp, tx_queued, cp->dev, "tx queued, slots %d-%d, skblen %d\n", ++ first_entry, entry, skb->len); + } +- cp->tx_head = entry; ++ cp->tx_head = NEXT_TX(entry); + + netdev_sent_queue(dev, skb->len); +- netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n", +- entry, skb->len); + if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1)) + netif_stop_queue(dev); + +@@ -1115,6 +1099,7 @@ static int cp_init_rings (struct cp_priv + { + memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); + cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd); ++ memset(cp->tx_opts, 0, sizeof(cp->tx_opts)); + + cp_init_rings_index(cp); + +@@ -1151,7 +1136,7 @@ static void cp_clean_rings (struct cp_pr + desc = cp->rx_ring + i; + dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr), + cp->rx_buf_sz, PCI_DMA_FROMDEVICE); +- dev_kfree_skb(cp->rx_skb[i]); ++ dev_kfree_skb_any(cp->rx_skb[i]); + } + } + +@@ -1164,7 +1149,7 @@ static void cp_clean_rings (struct cp_pr + le32_to_cpu(desc->opts1) & 0xffff, + PCI_DMA_TODEVICE); + if (le32_to_cpu(desc->opts1) & LastFrag) +- dev_kfree_skb(skb); ++ dev_kfree_skb_any(skb); + cp->dev->stats.tx_dropped++; + } + } +@@ -1172,6 +1157,7 @@ static void cp_clean_rings (struct cp_pr + + memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE); + memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE); ++ memset(cp->tx_opts, 0, sizeof(cp->tx_opts)); + + memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE); + memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE); +@@ -1249,7 +1235,7 @@ static void cp_tx_timeout(struct net_dev + { + struct cp_private *cp = netdev_priv(dev); + unsigned long flags; +- int rc; ++ int rc, i; + + netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n", + cpr8(Cmd), cpr16(CpCmd), +@@ -1257,13 +1243,26 @@ static void cp_tx_timeout(struct net_dev + + spin_lock_irqsave(&cp->lock, flags); + ++ netif_dbg(cp, tx_err, cp->dev, "TX ring head %d tail %d desc %x\n", ++ cp->tx_head, cp->tx_tail, cpr16(TxDmaOkLowDesc)); ++ for (i = 0; i < CP_TX_RING_SIZE; i++) { ++ netif_dbg(cp, tx_err, cp->dev, ++ "TX slot %d @%p: %08x (%08x) %08x %llx %p\n", ++ i, &cp->tx_ring[i], le32_to_cpu(cp->tx_ring[i].opts1), ++ cp->tx_opts[i], le32_to_cpu(cp->tx_ring[i].opts2), ++ le64_to_cpu(cp->tx_ring[i].addr), ++ cp->tx_skb[i]); ++ } ++ + cp_stop_hw(cp); + cp_clean_rings(cp); + rc = cp_init_rings(cp); + cp_start_hw(cp); +- cp_enable_irq(cp); ++ __cp_set_rx_mode(dev); ++ cpw16_f(IntrMask, cp_norx_intr_mask); + + netif_wake_queue(dev); ++ napi_schedule_irqoff(&cp->napi); + + spin_unlock_irqrestore(&cp->lock, flags); + } diff --git a/target/linux/generic/patches-4.1/761-8139cp-fixes-from-4.4.patch b/target/linux/generic/patches-4.1/761-8139cp-fixes-from-4.4.patch new file mode 100644 index 0000000..8fdf5f3 --- /dev/null +++ b/target/linux/generic/patches-4.1/761-8139cp-fixes-from-4.4.patch @@ -0,0 +1,103 @@ +commit 8b7a7048220f86547db31de0abe1ea6dd2cfa892 +Author: David Woodhouse +Date: Thu Sep 24 11:38:22 2015 +0100 + + 8139cp: Fix GSO MSS handling + + When fixing the TSO support I noticed we just mask ->gso_size with the + MSSMask value and don't care about the consequences. + + Provide a .ndo_features_check() method which drops the NETIF_F_TSO + feature for any skb which would exceed the maximum, and thus forces it + to be segmented by software. + + Then we can stop the masking in cp_start_xmit(), and just WARN if the + maximum is exceeded, which should now never happen. + + Finally, Francois Romieu noticed that we didn't even have the right + value for MSSMask anyway; it should be 0x7ff (11 bits) not 0xfff. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 5a58f227790faded5a3ef6075f3ddd65093e0f86 +Author: David Woodhouse +Date: Wed Sep 23 09:46:09 2015 +0100 + + 8139cp: Enable offload features by default + + I fixed TSO. Hardware checksum and scatter/gather also appear to be + working correctly both on real hardware and in QEMU's emulation. + + Let's enable them by default and see if anyone screams... + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller +--- a/drivers/net/ethernet/realtek/8139cp.c ++++ b/drivers/net/ethernet/realtek/8139cp.c +@@ -175,7 +175,7 @@ enum { + LastFrag = (1 << 28), /* Final segment of a packet */ + LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ + MSSShift = 16, /* MSS value position */ +- MSSMask = 0xfff, /* MSS value: 11 bits */ ++ MSSMask = 0x7ff, /* MSS value: 11 bits */ + TxError = (1 << 23), /* Tx error summary */ + RxError = (1 << 20), /* Rx error summary */ + IPCS = (1 << 18), /* Calculate IP checksum */ +@@ -754,10 +754,16 @@ static netdev_tx_t cp_start_xmit (struct + eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; + mss = skb_shinfo(skb)->gso_size; + ++ if (mss > MSSMask) { ++ WARN_ONCE(1, "Net bug: GSO size %d too large for 8139CP\n", ++ mss); ++ goto out_dma_error; ++ } ++ + opts2 = cpu_to_le32(cp_tx_vlan_tag(skb)); + opts1 = DescOwn; + if (mss) +- opts1 |= LargeSend | ((mss & MSSMask) << MSSShift); ++ opts1 |= LargeSend | (mss << MSSShift); + else if (skb->ip_summed == CHECKSUM_PARTIAL) { + const struct iphdr *ip = ip_hdr(skb); + if (ip->protocol == IPPROTO_TCP) +@@ -1852,6 +1858,15 @@ static void cp_set_d3_state (struct cp_p + pci_set_power_state (cp->pdev, PCI_D3hot); + } + ++static netdev_features_t cp_features_check(struct sk_buff *skb, ++ struct net_device *dev, ++ netdev_features_t features) ++{ ++ if (skb_shinfo(skb)->gso_size > MSSMask) ++ features &= ~NETIF_F_TSO; ++ ++ return vlan_features_check(skb, features); ++} + static const struct net_device_ops cp_netdev_ops = { + .ndo_open = cp_open, + .ndo_stop = cp_close, +@@ -1864,6 +1879,7 @@ static const struct net_device_ops cp_ne + .ndo_tx_timeout = cp_tx_timeout, + .ndo_set_features = cp_set_features, + .ndo_change_mtu = cp_change_mtu, ++ .ndo_features_check = cp_features_check, + + #ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = cp_poll_controller, +@@ -1983,12 +1999,12 @@ static int cp_init_one (struct pci_dev * + dev->ethtool_ops = &cp_ethtool_ops; + dev->watchdog_timeo = TX_TIMEOUT; + +- dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; ++ dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | ++ NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; + + if (pci_using_dac) + dev->features |= NETIF_F_HIGHDMA; + +- /* disabled by default until verified */ + dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | + NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; + dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | diff --git a/target/linux/generic/patches-4.1/773-bgmac-add-srab-switch.patch b/target/linux/generic/patches-4.1/773-bgmac-add-srab-switch.patch new file mode 100644 index 0000000..ae7cb1c --- /dev/null +++ b/target/linux/generic/patches-4.1/773-bgmac-add-srab-switch.patch @@ -0,0 +1,72 @@ +Register switch connected to srab + +Signed-off-by: Hauke Mehrtens + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + static const struct bcma_device_id bgmac_bcma_tbl[] = { +@@ -1538,6 +1539,17 @@ static void bgmac_mii_unregister(struct + mdiobus_free(mii_bus); + } + ++static struct b53_platform_data bgmac_b53_pdata = { ++}; ++ ++static struct platform_device bgmac_b53_dev = { ++ .name = "b53-srab-switch", ++ .id = -1, ++ .dev = { ++ .platform_data = &bgmac_b53_pdata, ++ }, ++}; ++ + /************************************************** + * BCMA bus ops + **************************************************/ +@@ -1664,6 +1676,16 @@ static int bgmac_probe(struct bcma_devic + net_dev->hw_features = net_dev->features; + net_dev->vlan_features = net_dev->features; + ++ if ((ci->id == BCMA_CHIP_ID_BCM4707 || ++ ci->id == BCMA_CHIP_ID_BCM53018) && ++ !bgmac_b53_pdata.regs) { ++ bgmac_b53_pdata.regs = ioremap_nocache(0x18007000, 0x1000); ++ ++ err = platform_device_register(&bgmac_b53_dev); ++ if (!err) ++ bgmac->b53_device = &bgmac_b53_dev; ++ } ++ + err = register_netdev(bgmac->net_dev); + if (err) { + bgmac_err(bgmac, "Cannot register net device\n"); +@@ -1690,6 +1712,10 @@ static void bgmac_remove(struct bcma_dev + { + struct bgmac *bgmac = bcma_get_drvdata(core); + ++ if (bgmac->b53_device) ++ platform_device_unregister(&bgmac_b53_dev); ++ bgmac->b53_device = NULL; ++ + unregister_netdev(bgmac->net_dev); + bgmac_mii_unregister(bgmac); + netif_napi_del(&bgmac->napi); +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -462,6 +462,9 @@ struct bgmac { + bool has_robosw; + + bool loopback; ++ ++ /* platform device for associated switch */ ++ struct platform_device *b53_device; + }; + + static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset) diff --git a/target/linux/generic/patches-4.1/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch b/target/linux/generic/patches-4.1/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch new file mode 100644 index 0000000..2603d6c --- /dev/null +++ b/target/linux/generic/patches-4.1/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch @@ -0,0 +1,40 @@ +From cb06d102327eadcd1bdc480bfd9f8876251d1007 Mon Sep 17 00:00:00 2001 +From: Christoph Paasch +Date: Fri, 21 Mar 2014 03:48:19 -0700 +Subject: [PATCH] igb: Fix Null-pointer dereference in igb_reset_q_vector + +When igb_set_interrupt_capability() calls +igb_reset_interrupt_capability() (e.g., because CONFIG_PCI_MSI is unset), +num_q_vectors has been set but no vector has yet been allocated. + +igb_reset_interrupt_capability() will then call igb_reset_q_vector, +which assumes that the vector is allocated. As this is not the case, we +are accessing a NULL-pointer. + +This patch fixes it by checking that q_vector is indeed different from +NULL. + +Fixes: 02ef6e1d0b0023 (igb: Fix queue allocation method to accommodate changing during runtime) +Cc: Carolyn Wyborny +Signed-off-by: Christoph Paasch +Tested-by: Jeff Pieper +Signed-off-by: Jeff Kirsher +--- + drivers/net/ethernet/intel/igb/igb_main.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/ethernet/intel/igb/igb_main.c ++++ b/drivers/net/ethernet/intel/igb/igb_main.c +@@ -1032,6 +1032,12 @@ static void igb_reset_q_vector(struct ig + if (!q_vector) + return; + ++ /* Coming from igb_set_interrupt_capability, the vectors are not yet ++ * allocated. So, q_vector is NULL so we should stop here. ++ */ ++ if (!q_vector) ++ return; ++ + if (q_vector->tx.ring) + adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; + diff --git a/target/linux/generic/patches-4.1/785-hso-support-0af0-9300.patch b/target/linux/generic/patches-4.1/785-hso-support-0af0-9300.patch new file mode 100644 index 0000000..621d08f --- /dev/null +++ b/target/linux/generic/patches-4.1/785-hso-support-0af0-9300.patch @@ -0,0 +1,25 @@ +--- a/drivers/net/usb/hso.c ++++ b/drivers/net/usb/hso.c +@@ -466,6 +466,7 @@ static const struct usb_device_id hso_id + {USB_DEVICE(0x0af0, 0x8900)}, + {USB_DEVICE(0x0af0, 0x9000)}, + {USB_DEVICE(0x0af0, 0x9200)}, /* Option GTM671WFS */ ++ {USB_DEVICE(0x0af0, 0x9300)}, /* GTM 66xxWFS */ + {USB_DEVICE(0x0af0, 0xd035)}, + {USB_DEVICE(0x0af0, 0xd055)}, + {USB_DEVICE(0x0af0, 0xd155)}, +--- a/drivers/usb/storage/unusual_devs.h ++++ b/drivers/usb/storage/unusual_devs.h +@@ -1330,6 +1330,12 @@ UNUSUAL_DEV( 0x0af0, 0x8304, 0x0000, 0x0 + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + 0 ), + ++UNUSUAL_DEV( 0x0af0, 0x9300, 0x0000, 0x0000, ++ "Option", ++ "Globetrotter 66xxWFS SD-Card", ++ USB_SC_DEVICE, USB_PR_DEVICE, NULL, ++ 0 ), ++ + UNUSUAL_DEV( 0x0af0, 0xc100, 0x0000, 0x0000, + "Option", + "GI 070x SD-Card", diff --git a/target/linux/generic/patches-4.1/810-pci_disable_common_quirks.patch b/target/linux/generic/patches-4.1/810-pci_disable_common_quirks.patch new file mode 100644 index 0000000..89d93e1 --- /dev/null +++ b/target/linux/generic/patches-4.1/810-pci_disable_common_quirks.patch @@ -0,0 +1,51 @@ +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -68,6 +68,12 @@ config XEN_PCIDEV_FRONTEND + The PCI device frontend driver allows the kernel to import arbitrary + PCI devices from a PCI backend to support PCI driver domains. + ++config PCI_DISABLE_COMMON_QUIRKS ++ bool "PCI disable common quirks" ++ depends on PCI ++ help ++ If you don't know what to do here, say N. ++ + config HT_IRQ + bool "Interrupts on hypertransport devices" + default y +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -41,6 +41,7 @@ static void quirk_mmio_always_on(struct + DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS + /* The Mellanox Tavor device gives false positive parity errors + * Mark this device with a broken_parity_status, to allow + * PCI scanning code to "skip" this now blacklisted device. +@@ -2965,6 +2966,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); + ++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ + + /* + * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To +@@ -3021,6 +3023,8 @@ static void fixup_debug_report(struct pc + } + } + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + /* + * Some BIOS implementations leave the Intel GPU interrupts enabled, + * even though no one is handling them (f.e. i915 driver is never loaded). +@@ -3055,6 +3059,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); + ++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ ++ + /* + * PCI devices which are on Intel chips can skip the 10ms delay + * before entering D3 mode. diff --git a/target/linux/generic/patches-4.1/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/patches-4.1/811-pci_disable_usb_common_quirks.patch new file mode 100644 index 0000000..6de4f6b --- /dev/null +++ b/target/linux/generic/patches-4.1/811-pci_disable_usb_common_quirks.patch @@ -0,0 +1,101 @@ + +--- a/drivers/usb/host/pci-quirks.c ++++ b/drivers/usb/host/pci-quirks.c +@@ -97,6 +97,8 @@ struct amd_chipset_type { + u8 rev; + }; + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + static struct amd_chipset_info { + struct pci_dev *nb_dev; + struct pci_dev *smbus_dev; +@@ -450,6 +452,10 @@ void usb_amd_dev_put(void) + } + EXPORT_SYMBOL_GPL(usb_amd_dev_put); + ++#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */ ++ ++#if IS_ENABLED(CONFIG_USB_UHCI_HCD) ++ + /* + * Make sure the controller is completely inactive, unable to + * generate interrupts or do DMA. +@@ -529,8 +535,17 @@ reset_needed: + uhci_reset_hc(pdev, base); + return 1; + } ++#else ++int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) ++{ ++ return 0; ++} ++ ++#endif + EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) + { + u16 cmd; +@@ -1095,3 +1110,4 @@ static void quirk_usb_early_handoff(stru + } + DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); ++#endif +--- a/drivers/usb/host/pci-quirks.h ++++ b/drivers/usb/host/pci-quirks.h +@@ -4,6 +4,9 @@ + #ifdef CONFIG_PCI + void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); + int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); ++#endif /* CONFIG_PCI */ ++ ++#if defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_COMMON_QUIRKS) + int usb_amd_find_chipset_info(void); + int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev); + bool usb_amd_hang_symptom_quirk(void); +@@ -16,11 +19,24 @@ void usb_disable_xhci_ports(struct pci_d + void sb800_prefetch(struct device *dev, int on); + #else + struct pci_dev; ++static inline int usb_amd_find_chipset_info(void) ++{ ++ return 0; ++} ++static inline bool usb_amd_hang_symptom_quirk(void) ++{ ++ return false; ++} ++static inline bool usb_amd_prefetch_quirk(void) ++{ ++ return false; ++} + static inline void usb_amd_quirk_pll_disable(void) {} + static inline void usb_amd_quirk_pll_enable(void) {} + static inline void usb_amd_dev_put(void) {} + static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {} + static inline void sb800_prefetch(struct device *dev, int on) {} +-#endif /* CONFIG_PCI */ ++static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {} ++#endif + + #endif /* __LINUX_USB_PCI_QUIRKS_H */ +--- a/include/linux/usb/hcd.h ++++ b/include/linux/usb/hcd.h +@@ -447,7 +447,14 @@ extern int usb_hcd_pci_probe(struct pci_ + extern void usb_hcd_pci_remove(struct pci_dev *dev); + extern void usb_hcd_pci_shutdown(struct pci_dev *dev); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS + extern int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev); ++#else ++static inline int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev) ++{ ++ return 0; ++} ++#endif + + #ifdef CONFIG_PM + extern const struct dev_pm_ops usb_hcd_pci_pm_ops; diff --git a/target/linux/generic/patches-4.1/820-usb_add_usb_find_device_by_name.patch b/target/linux/generic/patches-4.1/820-usb_add_usb_find_device_by_name.patch new file mode 100644 index 0000000..906f0e2 --- /dev/null +++ b/target/linux/generic/patches-4.1/820-usb_add_usb_find_device_by_name.patch @@ -0,0 +1,84 @@ +--- a/drivers/usb/core/usb.c ++++ b/drivers/usb/core/usb.c +@@ -704,6 +704,71 @@ int __usb_get_extra_descriptor(char *buf + } + EXPORT_SYMBOL_GPL(__usb_get_extra_descriptor); + ++static struct usb_device *match_device_name(struct usb_device *dev, ++ const char *name) ++{ ++ struct usb_device *ret_dev = NULL; ++ struct usb_device *childdev = NULL; ++ int child; ++ ++ dev_dbg(&dev->dev, "check for name %s ...\n", name); ++ ++ /* see if this device matches */ ++ if (strcmp(dev_name(&dev->dev), name) == 0 ) { ++ dev_dbg(&dev->dev, "matched this device!\n"); ++ ret_dev = usb_get_dev(dev); ++ goto exit; ++ } ++ /* look through all of the children of this device */ ++ usb_hub_for_each_child(dev, child, childdev) { ++ if (childdev) { ++ usb_lock_device(childdev); ++ ret_dev = match_device_name(childdev, name); ++ usb_unlock_device(childdev); ++ if (ret_dev) ++ goto exit; ++ } ++ } ++exit: ++ return ret_dev; ++} ++ ++/** ++ * usb_find_device_by_name - find a specific usb device in the system ++ * @name: the name of the device to find ++ * ++ * Returns a pointer to a struct usb_device if such a specified usb ++ * device is present in the system currently. The usage count of the ++ * device will be incremented if a device is found. Make sure to call ++ * usb_put_dev() when the caller is finished with the device. ++ * ++ * If a device with the specified bus id is not found, NULL is returned. ++ */ ++struct usb_device *usb_find_device_by_name(const char *name) ++{ ++ struct list_head *buslist; ++ struct usb_bus *bus; ++ struct usb_device *dev = NULL; ++ ++ mutex_lock(&usb_bus_list_lock); ++ for (buslist = usb_bus_list.next; ++ buslist != &usb_bus_list; ++ buslist = buslist->next) { ++ bus = container_of(buslist, struct usb_bus, bus_list); ++ if (!bus->root_hub) ++ continue; ++ usb_lock_device(bus->root_hub); ++ dev = match_device_name(bus->root_hub, name); ++ usb_unlock_device(bus->root_hub); ++ if (dev) ++ goto exit; ++ } ++exit: ++ mutex_unlock(&usb_bus_list_lock); ++ return dev; ++} ++EXPORT_SYMBOL_GPL(usb_find_device_by_name); ++ + /** + * usb_alloc_coherent - allocate dma-consistent buffer for URB_NO_xxx_DMA_MAP + * @dev: device the buffer will be used with +--- a/include/linux/usb.h ++++ b/include/linux/usb.h +@@ -721,6 +721,7 @@ static inline bool usb_device_no_sg_cons + return udev && udev->bus && udev->bus->no_sg_constraint; + } + ++extern struct usb_device *usb_find_device_by_name(const char *name); + + /*-------------------------------------------------------------------------*/ + diff --git a/target/linux/generic/patches-4.1/830-ledtrig_morse.patch b/target/linux/generic/patches-4.1/830-ledtrig_morse.patch new file mode 100644 index 0000000..31b5781 --- /dev/null +++ b/target/linux/generic/patches-4.1/830-ledtrig_morse.patch @@ -0,0 +1,28 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -108,4 +108,8 @@ config LEDS_TRIGGER_CAMERA + This enables direct flash/torch on/off by the driver, kernel space. + If unsure, say Y. + ++config LEDS_TRIGGER_MORSE ++ tristate "LED Morse Trigger" ++ depends on LEDS_TRIGGERS ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -65,3 +65,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ ++obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o +--- a/drivers/leds/ledtrig-morse.c ++++ b/drivers/leds/ledtrig-morse.c +@@ -26,7 +26,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/generic/patches-4.1/831-ledtrig_netdev.patch b/target/linux/generic/patches-4.1/831-ledtrig_netdev.patch new file mode 100644 index 0000000..f2a5a2a --- /dev/null +++ b/target/linux/generic/patches-4.1/831-ledtrig_netdev.patch @@ -0,0 +1,60 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -112,4 +112,11 @@ config LEDS_TRIGGER_MORSE + tristate "LED Morse Trigger" + depends on LEDS_TRIGGERS + ++config LEDS_TRIGGER_NETDEV ++ tristate "LED Netdev Trigger" ++ depends on NET && LEDS_TRIGGERS ++ help ++ This allows LEDs to be controlled by network device activity. ++ If unsure, say Y. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -66,3 +66,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o ++obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o +--- a/drivers/leds/ledtrig-netdev.c ++++ b/drivers/leds/ledtrig-netdev.c +@@ -22,7 +22,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -254,7 +253,7 @@ static int netdev_trig_notify(struct not + unsigned long evt, + void *dv) + { +- struct net_device *dev = dv; ++ struct net_device *dev = netdev_notifier_info_to_dev((struct netdev_notifier_info *) dv); + struct led_netdev_data *trigger_data = container_of(nb, struct led_netdev_data, notifier); + + if (evt != NETDEV_UP && evt != NETDEV_DOWN && evt != NETDEV_CHANGE && evt != NETDEV_REGISTER && evt != NETDEV_UNREGISTER) +@@ -294,8 +293,9 @@ done: + static void netdev_trig_timer(unsigned long arg) + { + struct led_netdev_data *trigger_data = (struct led_netdev_data *)arg; +- const struct net_device_stats *dev_stats; ++ struct rtnl_link_stats64 *dev_stats; + unsigned new_activity; ++ struct rtnl_link_stats64 temp; + + write_lock(&trigger_data->lock); + +@@ -305,7 +305,7 @@ static void netdev_trig_timer(unsigned l + goto no_restart; + } + +- dev_stats = dev_get_stats(trigger_data->net_dev); ++ dev_stats = dev_get_stats(trigger_data->net_dev, &temp); + new_activity = + ((trigger_data->mode & MODE_TX) ? dev_stats->tx_packets : 0) + + ((trigger_data->mode & MODE_RX) ? dev_stats->rx_packets : 0); diff --git a/target/linux/generic/patches-4.1/832-ledtrig_usbdev.patch b/target/linux/generic/patches-4.1/832-ledtrig_usbdev.patch new file mode 100644 index 0000000..564aab5 --- /dev/null +++ b/target/linux/generic/patches-4.1/832-ledtrig_usbdev.patch @@ -0,0 +1,31 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -119,4 +119,11 @@ config LEDS_TRIGGER_NETDEV + This allows LEDs to be controlled by network device activity. + If unsure, say Y. + ++config LEDS_TRIGGER_USBDEV ++ tristate "LED USB device Trigger" ++ depends on USB && LEDS_TRIGGERS ++ help ++ This allows LEDs to be controlled by the presence/activity of ++ an USB device. If unsure, say N. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -67,3 +67,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o + obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o ++obj-$(CONFIG_LEDS_TRIGGER_USBDEV) += ledtrig-usbdev.o +--- a/drivers/leds/ledtrig-usbdev.c ++++ b/drivers/leds/ledtrig-usbdev.c +@@ -24,7 +24,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/generic/patches-4.1/834-ledtrig-libata.patch b/target/linux/generic/patches-4.1/834-ledtrig-libata.patch new file mode 100644 index 0000000..84b722d --- /dev/null +++ b/target/linux/generic/patches-4.1/834-ledtrig-libata.patch @@ -0,0 +1,153 @@ +From 52cfd51cdf6a6e14d4fb270c6343abac3bac00f4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 12 Dec 2014 13:38:33 +0100 +Subject: [PATCH] libata: add ledtrig support +To: linux-ide@vger.kernel.org, + Tejun Heo + +This adds a LED trigger for each ATA port indicating disk activity. + +As this is needed only on specific platforms (NAS SoCs and such), +these platforms should define ARCH_WANTS_LIBATA_LEDS if there +are boards with LED(s) intended to indicate ATA disk activity and +need the OS to take care of that. +In that way, if not selected, LED trigger support not will be +included in libata-core and both, codepaths and structures remain +untouched. + +Signed-off-by: Daniel Golle +--- + drivers/ata/Kconfig | 16 ++++++++++++++++ + drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++ + include/linux/libata.h | 9 +++++++++ + 3 files changed, 66 insertions(+) + +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -46,6 +46,22 @@ config ATA_VERBOSE_ERROR + + If unsure, say Y. + ++config ARCH_WANT_LIBATA_LEDS ++ bool ++ ++config ATA_LEDS ++ bool "support ATA port LED triggers" ++ depends on ARCH_WANT_LIBATA_LEDS ++ select NEW_LEDS ++ select LEDS_CLASS ++ select LEDS_TRIGGERS ++ default y ++ help ++ This option adds a LED trigger for each registered ATA port. ++ It is used to drive disk activity leds connected via GPIO. ++ ++ If unsure, say N. ++ + config ATA_ACPI + bool "ATA ACPI Support" + depends on ACPI && PCI +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -728,6 +728,19 @@ u64 ata_tf_read_block(struct ata_taskfil + return block; + } + ++#ifdef CONFIG_ATA_LEDS ++#define LIBATA_BLINK_DELAY 20 /* ms */ ++static inline void ata_led_act(struct ata_port *ap) ++{ ++ unsigned long led_delay = LIBATA_BLINK_DELAY; ++ ++ if (unlikely(!ap->ledtrig)) ++ return; ++ ++ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0); ++} ++#endif ++ + /** + * ata_build_rw_tf - Build ATA taskfile for given read/write request + * @tf: Target ATA taskfile +@@ -4773,6 +4786,9 @@ struct ata_queued_cmd *ata_qc_new_init(s + if (tag < 0) + return NULL; + } ++#ifdef CONFIG_ATA_LEDS ++ ata_led_act(ap); ++#endif + + qc = __ata_qc_from_tag(ap, tag); + qc->tag = tag; +@@ -5670,6 +5686,9 @@ struct ata_port *ata_port_alloc(struct a + ap->stats.unhandled_irq = 1; + ap->stats.idle_irq = 1; + #endif ++#ifdef CONFIG_ATA_LEDS ++ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL); ++#endif + ata_sff_port_init(ap); + + return ap; +@@ -5691,6 +5710,12 @@ static void ata_host_release(struct devi + + kfree(ap->pmp_link); + kfree(ap->slave_link); ++#ifdef CONFIG_ATA_LEDS ++ if (ap->ledtrig) { ++ led_trigger_unregister(ap->ledtrig); ++ kfree(ap->ledtrig); ++ }; ++#endif + kfree(ap); + host->ports[i] = NULL; + } +@@ -6137,7 +6162,23 @@ int ata_host_register(struct ata_host *h + host->ports[i]->print_id = atomic_inc_return(&ata_print_id); + host->ports[i]->local_port_no = i + 1; + } ++#ifdef CONFIG_ATA_LEDS ++ for (i = 0; i < host->n_ports; i++) { ++ if (unlikely(!host->ports[i]->ledtrig)) ++ continue; + ++ snprintf(host->ports[i]->ledtrig_name, ++ sizeof(host->ports[i]->ledtrig_name), "ata%u", ++ host->ports[i]->print_id); ++ ++ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name; ++ ++ if (led_trigger_register(host->ports[i]->ledtrig)) { ++ kfree(host->ports[i]->ledtrig); ++ host->ports[i]->ledtrig = NULL; ++ } ++ } ++#endif + /* Create associated sysfs transport objects */ + for (i = 0; i < host->n_ports; i++) { + rc = ata_tport_add(host->dev,host->ports[i]); +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -38,6 +38,9 @@ + #include + #include + #include ++#ifdef CONFIG_ATA_LEDS ++#include ++#endif + + /* + * Define if arch has non-standard setup. This is a _PCI_ standard +@@ -876,6 +879,12 @@ struct ata_port { + #ifdef CONFIG_ATA_ACPI + struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ + #endif ++ ++#ifdef CONFIG_ATA_LEDS ++ struct led_trigger *ledtrig; ++ char ledtrig_name[8]; ++#endif ++ + /* owned by EH */ + u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; + }; diff --git a/target/linux/generic/patches-4.1/840-rtc7301.patch b/target/linux/generic/patches-4.1/840-rtc7301.patch new file mode 100644 index 0000000..148ccaa --- /dev/null +++ b/target/linux/generic/patches-4.1/840-rtc7301.patch @@ -0,0 +1,250 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1109,6 +1109,15 @@ config RTC_DRV_OPAL + This driver can also be built as a module. If so, the module + will be called rtc-opal. + ++config RTC_DRV_RTC7301 ++ tristate "Epson RTC-7301 SF/DG" ++ help ++ If you say Y here you will get support for the ++ Epson RTC-7301 SF/DG RTC chips. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-7301. ++ + comment "on-CPU RTC drivers" + + config RTC_DRV_DAVINCI +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -121,6 +121,7 @@ obj-$(CONFIG_RTC_DRV_RP5C01) += rtc-rp5c + obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o + obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o + obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o ++obj-$(CONFIG_RTC_DRV_RTC7301) += rtc-rtc7301.o + obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o + obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o + obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o +--- /dev/null ++++ b/drivers/rtc/rtc-rtc7301.c +@@ -0,0 +1,219 @@ ++/* ++ * Driver for Epson RTC-7301SF/DG ++ * ++ * Copyright (C) 2009 Jose Vasconcellos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RTC_NAME "rtc7301" ++#define RTC_VERSION "0.1" ++ ++/* Epson RTC-7301 register addresses */ ++#define RTC7301_SEC 0x00 ++#define RTC7301_SEC10 0x01 ++#define RTC7301_MIN 0x02 ++#define RTC7301_MIN10 0x03 ++#define RTC7301_HOUR 0x04 ++#define RTC7301_HOUR10 0x05 ++#define RTC7301_WEEKDAY 0x06 ++#define RTC7301_DAY 0x07 ++#define RTC7301_DAY10 0x08 ++#define RTC7301_MON 0x09 ++#define RTC7301_MON10 0x0A ++#define RTC7301_YEAR 0x0B ++#define RTC7301_YEAR10 0x0C ++#define RTC7301_YEAR100 0x0D ++#define RTC7301_YEAR1000 0x0E ++#define RTC7301_CTRLREG 0x0F ++ ++static uint8_t __iomem *rtc7301_base; ++ ++#define read_reg(offset) (readb(rtc7301_base + offset) & 0xf) ++#define write_reg(offset, data) writeb(data, rtc7301_base + (offset)) ++ ++#define rtc7301_isbusy() (read_reg(RTC7301_CTRLREG) & 1) ++ ++static void rtc7301_init_settings(void) ++{ ++ int i; ++ ++ write_reg(RTC7301_CTRLREG, 2); ++ write_reg(RTC7301_YEAR1000, 2); ++ udelay(122); ++ ++ /* bank 1 */ ++ write_reg(RTC7301_CTRLREG, 6); ++ for (i=0; i<15; i++) ++ write_reg(i, 0); ++ ++ /* bank 2 */ ++ write_reg(RTC7301_CTRLREG, 14); ++ for (i=0; i<15; i++) ++ write_reg(i, 0); ++ write_reg(RTC7301_CTRLREG, 0); ++} ++ ++static int rtc7301_get_datetime(struct device *dev, struct rtc_time *dt) ++{ ++ int cnt; ++ uint8_t buf[16]; ++ ++ cnt = 0; ++ while (rtc7301_isbusy()) { ++ udelay(244); ++ if (cnt++ > 100) { ++ dev_err(dev, "%s: timeout error %x\n", __func__, rtc7301_base[RTC7301_CTRLREG]); ++ return -EIO; ++ } ++ } ++ ++ for (cnt=0; cnt<16; cnt++) ++ buf[cnt] = read_reg(cnt); ++ ++ if (buf[RTC7301_SEC10] & 8) { ++ dev_err(dev, "%s: RTC not set\n", __func__); ++ return -EINVAL; ++ } ++ ++ memset(dt, 0, sizeof(*dt)); ++ ++ dt->tm_sec = buf[RTC7301_SEC] + buf[RTC7301_SEC10]*10; ++ dt->tm_min = buf[RTC7301_MIN] + buf[RTC7301_MIN10]*10; ++ dt->tm_hour = buf[RTC7301_HOUR] + buf[RTC7301_HOUR10]*10; ++ ++ dt->tm_mday = buf[RTC7301_DAY] + buf[RTC7301_DAY10]*10; ++ dt->tm_mon = buf[RTC7301_MON] + buf[RTC7301_MON10]*10 - 1; ++ dt->tm_year = buf[RTC7301_YEAR] + buf[RTC7301_YEAR10]*10 + ++ buf[RTC7301_YEAR100]*100 + ++ ((buf[RTC7301_YEAR1000] & 3)*1000) - 1900; ++ ++ /* the rtc device may contain illegal values on power up ++ * according to the data sheet. make sure they are valid. ++ */ ++ ++ return rtc_valid_tm(dt); ++} ++ ++static int rtc7301_set_datetime(struct device *dev, struct rtc_time *dt) ++{ ++ int data; ++ ++ data = dt->tm_year + 1900; ++ if (data >= 2100 || data < 1900) ++ return -EINVAL; ++ ++ write_reg(RTC7301_CTRLREG, 2); ++ udelay(122); ++ ++ data = bin2bcd(dt->tm_sec); ++ write_reg(RTC7301_SEC, data); ++ write_reg(RTC7301_SEC10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_min); ++ write_reg(RTC7301_MIN, data ); ++ write_reg(RTC7301_MIN10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_hour); ++ write_reg(RTC7301_HOUR, data); ++ write_reg(RTC7301_HOUR10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_mday); ++ write_reg(RTC7301_DAY, data); ++ write_reg(RTC7301_DAY10, (data>> 4)); ++ ++ data = bin2bcd(dt->tm_mon + 1); ++ write_reg(RTC7301_MON, data); ++ write_reg(RTC7301_MON10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_year % 100); ++ write_reg(RTC7301_YEAR, data); ++ write_reg(RTC7301_YEAR10, (data >> 4)); ++ data = bin2bcd((1900 + dt->tm_year) / 100); ++ write_reg(RTC7301_YEAR100, data); ++ ++ data = bin2bcd(dt->tm_wday); ++ write_reg(RTC7301_WEEKDAY, data); ++ ++ write_reg(RTC7301_CTRLREG, 0); ++ ++ return 0; ++} ++ ++static const struct rtc_class_ops rtc7301_rtc_ops = { ++ .read_time = rtc7301_get_datetime, ++ .set_time = rtc7301_set_datetime, ++}; ++ ++static int rtc7301_probe(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc; ++ struct resource *res; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return -ENOENT; ++ ++ rtc7301_base = ioremap_nocache(res->start, 0x1000 /*res->end - res->start + 1*/); ++ if (!rtc7301_base) ++ return -EINVAL; ++ ++ rtc = rtc_device_register(RTC_NAME, &pdev->dev, ++ &rtc7301_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtc)) { ++ iounmap(rtc7301_base); ++ return PTR_ERR(rtc); ++ } ++ ++ platform_set_drvdata(pdev, rtc); ++ ++ rtc7301_init_settings(); ++ return 0; ++} ++ ++static int rtc7301_remove(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc = platform_get_drvdata(pdev); ++ ++ if (rtc) ++ rtc_device_unregister(rtc); ++ if (rtc7301_base) ++ iounmap(rtc7301_base); ++ return 0; ++} ++ ++static struct platform_driver rtc7301_driver = { ++ .driver = { ++ .name = RTC_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = rtc7301_probe, ++ .remove = rtc7301_remove, ++}; ++ ++static __init int rtc7301_init(void) ++{ ++ return platform_driver_register(&rtc7301_driver); ++} ++module_init(rtc7301_init); ++ ++static __exit void rtc7301_exit(void) ++{ ++ platform_driver_unregister(&rtc7301_driver); ++} ++module_exit(rtc7301_exit); ++ ++MODULE_DESCRIPTION("Epson 7301 RTC driver"); ++MODULE_AUTHOR("Jose Vasconcellos "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" RTC_NAME); ++MODULE_VERSION(RTC_VERSION); diff --git a/target/linux/generic/patches-4.1/841-rtc_pt7c4338.patch b/target/linux/generic/patches-4.1/841-rtc_pt7c4338.patch new file mode 100644 index 0000000..5de1b87 --- /dev/null +++ b/target/linux/generic/patches-4.1/841-rtc_pt7c4338.patch @@ -0,0 +1,247 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -596,6 +596,15 @@ config RTC_DRV_S5M + This driver can also be built as a module. If so, the module + will be called rtc-s5m. + ++config RTC_DRV_PT7C4338 ++ tristate "Pericom Technology Inc. PT7C4338 RTC" ++ help ++ If you say yes here you get support for the Pericom Technology ++ Inc. PT7C4338 RTC chip. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-pt7c4338. ++ + endif # I2C + + comment "SPI RTC drivers" +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -112,6 +112,7 @@ obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030 + obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o + obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o + obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o ++obj-$(CONFIG_RTC_DRV_PT7C4338) += rtc-pt7c4338.o + obj-$(CONFIG_RTC_DRV_PUV3) += rtc-puv3.o + obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o + obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o +--- /dev/null ++++ b/drivers/rtc/rtc-pt7c4338.c +@@ -0,0 +1,216 @@ ++/* ++ * Copyright 2010 Freescale Semiconductor, Inc. ++ * ++ * Author: Priyanka Jain ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * This file provides Date & Time support (no alarms) for PT7C4338 chip. ++ * ++ * This file is based on drivers/rtc/rtc-ds1307.c ++ * ++ * PT7C4338 chip is manufactured by Pericom Technology Inc. ++ * It is a serial real-time clock which provides ++ * 1)Low-power clock/calendar. ++ * 2)Programmable square-wave output. ++ * It has 56 bytes of nonvolatile RAM. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* RTC register addresses */ ++#define PT7C4338_REG_SECONDS 0x00 ++#define PT7C4338_REG_MINUTES 0x01 ++#define PT7C4338_REG_HOURS 0x02 ++#define PT7C4338_REG_AMPM 0x02 ++#define PT7C4338_REG_DAY 0x03 ++#define PT7C4338_REG_DATE 0x04 ++#define PT7C4338_REG_MONTH 0x05 ++#define PT7C4338_REG_YEAR 0x06 ++#define PT7C4338_REG_CTRL_STAT 0x07 ++ ++/* RTC second register address bit */ ++#define PT7C4338_SEC_BIT_CH 0x80 /*Clock Halt (in Register 0)*/ ++ ++/* RTC control and status register bits */ ++#define PT7C4338_CTRL_STAT_BIT_RS0 0x1 /*Rate select 0*/ ++#define PT7C4338_CTRL_STAT_BIT_RS1 0x2 /*Rate select 1*/ ++#define PT7C4338_CTRL_STAT_BIT_SQWE 0x10 /*Square Wave Enable*/ ++#define PT7C4338_CTRL_STAT_BIT_OSF 0x20 /*Oscillator Stop Flag*/ ++#define PT7C4338_CTRL_STAT_BIT_OUT 0x80 /*Output Level Control*/ ++ ++static const struct i2c_device_id pt7c4338_id[] = { ++ { "pt7c4338", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, pt7c4338_id); ++ ++struct pt7c4338{ ++ struct i2c_client *client; ++ struct rtc_device *rtc; ++}; ++ ++static int pt7c4338_read_time(struct device *dev, struct rtc_time *time) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ int ret; ++ u8 buf[7]; ++ u8 year, month, day, hour, minute, second; ++ u8 week, twelve_hr, am_pm; ++ ++ ret = i2c_smbus_read_i2c_block_data(client, ++ PT7C4338_REG_SECONDS, 7, buf); ++ if (ret < 0) ++ return ret; ++ if (ret < 7) ++ return -EIO; ++ ++ second = buf[0]; ++ minute = buf[1]; ++ hour = buf[2]; ++ week = buf[3]; ++ day = buf[4]; ++ month = buf[5]; ++ year = buf[6]; ++ ++ /* Extract additional information for AM/PM */ ++ twelve_hr = hour & 0x40; ++ am_pm = hour & 0x20; ++ ++ /* Write to rtc_time structure */ ++ time->tm_sec = bcd2bin(second & 0x7f); ++ time->tm_min = bcd2bin(minute & 0x7f); ++ if (twelve_hr) { ++ /* Convert to 24 hr */ ++ if (am_pm) ++ time->tm_hour = bcd2bin(hour & 0x10) + 12; ++ else ++ time->tm_hour = bcd2bin(hour & 0xBF); ++ } else { ++ time->tm_hour = bcd2bin(hour); ++ } ++ ++ time->tm_wday = bcd2bin(week & 0x07) - 1; ++ time->tm_mday = bcd2bin(day & 0x3f); ++ time->tm_mon = bcd2bin(month & 0x1F) - 1; ++ /* assume 20YY not 19YY */ ++ time->tm_year = bcd2bin(year) + 100; ++ ++ return 0; ++} ++ ++static int pt7c4338_set_time(struct device *dev, struct rtc_time *time) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ u8 buf[7]; ++ ++ /* Extract time from rtc_time and load into pt7c4338*/ ++ buf[0] = bin2bcd(time->tm_sec); ++ buf[1] = bin2bcd(time->tm_min); ++ buf[2] = bin2bcd(time->tm_hour); ++ buf[3] = bin2bcd(time->tm_wday + 1); /* Day of the week */ ++ buf[4] = bin2bcd(time->tm_mday); /* Date */ ++ buf[5] = bin2bcd(time->tm_mon + 1); ++ ++ /* assume 20YY not 19YY */ ++ if (time->tm_year >= 100) ++ buf[6] = bin2bcd(time->tm_year - 100); ++ else ++ buf[6] = bin2bcd(time->tm_year); ++ ++ return i2c_smbus_write_i2c_block_data(client, ++ PT7C4338_REG_SECONDS, 7, buf); ++} ++ ++static const struct rtc_class_ops pt7c4338_rtc_ops = { ++ .read_time = pt7c4338_read_time, ++ .set_time = pt7c4338_set_time, ++}; ++ ++static int pt7c4338_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct pt7c4338 *pt7c4338; ++ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); ++ int ret; ++ ++ pt7c4338 = kzalloc(sizeof(struct pt7c4338), GFP_KERNEL); ++ if (!pt7c4338) ++ return -ENOMEM; ++ ++ pt7c4338->client = client; ++ i2c_set_clientdata(client, pt7c4338); ++ pt7c4338->rtc = rtc_device_register(client->name, &client->dev, ++ &pt7c4338_rtc_ops, THIS_MODULE); ++ if (IS_ERR(pt7c4338->rtc)) { ++ ret = PTR_ERR(pt7c4338->rtc); ++ dev_err(&client->dev, "unable to register the class device\n"); ++ goto out_free; ++ } ++ ++ return 0; ++out_free: ++ i2c_set_clientdata(client, NULL); ++ kfree(pt7c4338); ++ return ret; ++} ++ ++static int pt7c4338_remove(struct i2c_client *client) ++{ ++ struct pt7c4338 *pt7c4338 = i2c_get_clientdata(client); ++ ++ rtc_device_unregister(pt7c4338->rtc); ++ i2c_set_clientdata(client, NULL); ++ kfree(pt7c4338); ++ return 0; ++} ++ ++static struct i2c_driver pt7c4338_driver = { ++ .driver = { ++ .name = "rtc-pt7c4338", ++ .owner = THIS_MODULE, ++ }, ++ .probe = pt7c4338_probe, ++ .remove = pt7c4338_remove, ++ .id_table = pt7c4338_id, ++}; ++ ++static int __init pt7c4338_init(void) ++{ ++ return i2c_add_driver(&pt7c4338_driver); ++} ++ ++static void __exit pt7c4338_exit(void) ++{ ++ i2c_del_driver(&pt7c4338_driver); ++} ++ ++module_init(pt7c4338_init); ++module_exit(pt7c4338_exit); ++ ++MODULE_AUTHOR("Priyanka Jain "); ++MODULE_DESCRIPTION("pericom Technology Inc. PT7C4338 RTC Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.1/861-04_spi_gpio_implement_spi_delay.patch b/target/linux/generic/patches-4.1/861-04_spi_gpio_implement_spi_delay.patch new file mode 100644 index 0000000..fc1b40c --- /dev/null +++ b/target/linux/generic/patches-4.1/861-04_spi_gpio_implement_spi_delay.patch @@ -0,0 +1,58 @@ +Implement the SPI-GPIO delay function for busses that need speed limitation. + +--mb + + + +--- a/drivers/spi/spi-gpio.c ++++ b/drivers/spi/spi-gpio.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -69,6 +70,7 @@ struct spi_gpio { + * #define SPI_MOSI_GPIO 120 + * #define SPI_SCK_GPIO 121 + * #define SPI_N_CHIPSEL 4 ++ * #undef NEED_SPIDELAY + * #include "spi-gpio.c" + */ + +@@ -76,6 +78,7 @@ struct spi_gpio { + #define DRIVER_NAME "spi_gpio" + + #define GENERIC_BITBANG /* vs tight inlines */ ++#define NEED_SPIDELAY 1 + + /* all functions referencing these symbols must define pdata */ + #define SPI_MISO_GPIO ((pdata)->miso) +@@ -126,12 +129,20 @@ static inline int getmiso(const struct s + #undef pdata + + /* +- * NOTE: this clocks "as fast as we can". It "should" be a function of the +- * requested device clock. Software overhead means we usually have trouble +- * reaching even one Mbit/sec (except when we can inline bitops), so for now +- * we'll just assume we never need additional per-bit slowdowns. ++ * NOTE: to clock "as fast as we can", set spi_device.max_speed_hz ++ * and spi_transfer.speed_hz to 0. ++ * Otherwise this is a function of the requested device clock. ++ * Software overhead means we usually have trouble ++ * reaching even one Mbit/sec (except when we can inline bitops). So on small ++ * embedded devices with fast SPI slaves you usually don't need a delay. + */ +-#define spidelay(nsecs) do {} while (0) ++static inline void spidelay(unsigned nsecs) ++{ ++#ifdef NEED_SPIDELAY ++ if (unlikely(nsecs)) ++ ndelay(nsecs); ++#endif /* NEED_SPIDELAY */ ++} + + #include "spi-bitbang-txrx.h" + diff --git a/target/linux/generic/patches-4.1/862-gpio_spi_driver.patch b/target/linux/generic/patches-4.1/862-gpio_spi_driver.patch new file mode 100644 index 0000000..be05938 --- /dev/null +++ b/target/linux/generic/patches-4.1/862-gpio_spi_driver.patch @@ -0,0 +1,373 @@ +THIS CODE IS DEPRECATED. + +Please use the new mainline SPI-GPIO driver, as of 2.6.29. + +--mb + + + +--- + drivers/spi/Kconfig | 9 + + drivers/spi/Makefile | 1 + drivers/spi/spi_gpio_old.c | 251 +++++++++++++++++++++++++++++++++++++++ + include/linux/spi/spi_gpio_old.h | 73 +++++++++++ + 4 files changed, 334 insertions(+) + +--- /dev/null ++++ b/include/linux/spi/spi_gpio_old.h +@@ -0,0 +1,73 @@ ++/* ++ * spi_gpio interface to platform code ++ * ++ * Copyright (c) 2008 Piotr Skamruk ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef _LINUX_SPI_SPI_GPIO ++#define _LINUX_SPI_SPI_GPIO ++ ++#include ++#include ++ ++ ++/** ++ * struct spi_gpio_platform_data - Data definitions for a SPI-GPIO device. ++ * ++ * This structure holds information about a GPIO-based SPI device. ++ * ++ * @pin_clk: The GPIO pin number of the CLOCK pin. ++ * ++ * @pin_miso: The GPIO pin number of the MISO pin. ++ * ++ * @pin_mosi: The GPIO pin number of the MOSI pin. ++ * ++ * @pin_cs: The GPIO pin number of the CHIPSELECT pin. ++ * ++ * @cs_activelow: If true, the chip is selected when the CS line is low. ++ * ++ * @no_spi_delay: If true, no delay is done in the lowlevel bitbanging. ++ * Note that doing no delay is not standards compliant, ++ * but it might be needed to speed up transfers on some ++ * slow embedded machines. ++ * ++ * @boardinfo_setup: This callback is called after the ++ * SPI master device was registered, but before the ++ * device is registered. ++ * @boardinfo_setup_data: Data argument passed to boardinfo_setup(). ++ */ ++struct spi_gpio_platform_data { ++ unsigned int pin_clk; ++ unsigned int pin_miso; ++ unsigned int pin_mosi; ++ unsigned int pin_cs; ++ bool cs_activelow; ++ bool no_spi_delay; ++ int (*boardinfo_setup)(struct spi_board_info *bi, ++ struct spi_master *master, ++ void *data); ++ void *boardinfo_setup_data; ++}; ++ ++/** ++ * SPI_GPIO_PLATDEV_NAME - The platform device name string. ++ * ++ * The name string that has to be used for platform_device_alloc ++ * when allocating a spi-gpio device. ++ */ ++#define SPI_GPIO_PLATDEV_NAME "spi-gpio" ++ ++/** ++ * spi_gpio_next_id - Get another platform device ID number. ++ * ++ * This returns the next platform device ID number that has to be used ++ * for platform_device_alloc. The ID is opaque and should not be used for ++ * anything else. ++ */ ++int spi_gpio_next_id(void); ++ ++#endif /* _LINUX_SPI_SPI_GPIO */ +--- /dev/null ++++ b/drivers/spi/spi_gpio_old.c +@@ -0,0 +1,251 @@ ++/* ++ * Bitbanging SPI bus driver using GPIO API ++ * ++ * Copyright (c) 2008 Piotr Skamruk ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * based on spi_s3c2410_gpio.c ++ * Copyright (c) 2006 Ben Dooks ++ * Copyright (c) 2006 Simtec Electronics ++ * and on i2c-gpio.c ++ * Copyright (C) 2007 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++struct spi_gpio { ++ struct spi_bitbang bitbang; ++ struct spi_gpio_platform_data *info; ++ struct platform_device *pdev; ++ struct spi_board_info bi; ++}; ++ ++ ++static inline struct spi_gpio *spidev_to_sg(struct spi_device *dev) ++{ ++ return dev->controller_data; ++} ++ ++static inline void setsck(struct spi_device *dev, int val) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ gpio_set_value(sp->info->pin_clk, val ? 1 : 0); ++} ++ ++static inline void setmosi(struct spi_device *dev, int val) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ gpio_set_value(sp->info->pin_mosi, val ? 1 : 0); ++} ++ ++static inline u32 getmiso(struct spi_device *dev) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ return gpio_get_value(sp->info->pin_miso) ? 1 : 0; ++} ++ ++static inline void do_spidelay(struct spi_device *dev, unsigned nsecs) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ ++ if (!sp->info->no_spi_delay) ++ ndelay(nsecs); ++} ++ ++#define spidelay(nsecs) do { \ ++ /* Steal the spi_device pointer from our caller. \ ++ * The bitbang-API should probably get fixed here... */ \ ++ do_spidelay(spi, nsecs); \ ++ } while (0) ++ ++#define EXPAND_BITBANG_TXRX ++#include "spi-bitbang-txrx.h" ++ ++static u32 spi_gpio_txrx_mode0(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode1(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode2(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode3(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); ++} ++ ++static void spi_gpio_chipselect(struct spi_device *dev, int on) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ ++ if (sp->info->cs_activelow) ++ on = !on; ++ gpio_set_value(sp->info->pin_cs, on ? 1 : 0); ++} ++ ++static int spi_gpio_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct spi_gpio_platform_data *pdata; ++ struct spi_gpio *sp; ++ struct spi_device *spidev; ++ int err; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -ENXIO; ++ ++ err = -ENOMEM; ++ master = spi_alloc_master(&pdev->dev, sizeof(struct spi_gpio)); ++ if (!master) ++ goto err_alloc_master; ++ ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); ++ sp->info = pdata; ++ ++ err = gpio_request(pdata->pin_clk, "spi_clock"); ++ if (err) ++ goto err_request_clk; ++ err = gpio_request(pdata->pin_mosi, "spi_mosi"); ++ if (err) ++ goto err_request_mosi; ++ err = gpio_request(pdata->pin_miso, "spi_miso"); ++ if (err) ++ goto err_request_miso; ++ err = gpio_request(pdata->pin_cs, "spi_cs"); ++ if (err) ++ goto err_request_cs; ++ ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.master->bus_num = -1; ++ sp->bitbang.master->num_chipselect = 1; ++ sp->bitbang.chipselect = spi_gpio_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_txrx_mode0; ++ sp->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_txrx_mode1; ++ sp->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_txrx_mode2; ++ sp->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_txrx_mode3; ++ ++ gpio_direction_output(pdata->pin_clk, 0); ++ gpio_direction_output(pdata->pin_mosi, 0); ++ gpio_direction_output(pdata->pin_cs, ++ pdata->cs_activelow ? 1 : 0); ++ gpio_direction_input(pdata->pin_miso); ++ ++ err = spi_bitbang_start(&sp->bitbang); ++ if (err) ++ goto err_no_bitbang; ++ err = pdata->boardinfo_setup(&sp->bi, master, ++ pdata->boardinfo_setup_data); ++ if (err) ++ goto err_bi_setup; ++ sp->bi.controller_data = sp; ++ spidev = spi_new_device(master, &sp->bi); ++ if (!spidev) ++ goto err_new_dev; ++ ++ return 0; ++ ++err_new_dev: ++err_bi_setup: ++ spi_bitbang_stop(&sp->bitbang); ++err_no_bitbang: ++ spi_master_put(sp->bitbang.master); ++ gpio_free(pdata->pin_cs); ++err_request_cs: ++ gpio_free(pdata->pin_miso); ++err_request_miso: ++ gpio_free(pdata->pin_mosi); ++err_request_mosi: ++ gpio_free(pdata->pin_clk); ++err_request_clk: ++ kfree(master); ++ ++err_alloc_master: ++ return err; ++} ++ ++static int spi_gpio_remove(struct platform_device *pdev) ++{ ++ struct spi_gpio *sp; ++ struct spi_gpio_platform_data *pdata; ++ ++ pdata = pdev->dev.platform_data; ++ sp = platform_get_drvdata(pdev); ++ ++ gpio_free(pdata->pin_clk); ++ gpio_free(pdata->pin_mosi); ++ gpio_free(pdata->pin_miso); ++ gpio_free(pdata->pin_cs); ++ spi_bitbang_stop(&sp->bitbang); ++ spi_master_put(sp->bitbang.master); ++ ++ return 0; ++} ++ ++static struct platform_driver spi_gpio_driver = { ++ .driver = { ++ .name = SPI_GPIO_PLATDEV_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = spi_gpio_probe, ++ .remove = spi_gpio_remove, ++}; ++ ++int spi_gpio_next_id(void) ++{ ++ static atomic_t counter = ATOMIC_INIT(-1); ++ ++ return atomic_inc_return(&counter); ++} ++EXPORT_SYMBOL(spi_gpio_next_id); ++ ++static int __init spi_gpio_init(void) ++{ ++ int err; ++ ++ err = platform_driver_register(&spi_gpio_driver); ++ if (err) ++ printk(KERN_ERR "spi-gpio: register failed: %d\n", err); ++ ++ return err; ++} ++module_init(spi_gpio_init); ++ ++static void __exit spi_gpio_exit(void) ++{ ++ platform_driver_unregister(&spi_gpio_driver); ++} ++module_exit(spi_gpio_exit); ++ ++MODULE_AUTHOR("Piot Skamruk "); ++MODULE_AUTHOR("Michael Buesch"); ++MODULE_DESCRIPTION("Platform independent GPIO bitbanging SPI driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -242,6 +242,15 @@ config SPI_IMG_SPFI + This enables support for the SPFI master controller found on + IMG SoCs. + ++config SPI_GPIO_OLD ++ tristate "Old GPIO API based bitbanging SPI controller (DEPRECATED)" ++ depends on SPI_MASTER && GPIOLIB ++ select SPI_BITBANG ++ help ++ This code is deprecated. Please use the new mainline SPI-GPIO driver. ++ ++ If unsure, say N. ++ + config SPI_IMX + tristate "Freescale i.MX SPI controllers" + depends on ARCH_MXC || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -41,6 +41,7 @@ obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-li + obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o + obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o + obj-$(CONFIG_SPI_GPIO) += spi-gpio.o ++obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o + obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o + obj-$(CONFIG_SPI_IMX) += spi-imx.o + obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o diff --git a/target/linux/generic/patches-4.1/863-gpiommc.patch b/target/linux/generic/patches-4.1/863-gpiommc.patch new file mode 100644 index 0000000..bd3cc84 --- /dev/null +++ b/target/linux/generic/patches-4.1/863-gpiommc.patch @@ -0,0 +1,844 @@ +--- /dev/null ++++ b/drivers/mmc/host/gpiommc.c +@@ -0,0 +1,609 @@ ++/* ++ * Driver an MMC/SD card on a bitbanging GPIO SPI bus. ++ * This module hooks up the mmc_spi and spi_gpio modules and also ++ * provides a configfs interface. ++ * ++ * Copyright 2008 Michael Buesch ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#define PFX "gpio-mmc: " ++ ++ ++struct gpiommc_device { ++ struct platform_device *pdev; ++ struct platform_device *spi_pdev; ++ struct spi_board_info boardinfo; ++}; ++ ++ ++MODULE_DESCRIPTION("GPIO based MMC driver"); ++MODULE_AUTHOR("Michael Buesch"); ++MODULE_LICENSE("GPL"); ++ ++ ++static int gpiommc_boardinfo_setup(struct spi_board_info *bi, ++ struct spi_master *master, ++ void *data) ++{ ++ struct gpiommc_device *d = data; ++ struct gpiommc_platform_data *pdata = d->pdev->dev.platform_data; ++ ++ /* Bind the SPI master to the MMC-SPI host driver. */ ++ strlcpy(bi->modalias, "mmc_spi", sizeof(bi->modalias)); ++ ++ bi->max_speed_hz = pdata->max_bus_speed; ++ bi->bus_num = master->bus_num; ++ bi->mode = pdata->mode; ++ ++ return 0; ++} ++ ++static int gpiommc_probe(struct platform_device *pdev) ++{ ++ struct gpiommc_platform_data *mmc_pdata = pdev->dev.platform_data; ++ struct spi_gpio_platform_data spi_pdata; ++ struct gpiommc_device *d; ++ int err; ++ ++ err = -ENXIO; ++ if (!mmc_pdata) ++ goto error; ++ ++#ifdef CONFIG_MMC_SPI_MODULE ++ err = request_module("mmc_spi"); ++ if (err) { ++ printk(KERN_WARNING PFX ++ "Failed to request mmc_spi module.\n"); ++ } ++#endif /* CONFIG_MMC_SPI_MODULE */ ++ ++ /* Allocate the GPIO-MMC device */ ++ err = -ENOMEM; ++ d = kzalloc(sizeof(*d), GFP_KERNEL); ++ if (!d) ++ goto error; ++ d->pdev = pdev; ++ ++ /* Create the SPI-GPIO device */ ++ d->spi_pdev = platform_device_alloc(SPI_GPIO_PLATDEV_NAME, ++ spi_gpio_next_id()); ++ if (!d->spi_pdev) ++ goto err_free_d; ++ ++ memset(&spi_pdata, 0, sizeof(spi_pdata)); ++ spi_pdata.pin_clk = mmc_pdata->pins.gpio_clk; ++ spi_pdata.pin_miso = mmc_pdata->pins.gpio_do; ++ spi_pdata.pin_mosi = mmc_pdata->pins.gpio_di; ++ spi_pdata.pin_cs = mmc_pdata->pins.gpio_cs; ++ spi_pdata.cs_activelow = mmc_pdata->pins.cs_activelow; ++ spi_pdata.no_spi_delay = mmc_pdata->no_spi_delay; ++ spi_pdata.boardinfo_setup = gpiommc_boardinfo_setup; ++ spi_pdata.boardinfo_setup_data = d; ++ ++ err = platform_device_add_data(d->spi_pdev, &spi_pdata, ++ sizeof(spi_pdata)); ++ if (err) ++ goto err_free_pdev; ++ err = platform_device_add(d->spi_pdev); ++ if (err) ++ goto err_free_pdata; ++ platform_set_drvdata(pdev, d); ++ ++ printk(KERN_INFO PFX "MMC-Card \"%s\" " ++ "attached to GPIO pins di=%u, do=%u, clk=%u, cs=%u\n", ++ mmc_pdata->name, mmc_pdata->pins.gpio_di, ++ mmc_pdata->pins.gpio_do, ++ mmc_pdata->pins.gpio_clk, ++ mmc_pdata->pins.gpio_cs); ++ ++ return 0; ++ ++err_free_pdata: ++ kfree(d->spi_pdev->dev.platform_data); ++ d->spi_pdev->dev.platform_data = NULL; ++err_free_pdev: ++ platform_device_put(d->spi_pdev); ++err_free_d: ++ kfree(d); ++error: ++ return err; ++} ++ ++static int gpiommc_remove(struct platform_device *pdev) ++{ ++ struct gpiommc_device *d = platform_get_drvdata(pdev); ++ struct gpiommc_platform_data *pdata = d->pdev->dev.platform_data; ++ ++ platform_device_unregister(d->spi_pdev); ++ printk(KERN_INFO PFX "GPIO based MMC-Card \"%s\" removed\n", ++ pdata->name); ++ platform_device_put(d->spi_pdev); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ ++/* A device that was created through configfs */ ++struct gpiommc_configfs_device { ++ struct config_item item; ++ /* The platform device, after registration. */ ++ struct platform_device *pdev; ++ /* The configuration */ ++ struct gpiommc_platform_data pdata; ++}; ++ ++#define GPIO_INVALID -1 ++ ++static inline bool gpiommc_is_registered(struct gpiommc_configfs_device *dev) ++{ ++ return (dev->pdev != NULL); ++} ++ ++static inline struct gpiommc_configfs_device *ci_to_gpiommc(struct config_item *item) ++{ ++ return item ? container_of(item, struct gpiommc_configfs_device, item) : NULL; ++} ++ ++static struct configfs_attribute gpiommc_attr_DI = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_data_in", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_DO = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_data_out", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CLK = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_clock", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CS = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_chipselect", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CS_activelow = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_chipselect_activelow", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_spimode = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "spi_mode", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_spidelay = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "spi_delay", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_max_bus_speed = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "max_bus_speed", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_register = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "register", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute *gpiommc_config_attrs[] = { ++ &gpiommc_attr_DI, ++ &gpiommc_attr_DO, ++ &gpiommc_attr_CLK, ++ &gpiommc_attr_CS, ++ &gpiommc_attr_CS_activelow, ++ &gpiommc_attr_spimode, ++ &gpiommc_attr_spidelay, ++ &gpiommc_attr_max_bus_speed, ++ &gpiommc_attr_register, ++ NULL, ++}; ++ ++static ssize_t gpiommc_config_attr_show(struct config_item *item, ++ struct configfs_attribute *attr, ++ char *page) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ssize_t count = 0; ++ unsigned int gpio; ++ int err = 0; ++ ++ if (attr == &gpiommc_attr_DI) { ++ gpio = dev->pdata.pins.gpio_di; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_DO) { ++ gpio = dev->pdata.pins.gpio_do; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CLK) { ++ gpio = dev->pdata.pins.gpio_clk; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS) { ++ gpio = dev->pdata.pins.gpio_cs; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS_activelow) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.pins.cs_activelow); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spimode) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.mode); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spidelay) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ !dev->pdata.no_spi_delay); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_max_bus_speed) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.max_bus_speed); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_register) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ gpiommc_is_registered(dev)); ++ goto out; ++ } ++ WARN_ON(1); ++ err = -ENOSYS; ++out: ++ return err ? err : count; ++} ++ ++static int gpiommc_do_register(struct gpiommc_configfs_device *dev, ++ const char *name) ++{ ++ int err; ++ ++ if (gpiommc_is_registered(dev)) ++ return 0; ++ ++ if (!gpio_is_valid(dev->pdata.pins.gpio_di) || ++ !gpio_is_valid(dev->pdata.pins.gpio_do) || ++ !gpio_is_valid(dev->pdata.pins.gpio_clk) || ++ !gpio_is_valid(dev->pdata.pins.gpio_cs)) { ++ printk(KERN_ERR PFX ++ "configfs: Invalid GPIO pin number(s)\n"); ++ return -EINVAL; ++ } ++ ++ strlcpy(dev->pdata.name, name, ++ sizeof(dev->pdata.name)); ++ ++ dev->pdev = platform_device_alloc(GPIOMMC_PLATDEV_NAME, ++ gpiommc_next_id()); ++ if (!dev->pdev) ++ return -ENOMEM; ++ err = platform_device_add_data(dev->pdev, &dev->pdata, ++ sizeof(dev->pdata)); ++ if (err) { ++ platform_device_put(dev->pdev); ++ return err; ++ } ++ err = platform_device_add(dev->pdev); ++ if (err) { ++ platform_device_put(dev->pdev); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void gpiommc_do_unregister(struct gpiommc_configfs_device *dev) ++{ ++ if (!gpiommc_is_registered(dev)) ++ return; ++ ++ platform_device_unregister(dev->pdev); ++ dev->pdev = NULL; ++} ++ ++static ssize_t gpiommc_config_attr_store(struct config_item *item, ++ struct configfs_attribute *attr, ++ const char *page, size_t count) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ int err = -EINVAL; ++ unsigned long data; ++ ++ if (attr == &gpiommc_attr_register) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data == 1) ++ err = gpiommc_do_register(dev, item->ci_name); ++ if (data == 0) { ++ gpiommc_do_unregister(dev); ++ err = 0; ++ } ++ goto out; ++ } ++ ++ if (gpiommc_is_registered(dev)) { ++ /* The rest of the config parameters can only be set ++ * as long as the device is not registered, yet. */ ++ err = -EBUSY; ++ goto out; ++ } ++ ++ if (attr == &gpiommc_attr_DI) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_di = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_DO) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_do = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CLK) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_clk = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_cs = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS_activelow) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data != 0 && data != 1) ++ goto out; ++ dev->pdata.pins.cs_activelow = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spimode) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ switch (data) { ++ case 0: ++ dev->pdata.mode = SPI_MODE_0; ++ break; ++ case 1: ++ dev->pdata.mode = SPI_MODE_1; ++ break; ++ case 2: ++ dev->pdata.mode = SPI_MODE_2; ++ break; ++ case 3: ++ dev->pdata.mode = SPI_MODE_3; ++ break; ++ default: ++ goto out; ++ } ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spidelay) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data != 0 && data != 1) ++ goto out; ++ dev->pdata.no_spi_delay = !data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_max_bus_speed) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data > UINT_MAX) ++ goto out; ++ dev->pdata.max_bus_speed = data; ++ err = 0; ++ goto out; ++ } ++ WARN_ON(1); ++ err = -ENOSYS; ++out: ++ return err ? err : count; ++} ++ ++static void gpiommc_config_item_release(struct config_item *item) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ++ kfree(dev); ++} ++ ++static struct configfs_item_operations gpiommc_config_item_ops = { ++ .release = gpiommc_config_item_release, ++ .show_attribute = gpiommc_config_attr_show, ++ .store_attribute = gpiommc_config_attr_store, ++}; ++ ++static struct config_item_type gpiommc_dev_ci_type = { ++ .ct_item_ops = &gpiommc_config_item_ops, ++ .ct_attrs = gpiommc_config_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *gpiommc_make_item(struct config_group *group, ++ const char *name) ++{ ++ struct gpiommc_configfs_device *dev; ++ ++ if (strlen(name) > GPIOMMC_MAX_NAMELEN) { ++ printk(KERN_ERR PFX "configfs: device name too long\n"); ++ return NULL; ++ } ++ ++ dev = kzalloc(sizeof(*dev), GFP_KERNEL); ++ if (!dev) ++ return NULL; ++ ++ config_item_init_type_name(&dev->item, name, ++ &gpiommc_dev_ci_type); ++ ++ /* Assign default configuration */ ++ dev->pdata.pins.gpio_di = GPIO_INVALID; ++ dev->pdata.pins.gpio_do = GPIO_INVALID; ++ dev->pdata.pins.gpio_clk = GPIO_INVALID; ++ dev->pdata.pins.gpio_cs = GPIO_INVALID; ++ dev->pdata.pins.cs_activelow = 1; ++ dev->pdata.mode = SPI_MODE_0; ++ dev->pdata.no_spi_delay = 0; ++ dev->pdata.max_bus_speed = 5000000; /* 5 MHz */ ++ ++ return &(dev->item); ++} ++ ++static void gpiommc_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ++ gpiommc_do_unregister(dev); ++ kfree(dev); ++} ++ ++static struct configfs_group_operations gpiommc_ct_group_ops = { ++ .make_item = gpiommc_make_item, ++ .drop_item = gpiommc_drop_item, ++}; ++ ++static struct config_item_type gpiommc_ci_type = { ++ .ct_group_ops = &gpiommc_ct_group_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_subsystem gpiommc_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = GPIOMMC_PLATDEV_NAME, ++ .ci_type = &gpiommc_ci_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(gpiommc_subsys.su_mutex), ++}; ++ ++#endif /* CONFIG_GPIOMMC_CONFIGFS */ ++ ++static struct platform_driver gpiommc_plat_driver = { ++ .probe = gpiommc_probe, ++ .remove = gpiommc_remove, ++ .driver = { ++ .name = GPIOMMC_PLATDEV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int gpiommc_next_id(void) ++{ ++ static atomic_t counter = ATOMIC_INIT(-1); ++ ++ return atomic_inc_return(&counter); ++} ++EXPORT_SYMBOL(gpiommc_next_id); ++ ++static int __init gpiommc_modinit(void) ++{ ++ int err; ++ ++ err = platform_driver_register(&gpiommc_plat_driver); ++ if (err) ++ return err; ++ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ config_group_init(&gpiommc_subsys.su_group); ++ err = configfs_register_subsystem(&gpiommc_subsys); ++ if (err) { ++ platform_driver_unregister(&gpiommc_plat_driver); ++ return err; ++ } ++#endif /* CONFIG_GPIOMMC_CONFIGFS */ ++ ++ return 0; ++} ++module_init(gpiommc_modinit); ++ ++static void __exit gpiommc_modexit(void) ++{ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ configfs_unregister_subsystem(&gpiommc_subsys); ++#endif ++ platform_driver_unregister(&gpiommc_plat_driver); ++} ++module_exit(gpiommc_modexit); +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -556,6 +556,31 @@ config MMC_SDHI + This provides support for the SDHI SD/SDIO controller found in + SuperH and ARM SH-Mobile SoCs + ++config GPIOMMC ++ tristate "MMC/SD over GPIO-based SPI" ++ depends on MMC && MMC_SPI && SPI_GPIO_OLD ++ help ++ This driver hooks up the mmc_spi and spi_gpio modules so that ++ MMC/SD cards can be used on a GPIO based bus by bitbanging ++ the SPI protocol in software. ++ ++ This driver provides a configfs interface to dynamically create ++ and destroy GPIO-based MMC/SD card devices. It also provides ++ a platform device interface API. ++ See Documentation/gpiommc.txt for details. ++ ++ The module will be called gpiommc. ++ ++ If unsure, say N. ++ ++config GPIOMMC_CONFIGFS ++ bool ++ depends on GPIOMMC && CONFIGFS_FS ++ default y ++ help ++ This option automatically enables configfs support for gpiommc ++ if configfs is available. ++ + config MMC_CB710 + tristate "ENE CB710 MMC/SD Interface support" + depends on PCI +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -40,6 +40,7 @@ tmio_mmc_core-$(subst m,y,$(CONFIG_MMC_S + obj-$(CONFIG_MMC_SDHI) += sh_mobile_sdhi.o + obj-$(CONFIG_MMC_CB710) += cb710-mmc.o + obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o ++obj-$(CONFIG_GPIOMMC) += gpiommc.o + obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o + obj-$(CONFIG_MMC_DW) += dw_mmc.o + obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o +--- /dev/null ++++ b/include/linux/mmc/gpiommc.h +@@ -0,0 +1,71 @@ ++/* ++ * Device driver for MMC/SD cards driven over a GPIO bus. ++ * ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * Licensed under the GNU/GPL version 2. ++ */ ++#ifndef LINUX_GPIOMMC_H_ ++#define LINUX_GPIOMMC_H_ ++ ++#include ++ ++ ++#define GPIOMMC_MAX_NAMELEN 15 ++#define GPIOMMC_MAX_NAMELEN_STR __stringify(GPIOMMC_MAX_NAMELEN) ++ ++/** ++ * struct gpiommc_pins - Hardware pin assignments ++ * ++ * @gpio_di: The GPIO number of the DATA IN pin ++ * @gpio_do: The GPIO number of the DATA OUT pin ++ * @gpio_clk: The GPIO number of the CLOCK pin ++ * @gpio_cs: The GPIO number of the CHIPSELECT pin ++ * @cs_activelow: If true, the chip is considered selected if @gpio_cs is low. ++ */ ++struct gpiommc_pins { ++ unsigned int gpio_di; ++ unsigned int gpio_do; ++ unsigned int gpio_clk; ++ unsigned int gpio_cs; ++ bool cs_activelow; ++}; ++ ++/** ++ * struct gpiommc_platform_data - Platform data for a MMC-over-SPI-GPIO device. ++ * ++ * @name: The unique name string of the device. ++ * @pins: The hardware pin assignments. ++ * @mode: The hardware mode. This is either SPI_MODE_0, ++ * SPI_MODE_1, SPI_MODE_2 or SPI_MODE_3. See the SPI documentation. ++ * @no_spi_delay: Do not use delays in the lowlevel SPI bitbanging code. ++ * This is not standards compliant, but may be required for some ++ * embedded machines to gain reasonable speed. ++ * @max_bus_speed: The maximum speed of the SPI bus, in Hertz. ++ */ ++struct gpiommc_platform_data { ++ char name[GPIOMMC_MAX_NAMELEN + 1]; ++ struct gpiommc_pins pins; ++ u8 mode; ++ bool no_spi_delay; ++ unsigned int max_bus_speed; ++}; ++ ++/** ++ * GPIOMMC_PLATDEV_NAME - The platform device name string. ++ * ++ * The name string that has to be used for platform_device_alloc ++ * when allocating a gpiommc device. ++ */ ++#define GPIOMMC_PLATDEV_NAME "gpiommc" ++ ++/** ++ * gpiommc_next_id - Get another platform device ID number. ++ * ++ * This returns the next platform device ID number that has to be used ++ * for platform_device_alloc. The ID is opaque and should not be used for ++ * anything else. ++ */ ++int gpiommc_next_id(void); ++ ++#endif /* LINUX_GPIOMMC_H_ */ +--- /dev/null ++++ b/Documentation/gpiommc.txt +@@ -0,0 +1,97 @@ ++GPIOMMC - Driver for an MMC/SD card on a bitbanging GPIO SPI bus ++================================================================ ++ ++The gpiommc module hooks up the mmc_spi and spi_gpio modules for running an ++MMC or SD card on GPIO pins. ++ ++Two interfaces for registering a new MMC/SD card device are provided: ++A static platform-device based mechanism and a dynamic configfs based interface. ++ ++ ++Registering devices via platform-device ++======================================= ++ ++The platform-device interface is used for registering MMC/SD devices that are ++part of the hardware platform. This is most useful only for embedded machines ++with MMC/SD devices statically connected to the platform GPIO bus. ++ ++The data structures are declared in . ++ ++To register a new device, define an instance of struct gpiommc_platform_data. ++This structure holds any information about how the device is hooked up to the ++GPIO pins and what hardware modes the device supports. See the docbook-style ++documentation in the header file for more information on the struct fields. ++ ++Then allocate a new instance of a platform device by doing: ++ ++ pdev = platform_device_alloc(GPIOMMC_PLATDEV_NAME, gpiommc_next_id()); ++ ++This will allocate the platform device data structures and hook it up to the ++gpiommc driver. ++Then add the gpiommc_platform_data to the platform device. ++ ++ err = platform_device_add_data(pdev, pdata, sizeof(struct gpiommc_platform_data)); ++ ++You may free the local instance of struct gpiommc_platform_data now. (So the ++struct may be allocated on the stack, too). ++Now simply register the platform device. ++ ++ err = platform_device_add(pdev); ++ ++Done. The gpiommc probe routine will be invoked now and you should see a kernel ++log message for the added device. ++ ++ ++Registering devices via configfs ++================================ ++ ++MMC/SD cards connected via GPIO often are a pretty dynamic thing, as for example ++selfmade hacks for soldering an MMC/SD card to standard GPIO pins on embedded ++hardware are a common situation. ++So we provide a dynamic interface to conveniently handle adding and removing ++devices from userspace, without the need to recompile the kernel. ++ ++The "gpiommc" subdirectory at the configfs mountpoint is used for handling ++the dynamic configuration. ++ ++To create a new device, it must first be allocated with mkdir. ++The following command will allocate a device named "my_mmc": ++ mkdir /config/gpiommc/my_mmc ++ ++There are several configuration files available in the new ++/config/gpiommc/my_mmc/ directory: ++ ++gpio_data_in = The SPI data-IN GPIO pin number. ++gpio_data_out = The SPI data-OUT GPIO pin number. ++gpio_clock = The SPI Clock GPIO pin number. ++gpio_chipselect = The SPI Chipselect GPIO pin number. ++gpio_chipselect_activelow = Boolean. If 0, Chipselect is active-HIGH. ++ If 1, Chipselect is active-LOW. ++spi_mode = The SPI data mode. Can be 0-3. ++spi_delay = Enable all delays in the lowlevel bitbanging. ++max_bus_speed = The maximum SPI bus speed. In Hertz. ++ ++register = Not a configuration parameter. ++ Used to register the configured card ++ with the kernel. ++ ++The device must first get configured and then registered by writing "1" to ++the "register" file. ++The configuration parameters "gpio_data_in", "gpio_data_out", "gpio_clock" ++and "gpio_chipselect" are essential and _must_ be configured before writing ++"1" to the "register" file. The registration will fail, otherwise. ++ ++The default values for the other parameters are: ++gpio_chipselect_activelow = 1 (CS active-LOW) ++spi_mode = 0 (SPI_MODE_0) ++spi_delay = 1 (enabled) ++max_bus_speed = 5000000 (5 Mhz) ++ ++Configuration values can not be changed after registration. To unregister ++the device, write a "0" to the "register" file. The configuration can be ++changed again after unregistering. ++ ++To completely remove the device, simply rmdir the directory ++(/config/gpiommc/my_mmc in this example). ++There's no need to first unregister the device before removing it. That will ++be done automatically. +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -4531,6 +4531,11 @@ T: git git://linuxtv.org/anttip/media_tr + S: Maintained + F: drivers/media/usb/hackrf/ + ++GPIOMMC DRIVER ++P: Michael Buesch ++M: mb@bu3sch.de ++S: Maintained ++ + HARDWARE MONITORING + M: Jean Delvare + M: Guenter Roeck diff --git a/target/linux/generic/patches-4.1/864-gpiommc_configfs_locking.patch b/target/linux/generic/patches-4.1/864-gpiommc_configfs_locking.patch new file mode 100644 index 0000000..92815d9 --- /dev/null +++ b/target/linux/generic/patches-4.1/864-gpiommc_configfs_locking.patch @@ -0,0 +1,58 @@ +The gpiommc configfs context structure needs locking, as configfs +does not lock access between files. + +--- a/drivers/mmc/host/gpiommc.c ++++ b/drivers/mmc/host/gpiommc.c +@@ -144,6 +144,8 @@ struct gpiommc_configfs_device { + struct platform_device *pdev; + /* The configuration */ + struct gpiommc_platform_data pdata; ++ /* Mutex to protect this structure */ ++ struct mutex mutex; + }; + + #define GPIO_INVALID -1 +@@ -234,6 +236,8 @@ static ssize_t gpiommc_config_attr_show( + unsigned int gpio; + int err = 0; + ++ mutex_lock(&dev->mutex); ++ + if (attr == &gpiommc_attr_DI) { + gpio = dev->pdata.pins.gpio_di; + if (gpio == GPIO_INVALID) +@@ -294,6 +298,8 @@ static ssize_t gpiommc_config_attr_show( + WARN_ON(1); + err = -ENOSYS; + out: ++ mutex_unlock(&dev->mutex); ++ + return err ? err : count; + } + +@@ -353,6 +359,8 @@ static ssize_t gpiommc_config_attr_store + int err = -EINVAL; + unsigned long data; + ++ mutex_lock(&dev->mutex); ++ + if (attr == &gpiommc_attr_register) { + err = kstrtoul(page, 10, &data); + if (err) +@@ -478,6 +486,8 @@ static ssize_t gpiommc_config_attr_store + WARN_ON(1); + err = -ENOSYS; + out: ++ mutex_unlock(&dev->mutex); ++ + return err ? err : count; + } + +@@ -514,6 +524,7 @@ static struct config_item *gpiommc_make_ + if (!dev) + return NULL; + ++ mutex_init(&dev->mutex); + config_item_init_type_name(&dev->item, name, + &gpiommc_dev_ci_type); + diff --git a/target/linux/generic/patches-4.1/870-hifn795x_byteswap.patch b/target/linux/generic/patches-4.1/870-hifn795x_byteswap.patch new file mode 100644 index 0000000..3a37c95 --- /dev/null +++ b/target/linux/generic/patches-4.1/870-hifn795x_byteswap.patch @@ -0,0 +1,17 @@ +--- a/drivers/crypto/hifn_795x.c ++++ b/drivers/crypto/hifn_795x.c +@@ -682,12 +682,12 @@ static inline u32 hifn_read_1(struct hif + + static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) + { +- writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); ++ writel(val, dev->bar[0] + reg); + } + + static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) + { +- writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); ++ writel(val, dev->bar[1] + reg); + } + + static void hifn_wait_puc(struct hifn_device *dev) diff --git a/target/linux/generic/patches-4.1/880-gateworks_system_controller.patch b/target/linux/generic/patches-4.1/880-gateworks_system_controller.patch new file mode 100644 index 0000000..2657723 --- /dev/null +++ b/target/linux/generic/patches-4.1/880-gateworks_system_controller.patch @@ -0,0 +1,339 @@ +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -507,6 +507,15 @@ config SENSORS_G762 + This driver can also be built as a module. If so, the module + will be called g762. + ++config SENSORS_GSC ++ tristate "Gateworks System Controller" ++ depends on I2C ++ help ++ If you say yes here you get support for the Gateworks System Controller. ++ ++ This driver can also be built as a module. If so, the module ++ will be called gsc. ++ + config SENSORS_GPIO_FAN + tristate "GPIO fan" + depends on GPIOLIB +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -156,6 +156,7 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l7 + obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o + obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o + obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o ++obj-$(CONFIG_SENSORS_GSC) += gsc.o + + obj-$(CONFIG_PMBUS) += pmbus/ + +--- /dev/null ++++ b/drivers/hwmon/gsc.c +@@ -0,0 +1,308 @@ ++/* ++ * A hwmon driver for the Gateworks System Controller ++ * Copyright (C) 2009 Gateworks Corporation ++ * ++ * Author: Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License, ++ * as published by the Free Software Foundation - version 2. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRV_VERSION "0.2" ++ ++enum chips { gsp }; ++ ++/* AD7418 registers */ ++#define GSP_REG_TEMP_IN 0x00 ++#define GSP_REG_VIN 0x02 ++#define GSP_REG_3P3 0x05 ++#define GSP_REG_BAT 0x08 ++#define GSP_REG_5P0 0x0b ++#define GSP_REG_CORE 0x0e ++#define GSP_REG_CPU1 0x11 ++#define GSP_REG_CPU2 0x14 ++#define GSP_REG_DRAM 0x17 ++#define GSP_REG_EXT_BAT 0x1a ++#define GSP_REG_IO1 0x1d ++#define GSP_REG_IO2 0x20 ++#define GSP_REG_PCIE 0x23 ++#define GSP_REG_CURRENT 0x26 ++#define GSP_FAN_0 0x2C ++#define GSP_FAN_1 0x2E ++#define GSP_FAN_2 0x30 ++#define GSP_FAN_3 0x32 ++#define GSP_FAN_4 0x34 ++#define GSP_FAN_5 0x36 ++ ++struct gsp_sensor_info { ++ const char* name; ++ int reg; ++}; ++ ++static const struct gsp_sensor_info gsp_sensors[] = { ++ {"temp", GSP_REG_TEMP_IN}, ++ {"vin", GSP_REG_VIN}, ++ {"3p3", GSP_REG_3P3}, ++ {"bat", GSP_REG_BAT}, ++ {"5p0", GSP_REG_5P0}, ++ {"core", GSP_REG_CORE}, ++ {"cpu1", GSP_REG_CPU1}, ++ {"cpu2", GSP_REG_CPU2}, ++ {"dram", GSP_REG_DRAM}, ++ {"ext_bat", GSP_REG_EXT_BAT}, ++ {"io1", GSP_REG_IO1}, ++ {"io2", GSP_REG_IO2}, ++ {"pci2", GSP_REG_PCIE}, ++ {"current", GSP_REG_CURRENT}, ++ {"fan_point0", GSP_FAN_0}, ++ {"fan_point1", GSP_FAN_1}, ++ {"fan_point2", GSP_FAN_2}, ++ {"fan_point3", GSP_FAN_3}, ++ {"fan_point4", GSP_FAN_4}, ++ {"fan_point5", GSP_FAN_5}, ++}; ++ ++struct gsp_data { ++ struct device *hwmon_dev; ++ struct attribute_group attrs; ++ enum chips type; ++}; ++ ++static int gsp_probe(struct i2c_client *client, ++ const struct i2c_device_id *id); ++static int gsp_remove(struct i2c_client *client); ++ ++static const struct i2c_device_id gsp_id[] = { ++ { "gsp", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, gsp_id); ++ ++static struct i2c_driver gsp_driver = { ++ .driver = { ++ .name = "gsp", ++ }, ++ .probe = gsp_probe, ++ .remove = gsp_remove, ++ .id_table = gsp_id, ++}; ++ ++/* All registers are word-sized, except for the configuration registers. ++ * AD7418 uses a high-byte first convention. Do NOT use those functions to ++ * access the configuration registers CONF and CONF2, as they are byte-sized. ++ */ ++static inline int gsp_read(struct i2c_client *client, u8 reg) ++{ ++ unsigned int adc = 0; ++ if (reg == GSP_REG_TEMP_IN || reg > GSP_REG_CURRENT) ++ { ++ adc |= i2c_smbus_read_byte_data(client, reg); ++ adc |= i2c_smbus_read_byte_data(client, reg + 1) << 8; ++ return adc; ++ } ++ else ++ { ++ adc |= i2c_smbus_read_byte_data(client, reg); ++ adc |= i2c_smbus_read_byte_data(client, reg + 1) << 8; ++ adc |= i2c_smbus_read_byte_data(client, reg + 2) << 16; ++ return adc; ++ } ++} ++ ++static inline int gsp_write(struct i2c_client *client, u8 reg, u16 value) ++{ ++ i2c_smbus_write_byte_data(client, reg, value & 0xff); ++ i2c_smbus_write_byte_data(client, reg + 1, ((value >> 8) & 0xff)); ++ return 1; ++} ++ ++static ssize_t show_adc(struct device *dev, struct device_attribute *devattr, ++ char *buf) ++{ ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ struct i2c_client *client = to_i2c_client(dev); ++ return sprintf(buf, "%d\n", gsp_read(client, gsp_sensors[attr->index].reg)); ++} ++ ++static ssize_t show_label(struct device *dev, ++ struct device_attribute *devattr, char *buf) ++{ ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ ++ return sprintf(buf, "%s\n", gsp_sensors[attr->index].name); ++} ++ ++static ssize_t store_fan(struct device *dev, ++ struct device_attribute *devattr, const char *buf, size_t count) ++{ ++ u16 val; ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ struct i2c_client *client = to_i2c_client(dev); ++ val = simple_strtoul(buf, NULL, 10); ++ gsp_write(client, gsp_sensors[attr->index].reg, val); ++ return count; ++} ++ ++static SENSOR_DEVICE_ATTR(temp0_input, S_IRUGO, show_adc, NULL, 0); ++static SENSOR_DEVICE_ATTR(temp0_label, S_IRUGO, show_label, NULL, 0); ++ ++static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, show_adc, NULL, 1); ++static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, show_label, NULL, 1); ++static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, show_adc, NULL, 2); ++static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, show_label, NULL, 2); ++static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, show_adc, NULL, 3); ++static SENSOR_DEVICE_ATTR(in2_label, S_IRUGO, show_label, NULL, 3); ++static SENSOR_DEVICE_ATTR(in3_input, S_IRUGO, show_adc, NULL, 4); ++static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 4); ++static SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, show_adc, NULL, 5); ++static SENSOR_DEVICE_ATTR(in4_label, S_IRUGO, show_label, NULL, 5); ++static SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, show_adc, NULL, 6); ++static SENSOR_DEVICE_ATTR(in5_label, S_IRUGO, show_label, NULL, 6); ++static SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, show_adc, NULL, 7); ++static SENSOR_DEVICE_ATTR(in6_label, S_IRUGO, show_label, NULL, 7); ++static SENSOR_DEVICE_ATTR(in7_input, S_IRUGO, show_adc, NULL, 8); ++static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 8); ++static SENSOR_DEVICE_ATTR(in8_input, S_IRUGO, show_adc, NULL, 9); ++static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 9); ++static SENSOR_DEVICE_ATTR(in9_input, S_IRUGO, show_adc, NULL, 10); ++static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 10); ++static SENSOR_DEVICE_ATTR(in10_input, S_IRUGO, show_adc, NULL, 11); ++static SENSOR_DEVICE_ATTR(in10_label, S_IRUGO, show_label, NULL, 11); ++static SENSOR_DEVICE_ATTR(in11_input, S_IRUGO, show_adc, NULL, 12); ++static SENSOR_DEVICE_ATTR(in11_label, S_IRUGO, show_label, NULL, 12); ++static SENSOR_DEVICE_ATTR(in12_input, S_IRUGO, show_adc, NULL, 13); ++static SENSOR_DEVICE_ATTR(in12_label, S_IRUGO, show_label, NULL, 13); ++ ++static SENSOR_DEVICE_ATTR(fan0_point0, S_IRUGO | S_IWUSR, show_adc, store_fan, 14); ++static SENSOR_DEVICE_ATTR(fan0_point1, S_IRUGO | S_IWUSR, show_adc, store_fan, 15); ++static SENSOR_DEVICE_ATTR(fan0_point2, S_IRUGO | S_IWUSR, show_adc, store_fan, 16); ++static SENSOR_DEVICE_ATTR(fan0_point3, S_IRUGO | S_IWUSR, show_adc, store_fan, 17); ++static SENSOR_DEVICE_ATTR(fan0_point4, S_IRUGO | S_IWUSR, show_adc, store_fan, 18); ++static SENSOR_DEVICE_ATTR(fan0_point5, S_IRUGO | S_IWUSR, show_adc, store_fan, 19); ++ ++static struct attribute *gsp_attributes[] = { ++ &sensor_dev_attr_temp0_input.dev_attr.attr, ++ &sensor_dev_attr_in0_input.dev_attr.attr, ++ &sensor_dev_attr_in1_input.dev_attr.attr, ++ &sensor_dev_attr_in2_input.dev_attr.attr, ++ &sensor_dev_attr_in3_input.dev_attr.attr, ++ &sensor_dev_attr_in4_input.dev_attr.attr, ++ &sensor_dev_attr_in5_input.dev_attr.attr, ++ &sensor_dev_attr_in6_input.dev_attr.attr, ++ &sensor_dev_attr_in7_input.dev_attr.attr, ++ &sensor_dev_attr_in8_input.dev_attr.attr, ++ &sensor_dev_attr_in9_input.dev_attr.attr, ++ &sensor_dev_attr_in10_input.dev_attr.attr, ++ &sensor_dev_attr_in11_input.dev_attr.attr, ++ &sensor_dev_attr_in12_input.dev_attr.attr, ++ ++ &sensor_dev_attr_temp0_label.dev_attr.attr, ++ &sensor_dev_attr_in0_label.dev_attr.attr, ++ &sensor_dev_attr_in1_label.dev_attr.attr, ++ &sensor_dev_attr_in2_label.dev_attr.attr, ++ &sensor_dev_attr_in3_label.dev_attr.attr, ++ &sensor_dev_attr_in4_label.dev_attr.attr, ++ &sensor_dev_attr_in5_label.dev_attr.attr, ++ &sensor_dev_attr_in6_label.dev_attr.attr, ++ &sensor_dev_attr_in7_label.dev_attr.attr, ++ &sensor_dev_attr_in8_label.dev_attr.attr, ++ &sensor_dev_attr_in9_label.dev_attr.attr, ++ &sensor_dev_attr_in10_label.dev_attr.attr, ++ &sensor_dev_attr_in11_label.dev_attr.attr, ++ &sensor_dev_attr_in12_label.dev_attr.attr, ++ ++ &sensor_dev_attr_fan0_point0.dev_attr.attr, ++ &sensor_dev_attr_fan0_point1.dev_attr.attr, ++ &sensor_dev_attr_fan0_point2.dev_attr.attr, ++ &sensor_dev_attr_fan0_point3.dev_attr.attr, ++ &sensor_dev_attr_fan0_point4.dev_attr.attr, ++ &sensor_dev_attr_fan0_point5.dev_attr.attr, ++ NULL ++}; ++ ++ ++static int gsp_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct i2c_adapter *adapter = client->adapter; ++ struct gsp_data *data; ++ int err; ++ ++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | ++ I2C_FUNC_SMBUS_WORD_DATA)) { ++ err = -EOPNOTSUPP; ++ goto exit; ++ } ++ ++ if (!(data = kzalloc(sizeof(struct gsp_data), GFP_KERNEL))) { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ++ i2c_set_clientdata(client, data); ++ ++ data->type = id->driver_data; ++ ++ switch (data->type) { ++ case 0: ++ data->attrs.attrs = gsp_attributes; ++ break; ++ } ++ ++ dev_info(&client->dev, "%s chip found\n", client->name); ++ ++ /* Register sysfs hooks */ ++ if ((err = sysfs_create_group(&client->dev.kobj, &data->attrs))) ++ goto exit_free; ++ ++ data->hwmon_dev = hwmon_device_register(&client->dev); ++ if (IS_ERR(data->hwmon_dev)) { ++ err = PTR_ERR(data->hwmon_dev); ++ goto exit_remove; ++ } ++ ++ return 0; ++ ++exit_remove: ++ sysfs_remove_group(&client->dev.kobj, &data->attrs); ++exit_free: ++ kfree(data); ++exit: ++ return err; ++} ++ ++static int gsp_remove(struct i2c_client *client) ++{ ++ struct gsp_data *data = i2c_get_clientdata(client); ++ hwmon_device_unregister(data->hwmon_dev); ++ sysfs_remove_group(&client->dev.kobj, &data->attrs); ++ kfree(data); ++ return 0; ++} ++ ++static int __init gsp_init(void) ++{ ++ return i2c_add_driver(&gsp_driver); ++} ++ ++static void __exit gsp_exit(void) ++{ ++ i2c_del_driver(&gsp_driver); ++} ++ ++module_init(gsp_init); ++module_exit(gsp_exit); ++ ++MODULE_AUTHOR("Chris Lang "); ++MODULE_DESCRIPTION("GSC HWMON driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); ++ diff --git a/target/linux/generic/patches-4.1/890-8250_optional_sysrq.patch b/target/linux/generic/patches-4.1/890-8250_optional_sysrq.patch new file mode 100644 index 0000000..8815e4c --- /dev/null +++ b/target/linux/generic/patches-4.1/890-8250_optional_sysrq.patch @@ -0,0 +1,24 @@ +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -16,7 +16,7 @@ + * membase is an 'ioremapped' cookie. + */ + +-#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) ++#if defined(CONFIG_SERIAL_8250_SYSRQ) && defined(CONFIG_MAGIC_SYSRQ) + #define SUPPORT_SYSRQ + #endif + +--- a/drivers/tty/serial/8250/Kconfig ++++ b/drivers/tty/serial/8250/Kconfig +@@ -91,6 +91,10 @@ config SERIAL_8250_CONSOLE + + If unsure, say N. + ++config SERIAL_8250_SYSRQ ++ bool "Magic sysrq support on 8250/16550 devices" ++ depends on SERIAL_8250_CONSOLE ++ + config SERIAL_8250_GSC + tristate + depends on SERIAL_8250 && GSC diff --git a/target/linux/generic/patches-4.1/900-slab_maxsize.patch b/target/linux/generic/patches-4.1/900-slab_maxsize.patch new file mode 100644 index 0000000..10133f2 --- /dev/null +++ b/target/linux/generic/patches-4.1/900-slab_maxsize.patch @@ -0,0 +1,13 @@ +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -171,8 +171,8 @@ size_t ksize(const void *); + * to do various tricks to work around compiler limitations in order to + * ensure proper constant folding. + */ +-#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 25 ? \ +- (MAX_ORDER + PAGE_SHIFT - 1) : 25) ++#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 17 ? \ ++ (MAX_ORDER + PAGE_SHIFT - 1) : 17) + #define KMALLOC_SHIFT_MAX KMALLOC_SHIFT_HIGH + #ifndef KMALLOC_SHIFT_LOW + #define KMALLOC_SHIFT_LOW 5 diff --git a/target/linux/generic/patches-4.1/901-debloat_sock_diag.patch b/target/linux/generic/patches-4.1/901-debloat_sock_diag.patch new file mode 100644 index 0000000..0716169 --- /dev/null +++ b/target/linux/generic/patches-4.1/901-debloat_sock_diag.patch @@ -0,0 +1,65 @@ +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -89,6 +89,9 @@ source "net/netlabel/Kconfig" + + endif # if INET + ++config SOCK_DIAG ++ bool ++ + config NETWORK_SECMARK + bool "Security Marking" + help +--- a/net/core/Makefile ++++ b/net/core/Makefile +@@ -9,8 +9,9 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core. + + obj-y += dev.o ethtool.o dev_addr_lists.o dst.o netevent.o \ + neighbour.o rtnetlink.o utils.o link_watch.o filter.o \ +- sock_diag.o dev_ioctl.o tso.o ++ dev_ioctl.o tso.o + ++obj-$(CONFIG_SOCK_DIAG) += sock_diag.o + obj-$(CONFIG_XFRM) += flow.o + obj-y += net-sysfs.o + obj-$(CONFIG_PROC_FS) += net-procfs.o +--- a/net/ipv4/Kconfig ++++ b/net/ipv4/Kconfig +@@ -428,6 +428,7 @@ config INET_LRO + + config INET_DIAG + tristate "INET: socket monitoring interface" ++ select SOCK_DIAG + default y + ---help--- + Support for INET (TCP, DCCP, etc) socket monitoring interface used by +--- a/net/unix/Kconfig ++++ b/net/unix/Kconfig +@@ -22,6 +22,7 @@ config UNIX + config UNIX_DIAG + tristate "UNIX: socket monitoring interface" + depends on UNIX ++ select SOCK_DIAG + default n + ---help--- + Support for UNIX socket monitoring interface used by the ss tool. +--- a/net/netlink/Kconfig ++++ b/net/netlink/Kconfig +@@ -13,6 +13,7 @@ config NETLINK_MMAP + + config NETLINK_DIAG + tristate "NETLINK: socket monitoring interface" ++ select SOCK_DIAG + default n + ---help--- + Support for NETLINK socket monitoring interface used by the ss tool. +--- a/net/packet/Kconfig ++++ b/net/packet/Kconfig +@@ -18,6 +18,7 @@ config PACKET + config PACKET_DIAG + tristate "Packet: sockets monitoring interface" + depends on PACKET ++ select SOCK_DIAG + default n + ---help--- + Support for PF_PACKET sockets monitoring interface used by the ss tool. diff --git a/target/linux/generic/patches-4.1/902-debloat_proc.patch b/target/linux/generic/patches-4.1/902-debloat_proc.patch new file mode 100644 index 0000000..8207dad --- /dev/null +++ b/target/linux/generic/patches-4.1/902-debloat_proc.patch @@ -0,0 +1,341 @@ +--- a/fs/locks.c ++++ b/fs/locks.c +@@ -2676,6 +2676,8 @@ static const struct file_operations proc + + static int __init proc_locks_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("locks", 0, NULL, &proc_locks_operations); + return 0; + } +--- a/fs/proc/Kconfig ++++ b/fs/proc/Kconfig +@@ -71,3 +71,8 @@ config PROC_PAGE_MONITOR + /proc/pid/smaps, /proc/pid/clear_refs, /proc/pid/pagemap, + /proc/kpagecount, and /proc/kpageflags. Disabling these + interfaces will reduce the size of the kernel by approximately 4kb. ++ ++config PROC_STRIPPED ++ default n ++ depends on EXPERT ++ bool "Strip non-essential /proc functionality to reduce code size" +--- a/fs/proc/consoles.c ++++ b/fs/proc/consoles.c +@@ -106,6 +106,9 @@ static const struct file_operations proc + + static int __init proc_consoles_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + proc_create("consoles", 0, NULL, &proc_consoles_operations); + return 0; + } +--- a/fs/proc/proc_tty.c ++++ b/fs/proc/proc_tty.c +@@ -143,7 +143,10 @@ static const struct file_operations proc + void proc_tty_register_driver(struct tty_driver *driver) + { + struct proc_dir_entry *ent; +- ++ ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (!driver->driver_name || driver->proc_entry || + !driver->ops->proc_fops) + return; +@@ -160,6 +163,9 @@ void proc_tty_unregister_driver(struct t + { + struct proc_dir_entry *ent; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + ent = driver->proc_entry; + if (!ent) + return; +@@ -174,6 +180,9 @@ void proc_tty_unregister_driver(struct t + */ + void __init proc_tty_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (!proc_mkdir("tty", NULL)) + return; + proc_mkdir("tty/ldisc", NULL); /* Preserved: it's userspace visible */ +--- a/kernel/exec_domain.c ++++ b/kernel/exec_domain.c +@@ -41,6 +41,8 @@ static const struct file_operations exec + + static int __init proc_execdomains_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("execdomains", 0, NULL, &execdomains_proc_fops); + return 0; + } +--- a/kernel/irq/proc.c ++++ b/kernel/irq/proc.c +@@ -327,6 +327,9 @@ void register_irq_proc(unsigned int irq, + static DEFINE_MUTEX(register_lock); + char name [MAX_NAMELEN]; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + if (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip)) + return; + +@@ -376,6 +379,9 @@ void unregister_irq_proc(unsigned int ir + { + char name [MAX_NAMELEN]; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + if (!root_irq_dir || !desc->dir) + return; + #ifdef CONFIG_SMP +@@ -411,6 +417,9 @@ void init_irq_proc(void) + unsigned int irq; + struct irq_desc *desc; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + /* create /proc/irq */ + root_irq_dir = proc_mkdir("irq", NULL); + if (!root_irq_dir) +--- a/kernel/time/timer_list.c ++++ b/kernel/time/timer_list.c +@@ -388,6 +388,8 @@ static int __init init_timer_list_procfs + { + struct proc_dir_entry *pe; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + pe = proc_create("timer_list", 0444, NULL, &timer_list_fops); + if (!pe) + return -ENOMEM; +--- a/mm/vmalloc.c ++++ b/mm/vmalloc.c +@@ -2683,6 +2683,8 @@ static const struct file_operations proc + + static int __init proc_vmalloc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("vmallocinfo", S_IRUSR, NULL, &proc_vmalloc_operations); + return 0; + } +--- a/mm/vmstat.c ++++ b/mm/vmstat.c +@@ -1528,10 +1528,12 @@ static int __init setup_vmstat(void) + cpu_notifier_register_done(); + #endif + #ifdef CONFIG_PROC_FS +- proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations); +- proc_create("pagetypeinfo", S_IRUGO, NULL, &pagetypeinfo_file_ops); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations); ++ proc_create("pagetypeinfo", S_IRUGO, NULL, &pagetypeinfo_file_ops); ++ proc_create("zoneinfo", S_IRUGO, NULL, &proc_zoneinfo_file_operations); ++ } + proc_create("vmstat", S_IRUGO, NULL, &proc_vmstat_file_operations); +- proc_create("zoneinfo", S_IRUGO, NULL, &proc_zoneinfo_file_operations); + #endif + return 0; + } +--- a/net/8021q/vlanproc.c ++++ b/net/8021q/vlanproc.c +@@ -127,6 +127,9 @@ void vlan_proc_cleanup(struct net *net) + { + struct vlan_net *vn = net_generic(net, vlan_net_id); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (vn->proc_vlan_conf) + remove_proc_entry(name_conf, vn->proc_vlan_dir); + +@@ -146,6 +149,9 @@ int __net_init vlan_proc_init(struct net + { + struct vlan_net *vn = net_generic(net, vlan_net_id); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + vn->proc_vlan_dir = proc_net_mkdir(net, name_root, net->proc_net); + if (!vn->proc_vlan_dir) + goto err; +--- a/net/core/sock.c ++++ b/net/core/sock.c +@@ -2971,6 +2971,8 @@ static __net_initdata struct pernet_oper + + static int __init proto_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + return register_pernet_subsys(&proto_net_ops); + } + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -2626,10 +2626,12 @@ static const struct file_operations fib_ + + int __net_init fib_proc_init(struct net *net) + { +- if (!proc_create("fib_trie", S_IRUGO, net->proc_net, &fib_trie_fops)) ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("fib_trie", S_IRUGO, net->proc_net, &fib_trie_fops)) + goto out1; + +- if (!proc_create("fib_triestat", S_IRUGO, net->proc_net, ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("fib_triestat", S_IRUGO, net->proc_net, + &fib_triestat_fops)) + goto out2; + +@@ -2639,17 +2641,21 @@ int __net_init fib_proc_init(struct net + return 0; + + out3: +- remove_proc_entry("fib_triestat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("fib_triestat", net->proc_net); + out2: +- remove_proc_entry("fib_trie", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("fib_trie", net->proc_net); + out1: + return -ENOMEM; + } + + void __net_exit fib_proc_exit(struct net *net) + { +- remove_proc_entry("fib_trie", net->proc_net); +- remove_proc_entry("fib_triestat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ remove_proc_entry("fib_trie", net->proc_net); ++ remove_proc_entry("fib_triestat", net->proc_net); ++ } + remove_proc_entry("route", net->proc_net); + } + +--- a/net/ipv4/proc.c ++++ b/net/ipv4/proc.c +@@ -535,6 +535,9 @@ static __net_initdata struct pernet_oper + + int __init ip_misc_proc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + return register_pernet_subsys(&ip_proc_ops); + } + +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -415,6 +415,9 @@ static struct pernet_operations ip_rt_pr + + static int __init ip_rt_proc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + return register_pernet_subsys(&ip_rt_proc_ops); + } + +--- a/ipc/msg.c ++++ b/ipc/msg.c +@@ -1040,6 +1040,9 @@ void __init msg_init(void) + { + msg_init_ns(&init_ipc_ns); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + ipc_init_proc_interface("sysvipc/msg", + " key msqid perms cbytes qnum lspid lrpid uid gid cuid cgid stime rtime ctime\n", + IPC_MSG_IDS, sysvipc_msg_proc_show); +--- a/ipc/sem.c ++++ b/ipc/sem.c +@@ -191,6 +191,8 @@ void sem_exit_ns(struct ipc_namespace *n + void __init sem_init(void) + { + sem_init_ns(&init_ipc_ns); ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; + ipc_init_proc_interface("sysvipc/sem", + " key semid perms nsems uid gid cuid cgid otime ctime\n", + IPC_SEM_IDS, sysvipc_sem_proc_show); +--- a/ipc/shm.c ++++ b/ipc/shm.c +@@ -118,6 +118,8 @@ pure_initcall(ipc_ns_init); + + void __init shm_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; + ipc_init_proc_interface("sysvipc/shm", + #if BITS_PER_LONG <= 32 + " key shmid perms size cpid lpid nattch uid gid cuid cgid atime dtime ctime rss swap\n", +--- a/ipc/util.c ++++ b/ipc/util.c +@@ -121,6 +121,9 @@ void __init ipc_init_proc_interface(cons + struct proc_dir_entry *pde; + struct ipc_proc_iface *iface; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + iface = kmalloc(sizeof(*iface), GFP_KERNEL); + if (!iface) + return; +--- a/net/core/net-procfs.c ++++ b/net/core/net-procfs.c +@@ -318,10 +318,12 @@ static int __net_init dev_proc_net_init( + + if (!proc_create("dev", S_IRUGO, net->proc_net, &dev_seq_fops)) + goto out; +- if (!proc_create("softnet_stat", S_IRUGO, net->proc_net, ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("softnet_stat", S_IRUGO, net->proc_net, + &softnet_seq_fops)) + goto out_dev; +- if (!proc_create("ptype", S_IRUGO, net->proc_net, &ptype_seq_fops)) ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("ptype", S_IRUGO, net->proc_net, &ptype_seq_fops)) + goto out_softnet; + + if (wext_proc_init(net)) +@@ -330,9 +332,11 @@ static int __net_init dev_proc_net_init( + out: + return rc; + out_ptype: +- remove_proc_entry("ptype", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("ptype", net->proc_net); + out_softnet: +- remove_proc_entry("softnet_stat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("softnet_stat", net->proc_net); + out_dev: + remove_proc_entry("dev", net->proc_net); + goto out; +@@ -342,8 +346,10 @@ static void __net_exit dev_proc_net_exit + { + wext_proc_exit(net); + +- remove_proc_entry("ptype", net->proc_net); +- remove_proc_entry("softnet_stat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ remove_proc_entry("ptype", net->proc_net); ++ remove_proc_entry("softnet_stat", net->proc_net); ++ } + remove_proc_entry("dev", net->proc_net); + } + diff --git a/target/linux/generic/patches-4.1/903-debloat_direct_io.patch b/target/linux/generic/patches-4.1/903-debloat_direct_io.patch new file mode 100644 index 0000000..0bc9040 --- /dev/null +++ b/target/linux/generic/patches-4.1/903-debloat_direct_io.patch @@ -0,0 +1,80 @@ +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -71,6 +71,11 @@ config FILE_LOCKING + for filesystems like NFS and for the flock() system + call. Disabling this option saves about 11k. + ++config DIRECT_IO ++ bool "Enable O_DIRECT support" if EXPERT ++ depends on BLOCK ++ default y ++ + source "fs/notify/Kconfig" + + source "fs/quota/Kconfig" +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -14,7 +14,8 @@ obj-y := open.o read_write.o file_table. + stack.o fs_struct.o statfs.o fs_pin.o nsfs.o + + ifeq ($(CONFIG_BLOCK),y) +-obj-y += buffer.o block_dev.o direct-io.o mpage.o ++obj-y += buffer.o block_dev.o mpage.o ++obj-$(CONFIG_DIRECT_IO) += direct-io.o + else + obj-y += no-block.o + endif +--- a/include/linux/fs.h ++++ b/include/linux/fs.h +@@ -2647,6 +2647,7 @@ enum { + DIO_SKIP_DIO_COUNT = 0x08, + }; + ++#ifdef CONFIG_DIRECT_IO + void dio_end_io(struct bio *bio, int error); + + ssize_t __blockdev_direct_IO(struct kiocb *iocb, struct inode *inode, +@@ -2654,6 +2655,18 @@ ssize_t __blockdev_direct_IO(struct kioc + loff_t offset, get_block_t get_block, + dio_iodone_t end_io, dio_submit_t submit_io, + int flags); ++#else ++static inline void dio_end_io(struct bio *bio, int error) ++{ ++} ++static inline ssize_t __blockdev_direct_IO(struct kiocb *iocb, struct inode *inode, ++ struct block_device *bdev, struct iov_iter *iter, loff_t offset, ++ get_block_t get_block, dio_iodone_t end_io, ++ dio_submit_t submit_io, int flags) ++{ ++ return -EOPNOTSUPP; ++} ++#endif + + static inline ssize_t blockdev_direct_IO(struct kiocb *iocb, + struct inode *inode, +--- a/fs/fcntl.c ++++ b/fs/fcntl.c +@@ -52,8 +52,10 @@ static int setfl(int fd, struct file * f + arg |= O_NONBLOCK; + + if (arg & O_DIRECT) { ++#ifdef CONFIG_DIRECT_IO + if (!filp->f_mapping || !filp->f_mapping->a_ops || + !filp->f_mapping->a_ops->direct_IO) ++#endif + return -EINVAL; + } + +--- a/fs/open.c ++++ b/fs/open.c +@@ -671,7 +671,9 @@ int open_check_o_direct(struct file *f) + { + /* NB: we're sure to have correct a_ops only after f_op->open */ + if (f->f_flags & O_DIRECT) { ++#ifdef CONFIG_DIRECT_IO + if (!f->f_mapping->a_ops || !f->f_mapping->a_ops->direct_IO) ++#endif + return -EINVAL; + } + return 0; diff --git a/target/linux/generic/patches-4.1/910-kobject_uevent.patch b/target/linux/generic/patches-4.1/910-kobject_uevent.patch new file mode 100644 index 0000000..a2c935f --- /dev/null +++ b/target/linux/generic/patches-4.1/910-kobject_uevent.patch @@ -0,0 +1,21 @@ +--- a/lib/kobject_uevent.c ++++ b/lib/kobject_uevent.c +@@ -52,6 +52,18 @@ static const char *kobject_actions[] = { + [KOBJ_OFFLINE] = "offline", + }; + ++u64 uevent_next_seqnum(void) ++{ ++ u64 seq; ++ ++ mutex_lock(&uevent_sock_mutex); ++ seq = ++uevent_seqnum; ++ mutex_unlock(&uevent_sock_mutex); ++ ++ return seq; ++} ++EXPORT_SYMBOL_GPL(uevent_next_seqnum); ++ + /** + * kobject_action_type - translate action string to numeric type + * diff --git a/target/linux/generic/patches-4.1/911-kobject_add_broadcast_uevent.patch b/target/linux/generic/patches-4.1/911-kobject_add_broadcast_uevent.patch new file mode 100644 index 0000000..3afaac1 --- /dev/null +++ b/target/linux/generic/patches-4.1/911-kobject_add_broadcast_uevent.patch @@ -0,0 +1,65 @@ +--- a/include/linux/kobject.h ++++ b/include/linux/kobject.h +@@ -32,6 +32,8 @@ + #define UEVENT_NUM_ENVP 32 /* number of env pointers */ + #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */ + ++struct sk_buff; ++ + #ifdef CONFIG_UEVENT_HELPER + /* path to the userspace helper executed on an event */ + extern char uevent_helper[]; +@@ -221,4 +223,7 @@ int add_uevent_var(struct kobj_uevent_en + int kobject_action_type(const char *buf, size_t count, + enum kobject_action *type); + ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation); ++ + #endif /* _KOBJECT_H_ */ +--- a/lib/kobject_uevent.c ++++ b/lib/kobject_uevent.c +@@ -423,6 +423,43 @@ int add_uevent_var(struct kobj_uevent_en + EXPORT_SYMBOL_GPL(add_uevent_var); + + #if defined(CONFIG_NET) ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation) ++{ ++ struct uevent_sock *ue_sk; ++ int err = 0; ++ ++ /* send netlink message */ ++ mutex_lock(&uevent_sock_mutex); ++ list_for_each_entry(ue_sk, &uevent_sock_list, list) { ++ struct sock *uevent_sock = ue_sk->sk; ++ struct sk_buff *skb2; ++ ++ skb2 = skb_clone(skb, allocation); ++ if (!skb2) ++ break; ++ ++ err = netlink_broadcast(uevent_sock, skb2, pid, group, ++ allocation); ++ if (err) ++ break; ++ } ++ mutex_unlock(&uevent_sock_mutex); ++ ++ kfree_skb(skb); ++ return err; ++} ++#else ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation) ++{ ++ kfree_skb(skb); ++ return 0; ++} ++#endif ++EXPORT_SYMBOL_GPL(broadcast_uevent); ++ ++#if defined(CONFIG_NET) + static int uevent_net_init(struct net *net) + { + struct uevent_sock *ue_sk; diff --git a/target/linux/generic/patches-4.1/921-use_preinit_as_init.patch b/target/linux/generic/patches-4.1/921-use_preinit_as_init.patch new file mode 100644 index 0000000..73da5b3 --- /dev/null +++ b/target/linux/generic/patches-4.1/921-use_preinit_as_init.patch @@ -0,0 +1,12 @@ +--- a/init/main.c ++++ b/init/main.c +@@ -960,7 +960,8 @@ static int __ref kernel_init(void *unuse + panic("Requested init %s failed (error %d).", + execute_command, ret); + } +- if (!try_to_run_init_process("/sbin/init") || ++ if (!try_to_run_init_process("/etc/preinit") || ++ !try_to_run_init_process("/sbin/init") || + !try_to_run_init_process("/etc/init") || + !try_to_run_init_process("/bin/init") || + !try_to_run_init_process("/bin/sh")) diff --git a/target/linux/generic/patches-4.1/922-always-create-console-node-in-initramfs.patch b/target/linux/generic/patches-4.1/922-always-create-console-node-in-initramfs.patch new file mode 100644 index 0000000..988de35 --- /dev/null +++ b/target/linux/generic/patches-4.1/922-always-create-console-node-in-initramfs.patch @@ -0,0 +1,30 @@ +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -59,6 +59,18 @@ default_initramfs() { + EOF + } + ++list_openwrt_initramfs() { ++ : ++} ++ ++openwrt_initramfs() { ++ # make sure that /dev/console exists ++ cat <<-EOF >> ${output} ++ dir /dev 0755 0 0 ++ nod /dev/console 0600 0 0 c 5 1 ++ EOF ++} ++ + filetype() { + local argv1="$1" + +@@ -177,6 +189,8 @@ dir_filelist() { + if [ "$(echo "${dirlist}" | wc -l)" -gt 1 ]; then + ${dep_list}print_mtime "$1" + ++ ${dep_list}openwrt_initramfs ++ + echo "${dirlist}" | \ + while read x; do + ${dep_list}parse ${x} diff --git a/target/linux/generic/patches-4.1/930-crashlog.patch b/target/linux/generic/patches-4.1/930-crashlog.patch new file mode 100644 index 0000000..be0f7d0 --- /dev/null +++ b/target/linux/generic/patches-4.1/930-crashlog.patch @@ -0,0 +1,276 @@ +--- /dev/null ++++ b/include/linux/crashlog.h +@@ -0,0 +1,17 @@ ++#ifndef __CRASHLOG_H ++#define __CRASHLOG_H ++ ++#ifdef CONFIG_CRASHLOG ++void crashlog_init_bootmem(struct bootmem_data *bdata); ++void crashlog_init_memblock(phys_addr_t addr, phys_addr_t size); ++#else ++static inline void crashlog_init_bootmem(struct bootmem_data *bdata) ++{ ++} ++ ++static inline void crashlog_init_memblock(phys_addr_t addr, phys_addr_t size) ++{ ++} ++#endif ++ ++#endif +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1275,6 +1275,10 @@ config RELAY + + If unsure, say N. + ++config CRASHLOG ++ bool "Crash logging" ++ depends on (!NO_BOOTMEM || HAVE_MEMBLOCK) && !(ARM || SPARC || PPC) ++ + config BLK_DEV_INITRD + bool "Initial RAM filesystem and RAM disk (initramfs/initrd) support" + depends on BROKEN || !FRV +--- a/kernel/Makefile ++++ b/kernel/Makefile +@@ -98,6 +98,7 @@ obj-$(CONFIG_CRASH_DUMP) += crash_dump.o + obj-$(CONFIG_JUMP_LABEL) += jump_label.o + obj-$(CONFIG_CONTEXT_TRACKING) += context_tracking.o + obj-$(CONFIG_TORTURE_TEST) += torture.o ++obj-$(CONFIG_CRASHLOG) += crashlog.o + + $(obj)/configs.o: $(obj)/config_data.h + +--- /dev/null ++++ b/kernel/crashlog.c +@@ -0,0 +1,181 @@ ++/* ++ * Crash information logger ++ * Copyright (C) 2010 Felix Fietkau ++ * ++ * Based on ramoops.c ++ * Copyright (C) 2010 Marco Stornelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CRASHLOG_PAGES 4 ++#define CRASHLOG_SIZE (CRASHLOG_PAGES * PAGE_SIZE) ++#define CRASHLOG_MAGIC 0xa1eedead ++ ++/* ++ * Start the log at 1M before the end of RAM, as some boot loaders like ++ * to use the end of the RAM for stack usage and other things ++ * If this fails, fall back to using the last part. ++ */ ++#define CRASHLOG_OFFSET (1024 * 1024) ++ ++struct crashlog_data { ++ u32 magic; ++ u32 len; ++ u8 data[]; ++}; ++ ++static struct debugfs_blob_wrapper crashlog_blob; ++static unsigned long crashlog_addr = 0; ++static struct crashlog_data *crashlog_buf; ++static struct kmsg_dumper dump; ++static bool first = true; ++ ++extern struct list_head *crashlog_modules; ++ ++#ifndef CONFIG_NO_BOOTMEM ++void __init crashlog_init_bootmem(bootmem_data_t *bdata) ++{ ++ unsigned long addr; ++ ++ if (crashlog_addr) ++ return; ++ ++ addr = PFN_PHYS(bdata->node_low_pfn) - CRASHLOG_OFFSET; ++ if (reserve_bootmem(addr, CRASHLOG_SIZE, BOOTMEM_EXCLUSIVE) < 0) { ++ printk("Crashlog failed to allocate RAM at address 0x%lx\n", addr); ++ bdata->node_low_pfn -= CRASHLOG_PAGES; ++ addr = PFN_PHYS(bdata->node_low_pfn); ++ } ++ crashlog_addr = addr; ++} ++#endif ++ ++#ifdef CONFIG_HAVE_MEMBLOCK ++void __meminit crashlog_init_memblock(phys_addr_t addr, phys_addr_t size) ++{ ++ if (crashlog_addr) ++ return; ++ ++ addr += size - CRASHLOG_OFFSET; ++ if (memblock_reserve(addr, CRASHLOG_SIZE)) { ++ printk("Crashlog failed to allocate RAM at address 0x%lx\n", (unsigned long) addr); ++ return; ++ } ++ ++ crashlog_addr = addr; ++} ++#endif ++ ++static void __init crashlog_copy(void) ++{ ++ if (crashlog_buf->magic != CRASHLOG_MAGIC) ++ return; ++ ++ if (!crashlog_buf->len || crashlog_buf->len > ++ CRASHLOG_SIZE - sizeof(*crashlog_buf)) ++ return; ++ ++ crashlog_blob.size = crashlog_buf->len; ++ crashlog_blob.data = kmemdup(crashlog_buf->data, ++ crashlog_buf->len, GFP_KERNEL); ++ ++ debugfs_create_blob("crashlog", 0700, NULL, &crashlog_blob); ++} ++ ++static int get_maxlen(void) ++{ ++ return CRASHLOG_SIZE - sizeof(*crashlog_buf) - crashlog_buf->len; ++} ++ ++static void crashlog_printf(const char *fmt, ...) ++{ ++ va_list args; ++ int len = get_maxlen(); ++ ++ if (!len) ++ return; ++ ++ va_start(args, fmt); ++ crashlog_buf->len += vscnprintf( ++ &crashlog_buf->data[crashlog_buf->len], ++ len, fmt, args); ++ va_end(args); ++} ++ ++static void crashlog_do_dump(struct kmsg_dumper *dumper, ++ enum kmsg_dump_reason reason) ++{ ++ struct timeval tv; ++ struct module *m; ++ char *buf; ++ size_t len; ++ ++ if (!first) ++ crashlog_printf("\n===================================\n"); ++ ++ do_gettimeofday(&tv); ++ crashlog_printf("Time: %lu.%lu\n", ++ (long)tv.tv_sec, (long)tv.tv_usec); ++ ++ if (first) { ++ crashlog_printf("Modules:"); ++ list_for_each_entry(m, crashlog_modules, list) { ++ crashlog_printf("\t%s@%p+%x", m->name, ++ m->module_core, m->core_size, ++ m->module_init, m->init_size); ++ } ++ crashlog_printf("\n"); ++ first = false; ++ } ++ ++ buf = (char *)&crashlog_buf->data[crashlog_buf->len]; ++ ++ kmsg_dump_get_buffer(dumper, true, buf, get_maxlen(), &len); ++ ++ crashlog_buf->len += len; ++} ++ ++ ++int __init crashlog_init_fs(void) ++{ ++ if (!crashlog_addr) ++ return -ENOMEM; ++ ++ crashlog_buf = ioremap(crashlog_addr, CRASHLOG_SIZE); ++ ++ crashlog_copy(); ++ ++ crashlog_buf->magic = CRASHLOG_MAGIC; ++ crashlog_buf->len = 0; ++ ++ dump.max_reason = KMSG_DUMP_OOPS; ++ dump.dump = crashlog_do_dump; ++ kmsg_dump_register(&dump); ++ ++ return 0; ++} ++module_init(crashlog_init_fs); +--- a/mm/bootmem.c ++++ b/mm/bootmem.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -177,6 +178,7 @@ static unsigned long __init free_all_boo + if (!bdata->node_bootmem_map) + return 0; + ++ crashlog_init_bootmem(bdata); + map = bdata->node_bootmem_map; + start = bdata->node_min_pfn; + end = bdata->node_low_pfn; +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -104,6 +104,9 @@ static LIST_HEAD(modules); + #ifdef CONFIG_KGDB_KDB + struct list_head *kdb_modules = &modules; /* kdb needs the list of modules */ + #endif /* CONFIG_KGDB_KDB */ ++#ifdef CONFIG_CRASHLOG ++struct list_head *crashlog_modules = &modules; ++#endif + + #ifdef CONFIG_MODULE_SIG + #ifdef CONFIG_MODULE_SIG_FORCE +--- a/mm/memblock.c ++++ b/mm/memblock.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -477,6 +478,8 @@ static void __init_memblock memblock_ins + memblock_set_region_node(rgn, nid); + type->cnt++; + type->total_size += size; ++ if (type == &memblock.memory && idx == 0) ++ crashlog_init_memblock(base, size); + } + + /** diff --git a/target/linux/generic/patches-4.1/940-ocf_kbuild_integration.patch b/target/linux/generic/patches-4.1/940-ocf_kbuild_integration.patch new file mode 100644 index 0000000..a50cd9c --- /dev/null +++ b/target/linux/generic/patches-4.1/940-ocf_kbuild_integration.patch @@ -0,0 +1,20 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -1526,3 +1526,6 @@ source "drivers/crypto/Kconfig" + source crypto/asymmetric_keys/Kconfig + + endif # if CRYPTO ++ ++source "crypto/ocf/Kconfig" ++ +--- a/crypto/Makefile ++++ b/crypto/Makefile +@@ -103,6 +103,8 @@ obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) + + obj-$(CONFIG_CRYPTO_USER_API_RNG) += algif_rng.o + obj-$(CONFIG_CRYPTO_USER_API_AEAD) += algif_aead.o + ++obj-$(CONFIG_OCF_OCF) += ocf/ ++ + # + # generic algorithms and the async_tx api + # diff --git a/target/linux/generic/patches-4.1/941-ocf_20120127.patch b/target/linux/generic/patches-4.1/941-ocf_20120127.patch new file mode 100644 index 0000000..d5564b3 --- /dev/null +++ b/target/linux/generic/patches-4.1/941-ocf_20120127.patch @@ -0,0 +1,166 @@ +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -139,6 +139,9 @@ + * that might otherwise be identical and have very little entropy + * available to them (particularly common in the embedded world). + * ++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++ * int random_input_wait(void); ++ * + * add_input_randomness() uses the input layer interrupt timing, as well as + * the event type information from the hardware. + * +@@ -152,6 +155,13 @@ + * seek times do not make for good sources of entropy, as their seek + * times are usually fairly consistent. + * ++ * random_input_words() just provides a raw block of entropy to the input ++ * pool, such as from a hardware entropy generator. ++ * ++ * random_input_wait() suspends the caller until such time as the ++ * entropy pool falls below the write threshold, and returns a count of how ++ * much entropy (in bits) is needed to sustain the pool. ++ * + * All of these routines try to estimate how many bits of randomness a + * particular randomness source. They do this by keeping track of the + * first and second order deltas of the event timings. +@@ -938,6 +948,63 @@ void add_disk_randomness(struct gendisk + EXPORT_SYMBOL_GPL(add_disk_randomness); + #endif + ++/* ++ * random_input_words - add bulk entropy to pool ++ * ++ * @buf: buffer to add ++ * @wordcount: number of __u32 words to add ++ * @ent_count: total amount of entropy (in bits) to credit ++ * ++ * this provides bulk input of entropy to the input pool ++ * ++ */ ++void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++{ ++ mix_pool_bytes(&input_pool, buf, wordcount*4); ++ ++ credit_entropy_bits(&input_pool, ent_count); ++ ++ pr_notice("crediting %d bits => %d\n", ++ ent_count, input_pool.entropy_count); ++ /* ++ * Wake up waiting processes if we have enough ++ * entropy. ++ */ ++ if (input_pool.entropy_count >= random_read_wakeup_bits) ++ wake_up_interruptible(&random_read_wait); ++} ++EXPORT_SYMBOL(random_input_words); ++ ++/* ++ * random_input_wait - wait until random needs entropy ++ * ++ * this function sleeps until the /dev/random subsystem actually ++ * needs more entropy, and then return the amount of entropy ++ * that it would be nice to have added to the system. ++ */ ++int random_input_wait(void) ++{ ++ int count; ++ ++ wait_event_interruptible(random_write_wait, ++ input_pool.entropy_count < random_write_wakeup_bits); ++ ++ count = random_write_wakeup_bits - input_pool.entropy_count; ++ ++ /* likely we got woken up due to a signal */ ++ if (count <= 0) count = random_read_wakeup_bits; ++ ++ pr_notice("requesting %d bits from input_wait()er %d<%d\n", ++ count, ++ input_pool.entropy_count, random_write_wakeup_bits); ++ ++ return count; ++} ++EXPORT_SYMBOL(random_input_wait); ++ ++ ++#define EXTRACT_SIZE 10 ++ + /********************************************************************* + * + * Entropy extraction routines +--- a/fs/fcntl.c ++++ b/fs/fcntl.c +@@ -140,6 +140,7 @@ pid_t f_getown(struct file *filp) + read_unlock(&filp->f_owner.lock); + return pid; + } ++EXPORT_SYMBOL(sys_dup); + + static int f_setown_ex(struct file *filp, unsigned long arg) + { +--- a/include/linux/miscdevice.h ++++ b/include/linux/miscdevice.h +@@ -19,6 +19,7 @@ + #define APOLLO_MOUSE_MINOR 7 /* unused */ + #define PC110PAD_MINOR 9 /* unused */ + /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ ++#define CRYPTODEV_MINOR 70 /* /dev/crypto */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +--- a/include/uapi/linux/random.h ++++ b/include/uapi/linux/random.h +@@ -34,6 +34,30 @@ + /* Clear the entropy pool and associated counters. (Superuser only.) */ + #define RNDCLEARPOOL _IO( 'R', 0x06 ) + ++#ifdef CONFIG_FIPS_RNG ++ ++/* Size of seed value - equal to AES blocksize */ ++#define AES_BLOCK_SIZE_BYTES 16 ++#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES ++/* Size of AES key */ ++#define KEY_SIZE_BYTES 16 ++ ++/* ioctl() structure used by FIPS 140-2 Tests */ ++struct rand_fips_test { ++ unsigned char key[KEY_SIZE_BYTES]; /* Input */ ++ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char result[SEED_SIZE_BYTES]; /* Output */ ++}; ++ ++/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ ++#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) ++ ++/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ ++#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) ++ ++#endif /* #ifdef CONFIG_FIPS_RNG */ ++ + struct rand_pool_info { + int entropy_count; + int buf_size; +--- a/include/linux/random.h ++++ b/include/linux/random.h +@@ -13,6 +13,10 @@ extern void add_input_randomness(unsigne + unsigned int value); + extern void add_interrupt_randomness(int irq, int irq_flags); + ++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); ++extern int random_input_wait(void); ++#define HAS_RANDOM_INPUT_WAIT 1 ++ + extern void get_random_bytes(void *buf, int nbytes); + extern void get_random_bytes_arch(void *buf, int nbytes); + void generate_random_uuid(unsigned char uuid_out[16]); +--- a/kernel/pid.c ++++ b/kernel/pid.c +@@ -431,6 +431,7 @@ void transfer_pid(struct task_struct *ol + new->pids[type].pid = old->pids[type].pid; + hlist_replace_rcu(&old->pids[type].node, &new->pids[type].node); + } ++EXPORT_SYMBOL(find_task_by_vpid); + + struct task_struct *pid_task(struct pid *pid, enum pid_type type) + { diff --git a/target/linux/generic/patches-4.1/960-decompress_unlzo_fix.patch b/target/linux/generic/patches-4.1/960-decompress_unlzo_fix.patch new file mode 100644 index 0000000..37e322a --- /dev/null +++ b/target/linux/generic/patches-4.1/960-decompress_unlzo_fix.patch @@ -0,0 +1,23 @@ +--- /dev/null ++++ b/include/linux/decompress/unlzo_mm.h +@@ -0,0 +1,10 @@ ++#ifndef UNLZO_MM_H ++#define UNLZO_MM_H ++ ++#ifdef STATIC ++#define INIT ++#else ++#define INIT __init ++#endif ++ ++#endif +--- a/lib/decompress_unlzo.c ++++ b/lib/decompress_unlzo.c +@@ -39,6 +39,7 @@ + + #include + #include ++#include + #include + + #include diff --git a/target/linux/generic/patches-4.1/970-remove-unsane-filenames-from-deps_initramfs-list.patch b/target/linux/generic/patches-4.1/970-remove-unsane-filenames-from-deps_initramfs-list.patch new file mode 100644 index 0000000..ac13c9e --- /dev/null +++ b/target/linux/generic/patches-4.1/970-remove-unsane-filenames-from-deps_initramfs-list.patch @@ -0,0 +1,29 @@ +--- a/usr/Makefile ++++ b/usr/Makefile +@@ -53,6 +53,8 @@ ifneq ($(wildcard $(obj)/.initramfs_data + include $(obj)/.initramfs_data.cpio.d + endif + ++deps_initramfs_sane := $(foreach v,$(deps_initramfs),$(if $(findstring :,$(v)),,$(v))) ++ + quiet_cmd_initfs = GEN $@ + cmd_initfs = $(initramfs) -o $@ $(ramfs-args) $(ramfs-input) + +@@ -61,14 +63,14 @@ targets := initramfs_data.cpio.gz initra + initramfs_data.cpio.lzo initramfs_data.cpio.lz4 \ + initramfs_data.cpio + # do not try to update files included in initramfs +-$(deps_initramfs): ; ++$(deps_initramfs_sane): ; + +-$(deps_initramfs): klibcdirs ++$(deps_initramfs_sane): klibcdirs + # We rebuild initramfs_data.cpio if: + # 1) Any included file is newer then initramfs_data.cpio + # 2) There are changes in which files are included (added or deleted) + # 3) If gen_init_cpio are newer than initramfs_data.cpio + # 4) arguments to gen_initramfs.sh changes +-$(obj)/initramfs_data.cpio$(suffix_y): $(obj)/gen_init_cpio $(deps_initramfs) klibcdirs ++$(obj)/initramfs_data.cpio$(suffix_y): $(obj)/gen_init_cpio $(deps_initramfs_sane) klibcdirs + $(Q)$(initramfs) -l $(ramfs-input) > $(obj)/.initramfs_data.cpio.d + $(call if_changed,initfs) diff --git a/target/linux/generic/patches-4.1/980-arm_openwrt_machtypes.patch b/target/linux/generic/patches-4.1/980-arm_openwrt_machtypes.patch new file mode 100644 index 0000000..60ca07e --- /dev/null +++ b/target/linux/generic/patches-4.1/980-arm_openwrt_machtypes.patch @@ -0,0 +1,32 @@ +--- a/arch/arm/tools/mach-types ++++ b/arch/arm/tools/mach-types +@@ -1006,3 +1006,29 @@ eco5_bx2 MACH_ECO5_BX2 ECO5_BX2 4572 + eukrea_cpuimx28sd MACH_EUKREA_CPUIMX28SD EUKREA_CPUIMX28SD 4573 + domotab MACH_DOMOTAB DOMOTAB 4574 + pfla03 MACH_PFLA03 PFLA03 4575 ++# ++# Additional mach-types supported by OpenWrt ++# ++wg302v1 MACH_WG302V1 WG302V1 889 ++pronghorn MACH_PRONGHORN PRONGHORN 928 ++pronghorn_metro MACH_PRONGHORNMETRO PRONGHORNMETRO 1040 ++sidewinder MACH_SIDEWINDER SIDEWINDER 1041 ++wrt300nv2 MACH_WRT300NV2 WRT300NV2 1077 ++compex42x MACH_COMPEXWP18 COMPEXWP18 1273 ++goldfish MACH_GOLDFISH GOLDFISH 1441 ++cambria MACH_CAMBRIA CAMBRIA 1468 ++dt2 MACH_DT2 DT2 1514 ++ap1000 MACH_AP1000 AP1000 1543 ++tw2662 MACH_TW2662 TW2662 1658 ++tw5334 MACH_TW5334 TW5334 1664 ++usr8200 MACH_USR8200 USR8200 1762 ++mi424wr MACH_MI424WR MI424WR 1778 ++gw2388 MACH_GW2388 GW2388 2635 ++iconnect MACH_ICONNECT ICONNECT 2870 ++nsb3ast MACH_NSB3AST NSB3AST 2917 ++goflexnet MACH_GOFLEXNET GOFLEXNET 3089 ++nas6210 MACH_NAS6210 NAS6210 3104 ++ns_k330 MACH_NS_K330 NS_K330 3108 ++bcm2708 MACH_BCM2708 BCM2708 3138 ++wn802t MACH_WN802T WN802T 3306 ++nsa310 MACH_NSA310 NSA310 4022 diff --git a/target/linux/generic/patches-4.1/990-gpio_wdt.patch b/target/linux/generic/patches-4.1/990-gpio_wdt.patch new file mode 100644 index 0000000..9f5e7fa --- /dev/null +++ b/target/linux/generic/patches-4.1/990-gpio_wdt.patch @@ -0,0 +1,360 @@ +This generic GPIO watchdog is used on Huawei E970 (brcm47xx) + +Signed-off-by: Mathias Adam + +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1150,6 +1150,15 @@ config WDT_MTX1 + Hardware driver for the MTX-1 boards. This is a watchdog timer that + will reboot the machine after a 100 seconds timer expired. + ++config GPIO_WDT ++ tristate "GPIO Hardware Watchdog" ++ help ++ Hardware driver for GPIO-controlled watchdogs. GPIO pin and ++ toggle interval settings are platform-specific. The driver ++ will stop toggling the GPIO (i.e. machine reboots) after a ++ 100 second timer expired and no process has written to ++ /dev/watchdog during that time. ++ + config PNX833X_WDT + tristate "PNX833x Hardware Watchdog" + depends on SOC_PNX8335 +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -135,6 +135,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt + obj-$(CONFIG_INDYDOG) += indydog.o + obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o + obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o ++obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o +--- /dev/null ++++ b/drivers/watchdog/old_gpio_wdt.c +@@ -0,0 +1,301 @@ ++/* ++ * Driver for GPIO-controlled Hardware Watchdogs. ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * Replaces mtx1_wdt (driver for the MTX-1 Watchdog): ++ * ++ * (C) Copyright 2005 4G Systems , ++ * All Rights Reserved. ++ * http://www.4g-systems.biz ++ * ++ * (C) Copyright 2007 OpenWrt.org, Florian Fainelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Neither Michael Stickel nor 4G Systems admit liability nor provide ++ * warranty for any of this software. This material is provided ++ * "AS-IS" and at no charge. ++ * ++ * (c) Copyright 2005 4G Systems ++ * ++ * Release 0.01. ++ * Author: Michael Stickel michael.stickel@4g-systems.biz ++ * ++ * Release 0.02. ++ * Author: Florian Fainelli florian@openwrt.org ++ * use the Linux watchdog/timer APIs ++ * ++ * Release 0.03. ++ * Author: Mathias Adam ++ * make it a generic gpio watchdog driver ++ * ++ * The Watchdog is configured to reset the MTX-1 ++ * if it is not triggered for 100 seconds. ++ * It should not be triggered more often than 1.6 seconds. ++ * ++ * A timer triggers the watchdog every 5 seconds, until ++ * it is opened for the first time. After the first open ++ * it MUST be triggered every 2..95 seconds. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ticks = 100 * HZ; ++ ++static struct { ++ struct completion stop; ++ spinlock_t lock; ++ int running; ++ struct timer_list timer; ++ int queue; ++ int default_ticks; ++ unsigned long inuse; ++ unsigned gpio; ++ unsigned int gstate; ++ int interval; ++ int first_interval; ++} gpio_wdt_device; ++ ++static void gpio_wdt_trigger(unsigned long unused) ++{ ++ spin_lock(&gpio_wdt_device.lock); ++ if (gpio_wdt_device.running && ticks > 0) ++ ticks -= gpio_wdt_device.interval; ++ ++ /* toggle wdt gpio */ ++ gpio_wdt_device.gstate = !gpio_wdt_device.gstate; ++ gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate); ++ ++ if (gpio_wdt_device.queue && ticks > 0) ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval); ++ else ++ complete(&gpio_wdt_device.stop); ++ spin_unlock(&gpio_wdt_device.lock); ++} ++ ++static void gpio_wdt_reset(void) ++{ ++ ticks = gpio_wdt_device.default_ticks; ++} ++ ++ ++static void gpio_wdt_start(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (!gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 1; ++ gpio_wdt_device.gstate = 1; ++ gpio_set_value(gpio_wdt_device.gpio, 1); ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval); ++ } ++ gpio_wdt_device.running++; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++} ++ ++static int gpio_wdt_stop(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ gpio_wdt_device.gstate = 0; ++ gpio_set_value(gpio_wdt_device.gpio, 0); ++ } ++ ticks = gpio_wdt_device.default_ticks; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++ return 0; ++} ++ ++/* Filesystem functions */ ++ ++static int gpio_wdt_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(0, &gpio_wdt_device.inuse)) ++ return -EBUSY; ++ return nonseekable_open(inode, file); ++} ++ ++ ++static int gpio_wdt_release(struct inode *inode, struct file *file) ++{ ++ clear_bit(0, &gpio_wdt_device.inuse); ++ return 0; ++} ++ ++static long gpio_wdt_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ void __user *argp = (void __user *)arg; ++ int __user *p = (int __user *)argp; ++ unsigned int value; ++ static const struct watchdog_info ident = { ++ .options = WDIOF_CARDRESET, ++ .identity = "GPIO WDT", ++ }; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ if (copy_to_user(argp, &ident, sizeof(ident))) ++ return -EFAULT; ++ break; ++ case WDIOC_GETSTATUS: ++ case WDIOC_GETBOOTSTATUS: ++ put_user(0, p); ++ break; ++ case WDIOC_SETOPTIONS: ++ if (get_user(value, p)) ++ return -EFAULT; ++ if (value & WDIOS_ENABLECARD) ++ gpio_wdt_start(); ++ else if (value & WDIOS_DISABLECARD) ++ gpio_wdt_stop(); ++ else ++ return -EINVAL; ++ return 0; ++ case WDIOC_KEEPALIVE: ++ gpio_wdt_reset(); ++ break; ++ default: ++ return -ENOTTY; ++ } ++ return 0; ++} ++ ++ ++static ssize_t gpio_wdt_write(struct file *file, const char *buf, ++ size_t count, loff_t *ppos) ++{ ++ if (!count) ++ return -EIO; ++ gpio_wdt_reset(); ++ return count; ++} ++ ++static const struct file_operations gpio_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .unlocked_ioctl = gpio_wdt_ioctl, ++ .open = gpio_wdt_open, ++ .write = gpio_wdt_write, ++ .release = gpio_wdt_release, ++}; ++ ++ ++static struct miscdevice gpio_wdt_misc = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &gpio_wdt_fops, ++}; ++ ++ ++static int gpio_wdt_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data; ++ ++ gpio_wdt_device.gpio = gpio_wdt_data->gpio; ++ gpio_wdt_device.interval = gpio_wdt_data->interval; ++ gpio_wdt_device.first_interval = gpio_wdt_data->first_interval; ++ if (gpio_wdt_device.first_interval <= 0) { ++ gpio_wdt_device.first_interval = gpio_wdt_device.interval; ++ } ++ ++ ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt"); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to request gpio"); ++ return ret; ++ } ++ ++ spin_lock_init(&gpio_wdt_device.lock); ++ init_completion(&gpio_wdt_device.stop); ++ gpio_wdt_device.queue = 0; ++ clear_bit(0, &gpio_wdt_device.inuse); ++ setup_timer(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L); ++ gpio_wdt_device.default_ticks = ticks; ++ ++ gpio_wdt_start(); ++ dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n", ++ gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval); ++ return 0; ++} ++ ++static int gpio_wdt_remove(struct platform_device *pdev) ++{ ++ /* FIXME: do we need to lock this test ? */ ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ wait_for_completion(&gpio_wdt_device.stop); ++ } ++ ++ gpio_free(gpio_wdt_device.gpio); ++ misc_deregister(&gpio_wdt_misc); ++ return 0; ++} ++ ++static struct platform_driver gpio_wdt_driver = { ++ .probe = gpio_wdt_probe, ++ .remove = gpio_wdt_remove, ++ .driver.name = "gpio-wdt", ++ .driver.owner = THIS_MODULE, ++}; ++ ++static int __init gpio_wdt_init(void) ++{ ++ return platform_driver_register(&gpio_wdt_driver); ++} ++arch_initcall(gpio_wdt_init); ++ ++/* ++ * We do wdt initialization in two steps: arch_initcall probes the wdt ++ * very early to start pinging the watchdog (misc devices are not yet ++ * available), and later module_init() just registers the misc device. ++ */ ++static int gpio_wdt_init_late(void) ++{ ++ int ret; ++ ++ ret = misc_register(&gpio_wdt_misc); ++ if (ret < 0) { ++ pr_err("GPIO_WDT: failed to register misc device\n"); ++ return ret; ++ } ++ return 0; ++} ++#ifndef MODULE ++module_init(gpio_wdt_init_late); ++#endif ++ ++static void __exit gpio_wdt_exit(void) ++{ ++ platform_driver_unregister(&gpio_wdt_driver); ++} ++module_exit(gpio_wdt_exit); ++ ++MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam"); ++MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:gpio-wdt"); +--- /dev/null ++++ b/include/linux/old_gpio_wdt.h +@@ -0,0 +1,21 @@ ++/* ++ * Definitions for the GPIO watchdog driver ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef _GPIO_WDT_H_ ++#define _GPIO_WDT_H_ ++ ++struct gpio_wdt_platform_data { ++ int gpio; /* GPIO line number */ ++ int interval; /* watchdog reset interval in system ticks */ ++ int first_interval; /* first wd reset interval in system ticks */ ++}; ++ ++#endif /* _GPIO_WDT_H_ */ diff --git a/target/linux/generic/patches-4.1/995-mangle_bootargs.patch b/target/linux/generic/patches-4.1/995-mangle_bootargs.patch new file mode 100644 index 0000000..1062a69 --- /dev/null +++ b/target/linux/generic/patches-4.1/995-mangle_bootargs.patch @@ -0,0 +1,58 @@ +--- a/init/main.c ++++ b/init/main.c +@@ -352,6 +352,29 @@ static inline void setup_nr_cpu_ids(void + static inline void smp_prepare_cpus(unsigned int maxcpus) { } + #endif + ++#ifdef CONFIG_MANGLE_BOOTARGS ++static void __init mangle_bootargs(char *command_line) ++{ ++ char *rootdev; ++ char *rootfs; ++ ++ rootdev = strstr(command_line, "root=/dev/mtdblock"); ++ ++ if (rootdev) ++ strncpy(rootdev, "mangled_rootblock=", 18); ++ ++ rootfs = strstr(command_line, "rootfstype"); ++ ++ if (rootfs) ++ strncpy(rootfs, "mangled_fs", 10); ++ ++} ++#else ++static void __init mangle_bootargs(char *command_line) ++{ ++} ++#endif ++ + /* + * We need to store the untouched command line for future reference. + * We also need to store the touched command line since the parameter +@@ -522,6 +545,7 @@ asmlinkage __visible void __init start_k + pr_notice("%s", linux_banner); + setup_arch(&command_line); + mm_init_cpumask(&init_mm); ++ mangle_bootargs(command_line); + setup_command_line(command_line); + setup_nr_cpu_ids(); + setup_per_cpu_areas(); +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1607,6 +1607,15 @@ config EMBEDDED + an embedded system so certain expert options are available + for configuration. + ++config MANGLE_BOOTARGS ++ bool "Rename offending bootargs" ++ depends on EXPERT ++ help ++ Sometimes the bootloader passed bogus root= and rootfstype= ++ parameters to the kernel, and while you want to ignore them, ++ you need to know the values f.e. to support dual firmware ++ layouts on the flash. ++ + config HAVE_PERF_EVENTS + bool + help diff --git a/target/linux/generic/patches-4.1/997-device_tree_cmdline.patch b/target/linux/generic/patches-4.1/997-device_tree_cmdline.patch new file mode 100644 index 0000000..076cb6d --- /dev/null +++ b/target/linux/generic/patches-4.1/997-device_tree_cmdline.patch @@ -0,0 +1,24 @@ +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -935,6 +935,9 @@ int __init early_init_dt_scan_chosen(uns + p = of_get_flat_dt_prop(node, "bootargs", &l); + if (p != NULL && l > 0) + strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); ++ p = of_get_flat_dt_prop(node, "bootargs-append", &l); ++ if (p != NULL && l > 0) ++ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else +--- a/arch/mips/kernel/prom.c ++++ b/arch/mips/kernel/prom.c +@@ -50,6 +50,9 @@ void * __init early_init_dt_alloc_memory + + void __init __dt_setup_arch(void *bph) + { ++ if (boot_command_line[0] == '\0') ++ strcpy(boot_command_line, arcs_cmdline); ++ + if (!early_init_dt_scan(bph)) + return; + diff --git a/target/linux/generic/patches-4.1/998-enable_wilink_platform_without_drivers.patch b/target/linux/generic/patches-4.1/998-enable_wilink_platform_without_drivers.patch new file mode 100644 index 0000000..d317de1 --- /dev/null +++ b/target/linux/generic/patches-4.1/998-enable_wilink_platform_without_drivers.patch @@ -0,0 +1,15 @@ +We use backports for driver updates - make sure we can compile in the glue code regardless + +Signed-off-by: Imre Kaloz + +--- a/drivers/net/wireless/ti/Kconfig ++++ b/drivers/net/wireless/ti/Kconfig +@@ -15,7 +15,7 @@ source "drivers/net/wireless/ti/wlcore/K + + config WILINK_PLATFORM_DATA + bool "TI WiLink platform data" +- depends on WLCORE_SDIO || WL1251_SDIO ++ depends on WLCORE_SDIO || WL1251_SDIO || ARCH_OMAP2PLUS + default y + ---help--- + Small platform data bit needed to pass data to the sdio modules. diff --git a/target/linux/generic/patches-4.3/000-keep_initrafs_the_default.patch b/target/linux/generic/patches-4.3/000-keep_initrafs_the_default.patch new file mode 100644 index 0000000..e6f1be4 --- /dev/null +++ b/target/linux/generic/patches-4.3/000-keep_initrafs_the_default.patch @@ -0,0 +1,25 @@ +Upstream changed the default rootfs to tmpfs when none has been passed +to the kernel - this doesn't fit our purposes, so change it back. + +Signed-off-by: Imre Kaloz + +--- a/init/do_mounts.c ++++ b/init/do_mounts.c +@@ -633,6 +633,7 @@ int __init init_rootfs(void) + if (err) + return err; + ++#if 0 + if (IS_ENABLED(CONFIG_TMPFS) && !saved_root_name[0] && + (!root_fs_names || strstr(root_fs_names, "tmpfs"))) { + err = shmem_init(); +@@ -640,6 +641,9 @@ int __init init_rootfs(void) + } else { + err = init_ramfs_fs(); + } ++#else ++ err = init_ramfs_fs(); ++#endif + + if (err) + unregister_filesystem(&rootfs_fs_type); diff --git a/target/linux/generic/patches-4.3/020-bcma-from-4.4.patch b/target/linux/generic/patches-4.3/020-bcma-from-4.4.patch new file mode 100644 index 0000000..5704081 --- /dev/null +++ b/target/linux/generic/patches-4.3/020-bcma-from-4.4.patch @@ -0,0 +1,26 @@ +commit 55acca90da52b85299c033354e51ddaa7b73e019 +Author: Hante Meuleman +Date: Fri Sep 18 22:08:17 2015 +0200 + + brcmfmac: Add support for the BCM4365 and BCM4366 PCIE devices. + + This patch adds support for the BCM4365 and BCM4366 11ac Wave2 + PCIE devices. + + Reviewed-by: Arend Van Spriel + Reviewed-by: Pieter-Paul Giesberts + Signed-off-by: Hante Meuleman + Signed-off-by: Arend van Spriel + Signed-off-by: Kalle Valo + +--- a/include/linux/bcma/bcma.h ++++ b/include/linux/bcma/bcma.h +@@ -151,6 +151,8 @@ struct bcma_host_ops { + #define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */ + #define BCMA_CORE_USB30_DEV 0x83D + #define BCMA_CORE_ARM_CR4 0x83E ++#define BCMA_CORE_ARM_CA7 0x847 ++#define BCMA_CORE_SYS_MEM 0x849 + #define BCMA_CORE_DEFAULT 0xFFF + + #define BCMA_MAX_NR_CORES 16 diff --git a/target/linux/generic/patches-4.3/050-backport_netfilter_rtcache.patch b/target/linux/generic/patches-4.3/050-backport_netfilter_rtcache.patch new file mode 100644 index 0000000..6a79348 --- /dev/null +++ b/target/linux/generic/patches-4.3/050-backport_netfilter_rtcache.patch @@ -0,0 +1,505 @@ +Subject: netfilter: conntrack: cache route for forwarded connections + +... to avoid per-packet FIB lookup if possible. + +The cached dst is re-used provided the input interface +is the same as that of the previous packet in the same direction. + +If not, the cached dst is invalidated. + +For ipv6 we also need to store sernum, else dst_check doesn't work, +pointed out by Eric Dumazet. + +This should speed up forwarding when conntrack is already in use +anyway, especially when using reverse path filtering -- active RPF +enforces two FIB lookups for each packet. + +Before the routing cache removal this didn't matter since RPF was performed +only when route cache didn't yield a result; but without route cache it +comes at higher price. + +Julian Anastasov suggested to add NETDEV_UNREGISTER handler to +avoid holding on to dsts of 'frozen' conntracks. + +Signed-off-by: Florian Westphal + +--- a/include/net/netfilter/nf_conntrack_extend.h ++++ b/include/net/netfilter/nf_conntrack_extend.h +@@ -30,6 +30,9 @@ enum nf_ct_ext_id { + #if IS_ENABLED(CONFIG_NETFILTER_SYNPROXY) + NF_CT_EXT_SYNPROXY, + #endif ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_RTCACHE) ++ NF_CT_EXT_RTCACHE, ++#endif + NF_CT_EXT_NUM, + }; + +@@ -43,6 +46,7 @@ enum nf_ct_ext_id { + #define NF_CT_EXT_TIMEOUT_TYPE struct nf_conn_timeout + #define NF_CT_EXT_LABELS_TYPE struct nf_conn_labels + #define NF_CT_EXT_SYNPROXY_TYPE struct nf_conn_synproxy ++#define NF_CT_EXT_RTCACHE_TYPE struct nf_conn_rtcache + + /* Extensions: optional stuff which isn't permanently in struct. */ + struct nf_ct_ext { +--- /dev/null ++++ b/include/net/netfilter/nf_conntrack_rtcache.h +@@ -0,0 +1,34 @@ ++#include ++#include ++#include ++ ++struct dst_entry; ++ ++struct nf_conn_dst_cache { ++ struct dst_entry *dst; ++ int iif; ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ u32 cookie; ++#endif ++ ++}; ++ ++struct nf_conn_rtcache { ++ struct nf_conn_dst_cache cached_dst[IP_CT_DIR_MAX]; ++}; ++ ++static inline ++struct nf_conn_rtcache *nf_ct_rtcache_find(const struct nf_conn *ct) ++{ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_RTCACHE) ++ return nf_ct_ext_find(ct, NF_CT_EXT_RTCACHE); ++#else ++ return NULL; ++#endif ++} ++ ++static inline int nf_conn_rtcache_iif_get(const struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ return rtc->cached_dst[dir].iif; ++} +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -114,6 +114,18 @@ config NF_CONNTRACK_EVENTS + + If unsure, say `N'. + ++config NF_CONNTRACK_RTCACHE ++ tristate "Cache route entries in conntrack objects" ++ depends on NETFILTER_ADVANCED ++ depends on NF_CONNTRACK ++ help ++ If this option is enabled, the connection tracking code will ++ cache routing information for each connection that is being ++ forwarded, at a cost of 32 bytes per conntrack object. ++ ++ To compile it as a module, choose M here. If unsure, say N. ++ The module will be called nf_conntrack_rtcache. ++ + config NF_CONNTRACK_TIMEOUT + bool 'Connection tracking timeout' + depends on NETFILTER_ADVANCED +--- a/net/netfilter/Makefile ++++ b/net/netfilter/Makefile +@@ -18,6 +18,9 @@ obj-$(CONFIG_NETFILTER_NETLINK_LOG) += n + # connection tracking + obj-$(CONFIG_NF_CONNTRACK) += nf_conntrack.o + ++# optional conntrack route cache extension ++obj-$(CONFIG_NF_CONNTRACK_RTCACHE) += nf_conntrack_rtcache.o ++ + # SCTP protocol connection tracking + obj-$(CONFIG_NF_CT_PROTO_DCCP) += nf_conntrack_proto_dccp.o + obj-$(CONFIG_NF_CT_PROTO_GRE) += nf_conntrack_proto_gre.o +--- /dev/null ++++ b/net/netfilter/nf_conntrack_rtcache.c +@@ -0,0 +1,387 @@ ++/* route cache for netfilter. ++ * ++ * (C) 2014 Red Hat GmbH ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++#include ++#endif ++ ++static void __nf_conn_rtcache_destroy(struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ struct dst_entry *dst = rtc->cached_dst[dir].dst; ++ ++ dst_release(dst); ++} ++ ++static void nf_conn_rtcache_destroy(struct nf_conn *ct) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ ++ if (!rtc) ++ return; ++ ++ __nf_conn_rtcache_destroy(rtc, IP_CT_DIR_ORIGINAL); ++ __nf_conn_rtcache_destroy(rtc, IP_CT_DIR_REPLY); ++} ++ ++static void nf_ct_rtcache_ext_add(struct nf_conn *ct) ++{ ++ struct nf_conn_rtcache *rtc; ++ ++ rtc = nf_ct_ext_add(ct, NF_CT_EXT_RTCACHE, GFP_ATOMIC); ++ if (rtc) { ++ rtc->cached_dst[IP_CT_DIR_ORIGINAL].iif = -1; ++ rtc->cached_dst[IP_CT_DIR_ORIGINAL].dst = NULL; ++ rtc->cached_dst[IP_CT_DIR_REPLY].iif = -1; ++ rtc->cached_dst[IP_CT_DIR_REPLY].dst = NULL; ++ } ++} ++ ++static struct nf_conn_rtcache *nf_ct_rtcache_find_usable(struct nf_conn *ct) ++{ ++ if (nf_ct_is_untracked(ct)) ++ return NULL; ++ return nf_ct_rtcache_find(ct); ++} ++ ++static struct dst_entry * ++nf_conn_rtcache_dst_get(const struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ return rtc->cached_dst[dir].dst; ++} ++ ++static u32 nf_rtcache_get_cookie(int pf, const struct dst_entry *dst) ++{ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ if (pf == NFPROTO_IPV6) { ++ const struct rt6_info *rt = (const struct rt6_info *)dst; ++ ++ if (rt->rt6i_node) ++ return (u32)rt->rt6i_node->fn_sernum; ++ } ++#endif ++ return 0; ++} ++ ++static void nf_conn_rtcache_dst_set(int pf, ++ struct nf_conn_rtcache *rtc, ++ struct dst_entry *dst, ++ enum ip_conntrack_dir dir, int iif) ++{ ++ if (rtc->cached_dst[dir].iif != iif) ++ rtc->cached_dst[dir].iif = iif; ++ ++ if (rtc->cached_dst[dir].dst != dst) { ++ struct dst_entry *old; ++ ++ dst_hold(dst); ++ ++ old = xchg(&rtc->cached_dst[dir].dst, dst); ++ dst_release(old); ++ ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ if (pf == NFPROTO_IPV6) ++ rtc->cached_dst[dir].cookie = ++ nf_rtcache_get_cookie(pf, dst); ++#endif ++ } ++} ++ ++static void nf_conn_rtcache_dst_obsolete(struct nf_conn_rtcache *rtc, ++ enum ip_conntrack_dir dir) ++{ ++ struct dst_entry *old; ++ ++ pr_debug("Invalidate iif %d for dir %d on cache %p\n", ++ rtc->cached_dst[dir].iif, dir, rtc); ++ ++ old = xchg(&rtc->cached_dst[dir].dst, NULL); ++ dst_release(old); ++ rtc->cached_dst[dir].iif = -1; ++} ++ ++static unsigned int nf_rtcache_in(const struct nf_hook_ops *ops, ++ struct sk_buff *skb, ++ const struct nf_hook_state *state) ++{ ++ struct nf_conn_rtcache *rtc; ++ enum ip_conntrack_info ctinfo; ++ enum ip_conntrack_dir dir; ++ struct dst_entry *dst; ++ struct nf_conn *ct; ++ int iif; ++ u32 cookie; ++ ++ if (skb_dst(skb) || skb->sk) ++ return NF_ACCEPT; ++ ++ ct = nf_ct_get(skb, &ctinfo); ++ if (!ct) ++ return NF_ACCEPT; ++ ++ rtc = nf_ct_rtcache_find_usable(ct); ++ if (!rtc) ++ return NF_ACCEPT; ++ ++ /* if iif changes, don't use cache and let ip stack ++ * do route lookup. ++ * ++ * If rp_filter is enabled it might toss skb, so ++ * we don't want to avoid these checks. ++ */ ++ dir = CTINFO2DIR(ctinfo); ++ iif = nf_conn_rtcache_iif_get(rtc, dir); ++ if (state->in->ifindex != iif) { ++ pr_debug("ct %p, iif %d, cached iif %d, skip cached entry\n", ++ ct, iif, state->in->ifindex); ++ return NF_ACCEPT; ++ } ++ dst = nf_conn_rtcache_dst_get(rtc, dir); ++ if (dst == NULL) ++ return NF_ACCEPT; ++ ++ cookie = nf_rtcache_get_cookie(ops->pf, dst); ++ ++ dst = dst_check(dst, cookie); ++ pr_debug("obtained dst %p for skb %p, cookie %d\n", dst, skb, cookie); ++ if (likely(dst)) ++ skb_dst_set_noref(skb, dst); ++ else ++ nf_conn_rtcache_dst_obsolete(rtc, dir); ++ ++ return NF_ACCEPT; ++} ++ ++static unsigned int nf_rtcache_forward(const struct nf_hook_ops *ops, ++ struct sk_buff *skb, ++ const struct nf_hook_state *state) ++{ ++ struct nf_conn_rtcache *rtc; ++ enum ip_conntrack_info ctinfo; ++ enum ip_conntrack_dir dir; ++ struct nf_conn *ct; ++ struct dst_entry *dst = skb_dst(skb); ++ int iif; ++ ++ ct = nf_ct_get(skb, &ctinfo); ++ if (!ct) ++ return NF_ACCEPT; ++ ++ if (dst && dst_xfrm(dst)) ++ return NF_ACCEPT; ++ ++ if (!nf_ct_is_confirmed(ct)) { ++ if (WARN_ON(nf_ct_rtcache_find(ct))) ++ return NF_ACCEPT; ++ nf_ct_rtcache_ext_add(ct); ++ return NF_ACCEPT; ++ } ++ ++ rtc = nf_ct_rtcache_find_usable(ct); ++ if (!rtc) ++ return NF_ACCEPT; ++ ++ dir = CTINFO2DIR(ctinfo); ++ iif = nf_conn_rtcache_iif_get(rtc, dir); ++ pr_debug("ct %p, skb %p, dir %d, iif %d, cached iif %d\n", ++ ct, skb, dir, iif, state->in->ifindex); ++ if (likely(state->in->ifindex == iif)) ++ return NF_ACCEPT; ++ ++ nf_conn_rtcache_dst_set(ops->pf, rtc, skb_dst(skb), dir, state->in->ifindex); ++ return NF_ACCEPT; ++} ++ ++static int nf_rtcache_dst_remove(struct nf_conn *ct, void *data) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ struct net_device *dev = data; ++ ++ if (!rtc) ++ return 0; ++ ++ if (dev->ifindex == rtc->cached_dst[IP_CT_DIR_ORIGINAL].iif || ++ dev->ifindex == rtc->cached_dst[IP_CT_DIR_REPLY].iif) { ++ nf_conn_rtcache_dst_obsolete(rtc, IP_CT_DIR_ORIGINAL); ++ nf_conn_rtcache_dst_obsolete(rtc, IP_CT_DIR_REPLY); ++ } ++ ++ return 0; ++} ++ ++static int nf_rtcache_netdev_event(struct notifier_block *this, ++ unsigned long event, void *ptr) ++{ ++ struct net_device *dev = netdev_notifier_info_to_dev(ptr); ++ struct net *net = dev_net(dev); ++ ++ if (event == NETDEV_DOWN) ++ nf_ct_iterate_cleanup(net, nf_rtcache_dst_remove, dev, 0, 0); ++ ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block nf_rtcache_notifier = { ++ .notifier_call = nf_rtcache_netdev_event, ++}; ++ ++static struct nf_hook_ops rtcache_ops[] = { ++ { ++ .hook = nf_rtcache_in, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV4, ++ .hooknum = NF_INET_PRE_ROUTING, ++ .priority = NF_IP_PRI_LAST, ++ }, ++ { ++ .hook = nf_rtcache_forward, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV4, ++ .hooknum = NF_INET_FORWARD, ++ .priority = NF_IP_PRI_LAST, ++ }, ++#if IS_ENABLED(CONFIG_NF_CONNTRACK_IPV6) ++ { ++ .hook = nf_rtcache_in, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV6, ++ .hooknum = NF_INET_PRE_ROUTING, ++ .priority = NF_IP_PRI_LAST, ++ }, ++ { ++ .hook = nf_rtcache_forward, ++ .owner = THIS_MODULE, ++ .pf = NFPROTO_IPV6, ++ .hooknum = NF_INET_FORWARD, ++ .priority = NF_IP_PRI_LAST, ++ }, ++#endif ++}; ++ ++static struct nf_ct_ext_type rtcache_extend __read_mostly = { ++ .len = sizeof(struct nf_conn_rtcache), ++ .align = __alignof__(struct nf_conn_rtcache), ++ .id = NF_CT_EXT_RTCACHE, ++ .destroy = nf_conn_rtcache_destroy, ++}; ++ ++static int __init nf_conntrack_rtcache_init(void) ++{ ++ int ret = nf_ct_extend_register(&rtcache_extend); ++ ++ if (ret < 0) { ++ pr_err("nf_conntrack_rtcache: Unable to register extension\n"); ++ return ret; ++ } ++ ++ ret = nf_register_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ if (ret < 0) { ++ nf_ct_extend_unregister(&rtcache_extend); ++ return ret; ++ } ++ ++ ret = register_netdevice_notifier(&nf_rtcache_notifier); ++ if (ret) { ++ nf_unregister_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ nf_ct_extend_unregister(&rtcache_extend); ++ } ++ ++ return ret; ++} ++ ++static int nf_rtcache_ext_remove(struct nf_conn *ct, void *data) ++{ ++ struct nf_conn_rtcache *rtc = nf_ct_rtcache_find(ct); ++ ++ return rtc != NULL; ++} ++ ++static bool __exit nf_conntrack_rtcache_wait_for_dying(struct net *net) ++{ ++ bool wait = false; ++ int cpu; ++ ++ for_each_possible_cpu(cpu) { ++ struct nf_conntrack_tuple_hash *h; ++ struct hlist_nulls_node *n; ++ struct nf_conn *ct; ++ struct ct_pcpu *pcpu = per_cpu_ptr(net->ct.pcpu_lists, cpu); ++ ++ rcu_read_lock(); ++ spin_lock_bh(&pcpu->lock); ++ ++ hlist_nulls_for_each_entry(h, n, &pcpu->dying, hnnode) { ++ ct = nf_ct_tuplehash_to_ctrack(h); ++ if (nf_ct_rtcache_find(ct) != NULL) { ++ wait = true; ++ break; ++ } ++ } ++ spin_unlock_bh(&pcpu->lock); ++ rcu_read_unlock(); ++ } ++ ++ return wait; ++} ++ ++static void __exit nf_conntrack_rtcache_fini(void) ++{ ++ struct net *net; ++ int count = 0; ++ ++ /* remove hooks so no new connections get rtcache extension */ ++ nf_unregister_hooks(rtcache_ops, ARRAY_SIZE(rtcache_ops)); ++ ++ synchronize_net(); ++ ++ unregister_netdevice_notifier(&nf_rtcache_notifier); ++ ++ rtnl_lock(); ++ ++ /* zap all conntracks with rtcache extension */ ++ for_each_net(net) ++ nf_ct_iterate_cleanup(net, nf_rtcache_ext_remove, NULL, 0, 0); ++ ++ for_each_net(net) { ++ /* .. and make sure they're gone from dying list, too */ ++ while (nf_conntrack_rtcache_wait_for_dying(net)) { ++ msleep(200); ++ WARN_ONCE(++count > 25, "Waiting for all rtcache conntracks to go away\n"); ++ } ++ } ++ ++ rtnl_unlock(); ++ synchronize_net(); ++ nf_ct_extend_unregister(&rtcache_extend); ++} ++module_init(nf_conntrack_rtcache_init); ++module_exit(nf_conntrack_rtcache_fini); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Florian Westphal "); ++MODULE_DESCRIPTION("Conntrack route cache extension"); diff --git a/target/linux/generic/patches-4.3/060-mips_decompressor_memmove.patch b/target/linux/generic/patches-4.3/060-mips_decompressor_memmove.patch new file mode 100644 index 0000000..d215b80 --- /dev/null +++ b/target/linux/generic/patches-4.3/060-mips_decompressor_memmove.patch @@ -0,0 +1,22 @@ +--- a/arch/mips/boot/compressed/string.c ++++ b/arch/mips/boot/compressed/string.c +@@ -26,3 +26,19 @@ void *memset(void *s, int c, size_t n) + ss[i] = c; + return s; + } ++ ++void *memmove(void *__dest, __const void *__src, size_t count) ++{ ++ unsigned char *d = __dest; ++ const unsigned char *s = __src; ++ ++ if (__dest == __src) ++ return __dest; ++ ++ if (__dest < __src) ++ return memcpy(__dest, __src, count); ++ ++ while (count--) ++ d[count] = s[count]; ++ return __dest; ++} diff --git a/target/linux/generic/patches-4.3/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch b/target/linux/generic/patches-4.3/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch new file mode 100644 index 0000000..82cf6de --- /dev/null +++ b/target/linux/generic/patches-4.3/072-13-bgmac-fix-MAC-soft-reset-bit-for-corerev-4.patch @@ -0,0 +1,24 @@ +From: Felix Fietkau +Date: Mon, 13 Apr 2015 15:54:04 +0200 +Subject: [PATCH] bgmac: fix MAC soft-reset bit for corerev > 4 + +Only core revisions older than 4 use BGMAC_CMDCFG_SR_REV0 + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -199,9 +199,9 @@ + #define BGMAC_CMDCFG_TAI 0x00000200 + #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ + #define BGMAC_CMDCFG_HD_SHIFT 10 +-#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */ +-#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */ +-#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) ++#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */ ++#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */ ++#define BGMAC_CMDCFG_SR(rev) ((rev >= 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) + #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ + #define BGMAC_CMDCFG_AE 0x00400000 + #define BGMAC_CMDCFG_CFE 0x00800000 diff --git a/target/linux/generic/patches-4.3/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch b/target/linux/generic/patches-4.3/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch new file mode 100644 index 0000000..4d6981e --- /dev/null +++ b/target/linux/generic/patches-4.3/072-14-bgmac-reset-all-4-GMAC-cores-on-init.patch @@ -0,0 +1,28 @@ +From: Felix Fietkau +Date: Mon, 13 Apr 2015 15:56:26 +0200 +Subject: [PATCH] bgmac: reset all 4 GMAC cores on init + +On a BCM4709 based device, I found that GMAC cores may be enabled at +probe time, but only become usable after a full reset. +Disable cores before re-enabling them to ensure that they are properly +reset. + +Signed-off-by: Felix Fietkau +--- + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -1641,8 +1641,11 @@ static int bgmac_probe(struct bcma_devic + ns_core = bcma_find_core_unit(core->bus, + BCMA_CORE_MAC_GBIT, + ns_gmac); +- if (ns_core && !bcma_core_is_enabled(ns_core)) +- bcma_core_enable(ns_core, 0); ++ if (!ns_core) ++ continue; ++ ++ bcma_core_disable(ns_core, 0); ++ bcma_core_enable(ns_core, 0); + } + } + diff --git a/target/linux/generic/patches-4.3/102-ehci_hcd_ignore_oc.patch b/target/linux/generic/patches-4.3/102-ehci_hcd_ignore_oc.patch new file mode 100644 index 0000000..694e8cc --- /dev/null +++ b/target/linux/generic/patches-4.3/102-ehci_hcd_ignore_oc.patch @@ -0,0 +1,82 @@ +From 1e311820ec3055e3f08e687de6564692a7cec675 Mon Sep 17 00:00:00 2001 +From: Florian Fainelli +Date: Mon, 28 Jan 2013 20:06:29 +0100 +Subject: [PATCH 11/12] USB: EHCI: add ignore_oc flag to disable overcurrent + checking + +This patch adds an ignore_oc flag which can be set by EHCI controller +not supporting or wanting to disable overcurrent checking. The EHCI +platform data in include/linux/usb/ehci_pdriver.h is also augmented to +take advantage of this new flag. + +Signed-off-by: Florian Fainelli +--- + drivers/usb/host/ehci-hcd.c | 2 +- + drivers/usb/host/ehci-hub.c | 4 ++-- + drivers/usb/host/ehci-platform.c | 1 + + drivers/usb/host/ehci.h | 1 + + include/linux/usb/ehci_pdriver.h | 1 + + 5 files changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -639,7 +639,7 @@ static int ehci_run (struct usb_hcd *hcd + "USB %x.%x started, EHCI %x.%02x%s\n", + ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), + temp >> 8, temp & 0xff, +- ignore_oc ? ", overcurrent ignored" : ""); ++ (ignore_oc || ehci->ignore_oc) ? ", overcurrent ignored" : ""); + + ehci_writel(ehci, INTR_MASK, + &ehci->regs->intr_enable); /* Turn On Interrupts */ +--- a/drivers/usb/host/ehci-hub.c ++++ b/drivers/usb/host/ehci-hub.c +@@ -634,7 +634,7 @@ ehci_hub_status_data (struct usb_hcd *hc + * always set, seem to clear PORT_OCC and PORT_CSC when writing to + * PORT_POWER; that's surprising, but maybe within-spec. + */ +- if (!ignore_oc) ++ if (!ignore_oc && !ehci->ignore_oc) + mask = PORT_CSC | PORT_PEC | PORT_OCC; + else + mask = PORT_CSC | PORT_PEC; +@@ -996,7 +996,7 @@ int ehci_hub_control( + if (temp & PORT_PEC) + status |= USB_PORT_STAT_C_ENABLE << 16; + +- if ((temp & PORT_OCC) && !ignore_oc){ ++ if ((temp & PORT_OCC) && (!ignore_oc && !ehci->ignore_oc)){ + status |= USB_PORT_STAT_C_OVERCURRENT << 16; + + /* +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -251,6 +251,8 @@ static int ehci_platform_probe(struct pl + hcd->has_tt = 1; + if (pdata->reset_on_resume) + priv->reset_on_resume = true; ++ if (pdata->ignore_oc) ++ ehci->ignore_oc = 1; + + #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO + if (ehci->big_endian_mmio) { +--- a/drivers/usb/host/ehci.h ++++ b/drivers/usb/host/ehci.h +@@ -227,6 +227,7 @@ struct ehci_hcd { /* one per controlle + unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ + unsigned need_oc_pp_cycle:1; /* MPC834X port power */ + unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ ++ unsigned ignore_oc:1; + + /* required for usb32 quirk */ + #define OHCI_CTRL_HCFS (3 << 6) +--- a/include/linux/usb/ehci_pdriver.h ++++ b/include/linux/usb/ehci_pdriver.h +@@ -49,6 +49,7 @@ struct usb_ehci_pdata { + unsigned no_io_watchdog:1; + unsigned reset_on_resume:1; + unsigned dma_mask_64:1; ++ unsigned ignore_oc:1; + + /* Turn on all power and clocks */ + int (*power_on)(struct platform_device *pdev); diff --git a/target/linux/generic/patches-4.3/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch b/target/linux/generic/patches-4.3/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch new file mode 100644 index 0000000..d47aa45 --- /dev/null +++ b/target/linux/generic/patches-4.3/110-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch @@ -0,0 +1,86 @@ +From: Felix Fietkau +Date: Fri, 10 Apr 2015 13:35:29 +0200 +Subject: [PATCH] jffs2: use .rename2 and add RENAME_WHITEOUT support + +It is required for renames on overlayfs + +Signed-off-by: Felix Fietkau +--- + +--- a/fs/jffs2/dir.c ++++ b/fs/jffs2/dir.c +@@ -35,7 +35,7 @@ static int jffs2_mkdir (struct inode *,s + static int jffs2_rmdir (struct inode *,struct dentry *); + static int jffs2_mknod (struct inode *,struct dentry *,umode_t,dev_t); + static int jffs2_rename (struct inode *, struct dentry *, +- struct inode *, struct dentry *); ++ struct inode *, struct dentry *, unsigned int); + + const struct file_operations jffs2_dir_operations = + { +@@ -57,7 +57,7 @@ const struct inode_operations jffs2_dir_ + .mkdir = jffs2_mkdir, + .rmdir = jffs2_rmdir, + .mknod = jffs2_mknod, +- .rename = jffs2_rename, ++ .rename2 = jffs2_rename, + .get_acl = jffs2_get_acl, + .set_acl = jffs2_set_acl, + .setattr = jffs2_setattr, +@@ -757,8 +757,27 @@ static int jffs2_mknod (struct inode *di + return ret; + } + ++static int jffs2_whiteout(struct inode *old_dir, struct dentry *old_dentry) ++{ ++ struct dentry *wh; ++ int err; ++ ++ wh = d_alloc(old_dentry->d_parent, &old_dentry->d_name); ++ if (!wh) ++ return -ENOMEM; ++ ++ err = jffs2_mknod(old_dir, wh, S_IFCHR | WHITEOUT_MODE, ++ WHITEOUT_DEV); ++ if (err) ++ return err; ++ ++ d_rehash(wh); ++ return 0; ++} ++ + static int jffs2_rename (struct inode *old_dir_i, struct dentry *old_dentry, +- struct inode *new_dir_i, struct dentry *new_dentry) ++ struct inode *new_dir_i, struct dentry *new_dentry, ++ unsigned int flags) + { + int ret; + struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb); +@@ -766,6 +785,9 @@ static int jffs2_rename (struct inode *o + uint8_t type; + uint32_t now; + ++ if (flags & ~RENAME_WHITEOUT) ++ return -EINVAL; ++ + /* The VFS will check for us and prevent trying to rename a + * file over a directory and vice versa, but if it's a directory, + * the VFS can't check whether the victim is empty. The filesystem +@@ -829,9 +851,14 @@ static int jffs2_rename (struct inode *o + if (d_is_dir(old_dentry) && !victim_f) + inc_nlink(new_dir_i); + +- /* Unlink the original */ +- ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), +- old_dentry->d_name.name, old_dentry->d_name.len, NULL, now); ++ if (flags & RENAME_WHITEOUT) ++ /* Replace with whiteout */ ++ ret = jffs2_whiteout(old_dir_i, old_dentry); ++ else ++ /* Unlink the original */ ++ ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), ++ old_dentry->d_name.name, ++ old_dentry->d_name.len, NULL, now); + + /* We don't touch inode->i_nlink */ + diff --git a/target/linux/generic/patches-4.3/111-jffs2-add-RENAME_EXCHANGE-support.patch b/target/linux/generic/patches-4.3/111-jffs2-add-RENAME_EXCHANGE-support.patch new file mode 100644 index 0000000..cc5f440 --- /dev/null +++ b/target/linux/generic/patches-4.3/111-jffs2-add-RENAME_EXCHANGE-support.patch @@ -0,0 +1,58 @@ +From: Felix Fietkau +Date: Sat, 25 Apr 2015 12:41:32 +0200 +Subject: [PATCH] jffs2: add RENAME_EXCHANGE support + +Signed-off-by: Felix Fietkau +--- + +--- a/fs/jffs2/dir.c ++++ b/fs/jffs2/dir.c +@@ -785,7 +785,7 @@ static int jffs2_rename (struct inode *o + uint8_t type; + uint32_t now; + +- if (flags & ~RENAME_WHITEOUT) ++ if (flags & ~(RENAME_WHITEOUT | RENAME_EXCHANGE)) + return -EINVAL; + + /* The VFS will check for us and prevent trying to rename a +@@ -793,7 +793,7 @@ static int jffs2_rename (struct inode *o + * the VFS can't check whether the victim is empty. The filesystem + * needs to do that for itself. + */ +- if (d_really_is_positive(new_dentry)) { ++ if (d_really_is_positive(new_dentry) && !(flags & RENAME_EXCHANGE)) { + victim_f = JFFS2_INODE_INFO(d_inode(new_dentry)); + if (d_is_dir(new_dentry)) { + struct jffs2_full_dirent *fd; +@@ -828,7 +828,7 @@ static int jffs2_rename (struct inode *o + if (ret) + return ret; + +- if (victim_f) { ++ if (victim_f && !(flags & RENAME_EXCHANGE)) { + /* There was a victim. Kill it off nicely */ + if (d_is_dir(new_dentry)) + clear_nlink(d_inode(new_dentry)); +@@ -854,6 +854,12 @@ static int jffs2_rename (struct inode *o + if (flags & RENAME_WHITEOUT) + /* Replace with whiteout */ + ret = jffs2_whiteout(old_dir_i, old_dentry); ++ else if (flags & RENAME_EXCHANGE) ++ /* Replace the original */ ++ ret = jffs2_do_link(c, JFFS2_INODE_INFO(old_dir_i), ++ d_inode(new_dentry)->i_ino, type, ++ old_dentry->d_name.name, old_dentry->d_name.len, ++ now); + else + /* Unlink the original */ + ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), +@@ -880,7 +886,7 @@ static int jffs2_rename (struct inode *o + return ret; + } + +- if (d_is_dir(old_dentry)) ++ if (d_is_dir(old_dentry) && !(flags & RENAME_EXCHANGE)) + drop_nlink(old_dir_i); + + new_dir_i->i_mtime = new_dir_i->i_ctime = old_dir_i->i_mtime = old_dir_i->i_ctime = ITIME(now); diff --git a/target/linux/generic/patches-4.3/120-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/patches-4.3/120-bridge_allow_receiption_on_disabled_port.patch new file mode 100644 index 0000000..5cd2f57 --- /dev/null +++ b/target/linux/generic/patches-4.3/120-bridge_allow_receiption_on_disabled_port.patch @@ -0,0 +1,54 @@ +From: Stephen Hemminger +Subject: bridge: allow receiption on disabled port + +When an ethernet device is enslaved to a bridge, and the bridge STP +detects loss of carrier (or operational state down), then normally +packet receiption is blocked. + +This breaks control applications like WPA which maybe expecting to +receive packets to negotiate to bring link up. The bridge needs to +block forwarding packets from these disabled ports, but there is no +hard requirement to not allow local packet delivery. + +Signed-off-by: Stephen Hemminger +Signed-off-by: Felix Fietkau + +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -211,11 +211,13 @@ EXPORT_SYMBOL_GPL(br_handle_frame_finish + static int br_handle_local_finish(struct sock *sk, struct sk_buff *skb) + { + struct net_bridge_port *p = br_port_get_rcu(skb->dev); +- u16 vid = 0; ++ if (p->state != BR_STATE_DISABLED) { ++ u16 vid = 0; + +- /* check if vlan is allowed, to avoid spoofing */ +- if (p->flags & BR_LEARNING && br_should_learn(p, skb, &vid)) +- br_fdb_update(p->br, p, eth_hdr(skb)->h_source, vid, false); ++ /* check if vlan is allowed, to avoid spoofing */ ++ if (p->flags & BR_LEARNING && br_should_learn(p, skb, &vid)) ++ br_fdb_update(p->br, p, eth_hdr(skb)->h_source, vid, false); ++ } + return 0; /* process further */ + } + +@@ -289,6 +291,18 @@ rx_handler_result_t br_handle_frame(stru + + forward: + switch (p->state) { ++ case BR_STATE_DISABLED: ++ if (ether_addr_equal(p->br->dev->dev_addr, dest)) ++ skb->pkt_type = PACKET_HOST; ++ ++ if (NF_HOOK(NFPROTO_BRIDGE, NF_BR_PRE_ROUTING, NULL, skb, skb->dev, NULL, ++ br_handle_local_finish)) ++ break; ++ ++ BR_INPUT_SKB_CB(skb)->brdev = p->br->dev; ++ br_pass_frame_up(skb); ++ break; ++ + case BR_STATE_FORWARDING: + rhook = rcu_dereference(br_should_route_hook); + if (rhook) { diff --git a/target/linux/generic/patches-4.3/132-mips_inline_dma_ops.patch b/target/linux/generic/patches-4.3/132-mips_inline_dma_ops.patch new file mode 100644 index 0000000..738dca9 --- /dev/null +++ b/target/linux/generic/patches-4.3/132-mips_inline_dma_ops.patch @@ -0,0 +1,778 @@ +From 2c58080407554e1bac8fd50d23cb02420524caed Mon Sep 17 00:00:00 2001 +From: Felix Fietkau +Date: Mon, 12 Aug 2013 12:50:22 +0200 +Subject: [PATCH] MIPS: partially inline dma ops + +Several DMA ops are no-op on many platforms, and the indirection through +the mips_dma_map_ops function table is causing the compiler to emit +unnecessary code. + +Inlining visibly improves network performance in my tests (on a 24Kc +based system), and also slightly reduces code size of a few drivers. + +Signed-off-by: Felix Fietkau +--- + arch/mips/Kconfig | 4 + + arch/mips/include/asm/dma-mapping.h | 360 +++++++++++++++++++++++++++++++++++- + arch/mips/mm/dma-default.c | 163 ++-------------- + 3 files changed, 373 insertions(+), 154 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1586,6 +1586,7 @@ config CPU_CAVIUM_OCTEON + select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select MIPS_L1_CACHE_SHIFT_7 ++ select SYS_HAS_DMA_OPS + help + The Cavium Octeon processor is a highly integrated chip containing + many ethernet hardware widgets for networking tasks. The processor +@@ -1881,6 +1882,9 @@ config MIPS_MALTA_PM + bool + default y + ++config SYS_HAS_DMA_OPS ++ bool ++ + # + # CPU may reorder R->R, R->W, W->R, W->W + # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC +--- a/arch/mips/include/asm/dma-mapping.h ++++ b/arch/mips/include/asm/dma-mapping.h +@@ -1,9 +1,16 @@ + #ifndef _ASM_DMA_MAPPING_H + #define _ASM_DMA_MAPPING_H + ++#include ++#include + #include ++#include ++#include ++ + #include + #include ++#include ++#include + + #ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */ + #include +@@ -11,12 +18,53 @@ + + extern struct dma_map_ops *mips_dma_map_ops; + ++void __dma_sync(struct page *page, unsigned long offset, size_t size, ++ enum dma_data_direction direction); ++void *mips_dma_alloc_coherent(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp, ++ struct dma_attrs *attrs); ++void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, ++ dma_addr_t dma_handle, struct dma_attrs *attrs); ++ + static inline struct dma_map_ops *get_dma_ops(struct device *dev) + { ++#ifdef CONFIG_SYS_HAS_DMA_OPS + if (dev && dev->archdata.dma_ops) + return dev->archdata.dma_ops; + else + return mips_dma_map_ops; ++#else ++ return NULL; ++#endif ++} ++ ++/* ++ * The affected CPUs below in 'cpu_needs_post_dma_flush()' can ++ * speculatively fill random cachelines with stale data at any time, ++ * requiring an extra flush post-DMA. ++ * ++ * Warning on the terminology - Linux calls an uncached area coherent; ++ * MIPS terminology calls memory areas with hardware maintained coherency ++ * coherent. ++ * ++ * Note that the R14000 and R16000 should also be checked for in this ++ * condition. However this function is only called on non-I/O-coherent ++ * systems and only the R10000 and R12000 are used in such systems, the ++ * SGI IP28 Indigo² rsp. SGI IP32 aka O2. ++ */ ++static inline int cpu_needs_post_dma_flush(struct device *dev) ++{ ++ return !plat_device_is_coherent(dev) && ++ (boot_cpu_type() == CPU_R10000 || ++ boot_cpu_type() == CPU_R12000 || ++ boot_cpu_type() == CPU_BMIPS5000); ++} ++ ++static inline struct page *dma_addr_to_page(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return pfn_to_page( ++ plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); + } + + static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) +@@ -29,9 +77,399 @@ static inline bool dma_capable(struct de + + static inline void dma_mark_clean(void *addr, size_t size) {} + +-#include ++static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr, ++ size_t size, ++ enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ unsigned long offset = (unsigned long)ptr & ~PAGE_MASK; ++ struct page *page = virt_to_page(ptr); ++ dma_addr_t addr; ++ ++ kmemcheck_mark_initialized(ptr, size); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ addr = ops->map_page(dev, page, offset, size, dir, attrs); ++ } else { ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, offset, size, dir); ++ ++ addr = plat_map_dma_mem_page(dev, page) + offset; ++ } ++ debug_dma_map_page(dev, page, offset, size, dir, addr, true); ++ return addr; ++} ++ ++static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr, ++ size_t size, ++ enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->unmap_page(dev, addr, size, dir, attrs); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ plat_post_dma_flush(dev); ++ plat_unmap_dma_mem(dev, addr, size, dir); ++ } ++ debug_dma_unmap_page(dev, addr, size, dir, true); ++} ++ ++/* ++ * dma_maps_sg_attrs returns 0 on error and > 0 on success. ++ * It should never return a value < 0. ++ */ ++static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, ++ int nents, enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ int i, ents; ++ struct scatterlist *s; ++ ++ for_each_sg(sg, s, nents, i) ++ kmemcheck_mark_initialized(sg_virt(s), s->length); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ents = ops->map_sg(dev, sg, nents, dir, attrs); ++ } else { ++ for_each_sg(sg, s, nents, i) { ++ struct page *page = sg_page(s); ++ ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, s->offset, s->length, dir); ++#ifdef CONFIG_NEED_SG_DMA_LENGTH ++ s->dma_length = s->length; ++#endif ++ s->dma_address = ++ plat_map_dma_mem_page(dev, page) + s->offset; ++ } ++ ents = nents; ++ } ++ BUG_ON(ents < 0); ++ debug_dma_map_sg(dev, sg, nents, ents, dir); ++ ++ return ents; ++} ++ ++static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, ++ int nents, enum dma_data_direction dir, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ debug_dma_unmap_sg(dev, sg, nents, dir); ++ if (ops) { ++ ops->unmap_sg(dev, sg, nents, dir, attrs); ++ return; ++ } ++ for_each_sg(sg, s, nents, i) { ++ if (!plat_device_is_coherent(dev) && dir != DMA_TO_DEVICE) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ plat_unmap_dma_mem(dev, s->dma_address, s->length, dir); ++ } ++} ++ ++static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, ++ size_t offset, size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ dma_addr_t addr; ++ ++ kmemcheck_mark_initialized(page_address(page) + offset, size); ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ addr = ops->map_page(dev, page, offset, size, dir, NULL); ++ } else { ++ if (!plat_device_is_coherent(dev)) ++ __dma_sync(page, offset, size, dir); ++ ++ addr = plat_map_dma_mem_page(dev, page) + offset; ++ } ++ debug_dma_map_page(dev, page, offset, size, dir, addr, false); ++ ++ return addr; ++} ++ ++static inline void dma_unmap_page(struct device *dev, dma_addr_t addr, ++ size_t size, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->unmap_page(dev, addr, size, dir, NULL); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ plat_post_dma_flush(dev); ++ plat_unmap_dma_mem(dev, addr, size, dir); ++ } ++ debug_dma_unmap_page(dev, addr, size, dir, false); ++} ++ ++static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->sync_single_for_cpu(dev, addr, size, dir); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ plat_post_dma_flush(dev); ++ } ++ debug_dma_sync_single_for_cpu(dev, addr, size, dir); ++} ++ ++static inline void dma_sync_single_for_device(struct device *dev, ++ dma_addr_t addr, size_t size, ++ enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_device(dev, addr, size, dir); ++ else if (!plat_device_is_coherent(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr), ++ addr & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_for_device(dev, addr, size, dir); ++} ++ ++static inline void dma_sync_single_range_for_cpu(struct device *dev, ++ dma_addr_t addr, ++ unsigned long offset, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ const struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->sync_single_for_cpu(dev, addr + offset, size, dir); ++ } else { ++ if (cpu_needs_post_dma_flush(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr + offset), ++ (addr + offset) & ~PAGE_MASK, size, dir); ++ plat_post_dma_flush(dev); ++ } ++ ++ debug_dma_sync_single_range_for_cpu(dev, addr, offset, size, dir); ++} ++ ++static inline void dma_sync_single_range_for_device(struct device *dev, ++ dma_addr_t addr, ++ unsigned long offset, ++ size_t size, ++ enum dma_data_direction dir) ++{ ++ const struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) ++ ops->sync_single_for_device(dev, addr + offset, size, dir); ++ else if (!plat_device_is_coherent(dev)) ++ __dma_sync(dma_addr_to_page(dev, addr + offset), ++ (addr + offset) & ~PAGE_MASK, size, dir); ++ debug_dma_sync_single_range_for_device(dev, addr, offset, size, dir); ++} ++ ++static inline void ++dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, ++ int nelems, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->sync_sg_for_cpu(dev, sg, nelems, dir); ++ } else if (cpu_needs_post_dma_flush(dev)) { ++ for_each_sg(sg, s, nelems, i) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ } ++ plat_post_dma_flush(dev); ++ debug_dma_sync_sg_for_cpu(dev, sg, nelems, dir); ++} ++ ++static inline void ++dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, ++ int nelems, enum dma_data_direction dir) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ struct scatterlist *s; ++ int i; ++ ++ BUG_ON(!valid_dma_direction(dir)); ++ if (ops) { ++ ops->sync_sg_for_device(dev, sg, nelems, dir); ++ } else if (!plat_device_is_coherent(dev)) { ++ for_each_sg(sg, s, nelems, i) ++ __dma_sync(sg_page(s), s->offset, s->length, dir); ++ } ++ debug_dma_sync_sg_for_device(dev, sg, nelems, dir); ++ ++} ++ ++#define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, NULL) ++#define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, NULL) ++#define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, NULL) ++#define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, NULL) ++ ++extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, ++ void *cpu_addr, dma_addr_t dma_addr, size_t size); ++ ++/** ++ * dma_mmap_attrs - map a coherent DMA allocation into user space ++ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices ++ * @vma: vm_area_struct describing requested user mapping ++ * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs ++ * @handle: device-view address returned from dma_alloc_attrs ++ * @size: size of memory originally requested in dma_alloc_attrs ++ * @attrs: attributes of mapping properties requested in dma_alloc_attrs ++ * ++ * Map a coherent DMA buffer previously allocated by dma_alloc_attrs ++ * into user space. The coherent DMA buffer must not be freed by the ++ * driver until the user space mapping has been released. ++ */ ++static inline int ++dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr, ++ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ BUG_ON(!ops); ++ if (ops && ops->mmap) ++ return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); ++ return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size); ++} ++ ++#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL) ++ ++int ++dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, ++ void *cpu_addr, dma_addr_t dma_addr, size_t size); ++ ++static inline int ++dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, void *cpu_addr, ++ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ BUG_ON(!ops); ++ if (ops && ops->get_sgtable) ++ return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, ++ attrs); ++ return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, size); ++} ++ ++#define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, NULL) ++ ++static inline int dma_supported(struct device *dev, u64 mask) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ if (ops) ++ return ops->dma_supported(dev, mask); ++ return plat_dma_supported(dev, mask); ++} ++ ++static inline int dma_mapping_error(struct device *dev, u64 mask) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ debug_dma_mapping_error(dev, mask); ++ if (ops) ++ return ops->mapping_error(dev, mask); ++ return 0; ++} ++ ++static inline int ++dma_set_mask(struct device *dev, u64 mask) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ if(!dev->dma_mask || !dma_supported(dev, mask)) ++ return -EIO; ++ ++ if (ops && ops->set_dma_mask) ++ return ops->set_dma_mask(dev, mask); ++ ++ *dev->dma_mask = mask; ++ ++ return 0; ++} + + extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction); + ++#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) ++ ++static inline void *dma_alloc_attrs(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp, ++ struct dma_attrs *attrs) ++{ ++ void *ret; ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ if (ops) ++ ret = ops->alloc(dev, size, dma_handle, gfp, attrs); ++ else ++ ret = mips_dma_alloc_coherent(dev, size, dma_handle, gfp, ++ attrs); ++ ++ debug_dma_alloc_coherent(dev, size, *dma_handle, ret); ++ ++ return ret; ++} ++ ++#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) ++ ++static inline void dma_free_attrs(struct device *dev, size_t size, ++ void *vaddr, dma_addr_t dma_handle, ++ struct dma_attrs *attrs) ++{ ++ struct dma_map_ops *ops = get_dma_ops(dev); ++ ++ if (ops) ++ ops->free(dev, size, vaddr, dma_handle, attrs); ++ else ++ mips_dma_free_coherent(dev, size, vaddr, dma_handle, attrs); ++ ++ debug_dma_free_coherent(dev, size, vaddr, dma_handle); ++} ++ ++static inline void *dma_alloc_noncoherent(struct device *dev, size_t size, ++ dma_addr_t *dma_handle, gfp_t gfp) ++{ ++ DEFINE_DMA_ATTRS(attrs); ++ ++ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs); ++ return dma_alloc_attrs(dev, size, dma_handle, gfp, &attrs); ++} ++ ++static inline void dma_free_noncoherent(struct device *dev, size_t size, ++ void *cpu_addr, dma_addr_t dma_handle) ++{ ++ DEFINE_DMA_ATTRS(attrs); ++ ++ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs); ++ dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs); ++} ++ ++ + #endif /* _ASM_DMA_MAPPING_H */ +--- a/arch/mips/mm/dma-default.c ++++ b/arch/mips/mm/dma-default.c +@@ -46,35 +46,6 @@ static int __init setnocoherentio(char * + early_param("nocoherentio", setnocoherentio); + #endif + +-static inline struct page *dma_addr_to_page(struct device *dev, +- dma_addr_t dma_addr) +-{ +- return pfn_to_page( +- plat_dma_addr_to_phys(dev, dma_addr) >> PAGE_SHIFT); +-} +- +-/* +- * The affected CPUs below in 'cpu_needs_post_dma_flush()' can +- * speculatively fill random cachelines with stale data at any time, +- * requiring an extra flush post-DMA. +- * +- * Warning on the terminology - Linux calls an uncached area coherent; +- * MIPS terminology calls memory areas with hardware maintained coherency +- * coherent. +- * +- * Note that the R14000 and R16000 should also be checked for in this +- * condition. However this function is only called on non-I/O-coherent +- * systems and only the R10000 and R12000 are used in such systems, the +- * SGI IP28 Indigo² rsp. SGI IP32 aka O2. +- */ +-static inline int cpu_needs_post_dma_flush(struct device *dev) +-{ +- return !plat_device_is_coherent(dev) && +- (boot_cpu_type() == CPU_R10000 || +- boot_cpu_type() == CPU_R12000 || +- boot_cpu_type() == CPU_BMIPS5000); +-} +- + static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp) + { + gfp_t dma_flag; +@@ -129,7 +100,7 @@ static void *mips_dma_alloc_noncoherent( + return ret; + } + +-static void *mips_dma_alloc_coherent(struct device *dev, size_t size, ++void *mips_dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t * dma_handle, gfp_t gfp, struct dma_attrs *attrs) + { + void *ret; +@@ -165,6 +136,7 @@ static void *mips_dma_alloc_coherent(str + + return ret; + } ++EXPORT_SYMBOL(mips_dma_alloc_coherent); + + + static void mips_dma_free_noncoherent(struct device *dev, size_t size, +@@ -174,7 +146,7 @@ static void mips_dma_free_noncoherent(st + free_pages((unsigned long) vaddr, get_order(size)); + } + +-static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, ++void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr, + dma_addr_t dma_handle, struct dma_attrs *attrs) + { + unsigned long addr = (unsigned long) vaddr; +@@ -196,40 +168,7 @@ static void mips_dma_free_coherent(struc + if (!dma_release_from_contiguous(dev, page, count)) + __free_pages(page, get_order(size)); + } +- +-static int mips_dma_mmap(struct device *dev, struct vm_area_struct *vma, +- void *cpu_addr, dma_addr_t dma_addr, size_t size, +- struct dma_attrs *attrs) +-{ +- unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; +- unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; +- unsigned long addr = (unsigned long)cpu_addr; +- unsigned long off = vma->vm_pgoff; +- unsigned long pfn; +- int ret = -ENXIO; +- +- if (!plat_device_is_coherent(dev) && !hw_coherentio) +- addr = CAC_ADDR(addr); +- +- pfn = page_to_pfn(virt_to_page((void *)addr)); +- +- if (dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) +- vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); +- else +- vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); +- +- if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) +- return ret; +- +- if (off < count && user_count <= (count - off)) { +- ret = remap_pfn_range(vma, vma->vm_start, +- pfn + off, +- user_count << PAGE_SHIFT, +- vma->vm_page_prot); +- } +- +- return ret; +-} ++EXPORT_SYMBOL(mips_dma_free_coherent); + + static inline void __dma_sync_virtual(void *addr, size_t size, + enum dma_data_direction direction) +@@ -258,7 +197,7 @@ static inline void __dma_sync_virtual(vo + * If highmem is not configured then the bulk of this loop gets + * optimized out. + */ +-static inline void __dma_sync(struct page *page, ++void __dma_sync(struct page *page, + unsigned long offset, size_t size, enum dma_data_direction direction) + { + size_t left = size; +@@ -288,120 +227,7 @@ static inline void __dma_sync(struct pag + left -= len; + } while (left); + } +- +-static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, +- size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) +-{ +- if (cpu_needs_post_dma_flush(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_addr), +- dma_addr & ~PAGE_MASK, size, direction); +- plat_post_dma_flush(dev); +- plat_unmap_dma_mem(dev, dma_addr, size, direction); +-} +- +-static int mips_dma_map_sg(struct device *dev, struct scatterlist *sglist, +- int nents, enum dma_data_direction direction, struct dma_attrs *attrs) +-{ +- int i; +- struct scatterlist *sg; +- +- for_each_sg(sglist, sg, nents, i) { +- if (!plat_device_is_coherent(dev)) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +-#ifdef CONFIG_NEED_SG_DMA_LENGTH +- sg->dma_length = sg->length; +-#endif +- sg->dma_address = plat_map_dma_mem_page(dev, sg_page(sg)) + +- sg->offset; +- } +- +- return nents; +-} +- +-static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page, +- unsigned long offset, size_t size, enum dma_data_direction direction, +- struct dma_attrs *attrs) +-{ +- if (!plat_device_is_coherent(dev)) +- __dma_sync(page, offset, size, direction); +- +- return plat_map_dma_mem_page(dev, page) + offset; +-} +- +-static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sglist, +- int nhwentries, enum dma_data_direction direction, +- struct dma_attrs *attrs) +-{ +- int i; +- struct scatterlist *sg; +- +- for_each_sg(sglist, sg, nhwentries, i) { +- if (!plat_device_is_coherent(dev) && +- direction != DMA_TO_DEVICE) +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +- plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction); +- } +-} +- +-static void mips_dma_sync_single_for_cpu(struct device *dev, +- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +-{ +- if (cpu_needs_post_dma_flush(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_handle), +- dma_handle & ~PAGE_MASK, size, direction); +- plat_post_dma_flush(dev); +-} +- +-static void mips_dma_sync_single_for_device(struct device *dev, +- dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) +-{ +- if (!plat_device_is_coherent(dev)) +- __dma_sync(dma_addr_to_page(dev, dma_handle), +- dma_handle & ~PAGE_MASK, size, direction); +-} +- +-static void mips_dma_sync_sg_for_cpu(struct device *dev, +- struct scatterlist *sglist, int nelems, +- enum dma_data_direction direction) +-{ +- int i; +- struct scatterlist *sg; +- +- if (cpu_needs_post_dma_flush(dev)) { +- for_each_sg(sglist, sg, nelems, i) { +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +- } +- } +- plat_post_dma_flush(dev); +-} +- +-static void mips_dma_sync_sg_for_device(struct device *dev, +- struct scatterlist *sglist, int nelems, +- enum dma_data_direction direction) +-{ +- int i; +- struct scatterlist *sg; +- +- if (!plat_device_is_coherent(dev)) { +- for_each_sg(sglist, sg, nelems, i) { +- __dma_sync(sg_page(sg), sg->offset, sg->length, +- direction); +- } +- } +-} +- +-int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +-{ +- return 0; +-} +- +-int mips_dma_supported(struct device *dev, u64 mask) +-{ +- return plat_dma_supported(dev, mask); +-} ++EXPORT_SYMBOL(__dma_sync); + + void dma_cache_sync(struct device *dev, void *vaddr, size_t size, + enum dma_data_direction direction) +@@ -414,24 +240,10 @@ void dma_cache_sync(struct device *dev, + + EXPORT_SYMBOL(dma_cache_sync); + +-static struct dma_map_ops mips_default_dma_map_ops = { +- .alloc = mips_dma_alloc_coherent, +- .free = mips_dma_free_coherent, +- .mmap = mips_dma_mmap, +- .map_page = mips_dma_map_page, +- .unmap_page = mips_dma_unmap_page, +- .map_sg = mips_dma_map_sg, +- .unmap_sg = mips_dma_unmap_sg, +- .sync_single_for_cpu = mips_dma_sync_single_for_cpu, +- .sync_single_for_device = mips_dma_sync_single_for_device, +- .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu, +- .sync_sg_for_device = mips_dma_sync_sg_for_device, +- .mapping_error = mips_dma_mapping_error, +- .dma_supported = mips_dma_supported +-}; +- +-struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops; ++#ifdef CONFIG_SYS_HAS_DMA_OPS ++struct dma_map_ops *mips_dma_map_ops = NULL; + EXPORT_SYMBOL(mips_dma_map_ops); ++#endif + + #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16) + diff --git a/target/linux/generic/patches-4.3/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch b/target/linux/generic/patches-4.3/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch new file mode 100644 index 0000000..53353b3 --- /dev/null +++ b/target/linux/generic/patches-4.3/140-mtd-part-add-generic-parsing-of-linux-part-probe.patch @@ -0,0 +1,183 @@ +From 3e7056c3a369e9ef9ca804bc626b60ef6b62ee27 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 17 May 2015 18:48:38 +0200 +Subject: [PATCH 2/3] mtd: part: add generic parsing of linux,part-probe + +This moves the linux,part-probe device tree parsing code from +physmap_of.c to mtdpart.c. Now all drivers can use this feature by just +providing a reference to their device tree node in struct +mtd_part_parser_data. + +Signed-off-by: Hauke Mehrtens +--- + Documentation/devicetree/bindings/mtd/nand.txt | 16 +++++++++ + drivers/mtd/maps/physmap_of.c | 46 +------------------------- + drivers/mtd/mtdpart.c | 45 +++++++++++++++++++++++++ + 3 files changed, 62 insertions(+), 45 deletions(-) + +--- a/Documentation/devicetree/bindings/mtd/nand.txt ++++ b/Documentation/devicetree/bindings/mtd/nand.txt +@@ -12,6 +12,22 @@ + - nand-ecc-step-size: integer representing the number of data bytes + that are covered by a single ECC step. + ++- linux,part-probe: list of name as strings of the partition parser ++ which should be used to parse the partition table. ++ They will be tried in the specified ordering and ++ the next one will be used if the previous one ++ failed. ++ ++ Example: linux,part-probe = "cmdlinepart", "ofpart"; ++ ++ This is also the default value, which will be used ++ if this attribute is not specified. It could be ++ that the flash driver in use overwrote the default ++ value and uses some other default. ++ ++ Possible values are: bcm47xxpart, afs, ar7part, ++ ofoldpart, ofpart, bcm63xxpart, RedBoot, cmdlinepart ++ + The ECC strength and ECC step size properties define the correction capability + of a controller. Together, they say a controller can correct "{strength} bit + errors per {size} bytes". +--- a/drivers/mtd/maps/physmap_of.c ++++ b/drivers/mtd/maps/physmap_of.c +@@ -112,47 +112,9 @@ static struct mtd_info *obsolete_probe(s + static const char * const part_probe_types_def[] = { + "cmdlinepart", "RedBoot", "ofpart", "ofoldpart", NULL }; + +-static const char * const *of_get_probes(struct device_node *dp) +-{ +- const char *cp; +- int cplen; +- unsigned int l; +- unsigned int count; +- const char **res; +- +- cp = of_get_property(dp, "linux,part-probe", &cplen); +- if (cp == NULL) +- return part_probe_types_def; +- +- count = 0; +- for (l = 0; l != cplen; l++) +- if (cp[l] == 0) +- count++; +- +- res = kzalloc((count + 1)*sizeof(*res), GFP_KERNEL); +- if (!res) +- return NULL; +- count = 0; +- while (cplen > 0) { +- res[count] = cp; +- l = strlen(cp) + 1; +- cp += l; +- cplen -= l; +- count++; +- } +- return res; +-} +- +-static void of_free_probes(const char * const *probes) +-{ +- if (probes != part_probe_types_def) +- kfree(probes); +-} +- + static const struct of_device_id of_flash_match[]; + static int of_flash_probe(struct platform_device *dev) + { +- const char * const *part_probe_types; + const struct of_device_id *match; + struct device_node *dp = dev->dev.of_node; + struct resource res; +@@ -312,14 +274,8 @@ static int of_flash_probe(struct platfor + goto err_out; + + ppdata.of_node = dp; +- part_probe_types = of_get_probes(dp); +- if (!part_probe_types) { +- err = -ENOMEM; +- goto err_out; +- } +- mtd_device_parse_register(info->cmtd, part_probe_types, &ppdata, ++ mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata, + NULL, 0); +- of_free_probes(part_probe_types); + + kfree(mtd_list); + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -719,6 +720,42 @@ void deregister_mtd_parser(struct mtd_pa + EXPORT_SYMBOL_GPL(deregister_mtd_parser); + + /* ++ * Parses the linux,part-probe device tree property. ++ * When a non null value is returned it has to be freed with kfree() by ++ * the caller. ++ */ ++static const char * const *of_get_probes(struct device_node *dp) ++{ ++ const char *cp; ++ int cplen; ++ unsigned int l; ++ unsigned int count; ++ const char **res; ++ ++ cp = of_get_property(dp, "linux,part-probe", &cplen); ++ if (cp == NULL) ++ return NULL; ++ ++ count = 0; ++ for (l = 0; l != cplen; l++) ++ if (cp[l] == 0) ++ count++; ++ ++ res = kzalloc((count + 1) * sizeof(*res), GFP_KERNEL); ++ if (!res) ++ return NULL; ++ count = 0; ++ while (cplen > 0) { ++ res[count] = cp; ++ l = strlen(cp) + 1; ++ cp += l; ++ cplen -= l; ++ count++; ++ } ++ return res; ++} ++ ++/* + * Do not forget to update 'parse_mtd_partitions()' kerneldoc comment if you + * are changing this array! + */ +@@ -754,6 +791,13 @@ int parse_mtd_partitions(struct mtd_info + { + struct mtd_part_parser *parser; + int ret = 0; ++ const char *const *types_of = NULL; ++ ++ if (data && data->of_node) { ++ types_of = of_get_probes(data->of_node); ++ if (types_of != NULL) ++ types = types_of; ++ } + + if (!types) + types = default_mtd_part_types; +@@ -772,6 +816,7 @@ int parse_mtd_partitions(struct mtd_info + break; + } + } ++ kfree(types_of); + return ret; + } + diff --git a/target/linux/generic/patches-4.3/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch b/target/linux/generic/patches-4.3/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch new file mode 100644 index 0000000..fce5d29 --- /dev/null +++ b/target/linux/generic/patches-4.3/191-usb-ehci-orion-fix-probe-for-GENERIC_PHY.patch @@ -0,0 +1,35 @@ +From a95f03e51471dbdbafd3391991d867ac2358ed02 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 23 Aug 2015 14:23:29 +0200 +Subject: [PATCH] usb: ehci-orion: fix probe for !GENERIC_PHY + +Commit d445913ce0ab7f ("usb: ehci-orion: add optional PHY support") +added support for optional phys, but devm_phy_optional_get returns +-ENOSYS if GENERIC_PHY is not enabled. + +This causes probe failures, even when there are no phys specified: + +[ 1.443365] orion-ehci f1058000.usb: init f1058000.usb fail, -38 +[ 1.449403] orion-ehci: probe of f1058000.usb failed with error -38 + +Similar to dwc3, treat -ENOSYS as no phy. + +Fixes: d445913ce0ab7f ("usb: ehci-orion: add optional PHY support") + +Signed-off-by: Jonas Gorski +--- + drivers/usb/host/ehci-orion.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/ehci-orion.c ++++ b/drivers/usb/host/ehci-orion.c +@@ -224,7 +224,8 @@ static int ehci_orion_drv_probe(struct p + priv->phy = devm_phy_optional_get(&pdev->dev, "usb"); + if (IS_ERR(priv->phy)) { + err = PTR_ERR(priv->phy); +- goto err_phy_get; ++ if (err != -ENOSYS) ++ goto err_phy_get; + } else { + err = phy_init(priv->phy); + if (err) diff --git a/target/linux/generic/patches-4.3/200-fix_localversion.patch b/target/linux/generic/patches-4.3/200-fix_localversion.patch new file mode 100644 index 0000000..70228bb --- /dev/null +++ b/target/linux/generic/patches-4.3/200-fix_localversion.patch @@ -0,0 +1,11 @@ +--- a/scripts/setlocalversion ++++ b/scripts/setlocalversion +@@ -165,7 +165,7 @@ else + # annotated or signed tagged state (as git describe only + # looks at signed or annotated tags - git tag -a/-s) and + # LOCALVERSION= is not specified +- if test "${LOCALVERSION+set}" != "set"; then ++ if test "${CONFIG_LOCALVERSION+set}" != "set"; then + scm=$(scm_version --short) + res="$res${scm:++}" + fi diff --git a/target/linux/generic/patches-4.3/201-extra_optimization.patch b/target/linux/generic/patches-4.3/201-extra_optimization.patch new file mode 100644 index 0000000..625210d --- /dev/null +++ b/target/linux/generic/patches-4.3/201-extra_optimization.patch @@ -0,0 +1,14 @@ +--- a/Makefile ++++ b/Makefile +@@ -607,9 +607,9 @@ include arch/$(SRCARCH)/Makefile + KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,) + + ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE +-KBUILD_CFLAGS += -Os $(call cc-disable-warning,maybe-uninitialized,) ++KBUILD_CFLAGS += -Os $(EXTRA_OPTIMIZATION) $(call cc-disable-warning,maybe-uninitialized,) + else +-KBUILD_CFLAGS += -O2 ++KBUILD_CFLAGS += -O2 -fno-reorder-blocks -fno-tree-ch $(EXTRA_OPTIMIZATION) + endif + + # Tell gcc to never replace conditional load with a non-conditional one diff --git a/target/linux/generic/patches-4.3/202-reduce_module_size.patch b/target/linux/generic/patches-4.3/202-reduce_module_size.patch new file mode 100644 index 0000000..cef04d1 --- /dev/null +++ b/target/linux/generic/patches-4.3/202-reduce_module_size.patch @@ -0,0 +1,11 @@ +--- a/Makefile ++++ b/Makefile +@@ -398,7 +398,7 @@ KBUILD_CFLAGS_KERNEL := + KBUILD_AFLAGS := -D__ASSEMBLY__ + KBUILD_AFLAGS_MODULE := -DMODULE + KBUILD_CFLAGS_MODULE := -DMODULE +-KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds ++KBUILD_LDFLAGS_MODULE = -T $(srctree)/scripts/module-common.lds $(if $(CONFIG_PROFILING),,-s) + + # Read KERNELRELEASE from include/config/kernel.release (if it exists) + KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) diff --git a/target/linux/generic/patches-4.3/203-kallsyms_uncompressed.patch b/target/linux/generic/patches-4.3/203-kallsyms_uncompressed.patch new file mode 100644 index 0000000..cf8a447 --- /dev/null +++ b/target/linux/generic/patches-4.3/203-kallsyms_uncompressed.patch @@ -0,0 +1,108 @@ +--- a/scripts/kallsyms.c ++++ b/scripts/kallsyms.c +@@ -58,6 +58,7 @@ static struct addr_range percpu_range = + static struct sym_entry *table; + static unsigned int table_size, table_cnt; + static int all_symbols = 0; ++static int uncompressed = 0; + static int absolute_percpu = 0; + static char symbol_prefix_char = '\0'; + static unsigned long long kernel_start_addr = 0; +@@ -403,6 +404,9 @@ static void write_src(void) + + free(markers); + ++ if (uncompressed) ++ return; ++ + output_label("kallsyms_token_table"); + off = 0; + for (i = 0; i < 256; i++) { +@@ -461,6 +465,9 @@ static void *find_token(unsigned char *s + { + int i; + ++ if (uncompressed) ++ return NULL; ++ + for (i = 0; i < len - 1; i++) { + if (str[i] == token[0] && str[i+1] == token[1]) + return &str[i]; +@@ -533,6 +540,9 @@ static void optimize_result(void) + { + int i, best; + ++ if (uncompressed) ++ return; ++ + /* using the '\0' symbol last allows compress_symbols to use standard + * fast string functions */ + for (i = 255; i >= 0; i--) { +@@ -703,7 +713,9 @@ int main(int argc, char **argv) + } else if (strncmp(argv[i], "--page-offset=", 14) == 0) { + const char *p = &argv[i][14]; + kernel_start_addr = strtoull(p, NULL, 16); +- } else ++ } else if (strcmp(argv[i], "--uncompressed") == 0) ++ uncompressed = 1; ++ else + usage(); + } + } else if (argc != 1) +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1345,6 +1345,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW + the unaligned access emulation. + see arch/parisc/kernel/unaligned.c for reference + ++config KALLSYMS_UNCOMPRESSED ++ bool "Keep kallsyms uncompressed" ++ depends on KALLSYMS ++ help ++ Normally kallsyms contains compressed symbols (using a token table), ++ reducing the uncompressed kernel image size. Keeping the symbol table ++ uncompressed significantly improves the size of this part in compressed ++ kernel images. ++ ++ Say N unless you need compressed kernel images to be small. ++ + config HAVE_PCSPKR_PLATFORM + bool + +--- a/scripts/link-vmlinux.sh ++++ b/scripts/link-vmlinux.sh +@@ -90,6 +90,10 @@ kallsyms() + kallsymopt="${kallsymopt} --absolute-percpu" + fi + ++ if [ -n "${CONFIG_KALLSYMS_UNCOMPRESSED}" ]; then ++ kallsymopt="${kallsymopt} --uncompressed" ++ fi ++ + local aflags="${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL} \ + ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS}" + +--- a/kernel/kallsyms.c ++++ b/kernel/kallsyms.c +@@ -109,6 +109,11 @@ static unsigned int kallsyms_expand_symb + * For every byte on the compressed symbol data, copy the table + * entry for that byte. + */ ++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED ++ memcpy(result, data + 1, len - 1); ++ result += len - 1; ++ len = 0; ++#endif + while (len) { + tptr = &kallsyms_token_table[kallsyms_token_index[*data]]; + data++; +@@ -141,6 +146,9 @@ tail: + */ + static char kallsyms_get_symbol_type(unsigned int off) + { ++#ifdef CONFIG_KALLSYMS_UNCOMPRESSED ++ return kallsyms_names[off + 1]; ++#endif + /* + * Get just the first code, look it up in the token table, + * and return the first char from this token. diff --git a/target/linux/generic/patches-4.3/204-module_strip.patch b/target/linux/generic/patches-4.3/204-module_strip.patch new file mode 100644 index 0000000..4080ee6 --- /dev/null +++ b/target/linux/generic/patches-4.3/204-module_strip.patch @@ -0,0 +1,194 @@ +From: Felix Fietkau +Subject: [PATCH] build: add a hack for removing non-essential module info + +Signed-off-by: Felix Fietkau +--- +--- a/include/linux/module.h ++++ b/include/linux/module.h +@@ -169,9 +169,10 @@ void trim_init_extable(struct module *m) + + /* Generic info of form tag = "info" */ + #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info) ++#define MODULE_INFO_STRIP(tag, info) __MODULE_INFO_STRIP(tag, tag, info) + + /* For userspace: you can also call me... */ +-#define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias) ++#define MODULE_ALIAS(_alias) MODULE_INFO_STRIP(alias, _alias) + + /* Soft module dependencies. See man modprobe.d for details. + * Example: MODULE_SOFTDEP("pre: module-foo module-bar post: module-baz") +@@ -212,12 +213,12 @@ void trim_init_extable(struct module *m) + * Author(s), use "Name " or just "Name", for multiple + * authors use multiple MODULE_AUTHOR() statements/lines. + */ +-#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author) ++#define MODULE_AUTHOR(_author) MODULE_INFO_STRIP(author, _author) + + /* What your module does. */ +-#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description) ++#define MODULE_DESCRIPTION(_description) MODULE_INFO_STRIP(description, _description) + +-#ifdef MODULE ++#if defined(MODULE) && !defined(CONFIG_MODULE_STRIPPED) + /* Creates an alias so file2alias.c can find device table. */ + #define MODULE_DEVICE_TABLE(type, name) \ + extern const typeof(name) __mod_##type##__##name##_device_table \ +@@ -244,7 +245,9 @@ extern const typeof(name) __mod_##type## + */ + + #if defined(MODULE) || !defined(CONFIG_SYSFS) +-#define MODULE_VERSION(_version) MODULE_INFO(version, _version) ++#define MODULE_VERSION(_version) MODULE_INFO_STRIP(version, _version) ++#elif defined(CONFIG_MODULE_STRIPPED) ++#define MODULE_VERSION(_version) __MODULE_INFO_DISABLED(version) + #else + #define MODULE_VERSION(_version) \ + static struct module_version_attribute ___modver_attr = { \ +@@ -266,7 +269,7 @@ extern const typeof(name) __mod_##type## + /* Optional firmware file (or files) needed by the module + * format is simply firmware file name. Multiple firmware + * files require multiple MODULE_FIRMWARE() specifiers */ +-#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware) ++#define MODULE_FIRMWARE(_firmware) MODULE_INFO_STRIP(firmware, _firmware) + + /* Given an address, look for it in the exception tables */ + const struct exception_table_entry *search_exception_tables(unsigned long add); +--- a/include/linux/moduleparam.h ++++ b/include/linux/moduleparam.h +@@ -16,6 +16,16 @@ + /* Chosen so that structs with an unsigned long line up. */ + #define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long)) + ++/* This struct is here for syntactic coherency, it is not used */ ++#define __MODULE_INFO_DISABLED(name) \ ++ struct __UNIQUE_ID(name) {} ++ ++#ifdef CONFIG_MODULE_STRIPPED ++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO_DISABLED(name) ++#else ++#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO(tag, name, info) ++#endif ++ + #ifdef MODULE + #define __MODULE_INFO(tag, name, info) \ + static const char __UNIQUE_ID(name)[] \ +@@ -23,8 +33,7 @@ static const char __UNIQUE_ID(name)[] + = __stringify(tag) "=" info + #else /* !MODULE */ + /* This struct is here for syntactic coherency, it is not used */ +-#define __MODULE_INFO(tag, name, info) \ +- struct __UNIQUE_ID(name) {} ++#define __MODULE_INFO(tag, name, info) __MODULE_INFO_DISABLED(name) + #endif + #define __MODULE_PARM_TYPE(name, _type) \ + __MODULE_INFO(parmtype, name##type, #name ":" _type) +@@ -32,7 +41,7 @@ static const char __UNIQUE_ID(name)[] + /* One for each parameter, describing how to use it. Some files do + multiple of these per line, so can't just use MODULE_INFO. */ + #define MODULE_PARM_DESC(_parm, desc) \ +- __MODULE_INFO(parm, _parm, #_parm ":" desc) ++ __MODULE_INFO_STRIP(parm, _parm, #_parm ":" desc) + + struct kernel_param; + +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -2026,6 +2026,13 @@ config MODULE_COMPRESS_XZ + + endchoice + ++config MODULE_STRIPPED ++ bool "Reduce module size" ++ depends on MODULES ++ help ++ Remove module parameter descriptions, author info, version, aliases, ++ device tables, etc. ++ + endif # MODULES + + config MODULES_TREE_LOOKUP +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -2836,6 +2836,7 @@ static struct module *setup_load_info(st + + static int check_modinfo(struct module *mod, struct load_info *info, int flags) + { ++#ifndef CONFIG_MODULE_STRIPPED + const char *modmagic = get_modinfo(info, "vermagic"); + int err; + +@@ -2861,6 +2862,7 @@ static int check_modinfo(struct module * + pr_warn("%s: module is from the staging directory, the quality " + "is unknown, you have been warned.\n", mod->name); + } ++#endif + + /* Set up license info based on the info section */ + set_license(mod, get_modinfo(info, "license")); +--- a/scripts/mod/modpost.c ++++ b/scripts/mod/modpost.c +@@ -1960,7 +1960,9 @@ static void read_symbols(char *modname) + symname = remove_dot(info.strtab + sym->st_name); + + handle_modversions(mod, &info, sym, symname); ++#ifndef CONFIG_MODULE_STRIPPED + handle_moddevtable(mod, &info, sym, symname); ++#endif + } + if (!is_vmlinux(modname) || + (is_vmlinux(modname) && vmlinux_section_warnings)) +@@ -2104,7 +2106,9 @@ static void add_header(struct buffer *b, + buf_printf(b, "#include \n"); + buf_printf(b, "#include \n"); + buf_printf(b, "\n"); ++#ifndef CONFIG_MODULE_STRIPPED + buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n"); ++#endif + buf_printf(b, "\n"); + buf_printf(b, "__visible struct module __this_module\n"); + buf_printf(b, "__attribute__((section(\".gnu.linkonce.this_module\"))) = {\n"); +@@ -2121,16 +2125,20 @@ static void add_header(struct buffer *b, + + static void add_intree_flag(struct buffer *b, int is_intree) + { ++#ifndef CONFIG_MODULE_STRIPPED + if (is_intree) + buf_printf(b, "\nMODULE_INFO(intree, \"Y\");\n"); ++#endif + } + + static void add_staging_flag(struct buffer *b, const char *name) + { ++#ifndef CONFIG_MODULE_STRIPPED + static const char *staging_dir = "drivers/staging"; + + if (strncmp(staging_dir, name, strlen(staging_dir)) == 0) + buf_printf(b, "\nMODULE_INFO(staging, \"Y\");\n"); ++#endif + } + + /** +@@ -2223,11 +2231,13 @@ static void add_depends(struct buffer *b + + static void add_srcversion(struct buffer *b, struct module *mod) + { ++#ifndef CONFIG_MODULE_STRIPPED + if (mod->srcversion[0]) { + buf_printf(b, "\n"); + buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n", + mod->srcversion); + } ++#endif + } + + static void write_if_changed(struct buffer *b, const char *fname) +@@ -2458,7 +2468,9 @@ int main(int argc, char **argv) + add_staging_flag(&buf, mod->name); + err |= add_versions(&buf, mod); + add_depends(&buf, mod, modules); ++#ifndef CONFIG_MODULE_STRIPPED + add_moddevtable(&buf, mod); ++#endif + add_srcversion(&buf, mod); + + sprintf(fname, "%s.mod.c", mod->name); diff --git a/target/linux/generic/patches-4.3/205-backtrace_module_info.patch b/target/linux/generic/patches-4.3/205-backtrace_module_info.patch new file mode 100644 index 0000000..0550ec4 --- /dev/null +++ b/target/linux/generic/patches-4.3/205-backtrace_module_info.patch @@ -0,0 +1,36 @@ +--- a/lib/vsprintf.c ++++ b/lib/vsprintf.c +@@ -618,8 +618,10 @@ char *symbol_string(char *buf, char *end + struct printf_spec spec, const char *fmt) + { + unsigned long value; +-#ifdef CONFIG_KALLSYMS + char sym[KSYM_SYMBOL_LEN]; ++#ifndef CONFIG_KALLSYMS ++ struct module *mod; ++ int len; + #endif + + if (fmt[1] == 'R') +@@ -633,15 +635,15 @@ char *symbol_string(char *buf, char *end + sprint_symbol(sym, value); + else + sprint_symbol_no_offset(sym, value); +- +- return string(buf, end, sym, spec); + #else +- spec.field_width = 2 * sizeof(void *); +- spec.flags |= SPECIAL | SMALL | ZEROPAD; +- spec.base = 16; ++ len = snprintf(sym, sizeof(sym), "0x%lx", value); + +- return number(buf, end, value, spec); ++ mod = __module_address(value); ++ if (mod) ++ snprintf(sym + len, sizeof(sym) - len, " [%s@%p+0x%x]", ++ mod->name, mod->module_core, mod->core_size); + #endif ++ return string(buf, end, sym, spec); + } + + static noinline_for_stack diff --git a/target/linux/generic/patches-4.3/210-darwin_scripts_include.patch b/target/linux/generic/patches-4.3/210-darwin_scripts_include.patch new file mode 100644 index 0000000..63f618a --- /dev/null +++ b/target/linux/generic/patches-4.3/210-darwin_scripts_include.patch @@ -0,0 +1,3088 @@ +--- a/scripts/kallsyms.c ++++ b/scripts/kallsyms.c +@@ -22,6 +22,35 @@ + #include + #include + #include ++#ifdef __APPLE__ ++/* Darwin has no memmem implementation, this one is ripped of the uClibc-0.9.28 source */ ++void *memmem (const void *haystack, size_t haystack_len, ++ const void *needle, size_t needle_len) ++{ ++ const char *begin; ++ const char *const last_possible ++ = (const char *) haystack + haystack_len - needle_len; ++ ++ if (needle_len == 0) ++ /* The first occurrence of the empty string is deemed to occur at ++ the beginning of the string. */ ++ return (void *) haystack; ++ ++ /* Sanity check, otherwise the loop might search through the whole ++ memory. */ ++ if (__builtin_expect (haystack_len < needle_len, 0)) ++ return NULL; ++ ++ for (begin = (const char *) haystack; begin <= last_possible; ++begin) ++ if (begin[0] == ((const char *) needle)[0] && ++ !memcmp ((const void *) &begin[1], ++ (const void *) ((const char *) needle + 1), ++ needle_len - 1)) ++ return (void *) begin; ++ ++ return NULL; ++} ++#endif + + #ifndef ARRAY_SIZE + #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) +--- a/scripts/kconfig/Makefile ++++ b/scripts/kconfig/Makefile +@@ -156,6 +156,9 @@ check-lxdialog := $(srctree)/$(src)/lxd + # we really need to do so. (Do not call gcc as part of make mrproper) + HOST_EXTRACFLAGS += $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags) \ + -DLOCALE ++ifeq ($(shell uname -s),Darwin) ++HOST_LOADLIBES += -lncurses ++endif + + # =========================================================================== + # Shared Makefile for the various kconfig executables: +--- a/scripts/mod/mk_elfconfig.c ++++ b/scripts/mod/mk_elfconfig.c +@@ -1,7 +1,11 @@ + #include + #include + #include ++#ifndef __APPLE__ + #include ++#else ++#include "elf.h" ++#endif + + int + main(int argc, char **argv) +--- a/scripts/mod/modpost.h ++++ b/scripts/mod/modpost.h +@@ -7,7 +7,11 @@ + #include + #include + #include ++#if !(defined(__APPLE__) || defined(__CYGWIN__)) + #include ++#else ++#include "elf.h" ++#endif + + #include "elfconfig.h" + +--- /dev/null ++++ b/scripts/mod/elf.h +@@ -0,0 +1,3007 @@ ++/* This file defines standard ELF types, structures, and macros. ++ Copyright (C) 1995-2012 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, see ++ . */ ++ ++#ifndef _ELF_H ++#define _ELF_H 1 ++ ++/* Standard ELF types. */ ++ ++#include ++ ++/* Type for a 16-bit quantity. */ ++typedef uint16_t Elf32_Half; ++typedef uint16_t Elf64_Half; ++ ++/* Types for signed and unsigned 32-bit quantities. */ ++typedef uint32_t Elf32_Word; ++typedef int32_t Elf32_Sword; ++typedef uint32_t Elf64_Word; ++typedef int32_t Elf64_Sword; ++ ++/* Types for signed and unsigned 64-bit quantities. */ ++typedef uint64_t Elf32_Xword; ++typedef int64_t Elf32_Sxword; ++typedef uint64_t Elf64_Xword; ++typedef int64_t Elf64_Sxword; ++ ++/* Type of addresses. */ ++typedef uint32_t Elf32_Addr; ++typedef uint64_t Elf64_Addr; ++ ++/* Type of file offsets. */ ++typedef uint32_t Elf32_Off; ++typedef uint64_t Elf64_Off; ++ ++/* Type for section indices, which are 16-bit quantities. */ ++typedef uint16_t Elf32_Section; ++typedef uint16_t Elf64_Section; ++ ++/* Type for version symbol information. */ ++typedef Elf32_Half Elf32_Versym; ++typedef Elf64_Half Elf64_Versym; ++ ++ ++/* The ELF file header. This appears at the start of every ELF file. */ ++ ++#define EI_NIDENT (16) ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf32_Half e_type; /* Object file type */ ++ Elf32_Half e_machine; /* Architecture */ ++ Elf32_Word e_version; /* Object file version */ ++ Elf32_Addr e_entry; /* Entry point virtual address */ ++ Elf32_Off e_phoff; /* Program header table file offset */ ++ Elf32_Off e_shoff; /* Section header table file offset */ ++ Elf32_Word e_flags; /* Processor-specific flags */ ++ Elf32_Half e_ehsize; /* ELF header size in bytes */ ++ Elf32_Half e_phentsize; /* Program header table entry size */ ++ Elf32_Half e_phnum; /* Program header table entry count */ ++ Elf32_Half e_shentsize; /* Section header table entry size */ ++ Elf32_Half e_shnum; /* Section header table entry count */ ++ Elf32_Half e_shstrndx; /* Section header string table index */ ++} Elf32_Ehdr; ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf64_Half e_type; /* Object file type */ ++ Elf64_Half e_machine; /* Architecture */ ++ Elf64_Word e_version; /* Object file version */ ++ Elf64_Addr e_entry; /* Entry point virtual address */ ++ Elf64_Off e_phoff; /* Program header table file offset */ ++ Elf64_Off e_shoff; /* Section header table file offset */ ++ Elf64_Word e_flags; /* Processor-specific flags */ ++ Elf64_Half e_ehsize; /* ELF header size in bytes */ ++ Elf64_Half e_phentsize; /* Program header table entry size */ ++ Elf64_Half e_phnum; /* Program header table entry count */ ++ Elf64_Half e_shentsize; /* Section header table entry size */ ++ Elf64_Half e_shnum; /* Section header table entry count */ ++ Elf64_Half e_shstrndx; /* Section header string table index */ ++} Elf64_Ehdr; ++ ++/* Fields in the e_ident array. The EI_* macros are indices into the ++ array. The macros under each EI_* macro are the values the byte ++ may have. */ ++ ++#define EI_MAG0 0 /* File identification byte 0 index */ ++#define ELFMAG0 0x7f /* Magic number byte 0 */ ++ ++#define EI_MAG1 1 /* File identification byte 1 index */ ++#define ELFMAG1 'E' /* Magic number byte 1 */ ++ ++#define EI_MAG2 2 /* File identification byte 2 index */ ++#define ELFMAG2 'L' /* Magic number byte 2 */ ++ ++#define EI_MAG3 3 /* File identification byte 3 index */ ++#define ELFMAG3 'F' /* Magic number byte 3 */ ++ ++/* Conglomeration of the identification bytes, for easy testing as a word. */ ++#define ELFMAG "\177ELF" ++#define SELFMAG 4 ++ ++#define EI_CLASS 4 /* File class byte index */ ++#define ELFCLASSNONE 0 /* Invalid class */ ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++#define ELFCLASSNUM 3 ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATANONE 0 /* Invalid data encoding */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ ++#define ELFDATANUM 3 ++ ++#define EI_VERSION 6 /* File version byte index */ ++ /* Value must be EV_CURRENT */ ++ ++#define EI_OSABI 7 /* OS ABI identification */ ++#define ELFOSABI_NONE 0 /* UNIX System V ABI */ ++#define ELFOSABI_SYSV 0 /* Alias. */ ++#define ELFOSABI_HPUX 1 /* HP-UX */ ++#define ELFOSABI_NETBSD 2 /* NetBSD. */ ++#define ELFOSABI_GNU 3 /* Object uses GNU ELF extensions. */ ++#define ELFOSABI_LINUX ELFOSABI_GNU /* Compatibility alias. */ ++#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ ++#define ELFOSABI_AIX 7 /* IBM AIX. */ ++#define ELFOSABI_IRIX 8 /* SGI Irix. */ ++#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ ++#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ ++#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ ++#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ ++#define ELFOSABI_ARM_AEABI 64 /* ARM EABI */ ++#define ELFOSABI_ARM 97 /* ARM */ ++#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ ++ ++#define EI_ABIVERSION 8 /* ABI version */ ++ ++#define EI_PAD 9 /* Byte index of padding bytes */ ++ ++/* Legal values for e_type (object file type). */ ++ ++#define ET_NONE 0 /* No file type */ ++#define ET_REL 1 /* Relocatable file */ ++#define ET_EXEC 2 /* Executable file */ ++#define ET_DYN 3 /* Shared object file */ ++#define ET_CORE 4 /* Core file */ ++#define ET_NUM 5 /* Number of defined types */ ++#define ET_LOOS 0xfe00 /* OS-specific range start */ ++#define ET_HIOS 0xfeff /* OS-specific range end */ ++#define ET_LOPROC 0xff00 /* Processor-specific range start */ ++#define ET_HIPROC 0xffff /* Processor-specific range end */ ++ ++/* Legal values for e_machine (architecture). */ ++ ++#define EM_NONE 0 /* No machine */ ++#define EM_M32 1 /* AT&T WE 32100 */ ++#define EM_SPARC 2 /* SUN SPARC */ ++#define EM_386 3 /* Intel 80386 */ ++#define EM_68K 4 /* Motorola m68k family */ ++#define EM_88K 5 /* Motorola m88k family */ ++#define EM_860 7 /* Intel 80860 */ ++#define EM_MIPS 8 /* MIPS R3000 big-endian */ ++#define EM_S370 9 /* IBM System/370 */ ++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ ++ ++#define EM_PARISC 15 /* HPPA */ ++#define EM_VPP500 17 /* Fujitsu VPP500 */ ++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ ++#define EM_960 19 /* Intel 80960 */ ++#define EM_PPC 20 /* PowerPC */ ++#define EM_PPC64 21 /* PowerPC 64-bit */ ++#define EM_S390 22 /* IBM S390 */ ++ ++#define EM_V800 36 /* NEC V800 series */ ++#define EM_FR20 37 /* Fujitsu FR20 */ ++#define EM_RH32 38 /* TRW RH-32 */ ++#define EM_RCE 39 /* Motorola RCE */ ++#define EM_ARM 40 /* ARM */ ++#define EM_FAKE_ALPHA 41 /* Digital Alpha */ ++#define EM_SH 42 /* Hitachi SH */ ++#define EM_SPARCV9 43 /* SPARC v9 64-bit */ ++#define EM_TRICORE 44 /* Siemens Tricore */ ++#define EM_ARC 45 /* Argonaut RISC Core */ ++#define EM_H8_300 46 /* Hitachi H8/300 */ ++#define EM_H8_300H 47 /* Hitachi H8/300H */ ++#define EM_H8S 48 /* Hitachi H8S */ ++#define EM_H8_500 49 /* Hitachi H8/500 */ ++#define EM_IA_64 50 /* Intel Merced */ ++#define EM_MIPS_X 51 /* Stanford MIPS-X */ ++#define EM_COLDFIRE 52 /* Motorola Coldfire */ ++#define EM_68HC12 53 /* Motorola M68HC12 */ ++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ ++#define EM_PCP 55 /* Siemens PCP */ ++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ ++#define EM_NDR1 57 /* Denso NDR1 microprocessor */ ++#define EM_STARCORE 58 /* Motorola Start*Core processor */ ++#define EM_ME16 59 /* Toyota ME16 processor */ ++#define EM_ST100 60 /* STMicroelectronic ST100 processor */ ++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ ++#define EM_X86_64 62 /* AMD x86-64 architecture */ ++#define EM_PDSP 63 /* Sony DSP Processor */ ++ ++#define EM_FX66 66 /* Siemens FX66 microcontroller */ ++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ ++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ ++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ ++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ ++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ ++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ ++#define EM_SVX 73 /* Silicon Graphics SVx */ ++#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ ++#define EM_VAX 75 /* Digital VAX */ ++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ ++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ ++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ ++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ ++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ ++#define EM_HUANY 81 /* Harvard University machine-independent object files */ ++#define EM_PRISM 82 /* SiTera Prism */ ++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ ++#define EM_FR30 84 /* Fujitsu FR30 */ ++#define EM_D10V 85 /* Mitsubishi D10V */ ++#define EM_D30V 86 /* Mitsubishi D30V */ ++#define EM_V850 87 /* NEC v850 */ ++#define EM_M32R 88 /* Mitsubishi M32R */ ++#define EM_MN10300 89 /* Matsushita MN10300 */ ++#define EM_MN10200 90 /* Matsushita MN10200 */ ++#define EM_PJ 91 /* picoJava */ ++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ ++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ ++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ ++#define EM_TILEPRO 188 /* Tilera TILEPro */ ++#define EM_TILEGX 191 /* Tilera TILE-Gx */ ++#define EM_NUM 192 ++ ++/* If it is necessary to assign new unofficial EM_* values, please ++ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the ++ chances of collision with official or non-GNU unofficial values. */ ++ ++#define EM_ALPHA 0x9026 ++ ++/* Legal values for e_version (version). */ ++ ++#define EV_NONE 0 /* Invalid ELF version */ ++#define EV_CURRENT 1 /* Current version */ ++#define EV_NUM 2 ++ ++/* Section header. */ ++ ++typedef struct ++{ ++ Elf32_Word sh_name; /* Section name (string tbl index) */ ++ Elf32_Word sh_type; /* Section type */ ++ Elf32_Word sh_flags; /* Section flags */ ++ Elf32_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf32_Off sh_offset; /* Section file offset */ ++ Elf32_Word sh_size; /* Section size in bytes */ ++ Elf32_Word sh_link; /* Link to another section */ ++ Elf32_Word sh_info; /* Additional section information */ ++ Elf32_Word sh_addralign; /* Section alignment */ ++ Elf32_Word sh_entsize; /* Entry size if section holds table */ ++} Elf32_Shdr; ++ ++typedef struct ++{ ++ Elf64_Word sh_name; /* Section name (string tbl index) */ ++ Elf64_Word sh_type; /* Section type */ ++ Elf64_Xword sh_flags; /* Section flags */ ++ Elf64_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf64_Off sh_offset; /* Section file offset */ ++ Elf64_Xword sh_size; /* Section size in bytes */ ++ Elf64_Word sh_link; /* Link to another section */ ++ Elf64_Word sh_info; /* Additional section information */ ++ Elf64_Xword sh_addralign; /* Section alignment */ ++ Elf64_Xword sh_entsize; /* Entry size if section holds table */ ++} Elf64_Shdr; ++ ++/* Special section indices. */ ++ ++#define SHN_UNDEF 0 /* Undefined section */ ++#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ ++#define SHN_LOPROC 0xff00 /* Start of processor-specific */ ++#define SHN_BEFORE 0xff00 /* Order section before all others ++ (Solaris). */ ++#define SHN_AFTER 0xff01 /* Order section after all others ++ (Solaris). */ ++#define SHN_HIPROC 0xff1f /* End of processor-specific */ ++#define SHN_LOOS 0xff20 /* Start of OS-specific */ ++#define SHN_HIOS 0xff3f /* End of OS-specific */ ++#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ ++#define SHN_COMMON 0xfff2 /* Associated symbol is common */ ++#define SHN_XINDEX 0xffff /* Index is in extra table. */ ++#define SHN_HIRESERVE 0xffff /* End of reserved indices */ ++ ++/* Legal values for sh_type (section type). */ ++ ++#define SHT_NULL 0 /* Section header table entry unused */ ++#define SHT_PROGBITS 1 /* Program data */ ++#define SHT_SYMTAB 2 /* Symbol table */ ++#define SHT_STRTAB 3 /* String table */ ++#define SHT_RELA 4 /* Relocation entries with addends */ ++#define SHT_HASH 5 /* Symbol hash table */ ++#define SHT_DYNAMIC 6 /* Dynamic linking information */ ++#define SHT_NOTE 7 /* Notes */ ++#define SHT_NOBITS 8 /* Program space with no data (bss) */ ++#define SHT_REL 9 /* Relocation entries, no addends */ ++#define SHT_SHLIB 10 /* Reserved */ ++#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ ++#define SHT_INIT_ARRAY 14 /* Array of constructors */ ++#define SHT_FINI_ARRAY 15 /* Array of destructors */ ++#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ ++#define SHT_GROUP 17 /* Section group */ ++#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ ++#define SHT_NUM 19 /* Number of defined types. */ ++#define SHT_LOOS 0x60000000 /* Start OS-specific. */ ++#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes. */ ++#define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ ++#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ ++#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ ++#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ ++#define SHT_SUNW_move 0x6ffffffa ++#define SHT_SUNW_COMDAT 0x6ffffffb ++#define SHT_SUNW_syminfo 0x6ffffffc ++#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ ++#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ ++#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ ++#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ ++#define SHT_HIOS 0x6fffffff /* End OS-specific type */ ++#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define SHT_LOUSER 0x80000000 /* Start of application-specific */ ++#define SHT_HIUSER 0x8fffffff /* End of application-specific */ ++ ++/* Legal values for sh_flags (section flags). */ ++ ++#define SHF_WRITE (1 << 0) /* Writable */ ++#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ ++#define SHF_EXECINSTR (1 << 2) /* Executable */ ++#define SHF_MERGE (1 << 4) /* Might be merged */ ++#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ ++#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ ++#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ ++#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling ++ required */ ++#define SHF_GROUP (1 << 9) /* Section is member of a group. */ ++#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ ++#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ ++#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ ++#define SHF_ORDERED (1 << 30) /* Special ordering requirement ++ (Solaris). */ ++#define SHF_EXCLUDE (1 << 31) /* Section is excluded unless ++ referenced or allocated (Solaris).*/ ++ ++/* Section group handling. */ ++#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ ++ ++/* Symbol table entry. */ ++ ++typedef struct ++{ ++ Elf32_Word st_name; /* Symbol name (string tbl index) */ ++ Elf32_Addr st_value; /* Symbol value */ ++ Elf32_Word st_size; /* Symbol size */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf32_Section st_shndx; /* Section index */ ++} Elf32_Sym; ++ ++typedef struct ++{ ++ Elf64_Word st_name; /* Symbol name (string tbl index) */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf64_Section st_shndx; /* Section index */ ++ Elf64_Addr st_value; /* Symbol value */ ++ Elf64_Xword st_size; /* Symbol size */ ++} Elf64_Sym; ++ ++/* The syminfo section if available contains additional information about ++ every dynamic symbol. */ ++ ++typedef struct ++{ ++ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf32_Half si_flags; /* Per symbol flags */ ++} Elf32_Syminfo; ++ ++typedef struct ++{ ++ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf64_Half si_flags; /* Per symbol flags */ ++} Elf64_Syminfo; ++ ++/* Possible values for si_boundto. */ ++#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ ++#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ ++#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ ++ ++/* Possible bitmasks for si_flags. */ ++#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ ++#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ ++#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ ++#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy ++ loaded */ ++/* Syminfo version values. */ ++#define SYMINFO_NONE 0 ++#define SYMINFO_CURRENT 1 ++#define SYMINFO_NUM 2 ++ ++ ++/* How to extract and insert information held in the st_info field. */ ++ ++#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) ++#define ELF32_ST_TYPE(val) ((val) & 0xf) ++#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) ++ ++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ ++#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) ++#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) ++#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) ++ ++/* Legal values for ST_BIND subfield of st_info (symbol binding). */ ++ ++#define STB_LOCAL 0 /* Local symbol */ ++#define STB_GLOBAL 1 /* Global symbol */ ++#define STB_WEAK 2 /* Weak symbol */ ++#define STB_NUM 3 /* Number of defined types. */ ++#define STB_LOOS 10 /* Start of OS-specific */ ++#define STB_GNU_UNIQUE 10 /* Unique symbol. */ ++#define STB_HIOS 12 /* End of OS-specific */ ++#define STB_LOPROC 13 /* Start of processor-specific */ ++#define STB_HIPROC 15 /* End of processor-specific */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_NOTYPE 0 /* Symbol type is unspecified */ ++#define STT_OBJECT 1 /* Symbol is a data object */ ++#define STT_FUNC 2 /* Symbol is a code object */ ++#define STT_SECTION 3 /* Symbol associated with a section */ ++#define STT_FILE 4 /* Symbol's name is file name */ ++#define STT_COMMON 5 /* Symbol is a common data object */ ++#define STT_TLS 6 /* Symbol is thread-local data object*/ ++#define STT_NUM 7 /* Number of defined types. */ ++#define STT_LOOS 10 /* Start of OS-specific */ ++#define STT_GNU_IFUNC 10 /* Symbol is indirect code object */ ++#define STT_HIOS 12 /* End of OS-specific */ ++#define STT_LOPROC 13 /* Start of processor-specific */ ++#define STT_HIPROC 15 /* End of processor-specific */ ++ ++ ++/* Symbol table indices are found in the hash buckets and chain table ++ of a symbol hash table section. This special index value indicates ++ the end of a chain, meaning no further symbols are found in that bucket. */ ++ ++#define STN_UNDEF 0 /* End of a chain. */ ++ ++ ++/* How to extract and insert information held in the st_other field. */ ++ ++#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) ++ ++/* For ELF64 the definitions are the same. */ ++#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) ++ ++/* Symbol visibility specification encoded in the st_other field. */ ++#define STV_DEFAULT 0 /* Default symbol visibility rules */ ++#define STV_INTERNAL 1 /* Processor specific hidden class */ ++#define STV_HIDDEN 2 /* Sym unavailable in other modules */ ++#define STV_PROTECTED 3 /* Not preemptible, not exported */ ++ ++ ++/* Relocation table entry without addend (in section of type SHT_REL). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++} Elf32_Rel; ++ ++/* I have seen two different definitions of the Elf64_Rel and ++ Elf64_Rela structures, so we'll leave them out until Novell (or ++ whoever) gets their act together. */ ++/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++} Elf64_Rel; ++ ++/* Relocation table entry with addend (in section of type SHT_RELA). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++ Elf32_Sword r_addend; /* Addend */ ++} Elf32_Rela; ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++ Elf64_Sxword r_addend; /* Addend */ ++} Elf64_Rela; ++ ++/* How to extract and insert information held in the r_info field. */ ++ ++#define ELF32_R_SYM(val) ((val) >> 8) ++#define ELF32_R_TYPE(val) ((val) & 0xff) ++#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) ++ ++#define ELF64_R_SYM(i) ((i) >> 32) ++#define ELF64_R_TYPE(i) ((i) & 0xffffffff) ++#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) ++ ++/* Program segment header. */ ++ ++typedef struct ++{ ++ Elf32_Word p_type; /* Segment type */ ++ Elf32_Off p_offset; /* Segment file offset */ ++ Elf32_Addr p_vaddr; /* Segment virtual address */ ++ Elf32_Addr p_paddr; /* Segment physical address */ ++ Elf32_Word p_filesz; /* Segment size in file */ ++ Elf32_Word p_memsz; /* Segment size in memory */ ++ Elf32_Word p_flags; /* Segment flags */ ++ Elf32_Word p_align; /* Segment alignment */ ++} Elf32_Phdr; ++ ++typedef struct ++{ ++ Elf64_Word p_type; /* Segment type */ ++ Elf64_Word p_flags; /* Segment flags */ ++ Elf64_Off p_offset; /* Segment file offset */ ++ Elf64_Addr p_vaddr; /* Segment virtual address */ ++ Elf64_Addr p_paddr; /* Segment physical address */ ++ Elf64_Xword p_filesz; /* Segment size in file */ ++ Elf64_Xword p_memsz; /* Segment size in memory */ ++ Elf64_Xword p_align; /* Segment alignment */ ++} Elf64_Phdr; ++ ++/* Special value for e_phnum. This indicates that the real number of ++ program headers is too large to fit into e_phnum. Instead the real ++ value is in the field sh_info of section 0. */ ++ ++#define PN_XNUM 0xffff ++ ++/* Legal values for p_type (segment type). */ ++ ++#define PT_NULL 0 /* Program header table entry unused */ ++#define PT_LOAD 1 /* Loadable program segment */ ++#define PT_DYNAMIC 2 /* Dynamic linking information */ ++#define PT_INTERP 3 /* Program interpreter */ ++#define PT_NOTE 4 /* Auxiliary information */ ++#define PT_SHLIB 5 /* Reserved */ ++#define PT_PHDR 6 /* Entry for header table itself */ ++#define PT_TLS 7 /* Thread-local storage segment */ ++#define PT_NUM 8 /* Number of defined types */ ++#define PT_LOOS 0x60000000 /* Start of OS-specific */ ++#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ ++#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ ++#define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ ++#define PT_LOSUNW 0x6ffffffa ++#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ ++#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ ++#define PT_HISUNW 0x6fffffff ++#define PT_HIOS 0x6fffffff /* End of OS-specific */ ++#define PT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define PT_HIPROC 0x7fffffff /* End of processor-specific */ ++ ++/* Legal values for p_flags (segment flags). */ ++ ++#define PF_X (1 << 0) /* Segment is executable */ ++#define PF_W (1 << 1) /* Segment is writable */ ++#define PF_R (1 << 2) /* Segment is readable */ ++#define PF_MASKOS 0x0ff00000 /* OS-specific */ ++#define PF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Legal values for note segment descriptor types for core files. */ ++ ++#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ ++#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ ++#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ ++#define NT_PRXREG 4 /* Contains copy of prxregset struct */ ++#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ ++#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ ++#define NT_AUXV 6 /* Contains copy of auxv array */ ++#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ ++#define NT_ASRS 8 /* Contains copy of asrset struct */ ++#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ ++#define NT_PSINFO 13 /* Contains copy of psinfo struct */ ++#define NT_PRCRED 14 /* Contains copy of prcred struct */ ++#define NT_UTSNAME 15 /* Contains copy of utsname struct */ ++#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ ++#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ ++#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ ++#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ ++#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ ++#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ ++#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ ++#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ ++#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ ++#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ ++ ++/* Legal values for the note segment descriptor types for object files. */ ++ ++#define NT_VERSION 1 /* Contains a version string. */ ++ ++ ++/* Dynamic section entry. */ ++ ++typedef struct ++{ ++ Elf32_Sword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf32_Word d_val; /* Integer value */ ++ Elf32_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf32_Dyn; ++ ++typedef struct ++{ ++ Elf64_Sxword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf64_Xword d_val; /* Integer value */ ++ Elf64_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf64_Dyn; ++ ++/* Legal values for d_tag (dynamic entry type). */ ++ ++#define DT_NULL 0 /* Marks end of dynamic section */ ++#define DT_NEEDED 1 /* Name of needed library */ ++#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ ++#define DT_PLTGOT 3 /* Processor defined value */ ++#define DT_HASH 4 /* Address of symbol hash table */ ++#define DT_STRTAB 5 /* Address of string table */ ++#define DT_SYMTAB 6 /* Address of symbol table */ ++#define DT_RELA 7 /* Address of Rela relocs */ ++#define DT_RELASZ 8 /* Total size of Rela relocs */ ++#define DT_RELAENT 9 /* Size of one Rela reloc */ ++#define DT_STRSZ 10 /* Size of string table */ ++#define DT_SYMENT 11 /* Size of one symbol table entry */ ++#define DT_INIT 12 /* Address of init function */ ++#define DT_FINI 13 /* Address of termination function */ ++#define DT_SONAME 14 /* Name of shared object */ ++#define DT_RPATH 15 /* Library search path (deprecated) */ ++#define DT_SYMBOLIC 16 /* Start symbol search here */ ++#define DT_REL 17 /* Address of Rel relocs */ ++#define DT_RELSZ 18 /* Total size of Rel relocs */ ++#define DT_RELENT 19 /* Size of one Rel reloc */ ++#define DT_PLTREL 20 /* Type of reloc in PLT */ ++#define DT_DEBUG 21 /* For debugging; unspecified */ ++#define DT_TEXTREL 22 /* Reloc might modify .text */ ++#define DT_JMPREL 23 /* Address of PLT relocs */ ++#define DT_BIND_NOW 24 /* Process relocations of object */ ++#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ ++#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ ++#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ ++#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ ++#define DT_RUNPATH 29 /* Library search path */ ++#define DT_FLAGS 30 /* Flags for the object being loaded */ ++#define DT_ENCODING 32 /* Start of encoded range */ ++#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ ++#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ ++#define DT_NUM 34 /* Number used */ ++#define DT_LOOS 0x6000000d /* Start of OS-specific */ ++#define DT_HIOS 0x6ffff000 /* End of OS-specific */ ++#define DT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define DT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ ++ ++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the ++ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's ++ approach. */ ++#define DT_VALRNGLO 0x6ffffd00 ++#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ ++#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ ++#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ ++#define DT_CHECKSUM 0x6ffffdf8 ++#define DT_PLTPADSZ 0x6ffffdf9 ++#define DT_MOVEENT 0x6ffffdfa ++#define DT_MOVESZ 0x6ffffdfb ++#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ ++#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting ++ the following DT_* entry. */ ++#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ ++#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ ++#define DT_VALRNGHI 0x6ffffdff ++#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ ++#define DT_VALNUM 12 ++ ++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the ++ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. ++ ++ If any adjustment is made to the ELF object after it has been ++ built these entries will need to be adjusted. */ ++#define DT_ADDRRNGLO 0x6ffffe00 ++#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ ++#define DT_TLSDESC_PLT 0x6ffffef6 ++#define DT_TLSDESC_GOT 0x6ffffef7 ++#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ ++#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ ++#define DT_CONFIG 0x6ffffefa /* Configuration information. */ ++#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ ++#define DT_AUDIT 0x6ffffefc /* Object auditing. */ ++#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ ++#define DT_MOVETAB 0x6ffffefe /* Move table. */ ++#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ ++#define DT_ADDRRNGHI 0x6ffffeff ++#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ ++#define DT_ADDRNUM 11 ++ ++/* The versioning entry types. The next are defined as part of the ++ GNU extension. */ ++#define DT_VERSYM 0x6ffffff0 ++ ++#define DT_RELACOUNT 0x6ffffff9 ++#define DT_RELCOUNT 0x6ffffffa ++ ++/* These were chosen by Sun. */ ++#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ ++#define DT_VERDEF 0x6ffffffc /* Address of version definition ++ table */ ++#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ ++#define DT_VERNEED 0x6ffffffe /* Address of table with needed ++ versions */ ++#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ ++#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ ++#define DT_VERSIONTAGNUM 16 ++ ++/* Sun added these machine-independent extensions in the "processor-specific" ++ range. Be compatible. */ ++#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ ++#define DT_FILTER 0x7fffffff /* Shared object to get values from */ ++#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) ++#define DT_EXTRANUM 3 ++ ++/* Values of `d_un.d_val' in the DT_FLAGS entry. */ ++#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ ++#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ ++#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ ++#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ ++#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ ++ ++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 ++ entry in the dynamic section. */ ++#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ ++#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ ++#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ ++#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ ++#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ ++#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ ++#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ ++#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ ++#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ ++#define DF_1_TRANS 0x00000200 ++#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ ++#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ ++#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ ++#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ ++#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ ++#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ ++#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ ++ ++/* Flags for the feature selection in DT_FEATURE_1. */ ++#define DTF_1_PARINIT 0x00000001 ++#define DTF_1_CONFEXP 0x00000002 ++ ++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ ++#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ ++#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not ++ generally available. */ ++ ++/* Version definition sections. */ ++ ++typedef struct ++{ ++ Elf32_Half vd_version; /* Version revision */ ++ Elf32_Half vd_flags; /* Version information */ ++ Elf32_Half vd_ndx; /* Version Index */ ++ Elf32_Half vd_cnt; /* Number of associated aux entries */ ++ Elf32_Word vd_hash; /* Version name hash value */ ++ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf32_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf32_Verdef; ++ ++typedef struct ++{ ++ Elf64_Half vd_version; /* Version revision */ ++ Elf64_Half vd_flags; /* Version information */ ++ Elf64_Half vd_ndx; /* Version Index */ ++ Elf64_Half vd_cnt; /* Number of associated aux entries */ ++ Elf64_Word vd_hash; /* Version name hash value */ ++ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf64_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf64_Verdef; ++ ++ ++/* Legal values for vd_version (version revision). */ ++#define VER_DEF_NONE 0 /* No version */ ++#define VER_DEF_CURRENT 1 /* Current version */ ++#define VER_DEF_NUM 2 /* Given version number */ ++ ++/* Legal values for vd_flags (version information flags). */ ++#define VER_FLG_BASE 0x1 /* Version definition of file itself */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++/* Versym symbol index values. */ ++#define VER_NDX_LOCAL 0 /* Symbol is local. */ ++#define VER_NDX_GLOBAL 1 /* Symbol is global. */ ++#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ ++#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ ++ ++/* Auxialiary version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vda_name; /* Version or dependency names */ ++ Elf32_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf32_Verdaux; ++ ++typedef struct ++{ ++ Elf64_Word vda_name; /* Version or dependency names */ ++ Elf64_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf64_Verdaux; ++ ++ ++/* Version dependency section. */ ++ ++typedef struct ++{ ++ Elf32_Half vn_version; /* Version of structure */ ++ Elf32_Half vn_cnt; /* Number of associated aux entries */ ++ Elf32_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf32_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf32_Verneed; ++ ++typedef struct ++{ ++ Elf64_Half vn_version; /* Version of structure */ ++ Elf64_Half vn_cnt; /* Number of associated aux entries */ ++ Elf64_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf64_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf64_Verneed; ++ ++ ++/* Legal values for vn_version (version revision). */ ++#define VER_NEED_NONE 0 /* No version */ ++#define VER_NEED_CURRENT 1 /* Current version */ ++#define VER_NEED_NUM 2 /* Given version number */ ++ ++/* Auxiliary needed version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vna_hash; /* Hash value of dependency name */ ++ Elf32_Half vna_flags; /* Dependency specific information */ ++ Elf32_Half vna_other; /* Unused */ ++ Elf32_Word vna_name; /* Dependency name string offset */ ++ Elf32_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf32_Vernaux; ++ ++typedef struct ++{ ++ Elf64_Word vna_hash; /* Hash value of dependency name */ ++ Elf64_Half vna_flags; /* Dependency specific information */ ++ Elf64_Half vna_other; /* Unused */ ++ Elf64_Word vna_name; /* Dependency name string offset */ ++ Elf64_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf64_Vernaux; ++ ++ ++/* Legal values for vna_flags. */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++ ++/* Auxiliary vector. */ ++ ++/* This vector is normally only used by the program interpreter. The ++ usual definition in an ABI supplement uses the name auxv_t. The ++ vector is not usually defined in a standard file, but it ++ can't hurt. We rename it to avoid conflicts. The sizes of these ++ types are an arrangement between the exec server and the program ++ interpreter, so we don't fully specify them here. */ ++ ++typedef struct ++{ ++ uint32_t a_type; /* Entry type */ ++ union ++ { ++ uint32_t a_val; /* Integer value */ ++ /* We use to have pointer elements added here. We cannot do that, ++ though, since it does not work when using 32-bit definitions ++ on 64-bit platforms and vice versa. */ ++ } a_un; ++} Elf32_auxv_t; ++ ++typedef struct ++{ ++ uint64_t a_type; /* Entry type */ ++ union ++ { ++ uint64_t a_val; /* Integer value */ ++ /* We use to have pointer elements added here. We cannot do that, ++ though, since it does not work when using 32-bit definitions ++ on 64-bit platforms and vice versa. */ ++ } a_un; ++} Elf64_auxv_t; ++ ++/* Legal values for a_type (entry type). */ ++ ++#define AT_NULL 0 /* End of vector */ ++#define AT_IGNORE 1 /* Entry should be ignored */ ++#define AT_EXECFD 2 /* File descriptor of program */ ++#define AT_PHDR 3 /* Program headers for program */ ++#define AT_PHENT 4 /* Size of program header entry */ ++#define AT_PHNUM 5 /* Number of program headers */ ++#define AT_PAGESZ 6 /* System page size */ ++#define AT_BASE 7 /* Base address of interpreter */ ++#define AT_FLAGS 8 /* Flags */ ++#define AT_ENTRY 9 /* Entry point of program */ ++#define AT_NOTELF 10 /* Program is not ELF */ ++#define AT_UID 11 /* Real uid */ ++#define AT_EUID 12 /* Effective uid */ ++#define AT_GID 13 /* Real gid */ ++#define AT_EGID 14 /* Effective gid */ ++#define AT_CLKTCK 17 /* Frequency of times() */ ++ ++/* Some more special a_type values describing the hardware. */ ++#define AT_PLATFORM 15 /* String identifying platform. */ ++#define AT_HWCAP 16 /* Machine dependent hints about ++ processor capabilities. */ ++ ++/* This entry gives some information about the FPU initialization ++ performed by the kernel. */ ++#define AT_FPUCW 18 /* Used FPU control word. */ ++ ++/* Cache block sizes. */ ++#define AT_DCACHEBSIZE 19 /* Data cache block size. */ ++#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ ++#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ ++ ++/* A special ignored value for PPC, used by the kernel to control the ++ interpretation of the AUXV. Must be > 16. */ ++#define AT_IGNOREPPC 22 /* Entry should be ignored. */ ++ ++#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ ++ ++#define AT_BASE_PLATFORM 24 /* String identifying real platforms.*/ ++ ++#define AT_RANDOM 25 /* Address of 16 random bytes. */ ++ ++#define AT_EXECFN 31 /* Filename of executable. */ ++ ++/* Pointer to the global system page used for system calls and other ++ nice things. */ ++#define AT_SYSINFO 32 ++#define AT_SYSINFO_EHDR 33 ++ ++/* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains ++ log2 of line size; mask those to get cache size. */ ++#define AT_L1I_CACHESHAPE 34 ++#define AT_L1D_CACHESHAPE 35 ++#define AT_L2_CACHESHAPE 36 ++#define AT_L3_CACHESHAPE 37 ++ ++/* Note section contents. Each entry in the note section begins with ++ a header of a fixed form. */ ++ ++typedef struct ++{ ++ Elf32_Word n_namesz; /* Length of the note's name. */ ++ Elf32_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf32_Word n_type; /* Type of the note. */ ++} Elf32_Nhdr; ++ ++typedef struct ++{ ++ Elf64_Word n_namesz; /* Length of the note's name. */ ++ Elf64_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf64_Word n_type; /* Type of the note. */ ++} Elf64_Nhdr; ++ ++/* Known names of notes. */ ++ ++/* Solaris entries in the note section have this name. */ ++#define ELF_NOTE_SOLARIS "SUNW Solaris" ++ ++/* Note entries for GNU systems have this name. */ ++#define ELF_NOTE_GNU "GNU" ++ ++ ++/* Defined types of notes for Solaris. */ ++ ++/* Value of descriptor (one word) is desired pagesize for the binary. */ ++#define ELF_NOTE_PAGESIZE_HINT 1 ++ ++ ++/* Defined note types for GNU systems. */ ++ ++/* ABI information. The descriptor consists of words: ++ word 0: OS descriptor ++ word 1: major version of the ABI ++ word 2: minor version of the ABI ++ word 3: subminor version of the ABI ++*/ ++#define NT_GNU_ABI_TAG 1 ++#define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ ++ ++/* Known OSes. These values can appear in word 0 of an ++ NT_GNU_ABI_TAG note section entry. */ ++#define ELF_NOTE_OS_LINUX 0 ++#define ELF_NOTE_OS_GNU 1 ++#define ELF_NOTE_OS_SOLARIS2 2 ++#define ELF_NOTE_OS_FREEBSD 3 ++ ++/* Synthetic hwcap information. The descriptor begins with two words: ++ word 0: number of entries ++ word 1: bitmask of enabled entries ++ Then follow variable-length entries, one byte followed by a ++ '\0'-terminated hwcap name string. The byte gives the bit ++ number to test if enabled, (1U << bit) & bitmask. */ ++#define NT_GNU_HWCAP 2 ++ ++/* Build ID bits as generated by ld --build-id. ++ The descriptor consists of any nonzero number of bytes. */ ++#define NT_GNU_BUILD_ID 3 ++ ++/* Version note generated by GNU gold containing a version string. */ ++#define NT_GNU_GOLD_VERSION 4 ++ ++ ++/* Move records. */ ++typedef struct ++{ ++ Elf32_Xword m_value; /* Symbol value. */ ++ Elf32_Word m_info; /* Size and index. */ ++ Elf32_Word m_poffset; /* Symbol offset. */ ++ Elf32_Half m_repeat; /* Repeat count. */ ++ Elf32_Half m_stride; /* Stride info. */ ++} Elf32_Move; ++ ++typedef struct ++{ ++ Elf64_Xword m_value; /* Symbol value. */ ++ Elf64_Xword m_info; /* Size and index. */ ++ Elf64_Xword m_poffset; /* Symbol offset. */ ++ Elf64_Half m_repeat; /* Repeat count. */ ++ Elf64_Half m_stride; /* Stride info. */ ++} Elf64_Move; ++ ++/* Macro to construct move records. */ ++#define ELF32_M_SYM(info) ((info) >> 8) ++#define ELF32_M_SIZE(info) ((unsigned char) (info)) ++#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) ++ ++#define ELF64_M_SYM(info) ELF32_M_SYM (info) ++#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) ++#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) ++ ++ ++/* Motorola 68k specific definitions. */ ++ ++/* Values for Elf32_Ehdr.e_flags. */ ++#define EF_CPU32 0x00810000 ++ ++/* m68k relocs. */ ++ ++#define R_68K_NONE 0 /* No reloc */ ++#define R_68K_32 1 /* Direct 32 bit */ ++#define R_68K_16 2 /* Direct 16 bit */ ++#define R_68K_8 3 /* Direct 8 bit */ ++#define R_68K_PC32 4 /* PC relative 32 bit */ ++#define R_68K_PC16 5 /* PC relative 16 bit */ ++#define R_68K_PC8 6 /* PC relative 8 bit */ ++#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ ++#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ ++#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ ++#define R_68K_GOT32O 10 /* 32 bit GOT offset */ ++#define R_68K_GOT16O 11 /* 16 bit GOT offset */ ++#define R_68K_GOT8O 12 /* 8 bit GOT offset */ ++#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ ++#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ ++#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ ++#define R_68K_PLT32O 16 /* 32 bit PLT offset */ ++#define R_68K_PLT16O 17 /* 16 bit PLT offset */ ++#define R_68K_PLT8O 18 /* 8 bit PLT offset */ ++#define R_68K_COPY 19 /* Copy symbol at runtime */ ++#define R_68K_GLOB_DAT 20 /* Create GOT entry */ ++#define R_68K_JMP_SLOT 21 /* Create PLT entry */ ++#define R_68K_RELATIVE 22 /* Adjust by program base */ ++#define R_68K_TLS_GD32 25 /* 32 bit GOT offset for GD */ ++#define R_68K_TLS_GD16 26 /* 16 bit GOT offset for GD */ ++#define R_68K_TLS_GD8 27 /* 8 bit GOT offset for GD */ ++#define R_68K_TLS_LDM32 28 /* 32 bit GOT offset for LDM */ ++#define R_68K_TLS_LDM16 29 /* 16 bit GOT offset for LDM */ ++#define R_68K_TLS_LDM8 30 /* 8 bit GOT offset for LDM */ ++#define R_68K_TLS_LDO32 31 /* 32 bit module-relative offset */ ++#define R_68K_TLS_LDO16 32 /* 16 bit module-relative offset */ ++#define R_68K_TLS_LDO8 33 /* 8 bit module-relative offset */ ++#define R_68K_TLS_IE32 34 /* 32 bit GOT offset for IE */ ++#define R_68K_TLS_IE16 35 /* 16 bit GOT offset for IE */ ++#define R_68K_TLS_IE8 36 /* 8 bit GOT offset for IE */ ++#define R_68K_TLS_LE32 37 /* 32 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_LE16 38 /* 16 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_LE8 39 /* 8 bit offset relative to ++ static TLS block */ ++#define R_68K_TLS_DTPMOD32 40 /* 32 bit module number */ ++#define R_68K_TLS_DTPREL32 41 /* 32 bit module-relative offset */ ++#define R_68K_TLS_TPREL32 42 /* 32 bit TP-relative offset */ ++/* Keep this the last entry. */ ++#define R_68K_NUM 43 ++ ++/* Intel 80386 specific definitions. */ ++ ++/* i386 relocs. */ ++ ++#define R_386_NONE 0 /* No reloc */ ++#define R_386_32 1 /* Direct 32 bit */ ++#define R_386_PC32 2 /* PC relative 32 bit */ ++#define R_386_GOT32 3 /* 32 bit GOT entry */ ++#define R_386_PLT32 4 /* 32 bit PLT address */ ++#define R_386_COPY 5 /* Copy symbol at runtime */ ++#define R_386_GLOB_DAT 6 /* Create GOT entry */ ++#define R_386_JMP_SLOT 7 /* Create PLT entry */ ++#define R_386_RELATIVE 8 /* Adjust by program base */ ++#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ ++#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ ++#define R_386_32PLT 11 ++#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ ++#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS ++ block offset */ ++#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block ++ offset */ ++#define R_386_TLS_LE 17 /* Offset relative to static TLS ++ block */ ++#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of ++ general dynamic thread local data */ ++#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of ++ local dynamic thread local data ++ in LE code */ ++#define R_386_16 20 ++#define R_386_PC16 21 ++#define R_386_8 22 ++#define R_386_PC8 23 ++#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic ++ thread local data */ ++#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ ++#define R_386_TLS_GD_CALL 26 /* Relocation for call to ++ __tls_get_addr() */ ++#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ ++#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic ++ thread local data in LE code */ ++#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ ++#define R_386_TLS_LDM_CALL 30 /* Relocation for call to ++ __tls_get_addr() in LDM code */ ++#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ ++#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ ++#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS ++ block offset */ ++#define R_386_TLS_LE_32 34 /* Negated offset relative to static ++ TLS block */ ++#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ ++#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ ++#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ ++/* 38? */ ++#define R_386_TLS_GOTDESC 39 /* GOT offset for TLS descriptor. */ ++#define R_386_TLS_DESC_CALL 40 /* Marker of call through TLS ++ descriptor for ++ relaxation. */ ++#define R_386_TLS_DESC 41 /* TLS descriptor containing ++ pointer to code and to ++ argument, returning the TLS ++ offset for the symbol. */ ++#define R_386_IRELATIVE 42 /* Adjust indirectly by program base */ ++/* Keep this the last entry. */ ++#define R_386_NUM 43 ++ ++/* SUN SPARC specific definitions. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ ++ ++/* Values for Elf64_Ehdr.e_flags. */ ++ ++#define EF_SPARCV9_MM 3 ++#define EF_SPARCV9_TSO 0 ++#define EF_SPARCV9_PSO 1 ++#define EF_SPARCV9_RMO 2 ++#define EF_SPARC_LEDATA 0x800000 /* little endian data */ ++#define EF_SPARC_EXT_MASK 0xFFFF00 ++#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ ++#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ ++#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ ++#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ ++ ++/* SPARC relocs. */ ++ ++#define R_SPARC_NONE 0 /* No reloc */ ++#define R_SPARC_8 1 /* Direct 8 bit */ ++#define R_SPARC_16 2 /* Direct 16 bit */ ++#define R_SPARC_32 3 /* Direct 32 bit */ ++#define R_SPARC_DISP8 4 /* PC relative 8 bit */ ++#define R_SPARC_DISP16 5 /* PC relative 16 bit */ ++#define R_SPARC_DISP32 6 /* PC relative 32 bit */ ++#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ ++#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ ++#define R_SPARC_HI22 9 /* High 22 bit */ ++#define R_SPARC_22 10 /* Direct 22 bit */ ++#define R_SPARC_13 11 /* Direct 13 bit */ ++#define R_SPARC_LO10 12 /* Truncated 10 bit */ ++#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ ++#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ ++#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ ++#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ ++#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ ++#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ ++#define R_SPARC_COPY 19 /* Copy symbol at runtime */ ++#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ ++#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ ++#define R_SPARC_RELATIVE 22 /* Adjust by program base */ ++#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ ++ ++/* Additional Sparc64 relocs. */ ++ ++#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ ++#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ ++#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ ++#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ ++#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ ++#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ ++#define R_SPARC_10 30 /* Direct 10 bit */ ++#define R_SPARC_11 31 /* Direct 11 bit */ ++#define R_SPARC_64 32 /* Direct 64 bit */ ++#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ ++#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ ++#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ ++#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ ++#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ ++#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ ++#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ ++#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ ++#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ ++#define R_SPARC_GLOB_JMP 42 /* was part of v9 ABI but was removed */ ++#define R_SPARC_7 43 /* Direct 7 bit */ ++#define R_SPARC_5 44 /* Direct 5 bit */ ++#define R_SPARC_6 45 /* Direct 6 bit */ ++#define R_SPARC_DISP64 46 /* PC relative 64 bit */ ++#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ ++#define R_SPARC_HIX22 48 /* High 22 bit complemented */ ++#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ ++#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ ++#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ ++#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ ++#define R_SPARC_REGISTER 53 /* Global register usage */ ++#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ ++#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ ++#define R_SPARC_TLS_GD_HI22 56 ++#define R_SPARC_TLS_GD_LO10 57 ++#define R_SPARC_TLS_GD_ADD 58 ++#define R_SPARC_TLS_GD_CALL 59 ++#define R_SPARC_TLS_LDM_HI22 60 ++#define R_SPARC_TLS_LDM_LO10 61 ++#define R_SPARC_TLS_LDM_ADD 62 ++#define R_SPARC_TLS_LDM_CALL 63 ++#define R_SPARC_TLS_LDO_HIX22 64 ++#define R_SPARC_TLS_LDO_LOX10 65 ++#define R_SPARC_TLS_LDO_ADD 66 ++#define R_SPARC_TLS_IE_HI22 67 ++#define R_SPARC_TLS_IE_LO10 68 ++#define R_SPARC_TLS_IE_LD 69 ++#define R_SPARC_TLS_IE_LDX 70 ++#define R_SPARC_TLS_IE_ADD 71 ++#define R_SPARC_TLS_LE_HIX22 72 ++#define R_SPARC_TLS_LE_LOX10 73 ++#define R_SPARC_TLS_DTPMOD32 74 ++#define R_SPARC_TLS_DTPMOD64 75 ++#define R_SPARC_TLS_DTPOFF32 76 ++#define R_SPARC_TLS_DTPOFF64 77 ++#define R_SPARC_TLS_TPOFF32 78 ++#define R_SPARC_TLS_TPOFF64 79 ++#define R_SPARC_GOTDATA_HIX22 80 ++#define R_SPARC_GOTDATA_LOX10 81 ++#define R_SPARC_GOTDATA_OP_HIX22 82 ++#define R_SPARC_GOTDATA_OP_LOX10 83 ++#define R_SPARC_GOTDATA_OP 84 ++#define R_SPARC_H34 85 ++#define R_SPARC_SIZE32 86 ++#define R_SPARC_SIZE64 87 ++#define R_SPARC_WDISP10 88 ++#define R_SPARC_JMP_IREL 248 ++#define R_SPARC_IRELATIVE 249 ++#define R_SPARC_GNU_VTINHERIT 250 ++#define R_SPARC_GNU_VTENTRY 251 ++#define R_SPARC_REV32 252 ++/* Keep this the last entry. */ ++#define R_SPARC_NUM 253 ++ ++/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ ++ ++#define DT_SPARC_REGISTER 0x70000001 ++#define DT_SPARC_NUM 2 ++ ++/* MIPS R3000 specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ ++#define EF_MIPS_PIC 2 /* Contains PIC code */ ++#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ ++#define EF_MIPS_XGOT 8 ++#define EF_MIPS_64BIT_WHIRL 16 ++#define EF_MIPS_ABI2 32 ++#define EF_MIPS_ABI_ON32 64 ++#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ ++ ++/* Legal values for MIPS architecture level. */ ++ ++#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* The following are non-official names and should not be used. */ ++ ++#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* Special section indices. */ ++ ++#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ ++#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ ++#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ ++#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ ++#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ ++#define SHT_MIPS_MSYM 0x70000001 ++#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ ++#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ ++#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ ++#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ ++#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ ++#define SHT_MIPS_PACKAGE 0x70000007 ++#define SHT_MIPS_PACKSYM 0x70000008 ++#define SHT_MIPS_RELD 0x70000009 ++#define SHT_MIPS_IFACE 0x7000000b ++#define SHT_MIPS_CONTENT 0x7000000c ++#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ ++#define SHT_MIPS_SHDR 0x70000010 ++#define SHT_MIPS_FDESC 0x70000011 ++#define SHT_MIPS_EXTSYM 0x70000012 ++#define SHT_MIPS_DENSE 0x70000013 ++#define SHT_MIPS_PDESC 0x70000014 ++#define SHT_MIPS_LOCSYM 0x70000015 ++#define SHT_MIPS_AUXSYM 0x70000016 ++#define SHT_MIPS_OPTSYM 0x70000017 ++#define SHT_MIPS_LOCSTR 0x70000018 ++#define SHT_MIPS_LINE 0x70000019 ++#define SHT_MIPS_RFDESC 0x7000001a ++#define SHT_MIPS_DELTASYM 0x7000001b ++#define SHT_MIPS_DELTAINST 0x7000001c ++#define SHT_MIPS_DELTACLASS 0x7000001d ++#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ ++#define SHT_MIPS_DELTADECL 0x7000001f ++#define SHT_MIPS_SYMBOL_LIB 0x70000020 ++#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ ++#define SHT_MIPS_TRANSLATE 0x70000022 ++#define SHT_MIPS_PIXIE 0x70000023 ++#define SHT_MIPS_XLATE 0x70000024 ++#define SHT_MIPS_XLATE_DEBUG 0x70000025 ++#define SHT_MIPS_WHIRL 0x70000026 ++#define SHT_MIPS_EH_REGION 0x70000027 ++#define SHT_MIPS_XLATE_OLD 0x70000028 ++#define SHT_MIPS_PDR_EXCEPTION 0x70000029 ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ ++#define SHF_MIPS_MERGE 0x20000000 ++#define SHF_MIPS_ADDR 0x40000000 ++#define SHF_MIPS_STRINGS 0x80000000 ++#define SHF_MIPS_NOSTRIP 0x08000000 ++#define SHF_MIPS_LOCAL 0x04000000 ++#define SHF_MIPS_NAMES 0x02000000 ++#define SHF_MIPS_NODUPE 0x01000000 ++ ++ ++/* Symbol tables. */ ++ ++/* MIPS specific values for `st_other'. */ ++#define STO_MIPS_DEFAULT 0x0 ++#define STO_MIPS_INTERNAL 0x1 ++#define STO_MIPS_HIDDEN 0x2 ++#define STO_MIPS_PROTECTED 0x3 ++#define STO_MIPS_PLT 0x8 ++#define STO_MIPS_SC_ALIGN_UNUSED 0xff ++ ++/* MIPS specific values for `st_info'. */ ++#define STB_MIPS_SPLIT_COMMON 13 ++ ++/* Entries found in sections of type SHT_MIPS_GPTAB. */ ++ ++typedef union ++{ ++ struct ++ { ++ Elf32_Word gt_current_g_value; /* -G value used for compilation */ ++ Elf32_Word gt_unused; /* Not used */ ++ } gt_header; /* First entry in section */ ++ struct ++ { ++ Elf32_Word gt_g_value; /* If this value were used for -G */ ++ Elf32_Word gt_bytes; /* This many bytes would be used */ ++ } gt_entry; /* Subsequent entries in section */ ++} Elf32_gptab; ++ ++/* Entry found in sections of type SHT_MIPS_REGINFO. */ ++ ++typedef struct ++{ ++ Elf32_Word ri_gprmask; /* General registers used */ ++ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ ++ Elf32_Sword ri_gp_value; /* $gp register value */ ++} Elf32_RegInfo; ++ ++/* Entries found in sections of type SHT_MIPS_OPTIONS. */ ++ ++typedef struct ++{ ++ unsigned char kind; /* Determines interpretation of the ++ variable part of descriptor. */ ++ unsigned char size; /* Size of descriptor, including header. */ ++ Elf32_Section section; /* Section header index of section affected, ++ 0 for global options. */ ++ Elf32_Word info; /* Kind-specific information. */ ++} Elf_Options; ++ ++/* Values for `kind' field in Elf_Options. */ ++ ++#define ODK_NULL 0 /* Undefined. */ ++#define ODK_REGINFO 1 /* Register usage information. */ ++#define ODK_EXCEPTIONS 2 /* Exception processing options. */ ++#define ODK_PAD 3 /* Section padding options. */ ++#define ODK_HWPATCH 4 /* Hardware workarounds performed */ ++#define ODK_FILL 5 /* record the fill value used by the linker. */ ++#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ ++#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ ++#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ ++ ++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ ++ ++#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ ++#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ ++#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ ++#define OEX_SMM 0x20000 /* Force sequential memory mode? */ ++#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ ++#define OEX_PRECISEFP OEX_FPDBUG ++#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ ++ ++#define OEX_FPU_INVAL 0x10 ++#define OEX_FPU_DIV0 0x08 ++#define OEX_FPU_OFLO 0x04 ++#define OEX_FPU_UFLO 0x02 ++#define OEX_FPU_INEX 0x01 ++ ++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ ++ ++#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ ++#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ ++#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ ++#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ ++ ++#define OPAD_PREFIX 0x1 ++#define OPAD_POSTFIX 0x2 ++#define OPAD_SYMBOL 0x4 ++ ++/* Entry found in `.options' section. */ ++ ++typedef struct ++{ ++ Elf32_Word hwp_flags1; /* Extra flags. */ ++ Elf32_Word hwp_flags2; /* Extra flags. */ ++} Elf_Options_Hw; ++ ++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ ++ ++#define OHWA0_R4KEOP_CHECKED 0x00000001 ++#define OHWA1_R4KEOP_CLEAN 0x00000002 ++ ++/* MIPS relocs. */ ++ ++#define R_MIPS_NONE 0 /* No reloc */ ++#define R_MIPS_16 1 /* Direct 16 bit */ ++#define R_MIPS_32 2 /* Direct 32 bit */ ++#define R_MIPS_REL32 3 /* PC relative 32 bit */ ++#define R_MIPS_26 4 /* Direct 26 bit shifted */ ++#define R_MIPS_HI16 5 /* High 16 bit */ ++#define R_MIPS_LO16 6 /* Low 16 bit */ ++#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ ++#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ ++#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ ++#define R_MIPS_PC16 10 /* PC relative 16 bit */ ++#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ ++#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ ++ ++#define R_MIPS_SHIFT5 16 ++#define R_MIPS_SHIFT6 17 ++#define R_MIPS_64 18 ++#define R_MIPS_GOT_DISP 19 ++#define R_MIPS_GOT_PAGE 20 ++#define R_MIPS_GOT_OFST 21 ++#define R_MIPS_GOT_HI16 22 ++#define R_MIPS_GOT_LO16 23 ++#define R_MIPS_SUB 24 ++#define R_MIPS_INSERT_A 25 ++#define R_MIPS_INSERT_B 26 ++#define R_MIPS_DELETE 27 ++#define R_MIPS_HIGHER 28 ++#define R_MIPS_HIGHEST 29 ++#define R_MIPS_CALL_HI16 30 ++#define R_MIPS_CALL_LO16 31 ++#define R_MIPS_SCN_DISP 32 ++#define R_MIPS_REL16 33 ++#define R_MIPS_ADD_IMMEDIATE 34 ++#define R_MIPS_PJUMP 35 ++#define R_MIPS_RELGOT 36 ++#define R_MIPS_JALR 37 ++#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ ++#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ ++#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ ++#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ ++#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ ++#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ ++#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ ++#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ ++#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ ++#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ ++#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ ++#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ ++#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ ++#define R_MIPS_GLOB_DAT 51 ++#define R_MIPS_COPY 126 ++#define R_MIPS_JUMP_SLOT 127 ++/* Keep this the last entry. */ ++#define R_MIPS_NUM 128 ++ ++/* Legal values for p_type field of Elf32_Phdr. */ ++ ++#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ ++#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ ++#define PT_MIPS_OPTIONS 0x70000002 ++ ++/* Special program header types. */ ++ ++#define PF_MIPS_LOCAL 0x10000000 ++ ++/* Legal values for d_tag field of Elf32_Dyn. */ ++ ++#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ ++#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ ++#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ ++#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ ++#define DT_MIPS_FLAGS 0x70000005 /* Flags */ ++#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ ++#define DT_MIPS_MSYM 0x70000007 ++#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ ++#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ ++#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ ++#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ ++#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ ++#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ ++#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ ++#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ ++#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ ++#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ ++#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ ++#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in ++ DT_MIPS_DELTA_CLASS. */ ++#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ ++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in ++ DT_MIPS_DELTA_INSTANCE. */ ++#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ ++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in ++ DT_MIPS_DELTA_RELOC. */ ++#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta ++ relocations refer to. */ ++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in ++ DT_MIPS_DELTA_SYM. */ ++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the ++ class declaration. */ ++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in ++ DT_MIPS_DELTA_CLASSSYM. */ ++#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ ++#define DT_MIPS_PIXIE_INIT 0x70000023 ++#define DT_MIPS_SYMBOL_LIB 0x70000024 ++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 ++#define DT_MIPS_LOCAL_GOTIDX 0x70000026 ++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 ++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 ++#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ ++#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ ++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b ++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ ++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve ++ function stored in GOT. */ ++#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added ++ by rld on dlopen() calls. */ ++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ ++#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ ++#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ ++/* The address of .got.plt in an executable using the new non-PIC ABI. */ ++#define DT_MIPS_PLTGOT 0x70000032 ++/* The base of the PLT in an executable using the new non-PIC ABI if that ++ PLT is writable. For a non-writable PLT, this is omitted or has a zero ++ value. */ ++#define DT_MIPS_RWPLT 0x70000034 ++#define DT_MIPS_NUM 0x35 ++ ++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ ++ ++#define RHF_NONE 0 /* No flags */ ++#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ ++#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ ++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ ++#define RHF_NO_MOVE (1 << 3) ++#define RHF_SGI_ONLY (1 << 4) ++#define RHF_GUARANTEE_INIT (1 << 5) ++#define RHF_DELTA_C_PLUS_PLUS (1 << 6) ++#define RHF_GUARANTEE_START_INIT (1 << 7) ++#define RHF_PIXIE (1 << 8) ++#define RHF_DEFAULT_DELAY_LOAD (1 << 9) ++#define RHF_REQUICKSTART (1 << 10) ++#define RHF_REQUICKSTARTED (1 << 11) ++#define RHF_CORD (1 << 12) ++#define RHF_NO_UNRES_UNDEF (1 << 13) ++#define RHF_RLD_ORDER_SAFE (1 << 14) ++ ++/* Entries found in sections of type SHT_MIPS_LIBLIST. */ ++ ++typedef struct ++{ ++ Elf32_Word l_name; /* Name (string table index) */ ++ Elf32_Word l_time_stamp; /* Timestamp */ ++ Elf32_Word l_checksum; /* Checksum */ ++ Elf32_Word l_version; /* Interface version */ ++ Elf32_Word l_flags; /* Flags */ ++} Elf32_Lib; ++ ++typedef struct ++{ ++ Elf64_Word l_name; /* Name (string table index) */ ++ Elf64_Word l_time_stamp; /* Timestamp */ ++ Elf64_Word l_checksum; /* Checksum */ ++ Elf64_Word l_version; /* Interface version */ ++ Elf64_Word l_flags; /* Flags */ ++} Elf64_Lib; ++ ++ ++/* Legal values for l_flags. */ ++ ++#define LL_NONE 0 ++#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ ++#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ ++#define LL_REQUIRE_MINOR (1 << 2) ++#define LL_EXPORTS (1 << 3) ++#define LL_DELAY_LOAD (1 << 4) ++#define LL_DELTA (1 << 5) ++ ++/* Entries found in sections of type SHT_MIPS_CONFLICT. */ ++ ++typedef Elf32_Addr Elf32_Conflict; ++ ++ ++/* HPPA specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ ++#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ ++#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ ++#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ ++#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch ++ prediction. */ ++#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ ++#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ ++ ++/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ ++ ++#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ ++#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ ++#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ ++ ++/* Additional section indeces. */ ++ ++#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared ++ symbols in ANSI C. */ ++#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ ++#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ ++#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ ++#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ ++#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ ++ ++#define STT_HP_OPAQUE (STT_LOOS + 0x1) ++#define STT_HP_STUB (STT_LOOS + 0x2) ++ ++/* HPPA relocs. */ ++ ++#define R_PARISC_NONE 0 /* No reloc. */ ++#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ ++#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ ++#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ ++#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ ++#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ ++#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ ++#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ ++#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ ++#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ ++#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ ++#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ ++#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ ++#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ ++#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ ++#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ ++#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ ++#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ ++#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ ++#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ ++#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ ++#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ ++#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ ++#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ ++#define R_PARISC_FPTR64 64 /* 64 bits function address. */ ++#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ ++#define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ ++#define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ ++#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ ++#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ ++#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ ++#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ ++#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ ++#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ ++#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ ++#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ ++#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ ++#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ ++#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ ++#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ ++#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ ++#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ ++#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LORESERVE 128 ++#define R_PARISC_COPY 128 /* Copy relocation. */ ++#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ ++#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ ++#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ ++#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ ++#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ ++#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ ++#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ ++#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ ++#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_GNU_VTENTRY 232 ++#define R_PARISC_GNU_VTINHERIT 233 ++#define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ ++#define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ ++#define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ ++#define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ ++#define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ ++#define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ ++#define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ ++#define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ ++#define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ ++#define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ ++#define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ ++#define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ ++#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L ++#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R ++#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L ++#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R ++#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 ++#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 ++#define R_PARISC_HIRESERVE 255 ++ ++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PT_HP_TLS (PT_LOOS + 0x0) ++#define PT_HP_CORE_NONE (PT_LOOS + 0x1) ++#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) ++#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) ++#define PT_HP_CORE_COMM (PT_LOOS + 0x4) ++#define PT_HP_CORE_PROC (PT_LOOS + 0x5) ++#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) ++#define PT_HP_CORE_STACK (PT_LOOS + 0x7) ++#define PT_HP_CORE_SHM (PT_LOOS + 0x8) ++#define PT_HP_CORE_MMF (PT_LOOS + 0x9) ++#define PT_HP_PARALLEL (PT_LOOS + 0x10) ++#define PT_HP_FASTBIND (PT_LOOS + 0x11) ++#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) ++#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) ++#define PT_HP_STACK (PT_LOOS + 0x14) ++ ++#define PT_PARISC_ARCHEXT 0x70000000 ++#define PT_PARISC_UNWIND 0x70000001 ++ ++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PF_PARISC_SBP 0x08000000 ++ ++#define PF_HP_PAGE_SIZE 0x00100000 ++#define PF_HP_FAR_SHARED 0x00200000 ++#define PF_HP_NEAR_SHARED 0x00400000 ++#define PF_HP_CODE 0x01000000 ++#define PF_HP_MODIFY 0x02000000 ++#define PF_HP_LAZYSWAP 0x04000000 ++#define PF_HP_SBP 0x08000000 ++ ++ ++/* Alpha specific definitions. */ ++ ++/* Legal values for e_flags field of Elf64_Ehdr. */ ++ ++#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ ++#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ ++ ++/* Legal values for sh_type field of Elf64_Shdr. */ ++ ++/* These two are primerily concerned with ECOFF debugging info. */ ++#define SHT_ALPHA_DEBUG 0x70000001 ++#define SHT_ALPHA_REGINFO 0x70000002 ++ ++/* Legal values for sh_flags field of Elf64_Shdr. */ ++ ++#define SHF_ALPHA_GPREL 0x10000000 ++ ++/* Legal values for st_other field of Elf64_Sym. */ ++#define STO_ALPHA_NOPV 0x80 /* No PV required. */ ++#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ ++ ++/* Alpha relocs. */ ++ ++#define R_ALPHA_NONE 0 /* No reloc */ ++#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ ++#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ ++#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ ++#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ ++#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ ++#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ ++#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ ++#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ ++#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ ++#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ ++#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ ++#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ ++#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ ++#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ ++#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ ++#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ ++#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ ++#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ ++#define R_ALPHA_TLS_GD_HI 28 ++#define R_ALPHA_TLSGD 29 ++#define R_ALPHA_TLS_LDM 30 ++#define R_ALPHA_DTPMOD64 31 ++#define R_ALPHA_GOTDTPREL 32 ++#define R_ALPHA_DTPREL64 33 ++#define R_ALPHA_DTPRELHI 34 ++#define R_ALPHA_DTPRELLO 35 ++#define R_ALPHA_DTPREL16 36 ++#define R_ALPHA_GOTTPREL 37 ++#define R_ALPHA_TPREL64 38 ++#define R_ALPHA_TPRELHI 39 ++#define R_ALPHA_TPRELLO 40 ++#define R_ALPHA_TPREL16 41 ++/* Keep this the last entry. */ ++#define R_ALPHA_NUM 46 ++ ++/* Magic values of the LITUSE relocation addend. */ ++#define LITUSE_ALPHA_ADDR 0 ++#define LITUSE_ALPHA_BASE 1 ++#define LITUSE_ALPHA_BYTOFF 2 ++#define LITUSE_ALPHA_JSR 3 ++#define LITUSE_ALPHA_TLS_GD 4 ++#define LITUSE_ALPHA_TLS_LDM 5 ++ ++/* Legal values for d_tag of Elf64_Dyn. */ ++#define DT_ALPHA_PLTRO (DT_LOPROC + 0) ++#define DT_ALPHA_NUM 1 ++ ++/* PowerPC specific declarations */ ++ ++/* Values for Elf32/64_Ehdr.e_flags. */ ++#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ ++ ++/* Cygnus local bits below */ ++#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ ++#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib ++ flag */ ++ ++/* PowerPC relocations defined by the ABIs */ ++#define R_PPC_NONE 0 ++#define R_PPC_ADDR32 1 /* 32bit absolute address */ ++#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ ++#define R_PPC_ADDR16 3 /* 16bit absolute address */ ++#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ ++#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ ++#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ ++#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ ++#define R_PPC_ADDR14_BRTAKEN 8 ++#define R_PPC_ADDR14_BRNTAKEN 9 ++#define R_PPC_REL24 10 /* PC relative 26 bit */ ++#define R_PPC_REL14 11 /* PC relative 16 bit */ ++#define R_PPC_REL14_BRTAKEN 12 ++#define R_PPC_REL14_BRNTAKEN 13 ++#define R_PPC_GOT16 14 ++#define R_PPC_GOT16_LO 15 ++#define R_PPC_GOT16_HI 16 ++#define R_PPC_GOT16_HA 17 ++#define R_PPC_PLTREL24 18 ++#define R_PPC_COPY 19 ++#define R_PPC_GLOB_DAT 20 ++#define R_PPC_JMP_SLOT 21 ++#define R_PPC_RELATIVE 22 ++#define R_PPC_LOCAL24PC 23 ++#define R_PPC_UADDR32 24 ++#define R_PPC_UADDR16 25 ++#define R_PPC_REL32 26 ++#define R_PPC_PLT32 27 ++#define R_PPC_PLTREL32 28 ++#define R_PPC_PLT16_LO 29 ++#define R_PPC_PLT16_HI 30 ++#define R_PPC_PLT16_HA 31 ++#define R_PPC_SDAREL16 32 ++#define R_PPC_SECTOFF 33 ++#define R_PPC_SECTOFF_LO 34 ++#define R_PPC_SECTOFF_HI 35 ++#define R_PPC_SECTOFF_HA 36 ++ ++/* PowerPC relocations defined for the TLS access ABI. */ ++#define R_PPC_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ ++#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ ++#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ ++#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ ++#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ ++#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ ++#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ ++#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ ++#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ ++ ++/* The remaining relocs are from the Embedded ELF ABI, and are not ++ in the SVR4 ELF ABI. */ ++#define R_PPC_EMB_NADDR32 101 ++#define R_PPC_EMB_NADDR16 102 ++#define R_PPC_EMB_NADDR16_LO 103 ++#define R_PPC_EMB_NADDR16_HI 104 ++#define R_PPC_EMB_NADDR16_HA 105 ++#define R_PPC_EMB_SDAI16 106 ++#define R_PPC_EMB_SDA2I16 107 ++#define R_PPC_EMB_SDA2REL 108 ++#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ ++#define R_PPC_EMB_MRKREF 110 ++#define R_PPC_EMB_RELSEC16 111 ++#define R_PPC_EMB_RELST_LO 112 ++#define R_PPC_EMB_RELST_HI 113 ++#define R_PPC_EMB_RELST_HA 114 ++#define R_PPC_EMB_BIT_FLD 115 ++#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ ++ ++/* Diab tool relocations. */ ++#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ ++#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ ++#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ ++#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ ++#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ ++#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ ++ ++/* GNU extension to support local ifunc. */ ++#define R_PPC_IRELATIVE 248 ++ ++/* GNU relocs used in PIC code sequences. */ ++#define R_PPC_REL16 249 /* half16 (sym+add-.) */ ++#define R_PPC_REL16_LO 250 /* half16 (sym+add-.)@l */ ++#define R_PPC_REL16_HI 251 /* half16 (sym+add-.)@h */ ++#define R_PPC_REL16_HA 252 /* half16 (sym+add-.)@ha */ ++ ++/* This is a phony reloc to handle any old fashioned TOC16 references ++ that may still be in object files. */ ++#define R_PPC_TOC16 255 ++ ++/* PowerPC specific values for the Dyn d_tag field. */ ++#define DT_PPC_GOT (DT_LOPROC + 0) ++#define DT_PPC_NUM 1 ++ ++/* PowerPC64 relocations defined by the ABIs */ ++#define R_PPC64_NONE R_PPC_NONE ++#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ ++#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ ++#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ ++#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ ++#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ ++#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ ++#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ ++#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN ++#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN ++#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ ++#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ ++#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN ++#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN ++#define R_PPC64_GOT16 R_PPC_GOT16 ++#define R_PPC64_GOT16_LO R_PPC_GOT16_LO ++#define R_PPC64_GOT16_HI R_PPC_GOT16_HI ++#define R_PPC64_GOT16_HA R_PPC_GOT16_HA ++ ++#define R_PPC64_COPY R_PPC_COPY ++#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT ++#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT ++#define R_PPC64_RELATIVE R_PPC_RELATIVE ++ ++#define R_PPC64_UADDR32 R_PPC_UADDR32 ++#define R_PPC64_UADDR16 R_PPC_UADDR16 ++#define R_PPC64_REL32 R_PPC_REL32 ++#define R_PPC64_PLT32 R_PPC_PLT32 ++#define R_PPC64_PLTREL32 R_PPC_PLTREL32 ++#define R_PPC64_PLT16_LO R_PPC_PLT16_LO ++#define R_PPC64_PLT16_HI R_PPC_PLT16_HI ++#define R_PPC64_PLT16_HA R_PPC_PLT16_HA ++ ++#define R_PPC64_SECTOFF R_PPC_SECTOFF ++#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO ++#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ++#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA ++#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ ++#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ ++#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ ++#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ ++#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ ++#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ ++#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ ++#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ ++#define R_PPC64_PLT64 45 /* doubleword64 L + A */ ++#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ ++#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ ++#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ ++#define R_PPC64_TOC 51 /* doubleword64 .TOC */ ++#define R_PPC64_PLTGOT16 52 /* half16* M + A */ ++#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ ++#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ ++#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ ++ ++#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ ++#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ ++#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ ++#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ ++#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ ++#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ ++#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ ++#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ ++#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ ++#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ ++#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ ++ ++/* PowerPC64 relocations defined for the TLS access ABI. */ ++#define R_PPC64_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ ++#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ ++#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ ++#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ ++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ ++#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ ++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ ++#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ ++#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ ++#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ ++#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ ++#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ ++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ ++#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ ++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ ++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ ++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ ++ ++/* GNU extension to support local ifunc. */ ++#define R_PPC64_JMP_IREL 247 ++#define R_PPC64_IRELATIVE 248 ++#define R_PPC64_REL16 249 /* half16 (sym+add-.) */ ++#define R_PPC64_REL16_LO 250 /* half16 (sym+add-.)@l */ ++#define R_PPC64_REL16_HI 251 /* half16 (sym+add-.)@h */ ++#define R_PPC64_REL16_HA 252 /* half16 (sym+add-.)@ha */ ++ ++/* PowerPC64 specific values for the Dyn d_tag field. */ ++#define DT_PPC64_GLINK (DT_LOPROC + 0) ++#define DT_PPC64_OPD (DT_LOPROC + 1) ++#define DT_PPC64_OPDSZ (DT_LOPROC + 2) ++#define DT_PPC64_NUM 3 ++ ++ ++/* ARM specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_ARM_RELEXEC 0x01 ++#define EF_ARM_HASENTRY 0x02 ++#define EF_ARM_INTERWORK 0x04 ++#define EF_ARM_APCS_26 0x08 ++#define EF_ARM_APCS_FLOAT 0x10 ++#define EF_ARM_PIC 0x20 ++#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ ++#define EF_ARM_NEW_ABI 0x80 ++#define EF_ARM_OLD_ABI 0x100 ++#define EF_ARM_SOFT_FLOAT 0x200 ++#define EF_ARM_VFP_FLOAT 0x400 ++#define EF_ARM_MAVERICK_FLOAT 0x800 ++ ++ ++/* Other constants defined in the ARM ELF spec. version B-01. */ ++/* NB. These conflict with values defined above. */ ++#define EF_ARM_SYMSARESORTED 0x04 ++#define EF_ARM_DYNSYMSUSESEGIDX 0x08 ++#define EF_ARM_MAPSYMSFIRST 0x10 ++#define EF_ARM_EABIMASK 0XFF000000 ++ ++/* Constants defined in AAELF. */ ++#define EF_ARM_BE8 0x00800000 ++#define EF_ARM_LE8 0x00400000 ++ ++#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) ++#define EF_ARM_EABI_UNKNOWN 0x00000000 ++#define EF_ARM_EABI_VER1 0x01000000 ++#define EF_ARM_EABI_VER2 0x02000000 ++#define EF_ARM_EABI_VER3 0x03000000 ++#define EF_ARM_EABI_VER4 0x04000000 ++#define EF_ARM_EABI_VER5 0x05000000 ++ ++/* Additional symbol types for Thumb. */ ++#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ ++#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ ++ ++/* ARM-specific values for sh_flags */ ++#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ ++#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined ++ in the input to a link step. */ ++ ++/* ARM-specific program header flags */ ++#define PF_ARM_SB 0x10000000 /* Segment contains the location ++ addressed by the static base. */ ++#define PF_ARM_PI 0x20000000 /* Position-independent segment. */ ++#define PF_ARM_ABS 0x40000000 /* Absolute segment. */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */ ++#define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */ ++#define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */ ++ ++ ++/* ARM relocs. */ ++ ++#define R_ARM_NONE 0 /* No reloc */ ++#define R_ARM_PC24 1 /* PC relative 26 bit branch */ ++#define R_ARM_ABS32 2 /* Direct 32 bit */ ++#define R_ARM_REL32 3 /* PC relative 32 bit */ ++#define R_ARM_PC13 4 ++#define R_ARM_ABS16 5 /* Direct 16 bit */ ++#define R_ARM_ABS12 6 /* Direct 12 bit */ ++#define R_ARM_THM_ABS5 7 ++#define R_ARM_ABS8 8 /* Direct 8 bit */ ++#define R_ARM_SBREL32 9 ++#define R_ARM_THM_PC22 10 ++#define R_ARM_THM_PC8 11 ++#define R_ARM_AMP_VCALL9 12 ++#define R_ARM_SWI24 13 /* Obsolete static relocation. */ ++#define R_ARM_TLS_DESC 13 /* Dynamic relocation. */ ++#define R_ARM_THM_SWI8 14 ++#define R_ARM_XPC25 15 ++#define R_ARM_THM_XPC22 16 ++#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ ++#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ ++#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ ++#define R_ARM_COPY 20 /* Copy symbol at runtime */ ++#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ ++#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ ++#define R_ARM_RELATIVE 23 /* Adjust by program base */ ++#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ ++#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ ++#define R_ARM_GOT32 26 /* 32 bit GOT entry */ ++#define R_ARM_PLT32 27 /* 32 bit PLT address */ ++#define R_ARM_ALU_PCREL_7_0 32 ++#define R_ARM_ALU_PCREL_15_8 33 ++#define R_ARM_ALU_PCREL_23_15 34 ++#define R_ARM_LDR_SBREL_11_0 35 ++#define R_ARM_ALU_SBREL_19_12 36 ++#define R_ARM_ALU_SBREL_27_20 37 ++#define R_ARM_TLS_GOTDESC 90 ++#define R_ARM_TLS_CALL 91 ++#define R_ARM_TLS_DESCSEQ 92 ++#define R_ARM_THM_TLS_CALL 93 ++#define R_ARM_GNU_VTENTRY 100 ++#define R_ARM_GNU_VTINHERIT 101 ++#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ ++#define R_ARM_THM_PC9 103 /* thumb conditional branch */ ++#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic ++ thread local data */ ++#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic ++ thread local data */ ++#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS ++ block */ ++#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of ++ static TLS block offset */ ++#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static ++ TLS block */ ++#define R_ARM_THM_TLS_DESCSEQ 129 ++#define R_ARM_IRELATIVE 160 ++#define R_ARM_RXPC25 249 ++#define R_ARM_RSBREL32 250 ++#define R_ARM_THM_RPC22 251 ++#define R_ARM_RREL32 252 ++#define R_ARM_RABS22 253 ++#define R_ARM_RPC24 254 ++#define R_ARM_RBASE 255 ++/* Keep this the last entry. */ ++#define R_ARM_NUM 256 ++ ++/* IA-64 specific declarations. */ ++ ++/* Processor specific flags for the Ehdr e_flags field. */ ++#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ ++#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ ++#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ ++#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ ++#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) ++#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) ++#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) ++ ++/* Processor specific flags for the Phdr p_flags field. */ ++#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ ++#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ ++ ++/* Processor specific flags for the Shdr sh_flags field. */ ++#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ ++#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Dyn d_tag field. */ ++#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) ++#define DT_IA_64_NUM 1 ++ ++/* IA-64 relocations. */ ++#define R_IA64_NONE 0x00 /* none */ ++#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ ++#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ ++#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ ++#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ ++#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ ++#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ ++#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ ++#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ ++#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ ++#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ ++#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ ++#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ ++#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ ++#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ ++#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ ++#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ ++#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ ++#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ ++#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ ++#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ ++#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ ++#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ ++#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ ++#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ ++#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ ++#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ ++#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ ++#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ ++#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ ++#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ ++#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ ++#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ ++#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ ++#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ ++#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ ++#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ ++#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ ++#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ ++#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ ++#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ ++#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ ++#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ ++#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ ++#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ ++#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ ++#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ ++#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ ++#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ ++#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ ++#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ ++#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ ++#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ ++#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ ++#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ ++#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ ++#define R_IA64_COPY 0x84 /* copy relocation */ ++#define R_IA64_SUB 0x85 /* Addend and symbol difference */ ++#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ ++#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ ++#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ ++#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ ++#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ ++#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ ++#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ ++#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ ++#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ ++#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ ++#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ ++#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ ++#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ ++#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ ++#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ ++#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ ++ ++/* SH specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_SH_MACH_MASK 0x1f ++#define EF_SH_UNKNOWN 0x0 ++#define EF_SH1 0x1 ++#define EF_SH2 0x2 ++#define EF_SH3 0x3 ++#define EF_SH_DSP 0x4 ++#define EF_SH3_DSP 0x5 ++#define EF_SH4AL_DSP 0x6 ++#define EF_SH3E 0x8 ++#define EF_SH4 0x9 ++#define EF_SH2E 0xb ++#define EF_SH4A 0xc ++#define EF_SH2A 0xd ++#define EF_SH4_NOFPU 0x10 ++#define EF_SH4A_NOFPU 0x11 ++#define EF_SH4_NOMMU_NOFPU 0x12 ++#define EF_SH2A_NOFPU 0x13 ++#define EF_SH3_NOMMU 0x14 ++#define EF_SH2A_SH4_NOFPU 0x15 ++#define EF_SH2A_SH3_NOFPU 0x16 ++#define EF_SH2A_SH4 0x17 ++#define EF_SH2A_SH3E 0x18 ++ ++/* SH relocs. */ ++#define R_SH_NONE 0 ++#define R_SH_DIR32 1 ++#define R_SH_REL32 2 ++#define R_SH_DIR8WPN 3 ++#define R_SH_IND12W 4 ++#define R_SH_DIR8WPL 5 ++#define R_SH_DIR8WPZ 6 ++#define R_SH_DIR8BP 7 ++#define R_SH_DIR8W 8 ++#define R_SH_DIR8L 9 ++#define R_SH_SWITCH16 25 ++#define R_SH_SWITCH32 26 ++#define R_SH_USES 27 ++#define R_SH_COUNT 28 ++#define R_SH_ALIGN 29 ++#define R_SH_CODE 30 ++#define R_SH_DATA 31 ++#define R_SH_LABEL 32 ++#define R_SH_SWITCH8 33 ++#define R_SH_GNU_VTINHERIT 34 ++#define R_SH_GNU_VTENTRY 35 ++#define R_SH_TLS_GD_32 144 ++#define R_SH_TLS_LD_32 145 ++#define R_SH_TLS_LDO_32 146 ++#define R_SH_TLS_IE_32 147 ++#define R_SH_TLS_LE_32 148 ++#define R_SH_TLS_DTPMOD32 149 ++#define R_SH_TLS_DTPOFF32 150 ++#define R_SH_TLS_TPOFF32 151 ++#define R_SH_GOT32 160 ++#define R_SH_PLT32 161 ++#define R_SH_COPY 162 ++#define R_SH_GLOB_DAT 163 ++#define R_SH_JMP_SLOT 164 ++#define R_SH_RELATIVE 165 ++#define R_SH_GOTOFF 166 ++#define R_SH_GOTPC 167 ++/* Keep this the last entry. */ ++#define R_SH_NUM 256 ++ ++/* S/390 specific definitions. */ ++ ++/* Valid values for the e_flags field. */ ++ ++#define EF_S390_HIGH_GPRS 0x00000001 /* High GPRs kernel facility needed. */ ++ ++/* Additional s390 relocs */ ++ ++#define R_390_NONE 0 /* No reloc. */ ++#define R_390_8 1 /* Direct 8 bit. */ ++#define R_390_12 2 /* Direct 12 bit. */ ++#define R_390_16 3 /* Direct 16 bit. */ ++#define R_390_32 4 /* Direct 32 bit. */ ++#define R_390_PC32 5 /* PC relative 32 bit. */ ++#define R_390_GOT12 6 /* 12 bit GOT offset. */ ++#define R_390_GOT32 7 /* 32 bit GOT offset. */ ++#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ ++#define R_390_COPY 9 /* Copy symbol at runtime. */ ++#define R_390_GLOB_DAT 10 /* Create GOT entry. */ ++#define R_390_JMP_SLOT 11 /* Create PLT entry. */ ++#define R_390_RELATIVE 12 /* Adjust by program base. */ ++#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ ++#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ ++#define R_390_GOT16 15 /* 16 bit GOT offset. */ ++#define R_390_PC16 16 /* PC relative 16 bit. */ ++#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ ++#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ ++#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ ++#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ ++#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ ++#define R_390_64 22 /* Direct 64 bit. */ ++#define R_390_PC64 23 /* PC relative 64 bit. */ ++#define R_390_GOT64 24 /* 64 bit GOT offset. */ ++#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ ++#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ ++#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ ++#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ ++#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ ++#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ ++#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ ++#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ ++#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ ++#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ ++#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ ++#define R_390_TLS_GDCALL 38 /* Tag for function call in general ++ dynamic TLS code. */ ++#define R_390_TLS_LDCALL 39 /* Tag for function call in local ++ dynamic TLS code. */ ++#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ ++#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ ++#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS ++ block. */ ++#define R_390_20 57 /* Direct 20 bit. */ ++#define R_390_GOT20 58 /* 20 bit GOT offset. */ ++#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ ++#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_IRELATIVE 61 /* STT_GNU_IFUNC relocation. */ ++/* Keep this the last entry. */ ++#define R_390_NUM 62 ++ ++ ++/* CRIS relocations. */ ++#define R_CRIS_NONE 0 ++#define R_CRIS_8 1 ++#define R_CRIS_16 2 ++#define R_CRIS_32 3 ++#define R_CRIS_8_PCREL 4 ++#define R_CRIS_16_PCREL 5 ++#define R_CRIS_32_PCREL 6 ++#define R_CRIS_GNU_VTINHERIT 7 ++#define R_CRIS_GNU_VTENTRY 8 ++#define R_CRIS_COPY 9 ++#define R_CRIS_GLOB_DAT 10 ++#define R_CRIS_JUMP_SLOT 11 ++#define R_CRIS_RELATIVE 12 ++#define R_CRIS_16_GOT 13 ++#define R_CRIS_32_GOT 14 ++#define R_CRIS_16_GOTPLT 15 ++#define R_CRIS_32_GOTPLT 16 ++#define R_CRIS_32_GOTREL 17 ++#define R_CRIS_32_PLT_GOTREL 18 ++#define R_CRIS_32_PLT_PCREL 19 ++ ++#define R_CRIS_NUM 20 ++ ++ ++/* AMD x86-64 relocations. */ ++#define R_X86_64_NONE 0 /* No reloc */ ++#define R_X86_64_64 1 /* Direct 64 bit */ ++#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ ++#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ ++#define R_X86_64_PLT32 4 /* 32 bit PLT address */ ++#define R_X86_64_COPY 5 /* Copy symbol at runtime */ ++#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ ++#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ ++#define R_X86_64_RELATIVE 8 /* Adjust by program base */ ++#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative ++ offset to GOT */ ++#define R_X86_64_32 10 /* Direct 32 bit zero extended */ ++#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ ++#define R_X86_64_16 12 /* Direct 16 bit zero extended */ ++#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ ++#define R_X86_64_8 14 /* Direct 8 bit sign extended */ ++#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ ++#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ ++#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ ++#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ ++#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset ++ to two GOT entries for GD symbol */ ++#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset ++ to two GOT entries for LD symbol */ ++#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ ++#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset ++ to GOT entry for IE symbol */ ++#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ ++#define R_X86_64_PC64 24 /* PC relative 64 bit */ ++#define R_X86_64_GOTOFF64 25 /* 64 bit offset to GOT */ ++#define R_X86_64_GOTPC32 26 /* 32 bit signed pc relative ++ offset to GOT */ ++#define R_X86_64_GOT64 27 /* 64-bit GOT entry offset */ ++#define R_X86_64_GOTPCREL64 28 /* 64-bit PC relative offset ++ to GOT entry */ ++#define R_X86_64_GOTPC64 29 /* 64-bit PC relative offset to GOT */ ++#define R_X86_64_GOTPLT64 30 /* like GOT64, says PLT entry needed */ ++#define R_X86_64_PLTOFF64 31 /* 64-bit GOT relative offset ++ to PLT entry */ ++#define R_X86_64_SIZE32 32 /* Size of symbol plus 32-bit addend */ ++#define R_X86_64_SIZE64 33 /* Size of symbol plus 64-bit addend */ ++#define R_X86_64_GOTPC32_TLSDESC 34 /* GOT offset for TLS descriptor. */ ++#define R_X86_64_TLSDESC_CALL 35 /* Marker for call through TLS ++ descriptor. */ ++#define R_X86_64_TLSDESC 36 /* TLS descriptor. */ ++#define R_X86_64_IRELATIVE 37 /* Adjust indirectly by program base */ ++#define R_X86_64_RELATIVE64 38 /* 64-bit adjust by program base */ ++ ++#define R_X86_64_NUM 39 ++ ++ ++/* AM33 relocations. */ ++#define R_MN10300_NONE 0 /* No reloc. */ ++#define R_MN10300_32 1 /* Direct 32 bit. */ ++#define R_MN10300_16 2 /* Direct 16 bit. */ ++#define R_MN10300_8 3 /* Direct 8 bit. */ ++#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ ++#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ ++#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ ++#define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ ++#define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ ++#define R_MN10300_24 9 /* Direct 24 bit. */ ++#define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ ++#define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ ++#define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ ++#define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ ++#define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ ++#define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ ++#define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ ++#define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ ++#define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ ++#define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ ++#define R_MN10300_COPY 20 /* Copy symbol at runtime. */ ++#define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ ++#define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ ++#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ ++ ++#define R_MN10300_NUM 24 ++ ++ ++/* M32R relocs. */ ++#define R_M32R_NONE 0 /* No reloc. */ ++#define R_M32R_16 1 /* Direct 16 bit. */ ++#define R_M32R_32 2 /* Direct 32 bit. */ ++#define R_M32R_24 3 /* Direct 24 bit. */ ++#define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ ++#define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ ++#define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ ++#define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ ++#define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ ++#define R_M32R_LO16 9 /* Low 16 bit. */ ++#define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ ++#define R_M32R_GNU_VTINHERIT 11 ++#define R_M32R_GNU_VTENTRY 12 ++/* M32R relocs use SHT_RELA. */ ++#define R_M32R_16_RELA 33 /* Direct 16 bit. */ ++#define R_M32R_32_RELA 34 /* Direct 32 bit. */ ++#define R_M32R_24_RELA 35 /* Direct 24 bit. */ ++#define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ ++#define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ ++#define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ ++#define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ ++#define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ ++#define R_M32R_LO16_RELA 41 /* Low 16 bit */ ++#define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ ++#define R_M32R_RELA_GNU_VTINHERIT 43 ++#define R_M32R_RELA_GNU_VTENTRY 44 ++#define R_M32R_REL32 45 /* PC relative 32 bit. */ ++ ++#define R_M32R_GOT24 48 /* 24 bit GOT entry */ ++#define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ ++#define R_M32R_COPY 50 /* Copy symbol at runtime */ ++#define R_M32R_GLOB_DAT 51 /* Create GOT entry */ ++#define R_M32R_JMP_SLOT 52 /* Create PLT entry */ ++#define R_M32R_RELATIVE 53 /* Adjust by program base */ ++#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ ++#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ ++#define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned ++ low */ ++#define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed ++ low */ ++#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ ++#define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to ++ GOT with unsigned low */ ++#define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to ++ GOT with signed low */ ++#define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to ++ GOT */ ++#define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT ++ with unsigned low */ ++#define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT ++ with signed low */ ++#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ ++#define R_M32R_NUM 256 /* Keep this the last entry. */ ++ ++ ++/* TILEPro relocations. */ ++#define R_TILEPRO_NONE 0 /* No reloc */ ++#define R_TILEPRO_32 1 /* Direct 32 bit */ ++#define R_TILEPRO_16 2 /* Direct 16 bit */ ++#define R_TILEPRO_8 3 /* Direct 8 bit */ ++#define R_TILEPRO_32_PCREL 4 /* PC relative 32 bit */ ++#define R_TILEPRO_16_PCREL 5 /* PC relative 16 bit */ ++#define R_TILEPRO_8_PCREL 6 /* PC relative 8 bit */ ++#define R_TILEPRO_LO16 7 /* Low 16 bit */ ++#define R_TILEPRO_HI16 8 /* High 16 bit */ ++#define R_TILEPRO_HA16 9 /* High 16 bit, adjusted */ ++#define R_TILEPRO_COPY 10 /* Copy relocation */ ++#define R_TILEPRO_GLOB_DAT 11 /* Create GOT entry */ ++#define R_TILEPRO_JMP_SLOT 12 /* Create PLT entry */ ++#define R_TILEPRO_RELATIVE 13 /* Adjust by program base */ ++#define R_TILEPRO_BROFF_X1 14 /* X1 pipe branch offset */ ++#define R_TILEPRO_JOFFLONG_X1 15 /* X1 pipe jump offset */ ++#define R_TILEPRO_JOFFLONG_X1_PLT 16 /* X1 pipe jump offset to PLT */ ++#define R_TILEPRO_IMM8_X0 17 /* X0 pipe 8-bit */ ++#define R_TILEPRO_IMM8_Y0 18 /* Y0 pipe 8-bit */ ++#define R_TILEPRO_IMM8_X1 19 /* X1 pipe 8-bit */ ++#define R_TILEPRO_IMM8_Y1 20 /* Y1 pipe 8-bit */ ++#define R_TILEPRO_MT_IMM15_X1 21 /* X1 pipe mtspr */ ++#define R_TILEPRO_MF_IMM15_X1 22 /* X1 pipe mfspr */ ++#define R_TILEPRO_IMM16_X0 23 /* X0 pipe 16-bit */ ++#define R_TILEPRO_IMM16_X1 24 /* X1 pipe 16-bit */ ++#define R_TILEPRO_IMM16_X0_LO 25 /* X0 pipe low 16-bit */ ++#define R_TILEPRO_IMM16_X1_LO 26 /* X1 pipe low 16-bit */ ++#define R_TILEPRO_IMM16_X0_HI 27 /* X0 pipe high 16-bit */ ++#define R_TILEPRO_IMM16_X1_HI 28 /* X1 pipe high 16-bit */ ++#define R_TILEPRO_IMM16_X0_HA 29 /* X0 pipe high 16-bit, adjusted */ ++#define R_TILEPRO_IMM16_X1_HA 30 /* X1 pipe high 16-bit, adjusted */ ++#define R_TILEPRO_IMM16_X0_PCREL 31 /* X0 pipe PC relative 16 bit */ ++#define R_TILEPRO_IMM16_X1_PCREL 32 /* X1 pipe PC relative 16 bit */ ++#define R_TILEPRO_IMM16_X0_LO_PCREL 33 /* X0 pipe PC relative low 16 bit */ ++#define R_TILEPRO_IMM16_X1_LO_PCREL 34 /* X1 pipe PC relative low 16 bit */ ++#define R_TILEPRO_IMM16_X0_HI_PCREL 35 /* X0 pipe PC relative high 16 bit */ ++#define R_TILEPRO_IMM16_X1_HI_PCREL 36 /* X1 pipe PC relative high 16 bit */ ++#define R_TILEPRO_IMM16_X0_HA_PCREL 37 /* X0 pipe PC relative ha() 16 bit */ ++#define R_TILEPRO_IMM16_X1_HA_PCREL 38 /* X1 pipe PC relative ha() 16 bit */ ++#define R_TILEPRO_IMM16_X0_GOT 39 /* X0 pipe 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT 40 /* X1 pipe 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_LO 41 /* X0 pipe low 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_LO 42 /* X1 pipe low 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_HI 43 /* X0 pipe high 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_HI 44 /* X1 pipe high 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X0_GOT_HA 45 /* X0 pipe ha() 16-bit GOT offset */ ++#define R_TILEPRO_IMM16_X1_GOT_HA 46 /* X1 pipe ha() 16-bit GOT offset */ ++#define R_TILEPRO_MMSTART_X0 47 /* X0 pipe mm "start" */ ++#define R_TILEPRO_MMEND_X0 48 /* X0 pipe mm "end" */ ++#define R_TILEPRO_MMSTART_X1 49 /* X1 pipe mm "start" */ ++#define R_TILEPRO_MMEND_X1 50 /* X1 pipe mm "end" */ ++#define R_TILEPRO_SHAMT_X0 51 /* X0 pipe shift amount */ ++#define R_TILEPRO_SHAMT_X1 52 /* X1 pipe shift amount */ ++#define R_TILEPRO_SHAMT_Y0 53 /* Y0 pipe shift amount */ ++#define R_TILEPRO_SHAMT_Y1 54 /* Y1 pipe shift amount */ ++#define R_TILEPRO_DEST_IMM8_X1 55 /* X1 pipe destination 8-bit */ ++/* Relocs 56-59 are currently not defined. */ ++#define R_TILEPRO_TLS_GD_CALL 60 /* "jal" for TLS GD */ ++#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 /* X0 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 /* X1 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 /* Y0 pipe "addi" for TLS GD */ ++#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 /* Y1 pipe "addi" for TLS GD */ ++#define R_TILEPRO_TLS_IE_LOAD 65 /* "lw_tls" for TLS IE */ ++#define R_TILEPRO_IMM16_X0_TLS_GD 66 /* X0 pipe 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD 67 /* X1 pipe 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68 /* X0 pipe low 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69 /* X1 pipe low 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70 /* X0 pipe high 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71 /* X1 pipe high 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72 /* X0 pipe ha() 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73 /* X1 pipe ha() 16-bit TLS GD offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE 74 /* X0 pipe 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE 75 /* X1 pipe 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76 /* X0 pipe low 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77 /* X1 pipe low 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78 /* X0 pipe high 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79 /* X1 pipe high 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80 /* X0 pipe ha() 16-bit TLS IE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81 /* X1 pipe ha() 16-bit TLS IE offset */ ++#define R_TILEPRO_TLS_DTPMOD32 82 /* ID of module containing symbol */ ++#define R_TILEPRO_TLS_DTPOFF32 83 /* Offset in TLS block */ ++#define R_TILEPRO_TLS_TPOFF32 84 /* Offset in static TLS block */ ++#define R_TILEPRO_IMM16_X0_TLS_LE 85 /* X0 pipe 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE 86 /* X1 pipe 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87 /* X0 pipe low 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88 /* X1 pipe low 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89 /* X0 pipe high 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90 /* X1 pipe high 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91 /* X0 pipe ha() 16-bit TLS LE offset */ ++#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92 /* X1 pipe ha() 16-bit TLS LE offset */ ++ ++#define R_TILEPRO_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ ++#define R_TILEPRO_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ ++ ++#define R_TILEPRO_NUM 130 ++ ++ ++/* TILE-Gx relocations. */ ++#define R_TILEGX_NONE 0 /* No reloc */ ++#define R_TILEGX_64 1 /* Direct 64 bit */ ++#define R_TILEGX_32 2 /* Direct 32 bit */ ++#define R_TILEGX_16 3 /* Direct 16 bit */ ++#define R_TILEGX_8 4 /* Direct 8 bit */ ++#define R_TILEGX_64_PCREL 5 /* PC relative 64 bit */ ++#define R_TILEGX_32_PCREL 6 /* PC relative 32 bit */ ++#define R_TILEGX_16_PCREL 7 /* PC relative 16 bit */ ++#define R_TILEGX_8_PCREL 8 /* PC relative 8 bit */ ++#define R_TILEGX_HW0 9 /* hword 0 16-bit */ ++#define R_TILEGX_HW1 10 /* hword 1 16-bit */ ++#define R_TILEGX_HW2 11 /* hword 2 16-bit */ ++#define R_TILEGX_HW3 12 /* hword 3 16-bit */ ++#define R_TILEGX_HW0_LAST 13 /* last hword 0 16-bit */ ++#define R_TILEGX_HW1_LAST 14 /* last hword 1 16-bit */ ++#define R_TILEGX_HW2_LAST 15 /* last hword 2 16-bit */ ++#define R_TILEGX_COPY 16 /* Copy relocation */ ++#define R_TILEGX_GLOB_DAT 17 /* Create GOT entry */ ++#define R_TILEGX_JMP_SLOT 18 /* Create PLT entry */ ++#define R_TILEGX_RELATIVE 19 /* Adjust by program base */ ++#define R_TILEGX_BROFF_X1 20 /* X1 pipe branch offset */ ++#define R_TILEGX_JUMPOFF_X1 21 /* X1 pipe jump offset */ ++#define R_TILEGX_JUMPOFF_X1_PLT 22 /* X1 pipe jump offset to PLT */ ++#define R_TILEGX_IMM8_X0 23 /* X0 pipe 8-bit */ ++#define R_TILEGX_IMM8_Y0 24 /* Y0 pipe 8-bit */ ++#define R_TILEGX_IMM8_X1 25 /* X1 pipe 8-bit */ ++#define R_TILEGX_IMM8_Y1 26 /* Y1 pipe 8-bit */ ++#define R_TILEGX_DEST_IMM8_X1 27 /* X1 pipe destination 8-bit */ ++#define R_TILEGX_MT_IMM14_X1 28 /* X1 pipe mtspr */ ++#define R_TILEGX_MF_IMM14_X1 29 /* X1 pipe mfspr */ ++#define R_TILEGX_MMSTART_X0 30 /* X0 pipe mm "start" */ ++#define R_TILEGX_MMEND_X0 31 /* X0 pipe mm "end" */ ++#define R_TILEGX_SHAMT_X0 32 /* X0 pipe shift amount */ ++#define R_TILEGX_SHAMT_X1 33 /* X1 pipe shift amount */ ++#define R_TILEGX_SHAMT_Y0 34 /* Y0 pipe shift amount */ ++#define R_TILEGX_SHAMT_Y1 35 /* Y1 pipe shift amount */ ++#define R_TILEGX_IMM16_X0_HW0 36 /* X0 pipe hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0 37 /* X1 pipe hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1 38 /* X0 pipe hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1 39 /* X1 pipe hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2 40 /* X0 pipe hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2 41 /* X1 pipe hword 2 */ ++#define R_TILEGX_IMM16_X0_HW3 42 /* X0 pipe hword 3 */ ++#define R_TILEGX_IMM16_X1_HW3 43 /* X1 pipe hword 3 */ ++#define R_TILEGX_IMM16_X0_HW0_LAST 44 /* X0 pipe last hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_LAST 45 /* X1 pipe last hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_LAST 46 /* X0 pipe last hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_LAST 47 /* X1 pipe last hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_LAST 48 /* X0 pipe last hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_LAST 49 /* X1 pipe last hword 2 */ ++#define R_TILEGX_IMM16_X0_HW0_PCREL 50 /* X0 pipe PC relative hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_PCREL 51 /* X1 pipe PC relative hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_PCREL 52 /* X0 pipe PC relative hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_PCREL 53 /* X1 pipe PC relative hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_PCREL 54 /* X0 pipe PC relative hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_PCREL 55 /* X1 pipe PC relative hword 2 */ ++#define R_TILEGX_IMM16_X0_HW3_PCREL 56 /* X0 pipe PC relative hword 3 */ ++#define R_TILEGX_IMM16_X1_HW3_PCREL 57 /* X1 pipe PC relative hword 3 */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */ ++#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */ ++#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */ ++#define R_TILEGX_IMM16_X0_HW0_GOT 64 /* X0 pipe hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW0_GOT 65 /* X1 pipe hword 0 GOT offset */ ++/* Relocs 66-71 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */ ++/* Relocs 76-77 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78 /* X0 pipe hword 0 TLS GD offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79 /* X1 pipe hword 0 TLS GD offset */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80 /* X0 pipe hword 0 TLS LE offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81 /* X1 pipe hword 0 TLS LE offset */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */ ++/* Relocs 90-91 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92 /* X0 pipe hword 0 TLS IE offset */ ++#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93 /* X1 pipe hword 0 TLS IE offset */ ++/* Relocs 94-99 are currently not defined. */ ++#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */ ++#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */ ++#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */ ++#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */ ++/* Relocs 104-105 are currently not defined. */ ++#define R_TILEGX_TLS_DTPMOD64 106 /* 64-bit ID of symbol's module */ ++#define R_TILEGX_TLS_DTPOFF64 107 /* 64-bit offset in TLS block */ ++#define R_TILEGX_TLS_TPOFF64 108 /* 64-bit offset in static TLS block */ ++#define R_TILEGX_TLS_DTPMOD32 109 /* 32-bit ID of symbol's module */ ++#define R_TILEGX_TLS_DTPOFF32 110 /* 32-bit offset in TLS block */ ++#define R_TILEGX_TLS_TPOFF32 111 /* 32-bit offset in static TLS block */ ++#define R_TILEGX_TLS_GD_CALL 112 /* "jal" for TLS GD */ ++#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113 /* X0 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114 /* X1 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 /* Y0 pipe "addi" for TLS GD */ ++#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 /* Y1 pipe "addi" for TLS GD */ ++#define R_TILEGX_TLS_IE_LOAD 117 /* "ld_tls" for TLS IE */ ++#define R_TILEGX_IMM8_X0_TLS_ADD 118 /* X0 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_X1_TLS_ADD 119 /* X1 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_Y0_TLS_ADD 120 /* Y0 pipe "addi" for TLS GD/IE */ ++#define R_TILEGX_IMM8_Y1_TLS_ADD 121 /* Y1 pipe "addi" for TLS GD/IE */ ++ ++#define R_TILEGX_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ ++#define R_TILEGX_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ ++ ++#define R_TILEGX_NUM 130 ++ ++#endif /* elf.h */ diff --git a/target/linux/generic/patches-4.3/212-byteshift_portability.patch b/target/linux/generic/patches-4.3/212-byteshift_portability.patch new file mode 100644 index 0000000..0f23ba9 --- /dev/null +++ b/target/linux/generic/patches-4.3/212-byteshift_portability.patch @@ -0,0 +1,51 @@ +--- a/tools/include/tools/be_byteshift.h ++++ b/tools/include/tools/be_byteshift.h +@@ -1,6 +1,10 @@ + #ifndef _TOOLS_BE_BYTESHIFT_H + #define _TOOLS_BE_BYTESHIFT_H + ++#ifndef __linux__ ++#include "linux_types.h" ++#endif ++ + #include + + static inline uint16_t __get_unaligned_be16(const uint8_t *p) +--- a/tools/include/tools/le_byteshift.h ++++ b/tools/include/tools/le_byteshift.h +@@ -1,6 +1,10 @@ + #ifndef _TOOLS_LE_BYTESHIFT_H + #define _TOOLS_LE_BYTESHIFT_H + ++#ifndef __linux__ ++#include "linux_types.h" ++#endif ++ + #include + + static inline uint16_t __get_unaligned_le16(const uint8_t *p) +--- /dev/null ++++ b/tools/include/tools/linux_types.h +@@ -0,0 +1,22 @@ ++#ifndef __LINUX_TYPES_H ++#define __LINUX_TYPES_H ++ ++#include ++ ++typedef uint8_t __u8; ++typedef uint8_t __be8; ++typedef uint8_t __le8; ++ ++typedef uint16_t __u16; ++typedef uint16_t __be16; ++typedef uint16_t __le16; ++ ++typedef uint32_t __u32; ++typedef uint32_t __be32; ++typedef uint32_t __le32; ++ ++typedef uint64_t __u64; ++typedef uint64_t __be64; ++typedef uint64_t __le64; ++ ++#endif diff --git a/target/linux/generic/patches-4.3/214-spidev_h_portability.patch b/target/linux/generic/patches-4.3/214-spidev_h_portability.patch new file mode 100644 index 0000000..dbee090 --- /dev/null +++ b/target/linux/generic/patches-4.3/214-spidev_h_portability.patch @@ -0,0 +1,11 @@ +--- a/include/uapi/linux/spi/spidev.h ++++ b/include/uapi/linux/spi/spidev.h +@@ -111,7 +111,7 @@ struct spi_ioc_transfer { + + /* not all platforms use or _IOC_TYPECHECK() ... */ + #define SPI_MSGSIZE(N) \ +- ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ ++ ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << 13)) \ + ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) + #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + diff --git a/target/linux/generic/patches-4.3/220-gc_sections.patch b/target/linux/generic/patches-4.3/220-gc_sections.patch new file mode 100644 index 0000000..8eabe5f --- /dev/null +++ b/target/linux/generic/patches-4.3/220-gc_sections.patch @@ -0,0 +1,536 @@ +From: Felix Fietkau + +use -ffunction-sections, -fdata-sections and --gc-sections + +In combination with kernel symbol export stripping this significantly reduces +the kernel image size. Used on both ARM and MIPS architectures. + +Signed-off-by: Felix Fietkau +Signed-off-by: Jonas Gorski +Signed-off-by: Gabor Juhos +--- + +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -89,10 +89,14 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + # + cflags-y += -G 0 -mno-abicalls -fno-pic -pipe + cflags-y += -msoft-float +-LDFLAGS_vmlinux += -G 0 -static -n -nostdlib ++LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections + KBUILD_AFLAGS_MODULE += -mlong-calls + KBUILD_CFLAGS_MODULE += -mlong-calls + ++ifndef CONFIG_FUNCTION_TRACER ++KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections ++endif ++ + # + # pass -msoft-float to GAS if it supports it. However on newer binutils + # (specifically newer than 2.24.51.20140728) we then also need to explicitly +--- a/arch/mips/kernel/vmlinux.lds.S ++++ b/arch/mips/kernel/vmlinux.lds.S +@@ -67,7 +67,7 @@ SECTIONS + /* Exception table for data bus errors */ + __dbe_table : { + __start___dbe_table = .; +- *(__dbe_table) ++ KEEP(*(__dbe_table)) + __stop___dbe_table = .; + } + +@@ -112,7 +112,7 @@ SECTIONS + . = ALIGN(4); + .mips.machines.init : AT(ADDR(.mips.machines.init) - LOAD_OFFSET) { + __mips_machines_start = .; +- *(.mips.machines.init) ++ KEEP(*(.mips.machines.init)) + __mips_machines_end = .; + } + +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -89,7 +89,7 @@ + #ifdef CONFIG_FTRACE_MCOUNT_RECORD + #define MCOUNT_REC() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_mcount_loc) = .; \ +- *(__mcount_loc) \ ++ KEEP(*(__mcount_loc)) \ + VMLINUX_SYMBOL(__stop_mcount_loc) = .; + #else + #define MCOUNT_REC() +@@ -97,7 +97,7 @@ + + #ifdef CONFIG_TRACE_BRANCH_PROFILING + #define LIKELY_PROFILE() VMLINUX_SYMBOL(__start_annotated_branch_profile) = .; \ +- *(_ftrace_annotated_branch) \ ++ KEEP(*(_ftrace_annotated_branch)) \ + VMLINUX_SYMBOL(__stop_annotated_branch_profile) = .; + #else + #define LIKELY_PROFILE() +@@ -105,7 +105,7 @@ + + #ifdef CONFIG_PROFILE_ALL_BRANCHES + #define BRANCH_PROFILE() VMLINUX_SYMBOL(__start_branch_profile) = .; \ +- *(_ftrace_branch) \ ++ KEEP(*(_ftrace_branch)) \ + VMLINUX_SYMBOL(__stop_branch_profile) = .; + #else + #define BRANCH_PROFILE() +@@ -114,7 +114,7 @@ + #ifdef CONFIG_KPROBES + #define KPROBE_BLACKLIST() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_kprobe_blacklist) = .; \ +- *(_kprobe_blacklist) \ ++ KEEP(*(_kprobe_blacklist)) \ + VMLINUX_SYMBOL(__stop_kprobe_blacklist) = .; + #else + #define KPROBE_BLACKLIST() +@@ -123,10 +123,10 @@ + #ifdef CONFIG_EVENT_TRACING + #define FTRACE_EVENTS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_ftrace_events) = .; \ +- *(_ftrace_events) \ ++ KEEP(*(_ftrace_events)) \ + VMLINUX_SYMBOL(__stop_ftrace_events) = .; \ + VMLINUX_SYMBOL(__start_ftrace_enum_maps) = .; \ +- *(_ftrace_enum_map) \ ++ KEEP(*(_ftrace_enum_map)) \ + VMLINUX_SYMBOL(__stop_ftrace_enum_maps) = .; + #else + #define FTRACE_EVENTS() +@@ -134,7 +134,7 @@ + + #ifdef CONFIG_TRACING + #define TRACE_PRINTKS() VMLINUX_SYMBOL(__start___trace_bprintk_fmt) = .; \ +- *(__trace_printk_fmt) /* Trace_printk fmt' pointer */ \ ++ KEEP(*(__trace_printk_fmt)) /* Trace_printk fmt' pointer */ \ + VMLINUX_SYMBOL(__stop___trace_bprintk_fmt) = .; + #define TRACEPOINT_STR() VMLINUX_SYMBOL(__start___tracepoint_str) = .; \ + *(__tracepoint_str) /* Trace_printk fmt' pointer */ \ +@@ -147,7 +147,7 @@ + #ifdef CONFIG_FTRACE_SYSCALLS + #define TRACE_SYSCALLS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__start_syscalls_metadata) = .; \ +- *(__syscalls_metadata) \ ++ KEEP(*(__syscalls_metadata)) \ + VMLINUX_SYMBOL(__stop_syscalls_metadata) = .; + #else + #define TRACE_SYSCALLS() +@@ -169,8 +169,8 @@ + #define _OF_TABLE_1(name) \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__##name##_of_table) = .; \ +- *(__##name##_of_table) \ +- *(__##name##_of_table_end) ++ KEEP(*(__##name##_of_table)) \ ++ KEEP(*(__##name##_of_table_end)) + + #define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc) + #define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip) +@@ -184,7 +184,7 @@ + #define KERNEL_DTB() \ + STRUCT_ALIGN(); \ + VMLINUX_SYMBOL(__dtb_start) = .; \ +- *(.dtb.init.rodata) \ ++ KEEP(*(.dtb.init.rodata)) \ + VMLINUX_SYMBOL(__dtb_end) = .; + + /* .data section */ +@@ -200,16 +200,17 @@ + /* implement dynamic printk debug */ \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__start___jump_table) = .; \ +- *(__jump_table) \ ++ KEEP(*(__jump_table)) \ + VMLINUX_SYMBOL(__stop___jump_table) = .; \ + . = ALIGN(8); \ + VMLINUX_SYMBOL(__start___verbose) = .; \ +- *(__verbose) \ ++ KEEP(*(__verbose)) \ + VMLINUX_SYMBOL(__stop___verbose) = .; \ + LIKELY_PROFILE() \ + BRANCH_PROFILE() \ + TRACE_PRINTKS() \ +- TRACEPOINT_STR() ++ TRACEPOINT_STR() \ ++ *(.data.[a-zA-Z_]*) + + /* + * Data section helpers +@@ -263,35 +264,35 @@ + /* PCI quirks */ \ + .pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \ +- *(.pci_fixup_early) \ ++ KEEP(*(.pci_fixup_early)) \ + VMLINUX_SYMBOL(__end_pci_fixups_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_header) = .; \ +- *(.pci_fixup_header) \ ++ KEEP(*(.pci_fixup_header)) \ + VMLINUX_SYMBOL(__end_pci_fixups_header) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_final) = .; \ +- *(.pci_fixup_final) \ ++ KEEP(*(.pci_fixup_final)) \ + VMLINUX_SYMBOL(__end_pci_fixups_final) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_enable) = .; \ +- *(.pci_fixup_enable) \ ++ KEEP(*(.pci_fixup_enable)) \ + VMLINUX_SYMBOL(__end_pci_fixups_enable) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume) = .; \ +- *(.pci_fixup_resume) \ ++ KEEP(*(.pci_fixup_resume)) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_resume_early) = .; \ +- *(.pci_fixup_resume_early) \ ++ KEEP(*(.pci_fixup_resume_early)) \ + VMLINUX_SYMBOL(__end_pci_fixups_resume_early) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend) = .; \ +- *(.pci_fixup_suspend) \ ++ KEEP(*(.pci_fixup_suspend)) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend) = .; \ + VMLINUX_SYMBOL(__start_pci_fixups_suspend_late) = .; \ +- *(.pci_fixup_suspend_late) \ ++ KEEP(*(.pci_fixup_suspend_late)) \ + VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \ + } \ + \ + /* Built-in firmware blobs */ \ + .builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_builtin_fw) = .; \ +- *(.builtin_fw) \ ++ KEEP(*(.builtin_fw)) \ + VMLINUX_SYMBOL(__end_builtin_fw) = .; \ + } \ + \ +@@ -300,49 +301,49 @@ + /* Kernel symbol table: Normal symbols */ \ + __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab) = .; \ +- *(SORT(___ksymtab+*)) \ ++ KEEP(*(SORT(___ksymtab+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \ +- *(SORT(___ksymtab_gpl+*)) \ ++ KEEP(*(SORT(___ksymtab_gpl+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \ + } \ + \ + /* Kernel symbol table: Normal unused symbols */ \ + __ksymtab_unused : AT(ADDR(__ksymtab_unused) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_unused) = .; \ +- *(SORT(___ksymtab_unused+*)) \ ++ KEEP(*(SORT(___ksymtab_unused+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_unused) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only unused symbols */ \ + __ksymtab_unused_gpl : AT(ADDR(__ksymtab_unused_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_unused_gpl) = .; \ +- *(SORT(___ksymtab_unused_gpl+*)) \ ++ KEEP(*(SORT(___ksymtab_unused_gpl+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_unused_gpl) = .; \ + } \ + \ + /* Kernel symbol table: GPL-future-only symbols */ \ + __ksymtab_gpl_future : AT(ADDR(__ksymtab_gpl_future) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl_future) = .; \ +- *(SORT(___ksymtab_gpl_future+*)) \ ++ KEEP(*(SORT(___ksymtab_gpl_future+*))) \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl_future) = .; \ + } \ + \ + /* Kernel symbol table: Normal symbols */ \ + __kcrctab : AT(ADDR(__kcrctab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab) = .; \ +- *(SORT(___kcrctab+*)) \ ++ KEEP(*(SORT(___kcrctab+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_gpl) = .; \ +- *(SORT(___kcrctab_gpl+*)) \ ++ KEEP(*(SORT(___kcrctab_gpl+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_gpl) = .; \ + } \ + \ +@@ -356,14 +357,14 @@ + /* Kernel symbol table: GPL-only unused symbols */ \ + __kcrctab_unused_gpl : AT(ADDR(__kcrctab_unused_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_unused_gpl) = .; \ +- *(SORT(___kcrctab_unused_gpl+*)) \ ++ KEEP(*(SORT(___kcrctab_unused_gpl+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_unused_gpl) = .; \ + } \ + \ + /* Kernel symbol table: GPL-future-only symbols */ \ + __kcrctab_gpl_future : AT(ADDR(__kcrctab_gpl_future) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___kcrctab_gpl_future) = .; \ +- *(SORT(___kcrctab_gpl_future+*)) \ ++ KEEP(*(SORT(___kcrctab_gpl_future+*))) \ + VMLINUX_SYMBOL(__stop___kcrctab_gpl_future) = .; \ + } \ + \ +@@ -382,14 +383,14 @@ + /* Built-in module parameters. */ \ + __param : AT(ADDR(__param) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___param) = .; \ +- *(__param) \ ++ KEEP(*(__param)) \ + VMLINUX_SYMBOL(__stop___param) = .; \ + } \ + \ + /* Built-in module versions. */ \ + __modver : AT(ADDR(__modver) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___modver) = .; \ +- *(__modver) \ ++ KEEP(*(__modver)) \ + VMLINUX_SYMBOL(__stop___modver) = .; \ + . = ALIGN((align)); \ + VMLINUX_SYMBOL(__end_rodata) = .; \ +@@ -443,7 +444,7 @@ + #define ENTRY_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__entry_text_start) = .; \ +- *(.entry.text) \ ++ KEEP(*(.entry.text)) \ + VMLINUX_SYMBOL(__entry_text_end) = .; + + #ifdef CONFIG_FUNCTION_GRAPH_TRACER +@@ -471,7 +472,7 @@ + . = ALIGN(align); \ + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ex_table) = .; \ +- *(__ex_table) \ ++ KEEP(*(__ex_table)) \ + VMLINUX_SYMBOL(__stop___ex_table) = .; \ + } + +@@ -487,9 +488,9 @@ + #ifdef CONFIG_CONSTRUCTORS + #define KERNEL_CTORS() . = ALIGN(8); \ + VMLINUX_SYMBOL(__ctors_start) = .; \ +- *(.ctors) \ ++ KEEP(*(.ctors)) \ + *(SORT(.init_array.*)) \ +- *(.init_array) \ ++ KEEP(*(.init_array)) \ + VMLINUX_SYMBOL(__ctors_end) = .; + #else + #define KERNEL_CTORS() +@@ -540,7 +541,7 @@ + #define SBSS(sbss_align) \ + . = ALIGN(sbss_align); \ + .sbss : AT(ADDR(.sbss) - LOAD_OFFSET) { \ +- *(.sbss) \ ++ *(.sbss .sbss.*) \ + *(.scommon) \ + } + +@@ -558,7 +559,7 @@ + BSS_FIRST_SECTIONS \ + *(.bss..page_aligned) \ + *(.dynbss) \ +- *(.bss) \ ++ *(.bss .bss.*) \ + *(COMMON) \ + } + +@@ -607,7 +608,7 @@ + . = ALIGN(8); \ + __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___bug_table) = .; \ +- *(__bug_table) \ ++ KEEP(*(__bug_table)) \ + VMLINUX_SYMBOL(__stop___bug_table) = .; \ + } + #else +@@ -619,7 +620,7 @@ + . = ALIGN(4); \ + .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__tracedata_start) = .; \ +- *(.tracedata) \ ++ KEEP(*(.tracedata)) \ + VMLINUX_SYMBOL(__tracedata_end) = .; \ + } + #else +@@ -636,17 +637,17 @@ + #define INIT_SETUP(initsetup_align) \ + . = ALIGN(initsetup_align); \ + VMLINUX_SYMBOL(__setup_start) = .; \ +- *(.init.setup) \ ++ KEEP(*(.init.setup)) \ + VMLINUX_SYMBOL(__setup_end) = .; + + #define INIT_CALLS_LEVEL(level) \ + VMLINUX_SYMBOL(__initcall##level##_start) = .; \ +- *(.initcall##level##.init) \ +- *(.initcall##level##s.init) \ ++ KEEP(*(.initcall##level##.init)) \ ++ KEEP(*(.initcall##level##s.init)) \ + + #define INIT_CALLS \ + VMLINUX_SYMBOL(__initcall_start) = .; \ +- *(.initcallearly.init) \ ++ KEEP(*(.initcallearly.init)) \ + INIT_CALLS_LEVEL(0) \ + INIT_CALLS_LEVEL(1) \ + INIT_CALLS_LEVEL(2) \ +@@ -660,21 +661,21 @@ + + #define CON_INITCALL \ + VMLINUX_SYMBOL(__con_initcall_start) = .; \ +- *(.con_initcall.init) \ ++ KEEP(*(.con_initcall.init)) \ + VMLINUX_SYMBOL(__con_initcall_end) = .; + + #define SECURITY_INITCALL \ + VMLINUX_SYMBOL(__security_initcall_start) = .; \ +- *(.security_initcall.init) \ ++ KEEP(*(.security_initcall.init)) \ + VMLINUX_SYMBOL(__security_initcall_end) = .; + + #ifdef CONFIG_BLK_DEV_INITRD + #define INIT_RAM_FS \ + . = ALIGN(4); \ + VMLINUX_SYMBOL(__initramfs_start) = .; \ +- *(.init.ramfs) \ ++ KEEP(*(.init.ramfs)) \ + . = ALIGN(8); \ +- *(.init.ramfs.info) ++ KEEP(*(.init.ramfs.info)) + #else + #define INIT_RAM_FS + #endif +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -22,11 +22,16 @@ endif + ifeq ($(CONFIG_ARM_MODULE_PLTS),y) + LDFLAGS_MODULE += -T $(srctree)/arch/arm/kernel/module.lds + endif ++LDFLAGS_vmlinux += --gc-sections + + OBJCOPYFLAGS :=-O binary -R .comment -S + GZFLAGS :=-9 + #KBUILD_CFLAGS +=-pipe + ++ifndef CONFIG_FUNCTION_TRACER ++KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections ++endif ++ + # Never generate .eh_frame + KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) + +--- a/arch/arm/kernel/vmlinux.lds.S ++++ b/arch/arm/kernel/vmlinux.lds.S +@@ -15,13 +15,13 @@ + #define PROC_INFO \ + . = ALIGN(4); \ + VMLINUX_SYMBOL(__proc_info_begin) = .; \ +- *(.proc.info.init) \ ++ KEEP(*(.proc.info.init)) \ + VMLINUX_SYMBOL(__proc_info_end) = .; + + #define IDMAP_TEXT \ + ALIGN_FUNCTION(); \ + VMLINUX_SYMBOL(__idmap_text_start) = .; \ +- *(.idmap.text) \ ++ KEEP(*(.idmap.text)) \ + VMLINUX_SYMBOL(__idmap_text_end) = .; \ + . = ALIGN(PAGE_SIZE); \ + VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \ +@@ -102,7 +102,7 @@ SECTIONS + _stext = .; /* Text and read-only data */ + IDMAP_TEXT + __exception_text_start = .; +- *(.exception.text) ++ KEEP(*(.exception.text)) + __exception_text_end = .; + IRQENTRY_TEXT + TEXT_TEXT +@@ -126,7 +126,7 @@ SECTIONS + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { + __start___ex_table = .; + #ifdef CONFIG_MMU +- *(__ex_table) ++ KEEP(*(__ex_table)) + #endif + __stop___ex_table = .; + } +@@ -138,12 +138,12 @@ SECTIONS + . = ALIGN(8); + .ARM.unwind_idx : { + __start_unwind_idx = .; +- *(.ARM.exidx*) ++ KEEP(*(.ARM.exidx*)) + __stop_unwind_idx = .; + } + .ARM.unwind_tab : { + __start_unwind_tab = .; +- *(.ARM.extab*) ++ KEEP(*(.ARM.extab*)) + __stop_unwind_tab = .; + } + #endif +@@ -166,14 +166,14 @@ SECTIONS + */ + __vectors_start = .; + .vectors 0 : AT(__vectors_start) { +- *(.vectors) ++ KEEP(*(.vectors)) + } + . = __vectors_start + SIZEOF(.vectors); + __vectors_end = .; + + __stubs_start = .; + .stubs 0x1000 : AT(__stubs_start) { +- *(.stubs) ++ KEEP(*(.stubs)) + } + . = __stubs_start + SIZEOF(.stubs); + __stubs_end = .; +@@ -187,24 +187,24 @@ SECTIONS + } + .init.arch.info : { + __arch_info_begin = .; +- *(.arch.info.init) ++ KEEP(*(.arch.info.init)) + __arch_info_end = .; + } + .init.tagtable : { + __tagtable_begin = .; +- *(.taglist.init) ++ KEEP(*(.taglist.init)) + __tagtable_end = .; + } + #ifdef CONFIG_SMP_ON_UP + .init.smpalt : { + __smpalt_begin = .; +- *(.alt.smp.init) ++ KEEP(*(.alt.smp.init)) + __smpalt_end = .; + } + #endif + .init.pv_table : { + __pv_table_begin = .; +- *(.pv_table) ++ KEEP(*(.pv_table)) + __pv_table_end = .; + } + .init.data : { +--- a/arch/arm/boot/compressed/Makefile ++++ b/arch/arm/boot/compressed/Makefile +@@ -105,6 +105,7 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) + ORIG_CFLAGS := $(KBUILD_CFLAGS) + KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) + endif ++KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL)) + + ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) + asflags-y := -DZIMAGE diff --git a/target/linux/generic/patches-4.3/221-module_exports.patch b/target/linux/generic/patches-4.3/221-module_exports.patch new file mode 100644 index 0000000..02687fe --- /dev/null +++ b/target/linux/generic/patches-4.3/221-module_exports.patch @@ -0,0 +1,88 @@ +--- a/include/asm-generic/vmlinux.lds.h ++++ b/include/asm-generic/vmlinux.lds.h +@@ -54,6 +54,16 @@ + #define LOAD_OFFSET 0 + #endif + ++#ifndef SYMTAB_KEEP ++#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*))) ++#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*))) ++#endif ++ ++#ifndef SYMTAB_DISCARD ++#define SYMTAB_DISCARD ++#define SYMTAB_DISCARD_GPL ++#endif ++ + #include + + /* Align . to a 8 byte boundary equals to maximum function alignment. */ +@@ -301,14 +311,14 @@ + /* Kernel symbol table: Normal symbols */ \ + __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab) = .; \ +- KEEP(*(SORT(___ksymtab+*))) \ ++ SYMTAB_KEEP \ + VMLINUX_SYMBOL(__stop___ksymtab) = .; \ + } \ + \ + /* Kernel symbol table: GPL-only symbols */ \ + __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start___ksymtab_gpl) = .; \ +- KEEP(*(SORT(___ksymtab_gpl+*))) \ ++ SYMTAB_KEEP_GPL \ + VMLINUX_SYMBOL(__stop___ksymtab_gpl) = .; \ + } \ + \ +@@ -370,7 +380,7 @@ + \ + /* Kernel symbol table: strings */ \ + __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \ +- *(__ksymtab_strings) \ ++ *(__ksymtab_strings+*) \ + } \ + \ + /* __*init sections */ \ +@@ -694,6 +704,8 @@ + EXIT_TEXT \ + EXIT_DATA \ + EXIT_CALL \ ++ SYMTAB_DISCARD \ ++ SYMTAB_DISCARD_GPL \ + *(.discard) \ + *(.discard.*) \ + } +--- a/scripts/Makefile.build ++++ b/scripts/Makefile.build +@@ -299,7 +299,7 @@ targets += $(extra-y) $(MAKECMDGOALS) $( + # Linker scripts preprocessor (.lds.S -> .lds) + # --------------------------------------------------------------------------- + quiet_cmd_cpp_lds_S = LDS $@ +- cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -C -U$(ARCH) \ ++ cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -C -U$(ARCH) \ + -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< + + $(obj)/%.lds: $(src)/%.lds.S FORCE +--- a/include/linux/export.h ++++ b/include/linux/export.h +@@ -52,12 +52,19 @@ extern struct module __this_module; + #define __CRC_SYMBOL(sym, sec) + #endif + ++#ifdef MODULE ++#define __EXPORT_SUFFIX(sym) ++#else ++#define __EXPORT_SUFFIX(sym) "+" #sym ++#endif ++ + /* For every exported symbol, place a struct in the __ksymtab section */ + #define __EXPORT_SYMBOL(sym, sec) \ + extern typeof(sym) sym; \ + __CRC_SYMBOL(sym, sec) \ + static const char __kstrtab_##sym[] \ +- __attribute__((section("__ksymtab_strings"), aligned(1))) \ ++ __attribute__((section("__ksymtab_strings" \ ++ __EXPORT_SUFFIX(sym)), aligned(1))) \ + = VMLINUX_SYMBOL_STR(sym); \ + extern const struct kernel_symbol __ksymtab_##sym; \ + __visible const struct kernel_symbol __ksymtab_##sym \ diff --git a/target/linux/generic/patches-4.3/230-openwrt_lzma_options.patch b/target/linux/generic/patches-4.3/230-openwrt_lzma_options.patch new file mode 100644 index 0000000..d5bbb19 --- /dev/null +++ b/target/linux/generic/patches-4.3/230-openwrt_lzma_options.patch @@ -0,0 +1,58 @@ +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -324,7 +324,7 @@ cmd_bzip2 = (cat $(filter-out FORCE,$^) + + quiet_cmd_lzma = LZMA $@ + cmd_lzma = (cat $(filter-out FORCE,$^) | \ +- lzma -9 && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ ++ lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so && $(call size_append, $(filter-out FORCE,$^))) > $@ || \ + (rm -f $@ ; false) + + quiet_cmd_lzo = LZO $@ +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -226,7 +226,7 @@ cpio_list= + output="/dev/stdout" + output_file="" + is_cpio_compressed= +-compr="gzip -n -9 -f" ++compr="gzip -n -9 -f -" + + arg="$1" + case "$arg" in +@@ -242,13 +242,13 @@ case "$arg" in + output=${cpio_list} + echo "$output_file" | grep -q "\.gz$" \ + && [ -x "`which gzip 2> /dev/null`" ] \ +- && compr="gzip -n -9 -f" ++ && compr="gzip -n -9 -f -" + echo "$output_file" | grep -q "\.bz2$" \ + && [ -x "`which bzip2 2> /dev/null`" ] \ +- && compr="bzip2 -9 -f" ++ && compr="bzip2 -9 -f -" + echo "$output_file" | grep -q "\.lzma$" \ + && [ -x "`which lzma 2> /dev/null`" ] \ +- && compr="lzma -9 -f" ++ && compr="lzma e -d20 -lc1 -lp2 -pb2 -eos -si -so" + echo "$output_file" | grep -q "\.xz$" \ + && [ -x "`which xz 2> /dev/null`" ] \ + && compr="xz --check=crc32 --lzma2=dict=1MiB" +@@ -315,7 +315,7 @@ if [ ! -z ${output_file} ]; then + if [ "${is_cpio_compressed}" = "compressed" ]; then + cat ${cpio_tfile} > ${output_file} + else +- (cat ${cpio_tfile} | ${compr} - > ${output_file}) \ ++ (cat ${cpio_tfile} | ${compr} > ${output_file}) \ + || (rm -f ${output_file} ; false) + fi + [ -z ${cpio_file} ] && rm ${cpio_tfile} +--- a/lib/decompress.c ++++ b/lib/decompress.c +@@ -48,6 +48,7 @@ static const struct compress_format comp + { {0x1f, 0x9e}, "gzip", gunzip }, + { {0x42, 0x5a}, "bzip2", bunzip2 }, + { {0x5d, 0x00}, "lzma", unlzma }, ++ { {0x6d, 0x00}, "lzma-openwrt", unlzma }, + { {0xfd, 0x37}, "xz", unxz }, + { {0x89, 0x4c}, "lzo", unlzo }, + { {0x02, 0x21}, "lz4", unlz4 }, diff --git a/target/linux/generic/patches-4.3/250-netfilter_depends.patch b/target/linux/generic/patches-4.3/250-netfilter_depends.patch new file mode 100644 index 0000000..e19407d --- /dev/null +++ b/target/linux/generic/patches-4.3/250-netfilter_depends.patch @@ -0,0 +1,18 @@ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -218,7 +218,6 @@ config NF_CONNTRACK_FTP + + config NF_CONNTRACK_H323 + tristate "H.323 protocol support" +- depends on IPV6 || IPV6=n + depends on NETFILTER_ADVANCED + help + H.323 is a VoIP signalling protocol from ITU-T. As one of the most +@@ -929,7 +928,6 @@ config NETFILTER_XT_TARGET_SECMARK + + config NETFILTER_XT_TARGET_TCPMSS + tristate '"TCPMSS" target support' +- depends on IPV6 || IPV6=n + default m if NETFILTER_ADVANCED=n + ---help--- + This option adds a `TCPMSS' target, which allows you to alter the diff --git a/target/linux/generic/patches-4.3/251-sound_kconfig.patch b/target/linux/generic/patches-4.3/251-sound_kconfig.patch new file mode 100644 index 0000000..4cb67ad --- /dev/null +++ b/target/linux/generic/patches-4.3/251-sound_kconfig.patch @@ -0,0 +1,18 @@ +--- a/sound/core/Kconfig ++++ b/sound/core/Kconfig +@@ -16,13 +16,13 @@ config SND_DMAENGINE_PCM + tristate + + config SND_HWDEP +- tristate ++ tristate "Sound hardware support" + + config SND_RAWMIDI + tristate + + config SND_COMPRESS_OFFLOAD +- tristate ++ tristate "Compression offloading support" + + # To be effective this also requires INPUT - users should say: + # select SND_JACK if INPUT=y || INPUT=SND diff --git a/target/linux/generic/patches-4.3/252-mv_cesa_depends.patch b/target/linux/generic/patches-4.3/252-mv_cesa_depends.patch new file mode 100644 index 0000000..f54f3c7 --- /dev/null +++ b/target/linux/generic/patches-4.3/252-mv_cesa_depends.patch @@ -0,0 +1,10 @@ +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -163,6 +163,7 @@ config CRYPTO_DEV_MV_CESA + tristate "Marvell's Cryptographic Engine" + depends on PLAT_ORION + select CRYPTO_AES ++ select CRYPTO_HASH2 + select CRYPTO_BLKCIPHER + select CRYPTO_HASH + select SRAM diff --git a/target/linux/generic/patches-4.3/253-ssb_b43_default_on.patch b/target/linux/generic/patches-4.3/253-ssb_b43_default_on.patch new file mode 100644 index 0000000..29d2a41 --- /dev/null +++ b/target/linux/generic/patches-4.3/253-ssb_b43_default_on.patch @@ -0,0 +1,29 @@ +--- a/drivers/ssb/Kconfig ++++ b/drivers/ssb/Kconfig +@@ -29,6 +29,7 @@ config SSB_SPROM + config SSB_BLOCKIO + bool + depends on SSB ++ default y + + config SSB_PCIHOST_POSSIBLE + bool +@@ -49,7 +50,7 @@ config SSB_PCIHOST + config SSB_B43_PCI_BRIDGE + bool + depends on SSB_PCIHOST +- default n ++ default y + + config SSB_PCMCIAHOST_POSSIBLE + bool +--- a/drivers/bcma/Kconfig ++++ b/drivers/bcma/Kconfig +@@ -17,6 +17,7 @@ config BCMA + config BCMA_BLOCKIO + bool + depends on BCMA ++ default y + + config BCMA_HOST_PCI_POSSIBLE + bool diff --git a/target/linux/generic/patches-4.3/254-textsearch_kconfig_hacks.patch b/target/linux/generic/patches-4.3/254-textsearch_kconfig_hacks.patch new file mode 100644 index 0000000..a75883e --- /dev/null +++ b/target/linux/generic/patches-4.3/254-textsearch_kconfig_hacks.patch @@ -0,0 +1,23 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -332,16 +332,16 @@ config BCH_CONST_T + # Textsearch support is select'ed if needed + # + config TEXTSEARCH +- bool ++ boolean "Textsearch support" + + config TEXTSEARCH_KMP +- tristate ++ tristate "Textsearch KMP" + + config TEXTSEARCH_BM +- tristate ++ tristate "Textsearch BM" + + config TEXTSEARCH_FSM +- tristate ++ tristate "Textsearch FSM" + + config BTREE + bool diff --git a/target/linux/generic/patches-4.3/255-lib80211_kconfig_hacks.patch b/target/linux/generic/patches-4.3/255-lib80211_kconfig_hacks.patch new file mode 100644 index 0000000..8064b02 --- /dev/null +++ b/target/linux/generic/patches-4.3/255-lib80211_kconfig_hacks.patch @@ -0,0 +1,31 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -191,7 +191,7 @@ config CFG80211_WEXT_EXPORT + wext compatibility symbols to be exported. + + config LIB80211 +- tristate ++ tristate "LIB80211" + default n + help + This options enables a library of common routines used +@@ -200,13 +200,16 @@ config LIB80211 + Drivers should select this themselves if needed. + + config LIB80211_CRYPT_WEP +- tristate ++ tristate "LIB80211_CRYPT_WEP" ++ select LIB80211 + + config LIB80211_CRYPT_CCMP +- tristate ++ tristate "LIB80211_CRYPT_CCMP" ++ select LIB80211 + + config LIB80211_CRYPT_TKIP +- tristate ++ tristate "LIB80211_CRYPT_TKIP" ++ select LIB80211 + + config LIB80211_DEBUG + bool "lib80211 debugging messages" diff --git a/target/linux/generic/patches-4.3/256-crypto_add_kconfig_prompts.patch b/target/linux/generic/patches-4.3/256-crypto_add_kconfig_prompts.patch new file mode 100644 index 0000000..fb5d5dc --- /dev/null +++ b/target/linux/generic/patches-4.3/256-crypto_add_kconfig_prompts.patch @@ -0,0 +1,47 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -32,7 +32,7 @@ config CRYPTO_FIPS + this is. + + config CRYPTO_ALGAPI +- tristate ++ tristate "ALGAPI" + select CRYPTO_ALGAPI2 + help + This option provides the API for cryptographic algorithms. +@@ -41,7 +41,7 @@ config CRYPTO_ALGAPI2 + tristate + + config CRYPTO_AEAD +- tristate ++ tristate "AEAD" + select CRYPTO_AEAD2 + select CRYPTO_ALGAPI + +@@ -52,7 +52,7 @@ config CRYPTO_AEAD2 + select CRYPTO_RNG2 + + config CRYPTO_BLKCIPHER +- tristate ++ tristate "BLKCIPHER" + select CRYPTO_BLKCIPHER2 + select CRYPTO_ALGAPI + +@@ -63,7 +63,7 @@ config CRYPTO_BLKCIPHER2 + select CRYPTO_WORKQUEUE + + config CRYPTO_HASH +- tristate ++ tristate "HASH" + select CRYPTO_HASH2 + select CRYPTO_ALGAPI + +@@ -72,7 +72,7 @@ config CRYPTO_HASH2 + select CRYPTO_ALGAPI2 + + config CRYPTO_RNG +- tristate ++ tristate "RNG" + select CRYPTO_RNG2 + select CRYPTO_ALGAPI + diff --git a/target/linux/generic/patches-4.3/257-wireless_ext_kconfig_hack.patch b/target/linux/generic/patches-4.3/257-wireless_ext_kconfig_hack.patch new file mode 100644 index 0000000..daac589 --- /dev/null +++ b/target/linux/generic/patches-4.3/257-wireless_ext_kconfig_hack.patch @@ -0,0 +1,22 @@ +--- a/net/wireless/Kconfig ++++ b/net/wireless/Kconfig +@@ -1,5 +1,5 @@ + config WIRELESS_EXT +- bool ++ bool "Wireless extensions" + + config WEXT_CORE + def_bool y +@@ -11,10 +11,10 @@ config WEXT_PROC + depends on WEXT_CORE + + config WEXT_SPY +- bool ++ bool "WEXT_SPY" + + config WEXT_PRIV +- bool ++ bool "WEXT_PRIV" + + config CFG80211 + tristate "cfg80211 - wireless configuration API" diff --git a/target/linux/generic/patches-4.3/258-netfilter_netlink_kconfig_hack.patch b/target/linux/generic/patches-4.3/258-netfilter_netlink_kconfig_hack.patch new file mode 100644 index 0000000..4206c9a --- /dev/null +++ b/target/linux/generic/patches-4.3/258-netfilter_netlink_kconfig_hack.patch @@ -0,0 +1,11 @@ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -10,7 +10,7 @@ config NETFILTER_INGRESS + infrastructure. + + config NETFILTER_NETLINK +- tristate ++ tristate "Netfilter NFNETLINK interface" + + config NETFILTER_NETLINK_ACCT + tristate "Netfilter NFACCT over NFNETLINK interface" diff --git a/target/linux/generic/patches-4.3/259-regmap_dynamic.patch b/target/linux/generic/patches-4.3/259-regmap_dynamic.patch new file mode 100644 index 0000000..3259197 --- /dev/null +++ b/target/linux/generic/patches-4.3/259-regmap_dynamic.patch @@ -0,0 +1,87 @@ +--- a/drivers/base/regmap/Kconfig ++++ b/drivers/base/regmap/Kconfig +@@ -3,29 +3,35 @@ + # subsystems should select the appropriate symbols. + + config REGMAP +- default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ) + select LZO_COMPRESS + select LZO_DECOMPRESS + select IRQ_DOMAIN if REGMAP_IRQ +- bool ++ tristate "Regmap" + + config REGMAP_AC97 ++ select REGMAP + tristate + + config REGMAP_I2C +- tristate ++ tristate "Regmap I2C" ++ select REGMAP + depends on I2C + + config REGMAP_SPI +- tristate ++ tristate "Regmap SPI" ++ select REGMAP ++ depends on SPI_MASTER + depends on SPI + + config REGMAP_SPMI ++ select REGMAP + tristate + depends on SPMI + + config REGMAP_MMIO +- tristate ++ tristate "Regmap MMIO" ++ select REGMAP + + config REGMAP_IRQ ++ select REGMAP + bool +--- a/include/linux/regmap.h ++++ b/include/linux/regmap.h +@@ -65,7 +65,7 @@ struct reg_sequence { + unsigned int delay_us; + }; + +-#ifdef CONFIG_REGMAP ++#if IS_ENABLED(CONFIG_REGMAP) + + enum regmap_endian { + /* Unspecified -> 0 -> Backwards compatible default */ +--- a/drivers/base/regmap/Makefile ++++ b/drivers/base/regmap/Makefile +@@ -1,9 +1,11 @@ + # For include/trace/define_trace.h to include trace.h + CFLAGS_regmap.o := -I$(src) + +-obj-$(CONFIG_REGMAP) += regmap.o regcache.o +-obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-lzo.o regcache-flat.o +-obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o ++regmap-core-objs = regmap.o regcache.o regcache-rbtree.o regcache-lzo.o regcache-flat.o ++ifdef CONFIG_DEBUG_FS ++regmap-core-objs += regmap-debugfs.o ++endif ++obj-$(CONFIG_REGMAP) += regmap-core.o + obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o + obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o + obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o +--- a/drivers/base/regmap/regmap.c ++++ b/drivers/base/regmap/regmap.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -2852,3 +2853,5 @@ static int __init regmap_initcall(void) + return 0; + } + postcore_initcall(regmap_initcall); ++ ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.3/260-crypto_test_dependencies.patch b/target/linux/generic/patches-4.3/260-crypto_test_dependencies.patch new file mode 100644 index 0000000..c5606a0 --- /dev/null +++ b/target/linux/generic/patches-4.3/260-crypto_test_dependencies.patch @@ -0,0 +1,38 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -119,11 +119,11 @@ config CRYPTO_MANAGER + + config CRYPTO_MANAGER2 + def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) +- select CRYPTO_AEAD2 +- select CRYPTO_HASH2 +- select CRYPTO_BLKCIPHER2 +- select CRYPTO_PCOMP2 +- select CRYPTO_AKCIPHER2 ++ select CRYPTO_AEAD2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_HASH2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_BLKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_PCOMP2 if !CRYPTO_MANAGER_DISABLE_TESTS ++ select CRYPTO_AKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS + + config CRYPTO_USER + tristate "Userspace cryptographic algorithm configuration" +--- a/crypto/algboss.c ++++ b/crypto/algboss.c +@@ -248,12 +248,16 @@ static int cryptomgr_schedule_test(struc + type = alg->cra_flags; + + /* This piece of crap needs to disappear into per-type test hooks. */ ++#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS ++ type |= CRYPTO_ALG_TESTED; ++#else + if (!((type ^ CRYPTO_ALG_TYPE_BLKCIPHER) & + CRYPTO_ALG_TYPE_BLKCIPHER_MASK) && !(type & CRYPTO_ALG_GENIV) && + ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == + CRYPTO_ALG_TYPE_BLKCIPHER ? alg->cra_blkcipher.ivsize : + alg->cra_ablkcipher.ivsize)) + type |= CRYPTO_ALG_TESTED; ++#endif + + param->type = type; + diff --git a/target/linux/generic/patches-4.3/262-compressor_kconfig_hack.patch b/target/linux/generic/patches-4.3/262-compressor_kconfig_hack.patch new file mode 100644 index 0000000..13a51cf --- /dev/null +++ b/target/linux/generic/patches-4.3/262-compressor_kconfig_hack.patch @@ -0,0 +1,36 @@ +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -216,26 +216,26 @@ config 842_DECOMPRESS + tristate + + config ZLIB_INFLATE +- tristate ++ tristate "ZLIB inflate support" + + config ZLIB_DEFLATE +- tristate ++ tristate "ZLIB deflate support" + select BITREVERSE + + config LZO_COMPRESS +- tristate ++ tristate "LZO compress support" + + config LZO_DECOMPRESS +- tristate ++ tristate "LZO decompress support" + + config LZ4_COMPRESS +- tristate ++ tristate "LZ4 compress support" + + config LZ4HC_COMPRESS +- tristate ++ tristate "LZ4HC compress support" + + config LZ4_DECOMPRESS +- tristate ++ tristate "LZ4 decompress support" + + source "lib/xz/Kconfig" + diff --git a/target/linux/generic/patches-4.3/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch b/target/linux/generic/patches-4.3/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch new file mode 100644 index 0000000..762f498 --- /dev/null +++ b/target/linux/generic/patches-4.3/270-uapi-kernel.h-glibc-specific-inclusion-of-sysinfo.h.patch @@ -0,0 +1,34 @@ +From 8b05e325824d3b38e52a7748b3b5dc34dc1c0f6d Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 14:37:54 +0200 +Subject: [PATCH 1/3] uapi/kernel.h: glibc specific inclusion of sysinfo.h + +including sysinfo.h from kernel.h makes no sense whatsoever, +but removing it breaks glibc's userspace header, +which includes kernel.h instead of sysinfo.h from their sys/sysinfo.h. +this seems to be a historical mistake. +on musl, including any header that uses kernel.h directly or indirectly +plus sys/sysinfo.h will produce a compile error due to redefinition of +struct sysinfo from sys/sysinfo.h. +so for now, only include it on glibc or when including from kernel +in order not to break their headers. + +Signed-off-by: John Spencer +Signed-off-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/kernel.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/include/uapi/linux/kernel.h ++++ b/include/uapi/linux/kernel.h +@@ -1,7 +1,9 @@ + #ifndef _UAPI_LINUX_KERNEL_H + #define _UAPI_LINUX_KERNEL_H + ++#if defined(__KERNEL__) || defined( __GLIBC__) + #include ++#endif + + /* + * 'kernel.h' contains some often-used function prototypes etc diff --git a/target/linux/generic/patches-4.3/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch b/target/linux/generic/patches-4.3/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch new file mode 100644 index 0000000..61d3873 --- /dev/null +++ b/target/linux/generic/patches-4.3/271-uapi-libc-compat.h-do-not-rely-on-__GLIBC__.patch @@ -0,0 +1,81 @@ +From f972afc2509eebcb00d370256c55b112a3b5ffca Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 16:50:40 +0200 +Subject: [PATCH 2/3] uapi/libc-compat.h: do not rely on __GLIBC__ + +Musl provides the same structs as glibc, but does not provide a define to +allow its detection. Since the absence of __GLIBC__ also can mean that it +is included from the kernel, change the __GLIBC__ detection to +!__KERNEL__, which should always be true when included from userspace. + +Signed-off-by: John Spencer +Tested-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/libc-compat.h | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -48,13 +48,13 @@ + #ifndef _UAPI_LIBC_COMPAT_H + #define _UAPI_LIBC_COMPAT_H + +-/* We have included glibc headers... */ +-#if defined(__GLIBC__) ++/* We have included libc headers... */ ++#if !defined(__KERNEL__) + +-/* Coordinate with glibc netinet/in.h header. */ ++/* Coordinate with libc netinet/in.h header. */ + #if defined(_NETINET_IN_H) + +-/* GLIBC headers included first so don't define anything ++/* LIBC headers included first so don't define anything + * that would already be defined. */ + #define __UAPI_DEF_IN_ADDR 0 + #define __UAPI_DEF_IN_IPPROTO 0 +@@ -68,7 +68,7 @@ + * if the glibc code didn't define them. This guard matches + * the guard in glibc/inet/netinet/in.h which defines the + * additional in6_addr macros e.g. s6_addr16, and s6_addr32. */ +-#if defined(__USE_MISC) || defined (__USE_GNU) ++#if !defined(__GLIBC__) || defined(__USE_MISC) || defined (__USE_GNU) + #define __UAPI_DEF_IN6_ADDR_ALT 0 + #else + #define __UAPI_DEF_IN6_ADDR_ALT 1 +@@ -83,7 +83,7 @@ + #else + + /* Linux headers included first, and we must define everything +- * we need. The expectation is that glibc will check the ++ * we need. The expectation is that the libc will check the + * __UAPI_DEF_* defines and adjust appropriately. */ + #define __UAPI_DEF_IN_ADDR 1 + #define __UAPI_DEF_IN_IPPROTO 1 +@@ -93,7 +93,7 @@ + #define __UAPI_DEF_IN_CLASS 1 + + #define __UAPI_DEF_IN6_ADDR 1 +-/* We unconditionally define the in6_addr macros and glibc must ++/* We unconditionally define the in6_addr macros and the libc must + * coordinate. */ + #define __UAPI_DEF_IN6_ADDR_ALT 1 + #define __UAPI_DEF_SOCKADDR_IN6 1 +@@ -115,7 +115,7 @@ + /* If we did not see any headers from any supported C libraries, + * or we are being included in the kernel, then define everything + * that we need. */ +-#else /* !defined(__GLIBC__) */ ++#else /* defined(__KERNEL__) */ + + /* Definitions for in.h */ + #define __UAPI_DEF_IN_ADDR 1 +@@ -138,6 +138,6 @@ + /* Definitions for xattr.h */ + #define __UAPI_DEF_XATTR 1 + +-#endif /* __GLIBC__ */ ++#endif /* __KERNEL__ */ + + #endif /* _UAPI_LIBC_COMPAT_H */ diff --git a/target/linux/generic/patches-4.3/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch b/target/linux/generic/patches-4.3/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch new file mode 100644 index 0000000..ff7677f --- /dev/null +++ b/target/linux/generic/patches-4.3/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch @@ -0,0 +1,67 @@ +From fcbb6fed85ea9ff4feb4f1ebd4f0f235fdaf06b6 Mon Sep 17 00:00:00 2001 +From: David Heidelberger +Date: Mon, 29 Jun 2015 16:53:03 +0200 +Subject: [PATCH 3/3] uapi/if_ether.h: prevent redefinition of struct ethhdr + +Musl provides its own ethhdr struct definition. Add a guard to prevent +its definition of the appropriate musl header has already been included. + +Signed-off-by: John Spencer +Tested-by: David Heidelberger +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/if_ether.h | 3 +++ + include/uapi/linux/libc-compat.h | 11 +++++++++++ + 2 files changed, 14 insertions(+) + +--- a/include/uapi/linux/if_ether.h ++++ b/include/uapi/linux/if_ether.h +@@ -22,6 +22,7 @@ + #define _UAPI_LINUX_IF_ETHER_H + + #include ++#include + + /* + * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble +@@ -135,11 +136,13 @@ + * This is an Ethernet frame header. + */ + ++#if __UAPI_DEF_ETHHDR + struct ethhdr { + unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ + unsigned char h_source[ETH_ALEN]; /* source ether addr */ + __be16 h_proto; /* packet type ID field */ + } __attribute__((packed)); ++#endif + + + #endif /* _UAPI_LINUX_IF_ETHER_H */ +--- a/include/uapi/linux/libc-compat.h ++++ b/include/uapi/linux/libc-compat.h +@@ -51,6 +51,14 @@ + /* We have included libc headers... */ + #if !defined(__KERNEL__) + ++/* musl defines the ethhdr struct itself in its netinet/if_ether.h. ++ * Glibc just includes the kernel header and uses a different guard. */ ++#if defined(_NETINET_IF_ETHER_H) ++#define __UAPI_DEF_ETHHDR 0 ++#else ++#define __UAPI_DEF_ETHHDR 1 ++#endif ++ + /* Coordinate with libc netinet/in.h header. */ + #if defined(_NETINET_IN_H) + +@@ -117,6 +125,9 @@ + * that we need. */ + #else /* defined(__KERNEL__) */ + ++/* Definitions for if_ether.h */ ++#define __UAPI_DEF_ETHHDR 1 ++ + /* Definitions for in.h */ + #define __UAPI_DEF_IN_ADDR 1 + #define __UAPI_DEF_IN_IPPROTO 1 diff --git a/target/linux/generic/patches-4.3/300-mips_expose_boot_raw.patch b/target/linux/generic/patches-4.3/300-mips_expose_boot_raw.patch new file mode 100644 index 0000000..99be91d --- /dev/null +++ b/target/linux/generic/patches-4.3/300-mips_expose_boot_raw.patch @@ -0,0 +1,39 @@ +From: Mark Miller + +This exposes the CONFIG_BOOT_RAW symbol in Kconfig. This is needed on +certain Broadcom chipsets running CFE in order to load the kernel. + +Signed-off-by: Mark Miller +Acked-by: Rob Landley +--- +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1003,9 +1003,6 @@ config FW_ARC + config ARCH_MAY_HAVE_PC_FDC + bool + +-config BOOT_RAW +- bool +- + config CEVT_BCM1480 + bool + +@@ -2733,6 +2730,18 @@ choice + if you don't intend to always append a DTB. + endchoice + ++config BOOT_RAW ++ bool "Enable the kernel to be executed from the load address" ++ default n ++ help ++ Allow the kernel to be executed from the load address for ++ bootloaders which cannot read the ELF format. This places ++ a jump to start_kernel at the load address. ++ ++ If unsure, say N. ++ ++ ++ + endmenu + + config LOCKDEP_SUPPORT diff --git a/target/linux/generic/patches-4.3/301-mips_image_cmdline_hack.patch b/target/linux/generic/patches-4.3/301-mips_image_cmdline_hack.patch new file mode 100644 index 0000000..44c646a --- /dev/null +++ b/target/linux/generic/patches-4.3/301-mips_image_cmdline_hack.patch @@ -0,0 +1,28 @@ +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1091,6 +1091,10 @@ config SYNC_R4K + config MIPS_MACHINE + def_bool n + ++config IMAGE_CMDLINE_HACK ++ bool "OpenWrt specific image command line hack" ++ default n ++ + config NO_IOPORT_MAP + def_bool n + +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -80,6 +80,12 @@ FEXPORT(__kernel_entry) + j kernel_entry + #endif + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++ .ascii "CMDLINE:" ++EXPORT(__image_cmdline) ++ .fill 0x400 ++#endif /* CONFIG_IMAGE_CMDLINE_HACK */ ++ + __REF + + NESTED(kernel_entry, 16, sp) # kernel entry point diff --git a/target/linux/generic/patches-4.3/302-mips_no_branch_likely.patch b/target/linux/generic/patches-4.3/302-mips_no_branch_likely.patch new file mode 100644 index 0000000..44c6b04 --- /dev/null +++ b/target/linux/generic/patches-4.3/302-mips_no_branch_likely.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -87,7 +87,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + # machines may also. Since BFD is incredibly buggy with respect to + # crossformat linking we rely on the elf2ecoff tool for format conversion. + # +-cflags-y += -G 0 -mno-abicalls -fno-pic -pipe ++cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely + cflags-y += -msoft-float + LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections + KBUILD_AFLAGS_MODULE += -mlong-calls diff --git a/target/linux/generic/patches-4.3/304-mips_disable_fpu.patch b/target/linux/generic/patches-4.3/304-mips_disable_fpu.patch new file mode 100644 index 0000000..cceb36f --- /dev/null +++ b/target/linux/generic/patches-4.3/304-mips_disable_fpu.patch @@ -0,0 +1,106 @@ +From: Manuel Lauss +Subject: [RFC PATCH v4 2/2] MIPS: make FPU emulator optional +Date: Mon, 7 Apr 2014 12:57:04 +0200 +Message-Id: <1396868224-252888-2-git-send-email-manuel.lauss@gmail.com> + +This small patch makes the MIPS FPU emulator optional. The kernel +kills float-users on systems without a hardware FPU by sending a SIGILL. + +Disabling the emulator shrinks vmlinux by about 54kBytes (32bit, +optimizing for size). + +Signed-off-by: Manuel Lauss +--- +v4: rediffed because of patch 1/2, should now work with micromips as well +v3: updated patch description with size savings. +v2: incorporated changes suggested by Jonas Gorski + force the fpu emulator on for micromips: relocating the parts + of the mmips code in the emulator to other areas would be a + much larger change; I went the cheap route instead with this. + + arch/mips/Kbuild | 2 +- + arch/mips/Kconfig | 14 ++++++++++++++ + arch/mips/include/asm/fpu.h | 5 +++-- + arch/mips/include/asm/fpu_emulator.h | 15 +++++++++++++++ + 4 files changed, 33 insertions(+), 3 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -2680,6 +2680,20 @@ config MIPS_O32_FP64_SUPPORT + + If unsure, say N. + ++config MIPS_FPU_EMULATOR ++ bool "MIPS FPU Emulator" ++ default y ++ help ++ This option lets you disable the built-in MIPS FPU (Coprocessor 1) ++ emulator, which handles floating-point instructions on processors ++ without a hardware FPU. It is generally a good idea to keep the ++ emulator built-in, unless you are perfectly sure you have a ++ complete soft-float environment. With the emulator disabled, all ++ users of float operations will be killed with an illegal instr- ++ uction exception. ++ ++ Say Y, please. ++ + config USE_OF + bool + select OF +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -285,7 +285,7 @@ OBJCOPYFLAGS += --remove-section=.regin + head-y := arch/mips/kernel/head.o + + libs-y += arch/mips/lib/ +-libs-y += arch/mips/math-emu/ ++libs-$(CONFIG_MIPS_FPU_EMULATOR) += arch/mips/math-emu/ + + # See arch/mips/Kbuild for content of core part of the kernel + core-y += arch/mips/ +--- a/arch/mips/include/asm/fpu.h ++++ b/arch/mips/include/asm/fpu.h +@@ -223,8 +223,10 @@ static inline int init_fpu(void) + /* Restore FRE */ + write_c0_config5(config5); + enable_fpu_hazard(); +- } else ++ } else if (IS_ENABLED(CONFIG_MIPS_FPU_EMULATOR)) + fpu_emulator_init_fpu(); ++ else ++ ret = SIGILL; + + return ret; + } +--- a/arch/mips/include/asm/fpu_emulator.h ++++ b/arch/mips/include/asm/fpu_emulator.h +@@ -30,6 +30,7 @@ + #include + #include + ++#ifdef CONFIG_MIPS_FPU_EMULATOR + #ifdef CONFIG_DEBUG_FS + + struct mips_fpu_emulator_stats { +@@ -66,6 +67,21 @@ extern int do_dsemulret(struct pt_regs * + extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, + struct mips_fpu_struct *ctx, int has_fpu, + void *__user *fault_addr); ++#else /* no CONFIG_MIPS_FPU_EMULATOR */ ++static inline int do_dsemulret(struct pt_regs *xcp) ++{ ++ return 0; /* 0 means error, should never get here anyway */ ++} ++ ++static inline int fpu_emulator_cop1Handler(struct pt_regs *xcp, ++ struct mips_fpu_struct *ctx, int has_fpu, ++ void *__user *fault_addr) ++{ ++ *fault_addr = NULL; ++ return SIGILL; /* we don't speak MIPS FPU */ ++} ++#endif /* CONFIG_MIPS_FPU_EMULATOR */ ++ + int process_fpemu_return(int sig, void __user *fault_addr, + unsigned long fcr31); + int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, diff --git a/target/linux/generic/patches-4.3/305-mips_module_reloc.patch b/target/linux/generic/patches-4.3/305-mips_module_reloc.patch new file mode 100644 index 0000000..8b3975f --- /dev/null +++ b/target/linux/generic/patches-4.3/305-mips_module_reloc.patch @@ -0,0 +1,352 @@ +--- a/arch/mips/Makefile ++++ b/arch/mips/Makefile +@@ -90,8 +90,13 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin + cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely + cflags-y += -msoft-float + LDFLAGS_vmlinux += -G 0 -static -n -nostdlib --gc-sections ++ifdef CONFIG_64BIT + KBUILD_AFLAGS_MODULE += -mlong-calls + KBUILD_CFLAGS_MODULE += -mlong-calls ++else ++KBUILD_AFLAGS_MODULE += -mno-long-calls ++KBUILD_CFLAGS_MODULE += -mno-long-calls ++endif + + ifndef CONFIG_FUNCTION_TRACER + KBUILD_CFLAGS_KERNEL += -ffunction-sections -fdata-sections +--- a/arch/mips/include/asm/module.h ++++ b/arch/mips/include/asm/module.h +@@ -11,6 +11,11 @@ struct mod_arch_specific { + const struct exception_table_entry *dbe_start; + const struct exception_table_entry *dbe_end; + struct mips_hi16 *r_mips_hi16_list; ++ ++ void *phys_plt_tbl; ++ void *virt_plt_tbl; ++ unsigned int phys_plt_offset; ++ unsigned int virt_plt_offset; + }; + + typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ +--- a/arch/mips/kernel/module.c ++++ b/arch/mips/kernel/module.c +@@ -43,14 +43,221 @@ struct mips_hi16 { + static LIST_HEAD(dbe_list); + static DEFINE_SPINLOCK(dbe_lock); + +-#ifdef MODULE_START ++/* ++ * Get the potential max trampolines size required of the init and ++ * non-init sections. Only used if we cannot find enough contiguous ++ * physically mapped memory to put the module into. ++ */ ++static unsigned int ++get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, ++ const char *secstrings, unsigned int symindex, bool is_init) ++{ ++ unsigned long ret = 0; ++ unsigned int i, j; ++ Elf_Sym *syms; ++ ++ /* Everything marked ALLOC (this includes the exported symbols) */ ++ for (i = 1; i < hdr->e_shnum; ++i) { ++ unsigned int info = sechdrs[i].sh_info; ++ ++ if (sechdrs[i].sh_type != SHT_REL ++ && sechdrs[i].sh_type != SHT_RELA) ++ continue; ++ ++ /* Not a valid relocation section? */ ++ if (info >= hdr->e_shnum) ++ continue; ++ ++ /* Don't bother with non-allocated sections */ ++ if (!(sechdrs[info].sh_flags & SHF_ALLOC)) ++ continue; ++ ++ /* If it's called *.init*, and we're not init, we're ++ not interested */ ++ if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0) ++ != is_init) ++ continue; ++ ++ syms = (Elf_Sym *) sechdrs[symindex].sh_addr; ++ if (sechdrs[i].sh_type == SHT_REL) { ++ Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr; ++ unsigned int size = sechdrs[i].sh_size / sizeof(*rel); ++ ++ for (j = 0; j < size; ++j) { ++ Elf_Sym *sym; ++ ++ if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26) ++ continue; ++ ++ sym = syms + ELF_MIPS_R_SYM(rel[j]); ++ if (!is_init && sym->st_shndx != SHN_UNDEF) ++ continue; ++ ++ ret += 4 * sizeof(int); ++ } ++ } else { ++ Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr; ++ unsigned int size = sechdrs[i].sh_size / sizeof(*rela); ++ ++ for (j = 0; j < size; ++j) { ++ Elf_Sym *sym; ++ ++ if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26) ++ continue; ++ ++ sym = syms + ELF_MIPS_R_SYM(rela[j]); ++ if (!is_init && sym->st_shndx != SHN_UNDEF) ++ continue; ++ ++ ret += 4 * sizeof(int); ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++#ifndef MODULE_START ++static void *alloc_phys(unsigned long size) ++{ ++ unsigned order; ++ struct page *page; ++ struct page *p; ++ ++ size = PAGE_ALIGN(size); ++ order = get_order(size); ++ ++ page = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN | ++ __GFP_THISNODE, order); ++ if (!page) ++ return NULL; ++ ++ split_page(page, order); ++ ++ /* mark all pages except for the last one */ ++ for (p = page; p + 1 < page + (size >> PAGE_SHIFT); ++p) ++ set_bit(PG_owner_priv_1, &p->flags); ++ ++ for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p) ++ __free_page(p); ++ ++ return page_address(page); ++} ++#endif ++ ++static void free_phys(void *ptr) ++{ ++ struct page *page; ++ bool free; ++ ++ page = virt_to_page(ptr); ++ do { ++ free = test_and_clear_bit(PG_owner_priv_1, &page->flags); ++ __free_page(page); ++ page++; ++ } while (free); ++} ++ ++ + void *module_alloc(unsigned long size) + { ++#ifdef MODULE_START + return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, + GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, + __builtin_return_address(0)); ++#else ++ void *ptr; ++ ++ if (size == 0) ++ return NULL; ++ ++ ptr = alloc_phys(size); ++ ++ /* If we failed to allocate physically contiguous memory, ++ * fall back to regular vmalloc. The module loader code will ++ * create jump tables to handle long jumps */ ++ if (!ptr) ++ return vmalloc(size); ++ ++ return ptr; ++#endif + } ++ ++static inline bool is_phys_addr(void *ptr) ++{ ++#ifdef CONFIG_64BIT ++ return (KSEGX((unsigned long)ptr) == CKSEG0); ++#else ++ return (KSEGX(ptr) == KSEG0); + #endif ++} ++ ++/* Free memory returned from module_alloc */ ++void module_memfree(void *module_region) ++{ ++ if (is_phys_addr(module_region)) ++ free_phys(module_region); ++ else ++ vfree(module_region); ++} ++ ++static void *__module_alloc(int size, bool phys) ++{ ++ void *ptr; ++ ++ if (phys) ++ ptr = kmalloc(size, GFP_KERNEL); ++ else ++ ptr = vmalloc(size); ++ return ptr; ++} ++ ++static void __module_free(void *ptr) ++{ ++ if (is_phys_addr(ptr)) ++ kfree(ptr); ++ else ++ vfree(ptr); ++} ++ ++int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, ++ char *secstrings, struct module *mod) ++{ ++ unsigned int symindex = 0; ++ unsigned int core_size, init_size; ++ int i; ++ ++ mod->arch.phys_plt_offset = 0; ++ mod->arch.virt_plt_offset = 0; ++ mod->arch.phys_plt_tbl = NULL; ++ mod->arch.virt_plt_tbl = NULL; ++ ++ if (IS_ENABLED(CONFIG_64BIT)) ++ return 0; ++ ++ for (i = 1; i < hdr->e_shnum; i++) ++ if (sechdrs[i].sh_type == SHT_SYMTAB) ++ symindex = i; ++ ++ core_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false); ++ init_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true); ++ ++ if ((core_size + init_size) == 0) ++ return 0; ++ ++ mod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1); ++ if (!mod->arch.phys_plt_tbl) ++ return -ENOMEM; ++ ++ mod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0); ++ if (!mod->arch.virt_plt_tbl) { ++ __module_free(mod->arch.phys_plt_tbl); ++ mod->arch.phys_plt_tbl = NULL; ++ return -ENOMEM; ++ } ++ ++ return 0; ++} + + int apply_r_mips_none(struct module *me, u32 *location, Elf_Addr v) + { +@@ -64,8 +271,39 @@ static int apply_r_mips_32_rel(struct mo + return 0; + } + ++static Elf_Addr add_plt_entry_to(unsigned *plt_offset, ++ void *start, Elf_Addr v) ++{ ++ unsigned *tramp = start + *plt_offset; ++ *plt_offset += 4 * sizeof(int); ++ ++ /* adjust carry for addiu */ ++ if (v & 0x00008000) ++ v += 0x10000; ++ ++ tramp[0] = 0x3c190000 | (v >> 16); /* lui t9, hi16 */ ++ tramp[1] = 0x27390000 | (v & 0xffff); /* addiu t9, t9, lo16 */ ++ tramp[2] = 0x03200008; /* jr t9 */ ++ tramp[3] = 0x00000000; /* nop */ ++ ++ return (Elf_Addr) tramp; ++} ++ ++static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v) ++{ ++ if (is_phys_addr(location)) ++ return add_plt_entry_to(&me->arch.phys_plt_offset, ++ me->arch.phys_plt_tbl, v); ++ else ++ return add_plt_entry_to(&me->arch.virt_plt_offset, ++ me->arch.virt_plt_tbl, v); ++ ++} ++ + static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v) + { ++ u32 ofs = *location & 0x03ffffff; ++ + if (v % 4) { + pr_err("module %s: dangerous R_MIPS_26 REL relocation\n", + me->name); +@@ -73,14 +311,17 @@ static int apply_r_mips_26_rel(struct mo + } + + if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { +- printk(KERN_ERR +- "module %s: relocation overflow\n", +- me->name); +- return -ENOEXEC; ++ v = add_plt_entry(me, location, v + (ofs << 2)); ++ if (!v) { ++ printk(KERN_ERR ++ "module %s: relocation overflow\n", me->name); ++ return -ENOEXEC; ++ } ++ ofs = 0; + } + + *location = (*location & ~0x03ffffff) | +- ((*location + (v >> 2)) & 0x03ffffff); ++ ((ofs + (v >> 2)) & 0x03ffffff); + + return 0; + } +@@ -287,9 +528,33 @@ int module_finalize(const Elf_Ehdr *hdr, + list_add(&me->arch.dbe_list, &dbe_list); + spin_unlock_irq(&dbe_lock); + } ++ ++ /* Get rid of the fixup trampoline if we're running the module ++ * from physically mapped address space */ ++ if (me->arch.phys_plt_offset == 0) { ++ __module_free(me->arch.phys_plt_tbl); ++ me->arch.phys_plt_tbl = NULL; ++ } ++ if (me->arch.virt_plt_offset == 0) { ++ __module_free(me->arch.virt_plt_tbl); ++ me->arch.virt_plt_tbl = NULL; ++ } ++ + return 0; + } + ++void module_arch_freeing_init(struct module *mod) ++{ ++ if (mod->arch.phys_plt_tbl) { ++ __module_free(mod->arch.phys_plt_tbl); ++ mod->arch.phys_plt_tbl = NULL; ++ } ++ if (mod->arch.virt_plt_tbl) { ++ __module_free(mod->arch.virt_plt_tbl); ++ mod->arch.virt_plt_tbl = NULL; ++ } ++} ++ + void module_arch_cleanup(struct module *mod) + { + spin_lock_irq(&dbe_lock); diff --git a/target/linux/generic/patches-4.3/306-mips_mem_functions_performance.patch b/target/linux/generic/patches-4.3/306-mips_mem_functions_performance.patch new file mode 100644 index 0000000..9818677 --- /dev/null +++ b/target/linux/generic/patches-4.3/306-mips_mem_functions_performance.patch @@ -0,0 +1,83 @@ +--- a/arch/mips/include/asm/string.h ++++ b/arch/mips/include/asm/string.h +@@ -133,11 +133,44 @@ strncmp(__const__ char *__cs, __const__ + + #define __HAVE_ARCH_MEMSET + extern void *memset(void *__s, int __c, size_t __count); ++#define memset(__s, __c, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memset((__s), (__c), __len); \ ++ else \ ++ __ret = __builtin_memset((__s), (__c), __len); \ ++ __ret; \ ++}) + + #define __HAVE_ARCH_MEMCPY + extern void *memcpy(void *__to, __const__ void *__from, size_t __n); ++#define memcpy(dst, src, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memcpy((dst), (src), __len); \ ++ else \ ++ __ret = __builtin_memcpy((dst), (src), __len); \ ++ __ret; \ ++}) + + #define __HAVE_ARCH_MEMMOVE + extern void *memmove(void *__dest, __const__ void *__src, size_t __n); ++#define memmove(dst, src, len) \ ++({ \ ++ size_t __len = (len); \ ++ void *__ret; \ ++ if (__builtin_constant_p(len) && __len >= 64) \ ++ __ret = memmove((dst), (src), __len); \ ++ else \ ++ __ret = __builtin_memmove((dst), (src), __len); \ ++ __ret; \ ++}) ++ ++#define __HAVE_ARCH_MEMCMP ++#define memcmp(src1, src2, len) __builtin_memcmp((src1), (src2), (len)) + + #endif /* _ASM_STRING_H */ +--- a/arch/mips/lib/Makefile ++++ b/arch/mips/lib/Makefile +@@ -4,7 +4,7 @@ + + lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \ + mips-atomic.o strlen_user.o strncpy_user.o \ +- strnlen_user.o uncached.o ++ strnlen_user.o uncached.o memcmp.o + + obj-y += iomap.o + obj-$(CONFIG_PCI) += iomap-pci.o +--- /dev/null ++++ b/arch/mips/lib/memcmp.c +@@ -0,0 +1,22 @@ ++/* ++ * copied from linux/lib/string.c ++ * ++ * Copyright (C) 1991, 1992 Linus Torvalds ++ */ ++ ++#include ++#include ++ ++#undef memcmp ++int memcmp(const void *cs, const void *ct, size_t count) ++{ ++ const unsigned char *su1, *su2; ++ int res = 0; ++ ++ for (su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) ++ if ((res = *su1 - *su2) != 0) ++ break; ++ return res; ++} ++EXPORT_SYMBOL(memcmp); ++ diff --git a/target/linux/generic/patches-4.3/307-mips_highmem_offset.patch b/target/linux/generic/patches-4.3/307-mips_highmem_offset.patch new file mode 100644 index 0000000..c9f0c84 --- /dev/null +++ b/target/linux/generic/patches-4.3/307-mips_highmem_offset.patch @@ -0,0 +1,17 @@ +Adjust highmem offset to 0x10000000 to ensure that all kmalloc allocations +stay within the same 256M boundary. This ensures that -mlong-calls is not +needed on systems with more than 256M RAM. + +Signed-off-by: Felix Fietkau +--- +--- a/arch/mips/include/asm/mach-generic/spaces.h ++++ b/arch/mips/include/asm/mach-generic/spaces.h +@@ -44,7 +44,7 @@ + * Memory above this physical address will be considered highmem. + */ + #ifndef HIGHMEM_START +-#define HIGHMEM_START _AC(0x20000000, UL) ++#define HIGHMEM_START _AC(0x10000000, UL) + #endif + + #endif /* CONFIG_32BIT */ diff --git a/target/linux/generic/patches-4.3/309-mips_fuse_workaround.patch b/target/linux/generic/patches-4.3/309-mips_fuse_workaround.patch new file mode 100644 index 0000000..811dd6b --- /dev/null +++ b/target/linux/generic/patches-4.3/309-mips_fuse_workaround.patch @@ -0,0 +1,32 @@ +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -38,6 +38,7 @@ void (*__flush_cache_vunmap)(void); + + void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size); + EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); ++EXPORT_SYMBOL(__flush_cache_all); + void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size); + + /* MIPS specific cache operations */ +--- a/fs/fuse/dev.c ++++ b/fs/fuse/dev.c +@@ -19,6 +19,9 @@ + #include + #include + #include ++#ifdef CONFIG_MIPS ++#include ++#endif + + MODULE_ALIAS_MISCDEV(FUSE_MINOR); + MODULE_ALIAS("devname:fuse"); +@@ -802,6 +805,9 @@ static int fuse_copy_fill(struct fuse_co + static int fuse_copy_do(struct fuse_copy_state *cs, void **val, unsigned *size) + { + unsigned ncpy = min(*size, cs->len); ++#ifdef CONFIG_MIPS ++ __flush_cache_all(); ++#endif + if (val) { + void *pgaddr = kmap_atomic(cs->pg); + void *buf = pgaddr + cs->offset; diff --git a/target/linux/generic/patches-4.3/310-arm_module_unresolved_weak_sym.patch b/target/linux/generic/patches-4.3/310-arm_module_unresolved_weak_sym.patch new file mode 100644 index 0000000..327a475 --- /dev/null +++ b/target/linux/generic/patches-4.3/310-arm_module_unresolved_weak_sym.patch @@ -0,0 +1,13 @@ +--- a/arch/arm/kernel/module.c ++++ b/arch/arm/kernel/module.c +@@ -88,6 +88,10 @@ apply_relocate(Elf32_Shdr *sechdrs, cons + return -ENOEXEC; + } + ++ if ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) && ++ ELF_ST_BIND(sym->st_info) == STB_WEAK) ++ continue; ++ + loc = dstsec->sh_addr + rel->r_offset; + + switch (ELF32_R_TYPE(rel->r_info)) { diff --git a/target/linux/generic/patches-4.3/320-ppc4xx_optimization.patch b/target/linux/generic/patches-4.3/320-ppc4xx_optimization.patch new file mode 100644 index 0000000..c43d800 --- /dev/null +++ b/target/linux/generic/patches-4.3/320-ppc4xx_optimization.patch @@ -0,0 +1,31 @@ +Upstream doesn't optimize the kernel and bootwrappers for ppc44x because +they still want to support gcc 3.3 -- well, we don't. + +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -207,7 +207,8 @@ ifeq ($(CONFIG_FUNCTION_TRACER),y) + KBUILD_CFLAGS += -mno-sched-epilog + endif + +-cpu-as-$(CONFIG_4xx) += -Wa,-m405 ++cpu-as-$(CONFIG_40x) += -Wa,-m405 ++cpu-as-$(CONFIG_44x) += -Wa,-m440 + cpu-as-$(CONFIG_ALTIVEC) += -Wa,-maltivec + cpu-as-$(CONFIG_E200) += -Wa,-me200 + +--- a/arch/powerpc/boot/Makefile ++++ b/arch/powerpc/boot/Makefile +@@ -48,10 +48,10 @@ BOOTCFLAGS += -I$(obj) -I$(srctree)/$(ob + DTC_FLAGS ?= -p 1024 + + $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/ebony.o: BOOTCFLAGS += -mcpu=405 ++$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440 + $(obj)/cuboot-hotfoot.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405 +-$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405 ++$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=440 ++$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440 + $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 + $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 + $(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405 diff --git a/target/linux/generic/patches-4.3/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/patches-4.3/321-powerpc_crtsavres_prereq.patch new file mode 100644 index 0000000..987e000 --- /dev/null +++ b/target/linux/generic/patches-4.3/321-powerpc_crtsavres_prereq.patch @@ -0,0 +1,10 @@ +--- a/arch/powerpc/Makefile ++++ b/arch/powerpc/Makefile +@@ -169,7 +169,6 @@ CPP = $(CC) -E $(KBUILD_CFLAGS) + + CHECKFLAGS += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__ + +-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o + + ifeq ($(CONFIG_476FPE_ERR46),y) + KBUILD_LDFLAGS_MODULE += --ppc476-workaround \ diff --git a/target/linux/generic/patches-4.3/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch b/target/linux/generic/patches-4.3/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch new file mode 100644 index 0000000..a69d197 --- /dev/null +++ b/target/linux/generic/patches-4.3/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch @@ -0,0 +1,298 @@ +From d8582dcf1ed66eee88a11e4760f42c0d6c8822be Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 31 Jan 2015 22:26:03 +0800 +Subject: [PATCH 331/331] MIPS: kexec: Accept command line parameters from + userspace. + +Signed-off-by: Yousong Zhou +--- + arch/mips/kernel/machine_kexec.c | 153 +++++++++++++++++++++++++++++++----- + arch/mips/kernel/machine_kexec.h | 20 +++++ + arch/mips/kernel/relocate_kernel.S | 21 +++-- + 3 files changed, 167 insertions(+), 27 deletions(-) + create mode 100644 arch/mips/kernel/machine_kexec.h + +--- a/arch/mips/kernel/machine_kexec.c ++++ b/arch/mips/kernel/machine_kexec.c +@@ -10,45 +10,145 @@ + #include + #include + ++#include + #include + #include +- +-extern const unsigned char relocate_new_kernel[]; +-extern const size_t relocate_new_kernel_size; +- +-extern unsigned long kexec_start_address; +-extern unsigned long kexec_indirection_page; ++#include ++#include "machine_kexec.h" + + int (*_machine_kexec_prepare)(struct kimage *) = NULL; + void (*_machine_kexec_shutdown)(void) = NULL; + void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL; ++ + #ifdef CONFIG_SMP + void (*relocated_kexec_smp_wait) (void *); + atomic_t kexec_ready_to_reboot = ATOMIC_INIT(0); + #endif + +-int +-machine_kexec_prepare(struct kimage *kimage) ++static void machine_kexec_print_args(void) + { ++ unsigned long argc = (int)kexec_args[0]; ++ int i; ++ ++ pr_info("kexec_args[0] (argc): %lu\n", argc); ++ pr_info("kexec_args[1] (argv): %p\n", (void *)kexec_args[1]); ++ pr_info("kexec_args[2] (env ): %p\n", (void *)kexec_args[2]); ++ pr_info("kexec_args[3] (desc): %p\n", (void *)kexec_args[3]); ++ ++ for (i = 0; i < argc; i++) { ++ pr_info("kexec_argv[%d] = %p, %s\n", ++ i, kexec_argv[i], kexec_argv[i]); ++ } ++} ++ ++static void machine_kexec_init_argv(struct kimage *image) ++{ ++ void __user *buf = NULL; ++ size_t bufsz; ++ size_t size; ++ int i; ++ ++ bufsz = 0; ++ for (i = 0; i < image->nr_segments; i++) { ++ struct kexec_segment *seg; ++ ++ seg = &image->segment[i]; ++ if (seg->bufsz < 6) ++ continue; ++ ++ if (strncmp((char *) seg->buf, "kexec ", 6)) ++ continue; ++ ++ buf = seg->buf; ++ bufsz = seg->bufsz; ++ break; ++ } ++ ++ if (!buf) ++ return; ++ ++ size = KEXEC_COMMAND_LINE_SIZE; ++ size = min(size, bufsz); ++ if (size < bufsz) ++ pr_warn("kexec command line truncated to %zd bytes\n", size); ++ ++ /* Copy to kernel space */ ++ copy_from_user(kexec_argv_buf, buf, size); ++ kexec_argv_buf[size - 1] = 0; ++} ++ ++static void machine_kexec_parse_argv(struct kimage *image) ++{ ++ char *reboot_code_buffer; ++ int reloc_delta; ++ char *ptr; ++ int argc; ++ int i; ++ ++ ptr = kexec_argv_buf; ++ argc = 0; ++ ++ /* ++ * convert command line string to array of parameters ++ * (as bootloader does). ++ */ ++ while (ptr && *ptr && (KEXEC_MAX_ARGC > argc)) { ++ if (*ptr == ' ') { ++ *ptr++ = '\0'; ++ continue; ++ } ++ ++ kexec_argv[argc++] = ptr; ++ ptr = strchr(ptr, ' '); ++ } ++ ++ if (!argc) ++ return; ++ ++ kexec_args[0] = argc; ++ kexec_args[1] = (unsigned long)kexec_argv; ++ kexec_args[2] = 0; ++ kexec_args[3] = 0; ++ ++ reboot_code_buffer = page_address(image->control_code_page); ++ reloc_delta = reboot_code_buffer - (char *)kexec_relocate_new_kernel; ++ ++ kexec_args[1] += reloc_delta; ++ for (i = 0; i < argc; i++) ++ kexec_argv[i] += reloc_delta; ++} ++ ++int machine_kexec_prepare(struct kimage *kimage) ++{ ++ /* ++ * Whenever arguments passed from kexec-tools, Init the arguments as ++ * the original ones to try avoiding booting failure. ++ */ ++ ++ kexec_args[0] = fw_arg0; ++ kexec_args[1] = fw_arg1; ++ kexec_args[2] = fw_arg2; ++ kexec_args[3] = fw_arg3; ++ ++ machine_kexec_init_argv(kimage); ++ machine_kexec_parse_argv(kimage); ++ + if (_machine_kexec_prepare) + return _machine_kexec_prepare(kimage); + return 0; + } + +-void +-machine_kexec_cleanup(struct kimage *kimage) ++void machine_kexec_cleanup(struct kimage *kimage) + { + } + +-void +-machine_shutdown(void) ++void machine_shutdown(void) + { + if (_machine_kexec_shutdown) + _machine_kexec_shutdown(); + } + +-void +-machine_crash_shutdown(struct pt_regs *regs) ++void machine_crash_shutdown(struct pt_regs *regs) + { + if (_machine_crash_shutdown) + _machine_crash_shutdown(regs); +@@ -66,10 +166,12 @@ machine_kexec(struct kimage *image) + unsigned long *ptr; + + reboot_code_buffer = +- (unsigned long)page_address(image->control_code_page); ++ (unsigned long)page_address(image->control_code_page); ++ pr_info("reboot_code_buffer = %p\n", (void *)reboot_code_buffer); + + kexec_start_address = + (unsigned long) phys_to_virt(image->start); ++ pr_info("kexec_start_address = %p\n", (void *)kexec_start_address); + + if (image->type == KEXEC_TYPE_DEFAULT) { + kexec_indirection_page = +@@ -77,9 +179,19 @@ machine_kexec(struct kimage *image) + } else { + kexec_indirection_page = (unsigned long)&image->head; + } ++ pr_info("kexec_indirection_page = %p\n", (void *)kexec_indirection_page); + +- memcpy((void*)reboot_code_buffer, relocate_new_kernel, +- relocate_new_kernel_size); ++ pr_info("Where is memcpy: %p\n", memcpy); ++ pr_info("kexec_relocate_new_kernel = %p, kexec_relocate_new_kernel_end = %p\n", ++ (void *)kexec_relocate_new_kernel, &kexec_relocate_new_kernel_end); ++ pr_info("Copy %lu bytes from %p to %p\n", KEXEC_RELOCATE_NEW_KERNEL_SIZE, ++ (void *)kexec_relocate_new_kernel, (void *)reboot_code_buffer); ++ memcpy((void*)reboot_code_buffer, kexec_relocate_new_kernel, ++ KEXEC_RELOCATE_NEW_KERNEL_SIZE); ++ ++ pr_info("Before _print_args().\n"); ++ machine_kexec_print_args(); ++ pr_info("Before eval loop.\n"); + + /* + * The generic kexec code builds a page list with physical +@@ -98,15 +210,16 @@ machine_kexec(struct kimage *image) + /* + * we do not want to be bothered. + */ ++ pr_info("Before irq_disable.\n"); + local_irq_disable(); + +- printk("Will call new kernel at %08lx\n", image->start); +- printk("Bye ...\n"); ++ pr_info("Will call new kernel at %08lx\n", image->start); ++ pr_info("Bye ...\n"); + __flush_cache_all(); + #ifdef CONFIG_SMP + /* All secondary cpus now may jump to kexec_wait cycle */ + relocated_kexec_smp_wait = reboot_code_buffer + +- (void *)(kexec_smp_wait - relocate_new_kernel); ++ (void *)(kexec_smp_wait - kexec_relocate_new_kernel); + smp_wmb(); + atomic_set(&kexec_ready_to_reboot, 1); + #endif +--- /dev/null ++++ b/arch/mips/kernel/machine_kexec.h +@@ -0,0 +1,20 @@ ++#ifndef _MACHINE_KEXEC_H ++#define _MACHINE_KEXEC_H ++ ++#ifndef __ASSEMBLY__ ++extern const unsigned char kexec_relocate_new_kernel[]; ++extern unsigned long kexec_relocate_new_kernel_end; ++extern unsigned long kexec_start_address; ++extern unsigned long kexec_indirection_page; ++ ++extern char kexec_argv_buf[]; ++extern char *kexec_argv[]; ++ ++#define KEXEC_RELOCATE_NEW_KERNEL_SIZE ((unsigned long)&kexec_relocate_new_kernel_end - (unsigned long)kexec_relocate_new_kernel) ++#endif /* !__ASSEMBLY__ */ ++ ++#define KEXEC_COMMAND_LINE_SIZE 256 ++#define KEXEC_ARGV_SIZE (KEXEC_COMMAND_LINE_SIZE / 16) ++#define KEXEC_MAX_ARGC (KEXEC_ARGV_SIZE / sizeof(long)) ++ ++#endif +--- a/arch/mips/kernel/relocate_kernel.S ++++ b/arch/mips/kernel/relocate_kernel.S +@@ -12,8 +12,9 @@ + #include + #include + #include ++#include "machine_kexec.h" + +-LEAF(relocate_new_kernel) ++LEAF(kexec_relocate_new_kernel) + PTR_L a0, arg0 + PTR_L a1, arg1 + PTR_L a2, arg2 +@@ -98,7 +99,7 @@ done: + #endif + /* jump to kexec_start_address */ + j s1 +- END(relocate_new_kernel) ++ END(kexec_relocate_new_kernel) + + #ifdef CONFIG_SMP + /* +@@ -184,9 +185,15 @@ kexec_indirection_page: + PTR 0 + .size kexec_indirection_page, PTRSIZE + +-relocate_new_kernel_end: ++kexec_argv_buf: ++ EXPORT(kexec_argv_buf) ++ .skip KEXEC_COMMAND_LINE_SIZE ++ .size kexec_argv_buf, KEXEC_COMMAND_LINE_SIZE ++ ++kexec_argv: ++ EXPORT(kexec_argv) ++ .skip KEXEC_ARGV_SIZE ++ .size kexec_argv, KEXEC_ARGV_SIZE + +-relocate_new_kernel_size: +- EXPORT(relocate_new_kernel_size) +- PTR relocate_new_kernel_end - relocate_new_kernel +- .size relocate_new_kernel_size, PTRSIZE ++kexec_relocate_new_kernel_end: ++ EXPORT(kexec_relocate_new_kernel_end) diff --git a/target/linux/generic/patches-4.3/400-mtd-add-rootfs-split-support.patch b/target/linux/generic/patches-4.3/400-mtd-add-rootfs-split-support.patch new file mode 100644 index 0000000..ba64e09 --- /dev/null +++ b/target/linux/generic/patches-4.3/400-mtd-add-rootfs-split-support.patch @@ -0,0 +1,146 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -12,6 +12,23 @@ menuconfig MTD + + if MTD + ++menu "OpenWrt specific MTD options" ++ ++config MTD_ROOTFS_ROOT_DEV ++ bool "Automatically set 'rootfs' partition to be root filesystem" ++ default y ++ ++config MTD_SPLIT_FIRMWARE ++ bool "Automatically split firmware partition for kernel+rootfs" ++ default y ++ ++config MTD_SPLIT_FIRMWARE_NAME ++ string "Firmware partition name" ++ depends on MTD_SPLIT_FIRMWARE ++ default "firmware" ++ ++endmenu ++ + config MTD_TESTS + tristate "MTD tests support (DANGEROUS)" + depends on m +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -29,11 +29,13 @@ + #include + #include + #include ++#include + #include + #include + #include + + #include "mtdcore.h" ++#include "mtdsplit/mtdsplit.h" + + /* Our partition linked list */ + static LIST_HEAD(mtd_partitions); +@@ -47,13 +49,14 @@ struct mtd_part { + struct list_head list; + }; + ++static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part); ++ + /* + * Given a pointer to the MTD object in the mtd_part structure, we can retrieve + * the pointer to that structure with this macro. + */ + #define PART(x) ((struct mtd_part *)(x)) + +- + /* + * MTD methods which simply translate the effective address and pass through + * to the _real_ device. +@@ -579,8 +582,10 @@ static int mtd_add_partition_attrs(struc + return ret; + } + +-int mtd_add_partition(struct mtd_info *master, const char *name, +- long long offset, long long length) ++ ++static int ++__mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length, bool dup_check) + { + struct mtd_partition part; + struct mtd_part *new; +@@ -612,6 +617,7 @@ int mtd_add_partition(struct mtd_info *m + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&new->mtd); ++ mtd_partition_split(master, new); + + mtd_add_partition_attrs(new); + +@@ -619,6 +625,12 @@ int mtd_add_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_add_partition); + ++int mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length) ++{ ++ return __mtd_add_partition(master, name, offset, length, true); ++} ++ + int mtd_del_partition(struct mtd_info *master, int partno) + { + struct mtd_part *slave, *next; +@@ -644,6 +656,35 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME ++#define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME ++#else ++#define SPLIT_FIRMWARE_NAME "unused" ++#endif ++ ++static void split_firmware(struct mtd_info *master, struct mtd_part *part) ++{ ++} ++ ++void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++} ++ ++static void mtd_partition_split(struct mtd_info *master, struct mtd_part *part) ++{ ++ static int rootfs_found = 0; ++ ++ if (rootfs_found) ++ return; ++ ++ if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && ++ config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) ++ split_firmware(master, part); ++ ++ arch_split_mtd_part(master, part->mtd.name, part->offset, ++ part->mtd.size); ++} + /* + * This function, given a master MTD object and a partition table, creates + * and registers slave MTD objects which are bound to the master according to +@@ -673,6 +714,7 @@ int add_mtd_partitions(struct mtd_info * + mutex_unlock(&mtd_partitions_mutex); + + add_mtd_device(&slave->mtd); ++ mtd_partition_split(master, slave); + mtd_add_partition_attrs(slave); + + cur_offset = slave->offset + slave->mtd.size; +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -84,5 +84,7 @@ int mtd_add_partition(struct mtd_info *m + long long offset, long long length); + int mtd_del_partition(struct mtd_info *master, int partno); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); ++extern void __weak arch_split_mtd_part(struct mtd_info *master, ++ const char *name, int offset, int size); + + #endif diff --git a/target/linux/generic/patches-4.3/401-mtd-add-support-for-different-partition-parser-types.patch b/target/linux/generic/patches-4.3/401-mtd-add-support-for-different-partition-parser-types.patch new file mode 100644 index 0000000..ed09c2d --- /dev/null +++ b/target/linux/generic/patches-4.3/401-mtd-add-support-for-different-partition-parser-types.patch @@ -0,0 +1,113 @@ +From 02cff0ccaa6d364f5c1eeea83f47ac80ccc967d4 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 3 Sep 2013 18:11:50 +0200 +Subject: [PATCH] mtd: add support for different partition parser types + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/mtdpart.c | 56 ++++++++++++++++++++++++++++++++++++++++ + include/linux/mtd/partitions.h | 11 ++++++++ + 2 files changed, 67 insertions(+) + +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -745,6 +745,30 @@ static struct mtd_part_parser *get_parti + + #define put_partition_parser(p) do { module_put((p)->owner); } while (0) + ++static struct mtd_part_parser * ++get_partition_parser_by_type(enum mtd_parser_type type, ++ struct mtd_part_parser *start) ++{ ++ struct mtd_part_parser *p, *ret = NULL; ++ ++ spin_lock(&part_parser_lock); ++ ++ p = list_prepare_entry(start, &part_parsers, list); ++ if (start) ++ put_partition_parser(start); ++ ++ list_for_each_entry_continue(p, &part_parsers, list) { ++ if (p->type == type && try_module_get(p->owner)) { ++ ret = p; ++ break; ++ } ++ } ++ ++ spin_unlock(&part_parser_lock); ++ ++ return ret; ++} ++ + void register_mtd_parser(struct mtd_part_parser *p) + { + spin_lock(&part_parser_lock); +@@ -862,6 +886,38 @@ int parse_mtd_partitions(struct mtd_info + return ret; + } + ++int parse_mtd_partitions_by_type(struct mtd_info *master, ++ enum mtd_parser_type type, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct mtd_part_parser *prev = NULL; ++ int ret = 0; ++ ++ while (1) { ++ struct mtd_part_parser *parser; ++ ++ parser = get_partition_parser_by_type(type, prev); ++ if (!parser) ++ break; ++ ++ ret = (*parser->parse_fn)(master, pparts, data); ++ ++ if (ret > 0) { ++ put_partition_parser(parser); ++ printk(KERN_NOTICE ++ "%d %s partitions found on MTD device %s\n", ++ ret, parser->name, master->name); ++ break; ++ } ++ ++ prev = parser; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(parse_mtd_partitions_by_type); ++ + int mtd_is_partition(const struct mtd_info *mtd) + { + struct mtd_part *part; +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -68,12 +68,17 @@ struct mtd_part_parser_data { + * Functions dealing with the various ways of partitioning the space + */ + ++enum mtd_parser_type { ++ MTD_PARSER_TYPE_DEVICE = 0, ++}; ++ + struct mtd_part_parser { + struct list_head list; + struct module *owner; + const char *name; + int (*parse_fn)(struct mtd_info *, struct mtd_partition **, + struct mtd_part_parser_data *); ++ enum mtd_parser_type type; + }; + + extern void register_mtd_parser(struct mtd_part_parser *parser); +@@ -87,4 +92,9 @@ uint64_t mtd_get_device_size(const struc + extern void __weak arch_split_mtd_part(struct mtd_info *master, + const char *name, int offset, int size); + ++int parse_mtd_partitions_by_type(struct mtd_info *master, ++ enum mtd_parser_type type, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data); ++ + #endif diff --git a/target/linux/generic/patches-4.3/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch b/target/linux/generic/patches-4.3/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch new file mode 100644 index 0000000..725dbe8 --- /dev/null +++ b/target/linux/generic/patches-4.3/402-mtd-use-typed-mtd-parsers-for-rootfs-and-firmware-split.patch @@ -0,0 +1,72 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -656,6 +656,37 @@ int mtd_del_partition(struct mtd_info *m + } + EXPORT_SYMBOL_GPL(mtd_del_partition); + ++static int ++run_parsers_by_type(struct mtd_part *slave, enum mtd_parser_type type) ++{ ++ struct mtd_partition *parts; ++ int nr_parts; ++ int i; ++ ++ nr_parts = parse_mtd_partitions_by_type(&slave->mtd, type, &parts, ++ NULL); ++ if (nr_parts <= 0) ++ return nr_parts; ++ ++ if (WARN_ON(!parts)) ++ return 0; ++ ++ for (i = 0; i < nr_parts; i++) { ++ /* adjust partition offsets */ ++ parts[i].offset += slave->offset; ++ ++ __mtd_add_partition(slave->master, ++ parts[i].name, ++ parts[i].offset, ++ parts[i].size, ++ false); ++ } ++ ++ kfree(parts); ++ ++ return nr_parts; ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -664,6 +695,7 @@ EXPORT_SYMBOL_GPL(mtd_del_partition); + + static void split_firmware(struct mtd_info *master, struct mtd_part *part) + { ++ run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); + } + + void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, +@@ -678,6 +710,12 @@ static void mtd_partition_split(struct m + if (rootfs_found) + return; + ++ if (!strcmp(part->mtd.name, "rootfs")) { ++ run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); ++ ++ rootfs_found = 1; ++ } ++ + if (!strcmp(part->mtd.name, SPLIT_FIRMWARE_NAME) && + config_enabled(CONFIG_MTD_SPLIT_FIRMWARE)) + split_firmware(master, part); +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -70,6 +70,8 @@ struct mtd_part_parser_data { + + enum mtd_parser_type { + MTD_PARSER_TYPE_DEVICE = 0, ++ MTD_PARSER_TYPE_ROOTFS, ++ MTD_PARSER_TYPE_FIRMWARE, + }; + + struct mtd_part_parser { diff --git a/target/linux/generic/patches-4.3/403-mtd-hook-mtdsplit-to-Kbuild.patch b/target/linux/generic/patches-4.3/403-mtd-hook-mtdsplit-to-Kbuild.patch new file mode 100644 index 0000000..0cf1c38 --- /dev/null +++ b/target/linux/generic/patches-4.3/403-mtd-hook-mtdsplit-to-Kbuild.patch @@ -0,0 +1,22 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -27,6 +27,8 @@ config MTD_SPLIT_FIRMWARE_NAME + depends on MTD_SPLIT_FIRMWARE + default "firmware" + ++source "drivers/mtd/mtdsplit/Kconfig" ++ + endmenu + + config MTD_TESTS +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -6,6 +6,8 @@ + obj-$(CONFIG_MTD) += mtd.o + mtd-y := mtdcore.o mtdsuper.o mtdconcat.o mtdpart.o mtdchar.o + ++obj-$(CONFIG_MTD_SPLIT) += mtdsplit/ ++ + obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o + obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o diff --git a/target/linux/generic/patches-4.3/404-mtd-add-more-helper-functions.patch b/target/linux/generic/patches-4.3/404-mtd-add-more-helper-functions.patch new file mode 100644 index 0000000..243e4e2 --- /dev/null +++ b/target/linux/generic/patches-4.3/404-mtd-add-more-helper-functions.patch @@ -0,0 +1,101 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -453,14 +453,12 @@ static struct mtd_part *allocate_partiti + if (slave->offset == MTDPART_OFS_APPEND) + slave->offset = cur_offset; + if (slave->offset == MTDPART_OFS_NXTBLK) { +- slave->offset = cur_offset; +- if (mtd_mod_by_eb(cur_offset, master) != 0) { +- /* Round up to next erasesize */ +- slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize; ++ /* Round up to next erasesize */ ++ slave->offset = mtd_roundup_to_eb(cur_offset, master); ++ if (slave->offset != cur_offset) + printk(KERN_NOTICE "Moving partition %d: " + "0x%012llx -> 0x%012llx\n", partno, + (unsigned long long)cur_offset, (unsigned long long)slave->offset); +- } + } + if (slave->offset == MTDPART_OFS_RETAIN) { + slave->offset = cur_offset; +@@ -687,6 +685,17 @@ run_parsers_by_type(struct mtd_part *sla + return nr_parts; + } + ++static inline unsigned long ++mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len) ++{ ++ unsigned long mask = mtd->erasesize - 1; ++ ++ len += offset & mask; ++ len = (len + mask) & ~mask; ++ len -= offset & mask; ++ return len; ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -973,6 +982,24 @@ int mtd_is_partition(const struct mtd_in + } + EXPORT_SYMBOL_GPL(mtd_is_partition); + ++struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd) ++{ ++ if (!mtd_is_partition(mtd)) ++ return (struct mtd_info *)mtd; ++ ++ return PART(mtd)->master; ++} ++EXPORT_SYMBOL_GPL(mtdpart_get_master); ++ ++uint64_t mtdpart_get_offset(const struct mtd_info *mtd) ++{ ++ if (!mtd_is_partition(mtd)) ++ return 0; ++ ++ return PART(mtd)->offset; ++} ++EXPORT_SYMBOL_GPL(mtdpart_get_offset); ++ + /* Returns the size of the entire flash chip */ + uint64_t mtd_get_device_size(const struct mtd_info *mtd) + { +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -90,6 +90,8 @@ int mtd_is_partition(const struct mtd_in + int mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length); + int mtd_del_partition(struct mtd_info *master, int partno); ++struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd); ++uint64_t mtdpart_get_offset(const struct mtd_info *mtd); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); + extern void __weak arch_split_mtd_part(struct mtd_info *master, + const char *name, int offset, int size); +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -334,6 +334,24 @@ static inline uint32_t mtd_mod_by_eb(uin + return do_div(sz, mtd->erasesize); + } + ++static inline uint64_t mtd_roundup_to_eb(uint64_t sz, struct mtd_info *mtd) ++{ ++ if (mtd_mod_by_eb(sz, mtd) == 0) ++ return sz; ++ ++ /* Round up to next erase block */ ++ return (mtd_div_by_eb(sz, mtd) + 1) * mtd->erasesize; ++} ++ ++static inline uint64_t mtd_rounddown_to_eb(uint64_t sz, struct mtd_info *mtd) ++{ ++ if (mtd_mod_by_eb(sz, mtd) == 0) ++ return sz; ++ ++ /* Round down to the start of the current erase block */ ++ return (mtd_div_by_eb(sz, mtd)) * mtd->erasesize; ++} ++ + static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd) + { + if (mtd->writesize_shift) diff --git a/target/linux/generic/patches-4.3/405-mtd-old-firmware-uimage-splitter.patch b/target/linux/generic/patches-4.3/405-mtd-old-firmware-uimage-splitter.patch new file mode 100644 index 0000000..430fd6f --- /dev/null +++ b/target/linux/generic/patches-4.3/405-mtd-old-firmware-uimage-splitter.patch @@ -0,0 +1,70 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -27,6 +27,11 @@ config MTD_SPLIT_FIRMWARE_NAME + depends on MTD_SPLIT_FIRMWARE + default "firmware" + ++config MTD_UIMAGE_SPLIT ++ bool "Enable split support for firmware partitions containing a uImage" ++ depends on MTD_SPLIT_FIRMWARE ++ default y ++ + source "drivers/mtd/mtdsplit/Kconfig" + + endmenu +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -696,6 +696,37 @@ mtd_pad_erasesize(struct mtd_info *mtd, + return len; + } + ++#define UBOOT_MAGIC 0x27051956 ++ ++static void split_uimage(struct mtd_info *master, struct mtd_part *part) ++{ ++ struct { ++ __be32 magic; ++ __be32 pad[2]; ++ __be32 size; ++ } hdr; ++ size_t len; ++ ++ if (mtd_read(master, part->offset, sizeof(hdr), &len, (void *) &hdr)) ++ return; ++ ++ if (len != sizeof(hdr) || hdr.magic != cpu_to_be32(UBOOT_MAGIC)) ++ return; ++ ++ len = be32_to_cpu(hdr.size) + 0x40; ++ len = mtd_pad_erasesize(master, part->offset, len); ++ if (len + master->erasesize > part->mtd.size) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_SPLIT_UIMAGE_FW)) ++ pr_err("Dedicated partitioner didn't split firmware partition, please fill a bug report!\n"); ++ else ++ pr_warn("Support for built-in firmware splitter will be removed, please use CONFIG_MTD_SPLIT_UIMAGE_FW\n"); ++ ++ __mtd_add_partition(master, "rootfs", part->offset + len, ++ part->mtd.size - len, false); ++} ++ + #ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME + #define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME + #else +@@ -704,7 +735,14 @@ mtd_pad_erasesize(struct mtd_info *mtd, + + static void split_firmware(struct mtd_info *master, struct mtd_part *part) + { +- run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); ++ int ret; ++ ++ ret = run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); ++ if (ret > 0) ++ return; ++ ++ if (config_enabled(CONFIG_MTD_UIMAGE_SPLIT)) ++ split_uimage(master, part); + } + + void __weak arch_split_mtd_part(struct mtd_info *master, const char *name, diff --git a/target/linux/generic/patches-4.3/410-mtd-move-forward-declaration-of-struct-mtd_info.patch b/target/linux/generic/patches-4.3/410-mtd-move-forward-declaration-of-struct-mtd_info.patch new file mode 100644 index 0000000..78ebbf8 --- /dev/null +++ b/target/linux/generic/patches-4.3/410-mtd-move-forward-declaration-of-struct-mtd_info.patch @@ -0,0 +1,18 @@ +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -35,6 +35,7 @@ + * Note: writeable partitions require their size and offset be + * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK). + */ ++struct mtd_info; + + struct mtd_partition { + const char *name; /* identifier string */ +@@ -50,7 +51,6 @@ struct mtd_partition { + #define MTDPART_SIZ_FULL (0) + + +-struct mtd_info; + struct device_node; + + /** diff --git a/target/linux/generic/patches-4.3/411-mtd-partial_eraseblock_write.patch b/target/linux/generic/patches-4.3/411-mtd-partial_eraseblock_write.patch new file mode 100644 index 0000000..e6e809c --- /dev/null +++ b/target/linux/generic/patches-4.3/411-mtd-partial_eraseblock_write.patch @@ -0,0 +1,142 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -37,6 +37,8 @@ + #include "mtdcore.h" + #include "mtdsplit/mtdsplit.h" + ++#define MTD_ERASE_PARTIAL 0x8000 /* partition only covers parts of an erase block */ ++ + /* Our partition linked list */ + static LIST_HEAD(mtd_partitions); + static DEFINE_MUTEX(mtd_partitions_mutex); +@@ -235,13 +237,61 @@ static int part_erase(struct mtd_info *m + struct mtd_part *part = PART(mtd); + int ret; + ++ ++ instr->partial_start = false; ++ if (mtd->flags & MTD_ERASE_PARTIAL) { ++ size_t readlen = 0; ++ u64 mtd_ofs; ++ ++ instr->erase_buf = kmalloc(part->master->erasesize, GFP_ATOMIC); ++ if (!instr->erase_buf) ++ return -ENOMEM; ++ ++ mtd_ofs = part->offset + instr->addr; ++ instr->erase_buf_ofs = do_div(mtd_ofs, part->master->erasesize); ++ ++ if (instr->erase_buf_ofs > 0) { ++ instr->addr -= instr->erase_buf_ofs; ++ ret = mtd_read(part->master, ++ instr->addr + part->offset, ++ part->master->erasesize, ++ &readlen, instr->erase_buf); ++ ++ instr->len += instr->erase_buf_ofs; ++ instr->partial_start = true; ++ } else { ++ mtd_ofs = part->offset + part->mtd.size; ++ instr->erase_buf_ofs = part->master->erasesize - ++ do_div(mtd_ofs, part->master->erasesize); ++ ++ if (instr->erase_buf_ofs > 0) { ++ instr->len += instr->erase_buf_ofs; ++ ret = mtd_read(part->master, ++ part->offset + instr->addr + ++ instr->len - part->master->erasesize, ++ part->master->erasesize, &readlen, ++ instr->erase_buf); ++ } else { ++ ret = 0; ++ } ++ } ++ if (ret < 0) { ++ kfree(instr->erase_buf); ++ return ret; ++ } ++ ++ } ++ + instr->addr += part->offset; + ret = part->master->_erase(part->master, instr); + if (ret) { + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; ++ if (mtd->flags & MTD_ERASE_PARTIAL) ++ kfree(instr->erase_buf); + } ++ + return ret; + } + +@@ -249,7 +299,25 @@ void mtd_erase_callback(struct erase_inf + { + if (instr->mtd->_erase == part_erase) { + struct mtd_part *part = PART(instr->mtd); ++ size_t wrlen = 0; + ++ if (instr->mtd->flags & MTD_ERASE_PARTIAL) { ++ if (instr->partial_start) { ++ part->master->_write(part->master, ++ instr->addr, instr->erase_buf_ofs, ++ &wrlen, instr->erase_buf); ++ instr->addr += instr->erase_buf_ofs; ++ } else { ++ instr->len -= instr->erase_buf_ofs; ++ part->master->_write(part->master, ++ instr->addr + instr->len, ++ instr->erase_buf_ofs, &wrlen, ++ instr->erase_buf + ++ part->master->erasesize - ++ instr->erase_buf_ofs); ++ } ++ kfree(instr->erase_buf); ++ } + if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN) + instr->fail_addr -= part->offset; + instr->addr -= part->offset; +@@ -522,17 +590,20 @@ static struct mtd_part *allocate_partiti + if ((slave->mtd.flags & MTD_WRITEABLE) && + mtd_mod_by_eb(slave->offset, &slave->mtd)) { + /* Doesn't start on a boundary of major erase size */ +- /* FIXME: Let it be writable if it is on a boundary of +- * _minor_ erase size though */ +- slave->mtd.flags &= ~MTD_WRITEABLE; +- printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase block boundary -- force read-only\n", +- part->name); ++ slave->mtd.flags |= MTD_ERASE_PARTIAL; ++ if (((u32) slave->mtd.size) > master->erasesize) ++ slave->mtd.flags &= ~MTD_WRITEABLE; ++ else ++ slave->mtd.erasesize = slave->mtd.size; + } + if ((slave->mtd.flags & MTD_WRITEABLE) && +- mtd_mod_by_eb(slave->mtd.size, &slave->mtd)) { +- slave->mtd.flags &= ~MTD_WRITEABLE; +- printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase block -- force read-only\n", +- part->name); ++ mtd_mod_by_eb(slave->offset + slave->mtd.size, &slave->mtd)) { ++ slave->mtd.flags |= MTD_ERASE_PARTIAL; ++ ++ if ((u32) slave->mtd.size > master->erasesize) ++ slave->mtd.flags &= ~MTD_WRITEABLE; ++ else ++ slave->mtd.erasesize = slave->mtd.size; + } + + slave->mtd.ecclayout = master->ecclayout; +--- a/include/linux/mtd/mtd.h ++++ b/include/linux/mtd/mtd.h +@@ -55,6 +55,10 @@ struct erase_info { + u_long priv; + u_char state; + struct erase_info *next; ++ ++ u8 *erase_buf; ++ u32 erase_buf_ofs; ++ bool partial_start; + }; + + struct mtd_erase_region_info { diff --git a/target/linux/generic/patches-4.3/412-mtd-partial_eraseblock_unlock.patch b/target/linux/generic/patches-4.3/412-mtd-partial_eraseblock_unlock.patch new file mode 100644 index 0000000..b7964e2 --- /dev/null +++ b/target/linux/generic/patches-4.3/412-mtd-partial_eraseblock_unlock.patch @@ -0,0 +1,18 @@ +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -336,7 +336,14 @@ static int part_lock(struct mtd_info *mt + static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) + { + struct mtd_part *part = PART(mtd); +- return part->master->_unlock(part->master, ofs + part->offset, len); ++ ++ ofs += part->offset; ++ if (mtd->flags & MTD_ERASE_PARTIAL) { ++ /* round up len to next erasesize and round down offset to prev block */ ++ len = (mtd_div_by_eb(len, part->master) + 1) * part->master->erasesize; ++ ofs &= ~(part->master->erasesize - 1); ++ } ++ return part->master->_unlock(part->master, ofs, len); + } + + static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) diff --git a/target/linux/generic/patches-4.3/420-mtd-redboot_space.patch b/target/linux/generic/patches-4.3/420-mtd-redboot_space.patch new file mode 100644 index 0000000..f74affc --- /dev/null +++ b/target/linux/generic/patches-4.3/420-mtd-redboot_space.patch @@ -0,0 +1,30 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -265,14 +265,21 @@ static int parse_redboot_partitions(stru + #endif + names += strlen(names)+1; + +-#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + if(fl->next && fl->img->flash_base + fl->img->size + master->erasesize <= fl->next->img->flash_base) { +- i++; +- parts[i].offset = parts[i-1].size + parts[i-1].offset; +- parts[i].size = fl->next->img->flash_base - parts[i].offset; +- parts[i].name = nullname; +- } ++ if (!strcmp(parts[i].name, "rootfs")) { ++ parts[i].size = fl->next->img->flash_base; ++ parts[i].size &= ~(master->erasesize - 1); ++ parts[i].size -= parts[i].offset; ++#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED ++ nrparts--; ++ } else { ++ i++; ++ parts[i].offset = parts[i-1].size + parts[i-1].offset; ++ parts[i].size = fl->next->img->flash_base - parts[i].offset; ++ parts[i].name = nullname; + #endif ++ } ++ } + tmp_fl = fl; + fl = fl->next; + kfree(tmp_fl); diff --git a/target/linux/generic/patches-4.3/430-mtd-add-myloader-partition-parser.patch b/target/linux/generic/patches-4.3/430-mtd-add-myloader-partition-parser.patch new file mode 100644 index 0000000..fe74ad5 --- /dev/null +++ b/target/linux/generic/patches-4.3/430-mtd-add-myloader-partition-parser.patch @@ -0,0 +1,35 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -179,6 +179,22 @@ config MTD_BCM47XX_PARTS + This provides partitions parser for devices based on BCM47xx + boards. + ++config MTD_MYLOADER_PARTS ++ tristate "MyLoader partition parsing" ++ depends on ADM5120 || ATH25 || ATH79 ++ ---help--- ++ MyLoader is a bootloader which allows the user to define partitions ++ in flash devices, by putting a table in the second erase block ++ on the device, similar to a partition table. This table gives the ++ offsets and lengths of the user defined partitions. ++ ++ If you need code which can detect and parse these tables, and ++ register MTD 'partitions' corresponding to each image detected, ++ enable this option. ++ ++ You will still need the parsing functions to be called by the driver ++ for your particular device. It won't happen automatically. ++ + comment "User Modules And Translation Layers" + + # +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o ++obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/generic/patches-4.3/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch b/target/linux/generic/patches-4.3/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch new file mode 100644 index 0000000..a30e698 --- /dev/null +++ b/target/linux/generic/patches-4.3/431-mtd-bcm47xxpart-support-for-Xiaomi-specific-board_da.patch @@ -0,0 +1,34 @@ +From 841e59ba3e496d86ca5f069204d5e5c1ad43c01d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Tue, 27 Jan 2015 22:29:21 +0100 +Subject: [PATCH] mtd: bcm47xxpart: support for Xiaomi specific board_data + partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/bcm47xxpart.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -33,6 +33,7 @@ + /* Magics */ + #define BOARD_DATA_MAGIC 0x5246504D /* MPFR */ + #define BOARD_DATA_MAGIC2 0xBD0D0BBD ++#define BOARD_DATA_XIAOMI_MAGIC 0x474D4442 /* GMDB */ + #define CFE_MAGIC 0x43464531 /* 1EFC */ + #define FACTORY_MAGIC 0x59544346 /* FCTY */ + #define NVRAM_HEADER 0x48534C46 /* FLSH */ +@@ -262,7 +263,8 @@ static int bcm47xxpart_parse(struct mtd_ + } + + /* Some devices (ex. WNDR3700v3) don't have a standard 'MPFR' */ +- if (buf[0x000 / 4] == BOARD_DATA_MAGIC2) { ++ if (buf[0x000 / 4] == BOARD_DATA_MAGIC2 || ++ le32_to_cpu(buf[0x000 / 4]) == BOARD_DATA_XIAOMI_MAGIC) { + bcm47xxpart_add_part(&parts[curr_part++], "board_data", + offset, MTD_WRITEABLE); + continue; diff --git a/target/linux/generic/patches-4.3/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch b/target/linux/generic/patches-4.3/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch new file mode 100644 index 0000000..1edc995 --- /dev/null +++ b/target/linux/generic/patches-4.3/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch @@ -0,0 +1,42 @@ +From fd54aa583296f9adfb1f519affbc10ba521eb809 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= +Date: Wed, 28 Jan 2015 22:14:41 +0100 +Subject: [PATCH] mtd: bcm47xxpart: detect T_Meter partition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +It can be found on many Netgear devices. It consists of many 0x30 blocks +starting with 4D 54. + +Signed-off-by: Rafał Miłecki +--- + drivers/mtd/bcm47xxpart.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/bcm47xxpart.c ++++ b/drivers/mtd/bcm47xxpart.c +@@ -39,6 +39,7 @@ + #define NVRAM_HEADER 0x48534C46 /* FLSH */ + #define POT_MAGIC1 0x54544f50 /* POTT */ + #define POT_MAGIC2 0x504f /* OP */ ++#define T_METER_MAGIC 0x4D540000 /* MT */ + #define ML_MAGIC1 0x39685a42 + #define ML_MAGIC2 0x26594131 + #define TRX_MAGIC 0x30524448 +@@ -176,6 +177,15 @@ static int bcm47xxpart_parse(struct mtd_ + MTD_WRITEABLE); + continue; + } ++ ++ /* T_Meter */ ++ if ((le32_to_cpu(buf[0x000 / 4]) & 0xFFFF0000) == T_METER_MAGIC && ++ (le32_to_cpu(buf[0x030 / 4]) & 0xFFFF0000) == T_METER_MAGIC && ++ (le32_to_cpu(buf[0x060 / 4]) & 0xFFFF0000) == T_METER_MAGIC) { ++ bcm47xxpart_add_part(&parts[curr_part++], "T_Meter", offset, ++ MTD_WRITEABLE); ++ continue; ++ } + + /* TRX */ + if (buf[0x000 / 4] == TRX_MAGIC) { diff --git a/target/linux/generic/patches-4.3/440-block2mtd_init.patch b/target/linux/generic/patches-4.3/440-block2mtd_init.patch new file mode 100644 index 0000000..f2e62b4 --- /dev/null +++ b/target/linux/generic/patches-4.3/440-block2mtd_init.patch @@ -0,0 +1,108 @@ +--- a/drivers/mtd/devices/block2mtd.c ++++ b/drivers/mtd/devices/block2mtd.c +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -219,7 +220,7 @@ static void block2mtd_free_device(struct + + + static struct block2mtd_dev *add_device(char *devname, int erase_size, +- int timeout) ++ const char *mtdname, int timeout) + { + #ifndef MODULE + int i; +@@ -227,6 +228,7 @@ static struct block2mtd_dev *add_device( + const fmode_t mode = FMODE_READ | FMODE_WRITE | FMODE_EXCL; + struct block_device *bdev = ERR_PTR(-ENODEV); + struct block2mtd_dev *dev; ++ struct mtd_partition *part; + char *name; + + if (!devname) +@@ -283,13 +285,16 @@ static struct block2mtd_dev *add_device( + + /* Setup the MTD structure */ + /* make the name contain the block device in */ +- name = kasprintf(GFP_KERNEL, "block2mtd: %s", devname); ++ if (!mtdname) ++ mtdname = devname; ++ name = kmalloc(strlen(mtdname) + 1, GFP_KERNEL); + if (!name) + goto err_destroy_mutex; + ++ strcpy(name, mtdname); + dev->mtd.name = name; + +- dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK; ++ dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK & ~(erase_size - 1); + dev->mtd.erasesize = erase_size; + dev->mtd.writesize = 1; + dev->mtd.writebufsize = PAGE_SIZE; +@@ -302,7 +307,11 @@ static struct block2mtd_dev *add_device( + dev->mtd.priv = dev; + dev->mtd.owner = THIS_MODULE; + +- if (mtd_device_register(&dev->mtd, NULL, 0)) { ++ part = kzalloc(sizeof(struct mtd_partition), GFP_KERNEL); ++ part->name = name; ++ part->offset = 0; ++ part->size = dev->mtd.size; ++ if (mtd_device_register(&dev->mtd, part, 1)) { + /* Device didn't get added, so free the entry */ + goto err_destroy_mutex; + } +@@ -310,8 +319,7 @@ static struct block2mtd_dev *add_device( + list_add(&dev->list, &blkmtd_device_list); + pr_info("mtd%d: [%s] erase_size = %dKiB [%d]\n", + dev->mtd.index, +- dev->mtd.name + strlen("block2mtd: "), +- dev->mtd.erasesize >> 10, dev->mtd.erasesize); ++ mtdname, dev->mtd.erasesize >> 10, dev->mtd.erasesize); + return dev; + + err_destroy_mutex: +@@ -384,7 +392,7 @@ static int block2mtd_setup2(const char * + /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ + char buf[80 + 12 + 80 + 8]; + char *str = buf; +- char *token[2]; ++ char *token[3]; + char *name; + size_t erase_size = PAGE_SIZE; + unsigned long timeout = MTD_DEFAULT_TIMEOUT; +@@ -398,7 +406,7 @@ static int block2mtd_setup2(const char * + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 2; i++) ++ for (i = 0; i < 3; i++) + token[i] = strsep(&str, ","); + + if (str) { +@@ -424,8 +432,10 @@ static int block2mtd_setup2(const char * + return 0; + } + } ++ if (token[2] && (strlen(token[2]) + 1 > 80)) ++ pr_err("mtd device name too long\n"); + +- add_device(name, erase_size, timeout); ++ add_device(name, erase_size, token[2], timeout); + + return 0; + } +@@ -459,7 +469,7 @@ static int block2mtd_setup(const char *v + + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); +-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,]\""); ++MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); + + static int __init block2mtd_init(void) + { diff --git a/target/linux/generic/patches-4.3/441-block2mtd_probe.patch b/target/linux/generic/patches-4.3/441-block2mtd_probe.patch new file mode 100644 index 0000000..ed14537 --- /dev/null +++ b/target/linux/generic/patches-4.3/441-block2mtd_probe.patch @@ -0,0 +1,39 @@ +--- a/drivers/mtd/devices/block2mtd.c ++++ b/drivers/mtd/devices/block2mtd.c +@@ -392,7 +392,7 @@ static int block2mtd_setup2(const char * + /* 80 for device, 12 for erase size, 80 for name, 8 for timeout */ + char buf[80 + 12 + 80 + 8]; + char *str = buf; +- char *token[3]; ++ char *token[4]; + char *name; + size_t erase_size = PAGE_SIZE; + unsigned long timeout = MTD_DEFAULT_TIMEOUT; +@@ -406,7 +406,7 @@ static int block2mtd_setup2(const char * + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 3; i++) ++ for (i = 0; i < 4; i++) + token[i] = strsep(&str, ","); + + if (str) { +@@ -435,6 +435,9 @@ static int block2mtd_setup2(const char * + if (token[2] && (strlen(token[2]) + 1 > 80)) + pr_err("mtd device name too long\n"); + ++ if (token[3] && kstrtoul(token[3], 0, &timeout)) ++ pr_err("invalid timeout\n"); ++ + add_device(name, erase_size, token[2], timeout); + + return 0; +@@ -469,7 +472,7 @@ static int block2mtd_setup(const char *v + + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); +-MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,]]\""); ++MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=[,[,[,]]]\""); + + static int __init block2mtd_init(void) + { diff --git a/target/linux/generic/patches-4.3/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch b/target/linux/generic/patches-4.3/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch new file mode 100644 index 0000000..84d2e14 --- /dev/null +++ b/target/linux/generic/patches-4.3/450-mtd-nand-allow-to-use-platform-specific-chip-fixup.patch @@ -0,0 +1,37 @@ +--- + drivers/mtd/nand/plat_nand.c | 13 ++++++++++++- + include/linux/mtd/nand.h | 1 + + 2 files changed, 13 insertions(+), 1 deletion(-) + +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -869,6 +869,7 @@ struct platform_nand_chip { + unsigned int options; + unsigned int bbt_options; + const char **part_probe_types; ++ int (*chip_fixup)(struct mtd_info *mtd); + }; + + /* Keep gcc happy */ +--- a/drivers/mtd/nand/plat_nand.c ++++ b/drivers/mtd/nand/plat_nand.c +@@ -88,7 +88,18 @@ static int plat_nand_probe(struct platfo + } + + /* Scan to find existence of the device */ +- if (nand_scan(&data->mtd, pdata->chip.nr_chips)) { ++ if (nand_scan_ident(&data->mtd, pdata->chip.nr_chips, NULL)) { ++ err = -ENXIO; ++ goto out; ++ } ++ ++ if (pdata->chip.chip_fixup) { ++ err = pdata->chip.chip_fixup(&data->mtd); ++ if (err) ++ goto out; ++ } ++ ++ if (nand_scan_tail(&data->mtd)) { + err = -ENXIO; + goto out; + } diff --git a/target/linux/generic/patches-4.3/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch b/target/linux/generic/patches-4.3/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch new file mode 100644 index 0000000..6a2092c --- /dev/null +++ b/target/linux/generic/patches-4.3/451-mtd-nand-fix-return-code-of-nand_correct_data-function.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/nand/nand_ecc.c ++++ b/drivers/mtd/nand/nand_ecc.c +@@ -507,7 +507,7 @@ int __nand_correct_data(unsigned char *b + return 1; /* error in ECC data; no action needed */ + + pr_err("%s: uncorrectable ECC error\n", __func__); +- return -1; ++ return -EBADMSG; + } + EXPORT_SYMBOL(__nand_correct_data); + diff --git a/target/linux/generic/patches-4.3/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch b/target/linux/generic/patches-4.3/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch new file mode 100644 index 0000000..68fbd12 --- /dev/null +++ b/target/linux/generic/patches-4.3/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -809,7 +809,7 @@ static int get_chip(struct map_info *map + return 0; + + case FL_ERASING: +- if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || ++ if (1 /* no suspend */ || !cfip || !(cfip->EraseSuspend & (0x1|0x2)) || + !(mode == FL_READY || mode == FL_POINT || + (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) + goto sleep; diff --git a/target/linux/generic/patches-4.3/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch b/target/linux/generic/patches-4.3/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch new file mode 100644 index 0000000..c437a14 --- /dev/null +++ b/target/linux/generic/patches-4.3/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch @@ -0,0 +1,18 @@ +From: George Kashperko + +Issue map read after Write Buffer Load command to ensure chip is ready +to receive data. +Signed-off-by: George Kashperko +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 1 + + 1 file changed, 1 insertion(+) +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1830,6 +1830,7 @@ static int __xipram do_write_buffer(stru + + /* Write Buffer Load */ + map_write(map, CMD(0x25), cmd_adr); ++ (void) map_read(map, cmd_adr); + + chip->state = FL_WRITING_TO_BUFFER; + diff --git a/target/linux/generic/patches-4.3/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch b/target/linux/generic/patches-4.3/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch new file mode 100644 index 0000000..b8c2dc6 --- /dev/null +++ b/target/linux/generic/patches-4.3/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch @@ -0,0 +1,22 @@ +From 34e2b403040a2f9d3ba071d95a7f42457e2950f9 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Tue, 7 Apr 2015 18:35:15 +0200 +Subject: [PATCH] mtd: spi-nor: add support for the ISSI SI25CD512 SPI flash + +Signed-off-by: Gabor Juhos +--- + drivers/mtd/spi-nor/spi-nor.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -566,6 +566,9 @@ static const struct flash_info spi_nor_i + /* ISSI */ + { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, + ++ /* ISSI */ ++ { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, ++ + /* Macronix */ + { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, diff --git a/target/linux/generic/patches-4.3/480-mtd-set-rootfs-to-be-root-dev.patch b/target/linux/generic/patches-4.3/480-mtd-set-rootfs-to-be-root-dev.patch new file mode 100644 index 0000000..3ba61e1 --- /dev/null +++ b/target/linux/generic/patches-4.3/480-mtd-set-rootfs-to-be-root-dev.patch @@ -0,0 +1,26 @@ +--- a/drivers/mtd/mtdcore.c ++++ b/drivers/mtd/mtdcore.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -456,6 +457,15 @@ int add_mtd_device(struct mtd_info *mtd) + of this try_ nonsense, and no bitching about it + either. :) */ + __module_get(THIS_MODULE); ++ ++ if (!strcmp(mtd->name, "rootfs") && ++ config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ ROOT_DEV == 0) { ++ pr_notice("mtd: device %d (%s) set to be root filesystem\n", ++ mtd->index, mtd->name); ++ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index); ++ } ++ + return 0; + + fail_added: diff --git a/target/linux/generic/patches-4.3/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/patches-4.3/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch new file mode 100644 index 0000000..8494064 --- /dev/null +++ b/target/linux/generic/patches-4.3/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch @@ -0,0 +1,76 @@ +From 8a52e4100d7c3a4a1dfddfa02b8864a9b0068c13 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 17 May 2014 03:36:18 +0200 +Subject: [PATCH 1/5] ubi: auto-attach mtd device named "ubi" or "data" on boot +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/drivers/mtd/ubi/build.c ++++ b/drivers/mtd/ubi/build.c +@@ -1200,6 +1200,49 @@ static struct mtd_info * __init open_mtd + return mtd; + } + ++/* ++ * This function tries attaching mtd partitions named either "ubi" or "data" ++ * during boot. ++ */ ++static void __init ubi_auto_attach(void) ++{ ++ int err; ++ struct mtd_info *mtd; ++ ++ /* try attaching mtd device named "ubi" or "data" */ ++ mtd = open_mtd_device("ubi"); ++ if (IS_ERR(mtd)) ++ mtd = open_mtd_device("data"); ++ ++ if (!IS_ERR(mtd)) { ++ size_t len; ++ char magic[4]; ++ ++ /* check for a valid ubi magic */ ++ err = mtd_read(mtd, 0, 4, &len, (void *) magic); ++ if (!err && len == 4 && strncmp(magic, "UBI#", 4)) { ++ pr_err("UBI error: no valid UBI magic found inside mtd%d", mtd->index); ++ put_mtd_device(mtd); ++ return; ++ } ++ ++ /* auto-add only media types where UBI makes sense */ ++ if (mtd->type == MTD_NANDFLASH || ++ mtd->type == MTD_NORFLASH || ++ mtd->type == MTD_DATAFLASH || ++ mtd->type == MTD_MLCNANDFLASH) { ++ mutex_lock(&ubi_devices_mutex); ++ pr_notice("UBI: auto-attach mtd%d", mtd->index); ++ err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0); ++ mutex_unlock(&ubi_devices_mutex); ++ if (err < 0) { ++ pr_err("UBI error: cannot attach mtd%d", mtd->index); ++ put_mtd_device(mtd); ++ } ++ } ++ } ++} ++ + static int __init ubi_init(void) + { + int err, i, k; +@@ -1283,6 +1326,12 @@ static int __init ubi_init(void) + } + } + ++ /* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd ++ * parameter was given */ ++ if (config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ !ubi_is_module() && !mtd_devs) ++ ubi_auto_attach(); ++ + err = ubiblock_init(); + if (err) { + pr_err("UBI error: block: cannot initialize, error %d", err); diff --git a/target/linux/generic/patches-4.3/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/patches-4.3/491-ubi-auto-create-ubiblock-device-for-rootfs.patch new file mode 100644 index 0000000..da31112 --- /dev/null +++ b/target/linux/generic/patches-4.3/491-ubi-auto-create-ubiblock-device-for-rootfs.patch @@ -0,0 +1,69 @@ +From 0f3966579815f889bb2fcb4846152c35f65e79c4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 15 May 2014 21:06:33 +0200 +Subject: [PATCH 2/5] ubi: auto-create ubiblock device for rootfs +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/block.c | 42 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -628,6 +628,44 @@ static void __init ubiblock_create_from_ + } + } + ++#define UBIFS_NODE_MAGIC 0x06101831 ++static inline int ubi_vol_is_ubifs(struct ubi_volume_desc *desc) ++{ ++ int ret; ++ uint32_t magic_of, magic; ++ ret = ubi_read(desc, 0, (char *)&magic_of, 0, 4); ++ if (ret) ++ return 0; ++ magic = le32_to_cpu(magic_of); ++ return magic == UBIFS_NODE_MAGIC; ++} ++ ++static void __init ubiblock_create_auto_rootfs(void) ++{ ++ int ubi_num, ret, is_ubifs; ++ struct ubi_volume_desc *desc; ++ struct ubi_volume_info vi; ++ ++ for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) { ++ desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY); ++ if (IS_ERR(desc)) ++ continue; ++ ++ ubi_get_volume_info(desc, &vi); ++ is_ubifs = ubi_vol_is_ubifs(desc); ++ ubi_close_volume(desc); ++ if (is_ubifs) ++ break; ++ ++ ret = ubiblock_create(&vi); ++ if (ret) ++ pr_err("UBI error: block: can't add '%s' volume, err=%d\n", ++ vi.name, ret); ++ /* always break if we get here */ ++ break; ++ } ++} ++ + static void ubiblock_remove_all(void) + { + struct ubiblock *next; +@@ -658,6 +696,10 @@ int __init ubiblock_init(void) + */ + ubiblock_create_from_param(); + ++ /* auto-attach "rootfs" volume if existing and non-ubifs */ ++ if (config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV)) ++ ubiblock_create_auto_rootfs(); ++ + /* + * Block devices are only created upon user requests, so we ignore + * existing volumes. diff --git a/target/linux/generic/patches-4.3/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch b/target/linux/generic/patches-4.3/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch new file mode 100644 index 0000000..d21e6d2 --- /dev/null +++ b/target/linux/generic/patches-4.3/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch @@ -0,0 +1,53 @@ +From eea9e1785e4c05c2a3444506aabafa0ae958538f Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 17 May 2014 03:35:02 +0200 +Subject: [PATCH 4/5] try auto-mounting ubi0:rootfs in init/do_mounts.c +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + init/do_mounts.c | 26 +++++++++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +--- a/init/do_mounts.c ++++ b/init/do_mounts.c +@@ -438,7 +438,27 @@ retry: + out: + put_page(page); + } +- ++ ++static int __init mount_ubi_rootfs(void) ++{ ++ int flags = MS_SILENT; ++ int err, tried = 0; ++ ++ while (tried < 2) { ++ err = do_mount_root("ubi0:rootfs", "ubifs", flags, \ ++ root_mount_data); ++ switch (err) { ++ case -EACCES: ++ flags |= MS_RDONLY; ++ tried++; ++ default: ++ return err; ++ } ++ } ++ ++ return -EINVAL; ++} ++ + #ifdef CONFIG_ROOT_NFS + + #define NFSROOT_TIMEOUT_MIN 5 +@@ -532,6 +552,10 @@ void __init mount_root(void) + change_floppy("root floppy"); + } + #endif ++#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV ++ if (!mount_ubi_rootfs()) ++ return; ++#endif + #ifdef CONFIG_BLOCK + { + int err = create_dev("/dev/root", ROOT_DEV); diff --git a/target/linux/generic/patches-4.3/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/patches-4.3/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch new file mode 100644 index 0000000..f55e8e3 --- /dev/null +++ b/target/linux/generic/patches-4.3/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch @@ -0,0 +1,37 @@ +From cd68d1b12b5ea4c01a664c064179ada42bf55d3d Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Thu, 15 May 2014 20:55:42 +0200 +Subject: [PATCH 5/5] ubi: set ROOT_DEV to ubiblock "rootfs" if unset +To: openwrt-devel@lists.openwrt.org + +Signed-off-by: Daniel Golle +--- + drivers/mtd/ubi/block.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/ubi/block.c ++++ b/drivers/mtd/ubi/block.c +@@ -50,6 +50,7 @@ + #include + #include + #include ++#include + + #include "ubi-media.h" + #include "ubi.h" +@@ -448,6 +449,15 @@ int ubiblock_create(struct ubi_volume_in + add_disk(dev->gd); + dev_info(disk_to_dev(dev->gd), "created from ubi%d:%d(%s)", + dev->ubi_num, dev->vol_id, vi->name); ++ ++ if (!strcmp(vi->name, "rootfs") && ++ config_enabled(CONFIG_MTD_ROOTFS_ROOT_DEV) && ++ ROOT_DEV == 0) { ++ pr_notice("ubiblock: device ubiblock%d_%d (%s) set to be root filesystem\n", ++ dev->ubi_num, dev->vol_id, vi->name); ++ ROOT_DEV = MKDEV(gd->major, gd->first_minor); ++ } ++ + return 0; + + out_free_queue: diff --git a/target/linux/generic/patches-4.3/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/patches-4.3/494-mtd-ubi-add-EOF-marker-support.patch new file mode 100644 index 0000000..14fae76 --- /dev/null +++ b/target/linux/generic/patches-4.3/494-mtd-ubi-add-EOF-marker-support.patch @@ -0,0 +1,51 @@ +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -803,6 +803,13 @@ out_unlock: + return err; + } + ++static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech) ++{ ++ return ech->padding1[0] == 'E' && ++ ech->padding1[1] == 'O' && ++ ech->padding1[2] == 'F'; ++} ++ + /** + * scan_peb - scan and process UBI headers of a PEB. + * @ubi: UBI device description object +@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u + return 0; + } + +- err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); +- if (err < 0) +- return err; ++ if (!ai->eof_found) { ++ err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); ++ if (err < 0) ++ return err; ++ ++ if (ec_hdr_has_eof(ech)) { ++ pr_notice("UBI: EOF marker found, PEBs from %d will be erased", ++ pnum); ++ ai->eof_found = true; ++ } ++ } ++ ++ if (ai->eof_found) ++ err = UBI_IO_FF_BITFLIPS; ++ + switch (err) { + case 0: + break; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -739,6 +739,7 @@ struct ubi_attach_info { + int mean_ec; + uint64_t ec_sum; + int ec_count; ++ bool eof_found; + struct kmem_cache *aeb_slab_cache; + }; + diff --git a/target/linux/generic/patches-4.3/500-yaffs-Kbuild-integration.patch b/target/linux/generic/patches-4.3/500-yaffs-Kbuild-integration.patch new file mode 100644 index 0000000..ab184e6 --- /dev/null +++ b/target/linux/generic/patches-4.3/500-yaffs-Kbuild-integration.patch @@ -0,0 +1,18 @@ +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -30,6 +30,7 @@ source "fs/ocfs2/Kconfig" + source "fs/btrfs/Kconfig" + source "fs/nilfs2/Kconfig" + source "fs/f2fs/Kconfig" ++source "fs/yaffs2/Kconfig" + + config FS_DAX + bool "Direct Access (DAX) support" +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -125,3 +125,5 @@ obj-y += exofs/ # Multiple modules + obj-$(CONFIG_CEPH_FS) += ceph/ + obj-$(CONFIG_PSTORE) += pstore/ + obj-$(CONFIG_EFIVAR_FS) += efivarfs/ ++obj-$(CONFIG_YAFFS_FS) += yaffs2/ ++ diff --git a/target/linux/generic/patches-4.3/502-yaffs-fix-compat-tags-handling.patch b/target/linux/generic/patches-4.3/502-yaffs-fix-compat-tags-handling.patch new file mode 100644 index 0000000..a18cf6f --- /dev/null +++ b/target/linux/generic/patches-4.3/502-yaffs-fix-compat-tags-handling.patch @@ -0,0 +1,239 @@ +Subject: yaffs: fix compat tags handling + +Signed-off-by: Gabor Juhos +--- +--- a/fs/yaffs2/yaffs_tagscompat.c ++++ b/fs/yaffs2/yaffs_tagscompat.c +@@ -17,7 +17,9 @@ + #include "yaffs_getblockinfo.h" + #include "yaffs_trace.h" + ++#if 0 + static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk); ++#endif + + + /********** Tags ECC calculations *********/ +@@ -71,6 +73,7 @@ int yaffs_check_tags_ecc(struct yaffs_ta + return 0; + } + ++#if 0 + /********** Tags **********/ + + static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr, +@@ -379,3 +382,214 @@ void yaffs_tags_compat_install(struct ya + if(!dev->tagger.mark_bad_fn) + dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; + } ++#else ++ ++#include "yaffs_packedtags1.h" ++ ++static int yaffs_tags_compat_write(struct yaffs_dev *dev, ++ int nand_chunk, ++ const u8 *data, ++ const struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags1 pt1; ++ u8 tag_buf[9]; ++ int retval; ++ ++ /* we assume that yaffs_packed_tags1 and yaffs_tags are compatible */ ++ compile_time_assertion(sizeof(struct yaffs_packed_tags1) == 12); ++ compile_time_assertion(sizeof(struct yaffs_tags) == 8); ++ ++ yaffs_pack_tags1(&pt1, tags); ++ yaffs_calc_tags_ecc((struct yaffs_tags *)&pt1); ++ ++ /* When deleting a chunk, the upper layer provides only skeletal ++ * tags, one with is_deleted set. However, we need to update the ++ * tags, not erase them completely. So we use the NAND write property ++ * that only zeroed-bits stick and set tag bytes to all-ones and ++ * zero just the (not) deleted bit. ++ */ ++ if (!dev->param.tags_9bytes) { ++ if (tags->is_deleted) { ++ memset(&pt1, 0xff, 8); ++ /* clear delete status bit to indicate deleted */ ++ pt1.deleted = 0; ++ } ++ memcpy(tag_buf, &pt1, 8); ++ } else { ++ if (tags->is_deleted) { ++ memset(tag_buf, 0xff, 8); ++ tag_buf[8] = 0; ++ } else { ++ memcpy(tag_buf, &pt1, 8); ++ tag_buf[8] = 0xff; ++ } ++ } ++ ++ retval = dev->drv.drv_write_chunk_fn(dev, nand_chunk, ++ data, ++ (data) ? dev->data_bytes_per_chunk : 0, ++ tag_buf, ++ (dev->param.tags_9bytes) ? 9 : 8); ++ ++ return retval; ++} ++ ++/* Return with empty extended tags but add ecc_result. ++ */ ++static int return_empty_tags(struct yaffs_ext_tags *tags, ++ enum yaffs_ecc_result ecc_result, ++ int retval) ++{ ++ if (tags) { ++ memset(tags, 0, sizeof(*tags)); ++ tags->ecc_result = ecc_result; ++ } ++ ++ return retval; ++} ++ ++static int yaffs_tags_compat_read(struct yaffs_dev *dev, ++ int nand_chunk, ++ u8 *data, ++ struct yaffs_ext_tags *tags) ++{ ++ struct yaffs_packed_tags1 pt1; ++ enum yaffs_ecc_result ecc_result; ++ int retval; ++ int deleted; ++ u8 tag_buf[9]; ++ ++ retval = dev->drv.drv_read_chunk_fn(dev, nand_chunk, ++ data, dev->param.total_bytes_per_chunk, ++ tag_buf, ++ (dev->param.tags_9bytes) ? 9 : 8, ++ &ecc_result); ++ ++ switch (ecc_result) { ++ case YAFFS_ECC_RESULT_NO_ERROR: ++ case YAFFS_ECC_RESULT_FIXED: ++ break; ++ ++ case YAFFS_ECC_RESULT_UNFIXED: ++ default: ++ return_empty_tags(tags, YAFFS_ECC_RESULT_UNFIXED, 0); ++ tags->block_bad = dev->drv.drv_check_bad_fn(dev, nand_chunk); ++ return YAFFS_FAIL; ++ } ++ ++ /* Check for a blank/erased chunk. */ ++ if (yaffs_check_ff(tag_buf, 8)) { ++ /* when blank, upper layers want ecc_result to be <= NO_ERROR */ ++ return return_empty_tags(tags, YAFFS_ECC_RESULT_NO_ERROR, ++ YAFFS_OK); ++ } ++ ++ memcpy(&pt1, tag_buf, 8); ++ ++ if (!dev->param.tags_9bytes) { ++ /* Read deleted status (bit) then return it to it's non-deleted ++ * state before performing tags mini-ECC check. pt1.deleted is ++ * inverted. ++ */ ++ deleted = !pt1.deleted; ++ pt1.deleted = 1; ++ } else { ++ deleted = (hweight8(tag_buf[8]) < 7) ? 1 : 0; ++ } ++ ++ /* Check the packed tags mini-ECC and correct if necessary/possible. */ ++ retval = yaffs_check_tags_ecc((struct yaffs_tags *)&pt1); ++ switch (retval) { ++ case 0: ++ /* no tags error, use MTD result */ ++ break; ++ case 1: ++ /* recovered tags-ECC error */ ++ dev->n_tags_ecc_fixed++; ++ if (ecc_result == YAFFS_ECC_RESULT_NO_ERROR) ++ ecc_result = YAFFS_ECC_RESULT_FIXED; ++ break; ++ default: ++ /* unrecovered tags-ECC error */ ++ dev->n_tags_ecc_unfixed++; ++ return return_empty_tags(tags, YAFFS_ECC_RESULT_UNFIXED, ++ YAFFS_FAIL); ++ } ++ ++ /* Unpack the tags to extended form and set ECC result. ++ * [set should_be_ff just to keep yaffs_unpack_tags1 happy] ++ */ ++ pt1.should_be_ff = 0xffffffff; ++ yaffs_unpack_tags1(tags, &pt1); ++ tags->ecc_result = ecc_result; ++ ++ /* Set deleted state */ ++ tags->is_deleted = deleted; ++ return YAFFS_OK; ++} ++ ++static int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no) ++{ ++ return dev->drv.drv_mark_bad_fn(dev, block_no); ++} ++ ++static int yaffs_tags_compat_query_block(struct yaffs_dev *dev, ++ int block_no, ++ enum yaffs_block_state *state, ++ u32 *seq_number) ++{ ++ struct yaffs_ext_tags tags; ++ int retval; ++ ++ yaffs_trace(YAFFS_TRACE_MTD, "%s %d", __func__, block_no); ++ ++ *seq_number = 0; ++ ++ retval = dev->drv.drv_check_bad_fn(dev, block_no); ++ if (retval == YAFFS_FAIL) { ++ *state = YAFFS_BLOCK_STATE_DEAD; ++ goto out; ++ } ++ ++ yaffs_tags_compat_read(dev, block_no * dev->param.chunks_per_block, ++ NULL, &tags); ++ ++ if (tags.ecc_result != YAFFS_ECC_RESULT_NO_ERROR) { ++ yaffs_trace(YAFFS_TRACE_MTD, "block %d is marked bad", ++ block_no); ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else if (tags.chunk_used) { ++ *seq_number = tags.seq_number; ++ *state = YAFFS_BLOCK_STATE_NEEDS_SCAN; ++ } else { ++ *state = YAFFS_BLOCK_STATE_EMPTY; ++ } ++ ++ retval = YAFFS_OK; ++ ++out: ++ yaffs_trace(YAFFS_TRACE_MTD, ++ "block query returns seq %u state %d", ++ *seq_number, *state); ++ ++ return retval; ++} ++ ++void yaffs_tags_compat_install(struct yaffs_dev *dev) ++{ ++ if (dev->param.is_yaffs2) ++ return; ++ ++ if (!dev->tagger.write_chunk_tags_fn) ++ dev->tagger.write_chunk_tags_fn = yaffs_tags_compat_write; ++ ++ if (!dev->tagger.read_chunk_tags_fn) ++ dev->tagger.read_chunk_tags_fn = yaffs_tags_compat_read; ++ ++ if (!dev->tagger.query_block_fn) ++ dev->tagger.query_block_fn = yaffs_tags_compat_query_block; ++ ++ if (!dev->tagger.mark_bad_fn) ++ dev->tagger.mark_bad_fn = yaffs_tags_compat_mark_bad; ++} ++#endif diff --git a/target/linux/generic/patches-4.3/503-yaffs-add-tags-9bytes-mount-option.patch b/target/linux/generic/patches-4.3/503-yaffs-add-tags-9bytes-mount-option.patch new file mode 100644 index 0000000..3f51baf --- /dev/null +++ b/target/linux/generic/patches-4.3/503-yaffs-add-tags-9bytes-mount-option.patch @@ -0,0 +1,115 @@ +Subject: yaffs: add support for tags-9bytes mount option + +Signed-off-by: Gabor Juhos +--- +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -2644,6 +2644,7 @@ static const struct super_operations yaf + + struct yaffs_options { + int inband_tags; ++ int tags_9bytes; + int skip_checkpoint_read; + int skip_checkpoint_write; + int no_cache; +@@ -2683,6 +2684,8 @@ static int yaffs_parse_options(struct ya + + if (!strcmp(cur_opt, "inband-tags")) { + options->inband_tags = 1; ++ } else if (!strcmp(cur_opt, "tags-9bytes")) { ++ options->tags_9bytes = 1; + } else if (!strcmp(cur_opt, "tags-ecc-off")) { + options->tags_ecc_on = 0; + options->tags_ecc_overridden = 1; +@@ -2756,7 +2759,6 @@ static struct super_block *yaffs_interna + struct yaffs_param *param; + + int read_only = 0; +- int inband_tags = 0; + + struct yaffs_options options; + +@@ -2796,6 +2798,9 @@ static struct super_block *yaffs_interna + + memset(&options, 0, sizeof(options)); + ++ if (IS_ENABLED(CONFIG_YAFFS_9BYTE_TAGS)) ++ options.tags_9bytes = 1; ++ + if (yaffs_parse_options(&options, data_str)) { + /* Option parsing failed */ + return NULL; +@@ -2829,17 +2834,22 @@ static struct super_block *yaffs_interna + } + + /* Added NCB 26/5/2006 for completeness */ +- if (yaffs_version == 2 && !options.inband_tags +- && WRITE_SIZE(mtd) == 512) { ++ if (yaffs_version == 2 && ++ (!options.inband_tags || options.tags_9bytes) && ++ WRITE_SIZE(mtd) == 512) { + yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting yaffs1"); + yaffs_version = 1; + } + +- if (mtd->oobavail < sizeof(struct yaffs_packed_tags2) || +- options.inband_tags) +- inband_tags = 1; ++ if (yaffs_version == 2 && ++ mtd->oobavail < sizeof(struct yaffs_packed_tags2)) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, "auto selecting inband tags"); ++ options.inband_tags = 1; ++ } + +- if(yaffs_verify_mtd(mtd, yaffs_version, inband_tags) < 0) ++ err = yaffs_verify_mtd(mtd, yaffs_version, options.inband_tags, ++ options.tags_9bytes); ++ if (err < 0) + return NULL; + + /* OK, so if we got here, we have an MTD that's NAND and looks +@@ -2896,7 +2906,8 @@ static struct super_block *yaffs_interna + + param->n_reserved_blocks = 5; + param->n_caches = (options.no_cache) ? 0 : 10; +- param->inband_tags = inband_tags; ++ param->inband_tags = options.inband_tags; ++ param->tags_9bytes = options.tags_9bytes; + + param->enable_xattr = 1; + if (options.lazy_loading_overridden) +--- a/fs/yaffs2/yaffs_mtdif.c ++++ b/fs/yaffs2/yaffs_mtdif.c +@@ -278,7 +278,8 @@ struct mtd_info * yaffs_get_mtd_device(d + return mtd; + } + +-int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags) ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags, ++ int tags_9bytes) + { + if (yaffs_version == 2) { + if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || +@@ -297,6 +298,12 @@ int yaffs_verify_mtd(struct mtd_info *mt + ); + return -1; + } ++ ++ if (tags_9bytes && mtd->oobavail < 9) { ++ yaffs_trace(YAFFS_TRACE_ALWAYS, ++ "MTD device does not support 9-byte tags"); ++ return -1; ++ } + } + + return 0; +--- a/fs/yaffs2/yaffs_mtdif.h ++++ b/fs/yaffs2/yaffs_mtdif.h +@@ -21,5 +21,6 @@ + void yaffs_mtd_drv_install(struct yaffs_dev *dev); + struct mtd_info * yaffs_get_mtd_device(dev_t sdev); + void yaffs_put_mtd_device(struct mtd_info *mtd); +-int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags); ++int yaffs_verify_mtd(struct mtd_info *mtd, int yaffs_version, int inband_tags, ++ int tags_9bytes); + #endif diff --git a/target/linux/generic/patches-4.3/504-yaffs-3.16-new-fops.patch b/target/linux/generic/patches-4.3/504-yaffs-3.16-new-fops.patch new file mode 100644 index 0000000..32b4fdf --- /dev/null +++ b/target/linux/generic/patches-4.3/504-yaffs-3.16-new-fops.patch @@ -0,0 +1,29 @@ +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -774,7 +774,25 @@ static int yaffs_sync_object(struct file + } + + +-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) ++static const struct file_operations yaffs_file_operations = { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)) ++ .read = new_sync_read, ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0) */ ++ .read_iter = generic_file_read_iter, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0)) ++ .write = new_sync_write, ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0) */ ++ .write_iter = generic_file_write_iter, ++ .mmap = generic_file_mmap, ++ .flush = yaffs_file_flush, ++ .fsync = yaffs_sync_object, ++ .splice_read = generic_file_splice_read, ++ .splice_write = iter_file_splice_write, ++ .llseek = generic_file_llseek, ++}; ++ ++#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) + static const struct file_operations yaffs_file_operations = { + .read = do_sync_read, + .write = do_sync_write, diff --git a/target/linux/generic/patches-4.3/505-yaffs-3.19-f_dentry-remove.patch b/target/linux/generic/patches-4.3/505-yaffs-3.19-f_dentry-remove.patch new file mode 100644 index 0000000..0d4b6bf --- /dev/null +++ b/target/linux/generic/patches-4.3/505-yaffs-3.19-f_dentry-remove.patch @@ -0,0 +1,95 @@ +--- a/fs/yaffs2/yaffs_vfs.c ++++ b/fs/yaffs2/yaffs_vfs.c +@@ -283,7 +283,7 @@ static int yaffs_readpage_nolock(struct + (long long)pos, + (unsigned)PAGE_CACHE_SIZE); + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -481,7 +481,7 @@ static ssize_t yaffs_hold_space(struct f + + int n_free_chunks; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -499,7 +499,7 @@ static void yaffs_release_space(struct f + struct yaffs_obj *obj; + struct yaffs_dev *dev; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + dev = obj->my_dev; + +@@ -591,7 +591,7 @@ static ssize_t yaffs_file_write(struct f + struct inode *inode; + struct yaffs_dev *dev; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + + if (!obj) { + yaffs_trace(YAFFS_TRACE_OS, +@@ -603,7 +603,7 @@ static ssize_t yaffs_file_write(struct f + + yaffs_gross_lock(dev); + +- inode = f->f_dentry->d_inode; ++ inode = f->f_path.dentry->d_inode; + + if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) + ipos = inode->i_size; +@@ -727,7 +727,7 @@ static int yaffs_file_flush(struct file + static int yaffs_file_flush(struct file *file) + #endif + { +- struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_dentry); ++ struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_path.dentry); + + struct yaffs_dev *dev = obj->my_dev; + +@@ -1734,7 +1734,7 @@ static int yaffs_iterate(struct file *f, + + char name[YAFFS_MAX_NAME_LENGTH + 1]; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + dev = obj->my_dev; + + yaffs_gross_lock(dev); +@@ -1798,14 +1798,14 @@ static int yaffs_readdir(struct file *f, + struct yaffs_obj *obj; + struct yaffs_dev *dev; + struct yaffs_search_context *sc; +- struct inode *inode = f->f_dentry->d_inode; ++ struct inode *inode = f->f_path.dentry->d_inode; + unsigned long offset, curoffs; + struct yaffs_obj *l; + int ret_val = 0; + + char name[YAFFS_MAX_NAME_LENGTH + 1]; + +- obj = yaffs_dentry_to_obj(f->f_dentry); ++ obj = yaffs_dentry_to_obj(f->f_path.dentry); + dev = obj->my_dev; + + yaffs_gross_lock(dev); +@@ -1839,10 +1839,10 @@ static int yaffs_readdir(struct file *f, + if (offset == 1) { + yaffs_trace(YAFFS_TRACE_OS, + "yaffs_readdir: entry .. ino %d", +- (int)f->f_dentry->d_parent->d_inode->i_ino); ++ (int)f->f_path.dentry->d_parent->d_inode->i_ino); + yaffs_gross_unlock(dev); + if (filldir(dirent, "..", 2, offset, +- f->f_dentry->d_parent->d_inode->i_ino, ++ f->f_path.dentry->d_parent->d_inode->i_ino, + DT_DIR) < 0) { + yaffs_gross_lock(dev); + goto out; diff --git a/target/linux/generic/patches-4.3/520-squashfs_update_xz_comp_opts.patch b/target/linux/generic/patches-4.3/520-squashfs_update_xz_comp_opts.patch new file mode 100644 index 0000000..ad11b30 --- /dev/null +++ b/target/linux/generic/patches-4.3/520-squashfs_update_xz_comp_opts.patch @@ -0,0 +1,25 @@ +From f31b7c0efa255dd17a5f584022a319387f09b0d8 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Tue, 12 Apr 2011 19:55:41 +0200 +Subject: [PATCH] squashfs: update xz compressor options struct. + +Update the xz compressor options struct to match the squashfs userspace +one. +--- + fs/squashfs/xz_wrapper.c | 4 +++- + 1 files changed, 3 insertions(+), 1 deletions(-) + +--- a/fs/squashfs/xz_wrapper.c ++++ b/fs/squashfs/xz_wrapper.c +@@ -40,8 +40,10 @@ struct squashfs_xz { + }; + + struct disk_comp_opts { +- __le32 dictionary_size; + __le32 flags; ++ __le16 bit_opts; ++ __le16 fb; ++ __le32 dictionary_size; + }; + + struct comp_opts { diff --git a/target/linux/generic/patches-4.3/530-jffs2_make_lzma_available.patch b/target/linux/generic/patches-4.3/530-jffs2_make_lzma_available.patch new file mode 100644 index 0000000..d95563f --- /dev/null +++ b/target/linux/generic/patches-4.3/530-jffs2_make_lzma_available.patch @@ -0,0 +1,5142 @@ +--- a/fs/jffs2/Kconfig ++++ b/fs/jffs2/Kconfig +@@ -139,6 +139,15 @@ config JFFS2_LZO + This feature was added in July, 2007. Say 'N' if you need + compatibility with older bootloaders or kernels. + ++config JFFS2_LZMA ++ bool "JFFS2 LZMA compression support" if JFFS2_COMPRESSION_OPTIONS ++ select LZMA_COMPRESS ++ select LZMA_DECOMPRESS ++ depends on JFFS2_FS ++ default n ++ help ++ JFFS2 wrapper to the LZMA C SDK ++ + config JFFS2_RTIME + bool "JFFS2 RTIME compression support" if JFFS2_COMPRESSION_OPTIONS + depends on JFFS2_FS +--- a/fs/jffs2/Makefile ++++ b/fs/jffs2/Makefile +@@ -18,4 +18,7 @@ jffs2-$(CONFIG_JFFS2_RUBIN) += compr_rub + jffs2-$(CONFIG_JFFS2_RTIME) += compr_rtime.o + jffs2-$(CONFIG_JFFS2_ZLIB) += compr_zlib.o + jffs2-$(CONFIG_JFFS2_LZO) += compr_lzo.o ++jffs2-$(CONFIG_JFFS2_LZMA) += compr_lzma.o + jffs2-$(CONFIG_JFFS2_SUMMARY) += summary.o ++ ++CFLAGS_compr_lzma.o += -Iinclude/linux -Ilib/lzma +--- a/fs/jffs2/compr.c ++++ b/fs/jffs2/compr.c +@@ -378,6 +378,9 @@ int __init jffs2_compressors_init(void) + #ifdef CONFIG_JFFS2_LZO + jffs2_lzo_init(); + #endif ++#ifdef CONFIG_JFFS2_LZMA ++ jffs2_lzma_init(); ++#endif + /* Setting default compression mode */ + #ifdef CONFIG_JFFS2_CMODE_NONE + jffs2_compression_mode = JFFS2_COMPR_MODE_NONE; +@@ -401,6 +404,9 @@ int __init jffs2_compressors_init(void) + int jffs2_compressors_exit(void) + { + /* Unregistering compressors */ ++#ifdef CONFIG_JFFS2_LZMA ++ jffs2_lzma_exit(); ++#endif + #ifdef CONFIG_JFFS2_LZO + jffs2_lzo_exit(); + #endif +--- a/fs/jffs2/compr.h ++++ b/fs/jffs2/compr.h +@@ -29,9 +29,9 @@ + #define JFFS2_DYNRUBIN_PRIORITY 20 + #define JFFS2_LZARI_PRIORITY 30 + #define JFFS2_RTIME_PRIORITY 50 +-#define JFFS2_ZLIB_PRIORITY 60 +-#define JFFS2_LZO_PRIORITY 80 +- ++#define JFFS2_LZMA_PRIORITY 70 ++#define JFFS2_ZLIB_PRIORITY 80 ++#define JFFS2_LZO_PRIORITY 90 + + #define JFFS2_RUBINMIPS_DISABLED /* RUBINs will be used only */ + #define JFFS2_DYNRUBIN_DISABLED /* for decompression */ +@@ -101,5 +101,9 @@ void jffs2_zlib_exit(void); + int jffs2_lzo_init(void); + void jffs2_lzo_exit(void); + #endif ++#ifdef CONFIG_JFFS2_LZMA ++int jffs2_lzma_init(void); ++void jffs2_lzma_exit(void); ++#endif + + #endif /* __JFFS2_COMPR_H__ */ +--- /dev/null ++++ b/fs/jffs2/compr_lzma.c +@@ -0,0 +1,128 @@ ++/* ++ * JFFS2 -- Journalling Flash File System, Version 2. ++ * ++ * For licensing information, see the file 'LICENCE' in this directory. ++ * ++ * JFFS2 wrapper to the LZMA C SDK ++ * ++ */ ++ ++#include ++#include "compr.h" ++ ++#ifdef __KERNEL__ ++ static DEFINE_MUTEX(deflate_mutex); ++#endif ++ ++CLzmaEncHandle *p; ++Byte propsEncoded[LZMA_PROPS_SIZE]; ++SizeT propsSize = sizeof(propsEncoded); ++ ++STATIC void lzma_free_workspace(void) ++{ ++ LzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc); ++} ++ ++STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props) ++{ ++ if ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL) ++ { ++ PRINT_ERROR("Failed to allocate lzma deflate workspace\n"); ++ return -ENOMEM; ++ } ++ ++ if (LzmaEnc_SetProps(p, props) != SZ_OK) ++ { ++ lzma_free_workspace(); ++ return -1; ++ } ++ ++ if (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK) ++ { ++ lzma_free_workspace(); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out, ++ uint32_t *sourcelen, uint32_t *dstlen) ++{ ++ SizeT compress_size = (SizeT)(*dstlen); ++ int ret; ++ ++ #ifdef __KERNEL__ ++ mutex_lock(&deflate_mutex); ++ #endif ++ ++ ret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen, ++ 0, NULL, &lzma_alloc, &lzma_alloc); ++ ++ #ifdef __KERNEL__ ++ mutex_unlock(&deflate_mutex); ++ #endif ++ ++ if (ret != SZ_OK) ++ return -1; ++ ++ *dstlen = (uint32_t)compress_size; ++ ++ return 0; ++} ++ ++STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out, ++ uint32_t srclen, uint32_t destlen) ++{ ++ int ret; ++ SizeT dl = (SizeT)destlen; ++ SizeT sl = (SizeT)srclen; ++ ELzmaStatus status; ++ ++ ret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded, ++ propsSize, LZMA_FINISH_ANY, &status, &lzma_alloc); ++ ++ if (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen) ++ return -1; ++ ++ return 0; ++} ++ ++static struct jffs2_compressor jffs2_lzma_comp = { ++ .priority = JFFS2_LZMA_PRIORITY, ++ .name = "lzma", ++ .compr = JFFS2_COMPR_LZMA, ++ .compress = &jffs2_lzma_compress, ++ .decompress = &jffs2_lzma_decompress, ++ .disabled = 0, ++}; ++ ++int INIT jffs2_lzma_init(void) ++{ ++ int ret; ++ CLzmaEncProps props; ++ LzmaEncProps_Init(&props); ++ ++ props.dictSize = LZMA_BEST_DICT(0x2000); ++ props.level = LZMA_BEST_LEVEL; ++ props.lc = LZMA_BEST_LC; ++ props.lp = LZMA_BEST_LP; ++ props.pb = LZMA_BEST_PB; ++ props.fb = LZMA_BEST_FB; ++ ++ ret = lzma_alloc_workspace(&props); ++ if (ret < 0) ++ return ret; ++ ++ ret = jffs2_register_compressor(&jffs2_lzma_comp); ++ if (ret) ++ lzma_free_workspace(); ++ ++ return ret; ++} ++ ++void jffs2_lzma_exit(void) ++{ ++ jffs2_unregister_compressor(&jffs2_lzma_comp); ++ lzma_free_workspace(); ++} +--- a/fs/jffs2/super.c ++++ b/fs/jffs2/super.c +@@ -375,14 +375,41 @@ static int __init init_jffs2_fs(void) + BUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68); + BUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32); + +- pr_info("version 2.2." ++ pr_info("version 2.2" + #ifdef CONFIG_JFFS2_FS_WRITEBUFFER + " (NAND)" + #endif + #ifdef CONFIG_JFFS2_SUMMARY +- " (SUMMARY) " ++ " (SUMMARY)" + #endif +- " © 2001-2006 Red Hat, Inc.\n"); ++#ifdef CONFIG_JFFS2_ZLIB ++ " (ZLIB)" ++#endif ++#ifdef CONFIG_JFFS2_LZO ++ " (LZO)" ++#endif ++#ifdef CONFIG_JFFS2_LZMA ++ " (LZMA)" ++#endif ++#ifdef CONFIG_JFFS2_RTIME ++ " (RTIME)" ++#endif ++#ifdef CONFIG_JFFS2_RUBIN ++ " (RUBIN)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_NONE ++ " (CMODE_NONE)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_PRIORITY ++ " (CMODE_PRIORITY)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_SIZE ++ " (CMODE_SIZE)" ++#endif ++#ifdef CONFIG_JFFS2_CMODE_FAVOURLZO ++ " (CMODE_FAVOURLZO)" ++#endif ++ " (c) 2001-2006 Red Hat, Inc.\n"); + + jffs2_inode_cachep = kmem_cache_create("jffs2_i", + sizeof(struct jffs2_inode_info), +--- a/include/uapi/linux/jffs2.h ++++ b/include/uapi/linux/jffs2.h +@@ -46,6 +46,7 @@ + #define JFFS2_COMPR_DYNRUBIN 0x05 + #define JFFS2_COMPR_ZLIB 0x06 + #define JFFS2_COMPR_LZO 0x07 ++#define JFFS2_COMPR_LZMA 0x08 + /* Compatibility flags. */ + #define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ + #define JFFS2_NODE_ACCURATE 0x2000 +--- /dev/null ++++ b/include/linux/lzma.h +@@ -0,0 +1,62 @@ ++#ifndef __LZMA_H__ ++#define __LZMA_H__ ++ ++#ifdef __KERNEL__ ++ #include ++ #include ++ #include ++ #include ++ #include ++ #define LZMA_MALLOC vmalloc ++ #define LZMA_FREE vfree ++ #define PRINT_ERROR(msg) printk(KERN_WARNING #msg) ++ #define INIT __init ++ #define STATIC static ++#else ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #ifndef PAGE_SIZE ++ extern int page_size; ++ #define PAGE_SIZE page_size ++ #endif ++ #define LZMA_MALLOC malloc ++ #define LZMA_FREE free ++ #define PRINT_ERROR(msg) fprintf(stderr, msg) ++ #define INIT ++ #define STATIC ++#endif ++ ++#include "lzma/LzmaDec.h" ++#include "lzma/LzmaEnc.h" ++ ++#define LZMA_BEST_LEVEL (9) ++#define LZMA_BEST_LC (0) ++#define LZMA_BEST_LP (0) ++#define LZMA_BEST_PB (0) ++#define LZMA_BEST_FB (273) ++ ++#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2) ++ ++static void *p_lzma_malloc(void *p, size_t size) ++{ ++ if (size == 0) ++ return NULL; ++ ++ return LZMA_MALLOC(size); ++} ++ ++static void p_lzma_free(void *p, void *address) ++{ ++ if (address != NULL) ++ LZMA_FREE(address); ++} ++ ++static ISzAlloc lzma_alloc = {p_lzma_malloc, p_lzma_free}; ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzFind.h +@@ -0,0 +1,115 @@ ++/* LzFind.h -- Match finder for LZ algorithms ++2009-04-22 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZ_FIND_H ++#define __LZ_FIND_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef UInt32 CLzRef; ++ ++typedef struct _CMatchFinder ++{ ++ Byte *buffer; ++ UInt32 pos; ++ UInt32 posLimit; ++ UInt32 streamPos; ++ UInt32 lenLimit; ++ ++ UInt32 cyclicBufferPos; ++ UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */ ++ ++ UInt32 matchMaxLen; ++ CLzRef *hash; ++ CLzRef *son; ++ UInt32 hashMask; ++ UInt32 cutValue; ++ ++ Byte *bufferBase; ++ ISeqInStream *stream; ++ int streamEndWasReached; ++ ++ UInt32 blockSize; ++ UInt32 keepSizeBefore; ++ UInt32 keepSizeAfter; ++ ++ UInt32 numHashBytes; ++ int directInput; ++ size_t directInputRem; ++ int btMode; ++ int bigHash; ++ UInt32 historySize; ++ UInt32 fixedHashSize; ++ UInt32 hashSizeSum; ++ UInt32 numSons; ++ SRes result; ++ UInt32 crc[256]; ++} CMatchFinder; ++ ++#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer) ++#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)]) ++ ++#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) ++ ++int MatchFinder_NeedMove(CMatchFinder *p); ++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p); ++void MatchFinder_MoveBlock(CMatchFinder *p); ++void MatchFinder_ReadIfRequired(CMatchFinder *p); ++ ++void MatchFinder_Construct(CMatchFinder *p); ++ ++/* Conditions: ++ historySize <= 3 GB ++ keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB ++*/ ++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, ++ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, ++ ISzAlloc *alloc); ++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); ++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems); ++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue); ++ ++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, ++ UInt32 *distances, UInt32 maxLen); ++ ++/* ++Conditions: ++ Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func. ++ Mf_GetPointerToCurrentPos_Func's result must be used only before any other function ++*/ ++ ++typedef void (*Mf_Init_Func)(void *object); ++typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index); ++typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object); ++typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object); ++typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances); ++typedef void (*Mf_Skip_Func)(void *object, UInt32); ++ ++typedef struct _IMatchFinder ++{ ++ Mf_Init_Func Init; ++ Mf_GetIndexByte_Func GetIndexByte; ++ Mf_GetNumAvailableBytes_Func GetNumAvailableBytes; ++ Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos; ++ Mf_GetMatches_Func GetMatches; ++ Mf_Skip_Func Skip; ++} IMatchFinder; ++ ++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); ++ ++void MatchFinder_Init(CMatchFinder *p); ++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); ++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); ++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); ++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzHash.h +@@ -0,0 +1,54 @@ ++/* LzHash.h -- HASH functions for LZ algorithms ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZ_HASH_H ++#define __LZ_HASH_H ++ ++#define kHash2Size (1 << 10) ++#define kHash3Size (1 << 16) ++#define kHash4Size (1 << 20) ++ ++#define kFix3HashSize (kHash2Size) ++#define kFix4HashSize (kHash2Size + kHash3Size) ++#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size) ++ ++#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8); ++ ++#define HASH3_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; } ++ ++#define HASH4_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; } ++ ++#define HASH5_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \ ++ hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \ ++ hash4Value &= (kHash4Size - 1); } ++ ++/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */ ++#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF; ++ ++ ++#define MT_HASH2_CALC \ ++ hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1); ++ ++#define MT_HASH3_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); } ++ ++#define MT_HASH4_CALC { \ ++ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ ++ hash2Value = temp & (kHash2Size - 1); \ ++ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ ++ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); } ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzmaDec.h +@@ -0,0 +1,231 @@ ++/* LzmaDec.h -- LZMA Decoder ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZMA_DEC_H ++#define __LZMA_DEC_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* #define _LZMA_PROB32 */ ++/* _LZMA_PROB32 can increase the speed on some CPUs, ++ but memory usage for CLzmaDec::probs will be doubled in that case */ ++ ++#ifdef _LZMA_PROB32 ++#define CLzmaProb UInt32 ++#else ++#define CLzmaProb UInt16 ++#endif ++ ++ ++/* ---------- LZMA Properties ---------- */ ++ ++#define LZMA_PROPS_SIZE 5 ++ ++typedef struct _CLzmaProps ++{ ++ unsigned lc, lp, pb; ++ UInt32 dicSize; ++} CLzmaProps; ++ ++/* LzmaProps_Decode - decodes properties ++Returns: ++ SZ_OK ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++*/ ++ ++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); ++ ++ ++/* ---------- LZMA Decoder state ---------- */ ++ ++/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case. ++ Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */ ++ ++#define LZMA_REQUIRED_INPUT_MAX 20 ++ ++typedef struct ++{ ++ CLzmaProps prop; ++ CLzmaProb *probs; ++ Byte *dic; ++ const Byte *buf; ++ UInt32 range, code; ++ SizeT dicPos; ++ SizeT dicBufSize; ++ UInt32 processedPos; ++ UInt32 checkDicSize; ++ unsigned state; ++ UInt32 reps[4]; ++ unsigned remainLen; ++ int needFlush; ++ int needInitState; ++ UInt32 numProbs; ++ unsigned tempBufSize; ++ Byte tempBuf[LZMA_REQUIRED_INPUT_MAX]; ++} CLzmaDec; ++ ++#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } ++ ++void LzmaDec_Init(CLzmaDec *p); ++ ++/* There are two types of LZMA streams: ++ 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. ++ 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ ++ ++typedef enum ++{ ++ LZMA_FINISH_ANY, /* finish at any point */ ++ LZMA_FINISH_END /* block must be finished at the end */ ++} ELzmaFinishMode; ++ ++/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!! ++ ++ You must use LZMA_FINISH_END, when you know that current output buffer ++ covers last bytes of block. In other cases you must use LZMA_FINISH_ANY. ++ ++ If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK, ++ and output value of destLen will be less than output buffer size limit. ++ You can check status result also. ++ ++ You can use multiple checks to test data integrity after full decompression: ++ 1) Check Result and "status" variable. ++ 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize. ++ 3) Check that output(srcLen) = compressedSize, if you know real compressedSize. ++ You must use correct finish mode in that case. */ ++ ++typedef enum ++{ ++ LZMA_STATUS_NOT_SPECIFIED, /* use main error code instead */ ++ LZMA_STATUS_FINISHED_WITH_MARK, /* stream was finished with end mark. */ ++ LZMA_STATUS_NOT_FINISHED, /* stream was not finished */ ++ LZMA_STATUS_NEEDS_MORE_INPUT, /* you must provide more input bytes */ ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK /* there is probability that stream was finished without end mark */ ++} ELzmaStatus; ++ ++/* ELzmaStatus is used only as output value for function call */ ++ ++ ++/* ---------- Interfaces ---------- */ ++ ++/* There are 3 levels of interfaces: ++ 1) Dictionary Interface ++ 2) Buffer Interface ++ 3) One Call Interface ++ You can select any of these interfaces, but don't mix functions from different ++ groups for same object. */ ++ ++ ++/* There are two variants to allocate state for Dictionary Interface: ++ 1) LzmaDec_Allocate / LzmaDec_Free ++ 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs ++ You can use variant 2, if you set dictionary buffer manually. ++ For Buffer Interface you must always use variant 1. ++ ++LzmaDec_Allocate* can return: ++ SZ_OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++*/ ++ ++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); ++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); ++ ++SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); ++void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); ++ ++/* ---------- Dictionary Interface ---------- */ ++ ++/* You can use it, if you want to eliminate the overhead for data copying from ++ dictionary to some other external buffer. ++ You must work with CLzmaDec variables directly in this interface. ++ ++ STEPS: ++ LzmaDec_Constr() ++ LzmaDec_Allocate() ++ for (each new stream) ++ { ++ LzmaDec_Init() ++ while (it needs more decompression) ++ { ++ LzmaDec_DecodeToDic() ++ use data from CLzmaDec::dic and update CLzmaDec::dicPos ++ } ++ } ++ LzmaDec_Free() ++*/ ++ ++/* LzmaDec_DecodeToDic ++ ++ The decoding to internal dictionary buffer (CLzmaDec::dic). ++ You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (dicLimit). ++ LZMA_FINISH_ANY - Decode just dicLimit bytes. ++ LZMA_FINISH_END - Stream must be finished after dicLimit. ++ ++Returns: ++ SZ_OK ++ status: ++ LZMA_STATUS_FINISHED_WITH_MARK ++ LZMA_STATUS_NOT_FINISHED ++ LZMA_STATUS_NEEDS_MORE_INPUT ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK ++ SZ_ERROR_DATA - Data error ++*/ ++ ++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, ++ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); ++ ++ ++/* ---------- Buffer Interface ---------- */ ++ ++/* It's zlib-like interface. ++ See LzmaDec_DecodeToDic description for information about STEPS and return results, ++ but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need ++ to work with CLzmaDec variables manually. ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (*destLen). ++ LZMA_FINISH_ANY - Decode just destLen bytes. ++ LZMA_FINISH_END - Stream must be finished after (*destLen). ++*/ ++ ++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, ++ const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); ++ ++ ++/* ---------- One Call Interface ---------- */ ++ ++/* LzmaDecode ++ ++finishMode: ++ It has meaning only if the decoding reaches output limit (*destLen). ++ LZMA_FINISH_ANY - Decode just destLen bytes. ++ LZMA_FINISH_END - Stream must be finished after (*destLen). ++ ++Returns: ++ SZ_OK ++ status: ++ LZMA_STATUS_FINISHED_WITH_MARK ++ LZMA_STATUS_NOT_FINISHED ++ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK ++ SZ_ERROR_DATA - Data error ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_UNSUPPORTED - Unsupported properties ++ SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src). ++*/ ++ ++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ++ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, ++ ELzmaStatus *status, ISzAlloc *alloc); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/LzmaEnc.h +@@ -0,0 +1,80 @@ ++/* LzmaEnc.h -- LZMA Encoder ++2009-02-07 : Igor Pavlov : Public domain */ ++ ++#ifndef __LZMA_ENC_H ++#define __LZMA_ENC_H ++ ++#include "Types.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define LZMA_PROPS_SIZE 5 ++ ++typedef struct _CLzmaEncProps ++{ ++ int level; /* 0 <= level <= 9 */ ++ UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version ++ (1 << 12) <= dictSize <= (1 << 30) for 64-bit version ++ default = (1 << 24) */ ++ int lc; /* 0 <= lc <= 8, default = 3 */ ++ int lp; /* 0 <= lp <= 4, default = 0 */ ++ int pb; /* 0 <= pb <= 4, default = 2 */ ++ int algo; /* 0 - fast, 1 - normal, default = 1 */ ++ int fb; /* 5 <= fb <= 273, default = 32 */ ++ int btMode; /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */ ++ int numHashBytes; /* 2, 3 or 4, default = 4 */ ++ UInt32 mc; /* 1 <= mc <= (1 << 30), default = 32 */ ++ unsigned writeEndMark; /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */ ++ int numThreads; /* 1 or 2, default = 2 */ ++} CLzmaEncProps; ++ ++void LzmaEncProps_Init(CLzmaEncProps *p); ++void LzmaEncProps_Normalize(CLzmaEncProps *p); ++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2); ++ ++ ++/* ---------- CLzmaEncHandle Interface ---------- */ ++ ++/* LzmaEnc_* functions can return the following exit codes: ++Returns: ++ SZ_OK - OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_PARAM - Incorrect paramater in props ++ SZ_ERROR_WRITE - Write callback error. ++ SZ_ERROR_PROGRESS - some break from progress callback ++ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) ++*/ ++ ++typedef void * CLzmaEncHandle; ++ ++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc); ++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); ++SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); ++SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); ++SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++ ++/* ---------- One Call Interface ---------- */ ++ ++/* LzmaEncode ++Return code: ++ SZ_OK - OK ++ SZ_ERROR_MEM - Memory allocation error ++ SZ_ERROR_PARAM - Incorrect paramater ++ SZ_ERROR_OUTPUT_EOF - output buffer overflow ++ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) ++*/ ++ ++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +--- /dev/null ++++ b/include/linux/lzma/Types.h +@@ -0,0 +1,226 @@ ++/* Types.h -- Basic types ++2009-11-23 : Igor Pavlov : Public domain */ ++ ++#ifndef __7Z_TYPES_H ++#define __7Z_TYPES_H ++ ++#include ++ ++#ifdef _WIN32 ++#include ++#endif ++ ++#ifndef EXTERN_C_BEGIN ++#ifdef __cplusplus ++#define EXTERN_C_BEGIN extern "C" { ++#define EXTERN_C_END } ++#else ++#define EXTERN_C_BEGIN ++#define EXTERN_C_END ++#endif ++#endif ++ ++EXTERN_C_BEGIN ++ ++#define SZ_OK 0 ++ ++#define SZ_ERROR_DATA 1 ++#define SZ_ERROR_MEM 2 ++#define SZ_ERROR_CRC 3 ++#define SZ_ERROR_UNSUPPORTED 4 ++#define SZ_ERROR_PARAM 5 ++#define SZ_ERROR_INPUT_EOF 6 ++#define SZ_ERROR_OUTPUT_EOF 7 ++#define SZ_ERROR_READ 8 ++#define SZ_ERROR_WRITE 9 ++#define SZ_ERROR_PROGRESS 10 ++#define SZ_ERROR_FAIL 11 ++#define SZ_ERROR_THREAD 12 ++ ++#define SZ_ERROR_ARCHIVE 16 ++#define SZ_ERROR_NO_ARCHIVE 17 ++ ++typedef int SRes; ++ ++#ifdef _WIN32 ++typedef DWORD WRes; ++#else ++typedef int WRes; ++#endif ++ ++#ifndef RINOK ++#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; } ++#endif ++ ++typedef unsigned char Byte; ++typedef short Int16; ++typedef unsigned short UInt16; ++ ++#ifdef _LZMA_UINT32_IS_ULONG ++typedef long Int32; ++typedef unsigned long UInt32; ++#else ++typedef int Int32; ++typedef unsigned int UInt32; ++#endif ++ ++#ifdef _SZ_NO_INT_64 ++ ++/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers. ++ NOTES: Some code will work incorrectly in that case! */ ++ ++typedef long Int64; ++typedef unsigned long UInt64; ++ ++#else ++ ++#if defined(_MSC_VER) || defined(__BORLANDC__) ++typedef __int64 Int64; ++typedef unsigned __int64 UInt64; ++#else ++typedef long long int Int64; ++typedef unsigned long long int UInt64; ++#endif ++ ++#endif ++ ++#ifdef _LZMA_NO_SYSTEM_SIZE_T ++typedef UInt32 SizeT; ++#else ++typedef size_t SizeT; ++#endif ++ ++typedef int Bool; ++#define True 1 ++#define False 0 ++ ++ ++#ifdef _WIN32 ++#define MY_STD_CALL __stdcall ++#else ++#define MY_STD_CALL ++#endif ++ ++#ifdef _MSC_VER ++ ++#if _MSC_VER >= 1300 ++#define MY_NO_INLINE __declspec(noinline) ++#else ++#define MY_NO_INLINE ++#endif ++ ++#define MY_CDECL __cdecl ++#define MY_FAST_CALL __fastcall ++ ++#else ++ ++#define MY_CDECL ++#define MY_FAST_CALL ++ ++#endif ++ ++ ++/* The following interfaces use first parameter as pointer to structure */ ++ ++typedef struct ++{ ++ SRes (*Read)(void *p, void *buf, size_t *size); ++ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. ++ (output(*size) < input(*size)) is allowed */ ++} ISeqInStream; ++ ++/* it can return SZ_ERROR_INPUT_EOF */ ++SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size); ++SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType); ++SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf); ++ ++typedef struct ++{ ++ size_t (*Write)(void *p, const void *buf, size_t size); ++ /* Returns: result - the number of actually written bytes. ++ (result < size) means error */ ++} ISeqOutStream; ++ ++typedef enum ++{ ++ SZ_SEEK_SET = 0, ++ SZ_SEEK_CUR = 1, ++ SZ_SEEK_END = 2 ++} ESzSeek; ++ ++typedef struct ++{ ++ SRes (*Read)(void *p, void *buf, size_t *size); /* same as ISeqInStream::Read */ ++ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); ++} ISeekInStream; ++ ++typedef struct ++{ ++ SRes (*Look)(void *p, void **buf, size_t *size); ++ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. ++ (output(*size) > input(*size)) is not allowed ++ (output(*size) < input(*size)) is allowed */ ++ SRes (*Skip)(void *p, size_t offset); ++ /* offset must be <= output(*size) of Look */ ++ ++ SRes (*Read)(void *p, void *buf, size_t *size); ++ /* reads directly (without buffer). It's same as ISeqInStream::Read */ ++ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); ++} ILookInStream; ++ ++SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size); ++SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset); ++ ++/* reads via ILookInStream::Read */ ++SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType); ++SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size); ++ ++#define LookToRead_BUF_SIZE (1 << 14) ++ ++typedef struct ++{ ++ ILookInStream s; ++ ISeekInStream *realStream; ++ size_t pos; ++ size_t size; ++ Byte buf[LookToRead_BUF_SIZE]; ++} CLookToRead; ++ ++void LookToRead_CreateVTable(CLookToRead *p, int lookahead); ++void LookToRead_Init(CLookToRead *p); ++ ++typedef struct ++{ ++ ISeqInStream s; ++ ILookInStream *realStream; ++} CSecToLook; ++ ++void SecToLook_CreateVTable(CSecToLook *p); ++ ++typedef struct ++{ ++ ISeqInStream s; ++ ILookInStream *realStream; ++} CSecToRead; ++ ++void SecToRead_CreateVTable(CSecToRead *p); ++ ++typedef struct ++{ ++ SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize); ++ /* Returns: result. (result != SZ_OK) means break. ++ Value (UInt64)(Int64)-1 for size means unknown value. */ ++} ICompressProgress; ++ ++typedef struct ++{ ++ void *(*Alloc)(void *p, size_t size); ++ void (*Free)(void *p, void *address); /* address can be 0 */ ++} ISzAlloc; ++ ++#define IAlloc_Alloc(p, size) (p)->Alloc((p), size) ++#define IAlloc_Free(p, a) (p)->Free((p), a) ++ ++EXTERN_C_END ++ ++#endif +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -239,6 +239,12 @@ config LZ4_DECOMPRESS + + source "lib/xz/Kconfig" + ++config LZMA_COMPRESS ++ tristate ++ ++config LZMA_DECOMPRESS ++ tristate ++ + # + # These all provide a common interface (hence the apparent duplication with + # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -2,6 +2,16 @@ + # Makefile for some libs needed in the kernel. + # + ++ifdef CONFIG_JFFS2_ZLIB ++ CONFIG_ZLIB_INFLATE:=y ++ CONFIG_ZLIB_DEFLATE:=y ++endif ++ ++ifdef CONFIG_JFFS2_LZMA ++ CONFIG_LZMA_DECOMPRESS:=y ++ CONFIG_LZMA_COMPRESS:=y ++endif ++ + ifdef CONFIG_FUNCTION_TRACER + ORIG_CFLAGS := $(KBUILD_CFLAGS) + KBUILD_CFLAGS = $(subst $(CC_FLAGS_FTRACE),,$(ORIG_CFLAGS)) +@@ -96,6 +106,8 @@ obj-$(CONFIG_LZ4HC_COMPRESS) += lz4/ + obj-$(CONFIG_LZ4_DECOMPRESS) += lz4/ + obj-$(CONFIG_XZ_DEC) += xz/ + obj-$(CONFIG_RAID6_PQ) += raid6/ ++obj-$(CONFIG_LZMA_COMPRESS) += lzma/ ++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ + + lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o + lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o +--- /dev/null ++++ b/lib/lzma/LzFind.c +@@ -0,0 +1,761 @@ ++/* LzFind.c -- Match finder for LZ algorithms ++2009-04-22 : Igor Pavlov : Public domain */ ++ ++#include ++ ++#include "LzFind.h" ++#include "LzHash.h" ++ ++#define kEmptyHashValue 0 ++#define kMaxValForNormalize ((UInt32)0xFFFFFFFF) ++#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */ ++#define kNormalizeMask (~(kNormalizeStepMin - 1)) ++#define kMaxHistorySize ((UInt32)3 << 30) ++ ++#define kStartMaxLen 3 ++ ++static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ if (!p->directInput) ++ { ++ alloc->Free(alloc, p->bufferBase); ++ p->bufferBase = 0; ++ } ++} ++ ++/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */ ++ ++static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) ++{ ++ UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; ++ if (p->directInput) ++ { ++ p->blockSize = blockSize; ++ return 1; ++ } ++ if (p->bufferBase == 0 || p->blockSize != blockSize) ++ { ++ LzInWindow_Free(p, alloc); ++ p->blockSize = blockSize; ++ p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize); ++ } ++ return (p->bufferBase != 0); ++} ++ ++Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } ++Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } ++ ++UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } ++ ++void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) ++{ ++ p->posLimit -= subValue; ++ p->pos -= subValue; ++ p->streamPos -= subValue; ++} ++ ++static void MatchFinder_ReadBlock(CMatchFinder *p) ++{ ++ if (p->streamEndWasReached || p->result != SZ_OK) ++ return; ++ if (p->directInput) ++ { ++ UInt32 curSize = 0xFFFFFFFF - p->streamPos; ++ if (curSize > p->directInputRem) ++ curSize = (UInt32)p->directInputRem; ++ p->directInputRem -= curSize; ++ p->streamPos += curSize; ++ if (p->directInputRem == 0) ++ p->streamEndWasReached = 1; ++ return; ++ } ++ for (;;) ++ { ++ Byte *dest = p->buffer + (p->streamPos - p->pos); ++ size_t size = (p->bufferBase + p->blockSize - dest); ++ if (size == 0) ++ return; ++ p->result = p->stream->Read(p->stream, dest, &size); ++ if (p->result != SZ_OK) ++ return; ++ if (size == 0) ++ { ++ p->streamEndWasReached = 1; ++ return; ++ } ++ p->streamPos += (UInt32)size; ++ if (p->streamPos - p->pos > p->keepSizeAfter) ++ return; ++ } ++} ++ ++void MatchFinder_MoveBlock(CMatchFinder *p) ++{ ++ memmove(p->bufferBase, ++ p->buffer - p->keepSizeBefore, ++ (size_t)(p->streamPos - p->pos + p->keepSizeBefore)); ++ p->buffer = p->bufferBase + p->keepSizeBefore; ++} ++ ++int MatchFinder_NeedMove(CMatchFinder *p) ++{ ++ if (p->directInput) ++ return 0; ++ /* if (p->streamEndWasReached) return 0; */ ++ return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); ++} ++ ++void MatchFinder_ReadIfRequired(CMatchFinder *p) ++{ ++ if (p->streamEndWasReached) ++ return; ++ if (p->keepSizeAfter >= p->streamPos - p->pos) ++ MatchFinder_ReadBlock(p); ++} ++ ++static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) ++{ ++ if (MatchFinder_NeedMove(p)) ++ MatchFinder_MoveBlock(p); ++ MatchFinder_ReadBlock(p); ++} ++ ++static void MatchFinder_SetDefaultSettings(CMatchFinder *p) ++{ ++ p->cutValue = 32; ++ p->btMode = 1; ++ p->numHashBytes = 4; ++ p->bigHash = 0; ++} ++ ++#define kCrcPoly 0xEDB88320 ++ ++void MatchFinder_Construct(CMatchFinder *p) ++{ ++ UInt32 i; ++ p->bufferBase = 0; ++ p->directInput = 0; ++ p->hash = 0; ++ MatchFinder_SetDefaultSettings(p); ++ ++ for (i = 0; i < 256; i++) ++ { ++ UInt32 r = i; ++ int j; ++ for (j = 0; j < 8; j++) ++ r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1)); ++ p->crc[i] = r; ++ } ++} ++ ++static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->hash); ++ p->hash = 0; ++} ++ ++void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc) ++{ ++ MatchFinder_FreeThisClassMemory(p, alloc); ++ LzInWindow_Free(p, alloc); ++} ++ ++static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc) ++{ ++ size_t sizeInBytes = (size_t)num * sizeof(CLzRef); ++ if (sizeInBytes / sizeof(CLzRef) != num) ++ return 0; ++ return (CLzRef *)alloc->Alloc(alloc, sizeInBytes); ++} ++ ++int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, ++ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, ++ ISzAlloc *alloc) ++{ ++ UInt32 sizeReserv; ++ if (historySize > kMaxHistorySize) ++ { ++ MatchFinder_Free(p, alloc); ++ return 0; ++ } ++ sizeReserv = historySize >> 1; ++ if (historySize > ((UInt32)2 << 30)) ++ sizeReserv = historySize >> 2; ++ sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19); ++ ++ p->keepSizeBefore = historySize + keepAddBufferBefore + 1; ++ p->keepSizeAfter = matchMaxLen + keepAddBufferAfter; ++ /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */ ++ if (LzInWindow_Create(p, sizeReserv, alloc)) ++ { ++ UInt32 newCyclicBufferSize = historySize + 1; ++ UInt32 hs; ++ p->matchMaxLen = matchMaxLen; ++ { ++ p->fixedHashSize = 0; ++ if (p->numHashBytes == 2) ++ hs = (1 << 16) - 1; ++ else ++ { ++ hs = historySize - 1; ++ hs |= (hs >> 1); ++ hs |= (hs >> 2); ++ hs |= (hs >> 4); ++ hs |= (hs >> 8); ++ hs >>= 1; ++ hs |= 0xFFFF; /* don't change it! It's required for Deflate */ ++ if (hs > (1 << 24)) ++ { ++ if (p->numHashBytes == 3) ++ hs = (1 << 24) - 1; ++ else ++ hs >>= 1; ++ } ++ } ++ p->hashMask = hs; ++ hs++; ++ if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size; ++ if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size; ++ if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size; ++ hs += p->fixedHashSize; ++ } ++ ++ { ++ UInt32 prevSize = p->hashSizeSum + p->numSons; ++ UInt32 newSize; ++ p->historySize = historySize; ++ p->hashSizeSum = hs; ++ p->cyclicBufferSize = newCyclicBufferSize; ++ p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize); ++ newSize = p->hashSizeSum + p->numSons; ++ if (p->hash != 0 && prevSize == newSize) ++ return 1; ++ MatchFinder_FreeThisClassMemory(p, alloc); ++ p->hash = AllocRefs(newSize, alloc); ++ if (p->hash != 0) ++ { ++ p->son = p->hash + p->hashSizeSum; ++ return 1; ++ } ++ } ++ } ++ MatchFinder_Free(p, alloc); ++ return 0; ++} ++ ++static void MatchFinder_SetLimits(CMatchFinder *p) ++{ ++ UInt32 limit = kMaxValForNormalize - p->pos; ++ UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos; ++ if (limit2 < limit) ++ limit = limit2; ++ limit2 = p->streamPos - p->pos; ++ if (limit2 <= p->keepSizeAfter) ++ { ++ if (limit2 > 0) ++ limit2 = 1; ++ } ++ else ++ limit2 -= p->keepSizeAfter; ++ if (limit2 < limit) ++ limit = limit2; ++ { ++ UInt32 lenLimit = p->streamPos - p->pos; ++ if (lenLimit > p->matchMaxLen) ++ lenLimit = p->matchMaxLen; ++ p->lenLimit = lenLimit; ++ } ++ p->posLimit = p->pos + limit; ++} ++ ++void MatchFinder_Init(CMatchFinder *p) ++{ ++ UInt32 i; ++ for (i = 0; i < p->hashSizeSum; i++) ++ p->hash[i] = kEmptyHashValue; ++ p->cyclicBufferPos = 0; ++ p->buffer = p->bufferBase; ++ p->pos = p->streamPos = p->cyclicBufferSize; ++ p->result = SZ_OK; ++ p->streamEndWasReached = 0; ++ MatchFinder_ReadBlock(p); ++ MatchFinder_SetLimits(p); ++} ++ ++static UInt32 MatchFinder_GetSubValue(CMatchFinder *p) ++{ ++ return (p->pos - p->historySize - 1) & kNormalizeMask; ++} ++ ++void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) ++{ ++ UInt32 i; ++ for (i = 0; i < numItems; i++) ++ { ++ UInt32 value = items[i]; ++ if (value <= subValue) ++ value = kEmptyHashValue; ++ else ++ value -= subValue; ++ items[i] = value; ++ } ++} ++ ++static void MatchFinder_Normalize(CMatchFinder *p) ++{ ++ UInt32 subValue = MatchFinder_GetSubValue(p); ++ MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons); ++ MatchFinder_ReduceOffsets(p, subValue); ++} ++ ++static void MatchFinder_CheckLimits(CMatchFinder *p) ++{ ++ if (p->pos == kMaxValForNormalize) ++ MatchFinder_Normalize(p); ++ if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos) ++ MatchFinder_CheckAndMoveAndRead(p); ++ if (p->cyclicBufferPos == p->cyclicBufferSize) ++ p->cyclicBufferPos = 0; ++ MatchFinder_SetLimits(p); ++} ++ ++static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, ++ UInt32 *distances, UInt32 maxLen) ++{ ++ son[_cyclicBufferPos] = curMatch; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ return distances; ++ { ++ const Byte *pb = cur - delta; ++ curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)]; ++ if (pb[maxLen] == cur[maxLen] && *pb == *cur) ++ { ++ UInt32 len = 0; ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ if (maxLen < len) ++ { ++ *distances++ = maxLen = len; ++ *distances++ = delta - 1; ++ if (len == lenLimit) ++ return distances; ++ } ++ } ++ } ++ } ++} ++ ++UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, ++ UInt32 *distances, UInt32 maxLen) ++{ ++ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; ++ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); ++ UInt32 len0 = 0, len1 = 0; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ { ++ *ptr0 = *ptr1 = kEmptyHashValue; ++ return distances; ++ } ++ { ++ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); ++ const Byte *pb = cur - delta; ++ UInt32 len = (len0 < len1 ? len0 : len1); ++ if (pb[len] == cur[len]) ++ { ++ if (++len != lenLimit && pb[len] == cur[len]) ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ if (maxLen < len) ++ { ++ *distances++ = maxLen = len; ++ *distances++ = delta - 1; ++ if (len == lenLimit) ++ { ++ *ptr1 = pair[0]; ++ *ptr0 = pair[1]; ++ return distances; ++ } ++ } ++ } ++ if (pb[len] < cur[len]) ++ { ++ *ptr1 = curMatch; ++ ptr1 = pair + 1; ++ curMatch = *ptr1; ++ len1 = len; ++ } ++ else ++ { ++ *ptr0 = curMatch; ++ ptr0 = pair; ++ curMatch = *ptr0; ++ len0 = len; ++ } ++ } ++ } ++} ++ ++static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue) ++{ ++ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; ++ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); ++ UInt32 len0 = 0, len1 = 0; ++ for (;;) ++ { ++ UInt32 delta = pos - curMatch; ++ if (cutValue-- == 0 || delta >= _cyclicBufferSize) ++ { ++ *ptr0 = *ptr1 = kEmptyHashValue; ++ return; ++ } ++ { ++ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); ++ const Byte *pb = cur - delta; ++ UInt32 len = (len0 < len1 ? len0 : len1); ++ if (pb[len] == cur[len]) ++ { ++ while (++len != lenLimit) ++ if (pb[len] != cur[len]) ++ break; ++ { ++ if (len == lenLimit) ++ { ++ *ptr1 = pair[0]; ++ *ptr0 = pair[1]; ++ return; ++ } ++ } ++ } ++ if (pb[len] < cur[len]) ++ { ++ *ptr1 = curMatch; ++ ptr1 = pair + 1; ++ curMatch = *ptr1; ++ len1 = len; ++ } ++ else ++ { ++ *ptr0 = curMatch; ++ ptr0 = pair; ++ curMatch = *ptr0; ++ len0 = len; ++ } ++ } ++ } ++} ++ ++#define MOVE_POS \ ++ ++p->cyclicBufferPos; \ ++ p->buffer++; \ ++ if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); ++ ++#define MOVE_POS_RET MOVE_POS return offset; ++ ++static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } ++ ++#define GET_MATCHES_HEADER2(minLen, ret_op) \ ++ UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ ++ lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ ++ cur = p->buffer; ++ ++#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0) ++#define SKIP_HEADER(minLen) GET_MATCHES_HEADER2(minLen, continue) ++ ++#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue ++ ++#define GET_MATCHES_FOOTER(offset, maxLen) \ ++ offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \ ++ distances + offset, maxLen) - distances); MOVE_POS_RET; ++ ++#define SKIP_FOOTER \ ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS; ++ ++static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(2) ++ HASH2_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = 0; ++ GET_MATCHES_FOOTER(offset, 1) ++} ++ ++UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = 0; ++ GET_MATCHES_FOOTER(offset, 2) ++} ++ ++static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, delta2, maxLen, offset; ++ GET_MATCHES_HEADER(3) ++ ++ HASH3_CALC; ++ ++ delta2 = p->pos - p->hash[hash2Value]; ++ curMatch = p->hash[kFix3HashSize + hashValue]; ++ ++ p->hash[hash2Value] = ++ p->hash[kFix3HashSize + hashValue] = p->pos; ++ ++ ++ maxLen = 2; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[0] = maxLen; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ if (maxLen == lenLimit) ++ { ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); ++ MOVE_POS_RET; ++ } ++ } ++ GET_MATCHES_FOOTER(offset, maxLen) ++} ++ ++static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; ++ GET_MATCHES_HEADER(4) ++ ++ HASH4_CALC; ++ ++ delta2 = p->pos - p->hash[ hash2Value]; ++ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ ++ maxLen = 1; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ distances[0] = maxLen = 2; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ } ++ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) ++ { ++ maxLen = 3; ++ distances[offset + 1] = delta3 - 1; ++ offset += 2; ++ delta2 = delta3; ++ } ++ if (offset != 0) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[offset - 2] = maxLen; ++ if (maxLen == lenLimit) ++ { ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); ++ MOVE_POS_RET; ++ } ++ } ++ if (maxLen < 3) ++ maxLen = 3; ++ GET_MATCHES_FOOTER(offset, maxLen) ++} ++ ++static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; ++ GET_MATCHES_HEADER(4) ++ ++ HASH4_CALC; ++ ++ delta2 = p->pos - p->hash[ hash2Value]; ++ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ ++ maxLen = 1; ++ offset = 0; ++ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) ++ { ++ distances[0] = maxLen = 2; ++ distances[1] = delta2 - 1; ++ offset = 2; ++ } ++ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) ++ { ++ maxLen = 3; ++ distances[offset + 1] = delta3 - 1; ++ offset += 2; ++ delta2 = delta3; ++ } ++ if (offset != 0) ++ { ++ for (; maxLen != lenLimit; maxLen++) ++ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) ++ break; ++ distances[offset - 2] = maxLen; ++ if (maxLen == lenLimit) ++ { ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS_RET; ++ } ++ } ++ if (maxLen < 3) ++ maxLen = 3; ++ offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), ++ distances + offset, maxLen) - (distances)); ++ MOVE_POS_RET ++} ++ ++UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) ++{ ++ UInt32 offset; ++ GET_MATCHES_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), ++ distances, 2) - (distances)); ++ MOVE_POS_RET ++} ++ ++static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(2) ++ HASH2_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value; ++ SKIP_HEADER(3) ++ HASH3_CALC; ++ curMatch = p->hash[kFix3HashSize + hashValue]; ++ p->hash[hash2Value] = ++ p->hash[kFix3HashSize + hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value, hash3Value; ++ SKIP_HEADER(4) ++ HASH4_CALC; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = p->pos; ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ SKIP_FOOTER ++ } ++ while (--num != 0); ++} ++ ++static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ UInt32 hash2Value, hash3Value; ++ SKIP_HEADER(4) ++ HASH4_CALC; ++ curMatch = p->hash[kFix4HashSize + hashValue]; ++ p->hash[ hash2Value] = ++ p->hash[kFix3HashSize + hash3Value] = ++ p->hash[kFix4HashSize + hashValue] = p->pos; ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS ++ } ++ while (--num != 0); ++} ++ ++void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) ++{ ++ do ++ { ++ SKIP_HEADER(3) ++ HASH_ZIP_CALC; ++ curMatch = p->hash[hashValue]; ++ p->hash[hashValue] = p->pos; ++ p->son[p->cyclicBufferPos] = curMatch; ++ MOVE_POS ++ } ++ while (--num != 0); ++} ++ ++void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) ++{ ++ vTable->Init = (Mf_Init_Func)MatchFinder_Init; ++ vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; ++ vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; ++ vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; ++ if (!p->btMode) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip; ++ } ++ else if (p->numHashBytes == 2) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip; ++ } ++ else if (p->numHashBytes == 3) ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip; ++ } ++ else ++ { ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; ++ } ++} +--- /dev/null ++++ b/lib/lzma/LzmaDec.c +@@ -0,0 +1,999 @@ ++/* LzmaDec.c -- LZMA Decoder ++2009-09-20 : Igor Pavlov : Public domain */ ++ ++#include "LzmaDec.h" ++ ++#include ++ ++#define kNumTopBits 24 ++#define kTopValue ((UInt32)1 << kNumTopBits) ++ ++#define kNumBitModelTotalBits 11 ++#define kBitModelTotal (1 << kNumBitModelTotalBits) ++#define kNumMoveBits 5 ++ ++#define RC_INIT_SIZE 5 ++ ++#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); } ++ ++#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) ++#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits)); ++#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits)); ++#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \ ++ { UPDATE_0(p); i = (i + i); A0; } else \ ++ { UPDATE_1(p); i = (i + i) + 1; A1; } ++#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;) ++ ++#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); } ++#define TREE_DECODE(probs, limit, i) \ ++ { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; } ++ ++/* #define _LZMA_SIZE_OPT */ ++ ++#ifdef _LZMA_SIZE_OPT ++#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i) ++#else ++#define TREE_6_DECODE(probs, i) \ ++ { i = 1; \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ TREE_GET_BIT(probs, i); \ ++ i -= 0x40; } ++#endif ++ ++#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); } ++ ++#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) ++#define UPDATE_0_CHECK range = bound; ++#define UPDATE_1_CHECK range -= bound; code -= bound; ++#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \ ++ { UPDATE_0_CHECK; i = (i + i); A0; } else \ ++ { UPDATE_1_CHECK; i = (i + i) + 1; A1; } ++#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;) ++#define TREE_DECODE_CHECK(probs, limit, i) \ ++ { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; } ++ ++ ++#define kNumPosBitsMax 4 ++#define kNumPosStatesMax (1 << kNumPosBitsMax) ++ ++#define kLenNumLowBits 3 ++#define kLenNumLowSymbols (1 << kLenNumLowBits) ++#define kLenNumMidBits 3 ++#define kLenNumMidSymbols (1 << kLenNumMidBits) ++#define kLenNumHighBits 8 ++#define kLenNumHighSymbols (1 << kLenNumHighBits) ++ ++#define LenChoice 0 ++#define LenChoice2 (LenChoice + 1) ++#define LenLow (LenChoice2 + 1) ++#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) ++#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) ++#define kNumLenProbs (LenHigh + kLenNumHighSymbols) ++ ++ ++#define kNumStates 12 ++#define kNumLitStates 7 ++ ++#define kStartPosModelIndex 4 ++#define kEndPosModelIndex 14 ++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) ++ ++#define kNumPosSlotBits 6 ++#define kNumLenToPosStates 4 ++ ++#define kNumAlignBits 4 ++#define kAlignTableSize (1 << kNumAlignBits) ++ ++#define kMatchMinLen 2 ++#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) ++ ++#define IsMatch 0 ++#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) ++#define IsRepG0 (IsRep + kNumStates) ++#define IsRepG1 (IsRepG0 + kNumStates) ++#define IsRepG2 (IsRepG1 + kNumStates) ++#define IsRep0Long (IsRepG2 + kNumStates) ++#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) ++#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) ++#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) ++#define LenCoder (Align + kAlignTableSize) ++#define RepLenCoder (LenCoder + kNumLenProbs) ++#define Literal (RepLenCoder + kNumLenProbs) ++ ++#define LZMA_BASE_SIZE 1846 ++#define LZMA_LIT_SIZE 768 ++ ++#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp))) ++ ++#if Literal != LZMA_BASE_SIZE ++StopCompilingDueBUG ++#endif ++ ++#define LZMA_DIC_MIN (1 << 12) ++ ++/* First LZMA-symbol is always decoded. ++And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization ++Out: ++ Result: ++ SZ_OK - OK ++ SZ_ERROR_DATA - Error ++ p->remainLen: ++ < kMatchSpecLenStart : normal remain ++ = kMatchSpecLenStart : finished ++ = kMatchSpecLenStart + 1 : Flush marker ++ = kMatchSpecLenStart + 2 : State Init Marker ++*/ ++ ++static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit) ++{ ++ CLzmaProb *probs = p->probs; ++ ++ unsigned state = p->state; ++ UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3]; ++ unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1; ++ unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1; ++ unsigned lc = p->prop.lc; ++ ++ Byte *dic = p->dic; ++ SizeT dicBufSize = p->dicBufSize; ++ SizeT dicPos = p->dicPos; ++ ++ UInt32 processedPos = p->processedPos; ++ UInt32 checkDicSize = p->checkDicSize; ++ unsigned len = 0; ++ ++ const Byte *buf = p->buf; ++ UInt32 range = p->range; ++ UInt32 code = p->code; ++ ++ do ++ { ++ CLzmaProb *prob; ++ UInt32 bound; ++ unsigned ttt; ++ unsigned posState = processedPos & pbMask; ++ ++ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0(prob) ++ { ++ unsigned symbol; ++ UPDATE_0(prob); ++ prob = probs + Literal; ++ if (checkDicSize != 0 || processedPos != 0) ++ prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + ++ (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc)))); ++ ++ if (state < kNumLitStates) ++ { ++ state -= (state < 4) ? state : 3; ++ symbol = 1; ++ do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100); ++ } ++ else ++ { ++ unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ unsigned offs = 0x100; ++ state -= (state < 10) ? 3 : 6; ++ symbol = 1; ++ do ++ { ++ unsigned bit; ++ CLzmaProb *probLit; ++ matchByte <<= 1; ++ bit = (matchByte & offs); ++ probLit = prob + offs + bit + symbol; ++ GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit) ++ } ++ while (symbol < 0x100); ++ } ++ dic[dicPos++] = (Byte)symbol; ++ processedPos++; ++ continue; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ prob = probs + IsRep + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ state += kNumStates; ++ prob = probs + LenCoder; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ if (checkDicSize == 0 && processedPos == 0) ++ return SZ_ERROR_DATA; ++ prob = probs + IsRepG0 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ dicPos++; ++ processedPos++; ++ state = state < kNumLitStates ? 9 : 11; ++ continue; ++ } ++ UPDATE_1(prob); ++ } ++ else ++ { ++ UInt32 distance; ++ UPDATE_1(prob); ++ prob = probs + IsRepG1 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ distance = rep1; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ prob = probs + IsRepG2 + state; ++ IF_BIT_0(prob) ++ { ++ UPDATE_0(prob); ++ distance = rep2; ++ } ++ else ++ { ++ UPDATE_1(prob); ++ distance = rep3; ++ rep3 = rep2; ++ } ++ rep2 = rep1; ++ } ++ rep1 = rep0; ++ rep0 = distance; ++ } ++ state = state < kNumLitStates ? 8 : 11; ++ prob = probs + RepLenCoder; ++ } ++ { ++ unsigned limit, offset; ++ CLzmaProb *probLen = prob + LenChoice; ++ IF_BIT_0(probLen) ++ { ++ UPDATE_0(probLen); ++ probLen = prob + LenLow + (posState << kLenNumLowBits); ++ offset = 0; ++ limit = (1 << kLenNumLowBits); ++ } ++ else ++ { ++ UPDATE_1(probLen); ++ probLen = prob + LenChoice2; ++ IF_BIT_0(probLen) ++ { ++ UPDATE_0(probLen); ++ probLen = prob + LenMid + (posState << kLenNumMidBits); ++ offset = kLenNumLowSymbols; ++ limit = (1 << kLenNumMidBits); ++ } ++ else ++ { ++ UPDATE_1(probLen); ++ probLen = prob + LenHigh; ++ offset = kLenNumLowSymbols + kLenNumMidSymbols; ++ limit = (1 << kLenNumHighBits); ++ } ++ } ++ TREE_DECODE(probLen, limit, len); ++ len += offset; ++ } ++ ++ if (state >= kNumStates) ++ { ++ UInt32 distance; ++ prob = probs + PosSlot + ++ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); ++ TREE_6_DECODE(prob, distance); ++ if (distance >= kStartPosModelIndex) ++ { ++ unsigned posSlot = (unsigned)distance; ++ int numDirectBits = (int)(((distance >> 1) - 1)); ++ distance = (2 | (distance & 1)); ++ if (posSlot < kEndPosModelIndex) ++ { ++ distance <<= numDirectBits; ++ prob = probs + SpecPos + distance - posSlot - 1; ++ { ++ UInt32 mask = 1; ++ unsigned i = 1; ++ do ++ { ++ GET_BIT2(prob + i, i, ; , distance |= mask); ++ mask <<= 1; ++ } ++ while (--numDirectBits != 0); ++ } ++ } ++ else ++ { ++ numDirectBits -= kNumAlignBits; ++ do ++ { ++ NORMALIZE ++ range >>= 1; ++ ++ { ++ UInt32 t; ++ code -= range; ++ t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */ ++ distance = (distance << 1) + (t + 1); ++ code += range & t; ++ } ++ /* ++ distance <<= 1; ++ if (code >= range) ++ { ++ code -= range; ++ distance |= 1; ++ } ++ */ ++ } ++ while (--numDirectBits != 0); ++ prob = probs + Align; ++ distance <<= kNumAlignBits; ++ { ++ unsigned i = 1; ++ GET_BIT2(prob + i, i, ; , distance |= 1); ++ GET_BIT2(prob + i, i, ; , distance |= 2); ++ GET_BIT2(prob + i, i, ; , distance |= 4); ++ GET_BIT2(prob + i, i, ; , distance |= 8); ++ } ++ if (distance == (UInt32)0xFFFFFFFF) ++ { ++ len += kMatchSpecLenStart; ++ state -= kNumStates; ++ break; ++ } ++ } ++ } ++ rep3 = rep2; ++ rep2 = rep1; ++ rep1 = rep0; ++ rep0 = distance + 1; ++ if (checkDicSize == 0) ++ { ++ if (distance >= processedPos) ++ return SZ_ERROR_DATA; ++ } ++ else if (distance >= checkDicSize) ++ return SZ_ERROR_DATA; ++ state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3; ++ } ++ ++ len += kMatchMinLen; ++ ++ if (limit == dicPos) ++ return SZ_ERROR_DATA; ++ { ++ SizeT rem = limit - dicPos; ++ unsigned curLen = ((rem < len) ? (unsigned)rem : len); ++ SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0); ++ ++ processedPos += curLen; ++ ++ len -= curLen; ++ if (pos + curLen <= dicBufSize) ++ { ++ Byte *dest = dic + dicPos; ++ ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos; ++ const Byte *lim = dest + curLen; ++ dicPos += curLen; ++ do ++ *(dest) = (Byte)*(dest + src); ++ while (++dest != lim); ++ } ++ else ++ { ++ do ++ { ++ dic[dicPos++] = dic[pos]; ++ if (++pos == dicBufSize) ++ pos = 0; ++ } ++ while (--curLen != 0); ++ } ++ } ++ } ++ } ++ while (dicPos < limit && buf < bufLimit); ++ NORMALIZE; ++ p->buf = buf; ++ p->range = range; ++ p->code = code; ++ p->remainLen = len; ++ p->dicPos = dicPos; ++ p->processedPos = processedPos; ++ p->reps[0] = rep0; ++ p->reps[1] = rep1; ++ p->reps[2] = rep2; ++ p->reps[3] = rep3; ++ p->state = state; ++ ++ return SZ_OK; ++} ++ ++static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit) ++{ ++ if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart) ++ { ++ Byte *dic = p->dic; ++ SizeT dicPos = p->dicPos; ++ SizeT dicBufSize = p->dicBufSize; ++ unsigned len = p->remainLen; ++ UInt32 rep0 = p->reps[0]; ++ if (limit - dicPos < len) ++ len = (unsigned)(limit - dicPos); ++ ++ if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len) ++ p->checkDicSize = p->prop.dicSize; ++ ++ p->processedPos += len; ++ p->remainLen -= len; ++ while (len-- != 0) ++ { ++ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; ++ dicPos++; ++ } ++ p->dicPos = dicPos; ++ } ++} ++ ++static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit) ++{ ++ do ++ { ++ SizeT limit2 = limit; ++ if (p->checkDicSize == 0) ++ { ++ UInt32 rem = p->prop.dicSize - p->processedPos; ++ if (limit - p->dicPos > rem) ++ limit2 = p->dicPos + rem; ++ } ++ RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit)); ++ if (p->processedPos >= p->prop.dicSize) ++ p->checkDicSize = p->prop.dicSize; ++ LzmaDec_WriteRem(p, limit); ++ } ++ while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart); ++ ++ if (p->remainLen > kMatchSpecLenStart) ++ { ++ p->remainLen = kMatchSpecLenStart; ++ } ++ return 0; ++} ++ ++typedef enum ++{ ++ DUMMY_ERROR, /* unexpected end of input stream */ ++ DUMMY_LIT, ++ DUMMY_MATCH, ++ DUMMY_REP ++} ELzmaDummy; ++ ++static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize) ++{ ++ UInt32 range = p->range; ++ UInt32 code = p->code; ++ const Byte *bufLimit = buf + inSize; ++ CLzmaProb *probs = p->probs; ++ unsigned state = p->state; ++ ELzmaDummy res; ++ ++ { ++ CLzmaProb *prob; ++ UInt32 bound; ++ unsigned ttt; ++ unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1); ++ ++ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK ++ ++ /* if (bufLimit - buf >= 7) return DUMMY_LIT; */ ++ ++ prob = probs + Literal; ++ if (p->checkDicSize != 0 || p->processedPos != 0) ++ prob += (LZMA_LIT_SIZE * ++ ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + ++ (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc)))); ++ ++ if (state < kNumLitStates) ++ { ++ unsigned symbol = 1; ++ do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100); ++ } ++ else ++ { ++ unsigned matchByte = p->dic[p->dicPos - p->reps[0] + ++ ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)]; ++ unsigned offs = 0x100; ++ unsigned symbol = 1; ++ do ++ { ++ unsigned bit; ++ CLzmaProb *probLit; ++ matchByte <<= 1; ++ bit = (matchByte & offs); ++ probLit = prob + offs + bit + symbol; ++ GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit) ++ } ++ while (symbol < 0x100); ++ } ++ res = DUMMY_LIT; ++ } ++ else ++ { ++ unsigned len; ++ UPDATE_1_CHECK; ++ ++ prob = probs + IsRep + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ state = 0; ++ prob = probs + LenCoder; ++ res = DUMMY_MATCH; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ res = DUMMY_REP; ++ prob = probs + IsRepG0 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ NORMALIZE_CHECK; ++ return DUMMY_REP; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ } ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ prob = probs + IsRepG1 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ prob = probs + IsRepG2 + state; ++ IF_BIT_0_CHECK(prob) ++ { ++ UPDATE_0_CHECK; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ } ++ } ++ } ++ state = kNumStates; ++ prob = probs + RepLenCoder; ++ } ++ { ++ unsigned limit, offset; ++ CLzmaProb *probLen = prob + LenChoice; ++ IF_BIT_0_CHECK(probLen) ++ { ++ UPDATE_0_CHECK; ++ probLen = prob + LenLow + (posState << kLenNumLowBits); ++ offset = 0; ++ limit = 1 << kLenNumLowBits; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ probLen = prob + LenChoice2; ++ IF_BIT_0_CHECK(probLen) ++ { ++ UPDATE_0_CHECK; ++ probLen = prob + LenMid + (posState << kLenNumMidBits); ++ offset = kLenNumLowSymbols; ++ limit = 1 << kLenNumMidBits; ++ } ++ else ++ { ++ UPDATE_1_CHECK; ++ probLen = prob + LenHigh; ++ offset = kLenNumLowSymbols + kLenNumMidSymbols; ++ limit = 1 << kLenNumHighBits; ++ } ++ } ++ TREE_DECODE_CHECK(probLen, limit, len); ++ len += offset; ++ } ++ ++ if (state < 4) ++ { ++ unsigned posSlot; ++ prob = probs + PosSlot + ++ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << ++ kNumPosSlotBits); ++ TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot); ++ if (posSlot >= kStartPosModelIndex) ++ { ++ int numDirectBits = ((posSlot >> 1) - 1); ++ ++ /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */ ++ ++ if (posSlot < kEndPosModelIndex) ++ { ++ prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1; ++ } ++ else ++ { ++ numDirectBits -= kNumAlignBits; ++ do ++ { ++ NORMALIZE_CHECK ++ range >>= 1; ++ code -= range & (((code - range) >> 31) - 1); ++ /* if (code >= range) code -= range; */ ++ } ++ while (--numDirectBits != 0); ++ prob = probs + Align; ++ numDirectBits = kNumAlignBits; ++ } ++ { ++ unsigned i = 1; ++ do ++ { ++ GET_BIT_CHECK(prob + i, i); ++ } ++ while (--numDirectBits != 0); ++ } ++ } ++ } ++ } ++ } ++ NORMALIZE_CHECK; ++ return res; ++} ++ ++ ++static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data) ++{ ++ p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]); ++ p->range = 0xFFFFFFFF; ++ p->needFlush = 0; ++} ++ ++void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) ++{ ++ p->needFlush = 1; ++ p->remainLen = 0; ++ p->tempBufSize = 0; ++ ++ if (initDic) ++ { ++ p->processedPos = 0; ++ p->checkDicSize = 0; ++ p->needInitState = 1; ++ } ++ if (initState) ++ p->needInitState = 1; ++} ++ ++void LzmaDec_Init(CLzmaDec *p) ++{ ++ p->dicPos = 0; ++ LzmaDec_InitDicAndState(p, True, True); ++} ++ ++static void LzmaDec_InitStateReal(CLzmaDec *p) ++{ ++ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp)); ++ UInt32 i; ++ CLzmaProb *probs = p->probs; ++ for (i = 0; i < numProbs; i++) ++ probs[i] = kBitModelTotal >> 1; ++ p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1; ++ p->state = 0; ++ p->needInitState = 0; ++} ++ ++SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, ++ ELzmaFinishMode finishMode, ELzmaStatus *status) ++{ ++ SizeT inSize = *srcLen; ++ (*srcLen) = 0; ++ LzmaDec_WriteRem(p, dicLimit); ++ ++ *status = LZMA_STATUS_NOT_SPECIFIED; ++ ++ while (p->remainLen != kMatchSpecLenStart) ++ { ++ int checkEndMarkNow; ++ ++ if (p->needFlush != 0) ++ { ++ for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--) ++ p->tempBuf[p->tempBufSize++] = *src++; ++ if (p->tempBufSize < RC_INIT_SIZE) ++ { ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (p->tempBuf[0] != 0) ++ return SZ_ERROR_DATA; ++ ++ LzmaDec_InitRc(p, p->tempBuf); ++ p->tempBufSize = 0; ++ } ++ ++ checkEndMarkNow = 0; ++ if (p->dicPos >= dicLimit) ++ { ++ if (p->remainLen == 0 && p->code == 0) ++ { ++ *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK; ++ return SZ_OK; ++ } ++ if (finishMode == LZMA_FINISH_ANY) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_OK; ++ } ++ if (p->remainLen != 0) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ checkEndMarkNow = 1; ++ } ++ ++ if (p->needInitState) ++ LzmaDec_InitStateReal(p); ++ ++ if (p->tempBufSize == 0) ++ { ++ SizeT processed; ++ const Byte *bufLimit; ++ if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) ++ { ++ int dummyRes = LzmaDec_TryDummy(p, src, inSize); ++ if (dummyRes == DUMMY_ERROR) ++ { ++ memcpy(p->tempBuf, src, inSize); ++ p->tempBufSize = (unsigned)inSize; ++ (*srcLen) += inSize; ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ bufLimit = src; ++ } ++ else ++ bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX; ++ p->buf = src; ++ if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0) ++ return SZ_ERROR_DATA; ++ processed = (SizeT)(p->buf - src); ++ (*srcLen) += processed; ++ src += processed; ++ inSize -= processed; ++ } ++ else ++ { ++ unsigned rem = p->tempBufSize, lookAhead = 0; ++ while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize) ++ p->tempBuf[rem++] = src[lookAhead++]; ++ p->tempBufSize = rem; ++ if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) ++ { ++ int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem); ++ if (dummyRes == DUMMY_ERROR) ++ { ++ (*srcLen) += lookAhead; ++ *status = LZMA_STATUS_NEEDS_MORE_INPUT; ++ return SZ_OK; ++ } ++ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) ++ { ++ *status = LZMA_STATUS_NOT_FINISHED; ++ return SZ_ERROR_DATA; ++ } ++ } ++ p->buf = p->tempBuf; ++ if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0) ++ return SZ_ERROR_DATA; ++ lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf)); ++ (*srcLen) += lookAhead; ++ src += lookAhead; ++ inSize -= lookAhead; ++ p->tempBufSize = 0; ++ } ++ } ++ if (p->code == 0) ++ *status = LZMA_STATUS_FINISHED_WITH_MARK; ++ return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; ++} ++ ++SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) ++{ ++ SizeT outSize = *destLen; ++ SizeT inSize = *srcLen; ++ *srcLen = *destLen = 0; ++ for (;;) ++ { ++ SizeT inSizeCur = inSize, outSizeCur, dicPos; ++ ELzmaFinishMode curFinishMode; ++ SRes res; ++ if (p->dicPos == p->dicBufSize) ++ p->dicPos = 0; ++ dicPos = p->dicPos; ++ if (outSize > p->dicBufSize - dicPos) ++ { ++ outSizeCur = p->dicBufSize; ++ curFinishMode = LZMA_FINISH_ANY; ++ } ++ else ++ { ++ outSizeCur = dicPos + outSize; ++ curFinishMode = finishMode; ++ } ++ ++ res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); ++ src += inSizeCur; ++ inSize -= inSizeCur; ++ *srcLen += inSizeCur; ++ outSizeCur = p->dicPos - dicPos; ++ memcpy(dest, p->dic + dicPos, outSizeCur); ++ dest += outSizeCur; ++ outSize -= outSizeCur; ++ *destLen += outSizeCur; ++ if (res != 0) ++ return res; ++ if (outSizeCur == 0 || outSize == 0) ++ return SZ_OK; ++ } ++} ++ ++void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->probs); ++ p->probs = 0; ++} ++ ++static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->dic); ++ p->dic = 0; ++} ++ ++void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) ++{ ++ LzmaDec_FreeProbs(p, alloc); ++ LzmaDec_FreeDict(p, alloc); ++} ++ ++SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) ++{ ++ UInt32 dicSize; ++ Byte d; ++ ++ if (size < LZMA_PROPS_SIZE) ++ return SZ_ERROR_UNSUPPORTED; ++ else ++ dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24); ++ ++ if (dicSize < LZMA_DIC_MIN) ++ dicSize = LZMA_DIC_MIN; ++ p->dicSize = dicSize; ++ ++ d = data[0]; ++ if (d >= (9 * 5 * 5)) ++ return SZ_ERROR_UNSUPPORTED; ++ ++ p->lc = d % 9; ++ d /= 9; ++ p->pb = d / 5; ++ p->lp = d % 5; ++ ++ return SZ_OK; ++} ++ ++static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc) ++{ ++ UInt32 numProbs = LzmaProps_GetNumProbs(propNew); ++ if (p->probs == 0 || numProbs != p->numProbs) ++ { ++ LzmaDec_FreeProbs(p, alloc); ++ p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb)); ++ p->numProbs = numProbs; ++ if (p->probs == 0) ++ return SZ_ERROR_MEM; ++ } ++ return SZ_OK; ++} ++ ++SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++{ ++ CLzmaProps propNew; ++ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); ++ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); ++ p->prop = propNew; ++ return SZ_OK; ++} ++ ++SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++{ ++ CLzmaProps propNew; ++ SizeT dicBufSize; ++ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); ++ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); ++ dicBufSize = propNew.dicSize; ++ if (p->dic == 0 || dicBufSize != p->dicBufSize) ++ { ++ LzmaDec_FreeDict(p, alloc); ++ p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); ++ if (p->dic == 0) ++ { ++ LzmaDec_FreeProbs(p, alloc); ++ return SZ_ERROR_MEM; ++ } ++ } ++ p->dicBufSize = dicBufSize; ++ p->prop = propNew; ++ return SZ_OK; ++} ++ ++SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ++ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, ++ ELzmaStatus *status, ISzAlloc *alloc) ++{ ++ CLzmaDec p; ++ SRes res; ++ SizeT inSize = *srcLen; ++ SizeT outSize = *destLen; ++ *srcLen = *destLen = 0; ++ if (inSize < RC_INIT_SIZE) ++ return SZ_ERROR_INPUT_EOF; ++ ++ LzmaDec_Construct(&p); ++ res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc); ++ if (res != 0) ++ return res; ++ p.dic = dest; ++ p.dicBufSize = outSize; ++ ++ LzmaDec_Init(&p); ++ ++ *srcLen = inSize; ++ res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status); ++ ++ if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT) ++ res = SZ_ERROR_INPUT_EOF; ++ ++ (*destLen) = p.dicPos; ++ LzmaDec_FreeProbs(&p, alloc); ++ return res; ++} +--- /dev/null ++++ b/lib/lzma/LzmaEnc.c +@@ -0,0 +1,2271 @@ ++/* LzmaEnc.c -- LZMA Encoder ++2009-11-24 : Igor Pavlov : Public domain */ ++ ++#include ++ ++/* #define SHOW_STAT */ ++/* #define SHOW_STAT2 */ ++ ++#if defined(SHOW_STAT) || defined(SHOW_STAT2) ++#include ++#endif ++ ++#include "LzmaEnc.h" ++ ++/* disable MT */ ++#define _7ZIP_ST ++ ++#include "LzFind.h" ++#ifndef _7ZIP_ST ++#include "LzFindMt.h" ++#endif ++ ++#ifdef SHOW_STAT ++static int ttt = 0; ++#endif ++ ++#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1) ++ ++#define kBlockSize (9 << 10) ++#define kUnpackBlockSize (1 << 18) ++#define kMatchArraySize (1 << 21) ++#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX) ++ ++#define kNumMaxDirectBits (31) ++ ++#define kNumTopBits 24 ++#define kTopValue ((UInt32)1 << kNumTopBits) ++ ++#define kNumBitModelTotalBits 11 ++#define kBitModelTotal (1 << kNumBitModelTotalBits) ++#define kNumMoveBits 5 ++#define kProbInitValue (kBitModelTotal >> 1) ++ ++#define kNumMoveReducingBits 4 ++#define kNumBitPriceShiftBits 4 ++#define kBitPrice (1 << kNumBitPriceShiftBits) ++ ++void LzmaEncProps_Init(CLzmaEncProps *p) ++{ ++ p->level = 5; ++ p->dictSize = p->mc = 0; ++ p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1; ++ p->writeEndMark = 0; ++} ++ ++void LzmaEncProps_Normalize(CLzmaEncProps *p) ++{ ++ int level = p->level; ++ if (level < 0) level = 5; ++ p->level = level; ++ if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26))); ++ if (p->lc < 0) p->lc = 3; ++ if (p->lp < 0) p->lp = 0; ++ if (p->pb < 0) p->pb = 2; ++ if (p->algo < 0) p->algo = (level < 5 ? 0 : 1); ++ if (p->fb < 0) p->fb = (level < 7 ? 32 : 64); ++ if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1); ++ if (p->numHashBytes < 0) p->numHashBytes = 4; ++ if (p->mc == 0) p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1); ++ if (p->numThreads < 0) ++ p->numThreads = ++ #ifndef _7ZIP_ST ++ ((p->btMode && p->algo) ? 2 : 1); ++ #else ++ 1; ++ #endif ++} ++ ++UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) ++{ ++ CLzmaEncProps props = *props2; ++ LzmaEncProps_Normalize(&props); ++ return props.dictSize; ++} ++ ++/* #define LZMA_LOG_BSR */ ++/* Define it for Intel's CPU */ ++ ++ ++#ifdef LZMA_LOG_BSR ++ ++#define kDicLogSizeMaxCompress 30 ++ ++#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } ++ ++UInt32 GetPosSlot1(UInt32 pos) ++{ ++ UInt32 res; ++ BSR2_RET(pos, res); ++ return res; ++} ++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } ++#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); } ++ ++#else ++ ++#define kNumLogBits (9 + (int)sizeof(size_t) / 2) ++#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) ++ ++void LzmaEnc_FastPosInit(Byte *g_FastPos) ++{ ++ int c = 2, slotFast; ++ g_FastPos[0] = 0; ++ g_FastPos[1] = 1; ++ ++ for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++) ++ { ++ UInt32 k = (1 << ((slotFast >> 1) - 1)); ++ UInt32 j; ++ for (j = 0; j < k; j++, c++) ++ g_FastPos[c] = (Byte)slotFast; ++ } ++} ++ ++#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \ ++ (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \ ++ res = p->g_FastPos[pos >> i] + (i * 2); } ++/* ++#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \ ++ p->g_FastPos[pos >> 6] + 12 : \ ++ p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; } ++*/ ++ ++#define GetPosSlot1(pos) p->g_FastPos[pos] ++#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } ++#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); } ++ ++#endif ++ ++ ++#define LZMA_NUM_REPS 4 ++ ++typedef unsigned CState; ++ ++typedef struct ++{ ++ UInt32 price; ++ ++ CState state; ++ int prev1IsChar; ++ int prev2; ++ ++ UInt32 posPrev2; ++ UInt32 backPrev2; ++ ++ UInt32 posPrev; ++ UInt32 backPrev; ++ UInt32 backs[LZMA_NUM_REPS]; ++} COptimal; ++ ++#define kNumOpts (1 << 12) ++ ++#define kNumLenToPosStates 4 ++#define kNumPosSlotBits 6 ++#define kDicLogSizeMin 0 ++#define kDicLogSizeMax 32 ++#define kDistTableSizeMax (kDicLogSizeMax * 2) ++ ++ ++#define kNumAlignBits 4 ++#define kAlignTableSize (1 << kNumAlignBits) ++#define kAlignMask (kAlignTableSize - 1) ++ ++#define kStartPosModelIndex 4 ++#define kEndPosModelIndex 14 ++#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex) ++ ++#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) ++ ++#ifdef _LZMA_PROB32 ++#define CLzmaProb UInt32 ++#else ++#define CLzmaProb UInt16 ++#endif ++ ++#define LZMA_PB_MAX 4 ++#define LZMA_LC_MAX 8 ++#define LZMA_LP_MAX 4 ++ ++#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX) ++ ++ ++#define kLenNumLowBits 3 ++#define kLenNumLowSymbols (1 << kLenNumLowBits) ++#define kLenNumMidBits 3 ++#define kLenNumMidSymbols (1 << kLenNumMidBits) ++#define kLenNumHighBits 8 ++#define kLenNumHighSymbols (1 << kLenNumHighBits) ++ ++#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) ++ ++#define LZMA_MATCH_LEN_MIN 2 ++#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1) ++ ++#define kNumStates 12 ++ ++typedef struct ++{ ++ CLzmaProb choice; ++ CLzmaProb choice2; ++ CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits]; ++ CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits]; ++ CLzmaProb high[kLenNumHighSymbols]; ++} CLenEnc; ++ ++typedef struct ++{ ++ CLenEnc p; ++ UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal]; ++ UInt32 tableSize; ++ UInt32 counters[LZMA_NUM_PB_STATES_MAX]; ++} CLenPriceEnc; ++ ++typedef struct ++{ ++ UInt32 range; ++ Byte cache; ++ UInt64 low; ++ UInt64 cacheSize; ++ Byte *buf; ++ Byte *bufLim; ++ Byte *bufBase; ++ ISeqOutStream *outStream; ++ UInt64 processed; ++ SRes res; ++} CRangeEnc; ++ ++typedef struct ++{ ++ CLzmaProb *litProbs; ++ ++ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ CLzmaProb isRep[kNumStates]; ++ CLzmaProb isRepG0[kNumStates]; ++ CLzmaProb isRepG1[kNumStates]; ++ CLzmaProb isRepG2[kNumStates]; ++ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ ++ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; ++ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; ++ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; ++ ++ CLenPriceEnc lenEnc; ++ CLenPriceEnc repLenEnc; ++ ++ UInt32 reps[LZMA_NUM_REPS]; ++ UInt32 state; ++} CSaveState; ++ ++typedef struct ++{ ++ IMatchFinder matchFinder; ++ void *matchFinderObj; ++ ++ #ifndef _7ZIP_ST ++ Bool mtMode; ++ CMatchFinderMt matchFinderMt; ++ #endif ++ ++ CMatchFinder matchFinderBase; ++ ++ #ifndef _7ZIP_ST ++ Byte pad[128]; ++ #endif ++ ++ UInt32 optimumEndIndex; ++ UInt32 optimumCurrentIndex; ++ ++ UInt32 longestMatchLength; ++ UInt32 numPairs; ++ UInt32 numAvail; ++ COptimal opt[kNumOpts]; ++ ++ #ifndef LZMA_LOG_BSR ++ Byte g_FastPos[1 << kNumLogBits]; ++ #endif ++ ++ UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits]; ++ UInt32 matches[LZMA_MATCH_LEN_MAX * 2 + 2 + 1]; ++ UInt32 numFastBytes; ++ UInt32 additionalOffset; ++ UInt32 reps[LZMA_NUM_REPS]; ++ UInt32 state; ++ ++ UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax]; ++ UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances]; ++ UInt32 alignPrices[kAlignTableSize]; ++ UInt32 alignPriceCount; ++ ++ UInt32 distTableSize; ++ ++ unsigned lc, lp, pb; ++ unsigned lpMask, pbMask; ++ ++ CLzmaProb *litProbs; ++ ++ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ CLzmaProb isRep[kNumStates]; ++ CLzmaProb isRepG0[kNumStates]; ++ CLzmaProb isRepG1[kNumStates]; ++ CLzmaProb isRepG2[kNumStates]; ++ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; ++ ++ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; ++ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; ++ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; ++ ++ CLenPriceEnc lenEnc; ++ CLenPriceEnc repLenEnc; ++ ++ unsigned lclp; ++ ++ Bool fastMode; ++ ++ CRangeEnc rc; ++ ++ Bool writeEndMark; ++ UInt64 nowPos64; ++ UInt32 matchPriceCount; ++ Bool finished; ++ Bool multiThread; ++ ++ SRes result; ++ UInt32 dictSize; ++ UInt32 matchFinderCycles; ++ ++ int needInit; ++ ++ CSaveState saveState; ++} CLzmaEnc; ++ ++void LzmaEnc_SaveState(CLzmaEncHandle pp) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ CSaveState *dest = &p->saveState; ++ int i; ++ dest->lenEnc = p->lenEnc; ++ dest->repLenEnc = p->repLenEnc; ++ dest->state = p->state; ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); ++ memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); ++ } ++ for (i = 0; i < kNumLenToPosStates; i++) ++ memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); ++ memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); ++ memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); ++ memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); ++ memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); ++ memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); ++ memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); ++ memcpy(dest->reps, p->reps, sizeof(p->reps)); ++ memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb)); ++} ++ ++void LzmaEnc_RestoreState(CLzmaEncHandle pp) ++{ ++ CLzmaEnc *dest = (CLzmaEnc *)pp; ++ const CSaveState *p = &dest->saveState; ++ int i; ++ dest->lenEnc = p->lenEnc; ++ dest->repLenEnc = p->repLenEnc; ++ dest->state = p->state; ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); ++ memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); ++ } ++ for (i = 0; i < kNumLenToPosStates; i++) ++ memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); ++ memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); ++ memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); ++ memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); ++ memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); ++ memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); ++ memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); ++ memcpy(dest->reps, p->reps, sizeof(p->reps)); ++ memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb)); ++} ++ ++SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ CLzmaEncProps props = *props2; ++ LzmaEncProps_Normalize(&props); ++ ++ if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX || ++ props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30)) ++ return SZ_ERROR_PARAM; ++ p->dictSize = props.dictSize; ++ p->matchFinderCycles = props.mc; ++ { ++ unsigned fb = props.fb; ++ if (fb < 5) ++ fb = 5; ++ if (fb > LZMA_MATCH_LEN_MAX) ++ fb = LZMA_MATCH_LEN_MAX; ++ p->numFastBytes = fb; ++ } ++ p->lc = props.lc; ++ p->lp = props.lp; ++ p->pb = props.pb; ++ p->fastMode = (props.algo == 0); ++ p->matchFinderBase.btMode = props.btMode; ++ { ++ UInt32 numHashBytes = 4; ++ if (props.btMode) ++ { ++ if (props.numHashBytes < 2) ++ numHashBytes = 2; ++ else if (props.numHashBytes < 4) ++ numHashBytes = props.numHashBytes; ++ } ++ p->matchFinderBase.numHashBytes = numHashBytes; ++ } ++ ++ p->matchFinderBase.cutValue = props.mc; ++ ++ p->writeEndMark = props.writeEndMark; ++ ++ #ifndef _7ZIP_ST ++ /* ++ if (newMultiThread != _multiThread) ++ { ++ ReleaseMatchFinder(); ++ _multiThread = newMultiThread; ++ } ++ */ ++ p->multiThread = (props.numThreads > 1); ++ #endif ++ ++ return SZ_OK; ++} ++ ++static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 4, 5}; ++static const int kMatchNextStates[kNumStates] = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10}; ++static const int kRepNextStates[kNumStates] = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11}; ++static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11}; ++ ++#define IsCharState(s) ((s) < 7) ++ ++#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1) ++ ++#define kInfinityPrice (1 << 30) ++ ++static void RangeEnc_Construct(CRangeEnc *p) ++{ ++ p->outStream = 0; ++ p->bufBase = 0; ++} ++ ++#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize) ++ ++#define RC_BUF_SIZE (1 << 16) ++static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc) ++{ ++ if (p->bufBase == 0) ++ { ++ p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE); ++ if (p->bufBase == 0) ++ return 0; ++ p->bufLim = p->bufBase + RC_BUF_SIZE; ++ } ++ return 1; ++} ++ ++static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->bufBase); ++ p->bufBase = 0; ++} ++ ++static void RangeEnc_Init(CRangeEnc *p) ++{ ++ /* Stream.Init(); */ ++ p->low = 0; ++ p->range = 0xFFFFFFFF; ++ p->cacheSize = 1; ++ p->cache = 0; ++ ++ p->buf = p->bufBase; ++ ++ p->processed = 0; ++ p->res = SZ_OK; ++} ++ ++static void RangeEnc_FlushStream(CRangeEnc *p) ++{ ++ size_t num; ++ if (p->res != SZ_OK) ++ return; ++ num = p->buf - p->bufBase; ++ if (num != p->outStream->Write(p->outStream, p->bufBase, num)) ++ p->res = SZ_ERROR_WRITE; ++ p->processed += num; ++ p->buf = p->bufBase; ++} ++ ++static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p) ++{ ++ if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0) ++ { ++ Byte temp = p->cache; ++ do ++ { ++ Byte *buf = p->buf; ++ *buf++ = (Byte)(temp + (Byte)(p->low >> 32)); ++ p->buf = buf; ++ if (buf == p->bufLim) ++ RangeEnc_FlushStream(p); ++ temp = 0xFF; ++ } ++ while (--p->cacheSize != 0); ++ p->cache = (Byte)((UInt32)p->low >> 24); ++ } ++ p->cacheSize++; ++ p->low = (UInt32)p->low << 8; ++} ++ ++static void RangeEnc_FlushData(CRangeEnc *p) ++{ ++ int i; ++ for (i = 0; i < 5; i++) ++ RangeEnc_ShiftLow(p); ++} ++ ++static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits) ++{ ++ do ++ { ++ p->range >>= 1; ++ p->low += p->range & (0 - ((value >> --numBits) & 1)); ++ if (p->range < kTopValue) ++ { ++ p->range <<= 8; ++ RangeEnc_ShiftLow(p); ++ } ++ } ++ while (numBits != 0); ++} ++ ++static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol) ++{ ++ UInt32 ttt = *prob; ++ UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt; ++ if (symbol == 0) ++ { ++ p->range = newBound; ++ ttt += (kBitModelTotal - ttt) >> kNumMoveBits; ++ } ++ else ++ { ++ p->low += newBound; ++ p->range -= newBound; ++ ttt -= ttt >> kNumMoveBits; ++ } ++ *prob = (CLzmaProb)ttt; ++ if (p->range < kTopValue) ++ { ++ p->range <<= 8; ++ RangeEnc_ShiftLow(p); ++ } ++} ++ ++static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol) ++{ ++ symbol |= 0x100; ++ do ++ { ++ RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1); ++ symbol <<= 1; ++ } ++ while (symbol < 0x10000); ++} ++ ++static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte) ++{ ++ UInt32 offs = 0x100; ++ symbol |= 0x100; ++ do ++ { ++ matchByte <<= 1; ++ RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1); ++ symbol <<= 1; ++ offs &= ~(matchByte ^ symbol); ++ } ++ while (symbol < 0x10000); ++} ++ ++void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) ++{ ++ UInt32 i; ++ for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) ++ { ++ const int kCyclesBits = kNumBitPriceShiftBits; ++ UInt32 w = i; ++ UInt32 bitCount = 0; ++ int j; ++ for (j = 0; j < kCyclesBits; j++) ++ { ++ w = w * w; ++ bitCount <<= 1; ++ while (w >= ((UInt32)1 << 16)) ++ { ++ w >>= 1; ++ bitCount++; ++ } ++ } ++ ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount); ++ } ++} ++ ++ ++#define GET_PRICE(prob, symbol) \ ++ p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; ++ ++#define GET_PRICEa(prob, symbol) \ ++ ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; ++ ++#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits] ++#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] ++ ++#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits] ++#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] ++ ++static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ symbol |= 0x100; ++ do ++ { ++ price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1); ++ symbol <<= 1; ++ } ++ while (symbol < 0x10000); ++ return price; ++} ++ ++static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ UInt32 offs = 0x100; ++ symbol |= 0x100; ++ do ++ { ++ matchByte <<= 1; ++ price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1); ++ symbol <<= 1; ++ offs &= ~(matchByte ^ symbol); ++ } ++ while (symbol < 0x10000); ++ return price; ++} ++ ++ ++static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) ++{ ++ UInt32 m = 1; ++ int i; ++ for (i = numBitLevels; i != 0;) ++ { ++ UInt32 bit; ++ i--; ++ bit = (symbol >> i) & 1; ++ RangeEnc_EncodeBit(rc, probs + m, bit); ++ m = (m << 1) | bit; ++ } ++} ++ ++static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) ++{ ++ UInt32 m = 1; ++ int i; ++ for (i = 0; i < numBitLevels; i++) ++ { ++ UInt32 bit = symbol & 1; ++ RangeEnc_EncodeBit(rc, probs + m, bit); ++ m = (m << 1) | bit; ++ symbol >>= 1; ++ } ++} ++ ++static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ symbol |= (1 << numBitLevels); ++ while (symbol != 1) ++ { ++ price += GET_PRICEa(probs[symbol >> 1], symbol & 1); ++ symbol >>= 1; ++ } ++ return price; ++} ++ ++static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) ++{ ++ UInt32 price = 0; ++ UInt32 m = 1; ++ int i; ++ for (i = numBitLevels; i != 0; i--) ++ { ++ UInt32 bit = symbol & 1; ++ symbol >>= 1; ++ price += GET_PRICEa(probs[m], bit); ++ m = (m << 1) | bit; ++ } ++ return price; ++} ++ ++ ++static void LenEnc_Init(CLenEnc *p) ++{ ++ unsigned i; ++ p->choice = p->choice2 = kProbInitValue; ++ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++) ++ p->low[i] = kProbInitValue; ++ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++) ++ p->mid[i] = kProbInitValue; ++ for (i = 0; i < kLenNumHighSymbols; i++) ++ p->high[i] = kProbInitValue; ++} ++ ++static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState) ++{ ++ if (symbol < kLenNumLowSymbols) ++ { ++ RangeEnc_EncodeBit(rc, &p->choice, 0); ++ RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol); ++ } ++ else ++ { ++ RangeEnc_EncodeBit(rc, &p->choice, 1); ++ if (symbol < kLenNumLowSymbols + kLenNumMidSymbols) ++ { ++ RangeEnc_EncodeBit(rc, &p->choice2, 0); ++ RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols); ++ } ++ else ++ { ++ RangeEnc_EncodeBit(rc, &p->choice2, 1); ++ RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols); ++ } ++ } ++} ++ ++static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices) ++{ ++ UInt32 a0 = GET_PRICE_0a(p->choice); ++ UInt32 a1 = GET_PRICE_1a(p->choice); ++ UInt32 b0 = a1 + GET_PRICE_0a(p->choice2); ++ UInt32 b1 = a1 + GET_PRICE_1a(p->choice2); ++ UInt32 i = 0; ++ for (i = 0; i < kLenNumLowSymbols; i++) ++ { ++ if (i >= numSymbols) ++ return; ++ prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices); ++ } ++ for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++) ++ { ++ if (i >= numSymbols) ++ return; ++ prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices); ++ } ++ for (; i < numSymbols; i++) ++ prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices); ++} ++ ++static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices) ++{ ++ LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices); ++ p->counters[posState] = p->tableSize; ++} ++ ++static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices) ++{ ++ UInt32 posState; ++ for (posState = 0; posState < numPosStates; posState++) ++ LenPriceEnc_UpdateTable(p, posState, ProbPrices); ++} ++ ++static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices) ++{ ++ LenEnc_Encode(&p->p, rc, symbol, posState); ++ if (updatePrice) ++ if (--p->counters[posState] == 0) ++ LenPriceEnc_UpdateTable(p, posState, ProbPrices); ++} ++ ++ ++ ++ ++static void MovePos(CLzmaEnc *p, UInt32 num) ++{ ++ #ifdef SHOW_STAT ++ ttt += num; ++ printf("\n MovePos %d", num); ++ #endif ++ if (num != 0) ++ { ++ p->additionalOffset += num; ++ p->matchFinder.Skip(p->matchFinderObj, num); ++ } ++} ++ ++static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes) ++{ ++ UInt32 lenRes = 0, numPairs; ++ p->numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); ++ numPairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matches); ++ #ifdef SHOW_STAT ++ printf("\n i = %d numPairs = %d ", ttt, numPairs / 2); ++ ttt++; ++ { ++ UInt32 i; ++ for (i = 0; i < numPairs; i += 2) ++ printf("%2d %6d | ", p->matches[i], p->matches[i + 1]); ++ } ++ #endif ++ if (numPairs > 0) ++ { ++ lenRes = p->matches[numPairs - 2]; ++ if (lenRes == p->numFastBytes) ++ { ++ const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ UInt32 distance = p->matches[numPairs - 1] + 1; ++ UInt32 numAvail = p->numAvail; ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ { ++ const Byte *pby2 = pby - distance; ++ for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++); ++ } ++ } ++ } ++ p->additionalOffset++; ++ *numDistancePairsRes = numPairs; ++ return lenRes; ++} ++ ++ ++#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False; ++#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False; ++#define IsShortRep(p) ((p)->backPrev == 0) ++ ++static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState) ++{ ++ return ++ GET_PRICE_0(p->isRepG0[state]) + ++ GET_PRICE_0(p->isRep0Long[state][posState]); ++} ++ ++static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState) ++{ ++ UInt32 price; ++ if (repIndex == 0) ++ { ++ price = GET_PRICE_0(p->isRepG0[state]); ++ price += GET_PRICE_1(p->isRep0Long[state][posState]); ++ } ++ else ++ { ++ price = GET_PRICE_1(p->isRepG0[state]); ++ if (repIndex == 1) ++ price += GET_PRICE_0(p->isRepG1[state]); ++ else ++ { ++ price += GET_PRICE_1(p->isRepG1[state]); ++ price += GET_PRICE(p->isRepG2[state], repIndex - 2); ++ } ++ } ++ return price; ++} ++ ++static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState) ++{ ++ return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] + ++ GetPureRepPrice(p, repIndex, state, posState); ++} ++ ++static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur) ++{ ++ UInt32 posMem = p->opt[cur].posPrev; ++ UInt32 backMem = p->opt[cur].backPrev; ++ p->optimumEndIndex = cur; ++ do ++ { ++ if (p->opt[cur].prev1IsChar) ++ { ++ MakeAsChar(&p->opt[posMem]) ++ p->opt[posMem].posPrev = posMem - 1; ++ if (p->opt[cur].prev2) ++ { ++ p->opt[posMem - 1].prev1IsChar = False; ++ p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2; ++ p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2; ++ } ++ } ++ { ++ UInt32 posPrev = posMem; ++ UInt32 backCur = backMem; ++ ++ backMem = p->opt[posPrev].backPrev; ++ posMem = p->opt[posPrev].posPrev; ++ ++ p->opt[posPrev].backPrev = backCur; ++ p->opt[posPrev].posPrev = cur; ++ cur = posPrev; ++ } ++ } ++ while (cur != 0); ++ *backRes = p->opt[0].backPrev; ++ p->optimumCurrentIndex = p->opt[0].posPrev; ++ return p->optimumCurrentIndex; ++} ++ ++#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300) ++ ++static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes) ++{ ++ UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur; ++ UInt32 matchPrice, repMatchPrice, normalMatchPrice; ++ UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS]; ++ UInt32 *matches; ++ const Byte *data; ++ Byte curByte, matchByte; ++ if (p->optimumEndIndex != p->optimumCurrentIndex) ++ { ++ const COptimal *opt = &p->opt[p->optimumCurrentIndex]; ++ UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex; ++ *backRes = opt->backPrev; ++ p->optimumCurrentIndex = opt->posPrev; ++ return lenRes; ++ } ++ p->optimumCurrentIndex = p->optimumEndIndex = 0; ++ ++ if (p->additionalOffset == 0) ++ mainLen = ReadMatchDistances(p, &numPairs); ++ else ++ { ++ mainLen = p->longestMatchLength; ++ numPairs = p->numPairs; ++ } ++ ++ numAvail = p->numAvail; ++ if (numAvail < 2) ++ { ++ *backRes = (UInt32)(-1); ++ return 1; ++ } ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ repMaxIndex = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 lenTest; ++ const Byte *data2; ++ reps[i] = p->reps[i]; ++ data2 = data - (reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ { ++ repLens[i] = 0; ++ continue; ++ } ++ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); ++ repLens[i] = lenTest; ++ if (lenTest > repLens[repMaxIndex]) ++ repMaxIndex = i; ++ } ++ if (repLens[repMaxIndex] >= p->numFastBytes) ++ { ++ UInt32 lenRes; ++ *backRes = repMaxIndex; ++ lenRes = repLens[repMaxIndex]; ++ MovePos(p, lenRes - 1); ++ return lenRes; ++ } ++ ++ matches = p->matches; ++ if (mainLen >= p->numFastBytes) ++ { ++ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 1); ++ return mainLen; ++ } ++ curByte = *data; ++ matchByte = *(data - (reps[0] + 1)); ++ ++ if (mainLen < 2 && curByte != matchByte && repLens[repMaxIndex] < 2) ++ { ++ *backRes = (UInt32)-1; ++ return 1; ++ } ++ ++ p->opt[0].state = (CState)p->state; ++ ++ posState = (position & p->pbMask); ++ ++ { ++ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); ++ p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) + ++ (!IsCharState(p->state) ? ++ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : ++ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); ++ } ++ ++ MakeAsChar(&p->opt[1]); ++ ++ matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]); ++ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]); ++ ++ if (matchByte == curByte) ++ { ++ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState); ++ if (shortRepPrice < p->opt[1].price) ++ { ++ p->opt[1].price = shortRepPrice; ++ MakeAsShortRep(&p->opt[1]); ++ } ++ } ++ lenEnd = ((mainLen >= repLens[repMaxIndex]) ? mainLen : repLens[repMaxIndex]); ++ ++ if (lenEnd < 2) ++ { ++ *backRes = p->opt[1].backPrev; ++ return 1; ++ } ++ ++ p->opt[1].posPrev = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ p->opt[0].backs[i] = reps[i]; ++ ++ len = lenEnd; ++ do ++ p->opt[len--].price = kInfinityPrice; ++ while (len >= 2); ++ ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 repLen = repLens[i]; ++ UInt32 price; ++ if (repLen < 2) ++ continue; ++ price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState); ++ do ++ { ++ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2]; ++ COptimal *opt = &p->opt[repLen]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = 0; ++ opt->backPrev = i; ++ opt->prev1IsChar = False; ++ } ++ } ++ while (--repLen >= 2); ++ } ++ ++ normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]); ++ ++ len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2); ++ if (len <= mainLen) ++ { ++ UInt32 offs = 0; ++ while (len > matches[offs]) ++ offs += 2; ++ for (; ; len++) ++ { ++ COptimal *opt; ++ UInt32 distance = matches[offs + 1]; ++ ++ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN]; ++ UInt32 lenToPosState = GetLenToPosState(len); ++ if (distance < kNumFullDistances) ++ curAndLenPrice += p->distancesPrices[lenToPosState][distance]; ++ else ++ { ++ UInt32 slot; ++ GetPosSlot2(distance, slot); ++ curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot]; ++ } ++ opt = &p->opt[len]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = 0; ++ opt->backPrev = distance + LZMA_NUM_REPS; ++ opt->prev1IsChar = False; ++ } ++ if (len == matches[offs]) ++ { ++ offs += 2; ++ if (offs == numPairs) ++ break; ++ } ++ } ++ } ++ ++ cur = 0; ++ ++ #ifdef SHOW_STAT2 ++ if (position >= 0) ++ { ++ unsigned i; ++ printf("\n pos = %4X", position); ++ for (i = cur; i <= lenEnd; i++) ++ printf("\nprice[%4X] = %d", position - cur + i, p->opt[i].price); ++ } ++ #endif ++ ++ for (;;) ++ { ++ UInt32 numAvailFull, newLen, numPairs, posPrev, state, posState, startLen; ++ UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice; ++ Bool nextIsChar; ++ Byte curByte, matchByte; ++ const Byte *data; ++ COptimal *curOpt; ++ COptimal *nextOpt; ++ ++ cur++; ++ if (cur == lenEnd) ++ return Backward(p, backRes, cur); ++ ++ newLen = ReadMatchDistances(p, &numPairs); ++ if (newLen >= p->numFastBytes) ++ { ++ p->numPairs = numPairs; ++ p->longestMatchLength = newLen; ++ return Backward(p, backRes, cur); ++ } ++ position++; ++ curOpt = &p->opt[cur]; ++ posPrev = curOpt->posPrev; ++ if (curOpt->prev1IsChar) ++ { ++ posPrev--; ++ if (curOpt->prev2) ++ { ++ state = p->opt[curOpt->posPrev2].state; ++ if (curOpt->backPrev2 < LZMA_NUM_REPS) ++ state = kRepNextStates[state]; ++ else ++ state = kMatchNextStates[state]; ++ } ++ else ++ state = p->opt[posPrev].state; ++ state = kLiteralNextStates[state]; ++ } ++ else ++ state = p->opt[posPrev].state; ++ if (posPrev == cur - 1) ++ { ++ if (IsShortRep(curOpt)) ++ state = kShortRepNextStates[state]; ++ else ++ state = kLiteralNextStates[state]; ++ } ++ else ++ { ++ UInt32 pos; ++ const COptimal *prevOpt; ++ if (curOpt->prev1IsChar && curOpt->prev2) ++ { ++ posPrev = curOpt->posPrev2; ++ pos = curOpt->backPrev2; ++ state = kRepNextStates[state]; ++ } ++ else ++ { ++ pos = curOpt->backPrev; ++ if (pos < LZMA_NUM_REPS) ++ state = kRepNextStates[state]; ++ else ++ state = kMatchNextStates[state]; ++ } ++ prevOpt = &p->opt[posPrev]; ++ if (pos < LZMA_NUM_REPS) ++ { ++ UInt32 i; ++ reps[0] = prevOpt->backs[pos]; ++ for (i = 1; i <= pos; i++) ++ reps[i] = prevOpt->backs[i - 1]; ++ for (; i < LZMA_NUM_REPS; i++) ++ reps[i] = prevOpt->backs[i]; ++ } ++ else ++ { ++ UInt32 i; ++ reps[0] = (pos - LZMA_NUM_REPS); ++ for (i = 1; i < LZMA_NUM_REPS; i++) ++ reps[i] = prevOpt->backs[i - 1]; ++ } ++ } ++ curOpt->state = (CState)state; ++ ++ curOpt->backs[0] = reps[0]; ++ curOpt->backs[1] = reps[1]; ++ curOpt->backs[2] = reps[2]; ++ curOpt->backs[3] = reps[3]; ++ ++ curPrice = curOpt->price; ++ nextIsChar = False; ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ curByte = *data; ++ matchByte = *(data - (reps[0] + 1)); ++ ++ posState = (position & p->pbMask); ++ ++ curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]); ++ { ++ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); ++ curAnd1Price += ++ (!IsCharState(state) ? ++ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : ++ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); ++ } ++ ++ nextOpt = &p->opt[cur + 1]; ++ ++ if (curAnd1Price < nextOpt->price) ++ { ++ nextOpt->price = curAnd1Price; ++ nextOpt->posPrev = cur; ++ MakeAsChar(nextOpt); ++ nextIsChar = True; ++ } ++ ++ matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]); ++ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]); ++ ++ if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0)) ++ { ++ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState); ++ if (shortRepPrice <= nextOpt->price) ++ { ++ nextOpt->price = shortRepPrice; ++ nextOpt->posPrev = cur; ++ MakeAsShortRep(nextOpt); ++ nextIsChar = True; ++ } ++ } ++ numAvailFull = p->numAvail; ++ { ++ UInt32 temp = kNumOpts - 1 - cur; ++ if (temp < numAvailFull) ++ numAvailFull = temp; ++ } ++ ++ if (numAvailFull < 2) ++ continue; ++ numAvail = (numAvailFull <= p->numFastBytes ? numAvailFull : p->numFastBytes); ++ ++ if (!nextIsChar && matchByte != curByte) /* speed optimization */ ++ { ++ /* try Literal + rep0 */ ++ UInt32 temp; ++ UInt32 lenTest2; ++ const Byte *data2 = data - (reps[0] + 1); ++ UInt32 limit = p->numFastBytes + 1; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ ++ for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++); ++ lenTest2 = temp - 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kLiteralNextStates[state]; ++ UInt32 posStateNext = (position + 1) & p->pbMask; ++ UInt32 nextRepMatchPrice = curAnd1Price + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ UInt32 offset = cur + 1 + lenTest2; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = False; ++ } ++ } ++ } ++ } ++ ++ startLen = 2; /* speed optimization */ ++ { ++ UInt32 repIndex; ++ for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++) ++ { ++ UInt32 lenTest; ++ UInt32 lenTestTemp; ++ UInt32 price; ++ const Byte *data2 = data - (reps[repIndex] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); ++ while (lenEnd < cur + lenTest) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ lenTestTemp = lenTest; ++ price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState); ++ do ++ { ++ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2]; ++ COptimal *opt = &p->opt[cur + lenTest]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur; ++ opt->backPrev = repIndex; ++ opt->prev1IsChar = False; ++ } ++ } ++ while (--lenTest >= 2); ++ lenTest = lenTestTemp; ++ ++ if (repIndex == 0) ++ startLen = lenTest + 1; ++ ++ /* if (_maxMode) */ ++ { ++ UInt32 lenTest2 = lenTest + 1; ++ UInt32 limit = lenTest2 + p->numFastBytes; ++ UInt32 nextRepMatchPrice; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); ++ lenTest2 -= lenTest + 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kRepNextStates[state]; ++ UInt32 posStateNext = (position + lenTest) & p->pbMask; ++ UInt32 curAndLenCharPrice = ++ price + p->repLenEnc.prices[posState][lenTest - 2] + ++ GET_PRICE_0(p->isMatch[state2][posStateNext]) + ++ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), ++ data[lenTest], data2[lenTest], p->ProbPrices); ++ state2 = kLiteralNextStates[state2]; ++ posStateNext = (position + lenTest + 1) & p->pbMask; ++ nextRepMatchPrice = curAndLenCharPrice + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ UInt32 offset = cur + lenTest + 1 + lenTest2; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + lenTest + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = True; ++ opt->posPrev2 = cur; ++ opt->backPrev2 = repIndex; ++ } ++ } ++ } ++ } ++ } ++ } ++ /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */ ++ if (newLen > numAvail) ++ { ++ newLen = numAvail; ++ for (numPairs = 0; newLen > matches[numPairs]; numPairs += 2); ++ matches[numPairs] = newLen; ++ numPairs += 2; ++ } ++ if (newLen >= startLen) ++ { ++ UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]); ++ UInt32 offs, curBack, posSlot; ++ UInt32 lenTest; ++ while (lenEnd < cur + newLen) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ ++ offs = 0; ++ while (startLen > matches[offs]) ++ offs += 2; ++ curBack = matches[offs + 1]; ++ GetPosSlot2(curBack, posSlot); ++ for (lenTest = /*2*/ startLen; ; lenTest++) ++ { ++ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN]; ++ UInt32 lenToPosState = GetLenToPosState(lenTest); ++ COptimal *opt; ++ if (curBack < kNumFullDistances) ++ curAndLenPrice += p->distancesPrices[lenToPosState][curBack]; ++ else ++ curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask]; ++ ++ opt = &p->opt[cur + lenTest]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur; ++ opt->backPrev = curBack + LZMA_NUM_REPS; ++ opt->prev1IsChar = False; ++ } ++ ++ if (/*_maxMode && */lenTest == matches[offs]) ++ { ++ /* Try Match + Literal + Rep0 */ ++ const Byte *data2 = data - (curBack + 1); ++ UInt32 lenTest2 = lenTest + 1; ++ UInt32 limit = lenTest2 + p->numFastBytes; ++ UInt32 nextRepMatchPrice; ++ if (limit > numAvailFull) ++ limit = numAvailFull; ++ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); ++ lenTest2 -= lenTest + 1; ++ if (lenTest2 >= 2) ++ { ++ UInt32 state2 = kMatchNextStates[state]; ++ UInt32 posStateNext = (position + lenTest) & p->pbMask; ++ UInt32 curAndLenCharPrice = curAndLenPrice + ++ GET_PRICE_0(p->isMatch[state2][posStateNext]) + ++ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), ++ data[lenTest], data2[lenTest], p->ProbPrices); ++ state2 = kLiteralNextStates[state2]; ++ posStateNext = (posStateNext + 1) & p->pbMask; ++ nextRepMatchPrice = curAndLenCharPrice + ++ GET_PRICE_1(p->isMatch[state2][posStateNext]) + ++ GET_PRICE_1(p->isRep[state2]); ++ ++ /* for (; lenTest2 >= 2; lenTest2--) */ ++ { ++ UInt32 offset = cur + lenTest + 1 + lenTest2; ++ UInt32 curAndLenPrice; ++ COptimal *opt; ++ while (lenEnd < offset) ++ p->opt[++lenEnd].price = kInfinityPrice; ++ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); ++ opt = &p->opt[offset]; ++ if (curAndLenPrice < opt->price) ++ { ++ opt->price = curAndLenPrice; ++ opt->posPrev = cur + lenTest + 1; ++ opt->backPrev = 0; ++ opt->prev1IsChar = True; ++ opt->prev2 = True; ++ opt->posPrev2 = cur; ++ opt->backPrev2 = curBack + LZMA_NUM_REPS; ++ } ++ } ++ } ++ offs += 2; ++ if (offs == numPairs) ++ break; ++ curBack = matches[offs + 1]; ++ if (curBack >= kNumFullDistances) ++ GetPosSlot2(curBack, posSlot); ++ } ++ } ++ } ++ } ++} ++ ++#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist)) ++ ++static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes) ++{ ++ UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i; ++ const Byte *data; ++ const UInt32 *matches; ++ ++ if (p->additionalOffset == 0) ++ mainLen = ReadMatchDistances(p, &numPairs); ++ else ++ { ++ mainLen = p->longestMatchLength; ++ numPairs = p->numPairs; ++ } ++ ++ numAvail = p->numAvail; ++ *backRes = (UInt32)-1; ++ if (numAvail < 2) ++ return 1; ++ if (numAvail > LZMA_MATCH_LEN_MAX) ++ numAvail = LZMA_MATCH_LEN_MAX; ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ ++ repLen = repIndex = 0; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 len; ++ const Byte *data2 = data - (p->reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ for (len = 2; len < numAvail && data[len] == data2[len]; len++); ++ if (len >= p->numFastBytes) ++ { ++ *backRes = i; ++ MovePos(p, len - 1); ++ return len; ++ } ++ if (len > repLen) ++ { ++ repIndex = i; ++ repLen = len; ++ } ++ } ++ ++ matches = p->matches; ++ if (mainLen >= p->numFastBytes) ++ { ++ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 1); ++ return mainLen; ++ } ++ ++ mainDist = 0; /* for GCC */ ++ if (mainLen >= 2) ++ { ++ mainDist = matches[numPairs - 1]; ++ while (numPairs > 2 && mainLen == matches[numPairs - 4] + 1) ++ { ++ if (!ChangePair(matches[numPairs - 3], mainDist)) ++ break; ++ numPairs -= 2; ++ mainLen = matches[numPairs - 2]; ++ mainDist = matches[numPairs - 1]; ++ } ++ if (mainLen == 2 && mainDist >= 0x80) ++ mainLen = 1; ++ } ++ ++ if (repLen >= 2 && ( ++ (repLen + 1 >= mainLen) || ++ (repLen + 2 >= mainLen && mainDist >= (1 << 9)) || ++ (repLen + 3 >= mainLen && mainDist >= (1 << 15)))) ++ { ++ *backRes = repIndex; ++ MovePos(p, repLen - 1); ++ return repLen; ++ } ++ ++ if (mainLen < 2 || numAvail <= 2) ++ return 1; ++ ++ p->longestMatchLength = ReadMatchDistances(p, &p->numPairs); ++ if (p->longestMatchLength >= 2) ++ { ++ UInt32 newDistance = matches[p->numPairs - 1]; ++ if ((p->longestMatchLength >= mainLen && newDistance < mainDist) || ++ (p->longestMatchLength == mainLen + 1 && !ChangePair(mainDist, newDistance)) || ++ (p->longestMatchLength > mainLen + 1) || ++ (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist))) ++ return 1; ++ } ++ ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; ++ for (i = 0; i < LZMA_NUM_REPS; i++) ++ { ++ UInt32 len, limit; ++ const Byte *data2 = data - (p->reps[i] + 1); ++ if (data[0] != data2[0] || data[1] != data2[1]) ++ continue; ++ limit = mainLen - 1; ++ for (len = 2; len < limit && data[len] == data2[len]; len++); ++ if (len >= limit) ++ return 1; ++ } ++ *backRes = mainDist + LZMA_NUM_REPS; ++ MovePos(p, mainLen - 2); ++ return mainLen; ++} ++ ++static void WriteEndMarker(CLzmaEnc *p, UInt32 posState) ++{ ++ UInt32 len; ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); ++ p->state = kMatchNextStates[p->state]; ++ len = LZMA_MATCH_LEN_MIN; ++ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1); ++ RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits); ++ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask); ++} ++ ++static SRes CheckErrors(CLzmaEnc *p) ++{ ++ if (p->result != SZ_OK) ++ return p->result; ++ if (p->rc.res != SZ_OK) ++ p->result = SZ_ERROR_WRITE; ++ if (p->matchFinderBase.result != SZ_OK) ++ p->result = SZ_ERROR_READ; ++ if (p->result != SZ_OK) ++ p->finished = True; ++ return p->result; ++} ++ ++static SRes Flush(CLzmaEnc *p, UInt32 nowPos) ++{ ++ /* ReleaseMFStream(); */ ++ p->finished = True; ++ if (p->writeEndMark) ++ WriteEndMarker(p, nowPos & p->pbMask); ++ RangeEnc_FlushData(&p->rc); ++ RangeEnc_FlushStream(&p->rc); ++ return CheckErrors(p); ++} ++ ++static void FillAlignPrices(CLzmaEnc *p) ++{ ++ UInt32 i; ++ for (i = 0; i < kAlignTableSize; i++) ++ p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices); ++ p->alignPriceCount = 0; ++} ++ ++static void FillDistancesPrices(CLzmaEnc *p) ++{ ++ UInt32 tempPrices[kNumFullDistances]; ++ UInt32 i, lenToPosState; ++ for (i = kStartPosModelIndex; i < kNumFullDistances; i++) ++ { ++ UInt32 posSlot = GetPosSlot1(i); ++ UInt32 footerBits = ((posSlot >> 1) - 1); ++ UInt32 base = ((2 | (posSlot & 1)) << footerBits); ++ tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices); ++ } ++ ++ for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++) ++ { ++ UInt32 posSlot; ++ const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState]; ++ UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState]; ++ for (posSlot = 0; posSlot < p->distTableSize; posSlot++) ++ posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices); ++ for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++) ++ posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits); ++ ++ { ++ UInt32 *distancesPrices = p->distancesPrices[lenToPosState]; ++ UInt32 i; ++ for (i = 0; i < kStartPosModelIndex; i++) ++ distancesPrices[i] = posSlotPrices[i]; ++ for (; i < kNumFullDistances; i++) ++ distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i]; ++ } ++ } ++ p->matchPriceCount = 0; ++} ++ ++void LzmaEnc_Construct(CLzmaEnc *p) ++{ ++ RangeEnc_Construct(&p->rc); ++ MatchFinder_Construct(&p->matchFinderBase); ++ #ifndef _7ZIP_ST ++ MatchFinderMt_Construct(&p->matchFinderMt); ++ p->matchFinderMt.MatchFinder = &p->matchFinderBase; ++ #endif ++ ++ { ++ CLzmaEncProps props; ++ LzmaEncProps_Init(&props); ++ LzmaEnc_SetProps(p, &props); ++ } ++ ++ #ifndef LZMA_LOG_BSR ++ LzmaEnc_FastPosInit(p->g_FastPos); ++ #endif ++ ++ LzmaEnc_InitPriceTables(p->ProbPrices); ++ p->litProbs = 0; ++ p->saveState.litProbs = 0; ++} ++ ++CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc) ++{ ++ void *p; ++ p = alloc->Alloc(alloc, sizeof(CLzmaEnc)); ++ if (p != 0) ++ LzmaEnc_Construct((CLzmaEnc *)p); ++ return p; ++} ++ ++void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) ++{ ++ alloc->Free(alloc, p->litProbs); ++ alloc->Free(alloc, p->saveState.litProbs); ++ p->litProbs = 0; ++ p->saveState.litProbs = 0; ++} ++ ++void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ #ifndef _7ZIP_ST ++ MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); ++ #endif ++ MatchFinder_Free(&p->matchFinderBase, allocBig); ++ LzmaEnc_FreeLits(p, alloc); ++ RangeEnc_Free(&p->rc, alloc); ++} ++ ++void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig); ++ alloc->Free(alloc, p); ++} ++ ++static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize) ++{ ++ UInt32 nowPos32, startPos32; ++ if (p->needInit) ++ { ++ p->matchFinder.Init(p->matchFinderObj); ++ p->needInit = 0; ++ } ++ ++ if (p->finished) ++ return p->result; ++ RINOK(CheckErrors(p)); ++ ++ nowPos32 = (UInt32)p->nowPos64; ++ startPos32 = nowPos32; ++ ++ if (p->nowPos64 == 0) ++ { ++ UInt32 numPairs; ++ Byte curByte; ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) ++ return Flush(p, nowPos32); ++ ReadMatchDistances(p, &numPairs); ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0); ++ p->state = kLiteralNextStates[p->state]; ++ curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset); ++ LitEnc_Encode(&p->rc, p->litProbs, curByte); ++ p->additionalOffset--; ++ nowPos32++; ++ } ++ ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0) ++ for (;;) ++ { ++ UInt32 pos, len, posState; ++ ++ if (p->fastMode) ++ len = GetOptimumFast(p, &pos); ++ else ++ len = GetOptimum(p, nowPos32, &pos); ++ ++ #ifdef SHOW_STAT2 ++ printf("\n pos = %4X, len = %d pos = %d", nowPos32, len, pos); ++ #endif ++ ++ posState = nowPos32 & p->pbMask; ++ if (len == 1 && pos == (UInt32)-1) ++ { ++ Byte curByte; ++ CLzmaProb *probs; ++ const Byte *data; ++ ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0); ++ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; ++ curByte = *data; ++ probs = LIT_PROBS(nowPos32, *(data - 1)); ++ if (IsCharState(p->state)) ++ LitEnc_Encode(&p->rc, probs, curByte); ++ else ++ LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1)); ++ p->state = kLiteralNextStates[p->state]; ++ } ++ else ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); ++ if (pos < LZMA_NUM_REPS) ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1); ++ if (pos == 0) ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0); ++ RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1)); ++ } ++ else ++ { ++ UInt32 distance = p->reps[pos]; ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1); ++ if (pos == 1) ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0); ++ else ++ { ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1); ++ RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2); ++ if (pos == 3) ++ p->reps[3] = p->reps[2]; ++ p->reps[2] = p->reps[1]; ++ } ++ p->reps[1] = p->reps[0]; ++ p->reps[0] = distance; ++ } ++ if (len == 1) ++ p->state = kShortRepNextStates[p->state]; ++ else ++ { ++ LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ p->state = kRepNextStates[p->state]; ++ } ++ } ++ else ++ { ++ UInt32 posSlot; ++ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); ++ p->state = kMatchNextStates[p->state]; ++ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); ++ pos -= LZMA_NUM_REPS; ++ GetPosSlot(pos, posSlot); ++ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot); ++ ++ if (posSlot >= kStartPosModelIndex) ++ { ++ UInt32 footerBits = ((posSlot >> 1) - 1); ++ UInt32 base = ((2 | (posSlot & 1)) << footerBits); ++ UInt32 posReduced = pos - base; ++ ++ if (posSlot < kEndPosModelIndex) ++ RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced); ++ else ++ { ++ RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits); ++ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask); ++ p->alignPriceCount++; ++ } ++ } ++ p->reps[3] = p->reps[2]; ++ p->reps[2] = p->reps[1]; ++ p->reps[1] = p->reps[0]; ++ p->reps[0] = pos; ++ p->matchPriceCount++; ++ } ++ } ++ p->additionalOffset -= len; ++ nowPos32 += len; ++ if (p->additionalOffset == 0) ++ { ++ UInt32 processed; ++ if (!p->fastMode) ++ { ++ if (p->matchPriceCount >= (1 << 7)) ++ FillDistancesPrices(p); ++ if (p->alignPriceCount >= kAlignTableSize) ++ FillAlignPrices(p); ++ } ++ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) ++ break; ++ processed = nowPos32 - startPos32; ++ if (useLimits) ++ { ++ if (processed + kNumOpts + 300 >= maxUnpackSize || ++ RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize) ++ break; ++ } ++ else if (processed >= (1 << 15)) ++ { ++ p->nowPos64 += nowPos32 - startPos32; ++ return CheckErrors(p); ++ } ++ } ++ } ++ p->nowPos64 += nowPos32 - startPos32; ++ return Flush(p, nowPos32); ++} ++ ++#define kBigHashDicLimit ((UInt32)1 << 24) ++ ++static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ UInt32 beforeSize = kNumOpts; ++ Bool btMode; ++ if (!RangeEnc_Alloc(&p->rc, alloc)) ++ return SZ_ERROR_MEM; ++ btMode = (p->matchFinderBase.btMode != 0); ++ #ifndef _7ZIP_ST ++ p->mtMode = (p->multiThread && !p->fastMode && btMode); ++ #endif ++ ++ { ++ unsigned lclp = p->lc + p->lp; ++ if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp) ++ { ++ LzmaEnc_FreeLits(p, alloc); ++ p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); ++ p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); ++ if (p->litProbs == 0 || p->saveState.litProbs == 0) ++ { ++ LzmaEnc_FreeLits(p, alloc); ++ return SZ_ERROR_MEM; ++ } ++ p->lclp = lclp; ++ } ++ } ++ ++ p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit); ++ ++ if (beforeSize + p->dictSize < keepWindowSize) ++ beforeSize = keepWindowSize - p->dictSize; ++ ++ #ifndef _7ZIP_ST ++ if (p->mtMode) ++ { ++ RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)); ++ p->matchFinderObj = &p->matchFinderMt; ++ MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder); ++ } ++ else ++ #endif ++ { ++ if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)) ++ return SZ_ERROR_MEM; ++ p->matchFinderObj = &p->matchFinderBase; ++ MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder); ++ } ++ return SZ_OK; ++} ++ ++void LzmaEnc_Init(CLzmaEnc *p) ++{ ++ UInt32 i; ++ p->state = 0; ++ for (i = 0 ; i < LZMA_NUM_REPS; i++) ++ p->reps[i] = 0; ++ ++ RangeEnc_Init(&p->rc); ++ ++ ++ for (i = 0; i < kNumStates; i++) ++ { ++ UInt32 j; ++ for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++) ++ { ++ p->isMatch[i][j] = kProbInitValue; ++ p->isRep0Long[i][j] = kProbInitValue; ++ } ++ p->isRep[i] = kProbInitValue; ++ p->isRepG0[i] = kProbInitValue; ++ p->isRepG1[i] = kProbInitValue; ++ p->isRepG2[i] = kProbInitValue; ++ } ++ ++ { ++ UInt32 num = 0x300 << (p->lp + p->lc); ++ for (i = 0; i < num; i++) ++ p->litProbs[i] = kProbInitValue; ++ } ++ ++ { ++ for (i = 0; i < kNumLenToPosStates; i++) ++ { ++ CLzmaProb *probs = p->posSlotEncoder[i]; ++ UInt32 j; ++ for (j = 0; j < (1 << kNumPosSlotBits); j++) ++ probs[j] = kProbInitValue; ++ } ++ } ++ { ++ for (i = 0; i < kNumFullDistances - kEndPosModelIndex; i++) ++ p->posEncoders[i] = kProbInitValue; ++ } ++ ++ LenEnc_Init(&p->lenEnc.p); ++ LenEnc_Init(&p->repLenEnc.p); ++ ++ for (i = 0; i < (1 << kNumAlignBits); i++) ++ p->posAlignEncoder[i] = kProbInitValue; ++ ++ p->optimumEndIndex = 0; ++ p->optimumCurrentIndex = 0; ++ p->additionalOffset = 0; ++ ++ p->pbMask = (1 << p->pb) - 1; ++ p->lpMask = (1 << p->lp) - 1; ++} ++ ++void LzmaEnc_InitPrices(CLzmaEnc *p) ++{ ++ if (!p->fastMode) ++ { ++ FillDistancesPrices(p); ++ FillAlignPrices(p); ++ } ++ ++ p->lenEnc.tableSize = ++ p->repLenEnc.tableSize = ++ p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN; ++ LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices); ++ LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices); ++} ++ ++static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ UInt32 i; ++ for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++) ++ if (p->dictSize <= ((UInt32)1 << i)) ++ break; ++ p->distTableSize = i * 2; ++ ++ p->finished = False; ++ p->result = SZ_OK; ++ RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig)); ++ LzmaEnc_Init(p); ++ LzmaEnc_InitPrices(p); ++ p->nowPos64 = 0; ++ return SZ_OK; ++} ++ ++static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ p->matchFinderBase.stream = inStream; ++ p->needInit = 1; ++ p->rc.outStream = outStream; ++ return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig); ++} ++ ++SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, ++ ISeqInStream *inStream, UInt32 keepWindowSize, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ p->matchFinderBase.stream = inStream; ++ p->needInit = 1; ++ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); ++} ++ ++static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) ++{ ++ p->matchFinderBase.directInput = 1; ++ p->matchFinderBase.bufferBase = (Byte *)src; ++ p->matchFinderBase.directInputRem = srcLen; ++} ++ ++SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, ++ UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ LzmaEnc_SetInputBuf(p, src, srcLen); ++ p->needInit = 1; ++ ++ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); ++} ++ ++void LzmaEnc_Finish(CLzmaEncHandle pp) ++{ ++ #ifndef _7ZIP_ST ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ if (p->mtMode) ++ MatchFinderMt_ReleaseStream(&p->matchFinderMt); ++ #else ++ pp = pp; ++ #endif ++} ++ ++typedef struct ++{ ++ ISeqOutStream funcTable; ++ Byte *data; ++ SizeT rem; ++ Bool overflow; ++} CSeqOutStreamBuf; ++ ++static size_t MyWrite(void *pp, const void *data, size_t size) ++{ ++ CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp; ++ if (p->rem < size) ++ { ++ size = p->rem; ++ p->overflow = True; ++ } ++ memcpy(p->data, data, size); ++ p->rem -= size; ++ p->data += size; ++ return size; ++} ++ ++ ++UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp) ++{ ++ const CLzmaEnc *p = (CLzmaEnc *)pp; ++ return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); ++} ++ ++const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp) ++{ ++ const CLzmaEnc *p = (CLzmaEnc *)pp; ++ return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; ++} ++ ++SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, ++ Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ UInt64 nowPos64; ++ SRes res; ++ CSeqOutStreamBuf outStream; ++ ++ outStream.funcTable.Write = MyWrite; ++ outStream.data = dest; ++ outStream.rem = *destLen; ++ outStream.overflow = False; ++ ++ p->writeEndMark = False; ++ p->finished = False; ++ p->result = SZ_OK; ++ ++ if (reInit) ++ LzmaEnc_Init(p); ++ LzmaEnc_InitPrices(p); ++ nowPos64 = p->nowPos64; ++ RangeEnc_Init(&p->rc); ++ p->rc.outStream = &outStream.funcTable; ++ ++ res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize); ++ ++ *unpackSize = (UInt32)(p->nowPos64 - nowPos64); ++ *destLen -= outStream.rem; ++ if (outStream.overflow) ++ return SZ_ERROR_OUTPUT_EOF; ++ ++ return res; ++} ++ ++static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) ++{ ++ SRes res = SZ_OK; ++ ++ #ifndef _7ZIP_ST ++ Byte allocaDummy[0x300]; ++ int i = 0; ++ for (i = 0; i < 16; i++) ++ allocaDummy[i] = (Byte)i; ++ #endif ++ ++ for (;;) ++ { ++ res = LzmaEnc_CodeOneBlock(p, False, 0, 0); ++ if (res != SZ_OK || p->finished != 0) ++ break; ++ if (progress != 0) ++ { ++ res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc)); ++ if (res != SZ_OK) ++ { ++ res = SZ_ERROR_PROGRESS; ++ break; ++ } ++ } ++ } ++ LzmaEnc_Finish(p); ++ return res; ++} ++ ++SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress, ++ ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig)); ++ return LzmaEnc_Encode2((CLzmaEnc *)pp, progress); ++} ++ ++SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ int i; ++ UInt32 dictSize = p->dictSize; ++ if (*size < LZMA_PROPS_SIZE) ++ return SZ_ERROR_PARAM; ++ *size = LZMA_PROPS_SIZE; ++ props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc); ++ ++ for (i = 11; i <= 30; i++) ++ { ++ if (dictSize <= ((UInt32)2 << i)) ++ { ++ dictSize = (2 << i); ++ break; ++ } ++ if (dictSize <= ((UInt32)3 << i)) ++ { ++ dictSize = (3 << i); ++ break; ++ } ++ } ++ ++ for (i = 0; i < 4; i++) ++ props[1 + i] = (Byte)(dictSize >> (8 * i)); ++ return SZ_OK; ++} ++ ++SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ SRes res; ++ CLzmaEnc *p = (CLzmaEnc *)pp; ++ ++ CSeqOutStreamBuf outStream; ++ ++ LzmaEnc_SetInputBuf(p, src, srcLen); ++ ++ outStream.funcTable.Write = MyWrite; ++ outStream.data = dest; ++ outStream.rem = *destLen; ++ outStream.overflow = False; ++ ++ p->writeEndMark = writeEndMark; ++ ++ p->rc.outStream = &outStream.funcTable; ++ res = LzmaEnc_MemPrepare(pp, src, srcLen, 0, alloc, allocBig); ++ if (res == SZ_OK) ++ res = LzmaEnc_Encode2(p, progress); ++ ++ *destLen -= outStream.rem; ++ if (outStream.overflow) ++ return SZ_ERROR_OUTPUT_EOF; ++ return res; ++} ++ ++SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, ++ const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, ++ ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) ++{ ++ CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc); ++ SRes res; ++ if (p == 0) ++ return SZ_ERROR_MEM; ++ ++ res = LzmaEnc_SetProps(p, props); ++ if (res == SZ_OK) ++ { ++ res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize); ++ if (res == SZ_OK) ++ res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen, ++ writeEndMark, progress, alloc, allocBig); ++ } ++ ++ LzmaEnc_Destroy(p, alloc, allocBig); ++ return res; ++} +--- /dev/null ++++ b/lib/lzma/Makefile +@@ -0,0 +1,7 @@ ++lzma_compress-objs := LzFind.o LzmaEnc.o ++lzma_decompress-objs := LzmaDec.o ++ ++obj-$(CONFIG_LZMA_COMPRESS) += lzma_compress.o ++obj-$(CONFIG_LZMA_DECOMPRESS) += lzma_decompress.o ++ ++EXTRA_CFLAGS += -Iinclude/linux -Iinclude/linux/lzma -include types.h diff --git a/target/linux/generic/patches-4.3/531-debloat_lzma.patch b/target/linux/generic/patches-4.3/531-debloat_lzma.patch new file mode 100644 index 0000000..aa3c498 --- /dev/null +++ b/target/linux/generic/patches-4.3/531-debloat_lzma.patch @@ -0,0 +1,1024 @@ +--- a/include/linux/lzma/LzmaDec.h ++++ b/include/linux/lzma/LzmaDec.h +@@ -31,14 +31,6 @@ typedef struct _CLzmaProps + UInt32 dicSize; + } CLzmaProps; + +-/* LzmaProps_Decode - decodes properties +-Returns: +- SZ_OK +- SZ_ERROR_UNSUPPORTED - Unsupported properties +-*/ +- +-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size); +- + + /* ---------- LZMA Decoder state ---------- */ + +@@ -70,8 +62,6 @@ typedef struct + + #define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } + +-void LzmaDec_Init(CLzmaDec *p); +- + /* There are two types of LZMA streams: + 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. + 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ +@@ -108,97 +98,6 @@ typedef enum + + /* ELzmaStatus is used only as output value for function call */ + +- +-/* ---------- Interfaces ---------- */ +- +-/* There are 3 levels of interfaces: +- 1) Dictionary Interface +- 2) Buffer Interface +- 3) One Call Interface +- You can select any of these interfaces, but don't mix functions from different +- groups for same object. */ +- +- +-/* There are two variants to allocate state for Dictionary Interface: +- 1) LzmaDec_Allocate / LzmaDec_Free +- 2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs +- You can use variant 2, if you set dictionary buffer manually. +- For Buffer Interface you must always use variant 1. +- +-LzmaDec_Allocate* can return: +- SZ_OK +- SZ_ERROR_MEM - Memory allocation error +- SZ_ERROR_UNSUPPORTED - Unsupported properties +-*/ +- +-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc); +-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc); +- +-SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc); +-void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc); +- +-/* ---------- Dictionary Interface ---------- */ +- +-/* You can use it, if you want to eliminate the overhead for data copying from +- dictionary to some other external buffer. +- You must work with CLzmaDec variables directly in this interface. +- +- STEPS: +- LzmaDec_Constr() +- LzmaDec_Allocate() +- for (each new stream) +- { +- LzmaDec_Init() +- while (it needs more decompression) +- { +- LzmaDec_DecodeToDic() +- use data from CLzmaDec::dic and update CLzmaDec::dicPos +- } +- } +- LzmaDec_Free() +-*/ +- +-/* LzmaDec_DecodeToDic +- +- The decoding to internal dictionary buffer (CLzmaDec::dic). +- You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! +- +-finishMode: +- It has meaning only if the decoding reaches output limit (dicLimit). +- LZMA_FINISH_ANY - Decode just dicLimit bytes. +- LZMA_FINISH_END - Stream must be finished after dicLimit. +- +-Returns: +- SZ_OK +- status: +- LZMA_STATUS_FINISHED_WITH_MARK +- LZMA_STATUS_NOT_FINISHED +- LZMA_STATUS_NEEDS_MORE_INPUT +- LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK +- SZ_ERROR_DATA - Data error +-*/ +- +-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, +- const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); +- +- +-/* ---------- Buffer Interface ---------- */ +- +-/* It's zlib-like interface. +- See LzmaDec_DecodeToDic description for information about STEPS and return results, +- but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need +- to work with CLzmaDec variables manually. +- +-finishMode: +- It has meaning only if the decoding reaches output limit (*destLen). +- LZMA_FINISH_ANY - Decode just destLen bytes. +- LZMA_FINISH_END - Stream must be finished after (*destLen). +-*/ +- +-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, +- const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status); +- +- + /* ---------- One Call Interface ---------- */ + + /* LzmaDecode +--- a/lib/lzma/LzmaDec.c ++++ b/lib/lzma/LzmaDec.c +@@ -682,7 +682,7 @@ static void LzmaDec_InitRc(CLzmaDec *p, + p->needFlush = 0; + } + +-void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) ++static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) + { + p->needFlush = 1; + p->remainLen = 0; +@@ -698,7 +698,7 @@ void LzmaDec_InitDicAndState(CLzmaDec *p + p->needInitState = 1; + } + +-void LzmaDec_Init(CLzmaDec *p) ++static void LzmaDec_Init(CLzmaDec *p) + { + p->dicPos = 0; + LzmaDec_InitDicAndState(p, True, True); +@@ -716,7 +716,7 @@ static void LzmaDec_InitStateReal(CLzmaD + p->needInitState = 0; + } + +-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, ++static SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, + ELzmaFinishMode finishMode, ELzmaStatus *status) + { + SizeT inSize = *srcLen; +@@ -837,65 +837,13 @@ SRes LzmaDec_DecodeToDic(CLzmaDec *p, Si + return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; + } + +-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status) +-{ +- SizeT outSize = *destLen; +- SizeT inSize = *srcLen; +- *srcLen = *destLen = 0; +- for (;;) +- { +- SizeT inSizeCur = inSize, outSizeCur, dicPos; +- ELzmaFinishMode curFinishMode; +- SRes res; +- if (p->dicPos == p->dicBufSize) +- p->dicPos = 0; +- dicPos = p->dicPos; +- if (outSize > p->dicBufSize - dicPos) +- { +- outSizeCur = p->dicBufSize; +- curFinishMode = LZMA_FINISH_ANY; +- } +- else +- { +- outSizeCur = dicPos + outSize; +- curFinishMode = finishMode; +- } +- +- res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status); +- src += inSizeCur; +- inSize -= inSizeCur; +- *srcLen += inSizeCur; +- outSizeCur = p->dicPos - dicPos; +- memcpy(dest, p->dic + dicPos, outSizeCur); +- dest += outSizeCur; +- outSize -= outSizeCur; +- *destLen += outSizeCur; +- if (res != 0) +- return res; +- if (outSizeCur == 0 || outSize == 0) +- return SZ_OK; +- } +-} +- +-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) ++static void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) + { + alloc->Free(alloc, p->probs); + p->probs = 0; + } + +-static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) +-{ +- alloc->Free(alloc, p->dic); +- p->dic = 0; +-} +- +-void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc) +-{ +- LzmaDec_FreeProbs(p, alloc); +- LzmaDec_FreeDict(p, alloc); +-} +- +-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) ++static SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) + { + UInt32 dicSize; + Byte d; +@@ -935,7 +883,7 @@ static SRes LzmaDec_AllocateProbs2(CLzma + return SZ_OK; + } + +-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) ++static SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) + { + CLzmaProps propNew; + RINOK(LzmaProps_Decode(&propNew, props, propsSize)); +@@ -943,28 +891,6 @@ SRes LzmaDec_AllocateProbs(CLzmaDec *p, + p->prop = propNew; + return SZ_OK; + } +- +-SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) +-{ +- CLzmaProps propNew; +- SizeT dicBufSize; +- RINOK(LzmaProps_Decode(&propNew, props, propsSize)); +- RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); +- dicBufSize = propNew.dicSize; +- if (p->dic == 0 || dicBufSize != p->dicBufSize) +- { +- LzmaDec_FreeDict(p, alloc); +- p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize); +- if (p->dic == 0) +- { +- LzmaDec_FreeProbs(p, alloc); +- return SZ_ERROR_MEM; +- } +- } +- p->dicBufSize = dicBufSize; +- p->prop = propNew; +- return SZ_OK; +-} + + SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, + const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, +--- a/include/linux/lzma/LzmaEnc.h ++++ b/include/linux/lzma/LzmaEnc.h +@@ -31,9 +31,6 @@ typedef struct _CLzmaEncProps + } CLzmaEncProps; + + void LzmaEncProps_Init(CLzmaEncProps *p); +-void LzmaEncProps_Normalize(CLzmaEncProps *p); +-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2); +- + + /* ---------- CLzmaEncHandle Interface ---------- */ + +@@ -53,26 +50,9 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc * + void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); + SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); + SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); +-SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); + SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, + int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); + +-/* ---------- One Call Interface ---------- */ +- +-/* LzmaEncode +-Return code: +- SZ_OK - OK +- SZ_ERROR_MEM - Memory allocation error +- SZ_ERROR_PARAM - Incorrect paramater +- SZ_ERROR_OUTPUT_EOF - output buffer overflow +- SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) +-*/ +- +-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, +- const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); +- + #ifdef __cplusplus + } + #endif +--- a/lib/lzma/LzmaEnc.c ++++ b/lib/lzma/LzmaEnc.c +@@ -53,7 +53,7 @@ void LzmaEncProps_Init(CLzmaEncProps *p) + p->writeEndMark = 0; + } + +-void LzmaEncProps_Normalize(CLzmaEncProps *p) ++static void LzmaEncProps_Normalize(CLzmaEncProps *p) + { + int level = p->level; + if (level < 0) level = 5; +@@ -76,7 +76,7 @@ void LzmaEncProps_Normalize(CLzmaEncProp + #endif + } + +-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) ++static UInt32 __maybe_unused LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) + { + CLzmaEncProps props = *props2; + LzmaEncProps_Normalize(&props); +@@ -93,7 +93,7 @@ UInt32 LzmaEncProps_GetDictSize(const CL + + #define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } + +-UInt32 GetPosSlot1(UInt32 pos) ++static UInt32 GetPosSlot1(UInt32 pos) + { + UInt32 res; + BSR2_RET(pos, res); +@@ -107,7 +107,7 @@ UInt32 GetPosSlot1(UInt32 pos) + #define kNumLogBits (9 + (int)sizeof(size_t) / 2) + #define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) + +-void LzmaEnc_FastPosInit(Byte *g_FastPos) ++static void LzmaEnc_FastPosInit(Byte *g_FastPos) + { + int c = 2, slotFast; + g_FastPos[0] = 0; +@@ -339,58 +339,6 @@ typedef struct + CSaveState saveState; + } CLzmaEnc; + +-void LzmaEnc_SaveState(CLzmaEncHandle pp) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- CSaveState *dest = &p->saveState; +- int i; +- dest->lenEnc = p->lenEnc; +- dest->repLenEnc = p->repLenEnc; +- dest->state = p->state; +- +- for (i = 0; i < kNumStates; i++) +- { +- memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); +- memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); +- } +- for (i = 0; i < kNumLenToPosStates; i++) +- memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); +- memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); +- memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); +- memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); +- memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); +- memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); +- memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); +- memcpy(dest->reps, p->reps, sizeof(p->reps)); +- memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb)); +-} +- +-void LzmaEnc_RestoreState(CLzmaEncHandle pp) +-{ +- CLzmaEnc *dest = (CLzmaEnc *)pp; +- const CSaveState *p = &dest->saveState; +- int i; +- dest->lenEnc = p->lenEnc; +- dest->repLenEnc = p->repLenEnc; +- dest->state = p->state; +- +- for (i = 0; i < kNumStates; i++) +- { +- memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i])); +- memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i])); +- } +- for (i = 0; i < kNumLenToPosStates; i++) +- memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i])); +- memcpy(dest->isRep, p->isRep, sizeof(p->isRep)); +- memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0)); +- memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1)); +- memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2)); +- memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders)); +- memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder)); +- memcpy(dest->reps, p->reps, sizeof(p->reps)); +- memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb)); +-} +- + SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -600,7 +548,7 @@ static void LitEnc_EncodeMatched(CRangeE + while (symbol < 0x10000); + } + +-void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) ++static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) + { + UInt32 i; + for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) +@@ -1676,7 +1624,7 @@ static void FillDistancesPrices(CLzmaEnc + p->matchPriceCount = 0; + } + +-void LzmaEnc_Construct(CLzmaEnc *p) ++static void LzmaEnc_Construct(CLzmaEnc *p) + { + RangeEnc_Construct(&p->rc); + MatchFinder_Construct(&p->matchFinderBase); +@@ -1709,7 +1657,7 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc * + return p; + } + +-void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) ++static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) + { + alloc->Free(alloc, p->litProbs); + alloc->Free(alloc, p->saveState.litProbs); +@@ -1717,7 +1665,7 @@ void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAl + p->saveState.litProbs = 0; + } + +-void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) ++static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) + { + #ifndef _7ZIP_ST + MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); +@@ -1947,7 +1895,7 @@ static SRes LzmaEnc_Alloc(CLzmaEnc *p, U + return SZ_OK; + } + +-void LzmaEnc_Init(CLzmaEnc *p) ++static void LzmaEnc_Init(CLzmaEnc *p) + { + UInt32 i; + p->state = 0; +@@ -2005,7 +1953,7 @@ void LzmaEnc_Init(CLzmaEnc *p) + p->lpMask = (1 << p->lp) - 1; + } + +-void LzmaEnc_InitPrices(CLzmaEnc *p) ++static void LzmaEnc_InitPrices(CLzmaEnc *p) + { + if (!p->fastMode) + { +@@ -2037,26 +1985,6 @@ static SRes LzmaEnc_AllocAndInit(CLzmaEn + return SZ_OK; + } + +-static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- p->matchFinderBase.stream = inStream; +- p->needInit = 1; +- p->rc.outStream = outStream; +- return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig); +-} +- +-SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, +- ISeqInStream *inStream, UInt32 keepWindowSize, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- p->matchFinderBase.stream = inStream; +- p->needInit = 1; +- return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); +-} +- + static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) + { + p->matchFinderBase.directInput = 1; +@@ -2064,7 +1992,7 @@ static void LzmaEnc_SetInputBuf(CLzmaEnc + p->matchFinderBase.directInputRem = srcLen; + } + +-SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, ++static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, + UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2074,7 +2002,7 @@ SRes LzmaEnc_MemPrepare(CLzmaEncHandle p + return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); + } + +-void LzmaEnc_Finish(CLzmaEncHandle pp) ++static void LzmaEnc_Finish(CLzmaEncHandle pp) + { + #ifndef _7ZIP_ST + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2107,53 +2035,6 @@ static size_t MyWrite(void *pp, const vo + return size; + } + +- +-UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp) +-{ +- const CLzmaEnc *p = (CLzmaEnc *)pp; +- return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); +-} +- +-const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp) +-{ +- const CLzmaEnc *p = (CLzmaEnc *)pp; +- return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; +-} +- +-SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, +- Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize) +-{ +- CLzmaEnc *p = (CLzmaEnc *)pp; +- UInt64 nowPos64; +- SRes res; +- CSeqOutStreamBuf outStream; +- +- outStream.funcTable.Write = MyWrite; +- outStream.data = dest; +- outStream.rem = *destLen; +- outStream.overflow = False; +- +- p->writeEndMark = False; +- p->finished = False; +- p->result = SZ_OK; +- +- if (reInit) +- LzmaEnc_Init(p); +- LzmaEnc_InitPrices(p); +- nowPos64 = p->nowPos64; +- RangeEnc_Init(&p->rc); +- p->rc.outStream = &outStream.funcTable; +- +- res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize); +- +- *unpackSize = (UInt32)(p->nowPos64 - nowPos64); +- *destLen -= outStream.rem; +- if (outStream.overflow) +- return SZ_ERROR_OUTPUT_EOF; +- +- return res; +-} +- + static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) + { + SRes res = SZ_OK; +@@ -2184,13 +2065,6 @@ static SRes LzmaEnc_Encode2(CLzmaEnc *p, + return res; + } + +-SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress, +- ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig)); +- return LzmaEnc_Encode2((CLzmaEnc *)pp, progress); +-} +- + SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) + { + CLzmaEnc *p = (CLzmaEnc *)pp; +@@ -2247,25 +2121,3 @@ SRes LzmaEnc_MemEncode(CLzmaEncHandle pp + return SZ_ERROR_OUTPUT_EOF; + return res; + } +- +-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, +- const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, +- ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) +-{ +- CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc); +- SRes res; +- if (p == 0) +- return SZ_ERROR_MEM; +- +- res = LzmaEnc_SetProps(p, props); +- if (res == SZ_OK) +- { +- res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize); +- if (res == SZ_OK) +- res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen, +- writeEndMark, progress, alloc, allocBig); +- } +- +- LzmaEnc_Destroy(p, alloc, allocBig); +- return res; +-} +--- a/include/linux/lzma/LzFind.h ++++ b/include/linux/lzma/LzFind.h +@@ -55,11 +55,6 @@ typedef struct _CMatchFinder + + #define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) + +-int MatchFinder_NeedMove(CMatchFinder *p); +-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p); +-void MatchFinder_MoveBlock(CMatchFinder *p); +-void MatchFinder_ReadIfRequired(CMatchFinder *p); +- + void MatchFinder_Construct(CMatchFinder *p); + + /* Conditions: +@@ -70,12 +65,6 @@ int MatchFinder_Create(CMatchFinder *p, + UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, + ISzAlloc *alloc); + void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); +-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems); +-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue); +- +-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, +- UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, +- UInt32 *distances, UInt32 maxLen); + + /* + Conditions: +@@ -102,12 +91,6 @@ typedef struct _IMatchFinder + + void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); + +-void MatchFinder_Init(CMatchFinder *p); +-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); +-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances); +-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); +-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num); +- + #ifdef __cplusplus + } + #endif +--- a/lib/lzma/LzFind.c ++++ b/lib/lzma/LzFind.c +@@ -14,9 +14,15 @@ + + #define kStartMaxLen 3 + ++#if 0 ++#define DIRECT_INPUT p->directInput ++#else ++#define DIRECT_INPUT 1 ++#endif ++ + static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) + { +- if (!p->directInput) ++ if (!DIRECT_INPUT) + { + alloc->Free(alloc, p->bufferBase); + p->bufferBase = 0; +@@ -28,7 +34,7 @@ static void LzInWindow_Free(CMatchFinder + static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) + { + UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; +- if (p->directInput) ++ if (DIRECT_INPUT) + { + p->blockSize = blockSize; + return 1; +@@ -42,12 +48,12 @@ static int LzInWindow_Create(CMatchFinde + return (p->bufferBase != 0); + } + +-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } +-Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } ++static Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } ++static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } + +-UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } ++static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } + +-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) ++static void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) + { + p->posLimit -= subValue; + p->pos -= subValue; +@@ -58,7 +64,7 @@ static void MatchFinder_ReadBlock(CMatch + { + if (p->streamEndWasReached || p->result != SZ_OK) + return; +- if (p->directInput) ++ if (DIRECT_INPUT) + { + UInt32 curSize = 0xFFFFFFFF - p->streamPos; + if (curSize > p->directInputRem) +@@ -89,7 +95,7 @@ static void MatchFinder_ReadBlock(CMatch + } + } + +-void MatchFinder_MoveBlock(CMatchFinder *p) ++static void MatchFinder_MoveBlock(CMatchFinder *p) + { + memmove(p->bufferBase, + p->buffer - p->keepSizeBefore, +@@ -97,22 +103,14 @@ void MatchFinder_MoveBlock(CMatchFinder + p->buffer = p->bufferBase + p->keepSizeBefore; + } + +-int MatchFinder_NeedMove(CMatchFinder *p) ++static int MatchFinder_NeedMove(CMatchFinder *p) + { +- if (p->directInput) ++ if (DIRECT_INPUT) + return 0; + /* if (p->streamEndWasReached) return 0; */ + return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); + } + +-void MatchFinder_ReadIfRequired(CMatchFinder *p) +-{ +- if (p->streamEndWasReached) +- return; +- if (p->keepSizeAfter >= p->streamPos - p->pos) +- MatchFinder_ReadBlock(p); +-} +- + static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) + { + if (MatchFinder_NeedMove(p)) +@@ -268,7 +266,7 @@ static void MatchFinder_SetLimits(CMatch + p->posLimit = p->pos + limit; + } + +-void MatchFinder_Init(CMatchFinder *p) ++static void MatchFinder_Init(CMatchFinder *p) + { + UInt32 i; + for (i = 0; i < p->hashSizeSum; i++) +@@ -287,7 +285,7 @@ static UInt32 MatchFinder_GetSubValue(CM + return (p->pos - p->historySize - 1) & kNormalizeMask; + } + +-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) ++static void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) + { + UInt32 i; + for (i = 0; i < numItems; i++) +@@ -319,38 +317,7 @@ static void MatchFinder_CheckLimits(CMat + MatchFinder_SetLimits(p); + } + +-static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, +- UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, +- UInt32 *distances, UInt32 maxLen) +-{ +- son[_cyclicBufferPos] = curMatch; +- for (;;) +- { +- UInt32 delta = pos - curMatch; +- if (cutValue-- == 0 || delta >= _cyclicBufferSize) +- return distances; +- { +- const Byte *pb = cur - delta; +- curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)]; +- if (pb[maxLen] == cur[maxLen] && *pb == *cur) +- { +- UInt32 len = 0; +- while (++len != lenLimit) +- if (pb[len] != cur[len]) +- break; +- if (maxLen < len) +- { +- *distances++ = maxLen = len; +- *distances++ = delta - 1; +- if (len == lenLimit) +- return distances; +- } +- } +- } +- } +-} +- +-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, ++static UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, + UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, + UInt32 *distances, UInt32 maxLen) + { +@@ -460,10 +427,10 @@ static void SkipMatchesSpec(UInt32 lenLi + p->buffer++; \ + if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); + +-#define MOVE_POS_RET MOVE_POS return offset; +- + static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } + ++#define MOVE_POS_RET MatchFinder_MovePos(p); return offset; ++ + #define GET_MATCHES_HEADER2(minLen, ret_op) \ + UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ + lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ +@@ -479,62 +446,7 @@ static void MatchFinder_MovePos(CMatchFi + distances + offset, maxLen) - distances); MOVE_POS_RET; + + #define SKIP_FOOTER \ +- SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS; +- +-static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(2) +- HASH2_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = 0; +- GET_MATCHES_FOOTER(offset, 1) +-} +- +-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = 0; +- GET_MATCHES_FOOTER(offset, 2) +-} +- +-static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 hash2Value, delta2, maxLen, offset; +- GET_MATCHES_HEADER(3) +- +- HASH3_CALC; +- +- delta2 = p->pos - p->hash[hash2Value]; +- curMatch = p->hash[kFix3HashSize + hashValue]; +- +- p->hash[hash2Value] = +- p->hash[kFix3HashSize + hashValue] = p->pos; +- +- +- maxLen = 2; +- offset = 0; +- if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) +- { +- for (; maxLen != lenLimit; maxLen++) +- if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) +- break; +- distances[0] = maxLen; +- distances[1] = delta2 - 1; +- offset = 2; +- if (maxLen == lenLimit) +- { +- SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); +- MOVE_POS_RET; +- } +- } +- GET_MATCHES_FOOTER(offset, maxLen) +-} ++ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MatchFinder_MovePos(p); + + static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) + { +@@ -583,108 +495,6 @@ static UInt32 Bt4_MatchFinder_GetMatches + GET_MATCHES_FOOTER(offset, maxLen) + } + +-static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; +- GET_MATCHES_HEADER(4) +- +- HASH4_CALC; +- +- delta2 = p->pos - p->hash[ hash2Value]; +- delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; +- curMatch = p->hash[kFix4HashSize + hashValue]; +- +- p->hash[ hash2Value] = +- p->hash[kFix3HashSize + hash3Value] = +- p->hash[kFix4HashSize + hashValue] = p->pos; +- +- maxLen = 1; +- offset = 0; +- if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) +- { +- distances[0] = maxLen = 2; +- distances[1] = delta2 - 1; +- offset = 2; +- } +- if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) +- { +- maxLen = 3; +- distances[offset + 1] = delta3 - 1; +- offset += 2; +- delta2 = delta3; +- } +- if (offset != 0) +- { +- for (; maxLen != lenLimit; maxLen++) +- if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) +- break; +- distances[offset - 2] = maxLen; +- if (maxLen == lenLimit) +- { +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS_RET; +- } +- } +- if (maxLen < 3) +- maxLen = 3; +- offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), +- distances + offset, maxLen) - (distances)); +- MOVE_POS_RET +-} +- +-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) +-{ +- UInt32 offset; +- GET_MATCHES_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p), +- distances, 2) - (distances)); +- MOVE_POS_RET +-} +- +-static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(2) +- HASH2_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- +-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- +-static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- UInt32 hash2Value; +- SKIP_HEADER(3) +- HASH3_CALC; +- curMatch = p->hash[kFix3HashSize + hashValue]; +- p->hash[hash2Value] = +- p->hash[kFix3HashSize + hashValue] = p->pos; +- SKIP_FOOTER +- } +- while (--num != 0); +-} +- + static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) + { + do +@@ -701,61 +511,12 @@ static void Bt4_MatchFinder_Skip(CMatchF + while (--num != 0); + } + +-static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- UInt32 hash2Value, hash3Value; +- SKIP_HEADER(4) +- HASH4_CALC; +- curMatch = p->hash[kFix4HashSize + hashValue]; +- p->hash[ hash2Value] = +- p->hash[kFix3HashSize + hash3Value] = +- p->hash[kFix4HashSize + hashValue] = p->pos; +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS +- } +- while (--num != 0); +-} +- +-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num) +-{ +- do +- { +- SKIP_HEADER(3) +- HASH_ZIP_CALC; +- curMatch = p->hash[hashValue]; +- p->hash[hashValue] = p->pos; +- p->son[p->cyclicBufferPos] = curMatch; +- MOVE_POS +- } +- while (--num != 0); +-} +- + void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) + { + vTable->Init = (Mf_Init_Func)MatchFinder_Init; + vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; + vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; + vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; +- if (!p->btMode) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip; +- } +- else if (p->numHashBytes == 2) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip; +- } +- else if (p->numHashBytes == 3) +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip; +- } +- else +- { +- vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; +- vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; +- } ++ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; ++ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; + } diff --git a/target/linux/generic/patches-4.3/532-jffs2_eofdetect.patch b/target/linux/generic/patches-4.3/532-jffs2_eofdetect.patch new file mode 100644 index 0000000..9cbe183 --- /dev/null +++ b/target/linux/generic/patches-4.3/532-jffs2_eofdetect.patch @@ -0,0 +1,56 @@ +--- a/fs/jffs2/build.c ++++ b/fs/jffs2/build.c +@@ -114,6 +114,16 @@ static int jffs2_build_filesystem(struct + dbg_fsbuild("scanned flash completely\n"); + jffs2_dbg_dump_block_lists_nolock(c); + ++ if (c->flags & (1 << 7)) { ++ printk("%s(): unlocking the mtd device... ", __func__); ++ mtd_unlock(c->mtd, 0, c->mtd->size); ++ printk("done.\n"); ++ ++ printk("%s(): erasing all blocks after the end marker... ", __func__); ++ jffs2_erase_pending_blocks(c, -1); ++ printk("done.\n"); ++ } ++ + dbg_fsbuild("pass 1 starting\n"); + c->flags |= JFFS2_SB_FLAG_BUILDING; + /* Now scan the directory tree, increasing nlink according to every dirent found. */ +--- a/fs/jffs2/scan.c ++++ b/fs/jffs2/scan.c +@@ -148,8 +148,14 @@ int jffs2_scan_medium(struct jffs2_sb_in + /* reset summary info for next eraseblock scan */ + jffs2_sum_reset_collected(s); + +- ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), +- buf_size, s); ++ if (c->flags & (1 << 7)) { ++ if (mtd_block_isbad(c->mtd, jeb->offset)) ++ ret = BLK_STATE_BADBLOCK; ++ else ++ ret = BLK_STATE_ALLFF; ++ } else ++ ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), ++ buf_size, s); + + if (ret < 0) + goto out; +@@ -561,6 +567,17 @@ full_scan: + return err; + } + ++ if ((buf[0] == 0xde) && ++ (buf[1] == 0xad) && ++ (buf[2] == 0xc0) && ++ (buf[3] == 0xde)) { ++ /* end of filesystem. erase everything after this point */ ++ printk("%s(): End of filesystem marker found at 0x%x\n", __func__, jeb->offset); ++ c->flags |= (1 << 7); ++ ++ return BLK_STATE_ALLFF; ++ } ++ + /* We temporarily use 'ofs' as a pointer into the buffer/jeb */ + ofs = 0; + max_ofs = EMPTY_SCAN_SIZE(c->sector_size); diff --git a/target/linux/generic/patches-4.3/540-crypto-xz-decompression-support.patch b/target/linux/generic/patches-4.3/540-crypto-xz-decompression-support.patch new file mode 100644 index 0000000..4e385b6 --- /dev/null +++ b/target/linux/generic/patches-4.3/540-crypto-xz-decompression-support.patch @@ -0,0 +1,146 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -1536,6 +1536,13 @@ config CRYPTO_LZ4HC + help + This is the LZ4 high compression mode algorithm. + ++config CRYPTO_XZ ++ tristate "XZ compression algorithm" ++ select CRYPTO_ALGAPI ++ select XZ_DEC ++ help ++ This is the XZ algorithm. Only decompression is supported for now. ++ + comment "Random Number Generation" + + config CRYPTO_ANSI_CPRNG +--- a/crypto/Makefile ++++ b/crypto/Makefile +@@ -103,6 +103,7 @@ obj-$(CONFIG_CRYPTO_AUTHENC) += authenc. + obj-$(CONFIG_CRYPTO_LZO) += lzo.o + obj-$(CONFIG_CRYPTO_LZ4) += lz4.o + obj-$(CONFIG_CRYPTO_LZ4HC) += lz4hc.o ++obj-$(CONFIG_CRYPTO_XZ) += xz.o + obj-$(CONFIG_CRYPTO_842) += 842.o + obj-$(CONFIG_CRYPTO_RNG2) += rng.o + obj-$(CONFIG_CRYPTO_ANSI_CPRNG) += ansi_cprng.o +--- /dev/null ++++ b/crypto/xz.c +@@ -0,0 +1,117 @@ ++/* ++ * Cryptographic API. ++ * ++ * XZ decompression support. ++ * ++ * Copyright (c) 2012 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published by ++ * the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct xz_comp_ctx { ++ struct xz_dec *decomp_state; ++ struct xz_buf decomp_buf; ++}; ++ ++static int crypto_xz_decomp_init(struct xz_comp_ctx *ctx) ++{ ++ ctx->decomp_state = xz_dec_init(XZ_SINGLE, 0); ++ if (!ctx->decomp_state) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static void crypto_xz_decomp_exit(struct xz_comp_ctx *ctx) ++{ ++ xz_dec_end(ctx->decomp_state); ++} ++ ++static int crypto_xz_init(struct crypto_tfm *tfm) ++{ ++ struct xz_comp_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ return crypto_xz_decomp_init(ctx); ++} ++ ++static void crypto_xz_exit(struct crypto_tfm *tfm) ++{ ++ struct xz_comp_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ crypto_xz_decomp_exit(ctx); ++} ++ ++static int crypto_xz_compress(struct crypto_tfm *tfm, const u8 *src, ++ unsigned int slen, u8 *dst, unsigned int *dlen) ++{ ++ return -EOPNOTSUPP; ++} ++ ++static int crypto_xz_decompress(struct crypto_tfm *tfm, const u8 *src, ++ unsigned int slen, u8 *dst, unsigned int *dlen) ++{ ++ struct xz_comp_ctx *dctx = crypto_tfm_ctx(tfm); ++ struct xz_buf *xz_buf = &dctx->decomp_buf; ++ int ret; ++ ++ memset(xz_buf, '\0', sizeof(struct xz_buf)); ++ ++ xz_buf->in = (u8 *) src; ++ xz_buf->in_pos = 0; ++ xz_buf->in_size = slen; ++ xz_buf->out = (u8 *) dst; ++ xz_buf->out_pos = 0; ++ xz_buf->out_size = *dlen; ++ ++ ret = xz_dec_run(dctx->decomp_state, xz_buf); ++ if (ret != XZ_STREAM_END) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ *dlen = xz_buf->out_pos; ++ ret = 0; ++ ++out: ++ return ret; ++} ++ ++static struct crypto_alg crypto_xz_alg = { ++ .cra_name = "xz", ++ .cra_flags = CRYPTO_ALG_TYPE_COMPRESS, ++ .cra_ctxsize = sizeof(struct xz_comp_ctx), ++ .cra_module = THIS_MODULE, ++ .cra_list = LIST_HEAD_INIT(crypto_xz_alg.cra_list), ++ .cra_init = crypto_xz_init, ++ .cra_exit = crypto_xz_exit, ++ .cra_u = { .compress = { ++ .coa_compress = crypto_xz_compress, ++ .coa_decompress = crypto_xz_decompress } } ++}; ++ ++static int __init crypto_xz_mod_init(void) ++{ ++ return crypto_register_alg(&crypto_xz_alg); ++} ++ ++static void __exit crypto_xz_mod_exit(void) ++{ ++ crypto_unregister_alg(&crypto_xz_alg); ++} ++ ++module_init(crypto_xz_mod_init); ++module_exit(crypto_xz_mod_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Crypto XZ decompression support"); ++MODULE_AUTHOR("Gabor Juhos "); diff --git a/target/linux/generic/patches-4.3/541-ubifs-xz-decompression-support.patch b/target/linux/generic/patches-4.3/541-ubifs-xz-decompression-support.patch new file mode 100644 index 0000000..f85689c --- /dev/null +++ b/target/linux/generic/patches-4.3/541-ubifs-xz-decompression-support.patch @@ -0,0 +1,92 @@ +--- a/fs/ubifs/Kconfig ++++ b/fs/ubifs/Kconfig +@@ -5,8 +5,10 @@ config UBIFS_FS + select CRYPTO if UBIFS_FS_ADVANCED_COMPR + select CRYPTO if UBIFS_FS_LZO + select CRYPTO if UBIFS_FS_ZLIB ++ select CRYPTO if UBIFS_FS_XZ + select CRYPTO_LZO if UBIFS_FS_LZO + select CRYPTO_DEFLATE if UBIFS_FS_ZLIB ++ select CRYPTO_XZ if UBIFS_FS_XZ + depends on MTD_UBI + help + UBIFS is a file system for flash devices which works on top of UBI. +@@ -35,3 +37,12 @@ config UBIFS_FS_ZLIB + default y + help + Zlib compresses better than LZO but it is slower. Say 'Y' if unsure. ++ ++config UBIFS_FS_XZ ++ bool "XZ decompression support" if UBIFS_FS_ADVANCED_COMPR ++ depends on UBIFS_FS ++ default y ++ help ++ XZ compresses better the ZLIB but it is slower.. ++ Say 'Y' if unsure. ++ +--- a/fs/ubifs/compress.c ++++ b/fs/ubifs/compress.c +@@ -71,6 +71,24 @@ static struct ubifs_compressor zlib_comp + }; + #endif + ++#ifdef CONFIG_UBIFS_FS_XZ ++static DEFINE_MUTEX(xz_enc_mutex); ++static DEFINE_MUTEX(xz_dec_mutex); ++ ++static struct ubifs_compressor xz_compr = { ++ .compr_type = UBIFS_COMPR_XZ, ++ .comp_mutex = &xz_enc_mutex, ++ .decomp_mutex = &xz_dec_mutex, ++ .name = "xz", ++ .capi_name = "xz", ++}; ++#else ++static struct ubifs_compressor xz_compr = { ++ .compr_type = UBIFS_COMPR_XZ, ++ .name = "xz", ++}; ++#endif ++ + /* All UBIFS compressors */ + struct ubifs_compressor *ubifs_compressors[UBIFS_COMPR_TYPES_CNT]; + +@@ -232,9 +250,15 @@ int __init ubifs_compressors_init(void) + if (err) + goto out_lzo; + ++ err = compr_init(&xz_compr); ++ if (err) ++ goto out_zlib; ++ + ubifs_compressors[UBIFS_COMPR_NONE] = &none_compr; + return 0; + ++out_zlib: ++ compr_exit(&zlib_compr); + out_lzo: + compr_exit(&lzo_compr); + return err; +@@ -247,4 +271,5 @@ void ubifs_compressors_exit(void) + { + compr_exit(&lzo_compr); + compr_exit(&zlib_compr); ++ compr_exit(&xz_compr); + } +--- a/fs/ubifs/ubifs-media.h ++++ b/fs/ubifs/ubifs-media.h +@@ -332,12 +332,14 @@ enum { + * UBIFS_COMPR_NONE: no compression + * UBIFS_COMPR_LZO: LZO compression + * UBIFS_COMPR_ZLIB: ZLIB compression ++ * UBIFS_COMPR_XZ: XZ compression + * UBIFS_COMPR_TYPES_CNT: count of supported compression types + */ + enum { + UBIFS_COMPR_NONE, + UBIFS_COMPR_LZO, + UBIFS_COMPR_ZLIB, ++ UBIFS_COMPR_XZ, + UBIFS_COMPR_TYPES_CNT, + }; + diff --git a/target/linux/generic/patches-4.3/551-ubifs-fix-default-compression-selection.patch b/target/linux/generic/patches-4.3/551-ubifs-fix-default-compression-selection.patch new file mode 100644 index 0000000..1b0f307 --- /dev/null +++ b/target/linux/generic/patches-4.3/551-ubifs-fix-default-compression-selection.patch @@ -0,0 +1,29 @@ +--- a/fs/ubifs/sb.c ++++ b/fs/ubifs/sb.c +@@ -63,6 +63,17 @@ + /* Default time granularity in nanoseconds */ + #define DEFAULT_TIME_GRAN 1000000000 + ++static int get_default_compressor(void) ++{ ++ if (ubifs_compr_present(UBIFS_COMPR_LZO)) ++ return UBIFS_COMPR_LZO; ++ ++ if (ubifs_compr_present(UBIFS_COMPR_ZLIB)) ++ return UBIFS_COMPR_ZLIB; ++ ++ return UBIFS_COMPR_NONE; ++} ++ + /** + * create_default_filesystem - format empty UBI volume. + * @c: UBIFS file-system description object +@@ -183,7 +194,7 @@ static int create_default_filesystem(str + if (c->mount_opts.override_compr) + sup->default_compr = cpu_to_le16(c->mount_opts.compr_type); + else +- sup->default_compr = cpu_to_le16(UBIFS_COMPR_LZO); ++ sup->default_compr = cpu_to_le16(get_default_compressor()); + + generate_random_uuid(sup->uuid); + diff --git a/target/linux/generic/patches-4.3/600-netfilter_conntrack_flush.patch b/target/linux/generic/patches-4.3/600-netfilter_conntrack_flush.patch new file mode 100644 index 0000000..8794739 --- /dev/null +++ b/target/linux/generic/patches-4.3/600-netfilter_conntrack_flush.patch @@ -0,0 +1,86 @@ +--- a/net/netfilter/nf_conntrack_standalone.c ++++ b/net/netfilter/nf_conntrack_standalone.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #ifdef CONFIG_SYSCTL + #include +@@ -288,10 +289,66 @@ static int ct_open(struct inode *inode, + sizeof(struct ct_iter_state)); + } + ++struct kill_request { ++ u16 family; ++ union nf_inet_addr addr; ++}; ++ ++static int kill_matching(struct nf_conn *i, void *data) ++{ ++ struct kill_request *kr = data; ++ struct nf_conntrack_tuple *t1 = &i->tuplehash[IP_CT_DIR_ORIGINAL].tuple; ++ struct nf_conntrack_tuple *t2 = &i->tuplehash[IP_CT_DIR_REPLY].tuple; ++ ++ if (!kr->family) ++ return 1; ++ ++ if (t1->src.l3num != kr->family) ++ return 0; ++ ++ return (nf_inet_addr_cmp(&kr->addr, &t1->src.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t1->dst.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t2->src.u3) || ++ nf_inet_addr_cmp(&kr->addr, &t2->dst.u3)); ++} ++ ++static ssize_t ct_file_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *seq = file->private_data; ++ struct net *net = seq_file_net(seq); ++ struct kill_request kr = { }; ++ char req[INET6_ADDRSTRLEN] = { }; ++ ++ if (count == 0) ++ return 0; ++ ++ if (count >= INET6_ADDRSTRLEN) ++ count = INET6_ADDRSTRLEN - 1; ++ ++ if (copy_from_user(req, buf, count)) ++ return -EFAULT; ++ ++ if (strnchr(req, count, ':')) { ++ kr.family = AF_INET6; ++ if (!in6_pton(req, count, (void *)&kr.addr, '\n', NULL)) ++ return -EINVAL; ++ } else if (strnchr(req, count, '.')) { ++ kr.family = AF_INET; ++ if (!in4_pton(req, count, (void *)&kr.addr, '\n', NULL)) ++ return -EINVAL; ++ } ++ ++ nf_ct_iterate_cleanup(net, kill_matching, &kr, 0, 0); ++ ++ return count; ++} ++ + static const struct file_operations ct_file_ops = { + .owner = THIS_MODULE, + .open = ct_open, + .read = seq_read, ++ .write = ct_file_write, + .llseek = seq_lseek, + .release = seq_release_net, + }; +@@ -393,7 +450,7 @@ static int nf_conntrack_standalone_init_ + { + struct proc_dir_entry *pde; + +- pde = proc_create("nf_conntrack", 0440, net->proc_net, &ct_file_ops); ++ pde = proc_create("nf_conntrack", 0660, net->proc_net, &ct_file_ops); + if (!pde) + goto out_nf_conntrack; + diff --git a/target/linux/generic/patches-4.3/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/patches-4.3/610-netfilter_match_bypass_default_checks.patch new file mode 100644 index 0000000..c7908a3 --- /dev/null +++ b/target/linux/generic/patches-4.3/610-netfilter_match_bypass_default_checks.patch @@ -0,0 +1,93 @@ +--- a/include/uapi/linux/netfilter_ipv4/ip_tables.h ++++ b/include/uapi/linux/netfilter_ipv4/ip_tables.h +@@ -87,6 +87,7 @@ struct ipt_ip { + #define IPT_F_FRAG 0x01 /* Set if rule is a fragment rule */ + #define IPT_F_GOTO 0x02 /* Set if jump is a goto */ + #define IPT_F_MASK 0x03 /* All possible flag bits mask. */ ++#define IPT_F_NO_DEF_MATCH 0x80 /* Internal: no default match rules present */ + + /* Values for "inv" field in struct ipt_ip. */ + #define IPT_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -82,6 +82,9 @@ ip_packet_match(const struct iphdr *ip, + + #define FWINV(bool, invflg) ((bool) ^ !!(ipinfo->invflags & (invflg))) + ++ if (ipinfo->flags & IPT_F_NO_DEF_MATCH) ++ return true; ++ + if (FWINV((ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, + IPT_INV_SRCIP) || + FWINV((ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, +@@ -135,6 +138,29 @@ ip_packet_match(const struct iphdr *ip, + return true; + } + ++static void ++ip_checkdefault(struct ipt_ip *ip) ++{ ++ static const char iface_mask[IFNAMSIZ] = {}; ++ ++ if (ip->invflags || ip->flags & IPT_F_FRAG) ++ return; ++ ++ if (memcmp(ip->iniface_mask, iface_mask, IFNAMSIZ) != 0) ++ return; ++ ++ if (memcmp(ip->outiface_mask, iface_mask, IFNAMSIZ) != 0) ++ return; ++ ++ if (ip->smsk.s_addr || ip->dmsk.s_addr) ++ return; ++ ++ if (ip->proto) ++ return; ++ ++ ip->flags |= IPT_F_NO_DEF_MATCH; ++} ++ + static bool + ip_checkentry(const struct ipt_ip *ip) + { +@@ -568,7 +594,7 @@ static void cleanup_match(struct xt_entr + } + + static int +-check_entry(const struct ipt_entry *e, const char *name) ++check_entry(struct ipt_entry *e, const char *name) + { + const struct xt_entry_target *t; + +@@ -577,6 +603,8 @@ check_entry(const struct ipt_entry *e, c + return -EINVAL; + } + ++ ip_checkdefault(&e->ip); ++ + if (e->target_offset + sizeof(struct xt_entry_target) > + e->next_offset) + return -EINVAL; +@@ -943,6 +971,7 @@ copy_entries_to_user(unsigned int total_ + const struct xt_table_info *private = table->private; + int ret = 0; + const void *loc_cpu_entry; ++ u8 flags; + + counters = alloc_counters(table); + if (IS_ERR(counters)) +@@ -969,6 +998,14 @@ copy_entries_to_user(unsigned int total_ + ret = -EFAULT; + goto free_counters; + } ++ ++ flags = e->ip.flags & IPT_F_MASK; ++ if (copy_to_user(userptr + off ++ + offsetof(struct ipt_entry, ip.flags), ++ &flags, sizeof(flags)) != 0) { ++ ret = -EFAULT; ++ goto free_counters; ++ } + + for (i = sizeof(struct ipt_entry); + i < e->target_offset; diff --git a/target/linux/generic/patches-4.3/611-netfilter_match_bypass_default_table.patch b/target/linux/generic/patches-4.3/611-netfilter_match_bypass_default_table.patch new file mode 100644 index 0000000..c438519 --- /dev/null +++ b/target/linux/generic/patches-4.3/611-netfilter_match_bypass_default_table.patch @@ -0,0 +1,106 @@ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -308,6 +308,33 @@ struct ipt_entry *ipt_next_entry(const s + return (void *)entry + entry->next_offset; + } + ++static bool ++ipt_handle_default_rule(struct ipt_entry *e, unsigned int *verdict) ++{ ++ struct xt_entry_target *t; ++ struct xt_standard_target *st; ++ ++ if (e->target_offset != sizeof(struct ipt_entry)) ++ return false; ++ ++ if (!(e->ip.flags & IPT_F_NO_DEF_MATCH)) ++ return false; ++ ++ t = ipt_get_target(e); ++ if (t->u.kernel.target->target) ++ return false; ++ ++ st = (struct xt_standard_target *) t; ++ if (st->verdict == XT_RETURN) ++ return false; ++ ++ if (st->verdict >= 0) ++ return false; ++ ++ *verdict = (unsigned)(-st->verdict) - 1; ++ return true; ++} ++ + /* Returns one of the generic firewall policies, like NF_ACCEPT. */ + unsigned int + ipt_do_table(struct sk_buff *skb, +@@ -328,27 +355,8 @@ ipt_do_table(struct sk_buff *skb, + unsigned int addend; + + /* Initialization */ +- stackidx = 0; +- ip = ip_hdr(skb); +- indev = state->in ? state->in->name : nulldevname; +- outdev = state->out ? state->out->name : nulldevname; +- /* We handle fragments by dealing with the first fragment as +- * if it was a normal packet. All other fragments are treated +- * normally, except that they will NEVER match rules that ask +- * things we don't know, ie. tcp syn flag or ports). If the +- * rule is also a fragment-specific rule, non-fragments won't +- * match it. */ +- acpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET; +- acpar.thoff = ip_hdrlen(skb); +- acpar.hotdrop = false; +- acpar.in = state->in; +- acpar.out = state->out; +- acpar.family = NFPROTO_IPV4; +- acpar.hooknum = hook; +- + IP_NF_ASSERT(table->valid_hooks & (1 << hook)); + local_bh_disable(); +- addend = xt_write_recseq_begin(); + private = table->private; + cpu = smp_processor_id(); + /* +@@ -357,6 +365,20 @@ ipt_do_table(struct sk_buff *skb, + */ + smp_read_barrier_depends(); + table_base = private->entries; ++ ++ e = get_entry(table_base, private->hook_entry[hook]); ++ if (ipt_handle_default_rule(e, &verdict)) { ++ ADD_COUNTER(e->counters, skb->len, 1); ++ local_bh_enable(); ++ return verdict; ++ } ++ ++ stackidx = 0; ++ ip = ip_hdr(skb); ++ indev = state->in ? state->in->name : nulldevname; ++ outdev = state->out ? state->out->name : nulldevname; ++ ++ addend = xt_write_recseq_begin(); + jumpstack = (struct ipt_entry **)private->jumpstack[cpu]; + + /* Switch to alternate jumpstack if we're being invoked via TEE. +@@ -369,7 +391,19 @@ ipt_do_table(struct sk_buff *skb, + if (static_key_false(&xt_tee_enabled)) + jumpstack += private->stacksize * __this_cpu_read(nf_skb_duplicated); + +- e = get_entry(table_base, private->hook_entry[hook]); ++ /* We handle fragments by dealing with the first fragment as ++ * if it was a normal packet. All other fragments are treated ++ * normally, except that they will NEVER match rules that ask ++ * things we don't know, ie. tcp syn flag or ports). If the ++ * rule is also a fragment-specific rule, non-fragments won't ++ * match it. */ ++ acpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET; ++ acpar.thoff = ip_hdrlen(skb); ++ acpar.hotdrop = false; ++ acpar.in = state->in; ++ acpar.out = state->out; ++ acpar.family = NFPROTO_IPV4; ++ acpar.hooknum = hook; + + pr_debug("Entering %s(hook %u), UF %p\n", + table->name, hook, diff --git a/target/linux/generic/patches-4.3/612-netfilter_match_reduce_memory_access.patch b/target/linux/generic/patches-4.3/612-netfilter_match_reduce_memory_access.patch new file mode 100644 index 0000000..72172d8 --- /dev/null +++ b/target/linux/generic/patches-4.3/612-netfilter_match_reduce_memory_access.patch @@ -0,0 +1,16 @@ +--- a/net/ipv4/netfilter/ip_tables.c ++++ b/net/ipv4/netfilter/ip_tables.c +@@ -85,9 +85,11 @@ ip_packet_match(const struct iphdr *ip, + if (ipinfo->flags & IPT_F_NO_DEF_MATCH) + return true; + +- if (FWINV((ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, ++ if (FWINV(ipinfo->smsk.s_addr && ++ (ip->saddr&ipinfo->smsk.s_addr) != ipinfo->src.s_addr, + IPT_INV_SRCIP) || +- FWINV((ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, ++ FWINV(ipinfo->dmsk.s_addr && ++ (ip->daddr&ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr, + IPT_INV_DSTIP)) { + dprintf("Source or dest mismatch.\n"); + diff --git a/target/linux/generic/patches-4.3/613-netfilter_optional_tcp_window_check.patch b/target/linux/generic/patches-4.3/613-netfilter_optional_tcp_window_check.patch new file mode 100644 index 0000000..3740dd7 --- /dev/null +++ b/target/linux/generic/patches-4.3/613-netfilter_optional_tcp_window_check.patch @@ -0,0 +1,36 @@ +--- a/net/netfilter/nf_conntrack_proto_tcp.c ++++ b/net/netfilter/nf_conntrack_proto_tcp.c +@@ -33,6 +33,9 @@ + #include + #include + ++/* Do not check the TCP window for incoming packets */ ++static int nf_ct_tcp_no_window_check __read_mostly = 1; ++ + /* "Be conservative in what you do, + be liberal in what you accept from others." + If it's non-zero, we mark only out of window RST segments as INVALID. */ +@@ -515,6 +518,9 @@ static bool tcp_in_window(const struct n + s32 receiver_offset; + bool res, in_recv_win; + ++ if (nf_ct_tcp_no_window_check) ++ return true; ++ + /* + * Get the required data from the packet. + */ +@@ -1481,6 +1487,13 @@ static struct ctl_table tcp_sysctl_table + .mode = 0644, + .proc_handler = proc_dointvec, + }, ++ { ++ .procname = "nf_conntrack_tcp_no_window_check", ++ .data = &nf_ct_tcp_no_window_check, ++ .maxlen = sizeof(unsigned int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec, ++ }, + { } + }; + diff --git a/target/linux/generic/patches-4.3/615-netfilter_add_xt_id_match.patch b/target/linux/generic/patches-4.3/615-netfilter_add_xt_id_match.patch new file mode 100644 index 0000000..a8fcb8f --- /dev/null +++ b/target/linux/generic/patches-4.3/615-netfilter_add_xt_id_match.patch @@ -0,0 +1,95 @@ +--- a/include/uapi/linux/netfilter/Kbuild ++++ b/include/uapi/linux/netfilter/Kbuild +@@ -55,6 +55,7 @@ header-y += xt_ecn.h + header-y += xt_esp.h + header-y += xt_hashlimit.h + header-y += xt_helper.h ++header-y += xt_id.h + header-y += xt_ipcomp.h + header-y += xt_iprange.h + header-y += xt_ipvs.h +--- /dev/null ++++ b/include/uapi/linux/netfilter/xt_id.h +@@ -0,0 +1,8 @@ ++#ifndef _XT_ID_H ++#define _XT_ID_H ++ ++struct xt_id_info { ++ u32 id; ++}; ++ ++#endif /* XT_ID_H */ +--- a/net/netfilter/Kconfig ++++ b/net/netfilter/Kconfig +@@ -1179,6 +1179,13 @@ config NETFILTER_XT_MATCH_IPCOMP + + To compile it as a module, choose M here. If unsure, say N. + ++config NETFILTER_XT_MATCH_ID ++ tristate '"id" match support' ++ depends on NETFILTER_ADVANCED ++ ---help--- ++ This option adds a `id' dummy-match, which allows you to put ++ numeric IDs into your iptables ruleset. ++ + config NETFILTER_XT_MATCH_IPRANGE + tristate '"iprange" address range match support' + depends on NETFILTER_ADVANCED +--- a/net/netfilter/Makefile ++++ b/net/netfilter/Makefile +@@ -146,6 +146,7 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_ESP) += + obj-$(CONFIG_NETFILTER_XT_MATCH_HASHLIMIT) += xt_hashlimit.o + obj-$(CONFIG_NETFILTER_XT_MATCH_HELPER) += xt_helper.o + obj-$(CONFIG_NETFILTER_XT_MATCH_HL) += xt_hl.o ++obj-$(CONFIG_NETFILTER_XT_MATCH_ID) += xt_id.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPCOMP) += xt_ipcomp.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPRANGE) += xt_iprange.o + obj-$(CONFIG_NETFILTER_XT_MATCH_IPVS) += xt_ipvs.o +--- /dev/null ++++ b/net/netfilter/xt_id.c +@@ -0,0 +1,45 @@ ++/* ++ * Implements a dummy match to allow attaching IDs to rules ++ * ++ * 2014-08-01 Jo-Philipp Wich ++ */ ++ ++#include ++#include ++#include ++#include ++ ++MODULE_AUTHOR("Jo-Philipp Wich "); ++MODULE_DESCRIPTION("Xtables: No-op match which can be tagged with a 32bit ID"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("ipt_id"); ++MODULE_ALIAS("ip6t_id"); ++ ++static bool ++id_mt(const struct sk_buff *skb, struct xt_action_param *par) ++{ ++ /* We always match */ ++ return true; ++} ++ ++static struct xt_match id_mt_reg __read_mostly = { ++ .name = "id", ++ .revision = 0, ++ .family = NFPROTO_UNSPEC, ++ .match = id_mt, ++ .matchsize = sizeof(struct xt_id_info), ++ .me = THIS_MODULE, ++}; ++ ++static int __init id_mt_init(void) ++{ ++ return xt_register_match(&id_mt_reg); ++} ++ ++static void __exit id_mt_exit(void) ++{ ++ xt_unregister_match(&id_mt_reg); ++} ++ ++module_init(id_mt_init); ++module_exit(id_mt_exit); diff --git a/target/linux/generic/patches-4.3/616-net_optimize_xfrm_calls.patch b/target/linux/generic/patches-4.3/616-net_optimize_xfrm_calls.patch new file mode 100644 index 0000000..2a64d54 --- /dev/null +++ b/target/linux/generic/patches-4.3/616-net_optimize_xfrm_calls.patch @@ -0,0 +1,12 @@ +--- a/net/netfilter/nf_nat_core.c ++++ b/net/netfilter/nf_nat_core.c +@@ -90,6 +90,9 @@ int nf_xfrm_me_harder(struct sk_buff *sk + struct dst_entry *dst; + int err; + ++ if (skb->dev && !dev_net(skb->dev)->xfrm.policy_count[XFRM_POLICY_OUT]) ++ return 0; ++ + err = xfrm_decode_session(skb, &fl, family); + if (err < 0) + return err; diff --git a/target/linux/generic/patches-4.3/620-sched_esfq.patch b/target/linux/generic/patches-4.3/620-sched_esfq.patch new file mode 100644 index 0000000..e1b473b --- /dev/null +++ b/target/linux/generic/patches-4.3/620-sched_esfq.patch @@ -0,0 +1,791 @@ +--- a/include/uapi/linux/pkt_sched.h ++++ b/include/uapi/linux/pkt_sched.h +@@ -226,6 +226,33 @@ struct tc_sfq_xstats { + __s32 allot; + }; + ++/* ESFQ section */ ++ ++enum ++{ ++ /* traditional */ ++ TCA_SFQ_HASH_CLASSIC, ++ TCA_SFQ_HASH_DST, ++ TCA_SFQ_HASH_SRC, ++ TCA_SFQ_HASH_FWMARK, ++ /* conntrack */ ++ TCA_SFQ_HASH_CTORIGDST, ++ TCA_SFQ_HASH_CTORIGSRC, ++ TCA_SFQ_HASH_CTREPLDST, ++ TCA_SFQ_HASH_CTREPLSRC, ++ TCA_SFQ_HASH_CTNATCHG, ++}; ++ ++struct tc_esfq_qopt ++{ ++ unsigned quantum; /* Bytes per round allocated to flow */ ++ int perturb_period; /* Period of hash perturbation */ ++ __u32 limit; /* Maximal packets in queue */ ++ unsigned divisor; /* Hash divisor */ ++ unsigned flows; /* Maximal number of flows */ ++ unsigned hash_kind; /* Hash function to use for flow identification */ ++}; ++ + /* RED section */ + + enum { +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -149,6 +149,37 @@ config NET_SCH_SFQ + To compile this code as a module, choose M here: the + module will be called sch_sfq. + ++config NET_SCH_ESFQ ++ tristate "Enhanced Stochastic Fairness Queueing (ESFQ)" ++ ---help--- ++ Say Y here if you want to use the Enhanced Stochastic Fairness ++ Queueing (ESFQ) packet scheduling algorithm for some of your network ++ devices or as a leaf discipline for a classful qdisc such as HTB or ++ CBQ (see the top of for details and ++ references to the SFQ algorithm). ++ ++ This is an enchanced SFQ version which allows you to control some ++ hardcoded values in the SFQ scheduler. ++ ++ ESFQ also adds control of the hash function used to identify packet ++ flows. The original SFQ discipline hashes by connection; ESFQ add ++ several other hashing methods, such as by src IP or by dst IP, which ++ can be more fair to users in some networking situations. ++ ++ To compile this code as a module, choose M here: the ++ module will be called sch_esfq. ++ ++config NET_SCH_ESFQ_NFCT ++ bool "Connection Tracking Hash Types" ++ depends on NET_SCH_ESFQ && NF_CONNTRACK ++ ---help--- ++ Say Y here to enable support for hashing based on netfilter connection ++ tracking information. This is useful for a router that is also using ++ NAT to connect privately-addressed hosts to the Internet. If you want ++ to provide fair distribution of upstream bandwidth, ESFQ must use ++ connection tracking information, since all outgoing packets will share ++ the same source address. ++ + config NET_SCH_TEQL + tristate "True Link Equalizer (TEQL)" + ---help--- +--- a/net/sched/Makefile ++++ b/net/sched/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_NET_SCH_INGRESS) += sch_ing + obj-$(CONFIG_NET_SCH_DSMARK) += sch_dsmark.o + obj-$(CONFIG_NET_SCH_SFB) += sch_sfb.o + obj-$(CONFIG_NET_SCH_SFQ) += sch_sfq.o ++obj-$(CONFIG_NET_SCH_ESFQ) += sch_esfq.o + obj-$(CONFIG_NET_SCH_TBF) += sch_tbf.o + obj-$(CONFIG_NET_SCH_TEQL) += sch_teql.o + obj-$(CONFIG_NET_SCH_PRIO) += sch_prio.o +--- /dev/null ++++ b/net/sched/sch_esfq.c +@@ -0,0 +1,702 @@ ++/* ++ * net/sched/sch_esfq.c Extended Stochastic Fairness Queueing discipline. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Authors: Alexey Kuznetsov, ++ * ++ * Changes: Alexander Atanasov, ++ * Added dynamic depth,limit,divisor,hash_kind options. ++ * Added dst and src hashes. ++ * ++ * Alexander Clouter, ++ * Ported ESFQ to Linux 2.6. ++ * ++ * Corey Hickey, ++ * Maintenance of the Linux 2.6 port. ++ * Added fwmark hash (thanks to Robert Kurjata). ++ * Added usage of jhash. ++ * Added conntrack support. ++ * Added ctnatchg hash (thanks to Ben Pfountz). ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++#include ++#endif ++ ++/* Stochastic Fairness Queuing algorithm. ++ For more comments look at sch_sfq.c. ++ The difference is that you can change limit, depth, ++ hash table size and choose alternate hash types. ++ ++ classic: same as in sch_sfq.c ++ dst: destination IP address ++ src: source IP address ++ fwmark: netfilter mark value ++ ctorigdst: original destination IP address ++ ctorigsrc: original source IP address ++ ctrepldst: reply destination IP address ++ ctreplsrc: reply source IP ++ ++*/ ++ ++#define ESFQ_HEAD 0 ++#define ESFQ_TAIL 1 ++ ++/* This type should contain at least SFQ_DEPTH*2 values */ ++typedef unsigned int esfq_index; ++ ++struct esfq_head ++{ ++ esfq_index next; ++ esfq_index prev; ++}; ++ ++struct esfq_sched_data ++{ ++/* Parameters */ ++ int perturb_period; ++ unsigned quantum; /* Allotment per round: MUST BE >= MTU */ ++ int limit; ++ unsigned depth; ++ unsigned hash_divisor; ++ unsigned hash_kind; ++/* Variables */ ++ struct timer_list perturb_timer; ++ int perturbation; ++ esfq_index tail; /* Index of current slot in round */ ++ esfq_index max_depth; /* Maximal depth */ ++ ++ esfq_index *ht; /* Hash table */ ++ esfq_index *next; /* Active slots link */ ++ short *allot; /* Current allotment per slot */ ++ unsigned short *hash; /* Hash value indexed by slots */ ++ struct sk_buff_head *qs; /* Slot queue */ ++ struct esfq_head *dep; /* Linked list of slots, indexed by depth */ ++}; ++ ++/* This contains the info we will hash. */ ++struct esfq_packet_info ++{ ++ u32 proto; /* protocol or port */ ++ u32 src; /* source from packet header */ ++ u32 dst; /* destination from packet header */ ++ u32 ctorigsrc; /* original source from conntrack */ ++ u32 ctorigdst; /* original destination from conntrack */ ++ u32 ctreplsrc; /* reply source from conntrack */ ++ u32 ctrepldst; /* reply destination from conntrack */ ++ u32 mark; /* netfilter mark (fwmark) */ ++}; ++ ++static __inline__ unsigned esfq_jhash_1word(struct esfq_sched_data *q,u32 a) ++{ ++ return jhash_1word(a, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static __inline__ unsigned esfq_jhash_2words(struct esfq_sched_data *q, u32 a, u32 b) ++{ ++ return jhash_2words(a, b, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static __inline__ unsigned esfq_jhash_3words(struct esfq_sched_data *q, u32 a, u32 b, u32 c) ++{ ++ return jhash_3words(a, b, c, q->perturbation) & (q->hash_divisor-1); ++} ++ ++static unsigned esfq_hash(struct esfq_sched_data *q, struct sk_buff *skb) ++{ ++ struct esfq_packet_info info; ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ enum ip_conntrack_info ctinfo; ++ struct nf_conn *ct = nf_ct_get(skb, &ctinfo); ++#endif ++ ++ switch (skb->protocol) { ++ case __constant_htons(ETH_P_IP): ++ { ++ struct iphdr *iph = ip_hdr(skb); ++ info.dst = iph->daddr; ++ info.src = iph->saddr; ++ if (!(iph->frag_off&htons(IP_MF|IP_OFFSET)) && ++ (iph->protocol == IPPROTO_TCP || ++ iph->protocol == IPPROTO_UDP || ++ iph->protocol == IPPROTO_SCTP || ++ iph->protocol == IPPROTO_DCCP || ++ iph->protocol == IPPROTO_ESP)) ++ info.proto = *(((u32*)iph) + iph->ihl); ++ else ++ info.proto = iph->protocol; ++ break; ++ } ++ case __constant_htons(ETH_P_IPV6): ++ { ++ struct ipv6hdr *iph = ipv6_hdr(skb); ++ /* Hash ipv6 addresses into a u32. This isn't ideal, ++ * but the code is simple. */ ++ info.dst = jhash2(iph->daddr.s6_addr32, 4, q->perturbation); ++ info.src = jhash2(iph->saddr.s6_addr32, 4, q->perturbation); ++ if (iph->nexthdr == IPPROTO_TCP || ++ iph->nexthdr == IPPROTO_UDP || ++ iph->nexthdr == IPPROTO_SCTP || ++ iph->nexthdr == IPPROTO_DCCP || ++ iph->nexthdr == IPPROTO_ESP) ++ info.proto = *(u32*)&iph[1]; ++ else ++ info.proto = iph->nexthdr; ++ break; ++ } ++ default: ++ info.dst = (u32)(unsigned long)skb_dst(skb); ++ info.src = (u32)(unsigned long)skb->sk; ++ info.proto = skb->protocol; ++ } ++ ++ info.mark = skb->mark; ++ ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ /* defaults if there is no conntrack info */ ++ info.ctorigsrc = info.src; ++ info.ctorigdst = info.dst; ++ info.ctreplsrc = info.dst; ++ info.ctrepldst = info.src; ++ /* collect conntrack info */ ++ if (ct && ct != &nf_conntrack_untracked) { ++ if (skb->protocol == __constant_htons(ETH_P_IP)) { ++ info.ctorigsrc = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip; ++ info.ctorigdst = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.u3.ip; ++ info.ctreplsrc = ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip; ++ info.ctrepldst = ct->tuplehash[IP_CT_DIR_REPLY].tuple.dst.u3.ip; ++ } ++ else if (skb->protocol == __constant_htons(ETH_P_IPV6)) { ++ /* Again, hash ipv6 addresses into a single u32. */ ++ info.ctorigsrc = jhash2(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip6, 4, q->perturbation); ++ info.ctorigdst = jhash2(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.u3.ip6, 4, q->perturbation); ++ info.ctreplsrc = jhash2(ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip6, 4, q->perturbation); ++ info.ctrepldst = jhash2(ct->tuplehash[IP_CT_DIR_REPLY].tuple.dst.u3.ip6, 4, q->perturbation); ++ } ++ ++ } ++#endif ++ ++ switch(q->hash_kind) { ++ case TCA_SFQ_HASH_CLASSIC: ++ return esfq_jhash_3words(q, info.dst, info.src, info.proto); ++ case TCA_SFQ_HASH_DST: ++ return esfq_jhash_1word(q, info.dst); ++ case TCA_SFQ_HASH_SRC: ++ return esfq_jhash_1word(q, info.src); ++ case TCA_SFQ_HASH_FWMARK: ++ return esfq_jhash_1word(q, info.mark); ++#ifdef CONFIG_NET_SCH_ESFQ_NFCT ++ case TCA_SFQ_HASH_CTORIGDST: ++ return esfq_jhash_1word(q, info.ctorigdst); ++ case TCA_SFQ_HASH_CTORIGSRC: ++ return esfq_jhash_1word(q, info.ctorigsrc); ++ case TCA_SFQ_HASH_CTREPLDST: ++ return esfq_jhash_1word(q, info.ctrepldst); ++ case TCA_SFQ_HASH_CTREPLSRC: ++ return esfq_jhash_1word(q, info.ctreplsrc); ++ case TCA_SFQ_HASH_CTNATCHG: ++ { ++ if (info.ctorigdst == info.ctreplsrc) ++ return esfq_jhash_1word(q, info.ctorigsrc); ++ return esfq_jhash_1word(q, info.ctreplsrc); ++ } ++#endif ++ default: ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Unknown hash method. Falling back to classic.\n"); ++ } ++ return esfq_jhash_3words(q, info.dst, info.src, info.proto); ++} ++ ++static inline void esfq_link(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ int d = q->qs[x].qlen + q->depth; ++ ++ p = d; ++ n = q->dep[d].next; ++ q->dep[x].next = n; ++ q->dep[x].prev = p; ++ q->dep[p].next = q->dep[n].prev = x; ++} ++ ++static inline void esfq_dec(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ ++ n = q->dep[x].next; ++ p = q->dep[x].prev; ++ q->dep[p].next = n; ++ q->dep[n].prev = p; ++ ++ if (n == p && q->max_depth == q->qs[x].qlen + 1) ++ q->max_depth--; ++ ++ esfq_link(q, x); ++} ++ ++static inline void esfq_inc(struct esfq_sched_data *q, esfq_index x) ++{ ++ esfq_index p, n; ++ int d; ++ ++ n = q->dep[x].next; ++ p = q->dep[x].prev; ++ q->dep[p].next = n; ++ q->dep[n].prev = p; ++ d = q->qs[x].qlen; ++ if (q->max_depth < d) ++ q->max_depth = d; ++ ++ esfq_link(q, x); ++} ++ ++static unsigned int esfq_drop(struct Qdisc *sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_index d = q->max_depth; ++ struct sk_buff *skb; ++ unsigned int len; ++ ++ /* Queue is full! Find the longest slot and ++ drop a packet from it */ ++ ++ if (d > 1) { ++ esfq_index x = q->dep[d+q->depth].next; ++ skb = q->qs[x].prev; ++ len = skb->len; ++ __skb_unlink(skb, &q->qs[x]); ++ kfree_skb(skb); ++ esfq_dec(q, x); ++ sch->q.qlen--; ++ sch->qstats.drops++; ++ sch->qstats.backlog -= len; ++ return len; ++ } ++ ++ if (d == 1) { ++ /* It is difficult to believe, but ALL THE SLOTS HAVE LENGTH 1. */ ++ d = q->next[q->tail]; ++ q->next[q->tail] = q->next[d]; ++ q->allot[q->next[d]] += q->quantum; ++ skb = q->qs[d].prev; ++ len = skb->len; ++ __skb_unlink(skb, &q->qs[d]); ++ kfree_skb(skb); ++ esfq_dec(q, d); ++ sch->q.qlen--; ++ q->ht[q->hash[d]] = q->depth; ++ sch->qstats.drops++; ++ sch->qstats.backlog -= len; ++ return len; ++ } ++ ++ return 0; ++} ++ ++static void esfq_q_enqueue(struct sk_buff *skb, struct esfq_sched_data *q, unsigned int end) ++{ ++ unsigned hash = esfq_hash(q, skb); ++ unsigned depth = q->depth; ++ esfq_index x; ++ ++ x = q->ht[hash]; ++ if (x == depth) { ++ q->ht[hash] = x = q->dep[depth].next; ++ q->hash[x] = hash; ++ } ++ ++ if (end == ESFQ_TAIL) ++ __skb_queue_tail(&q->qs[x], skb); ++ else ++ __skb_queue_head(&q->qs[x], skb); ++ ++ esfq_inc(q, x); ++ if (q->qs[x].qlen == 1) { /* The flow is new */ ++ if (q->tail == depth) { /* It is the first flow */ ++ q->tail = x; ++ q->next[x] = x; ++ q->allot[x] = q->quantum; ++ } else { ++ q->next[x] = q->next[q->tail]; ++ q->next[q->tail] = x; ++ q->tail = x; ++ } ++ } ++} ++ ++static int esfq_enqueue(struct sk_buff *skb, struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_q_enqueue(skb, q, ESFQ_TAIL); ++ sch->qstats.backlog += skb->len; ++ if (++sch->q.qlen < q->limit-1) { ++ sch->bstats.bytes += skb->len; ++ sch->bstats.packets++; ++ return 0; ++ } ++ ++ sch->qstats.drops++; ++ esfq_drop(sch); ++ return NET_XMIT_CN; ++} ++ ++static struct sk_buff *esfq_peek(struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_index a; ++ ++ /* No active slots */ ++ if (q->tail == q->depth) ++ return NULL; ++ ++ a = q->next[q->tail]; ++ return skb_peek(&q->qs[a]); ++} ++ ++static struct sk_buff *esfq_q_dequeue(struct esfq_sched_data *q) ++{ ++ struct sk_buff *skb; ++ unsigned depth = q->depth; ++ esfq_index a, old_a; ++ ++ /* No active slots */ ++ if (q->tail == depth) ++ return NULL; ++ ++ a = old_a = q->next[q->tail]; ++ ++ /* Grab packet */ ++ skb = __skb_dequeue(&q->qs[a]); ++ esfq_dec(q, a); ++ ++ /* Is the slot empty? */ ++ if (q->qs[a].qlen == 0) { ++ q->ht[q->hash[a]] = depth; ++ a = q->next[a]; ++ if (a == old_a) { ++ q->tail = depth; ++ return skb; ++ } ++ q->next[q->tail] = a; ++ q->allot[a] += q->quantum; ++ } else if ((q->allot[a] -= skb->len) <= 0) { ++ q->tail = a; ++ a = q->next[a]; ++ q->allot[a] += q->quantum; ++ } ++ ++ return skb; ++} ++ ++static struct sk_buff *esfq_dequeue(struct Qdisc* sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ struct sk_buff *skb; ++ ++ skb = esfq_q_dequeue(q); ++ if (skb == NULL) ++ return NULL; ++ sch->q.qlen--; ++ sch->qstats.backlog -= skb->len; ++ return skb; ++} ++ ++static void esfq_q_destroy(struct esfq_sched_data *q) ++{ ++ del_timer(&q->perturb_timer); ++ if(q->ht) ++ kfree(q->ht); ++ if(q->dep) ++ kfree(q->dep); ++ if(q->next) ++ kfree(q->next); ++ if(q->allot) ++ kfree(q->allot); ++ if(q->hash) ++ kfree(q->hash); ++ if(q->qs) ++ kfree(q->qs); ++} ++ ++static void esfq_destroy(struct Qdisc *sch) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ esfq_q_destroy(q); ++} ++ ++ ++static void esfq_reset(struct Qdisc* sch) ++{ ++ struct sk_buff *skb; ++ ++ while ((skb = esfq_dequeue(sch)) != NULL) ++ kfree_skb(skb); ++} ++ ++static void esfq_perturbation(unsigned long arg) ++{ ++ struct Qdisc *sch = (struct Qdisc*)arg; ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ ++ q->perturbation = prandom_u32()&0x1F; ++ ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } ++} ++ ++static unsigned int esfq_check_hash(unsigned int kind) ++{ ++ switch (kind) { ++ case TCA_SFQ_HASH_CTORIGDST: ++ case TCA_SFQ_HASH_CTORIGSRC: ++ case TCA_SFQ_HASH_CTREPLDST: ++ case TCA_SFQ_HASH_CTREPLSRC: ++ case TCA_SFQ_HASH_CTNATCHG: ++#ifndef CONFIG_NET_SCH_ESFQ_NFCT ++ { ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Conntrack hash types disabled in kernel config. Falling back to classic.\n"); ++ return TCA_SFQ_HASH_CLASSIC; ++ } ++#endif ++ case TCA_SFQ_HASH_CLASSIC: ++ case TCA_SFQ_HASH_DST: ++ case TCA_SFQ_HASH_SRC: ++ case TCA_SFQ_HASH_FWMARK: ++ return kind; ++ default: ++ { ++ if (net_ratelimit()) ++ printk(KERN_WARNING "ESFQ: Unknown hash type. Falling back to classic.\n"); ++ return TCA_SFQ_HASH_CLASSIC; ++ } ++ } ++} ++ ++static int esfq_q_init(struct esfq_sched_data *q, struct nlattr *opt) ++{ ++ struct tc_esfq_qopt *ctl = nla_data(opt); ++ esfq_index p = ~0U/2; ++ int i; ++ ++ if (opt && opt->nla_len < nla_attr_size(sizeof(*ctl))) ++ return -EINVAL; ++ ++ q->perturbation = 0; ++ q->hash_kind = TCA_SFQ_HASH_CLASSIC; ++ q->max_depth = 0; ++ if (opt == NULL) { ++ q->perturb_period = 0; ++ q->hash_divisor = 1024; ++ q->tail = q->limit = q->depth = 128; ++ ++ } else { ++ struct tc_esfq_qopt *ctl = nla_data(opt); ++ if (ctl->quantum) ++ q->quantum = ctl->quantum; ++ q->perturb_period = ctl->perturb_period*HZ; ++ q->hash_divisor = ctl->divisor ? : 1024; ++ q->tail = q->limit = q->depth = ctl->flows ? : 128; ++ ++ if ( q->depth > p - 1 ) ++ return -EINVAL; ++ ++ if (ctl->limit) ++ q->limit = min_t(u32, ctl->limit, q->depth); ++ ++ if (ctl->hash_kind) { ++ q->hash_kind = esfq_check_hash(ctl->hash_kind); ++ } ++ } ++ ++ q->ht = kmalloc(q->hash_divisor*sizeof(esfq_index), GFP_KERNEL); ++ if (!q->ht) ++ goto err_case; ++ q->dep = kmalloc((1+q->depth*2)*sizeof(struct esfq_head), GFP_KERNEL); ++ if (!q->dep) ++ goto err_case; ++ q->next = kmalloc(q->depth*sizeof(esfq_index), GFP_KERNEL); ++ if (!q->next) ++ goto err_case; ++ q->allot = kmalloc(q->depth*sizeof(short), GFP_KERNEL); ++ if (!q->allot) ++ goto err_case; ++ q->hash = kmalloc(q->depth*sizeof(unsigned short), GFP_KERNEL); ++ if (!q->hash) ++ goto err_case; ++ q->qs = kmalloc(q->depth*sizeof(struct sk_buff_head), GFP_KERNEL); ++ if (!q->qs) ++ goto err_case; ++ ++ for (i=0; i< q->hash_divisor; i++) ++ q->ht[i] = q->depth; ++ for (i=0; idepth; i++) { ++ skb_queue_head_init(&q->qs[i]); ++ q->dep[i+q->depth].next = i+q->depth; ++ q->dep[i+q->depth].prev = i+q->depth; ++ } ++ ++ for (i=0; idepth; i++) ++ esfq_link(q, i); ++ return 0; ++err_case: ++ esfq_q_destroy(q); ++ return -ENOBUFS; ++} ++ ++static int esfq_init(struct Qdisc *sch, struct nlattr *opt) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ int err; ++ ++ q->quantum = psched_mtu(qdisc_dev(sch)); /* default */ ++ if ((err = esfq_q_init(q, opt))) ++ return err; ++ ++ init_timer(&q->perturb_timer); ++ q->perturb_timer.data = (unsigned long)sch; ++ q->perturb_timer.function = esfq_perturbation; ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } ++ ++ return 0; ++} ++ ++static int esfq_change(struct Qdisc *sch, struct nlattr *opt) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ struct esfq_sched_data new; ++ struct sk_buff *skb; ++ int err; ++ ++ /* set up new queue */ ++ memset(&new, 0, sizeof(struct esfq_sched_data)); ++ new.quantum = psched_mtu(qdisc_dev(sch)); /* default */ ++ if ((err = esfq_q_init(&new, opt))) ++ return err; ++ ++ /* copy all packets from the old queue to the new queue */ ++ sch_tree_lock(sch); ++ while ((skb = esfq_q_dequeue(q)) != NULL) ++ esfq_q_enqueue(skb, &new, ESFQ_TAIL); ++ ++ /* clean up the old queue */ ++ esfq_q_destroy(q); ++ ++ /* copy elements of the new queue into the old queue */ ++ q->perturb_period = new.perturb_period; ++ q->quantum = new.quantum; ++ q->limit = new.limit; ++ q->depth = new.depth; ++ q->hash_divisor = new.hash_divisor; ++ q->hash_kind = new.hash_kind; ++ q->tail = new.tail; ++ q->max_depth = new.max_depth; ++ q->ht = new.ht; ++ q->dep = new.dep; ++ q->next = new.next; ++ q->allot = new.allot; ++ q->hash = new.hash; ++ q->qs = new.qs; ++ ++ /* finish up */ ++ if (q->perturb_period) { ++ q->perturb_timer.expires = jiffies + q->perturb_period; ++ add_timer(&q->perturb_timer); ++ } else { ++ q->perturbation = 0; ++ } ++ sch_tree_unlock(sch); ++ return 0; ++} ++ ++static int esfq_dump(struct Qdisc *sch, struct sk_buff *skb) ++{ ++ struct esfq_sched_data *q = qdisc_priv(sch); ++ unsigned char *b = skb_tail_pointer(skb); ++ struct tc_esfq_qopt opt; ++ ++ opt.quantum = q->quantum; ++ opt.perturb_period = q->perturb_period/HZ; ++ ++ opt.limit = q->limit; ++ opt.divisor = q->hash_divisor; ++ opt.flows = q->depth; ++ opt.hash_kind = q->hash_kind; ++ ++ if (nla_put(skb, TCA_OPTIONS, sizeof(opt), &opt)) ++ goto nla_put_failure; ++ ++ return skb->len; ++ ++nla_put_failure: ++ nlmsg_trim(skb, b); ++ return -1; ++} ++ ++static struct Qdisc_ops esfq_qdisc_ops = ++{ ++ .next = NULL, ++ .cl_ops = NULL, ++ .id = "esfq", ++ .priv_size = sizeof(struct esfq_sched_data), ++ .enqueue = esfq_enqueue, ++ .dequeue = esfq_dequeue, ++ .peek = esfq_peek, ++ .drop = esfq_drop, ++ .init = esfq_init, ++ .reset = esfq_reset, ++ .destroy = esfq_destroy, ++ .change = esfq_change, ++ .dump = esfq_dump, ++ .owner = THIS_MODULE, ++}; ++ ++static int __init esfq_module_init(void) ++{ ++ return register_qdisc(&esfq_qdisc_ops); ++} ++static void __exit esfq_module_exit(void) ++{ ++ unregister_qdisc(&esfq_qdisc_ops); ++} ++module_init(esfq_module_init) ++module_exit(esfq_module_exit) ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.3/630-packet_socket_type.patch b/target/linux/generic/patches-4.3/630-packet_socket_type.patch new file mode 100644 index 0000000..add00c7 --- /dev/null +++ b/target/linux/generic/patches-4.3/630-packet_socket_type.patch @@ -0,0 +1,134 @@ +This patch allows the user to specify desired packet types (outgoing, +broadcast, unicast, etc.) on packet sockets via setsockopt. +This can reduce the load in situations where only a limited number +of packet types are necessary + +Signed-off-by: Felix Fietkau + +--- a/include/uapi/linux/if_packet.h ++++ b/include/uapi/linux/if_packet.h +@@ -31,6 +31,8 @@ struct sockaddr_ll { + #define PACKET_KERNEL 7 /* To kernel space */ + /* Unused, PACKET_FASTROUTE and PACKET_LOOPBACK are invisible to user space */ + #define PACKET_FASTROUTE 6 /* Fastrouted frame */ ++#define PACKET_MASK_ANY 0xffffffff /* mask for packet type bits */ ++ + + /* Packet socket options */ + +@@ -56,6 +58,7 @@ struct sockaddr_ll { + #define PACKET_QDISC_BYPASS 20 + #define PACKET_ROLLOVER_STATS 21 + #define PACKET_FANOUT_DATA 22 ++#define PACKET_RECV_TYPE 23 + + #define PACKET_FANOUT_HASH 0 + #define PACKET_FANOUT_LB 1 +--- a/net/packet/af_packet.c ++++ b/net/packet/af_packet.c +@@ -1750,6 +1750,7 @@ static int packet_rcv_spkt(struct sk_buf + { + struct sock *sk; + struct sockaddr_pkt *spkt; ++ struct packet_sock *po; + + /* + * When we registered the protocol we saved the socket in the data +@@ -1757,6 +1758,7 @@ static int packet_rcv_spkt(struct sk_buf + */ + + sk = pt->af_packet_priv; ++ po = pkt_sk(sk); + + /* + * Yank back the headers [hope the device set this +@@ -1769,7 +1771,7 @@ static int packet_rcv_spkt(struct sk_buf + * so that this procedure is noop. + */ + +- if (skb->pkt_type == PACKET_LOOPBACK) ++ if (!(po->pkt_type & (1 << skb->pkt_type))) + goto out; + + if (!net_eq(dev_net(dev), sock_net(sk))) +@@ -1976,12 +1978,12 @@ static int packet_rcv(struct sk_buff *sk + int skb_len = skb->len; + unsigned int snaplen, res; + +- if (skb->pkt_type == PACKET_LOOPBACK) +- goto drop; +- + sk = pt->af_packet_priv; + po = pkt_sk(sk); + ++ if (!(po->pkt_type & (1 << skb->pkt_type))) ++ goto drop; ++ + if (!net_eq(dev_net(dev), sock_net(sk))) + goto drop; + +@@ -2101,12 +2103,12 @@ static int tpacket_rcv(struct sk_buff *s + BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32); + BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48); + +- if (skb->pkt_type == PACKET_LOOPBACK) +- goto drop; +- + sk = pt->af_packet_priv; + po = pkt_sk(sk); + ++ if (!(po->pkt_type & (1 << skb->pkt_type))) ++ goto drop; ++ + if (!net_eq(dev_net(dev), sock_net(sk))) + goto drop; + +@@ -3069,6 +3071,7 @@ static int packet_create(struct net *net + mutex_init(&po->pg_vec_lock); + po->rollover = NULL; + po->prot_hook.func = packet_rcv; ++ po->pkt_type = PACKET_MASK_ANY & ~(1 << PACKET_LOOPBACK); + + if (sock->type == SOCK_PACKET) + po->prot_hook.func = packet_rcv_spkt; +@@ -3684,6 +3687,16 @@ packet_setsockopt(struct socket *sock, i + po->xmit = val ? packet_direct_xmit : dev_queue_xmit; + return 0; + } ++ case PACKET_RECV_TYPE: ++ { ++ unsigned int val; ++ if (optlen != sizeof(val)) ++ return -EINVAL; ++ if (copy_from_user(&val, optval, sizeof(val))) ++ return -EFAULT; ++ po->pkt_type = val & ~BIT(PACKET_LOOPBACK); ++ return 0; ++ } + default: + return -ENOPROTOOPT; + } +@@ -3736,6 +3749,13 @@ static int packet_getsockopt(struct sock + case PACKET_VNET_HDR: + val = po->has_vnet_hdr; + break; ++ case PACKET_RECV_TYPE: ++ if (len > sizeof(unsigned int)) ++ len = sizeof(unsigned int); ++ val = po->pkt_type; ++ ++ data = &val; ++ break; + case PACKET_VERSION: + val = po->tp_version; + break; +--- a/net/packet/internal.h ++++ b/net/packet/internal.h +@@ -129,6 +129,7 @@ struct packet_sock { + struct net_device __rcu *cached_dev; + int (*xmit)(struct sk_buff *skb); + struct packet_type prot_hook ____cacheline_aligned_in_smp; ++ unsigned int pkt_type; + }; + + static struct packet_sock *pkt_sk(struct sock *sk) diff --git a/target/linux/generic/patches-4.3/640-bridge_no_eap_forward.patch b/target/linux/generic/patches-4.3/640-bridge_no_eap_forward.patch new file mode 100644 index 0000000..de52c02 --- /dev/null +++ b/target/linux/generic/patches-4.3/640-bridge_no_eap_forward.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: no EAP forward + +When bridging, do not forward EAP frames to other ports, only deliver +them locally. +Fixes WPA authentication issues with multiples APs that are connected to +each other via bridges. +--- +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -162,7 +162,11 @@ int br_handle_frame_finish(struct sock * + if (IS_ENABLED(CONFIG_INET) && skb->protocol == htons(ETH_P_ARP)) + br_do_proxy_arp(skb, br, vid, p); + +- if (is_broadcast_ether_addr(dest)) { ++ if (skb->protocol == htons(ETH_P_PAE)) { ++ skb2 = skb; ++ /* Do not forward 802.1x/EAP frames */ ++ skb = NULL; ++ } else if (is_broadcast_ether_addr(dest)) { + skb2 = skb; + unicast = false; + } else if (is_multicast_ether_addr(dest)) { diff --git a/target/linux/generic/patches-4.3/641-bridge_always_accept_eap.patch b/target/linux/generic/patches-4.3/641-bridge_always_accept_eap.patch new file mode 100644 index 0000000..61f96e5 --- /dev/null +++ b/target/linux/generic/patches-4.3/641-bridge_always_accept_eap.patch @@ -0,0 +1,17 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: always accept EAP + +Allow EAP frames to pass through bridges even in learning state. Fixes +issues with WDS. +--- +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -146,7 +146,7 @@ int br_handle_frame_finish(struct sock * + br_multicast_rcv(br, p, skb, vid)) + goto drop; + +- if (p->state == BR_STATE_LEARNING) ++ if ((p->state == BR_STATE_LEARNING) && skb->protocol != htons(ETH_P_PAE)) + goto drop; + + BR_INPUT_SKB_CB(skb)->brdev = br->dev; diff --git a/target/linux/generic/patches-4.3/642-bridge_port_isolate.patch b/target/linux/generic/patches-4.3/642-bridge_port_isolate.patch new file mode 100644 index 0000000..9f9c03a --- /dev/null +++ b/target/linux/generic/patches-4.3/642-bridge_port_isolate.patch @@ -0,0 +1,107 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: port isolate + +Isolating individual bridge ports +--- +--- a/include/linux/if_bridge.h ++++ b/include/linux/if_bridge.h +@@ -45,6 +45,7 @@ struct br_ip_list { + #define BR_PROXYARP BIT(8) + #define BR_LEARNING_SYNC BIT(9) + #define BR_PROXYARP_WIFI BIT(10) ++#define BR_ISOLATE_MODE BIT(11) + + extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *)); + +--- a/net/bridge/br_sysfs_if.c ++++ b/net/bridge/br_sysfs_if.c +@@ -173,6 +173,22 @@ BRPORT_ATTR_FLAG(unicast_flood, BR_FLOOD + BRPORT_ATTR_FLAG(proxyarp, BR_PROXYARP); + BRPORT_ATTR_FLAG(proxyarp_wifi, BR_PROXYARP_WIFI); + ++static ssize_t show_isolate_mode(struct net_bridge_port *p, char *buf) ++{ ++ int isolate_mode = (p->flags & BR_ISOLATE_MODE) ? 1 : 0; ++ return sprintf(buf, "%d\n", isolate_mode); ++} ++static ssize_t store_isolate_mode(struct net_bridge_port *p, unsigned long v) ++{ ++ if (v) ++ p->flags |= BR_ISOLATE_MODE; ++ else ++ p->flags &= ~BR_ISOLATE_MODE; ++ return 0; ++} ++static BRPORT_ATTR(isolate_mode, S_IRUGO | S_IWUSR, ++ show_isolate_mode, store_isolate_mode); ++ + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf) + { +@@ -217,6 +233,7 @@ static const struct brport_attribute *br + #endif + &brport_attr_proxyarp, + &brport_attr_proxyarp_wifi, ++ &brport_attr_isolate_mode, + NULL + }; + +--- a/net/bridge/br_input.c ++++ b/net/bridge/br_input.c +@@ -185,8 +185,8 @@ int br_handle_frame_finish(struct sock * + + unicast = false; + br->dev->stats.multicast++; +- } else if ((dst = __br_fdb_get(br, dest, vid)) && +- dst->is_local) { ++ } else if ((p->flags & BR_ISOLATE_MODE) || ++ ((dst = __br_fdb_get(br, dest, vid)) && dst->is_local)) { + skb2 = skb; + /* Do not forward the packet since it's local. */ + skb = NULL; +--- a/net/bridge/br_forward.c ++++ b/net/bridge/br_forward.c +@@ -134,7 +134,7 @@ EXPORT_SYMBOL_GPL(br_deliver); + /* called with rcu_read_lock */ + void br_forward(const struct net_bridge_port *to, struct sk_buff *skb, struct sk_buff *skb0) + { +- if (should_deliver(to, skb)) { ++ if (should_deliver(to, skb) && !(to->flags & BR_ISOLATE_MODE)) { + if (skb0) + deliver_clone(to, skb, __br_forward); + else +@@ -190,7 +190,7 @@ static void br_flood(struct net_bridge * + struct sk_buff *skb0, + void (*__packet_hook)(const struct net_bridge_port *p, + struct sk_buff *skb), +- bool unicast) ++ bool unicast, bool forward) + { + struct net_bridge_port *p; + struct net_bridge_port *prev; +@@ -198,6 +198,8 @@ static void br_flood(struct net_bridge * + prev = NULL; + + list_for_each_entry_rcu(p, &br->port_list, list) { ++ if (forward && (p->flags & BR_ISOLATE_MODE)) ++ continue; + /* Do not flood unicast traffic to ports that turn it off */ + if (unicast && !(p->flags & BR_FLOOD)) + continue; +@@ -232,14 +234,14 @@ out: + /* called with rcu_read_lock */ + void br_flood_deliver(struct net_bridge *br, struct sk_buff *skb, bool unicast) + { +- br_flood(br, skb, NULL, __br_deliver, unicast); ++ br_flood(br, skb, NULL, __br_deliver, unicast, false); + } + + /* called under bridge lock */ + void br_flood_forward(struct net_bridge *br, struct sk_buff *skb, + struct sk_buff *skb2, bool unicast) + { +- br_flood(br, skb, skb2, __br_forward, unicast); ++ br_flood(br, skb, skb2, __br_forward, unicast, true); + } + + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING diff --git a/target/linux/generic/patches-4.3/643-bridge_remove_ipv6_dependency.patch b/target/linux/generic/patches-4.3/643-bridge_remove_ipv6_dependency.patch new file mode 100644 index 0000000..ee5c244 --- /dev/null +++ b/target/linux/generic/patches-4.3/643-bridge_remove_ipv6_dependency.patch @@ -0,0 +1,123 @@ +From: Jonas Gorski +Subject: [PATCH] bridge: remove IPv6 depependency of bridge in 2.6.38+ + +Since 2.6.38 the bridge module has a dependency to IPv6 if IPv6 is +enabled. Since the IPv6 module isn't exactly lightweight and bridge also +only needs a single function from IPv6, it's rather easy to create a +common "lib" module with a RCU pointer to the actual implementation, if +the IPv6 module is loaded (although slightly hackish). + +The codepath seems to be only taken when using IPv6, so there should be +no negative side effects when IPv6 isn't loaded. I did not measure how +big the performance impact is. +--- +--- a/include/net/addrconf.h ++++ b/include/net/addrconf.h +@@ -122,6 +122,12 @@ static inline int addrconf_ifid_eui48(u8 + return 0; + } + ++extern int (*ipv6_dev_get_saddr_hook)(struct net *net, ++ const struct net_device *dev, ++ const struct in6_addr *daddr, ++ unsigned int prefs, ++ struct in6_addr *saddr); ++ + static inline unsigned long addrconf_timeout_fixup(u32 timeout, + unsigned int unit) + { +--- a/net/bridge/Kconfig ++++ b/net/bridge/Kconfig +@@ -6,7 +6,6 @@ config BRIDGE + tristate "802.1d Ethernet Bridging" + select LLC + select STP +- depends on IPV6 || IPV6=n + ---help--- + If you say Y here, then your Linux box will be able to act as an + Ethernet bridge, which means that the different Ethernet segments it +--- a/net/ipv6/Makefile ++++ b/net/ipv6/Makefile +@@ -46,6 +46,7 @@ obj-y += addrconf_core.o exthdrs_core.o + obj-$(CONFIG_INET) += output_core.o protocol.o $(ipv6-offload) + + obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_hashtables.o ++obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_stubs.o + + ifneq ($(CONFIG_IPV6),) + obj-$(CONFIG_NET_UDP_TUNNEL) += ip6_udp_tunnel.o +--- a/net/ipv6/addrconf.c ++++ b/net/ipv6/addrconf.c +@@ -1509,7 +1509,7 @@ out: + return hiscore_idx; + } + +-int ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, ++static int ___ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, + const struct in6_addr *daddr, unsigned int prefs, + struct in6_addr *saddr) + { +@@ -1579,7 +1579,6 @@ int ipv6_dev_get_saddr(struct net *net, + in6_ifa_put(hiscore->ifa); + return 0; + } +-EXPORT_SYMBOL(ipv6_dev_get_saddr); + + int __ipv6_get_lladdr(struct inet6_dev *idev, struct in6_addr *addr, + u32 banned_flags) +@@ -5941,6 +5940,9 @@ int __init addrconf_init(void) + + ipv6_addr_label_rtnl_register(); + ++ BUG_ON(ipv6_dev_get_saddr_hook != NULL); ++ rcu_assign_pointer(ipv6_dev_get_saddr_hook, ___ipv6_dev_get_saddr); ++ + return 0; + errout: + rtnl_af_unregister(&inet6_ops); +@@ -5960,6 +5962,9 @@ void addrconf_cleanup(void) + struct net_device *dev; + int i; + ++ rcu_assign_pointer(ipv6_dev_get_saddr_hook, NULL); ++ synchronize_rcu(); ++ + unregister_netdevice_notifier(&ipv6_dev_notf); + unregister_pernet_subsys(&addrconf_ops); + ipv6_addr_label_cleanup(); +--- /dev/null ++++ b/net/ipv6/inet6_stubs.c +@@ -0,0 +1,33 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#include ++#include ++ ++int (*ipv6_dev_get_saddr_hook)(struct net *net, const struct net_device *dev, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr); ++ ++EXPORT_SYMBOL(ipv6_dev_get_saddr_hook); ++ ++int ipv6_dev_get_saddr(struct net *net, const struct net_device *dst_dev, ++ const struct in6_addr *daddr, unsigned int prefs, ++ struct in6_addr *saddr) ++{ ++ int ret = -EADDRNOTAVAIL; ++ typeof(ipv6_dev_get_saddr_hook) dev_get_saddr; ++ ++ rcu_read_lock(); ++ dev_get_saddr = rcu_dereference(ipv6_dev_get_saddr_hook); ++ ++ if (dev_get_saddr) ++ ret = dev_get_saddr(net, dst_dev, daddr, prefs, saddr); ++ ++ rcu_read_unlock(); ++ return ret; ++} ++EXPORT_SYMBOL(ipv6_dev_get_saddr); ++ diff --git a/target/linux/generic/patches-4.3/645-bridge_multicast_to_unicast.patch b/target/linux/generic/patches-4.3/645-bridge_multicast_to_unicast.patch new file mode 100644 index 0000000..d3ce4ef --- /dev/null +++ b/target/linux/generic/patches-4.3/645-bridge_multicast_to_unicast.patch @@ -0,0 +1,417 @@ +From: Felix Fietkau +Subject: [PATCH] bridge: multicast to unicast + +Implement optinal multicast->unicast conversion for igmp snooping +--- +--- a/include/linux/if_bridge.h ++++ b/include/linux/if_bridge.h +@@ -46,6 +46,7 @@ struct br_ip_list { + #define BR_LEARNING_SYNC BIT(9) + #define BR_PROXYARP_WIFI BIT(10) + #define BR_ISOLATE_MODE BIT(11) ++#define BR_MULTICAST_TO_UCAST BIT(12) + + extern void brioctl_set(int (*ioctl_hook)(struct net *, unsigned int, void __user *)); + +--- a/net/bridge/br_multicast.c ++++ b/net/bridge/br_multicast.c +@@ -42,12 +42,13 @@ static void br_multicast_add_router(stru + static void br_ip4_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, + __be32 group, +- __u16 vid); ++ __u16 vid, ++ const unsigned char *src); + #if IS_ENABLED(CONFIG_IPV6) + static void br_ip6_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid); ++ __u16 vid, const unsigned char *src); + #endif + unsigned int br_mdb_rehash_seq; + +@@ -649,7 +650,8 @@ struct net_bridge_port_group *br_multica + struct net_bridge_port *port, + struct br_ip *group, + struct net_bridge_port_group __rcu *next, +- unsigned char state) ++ unsigned char state, ++ const unsigned char *src) + { + struct net_bridge_port_group *p; + +@@ -664,12 +666,33 @@ struct net_bridge_port_group *br_multica + hlist_add_head(&p->mglist, &port->mglist); + setup_timer(&p->timer, br_multicast_port_group_expired, + (unsigned long)p); ++ if ((port->flags & BR_MULTICAST_TO_UCAST) && src) { ++ memcpy(p->eth_addr, src, ETH_ALEN); ++ p->unicast = true; ++ } + return p; + } + ++static bool br_port_group_equal(struct net_bridge_port_group *p, ++ struct net_bridge_port *port, ++ const unsigned char *src) ++{ ++ if (p->port != port) ++ return false; ++ ++ if (!p->unicast) ++ return true; ++ ++ if (!src) ++ return false; ++ ++ return ether_addr_equal(src, p->eth_addr); ++} ++ + static int br_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, +- struct br_ip *group) ++ struct br_ip *group, ++ const unsigned char *src) + { + struct net_bridge_mdb_entry *mp; + struct net_bridge_port_group *p; +@@ -696,13 +719,13 @@ static int br_multicast_add_group(struct + for (pp = &mp->ports; + (p = mlock_dereference(*pp, br)) != NULL; + pp = &p->next) { +- if (p->port == port) ++ if (br_port_group_equal(p, port, src)) + goto found; + if ((unsigned long)p->port < (unsigned long)port) + break; + } + +- p = br_multicast_new_port_group(port, group, *pp, MDB_TEMPORARY); ++ p = br_multicast_new_port_group(port, group, *pp, MDB_TEMPORARY, src); + if (unlikely(!p)) + goto err; + rcu_assign_pointer(*pp, p); +@@ -721,7 +744,7 @@ err: + static int br_ip4_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, + __be32 group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + +@@ -732,14 +755,14 @@ static int br_ip4_multicast_add_group(st + br_group.proto = htons(ETH_P_IP); + br_group.vid = vid; + +- return br_multicast_add_group(br, port, &br_group); ++ return br_multicast_add_group(br, port, &br_group, src); + } + + #if IS_ENABLED(CONFIG_IPV6) + static int br_ip6_multicast_add_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + +@@ -750,7 +773,7 @@ static int br_ip6_multicast_add_group(st + br_group.proto = htons(ETH_P_IPV6); + br_group.vid = vid; + +- return br_multicast_add_group(br, port, &br_group); ++ return br_multicast_add_group(br, port, &br_group, src); + } + #endif + +@@ -995,6 +1018,7 @@ static int br_ip4_multicast_igmp3_report + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct igmpv3_report *ih; + struct igmpv3_grec *grec; + int i; +@@ -1038,9 +1062,10 @@ static int br_ip4_multicast_igmp3_report + if ((type == IGMPV3_CHANGE_TO_INCLUDE || + type == IGMPV3_MODE_IS_INCLUDE) && + ntohs(grec->grec_nsrcs) == 0) { +- br_ip4_multicast_leave_group(br, port, group, vid); ++ br_ip4_multicast_leave_group(br, port, group, vid, src); + } else { +- err = br_ip4_multicast_add_group(br, port, group, vid); ++ src = eth_hdr(skb)->h_source; ++ err = br_ip4_multicast_add_group(br, port, group, vid, src); + if (err) + break; + } +@@ -1055,6 +1080,7 @@ static int br_ip6_multicast_mld2_report( + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src = eth_hdr(skb)->h_source; + struct icmp6hdr *icmp6h; + struct mld2_grec *grec; + int i; +@@ -1106,10 +1132,10 @@ static int br_ip6_multicast_mld2_report( + grec->grec_type == MLD2_MODE_IS_INCLUDE) && + ntohs(*nsrcs) == 0) { + br_ip6_multicast_leave_group(br, port, &grec->grec_mca, +- vid); ++ vid, src); + } else { + err = br_ip6_multicast_add_group(br, port, +- &grec->grec_mca, vid); ++ &grec->grec_mca, vid, src); + if (!err) + break; + } +@@ -1422,7 +1448,8 @@ br_multicast_leave_group(struct net_brid + struct net_bridge_port *port, + struct br_ip *group, + struct bridge_mcast_other_query *other_query, +- struct bridge_mcast_own_query *own_query) ++ struct bridge_mcast_own_query *own_query, ++ const unsigned char *src) + { + struct net_bridge_mdb_htable *mdb; + struct net_bridge_mdb_entry *mp; +@@ -1446,7 +1473,7 @@ br_multicast_leave_group(struct net_brid + for (pp = &mp->ports; + (p = mlock_dereference(*pp, br)) != NULL; + pp = &p->next) { +- if (p->port != port) ++ if (!br_port_group_equal(p, port, src)) + continue; + + rcu_assign_pointer(*pp, p->next); +@@ -1509,7 +1536,7 @@ br_multicast_leave_group(struct net_brid + for (p = mlock_dereference(mp->ports, br); + p != NULL; + p = mlock_dereference(p->next, br)) { +- if (p->port != port) ++ if (!br_port_group_equal(p, port, src)) + continue; + + if (!hlist_unhashed(&p->mglist) && +@@ -1527,8 +1554,8 @@ out: + + static void br_ip4_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, +- __be32 group, +- __u16 vid) ++ __be32 group, __u16 vid, ++ const unsigned char *src) + { + struct br_ip br_group; + struct bridge_mcast_own_query *own_query; +@@ -1543,14 +1570,14 @@ static void br_ip4_multicast_leave_group + br_group.vid = vid; + + br_multicast_leave_group(br, port, &br_group, &br->ip4_other_query, +- own_query); ++ own_query, src); + } + + #if IS_ENABLED(CONFIG_IPV6) + static void br_ip6_multicast_leave_group(struct net_bridge *br, + struct net_bridge_port *port, + const struct in6_addr *group, +- __u16 vid) ++ __u16 vid, const unsigned char *src) + { + struct br_ip br_group; + struct bridge_mcast_own_query *own_query; +@@ -1565,7 +1592,7 @@ static void br_ip6_multicast_leave_group + br_group.vid = vid; + + br_multicast_leave_group(br, port, &br_group, &br->ip6_other_query, +- own_query); ++ own_query, src); + } + #endif + +@@ -1574,6 +1601,7 @@ static int br_multicast_ipv4_rcv(struct + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct sk_buff *skb_trimmed = NULL; + struct igmphdr *ih; + int err; +@@ -1590,12 +1618,13 @@ static int br_multicast_ipv4_rcv(struct + + BR_INPUT_SKB_CB(skb)->igmp = 1; + ih = igmp_hdr(skb); ++ src = eth_hdr(skb)->h_source; + + switch (ih->type) { + case IGMP_HOST_MEMBERSHIP_REPORT: + case IGMPV2_HOST_MEMBERSHIP_REPORT: + BR_INPUT_SKB_CB(skb)->mrouters_only = 1; +- err = br_ip4_multicast_add_group(br, port, ih->group, vid); ++ err = br_ip4_multicast_add_group(br, port, ih->group, vid, src); + break; + case IGMPV3_HOST_MEMBERSHIP_REPORT: + err = br_ip4_multicast_igmp3_report(br, port, skb_trimmed, vid); +@@ -1604,7 +1633,7 @@ static int br_multicast_ipv4_rcv(struct + err = br_ip4_multicast_query(br, port, skb_trimmed, vid); + break; + case IGMP_HOST_LEAVE_MESSAGE: +- br_ip4_multicast_leave_group(br, port, ih->group, vid); ++ br_ip4_multicast_leave_group(br, port, ih->group, vid, src); + break; + } + +@@ -1620,6 +1649,7 @@ static int br_multicast_ipv6_rcv(struct + struct sk_buff *skb, + u16 vid) + { ++ const unsigned char *src; + struct sk_buff *skb_trimmed = NULL; + struct mld_msg *mld; + int err; +@@ -1639,8 +1669,9 @@ static int br_multicast_ipv6_rcv(struct + + switch (mld->mld_type) { + case ICMPV6_MGM_REPORT: ++ src = eth_hdr(skb)->h_source; + BR_INPUT_SKB_CB(skb)->mrouters_only = 1; +- err = br_ip6_multicast_add_group(br, port, &mld->mld_mca, vid); ++ err = br_ip6_multicast_add_group(br, port, &mld->mld_mca, vid, src); + break; + case ICMPV6_MLD2_REPORT: + err = br_ip6_multicast_mld2_report(br, port, skb_trimmed, vid); +@@ -1649,7 +1680,8 @@ static int br_multicast_ipv6_rcv(struct + err = br_ip6_multicast_query(br, port, skb_trimmed, vid); + break; + case ICMPV6_MGM_REDUCTION: +- br_ip6_multicast_leave_group(br, port, &mld->mld_mca, vid); ++ src = eth_hdr(skb)->h_source; ++ br_ip6_multicast_leave_group(br, port, &mld->mld_mca, vid, src); + break; + } + +--- a/net/bridge/br_private.h ++++ b/net/bridge/br_private.h +@@ -114,6 +114,9 @@ struct net_bridge_port_group { + struct timer_list timer; + struct br_ip addr; + unsigned char state; ++ ++ unsigned char eth_addr[ETH_ALEN]; ++ bool unicast; + }; + + struct net_bridge_mdb_entry +@@ -485,7 +488,8 @@ void br_multicast_free_pg(struct rcu_hea + struct net_bridge_port_group * + br_multicast_new_port_group(struct net_bridge_port *port, struct br_ip *group, + struct net_bridge_port_group __rcu *next, +- unsigned char state); ++ unsigned char state, ++ const unsigned char *src); + void br_mdb_init(void); + void br_mdb_uninit(void); + void br_mdb_notify(struct net_device *dev, struct net_bridge_port *port, +--- a/net/bridge/br_mdb.c ++++ b/net/bridge/br_mdb.c +@@ -416,7 +416,7 @@ static int br_mdb_add_group(struct net_b + break; + } + +- p = br_multicast_new_port_group(port, group, *pp, state); ++ p = br_multicast_new_port_group(port, group, *pp, state, NULL); + if (unlikely(!p)) + return -ENOMEM; + rcu_assign_pointer(*pp, p); +--- a/net/bridge/br_forward.c ++++ b/net/bridge/br_forward.c +@@ -185,6 +185,34 @@ out: + return p; + } + ++static struct net_bridge_port *maybe_deliver_addr( ++ struct net_bridge_port *prev, struct net_bridge_port *p, ++ struct sk_buff *skb, const unsigned char *addr, ++ void (*__packet_hook)(const struct net_bridge_port *p, ++ struct sk_buff *skb)) ++{ ++ struct net_device *dev = BR_INPUT_SKB_CB(skb)->brdev; ++ const unsigned char *src = eth_hdr(skb)->h_source; ++ ++ if (!should_deliver(p, skb)) ++ return prev; ++ ++ /* Even with hairpin, no soliloquies - prevent breaking IPv6 DAD */ ++ if (skb->dev == p->dev && ether_addr_equal(src, addr)) ++ return prev; ++ ++ skb = skb_copy(skb, GFP_ATOMIC); ++ if (!skb) { ++ dev->stats.tx_dropped++; ++ return prev; ++ } ++ ++ memcpy(eth_hdr(skb)->h_dest, addr, ETH_ALEN); ++ __packet_hook(p, skb); ++ ++ return prev; ++} ++ + /* called under bridge lock */ + static void br_flood(struct net_bridge *br, struct sk_buff *skb, + struct sk_buff *skb0, +@@ -257,6 +285,7 @@ static void br_multicast_flood(struct ne + struct net_bridge_port *prev = NULL; + struct net_bridge_port_group *p; + struct hlist_node *rp; ++ const unsigned char *addr; + + rp = rcu_dereference(hlist_first_rcu(&br->router_list)); + p = mdst ? rcu_dereference(mdst->ports) : NULL; +@@ -267,10 +296,19 @@ static void br_multicast_flood(struct ne + rport = rp ? hlist_entry(rp, struct net_bridge_port, rlist) : + NULL; + +- port = (unsigned long)lport > (unsigned long)rport ? +- lport : rport; +- +- prev = maybe_deliver(prev, port, skb, __packet_hook); ++ if ((unsigned long)lport > (unsigned long)rport) { ++ port = lport; ++ addr = p->unicast ? p->eth_addr : NULL; ++ } else { ++ port = rport; ++ addr = NULL; ++ } ++ ++ if (addr) ++ prev = maybe_deliver_addr(prev, port, skb, addr, ++ __packet_hook); ++ else ++ prev = maybe_deliver(prev, port, skb, __packet_hook); + if (IS_ERR(prev)) + goto out; + +--- a/net/bridge/br_sysfs_if.c ++++ b/net/bridge/br_sysfs_if.c +@@ -204,6 +204,7 @@ static BRPORT_ATTR(multicast_router, S_I + store_multicast_router); + + BRPORT_ATTR_FLAG(multicast_fast_leave, BR_MULTICAST_FAST_LEAVE); ++BRPORT_ATTR_FLAG(multicast_to_unicast, BR_MULTICAST_TO_UCAST); + #endif + + static const struct brport_attribute *brport_attrs[] = { +@@ -230,6 +231,7 @@ static const struct brport_attribute *br + #ifdef CONFIG_BRIDGE_IGMP_SNOOPING + &brport_attr_multicast_router, + &brport_attr_multicast_fast_leave, ++ &brport_attr_multicast_to_unicast, + #endif + &brport_attr_proxyarp, + &brport_attr_proxyarp_wifi, diff --git a/target/linux/generic/patches-4.3/650-pppoe_header_pad.patch b/target/linux/generic/patches-4.3/650-pppoe_header_pad.patch new file mode 100644 index 0000000..2804469 --- /dev/null +++ b/target/linux/generic/patches-4.3/650-pppoe_header_pad.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/ppp/pppoe.c ++++ b/drivers/net/ppp/pppoe.c +@@ -871,7 +871,7 @@ static int pppoe_sendmsg(struct socket * + goto end; + + +- skb = sock_wmalloc(sk, total_len + dev->hard_header_len + 32, ++ skb = sock_wmalloc(sk, total_len + dev->hard_header_len + 32 + NET_SKB_PAD, + 0, GFP_KERNEL); + if (!skb) { + error = -ENOMEM; +@@ -879,7 +879,7 @@ static int pppoe_sendmsg(struct socket * + } + + /* Reserve space for headers. */ +- skb_reserve(skb, dev->hard_header_len); ++ skb_reserve(skb, dev->hard_header_len + NET_SKB_PAD); + skb_reset_network_header(skb); + + skb->dev = dev; diff --git a/target/linux/generic/patches-4.3/651-wireless_mesh_header.patch b/target/linux/generic/patches-4.3/651-wireless_mesh_header.patch new file mode 100644 index 0000000..17bcb6d --- /dev/null +++ b/target/linux/generic/patches-4.3/651-wireless_mesh_header.patch @@ -0,0 +1,11 @@ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -133,7 +133,7 @@ static inline bool dev_xmit_complete(int + */ + + #if defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) +-# if defined(CONFIG_MAC80211_MESH) ++# if 1 || defined(CONFIG_MAC80211_MESH) + # define LL_MAX_HEADER 128 + # else + # define LL_MAX_HEADER 96 diff --git a/target/linux/generic/patches-4.3/653-disable_netlink_trim.patch b/target/linux/generic/patches-4.3/653-disable_netlink_trim.patch new file mode 100644 index 0000000..2f64696 --- /dev/null +++ b/target/linux/generic/patches-4.3/653-disable_netlink_trim.patch @@ -0,0 +1,30 @@ +--- a/net/netlink/af_netlink.c ++++ b/net/netlink/af_netlink.c +@@ -1795,27 +1795,7 @@ void netlink_detachskb(struct sock *sk, + + static struct sk_buff *netlink_trim(struct sk_buff *skb, gfp_t allocation) + { +- int delta; +- + WARN_ON(skb->sk != NULL); +- if (netlink_skb_is_mmaped(skb)) +- return skb; +- +- delta = skb->end - skb->tail; +- if (is_vmalloc_addr(skb->head) || delta * 2 < skb->truesize) +- return skb; +- +- if (skb_shared(skb)) { +- struct sk_buff *nskb = skb_clone(skb, allocation); +- if (!nskb) +- return skb; +- consume_skb(skb); +- skb = nskb; +- } +- +- if (!pskb_expand_head(skb, 0, -delta, allocation)) +- skb->truesize -= delta; +- + return skb; + } + diff --git a/target/linux/generic/patches-4.3/655-increase_skb_pad.patch b/target/linux/generic/patches-4.3/655-increase_skb_pad.patch new file mode 100644 index 0000000..3e20bdf --- /dev/null +++ b/target/linux/generic/patches-4.3/655-increase_skb_pad.patch @@ -0,0 +1,11 @@ +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2145,7 +2145,7 @@ static inline int pskb_network_may_pull( + * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8) + */ + #ifndef NET_SKB_PAD +-#define NET_SKB_PAD max(32, L1_CACHE_BYTES) ++#define NET_SKB_PAD max(64, L1_CACHE_BYTES) + #endif + + int ___pskb_trim(struct sk_buff *skb, unsigned int len); diff --git a/target/linux/generic/patches-4.3/656-skb_reduce_truesize-helper.patch b/target/linux/generic/patches-4.3/656-skb_reduce_truesize-helper.patch new file mode 100644 index 0000000..4465b37 --- /dev/null +++ b/target/linux/generic/patches-4.3/656-skb_reduce_truesize-helper.patch @@ -0,0 +1,41 @@ +From 4593a806e31119c5bd3faa00c7210ad862d515af Mon Sep 17 00:00:00 2001 +From: Dave Taht +Date: Mon, 31 Dec 2012 10:02:21 -0800 +Subject: [PATCH 3/7] skb_reduce_truesize: helper function for shrinking skbs + whenever needed + +On embedded devices in particular, large queues of small packets from the rx +path with a large truesize can exist. Reducing their size can reduce +memory pressure. skb_reduce_truesize is a helper function for doing this, +when needed. +--- + include/linux/skbuff.h | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2190,6 +2190,24 @@ static inline void pskb_trim_unique(stru + BUG_ON(err); + } + ++/* ++ * Caller wants to reduce memory needs before queueing skb ++ * The (expensive) copy should not be be done in fast path. ++ */ ++static inline struct sk_buff *skb_reduce_truesize(struct sk_buff *skb) ++{ ++ if (skb->truesize > 2 * SKB_TRUESIZE(skb->len)) { ++ struct sk_buff *nskb; ++ nskb = skb_copy_expand(skb, skb_headroom(skb), 0, ++ GFP_ATOMIC | __GFP_NOWARN); ++ if (nskb) { ++ __kfree_skb(skb); ++ skb = nskb; ++ } ++ } ++ return skb; ++} ++ + /** + * skb_orphan - orphan a buffer + * @skb: buffer to orphan diff --git a/target/linux/generic/patches-4.3/657-qdisc_reduce_truesize.patch b/target/linux/generic/patches-4.3/657-qdisc_reduce_truesize.patch new file mode 100644 index 0000000..d9f5b4f --- /dev/null +++ b/target/linux/generic/patches-4.3/657-qdisc_reduce_truesize.patch @@ -0,0 +1,63 @@ +From bc9fec2f87d57bdbff30d296605e24504513f65c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Dave=20T=C3=A4ht?= +Date: Mon, 17 Sep 2012 19:20:22 -0700 +Subject: [PATCH 4/7] net: add skb_reduce_truesize support to common qdiscs + +Reduce skb size under load when queues begin to fill on the +commont qdiscs. +--- + net/sched/sch_codel.c | 2 ++ + net/sched/sch_fifo.c | 12 ++++++++---- + net/sched/sch_fq_codel.c | 2 ++ + 3 files changed, 12 insertions(+), 4 deletions(-) + +--- a/net/sched/sch_codel.c ++++ b/net/sched/sch_codel.c +@@ -96,6 +96,8 @@ static int codel_qdisc_enqueue(struct sk + struct codel_sched_data *q; + + if (likely(qdisc_qlen(sch) < sch->limit)) { ++ if(qdisc_qlen(sch) > 128) ++ skb = skb_reduce_truesize(skb); + codel_set_enqueue_time(skb); + return qdisc_enqueue_tail(skb, sch); + } +--- a/net/sched/sch_fifo.c ++++ b/net/sched/sch_fifo.c +@@ -29,17 +29,21 @@ static int bfifo_enqueue(struct sk_buff + + static int pfifo_enqueue(struct sk_buff *skb, struct Qdisc *sch) + { +- if (likely(skb_queue_len(&sch->q) < sch->limit)) ++ if (likely(skb_queue_len(&sch->q) < sch->limit)) { ++ if (skb_queue_len(&sch->q) > 128) ++ skb = skb_reduce_truesize(skb); + return qdisc_enqueue_tail(skb, sch); +- ++ } + return qdisc_reshape_fail(skb, sch); + } + + static int pfifo_tail_enqueue(struct sk_buff *skb, struct Qdisc *sch) + { +- if (likely(skb_queue_len(&sch->q) < sch->limit)) ++ if (likely(skb_queue_len(&sch->q) < sch->limit)) { ++ if (skb_queue_len(&sch->q) > 128) ++ skb = skb_reduce_truesize(skb); + return qdisc_enqueue_tail(skb, sch); +- ++ } + /* queue full, remove one skb to fulfill the limit */ + __qdisc_queue_drop_head(sch, &sch->q); + qdisc_qstats_drop(sch); +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -187,6 +187,8 @@ static int fq_codel_enqueue(struct sk_bu + return ret; + } + idx--; ++ if (sch->q.qlen > 128) ++ skb = skb_reduce_truesize(skb); + + codel_set_enqueue_time(skb); + flow = &q->flows[idx]; diff --git a/target/linux/generic/patches-4.3/660-fq_codel_defaults.patch b/target/linux/generic/patches-4.3/660-fq_codel_defaults.patch new file mode 100644 index 0000000..a2ff805 --- /dev/null +++ b/target/linux/generic/patches-4.3/660-fq_codel_defaults.patch @@ -0,0 +1,14 @@ +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -412,9 +412,9 @@ static int fq_codel_init(struct Qdisc *s + struct fq_codel_sched_data *q = qdisc_priv(sch); + int i; + +- sch->limit = 10*1024; ++ sch->limit = 1024; + q->flows_cnt = 1024; +- q->quantum = psched_mtu(qdisc_dev(sch)); ++ q->quantum = 300; + q->perturbation = prandom_u32(); + INIT_LIST_HEAD(&q->new_flows); + INIT_LIST_HEAD(&q->old_flows); diff --git a/target/linux/generic/patches-4.3/661-fq_codel_keep_dropped_stats.patch b/target/linux/generic/patches-4.3/661-fq_codel_keep_dropped_stats.patch new file mode 100644 index 0000000..0efc61b --- /dev/null +++ b/target/linux/generic/patches-4.3/661-fq_codel_keep_dropped_stats.patch @@ -0,0 +1,10 @@ +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -200,7 +200,6 @@ static int fq_codel_enqueue(struct sk_bu + list_add_tail(&flow->flowchain, &q->new_flows); + q->new_flow_count++; + flow->deficit = q->quantum; +- flow->dropped = 0; + } + if (++sch->q.qlen <= sch->limit) + return NET_XMIT_SUCCESS; diff --git a/target/linux/generic/patches-4.3/662-use_fq_codel_by_default.patch b/target/linux/generic/patches-4.3/662-use_fq_codel_by_default.patch new file mode 100644 index 0000000..fba373a --- /dev/null +++ b/target/linux/generic/patches-4.3/662-use_fq_codel_by_default.patch @@ -0,0 +1,75 @@ +--- a/net/sched/Kconfig ++++ b/net/sched/Kconfig +@@ -3,8 +3,9 @@ + # + + menuconfig NET_SCHED +- bool "QoS and/or fair queueing" ++ def_bool y + select NET_SCH_FIFO ++ select NET_SCH_FQ_CODEL + ---help--- + When the kernel has several packets to send out over a network + device, it has to decide which ones to send first, which ones to +--- a/net/sched/sch_fq_codel.c ++++ b/net/sched/sch_fq_codel.c +@@ -623,7 +623,7 @@ static const struct Qdisc_class_ops fq_c + .walk = fq_codel_walk, + }; + +-static struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = { ++struct Qdisc_ops fq_codel_qdisc_ops __read_mostly = { + .cl_ops = &fq_codel_class_ops, + .id = "fq_codel", + .priv_size = sizeof(struct fq_codel_sched_data), +@@ -639,6 +639,7 @@ static struct Qdisc_ops fq_codel_qdisc_o + .dump_stats = fq_codel_dump_stats, + .owner = THIS_MODULE, + }; ++EXPORT_SYMBOL(fq_codel_qdisc_ops); + + static int __init fq_codel_module_init(void) + { +--- a/include/net/sch_generic.h ++++ b/include/net/sch_generic.h +@@ -341,6 +341,7 @@ extern struct Qdisc_ops noop_qdisc_ops; + extern struct Qdisc_ops pfifo_fast_ops; + extern struct Qdisc_ops mq_qdisc_ops; + extern struct Qdisc_ops noqueue_qdisc_ops; ++extern struct Qdisc_ops fq_codel_qdisc_ops; + extern const struct Qdisc_ops *default_qdisc_ops; + + struct Qdisc_class_common { +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -726,7 +726,7 @@ static void attach_one_default_qdisc(str + void *_unused) + { + struct Qdisc *qdisc; +- const struct Qdisc_ops *ops = default_qdisc_ops; ++ const struct Qdisc_ops *ops = &fq_codel_qdisc_ops; + + if (dev->priv_flags & IFF_NO_QUEUE) + ops = &noqueue_qdisc_ops; +--- a/net/sched/sch_mq.c ++++ b/net/sched/sch_mq.c +@@ -57,7 +57,7 @@ static int mq_init(struct Qdisc *sch, st + + for (ntx = 0; ntx < dev->num_tx_queues; ntx++) { + dev_queue = netdev_get_tx_queue(dev, ntx); +- qdisc = qdisc_create_dflt(dev_queue, default_qdisc_ops, ++ qdisc = qdisc_create_dflt(dev_queue, &fq_codel_qdisc_ops, + TC_H_MAKE(TC_H_MAJ(sch->handle), + TC_H_MIN(ntx + 1))); + if (qdisc == NULL) +--- a/net/sched/sch_mqprio.c ++++ b/net/sched/sch_mqprio.c +@@ -124,7 +124,7 @@ static int mqprio_init(struct Qdisc *sch + + for (i = 0; i < dev->num_tx_queues; i++) { + dev_queue = netdev_get_tx_queue(dev, i); +- qdisc = qdisc_create_dflt(dev_queue, default_qdisc_ops, ++ qdisc = qdisc_create_dflt(dev_queue, &fq_codel_qdisc_ops, + TC_H_MAKE(TC_H_MAJ(sch->handle), + TC_H_MIN(i + 1))); + if (qdisc == NULL) { diff --git a/target/linux/generic/patches-4.3/663-remove_pfifo_fast.patch b/target/linux/generic/patches-4.3/663-remove_pfifo_fast.patch new file mode 100644 index 0000000..d28835b --- /dev/null +++ b/target/linux/generic/patches-4.3/663-remove_pfifo_fast.patch @@ -0,0 +1,142 @@ +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -435,139 +435,6 @@ struct Qdisc_ops noqueue_qdisc_ops __rea + .owner = THIS_MODULE, + }; + +-static const u8 prio2band[TC_PRIO_MAX + 1] = { +- 1, 2, 2, 2, 1, 2, 0, 0 , 1, 1, 1, 1, 1, 1, 1, 1 +-}; +- +-/* 3-band FIFO queue: old style, but should be a bit faster than +- generic prio+fifo combination. +- */ +- +-#define PFIFO_FAST_BANDS 3 +- +-/* +- * Private data for a pfifo_fast scheduler containing: +- * - queues for the three band +- * - bitmap indicating which of the bands contain skbs +- */ +-struct pfifo_fast_priv { +- u32 bitmap; +- struct sk_buff_head q[PFIFO_FAST_BANDS]; +-}; +- +-/* +- * Convert a bitmap to the first band number where an skb is queued, where: +- * bitmap=0 means there are no skbs on any band. +- * bitmap=1 means there is an skb on band 0. +- * bitmap=7 means there are skbs on all 3 bands, etc. +- */ +-static const int bitmap2band[] = {-1, 0, 1, 0, 2, 0, 1, 0}; +- +-static inline struct sk_buff_head *band2list(struct pfifo_fast_priv *priv, +- int band) +-{ +- return priv->q + band; +-} +- +-static int pfifo_fast_enqueue(struct sk_buff *skb, struct Qdisc *qdisc) +-{ +- if (skb_queue_len(&qdisc->q) < qdisc_dev(qdisc)->tx_queue_len) { +- int band = prio2band[skb->priority & TC_PRIO_MAX]; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- struct sk_buff_head *list = band2list(priv, band); +- +- priv->bitmap |= (1 << band); +- qdisc->q.qlen++; +- return __qdisc_enqueue_tail(skb, qdisc, list); +- } +- +- return qdisc_drop(skb, qdisc); +-} +- +-static struct sk_buff *pfifo_fast_dequeue(struct Qdisc *qdisc) +-{ +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- int band = bitmap2band[priv->bitmap]; +- +- if (likely(band >= 0)) { +- struct sk_buff_head *list = band2list(priv, band); +- struct sk_buff *skb = __qdisc_dequeue_head(qdisc, list); +- +- qdisc->q.qlen--; +- if (skb_queue_empty(list)) +- priv->bitmap &= ~(1 << band); +- +- return skb; +- } +- +- return NULL; +-} +- +-static struct sk_buff *pfifo_fast_peek(struct Qdisc *qdisc) +-{ +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- int band = bitmap2band[priv->bitmap]; +- +- if (band >= 0) { +- struct sk_buff_head *list = band2list(priv, band); +- +- return skb_peek(list); +- } +- +- return NULL; +-} +- +-static void pfifo_fast_reset(struct Qdisc *qdisc) +-{ +- int prio; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- +- for (prio = 0; prio < PFIFO_FAST_BANDS; prio++) +- __qdisc_reset_queue(qdisc, band2list(priv, prio)); +- +- priv->bitmap = 0; +- qdisc->qstats.backlog = 0; +- qdisc->q.qlen = 0; +-} +- +-static int pfifo_fast_dump(struct Qdisc *qdisc, struct sk_buff *skb) +-{ +- struct tc_prio_qopt opt = { .bands = PFIFO_FAST_BANDS }; +- +- memcpy(&opt.priomap, prio2band, TC_PRIO_MAX + 1); +- if (nla_put(skb, TCA_OPTIONS, sizeof(opt), &opt)) +- goto nla_put_failure; +- return skb->len; +- +-nla_put_failure: +- return -1; +-} +- +-static int pfifo_fast_init(struct Qdisc *qdisc, struct nlattr *opt) +-{ +- int prio; +- struct pfifo_fast_priv *priv = qdisc_priv(qdisc); +- +- for (prio = 0; prio < PFIFO_FAST_BANDS; prio++) +- __skb_queue_head_init(band2list(priv, prio)); +- +- /* Can by-pass the queue discipline */ +- qdisc->flags |= TCQ_F_CAN_BYPASS; +- return 0; +-} +- +-struct Qdisc_ops pfifo_fast_ops __read_mostly = { +- .id = "pfifo_fast", +- .priv_size = sizeof(struct pfifo_fast_priv), +- .enqueue = pfifo_fast_enqueue, +- .dequeue = pfifo_fast_dequeue, +- .peek = pfifo_fast_peek, +- .init = pfifo_fast_init, +- .reset = pfifo_fast_reset, +- .dump = pfifo_fast_dump, +- .owner = THIS_MODULE, +-}; +- + static struct lock_class_key qdisc_tx_busylock; + + struct Qdisc *qdisc_alloc(struct netdev_queue *dev_queue, diff --git a/target/linux/generic/patches-4.3/664-codel_fix_3_12.patch b/target/linux/generic/patches-4.3/664-codel_fix_3_12.patch new file mode 100644 index 0000000..838c9f6 --- /dev/null +++ b/target/linux/generic/patches-4.3/664-codel_fix_3_12.patch @@ -0,0 +1,22 @@ +--- a/net/sched/sch_api.c ++++ b/net/sched/sch_api.c +@@ -1936,7 +1936,7 @@ static int __init pktsched_init(void) + return err; + } + +- register_qdisc(&pfifo_fast_ops); ++ register_qdisc(&fq_codel_qdisc_ops); + register_qdisc(&pfifo_qdisc_ops); + register_qdisc(&bfifo_qdisc_ops); + register_qdisc(&pfifo_head_drop_qdisc_ops); +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -31,7 +31,7 @@ + #include + + /* Qdisc to use by default */ +-const struct Qdisc_ops *default_qdisc_ops = &pfifo_fast_ops; ++const struct Qdisc_ops *default_qdisc_ops = &fq_codel_qdisc_ops; + EXPORT_SYMBOL(default_qdisc_ops); + + /* Main transmission queue. */ diff --git a/target/linux/generic/patches-4.3/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/patches-4.3/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch new file mode 100644 index 0000000..7123c80 --- /dev/null +++ b/target/linux/generic/patches-4.3/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch @@ -0,0 +1,495 @@ +From 775d6fe74d1eaec2ba387535b068dde2dc89de9e Mon Sep 17 00:00:00 2001 +From: Steven Barth +Date: Thu, 22 May 2014 09:49:05 +0200 +Subject: [PATCH] Add support for MAP-E FMRs (mesh mode) + +MAP-E FMRs (draft-ietf-softwire-map-10) are rules for IPv4-communication +between MAP CEs (mesh mode) without the need to forward such data to a +border relay. This is similar to how 6rd works but for IPv4 over IPv6. + +Signed-off-by: Steven Barth +--- + include/net/ip6_tunnel.h | 13 ++ + include/uapi/linux/if_tunnel.h | 13 ++ + net/ipv6/ip6_tunnel.c | 276 +++++++++++++++++++++++++++++++++++++++-- + 3 files changed, 291 insertions(+), 11 deletions(-) + +--- a/include/net/ip6_tunnel.h ++++ b/include/net/ip6_tunnel.h +@@ -15,6 +15,18 @@ + /* determine capability on a per-packet basis */ + #define IP6_TNL_F_CAP_PER_PACKET 0x40000 + ++/* IPv6 tunnel FMR */ ++struct __ip6_tnl_fmr { ++ struct __ip6_tnl_fmr *next; /* next fmr in list */ ++ struct in6_addr ip6_prefix; ++ struct in_addr ip4_prefix; ++ ++ __u8 ip6_prefix_len; ++ __u8 ip4_prefix_len; ++ __u8 ea_len; ++ __u8 offset; ++}; ++ + struct __ip6_tnl_parm { + char name[IFNAMSIZ]; /* name of tunnel device */ + int link; /* ifindex of underlying L2 interface */ +@@ -25,6 +37,7 @@ struct __ip6_tnl_parm { + __u32 flags; /* tunnel flags */ + struct in6_addr laddr; /* local tunnel end-point address */ + struct in6_addr raddr; /* remote tunnel end-point address */ ++ struct __ip6_tnl_fmr *fmrs; /* FMRs */ + + __be16 i_flags; + __be16 o_flags; +--- a/include/uapi/linux/if_tunnel.h ++++ b/include/uapi/linux/if_tunnel.h +@@ -57,10 +57,23 @@ enum { + IFLA_IPTUN_ENCAP_FLAGS, + IFLA_IPTUN_ENCAP_SPORT, + IFLA_IPTUN_ENCAP_DPORT, ++ IFLA_IPTUN_FMRS, + __IFLA_IPTUN_MAX, + }; + #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) + ++enum { ++ IFLA_IPTUN_FMR_UNSPEC, ++ IFLA_IPTUN_FMR_IP6_PREFIX, ++ IFLA_IPTUN_FMR_IP4_PREFIX, ++ IFLA_IPTUN_FMR_IP6_PREFIX_LEN, ++ IFLA_IPTUN_FMR_IP4_PREFIX_LEN, ++ IFLA_IPTUN_FMR_EA_LEN, ++ IFLA_IPTUN_FMR_OFFSET, ++ __IFLA_IPTUN_FMR_MAX, ++}; ++#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1) ++ + enum tunnel_encap_types { + TUNNEL_ENCAP_NONE, + TUNNEL_ENCAP_FOU, +--- a/net/ipv6/ip6_tunnel.c ++++ b/net/ipv6/ip6_tunnel.c +@@ -16,6 +16,8 @@ + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * ++ * Changes: ++ * Steven Barth : MAP-E FMR support + */ + + #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +@@ -71,11 +73,9 @@ static bool log_ecn_error = true; + module_param(log_ecn_error, bool, 0644); + MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN"); + +-static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2) ++static u32 HASH(const struct in6_addr *addr) + { +- u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2); +- +- return hash_32(hash, HASH_SIZE_SHIFT); ++ return hash_32(ipv6_addr_hash(addr), HASH_SIZE_SHIFT); + } + + static int ip6_tnl_dev_init(struct net_device *dev); +@@ -230,27 +230,36 @@ EXPORT_SYMBOL_GPL(ip6_tnl_dst_init); + static struct ip6_tnl * + ip6_tnl_lookup(struct net *net, const struct in6_addr *remote, const struct in6_addr *local) + { +- unsigned int hash = HASH(remote, local); ++ unsigned int hash = HASH(local); + struct ip6_tnl *t; + struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + struct in6_addr any; ++ struct __ip6_tnl_fmr *fmr; + + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { +- if (ipv6_addr_equal(local, &t->parms.laddr) && +- ipv6_addr_equal(remote, &t->parms.raddr) && +- (t->dev->flags & IFF_UP)) ++ if (!ipv6_addr_equal(local, &t->parms.laddr) || ++ !(t->dev->flags & IFF_UP)) ++ continue; ++ ++ if (ipv6_addr_equal(remote, &t->parms.raddr)) + return t; ++ ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { ++ if (ipv6_prefix_equal(remote, &fmr->ip6_prefix, ++ fmr->ip6_prefix_len)) ++ return t; ++ } + } + + memset(&any, 0, sizeof(any)); +- hash = HASH(&any, local); ++ hash = HASH(local); + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { + if (ipv6_addr_equal(local, &t->parms.laddr) && + (t->dev->flags & IFF_UP)) + return t; + } + +- hash = HASH(remote, &any); ++ hash = HASH(&any); + for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { + if (ipv6_addr_equal(remote, &t->parms.raddr) && + (t->dev->flags & IFF_UP)) +@@ -285,7 +294,7 @@ ip6_tnl_bucket(struct ip6_tnl_net *ip6n, + + if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) { + prio = 1; +- h = HASH(remote, local); ++ h = HASH(local); + } + return &ip6n->tnls[prio][h]; + } +@@ -458,6 +467,12 @@ ip6_tnl_dev_uninit(struct net_device *de + struct net *net = t->net; + struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + ++ while (t->parms.fmrs) { ++ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; ++ kfree(t->parms.fmrs); ++ t->parms.fmrs = next; ++ } ++ + if (dev == ip6n->fb_tnl_dev) + RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL); + else +@@ -844,6 +859,108 @@ int ip6_tnl_rcv_ctl(struct ip6_tnl *t, + } + EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl); + ++ ++/** ++ * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR ++ * @dest: destination IPv6 address buffer ++ * @skb: received socket buffer ++ * @fmr: MAP FMR ++ * @xmit: Calculate for xmit or rcv ++ **/ ++static void ip4ip6_fmr_calc(struct in6_addr *dest, ++ const struct iphdr *iph, const uint8_t *end, ++ const struct __ip6_tnl_fmr *fmr, bool xmit) ++{ ++ int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len); ++ u8 *portp = NULL; ++ bool use_dest_addr; ++ const struct iphdr *dsth = iph; ++ ++ if ((u8*)dsth >= end) ++ return; ++ ++ /* find significant IP header */ ++ if (iph->protocol == IPPROTO_ICMP) { ++ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); ++ if (ih && ((u8*)&ih[1]) <= end && ( ++ ih->type == ICMP_DEST_UNREACH || ++ ih->type == ICMP_SOURCE_QUENCH || ++ ih->type == ICMP_TIME_EXCEEDED || ++ ih->type == ICMP_PARAMETERPROB || ++ ih->type == ICMP_REDIRECT)) ++ dsth = (const struct iphdr*)&ih[1]; ++ } ++ ++ /* in xmit-path use dest port by default and source port only if ++ this is an ICMP reply to something else; vice versa in rcv-path */ ++ use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph); ++ ++ /* get dst port */ ++ if (((u8*)&dsth[1]) <= end && ( ++ dsth->protocol == IPPROTO_UDP || ++ dsth->protocol == IPPROTO_TCP || ++ dsth->protocol == IPPROTO_SCTP || ++ dsth->protocol == IPPROTO_DCCP)) { ++ /* for UDP, TCP, SCTP and DCCP source and dest port ++ follow IPv4 header directly */ ++ portp = ((u8*)dsth) + dsth->ihl * 4; ++ ++ if (use_dest_addr) ++ portp += sizeof(u16); ++ } else if (iph->protocol == IPPROTO_ICMP) { ++ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); ++ ++ /* use icmp identifier as port */ ++ if (((u8*)&ih) <= end && ( ++ (use_dest_addr && ( ++ ih->type == ICMP_ECHOREPLY || ++ ih->type == ICMP_TIMESTAMPREPLY || ++ ih->type == ICMP_INFO_REPLY || ++ ih->type == ICMP_ADDRESSREPLY)) || ++ (!use_dest_addr && ( ++ ih->type == ICMP_ECHO || ++ ih->type == ICMP_TIMESTAMP || ++ ih->type == ICMP_INFO_REQUEST || ++ ih->type == ICMP_ADDRESS) ++ ))) ++ portp = (u8*)&ih->un.echo.id; ++ } ++ ++ if ((portp && &portp[2] <= end) || psidlen == 0) { ++ int frombyte = fmr->ip6_prefix_len / 8; ++ int fromrem = fmr->ip6_prefix_len % 8; ++ int bytes = sizeof(struct in6_addr) - frombyte; ++ const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr; ++ u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len); ++ u64 t = 0; ++ ++ /* extract PSID from port and add it to eabits */ ++ u16 psidbits = 0; ++ if (psidlen > 0) { ++ psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]); ++ psidbits >>= 16 - psidlen - fmr->offset; ++ psidbits = (u16)(psidbits << (16 - psidlen)); ++ eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen)); ++ } ++ ++ /* rewrite destination address */ ++ *dest = fmr->ip6_prefix; ++ memcpy(&dest->s6_addr[10], addr, sizeof(*addr)); ++ dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen)); ++ ++ if (bytes > sizeof(u64)) ++ bytes = sizeof(u64); ++ ++ /* insert eabits */ ++ memcpy(&t, &dest->s6_addr[frombyte], bytes); ++ t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1) ++ << (64 - fmr->ea_len - fromrem)); ++ t = cpu_to_be64(t | (eabits >> fromrem)); ++ memcpy(&dest->s6_addr[frombyte], &t, bytes); ++ } ++} ++ ++ + /** + * ip6_tnl_rcv - decapsulate IPv6 packet and retransmit it locally + * @skb: received socket buffer +@@ -889,6 +1006,26 @@ static int ip6_tnl_rcv(struct sk_buff *s + skb_reset_network_header(skb); + skb->protocol = htons(protocol); + memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); ++ if (protocol == ETH_P_IP && ++ !ipv6_addr_equal(&ipv6h->saddr, &t->parms.raddr)) { ++ /* Packet didn't come from BR, so lookup FMR */ ++ struct __ip6_tnl_fmr *fmr; ++ struct in6_addr expected = t->parms.raddr; ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) ++ if (ipv6_prefix_equal(&ipv6h->saddr, ++ &fmr->ip6_prefix, fmr->ip6_prefix_len)) ++ break; ++ ++ /* Check that IPv6 matches IPv4 source to prevent spoofing */ ++ if (fmr) ++ ip4ip6_fmr_calc(&expected, ip_hdr(skb), ++ skb_tail_pointer(skb), fmr, false); ++ ++ if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) { ++ rcu_read_unlock(); ++ goto discard; ++ } ++ } + + __skb_tunnel_rx(skb, t->dev, t->net); + +@@ -1179,6 +1316,7 @@ ip4ip6_tnl_xmit(struct sk_buff *skb, str + __u32 mtu; + u8 tproto; + int err; ++ struct __ip6_tnl_fmr *fmr; + + tproto = ACCESS_ONCE(t->parms.proto); + if (tproto != IPPROTO_IPIP && tproto != 0) +@@ -1198,6 +1336,18 @@ ip4ip6_tnl_xmit(struct sk_buff *skb, str + if (t->parms.flags & IP6_TNL_F_USE_ORIG_FWMARK) + fl6.flowi6_mark = skb->mark; + ++ /* try to find matching FMR */ ++ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { ++ unsigned mshift = 32 - fmr->ip4_prefix_len; ++ if (ntohl(fmr->ip4_prefix.s_addr) >> mshift == ++ ntohl(iph->daddr) >> mshift) ++ break; ++ } ++ ++ /* change dstaddr according to FMR */ ++ if (fmr) ++ ip4ip6_fmr_calc(&fl6.daddr, iph, skb_tail_pointer(skb), fmr, true); ++ + err = ip6_tnl_xmit2(skb, dev, dsfield, &fl6, encap_limit, &mtu); + if (err != 0) { + /* XXX: send ICMP error even if DF is not set. */ +@@ -1366,6 +1516,14 @@ ip6_tnl_change(struct ip6_tnl *t, const + t->parms.flowinfo = p->flowinfo; + t->parms.link = p->link; + t->parms.proto = p->proto; ++ ++ while (t->parms.fmrs) { ++ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; ++ kfree(t->parms.fmrs); ++ t->parms.fmrs = next; ++ } ++ t->parms.fmrs = p->fmrs; ++ + ip6_tnl_dst_reset(t); + ip6_tnl_link_config(t); + return 0; +@@ -1404,6 +1562,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_ + p->flowinfo = u->flowinfo; + p->link = u->link; + p->proto = u->proto; ++ p->fmrs = NULL; + memcpy(p->name, u->name, sizeof(u->name)); + } + +@@ -1699,6 +1858,15 @@ static int ip6_tnl_validate(struct nlatt + return 0; + } + ++static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = { ++ [IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) }, ++ [IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) }, ++ [IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 } ++}; ++ + static void ip6_tnl_netlink_parms(struct nlattr *data[], + struct __ip6_tnl_parm *parms) + { +@@ -1730,6 +1898,46 @@ static void ip6_tnl_netlink_parms(struct + + if (data[IFLA_IPTUN_PROTO]) + parms->proto = nla_get_u8(data[IFLA_IPTUN_PROTO]); ++ ++ if (data[IFLA_IPTUN_FMRS]) { ++ unsigned rem; ++ struct nlattr *fmr; ++ nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) { ++ struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c; ++ struct __ip6_tnl_fmr *nfmr; ++ ++ nla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX, ++ fmr, ip6_tnl_fmr_policy); ++ ++ if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL))) ++ continue; ++ ++ nfmr->offset = 6; ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX])) ++ nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX], ++ sizeof(nfmr->ip6_prefix)); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX])) ++ nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX], ++ sizeof(nfmr->ip4_prefix)); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN])) ++ nfmr->ip6_prefix_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN])) ++ nfmr->ip4_prefix_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN])) ++ nfmr->ea_len = nla_get_u8(c); ++ ++ if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET])) ++ nfmr->offset = nla_get_u8(c); ++ ++ nfmr->next = parms->fmrs; ++ parms->fmrs = nfmr; ++ } ++ } + } + + static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev, +@@ -1782,6 +1990,12 @@ static void ip6_tnl_dellink(struct net_d + + static size_t ip6_tnl_get_size(const struct net_device *dev) + { ++ const struct ip6_tnl *t = netdev_priv(dev); ++ struct __ip6_tnl_fmr *c; ++ int fmrs = 0; ++ for (c = t->parms.fmrs; c; c = c->next) ++ ++fmrs; ++ + return + /* IFLA_IPTUN_LINK */ + nla_total_size(4) + +@@ -1799,6 +2013,24 @@ static size_t ip6_tnl_get_size(const str + nla_total_size(4) + + /* IFLA_IPTUN_PROTO */ + nla_total_size(1) + ++ /* IFLA_IPTUN_FMRS */ ++ nla_total_size(0) + ++ ( ++ /* nest */ ++ nla_total_size(0) + ++ /* IFLA_IPTUN_FMR_IP6_PREFIX */ ++ nla_total_size(sizeof(struct in6_addr)) + ++ /* IFLA_IPTUN_FMR_IP4_PREFIX */ ++ nla_total_size(sizeof(struct in_addr)) + ++ /* IFLA_IPTUN_FMR_EA_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */ ++ nla_total_size(1) + ++ /* IFLA_IPTUN_FMR_OFFSET */ ++ nla_total_size(1) ++ ) * fmrs + + 0; + } + +@@ -1806,6 +2038,9 @@ static int ip6_tnl_fill_info(struct sk_b + { + struct ip6_tnl *tunnel = netdev_priv(dev); + struct __ip6_tnl_parm *parm = &tunnel->parms; ++ struct __ip6_tnl_fmr *c; ++ int fmrcnt = 0; ++ struct nlattr *fmrs; + + if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || + nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || +@@ -1814,8 +2049,27 @@ static int ip6_tnl_fill_info(struct sk_b + nla_put_u8(skb, IFLA_IPTUN_ENCAP_LIMIT, parm->encap_limit) || + nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || + nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || +- nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto)) ++ nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || ++ !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS))) + goto nla_put_failure; ++ ++ for (c = parm->fmrs; c; c = c->next) { ++ struct nlattr *fmr = nla_nest_start(skb, ++fmrcnt); ++ if (!fmr || ++ nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX, ++ sizeof(c->ip6_prefix), &c->ip6_prefix) || ++ nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX, ++ sizeof(c->ip4_prefix), &c->ip4_prefix) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) || ++ nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset)) ++ goto nla_put_failure; ++ ++ nla_nest_end(skb, fmr); ++ } ++ nla_nest_end(skb, fmrs); ++ + return 0; + + nla_put_failure: +@@ -1839,6 +2093,7 @@ static const struct nla_policy ip6_tnl_p + [IFLA_IPTUN_FLOWINFO] = { .type = NLA_U32 }, + [IFLA_IPTUN_FLAGS] = { .type = NLA_U32 }, + [IFLA_IPTUN_PROTO] = { .type = NLA_U8 }, ++ [IFLA_IPTUN_FMRS] = { .type = NLA_NESTED }, + }; + + static struct rtnl_link_ops ip6_link_ops __read_mostly = { diff --git a/target/linux/generic/patches-4.3/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/patches-4.3/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch new file mode 100644 index 0000000..d2e1465 --- /dev/null +++ b/target/linux/generic/patches-4.3/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch @@ -0,0 +1,249 @@ +From 1b5aaa4b16f6e6471ab1c07b38068197a1b4c395 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Fri, 24 May 2013 14:40:54 +0200 +Subject: [PATCH 1/2] ipv6: allow rejecting with "source address failed policy" + +RFC6204 L-14 requires rejecting traffic from invalid addresses with +ICMPv6 Destination Unreachable, Code 5 (Source address failed ingress/ +egress policy) on the LAN side, so add an appropriate rule for that. + +Signed-off-by: Jonas Gorski +--- + include/net/netns/ipv6.h | 1 + + include/uapi/linux/fib_rules.h | 4 +++ + include/uapi/linux/rtnetlink.h | 1 + + net/ipv4/fib_semantics.c | 4 +++ + net/ipv4/fib_trie.c | 1 + + net/ipv4/ipmr.c | 1 + + net/ipv6/fib6_rules.c | 4 +++ + net/ipv6/ip6mr.c | 2 ++ + net/ipv6/route.c | 58 +++++++++++++++++++++++++++++++++++++++++- + 9 files changed, 75 insertions(+), 1 deletion(-) + +--- a/include/net/netns/ipv6.h ++++ b/include/net/netns/ipv6.h +@@ -63,6 +63,7 @@ struct netns_ipv6 { + unsigned long ip6_rt_last_gc; + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + struct rt6_info *ip6_prohibit_entry; ++ struct rt6_info *ip6_policy_failed_entry; + struct rt6_info *ip6_blk_hole_entry; + struct fib6_table *fib6_local_tbl; + struct fib_rules_ops *fib6_rules_ops; +--- a/include/uapi/linux/fib_rules.h ++++ b/include/uapi/linux/fib_rules.h +@@ -64,6 +64,10 @@ enum { + FR_ACT_BLACKHOLE, /* Drop without notification */ + FR_ACT_UNREACHABLE, /* Drop with ENETUNREACH */ + FR_ACT_PROHIBIT, /* Drop with EACCES */ ++ FR_ACT_RES9, ++ FR_ACT_RES10, ++ FR_ACT_RES11, ++ FR_ACT_POLICY_FAILED, /* Drop with EACCES */ + __FR_ACT_MAX, + }; + +--- a/include/uapi/linux/rtnetlink.h ++++ b/include/uapi/linux/rtnetlink.h +@@ -210,6 +210,7 @@ enum { + RTN_THROW, /* Not in this table */ + RTN_NAT, /* Translate this address */ + RTN_XRESOLVE, /* Use external resolver */ ++ RTN_POLICY_FAILED, /* Failed ingress/egress policy */ + __RTN_MAX + }; + +--- a/net/ipv4/fib_semantics.c ++++ b/net/ipv4/fib_semantics.c +@@ -139,6 +139,10 @@ const struct fib_prop fib_props[RTN_MAX + .error = -EINVAL, + .scope = RT_SCOPE_NOWHERE, + }, ++ [RTN_POLICY_FAILED] = { ++ .error = -EACCES, ++ .scope = RT_SCOPE_UNIVERSE, ++ }, + }; + + static void rt_fibinfo_free(struct rtable __rcu **rtp) +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -2368,6 +2368,7 @@ static const char *const rtn_type_names[ + [RTN_THROW] = "THROW", + [RTN_NAT] = "NAT", + [RTN_XRESOLVE] = "XRESOLVE", ++ [RTN_POLICY_FAILED] = "POLICY_FAILED", + }; + + static inline const char *rtn_type(char *buf, size_t len, unsigned int t) +--- a/net/ipv4/ipmr.c ++++ b/net/ipv4/ipmr.c +@@ -182,6 +182,7 @@ static int ipmr_rule_action(struct fib_r + case FR_ACT_UNREACHABLE: + return -ENETUNREACH; + case FR_ACT_PROHIBIT: ++ case FR_ACT_POLICY_FAILED: + return -EACCES; + case FR_ACT_BLACKHOLE: + default: +--- a/net/ipv6/fib6_rules.c ++++ b/net/ipv6/fib6_rules.c +@@ -73,6 +73,10 @@ static int fib6_rule_action(struct fib_r + err = -EACCES; + rt = net->ipv6.ip6_prohibit_entry; + goto discard_pkt; ++ case FR_ACT_POLICY_FAILED: ++ err = -EACCES; ++ rt = net->ipv6.ip6_policy_failed_entry; ++ goto discard_pkt; + } + + table = fib6_get_table(net, rule->table); +--- a/net/ipv6/ip6mr.c ++++ b/net/ipv6/ip6mr.c +@@ -167,6 +167,8 @@ static int ip6mr_rule_action(struct fib_ + return -ENETUNREACH; + case FR_ACT_PROHIBIT: + return -EACCES; ++ case FR_ACT_POLICY_FAILED: ++ return -EACCES; + case FR_ACT_BLACKHOLE: + default: + return -EINVAL; +--- a/net/ipv6/route.c ++++ b/net/ipv6/route.c +@@ -89,6 +89,8 @@ static int ip6_pkt_discard(struct sk_bu + static int ip6_pkt_discard_out(struct sock *sk, struct sk_buff *skb); + static int ip6_pkt_prohibit(struct sk_buff *skb); + static int ip6_pkt_prohibit_out(struct sock *sk, struct sk_buff *skb); ++static int ip6_pkt_policy_failed(struct sk_buff *skb); ++static int ip6_pkt_policy_failed_out(struct sock *sk, struct sk_buff *skb); + static void ip6_link_failure(struct sk_buff *skb); + static void ip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk, + struct sk_buff *skb, u32 mtu); +@@ -296,6 +298,21 @@ static const struct rt6_info ip6_prohibi + .rt6i_ref = ATOMIC_INIT(1), + }; + ++static const struct rt6_info ip6_policy_failed_entry_template = { ++ .dst = { ++ .__refcnt = ATOMIC_INIT(1), ++ .__use = 1, ++ .obsolete = DST_OBSOLETE_FORCE_CHK, ++ .error = -EACCES, ++ .input = ip6_pkt_policy_failed, ++ .output = ip6_pkt_policy_failed_out, ++ }, ++ .rt6i_flags = (RTF_REJECT | RTF_NONEXTHOP), ++ .rt6i_protocol = RTPROT_KERNEL, ++ .rt6i_metric = ~(u32) 0, ++ .rt6i_ref = ATOMIC_INIT(1), ++}; ++ + static const struct rt6_info ip6_blk_hole_entry_template = { + .dst = { + .__refcnt = ATOMIC_INIT(1), +@@ -1881,6 +1898,11 @@ int ip6_route_info_create(struct fib6_co + rt->dst.output = ip6_pkt_prohibit_out; + rt->dst.input = ip6_pkt_prohibit; + break; ++ case RTN_POLICY_FAILED: ++ rt->dst.error = -EACCES; ++ rt->dst.output = ip6_pkt_policy_failed_out; ++ rt->dst.input = ip6_pkt_policy_failed; ++ break; + case RTN_THROW: + case RTN_UNREACHABLE: + default: +@@ -2483,6 +2505,17 @@ static int ip6_pkt_prohibit_out(struct s + return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES); + } + ++static int ip6_pkt_policy_failed(struct sk_buff *skb) ++{ ++ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_INNOROUTES); ++} ++ ++static int ip6_pkt_policy_failed_out(struct sock *sk, struct sk_buff *skb) ++{ ++ skb->dev = skb_dst(skb)->dev; ++ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_OUTNOROUTES); ++} ++ + /* + * Allocate a dst for local (unicast / anycast) address. + */ +@@ -2723,7 +2756,8 @@ static int rtm_to_fib6_config(struct sk_ + if (rtm->rtm_type == RTN_UNREACHABLE || + rtm->rtm_type == RTN_BLACKHOLE || + rtm->rtm_type == RTN_PROHIBIT || +- rtm->rtm_type == RTN_THROW) ++ rtm->rtm_type == RTN_THROW || ++ rtm->rtm_type == RTN_POLICY_FAILED) + cfg->fc_flags |= RTF_REJECT; + + if (rtm->rtm_type == RTN_LOCAL) +@@ -3079,6 +3113,9 @@ static int rt6_fill_node(struct net *net + case -EACCES: + rtm->rtm_type = RTN_PROHIBIT; + break; ++ case -EPERM: ++ rtm->rtm_type = RTN_POLICY_FAILED; ++ break; + case -EAGAIN: + rtm->rtm_type = RTN_THROW; + break; +@@ -3347,6 +3384,8 @@ static int ip6_route_dev_notify(struct n + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + net->ipv6.ip6_prohibit_entry->dst.dev = dev; + net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev); ++ net->ipv6.ip6_policy_failed_entry->dst.dev = dev; ++ net->ipv6.ip6_policy_failed_entry->rt6i_idev = in6_dev_get(dev); + net->ipv6.ip6_blk_hole_entry->dst.dev = dev; + net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev); + #endif +@@ -3563,6 +3602,17 @@ static int __net_init ip6_route_net_init + net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops; + dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst, + ip6_template_metrics, true); ++ ++ net->ipv6.ip6_policy_failed_entry = ++ kmemdup(&ip6_policy_failed_entry_template, ++ sizeof(*net->ipv6.ip6_policy_failed_entry), GFP_KERNEL); ++ if (!net->ipv6.ip6_policy_failed_entry) ++ goto out_ip6_blk_hole_entry; ++ net->ipv6.ip6_policy_failed_entry->dst.path = ++ (struct dst_entry *)net->ipv6.ip6_policy_failed_entry; ++ net->ipv6.ip6_policy_failed_entry->dst.ops = &net->ipv6.ip6_dst_ops; ++ dst_init_metrics(&net->ipv6.ip6_policy_failed_entry->dst, ++ ip6_template_metrics, true); + #endif + + net->ipv6.sysctl.flush_delay = 0; +@@ -3581,6 +3631,8 @@ out: + return ret; + + #ifdef CONFIG_IPV6_MULTIPLE_TABLES ++out_ip6_blk_hole_entry: ++ kfree(net->ipv6.ip6_blk_hole_entry); + out_ip6_prohibit_entry: + kfree(net->ipv6.ip6_prohibit_entry); + out_ip6_null_entry: +@@ -3598,6 +3650,7 @@ static void __net_exit ip6_route_net_exi + #ifdef CONFIG_IPV6_MULTIPLE_TABLES + kfree(net->ipv6.ip6_prohibit_entry); + kfree(net->ipv6.ip6_blk_hole_entry); ++ kfree(net->ipv6.ip6_policy_failed_entry); + #endif + dst_entries_destroy(&net->ipv6.ip6_dst_ops); + } +@@ -3695,6 +3748,9 @@ int __init ip6_route_init(void) + init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); + init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev; + init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); ++ init_net.ipv6.ip6_policy_failed_entry->dst.dev = init_net.loopback_dev; ++ init_net.ipv6.ip6_policy_failed_entry->rt6i_idev = ++ in6_dev_get(init_net.loopback_dev); + #endif + ret = fib6_init(); + if (ret) diff --git a/target/linux/generic/patches-4.3/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch b/target/linux/generic/patches-4.3/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch new file mode 100644 index 0000000..dafb56c --- /dev/null +++ b/target/linux/generic/patches-4.3/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch @@ -0,0 +1,53 @@ +From 7749b481ce5d7e232b1f7da5e6b2c44816f51681 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 19 Jan 2014 20:45:51 +0100 +Subject: [PATCH 2/2] net: provide defines for _POLICY_FAILED until all code is + updated + +Upstream introduced ICMPV6_POLICY_FAIL for code 5 of destination +unreachable, conflicting with our name. + +Add appropriate defines to allow our code to build with the new +name until we have updated our local patches for older kernels +and userspace packages. + +Signed-off-by: Jonas Gorski +--- + include/uapi/linux/fib_rules.h | 2 ++ + include/uapi/linux/icmpv6.h | 2 ++ + include/uapi/linux/rtnetlink.h | 2 ++ + 3 files changed, 6 insertions(+) + +--- a/include/uapi/linux/fib_rules.h ++++ b/include/uapi/linux/fib_rules.h +@@ -71,6 +71,8 @@ enum { + __FR_ACT_MAX, + }; + ++#define FR_ACT_FAILED_POLICY FR_ACT_POLICY_FAILED ++ + #define FR_ACT_MAX (__FR_ACT_MAX - 1) + + #endif +--- a/include/uapi/linux/icmpv6.h ++++ b/include/uapi/linux/icmpv6.h +@@ -118,6 +118,8 @@ struct icmp6hdr { + #define ICMPV6_POLICY_FAIL 5 + #define ICMPV6_REJECT_ROUTE 6 + ++#define ICMPV6_FAILED_POLICY ICMPV6_POLICY_FAIL ++ + /* + * Codes for Time Exceeded + */ +--- a/include/uapi/linux/rtnetlink.h ++++ b/include/uapi/linux/rtnetlink.h +@@ -214,6 +214,8 @@ enum { + __RTN_MAX + }; + ++#define RTN_FAILED_POLICY RTN_POLICY_FAILED ++ + #define RTN_MAX (__RTN_MAX - 1) + + diff --git a/target/linux/generic/patches-4.3/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/patches-4.3/680-NET-skip-GRO-for-foreign-MAC-addresses.patch new file mode 100644 index 0000000..1d86e2f --- /dev/null +++ b/target/linux/generic/patches-4.3/680-NET-skip-GRO-for-foreign-MAC-addresses.patch @@ -0,0 +1,160 @@ +Subject: NET: skip GRO for foreign MAC addresses + +For network drivers using napi_gro_receive, packets are run through GRO, +even when the destination MAC address does not match, and they're supposed +to be delivered to another host behind a different bridge port. + +This can be very expensive, because for drivers without TSO or scatter- +gather, this can only be undone by copying the skb and checksumming it +again. + +To be able to track foreign MAC addresses in an inexpensive way, create +a mask of changed bits in MAC addresses of upper devices. This allows +handling VLANs and bridge devices with different addresses (as long as +they are not too different). + +Signed-off-by: Felix Fietkau + +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -4158,6 +4158,9 @@ static enum gro_result dev_gro_receive(s + enum gro_result ret; + int grow; + ++ if (skb->gro_skip) ++ goto normal; ++ + if (!(skb->dev->features & NETIF_F_GRO)) + goto normal; + +@@ -5309,6 +5312,48 @@ static void __netdev_adjacent_dev_unlink + &upper_dev->adj_list.lower); + } + ++static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr, ++ struct net_device *dev) ++{ ++ int i; ++ ++ for (i = 0; i < dev->addr_len; i++) ++ mask[i] |= addr[i] ^ dev->dev_addr[i]; ++} ++ ++static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev, ++ struct net_device *lower) ++{ ++ struct net_device *cur; ++ struct list_head *iter; ++ ++ netdev_for_each_upper_dev_rcu(dev, cur, iter) { ++ __netdev_addr_mask(mask, cur->dev_addr, lower); ++ __netdev_upper_mask(mask, cur, lower); ++ } ++} ++ ++static void __netdev_update_addr_mask(struct net_device *dev) ++{ ++ unsigned char mask[MAX_ADDR_LEN]; ++ struct net_device *cur; ++ struct list_head *iter; ++ ++ memset(mask, 0, sizeof(mask)); ++ __netdev_upper_mask(mask, dev, dev); ++ memcpy(dev->local_addr_mask, mask, dev->addr_len); ++ ++ netdev_for_each_lower_dev(dev, cur, iter) ++ __netdev_update_addr_mask(cur); ++} ++ ++static void netdev_update_addr_mask(struct net_device *dev) ++{ ++ rcu_read_lock(); ++ __netdev_update_addr_mask(dev); ++ rcu_read_unlock(); ++} ++ + static int __netdev_upper_dev_link(struct net_device *dev, + struct net_device *upper_dev, bool master, + void *private) +@@ -5374,6 +5419,7 @@ static int __netdev_upper_dev_link(struc + goto rollback_lower_mesh; + } + ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, dev, + &changeupper_info.info); + return 0; +@@ -5497,6 +5543,7 @@ void netdev_upper_dev_unlink(struct net_ + list_for_each_entry(i, &upper_dev->all_adj_list.upper, list) + __netdev_adjacent_dev_unlink(dev, i->dev); + ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, dev, + &changeupper_info.info); + } +@@ -6037,6 +6084,7 @@ int dev_set_mac_address(struct net_devic + if (err) + return err; + dev->addr_assign_type = NET_ADDR_SET; ++ netdev_update_addr_mask(dev); + call_netdevice_notifiers(NETDEV_CHANGEADDR, dev); + add_device_randomness(dev->dev_addr, dev->addr_len); + return 0; +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1623,6 +1623,8 @@ struct net_device { + struct netdev_hw_addr_list mc; + struct netdev_hw_addr_list dev_addrs; + ++ unsigned char local_addr_mask[MAX_ADDR_LEN]; ++ + #ifdef CONFIG_SYSFS + struct kset *queues_kset; + #endif +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -632,7 +632,8 @@ struct sk_buff { + __u8 ipvs_property:1; + __u8 inner_protocol_type:1; + __u8 remcsum_offload:1; +- /* 3 or 5 bit hole */ ++ __u8 gro_skip:1; ++ /* 2 or 4 bit hole */ + + #ifdef CONFIG_NET_SCHED + __u16 tc_index; /* traffic control index */ +--- a/net/ethernet/eth.c ++++ b/net/ethernet/eth.c +@@ -140,6 +140,18 @@ u32 eth_get_headlen(void *data, unsigned + } + EXPORT_SYMBOL(eth_get_headlen); + ++static inline bool ++eth_check_local_mask(const void *addr1, const void *addr2, const void *mask) ++{ ++ const u16 *a1 = addr1; ++ const u16 *a2 = addr2; ++ const u16 *m = mask; ++ ++ return (((a1[0] ^ a2[0]) & ~m[0]) | ++ ((a1[1] ^ a2[1]) & ~m[1]) | ++ ((a1[2] ^ a2[2]) & ~m[2])); ++} ++ + /** + * eth_type_trans - determine the packet's protocol ID. + * @skb: received socket data +@@ -168,8 +180,12 @@ __be16 eth_type_trans(struct sk_buff *sk + skb->pkt_type = PACKET_MULTICAST; + } + else if (unlikely(!ether_addr_equal_64bits(eth->h_dest, +- dev->dev_addr))) ++ dev->dev_addr))) { + skb->pkt_type = PACKET_OTHERHOST; ++ if (eth_check_local_mask(eth->h_dest, dev->dev_addr, ++ dev->local_addr_mask)) ++ skb->gro_skip = 1; ++ } + + /* + * Some variants of DSA tagging don't have an ethertype field diff --git a/target/linux/generic/patches-4.3/681-NET-add-of_get_mac_address_mtd.patch b/target/linux/generic/patches-4.3/681-NET-add-of_get_mac_address_mtd.patch new file mode 100644 index 0000000..688cf6e --- /dev/null +++ b/target/linux/generic/patches-4.3/681-NET-add-of_get_mac_address_mtd.patch @@ -0,0 +1,88 @@ +From: John Crispin +Date: Sun, 27 Jul 2014 09:40:01 +0100 +Subject: NET: add of_get_mac_address_mtd() + +Many embedded devices have information such as mac addresses stored inside mtd +devices. This patch allows us to add a property inside a node describing a +network interface. The new property points at a mtd partition with an offset +where the mac address can be found. + +Signed-off-by: John Crispin +--- + drivers/of/of_net.c | 37 +++++++++++++++++++++++++++++++++++++ + include/linux/of_net.h | 1 + + 2 files changed, 38 insertions(+) + +--- a/drivers/of/of_net.c ++++ b/drivers/of/of_net.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + /** + * of_get_phy_mode - Get phy mode for given device_node +@@ -80,3 +81,45 @@ const void *of_get_mac_address(struct de + return of_get_mac_addr(np, "address"); + } + EXPORT_SYMBOL(of_get_mac_address); ++ ++#ifdef CONFIG_MTD ++int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac) ++{ ++ struct device_node *mtd_np = NULL; ++ size_t retlen; ++ int size, ret; ++ struct mtd_info *mtd; ++ const char *part; ++ const __be32 *list; ++ phandle phandle; ++ u32 mac_inc = 0; ++ ++ list = of_get_property(np, "mtd-mac-address", &size); ++ if (!list || (size != (2 * sizeof(*list)))) ++ return -ENOENT; ++ ++ phandle = be32_to_cpup(list++); ++ if (phandle) ++ mtd_np = of_find_node_by_phandle(phandle); ++ ++ if (!mtd_np) ++ return -ENOENT; ++ ++ part = of_get_property(mtd_np, "label", NULL); ++ if (!part) ++ part = mtd_np->name; ++ ++ mtd = get_mtd_device_nm(part); ++ if (IS_ERR(mtd)) ++ return PTR_ERR(mtd); ++ ++ ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, mac); ++ put_mtd_device(mtd); ++ ++ if (!of_property_read_u32(np, "mtd-mac-address-increment", &mac_inc)) ++ mac[5] += mac_inc; ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(of_get_mac_address_mtd); ++#endif +--- a/include/linux/of_net.h ++++ b/include/linux/of_net.h +@@ -13,6 +13,14 @@ + struct net_device; + extern int of_get_phy_mode(struct device_node *np); + extern const void *of_get_mac_address(struct device_node *np); ++#ifdef CONFIG_MTD ++extern int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac); ++#else ++static inline int of_get_mac_address_mtd(struct device_node *np, unsigned char *mac) ++{ ++ return -ENOENT; ++} ++#endif + extern struct net_device *of_find_net_device_by_node(struct device_node *np); + #else + static inline int of_get_phy_mode(struct device_node *np) diff --git a/target/linux/generic/patches-4.3/700-swconfig.patch b/target/linux/generic/patches-4.3/700-swconfig.patch new file mode 100644 index 0000000..2b4c20e --- /dev/null +++ b/target/linux/generic/patches-4.3/700-swconfig.patch @@ -0,0 +1,39 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -12,6 +12,16 @@ menuconfig PHYLIB + + if PHYLIB + ++config SWCONFIG ++ tristate "Switch configuration API" ++ ---help--- ++ Switch configuration API using netlink. This allows ++ you to configure the VLAN features of certain switches. ++ ++config SWCONFIG_LEDS ++ bool "Switch LED trigger support" ++ depends on (SWCONFIG && LEDS_TRIGGERS) ++ + comment "MII PHY device drivers" + + config AQUANTIA_PHY +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -3,6 +3,7 @@ + libphy-objs := phy.o phy_device.o mdio_bus.o + + obj-$(CONFIG_PHYLIB) += libphy.o ++obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o + obj-$(CONFIG_MARVELL_PHY) += marvell.o + obj-$(CONFIG_DAVICOM_PHY) += davicom.o +--- a/include/uapi/linux/Kbuild ++++ b/include/uapi/linux/Kbuild +@@ -385,6 +385,7 @@ header-y += stddef.h + header-y += string.h + header-y += suspend_ioctls.h + header-y += swab.h ++header-y += switch.h + header-y += synclink.h + header-y += sysctl.h + header-y += sysinfo.h diff --git a/target/linux/generic/patches-4.3/701-phy_extension.patch b/target/linux/generic/patches-4.3/701-phy_extension.patch new file mode 100644 index 0000000..cc3ccd7 --- /dev/null +++ b/target/linux/generic/patches-4.3/701-phy_extension.patch @@ -0,0 +1,63 @@ +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -385,6 +385,50 @@ int phy_ethtool_gset(struct phy_device * + } + EXPORT_SYMBOL(phy_ethtool_gset); + ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) ++{ ++ u32 cmd; ++ int tmp; ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ++ if (get_user(cmd, (u32 *) useraddr)) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case ETHTOOL_GSET: ++ phy_ethtool_gset(phydev, &ecmd); ++ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) ++ return -EFAULT; ++ return 0; ++ ++ case ETHTOOL_SSET: ++ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) ++ return -EFAULT; ++ return phy_ethtool_sset(phydev, &ecmd); ++ ++ case ETHTOOL_NWAY_RST: ++ /* if autoneg is off, it's an error */ ++ tmp = phy_read(phydev, MII_BMCR); ++ if (tmp & BMCR_ANENABLE) { ++ tmp |= (BMCR_ANRESTART); ++ phy_write(phydev, MII_BMCR, tmp); ++ return 0; ++ } ++ return -EINVAL; ++ ++ case ETHTOOL_GLINK: ++ edata.data = (phy_read(phydev, ++ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++ } ++ ++ return -EOPNOTSUPP; ++} ++EXPORT_SYMBOL(phy_ethtool_ioctl); ++ + /** + * phy_mii_ioctl - generic PHY MII ioctl interface + * @phydev: the phy_device struct +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -794,6 +794,7 @@ void phy_start_machine(struct phy_device + void phy_stop_machine(struct phy_device *phydev); + int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); + int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); + int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd); + int phy_start_interrupts(struct phy_device *phydev); + void phy_print_status(struct phy_device *phydev); diff --git a/target/linux/generic/patches-4.3/702-phy_add_aneg_done_function.patch b/target/linux/generic/patches-4.3/702-phy_add_aneg_done_function.patch new file mode 100644 index 0000000..1b5ff79 --- /dev/null +++ b/target/linux/generic/patches-4.3/702-phy_add_aneg_done_function.patch @@ -0,0 +1,27 @@ +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -499,6 +499,12 @@ struct phy_driver { + /* Determines the negotiated speed and duplex */ + int (*read_status)(struct phy_device *phydev); + ++ /* ++ * Update the value in phydev->link to reflect the ++ * current link value ++ */ ++ int (*update_link)(struct phy_device *phydev); ++ + /* Clears any pending interrupts */ + int (*ack_interrupt)(struct phy_device *phydev); + +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -971,6 +971,9 @@ int genphy_update_link(struct phy_device + { + int status; + ++ if (phydev->drv->update_link) ++ return phydev->drv->update_link(phydev); ++ + /* Do a fake read */ + status = phy_read(phydev, MII_BMSR); + if (status < 0) diff --git a/target/linux/generic/patches-4.3/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/patches-4.3/703-phy-add-detach-callback-to-struct-phy_driver.patch new file mode 100644 index 0000000..de30453 --- /dev/null +++ b/target/linux/generic/patches-4.3/703-phy-add-detach-callback-to-struct-phy_driver.patch @@ -0,0 +1,27 @@ +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -710,6 +710,9 @@ void phy_detach(struct phy_device *phyde + struct mii_bus *bus; + int i; + ++ if (phydev->drv && phydev->drv->detach) ++ phydev->drv->detach(phydev); ++ + phydev->attached_dev->phydev = NULL; + phydev->attached_dev = NULL; + phy_suspend(phydev); +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -517,6 +517,12 @@ struct phy_driver { + */ + int (*did_interrupt)(struct phy_device *phydev); + ++ /* ++ * Called before an ethernet device is detached ++ * from the PHY. ++ */ ++ void (*detach)(struct phy_device *phydev); ++ + /* Clears up any memory if needed */ + void (*remove)(struct phy_device *phydev); + diff --git a/target/linux/generic/patches-4.3/704-phy-no-genphy-soft-reset.patch b/target/linux/generic/patches-4.3/704-phy-no-genphy-soft-reset.patch new file mode 100644 index 0000000..3f32e48 --- /dev/null +++ b/target/linux/generic/patches-4.3/704-phy-no-genphy-soft-reset.patch @@ -0,0 +1,29 @@ +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -1189,7 +1189,7 @@ int genphy_config_init(struct phy_device + return 0; + } + +-static int gen10g_soft_reset(struct phy_device *phydev) ++static int no_soft_reset(struct phy_device *phydev) + { + /* Do nothing for now */ + return 0; +@@ -1403,7 +1403,7 @@ static struct phy_driver genphy_driver[] + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic PHY", +- .soft_reset = genphy_soft_reset, ++ .soft_reset = no_soft_reset, + .config_init = genphy_config_init, + .features = PHY_GBIT_FEATURES | SUPPORTED_MII | + SUPPORTED_AUI | SUPPORTED_FIBRE | +@@ -1418,7 +1418,7 @@ static struct phy_driver genphy_driver[] + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic 10G PHY", +- .soft_reset = gen10g_soft_reset, ++ .soft_reset = no_soft_reset, + .config_init = gen10g_config_init, + .features = 0, + .config_aneg = gen10g_config_aneg, diff --git a/target/linux/generic/patches-4.3/710-phy-add-mdio_register_board_info.patch b/target/linux/generic/patches-4.3/710-phy-add-mdio_register_board_info.patch new file mode 100644 index 0000000..d686f2b --- /dev/null +++ b/target/linux/generic/patches-4.3/710-phy-add-mdio_register_board_info.patch @@ -0,0 +1,193 @@ +--- a/drivers/net/phy/mdio_bus.c ++++ b/drivers/net/phy/mdio_bus.c +@@ -38,6 +38,8 @@ + + #include + ++#include "mdio-boardinfo.h" ++ + /** + * mdiobus_alloc_size - allocate a mii_bus structure + * @size: extra amount of memory to allocate for private storage. +@@ -346,9 +348,21 @@ void mdiobus_free(struct mii_bus *bus) + } + EXPORT_SYMBOL(mdiobus_free); + ++static void mdiobus_setup_phydev_from_boardinfo(struct mii_bus *bus, ++ struct phy_device *phydev, ++ struct mdio_board_info *bi) ++{ ++ if (strcmp(bus->id, bi->bus_id) || ++ bi->phy_addr != phydev->addr) ++ return; ++ ++ phydev->dev.platform_data = (void *) bi->platform_data; ++} ++ + struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr) + { + struct phy_device *phydev; ++ struct mdio_board_entry *be; + int err; + + phydev = get_phy_device(bus, addr, false); +@@ -361,6 +375,12 @@ struct phy_device *mdiobus_scan(struct m + */ + of_mdiobus_link_phydev(bus, phydev); + ++ mutex_lock(&__mdio_board_lock); ++ list_for_each_entry(be, &__mdio_board_list, list) ++ mdiobus_setup_phydev_from_boardinfo(bus, phydev, ++ &be->board_info); ++ mutex_unlock(&__mdio_board_lock); ++ + err = phy_device_register(phydev); + if (err) { + phy_device_free(phydev); +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -832,6 +832,23 @@ void mdio_bus_exit(void); + + extern struct bus_type mdio_bus_type; + ++struct mdio_board_info { ++ const char *bus_id; ++ int phy_addr; ++ ++ const void *platform_data; ++}; ++ ++#ifdef CONFIG_MDIO_BOARDINFO ++int mdiobus_register_board_info(const struct mdio_board_info *info, unsigned n); ++#else ++static inline int ++mdiobus_register_board_info(const struct mdio_board_info *info, unsigned n) ++{ ++ return 0; ++} ++#endif ++ + /** + * module_phy_driver() - Helper macro for registering PHY drivers + * @__phy_drivers: array of PHY drivers to register +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -12,6 +12,10 @@ menuconfig PHYLIB + + if PHYLIB + ++config MDIO_BOARDINFO ++ bool ++ default y ++ + config SWCONFIG + tristate "Switch configuration API" + ---help--- +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -2,6 +2,8 @@ + + libphy-objs := phy.o phy_device.o mdio_bus.o + ++obj-$(CONFIG_MDIO_BOARDINFO) += mdio-boardinfo.o ++ + obj-$(CONFIG_PHYLIB) += libphy.o + obj-$(CONFIG_SWCONFIG) += swconfig.o + obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o +--- /dev/null ++++ b/drivers/net/phy/mdio-boardinfo.c +@@ -0,0 +1,58 @@ ++/* ++ * mdio-boardinfo.c - collect pre-declarations of PHY devices ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdio-boardinfo.h" ++ ++/* ++ * These symbols are exported ONLY FOR the mdio_bus component. ++ * No other users will be supported. ++ */ ++ ++LIST_HEAD(__mdio_board_list); ++EXPORT_SYMBOL_GPL(__mdio_board_list); ++ ++DEFINE_MUTEX(__mdio_board_lock); ++EXPORT_SYMBOL_GPL(__mdio_board_lock); ++ ++/** ++ * mdio_register_board_info - register PHY devices for a given board ++ * @info: array of chip descriptors ++ * @n: how many descriptors are provided ++ * Context: can sleep ++ * ++ * The board info passed can safely be __initdata ... but be careful of ++ * any embedded pointers (platform_data, etc), they're copied as-is. ++ */ ++int __init ++mdiobus_register_board_info(struct mdio_board_info const *info, unsigned n) ++{ ++ struct mdio_board_entry *be; ++ int i; ++ ++ be = kzalloc(n * sizeof(*be), GFP_KERNEL); ++ if (!be) ++ return -ENOMEM; ++ ++ for (i = 0; i < n; i++, be++, info++) { ++ memcpy(&be->board_info, info, sizeof(*info)); ++ mutex_lock(&__mdio_board_lock); ++ list_add_tail(&be->list, &__mdio_board_list); ++ mutex_unlock(&__mdio_board_lock); ++ } ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/net/phy/mdio-boardinfo.h +@@ -0,0 +1,22 @@ ++/* ++ * mdio-boardinfo.h - boardinfo interface internal to the mdio_bus component ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++ ++struct mdio_board_entry { ++ struct list_head list; ++ struct mdio_board_info board_info; ++}; ++ ++/* __mdio_board_lock protects __mdio_board_list ++ * only mdio_bus components are allowed to use these symbols. ++ */ ++extern struct mutex __mdio_board_lock; ++extern struct list_head __mdio_board_list; +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -16,7 +16,7 @@ obj-$(CONFIG_MII) += mii.o + obj-$(CONFIG_MDIO) += mdio.o + obj-$(CONFIG_NET) += Space.o loopback.o + obj-$(CONFIG_NETCONSOLE) += netconsole.o +-obj-$(CONFIG_PHYLIB) += phy/ ++obj-y += phy/ + obj-$(CONFIG_RIONET) += rionet.o + obj-$(CONFIG_NET_TEAM) += team/ + obj-$(CONFIG_TUN) += tun.o diff --git a/target/linux/generic/patches-4.3/720-phy_adm6996.patch b/target/linux/generic/patches-4.3/720-phy_adm6996.patch new file mode 100644 index 0000000..1c32b76 --- /dev/null +++ b/target/linux/generic/patches-4.3/720-phy_adm6996.patch @@ -0,0 +1,26 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -146,6 +146,13 @@ config MICROCHIP_PHY + help + Supports the LAN88XX PHYs. + ++config ADM6996_PHY ++ tristate "Driver for ADM6996 switches" ++ select SWCONFIG ++ ---help--- ++ Currently supports the ADM6996FC and ADM6996M switches. ++ Support for FC is very limited. ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o + obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o ++obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.3/721-phy_packets.patch b/target/linux/generic/patches-4.3/721-phy_packets.patch new file mode 100644 index 0000000..e83eadb --- /dev/null +++ b/target/linux/generic/patches-4.3/721-phy_packets.patch @@ -0,0 +1,161 @@ +--- a/include/linux/netdevice.h ++++ b/include/linux/netdevice.h +@@ -1286,6 +1286,7 @@ enum netdev_priv_flags { + IFF_VRF_MASTER = 1<<20, + IFF_NO_QUEUE = 1<<21, + IFF_OPENVSWITCH = 1<<22, ++ IFF_NO_IP_ALIGN = 1<<23, + }; + + #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN +@@ -1311,6 +1312,7 @@ enum netdev_priv_flags { + #define IFF_VRF_MASTER IFF_VRF_MASTER + #define IFF_NO_QUEUE IFF_NO_QUEUE + #define IFF_OPENVSWITCH IFF_OPENVSWITCH ++#define IFF_NO_IP_ALIGN IFF_NO_IP_ALIGN + + /** + * struct net_device - The DEVICE structure. +@@ -1588,6 +1590,11 @@ struct net_device { + const struct switchdev_ops *switchdev_ops; + #endif + ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ void (*eth_mangle_rx)(struct net_device *dev, struct sk_buff *skb); ++ struct sk_buff *(*eth_mangle_tx)(struct net_device *dev, struct sk_buff *skb); ++#endif ++ + const struct header_ops *header_ops; + + unsigned int flags; +@@ -1655,6 +1662,10 @@ struct net_device { + struct mpls_dev __rcu *mpls_ptr; + #endif + ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ void *phy_ptr; /* PHY device specific data */ ++#endif ++ + /* + * Cache lines mostly used on receive path (including eth_type_trans()) + */ +--- a/include/linux/skbuff.h ++++ b/include/linux/skbuff.h +@@ -2176,6 +2176,10 @@ static inline int pskb_trim(struct sk_bu + return (len < skb->len) ? __pskb_trim(skb, len) : 0; + } + ++extern struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, ++ unsigned int length, gfp_t gfp); ++ ++ + /** + * pskb_trim_unique - remove end from a paged unique (not cloned) buffer + * @skb: buffer to alter +@@ -2298,16 +2302,6 @@ static inline struct sk_buff *dev_alloc_ + } + + +-static inline struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, +- unsigned int length, gfp_t gfp) +-{ +- struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); +- +- if (NET_IP_ALIGN && skb) +- skb_reserve(skb, NET_IP_ALIGN); +- return skb; +-} +- + static inline struct sk_buff *netdev_alloc_skb_ip_align(struct net_device *dev, + unsigned int length) + { +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -25,6 +25,12 @@ menuconfig NET + + if NET + ++config ETHERNET_PACKET_MANGLE ++ bool ++ help ++ This option can be selected by phy drivers that need to mangle ++ packets going in or out of an ethernet device. ++ + config WANT_COMPAT_NETLINK_MESSAGES + bool + help +--- a/net/core/dev.c ++++ b/net/core/dev.c +@@ -2678,10 +2678,20 @@ static int xmit_one(struct sk_buff *skb, + if (!list_empty(&ptype_all) || !list_empty(&dev->ptype_all)) + dev_queue_xmit_nit(skb, dev); + +- len = skb->len; +- trace_net_dev_start_xmit(skb, dev); +- rc = netdev_start_xmit(skb, dev, txq, more); +- trace_net_dev_xmit(skb, rc, dev, len); ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (!dev->eth_mangle_tx || ++ (skb = dev->eth_mangle_tx(dev, skb)) != NULL) ++#else ++ if (1) ++#endif ++ { ++ len = skb->len; ++ trace_net_dev_start_xmit(skb, dev); ++ rc = netdev_start_xmit(skb, dev, txq, more); ++ trace_net_dev_xmit(skb, rc, dev, len); ++ } else { ++ rc = NETDEV_TX_OK; ++ } + + return rc; + } +--- a/net/core/skbuff.c ++++ b/net/core/skbuff.c +@@ -63,6 +63,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -518,6 +519,22 @@ skb_fail: + } + EXPORT_SYMBOL(__napi_alloc_skb); + ++struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, ++ unsigned int length, gfp_t gfp) ++{ ++ struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); ++ ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (dev && (dev->priv_flags & IFF_NO_IP_ALIGN)) ++ return skb; ++#endif ++ ++ if (NET_IP_ALIGN && skb) ++ skb_reserve(skb, NET_IP_ALIGN); ++ return skb; ++} ++EXPORT_SYMBOL(__netdev_alloc_skb_ip_align); ++ + void skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page, int off, + int size, unsigned int truesize) + { +--- a/net/ethernet/eth.c ++++ b/net/ethernet/eth.c +@@ -168,6 +168,12 @@ __be16 eth_type_trans(struct sk_buff *sk + const struct ethhdr *eth; + + skb->dev = dev; ++ ++#ifdef CONFIG_ETHERNET_PACKET_MANGLE ++ if (dev->eth_mangle_rx) ++ dev->eth_mangle_rx(dev, skb); ++#endif ++ + skb_reset_mac_header(skb); + + eth = (struct ethhdr *)skb->data; diff --git a/target/linux/generic/patches-4.3/722-phy_mvswitch.patch b/target/linux/generic/patches-4.3/722-phy_mvswitch.patch new file mode 100644 index 0000000..2d366bf --- /dev/null +++ b/target/linux/generic/patches-4.3/722-phy_mvswitch.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -153,6 +153,10 @@ config ADM6996_PHY + Currently supports the ADM6996FC and ADM6996M switches. + Support for FC is very limited. + ++config MVSWITCH_PHY ++ tristate "Driver for Marvell 88E6060 switches" ++ select ETHERNET_PACKET_MANGLE ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -21,6 +21,7 @@ obj-$(CONFIG_BCM7XXX_PHY) += bcm7xxx.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o ++obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.3/723-phy_ip175c.patch b/target/linux/generic/patches-4.3/723-phy_ip175c.patch new file mode 100644 index 0000000..e5c9bce --- /dev/null +++ b/target/linux/generic/patches-4.3/723-phy_ip175c.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -157,6 +157,10 @@ config MVSWITCH_PHY + tristate "Driver for Marvell 88E6060 switches" + select ETHERNET_PACKET_MANGLE + ++config IP17XX_PHY ++ tristate "Driver for IC+ IP17xx switches" ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o ++obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o diff --git a/target/linux/generic/patches-4.3/724-phy_ar8216.patch b/target/linux/generic/patches-4.3/724-phy_ar8216.patch new file mode 100644 index 0000000..de94037 --- /dev/null +++ b/target/linux/generic/patches-4.3/724-phy_ar8216.patch @@ -0,0 +1,24 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -161,6 +161,11 @@ config IP17XX_PHY + tristate "Driver for IC+ IP17xx switches" + select SWCONFIG + ++config AR8216_PHY ++ tristate "Driver for Atheros AR8216 switches" ++ select ETHERNET_PACKET_MANGLE ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o ++obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.3/725-phy_rtl8306.patch b/target/linux/generic/patches-4.3/725-phy_rtl8306.patch new file mode 100644 index 0000000..803e770 --- /dev/null +++ b/target/linux/generic/patches-4.3/725-phy_rtl8306.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -166,6 +166,10 @@ config AR8216_PHY + select ETHERNET_PACKET_MANGLE + select SWCONFIG + ++config RTL8306_PHY ++ tristate "Driver for Realtek RTL8306S switches" ++ select SWCONFIG ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -25,6 +25,7 @@ obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o ++obj-$(CONFIG_RTL8306_PHY) += rtl8306.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.3/726-phy_rtl8366.patch b/target/linux/generic/patches-4.3/726-phy_rtl8366.patch new file mode 100644 index 0000000..bba83b3 --- /dev/null +++ b/target/linux/generic/patches-4.3/726-phy_rtl8366.patch @@ -0,0 +1,46 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -261,6 +261,31 @@ config MDIO_BCM_UNIMAC + This hardware can be found in the Broadcom GENET Ethernet MAC + controllers as well as some Broadcom Ethernet switches such as the + Starfighter 2 switches. ++ ++config RTL8366_SMI ++ tristate "Driver for the RTL8366 SMI interface" ++ depends on GPIOLIB ++ ---help--- ++ This module implements the SMI interface protocol which is used ++ by some RTL8366 ethernet switch devices via the generic GPIO API. ++ ++if RTL8366_SMI ++ ++config RTL8366_SMI_DEBUG_FS ++ bool "RTL8366 SMI interface debugfs support" ++ depends on DEBUG_FS ++ default n ++ ++config RTL8366S_PHY ++ tristate "Driver for the Realtek RTL8366S switch" ++ select SWCONFIG ++ ++config RTL8366RB_PHY ++ tristate "Driver for the Realtek RTL8366RB switch" ++ select SWCONFIG ++ ++endif # RTL8366_SMI ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -26,6 +26,9 @@ obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o + obj-$(CONFIG_RTL8306_PHY) += rtl8306.o ++obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o ++obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o ++obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.3/727-phy-rtl8367.patch b/target/linux/generic/patches-4.3/727-phy-rtl8367.patch new file mode 100644 index 0000000..a10856f --- /dev/null +++ b/target/linux/generic/patches-4.3/727-phy-rtl8367.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -284,6 +284,10 @@ config RTL8366RB_PHY + tristate "Driver for the Realtek RTL8366RB switch" + select SWCONFIG + ++config RTL8367_PHY ++ tristate "Driver for the Realtek RTL8367R/M switches" ++ select SWCONFIG ++ + endif # RTL8366_SMI + + endif # PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_RTL8306_PHY) += rtl8306.o + obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o + obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o + obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o ++obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.3/728-phy-rtl8367b.patch b/target/linux/generic/patches-4.3/728-phy-rtl8367b.patch new file mode 100644 index 0000000..881be7d --- /dev/null +++ b/target/linux/generic/patches-4.3/728-phy-rtl8367b.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -288,6 +288,10 @@ config RTL8367_PHY + tristate "Driver for the Realtek RTL8367R/M switches" + select SWCONFIG + ++config RTL8367B_PHY ++ tristate "Driver fot the Realtek RTL8367R-VB switch" ++ select SWCONFIG ++ + endif # RTL8366_SMI + + endif # PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -30,6 +30,7 @@ obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi + obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o + obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o ++obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/target/linux/generic/patches-4.3/729-phy-tantos.patch b/target/linux/generic/patches-4.3/729-phy-tantos.patch new file mode 100644 index 0000000..19ea8b0 --- /dev/null +++ b/target/linux/generic/patches-4.3/729-phy-tantos.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -299,3 +299,8 @@ endif # PHYLIB + config MICREL_KS8995MA + tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch" + depends on SPI ++ ++config PSB6970_PHY ++ tristate "Lantiq XWAY Tantos (PSB6970) Ethernet switch" ++ select SWCONFIG ++ select ETHERNET_PACKET_MANGLE +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o ++obj-$(CONFIG_PSB6970_PHY) += psb6970.o + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/generic/patches-4.3/730-phy_b53.patch b/target/linux/generic/patches-4.3/730-phy_b53.patch new file mode 100644 index 0000000..648919f --- /dev/null +++ b/target/linux/generic/patches-4.3/730-phy_b53.patch @@ -0,0 +1,21 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -294,6 +294,8 @@ config RTL8367B_PHY + + endif # RTL8366_SMI + ++source "drivers/net/phy/b53/Kconfig" ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -33,6 +33,7 @@ obj-$(CONFIG_RTL8367_PHY) += rtl8367.o + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o + obj-$(CONFIG_PSB6970_PHY) += psb6970.o ++obj-$(CONFIG_B53) += b53/ + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o + obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o + obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o diff --git a/target/linux/generic/patches-4.3/731-phy_mvswitch_3.10_compilation.patch b/target/linux/generic/patches-4.3/731-phy_mvswitch_3.10_compilation.patch new file mode 100644 index 0000000..2053bd2 --- /dev/null +++ b/target/linux/generic/patches-4.3/731-phy_mvswitch_3.10_compilation.patch @@ -0,0 +1,35 @@ +From e6a5abb9a02be0bceb4782d9f736bfb4ae217505 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sat, 21 Sep 2013 13:56:51 +0200 +Subject: [PATCH] phy: mvswitch: fix 3.10 compilation + +Update to API changes in 3.10. + +Signed-off-by: Jonas Gorsi +--- + target/linux/generic/files/drivers/net/phy/mvswitch.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/mvswitch.c ++++ b/drivers/net/phy/mvswitch.c +@@ -173,7 +173,7 @@ mvswitch_mangle_rx(struct net_device *de + if (vlan == -1) + return; + +- __vlan_hwaccel_put_tag(skb, vlan); ++ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan); + } + + +@@ -307,9 +307,9 @@ mvswitch_config_init(struct phy_device * + + #ifdef HEADER_MODE + dev->priv_flags |= IFF_NO_IP_ALIGN; +- dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX; ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; + #else +- dev->features |= NETIF_F_HW_VLAN_RX; ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX; + #endif + + return 0; diff --git a/target/linux/generic/patches-4.3/732-phy-ar8216-led-support.patch b/target/linux/generic/patches-4.3/732-phy-ar8216-led-support.patch new file mode 100644 index 0000000..7567f66 --- /dev/null +++ b/target/linux/generic/patches-4.3/732-phy-ar8216-led-support.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -166,6 +166,10 @@ config AR8216_PHY + select ETHERNET_PACKET_MANGLE + select SWCONFIG + ++config AR8216_PHY_LEDS ++ bool "Atheros AR8216 switch LED support" ++ depends on (AR8216_PHY && LEDS_CLASS) ++ + config RTL8306_PHY + tristate "Driver for Realtek RTL8306S switches" + select SWCONFIG diff --git a/target/linux/generic/patches-4.3/733-phy_mvsw61xx.patch b/target/linux/generic/patches-4.3/733-phy_mvsw61xx.patch new file mode 100644 index 0000000..9f7274c --- /dev/null +++ b/target/linux/generic/patches-4.3/733-phy_mvsw61xx.patch @@ -0,0 +1,23 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -157,6 +157,10 @@ config MVSWITCH_PHY + tristate "Driver for Marvell 88E6060 switches" + select ETHERNET_PACKET_MANGLE + ++config MVSW61XX_PHY ++ tristate "Driver for Marvell 88E6171/6172 switches" ++ select SWCONFIG ++ + config IP17XX_PHY + tristate "Driver for IC+ IP17xx switches" + select SWCONFIG +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_ICPLUS_PHY) += icplus.o + obj-$(CONFIG_ADM6996_PHY) += adm6996.o + obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o ++obj-$(CONFIG_MVSW61XX_PHY) += mvsw61xx.o + obj-$(CONFIG_IP17XX_PHY) += ip17xx.o + obj-$(CONFIG_REALTEK_PHY) += realtek.o + obj-$(CONFIG_AR8216_PHY) += ar8216.o ar8327.o diff --git a/target/linux/generic/patches-4.3/750-hostap_txpower.patch b/target/linux/generic/patches-4.3/750-hostap_txpower.patch new file mode 100644 index 0000000..768c80f --- /dev/null +++ b/target/linux/generic/patches-4.3/750-hostap_txpower.patch @@ -0,0 +1,154 @@ +--- a/drivers/net/wireless/hostap/hostap_ap.c ++++ b/drivers/net/wireless/hostap/hostap_ap.c +@@ -2403,13 +2403,13 @@ int prism2_ap_get_sta_qual(local_info_t + addr[count].sa_family = ARPHRD_ETHER; + memcpy(addr[count].sa_data, sta->addr, ETH_ALEN); + if (sta->last_rx_silence == 0) +- qual[count].qual = sta->last_rx_signal < 27 ? +- 0 : (sta->last_rx_signal - 27) * 92 / 127; ++ qual[count].qual = (sta->last_rx_signal - 156) == 0 ? ++ 0 : (sta->last_rx_signal - 156) * 92 / 64; + else +- qual[count].qual = sta->last_rx_signal - +- sta->last_rx_silence - 35; +- qual[count].level = HFA384X_LEVEL_TO_dBm(sta->last_rx_signal); +- qual[count].noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); ++ qual[count].qual = (sta->last_rx_signal - ++ sta->last_rx_silence) * 92 / 64; ++ qual[count].level = sta->last_rx_signal; ++ qual[count].noise = sta->last_rx_silence; + qual[count].updated = sta->last_rx_updated; + + sta->last_rx_updated = IW_QUAL_DBM; +@@ -2475,13 +2475,13 @@ int prism2_ap_translate_scan(struct net_ + memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVQUAL; + if (sta->last_rx_silence == 0) +- iwe.u.qual.qual = sta->last_rx_signal < 27 ? +- 0 : (sta->last_rx_signal - 27) * 92 / 127; ++ iwe.u.qual.qual = (sta->last_rx_signal -156) == 0 ? ++ 0 : (sta->last_rx_signal - 156) * 92 / 64; + else +- iwe.u.qual.qual = sta->last_rx_signal - +- sta->last_rx_silence - 35; +- iwe.u.qual.level = HFA384X_LEVEL_TO_dBm(sta->last_rx_signal); +- iwe.u.qual.noise = HFA384X_LEVEL_TO_dBm(sta->last_rx_silence); ++ iwe.u.qual.qual = (sta->last_rx_signal - ++ sta->last_rx_silence) * 92 / 64; ++ iwe.u.qual.level = sta->last_rx_signal; ++ iwe.u.qual.noise = sta->last_rx_silence; + iwe.u.qual.updated = sta->last_rx_updated; + iwe.len = IW_EV_QUAL_LEN; + current_ev = iwe_stream_add_event(info, current_ev, end_buf, +--- a/drivers/net/wireless/hostap/hostap_config.h ++++ b/drivers/net/wireless/hostap/hostap_config.h +@@ -45,4 +45,9 @@ + */ + /* #define PRISM2_NO_STATION_MODES */ + ++/* Enable TX power Setting functions ++ * (min att = -128 , max att = 127) ++ */ ++#define RAW_TXPOWER_SETTING ++ + #endif /* HOSTAP_CONFIG_H */ +--- a/drivers/net/wireless/hostap/hostap.h ++++ b/drivers/net/wireless/hostap/hostap.h +@@ -90,6 +90,7 @@ extern const struct iw_handler_def hosta + extern const struct ethtool_ops prism2_ethtool_ops; + + int hostap_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); ++int hostap_restore_power(struct net_device *dev); + + + #endif /* HOSTAP_H */ +--- a/drivers/net/wireless/hostap/hostap_hw.c ++++ b/drivers/net/wireless/hostap/hostap_hw.c +@@ -928,6 +928,7 @@ static int hfa384x_set_rid(struct net_de + prism2_hw_reset(dev); + } + ++ hostap_restore_power(dev); + return res; + } + +--- a/drivers/net/wireless/hostap/hostap_info.c ++++ b/drivers/net/wireless/hostap/hostap_info.c +@@ -435,6 +435,11 @@ static void handle_info_queue_linkstatus + } + + /* Get BSSID if we have a valid AP address */ ++ ++ if ( val == HFA384X_LINKSTATUS_CONNECTED || ++ val == HFA384X_LINKSTATUS_DISCONNECTED ) ++ hostap_restore_power(local->dev); ++ + if (connected) { + netif_carrier_on(local->dev); + netif_carrier_on(local->ddev); +--- a/drivers/net/wireless/hostap/hostap_ioctl.c ++++ b/drivers/net/wireless/hostap/hostap_ioctl.c +@@ -1479,23 +1479,20 @@ static int prism2_txpower_hfa386x_to_dBm + val = 255; + + tmp = val; +- tmp >>= 2; + +- return -12 - tmp; ++ return tmp; + } + + static u16 prism2_txpower_dBm_to_hfa386x(int val) + { + signed char tmp; + +- if (val > 20) +- return 128; +- else if (val < -43) ++ if (val > 127) + return 127; ++ else if (val < -128) ++ return 128; + + tmp = val; +- tmp = -12 - tmp; +- tmp <<= 2; + + return (unsigned char) tmp; + } +@@ -4052,3 +4049,35 @@ int hostap_ioctl(struct net_device *dev, + + return ret; + } ++ ++/* BUG FIX: Restore power setting value when lost due to F/W bug */ ++ ++int hostap_restore_power(struct net_device *dev) ++{ ++ struct hostap_interface *iface = netdev_priv(dev); ++ local_info_t *local = iface->local; ++ ++ u16 val; ++ int ret = 0; ++ ++ if (local->txpower_type == PRISM2_TXPOWER_OFF) { ++ val = 0xff; /* use all standby and sleep modes */ ++ ret = local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, ++ HFA386X_CR_A_D_TEST_MODES2, ++ &val, NULL); ++ } ++ ++#ifdef RAW_TXPOWER_SETTING ++ if (local->txpower_type == PRISM2_TXPOWER_FIXED) { ++ val = HFA384X_TEST_CFG_BIT_ALC; ++ local->func->cmd(dev, HFA384X_CMDCODE_TEST | ++ (HFA384X_TEST_CFG_BITS << 8), 0, &val, NULL); ++ val = prism2_txpower_dBm_to_hfa386x(local->txpower); ++ ret = (local->func->cmd(dev, HFA384X_CMDCODE_WRITEMIF, ++ HFA386X_CR_MANUAL_TX_POWER, &val, NULL)); ++ } ++#endif /* RAW_TXPOWER_SETTING */ ++ return (ret ? -EOPNOTSUPP : 0); ++} ++ ++EXPORT_SYMBOL(hostap_restore_power); diff --git a/target/linux/generic/patches-4.3/761-8139cp-fixes-from-4.4.patch b/target/linux/generic/patches-4.3/761-8139cp-fixes-from-4.4.patch new file mode 100644 index 0000000..8fdf5f3 --- /dev/null +++ b/target/linux/generic/patches-4.3/761-8139cp-fixes-from-4.4.patch @@ -0,0 +1,103 @@ +commit 8b7a7048220f86547db31de0abe1ea6dd2cfa892 +Author: David Woodhouse +Date: Thu Sep 24 11:38:22 2015 +0100 + + 8139cp: Fix GSO MSS handling + + When fixing the TSO support I noticed we just mask ->gso_size with the + MSSMask value and don't care about the consequences. + + Provide a .ndo_features_check() method which drops the NETIF_F_TSO + feature for any skb which would exceed the maximum, and thus forces it + to be segmented by software. + + Then we can stop the masking in cp_start_xmit(), and just WARN if the + maximum is exceeded, which should now never happen. + + Finally, Francois Romieu noticed that we didn't even have the right + value for MSSMask anyway; it should be 0x7ff (11 bits) not 0xfff. + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller + +commit 5a58f227790faded5a3ef6075f3ddd65093e0f86 +Author: David Woodhouse +Date: Wed Sep 23 09:46:09 2015 +0100 + + 8139cp: Enable offload features by default + + I fixed TSO. Hardware checksum and scatter/gather also appear to be + working correctly both on real hardware and in QEMU's emulation. + + Let's enable them by default and see if anyone screams... + + Signed-off-by: David Woodhouse + Signed-off-by: David S. Miller +--- a/drivers/net/ethernet/realtek/8139cp.c ++++ b/drivers/net/ethernet/realtek/8139cp.c +@@ -175,7 +175,7 @@ enum { + LastFrag = (1 << 28), /* Final segment of a packet */ + LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ + MSSShift = 16, /* MSS value position */ +- MSSMask = 0xfff, /* MSS value: 11 bits */ ++ MSSMask = 0x7ff, /* MSS value: 11 bits */ + TxError = (1 << 23), /* Tx error summary */ + RxError = (1 << 20), /* Rx error summary */ + IPCS = (1 << 18), /* Calculate IP checksum */ +@@ -754,10 +754,16 @@ static netdev_tx_t cp_start_xmit (struct + eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; + mss = skb_shinfo(skb)->gso_size; + ++ if (mss > MSSMask) { ++ WARN_ONCE(1, "Net bug: GSO size %d too large for 8139CP\n", ++ mss); ++ goto out_dma_error; ++ } ++ + opts2 = cpu_to_le32(cp_tx_vlan_tag(skb)); + opts1 = DescOwn; + if (mss) +- opts1 |= LargeSend | ((mss & MSSMask) << MSSShift); ++ opts1 |= LargeSend | (mss << MSSShift); + else if (skb->ip_summed == CHECKSUM_PARTIAL) { + const struct iphdr *ip = ip_hdr(skb); + if (ip->protocol == IPPROTO_TCP) +@@ -1852,6 +1858,15 @@ static void cp_set_d3_state (struct cp_p + pci_set_power_state (cp->pdev, PCI_D3hot); + } + ++static netdev_features_t cp_features_check(struct sk_buff *skb, ++ struct net_device *dev, ++ netdev_features_t features) ++{ ++ if (skb_shinfo(skb)->gso_size > MSSMask) ++ features &= ~NETIF_F_TSO; ++ ++ return vlan_features_check(skb, features); ++} + static const struct net_device_ops cp_netdev_ops = { + .ndo_open = cp_open, + .ndo_stop = cp_close, +@@ -1864,6 +1879,7 @@ static const struct net_device_ops cp_ne + .ndo_tx_timeout = cp_tx_timeout, + .ndo_set_features = cp_set_features, + .ndo_change_mtu = cp_change_mtu, ++ .ndo_features_check = cp_features_check, + + #ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = cp_poll_controller, +@@ -1983,12 +1999,12 @@ static int cp_init_one (struct pci_dev * + dev->ethtool_ops = &cp_ethtool_ops; + dev->watchdog_timeo = TX_TIMEOUT; + +- dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; ++ dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | ++ NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; + + if (pci_using_dac) + dev->features |= NETIF_F_HIGHDMA; + +- /* disabled by default until verified */ + dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | + NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; + dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | diff --git a/target/linux/generic/patches-4.3/773-bgmac-add-srab-switch.patch b/target/linux/generic/patches-4.3/773-bgmac-add-srab-switch.patch new file mode 100644 index 0000000..f5bd743 --- /dev/null +++ b/target/linux/generic/patches-4.3/773-bgmac-add-srab-switch.patch @@ -0,0 +1,72 @@ +Register switch connected to srab + +Signed-off-by: Hauke Mehrtens + +--- a/drivers/net/ethernet/broadcom/bgmac.c ++++ b/drivers/net/ethernet/broadcom/bgmac.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + static const struct bcma_device_id bgmac_bcma_tbl[] = { +@@ -1538,6 +1539,17 @@ static void bgmac_mii_unregister(struct + mdiobus_free(mii_bus); + } + ++static struct b53_platform_data bgmac_b53_pdata = { ++}; ++ ++static struct platform_device bgmac_b53_dev = { ++ .name = "b53-srab-switch", ++ .id = -1, ++ .dev = { ++ .platform_data = &bgmac_b53_pdata, ++ }, ++}; ++ + /************************************************** + * BCMA bus ops + **************************************************/ +@@ -1682,6 +1694,16 @@ static int bgmac_probe(struct bcma_devic + net_dev->hw_features = net_dev->features; + net_dev->vlan_features = net_dev->features; + ++ if ((ci->id == BCMA_CHIP_ID_BCM4707 || ++ ci->id == BCMA_CHIP_ID_BCM53018) && ++ !bgmac_b53_pdata.regs) { ++ bgmac_b53_pdata.regs = ioremap_nocache(0x18007000, 0x1000); ++ ++ err = platform_device_register(&bgmac_b53_dev); ++ if (!err) ++ bgmac->b53_device = &bgmac_b53_dev; ++ } ++ + err = register_netdev(bgmac->net_dev); + if (err) { + bgmac_err(bgmac, "Cannot register net device\n"); +@@ -1708,6 +1730,10 @@ static void bgmac_remove(struct bcma_dev + { + struct bgmac *bgmac = bcma_get_drvdata(core); + ++ if (bgmac->b53_device) ++ platform_device_unregister(&bgmac_b53_dev); ++ bgmac->b53_device = NULL; ++ + unregister_netdev(bgmac->net_dev); + bgmac_mii_unregister(bgmac); + netif_napi_del(&bgmac->napi); +--- a/drivers/net/ethernet/broadcom/bgmac.h ++++ b/drivers/net/ethernet/broadcom/bgmac.h +@@ -463,6 +463,9 @@ struct bgmac { + bool has_robosw; + + bool loopback; ++ ++ /* platform device for associated switch */ ++ struct platform_device *b53_device; + }; + + static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset) diff --git a/target/linux/generic/patches-4.3/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch b/target/linux/generic/patches-4.3/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch new file mode 100644 index 0000000..e541b2c --- /dev/null +++ b/target/linux/generic/patches-4.3/780-igb-Fix-Null-pointer-dereference-in-igb_reset_q_vect.patch @@ -0,0 +1,40 @@ +From cb06d102327eadcd1bdc480bfd9f8876251d1007 Mon Sep 17 00:00:00 2001 +From: Christoph Paasch +Date: Fri, 21 Mar 2014 03:48:19 -0700 +Subject: [PATCH] igb: Fix Null-pointer dereference in igb_reset_q_vector + +When igb_set_interrupt_capability() calls +igb_reset_interrupt_capability() (e.g., because CONFIG_PCI_MSI is unset), +num_q_vectors has been set but no vector has yet been allocated. + +igb_reset_interrupt_capability() will then call igb_reset_q_vector, +which assumes that the vector is allocated. As this is not the case, we +are accessing a NULL-pointer. + +This patch fixes it by checking that q_vector is indeed different from +NULL. + +Fixes: 02ef6e1d0b0023 (igb: Fix queue allocation method to accommodate changing during runtime) +Cc: Carolyn Wyborny +Signed-off-by: Christoph Paasch +Tested-by: Jeff Pieper +Signed-off-by: Jeff Kirsher +--- + drivers/net/ethernet/intel/igb/igb_main.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/net/ethernet/intel/igb/igb_main.c ++++ b/drivers/net/ethernet/intel/igb/igb_main.c +@@ -1034,6 +1034,12 @@ static void igb_reset_q_vector(struct ig + if (!q_vector) + return; + ++ /* Coming from igb_set_interrupt_capability, the vectors are not yet ++ * allocated. So, q_vector is NULL so we should stop here. ++ */ ++ if (!q_vector) ++ return; ++ + if (q_vector->tx.ring) + adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; + diff --git a/target/linux/generic/patches-4.3/785-hso-support-0af0-9300.patch b/target/linux/generic/patches-4.3/785-hso-support-0af0-9300.patch new file mode 100644 index 0000000..621d08f --- /dev/null +++ b/target/linux/generic/patches-4.3/785-hso-support-0af0-9300.patch @@ -0,0 +1,25 @@ +--- a/drivers/net/usb/hso.c ++++ b/drivers/net/usb/hso.c +@@ -466,6 +466,7 @@ static const struct usb_device_id hso_id + {USB_DEVICE(0x0af0, 0x8900)}, + {USB_DEVICE(0x0af0, 0x9000)}, + {USB_DEVICE(0x0af0, 0x9200)}, /* Option GTM671WFS */ ++ {USB_DEVICE(0x0af0, 0x9300)}, /* GTM 66xxWFS */ + {USB_DEVICE(0x0af0, 0xd035)}, + {USB_DEVICE(0x0af0, 0xd055)}, + {USB_DEVICE(0x0af0, 0xd155)}, +--- a/drivers/usb/storage/unusual_devs.h ++++ b/drivers/usb/storage/unusual_devs.h +@@ -1330,6 +1330,12 @@ UNUSUAL_DEV( 0x0af0, 0x8304, 0x0000, 0x0 + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + 0 ), + ++UNUSUAL_DEV( 0x0af0, 0x9300, 0x0000, 0x0000, ++ "Option", ++ "Globetrotter 66xxWFS SD-Card", ++ USB_SC_DEVICE, USB_PR_DEVICE, NULL, ++ 0 ), ++ + UNUSUAL_DEV( 0x0af0, 0xc100, 0x0000, 0x0000, + "Option", + "GI 070x SD-Card", diff --git a/target/linux/generic/patches-4.3/810-pci_disable_common_quirks.patch b/target/linux/generic/patches-4.3/810-pci_disable_common_quirks.patch new file mode 100644 index 0000000..883548d --- /dev/null +++ b/target/linux/generic/patches-4.3/810-pci_disable_common_quirks.patch @@ -0,0 +1,51 @@ +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -68,6 +68,12 @@ config XEN_PCIDEV_FRONTEND + The PCI device frontend driver allows the kernel to import arbitrary + PCI devices from a PCI backend to support PCI driver domains. + ++config PCI_DISABLE_COMMON_QUIRKS ++ bool "PCI disable common quirks" ++ depends on PCI ++ help ++ If you don't know what to do here, say N. ++ + config HT_IRQ + bool "Interrupts on hypertransport devices" + default y +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -41,6 +41,7 @@ static void quirk_mmio_always_on(struct + DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS + /* The Mellanox Tavor device gives false positive parity errors + * Mark this device with a broken_parity_status, to allow + * PCI scanning code to "skip" this now blacklisted device. +@@ -2962,6 +2963,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); + ++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ + + /* + * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To +@@ -3018,6 +3020,8 @@ static void fixup_debug_report(struct pc + } + } + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + /* + * Some BIOS implementations leave the Intel GPU interrupts enabled, + * even though no one is handling them (f.e. i915 driver is never loaded). +@@ -3052,6 +3056,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); + ++#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ ++ + /* + * PCI devices which are on Intel chips can skip the 10ms delay + * before entering D3 mode. diff --git a/target/linux/generic/patches-4.3/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/patches-4.3/811-pci_disable_usb_common_quirks.patch new file mode 100644 index 0000000..6de4f6b --- /dev/null +++ b/target/linux/generic/patches-4.3/811-pci_disable_usb_common_quirks.patch @@ -0,0 +1,101 @@ + +--- a/drivers/usb/host/pci-quirks.c ++++ b/drivers/usb/host/pci-quirks.c +@@ -97,6 +97,8 @@ struct amd_chipset_type { + u8 rev; + }; + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + static struct amd_chipset_info { + struct pci_dev *nb_dev; + struct pci_dev *smbus_dev; +@@ -450,6 +452,10 @@ void usb_amd_dev_put(void) + } + EXPORT_SYMBOL_GPL(usb_amd_dev_put); + ++#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */ ++ ++#if IS_ENABLED(CONFIG_USB_UHCI_HCD) ++ + /* + * Make sure the controller is completely inactive, unable to + * generate interrupts or do DMA. +@@ -529,8 +535,17 @@ reset_needed: + uhci_reset_hc(pdev, base); + return 1; + } ++#else ++int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) ++{ ++ return 0; ++} ++ ++#endif + EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS ++ + static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) + { + u16 cmd; +@@ -1095,3 +1110,4 @@ static void quirk_usb_early_handoff(stru + } + DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, + PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); ++#endif +--- a/drivers/usb/host/pci-quirks.h ++++ b/drivers/usb/host/pci-quirks.h +@@ -4,6 +4,9 @@ + #ifdef CONFIG_PCI + void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); + int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); ++#endif /* CONFIG_PCI */ ++ ++#if defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_COMMON_QUIRKS) + int usb_amd_find_chipset_info(void); + int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev); + bool usb_amd_hang_symptom_quirk(void); +@@ -16,11 +19,24 @@ void usb_disable_xhci_ports(struct pci_d + void sb800_prefetch(struct device *dev, int on); + #else + struct pci_dev; ++static inline int usb_amd_find_chipset_info(void) ++{ ++ return 0; ++} ++static inline bool usb_amd_hang_symptom_quirk(void) ++{ ++ return false; ++} ++static inline bool usb_amd_prefetch_quirk(void) ++{ ++ return false; ++} + static inline void usb_amd_quirk_pll_disable(void) {} + static inline void usb_amd_quirk_pll_enable(void) {} + static inline void usb_amd_dev_put(void) {} + static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {} + static inline void sb800_prefetch(struct device *dev, int on) {} +-#endif /* CONFIG_PCI */ ++static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {} ++#endif + + #endif /* __LINUX_USB_PCI_QUIRKS_H */ +--- a/include/linux/usb/hcd.h ++++ b/include/linux/usb/hcd.h +@@ -447,7 +447,14 @@ extern int usb_hcd_pci_probe(struct pci_ + extern void usb_hcd_pci_remove(struct pci_dev *dev); + extern void usb_hcd_pci_shutdown(struct pci_dev *dev); + ++#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS + extern int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev); ++#else ++static inline int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev) ++{ ++ return 0; ++} ++#endif + + #ifdef CONFIG_PM + extern const struct dev_pm_ops usb_hcd_pci_pm_ops; diff --git a/target/linux/generic/patches-4.3/820-usb_add_usb_find_device_by_name.patch b/target/linux/generic/patches-4.3/820-usb_add_usb_find_device_by_name.patch new file mode 100644 index 0000000..906f0e2 --- /dev/null +++ b/target/linux/generic/patches-4.3/820-usb_add_usb_find_device_by_name.patch @@ -0,0 +1,84 @@ +--- a/drivers/usb/core/usb.c ++++ b/drivers/usb/core/usb.c +@@ -704,6 +704,71 @@ int __usb_get_extra_descriptor(char *buf + } + EXPORT_SYMBOL_GPL(__usb_get_extra_descriptor); + ++static struct usb_device *match_device_name(struct usb_device *dev, ++ const char *name) ++{ ++ struct usb_device *ret_dev = NULL; ++ struct usb_device *childdev = NULL; ++ int child; ++ ++ dev_dbg(&dev->dev, "check for name %s ...\n", name); ++ ++ /* see if this device matches */ ++ if (strcmp(dev_name(&dev->dev), name) == 0 ) { ++ dev_dbg(&dev->dev, "matched this device!\n"); ++ ret_dev = usb_get_dev(dev); ++ goto exit; ++ } ++ /* look through all of the children of this device */ ++ usb_hub_for_each_child(dev, child, childdev) { ++ if (childdev) { ++ usb_lock_device(childdev); ++ ret_dev = match_device_name(childdev, name); ++ usb_unlock_device(childdev); ++ if (ret_dev) ++ goto exit; ++ } ++ } ++exit: ++ return ret_dev; ++} ++ ++/** ++ * usb_find_device_by_name - find a specific usb device in the system ++ * @name: the name of the device to find ++ * ++ * Returns a pointer to a struct usb_device if such a specified usb ++ * device is present in the system currently. The usage count of the ++ * device will be incremented if a device is found. Make sure to call ++ * usb_put_dev() when the caller is finished with the device. ++ * ++ * If a device with the specified bus id is not found, NULL is returned. ++ */ ++struct usb_device *usb_find_device_by_name(const char *name) ++{ ++ struct list_head *buslist; ++ struct usb_bus *bus; ++ struct usb_device *dev = NULL; ++ ++ mutex_lock(&usb_bus_list_lock); ++ for (buslist = usb_bus_list.next; ++ buslist != &usb_bus_list; ++ buslist = buslist->next) { ++ bus = container_of(buslist, struct usb_bus, bus_list); ++ if (!bus->root_hub) ++ continue; ++ usb_lock_device(bus->root_hub); ++ dev = match_device_name(bus->root_hub, name); ++ usb_unlock_device(bus->root_hub); ++ if (dev) ++ goto exit; ++ } ++exit: ++ mutex_unlock(&usb_bus_list_lock); ++ return dev; ++} ++EXPORT_SYMBOL_GPL(usb_find_device_by_name); ++ + /** + * usb_alloc_coherent - allocate dma-consistent buffer for URB_NO_xxx_DMA_MAP + * @dev: device the buffer will be used with +--- a/include/linux/usb.h ++++ b/include/linux/usb.h +@@ -721,6 +721,7 @@ static inline bool usb_device_no_sg_cons + return udev && udev->bus && udev->bus->no_sg_constraint; + } + ++extern struct usb_device *usb_find_device_by_name(const char *name); + + /*-------------------------------------------------------------------------*/ + diff --git a/target/linux/generic/patches-4.3/830-ledtrig_morse.patch b/target/linux/generic/patches-4.3/830-ledtrig_morse.patch new file mode 100644 index 0000000..87619d4 --- /dev/null +++ b/target/linux/generic/patches-4.3/830-ledtrig_morse.patch @@ -0,0 +1,28 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -108,4 +108,8 @@ config LEDS_TRIGGER_CAMERA + This enables direct flash/torch on/off by the driver, kernel space. + If unsure, say Y. + ++config LEDS_TRIGGER_MORSE ++ tristate "LED Morse Trigger" ++ depends on LEDS_TRIGGERS ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -71,3 +71,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ ++obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o +--- a/drivers/leds/ledtrig-morse.c ++++ b/drivers/leds/ledtrig-morse.c +@@ -26,7 +26,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/generic/patches-4.3/831-ledtrig_netdev.patch b/target/linux/generic/patches-4.3/831-ledtrig_netdev.patch new file mode 100644 index 0000000..e3bb556 --- /dev/null +++ b/target/linux/generic/patches-4.3/831-ledtrig_netdev.patch @@ -0,0 +1,60 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -112,4 +112,11 @@ config LEDS_TRIGGER_MORSE + tristate "LED Morse Trigger" + depends on LEDS_TRIGGERS + ++config LEDS_TRIGGER_NETDEV ++ tristate "LED Netdev Trigger" ++ depends on NET && LEDS_TRIGGERS ++ help ++ This allows LEDs to be controlled by network device activity. ++ If unsure, say Y. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -72,3 +72,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + # LED Triggers + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o ++obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o +--- a/drivers/leds/ledtrig-netdev.c ++++ b/drivers/leds/ledtrig-netdev.c +@@ -22,7 +22,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -254,7 +253,7 @@ static int netdev_trig_notify(struct not + unsigned long evt, + void *dv) + { +- struct net_device *dev = dv; ++ struct net_device *dev = netdev_notifier_info_to_dev((struct netdev_notifier_info *) dv); + struct led_netdev_data *trigger_data = container_of(nb, struct led_netdev_data, notifier); + + if (evt != NETDEV_UP && evt != NETDEV_DOWN && evt != NETDEV_CHANGE && evt != NETDEV_REGISTER && evt != NETDEV_UNREGISTER) +@@ -294,8 +293,9 @@ done: + static void netdev_trig_timer(unsigned long arg) + { + struct led_netdev_data *trigger_data = (struct led_netdev_data *)arg; +- const struct net_device_stats *dev_stats; ++ struct rtnl_link_stats64 *dev_stats; + unsigned new_activity; ++ struct rtnl_link_stats64 temp; + + write_lock(&trigger_data->lock); + +@@ -305,7 +305,7 @@ static void netdev_trig_timer(unsigned l + goto no_restart; + } + +- dev_stats = dev_get_stats(trigger_data->net_dev); ++ dev_stats = dev_get_stats(trigger_data->net_dev, &temp); + new_activity = + ((trigger_data->mode & MODE_TX) ? dev_stats->tx_packets : 0) + + ((trigger_data->mode & MODE_RX) ? dev_stats->rx_packets : 0); diff --git a/target/linux/generic/patches-4.3/832-ledtrig_usbdev.patch b/target/linux/generic/patches-4.3/832-ledtrig_usbdev.patch new file mode 100644 index 0000000..9c69fe5 --- /dev/null +++ b/target/linux/generic/patches-4.3/832-ledtrig_usbdev.patch @@ -0,0 +1,31 @@ +--- a/drivers/leds/trigger/Kconfig ++++ b/drivers/leds/trigger/Kconfig +@@ -119,4 +119,11 @@ config LEDS_TRIGGER_NETDEV + This allows LEDs to be controlled by network device activity. + If unsure, say Y. + ++config LEDS_TRIGGER_USBDEV ++ tristate "LED USB device Trigger" ++ depends on USB && LEDS_TRIGGERS ++ help ++ This allows LEDs to be controlled by the presence/activity of ++ an USB device. If unsure, say N. ++ + endif # LEDS_TRIGGERS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -73,3 +73,4 @@ obj-$(CONFIG_LEDS_DAC124S085) += leds-d + obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ + obj-$(CONFIG_LEDS_TRIGGER_MORSE) += ledtrig-morse.o + obj-$(CONFIG_LEDS_TRIGGER_NETDEV) += ledtrig-netdev.o ++obj-$(CONFIG_LEDS_TRIGGER_USBDEV) += ledtrig-usbdev.o +--- a/drivers/leds/ledtrig-usbdev.c ++++ b/drivers/leds/ledtrig-usbdev.c +@@ -24,7 +24,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/generic/patches-4.3/834-ledtrig-libata.patch b/target/linux/generic/patches-4.3/834-ledtrig-libata.patch new file mode 100644 index 0000000..2144651 --- /dev/null +++ b/target/linux/generic/patches-4.3/834-ledtrig-libata.patch @@ -0,0 +1,153 @@ +From 52cfd51cdf6a6e14d4fb270c6343abac3bac00f4 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 12 Dec 2014 13:38:33 +0100 +Subject: [PATCH] libata: add ledtrig support +To: linux-ide@vger.kernel.org, + Tejun Heo + +This adds a LED trigger for each ATA port indicating disk activity. + +As this is needed only on specific platforms (NAS SoCs and such), +these platforms should define ARCH_WANTS_LIBATA_LEDS if there +are boards with LED(s) intended to indicate ATA disk activity and +need the OS to take care of that. +In that way, if not selected, LED trigger support not will be +included in libata-core and both, codepaths and structures remain +untouched. + +Signed-off-by: Daniel Golle +--- + drivers/ata/Kconfig | 16 ++++++++++++++++ + drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++ + include/linux/libata.h | 9 +++++++++ + 3 files changed, 66 insertions(+) + +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -46,6 +46,22 @@ config ATA_VERBOSE_ERROR + + If unsure, say Y. + ++config ARCH_WANT_LIBATA_LEDS ++ bool ++ ++config ATA_LEDS ++ bool "support ATA port LED triggers" ++ depends on ARCH_WANT_LIBATA_LEDS ++ select NEW_LEDS ++ select LEDS_CLASS ++ select LEDS_TRIGGERS ++ default y ++ help ++ This option adds a LED trigger for each registered ATA port. ++ It is used to drive disk activity leds connected via GPIO. ++ ++ If unsure, say N. ++ + config ATA_ACPI + bool "ATA ACPI Support" + depends on ACPI +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -728,6 +728,19 @@ u64 ata_tf_read_block(struct ata_taskfil + return block; + } + ++#ifdef CONFIG_ATA_LEDS ++#define LIBATA_BLINK_DELAY 20 /* ms */ ++static inline void ata_led_act(struct ata_port *ap) ++{ ++ unsigned long led_delay = LIBATA_BLINK_DELAY; ++ ++ if (unlikely(!ap->ledtrig)) ++ return; ++ ++ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0); ++} ++#endif ++ + /** + * ata_build_rw_tf - Build ATA taskfile for given read/write request + * @tf: Target ATA taskfile +@@ -4774,6 +4787,9 @@ struct ata_queued_cmd *ata_qc_new_init(s + if (tag < 0) + return NULL; + } ++#ifdef CONFIG_ATA_LEDS ++ ata_led_act(ap); ++#endif + + qc = __ata_qc_from_tag(ap, tag); + qc->tag = tag; +@@ -5671,6 +5687,9 @@ struct ata_port *ata_port_alloc(struct a + ap->stats.unhandled_irq = 1; + ap->stats.idle_irq = 1; + #endif ++#ifdef CONFIG_ATA_LEDS ++ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL); ++#endif + ata_sff_port_init(ap); + + return ap; +@@ -5692,6 +5711,12 @@ static void ata_host_release(struct devi + + kfree(ap->pmp_link); + kfree(ap->slave_link); ++#ifdef CONFIG_ATA_LEDS ++ if (ap->ledtrig) { ++ led_trigger_unregister(ap->ledtrig); ++ kfree(ap->ledtrig); ++ }; ++#endif + kfree(ap); + host->ports[i] = NULL; + } +@@ -6138,7 +6163,23 @@ int ata_host_register(struct ata_host *h + host->ports[i]->print_id = atomic_inc_return(&ata_print_id); + host->ports[i]->local_port_no = i + 1; + } ++#ifdef CONFIG_ATA_LEDS ++ for (i = 0; i < host->n_ports; i++) { ++ if (unlikely(!host->ports[i]->ledtrig)) ++ continue; + ++ snprintf(host->ports[i]->ledtrig_name, ++ sizeof(host->ports[i]->ledtrig_name), "ata%u", ++ host->ports[i]->print_id); ++ ++ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name; ++ ++ if (led_trigger_register(host->ports[i]->ledtrig)) { ++ kfree(host->ports[i]->ledtrig); ++ host->ports[i]->ledtrig = NULL; ++ } ++ } ++#endif + /* Create associated sysfs transport objects */ + for (i = 0; i < host->n_ports; i++) { + rc = ata_tport_add(host->dev,host->ports[i]); +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -38,6 +38,9 @@ + #include + #include + #include ++#ifdef CONFIG_ATA_LEDS ++#include ++#endif + + /* + * Define if arch has non-standard setup. This is a _PCI_ standard +@@ -875,6 +878,12 @@ struct ata_port { + #ifdef CONFIG_ATA_ACPI + struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ + #endif ++ ++#ifdef CONFIG_ATA_LEDS ++ struct led_trigger *ledtrig; ++ char ledtrig_name[8]; ++#endif ++ + /* owned by EH */ + u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; + }; diff --git a/target/linux/generic/patches-4.3/840-rtc7301.patch b/target/linux/generic/patches-4.3/840-rtc7301.patch new file mode 100644 index 0000000..d329e92 --- /dev/null +++ b/target/linux/generic/patches-4.3/840-rtc7301.patch @@ -0,0 +1,250 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1123,6 +1123,15 @@ config RTC_DRV_ZYNQMP + If you say yes here you get support for the RTC controller found on + Xilinx Zynq Ultrascale+ MPSoC. + ++config RTC_DRV_RTC7301 ++ tristate "Epson RTC-7301 SF/DG" ++ help ++ If you say Y here you will get support for the ++ Epson RTC-7301 SF/DG RTC chips. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-7301. ++ + comment "on-CPU RTC drivers" + + config RTC_DRV_DAVINCI +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -125,6 +125,7 @@ obj-$(CONFIG_RTC_DRV_RP5C01) += rtc-rp5c + obj-$(CONFIG_RTC_DRV_RS5C313) += rtc-rs5c313.o + obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o + obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o ++obj-$(CONFIG_RTC_DRV_RTC7301) += rtc-rtc7301.o + obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o + obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o + obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o +--- /dev/null ++++ b/drivers/rtc/rtc-rtc7301.c +@@ -0,0 +1,219 @@ ++/* ++ * Driver for Epson RTC-7301SF/DG ++ * ++ * Copyright (C) 2009 Jose Vasconcellos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RTC_NAME "rtc7301" ++#define RTC_VERSION "0.1" ++ ++/* Epson RTC-7301 register addresses */ ++#define RTC7301_SEC 0x00 ++#define RTC7301_SEC10 0x01 ++#define RTC7301_MIN 0x02 ++#define RTC7301_MIN10 0x03 ++#define RTC7301_HOUR 0x04 ++#define RTC7301_HOUR10 0x05 ++#define RTC7301_WEEKDAY 0x06 ++#define RTC7301_DAY 0x07 ++#define RTC7301_DAY10 0x08 ++#define RTC7301_MON 0x09 ++#define RTC7301_MON10 0x0A ++#define RTC7301_YEAR 0x0B ++#define RTC7301_YEAR10 0x0C ++#define RTC7301_YEAR100 0x0D ++#define RTC7301_YEAR1000 0x0E ++#define RTC7301_CTRLREG 0x0F ++ ++static uint8_t __iomem *rtc7301_base; ++ ++#define read_reg(offset) (readb(rtc7301_base + offset) & 0xf) ++#define write_reg(offset, data) writeb(data, rtc7301_base + (offset)) ++ ++#define rtc7301_isbusy() (read_reg(RTC7301_CTRLREG) & 1) ++ ++static void rtc7301_init_settings(void) ++{ ++ int i; ++ ++ write_reg(RTC7301_CTRLREG, 2); ++ write_reg(RTC7301_YEAR1000, 2); ++ udelay(122); ++ ++ /* bank 1 */ ++ write_reg(RTC7301_CTRLREG, 6); ++ for (i=0; i<15; i++) ++ write_reg(i, 0); ++ ++ /* bank 2 */ ++ write_reg(RTC7301_CTRLREG, 14); ++ for (i=0; i<15; i++) ++ write_reg(i, 0); ++ write_reg(RTC7301_CTRLREG, 0); ++} ++ ++static int rtc7301_get_datetime(struct device *dev, struct rtc_time *dt) ++{ ++ int cnt; ++ uint8_t buf[16]; ++ ++ cnt = 0; ++ while (rtc7301_isbusy()) { ++ udelay(244); ++ if (cnt++ > 100) { ++ dev_err(dev, "%s: timeout error %x\n", __func__, rtc7301_base[RTC7301_CTRLREG]); ++ return -EIO; ++ } ++ } ++ ++ for (cnt=0; cnt<16; cnt++) ++ buf[cnt] = read_reg(cnt); ++ ++ if (buf[RTC7301_SEC10] & 8) { ++ dev_err(dev, "%s: RTC not set\n", __func__); ++ return -EINVAL; ++ } ++ ++ memset(dt, 0, sizeof(*dt)); ++ ++ dt->tm_sec = buf[RTC7301_SEC] + buf[RTC7301_SEC10]*10; ++ dt->tm_min = buf[RTC7301_MIN] + buf[RTC7301_MIN10]*10; ++ dt->tm_hour = buf[RTC7301_HOUR] + buf[RTC7301_HOUR10]*10; ++ ++ dt->tm_mday = buf[RTC7301_DAY] + buf[RTC7301_DAY10]*10; ++ dt->tm_mon = buf[RTC7301_MON] + buf[RTC7301_MON10]*10 - 1; ++ dt->tm_year = buf[RTC7301_YEAR] + buf[RTC7301_YEAR10]*10 + ++ buf[RTC7301_YEAR100]*100 + ++ ((buf[RTC7301_YEAR1000] & 3)*1000) - 1900; ++ ++ /* the rtc device may contain illegal values on power up ++ * according to the data sheet. make sure they are valid. ++ */ ++ ++ return rtc_valid_tm(dt); ++} ++ ++static int rtc7301_set_datetime(struct device *dev, struct rtc_time *dt) ++{ ++ int data; ++ ++ data = dt->tm_year + 1900; ++ if (data >= 2100 || data < 1900) ++ return -EINVAL; ++ ++ write_reg(RTC7301_CTRLREG, 2); ++ udelay(122); ++ ++ data = bin2bcd(dt->tm_sec); ++ write_reg(RTC7301_SEC, data); ++ write_reg(RTC7301_SEC10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_min); ++ write_reg(RTC7301_MIN, data ); ++ write_reg(RTC7301_MIN10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_hour); ++ write_reg(RTC7301_HOUR, data); ++ write_reg(RTC7301_HOUR10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_mday); ++ write_reg(RTC7301_DAY, data); ++ write_reg(RTC7301_DAY10, (data>> 4)); ++ ++ data = bin2bcd(dt->tm_mon + 1); ++ write_reg(RTC7301_MON, data); ++ write_reg(RTC7301_MON10, (data >> 4)); ++ ++ data = bin2bcd(dt->tm_year % 100); ++ write_reg(RTC7301_YEAR, data); ++ write_reg(RTC7301_YEAR10, (data >> 4)); ++ data = bin2bcd((1900 + dt->tm_year) / 100); ++ write_reg(RTC7301_YEAR100, data); ++ ++ data = bin2bcd(dt->tm_wday); ++ write_reg(RTC7301_WEEKDAY, data); ++ ++ write_reg(RTC7301_CTRLREG, 0); ++ ++ return 0; ++} ++ ++static const struct rtc_class_ops rtc7301_rtc_ops = { ++ .read_time = rtc7301_get_datetime, ++ .set_time = rtc7301_set_datetime, ++}; ++ ++static int rtc7301_probe(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc; ++ struct resource *res; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return -ENOENT; ++ ++ rtc7301_base = ioremap_nocache(res->start, 0x1000 /*res->end - res->start + 1*/); ++ if (!rtc7301_base) ++ return -EINVAL; ++ ++ rtc = rtc_device_register(RTC_NAME, &pdev->dev, ++ &rtc7301_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtc)) { ++ iounmap(rtc7301_base); ++ return PTR_ERR(rtc); ++ } ++ ++ platform_set_drvdata(pdev, rtc); ++ ++ rtc7301_init_settings(); ++ return 0; ++} ++ ++static int rtc7301_remove(struct platform_device *pdev) ++{ ++ struct rtc_device *rtc = platform_get_drvdata(pdev); ++ ++ if (rtc) ++ rtc_device_unregister(rtc); ++ if (rtc7301_base) ++ iounmap(rtc7301_base); ++ return 0; ++} ++ ++static struct platform_driver rtc7301_driver = { ++ .driver = { ++ .name = RTC_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = rtc7301_probe, ++ .remove = rtc7301_remove, ++}; ++ ++static __init int rtc7301_init(void) ++{ ++ return platform_driver_register(&rtc7301_driver); ++} ++module_init(rtc7301_init); ++ ++static __exit void rtc7301_exit(void) ++{ ++ platform_driver_unregister(&rtc7301_driver); ++} ++module_exit(rtc7301_exit); ++ ++MODULE_DESCRIPTION("Epson 7301 RTC driver"); ++MODULE_AUTHOR("Jose Vasconcellos "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" RTC_NAME); ++MODULE_VERSION(RTC_VERSION); diff --git a/target/linux/generic/patches-4.3/841-rtc_pt7c4338.patch b/target/linux/generic/patches-4.3/841-rtc_pt7c4338.patch new file mode 100644 index 0000000..7c8e0d0 --- /dev/null +++ b/target/linux/generic/patches-4.3/841-rtc_pt7c4338.patch @@ -0,0 +1,247 @@ +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -603,6 +603,15 @@ config RTC_DRV_S5M + This driver can also be built as a module. If so, the module + will be called rtc-s5m. + ++config RTC_DRV_PT7C4338 ++ tristate "Pericom Technology Inc. PT7C4338 RTC" ++ help ++ If you say yes here you get support for the Pericom Technology ++ Inc. PT7C4338 RTC chip. ++ ++ This driver can also be built as a module. If so, the module ++ will be called rtc-pt7c4338. ++ + endif # I2C + + comment "SPI RTC drivers" +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -116,6 +116,7 @@ obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030 + obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o + obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o + obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o ++obj-$(CONFIG_RTC_DRV_PT7C4338) += rtc-pt7c4338.o + obj-$(CONFIG_RTC_DRV_PUV3) += rtc-puv3.o + obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o + obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o +--- /dev/null ++++ b/drivers/rtc/rtc-pt7c4338.c +@@ -0,0 +1,216 @@ ++/* ++ * Copyright 2010 Freescale Semiconductor, Inc. ++ * ++ * Author: Priyanka Jain ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * This file provides Date & Time support (no alarms) for PT7C4338 chip. ++ * ++ * This file is based on drivers/rtc/rtc-ds1307.c ++ * ++ * PT7C4338 chip is manufactured by Pericom Technology Inc. ++ * It is a serial real-time clock which provides ++ * 1)Low-power clock/calendar. ++ * 2)Programmable square-wave output. ++ * It has 56 bytes of nonvolatile RAM. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* RTC register addresses */ ++#define PT7C4338_REG_SECONDS 0x00 ++#define PT7C4338_REG_MINUTES 0x01 ++#define PT7C4338_REG_HOURS 0x02 ++#define PT7C4338_REG_AMPM 0x02 ++#define PT7C4338_REG_DAY 0x03 ++#define PT7C4338_REG_DATE 0x04 ++#define PT7C4338_REG_MONTH 0x05 ++#define PT7C4338_REG_YEAR 0x06 ++#define PT7C4338_REG_CTRL_STAT 0x07 ++ ++/* RTC second register address bit */ ++#define PT7C4338_SEC_BIT_CH 0x80 /*Clock Halt (in Register 0)*/ ++ ++/* RTC control and status register bits */ ++#define PT7C4338_CTRL_STAT_BIT_RS0 0x1 /*Rate select 0*/ ++#define PT7C4338_CTRL_STAT_BIT_RS1 0x2 /*Rate select 1*/ ++#define PT7C4338_CTRL_STAT_BIT_SQWE 0x10 /*Square Wave Enable*/ ++#define PT7C4338_CTRL_STAT_BIT_OSF 0x20 /*Oscillator Stop Flag*/ ++#define PT7C4338_CTRL_STAT_BIT_OUT 0x80 /*Output Level Control*/ ++ ++static const struct i2c_device_id pt7c4338_id[] = { ++ { "pt7c4338", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, pt7c4338_id); ++ ++struct pt7c4338{ ++ struct i2c_client *client; ++ struct rtc_device *rtc; ++}; ++ ++static int pt7c4338_read_time(struct device *dev, struct rtc_time *time) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ int ret; ++ u8 buf[7]; ++ u8 year, month, day, hour, minute, second; ++ u8 week, twelve_hr, am_pm; ++ ++ ret = i2c_smbus_read_i2c_block_data(client, ++ PT7C4338_REG_SECONDS, 7, buf); ++ if (ret < 0) ++ return ret; ++ if (ret < 7) ++ return -EIO; ++ ++ second = buf[0]; ++ minute = buf[1]; ++ hour = buf[2]; ++ week = buf[3]; ++ day = buf[4]; ++ month = buf[5]; ++ year = buf[6]; ++ ++ /* Extract additional information for AM/PM */ ++ twelve_hr = hour & 0x40; ++ am_pm = hour & 0x20; ++ ++ /* Write to rtc_time structure */ ++ time->tm_sec = bcd2bin(second & 0x7f); ++ time->tm_min = bcd2bin(minute & 0x7f); ++ if (twelve_hr) { ++ /* Convert to 24 hr */ ++ if (am_pm) ++ time->tm_hour = bcd2bin(hour & 0x10) + 12; ++ else ++ time->tm_hour = bcd2bin(hour & 0xBF); ++ } else { ++ time->tm_hour = bcd2bin(hour); ++ } ++ ++ time->tm_wday = bcd2bin(week & 0x07) - 1; ++ time->tm_mday = bcd2bin(day & 0x3f); ++ time->tm_mon = bcd2bin(month & 0x1F) - 1; ++ /* assume 20YY not 19YY */ ++ time->tm_year = bcd2bin(year) + 100; ++ ++ return 0; ++} ++ ++static int pt7c4338_set_time(struct device *dev, struct rtc_time *time) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ u8 buf[7]; ++ ++ /* Extract time from rtc_time and load into pt7c4338*/ ++ buf[0] = bin2bcd(time->tm_sec); ++ buf[1] = bin2bcd(time->tm_min); ++ buf[2] = bin2bcd(time->tm_hour); ++ buf[3] = bin2bcd(time->tm_wday + 1); /* Day of the week */ ++ buf[4] = bin2bcd(time->tm_mday); /* Date */ ++ buf[5] = bin2bcd(time->tm_mon + 1); ++ ++ /* assume 20YY not 19YY */ ++ if (time->tm_year >= 100) ++ buf[6] = bin2bcd(time->tm_year - 100); ++ else ++ buf[6] = bin2bcd(time->tm_year); ++ ++ return i2c_smbus_write_i2c_block_data(client, ++ PT7C4338_REG_SECONDS, 7, buf); ++} ++ ++static const struct rtc_class_ops pt7c4338_rtc_ops = { ++ .read_time = pt7c4338_read_time, ++ .set_time = pt7c4338_set_time, ++}; ++ ++static int pt7c4338_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct pt7c4338 *pt7c4338; ++ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); ++ int ret; ++ ++ pt7c4338 = kzalloc(sizeof(struct pt7c4338), GFP_KERNEL); ++ if (!pt7c4338) ++ return -ENOMEM; ++ ++ pt7c4338->client = client; ++ i2c_set_clientdata(client, pt7c4338); ++ pt7c4338->rtc = rtc_device_register(client->name, &client->dev, ++ &pt7c4338_rtc_ops, THIS_MODULE); ++ if (IS_ERR(pt7c4338->rtc)) { ++ ret = PTR_ERR(pt7c4338->rtc); ++ dev_err(&client->dev, "unable to register the class device\n"); ++ goto out_free; ++ } ++ ++ return 0; ++out_free: ++ i2c_set_clientdata(client, NULL); ++ kfree(pt7c4338); ++ return ret; ++} ++ ++static int pt7c4338_remove(struct i2c_client *client) ++{ ++ struct pt7c4338 *pt7c4338 = i2c_get_clientdata(client); ++ ++ rtc_device_unregister(pt7c4338->rtc); ++ i2c_set_clientdata(client, NULL); ++ kfree(pt7c4338); ++ return 0; ++} ++ ++static struct i2c_driver pt7c4338_driver = { ++ .driver = { ++ .name = "rtc-pt7c4338", ++ .owner = THIS_MODULE, ++ }, ++ .probe = pt7c4338_probe, ++ .remove = pt7c4338_remove, ++ .id_table = pt7c4338_id, ++}; ++ ++static int __init pt7c4338_init(void) ++{ ++ return i2c_add_driver(&pt7c4338_driver); ++} ++ ++static void __exit pt7c4338_exit(void) ++{ ++ i2c_del_driver(&pt7c4338_driver); ++} ++ ++module_init(pt7c4338_init); ++module_exit(pt7c4338_exit); ++ ++MODULE_AUTHOR("Priyanka Jain "); ++MODULE_DESCRIPTION("pericom Technology Inc. PT7C4338 RTC Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/patches-4.3/861-04_spi_gpio_implement_spi_delay.patch b/target/linux/generic/patches-4.3/861-04_spi_gpio_implement_spi_delay.patch new file mode 100644 index 0000000..fc1b40c --- /dev/null +++ b/target/linux/generic/patches-4.3/861-04_spi_gpio_implement_spi_delay.patch @@ -0,0 +1,58 @@ +Implement the SPI-GPIO delay function for busses that need speed limitation. + +--mb + + + +--- a/drivers/spi/spi-gpio.c ++++ b/drivers/spi/spi-gpio.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -69,6 +70,7 @@ struct spi_gpio { + * #define SPI_MOSI_GPIO 120 + * #define SPI_SCK_GPIO 121 + * #define SPI_N_CHIPSEL 4 ++ * #undef NEED_SPIDELAY + * #include "spi-gpio.c" + */ + +@@ -76,6 +78,7 @@ struct spi_gpio { + #define DRIVER_NAME "spi_gpio" + + #define GENERIC_BITBANG /* vs tight inlines */ ++#define NEED_SPIDELAY 1 + + /* all functions referencing these symbols must define pdata */ + #define SPI_MISO_GPIO ((pdata)->miso) +@@ -126,12 +129,20 @@ static inline int getmiso(const struct s + #undef pdata + + /* +- * NOTE: this clocks "as fast as we can". It "should" be a function of the +- * requested device clock. Software overhead means we usually have trouble +- * reaching even one Mbit/sec (except when we can inline bitops), so for now +- * we'll just assume we never need additional per-bit slowdowns. ++ * NOTE: to clock "as fast as we can", set spi_device.max_speed_hz ++ * and spi_transfer.speed_hz to 0. ++ * Otherwise this is a function of the requested device clock. ++ * Software overhead means we usually have trouble ++ * reaching even one Mbit/sec (except when we can inline bitops). So on small ++ * embedded devices with fast SPI slaves you usually don't need a delay. + */ +-#define spidelay(nsecs) do {} while (0) ++static inline void spidelay(unsigned nsecs) ++{ ++#ifdef NEED_SPIDELAY ++ if (unlikely(nsecs)) ++ ndelay(nsecs); ++#endif /* NEED_SPIDELAY */ ++} + + #include "spi-bitbang-txrx.h" + diff --git a/target/linux/generic/patches-4.3/862-gpio_spi_driver.patch b/target/linux/generic/patches-4.3/862-gpio_spi_driver.patch new file mode 100644 index 0000000..1cb1f0a --- /dev/null +++ b/target/linux/generic/patches-4.3/862-gpio_spi_driver.patch @@ -0,0 +1,373 @@ +THIS CODE IS DEPRECATED. + +Please use the new mainline SPI-GPIO driver, as of 2.6.29. + +--mb + + + +--- + drivers/spi/Kconfig | 9 + + drivers/spi/Makefile | 1 + drivers/spi/spi_gpio_old.c | 251 +++++++++++++++++++++++++++++++++++++++ + include/linux/spi/spi_gpio_old.h | 73 +++++++++++ + 4 files changed, 334 insertions(+) + +--- /dev/null ++++ b/include/linux/spi/spi_gpio_old.h +@@ -0,0 +1,73 @@ ++/* ++ * spi_gpio interface to platform code ++ * ++ * Copyright (c) 2008 Piotr Skamruk ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef _LINUX_SPI_SPI_GPIO ++#define _LINUX_SPI_SPI_GPIO ++ ++#include ++#include ++ ++ ++/** ++ * struct spi_gpio_platform_data - Data definitions for a SPI-GPIO device. ++ * ++ * This structure holds information about a GPIO-based SPI device. ++ * ++ * @pin_clk: The GPIO pin number of the CLOCK pin. ++ * ++ * @pin_miso: The GPIO pin number of the MISO pin. ++ * ++ * @pin_mosi: The GPIO pin number of the MOSI pin. ++ * ++ * @pin_cs: The GPIO pin number of the CHIPSELECT pin. ++ * ++ * @cs_activelow: If true, the chip is selected when the CS line is low. ++ * ++ * @no_spi_delay: If true, no delay is done in the lowlevel bitbanging. ++ * Note that doing no delay is not standards compliant, ++ * but it might be needed to speed up transfers on some ++ * slow embedded machines. ++ * ++ * @boardinfo_setup: This callback is called after the ++ * SPI master device was registered, but before the ++ * device is registered. ++ * @boardinfo_setup_data: Data argument passed to boardinfo_setup(). ++ */ ++struct spi_gpio_platform_data { ++ unsigned int pin_clk; ++ unsigned int pin_miso; ++ unsigned int pin_mosi; ++ unsigned int pin_cs; ++ bool cs_activelow; ++ bool no_spi_delay; ++ int (*boardinfo_setup)(struct spi_board_info *bi, ++ struct spi_master *master, ++ void *data); ++ void *boardinfo_setup_data; ++}; ++ ++/** ++ * SPI_GPIO_PLATDEV_NAME - The platform device name string. ++ * ++ * The name string that has to be used for platform_device_alloc ++ * when allocating a spi-gpio device. ++ */ ++#define SPI_GPIO_PLATDEV_NAME "spi-gpio" ++ ++/** ++ * spi_gpio_next_id - Get another platform device ID number. ++ * ++ * This returns the next platform device ID number that has to be used ++ * for platform_device_alloc. The ID is opaque and should not be used for ++ * anything else. ++ */ ++int spi_gpio_next_id(void); ++ ++#endif /* _LINUX_SPI_SPI_GPIO */ +--- /dev/null ++++ b/drivers/spi/spi_gpio_old.c +@@ -0,0 +1,251 @@ ++/* ++ * Bitbanging SPI bus driver using GPIO API ++ * ++ * Copyright (c) 2008 Piotr Skamruk ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * based on spi_s3c2410_gpio.c ++ * Copyright (c) 2006 Ben Dooks ++ * Copyright (c) 2006 Simtec Electronics ++ * and on i2c-gpio.c ++ * Copyright (C) 2007 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++struct spi_gpio { ++ struct spi_bitbang bitbang; ++ struct spi_gpio_platform_data *info; ++ struct platform_device *pdev; ++ struct spi_board_info bi; ++}; ++ ++ ++static inline struct spi_gpio *spidev_to_sg(struct spi_device *dev) ++{ ++ return dev->controller_data; ++} ++ ++static inline void setsck(struct spi_device *dev, int val) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ gpio_set_value(sp->info->pin_clk, val ? 1 : 0); ++} ++ ++static inline void setmosi(struct spi_device *dev, int val) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ gpio_set_value(sp->info->pin_mosi, val ? 1 : 0); ++} ++ ++static inline u32 getmiso(struct spi_device *dev) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ return gpio_get_value(sp->info->pin_miso) ? 1 : 0; ++} ++ ++static inline void do_spidelay(struct spi_device *dev, unsigned nsecs) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ ++ if (!sp->info->no_spi_delay) ++ ndelay(nsecs); ++} ++ ++#define spidelay(nsecs) do { \ ++ /* Steal the spi_device pointer from our caller. \ ++ * The bitbang-API should probably get fixed here... */ \ ++ do_spidelay(spi, nsecs); \ ++ } while (0) ++ ++#define EXPAND_BITBANG_TXRX ++#include "spi-bitbang-txrx.h" ++ ++static u32 spi_gpio_txrx_mode0(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode1(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode2(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); ++} ++ ++static u32 spi_gpio_txrx_mode3(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); ++} ++ ++static void spi_gpio_chipselect(struct spi_device *dev, int on) ++{ ++ struct spi_gpio *sp = spidev_to_sg(dev); ++ ++ if (sp->info->cs_activelow) ++ on = !on; ++ gpio_set_value(sp->info->pin_cs, on ? 1 : 0); ++} ++ ++static int spi_gpio_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct spi_gpio_platform_data *pdata; ++ struct spi_gpio *sp; ++ struct spi_device *spidev; ++ int err; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -ENXIO; ++ ++ err = -ENOMEM; ++ master = spi_alloc_master(&pdev->dev, sizeof(struct spi_gpio)); ++ if (!master) ++ goto err_alloc_master; ++ ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); ++ sp->info = pdata; ++ ++ err = gpio_request(pdata->pin_clk, "spi_clock"); ++ if (err) ++ goto err_request_clk; ++ err = gpio_request(pdata->pin_mosi, "spi_mosi"); ++ if (err) ++ goto err_request_mosi; ++ err = gpio_request(pdata->pin_miso, "spi_miso"); ++ if (err) ++ goto err_request_miso; ++ err = gpio_request(pdata->pin_cs, "spi_cs"); ++ if (err) ++ goto err_request_cs; ++ ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.master->bus_num = -1; ++ sp->bitbang.master->num_chipselect = 1; ++ sp->bitbang.chipselect = spi_gpio_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_txrx_mode0; ++ sp->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_txrx_mode1; ++ sp->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_txrx_mode2; ++ sp->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_txrx_mode3; ++ ++ gpio_direction_output(pdata->pin_clk, 0); ++ gpio_direction_output(pdata->pin_mosi, 0); ++ gpio_direction_output(pdata->pin_cs, ++ pdata->cs_activelow ? 1 : 0); ++ gpio_direction_input(pdata->pin_miso); ++ ++ err = spi_bitbang_start(&sp->bitbang); ++ if (err) ++ goto err_no_bitbang; ++ err = pdata->boardinfo_setup(&sp->bi, master, ++ pdata->boardinfo_setup_data); ++ if (err) ++ goto err_bi_setup; ++ sp->bi.controller_data = sp; ++ spidev = spi_new_device(master, &sp->bi); ++ if (!spidev) ++ goto err_new_dev; ++ ++ return 0; ++ ++err_new_dev: ++err_bi_setup: ++ spi_bitbang_stop(&sp->bitbang); ++err_no_bitbang: ++ spi_master_put(sp->bitbang.master); ++ gpio_free(pdata->pin_cs); ++err_request_cs: ++ gpio_free(pdata->pin_miso); ++err_request_miso: ++ gpio_free(pdata->pin_mosi); ++err_request_mosi: ++ gpio_free(pdata->pin_clk); ++err_request_clk: ++ kfree(master); ++ ++err_alloc_master: ++ return err; ++} ++ ++static int spi_gpio_remove(struct platform_device *pdev) ++{ ++ struct spi_gpio *sp; ++ struct spi_gpio_platform_data *pdata; ++ ++ pdata = pdev->dev.platform_data; ++ sp = platform_get_drvdata(pdev); ++ ++ gpio_free(pdata->pin_clk); ++ gpio_free(pdata->pin_mosi); ++ gpio_free(pdata->pin_miso); ++ gpio_free(pdata->pin_cs); ++ spi_bitbang_stop(&sp->bitbang); ++ spi_master_put(sp->bitbang.master); ++ ++ return 0; ++} ++ ++static struct platform_driver spi_gpio_driver = { ++ .driver = { ++ .name = SPI_GPIO_PLATDEV_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = spi_gpio_probe, ++ .remove = spi_gpio_remove, ++}; ++ ++int spi_gpio_next_id(void) ++{ ++ static atomic_t counter = ATOMIC_INIT(-1); ++ ++ return atomic_inc_return(&counter); ++} ++EXPORT_SYMBOL(spi_gpio_next_id); ++ ++static int __init spi_gpio_init(void) ++{ ++ int err; ++ ++ err = platform_driver_register(&spi_gpio_driver); ++ if (err) ++ printk(KERN_ERR "spi-gpio: register failed: %d\n", err); ++ ++ return err; ++} ++module_init(spi_gpio_init); ++ ++static void __exit spi_gpio_exit(void) ++{ ++ platform_driver_unregister(&spi_gpio_driver); ++} ++module_exit(spi_gpio_exit); ++ ++MODULE_AUTHOR("Piot Skamruk "); ++MODULE_AUTHOR("Michael Buesch"); ++MODULE_DESCRIPTION("Platform independent GPIO bitbanging SPI driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -243,6 +243,15 @@ config SPI_IMG_SPFI + This enables support for the SPFI master controller found on + IMG SoCs. + ++config SPI_GPIO_OLD ++ tristate "Old GPIO API based bitbanging SPI controller (DEPRECATED)" ++ depends on SPI_MASTER && GPIOLIB ++ select SPI_BITBANG ++ help ++ This code is deprecated. Please use the new mainline SPI-GPIO driver. ++ ++ If unsure, say N. ++ + config SPI_IMX + tristate "Freescale i.MX SPI controllers" + depends on ARCH_MXC || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -41,6 +41,7 @@ obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-li + obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o + obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o + obj-$(CONFIG_SPI_GPIO) += spi-gpio.o ++obj-$(CONFIG_SPI_GPIO_OLD) += spi_gpio_old.o + obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o + obj-$(CONFIG_SPI_IMX) += spi-imx.o + obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o diff --git a/target/linux/generic/patches-4.3/863-gpiommc.patch b/target/linux/generic/patches-4.3/863-gpiommc.patch new file mode 100644 index 0000000..8f786b9 --- /dev/null +++ b/target/linux/generic/patches-4.3/863-gpiommc.patch @@ -0,0 +1,844 @@ +--- /dev/null ++++ b/drivers/mmc/host/gpiommc.c +@@ -0,0 +1,609 @@ ++/* ++ * Driver an MMC/SD card on a bitbanging GPIO SPI bus. ++ * This module hooks up the mmc_spi and spi_gpio modules and also ++ * provides a configfs interface. ++ * ++ * Copyright 2008 Michael Buesch ++ * ++ * Licensed under the GNU/GPL. See COPYING for details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#define PFX "gpio-mmc: " ++ ++ ++struct gpiommc_device { ++ struct platform_device *pdev; ++ struct platform_device *spi_pdev; ++ struct spi_board_info boardinfo; ++}; ++ ++ ++MODULE_DESCRIPTION("GPIO based MMC driver"); ++MODULE_AUTHOR("Michael Buesch"); ++MODULE_LICENSE("GPL"); ++ ++ ++static int gpiommc_boardinfo_setup(struct spi_board_info *bi, ++ struct spi_master *master, ++ void *data) ++{ ++ struct gpiommc_device *d = data; ++ struct gpiommc_platform_data *pdata = d->pdev->dev.platform_data; ++ ++ /* Bind the SPI master to the MMC-SPI host driver. */ ++ strlcpy(bi->modalias, "mmc_spi", sizeof(bi->modalias)); ++ ++ bi->max_speed_hz = pdata->max_bus_speed; ++ bi->bus_num = master->bus_num; ++ bi->mode = pdata->mode; ++ ++ return 0; ++} ++ ++static int gpiommc_probe(struct platform_device *pdev) ++{ ++ struct gpiommc_platform_data *mmc_pdata = pdev->dev.platform_data; ++ struct spi_gpio_platform_data spi_pdata; ++ struct gpiommc_device *d; ++ int err; ++ ++ err = -ENXIO; ++ if (!mmc_pdata) ++ goto error; ++ ++#ifdef CONFIG_MMC_SPI_MODULE ++ err = request_module("mmc_spi"); ++ if (err) { ++ printk(KERN_WARNING PFX ++ "Failed to request mmc_spi module.\n"); ++ } ++#endif /* CONFIG_MMC_SPI_MODULE */ ++ ++ /* Allocate the GPIO-MMC device */ ++ err = -ENOMEM; ++ d = kzalloc(sizeof(*d), GFP_KERNEL); ++ if (!d) ++ goto error; ++ d->pdev = pdev; ++ ++ /* Create the SPI-GPIO device */ ++ d->spi_pdev = platform_device_alloc(SPI_GPIO_PLATDEV_NAME, ++ spi_gpio_next_id()); ++ if (!d->spi_pdev) ++ goto err_free_d; ++ ++ memset(&spi_pdata, 0, sizeof(spi_pdata)); ++ spi_pdata.pin_clk = mmc_pdata->pins.gpio_clk; ++ spi_pdata.pin_miso = mmc_pdata->pins.gpio_do; ++ spi_pdata.pin_mosi = mmc_pdata->pins.gpio_di; ++ spi_pdata.pin_cs = mmc_pdata->pins.gpio_cs; ++ spi_pdata.cs_activelow = mmc_pdata->pins.cs_activelow; ++ spi_pdata.no_spi_delay = mmc_pdata->no_spi_delay; ++ spi_pdata.boardinfo_setup = gpiommc_boardinfo_setup; ++ spi_pdata.boardinfo_setup_data = d; ++ ++ err = platform_device_add_data(d->spi_pdev, &spi_pdata, ++ sizeof(spi_pdata)); ++ if (err) ++ goto err_free_pdev; ++ err = platform_device_add(d->spi_pdev); ++ if (err) ++ goto err_free_pdata; ++ platform_set_drvdata(pdev, d); ++ ++ printk(KERN_INFO PFX "MMC-Card \"%s\" " ++ "attached to GPIO pins di=%u, do=%u, clk=%u, cs=%u\n", ++ mmc_pdata->name, mmc_pdata->pins.gpio_di, ++ mmc_pdata->pins.gpio_do, ++ mmc_pdata->pins.gpio_clk, ++ mmc_pdata->pins.gpio_cs); ++ ++ return 0; ++ ++err_free_pdata: ++ kfree(d->spi_pdev->dev.platform_data); ++ d->spi_pdev->dev.platform_data = NULL; ++err_free_pdev: ++ platform_device_put(d->spi_pdev); ++err_free_d: ++ kfree(d); ++error: ++ return err; ++} ++ ++static int gpiommc_remove(struct platform_device *pdev) ++{ ++ struct gpiommc_device *d = platform_get_drvdata(pdev); ++ struct gpiommc_platform_data *pdata = d->pdev->dev.platform_data; ++ ++ platform_device_unregister(d->spi_pdev); ++ printk(KERN_INFO PFX "GPIO based MMC-Card \"%s\" removed\n", ++ pdata->name); ++ platform_device_put(d->spi_pdev); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ ++/* A device that was created through configfs */ ++struct gpiommc_configfs_device { ++ struct config_item item; ++ /* The platform device, after registration. */ ++ struct platform_device *pdev; ++ /* The configuration */ ++ struct gpiommc_platform_data pdata; ++}; ++ ++#define GPIO_INVALID -1 ++ ++static inline bool gpiommc_is_registered(struct gpiommc_configfs_device *dev) ++{ ++ return (dev->pdev != NULL); ++} ++ ++static inline struct gpiommc_configfs_device *ci_to_gpiommc(struct config_item *item) ++{ ++ return item ? container_of(item, struct gpiommc_configfs_device, item) : NULL; ++} ++ ++static struct configfs_attribute gpiommc_attr_DI = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_data_in", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_DO = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_data_out", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CLK = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_clock", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CS = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_chipselect", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_CS_activelow = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "gpio_chipselect_activelow", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_spimode = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "spi_mode", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_spidelay = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "spi_delay", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_max_bus_speed = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "max_bus_speed", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute gpiommc_attr_register = { ++ .ca_owner = THIS_MODULE, ++ .ca_name = "register", ++ .ca_mode = S_IRUGO | S_IWUSR, ++}; ++ ++static struct configfs_attribute *gpiommc_config_attrs[] = { ++ &gpiommc_attr_DI, ++ &gpiommc_attr_DO, ++ &gpiommc_attr_CLK, ++ &gpiommc_attr_CS, ++ &gpiommc_attr_CS_activelow, ++ &gpiommc_attr_spimode, ++ &gpiommc_attr_spidelay, ++ &gpiommc_attr_max_bus_speed, ++ &gpiommc_attr_register, ++ NULL, ++}; ++ ++static ssize_t gpiommc_config_attr_show(struct config_item *item, ++ struct configfs_attribute *attr, ++ char *page) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ssize_t count = 0; ++ unsigned int gpio; ++ int err = 0; ++ ++ if (attr == &gpiommc_attr_DI) { ++ gpio = dev->pdata.pins.gpio_di; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_DO) { ++ gpio = dev->pdata.pins.gpio_do; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CLK) { ++ gpio = dev->pdata.pins.gpio_clk; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS) { ++ gpio = dev->pdata.pins.gpio_cs; ++ if (gpio == GPIO_INVALID) ++ count = snprintf(page, PAGE_SIZE, "not configured\n"); ++ else ++ count = snprintf(page, PAGE_SIZE, "%u\n", gpio); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS_activelow) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.pins.cs_activelow); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spimode) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.mode); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spidelay) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ !dev->pdata.no_spi_delay); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_max_bus_speed) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ dev->pdata.max_bus_speed); ++ goto out; ++ } ++ if (attr == &gpiommc_attr_register) { ++ count = snprintf(page, PAGE_SIZE, "%u\n", ++ gpiommc_is_registered(dev)); ++ goto out; ++ } ++ WARN_ON(1); ++ err = -ENOSYS; ++out: ++ return err ? err : count; ++} ++ ++static int gpiommc_do_register(struct gpiommc_configfs_device *dev, ++ const char *name) ++{ ++ int err; ++ ++ if (gpiommc_is_registered(dev)) ++ return 0; ++ ++ if (!gpio_is_valid(dev->pdata.pins.gpio_di) || ++ !gpio_is_valid(dev->pdata.pins.gpio_do) || ++ !gpio_is_valid(dev->pdata.pins.gpio_clk) || ++ !gpio_is_valid(dev->pdata.pins.gpio_cs)) { ++ printk(KERN_ERR PFX ++ "configfs: Invalid GPIO pin number(s)\n"); ++ return -EINVAL; ++ } ++ ++ strlcpy(dev->pdata.name, name, ++ sizeof(dev->pdata.name)); ++ ++ dev->pdev = platform_device_alloc(GPIOMMC_PLATDEV_NAME, ++ gpiommc_next_id()); ++ if (!dev->pdev) ++ return -ENOMEM; ++ err = platform_device_add_data(dev->pdev, &dev->pdata, ++ sizeof(dev->pdata)); ++ if (err) { ++ platform_device_put(dev->pdev); ++ return err; ++ } ++ err = platform_device_add(dev->pdev); ++ if (err) { ++ platform_device_put(dev->pdev); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static void gpiommc_do_unregister(struct gpiommc_configfs_device *dev) ++{ ++ if (!gpiommc_is_registered(dev)) ++ return; ++ ++ platform_device_unregister(dev->pdev); ++ dev->pdev = NULL; ++} ++ ++static ssize_t gpiommc_config_attr_store(struct config_item *item, ++ struct configfs_attribute *attr, ++ const char *page, size_t count) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ int err = -EINVAL; ++ unsigned long data; ++ ++ if (attr == &gpiommc_attr_register) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data == 1) ++ err = gpiommc_do_register(dev, item->ci_name); ++ if (data == 0) { ++ gpiommc_do_unregister(dev); ++ err = 0; ++ } ++ goto out; ++ } ++ ++ if (gpiommc_is_registered(dev)) { ++ /* The rest of the config parameters can only be set ++ * as long as the device is not registered, yet. */ ++ err = -EBUSY; ++ goto out; ++ } ++ ++ if (attr == &gpiommc_attr_DI) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_di = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_DO) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_do = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CLK) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_clk = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (!gpio_is_valid(data)) ++ goto out; ++ dev->pdata.pins.gpio_cs = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_CS_activelow) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data != 0 && data != 1) ++ goto out; ++ dev->pdata.pins.cs_activelow = data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spimode) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ switch (data) { ++ case 0: ++ dev->pdata.mode = SPI_MODE_0; ++ break; ++ case 1: ++ dev->pdata.mode = SPI_MODE_1; ++ break; ++ case 2: ++ dev->pdata.mode = SPI_MODE_2; ++ break; ++ case 3: ++ dev->pdata.mode = SPI_MODE_3; ++ break; ++ default: ++ goto out; ++ } ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_spidelay) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data != 0 && data != 1) ++ goto out; ++ dev->pdata.no_spi_delay = !data; ++ err = 0; ++ goto out; ++ } ++ if (attr == &gpiommc_attr_max_bus_speed) { ++ err = kstrtoul(page, 10, &data); ++ if (err) ++ goto out; ++ err = -EINVAL; ++ if (data > UINT_MAX) ++ goto out; ++ dev->pdata.max_bus_speed = data; ++ err = 0; ++ goto out; ++ } ++ WARN_ON(1); ++ err = -ENOSYS; ++out: ++ return err ? err : count; ++} ++ ++static void gpiommc_config_item_release(struct config_item *item) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ++ kfree(dev); ++} ++ ++static struct configfs_item_operations gpiommc_config_item_ops = { ++ .release = gpiommc_config_item_release, ++ .show_attribute = gpiommc_config_attr_show, ++ .store_attribute = gpiommc_config_attr_store, ++}; ++ ++static struct config_item_type gpiommc_dev_ci_type = { ++ .ct_item_ops = &gpiommc_config_item_ops, ++ .ct_attrs = gpiommc_config_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *gpiommc_make_item(struct config_group *group, ++ const char *name) ++{ ++ struct gpiommc_configfs_device *dev; ++ ++ if (strlen(name) > GPIOMMC_MAX_NAMELEN) { ++ printk(KERN_ERR PFX "configfs: device name too long\n"); ++ return NULL; ++ } ++ ++ dev = kzalloc(sizeof(*dev), GFP_KERNEL); ++ if (!dev) ++ return NULL; ++ ++ config_item_init_type_name(&dev->item, name, ++ &gpiommc_dev_ci_type); ++ ++ /* Assign default configuration */ ++ dev->pdata.pins.gpio_di = GPIO_INVALID; ++ dev->pdata.pins.gpio_do = GPIO_INVALID; ++ dev->pdata.pins.gpio_clk = GPIO_INVALID; ++ dev->pdata.pins.gpio_cs = GPIO_INVALID; ++ dev->pdata.pins.cs_activelow = 1; ++ dev->pdata.mode = SPI_MODE_0; ++ dev->pdata.no_spi_delay = 0; ++ dev->pdata.max_bus_speed = 5000000; /* 5 MHz */ ++ ++ return &(dev->item); ++} ++ ++static void gpiommc_drop_item(struct config_group *group, ++ struct config_item *item) ++{ ++ struct gpiommc_configfs_device *dev = ci_to_gpiommc(item); ++ ++ gpiommc_do_unregister(dev); ++ kfree(dev); ++} ++ ++static struct configfs_group_operations gpiommc_ct_group_ops = { ++ .make_item = gpiommc_make_item, ++ .drop_item = gpiommc_drop_item, ++}; ++ ++static struct config_item_type gpiommc_ci_type = { ++ .ct_group_ops = &gpiommc_ct_group_ops, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct configfs_subsystem gpiommc_subsys = { ++ .su_group = { ++ .cg_item = { ++ .ci_namebuf = GPIOMMC_PLATDEV_NAME, ++ .ci_type = &gpiommc_ci_type, ++ }, ++ }, ++ .su_mutex = __MUTEX_INITIALIZER(gpiommc_subsys.su_mutex), ++}; ++ ++#endif /* CONFIG_GPIOMMC_CONFIGFS */ ++ ++static struct platform_driver gpiommc_plat_driver = { ++ .probe = gpiommc_probe, ++ .remove = gpiommc_remove, ++ .driver = { ++ .name = GPIOMMC_PLATDEV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int gpiommc_next_id(void) ++{ ++ static atomic_t counter = ATOMIC_INIT(-1); ++ ++ return atomic_inc_return(&counter); ++} ++EXPORT_SYMBOL(gpiommc_next_id); ++ ++static int __init gpiommc_modinit(void) ++{ ++ int err; ++ ++ err = platform_driver_register(&gpiommc_plat_driver); ++ if (err) ++ return err; ++ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ config_group_init(&gpiommc_subsys.su_group); ++ err = configfs_register_subsystem(&gpiommc_subsys); ++ if (err) { ++ platform_driver_unregister(&gpiommc_plat_driver); ++ return err; ++ } ++#endif /* CONFIG_GPIOMMC_CONFIGFS */ ++ ++ return 0; ++} ++module_init(gpiommc_modinit); ++ ++static void __exit gpiommc_modexit(void) ++{ ++#ifdef CONFIG_GPIOMMC_CONFIGFS ++ configfs_unregister_subsystem(&gpiommc_subsys); ++#endif ++ platform_driver_unregister(&gpiommc_plat_driver); ++} ++module_exit(gpiommc_modexit); +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -565,6 +565,31 @@ config MMC_SDHI + This provides support for the SDHI SD/SDIO controller found in + SuperH and ARM SH-Mobile SoCs + ++config GPIOMMC ++ tristate "MMC/SD over GPIO-based SPI" ++ depends on MMC && MMC_SPI && SPI_GPIO_OLD ++ help ++ This driver hooks up the mmc_spi and spi_gpio modules so that ++ MMC/SD cards can be used on a GPIO based bus by bitbanging ++ the SPI protocol in software. ++ ++ This driver provides a configfs interface to dynamically create ++ and destroy GPIO-based MMC/SD card devices. It also provides ++ a platform device interface API. ++ See Documentation/gpiommc.txt for details. ++ ++ The module will be called gpiommc. ++ ++ If unsure, say N. ++ ++config GPIOMMC_CONFIGFS ++ bool ++ depends on GPIOMMC && CONFIGFS_FS ++ default y ++ help ++ This option automatically enables configfs support for gpiommc ++ if configfs is available. ++ + config MMC_CB710 + tristate "ENE CB710 MMC/SD Interface support" + depends on PCI +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -41,6 +41,7 @@ tmio_mmc_core-$(subst m,y,$(CONFIG_MMC_S + obj-$(CONFIG_MMC_SDHI) += sh_mobile_sdhi.o + obj-$(CONFIG_MMC_CB710) += cb710-mmc.o + obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o ++obj-$(CONFIG_GPIOMMC) += gpiommc.o + obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o + obj-$(CONFIG_MMC_DW) += dw_mmc.o + obj-$(CONFIG_MMC_DW_PLTFM) += dw_mmc-pltfm.o +--- /dev/null ++++ b/include/linux/mmc/gpiommc.h +@@ -0,0 +1,71 @@ ++/* ++ * Device driver for MMC/SD cards driven over a GPIO bus. ++ * ++ * Copyright (c) 2008 Michael Buesch ++ * ++ * Licensed under the GNU/GPL version 2. ++ */ ++#ifndef LINUX_GPIOMMC_H_ ++#define LINUX_GPIOMMC_H_ ++ ++#include ++ ++ ++#define GPIOMMC_MAX_NAMELEN 15 ++#define GPIOMMC_MAX_NAMELEN_STR __stringify(GPIOMMC_MAX_NAMELEN) ++ ++/** ++ * struct gpiommc_pins - Hardware pin assignments ++ * ++ * @gpio_di: The GPIO number of the DATA IN pin ++ * @gpio_do: The GPIO number of the DATA OUT pin ++ * @gpio_clk: The GPIO number of the CLOCK pin ++ * @gpio_cs: The GPIO number of the CHIPSELECT pin ++ * @cs_activelow: If true, the chip is considered selected if @gpio_cs is low. ++ */ ++struct gpiommc_pins { ++ unsigned int gpio_di; ++ unsigned int gpio_do; ++ unsigned int gpio_clk; ++ unsigned int gpio_cs; ++ bool cs_activelow; ++}; ++ ++/** ++ * struct gpiommc_platform_data - Platform data for a MMC-over-SPI-GPIO device. ++ * ++ * @name: The unique name string of the device. ++ * @pins: The hardware pin assignments. ++ * @mode: The hardware mode. This is either SPI_MODE_0, ++ * SPI_MODE_1, SPI_MODE_2 or SPI_MODE_3. See the SPI documentation. ++ * @no_spi_delay: Do not use delays in the lowlevel SPI bitbanging code. ++ * This is not standards compliant, but may be required for some ++ * embedded machines to gain reasonable speed. ++ * @max_bus_speed: The maximum speed of the SPI bus, in Hertz. ++ */ ++struct gpiommc_platform_data { ++ char name[GPIOMMC_MAX_NAMELEN + 1]; ++ struct gpiommc_pins pins; ++ u8 mode; ++ bool no_spi_delay; ++ unsigned int max_bus_speed; ++}; ++ ++/** ++ * GPIOMMC_PLATDEV_NAME - The platform device name string. ++ * ++ * The name string that has to be used for platform_device_alloc ++ * when allocating a gpiommc device. ++ */ ++#define GPIOMMC_PLATDEV_NAME "gpiommc" ++ ++/** ++ * gpiommc_next_id - Get another platform device ID number. ++ * ++ * This returns the next platform device ID number that has to be used ++ * for platform_device_alloc. The ID is opaque and should not be used for ++ * anything else. ++ */ ++int gpiommc_next_id(void); ++ ++#endif /* LINUX_GPIOMMC_H_ */ +--- /dev/null ++++ b/Documentation/gpiommc.txt +@@ -0,0 +1,97 @@ ++GPIOMMC - Driver for an MMC/SD card on a bitbanging GPIO SPI bus ++================================================================ ++ ++The gpiommc module hooks up the mmc_spi and spi_gpio modules for running an ++MMC or SD card on GPIO pins. ++ ++Two interfaces for registering a new MMC/SD card device are provided: ++A static platform-device based mechanism and a dynamic configfs based interface. ++ ++ ++Registering devices via platform-device ++======================================= ++ ++The platform-device interface is used for registering MMC/SD devices that are ++part of the hardware platform. This is most useful only for embedded machines ++with MMC/SD devices statically connected to the platform GPIO bus. ++ ++The data structures are declared in . ++ ++To register a new device, define an instance of struct gpiommc_platform_data. ++This structure holds any information about how the device is hooked up to the ++GPIO pins and what hardware modes the device supports. See the docbook-style ++documentation in the header file for more information on the struct fields. ++ ++Then allocate a new instance of a platform device by doing: ++ ++ pdev = platform_device_alloc(GPIOMMC_PLATDEV_NAME, gpiommc_next_id()); ++ ++This will allocate the platform device data structures and hook it up to the ++gpiommc driver. ++Then add the gpiommc_platform_data to the platform device. ++ ++ err = platform_device_add_data(pdev, pdata, sizeof(struct gpiommc_platform_data)); ++ ++You may free the local instance of struct gpiommc_platform_data now. (So the ++struct may be allocated on the stack, too). ++Now simply register the platform device. ++ ++ err = platform_device_add(pdev); ++ ++Done. The gpiommc probe routine will be invoked now and you should see a kernel ++log message for the added device. ++ ++ ++Registering devices via configfs ++================================ ++ ++MMC/SD cards connected via GPIO often are a pretty dynamic thing, as for example ++selfmade hacks for soldering an MMC/SD card to standard GPIO pins on embedded ++hardware are a common situation. ++So we provide a dynamic interface to conveniently handle adding and removing ++devices from userspace, without the need to recompile the kernel. ++ ++The "gpiommc" subdirectory at the configfs mountpoint is used for handling ++the dynamic configuration. ++ ++To create a new device, it must first be allocated with mkdir. ++The following command will allocate a device named "my_mmc": ++ mkdir /config/gpiommc/my_mmc ++ ++There are several configuration files available in the new ++/config/gpiommc/my_mmc/ directory: ++ ++gpio_data_in = The SPI data-IN GPIO pin number. ++gpio_data_out = The SPI data-OUT GPIO pin number. ++gpio_clock = The SPI Clock GPIO pin number. ++gpio_chipselect = The SPI Chipselect GPIO pin number. ++gpio_chipselect_activelow = Boolean. If 0, Chipselect is active-HIGH. ++ If 1, Chipselect is active-LOW. ++spi_mode = The SPI data mode. Can be 0-3. ++spi_delay = Enable all delays in the lowlevel bitbanging. ++max_bus_speed = The maximum SPI bus speed. In Hertz. ++ ++register = Not a configuration parameter. ++ Used to register the configured card ++ with the kernel. ++ ++The device must first get configured and then registered by writing "1" to ++the "register" file. ++The configuration parameters "gpio_data_in", "gpio_data_out", "gpio_clock" ++and "gpio_chipselect" are essential and _must_ be configured before writing ++"1" to the "register" file. The registration will fail, otherwise. ++ ++The default values for the other parameters are: ++gpio_chipselect_activelow = 1 (CS active-LOW) ++spi_mode = 0 (SPI_MODE_0) ++spi_delay = 1 (enabled) ++max_bus_speed = 5000000 (5 Mhz) ++ ++Configuration values can not be changed after registration. To unregister ++the device, write a "0" to the "register" file. The configuration can be ++changed again after unregistering. ++ ++To completely remove the device, simply rmdir the directory ++(/config/gpiommc/my_mmc in this example). ++There's no need to first unregister the device before removing it. That will ++be done automatically. +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -4792,6 +4792,11 @@ T: git git://linuxtv.org/anttip/media_tr + S: Maintained + F: drivers/media/usb/hackrf/ + ++GPIOMMC DRIVER ++P: Michael Buesch ++M: mb@bu3sch.de ++S: Maintained ++ + HARDWARE MONITORING + M: Jean Delvare + M: Guenter Roeck diff --git a/target/linux/generic/patches-4.3/864-gpiommc_configfs_locking.patch b/target/linux/generic/patches-4.3/864-gpiommc_configfs_locking.patch new file mode 100644 index 0000000..92815d9 --- /dev/null +++ b/target/linux/generic/patches-4.3/864-gpiommc_configfs_locking.patch @@ -0,0 +1,58 @@ +The gpiommc configfs context structure needs locking, as configfs +does not lock access between files. + +--- a/drivers/mmc/host/gpiommc.c ++++ b/drivers/mmc/host/gpiommc.c +@@ -144,6 +144,8 @@ struct gpiommc_configfs_device { + struct platform_device *pdev; + /* The configuration */ + struct gpiommc_platform_data pdata; ++ /* Mutex to protect this structure */ ++ struct mutex mutex; + }; + + #define GPIO_INVALID -1 +@@ -234,6 +236,8 @@ static ssize_t gpiommc_config_attr_show( + unsigned int gpio; + int err = 0; + ++ mutex_lock(&dev->mutex); ++ + if (attr == &gpiommc_attr_DI) { + gpio = dev->pdata.pins.gpio_di; + if (gpio == GPIO_INVALID) +@@ -294,6 +298,8 @@ static ssize_t gpiommc_config_attr_show( + WARN_ON(1); + err = -ENOSYS; + out: ++ mutex_unlock(&dev->mutex); ++ + return err ? err : count; + } + +@@ -353,6 +359,8 @@ static ssize_t gpiommc_config_attr_store + int err = -EINVAL; + unsigned long data; + ++ mutex_lock(&dev->mutex); ++ + if (attr == &gpiommc_attr_register) { + err = kstrtoul(page, 10, &data); + if (err) +@@ -478,6 +486,8 @@ static ssize_t gpiommc_config_attr_store + WARN_ON(1); + err = -ENOSYS; + out: ++ mutex_unlock(&dev->mutex); ++ + return err ? err : count; + } + +@@ -514,6 +524,7 @@ static struct config_item *gpiommc_make_ + if (!dev) + return NULL; + ++ mutex_init(&dev->mutex); + config_item_init_type_name(&dev->item, name, + &gpiommc_dev_ci_type); + diff --git a/target/linux/generic/patches-4.3/870-hifn795x_byteswap.patch b/target/linux/generic/patches-4.3/870-hifn795x_byteswap.patch new file mode 100644 index 0000000..3a37c95 --- /dev/null +++ b/target/linux/generic/patches-4.3/870-hifn795x_byteswap.patch @@ -0,0 +1,17 @@ +--- a/drivers/crypto/hifn_795x.c ++++ b/drivers/crypto/hifn_795x.c +@@ -682,12 +682,12 @@ static inline u32 hifn_read_1(struct hif + + static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) + { +- writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); ++ writel(val, dev->bar[0] + reg); + } + + static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) + { +- writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); ++ writel(val, dev->bar[1] + reg); + } + + static void hifn_wait_puc(struct hifn_device *dev) diff --git a/target/linux/generic/patches-4.3/880-gateworks_system_controller.patch b/target/linux/generic/patches-4.3/880-gateworks_system_controller.patch new file mode 100644 index 0000000..2a9936b --- /dev/null +++ b/target/linux/generic/patches-4.3/880-gateworks_system_controller.patch @@ -0,0 +1,339 @@ +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -518,6 +518,15 @@ config SENSORS_G762 + This driver can also be built as a module. If so, the module + will be called g762. + ++config SENSORS_GSC ++ tristate "Gateworks System Controller" ++ depends on I2C ++ help ++ If you say yes here you get support for the Gateworks System Controller. ++ ++ This driver can also be built as a module. If so, the module ++ will be called gsc. ++ + config SENSORS_GPIO_FAN + tristate "GPIO fan" + depends on GPIOLIB || COMPILE_TEST +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -158,6 +158,7 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l7 + obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o + obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o + obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o ++obj-$(CONFIG_SENSORS_GSC) += gsc.o + + obj-$(CONFIG_PMBUS) += pmbus/ + +--- /dev/null ++++ b/drivers/hwmon/gsc.c +@@ -0,0 +1,308 @@ ++/* ++ * A hwmon driver for the Gateworks System Controller ++ * Copyright (C) 2009 Gateworks Corporation ++ * ++ * Author: Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License, ++ * as published by the Free Software Foundation - version 2. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRV_VERSION "0.2" ++ ++enum chips { gsp }; ++ ++/* AD7418 registers */ ++#define GSP_REG_TEMP_IN 0x00 ++#define GSP_REG_VIN 0x02 ++#define GSP_REG_3P3 0x05 ++#define GSP_REG_BAT 0x08 ++#define GSP_REG_5P0 0x0b ++#define GSP_REG_CORE 0x0e ++#define GSP_REG_CPU1 0x11 ++#define GSP_REG_CPU2 0x14 ++#define GSP_REG_DRAM 0x17 ++#define GSP_REG_EXT_BAT 0x1a ++#define GSP_REG_IO1 0x1d ++#define GSP_REG_IO2 0x20 ++#define GSP_REG_PCIE 0x23 ++#define GSP_REG_CURRENT 0x26 ++#define GSP_FAN_0 0x2C ++#define GSP_FAN_1 0x2E ++#define GSP_FAN_2 0x30 ++#define GSP_FAN_3 0x32 ++#define GSP_FAN_4 0x34 ++#define GSP_FAN_5 0x36 ++ ++struct gsp_sensor_info { ++ const char* name; ++ int reg; ++}; ++ ++static const struct gsp_sensor_info gsp_sensors[] = { ++ {"temp", GSP_REG_TEMP_IN}, ++ {"vin", GSP_REG_VIN}, ++ {"3p3", GSP_REG_3P3}, ++ {"bat", GSP_REG_BAT}, ++ {"5p0", GSP_REG_5P0}, ++ {"core", GSP_REG_CORE}, ++ {"cpu1", GSP_REG_CPU1}, ++ {"cpu2", GSP_REG_CPU2}, ++ {"dram", GSP_REG_DRAM}, ++ {"ext_bat", GSP_REG_EXT_BAT}, ++ {"io1", GSP_REG_IO1}, ++ {"io2", GSP_REG_IO2}, ++ {"pci2", GSP_REG_PCIE}, ++ {"current", GSP_REG_CURRENT}, ++ {"fan_point0", GSP_FAN_0}, ++ {"fan_point1", GSP_FAN_1}, ++ {"fan_point2", GSP_FAN_2}, ++ {"fan_point3", GSP_FAN_3}, ++ {"fan_point4", GSP_FAN_4}, ++ {"fan_point5", GSP_FAN_5}, ++}; ++ ++struct gsp_data { ++ struct device *hwmon_dev; ++ struct attribute_group attrs; ++ enum chips type; ++}; ++ ++static int gsp_probe(struct i2c_client *client, ++ const struct i2c_device_id *id); ++static int gsp_remove(struct i2c_client *client); ++ ++static const struct i2c_device_id gsp_id[] = { ++ { "gsp", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, gsp_id); ++ ++static struct i2c_driver gsp_driver = { ++ .driver = { ++ .name = "gsp", ++ }, ++ .probe = gsp_probe, ++ .remove = gsp_remove, ++ .id_table = gsp_id, ++}; ++ ++/* All registers are word-sized, except for the configuration registers. ++ * AD7418 uses a high-byte first convention. Do NOT use those functions to ++ * access the configuration registers CONF and CONF2, as they are byte-sized. ++ */ ++static inline int gsp_read(struct i2c_client *client, u8 reg) ++{ ++ unsigned int adc = 0; ++ if (reg == GSP_REG_TEMP_IN || reg > GSP_REG_CURRENT) ++ { ++ adc |= i2c_smbus_read_byte_data(client, reg); ++ adc |= i2c_smbus_read_byte_data(client, reg + 1) << 8; ++ return adc; ++ } ++ else ++ { ++ adc |= i2c_smbus_read_byte_data(client, reg); ++ adc |= i2c_smbus_read_byte_data(client, reg + 1) << 8; ++ adc |= i2c_smbus_read_byte_data(client, reg + 2) << 16; ++ return adc; ++ } ++} ++ ++static inline int gsp_write(struct i2c_client *client, u8 reg, u16 value) ++{ ++ i2c_smbus_write_byte_data(client, reg, value & 0xff); ++ i2c_smbus_write_byte_data(client, reg + 1, ((value >> 8) & 0xff)); ++ return 1; ++} ++ ++static ssize_t show_adc(struct device *dev, struct device_attribute *devattr, ++ char *buf) ++{ ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ struct i2c_client *client = to_i2c_client(dev); ++ return sprintf(buf, "%d\n", gsp_read(client, gsp_sensors[attr->index].reg)); ++} ++ ++static ssize_t show_label(struct device *dev, ++ struct device_attribute *devattr, char *buf) ++{ ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ ++ return sprintf(buf, "%s\n", gsp_sensors[attr->index].name); ++} ++ ++static ssize_t store_fan(struct device *dev, ++ struct device_attribute *devattr, const char *buf, size_t count) ++{ ++ u16 val; ++ struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); ++ struct i2c_client *client = to_i2c_client(dev); ++ val = simple_strtoul(buf, NULL, 10); ++ gsp_write(client, gsp_sensors[attr->index].reg, val); ++ return count; ++} ++ ++static SENSOR_DEVICE_ATTR(temp0_input, S_IRUGO, show_adc, NULL, 0); ++static SENSOR_DEVICE_ATTR(temp0_label, S_IRUGO, show_label, NULL, 0); ++ ++static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, show_adc, NULL, 1); ++static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, show_label, NULL, 1); ++static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, show_adc, NULL, 2); ++static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, show_label, NULL, 2); ++static SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, show_adc, NULL, 3); ++static SENSOR_DEVICE_ATTR(in2_label, S_IRUGO, show_label, NULL, 3); ++static SENSOR_DEVICE_ATTR(in3_input, S_IRUGO, show_adc, NULL, 4); ++static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 4); ++static SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, show_adc, NULL, 5); ++static SENSOR_DEVICE_ATTR(in4_label, S_IRUGO, show_label, NULL, 5); ++static SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, show_adc, NULL, 6); ++static SENSOR_DEVICE_ATTR(in5_label, S_IRUGO, show_label, NULL, 6); ++static SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, show_adc, NULL, 7); ++static SENSOR_DEVICE_ATTR(in6_label, S_IRUGO, show_label, NULL, 7); ++static SENSOR_DEVICE_ATTR(in7_input, S_IRUGO, show_adc, NULL, 8); ++static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 8); ++static SENSOR_DEVICE_ATTR(in8_input, S_IRUGO, show_adc, NULL, 9); ++static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 9); ++static SENSOR_DEVICE_ATTR(in9_input, S_IRUGO, show_adc, NULL, 10); ++static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 10); ++static SENSOR_DEVICE_ATTR(in10_input, S_IRUGO, show_adc, NULL, 11); ++static SENSOR_DEVICE_ATTR(in10_label, S_IRUGO, show_label, NULL, 11); ++static SENSOR_DEVICE_ATTR(in11_input, S_IRUGO, show_adc, NULL, 12); ++static SENSOR_DEVICE_ATTR(in11_label, S_IRUGO, show_label, NULL, 12); ++static SENSOR_DEVICE_ATTR(in12_input, S_IRUGO, show_adc, NULL, 13); ++static SENSOR_DEVICE_ATTR(in12_label, S_IRUGO, show_label, NULL, 13); ++ ++static SENSOR_DEVICE_ATTR(fan0_point0, S_IRUGO | S_IWUSR, show_adc, store_fan, 14); ++static SENSOR_DEVICE_ATTR(fan0_point1, S_IRUGO | S_IWUSR, show_adc, store_fan, 15); ++static SENSOR_DEVICE_ATTR(fan0_point2, S_IRUGO | S_IWUSR, show_adc, store_fan, 16); ++static SENSOR_DEVICE_ATTR(fan0_point3, S_IRUGO | S_IWUSR, show_adc, store_fan, 17); ++static SENSOR_DEVICE_ATTR(fan0_point4, S_IRUGO | S_IWUSR, show_adc, store_fan, 18); ++static SENSOR_DEVICE_ATTR(fan0_point5, S_IRUGO | S_IWUSR, show_adc, store_fan, 19); ++ ++static struct attribute *gsp_attributes[] = { ++ &sensor_dev_attr_temp0_input.dev_attr.attr, ++ &sensor_dev_attr_in0_input.dev_attr.attr, ++ &sensor_dev_attr_in1_input.dev_attr.attr, ++ &sensor_dev_attr_in2_input.dev_attr.attr, ++ &sensor_dev_attr_in3_input.dev_attr.attr, ++ &sensor_dev_attr_in4_input.dev_attr.attr, ++ &sensor_dev_attr_in5_input.dev_attr.attr, ++ &sensor_dev_attr_in6_input.dev_attr.attr, ++ &sensor_dev_attr_in7_input.dev_attr.attr, ++ &sensor_dev_attr_in8_input.dev_attr.attr, ++ &sensor_dev_attr_in9_input.dev_attr.attr, ++ &sensor_dev_attr_in10_input.dev_attr.attr, ++ &sensor_dev_attr_in11_input.dev_attr.attr, ++ &sensor_dev_attr_in12_input.dev_attr.attr, ++ ++ &sensor_dev_attr_temp0_label.dev_attr.attr, ++ &sensor_dev_attr_in0_label.dev_attr.attr, ++ &sensor_dev_attr_in1_label.dev_attr.attr, ++ &sensor_dev_attr_in2_label.dev_attr.attr, ++ &sensor_dev_attr_in3_label.dev_attr.attr, ++ &sensor_dev_attr_in4_label.dev_attr.attr, ++ &sensor_dev_attr_in5_label.dev_attr.attr, ++ &sensor_dev_attr_in6_label.dev_attr.attr, ++ &sensor_dev_attr_in7_label.dev_attr.attr, ++ &sensor_dev_attr_in8_label.dev_attr.attr, ++ &sensor_dev_attr_in9_label.dev_attr.attr, ++ &sensor_dev_attr_in10_label.dev_attr.attr, ++ &sensor_dev_attr_in11_label.dev_attr.attr, ++ &sensor_dev_attr_in12_label.dev_attr.attr, ++ ++ &sensor_dev_attr_fan0_point0.dev_attr.attr, ++ &sensor_dev_attr_fan0_point1.dev_attr.attr, ++ &sensor_dev_attr_fan0_point2.dev_attr.attr, ++ &sensor_dev_attr_fan0_point3.dev_attr.attr, ++ &sensor_dev_attr_fan0_point4.dev_attr.attr, ++ &sensor_dev_attr_fan0_point5.dev_attr.attr, ++ NULL ++}; ++ ++ ++static int gsp_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct i2c_adapter *adapter = client->adapter; ++ struct gsp_data *data; ++ int err; ++ ++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | ++ I2C_FUNC_SMBUS_WORD_DATA)) { ++ err = -EOPNOTSUPP; ++ goto exit; ++ } ++ ++ if (!(data = kzalloc(sizeof(struct gsp_data), GFP_KERNEL))) { ++ err = -ENOMEM; ++ goto exit; ++ } ++ ++ i2c_set_clientdata(client, data); ++ ++ data->type = id->driver_data; ++ ++ switch (data->type) { ++ case 0: ++ data->attrs.attrs = gsp_attributes; ++ break; ++ } ++ ++ dev_info(&client->dev, "%s chip found\n", client->name); ++ ++ /* Register sysfs hooks */ ++ if ((err = sysfs_create_group(&client->dev.kobj, &data->attrs))) ++ goto exit_free; ++ ++ data->hwmon_dev = hwmon_device_register(&client->dev); ++ if (IS_ERR(data->hwmon_dev)) { ++ err = PTR_ERR(data->hwmon_dev); ++ goto exit_remove; ++ } ++ ++ return 0; ++ ++exit_remove: ++ sysfs_remove_group(&client->dev.kobj, &data->attrs); ++exit_free: ++ kfree(data); ++exit: ++ return err; ++} ++ ++static int gsp_remove(struct i2c_client *client) ++{ ++ struct gsp_data *data = i2c_get_clientdata(client); ++ hwmon_device_unregister(data->hwmon_dev); ++ sysfs_remove_group(&client->dev.kobj, &data->attrs); ++ kfree(data); ++ return 0; ++} ++ ++static int __init gsp_init(void) ++{ ++ return i2c_add_driver(&gsp_driver); ++} ++ ++static void __exit gsp_exit(void) ++{ ++ i2c_del_driver(&gsp_driver); ++} ++ ++module_init(gsp_init); ++module_exit(gsp_exit); ++ ++MODULE_AUTHOR("Chris Lang "); ++MODULE_DESCRIPTION("GSC HWMON driver"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); ++ diff --git a/target/linux/generic/patches-4.3/890-8250_optional_sysrq.patch b/target/linux/generic/patches-4.3/890-8250_optional_sysrq.patch new file mode 100644 index 0000000..525a7b9 --- /dev/null +++ b/target/linux/generic/patches-4.3/890-8250_optional_sysrq.patch @@ -0,0 +1,24 @@ +--- a/drivers/tty/serial/8250/8250_port.c ++++ b/drivers/tty/serial/8250/8250_port.c +@@ -15,7 +15,7 @@ + * membase is an 'ioremapped' cookie. + */ + +-#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) ++#if defined(CONFIG_SERIAL_8250_SYSRQ) && defined(CONFIG_MAGIC_SYSRQ) + #define SUPPORT_SYSRQ + #endif + +--- a/drivers/tty/serial/8250/Kconfig ++++ b/drivers/tty/serial/8250/Kconfig +@@ -91,6 +91,10 @@ config SERIAL_8250_CONSOLE + + If unsure, say N. + ++config SERIAL_8250_SYSRQ ++ bool "Magic sysrq support on 8250/16550 devices" ++ depends on SERIAL_8250_CONSOLE ++ + config SERIAL_8250_GSC + tristate + depends on SERIAL_8250 && GSC diff --git a/target/linux/generic/patches-4.3/900-slab_maxsize.patch b/target/linux/generic/patches-4.3/900-slab_maxsize.patch new file mode 100644 index 0000000..10133f2 --- /dev/null +++ b/target/linux/generic/patches-4.3/900-slab_maxsize.patch @@ -0,0 +1,13 @@ +--- a/include/linux/slab.h ++++ b/include/linux/slab.h +@@ -171,8 +171,8 @@ size_t ksize(const void *); + * to do various tricks to work around compiler limitations in order to + * ensure proper constant folding. + */ +-#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 25 ? \ +- (MAX_ORDER + PAGE_SHIFT - 1) : 25) ++#define KMALLOC_SHIFT_HIGH ((MAX_ORDER + PAGE_SHIFT - 1) <= 17 ? \ ++ (MAX_ORDER + PAGE_SHIFT - 1) : 17) + #define KMALLOC_SHIFT_MAX KMALLOC_SHIFT_HIGH + #ifndef KMALLOC_SHIFT_LOW + #define KMALLOC_SHIFT_LOW 5 diff --git a/target/linux/generic/patches-4.3/901-debloat_sock_diag.patch b/target/linux/generic/patches-4.3/901-debloat_sock_diag.patch new file mode 100644 index 0000000..bf03c39 --- /dev/null +++ b/target/linux/generic/patches-4.3/901-debloat_sock_diag.patch @@ -0,0 +1,79 @@ +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -92,6 +92,9 @@ source "net/netlabel/Kconfig" + + endif # if INET + ++config SOCK_DIAG ++ bool ++ + config NETWORK_SECMARK + bool "Security Marking" + help +--- a/net/core/Makefile ++++ b/net/core/Makefile +@@ -9,8 +9,9 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core. + + obj-y += dev.o ethtool.o dev_addr_lists.o dst.o netevent.o \ + neighbour.o rtnetlink.o utils.o link_watch.o filter.o \ +- sock_diag.o dev_ioctl.o tso.o ++ dev_ioctl.o tso.o + ++obj-$(CONFIG_SOCK_DIAG) += sock_diag.o + obj-$(CONFIG_XFRM) += flow.o + obj-y += net-sysfs.o + obj-$(CONFIG_PROC_FS) += net-procfs.o +--- a/net/core/sock.c ++++ b/net/core/sock.c +@@ -1454,9 +1454,11 @@ void sk_destruct(struct sock *sk) + + static void __sk_free(struct sock *sk) + { ++#ifdef CONFIG_SOCK_DIAG + if (unlikely(sock_diag_has_destroy_listeners(sk) && sk->sk_net_refcnt)) + sock_diag_broadcast_destroy(sk); + else ++#endif + sk_destruct(sk); + } + +--- a/net/ipv4/Kconfig ++++ b/net/ipv4/Kconfig +@@ -414,6 +414,7 @@ config INET_LRO + + config INET_DIAG + tristate "INET: socket monitoring interface" ++ select SOCK_DIAG + default y + ---help--- + Support for INET (TCP, DCCP, etc) socket monitoring interface used by +--- a/net/unix/Kconfig ++++ b/net/unix/Kconfig +@@ -22,6 +22,7 @@ config UNIX + config UNIX_DIAG + tristate "UNIX: socket monitoring interface" + depends on UNIX ++ select SOCK_DIAG + default n + ---help--- + Support for UNIX socket monitoring interface used by the ss tool. +--- a/net/netlink/Kconfig ++++ b/net/netlink/Kconfig +@@ -13,6 +13,7 @@ config NETLINK_MMAP + + config NETLINK_DIAG + tristate "NETLINK: socket monitoring interface" ++ select SOCK_DIAG + default n + ---help--- + Support for NETLINK socket monitoring interface used by the ss tool. +--- a/net/packet/Kconfig ++++ b/net/packet/Kconfig +@@ -18,6 +18,7 @@ config PACKET + config PACKET_DIAG + tristate "Packet: sockets monitoring interface" + depends on PACKET ++ select SOCK_DIAG + default n + ---help--- + Support for PF_PACKET sockets monitoring interface used by the ss tool. diff --git a/target/linux/generic/patches-4.3/902-debloat_proc.patch b/target/linux/generic/patches-4.3/902-debloat_proc.patch new file mode 100644 index 0000000..0d409b6 --- /dev/null +++ b/target/linux/generic/patches-4.3/902-debloat_proc.patch @@ -0,0 +1,341 @@ +--- a/fs/locks.c ++++ b/fs/locks.c +@@ -2675,6 +2675,8 @@ static const struct file_operations proc + + static int __init proc_locks_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("locks", 0, NULL, &proc_locks_operations); + return 0; + } +--- a/fs/proc/Kconfig ++++ b/fs/proc/Kconfig +@@ -81,3 +81,8 @@ config PROC_CHILDREN + + Say Y if you are running any user-space software which takes benefit from + this interface. For example, rkt is such a piece of software. ++ ++config PROC_STRIPPED ++ default n ++ depends on EXPERT ++ bool "Strip non-essential /proc functionality to reduce code size" +--- a/fs/proc/consoles.c ++++ b/fs/proc/consoles.c +@@ -106,6 +106,9 @@ static const struct file_operations proc + + static int __init proc_consoles_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + proc_create("consoles", 0, NULL, &proc_consoles_operations); + return 0; + } +--- a/fs/proc/proc_tty.c ++++ b/fs/proc/proc_tty.c +@@ -143,7 +143,10 @@ static const struct file_operations proc + void proc_tty_register_driver(struct tty_driver *driver) + { + struct proc_dir_entry *ent; +- ++ ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (!driver->driver_name || driver->proc_entry || + !driver->ops->proc_fops) + return; +@@ -160,6 +163,9 @@ void proc_tty_unregister_driver(struct t + { + struct proc_dir_entry *ent; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + ent = driver->proc_entry; + if (!ent) + return; +@@ -174,6 +180,9 @@ void proc_tty_unregister_driver(struct t + */ + void __init proc_tty_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (!proc_mkdir("tty", NULL)) + return; + proc_mkdir("tty/ldisc", NULL); /* Preserved: it's userspace visible */ +--- a/kernel/exec_domain.c ++++ b/kernel/exec_domain.c +@@ -41,6 +41,8 @@ static const struct file_operations exec + + static int __init proc_execdomains_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("execdomains", 0, NULL, &execdomains_proc_fops); + return 0; + } +--- a/kernel/irq/proc.c ++++ b/kernel/irq/proc.c +@@ -327,6 +327,9 @@ void register_irq_proc(unsigned int irq, + static DEFINE_MUTEX(register_lock); + char name [MAX_NAMELEN]; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + if (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip)) + return; + +@@ -376,6 +379,9 @@ void unregister_irq_proc(unsigned int ir + { + char name [MAX_NAMELEN]; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + if (!root_irq_dir || !desc->dir) + return; + #ifdef CONFIG_SMP +@@ -411,6 +417,9 @@ void init_irq_proc(void) + unsigned int irq; + struct irq_desc *desc; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) ++ return; ++ + /* create /proc/irq */ + root_irq_dir = proc_mkdir("irq", NULL); + if (!root_irq_dir) +--- a/kernel/time/timer_list.c ++++ b/kernel/time/timer_list.c +@@ -393,6 +393,8 @@ static int __init init_timer_list_procfs + { + struct proc_dir_entry *pe; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + pe = proc_create("timer_list", 0444, NULL, &timer_list_fops); + if (!pe) + return -ENOMEM; +--- a/mm/vmalloc.c ++++ b/mm/vmalloc.c +@@ -2683,6 +2683,8 @@ static const struct file_operations proc + + static int __init proc_vmalloc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + proc_create("vmallocinfo", S_IRUSR, NULL, &proc_vmalloc_operations); + return 0; + } +--- a/mm/vmstat.c ++++ b/mm/vmstat.c +@@ -1529,10 +1529,12 @@ static int __init setup_vmstat(void) + cpu_notifier_register_done(); + #endif + #ifdef CONFIG_PROC_FS +- proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations); +- proc_create("pagetypeinfo", S_IRUGO, NULL, &pagetypeinfo_file_ops); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations); ++ proc_create("pagetypeinfo", S_IRUGO, NULL, &pagetypeinfo_file_ops); ++ proc_create("zoneinfo", S_IRUGO, NULL, &proc_zoneinfo_file_operations); ++ } + proc_create("vmstat", S_IRUGO, NULL, &proc_vmstat_file_operations); +- proc_create("zoneinfo", S_IRUGO, NULL, &proc_zoneinfo_file_operations); + #endif + return 0; + } +--- a/net/8021q/vlanproc.c ++++ b/net/8021q/vlanproc.c +@@ -127,6 +127,9 @@ void vlan_proc_cleanup(struct net *net) + { + struct vlan_net *vn = net_generic(net, vlan_net_id); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + if (vn->proc_vlan_conf) + remove_proc_entry(name_conf, vn->proc_vlan_dir); + +@@ -146,6 +149,9 @@ int __net_init vlan_proc_init(struct net + { + struct vlan_net *vn = net_generic(net, vlan_net_id); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + vn->proc_vlan_dir = proc_net_mkdir(net, name_root, net->proc_net); + if (!vn->proc_vlan_dir) + goto err; +--- a/net/core/sock.c ++++ b/net/core/sock.c +@@ -2969,6 +2969,8 @@ static __net_initdata struct pernet_oper + + static int __init proto_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; + return register_pernet_subsys(&proto_net_ops); + } + +--- a/net/ipv4/fib_trie.c ++++ b/net/ipv4/fib_trie.c +@@ -2646,10 +2646,12 @@ static const struct file_operations fib_ + + int __net_init fib_proc_init(struct net *net) + { +- if (!proc_create("fib_trie", S_IRUGO, net->proc_net, &fib_trie_fops)) ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("fib_trie", S_IRUGO, net->proc_net, &fib_trie_fops)) + goto out1; + +- if (!proc_create("fib_triestat", S_IRUGO, net->proc_net, ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("fib_triestat", S_IRUGO, net->proc_net, + &fib_triestat_fops)) + goto out2; + +@@ -2659,17 +2661,21 @@ int __net_init fib_proc_init(struct net + return 0; + + out3: +- remove_proc_entry("fib_triestat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("fib_triestat", net->proc_net); + out2: +- remove_proc_entry("fib_trie", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("fib_trie", net->proc_net); + out1: + return -ENOMEM; + } + + void __net_exit fib_proc_exit(struct net *net) + { +- remove_proc_entry("fib_trie", net->proc_net); +- remove_proc_entry("fib_triestat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ remove_proc_entry("fib_trie", net->proc_net); ++ remove_proc_entry("fib_triestat", net->proc_net); ++ } + remove_proc_entry("route", net->proc_net); + } + +--- a/net/ipv4/proc.c ++++ b/net/ipv4/proc.c +@@ -539,6 +539,9 @@ static __net_initdata struct pernet_oper + + int __init ip_misc_proc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + return register_pernet_subsys(&ip_proc_ops); + } + +--- a/net/ipv4/route.c ++++ b/net/ipv4/route.c +@@ -419,6 +419,9 @@ static struct pernet_operations ip_rt_pr + + static int __init ip_rt_proc_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return 0; ++ + return register_pernet_subsys(&ip_rt_proc_ops); + } + +--- a/ipc/msg.c ++++ b/ipc/msg.c +@@ -1068,6 +1068,9 @@ void __init msg_init(void) + { + msg_init_ns(&init_ipc_ns); + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + ipc_init_proc_interface("sysvipc/msg", + " key msqid perms cbytes qnum lspid lrpid uid gid cuid cgid stime rtime ctime\n", + IPC_MSG_IDS, sysvipc_msg_proc_show); +--- a/ipc/sem.c ++++ b/ipc/sem.c +@@ -191,6 +191,8 @@ void sem_exit_ns(struct ipc_namespace *n + void __init sem_init(void) + { + sem_init_ns(&init_ipc_ns); ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; + ipc_init_proc_interface("sysvipc/sem", + " key semid perms nsems uid gid cuid cgid otime ctime\n", + IPC_SEM_IDS, sysvipc_sem_proc_show); +--- a/ipc/shm.c ++++ b/ipc/shm.c +@@ -118,6 +118,8 @@ pure_initcall(ipc_ns_init); + + void __init shm_init(void) + { ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; + ipc_init_proc_interface("sysvipc/shm", + #if BITS_PER_LONG <= 32 + " key shmid perms size cpid lpid nattch uid gid cuid cgid atime dtime ctime rss swap\n", +--- a/ipc/util.c ++++ b/ipc/util.c +@@ -121,6 +121,9 @@ void __init ipc_init_proc_interface(cons + struct proc_dir_entry *pde; + struct ipc_proc_iface *iface; + ++ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ return; ++ + iface = kmalloc(sizeof(*iface), GFP_KERNEL); + if (!iface) + return; +--- a/net/core/net-procfs.c ++++ b/net/core/net-procfs.c +@@ -318,10 +318,12 @@ static int __net_init dev_proc_net_init( + + if (!proc_create("dev", S_IRUGO, net->proc_net, &dev_seq_fops)) + goto out; +- if (!proc_create("softnet_stat", S_IRUGO, net->proc_net, ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("softnet_stat", S_IRUGO, net->proc_net, + &softnet_seq_fops)) + goto out_dev; +- if (!proc_create("ptype", S_IRUGO, net->proc_net, &ptype_seq_fops)) ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && ++ !proc_create("ptype", S_IRUGO, net->proc_net, &ptype_seq_fops)) + goto out_softnet; + + if (wext_proc_init(net)) +@@ -330,9 +332,11 @@ static int __net_init dev_proc_net_init( + out: + return rc; + out_ptype: +- remove_proc_entry("ptype", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("ptype", net->proc_net); + out_softnet: +- remove_proc_entry("softnet_stat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) ++ remove_proc_entry("softnet_stat", net->proc_net); + out_dev: + remove_proc_entry("dev", net->proc_net); + goto out; +@@ -342,8 +346,10 @@ static void __net_exit dev_proc_net_exit + { + wext_proc_exit(net); + +- remove_proc_entry("ptype", net->proc_net); +- remove_proc_entry("softnet_stat", net->proc_net); ++ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { ++ remove_proc_entry("ptype", net->proc_net); ++ remove_proc_entry("softnet_stat", net->proc_net); ++ } + remove_proc_entry("dev", net->proc_net); + } + diff --git a/target/linux/generic/patches-4.3/903-debloat_direct_io.patch b/target/linux/generic/patches-4.3/903-debloat_direct_io.patch new file mode 100644 index 0000000..2ff3093 --- /dev/null +++ b/target/linux/generic/patches-4.3/903-debloat_direct_io.patch @@ -0,0 +1,80 @@ +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -68,6 +68,11 @@ config FILE_LOCKING + for filesystems like NFS and for the flock() system + call. Disabling this option saves about 11k. + ++config DIRECT_IO ++ bool "Enable O_DIRECT support" if EXPERT ++ depends on BLOCK ++ default y ++ + source "fs/notify/Kconfig" + + source "fs/quota/Kconfig" +--- a/fs/Makefile ++++ b/fs/Makefile +@@ -14,7 +14,8 @@ obj-y := open.o read_write.o file_table. + stack.o fs_struct.o statfs.o fs_pin.o nsfs.o + + ifeq ($(CONFIG_BLOCK),y) +-obj-y += buffer.o block_dev.o direct-io.o mpage.o ++obj-y += buffer.o block_dev.o mpage.o ++obj-$(CONFIG_DIRECT_IO) += direct-io.o + else + obj-y += no-block.o + endif +--- a/include/linux/fs.h ++++ b/include/linux/fs.h +@@ -2695,6 +2695,7 @@ enum { + DIO_SKIP_DIO_COUNT = 0x08, + }; + ++#ifdef CONFIG_DIRECT_IO + void dio_end_io(struct bio *bio, int error); + + ssize_t __blockdev_direct_IO(struct kiocb *iocb, struct inode *inode, +@@ -2702,6 +2703,18 @@ ssize_t __blockdev_direct_IO(struct kioc + loff_t offset, get_block_t get_block, + dio_iodone_t end_io, dio_submit_t submit_io, + int flags); ++#else ++static inline void dio_end_io(struct bio *bio, int error) ++{ ++} ++static inline ssize_t __blockdev_direct_IO(struct kiocb *iocb, struct inode *inode, ++ struct block_device *bdev, struct iov_iter *iter, loff_t offset, ++ get_block_t get_block, dio_iodone_t end_io, ++ dio_submit_t submit_io, int flags) ++{ ++ return -EOPNOTSUPP; ++} ++#endif + + static inline ssize_t blockdev_direct_IO(struct kiocb *iocb, + struct inode *inode, +--- a/fs/fcntl.c ++++ b/fs/fcntl.c +@@ -52,8 +52,10 @@ static int setfl(int fd, struct file * f + arg |= O_NONBLOCK; + + if (arg & O_DIRECT) { ++#ifdef CONFIG_DIRECT_IO + if (!filp->f_mapping || !filp->f_mapping->a_ops || + !filp->f_mapping->a_ops->direct_IO) ++#endif + return -EINVAL; + } + +--- a/fs/open.c ++++ b/fs/open.c +@@ -673,7 +673,9 @@ int open_check_o_direct(struct file *f) + { + /* NB: we're sure to have correct a_ops only after f_op->open */ + if (f->f_flags & O_DIRECT) { ++#ifdef CONFIG_DIRECT_IO + if (!f->f_mapping->a_ops || !f->f_mapping->a_ops->direct_IO) ++#endif + return -EINVAL; + } + return 0; diff --git a/target/linux/generic/patches-4.3/910-kobject_uevent.patch b/target/linux/generic/patches-4.3/910-kobject_uevent.patch new file mode 100644 index 0000000..a2c935f --- /dev/null +++ b/target/linux/generic/patches-4.3/910-kobject_uevent.patch @@ -0,0 +1,21 @@ +--- a/lib/kobject_uevent.c ++++ b/lib/kobject_uevent.c +@@ -52,6 +52,18 @@ static const char *kobject_actions[] = { + [KOBJ_OFFLINE] = "offline", + }; + ++u64 uevent_next_seqnum(void) ++{ ++ u64 seq; ++ ++ mutex_lock(&uevent_sock_mutex); ++ seq = ++uevent_seqnum; ++ mutex_unlock(&uevent_sock_mutex); ++ ++ return seq; ++} ++EXPORT_SYMBOL_GPL(uevent_next_seqnum); ++ + /** + * kobject_action_type - translate action string to numeric type + * diff --git a/target/linux/generic/patches-4.3/911-kobject_add_broadcast_uevent.patch b/target/linux/generic/patches-4.3/911-kobject_add_broadcast_uevent.patch new file mode 100644 index 0000000..a3401ff --- /dev/null +++ b/target/linux/generic/patches-4.3/911-kobject_add_broadcast_uevent.patch @@ -0,0 +1,65 @@ +--- a/include/linux/kobject.h ++++ b/include/linux/kobject.h +@@ -32,6 +32,8 @@ + #define UEVENT_NUM_ENVP 32 /* number of env pointers */ + #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */ + ++struct sk_buff; ++ + #ifdef CONFIG_UEVENT_HELPER + /* path to the userspace helper executed on an event */ + extern char uevent_helper[]; +@@ -222,4 +224,7 @@ int add_uevent_var(struct kobj_uevent_en + int kobject_action_type(const char *buf, size_t count, + enum kobject_action *type); + ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation); ++ + #endif /* _KOBJECT_H_ */ +--- a/lib/kobject_uevent.c ++++ b/lib/kobject_uevent.c +@@ -423,6 +423,43 @@ int add_uevent_var(struct kobj_uevent_en + EXPORT_SYMBOL_GPL(add_uevent_var); + + #if defined(CONFIG_NET) ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation) ++{ ++ struct uevent_sock *ue_sk; ++ int err = 0; ++ ++ /* send netlink message */ ++ mutex_lock(&uevent_sock_mutex); ++ list_for_each_entry(ue_sk, &uevent_sock_list, list) { ++ struct sock *uevent_sock = ue_sk->sk; ++ struct sk_buff *skb2; ++ ++ skb2 = skb_clone(skb, allocation); ++ if (!skb2) ++ break; ++ ++ err = netlink_broadcast(uevent_sock, skb2, pid, group, ++ allocation); ++ if (err) ++ break; ++ } ++ mutex_unlock(&uevent_sock_mutex); ++ ++ kfree_skb(skb); ++ return err; ++} ++#else ++int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, ++ gfp_t allocation) ++{ ++ kfree_skb(skb); ++ return 0; ++} ++#endif ++EXPORT_SYMBOL_GPL(broadcast_uevent); ++ ++#if defined(CONFIG_NET) + static int uevent_net_init(struct net *net) + { + struct uevent_sock *ue_sk; diff --git a/target/linux/generic/patches-4.3/921-use_preinit_as_init.patch b/target/linux/generic/patches-4.3/921-use_preinit_as_init.patch new file mode 100644 index 0000000..1f4e632 --- /dev/null +++ b/target/linux/generic/patches-4.3/921-use_preinit_as_init.patch @@ -0,0 +1,12 @@ +--- a/init/main.c ++++ b/init/main.c +@@ -964,7 +964,8 @@ static int __ref kernel_init(void *unuse + panic("Requested init %s failed (error %d).", + execute_command, ret); + } +- if (!try_to_run_init_process("/sbin/init") || ++ if (!try_to_run_init_process("/etc/preinit") || ++ !try_to_run_init_process("/sbin/init") || + !try_to_run_init_process("/etc/init") || + !try_to_run_init_process("/bin/init") || + !try_to_run_init_process("/bin/sh")) diff --git a/target/linux/generic/patches-4.3/922-always-create-console-node-in-initramfs.patch b/target/linux/generic/patches-4.3/922-always-create-console-node-in-initramfs.patch new file mode 100644 index 0000000..988de35 --- /dev/null +++ b/target/linux/generic/patches-4.3/922-always-create-console-node-in-initramfs.patch @@ -0,0 +1,30 @@ +--- a/scripts/gen_initramfs_list.sh ++++ b/scripts/gen_initramfs_list.sh +@@ -59,6 +59,18 @@ default_initramfs() { + EOF + } + ++list_openwrt_initramfs() { ++ : ++} ++ ++openwrt_initramfs() { ++ # make sure that /dev/console exists ++ cat <<-EOF >> ${output} ++ dir /dev 0755 0 0 ++ nod /dev/console 0600 0 0 c 5 1 ++ EOF ++} ++ + filetype() { + local argv1="$1" + +@@ -177,6 +189,8 @@ dir_filelist() { + if [ "$(echo "${dirlist}" | wc -l)" -gt 1 ]; then + ${dep_list}print_mtime "$1" + ++ ${dep_list}openwrt_initramfs ++ + echo "${dirlist}" | \ + while read x; do + ${dep_list}parse ${x} diff --git a/target/linux/generic/patches-4.3/930-crashlog.patch b/target/linux/generic/patches-4.3/930-crashlog.patch new file mode 100644 index 0000000..bb6805b --- /dev/null +++ b/target/linux/generic/patches-4.3/930-crashlog.patch @@ -0,0 +1,276 @@ +--- /dev/null ++++ b/include/linux/crashlog.h +@@ -0,0 +1,17 @@ ++#ifndef __CRASHLOG_H ++#define __CRASHLOG_H ++ ++#ifdef CONFIG_CRASHLOG ++void crashlog_init_bootmem(struct bootmem_data *bdata); ++void crashlog_init_memblock(phys_addr_t addr, phys_addr_t size); ++#else ++static inline void crashlog_init_bootmem(struct bootmem_data *bdata) ++{ ++} ++ ++static inline void crashlog_init_memblock(phys_addr_t addr, phys_addr_t size) ++{ ++} ++#endif ++ ++#endif +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1286,6 +1286,10 @@ config RELAY + + If unsure, say N. + ++config CRASHLOG ++ bool "Crash logging" ++ depends on (!NO_BOOTMEM || HAVE_MEMBLOCK) && !(ARM || SPARC || PPC) ++ + config BLK_DEV_INITRD + bool "Initial RAM filesystem and RAM disk (initramfs/initrd) support" + depends on BROKEN || !FRV +--- a/kernel/Makefile ++++ b/kernel/Makefile +@@ -103,6 +103,7 @@ obj-$(CONFIG_TORTURE_TEST) += torture.o + obj-$(CONFIG_MEMBARRIER) += membarrier.o + + obj-$(CONFIG_HAS_IOMEM) += memremap.o ++obj-$(CONFIG_CRASHLOG) += crashlog.o + + $(obj)/configs.o: $(obj)/config_data.h + +--- /dev/null ++++ b/kernel/crashlog.c +@@ -0,0 +1,181 @@ ++/* ++ * Crash information logger ++ * Copyright (C) 2010 Felix Fietkau ++ * ++ * Based on ramoops.c ++ * Copyright (C) 2010 Marco Stornelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CRASHLOG_PAGES 4 ++#define CRASHLOG_SIZE (CRASHLOG_PAGES * PAGE_SIZE) ++#define CRASHLOG_MAGIC 0xa1eedead ++ ++/* ++ * Start the log at 1M before the end of RAM, as some boot loaders like ++ * to use the end of the RAM for stack usage and other things ++ * If this fails, fall back to using the last part. ++ */ ++#define CRASHLOG_OFFSET (1024 * 1024) ++ ++struct crashlog_data { ++ u32 magic; ++ u32 len; ++ u8 data[]; ++}; ++ ++static struct debugfs_blob_wrapper crashlog_blob; ++static unsigned long crashlog_addr = 0; ++static struct crashlog_data *crashlog_buf; ++static struct kmsg_dumper dump; ++static bool first = true; ++ ++extern struct list_head *crashlog_modules; ++ ++#ifndef CONFIG_NO_BOOTMEM ++void __init crashlog_init_bootmem(bootmem_data_t *bdata) ++{ ++ unsigned long addr; ++ ++ if (crashlog_addr) ++ return; ++ ++ addr = PFN_PHYS(bdata->node_low_pfn) - CRASHLOG_OFFSET; ++ if (reserve_bootmem(addr, CRASHLOG_SIZE, BOOTMEM_EXCLUSIVE) < 0) { ++ printk("Crashlog failed to allocate RAM at address 0x%lx\n", addr); ++ bdata->node_low_pfn -= CRASHLOG_PAGES; ++ addr = PFN_PHYS(bdata->node_low_pfn); ++ } ++ crashlog_addr = addr; ++} ++#endif ++ ++#ifdef CONFIG_HAVE_MEMBLOCK ++void __meminit crashlog_init_memblock(phys_addr_t addr, phys_addr_t size) ++{ ++ if (crashlog_addr) ++ return; ++ ++ addr += size - CRASHLOG_OFFSET; ++ if (memblock_reserve(addr, CRASHLOG_SIZE)) { ++ printk("Crashlog failed to allocate RAM at address 0x%lx\n", (unsigned long) addr); ++ return; ++ } ++ ++ crashlog_addr = addr; ++} ++#endif ++ ++static void __init crashlog_copy(void) ++{ ++ if (crashlog_buf->magic != CRASHLOG_MAGIC) ++ return; ++ ++ if (!crashlog_buf->len || crashlog_buf->len > ++ CRASHLOG_SIZE - sizeof(*crashlog_buf)) ++ return; ++ ++ crashlog_blob.size = crashlog_buf->len; ++ crashlog_blob.data = kmemdup(crashlog_buf->data, ++ crashlog_buf->len, GFP_KERNEL); ++ ++ debugfs_create_blob("crashlog", 0700, NULL, &crashlog_blob); ++} ++ ++static int get_maxlen(void) ++{ ++ return CRASHLOG_SIZE - sizeof(*crashlog_buf) - crashlog_buf->len; ++} ++ ++static void crashlog_printf(const char *fmt, ...) ++{ ++ va_list args; ++ int len = get_maxlen(); ++ ++ if (!len) ++ return; ++ ++ va_start(args, fmt); ++ crashlog_buf->len += vscnprintf( ++ &crashlog_buf->data[crashlog_buf->len], ++ len, fmt, args); ++ va_end(args); ++} ++ ++static void crashlog_do_dump(struct kmsg_dumper *dumper, ++ enum kmsg_dump_reason reason) ++{ ++ struct timeval tv; ++ struct module *m; ++ char *buf; ++ size_t len; ++ ++ if (!first) ++ crashlog_printf("\n===================================\n"); ++ ++ do_gettimeofday(&tv); ++ crashlog_printf("Time: %lu.%lu\n", ++ (long)tv.tv_sec, (long)tv.tv_usec); ++ ++ if (first) { ++ crashlog_printf("Modules:"); ++ list_for_each_entry(m, crashlog_modules, list) { ++ crashlog_printf("\t%s@%p+%x", m->name, ++ m->module_core, m->core_size, ++ m->module_init, m->init_size); ++ } ++ crashlog_printf("\n"); ++ first = false; ++ } ++ ++ buf = (char *)&crashlog_buf->data[crashlog_buf->len]; ++ ++ kmsg_dump_get_buffer(dumper, true, buf, get_maxlen(), &len); ++ ++ crashlog_buf->len += len; ++} ++ ++ ++int __init crashlog_init_fs(void) ++{ ++ if (!crashlog_addr) ++ return -ENOMEM; ++ ++ crashlog_buf = ioremap(crashlog_addr, CRASHLOG_SIZE); ++ ++ crashlog_copy(); ++ ++ crashlog_buf->magic = CRASHLOG_MAGIC; ++ crashlog_buf->len = 0; ++ ++ dump.max_reason = KMSG_DUMP_OOPS; ++ dump.dump = crashlog_do_dump; ++ kmsg_dump_register(&dump); ++ ++ return 0; ++} ++module_init(crashlog_init_fs); +--- a/mm/bootmem.c ++++ b/mm/bootmem.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -177,6 +178,7 @@ static unsigned long __init free_all_boo + if (!bdata->node_bootmem_map) + return 0; + ++ crashlog_init_bootmem(bdata); + map = bdata->node_bootmem_map; + start = bdata->node_min_pfn; + end = bdata->node_low_pfn; +--- a/kernel/module.c ++++ b/kernel/module.c +@@ -275,6 +275,9 @@ static void mod_update_bounds(struct mod + #ifdef CONFIG_KGDB_KDB + struct list_head *kdb_modules = &modules; /* kdb needs the list of modules */ + #endif /* CONFIG_KGDB_KDB */ ++#ifdef CONFIG_CRASHLOG ++struct list_head *crashlog_modules = &modules; ++#endif + + static void module_assert_mutex(void) + { +--- a/mm/memblock.c ++++ b/mm/memblock.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -503,6 +504,8 @@ static void __init_memblock memblock_ins + memblock_set_region_node(rgn, nid); + type->cnt++; + type->total_size += size; ++ if (type == &memblock.memory && idx == 0) ++ crashlog_init_memblock(base, size); + } + + /** diff --git a/target/linux/generic/patches-4.3/940-ocf_kbuild_integration.patch b/target/linux/generic/patches-4.3/940-ocf_kbuild_integration.patch new file mode 100644 index 0000000..68f0a84 --- /dev/null +++ b/target/linux/generic/patches-4.3/940-ocf_kbuild_integration.patch @@ -0,0 +1,20 @@ +--- a/crypto/Kconfig ++++ b/crypto/Kconfig +@@ -1645,3 +1645,6 @@ source crypto/asymmetric_keys/Kconfig + source certs/Kconfig + + endif # if CRYPTO ++ ++source "crypto/ocf/Kconfig" ++ +--- a/crypto/Makefile ++++ b/crypto/Makefile +@@ -119,6 +119,8 @@ obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) + + obj-$(CONFIG_CRYPTO_USER_API_RNG) += algif_rng.o + obj-$(CONFIG_CRYPTO_USER_API_AEAD) += algif_aead.o + ++obj-$(CONFIG_OCF_OCF) += ocf/ ++ + # + # generic algorithms and the async_tx api + # diff --git a/target/linux/generic/patches-4.3/941-ocf_20120127.patch b/target/linux/generic/patches-4.3/941-ocf_20120127.patch new file mode 100644 index 0000000..a016f5b --- /dev/null +++ b/target/linux/generic/patches-4.3/941-ocf_20120127.patch @@ -0,0 +1,166 @@ +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -139,6 +139,9 @@ + * that might otherwise be identical and have very little entropy + * available to them (particularly common in the embedded world). + * ++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++ * int random_input_wait(void); ++ * + * add_input_randomness() uses the input layer interrupt timing, as well as + * the event type information from the hardware. + * +@@ -152,6 +155,13 @@ + * seek times do not make for good sources of entropy, as their seek + * times are usually fairly consistent. + * ++ * random_input_words() just provides a raw block of entropy to the input ++ * pool, such as from a hardware entropy generator. ++ * ++ * random_input_wait() suspends the caller until such time as the ++ * entropy pool falls below the write threshold, and returns a count of how ++ * much entropy (in bits) is needed to sustain the pool. ++ * + * All of these routines try to estimate how many bits of randomness a + * particular randomness source. They do this by keeping track of the + * first and second order deltas of the event timings. +@@ -958,6 +968,63 @@ void add_disk_randomness(struct gendisk + EXPORT_SYMBOL_GPL(add_disk_randomness); + #endif + ++/* ++ * random_input_words - add bulk entropy to pool ++ * ++ * @buf: buffer to add ++ * @wordcount: number of __u32 words to add ++ * @ent_count: total amount of entropy (in bits) to credit ++ * ++ * this provides bulk input of entropy to the input pool ++ * ++ */ ++void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++{ ++ mix_pool_bytes(&input_pool, buf, wordcount*4); ++ ++ credit_entropy_bits(&input_pool, ent_count); ++ ++ pr_notice("crediting %d bits => %d\n", ++ ent_count, input_pool.entropy_count); ++ /* ++ * Wake up waiting processes if we have enough ++ * entropy. ++ */ ++ if (input_pool.entropy_count >= random_read_wakeup_bits) ++ wake_up_interruptible(&random_read_wait); ++} ++EXPORT_SYMBOL(random_input_words); ++ ++/* ++ * random_input_wait - wait until random needs entropy ++ * ++ * this function sleeps until the /dev/random subsystem actually ++ * needs more entropy, and then return the amount of entropy ++ * that it would be nice to have added to the system. ++ */ ++int random_input_wait(void) ++{ ++ int count; ++ ++ wait_event_interruptible(random_write_wait, ++ input_pool.entropy_count < random_write_wakeup_bits); ++ ++ count = random_write_wakeup_bits - input_pool.entropy_count; ++ ++ /* likely we got woken up due to a signal */ ++ if (count <= 0) count = random_read_wakeup_bits; ++ ++ pr_notice("requesting %d bits from input_wait()er %d<%d\n", ++ count, ++ input_pool.entropy_count, random_write_wakeup_bits); ++ ++ return count; ++} ++EXPORT_SYMBOL(random_input_wait); ++ ++ ++#define EXTRACT_SIZE 10 ++ + /********************************************************************* + * + * Entropy extraction routines +--- a/fs/fcntl.c ++++ b/fs/fcntl.c +@@ -140,6 +140,7 @@ pid_t f_getown(struct file *filp) + read_unlock(&filp->f_owner.lock); + return pid; + } ++EXPORT_SYMBOL(sys_dup); + + static int f_setown_ex(struct file *filp, unsigned long arg) + { +--- a/include/linux/miscdevice.h ++++ b/include/linux/miscdevice.h +@@ -19,6 +19,7 @@ + #define APOLLO_MOUSE_MINOR 7 /* unused */ + #define PC110PAD_MINOR 9 /* unused */ + /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ ++#define CRYPTODEV_MINOR 70 /* /dev/crypto */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +--- a/include/uapi/linux/random.h ++++ b/include/uapi/linux/random.h +@@ -34,6 +34,30 @@ + /* Clear the entropy pool and associated counters. (Superuser only.) */ + #define RNDCLEARPOOL _IO( 'R', 0x06 ) + ++#ifdef CONFIG_FIPS_RNG ++ ++/* Size of seed value - equal to AES blocksize */ ++#define AES_BLOCK_SIZE_BYTES 16 ++#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES ++/* Size of AES key */ ++#define KEY_SIZE_BYTES 16 ++ ++/* ioctl() structure used by FIPS 140-2 Tests */ ++struct rand_fips_test { ++ unsigned char key[KEY_SIZE_BYTES]; /* Input */ ++ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ ++ unsigned char result[SEED_SIZE_BYTES]; /* Output */ ++}; ++ ++/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ ++#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) ++ ++/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ ++#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) ++ ++#endif /* #ifdef CONFIG_FIPS_RNG */ ++ + struct rand_pool_info { + int entropy_count; + int buf_size; +--- a/include/linux/random.h ++++ b/include/linux/random.h +@@ -20,6 +20,10 @@ extern void add_input_randomness(unsigne + unsigned int value); + extern void add_interrupt_randomness(int irq, int irq_flags); + ++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); ++extern int random_input_wait(void); ++#define HAS_RANDOM_INPUT_WAIT 1 ++ + extern void get_random_bytes(void *buf, int nbytes); + extern int add_random_ready_callback(struct random_ready_callback *rdy); + extern void del_random_ready_callback(struct random_ready_callback *rdy); +--- a/kernel/pid.c ++++ b/kernel/pid.c +@@ -431,6 +431,7 @@ void transfer_pid(struct task_struct *ol + new->pids[type].pid = old->pids[type].pid; + hlist_replace_rcu(&old->pids[type].node, &new->pids[type].node); + } ++EXPORT_SYMBOL(find_task_by_vpid); + + struct task_struct *pid_task(struct pid *pid, enum pid_type type) + { diff --git a/target/linux/generic/patches-4.3/960-decompress_unlzo_fix.patch b/target/linux/generic/patches-4.3/960-decompress_unlzo_fix.patch new file mode 100644 index 0000000..37e322a --- /dev/null +++ b/target/linux/generic/patches-4.3/960-decompress_unlzo_fix.patch @@ -0,0 +1,23 @@ +--- /dev/null ++++ b/include/linux/decompress/unlzo_mm.h +@@ -0,0 +1,10 @@ ++#ifndef UNLZO_MM_H ++#define UNLZO_MM_H ++ ++#ifdef STATIC ++#define INIT ++#else ++#define INIT __init ++#endif ++ ++#endif +--- a/lib/decompress_unlzo.c ++++ b/lib/decompress_unlzo.c +@@ -39,6 +39,7 @@ + + #include + #include ++#include + #include + + #include diff --git a/target/linux/generic/patches-4.3/970-remove-unsane-filenames-from-deps_initramfs-list.patch b/target/linux/generic/patches-4.3/970-remove-unsane-filenames-from-deps_initramfs-list.patch new file mode 100644 index 0000000..ac13c9e --- /dev/null +++ b/target/linux/generic/patches-4.3/970-remove-unsane-filenames-from-deps_initramfs-list.patch @@ -0,0 +1,29 @@ +--- a/usr/Makefile ++++ b/usr/Makefile +@@ -53,6 +53,8 @@ ifneq ($(wildcard $(obj)/.initramfs_data + include $(obj)/.initramfs_data.cpio.d + endif + ++deps_initramfs_sane := $(foreach v,$(deps_initramfs),$(if $(findstring :,$(v)),,$(v))) ++ + quiet_cmd_initfs = GEN $@ + cmd_initfs = $(initramfs) -o $@ $(ramfs-args) $(ramfs-input) + +@@ -61,14 +63,14 @@ targets := initramfs_data.cpio.gz initra + initramfs_data.cpio.lzo initramfs_data.cpio.lz4 \ + initramfs_data.cpio + # do not try to update files included in initramfs +-$(deps_initramfs): ; ++$(deps_initramfs_sane): ; + +-$(deps_initramfs): klibcdirs ++$(deps_initramfs_sane): klibcdirs + # We rebuild initramfs_data.cpio if: + # 1) Any included file is newer then initramfs_data.cpio + # 2) There are changes in which files are included (added or deleted) + # 3) If gen_init_cpio are newer than initramfs_data.cpio + # 4) arguments to gen_initramfs.sh changes +-$(obj)/initramfs_data.cpio$(suffix_y): $(obj)/gen_init_cpio $(deps_initramfs) klibcdirs ++$(obj)/initramfs_data.cpio$(suffix_y): $(obj)/gen_init_cpio $(deps_initramfs_sane) klibcdirs + $(Q)$(initramfs) -l $(ramfs-input) > $(obj)/.initramfs_data.cpio.d + $(call if_changed,initfs) diff --git a/target/linux/generic/patches-4.3/980-arm_openwrt_machtypes.patch b/target/linux/generic/patches-4.3/980-arm_openwrt_machtypes.patch new file mode 100644 index 0000000..60ca07e --- /dev/null +++ b/target/linux/generic/patches-4.3/980-arm_openwrt_machtypes.patch @@ -0,0 +1,32 @@ +--- a/arch/arm/tools/mach-types ++++ b/arch/arm/tools/mach-types +@@ -1006,3 +1006,29 @@ eco5_bx2 MACH_ECO5_BX2 ECO5_BX2 4572 + eukrea_cpuimx28sd MACH_EUKREA_CPUIMX28SD EUKREA_CPUIMX28SD 4573 + domotab MACH_DOMOTAB DOMOTAB 4574 + pfla03 MACH_PFLA03 PFLA03 4575 ++# ++# Additional mach-types supported by OpenWrt ++# ++wg302v1 MACH_WG302V1 WG302V1 889 ++pronghorn MACH_PRONGHORN PRONGHORN 928 ++pronghorn_metro MACH_PRONGHORNMETRO PRONGHORNMETRO 1040 ++sidewinder MACH_SIDEWINDER SIDEWINDER 1041 ++wrt300nv2 MACH_WRT300NV2 WRT300NV2 1077 ++compex42x MACH_COMPEXWP18 COMPEXWP18 1273 ++goldfish MACH_GOLDFISH GOLDFISH 1441 ++cambria MACH_CAMBRIA CAMBRIA 1468 ++dt2 MACH_DT2 DT2 1514 ++ap1000 MACH_AP1000 AP1000 1543 ++tw2662 MACH_TW2662 TW2662 1658 ++tw5334 MACH_TW5334 TW5334 1664 ++usr8200 MACH_USR8200 USR8200 1762 ++mi424wr MACH_MI424WR MI424WR 1778 ++gw2388 MACH_GW2388 GW2388 2635 ++iconnect MACH_ICONNECT ICONNECT 2870 ++nsb3ast MACH_NSB3AST NSB3AST 2917 ++goflexnet MACH_GOFLEXNET GOFLEXNET 3089 ++nas6210 MACH_NAS6210 NAS6210 3104 ++ns_k330 MACH_NS_K330 NS_K330 3108 ++bcm2708 MACH_BCM2708 BCM2708 3138 ++wn802t MACH_WN802T WN802T 3306 ++nsa310 MACH_NSA310 NSA310 4022 diff --git a/target/linux/generic/patches-4.3/990-gpio_wdt.patch b/target/linux/generic/patches-4.3/990-gpio_wdt.patch new file mode 100644 index 0000000..32af351 --- /dev/null +++ b/target/linux/generic/patches-4.3/990-gpio_wdt.patch @@ -0,0 +1,360 @@ +This generic GPIO watchdog is used on Huawei E970 (brcm47xx) + +Signed-off-by: Mathias Adam + +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1216,6 +1216,15 @@ config WDT_MTX1 + Hardware driver for the MTX-1 boards. This is a watchdog timer that + will reboot the machine after a 100 seconds timer expired. + ++config GPIO_WDT ++ tristate "GPIO Hardware Watchdog" ++ help ++ Hardware driver for GPIO-controlled watchdogs. GPIO pin and ++ toggle interval settings are platform-specific. The driver ++ will stop toggling the GPIO (i.e. machine reboots) after a ++ 100 second timer expired and no process has written to ++ /dev/watchdog during that time. ++ + config PNX833X_WDT + tristate "PNX833x Hardware Watchdog" + depends on SOC_PNX8335 +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -139,6 +139,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt + obj-$(CONFIG_INDYDOG) += indydog.o + obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o + obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o ++obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o +--- /dev/null ++++ b/drivers/watchdog/old_gpio_wdt.c +@@ -0,0 +1,301 @@ ++/* ++ * Driver for GPIO-controlled Hardware Watchdogs. ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * Replaces mtx1_wdt (driver for the MTX-1 Watchdog): ++ * ++ * (C) Copyright 2005 4G Systems , ++ * All Rights Reserved. ++ * http://www.4g-systems.biz ++ * ++ * (C) Copyright 2007 OpenWrt.org, Florian Fainelli ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * Neither Michael Stickel nor 4G Systems admit liability nor provide ++ * warranty for any of this software. This material is provided ++ * "AS-IS" and at no charge. ++ * ++ * (c) Copyright 2005 4G Systems ++ * ++ * Release 0.01. ++ * Author: Michael Stickel michael.stickel@4g-systems.biz ++ * ++ * Release 0.02. ++ * Author: Florian Fainelli florian@openwrt.org ++ * use the Linux watchdog/timer APIs ++ * ++ * Release 0.03. ++ * Author: Mathias Adam ++ * make it a generic gpio watchdog driver ++ * ++ * The Watchdog is configured to reset the MTX-1 ++ * if it is not triggered for 100 seconds. ++ * It should not be triggered more often than 1.6 seconds. ++ * ++ * A timer triggers the watchdog every 5 seconds, until ++ * it is opened for the first time. After the first open ++ * it MUST be triggered every 2..95 seconds. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int ticks = 100 * HZ; ++ ++static struct { ++ struct completion stop; ++ spinlock_t lock; ++ int running; ++ struct timer_list timer; ++ int queue; ++ int default_ticks; ++ unsigned long inuse; ++ unsigned gpio; ++ unsigned int gstate; ++ int interval; ++ int first_interval; ++} gpio_wdt_device; ++ ++static void gpio_wdt_trigger(unsigned long unused) ++{ ++ spin_lock(&gpio_wdt_device.lock); ++ if (gpio_wdt_device.running && ticks > 0) ++ ticks -= gpio_wdt_device.interval; ++ ++ /* toggle wdt gpio */ ++ gpio_wdt_device.gstate = !gpio_wdt_device.gstate; ++ gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate); ++ ++ if (gpio_wdt_device.queue && ticks > 0) ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval); ++ else ++ complete(&gpio_wdt_device.stop); ++ spin_unlock(&gpio_wdt_device.lock); ++} ++ ++static void gpio_wdt_reset(void) ++{ ++ ticks = gpio_wdt_device.default_ticks; ++} ++ ++ ++static void gpio_wdt_start(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (!gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 1; ++ gpio_wdt_device.gstate = 1; ++ gpio_set_value(gpio_wdt_device.gpio, 1); ++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval); ++ } ++ gpio_wdt_device.running++; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++} ++ ++static int gpio_wdt_stop(void) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_wdt_device.lock, flags); ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ gpio_wdt_device.gstate = 0; ++ gpio_set_value(gpio_wdt_device.gpio, 0); ++ } ++ ticks = gpio_wdt_device.default_ticks; ++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); ++ return 0; ++} ++ ++/* Filesystem functions */ ++ ++static int gpio_wdt_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(0, &gpio_wdt_device.inuse)) ++ return -EBUSY; ++ return nonseekable_open(inode, file); ++} ++ ++ ++static int gpio_wdt_release(struct inode *inode, struct file *file) ++{ ++ clear_bit(0, &gpio_wdt_device.inuse); ++ return 0; ++} ++ ++static long gpio_wdt_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ void __user *argp = (void __user *)arg; ++ int __user *p = (int __user *)argp; ++ unsigned int value; ++ static const struct watchdog_info ident = { ++ .options = WDIOF_CARDRESET, ++ .identity = "GPIO WDT", ++ }; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ if (copy_to_user(argp, &ident, sizeof(ident))) ++ return -EFAULT; ++ break; ++ case WDIOC_GETSTATUS: ++ case WDIOC_GETBOOTSTATUS: ++ put_user(0, p); ++ break; ++ case WDIOC_SETOPTIONS: ++ if (get_user(value, p)) ++ return -EFAULT; ++ if (value & WDIOS_ENABLECARD) ++ gpio_wdt_start(); ++ else if (value & WDIOS_DISABLECARD) ++ gpio_wdt_stop(); ++ else ++ return -EINVAL; ++ return 0; ++ case WDIOC_KEEPALIVE: ++ gpio_wdt_reset(); ++ break; ++ default: ++ return -ENOTTY; ++ } ++ return 0; ++} ++ ++ ++static ssize_t gpio_wdt_write(struct file *file, const char *buf, ++ size_t count, loff_t *ppos) ++{ ++ if (!count) ++ return -EIO; ++ gpio_wdt_reset(); ++ return count; ++} ++ ++static const struct file_operations gpio_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .unlocked_ioctl = gpio_wdt_ioctl, ++ .open = gpio_wdt_open, ++ .write = gpio_wdt_write, ++ .release = gpio_wdt_release, ++}; ++ ++ ++static struct miscdevice gpio_wdt_misc = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &gpio_wdt_fops, ++}; ++ ++ ++static int gpio_wdt_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data; ++ ++ gpio_wdt_device.gpio = gpio_wdt_data->gpio; ++ gpio_wdt_device.interval = gpio_wdt_data->interval; ++ gpio_wdt_device.first_interval = gpio_wdt_data->first_interval; ++ if (gpio_wdt_device.first_interval <= 0) { ++ gpio_wdt_device.first_interval = gpio_wdt_device.interval; ++ } ++ ++ ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt"); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to request gpio"); ++ return ret; ++ } ++ ++ spin_lock_init(&gpio_wdt_device.lock); ++ init_completion(&gpio_wdt_device.stop); ++ gpio_wdt_device.queue = 0; ++ clear_bit(0, &gpio_wdt_device.inuse); ++ setup_timer(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L); ++ gpio_wdt_device.default_ticks = ticks; ++ ++ gpio_wdt_start(); ++ dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n", ++ gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval); ++ return 0; ++} ++ ++static int gpio_wdt_remove(struct platform_device *pdev) ++{ ++ /* FIXME: do we need to lock this test ? */ ++ if (gpio_wdt_device.queue) { ++ gpio_wdt_device.queue = 0; ++ wait_for_completion(&gpio_wdt_device.stop); ++ } ++ ++ gpio_free(gpio_wdt_device.gpio); ++ misc_deregister(&gpio_wdt_misc); ++ return 0; ++} ++ ++static struct platform_driver gpio_wdt_driver = { ++ .probe = gpio_wdt_probe, ++ .remove = gpio_wdt_remove, ++ .driver.name = "gpio-wdt", ++ .driver.owner = THIS_MODULE, ++}; ++ ++static int __init gpio_wdt_init(void) ++{ ++ return platform_driver_register(&gpio_wdt_driver); ++} ++arch_initcall(gpio_wdt_init); ++ ++/* ++ * We do wdt initialization in two steps: arch_initcall probes the wdt ++ * very early to start pinging the watchdog (misc devices are not yet ++ * available), and later module_init() just registers the misc device. ++ */ ++static int gpio_wdt_init_late(void) ++{ ++ int ret; ++ ++ ret = misc_register(&gpio_wdt_misc); ++ if (ret < 0) { ++ pr_err("GPIO_WDT: failed to register misc device\n"); ++ return ret; ++ } ++ return 0; ++} ++#ifndef MODULE ++module_init(gpio_wdt_init_late); ++#endif ++ ++static void __exit gpio_wdt_exit(void) ++{ ++ platform_driver_unregister(&gpio_wdt_driver); ++} ++module_exit(gpio_wdt_exit); ++ ++MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam"); ++MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS("platform:gpio-wdt"); +--- /dev/null ++++ b/include/linux/old_gpio_wdt.h +@@ -0,0 +1,21 @@ ++/* ++ * Definitions for the GPIO watchdog driver ++ * ++ * Copyright (C) 2013 Mathias Adam ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef _GPIO_WDT_H_ ++#define _GPIO_WDT_H_ ++ ++struct gpio_wdt_platform_data { ++ int gpio; /* GPIO line number */ ++ int interval; /* watchdog reset interval in system ticks */ ++ int first_interval; /* first wd reset interval in system ticks */ ++}; ++ ++#endif /* _GPIO_WDT_H_ */ diff --git a/target/linux/generic/patches-4.3/995-mangle_bootargs.patch b/target/linux/generic/patches-4.3/995-mangle_bootargs.patch new file mode 100644 index 0000000..eb52561 --- /dev/null +++ b/target/linux/generic/patches-4.3/995-mangle_bootargs.patch @@ -0,0 +1,58 @@ +--- a/init/main.c ++++ b/init/main.c +@@ -355,6 +355,29 @@ static inline void setup_nr_cpu_ids(void + static inline void smp_prepare_cpus(unsigned int maxcpus) { } + #endif + ++#ifdef CONFIG_MANGLE_BOOTARGS ++static void __init mangle_bootargs(char *command_line) ++{ ++ char *rootdev; ++ char *rootfs; ++ ++ rootdev = strstr(command_line, "root=/dev/mtdblock"); ++ ++ if (rootdev) ++ strncpy(rootdev, "mangled_rootblock=", 18); ++ ++ rootfs = strstr(command_line, "rootfstype"); ++ ++ if (rootfs) ++ strncpy(rootfs, "mangled_fs", 10); ++ ++} ++#else ++static void __init mangle_bootargs(char *command_line) ++{ ++} ++#endif ++ + /* + * We need to store the untouched command line for future reference. + * We also need to store the touched command line since the parameter +@@ -527,6 +550,7 @@ asmlinkage __visible void __init start_k + pr_notice("%s", linux_banner); + setup_arch(&command_line); + mm_init_cpumask(&init_mm); ++ mangle_bootargs(command_line); + setup_command_line(command_line); + setup_nr_cpu_ids(); + setup_per_cpu_areas(); +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1638,6 +1638,15 @@ config EMBEDDED + an embedded system so certain expert options are available + for configuration. + ++config MANGLE_BOOTARGS ++ bool "Rename offending bootargs" ++ depends on EXPERT ++ help ++ Sometimes the bootloader passed bogus root= and rootfstype= ++ parameters to the kernel, and while you want to ignore them, ++ you need to know the values f.e. to support dual firmware ++ layouts on the flash. ++ + config HAVE_PERF_EVENTS + bool + help diff --git a/target/linux/generic/patches-4.3/997-device_tree_cmdline.patch b/target/linux/generic/patches-4.3/997-device_tree_cmdline.patch new file mode 100644 index 0000000..5708085 --- /dev/null +++ b/target/linux/generic/patches-4.3/997-device_tree_cmdline.patch @@ -0,0 +1,24 @@ +--- a/drivers/of/fdt.c ++++ b/drivers/of/fdt.c +@@ -947,6 +947,9 @@ int __init early_init_dt_scan_chosen(uns + p = of_get_flat_dt_prop(node, "bootargs", &l); + if (p != NULL && l > 0) + strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); ++ p = of_get_flat_dt_prop(node, "bootargs-append", &l); ++ if (p != NULL && l > 0) ++ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else +--- a/arch/mips/kernel/prom.c ++++ b/arch/mips/kernel/prom.c +@@ -51,6 +51,9 @@ void * __init early_init_dt_alloc_memory + + void __init __dt_setup_arch(void *bph) + { ++ if (boot_command_line[0] == '\0') ++ strcpy(boot_command_line, arcs_cmdline); ++ + if (!early_init_dt_scan(bph)) + return; + diff --git a/target/linux/generic/patches-4.3/998-enable_wilink_platform_without_drivers.patch b/target/linux/generic/patches-4.3/998-enable_wilink_platform_without_drivers.patch new file mode 100644 index 0000000..d317de1 --- /dev/null +++ b/target/linux/generic/patches-4.3/998-enable_wilink_platform_without_drivers.patch @@ -0,0 +1,15 @@ +We use backports for driver updates - make sure we can compile in the glue code regardless + +Signed-off-by: Imre Kaloz + +--- a/drivers/net/wireless/ti/Kconfig ++++ b/drivers/net/wireless/ti/Kconfig +@@ -15,7 +15,7 @@ source "drivers/net/wireless/ti/wlcore/K + + config WILINK_PLATFORM_DATA + bool "TI WiLink platform data" +- depends on WLCORE_SDIO || WL1251_SDIO ++ depends on WLCORE_SDIO || WL1251_SDIO || ARCH_OMAP2PLUS + default y + ---help--- + Small platform data bit needed to pass data to the sdio modules. diff --git a/target/linux/imx6/Makefile b/target/linux/imx6/Makefile new file mode 100644 index 0000000..479b48e --- /dev/null +++ b/target/linux/imx6/Makefile @@ -0,0 +1,25 @@ +# +# Copyright (C) 2013-2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=imx6 +BOARDNAME:=Freescale i.MX 6 +FEATURES:=audio display fpu gpio pcie rtc usb usbgadget squashfs targz nand ubifs +CPU_TYPE:=cortex-a9 +CPU_SUBTYPE:=neon +MAINTAINER:=Luka Perkov + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +KERNELNAME:=zImage dtbs + +DEFAULT_PACKAGES += uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/target/linux/imx6/base-files.mk b/target/linux/imx6/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/imx6/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/imx6/base-files/etc/uci-defaults/02_network b/target/linux/imx6/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..bf83063 --- /dev/null +++ b/target/linux/imx6/base-files/etc/uci-defaults/02_network @@ -0,0 +1,34 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/imx6.sh + +board=$(imx6_board_name) + +ucidef_set_interface_loopback + +case "$board" in +*gw51xx |\ +*gw52xx) + ucidef_set_interface_lan 'eth0' + ;; +*gw53xx |\ +*gw54xx |\ +*gw552x) + ucidef_set_interfaces_lan_wan 'eth0' 'eth1' + ;; +*wandboard) + ucidef_set_interface_wan 'eth0' + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/imx6/base-files/lib/imx6.sh b/target/linux/imx6/base-files/lib/imx6.sh new file mode 100755 index 0000000..360ec58 --- /dev/null +++ b/target/linux/imx6/base-files/lib/imx6.sh @@ -0,0 +1,68 @@ +#!/bin/sh +# +# Copyright (C) 2010-2013 OpenWrt.org +# + +IMX6_BOARD_NAME= +IMX6_MODEL= + +imx6_board_detect() { + local machine + local name + + machine=$(cat /proc/device-tree/model) + + case "$machine" in + "Gateworks Ventana i.MX6 DualLite/Solo GW51XX" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW51XX") + name="gw51xx" + ;; + + "Gateworks Ventana i.MX6 DualLite/Solo GW52XX" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW52XX") + name="gw52xx" + ;; + + "Gateworks Ventana i.MX6 DualLite/Solo GW53XX" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW53XX") + name="gw53xx" + ;; + + "Gateworks Ventana i.MX6 DualLite/Solo GW54XX" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW54XX" |\ + "Gateworks Ventana GW5400-A") + name="gw54xx" + ;; + + "Gateworks Ventana i.MX6 DualLite/Solo GW552X" |\ + "Gateworks Ventana i.MX6 Dual/Quad GW552X") + name="gw552x" + ;; + + "Wandboard i.MX6 Dual Lite Board") + name="wandboard" + ;; + + *) + name="generic" + ;; + esac + + [ -z "$IMX6_BOARD_NAME" ] && IMX6_BOARD_NAME="$name" + [ -z "$IMX6_MODEL" ] && IMX6_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$IMX6_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$IMX6_MODEL" > /tmp/sysinfo/model +} + +imx6_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] || imx6_board_detect + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/imx6/base-files/lib/upgrade/platform.sh b/target/linux/imx6/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000..0bbf110 --- /dev/null +++ b/target/linux/imx6/base-files/lib/upgrade/platform.sh @@ -0,0 +1,29 @@ +# +# Copyright (C) 2010-2015 OpenWrt.org +# + +. /lib/imx6.sh + +platform_check_image() { + local board=$(imx6_board_name) + + case "$board" in + *gw5*) + nand_do_platform_check $board $1 + return $?; + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_pre_upgrade() { + local board=$(imx6_board_name) + + case "$board" in + *gw5*) + nand_do_upgrade "$1" + ;; + esac +} diff --git a/target/linux/imx6/config-3.18 b/target/linux/imx6/config-3.18 new file mode 100644 index 0000000..fcd86d4 --- /dev/null +++ b/target/linux/imx6/config-3.18 @@ -0,0 +1,369 @@ +CONFIG_AHCI_IMX=y +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATA=y +CONFIG_ATAGS=y +# CONFIG_ATA_SFF is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_SHA1_ARM_NEON=y +CONFIG_CRYPTO_SHA512_ARM_NEON=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_IMX_UART_PORT=1 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +# CONFIG_EMAC_ROCKCHIP is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FEC=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MXC=y +# CONFIG_GPIO_SYSCON is not set +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IMX_ANATOP=y +CONFIG_HAVE_IMX_GPC=y +CONFIG_HAVE_IMX_MMDC=y +CONFIG_HAVE_IMX_SRC=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_IMX=y +CONFIG_IMX2_WDT=y +CONFIG_IMX_DMA=y +CONFIG_IMX_SDMA=y +# CONFIG_IMX_WEIM is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD=y +CONFIG_JBD2=y +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_SYSCON is not set +CONFIG_LIBFDT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_MXC is not set +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_GPMI_NAND=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MX3_IPU is not set +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_MXS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_IMX6=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX=y +CONFIG_PINCTRL_IMX6Q=y +CONFIG_PINCTRL_IMX6SL=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PM_OPP=y +CONFIG_PPS=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PTP_1588_CLOCK=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ANATOP=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_PFUZE100=y +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_MXC is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SCHED_HRTICK=y +CONFIG_SCSI=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_IMX50 is not set +# CONFIG_SOC_IMX51 is not set +# CONFIG_SOC_IMX53 is not set +CONFIG_SOC_IMX6=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +# CONFIG_SOC_IMX6SX is not set +# CONFIG_SOC_VF610 is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_IMX=y +CONFIG_SPI_MASTER=y +CONFIG_SRAM=y +CONFIG_STMP_DEVICE=y +CONFIG_STOP_MACHINE=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_USB_MXS_PHY is not set +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_XEN is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/imx6/config-4.1 b/target/linux/imx6/config-4.1 new file mode 100644 index 0000000..18a26d6 --- /dev/null +++ b/target/linux/imx6/config-4.1 @@ -0,0 +1,382 @@ +CONFIG_AHCI_IMX=y +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MXC=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ATA=y +CONFIG_ATAGS=y +# CONFIG_ATA_SFF is not set +CONFIG_AUTO_ZRELADDR=y +CONFIG_CACHE_L2X0=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_IMX_UART_PORT=1 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_PCI is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FEC=y +CONFIG_FRAME_POINTER=y +# CONFIG_FSL_PQ_MDIO is not set +CONFIG_FS_MBCACHE=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MXC=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IMX_ANATOP=y +CONFIG_HAVE_IMX_GPC=y +CONFIG_HAVE_IMX_MMDC=y +CONFIG_HAVE_IMX_SRC=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HSU_DMA_PCI is not set +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_IMX=y +CONFIG_IMX2_WDT=y +CONFIG_IMX_DMA=y +CONFIG_IMX_SDMA=y +# CONFIG_IMX_WEIM is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD=y +CONFIG_JBD2=y +CONFIG_LIBFDT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_MXC is not set +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_GPMI_NAND=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MX3_IPU is not set +CONFIG_MXS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +# CONFIG_PCIE_IPROC is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_IMX6=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX=y +CONFIG_PINCTRL_IMX6Q=y +CONFIG_PINCTRL_IMX6SL=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +# CONFIG_PL310_ERRATA_753970 is not set +CONFIG_PL310_ERRATA_769419=y +CONFIG_PM_OPP=y +CONFIG_PPS=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_MXC is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SCHED_HRTICK=y +CONFIG_SCSI=y +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +# CONFIG_SOC_IMX50 is not set +# CONFIG_SOC_IMX51 is not set +# CONFIG_SOC_IMX53 is not set +CONFIG_SOC_IMX6=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +# CONFIG_SOC_IMX6SX is not set +# CONFIG_SOC_LS1021A is not set +# CONFIG_SOC_VF610 is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_IMX=y +CONFIG_SPI_MASTER=y +CONFIG_SRAM=y +CONFIG_SRCU=y +CONFIG_STMP_DEVICE=y +CONFIG_STOP_MACHINE=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_USB_MXS_PHY is not set +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_3G is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/imx6/files-3.18/drivers/net/phy/gw16083.c b/target/linux/imx6/files-3.18/drivers/net/phy/gw16083.c new file mode 100644 index 0000000..66b5536 --- /dev/null +++ b/target/linux/imx6/files-3.18/drivers/net/phy/gw16083.c @@ -0,0 +1,949 @@ +/* + * drivers/net/phy/gw16083.c + * + * Driver for GW16083 Ventana Ethernet Expansion Mezzanine + * + * Author: Tim Harvey + * + * Copyright (c) 2014 Tim Harvey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/* + * The GW16083 interfaces with a Ventana baseboard via the PCIe bus, an i2c + * bus (i2c2), and a couple of GPIO's. On the PCIe bus is an i210 GigE with + * its MAC connected to Port4 of a Marvell MV88E6176 7-port GigE switch via + * MDIO and RGMII. Ports 0-3 are standard copper RJ45 but Ports 5 and 6 + * connect to Marvell MV88E1111 dual-mode Copper/Fiber PHY's over SGMII and + * MDIO. The PHY's have both an RG45 for copper and an SFP module. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "gw16083.h" + +#undef FAIL_ON_CHECKSUM_ERR /* fail to configure SFP if checksum bad */ +#define PORT_POWER_CONTROL /* ports can be enabled/disabled via sysfs */ +#define PORT_MODE_CONTROL /* ports 5/6 can have SFP/RJ45 mode forced */ + +MODULE_DESCRIPTION("GW16083 driver"); +MODULE_AUTHOR("Tim Harvey"); +MODULE_LICENSE("GPL"); + +struct mv88e1111_port_state { + int port; + bool present; + bool serdes; + bool sfp_signal; + bool sfp_present; + bool sfp_compat; + bool sfp_enabled; + char sfp_id[64]; +}; + +struct mv88e1111_priv { + struct phy_device *phydev; + struct i2c_client *client; + struct mv88e1111_port_state port5; + struct mv88e1111_port_state port6; + struct kobject *sysfs_kobj; +}; + +enum { + mode_copper = 0, + mode_serdes = 1, +}; + +static struct i2c_client *gw16083_client = NULL; + +static int gw16083_read_port_sfp(struct i2c_client *client, + struct mv88e1111_port_state *state); + +/* read switch port register from port0-6 */ +u16 read_switch_port(struct phy_device *pdev, int port, u8 regaddr) +{ + return pdev->bus->read(pdev->bus, MV_BASE + port, regaddr); +} + +/* write switch port register to port0-6 */ +int write_switch_port(struct phy_device *pdev, int port, u8 regaddr, u16 val) +{ + return pdev->bus->write(pdev->bus, MV_BASE + port, regaddr, val); +} + +/* + * read_switch_port_phy - write a register for a specific port on 88E6176 + * The 88E6176 PHY registers must be accessed thorugh the Global2 address + * using the SMI_PHY_COMMAND_REG and SMI_PHY_DATA_REG. + */ +int read_switch_port_phy(struct phy_device *pdev, int port, u8 regaddr) +{ + u16 reg; + int i; + + dev_dbg(&pdev->dev, "read_phy: port%d reg=0x%02x\n", port, regaddr); + reg = SMIBUSY | SMIMODE22 | SMIOP_READ; + reg |= port << DEVADDR; + reg |= regaddr << REGADDR; + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SMI_PHY_COMMAND, reg); + for (i = 0; i < 10; i++) { + reg = pdev->bus->read(pdev->bus, MV_GLOBAL2, + MV_SMI_PHY_COMMAND); + if (!(reg & (1<<15))) + break; + mdelay(1); + } + /* timeout */ + if (i == 10) + return 0xffff; + reg = pdev->bus->read(pdev->bus, MV_GLOBAL2, MV_SMI_PHY_DATA); + return reg; +} + +/* + * write_switch_port_phy - write a register for a specific port on 88E6176 + * The 88E6176 PHY registers must be accessed thorugh the Global2 address + * using the SMI_PHY_COMMAND_REG and SMI_PHY_DATA_REG. + */ +int write_switch_port_phy(struct phy_device *pdev, int port, u8 addr, u16 reg) +{ + int i; + + dev_dbg(&pdev->dev, "write_phy: port%d reg=0x%02x val=0x%04x\n", port, + addr, reg); + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SMI_PHY_DATA, reg); + reg = SMIBUSY | SMIMODE22 | SMIOP_WRITE; + reg |= port << DEVADDR; + reg |= addr << REGADDR; + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SMI_PHY_COMMAND, reg); + for (i = 0; i < 10; i++) { + reg = pdev->bus->read(pdev->bus, MV_GLOBAL2, + MV_SMI_PHY_COMMAND); + if (!(reg & (1<<15))) + break; + mdelay(1); + } + /* timeout */ + if (i == 10) + return -ETIMEDOUT; + + return 0; +} + +/* read a scratch register from switch */ +inline u8 read_switch_scratch(struct phy_device *pdev, u8 reg) +{ + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SCRATCH_MISC, (reg << 8)); + return pdev->bus->read(pdev->bus, MV_GLOBAL2, MV_SCRATCH_MISC) & 0xff; +} + +/* write a scratch register to switch */ +inline void write_switch_scratch(struct phy_device *pdev, u8 reg, u8 val) +{ + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SCRATCH_MISC, + (1 << 15) | (reg << 8) | val); +} + +/* enable or disable an SFP's TXEN signal */ +static int enable_sfp_txen(struct phy_device *pdev, int port, bool enable) +{ + u8 gpio; + int bit; + + if (port != 5 && port != 6) + return -EINVAL; + + /* GPIO[2:1] output low to enable TXEN */ + bit = (port == 5) ? 1 : 2; + gpio = read_switch_scratch(pdev, MV_GPIO_DATA); + if (enable) + gpio |= (1 << bit); + else + gpio &= (1 << bit); + write_switch_scratch(pdev, MV_GPIO_DATA, gpio); + dev_info(&pdev->dev, "Port%d: SFP TX %s\n", port, enable ? + "enabled" : "disabled"); + return 0; +} + +/* configure mv88e1111 port for copper or serdes + * For Copper we set auto link/duplex/speed detection + * For SerDes/Fiber we force 1000mbps link up and auto-neg duplex + */ +static int config_mv88e1111_port_sfp(struct phy_device *pdev, int port, + bool sfp) +{ + u16 reg; + + if (port != 5 && port != 6) + return -EINVAL; + + dev_dbg(&pdev->dev, "%s: Port%d %s\n", __func__, port, + sfp ? "SFP" : "copper"); + if (sfp) { + enable_sfp_txen(pdev, port, 1); + + /* configure MV88E6176 Physical Control Port Register */ + dev_info(&pdev->dev, + "Port%d: SFP: force 1000mbps link up " + "(auto-negotiate duplex)\n", + port); + reg = read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL); + reg &= ~0x3f; /* clear 5-0 */ + reg |= (1 << 4) | (1 << 5); /* force link up */ + reg |= 2; /* force 1000mbps */ + write_switch_port(pdev, port, MV_PORT_PHYS_CONTROL, reg); + reg = read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL); + } + + /* copper */ + else { + enable_sfp_txen(pdev, port, 0); + + /* configure MV88E6176 Physical Control Port Register */ + dev_info(&pdev->dev, + "Port%d: Copper: set auto-neg link/duplex/speed\n", + port); + reg = read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL); + reg &= ~0x3f; /* clear 5-0 */ + reg |= 3; /* speed not forced */ + write_switch_port(pdev, port, MV_PORT_PHYS_CONTROL, reg); + reg = read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL); + } + dev_dbg(&pdev->dev, "%s: Port%d %s PORT_PHYS_CONTROL=0x%04x\n", + __func__, port, sfp ? "SFP" : "copper", + read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL)); + + return 0; +} + +#if defined(PORT_POWER_CONTROL) +static int enable_switch_port(struct phy_device *pdev, int port, bool enable) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(&pdev->dev); + u16 reg; + + /* power up port */ + dev_info(&priv->client->dev, "Port%d: %s\n", port, + enable ? "normal operation" : "power down"); + reg = read_switch_port_phy(pdev, port, MV_PHY_CONTROL); + if (enable) + reg &= ~(1 << 11); /* Normal Operation */ + else + reg |= (1 << 11); /* power down */ + write_switch_port_phy(pdev, port, MV_PHY_CONTROL, reg); + + reg = read_switch_port_phy(pdev, port, MV_PHY_CONTROL1); + if (enable) + reg &= ~(1 << 2); /* Normal Operation */ + else + reg |= (1 << 2); /* power down */ + write_switch_port_phy(pdev, port, MV_PHY_CONTROL1, reg); + + return 0; +} +#endif + +/* + * Sysfs API + */ + +struct mv88e1111_port_state *get_port_state(struct mv88e1111_priv *priv, + int port) +{ + if (port == 5) + return &priv->port5; + if (port == 6) + return &priv->port6; + return NULL; +} + +/* + * get MV88E6176 port number for a specific GW16083 port name + * The GW16083 ports as shown on the silkscreen are not mapped according to + * the MV88E6176 ports numbers. + */ +static int gw16083_get_port(const char* name) +{ + int i; + int map[] = { 3, 2, 1, 0, 5, 6 }; + + if (strncasecmp(name, "ETHERNET", 8) != 0 || strlen(name) != 9) + return -1; + i = name[8] - '0'; + if (i < 1 || i > 6) + return -1; + return map[i-1]; +} + +static ssize_t port_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + int port = -1; + u16 reg; + + if (sscanf(attr->attr.name, "port%d", &port) != 1) + return 0; + if (port < 0 || port > 6) + return 0; + reg = read_switch_port_phy(priv->phydev, port, MV_PHY_CONTROL); + return sprintf(buf, "%s\n", (reg & (1 << 11)) ? "disabled" : "enabled"); +} + +#if defined(PORT_POWER_CONTROL) +static ssize_t port_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + int port = -1; + int val; + + port = gw16083_get_port(attr->attr.name); + if (port < 0) + return 0; + if (sscanf(buf, "%d", &val) != 1) + return 0; + enable_switch_port(priv->phydev, port, val ? 1 : 0); + return count; +} + +static DEVICE_ATTR(ethernet1, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet2, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet3, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet4, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet5, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet6, S_IWUSR | S_IRUGO, port_show, port_store); +#else +static DEVICE_ATTR(ethernet1, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet2, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet3, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet4, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet5, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet6, S_IRUGO, port_show, NULL); +#endif + +static ssize_t portsfp_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + struct mv88e1111_port_state *state; + + state = get_port_state(priv, gw16083_get_port(attr->attr.name)); + if (!state) + return 0; + + if (!state->sfp_present) + return 0; + + return sprintf(buf, "%s\n", state->sfp_id); +} + +static ssize_t portmode_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + struct mv88e1111_port_state *state; + + state = get_port_state(priv, gw16083_get_port(attr->attr.name)); + if (!state) + return 0; + + return sprintf(buf, "%s\n", state->serdes ? "SFP" : "RJ45"); +} +static DEVICE_ATTR(ethernet5_sfp, S_IRUGO, portsfp_show, NULL); +static DEVICE_ATTR(ethernet6_sfp, S_IRUGO, portsfp_show, NULL); + +#ifdef PORT_MODE_CONTROL +static ssize_t portmode_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + struct mv88e1111_port_state *state; + u16 reg; + int port; + + port = gw16083_get_port(attr->attr.name); + state = get_port_state(priv, port); + if (!state) + return 0; + + reg = read_switch_port_phy(priv->phydev, port, MII_M1111_PHY_EXT_SR); + if (strcasecmp(buf, "auto") == 0) { + reg &= ~(1<<15); /* enable auto-selection */ + dev_info(&priv->client->dev, "Port%d: enable auto-selection\n", + port); + } else if (strcasecmp(buf, "RJ45") == 0) { + reg |= (1<<15); /* disable auto-selection */ + reg |= 0xb; /* RGMII to Copper */ + config_mv88e1111_port_sfp(priv->phydev, port, 0); + dev_info(&priv->client->dev, "Port%d: select RJ45\n", port); + } else if (strcasecmp(buf, "SFP") == 0) { + reg |= (1<<15); /* disable auto-selection */ + reg |= 0x3; /* RGMII to Fiber */ + config_mv88e1111_port_sfp(priv->phydev, port, 1); + dev_info(&priv->client->dev, "Port%d: select SFP\n", port); + } + write_switch_port_phy(priv->phydev, port, MII_M1111_PHY_EXT_SR, reg); + + return count; +} + +static DEVICE_ATTR(ethernet5_mode, S_IWUSR | S_IRUGO, portmode_show, + portmode_store); +static DEVICE_ATTR(ethernet6_mode, S_IWUSR | S_IRUGO, portmode_show, + portmode_store); +#else +static DEVICE_ATTR(ethernet5_mode, S_IRUGO, portmode_show, NULL); +static DEVICE_ATTR(ethernet6_mode, S_IRUGO, portmode_show, NULL); +#endif + + +/* + * PHY driver + */ + +static int +mv88e6176_config_init(struct phy_device *pdev) +{ + dev_dbg(&pdev->dev, "%s\n", __func__); + pdev->state = PHY_RUNNING; + + return 0; +} + +/* check MV88E1111 PHY status and MV88E6176 GPIO */ +static int +mv88e6176_read_status(struct phy_device *pdev) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(&pdev->dev); + struct mv88e1111_port_state *state; + bool serdes, sfp_present, sfp_signal; + int port; + int ret = 0; + u16 gpio; + + dev_dbg(&pdev->dev, "%s", __func__); + gpio = read_switch_scratch(pdev, MV_GPIO_DATA); + for (port = 5; port < 7; port++) { + serdes = (read_switch_port_phy(pdev, port, MII_M1111_PHY_EXT_SR) + & (1<<13)) ? 1 : 0; + dev_dbg(&pdev->dev, "%s: Port%d GPIO:0x%02x SerDes:%d\n", + __func__, port, gpio, serdes); + switch(port) { + case 5: + state = &priv->port5; + sfp_present = !((gpio >> 5) & 1); + sfp_signal = !((gpio >> 6) & 1); + break; + case 6: + state = &priv->port6; + sfp_present = !((gpio >> 3) & 1); + sfp_signal = !((gpio >> 4) & 1); + break; + } + + /* + * on sfp_detect read/verify SFP MSA and set sfp_compat + * on sfp_signal issue link down? + * on serdes auto-select + */ + if (state->sfp_present != sfp_present) { + state->sfp_present = sfp_present; + dev_info(&pdev->dev, "Port%d: SFP %s\n", + port, sfp_present ? "inserted" : "removed"); + if (state->sfp_present) { + if (gw16083_read_port_sfp(priv->client, state)) + state->sfp_compat = false; + else + state->sfp_compat = true; + } else { + state->sfp_compat = false; + state->sfp_enabled = false; + } + } + if (state->sfp_signal != sfp_signal) { + state->sfp_signal = sfp_signal; + dev_info(&pdev->dev, "Port%d: SFP signal %s\n", + port, sfp_signal ? "detected" : "lost"); + } + if (state->serdes != serdes) { + state->serdes = serdes; + dev_info(&pdev->dev, "Port%d: %s auto-selected\n", + port, serdes ? "SERDES" : "copper"); + + /* + * if auto-selection has switched to copper + * disable serdes + */ + if (!serdes) { + config_mv88e1111_port_sfp(pdev, port, 0); + state->sfp_enabled = false; + } + } + + /* + * if serdes and compatible SFP module and not yet enabled + * then enable for serdes + */ + if (serdes && state->sfp_compat && state->sfp_signal && + !state->sfp_enabled) + { + if (!config_mv88e1111_port_sfp(pdev, port, 1)) + state->sfp_enabled = true; + } + } + + return ret; +} + +static int +mv88e6176_config_aneg(struct phy_device *pdev) +{ + dev_dbg(&pdev->dev, "%s", __func__); + return 0; +} + +static void +mv88e6176_remove(struct phy_device *pdev) +{ + dev_dbg(&pdev->dev, "%s", __func__); + + device_remove_file(&pdev->dev, &dev_attr_ethernet1); + device_remove_file(&pdev->dev, &dev_attr_ethernet2); + device_remove_file(&pdev->dev, &dev_attr_ethernet3); + device_remove_file(&pdev->dev, &dev_attr_ethernet4); + device_remove_file(&pdev->dev, &dev_attr_ethernet5); + device_remove_file(&pdev->dev, &dev_attr_ethernet6); + device_remove_file(&pdev->dev, &dev_attr_ethernet5_sfp); + device_remove_file(&pdev->dev, &dev_attr_ethernet6_sfp); + device_remove_file(&pdev->dev, &dev_attr_ethernet5_mode); + device_remove_file(&pdev->dev, &dev_attr_ethernet6_mode); + sysfs_remove_link(kernel_kobj, "gw16083"); +} + +static int +mv88e6176_probe(struct phy_device *pdev) +{ + int port; + int ret = 0; + u32 id, reg; + struct mv88e1111_priv *priv; + + dev_dbg(&pdev->dev, "%s: addr=0x%02x bus=%s:%s gw16083_client=%p\n", + __func__, pdev->addr, pdev->bus->name, pdev->bus->id, + gw16083_client); + + /* In single-chip addressing mode the MV88E6176 shows up on 0x10-0x16 */ + if (pdev->addr != MV_BASE) + return 0; + + /* i2c driver needs to be loaded first */ + if (!gw16083_client) + return 0; + + /* gw16083 has MV88E1676 hanging off of i210 mdio bus */ + if (strcmp(pdev->bus->name, "igb_enet_mii_bus") != 0) + return 0; + + //dev_info(&pdev->dev, "Detected"); + dev_info(&gw16083_client->dev, "%s: MV88E6176 7-port switch detected", + pdev->bus->id); + + /* + * port5/6 config: MV88E1111 PHY + * Register 20: PHY Control Register + * R20_7: add delay to RX_CLK for RXD + * R20_1: add delay to TX_CLK for TXD + * Register 24: LED Control Register + * 0x4111: + * Pulse stretch 170 to 340 ms + * Register 0: Control Register + * R0_15: phy reset + */ + for (port = 5; port < 7; port++) { +#ifndef RGMII_DELAY_ON_PHY + write_switch_port(pdev, port, MV_PORT_PHYS_CONTROL, 0xC003); +#endif + + id = read_switch_port_phy(pdev, port, + MII_M1111_PHY_IDENT0) << 16; + id |= read_switch_port_phy(pdev, port, MII_M1111_PHY_IDENT1); + if ((id & MII_M1111_PHY_ID_MASK) != MII_M1111_PHY_ID) { + dev_err(&gw16083_client->dev, + "Port%d: No MV88E1111 PHY detected", port); + return 0; + //continue; + } + +#ifdef RGMII_DELAY_ON_PHY + /* phy rx/tx delay */ + reg = read_switch_port_phy(pdev, port, MII_M1111_PHY_EXT_CR); + reg |= (1<<1) | (1<<7); + write_switch_port_phy(pdev, port, MII_M1111_PHY_EXT_CR, reg); +#endif + /* led config */ + write_switch_port_phy(pdev, port, MII_M1111_PHY_LED_CONTROL, + MII_M1111_PHY_LED_PULSE_STR); + /* reset phy */ + reg = read_switch_port_phy(pdev, port, MII_M1111_PHY_CONTROL); + reg |= MII_M1111_PHY_CONTROL_RESET; + write_switch_port_phy(pdev, port, MII_M1111_PHY_CONTROL, reg); + dev_info(&gw16083_client->dev, + "Port%d MV88E111 PHY configured\n", port); + } + + /* + * GPIO Configuration: + * GPIO1: FIB5_TXEN# (output) + * GPIO2: FIB6_TXEN# (output) + * GPIO3: FIB6_PRES# (input) + * GPIO4: FIB6_LOS (input) + * GPIO5: FIB5_PRES# (input) + * GPIO6: FIB5_LOS (input) + */ + write_switch_scratch(pdev, MV_GPIO_DATA, 0x06); /* GPIO[2:1] out hi */ + write_switch_scratch(pdev, MV_GPIO_DIR, 0x78); /* GPIO[6:3] inp */ + + pdev->irq = PHY_POLL; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + memset(priv, 0, sizeof(*priv)); + priv->phydev = pdev; + priv->client = gw16083_client; + priv->port5.port = 5; + priv->port6.port = 6; + dev_set_drvdata(&pdev->dev, priv); + + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet1); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet2); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet3); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet4); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet5); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet6); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet5_sfp); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet6_sfp); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet5_mode); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet6_mode); + + if (unlikely(ret)) + dev_err(&pdev->dev, "Failed creating attrs\n"); + + /* Add a nice symlink to the real device */ + ret = sysfs_create_link(kernel_kobj, &pdev->dev.kobj, "gw16083"); + + dev_dbg(&pdev->dev, "initial state: GPIO=0x%02x " + "Port5_serdes=%d Port6_serdes=%d\n", + read_switch_scratch(pdev, MV_GPIO_DATA), + (read_switch_port_phy(pdev, 5, MII_M1111_PHY_EXT_SR) + & (1<<13) ? 1:0), + (read_switch_port_phy(pdev, 6, MII_M1111_PHY_EXT_SR) + & (1<<13) ? 1:0)); + + return ret; +} + +static struct phy_driver mv88e6176_phy_driver = { + .name = "MV88E6176", + .phy_id = MV_IDENT_VALUE, + .phy_id_mask = MV_IDENT_MASK, + .features = PHY_BASIC_FEATURES, + .probe = &mv88e6176_probe, + .remove = &mv88e6176_remove, + .config_init = &mv88e6176_config_init, + .config_aneg = &mv88e6176_config_aneg, + .read_status = &mv88e6176_read_status, + .driver = { .owner = THIS_MODULE }, +}; + +/* + * I2C driver + */ + +/* See SFF-8472 */ +struct sfp_msa { + /* Basic ID fields */ + u8 identifier; + u8 ext_identifier; + u8 connector; + u8 transceiver[8]; + u8 encoding; + u8 br_nominal; + u8 rate_identifier; + u8 length_smf_km; + u8 length_smf; + u8 length_om2; + u8 length_om1; + u8 length_om4; + u8 length_om3; + u8 vendor_name[16]; + u8 transceiver2; + u8 vendor_oui[3]; + u8 vendor_pn[16]; + u8 vendor_rev[4]; + u8 wavelength[2]; + u8 resv1; + u8 cc_base; + + /* extended id fields */ + u8 options[2]; + u8 br_max; + u8 br_min; + u8 vendor_sn[16]; + u8 date_code[8]; + u8 diags_type; + u8 enhanced_options; + u8 sff8472_compliance; + u8 cc_ext; + + /* Vendor specific ID fields */ + u8 vendor_data[32]; + u8 sff8079[128]; +}; + +enum identifier { + UNKNOWN, + GBIC, + SFF, + SFP, + XBI, + XENPACK, + XFP, + XFF, + XFP_E, + XPAK, + X2, + DWDM_SFP, + QSFP, + MAX_ID, +}; + +const char* id_names[] = { + "UNKONWN", + "GBIC", + "SFF", + "SFP", + NULL, +}; + +/* Flags for SFP modules compatible with ETH up to 1Gb */ +struct sfp_flags { + u8 e1000_base_sx:1; + u8 e1000_base_lx:1; + u8 e1000_base_cx:1; + u8 e1000_base_t:1; + u8 e100_base_lx:1; + u8 e100_base_fx:1; + u8 e10_base_bx10:1; + u8 e10_base_px:1; +}; + +#define STRING_APPEND(str, src) \ + strncat(str, src, sizeof(src)); \ + for (i = 1; i < sizeof(str); i++) \ + if (str[i-1] == ' ' && str[i] == ' ') \ + str[i] = 0; + +static int gw16083_read_port_sfp(struct i2c_client *client, + struct mv88e1111_port_state *state) +{ + int ret = 0; + u8 data[256]; + struct sfp_flags *eth_flags; + u8 crc; + int i; + u8 *str; + struct sfp_msa *sfp_msa = (struct sfp_msa *)data; + int port = state->port; + union i2c_smbus_data d; + + dev_dbg(&client->dev, "%s Port%d\n", __func__, port); + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) + return -ENODEV; + d.byte = (port == 5) ? 1 : 2; + if (i2c_smbus_xfer(client->adapter, GW16083_I2C_ADDR_PCA9543, + client->flags, I2C_SMBUS_WRITE, 0, + I2C_SMBUS_BYTE_DATA, &d) < 0) + { + dev_err(&client->dev, + "Port%d: failed writing PCA9543 register\n", port); + return ret; + } + + /* read all 256 bytes of SFP EEPROM */ + for (i = 0; i < sizeof(data); i += I2C_SMBUS_BLOCK_MAX) { + d.block[0] = I2C_SMBUS_BLOCK_MAX; + if (i2c_smbus_xfer(client->adapter, GW16083_I2C_ADDR_SFP1, + client->flags, I2C_SMBUS_READ, i, + I2C_SMBUS_I2C_BLOCK_DATA, &d) < 0) + { + dev_err(&client->dev, + "Port%d: failed reading SFP data\n", port); + return ret; + } + memcpy(data + i, d.block + 1, I2C_SMBUS_BLOCK_MAX); + } + + /* Validate checksums */ + for (crc = 0, i = 0; i < 63; i++) + crc += data[i]; + if (crc != sfp_msa->cc_base) { + dev_err(&client->dev, "Port%d: " + "Checksum failure for Base ID fields: 0x%02x\n", port, + crc); +#ifdef FAIL_ON_CHECKSUM_ERR + return -EINVAL; +#endif + } + for (crc = 0, i = 64; i < 95; i++) + crc += data[i]; + if (crc != sfp_msa->cc_ext) { + dev_err(&client->dev, "Port%d: " + "Checksum failure for Extended ID fields: 0x%02x\n", + port, crc); +#ifdef FAIL_ON_CHECKSUM_ERR + return -EINVAL; +#endif + } + state->sfp_id[0] = 0; + for (i = 0; id_names[i]; i++) { + if (sfp_msa->identifier == i) { + sprintf(state->sfp_id, "%s: ", id_names[i]); + break; + } + } + STRING_APPEND(state->sfp_id, sfp_msa->vendor_oui); + STRING_APPEND(state->sfp_id, sfp_msa->vendor_name); + STRING_APPEND(state->sfp_id, sfp_msa->vendor_pn); + STRING_APPEND(state->sfp_id, sfp_msa->vendor_rev); + STRING_APPEND(state->sfp_id, sfp_msa->vendor_sn); + dev_info(&client->dev, "Port%d: %s\n", port, state->sfp_id); + + if ((sfp_msa->identifier != GBIC) && + (sfp_msa->identifier != SFF) && + (sfp_msa->identifier != SFP)) + { + dev_err(&client->dev, "Port%d: Unknown module identifier: %d\n", + port, sfp_msa->identifier); + return -EINVAL; + } + + str = ""; + eth_flags = (struct sfp_flags *)(sfp_msa->transceiver + 3); + if (eth_flags->e1000_base_sx) { + str = "1000Base-SX (Fiber)"; + } else if (eth_flags->e1000_base_lx) { + str = "1000Base-LX (Fiber)"; + } else if (eth_flags->e1000_base_t) { + str = "1000Base-T (Copper)"; + } else if (eth_flags->e100_base_fx) { + str = "100Base-FX (Fiber) - not supported"; + ret = -EINVAL; + } else { + str = "Unknown/Unsupported media type"; + ret = -EINVAL; + } + if (ret) + dev_err(&client->dev, "Port%d: %s (0x%02x)\n", port, str, + sfp_msa->transceiver[3]); + else + dev_info(&client->dev, "Port%d: %s (0x%02x)\n", port, str, + sfp_msa->transceiver[3]); + + return ret; +} + +static int gw16083_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + + dev_info(&client->dev, "GW16083 Ethernet Expansion Mezzanine\n"); + if (gw16083_client) { + dev_err(&client->dev, "client already registered\n"); + return -EINVAL; + } + gw16083_client = client; + + ret = phy_driver_register(&mv88e6176_phy_driver); + if (ret) + dev_err(&client->dev, + "failed to register mv88e6176 phy driver: %d\n", ret); + return ret; +} + +static int gw16083_remove(struct i2c_client *client) +{ + dev_dbg(&client->dev, "%s\n", __func__); + + phy_driver_unregister(&mv88e6176_phy_driver); + gw16083_client = NULL; + return 0; +} + +static const struct of_device_id gw16083_dt_ids[] = { + { .compatible = "gateworks,gw16083", }, + { } +}; + +MODULE_DEVICE_TABLE(of, gw16083_dt_ids); + +static const struct i2c_device_id gw16083_id[] = { + { "gw16083", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, gw16083_id); + +static struct i2c_driver gw16083_driver = { + .driver = { + .name = "gw16083", + .of_match_table = gw16083_dt_ids, + }, + .probe = gw16083_probe, + .remove = gw16083_remove, + .id_table = gw16083_id, +}; + +static int __init mv88e6176_init(void) +{ + return i2c_add_driver(&gw16083_driver); +} + +static void __exit mv88e6176_exit(void) +{ + i2c_del_driver(&gw16083_driver); +} + +module_init(mv88e6176_init); +module_exit(mv88e6176_exit); diff --git a/target/linux/imx6/files-3.18/drivers/net/phy/gw16083.h b/target/linux/imx6/files-3.18/drivers/net/phy/gw16083.h new file mode 100644 index 0000000..db96f2b --- /dev/null +++ b/target/linux/imx6/files-3.18/drivers/net/phy/gw16083.h @@ -0,0 +1,123 @@ +/* + * drivers/net/phy/mv88e6176.h + * + * Driver for Marvell Switch + * + * Author: Tim Harvey + * + * Copyright (c) 2014 Tim Harvey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _GW16083_H_ +#define _GW16083_H_ + +#define MII_MARVELL_PHY_PAGE 22 + +/* + * I2C Addresses + */ +#define GW16083_I2C_ADDR_SFP1 0x50 +#define GW16083_I2C_ADDR_SFP2 0x51 +#define GW16083_I2C_ADDR_EEPROM 0x52 +#define GW16083_I2C_ADDR_PCA9543 0x70 + +/* + * MV88E1111 PHY Registers + */ +enum { + MII_M1111_PHY_CONTROL = 0, + MII_M1111_PHY_STATUS = 1, + MII_M1111_PHY_IDENT0 = 2, + MII_M1111_PHY_IDENT1 = 3, + MII_M1111_PHY_EXT_CR = 20, + MII_M1111_PHY_LED_CONTROL = 24, + MII_M1111_PHY_EXT_SR = 27, +}; + +#define MII_M1111_PHY_ID_MASK 0xfffffff0 +#define MII_M1111_PHY_ID 0x01410cc0 + +#define MII_M1111_PHY_CONTROL_RESET (1 << 15) +#define MII_M1111_PHY_LED_DIRECT 0x4100 +#define MII_M1111_PHY_LED_PULSE_STR 0x4111 +#define MII_M1111_PHY_LED_COMBINE 0x411c +#define MII_M1111_RX_DELAY 0x80 +#define MII_M1111_TX_DELAY 0x2 + +/* + * MV88E6176 Switch Registers + */ + +/* PHY Addrs */ +#define MV_BASE 0x10 +#define MV_GLOBAL1 0x1b +#define MV_GLOBAL2 0x1c +#define MV_GLOBAL3 0x1d + +/* Global2 Registers */ +enum { + MV_SMI_PHY_COMMAND = 0x18, + MV_SMI_PHY_DATA = 0x19, + MV_SCRATCH_MISC = 0x1A, +}; + +/* Scratch And Misc Reg offsets */ +enum { + MV_GPIO_MODE = 0x60, + MV_GPIO_DIR = 0x62, + MV_GPIO_DATA = 0x64, + MV_GPIO76_CNTL = 0x6B, + MV_GPIO54_CNTL = 0x6A, + MV_GPIO32_CNTL = 0x69, + MV_GPIO10_CNTL = 0x68, + MV_CONFIG0 = 0x70, + MV_CONFIG1 = 0x71, + MV_CONFIG2 = 0x72, + MV_CONFIG3 = 0x73, +}; + +/* PHY Registers */ +enum { + MV_PHY_CONTROL = 0x00, + MV_PHY_STATUS = 0x01, + MV_PHY_IDENT0 = 0x02, + MV_PHY_IDENT1 = 0x03, + MV_PHY_ANEG = 0x04, + MV_PHY_LINK_ABILITY = 0x05, + MV_PHY_ANEG_EXPAND = 0x06, + MV_PHY_XMIT_NEXTP = 0x07, + MV_PHY_LINK_NEXTP = 0x08, + MV_PHY_CONTROL1 = 0x10, + MV_PHY_STATUS1 = 0x11, + MV_PHY_INTR_EN = 0x12, +}; + +/* Port Registers */ +enum { + MV_PORT_STATUS = 0x00, + MV_PORT_PHYS_CONTROL = 0x01, + MV_PORT_IDENT = 0x03, + MV_PORT_CONTROL = 0x04, + MV_PORT_VLANMAP = 0x06, + MV_PORT_ASSOC = 0x0b, + MV_PORT_RXCOUNT = 0x10, + MV_PORT_TXCOUNT = 0x11, +}; + +#define SMIBUSY (1<<15) +#define SMIMODE22 (1<<12) +#define SMIOP_READ (2<<10) +#define SMIOP_WRITE (1<<10) +#define DEVADDR 5 +#define REGADDR 0 + +#define MV_IDENT_MASK 0x0000fff0 +#define MV_IDENT_VALUE 0x00001760 + +#endif /* _GW16083_H_ */ diff --git a/target/linux/imx6/files-4.1/drivers/net/phy/gw16083.c b/target/linux/imx6/files-4.1/drivers/net/phy/gw16083.c new file mode 100644 index 0000000..e41577b --- /dev/null +++ b/target/linux/imx6/files-4.1/drivers/net/phy/gw16083.c @@ -0,0 +1,950 @@ +/* + * drivers/net/phy/gw16083.c + * + * Driver for GW16083 Ventana Ethernet Expansion Mezzanine + * + * Author: Tim Harvey + * + * Copyright (c) 2014 Tim Harvey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +/* + * The GW16083 interfaces with a Ventana baseboard via the PCIe bus, an i2c + * bus (i2c2), and a couple of GPIO's. On the PCIe bus is an i210 GigE with + * its MAC connected to Port4 of a Marvell MV88E6176 7-port GigE switch via + * MDIO and RGMII. Ports 0-3 are standard copper RJ45 but Ports 5 and 6 + * connect to Marvell MV88E1111 dual-mode Copper/Fiber PHY's over SGMII and + * MDIO. The PHY's have both an RG45 for copper and an SFP module. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "gw16083.h" + +#undef FAIL_ON_CHECKSUM_ERR /* fail to configure SFP if checksum bad */ +#define PORT_POWER_CONTROL /* ports can be enabled/disabled via sysfs */ +#define PORT_MODE_CONTROL /* ports 5/6 can have SFP/RJ45 mode forced */ + +MODULE_DESCRIPTION("GW16083 driver"); +MODULE_AUTHOR("Tim Harvey"); +MODULE_LICENSE("GPL"); + +struct mv88e1111_port_state { + int port; + bool present; + bool serdes; + bool sfp_signal; + bool sfp_present; + bool sfp_compat; + bool sfp_enabled; + char sfp_id[64]; +}; + +struct mv88e1111_priv { + struct phy_device *phydev; + struct i2c_client *client; + struct mv88e1111_port_state port5; + struct mv88e1111_port_state port6; + struct kobject *sysfs_kobj; +}; + +enum { + mode_copper = 0, + mode_serdes = 1, +}; + +static struct i2c_client *gw16083_client = NULL; + +static int gw16083_read_port_sfp(struct i2c_client *client, + struct mv88e1111_port_state *state); + +/* read switch port register from port0-6 */ +u16 read_switch_port(struct phy_device *pdev, int port, u8 regaddr) +{ + return pdev->bus->read(pdev->bus, MV_BASE + port, regaddr); +} + +/* write switch port register to port0-6 */ +int write_switch_port(struct phy_device *pdev, int port, u8 regaddr, u16 val) +{ + return pdev->bus->write(pdev->bus, MV_BASE + port, regaddr, val); +} + +/* + * read_switch_port_phy - write a register for a specific port on 88E6176 + * The 88E6176 PHY registers must be accessed thorugh the Global2 address + * using the SMI_PHY_COMMAND_REG and SMI_PHY_DATA_REG. + */ +int read_switch_port_phy(struct phy_device *pdev, int port, u8 regaddr) +{ + u16 reg; + int i; + + dev_dbg(&pdev->dev, "read_phy: port%d reg=0x%02x\n", port, regaddr); + reg = SMIBUSY | SMIMODE22 | SMIOP_READ; + reg |= port << DEVADDR; + reg |= regaddr << REGADDR; + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SMI_PHY_COMMAND, reg); + for (i = 0; i < 10; i++) { + reg = pdev->bus->read(pdev->bus, MV_GLOBAL2, + MV_SMI_PHY_COMMAND); + if (!(reg & (1<<15))) + break; + mdelay(1); + } + /* timeout */ + if (i == 10) + return 0xffff; + reg = pdev->bus->read(pdev->bus, MV_GLOBAL2, MV_SMI_PHY_DATA); + return reg; +} + +/* + * write_switch_port_phy - write a register for a specific port on 88E6176 + * The 88E6176 PHY registers must be accessed thorugh the Global2 address + * using the SMI_PHY_COMMAND_REG and SMI_PHY_DATA_REG. + */ +int write_switch_port_phy(struct phy_device *pdev, int port, u8 addr, u16 reg) +{ + int i; + + dev_dbg(&pdev->dev, "write_phy: port%d reg=0x%02x val=0x%04x\n", port, + addr, reg); + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SMI_PHY_DATA, reg); + reg = SMIBUSY | SMIMODE22 | SMIOP_WRITE; + reg |= port << DEVADDR; + reg |= addr << REGADDR; + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SMI_PHY_COMMAND, reg); + for (i = 0; i < 10; i++) { + reg = pdev->bus->read(pdev->bus, MV_GLOBAL2, + MV_SMI_PHY_COMMAND); + if (!(reg & (1<<15))) + break; + mdelay(1); + } + /* timeout */ + if (i == 10) + return -ETIMEDOUT; + + return 0; +} + +/* read a scratch register from switch */ +inline u8 read_switch_scratch(struct phy_device *pdev, u8 reg) +{ + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SCRATCH_MISC, (reg << 8)); + return pdev->bus->read(pdev->bus, MV_GLOBAL2, MV_SCRATCH_MISC) & 0xff; +} + +/* write a scratch register to switch */ +inline void write_switch_scratch(struct phy_device *pdev, u8 reg, u8 val) +{ + pdev->bus->write(pdev->bus, MV_GLOBAL2, MV_SCRATCH_MISC, + (1 << 15) | (reg << 8) | val); +} + +/* enable or disable an SFP's TXEN signal */ +static int enable_sfp_txen(struct phy_device *pdev, int port, bool enable) +{ + u8 gpio; + int bit; + + if (port != 5 && port != 6) + return -EINVAL; + + /* GPIO[2:1] output low to enable TXEN */ + bit = (port == 5) ? 1 : 2; + gpio = read_switch_scratch(pdev, MV_GPIO_DATA); + if (enable) + gpio |= (1 << bit); + else + gpio &= (1 << bit); + write_switch_scratch(pdev, MV_GPIO_DATA, gpio); + dev_info(&pdev->dev, "Port%d: SFP TX %s\n", port, enable ? + "enabled" : "disabled"); + return 0; +} + +/* configure mv88e1111 port for copper or serdes + * For Copper we set auto link/duplex/speed detection + * For SerDes/Fiber we force 1000mbps link up and auto-neg duplex + */ +static int config_mv88e1111_port_sfp(struct phy_device *pdev, int port, + bool sfp) +{ + u16 reg; + + if (port != 5 && port != 6) + return -EINVAL; + + dev_dbg(&pdev->dev, "%s: Port%d %s\n", __func__, port, + sfp ? "SFP" : "copper"); + if (sfp) { + enable_sfp_txen(pdev, port, 1); + + /* configure MV88E6176 Physical Control Port Register */ + dev_info(&pdev->dev, + "Port%d: SFP: force 1000mbps link up " + "(auto-negotiate duplex)\n", + port); + reg = read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL); + reg &= ~0x3f; /* clear 5-0 */ + reg |= (1 << 4) | (1 << 5); /* force link up */ + reg |= 2; /* force 1000mbps */ + write_switch_port(pdev, port, MV_PORT_PHYS_CONTROL, reg); + reg = read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL); + } + + /* copper */ + else { + enable_sfp_txen(pdev, port, 0); + + /* configure MV88E6176 Physical Control Port Register */ + dev_info(&pdev->dev, + "Port%d: Copper: set auto-neg link/duplex/speed\n", + port); + reg = read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL); + reg &= ~0x3f; /* clear 5-0 */ + reg |= 3; /* speed not forced */ + write_switch_port(pdev, port, MV_PORT_PHYS_CONTROL, reg); + reg = read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL); + } + dev_dbg(&pdev->dev, "%s: Port%d %s PORT_PHYS_CONTROL=0x%04x\n", + __func__, port, sfp ? "SFP" : "copper", + read_switch_port(pdev, port, MV_PORT_PHYS_CONTROL)); + + return 0; +} + +#if defined(PORT_POWER_CONTROL) +static int enable_switch_port(struct phy_device *pdev, int port, bool enable) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(&pdev->dev); + u16 reg; + + /* power up port */ + dev_info(&priv->client->dev, "Port%d: %s\n", port, + enable ? "normal operation" : "power down"); + reg = read_switch_port_phy(pdev, port, MV_PHY_CONTROL); + if (enable) + reg &= ~(1 << 11); /* Normal Operation */ + else + reg |= (1 << 11); /* power down */ + write_switch_port_phy(pdev, port, MV_PHY_CONTROL, reg); + + reg = read_switch_port_phy(pdev, port, MV_PHY_CONTROL1); + if (enable) + reg &= ~(1 << 2); /* Normal Operation */ + else + reg |= (1 << 2); /* power down */ + write_switch_port_phy(pdev, port, MV_PHY_CONTROL1, reg); + + return 0; +} +#endif + +/* + * Sysfs API + */ + +struct mv88e1111_port_state *get_port_state(struct mv88e1111_priv *priv, + int port) +{ + if (port == 5) + return &priv->port5; + if (port == 6) + return &priv->port6; + return NULL; +} + +/* + * get MV88E6176 port number for a specific GW16083 port name + * The GW16083 ports as shown on the silkscreen are not mapped according to + * the MV88E6176 ports numbers. + */ +static int gw16083_get_port(const char* name) +{ + int i; + int map[] = { 3, 2, 1, 0, 5, 6 }; + + if (strncasecmp(name, "ETHERNET", 8) != 0 || strlen(name) != 9) + return -1; + i = name[8] - '0'; + if (i < 1 || i > 6) + return -1; + return map[i-1]; +} + +static ssize_t port_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + int port = -1; + u16 reg; + + if (sscanf(attr->attr.name, "port%d", &port) != 1) + return 0; + if (port < 0 || port > 6) + return 0; + reg = read_switch_port_phy(priv->phydev, port, MV_PHY_CONTROL); + return sprintf(buf, "%s\n", (reg & (1 << 11)) ? "disabled" : "enabled"); +} + +#if defined(PORT_POWER_CONTROL) +static ssize_t port_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + int port = -1; + int val; + + port = gw16083_get_port(attr->attr.name); + if (port < 0) + return 0; + if (sscanf(buf, "%d", &val) != 1) + return 0; + enable_switch_port(priv->phydev, port, val ? 1 : 0); + return count; +} + +static DEVICE_ATTR(ethernet1, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet2, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet3, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet4, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet5, S_IWUSR | S_IRUGO, port_show, port_store); +static DEVICE_ATTR(ethernet6, S_IWUSR | S_IRUGO, port_show, port_store); +#else +static DEVICE_ATTR(ethernet1, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet2, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet3, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet4, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet5, S_IRUGO, port_show, NULL); +static DEVICE_ATTR(ethernet6, S_IRUGO, port_show, NULL); +#endif + +static ssize_t portsfp_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + struct mv88e1111_port_state *state; + + state = get_port_state(priv, gw16083_get_port(attr->attr.name)); + if (!state) + return 0; + + if (!state->sfp_present) + return 0; + + return sprintf(buf, "%s\n", state->sfp_id); +} + +static ssize_t portmode_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + struct mv88e1111_port_state *state; + + state = get_port_state(priv, gw16083_get_port(attr->attr.name)); + if (!state) + return 0; + + return sprintf(buf, "%s\n", state->serdes ? "SFP" : "RJ45"); +} +static DEVICE_ATTR(ethernet5_sfp, S_IRUGO, portsfp_show, NULL); +static DEVICE_ATTR(ethernet6_sfp, S_IRUGO, portsfp_show, NULL); + +#ifdef PORT_MODE_CONTROL +static ssize_t portmode_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(dev); + struct mv88e1111_port_state *state; + u16 reg; + int port; + + port = gw16083_get_port(attr->attr.name); + state = get_port_state(priv, port); + if (!state) + return 0; + + reg = read_switch_port_phy(priv->phydev, port, MII_M1111_PHY_EXT_SR); + if (strcasecmp(buf, "auto") == 0) { + reg &= ~(1<<15); /* enable auto-selection */ + dev_info(&priv->client->dev, "Port%d: enable auto-selection\n", + port); + } else if (strcasecmp(buf, "RJ45") == 0) { + reg |= (1<<15); /* disable auto-selection */ + reg |= 0xb; /* RGMII to Copper */ + config_mv88e1111_port_sfp(priv->phydev, port, 0); + dev_info(&priv->client->dev, "Port%d: select RJ45\n", port); + } else if (strcasecmp(buf, "SFP") == 0) { + reg |= (1<<15); /* disable auto-selection */ + reg |= 0x3; /* RGMII to Fiber */ + config_mv88e1111_port_sfp(priv->phydev, port, 1); + dev_info(&priv->client->dev, "Port%d: select SFP\n", port); + } + write_switch_port_phy(priv->phydev, port, MII_M1111_PHY_EXT_SR, reg); + + return count; +} + +static DEVICE_ATTR(ethernet5_mode, S_IWUSR | S_IRUGO, portmode_show, + portmode_store); +static DEVICE_ATTR(ethernet6_mode, S_IWUSR | S_IRUGO, portmode_show, + portmode_store); +#else +static DEVICE_ATTR(ethernet5_mode, S_IRUGO, portmode_show, NULL); +static DEVICE_ATTR(ethernet6_mode, S_IRUGO, portmode_show, NULL); +#endif + + +/* + * PHY driver + */ + +static int +mv88e6176_config_init(struct phy_device *pdev) +{ + dev_dbg(&pdev->dev, "%s\n", __func__); + pdev->state = PHY_RUNNING; + + return 0; +} + +/* check MV88E1111 PHY status and MV88E6176 GPIO */ +static int +mv88e6176_read_status(struct phy_device *pdev) +{ + struct mv88e1111_priv *priv = dev_get_drvdata(&pdev->dev); + struct mv88e1111_port_state *state; + bool serdes, sfp_present, sfp_signal; + int port; + int ret = 0; + u16 gpio; + + dev_dbg(&pdev->dev, "%s", __func__); + gpio = read_switch_scratch(pdev, MV_GPIO_DATA); + for (port = 5; port < 7; port++) { + serdes = (read_switch_port_phy(pdev, port, MII_M1111_PHY_EXT_SR) + & (1<<13)) ? 1 : 0; + dev_dbg(&pdev->dev, "%s: Port%d GPIO:0x%02x SerDes:%d\n", + __func__, port, gpio, serdes); + switch(port) { + case 5: + state = &priv->port5; + sfp_present = !((gpio >> 5) & 1); + sfp_signal = !((gpio >> 6) & 1); + break; + case 6: + state = &priv->port6; + sfp_present = !((gpio >> 3) & 1); + sfp_signal = !((gpio >> 4) & 1); + break; + } + + /* + * on sfp_detect read/verify SFP MSA and set sfp_compat + * on sfp_signal issue link down? + * on serdes auto-select + */ + if (state->sfp_present != sfp_present) { + state->sfp_present = sfp_present; + dev_info(&pdev->dev, "Port%d: SFP %s\n", + port, sfp_present ? "inserted" : "removed"); + if (state->sfp_present) { + if (gw16083_read_port_sfp(priv->client, state)) + state->sfp_compat = false; + else + state->sfp_compat = true; + /* trigger a re-select/enable below */ + state->serdes = !serdes; + pdev->state = PHY_RUNNING; + } else { + state->sfp_compat = false; + state->sfp_enabled = false; + pdev->state = PHY_NOLINK; + } + } + if (state->sfp_signal != sfp_signal) { + state->sfp_signal = sfp_signal; + dev_info(&pdev->dev, "Port%d: SFP signal %s\n", + port, sfp_signal ? "detected" : "lost"); + } + if (state->serdes != serdes) { + state->serdes = serdes; + dev_info(&pdev->dev, "Port%d: %s auto-selected\n", + port, serdes ? "SERDES" : "copper"); + + /* + * if auto-selection has switched to copper + * disable serdes + */ + if (!serdes) { + config_mv88e1111_port_sfp(pdev, port, 0); + state->sfp_enabled = false; + } + } + + /* if compatible SFP module and not yet enabled then enable */ + if (state->sfp_compat && state->sfp_signal && + !state->sfp_enabled) + { + if (!config_mv88e1111_port_sfp(pdev, port, 1)) + state->sfp_enabled = true; + } + } + + return ret; +} + +static int +mv88e6176_config_aneg(struct phy_device *pdev) +{ + dev_dbg(&pdev->dev, "%s", __func__); + return 0; +} + +static void +mv88e6176_remove(struct phy_device *pdev) +{ + dev_dbg(&pdev->dev, "%s", __func__); + + device_remove_file(&pdev->dev, &dev_attr_ethernet1); + device_remove_file(&pdev->dev, &dev_attr_ethernet2); + device_remove_file(&pdev->dev, &dev_attr_ethernet3); + device_remove_file(&pdev->dev, &dev_attr_ethernet4); + device_remove_file(&pdev->dev, &dev_attr_ethernet5); + device_remove_file(&pdev->dev, &dev_attr_ethernet6); + device_remove_file(&pdev->dev, &dev_attr_ethernet5_sfp); + device_remove_file(&pdev->dev, &dev_attr_ethernet6_sfp); + device_remove_file(&pdev->dev, &dev_attr_ethernet5_mode); + device_remove_file(&pdev->dev, &dev_attr_ethernet6_mode); + sysfs_remove_link(kernel_kobj, "gw16083"); +} + +static int +mv88e6176_probe(struct phy_device *pdev) +{ + int port; + int ret = 0; + u32 id, reg; + struct mv88e1111_priv *priv; + + dev_dbg(&pdev->dev, "%s: addr=0x%02x bus=%s:%s gw16083_client=%p\n", + __func__, pdev->addr, pdev->bus->name, pdev->bus->id, + gw16083_client); + + /* In single-chip addressing mode the MV88E6176 shows up on 0x10-0x16 */ + if (pdev->addr != MV_BASE) + return 0; + + /* i2c driver needs to be loaded first */ + if (!gw16083_client) + return 0; + + /* gw16083 has MV88E1676 hanging off of i210 mdio bus */ + if (strcmp(pdev->bus->name, "igb_enet_mii_bus") != 0) + return 0; + + //dev_info(&pdev->dev, "Detected"); + dev_info(&gw16083_client->dev, "%s: MV88E6176 7-port switch detected", + pdev->bus->id); + + /* + * port5/6 config: MV88E1111 PHY + * Register 20: PHY Control Register + * R20_7: add delay to RX_CLK for RXD + * R20_1: add delay to TX_CLK for TXD + * Register 24: LED Control Register + * 0x4111: + * Pulse stretch 170 to 340 ms + * Register 0: Control Register + * R0_15: phy reset + */ + for (port = 5; port < 7; port++) { +#ifndef RGMII_DELAY_ON_PHY + write_switch_port(pdev, port, MV_PORT_PHYS_CONTROL, 0xC003); +#endif + + id = read_switch_port_phy(pdev, port, + MII_M1111_PHY_IDENT0) << 16; + id |= read_switch_port_phy(pdev, port, MII_M1111_PHY_IDENT1); + if ((id & MII_M1111_PHY_ID_MASK) != MII_M1111_PHY_ID) { + dev_err(&gw16083_client->dev, + "Port%d: No MV88E1111 PHY detected", port); + return 0; + //continue; + } + +#ifdef RGMII_DELAY_ON_PHY + /* phy rx/tx delay */ + reg = read_switch_port_phy(pdev, port, MII_M1111_PHY_EXT_CR); + reg |= (1<<1) | (1<<7); + write_switch_port_phy(pdev, port, MII_M1111_PHY_EXT_CR, reg); +#endif + /* led config */ + write_switch_port_phy(pdev, port, MII_M1111_PHY_LED_CONTROL, + MII_M1111_PHY_LED_PULSE_STR); + /* reset phy */ + reg = read_switch_port_phy(pdev, port, MII_M1111_PHY_CONTROL); + reg |= MII_M1111_PHY_CONTROL_RESET; + write_switch_port_phy(pdev, port, MII_M1111_PHY_CONTROL, reg); + dev_info(&gw16083_client->dev, + "Port%d MV88E111 PHY configured\n", port); + } + + /* + * GPIO Configuration: + * GPIO1: FIB5_TXEN# (output) + * GPIO2: FIB6_TXEN# (output) + * GPIO3: FIB6_PRES# (input) + * GPIO4: FIB6_LOS (input) + * GPIO5: FIB5_PRES# (input) + * GPIO6: FIB5_LOS (input) + */ + write_switch_scratch(pdev, MV_GPIO_DATA, 0x06); /* GPIO[2:1] out hi */ + write_switch_scratch(pdev, MV_GPIO_DIR, 0x78); /* GPIO[6:3] inp */ + + pdev->irq = PHY_POLL; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + memset(priv, 0, sizeof(*priv)); + priv->phydev = pdev; + priv->client = gw16083_client; + priv->port5.port = 5; + priv->port6.port = 6; + dev_set_drvdata(&pdev->dev, priv); + + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet1); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet2); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet3); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet4); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet5); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet6); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet5_sfp); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet6_sfp); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet5_mode); + ret |= device_create_file(&pdev->dev, &dev_attr_ethernet6_mode); + + if (unlikely(ret)) + dev_err(&pdev->dev, "Failed creating attrs\n"); + + /* Add a nice symlink to the real device */ + ret = sysfs_create_link(kernel_kobj, &pdev->dev.kobj, "gw16083"); + + dev_dbg(&pdev->dev, "initial state: GPIO=0x%02x " + "Port5_serdes=%d Port6_serdes=%d\n", + read_switch_scratch(pdev, MV_GPIO_DATA), + (read_switch_port_phy(pdev, 5, MII_M1111_PHY_EXT_SR) + & (1<<13) ? 1:0), + (read_switch_port_phy(pdev, 6, MII_M1111_PHY_EXT_SR) + & (1<<13) ? 1:0)); + + return ret; +} + +static struct phy_driver mv88e6176_phy_driver = { + .name = "MV88E6176", + .phy_id = MV_IDENT_VALUE, + .phy_id_mask = MV_IDENT_MASK, + .features = PHY_BASIC_FEATURES, + .probe = &mv88e6176_probe, + .remove = &mv88e6176_remove, + .config_init = &mv88e6176_config_init, + .config_aneg = &mv88e6176_config_aneg, + .read_status = &mv88e6176_read_status, + .driver = { .owner = THIS_MODULE }, +}; + +/* + * I2C driver + */ + +/* See SFF-8472 */ +struct sfp_msa { + /* Basic ID fields */ + u8 identifier; + u8 ext_identifier; + u8 connector; + u8 transceiver[8]; + u8 encoding; + u8 br_nominal; + u8 rate_identifier; + u8 length_smf_km; + u8 length_smf; + u8 length_om2; + u8 length_om1; + u8 length_om4; + u8 length_om3; + u8 vendor_name[16]; + u8 transceiver2; + u8 vendor_oui[3]; + u8 vendor_pn[16]; + u8 vendor_rev[4]; + u8 wavelength[2]; + u8 resv1; + u8 cc_base; + + /* extended id fields */ + u8 options[2]; + u8 br_max; + u8 br_min; + u8 vendor_sn[16]; + u8 date_code[8]; + u8 diags_type; + u8 enhanced_options; + u8 sff8472_compliance; + u8 cc_ext; + + /* Vendor specific ID fields */ + u8 vendor_data[32]; + u8 sff8079[128]; +}; + +enum identifier { + UNKNOWN, + GBIC, + SFF, + SFP, + XBI, + XENPACK, + XFP, + XFF, + XFP_E, + XPAK, + X2, + DWDM_SFP, + QSFP, + MAX_ID, +}; + +const char* id_names[] = { + "UNKONWN", + "GBIC", + "SFF", + "SFP", + NULL, +}; + +/* Flags for SFP modules compatible with ETH up to 1Gb */ +struct sfp_flags { + u8 e1000_base_sx:1; + u8 e1000_base_lx:1; + u8 e1000_base_cx:1; + u8 e1000_base_t:1; + u8 e100_base_lx:1; + u8 e100_base_fx:1; + u8 e10_base_bx10:1; + u8 e10_base_px:1; +}; + +#define STRING_APPEND(str, src) \ + strncat(str, src, sizeof(src)); \ + for (i = 1; i < sizeof(str); i++) \ + if (str[i-1] == ' ' && str[i] == ' ') \ + str[i] = 0; + +static int gw16083_read_port_sfp(struct i2c_client *client, + struct mv88e1111_port_state *state) +{ + int ret = 0; + u8 data[256]; + struct sfp_flags *eth_flags; + u8 crc; + int i; + u8 *str; + struct sfp_msa *sfp_msa = (struct sfp_msa *)data; + int port = state->port; + union i2c_smbus_data d; + + dev_dbg(&client->dev, "%s Port%d\n", __func__, port); + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) + return -ENODEV; + d.byte = (port == 5) ? 1 : 2; + if (i2c_smbus_xfer(client->adapter, GW16083_I2C_ADDR_PCA9543, + client->flags, I2C_SMBUS_WRITE, 0, + I2C_SMBUS_BYTE_DATA, &d) < 0) + { + dev_err(&client->dev, + "Port%d: failed writing PCA9543 register\n", port); + return ret; + } + + /* read all 256 bytes of SFP EEPROM */ + for (i = 0; i < sizeof(data); i += I2C_SMBUS_BLOCK_MAX) { + d.block[0] = I2C_SMBUS_BLOCK_MAX; + if (i2c_smbus_xfer(client->adapter, GW16083_I2C_ADDR_SFP1, + client->flags, I2C_SMBUS_READ, i, + I2C_SMBUS_I2C_BLOCK_DATA, &d) < 0) + { + dev_err(&client->dev, + "Port%d: failed reading SFP data\n", port); + return ret; + } + memcpy(data + i, d.block + 1, I2C_SMBUS_BLOCK_MAX); + } + + /* Validate checksums */ + for (crc = 0, i = 0; i < 63; i++) + crc += data[i]; + if (crc != sfp_msa->cc_base) { + dev_err(&client->dev, "Port%d: " + "Checksum failure for Base ID fields: 0x%02x\n", port, + crc); +#ifdef FAIL_ON_CHECKSUM_ERR + return -EINVAL; +#endif + } + for (crc = 0, i = 64; i < 95; i++) + crc += data[i]; + if (crc != sfp_msa->cc_ext) { + dev_err(&client->dev, "Port%d: " + "Checksum failure for Extended ID fields: 0x%02x\n", + port, crc); +#ifdef FAIL_ON_CHECKSUM_ERR + return -EINVAL; +#endif + } + state->sfp_id[0] = 0; + for (i = 0; id_names[i]; i++) { + if (sfp_msa->identifier == i) { + sprintf(state->sfp_id, "%s: ", id_names[i]); + break; + } + } + STRING_APPEND(state->sfp_id, sfp_msa->vendor_oui); + STRING_APPEND(state->sfp_id, sfp_msa->vendor_name); + STRING_APPEND(state->sfp_id, sfp_msa->vendor_pn); + STRING_APPEND(state->sfp_id, sfp_msa->vendor_rev); + STRING_APPEND(state->sfp_id, sfp_msa->vendor_sn); + dev_info(&client->dev, "Port%d: %s\n", port, state->sfp_id); + + if ((sfp_msa->identifier != GBIC) && + (sfp_msa->identifier != SFF) && + (sfp_msa->identifier != SFP)) + { + dev_err(&client->dev, "Port%d: Unknown module identifier: %d\n", + port, sfp_msa->identifier); + return -EINVAL; + } + + str = ""; + eth_flags = (struct sfp_flags *)(sfp_msa->transceiver + 3); + if (eth_flags->e1000_base_sx) { + str = "1000Base-SX (Fiber)"; + } else if (eth_flags->e1000_base_lx) { + str = "1000Base-LX (Fiber)"; + } else if (eth_flags->e1000_base_t) { + str = "1000Base-T (Copper)"; + } else if (eth_flags->e100_base_fx) { + str = "100Base-FX (Fiber) - not supported"; + ret = -EINVAL; + } else { + str = "Unknown/Unsupported media type"; + ret = -EINVAL; + } + if (ret) + dev_err(&client->dev, "Port%d: %s (0x%02x)\n", port, str, + sfp_msa->transceiver[3]); + else + dev_info(&client->dev, "Port%d: %s (0x%02x)\n", port, str, + sfp_msa->transceiver[3]); + + return ret; +} + +static int gw16083_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret; + + dev_info(&client->dev, "GW16083 Ethernet Expansion Mezzanine\n"); + if (gw16083_client) { + dev_err(&client->dev, "client already registered\n"); + return -EINVAL; + } + gw16083_client = client; + + ret = phy_driver_register(&mv88e6176_phy_driver); + if (ret) + dev_err(&client->dev, + "failed to register mv88e6176 phy driver: %d\n", ret); + return ret; +} + +static int gw16083_remove(struct i2c_client *client) +{ + dev_dbg(&client->dev, "%s\n", __func__); + + phy_driver_unregister(&mv88e6176_phy_driver); + gw16083_client = NULL; + return 0; +} + +static const struct of_device_id gw16083_dt_ids[] = { + { .compatible = "gateworks,gw16083", }, + { } +}; + +MODULE_DEVICE_TABLE(of, gw16083_dt_ids); + +static const struct i2c_device_id gw16083_id[] = { + { "gw16083", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, gw16083_id); + +static struct i2c_driver gw16083_driver = { + .driver = { + .name = "gw16083", + .of_match_table = gw16083_dt_ids, + }, + .probe = gw16083_probe, + .remove = gw16083_remove, + .id_table = gw16083_id, +}; + +static int __init mv88e6176_init(void) +{ + return i2c_add_driver(&gw16083_driver); +} + +static void __exit mv88e6176_exit(void) +{ + i2c_del_driver(&gw16083_driver); +} + +module_init(mv88e6176_init); +module_exit(mv88e6176_exit); diff --git a/target/linux/imx6/files-4.1/drivers/net/phy/gw16083.h b/target/linux/imx6/files-4.1/drivers/net/phy/gw16083.h new file mode 100644 index 0000000..db96f2b --- /dev/null +++ b/target/linux/imx6/files-4.1/drivers/net/phy/gw16083.h @@ -0,0 +1,123 @@ +/* + * drivers/net/phy/mv88e6176.h + * + * Driver for Marvell Switch + * + * Author: Tim Harvey + * + * Copyright (c) 2014 Tim Harvey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _GW16083_H_ +#define _GW16083_H_ + +#define MII_MARVELL_PHY_PAGE 22 + +/* + * I2C Addresses + */ +#define GW16083_I2C_ADDR_SFP1 0x50 +#define GW16083_I2C_ADDR_SFP2 0x51 +#define GW16083_I2C_ADDR_EEPROM 0x52 +#define GW16083_I2C_ADDR_PCA9543 0x70 + +/* + * MV88E1111 PHY Registers + */ +enum { + MII_M1111_PHY_CONTROL = 0, + MII_M1111_PHY_STATUS = 1, + MII_M1111_PHY_IDENT0 = 2, + MII_M1111_PHY_IDENT1 = 3, + MII_M1111_PHY_EXT_CR = 20, + MII_M1111_PHY_LED_CONTROL = 24, + MII_M1111_PHY_EXT_SR = 27, +}; + +#define MII_M1111_PHY_ID_MASK 0xfffffff0 +#define MII_M1111_PHY_ID 0x01410cc0 + +#define MII_M1111_PHY_CONTROL_RESET (1 << 15) +#define MII_M1111_PHY_LED_DIRECT 0x4100 +#define MII_M1111_PHY_LED_PULSE_STR 0x4111 +#define MII_M1111_PHY_LED_COMBINE 0x411c +#define MII_M1111_RX_DELAY 0x80 +#define MII_M1111_TX_DELAY 0x2 + +/* + * MV88E6176 Switch Registers + */ + +/* PHY Addrs */ +#define MV_BASE 0x10 +#define MV_GLOBAL1 0x1b +#define MV_GLOBAL2 0x1c +#define MV_GLOBAL3 0x1d + +/* Global2 Registers */ +enum { + MV_SMI_PHY_COMMAND = 0x18, + MV_SMI_PHY_DATA = 0x19, + MV_SCRATCH_MISC = 0x1A, +}; + +/* Scratch And Misc Reg offsets */ +enum { + MV_GPIO_MODE = 0x60, + MV_GPIO_DIR = 0x62, + MV_GPIO_DATA = 0x64, + MV_GPIO76_CNTL = 0x6B, + MV_GPIO54_CNTL = 0x6A, + MV_GPIO32_CNTL = 0x69, + MV_GPIO10_CNTL = 0x68, + MV_CONFIG0 = 0x70, + MV_CONFIG1 = 0x71, + MV_CONFIG2 = 0x72, + MV_CONFIG3 = 0x73, +}; + +/* PHY Registers */ +enum { + MV_PHY_CONTROL = 0x00, + MV_PHY_STATUS = 0x01, + MV_PHY_IDENT0 = 0x02, + MV_PHY_IDENT1 = 0x03, + MV_PHY_ANEG = 0x04, + MV_PHY_LINK_ABILITY = 0x05, + MV_PHY_ANEG_EXPAND = 0x06, + MV_PHY_XMIT_NEXTP = 0x07, + MV_PHY_LINK_NEXTP = 0x08, + MV_PHY_CONTROL1 = 0x10, + MV_PHY_STATUS1 = 0x11, + MV_PHY_INTR_EN = 0x12, +}; + +/* Port Registers */ +enum { + MV_PORT_STATUS = 0x00, + MV_PORT_PHYS_CONTROL = 0x01, + MV_PORT_IDENT = 0x03, + MV_PORT_CONTROL = 0x04, + MV_PORT_VLANMAP = 0x06, + MV_PORT_ASSOC = 0x0b, + MV_PORT_RXCOUNT = 0x10, + MV_PORT_TXCOUNT = 0x11, +}; + +#define SMIBUSY (1<<15) +#define SMIMODE22 (1<<12) +#define SMIOP_READ (2<<10) +#define SMIOP_WRITE (1<<10) +#define DEVADDR 5 +#define REGADDR 0 + +#define MV_IDENT_MASK 0x0000fff0 +#define MV_IDENT_VALUE 0x00001760 + +#endif /* _GW16083_H_ */ diff --git a/target/linux/imx6/image/Makefile b/target/linux/imx6/image/Makefile new file mode 100644 index 0000000..9b9f948 --- /dev/null +++ b/target/linux/imx6/image/Makefile @@ -0,0 +1,132 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Image/BuildKernel/Template + + ifneq ($(1),) + $(CP) $(DTS_DIR)/$(1).dtb $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb + + $(call Image/BuildKernel/MkFIT,$(1),$(KDIR)/zImage,$(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb,none,0x10008000,0x10008000) + $(CP) $(KDIR)/fit-$(1).itb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage.itb + + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/BuildKernel/MkFIT,$(1),$(KDIR)/zImage-initramfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb,none,0x10008000,0x10008000,-initramfs) + $(CP) $(KDIR)/fit-$(1)-initramfs.itb $(BIN_DIR)/$(IMG_PREFIX)-$(1)-fit-uImage-initramfs.itb + endif + endif + + $(CP) $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage + $(call Image/BuildKernel/MkuImage, \ + none, 0x10008000, 0x10008000, \ + $(BIN_DIR)/$(IMG_PREFIX)-zImage, \ + $(BIN_DIR)/$(IMG_PREFIX)-uImage \ + ) + + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs + $(call Image/BuildKernel/MkuImage, \ + none, 0x10008000, 0x10008000, \ + $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs, \ + $(BIN_DIR)/$(IMG_PREFIX)-uImage-initramfs \ + ) + endif +endef + +define Image/InstallKernel/Template + + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_KERNEL)$(CONFIG_TARGET_imx6_VENTANA),) + $(INSTALL_DIR) $(TARGET_DIR)/boot + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_UIMAGE)$(CONFIG_TARGET_imx6_VENTANA),) + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-uImage $(TARGET_DIR)/boot/ + ln -sf $(IMG_PREFIX)-uImage $(TARGET_DIR)/boot/uImage + endif + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_ZIMAGE),) + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/ + ln -sf $(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/zImage + endif + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_FIT),) + $(foreach dts,$(shell echo $(1)), \ + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(dts)-fit-uImage.itb $(TARGET_DIR)/boot/ + ) + endif + endif + + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB)$(CONFIG_TARGET_imx6_VENTANA),) + $(INSTALL_DIR) $(TARGET_DIR)/boot + $(foreach dts,$(shell echo $(1)), \ + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(dts).dtb $(TARGET_DIR)/boot/ ; \ + ln -sf $(IMG_PREFIX)-$(dts).dtb $(TARGET_DIR)/boot/$(dts).dtb ; \ + ) + endif +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).bin bs=128k conv=sync + [ -f "$(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-fit-uImage.itb" ] && ( \ + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-fit-uImage.itb bs=2048k conv=sync; \ + dd if=$(KDIR)/root.$(1) bs=128k conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-fit-$(1).bin || true +endef + +define ubifs_imx_gateworks_ventana + # Micron MT29F1G08ABAD/MT29F2G08ABAE/MT29F4G08ABAD/MT29F8G08ADAD NAND + $(eval VENTANA_UBIFS_OPTS:="-m 2048 -e 124KiB -c 8124") + $(eval VENTANA_UBI_OPTS:="-m 2048 -p 128KiB -s 2048") + $(call Image/mkfs/ubifs) + $(CP) $(KDIR)/root.ubifs $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-rootfs_normal.ubifs + $(CP) $(KDIR)/root.ubi $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-rootfs_normal.ubi + + # Micron MT29F8G08ABAC/MT29F16G08ADAC 1GB/2GB NAND + $(eval VENTANA_UBIFS_OPTS:="-m 4096 -e 248KiB -c 8124") + $(eval VENTANA_UBI_OPTS:="-m 4096 -p 256KiB -s 4096") + $(call Image/mkfs/ubifs) + $(CP) $(KDIR)/root.ubifs $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-rootfs_large.ubifs + $(CP) $(KDIR)/root.ubi $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-rootfs_large.ubi +endef + +define Image/Build/ubifs + true +endef + +define Image/Build/ubi + true +endef + + +Image/BuildKernel/Template/Generic=$(call Image/BuildKernel/Template) +Image/InstallKernel/Template/Generic=$(call Image/InstallKernel/Template) + +Image/BuildKernel/Template/IMX6DL_WANDBOARD=$(call Image/BuildKernel/Template,imx6dl-wandboard) +Image/InstallKernel/Template/IMX6DL_WANDBOARD=$(call Image/InstallKernel/Template,imx6dl-wandboard) + +Image/BuildKernel/Template/VENTANA=$(foreach dts,$(shell echo $(VENTANA_DTS)),$(call Image/BuildKernel/Template,$(dts))) +Image/InstallKernel/Template/VENTANA=$(call Image/InstallKernel/Template,$(VENTANA_DTS)) +Image/ubifs/VENTANA=$(call ubifs_imx_gateworks_ventana) + + +define Image/BuildKernel + $(call Image/BuildKernel/Template/$(PROFILE)) +endef + +define Image/InstallKernel + $(call Image/InstallKernel/Template/$(PROFILE)) + $(if $(Image/ubifs/$(PROFILE)), \ + $(call Image/ubifs/$(PROFILE)) + ) +endef + +define Image/Build + $(if $(Image/Build/$(1)), \ + $(call Image/Build/$(1),$(1)), \ + $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-$(1).img \ + ) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/imx6/image/ubinize.cfg b/target/linux/imx6/image/ubinize.cfg new file mode 100644 index 0000000..e4149ec --- /dev/null +++ b/target/linux/imx6/image/ubinize.cfg @@ -0,0 +1,13 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.ubifs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs +# Autoresize volume at first mount +vol_flags=autoresize diff --git a/target/linux/imx6/patches-3.18/100-bootargs.patch b/target/linux/imx6/patches-3.18/100-bootargs.patch new file mode 100644 index 0000000..0954391 --- /dev/null +++ b/target/linux/imx6/patches-3.18/100-bootargs.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/imx6dl-wandboard.dts ++++ b/arch/arm/boot/dts/imx6dl-wandboard.dts +@@ -19,4 +19,8 @@ + memory { + reg = <0x10000000 0x40000000>; + }; ++ ++ chosen { ++ bootargs = "console=ttymxc0,115200"; ++ }; + }; diff --git a/target/linux/imx6/patches-3.18/200-pci_designware_add-ability-for-custom-swizzle.patch b/target/linux/imx6/patches-3.18/200-pci_designware_add-ability-for-custom-swizzle.patch new file mode 100644 index 0000000..75218d2 --- /dev/null +++ b/target/linux/imx6/patches-3.18/200-pci_designware_add-ability-for-custom-swizzle.patch @@ -0,0 +1,33 @@ +commit e84634dc6c7f3f6af9b8ef1fb36f0d85c476ab95 +Author: Tim Harvey +Date: Thu Feb 27 01:02:23 2014 -0800 + + PCI: designware: add ability for custom swizzle + + Add the ability for a platform driver to provide a platform-specific + swizzle function. + + Signed-off-by: Tim Harvey + +--- a/drivers/pci/host/pcie-designware.c ++++ b/drivers/pci/host/pcie-designware.c +@@ -492,6 +492,9 @@ int dw_pcie_host_init(struct pcie_port * + if (pp->ops->host_init) + pp->ops->host_init(pp); + ++ if (pp->swizzle) ++ dw_pci.swizzle = pp->swizzle; ++ + dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); + + /* program correct class for RC */ +--- a/drivers/pci/host/pcie-designware.h ++++ b/drivers/pci/host/pcie-designware.h +@@ -53,6 +53,7 @@ struct pcie_port { + struct irq_domain *irq_domain; + unsigned long msi_data; + DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); ++ u8 (*swizzle)(struct pci_dev *, u8 *); + }; + + struct pcie_host_ops { diff --git a/target/linux/imx6/patches-3.18/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch b/target/linux/imx6/patches-3.18/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch new file mode 100644 index 0000000..4db1569 --- /dev/null +++ b/target/linux/imx6/patches-3.18/201-pci_imx6_ventana_fixup-for-IRQ-mismapping.patch @@ -0,0 +1,81 @@ +commit 2c0d0491438433a1f327f2e754c7b6b55fec51c4 +Author: Tim Harvey +Date: Thu Feb 27 00:59:53 2014 -0800 + + PCI: imx6: ventana: fixup for IRQ mismapping + + The TI XIO2001 PCIe-to-PCI bridge used on several Ventana expansion boards + has its slot-to-bridge IRQ mapping reversed from the PCI specification: + + INTA->INTD + INTB->INTC + INTC->INTB + INTD->INTA + + Implement a custom swizzle function that does a fixup on the interrupt for + devices on a TI XIO2001 bridge. + + Signed-off-by: Tim Harvey + +--- a/drivers/pci/host/pci-imx6.c ++++ b/drivers/pci/host/pci-imx6.c +@@ -553,6 +553,39 @@ static int __init imx6_add_pcie_port(str + return 0; + } + ++/* TI XIO2001 PCIe-to-PCI bridge on GW16082 exp card has IRQs reversed */ ++u8 ventana_swizzle(struct pci_dev *dev, u8 *pin) ++{ ++ u8 i = 0; ++ struct pci_dev *pdev = dev; ++ ++ /* count number of TI XIO2001 bridges on bus */ ++ while (!pci_is_root_bus(pdev->bus)) { ++ if (pdev->bus && pdev->bus->self && ++ (pdev->bus->self->vendor == PCI_VENDOR_ID_TI) && ++ (pdev->bus->self->device == PCI_DEVICE_ID_TI_XIO2001)) { ++ i++; ++ } ++ pdev = pdev->bus->self; ++ } ++ while (!pci_is_root_bus(dev->bus)) { ++ /* if we are directly downstream from 1st TI XIO2001 bridge */ ++ if (dev->bus && dev->bus->self && ++ (dev->bus->self->vendor == PCI_VENDOR_ID_TI) && ++ (dev->bus->self->device == PCI_DEVICE_ID_TI_XIO2001)) { ++ if (--i == 0) { ++ /* swap IRQs and swizzle backwards */ ++ *pin = (15 - PCI_SLOT(dev->devfn)) + 1; ++ dev = dev->bus->self; ++ continue; ++ } ++ } ++ *pin = pci_swizzle_interrupt_pin(dev, *pin); ++ dev = dev->bus->self; ++ } ++ return PCI_SLOT(dev->devfn); ++} ++ + static int __init imx6_pcie_probe(struct platform_device *pdev) + { + struct imx6_pcie *imx6_pcie; +@@ -618,6 +651,9 @@ static int __init imx6_pcie_probe(struct + return PTR_ERR(imx6_pcie->iomuxc_gpr); + } + ++ if (of_machine_is_compatible("gw,ventana")) ++ pp->swizzle = ventana_swizzle; ++ + ret = imx6_add_pcie_port(pp, pdev); + if (ret < 0) + return ret; +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -827,6 +827,7 @@ + #define PCI_DEVICE_ID_TI_XX12 0x8039 + #define PCI_DEVICE_ID_TI_XX12_FM 0x803b + #define PCI_DEVICE_ID_TI_XIO2000A 0x8231 ++#define PCI_DEVICE_ID_TI_XIO2001 0x8240 + #define PCI_DEVICE_ID_TI_1130 0xac12 + #define PCI_DEVICE_ID_TI_1031 0xac13 + #define PCI_DEVICE_ID_TI_1131 0xac15 diff --git a/target/linux/imx6/patches-3.18/202-net-igb-add-i210-i211-support-for-phy-read-write.patch b/target/linux/imx6/patches-3.18/202-net-igb-add-i210-i211-support-for-phy-read-write.patch new file mode 100644 index 0000000..fb4b722 --- /dev/null +++ b/target/linux/imx6/patches-3.18/202-net-igb-add-i210-i211-support-for-phy-read-write.patch @@ -0,0 +1,129 @@ +Author: Tim Harvey +Date: Thu May 15 00:12:26 2014 -0700 + + net: igb: add i210/i211 support for phy read/write + + The i210/i211 uses the MDICNFG register for the phy address instead of the + MDIC register. + + Signed-off-by: Tim Harvey + +--- a/drivers/net/ethernet/intel/igb/e1000_phy.c ++++ b/drivers/net/ethernet/intel/igb/e1000_phy.c +@@ -135,7 +135,7 @@ out: + s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) + { + struct e1000_phy_info *phy = &hw->phy; +- u32 i, mdic = 0; ++ u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + + if (offset > MAX_PHY_REG_ADDRESS) { +@@ -148,11 +148,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ +- mdic = ((offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | +- (E1000_MDIC_OP_READ)); ++ switch (hw->mac.type) { ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ break; ++ default: ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ break; ++ } + + wr32(E1000_MDIC, mdic); ++ wrfl(); + + /* Poll the ready bit to see if the MDI read completed + * Increasing the time out as testing showed failures with +@@ -177,6 +191,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h + *data = (u16) mdic; + + out: ++ switch (hw->mac.type) { ++ /* restore MDICNFG to have phy's addr */ ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ break; ++ default: ++ break; ++ } + return ret_val; + } + +@@ -191,7 +217,7 @@ out: + s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) + { + struct e1000_phy_info *phy = &hw->phy; +- u32 i, mdic = 0; ++ u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + + if (offset > MAX_PHY_REG_ADDRESS) { +@@ -204,12 +230,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ +- mdic = (((u32)data) | +- (offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | +- (E1000_MDIC_OP_WRITE)); ++ switch (hw->mac.type) { ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ break; ++ default: ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ break; ++ } + + wr32(E1000_MDIC, mdic); ++ wrfl(); + + /* Poll the ready bit to see if the MDI read completed + * Increasing the time out as testing showed failures with +@@ -233,6 +274,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + } + + out: ++ switch (hw->mac.type) { ++ /* restore MDICNFG to have phy's addr */ ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ break; ++ default: ++ break; ++ } + return ret_val; + } + diff --git a/target/linux/imx6/patches-3.18/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch b/target/linux/imx6/patches-3.18/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch new file mode 100644 index 0000000..7869b1c --- /dev/null +++ b/target/linux/imx6/patches-3.18/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch @@ -0,0 +1,260 @@ +From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001 +From: Tim Harvey +Date: Thu, 15 May 2014 00:29:18 -0700 +Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr + +Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address. +The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers +to this function. + +Signed-off-by: Tim Harvey +--- + drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +- + drivers/net/ethernet/intel/igb/e1000_phy.c | 74 +++++++++++++++++++--------- + drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++- + 3 files changed, 58 insertions(+), 26 deletions(-) + +--- a/drivers/net/ethernet/intel/igb/e1000_82575.c ++++ b/drivers/net/ethernet/intel/igb/e1000_82575.c +@@ -2129,7 +2129,7 @@ static s32 igb_read_phy_reg_82580(struct + if (ret_val) + goto out; + +- ret_val = igb_read_phy_reg_mdic(hw, offset, data); ++ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data); + + hw->phy.ops.release(hw); + +@@ -2154,7 +2154,7 @@ static s32 igb_write_phy_reg_82580(struc + if (ret_val) + goto out; + +- ret_val = igb_write_phy_reg_mdic(hw, offset, data); ++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data); + + hw->phy.ops.release(hw); + +--- a/drivers/net/ethernet/intel/igb/e1000_phy.c ++++ b/drivers/net/ethernet/intel/igb/e1000_phy.c +@@ -132,9 +132,8 @@ out: + * Reads the MDI control regsiter in the PHY at offset and stores the + * information read to data. + **/ +-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) + { +- struct e1000_phy_info *phy = &hw->phy; + u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + +@@ -153,14 +152,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h + case e1000_i211: + mdicnfg = rd32(E1000_MDICNFG); + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); +- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); + wr32(E1000_MDICNFG, mdicnfg); + mdic = ((offset << E1000_MDIC_REG_SHIFT) | + (E1000_MDIC_OP_READ)); + break; + default: + mdic = ((offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_READ)); + break; + } +@@ -214,9 +213,8 @@ out: + * + * Writes data to MDI control register in the PHY at offset. + **/ +-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) ++s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) + { +- struct e1000_phy_info *phy = &hw->phy; + u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + +@@ -235,7 +233,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + case e1000_i211: + mdicnfg = rd32(E1000_MDICNFG); + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); +- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); + wr32(E1000_MDICNFG, mdicnfg); + mdic = (((u32)data) | + (offset << E1000_MDIC_REG_SHIFT) | +@@ -244,7 +242,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + default: + mdic = (((u32)data) | + (offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_WRITE)); + break; + } +@@ -464,7 +462,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw + goto out; + + if (offset > MAX_PHY_MULTI_PAGE_REG) { +- ret_val = igb_write_phy_reg_mdic(hw, ++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, + IGP01E1000_PHY_PAGE_SELECT, + (u16)offset); + if (ret_val) { +@@ -473,8 +471,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw + } + } + +- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, +- data); ++ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, ++ MAX_PHY_REG_ADDRESS & offset, data); + + hw->phy.ops.release(hw); + +@@ -503,7 +501,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h + goto out; + + if (offset > MAX_PHY_MULTI_PAGE_REG) { +- ret_val = igb_write_phy_reg_mdic(hw, ++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, + IGP01E1000_PHY_PAGE_SELECT, + (u16)offset); + if (ret_val) { +@@ -512,8 +510,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h + } + } + +- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, +- data); ++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, ++ MAX_PHY_REG_ADDRESS & offset, data); + + hw->phy.ops.release(hw); + +@@ -2464,8 +2462,9 @@ out: + } + + /** +- * igb_write_phy_reg_gs40g - Write GS40G PHY register ++ * igb_write_reg_gs40g - Write GS40G PHY register + * @hw: pointer to the HW structure ++ * @addr: phy address to write to + * @offset: lower half is register offset to write to + * upper half is page to use. + * @data: data to write at register offset +@@ -2473,7 +2472,7 @@ out: + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) ++s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) + { + s32 ret_val; + u16 page = offset >> GS40G_PAGE_SHIFT; +@@ -2483,10 +2482,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000 + if (ret_val) + return ret_val; + +- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); ++ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); + if (ret_val) + goto release; +- ret_val = igb_write_phy_reg_mdic(hw, offset, data); ++ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data); + + release: + hw->phy.ops.release(hw); +@@ -2494,8 +2493,24 @@ release: + } + + /** +- * igb_read_phy_reg_gs40g - Read GS40G PHY register ++ * igb_write_phy_reg_gs40g - Write GS40G PHY register ++ * @hw: pointer to the HW structure ++ * @offset: lower half is register offset to write to ++ * upper half is page to use. ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data); ++} ++ ++/** ++ * igb_read_reg_gs40g - Read GS40G PHY register + * @hw: pointer to the HW structure ++ * @addr: phy address to read from + * @offset: lower half is register offset to read to + * upper half is page to use. + * @data: data to read at register offset +@@ -2503,7 +2518,7 @@ release: + * Acquires semaphore, if necessary, then reads the data in the PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) + { + s32 ret_val; + u16 page = offset >> GS40G_PAGE_SHIFT; +@@ -2513,10 +2528,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_ + if (ret_val) + return ret_val; + +- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); ++ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); + if (ret_val) + goto release; +- ret_val = igb_read_phy_reg_mdic(hw, offset, data); ++ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data); + + release: + hw->phy.ops.release(hw); +@@ -2524,6 +2539,21 @@ release: + } + + /** ++ * igb_read_phy_reg_gs40g - Read GS40G PHY register ++ * @hw: pointer to the HW structure ++ * @offset: lower half is register offset to read to ++ * upper half is page to use. ++ * @data: data to read at register offset ++ * ++ * Acquires semaphore, if necessary, then reads the data in the PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data); ++} ++ ++/** + * igb_set_master_slave_mode - Setup PHY for Master/slave mode + * @hw: pointer to the HW structure + * +--- a/drivers/net/ethernet/intel/igb/e1000_phy.h ++++ b/drivers/net/ethernet/intel/igb/e1000_phy.h +@@ -61,8 +61,8 @@ s32 igb_phy_has_link(struct e1000_hw *h + void igb_power_up_phy_copper(struct e1000_hw *hw); + void igb_power_down_phy_copper(struct e1000_hw *hw); + s32 igb_phy_init_script_igp3(struct e1000_hw *hw); +-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); +-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); ++s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); ++s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); + s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); + s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); + s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); +@@ -72,6 +72,8 @@ s32 igb_phy_force_speed_duplex_82580(st + s32 igb_get_cable_length_82580(struct e1000_hw *hw); + s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); + s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); ++s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); ++s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); + s32 igb_check_polarity_m88(struct e1000_hw *hw); + + /* IGP01E1000 Specific Registers */ diff --git a/target/linux/imx6/patches-3.18/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch b/target/linux/imx6/patches-3.18/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch new file mode 100644 index 0000000..129a0bc --- /dev/null +++ b/target/linux/imx6/patches-3.18/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch @@ -0,0 +1,308 @@ +From 03855caf93f7332a3f320228ba1a0e7baae8a749 Mon Sep 17 00:00:00 2001 +From: Tim Harvey +Date: Thu, 15 May 2014 12:36:23 -0700 +Subject: [PATCH] net: igb: register mii_bus for SerDes w/ external phy + +If an i210 is configured for 1000BASE-BX link_mode and has an external phy +specified, then register an mii bus using the external phy address as +a mask. + +An i210 hooked to an external standard phy will be configured with a link_mo +of SGMII in which case phy ops will be configured and used internall in the +igb driver for link status. However, in certain cases one might be using a +backplane SerDes connection to something that talks on the mdio bus but is +not a standard phy, such as a switch. In this case by registering an mdio +bus a phy driver can manage the device. + +Signed-off-by: Tim Harvey +--- + drivers/net/ethernet/intel/igb/e1000_82575.c | 15 +++ + drivers/net/ethernet/intel/igb/e1000_hw.h | 7 ++ + drivers/net/ethernet/intel/igb/igb_main.c | 168 ++++++++++++++++++++++++++- + 3 files changed, 185 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/intel/igb/e1000_82575.c ++++ b/drivers/net/ethernet/intel/igb/e1000_82575.c +@@ -598,13 +598,25 @@ static s32 igb_get_invariants_82575(stru + switch (link_mode) { + case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: + hw->phy.media_type = e1000_media_type_internal_serdes; ++ if (igb_sgmii_uses_mdio_82575(hw)) { ++ u32 mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= E1000_MDICNFG_PHY_MASK; ++ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT; ++ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n", ++ hw->phy.addr); ++ } else { ++ hw_dbg("1000BASE_KX"); ++ } + break; + case E1000_CTRL_EXT_LINK_MODE_SGMII: + /* Get phy control interface type set (MDIO vs. I2C)*/ + if (igb_sgmii_uses_mdio_82575(hw)) { + hw->phy.media_type = e1000_media_type_copper; + dev_spec->sgmii_active = true; ++ hw_dbg("SGMII with external MDIO PHY"); + break; ++ } else { ++ hw_dbg("SGMII with external I2C PHY"); + } + /* fall through for I2C based SGMII */ + case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: +@@ -621,8 +633,11 @@ static s32 igb_get_invariants_82575(stru + hw->phy.media_type = e1000_media_type_copper; + dev_spec->sgmii_active = true; + } ++ hw_dbg("SERDES with external SFP"); + + break; ++ } else { ++ hw_dbg("SERDES"); + } + + /* do not change link mode for 100BaseFX */ +--- a/drivers/net/ethernet/intel/igb/e1000_hw.h ++++ b/drivers/net/ethernet/intel/igb/e1000_hw.h +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include "e1000_regs.h" + #include "e1000_defines.h" +@@ -543,6 +544,12 @@ struct e1000_hw { + struct e1000_mbx_info mbx; + struct e1000_host_mng_dhcp_cookie mng_cookie; + ++#ifdef CONFIG_PHYLIB ++ /* Phylib and MDIO interface */ ++ struct mii_bus *mii_bus; ++ struct phy_device *phy_dev; ++ phy_interface_t phy_interface; ++#endif + union { + struct e1000_dev_spec_82575 _82575; + } dev_spec; +--- a/drivers/net/ethernet/intel/igb/igb_main.c ++++ b/drivers/net/ethernet/intel/igb/igb_main.c +@@ -41,6 +41,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -2237,6 +2238,126 @@ static s32 igb_init_i2c(struct igb_adapt + return status; + } + ++ ++#ifdef CONFIG_PHYLIB ++/* ++ * MMIO/PHYdev support ++ */ ++ ++static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) ++{ ++ struct e1000_hw *hw = bus->priv; ++ u16 out; ++ int err; ++ ++ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out); ++ if (err) ++ return err; ++ return out; ++} ++ ++static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, ++ u16 val) ++{ ++ struct e1000_hw *hw = bus->priv; ++ ++ return igb_write_reg_gs40g(hw, mii_id, regnum, val); ++} ++ ++static int igb_enet_mdio_reset(struct mii_bus *bus) ++{ ++ udelay(300); ++ return 0; ++} ++ ++static void igb_enet_mii_link(struct net_device *netdev) ++{ ++} ++ ++/* Probe the mdio bus for phys and connect them */ ++static int igb_enet_mii_probe(struct net_device *netdev) ++{ ++ struct igb_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ struct phy_device *phy_dev = NULL; ++ int phy_id; ++ ++ /* check for attached phy */ ++ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { ++ if (hw->mii_bus->phy_map[phy_id]) { ++ phy_dev = hw->mii_bus->phy_map[phy_id]; ++ break; ++ } ++ } ++ if (!phy_dev) { ++ netdev_err(netdev, "no PHY found\n"); ++ return -ENODEV; ++ } ++ ++ hw->phy_interface = PHY_INTERFACE_MODE_RGMII; ++ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev), ++ igb_enet_mii_link, hw->phy_interface); ++ if (IS_ERR(phy_dev)) { ++ netdev_err(netdev, "could not attach to PHY\n"); ++ return PTR_ERR(phy_dev); ++ } ++ ++ hw->phy_dev = phy_dev; ++ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n", ++ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev)); ++ ++ return 0; ++} ++ ++/* Create and register mdio bus */ ++static int igb_enet_mii_init(struct pci_dev *pdev) ++{ ++ struct mii_bus *mii_bus; ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct igb_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ int err; ++ ++ mii_bus = mdiobus_alloc(); ++ if (mii_bus == NULL) { ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ mii_bus->name = "igb_enet_mii_bus"; ++ mii_bus->read = igb_enet_mdio_read; ++ mii_bus->write = igb_enet_mdio_write; ++ mii_bus->reset = igb_enet_mdio_reset; ++ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", ++ pci_name(pdev), hw->device_id + 1); ++ mii_bus->priv = hw; ++ mii_bus->parent = &pdev->dev; ++ mii_bus->phy_mask = ~(1 << hw->phy.addr); ++ ++ err = mdiobus_register(mii_bus); ++ if (err) { ++ printk(KERN_ERR "failed to register mii_bus: %d\n", err); ++ goto err_out_free_mdiobus; ++ } ++ hw->mii_bus = mii_bus; ++ ++ return 0; ++ ++err_out_free_mdiobus: ++ mdiobus_free(mii_bus); ++err_out: ++ return err; ++} ++ ++static void igb_enet_mii_remove(struct e1000_hw *hw) ++{ ++ if (hw->mii_bus) { ++ mdiobus_unregister(hw->mii_bus); ++ mdiobus_free(hw->mii_bus); ++ } ++} ++#endif /* CONFIG_PHYLIB */ ++ + /** + * igb_probe - Device Initialization Routine + * @pdev: PCI device information struct +@@ -2659,6 +2780,13 @@ static int igb_probe(struct pci_dev *pde + } + } + pm_runtime_put_noidle(&pdev->dev); ++ ++#ifdef CONFIG_PHYLIB ++ /* create and register the mdio bus if using ext phy */ ++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) ++ igb_enet_mii_init(pdev); ++#endif ++ + return 0; + + err_register: +@@ -2802,6 +2930,10 @@ static void igb_remove(struct pci_dev *p + struct e1000_hw *hw = &adapter->hw; + + pm_runtime_get_noresume(&pdev->dev); ++#ifdef CONFIG_PHYLIB ++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) ++ igb_enet_mii_remove(hw); ++#endif + #ifdef CONFIG_IGB_HWMON + igb_sysfs_exit(adapter); + #endif +@@ -3115,6 +3247,12 @@ static int __igb_open(struct net_device + if (!resuming) + pm_runtime_put(&pdev->dev); + ++#ifdef CONFIG_PHYLIB ++ /* Probe and connect to PHY if using ext phy */ ++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) ++ igb_enet_mii_probe(netdev); ++#endif ++ + /* start the watchdog. */ + hw->mac.get_link_status = 1; + schedule_work(&adapter->watchdog_task); +@@ -7111,21 +7249,41 @@ void igb_alloc_rx_buffers(struct igb_rin + static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) + { + struct igb_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; + struct mii_ioctl_data *data = if_mii(ifr); + +- if (adapter->hw.phy.media_type != e1000_media_type_copper) ++ if (adapter->hw.phy.media_type != e1000_media_type_copper && ++ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)) + return -EOPNOTSUPP; + + switch (cmd) { + case SIOCGMIIPHY: +- data->phy_id = adapter->hw.phy.addr; ++ data->phy_id = hw->phy.addr; + break; + case SIOCGMIIREG: +- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, +- &data->val_out)) +- return -EIO; ++ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { ++ if (igb_read_reg_gs40g(&adapter->hw, data->phy_id, ++ data->reg_num & 0x1F, ++ &data->val_out)) ++ return -EIO; ++ } else { ++ if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, ++ &data->val_out)) ++ return -EIO; ++ } + break; + case SIOCSMIIREG: ++ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { ++ if (igb_write_reg_gs40g(hw, data->phy_id, ++ data->reg_num & 0x1F, ++ data->val_in)) ++ return -EIO; ++ } else { ++ if (igb_write_phy_reg(hw, data->reg_num & 0x1F, ++ data->val_in)) ++ return -EIO; ++ } ++ break; + default: + return -EOPNOTSUPP; + } diff --git a/target/linux/imx6/patches-3.18/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch b/target/linux/imx6/patches-3.18/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch new file mode 100644 index 0000000..e991fad --- /dev/null +++ b/target/linux/imx6/patches-3.18/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch @@ -0,0 +1,27 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -292,6 +292,14 @@ endif # RTL8366_SMI + + source "drivers/net/phy/b53/Kconfig" + ++config GATEWORKS_GW16083 ++ tristate "Gateworks GW16083 Ethernet Expansion Mezzanine" ++ ---help--- ++ The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a ++ Gateworks Ventana baseboard and provides a 7-port GbE managed ++ Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP ++ ports" ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_DP83640_PHY) += dp83640.o + obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_MICREL_PHY) += micrel.o ++obj-$(CONFIG_GATEWORKS_GW16083) += gw16083.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_AT803X_PHY) += at803x.o diff --git a/target/linux/imx6/patches-3.18/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch b/target/linux/imx6/patches-3.18/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch new file mode 100644 index 0000000..6f31f95 --- /dev/null +++ b/target/linux/imx6/patches-3.18/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch @@ -0,0 +1,56 @@ +--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +@@ -89,6 +89,11 @@ + enable-active-high; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &fec { +--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +@@ -266,6 +266,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &pcie { +--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +@@ -267,6 +267,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &pcie { +--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +@@ -308,6 +308,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &i2c3 { diff --git a/target/linux/imx6/patches-3.18/207-ARM-dts-imx6-ventana-Add-PCI-nodes-for-on-board-PCI-.patch b/target/linux/imx6/patches-3.18/207-ARM-dts-imx6-ventana-Add-PCI-nodes-for-on-board-PCI-.patch new file mode 100644 index 0000000..b581f78 --- /dev/null +++ b/target/linux/imx6/patches-3.18/207-ARM-dts-imx6-ventana-Add-PCI-nodes-for-on-board-PCI-.patch @@ -0,0 +1,110 @@ +From 840202d23892baaff74be11ec71c3ffc6ad6298e Mon Sep 17 00:00:00 2001 +From: Tim Harvey +Date: Tue, 20 Jan 2015 08:46:55 -0800 +Subject: [PATCH] ARM: dts: imx6 ventana: Add PCI nodes for on-board PCI + devices + +If the PCI nodes are defined, drivers can access information from the DT. +For example, the sky2 enet driver can obtain the mac address configured +from the bootloader (which is applied to the DT node with the ethernet1 alias). + +Signed-off-by: Tim Harvey +--- + arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 38 +++++++++++++++++++++++++++++++++-- + arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 38 +++++++++++++++++++++++++++++++++-- + 2 files changed, 72 insertions(+), 4 deletions(-) + +--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +@@ -280,8 +280,42 @@ + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; + +- eth1: sky2@8 { /* MAC/PHY on bus 8 */ +- compatible = "marvell,sky2"; ++ pcie@0,0 { ++ /* 00:00.0 0604: 16c3:abcd root host-bridge */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ reg = <0x0 0 0 0 0>; ++ ++ pcie@0,0 { ++ /* 01:00.0 0604: 10b5:8609 PEX switch bridge */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ reg = <0x0 0 0 0 0>; ++ ++ /* ++ * GigE PCI dev node needs to be defined so that enet ++ * driver can use it to obtain its boot-loader ++ * specified MAC ++ */ ++ pcie@4,0 { ++ /* 02:04.0 0604: 10b5:8609: PEX port bridge */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ reg = <0x2000 0 0 0 0>; ++ ++ eth1: pci@0,0 { ++ /* 04:00.0 0200: 11ab:4380: GigE */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ reg = <0x0 0 0 0 0>; ++ compatible = "marvell,sky2"; ++ }; ++ }; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +@@ -369,8 +369,42 @@ + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; + +- eth1: sky2@8 { /* MAC/PHY on bus 8 */ +- compatible = "marvell,sky2"; ++ pcie@0,0 { ++ /* 00:00.0 0604: 16c3:abcd root host-bridge */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ reg = <0x0 0 0 0 0>; ++ ++ pcie@0,0 { ++ /* 01:00.0 0604: 10b5:8609 PEX switch bridge */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ reg = <0x0 0 0 0 0>; ++ ++ /* ++ * GigE PCI dev node needs to be defined so that enet ++ * driver can use it to obtain its boot-loader ++ * specified MAC ++ */ ++ pcie@8,0 { ++ /* 02:08.0 0604: 10b5:8609: PEX port bridge */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ reg = <0x4000 0 0 0 0>; ++ ++ eth1: pci@0,0 { ++ /* 08:00.0 0200: 11ab:4380: GigE */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ reg = <0x0 0 0 0 0>; ++ compatible = "marvell,sky2"; ++ }; ++ }; ++ }; + }; + }; + diff --git a/target/linux/imx6/patches-4.1/100-bootargs.patch b/target/linux/imx6/patches-4.1/100-bootargs.patch new file mode 100644 index 0000000..0954391 --- /dev/null +++ b/target/linux/imx6/patches-4.1/100-bootargs.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/imx6dl-wandboard.dts ++++ b/arch/arm/boot/dts/imx6dl-wandboard.dts +@@ -19,4 +19,8 @@ + memory { + reg = <0x10000000 0x40000000>; + }; ++ ++ chosen { ++ bootargs = "console=ttymxc0,115200"; ++ }; + }; diff --git a/target/linux/imx6/patches-4.1/202-net-igb-add-i210-i211-support-for-phy-read-write.patch b/target/linux/imx6/patches-4.1/202-net-igb-add-i210-i211-support-for-phy-read-write.patch new file mode 100644 index 0000000..fb4b722 --- /dev/null +++ b/target/linux/imx6/patches-4.1/202-net-igb-add-i210-i211-support-for-phy-read-write.patch @@ -0,0 +1,129 @@ +Author: Tim Harvey +Date: Thu May 15 00:12:26 2014 -0700 + + net: igb: add i210/i211 support for phy read/write + + The i210/i211 uses the MDICNFG register for the phy address instead of the + MDIC register. + + Signed-off-by: Tim Harvey + +--- a/drivers/net/ethernet/intel/igb/e1000_phy.c ++++ b/drivers/net/ethernet/intel/igb/e1000_phy.c +@@ -135,7 +135,7 @@ out: + s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) + { + struct e1000_phy_info *phy = &hw->phy; +- u32 i, mdic = 0; ++ u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + + if (offset > MAX_PHY_REG_ADDRESS) { +@@ -148,11 +148,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ +- mdic = ((offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | +- (E1000_MDIC_OP_READ)); ++ switch (hw->mac.type) { ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ break; ++ default: ++ mdic = ((offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_READ)); ++ break; ++ } + + wr32(E1000_MDIC, mdic); ++ wrfl(); + + /* Poll the ready bit to see if the MDI read completed + * Increasing the time out as testing showed failures with +@@ -177,6 +191,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h + *data = (u16) mdic; + + out: ++ switch (hw->mac.type) { ++ /* restore MDICNFG to have phy's addr */ ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ break; ++ default: ++ break; ++ } + return ret_val; + } + +@@ -191,7 +217,7 @@ out: + s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) + { + struct e1000_phy_info *phy = &hw->phy; +- u32 i, mdic = 0; ++ u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + + if (offset > MAX_PHY_REG_ADDRESS) { +@@ -204,12 +230,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ +- mdic = (((u32)data) | +- (offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | +- (E1000_MDIC_OP_WRITE)); ++ switch (hw->mac.type) { ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ break; ++ default: ++ mdic = (((u32)data) | ++ (offset << E1000_MDIC_REG_SHIFT) | ++ (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (E1000_MDIC_OP_WRITE)); ++ break; ++ } + + wr32(E1000_MDIC, mdic); ++ wrfl(); + + /* Poll the ready bit to see if the MDI read completed + * Increasing the time out as testing showed failures with +@@ -233,6 +274,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + } + + out: ++ switch (hw->mac.type) { ++ /* restore MDICNFG to have phy's addr */ ++ case e1000_i210: ++ case e1000_i211: ++ mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); ++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); ++ wr32(E1000_MDICNFG, mdicnfg); ++ break; ++ default: ++ break; ++ } + return ret_val; + } + diff --git a/target/linux/imx6/patches-4.1/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch b/target/linux/imx6/patches-4.1/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch new file mode 100644 index 0000000..7869b1c --- /dev/null +++ b/target/linux/imx6/patches-4.1/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch @@ -0,0 +1,260 @@ +From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001 +From: Tim Harvey +Date: Thu, 15 May 2014 00:29:18 -0700 +Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr + +Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address. +The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers +to this function. + +Signed-off-by: Tim Harvey +--- + drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +- + drivers/net/ethernet/intel/igb/e1000_phy.c | 74 +++++++++++++++++++--------- + drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++- + 3 files changed, 58 insertions(+), 26 deletions(-) + +--- a/drivers/net/ethernet/intel/igb/e1000_82575.c ++++ b/drivers/net/ethernet/intel/igb/e1000_82575.c +@@ -2129,7 +2129,7 @@ static s32 igb_read_phy_reg_82580(struct + if (ret_val) + goto out; + +- ret_val = igb_read_phy_reg_mdic(hw, offset, data); ++ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data); + + hw->phy.ops.release(hw); + +@@ -2154,7 +2154,7 @@ static s32 igb_write_phy_reg_82580(struc + if (ret_val) + goto out; + +- ret_val = igb_write_phy_reg_mdic(hw, offset, data); ++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data); + + hw->phy.ops.release(hw); + +--- a/drivers/net/ethernet/intel/igb/e1000_phy.c ++++ b/drivers/net/ethernet/intel/igb/e1000_phy.c +@@ -132,9 +132,8 @@ out: + * Reads the MDI control regsiter in the PHY at offset and stores the + * information read to data. + **/ +-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) + { +- struct e1000_phy_info *phy = &hw->phy; + u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + +@@ -153,14 +152,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h + case e1000_i211: + mdicnfg = rd32(E1000_MDICNFG); + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); +- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); + wr32(E1000_MDICNFG, mdicnfg); + mdic = ((offset << E1000_MDIC_REG_SHIFT) | + (E1000_MDIC_OP_READ)); + break; + default: + mdic = ((offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_READ)); + break; + } +@@ -214,9 +213,8 @@ out: + * + * Writes data to MDI control register in the PHY at offset. + **/ +-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) ++s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) + { +- struct e1000_phy_info *phy = &hw->phy; + u32 i, mdicnfg, mdic = 0; + s32 ret_val = 0; + +@@ -235,7 +233,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + case e1000_i211: + mdicnfg = rd32(E1000_MDICNFG); + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); +- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); ++ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); + wr32(E1000_MDICNFG, mdicnfg); + mdic = (((u32)data) | + (offset << E1000_MDIC_REG_SHIFT) | +@@ -244,7 +242,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ + default: + mdic = (((u32)data) | + (offset << E1000_MDIC_REG_SHIFT) | +- (phy->addr << E1000_MDIC_PHY_SHIFT) | ++ (addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_WRITE)); + break; + } +@@ -464,7 +462,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw + goto out; + + if (offset > MAX_PHY_MULTI_PAGE_REG) { +- ret_val = igb_write_phy_reg_mdic(hw, ++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, + IGP01E1000_PHY_PAGE_SELECT, + (u16)offset); + if (ret_val) { +@@ -473,8 +471,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw + } + } + +- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, +- data); ++ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, ++ MAX_PHY_REG_ADDRESS & offset, data); + + hw->phy.ops.release(hw); + +@@ -503,7 +501,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h + goto out; + + if (offset > MAX_PHY_MULTI_PAGE_REG) { +- ret_val = igb_write_phy_reg_mdic(hw, ++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, + IGP01E1000_PHY_PAGE_SELECT, + (u16)offset); + if (ret_val) { +@@ -512,8 +510,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h + } + } + +- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, +- data); ++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, ++ MAX_PHY_REG_ADDRESS & offset, data); + + hw->phy.ops.release(hw); + +@@ -2464,8 +2462,9 @@ out: + } + + /** +- * igb_write_phy_reg_gs40g - Write GS40G PHY register ++ * igb_write_reg_gs40g - Write GS40G PHY register + * @hw: pointer to the HW structure ++ * @addr: phy address to write to + * @offset: lower half is register offset to write to + * upper half is page to use. + * @data: data to write at register offset +@@ -2473,7 +2472,7 @@ out: + * Acquires semaphore, if necessary, then writes the data to PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) ++s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) + { + s32 ret_val; + u16 page = offset >> GS40G_PAGE_SHIFT; +@@ -2483,10 +2482,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000 + if (ret_val) + return ret_val; + +- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); ++ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); + if (ret_val) + goto release; +- ret_val = igb_write_phy_reg_mdic(hw, offset, data); ++ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data); + + release: + hw->phy.ops.release(hw); +@@ -2494,8 +2493,24 @@ release: + } + + /** +- * igb_read_phy_reg_gs40g - Read GS40G PHY register ++ * igb_write_phy_reg_gs40g - Write GS40G PHY register ++ * @hw: pointer to the HW structure ++ * @offset: lower half is register offset to write to ++ * upper half is page to use. ++ * @data: data to write at register offset ++ * ++ * Acquires semaphore, if necessary, then writes the data to PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) ++{ ++ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data); ++} ++ ++/** ++ * igb_read_reg_gs40g - Read GS40G PHY register + * @hw: pointer to the HW structure ++ * @addr: phy address to read from + * @offset: lower half is register offset to read to + * upper half is page to use. + * @data: data to read at register offset +@@ -2503,7 +2518,7 @@ release: + * Acquires semaphore, if necessary, then reads the data in the PHY register + * at the offset. Release any acquired semaphores before exiting. + **/ +-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) ++s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) + { + s32 ret_val; + u16 page = offset >> GS40G_PAGE_SHIFT; +@@ -2513,10 +2528,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_ + if (ret_val) + return ret_val; + +- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); ++ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); + if (ret_val) + goto release; +- ret_val = igb_read_phy_reg_mdic(hw, offset, data); ++ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data); + + release: + hw->phy.ops.release(hw); +@@ -2524,6 +2539,21 @@ release: + } + + /** ++ * igb_read_phy_reg_gs40g - Read GS40G PHY register ++ * @hw: pointer to the HW structure ++ * @offset: lower half is register offset to read to ++ * upper half is page to use. ++ * @data: data to read at register offset ++ * ++ * Acquires semaphore, if necessary, then reads the data in the PHY register ++ * at the offset. Release any acquired semaphores before exiting. ++ **/ ++s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) ++{ ++ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data); ++} ++ ++/** + * igb_set_master_slave_mode - Setup PHY for Master/slave mode + * @hw: pointer to the HW structure + * +--- a/drivers/net/ethernet/intel/igb/e1000_phy.h ++++ b/drivers/net/ethernet/intel/igb/e1000_phy.h +@@ -61,8 +61,8 @@ s32 igb_phy_has_link(struct e1000_hw *h + void igb_power_up_phy_copper(struct e1000_hw *hw); + void igb_power_down_phy_copper(struct e1000_hw *hw); + s32 igb_phy_init_script_igp3(struct e1000_hw *hw); +-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); +-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); ++s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); ++s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); + s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); + s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); + s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); +@@ -72,6 +72,8 @@ s32 igb_phy_force_speed_duplex_82580(st + s32 igb_get_cable_length_82580(struct e1000_hw *hw); + s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); + s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); ++s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); ++s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); + s32 igb_check_polarity_m88(struct e1000_hw *hw); + + /* IGP01E1000 Specific Registers */ diff --git a/target/linux/imx6/patches-4.1/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch b/target/linux/imx6/patches-4.1/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch new file mode 100644 index 0000000..d503e91 --- /dev/null +++ b/target/linux/imx6/patches-4.1/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch @@ -0,0 +1,308 @@ +From 03855caf93f7332a3f320228ba1a0e7baae8a749 Mon Sep 17 00:00:00 2001 +From: Tim Harvey +Date: Thu, 15 May 2014 12:36:23 -0700 +Subject: [PATCH] net: igb: register mii_bus for SerDes w/ external phy + +If an i210 is configured for 1000BASE-BX link_mode and has an external phy +specified, then register an mii bus using the external phy address as +a mask. + +An i210 hooked to an external standard phy will be configured with a link_mo +of SGMII in which case phy ops will be configured and used internall in the +igb driver for link status. However, in certain cases one might be using a +backplane SerDes connection to something that talks on the mdio bus but is +not a standard phy, such as a switch. In this case by registering an mdio +bus a phy driver can manage the device. + +Signed-off-by: Tim Harvey +--- + drivers/net/ethernet/intel/igb/e1000_82575.c | 15 +++ + drivers/net/ethernet/intel/igb/e1000_hw.h | 7 ++ + drivers/net/ethernet/intel/igb/igb_main.c | 168 ++++++++++++++++++++++++++- + 3 files changed, 185 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/intel/igb/e1000_82575.c ++++ b/drivers/net/ethernet/intel/igb/e1000_82575.c +@@ -598,13 +598,25 @@ static s32 igb_get_invariants_82575(stru + switch (link_mode) { + case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: + hw->phy.media_type = e1000_media_type_internal_serdes; ++ if (igb_sgmii_uses_mdio_82575(hw)) { ++ u32 mdicnfg = rd32(E1000_MDICNFG); ++ mdicnfg &= E1000_MDICNFG_PHY_MASK; ++ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT; ++ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n", ++ hw->phy.addr); ++ } else { ++ hw_dbg("1000BASE_KX"); ++ } + break; + case E1000_CTRL_EXT_LINK_MODE_SGMII: + /* Get phy control interface type set (MDIO vs. I2C)*/ + if (igb_sgmii_uses_mdio_82575(hw)) { + hw->phy.media_type = e1000_media_type_copper; + dev_spec->sgmii_active = true; ++ hw_dbg("SGMII with external MDIO PHY"); + break; ++ } else { ++ hw_dbg("SGMII with external I2C PHY"); + } + /* fall through for I2C based SGMII */ + case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: +@@ -621,8 +633,11 @@ static s32 igb_get_invariants_82575(stru + hw->phy.media_type = e1000_media_type_copper; + dev_spec->sgmii_active = true; + } ++ hw_dbg("SERDES with external SFP"); + + break; ++ } else { ++ hw_dbg("SERDES"); + } + + /* do not change link mode for 100BaseFX */ +--- a/drivers/net/ethernet/intel/igb/e1000_hw.h ++++ b/drivers/net/ethernet/intel/igb/e1000_hw.h +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include "e1000_regs.h" + #include "e1000_defines.h" +@@ -543,6 +544,12 @@ struct e1000_hw { + struct e1000_mbx_info mbx; + struct e1000_host_mng_dhcp_cookie mng_cookie; + ++#ifdef CONFIG_PHYLIB ++ /* Phylib and MDIO interface */ ++ struct mii_bus *mii_bus; ++ struct phy_device *phy_dev; ++ phy_interface_t phy_interface; ++#endif + union { + struct e1000_dev_spec_82575 _82575; + } dev_spec; +--- a/drivers/net/ethernet/intel/igb/igb_main.c ++++ b/drivers/net/ethernet/intel/igb/igb_main.c +@@ -41,6 +41,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -2231,6 +2232,126 @@ static s32 igb_init_i2c(struct igb_adapt + return status; + } + ++ ++#ifdef CONFIG_PHYLIB ++/* ++ * MMIO/PHYdev support ++ */ ++ ++static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) ++{ ++ struct e1000_hw *hw = bus->priv; ++ u16 out; ++ int err; ++ ++ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out); ++ if (err) ++ return err; ++ return out; ++} ++ ++static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, ++ u16 val) ++{ ++ struct e1000_hw *hw = bus->priv; ++ ++ return igb_write_reg_gs40g(hw, mii_id, regnum, val); ++} ++ ++static int igb_enet_mdio_reset(struct mii_bus *bus) ++{ ++ udelay(300); ++ return 0; ++} ++ ++static void igb_enet_mii_link(struct net_device *netdev) ++{ ++} ++ ++/* Probe the mdio bus for phys and connect them */ ++static int igb_enet_mii_probe(struct net_device *netdev) ++{ ++ struct igb_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ struct phy_device *phy_dev = NULL; ++ int phy_id; ++ ++ /* check for attached phy */ ++ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { ++ if (hw->mii_bus->phy_map[phy_id]) { ++ phy_dev = hw->mii_bus->phy_map[phy_id]; ++ break; ++ } ++ } ++ if (!phy_dev) { ++ netdev_err(netdev, "no PHY found\n"); ++ return -ENODEV; ++ } ++ ++ hw->phy_interface = PHY_INTERFACE_MODE_RGMII; ++ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev), ++ igb_enet_mii_link, hw->phy_interface); ++ if (IS_ERR(phy_dev)) { ++ netdev_err(netdev, "could not attach to PHY\n"); ++ return PTR_ERR(phy_dev); ++ } ++ ++ hw->phy_dev = phy_dev; ++ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n", ++ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev)); ++ ++ return 0; ++} ++ ++/* Create and register mdio bus */ ++static int igb_enet_mii_init(struct pci_dev *pdev) ++{ ++ struct mii_bus *mii_bus; ++ struct net_device *netdev = pci_get_drvdata(pdev); ++ struct igb_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; ++ int err; ++ ++ mii_bus = mdiobus_alloc(); ++ if (mii_bus == NULL) { ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ mii_bus->name = "igb_enet_mii_bus"; ++ mii_bus->read = igb_enet_mdio_read; ++ mii_bus->write = igb_enet_mdio_write; ++ mii_bus->reset = igb_enet_mdio_reset; ++ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", ++ pci_name(pdev), hw->device_id + 1); ++ mii_bus->priv = hw; ++ mii_bus->parent = &pdev->dev; ++ mii_bus->phy_mask = ~(1 << hw->phy.addr); ++ ++ err = mdiobus_register(mii_bus); ++ if (err) { ++ printk(KERN_ERR "failed to register mii_bus: %d\n", err); ++ goto err_out_free_mdiobus; ++ } ++ hw->mii_bus = mii_bus; ++ ++ return 0; ++ ++err_out_free_mdiobus: ++ mdiobus_free(mii_bus); ++err_out: ++ return err; ++} ++ ++static void igb_enet_mii_remove(struct e1000_hw *hw) ++{ ++ if (hw->mii_bus) { ++ mdiobus_unregister(hw->mii_bus); ++ mdiobus_free(hw->mii_bus); ++ } ++} ++#endif /* CONFIG_PHYLIB */ ++ + /** + * igb_probe - Device Initialization Routine + * @pdev: PCI device information struct +@@ -2653,6 +2774,13 @@ static int igb_probe(struct pci_dev *pde + } + } + pm_runtime_put_noidle(&pdev->dev); ++ ++#ifdef CONFIG_PHYLIB ++ /* create and register the mdio bus if using ext phy */ ++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) ++ igb_enet_mii_init(pdev); ++#endif ++ + return 0; + + err_register: +@@ -2796,6 +2924,10 @@ static void igb_remove(struct pci_dev *p + struct e1000_hw *hw = &adapter->hw; + + pm_runtime_get_noresume(&pdev->dev); ++#ifdef CONFIG_PHYLIB ++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) ++ igb_enet_mii_remove(hw); ++#endif + #ifdef CONFIG_IGB_HWMON + igb_sysfs_exit(adapter); + #endif +@@ -3101,6 +3233,12 @@ static int __igb_open(struct net_device + if (!resuming) + pm_runtime_put(&pdev->dev); + ++#ifdef CONFIG_PHYLIB ++ /* Probe and connect to PHY if using ext phy */ ++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) ++ igb_enet_mii_probe(netdev); ++#endif ++ + /* start the watchdog. */ + hw->mac.get_link_status = 1; + schedule_work(&adapter->watchdog_task); +@@ -7097,21 +7235,41 @@ void igb_alloc_rx_buffers(struct igb_rin + static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) + { + struct igb_adapter *adapter = netdev_priv(netdev); ++ struct e1000_hw *hw = &adapter->hw; + struct mii_ioctl_data *data = if_mii(ifr); + +- if (adapter->hw.phy.media_type != e1000_media_type_copper) ++ if (adapter->hw.phy.media_type != e1000_media_type_copper && ++ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)) + return -EOPNOTSUPP; + + switch (cmd) { + case SIOCGMIIPHY: +- data->phy_id = adapter->hw.phy.addr; ++ data->phy_id = hw->phy.addr; + break; + case SIOCGMIIREG: +- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, +- &data->val_out)) +- return -EIO; ++ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { ++ if (igb_read_reg_gs40g(&adapter->hw, data->phy_id, ++ data->reg_num & 0x1F, ++ &data->val_out)) ++ return -EIO; ++ } else { ++ if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, ++ &data->val_out)) ++ return -EIO; ++ } + break; + case SIOCSMIIREG: ++ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { ++ if (igb_write_reg_gs40g(hw, data->phy_id, ++ data->reg_num & 0x1F, ++ data->val_in)) ++ return -EIO; ++ } else { ++ if (igb_write_phy_reg(hw, data->reg_num & 0x1F, ++ data->val_in)) ++ return -EIO; ++ } ++ break; + default: + return -EOPNOTSUPP; + } diff --git a/target/linux/imx6/patches-4.1/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch b/target/linux/imx6/patches-4.1/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch new file mode 100644 index 0000000..e991fad --- /dev/null +++ b/target/linux/imx6/patches-4.1/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch @@ -0,0 +1,27 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -292,6 +292,14 @@ endif # RTL8366_SMI + + source "drivers/net/phy/b53/Kconfig" + ++config GATEWORKS_GW16083 ++ tristate "Gateworks GW16083 Ethernet Expansion Mezzanine" ++ ---help--- ++ The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a ++ Gateworks Ventana baseboard and provides a 7-port GbE managed ++ Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP ++ ports" ++ + endif # PHYLIB + + config MICREL_KS8995MA +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_DP83640_PHY) += dp83640.o + obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_MICREL_PHY) += micrel.o ++obj-$(CONFIG_GATEWORKS_GW16083) += gw16083.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_AT803X_PHY) += at803x.o diff --git a/target/linux/imx6/patches-4.1/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch b/target/linux/imx6/patches-4.1/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch new file mode 100644 index 0000000..6f31f95 --- /dev/null +++ b/target/linux/imx6/patches-4.1/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch @@ -0,0 +1,56 @@ +--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +@@ -89,6 +89,11 @@ + enable-active-high; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &fec { +--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +@@ -266,6 +266,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &pcie { +--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +@@ -267,6 +267,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &pcie { +--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi ++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +@@ -308,6 +308,11 @@ + }; + }; + }; ++ ++ gw16083: gw16083@52 { ++ compatible = "gateworks,gw16083"; ++ reg = <0x52>; ++ }; + }; + + &i2c3 { diff --git a/target/linux/imx6/profiles/100-generic.mk b/target/linux/imx6/profiles/100-generic.mk new file mode 100644 index 0000000..cdb58e4 --- /dev/null +++ b/target/linux/imx6/profiles/100-generic.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Generic + NAME:=Generic (default) + PACKAGES:= \ + kmod-thermal-imx kmod-usb-chipidea-imx kmod-usb-mxs-phy +endef + +define Profile/Generic/Description + Package set compatible with most Freescale i.MX 6 based boards. +endef + +$(eval $(call Profile,Generic)) diff --git a/target/linux/imx6/profiles/110-wandboard.mk b/target/linux/imx6/profiles/110-wandboard.mk new file mode 100644 index 0000000..0763355 --- /dev/null +++ b/target/linux/imx6/profiles/110-wandboard.mk @@ -0,0 +1,14 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/IMX6DL_WANDBOARD + NAME:=Wandboard Dual + PACKAGES:= \ + kmod-thermal-imx kmod-usb-chipidea-imx kmod-usb-mxs-phy +endef + +$(eval $(call Profile,IMX6DL_WANDBOARD)) diff --git a/target/linux/imx6/profiles/120-gateworks.mk b/target/linux/imx6/profiles/120-gateworks.mk new file mode 100644 index 0000000..115021a --- /dev/null +++ b/target/linux/imx6/profiles/120-gateworks.mk @@ -0,0 +1,52 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/VENTANA + NAME:=Gateworks Ventana family + PACKAGES:= \ + kmod-thermal-imx kmod-sky2 kmod-usb-chipidea-imx kmod-usb-mxs-phy \ + kmod-sound-core kmod-sound-soc-imx kmod-sound-soc-imx-sgtl5000 \ + kmod-can kmod-can-flexcan kmod-can-raw \ + kmod-rtc-ds1672 kmod-gpio-pca953x kmod-hwmon-gsc kmod-eeprom-at24 \ + kmod-leds-gpio kmod-pps-gpio kmod-gw16083 \ + kobs-ng +endef + +define Profile/VENTANA/Description + The Gateworks Ventana family of products is based on the Freescale i.MX6Q SoC + and offers a large variety of peripherals such as: + + * DDR3 + * NAND or SPI flash + * multiple PCIe (with USB for Cellular modems) + * Optional expansion for additional USB/PCI based periperhals + * USB EHCI + * USB OTG + * HDMI Audio/Video in/out + * Analog Video in/out + * Analog Audio in/out + * Gateworks System Controller + * Optional GPS with PPS + * Canbus + * User GPIO + * mSATA +endef + +VENTANA_DTS:= \ + imx6dl-gw51xx \ + imx6dl-gw52xx \ + imx6dl-gw53xx \ + imx6dl-gw54xx \ + imx6dl-gw552x \ + imx6q-gw51xx \ + imx6q-gw52xx \ + imx6q-gw53xx \ + imx6q-gw54xx \ + imx6q-gw5400-a \ + imx6q-gw552x + +$(eval $(call Profile,VENTANA)) diff --git a/target/linux/ipq806x/Makefile b/target/linux/ipq806x/Makefile new file mode 100644 index 0000000..45f83dd --- /dev/null +++ b/target/linux/ipq806x/Makefile @@ -0,0 +1,22 @@ +# Copyright (c) 2013 The Linux Foundation. All rights reserved. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=ipq806x +BOARDNAME:=Qualcomm Atheros IPQ806X +FEATURES:=squashfs nand ubifs +CPU_TYPE:=cortex-a7 +MAINTAINER:=John Crispin + +KERNEL_PATCHVER:=3.18 + +KERNELNAME:=zImage Image dtbs + +include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += \ + kmod-leds-gpio kmod-gpio-button-hotplug swconfig \ + kmod-ata-core kmod-ata-ahci kmod-ata-ahci-platform + + +$(eval $(call BuildTarget)) diff --git a/target/linux/ipq806x/base-files.mk b/target/linux/ipq806x/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/ipq806x/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/ipq806x/base-files/etc/inittab b/target/linux/ipq806x/base-files/etc/inittab new file mode 100644 index 0000000..19a6e11 --- /dev/null +++ b/target/linux/ipq806x/base-files/etc/inittab @@ -0,0 +1,4 @@ +# Copyright (c) 2013 The Linux Foundation. All rights reserved. +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttyMSM0::askfirst:/bin/ash --login diff --git a/target/linux/ipq806x/base-files/etc/uci-defaults/leds b/target/linux/ipq806x/base-files/etc/uci-defaults/leds new file mode 100644 index 0000000..362c5b6 --- /dev/null +++ b/target/linux/ipq806x/base-files/etc/uci-defaults/leds @@ -0,0 +1,26 @@ +#!/bin/sh +# +# Copyright (C) 2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/ipq806x.sh + +board=$(ipq806x_board_name) + +case "$board" in +r7500) + ucidef_set_led_usbdev "usb1" "USB 1" "r7500:white:usb1" "1-1" + ucidef_set_led_usbdev "usb2" "USB 2" "r7500:white:usb3" "3-1" + ucidef_set_led_netdev "wan" "WAN" "r7500:white:wan" "eth0" + ucidef_set_led_ide_disk "esata" "eSATA" "r7500:amber:esata" + ucidef_set_led_default "wps" "WPS" "r7500:white:wps" "0" + ucidef_set_led_default "rfkill" "rfkill" "r7500:white:rfkill" "0" + ;; +*) + ;; +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/ipq806x/base-files/etc/uci-defaults/network b/target/linux/ipq806x/base-files/etc/uci-defaults/network new file mode 100755 index 0000000..7742b73 --- /dev/null +++ b/target/linux/ipq806x/base-files/etc/uci-defaults/network @@ -0,0 +1,39 @@ +#!/bin/sh +# +# Copyright (c) 2015 The Linux Foundation. All rights reserved. +# Copyright (C) 2011 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/ipq806x.sh + +ucidef_set_interface_loopback + +board=$(ipq806x_board_name) + +case "$board" in +ap148 |\ +r7500) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "6 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0 5" + ;; +db149) + ucidef_set_interfaces_lan_wan "eth1 eth2 eth3" "eth0" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "6 1 2 3 4" + ucidef_add_switch_vlan "switch0" "2" "0 5" + ;; +*) + echo "Unsupported hardware. Network interfaces not intialized" + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/ipq806x/base-files/lib/ipq806x.sh b/target/linux/ipq806x/base-files/lib/ipq806x.sh new file mode 100644 index 0000000..5b27bde --- /dev/null +++ b/target/linux/ipq806x/base-files/lib/ipq806x.sh @@ -0,0 +1,46 @@ +#!/bin/sh +# +# Copyright (c) 2014 The Linux Foundation. All rights reserved. +# Copyright (C) 2011 OpenWrt.org +# + +IPQ806X_BOARD_NAME= +IPQ806X_MODEL= + +ipq806x_board_detect() { + local machine + local name + + machine=$(cat /proc/device-tree/model) + + case "$machine" in + *"AP148") + name="ap148" + ;; + *"DB149") + name="db149" + ;; + *"R7500") + name="r7500" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$IPQ806X_BOARD_NAME" ] && IPQ806X_BOARD_NAME="$name" + [ -z "$IPQ806X_MODEL" ] && IPQ806X_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$IPQ806X_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$IPQ806X_MODEL" > /tmp/sysinfo/model +} + +ipq806x_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/ipq806x/base-files/lib/preinit/03_preinit_do_ipq806x.sh b/target/linux/ipq806x/base-files/lib/preinit/03_preinit_do_ipq806x.sh new file mode 100644 index 0000000..785f1eb --- /dev/null +++ b/target/linux/ipq806x/base-files/lib/preinit/03_preinit_do_ipq806x.sh @@ -0,0 +1,12 @@ +#!/bin/sh +# +# Copyright (c) 2014 The Linux Foundation. All rights reserved. +# + +do_ipq806x() { + . /lib/ipq806x.sh + + ipq806x_board_detect +} + +boot_hook_add preinit_main do_ipq806x diff --git a/target/linux/ipq806x/base-files/lib/upgrade/platform.sh b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..c0e19a1 --- /dev/null +++ b/target/linux/ipq806x/base-files/lib/upgrade/platform.sh @@ -0,0 +1,30 @@ +. /lib/ipq806x.sh + +PART_NAME=firmware + +platform_check_image() { + local board=$(ipq806x_board_name) + + case "$board" in + AP148 |\ + r7500) + nand_do_platform_check $board $1 + return $?; + ;; + *) + return 1; + esac +} + +platform_pre_upgrade() { + local board=$(ipq806x_board_name) + + case "$board" in + AP148 |\ + r7500) + nand_do_upgrade "$1" + ;; + esac +} + +# use default for platform_do_upgrade() diff --git a/target/linux/ipq806x/config-3.18 b/target/linux/ipq806x/config-3.18 new file mode 100644 index 0000000..cb3dcfc --- /dev/null +++ b/target/linux/ipq806x/config-3.18 @@ -0,0 +1,444 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_AMBA_PL08X is not set +# CONFIG_APM_EMULATION is not set +CONFIG_APQ_GCC_8084=y +CONFIG_APQ_MMCC_8084=y +CONFIG_AR8216_PHY=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MSM8960=y +CONFIG_ARCH_MSM8974=y +CONFIG_ARCH_MSM8X60=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_QCOM_CPUFREQ=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AT803X_PHY=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_BOUNCE=y +CONFIG_BUILD_BIN2C=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CLEANCACHE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_QCOM=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_COMPACTION=y +CONFIG_COREDUMP=y +# CONFIG_CPUFREQ_DT is not set +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_SHA1_ARM_NEON is not set +# CONFIG_CRYPTO_SHA512_ARM_NEON is not set +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DWMAC_IPQ806X=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_FIXED_PHY=y +CONFIG_FREEZER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CPUFREQ_KRAIT=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_DEVRES=y +# CONFIG_GPIO_MSM_V2 is not set +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_QUP=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_API=y +CONFIG_IOMMU_HELPER=y +CONFIG_IOMMU_PGTABLES_L2=y +CONFIG_IOMMU_SUPPORT=y +CONFIG_IPQ_GCC_806X=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KPSS_XCC=y +CONFIG_KRAITCC=y +CONFIG_KRAIT_CLOCKS=y +CONFIG_KRAIT_L2_ACCESSORS=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LIBFDT=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MDIO_GPIO=y +CONFIG_MFD_QCOM_RPM=y +# CONFIG_MFD_SPMI_PMIC is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MSM_GCC_8660=y +CONFIG_MSM_GCC_8960=y +CONFIG_MSM_GCC_8974=y +CONFIG_MSM_IOMMU=y +CONFIG_MSM_MMCC_8960=y +CONFIG_MSM_MMCC_8974=y +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_IMPA7 is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_QCOM_SMEM_PARTS=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IOMMU=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +CONFIG_PCIE_QCOM=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_MSI=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +# CONFIG_PHY_QCOM_APQ8064_SATA is not set +CONFIG_PHY_QCOM_IPQ806X_SATA=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_APQ8064=y +# CONFIG_PINCTRL_APQ8084 is not set +CONFIG_PINCTRL_IPQ8064=y +CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_MSM8960 is not set +CONFIG_PINCTRL_MSM8X74=y +# CONFIG_PL330_DMA is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +CONFIG_POWER_RESET_MSM=y +# CONFIG_POWER_RESET_SYSCON is not set +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_QCOM_ADM=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_GSBI=y +CONFIG_QCOM_HFPLL=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_WDT=y +CONFIG_RAS=y +# CONFIG_RCU_BOOST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_CPU_STALL_VERBOSE=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_GZIP=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_QCOM_RPM=y +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_QUP=y +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +# CONFIG_STMMAC_DA is not set +CONFIG_STMMAC_DEBUG_FS=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_STOP_MACHINE=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFIO is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WIZNET_W5100 is not set +# CONFIG_WIZNET_W5300 is not set +# CONFIG_WL_TI is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ipq806x/config-4.1 b/target/linux/ipq806x/config-4.1 new file mode 100644 index 0000000..4ead455 --- /dev/null +++ b/target/linux/ipq806x/config-4.1 @@ -0,0 +1,449 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_AMBA_PL08X is not set +# CONFIG_APM_EMULATION is not set +CONFIG_APQ_GCC_8084=y +CONFIG_APQ_MMCC_8084=y +CONFIG_AR8216_PHY=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MSM8960=y +CONFIG_ARCH_MSM8974=y +CONFIG_ARCH_MSM8X60=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_QCOM=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_CCI=y +CONFIG_ARM_CCI400_COMMON=y +CONFIG_ARM_CCI400_PMU=y +# CONFIG_ARM_CPUIDLE is not set +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_QCOM_CPUFREQ=y +# CONFIG_ARM_SMMU is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AT803X_PHY=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_BOUNCE=y +CONFIG_BUILD_BIN2C=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CLEANCACHE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_QCOM=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_COMPACTION=y +CONFIG_COREDUMP=y +# CONFIG_CPUFREQ_DT is not set +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DEVMEM=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_PCI is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_FIXED_PHY=y +CONFIG_FREEZER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPUFREQ_KRAIT=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_DEVRES=y +# CONFIG_GPIO_MSM_V2 is not set +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CPU=y +# CONFIG_HSU_DMA_PCI is not set +CONFIG_HWMON=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_QUP=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IPQ_GCC_806X=y +# CONFIG_IPQ_LCC_806X is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KPSS_XCC=y +CONFIG_KRAITCC=y +CONFIG_KRAIT_CLOCKS=y +CONFIG_KRAIT_L2_ACCESSORS=y +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LIBFDT=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MDIO_GPIO=y +CONFIG_MFD_QCOM_RPM=y +# CONFIG_MFD_SPMI_PMIC is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MIGRATION=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MSM_GCC_8660=y +# CONFIG_MSM_GCC_8916 is not set +CONFIG_MSM_GCC_8960=y +CONFIG_MSM_GCC_8974=y +# CONFIG_MSM_LCC_8960 is not set +CONFIG_MSM_MMCC_8960=y +CONFIG_MSM_MMCC_8974=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_QCOM=y +CONFIG_MTD_QCOM_SMEM_PARTS=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_DW=y +# CONFIG_PCIE_IPROC is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_QCOM=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_PHY_QCOM_APQ8064_SATA is not set +CONFIG_PHY_QCOM_IPQ806X_SATA=y +# CONFIG_PHY_QCOM_UFS is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_APQ8064=y +# CONFIG_PINCTRL_APQ8084 is not set +CONFIG_PINCTRL_IPQ8064=y +CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_MSM8916 is not set +# CONFIG_PINCTRL_MSM8960 is not set +CONFIG_PINCTRL_MSM8X74=y +# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set +# CONFIG_PL330_DMA is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_QCOM_ADM=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_GSBI=y +CONFIG_QCOM_HFPLL=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_WDT=y +CONFIG_RAS=y +# CONFIG_RCU_BOOST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_GZIP=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_QCOM_RPM=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_QUP=y +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB=y +CONFIG_SRCU=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_STOP_MACHINE=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VDSO=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WIZNET_W5100 is not set +# CONFIG_WIZNET_W5300 is not set +# CONFIG_WL_TI is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ipq806x/image/Makefile b/target/linux/ipq806x/image/Makefile new file mode 100644 index 0000000..14cf442 --- /dev/null +++ b/target/linux/ipq806x/image/Makefile @@ -0,0 +1,126 @@ +# Copyright (c) 2014 The Linux Foundation. All rights reserved. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +UBIFS_OPTS = -m 2048 -e 124KiB -c 4096 -U -F +UBINIZE_OPTS = -m 2048 -p 128KiB + +KERNEL_LOADADDR := 0x42208000 + +define Image/Prepare + $(CP) $(LINUX_DIR)/vmlinux $(KDIR)/$(IMG_PREFIX)-vmlinux.elf + mkimage -A arm -O linux -T filesystem -C none \ + -a $(KERNEL_LOADADDR) -e $(KERNEL_LOADADDR) \ + -n 'ARM OpenWrt fakeroot' \ + -s $(KDIR_TMP)/root.dummy-uImage.tmp + echo -ne '\xff' > $(KDIR_TMP)/root.dummy + cat $(KDIR_TMP)/root.dummy $(KDIR_TMP)/root.dummy-uImage.tmp > $(KDIR)/root.dummy +endef + +define Image/BuildKernel + $(CP) $(KDIR)/$(IMG_PREFIX)-vmlinux.elf $(BIN_DIR) +endef + +define Image/Build/squashfs + cp $(KDIR)/root.squashfs $(KDIR)/root.squashfs-raw + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +endef + +define Image/Build + $(call Image/Build/$(1),$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-root.img bs=2k conv=sync +endef + +define Build/append-dtb + cat $(DTS_DIR)/$(DEVICE_DTS).dtb >> $@ +endef + +define Build/append-file + cat $(1) >> $@ +endef + +define Device/Default + PROFILES := Default + KERNEL_INITRAMFS_PREFIX := $$(IMG_PREFIX)-$(1)-initramfs + DEVICE_DTS := + KERNEL_PREFIX := $$(IMAGE_PREFIX) + IMAGES := + KERNEL_IN_UBI := + BOARD_NAME := +endef +DEVICE_VARS += DEVICE_DTS KERNEL_IN_UBI BOARD_NAME + +define Device/LegacyImage + KERNEL_SUFFIX := -uImage + KERNEL = kernel-bin | append-dtb | uImage none + KERNEL_NAME := zImage +endef + +define Device/FitImage + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +define Device/UbiFit + KERNEL_IN_UBI := 1 + IMAGES := nand-factory.ubi nand-sysupgrade.tar + IMAGE/nand-factory.ubi := append-ubi + IMAGE/nand-sysupgrade.tar := sysupgrade-nand +endef + +define Device/DniImage + PROFILES += $$(DEVICE_NAME) + FILESYSTEMS := squashfs + KERNEL_SUFFIX := -uImage + KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none + KERNEL = kernel-bin | append-dtb | pad-to $$$$(($$(KERNEL_SIZE)-2*64-1)) | uImage none | append-file $(KDIR)/root.dummy + KERNEL_NAME := zImage + NETGEAR_BOARD_ID := + NETGEAR_HW_ID := + IMAGES := factory.img sysupgrade.tar + IMAGE/factory.img := append-kernel | append-ubi | netgear-dni + IMAGE/sysupgrade.tar = sysupgrade-nand +endef +DEVICE_VARS += KERNEL_SIZE NETGEAR_BOARD_ID NETGEAR_HW_ID DEVICE_BLOCK_SIZE DEVICE_PAGE_SIZE + +define Device/AP148 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_DTS := qcom-ipq8064-ap148 + BLOCKSIZE := 128KiB + PAGESIZE := 2048 + BOARD_NAME := ap148 +endef + +define Device/AP148-legacy + $(call Device/LegacyImage) + $(call Device/UbiFit) + DEVICE_DTS := qcom-ipq8064-ap148 + BLOCKSIZE := 128KiB + PAGESIZE := 2048 + BOARD_NAME := ap148 +endef + +define Device/DB149 + $(call Device/FitImage) + DEVICE_DTS := qcom-ipq8064-db149 + KERNEL_INSTALL := 1 + BOARD_NAME := db149 +endef + +define Device/R7500 + $(call Device/DniImage) + DEVICE_DTS := qcom-ipq8064-r7500 + KERNEL_SIZE := 2097152 + NETGEAR_BOARD_ID := R7500 + NETGEAR_HW_ID := 29764841+0+128+256+3x3+4x4 + BLOCKSIZE := 128KiB + PAGESIZE := 2048 + BOARD_NAME := r7500 +endef + +TARGET_DEVICES += AP148 AP148-legacy DB149 R7500 + +$(eval $(call BuildImage)) diff --git a/target/linux/ipq806x/modules.mk b/target/linux/ipq806x/modules.mk new file mode 100644 index 0000000..04a2d4f --- /dev/null +++ b/target/linux/ipq806x/modules.mk @@ -0,0 +1,32 @@ +define KernelPackage/usb-phy-qcom-dwc3 + TITLE:=DWC3 USB QCOM PHY driver + DEPENDS:=@TARGET_ipq806x + KCONFIG:= CONFIG_PHY_QCOM_DWC3 + FILES:= $(LINUX_DIR)/drivers/phy/phy-qcom-dwc3.ko + AUTOLOAD:=$(call AutoLoad,45,phy-qcom-dwc3,1) + $(call AddDepends/usb) +endef + +define KernelPackage/usb-phy-qcom-dwc3/description + This driver provides support for the integrated DesignWare + USB3 IP Core within the QCOM SoCs. +endef + +$(eval $(call KernelPackage,usb-phy-qcom-dwc3)) + + +define KernelPackage/usb-dwc3-qcom + TITLE:=DWC3 USB QCOM controller driver + DEPENDS:=@TARGET_ipq806x +kmod-usb-dwc3 +kmod-usb-phy-qcom-dwc3 + KCONFIG:= CONFIG_USB_DWC3_QCOM + FILES:= $(LINUX_DIR)/drivers/usb/dwc3/dwc3-qcom.ko + AUTOLOAD:=$(call AutoLoad,53,dwc3-qcom,1) + $(call AddDepends/usb) +endef + +define KernelPackage/usb-dwc3-qcom/description + This driver provides support for the integrated DesignWare + USB3 IP Core within the QCOM SoCs. +endef + +$(eval $(call KernelPackage,usb-dwc3-qcom)) diff --git a/target/linux/ipq806x/patches-3.18/001-spi-qup-Add-DMA-capabilities.patch b/target/linux/ipq806x/patches-3.18/001-spi-qup-Add-DMA-capabilities.patch new file mode 100644 index 0000000..e110bf7 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/001-spi-qup-Add-DMA-capabilities.patch @@ -0,0 +1,522 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: spi: qup: Add DMA capabilities +From: Andy Gross +X-Patchwork-Id: 4432401 +Message-Id: <1403816781-31008-1-git-send-email-agross@codeaurora.org> +To: Mark Brown +Cc: linux-spi@vger.kernel.org, Sagar Dharia , + Daniel Sneddon , + Bjorn Andersson , + "Ivan T. Ivanov" , + linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + linux-arm-msm@vger.kernel.org, Andy Gross +Date: Thu, 26 Jun 2014 16:06:21 -0500 + +This patch adds DMA capabilities to the spi-qup driver. If DMA channels are +present, the QUP will use DMA instead of block mode for transfers to/from SPI +peripherals for transactions larger than the length of a block. + +Signed-off-by: Andy Gross + +--- +.../devicetree/bindings/spi/qcom,spi-qup.txt | 10 + + drivers/spi/spi-qup.c | 361 ++++++++++++++++++-- + 2 files changed, 350 insertions(+), 21 deletions(-) + +--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt ++++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +@@ -27,6 +27,11 @@ Optional properties: + - spi-max-frequency: Specifies maximum SPI clock frequency, + Units - Hz. Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt ++- dmas : Two DMA channel specifiers following the convention outlined ++ in bindings/dma/dma.txt ++- dma-names: Names for the dma channels, if present. There must be at ++ least one channel named "tx" for transmit and named "rx" for ++ receive. + - num-cs: total number of chipselects + - cs-gpios: should specify GPIOs used for chipselects. + The gpios will be referred to as reg = in the SPI child +@@ -51,6 +56,10 @@ Example: + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + ++ dmas = <&blsp2_bam 2>, ++ <&blsp2_bam 3>; ++ dma-names = "rx", "tx"; ++ + pinctrl-names = "default"; + pinctrl-0 = <&spi8_default>; + +--- a/drivers/spi/spi-qup.c ++++ b/drivers/spi/spi-qup.c +@@ -22,6 +22,8 @@ + #include + #include + #include ++#include ++#include + + #define QUP_CONFIG 0x0000 + #define QUP_STATE 0x0004 +@@ -116,6 +118,8 @@ + + #define SPI_NUM_CHIPSELECTS 4 + ++#define SPI_MAX_XFER (SZ_64K - 64) ++ + /* high speed mode is when bus rate is greater then 26MHz */ + #define SPI_HS_MIN_RATE 26000000 + #define SPI_MAX_RATE 50000000 +@@ -143,6 +147,17 @@ struct spi_qup { + int tx_bytes; + int rx_bytes; + int qup_v1; ++ ++ int use_dma; ++ ++ struct dma_chan *rx_chan; ++ struct dma_slave_config rx_conf; ++ struct dma_chan *tx_chan; ++ struct dma_slave_config tx_conf; ++ dma_addr_t rx_dma; ++ dma_addr_t tx_dma; ++ void *dummy; ++ atomic_t dma_outstanding; + }; + + +@@ -266,6 +281,221 @@ static void spi_qup_fifo_write(struct sp + } + } + ++static void qup_dma_callback(void *data) ++{ ++ struct spi_qup *controller = data; ++ ++ if (atomic_dec_and_test(&controller->dma_outstanding)) ++ complete(&controller->done); ++} ++ ++static int spi_qup_do_dma(struct spi_qup *controller, struct spi_transfer *xfer) ++{ ++ struct dma_async_tx_descriptor *rxd, *txd; ++ dma_cookie_t rx_cookie, tx_cookie; ++ u32 xfer_len, rx_align = 0, tx_align = 0, n_words; ++ struct scatterlist tx_sg[2], rx_sg[2]; ++ int ret = 0; ++ u32 bytes_to_xfer = xfer->len; ++ u32 offset = 0; ++ u32 rx_nents = 0, tx_nents = 0; ++ dma_addr_t rx_dma = 0, tx_dma = 0, rx_dummy_dma = 0, tx_dummy_dma = 0; ++ ++ ++ if (xfer->rx_buf) { ++ rx_dma = dma_map_single(controller->dev, xfer->rx_buf, ++ xfer->len, DMA_FROM_DEVICE); ++ ++ if (dma_mapping_error(controller->dev, rx_dma)) { ++ ret = -ENOMEM; ++ return ret; ++ } ++ ++ /* check to see if we need dummy buffer for leftover bytes */ ++ rx_align = xfer->len % controller->in_blk_sz; ++ if (rx_align) { ++ rx_dummy_dma = dma_map_single(controller->dev, ++ controller->dummy, controller->in_fifo_sz, ++ DMA_FROM_DEVICE); ++ ++ if (dma_mapping_error(controller->dev, rx_dummy_dma)) { ++ ret = -ENOMEM; ++ goto err_map_rx_dummy; ++ } ++ } ++ } ++ ++ if (xfer->tx_buf) { ++ tx_dma = dma_map_single(controller->dev, ++ (void *)xfer->tx_buf, xfer->len, DMA_TO_DEVICE); ++ ++ if (dma_mapping_error(controller->dev, tx_dma)) { ++ ret = -ENOMEM; ++ goto err_map_tx; ++ } ++ ++ /* check to see if we need dummy buffer for leftover bytes */ ++ tx_align = xfer->len % controller->out_blk_sz; ++ if (tx_align) { ++ memcpy(controller->dummy + SZ_1K, ++ xfer->tx_buf + xfer->len - tx_align, ++ tx_align); ++ memset(controller->dummy + SZ_1K + tx_align, 0, ++ controller->out_blk_sz - tx_align); ++ ++ tx_dummy_dma = dma_map_single(controller->dev, ++ controller->dummy + SZ_1K, ++ controller->out_blk_sz, DMA_TO_DEVICE); ++ ++ if (dma_mapping_error(controller->dev, tx_dummy_dma)) { ++ ret = -ENOMEM; ++ goto err_map_tx_dummy; ++ } ++ } ++ } ++ ++ atomic_set(&controller->dma_outstanding, 0); ++ ++ while (bytes_to_xfer > 0) { ++ xfer_len = min_t(u32, bytes_to_xfer, SPI_MAX_XFER); ++ n_words = DIV_ROUND_UP(xfer_len, controller->w_size); ++ ++ /* write out current word count to controller */ ++ writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); ++ writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); ++ ++ reinit_completion(&controller->done); ++ ++ if (xfer->tx_buf) { ++ /* recalc align for each transaction */ ++ tx_align = xfer_len % controller->out_blk_sz; ++ ++ if (tx_align) ++ tx_nents = 2; ++ else ++ tx_nents = 1; ++ ++ /* initialize scatterlists */ ++ sg_init_table(tx_sg, tx_nents); ++ sg_dma_len(&tx_sg[0]) = xfer_len - tx_align; ++ sg_dma_address(&tx_sg[0]) = tx_dma + offset; ++ ++ /* account for non block size transfer */ ++ if (tx_align) { ++ sg_dma_len(&tx_sg[1]) = controller->out_blk_sz; ++ sg_dma_address(&tx_sg[1]) = tx_dummy_dma; ++ } ++ ++ txd = dmaengine_prep_slave_sg(controller->tx_chan, ++ tx_sg, tx_nents, DMA_MEM_TO_DEV, 0); ++ if (!txd) { ++ ret = -ENOMEM; ++ goto err_unmap; ++ } ++ ++ atomic_inc(&controller->dma_outstanding); ++ ++ txd->callback = qup_dma_callback; ++ txd->callback_param = controller; ++ ++ tx_cookie = dmaengine_submit(txd); ++ ++ dma_async_issue_pending(controller->tx_chan); ++ } ++ ++ if (xfer->rx_buf) { ++ /* recalc align for each transaction */ ++ rx_align = xfer_len % controller->in_blk_sz; ++ ++ if (rx_align) ++ rx_nents = 2; ++ else ++ rx_nents = 1; ++ ++ /* initialize scatterlists */ ++ sg_init_table(rx_sg, rx_nents); ++ sg_dma_address(&rx_sg[0]) = rx_dma + offset; ++ sg_dma_len(&rx_sg[0]) = xfer_len - rx_align; ++ ++ /* account for non block size transfer */ ++ if (rx_align) { ++ sg_dma_len(&rx_sg[1]) = controller->in_blk_sz; ++ sg_dma_address(&rx_sg[1]) = rx_dummy_dma; ++ } ++ ++ rxd = dmaengine_prep_slave_sg(controller->rx_chan, ++ rx_sg, rx_nents, DMA_DEV_TO_MEM, 0); ++ if (!rxd) { ++ ret = -ENOMEM; ++ goto err_unmap; ++ } ++ ++ atomic_inc(&controller->dma_outstanding); ++ ++ rxd->callback = qup_dma_callback; ++ rxd->callback_param = controller; ++ ++ rx_cookie = dmaengine_submit(rxd); ++ ++ dma_async_issue_pending(controller->rx_chan); ++ } ++ ++ if (spi_qup_set_state(controller, QUP_STATE_RUN)) { ++ dev_warn(controller->dev, "cannot set EXECUTE state\n"); ++ goto err_unmap; ++ } ++ ++ if (!wait_for_completion_timeout(&controller->done, ++ msecs_to_jiffies(1000))) { ++ ret = -ETIMEDOUT; ++ ++ /* clear out all the DMA transactions */ ++ if (xfer->tx_buf) ++ dmaengine_terminate_all(controller->tx_chan); ++ if (xfer->rx_buf) ++ dmaengine_terminate_all(controller->rx_chan); ++ ++ goto err_unmap; ++ } ++ ++ if (rx_align) ++ memcpy(xfer->rx_buf + offset + xfer->len - rx_align, ++ controller->dummy, rx_align); ++ ++ /* adjust remaining bytes to transfer */ ++ bytes_to_xfer -= xfer_len; ++ offset += xfer_len; ++ ++ ++ /* reset mini-core state so we can program next transaction */ ++ if (spi_qup_set_state(controller, QUP_STATE_RESET)) { ++ dev_err(controller->dev, "cannot set RESET state\n"); ++ goto err_unmap; ++ } ++ } ++ ++ ret = 0; ++ ++err_unmap: ++ if (tx_align) ++ dma_unmap_single(controller->dev, tx_dummy_dma, ++ controller->out_fifo_sz, DMA_TO_DEVICE); ++err_map_tx_dummy: ++ if (xfer->tx_buf) ++ dma_unmap_single(controller->dev, tx_dma, xfer->len, ++ DMA_TO_DEVICE); ++err_map_tx: ++ if (rx_align) ++ dma_unmap_single(controller->dev, rx_dummy_dma, ++ controller->in_fifo_sz, DMA_FROM_DEVICE); ++err_map_rx_dummy: ++ if (xfer->rx_buf) ++ dma_unmap_single(controller->dev, rx_dma, xfer->len, ++ DMA_FROM_DEVICE); ++ ++ return ret; ++} ++ + static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) + { + struct spi_qup *controller = dev_id; +@@ -315,11 +545,13 @@ static irqreturn_t spi_qup_qup_irq(int i + error = -EIO; + } + +- if (opflags & QUP_OP_IN_SERVICE_FLAG) +- spi_qup_fifo_read(controller, xfer); ++ if (!controller->use_dma) { ++ if (opflags & QUP_OP_IN_SERVICE_FLAG) ++ spi_qup_fifo_read(controller, xfer); + +- if (opflags & QUP_OP_OUT_SERVICE_FLAG) +- spi_qup_fifo_write(controller, xfer); ++ if (opflags & QUP_OP_OUT_SERVICE_FLAG) ++ spi_qup_fifo_write(controller, xfer); ++ } + + spin_lock_irqsave(&controller->lock, flags); + controller->error = error; +@@ -339,6 +571,8 @@ static int spi_qup_io_config(struct spi_ + struct spi_qup *controller = spi_master_get_devdata(spi->master); + u32 config, iomode, mode; + int ret, n_words, w_size; ++ size_t dma_align = dma_get_cache_alignment(); ++ u32 dma_available = 0; + + if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { + dev_err(controller->dev, "too big size for loopback %d > %d\n", +@@ -367,6 +601,11 @@ static int spi_qup_io_config(struct spi_ + n_words = xfer->len / w_size; + controller->w_size = w_size; + ++ if (controller->rx_chan && ++ IS_ALIGNED((size_t)xfer->tx_buf, dma_align) && ++ IS_ALIGNED((size_t)xfer->rx_buf, dma_align)) ++ dma_available = 1; ++ + if (n_words <= (controller->in_fifo_sz / sizeof(u32))) { + mode = QUP_IO_M_MODE_FIFO; + writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); +@@ -374,19 +613,31 @@ static int spi_qup_io_config(struct spi_ + /* must be zero for FIFO */ + writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); + writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); +- } else { ++ controller->use_dma = 0; ++ } else if (!dma_available) { + mode = QUP_IO_M_MODE_BLOCK; + writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); + writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); + /* must be zero for BLOCK and BAM */ + writel_relaxed(0, controller->base + QUP_MX_READ_CNT); + writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); ++ controller->use_dma = 0; ++ } else { ++ mode = QUP_IO_M_MODE_DMOV; ++ writel_relaxed(0, controller->base + QUP_MX_READ_CNT); ++ writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); ++ controller->use_dma = 1; + } + + iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); + /* Set input and output transfer mode */ + iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK); +- iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); ++ ++ if (!controller->use_dma) ++ iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); ++ else ++ iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN; ++ + iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); + iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); + +@@ -419,6 +670,14 @@ static int spi_qup_io_config(struct spi_ + config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); + config |= xfer->bits_per_word - 1; + config |= QUP_CONFIG_SPI_MODE; ++ ++ if (controller->use_dma) { ++ if (!xfer->tx_buf) ++ config |= QUP_CONFIG_NO_OUTPUT; ++ if (!xfer->rx_buf) ++ config |= QUP_CONFIG_NO_INPUT; ++ } ++ + writel_relaxed(config, controller->base + QUP_CONFIG); + + /* only write to OPERATIONAL_MASK when register is present */ +@@ -452,25 +711,29 @@ static int spi_qup_transfer_one(struct s + controller->tx_bytes = 0; + spin_unlock_irqrestore(&controller->lock, flags); + +- if (spi_qup_set_state(controller, QUP_STATE_RUN)) { +- dev_warn(controller->dev, "cannot set RUN state\n"); +- goto exit; +- } ++ if (controller->use_dma) { ++ ret = spi_qup_do_dma(controller, xfer); ++ } else { ++ if (spi_qup_set_state(controller, QUP_STATE_RUN)) { ++ dev_warn(controller->dev, "cannot set RUN state\n"); ++ goto exit; ++ } + +- if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) { +- dev_warn(controller->dev, "cannot set PAUSE state\n"); +- goto exit; +- } ++ if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) { ++ dev_warn(controller->dev, "cannot set PAUSE state\n"); ++ goto exit; ++ } + +- spi_qup_fifo_write(controller, xfer); ++ spi_qup_fifo_write(controller, xfer); + +- if (spi_qup_set_state(controller, QUP_STATE_RUN)) { +- dev_warn(controller->dev, "cannot set EXECUTE state\n"); +- goto exit; +- } ++ if (spi_qup_set_state(controller, QUP_STATE_RUN)) { ++ dev_warn(controller->dev, "cannot set EXECUTE state\n"); ++ goto exit; ++ } + +- if (!wait_for_completion_timeout(&controller->done, timeout)) +- ret = -ETIMEDOUT; ++ if (!wait_for_completion_timeout(&controller->done, timeout)) ++ ret = -ETIMEDOUT; ++ } + exit: + spi_qup_set_state(controller, QUP_STATE_RESET); + spin_lock_irqsave(&controller->lock, flags); +@@ -554,6 +817,7 @@ static int spi_qup_probe(struct platform + master->transfer_one = spi_qup_transfer_one; + master->dev.of_node = pdev->dev.of_node; + master->auto_runtime_pm = true; ++ master->dma_alignment = dma_get_cache_alignment(); + + platform_set_drvdata(pdev, master); + +@@ -619,6 +883,56 @@ static int spi_qup_probe(struct platform + QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN, + base + QUP_ERROR_FLAGS_EN); + ++ /* allocate dma resources, if available */ ++ controller->rx_chan = dma_request_slave_channel(&pdev->dev, "rx"); ++ if (controller->rx_chan) { ++ controller->tx_chan = ++ dma_request_slave_channel(&pdev->dev, "tx"); ++ ++ if (!controller->tx_chan) { ++ dev_err(&pdev->dev, "Failed to allocate dma tx chan"); ++ dma_release_channel(controller->rx_chan); ++ } ++ ++ /* set DMA parameters */ ++ controller->rx_conf.device_fc = 1; ++ controller->rx_conf.src_addr = res->start + QUP_INPUT_FIFO; ++ controller->rx_conf.src_maxburst = controller->in_blk_sz; ++ ++ controller->tx_conf.device_fc = 1; ++ controller->tx_conf.dst_addr = res->start + QUP_OUTPUT_FIFO; ++ controller->tx_conf.dst_maxburst = controller->out_blk_sz; ++ ++ if (dmaengine_slave_config(controller->rx_chan, ++ &controller->rx_conf)) { ++ dev_err(&pdev->dev, "failed to configure RX channel\n"); ++ ++ dma_release_channel(controller->rx_chan); ++ dma_release_channel(controller->tx_chan); ++ controller->tx_chan = NULL; ++ controller->rx_chan = NULL; ++ } else if (dmaengine_slave_config(controller->tx_chan, ++ &controller->tx_conf)) { ++ dev_err(&pdev->dev, "failed to configure TX channel\n"); ++ ++ dma_release_channel(controller->rx_chan); ++ dma_release_channel(controller->tx_chan); ++ controller->tx_chan = NULL; ++ controller->rx_chan = NULL; ++ } ++ ++ controller->dummy = devm_kmalloc(controller->dev, PAGE_SIZE, ++ GFP_KERNEL); ++ ++ if (!controller->dummy) { ++ dma_release_channel(controller->rx_chan); ++ dma_release_channel(controller->tx_chan); ++ controller->tx_chan = NULL; ++ controller->rx_chan = NULL; ++ } ++ } ++ ++ + writel_relaxed(0, base + SPI_CONFIG); + writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); + +@@ -731,6 +1045,11 @@ static int spi_qup_remove(struct platfor + if (ret) + return ret; + ++ if (controller->rx_chan) ++ dma_release_channel(controller->rx_chan); ++ if (controller->tx_chan) ++ dma_release_channel(controller->tx_chan); ++ + clk_disable_unprepare(controller->cclk); + clk_disable_unprepare(controller->iclk); + diff --git a/target/linux/ipq806x/patches-3.18/002-v3-spi-qup-Fix-incorrect-block-transfers.patch b/target/linux/ipq806x/patches-3.18/002-v3-spi-qup-Fix-incorrect-block-transfers.patch new file mode 100644 index 0000000..62ee5b4 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/002-v3-spi-qup-Fix-incorrect-block-transfers.patch @@ -0,0 +1,376 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3] spi: qup: Fix incorrect block transfers +From: Andy Gross +X-Patchwork-Id: 5007321 +Message-Id: <1412112088-25928-1-git-send-email-agross@codeaurora.org> +To: Mark Brown +Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, + "Ivan T. Ivanov" , + Bjorn Andersson , + Kumar Gala , Andy Gross +Date: Tue, 30 Sep 2014 16:21:28 -0500 + +This patch fixes a number of errors with the QUP block transfer mode. Errors +manifested themselves as input underruns, output overruns, and timed out +transactions. + +The block mode does not require the priming that occurs in FIFO mode. At the +moment that the QUP is placed into the RUN state, the QUP will immediately raise +an interrupt if the request is a write. Therefore, there is no need to prime +the pump. + +In addition, the block transfers require that whole blocks of data are +read/written at a time. The last block of data that completes a transaction may +contain less than a full blocks worth of data. + +Each block of data results in an input/output service interrupt accompanied with +a input/output block flag set. Additional block reads/writes require clearing +of the service flag. It is ok to check for additional blocks of data in the +ISR, but you have to ack every block you transfer. Imbalanced acks result in +early return from complete transactions with pending interrupts that still have +to be ack'd. The next transaction can be affected by these interrupts. +Transactions are deemed complete when the MAX_INPUT or MAX_OUTPUT flag are set. + +Changes from v2: +- Added in additional completion check so that transaction done is not + prematurely signaled. +- Fixed various review comments. + +Changes from v1: +- Split out read/write block function. +- Removed extraneous checks for transfer length + +Signed-off-by: Andy Gross + +--- +drivers/spi/spi-qup.c | 201 ++++++++++++++++++++++++++++++++++++------------- + 1 file changed, 148 insertions(+), 53 deletions(-) + +--- a/drivers/spi/spi-qup.c ++++ b/drivers/spi/spi-qup.c +@@ -82,6 +82,8 @@ + #define QUP_IO_M_MODE_BAM 3 + + /* QUP_OPERATIONAL fields */ ++#define QUP_OP_IN_BLOCK_READ_REQ BIT(13) ++#define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12) + #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11) + #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10) + #define QUP_OP_IN_SERVICE_FLAG BIT(9) +@@ -147,6 +149,7 @@ struct spi_qup { + int tx_bytes; + int rx_bytes; + int qup_v1; ++ int mode; + + int use_dma; + +@@ -213,30 +216,14 @@ static int spi_qup_set_state(struct spi_ + return 0; + } + +- +-static void spi_qup_fifo_read(struct spi_qup *controller, +- struct spi_transfer *xfer) ++static void spi_qup_fill_read_buffer(struct spi_qup *controller, ++ struct spi_transfer *xfer, u32 data) + { + u8 *rx_buf = xfer->rx_buf; +- u32 word, state; +- int idx, shift, w_size; +- +- w_size = controller->w_size; +- +- while (controller->rx_bytes < xfer->len) { +- +- state = readl_relaxed(controller->base + QUP_OPERATIONAL); +- if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY)) +- break; +- +- word = readl_relaxed(controller->base + QUP_INPUT_FIFO); +- +- if (!rx_buf) { +- controller->rx_bytes += w_size; +- continue; +- } ++ int idx, shift; + +- for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) { ++ if (rx_buf) ++ for (idx = 0; idx < controller->w_size; idx++) { + /* + * The data format depends on bytes per SPI word: + * 4 bytes: 0x12345678 +@@ -244,41 +231,139 @@ static void spi_qup_fifo_read(struct spi + * 1 byte : 0x00000012 + */ + shift = BITS_PER_BYTE; +- shift *= (w_size - idx - 1); +- rx_buf[controller->rx_bytes] = word >> shift; ++ shift *= (controller->w_size - idx - 1); ++ rx_buf[controller->rx_bytes + idx] = data >> shift; ++ } ++ ++ controller->rx_bytes += controller->w_size; ++} ++ ++static void spi_qup_prepare_write_data(struct spi_qup *controller, ++ struct spi_transfer *xfer, u32 *data) ++{ ++ const u8 *tx_buf = xfer->tx_buf; ++ u32 val; ++ int idx; ++ ++ *data = 0; ++ ++ if (tx_buf) ++ for (idx = 0; idx < controller->w_size; idx++) { ++ val = tx_buf[controller->tx_bytes + idx]; ++ *data |= val << (BITS_PER_BYTE * (3 - idx)); + } ++ ++ controller->tx_bytes += controller->w_size; ++} ++ ++static void spi_qup_fifo_read(struct spi_qup *controller, ++ struct spi_transfer *xfer) ++{ ++ u32 data; ++ ++ /* clear service request */ ++ writel_relaxed(QUP_OP_IN_SERVICE_FLAG, ++ controller->base + QUP_OPERATIONAL); ++ ++ while (controller->rx_bytes < xfer->len) { ++ if (!(readl_relaxed(controller->base + QUP_OPERATIONAL) & ++ QUP_OP_IN_FIFO_NOT_EMPTY)) ++ break; ++ ++ data = readl_relaxed(controller->base + QUP_INPUT_FIFO); ++ ++ spi_qup_fill_read_buffer(controller, xfer, data); + } + } + + static void spi_qup_fifo_write(struct spi_qup *controller, +- struct spi_transfer *xfer) ++ struct spi_transfer *xfer) + { +- const u8 *tx_buf = xfer->tx_buf; +- u32 word, state, data; +- int idx, w_size; ++ u32 data; + +- w_size = controller->w_size; ++ /* clear service request */ ++ writel_relaxed(QUP_OP_OUT_SERVICE_FLAG, ++ controller->base + QUP_OPERATIONAL); + + while (controller->tx_bytes < xfer->len) { + +- state = readl_relaxed(controller->base + QUP_OPERATIONAL); +- if (state & QUP_OP_OUT_FIFO_FULL) ++ if (readl_relaxed(controller->base + QUP_OPERATIONAL) & ++ QUP_OP_OUT_FIFO_FULL) + break; + +- word = 0; +- for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) { ++ spi_qup_prepare_write_data(controller, xfer, &data); ++ writel_relaxed(data, controller->base + QUP_OUTPUT_FIFO); + +- if (!tx_buf) { +- controller->tx_bytes += w_size; +- break; +- } ++ } ++} + +- data = tx_buf[controller->tx_bytes]; +- word |= data << (BITS_PER_BYTE * (3 - idx)); +- } ++static void spi_qup_block_read(struct spi_qup *controller, ++ struct spi_transfer *xfer) ++{ ++ u32 data; ++ u32 reads_per_blk = controller->in_blk_sz >> 2; ++ u32 num_words = (xfer->len - controller->rx_bytes) / controller->w_size; ++ int i; ++ ++ do { ++ /* ACK by clearing service flag */ ++ writel_relaxed(QUP_OP_IN_SERVICE_FLAG, ++ controller->base + QUP_OPERATIONAL); ++ ++ /* transfer up to a block size of data in a single pass */ ++ for (i = 0; num_words && i < reads_per_blk; i++, num_words--) { ++ ++ /* read data and fill up rx buffer */ ++ data = readl_relaxed(controller->base + QUP_INPUT_FIFO); ++ spi_qup_fill_read_buffer(controller, xfer, data); ++ } ++ ++ /* check to see if next block is ready */ ++ if (!(readl_relaxed(controller->base + QUP_OPERATIONAL) & ++ QUP_OP_IN_BLOCK_READ_REQ)) ++ break; + +- writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); +- } ++ } while (num_words); ++ ++ /* ++ * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block ++ * reads, it has to be cleared again at the very end ++ */ ++ if (readl_relaxed(controller->base + QUP_OPERATIONAL) & ++ QUP_OP_MAX_INPUT_DONE_FLAG) ++ writel_relaxed(QUP_OP_IN_SERVICE_FLAG, ++ controller->base + QUP_OPERATIONAL); ++ ++} ++ ++static void spi_qup_block_write(struct spi_qup *controller, ++ struct spi_transfer *xfer) ++{ ++ u32 data; ++ u32 writes_per_blk = controller->out_blk_sz >> 2; ++ u32 num_words = (xfer->len - controller->tx_bytes) / controller->w_size; ++ int i; ++ ++ do { ++ /* ACK by clearing service flag */ ++ writel_relaxed(QUP_OP_OUT_SERVICE_FLAG, ++ controller->base + QUP_OPERATIONAL); ++ ++ /* transfer up to a block size of data in a single pass */ ++ for (i = 0; num_words && i < writes_per_blk; i++, num_words--) { ++ ++ /* swizzle the bytes for output and write out */ ++ spi_qup_prepare_write_data(controller, xfer, &data); ++ writel_relaxed(data, ++ controller->base + QUP_OUTPUT_FIFO); ++ } ++ ++ /* check to see if next block is ready */ ++ if (!(readl_relaxed(controller->base + QUP_OPERATIONAL) & ++ QUP_OP_OUT_BLOCK_WRITE_REQ)) ++ break; ++ ++ } while (num_words); + } + + static void qup_dma_callback(void *data) +@@ -515,9 +600,9 @@ static irqreturn_t spi_qup_qup_irq(int i + + writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); + writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); +- writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); + + if (!xfer) { ++ writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); + dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n", + qup_err, spi_err, opflags); + return IRQ_HANDLED; +@@ -546,11 +631,19 @@ static irqreturn_t spi_qup_qup_irq(int i + } + + if (!controller->use_dma) { +- if (opflags & QUP_OP_IN_SERVICE_FLAG) +- spi_qup_fifo_read(controller, xfer); ++ if (opflags & QUP_OP_IN_SERVICE_FLAG) { ++ if (opflags & QUP_OP_IN_BLOCK_READ_REQ) ++ spi_qup_block_read(controller, xfer); ++ else ++ spi_qup_fifo_read(controller, xfer); ++ } + +- if (opflags & QUP_OP_OUT_SERVICE_FLAG) +- spi_qup_fifo_write(controller, xfer); ++ if (opflags & QUP_OP_OUT_SERVICE_FLAG) { ++ if (opflags & QUP_OP_OUT_BLOCK_WRITE_REQ) ++ spi_qup_block_write(controller, xfer); ++ else ++ spi_qup_fifo_write(controller, xfer); ++ } + } + + spin_lock_irqsave(&controller->lock, flags); +@@ -558,7 +651,8 @@ static irqreturn_t spi_qup_qup_irq(int i + controller->xfer = xfer; + spin_unlock_irqrestore(&controller->lock, flags); + +- if (controller->rx_bytes == xfer->len || error) ++ if ((controller->rx_bytes == xfer->len && ++ (opflags & QUP_OP_MAX_INPUT_DONE_FLAG)) || error) + complete(&controller->done); + + return IRQ_HANDLED; +@@ -569,7 +663,7 @@ static irqreturn_t spi_qup_qup_irq(int i + static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) + { + struct spi_qup *controller = spi_master_get_devdata(spi->master); +- u32 config, iomode, mode; ++ u32 config, iomode; + int ret, n_words, w_size; + size_t dma_align = dma_get_cache_alignment(); + u32 dma_available = 0; +@@ -607,7 +701,7 @@ static int spi_qup_io_config(struct spi_ + dma_available = 1; + + if (n_words <= (controller->in_fifo_sz / sizeof(u32))) { +- mode = QUP_IO_M_MODE_FIFO; ++ controller->mode = QUP_IO_M_MODE_FIFO; + writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); + writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); + /* must be zero for FIFO */ +@@ -615,7 +709,7 @@ static int spi_qup_io_config(struct spi_ + writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); + controller->use_dma = 0; + } else if (!dma_available) { +- mode = QUP_IO_M_MODE_BLOCK; ++ controller->mode = QUP_IO_M_MODE_BLOCK; + writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); + writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); + /* must be zero for BLOCK and BAM */ +@@ -623,7 +717,7 @@ static int spi_qup_io_config(struct spi_ + writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); + controller->use_dma = 0; + } else { +- mode = QUP_IO_M_MODE_DMOV; ++ controller->mode = QUP_IO_M_MODE_DMOV; + writel_relaxed(0, controller->base + QUP_MX_READ_CNT); + writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); + controller->use_dma = 1; +@@ -638,8 +732,8 @@ static int spi_qup_io_config(struct spi_ + else + iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN; + +- iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); +- iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); ++ iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); ++ iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); + + writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); + +@@ -724,7 +818,8 @@ static int spi_qup_transfer_one(struct s + goto exit; + } + +- spi_qup_fifo_write(controller, xfer); ++ if (controller->mode == QUP_IO_M_MODE_FIFO) ++ spi_qup_fifo_write(controller, xfer); + + if (spi_qup_set_state(controller, QUP_STATE_RUN)) { + dev_warn(controller->dev, "cannot set EXECUTE state\n"); +@@ -741,6 +836,7 @@ exit: + if (!ret) + ret = controller->error; + spin_unlock_irqrestore(&controller->lock, flags); ++ + return ret; + } + diff --git a/target/linux/ipq806x/patches-3.18/003-spi-qup-Ensure-done-detection.patch b/target/linux/ipq806x/patches-3.18/003-spi-qup-Ensure-done-detection.patch new file mode 100644 index 0000000..7052227 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/003-spi-qup-Ensure-done-detection.patch @@ -0,0 +1,56 @@ +From 4faba89e3ffbb1c5f6232651375b9b3212b50f02 Mon Sep 17 00:00:00 2001 +From: Andy Gross +Date: Thu, 15 Jan 2015 17:56:02 -0800 +Subject: [PATCH] spi: qup: Ensure done detection + +This patch fixes an issue where a SPI transaction has completed, but the done +condition is missed. This occurs because at the time of interrupt the +MAX_INPUT_DONE_FLAG is not asserted. However, in the process of reading blocks +of data from the FIFO, the last portion of data comes in. + +The opflags read at the beginning of the irq handler no longer matches the +current opflag state. To get around this condition, the block read function +should update the opflags so that done detection is correct after the return. + +Change-Id: If109e0eeb432f96000d765c4b34dbb2269f8093f +Signed-off-by: Andy Gross +--- + drivers/spi/spi-qup.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +--- a/drivers/spi/spi-qup.c ++++ b/drivers/spi/spi-qup.c +@@ -298,7 +298,7 @@ static void spi_qup_fifo_write(struct sp + } + + static void spi_qup_block_read(struct spi_qup *controller, +- struct spi_transfer *xfer) ++ struct spi_transfer *xfer, u32 *opflags) + { + u32 data; + u32 reads_per_blk = controller->in_blk_sz >> 2; +@@ -327,10 +327,12 @@ static void spi_qup_block_read(struct sp + + /* + * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block +- * reads, it has to be cleared again at the very end ++ * reads, it has to be cleared again at the very end. However, be sure ++ * to refresh opflags value because MAX_INPUT_DONE_FLAG may now be ++ * present and this is used to determine if transaction is complete + */ +- if (readl_relaxed(controller->base + QUP_OPERATIONAL) & +- QUP_OP_MAX_INPUT_DONE_FLAG) ++ *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); ++ if (*opflags & QUP_OP_MAX_INPUT_DONE_FLAG) + writel_relaxed(QUP_OP_IN_SERVICE_FLAG, + controller->base + QUP_OPERATIONAL); + +@@ -633,7 +635,7 @@ static irqreturn_t spi_qup_qup_irq(int i + if (!controller->use_dma) { + if (opflags & QUP_OP_IN_SERVICE_FLAG) { + if (opflags & QUP_OP_IN_BLOCK_READ_REQ) +- spi_qup_block_read(controller, xfer); ++ spi_qup_block_read(controller, xfer, &opflags); + else + spi_qup_fifo_read(controller, xfer); + } diff --git a/target/linux/ipq806x/patches-3.18/011-watchdog-qcom-use-timer-devicetree-binding.patch b/target/linux/ipq806x/patches-3.18/011-watchdog-qcom-use-timer-devicetree-binding.patch new file mode 100644 index 0000000..68489a8 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/011-watchdog-qcom-use-timer-devicetree-binding.patch @@ -0,0 +1,67 @@ +From fded70251b1b58f68de1d3757ece9965f0b75452 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Thu, 19 Feb 2015 20:19:30 -0800 +Subject: [PATCH 1/3] watchdog: qcom: use timer devicetree binding + +MSM watchdog configuration happens in the same register block as the +timer, so we'll use the same binding as the existing timer. + +The qcom-wdt will now be probed when devicetree has an entry compatible +with "qcom,kpss-timer" or "qcom-scss-timer". + +Signed-off-by: Mathieu Olivari +--- + drivers/watchdog/qcom-wdt.c | 21 +++++++++++++++------ + 1 file changed, 15 insertions(+), 6 deletions(-) + +--- a/drivers/watchdog/qcom-wdt.c ++++ b/drivers/watchdog/qcom-wdt.c +@@ -20,9 +20,9 @@ + #include + #include + +-#define WDT_RST 0x0 +-#define WDT_EN 0x8 +-#define WDT_BITE_TIME 0x24 ++#define WDT_RST 0x38 ++#define WDT_EN 0x40 ++#define WDT_BITE_TIME 0x5C + + struct qcom_wdt { + struct watchdog_device wdd; +@@ -117,6 +117,8 @@ static int qcom_wdt_probe(struct platfor + { + struct qcom_wdt *wdt; + struct resource *res; ++ struct device_node *np = pdev->dev.of_node; ++ u32 percpu_offset; + int ret; + + wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); +@@ -124,6 +126,14 @@ static int qcom_wdt_probe(struct platfor + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ /* We use CPU0's DGT for the watchdog */ ++ if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) ++ percpu_offset = 0; ++ ++ res->start += percpu_offset; ++ res->end += percpu_offset; ++ + wdt->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(wdt->base)) + return PTR_ERR(wdt->base); +@@ -203,9 +213,8 @@ static int qcom_wdt_remove(struct platfo + } + + static const struct of_device_id qcom_wdt_of_table[] = { +- { .compatible = "qcom,kpss-wdt-msm8960", }, +- { .compatible = "qcom,kpss-wdt-apq8064", }, +- { .compatible = "qcom,kpss-wdt-ipq8064", }, ++ { .compatible = "qcom,kpss-timer" }, ++ { .compatible = "qcom,scss-timer" }, + { }, + }; + MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); diff --git a/target/linux/ipq806x/patches-3.18/012-ARM-qcom-add-description-of-KPSS-WDT-for-IPQ8064.patch b/target/linux/ipq806x/patches-3.18/012-ARM-qcom-add-description-of-KPSS-WDT-for-IPQ8064.patch new file mode 100644 index 0000000..ae96776 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/012-ARM-qcom-add-description-of-KPSS-WDT-for-IPQ8064.patch @@ -0,0 +1,48 @@ +From 297cf8136ecd6a56520888fd28948393766b8ee7 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Thu, 19 Feb 2015 20:27:39 -0800 +Subject: [PATCH 2/3] ARM: qcom: add description of KPSS WDT for IPQ8064 + +Add the watchdog related entries to the Krait Processor Sub-system +(KPSS) timer IPQ8064 devicetree section. Also, add a fixed-clock +description of SLEEP_CLK, which will do for now. + +Signed-off-by: Josh Cartwright +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -60,6 +60,14 @@ + }; + }; + ++ clocks { ++ sleep_clk: sleep_clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ #clock-cells = <0>; ++ }; ++ }; ++ + soc: soc { + #address-cells = <1>; + #size-cells = <1>; +@@ -89,10 +97,14 @@ + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, +- <1 3 0x301>; ++ <1 3 0x301>, ++ <1 4 0x301>, ++ <1 5 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <25000000>, + <32768>; ++ clocks = <&sleep_clk>; ++ clock-names = "sleep"; + cpu-offset = <0x80000>; + }; + diff --git a/target/linux/ipq806x/patches-3.18/013-ARM-msm-add-watchdog-entries-to-DT-timer-binding-doc.patch b/target/linux/ipq806x/patches-3.18/013-ARM-msm-add-watchdog-entries-to-DT-timer-binding-doc.patch new file mode 100644 index 0000000..6876768 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/013-ARM-msm-add-watchdog-entries-to-DT-timer-binding-doc.patch @@ -0,0 +1,50 @@ +From e535f01dffb6dd9e09934fa219be52af3437a8f6 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Thu, 19 Feb 2015 20:36:27 -0800 +Subject: [PATCH 3/3] ARM: msm: add watchdog entries to DT timer binding doc + +The watchdog has been reworked to use the same DT node as the timer. +This change is updating the device tree doc accordingly. + +Signed-off-by: Mathieu Olivari +--- + Documentation/devicetree/bindings/arm/msm/timer.txt | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +--- a/Documentation/devicetree/bindings/arm/msm/timer.txt ++++ b/Documentation/devicetree/bindings/arm/msm/timer.txt +@@ -9,11 +9,17 @@ Properties: + "qcom,scss-timer" - scorpion subsystem + + - interrupts : Interrupts for the the debug timer, the first general purpose +- timer, and optionally a second general purpose timer in that +- order. ++ timer, and optionally a second general purpose timer, and ++ optionally as well, 2 watchdog interrupts, in that order. + + - reg : Specifies the base address of the timer registers. + ++- clocks: Reference to the parent clocks, one per output clock. The parents ++ must appear in the same order as the clock names. ++ ++- clock-names: The name of the clocks as free-form strings. They should be in ++ the same order as the clocks. ++ + - clock-frequency : The frequency of the debug timer and the general purpose + timer(s) in Hz in that order. + +@@ -29,9 +35,13 @@ Example: + compatible = "qcom,scss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, +- <1 3 0x301>; ++ <1 3 0x301>, ++ <1 4 0x301>, ++ <1 5 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <19200000>, + <32768>; ++ clocks = <&sleep_clk>; ++ clock-names = "sleep"; + cpu-offset = <0x40000>; + }; diff --git a/target/linux/ipq806x/patches-3.18/020-add-ap148-bootargs.patch b/target/linux/ipq806x/patches-3.18/020-add-ap148-bootargs.patch new file mode 100644 index 0000000..a61481e --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/020-add-ap148-bootargs.patch @@ -0,0 +1,46 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -14,6 +14,14 @@ + }; + }; + ++ alias { ++ serial0 = &uart4; ++ }; ++ ++ chosen { ++ linux,stdout-path = "serial0:115200n8"; ++ }; ++ + soc { + pinmux@800000 { + i2c4_pins: i2c4_pinmux { +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -140,7 +140,7 @@ + ranges; + status = "disabled"; + +- serial@12490000 { ++ uart2: serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, + <0x12480000 0x1000>; +@@ -175,7 +175,7 @@ + ranges; + status = "disabled"; + +- serial@16340000 { ++ uart4: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; +@@ -209,7 +209,7 @@ + ranges; + status = "disabled"; + +- serial@1a240000 { ++ uart5: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, + <0x1a200000 0x1000>; diff --git a/target/linux/ipq806x/patches-3.18/021-add-ap148-partitions.patch b/target/linux/ipq806x/patches-3.18/021-add-ap148-partitions.patch new file mode 100644 index 0000000..bfdb30f --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/021-add-ap148-partitions.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -77,15 +77,7 @@ + spi-max-frequency = <50000000>; + reg = <0>; + +- partition@0 { +- label = "rootfs"; +- reg = <0x0 0x1000000>; +- }; +- +- partition@1 { +- label = "scratch"; +- reg = <0x1000000 0x1000000>; +- }; ++ linux,part-probe = "qcom-smem"; + }; + }; + }; diff --git a/target/linux/ipq806x/patches-3.18/022-add-db149-dts.patch b/target/linux/ipq806x/patches-3.18/022-add-db149-dts.patch new file mode 100644 index 0000000..bd6ec1e --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/022-add-db149-dts.patch @@ -0,0 +1,160 @@ +From a32d6e7c8fca6371a2614924b89981bc912b6378 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Tue, 7 Apr 2015 19:58:58 -0700 +Subject: [PATCH] ARM: dts: qcom: add initial DB149 device-tree + +Add basic DB149 (IPQ806x based platform) device-tree. It supports UART, +SATA, USB2, USB3 and NOR flash. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/qcom-ipq8064-db149.dts | 257 +++++++++++++++++++++++++++++++ + 2 files changed, 258 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-db149.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -360,6 +360,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8084-ifc6540.dtb \ + qcom-apq8084-mtp.dtb \ + qcom-ipq8064-ap148.dtb \ ++ qcom-ipq8064-db149.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb \ + qcom-msm8974-sony-xperia-honami.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts +@@ -0,0 +1,132 @@ ++#include "qcom-ipq8064-v1.0.dtsi" ++ ++/ { ++ model = "Qualcomm IPQ8064/DB149"; ++ compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ rsvd@41200000 { ++ reg = <0x41200000 0x300000>; ++ no-map; ++ }; ++ }; ++ ++ alias { ++ serial0 = &uart2; ++ }; ++ ++ chosen { ++ linux,stdout-path = "serial0:115200n8"; ++ }; ++ ++ soc { ++ pinmux@800000 { ++ i2c4_pins: i2c4_pinmux { ++ pins = "gpio12", "gpio13"; ++ function = "gsbi4"; ++ bias-disable; ++ }; ++ ++ spi_pins: spi_pins { ++ mux { ++ pins = "gpio18", "gpio19", "gpio21"; ++ function = "gsbi5"; ++ drive-strength = <10>; ++ bias-none; ++ }; ++ }; ++ }; ++ ++ gsbi2: gsbi@12480000 { ++ qcom,mode = ; ++ status = "ok"; ++ uart2: serial@12490000 { ++ status = "ok"; ++ }; ++ }; ++ ++ gsbi5: gsbi@1a200000 { ++ qcom,mode = ; ++ status = "ok"; ++ ++ spi4: spi@1a280000 { ++ status = "ok"; ++ spi-max-frequency = <50000000>; ++ ++ pinctrl-0 = <&spi_pins>; ++ pinctrl-names = "default"; ++ ++ cs-gpios = <&qcom_pinmux 20 0>; ++ ++ flash: m25p80@0 { ++ compatible = "s25fl256s1"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ spi-max-frequency = <50000000>; ++ reg = <0>; ++ m25p,fast-read; ++ ++ partition@0 { ++ label = "lowlevel_init"; ++ reg = <0x0 0x1b0000>; ++ }; ++ ++ partition@1 { ++ label = "u-boot"; ++ reg = <0x1b0000 0x80000>; ++ }; ++ ++ partition@2 { ++ label = "u-boot-env"; ++ reg = <0x230000 0x40000>; ++ }; ++ ++ partition@3 { ++ label = "caldata"; ++ reg = <0x270000 0x40000>; ++ }; ++ ++ partition@4 { ++ label = "firmware"; ++ reg = <0x2b0000 0x1d50000>; ++ }; ++ }; ++ }; ++ }; ++ ++ sata-phy@1b400000 { ++ status = "ok"; ++ }; ++ ++ sata@29000000 { ++ status = "ok"; ++ }; ++ ++ phy@100f8800 { /* USB3 port 1 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@100f8830 { /* USB3 port 1 SS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8800 { /* USB3 port 0 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8830 { /* USB3 port 0 SS phy */ ++ status = "ok"; ++ }; ++ ++ usb30@0 { ++ status = "ok"; ++ }; ++ ++ usb30@1 { ++ status = "ok"; ++ }; ++ }; ++}; diff --git a/target/linux/ipq806x/patches-3.18/023-ARM-dts-ipq806x-Disable-i2c-device-on-gsbi4.patch b/target/linux/ipq806x/patches-3.18/023-ARM-dts-ipq806x-Disable-i2c-device-on-gsbi4.patch new file mode 100644 index 0000000..319859b --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/023-ARM-dts-ipq806x-Disable-i2c-device-on-gsbi4.patch @@ -0,0 +1,53 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -46,15 +46,12 @@ + serial@16340000 { + status = "ok"; + }; +- +- i2c4: i2c@16380000 { +- status = "ok"; +- +- clock-frequency = <200000>; +- +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-names = "default"; +- }; ++ /* ++ * The i2c device on gsbi4 should not be enabled. ++ * On ipq806x designs gsbi4 i2c is meant for exclusive ++ * RPM usage. Turning this on in kernel manifests as ++ * i2c failure for the RPM. ++ */ + }; + + gsbi5: gsbi@1a200000 { +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -794,7 +794,7 @@ static struct clk_rcg gsbi7_qup_src = { + .parent_names = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, +- .flags = CLK_SET_PARENT_GATE, ++ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -810,7 +810,7 @@ static struct clk_branch gsbi7_qup_clk = + .parent_names = (const char *[]){ "gsbi7_qup_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -858,7 +858,7 @@ static struct clk_branch gsbi4_h_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_h_clk", + .ops = &clk_branch_ops, +- .flags = CLK_IS_ROOT, ++ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED, + }, + }, + }; diff --git a/target/linux/ipq806x/patches-3.18/024-ap148-add-memory-node.patch b/target/linux/ipq806x/patches-3.18/024-ap148-add-memory-node.patch new file mode 100644 index 0000000..f026ed9 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/024-ap148-add-memory-node.patch @@ -0,0 +1,14 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -4,6 +4,11 @@ + model = "Qualcomm IPQ8064/AP148"; + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + ++ memory@0 { ++ reg = <0x42000000 0x1e000000>; ++ device_type = "memory"; ++ }; ++ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; diff --git a/target/linux/ipq806x/patches-3.18/030-hwspinlock-core-add-device-tree-support.patch b/target/linux/ipq806x/patches-3.18/030-hwspinlock-core-add-device-tree-support.patch new file mode 100644 index 0000000..04f35b7 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/030-hwspinlock-core-add-device-tree-support.patch @@ -0,0 +1,167 @@ +From fb7737e949e31d8a71acee6bbb670f32dbd2a2c0 Mon Sep 17 00:00:00 2001 +From: Suman Anna +Date: Wed, 4 Mar 2015 20:01:14 -0600 +Subject: [PATCH] hwspinlock/core: add device tree support + +This patch adds a new OF-friendly API of_hwspin_lock_get_id() +for hwspinlock clients to use/request locks from a hwspinlock +device instantiated through a device-tree blob. This new API +can be used by hwspinlock clients to get the id for a specific +lock using the phandle + args specifier, so that it can be +requested using the available hwspin_lock_request_specific() +API. + +Signed-off-by: Suman Anna +Reviewed-by: Bjorn Andersson +[small comment clarification] +Signed-off-by: Ohad Ben-Cohen +--- + Documentation/hwspinlock.txt | 10 +++++ + drivers/hwspinlock/hwspinlock_core.c | 79 ++++++++++++++++++++++++++++++++++++ + include/linux/hwspinlock.h | 7 ++++ + 3 files changed, 96 insertions(+) + +--- a/Documentation/hwspinlock.txt ++++ b/Documentation/hwspinlock.txt +@@ -48,6 +48,16 @@ independent, drivers. + ids for predefined purposes. + Should be called from a process context (might sleep). + ++ int of_hwspin_lock_get_id(struct device_node *np, int index); ++ - retrieve the global lock id for an OF phandle-based specific lock. ++ This function provides a means for DT users of a hwspinlock module ++ to get the global lock id of a specific hwspinlock, so that it can ++ be requested using the normal hwspin_lock_request_specific() API. ++ The function returns a lock id number on success, -EPROBE_DEFER if ++ the hwspinlock device is not yet registered with the core, or other ++ error values. ++ Should be called from a process context (might sleep). ++ + int hwspin_lock_free(struct hwspinlock *hwlock); + - free a previously-assigned hwspinlock; returns 0 on success, or an + appropriate error code on failure (e.g. -EINVAL if the hwspinlock +--- a/drivers/hwspinlock/hwspinlock_core.c ++++ b/drivers/hwspinlock/hwspinlock_core.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include "hwspinlock_internal.h" + +@@ -257,6 +258,84 @@ void __hwspin_unlock(struct hwspinlock * + } + EXPORT_SYMBOL_GPL(__hwspin_unlock); + ++/** ++ * of_hwspin_lock_simple_xlate - translate hwlock_spec to return a lock id ++ * @bank: the hwspinlock device bank ++ * @hwlock_spec: hwlock specifier as found in the device tree ++ * ++ * This is a simple translation function, suitable for hwspinlock platform ++ * drivers that only has a lock specifier length of 1. ++ * ++ * Returns a relative index of the lock within a specified bank on success, ++ * or -EINVAL on invalid specifier cell count. ++ */ ++static inline int ++of_hwspin_lock_simple_xlate(const struct of_phandle_args *hwlock_spec) ++{ ++ if (WARN_ON(hwlock_spec->args_count != 1)) ++ return -EINVAL; ++ ++ return hwlock_spec->args[0]; ++} ++ ++/** ++ * of_hwspin_lock_get_id() - get lock id for an OF phandle-based specific lock ++ * @np: device node from which to request the specific hwlock ++ * @index: index of the hwlock in the list of values ++ * ++ * This function provides a means for DT users of the hwspinlock module to ++ * get the global lock id of a specific hwspinlock using the phandle of the ++ * hwspinlock device, so that it can be requested using the normal ++ * hwspin_lock_request_specific() API. ++ * ++ * Returns the global lock id number on success, -EPROBE_DEFER if the hwspinlock ++ * device is not yet registered, -EINVAL on invalid args specifier value or an ++ * appropriate error as returned from the OF parsing of the DT client node. ++ */ ++int of_hwspin_lock_get_id(struct device_node *np, int index) ++{ ++ struct of_phandle_args args; ++ struct hwspinlock *hwlock; ++ struct radix_tree_iter iter; ++ void **slot; ++ int id; ++ int ret; ++ ++ ret = of_parse_phandle_with_args(np, "hwlocks", "#hwlock-cells", index, ++ &args); ++ if (ret) ++ return ret; ++ ++ /* Find the hwspinlock device: we need its base_id */ ++ ret = -EPROBE_DEFER; ++ rcu_read_lock(); ++ radix_tree_for_each_slot(slot, &hwspinlock_tree, &iter, 0) { ++ hwlock = radix_tree_deref_slot(slot); ++ if (unlikely(!hwlock)) ++ continue; ++ ++ if (hwlock->bank->dev->of_node == args.np) { ++ ret = 0; ++ break; ++ } ++ } ++ rcu_read_unlock(); ++ if (ret < 0) ++ goto out; ++ ++ id = of_hwspin_lock_simple_xlate(&args); ++ if (id < 0 || id >= hwlock->bank->num_locks) { ++ ret = -EINVAL; ++ goto out; ++ } ++ id += hwlock->bank->base_id; ++ ++out: ++ of_node_put(args.np); ++ return ret ? ret : id; ++} ++EXPORT_SYMBOL_GPL(of_hwspin_lock_get_id); ++ + static int hwspin_lock_register_single(struct hwspinlock *hwlock, int id) + { + struct hwspinlock *tmp; +--- a/include/linux/hwspinlock.h ++++ b/include/linux/hwspinlock.h +@@ -26,6 +26,7 @@ + #define HWLOCK_IRQ 0x02 /* Disable interrupts, don't save state */ + + struct device; ++struct device_node; + struct hwspinlock; + struct hwspinlock_device; + struct hwspinlock_ops; +@@ -66,6 +67,7 @@ int hwspin_lock_unregister(struct hwspin + struct hwspinlock *hwspin_lock_request(void); + struct hwspinlock *hwspin_lock_request_specific(unsigned int id); + int hwspin_lock_free(struct hwspinlock *hwlock); ++int of_hwspin_lock_get_id(struct device_node *np, int index); + int hwspin_lock_get_id(struct hwspinlock *hwlock); + int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int, + unsigned long *); +@@ -120,6 +122,11 @@ void __hwspin_unlock(struct hwspinlock * + { + } + ++static inline int of_hwspin_lock_get_id(struct device_node *np, int index) ++{ ++ return 0; ++} ++ + static inline int hwspin_lock_get_id(struct hwspinlock *hwlock) + { + return 0; diff --git a/target/linux/ipq806x/patches-3.18/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch b/target/linux/ipq806x/patches-3.18/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch new file mode 100644 index 0000000..581b199 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch @@ -0,0 +1,234 @@ +From 19a0f61224d2d91860fa8291ab63cb104ee86bdd Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Tue, 24 Mar 2015 10:11:05 -0700 +Subject: [PATCH] hwspinlock: qcom: Add support for Qualcomm HW Mutex block + +Add driver for Qualcomm Hardware Mutex block found in many Qualcomm +SoCs. + +Based on initial effort by Kumar Gala + +Signed-off-by: Bjorn Andersson +Reviewed-by: Andy Gross +Reviewed-by: Jeffrey Hugo +Signed-off-by: Ohad Ben-Cohen +--- + drivers/hwspinlock/Kconfig | 12 +++ + drivers/hwspinlock/Makefile | 1 + + drivers/hwspinlock/qcom_hwspinlock.c | 181 +++++++++++++++++++++++++++++++++++ + 3 files changed, 194 insertions(+) + create mode 100644 drivers/hwspinlock/qcom_hwspinlock.c + +--- a/drivers/hwspinlock/Kconfig ++++ b/drivers/hwspinlock/Kconfig +@@ -18,6 +18,18 @@ config HWSPINLOCK_OMAP + + If unsure, say N. + ++config HWSPINLOCK_QCOM ++ tristate "Qualcomm Hardware Spinlock device" ++ depends on ARCH_QCOM ++ select HWSPINLOCK ++ select MFD_SYSCON ++ help ++ Say y here to support the Qualcomm Hardware Mutex functionality, which ++ provides a synchronisation mechanism for the various processors on ++ the SoC. ++ ++ If unsure, say N. ++ + config HSEM_U8500 + tristate "STE Hardware Semaphore functionality" + depends on ARCH_U8500 +--- a/drivers/hwspinlock/Makefile ++++ b/drivers/hwspinlock/Makefile +@@ -4,4 +4,5 @@ + + obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o + obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o ++obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o + obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o +--- /dev/null ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -0,0 +1,181 @@ ++/* ++ * Copyright (c) 2013, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2015, Sony Mobile Communications AB ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "hwspinlock_internal.h" ++ ++#define QCOM_MUTEX_APPS_PROC_ID 1 ++#define QCOM_MUTEX_NUM_LOCKS 32 ++ ++static int qcom_hwspinlock_trylock(struct hwspinlock *lock) ++{ ++ struct regmap_field *field = lock->priv; ++ u32 lock_owner; ++ int ret; ++ ++ ret = regmap_field_write(field, QCOM_MUTEX_APPS_PROC_ID); ++ if (ret) ++ return ret; ++ ++ ret = regmap_field_read(field, &lock_owner); ++ if (ret) ++ return ret; ++ ++ return lock_owner == QCOM_MUTEX_APPS_PROC_ID; ++} ++ ++static void qcom_hwspinlock_unlock(struct hwspinlock *lock) ++{ ++ struct regmap_field *field = lock->priv; ++ u32 lock_owner; ++ int ret; ++ ++ ret = regmap_field_read(field, &lock_owner); ++ if (ret) { ++ pr_err("%s: unable to query spinlock owner\n", __func__); ++ return; ++ } ++ ++ if (lock_owner != QCOM_MUTEX_APPS_PROC_ID) { ++ pr_err("%s: spinlock not owned by us (actual owner is %d)\n", ++ __func__, lock_owner); ++ } ++ ++ ret = regmap_field_write(field, 0); ++ if (ret) ++ pr_err("%s: failed to unlock spinlock\n", __func__); ++} ++ ++static const struct hwspinlock_ops qcom_hwspinlock_ops = { ++ .trylock = qcom_hwspinlock_trylock, ++ .unlock = qcom_hwspinlock_unlock, ++}; ++ ++static const struct of_device_id qcom_hwspinlock_of_match[] = { ++ { .compatible = "qcom,sfpb-mutex" }, ++ { .compatible = "qcom,tcsr-mutex" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); ++ ++static int qcom_hwspinlock_probe(struct platform_device *pdev) ++{ ++ struct hwspinlock_device *bank; ++ struct device_node *syscon; ++ struct reg_field field; ++ struct regmap *regmap; ++ size_t array_size; ++ u32 stride; ++ u32 base; ++ int ret; ++ int i; ++ ++ syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0); ++ if (!syscon) { ++ dev_err(&pdev->dev, "no syscon property\n"); ++ return -ENODEV; ++ } ++ ++ regmap = syscon_node_to_regmap(syscon); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no offset in syscon\n"); ++ return -EINVAL; ++ } ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no stride syscon\n"); ++ return -EINVAL; ++ } ++ ++ array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); ++ bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL); ++ if (!bank) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, bank); ++ ++ for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { ++ field.reg = base + i * stride; ++ field.lsb = 0; ++ field.msb = 32; ++ ++ bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, ++ regmap, field); ++ } ++ ++ pm_runtime_enable(&pdev->dev); ++ ++ ret = hwspin_lock_register(bank, &pdev->dev, &qcom_hwspinlock_ops, ++ 0, QCOM_MUTEX_NUM_LOCKS); ++ if (ret) ++ pm_runtime_disable(&pdev->dev); ++ ++ return ret; ++} ++ ++static int qcom_hwspinlock_remove(struct platform_device *pdev) ++{ ++ struct hwspinlock_device *bank = platform_get_drvdata(pdev); ++ int ret; ++ ++ ret = hwspin_lock_unregister(bank); ++ if (ret) { ++ dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static struct platform_driver qcom_hwspinlock_driver = { ++ .probe = qcom_hwspinlock_probe, ++ .remove = qcom_hwspinlock_remove, ++ .driver = { ++ .name = "qcom_hwspinlock", ++ .of_match_table = qcom_hwspinlock_of_match, ++ }, ++}; ++ ++static int __init qcom_hwspinlock_init(void) ++{ ++ return platform_driver_register(&qcom_hwspinlock_driver); ++} ++/* board init code might need to reserve hwspinlocks for predefined purposes */ ++postcore_initcall(qcom_hwspinlock_init); ++ ++static void __exit qcom_hwspinlock_exit(void) ++{ ++ platform_driver_unregister(&qcom_hwspinlock_driver); ++} ++module_exit(qcom_hwspinlock_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Hardware spinlock driver for Qualcomm SoCs"); diff --git a/target/linux/ipq806x/patches-3.18/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch b/target/linux/ipq806x/patches-3.18/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch new file mode 100644 index 0000000..70d5a58 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch @@ -0,0 +1,26 @@ +From bd5717a4632cdecafe82d03de7dcb3b1876e2828 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Fri, 26 Jun 2015 14:47:21 -0700 +Subject: [PATCH] hwspinlock: qcom: Correct msb in regmap_field + +msb of the regmap_field was mistakenly given the value 32, to set all bits +in the regmap update mask; although incorrect this worked until 921cc294, +where the mask calculation was corrected. + +Signed-off-by: Bjorn Andersson +Signed-off-by: Ohad Ben-Cohen +--- + drivers/hwspinlock/qcom_hwspinlock.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwspinlock/qcom_hwspinlock.c ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -123,7 +123,7 @@ static int qcom_hwspinlock_probe(struct + for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { + field.reg = base + i * stride; + field.lsb = 0; +- field.msb = 32; ++ field.msb = 31; + + bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, + regmap, field); diff --git a/target/linux/ipq806x/patches-3.18/033-ARM-qcom-add-SFPB-nodes-to-IPQ806x-dts.patch b/target/linux/ipq806x/patches-3.18/033-ARM-qcom-add-SFPB-nodes-to-IPQ806x-dts.patch new file mode 100644 index 0000000..4a35325 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/033-ARM-qcom-add-SFPB-nodes-to-IPQ806x-dts.patch @@ -0,0 +1,34 @@ +From c7c482da19a5e4ba7101198c21c2434056b0b2da Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Thu, 13 Aug 2015 09:45:26 -0700 +Subject: [PATCH 1/3] ARM: qcom: add SFPB nodes to IPQ806x dts + +Add one new node to the ipq806x.dtsi file to declare & register the +hardware spinlock devices. This mechanism is required to be used by +other drivers such as SMEM. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -291,5 +291,17 @@ + #clock-cells = <1>; + #reset-cells = <1>; + }; ++ ++ sfpb_mutex_block: syscon@1200600 { ++ compatible = "syscon"; ++ reg = <0x01200600 0x100>; ++ }; + }; ++ ++ sfpb_mutex: sfpb-mutex { ++ compatible = "qcom,sfpb-mutex"; ++ syscon = <&sfpb_mutex_block 4 4>; ++ ++ #hwlock-cells = <1>; ++ }; + }; diff --git a/target/linux/ipq806x/patches-3.18/034-soc-qcom-Add-device-tree-binding-for-SMEM.patch b/target/linux/ipq806x/patches-3.18/034-soc-qcom-Add-device-tree-binding-for-SMEM.patch new file mode 100644 index 0000000..d22db22 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/034-soc-qcom-Add-device-tree-binding-for-SMEM.patch @@ -0,0 +1,82 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,1/2] soc: qcom: Add device tree binding for SMEM +From: Bjorn Andersson +X-Patchwork-Id: 6202201 +Message-Id: <1428795178-24312-1-git-send-email-bjorn.andersson@sonymobile.com> +To: Rob Herring , Pawel Moll , + Mark Rutland , + Ian Campbell , + Kumar Gala , Jeffrey Hugo , + Andry Gross +Cc: , + linux-arm-msm , + +Date: Sat, 11 Apr 2015 16:32:57 -0700 + +Add device tree binding documentation for the Qualcom Shared Memory +manager. + +Signed-off-by: Bjorn Andersson + +--- +Changes since v1: +- None + + .../devicetree/bindings/soc/qcom/qcom,smem.txt | 49 ++++++++++++++++++++++ + 1 file changed, 49 insertions(+) + create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt +@@ -0,0 +1,49 @@ ++Qualcomm Shared Memory binding ++ ++This binding describes the Qualcomm Shared Memory, used to share data between ++various subsystems and OSes in Qualcomm platforms. ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: must be: ++ "qcom,smem" ++ ++- memory-region: ++ Usage: required ++ Value type: ++ Definition: handle to memory reservation for main smem memory region. ++ ++- reg: ++ Usage: optional ++ Value type: ++ Definition: base address and size pair for any additional memory areas ++ of the shared memory. ++ ++- hwspinlocks: ++ Usage: required ++ Value type: ++ Definition: reference to a hwspinlock used to protect allocations from ++ the shared memory ++ ++= EXAMPLE ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ smem_region: smem@fa00000 { ++ reg = <0xfa00000 0x200000>; ++ no-map; ++ }; ++ }; ++ ++ smem@fa00000 { ++ compatible = "qcom,smem"; ++ ++ memory-region = <&smem_region>; ++ reg = <0xfc428000 0x4000>; ++ ++ hwlocks = <&tcsr_mutex 3>; ++ }; diff --git a/target/linux/ipq806x/patches-3.18/035-soc-qcom-Add-Shared-Memory-Manager-driver.patch b/target/linux/ipq806x/patches-3.18/035-soc-qcom-Add-Shared-Memory-Manager-driver.patch new file mode 100644 index 0000000..c8cff1a --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/035-soc-qcom-Add-Shared-Memory-Manager-driver.patch @@ -0,0 +1,841 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,2/2] soc: qcom: Add Shared Memory Manager driver +From: Bjorn Andersson +X-Patchwork-Id: 6202211 +Message-Id: <1428795178-24312-2-git-send-email-bjorn.andersson@sonymobile.com> +To: Kumar Gala , Andy Gross , + David Brown , Jeffrey Hugo +Cc: , , + +Date: Sat, 11 Apr 2015 16:32:58 -0700 + +The Shared Memory Manager driver implements an interface for allocating +and accessing items in the memory area shared among all of the +processors in a Qualcomm platform. + +Signed-off-by: Bjorn Andersson +Reviewed-by: Andy Gross +Tested-by: Andy Gross + +--- +Changes since v1: +- ioremapping the regions nocache +- improved documentation of the two regions of partitions +- corrected free space check in private allocator + + drivers/soc/qcom/Kconfig | 7 + + drivers/soc/qcom/Makefile | 1 + + drivers/soc/qcom/smem.c | 768 ++++++++++++++++++++++++++++++++++++++++++ + include/linux/soc/qcom/smem.h | 14 + + 4 files changed, 790 insertions(+) + create mode 100644 drivers/soc/qcom/smem.c + create mode 100644 include/linux/soc/qcom/smem.h + +--- a/drivers/soc/qcom/Kconfig ++++ b/drivers/soc/qcom/Kconfig +@@ -9,3 +9,10 @@ config QCOM_GSBI + functions for connecting the underlying serial UART, SPI, and I2C + devices to the output pins. + ++config QCOM_SMEM ++ tristate "Qualcomm Shared Memory Manager (SMEM)" ++ depends on ARCH_QCOM ++ help ++ Say y here to enable support for the Qualcomm Shared Memory Manager. ++ The driver provides an interface to items in a heap shared among all ++ processors in a Qualcomm platform. +--- a/drivers/soc/qcom/Makefile ++++ b/drivers/soc/qcom/Makefile +@@ -1 +1,2 @@ + obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o ++obj-$(CONFIG_QCOM_SMEM) += smem.o +--- /dev/null ++++ b/drivers/soc/qcom/smem.c +@@ -0,0 +1,768 @@ ++/* ++ * Copyright (c) 2015, Sony Mobile Communications AB. ++ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * The Qualcomm shared memory system is a allocate only heap structure that ++ * consists of one of more memory areas that can be accessed by the processors ++ * in the SoC. ++ * ++ * All systems contains a global heap, accessible by all processors in the SoC, ++ * with a table of contents data structure (@smem_header) at the beginning of ++ * the main shared memory block. ++ * ++ * The global header contains metadata for allocations as well as a fixed list ++ * of 512 entries (@smem_global_entry) that can be initialized to reference ++ * parts of the shared memory space. ++ * ++ * ++ * In addition to this global heap a set of "private" heaps can be set up at ++ * boot time with access restrictions so that only certain processor pairs can ++ * access the data. ++ * ++ * These partitions are referenced from an optional partition table ++ * (@smem_ptable), that is found 4kB from the end of the main smem region. The ++ * partition table entries (@smem_ptable_entry) lists the involved processors ++ * (or hosts) and their location in the main shared memory region. ++ * ++ * Each partition starts with a header (@smem_partition_header) that identifies ++ * the partition and holds properties for the two internal memory regions. The ++ * two regions are cached and non-cached memory respectively. Each region ++ * contain a link list of allocation headers (@smem_private_entry) followed by ++ * their data. ++ * ++ * Items in the non-cached region are allocated from the start of the partition ++ * while items in the cached region are allocated from the end. The free area ++ * is hence the region between the cached and non-cached offsets. ++ * ++ * ++ * To synchronize allocations in the shared memory heaps a remote spinlock must ++ * be held - currently lock number 3 of the sfpb or tcsr is used for this on all ++ * platforms. ++ * ++ */ ++ ++/** ++ * struct smem_proc_comm - proc_comm communication struct (legacy) ++ * @command: current command to be executed ++ * @status: status of the currently requested command ++ * @params: parameters to the command ++ */ ++struct smem_proc_comm { ++ u32 command; ++ u32 status; ++ u32 params[2]; ++}; ++ ++/** ++ * struct smem_global_entry - entry to reference smem items on the heap ++ * @allocated: boolean to indicate if this entry is used ++ * @offset: offset to the allocated space ++ * @size: size of the allocated space, 8 byte aligned ++ * @aux_base: base address for the memory region used by this unit, or 0 for ++ * the default region. bits 0,1 are reserved ++ */ ++struct smem_global_entry { ++ u32 allocated; ++ u32 offset; ++ u32 size; ++ u32 aux_base; /* bits 1:0 reserved */ ++}; ++#define AUX_BASE_MASK 0xfffffffc ++ ++/** ++ * struct smem_header - header found in beginning of primary smem region ++ * @proc_comm: proc_comm communication interface (legacy) ++ * @version: array of versions for the various subsystems ++ * @initialized: boolean to indicate that smem is initialized ++ * @free_offset: index of the first unallocated byte in smem ++ * @available: number of bytes available for allocation ++ * @reserved: reserved field, must be 0 ++ * toc: array of references to items ++ */ ++struct smem_header { ++ struct smem_proc_comm proc_comm[4]; ++ u32 version[32]; ++ u32 initialized; ++ u32 free_offset; ++ u32 available; ++ u32 reserved; ++ struct smem_global_entry toc[]; ++}; ++ ++/** ++ * struct smem_ptable_entry - one entry in the @smem_ptable list ++ * @offset: offset, within the main shared memory region, of the partition ++ * @size: size of the partition ++ * @flags: flags for the partition (currently unused) ++ * @host0: first processor/host with access to this partition ++ * @host1: second processor/host with access to this partition ++ * @reserved: reserved entries for later use ++ */ ++struct smem_ptable_entry { ++ u32 offset; ++ u32 size; ++ u32 flags; ++ u16 host0; ++ u16 host1; ++ u32 reserved[8]; ++}; ++ ++/** ++ * struct smem_ptable - partition table for the private partitions ++ * @magic: magic number, must be SMEM_PTABLE_MAGIC ++ * @version: version of the partition table ++ * @num_entries: number of partitions in the table ++ * @reserved: for now reserved entries ++ * @entry: list of @smem_ptable_entry for the @num_entries partitions ++ */ ++struct smem_ptable { ++ u32 magic; ++ u32 version; ++ u32 num_entries; ++ u32 reserved[5]; ++ struct smem_ptable_entry entry[]; ++}; ++#define SMEM_PTABLE_MAGIC 0x434f5424 /* "$TOC" */ ++ ++/** ++ * struct smem_partition_header - header of the partitions ++ * @magic: magic number, must be SMEM_PART_MAGIC ++ * @host0: first processor/host with access to this partition ++ * @host1: second processor/host with access to this partition ++ * @size: size of the partition ++ * @offset_free_uncached: offset to the first free byte of uncached memory in ++ * this partition ++ * @offset_free_cached: offset to the first free byte of cached memory in this ++ * partition ++ * @reserved: for now reserved entries ++ */ ++struct smem_partition_header { ++ u32 magic; ++ u16 host0; ++ u16 host1; ++ u32 size; ++ u32 offset_free_uncached; ++ u32 offset_free_cached; ++ u32 reserved[3]; ++}; ++#define SMEM_PART_MAGIC 0x54525024 /* "$PRT" */ ++ ++/** ++ * struct smem_private_entry - header of each item in the private partition ++ * @canary: magic number, must be SMEM_PRIVATE_CANARY ++ * @item: identifying number of the smem item ++ * @size: size of the data, including padding bytes ++ * @padding_data: number of bytes of padding of data ++ * @padding_hdr: number of bytes of padding between the header and the data ++ * @reserved: for now reserved entry ++ */ ++struct smem_private_entry { ++ u16 canary; ++ u16 item; ++ u32 size; /* includes padding bytes */ ++ u16 padding_data; ++ u16 padding_hdr; ++ u32 reserved; ++}; ++#define SMEM_PRIVATE_CANARY 0xa5a5 ++ ++/* ++ * Item 3 of the global heap contains an array of versions for the various ++ * software components in the SoC. We verify that the boot loader version is ++ * what the expected version (SMEM_EXPECTED_VERSION) as a sanity check. ++ */ ++#define SMEM_ITEM_VERSION 3 ++#define SMEM_MASTER_SBL_VERSION_INDEX 7 ++#define SMEM_EXPECTED_VERSION 11 ++ ++/* ++ * The first 8 items are only to be allocated by the boot loader while ++ * initializing the heap. ++ */ ++#define SMEM_ITEM_LAST_FIXED 8 ++ ++/* Highest accepted item number, for both global and private heaps */ ++#define SMEM_ITEM_LAST 512 ++ ++/* Processor/host identifier for the application processor */ ++#define SMEM_HOST_APPS 0 ++ ++/* Max number of processors/hosts in a system */ ++#define SMEM_HOST_COUNT 7 ++ ++/** ++ * struct smem_region - representation of a chunk of memory used for smem ++ * @aux_base: identifier of aux_mem base ++ * @virt_base: virtual base address of memory with this aux_mem identifier ++ * @size: size of the memory region ++ */ ++struct smem_region { ++ u32 aux_base; ++ void __iomem *virt_base; ++ size_t size; ++}; ++ ++/** ++ * struct qcom_smem - device data for the smem device ++ * @dev: device pointer ++ * @hwlock: reference to a hwspinlock ++ * @partitions: list of pointers to partitions affecting the current ++ * processor/host ++ * @num_regions: number of @regions ++ * @regions: list of the memory regions defining the shared memory ++ */ ++struct qcom_smem { ++ struct device *dev; ++ ++ struct hwspinlock *hwlock; ++ ++ struct smem_partition_header *partitions[SMEM_HOST_COUNT]; ++ ++ unsigned num_regions; ++ struct smem_region regions[0]; ++}; ++ ++/* Pointer to the one and only smem handle */ ++static struct qcom_smem *__smem; ++ ++/* Timeout (ms) for the trylock of remote spinlocks */ ++#define HWSPINLOCK_TIMEOUT 1000 ++ ++static int qcom_smem_alloc_private(struct qcom_smem *smem, ++ unsigned host, ++ unsigned item, ++ size_t size) ++{ ++ struct smem_partition_header *phdr; ++ struct smem_private_entry *hdr; ++ size_t alloc_size; ++ void *p; ++ ++ /* We're not going to find it if there's no matching partition */ ++ if (host >= SMEM_HOST_COUNT || !smem->partitions[host]) ++ return -ENOENT; ++ ++ phdr = smem->partitions[host]; ++ ++ p = (void *)phdr + sizeof(*phdr); ++ while (p < (void *)phdr + phdr->offset_free_uncached) { ++ hdr = p; ++ ++ if (hdr->canary != SMEM_PRIVATE_CANARY) { ++ dev_err(smem->dev, ++ "Found invalid canary in host %d partition\n", ++ host); ++ return -EINVAL; ++ } ++ ++ if (hdr->item == item) ++ return -EEXIST; ++ ++ p += sizeof(*hdr) + hdr->padding_hdr + hdr->size; ++ } ++ ++ /* Check that we don't grow into the cached region */ ++ alloc_size = sizeof(*hdr) + ALIGN(size, 8); ++ if (p + alloc_size >= (void *)phdr + phdr->offset_free_cached) { ++ dev_err(smem->dev, "Out of memory\n"); ++ return -ENOSPC; ++ } ++ ++ hdr = p; ++ hdr->canary = SMEM_PRIVATE_CANARY; ++ hdr->item = item; ++ hdr->size = ALIGN(size, 8); ++ hdr->padding_data = hdr->size - size; ++ hdr->padding_hdr = 0; ++ ++ /* ++ * Ensure the header is written before we advance the free offset, so ++ * that remote processors that does not take the remote spinlock still ++ * gets a consistent view of the linked list. ++ */ ++ wmb(); ++ phdr->offset_free_uncached += alloc_size; ++ ++ return 0; ++} ++ ++static int qcom_smem_alloc_global(struct qcom_smem *smem, ++ unsigned item, ++ size_t size) ++{ ++ struct smem_header *header; ++ struct smem_global_entry *entry; ++ ++ if (WARN_ON(item >= SMEM_ITEM_LAST)) ++ return -EINVAL; ++ ++ header = smem->regions[0].virt_base; ++ entry = &header->toc[item]; ++ if (entry->allocated) ++ return -EEXIST; ++ ++ size = ALIGN(size, 8); ++ if (WARN_ON(size > header->available)) ++ return -ENOMEM; ++ ++ entry->offset = header->free_offset; ++ entry->size = size; ++ ++ /* ++ * Ensure the header is consistent before we mark the item allocated, ++ * so that remote processors will get a consistent view of the item ++ * even though they do not take the spinlock on read. ++ */ ++ wmb(); ++ entry->allocated = 1; ++ ++ header->free_offset += size; ++ header->available -= size; ++ ++ return 0; ++} ++ ++/** ++ * qcom_smem_alloc - allocate space for a smem item ++ * @host: remote processor id, or -1 ++ * @item: smem item handle ++ * @size: number of bytes to be allocated ++ * ++ * Allocate space for a given smem item of size @size, given that the item is ++ * not yet allocated. ++ */ ++int qcom_smem_alloc(unsigned host, unsigned item, size_t size) ++{ ++ unsigned long flags; ++ int ret; ++ ++ if (!__smem) ++ return -EPROBE_DEFER; ++ ++ if (item < SMEM_ITEM_LAST_FIXED) { ++ dev_err(__smem->dev, ++ "Rejecting allocation of static entry %d\n", item); ++ return -EINVAL; ++ } ++ ++ ret = hwspin_lock_timeout_irqsave(__smem->hwlock, ++ HWSPINLOCK_TIMEOUT, ++ &flags); ++ if (ret) ++ return ret; ++ ++ ret = qcom_smem_alloc_private(__smem, host, item, size); ++ if (ret == -ENOENT) ++ ret = qcom_smem_alloc_global(__smem, item, size); ++ ++ hwspin_unlock_irqrestore(__smem->hwlock, &flags); ++ ++ return ret; ++} ++EXPORT_SYMBOL(qcom_smem_alloc); ++ ++static int qcom_smem_get_global(struct qcom_smem *smem, ++ unsigned item, ++ void **ptr, ++ size_t *size) ++{ ++ struct smem_header *header; ++ struct smem_region *area; ++ struct smem_global_entry *entry; ++ u32 aux_base; ++ unsigned i; ++ ++ if (WARN_ON(item >= SMEM_ITEM_LAST)) ++ return -EINVAL; ++ ++ header = smem->regions[0].virt_base; ++ entry = &header->toc[item]; ++ if (!entry->allocated) ++ return -ENXIO; ++ ++ if (ptr != NULL) { ++ aux_base = entry->aux_base & AUX_BASE_MASK; ++ ++ for (i = 0; i < smem->num_regions; i++) { ++ area = &smem->regions[i]; ++ ++ if (area->aux_base == aux_base || !aux_base) { ++ *ptr = area->virt_base + entry->offset; ++ break; ++ } ++ } ++ } ++ if (size != NULL) ++ *size = entry->size; ++ ++ return 0; ++} ++ ++static int qcom_smem_get_private(struct qcom_smem *smem, ++ unsigned host, ++ unsigned item, ++ void **ptr, ++ size_t *size) ++{ ++ struct smem_partition_header *phdr; ++ struct smem_private_entry *hdr; ++ void *p; ++ ++ /* We're not going to find it if there's no matching partition */ ++ if (host >= SMEM_HOST_COUNT || !smem->partitions[host]) ++ return -ENOENT; ++ ++ phdr = smem->partitions[host]; ++ ++ p = (void *)phdr + sizeof(*phdr); ++ while (p < (void *)phdr + phdr->offset_free_uncached) { ++ hdr = p; ++ ++ if (hdr->canary != SMEM_PRIVATE_CANARY) { ++ dev_err(smem->dev, ++ "Found invalid canary in host %d partition\n", ++ host); ++ return -EINVAL; ++ } ++ ++ if (hdr->item == item) { ++ if (ptr != NULL) ++ *ptr = p + sizeof(*hdr) + hdr->padding_hdr; ++ ++ if (size != NULL) ++ *size = hdr->size - hdr->padding_data; ++ ++ return 0; ++ } ++ ++ p += sizeof(*hdr) + hdr->padding_hdr + hdr->size; ++ } ++ ++ return -ENOENT; ++} ++ ++/** ++ * qcom_smem_get - resolve ptr of size of a smem item ++ * @host: the remote processor, or -1 ++ * @item: smem item handle ++ * @ptr: pointer to be filled out with address of the item ++ * @size: pointer to be filled out with size of the item ++ * ++ * Looks up pointer and size of a smem item. ++ */ ++int qcom_smem_get(unsigned host, unsigned item, void **ptr, size_t *size) ++{ ++ unsigned long flags; ++ int ret; ++ ++ if (!__smem) ++ return -EPROBE_DEFER; ++ ++ ret = hwspin_lock_timeout_irqsave(__smem->hwlock, ++ HWSPINLOCK_TIMEOUT, ++ &flags); ++ if (ret) ++ return ret; ++ ++ ret = qcom_smem_get_private(__smem, host, item, ptr, size); ++ if (ret == -ENOENT) ++ ret = qcom_smem_get_global(__smem, item, ptr, size); ++ ++ hwspin_unlock_irqrestore(__smem->hwlock, &flags); ++ return ret; ++ ++} ++EXPORT_SYMBOL(qcom_smem_get); ++ ++/** ++ * qcom_smem_get_free_space - retrieve amont of free space in a partition ++ * @host: the remote processor identifing a partition, or -1 ++ * ++ * To be used by smem clients as a quick way to determine if any new ++ * allocations has been made. ++ */ ++int qcom_smem_get_free_space(unsigned host) ++{ ++ struct smem_partition_header *phdr; ++ struct smem_header *header; ++ unsigned ret; ++ ++ if (!__smem) ++ return -EPROBE_DEFER; ++ ++ if (host < SMEM_HOST_COUNT && __smem->partitions[host]) { ++ phdr = __smem->partitions[host]; ++ ret = phdr->offset_free_uncached; ++ } else { ++ header = __smem->regions[0].virt_base; ++ ret = header->available; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL(qcom_smem_get_free_space); ++ ++static int qcom_smem_get_sbl_version(struct qcom_smem *smem) ++{ ++ unsigned *versions; ++ size_t size; ++ int ret; ++ ++ ret = qcom_smem_get_global(smem, SMEM_ITEM_VERSION, ++ (void **)&versions, &size); ++ if (ret < 0) { ++ dev_err(smem->dev, "Unable to read the version item\n"); ++ return -ENOENT; ++ } ++ ++ if (size < sizeof(unsigned) * SMEM_MASTER_SBL_VERSION_INDEX) { ++ dev_err(smem->dev, "Version item is too small\n"); ++ return -EINVAL; ++ } ++ ++ return versions[SMEM_MASTER_SBL_VERSION_INDEX]; ++} ++ ++static int qcom_smem_enumerate_partitions(struct qcom_smem *smem, ++ unsigned local_host) ++{ ++ struct smem_partition_header *header; ++ struct smem_ptable_entry *entry; ++ struct smem_ptable *ptable; ++ unsigned remote_host; ++ int i; ++ ++ ptable = smem->regions[0].virt_base + smem->regions[0].size - 4 * 1024; ++ if (ptable->magic != SMEM_PTABLE_MAGIC) ++ return 0; ++ ++ if (ptable->version != 1) { ++ dev_err(smem->dev, ++ "Unsupported partition header version %d\n", ++ ptable->version); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < ptable->num_entries; i++) { ++ entry = &ptable->entry[i]; ++ ++ if (entry->host0 != local_host && entry->host1 != local_host) ++ continue; ++ ++ if (!entry->offset) ++ continue; ++ ++ if (!entry->size) ++ continue; ++ ++ if (entry->host0 == local_host) ++ remote_host = entry->host1; ++ else ++ remote_host = entry->host0; ++ ++ if (smem->partitions[remote_host]) { ++ dev_err(smem->dev, ++ "Already found a partition for host %d\n", ++ remote_host); ++ return -EINVAL; ++ } ++ ++ header = smem->regions[0].virt_base + entry->offset; ++ ++ if (header->magic != SMEM_PART_MAGIC) { ++ dev_err(smem->dev, ++ "Partition %d has invalid magic\n", i); ++ return -EINVAL; ++ } ++ ++ if (header->host0 != local_host && header->host1 != local_host) { ++ dev_err(smem->dev, ++ "Partition %d hosts are invalid\n", i); ++ return -EINVAL; ++ } ++ ++ if (header->host0 != remote_host && header->host1 != remote_host) { ++ dev_err(smem->dev, ++ "Partition %d hosts are invalid\n", i); ++ return -EINVAL; ++ } ++ ++ if (header->size != entry->size) { ++ dev_err(smem->dev, ++ "Partition %d has invalid size\n", i); ++ return -EINVAL; ++ } ++ ++ if (header->offset_free_uncached > header->size) { ++ dev_err(smem->dev, ++ "Partition %d has invalid free pointer\n", i); ++ return -EINVAL; ++ } ++ ++ smem->partitions[remote_host] = header; ++ } ++ ++ return 0; ++} ++ ++static int qcom_smem_count_mem_regions(struct platform_device *pdev) ++{ ++ struct resource *res; ++ int num_regions = 0; ++ int i; ++ ++ for (i = 0; i < pdev->num_resources; i++) { ++ res = &pdev->resource[i]; ++ ++ if (resource_type(res) == IORESOURCE_MEM) ++ num_regions++; ++ } ++ ++ return num_regions; ++} ++ ++static int qcom_smem_probe(struct platform_device *pdev) ++{ ++ struct smem_header *header; ++ struct device_node *np; ++ struct qcom_smem *smem; ++ struct resource *res; ++ struct resource r; ++ size_t array_size; ++ int num_regions = 0; ++ int hwlock_id; ++ u32 version; ++ int ret; ++ int i; ++ ++ num_regions = qcom_smem_count_mem_regions(pdev) + 1; ++ ++ array_size = num_regions * sizeof(struct smem_region); ++ smem = devm_kzalloc(&pdev->dev, sizeof(*smem) + array_size, GFP_KERNEL); ++ if (!smem) ++ return -ENOMEM; ++ ++ smem->dev = &pdev->dev; ++ smem->num_regions = num_regions; ++ ++ np = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); ++ if (!np) { ++ dev_err(&pdev->dev, "No memory-region specified\n"); ++ return -EINVAL; ++ } ++ ++ ret = of_address_to_resource(np, 0, &r); ++ of_node_put(np); ++ if (ret) ++ return ret; ++ ++ smem->regions[0].aux_base = (u32)r.start; ++ smem->regions[0].size = resource_size(&r); ++ smem->regions[0].virt_base = devm_ioremap_nocache(&pdev->dev, ++ r.start, ++ resource_size(&r)); ++ if (!smem->regions[0].virt_base) ++ return -ENOMEM; ++ ++ for (i = 1; i < num_regions; i++) { ++ res = platform_get_resource(pdev, IORESOURCE_MEM, i - 1); ++ ++ smem->regions[i].aux_base = (u32)res->start; ++ smem->regions[i].size = resource_size(res); ++ smem->regions[i].virt_base = devm_ioremap_nocache(&pdev->dev, ++ res->start, ++ resource_size(res)); ++ if (!smem->regions[i].virt_base) ++ return -ENOMEM; ++ } ++ ++ header = smem->regions[0].virt_base; ++ if (header->initialized != 1 || header->reserved) { ++ dev_err(&pdev->dev, "SMEM is not initilized by SBL\n"); ++ return -EINVAL; ++ } ++ ++ version = qcom_smem_get_sbl_version(smem); ++ if (version >> 16 != SMEM_EXPECTED_VERSION) { ++ dev_err(&pdev->dev, "Unsupported smem version 0x%x\n", version); ++ return -EINVAL; ++ } ++ ++ ret = qcom_smem_enumerate_partitions(smem, SMEM_HOST_APPS); ++ if (ret < 0) ++ return ret; ++ ++ hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); ++ if (hwlock_id < 0) { ++ dev_err(&pdev->dev, "failed to retrieve hwlock\n"); ++ return hwlock_id; ++ } ++ ++ smem->hwlock = hwspin_lock_request_specific(hwlock_id); ++ if (!smem->hwlock) ++ return -ENXIO; ++ ++ __smem = smem; ++ ++ return 0; ++} ++ ++static int qcom_smem_remove(struct platform_device *pdev) ++{ ++ hwspin_lock_free(__smem->hwlock); ++ __smem = NULL; ++ ++ return 0; ++} ++ ++static const struct of_device_id qcom_smem_of_match[] = { ++ { .compatible = "qcom,smem" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, qcom_smem_of_match); ++ ++static struct platform_driver qcom_smem_driver = { ++ .probe = qcom_smem_probe, ++ .remove = qcom_smem_remove, ++ .driver = { ++ .name = "qcom_smem", ++ .of_match_table = qcom_smem_of_match, ++ .suppress_bind_attrs = true, ++ }, ++}; ++ ++static int __init qcom_smem_init(void) ++{ ++ return platform_driver_register(&qcom_smem_driver); ++} ++arch_initcall(qcom_smem_init); ++ ++static void __exit qcom_smem_exit(void) ++{ ++ platform_driver_unregister(&qcom_smem_driver); ++} ++module_exit(qcom_smem_exit) ++ ++MODULE_AUTHOR("Bjorn Andersson "); ++MODULE_DESCRIPTION("Qualcomm Shared Memory Manager"); ++MODULE_LICENSE("GPLv2"); +--- /dev/null ++++ b/include/linux/soc/qcom/smem.h +@@ -0,0 +1,14 @@ ++#ifndef __QCOM_SMEM_H__ ++#define __QCOM_SMEM_H__ ++ ++struct device_node; ++struct qcom_smem; ++ ++#define QCOM_SMEM_HOST_ANY -1 ++ ++int qcom_smem_alloc(unsigned host, unsigned item, size_t size); ++int qcom_smem_get(unsigned host, unsigned item, void **ptr, size_t *size); ++ ++int qcom_smem_get_free_space(unsigned host); ++ ++#endif diff --git a/target/linux/ipq806x/patches-3.18/036-ARM-qcom-add-SMEM-device-node-to-IPQ806x-dts.patch b/target/linux/ipq806x/patches-3.18/036-ARM-qcom-add-SMEM-device-node-to-IPQ806x-dts.patch new file mode 100644 index 0000000..b2b9a74 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/036-ARM-qcom-add-SMEM-device-node-to-IPQ806x-dts.patch @@ -0,0 +1,36 @@ +From f212be3a6134db8dd7c5f6f0987536a669401fae Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 14 Aug 2015 11:17:20 -0700 +Subject: [PATCH 2/3] ARM: qcom: add SMEM device node to IPQ806x dts + +SMEM is used on IPQ806x to store various board related information such +as boot device and flash partition layout. We'll declare it as a device +so we can make use of it thanks to the new SMEM soc driver. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -54,7 +54,7 @@ + no-map; + }; + +- smem@41000000 { ++ smem: smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; +@@ -304,4 +304,10 @@ + + #hwlock-cells = <1>; + }; ++ ++ smem { ++ compatible = "qcom,smem"; ++ memory-region = <&smem>; ++ hwlocks = <&sfpb_mutex 3>; ++ }; + }; diff --git a/target/linux/ipq806x/patches-3.18/037-mtd-add-SMEM-parser-for-QCOM-platforms.patch b/target/linux/ipq806x/patches-3.18/037-mtd-add-SMEM-parser-for-QCOM-platforms.patch new file mode 100644 index 0000000..b2c8cd5 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/037-mtd-add-SMEM-parser-for-QCOM-platforms.patch @@ -0,0 +1,277 @@ +From 0501f76b138cf1dc11a313bb7a094da524b79337 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Thu, 13 Aug 2015 09:53:14 -0700 +Subject: [PATCH 3/3] mtd: add SMEM parser for QCOM platforms + +On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is +used to store partition layout. This new parser can now be used to read +SMEM and use it to register an MTD layout according to its content. + +Signed-off-by: Mathieu Olivari +--- + drivers/mtd/Kconfig | 7 ++ + drivers/mtd/Makefile | 1 + + drivers/mtd/qcom_smem_part.c | 231 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 239 insertions(+) + create mode 100644 drivers/mtd/qcom_smem_part.c + +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -200,6 +200,13 @@ config MTD_MYLOADER_PARTS + You will still need the parsing functions to be called by the driver + for your particular device. It won't happen automatically. + ++config MTD_QCOM_SMEM_PARTS ++ tristate "QCOM SMEM partitioning support" ++ depends on QCOM_SMEM ++ help ++ This provides partitions parser for QCOM devices using SMEM ++ such as IPQ806x. ++ + comment "User Modules And Translation Layers" + + # +--- /dev/null ++++ b/drivers/mtd/qcom_smem_part.c +@@ -0,0 +1,231 @@ ++/* ++ * Copyright (c) 2015, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* Processor/host identifier for the application processor */ ++#define SMEM_HOST_APPS 0 ++ ++/* SMEM items index */ ++#define SMEM_AARM_PARTITION_TABLE 9 ++#define SMEM_BOOT_FLASH_TYPE 421 ++#define SMEM_BOOT_FLASH_BLOCK_SIZE 424 ++ ++/* SMEM Flash types */ ++#define SMEM_FLASH_NAND 2 ++#define SMEM_FLASH_SPI 6 ++ ++#define SMEM_PART_NAME_SZ 16 ++#define SMEM_PARTS_MAX 32 ++ ++struct smem_partition { ++ char name[SMEM_PART_NAME_SZ]; ++ __le32 start; ++ __le32 size; ++ __le32 attr; ++}; ++ ++struct smem_partition_table { ++ u8 magic[8]; ++ __le32 version; ++ __le32 len; ++ struct smem_partition parts[SMEM_PARTS_MAX]; ++}; ++ ++/* SMEM Magic values in partition table */ ++static const u8 SMEM_PTABLE_MAGIC[] = { ++ 0xaa, 0x73, 0xee, 0x55, ++ 0xdb, 0xbd, 0x5e, 0xe3, ++}; ++ ++static int qcom_smem_get_flash_blksz(u64 **smem_blksz) ++{ ++ int ret; ++ size_t size; ++ ++ ret = qcom_smem_get(SMEM_HOST_APPS, SMEM_BOOT_FLASH_BLOCK_SIZE, ++ (void **) smem_blksz, &size); ++ ++ if (ret < 0) { ++ pr_err("Unable to read flash blksz from SMEM\n"); ++ return -ENOENT; ++ } ++ ++ if (size != sizeof(**smem_blksz)) { ++ pr_err("Invalid flash blksz size in SMEM\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int qcom_smem_get_flash_type(u64 **smem_flash_type) ++{ ++ int ret; ++ size_t size; ++ ++ ret = qcom_smem_get(SMEM_HOST_APPS, SMEM_BOOT_FLASH_TYPE, ++ (void **) smem_flash_type, &size); ++ ++ if (ret < 0) { ++ pr_err("Unable to read flash type from SMEM\n"); ++ return -ENOENT; ++ } ++ ++ if (size != sizeof(**smem_flash_type)) { ++ pr_err("Invalid flash type size in SMEM\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int qcom_smem_get_flash_partitions(struct smem_partition_table **pparts) ++{ ++ int ret; ++ size_t size; ++ ++ ret = qcom_smem_get(SMEM_HOST_APPS, SMEM_AARM_PARTITION_TABLE, ++ (void **) pparts, &size); ++ ++ if (ret < 0) { ++ pr_err("Unable to read partition table from SMEM\n"); ++ return -ENOENT; ++ } ++ ++ return 0; ++} ++ ++static int of_dev_node_match(struct device *dev, void *data) ++{ ++ return dev->of_node == data; ++} ++ ++static bool is_spi_device(struct device_node *np) ++{ ++ struct device *dev; ++ ++ dev = bus_find_device(&spi_bus_type, NULL, np, of_dev_node_match); ++ if (!dev) ++ return false; ++ ++ put_device(dev); ++ return true; ++} ++ ++static int parse_qcom_smem_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct smem_partition_table *smem_parts; ++ u64 *smem_flash_type, *smem_blksz; ++ struct mtd_partition *mtd_parts; ++ struct device_node *of_node = data->of_node; ++ int i, ret; ++ ++ /* ++ * SMEM will only store the partition table of the boot device. ++ * If this is not the boot device, do not return any partition. ++ */ ++ ret = qcom_smem_get_flash_type(&smem_flash_type); ++ if (ret < 0) ++ return ret; ++ ++ if ((*smem_flash_type == SMEM_FLASH_NAND && !mtd_type_is_nand(master)) ++ || (*smem_flash_type == SMEM_FLASH_SPI && !is_spi_device(of_node))) ++ return 0; ++ ++ /* ++ * Just for sanity purpose, make sure the block size in SMEM matches the ++ * block size of the MTD device ++ */ ++ ret = qcom_smem_get_flash_blksz(&smem_blksz); ++ if (ret < 0) ++ return ret; ++ ++ if (*smem_blksz != master->erasesize) { ++ pr_err("SMEM block size differs from MTD block size\n"); ++ return -EINVAL; ++ } ++ ++ /* Get partition pointer from SMEM */ ++ ret = qcom_smem_get_flash_partitions(&smem_parts); ++ if (ret < 0) ++ return ret; ++ ++ if (memcmp(SMEM_PTABLE_MAGIC, smem_parts->magic, ++ sizeof(SMEM_PTABLE_MAGIC))) { ++ pr_err("SMEM partition magic invalid\n"); ++ return -EINVAL; ++ } ++ ++ /* Allocate and populate the mtd structures */ ++ mtd_parts = kcalloc(le32_to_cpu(smem_parts->len), sizeof(*mtd_parts), ++ GFP_KERNEL); ++ if (!mtd_parts) ++ return -ENOMEM; ++ ++ for (i = 0; i < smem_parts->len; i++) { ++ struct smem_partition *s_part = &smem_parts->parts[i]; ++ struct mtd_partition *m_part = &mtd_parts[i]; ++ ++ m_part->name = s_part->name; ++ m_part->size = le32_to_cpu(s_part->size) * (*smem_blksz); ++ m_part->offset = le32_to_cpu(s_part->start) * (*smem_blksz); ++ ++ /* ++ * The last SMEM partition may have its size marked as ++ * something like 0xffffffff, which means "until the end of the ++ * flash device". In this case, truncate it. ++ */ ++ if (m_part->offset + m_part->size > master->size) ++ m_part->size = master->size - m_part->offset; ++ } ++ ++ *pparts = mtd_parts; ++ ++ return smem_parts->len; ++} ++ ++static struct mtd_part_parser qcom_smem_parser = { ++ .owner = THIS_MODULE, ++ .parse_fn = parse_qcom_smem_partitions, ++ .name = "qcom-smem", ++}; ++ ++static int __init qcom_smem_parser_init(void) ++{ ++ register_mtd_parser(&qcom_smem_parser); ++ return 0; ++} ++ ++static void __exit qcom_smem_parser_exit(void) ++{ ++ deregister_mtd_parser(&qcom_smem_parser); ++} ++ ++module_init(qcom_smem_parser_init); ++module_exit(qcom_smem_parser_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Mathieu Olivari "); ++MODULE_DESCRIPTION("Parsing code for SMEM based partition tables"); +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_QCOM_SMEM_PARTS) += qcom_smem_part.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/ipq806x/patches-3.18/100-usb-phy-Add-Qualcomm-DWC3-HS-SS-PHY-drivers.patch b/target/linux/ipq806x/patches-3.18/100-usb-phy-Add-Qualcomm-DWC3-HS-SS-PHY-drivers.patch new file mode 100644 index 0000000..25803b8 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/100-usb-phy-Add-Qualcomm-DWC3-HS-SS-PHY-drivers.patch @@ -0,0 +1,511 @@ +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -256,4 +256,15 @@ config PHY_STIH41X_USB + Enable this to support the USB transceiver that is part of + STMicroelectronics STiH41x SoC series. + ++config PHY_QCOM_DWC3 ++ tristate "QCOM DWC3 USB PHY support" ++ depends on ARCH_QCOM ++ depends on HAS_IOMEM ++ depends on OF ++ select GENERIC_PHY ++ help ++ This option enables support for the Synopsis PHYs present inside the ++ Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS ++ PHY controllers. ++ + endmenu +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -31,3 +31,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += + obj-$(CONFIG_PHY_XGENE) += phy-xgene.o + obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o + obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o ++obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o +--- /dev/null ++++ b/drivers/phy/phy-qcom-dwc3.c +@@ -0,0 +1,483 @@ ++/* Copyright (c) 2013-2014, Code Aurora Forum. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/** ++ * USB QSCRATCH Hardware registers ++ */ ++#define QSCRATCH_GENERAL_CFG (0x08) ++#define HSUSB_PHY_CTRL_REG (0x10) ++ ++/* PHY_CTRL_REG */ ++#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24) ++#define HSUSB_CTRL_USB2_SUSPEND BIT(23) ++#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) ++#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) ++#define HSUSB_CTRL_USE_CLKCORE BIT(18) ++#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17) ++#define HSUSB_CTRL_COMMONONN BIT(11) ++#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) ++#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8) ++#define HSUSB_CTRL_CLAMP_EN BIT(7) ++#define HSUSB_CTRL_RETENABLEN BIT(1) ++#define HSUSB_CTRL_POR BIT(0) ++ ++/* QSCRATCH_GENERAL_CFG */ ++#define HSUSB_GCFG_XHCI_REV BIT(2) ++ ++/** ++ * USB QSCRATCH Hardware registers ++ */ ++#define SSUSB_PHY_CTRL_REG (0x00) ++#define SSUSB_PHY_PARAM_CTRL_1 (0x04) ++#define SSUSB_PHY_PARAM_CTRL_2 (0x08) ++#define CR_PROTOCOL_DATA_IN_REG (0x0c) ++#define CR_PROTOCOL_DATA_OUT_REG (0x10) ++#define CR_PROTOCOL_CAP_ADDR_REG (0x14) ++#define CR_PROTOCOL_CAP_DATA_REG (0x18) ++#define CR_PROTOCOL_READ_REG (0x1c) ++#define CR_PROTOCOL_WRITE_REG (0x20) ++ ++/* PHY_CTRL_REG */ ++#define SSUSB_CTRL_REF_USE_PAD BIT(28) ++#define SSUSB_CTRL_TEST_POWERDOWN BIT(27) ++#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) ++#define SSUSB_CTRL_SS_PHY_EN BIT(8) ++#define SSUSB_CTRL_SS_PHY_RESET BIT(7) ++ ++/* SSPHY control registers */ ++#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane) ++#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane) ++ ++/* RX OVRD IN HI bits */ ++#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13) ++#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12) ++#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) ++#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700 ++#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8 ++#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7) ++#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6) ++#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5) ++#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018 ++#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2) ++#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003 ++ ++/* TX OVRD DRV LO register bits */ ++#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F ++#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80 ++#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7 ++#define TX_OVRD_DRV_LO_EN BIT(14) ++ ++struct qcom_dwc3_usb_phy { ++ void __iomem *base; ++ struct device *dev; ++ struct phy *phy; ++ ++ int (*phy_init)(struct qcom_dwc3_usb_phy *phy_dwc3); ++ int (*phy_exit)(struct qcom_dwc3_usb_phy *phy_dwc3); ++ ++ struct clk *xo_clk; ++ struct clk *ref_clk; ++}; ++ ++/** ++ * Write register and read back masked value to confirm it is written ++ * ++ * @base - QCOM DWC3 PHY base virtual address. ++ * @offset - register offset. ++ * @mask - register bitmask specifying what should be updated ++ * @val - value to write. ++ */ ++static inline void qcom_dwc3_phy_write_readback( ++ struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset, ++ const u32 mask, u32 val) ++{ ++ u32 write_val, tmp = readl(phy_dwc3->base + offset); ++ ++ tmp &= ~mask; /* retain other bits */ ++ write_val = tmp | val; ++ ++ writel(write_val, phy_dwc3->base + offset); ++ ++ /* Read back to see if val was written */ ++ tmp = readl(phy_dwc3->base + offset); ++ tmp &= mask; /* clear other bits */ ++ ++ if (tmp != val) ++ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", ++ val, offset); ++} ++ ++static int wait_for_latch(void __iomem *addr) ++{ ++ u32 retry = 10; ++ ++ while (true) { ++ if (!readl(addr)) ++ break; ++ ++ if (--retry == 0) ++ return -ETIMEDOUT; ++ ++ usleep_range(10, 20); ++ } ++ ++ return 0; ++} ++ ++/** ++ * Write SSPHY register ++ * ++ * @base - QCOM DWC3 PHY base virtual address. ++ * @addr - SSPHY address to write. ++ * @val - value to write. ++ */ ++static int qcom_dwc3_ss_write_phycreg(void __iomem *base, u32 addr, u32 val) ++{ ++ int ret; ++ ++ writel(addr, base + CR_PROTOCOL_DATA_IN_REG); ++ writel(0x1, base + CR_PROTOCOL_CAP_ADDR_REG); ++ ++ ret = wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG); ++ if (ret) ++ goto err_wait; ++ ++ writel(val, base + CR_PROTOCOL_DATA_IN_REG); ++ writel(0x1, base + CR_PROTOCOL_CAP_DATA_REG); ++ ++ ret = wait_for_latch(base + CR_PROTOCOL_CAP_DATA_REG); ++ if (ret) ++ goto err_wait; ++ ++ writel(0x1, base + CR_PROTOCOL_WRITE_REG); ++ ++ ret = wait_for_latch(base + CR_PROTOCOL_WRITE_REG); ++ ++err_wait: ++ return ret; ++} ++ ++/** ++ * Read SSPHY register. ++ * ++ * @base - QCOM DWC3 PHY base virtual address. ++ * @addr - SSPHY address to read. ++ */ ++static int qcom_dwc3_ss_read_phycreg(void __iomem *base, u32 addr, u32 *val) ++{ ++ int ret; ++ bool first_read = true; ++ ++ writel(addr, base + CR_PROTOCOL_DATA_IN_REG); ++ writel(0x1, base + CR_PROTOCOL_CAP_ADDR_REG); ++ ++ ret = wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG); ++ if (ret) ++ goto err_wait; ++ ++ /* ++ * Due to hardware bug, first read of SSPHY register might be ++ * incorrect. Hence as workaround, SW should perform SSPHY register ++ * read twice, but use only second read and ignore first read. ++ */ ++retry: ++ writel(0x1, base + CR_PROTOCOL_READ_REG); ++ ++ ret = wait_for_latch(base + CR_PROTOCOL_READ_REG); ++ if (ret) ++ goto err_wait; ++ ++ if (first_read) { ++ readl(base + CR_PROTOCOL_DATA_OUT_REG); ++ first_read = false; ++ goto retry; ++ } ++ ++ *val = readl(base + CR_PROTOCOL_DATA_OUT_REG); ++ ++err_wait: ++ return ret; ++} ++ ++static int qcom_dwc3_phy_power_on(struct phy *phy) ++{ ++ int ret; ++ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); ++ ++ ret = clk_prepare_enable(phy_dwc3->xo_clk); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(phy_dwc3->ref_clk); ++ if (ret) ++ clk_disable_unprepare(phy_dwc3->xo_clk); ++ ++ return ret; ++} ++ ++static int qcom_dwc3_phy_power_off(struct phy *phy) ++{ ++ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); ++ ++ clk_disable_unprepare(phy_dwc3->ref_clk); ++ clk_disable_unprepare(phy_dwc3->xo_clk); ++ ++ return 0; ++} ++ ++static int qcom_dwc3_hs_phy_init(struct qcom_dwc3_usb_phy *phy_dwc3) ++{ ++ u32 val; ++ ++ /* ++ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel ++ * enable clamping, and disable RETENTION (power-on default is ENABLED) ++ */ ++ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP | ++ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN | ++ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP | ++ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID | ++ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70; ++ ++ /* use core clock if external reference is not present */ ++ if (!phy_dwc3->xo_clk) ++ val |= HSUSB_CTRL_USE_CLKCORE; ++ ++ writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG); ++ usleep_range(2000, 2200); ++ ++ /* Disable (bypass) VBUS and ID filters */ ++ writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG); ++ ++ return 0; ++} ++ ++static int qcom_dwc3_ss_phy_init(struct qcom_dwc3_usb_phy *phy_dwc3) ++{ ++ int ret; ++ u32 data = 0; ++ ++ /* reset phy */ ++ data = readl_relaxed(phy_dwc3->base + SSUSB_PHY_CTRL_REG); ++ writel_relaxed(data | SSUSB_CTRL_SS_PHY_RESET, ++ phy_dwc3->base + SSUSB_PHY_CTRL_REG); ++ usleep_range(2000, 2200); ++ writel_relaxed(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG); ++ ++ /* clear REF_PAD if we don't have XO clk */ ++ if (!phy_dwc3->xo_clk) ++ data &= ~SSUSB_CTRL_REF_USE_PAD; ++ else ++ data |= SSUSB_CTRL_REF_USE_PAD; ++ ++ writel_relaxed(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG); ++ msleep(30); ++ ++ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT; ++ writel_relaxed(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG); ++ ++ /* ++ * Fix RX Equalization setting as follows ++ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 ++ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 ++ * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 ++ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 ++ */ ++ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, ++ SSPHY_CTRL_RX_OVRD_IN_HI(0), &data); ++ if (ret) ++ goto err_phy_trans; ++ ++ data &= ~RX_OVRD_IN_HI_RX_EQ_EN; ++ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD; ++ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK; ++ data |= 0x3 << RX_OVRD_IN_HI_RX_EQ_SHIFT; ++ data |= RX_OVRD_IN_HI_RX_EQ_OVRD; ++ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3->base, ++ SSPHY_CTRL_RX_OVRD_IN_HI(0), data); ++ if (ret) ++ goto err_phy_trans; ++ ++ /* ++ * Set EQ and TX launch amplitudes as follows ++ * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 ++ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 ++ * LANE0.TX_OVRD_DRV_LO.EN set to 1. ++ */ ++ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, ++ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data); ++ if (ret) ++ goto err_phy_trans; ++ ++ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK; ++ data |= 0x16 << TX_OVRD_DRV_LO_PREEMPH_SHIFT; ++ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK; ++ data |= 0x7f; ++ data |= TX_OVRD_DRV_LO_EN; ++ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3->base, ++ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data); ++ if (ret) ++ goto err_phy_trans; ++ ++ /* ++ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows ++ * TX_FULL_SWING [26:20] amplitude to 127 ++ * TX_DEEMPH_3_5DB [13:8] to 22 ++ * LOS_BIAS [2:0] to 0x5 ++ */ ++ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1, ++ 0x07f03f07, 0x07f01605); ++ ++err_phy_trans: ++ return ret; ++} ++ ++static int qcom_dwc3_ss_phy_exit(struct qcom_dwc3_usb_phy *phy_dwc3) ++{ ++ /* Sequence to put SSPHY in low power state: ++ * 1. Clear REF_PHY_EN in PHY_CTRL_REG ++ * 2. Clear REF_USE_PAD in PHY_CTRL_REG ++ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention ++ * 4. Disable SSPHY ref clk ++ */ ++ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, ++ SSUSB_CTRL_SS_PHY_EN, 0x0); ++ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, ++ SSUSB_CTRL_REF_USE_PAD, 0x0); ++ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG, ++ 0x0, SSUSB_CTRL_TEST_POWERDOWN); ++ ++ return 0; ++} ++ ++static int qcom_dwc3_phy_init(struct phy *phy) ++{ ++ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); ++ ++ if (phy_dwc3->phy_init) ++ return phy_dwc3->phy_init(phy_dwc3); ++ ++ return 0; ++} ++ ++static int qcom_dwc3_phy_exit(struct phy *phy) ++{ ++ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy); ++ ++ if (phy_dwc3->phy_exit) ++ return qcom_dwc3_ss_phy_exit(phy_dwc3); ++ ++ return 0; ++} ++ ++static struct phy_ops qcom_dwc3_phy_ops = { ++ .init = qcom_dwc3_phy_init, ++ .exit = qcom_dwc3_phy_exit, ++ .power_on = qcom_dwc3_phy_power_on, ++ .power_off = qcom_dwc3_phy_power_off, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct of_device_id qcom_dwc3_phy_table[] = { ++ { .compatible = "qcom,dwc3-hs-usb-phy", }, ++ { .compatible = "qcom,dwc3-ss-usb-phy", }, ++ { /* Sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table); ++ ++static int qcom_dwc3_phy_probe(struct platform_device *pdev) ++{ ++ struct qcom_dwc3_usb_phy *phy_dwc3; ++ struct phy_provider *phy_provider; ++ struct resource *res; ++ ++ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL); ++ if (!phy_dwc3) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, phy_dwc3); ++ ++ phy_dwc3->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ phy_dwc3->base = devm_ioremap_resource(phy_dwc3->dev, res); ++ if (IS_ERR(phy_dwc3->base)) ++ return PTR_ERR(phy_dwc3->base); ++ ++ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref"); ++ if (IS_ERR(phy_dwc3->ref_clk)) { ++ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n"); ++ return PTR_ERR(phy_dwc3->ref_clk); ++ } ++ ++ if (of_device_is_compatible(pdev->dev.of_node, ++ "qcom,dwc3-hs-usb-phy")) { ++ clk_set_rate(phy_dwc3->ref_clk, 60000000); ++ phy_dwc3->phy_init = qcom_dwc3_hs_phy_init; ++ } else if (of_device_is_compatible(pdev->dev.of_node, ++ "qcom,dwc3-ss-usb-phy")) { ++ phy_dwc3->phy_init = qcom_dwc3_ss_phy_init; ++ phy_dwc3->phy_exit = qcom_dwc3_ss_phy_exit; ++ clk_set_rate(phy_dwc3->ref_clk, 125000000); ++ } else { ++ dev_err(phy_dwc3->dev, "Unknown phy\n"); ++ return -EINVAL; ++ } ++ ++ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo"); ++ if (IS_ERR(phy_dwc3->xo_clk)) { ++ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n"); ++ phy_dwc3->xo_clk = NULL; ++ } ++ ++ phy_dwc3->phy = devm_phy_create(phy_dwc3->dev, NULL, &qcom_dwc3_phy_ops, ++ NULL); ++ ++ if (IS_ERR(phy_dwc3->phy)) ++ return PTR_ERR(phy_dwc3->phy); ++ ++ phy_set_drvdata(phy_dwc3->phy, phy_dwc3); ++ ++ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev, ++ of_phy_simple_xlate); ++ ++ if (IS_ERR(phy_provider)) ++ return PTR_ERR(phy_provider); ++ ++ return 0; ++} ++ ++static struct platform_driver qcom_dwc3_phy_driver = { ++ .probe = qcom_dwc3_phy_probe, ++ .driver = { ++ .name = "qcom-dwc3-usb-phy", ++ .owner = THIS_MODULE, ++ .of_match_table = qcom_dwc3_phy_table, ++ }, ++}; ++ ++module_platform_driver(qcom_dwc3_phy_driver); ++ ++MODULE_ALIAS("platform:phy-qcom-dwc3"); ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Andy Gross "); ++MODULE_AUTHOR("Ivan T. Ivanov "); ++MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver"); diff --git a/target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch b/target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch new file mode 100644 index 0000000..e2d03d4 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch @@ -0,0 +1,126 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -91,5 +91,29 @@ + sata@29000000 { + status = "ok"; + }; ++ ++ phy@100f8800 { /* USB3 port 1 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@100f8830 { /* USB3 port 1 SS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8800 { /* USB3 port 0 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8830 { /* USB3 port 0 SS phy */ ++ status = "ok"; ++ }; ++ ++ usb30@0 { ++ status = "ok"; ++ }; ++ ++ usb30@1 { ++ status = "ok"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -296,6 +296,91 @@ + compatible = "syscon"; + reg = <0x01200600 0x100>; + }; ++ ++ hs_phy_1: phy@100f8800 { ++ compatible = "qcom,dwc3-hs-usb-phy"; ++ reg = <0x100f8800 0x30>; ++ clocks = <&gcc USB30_1_UTMI_CLK>; ++ clock-names = "ref"; ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ ++ ss_phy_1: phy@100f8830 { ++ compatible = "qcom,dwc3-ss-usb-phy"; ++ reg = <0x100f8830 0x30>; ++ clocks = <&gcc USB30_1_MASTER_CLK>; ++ clock-names = "ref"; ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ ++ hs_phy_0: phy@110f8800 { ++ compatible = "qcom,dwc3-hs-usb-phy"; ++ reg = <0x110f8800 0x30>; ++ clocks = <&gcc USB30_0_UTMI_CLK>; ++ clock-names = "ref"; ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ ++ ss_phy_0: phy@110f8830 { ++ compatible = "qcom,dwc3-ss-usb-phy"; ++ reg = <0x110f8830 0x30>; ++ clocks = <&gcc USB30_0_MASTER_CLK>; ++ clock-names = "ref"; ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ ++ usb3_0: usb30@0 { ++ compatible = "qcom,dwc3"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&gcc USB30_0_MASTER_CLK>; ++ clock-names = "core"; ++ ++ ranges; ++ ++ status = "disabled"; ++ ++ dwc3@11000000 { ++ compatible = "snps,dwc3"; ++ reg = <0x11000000 0xcd00>; ++ interrupts = <0 110 0x4>; ++ phys = <&hs_phy_0>, <&ss_phy_0>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ tx-fifo-resize; ++ dr_mode = "host"; ++ }; ++ }; ++ ++ usb3_1: usb30@1 { ++ compatible = "qcom,dwc3"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ clocks = <&gcc USB30_1_MASTER_CLK>; ++ clock-names = "core"; ++ ++ ranges; ++ ++ status = "disabled"; ++ ++ dwc3@10000000 { ++ compatible = "snps,dwc3"; ++ reg = <0x10000000 0xcd00>; ++ interrupts = <0 205 0x4>; ++ phys = <&hs_phy_1>, <&ss_phy_1>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ tx-fifo-resize; ++ dr_mode = "host"; ++ }; ++ }; ++ + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-3.18/102-soc-qcom-gsbi-Add-support-for-ADM-CRCI-muxing.patch b/target/linux/ipq806x/patches-3.18/102-soc-qcom-gsbi-Add-support-for-ADM-CRCI-muxing.patch new file mode 100644 index 0000000..752f3f7 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/102-soc-qcom-gsbi-Add-support-for-ADM-CRCI-muxing.patch @@ -0,0 +1,249 @@ +--- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt ++++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt +@@ -6,7 +6,8 @@ configuration settings. The mode settin + the 4 GSBI IOs. + + Required properties: +-- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064 ++- compatible: Should contain "qcom,gsbi-v1.0.0" ++- cell-index: Should contain the GSBI index + - reg: Address range for GSBI registers + - clocks: required clock + - clock-names: must contain "iface" entry +@@ -16,6 +17,8 @@ Required properties: + Optional properties: + - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference + dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. ++- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses ++ dma. + + Required properties if child node exists: + - #address-cells: Must be 1 +@@ -39,6 +42,7 @@ Example for APQ8064: + + gsbi4@16300000 { + compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; +@@ -48,6 +52,8 @@ Example for APQ8064: + qcom,mode = ; + qcom,crci = ; + ++ syscon-tcsr = <&tcsr>; ++ + /* child nodes go under here */ + + i2c_qup4: i2c@16380000 { +@@ -76,3 +82,9 @@ Example for APQ8064: + }; + }; + ++ tcsr: syscon@1a400000 { ++ compatible = "qcom,apq8064-tcsr", "syscon"; ++ reg = <0x1a400000 0x100>; ++ }; ++ ++ +--- a/drivers/soc/qcom/Kconfig ++++ b/drivers/soc/qcom/Kconfig +@@ -4,6 +4,7 @@ + config QCOM_GSBI + tristate "QCOM General Serial Bus Interface" + depends on ARCH_QCOM ++ select MFD_SYSCON + help + Say y here to enable GSBI support. The GSBI provides control + functions for connecting the underlying serial UART, SPI, and I2C +--- a/drivers/soc/qcom/qcom_gsbi.c ++++ b/drivers/soc/qcom/qcom_gsbi.c +@@ -18,22 +18,129 @@ + #include + #include + #include ++#include ++#include ++#include + + #define GSBI_CTRL_REG 0x0000 + #define GSBI_PROTOCOL_SHIFT 4 ++#define MAX_GSBI 12 ++ ++#define TCSR_ADM_CRCI_BASE 0x70 ++ ++struct crci_config { ++ u32 num_rows; ++ const u32 (*array)[MAX_GSBI]; ++}; ++ ++static const u32 crci_ipq8064[][MAX_GSBI] = { ++ { ++ 0x000003, 0x00000c, 0x000030, 0x0000c0, ++ 0x000300, 0x000c00, 0x003000, 0x00c000, ++ 0x030000, 0x0c0000, 0x300000, 0xc00000 ++ }, ++ { ++ 0x000003, 0x00000c, 0x000030, 0x0000c0, ++ 0x000300, 0x000c00, 0x003000, 0x00c000, ++ 0x030000, 0x0c0000, 0x300000, 0xc00000 ++ }, ++}; ++ ++static const struct crci_config config_ipq8064 = { ++ .num_rows = ARRAY_SIZE(crci_ipq8064), ++ .array = crci_ipq8064, ++}; ++ ++static const unsigned int crci_apq8064[][MAX_GSBI] = { ++ { ++ 0x001800, 0x006000, 0x000030, 0x0000c0, ++ 0x000300, 0x000400, 0x000000, 0x000000, ++ 0x000000, 0x000000, 0x000000, 0x000000 ++ }, ++ { ++ 0x000000, 0x000000, 0x000000, 0x000000, ++ 0x000000, 0x000020, 0x0000c0, 0x000000, ++ 0x000000, 0x000000, 0x000000, 0x000000 ++ }, ++}; ++ ++static const struct crci_config config_apq8064 = { ++ .num_rows = ARRAY_SIZE(crci_apq8064), ++ .array = crci_apq8064, ++}; ++ ++static const unsigned int crci_msm8960[][MAX_GSBI] = { ++ { ++ 0x000003, 0x00000c, 0x000030, 0x0000c0, ++ 0x000300, 0x000400, 0x000000, 0x000000, ++ 0x000000, 0x000000, 0x000000, 0x000000 ++ }, ++ { ++ 0x000000, 0x000000, 0x000000, 0x000000, ++ 0x000000, 0x000020, 0x0000c0, 0x000300, ++ 0x001800, 0x006000, 0x000000, 0x000000 ++ }, ++}; ++ ++static const struct crci_config config_msm8960 = { ++ .num_rows = ARRAY_SIZE(crci_msm8960), ++ .array = crci_msm8960, ++}; ++ ++static const unsigned int crci_msm8660[][MAX_GSBI] = { ++ { /* ADM 0 - B */ ++ 0x000003, 0x00000c, 0x000030, 0x0000c0, ++ 0x000300, 0x000c00, 0x003000, 0x00c000, ++ 0x030000, 0x0c0000, 0x300000, 0xc00000 ++ }, ++ { /* ADM 0 - B */ ++ 0x000003, 0x00000c, 0x000030, 0x0000c0, ++ 0x000300, 0x000c00, 0x003000, 0x00c000, ++ 0x030000, 0x0c0000, 0x300000, 0xc00000 ++ }, ++ { /* ADM 1 - A */ ++ 0x000003, 0x00000c, 0x000030, 0x0000c0, ++ 0x000300, 0x000c00, 0x003000, 0x00c000, ++ 0x030000, 0x0c0000, 0x300000, 0xc00000 ++ }, ++ { /* ADM 1 - B */ ++ 0x000003, 0x00000c, 0x000030, 0x0000c0, ++ 0x000300, 0x000c00, 0x003000, 0x00c000, ++ 0x030000, 0x0c0000, 0x300000, 0xc00000 ++ }, ++}; ++ ++static const struct crci_config config_msm8660 = { ++ .num_rows = ARRAY_SIZE(crci_msm8660), ++ .array = crci_msm8660, ++}; + + struct gsbi_info { + struct clk *hclk; + u32 mode; + u32 crci; ++ struct regmap *tcsr; ++}; ++ ++static const struct of_device_id tcsr_dt_match[] = { ++ { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064}, ++ { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064}, ++ { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960}, ++ { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660}, ++ { }, + }; + + static int gsbi_probe(struct platform_device *pdev) + { + struct device_node *node = pdev->dev.of_node; ++ struct device_node *tcsr_node; ++ const struct of_device_id *match; + struct resource *res; + void __iomem *base; + struct gsbi_info *gsbi; ++ int i; ++ u32 mask, gsbi_num; ++ const struct crci_config *config = NULL; + + gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL); + +@@ -45,6 +152,32 @@ static int gsbi_probe(struct platform_de + if (IS_ERR(base)) + return PTR_ERR(base); + ++ /* get the tcsr node and setup the config and regmap */ ++ gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr"); ++ ++ if (!IS_ERR(gsbi->tcsr)) { ++ tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0); ++ if (tcsr_node) { ++ match = of_match_node(tcsr_dt_match, tcsr_node); ++ if (match) ++ config = match->data; ++ else ++ dev_warn(&pdev->dev, "no matching TCSR\n"); ++ ++ of_node_put(tcsr_node); ++ } ++ } ++ ++ if (of_property_read_u32(node, "cell-index", &gsbi_num)) { ++ dev_err(&pdev->dev, "missing cell-index\n"); ++ return -EINVAL; ++ } ++ ++ if (gsbi_num < 1 || gsbi_num > MAX_GSBI) { ++ dev_err(&pdev->dev, "invalid cell-index\n"); ++ return -EINVAL; ++ } ++ + if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) { + dev_err(&pdev->dev, "missing mode configuration\n"); + return -EINVAL; +@@ -64,6 +197,25 @@ static int gsbi_probe(struct platform_de + writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci, + base + GSBI_CTRL_REG); + ++ /* ++ * modify tcsr to reflect mode and ADM CRCI mux ++ * Each gsbi contains a pair of bits, one for RX and one for TX ++ * SPI mode requires both bits cleared, otherwise they are set ++ */ ++ if (config) { ++ for (i = 0; i < config->num_rows; i++) { ++ mask = config->array[i][gsbi_num - 1]; ++ ++ if (gsbi->mode == GSBI_PROT_SPI) ++ regmap_update_bits(gsbi->tcsr, ++ TCSR_ADM_CRCI_BASE + 4 * i, mask, 0); ++ else ++ regmap_update_bits(gsbi->tcsr, ++ TCSR_ADM_CRCI_BASE + 4 * i, mask, mask); ++ ++ } ++ } ++ + /* make sure the gsbi control write is not reordered */ + wmb(); + diff --git a/target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch b/target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch new file mode 100644 index 0000000..322e1d9 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch @@ -0,0 +1,65 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -132,6 +132,7 @@ + + gsbi2: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <2>; + reg = <0x12480000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; +@@ -140,6 +141,8 @@ + ranges; + status = "disabled"; + ++ syscon-tcsr = <&tcsr>; ++ + uart2: serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, +@@ -167,6 +170,7 @@ + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; +@@ -175,6 +179,8 @@ + ranges; + status = "disabled"; + ++ syscon-tcsr = <&tcsr>; ++ + uart4: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, +@@ -201,6 +207,7 @@ + + gsbi5: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <5>; + reg = <0x1a200000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; +@@ -209,6 +216,8 @@ + ranges; + status = "disabled"; + ++ syscon-tcsr = <&tcsr>; ++ + uart5: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, +@@ -279,6 +288,11 @@ + status = "disabled"; + }; + ++ tcsr: syscon@1a400000 { ++ compatible = "qcom,tcsr-ipq8064", "syscon"; ++ reg = <0x1a400000 0x100>; ++ }; ++ + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; diff --git a/target/linux/ipq806x/patches-3.18/110-DT-PCI-qcom-Document-PCIe-devicetree-bindings.patch b/target/linux/ipq806x/patches-3.18/110-DT-PCI-qcom-Document-PCIe-devicetree-bindings.patch new file mode 100644 index 0000000..41f91fa --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/110-DT-PCI-qcom-Document-PCIe-devicetree-bindings.patch @@ -0,0 +1,263 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,3/5] DT: PCI: qcom: Document PCIe devicetree bindings +From: Stanimir Varbanov +X-Patchwork-Id: 6326181 +Message-Id: <1430743338-10441-4-git-send-email-svarbanov@mm-sol.com> +To: Rob Herring , Kumar Gala , + Mark Rutland , + Grant Likely , + Bjorn Helgaas , + Kishon Vijay Abraham I , + Russell King , Arnd Bergmann +Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, + linux-pci@vger.kernel.org, Mathieu Olivari , + Srinivas Kandagatla , + Stanimir Varbanov +Date: Mon, 4 May 2015 15:42:16 +0300 + +Document Qualcomm PCIe driver devicetree bindings. + +Signed-off-by: Stanimir Varbanov + +--- +.../devicetree/bindings/pci/qcom,pcie.txt | 231 ++++++++++++++++++++ + 1 files changed, 231 insertions(+), 0 deletions(-) + create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt +@@ -0,0 +1,231 @@ ++* Qualcomm PCI express root complex ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: Value shall include ++ - "qcom,pcie-v0" for apq/ipq8064 ++ - "qcom,pcie-v1" for apq8084 ++ ++- reg: ++ Usage: required ++ Value type: ++ Definition: Register ranges as listed in the reg-names property ++ ++- reg-names: ++ Usage: required ++ Value type: ++ Definition: Must include the following entries ++ - "parf" Qualcomm specific registers ++ - "dbi" Designware PCIe registers ++ - "elbi" External local bus interface registers ++ - "config" PCIe configuration space ++ ++- device_type: ++ Usage: required ++ Value type: ++ Definition: Should be "pci". As specified in designware-pcie.txt ++ ++- #address-cells: ++ Usage: required ++ Value type: ++ Definition: Should be set to 3. As specified in designware-pcie.txt ++ ++- #size-cells: ++ Usage: required ++ Value type: ++ Definition: Should be set 2. As specified in designware-pcie.txt ++ ++- ranges: ++ Usage: required ++ Value type: ++ Definition: As specified in designware-pcie.txt ++ ++- interrupts: ++ Usage: required ++ Value type: ++ Definition: MSI interrupt ++ ++- interrupt-names: ++ Usage: required ++ Value type: ++ Definition: Should contain "msi" ++ ++- #interrupt-cells: ++ Usage: required ++ Value type: ++ Definition: Should be 1. As specified in designware-pcie.txt ++ ++- interrupt-map-mask: ++ Usage: required ++ Value type: ++ Definition: As specified in designware-pcie.txt ++ ++- interrupt-map: ++ Usage: required ++ Value type: ++ Definition: As specified in designware-pcie.txt ++ ++- clocks: ++ Usage: required ++ Value type: ++ Definition: List of phandle and clock specifier pairs as listed ++ in clock-names property ++ ++- clock-names: ++ Usage: required ++ Value type: ++ Definition: Should contain the following entries ++ * should be populated for v0 and v1 ++ - "iface" Configuration AHB clock ++ ++ * should be populated for v0 ++ - "core" Clocks the pcie hw block ++ - "phy" Clocks the pcie PHY block ++ ++ * should be populated for v1 ++ - "aux" Auxiliary (AUX) clock ++ - "bus_master" Master AXI clock ++ - "bus_slave" Slave AXI clock ++ ++- resets: ++ Usage: required ++ Value type: ++ Definition: List of phandle and reset specifier pairs as listed ++ in reset-names property ++ ++- reset-names: ++ Usage: required ++ Value type: ++ Definition: Should contain the following entries ++ * should be populated for v0 ++ - "axi" AXI reset ++ - "ahb" AHB reset ++ - "por" POR reset ++ - "pci" PCI reset ++ - "phy" PHY reset ++ ++ * should be populated for v1 ++ - "core" Core reset ++ ++- power-domains: ++ Usage: required (for v1 only) ++ Value type: ++ Definition: A phandle and power domain specifier pair to the ++ power domain which is responsible for collapsing ++ and restoring power to the peripheral ++ ++- -supply: ++ Usage: required ++ Value type: ++ Definition: List of phandles to the power supply regulator(s) ++ * should be populated for v0 and v1 ++ - "vdda" core analog power supply ++ ++ * should be populated for v0 ++ - "vdda_phy" analog power supply for PHY ++ - "vdda_refclk" analog power supply for IC which generate ++ reference clock ++ ++- phys: ++ Usage: required (for v1 only) ++ Value type: ++ Definition: List of phandle(s) as listed in phy-names property ++ ++- phy-names: ++ Usage: required (for v1 only) ++ Value type: ++ Definition: Should contain "pciephy" ++ ++- -gpio: ++ Usage: optional ++ Value type: ++ Definition: List of phandle and gpio specifier pairs. Should contain ++ - "perst" PCIe endpoint reset signal line ++ - "pewake" PCIe endpoint wake signal line ++ ++- pinctrl-0: ++ Usage: required ++ Value type: ++ Definition: List of phandles pointing at a pin(s) configuration ++ ++- pinctrl-names ++ Usage: required ++ Value type: ++ Definition: List of names of pinctrl-0 state ++ ++* Example for v0 ++ pcie0: pci@1b500000 { ++ compatible = "qcom,pcie-v0"; ++ reg = <0x1b500000 0x1000 ++ 0x1b502000 0x80 ++ 0x1b600000 0x100 ++ 0x0ff00000 0x100000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ ++ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* memory */ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ clocks = <&gcc PCIE_A_CLK>, ++ <&gcc PCIE_H_CLK>, ++ <&gcc PCIE_PHY_CLK>; ++ clock-names = "core", "iface", "phy"; ++ resets = <&gcc PCIE_ACLK_RESET>, ++ <&gcc PCIE_HCLK_RESET>, ++ <&gcc PCIE_POR_RESET>, ++ <&gcc PCIE_PCI_RESET>, ++ <&gcc PCIE_PHY_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy"; ++ }; ++ ++* Example for v1 ++ pcie0@fc520000 { ++ compatible = "qcom,pcie-v1"; ++ reg = <0xfc520000 0x2000>, ++ <0xff000000 0x1000>, ++ <0xff001000 0x1000>, ++ <0xff002000 0x2000>; ++ reg-names = "parf", "dbi", "elbi", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ ++ 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, ++ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, ++ <&gcc GCC_PCIE_0_SLV_AXI_CLK>, ++ <&gcc GCC_PCIE_0_AUX_CLK>; ++ clock-names = "iface", "master_bus", "slave_bus", "aux"; ++ resets = <&gcc GCC_PCIE_0_BCR>; ++ reset-names = "core"; ++ power-domains = <&gcc PCIE0_GDSC>; ++ vdda-supply = <&pma8084_l3>; ++ phys = <&pciephy0>; ++ phy-names = "pciephy"; ++ perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&pcie0_pins_default>; ++ pinctrl-names = "default"; ++ }; diff --git a/target/linux/ipq806x/patches-3.18/111-PCI-qcom-Add-Qualcomm-PCIe-controller-driver.patch b/target/linux/ipq806x/patches-3.18/111-PCI-qcom-Add-Qualcomm-PCIe-controller-driver.patch new file mode 100644 index 0000000..a0c9c7c --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/111-PCI-qcom-Add-Qualcomm-PCIe-controller-driver.patch @@ -0,0 +1,753 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,4/5] PCI: qcom: Add Qualcomm PCIe controller driver +From: Stanimir Varbanov +X-Patchwork-Id: 6326161 +Message-Id: <1430743338-10441-5-git-send-email-svarbanov@mm-sol.com> +To: Rob Herring , Kumar Gala , + Mark Rutland , + Grant Likely , + Bjorn Helgaas , + Kishon Vijay Abraham I , + Russell King , Arnd Bergmann +Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, + linux-pci@vger.kernel.org, Mathieu Olivari , + Srinivas Kandagatla , + Stanimir Varbanov +Date: Mon, 4 May 2015 15:42:17 +0300 + +The PCIe driver reuse the Designware common code for host +and MSI initialization, and also program the Qualcomm +application specific registers. + +Signed-off-by: Stanimir Varbanov + +--- +MAINTAINERS | 7 + + drivers/pci/host/Kconfig | 9 + + drivers/pci/host/Makefile | 1 + + drivers/pci/host/pcie-qcom.c | 677 ++++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 694 insertions(+), 0 deletions(-) + create mode 100644 drivers/pci/host/pcie-qcom.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -7127,6 +7127,13 @@ L: linux-pci@vger.kernel.org + S: Maintained + F: drivers/pci/host/*spear* + ++PCIE DRIVER FOR QUALCOMM MSM ++M: Stanimir Varbanov ++L: linux-pci@vger.kernel.org ++L: linux-arm-msm@vger.kernel.org ++S: Maintained ++F: drivers/pci/host/*qcom* ++ + PCMCIA SUBSYSTEM + P: Linux PCMCIA Team + L: linux-pcmcia@lists.infradead.org +--- a/drivers/pci/host/Kconfig ++++ b/drivers/pci/host/Kconfig +@@ -91,4 +91,13 @@ config PCI_XGENE + There are 5 internal PCIe ports available. Each port is GEN3 capable + and have varied lanes from x1 to x8. + ++config PCIE_QCOM ++ bool "Qualcomm PCIe controller" ++ depends on ARCH_QCOM && OF || (ARM && COMPILE_TEST) ++ select PCIE_DW ++ select PCIEPORTBUS ++ help ++ Say Y here to enable PCIe controller support on Qualcomm SoCs. The ++ PCIe controller use Designware core plus Qualcomm specific hardware ++ wrappers. + endmenu +--- /dev/null ++++ b/drivers/pci/host/pcie-qcom.c +@@ -0,0 +1,677 @@ ++/* ++ * Copyright (c) 2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-designware.h" ++ ++#define PCIE20_PARF_PHY_CTRL 0x40 ++#define PCIE20_PARF_PHY_REFCLK 0x4C ++#define PCIE20_PARF_DBI_BASE_ADDR 0x168 ++#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c ++#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 ++ ++#define PCIE20_ELBI_SYS_CTRL 0x04 ++#define PCIE20_ELBI_SYS_STTS 0x08 ++#define XMLH_LINK_UP BIT(10) ++ ++#define PCIE20_CAP 0x70 ++#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) ++ ++#define PERST_DELAY_MIN_US 1000 ++#define PERST_DELAY_MAX_US 1005 ++ ++#define LINKUP_DELAY_MIN_US 5000 ++#define LINKUP_DELAY_MAX_US 5100 ++#define LINKUP_RETRIES_COUNT 20 ++ ++#define PCIE_V0 0 /* apq8064 */ ++#define PCIE_V1 1 /* apq8084 */ ++ ++struct qcom_pcie_resources_v0 { ++ struct clk *iface_clk; ++ struct clk *core_clk; ++ struct clk *phy_clk; ++ struct reset_control *pci_reset; ++ struct reset_control *axi_reset; ++ struct reset_control *ahb_reset; ++ struct reset_control *por_reset; ++ struct reset_control *phy_reset; ++ struct regulator *vdda; ++ struct regulator *vdda_phy; ++ struct regulator *vdda_refclk; ++}; ++ ++struct qcom_pcie_resources_v1 { ++ struct clk *iface; ++ struct clk *aux; ++ struct clk *master_bus; ++ struct clk *slave_bus; ++ struct reset_control *core; ++ struct regulator *vdda; ++}; ++ ++union pcie_resources { ++ struct qcom_pcie_resources_v0 v0; ++ struct qcom_pcie_resources_v1 v1; ++}; ++ ++struct qcom_pcie { ++ struct pcie_port pp; ++ struct device *dev; ++ union pcie_resources res; ++ void __iomem *parf; ++ void __iomem *dbi; ++ void __iomem *elbi; ++ struct phy *phy; ++ struct gpio_desc *reset; ++ unsigned int version; ++}; ++ ++#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp) ++ ++static inline void ++writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask) ++{ ++ u32 val = readl(addr); ++ ++ val &= ~clear_mask; ++ val |= set_mask; ++ writel(val, addr); ++} ++ ++static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert) ++{ ++ int val, active_low; ++ ++ if (IS_ERR_OR_NULL(pcie->reset)) ++ return; ++ ++ active_low = gpiod_is_active_low(pcie->reset); ++ ++ if (assert) ++ val = !!active_low; ++ else ++ val = !active_low; ++ ++ gpiod_set_value(pcie->reset, val); ++ ++ usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US); ++} ++ ++static void qcom_ep_reset_assert(struct qcom_pcie *pcie) ++{ ++ qcom_ep_reset_assert_deassert(pcie, 1); ++} ++ ++static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) ++{ ++ qcom_ep_reset_assert_deassert(pcie, 0); ++} ++ ++static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg) ++{ ++ struct pcie_port *pp = arg; ++ ++ return dw_handle_msi_irq(pp); ++} ++ ++static int qcom_pcie_link_up(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ u32 val = readl(pcie->dbi + PCIE20_CAP_LINKCTRLSTATUS); ++ ++ return val & BIT(29) ? 1 : 0; ++} ++ ++static void qcom_pcie_disable_resources_v0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v0 *res = &pcie->res.v0; ++ ++ reset_control_assert(res->pci_reset); ++ reset_control_assert(res->axi_reset); ++ reset_control_assert(res->ahb_reset); ++ reset_control_assert(res->por_reset); ++ reset_control_assert(res->pci_reset); ++ clk_disable_unprepare(res->iface_clk); ++ clk_disable_unprepare(res->core_clk); ++ clk_disable_unprepare(res->phy_clk); ++ regulator_disable(res->vdda); ++ regulator_disable(res->vdda_phy); ++ regulator_disable(res->vdda_refclk); ++} ++ ++static void qcom_pcie_disable_resources_v1(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v1 *res = &pcie->res.v1; ++ ++ reset_control_assert(res->core); ++ clk_disable_unprepare(res->slave_bus); ++ clk_disable_unprepare(res->master_bus); ++ clk_disable_unprepare(res->iface); ++ clk_disable_unprepare(res->aux); ++ regulator_disable(res->vdda); ++} ++ ++static int qcom_pcie_enable_resources_v0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v0 *res = &pcie->res.v0; ++ struct device *dev = pcie->dev; ++ int ret; ++ ++ ret = regulator_enable(res->vdda); ++ if (ret) { ++ dev_err(dev, "cannot enable vdda regulator\n"); ++ return ret; ++ } ++ ++ ret = regulator_enable(res->vdda_refclk); ++ if (ret) { ++ dev_err(dev, "cannot enable vdda_refclk regulator\n"); ++ goto err_refclk; ++ } ++ ++ ret = regulator_enable(res->vdda_phy); ++ if (ret) { ++ dev_err(dev, "cannot enable vdda_phy regulator\n"); ++ goto err_vdda_phy; ++ } ++ ++ ret = clk_prepare_enable(res->iface_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable iface clock\n"); ++ goto err_iface; ++ } ++ ++ ret = clk_prepare_enable(res->core_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable core clock\n"); ++ goto err_clk_core; ++ } ++ ++ ret = clk_prepare_enable(res->phy_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable phy clock\n"); ++ goto err_clk_phy; ++ } ++ ++ ret = reset_control_deassert(res->ahb_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert ahb reset\n"); ++ goto err_reset_ahb; ++ } ++ ++ return 0; ++ ++err_reset_ahb: ++ clk_disable_unprepare(res->phy_clk); ++err_clk_phy: ++ clk_disable_unprepare(res->core_clk); ++err_clk_core: ++ clk_disable_unprepare(res->iface_clk); ++err_iface: ++ regulator_disable(res->vdda_phy); ++err_vdda_phy: ++ regulator_disable(res->vdda_refclk); ++err_refclk: ++ regulator_disable(res->vdda); ++ return ret; ++} ++ ++static int qcom_pcie_enable_resources_v1(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v1 *res = &pcie->res.v1; ++ struct device *dev = pcie->dev; ++ int ret; ++ ++ ret = reset_control_deassert(res->core); ++ if (ret) { ++ dev_err(dev, "cannot deassert core reset\n"); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(res->aux); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable aux clock\n"); ++ goto err_res; ++ } ++ ++ ret = clk_prepare_enable(res->iface); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable iface clock\n"); ++ goto err_aux; ++ } ++ ++ ret = clk_prepare_enable(res->master_bus); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable master_bus clock\n"); ++ goto err_iface; ++ } ++ ++ ret = clk_prepare_enable(res->slave_bus); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable slave_bus clock\n"); ++ goto err_master; ++ } ++ ++ ret = regulator_enable(res->vdda); ++ if (ret) { ++ dev_err(dev, "cannot enable vdda regulator\n"); ++ goto err_slave; ++ } ++ ++ return 0; ++ ++err_slave: ++ clk_disable_unprepare(res->slave_bus); ++err_master: ++ clk_disable_unprepare(res->master_bus); ++err_iface: ++ clk_disable_unprepare(res->iface); ++err_aux: ++ clk_disable_unprepare(res->aux); ++err_res: ++ reset_control_assert(res->core); ++ ++ return ret; ++} ++ ++static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v0 *res = &pcie->res.v0; ++ struct device *dev = pcie->dev; ++ ++ res->vdda = devm_regulator_get(dev, "vdda"); ++ if (IS_ERR(res->vdda)) ++ return PTR_ERR(res->vdda); ++ ++ res->vdda_phy = devm_regulator_get(dev, "vdda_phy"); ++ if (IS_ERR(res->vdda_phy)) ++ return PTR_ERR(res->vdda_phy); ++ ++ res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk"); ++ if (IS_ERR(res->vdda_refclk)) ++ return PTR_ERR(res->vdda_refclk); ++ ++ res->iface_clk = devm_clk_get(dev, "iface"); ++ if (IS_ERR(res->iface_clk)) ++ return PTR_ERR(res->iface_clk); ++ ++ res->core_clk = devm_clk_get(dev, "core"); ++ if (IS_ERR(res->core_clk)) ++ return PTR_ERR(res->core_clk); ++ ++ res->phy_clk = devm_clk_get(dev, "phy"); ++ if (IS_ERR(res->phy_clk)) ++ return PTR_ERR(res->phy_clk); ++ ++ res->pci_reset = devm_reset_control_get(dev, "pci"); ++ if (IS_ERR(res->pci_reset)) ++ return PTR_ERR(res->pci_reset); ++ ++ res->axi_reset = devm_reset_control_get(dev, "axi"); ++ if (IS_ERR(res->axi_reset)) ++ return PTR_ERR(res->axi_reset); ++ ++ res->ahb_reset = devm_reset_control_get(dev, "ahb"); ++ if (IS_ERR(res->ahb_reset)) ++ return PTR_ERR(res->ahb_reset); ++ ++ res->por_reset = devm_reset_control_get(dev, "por"); ++ if (IS_ERR(res->por_reset)) ++ return PTR_ERR(res->por_reset); ++ ++ res->phy_reset = devm_reset_control_get(dev, "phy"); ++ if (IS_ERR(res->phy_reset)) ++ return PTR_ERR(res->phy_reset); ++ ++ return 0; ++} ++ ++static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v1 *res = &pcie->res.v1; ++ struct device *dev = pcie->dev; ++ ++ res->vdda = devm_regulator_get(dev, "vdda"); ++ if (IS_ERR(res->vdda)) ++ return PTR_ERR(res->vdda); ++ ++ res->iface = devm_clk_get(dev, "iface"); ++ if (IS_ERR(res->iface)) ++ return PTR_ERR(res->iface); ++ ++ res->aux = devm_clk_get(dev, "aux"); ++ if (IS_ERR(res->aux) && PTR_ERR(res->aux) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ else if (IS_ERR(res->aux)) ++ res->aux = NULL; ++ ++ res->master_bus = devm_clk_get(dev, "master_bus"); ++ if (IS_ERR(res->master_bus)) ++ return PTR_ERR(res->master_bus); ++ ++ res->slave_bus = devm_clk_get(dev, "slave_bus"); ++ if (IS_ERR(res->slave_bus)) ++ return PTR_ERR(res->slave_bus); ++ ++ res->core = devm_reset_control_get(dev, "core"); ++ if (IS_ERR(res->core)) ++ return PTR_ERR(res->core); ++ ++ return 0; ++} ++ ++static int qcom_pcie_enable_link_training(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ struct device *dev = pp->dev; ++ int retries; ++ u32 val; ++ ++ /* enable link training */ ++ writel_masked(pcie->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0)); ++ ++ /* wait for up to 100ms for the link to come up */ ++ retries = LINKUP_RETRIES_COUNT; ++ do { ++ val = readl(pcie->elbi + PCIE20_ELBI_SYS_STTS); ++ if (val & XMLH_LINK_UP) ++ break; ++ usleep_range(LINKUP_DELAY_MIN_US, LINKUP_DELAY_MAX_US); ++ } while (retries--); ++ ++ if (retries < 0 || !dw_pcie_link_up(pp)) { ++ dev_err(dev, "link initialization failed\n"); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static void qcom_pcie_host_init_v1(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ int ret; ++ ++ qcom_ep_reset_assert(pcie); ++ ++ ret = qcom_pcie_enable_resources_v1(pcie); ++ if (ret) ++ return; ++ ++ /* change DBI base address */ ++ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) ++ writel_masked(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT, ++ 0, BIT(31)); ++ ++ ret = phy_init(pcie->phy); ++ if (ret) ++ goto err_res; ++ ++ ret = phy_power_on(pcie->phy); ++ if (ret) ++ goto err_phy; ++ ++ dw_pcie_setup_rc(pp); ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) ++ dw_pcie_msi_init(pp); ++ ++ qcom_ep_reset_deassert(pcie); ++ ++ ret = qcom_pcie_enable_link_training(pp); ++ if (ret) ++ goto err; ++ ++ return; ++ ++err: ++ qcom_ep_reset_assert(pcie); ++ phy_power_off(pcie->phy); ++err_phy: ++ phy_exit(pcie->phy); ++err_res: ++ qcom_pcie_disable_resources_v1(pcie); ++} ++ ++static void qcom_pcie_host_init_v0(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ struct qcom_pcie_resources_v0 *res = &pcie->res.v0; ++ struct device *dev = pcie->dev; ++ int ret; ++ ++ qcom_ep_reset_assert(pcie); ++ ++ ret = qcom_pcie_enable_resources_v0(pcie); ++ if (ret) ++ return; ++ ++ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); ++ ++ /* enable external reference clock */ ++ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16)); ++ ++ ret = reset_control_deassert(res->phy_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert phy reset\n"); ++ return; ++ } ++ ++ ret = reset_control_deassert(res->pci_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert pci reset\n"); ++ return; ++ } ++ ++ ret = reset_control_deassert(res->por_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert por reset\n"); ++ return; ++ } ++ ++ ret = reset_control_deassert(res->axi_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert axi reset\n"); ++ return; ++ } ++ ++ /* wait 150ms for clock acquisition */ ++ usleep_range(10000, 15000); ++ ++ dw_pcie_setup_rc(pp); ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) ++ dw_pcie_msi_init(pp); ++ ++ qcom_ep_reset_deassert(pcie); ++ ++ ret = qcom_pcie_enable_link_training(pp); ++ if (ret) ++ goto err; ++ ++ return; ++err: ++ qcom_ep_reset_assert(pcie); ++ qcom_pcie_disable_resources_v0(pcie); ++} ++ ++static void qcom_pcie_host_init(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ ++ if (pcie->version == PCIE_V0) ++ return qcom_pcie_host_init_v0(pp); ++ else ++ return qcom_pcie_host_init_v1(pp); ++} ++ ++static int ++qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val) ++{ ++ /* the device class is not reported correctly from the register */ ++ if (where == PCI_CLASS_REVISION && size == 4) { ++ *val = readl(pp->dbi_base + PCI_CLASS_REVISION); ++ *val &= ~(0xffff << 16); ++ *val |= PCI_CLASS_BRIDGE_PCI << 16; ++ return PCIBIOS_SUCCESSFUL; ++ } ++ ++ return dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, ++ size, val); ++} ++ ++static struct pcie_host_ops qcom_pcie_ops = { ++ .link_up = qcom_pcie_link_up, ++ .host_init = qcom_pcie_host_init, ++ .rd_own_conf = qcom_pcie_rd_own_conf, ++}; ++ ++static const struct of_device_id qcom_pcie_match[] = { ++ { .compatible = "qcom,pcie-v0", .data = (void *)PCIE_V0 }, ++ { .compatible = "qcom,pcie-v1", .data = (void *)PCIE_V1 }, ++ { } ++}; ++ ++static int qcom_pcie_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ const struct of_device_id *match; ++ struct resource *res; ++ struct qcom_pcie *pcie; ++ struct pcie_port *pp; ++ int ret; ++ ++ match = of_match_node(qcom_pcie_match, dev->of_node); ++ if (!match) ++ return -ENXIO; ++ ++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) ++ return -ENOMEM; ++ ++ pcie->version = (unsigned int)match->data; ++ ++ pcie->reset = devm_gpiod_get_optional(dev, "perst"); ++ if (IS_ERR(pcie->reset) && PTR_ERR(pcie->reset) == -EPROBE_DEFER) ++ return PTR_ERR(pcie->reset); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); ++ pcie->parf = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pcie->parf)) ++ return PTR_ERR(pcie->parf); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); ++ pcie->dbi = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pcie->dbi)) ++ return PTR_ERR(pcie->dbi); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); ++ pcie->elbi = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pcie->elbi)) ++ return PTR_ERR(pcie->elbi); ++ ++ pcie->phy = devm_phy_optional_get(dev, "pciephy"); ++ if (IS_ERR(pcie->phy)) ++ return PTR_ERR(pcie->phy); ++ ++ pcie->dev = dev; ++ ++ if (pcie->version == PCIE_V0) ++ ret = qcom_pcie_get_resources_v0(pcie); ++ else ++ ret = qcom_pcie_get_resources_v1(pcie); ++ ++ if (ret) ++ return ret; ++ ++ pp = &pcie->pp; ++ pp->dev = dev; ++ pp->dbi_base = pcie->dbi; ++ pp->root_bus_nr = -1; ++ pp->ops = &qcom_pcie_ops; ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) { ++ pp->msi_irq = platform_get_irq_byname(pdev, "msi"); ++ if (pp->msi_irq < 0) { ++ dev_err(dev, "cannot get msi irq\n"); ++ return pp->msi_irq; ++ } ++ ++ ret = devm_request_irq(dev, pp->msi_irq, ++ qcom_pcie_msi_irq_handler, ++ IRQF_SHARED, "qcom-pcie-msi", pp); ++ if (ret) { ++ dev_err(dev, "cannot request msi irq\n"); ++ return ret; ++ } ++ } ++ ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(dev, "cannot initialize host\n"); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, pcie); ++ ++ return 0; ++} ++ ++static int qcom_pcie_remove(struct platform_device *pdev) ++{ ++ struct qcom_pcie *pcie = platform_get_drvdata(pdev); ++ ++ qcom_ep_reset_assert(pcie); ++ phy_power_off(pcie->phy); ++ phy_exit(pcie->phy); ++ if (pcie->version == PCIE_V0) ++ qcom_pcie_disable_resources_v0(pcie); ++ else ++ qcom_pcie_disable_resources_v1(pcie); ++ ++ return 0; ++} ++ ++static struct platform_driver qcom_pcie_driver = { ++ .probe = qcom_pcie_probe, ++ .remove = qcom_pcie_remove, ++ .driver = { ++ .name = "qcom-pcie", ++ .of_match_table = qcom_pcie_match, ++ }, ++}; ++ ++module_platform_driver(qcom_pcie_driver); ++ ++MODULE_AUTHOR("Stanimir Varbanov "); ++MODULE_DESCRIPTION("Qualcomm PCIe root complex driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:qcom-pcie"); +--- a/drivers/pci/host/Makefile ++++ b/drivers/pci/host/Makefile +@@ -11,3 +11,4 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spe + obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o + obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o + obj-$(CONFIG_PCI_XGENE) += pci-xgene.o ++obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o diff --git a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch new file mode 100644 index 0000000..d15f0ac --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch @@ -0,0 +1,266 @@ +From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Tue, 21 Apr 2015 19:01:42 -0700 +Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms + +qcom-pcie driver now supports version 0 of the controller. This change +adds the corresponding entries to the IPQ806x dtsi file and +corresponding platform (AP148). + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++ + arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++ + 2 files changed, 154 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -35,6 +35,24 @@ + bias-disable; + }; + ++ pcie0_pins: pcie0_pinmux { ++ mux { ++ pins = "gpio3"; ++ function = "pcie1_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ pcie1_pins: pcie1_pinmux { ++ mux { ++ pins = "gpio48"; ++ function = "pcie2_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; +@@ -115,5 +133,19 @@ + usb30@1 { + status = "ok"; + }; ++ ++ pcie0: pci@1b500000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 3 0>; ++ pinctrl-0 = <&pcie0_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ pcie1: pci@1b700000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 48 0>; ++ pinctrl-0 = <&pcie1_pins>; ++ pinctrl-names = "default"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts +@@ -30,6 +30,33 @@ + bias-disable; + }; + ++ pcie0_pins: pcie0_pinmux { ++ mux { ++ pins = "gpio3"; ++ function = "pcie1_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ pcie1_pins: pcie1_pinmux { ++ mux { ++ pins = "gpio48"; ++ function = "pcie2_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ pcie2_pins: pcie2_pinmux { ++ mux { ++ pins = "gpio63"; ++ function = "pcie3_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; +@@ -128,5 +155,26 @@ + usb30@1 { + status = "ok"; + }; ++ ++ pcie0: pci@1b500000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 3 0>; ++ pinctrl-0 = <&pcie0_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ pcie1: pci@1b700000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 48 0>; ++ pinctrl-0 = <&pcie1_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ pcie2: pci@1b900000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 63 0>; ++ pinctrl-0 = <&pcie2_pins>; ++ pinctrl-names = "default"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -3,6 +3,8 @@ + #include "skeleton.dtsi" + #include + #include ++#include ++#include + + / { + model = "Qualcomm IPQ8064"; +@@ -311,6 +313,129 @@ + reg = <0x01200600 0x100>; + }; + ++ pcie0: pci@1b500000 { ++ compatible = "qcom,pcie-v0"; ++ reg = <0x1b500000 0x1000 ++ 0x1b502000 0x80 ++ 0x1b600000 0x100 ++ 0x0ff00000 0x100000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */ ++ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ ++ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ ++ clocks = <&gcc PCIE_A_CLK>, ++ <&gcc PCIE_H_CLK>, ++ <&gcc PCIE_PHY_CLK>; ++ clock-names = "core", "iface", "phy"; ++ ++ resets = <&gcc PCIE_ACLK_RESET>, ++ <&gcc PCIE_HCLK_RESET>, ++ <&gcc PCIE_POR_RESET>, ++ <&gcc PCIE_PCI_RESET>, ++ <&gcc PCIE_PHY_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy"; ++ ++ status = "disabled"; ++ }; ++ ++ pcie1: pci@1b700000 { ++ compatible = "qcom,pcie-v0"; ++ reg = <0x1b700000 0x1000 ++ 0x1b702000 0x80 ++ 0x1b800000 0x100 ++ 0x31f00000 0x100000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <1>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */ ++ 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ ++ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ ++ clocks = <&gcc PCIE_1_A_CLK>, ++ <&gcc PCIE_1_H_CLK>, ++ <&gcc PCIE_1_PHY_CLK>; ++ clock-names = "core", "iface", "phy"; ++ ++ resets = <&gcc PCIE_1_ACLK_RESET>, ++ <&gcc PCIE_1_HCLK_RESET>, ++ <&gcc PCIE_1_POR_RESET>, ++ <&gcc PCIE_1_PCI_RESET>, ++ <&gcc PCIE_1_PHY_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy"; ++ ++ status = "disabled"; ++ }; ++ ++ pcie2: pci@1b900000 { ++ compatible = "qcom,pcie-v0"; ++ reg = <0x1b900000 0x1000 ++ 0x1b902000 0x80 ++ 0x1ba00000 0x100 ++ 0x35f00000 0x100000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x81000000 0 0 0x35e00000 0 0x00100000 /* downstream I/O */ ++ 0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ ++ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ ++ clocks = <&gcc PCIE_2_A_CLK>, ++ <&gcc PCIE_2_H_CLK>, ++ <&gcc PCIE_2_PHY_CLK>; ++ clock-names = "core", "iface", "phy"; ++ ++ resets = <&gcc PCIE_2_ACLK_RESET>, ++ <&gcc PCIE_2_HCLK_RESET>, ++ <&gcc PCIE_2_POR_RESET>, ++ <&gcc PCIE_2_PCI_RESET>, ++ <&gcc PCIE_2_PHY_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy"; ++ ++ status = "disabled"; ++ }; ++ + hs_phy_1: phy@100f8800 { + compatible = "qcom,dwc3-hs-usb-phy"; + reg = <0x100f8800 0x30>; diff --git a/target/linux/ipq806x/patches-3.18/113-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch b/target/linux/ipq806x/patches-3.18/113-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch new file mode 100644 index 0000000..4f0e45f --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/113-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch @@ -0,0 +1,29 @@ +From f004aa1dec6e2e206be025de15b115d60f2b21e3 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Tue, 21 Apr 2015 19:09:07 -0700 +Subject: [PATCH 9/9] ARM: qcom: automatically select PCI_DOMAINS if PCI is + enabled + +If multiple PCIe devices are present in the system, the kernel will +panic at boot time when trying to scan the PCI buses. This happens on +IPQ806x based platforms, which has 3 PCIe ports. + +Enabling this option allows the kernel to assign the pci-domains +according to the device-tree content. This allows multiple PCIe +controllers to coexist in the system. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/mach-qcom/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-qcom/Kconfig ++++ b/arch/arm/mach-qcom/Kconfig +@@ -6,6 +6,7 @@ menuconfig ARCH_QCOM + select CLKSRC_OF + select PINCTRL + select QCOM_SCM if SMP ++ select PCI_DOMAINS if PCI + help + Support for Qualcomm's devicetree based systems. + diff --git a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch new file mode 100644 index 0000000..11c9810 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch @@ -0,0 +1,278 @@ +--- a/drivers/pci/host/pcie-qcom.c ++++ b/drivers/pci/host/pcie-qcom.c +@@ -29,8 +29,53 @@ + + #include "pcie-designware.h" + ++/* DBI registers */ ++#define PCIE20_CAP 0x70 ++#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) ++ ++#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 ++#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c ++ ++#define PCIE20_PLR_IATU_VIEWPORT 0x900 ++#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31) ++#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0) ++ ++#define PCIE20_PLR_IATU_CTRL1 0x904 ++#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0) ++#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0) ++ ++#define PCIE20_PLR_IATU_CTRL2 0x908 ++#define PCIE20_PLR_IATU_ENABLE BIT(31) ++ ++#define PCIE20_PLR_IATU_LBAR 0x90C ++#define PCIE20_PLR_IATU_UBAR 0x910 ++#define PCIE20_PLR_IATU_LAR 0x914 ++#define PCIE20_PLR_IATU_LTAR 0x918 ++#define PCIE20_PLR_IATU_UTAR 0x91c ++ ++#define MSM_PCIE_DEV_CFG_ADDR 0x01000000 ++ ++/* PARF registers */ ++#define PCIE20_PARF_PCS_DEEMPH 0x34 ++#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16) ++#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8) ++#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0) ++ ++#define PCIE20_PARF_PCS_SWING 0x38 ++#define PCS_SWING_TX_SWING_FULL(x) (x << 8) ++#define PCS_SWING_TX_SWING_LOW(x) (x << 0) ++ + #define PCIE20_PARF_PHY_CTRL 0x40 ++#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16) ++#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16) ++ + #define PCIE20_PARF_PHY_REFCLK 0x4C ++#define REF_SSP_EN BIT(16) ++#define REF_USE_PAD BIT(12) ++ ++#define PCIE20_PARF_CONFIG_BITS 0x50 ++#define PHY_RX0_EQ(x) (x << 24) ++ + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 + #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c + #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +@@ -39,9 +84,6 @@ + #define PCIE20_ELBI_SYS_STTS 0x08 + #define XMLH_LINK_UP BIT(10) + +-#define PCIE20_CAP 0x70 +-#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) +- + #define PERST_DELAY_MIN_US 1000 + #define PERST_DELAY_MAX_US 1005 + +@@ -56,14 +98,18 @@ struct qcom_pcie_resources_v0 { + struct clk *iface_clk; + struct clk *core_clk; + struct clk *phy_clk; ++ struct clk *aux_clk; ++ struct clk *ref_clk; + struct reset_control *pci_reset; + struct reset_control *axi_reset; + struct reset_control *ahb_reset; + struct reset_control *por_reset; + struct reset_control *phy_reset; ++ struct reset_control *ext_reset; + struct regulator *vdda; + struct regulator *vdda_phy; + struct regulator *vdda_refclk; ++ uint8_t phy_tx0_term_offset; + }; + + struct qcom_pcie_resources_v1 { +@@ -156,10 +202,13 @@ static void qcom_pcie_disable_resources_ + reset_control_assert(res->axi_reset); + reset_control_assert(res->ahb_reset); + reset_control_assert(res->por_reset); +- reset_control_assert(res->pci_reset); ++ reset_control_assert(res->phy_reset); ++ reset_control_assert(res->ext_reset); + clk_disable_unprepare(res->iface_clk); + clk_disable_unprepare(res->core_clk); + clk_disable_unprepare(res->phy_clk); ++ clk_disable_unprepare(res->aux_clk); ++ clk_disable_unprepare(res->ref_clk); + regulator_disable(res->vdda); + regulator_disable(res->vdda_phy); + regulator_disable(res->vdda_refclk); +@@ -201,6 +250,12 @@ static int qcom_pcie_enable_resources_v0 + goto err_vdda_phy; + } + ++ ret = reset_control_deassert(res->ext_reset); ++ if (ret) { ++ dev_err(dev, "cannot assert ext reset\n"); ++ goto err_reset_ext; ++ } ++ + ret = clk_prepare_enable(res->iface_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable iface clock\n"); +@@ -219,6 +274,18 @@ static int qcom_pcie_enable_resources_v0 + goto err_clk_phy; + } + ++ ret = clk_prepare_enable(res->aux_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable aux clock\n"); ++ goto err_clk_aux; ++ } ++ ++ ret = clk_prepare_enable(res->ref_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable ref clock\n"); ++ goto err_clk_ref; ++ } ++ + ret = reset_control_deassert(res->ahb_reset); + if (ret) { + dev_err(dev, "cannot deassert ahb reset\n"); +@@ -228,12 +295,18 @@ static int qcom_pcie_enable_resources_v0 + return 0; + + err_reset_ahb: ++ clk_disable_unprepare(res->ref_clk); ++err_clk_ref: ++ clk_disable_unprepare(res->aux_clk); ++err_clk_aux: + clk_disable_unprepare(res->phy_clk); + err_clk_phy: + clk_disable_unprepare(res->core_clk); + err_clk_core: + clk_disable_unprepare(res->iface_clk); + err_iface: ++ reset_control_assert(res->ext_reset); ++err_reset_ext: + regulator_disable(res->vdda_phy); + err_vdda_phy: + regulator_disable(res->vdda_refclk); +@@ -329,6 +402,14 @@ static int qcom_pcie_get_resources_v0(st + if (IS_ERR(res->phy_clk)) + return PTR_ERR(res->phy_clk); + ++ res->aux_clk = devm_clk_get(dev, "aux"); ++ if (IS_ERR(res->aux_clk)) ++ return PTR_ERR(res->aux_clk); ++ ++ res->ref_clk = devm_clk_get(dev, "ref"); ++ if (IS_ERR(res->ref_clk)) ++ return PTR_ERR(res->ref_clk); ++ + res->pci_reset = devm_reset_control_get(dev, "pci"); + if (IS_ERR(res->pci_reset)) + return PTR_ERR(res->pci_reset); +@@ -349,6 +430,14 @@ static int qcom_pcie_get_resources_v0(st + if (IS_ERR(res->phy_reset)) + return PTR_ERR(res->phy_reset); + ++ res->ext_reset = devm_reset_control_get(dev, "ext"); ++ if (IS_ERR(res->ext_reset)) ++ return PTR_ERR(res->ext_reset); ++ ++ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset", ++ &res->phy_tx0_term_offset)) ++ res->phy_tx0_term_offset = 0; ++ + return 0; + } + +@@ -461,6 +550,57 @@ err_res: + qcom_pcie_disable_resources_v1(pcie); + } + ++static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev) ++{ ++ struct pcie_port *pp = &pcie->pp; ++ ++ /* ++ * program and enable address translation region 0 (device config ++ * address space); region type config; ++ * axi config address range to device config address range ++ */ ++ writel(PCIE20_PLR_IATU_REGION_OUTBOUND | ++ PCIE20_PLR_IATU_REGION_INDEX(0), ++ pcie->dbi + PCIE20_PLR_IATU_VIEWPORT); ++ ++ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->dbi + PCIE20_PLR_IATU_CTRL1); ++ writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2); ++ writel(pp->cfg0_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR); ++ writel((pp->cfg0_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR); ++ writel((pp->cfg0_mod_base + pp->cfg0_size - 1), ++ pcie->dbi + PCIE20_PLR_IATU_LAR); ++ writel(busdev, pcie->dbi + PCIE20_PLR_IATU_LTAR); ++ writel(0, pcie->dbi + PCIE20_PLR_IATU_UTAR); ++} ++ ++static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie) ++{ ++ struct pcie_port *pp = &pcie->pp; ++ ++ /* ++ * program and enable address translation region 2 (device resource ++ * address space); region type memory; ++ * axi device bar address range to device bar address range ++ */ ++ writel(PCIE20_PLR_IATU_REGION_OUTBOUND | ++ PCIE20_PLR_IATU_REGION_INDEX(2), ++ pcie->dbi + PCIE20_PLR_IATU_VIEWPORT); ++ ++ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->dbi + PCIE20_PLR_IATU_CTRL1); ++ writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2); ++ writel(pp->mem_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR); ++ writel((pp->mem_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR); ++ writel(pp->mem_mod_base + pp->mem_size - 1, ++ pcie->dbi + PCIE20_PLR_IATU_LAR); ++ writel(pp->mem_bus_addr, pcie->dbi + PCIE20_PLR_IATU_LTAR); ++ writel(upper_32_bits(pp->mem_bus_addr), ++ pcie->dbi + PCIE20_PLR_IATU_UTAR); ++ ++ /* 1K PCIE buffer setting */ ++ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); ++ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); ++} ++ + static void qcom_pcie_host_init_v0(struct pcie_port *pp) + { + struct qcom_pcie *pcie = to_qcom_pcie(pp); +@@ -476,9 +616,26 @@ static void qcom_pcie_host_init_v0(struc + + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); + +- /* enable external reference clock */ +- writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16)); ++ /* Set Tx termination offset */ ++ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, ++ PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, ++ PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset)); ++ ++ /* PARF programming */ ++ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) | ++ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) | ++ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22), ++ pcie->parf + PCIE20_PARF_PCS_DEEMPH); ++ writel(PCS_SWING_TX_SWING_FULL(0x78) | ++ PCS_SWING_TX_SWING_LOW(0x78), ++ pcie->parf + PCIE20_PARF_PCS_SWING); ++ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS); ++ ++ /* Enable reference clock */ ++ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, ++ REF_USE_PAD, REF_SSP_EN); + ++ /* De-assert PHY, PCIe, POR and AXI resets */ + ret = reset_control_deassert(res->phy_reset); + if (ret) { + dev_err(dev, "cannot deassert phy reset\n"); +@@ -517,6 +674,9 @@ static void qcom_pcie_host_init_v0(struc + if (ret) + goto err; + ++ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR); ++ qcom_pcie_prog_viewport_mem2_outbound(pcie); ++ + return; + err: + qcom_ep_reset_assert(pcie); diff --git a/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch b/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch new file mode 100644 index 0000000..83c5f55 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/115-add-pcie-aux-clk-dts.patch @@ -0,0 +1,80 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -341,15 +341,21 @@ + + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, +- <&gcc PCIE_PHY_CLK>; +- clock-names = "core", "iface", "phy"; ++ <&gcc PCIE_PHY_CLK>, ++ <&gcc PCIE_AUX_CLK>, ++ <&gcc PCIE_ALT_REF_CLK>; ++ clock-names = "core", "iface", "phy", "aux", "ref"; ++ ++ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; ++ assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, +- <&gcc PCIE_PHY_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy"; ++ <&gcc PCIE_PHY_RESET>, ++ <&gcc PCIE_EXT_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + status = "disabled"; + }; +@@ -382,15 +388,21 @@ + + clocks = <&gcc PCIE_1_A_CLK>, + <&gcc PCIE_1_H_CLK>, +- <&gcc PCIE_1_PHY_CLK>; +- clock-names = "core", "iface", "phy"; ++ <&gcc PCIE_1_PHY_CLK>, ++ <&gcc PCIE_1_AUX_CLK>, ++ <&gcc PCIE_1_ALT_REF_CLK>; ++ clock-names = "core", "iface", "phy", "aux", "ref"; ++ ++ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; ++ assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_1_ACLK_RESET>, + <&gcc PCIE_1_HCLK_RESET>, + <&gcc PCIE_1_POR_RESET>, + <&gcc PCIE_1_PCI_RESET>, +- <&gcc PCIE_1_PHY_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy"; ++ <&gcc PCIE_1_PHY_RESET>, ++ <&gcc PCIE_1_EXT_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + status = "disabled"; + }; +@@ -423,15 +435,21 @@ + + clocks = <&gcc PCIE_2_A_CLK>, + <&gcc PCIE_2_H_CLK>, +- <&gcc PCIE_2_PHY_CLK>; +- clock-names = "core", "iface", "phy"; ++ <&gcc PCIE_2_PHY_CLK>, ++ <&gcc PCIE_2_AUX_CLK>, ++ <&gcc PCIE_2_ALT_REF_CLK>; ++ clock-names = "core", "iface", "phy", "aux", "ref"; ++ ++ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; ++ assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_2_ACLK_RESET>, + <&gcc PCIE_2_HCLK_RESET>, + <&gcc PCIE_2_POR_RESET>, + <&gcc PCIE_2_PCI_RESET>, +- <&gcc PCIE_2_PHY_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy"; ++ <&gcc PCIE_2_PHY_RESET>, ++ <&gcc PCIE_2_EXT_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + status = "disabled"; + }; diff --git a/target/linux/ipq806x/patches-3.18/120-mfd-qcom-rpm-Driver-for-the-Qualcomm-RPM.patch b/target/linux/ipq806x/patches-3.18/120-mfd-qcom-rpm-Driver-for-the-Qualcomm-RPM.patch new file mode 100644 index 0000000..d819142 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/120-mfd-qcom-rpm-Driver-for-the-Qualcomm-RPM.patch @@ -0,0 +1,654 @@ +From 58e214382bdd1eb48c5a3519182bddcb26edabad Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Wed, 26 Nov 2014 13:51:00 -0800 +Subject: [PATCH] mfd: qcom-rpm: Driver for the Qualcomm RPM + +Driver for the Resource Power Manager (RPM) found in Qualcomm 8660, 8960 +and 8064 based devices. The driver exposes resources that child drivers +can operate on; to implementing regulator, clock and bus frequency +drivers. + +Signed-off-by: Bjorn Andersson +Signed-off-by: Lee Jones +--- + drivers/mfd/Kconfig | 14 ++ + drivers/mfd/Makefile | 1 + + drivers/mfd/qcom_rpm.c | 581 +++++++++++++++++++++++++++++++++++++++++++ + include/linux/mfd/qcom_rpm.h | 13 + + 4 files changed, 609 insertions(+) + create mode 100644 drivers/mfd/qcom_rpm.c + create mode 100644 include/linux/mfd/qcom_rpm.h + +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -567,6 +567,20 @@ config MFD_PM8921_CORE + Say M here if you want to include support for PM8921 chip as a module. + This will build a module called "pm8921-core". + ++config MFD_QCOM_RPM ++ tristate "Qualcomm Resource Power Manager (RPM)" ++ depends on ARCH_QCOM && OF ++ help ++ If you say yes to this option, support will be included for the ++ Resource Power Manager system found in the Qualcomm 8660, 8960 and ++ 8064 based devices. ++ ++ This is required to access many regulators, clocks and bus ++ frequencies controlled by the RPM on these devices. ++ ++ Say M here if you want to include support for the Qualcomm RPM as a ++ module. This will build a module called "qcom_rpm". ++ + config MFD_SPMI_PMIC + tristate "Qualcomm SPMI PMICs" + depends on ARCH_QCOM || COMPILE_TEST +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -153,6 +153,7 @@ obj-$(CONFIG_MFD_SI476X_CORE) += si476x- + obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o + obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o omap-usb-tll.o + obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o ssbi.o ++obj-$(CONFIG_MFD_QCOM_RPM) += qcom_rpm.o + obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o + obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o + obj-$(CONFIG_MFD_TPS65090) += tps65090.o +--- /dev/null ++++ b/drivers/mfd/qcom_rpm.c +@@ -0,0 +1,581 @@ ++/* ++ * Copyright (c) 2014, Sony Mobile Communications AB. ++ * Copyright (c) 2013, The Linux Foundation. All rights reserved. ++ * Author: Bjorn Andersson ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++struct qcom_rpm_resource { ++ unsigned target_id; ++ unsigned status_id; ++ unsigned select_id; ++ unsigned size; ++}; ++ ++struct qcom_rpm_data { ++ u32 version; ++ const struct qcom_rpm_resource *resource_table; ++ unsigned n_resources; ++}; ++ ++struct qcom_rpm { ++ struct device *dev; ++ struct regmap *ipc_regmap; ++ unsigned ipc_offset; ++ unsigned ipc_bit; ++ ++ struct completion ack; ++ struct mutex lock; ++ ++ void __iomem *status_regs; ++ void __iomem *ctrl_regs; ++ void __iomem *req_regs; ++ ++ u32 ack_status; ++ ++ const struct qcom_rpm_data *data; ++}; ++ ++#define RPM_STATUS_REG(rpm, i) ((rpm)->status_regs + (i) * 4) ++#define RPM_CTRL_REG(rpm, i) ((rpm)->ctrl_regs + (i) * 4) ++#define RPM_REQ_REG(rpm, i) ((rpm)->req_regs + (i) * 4) ++ ++#define RPM_REQUEST_TIMEOUT (5 * HZ) ++ ++#define RPM_REQUEST_CONTEXT 3 ++#define RPM_REQ_SELECT 11 ++#define RPM_ACK_CONTEXT 15 ++#define RPM_ACK_SELECTOR 23 ++#define RPM_SELECT_SIZE 7 ++ ++#define RPM_NOTIFICATION BIT(30) ++#define RPM_REJECTED BIT(31) ++ ++#define RPM_SIGNAL BIT(2) ++ ++static const struct qcom_rpm_resource apq8064_rpm_resource_table[] = { ++ [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 }, ++ [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 }, ++ [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 }, ++ [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 }, ++ [QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 }, ++ [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 }, ++ [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 }, ++ [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 }, ++ [QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 }, ++ [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 }, ++ [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 }, ++ [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 }, ++ [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 }, ++ [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 }, ++ [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 }, ++ [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 }, ++ [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 }, ++ [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 }, ++ [QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 1 }, ++ [QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 1 }, ++ [QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 }, ++ [QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 21 }, ++ [QCOM_RPM_PM8921_SMPS1] = { 116, 31, 30, 2 }, ++ [QCOM_RPM_PM8921_SMPS2] = { 118, 33, 31, 2 }, ++ [QCOM_RPM_PM8921_SMPS3] = { 120, 35, 32, 2 }, ++ [QCOM_RPM_PM8921_SMPS4] = { 122, 37, 33, 2 }, ++ [QCOM_RPM_PM8921_SMPS5] = { 124, 39, 34, 2 }, ++ [QCOM_RPM_PM8921_SMPS6] = { 126, 41, 35, 2 }, ++ [QCOM_RPM_PM8921_SMPS7] = { 128, 43, 36, 2 }, ++ [QCOM_RPM_PM8921_SMPS8] = { 130, 45, 37, 2 }, ++ [QCOM_RPM_PM8921_LDO1] = { 132, 47, 38, 2 }, ++ [QCOM_RPM_PM8921_LDO2] = { 134, 49, 39, 2 }, ++ [QCOM_RPM_PM8921_LDO3] = { 136, 51, 40, 2 }, ++ [QCOM_RPM_PM8921_LDO4] = { 138, 53, 41, 2 }, ++ [QCOM_RPM_PM8921_LDO5] = { 140, 55, 42, 2 }, ++ [QCOM_RPM_PM8921_LDO6] = { 142, 57, 43, 2 }, ++ [QCOM_RPM_PM8921_LDO7] = { 144, 59, 44, 2 }, ++ [QCOM_RPM_PM8921_LDO8] = { 146, 61, 45, 2 }, ++ [QCOM_RPM_PM8921_LDO9] = { 148, 63, 46, 2 }, ++ [QCOM_RPM_PM8921_LDO10] = { 150, 65, 47, 2 }, ++ [QCOM_RPM_PM8921_LDO11] = { 152, 67, 48, 2 }, ++ [QCOM_RPM_PM8921_LDO12] = { 154, 69, 49, 2 }, ++ [QCOM_RPM_PM8921_LDO13] = { 156, 71, 50, 2 }, ++ [QCOM_RPM_PM8921_LDO14] = { 158, 73, 51, 2 }, ++ [QCOM_RPM_PM8921_LDO15] = { 160, 75, 52, 2 }, ++ [QCOM_RPM_PM8921_LDO16] = { 162, 77, 53, 2 }, ++ [QCOM_RPM_PM8921_LDO17] = { 164, 79, 54, 2 }, ++ [QCOM_RPM_PM8921_LDO18] = { 166, 81, 55, 2 }, ++ [QCOM_RPM_PM8921_LDO19] = { 168, 83, 56, 2 }, ++ [QCOM_RPM_PM8921_LDO20] = { 170, 85, 57, 2 }, ++ [QCOM_RPM_PM8921_LDO21] = { 172, 87, 58, 2 }, ++ [QCOM_RPM_PM8921_LDO22] = { 174, 89, 59, 2 }, ++ [QCOM_RPM_PM8921_LDO23] = { 176, 91, 60, 2 }, ++ [QCOM_RPM_PM8921_LDO24] = { 178, 93, 61, 2 }, ++ [QCOM_RPM_PM8921_LDO25] = { 180, 95, 62, 2 }, ++ [QCOM_RPM_PM8921_LDO26] = { 182, 97, 63, 2 }, ++ [QCOM_RPM_PM8921_LDO27] = { 184, 99, 64, 2 }, ++ [QCOM_RPM_PM8921_LDO28] = { 186, 101, 65, 2 }, ++ [QCOM_RPM_PM8921_LDO29] = { 188, 103, 66, 2 }, ++ [QCOM_RPM_PM8921_CLK1] = { 190, 105, 67, 2 }, ++ [QCOM_RPM_PM8921_CLK2] = { 192, 107, 68, 2 }, ++ [QCOM_RPM_PM8921_LVS1] = { 194, 109, 69, 1 }, ++ [QCOM_RPM_PM8921_LVS2] = { 195, 110, 70, 1 }, ++ [QCOM_RPM_PM8921_LVS3] = { 196, 111, 71, 1 }, ++ [QCOM_RPM_PM8921_LVS4] = { 197, 112, 72, 1 }, ++ [QCOM_RPM_PM8921_LVS5] = { 198, 113, 73, 1 }, ++ [QCOM_RPM_PM8921_LVS6] = { 199, 114, 74, 1 }, ++ [QCOM_RPM_PM8921_LVS7] = { 200, 115, 75, 1 }, ++ [QCOM_RPM_PM8821_SMPS1] = { 201, 116, 76, 2 }, ++ [QCOM_RPM_PM8821_SMPS2] = { 203, 118, 77, 2 }, ++ [QCOM_RPM_PM8821_LDO1] = { 205, 120, 78, 2 }, ++ [QCOM_RPM_PM8921_NCP] = { 207, 122, 80, 2 }, ++ [QCOM_RPM_CXO_BUFFERS] = { 209, 124, 81, 1 }, ++ [QCOM_RPM_USB_OTG_SWITCH] = { 210, 125, 82, 1 }, ++ [QCOM_RPM_HDMI_SWITCH] = { 211, 126, 83, 1 }, ++ [QCOM_RPM_DDR_DMM] = { 212, 127, 84, 2 }, ++ [QCOM_RPM_VDDMIN_GPIO] = { 215, 131, 89, 1 }, ++}; ++ ++static const struct qcom_rpm_data apq8064_template = { ++ .version = 3, ++ .resource_table = apq8064_rpm_resource_table, ++ .n_resources = ARRAY_SIZE(apq8064_rpm_resource_table), ++}; ++ ++static const struct qcom_rpm_resource msm8660_rpm_resource_table[] = { ++ [QCOM_RPM_CXO_CLK] = { 32, 12, 5, 1 }, ++ [QCOM_RPM_PXO_CLK] = { 33, 13, 6, 1 }, ++ [QCOM_RPM_PLL_4] = { 34, 14, 7, 1 }, ++ [QCOM_RPM_APPS_FABRIC_CLK] = { 35, 15, 8, 1 }, ++ [QCOM_RPM_SYS_FABRIC_CLK] = { 36, 16, 9, 1 }, ++ [QCOM_RPM_MM_FABRIC_CLK] = { 37, 17, 10, 1 }, ++ [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 38, 18, 11, 1 }, ++ [QCOM_RPM_SFPB_CLK] = { 39, 19, 12, 1 }, ++ [QCOM_RPM_CFPB_CLK] = { 40, 20, 13, 1 }, ++ [QCOM_RPM_MMFPB_CLK] = { 41, 21, 14, 1 }, ++ [QCOM_RPM_SMI_CLK] = { 42, 22, 15, 1 }, ++ [QCOM_RPM_EBI1_CLK] = { 43, 23, 16, 1 }, ++ [QCOM_RPM_APPS_L2_CACHE_CTL] = { 44, 24, 17, 1 }, ++ [QCOM_RPM_APPS_FABRIC_HALT] = { 45, 25, 18, 2 }, ++ [QCOM_RPM_APPS_FABRIC_MODE] = { 47, 26, 19, 3 }, ++ [QCOM_RPM_APPS_FABRIC_ARB] = { 51, 28, 21, 6 }, ++ [QCOM_RPM_SYS_FABRIC_HALT] = { 63, 29, 22, 2 }, ++ [QCOM_RPM_SYS_FABRIC_MODE] = { 65, 30, 23, 3 }, ++ [QCOM_RPM_SYS_FABRIC_ARB] = { 69, 32, 25, 22 }, ++ [QCOM_RPM_MM_FABRIC_HALT] = { 105, 33, 26, 2 }, ++ [QCOM_RPM_MM_FABRIC_MODE] = { 107, 34, 27, 3 }, ++ [QCOM_RPM_MM_FABRIC_ARB] = { 111, 36, 29, 23 }, ++ [QCOM_RPM_PM8901_SMPS0] = { 134, 37, 30, 2 }, ++ [QCOM_RPM_PM8901_SMPS1] = { 136, 39, 31, 2 }, ++ [QCOM_RPM_PM8901_SMPS2] = { 138, 41, 32, 2 }, ++ [QCOM_RPM_PM8901_SMPS3] = { 140, 43, 33, 2 }, ++ [QCOM_RPM_PM8901_SMPS4] = { 142, 45, 34, 2 }, ++ [QCOM_RPM_PM8901_LDO0] = { 144, 47, 35, 2 }, ++ [QCOM_RPM_PM8901_LDO1] = { 146, 49, 36, 2 }, ++ [QCOM_RPM_PM8901_LDO2] = { 148, 51, 37, 2 }, ++ [QCOM_RPM_PM8901_LDO3] = { 150, 53, 38, 2 }, ++ [QCOM_RPM_PM8901_LDO4] = { 152, 55, 39, 2 }, ++ [QCOM_RPM_PM8901_LDO5] = { 154, 57, 40, 2 }, ++ [QCOM_RPM_PM8901_LDO6] = { 156, 59, 41, 2 }, ++ [QCOM_RPM_PM8901_LVS0] = { 158, 61, 42, 1 }, ++ [QCOM_RPM_PM8901_LVS1] = { 159, 62, 43, 1 }, ++ [QCOM_RPM_PM8901_LVS2] = { 160, 63, 44, 1 }, ++ [QCOM_RPM_PM8901_LVS3] = { 161, 64, 45, 1 }, ++ [QCOM_RPM_PM8901_MVS] = { 162, 65, 46, 1 }, ++ [QCOM_RPM_PM8058_SMPS0] = { 163, 66, 47, 2 }, ++ [QCOM_RPM_PM8058_SMPS1] = { 165, 68, 48, 2 }, ++ [QCOM_RPM_PM8058_SMPS2] = { 167, 70, 49, 2 }, ++ [QCOM_RPM_PM8058_SMPS3] = { 169, 72, 50, 2 }, ++ [QCOM_RPM_PM8058_SMPS4] = { 171, 74, 51, 2 }, ++ [QCOM_RPM_PM8058_LDO0] = { 173, 76, 52, 2 }, ++ [QCOM_RPM_PM8058_LDO1] = { 175, 78, 53, 2 }, ++ [QCOM_RPM_PM8058_LDO2] = { 177, 80, 54, 2 }, ++ [QCOM_RPM_PM8058_LDO3] = { 179, 82, 55, 2 }, ++ [QCOM_RPM_PM8058_LDO4] = { 181, 84, 56, 2 }, ++ [QCOM_RPM_PM8058_LDO5] = { 183, 86, 57, 2 }, ++ [QCOM_RPM_PM8058_LDO6] = { 185, 88, 58, 2 }, ++ [QCOM_RPM_PM8058_LDO7] = { 187, 90, 59, 2 }, ++ [QCOM_RPM_PM8058_LDO8] = { 189, 92, 60, 2 }, ++ [QCOM_RPM_PM8058_LDO9] = { 191, 94, 61, 2 }, ++ [QCOM_RPM_PM8058_LDO10] = { 193, 96, 62, 2 }, ++ [QCOM_RPM_PM8058_LDO11] = { 195, 98, 63, 2 }, ++ [QCOM_RPM_PM8058_LDO12] = { 197, 100, 64, 2 }, ++ [QCOM_RPM_PM8058_LDO13] = { 199, 102, 65, 2 }, ++ [QCOM_RPM_PM8058_LDO14] = { 201, 104, 66, 2 }, ++ [QCOM_RPM_PM8058_LDO15] = { 203, 106, 67, 2 }, ++ [QCOM_RPM_PM8058_LDO16] = { 205, 108, 68, 2 }, ++ [QCOM_RPM_PM8058_LDO17] = { 207, 110, 69, 2 }, ++ [QCOM_RPM_PM8058_LDO18] = { 209, 112, 70, 2 }, ++ [QCOM_RPM_PM8058_LDO19] = { 211, 114, 71, 2 }, ++ [QCOM_RPM_PM8058_LDO20] = { 213, 116, 72, 2 }, ++ [QCOM_RPM_PM8058_LDO21] = { 215, 118, 73, 2 }, ++ [QCOM_RPM_PM8058_LDO22] = { 217, 120, 74, 2 }, ++ [QCOM_RPM_PM8058_LDO23] = { 219, 122, 75, 2 }, ++ [QCOM_RPM_PM8058_LDO24] = { 221, 124, 76, 2 }, ++ [QCOM_RPM_PM8058_LDO25] = { 223, 126, 77, 2 }, ++ [QCOM_RPM_PM8058_LVS0] = { 225, 128, 78, 1 }, ++ [QCOM_RPM_PM8058_LVS1] = { 226, 129, 79, 1 }, ++ [QCOM_RPM_PM8058_NCP] = { 227, 130, 80, 2 }, ++ [QCOM_RPM_CXO_BUFFERS] = { 229, 132, 81, 1 }, ++}; ++ ++static const struct qcom_rpm_data msm8660_template = { ++ .version = 2, ++ .resource_table = msm8660_rpm_resource_table, ++ .n_resources = ARRAY_SIZE(msm8660_rpm_resource_table), ++}; ++ ++static const struct qcom_rpm_resource msm8960_rpm_resource_table[] = { ++ [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 }, ++ [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 }, ++ [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 }, ++ [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 }, ++ [QCOM_RPM_MM_FABRIC_CLK] = { 29, 13, 10, 1 }, ++ [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 }, ++ [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 }, ++ [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 }, ++ [QCOM_RPM_MMFPB_CLK] = { 33, 17, 14, 1 }, ++ [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 }, ++ [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 1 }, ++ [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 1 }, ++ [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 }, ++ [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 }, ++ [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 1 }, ++ [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 1 }, ++ [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 }, ++ [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 29 }, ++ [QCOM_RPM_MM_FABRIC_HALT] = { 88, 27, 26, 1 }, ++ [QCOM_RPM_MM_FABRIC_MODE] = { 90, 28, 27, 1 }, ++ [QCOM_RPM_MM_FABRIC_IOCTL] = { 93, 29, 28, 1 }, ++ [QCOM_RPM_MM_FABRIC_ARB] = { 94, 30, 29, 23 }, ++ [QCOM_RPM_PM8921_SMPS1] = { 117, 31, 30, 2 }, ++ [QCOM_RPM_PM8921_SMPS2] = { 119, 33, 31, 2 }, ++ [QCOM_RPM_PM8921_SMPS3] = { 121, 35, 32, 2 }, ++ [QCOM_RPM_PM8921_SMPS4] = { 123, 37, 33, 2 }, ++ [QCOM_RPM_PM8921_SMPS5] = { 125, 39, 34, 2 }, ++ [QCOM_RPM_PM8921_SMPS6] = { 127, 41, 35, 2 }, ++ [QCOM_RPM_PM8921_SMPS7] = { 129, 43, 36, 2 }, ++ [QCOM_RPM_PM8921_SMPS8] = { 131, 45, 37, 2 }, ++ [QCOM_RPM_PM8921_LDO1] = { 133, 47, 38, 2 }, ++ [QCOM_RPM_PM8921_LDO2] = { 135, 49, 39, 2 }, ++ [QCOM_RPM_PM8921_LDO3] = { 137, 51, 40, 2 }, ++ [QCOM_RPM_PM8921_LDO4] = { 139, 53, 41, 2 }, ++ [QCOM_RPM_PM8921_LDO5] = { 141, 55, 42, 2 }, ++ [QCOM_RPM_PM8921_LDO6] = { 143, 57, 43, 2 }, ++ [QCOM_RPM_PM8921_LDO7] = { 145, 59, 44, 2 }, ++ [QCOM_RPM_PM8921_LDO8] = { 147, 61, 45, 2 }, ++ [QCOM_RPM_PM8921_LDO9] = { 149, 63, 46, 2 }, ++ [QCOM_RPM_PM8921_LDO10] = { 151, 65, 47, 2 }, ++ [QCOM_RPM_PM8921_LDO11] = { 153, 67, 48, 2 }, ++ [QCOM_RPM_PM8921_LDO12] = { 155, 69, 49, 2 }, ++ [QCOM_RPM_PM8921_LDO13] = { 157, 71, 50, 2 }, ++ [QCOM_RPM_PM8921_LDO14] = { 159, 73, 51, 2 }, ++ [QCOM_RPM_PM8921_LDO15] = { 161, 75, 52, 2 }, ++ [QCOM_RPM_PM8921_LDO16] = { 163, 77, 53, 2 }, ++ [QCOM_RPM_PM8921_LDO17] = { 165, 79, 54, 2 }, ++ [QCOM_RPM_PM8921_LDO18] = { 167, 81, 55, 2 }, ++ [QCOM_RPM_PM8921_LDO19] = { 169, 83, 56, 2 }, ++ [QCOM_RPM_PM8921_LDO20] = { 171, 85, 57, 2 }, ++ [QCOM_RPM_PM8921_LDO21] = { 173, 87, 58, 2 }, ++ [QCOM_RPM_PM8921_LDO22] = { 175, 89, 59, 2 }, ++ [QCOM_RPM_PM8921_LDO23] = { 177, 91, 60, 2 }, ++ [QCOM_RPM_PM8921_LDO24] = { 179, 93, 61, 2 }, ++ [QCOM_RPM_PM8921_LDO25] = { 181, 95, 62, 2 }, ++ [QCOM_RPM_PM8921_LDO26] = { 183, 97, 63, 2 }, ++ [QCOM_RPM_PM8921_LDO27] = { 185, 99, 64, 2 }, ++ [QCOM_RPM_PM8921_LDO28] = { 187, 101, 65, 2 }, ++ [QCOM_RPM_PM8921_LDO29] = { 189, 103, 66, 2 }, ++ [QCOM_RPM_PM8921_CLK1] = { 191, 105, 67, 2 }, ++ [QCOM_RPM_PM8921_CLK2] = { 193, 107, 68, 2 }, ++ [QCOM_RPM_PM8921_LVS1] = { 195, 109, 69, 1 }, ++ [QCOM_RPM_PM8921_LVS2] = { 196, 110, 70, 1 }, ++ [QCOM_RPM_PM8921_LVS3] = { 197, 111, 71, 1 }, ++ [QCOM_RPM_PM8921_LVS4] = { 198, 112, 72, 1 }, ++ [QCOM_RPM_PM8921_LVS5] = { 199, 113, 73, 1 }, ++ [QCOM_RPM_PM8921_LVS6] = { 200, 114, 74, 1 }, ++ [QCOM_RPM_PM8921_LVS7] = { 201, 115, 75, 1 }, ++ [QCOM_RPM_PM8921_NCP] = { 202, 116, 80, 2 }, ++ [QCOM_RPM_CXO_BUFFERS] = { 204, 118, 81, 1 }, ++ [QCOM_RPM_USB_OTG_SWITCH] = { 205, 119, 82, 1 }, ++ [QCOM_RPM_HDMI_SWITCH] = { 206, 120, 83, 1 }, ++ [QCOM_RPM_DDR_DMM] = { 207, 121, 84, 2 }, ++}; ++ ++static const struct qcom_rpm_data msm8960_template = { ++ .version = 3, ++ .resource_table = msm8960_rpm_resource_table, ++ .n_resources = ARRAY_SIZE(msm8960_rpm_resource_table), ++}; ++ ++static const struct of_device_id qcom_rpm_of_match[] = { ++ { .compatible = "qcom,rpm-apq8064", .data = &apq8064_template }, ++ { .compatible = "qcom,rpm-msm8660", .data = &msm8660_template }, ++ { .compatible = "qcom,rpm-msm8960", .data = &msm8960_template }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qcom_rpm_of_match); ++ ++int qcom_rpm_write(struct qcom_rpm *rpm, ++ int state, ++ int resource, ++ u32 *buf, size_t count) ++{ ++ const struct qcom_rpm_resource *res; ++ const struct qcom_rpm_data *data = rpm->data; ++ u32 sel_mask[RPM_SELECT_SIZE] = { 0 }; ++ int left; ++ int ret = 0; ++ int i; ++ ++ if (WARN_ON(resource < 0 || resource >= data->n_resources)) ++ return -EINVAL; ++ ++ res = &data->resource_table[resource]; ++ if (WARN_ON(res->size != count)) ++ return -EINVAL; ++ ++ mutex_lock(&rpm->lock); ++ ++ for (i = 0; i < res->size; i++) ++ writel_relaxed(buf[i], RPM_REQ_REG(rpm, res->target_id + i)); ++ ++ bitmap_set((unsigned long *)sel_mask, res->select_id, 1); ++ for (i = 0; i < ARRAY_SIZE(sel_mask); i++) { ++ writel_relaxed(sel_mask[i], ++ RPM_CTRL_REG(rpm, RPM_REQ_SELECT + i)); ++ } ++ ++ writel_relaxed(BIT(state), RPM_CTRL_REG(rpm, RPM_REQUEST_CONTEXT)); ++ ++ reinit_completion(&rpm->ack); ++ regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit)); ++ ++ left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT); ++ if (!left) ++ ret = -ETIMEDOUT; ++ else if (rpm->ack_status & RPM_REJECTED) ++ ret = -EIO; ++ ++ mutex_unlock(&rpm->lock); ++ ++ return ret; ++} ++EXPORT_SYMBOL(qcom_rpm_write); ++ ++static irqreturn_t qcom_rpm_ack_interrupt(int irq, void *dev) ++{ ++ struct qcom_rpm *rpm = dev; ++ u32 ack; ++ int i; ++ ++ ack = readl_relaxed(RPM_CTRL_REG(rpm, RPM_ACK_CONTEXT)); ++ for (i = 0; i < RPM_SELECT_SIZE; i++) ++ writel_relaxed(0, RPM_CTRL_REG(rpm, RPM_ACK_SELECTOR + i)); ++ writel(0, RPM_CTRL_REG(rpm, RPM_ACK_CONTEXT)); ++ ++ if (ack & RPM_NOTIFICATION) { ++ dev_warn(rpm->dev, "ignoring notification!\n"); ++ } else { ++ rpm->ack_status = ack; ++ complete(&rpm->ack); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t qcom_rpm_err_interrupt(int irq, void *dev) ++{ ++ struct qcom_rpm *rpm = dev; ++ ++ regmap_write(rpm->ipc_regmap, rpm->ipc_offset, BIT(rpm->ipc_bit)); ++ dev_err(rpm->dev, "RPM triggered fatal error\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t qcom_rpm_wakeup_interrupt(int irq, void *dev) ++{ ++ return IRQ_HANDLED; ++} ++ ++static int qcom_rpm_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *match; ++ struct device_node *syscon_np; ++ struct resource *res; ++ struct qcom_rpm *rpm; ++ u32 fw_version[3]; ++ int irq_wakeup; ++ int irq_ack; ++ int irq_err; ++ int ret; ++ ++ rpm = devm_kzalloc(&pdev->dev, sizeof(*rpm), GFP_KERNEL); ++ if (!rpm) ++ return -ENOMEM; ++ ++ rpm->dev = &pdev->dev; ++ mutex_init(&rpm->lock); ++ init_completion(&rpm->ack); ++ ++ irq_ack = platform_get_irq_byname(pdev, "ack"); ++ if (irq_ack < 0) { ++ dev_err(&pdev->dev, "required ack interrupt missing\n"); ++ return irq_ack; ++ } ++ ++ irq_err = platform_get_irq_byname(pdev, "err"); ++ if (irq_err < 0) { ++ dev_err(&pdev->dev, "required err interrupt missing\n"); ++ return irq_err; ++ } ++ ++ irq_wakeup = platform_get_irq_byname(pdev, "wakeup"); ++ if (irq_wakeup < 0) { ++ dev_err(&pdev->dev, "required wakeup interrupt missing\n"); ++ return irq_wakeup; ++ } ++ ++ match = of_match_device(qcom_rpm_of_match, &pdev->dev); ++ rpm->data = match->data; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ rpm->status_regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(rpm->status_regs)) ++ return PTR_ERR(rpm->status_regs); ++ rpm->ctrl_regs = rpm->status_regs + 0x400; ++ rpm->req_regs = rpm->status_regs + 0x600; ++ ++ syscon_np = of_parse_phandle(pdev->dev.of_node, "qcom,ipc", 0); ++ if (!syscon_np) { ++ dev_err(&pdev->dev, "no qcom,ipc node\n"); ++ return -ENODEV; ++ } ++ ++ rpm->ipc_regmap = syscon_node_to_regmap(syscon_np); ++ if (IS_ERR(rpm->ipc_regmap)) ++ return PTR_ERR(rpm->ipc_regmap); ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 1, ++ &rpm->ipc_offset); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no offset in qcom,ipc\n"); ++ return -EINVAL; ++ } ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,ipc", 2, ++ &rpm->ipc_bit); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no bit in qcom,ipc\n"); ++ return -EINVAL; ++ } ++ ++ dev_set_drvdata(&pdev->dev, rpm); ++ ++ fw_version[0] = readl(RPM_STATUS_REG(rpm, 0)); ++ fw_version[1] = readl(RPM_STATUS_REG(rpm, 1)); ++ fw_version[2] = readl(RPM_STATUS_REG(rpm, 2)); ++ if (fw_version[0] != rpm->data->version) { ++ dev_err(&pdev->dev, ++ "RPM version %u.%u.%u incompatible with driver version %u", ++ fw_version[0], ++ fw_version[1], ++ fw_version[2], ++ rpm->data->version); ++ return -EFAULT; ++ } ++ ++ dev_info(&pdev->dev, "RPM firmware %u.%u.%u\n", fw_version[0], ++ fw_version[1], ++ fw_version[2]); ++ ++ ret = devm_request_irq(&pdev->dev, ++ irq_ack, ++ qcom_rpm_ack_interrupt, ++ IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, ++ "qcom_rpm_ack", ++ rpm); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request ack interrupt\n"); ++ return ret; ++ } ++ ++ ret = irq_set_irq_wake(irq_ack, 1); ++ if (ret) ++ dev_warn(&pdev->dev, "failed to mark ack irq as wakeup\n"); ++ ++ ret = devm_request_irq(&pdev->dev, ++ irq_err, ++ qcom_rpm_err_interrupt, ++ IRQF_TRIGGER_RISING, ++ "qcom_rpm_err", ++ rpm); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request err interrupt\n"); ++ return ret; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, ++ irq_wakeup, ++ qcom_rpm_wakeup_interrupt, ++ IRQF_TRIGGER_RISING, ++ "qcom_rpm_wakeup", ++ rpm); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request wakeup interrupt\n"); ++ return ret; ++ } ++ ++ ret = irq_set_irq_wake(irq_wakeup, 1); ++ if (ret) ++ dev_warn(&pdev->dev, "failed to mark wakeup irq as wakeup\n"); ++ ++ return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); ++} ++ ++static int qcom_rpm_remove(struct platform_device *pdev) ++{ ++ of_platform_depopulate(&pdev->dev); ++ return 0; ++} ++ ++static struct platform_driver qcom_rpm_driver = { ++ .probe = qcom_rpm_probe, ++ .remove = qcom_rpm_remove, ++ .driver = { ++ .name = "qcom_rpm", ++ .of_match_table = qcom_rpm_of_match, ++ }, ++}; ++ ++static int __init qcom_rpm_init(void) ++{ ++ return platform_driver_register(&qcom_rpm_driver); ++} ++arch_initcall(qcom_rpm_init); ++ ++static void __exit qcom_rpm_exit(void) ++{ ++ platform_driver_unregister(&qcom_rpm_driver); ++} ++module_exit(qcom_rpm_exit) ++ ++MODULE_DESCRIPTION("Qualcomm Resource Power Manager driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Bjorn Andersson "); +--- /dev/null ++++ b/include/linux/mfd/qcom_rpm.h +@@ -0,0 +1,13 @@ ++#ifndef __QCOM_RPM_H__ ++#define __QCOM_RPM_H__ ++ ++#include ++ ++struct qcom_rpm; ++ ++#define QCOM_RPM_ACTIVE_STATE 0 ++#define QCOM_RPM_SLEEP_STATE 1 ++ ++int qcom_rpm_write(struct qcom_rpm *rpm, int state, int resource, u32 *buf, size_t count); ++ ++#endif diff --git a/target/linux/ipq806x/patches-3.18/121-mfd-qcom_rpm-Add-support-for-IPQ8064.patch b/target/linux/ipq806x/patches-3.18/121-mfd-qcom_rpm-Add-support-for-IPQ8064.patch new file mode 100644 index 0000000..e5e9e4e --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/121-mfd-qcom_rpm-Add-support-for-IPQ8064.patch @@ -0,0 +1,71 @@ +From 4d54b0adfa67476e6509bc8646b9dbac642e8a29 Mon Sep 17 00:00:00 2001 +From: Josh Cartwright +Date: Thu, 26 Mar 2015 11:29:26 -0700 +Subject: [PATCH] mfd: qcom_rpm: Add support for IPQ8064 + +The IPQ8064 also includes an RPM following the same message structure as +other chips. In addition, it supports a few new resource types to +support the NSS fabric clocks and the SMB208/SMB209 regulators found on +the reference boards. + +Signed-off-by: Josh Cartwright +Signed-off-by: Stephen Boyd +Signed-off-by: Lee Jones +--- + drivers/mfd/qcom_rpm.c | 41 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/drivers/mfd/qcom_rpm.c ++++ b/drivers/mfd/qcom_rpm.c +@@ -323,10 +323,51 @@ static const struct qcom_rpm_data msm896 + .n_resources = ARRAY_SIZE(msm8960_rpm_resource_table), + }; + ++static const struct qcom_rpm_resource ipq806x_rpm_resource_table[] = { ++ [QCOM_RPM_CXO_CLK] = { 25, 9, 5, 1 }, ++ [QCOM_RPM_PXO_CLK] = { 26, 10, 6, 1 }, ++ [QCOM_RPM_APPS_FABRIC_CLK] = { 27, 11, 8, 1 }, ++ [QCOM_RPM_SYS_FABRIC_CLK] = { 28, 12, 9, 1 }, ++ [QCOM_RPM_NSS_FABRIC_0_CLK] = { 29, 13, 10, 1 }, ++ [QCOM_RPM_DAYTONA_FABRIC_CLK] = { 30, 14, 11, 1 }, ++ [QCOM_RPM_SFPB_CLK] = { 31, 15, 12, 1 }, ++ [QCOM_RPM_CFPB_CLK] = { 32, 16, 13, 1 }, ++ [QCOM_RPM_NSS_FABRIC_1_CLK] = { 33, 17, 14, 1 }, ++ [QCOM_RPM_EBI1_CLK] = { 34, 18, 16, 1 }, ++ [QCOM_RPM_APPS_FABRIC_HALT] = { 35, 19, 18, 2 }, ++ [QCOM_RPM_APPS_FABRIC_MODE] = { 37, 20, 19, 3 }, ++ [QCOM_RPM_APPS_FABRIC_IOCTL] = { 40, 21, 20, 1 }, ++ [QCOM_RPM_APPS_FABRIC_ARB] = { 41, 22, 21, 12 }, ++ [QCOM_RPM_SYS_FABRIC_HALT] = { 53, 23, 22, 2 }, ++ [QCOM_RPM_SYS_FABRIC_MODE] = { 55, 24, 23, 3 }, ++ [QCOM_RPM_SYS_FABRIC_IOCTL] = { 58, 25, 24, 1 }, ++ [QCOM_RPM_SYS_FABRIC_ARB] = { 59, 26, 25, 30 }, ++ [QCOM_RPM_MM_FABRIC_HALT] = { 89, 27, 26, 2 }, ++ [QCOM_RPM_MM_FABRIC_MODE] = { 91, 28, 27, 3 }, ++ [QCOM_RPM_MM_FABRIC_IOCTL] = { 94, 29, 28, 1 }, ++ [QCOM_RPM_MM_FABRIC_ARB] = { 95, 30, 29, 2 }, ++ [QCOM_RPM_CXO_BUFFERS] = { 209, 33, 31, 1 }, ++ [QCOM_RPM_USB_OTG_SWITCH] = { 210, 34, 32, 1 }, ++ [QCOM_RPM_HDMI_SWITCH] = { 211, 35, 33, 1 }, ++ [QCOM_RPM_DDR_DMM] = { 212, 36, 34, 2 }, ++ [QCOM_RPM_VDDMIN_GPIO] = { 215, 40, 39, 1 }, ++ [QCOM_RPM_SMB208_S1a] = { 216, 41, 90, 2 }, ++ [QCOM_RPM_SMB208_S1b] = { 218, 43, 91, 2 }, ++ [QCOM_RPM_SMB208_S2a] = { 220, 45, 92, 2 }, ++ [QCOM_RPM_SMB208_S2b] = { 222, 47, 93, 2 }, ++}; ++ ++static const struct qcom_rpm_data ipq806x_template = { ++ .version = 3, ++ .resource_table = ipq806x_rpm_resource_table, ++ .n_resources = ARRAY_SIZE(ipq806x_rpm_resource_table), ++}; ++ + static const struct of_device_id qcom_rpm_of_match[] = { + { .compatible = "qcom,rpm-apq8064", .data = &apq8064_template }, + { .compatible = "qcom,rpm-msm8660", .data = &msm8660_template }, + { .compatible = "qcom,rpm-msm8960", .data = &msm8960_template }, ++ { .compatible = "qcom,rpm-ipq8064", .data = &ipq806x_template }, + { } + }; + MODULE_DEVICE_TABLE(of, qcom_rpm_of_match); diff --git a/target/linux/ipq806x/patches-3.18/122-mfd-devicetree-bindings-Add-Qualcomm-RPM-DT-binding.patch b/target/linux/ipq806x/patches-3.18/122-mfd-devicetree-bindings-Add-Qualcomm-RPM-DT-binding.patch new file mode 100644 index 0000000..a65d2c5 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/122-mfd-devicetree-bindings-Add-Qualcomm-RPM-DT-binding.patch @@ -0,0 +1,247 @@ +From aa0c4b815045420ea54d5ae5362f5a0190609d46 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Wed, 26 Nov 2014 13:50:59 -0800 +Subject: [PATCH] mfd: devicetree: bindings: Add Qualcomm RPM DT binding + +Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, +8960 and 8064 based devices. + +Signed-off-by: Bjorn Andersson +Signed-off-by: Lee Jones +--- + Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 70 ++++++++++ + include/dt-bindings/mfd/qcom-rpm.h | 154 +++++++++++++++++++++ + 2 files changed, 224 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mfd/qcom-rpm.txt + create mode 100644 include/dt-bindings/mfd/qcom-rpm.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt +@@ -0,0 +1,70 @@ ++Qualcomm Resource Power Manager (RPM) ++ ++This driver is used to interface with the Resource Power Manager (RPM) found in ++various Qualcomm platforms. The RPM allows each component in the system to vote ++for state of the system resources, such as clocks, regulators and bus ++frequencies. ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: must be one of: ++ "qcom,rpm-apq8064" ++ "qcom,rpm-msm8660" ++ "qcom,rpm-msm8960" ++ ++- reg: ++ Usage: required ++ Value type: ++ Definition: base address and size of the RPM's message ram ++ ++- interrupts: ++ Usage: required ++ Value type: ++ Definition: three entries specifying the RPM's: ++ 1. acknowledgement interrupt ++ 2. error interrupt ++ 3. wakeup interrupt ++ ++- interrupt-names: ++ Usage: required ++ Value type: ++ Definition: must be the three strings "ack", "err" and "wakeup", in order ++ ++- #address-cells: ++ Usage: required ++ Value type: ++ Definition: must be 1 ++ ++- #size-cells: ++ Usage: required ++ Value type: ++ Definition: must be 0 ++ ++- qcom,ipc: ++ Usage: required ++ Value type: ++ ++ Definition: three entries specifying the outgoing ipc bit used for ++ signaling the RPM: ++ - phandle to a syscon node representing the apcs registers ++ - u32 representing offset to the register within the syscon ++ - u32 representing the ipc bit within the register ++ ++ ++= EXAMPLE ++ ++ #include ++ ++ rpm@108000 { ++ compatible = "qcom,rpm-msm8960"; ++ reg = <0x108000 0x1000>; ++ qcom,ipc = <&apcs 0x8 2>; ++ ++ interrupts = <0 19 0>, <0 21 0>, <0 22 0>; ++ interrupt-names = "ack", "err", "wakeup"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ +--- /dev/null ++++ b/include/dt-bindings/mfd/qcom-rpm.h +@@ -0,0 +1,154 @@ ++/* ++ * This header provides constants for the Qualcomm RPM bindings. ++ */ ++ ++#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H ++#define _DT_BINDINGS_MFD_QCOM_RPM_H ++ ++/* ++ * Constants use to identify individual resources in the RPM. ++ */ ++#define QCOM_RPM_APPS_FABRIC_ARB 1 ++#define QCOM_RPM_APPS_FABRIC_CLK 2 ++#define QCOM_RPM_APPS_FABRIC_HALT 3 ++#define QCOM_RPM_APPS_FABRIC_IOCTL 4 ++#define QCOM_RPM_APPS_FABRIC_MODE 5 ++#define QCOM_RPM_APPS_L2_CACHE_CTL 6 ++#define QCOM_RPM_CFPB_CLK 7 ++#define QCOM_RPM_CXO_BUFFERS 8 ++#define QCOM_RPM_CXO_CLK 9 ++#define QCOM_RPM_DAYTONA_FABRIC_CLK 10 ++#define QCOM_RPM_DDR_DMM 11 ++#define QCOM_RPM_EBI1_CLK 12 ++#define QCOM_RPM_HDMI_SWITCH 13 ++#define QCOM_RPM_MMFPB_CLK 14 ++#define QCOM_RPM_MM_FABRIC_ARB 15 ++#define QCOM_RPM_MM_FABRIC_CLK 16 ++#define QCOM_RPM_MM_FABRIC_HALT 17 ++#define QCOM_RPM_MM_FABRIC_IOCTL 18 ++#define QCOM_RPM_MM_FABRIC_MODE 19 ++#define QCOM_RPM_PLL_4 20 ++#define QCOM_RPM_PM8058_LDO0 21 ++#define QCOM_RPM_PM8058_LDO1 22 ++#define QCOM_RPM_PM8058_LDO2 23 ++#define QCOM_RPM_PM8058_LDO3 24 ++#define QCOM_RPM_PM8058_LDO4 25 ++#define QCOM_RPM_PM8058_LDO5 26 ++#define QCOM_RPM_PM8058_LDO6 27 ++#define QCOM_RPM_PM8058_LDO7 28 ++#define QCOM_RPM_PM8058_LDO8 29 ++#define QCOM_RPM_PM8058_LDO9 30 ++#define QCOM_RPM_PM8058_LDO10 31 ++#define QCOM_RPM_PM8058_LDO11 32 ++#define QCOM_RPM_PM8058_LDO12 33 ++#define QCOM_RPM_PM8058_LDO13 34 ++#define QCOM_RPM_PM8058_LDO14 35 ++#define QCOM_RPM_PM8058_LDO15 36 ++#define QCOM_RPM_PM8058_LDO16 37 ++#define QCOM_RPM_PM8058_LDO17 38 ++#define QCOM_RPM_PM8058_LDO18 39 ++#define QCOM_RPM_PM8058_LDO19 40 ++#define QCOM_RPM_PM8058_LDO20 41 ++#define QCOM_RPM_PM8058_LDO21 42 ++#define QCOM_RPM_PM8058_LDO22 43 ++#define QCOM_RPM_PM8058_LDO23 44 ++#define QCOM_RPM_PM8058_LDO24 45 ++#define QCOM_RPM_PM8058_LDO25 46 ++#define QCOM_RPM_PM8058_LVS0 47 ++#define QCOM_RPM_PM8058_LVS1 48 ++#define QCOM_RPM_PM8058_NCP 49 ++#define QCOM_RPM_PM8058_SMPS0 50 ++#define QCOM_RPM_PM8058_SMPS1 51 ++#define QCOM_RPM_PM8058_SMPS2 52 ++#define QCOM_RPM_PM8058_SMPS3 53 ++#define QCOM_RPM_PM8058_SMPS4 54 ++#define QCOM_RPM_PM8821_LDO1 55 ++#define QCOM_RPM_PM8821_SMPS1 56 ++#define QCOM_RPM_PM8821_SMPS2 57 ++#define QCOM_RPM_PM8901_LDO0 58 ++#define QCOM_RPM_PM8901_LDO1 59 ++#define QCOM_RPM_PM8901_LDO2 60 ++#define QCOM_RPM_PM8901_LDO3 61 ++#define QCOM_RPM_PM8901_LDO4 62 ++#define QCOM_RPM_PM8901_LDO5 63 ++#define QCOM_RPM_PM8901_LDO6 64 ++#define QCOM_RPM_PM8901_LVS0 65 ++#define QCOM_RPM_PM8901_LVS1 66 ++#define QCOM_RPM_PM8901_LVS2 67 ++#define QCOM_RPM_PM8901_LVS3 68 ++#define QCOM_RPM_PM8901_MVS 69 ++#define QCOM_RPM_PM8901_SMPS0 70 ++#define QCOM_RPM_PM8901_SMPS1 71 ++#define QCOM_RPM_PM8901_SMPS2 72 ++#define QCOM_RPM_PM8901_SMPS3 73 ++#define QCOM_RPM_PM8901_SMPS4 74 ++#define QCOM_RPM_PM8921_CLK1 75 ++#define QCOM_RPM_PM8921_CLK2 76 ++#define QCOM_RPM_PM8921_LDO1 77 ++#define QCOM_RPM_PM8921_LDO2 78 ++#define QCOM_RPM_PM8921_LDO3 79 ++#define QCOM_RPM_PM8921_LDO4 80 ++#define QCOM_RPM_PM8921_LDO5 81 ++#define QCOM_RPM_PM8921_LDO6 82 ++#define QCOM_RPM_PM8921_LDO7 83 ++#define QCOM_RPM_PM8921_LDO8 84 ++#define QCOM_RPM_PM8921_LDO9 85 ++#define QCOM_RPM_PM8921_LDO10 86 ++#define QCOM_RPM_PM8921_LDO11 87 ++#define QCOM_RPM_PM8921_LDO12 88 ++#define QCOM_RPM_PM8921_LDO13 89 ++#define QCOM_RPM_PM8921_LDO14 90 ++#define QCOM_RPM_PM8921_LDO15 91 ++#define QCOM_RPM_PM8921_LDO16 92 ++#define QCOM_RPM_PM8921_LDO17 93 ++#define QCOM_RPM_PM8921_LDO18 94 ++#define QCOM_RPM_PM8921_LDO19 95 ++#define QCOM_RPM_PM8921_LDO20 96 ++#define QCOM_RPM_PM8921_LDO21 97 ++#define QCOM_RPM_PM8921_LDO22 98 ++#define QCOM_RPM_PM8921_LDO23 99 ++#define QCOM_RPM_PM8921_LDO24 100 ++#define QCOM_RPM_PM8921_LDO25 101 ++#define QCOM_RPM_PM8921_LDO26 102 ++#define QCOM_RPM_PM8921_LDO27 103 ++#define QCOM_RPM_PM8921_LDO28 104 ++#define QCOM_RPM_PM8921_LDO29 105 ++#define QCOM_RPM_PM8921_LVS1 106 ++#define QCOM_RPM_PM8921_LVS2 107 ++#define QCOM_RPM_PM8921_LVS3 108 ++#define QCOM_RPM_PM8921_LVS4 109 ++#define QCOM_RPM_PM8921_LVS5 110 ++#define QCOM_RPM_PM8921_LVS6 111 ++#define QCOM_RPM_PM8921_LVS7 112 ++#define QCOM_RPM_PM8921_MVS 113 ++#define QCOM_RPM_PM8921_NCP 114 ++#define QCOM_RPM_PM8921_SMPS1 115 ++#define QCOM_RPM_PM8921_SMPS2 116 ++#define QCOM_RPM_PM8921_SMPS3 117 ++#define QCOM_RPM_PM8921_SMPS4 118 ++#define QCOM_RPM_PM8921_SMPS5 119 ++#define QCOM_RPM_PM8921_SMPS6 120 ++#define QCOM_RPM_PM8921_SMPS7 121 ++#define QCOM_RPM_PM8921_SMPS8 122 ++#define QCOM_RPM_PXO_CLK 123 ++#define QCOM_RPM_QDSS_CLK 124 ++#define QCOM_RPM_SFPB_CLK 125 ++#define QCOM_RPM_SMI_CLK 126 ++#define QCOM_RPM_SYS_FABRIC_ARB 127 ++#define QCOM_RPM_SYS_FABRIC_CLK 128 ++#define QCOM_RPM_SYS_FABRIC_HALT 129 ++#define QCOM_RPM_SYS_FABRIC_IOCTL 130 ++#define QCOM_RPM_SYS_FABRIC_MODE 131 ++#define QCOM_RPM_USB_OTG_SWITCH 132 ++#define QCOM_RPM_VDDMIN_GPIO 133 ++ ++/* ++ * Constants used to select force mode for regulators. ++ */ ++#define QCOM_RPM_FORCE_MODE_NONE 0 ++#define QCOM_RPM_FORCE_MODE_LPM 1 ++#define QCOM_RPM_FORCE_MODE_HPM 2 ++#define QCOM_RPM_FORCE_MODE_AUTO 3 ++#define QCOM_RPM_FORCE_MODE_BYPASS 4 ++ ++#endif diff --git a/target/linux/ipq806x/patches-3.18/123-mfd-devicetree-qcom_rpm-Document-IPQ8064-resources.patch b/target/linux/ipq806x/patches-3.18/123-mfd-devicetree-qcom_rpm-Document-IPQ8064-resources.patch new file mode 100644 index 0000000..c8a9f3f --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/123-mfd-devicetree-qcom_rpm-Document-IPQ8064-resources.patch @@ -0,0 +1,42 @@ +From 30bc3aa5c4ed3072bdff7d915772df1b91307ed4 Mon Sep 17 00:00:00 2001 +From: Josh Cartwright +Date: Thu, 26 Mar 2015 11:29:25 -0700 +Subject: [PATCH] mfd: devicetree: qcom_rpm: Document IPQ8064 resources + +The IPQ8064 SoC has several RPM-controlled resources, an NSS fabrick +clock and four regulator resources. Provide definitions for them. + +Signed-off-by: Josh Cartwright +[sboyd@codeaurora.org: Drop regulator part of binding] +Signed-off-by: Stephen Boyd +Signed-off-by: Lee Jones +--- + Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 1 + + include/dt-bindings/mfd/qcom-rpm.h | 6 ++++++ + 2 files changed, 7 insertions(+) + +--- a/Documentation/devicetree/bindings/mfd/qcom-rpm.txt ++++ b/Documentation/devicetree/bindings/mfd/qcom-rpm.txt +@@ -12,6 +12,7 @@ frequencies. + "qcom,rpm-apq8064" + "qcom,rpm-msm8660" + "qcom,rpm-msm8960" ++ "qcom,rpm-ipq8064" + + - reg: + Usage: required +--- a/include/dt-bindings/mfd/qcom-rpm.h ++++ b/include/dt-bindings/mfd/qcom-rpm.h +@@ -141,6 +141,12 @@ + #define QCOM_RPM_SYS_FABRIC_MODE 131 + #define QCOM_RPM_USB_OTG_SWITCH 132 + #define QCOM_RPM_VDDMIN_GPIO 133 ++#define QCOM_RPM_NSS_FABRIC_0_CLK 134 ++#define QCOM_RPM_NSS_FABRIC_1_CLK 135 ++#define QCOM_RPM_SMB208_S1a 136 ++#define QCOM_RPM_SMB208_S1b 137 ++#define QCOM_RPM_SMB208_S2a 138 ++#define QCOM_RPM_SMB208_S2b 139 + + /* + * Constants used to select force mode for regulators. diff --git a/target/linux/ipq806x/patches-3.18/124-regulator-rpm-add-support-for-RPM-controller-SMB208.patch b/target/linux/ipq806x/patches-3.18/124-regulator-rpm-add-support-for-RPM-controller-SMB208.patch new file mode 100644 index 0000000..e4f094c --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/124-regulator-rpm-add-support-for-RPM-controller-SMB208.patch @@ -0,0 +1,58 @@ +From 0f5bb5b5de3b18877373f746bdb85d8ea0efeedf Mon Sep 17 00:00:00 2001 +From: Josh Cartwright +Date: Thu, 20 Nov 2014 13:41:25 -0600 +Subject: [PATCH] regulator: rpm: add support for RPM-controller SMB208 + +The IPQ8064 reference boards make use of SMB208 regulators which are +controlled by RPM. Implement support for these regulators in the RPM +regulator driver. + +Signed-off-by: Josh Cartwright +Acked-by: Bjorn Andersson +Signed-off-by: Mark Brown +--- + drivers/regulator/qcom_rpm-regulator.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/drivers/regulator/qcom_rpm-regulator.c ++++ b/drivers/regulator/qcom_rpm-regulator.c +@@ -183,6 +183,13 @@ static const struct regulator_linear_ran + REGULATOR_LINEAR_RANGE(1500000, 64, 100, 50000), + }; + ++static const struct regulator_linear_range smb208_ranges[] = { ++ REGULATOR_LINEAR_RANGE( 375000, 0, 29, 12500), ++ REGULATOR_LINEAR_RANGE( 750000, 30, 89, 12500), ++ REGULATOR_LINEAR_RANGE(1500000, 90, 153, 25000), ++ REGULATOR_LINEAR_RANGE(3100000, 154, 234, 25000), ++}; ++ + static const struct regulator_linear_range ncp_ranges[] = { + REGULATOR_LINEAR_RANGE(1500000, 0, 31, 50000), + }; +@@ -559,6 +566,16 @@ static const struct qcom_rpm_reg pm8921_ + .parts = &rpm8960_switch_parts, + }; + ++static const struct qcom_rpm_reg smb208_smps = { ++ .desc.linear_ranges = smb208_ranges, ++ .desc.n_linear_ranges = ARRAY_SIZE(smb208_ranges), ++ .desc.n_voltages = 235, ++ .desc.ops = &uV_ops, ++ .parts = &rpm8960_smps_parts, ++ .supports_force_mode_auto = false, ++ .supports_force_mode_bypass = false, ++}; ++ + static const struct of_device_id rpm_of_match[] = { + { .compatible = "qcom,rpm-pm8058-pldo", .data = &pm8058_pldo }, + { .compatible = "qcom,rpm-pm8058-nldo", .data = &pm8058_nldo }, +@@ -578,6 +595,8 @@ static const struct of_device_id rpm_of_ + { .compatible = "qcom,rpm-pm8921-ftsmps", .data = &pm8921_ftsmps }, + { .compatible = "qcom,rpm-pm8921-ncp", .data = &pm8921_ncp }, + { .compatible = "qcom,rpm-pm8921-switch", .data = &pm8921_switch }, ++ ++ { .compatible = "qcom,rpm-smb208", .data = &smb208_smps }, + { } + }; + MODULE_DEVICE_TABLE(of, rpm_of_match); diff --git a/target/linux/ipq806x/patches-3.18/125-regulator-qcom-rpm-Add-missing-state-flag-in-call-to.patch b/target/linux/ipq806x/patches-3.18/125-regulator-qcom-rpm-Add-missing-state-flag-in-call-to.patch new file mode 100644 index 0000000..48921a8 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/125-regulator-qcom-rpm-Add-missing-state-flag-in-call-to.patch @@ -0,0 +1,25 @@ +From 803926825fa4db007437f76654e3e63bafb9b906 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Wed, 26 Nov 2014 13:51:01 -0800 +Subject: [PATCH] regulator: qcom-rpm: Add missing state flag in call to RPM + +This adds the missing state parameter to the call down to the RPM. This +is currently hard coded to the active state, as that's all we're +supporting at this moment. + +Signed-off-by: Bjorn Andersson +Signed-off-by: Lee Jones +--- + drivers/regulator/qcom_rpm-regulator.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/regulator/qcom_rpm-regulator.c ++++ b/drivers/regulator/qcom_rpm-regulator.c +@@ -205,6 +205,7 @@ static int rpm_reg_write(struct qcom_rpm + vreg->val[req->word] |= value << req->shift; + + return qcom_rpm_write(vreg->rpm, ++ QCOM_RPM_ACTIVE_STATE, + vreg->resource, + vreg->val, + vreg->parts->request_len); diff --git a/target/linux/ipq806x/patches-3.18/126-add-rpm-to-ipq8064-dts.patch b/target/linux/ipq806x/patches-3.18/126-add-rpm-to-ipq8064-dts.patch new file mode 100644 index 0000000..7e4c5cb --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/126-add-rpm-to-ipq8064-dts.patch @@ -0,0 +1,87 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -2,6 +2,7 @@ + + #include "skeleton.dtsi" + #include ++#include + #include + #include + #include +@@ -76,6 +77,63 @@ + ranges; + compatible = "simple-bus"; + ++ rpm@108000 { ++ compatible = "qcom,rpm-ipq8064"; ++ reg = <0x108000 0x1000>; ++ qcom,ipc = <&l2cc 0x8 2>; ++ ++ interrupts = <0 19 0>, ++ <0 21 0>, ++ <0 22 0>; ++ interrupt-names = "ack", ++ "err", ++ "wakeup"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ smb208_s1a: smb208-s1a { ++ compatible = "qcom,rpm-smb208"; ++ reg = ; ++ ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ ++ }; ++ ++ smb208_s1b: smb208-s1b { ++ compatible = "qcom,rpm-smb208"; ++ reg = ; ++ ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: smb208-s2a { ++ compatible = "qcom,rpm-smb208"; ++ reg = ; ++ ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: smb208-s2b { ++ compatible = "qcom,rpm-smb208"; ++ reg = ; ++ ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++ + qcom_pinmux: pinmux@800000 { + compatible = "qcom,ipq8064-pinctrl"; + reg = <0x800000 0x4000>; +@@ -120,6 +178,12 @@ + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + ++ l2cc: clock-controller@2011000 { ++ compatible = "qcom,kpss-gcc", "syscon"; ++ reg = <0x2011000 0x1000>; ++ clock-output-names = "acpu_l2_aux"; ++ }; ++ + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; diff --git a/target/linux/ipq806x/patches-3.18/130-clk_mux-Fix-set_parent-doing-the-wrong-thing-when-IN.patch b/target/linux/ipq806x/patches-3.18/130-clk_mux-Fix-set_parent-doing-the-wrong-thing-when-IN.patch new file mode 100644 index 0000000..29f74b7 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/130-clk_mux-Fix-set_parent-doing-the-wrong-thing-when-IN.patch @@ -0,0 +1,55 @@ +From 6793b3cd5da817c4be218bd8632f07cf4d2b0d26 Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Wed, 19 Nov 2014 14:48:59 +0100 +Subject: [PATCH] clk_mux: Fix set_parent doing the wrong thing when INDEX_BIT + && index >= 3 + +If CLK_MUX_INDEX_BIT is set, then each bit turns on / off a single parent, +so theoretically multiple parents could be enabled at the same time, but in +practice only one bit should ever be 1. So to select parent 0, set +the register (*) to 0x01, to select parent 1 set it 0x02, parent 2, 0x04, +parent 3, 0x08, etc. + +But the current code does: + + if (mux->flags & CLK_MUX_INDEX_BIT) + index = (1 << ffs(index)); + +Which means that: + +For an input index of 0, ffs returns 0, so we set the register +to 0x01, ok. + +For an input index of 1, ffs returns 1, so we set the register +to 0x02, ok. + +For an input index of 2, ffs returns 2, so we set the register +to 0x04, ok. + +For an input index of 3, ffs returns 1, so we set the register +to 0x02, not good! + +The code should simply be: + + if (mux->flags & CLK_MUX_INDEX_BIT) + index = 1 << index; + +Which always does the right thing, this commit fixes this. + +Signed-off-by: Hans de Goede +Signed-off-by: Michael Turquette +--- + drivers/clk/clk-mux.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/clk-mux.c ++++ b/drivers/clk/clk-mux.c +@@ -77,7 +77,7 @@ static int clk_mux_set_parent(struct clk + + else { + if (mux->flags & CLK_MUX_INDEX_BIT) +- index = (1 << ffs(index)); ++ index = 1 << index; + + if (mux->flags & CLK_MUX_INDEX_ONE) + index++; diff --git a/target/linux/ipq806x/patches-3.18/131-clk-Add-__clk_mux_determine_rate_closest.patch b/target/linux/ipq806x/patches-3.18/131-clk-Add-__clk_mux_determine_rate_closest.patch new file mode 100644 index 0000000..18972f3 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/131-clk-Add-__clk_mux_determine_rate_closest.patch @@ -0,0 +1,120 @@ +From 15a02c1f6dd7c2bb150c61d00ffb33f584ff2288 Mon Sep 17 00:00:00 2001 +From: Stephen Boyd +Date: Mon, 19 Jan 2015 18:05:28 -0800 +Subject: [PATCH] clk: Add __clk_mux_determine_rate_closest + +Some clock drivers want to find the closest rate on the input of +a mux instead of a rate that's less than or equal to the desired +rate. Add a generic mux function to support this. + +Signed-off-by: Stephen Boyd +Tested-by: Kenneth Westfield +Signed-off-by: Michael Turquette +--- + drivers/clk/clk.c | 47 +++++++++++++++++++++++++++++++++++--------- + include/linux/clk-provider.h | 8 +++++++- + 2 files changed, 45 insertions(+), 10 deletions(-) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -695,14 +695,20 @@ struct clk *__clk_lookup(const char *nam + return NULL; + } + +-/* +- * Helper for finding best parent to provide a given frequency. This can be used +- * directly as a determine_rate callback (e.g. for a mux), or from a more +- * complex clock that may combine a mux with other operations. +- */ +-long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, +- unsigned long *best_parent_rate, +- struct clk **best_parent_p) ++static bool mux_is_better_rate(unsigned long rate, unsigned long now, ++ unsigned long best, unsigned long flags) ++{ ++ if (flags & CLK_MUX_ROUND_CLOSEST) ++ return abs(now - rate) < abs(best - rate); ++ ++ return now <= rate && now > best; ++} ++ ++static long ++clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate, ++ unsigned long *best_parent_rate, ++ struct clk **best_parent_p, ++ unsigned long flags) + { + struct clk *clk = hw->clk, *parent, *best_parent = NULL; + int i, num_parents; +@@ -730,7 +736,7 @@ long __clk_mux_determine_rate(struct clk + parent_rate = __clk_round_rate(parent, rate); + else + parent_rate = __clk_get_rate(parent); +- if (parent_rate <= rate && parent_rate > best) { ++ if (mux_is_better_rate(rate, parent_rate, best, flags)) { + best_parent = parent; + best = parent_rate; + } +@@ -743,8 +749,31 @@ out: + + return best; + } ++ ++/* ++ * Helper for finding best parent to provide a given frequency. This can be used ++ * directly as a determine_rate callback (e.g. for a mux), or from a more ++ * complex clock that may combine a mux with other operations. ++ */ ++long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *best_parent_rate, ++ struct clk **best_parent_p) ++{ ++ return clk_mux_determine_rate_flags(hw, rate, best_parent_rate, ++ best_parent_p, 0); ++} + EXPORT_SYMBOL_GPL(__clk_mux_determine_rate); + ++long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate, ++ unsigned long *best_parent_rate, ++ struct clk **best_parent_p) ++{ ++ return clk_mux_determine_rate_flags(hw, rate, best_parent_rate, ++ best_parent_p, ++ CLK_MUX_ROUND_CLOSEST); ++} ++EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest); ++ + /*** clk api ***/ + + void __clk_unprepare(struct clk *clk) +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -382,6 +382,8 @@ struct clk *clk_register_divider_table(s + * register, and mask of mux bits are in higher 16-bit of this register. + * While setting the mux bits, higher 16-bit should also be updated to + * indicate changing mux bits. ++ * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired ++ * frequency. + */ + struct clk_mux { + struct clk_hw hw; +@@ -396,7 +398,8 @@ struct clk_mux { + #define CLK_MUX_INDEX_ONE BIT(0) + #define CLK_MUX_INDEX_BIT BIT(1) + #define CLK_MUX_HIWORD_MASK BIT(2) +-#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ ++#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ ++#define CLK_MUX_ROUND_CLOSEST BIT(4) + + extern const struct clk_ops clk_mux_ops; + extern const struct clk_ops clk_mux_ro_ops; +@@ -554,6 +557,9 @@ struct clk *__clk_lookup(const char *nam + long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *best_parent_rate, + struct clk **best_parent_p); ++long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate, ++ unsigned long *best_parent_rate, ++ struct clk **best_parent_p); + + /* + * FIXME clock api without lock protection diff --git a/target/linux/ipq806x/patches-3.18/132-clk-Add-clk_unregister_-divider-gate-mux-to-close-me.patch b/target/linux/ipq806x/patches-3.18/132-clk-Add-clk_unregister_-divider-gate-mux-to-close-me.patch new file mode 100644 index 0000000..790f25d --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/132-clk-Add-clk_unregister_-divider-gate-mux-to-close-me.patch @@ -0,0 +1,115 @@ +From 4e3c021fb995bcbb5d1f814d00584cb80eb904a8 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Mon, 5 Jan 2015 10:52:40 +0100 +Subject: [PATCH] clk: Add clk_unregister_{divider, gate, mux} to close memory + leak + +The common clk_register_{divider,gate,mux} functions allocated memory +for internal data which wasn't freed anywhere. Drivers using these +helpers could only unregister clocks but the memory would still leak. + +Add corresponding unregister functions which will release all resources. + +Signed-off-by: Krzysztof Kozlowski +Reviewed-by: Stephen Boyd +Signed-off-by: Michael Turquette +--- + drivers/clk/clk-divider.c | 16 ++++++++++++++++ + drivers/clk/clk-gate.c | 16 ++++++++++++++++ + drivers/clk/clk-mux.c | 16 ++++++++++++++++ + include/linux/clk-provider.h | 4 ++++ + 4 files changed, 52 insertions(+) + +--- a/drivers/clk/clk-divider.c ++++ b/drivers/clk/clk-divider.c +@@ -461,3 +461,19 @@ struct clk *clk_register_divider_table(s + width, clk_divider_flags, table, lock); + } + EXPORT_SYMBOL_GPL(clk_register_divider_table); ++ ++void clk_unregister_divider(struct clk *clk) ++{ ++ struct clk_divider *div; ++ struct clk_hw *hw; ++ ++ hw = __clk_get_hw(clk); ++ if (!hw) ++ return; ++ ++ div = to_clk_divider(hw); ++ ++ clk_unregister(clk); ++ kfree(div); ++} ++EXPORT_SYMBOL_GPL(clk_unregister_divider); +--- a/drivers/clk/clk-gate.c ++++ b/drivers/clk/clk-gate.c +@@ -162,3 +162,19 @@ struct clk *clk_register_gate(struct dev + return clk; + } + EXPORT_SYMBOL_GPL(clk_register_gate); ++ ++void clk_unregister_gate(struct clk *clk) ++{ ++ struct clk_gate *gate; ++ struct clk_hw *hw; ++ ++ hw = __clk_get_hw(clk); ++ if (!hw) ++ return; ++ ++ gate = to_clk_gate(hw); ++ ++ clk_unregister(clk); ++ kfree(gate); ++} ++EXPORT_SYMBOL_GPL(clk_unregister_gate); +--- a/drivers/clk/clk-mux.c ++++ b/drivers/clk/clk-mux.c +@@ -177,3 +177,19 @@ struct clk *clk_register_mux(struct devi + NULL, lock); + } + EXPORT_SYMBOL_GPL(clk_register_mux); ++ ++void clk_unregister_mux(struct clk *clk) ++{ ++ struct clk_mux *mux; ++ struct clk_hw *hw; ++ ++ hw = __clk_get_hw(clk); ++ if (!hw) ++ return; ++ ++ mux = to_clk_mux(hw); ++ ++ clk_unregister(clk); ++ kfree(mux); ++} ++EXPORT_SYMBOL_GPL(clk_unregister_mux); +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -294,6 +294,7 @@ struct clk *clk_register_gate(struct dev + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); ++void clk_unregister_gate(struct clk *clk); + + struct clk_div_table { + unsigned int val; +@@ -361,6 +362,7 @@ struct clk *clk_register_divider_table(s + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock); ++void clk_unregister_divider(struct clk *clk); + + /** + * struct clk_mux - multiplexer clock +@@ -414,6 +416,8 @@ struct clk *clk_register_mux_table(struc + void __iomem *reg, u8 shift, u32 mask, + u8 clk_mux_flags, u32 *table, spinlock_t *lock); + ++void clk_unregister_mux(struct clk *clk); ++ + void of_fixed_factor_clk_setup(struct device_node *node); + + /** diff --git a/target/linux/ipq806x/patches-3.18/133-ARM-Add-Krait-L2-register-accessor-functions.patch b/target/linux/ipq806x/patches-3.18/133-ARM-Add-Krait-L2-register-accessor-functions.patch new file mode 100644 index 0000000..36a92c8 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/133-ARM-Add-Krait-L2-register-accessor-functions.patch @@ -0,0 +1,144 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,01/13] ARM: Add Krait L2 register accessor functions +From: Stephen Boyd +X-Patchwork-Id: 6063051 +Message-Id: <1426920332-9340-2-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , + Mark Rutland , Russell King , + Courtney Cavin +Date: Fri, 20 Mar 2015 23:45:20 -0700 + +Krait CPUs have a handful of L2 cache controller registers that +live behind a cp15 based indirection register. First you program +the indirection register (l2cpselr) to point the L2 'window' +register (l2cpdr) at what you want to read/write. Then you +read/write the 'window' register to do what you want. The +l2cpselr register is not banked per-cpu so we must lock around +accesses to it to prevent other CPUs from re-pointing l2cpdr +underneath us. + +Cc: Mark Rutland +Cc: Russell King +Cc: Courtney Cavin +Signed-off-by: Stephen Boyd + +--- +arch/arm/common/Kconfig | 3 ++ + arch/arm/common/Makefile | 1 + + arch/arm/common/krait-l2-accessors.c | 58 +++++++++++++++++++++++++++++++ + arch/arm/include/asm/krait-l2-accessors.h | 20 +++++++++++ + 4 files changed, 82 insertions(+) + create mode 100644 arch/arm/common/krait-l2-accessors.c + create mode 100644 arch/arm/include/asm/krait-l2-accessors.h + +--- a/arch/arm/common/Kconfig ++++ b/arch/arm/common/Kconfig +@@ -9,6 +9,9 @@ config DMABOUNCE + bool + select ZONE_DMA + ++config KRAIT_L2_ACCESSORS ++ bool ++ + config SHARP_LOCOMO + bool + +--- a/arch/arm/common/Makefile ++++ b/arch/arm/common/Makefile +@@ -7,6 +7,7 @@ obj-y += firmware.o + obj-$(CONFIG_ICST) += icst.o + obj-$(CONFIG_SA1111) += sa1111.o + obj-$(CONFIG_DMABOUNCE) += dmabounce.o ++obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o + obj-$(CONFIG_SHARP_LOCOMO) += locomo.o + obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o + obj-$(CONFIG_SHARP_SCOOP) += scoop.o +--- /dev/null ++++ b/arch/arm/common/krait-l2-accessors.c +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++ ++static DEFINE_RAW_SPINLOCK(krait_l2_lock); ++ ++void krait_set_l2_indirect_reg(u32 addr, u32 val) ++{ ++ unsigned long flags; ++ ++ raw_spin_lock_irqsave(&krait_l2_lock, flags); ++ /* ++ * Select the L2 window by poking l2cpselr, then write to the window ++ * via l2cpdr. ++ */ ++ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr)); ++ isb(); ++ asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val)); ++ isb(); ++ ++ raw_spin_unlock_irqrestore(&krait_l2_lock, flags); ++} ++EXPORT_SYMBOL(krait_set_l2_indirect_reg); ++ ++u32 krait_get_l2_indirect_reg(u32 addr) ++{ ++ u32 val; ++ unsigned long flags; ++ ++ raw_spin_lock_irqsave(&krait_l2_lock, flags); ++ /* ++ * Select the L2 window by poking l2cpselr, then read from the window ++ * via l2cpdr. ++ */ ++ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr)); ++ isb(); ++ asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val)); ++ ++ raw_spin_unlock_irqrestore(&krait_l2_lock, flags); ++ ++ return val; ++} ++EXPORT_SYMBOL(krait_get_l2_indirect_reg); +--- /dev/null ++++ b/arch/arm/include/asm/krait-l2-accessors.h +@@ -0,0 +1,20 @@ ++/* ++ * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H ++#define __ASMARM_KRAIT_L2_ACCESSORS_H ++ ++extern void krait_set_l2_indirect_reg(u32 addr, u32 val); ++extern u32 krait_get_l2_indirect_reg(u32 addr); ++ ++#endif diff --git a/target/linux/ipq806x/patches-3.18/134-clk-mux-Split-out-register-accessors-for-reuse.patch b/target/linux/ipq806x/patches-3.18/134-clk-mux-Split-out-register-accessors-for-reuse.patch new file mode 100644 index 0000000..50022e6 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/134-clk-mux-Split-out-register-accessors-for-reuse.patch @@ -0,0 +1,192 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,02/13] clk: mux: Split out register accessors for reuse +From: Stephen Boyd +X-Patchwork-Id: 6063111 +Message-Id: <1426920332-9340-3-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:21 -0700 + +We want to reuse the logic in clk-mux.c for other clock drivers +that don't use readl as register accessors. Fortunately, there +really isn't much to the mux code besides the table indirection +and quirk flags if you assume any bit shifting and masking has +been done already. Pull that logic out into reusable functions +that operate on an optional table and some flags so that other +drivers can use the same logic. + +Signed-off-by: Stephen Boyd + +--- +drivers/clk/clk-mux.c | 76 +++++++++++++++++++++++++++----------------- + include/linux/clk-provider.h | 9 ++++-- + 2 files changed, 54 insertions(+), 31 deletions(-) + +--- a/drivers/clk/clk-mux.c ++++ b/drivers/clk/clk-mux.c +@@ -29,35 +29,24 @@ + + #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) + +-static u8 clk_mux_get_parent(struct clk_hw *hw) ++unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val, ++ unsigned int *table, unsigned long flags) + { +- struct clk_mux *mux = to_clk_mux(hw); + int num_parents = __clk_get_num_parents(hw->clk); +- u32 val; + +- /* +- * FIXME need a mux-specific flag to determine if val is bitwise or numeric +- * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 +- * to 0x7 (index starts at one) +- * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so +- * val = 0x4 really means "bit 2, index starts at bit 0" +- */ +- val = clk_readl(mux->reg) >> mux->shift; +- val &= mux->mask; +- +- if (mux->table) { ++ if (table) { + int i; + + for (i = 0; i < num_parents; i++) +- if (mux->table[i] == val) ++ if (table[i] == val) + return i; + return -EINVAL; + } + +- if (val && (mux->flags & CLK_MUX_INDEX_BIT)) ++ if (val && (flags & CLK_MUX_INDEX_BIT)) + val = ffs(val) - 1; + +- if (val && (mux->flags & CLK_MUX_INDEX_ONE)) ++ if (val && (flags & CLK_MUX_INDEX_ONE)) + val--; + + if (val >= num_parents) +@@ -65,24 +54,53 @@ static u8 clk_mux_get_parent(struct clk_ + + return val; + } ++EXPORT_SYMBOL_GPL(clk_mux_get_parent); + +-static int clk_mux_set_parent(struct clk_hw *hw, u8 index) ++static u8 _clk_mux_get_parent(struct clk_hw *hw) + { + struct clk_mux *mux = to_clk_mux(hw); + u32 val; +- unsigned long flags = 0; + +- if (mux->table) +- index = mux->table[index]; ++ /* ++ * FIXME need a mux-specific flag to determine if val is bitwise or numeric ++ * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 ++ * to 0x7 (index starts at one) ++ * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so ++ * val = 0x4 really means "bit 2, index starts at bit 0" ++ */ ++ val = clk_readl(mux->reg) >> mux->shift; ++ val &= mux->mask; ++ ++ return clk_mux_get_parent(hw, val, mux->table, mux->flags); ++} + +- else { +- if (mux->flags & CLK_MUX_INDEX_BIT) +- index = 1 << index; ++unsigned int clk_mux_reindex(u8 index, unsigned int *table, ++ unsigned long flags) ++{ ++ unsigned int val = index; + +- if (mux->flags & CLK_MUX_INDEX_ONE) +- index++; ++ if (table) { ++ val = table[val]; ++ } else { ++ if (flags & CLK_MUX_INDEX_BIT) ++ val = 1 << index; ++ ++ if (flags & CLK_MUX_INDEX_ONE) ++ val++; + } + ++ return val; ++} ++EXPORT_SYMBOL_GPL(clk_mux_reindex); ++ ++static int clk_mux_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct clk_mux *mux = to_clk_mux(hw); ++ u32 val; ++ unsigned long flags = 0; ++ ++ index = clk_mux_reindex(index, mux->table, mux->flags); ++ + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + +@@ -102,21 +120,21 @@ static int clk_mux_set_parent(struct clk + } + + const struct clk_ops clk_mux_ops = { +- .get_parent = clk_mux_get_parent, ++ .get_parent = _clk_mux_get_parent, + .set_parent = clk_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, + }; + EXPORT_SYMBOL_GPL(clk_mux_ops); + + const struct clk_ops clk_mux_ro_ops = { +- .get_parent = clk_mux_get_parent, ++ .get_parent = _clk_mux_get_parent, + }; + EXPORT_SYMBOL_GPL(clk_mux_ro_ops); + + struct clk *clk_register_mux_table(struct device *dev, const char *name, + const char **parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u32 mask, +- u8 clk_mux_flags, u32 *table, spinlock_t *lock) ++ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock) + { + struct clk_mux *mux; + struct clk *clk; +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -390,7 +390,7 @@ void clk_unregister_divider(struct clk * + struct clk_mux { + struct clk_hw hw; + void __iomem *reg; +- u32 *table; ++ unsigned int *table; + u32 mask; + u8 shift; + u8 flags; +@@ -406,6 +406,11 @@ struct clk_mux { + extern const struct clk_ops clk_mux_ops; + extern const struct clk_ops clk_mux_ro_ops; + ++unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val, ++ unsigned int *table, unsigned long flags); ++unsigned int clk_mux_reindex(u8 index, unsigned int *table, ++ unsigned long flags); ++ + struct clk *clk_register_mux(struct device *dev, const char *name, + const char **parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, +@@ -414,7 +419,7 @@ struct clk *clk_register_mux(struct devi + struct clk *clk_register_mux_table(struct device *dev, const char *name, + const char **parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u32 mask, +- u8 clk_mux_flags, u32 *table, spinlock_t *lock); ++ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock); + + void clk_unregister_mux(struct clk *clk); + diff --git a/target/linux/ipq806x/patches-3.18/135-clk-Avoid-sending-high-rates-to-downstream-clocks-during-set_rate.patch b/target/linux/ipq806x/patches-3.18/135-clk-Avoid-sending-high-rates-to-downstream-clocks-during-set_rate.patch new file mode 100644 index 0000000..02d96ad --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/135-clk-Avoid-sending-high-rates-to-downstream-clocks-during-set_rate.patch @@ -0,0 +1,129 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3, 03/13] clk: Avoid sending high rates to downstream clocks during + set_rate +From: Stephen Boyd +X-Patchwork-Id: 6063271 +Message-Id: <1426920332-9340-4-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:22 -0700 + +If a clock is on and we call clk_set_rate() on it we may get into +a situation where the clock temporarily increases in rate +dramatically while we walk the tree and call .set_rate() ops. For +example, consider a case where a PLL feeds into a divider. +Initially the divider is set to divide by 1 and the PLL is +running fairly slow (100MHz). The downstream consumer of the +divider output can only handle rates =< 400 MHz, but the divider +can only choose between divisors of 1 and 4. + + +-----+ +----------------+ + | PLL |-->| div 1 or div 4 |---> consumer device + +-----+ +----------------+ + +To achieve a rate of 400MHz on the output of the divider, we +would have to set the rate of the PLL to 1.6 GHz and then divide +it by 4. The current code would set the PLL to 1.6GHz first while +the divider is still set to 1, thus causing the downstream +consumer of the clock to receive a few clock cycles of 1.6GHz +clock (far beyond it's maximum acceptable rate). We should be +changing the divider first before increasing the PLL rate to +avoid this problem. + +Therefore, set the rate of any child clocks that are increasing +in rate from their current rate so that they can increase their +dividers if necessary. We assume that there isn't such a thing as +minimum rate requirements. + +Signed-off-by: Stephen Boyd + +--- +drivers/clk/clk.c | 34 ++++++++++++++++++++++------------ + 1 file changed, 22 insertions(+), 12 deletions(-) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -1476,21 +1476,23 @@ static struct clk *clk_propagate_rate_ch + * walk down a subtree and set the new rates notifying the rate + * change on the way + */ +-static void clk_change_rate(struct clk *clk) ++static void clk_change_rate(struct clk *clk, unsigned long best_parent_rate) + { + struct clk *child; + struct hlist_node *tmp; + unsigned long old_rate; +- unsigned long best_parent_rate = 0; + bool skip_set_rate = false; + struct clk *old_parent; + +- old_rate = clk->rate; ++ hlist_for_each_entry(child, &clk->children, child_node) { ++ /* Skip children who will be reparented to another clock */ ++ if (child->new_parent && child->new_parent != clk) ++ continue; ++ if (child->new_rate > child->rate) ++ clk_change_rate(child, clk->new_rate); ++ } + +- if (clk->new_parent) +- best_parent_rate = clk->new_parent->rate; +- else if (clk->parent) +- best_parent_rate = clk->parent->rate; ++ old_rate = clk->rate; + + if (clk->new_parent && clk->new_parent != clk->parent) { + old_parent = __clk_set_parent_before(clk, clk->new_parent); +@@ -1510,7 +1512,7 @@ static void clk_change_rate(struct clk * + if (!skip_set_rate && clk->ops->set_rate) + clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate); + +- clk->rate = clk_recalc(clk, best_parent_rate); ++ clk->rate = clk->new_rate; + + if (clk->notifier_count && old_rate != clk->rate) + __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); +@@ -1523,12 +1525,13 @@ static void clk_change_rate(struct clk * + /* Skip children who will be reparented to another clock */ + if (child->new_parent && child->new_parent != clk) + continue; +- clk_change_rate(child); ++ if (child->new_rate != child->rate) ++ clk_change_rate(child, clk->new_rate); + } + + /* handle the new child who might not be in clk->children yet */ +- if (clk->new_child) +- clk_change_rate(clk->new_child); ++ if (clk->new_child && clk->new_child->new_rate != clk->new_child->rate) ++ clk_change_rate(clk->new_child, clk->new_rate); + } + + /** +@@ -1556,6 +1559,7 @@ int clk_set_rate(struct clk *clk, unsign + { + struct clk *top, *fail_clk; + int ret = 0; ++ unsigned long parent_rate; + + if (!clk) + return 0; +@@ -1589,8 +1593,13 @@ int clk_set_rate(struct clk *clk, unsign + goto out; + } + ++ if (top->parent) ++ parent_rate = top->parent->rate; ++ else ++ parent_rate = 0; ++ + /* change the rates */ +- clk_change_rate(top); ++ clk_change_rate(top, parent_rate); + + out: + clk_prepare_unlock(); diff --git a/target/linux/ipq806x/patches-3.18/136-clk-Add-safe-switch-hook.patch b/target/linux/ipq806x/patches-3.18/136-clk-Add-safe-switch-hook.patch new file mode 100644 index 0000000..227f8ce --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/136-clk-Add-safe-switch-hook.patch @@ -0,0 +1,170 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,04/13] clk: Add safe switch hook +From: Stephen Boyd +X-Patchwork-Id: 6063211 +Message-Id: <1426920332-9340-5-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:23 -0700 + +Sometimes clocks can't accept their parent source turning off +while the source is reprogrammed to a different rate. Most +notably CPU clocks require a way to switch away from the current +PLL they're running on, reprogram that PLL to a new rate, and +then switch back to the PLL with the new rate once they're done. +Add a hook that drivers can implement allowing them to return a +'safe parent' that they can switch their parent to while the +upstream source is reprogrammed to support this. + +Signed-off-by: Stephen Boyd + +--- +This patch is good enough for Krait, but soon I'll need to +support a "safe rate" where we ask a clock what rate it needs to be running +at to be sure it's within voltage constraints. Right now safe parent +handles that problem on Krait, but on other platforms it won't work. + + drivers/clk/clk.c | 61 ++++++++++++++++++++++++++++++++++++++------ + include/linux/clk-provider.h | 1 + + 2 files changed, 54 insertions(+), 8 deletions(-) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -1350,7 +1350,8 @@ out: + static void clk_calc_subtree(struct clk *clk, unsigned long new_rate, + struct clk *new_parent, u8 p_index) + { +- struct clk *child; ++ struct clk *child, *parent; ++ struct clk_hw *parent_hw; + + clk->new_rate = new_rate; + clk->new_parent = new_parent; +@@ -1360,6 +1361,18 @@ static void clk_calc_subtree(struct clk + if (new_parent && new_parent != clk->parent) + new_parent->new_child = clk; + ++ if (clk->ops->get_safe_parent) { ++ parent_hw = clk->ops->get_safe_parent(clk->hw); ++ if (parent_hw) { ++ parent = parent_hw->clk; ++ p_index = clk_fetch_parent_index(clk, parent); ++ clk->safe_parent_index = p_index; ++ clk->safe_parent = parent; ++ } ++ } else { ++ clk->safe_parent = NULL; ++ } ++ + hlist_for_each_entry(child, &clk->children, child_node) { + child->new_rate = clk_recalc(child, new_rate); + clk_calc_subtree(child, child->new_rate, NULL, 0); +@@ -1439,17 +1452,47 @@ out: + * so that in case of an error we can walk down the whole tree again and + * abort the change. + */ +-static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long event) ++static struct clk *clk_propagate_rate_change(struct clk *clk, ++ unsigned long event) + { + struct clk *child, *tmp_clk, *fail_clk = NULL; ++ struct clk *old_parent; + int ret = NOTIFY_DONE; + +- if (clk->rate == clk->new_rate) ++ if (clk->rate == clk->new_rate && event != POST_RATE_CHANGE) + return NULL; + ++ switch (event) { ++ case PRE_RATE_CHANGE: ++ if (clk->safe_parent) ++ clk->ops->set_parent(clk->hw, clk->safe_parent_index); ++ clk->old_rate = clk->rate; ++ break; ++ case POST_RATE_CHANGE: ++ if (clk->safe_parent) { ++ old_parent = __clk_set_parent_before(clk, ++ clk->new_parent); ++ if (clk->ops->set_rate_and_parent) { ++ clk->ops->set_rate_and_parent(clk->hw, ++ clk->new_rate, ++ clk->new_parent ? ++ clk->new_parent->rate : 0, ++ clk->new_parent_index); ++ } else if (clk->ops->set_parent) { ++ clk->ops->set_parent(clk->hw, ++ clk->new_parent_index); ++ } ++ __clk_set_parent_after(clk, clk->new_parent, ++ old_parent); ++ } ++ break; ++ } ++ + if (clk->notifier_count) { +- ret = __clk_notify(clk, event, clk->rate, clk->new_rate); +- if (ret & NOTIFY_STOP_MASK) ++ if (event != POST_RATE_CHANGE || clk->old_rate != clk->rate) ++ ret = __clk_notify(clk, event, clk->old_rate, ++ clk->new_rate); ++ if (ret & NOTIFY_STOP_MASK && event != POST_RATE_CHANGE) + fail_clk = clk; + } + +@@ -1494,7 +1537,8 @@ static void clk_change_rate(struct clk * + + old_rate = clk->rate; + +- if (clk->new_parent && clk->new_parent != clk->parent) { ++ if (clk->new_parent && clk->new_parent != clk->parent && ++ !clk->safe_parent) { + old_parent = __clk_set_parent_before(clk, clk->new_parent); + + if (clk->ops->set_rate_and_parent) { +@@ -1514,9 +1558,6 @@ static void clk_change_rate(struct clk * + + clk->rate = clk->new_rate; + +- if (clk->notifier_count && old_rate != clk->rate) +- __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); +- + /* + * Use safe iteration, as change_rate can actually swap parents + * for certain clock types. +@@ -1601,6 +1642,8 @@ int clk_set_rate(struct clk *clk, unsign + /* change the rates */ + clk_change_rate(top, parent_rate); + ++ clk_propagate_rate_change(top, POST_RATE_CHANGE); ++ + out: + clk_prepare_unlock(); + +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -179,6 +179,7 @@ struct clk_ops { + struct clk **best_parent_clk); + int (*set_parent)(struct clk_hw *hw, u8 index); + u8 (*get_parent)(struct clk_hw *hw); ++ struct clk_hw *(*get_safe_parent)(struct clk_hw *hw); + int (*set_rate)(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); + int (*set_rate_and_parent)(struct clk_hw *hw, +--- a/include/linux/clk-private.h ++++ b/include/linux/clk-private.h +@@ -38,8 +38,11 @@ struct clk { + struct clk **parents; + u8 num_parents; + u8 new_parent_index; ++ u8 safe_parent_index; + unsigned long rate; ++ unsigned long old_rate; + unsigned long new_rate; ++ struct clk *safe_parent; + struct clk *new_parent; + struct clk *new_child; + unsigned long flags; diff --git a/target/linux/ipq806x/patches-3.18/137-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch b/target/linux/ipq806x/patches-3.18/137-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch new file mode 100644 index 0000000..701d5e7 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/137-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch @@ -0,0 +1,351 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,05/13] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) +From: Stephen Boyd +X-Patchwork-Id: 6063261 +Message-Id: <1426920332-9340-6-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:24 -0700 + +HFPLLs are the main frequency source for Krait CPU clocks. Add +support for changing the rate of these PLLs. + +Signed-off-by: Stephen Boyd + +--- +I'd really like to get rid of __clk_hfpll_init_once() if possible... + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/clk-hfpll.c | 253 +++++++++++++++++++++++++++++++++++++++++++ + drivers/clk/qcom/clk-hfpll.h | 54 +++++++++ + 3 files changed, 308 insertions(+) + create mode 100644 drivers/clk/qcom/clk-hfpll.c + create mode 100644 drivers/clk/qcom/clk-hfpll.h + +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -6,6 +6,7 @@ clk-qcom-y += clk-pll.o + clk-qcom-y += clk-rcg.o + clk-qcom-y += clk-rcg2.o + clk-qcom-y += clk-branch.o ++clk-qcom-y += clk-hfpll.o + clk-qcom-y += reset.o + + obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o +--- /dev/null ++++ b/drivers/clk/qcom/clk-hfpll.c +@@ -0,0 +1,253 @@ ++/* ++ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-regmap.h" ++#include "clk-hfpll.h" ++ ++#define PLL_OUTCTRL BIT(0) ++#define PLL_BYPASSNL BIT(1) ++#define PLL_RESET_N BIT(2) ++ ++/* Initialize a HFPLL at a given rate and enable it. */ ++static void __clk_hfpll_init_once(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ ++ if (likely(h->init_done)) ++ return; ++ ++ /* Configure PLL parameters for integer mode. */ ++ if (hd->config_val) ++ regmap_write(regmap, hd->config_reg, hd->config_val); ++ regmap_write(regmap, hd->m_reg, 0); ++ regmap_write(regmap, hd->n_reg, 1); ++ ++ if (hd->user_reg) { ++ u32 regval = hd->user_val; ++ unsigned long rate; ++ ++ rate = __clk_get_rate(hw->clk); ++ ++ /* Pick the right VCO. */ ++ if (hd->user_vco_mask && rate > hd->low_vco_max_rate) ++ regval |= hd->user_vco_mask; ++ regmap_write(regmap, hd->user_reg, regval); ++ } ++ ++ if (hd->droop_reg) ++ regmap_write(regmap, hd->droop_reg, hd->droop_val); ++ ++ h->init_done = true; ++} ++ ++static void __clk_hfpll_enable(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 val; ++ ++ __clk_hfpll_init_once(hw); ++ ++ /* Disable PLL bypass mode. */ ++ regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); ++ ++ /* ++ * H/W requires a 5us delay between disabling the bypass and ++ * de-asserting the reset. Delay 10us just to be safe. ++ */ ++ udelay(10); ++ ++ /* De-assert active-low PLL reset. */ ++ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); ++ ++ /* Wait for PLL to lock. */ ++ if (hd->status_reg) { ++ do { ++ regmap_read(regmap, hd->status_reg, &val); ++ } while (!(val & BIT(hd->lock_bit))); ++ } else { ++ udelay(60); ++ } ++ ++ /* Enable PLL output. */ ++ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); ++} ++ ++/* Enable an already-configured HFPLL. */ ++static int clk_hfpll_enable(struct clk_hw *hw) ++{ ++ unsigned long flags; ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 mode; ++ ++ spin_lock_irqsave(&h->lock, flags); ++ regmap_read(regmap, hd->mode_reg, &mode); ++ if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) ++ __clk_hfpll_enable(hw); ++ spin_unlock_irqrestore(&h->lock, flags); ++ ++ return 0; ++} ++ ++static void __clk_hfpll_disable(struct clk_hfpll *h) ++{ ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ ++ /* ++ * Disable the PLL output, disable test mode, enable the bypass mode, ++ * and assert the reset. ++ */ ++ regmap_update_bits(regmap, hd->mode_reg, ++ PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); ++} ++ ++static void clk_hfpll_disable(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&h->lock, flags); ++ __clk_hfpll_disable(h); ++ spin_unlock_irqrestore(&h->lock, flags); ++} ++ ++static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ unsigned long rrate; ++ ++ rate = clamp(rate, hd->min_rate, hd->max_rate); ++ ++ rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate; ++ if (rrate > hd->max_rate) ++ rrate -= *parent_rate; ++ ++ return rrate; ++} ++ ++/* ++ * For optimization reasons, assumes no downstream clocks are actively using ++ * it. ++ */ ++static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ unsigned long flags; ++ u32 l_val, val; ++ bool enabled; ++ ++ l_val = rate / parent_rate; ++ ++ spin_lock_irqsave(&h->lock, flags); ++ ++ enabled = __clk_is_enabled(hw->clk); ++ if (enabled) ++ __clk_hfpll_disable(h); ++ ++ /* Pick the right VCO. */ ++ if (hd->user_reg && hd->user_vco_mask) { ++ regmap_read(regmap, hd->user_reg, &val); ++ if (rate <= hd->low_vco_max_rate) ++ val &= ~hd->user_vco_mask; ++ else ++ val |= hd->user_vco_mask; ++ regmap_write(regmap, hd->user_reg, val); ++ } ++ ++ regmap_write(regmap, hd->l_reg, l_val); ++ ++ if (enabled) ++ __clk_hfpll_enable(hw); ++ ++ spin_unlock_irqrestore(&h->lock, flags); ++ ++ return 0; ++} ++ ++static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 l_val; ++ ++ regmap_read(regmap, hd->l_reg, &l_val); ++ ++ return l_val * parent_rate; ++} ++ ++static void clk_hfpll_init(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 mode, status; ++ ++ regmap_read(regmap, hd->mode_reg, &mode); ++ if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { ++ __clk_hfpll_init_once(hw); ++ return; ++ } ++ ++ if (hd->status_reg) { ++ regmap_read(regmap, hd->status_reg, &status); ++ if (!(status & BIT(hd->lock_bit))) { ++ WARN(1, "HFPLL %s is ON, but not locked!\n", ++ __clk_get_name(hw->clk)); ++ clk_hfpll_disable(hw); ++ __clk_hfpll_init_once(hw); ++ } ++ } ++} ++ ++static int hfpll_is_enabled(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 mode; ++ ++ regmap_read(regmap, hd->mode_reg, &mode); ++ mode &= 0x7; ++ return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); ++} ++ ++const struct clk_ops clk_ops_hfpll = { ++ .enable = clk_hfpll_enable, ++ .disable = clk_hfpll_disable, ++ .is_enabled = hfpll_is_enabled, ++ .round_rate = clk_hfpll_round_rate, ++ .set_rate = clk_hfpll_set_rate, ++ .recalc_rate = clk_hfpll_recalc_rate, ++ .init = clk_hfpll_init, ++}; ++EXPORT_SYMBOL_GPL(clk_ops_hfpll); +--- /dev/null ++++ b/drivers/clk/qcom/clk-hfpll.h +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#ifndef __QCOM_CLK_HFPLL_H__ ++#define __QCOM_CLK_HFPLL_H__ ++ ++#include ++#include ++#include "clk-regmap.h" ++ ++struct hfpll_data { ++ u32 mode_reg; ++ u32 l_reg; ++ u32 m_reg; ++ u32 n_reg; ++ u32 user_reg; ++ u32 droop_reg; ++ u32 config_reg; ++ u32 status_reg; ++ u8 lock_bit; ++ ++ u32 droop_val; ++ u32 config_val; ++ u32 user_val; ++ u32 user_vco_mask; ++ unsigned long low_vco_max_rate; ++ ++ unsigned long min_rate; ++ unsigned long max_rate; ++}; ++ ++struct clk_hfpll { ++ struct hfpll_data const *d; ++ int init_done; ++ ++ struct clk_regmap clkr; ++ spinlock_t lock; ++}; ++ ++#define to_clk_hfpll(_hw) \ ++ container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr) ++ ++extern const struct clk_ops clk_ops_hfpll; ++ ++#endif diff --git a/target/linux/ipq806x/patches-3.18/138-clk-qcom-Add-HFPLL-driver.patch b/target/linux/ipq806x/patches-3.18/138-clk-qcom-Add-HFPLL-driver.patch new file mode 100644 index 0000000..a0b1d64 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/138-clk-qcom-Add-HFPLL-driver.patch @@ -0,0 +1,206 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,06/13] clk: qcom: Add HFPLL driver +From: Stephen Boyd +X-Patchwork-Id: 6063231 +Message-Id: <1426920332-9340-7-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , +Date: Fri, 20 Mar 2015 23:45:25 -0700 + +On some devices (MSM8974 for example), the HFPLLs are +instantiated within the Krait processor subsystem as separate +register regions. Add a driver for these PLLs so that we can +provide HFPLL clocks for use by the system. + +Cc: +Signed-off-by: Stephen Boyd + +--- +.../devicetree/bindings/clock/qcom,hfpll.txt | 40 ++++++++ + drivers/clk/qcom/Kconfig | 8 ++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/hfpll.c | 109 +++++++++++++++++++++ + 4 files changed, 158 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt + create mode 100644 drivers/clk/qcom/hfpll.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt +@@ -0,0 +1,40 @@ ++High-Frequency PLL (HFPLL) ++ ++PROPERTIES ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: must be "qcom,hfpll" ++ ++- reg: ++ Usage: required ++ Value type: ++ Definition: address and size of HPLL registers. An optional second ++ element specifies the address and size of the alias ++ register region. ++ ++- clock-output-names: ++ Usage: required ++ Value type: ++ Definition: Name of the PLL. Typically hfpllX where X is a CPU number ++ starting at 0. Otherwise hfpll_Y where Y is more specific ++ such as "l2". ++ ++Example: ++ ++1) An HFPLL for the L2 cache. ++ ++ clock-controller@f9016000 { ++ compatible = "qcom,hfpll"; ++ reg = <0xf9016000 0x30>; ++ clock-output-names = "hfpll_l2"; ++ }; ++ ++2) An HFPLL for CPU0. This HFPLL has the alias register region. ++ ++ clock-controller@f908a000 { ++ compatible = "qcom,hfpll"; ++ reg = <0xf908a000 0x30>, <0xf900a000 0x30>; ++ clock-output-names = "hfpll0"; ++ }; +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -70,3 +70,11 @@ config MSM_MMCC_8974 + Support for the multimedia clock controller on msm8974 devices. + Say Y if you want to support multimedia devices such as display, + graphics, video encode/decode, camera, etc. ++ ++config QCOM_HFPLL ++ tristate "High-Frequency PLL (HFPLL) Clock Controller" ++ depends on COMMON_CLK_QCOM ++ help ++ Support for the high-frequency PLLs present on Qualcomm devices. ++ Say Y if you want to support CPU frequency scaling on devices ++ such as MSM8974, APQ8084, etc. +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -17,3 +17,4 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm896 + obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o + obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o + obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o ++obj-$(CONFIG_QCOM_HFPLL) += hfpll.o +--- /dev/null ++++ b/drivers/clk/qcom/hfpll.c +@@ -0,0 +1,109 @@ ++/* ++ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-regmap.h" ++#include "clk-hfpll.h" ++ ++static const struct hfpll_data hdata = { ++ .mode_reg = 0x00, ++ .l_reg = 0x04, ++ .m_reg = 0x08, ++ .n_reg = 0x0c, ++ .user_reg = 0x10, ++ .config_reg = 0x14, ++ .config_val = 0x430405d, ++ .status_reg = 0x1c, ++ .lock_bit = 16, ++ ++ .user_val = 0x8, ++ .user_vco_mask = 0x100000, ++ .low_vco_max_rate = 1248000000, ++ .min_rate = 537600000UL, ++ .max_rate = 2900000000UL, ++}; ++ ++static const struct of_device_id qcom_hfpll_match_table[] = { ++ { .compatible = "qcom,hfpll" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table); ++ ++static const struct regmap_config hfpll_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x30, ++ .fast_io = true, ++}; ++ ++static int qcom_hfpll_probe(struct platform_device *pdev) ++{ ++ struct clk *clk; ++ struct resource *res; ++ struct device *dev = &pdev->dev; ++ void __iomem *base; ++ struct regmap *regmap; ++ struct clk_hfpll *h; ++ struct clk_init_data init = { ++ .parent_names = (const char *[]){ "xo" }, ++ .num_parents = 1, ++ .ops = &clk_ops_hfpll, ++ }; ++ ++ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL); ++ if (!h) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ if (of_property_read_string_index(dev->of_node, "clock-output-names", ++ 0, &init.name)) ++ return -ENODEV; ++ ++ h->d = &hdata; ++ h->clkr.hw.init = &init; ++ spin_lock_init(&h->lock); ++ ++ clk = devm_clk_register_regmap(&pdev->dev, &h->clkr); ++ ++ return PTR_ERR_OR_ZERO(clk); ++} ++ ++static struct platform_driver qcom_hfpll_driver = { ++ .probe = qcom_hfpll_probe, ++ .driver = { ++ .name = "qcom-hfpll", ++ .of_match_table = qcom_hfpll_match_table, ++ }, ++}; ++module_platform_driver(qcom_hfpll_driver); ++ ++MODULE_DESCRIPTION("QCOM HFPLL Clock Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:qcom-hfpll"); diff --git a/target/linux/ipq806x/patches-3.18/139-clk-qcom-Add-IPQ806X-s-HFPLLs.patch b/target/linux/ipq806x/patches-3.18/139-clk-qcom-Add-IPQ806X-s-HFPLLs.patch new file mode 100644 index 0000000..7fd53d1 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/139-clk-qcom-Add-IPQ806X-s-HFPLLs.patch @@ -0,0 +1,127 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,08/13] clk: qcom: Add IPQ806X's HFPLLs +From: Stephen Boyd +X-Patchwork-Id: 6063241 +Message-Id: <1426920332-9340-9-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:27 -0700 + +Describe the HFPLLs present on IPQ806X devices. + +Signed-off-by: Stephen Boyd + +--- +drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 83 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -30,6 +30,7 @@ + #include "clk-pll.h" + #include "clk-rcg.h" + #include "clk-branch.h" ++#include "clk-hfpll.h" + #include "reset.h" + + static struct clk_pll pll0 = { +@@ -102,6 +103,85 @@ static struct clk_regmap pll8_vote = { + }, + }; + ++static struct hfpll_data hfpll0_data = { ++ .mode_reg = 0x3200, ++ .l_reg = 0x3208, ++ .m_reg = 0x320c, ++ .n_reg = 0x3210, ++ .config_reg = 0x3204, ++ .status_reg = 0x321c, ++ .config_val = 0x7845c665, ++ .droop_reg = 0x3214, ++ .droop_val = 0x0108c000, ++ .min_rate = 600000000UL, ++ .max_rate = 1800000000UL, ++}; ++ ++static struct clk_hfpll hfpll0 = { ++ .d = &hfpll0_data, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .parent_names = (const char *[]){ "pxo" }, ++ .num_parents = 1, ++ .name = "hfpll0", ++ .ops = &clk_ops_hfpll, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock), ++}; ++ ++static struct hfpll_data hfpll1_data = { ++ .mode_reg = 0x3240, ++ .l_reg = 0x3248, ++ .m_reg = 0x324c, ++ .n_reg = 0x3250, ++ .config_reg = 0x3244, ++ .status_reg = 0x325c, ++ .config_val = 0x7845c665, ++ .droop_reg = 0x3314, ++ .droop_val = 0x0108c000, ++ .min_rate = 600000000UL, ++ .max_rate = 1800000000UL, ++}; ++ ++static struct clk_hfpll hfpll1 = { ++ .d = &hfpll1_data, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .parent_names = (const char *[]){ "pxo" }, ++ .num_parents = 1, ++ .name = "hfpll1", ++ .ops = &clk_ops_hfpll, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock), ++}; ++ ++static struct hfpll_data hfpll_l2_data = { ++ .mode_reg = 0x3300, ++ .l_reg = 0x3308, ++ .m_reg = 0x330c, ++ .n_reg = 0x3310, ++ .config_reg = 0x3304, ++ .status_reg = 0x331c, ++ .config_val = 0x7845c665, ++ .droop_reg = 0x3314, ++ .droop_val = 0x0108c000, ++ .min_rate = 600000000UL, ++ .max_rate = 1800000000UL, ++}; ++ ++static struct clk_hfpll hfpll_l2 = { ++ .d = &hfpll_l2_data, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .parent_names = (const char *[]){ "pxo" }, ++ .num_parents = 1, ++ .name = "hfpll_l2", ++ .ops = &clk_ops_hfpll, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock), ++}; ++ ++ + static struct clk_pll pll14 = { + .l_reg = 0x31c4, + .m_reg = 0x31c8, +@@ -2261,6 +2341,9 @@ static struct clk_regmap *gcc_ipq806x_cl + [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, + [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, + [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, ++ [PLL9] = &hfpll0.clkr, ++ [PLL10] = &hfpll1.clkr, ++ [PLL12] = &hfpll_l2.clkr, + }; + + static const struct qcom_reset_map gcc_ipq806x_resets[] = { diff --git a/target/linux/ipq806x/patches-3.18/140-clk-qcom-Add-support-for-Krait-clocks.patch b/target/linux/ipq806x/patches-3.18/140-clk-qcom-Add-support-for-Krait-clocks.patch new file mode 100644 index 0000000..63292e8 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/140-clk-qcom-Add-support-for-Krait-clocks.patch @@ -0,0 +1,271 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,09/13] clk: qcom: Add support for Krait clocks +From: Stephen Boyd +X-Patchwork-Id: 6063251 +Message-Id: <1426920332-9340-10-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:28 -0700 + +The Krait clocks are made up of a series of muxes and a divider +that choose between a fixed rate clock and dedicated HFPLLs for +each CPU. Instead of using mmio accesses to remux parents, the +Krait implementation exposes the remux control via cp15 +registers. Support these clocks. + +Signed-off-by: Stephen Boyd + +--- +drivers/clk/qcom/Kconfig | 4 ++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/clk-krait.c | 166 +++++++++++++++++++++++++++++++++++++++++++ + drivers/clk/qcom/clk-krait.h | 49 +++++++++++++ + 4 files changed, 220 insertions(+) + create mode 100644 drivers/clk/qcom/clk-krait.c + create mode 100644 drivers/clk/qcom/clk-krait.h + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -78,3 +78,7 @@ config QCOM_HFPLL + Support for the high-frequency PLLs present on Qualcomm devices. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8974, APQ8084, etc. ++ ++config KRAIT_CLOCKS ++ bool ++ select KRAIT_L2_ACCESSORS +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -6,6 +6,7 @@ clk-qcom-y += clk-pll.o + clk-qcom-y += clk-rcg.o + clk-qcom-y += clk-rcg2.o + clk-qcom-y += clk-branch.o ++clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o + clk-qcom-y += clk-hfpll.o + clk-qcom-y += reset.o + +--- /dev/null ++++ b/drivers/clk/qcom/clk-krait.c +@@ -0,0 +1,166 @@ ++/* ++ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-krait.h" ++ ++/* Secondary and primary muxes share the same cp15 register */ ++static DEFINE_SPINLOCK(krait_clock_reg_lock); ++ ++#define LPL_SHIFT 8 ++static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) ++{ ++ unsigned long flags; ++ u32 regval; ++ ++ spin_lock_irqsave(&krait_clock_reg_lock, flags); ++ regval = krait_get_l2_indirect_reg(mux->offset); ++ regval &= ~(mux->mask << mux->shift); ++ regval |= (sel & mux->mask) << mux->shift; ++ if (mux->lpl) { ++ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); ++ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); ++ } ++ krait_set_l2_indirect_reg(mux->offset, regval); ++ spin_unlock_irqrestore(&krait_clock_reg_lock, flags); ++ ++ /* Wait for switch to complete. */ ++ mb(); ++ udelay(1); ++} ++ ++static int krait_mux_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ u32 sel; ++ ++ sel = clk_mux_reindex(index, mux->parent_map, 0); ++ mux->en_mask = sel; ++ /* Don't touch mux if CPU is off as it won't work */ ++ if (__clk_is_enabled(hw->clk)) ++ __krait_mux_set_sel(mux, sel); ++ return 0; ++} ++ ++static u8 krait_mux_get_parent(struct clk_hw *hw) ++{ ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ u32 sel; ++ ++ sel = krait_get_l2_indirect_reg(mux->offset); ++ sel >>= mux->shift; ++ sel &= mux->mask; ++ mux->en_mask = sel; ++ ++ return clk_mux_get_parent(hw, sel, mux->parent_map, 0); ++} ++ ++static struct clk_hw *krait_mux_get_safe_parent(struct clk_hw *hw) ++{ ++ int i; ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ int num_parents = __clk_get_num_parents(hw->clk); ++ ++ i = mux->safe_sel; ++ for (i = 0; i < num_parents; i++) ++ if (mux->safe_sel == mux->parent_map[i]) ++ break; ++ ++ return __clk_get_hw(clk_get_parent_by_index(hw->clk, i)); ++} ++ ++static int krait_mux_enable(struct clk_hw *hw) ++{ ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ ++ __krait_mux_set_sel(mux, mux->en_mask); ++ ++ return 0; ++} ++ ++static void krait_mux_disable(struct clk_hw *hw) ++{ ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ ++ __krait_mux_set_sel(mux, mux->safe_sel); ++} ++ ++const struct clk_ops krait_mux_clk_ops = { ++ .enable = krait_mux_enable, ++ .disable = krait_mux_disable, ++ .set_parent = krait_mux_set_parent, ++ .get_parent = krait_mux_get_parent, ++ .determine_rate = __clk_mux_determine_rate_closest, ++ .get_safe_parent = krait_mux_get_safe_parent, ++}; ++EXPORT_SYMBOL_GPL(krait_mux_clk_ops); ++ ++/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */ ++static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ *parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), rate * 2); ++ return DIV_ROUND_UP(*parent_rate, 2); ++} ++ ++static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct krait_div2_clk *d = to_krait_div2_clk(hw); ++ unsigned long flags; ++ u32 val; ++ u32 mask = BIT(d->width) - 1; ++ ++ if (d->lpl) ++ mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; ++ ++ spin_lock_irqsave(&krait_clock_reg_lock, flags); ++ val = krait_get_l2_indirect_reg(d->offset); ++ val &= ~mask; ++ krait_set_l2_indirect_reg(d->offset, val); ++ spin_unlock_irqrestore(&krait_clock_reg_lock, flags); ++ ++ return 0; ++} ++ ++static unsigned long ++krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ struct krait_div2_clk *d = to_krait_div2_clk(hw); ++ u32 mask = BIT(d->width) - 1; ++ u32 div; ++ ++ div = krait_get_l2_indirect_reg(d->offset); ++ div >>= d->shift; ++ div &= mask; ++ div = (div + 1) * 2; ++ ++ return DIV_ROUND_UP(parent_rate, div); ++} ++ ++const struct clk_ops krait_div2_clk_ops = { ++ .round_rate = krait_div2_round_rate, ++ .set_rate = krait_div2_set_rate, ++ .recalc_rate = krait_div2_recalc_rate, ++}; ++EXPORT_SYMBOL_GPL(krait_div2_clk_ops); +--- /dev/null ++++ b/drivers/clk/qcom/clk-krait.h +@@ -0,0 +1,49 @@ ++/* ++ * Copyright (c) 2013, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __QCOM_CLK_KRAIT_H ++#define __QCOM_CLK_KRAIT_H ++ ++#include ++ ++struct krait_mux_clk { ++ unsigned int *parent_map; ++ bool has_safe_parent; ++ u8 safe_sel; ++ u32 offset; ++ u32 mask; ++ u32 shift; ++ u32 en_mask; ++ bool lpl; ++ ++ struct clk_hw hw; ++}; ++ ++#define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw) ++ ++extern const struct clk_ops krait_mux_clk_ops; ++ ++struct krait_div2_clk { ++ u32 offset; ++ u8 width; ++ u32 shift; ++ bool lpl; ++ ++ struct clk_hw hw; ++}; ++ ++#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw) ++ ++extern const struct clk_ops krait_div2_clk_ops; ++ ++#endif diff --git a/target/linux/ipq806x/patches-3.18/141-clk-qcom-Add-KPSS-ACC-GCC-driver.patch b/target/linux/ipq806x/patches-3.18/141-clk-qcom-Add-KPSS-ACC-GCC-driver.patch new file mode 100644 index 0000000..06b14d8 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/141-clk-qcom-Add-KPSS-ACC-GCC-driver.patch @@ -0,0 +1,205 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,10/13] clk: qcom: Add KPSS ACC/GCC driver +From: Stephen Boyd +X-Patchwork-Id: 6063201 +Message-Id: <1426920332-9340-11-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , +Date: Fri, 20 Mar 2015 23:45:29 -0700 + +The ACC and GCC regions present in KPSSv1 contain registers to +control clocks and power to each Krait CPU and L2. For CPUfreq +purposes probe these devices and expose a mux clock that chooses +between PXO and PLL8. + +Cc: +Signed-off-by: Stephen Boyd + +--- +.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 ++ + .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 28 +++++++ + drivers/clk/qcom/Kconfig | 8 ++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/kpss-xcc.c | 95 ++++++++++++++++++++++ + 5 files changed, 139 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt + create mode 100644 drivers/clk/qcom/kpss-xcc.c + +--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt ++++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +@@ -21,10 +21,17 @@ PROPERTIES + the register region. An optional second element specifies + the base address and size of the alias register region. + ++- clock-output-names: ++ Usage: optional ++ Value type: ++ Definition: Name of the output clock. Typically acpuX_aux where X is a ++ CPU number starting at 0. ++ + Example: + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x02088000 0x1000>, + <0x02008000 0x1000>; ++ clock-output-names = "acpu0_aux"; + }; +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +@@ -0,0 +1,28 @@ ++Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) ++ ++PROPERTIES ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: should be one of: ++ "qcom,kpss-gcc" ++ ++- reg: ++ Usage: required ++ Value type: ++ Definition: base address and size of the register region ++ ++- clock-output-names: ++ Usage: required ++ Value type: ++ Definition: Name of the output clock. Typically acpu_l2_aux indicating ++ an L2 cache auxiliary clock. ++ ++Example: ++ ++ l2cc: clock-controller@2011000 { ++ compatible = "qcom,kpss-gcc"; ++ reg = <0x2011000 0x1000>; ++ clock-output-names = "acpu_l2_aux"; ++ }; +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -79,6 +79,14 @@ config QCOM_HFPLL + Say Y if you want to support CPU frequency scaling on devices + such as MSM8974, APQ8084, etc. + ++config KPSS_XCC ++ tristate "KPSS Clock Controller" ++ depends on COMMON_CLK_QCOM ++ help ++ Support for the Krait ACC and GCC clock controllers. Say Y ++ if you want to support CPU frequency scaling on devices such ++ as MSM8960, APQ8064, etc. ++ + config KRAIT_CLOCKS + bool + select KRAIT_L2_ACCESSORS +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -18,4 +18,5 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm896 + obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o + obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o + obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o ++obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o + obj-$(CONFIG_QCOM_HFPLL) += hfpll.o +--- /dev/null ++++ b/drivers/clk/qcom/kpss-xcc.c +@@ -0,0 +1,95 @@ ++/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const char *aux_parents[] = { ++ "pll8_vote", ++ "pxo", ++}; ++ ++static unsigned int aux_parent_map[] = { ++ 3, ++ 0, ++}; ++ ++static const struct of_device_id kpss_xcc_match_table[] = { ++ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL }, ++ { .compatible = "qcom,kpss-gcc" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); ++ ++static int kpss_xcc_driver_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *id; ++ struct clk *clk; ++ struct resource *res; ++ void __iomem *base; ++ const char *name; ++ ++ id = of_match_device(kpss_xcc_match_table, &pdev->dev); ++ if (!id) ++ return -ENODEV; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ if (id->data) { ++ if (of_property_read_string_index(pdev->dev.of_node, ++ "clock-output-names", 0, &name)) ++ return -ENODEV; ++ base += 0x14; ++ } else { ++ name = "acpu_l2_aux"; ++ base += 0x28; ++ } ++ ++ clk = clk_register_mux_table(&pdev->dev, name, aux_parents, ++ ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, ++ 0, aux_parent_map, NULL); ++ ++ platform_set_drvdata(pdev, clk); ++ ++ return PTR_ERR_OR_ZERO(clk); ++} ++ ++static int kpss_xcc_driver_remove(struct platform_device *pdev) ++{ ++ clk_unregister_mux(platform_get_drvdata(pdev)); ++ return 0; ++} ++ ++static struct platform_driver kpss_xcc_driver = { ++ .probe = kpss_xcc_driver_probe, ++ .remove = kpss_xcc_driver_remove, ++ .driver = { ++ .name = "kpss-xcc", ++ .of_match_table = kpss_xcc_match_table, ++ }, ++}; ++module_platform_driver(kpss_xcc_driver); ++ ++MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:kpss-xcc"); diff --git a/target/linux/ipq806x/patches-3.18/142-clk-qcom-Add-Krait-clock-controller-driver.patch b/target/linux/ipq806x/patches-3.18/142-clk-qcom-Add-Krait-clock-controller-driver.patch new file mode 100644 index 0000000..98a09ac --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/142-clk-qcom-Add-Krait-clock-controller-driver.patch @@ -0,0 +1,435 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,11/13] clk: qcom: Add Krait clock controller driver +From: Stephen Boyd +X-Patchwork-Id: 6063121 +Message-Id: <1426920332-9340-12-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , +Date: Fri, 20 Mar 2015 23:45:30 -0700 + +The Krait CPU clocks are made up of a primary mux and secondary +mux for each CPU and the L2, controlled via cp15 accessors. For +Kraits within KPSSv1 each secondary mux accepts a different aux +source, but on KPSSv2 each secondary mux accepts the same aux +source. + +Cc: +Signed-off-by: Stephen Boyd + +--- +.../devicetree/bindings/clock/qcom,krait-cc.txt | 22 ++ + drivers/clk/qcom/Kconfig | 8 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/krait-cc.c | 352 +++++++++++++++++++++ + 4 files changed, 383 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt + create mode 100644 drivers/clk/qcom/krait-cc.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +@@ -0,0 +1,22 @@ ++Krait Clock Controller ++ ++PROPERTIES ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: must be one of: ++ "qcom,krait-cc-v1" ++ "qcom,krait-cc-v2" ++ ++- #clock-cells: ++ Usage: required ++ Value type: ++ Definition: must be 1 ++ ++Example: ++ ++ kraitcc: clock-controller { ++ compatible = "qcom,krait-cc-v1"; ++ #clock-cells = <1>; ++ }; +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -87,6 +87,14 @@ config KPSS_XCC + if you want to support CPU frequency scaling on devices such + as MSM8960, APQ8064, etc. + ++config KRAITCC ++ tristate "Krait Clock Controller" ++ depends on COMMON_CLK_QCOM && ARM ++ select KRAIT_CLOCKS ++ help ++ Support for the Krait CPU clocks on Qualcomm devices. ++ Say Y if you want to support CPU frequency scaling. ++ + config KRAIT_CLOCKS + bool + select KRAIT_L2_ACCESSORS +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -20,3 +20,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8 + obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o + obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o + obj-$(CONFIG_QCOM_HFPLL) += hfpll.o ++obj-$(CONFIG_KRAITCC) += krait-cc.o +--- /dev/null ++++ b/drivers/clk/qcom/krait-cc.c +@@ -0,0 +1,352 @@ ++/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-krait.h" ++ ++static unsigned int sec_mux_map[] = { ++ 2, ++ 0, ++}; ++ ++static unsigned int pri_mux_map[] = { ++ 1, ++ 2, ++ 0, ++}; ++ ++static int ++krait_add_div(struct device *dev, int id, const char *s, unsigned offset) ++{ ++ struct krait_div2_clk *div; ++ struct clk_init_data init = { ++ .num_parents = 1, ++ .ops = &krait_div2_clk_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }; ++ const char *p_names[1]; ++ struct clk *clk; ++ ++ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); ++ if (!div) ++ return -ENOMEM; ++ ++ div->width = 2; ++ div->shift = 6; ++ div->lpl = id >= 0; ++ div->offset = offset; ++ div->hw.init = &init; ++ ++ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); ++ if (!init.name) ++ return -ENOMEM; ++ ++ init.parent_names = p_names; ++ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); ++ if (!p_names[0]) { ++ kfree(init.name); ++ return -ENOMEM; ++ } ++ ++ clk = devm_clk_register(dev, &div->hw); ++ kfree(p_names[0]); ++ kfree(init.name); ++ ++ return PTR_ERR_OR_ZERO(clk); ++} ++ ++static int ++krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset, ++ bool unique_aux) ++{ ++ struct krait_mux_clk *mux; ++ static const char *sec_mux_list[] = { ++ "acpu_aux", ++ "qsb", ++ }; ++ struct clk_init_data init = { ++ .parent_names = sec_mux_list, ++ .num_parents = ARRAY_SIZE(sec_mux_list), ++ .ops = &krait_mux_clk_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }; ++ struct clk *clk; ++ ++ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); ++ if (!mux) ++ return -ENOMEM; ++ ++ mux->offset = offset; ++ mux->lpl = id >= 0; ++ mux->has_safe_parent = true; ++ mux->safe_sel = 2; ++ mux->mask = 0x3; ++ mux->shift = 2; ++ mux->parent_map = sec_mux_map; ++ mux->hw.init = &init; ++ ++ init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); ++ if (!init.name) ++ return -ENOMEM; ++ ++ if (unique_aux) { ++ sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); ++ if (!sec_mux_list[0]) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_aux; ++ } ++ } ++ ++ clk = devm_clk_register(dev, &mux->hw); ++ ++ if (unique_aux) ++ kfree(sec_mux_list[0]); ++err_aux: ++ kfree(init.name); ++ return PTR_ERR_OR_ZERO(clk); ++} ++ ++static struct clk * ++krait_add_pri_mux(struct device *dev, int id, const char *s, unsigned offset) ++{ ++ struct krait_mux_clk *mux; ++ const char *p_names[3]; ++ struct clk_init_data init = { ++ .parent_names = p_names, ++ .num_parents = ARRAY_SIZE(p_names), ++ .ops = &krait_mux_clk_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }; ++ struct clk *clk; ++ ++ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); ++ if (!mux) ++ return ERR_PTR(-ENOMEM); ++ ++ mux->has_safe_parent = true; ++ mux->safe_sel = 0; ++ mux->mask = 0x3; ++ mux->shift = 0; ++ mux->offset = offset; ++ mux->lpl = id >= 0; ++ mux->parent_map = pri_mux_map; ++ mux->hw.init = &init; ++ ++ init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); ++ if (!init.name) ++ return ERR_PTR(-ENOMEM); ++ ++ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); ++ if (!p_names[0]) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_p0; ++ } ++ ++ p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); ++ if (!p_names[1]) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_p1; ++ } ++ ++ p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); ++ if (!p_names[2]) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_p2; ++ } ++ ++ clk = devm_clk_register(dev, &mux->hw); ++ ++ kfree(p_names[2]); ++err_p2: ++ kfree(p_names[1]); ++err_p1: ++ kfree(p_names[0]); ++err_p0: ++ kfree(init.name); ++ return clk; ++} ++ ++/* id < 0 for L2, otherwise id == physical CPU number */ ++static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) ++{ ++ int ret; ++ unsigned offset; ++ void *p = NULL; ++ const char *s; ++ struct clk *clk; ++ ++ if (id >= 0) { ++ offset = 0x4501 + (0x1000 * id); ++ s = p = kasprintf(GFP_KERNEL, "%d", id); ++ if (!s) ++ return ERR_PTR(-ENOMEM); ++ } else { ++ offset = 0x500; ++ s = "_l2"; ++ } ++ ++ ret = krait_add_div(dev, id, s, offset); ++ if (ret) { ++ clk = ERR_PTR(ret); ++ goto err; ++ } ++ ++ ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); ++ if (ret) { ++ clk = ERR_PTR(ret); ++ goto err; ++ } ++ ++ clk = krait_add_pri_mux(dev, id, s, offset); ++err: ++ kfree(p); ++ return clk; ++} ++ ++static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) ++{ ++ unsigned int idx = clkspec->args[0]; ++ struct clk **clks = data; ++ ++ if (idx >= 5) { ++ pr_err("%s: invalid clock index %d\n", __func__, idx); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return clks[idx] ? : ERR_PTR(-ENODEV); ++} ++ ++static const struct of_device_id krait_cc_match_table[] = { ++ { .compatible = "qcom,krait-cc-v1", (void *)1UL }, ++ { .compatible = "qcom,krait-cc-v2" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, krait_cc_match_table); ++ ++static int krait_cc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ const struct of_device_id *id; ++ unsigned long cur_rate, aux_rate; ++ int cpu; ++ struct clk *clk; ++ struct clk **clks; ++ struct clk *l2_pri_mux_clk; ++ ++ id = of_match_device(krait_cc_match_table, dev); ++ if (!id) ++ return -ENODEV; ++ ++ /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ ++ clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ if (!id->data) { ++ clk = clk_register_fixed_factor(dev, "acpu_aux", ++ "gpll0_vote", 0, 1, 2); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ } ++ ++ /* Krait configurations have at most 4 CPUs and one L2 */ ++ clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL); ++ if (!clks) ++ return -ENOMEM; ++ ++ for_each_possible_cpu(cpu) { ++ clk = krait_add_clks(dev, cpu, id->data); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ clks[cpu] = clk; ++ } ++ ++ l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); ++ if (IS_ERR(l2_pri_mux_clk)) ++ return PTR_ERR(l2_pri_mux_clk); ++ clks[4] = l2_pri_mux_clk; ++ ++ /* ++ * We don't want the CPU or L2 clocks to be turned off at late init ++ * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the ++ * refcount of these clocks. Any cpufreq/hotplug manager can assume ++ * that the clocks have already been prepared and enabled by the time ++ * they take over. ++ */ ++ for_each_online_cpu(cpu) { ++ clk_prepare_enable(l2_pri_mux_clk); ++ WARN(clk_prepare_enable(clks[cpu]), ++ "Unable to turn on CPU%d clock", cpu); ++ } ++ ++ /* ++ * Force reinit of HFPLLs and muxes to overwrite any potential ++ * incorrect configuration of HFPLLs and muxes by the bootloader. ++ * While at it, also make sure the cores are running at known rates ++ * and print the current rate. ++ * ++ * The clocks are set to aux clock rate first to make sure the ++ * secondary mux is not sourcing off of QSB. The rate is then set to ++ * two different rates to force a HFPLL reinit under all ++ * circumstances. ++ */ ++ cur_rate = clk_get_rate(l2_pri_mux_clk); ++ aux_rate = 384000000; ++ if (cur_rate == 1) { ++ pr_info("L2 @ QSB rate. Forcing new rate.\n"); ++ cur_rate = aux_rate; ++ } ++ clk_set_rate(l2_pri_mux_clk, aux_rate); ++ clk_set_rate(l2_pri_mux_clk, 2); ++ clk_set_rate(l2_pri_mux_clk, cur_rate); ++ pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); ++ for_each_possible_cpu(cpu) { ++ clk = clks[cpu]; ++ cur_rate = clk_get_rate(clk); ++ if (cur_rate == 1) { ++ pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); ++ cur_rate = aux_rate; ++ } ++ clk_set_rate(clk, aux_rate); ++ clk_set_rate(clk, 2); ++ clk_set_rate(clk, cur_rate); ++ pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); ++ } ++ ++ of_clk_add_provider(dev->of_node, krait_of_get, clks); ++ ++ return 0; ++} ++ ++static struct platform_driver krait_cc_driver = { ++ .probe = krait_cc_probe, ++ .driver = { ++ .name = "krait-cc", ++ .of_match_table = krait_cc_match_table, ++ }, ++}; ++module_platform_driver(krait_cc_driver); ++ ++MODULE_DESCRIPTION("Krait CPU Clock Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:krait-cc"); diff --git a/target/linux/ipq806x/patches-3.18/143-cpufreq-Add-module-to-register-cpufreq-on-Krait-CPUs.patch b/target/linux/ipq806x/patches-3.18/143-cpufreq-Add-module-to-register-cpufreq-on-Krait-CPUs.patch new file mode 100644 index 0000000..c3ca9b5 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/143-cpufreq-Add-module-to-register-cpufreq-on-Krait-CPUs.patch @@ -0,0 +1,304 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,12/13] cpufreq: Add module to register cpufreq on Krait CPUs +From: Stephen Boyd +X-Patchwork-Id: 6063191 +Message-Id: <1426920332-9340-13-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , +Date: Fri, 20 Mar 2015 23:45:31 -0700 + +Register a cpufreq-generic device whenever we detect that a +"qcom,krait" compatible CPU is present in DT. + +Cc: +Signed-off-by: Stephen Boyd + +--- +.../devicetree/bindings/arm/msm/qcom,pvs.txt | 38 ++++ + drivers/cpufreq/Kconfig.arm | 9 + + drivers/cpufreq/Makefile | 1 + + drivers/cpufreq/qcom-cpufreq.c | 204 +++++++++++++++++++++ + 4 files changed, 252 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt + create mode 100644 drivers/cpufreq/qcom-cpufreq.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt +@@ -0,0 +1,38 @@ ++Qualcomm Process Voltage Scaling Tables ++ ++The node name is required to be "qcom,pvs". There shall only be one ++such node present in the root of the tree. ++ ++PROPERTIES ++ ++- qcom,pvs-format-a or qcom,pvs-format-b: ++ Usage: required ++ Value type: ++ Definition: Indicates the format of qcom,speedX-pvsY-bin-vZ properties. ++ If qcom,pvs-format-a is used the table is two columns ++ (frequency and voltage in that order). If qcom,pvs-format-b is used the table is three columns (frequency, voltage, ++ and current in that order). ++ ++- qcom,speedX-pvsY-bin-vZ: ++ Usage: required ++ Value type: ++ Definition: The PVS table corresponding to the speed bin X, pvs bin Y, ++ and version Z. ++Example: ++ ++ qcom,pvs { ++ qcom,pvs-format-a; ++ qcom,speed0-pvs0-bin-v0 = ++ < 384000000 950000 >, ++ < 486000000 975000 >, ++ < 594000000 1000000 >, ++ < 702000000 1025000 >, ++ < 810000000 1075000 >, ++ < 918000000 1100000 >, ++ < 1026000000 1125000 >, ++ < 1134000000 1175000 >, ++ < 1242000000 1200000 >, ++ < 1350000000 1225000 >, ++ < 1458000000 1237500 >, ++ < 1512000000 1250000 >; ++ }; +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -129,6 +129,15 @@ config ARM_OMAP2PLUS_CPUFREQ + depends on ARCH_OMAP2PLUS + default ARCH_OMAP2PLUS + ++config ARM_QCOM_CPUFREQ ++ tristate "Qualcomm based" ++ depends on ARCH_QCOM ++ select PM_OPP ++ help ++ This adds the CPUFreq driver for Qualcomm SoC based boards. ++ ++ If in doubt, say N. ++ + config ARM_S3C_CPUFREQ + bool + help +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -64,6 +64,7 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += o + obj-$(CONFIG_PXA25x) += pxa2xx-cpufreq.o + obj-$(CONFIG_PXA27x) += pxa2xx-cpufreq.o + obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o ++obj-$(CONFIG_ARM_QCOM_CPUFREQ) += qcom-cpufreq.o + obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o + obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o + obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o +--- /dev/null ++++ b/drivers/cpufreq/qcom-cpufreq.c +@@ -0,0 +1,204 @@ ++/* Copyright (c) 2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver) ++{ ++ void __iomem *base; ++ u32 pte_efuse; ++ ++ *speed = *pvs = *pvs_ver = 0; ++ ++ base = ioremap(0x007000c0, 4); ++ if (!base) { ++ pr_warn("Unable to read efuse data. Defaulting to 0!\n"); ++ return; ++ } ++ ++ pte_efuse = readl_relaxed(base); ++ iounmap(base); ++ ++ *speed = pte_efuse & 0xf; ++ if (*speed == 0xf) ++ *speed = (pte_efuse >> 4) & 0xf; ++ ++ if (*speed == 0xf) { ++ *speed = 0; ++ pr_warn("Speed bin: Defaulting to %d\n", *speed); ++ } else { ++ pr_info("Speed bin: %d\n", *speed); ++ } ++ ++ *pvs = (pte_efuse >> 10) & 0x7; ++ if (*pvs == 0x7) ++ *pvs = (pte_efuse >> 13) & 0x7; ++ ++ if (*pvs == 0x7) { ++ *pvs = 0; ++ pr_warn("PVS bin: Defaulting to %d\n", *pvs); ++ } else { ++ pr_info("PVS bin: %d\n", *pvs); ++ } ++} ++ ++static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver) ++{ ++ u32 pte_efuse, redundant_sel; ++ void __iomem *base; ++ ++ *speed = 0; ++ *pvs = 0; ++ *pvs_ver = 0; ++ ++ base = ioremap(0xfc4b80b0, 8); ++ if (!base) { ++ pr_warn("Unable to read efuse data. Defaulting to 0!\n"); ++ return; ++ } ++ ++ pte_efuse = readl_relaxed(base); ++ redundant_sel = (pte_efuse >> 24) & 0x7; ++ *speed = pte_efuse & 0x7; ++ /* 4 bits of PVS are in efuse register bits 31, 8-6. */ ++ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); ++ *pvs_ver = (pte_efuse >> 4) & 0x3; ++ ++ switch (redundant_sel) { ++ case 1: ++ *speed = (pte_efuse >> 27) & 0xf; ++ break; ++ case 2: ++ *pvs = (pte_efuse >> 27) & 0xf; ++ break; ++ } ++ ++ /* Check SPEED_BIN_BLOW_STATUS */ ++ if (pte_efuse & BIT(3)) { ++ pr_info("Speed bin: %d\n", *speed); ++ } else { ++ pr_warn("Speed bin not set. Defaulting to 0!\n"); ++ *speed = 0; ++ } ++ ++ /* Check PVS_BLOW_STATUS */ ++ pte_efuse = readl_relaxed(base + 0x4) & BIT(21); ++ if (pte_efuse) { ++ pr_info("PVS bin: %d\n", *pvs); ++ } else { ++ pr_warn("PVS bin not set. Defaulting to 0!\n"); ++ *pvs = 0; ++ } ++ ++ pr_info("PVS version: %d\n", *pvs_ver); ++ iounmap(base); ++} ++ ++static int __init qcom_cpufreq_populate_opps(void) ++{ ++ int len, rows, cols, i, k, speed, pvs, pvs_ver; ++ char table_name[] = "qcom,speedXX-pvsXX-bin-vXX"; ++ struct device_node *np; ++ struct device *dev; ++ int cpu = 0; ++ ++ np = of_find_node_by_name(NULL, "qcom,pvs"); ++ if (!np) ++ return -ENODEV; ++ ++ if (of_property_read_bool(np, "qcom,pvs-format-a")) { ++ get_krait_bin_format_a(&speed, &pvs, &pvs_ver); ++ cols = 2; ++ } else if (of_property_read_bool(np, "qcom,pvs-format-b")) { ++ get_krait_bin_format_b(&speed, &pvs, &pvs_ver); ++ cols = 3; ++ } else { ++ return -ENODEV; ++ } ++ ++ snprintf(table_name, sizeof(table_name), ++ "qcom,speed%d-pvs%d-bin-v%d", speed, pvs, pvs_ver); ++ ++ if (!of_find_property(np, table_name, &len)) ++ return -EINVAL; ++ ++ len /= sizeof(u32); ++ if (len % cols || len == 0) ++ return -EINVAL; ++ ++ rows = len / cols; ++ ++ for (i = 0, k = 0; i < rows; i++) { ++ u32 freq, volt; ++ ++ of_property_read_u32_index(np, table_name, k++, &freq); ++ of_property_read_u32_index(np, table_name, k++, &volt); ++ while (k % cols) ++ k++; /* Skip uA entries if present */ ++ for (cpu = 0; cpu < num_possible_cpus(); cpu++) { ++ dev = get_cpu_device(cpu); ++ if (!dev) ++ return -ENODEV; ++ if (dev_pm_opp_add(dev, freq, volt)) ++ pr_warn("failed to add OPP %u\n", freq); ++ } ++ } ++ ++ return 0; ++} ++ ++static int __init qcom_cpufreq_driver_init(void) ++{ ++ struct cpufreq_dt_platform_data pdata = { .independent_clocks = true }; ++ struct platform_device_info devinfo = { ++ .name = "cpufreq-dt", ++ .data = &pdata, ++ .size_data = sizeof(pdata), ++ }; ++ struct device *cpu_dev; ++ struct device_node *np; ++ int ret; ++ ++ cpu_dev = get_cpu_device(0); ++ if (!cpu_dev) ++ return -ENODEV; ++ ++ np = of_node_get(cpu_dev->of_node); ++ if (!np) ++ return -ENOENT; ++ ++ if (!of_device_is_compatible(np, "qcom,krait")) { ++ of_node_put(np); ++ return -ENODEV; ++ } ++ of_node_put(np); ++ ++ ret = qcom_cpufreq_populate_opps(); ++ if (ret) ++ return ret; ++ ++ return PTR_ERR_OR_ZERO(platform_device_register_full(&devinfo)); ++} ++module_init(qcom_cpufreq_driver_init); ++ ++MODULE_DESCRIPTION("Qualcomm CPUfreq driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-3.18/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch b/target/linux/ipq806x/patches-3.18/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch new file mode 100644 index 0000000..a3c3bbf --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch @@ -0,0 +1,100 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -24,6 +24,11 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; ++ clocks = <&kraitcc 0>; ++ clock-names = "cpu"; ++ clock-latency = <100000>; ++ core-supply = <&smb208_s2a>; ++ voltage-tolerance = <5>; + }; + + cpu@1 { +@@ -34,11 +39,24 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; ++ clocks = <&kraitcc 1>; ++ clock-names = "cpu"; ++ clock-latency = <100000>; ++ core-supply = <&smb208_s2b>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; ++ clocks = <&kraitcc 4>; ++ clock-names = "cache"; ++ cache-points-kHz = < ++ /* kHz uV CPU kHz */ ++ 1200000 1150000 1200000 ++ 1000000 1100000 600000 ++ 384000 1100000 384000 ++ >; ++ vdd_dig-supply = <&smb208_s1a>; + }; + }; + +@@ -71,6 +89,46 @@ + }; + }; + ++ kraitcc: clock-controller { ++ compatible = "qcom,krait-cc-v1"; ++ #clock-cells = <1>; ++ }; ++ ++ qcom,pvs { ++ qcom,pvs-format-a; ++ qcom,speed0-pvs0-bin-v0 = ++ < 1400000000 1250000 >, ++ < 1200000000 1200000 >, ++ < 1000000000 1150000 >, ++ < 800000000 1100000 >, ++ < 600000000 1050000 >, ++ < 384000000 1000000 >; ++ ++ qcom,speed0-pvs1-bin-v0 = ++ < 1400000000 1175000 >, ++ < 1200000000 1125000 >, ++ < 1000000000 1075000 >, ++ < 800000000 1025000 >, ++ < 600000000 975000 >, ++ < 384000000 925000 >; ++ ++ qcom,speed0-pvs2-bin-v0 = ++ < 1400000000 1125000 >, ++ < 1200000000 1075000 >, ++ < 1000000000 1025000 >, ++ < 800000000 995000 >, ++ < 600000000 925000 >, ++ < 384000000 875000 >; ++ ++ qcom,speed0-pvs3-bin-v0 = ++ < 1400000000 1050000 >, ++ < 1200000000 1000000 >, ++ < 1000000000 950000 >, ++ < 800000000 900000 >, ++ < 600000000 850000 >, ++ < 384000000 800000 >; ++ }; ++ + soc: soc { + #address-cells = <1>; + #size-cells = <1>; +@@ -171,11 +229,13 @@ + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; ++ clock-output-names = "acpu0_aux"; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; ++ clock-output-names = "acpu1_aux"; + }; + + l2cc: clock-controller@2011000 { diff --git a/target/linux/ipq806x/patches-3.18/145-cpufreq-Add-a-cpufreq-krait-based-on-cpufre.patch b/target/linux/ipq806x/patches-3.18/145-cpufreq-Add-a-cpufreq-krait-based-on-cpufre.patch new file mode 100644 index 0000000..6052b41 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/145-cpufreq-Add-a-cpufreq-krait-based-on-cpufre.patch @@ -0,0 +1,461 @@ +From dd77db4143290689d3a5e1ec61627233d0711b66 Mon Sep 17 00:00:00 2001 +From: Stephen Boyd +Date: Fri, 30 May 2014 16:36:11 -0700 +Subject: [PATCH] FROMLIST: cpufreq: Add a cpufreq-krait based on cpufreq-cpu0 + +Krait processors have individual clocks for each CPU that can +scale independently from one another. cpufreq-cpu0 is fairly +close to this, but assumes that there is only one clock for all +CPUs. Add a driver to support the Krait configuration. + +TODO: Merge into cpufreq-cpu0? Or make generic? + +Signed-off-by: Stephen Boyd + +--- + drivers/cpufreq/Kconfig | 13 +++ + drivers/cpufreq/Makefile | 1 + + drivers/cpufreq/cpufreq-krait.c | 190 ++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 204 insertions(+) + create mode 100644 drivers/cpufreq/cpufreq-krait.c + +--- a/drivers/cpufreq/Kconfig ++++ b/drivers/cpufreq/Kconfig +@@ -196,6 +196,19 @@ config CPUFREQ_DT + + If in doubt, say N. + ++config GENERIC_CPUFREQ_KRAIT ++ tristate "Krait cpufreq driver" ++ depends on HAVE_CLK && OF ++ # if CPU_THERMAL is on and THERMAL=m, CPU0 cannot be =y: ++ depends on !CPU_THERMAL || THERMAL ++ select PM_OPP ++ help ++ This adds a generic cpufreq driver for CPU0 frequency management. ++ It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) ++ systems which share clock and voltage across all CPUs. ++ ++ If in doubt, say N. ++ + menu "x86 CPU frequency scaling drivers" + depends on X86 + source "drivers/cpufreq/Kconfig.x86" +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE) + obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o + + obj-$(CONFIG_CPUFREQ_DT) += cpufreq-dt.o ++obj-$(CONFIG_GENERIC_CPUFREQ_KRAIT) += cpufreq-krait.o + + ################################################################################## + # x86 drivers. +--- /dev/null ++++ b/drivers/cpufreq/cpufreq-krait.c +@@ -0,0 +1,390 @@ ++/* ++ * Copyright (C) 2012 Freescale Semiconductor, Inc. ++ * Copyright (c) 2014, The Linux Foundation. All rights reserved. ++ * ++ * The OPP code in function krait_set_target() is reused from ++ * drivers/cpufreq/omap-cpufreq.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static unsigned int transition_latency; ++static unsigned int voltage_tolerance; /* in percentage */ ++ ++static struct device *cpu_dev; ++static DEFINE_PER_CPU(struct clk *, krait_cpu_clks); ++static DEFINE_PER_CPU(struct regulator *, krait_supply_core); ++static struct cpufreq_frequency_table *freq_table; ++static struct thermal_cooling_device *cdev; ++ ++struct cache_points { ++ unsigned long cache_freq; ++ unsigned int cache_volt; ++ unsigned long cpu_freq; ++}; ++ ++static struct regulator *krait_l2_reg; ++static struct clk *krait_l2_clk; ++static struct cache_points *krait_l2_points; ++static int nr_krait_l2_points; ++ ++static int krait_parse_cache_points(struct device *dev, ++ struct device_node *of_node) ++{ ++ const struct property *prop; ++ const __be32 *val; ++ int nr, i; ++ ++ prop = of_find_property(of_node, "cache-points-kHz", NULL); ++ if (!prop) ++ return -ENODEV; ++ if (!prop->value) ++ return -ENODATA; ++ ++ /* ++ * Each OPP is a set of tuples consisting of frequency and ++ * cpu-frequency like . ++ */ ++ nr = prop->length / sizeof(u32); ++ if (nr % 3) { ++ dev_err(dev, "%s: Invalid cache points\n", __func__); ++ return -EINVAL; ++ } ++ nr /= 3; ++ ++ krait_l2_points = devm_kcalloc(dev, nr, sizeof(*krait_l2_points), ++ GFP_KERNEL); ++ if (!krait_l2_points) ++ return -ENOMEM; ++ nr_krait_l2_points = nr; ++ ++ for (i = 0, val = prop->value; i < nr; i++) { ++ unsigned long cache_freq = be32_to_cpup(val++) * 1000; ++ unsigned int cache_volt = be32_to_cpup(val++); ++ unsigned long cpu_freq = be32_to_cpup(val++) * 1000; ++ ++ krait_l2_points[i].cache_freq = cache_freq; ++ krait_l2_points[i].cache_volt = cache_volt; ++ krait_l2_points[i].cpu_freq = cpu_freq; ++ } ++ ++ return 0; ++} ++ ++static int krait_set_target(struct cpufreq_policy *policy, unsigned int index) ++{ ++ struct dev_pm_opp *opp; ++ unsigned long volt = 0, volt_old = 0, tol = 0; ++ unsigned long freq, max_cpu_freq = 0; ++ unsigned int old_freq, new_freq; ++ long freq_Hz, freq_exact; ++ int ret, i; ++ struct clk *cpu_clk; ++ struct regulator *core; ++ unsigned int cpu; ++ ++ cpu_clk = per_cpu(krait_cpu_clks, policy->cpu); ++ ++ freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); ++ if (freq_Hz <= 0) ++ freq_Hz = freq_table[index].frequency * 1000; ++ ++ freq_exact = freq_Hz; ++ new_freq = freq_Hz / 1000; ++ old_freq = clk_get_rate(cpu_clk) / 1000; ++ ++ core = per_cpu(krait_supply_core, policy->cpu); ++ ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("failed to find OPP for %ld\n", freq_Hz); ++ return PTR_ERR(opp); ++ } ++ volt = dev_pm_opp_get_voltage(opp); ++ rcu_read_unlock(); ++ tol = volt * voltage_tolerance / 100; ++ volt_old = regulator_get_voltage(core); ++ ++ pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n", ++ old_freq / 1000, volt_old ? volt_old / 1000 : -1, ++ new_freq / 1000, volt ? volt / 1000 : -1); ++ ++ /* scaling up? scale voltage before frequency */ ++ if (new_freq > old_freq) { ++ ret = regulator_set_voltage_tol(core, volt, tol); ++ if (ret) { ++ pr_err("failed to scale voltage up: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ ret = clk_set_rate(cpu_clk, freq_exact); ++ if (ret) { ++ pr_err("failed to set clock rate: %d\n", ret); ++ return ret; ++ } ++ ++ /* scaling down? scale voltage after frequency */ ++ if (new_freq < old_freq) { ++ ret = regulator_set_voltage_tol(core, volt, tol); ++ if (ret) { ++ pr_err("failed to scale voltage down: %d\n", ret); ++ clk_set_rate(cpu_clk, old_freq * 1000); ++ } ++ } ++ ++ for_each_possible_cpu(cpu) { ++ freq = clk_get_rate(per_cpu(krait_cpu_clks, cpu)); ++ max_cpu_freq = max(max_cpu_freq, freq); ++ } ++ ++ for (i = 0; i < nr_krait_l2_points; i++) { ++ if (max_cpu_freq >= krait_l2_points[i].cpu_freq) { ++ if (krait_l2_reg) { ++ ret = regulator_set_voltage_tol(krait_l2_reg, ++ krait_l2_points[i].cache_volt, ++ tol); ++ if (ret) { ++ pr_err("failed to scale l2 voltage: %d\n", ++ ret); ++ } ++ } ++ ret = clk_set_rate(krait_l2_clk, ++ krait_l2_points[i].cache_freq); ++ if (ret) ++ pr_err("failed to scale l2 clk: %d\n", ret); ++ break; ++ } ++ ++ } ++ ++ return ret; ++} ++ ++static int krait_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ int ret; ++ ++ policy->clk = per_cpu(krait_cpu_clks, policy->cpu); ++ ++ ret = cpufreq_table_validate_and_show(policy, freq_table); ++ if (ret) { ++ pr_err("%s: invalid frequency table: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ policy->cpuinfo.transition_latency = transition_latency; ++ ++ return 0; ++} ++ ++static struct cpufreq_driver krait_cpufreq_driver = { ++ .flags = CPUFREQ_STICKY, ++ .verify = cpufreq_generic_frequency_table_verify, ++ .target_index = krait_set_target, ++ .get = cpufreq_generic_get, ++ .init = krait_cpufreq_init, ++ .name = "generic_krait", ++ .attr = cpufreq_generic_attr, ++}; ++ ++static int krait_cpufreq_probe(struct platform_device *pdev) ++{ ++ struct device_node *np, *cache; ++ int ret, i; ++ unsigned int cpu; ++ struct device *dev; ++ struct clk *clk; ++ struct regulator *core; ++ unsigned long freq_Hz, freq, max_cpu_freq = 0; ++ struct dev_pm_opp *opp; ++ unsigned long volt, tol; ++ ++ cpu_dev = get_cpu_device(0); ++ if (!cpu_dev) { ++ pr_err("failed to get krait device\n"); ++ return -ENODEV; ++ } ++ ++ np = of_node_get(cpu_dev->of_node); ++ if (!np) { ++ pr_err("failed to find krait node\n"); ++ return -ENOENT; ++ } ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); ++ if (ret) { ++ pr_err("failed to init cpufreq table: %d\n", ret); ++ goto out_put_node; ++ } ++ ++ of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance); ++ ++ if (of_property_read_u32(np, "clock-latency", &transition_latency)) ++ transition_latency = CPUFREQ_ETERNAL; ++ ++ cache = of_find_next_cache_node(np); ++ if (cache) { ++ struct device_node *vdd; ++ ++ vdd = of_parse_phandle(cache, "vdd_dig-supply", 0); ++ if (vdd) { ++ krait_l2_reg = regulator_get(NULL, vdd->name); ++ if (IS_ERR(krait_l2_reg)) { ++ pr_warn("failed to get l2 vdd_dig supply\n"); ++ krait_l2_reg = NULL; ++ } ++ of_node_put(vdd); ++ } ++ ++ krait_l2_clk = of_clk_get(cache, 0); ++ if (!IS_ERR(krait_l2_clk)) { ++ ret = krait_parse_cache_points(&pdev->dev, cache); ++ if (ret) ++ clk_put(krait_l2_clk); ++ } ++ if (IS_ERR(krait_l2_clk) || ret) ++ krait_l2_clk = NULL; ++ } ++ ++ for_each_possible_cpu(cpu) { ++ dev = get_cpu_device(cpu); ++ if (!dev) { ++ pr_err("failed to get krait device\n"); ++ ret = -ENOENT; ++ goto out_free_table; ++ } ++ per_cpu(krait_cpu_clks, cpu) = clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(clk)) { ++ ret = PTR_ERR(clk); ++ goto out_free_table; ++ } ++ core = devm_regulator_get(dev, "core"); ++ if (IS_ERR(core)) { ++ pr_debug("failed to get core regulator\n"); ++ ret = PTR_ERR(core); ++ goto out_free_table; ++ } ++ per_cpu(krait_supply_core, cpu) = core; ++ ++ freq = freq_Hz = clk_get_rate(clk); ++ ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("failed to find OPP for %ld\n", freq_Hz); ++ ret = PTR_ERR(opp); ++ goto out_free_table; ++ } ++ volt = dev_pm_opp_get_voltage(opp); ++ rcu_read_unlock(); ++ ++ tol = volt * voltage_tolerance / 100; ++ ret = regulator_set_voltage_tol(core, volt, tol); ++ if (ret) { ++ pr_err("failed to scale voltage up: %d\n", ret); ++ goto out_free_table; ++ } ++ ret = regulator_enable(core); ++ if (ret) { ++ pr_err("failed to enable regulator: %d\n", ret); ++ goto out_free_table; ++ } ++ max_cpu_freq = max(max_cpu_freq, freq); ++ } ++ ++ for (i = 0; i < nr_krait_l2_points; i++) { ++ if (max_cpu_freq >= krait_l2_points[i].cpu_freq) { ++ if (krait_l2_reg) { ++ ret = regulator_set_voltage_tol(krait_l2_reg, ++ krait_l2_points[i].cache_volt, ++ tol); ++ if (ret) ++ pr_err("failed to scale l2 voltage: %d\n", ++ ret); ++ ret = regulator_enable(krait_l2_reg); ++ if (ret) ++ pr_err("failed to enable l2 voltage: %d\n", ++ ret); ++ } ++ break; ++ } ++ ++ } ++ ++ ret = cpufreq_register_driver(&krait_cpufreq_driver); ++ if (ret) { ++ pr_err("failed register driver: %d\n", ret); ++ goto out_free_table; ++ } ++ of_node_put(np); ++ ++ /* ++ * For now, just loading the cooling device; ++ * thermal DT code takes care of matching them. ++ */ ++ for_each_possible_cpu(cpu) { ++ dev = get_cpu_device(cpu); ++ np = of_node_get(dev->of_node); ++ if (of_find_property(np, "#cooling-cells", NULL)) { ++ cdev = of_cpufreq_cooling_register(np, cpumask_of(cpu)); ++ if (IS_ERR(cdev)) ++ pr_err("running cpufreq without cooling device: %ld\n", ++ PTR_ERR(cdev)); ++ } ++ of_node_put(np); ++ } ++ ++ return 0; ++ ++out_free_table: ++ regulator_put(krait_l2_reg); ++ clk_put(krait_l2_clk); ++ dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); ++out_put_node: ++ of_node_put(np); ++ return ret; ++} ++ ++static int krait_cpufreq_remove(struct platform_device *pdev) ++{ ++ cpufreq_cooling_unregister(cdev); ++ cpufreq_unregister_driver(&krait_cpufreq_driver); ++ dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); ++ clk_put(krait_l2_clk); ++ regulator_put(krait_l2_reg); ++ ++ return 0; ++} ++ ++static struct platform_driver krait_cpufreq_platdrv = { ++ .driver = { ++ .name = "cpufreq-krait", ++ .owner = THIS_MODULE, ++ }, ++ .probe = krait_cpufreq_probe, ++ .remove = krait_cpufreq_remove, ++}; ++module_platform_driver(krait_cpufreq_platdrv); ++ ++MODULE_DESCRIPTION("Krait CPUfreq driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/cpufreq/qcom-cpufreq.c ++++ b/drivers/cpufreq/qcom-cpufreq.c +@@ -168,11 +168,8 @@ static int __init qcom_cpufreq_populate_ + + static int __init qcom_cpufreq_driver_init(void) + { +- struct cpufreq_dt_platform_data pdata = { .independent_clocks = true }; + struct platform_device_info devinfo = { +- .name = "cpufreq-dt", +- .data = &pdata, +- .size_data = sizeof(pdata), ++ .name = "cpufreq-krait", + }; + struct device *cpu_dev; + struct device_node *np; diff --git a/target/linux/ipq806x/patches-3.18/150-dmaengine-Rework-dma_chan_get.patch b/target/linux/ipq806x/patches-3.18/150-dmaengine-Rework-dma_chan_get.patch new file mode 100644 index 0000000..880e67c --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/150-dmaengine-Rework-dma_chan_get.patch @@ -0,0 +1,70 @@ +From d2f4f99db3e9ec8b063cf2e45704e2bb95428317 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Mon, 17 Nov 2014 14:41:58 +0100 +Subject: [PATCH] dmaengine: Rework dma_chan_get + +dma_chan_get uses a rather interesting error handling and code path. + +Change it to something more usual in the kernel. + +Signed-off-by: Maxime Ripard +Acked-by: Laurent Pinchart +Signed-off-by: Vinod Koul +--- + drivers/dma/dmaengine.c | 36 +++++++++++++++++++----------------- + 1 file changed, 19 insertions(+), 17 deletions(-) + +--- a/drivers/dma/dmaengine.c ++++ b/drivers/dma/dmaengine.c +@@ -222,31 +222,33 @@ static void balance_ref_count(struct dma + */ + static int dma_chan_get(struct dma_chan *chan) + { +- int err = -ENODEV; + struct module *owner = dma_chan_to_owner(chan); ++ int ret; + ++ /* The channel is already in use, update client count */ + if (chan->client_count) { + __module_get(owner); +- err = 0; +- } else if (try_module_get(owner)) +- err = 0; ++ goto out; ++ } + +- if (err == 0) +- chan->client_count++; ++ if (!try_module_get(owner)) ++ return -ENODEV; + + /* allocate upon first client reference */ +- if (chan->client_count == 1 && err == 0) { +- int desc_cnt = chan->device->device_alloc_chan_resources(chan); +- +- if (desc_cnt < 0) { +- err = desc_cnt; +- chan->client_count = 0; +- module_put(owner); +- } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask)) +- balance_ref_count(chan); +- } +- +- return err; ++ ret = chan->device->device_alloc_chan_resources(chan); ++ if (ret < 0) ++ goto err_out; ++ ++ if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask)) ++ balance_ref_count(chan); ++ ++out: ++ chan->client_count++; ++ return 0; ++ ++err_out: ++ module_put(owner); ++ return ret; + } + + /** diff --git a/target/linux/ipq806x/patches-3.18/151-dmaengine-Remove-the-need-to-declare-device_control.patch b/target/linux/ipq806x/patches-3.18/151-dmaengine-Remove-the-need-to-declare-device_control.patch new file mode 100644 index 0000000..b24a10b --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/151-dmaengine-Remove-the-need-to-declare-device_control.patch @@ -0,0 +1,27 @@ +From 4f8ef9f4140cc286d7d1cf9237da7a7439e4fc0b Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Mon, 17 Nov 2014 14:42:03 +0100 +Subject: [PATCH] dmaengine: Remove the need to declare device_control + +In order to migrate the drivers without triggering a BUG_ON for the converted +drivers, which would cause bisectability issues, we need to remove that check +before removing the device_control function entirely. + +Signed-off-by: Maxime Ripard +Acked-by: Laurent Pinchart +Signed-off-by: Vinod Koul +--- + drivers/dma/dmaengine.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/dma/dmaengine.c ++++ b/drivers/dma/dmaengine.c +@@ -814,8 +814,6 @@ int dma_async_device_register(struct dma + !device->device_prep_dma_sg); + BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) && + !device->device_prep_dma_cyclic); +- BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) && +- !device->device_control); + BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) && + !device->device_prep_interleaved_dma); + diff --git a/target/linux/ipq806x/patches-3.18/152-dmaengine-Make-channel-allocation-callbacks-optional.patch b/target/linux/ipq806x/patches-3.18/152-dmaengine-Make-channel-allocation-callbacks-optional.patch new file mode 100644 index 0000000..6337259 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/152-dmaengine-Make-channel-allocation-callbacks-optional.patch @@ -0,0 +1,62 @@ +From c4b54a648e682f678c338619df848233a6babc46 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Mon, 17 Nov 2014 14:41:59 +0100 +Subject: [PATCH] dmaengine: Make channel allocation callbacks optional + +Nowadays, some drivers don't have anything in there channel allocation +callbacks anymore. + +Remove the BUG_ON if those callbacks aren't implemented, in order to allow +drivers to not implement them. + +Signed-off-by: Maxime Ripard +Acked-by: Laurent Pinchart +Signed-off-by: Vinod Koul +--- + drivers/dma/dmaengine.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +--- a/drivers/dma/dmaengine.c ++++ b/drivers/dma/dmaengine.c +@@ -235,9 +235,11 @@ static int dma_chan_get(struct dma_chan + return -ENODEV; + + /* allocate upon first client reference */ +- ret = chan->device->device_alloc_chan_resources(chan); +- if (ret < 0) +- goto err_out; ++ if (chan->device->device_alloc_chan_resources) { ++ ret = chan->device->device_alloc_chan_resources(chan); ++ if (ret < 0) ++ goto err_out; ++ } + + if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask)) + balance_ref_count(chan); +@@ -259,11 +261,15 @@ err_out: + */ + static void dma_chan_put(struct dma_chan *chan) + { ++ /* This channel is not in use, bail out */ + if (!chan->client_count) +- return; /* this channel failed alloc_chan_resources */ ++ return; ++ + chan->client_count--; + module_put(dma_chan_to_owner(chan)); +- if (chan->client_count == 0) ++ ++ /* This channel is not in use anymore, free it */ ++ if (!chan->client_count && chan->device->device_free_chan_resources) + chan->device->device_free_chan_resources(chan); + } + +@@ -817,8 +823,6 @@ int dma_async_device_register(struct dma + BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) && + !device->device_prep_interleaved_dma); + +- BUG_ON(!device->device_alloc_chan_resources); +- BUG_ON(!device->device_free_chan_resources); + BUG_ON(!device->device_tx_status); + BUG_ON(!device->device_issue_pending); + BUG_ON(!device->dev); diff --git a/target/linux/ipq806x/patches-3.18/153-dmaengine-Introduce-a-device_config-callback.patch b/target/linux/ipq806x/patches-3.18/153-dmaengine-Introduce-a-device_config-callback.patch new file mode 100644 index 0000000..ced452f --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/153-dmaengine-Introduce-a-device_config-callback.patch @@ -0,0 +1,51 @@ +From 94a73e30dfe6722e9f4ef19f7892901d7d00eab1 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Mon, 17 Nov 2014 14:42:00 +0100 +Subject: [PATCH] dmaengine: Introduce a device_config callback + +The fact that the channel configuration is done in device_control is rather +misleading, since it's not really advertised as such, plus, the fact that the +framework exposes a function of its own makes it not really intuitive, while +we're losing the type checking whenever we pass that unsigned long argument. + +Add a device_config callback to dma_device, with a fallback on the old +behaviour for now for existing drivers to opt in. + +Signed-off-by: Maxime Ripard +Acked-by: Laurent Pinchart +Signed-off-by: Vinod Koul +--- + include/linux/dmaengine.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/include/linux/dmaengine.h ++++ b/include/linux/dmaengine.h +@@ -607,6 +607,8 @@ struct dma_tx_state { + * The function takes a buffer of size buf_len. The callback function will + * be called after period_len bytes have been transferred. + * @device_prep_interleaved_dma: Transfer expression in a generic way. ++ * @device_config: Pushes a new configuration to a channel, return 0 or an error ++ * code + * @device_control: manipulate all pending operations on a channel, returns + * zero or error code + * @device_tx_status: poll for transaction completion, the optional +@@ -673,6 +675,9 @@ struct dma_device { + struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( + struct dma_chan *chan, struct dma_interleaved_template *xt, + unsigned long flags); ++ ++ int (*device_config)(struct dma_chan *chan, ++ struct dma_slave_config *config); + int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg); + +@@ -696,6 +701,9 @@ static inline int dmaengine_device_contr + static inline int dmaengine_slave_config(struct dma_chan *chan, + struct dma_slave_config *config) + { ++ if (chan->device->device_config) ++ return chan->device->device_config(chan, config); ++ + return dmaengine_device_control(chan, DMA_SLAVE_CONFIG, + (unsigned long)config); + } diff --git a/target/linux/ipq806x/patches-3.18/154-dmaengine-Add-device_terminate_all-callback.patch b/target/linux/ipq806x/patches-3.18/154-dmaengine-Add-device_terminate_all-callback.patch new file mode 100644 index 0000000..422f7fb --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/154-dmaengine-Add-device_terminate_all-callback.patch @@ -0,0 +1,47 @@ +From 7fa0cf462daa6f6121b332b87833d7f5bdb515c0 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Mon, 17 Nov 2014 14:42:02 +0100 +Subject: [PATCH] dmaengine: Add device_terminate_all callback + +Split out the terminate_all command from device_control to a dma_device +callback. In order to preserve backward capability, still rely on +device_control if no such callback has been implemented. + +Eventually, this will allow to create a generic dma_slave_caps callback. + +Signed-off-by: Maxime Ripard +Acked-by: Laurent Pinchart +Signed-off-by: Vinod Koul +--- + include/linux/dmaengine.h | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/include/linux/dmaengine.h ++++ b/include/linux/dmaengine.h +@@ -611,6 +611,8 @@ struct dma_tx_state { + * code + * @device_control: manipulate all pending operations on a channel, returns + * zero or error code ++ * @device_terminate_all: Aborts all transfers on a channel. Returns 0 ++ * or an error code + * @device_tx_status: poll for transaction completion, the optional + * txstate parameter can be supplied with a pointer to get a + * struct with auxiliary transfer status information, otherwise the call +@@ -680,6 +682,7 @@ struct dma_device { + struct dma_slave_config *config); + int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg); ++ int (*device_terminate_all)(struct dma_chan *chan); + + enum dma_status (*device_tx_status)(struct dma_chan *chan, + dma_cookie_t cookie, +@@ -789,6 +792,9 @@ static inline int dma_get_slave_caps(str + + static inline int dmaengine_terminate_all(struct dma_chan *chan) + { ++ if (chan->device->device_terminate_all) ++ return chan->device->device_terminate_all(chan); ++ + return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); + } + diff --git a/target/linux/ipq806x/patches-3.18/155-dt-bindings-qcom_adm-Fix-channel-specifiers.patch b/target/linux/ipq806x/patches-3.18/155-dt-bindings-qcom_adm-Fix-channel-specifiers.patch new file mode 100644 index 0000000..4f5c0ef --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/155-dt-bindings-qcom_adm-Fix-channel-specifiers.patch @@ -0,0 +1,76 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v6,1/2] dt/bindings: qcom_adm: Fix channel specifiers +From: Andy Gross +X-Patchwork-Id: 6027361 +Message-Id: <1426571172-9711-2-git-send-email-agross@codeaurora.org> +To: Vinod Koul +Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, + linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, Kumar Gala , + Bjorn Andersson , + Andy Gross +Date: Tue, 17 Mar 2015 00:46:11 -0500 + +This patch removes the crci information from the dma channel property. At least +one client device requires using more than one CRCI value for a channel. This +does not match the current binding and the crci information needs to be removed. + +Instead, the client device will provide this information via other means. + +Signed-off-by: Andy Gross + +--- +Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++---------- + 1 file changed, 6 insertions(+), 10 deletions(-) + +--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt ++++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt +@@ -4,8 +4,7 @@ Required properties: + - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 + - reg: Address range for DMA registers + - interrupts: Should contain one interrupt shared by all channels +-- #dma-cells: must be <2>. First cell denotes the channel number. Second cell +- denotes CRCI (client rate control interface) flow control assignment. ++- #dma-cells: must be <1>. First cell denotes the channel number. + - clocks: Should contain the core clock and interface clock. + - clock-names: Must contain "core" for the core clock and "iface" for the + interface clock. +@@ -22,7 +21,7 @@ Example: + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <0 170 0>; +- #dma-cells = <2>; ++ #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; +@@ -35,15 +34,12 @@ Example: + qcom,ee = <0>; + }; + +-DMA clients must use the format descripted in the dma.txt file, using a three ++DMA clients must use the format descripted in the dma.txt file, using a two + cell specifier for each channel. + +-Each dmas request consists of 3 cells: ++Each dmas request consists of two cells: + 1. phandle pointing to the DMA controller + 2. channel number +- 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. +- The CRCI is used for flow control. It identifies the peripheral device that +- is the source/destination for the transferred data. + + Example: + +@@ -56,7 +52,7 @@ Example: + + cs-gpios = <&qcom_pinmux 20 0>; + +- dmas = <&adm_dma 6 9>, +- <&adm_dma 5 10>; ++ dmas = <&adm_dma 6>, ++ <&adm_dma 5>; + dma-names = "rx", "tx"; + }; diff --git a/target/linux/ipq806x/patches-3.18/156-dmaengine-Add-ADM-driver.patch b/target/linux/ipq806x/patches-3.18/156-dmaengine-Add-ADM-driver.patch new file mode 100644 index 0000000..16d000e --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/156-dmaengine-Add-ADM-driver.patch @@ -0,0 +1,958 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v6,2/2] dmaengine: Add ADM driver +From: Andy Gross +X-Patchwork-Id: 6027351 +Message-Id: <1426571172-9711-3-git-send-email-agross@codeaurora.org> +To: Vinod Koul +Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, + linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, Kumar Gala , + Bjorn Andersson , + Andy Gross +Date: Tue, 17 Mar 2015 00:46:12 -0500 + +Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA +controller found in the MSM8x60 and IPQ/APQ8064 platforms. + +The ADM supports both memory to memory transactions and memory +to/from peripheral device transactions. The controller also provides flow +control capabilities for transactions to/from peripheral devices. + +The initial release of this driver supports slave transfers to/from peripherals +and also incorporates CRCI (client rate control interface) flow control. + +Signed-off-by: Andy Gross +Reviewed-by: sricharan + +--- +drivers/dma/Kconfig | 10 + + drivers/dma/Makefile | 1 + + drivers/dma/qcom_adm.c | 900 ++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 911 insertions(+) + create mode 100644 drivers/dma/qcom_adm.c + +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -457,4 +457,14 @@ config QCOM_BAM_DMA + Enable support for the QCOM BAM DMA controller. This controller + provides DMA capabilities for a variety of on-chip devices. + ++config QCOM_ADM ++ tristate "Qualcomm ADM support" ++ depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) ++ select DMA_ENGINE ++ select DMA_VIRTUAL_CHANNELS ++ ---help--- ++ Enable support for the Qualcomm ADM DMA controller. This controller ++ provides DMA capabilities for both general purpose and on-chip ++ peripheral devices. ++ + endif +--- /dev/null ++++ b/drivers/dma/qcom_adm.c +@@ -0,0 +1,896 @@ ++/* ++ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dmaengine.h" ++#include "virt-dma.h" ++ ++/* ADM registers - calculated from channel number and security domain */ ++#define ADM_CHAN_MULTI 0x4 ++#define ADM_CI_MULTI 0x4 ++#define ADM_CRCI_MULTI 0x4 ++#define ADM_EE_MULTI 0x800 ++#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan) ++#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * ee) ++#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee)) ++#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan) ++#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci)) ++#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan)) ++#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee)) ++#define ADM_CI_CONF(ci) (0x390 + ci * ADM_CI_MULTI) ++#define ADM_GP_CTL 0x3d8 ++#define ADM_CRCI_CTL(crci, ee) (0x400 + crci * ADM_CRCI_MULTI + \ ++ ADM_EE_OFFS(ee)) ++ ++/* channel status */ ++#define ADM_CH_STATUS_VALID BIT(1) ++ ++/* channel result */ ++#define ADM_CH_RSLT_VALID BIT(31) ++#define ADM_CH_RSLT_ERR BIT(3) ++#define ADM_CH_RSLT_FLUSH BIT(2) ++#define ADM_CH_RSLT_TPD BIT(1) ++ ++/* channel conf */ ++#define ADM_CH_CONF_SHADOW_EN BIT(12) ++#define ADM_CH_CONF_MPU_DISABLE BIT(11) ++#define ADM_CH_CONF_PERM_MPU_CONF BIT(9) ++#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7) ++#define ADM_CH_CONF_SEC_DOMAIN(ee) (((ee & 0x3) << 4) | ((ee & 0x4) << 11)) ++ ++/* channel result conf */ ++#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1) ++#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0) ++ ++/* CRCI CTL */ ++#define ADM_CRCI_CTL_MUX_SEL BIT(18) ++#define ADM_CRCI_CTL_RST BIT(17) ++ ++/* CI configuration */ ++#define ADM_CI_RANGE_END(x) (x << 24) ++#define ADM_CI_RANGE_START(x) (x << 16) ++#define ADM_CI_BURST_4_WORDS BIT(2) ++#define ADM_CI_BURST_8_WORDS BIT(3) ++ ++/* GP CTL */ ++#define ADM_GP_CTL_LP_EN BIT(12) ++#define ADM_GP_CTL_LP_CNT(x) (x << 8) ++ ++/* Command pointer list entry */ ++#define ADM_CPLE_LP BIT(31) ++#define ADM_CPLE_CMD_PTR_LIST BIT(29) ++ ++/* Command list entry */ ++#define ADM_CMD_LC BIT(31) ++#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7) ++#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3) ++ ++#define ADM_CMD_TYPE_SINGLE 0x0 ++#define ADM_CMD_TYPE_BOX 0x3 ++ ++#define ADM_CRCI_MUX_SEL BIT(4) ++#define ADM_DESC_ALIGN 8 ++#define ADM_MAX_XFER (SZ_64K-1) ++#define ADM_MAX_ROWS (SZ_64K-1) ++#define ADM_MAX_CHANNELS 16 ++ ++struct adm_desc_hw_box { ++ u32 cmd; ++ u32 src_addr; ++ u32 dst_addr; ++ u32 row_len; ++ u32 num_rows; ++ u32 row_offset; ++}; ++ ++struct adm_desc_hw_single { ++ u32 cmd; ++ u32 src_addr; ++ u32 dst_addr; ++ u32 len; ++}; ++ ++struct adm_async_desc { ++ struct virt_dma_desc vd; ++ struct adm_device *adev; ++ ++ size_t length; ++ enum dma_transfer_direction dir; ++ dma_addr_t dma_addr; ++ size_t dma_len; ++ ++ void *cpl; ++ dma_addr_t cp_addr; ++ u32 crci; ++ u32 mux; ++ u32 blk_size; ++}; ++ ++struct adm_chan { ++ struct virt_dma_chan vc; ++ struct adm_device *adev; ++ ++ /* parsed from DT */ ++ u32 id; /* channel id */ ++ ++ struct adm_async_desc *curr_txd; ++ struct dma_slave_config slave; ++ struct list_head node; ++ ++ int error; ++ int initialized; ++}; ++ ++static inline struct adm_chan *to_adm_chan(struct dma_chan *common) ++{ ++ return container_of(common, struct adm_chan, vc.chan); ++} ++ ++struct adm_device { ++ void __iomem *regs; ++ struct device *dev; ++ struct dma_device common; ++ struct device_dma_parameters dma_parms; ++ struct adm_chan *channels; ++ ++ u32 ee; ++ ++ struct clk *core_clk; ++ struct clk *iface_clk; ++ ++ struct reset_control *clk_reset; ++ struct reset_control *c0_reset; ++ struct reset_control *c1_reset; ++ struct reset_control *c2_reset; ++ int irq; ++}; ++ ++/** ++ * adm_free_chan - Frees dma resources associated with the specific channel ++ * ++ * Free all allocated descriptors associated with this channel ++ * ++ */ ++static void adm_free_chan(struct dma_chan *chan) ++{ ++ /* free all queued descriptors */ ++ vchan_free_chan_resources(to_virt_chan(chan)); ++} ++ ++/** ++ * adm_get_blksize - Get block size from burst value ++ * ++ */ ++static int adm_get_blksize(unsigned int burst) ++{ ++ int ret; ++ ++ switch (burst) { ++ case 16: ++ case 32: ++ case 64: ++ case 128: ++ ret = ffs(burst>>4) - 1; ++ break; ++ case 192: ++ ret = 4; ++ break; ++ case 256: ++ ret = 5; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++/** ++ * adm_process_fc_descriptors - Process descriptors for flow controlled xfers ++ * ++ * @achan: ADM channel ++ * @desc: Descriptor memory pointer ++ * @sg: Scatterlist entry ++ * @crci: CRCI value ++ * @burst: Burst size of transaction ++ * @direction: DMA transfer direction ++ */ ++static void *adm_process_fc_descriptors(struct adm_chan *achan, ++ void *desc, struct scatterlist *sg, u32 crci, u32 burst, ++ enum dma_transfer_direction direction) ++{ ++ struct adm_desc_hw_box *box_desc = NULL; ++ struct adm_desc_hw_single *single_desc; ++ u32 remainder = sg_dma_len(sg); ++ u32 rows, row_offset, crci_cmd; ++ u32 mem_addr = sg_dma_address(sg); ++ u32 *incr_addr = &mem_addr; ++ u32 *src, *dst; ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ crci_cmd = ADM_CMD_SRC_CRCI(crci); ++ row_offset = burst; ++ src = &achan->slave.src_addr; ++ dst = &mem_addr; ++ } else { ++ crci_cmd = ADM_CMD_DST_CRCI(crci); ++ row_offset = burst << 16; ++ src = &mem_addr; ++ dst = &achan->slave.dst_addr; ++ } ++ ++ while (remainder >= burst) { ++ box_desc = desc; ++ box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd; ++ box_desc->row_offset = row_offset; ++ box_desc->src_addr = *src; ++ box_desc->dst_addr = *dst; ++ ++ rows = remainder / burst; ++ rows = min_t(u32, rows, ADM_MAX_ROWS); ++ box_desc->num_rows = rows << 16 | rows; ++ box_desc->row_len = burst << 16 | burst; ++ ++ *incr_addr += burst * rows; ++ remainder -= burst * rows; ++ desc += sizeof(*box_desc); ++ } ++ ++ /* if leftover bytes, do one single descriptor */ ++ if (remainder) { ++ single_desc = desc; ++ single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd; ++ single_desc->len = remainder; ++ single_desc->src_addr = *src; ++ single_desc->dst_addr = *dst; ++ desc += sizeof(*single_desc); ++ ++ if (sg_is_last(sg)) ++ single_desc->cmd |= ADM_CMD_LC; ++ } else { ++ if (box_desc && sg_is_last(sg)) ++ box_desc->cmd |= ADM_CMD_LC; ++ } ++ ++ return desc; ++} ++ ++/** ++ * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers ++ * ++ * @achan: ADM channel ++ * @desc: Descriptor memory pointer ++ * @sg: Scatterlist entry ++ * @direction: DMA transfer direction ++ */ ++static void *adm_process_non_fc_descriptors(struct adm_chan *achan, ++ void *desc, struct scatterlist *sg, ++ enum dma_transfer_direction direction) ++{ ++ struct adm_desc_hw_single *single_desc; ++ u32 remainder = sg_dma_len(sg); ++ u32 mem_addr = sg_dma_address(sg); ++ u32 *incr_addr = &mem_addr; ++ u32 *src, *dst; ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ src = &achan->slave.src_addr; ++ dst = &mem_addr; ++ } else { ++ src = &mem_addr; ++ dst = &achan->slave.dst_addr; ++ } ++ ++ do { ++ single_desc = desc; ++ single_desc->cmd = ADM_CMD_TYPE_SINGLE; ++ single_desc->src_addr = *src; ++ single_desc->dst_addr = *dst; ++ single_desc->len = (remainder > ADM_MAX_XFER) ? ++ ADM_MAX_XFER : remainder; ++ ++ remainder -= single_desc->len; ++ *incr_addr += single_desc->len; ++ desc += sizeof(*single_desc); ++ } while (remainder); ++ ++ /* set last command if this is the end of the whole transaction */ ++ if (sg_is_last(sg)) ++ single_desc->cmd |= ADM_CMD_LC; ++ ++ return desc; ++} ++ ++/** ++ * adm_prep_slave_sg - Prep slave sg transaction ++ * ++ * @chan: dma channel ++ * @sgl: scatter gather list ++ * @sg_len: length of sg ++ * @direction: DMA transfer direction ++ * @flags: DMA flags ++ * @context: transfer context (unused) ++ */ ++static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan, ++ struct scatterlist *sgl, unsigned int sg_len, ++ enum dma_transfer_direction direction, unsigned long flags, ++ void *context) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct adm_device *adev = achan->adev; ++ struct adm_async_desc *async_desc; ++ struct scatterlist *sg; ++ u32 i, burst; ++ u32 single_count = 0, box_count = 0, crci = 0; ++ void *desc; ++ u32 *cple; ++ int blk_size = 0; ++ ++ if (!is_slave_direction(direction)) { ++ dev_err(adev->dev, "invalid dma direction\n"); ++ return NULL; ++ } ++ ++ /* ++ * get burst value from slave configuration ++ */ ++ burst = (direction == DMA_MEM_TO_DEV) ? ++ achan->slave.dst_maxburst : ++ achan->slave.src_maxburst; ++ ++ /* if using flow control, validate burst and crci values */ ++ if (achan->slave.device_fc) { ++ ++ blk_size = adm_get_blksize(burst); ++ if (blk_size < 0) { ++ dev_err(adev->dev, "invalid burst value: %d\n", ++ burst); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ crci = achan->slave.slave_id & 0xf; ++ if (!crci || achan->slave.slave_id > 0x1f) { ++ dev_err(adev->dev, "invalid crci value\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ } ++ ++ /* iterate through sgs and compute allocation size of structures */ ++ for_each_sg(sgl, sg, sg_len, i) { ++ if (achan->slave.device_fc) { ++ box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst, ++ ADM_MAX_ROWS); ++ if (sg_dma_len(sg) % burst) ++ single_count++; ++ } else { ++ single_count += DIV_ROUND_UP(sg_dma_len(sg), ++ ADM_MAX_XFER); ++ } ++ } ++ ++ async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT); ++ if (!async_desc) ++ return ERR_PTR(-ENOMEM); ++ ++ if (crci) ++ async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ? ++ ADM_CRCI_CTL_MUX_SEL : 0; ++ async_desc->crci = crci; ++ async_desc->blk_size = blk_size; ++ async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) + ++ box_count * sizeof(struct adm_desc_hw_box) + ++ sizeof(*cple) + 2 * ADM_DESC_ALIGN; ++ ++ async_desc->cpl = dma_alloc_writecombine(adev->dev, async_desc->dma_len, ++ &async_desc->dma_addr, GFP_NOWAIT); ++ ++ if (!async_desc->cpl) { ++ kfree(async_desc); ++ return ERR_PTR(-ENOMEM); ++ } ++ ++ async_desc->adev = adev; ++ ++ /* both command list entry and descriptors must be 8 byte aligned */ ++ cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN); ++ desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN); ++ ++ /* init cmd list */ ++ *cple = ADM_CPLE_LP; ++ *cple |= (desc - async_desc->cpl + async_desc->dma_addr) >> 3; ++ ++ for_each_sg(sgl, sg, sg_len, i) { ++ async_desc->length += sg_dma_len(sg); ++ ++ if (achan->slave.device_fc) ++ desc = adm_process_fc_descriptors(achan, desc, sg, crci, ++ burst, direction); ++ else ++ desc = adm_process_non_fc_descriptors(achan, desc, sg, ++ direction); ++ } ++ ++ return vchan_tx_prep(&achan->vc, &async_desc->vd, flags); ++} ++ ++/** ++ * adm_terminate_all - terminate all transactions on a channel ++ * @achan: adm dma channel ++ * ++ * Dequeues and frees all transactions, aborts current transaction ++ * No callbacks are done ++ * ++ */ ++static int adm_terminate_all(struct dma_chan *chan) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct adm_device *adev = achan->adev; ++ unsigned long flags; ++ LIST_HEAD(head); ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ vchan_get_all_descriptors(&achan->vc, &head); ++ ++ /* send flush command to terminate current transaction */ ++ writel_relaxed(0x0, ++ adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee)); ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ ++ vchan_dma_desc_free_list(&achan->vc, &head); ++ ++ return 0; ++} ++ ++static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ unsigned long flag; ++ ++ spin_lock_irqsave(&achan->vc.lock, flag); ++ memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config)); ++ spin_unlock_irqrestore(&achan->vc.lock, flag); ++ ++ return 0; ++} ++ ++/** ++ * adm_start_dma - start next transaction ++ * @achan - ADM dma channel ++ */ ++static void adm_start_dma(struct adm_chan *achan) ++{ ++ struct virt_dma_desc *vd = vchan_next_desc(&achan->vc); ++ struct adm_device *adev = achan->adev; ++ struct adm_async_desc *async_desc; ++ ++ lockdep_assert_held(&achan->vc.lock); ++ ++ if (!vd) ++ return; ++ ++ list_del(&vd->node); ++ ++ /* write next command list out to the CMD FIFO */ ++ async_desc = container_of(vd, struct adm_async_desc, vd); ++ achan->curr_txd = async_desc; ++ ++ /* reset channel error */ ++ achan->error = 0; ++ ++ if (!achan->initialized) { ++ /* enable interrupts */ ++ writel(ADM_CH_CONF_SHADOW_EN | ++ ADM_CH_CONF_PERM_MPU_CONF | ++ ADM_CH_CONF_MPU_DISABLE | ++ ADM_CH_CONF_SEC_DOMAIN(adev->ee), ++ adev->regs + ADM_CH_CONF(achan->id)); ++ ++ writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN, ++ adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); ++ ++ achan->initialized = 1; ++ } ++ ++ /* set the crci block size if this transaction requires CRCI */ ++ if (async_desc->crci) { ++ writel(async_desc->mux | async_desc->blk_size, ++ adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee)); ++ } ++ ++ /* make sure IRQ enable doesn't get reordered */ ++ wmb(); ++ ++ /* write next command list out to the CMD FIFO */ ++ writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3, ++ adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee)); ++} ++ ++/** ++ * adm_dma_irq - irq handler for ADM controller ++ * @irq: IRQ of interrupt ++ * @data: callback data ++ * ++ * IRQ handler for the bam controller ++ */ ++static irqreturn_t adm_dma_irq(int irq, void *data) ++{ ++ struct adm_device *adev = data; ++ u32 srcs, i; ++ struct adm_async_desc *async_desc; ++ unsigned long flags; ++ ++ srcs = readl_relaxed(adev->regs + ++ ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee)); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) { ++ struct adm_chan *achan = &adev->channels[i]; ++ u32 status, result; ++ ++ if (srcs & BIT(i)) { ++ status = readl_relaxed(adev->regs + ++ ADM_CH_STATUS_SD(i, adev->ee)); ++ ++ /* if no result present, skip */ ++ if (!(status & ADM_CH_STATUS_VALID)) ++ continue; ++ ++ result = readl_relaxed(adev->regs + ++ ADM_CH_RSLT(i, adev->ee)); ++ ++ /* no valid results, skip */ ++ if (!(result & ADM_CH_RSLT_VALID)) ++ continue; ++ ++ /* flag error if transaction was flushed or failed */ ++ if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH)) ++ achan->error = 1; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ async_desc = achan->curr_txd; ++ ++ achan->curr_txd = NULL; ++ ++ if (async_desc) { ++ vchan_cookie_complete(&async_desc->vd); ++ ++ /* kick off next DMA */ ++ adm_start_dma(achan); ++ } ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/** ++ * adm_tx_status - returns status of transaction ++ * @chan: dma channel ++ * @cookie: transaction cookie ++ * @txstate: DMA transaction state ++ * ++ * Return status of dma transaction ++ */ ++static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie, ++ struct dma_tx_state *txstate) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct virt_dma_desc *vd; ++ enum dma_status ret; ++ unsigned long flags; ++ size_t residue = 0; ++ ++ ret = dma_cookie_status(chan, cookie, txstate); ++ if (ret == DMA_COMPLETE || !txstate) ++ return ret; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ ++ vd = vchan_find_desc(&achan->vc, cookie); ++ if (vd) ++ residue = container_of(vd, struct adm_async_desc, vd)->length; ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ ++ /* ++ * residue is either the full length if it is in the issued list, or 0 ++ * if it is in progress. We have no reliable way of determining ++ * anything inbetween ++ */ ++ dma_set_residue(txstate, residue); ++ ++ if (achan->error) ++ return DMA_ERROR; ++ ++ return ret; ++} ++ ++/** ++ * adm_issue_pending - starts pending transactions ++ * @chan: dma channel ++ * ++ * Issues all pending transactions and starts DMA ++ */ ++static void adm_issue_pending(struct dma_chan *chan) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ ++ if (vchan_issue_pending(&achan->vc) && !achan->curr_txd) ++ adm_start_dma(achan); ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++} ++ ++/** ++ * adm_dma_free_desc - free descriptor memory ++ * @vd: virtual descriptor ++ * ++ */ ++static void adm_dma_free_desc(struct virt_dma_desc *vd) ++{ ++ struct adm_async_desc *async_desc = container_of(vd, ++ struct adm_async_desc, vd); ++ ++ dma_free_writecombine(async_desc->adev->dev, async_desc->dma_len, ++ async_desc->cpl, async_desc->dma_addr); ++ kfree(async_desc); ++} ++ ++static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan, ++ u32 index) ++{ ++ achan->id = index; ++ achan->adev = adev; ++ ++ vchan_init(&achan->vc, &adev->common); ++ achan->vc.desc_free = adm_dma_free_desc; ++} ++ ++static int adm_dma_probe(struct platform_device *pdev) ++{ ++ struct adm_device *adev; ++ struct resource *iores; ++ int ret; ++ u32 i; ++ ++ adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); ++ if (!adev) ++ return -ENOMEM; ++ ++ adev->dev = &pdev->dev; ++ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ adev->regs = devm_ioremap_resource(&pdev->dev, iores); ++ if (IS_ERR(adev->regs)) ++ return PTR_ERR(adev->regs); ++ ++ adev->irq = platform_get_irq(pdev, 0); ++ if (adev->irq < 0) ++ return adev->irq; ++ ++ ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee); ++ if (ret) { ++ dev_err(adev->dev, "Execution environment unspecified\n"); ++ return ret; ++ } ++ ++ adev->core_clk = devm_clk_get(adev->dev, "core"); ++ if (IS_ERR(adev->core_clk)) ++ return PTR_ERR(adev->core_clk); ++ ++ ret = clk_prepare_enable(adev->core_clk); ++ if (ret) { ++ dev_err(adev->dev, "failed to prepare/enable core clock\n"); ++ return ret; ++ } ++ ++ adev->iface_clk = devm_clk_get(adev->dev, "iface"); ++ if (IS_ERR(adev->iface_clk)) { ++ ret = PTR_ERR(adev->iface_clk); ++ goto err_disable_core_clk; ++ } ++ ++ ret = clk_prepare_enable(adev->iface_clk); ++ if (ret) { ++ dev_err(adev->dev, "failed to prepare/enable iface clock\n"); ++ goto err_disable_core_clk; ++ } ++ ++ adev->clk_reset = devm_reset_control_get(&pdev->dev, "clk"); ++ if (IS_ERR(adev->clk_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 reset\n"); ++ ret = PTR_ERR(adev->clk_reset); ++ goto err_disable_clks; ++ } ++ ++ adev->c0_reset = devm_reset_control_get(&pdev->dev, "c0"); ++ if (IS_ERR(adev->c0_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C0 reset\n"); ++ ret = PTR_ERR(adev->c0_reset); ++ goto err_disable_clks; ++ } ++ ++ adev->c1_reset = devm_reset_control_get(&pdev->dev, "c1"); ++ if (IS_ERR(adev->c1_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C1 reset\n"); ++ ret = PTR_ERR(adev->c1_reset); ++ goto err_disable_clks; ++ } ++ ++ adev->c2_reset = devm_reset_control_get(&pdev->dev, "c2"); ++ if (IS_ERR(adev->c2_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C2 reset\n"); ++ ret = PTR_ERR(adev->c2_reset); ++ goto err_disable_clks; ++ } ++ ++ reset_control_assert(adev->clk_reset); ++ reset_control_assert(adev->c0_reset); ++ reset_control_assert(adev->c1_reset); ++ reset_control_assert(adev->c2_reset); ++ ++ reset_control_deassert(adev->clk_reset); ++ reset_control_deassert(adev->c0_reset); ++ reset_control_deassert(adev->c1_reset); ++ reset_control_deassert(adev->c2_reset); ++ ++ adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS, ++ sizeof(*adev->channels), GFP_KERNEL); ++ ++ if (!adev->channels) { ++ ret = -ENOMEM; ++ goto err_disable_clks; ++ } ++ ++ /* allocate and initialize channels */ ++ INIT_LIST_HEAD(&adev->common.channels); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) ++ adm_channel_init(adev, &adev->channels[i], i); ++ ++ /* reset CRCIs */ ++ for (i = 0; i < 16; i++) ++ writel(ADM_CRCI_CTL_RST, adev->regs + ++ ADM_CRCI_CTL(i, adev->ee)); ++ ++ /* configure client interfaces */ ++ writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0)); ++ writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1)); ++ writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2)); ++ writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf), ++ adev->regs + ADM_GP_CTL); ++ ++ ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq, ++ 0, "adm_dma", adev); ++ if (ret) ++ goto err_disable_clks; ++ ++ platform_set_drvdata(pdev, adev); ++ ++ adev->common.dev = adev->dev; ++ adev->common.dev->dma_parms = &adev->dma_parms; ++ ++ /* set capabilities */ ++ dma_cap_zero(adev->common.cap_mask); ++ dma_cap_set(DMA_SLAVE, adev->common.cap_mask); ++ dma_cap_set(DMA_PRIVATE, adev->common.cap_mask); ++ ++ /* initialize dmaengine apis */ ++ adev->common.device_free_chan_resources = adm_free_chan; ++ adev->common.device_prep_slave_sg = adm_prep_slave_sg; ++ adev->common.device_issue_pending = adm_issue_pending; ++ adev->common.device_tx_status = adm_tx_status; ++ adev->common.device_terminate_all = adm_terminate_all; ++ adev->common.device_config = adm_slave_config; ++ ++ ret = dma_async_device_register(&adev->common); ++ if (ret) { ++ dev_err(adev->dev, "failed to register dma async device\n"); ++ goto err_disable_clks; ++ } ++ ++ ret = of_dma_controller_register(pdev->dev.of_node, ++ of_dma_xlate_by_chan_id, ++ &adev->common); ++ if (ret) ++ goto err_unregister_dma; ++ ++ return 0; ++ ++err_unregister_dma: ++ dma_async_device_unregister(&adev->common); ++err_disable_clks: ++ clk_disable_unprepare(adev->iface_clk); ++err_disable_core_clk: ++ clk_disable_unprepare(adev->core_clk); ++ ++ return ret; ++} ++ ++static int adm_dma_remove(struct platform_device *pdev) ++{ ++ struct adm_device *adev = platform_get_drvdata(pdev); ++ struct adm_chan *achan; ++ u32 i; ++ ++ of_dma_controller_free(pdev->dev.of_node); ++ dma_async_device_unregister(&adev->common); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) { ++ achan = &adev->channels[i]; ++ ++ /* mask IRQs for this channel/EE pair */ ++ writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); ++ ++ adm_terminate_all(&adev->channels[i].vc.chan); ++ } ++ ++ devm_free_irq(adev->dev, adev->irq, adev); ++ ++ clk_disable_unprepare(adev->core_clk); ++ clk_disable_unprepare(adev->iface_clk); ++ ++ return 0; ++} ++ ++static const struct of_device_id adm_of_match[] = { ++ { .compatible = "qcom,adm", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, adm_of_match); ++ ++static struct platform_driver adm_dma_driver = { ++ .probe = adm_dma_probe, ++ .remove = adm_dma_remove, ++ .driver = { ++ .name = "adm-dma-engine", ++ .of_match_table = adm_of_match, ++ }, ++}; ++ ++module_platform_driver(adm_dma_driver); ++ ++MODULE_AUTHOR("Andy Gross "); ++MODULE_DESCRIPTION("QCOM ADM DMA engine driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/dma/Makefile ++++ b/drivers/dma/Makefile +@@ -49,3 +49,4 @@ obj-y += xilinx/ + obj-$(CONFIG_INTEL_MIC_X100_DMA) += mic_x100_dma.o + obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o + obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o ++obj-$(CONFIG_QCOM_ADM) += qcom_adm.o diff --git a/target/linux/ipq806x/patches-3.18/157-ARM-DT-ipq8064-Add-ADM-device-node.patch b/target/linux/ipq806x/patches-3.18/157-ARM-DT-ipq8064-Add-ADM-device-node.patch new file mode 100644 index 0000000..657e36a --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/157-ARM-DT-ipq8064-Add-ADM-device-node.patch @@ -0,0 +1,42 @@ +From 1fb18acab2d71e7e4efd9c10492edb1baf84dcc0 Mon Sep 17 00:00:00 2001 +From: Andy Gross +Date: Wed, 20 May 2015 15:41:07 +0530 +Subject: [PATCH] ARM: DT: ipq8064: Add ADM device node + +This patch adds support for the ADM DMA on the IPQ8064 SOC + +Signed-off-by: Andy Gross +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 4 ++++ + arch/arm/boot/dts/qcom-ipq8064.dtsi | 21 +++++++++++++++++++++ + 2 files changed, 25 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -662,6 +662,26 @@ + }; + }; + ++ adm_dma: dma@18300000 { ++ compatible = "qcom,adm"; ++ reg = <0x18300000 0x100000>; ++ interrupts = <0 170 0>; ++ #dma-cells = <1>; ++ ++ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; ++ clock-names = "core", "iface"; ++ ++ resets = <&gcc ADM0_RESET>, ++ <&gcc ADM0_PBUS_RESET>, ++ <&gcc ADM0_C0_RESET>, ++ <&gcc ADM0_C1_RESET>, ++ <&gcc ADM0_C2_RESET>; ++ reset-names = "clk", "pbus", "c0", "c1", "c2"; ++ qcom,ee = <0>; ++ ++ status = "disabled"; ++ }; ++ + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-3.18/160-clk-qcom-Add-EBI2-clocks-for-IPQ806x.patch b/target/linux/ipq806x/patches-3.18/160-clk-qcom-Add-EBI2-clocks-for-IPQ806x.patch new file mode 100644 index 0000000..77d29d8 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/160-clk-qcom-Add-EBI2-clocks-for-IPQ806x.patch @@ -0,0 +1,74 @@ +From 4c385b25fab119144bffb255ad77712fe586ac10 Mon Sep 17 00:00:00 2001 +From: Archit Taneja +Date: Thu, 2 Apr 2015 11:20:41 +0530 +Subject: [PATCH] clk: qcom: Add EBI2 clocks for IPQ806x + +The NAND controller within EBI2 requires EBI2_CLK and +EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so +that they can be used by the NAND controller driver. Add an entry +for EBI2_AON_CLK in the gcc-ipq806x DT binding document. + +Signed-off-by: Archit Taneja +Signed-off-by: Stephen Boyd +--- + drivers/clk/qcom/gcc-ipq806x.c | 32 ++++++++++++++++++++++++++++ + include/dt-bindings/clock/qcom,gcc-ipq806x.h | 1 + + 2 files changed, 33 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -2239,6 +2239,36 @@ static struct clk_branch usb_fs1_h_clk = + }, + }; + ++static struct clk_branch ebi2_clk = { ++ .hwcg_reg = 0x3b00, ++ .hwcg_bit = 6, ++ .halt_reg = 0x2fcc, ++ .halt_bit = 1, ++ .clkr = { ++ .enable_reg = 0x3b00, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "ebi2_clk", ++ .ops = &clk_branch_ops, ++ .flags = CLK_IS_ROOT, ++ }, ++ }, ++}; ++ ++static struct clk_branch ebi2_aon_clk = { ++ .halt_reg = 0x2fcc, ++ .halt_bit = 0, ++ .clkr = { ++ .enable_reg = 0x3b00, ++ .enable_mask = BIT(8), ++ .hw.init = &(struct clk_init_data){ ++ .name = "ebi2_always_on_clk", ++ .ops = &clk_branch_ops, ++ .flags = CLK_IS_ROOT, ++ }, ++ }, ++}; ++ + static struct clk_regmap *gcc_ipq806x_clks[] = { + [PLL0] = &pll0.clkr, + [PLL0_VOTE] = &pll0_vote, +@@ -2341,6 +2371,8 @@ static struct clk_regmap *gcc_ipq806x_cl + [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, + [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, + [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, ++ [EBI2_CLK] = &ebi2_clk.clkr, ++ [EBI2_AON_CLK] = &ebi2_aon_clk.clkr, + [PLL9] = &hfpll0.clkr, + [PLL10] = &hfpll1.clkr, + [PLL12] = &hfpll_l2.clkr, +--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h +@@ -289,5 +289,6 @@ + #define UBI32_CORE2_CLK_SRC 278 + #define UBI32_CORE1_CLK 279 + #define UBI32_CORE2_CLK 280 ++#define EBI2_AON_CLK 281 + + #endif diff --git a/target/linux/ipq806x/patches-3.18/161-mtd-nand-Create-a-BBT-flag-to-access-bad-block-markers-in-raw-mode.patch b/target/linux/ipq806x/patches-3.18/161-mtd-nand-Create-a-BBT-flag-to-access-bad-block-markers-in-raw-mode.patch new file mode 100644 index 0000000..3fb4785 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/161-mtd-nand-Create-a-BBT-flag-to-access-bad-block-markers-in-raw-mode.patch @@ -0,0 +1,84 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3, + 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw + mode +From: Archit Taneja +X-Patchwork-Id: 6927081 +Message-Id: <1438578498-32254-2-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja +Date: Mon, 3 Aug 2015 10:38:14 +0530 + +Some controllers can access the factory bad block marker from OOB only +when they read it in raw mode. When ECC is enabled, these controllers +discard reading/writing bad block markers, preventing access to them +altogether. + +The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks. +This results in the nand driver's ecc->read_oob() op to be called, which +works with ECC enabled. + +Create a new BBT option flag that tells nand_bbt to force the mode to +MTD_OPS_RAW. This would result in the correct op being called for the +underlying nand controller driver. + +Reviewed-by: Andy Gross +Signed-off-by: Archit Taneja + +--- +drivers/mtd/nand/nand_base.c | 6 +++++- + drivers/mtd/nand/nand_bbt.c | 6 +++++- + include/linux/mtd/bbm.h | 7 +++++++ + 3 files changed, 17 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -396,7 +396,11 @@ static int nand_default_block_markbad(st + } else { + ops.len = ops.ooblen = 1; + } +- ops.mode = MTD_OPS_PLACE_OOB; ++ ++ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW)) ++ ops.mode = MTD_OPS_RAW; ++ else ++ ops.mode = MTD_OPS_PLACE_OOB; + + /* Write to first/last page(s) if necessary */ + if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) +--- a/drivers/mtd/nand/nand_bbt.c ++++ b/drivers/mtd/nand/nand_bbt.c +@@ -423,7 +423,11 @@ static int scan_block_fast(struct mtd_in + ops.oobbuf = buf; + ops.ooboffs = 0; + ops.datbuf = NULL; +- ops.mode = MTD_OPS_PLACE_OOB; ++ ++ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW)) ++ ops.mode = MTD_OPS_RAW; ++ else ++ ops.mode = MTD_OPS_PLACE_OOB; + + for (j = 0; j < numpages; j++) { + /* +--- a/include/linux/mtd/bbm.h ++++ b/include/linux/mtd/bbm.h +@@ -116,6 +116,13 @@ struct nand_bbt_descr { + #define NAND_BBT_NO_OOB_BBM 0x00080000 + + /* ++ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To ++ * be used by controllers which can access BBM only when ECC is disabled, i.e, ++ * when in RAW access mode ++ */ ++#define NAND_BBT_ACCESS_BBM_RAW 0x00100000 ++ ++/* + * Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr + * was allocated dynamicaly and must be freed in nand_release(). Has no meaning + * in nand_chip.bbt_options. diff --git a/target/linux/ipq806x/patches-3.18/162-mtd-nand-Qualcomm-NAND-controller-driver.patch b/target/linux/ipq806x/patches-3.18/162-mtd-nand-Qualcomm-NAND-controller-driver.patch new file mode 100644 index 0000000..6172f7d --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/162-mtd-nand-Qualcomm-NAND-controller-driver.patch @@ -0,0 +1,2024 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,2/5] mtd: nand: Qualcomm NAND controller driver +From: Archit Taneja +X-Patchwork-Id: 6927101 +Message-Id: <1438578498-32254-3-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja +Date: Mon, 3 Aug 2015 10:38:15 +0530 + +The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, +MDM9x15 series. + +It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) +and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a +broader interface for external slow peripheral devices such as LCD and +NAND/NOR flash memory or SRAM like interfaces. + +We add support for the NAND controller found within EBI2. For the SoCs +of our interest, we only use the NAND controller within EBI2. Therefore, +it's safe for us to assume that the NAND controller is a standalone block +within the SoC. + +The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND +flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and +16 bit correction/step) and RS ECC(4 bit correction/step) that covers main +and spare data. The controller contains an internal 512 byte page buffer +to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA +for register read/write and data transfers. The controller performs page +reads and writes at a codeword/step level of 512 bytes. It can support up +to 2 external chips of different configurations. + +The driver prepares register read and write configuration descriptors for +each codeword, followed by data descriptors to read or write data from the +controller's internal buffer. It uses a single ADM DMA channel that we get +via dmaengine API. The controller requires 2 ADM CRCIs for command and +data flow control. These are passed via DT. + +The ecc layout used by the controller is syndrome like, but we can't use +the standard syndrome ecc ops because of several reasons. First, the amount +of data bytes covered by ecc isn't same in each step. Second, writing to +free oob space requires us writing to the entire step in which the oob +lies. This forces us to create our own ecc ops. + +One more difference is how the controller accesses the bad block marker. +The controller ignores reading the marker when ECC is enabled. ECC needs +to be explicity disabled to read or write to the bad block marker. For +this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to +read the factory provided bad block markers. + +v3: +- Refactor dma functions for maximum reuse +- Use dma_slave_confing on stack +- optimize and clean upempty_page_fixup using memchr_inv +- ensure portability with dma register reads using le32_* funcs +- use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves +- fix handling of return values of dmaengine funcs +- constify wherever possible +- Remove dependency on ADM DMA in Kconfig +- Misc fixes and clean ups + +v2: +- Use new BBT flag that allows us to read BBM in raw mode +- reduce memcpy-s in the driver +- some refactor and clean ups because of above changes + +Reviewed-by: Andy Gross +Signed-off-by: Archit Taneja + +--- +drivers/mtd/nand/Kconfig | 7 + + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/qcom_nandc.c | 1913 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 1921 insertions(+) + create mode 100644 drivers/mtd/nand/qcom_nandc.c + +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -516,4 +516,11 @@ config MTD_NAND_XWAY + Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached + to the External Bus Unit (EBU). + ++config MTD_NAND_QCOM ++ tristate "Support for NAND on QCOM SoCs" ++ depends on ARCH_QCOM ++ help ++ Enables support for NAND flash chips on SoCs containing the EBI2 NAND ++ controller. This controller is found on IPQ806x SoC. ++ + endif # MTD_NAND +--- /dev/null ++++ b/drivers/mtd/nand/qcom_nandc.c +@@ -0,0 +1,1918 @@ ++/* ++ * Copyright (c) 2015, The Linux Foundation. All rights reserved. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* NANDc reg offsets */ ++#define NAND_FLASH_CMD 0x00 ++#define NAND_ADDR0 0x04 ++#define NAND_ADDR1 0x08 ++#define NAND_FLASH_CHIP_SELECT 0x0c ++#define NAND_EXEC_CMD 0x10 ++#define NAND_FLASH_STATUS 0x14 ++#define NAND_BUFFER_STATUS 0x18 ++#define NAND_DEV0_CFG0 0x20 ++#define NAND_DEV0_CFG1 0x24 ++#define NAND_DEV0_ECC_CFG 0x28 ++#define NAND_DEV1_ECC_CFG 0x2c ++#define NAND_DEV1_CFG0 0x30 ++#define NAND_DEV1_CFG1 0x34 ++#define NAND_READ_ID 0x40 ++#define NAND_READ_STATUS 0x44 ++#define NAND_DEV_CMD0 0xa0 ++#define NAND_DEV_CMD1 0xa4 ++#define NAND_DEV_CMD2 0xa8 ++#define NAND_DEV_CMD_VLD 0xac ++#define SFLASHC_BURST_CFG 0xe0 ++#define NAND_ERASED_CW_DETECT_CFG 0xe8 ++#define NAND_ERASED_CW_DETECT_STATUS 0xec ++#define NAND_EBI2_ECC_BUF_CFG 0xf0 ++#define FLASH_BUF_ACC 0x100 ++ ++#define NAND_CTRL 0xf00 ++#define NAND_VERSION 0xf08 ++#define NAND_READ_LOCATION_0 0xf20 ++#define NAND_READ_LOCATION_1 0xf24 ++ ++/* dummy register offsets, used by write_reg_dma */ ++#define NAND_DEV_CMD1_RESTORE 0xdead ++#define NAND_DEV_CMD_VLD_RESTORE 0xbeef ++ ++/* NAND_FLASH_CMD bits */ ++#define PAGE_ACC BIT(4) ++#define LAST_PAGE BIT(5) ++ ++/* NAND_FLASH_CHIP_SELECT bits */ ++#define NAND_DEV_SEL 0 ++#define DM_EN BIT(2) ++ ++/* NAND_FLASH_STATUS bits */ ++#define FS_OP_ERR BIT(4) ++#define FS_READY_BSY_N BIT(5) ++#define FS_MPU_ERR BIT(8) ++#define FS_DEVICE_STS_ERR BIT(16) ++#define FS_DEVICE_WP BIT(23) ++ ++/* NAND_BUFFER_STATUS bits */ ++#define BS_UNCORRECTABLE_BIT BIT(8) ++#define BS_CORRECTABLE_ERR_MSK 0x1f ++ ++/* NAND_DEVn_CFG0 bits */ ++#define DISABLE_STATUS_AFTER_WRITE 4 ++#define CW_PER_PAGE 6 ++#define UD_SIZE_BYTES 9 ++#define ECC_PARITY_SIZE_BYTES_RS 19 ++#define SPARE_SIZE_BYTES 23 ++#define NUM_ADDR_CYCLES 27 ++#define STATUS_BFR_READ 30 ++#define SET_RD_MODE_AFTER_STATUS 31 ++ ++/* NAND_DEVn_CFG0 bits */ ++#define DEV0_CFG1_ECC_DISABLE 0 ++#define WIDE_FLASH 1 ++#define NAND_RECOVERY_CYCLES 2 ++#define CS_ACTIVE_BSY 5 ++#define BAD_BLOCK_BYTE_NUM 6 ++#define BAD_BLOCK_IN_SPARE_AREA 16 ++#define WR_RD_BSY_GAP 17 ++#define ENABLE_BCH_ECC 27 ++ ++/* NAND_DEV0_ECC_CFG bits */ ++#define ECC_CFG_ECC_DISABLE 0 ++#define ECC_SW_RESET 1 ++#define ECC_MODE 4 ++#define ECC_PARITY_SIZE_BYTES_BCH 8 ++#define ECC_NUM_DATA_BYTES 16 ++#define ECC_FORCE_CLK_OPEN 30 ++ ++/* NAND_DEV_CMD1 bits */ ++#define READ_ADDR 0 ++ ++/* NAND_DEV_CMD_VLD bits */ ++#define READ_START_VLD 0 ++ ++/* NAND_EBI2_ECC_BUF_CFG bits */ ++#define NUM_STEPS 0 ++ ++/* NAND_ERASED_CW_DETECT_CFG bits */ ++#define ERASED_CW_ECC_MASK 1 ++#define AUTO_DETECT_RES 0 ++#define MASK_ECC (1 << ERASED_CW_ECC_MASK) ++#define RESET_ERASED_DET (1 << AUTO_DETECT_RES) ++#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) ++#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) ++#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) ++ ++/* NAND_ERASED_CW_DETECT_STATUS bits */ ++#define PAGE_ALL_ERASED BIT(7) ++#define CODEWORD_ALL_ERASED BIT(6) ++#define PAGE_ERASED BIT(5) ++#define CODEWORD_ERASED BIT(4) ++#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED) ++#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED) ++ ++/* Version Mask */ ++#define NAND_VERSION_MAJOR_MASK 0xf0000000 ++#define NAND_VERSION_MAJOR_SHIFT 28 ++#define NAND_VERSION_MINOR_MASK 0x0fff0000 ++#define NAND_VERSION_MINOR_SHIFT 16 ++ ++/* NAND OP_CMDs */ ++#define PAGE_READ 0x2 ++#define PAGE_READ_WITH_ECC 0x3 ++#define PAGE_READ_WITH_ECC_SPARE 0x4 ++#define PROGRAM_PAGE 0x6 ++#define PAGE_PROGRAM_WITH_ECC 0x7 ++#define PROGRAM_PAGE_SPARE 0x9 ++#define BLOCK_ERASE 0xa ++#define FETCH_ID 0xb ++#define RESET_DEVICE 0xd ++ ++/* ++ * the NAND controller performs reads/writes with ECC in 516 byte chunks. ++ * the driver calls the chunks 'step' or 'codeword' interchangeably ++ */ ++#define NANDC_STEP_SIZE 512 ++ ++/* ++ * the largest page size we support is 8K, this will have 16 steps/codewords ++ * of 512 bytes each ++ */ ++#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE) ++ ++/* we read at most 3 registers per codeword scan */ ++#define MAX_REG_RD (3 * MAX_NUM_STEPS) ++ ++/* ECC modes */ ++#define ECC_NONE BIT(0) ++#define ECC_RS_4BIT BIT(1) ++#define ECC_BCH_4BIT BIT(2) ++#define ECC_BCH_8BIT BIT(3) ++ ++struct desc_info { ++ struct list_head list; ++ ++ enum dma_transfer_direction dir; ++ struct scatterlist sgl; ++ struct dma_async_tx_descriptor *dma_desc; ++}; ++ ++/* ++ * holds the current register values that we want to write. acts as a contiguous ++ * chunk of memory which we use to write the controller registers through DMA. ++ */ ++struct nandc_regs { ++ u32 cmd; ++ u32 addr0; ++ u32 addr1; ++ u32 chip_sel; ++ u32 exec; ++ ++ u32 cfg0; ++ u32 cfg1; ++ u32 ecc_bch_cfg; ++ ++ u32 clrflashstatus; ++ u32 clrreadstatus; ++ ++ u32 cmd1; ++ u32 vld; ++ ++ u32 orig_cmd1; ++ u32 orig_vld; ++ ++ u32 ecc_buf_cfg; ++}; ++ ++/* ++ * @cmd_crci: ADM DMA CRCI for command flow control ++ * @data_crci: ADM DMA CRCI for data flow control ++ * @list: DMA descriptor list (list of desc_infos) ++ * @dma_done: completion param to denote end of last ++ * descriptor in the list ++ * @data_buffer: our local DMA buffer for page read/writes, ++ * used when we can't use the buffer provided ++ * by upper layers directly ++ * @buf_size/count/start: markers for chip->read_buf/write_buf functions ++ * @reg_read_buf: buffer for reading register data via DMA ++ * @reg_read_pos: marker for data read in reg_read_buf ++ * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for ++ * ecc/non-ecc mode for the current nand flash ++ * device ++ * @regs: a contiguous chunk of memory for DMA register ++ * writes ++ * @ecc_strength: 4 bit or 8 bit ecc, received via DT ++ * @bus_width: 8 bit or 16 bit NAND bus width, received via DT ++ * @ecc_modes: supported ECC modes by the current controller, ++ * initialized via DT match data ++ * @cw_size: the number of bytes in a single step/codeword ++ * of a page, consisting of all data, ecc, spare ++ * and reserved bytes ++ * @cw_data: the number of bytes within a codeword protected ++ * by ECC ++ * @bch_enabled: flag to tell whether BCH or RS ECC mode is used ++ * @status: value to be returned if NAND_CMD_STATUS command ++ * is executed ++ */ ++struct qcom_nandc_data { ++ struct platform_device *pdev; ++ struct device *dev; ++ ++ void __iomem *base; ++ struct resource *res; ++ ++ struct clk *core_clk; ++ struct clk *aon_clk; ++ ++ /* DMA stuff */ ++ struct dma_chan *chan; ++ struct dma_slave_config slave_conf; ++ unsigned int cmd_crci; ++ unsigned int data_crci; ++ struct list_head list; ++ struct completion dma_done; ++ ++ /* MTD stuff */ ++ struct nand_chip chip; ++ struct mtd_info mtd; ++ ++ /* local data buffer and markers */ ++ u8 *data_buffer; ++ int buf_size; ++ int buf_count; ++ int buf_start; ++ ++ /* local buffer to read back registers */ ++ u32 *reg_read_buf; ++ int reg_read_pos; ++ ++ /* required configs */ ++ u32 cfg0, cfg1; ++ u32 cfg0_raw, cfg1_raw; ++ u32 ecc_buf_cfg; ++ u32 ecc_bch_cfg; ++ u32 clrflashstatus; ++ u32 clrreadstatus; ++ u32 sflashc_burst_cfg; ++ u32 cmd1, vld; ++ ++ /* register state */ ++ struct nandc_regs *regs; ++ ++ /* things we get from DT */ ++ int ecc_strength; ++ int bus_width; ++ ++ u32 ecc_modes; ++ ++ /* misc params */ ++ int cw_size; ++ int cw_data; ++ bool use_ecc; ++ bool bch_enabled; ++ u8 status; ++ int last_command; ++}; ++ ++static inline u32 nandc_read(struct qcom_nandc_data *this, int offset) ++{ ++ return ioread32(this->base + offset); ++} ++ ++static inline void nandc_write(struct qcom_nandc_data *this, int offset, ++ u32 val) ++{ ++ iowrite32(val, this->base + offset); ++} ++ ++/* helper to configure address register values */ ++static void set_address(struct qcom_nandc_data *this, u16 column, int page) ++{ ++ struct nand_chip *chip = &this->chip; ++ struct nandc_regs *regs = this->regs; ++ ++ if (chip->options & NAND_BUSWIDTH_16) ++ column >>= 1; ++ ++ regs->addr0 = page << 16 | column; ++ regs->addr1 = page >> 16 & 0xff; ++} ++ ++/* ++ * update_rw_regs: set up read/write register values, these will be ++ * written to the NAND controller registers via DMA ++ * ++ * @num_cw: number of steps for the read/write operation ++ * @read: read or write operation ++ */ ++static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ if (read) { ++ if (this->use_ecc) ++ regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE; ++ else ++ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE; ++ } else { ++ regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE; ++ } ++ ++ if (this->use_ecc) { ++ regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) | ++ (num_cw - 1) << CW_PER_PAGE; ++ ++ regs->cfg1 = this->cfg1; ++ regs->ecc_bch_cfg = this->ecc_bch_cfg; ++ } else { ++ regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) | ++ (num_cw - 1) << CW_PER_PAGE; ++ ++ regs->cfg1 = this->cfg1_raw; ++ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE; ++ } ++ ++ regs->ecc_buf_cfg = this->ecc_buf_cfg; ++ regs->clrflashstatus = this->clrflashstatus; ++ regs->clrreadstatus = this->clrreadstatus; ++ regs->exec = 1; ++} ++ ++static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off, ++ const void *vaddr, int size, bool flow_control) ++{ ++ struct desc_info *desc; ++ struct dma_async_tx_descriptor *dma_desc; ++ struct scatterlist *sgl; ++ struct dma_slave_config slave_conf; ++ int r; ++ ++ desc = kzalloc(sizeof(*desc), GFP_KERNEL); ++ if (!desc) ++ return -ENOMEM; ++ ++ list_add_tail(&desc->list, &this->list); ++ ++ sgl = &desc->sgl; ++ ++ sg_init_one(sgl, vaddr, size); ++ ++ desc->dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; ++ ++ r = dma_map_sg(this->dev, sgl, 1, desc->dir); ++ if (r == 0) { ++ r = -ENOMEM; ++ goto err; ++ } ++ ++ memset(&slave_conf, 0x00, sizeof(slave_conf)); ++ ++ slave_conf.device_fc = flow_control; ++ if (read) { ++ slave_conf.src_maxburst = 16; ++ slave_conf.src_addr = this->res->start + reg_off; ++ slave_conf.slave_id = this->data_crci; ++ } else { ++ slave_conf.dst_maxburst = 16; ++ slave_conf.dst_addr = this->res->start + reg_off; ++ slave_conf.slave_id = this->cmd_crci; ++ } ++ ++ r = dmaengine_slave_config(this->chan, &slave_conf); ++ if (r) { ++ dev_err(this->dev, "failed to configure dma channel\n"); ++ goto err; ++ } ++ ++ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0); ++ if (!dma_desc) { ++ dev_err(this->dev, "failed to prepare desc\n"); ++ r = -EINVAL; ++ goto err; ++ } ++ ++ desc->dma_desc = dma_desc; ++ ++ return 0; ++err: ++ kfree(desc); ++ ++ return r; ++} ++ ++/* ++ * read_reg_dma: prepares a descriptor to read a given number of ++ * contiguous registers to the reg_read_buf pointer ++ * ++ * @first: offset of the first register in the contiguous block ++ * @num_regs: number of registers to read ++ */ ++static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs) ++{ ++ bool flow_control = false; ++ void *vaddr; ++ int size; ++ ++ if (first == NAND_READ_ID || first == NAND_FLASH_STATUS) ++ flow_control = true; ++ ++ size = num_regs * sizeof(u32); ++ vaddr = this->reg_read_buf + this->reg_read_pos; ++ this->reg_read_pos += num_regs; ++ ++ return prep_dma_desc(this, true, first, vaddr, size, flow_control); ++} ++ ++/* ++ * write_reg_dma: prepares a descriptor to write a given number of ++ * contiguous registers ++ * ++ * @first: offset of the first register in the contiguous block ++ * @num_regs: number of registers to write ++ */ ++static int write_reg_dma(struct qcom_nandc_data *this, int first, int num_regs) ++{ ++ bool flow_control = false; ++ struct nandc_regs *regs = this->regs; ++ void *vaddr; ++ int size; ++ ++ switch (first) { ++ case NAND_FLASH_CMD: ++ vaddr = ®s->cmd; ++ flow_control = true; ++ break; ++ case NAND_EXEC_CMD: ++ vaddr = ®s->exec; ++ break; ++ case NAND_FLASH_STATUS: ++ vaddr = ®s->clrflashstatus; ++ break; ++ case NAND_DEV0_CFG0: ++ vaddr = ®s->cfg0; ++ break; ++ case NAND_READ_STATUS: ++ vaddr = ®s->clrreadstatus; ++ break; ++ case NAND_DEV_CMD1: ++ vaddr = ®s->cmd1; ++ break; ++ case NAND_DEV_CMD1_RESTORE: ++ first = NAND_DEV_CMD1; ++ vaddr = ®s->orig_cmd1; ++ break; ++ case NAND_DEV_CMD_VLD: ++ vaddr = ®s->vld; ++ break; ++ case NAND_DEV_CMD_VLD_RESTORE: ++ first = NAND_DEV_CMD_VLD; ++ vaddr = ®s->orig_vld; ++ break; ++ case NAND_EBI2_ECC_BUF_CFG: ++ vaddr = ®s->ecc_buf_cfg; ++ break; ++ default: ++ dev_err(this->dev, "invalid starting register\n"); ++ return -EINVAL; ++ } ++ ++ size = num_regs * sizeof(u32); ++ ++ return prep_dma_desc(this, false, first, vaddr, size, flow_control); ++} ++ ++/* ++ * read_data_dma: prepares a DMA descriptor to transfer data from the ++ * controller's internal buffer to the buffer 'vaddr' ++ * ++ * @reg_off: offset within the controller's data buffer ++ * @vaddr: virtual address of the buffer we want to write to ++ * @size: DMA transaction size in bytes ++ */ ++static int read_data_dma(struct qcom_nandc_data *this, int reg_off, ++ const u8 *vaddr, int size) ++{ ++ return prep_dma_desc(this, true, reg_off, vaddr, size, false); ++} ++ ++/* ++ * write_data_dma: prepares a DMA descriptor to transfer data from ++ * 'vaddr' to the controller's internal buffer ++ * ++ * @reg_off: offset within the controller's data buffer ++ * @vaddr: virtual address of the buffer we want to read from ++ * @size: DMA transaction size in bytes ++ */ ++static int write_data_dma(struct qcom_nandc_data *this, int reg_off, ++ const u8 *vaddr, int size) ++{ ++ return prep_dma_desc(this, false, reg_off, vaddr, size, false); ++} ++ ++/* ++ * helper to prepare dma descriptors to configure registers needed for reading a ++ * codeword/step in a page ++ */ ++static void config_cw_read(struct qcom_nandc_data *this) ++{ ++ write_reg_dma(this, NAND_FLASH_CMD, 3); ++ write_reg_dma(this, NAND_DEV0_CFG0, 3); ++ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1); ++ ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_FLASH_STATUS, 2); ++ read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1); ++} ++ ++/* ++ * helpers to prepare dma descriptors used to configure registers needed for ++ * writing a codeword/step in a page ++ */ ++static void config_cw_write_pre(struct qcom_nandc_data *this) ++{ ++ write_reg_dma(this, NAND_FLASH_CMD, 3); ++ write_reg_dma(this, NAND_DEV0_CFG0, 3); ++ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1); ++} ++ ++static void config_cw_write_post(struct qcom_nandc_data *this) ++{ ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_FLASH_STATUS, 1); ++ ++ write_reg_dma(this, NAND_FLASH_STATUS, 1); ++ write_reg_dma(this, NAND_READ_STATUS, 1); ++} ++ ++/* ++ * the following functions are used within chip->cmdfunc() to perform different ++ * NAND_CMD_* commands ++ */ ++ ++/* sets up descriptors for NAND_CMD_PARAM */ ++static int nandc_param(struct qcom_nandc_data *this) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ /* ++ * NAND_CMD_PARAM is called before we know much about the FLASH chip ++ * in use. we configure the controller to perform a raw read of 512 ++ * bytes to read onfi params ++ */ ++ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE; ++ regs->addr0 = 0; ++ regs->addr1 = 0; ++ regs->cfg0 = 0 << CW_PER_PAGE ++ | 512 << UD_SIZE_BYTES ++ | 5 << NUM_ADDR_CYCLES ++ | 0 << SPARE_SIZE_BYTES; ++ ++ regs->cfg1 = 7 << NAND_RECOVERY_CYCLES ++ | 0 << CS_ACTIVE_BSY ++ | 17 << BAD_BLOCK_BYTE_NUM ++ | 1 << BAD_BLOCK_IN_SPARE_AREA ++ | 2 << WR_RD_BSY_GAP ++ | 0 << WIDE_FLASH ++ | 1 << DEV0_CFG1_ECC_DISABLE; ++ ++ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE; ++ ++ /* configure CMD1 and VLD for ONFI param probing */ ++ regs->vld = (this->vld & ~(1 << READ_START_VLD)) ++ | 0 << READ_START_VLD; ++ ++ regs->cmd1 = (this->cmd1 & ~(0xFF << READ_ADDR)) ++ | NAND_CMD_PARAM << READ_ADDR; ++ ++ regs->exec = 1; ++ ++ regs->orig_cmd1 = this->cmd1; ++ regs->orig_vld = this->vld; ++ ++ write_reg_dma(this, NAND_DEV_CMD_VLD, 1); ++ write_reg_dma(this, NAND_DEV_CMD1, 1); ++ ++ this->buf_count = 512; ++ memset(this->data_buffer, 0xff, this->buf_count); ++ ++ config_cw_read(this); ++ ++ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->buf_count); ++ ++ /* restore CMD1 and VLD regs */ ++ write_reg_dma(this, NAND_DEV_CMD1_RESTORE, 1); ++ write_reg_dma(this, NAND_DEV_CMD_VLD_RESTORE, 1); ++ ++ return 0; ++} ++ ++/* sets up descriptors for NAND_CMD_ERASE1 */ ++static int erase_block(struct qcom_nandc_data *this, int page_addr) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ regs->cmd = BLOCK_ERASE | PAGE_ACC | LAST_PAGE; ++ regs->addr0 = page_addr; ++ regs->addr1 = 0; ++ regs->cfg0 = this->cfg0_raw & ~(7 << CW_PER_PAGE); ++ regs->cfg1 = this->cfg1_raw; ++ regs->exec = 1; ++ regs->clrflashstatus = this->clrflashstatus; ++ regs->clrreadstatus = this->clrreadstatus; ++ ++ write_reg_dma(this, NAND_FLASH_CMD, 3); ++ write_reg_dma(this, NAND_DEV0_CFG0, 2); ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_FLASH_STATUS, 1); ++ ++ write_reg_dma(this, NAND_FLASH_STATUS, 1); ++ write_reg_dma(this, NAND_READ_STATUS, 1); ++ ++ return 0; ++} ++ ++/* sets up descriptors for NAND_CMD_READID */ ++static int read_id(struct qcom_nandc_data *this, int column) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ if (column == -1) ++ return 0; ++ ++ regs->cmd = FETCH_ID; ++ regs->addr0 = column; ++ regs->addr1 = 0; ++ regs->chip_sel = DM_EN; ++ regs->exec = 1; ++ ++ write_reg_dma(this, NAND_FLASH_CMD, 4); ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_READ_ID, 1); ++ ++ return 0; ++} ++ ++/* sets up descriptors for NAND_CMD_RESET */ ++static int reset(struct qcom_nandc_data *this) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ regs->cmd = RESET_DEVICE; ++ regs->exec = 1; ++ ++ write_reg_dma(this, NAND_FLASH_CMD, 1); ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_FLASH_STATUS, 1); ++ ++ return 0; ++} ++ ++/* helpers to submit/free our list of dma descriptors */ ++static void dma_callback(void *param) ++{ ++ struct qcom_nandc_data *this = param; ++ struct completion *c = &this->dma_done; ++ ++ complete(c); ++} ++ ++static int submit_descs(struct qcom_nandc_data *this) ++{ ++ struct completion *c = &this->dma_done; ++ struct desc_info *desc; ++ int r; ++ ++ init_completion(c); ++ ++ list_for_each_entry(desc, &this->list, list) { ++ /* ++ * we add a callback to the last descriptor in our list to ++ * notify completion of command ++ */ ++ if (list_is_last(&desc->list, &this->list)) { ++ desc->dma_desc->callback = dma_callback; ++ desc->dma_desc->callback_param = this; ++ } ++ ++ dmaengine_submit(desc->dma_desc); ++ } ++ ++ dma_async_issue_pending(this->chan); ++ ++ r = wait_for_completion_timeout(c, msecs_to_jiffies(500)); ++ if (!r) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++ ++static void free_descs(struct qcom_nandc_data *this) ++{ ++ struct desc_info *desc, *n; ++ ++ list_for_each_entry_safe(desc, n, &this->list, list) { ++ list_del(&desc->list); ++ dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir); ++ kfree(desc); ++ } ++} ++ ++/* reset the register read buffer for next NAND operation */ ++static void clear_read_regs(struct qcom_nandc_data *this) ++{ ++ this->reg_read_pos = 0; ++ memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(*this->reg_read_buf)); ++} ++ ++static void pre_command(struct qcom_nandc_data *this, int command) ++{ ++ this->buf_count = 0; ++ this->buf_start = 0; ++ this->use_ecc = false; ++ this->last_command = command; ++ ++ clear_read_regs(this); ++} ++ ++/* ++ * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our ++ * privately maintained status byte, this status byte can be read after ++ * NAND_CMD_STATUS is called ++ */ ++static void parse_erase_write_errors(struct qcom_nandc_data *this, int command) ++{ ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int num_cw; ++ int i; ++ ++ num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1; ++ ++ for (i = 0; i < num_cw; i++) { ++ __le32 flash_status = le32_to_cpu(this->reg_read_buf[i]); ++ ++ if (flash_status & FS_MPU_ERR) ++ this->status &= ~NAND_STATUS_WP; ++ ++ if (flash_status & FS_OP_ERR || (i == (num_cw - 1) && ++ (flash_status & FS_DEVICE_STS_ERR))) ++ this->status |= NAND_STATUS_FAIL; ++ } ++} ++ ++static void post_command(struct qcom_nandc_data *this, int command) ++{ ++ switch (command) { ++ case NAND_CMD_READID: ++ memcpy(this->data_buffer, this->reg_read_buf, this->buf_count); ++ break; ++ case NAND_CMD_PAGEPROG: ++ case NAND_CMD_ERASE1: ++ parse_erase_write_errors(this, command); ++ break; ++ default: ++ break; ++ } ++} ++ ++/* ++ * Implements chip->cmdfunc. It's only used for a limited set of commands. ++ * The rest of the commands wouldn't be called by upper layers. For example, ++ * NAND_CMD_READOOB would never be called because we have our own versions ++ * of read_oob ops for nand_ecc_ctrl. ++ */ ++static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command, ++ int column, int page_addr) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ struct qcom_nandc_data *this = chip->priv; ++ bool wait = false; ++ int r = 0; ++ ++ pre_command(this, command); ++ ++ switch (command) { ++ case NAND_CMD_RESET: ++ r = reset(this); ++ wait = true; ++ break; ++ ++ case NAND_CMD_READID: ++ this->buf_count = 4; ++ r = read_id(this, column); ++ wait = true; ++ break; ++ ++ case NAND_CMD_PARAM: ++ r = nandc_param(this); ++ wait = true; ++ break; ++ ++ case NAND_CMD_ERASE1: ++ r = erase_block(this, page_addr); ++ wait = true; ++ break; ++ ++ case NAND_CMD_READ0: ++ /* we read the entire page for now */ ++ WARN_ON(column != 0); ++ ++ this->use_ecc = true; ++ set_address(this, 0, page_addr); ++ update_rw_regs(this, ecc->steps, true); ++ break; ++ ++ case NAND_CMD_SEQIN: ++ WARN_ON(column != 0); ++ set_address(this, 0, page_addr); ++ break; ++ ++ case NAND_CMD_PAGEPROG: ++ case NAND_CMD_STATUS: ++ case NAND_CMD_NONE: ++ default: ++ break; ++ } ++ ++ if (r) { ++ dev_err(this->dev, "failure executing command %d\n", ++ command); ++ free_descs(this); ++ return; ++ } ++ ++ if (wait) { ++ r = submit_descs(this); ++ if (r) ++ dev_err(this->dev, ++ "failure submitting descs for command %d\n", ++ command); ++ } ++ ++ free_descs(this); ++ ++ post_command(this, command); ++} ++ ++/* ++ * when using RS ECC, the NAND controller flags an error when reading an ++ * erased page. however, there are special characters at certain offsets when ++ * we read the erased page. we check here if the page is really empty. if so, ++ * we replace the magic characters with 0xffs ++ */ ++static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int cwperpage = ecc->steps; ++ u8 orig1[MAX_NUM_STEPS], orig2[MAX_NUM_STEPS]; ++ int i, j; ++ ++ /* if BCH is enabled, HW will take care of detecting erased pages */ ++ if (this->bch_enabled || !this->use_ecc) ++ return false; ++ ++ for (i = 0; i < cwperpage; i++) { ++ u8 *empty1, *empty2; ++ __le32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]); ++ ++ /* ++ * an erased page flags an error in NAND_FLASH_STATUS, check if ++ * the page is erased by looking for 0x54s at offsets 3 and 175 ++ * from the beginning of each codeword ++ */ ++ if (!(flash_status & FS_OP_ERR)) ++ break; ++ ++ empty1 = &data_buf[3 + i * this->cw_data]; ++ empty2 = &data_buf[175 + i * this->cw_data]; ++ ++ /* ++ * if the error wasn't because of an erased page, bail out and ++ * and let someone else do the error checking ++ */ ++ if ((*empty1 == 0x54 && *empty2 == 0xff) || ++ (*empty1 == 0xff && *empty2 == 0x54)) { ++ orig1[i] = *empty1; ++ orig2[i] = *empty2; ++ ++ *empty1 = 0xff; ++ *empty2 = 0xff; ++ } else { ++ break; ++ } ++ } ++ ++ if (i < cwperpage || memchr_inv(data_buf, 0xff, mtd->writesize)) ++ goto not_empty; ++ ++ /* ++ * tell the caller that the page was empty and is fixed up, so that ++ * parse_read_errors() doesn't think it's an error ++ */ ++ return true; ++ ++not_empty: ++ /* restore original values if not empty*/ ++ for (j = 0; j < i; j++) { ++ data_buf[3 + j * this->cw_data] = orig1[j]; ++ data_buf[175 + j * this->cw_data] = orig2[j]; ++ } ++ ++ return false; ++} ++ ++struct read_stats { ++ __le32 flash; ++ __le32 buffer; ++ __le32 erased_cw; ++}; ++ ++/* ++ * reads back status registers set by the controller to notify page read ++ * errors. this is equivalent to what 'ecc->correct()' would do. ++ */ ++static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int cwperpage = ecc->steps; ++ unsigned int max_bitflips = 0; ++ int i; ++ ++ for (i = 0; i < cwperpage; i++) { ++ int stat; ++ struct read_stats *buf; ++ ++ buf = (struct read_stats *) (this->reg_read_buf + 3 * i); ++ ++ buf->flash = le32_to_cpu(buf->flash); ++ buf->buffer = le32_to_cpu(buf->buffer); ++ buf->erased_cw = le32_to_cpu(buf->erased_cw); ++ ++ if (buf->flash & (FS_OP_ERR | FS_MPU_ERR)) { ++ ++ /* ignore erased codeword errors */ ++ if (this->bch_enabled) { ++ if ((buf->erased_cw & ERASED_CW) == ERASED_CW) ++ continue; ++ } else if (erased_page) { ++ continue; ++ } ++ ++ if (buf->buffer & BS_UNCORRECTABLE_BIT) { ++ mtd->ecc_stats.failed++; ++ continue; ++ } ++ } ++ ++ stat = buf->buffer & BS_CORRECTABLE_ERR_MSK; ++ mtd->ecc_stats.corrected += stat; ++ ++ max_bitflips = max_t(unsigned int, max_bitflips, stat); ++ } ++ ++ return max_bitflips; ++} ++ ++/* ++ * helper to perform the actual page read operation, used by ecc->read_page() ++ * and ecc->read_oob() ++ */ ++static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf, ++ u8 *oob_buf) ++{ ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int i, r; ++ ++ /* queue cmd descs for each codeword */ ++ for (i = 0; i < ecc->steps; i++) { ++ int data_size, oob_size; ++ ++ if (i == (ecc->steps - 1)) { ++ data_size = ecc->size - ((ecc->steps - 1) << 2); ++ oob_size = (ecc->steps << 2) + ecc->bytes; ++ } else { ++ data_size = this->cw_data; ++ oob_size = ecc->bytes; ++ } ++ ++ config_cw_read(this); ++ ++ if (data_buf) ++ read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size); ++ ++ if (oob_buf) ++ read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf, ++ oob_size); ++ ++ if (data_buf) ++ data_buf += data_size; ++ if (oob_buf) ++ oob_buf += oob_size; ++ } ++ ++ r = submit_descs(this); ++ if (r) ++ dev_err(this->dev, "failure to read page/oob\n"); ++ ++ free_descs(this); ++ ++ return r; ++} ++ ++/* ++ * a helper that copies the last step/codeword of a page (containing free oob) ++ * into our local buffer ++ */ ++static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page) ++{ ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int size; ++ int r; ++ ++ clear_read_regs(this); ++ ++ size = use_ecc ? this->cw_data : this->cw_size; ++ ++ /* prepare a clean read buffer */ ++ memset(this->data_buffer, 0xff, size); ++ ++ this->use_ecc = use_ecc; ++ set_address(this, this->cw_size * (ecc->steps - 1), page); ++ update_rw_regs(this, 1, true); ++ ++ config_cw_read(this); ++ ++ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size); ++ ++ r = submit_descs(this); ++ if (r) ++ dev_err(this->dev, "failed to copy last codeword\n"); ++ ++ free_descs(this); ++ ++ return r; ++} ++ ++/* implements ecc->read_page() */ ++static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf, int oob_required, int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ u8 *data_buf, *oob_buf = NULL; ++ bool erased_page; ++ int r; ++ ++ data_buf = buf; ++ oob_buf = oob_required ? chip->oob_poi : NULL; ++ ++ r = read_page_low(this, data_buf, oob_buf); ++ if (r) { ++ dev_err(this->dev, "failure to read page\n"); ++ return r; ++ } ++ ++ erased_page = empty_page_fixup(this, data_buf); ++ ++ return parse_read_errors(this, erased_page); ++} ++ ++/* implements ecc->read_oob() */ ++static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int r; ++ ++ clear_read_regs(this); ++ ++ this->use_ecc = true; ++ set_address(this, 0, page); ++ update_rw_regs(this, ecc->steps, true); ++ ++ r = read_page_low(this, NULL, chip->oob_poi); ++ if (r) ++ dev_err(this->dev, "failure to read oob\n"); ++ ++ return r; ++} ++ ++/* implements ecc->read_oob_raw(), used to read the bad block marker flag */ ++static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ uint8_t *oob = chip->oob_poi; ++ int start, length; ++ int r; ++ ++ /* ++ * configure registers for a raw page read, the address is set to the ++ * beginning of the last codeword, we don't care about reading ecc ++ * portion of oob, just the free stuff ++ */ ++ r = copy_last_cw(this, false, page); ++ if (r) ++ return r; ++ ++ /* ++ * reading raw oob has 2 parts, first the bad block byte, then the ++ * actual free oob region. perform a memcpy in two steps ++ */ ++ start = mtd->writesize - (this->cw_size * (ecc->steps - 1)); ++ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1; ++ ++ memcpy(oob, this->data_buffer + start, length); ++ ++ oob += length; ++ ++ start = this->cw_data - (ecc->steps << 2) + 1; ++ length = ecc->steps << 2; ++ ++ memcpy(oob, this->data_buffer + start, length); ++ ++ return 0; ++} ++ ++/* implements ecc->write_page() */ ++static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf, int oob_required) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ u8 *data_buf, *oob_buf; ++ int i, r = 0; ++ ++ clear_read_regs(this); ++ ++ data_buf = (u8 *) buf; ++ oob_buf = chip->oob_poi; ++ ++ this->use_ecc = true; ++ update_rw_regs(this, ecc->steps, false); ++ ++ for (i = 0; i < ecc->steps; i++) { ++ int data_size, oob_size; ++ ++ if (i == (ecc->steps - 1)) { ++ data_size = ecc->size - ((ecc->steps - 1) << 2); ++ oob_size = (ecc->steps << 2) + ecc->bytes; ++ } else { ++ data_size = this->cw_data; ++ oob_size = ecc->bytes; ++ } ++ ++ config_cw_write_pre(this); ++ write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size); ++ ++ /* ++ * we don't really need to write anything to oob for the ++ * first n - 1 codewords since these oob regions just ++ * contain ecc that's written by the controller itself ++ */ ++ if (i == (ecc->steps - 1)) ++ write_data_dma(this, FLASH_BUF_ACC + data_size, ++ oob_buf, oob_size); ++ config_cw_write_post(this); ++ ++ data_buf += data_size; ++ oob_buf += oob_size; ++ } ++ ++ r = submit_descs(this); ++ if (r) ++ dev_err(this->dev, "failure to write page\n"); ++ ++ free_descs(this); ++ ++ return r; ++} ++ ++/* ++ * implements ecc->write_oob() ++ * ++ * the NAND controller cannot write only data or only oob within a codeword, ++ * since ecc is calculated for the combined codeword. we first copy the ++ * entire contents for the last codeword(data + oob), replace the old oob ++ * with the new one in chip->oob_poi, and then write the entire codeword. ++ * this read-copy-write operation results in a slight perormance loss. ++ */ ++static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ uint8_t *oob = chip->oob_poi; ++ int free_boff; ++ int data_size, oob_size; ++ int r, status = 0; ++ ++ r = copy_last_cw(this, true, page); ++ if (r) ++ return r; ++ ++ clear_read_regs(this); ++ ++ /* calculate the data and oob size for the last codeword/step */ ++ data_size = ecc->size - ((ecc->steps - 1) << 2); ++ oob_size = (ecc->steps << 2) + ecc->bytes; ++ ++ /* ++ * the location of spare data in the oob buffer, we could also use ++ * ecc->layout.oobfree here ++ */ ++ free_boff = ecc->bytes * (ecc->steps - 1); ++ ++ /* override new oob content to last codeword */ ++ memcpy(this->data_buffer + data_size, oob + free_boff, oob_size); ++ ++ this->use_ecc = true; ++ set_address(this, this->cw_size * (ecc->steps - 1), page); ++ update_rw_regs(this, 1, false); ++ ++ config_cw_write_pre(this); ++ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, ++ data_size + oob_size); ++ config_cw_write_post(this); ++ ++ r = submit_descs(this); ++ ++ free_descs(this); ++ ++ if (r) { ++ dev_err(this->dev, "failure to write oob\n"); ++ return -EIO; ++ } ++ ++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); ++ ++ status = chip->waitfunc(mtd, chip); ++ ++ return status & NAND_STATUS_FAIL ? -EIO : 0; ++} ++ ++/* implements ecc->write_oob_raw(), used to write bad block marker flag */ ++static int qcom_nandc_write_oob_raw(struct mtd_info *mtd, ++ struct nand_chip *chip, int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ uint8_t *oob = chip->oob_poi; ++ int start, length; ++ int r, status = 0; ++ ++ r = copy_last_cw(this, false, page); ++ if (r) ++ return r; ++ ++ clear_read_regs(this); ++ ++ /* ++ * writing raw oob has 2 parts, first the bad block region, then the ++ * actual free region ++ */ ++ start = mtd->writesize - (this->cw_size * (ecc->steps - 1)); ++ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1; ++ ++ memcpy(this->data_buffer + start, oob, length); ++ ++ oob += length; ++ ++ start = this->cw_data - (ecc->steps << 2) + 1; ++ length = ecc->steps << 2; ++ ++ memcpy(this->data_buffer + start, oob, length); ++ ++ /* prepare write */ ++ this->use_ecc = false; ++ set_address(this, this->cw_size * (ecc->steps - 1), page); ++ update_rw_regs(this, 1, false); ++ ++ config_cw_write_pre(this); ++ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size); ++ config_cw_write_post(this); ++ ++ r = submit_descs(this); ++ ++ free_descs(this); ++ ++ if (r) { ++ dev_err(this->dev, "failure to write updated oob\n"); ++ return -EIO; ++ } ++ ++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); ++ ++ status = chip->waitfunc(mtd, chip); ++ ++ return status & NAND_STATUS_FAIL ? -EIO : 0; ++} ++ ++/* ++ * the three functions below implement chip->read_byte(), chip->read_buf() ++ * and chip->write_buf() respectively. these aren't used for ++ * reading/writing page data, they are used for smaller data like reading ++ * id, status etc ++ */ ++static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct qcom_nandc_data *this = chip->priv; ++ uint8_t *buf = this->data_buffer; ++ uint8_t ret = 0x0; ++ ++ if (this->last_command == NAND_CMD_STATUS) { ++ ret = this->status; ++ ++ this->status = NAND_STATUS_READY | NAND_STATUS_WP; ++ ++ return ret; ++ } ++ ++ if (this->buf_start < this->buf_count) ++ ret = buf[this->buf_start++]; ++ ++ return ret; ++} ++ ++static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct qcom_nandc_data *this = chip->priv; ++ int real_len = min_t(size_t, len, this->buf_count - this->buf_start); ++ ++ memcpy(buf, this->data_buffer + this->buf_start, real_len); ++ this->buf_start += real_len; ++} ++ ++static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf, ++ int len) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct qcom_nandc_data *this = chip->priv; ++ int real_len = min_t(size_t, len, this->buf_count - this->buf_start); ++ ++ memcpy(this->data_buffer + this->buf_start, buf, real_len); ++ ++ this->buf_start += real_len; ++} ++ ++/* we support only one external chip for now */ ++static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct qcom_nandc_data *this = chip->priv; ++ ++ if (chipnr <= 0) ++ return; ++ ++ dev_warn(this->dev, "invalid chip select\n"); ++} ++ ++/* ++ * NAND controller page layout info ++ * ++ * |-----------------------| |---------------------------------| ++ * | xx.......xx| | *********xx.......xx| ++ * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx| ++ * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx| ++ * | xx.......xx| | *********xx.......xx| ++ * |-----------------------| |---------------------------------| ++ * codeword 1,2..n-1 codeword n ++ * <---(528/532 Bytes)----> <-------(528/532 Bytes)----------> ++ * ++ * n = number of codewords in the page ++ * . = ECC bytes ++ * * = spare bytes ++ * x = unused/reserved bytes ++ * ++ * 2K page: n = 4, spare = 16 bytes ++ * 4K page: n = 8, spare = 32 bytes ++ * 8K page: n = 16, spare = 64 bytes ++ * ++ * the qcom nand controller operates at a sub page/codeword level. each ++ * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively. ++ * the number of ECC bytes vary based on the ECC strength and the bus width. ++ * ++ * the first n - 1 codewords contains 516 bytes of user data, the remaining ++ * 12/16 bytes consist of ECC and reserved data. The nth codeword contains ++ * both user data and spare(oobavail) bytes that sum up to 516 bytes. ++ * ++ * the layout described above is used by the controller when the ECC block is ++ * enabled. When we read a page with ECC enabled, the unused/reserved bytes are ++ * skipped and not copied to our internal buffer. therefore, the nand_ecclayout ++ * layouts defined below doesn't consider the positions occupied by the reserved ++ * bytes ++ * ++ * when the ECC block is disabled, one unused byte (or two for 16 bit bus width) ++ * in the last codeword is the position of bad block marker. the bad block ++ * marker cannot be accessed when ECC is enabled. ++ * ++ */ ++ ++/* ++ * Layouts for different page sizes and ecc modes. We skip the eccpos field ++ * since it isn't needed for this driver ++ */ ++ ++/* 2K page, 4 bit ECC */ ++static struct nand_ecclayout layout_oob_64 = { ++ .eccbytes = 40, ++ .oobfree = { ++ { 30, 16 }, ++ }, ++}; ++ ++/* 4K page, 4 bit ECC, 8/16 bit bus width */ ++static struct nand_ecclayout layout_oob_128 = { ++ .eccbytes = 80, ++ .oobfree = { ++ { 70, 32 }, ++ }, ++}; ++ ++/* 4K page, 8 bit ECC, 8 bit bus width */ ++static struct nand_ecclayout layout_oob_224_x8 = { ++ .eccbytes = 104, ++ .oobfree = { ++ { 91, 32 }, ++ }, ++}; ++ ++/* 4K page, 8 bit ECC, 16 bit bus width */ ++static struct nand_ecclayout layout_oob_224_x16 = { ++ .eccbytes = 112, ++ .oobfree = { ++ { 98, 32 }, ++ }, ++}; ++ ++/* 8K page, 4 bit ECC, 8/16 bit bus width */ ++static struct nand_ecclayout layout_oob_256 = { ++ .eccbytes = 160, ++ .oobfree = { ++ { 151, 64 }, ++ }, ++}; ++ ++/* ++ * this is called before scan_ident, we do some minimal configurations so ++ * that reading ID and ONFI params work ++ */ ++static void qcom_nandc_pre_init(struct qcom_nandc_data *this) ++{ ++ /* kill onenand */ ++ nandc_write(this, SFLASHC_BURST_CFG, 0); ++ ++ /* enable ADM DMA */ ++ nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN); ++ ++ /* save the original values of these registers */ ++ this->cmd1 = nandc_read(this, NAND_DEV_CMD1); ++ this->vld = nandc_read(this, NAND_DEV_CMD_VLD); ++ ++ /* initial status value */ ++ this->status = NAND_STATUS_READY | NAND_STATUS_WP; ++} ++ ++static int qcom_nandc_ecc_init(struct qcom_nandc_data *this) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int cwperpage; ++ bool wide_bus; ++ ++ /* the nand controller fetches codewords/chunks of 512 bytes */ ++ cwperpage = mtd->writesize >> 9; ++ ++ ecc->strength = this->ecc_strength; ++ ++ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; ++ ++ if (ecc->strength >= 8) { ++ /* 8 bit ECC defaults to BCH ECC on all platforms */ ++ ecc->bytes = wide_bus ? 14 : 13; ++ } else { ++ /* ++ * if the controller supports BCH for 4 bit ECC, the controller ++ * uses lesser bytes for ECC. If RS is used, the ECC bytes is ++ * always 10 bytes ++ */ ++ if (this->ecc_modes & ECC_BCH_4BIT) ++ ecc->bytes = wide_bus ? 8 : 7; ++ else ++ ecc->bytes = 10; ++ } ++ ++ /* each step consists of 512 bytes of data */ ++ ecc->size = NANDC_STEP_SIZE; ++ ++ ecc->read_page = qcom_nandc_read_page; ++ ecc->read_oob = qcom_nandc_read_oob; ++ ecc->write_page = qcom_nandc_write_page; ++ ecc->write_oob = qcom_nandc_write_oob; ++ ++ /* ++ * the bad block marker is readable only when we read the page with ECC ++ * disabled. all the ops above run with ECC enabled. We need raw read ++ * and write function for oob in order to access bad block marker. ++ */ ++ ecc->read_oob_raw = qcom_nandc_read_oob_raw; ++ ecc->write_oob_raw = qcom_nandc_write_oob_raw; ++ ++ switch (mtd->oobsize) { ++ case 64: ++ ecc->layout = &layout_oob_64; ++ break; ++ case 128: ++ ecc->layout = &layout_oob_128; ++ break; ++ case 224: ++ if (wide_bus) ++ ecc->layout = &layout_oob_224_x16; ++ else ++ ecc->layout = &layout_oob_224_x8; ++ break; ++ case 256: ++ ecc->layout = &layout_oob_256; ++ break; ++ default: ++ dev_err(this->dev, "unsupported NAND device, oobsize %d\n", ++ mtd->oobsize); ++ return -ENODEV; ++ } ++ ++ ecc->mode = NAND_ECC_HW; ++ ++ /* enable ecc by default */ ++ this->use_ecc = true; ++ ++ return 0; ++} ++ ++static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int cwperpage = mtd->writesize / ecc->size; ++ int spare_bytes, bad_block_byte; ++ bool wide_bus; ++ int ecc_mode = 0; ++ ++ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; ++ ++ if (ecc->strength >= 8) { ++ this->cw_size = 532; ++ ++ spare_bytes = wide_bus ? 0 : 2; ++ ++ this->bch_enabled = true; ++ ecc_mode = 1; ++ } else { ++ this->cw_size = 528; ++ ++ if (this->ecc_modes & ECC_BCH_4BIT) { ++ spare_bytes = wide_bus ? 2 : 4; ++ ++ this->bch_enabled = true; ++ ecc_mode = 0; ++ } else { ++ spare_bytes = wide_bus ? 0 : 1; ++ } ++ } ++ ++ /* ++ * DATA_UD_BYTES varies based on whether the read/write command protects ++ * spare data with ECC too. We protect spare data by default, so we set ++ * it to main + spare data, which are 512 and 4 bytes respectively. ++ */ ++ this->cw_data = 516; ++ ++ bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1; ++ ++ this->cfg0 = (cwperpage - 1) << CW_PER_PAGE ++ | this->cw_data << UD_SIZE_BYTES ++ | 0 << DISABLE_STATUS_AFTER_WRITE ++ | 5 << NUM_ADDR_CYCLES ++ | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS ++ | 0 << STATUS_BFR_READ ++ | 1 << SET_RD_MODE_AFTER_STATUS ++ | spare_bytes << SPARE_SIZE_BYTES; ++ ++ this->cfg1 = 7 << NAND_RECOVERY_CYCLES ++ | 0 << CS_ACTIVE_BSY ++ | bad_block_byte << BAD_BLOCK_BYTE_NUM ++ | 0 << BAD_BLOCK_IN_SPARE_AREA ++ | 2 << WR_RD_BSY_GAP ++ | wide_bus << WIDE_FLASH ++ | this->bch_enabled << ENABLE_BCH_ECC; ++ ++ this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE ++ | this->cw_size << UD_SIZE_BYTES ++ | 5 << NUM_ADDR_CYCLES ++ | 0 << SPARE_SIZE_BYTES; ++ ++ this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES ++ | 0 << CS_ACTIVE_BSY ++ | 17 << BAD_BLOCK_BYTE_NUM ++ | 1 << BAD_BLOCK_IN_SPARE_AREA ++ | 2 << WR_RD_BSY_GAP ++ | wide_bus << WIDE_FLASH ++ | 1 << DEV0_CFG1_ECC_DISABLE; ++ ++ this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE ++ | 0 << ECC_SW_RESET ++ | this->cw_data << ECC_NUM_DATA_BYTES ++ | 1 << ECC_FORCE_CLK_OPEN ++ | ecc_mode << ECC_MODE ++ | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH; ++ ++ this->ecc_buf_cfg = 0x203 << NUM_STEPS; ++ ++ this->clrflashstatus = FS_READY_BSY_N; ++ this->clrreadstatus = 0xc0; ++ ++ dev_dbg(this->dev, ++ "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n", ++ this->cfg0, this->cfg1, this->ecc_buf_cfg, ++ this->ecc_bch_cfg, this->cw_size, this->cw_data, ++ ecc->strength, ecc->bytes, cwperpage); ++} ++ ++static int qcom_nandc_alloc(struct qcom_nandc_data *this) ++{ ++ int r; ++ ++ r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32)); ++ if (r) { ++ dev_err(this->dev, "failed to set DMA mask\n"); ++ return r; ++ } ++ ++ /* ++ * we use the internal buffer for reading ONFI params, reading small ++ * data like ID and status, and preforming read-copy-write operations ++ * when writing to a codeword partially. 532 is the maximum possible ++ * size of a codeword for our nand controller ++ */ ++ this->buf_size = 532; ++ ++ this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL); ++ if (!this->data_buffer) ++ return -ENOMEM; ++ ++ this->regs = devm_kzalloc(this->dev, sizeof(*this->regs), GFP_KERNEL); ++ if (!this->regs) ++ return -ENOMEM; ++ ++ this->reg_read_buf = devm_kzalloc(this->dev, ++ MAX_REG_RD * sizeof(*this->reg_read_buf), ++ GFP_KERNEL); ++ if (!this->reg_read_buf) ++ return -ENOMEM; ++ ++ INIT_LIST_HEAD(&this->list); ++ ++ this->chan = dma_request_slave_channel(this->dev, "rxtx"); ++ if (!this->chan) { ++ dev_err(this->dev, "failed to request slave channel\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static void qcom_nandc_unalloc(struct qcom_nandc_data *this) ++{ ++ dma_release_channel(this->chan); ++} ++ ++static int qcom_nandc_init(struct qcom_nandc_data *this) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct device_node *np = this->dev->of_node; ++ struct mtd_part_parser_data ppdata = { .of_node = np }; ++ int r; ++ ++ mtd->priv = chip; ++ mtd->name = "qcom-nandc"; ++ mtd->owner = THIS_MODULE; ++ ++ chip->priv = this; ++ ++ chip->cmdfunc = qcom_nandc_command; ++ chip->select_chip = qcom_nandc_select_chip; ++ chip->read_byte = qcom_nandc_read_byte; ++ chip->read_buf = qcom_nandc_read_buf; ++ chip->write_buf = qcom_nandc_write_buf; ++ ++ chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER; ++ if (this->bus_width == 16) ++ chip->options |= NAND_BUSWIDTH_16; ++ ++ chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW; ++ if (of_get_nand_on_flash_bbt(np)) ++ chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; ++ ++ qcom_nandc_pre_init(this); ++ ++ r = nand_scan_ident(mtd, 1, NULL); ++ if (r) ++ return r; ++ ++ r = qcom_nandc_ecc_init(this); ++ if (r) ++ return r; ++ ++ qcom_nandc_hw_post_init(this); ++ ++ r = nand_scan_tail(mtd); ++ if (r) ++ return r; ++ ++ return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); ++} ++ ++static int qcom_nandc_parse_dt(struct platform_device *pdev) ++{ ++ struct qcom_nandc_data *this = platform_get_drvdata(pdev); ++ struct device_node *np = this->dev->of_node; ++ int r; ++ ++ this->ecc_strength = of_get_nand_ecc_strength(np); ++ if (this->ecc_strength < 0) { ++ dev_warn(this->dev, ++ "incorrect ecc strength, setting to 4 bits/step\n"); ++ this->ecc_strength = 4; ++ } ++ ++ this->bus_width = of_get_nand_bus_width(np); ++ if (this->bus_width < 0) { ++ dev_warn(this->dev, "incorrect bus width, setting to 8\n"); ++ this->bus_width = 8; ++ } ++ ++ r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci); ++ if (r) { ++ dev_err(this->dev, "command CRCI unspecified\n"); ++ return r; ++ } ++ ++ r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci); ++ if (r) { ++ dev_err(this->dev, "data CRCI unspecified\n"); ++ return r; ++ } ++ ++ return 0; ++} ++ ++static int qcom_nandc_probe(struct platform_device *pdev) ++{ ++ struct qcom_nandc_data *this; ++ const struct of_device_id *match; ++ int r; ++ ++ this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL); ++ if (!this) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, this); ++ ++ this->pdev = pdev; ++ this->dev = &pdev->dev; ++ ++ match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev); ++ if (!match) { ++ dev_err(&pdev->dev, "failed to match device\n"); ++ return -ENODEV; ++ } ++ ++ if (!match->data) { ++ dev_err(&pdev->dev, "failed to get device data\n"); ++ return -ENODEV; ++ } ++ ++ this->ecc_modes = (u32) match->data; ++ ++ this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ this->base = devm_ioremap_resource(&pdev->dev, this->res); ++ if (IS_ERR(this->base)) ++ return PTR_ERR(this->base); ++ ++ this->core_clk = devm_clk_get(&pdev->dev, "core"); ++ if (IS_ERR(this->core_clk)) ++ return PTR_ERR(this->core_clk); ++ ++ this->aon_clk = devm_clk_get(&pdev->dev, "aon"); ++ if (IS_ERR(this->aon_clk)) ++ return PTR_ERR(this->aon_clk); ++ ++ r = qcom_nandc_parse_dt(pdev); ++ if (r) ++ return r; ++ ++ r = qcom_nandc_alloc(this); ++ if (r) ++ return r; ++ ++ r = clk_prepare_enable(this->core_clk); ++ if (r) ++ goto err_core_clk; ++ ++ r = clk_prepare_enable(this->aon_clk); ++ if (r) ++ goto err_aon_clk; ++ ++ r = qcom_nandc_init(this); ++ if (r) ++ goto err_init; ++ ++ return 0; ++ ++err_init: ++ clk_disable_unprepare(this->aon_clk); ++err_aon_clk: ++ clk_disable_unprepare(this->core_clk); ++err_core_clk: ++ qcom_nandc_unalloc(this); ++ ++ return r; ++} ++ ++static int qcom_nandc_remove(struct platform_device *pdev) ++{ ++ struct qcom_nandc_data *this = platform_get_drvdata(pdev); ++ ++ qcom_nandc_unalloc(this); ++ ++ clk_disable_unprepare(this->aon_clk); ++ clk_disable_unprepare(this->core_clk); ++ ++ return 0; ++} ++ ++#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT) ++ ++/* ++ * data will hold a struct pointer containing more differences once we support ++ * more IPs ++ */ ++static const struct of_device_id qcom_nandc_of_match[] = { ++ { .compatible = "qcom,ebi2-nandc", ++ .data = (void *) EBI2_NANDC_ECC_MODES, ++ }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, qcom_nandc_of_match); ++ ++static struct platform_driver qcom_nandc_driver = { ++ .driver = { ++ .name = "qcom-nandc", ++ .of_match_table = qcom_nandc_of_match, ++ }, ++ .probe = qcom_nandc_probe, ++ .remove = qcom_nandc_remove, ++}; ++module_platform_driver(qcom_nandc_driver); ++ ++MODULE_AUTHOR("Archit Taneja "); ++MODULE_DESCRIPTION("Qualcomm NAND Controller driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -50,5 +50,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740 + obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ + obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o + obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ ++obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o + + nand-objs := nand_base.o nand_bbt.o nand_timings.o diff --git a/target/linux/ipq806x/patches-3.18/163-dt-bindings-qcom_nandc-Add-DT-bindings.patch b/target/linux/ipq806x/patches-3.18/163-dt-bindings-qcom_nandc-Add-DT-bindings.patch new file mode 100644 index 0000000..6530eb1 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/163-dt-bindings-qcom_nandc-Add-DT-bindings.patch @@ -0,0 +1,82 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,3/5] dt/bindings: qcom_nandc: Add DT bindings +From: Archit Taneja +X-Patchwork-Id: 6927141 +Message-Id: <1438578498-32254-4-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja , devicetree@vger.kernel.org +Date: Mon, 3 Aug 2015 10:38:16 +0530 + +Add DT bindings document for the Qualcomm NAND controller driver. + +Cc: devicetree@vger.kernel.org + +v3: +- Don't use '0x' when specifying nand controller address space +- Add optional property for on-flash bbt usage + +Acked-by: Andy Gross +Signed-off-by: Archit Taneja + +--- +.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++ + 1 file changed, 49 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +@@ -0,0 +1,49 @@ ++* Qualcomm NAND controller ++ ++Required properties: ++- compatible: should be "qcom,ebi2-nand" for IPQ806x ++- reg: MMIO address range ++- clocks: must contain core clock and always on clock ++- clock-names: must contain "core" for the core clock and "aon" for the ++ always on clock ++- dmas: DMA specifier, consisting of a phandle to the ADM DMA ++ controller node and the channel number to be used for ++ NAND. Refer to dma.txt and qcom_adm.txt for more details ++- dma-names: must be "rxtx" ++- qcom,cmd-crci: must contain the ADM command type CRCI block instance ++ number specified for the NAND controller on the given ++ platform ++- qcom,data-crci: must contain the ADM data type CRCI block instance ++ number specified for the NAND controller on the given ++ platform ++ ++Optional properties: ++- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen ++ as default ++ ++- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8 ++ bits. If not present, 4 is chosen as default ++- nand-on-flash-bbt: Create/use on-flash bad block table ++ ++The device tree may optionally contain sub-nodes describing partitions of the ++address space. See partition.txt for more detail. ++ ++Example: ++ ++nand@1ac00000 { ++ compatible = "qcom,ebi2-nandc"; ++ reg = <0x1ac00000 0x800>; ++ ++ clocks = <&gcc EBI2_CLK>, ++ <&gcc EBI2_AON_CLK>; ++ clock-names = "core", "aon"; ++ ++ dmas = <&adm_dma 3>; ++ dma-names = "rxtx"; ++ qcom,cmd-crci = <15>; ++ qcom,data-crci = <3>; ++ ++ partition@0 { ++ ... ++ }; ++}; diff --git a/target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch b/target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch new file mode 100644 index 0000000..29e1592 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch @@ -0,0 +1,51 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,4/5] arm: qcom: dts: Add NAND controller node for ipq806x +From: Archit Taneja +X-Patchwork-Id: 6927121 +Message-Id: <1438578498-32254-5-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja , devicetree@vger.kernel.org +Date: Mon, 3 Aug 2015 10:38:17 +0530 + +The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding +compatible string. + +Cc: devicetree@vger.kernel.org + +Reviewed-by: Andy Gross +Signed-off-by: Archit Taneja + +--- +arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -682,6 +682,22 @@ + status = "disabled"; + }; + ++ nand@1ac00000 { ++ compatible = "qcom,ebi2-nandc"; ++ reg = <0x1ac00000 0x800>; ++ ++ clocks = <&gcc EBI2_CLK>, ++ <&gcc EBI2_AON_CLK>; ++ clock-names = "core", "aon"; ++ ++ dmas = <&adm_dma 3>; ++ dma-names = "rxtx"; ++ qcom,cmd-crci = <15>; ++ qcom,data-crci = <3>; ++ ++ status = "disabled"; ++ }; ++ + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-3.18/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch b/target/linux/ipq806x/patches-3.18/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch new file mode 100644 index 0000000..d62564c --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch @@ -0,0 +1,79 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform +From: Archit Taneja +X-Patchwork-Id: 6927091 +Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja , devicetree@vger.kernel.org +Date: Mon, 3 Aug 2015 10:38:18 +0530 + +Enable the NAND controller node on the AP148 platform. Provide pinmux +information. + +Cc: devicetree@vger.kernel.org + +Signed-off-by: Archit Taneja + +--- +arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -61,6 +61,31 @@ + bias-none; + }; + }; ++ ++ nand_pins: nand_pins { ++ mux { ++ pins = "gpio34", "gpio35", "gpio36", ++ "gpio37", "gpio38", "gpio39", ++ "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ function = "nand"; ++ drive-strength = <10>; ++ bias-disable; ++ }; ++ ++ pullups { ++ pins = "gpio39"; ++ bias-pull-up; ++ }; ++ ++ hold { ++ pins = "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ bias-bus-hold; ++ }; ++ }; + }; + + gsbi@16300000 { +@@ -147,5 +172,19 @@ + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + }; ++ ++ nand@1ac00000 { ++ status = "ok"; ++ ++ pinctrl-0 = <&nand_pins>; ++ pinctrl-names = "default"; ++ ++ nand-ecc-strength = <4>; ++ nand-bus-width = <8>; ++ }; + }; + }; ++ ++&adm_dma { ++ status = "ok"; ++}; diff --git a/target/linux/ipq806x/patches-3.18/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch b/target/linux/ipq806x/patches-3.18/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch new file mode 100644 index 0000000..cae7f15 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -181,6 +181,8 @@ + + nand-ecc-strength = <4>; + nand-bus-width = <8>; ++ ++ linux,part-probe = "qcom-smem"; + }; + }; + }; diff --git a/target/linux/ipq806x/patches-3.18/300-arch-arm-force-ZRELADDR-on-arch-qcom.patch b/target/linux/ipq806x/patches-3.18/300-arch-arm-force-ZRELADDR-on-arch-qcom.patch new file mode 100644 index 0000000..8669b02 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/300-arch-arm-force-ZRELADDR-on-arch-qcom.patch @@ -0,0 +1,62 @@ +From b12e230f09d4481424e6a5d7e2ae566b6954e83f Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Wed, 29 Apr 2015 15:21:46 -0700 +Subject: [PATCH] HACK: arch: arm: force ZRELADDR on arch-qcom + +ARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended +on most ARM architectures. This automatically calculate ZRELADDR by +masking PHYS_OFFSET with 0xf8000000. + +However, on IPQ806x, the first ~20MB of RAM is reserved for the hardware +network accelerators, and the bootloader removes this section from the +layout passed from the ATAGS (when used). + +For newer bootloader, when DT is used, this is not a problem, we just +reserve this memory in the device tree. But if the bootloader doesn't +have DT support, then ATAGS have to be used. In this case, the ARM +decompressor will position the kernel in this low mem, which will not be +in the RAM section mapped by the bootloader, which means the kernel will +freeze in the middle of the boot process trying to map the memory. + +As a work around, this patch allows disabling AUTO_ZRELADDR when +ARCH_QCOM is selected. It makes the zImage usage possible on bootloaders +which don't support device-tree, which is the case on certain early +IPQ806x based designs. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/Kconfig | 2 +- + arch/arm/Makefile | 2 ++ + arch/arm/mach-qcom/Makefile.boot | 1 + + 3 files changed, 4 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/mach-qcom/Makefile.boot + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -311,7 +311,7 @@ config ARCH_MULTIPLATFORM + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_HAS_SG_CHAIN + select ARM_PATCH_PHYS_VIRT +- select AUTO_ZRELADDR ++ select AUTO_ZRELADDR if !ARCH_QCOM + select CLKSRC_OF + select COMMON_CLK + select GENERIC_CLOCKEVENTS +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -248,9 +248,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac + else + MACHINE := + endif ++ifeq ($(CONFIG_ARCH_QCOM),) + ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y) + MACHINE := + endif ++endif + + machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) + platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y))) +--- /dev/null ++++ b/arch/arm/mach-qcom/Makefile.boot +@@ -0,0 +1 @@ ++zreladdr-y+= 0x42208000 diff --git a/target/linux/ipq806x/patches-3.18/301-ARM-qcom-add-Netgear-Nighthawk-X4-R7500-device-tree.patch b/target/linux/ipq806x/patches-3.18/301-ARM-qcom-add-Netgear-Nighthawk-X4-R7500-device-tree.patch new file mode 100644 index 0000000..a9b83a1 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/301-ARM-qcom-add-Netgear-Nighthawk-X4-R7500-device-tree.patch @@ -0,0 +1,387 @@ +From 7e77aa188a7a7c4391856a9e5ef5ef58f769e679 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Aug 2015 13:02:38 +0200 +Subject: [PATCH] ARM: qcom: add Netgear Nighthawk X4 R7500 device tree + +Signed-off-by: Jonas Gorski +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 370 +++++++++++++++++++++++++++++++ + 2 files changed, 371 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-r7500.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -361,6 +361,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8084-mtp.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-db149.dtb \ ++ qcom-ipq8064-r7500.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb \ + qcom-msm8974-sony-xperia-honami.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +@@ -0,0 +1,362 @@ ++#include "qcom-ipq8064-v1.0.dtsi" ++ ++#include ++ ++/ { ++ model = "Netgear Nighthawk X4 R7500"; ++ compatible = "netgear,r7500", "qcom,ipq8064"; ++ ++ memory@0 { ++ reg = <0x42000000 0xe000000>; ++ device_type = "memory"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ rsvd@41200000 { ++ reg = <0x41200000 0x300000>; ++ no-map; ++ }; ++ }; ++ ++ aliases { ++ serial0 = &uart4; ++ mdio-gpio0 = &mdio0; ++ }; ++ ++ chosen { ++ bootargs = "rootfstype=squashfs noinitrd"; ++ linux,stdout-path = "serial0:115200n8"; ++ }; ++ ++ soc { ++ pinmux@800000 { ++ i2c4_pins: i2c4_pinmux { ++ pins = "gpio12", "gpio13"; ++ function = "gsbi4"; ++ bias-disable; ++ }; ++ ++ pcie0_pins: pcie0_pinmux { ++ mux { ++ pins = "gpio3"; ++ function = "pcie1_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ pcie1_pins: pcie1_pinmux { ++ mux { ++ pins = "gpio48"; ++ function = "pcie2_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ nand_pins: nand_pins { ++ mux { ++ pins = "gpio34", "gpio35", "gpio36", ++ "gpio37", "gpio38", "gpio39", ++ "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ function = "nand"; ++ drive-strength = <10>; ++ bias-disable; ++ }; ++ pullups { ++ pins = "gpio39"; ++ bias-pull-up; ++ }; ++ hold { ++ pins = "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ bias-bus-hold; ++ }; ++ }; ++ ++ mdio0_pins: mdio0_pins { ++ mux { ++ pins = "gpio0", "gpio1"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ rgmii2_pins: rgmii2_pins { ++ mux { ++ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", ++ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; ++ function = "rgmii2"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ }; ++ ++ gsbi@16300000 { ++ qcom,mode = ; ++ status = "ok"; ++ serial@16340000 { ++ status = "ok"; ++ }; ++ /* ++ * The i2c device on gsbi4 should not be enabled. ++ * On ipq806x designs gsbi4 i2c is meant for exclusive ++ * RPM usage. Turning this on in kernel manifests as ++ * i2c failure for the RPM. ++ */ ++ }; ++ ++ sata-phy@1b400000 { ++ status = "ok"; ++ }; ++ ++ sata@29000000 { ++ status = "ok"; ++ }; ++ ++ phy@100f8800 { /* USB3 port 1 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@100f8830 { /* USB3 port 1 SS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8800 { /* USB3 port 0 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8830 { /* USB3 port 0 SS phy */ ++ status = "ok"; ++ }; ++ ++ usb30@0 { ++ status = "ok"; ++ }; ++ ++ usb30@1 { ++ status = "ok"; ++ }; ++ ++ pcie0: pci@1b500000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 3 0>; ++ pinctrl-0 = <&pcie0_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ pcie1: pci@1b700000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 48 0>; ++ pinctrl-0 = <&pcie1_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ nand@1ac00000 { ++ status = "ok"; ++ ++ pinctrl-0 = <&nand_pins>; ++ pinctrl-names = "default"; ++ ++ nand-ecc-strength = <4>; ++ nand-bus-width = <8>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ qcadata@0 { ++ label = "qcadata"; ++ reg = <0x0000000 0x0c80000>; ++ read-only; ++ }; ++ ++ APPSBL@c80000 { ++ label = "APPSBL"; ++ reg = <0x0c80000 0x0500000>; ++ read-only; ++ }; ++ ++ APPSBLENV@1180000 { ++ label = "APPSBLENV"; ++ reg = <0x1180000 0x0080000>; ++ read-only; ++ }; ++ ++ art: art@1200000 { ++ label = "art"; ++ reg = <0x1200000 0x0140000>; ++ read-only; ++ }; ++ ++ kernel@1340000 { ++ label = "kernel"; ++ reg = <0x1340000 0x0200000>; ++ }; ++ ++ ubi@1540000 { ++ label = "ubi"; ++ reg = <0x1540000 0x1800000>; ++ }; ++ ++ netgear@2d40000 { ++ label = "netgear"; ++ reg = <0x2d40000 0x0c00000>; ++ read-only; ++ }; ++ ++ reserve@3940000 { ++ label = "reserve"; ++ reg = <0x3940000 0x46c0000>; ++ read-only; ++ }; ++ ++ firmware@1340000 { ++ label = "firmware"; ++ reg = <0x1340000 0x1a00000>; ++ }; ++ ++ }; ++ ++ mdio0: mdio { ++ compatible = "virtual,mdio-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>; ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++ ++ phy0: ethernet-phy@0 { ++ device_type = "ethernet-phy"; ++ reg = <0>; ++ qca,ar8327-initvals = < ++ 0x00004 0x7600000 /* PAD0_MODE */ ++ 0x00008 0x1000000 /* PAD5_MODE */ ++ 0x0000c 0x80 /* PAD6_MODE */ ++ 0x000e4 0xaa545 /* MAC_POWER_SEL */ ++ 0x000e0 0xc74164de /* SGMII_CTRL */ ++ 0x0007c 0x4e /* PORT0_STATUS */ ++ 0x00094 0x4e /* PORT6_STATUS */ ++ >; ++ }; ++ ++ phy4: ethernet-phy@4 { ++ device_type = "ethernet-phy"; ++ reg = <4>; ++ }; ++ }; ++ ++ gmac1: ethernet@37200000 { ++ status = "ok"; ++ phy-mode = "rgmii"; ++ phy-handle = <&phy4>; ++ qcom,id = <1>; ++ ++ pinctrl-0 = <&rgmii2_pins>; ++ pinctrl-names = "default"; ++ ++ mtd-mac-address = <&art 6>; ++ }; ++ ++ gmac2: ethernet@37400000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <2>; ++ ++ mtd-mac-address = <&art 0>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ wifi { ++ label = "wifi"; ++ gpios = <&qcom_pinmux 6 1>; ++ linux,code = ; ++ }; ++ ++ reset { ++ label = "reset"; ++ gpios = <&qcom_pinmux 54 1>; ++ linux,code = ; ++ }; ++ ++ wps { ++ label = "wps"; ++ gpios = <&qcom_pinmux 65 1>; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ ++ usb1 { ++ label = "r7500:amber:usb1"; ++ gpios = <&qcom_pinmux 7 0>; ++ }; ++ ++ usb3 { ++ label = "r7500:amber:usb3"; ++ gpios = <&qcom_pinmux 8 0>; ++ }; ++ ++ status { ++ label = "r7500:amber:status"; ++ gpios = <&qcom_pinmux 9 0>; ++ }; ++ ++ internet { ++ label = "r7500:white:internet"; ++ gpios = <&qcom_pinmux 22 0>; ++ }; ++ ++ wan { ++ label = "r7500:white:wan"; ++ gpios = <&qcom_pinmux 23 0>; ++ }; ++ ++ wps { ++ label = "r7500:white:wps"; ++ gpios = <&qcom_pinmux 24 0>; ++ }; ++ ++ esata { ++ label = "r7500:white:esata"; ++ gpios = <&qcom_pinmux 26 0>; ++ }; ++ ++ power { ++ label = "r7500:white:power"; ++ gpios = <&qcom_pinmux 53 0>; ++ default-state = "on"; ++ }; ++ ++ rfkill { ++ label = "r7500:white:rfkill"; ++ gpios = <&qcom_pinmux 64 0>; ++ }; ++ ++ wifi5g { ++ label = "r7500:white:wifi5g"; ++ gpios = <&qcom_pinmux 67 0>; ++ }; ++ }; ++}; ++ ++&adm_dma { ++ status = "ok"; ++}; diff --git a/target/linux/ipq806x/patches-3.18/302-mtd-qcom-smem-rename-rootfs-ubi.patch b/target/linux/ipq806x/patches-3.18/302-mtd-qcom-smem-rename-rootfs-ubi.patch new file mode 100644 index 0000000..471a87b --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/302-mtd-qcom-smem-rename-rootfs-ubi.patch @@ -0,0 +1,13 @@ +--- a/drivers/mtd/qcom_smem_part.c ++++ b/drivers/mtd/qcom_smem_part.c +@@ -192,6 +192,10 @@ static int parse_qcom_smem_partitions(st + m_part->size = le32_to_cpu(s_part->size) * (*smem_blksz); + m_part->offset = le32_to_cpu(s_part->start) * (*smem_blksz); + ++ /* "rootfs" conflicts with OpenWrt auto mounting */ ++ if (mtd_type_is_nand(master) && !strcmp(m_part->name, "rootfs")) ++ m_part->name = "ubi"; ++ + /* + * The last SMEM partition may have its size marked as + * something like 0xffffffff, which means "until the end of the diff --git a/target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch b/target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch new file mode 100644 index 0000000..22d28ac --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch @@ -0,0 +1,733 @@ +From 2fbb18f85826a9ba308fedb2cf90d3a661a39fd7 Mon Sep 17 00:00:00 2001 +From: Stephen Boyd +Date: Fri, 27 Mar 2015 00:16:14 -0700 +Subject: [PATCH] clk: qcom: Add support for NSS/GMAC clocks and resets + +Add the NSS/GMAC clocks and the TCM clock and NSS resets. + +Signed-off-by: Stephen Boyd +--- + drivers/clk/qcom/gcc-ipq806x.c | 594 ++++++++++++++++++++++++++- + drivers/clk/qcom/gcc-ipq806x.c.rej | 50 +++ + include/dt-bindings/clock/qcom,gcc-ipq806x.h | 2 + + include/dt-bindings/reset/qcom,gcc-ipq806x.h | 43 ++ + 4 files changed, 688 insertions(+), 1 deletion(-) + create mode 100644 drivers/clk/qcom/gcc-ipq806x.c.rej + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -209,11 +209,46 @@ static struct clk_regmap pll14_vote = { + }, + }; + ++#define NSS_PLL_RATE(f, _l, _m, _n, i) \ ++ { \ ++ .freq = f, \ ++ .l = _l, \ ++ .m = _m, \ ++ .n = _n, \ ++ .ibits = i, \ ++ } ++ ++static struct pll_freq_tbl pll18_freq_tbl[] = { ++ NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), ++ NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), ++}; ++ ++static struct clk_pll pll18 = { ++ .l_reg = 0x31a4, ++ .m_reg = 0x31a8, ++ .n_reg = 0x31ac, ++ .config_reg = 0x31b4, ++ .mode_reg = 0x31a0, ++ .status_reg = 0x31b8, ++ .status_bit = 16, ++ .post_div_shift = 16, ++ .post_div_width = 1, ++ .freq_tbl = pll18_freq_tbl, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "pll18", ++ .parent_names = (const char *[]){ "pxo" }, ++ .num_parents = 1, ++ .ops = &clk_pll_ops, ++ }, ++}; ++ + #define P_PXO 0 + #define P_PLL8 1 + #define P_PLL3 1 + #define P_PLL0 2 + #define P_CXO 2 ++#define P_PLL14 3 ++#define P_PLL18 4 + + static const u8 gcc_pxo_pll8_map[] = { + [P_PXO] = 0, +@@ -264,6 +299,22 @@ static const char *gcc_pxo_pll8_pll0_map + "pll0_vote", + }; + ++static const u8 gcc_pxo_pll8_pll14_pll18_pll0_map[] = { ++ [P_PXO] = 0 , ++ [P_PLL8] = 4, ++ [P_PLL0] = 2, ++ [P_PLL14] = 5, ++ [P_PLL18] = 1, ++}; ++ ++static const char *gcc_pxo_pll8_pll14_pll18_pll0[] = { ++ "pxo", ++ "pll8_vote", ++ "pll0_vote", ++ "pll14", ++ "pll18", ++}; ++ + static struct freq_tbl clk_tbl_gsbi_uart[] = { + { 1843200, P_PLL8, 2, 6, 625 }, + { 3686400, P_PLL8, 2, 12, 625 }, +@@ -2269,6 +2320,472 @@ static struct clk_branch ebi2_aon_clk = + }, + }; + ++static const struct freq_tbl clk_tbl_gmac[] = { ++ { 133000000, P_PLL0, 1, 50, 301 }, ++ { 266000000, P_PLL0, 1, 127, 382 }, ++ { } ++}; ++ ++static struct clk_dyn_rcg gmac_core1_src = { ++ .ns_reg[0] = 0x3cac, ++ .ns_reg[1] = 0x3cb0, ++ .md_reg[0] = 0x3ca4, ++ .md_reg[1] = 0x3ca8, ++ .bank_reg = 0x3ca0, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_gmac, ++ .clkr = { ++ .enable_reg = 0x3ca0, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core1_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gmac_core1_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 4, ++ .hwcg_reg = 0x3cb4, ++ .hwcg_bit = 6, ++ .clkr = { ++ .enable_reg = 0x3cb4, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core1_clk", ++ .parent_names = (const char *[]){ ++ "gmac_core1_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_dyn_rcg gmac_core2_src = { ++ .ns_reg[0] = 0x3ccc, ++ .ns_reg[1] = 0x3cd0, ++ .md_reg[0] = 0x3cc4, ++ .md_reg[1] = 0x3cc8, ++ .bank_reg = 0x3ca0, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_gmac, ++ .clkr = { ++ .enable_reg = 0x3cc0, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core2_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gmac_core2_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 5, ++ .hwcg_reg = 0x3cd4, ++ .hwcg_bit = 6, ++ .clkr = { ++ .enable_reg = 0x3cd4, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core2_clk", ++ .parent_names = (const char *[]){ ++ "gmac_core2_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_dyn_rcg gmac_core3_src = { ++ .ns_reg[0] = 0x3cec, ++ .ns_reg[1] = 0x3cf0, ++ .md_reg[0] = 0x3ce4, ++ .md_reg[1] = 0x3ce8, ++ .bank_reg = 0x3ce0, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_gmac, ++ .clkr = { ++ .enable_reg = 0x3ce0, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core3_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gmac_core3_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 6, ++ .hwcg_reg = 0x3cf4, ++ .hwcg_bit = 6, ++ .clkr = { ++ .enable_reg = 0x3cf4, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core3_clk", ++ .parent_names = (const char *[]){ ++ "gmac_core3_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_dyn_rcg gmac_core4_src = { ++ .ns_reg[0] = 0x3d0c, ++ .ns_reg[1] = 0x3d10, ++ .md_reg[0] = 0x3d04, ++ .md_reg[1] = 0x3d08, ++ .bank_reg = 0x3d00, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_gmac, ++ .clkr = { ++ .enable_reg = 0x3d00, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core4_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gmac_core4_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 7, ++ .hwcg_reg = 0x3d14, ++ .hwcg_bit = 6, ++ .clkr = { ++ .enable_reg = 0x3d14, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core4_clk", ++ .parent_names = (const char *[]){ ++ "gmac_core4_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl clk_tbl_nss_tcm[] = { ++ { 266000000, P_PLL0, 3, 0, 0 }, ++ { 400000000, P_PLL0, 2, 0, 0 }, ++ { } ++}; ++ ++static struct clk_dyn_rcg nss_tcm_src = { ++ .ns_reg[0] = 0x3dc4, ++ .ns_reg[1] = 0x3dc8, ++ .bank_reg = 0x3dc0, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 4, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 4, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_nss_tcm, ++ .clkr = { ++ .enable_reg = 0x3dc0, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "nss_tcm_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_tcm_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 14, ++ .clkr = { ++ .enable_reg = 0x3dd0, ++ .enable_mask = BIT(6) | BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "nss_tcm_clk", ++ .parent_names = (const char *[]){ ++ "nss_tcm_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl clk_tbl_nss[] = { ++ { 110000000, P_PLL18, 1, 1, 5 }, ++ { 275000000, P_PLL18, 2, 0, 0 }, ++ { 550000000, P_PLL18, 1, 0, 0 }, ++ { 733000000, P_PLL18, 1, 0, 0 }, ++ { } ++}; ++ ++static struct clk_dyn_rcg ubi32_core1_src_clk = { ++ .ns_reg[0] = 0x3d2c, ++ .ns_reg[1] = 0x3d30, ++ .md_reg[0] = 0x3d24, ++ .md_reg[1] = 0x3d28, ++ .bank_reg = 0x3d20, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_nss, ++ .clkr = { ++ .enable_reg = 0x3d20, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "ubi32_core1_src_clk", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, ++ }, ++ }, ++}; ++ ++static struct clk_dyn_rcg ubi32_core2_src_clk = { ++ .ns_reg[0] = 0x3d4c, ++ .ns_reg[1] = 0x3d50, ++ .md_reg[0] = 0x3d44, ++ .md_reg[1] = 0x3d48, ++ .bank_reg = 0x3d40, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_nss, ++ .clkr = { ++ .enable_reg = 0x3d40, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "ubi32_core2_src_clk", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, ++ }, ++ }, ++}; ++ + static struct clk_regmap *gcc_ipq806x_clks[] = { + [PLL0] = &pll0.clkr, + [PLL0_VOTE] = &pll0_vote, +@@ -2277,6 +2794,7 @@ static struct clk_regmap *gcc_ipq806x_cl + [PLL8_VOTE] = &pll8_vote, + [PLL14] = &pll14.clkr, + [PLL14_VOTE] = &pll14_vote, ++ [PLL18] = &pll18.clkr, + [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, + [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, + [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, +@@ -2376,6 +2894,18 @@ static struct clk_regmap *gcc_ipq806x_cl + [PLL9] = &hfpll0.clkr, + [PLL10] = &hfpll1.clkr, + [PLL12] = &hfpll_l2.clkr, ++ [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr, ++ [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr, ++ [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr, ++ [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr, ++ [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr, ++ [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr, ++ [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr, ++ [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr, ++ [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr, ++ [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, ++ [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, ++ [NSSTCM_CLK] = &nss_tcm_clk.clkr, + }; + + static const struct qcom_reset_map gcc_ipq806x_resets[] = { +@@ -2494,6 +3024,48 @@ static const struct qcom_reset_map gcc_i + [USB30_1_PHY_RESET] = { 0x3b58, 0 }, + [NSSFB0_RESET] = { 0x3b60, 6 }, + [NSSFB1_RESET] = { 0x3b60, 7 }, ++ [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3}, ++ [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 }, ++ [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 }, ++ [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 }, ++ [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 }, ++ [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 }, ++ [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 }, ++ [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 }, ++ [GMAC_CORE1_RESET] = { 0x3cbc, 0 }, ++ [GMAC_CORE2_RESET] = { 0x3cdc, 0 }, ++ [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, ++ [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, ++ [GMAC_AHB_RESET] = { 0x3e24, 0 }, ++ [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, ++ [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, ++ [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, ++ [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 }, ++ [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 }, ++ [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 }, ++ [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 }, ++ [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 }, ++ [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 }, ++ [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 }, ++ [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 }, ++ [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 }, ++ [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 }, ++ [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 }, ++ [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 }, ++ [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 }, ++ [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 }, ++ [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 }, ++ [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 }, ++ [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 }, ++ [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 }, ++ [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 }, ++ [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 }, ++ [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 }, ++ [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 }, ++ [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 }, ++ [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 }, ++ [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 }, ++ [NSS_SRDS_N_RESET] = { 0x3b60, 28 }, + }; + + static const struct regmap_config gcc_ipq806x_regmap_config = { +@@ -2522,6 +3094,8 @@ static int gcc_ipq806x_probe(struct plat + { + struct clk *clk; + struct device *dev = &pdev->dev; ++ struct regmap *regmap; ++ int ret; + + /* Temporary until RPM clocks supported */ + clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); +@@ -2532,7 +3106,25 @@ static int gcc_ipq806x_probe(struct plat + if (IS_ERR(clk)) + return PTR_ERR(clk); + +- return qcom_cc_probe(pdev, &gcc_ipq806x_desc); ++ ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); ++ if (ret) ++ return ret; ++ ++ regmap = dev_get_regmap(dev, NULL); ++ if (!regmap) ++ return -ENODEV; ++ ++ /* Setup PLL18 static bits */ ++ regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); ++ regmap_write(regmap, 0x31b0, 0x3080); ++ ++ /* Set GMAC footswitch sleep/wakeup values */ ++ regmap_write(regmap, 0x3cb8, 8); ++ regmap_write(regmap, 0x3cd8, 8); ++ regmap_write(regmap, 0x3cf8, 8); ++ regmap_write(regmap, 0x3d18, 8); ++ ++ return 0; + } + + static int gcc_ipq806x_remove(struct platform_device *pdev) +--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h +@@ -290,5 +290,7 @@ + #define UBI32_CORE1_CLK 279 + #define UBI32_CORE2_CLK 280 + #define EBI2_AON_CLK 281 ++#define NSSTCM_CLK_SRC 282 ++#define NSSTCM_CLK 283 + + #endif +--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h +@@ -129,4 +129,47 @@ + #define USB30_1_PHY_RESET 112 + #define NSSFB0_RESET 113 + #define NSSFB1_RESET 114 ++#define UBI32_CORE1_CLKRST_CLAMP_RESET 115 ++#define UBI32_CORE1_CLAMP_RESET 116 ++#define UBI32_CORE1_AHB_RESET 117 ++#define UBI32_CORE1_AXI_RESET 118 ++#define UBI32_CORE2_CLKRST_CLAMP_RESET 119 ++#define UBI32_CORE2_CLAMP_RESET 120 ++#define UBI32_CORE2_AHB_RESET 121 ++#define UBI32_CORE2_AXI_RESET 122 ++#define GMAC_CORE1_RESET 123 ++#define GMAC_CORE2_RESET 124 ++#define GMAC_CORE3_RESET 125 ++#define GMAC_CORE4_RESET 126 ++#define GMAC_AHB_RESET 127 ++#define NSS_CH0_RST_RX_CLK_N_RESET 128 ++#define NSS_CH0_RST_TX_CLK_N_RESET 129 ++#define NSS_CH0_RST_RX_125M_N_RESET 130 ++#define NSS_CH0_HW_RST_RX_125M_N_RESET 131 ++#define NSS_CH0_RST_TX_125M_N_RESET 132 ++#define NSS_CH1_RST_RX_CLK_N_RESET 133 ++#define NSS_CH1_RST_TX_CLK_N_RESET 134 ++#define NSS_CH1_RST_RX_125M_N_RESET 135 ++#define NSS_CH1_HW_RST_RX_125M_N_RESET 136 ++#define NSS_CH1_RST_TX_125M_N_RESET 137 ++#define NSS_CH2_RST_RX_CLK_N_RESET 138 ++#define NSS_CH2_RST_TX_CLK_N_RESET 139 ++#define NSS_CH2_RST_RX_125M_N_RESET 140 ++#define NSS_CH2_HW_RST_RX_125M_N_RESET 141 ++#define NSS_CH2_RST_TX_125M_N_RESET 142 ++#define NSS_CH3_RST_RX_CLK_N_RESET 143 ++#define NSS_CH3_RST_TX_CLK_N_RESET 144 ++#define NSS_CH3_RST_RX_125M_N_RESET 145 ++#define NSS_CH3_HW_RST_RX_125M_N_RESET 146 ++#define NSS_CH3_RST_TX_125M_N_RESET 147 ++#define NSS_RST_RX_250M_125M_N_RESET 148 ++#define NSS_RST_TX_250M_125M_N_RESET 149 ++#define NSS_QSGMII_TXPI_RST_N_RESET 150 ++#define NSS_QSGMII_CDR_RST_N_RESET 151 ++#define NSS_SGMII2_CDR_RST_N_RESET 152 ++#define NSS_SGMII3_CDR_RST_N_RESET 153 ++#define NSS_CAL_PRBS_RST_N_RESET 154 ++#define NSS_LCKDT_RST_N_RESET 155 ++#define NSS_SRDS_N_RESET 156 ++ + #endif diff --git a/target/linux/ipq806x/patches-3.18/701-stmmac-add-phy-handle-support-to-the-platform-layer.patch b/target/linux/ipq806x/patches-3.18/701-stmmac-add-phy-handle-support-to-the-platform-layer.patch new file mode 100644 index 0000000..8e59b5c --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/701-stmmac-add-phy-handle-support-to-the-platform-layer.patch @@ -0,0 +1,105 @@ +From 4f09499bc1d9bb095caccbcd73ff951ee631e521 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 15:42:40 -0700 +Subject: [PATCH 1/8] stmmac: add phy-handle support to the platform layer + +On stmmac driver, PHY specification in device-tree was done using the +non-standard property "snps,phy-addr". Specifying a PHY on a different +MDIO bus that the one within the stmmac controller doesn't seem to be +possible when device-tree is used. + +This change adds support for the phy-handle property, as specified in +Documentation/devicetree/bindings/net/ethernet.txt. + +Signed-off-by: Mathieu Olivari +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 28 ++++++++++++++-------- + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 6 ++++- + include/linux/stmmac.h | 1 + + 3 files changed, 24 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -52,6 +52,7 @@ + #include "stmmac_ptp.h" + #include "stmmac.h" + #include ++#include + + #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) + +@@ -818,18 +819,25 @@ static int stmmac_init_phy(struct net_de + priv->speed = 0; + priv->oldduplex = -1; + +- if (priv->plat->phy_bus_name) +- snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", +- priv->plat->phy_bus_name, priv->plat->bus_id); +- else +- snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", +- priv->plat->bus_id); +- +- snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, +- priv->plat->phy_addr); +- pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); ++ if (priv->plat->phy_node) { ++ phydev = of_phy_connect(dev, priv->plat->phy_node, ++ &stmmac_adjust_link, 0, interface); ++ } else { ++ if (priv->plat->phy_bus_name) ++ snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", ++ priv->plat->phy_bus_name, priv->plat->bus_id); ++ else ++ snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", ++ priv->plat->bus_id); ++ ++ snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, ++ priv->plat->phy_addr); ++ pr_debug("stmmac_init_phy: trying to attach to %s\n", ++ phy_id_fmt); + +- phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); ++ phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, ++ interface); ++ } + + if (IS_ERR(phydev)) { + pr_err("%s: Could not attach to PHY\n", dev->name); +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + #include "stmmac.h" + + static const struct of_device_id stmmac_dt_ids[] = { +@@ -155,13 +156,16 @@ static int stmmac_probe_config_dt(struct + /* Default to phy auto-detection */ + plat->phy_addr = -1; + ++ /* If we find a phy-handle property, use it as the PHY */ ++ plat->phy_node = of_parse_phandle(np, "phy-handle", 0); ++ + /* "snps,phy-addr" is not a standard property. Mark it as deprecated + * and warn of its use. Remove this when phy node support is added. + */ + if (of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0) + dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n"); + +- if (plat->phy_bus_name) ++ if (plat->phy_node || plat->phy_bus_name) + plat->mdio_bus_data = NULL; + else + plat->mdio_bus_data = +--- a/include/linux/stmmac.h ++++ b/include/linux/stmmac.h +@@ -99,6 +99,7 @@ struct plat_stmmacenet_data { + int phy_addr; + int interface; + struct stmmac_mdio_bus_data *mdio_bus_data; ++ struct device_node *phy_node; + struct stmmac_dma_cfg *dma_cfg; + int clk_csr; + int has_gmac; diff --git a/target/linux/ipq806x/patches-3.18/702-stmmac-move-error-path-at-the-end-of-stmmac_probe_co.patch b/target/linux/ipq806x/patches-3.18/702-stmmac-move-error-path-at-the-end-of-stmmac_probe_co.patch new file mode 100644 index 0000000..e8f9b5c --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/702-stmmac-move-error-path-at-the-end-of-stmmac_probe_co.patch @@ -0,0 +1,65 @@ +From 0149d275415cd1b2382ce94e5eb32641590097d0 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 15:57:12 -0700 +Subject: [PATCH 2/8] stmmac: move error path at the end of + stmmac_probe_config_dt() + +We will want to do additional clean-up on certain errors. Therefore, +this change moves the error path at the end of the function for better +code readability. + +This patch doesn't change anything functionally. + +Signed-off-by: Mathieu Olivari +--- + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 22 ++++++++++++++++------ + 1 file changed, 16 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -117,13 +117,18 @@ static int stmmac_probe_config_dt(struct + struct device_node *np = pdev->dev.of_node; + struct stmmac_dma_cfg *dma_cfg; + const struct of_device_id *device; ++ int ret; + +- if (!np) +- return -ENODEV; ++ if (!np) { ++ ret = -ENODEV; ++ goto err; ++ } + + device = of_match_device(stmmac_dt_ids, &pdev->dev); +- if (!device) +- return -ENODEV; ++ if (!device) { ++ ret = -ENODEV; ++ goto err; ++ } + + if (device->data) { + const struct stmmac_of_data *data = device->data; +@@ -219,8 +224,10 @@ static int stmmac_probe_config_dt(struct + if (of_find_property(np, "snps,pbl", NULL)) { + dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg), + GFP_KERNEL); +- if (!dma_cfg) +- return -ENOMEM; ++ if (!dma_cfg) { ++ ret = -ENOMEM; ++ goto err; ++ } + plat->dma_cfg = dma_cfg; + of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl); + dma_cfg->fixed_burst = +@@ -235,6 +242,9 @@ static int stmmac_probe_config_dt(struct + } + + return 0; ++ ++err: ++ return ret; + } + #else + static int stmmac_probe_config_dt(struct platform_device *pdev, diff --git a/target/linux/ipq806x/patches-3.18/703-stmmac-add-fixed-link-device-tree-support.patch b/target/linux/ipq806x/patches-3.18/703-stmmac-add-fixed-link-device-tree-support.patch new file mode 100644 index 0000000..3c20fe4 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/703-stmmac-add-fixed-link-device-tree-support.patch @@ -0,0 +1,64 @@ +From 3a95f75867be562cb919ff23a738f70357188fbd Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 16:02:03 -0700 +Subject: [PATCH 3/8] stmmac: add fixed-link device-tree support + +In case DT is used, this change adds the ability to the stmmac driver to +detect a fixed-link PHY, instanciate it, and use it during +phy_connect(). + +Fixed link PHYs DT usage is described in: +Documentation/devicetree/bindings/net/fixed-link.txt + +Signed-off-by: Mathieu Olivari +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 +++++++++++- + 2 files changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -858,7 +858,7 @@ static int stmmac_init_phy(struct net_de + * device as well. + * Note: phydev->phy_id is the result of reading the UID PHY registers. + */ +- if (phydev->phy_id == 0) { ++ if (!priv->plat->phy_node && phydev->phy_id == 0) { + phy_disconnect(phydev); + return -ENODEV; + } +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -164,6 +164,14 @@ static int stmmac_probe_config_dt(struct + /* If we find a phy-handle property, use it as the PHY */ + plat->phy_node = of_parse_phandle(np, "phy-handle", 0); + ++ /* If phy-handle is not specified, check if we have a fixed-phy */ ++ if (!plat->phy_node && of_phy_is_fixed_link(np)) { ++ if ((of_phy_register_fixed_link(np) < 0)) ++ return -ENODEV; ++ ++ plat->phy_node = of_node_get(np); ++ } ++ + /* "snps,phy-addr" is not a standard property. Mark it as deprecated + * and warn of its use. Remove this when phy node support is added. + */ +@@ -226,7 +234,7 @@ static int stmmac_probe_config_dt(struct + GFP_KERNEL); + if (!dma_cfg) { + ret = -ENOMEM; +- goto err; ++ goto err2; + } + plat->dma_cfg = dma_cfg; + of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl); +@@ -243,6 +251,8 @@ static int stmmac_probe_config_dt(struct + + return 0; + ++err2: ++ of_node_put(np); + err: + return ret; + } diff --git a/target/linux/ipq806x/patches-3.18/704-stmmac-add-ipq806x-glue-layer.patch b/target/linux/ipq806x/patches-3.18/704-stmmac-add-ipq806x-glue-layer.patch new file mode 100644 index 0000000..fa67404 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/704-stmmac-add-ipq806x-glue-layer.patch @@ -0,0 +1,427 @@ +From 69fb970ad3fe05af7cb99ea78230c69c7ca0d03b Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 16:10:22 -0700 +Subject: [PATCH 4/8] stmmac: add ipq806x glue layer + +The ethernet controller available in IPQ806x is a Synopsys DesignWare +Gigabit MAC IP core, already supported by the stmmac driver. + +This glue layer implements some platform specific settings required to +get the controller working on an IPQ806x based platform. + +Signed-off-by: Mathieu Olivari +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + + drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +- + drivers/net/ethernet/stmicro/stmmac/dwmac-ipq.c | 324 +++++++++++++++++++++ + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + + .../net/ethernet/stmicro/stmmac/stmmac_platform.h | 1 + + 5 files changed, 328 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq.c + +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -16,6 +16,7 @@ if STMMAC_ETH + config STMMAC_PLATFORM + bool "STMMAC Platform bus support" + depends on STMMAC_ETH ++ select MFD_SYSCON + default y + ---help--- + This selects the platform specific bus support for +@@ -26,6 +27,15 @@ config STMMAC_PLATFORM + + If unsure, say N. + ++config DWMAC_IPQ806X ++ bool "QCA IPQ806x dwmac support" ++ depends on STMMAC_PLATFORM && ARCH_QCOM ++ help ++ Support for Ethernet controller on QCA IPQ806x SoC. ++ ++ This selects the QCA IPQ806x SoC glue layer support for ++ the stmmac device driver. ++ + config DWMAC_MESON + bool "Amlogic Meson dwmac support" + depends on STMMAC_PLATFORM && ARCH_MESON +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -1,6 +1,7 @@ + obj-$(CONFIG_STMMAC_ETH) += stmmac.o + stmmac-$(CONFIG_STMMAC_PLATFORM) += stmmac_platform.o + stmmac-$(CONFIG_STMMAC_PCI) += stmmac_pci.o ++stmmac-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o + stmmac-$(CONFIG_DWMAC_MESON) += dwmac-meson.o + stmmac-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o + stmmac-$(CONFIG_DWMAC_STI) += dwmac-sti.o +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -46,6 +46,9 @@ static const struct of_device_id stmmac_ + #ifdef CONFIG_DWMAC_SOCFPGA + { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gmac_data }, + #endif ++#ifdef CONFIG_DWMAC_IPQ806X ++ { .compatible = "qcom,ipq806x-gmac", .data = &ipq806x_gmac_data }, ++#endif + /* SoC specific glue layers should come before generic bindings */ + { .compatible = "st,spear600-gmac"}, + { .compatible = "snps,dwmac-3.610"}, +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c +@@ -0,0 +1,343 @@ ++/* ++ * Qualcomm Atheros IPQ806x GMAC glue layer ++ * ++ * Copyright (C) 2015 The Linux Foundation ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "stmmac.h" ++ ++#define NSS_COMMON_CLK_GATE 0x8 ++#define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x) ++#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2)) ++#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2)) ++#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x) ++#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x) ++ ++#define NSS_COMMON_CLK_DIV0 0xC ++#define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8) ++#define NSS_COMMON_CLK_DIV_MASK 0x7f ++ ++#define NSS_COMMON_CLK_SRC_CTRL 0x14 ++#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (1 << x) ++/* Mode is coded on 1 bit but is different depending on the MAC ID: ++ * MAC0: QSGMII=0 RGMII=1 ++ * MAC1: QSGMII=0 SGMII=0 RGMII=1 ++ * MAC2 & MAC3: QSGMII=0 SGMII=1 ++ */ ++#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1 ++#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0) ++ ++#define NSS_COMMON_MACSEC_CTL 0x28 ++#define NSS_COMMON_MACSEC_CTL_EXT_BYPASS_EN(x) (1 << x) ++ ++#define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4)) ++#define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19) ++#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16) ++#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET 8 ++#define NSS_COMMON_GMAC_CTL_IFG_OFFSET 0 ++#define NSS_COMMON_GMAC_CTL_IFG_MASK 0x3f ++ ++#define NSS_COMMON_CLK_DIV_RGMII_1000 1 ++#define NSS_COMMON_CLK_DIV_RGMII_100 9 ++#define NSS_COMMON_CLK_DIV_RGMII_10 99 ++#define NSS_COMMON_CLK_DIV_SGMII_1000 0 ++#define NSS_COMMON_CLK_DIV_SGMII_100 4 ++#define NSS_COMMON_CLK_DIV_SGMII_10 49 ++ ++#define QSGMII_PCS_MODE_CTL 0x68 ++#define QSGMII_PCS_MODE_CTL_AUTONEG_EN(x) BIT((x * 8) + 7) ++ ++#define QSGMII_PCS_CAL_LCKDT_CTL 0x120 ++#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) ++ ++/* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */ ++#define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \ ++ (0x13c + (4 * (x - 2)))) ++#define QSGMII_PHY_CDR_EN BIT(0) ++#define QSGMII_PHY_RX_FRONT_EN BIT(1) ++#define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2) ++#define QSGMII_PHY_TX_DRIVER_EN BIT(3) ++#define QSGMII_PHY_QSGMII_EN BIT(7) ++#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12 ++#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK 0x7 ++#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18 ++#define QSGMII_PHY_RX_DC_BIAS_MASK 0x3 ++#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20 ++#define QSGMII_PHY_RX_INPUT_EQU_MASK 0x3 ++#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22 ++#define QSGMII_PHY_CDR_PI_SLEW_MASK 0x3 ++#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28 ++#define QSGMII_PHY_TX_DRV_AMP_MASK 0xf ++ ++struct ipq806x_gmac { ++ struct platform_device *pdev; ++ struct regmap *nss_common; ++ struct regmap *qsgmii_csr; ++ uint32_t id; ++ struct clk *core_clk; ++ phy_interface_t phy_mode; ++}; ++ ++static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed) ++{ ++ struct device *dev = &gmac->pdev->dev; ++ int div; ++ ++ switch (speed) { ++ case SPEED_1000: ++ div = NSS_COMMON_CLK_DIV_SGMII_1000; ++ break; ++ ++ case SPEED_100: ++ div = NSS_COMMON_CLK_DIV_SGMII_100; ++ break; ++ ++ case SPEED_10: ++ div = NSS_COMMON_CLK_DIV_SGMII_10; ++ break; ++ ++ default: ++ dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed); ++ return -EINVAL; ++ } ++ ++ return div; ++} ++ ++static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed) ++{ ++ struct device *dev = &gmac->pdev->dev; ++ int div; ++ ++ switch (speed) { ++ case SPEED_1000: ++ div = NSS_COMMON_CLK_DIV_RGMII_1000; ++ break; ++ ++ case SPEED_100: ++ div = NSS_COMMON_CLK_DIV_RGMII_100; ++ break; ++ ++ case SPEED_10: ++ div = NSS_COMMON_CLK_DIV_RGMII_10; ++ break; ++ ++ default: ++ dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed); ++ return -EINVAL; ++ } ++ ++ return div; ++} ++ ++static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed) ++{ ++ uint32_t clk_bits, val; ++ int div; ++ ++ switch (gmac->phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ div = get_clk_div_rgmii(gmac, speed); ++ clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | ++ NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); ++ break; ++ ++ case PHY_INTERFACE_MODE_SGMII: ++ div = get_clk_div_sgmii(gmac, speed); ++ clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) | ++ NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id); ++ break; ++ ++ default: ++ dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n", ++ phy_modes(gmac->phy_mode)); ++ return -EINVAL; ++ } ++ ++ /* Disable the clocks */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); ++ val &= ~clk_bits; ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); ++ ++ /* Set the divider */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val); ++ val &= ~(NSS_COMMON_CLK_DIV_MASK ++ << NSS_COMMON_CLK_DIV_OFFSET(gmac->id)); ++ val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id); ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val); ++ ++ /* Enable the clock back */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); ++ val |= clk_bits; ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); ++ ++ return 0; ++} ++ ++static void *ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac) ++{ ++ struct device *dev = &gmac->pdev->dev; ++ ++ gmac->phy_mode = of_get_phy_mode(dev->of_node); ++ if (gmac->phy_mode < 0) { ++ dev_err(dev, "missing phy mode property\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) { ++ dev_err(dev, "missing qcom id property\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ /* The GMACs are called 1 to 4 in the documentation, but to simplify the ++ * code and keep it consistent with the Linux convention, we'll number ++ * them from 0 to 3 here. ++ */ ++ if (gmac->id < 0 || gmac->id > 3) { ++ dev_err(dev, "invalid gmac id\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ gmac->core_clk = devm_clk_get(dev, "stmmaceth"); ++ if (IS_ERR(gmac->core_clk)) { ++ dev_err(dev, "missing stmmaceth clk property\n"); ++ return gmac->core_clk; ++ } ++ clk_set_rate(gmac->core_clk, 266000000); ++ ++ /* Setup the register map for the nss common registers */ ++ gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node, ++ "qcom,nss-common"); ++ if (IS_ERR(gmac->nss_common)) { ++ dev_err(dev, "missing nss-common node\n"); ++ return gmac->nss_common; ++ } ++ ++ /* Setup the register map for the qsgmii csr registers */ ++ gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node, ++ "qcom,qsgmii-csr"); ++ if (IS_ERR(gmac->qsgmii_csr)) { ++ dev_err(dev, "missing qsgmii-csr node\n"); ++ return gmac->qsgmii_csr; ++ } ++ ++ return NULL; ++} ++ ++static void *ipq806x_gmac_setup(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ipq806x_gmac *gmac; ++ int val; ++ void *err; ++ ++ gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); ++ if (!gmac) ++ return ERR_PTR(-ENOMEM); ++ ++ gmac->pdev = pdev; ++ ++ err = ipq806x_gmac_of_parse(gmac); ++ if (err) { ++ dev_err(dev, "device tree parsing error\n"); ++ return err; ++ } ++ ++ regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL, ++ QSGMII_PCS_CAL_LCKDT_CTL_RST); ++ ++ /* Inter frame gap is set to 12 */ ++ val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET | ++ 12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET; ++ /* We also initiate an AXI low power exit request */ ++ val |= NSS_COMMON_GMAC_CTL_CSYS_REQ; ++ switch (gmac->phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL; ++ break; ++ case PHY_INTERFACE_MODE_SGMII: ++ val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL; ++ break; ++ default: ++ dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n", ++ phy_modes(gmac->phy_mode)); ++ return NULL; ++ } ++ regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val); ++ ++ /* Configure the clock src according to the mode */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val); ++ val &= ~NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); ++ switch (gmac->phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) << ++ NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); ++ break; ++ case PHY_INTERFACE_MODE_SGMII: ++ val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) << ++ NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); ++ break; ++ default: ++ dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n", ++ phy_modes(gmac->phy_mode)); ++ return NULL; ++ } ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val); ++ ++ /* Enable PTP clock */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); ++ val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id); ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); ++ ++ if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) { ++ regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), ++ QSGMII_PHY_CDR_EN | ++ QSGMII_PHY_RX_FRONT_EN | ++ QSGMII_PHY_RX_SIGNAL_DETECT_EN | ++ QSGMII_PHY_TX_DRIVER_EN | ++ QSGMII_PHY_QSGMII_EN | ++ 0x4 << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET | ++ 0x3 << QSGMII_PHY_RX_DC_BIAS_OFFSET | ++ 0x1 << QSGMII_PHY_RX_INPUT_EQU_OFFSET | ++ 0x2 << QSGMII_PHY_CDR_PI_SLEW_OFFSET | ++ 0xC << QSGMII_PHY_TX_DRV_AMP_OFFSET); ++ } ++ ++ return gmac; ++} ++ ++static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed) ++{ ++ struct ipq806x_gmac *gmac = priv; ++ ++ ipq806x_gmac_set_speed(gmac, speed); ++} ++ ++const struct stmmac_of_data ipq806x_gmac_data = { ++ .has_gmac = 1, ++ .setup = ipq806x_gmac_setup, ++ .fix_mac_speed = ipq806x_gmac_fix_mac_speed, ++}; +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h +@@ -137,6 +137,9 @@ void stmmac_disable_eee_mode(struct stmm + bool stmmac_eee_init(struct stmmac_priv *priv); + + #ifdef CONFIG_STMMAC_PLATFORM ++#ifdef CONFIG_DWMAC_IPQ806X ++extern const struct stmmac_of_data ipq806x_gmac_data; ++#endif + #ifdef CONFIG_DWMAC_MESON + extern const struct stmmac_of_data meson6_dwmac_data; + #endif diff --git a/target/linux/ipq806x/patches-3.18/705-net-stmmac-ipq806x-document-device-tree-bindings.patch b/target/linux/ipq806x/patches-3.18/705-net-stmmac-ipq806x-document-device-tree-bindings.patch new file mode 100644 index 0000000..3144fa3 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/705-net-stmmac-ipq806x-document-device-tree-bindings.patch @@ -0,0 +1,52 @@ +From 0f9605d9409b77a89daef91cc68239fc2ff50457 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 16:51:25 -0700 +Subject: [PATCH 5/8] net: stmmac: ipq806x: document device tree bindings + +Add the device tree bindings documentation for the QCA IPQ806x +variant of the Synopsys DesignWare MAC. + +Signed-off-by: Mathieu Olivari +--- + .../devicetree/bindings/net/ipq806x-dwmac.txt | 35 ++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt +@@ -0,0 +1,35 @@ ++* IPQ806x DWMAC Ethernet controller ++ ++The device inherits all the properties of the dwmac/stmmac devices ++described in the file net/stmmac.txt with the following changes. ++ ++Required properties: ++ ++- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac" ++ and any applicable more detailed version number ++ described in net/stmmac.txt ++ ++- qcom,nss-common: should contain a phandle to a syscon device mapping the ++ nss-common registers. ++ ++- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the ++ qsgmii-csr registers. ++ ++Example: ++ ++ gmac: ethernet@37000000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37000000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE1_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE1_RESET>; ++ reset-names = "stmmaceth"; ++ }; diff --git a/target/linux/ipq806x/patches-3.18/706-net-stmmac-create-one-debugfs-dir-per-net-device.patch b/target/linux/ipq806x/patches-3.18/706-net-stmmac-create-one-debugfs-dir-per-net-device.patch new file mode 100644 index 0000000..50127fd --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/706-net-stmmac-create-one-debugfs-dir-per-net-device.patch @@ -0,0 +1,171 @@ +From df944689d491e6af533173bf2ef448c3dd334f15 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Mon, 11 May 2015 15:15:25 -0700 +Subject: [PATCH 6/8] net: stmmac: create one debugfs dir per net-device + +stmmac DebugFS entries are currently global to the driver. As a result, +having more than one stmmac device in the system creates the following +error: +* ERROR stmmaceth, debugfs create directory failed +* stmmac_hw_setup: failed debugFS registration + +This also results in being able to access the debugfs information for +the first registered device only. + +This patch changes the debugfs structure to have one sub-directory per +net-device. Files under "/sys/kernel/debug/stmmaceth" will now show-up +under /sys/kernel/debug/stmmaceth/ethN/. + +Signed-off-by: Mathieu Olivari +--- + drivers/net/ethernet/stmicro/stmmac/stmmac.h | 6 ++ + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 76 ++++++++++++++++------- + 2 files changed, 59 insertions(+), 23 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h +@@ -116,6 +116,12 @@ struct stmmac_priv { + int use_riwt; + int irq_wake; + spinlock_t ptp_lock; ++ ++#ifdef CONFIG_DEBUG_FS ++ struct dentry *dbgfs_dir; ++ struct dentry *dbgfs_rings_status; ++ struct dentry *dbgfs_dma_cap; ++#endif + }; + + int stmmac_mdio_unregister(struct net_device *ndev); +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -119,7 +119,7 @@ static irqreturn_t stmmac_interrupt(int + + #ifdef CONFIG_STMMAC_DEBUG_FS + static int stmmac_init_fs(struct net_device *dev); +-static void stmmac_exit_fs(void); ++static void stmmac_exit_fs(struct net_device *dev); + #endif + + #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) +@@ -1879,7 +1879,7 @@ static int stmmac_release(struct net_dev + netif_carrier_off(dev); + + #ifdef CONFIG_STMMAC_DEBUG_FS +- stmmac_exit_fs(); ++ stmmac_exit_fs(dev); + #endif + + stmmac_release_ptp(priv); +@@ -2467,8 +2467,6 @@ static int stmmac_ioctl(struct net_devic + + #ifdef CONFIG_STMMAC_DEBUG_FS + static struct dentry *stmmac_fs_dir; +-static struct dentry *stmmac_rings_status; +-static struct dentry *stmmac_dma_cap; + + static void sysfs_display_ring(void *head, int size, int extend_desc, + struct seq_file *seq) +@@ -2607,36 +2605,39 @@ static const struct file_operations stmm + + static int stmmac_init_fs(struct net_device *dev) + { +- /* Create debugfs entries */ +- stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); ++ struct stmmac_priv *priv = netdev_priv(dev); ++ ++ /* Create per netdev entries */ ++ priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); + +- if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { +- pr_err("ERROR %s, debugfs create directory failed\n", +- STMMAC_RESOURCE_NAME); ++ if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { ++ pr_err("ERROR %s/%s, debugfs create directory failed\n", ++ STMMAC_RESOURCE_NAME, dev->name); + + return -ENOMEM; + } + + /* Entry to report DMA RX/TX rings */ +- stmmac_rings_status = debugfs_create_file("descriptors_status", +- S_IRUGO, stmmac_fs_dir, dev, +- &stmmac_rings_status_fops); ++ priv->dbgfs_rings_status = ++ debugfs_create_file("descriptors_status", S_IRUGO, ++ priv->dbgfs_dir, dev, ++ &stmmac_rings_status_fops); + +- if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { ++ if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { + pr_info("ERROR creating stmmac ring debugfs file\n"); +- debugfs_remove(stmmac_fs_dir); ++ debugfs_remove_recursive(priv->dbgfs_dir); + + return -ENOMEM; + } + + /* Entry to report the DMA HW features */ +- stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, +- dev, &stmmac_dma_cap_fops); ++ priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, ++ priv->dbgfs_dir, ++ dev, &stmmac_dma_cap_fops); + +- if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { ++ if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { + pr_info("ERROR creating stmmac MMC debugfs file\n"); +- debugfs_remove(stmmac_rings_status); +- debugfs_remove(stmmac_fs_dir); ++ debugfs_remove_recursive(priv->dbgfs_dir); + + return -ENOMEM; + } +@@ -2644,11 +2645,11 @@ static int stmmac_init_fs(struct net_dev + return 0; + } + +-static void stmmac_exit_fs(void) ++static void stmmac_exit_fs(struct net_device *dev) + { +- debugfs_remove(stmmac_rings_status); +- debugfs_remove(stmmac_dma_cap); +- debugfs_remove(stmmac_fs_dir); ++ struct stmmac_priv *priv = netdev_priv(dev); ++ ++ debugfs_remove_recursive(priv->dbgfs_dir); + } + #endif /* CONFIG_STMMAC_DEBUG_FS */ + +@@ -3032,6 +3033,21 @@ static int __init stmmac_init(void) + ret = stmmac_register_pci(); + if (ret) + goto err_pci; ++ ++#ifdef CONFIG_STMMAC_DEBUG_FS ++ /* Create debugfs main directory if it doesn't exist yet */ ++ if (stmmac_fs_dir == NULL) { ++ stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); ++ ++ if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { ++ pr_err("ERROR %s, debugfs create directory failed\n", ++ STMMAC_RESOURCE_NAME); ++ ++ return -ENOMEM; ++ } ++ } ++#endif ++ + return 0; + err_pci: + stmmac_unregister_platform(); +@@ -3042,6 +3058,9 @@ err: + + static void __exit stmmac_exit(void) + { ++#ifdef CONFIG_STMMAC_DEBUG_FS ++ debugfs_remove_recursive(stmmac_fs_dir); ++#endif + stmmac_unregister_platform(); + stmmac_unregister_pci(); + } diff --git a/target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch b/target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch new file mode 100644 index 0000000..fe28942 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch @@ -0,0 +1,146 @@ +From e81de9d28bd0421c236df322872e64edf4ee1852 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Mon, 11 May 2015 16:32:09 -0700 +Subject: [PATCH 7/8] ARM: dts: qcom: add mdio nodes to ap148 & db149 + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40 ++++++++++++++++++++++++++- + arch/arm/boot/dts/qcom-ipq8064-db149.dts | 46 ++++++++++++++++++++++++++++++++ + 2 files changed, 85 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -19,8 +19,9 @@ + }; + }; + +- alias { ++ aliases { + serial0 = &uart4; ++ mdio-gpio0 = &mdio0; + }; + + chosen { +@@ -86,6 +87,15 @@ + bias-bus-hold; + }; + }; ++ ++ mdio0_pins: mdio0_pins { ++ mux { ++ pins = "gpio0", "gpio1"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + gsbi@16300000 { +@@ -184,6 +194,34 @@ + + linux,part-probe = "qcom-smem"; + }; ++ ++ mdio0: mdio { ++ compatible = "virtual,mdio-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>; ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++ ++ phy0: ethernet-phy@0 { ++ device_type = "ethernet-phy"; ++ reg = <0>; ++ qca,ar8327-initvals = < ++ 0x00004 0x7600000 /* PAD0_MODE */ ++ 0x00008 0x1000000 /* PAD5_MODE */ ++ 0x0000c 0x80 /* PAD6_MODE */ ++ 0x000e4 0xaa545 /* MAC_POWER_SEL */ ++ 0x000e0 0xc74164de /* SGMII_CTRL */ ++ 0x0007c 0x4e /* PORT0_STATUS */ ++ 0x00094 0x4e /* PORT6_STATUS */ ++ >; ++ }; ++ ++ phy4: ethernet-phy@4 { ++ device_type = "ethernet-phy"; ++ reg = <4>; ++ }; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts +@@ -16,6 +16,7 @@ + + alias { + serial0 = &uart2; ++ mdio-gpio0 = &mdio0; + }; + + chosen { +@@ -65,6 +66,15 @@ + bias-none; + }; + }; ++ ++ mdio0_pins: mdio0_pins { ++ mux { ++ pins = "gpio0", "gpio1"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + gsbi2: gsbi@12480000 { +@@ -176,5 +186,44 @@ + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; + }; ++ ++ mdio0: mdio { ++ compatible = "virtual,mdio-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>; ++ ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++ ++ phy0: ethernet-phy@0 { ++ device_type = "ethernet-phy"; ++ reg = <0>; ++ qca,ar8327-initvals = < ++ 0x00004 0x7600000 /* PAD0_MODE */ ++ 0x00008 0x1000000 /* PAD5_MODE */ ++ 0x0000c 0x80 /* PAD6_MODE */ ++ 0x000e4 0xaa545 /* MAC_POWER_SEL */ ++ 0x000e0 0xc74164de /* SGMII_CTRL */ ++ 0x0007c 0x4e /* PORT0_STATUS */ ++ 0x00094 0x4e /* PORT6_STATUS */ ++ >; ++ }; ++ ++ phy4: ethernet-phy@4 { ++ device_type = "ethernet-phy"; ++ reg = <4>; ++ }; ++ ++ phy6: ethernet-phy@6 { ++ device_type = "ethernet-phy"; ++ reg = <6>; ++ }; ++ ++ phy7: ethernet-phy@7 { ++ device_type = "ethernet-phy"; ++ reg = <7>; ++ }; ++ }; + }; + }; diff --git a/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch new file mode 100644 index 0000000..3455d45 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch @@ -0,0 +1,212 @@ +From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Mon, 11 May 2015 12:29:18 -0700 +Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++ + arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++ + arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++ + 3 files changed, 160 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -96,6 +96,16 @@ + bias-disable; + }; + }; ++ ++ rgmii2_pins: rgmii2_pins { ++ mux { ++ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", ++ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; ++ function = "rgmii2"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + gsbi@16300000 { +@@ -222,6 +232,27 @@ + reg = <4>; + }; + }; ++ ++ gmac1: ethernet@37200000 { ++ status = "ok"; ++ phy-mode = "rgmii"; ++ phy-handle = <&phy4>; ++ qcom,id = <1>; ++ ++ pinctrl-0 = <&rgmii2_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ gmac2: ethernet@37400000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <2>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts +@@ -75,6 +75,14 @@ + bias-disable; + }; + }; ++ ++ rgmii0_pins: rgmii0_pins { ++ mux { ++ pins = "gpio2", "gpio66"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + gsbi2: gsbi@12480000 { +@@ -225,5 +233,40 @@ + reg = <7>; + }; + }; ++ ++ gmac0: ethernet@37000000 { ++ status = "ok"; ++ phy-mode = "rgmii"; ++ qcom,id = <0>; ++ phy-handle = <&phy4>; ++ ++ pinctrl-0 = <&rgmii0_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ gmac1: ethernet@37200000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <1>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ gmac2: ethernet@37400000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <2>; ++ phy-handle = <&phy6>; ++ }; ++ ++ gmac3: ethernet@37600000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <3>; ++ phy-handle = <&phy7>; ++ }; + }; + }; +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -698,6 +698,92 @@ + status = "disabled"; + }; + ++ nss_common: syscon@03000000 { ++ compatible = "syscon"; ++ reg = <0x03000000 0x0000FFFF>; ++ }; ++ ++ qsgmii_csr: syscon@1bb00000 { ++ compatible = "syscon"; ++ reg = <0x1bb00000 0x000001FF>; ++ }; ++ ++ gmac0: ethernet@37000000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37000000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE1_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE1_RESET>; ++ reset-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ ++ gmac1: ethernet@37200000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37200000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE2_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE2_RESET>; ++ reset-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ ++ gmac2: ethernet@37400000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37400000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE3_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE3_RESET>; ++ reset-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ ++ gmac3: ethernet@37600000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37600000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE4_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE4_RESET>; ++ reset-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-3.18/709-stmac-platform-add-support-for-retreiving-mac-from-m.patch b/target/linux/ipq806x/patches-3.18/709-stmac-platform-add-support-for-retreiving-mac-from-m.patch new file mode 100644 index 0000000..68222ce --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/709-stmac-platform-add-support-for-retreiving-mac-from-m.patch @@ -0,0 +1,35 @@ +From 5bf2dabde1fa3af0c9082b42b6847ef3fd198b13 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Aug 2015 12:53:55 +0200 +Subject: [PATCH] stmac: platform: add support for retreiving mac from mtd + +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -284,6 +284,7 @@ static int stmmac_pltfr_probe(struct pla + struct stmmac_priv *priv = NULL; + struct plat_stmmacenet_data *plat_dat = NULL; + const char *mac = NULL; ++ u8 mtd_mac[ETH_ALEN] = { }; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + addr = devm_ioremap_resource(dev, res); +@@ -313,6 +314,15 @@ static int stmmac_pltfr_probe(struct pla + pr_err("%s: main dt probe failed", __func__); + return ret; + } ++ ++ if (!mac) { ++ ret = of_get_mac_address_mtd(dev->of_node, &mtd_mac); ++ if (ret == -EPROBE_DEFER) ++ return ret; ++ ++ if (is_valid_ether_addr(&mtd_mac)) ++ mac = mtd_mac; ++ } + } + + /* Custom setup (if needed) */ diff --git a/target/linux/ipq806x/patches-4.1/020-add-ap148-bootargs.patch b/target/linux/ipq806x/patches-4.1/020-add-ap148-bootargs.patch new file mode 100644 index 0000000..c0ad74c --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/020-add-ap148-bootargs.patch @@ -0,0 +1,46 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -14,6 +14,14 @@ + }; + }; + ++ alias { ++ serial0 = &uart4; ++ }; ++ ++ chosen { ++ linux,stdout-path = "serial0:115200n8"; ++ }; ++ + soc { + pinmux@800000 { + i2c4_pins: i2c4_pinmux { +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -159,7 +159,7 @@ + + syscon-tcsr = <&tcsr>; + +- serial@12490000 { ++ uart2: serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, + <0x12480000 0x1000>; +@@ -197,7 +197,7 @@ + + syscon-tcsr = <&tcsr>; + +- serial@16340000 { ++ uart4: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; +@@ -234,7 +234,7 @@ + + syscon-tcsr = <&tcsr>; + +- serial@1a240000 { ++ uart5: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, + <0x1a200000 0x1000>; diff --git a/target/linux/ipq806x/patches-4.1/021-add-ap148-partitions.patch b/target/linux/ipq806x/patches-4.1/021-add-ap148-partitions.patch new file mode 100644 index 0000000..bfdb30f --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/021-add-ap148-partitions.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -77,15 +77,7 @@ + spi-max-frequency = <50000000>; + reg = <0>; + +- partition@0 { +- label = "rootfs"; +- reg = <0x0 0x1000000>; +- }; +- +- partition@1 { +- label = "scratch"; +- reg = <0x1000000 0x1000000>; +- }; ++ linux,part-probe = "qcom-smem"; + }; + }; + }; diff --git a/target/linux/ipq806x/patches-4.1/022-add-db149-dts.patch b/target/linux/ipq806x/patches-4.1/022-add-db149-dts.patch new file mode 100644 index 0000000..7d8c8e8 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/022-add-db149-dts.patch @@ -0,0 +1,160 @@ +From f26cc3733bdd697bd81ae505fc133fa7c9b6ea19 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Tue, 7 Apr 2015 19:58:58 -0700 +Subject: [PATCH] ARM: dts: qcom: add initial DB149 device-tree + +Add basic DB149 (IPQ806x based platform) device-tree. It supports UART, +SATA, USB2, USB3 and NOR flash. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/qcom-ipq8064-db149.dts | 132 +++++++++++++++++++++++++++++++ + 2 files changed, 133 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-db149.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -451,6 +451,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8084-ifc6540.dtb \ + qcom-apq8084-mtp.dtb \ + qcom-ipq8064-ap148.dtb \ ++ qcom-ipq8064-db149.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb \ + qcom-msm8974-sony-xperia-honami.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts +@@ -0,0 +1,132 @@ ++#include "qcom-ipq8064-v1.0.dtsi" ++ ++/ { ++ model = "Qualcomm IPQ8064/DB149"; ++ compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ rsvd@41200000 { ++ reg = <0x41200000 0x300000>; ++ no-map; ++ }; ++ }; ++ ++ alias { ++ serial0 = &uart2; ++ }; ++ ++ chosen { ++ linux,stdout-path = "serial0:115200n8"; ++ }; ++ ++ soc { ++ pinmux@800000 { ++ i2c4_pins: i2c4_pinmux { ++ pins = "gpio12", "gpio13"; ++ function = "gsbi4"; ++ bias-disable; ++ }; ++ ++ spi_pins: spi_pins { ++ mux { ++ pins = "gpio18", "gpio19", "gpio21"; ++ function = "gsbi5"; ++ drive-strength = <10>; ++ bias-none; ++ }; ++ }; ++ }; ++ ++ gsbi2: gsbi@12480000 { ++ qcom,mode = ; ++ status = "ok"; ++ uart2: serial@12490000 { ++ status = "ok"; ++ }; ++ }; ++ ++ gsbi5: gsbi@1a200000 { ++ qcom,mode = ; ++ status = "ok"; ++ ++ spi4: spi@1a280000 { ++ status = "ok"; ++ spi-max-frequency = <50000000>; ++ ++ pinctrl-0 = <&spi_pins>; ++ pinctrl-names = "default"; ++ ++ cs-gpios = <&qcom_pinmux 20 0>; ++ ++ flash: m25p80@0 { ++ compatible = "s25fl256s1"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ spi-max-frequency = <50000000>; ++ reg = <0>; ++ m25p,fast-read; ++ ++ partition@0 { ++ label = "lowlevel_init"; ++ reg = <0x0 0x1b0000>; ++ }; ++ ++ partition@1 { ++ label = "u-boot"; ++ reg = <0x1b0000 0x80000>; ++ }; ++ ++ partition@2 { ++ label = "u-boot-env"; ++ reg = <0x230000 0x40000>; ++ }; ++ ++ partition@3 { ++ label = "caldata"; ++ reg = <0x270000 0x40000>; ++ }; ++ ++ partition@4 { ++ label = "firmware"; ++ reg = <0x2b0000 0x1d50000>; ++ }; ++ }; ++ }; ++ }; ++ ++ sata-phy@1b400000 { ++ status = "ok"; ++ }; ++ ++ sata@29000000 { ++ status = "ok"; ++ }; ++ ++ phy@100f8800 { /* USB3 port 1 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@100f8830 { /* USB3 port 1 SS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8800 { /* USB3 port 0 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8830 { /* USB3 port 0 SS phy */ ++ status = "ok"; ++ }; ++ ++ usb30@0 { ++ status = "ok"; ++ }; ++ ++ usb30@1 { ++ status = "ok"; ++ }; ++ }; ++}; diff --git a/target/linux/ipq806x/patches-4.1/023-ARM-dts-ipq806x-Disable-i2c-device-on-gsbi4.patch b/target/linux/ipq806x/patches-4.1/023-ARM-dts-ipq806x-Disable-i2c-device-on-gsbi4.patch new file mode 100644 index 0000000..6b29637 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/023-ARM-dts-ipq806x-Disable-i2c-device-on-gsbi4.patch @@ -0,0 +1,53 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -46,15 +46,12 @@ + serial@16340000 { + status = "ok"; + }; +- +- i2c4: i2c@16380000 { +- status = "ok"; +- +- clock-frequency = <200000>; +- +- pinctrl-0 = <&i2c4_pins>; +- pinctrl-names = "default"; +- }; ++ /* ++ * The i2c device on gsbi4 should not be enabled. ++ * On ipq806x designs gsbi4 i2c is meant for exclusive ++ * RPM usage. Turning this on in kernel manifests as ++ * i2c failure for the RPM. ++ */ + }; + + gsbi5: gsbi@1a200000 { +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -807,7 +807,7 @@ static struct clk_rcg gsbi7_qup_src = { + .parent_names = gcc_pxo_pll8, + .num_parents = 2, + .ops = &clk_rcg_ops, +- .flags = CLK_SET_PARENT_GATE, ++ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -823,7 +823,7 @@ static struct clk_branch gsbi7_qup_clk = + .parent_names = (const char *[]){ "gsbi7_qup_src" }, + .num_parents = 1, + .ops = &clk_branch_ops, +- .flags = CLK_SET_RATE_PARENT, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, + }, + }; +@@ -871,7 +871,7 @@ static struct clk_branch gsbi4_h_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gsbi4_h_clk", + .ops = &clk_branch_ops, +- .flags = CLK_IS_ROOT, ++ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED, + }, + }, + }; diff --git a/target/linux/ipq806x/patches-4.1/024-ap148-add-memory-node.patch b/target/linux/ipq806x/patches-4.1/024-ap148-add-memory-node.patch new file mode 100644 index 0000000..f026ed9 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/024-ap148-add-memory-node.patch @@ -0,0 +1,14 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -4,6 +4,11 @@ + model = "Qualcomm IPQ8064/AP148"; + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + ++ memory@0 { ++ reg = <0x42000000 0x1e000000>; ++ device_type = "memory"; ++ }; ++ + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; diff --git a/target/linux/ipq806x/patches-4.1/030-hwspinlock-core-add-device-tree-support.patch b/target/linux/ipq806x/patches-4.1/030-hwspinlock-core-add-device-tree-support.patch new file mode 100644 index 0000000..04f35b7 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/030-hwspinlock-core-add-device-tree-support.patch @@ -0,0 +1,167 @@ +From fb7737e949e31d8a71acee6bbb670f32dbd2a2c0 Mon Sep 17 00:00:00 2001 +From: Suman Anna +Date: Wed, 4 Mar 2015 20:01:14 -0600 +Subject: [PATCH] hwspinlock/core: add device tree support + +This patch adds a new OF-friendly API of_hwspin_lock_get_id() +for hwspinlock clients to use/request locks from a hwspinlock +device instantiated through a device-tree blob. This new API +can be used by hwspinlock clients to get the id for a specific +lock using the phandle + args specifier, so that it can be +requested using the available hwspin_lock_request_specific() +API. + +Signed-off-by: Suman Anna +Reviewed-by: Bjorn Andersson +[small comment clarification] +Signed-off-by: Ohad Ben-Cohen +--- + Documentation/hwspinlock.txt | 10 +++++ + drivers/hwspinlock/hwspinlock_core.c | 79 ++++++++++++++++++++++++++++++++++++ + include/linux/hwspinlock.h | 7 ++++ + 3 files changed, 96 insertions(+) + +--- a/Documentation/hwspinlock.txt ++++ b/Documentation/hwspinlock.txt +@@ -48,6 +48,16 @@ independent, drivers. + ids for predefined purposes. + Should be called from a process context (might sleep). + ++ int of_hwspin_lock_get_id(struct device_node *np, int index); ++ - retrieve the global lock id for an OF phandle-based specific lock. ++ This function provides a means for DT users of a hwspinlock module ++ to get the global lock id of a specific hwspinlock, so that it can ++ be requested using the normal hwspin_lock_request_specific() API. ++ The function returns a lock id number on success, -EPROBE_DEFER if ++ the hwspinlock device is not yet registered with the core, or other ++ error values. ++ Should be called from a process context (might sleep). ++ + int hwspin_lock_free(struct hwspinlock *hwlock); + - free a previously-assigned hwspinlock; returns 0 on success, or an + appropriate error code on failure (e.g. -EINVAL if the hwspinlock +--- a/drivers/hwspinlock/hwspinlock_core.c ++++ b/drivers/hwspinlock/hwspinlock_core.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include "hwspinlock_internal.h" + +@@ -257,6 +258,84 @@ void __hwspin_unlock(struct hwspinlock * + } + EXPORT_SYMBOL_GPL(__hwspin_unlock); + ++/** ++ * of_hwspin_lock_simple_xlate - translate hwlock_spec to return a lock id ++ * @bank: the hwspinlock device bank ++ * @hwlock_spec: hwlock specifier as found in the device tree ++ * ++ * This is a simple translation function, suitable for hwspinlock platform ++ * drivers that only has a lock specifier length of 1. ++ * ++ * Returns a relative index of the lock within a specified bank on success, ++ * or -EINVAL on invalid specifier cell count. ++ */ ++static inline int ++of_hwspin_lock_simple_xlate(const struct of_phandle_args *hwlock_spec) ++{ ++ if (WARN_ON(hwlock_spec->args_count != 1)) ++ return -EINVAL; ++ ++ return hwlock_spec->args[0]; ++} ++ ++/** ++ * of_hwspin_lock_get_id() - get lock id for an OF phandle-based specific lock ++ * @np: device node from which to request the specific hwlock ++ * @index: index of the hwlock in the list of values ++ * ++ * This function provides a means for DT users of the hwspinlock module to ++ * get the global lock id of a specific hwspinlock using the phandle of the ++ * hwspinlock device, so that it can be requested using the normal ++ * hwspin_lock_request_specific() API. ++ * ++ * Returns the global lock id number on success, -EPROBE_DEFER if the hwspinlock ++ * device is not yet registered, -EINVAL on invalid args specifier value or an ++ * appropriate error as returned from the OF parsing of the DT client node. ++ */ ++int of_hwspin_lock_get_id(struct device_node *np, int index) ++{ ++ struct of_phandle_args args; ++ struct hwspinlock *hwlock; ++ struct radix_tree_iter iter; ++ void **slot; ++ int id; ++ int ret; ++ ++ ret = of_parse_phandle_with_args(np, "hwlocks", "#hwlock-cells", index, ++ &args); ++ if (ret) ++ return ret; ++ ++ /* Find the hwspinlock device: we need its base_id */ ++ ret = -EPROBE_DEFER; ++ rcu_read_lock(); ++ radix_tree_for_each_slot(slot, &hwspinlock_tree, &iter, 0) { ++ hwlock = radix_tree_deref_slot(slot); ++ if (unlikely(!hwlock)) ++ continue; ++ ++ if (hwlock->bank->dev->of_node == args.np) { ++ ret = 0; ++ break; ++ } ++ } ++ rcu_read_unlock(); ++ if (ret < 0) ++ goto out; ++ ++ id = of_hwspin_lock_simple_xlate(&args); ++ if (id < 0 || id >= hwlock->bank->num_locks) { ++ ret = -EINVAL; ++ goto out; ++ } ++ id += hwlock->bank->base_id; ++ ++out: ++ of_node_put(args.np); ++ return ret ? ret : id; ++} ++EXPORT_SYMBOL_GPL(of_hwspin_lock_get_id); ++ + static int hwspin_lock_register_single(struct hwspinlock *hwlock, int id) + { + struct hwspinlock *tmp; +--- a/include/linux/hwspinlock.h ++++ b/include/linux/hwspinlock.h +@@ -26,6 +26,7 @@ + #define HWLOCK_IRQ 0x02 /* Disable interrupts, don't save state */ + + struct device; ++struct device_node; + struct hwspinlock; + struct hwspinlock_device; + struct hwspinlock_ops; +@@ -66,6 +67,7 @@ int hwspin_lock_unregister(struct hwspin + struct hwspinlock *hwspin_lock_request(void); + struct hwspinlock *hwspin_lock_request_specific(unsigned int id); + int hwspin_lock_free(struct hwspinlock *hwlock); ++int of_hwspin_lock_get_id(struct device_node *np, int index); + int hwspin_lock_get_id(struct hwspinlock *hwlock); + int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int, + unsigned long *); +@@ -120,6 +122,11 @@ void __hwspin_unlock(struct hwspinlock * + { + } + ++static inline int of_hwspin_lock_get_id(struct device_node *np, int index) ++{ ++ return 0; ++} ++ + static inline int hwspin_lock_get_id(struct hwspinlock *hwlock) + { + return 0; diff --git a/target/linux/ipq806x/patches-4.1/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch b/target/linux/ipq806x/patches-4.1/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch new file mode 100644 index 0000000..581b199 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/031-hwspinlock-qcom-Add-support-for-Qualcomm-HW-Mutex-bl.patch @@ -0,0 +1,234 @@ +From 19a0f61224d2d91860fa8291ab63cb104ee86bdd Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Tue, 24 Mar 2015 10:11:05 -0700 +Subject: [PATCH] hwspinlock: qcom: Add support for Qualcomm HW Mutex block + +Add driver for Qualcomm Hardware Mutex block found in many Qualcomm +SoCs. + +Based on initial effort by Kumar Gala + +Signed-off-by: Bjorn Andersson +Reviewed-by: Andy Gross +Reviewed-by: Jeffrey Hugo +Signed-off-by: Ohad Ben-Cohen +--- + drivers/hwspinlock/Kconfig | 12 +++ + drivers/hwspinlock/Makefile | 1 + + drivers/hwspinlock/qcom_hwspinlock.c | 181 +++++++++++++++++++++++++++++++++++ + 3 files changed, 194 insertions(+) + create mode 100644 drivers/hwspinlock/qcom_hwspinlock.c + +--- a/drivers/hwspinlock/Kconfig ++++ b/drivers/hwspinlock/Kconfig +@@ -18,6 +18,18 @@ config HWSPINLOCK_OMAP + + If unsure, say N. + ++config HWSPINLOCK_QCOM ++ tristate "Qualcomm Hardware Spinlock device" ++ depends on ARCH_QCOM ++ select HWSPINLOCK ++ select MFD_SYSCON ++ help ++ Say y here to support the Qualcomm Hardware Mutex functionality, which ++ provides a synchronisation mechanism for the various processors on ++ the SoC. ++ ++ If unsure, say N. ++ + config HSEM_U8500 + tristate "STE Hardware Semaphore functionality" + depends on ARCH_U8500 +--- a/drivers/hwspinlock/Makefile ++++ b/drivers/hwspinlock/Makefile +@@ -4,4 +4,5 @@ + + obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o + obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o ++obj-$(CONFIG_HWSPINLOCK_QCOM) += qcom_hwspinlock.o + obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o +--- /dev/null ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -0,0 +1,181 @@ ++/* ++ * Copyright (c) 2013, The Linux Foundation. All rights reserved. ++ * Copyright (c) 2015, Sony Mobile Communications AB ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "hwspinlock_internal.h" ++ ++#define QCOM_MUTEX_APPS_PROC_ID 1 ++#define QCOM_MUTEX_NUM_LOCKS 32 ++ ++static int qcom_hwspinlock_trylock(struct hwspinlock *lock) ++{ ++ struct regmap_field *field = lock->priv; ++ u32 lock_owner; ++ int ret; ++ ++ ret = regmap_field_write(field, QCOM_MUTEX_APPS_PROC_ID); ++ if (ret) ++ return ret; ++ ++ ret = regmap_field_read(field, &lock_owner); ++ if (ret) ++ return ret; ++ ++ return lock_owner == QCOM_MUTEX_APPS_PROC_ID; ++} ++ ++static void qcom_hwspinlock_unlock(struct hwspinlock *lock) ++{ ++ struct regmap_field *field = lock->priv; ++ u32 lock_owner; ++ int ret; ++ ++ ret = regmap_field_read(field, &lock_owner); ++ if (ret) { ++ pr_err("%s: unable to query spinlock owner\n", __func__); ++ return; ++ } ++ ++ if (lock_owner != QCOM_MUTEX_APPS_PROC_ID) { ++ pr_err("%s: spinlock not owned by us (actual owner is %d)\n", ++ __func__, lock_owner); ++ } ++ ++ ret = regmap_field_write(field, 0); ++ if (ret) ++ pr_err("%s: failed to unlock spinlock\n", __func__); ++} ++ ++static const struct hwspinlock_ops qcom_hwspinlock_ops = { ++ .trylock = qcom_hwspinlock_trylock, ++ .unlock = qcom_hwspinlock_unlock, ++}; ++ ++static const struct of_device_id qcom_hwspinlock_of_match[] = { ++ { .compatible = "qcom,sfpb-mutex" }, ++ { .compatible = "qcom,tcsr-mutex" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match); ++ ++static int qcom_hwspinlock_probe(struct platform_device *pdev) ++{ ++ struct hwspinlock_device *bank; ++ struct device_node *syscon; ++ struct reg_field field; ++ struct regmap *regmap; ++ size_t array_size; ++ u32 stride; ++ u32 base; ++ int ret; ++ int i; ++ ++ syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0); ++ if (!syscon) { ++ dev_err(&pdev->dev, "no syscon property\n"); ++ return -ENODEV; ++ } ++ ++ regmap = syscon_node_to_regmap(syscon); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no offset in syscon\n"); ++ return -EINVAL; ++ } ++ ++ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "no stride syscon\n"); ++ return -EINVAL; ++ } ++ ++ array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock); ++ bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL); ++ if (!bank) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, bank); ++ ++ for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { ++ field.reg = base + i * stride; ++ field.lsb = 0; ++ field.msb = 32; ++ ++ bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, ++ regmap, field); ++ } ++ ++ pm_runtime_enable(&pdev->dev); ++ ++ ret = hwspin_lock_register(bank, &pdev->dev, &qcom_hwspinlock_ops, ++ 0, QCOM_MUTEX_NUM_LOCKS); ++ if (ret) ++ pm_runtime_disable(&pdev->dev); ++ ++ return ret; ++} ++ ++static int qcom_hwspinlock_remove(struct platform_device *pdev) ++{ ++ struct hwspinlock_device *bank = platform_get_drvdata(pdev); ++ int ret; ++ ++ ret = hwspin_lock_unregister(bank); ++ if (ret) { ++ dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static struct platform_driver qcom_hwspinlock_driver = { ++ .probe = qcom_hwspinlock_probe, ++ .remove = qcom_hwspinlock_remove, ++ .driver = { ++ .name = "qcom_hwspinlock", ++ .of_match_table = qcom_hwspinlock_of_match, ++ }, ++}; ++ ++static int __init qcom_hwspinlock_init(void) ++{ ++ return platform_driver_register(&qcom_hwspinlock_driver); ++} ++/* board init code might need to reserve hwspinlocks for predefined purposes */ ++postcore_initcall(qcom_hwspinlock_init); ++ ++static void __exit qcom_hwspinlock_exit(void) ++{ ++ platform_driver_unregister(&qcom_hwspinlock_driver); ++} ++module_exit(qcom_hwspinlock_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Hardware spinlock driver for Qualcomm SoCs"); diff --git a/target/linux/ipq806x/patches-4.1/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch b/target/linux/ipq806x/patches-4.1/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch new file mode 100644 index 0000000..70d5a58 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/032-hwspinlock-qcom-Correct-msb-in-regmap_field.patch @@ -0,0 +1,26 @@ +From bd5717a4632cdecafe82d03de7dcb3b1876e2828 Mon Sep 17 00:00:00 2001 +From: Bjorn Andersson +Date: Fri, 26 Jun 2015 14:47:21 -0700 +Subject: [PATCH] hwspinlock: qcom: Correct msb in regmap_field + +msb of the regmap_field was mistakenly given the value 32, to set all bits +in the regmap update mask; although incorrect this worked until 921cc294, +where the mask calculation was corrected. + +Signed-off-by: Bjorn Andersson +Signed-off-by: Ohad Ben-Cohen +--- + drivers/hwspinlock/qcom_hwspinlock.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwspinlock/qcom_hwspinlock.c ++++ b/drivers/hwspinlock/qcom_hwspinlock.c +@@ -123,7 +123,7 @@ static int qcom_hwspinlock_probe(struct + for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) { + field.reg = base + i * stride; + field.lsb = 0; +- field.msb = 32; ++ field.msb = 31; + + bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev, + regmap, field); diff --git a/target/linux/ipq806x/patches-4.1/033-ARM-qcom-add-SFPB-nodes-to-IPQ806x-dts.patch b/target/linux/ipq806x/patches-4.1/033-ARM-qcom-add-SFPB-nodes-to-IPQ806x-dts.patch new file mode 100644 index 0000000..a126d69 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/033-ARM-qcom-add-SFPB-nodes-to-IPQ806x-dts.patch @@ -0,0 +1,33 @@ +From c7c482da19a5e4ba7101198c21c2434056b0b2da Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Thu, 13 Aug 2015 09:45:26 -0700 +Subject: [PATCH 1/3] ARM: qcom: add SFPB nodes to IPQ806x dts + +Add one new node to the ipq806x.dtsi file to declare & register the +hardware spinlock devices. This mechanism is required to be used by +other drivers such as SMEM. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -329,5 +329,16 @@ + #reset-cells = <1>; + }; + ++ sfpb_mutex_block: syscon@1200600 { ++ compatible = "syscon"; ++ reg = <0x01200600 0x100>; ++ }; + }; ++ ++ sfpb_mutex: sfpb-mutex { ++ compatible = "qcom,sfpb-mutex"; ++ syscon = <&sfpb_mutex_block 4 4>; ++ ++ #hwlock-cells = <1>; ++ }; + }; diff --git a/target/linux/ipq806x/patches-4.1/034-soc-qcom-Add-device-tree-binding-for-SMEM.patch b/target/linux/ipq806x/patches-4.1/034-soc-qcom-Add-device-tree-binding-for-SMEM.patch new file mode 100644 index 0000000..d22db22 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/034-soc-qcom-Add-device-tree-binding-for-SMEM.patch @@ -0,0 +1,82 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,1/2] soc: qcom: Add device tree binding for SMEM +From: Bjorn Andersson +X-Patchwork-Id: 6202201 +Message-Id: <1428795178-24312-1-git-send-email-bjorn.andersson@sonymobile.com> +To: Rob Herring , Pawel Moll , + Mark Rutland , + Ian Campbell , + Kumar Gala , Jeffrey Hugo , + Andry Gross +Cc: , + linux-arm-msm , + +Date: Sat, 11 Apr 2015 16:32:57 -0700 + +Add device tree binding documentation for the Qualcom Shared Memory +manager. + +Signed-off-by: Bjorn Andersson + +--- +Changes since v1: +- None + + .../devicetree/bindings/soc/qcom/qcom,smem.txt | 49 ++++++++++++++++++++++ + 1 file changed, 49 insertions(+) + create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smem.txt +@@ -0,0 +1,49 @@ ++Qualcomm Shared Memory binding ++ ++This binding describes the Qualcomm Shared Memory, used to share data between ++various subsystems and OSes in Qualcomm platforms. ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: must be: ++ "qcom,smem" ++ ++- memory-region: ++ Usage: required ++ Value type: ++ Definition: handle to memory reservation for main smem memory region. ++ ++- reg: ++ Usage: optional ++ Value type: ++ Definition: base address and size pair for any additional memory areas ++ of the shared memory. ++ ++- hwspinlocks: ++ Usage: required ++ Value type: ++ Definition: reference to a hwspinlock used to protect allocations from ++ the shared memory ++ ++= EXAMPLE ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ smem_region: smem@fa00000 { ++ reg = <0xfa00000 0x200000>; ++ no-map; ++ }; ++ }; ++ ++ smem@fa00000 { ++ compatible = "qcom,smem"; ++ ++ memory-region = <&smem_region>; ++ reg = <0xfc428000 0x4000>; ++ ++ hwlocks = <&tcsr_mutex 3>; ++ }; diff --git a/target/linux/ipq806x/patches-4.1/035-soc-qcom-Add-Shared-Memory-Manager-driver.patch b/target/linux/ipq806x/patches-4.1/035-soc-qcom-Add-Shared-Memory-Manager-driver.patch new file mode 100644 index 0000000..5598da2 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/035-soc-qcom-Add-Shared-Memory-Manager-driver.patch @@ -0,0 +1,841 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,2/2] soc: qcom: Add Shared Memory Manager driver +From: Bjorn Andersson +X-Patchwork-Id: 6202211 +Message-Id: <1428795178-24312-2-git-send-email-bjorn.andersson@sonymobile.com> +To: Kumar Gala , Andy Gross , + David Brown , Jeffrey Hugo +Cc: , , + +Date: Sat, 11 Apr 2015 16:32:58 -0700 + +The Shared Memory Manager driver implements an interface for allocating +and accessing items in the memory area shared among all of the +processors in a Qualcomm platform. + +Signed-off-by: Bjorn Andersson +Reviewed-by: Andy Gross +Tested-by: Andy Gross + +--- +Changes since v1: +- ioremapping the regions nocache +- improved documentation of the two regions of partitions +- corrected free space check in private allocator + + drivers/soc/qcom/Kconfig | 7 + + drivers/soc/qcom/Makefile | 1 + + drivers/soc/qcom/smem.c | 768 ++++++++++++++++++++++++++++++++++++++++++ + include/linux/soc/qcom/smem.h | 14 + + 4 files changed, 790 insertions(+) + create mode 100644 drivers/soc/qcom/smem.c + create mode 100644 include/linux/soc/qcom/smem.h + +--- a/drivers/soc/qcom/Kconfig ++++ b/drivers/soc/qcom/Kconfig +@@ -10,3 +10,10 @@ config QCOM_GSBI + functions for connecting the underlying serial UART, SPI, and I2C + devices to the output pins. + ++config QCOM_SMEM ++ tristate "Qualcomm Shared Memory Manager (SMEM)" ++ depends on ARCH_QCOM ++ help ++ Say y here to enable support for the Qualcomm Shared Memory Manager. ++ The driver provides an interface to items in a heap shared among all ++ processors in a Qualcomm platform. +--- a/drivers/soc/qcom/Makefile ++++ b/drivers/soc/qcom/Makefile +@@ -1 +1,2 @@ + obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o ++obj-$(CONFIG_QCOM_SMEM) += smem.o +--- /dev/null ++++ b/drivers/soc/qcom/smem.c +@@ -0,0 +1,768 @@ ++/* ++ * Copyright (c) 2015, Sony Mobile Communications AB. ++ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * The Qualcomm shared memory system is a allocate only heap structure that ++ * consists of one of more memory areas that can be accessed by the processors ++ * in the SoC. ++ * ++ * All systems contains a global heap, accessible by all processors in the SoC, ++ * with a table of contents data structure (@smem_header) at the beginning of ++ * the main shared memory block. ++ * ++ * The global header contains metadata for allocations as well as a fixed list ++ * of 512 entries (@smem_global_entry) that can be initialized to reference ++ * parts of the shared memory space. ++ * ++ * ++ * In addition to this global heap a set of "private" heaps can be set up at ++ * boot time with access restrictions so that only certain processor pairs can ++ * access the data. ++ * ++ * These partitions are referenced from an optional partition table ++ * (@smem_ptable), that is found 4kB from the end of the main smem region. The ++ * partition table entries (@smem_ptable_entry) lists the involved processors ++ * (or hosts) and their location in the main shared memory region. ++ * ++ * Each partition starts with a header (@smem_partition_header) that identifies ++ * the partition and holds properties for the two internal memory regions. The ++ * two regions are cached and non-cached memory respectively. Each region ++ * contain a link list of allocation headers (@smem_private_entry) followed by ++ * their data. ++ * ++ * Items in the non-cached region are allocated from the start of the partition ++ * while items in the cached region are allocated from the end. The free area ++ * is hence the region between the cached and non-cached offsets. ++ * ++ * ++ * To synchronize allocations in the shared memory heaps a remote spinlock must ++ * be held - currently lock number 3 of the sfpb or tcsr is used for this on all ++ * platforms. ++ * ++ */ ++ ++/** ++ * struct smem_proc_comm - proc_comm communication struct (legacy) ++ * @command: current command to be executed ++ * @status: status of the currently requested command ++ * @params: parameters to the command ++ */ ++struct smem_proc_comm { ++ u32 command; ++ u32 status; ++ u32 params[2]; ++}; ++ ++/** ++ * struct smem_global_entry - entry to reference smem items on the heap ++ * @allocated: boolean to indicate if this entry is used ++ * @offset: offset to the allocated space ++ * @size: size of the allocated space, 8 byte aligned ++ * @aux_base: base address for the memory region used by this unit, or 0 for ++ * the default region. bits 0,1 are reserved ++ */ ++struct smem_global_entry { ++ u32 allocated; ++ u32 offset; ++ u32 size; ++ u32 aux_base; /* bits 1:0 reserved */ ++}; ++#define AUX_BASE_MASK 0xfffffffc ++ ++/** ++ * struct smem_header - header found in beginning of primary smem region ++ * @proc_comm: proc_comm communication interface (legacy) ++ * @version: array of versions for the various subsystems ++ * @initialized: boolean to indicate that smem is initialized ++ * @free_offset: index of the first unallocated byte in smem ++ * @available: number of bytes available for allocation ++ * @reserved: reserved field, must be 0 ++ * toc: array of references to items ++ */ ++struct smem_header { ++ struct smem_proc_comm proc_comm[4]; ++ u32 version[32]; ++ u32 initialized; ++ u32 free_offset; ++ u32 available; ++ u32 reserved; ++ struct smem_global_entry toc[]; ++}; ++ ++/** ++ * struct smem_ptable_entry - one entry in the @smem_ptable list ++ * @offset: offset, within the main shared memory region, of the partition ++ * @size: size of the partition ++ * @flags: flags for the partition (currently unused) ++ * @host0: first processor/host with access to this partition ++ * @host1: second processor/host with access to this partition ++ * @reserved: reserved entries for later use ++ */ ++struct smem_ptable_entry { ++ u32 offset; ++ u32 size; ++ u32 flags; ++ u16 host0; ++ u16 host1; ++ u32 reserved[8]; ++}; ++ ++/** ++ * struct smem_ptable - partition table for the private partitions ++ * @magic: magic number, must be SMEM_PTABLE_MAGIC ++ * @version: version of the partition table ++ * @num_entries: number of partitions in the table ++ * @reserved: for now reserved entries ++ * @entry: list of @smem_ptable_entry for the @num_entries partitions ++ */ ++struct smem_ptable { ++ u32 magic; ++ u32 version; ++ u32 num_entries; ++ u32 reserved[5]; ++ struct smem_ptable_entry entry[]; ++}; ++#define SMEM_PTABLE_MAGIC 0x434f5424 /* "$TOC" */ ++ ++/** ++ * struct smem_partition_header - header of the partitions ++ * @magic: magic number, must be SMEM_PART_MAGIC ++ * @host0: first processor/host with access to this partition ++ * @host1: second processor/host with access to this partition ++ * @size: size of the partition ++ * @offset_free_uncached: offset to the first free byte of uncached memory in ++ * this partition ++ * @offset_free_cached: offset to the first free byte of cached memory in this ++ * partition ++ * @reserved: for now reserved entries ++ */ ++struct smem_partition_header { ++ u32 magic; ++ u16 host0; ++ u16 host1; ++ u32 size; ++ u32 offset_free_uncached; ++ u32 offset_free_cached; ++ u32 reserved[3]; ++}; ++#define SMEM_PART_MAGIC 0x54525024 /* "$PRT" */ ++ ++/** ++ * struct smem_private_entry - header of each item in the private partition ++ * @canary: magic number, must be SMEM_PRIVATE_CANARY ++ * @item: identifying number of the smem item ++ * @size: size of the data, including padding bytes ++ * @padding_data: number of bytes of padding of data ++ * @padding_hdr: number of bytes of padding between the header and the data ++ * @reserved: for now reserved entry ++ */ ++struct smem_private_entry { ++ u16 canary; ++ u16 item; ++ u32 size; /* includes padding bytes */ ++ u16 padding_data; ++ u16 padding_hdr; ++ u32 reserved; ++}; ++#define SMEM_PRIVATE_CANARY 0xa5a5 ++ ++/* ++ * Item 3 of the global heap contains an array of versions for the various ++ * software components in the SoC. We verify that the boot loader version is ++ * what the expected version (SMEM_EXPECTED_VERSION) as a sanity check. ++ */ ++#define SMEM_ITEM_VERSION 3 ++#define SMEM_MASTER_SBL_VERSION_INDEX 7 ++#define SMEM_EXPECTED_VERSION 11 ++ ++/* ++ * The first 8 items are only to be allocated by the boot loader while ++ * initializing the heap. ++ */ ++#define SMEM_ITEM_LAST_FIXED 8 ++ ++/* Highest accepted item number, for both global and private heaps */ ++#define SMEM_ITEM_LAST 512 ++ ++/* Processor/host identifier for the application processor */ ++#define SMEM_HOST_APPS 0 ++ ++/* Max number of processors/hosts in a system */ ++#define SMEM_HOST_COUNT 7 ++ ++/** ++ * struct smem_region - representation of a chunk of memory used for smem ++ * @aux_base: identifier of aux_mem base ++ * @virt_base: virtual base address of memory with this aux_mem identifier ++ * @size: size of the memory region ++ */ ++struct smem_region { ++ u32 aux_base; ++ void __iomem *virt_base; ++ size_t size; ++}; ++ ++/** ++ * struct qcom_smem - device data for the smem device ++ * @dev: device pointer ++ * @hwlock: reference to a hwspinlock ++ * @partitions: list of pointers to partitions affecting the current ++ * processor/host ++ * @num_regions: number of @regions ++ * @regions: list of the memory regions defining the shared memory ++ */ ++struct qcom_smem { ++ struct device *dev; ++ ++ struct hwspinlock *hwlock; ++ ++ struct smem_partition_header *partitions[SMEM_HOST_COUNT]; ++ ++ unsigned num_regions; ++ struct smem_region regions[0]; ++}; ++ ++/* Pointer to the one and only smem handle */ ++static struct qcom_smem *__smem; ++ ++/* Timeout (ms) for the trylock of remote spinlocks */ ++#define HWSPINLOCK_TIMEOUT 1000 ++ ++static int qcom_smem_alloc_private(struct qcom_smem *smem, ++ unsigned host, ++ unsigned item, ++ size_t size) ++{ ++ struct smem_partition_header *phdr; ++ struct smem_private_entry *hdr; ++ size_t alloc_size; ++ void *p; ++ ++ /* We're not going to find it if there's no matching partition */ ++ if (host >= SMEM_HOST_COUNT || !smem->partitions[host]) ++ return -ENOENT; ++ ++ phdr = smem->partitions[host]; ++ ++ p = (void *)phdr + sizeof(*phdr); ++ while (p < (void *)phdr + phdr->offset_free_uncached) { ++ hdr = p; ++ ++ if (hdr->canary != SMEM_PRIVATE_CANARY) { ++ dev_err(smem->dev, ++ "Found invalid canary in host %d partition\n", ++ host); ++ return -EINVAL; ++ } ++ ++ if (hdr->item == item) ++ return -EEXIST; ++ ++ p += sizeof(*hdr) + hdr->padding_hdr + hdr->size; ++ } ++ ++ /* Check that we don't grow into the cached region */ ++ alloc_size = sizeof(*hdr) + ALIGN(size, 8); ++ if (p + alloc_size >= (void *)phdr + phdr->offset_free_cached) { ++ dev_err(smem->dev, "Out of memory\n"); ++ return -ENOSPC; ++ } ++ ++ hdr = p; ++ hdr->canary = SMEM_PRIVATE_CANARY; ++ hdr->item = item; ++ hdr->size = ALIGN(size, 8); ++ hdr->padding_data = hdr->size - size; ++ hdr->padding_hdr = 0; ++ ++ /* ++ * Ensure the header is written before we advance the free offset, so ++ * that remote processors that does not take the remote spinlock still ++ * gets a consistent view of the linked list. ++ */ ++ wmb(); ++ phdr->offset_free_uncached += alloc_size; ++ ++ return 0; ++} ++ ++static int qcom_smem_alloc_global(struct qcom_smem *smem, ++ unsigned item, ++ size_t size) ++{ ++ struct smem_header *header; ++ struct smem_global_entry *entry; ++ ++ if (WARN_ON(item >= SMEM_ITEM_LAST)) ++ return -EINVAL; ++ ++ header = smem->regions[0].virt_base; ++ entry = &header->toc[item]; ++ if (entry->allocated) ++ return -EEXIST; ++ ++ size = ALIGN(size, 8); ++ if (WARN_ON(size > header->available)) ++ return -ENOMEM; ++ ++ entry->offset = header->free_offset; ++ entry->size = size; ++ ++ /* ++ * Ensure the header is consistent before we mark the item allocated, ++ * so that remote processors will get a consistent view of the item ++ * even though they do not take the spinlock on read. ++ */ ++ wmb(); ++ entry->allocated = 1; ++ ++ header->free_offset += size; ++ header->available -= size; ++ ++ return 0; ++} ++ ++/** ++ * qcom_smem_alloc - allocate space for a smem item ++ * @host: remote processor id, or -1 ++ * @item: smem item handle ++ * @size: number of bytes to be allocated ++ * ++ * Allocate space for a given smem item of size @size, given that the item is ++ * not yet allocated. ++ */ ++int qcom_smem_alloc(unsigned host, unsigned item, size_t size) ++{ ++ unsigned long flags; ++ int ret; ++ ++ if (!__smem) ++ return -EPROBE_DEFER; ++ ++ if (item < SMEM_ITEM_LAST_FIXED) { ++ dev_err(__smem->dev, ++ "Rejecting allocation of static entry %d\n", item); ++ return -EINVAL; ++ } ++ ++ ret = hwspin_lock_timeout_irqsave(__smem->hwlock, ++ HWSPINLOCK_TIMEOUT, ++ &flags); ++ if (ret) ++ return ret; ++ ++ ret = qcom_smem_alloc_private(__smem, host, item, size); ++ if (ret == -ENOENT) ++ ret = qcom_smem_alloc_global(__smem, item, size); ++ ++ hwspin_unlock_irqrestore(__smem->hwlock, &flags); ++ ++ return ret; ++} ++EXPORT_SYMBOL(qcom_smem_alloc); ++ ++static int qcom_smem_get_global(struct qcom_smem *smem, ++ unsigned item, ++ void **ptr, ++ size_t *size) ++{ ++ struct smem_header *header; ++ struct smem_region *area; ++ struct smem_global_entry *entry; ++ u32 aux_base; ++ unsigned i; ++ ++ if (WARN_ON(item >= SMEM_ITEM_LAST)) ++ return -EINVAL; ++ ++ header = smem->regions[0].virt_base; ++ entry = &header->toc[item]; ++ if (!entry->allocated) ++ return -ENXIO; ++ ++ if (ptr != NULL) { ++ aux_base = entry->aux_base & AUX_BASE_MASK; ++ ++ for (i = 0; i < smem->num_regions; i++) { ++ area = &smem->regions[i]; ++ ++ if (area->aux_base == aux_base || !aux_base) { ++ *ptr = area->virt_base + entry->offset; ++ break; ++ } ++ } ++ } ++ if (size != NULL) ++ *size = entry->size; ++ ++ return 0; ++} ++ ++static int qcom_smem_get_private(struct qcom_smem *smem, ++ unsigned host, ++ unsigned item, ++ void **ptr, ++ size_t *size) ++{ ++ struct smem_partition_header *phdr; ++ struct smem_private_entry *hdr; ++ void *p; ++ ++ /* We're not going to find it if there's no matching partition */ ++ if (host >= SMEM_HOST_COUNT || !smem->partitions[host]) ++ return -ENOENT; ++ ++ phdr = smem->partitions[host]; ++ ++ p = (void *)phdr + sizeof(*phdr); ++ while (p < (void *)phdr + phdr->offset_free_uncached) { ++ hdr = p; ++ ++ if (hdr->canary != SMEM_PRIVATE_CANARY) { ++ dev_err(smem->dev, ++ "Found invalid canary in host %d partition\n", ++ host); ++ return -EINVAL; ++ } ++ ++ if (hdr->item == item) { ++ if (ptr != NULL) ++ *ptr = p + sizeof(*hdr) + hdr->padding_hdr; ++ ++ if (size != NULL) ++ *size = hdr->size - hdr->padding_data; ++ ++ return 0; ++ } ++ ++ p += sizeof(*hdr) + hdr->padding_hdr + hdr->size; ++ } ++ ++ return -ENOENT; ++} ++ ++/** ++ * qcom_smem_get - resolve ptr of size of a smem item ++ * @host: the remote processor, or -1 ++ * @item: smem item handle ++ * @ptr: pointer to be filled out with address of the item ++ * @size: pointer to be filled out with size of the item ++ * ++ * Looks up pointer and size of a smem item. ++ */ ++int qcom_smem_get(unsigned host, unsigned item, void **ptr, size_t *size) ++{ ++ unsigned long flags; ++ int ret; ++ ++ if (!__smem) ++ return -EPROBE_DEFER; ++ ++ ret = hwspin_lock_timeout_irqsave(__smem->hwlock, ++ HWSPINLOCK_TIMEOUT, ++ &flags); ++ if (ret) ++ return ret; ++ ++ ret = qcom_smem_get_private(__smem, host, item, ptr, size); ++ if (ret == -ENOENT) ++ ret = qcom_smem_get_global(__smem, item, ptr, size); ++ ++ hwspin_unlock_irqrestore(__smem->hwlock, &flags); ++ return ret; ++ ++} ++EXPORT_SYMBOL(qcom_smem_get); ++ ++/** ++ * qcom_smem_get_free_space - retrieve amont of free space in a partition ++ * @host: the remote processor identifing a partition, or -1 ++ * ++ * To be used by smem clients as a quick way to determine if any new ++ * allocations has been made. ++ */ ++int qcom_smem_get_free_space(unsigned host) ++{ ++ struct smem_partition_header *phdr; ++ struct smem_header *header; ++ unsigned ret; ++ ++ if (!__smem) ++ return -EPROBE_DEFER; ++ ++ if (host < SMEM_HOST_COUNT && __smem->partitions[host]) { ++ phdr = __smem->partitions[host]; ++ ret = phdr->offset_free_uncached; ++ } else { ++ header = __smem->regions[0].virt_base; ++ ret = header->available; ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL(qcom_smem_get_free_space); ++ ++static int qcom_smem_get_sbl_version(struct qcom_smem *smem) ++{ ++ unsigned *versions; ++ size_t size; ++ int ret; ++ ++ ret = qcom_smem_get_global(smem, SMEM_ITEM_VERSION, ++ (void **)&versions, &size); ++ if (ret < 0) { ++ dev_err(smem->dev, "Unable to read the version item\n"); ++ return -ENOENT; ++ } ++ ++ if (size < sizeof(unsigned) * SMEM_MASTER_SBL_VERSION_INDEX) { ++ dev_err(smem->dev, "Version item is too small\n"); ++ return -EINVAL; ++ } ++ ++ return versions[SMEM_MASTER_SBL_VERSION_INDEX]; ++} ++ ++static int qcom_smem_enumerate_partitions(struct qcom_smem *smem, ++ unsigned local_host) ++{ ++ struct smem_partition_header *header; ++ struct smem_ptable_entry *entry; ++ struct smem_ptable *ptable; ++ unsigned remote_host; ++ int i; ++ ++ ptable = smem->regions[0].virt_base + smem->regions[0].size - 4 * 1024; ++ if (ptable->magic != SMEM_PTABLE_MAGIC) ++ return 0; ++ ++ if (ptable->version != 1) { ++ dev_err(smem->dev, ++ "Unsupported partition header version %d\n", ++ ptable->version); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < ptable->num_entries; i++) { ++ entry = &ptable->entry[i]; ++ ++ if (entry->host0 != local_host && entry->host1 != local_host) ++ continue; ++ ++ if (!entry->offset) ++ continue; ++ ++ if (!entry->size) ++ continue; ++ ++ if (entry->host0 == local_host) ++ remote_host = entry->host1; ++ else ++ remote_host = entry->host0; ++ ++ if (smem->partitions[remote_host]) { ++ dev_err(smem->dev, ++ "Already found a partition for host %d\n", ++ remote_host); ++ return -EINVAL; ++ } ++ ++ header = smem->regions[0].virt_base + entry->offset; ++ ++ if (header->magic != SMEM_PART_MAGIC) { ++ dev_err(smem->dev, ++ "Partition %d has invalid magic\n", i); ++ return -EINVAL; ++ } ++ ++ if (header->host0 != local_host && header->host1 != local_host) { ++ dev_err(smem->dev, ++ "Partition %d hosts are invalid\n", i); ++ return -EINVAL; ++ } ++ ++ if (header->host0 != remote_host && header->host1 != remote_host) { ++ dev_err(smem->dev, ++ "Partition %d hosts are invalid\n", i); ++ return -EINVAL; ++ } ++ ++ if (header->size != entry->size) { ++ dev_err(smem->dev, ++ "Partition %d has invalid size\n", i); ++ return -EINVAL; ++ } ++ ++ if (header->offset_free_uncached > header->size) { ++ dev_err(smem->dev, ++ "Partition %d has invalid free pointer\n", i); ++ return -EINVAL; ++ } ++ ++ smem->partitions[remote_host] = header; ++ } ++ ++ return 0; ++} ++ ++static int qcom_smem_count_mem_regions(struct platform_device *pdev) ++{ ++ struct resource *res; ++ int num_regions = 0; ++ int i; ++ ++ for (i = 0; i < pdev->num_resources; i++) { ++ res = &pdev->resource[i]; ++ ++ if (resource_type(res) == IORESOURCE_MEM) ++ num_regions++; ++ } ++ ++ return num_regions; ++} ++ ++static int qcom_smem_probe(struct platform_device *pdev) ++{ ++ struct smem_header *header; ++ struct device_node *np; ++ struct qcom_smem *smem; ++ struct resource *res; ++ struct resource r; ++ size_t array_size; ++ int num_regions = 0; ++ int hwlock_id; ++ u32 version; ++ int ret; ++ int i; ++ ++ num_regions = qcom_smem_count_mem_regions(pdev) + 1; ++ ++ array_size = num_regions * sizeof(struct smem_region); ++ smem = devm_kzalloc(&pdev->dev, sizeof(*smem) + array_size, GFP_KERNEL); ++ if (!smem) ++ return -ENOMEM; ++ ++ smem->dev = &pdev->dev; ++ smem->num_regions = num_regions; ++ ++ np = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); ++ if (!np) { ++ dev_err(&pdev->dev, "No memory-region specified\n"); ++ return -EINVAL; ++ } ++ ++ ret = of_address_to_resource(np, 0, &r); ++ of_node_put(np); ++ if (ret) ++ return ret; ++ ++ smem->regions[0].aux_base = (u32)r.start; ++ smem->regions[0].size = resource_size(&r); ++ smem->regions[0].virt_base = devm_ioremap_nocache(&pdev->dev, ++ r.start, ++ resource_size(&r)); ++ if (!smem->regions[0].virt_base) ++ return -ENOMEM; ++ ++ for (i = 1; i < num_regions; i++) { ++ res = platform_get_resource(pdev, IORESOURCE_MEM, i - 1); ++ ++ smem->regions[i].aux_base = (u32)res->start; ++ smem->regions[i].size = resource_size(res); ++ smem->regions[i].virt_base = devm_ioremap_nocache(&pdev->dev, ++ res->start, ++ resource_size(res)); ++ if (!smem->regions[i].virt_base) ++ return -ENOMEM; ++ } ++ ++ header = smem->regions[0].virt_base; ++ if (header->initialized != 1 || header->reserved) { ++ dev_err(&pdev->dev, "SMEM is not initilized by SBL\n"); ++ return -EINVAL; ++ } ++ ++ version = qcom_smem_get_sbl_version(smem); ++ if (version >> 16 != SMEM_EXPECTED_VERSION) { ++ dev_err(&pdev->dev, "Unsupported smem version 0x%x\n", version); ++ return -EINVAL; ++ } ++ ++ ret = qcom_smem_enumerate_partitions(smem, SMEM_HOST_APPS); ++ if (ret < 0) ++ return ret; ++ ++ hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); ++ if (hwlock_id < 0) { ++ dev_err(&pdev->dev, "failed to retrieve hwlock\n"); ++ return hwlock_id; ++ } ++ ++ smem->hwlock = hwspin_lock_request_specific(hwlock_id); ++ if (!smem->hwlock) ++ return -ENXIO; ++ ++ __smem = smem; ++ ++ return 0; ++} ++ ++static int qcom_smem_remove(struct platform_device *pdev) ++{ ++ hwspin_lock_free(__smem->hwlock); ++ __smem = NULL; ++ ++ return 0; ++} ++ ++static const struct of_device_id qcom_smem_of_match[] = { ++ { .compatible = "qcom,smem" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, qcom_smem_of_match); ++ ++static struct platform_driver qcom_smem_driver = { ++ .probe = qcom_smem_probe, ++ .remove = qcom_smem_remove, ++ .driver = { ++ .name = "qcom_smem", ++ .of_match_table = qcom_smem_of_match, ++ .suppress_bind_attrs = true, ++ }, ++}; ++ ++static int __init qcom_smem_init(void) ++{ ++ return platform_driver_register(&qcom_smem_driver); ++} ++arch_initcall(qcom_smem_init); ++ ++static void __exit qcom_smem_exit(void) ++{ ++ platform_driver_unregister(&qcom_smem_driver); ++} ++module_exit(qcom_smem_exit) ++ ++MODULE_AUTHOR("Bjorn Andersson "); ++MODULE_DESCRIPTION("Qualcomm Shared Memory Manager"); ++MODULE_LICENSE("GPLv2"); +--- /dev/null ++++ b/include/linux/soc/qcom/smem.h +@@ -0,0 +1,14 @@ ++#ifndef __QCOM_SMEM_H__ ++#define __QCOM_SMEM_H__ ++ ++struct device_node; ++struct qcom_smem; ++ ++#define QCOM_SMEM_HOST_ANY -1 ++ ++int qcom_smem_alloc(unsigned host, unsigned item, size_t size); ++int qcom_smem_get(unsigned host, unsigned item, void **ptr, size_t *size); ++ ++int qcom_smem_get_free_space(unsigned host); ++ ++#endif diff --git a/target/linux/ipq806x/patches-4.1/036-ARM-qcom-add-SMEM-device-node-to-IPQ806x-dts.patch b/target/linux/ipq806x/patches-4.1/036-ARM-qcom-add-SMEM-device-node-to-IPQ806x-dts.patch new file mode 100644 index 0000000..b55f174 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/036-ARM-qcom-add-SMEM-device-node-to-IPQ806x-dts.patch @@ -0,0 +1,36 @@ +From f212be3a6134db8dd7c5f6f0987536a669401fae Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 14 Aug 2015 11:17:20 -0700 +Subject: [PATCH 2/3] ARM: qcom: add SMEM device node to IPQ806x dts + +SMEM is used on IPQ806x to store various board related information such +as boot device and flash partition layout. We'll declare it as a device +so we can make use of it thanks to the new SMEM soc driver. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -55,7 +55,7 @@ + no-map; + }; + +- smem@41000000 { ++ smem: smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; +@@ -341,4 +341,10 @@ + + #hwlock-cells = <1>; + }; ++ ++ smem { ++ compatible = "qcom,smem"; ++ memory-region = <&smem>; ++ hwlocks = <&sfpb_mutex 3>; ++ }; + }; diff --git a/target/linux/ipq806x/patches-4.1/037-mtd-add-SMEM-parser-for-QCOM-platforms.patch b/target/linux/ipq806x/patches-4.1/037-mtd-add-SMEM-parser-for-QCOM-platforms.patch new file mode 100644 index 0000000..5fc5413 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/037-mtd-add-SMEM-parser-for-QCOM-platforms.patch @@ -0,0 +1,277 @@ +From 0501f76b138cf1dc11a313bb7a094da524b79337 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Thu, 13 Aug 2015 09:53:14 -0700 +Subject: [PATCH 3/3] mtd: add SMEM parser for QCOM platforms + +On QCOM platforms using MTD devices storage (such as IPQ806x), SMEM is +used to store partition layout. This new parser can now be used to read +SMEM and use it to register an MTD layout according to its content. + +Signed-off-by: Mathieu Olivari +--- + drivers/mtd/Kconfig | 7 ++ + drivers/mtd/Makefile | 1 + + drivers/mtd/qcom_smem_part.c | 231 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 239 insertions(+) + create mode 100644 drivers/mtd/qcom_smem_part.c + +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -195,6 +195,13 @@ config MTD_MYLOADER_PARTS + You will still need the parsing functions to be called by the driver + for your particular device. It won't happen automatically. + ++config MTD_QCOM_SMEM_PARTS ++ tristate "QCOM SMEM partitioning support" ++ depends on QCOM_SMEM ++ help ++ This provides partitions parser for QCOM devices using SMEM ++ such as IPQ806x. ++ + comment "User Modules And Translation Layers" + + # +--- /dev/null ++++ b/drivers/mtd/qcom_smem_part.c +@@ -0,0 +1,231 @@ ++/* ++ * Copyright (c) 2015, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* Processor/host identifier for the application processor */ ++#define SMEM_HOST_APPS 0 ++ ++/* SMEM items index */ ++#define SMEM_AARM_PARTITION_TABLE 9 ++#define SMEM_BOOT_FLASH_TYPE 421 ++#define SMEM_BOOT_FLASH_BLOCK_SIZE 424 ++ ++/* SMEM Flash types */ ++#define SMEM_FLASH_NAND 2 ++#define SMEM_FLASH_SPI 6 ++ ++#define SMEM_PART_NAME_SZ 16 ++#define SMEM_PARTS_MAX 32 ++ ++struct smem_partition { ++ char name[SMEM_PART_NAME_SZ]; ++ __le32 start; ++ __le32 size; ++ __le32 attr; ++}; ++ ++struct smem_partition_table { ++ u8 magic[8]; ++ __le32 version; ++ __le32 len; ++ struct smem_partition parts[SMEM_PARTS_MAX]; ++}; ++ ++/* SMEM Magic values in partition table */ ++static const u8 SMEM_PTABLE_MAGIC[] = { ++ 0xaa, 0x73, 0xee, 0x55, ++ 0xdb, 0xbd, 0x5e, 0xe3, ++}; ++ ++static int qcom_smem_get_flash_blksz(u64 **smem_blksz) ++{ ++ int ret; ++ size_t size; ++ ++ ret = qcom_smem_get(SMEM_HOST_APPS, SMEM_BOOT_FLASH_BLOCK_SIZE, ++ (void **) smem_blksz, &size); ++ ++ if (ret < 0) { ++ pr_err("Unable to read flash blksz from SMEM\n"); ++ return -ENOENT; ++ } ++ ++ if (size != sizeof(**smem_blksz)) { ++ pr_err("Invalid flash blksz size in SMEM\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int qcom_smem_get_flash_type(u64 **smem_flash_type) ++{ ++ int ret; ++ size_t size; ++ ++ ret = qcom_smem_get(SMEM_HOST_APPS, SMEM_BOOT_FLASH_TYPE, ++ (void **) smem_flash_type, &size); ++ ++ if (ret < 0) { ++ pr_err("Unable to read flash type from SMEM\n"); ++ return -ENOENT; ++ } ++ ++ if (size != sizeof(**smem_flash_type)) { ++ pr_err("Invalid flash type size in SMEM\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int qcom_smem_get_flash_partitions(struct smem_partition_table **pparts) ++{ ++ int ret; ++ size_t size; ++ ++ ret = qcom_smem_get(SMEM_HOST_APPS, SMEM_AARM_PARTITION_TABLE, ++ (void **) pparts, &size); ++ ++ if (ret < 0) { ++ pr_err("Unable to read partition table from SMEM\n"); ++ return -ENOENT; ++ } ++ ++ return 0; ++} ++ ++static int of_dev_node_match(struct device *dev, void *data) ++{ ++ return dev->of_node == data; ++} ++ ++static bool is_spi_device(struct device_node *np) ++{ ++ struct device *dev; ++ ++ dev = bus_find_device(&spi_bus_type, NULL, np, of_dev_node_match); ++ if (!dev) ++ return false; ++ ++ put_device(dev); ++ return true; ++} ++ ++static int parse_qcom_smem_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct smem_partition_table *smem_parts; ++ u64 *smem_flash_type, *smem_blksz; ++ struct mtd_partition *mtd_parts; ++ struct device_node *of_node = data->of_node; ++ int i, ret; ++ ++ /* ++ * SMEM will only store the partition table of the boot device. ++ * If this is not the boot device, do not return any partition. ++ */ ++ ret = qcom_smem_get_flash_type(&smem_flash_type); ++ if (ret < 0) ++ return ret; ++ ++ if ((*smem_flash_type == SMEM_FLASH_NAND && !mtd_type_is_nand(master)) ++ || (*smem_flash_type == SMEM_FLASH_SPI && !is_spi_device(of_node))) ++ return 0; ++ ++ /* ++ * Just for sanity purpose, make sure the block size in SMEM matches the ++ * block size of the MTD device ++ */ ++ ret = qcom_smem_get_flash_blksz(&smem_blksz); ++ if (ret < 0) ++ return ret; ++ ++ if (*smem_blksz != master->erasesize) { ++ pr_err("SMEM block size differs from MTD block size\n"); ++ return -EINVAL; ++ } ++ ++ /* Get partition pointer from SMEM */ ++ ret = qcom_smem_get_flash_partitions(&smem_parts); ++ if (ret < 0) ++ return ret; ++ ++ if (memcmp(SMEM_PTABLE_MAGIC, smem_parts->magic, ++ sizeof(SMEM_PTABLE_MAGIC))) { ++ pr_err("SMEM partition magic invalid\n"); ++ return -EINVAL; ++ } ++ ++ /* Allocate and populate the mtd structures */ ++ mtd_parts = kcalloc(le32_to_cpu(smem_parts->len), sizeof(*mtd_parts), ++ GFP_KERNEL); ++ if (!mtd_parts) ++ return -ENOMEM; ++ ++ for (i = 0; i < smem_parts->len; i++) { ++ struct smem_partition *s_part = &smem_parts->parts[i]; ++ struct mtd_partition *m_part = &mtd_parts[i]; ++ ++ m_part->name = s_part->name; ++ m_part->size = le32_to_cpu(s_part->size) * (*smem_blksz); ++ m_part->offset = le32_to_cpu(s_part->start) * (*smem_blksz); ++ ++ /* ++ * The last SMEM partition may have its size marked as ++ * something like 0xffffffff, which means "until the end of the ++ * flash device". In this case, truncate it. ++ */ ++ if (m_part->offset + m_part->size > master->size) ++ m_part->size = master->size - m_part->offset; ++ } ++ ++ *pparts = mtd_parts; ++ ++ return smem_parts->len; ++} ++ ++static struct mtd_part_parser qcom_smem_parser = { ++ .owner = THIS_MODULE, ++ .parse_fn = parse_qcom_smem_partitions, ++ .name = "qcom-smem", ++}; ++ ++static int __init qcom_smem_parser_init(void) ++{ ++ register_mtd_parser(&qcom_smem_parser); ++ return 0; ++} ++ ++static void __exit qcom_smem_parser_exit(void) ++{ ++ deregister_mtd_parser(&qcom_smem_parser); ++} ++ ++module_init(qcom_smem_parser_init); ++module_exit(qcom_smem_parser_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Mathieu Olivari "); ++MODULE_DESCRIPTION("Parsing code for SMEM based partition tables"); +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o + obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o + obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o + obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o ++obj-$(CONFIG_MTD_QCOM_SMEM_PARTS) += qcom_smem_part.o + + # 'Users' - code which presents functionality to userspace. + obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o diff --git a/target/linux/ipq806x/patches-4.1/110-DT-PCI-qcom-Document-PCIe-devicetree-bindings.patch b/target/linux/ipq806x/patches-4.1/110-DT-PCI-qcom-Document-PCIe-devicetree-bindings.patch new file mode 100644 index 0000000..41f91fa --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/110-DT-PCI-qcom-Document-PCIe-devicetree-bindings.patch @@ -0,0 +1,263 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,3/5] DT: PCI: qcom: Document PCIe devicetree bindings +From: Stanimir Varbanov +X-Patchwork-Id: 6326181 +Message-Id: <1430743338-10441-4-git-send-email-svarbanov@mm-sol.com> +To: Rob Herring , Kumar Gala , + Mark Rutland , + Grant Likely , + Bjorn Helgaas , + Kishon Vijay Abraham I , + Russell King , Arnd Bergmann +Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, + linux-pci@vger.kernel.org, Mathieu Olivari , + Srinivas Kandagatla , + Stanimir Varbanov +Date: Mon, 4 May 2015 15:42:16 +0300 + +Document Qualcomm PCIe driver devicetree bindings. + +Signed-off-by: Stanimir Varbanov + +--- +.../devicetree/bindings/pci/qcom,pcie.txt | 231 ++++++++++++++++++++ + 1 files changed, 231 insertions(+), 0 deletions(-) + create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt +@@ -0,0 +1,231 @@ ++* Qualcomm PCI express root complex ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: Value shall include ++ - "qcom,pcie-v0" for apq/ipq8064 ++ - "qcom,pcie-v1" for apq8084 ++ ++- reg: ++ Usage: required ++ Value type: ++ Definition: Register ranges as listed in the reg-names property ++ ++- reg-names: ++ Usage: required ++ Value type: ++ Definition: Must include the following entries ++ - "parf" Qualcomm specific registers ++ - "dbi" Designware PCIe registers ++ - "elbi" External local bus interface registers ++ - "config" PCIe configuration space ++ ++- device_type: ++ Usage: required ++ Value type: ++ Definition: Should be "pci". As specified in designware-pcie.txt ++ ++- #address-cells: ++ Usage: required ++ Value type: ++ Definition: Should be set to 3. As specified in designware-pcie.txt ++ ++- #size-cells: ++ Usage: required ++ Value type: ++ Definition: Should be set 2. As specified in designware-pcie.txt ++ ++- ranges: ++ Usage: required ++ Value type: ++ Definition: As specified in designware-pcie.txt ++ ++- interrupts: ++ Usage: required ++ Value type: ++ Definition: MSI interrupt ++ ++- interrupt-names: ++ Usage: required ++ Value type: ++ Definition: Should contain "msi" ++ ++- #interrupt-cells: ++ Usage: required ++ Value type: ++ Definition: Should be 1. As specified in designware-pcie.txt ++ ++- interrupt-map-mask: ++ Usage: required ++ Value type: ++ Definition: As specified in designware-pcie.txt ++ ++- interrupt-map: ++ Usage: required ++ Value type: ++ Definition: As specified in designware-pcie.txt ++ ++- clocks: ++ Usage: required ++ Value type: ++ Definition: List of phandle and clock specifier pairs as listed ++ in clock-names property ++ ++- clock-names: ++ Usage: required ++ Value type: ++ Definition: Should contain the following entries ++ * should be populated for v0 and v1 ++ - "iface" Configuration AHB clock ++ ++ * should be populated for v0 ++ - "core" Clocks the pcie hw block ++ - "phy" Clocks the pcie PHY block ++ ++ * should be populated for v1 ++ - "aux" Auxiliary (AUX) clock ++ - "bus_master" Master AXI clock ++ - "bus_slave" Slave AXI clock ++ ++- resets: ++ Usage: required ++ Value type: ++ Definition: List of phandle and reset specifier pairs as listed ++ in reset-names property ++ ++- reset-names: ++ Usage: required ++ Value type: ++ Definition: Should contain the following entries ++ * should be populated for v0 ++ - "axi" AXI reset ++ - "ahb" AHB reset ++ - "por" POR reset ++ - "pci" PCI reset ++ - "phy" PHY reset ++ ++ * should be populated for v1 ++ - "core" Core reset ++ ++- power-domains: ++ Usage: required (for v1 only) ++ Value type: ++ Definition: A phandle and power domain specifier pair to the ++ power domain which is responsible for collapsing ++ and restoring power to the peripheral ++ ++- -supply: ++ Usage: required ++ Value type: ++ Definition: List of phandles to the power supply regulator(s) ++ * should be populated for v0 and v1 ++ - "vdda" core analog power supply ++ ++ * should be populated for v0 ++ - "vdda_phy" analog power supply for PHY ++ - "vdda_refclk" analog power supply for IC which generate ++ reference clock ++ ++- phys: ++ Usage: required (for v1 only) ++ Value type: ++ Definition: List of phandle(s) as listed in phy-names property ++ ++- phy-names: ++ Usage: required (for v1 only) ++ Value type: ++ Definition: Should contain "pciephy" ++ ++- -gpio: ++ Usage: optional ++ Value type: ++ Definition: List of phandle and gpio specifier pairs. Should contain ++ - "perst" PCIe endpoint reset signal line ++ - "pewake" PCIe endpoint wake signal line ++ ++- pinctrl-0: ++ Usage: required ++ Value type: ++ Definition: List of phandles pointing at a pin(s) configuration ++ ++- pinctrl-names ++ Usage: required ++ Value type: ++ Definition: List of names of pinctrl-0 state ++ ++* Example for v0 ++ pcie0: pci@1b500000 { ++ compatible = "qcom,pcie-v0"; ++ reg = <0x1b500000 0x1000 ++ 0x1b502000 0x80 ++ 0x1b600000 0x100 ++ 0x0ff00000 0x100000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ ++ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* memory */ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ clocks = <&gcc PCIE_A_CLK>, ++ <&gcc PCIE_H_CLK>, ++ <&gcc PCIE_PHY_CLK>; ++ clock-names = "core", "iface", "phy"; ++ resets = <&gcc PCIE_ACLK_RESET>, ++ <&gcc PCIE_HCLK_RESET>, ++ <&gcc PCIE_POR_RESET>, ++ <&gcc PCIE_PCI_RESET>, ++ <&gcc PCIE_PHY_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy"; ++ }; ++ ++* Example for v1 ++ pcie0@fc520000 { ++ compatible = "qcom,pcie-v1"; ++ reg = <0xfc520000 0x2000>, ++ <0xff000000 0x1000>, ++ <0xff001000 0x1000>, ++ <0xff002000 0x2000>; ++ reg-names = "parf", "dbi", "elbi", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ ++ 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, ++ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, ++ <&gcc GCC_PCIE_0_SLV_AXI_CLK>, ++ <&gcc GCC_PCIE_0_AUX_CLK>; ++ clock-names = "iface", "master_bus", "slave_bus", "aux"; ++ resets = <&gcc GCC_PCIE_0_BCR>; ++ reset-names = "core"; ++ power-domains = <&gcc PCIE0_GDSC>; ++ vdda-supply = <&pma8084_l3>; ++ phys = <&pciephy0>; ++ phy-names = "pciephy"; ++ perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&pcie0_pins_default>; ++ pinctrl-names = "default"; ++ }; diff --git a/target/linux/ipq806x/patches-4.1/111-PCI-qcom-Add-Qualcomm-PCIe-controller-driver.patch b/target/linux/ipq806x/patches-4.1/111-PCI-qcom-Add-Qualcomm-PCIe-controller-driver.patch new file mode 100644 index 0000000..dbf16a3 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/111-PCI-qcom-Add-Qualcomm-PCIe-controller-driver.patch @@ -0,0 +1,753 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v2,4/5] PCI: qcom: Add Qualcomm PCIe controller driver +From: Stanimir Varbanov +X-Patchwork-Id: 6326161 +Message-Id: <1430743338-10441-5-git-send-email-svarbanov@mm-sol.com> +To: Rob Herring , Kumar Gala , + Mark Rutland , + Grant Likely , + Bjorn Helgaas , + Kishon Vijay Abraham I , + Russell King , Arnd Bergmann +Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, + linux-pci@vger.kernel.org, Mathieu Olivari , + Srinivas Kandagatla , + Stanimir Varbanov +Date: Mon, 4 May 2015 15:42:17 +0300 + +The PCIe driver reuse the Designware common code for host +and MSI initialization, and also program the Qualcomm +application specific registers. + +Signed-off-by: Stanimir Varbanov + +--- +MAINTAINERS | 7 + + drivers/pci/host/Kconfig | 9 + + drivers/pci/host/Makefile | 1 + + drivers/pci/host/pcie-qcom.c | 677 ++++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 694 insertions(+), 0 deletions(-) + create mode 100644 drivers/pci/host/pcie-qcom.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -7599,6 +7599,13 @@ L: linux-pci@vger.kernel.org + S: Maintained + F: drivers/pci/host/*spear* + ++PCIE DRIVER FOR QUALCOMM MSM ++M: Stanimir Varbanov ++L: linux-pci@vger.kernel.org ++L: linux-arm-msm@vger.kernel.org ++S: Maintained ++F: drivers/pci/host/*qcom* ++ + PCMCIA SUBSYSTEM + P: Linux PCMCIA Team + L: linux-pcmcia@lists.infradead.org +--- a/drivers/pci/host/Kconfig ++++ b/drivers/pci/host/Kconfig +@@ -125,4 +125,13 @@ config PCIE_IPROC_PLATFORM + Say Y here if you want to use the Broadcom iProc PCIe controller + through the generic platform bus interface + ++config PCIE_QCOM ++ bool "Qualcomm PCIe controller" ++ depends on ARCH_QCOM && OF || (ARM && COMPILE_TEST) ++ select PCIE_DW ++ select PCIEPORTBUS ++ help ++ Say Y here to enable PCIe controller support on Qualcomm SoCs. The ++ PCIe controller use Designware core plus Qualcomm specific hardware ++ wrappers. + endmenu +--- /dev/null ++++ b/drivers/pci/host/pcie-qcom.c +@@ -0,0 +1,677 @@ ++/* ++ * Copyright (c) 2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie-designware.h" ++ ++#define PCIE20_PARF_PHY_CTRL 0x40 ++#define PCIE20_PARF_PHY_REFCLK 0x4C ++#define PCIE20_PARF_DBI_BASE_ADDR 0x168 ++#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c ++#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 ++ ++#define PCIE20_ELBI_SYS_CTRL 0x04 ++#define PCIE20_ELBI_SYS_STTS 0x08 ++#define XMLH_LINK_UP BIT(10) ++ ++#define PCIE20_CAP 0x70 ++#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) ++ ++#define PERST_DELAY_MIN_US 1000 ++#define PERST_DELAY_MAX_US 1005 ++ ++#define LINKUP_DELAY_MIN_US 5000 ++#define LINKUP_DELAY_MAX_US 5100 ++#define LINKUP_RETRIES_COUNT 20 ++ ++#define PCIE_V0 0 /* apq8064 */ ++#define PCIE_V1 1 /* apq8084 */ ++ ++struct qcom_pcie_resources_v0 { ++ struct clk *iface_clk; ++ struct clk *core_clk; ++ struct clk *phy_clk; ++ struct reset_control *pci_reset; ++ struct reset_control *axi_reset; ++ struct reset_control *ahb_reset; ++ struct reset_control *por_reset; ++ struct reset_control *phy_reset; ++ struct regulator *vdda; ++ struct regulator *vdda_phy; ++ struct regulator *vdda_refclk; ++}; ++ ++struct qcom_pcie_resources_v1 { ++ struct clk *iface; ++ struct clk *aux; ++ struct clk *master_bus; ++ struct clk *slave_bus; ++ struct reset_control *core; ++ struct regulator *vdda; ++}; ++ ++union pcie_resources { ++ struct qcom_pcie_resources_v0 v0; ++ struct qcom_pcie_resources_v1 v1; ++}; ++ ++struct qcom_pcie { ++ struct pcie_port pp; ++ struct device *dev; ++ union pcie_resources res; ++ void __iomem *parf; ++ void __iomem *dbi; ++ void __iomem *elbi; ++ struct phy *phy; ++ struct gpio_desc *reset; ++ unsigned int version; ++}; ++ ++#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp) ++ ++static inline void ++writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask) ++{ ++ u32 val = readl(addr); ++ ++ val &= ~clear_mask; ++ val |= set_mask; ++ writel(val, addr); ++} ++ ++static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert) ++{ ++ int val, active_low; ++ ++ if (IS_ERR_OR_NULL(pcie->reset)) ++ return; ++ ++ active_low = gpiod_is_active_low(pcie->reset); ++ ++ if (assert) ++ val = !!active_low; ++ else ++ val = !active_low; ++ ++ gpiod_set_value(pcie->reset, val); ++ ++ usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US); ++} ++ ++static void qcom_ep_reset_assert(struct qcom_pcie *pcie) ++{ ++ qcom_ep_reset_assert_deassert(pcie, 1); ++} ++ ++static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) ++{ ++ qcom_ep_reset_assert_deassert(pcie, 0); ++} ++ ++static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg) ++{ ++ struct pcie_port *pp = arg; ++ ++ return dw_handle_msi_irq(pp); ++} ++ ++static int qcom_pcie_link_up(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ u32 val = readl(pcie->dbi + PCIE20_CAP_LINKCTRLSTATUS); ++ ++ return val & BIT(29) ? 1 : 0; ++} ++ ++static void qcom_pcie_disable_resources_v0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v0 *res = &pcie->res.v0; ++ ++ reset_control_assert(res->pci_reset); ++ reset_control_assert(res->axi_reset); ++ reset_control_assert(res->ahb_reset); ++ reset_control_assert(res->por_reset); ++ reset_control_assert(res->pci_reset); ++ clk_disable_unprepare(res->iface_clk); ++ clk_disable_unprepare(res->core_clk); ++ clk_disable_unprepare(res->phy_clk); ++ regulator_disable(res->vdda); ++ regulator_disable(res->vdda_phy); ++ regulator_disable(res->vdda_refclk); ++} ++ ++static void qcom_pcie_disable_resources_v1(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v1 *res = &pcie->res.v1; ++ ++ reset_control_assert(res->core); ++ clk_disable_unprepare(res->slave_bus); ++ clk_disable_unprepare(res->master_bus); ++ clk_disable_unprepare(res->iface); ++ clk_disable_unprepare(res->aux); ++ regulator_disable(res->vdda); ++} ++ ++static int qcom_pcie_enable_resources_v0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v0 *res = &pcie->res.v0; ++ struct device *dev = pcie->dev; ++ int ret; ++ ++ ret = regulator_enable(res->vdda); ++ if (ret) { ++ dev_err(dev, "cannot enable vdda regulator\n"); ++ return ret; ++ } ++ ++ ret = regulator_enable(res->vdda_refclk); ++ if (ret) { ++ dev_err(dev, "cannot enable vdda_refclk regulator\n"); ++ goto err_refclk; ++ } ++ ++ ret = regulator_enable(res->vdda_phy); ++ if (ret) { ++ dev_err(dev, "cannot enable vdda_phy regulator\n"); ++ goto err_vdda_phy; ++ } ++ ++ ret = clk_prepare_enable(res->iface_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable iface clock\n"); ++ goto err_iface; ++ } ++ ++ ret = clk_prepare_enable(res->core_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable core clock\n"); ++ goto err_clk_core; ++ } ++ ++ ret = clk_prepare_enable(res->phy_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable phy clock\n"); ++ goto err_clk_phy; ++ } ++ ++ ret = reset_control_deassert(res->ahb_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert ahb reset\n"); ++ goto err_reset_ahb; ++ } ++ ++ return 0; ++ ++err_reset_ahb: ++ clk_disable_unprepare(res->phy_clk); ++err_clk_phy: ++ clk_disable_unprepare(res->core_clk); ++err_clk_core: ++ clk_disable_unprepare(res->iface_clk); ++err_iface: ++ regulator_disable(res->vdda_phy); ++err_vdda_phy: ++ regulator_disable(res->vdda_refclk); ++err_refclk: ++ regulator_disable(res->vdda); ++ return ret; ++} ++ ++static int qcom_pcie_enable_resources_v1(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v1 *res = &pcie->res.v1; ++ struct device *dev = pcie->dev; ++ int ret; ++ ++ ret = reset_control_deassert(res->core); ++ if (ret) { ++ dev_err(dev, "cannot deassert core reset\n"); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(res->aux); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable aux clock\n"); ++ goto err_res; ++ } ++ ++ ret = clk_prepare_enable(res->iface); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable iface clock\n"); ++ goto err_aux; ++ } ++ ++ ret = clk_prepare_enable(res->master_bus); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable master_bus clock\n"); ++ goto err_iface; ++ } ++ ++ ret = clk_prepare_enable(res->slave_bus); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable slave_bus clock\n"); ++ goto err_master; ++ } ++ ++ ret = regulator_enable(res->vdda); ++ if (ret) { ++ dev_err(dev, "cannot enable vdda regulator\n"); ++ goto err_slave; ++ } ++ ++ return 0; ++ ++err_slave: ++ clk_disable_unprepare(res->slave_bus); ++err_master: ++ clk_disable_unprepare(res->master_bus); ++err_iface: ++ clk_disable_unprepare(res->iface); ++err_aux: ++ clk_disable_unprepare(res->aux); ++err_res: ++ reset_control_assert(res->core); ++ ++ return ret; ++} ++ ++static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v0 *res = &pcie->res.v0; ++ struct device *dev = pcie->dev; ++ ++ res->vdda = devm_regulator_get(dev, "vdda"); ++ if (IS_ERR(res->vdda)) ++ return PTR_ERR(res->vdda); ++ ++ res->vdda_phy = devm_regulator_get(dev, "vdda_phy"); ++ if (IS_ERR(res->vdda_phy)) ++ return PTR_ERR(res->vdda_phy); ++ ++ res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk"); ++ if (IS_ERR(res->vdda_refclk)) ++ return PTR_ERR(res->vdda_refclk); ++ ++ res->iface_clk = devm_clk_get(dev, "iface"); ++ if (IS_ERR(res->iface_clk)) ++ return PTR_ERR(res->iface_clk); ++ ++ res->core_clk = devm_clk_get(dev, "core"); ++ if (IS_ERR(res->core_clk)) ++ return PTR_ERR(res->core_clk); ++ ++ res->phy_clk = devm_clk_get(dev, "phy"); ++ if (IS_ERR(res->phy_clk)) ++ return PTR_ERR(res->phy_clk); ++ ++ res->pci_reset = devm_reset_control_get(dev, "pci"); ++ if (IS_ERR(res->pci_reset)) ++ return PTR_ERR(res->pci_reset); ++ ++ res->axi_reset = devm_reset_control_get(dev, "axi"); ++ if (IS_ERR(res->axi_reset)) ++ return PTR_ERR(res->axi_reset); ++ ++ res->ahb_reset = devm_reset_control_get(dev, "ahb"); ++ if (IS_ERR(res->ahb_reset)) ++ return PTR_ERR(res->ahb_reset); ++ ++ res->por_reset = devm_reset_control_get(dev, "por"); ++ if (IS_ERR(res->por_reset)) ++ return PTR_ERR(res->por_reset); ++ ++ res->phy_reset = devm_reset_control_get(dev, "phy"); ++ if (IS_ERR(res->phy_reset)) ++ return PTR_ERR(res->phy_reset); ++ ++ return 0; ++} ++ ++static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie) ++{ ++ struct qcom_pcie_resources_v1 *res = &pcie->res.v1; ++ struct device *dev = pcie->dev; ++ ++ res->vdda = devm_regulator_get(dev, "vdda"); ++ if (IS_ERR(res->vdda)) ++ return PTR_ERR(res->vdda); ++ ++ res->iface = devm_clk_get(dev, "iface"); ++ if (IS_ERR(res->iface)) ++ return PTR_ERR(res->iface); ++ ++ res->aux = devm_clk_get(dev, "aux"); ++ if (IS_ERR(res->aux) && PTR_ERR(res->aux) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ else if (IS_ERR(res->aux)) ++ res->aux = NULL; ++ ++ res->master_bus = devm_clk_get(dev, "master_bus"); ++ if (IS_ERR(res->master_bus)) ++ return PTR_ERR(res->master_bus); ++ ++ res->slave_bus = devm_clk_get(dev, "slave_bus"); ++ if (IS_ERR(res->slave_bus)) ++ return PTR_ERR(res->slave_bus); ++ ++ res->core = devm_reset_control_get(dev, "core"); ++ if (IS_ERR(res->core)) ++ return PTR_ERR(res->core); ++ ++ return 0; ++} ++ ++static int qcom_pcie_enable_link_training(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ struct device *dev = pp->dev; ++ int retries; ++ u32 val; ++ ++ /* enable link training */ ++ writel_masked(pcie->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0)); ++ ++ /* wait for up to 100ms for the link to come up */ ++ retries = LINKUP_RETRIES_COUNT; ++ do { ++ val = readl(pcie->elbi + PCIE20_ELBI_SYS_STTS); ++ if (val & XMLH_LINK_UP) ++ break; ++ usleep_range(LINKUP_DELAY_MIN_US, LINKUP_DELAY_MAX_US); ++ } while (retries--); ++ ++ if (retries < 0 || !dw_pcie_link_up(pp)) { ++ dev_err(dev, "link initialization failed\n"); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static void qcom_pcie_host_init_v1(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ int ret; ++ ++ qcom_ep_reset_assert(pcie); ++ ++ ret = qcom_pcie_enable_resources_v1(pcie); ++ if (ret) ++ return; ++ ++ /* change DBI base address */ ++ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) ++ writel_masked(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT, ++ 0, BIT(31)); ++ ++ ret = phy_init(pcie->phy); ++ if (ret) ++ goto err_res; ++ ++ ret = phy_power_on(pcie->phy); ++ if (ret) ++ goto err_phy; ++ ++ dw_pcie_setup_rc(pp); ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) ++ dw_pcie_msi_init(pp); ++ ++ qcom_ep_reset_deassert(pcie); ++ ++ ret = qcom_pcie_enable_link_training(pp); ++ if (ret) ++ goto err; ++ ++ return; ++ ++err: ++ qcom_ep_reset_assert(pcie); ++ phy_power_off(pcie->phy); ++err_phy: ++ phy_exit(pcie->phy); ++err_res: ++ qcom_pcie_disable_resources_v1(pcie); ++} ++ ++static void qcom_pcie_host_init_v0(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ struct qcom_pcie_resources_v0 *res = &pcie->res.v0; ++ struct device *dev = pcie->dev; ++ int ret; ++ ++ qcom_ep_reset_assert(pcie); ++ ++ ret = qcom_pcie_enable_resources_v0(pcie); ++ if (ret) ++ return; ++ ++ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); ++ ++ /* enable external reference clock */ ++ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16)); ++ ++ ret = reset_control_deassert(res->phy_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert phy reset\n"); ++ return; ++ } ++ ++ ret = reset_control_deassert(res->pci_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert pci reset\n"); ++ return; ++ } ++ ++ ret = reset_control_deassert(res->por_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert por reset\n"); ++ return; ++ } ++ ++ ret = reset_control_deassert(res->axi_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert axi reset\n"); ++ return; ++ } ++ ++ /* wait 150ms for clock acquisition */ ++ usleep_range(10000, 15000); ++ ++ dw_pcie_setup_rc(pp); ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) ++ dw_pcie_msi_init(pp); ++ ++ qcom_ep_reset_deassert(pcie); ++ ++ ret = qcom_pcie_enable_link_training(pp); ++ if (ret) ++ goto err; ++ ++ return; ++err: ++ qcom_ep_reset_assert(pcie); ++ qcom_pcie_disable_resources_v0(pcie); ++} ++ ++static void qcom_pcie_host_init(struct pcie_port *pp) ++{ ++ struct qcom_pcie *pcie = to_qcom_pcie(pp); ++ ++ if (pcie->version == PCIE_V0) ++ return qcom_pcie_host_init_v0(pp); ++ else ++ return qcom_pcie_host_init_v1(pp); ++} ++ ++static int ++qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val) ++{ ++ /* the device class is not reported correctly from the register */ ++ if (where == PCI_CLASS_REVISION && size == 4) { ++ *val = readl(pp->dbi_base + PCI_CLASS_REVISION); ++ *val &= ~(0xffff << 16); ++ *val |= PCI_CLASS_BRIDGE_PCI << 16; ++ return PCIBIOS_SUCCESSFUL; ++ } ++ ++ return dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, ++ size, val); ++} ++ ++static struct pcie_host_ops qcom_pcie_ops = { ++ .link_up = qcom_pcie_link_up, ++ .host_init = qcom_pcie_host_init, ++ .rd_own_conf = qcom_pcie_rd_own_conf, ++}; ++ ++static const struct of_device_id qcom_pcie_match[] = { ++ { .compatible = "qcom,pcie-v0", .data = (void *)PCIE_V0 }, ++ { .compatible = "qcom,pcie-v1", .data = (void *)PCIE_V1 }, ++ { } ++}; ++ ++static int qcom_pcie_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ const struct of_device_id *match; ++ struct resource *res; ++ struct qcom_pcie *pcie; ++ struct pcie_port *pp; ++ int ret; ++ ++ match = of_match_node(qcom_pcie_match, dev->of_node); ++ if (!match) ++ return -ENXIO; ++ ++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) ++ return -ENOMEM; ++ ++ pcie->version = (unsigned int)match->data; ++ ++ pcie->reset = devm_gpiod_get_optional(dev, "perst"); ++ if (IS_ERR(pcie->reset) && PTR_ERR(pcie->reset) == -EPROBE_DEFER) ++ return PTR_ERR(pcie->reset); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); ++ pcie->parf = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pcie->parf)) ++ return PTR_ERR(pcie->parf); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); ++ pcie->dbi = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pcie->dbi)) ++ return PTR_ERR(pcie->dbi); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); ++ pcie->elbi = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pcie->elbi)) ++ return PTR_ERR(pcie->elbi); ++ ++ pcie->phy = devm_phy_optional_get(dev, "pciephy"); ++ if (IS_ERR(pcie->phy)) ++ return PTR_ERR(pcie->phy); ++ ++ pcie->dev = dev; ++ ++ if (pcie->version == PCIE_V0) ++ ret = qcom_pcie_get_resources_v0(pcie); ++ else ++ ret = qcom_pcie_get_resources_v1(pcie); ++ ++ if (ret) ++ return ret; ++ ++ pp = &pcie->pp; ++ pp->dev = dev; ++ pp->dbi_base = pcie->dbi; ++ pp->root_bus_nr = -1; ++ pp->ops = &qcom_pcie_ops; ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) { ++ pp->msi_irq = platform_get_irq_byname(pdev, "msi"); ++ if (pp->msi_irq < 0) { ++ dev_err(dev, "cannot get msi irq\n"); ++ return pp->msi_irq; ++ } ++ ++ ret = devm_request_irq(dev, pp->msi_irq, ++ qcom_pcie_msi_irq_handler, ++ IRQF_SHARED, "qcom-pcie-msi", pp); ++ if (ret) { ++ dev_err(dev, "cannot request msi irq\n"); ++ return ret; ++ } ++ } ++ ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(dev, "cannot initialize host\n"); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, pcie); ++ ++ return 0; ++} ++ ++static int qcom_pcie_remove(struct platform_device *pdev) ++{ ++ struct qcom_pcie *pcie = platform_get_drvdata(pdev); ++ ++ qcom_ep_reset_assert(pcie); ++ phy_power_off(pcie->phy); ++ phy_exit(pcie->phy); ++ if (pcie->version == PCIE_V0) ++ qcom_pcie_disable_resources_v0(pcie); ++ else ++ qcom_pcie_disable_resources_v1(pcie); ++ ++ return 0; ++} ++ ++static struct platform_driver qcom_pcie_driver = { ++ .probe = qcom_pcie_probe, ++ .remove = qcom_pcie_remove, ++ .driver = { ++ .name = "qcom-pcie", ++ .of_match_table = qcom_pcie_match, ++ }, ++}; ++ ++module_platform_driver(qcom_pcie_driver); ++ ++MODULE_AUTHOR("Stanimir Varbanov "); ++MODULE_DESCRIPTION("Qualcomm PCIe root complex driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:qcom-pcie"); +--- a/drivers/pci/host/Makefile ++++ b/drivers/pci/host/Makefile +@@ -15,3 +15,4 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-laye + obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o + obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o + obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o ++obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o diff --git a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch new file mode 100644 index 0000000..77cf3c3 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch @@ -0,0 +1,266 @@ +From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Tue, 21 Apr 2015 19:01:42 -0700 +Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms + +qcom-pcie driver now supports version 0 of the controller. This change +adds the corresponding entries to the IPQ806x dtsi file and +corresponding platform (AP148). + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++ + arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++ + 2 files changed, 154 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -35,6 +35,24 @@ + bias-disable; + }; + ++ pcie0_pins: pcie0_pinmux { ++ mux { ++ pins = "gpio3"; ++ function = "pcie1_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ pcie1_pins: pcie1_pinmux { ++ mux { ++ pins = "gpio48"; ++ function = "pcie2_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; +@@ -91,5 +109,19 @@ + sata@29000000 { + status = "ok"; + }; ++ ++ pcie0: pci@1b500000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 3 0>; ++ pinctrl-0 = <&pcie0_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ pcie1: pci@1b700000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 48 0>; ++ pinctrl-0 = <&pcie1_pins>; ++ pinctrl-names = "default"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts +@@ -30,6 +30,33 @@ + bias-disable; + }; + ++ pcie0_pins: pcie0_pinmux { ++ mux { ++ pins = "gpio3"; ++ function = "pcie1_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ pcie1_pins: pcie1_pinmux { ++ mux { ++ pins = "gpio48"; ++ function = "pcie2_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ pcie2_pins: pcie2_pinmux { ++ mux { ++ pins = "gpio63"; ++ function = "pcie3_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; +@@ -128,5 +155,26 @@ + usb30@1 { + status = "ok"; + }; ++ ++ pcie0: pci@1b500000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 3 0>; ++ pinctrl-0 = <&pcie0_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ pcie1: pci@1b700000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 48 0>; ++ pinctrl-0 = <&pcie1_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ pcie2: pci@1b900000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 63 0>; ++ pinctrl-0 = <&pcie2_pins>; ++ pinctrl-names = "default"; ++ }; + }; + }; +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -4,6 +4,8 @@ + #include + #include + #include ++#include ++#include + + / { + model = "Qualcomm IPQ8064"; +@@ -333,6 +335,129 @@ + compatible = "syscon"; + reg = <0x01200600 0x100>; + }; ++ ++ pcie0: pci@1b500000 { ++ compatible = "qcom,pcie-v0"; ++ reg = <0x1b500000 0x1000 ++ 0x1b502000 0x80 ++ 0x1b600000 0x100 ++ 0x0ff00000 0x100000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <0>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */ ++ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ ++ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ ++ clocks = <&gcc PCIE_A_CLK>, ++ <&gcc PCIE_H_CLK>, ++ <&gcc PCIE_PHY_CLK>; ++ clock-names = "core", "iface", "phy"; ++ ++ resets = <&gcc PCIE_ACLK_RESET>, ++ <&gcc PCIE_HCLK_RESET>, ++ <&gcc PCIE_POR_RESET>, ++ <&gcc PCIE_PCI_RESET>, ++ <&gcc PCIE_PHY_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy"; ++ ++ status = "disabled"; ++ }; ++ ++ pcie1: pci@1b700000 { ++ compatible = "qcom,pcie-v0"; ++ reg = <0x1b700000 0x1000 ++ 0x1b702000 0x80 ++ 0x1b800000 0x100 ++ 0x31f00000 0x100000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <1>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */ ++ 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ ++ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ ++ clocks = <&gcc PCIE_1_A_CLK>, ++ <&gcc PCIE_1_H_CLK>, ++ <&gcc PCIE_1_PHY_CLK>; ++ clock-names = "core", "iface", "phy"; ++ ++ resets = <&gcc PCIE_1_ACLK_RESET>, ++ <&gcc PCIE_1_HCLK_RESET>, ++ <&gcc PCIE_1_POR_RESET>, ++ <&gcc PCIE_1_PCI_RESET>, ++ <&gcc PCIE_1_PHY_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy"; ++ ++ status = "disabled"; ++ }; ++ ++ pcie2: pci@1b900000 { ++ compatible = "qcom,pcie-v0"; ++ reg = <0x1b900000 0x1000 ++ 0x1b902000 0x80 ++ 0x1ba00000 0x100 ++ 0x35f00000 0x100000>; ++ reg-names = "dbi", "elbi", "parf", "config"; ++ device_type = "pci"; ++ linux,pci-domain = <2>; ++ bus-range = <0x00 0xff>; ++ num-lanes = <1>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ ranges = <0x81000000 0 0 0x35e00000 0 0x00100000 /* downstream I/O */ ++ 0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ ++ ++ interrupts = ; ++ interrupt-names = "msi"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ ++ <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ ++ <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ ++ <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ ++ ++ clocks = <&gcc PCIE_2_A_CLK>, ++ <&gcc PCIE_2_H_CLK>, ++ <&gcc PCIE_2_PHY_CLK>; ++ clock-names = "core", "iface", "phy"; ++ ++ resets = <&gcc PCIE_2_ACLK_RESET>, ++ <&gcc PCIE_2_HCLK_RESET>, ++ <&gcc PCIE_2_POR_RESET>, ++ <&gcc PCIE_2_PCI_RESET>, ++ <&gcc PCIE_2_PHY_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy"; ++ ++ status = "disabled"; ++ }; + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-4.1/113-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch b/target/linux/ipq806x/patches-4.1/113-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch new file mode 100644 index 0000000..e2d3135 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/113-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch @@ -0,0 +1,29 @@ +From f004aa1dec6e2e206be025de15b115d60f2b21e3 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Tue, 21 Apr 2015 19:09:07 -0700 +Subject: [PATCH 9/9] ARM: qcom: automatically select PCI_DOMAINS if PCI is + enabled + +If multiple PCIe devices are present in the system, the kernel will +panic at boot time when trying to scan the PCI buses. This happens on +IPQ806x based platforms, which has 3 PCIe ports. + +Enabling this option allows the kernel to assign the pci-domains +according to the device-tree content. This allows multiple PCIe +controllers to coexist in the system. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/mach-qcom/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-qcom/Kconfig ++++ b/arch/arm/mach-qcom/Kconfig +@@ -5,6 +5,7 @@ menuconfig ARCH_QCOM + select ARM_AMBA + select PINCTRL + select QCOM_SCM if SMP ++ select PCI_DOMAINS if PCI + help + Support for Qualcomm's devicetree based systems. + diff --git a/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch new file mode 100644 index 0000000..11c9810 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch @@ -0,0 +1,278 @@ +--- a/drivers/pci/host/pcie-qcom.c ++++ b/drivers/pci/host/pcie-qcom.c +@@ -29,8 +29,53 @@ + + #include "pcie-designware.h" + ++/* DBI registers */ ++#define PCIE20_CAP 0x70 ++#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) ++ ++#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 ++#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c ++ ++#define PCIE20_PLR_IATU_VIEWPORT 0x900 ++#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31) ++#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0) ++ ++#define PCIE20_PLR_IATU_CTRL1 0x904 ++#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0) ++#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0) ++ ++#define PCIE20_PLR_IATU_CTRL2 0x908 ++#define PCIE20_PLR_IATU_ENABLE BIT(31) ++ ++#define PCIE20_PLR_IATU_LBAR 0x90C ++#define PCIE20_PLR_IATU_UBAR 0x910 ++#define PCIE20_PLR_IATU_LAR 0x914 ++#define PCIE20_PLR_IATU_LTAR 0x918 ++#define PCIE20_PLR_IATU_UTAR 0x91c ++ ++#define MSM_PCIE_DEV_CFG_ADDR 0x01000000 ++ ++/* PARF registers */ ++#define PCIE20_PARF_PCS_DEEMPH 0x34 ++#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16) ++#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8) ++#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0) ++ ++#define PCIE20_PARF_PCS_SWING 0x38 ++#define PCS_SWING_TX_SWING_FULL(x) (x << 8) ++#define PCS_SWING_TX_SWING_LOW(x) (x << 0) ++ + #define PCIE20_PARF_PHY_CTRL 0x40 ++#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16) ++#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16) ++ + #define PCIE20_PARF_PHY_REFCLK 0x4C ++#define REF_SSP_EN BIT(16) ++#define REF_USE_PAD BIT(12) ++ ++#define PCIE20_PARF_CONFIG_BITS 0x50 ++#define PHY_RX0_EQ(x) (x << 24) ++ + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 + #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c + #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +@@ -39,9 +84,6 @@ + #define PCIE20_ELBI_SYS_STTS 0x08 + #define XMLH_LINK_UP BIT(10) + +-#define PCIE20_CAP 0x70 +-#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10) +- + #define PERST_DELAY_MIN_US 1000 + #define PERST_DELAY_MAX_US 1005 + +@@ -56,14 +98,18 @@ struct qcom_pcie_resources_v0 { + struct clk *iface_clk; + struct clk *core_clk; + struct clk *phy_clk; ++ struct clk *aux_clk; ++ struct clk *ref_clk; + struct reset_control *pci_reset; + struct reset_control *axi_reset; + struct reset_control *ahb_reset; + struct reset_control *por_reset; + struct reset_control *phy_reset; ++ struct reset_control *ext_reset; + struct regulator *vdda; + struct regulator *vdda_phy; + struct regulator *vdda_refclk; ++ uint8_t phy_tx0_term_offset; + }; + + struct qcom_pcie_resources_v1 { +@@ -156,10 +202,13 @@ static void qcom_pcie_disable_resources_ + reset_control_assert(res->axi_reset); + reset_control_assert(res->ahb_reset); + reset_control_assert(res->por_reset); +- reset_control_assert(res->pci_reset); ++ reset_control_assert(res->phy_reset); ++ reset_control_assert(res->ext_reset); + clk_disable_unprepare(res->iface_clk); + clk_disable_unprepare(res->core_clk); + clk_disable_unprepare(res->phy_clk); ++ clk_disable_unprepare(res->aux_clk); ++ clk_disable_unprepare(res->ref_clk); + regulator_disable(res->vdda); + regulator_disable(res->vdda_phy); + regulator_disable(res->vdda_refclk); +@@ -201,6 +250,12 @@ static int qcom_pcie_enable_resources_v0 + goto err_vdda_phy; + } + ++ ret = reset_control_deassert(res->ext_reset); ++ if (ret) { ++ dev_err(dev, "cannot assert ext reset\n"); ++ goto err_reset_ext; ++ } ++ + ret = clk_prepare_enable(res->iface_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable iface clock\n"); +@@ -219,6 +274,18 @@ static int qcom_pcie_enable_resources_v0 + goto err_clk_phy; + } + ++ ret = clk_prepare_enable(res->aux_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable aux clock\n"); ++ goto err_clk_aux; ++ } ++ ++ ret = clk_prepare_enable(res->ref_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable ref clock\n"); ++ goto err_clk_ref; ++ } ++ + ret = reset_control_deassert(res->ahb_reset); + if (ret) { + dev_err(dev, "cannot deassert ahb reset\n"); +@@ -228,12 +295,18 @@ static int qcom_pcie_enable_resources_v0 + return 0; + + err_reset_ahb: ++ clk_disable_unprepare(res->ref_clk); ++err_clk_ref: ++ clk_disable_unprepare(res->aux_clk); ++err_clk_aux: + clk_disable_unprepare(res->phy_clk); + err_clk_phy: + clk_disable_unprepare(res->core_clk); + err_clk_core: + clk_disable_unprepare(res->iface_clk); + err_iface: ++ reset_control_assert(res->ext_reset); ++err_reset_ext: + regulator_disable(res->vdda_phy); + err_vdda_phy: + regulator_disable(res->vdda_refclk); +@@ -329,6 +402,14 @@ static int qcom_pcie_get_resources_v0(st + if (IS_ERR(res->phy_clk)) + return PTR_ERR(res->phy_clk); + ++ res->aux_clk = devm_clk_get(dev, "aux"); ++ if (IS_ERR(res->aux_clk)) ++ return PTR_ERR(res->aux_clk); ++ ++ res->ref_clk = devm_clk_get(dev, "ref"); ++ if (IS_ERR(res->ref_clk)) ++ return PTR_ERR(res->ref_clk); ++ + res->pci_reset = devm_reset_control_get(dev, "pci"); + if (IS_ERR(res->pci_reset)) + return PTR_ERR(res->pci_reset); +@@ -349,6 +430,14 @@ static int qcom_pcie_get_resources_v0(st + if (IS_ERR(res->phy_reset)) + return PTR_ERR(res->phy_reset); + ++ res->ext_reset = devm_reset_control_get(dev, "ext"); ++ if (IS_ERR(res->ext_reset)) ++ return PTR_ERR(res->ext_reset); ++ ++ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset", ++ &res->phy_tx0_term_offset)) ++ res->phy_tx0_term_offset = 0; ++ + return 0; + } + +@@ -461,6 +550,57 @@ err_res: + qcom_pcie_disable_resources_v1(pcie); + } + ++static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev) ++{ ++ struct pcie_port *pp = &pcie->pp; ++ ++ /* ++ * program and enable address translation region 0 (device config ++ * address space); region type config; ++ * axi config address range to device config address range ++ */ ++ writel(PCIE20_PLR_IATU_REGION_OUTBOUND | ++ PCIE20_PLR_IATU_REGION_INDEX(0), ++ pcie->dbi + PCIE20_PLR_IATU_VIEWPORT); ++ ++ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->dbi + PCIE20_PLR_IATU_CTRL1); ++ writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2); ++ writel(pp->cfg0_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR); ++ writel((pp->cfg0_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR); ++ writel((pp->cfg0_mod_base + pp->cfg0_size - 1), ++ pcie->dbi + PCIE20_PLR_IATU_LAR); ++ writel(busdev, pcie->dbi + PCIE20_PLR_IATU_LTAR); ++ writel(0, pcie->dbi + PCIE20_PLR_IATU_UTAR); ++} ++ ++static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie) ++{ ++ struct pcie_port *pp = &pcie->pp; ++ ++ /* ++ * program and enable address translation region 2 (device resource ++ * address space); region type memory; ++ * axi device bar address range to device bar address range ++ */ ++ writel(PCIE20_PLR_IATU_REGION_OUTBOUND | ++ PCIE20_PLR_IATU_REGION_INDEX(2), ++ pcie->dbi + PCIE20_PLR_IATU_VIEWPORT); ++ ++ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->dbi + PCIE20_PLR_IATU_CTRL1); ++ writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2); ++ writel(pp->mem_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR); ++ writel((pp->mem_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR); ++ writel(pp->mem_mod_base + pp->mem_size - 1, ++ pcie->dbi + PCIE20_PLR_IATU_LAR); ++ writel(pp->mem_bus_addr, pcie->dbi + PCIE20_PLR_IATU_LTAR); ++ writel(upper_32_bits(pp->mem_bus_addr), ++ pcie->dbi + PCIE20_PLR_IATU_UTAR); ++ ++ /* 1K PCIE buffer setting */ ++ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); ++ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); ++} ++ + static void qcom_pcie_host_init_v0(struct pcie_port *pp) + { + struct qcom_pcie *pcie = to_qcom_pcie(pp); +@@ -476,9 +616,26 @@ static void qcom_pcie_host_init_v0(struc + + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); + +- /* enable external reference clock */ +- writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16)); ++ /* Set Tx termination offset */ ++ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, ++ PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, ++ PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset)); ++ ++ /* PARF programming */ ++ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) | ++ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) | ++ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22), ++ pcie->parf + PCIE20_PARF_PCS_DEEMPH); ++ writel(PCS_SWING_TX_SWING_FULL(0x78) | ++ PCS_SWING_TX_SWING_LOW(0x78), ++ pcie->parf + PCIE20_PARF_PCS_SWING); ++ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS); ++ ++ /* Enable reference clock */ ++ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, ++ REF_USE_PAD, REF_SSP_EN); + ++ /* De-assert PHY, PCIe, POR and AXI resets */ + ret = reset_control_deassert(res->phy_reset); + if (ret) { + dev_err(dev, "cannot deassert phy reset\n"); +@@ -517,6 +674,9 @@ static void qcom_pcie_host_init_v0(struc + if (ret) + goto err; + ++ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR); ++ qcom_pcie_prog_viewport_mem2_outbound(pcie); ++ + return; + err: + qcom_ep_reset_assert(pcie); diff --git a/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch b/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch new file mode 100644 index 0000000..d01e5a8 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch @@ -0,0 +1,80 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -364,15 +364,21 @@ + + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, +- <&gcc PCIE_PHY_CLK>; +- clock-names = "core", "iface", "phy"; ++ <&gcc PCIE_PHY_CLK>, ++ <&gcc PCIE_AUX_CLK>, ++ <&gcc PCIE_ALT_REF_CLK>; ++ clock-names = "core", "iface", "phy", "aux", "ref"; ++ ++ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; ++ assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, +- <&gcc PCIE_PHY_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy"; ++ <&gcc PCIE_PHY_RESET>, ++ <&gcc PCIE_EXT_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + status = "disabled"; + }; +@@ -405,15 +411,21 @@ + + clocks = <&gcc PCIE_1_A_CLK>, + <&gcc PCIE_1_H_CLK>, +- <&gcc PCIE_1_PHY_CLK>; +- clock-names = "core", "iface", "phy"; ++ <&gcc PCIE_1_PHY_CLK>, ++ <&gcc PCIE_1_AUX_CLK>, ++ <&gcc PCIE_1_ALT_REF_CLK>; ++ clock-names = "core", "iface", "phy", "aux", "ref"; ++ ++ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; ++ assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_1_ACLK_RESET>, + <&gcc PCIE_1_HCLK_RESET>, + <&gcc PCIE_1_POR_RESET>, + <&gcc PCIE_1_PCI_RESET>, +- <&gcc PCIE_1_PHY_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy"; ++ <&gcc PCIE_1_PHY_RESET>, ++ <&gcc PCIE_1_EXT_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + status = "disabled"; + }; +@@ -446,15 +458,21 @@ + + clocks = <&gcc PCIE_2_A_CLK>, + <&gcc PCIE_2_H_CLK>, +- <&gcc PCIE_2_PHY_CLK>; +- clock-names = "core", "iface", "phy"; ++ <&gcc PCIE_2_PHY_CLK>, ++ <&gcc PCIE_2_AUX_CLK>, ++ <&gcc PCIE_2_ALT_REF_CLK>; ++ clock-names = "core", "iface", "phy", "aux", "ref"; ++ ++ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; ++ assigned-clock-rates = <100000000>; + + resets = <&gcc PCIE_2_ACLK_RESET>, + <&gcc PCIE_2_HCLK_RESET>, + <&gcc PCIE_2_POR_RESET>, + <&gcc PCIE_2_PCI_RESET>, +- <&gcc PCIE_2_PHY_RESET>; +- reset-names = "axi", "ahb", "por", "pci", "phy"; ++ <&gcc PCIE_2_PHY_RESET>, ++ <&gcc PCIE_2_EXT_RESET>; ++ reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + + status = "disabled"; + }; diff --git a/target/linux/ipq806x/patches-4.1/126-add-rpm-to-ipq8064-dts.patch b/target/linux/ipq806x/patches-4.1/126-add-rpm-to-ipq8064-dts.patch new file mode 100644 index 0000000..be80f4c --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/126-add-rpm-to-ipq8064-dts.patch @@ -0,0 +1,87 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -2,6 +2,7 @@ + + #include "skeleton.dtsi" + #include ++#include + #include + #include + #include +@@ -92,6 +93,63 @@ + reg-names = "lpass-lpaif"; + }; + ++ rpm@108000 { ++ compatible = "qcom,rpm-ipq8064"; ++ reg = <0x108000 0x1000>; ++ qcom,ipc = <&l2cc 0x8 2>; ++ ++ interrupts = <0 19 0>, ++ <0 21 0>, ++ <0 22 0>; ++ interrupt-names = "ack", ++ "err", ++ "wakeup"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ smb208_s1a: smb208-s1a { ++ compatible = "qcom,rpm-smb208"; ++ reg = ; ++ ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ ++ }; ++ ++ smb208_s1b: smb208-s1b { ++ compatible = "qcom,rpm-smb208"; ++ reg = ; ++ ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: smb208-s2a { ++ compatible = "qcom,rpm-smb208"; ++ reg = ; ++ ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: smb208-s2b { ++ compatible = "qcom,rpm-smb208"; ++ reg = ; ++ ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++ + qcom_pinmux: pinmux@800000 { + compatible = "qcom,ipq8064-pinctrl"; + reg = <0x800000 0x4000>; +@@ -136,6 +194,12 @@ + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + ++ l2cc: clock-controller@2011000 { ++ compatible = "qcom,kpss-gcc", "syscon"; ++ reg = <0x2011000 0x1000>; ++ clock-output-names = "acpu_l2_aux"; ++ }; ++ + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; diff --git a/target/linux/ipq806x/patches-4.1/133-ARM-Add-Krait-L2-register-accessor-functions.patch b/target/linux/ipq806x/patches-4.1/133-ARM-Add-Krait-L2-register-accessor-functions.patch new file mode 100644 index 0000000..36a92c8 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/133-ARM-Add-Krait-L2-register-accessor-functions.patch @@ -0,0 +1,144 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,01/13] ARM: Add Krait L2 register accessor functions +From: Stephen Boyd +X-Patchwork-Id: 6063051 +Message-Id: <1426920332-9340-2-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , + Mark Rutland , Russell King , + Courtney Cavin +Date: Fri, 20 Mar 2015 23:45:20 -0700 + +Krait CPUs have a handful of L2 cache controller registers that +live behind a cp15 based indirection register. First you program +the indirection register (l2cpselr) to point the L2 'window' +register (l2cpdr) at what you want to read/write. Then you +read/write the 'window' register to do what you want. The +l2cpselr register is not banked per-cpu so we must lock around +accesses to it to prevent other CPUs from re-pointing l2cpdr +underneath us. + +Cc: Mark Rutland +Cc: Russell King +Cc: Courtney Cavin +Signed-off-by: Stephen Boyd + +--- +arch/arm/common/Kconfig | 3 ++ + arch/arm/common/Makefile | 1 + + arch/arm/common/krait-l2-accessors.c | 58 +++++++++++++++++++++++++++++++ + arch/arm/include/asm/krait-l2-accessors.h | 20 +++++++++++ + 4 files changed, 82 insertions(+) + create mode 100644 arch/arm/common/krait-l2-accessors.c + create mode 100644 arch/arm/include/asm/krait-l2-accessors.h + +--- a/arch/arm/common/Kconfig ++++ b/arch/arm/common/Kconfig +@@ -9,6 +9,9 @@ config DMABOUNCE + bool + select ZONE_DMA + ++config KRAIT_L2_ACCESSORS ++ bool ++ + config SHARP_LOCOMO + bool + +--- a/arch/arm/common/Makefile ++++ b/arch/arm/common/Makefile +@@ -7,6 +7,7 @@ obj-y += firmware.o + obj-$(CONFIG_ICST) += icst.o + obj-$(CONFIG_SA1111) += sa1111.o + obj-$(CONFIG_DMABOUNCE) += dmabounce.o ++obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o + obj-$(CONFIG_SHARP_LOCOMO) += locomo.o + obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o + obj-$(CONFIG_SHARP_SCOOP) += scoop.o +--- /dev/null ++++ b/arch/arm/common/krait-l2-accessors.c +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++ ++static DEFINE_RAW_SPINLOCK(krait_l2_lock); ++ ++void krait_set_l2_indirect_reg(u32 addr, u32 val) ++{ ++ unsigned long flags; ++ ++ raw_spin_lock_irqsave(&krait_l2_lock, flags); ++ /* ++ * Select the L2 window by poking l2cpselr, then write to the window ++ * via l2cpdr. ++ */ ++ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr)); ++ isb(); ++ asm volatile ("mcr p15, 3, %0, c15, c0, 7 @ l2cpdr" : : "r" (val)); ++ isb(); ++ ++ raw_spin_unlock_irqrestore(&krait_l2_lock, flags); ++} ++EXPORT_SYMBOL(krait_set_l2_indirect_reg); ++ ++u32 krait_get_l2_indirect_reg(u32 addr) ++{ ++ u32 val; ++ unsigned long flags; ++ ++ raw_spin_lock_irqsave(&krait_l2_lock, flags); ++ /* ++ * Select the L2 window by poking l2cpselr, then read from the window ++ * via l2cpdr. ++ */ ++ asm volatile ("mcr p15, 3, %0, c15, c0, 6 @ l2cpselr" : : "r" (addr)); ++ isb(); ++ asm volatile ("mrc p15, 3, %0, c15, c0, 7 @ l2cpdr" : "=r" (val)); ++ ++ raw_spin_unlock_irqrestore(&krait_l2_lock, flags); ++ ++ return val; ++} ++EXPORT_SYMBOL(krait_get_l2_indirect_reg); +--- /dev/null ++++ b/arch/arm/include/asm/krait-l2-accessors.h +@@ -0,0 +1,20 @@ ++/* ++ * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __ASMARM_KRAIT_L2_ACCESSORS_H ++#define __ASMARM_KRAIT_L2_ACCESSORS_H ++ ++extern void krait_set_l2_indirect_reg(u32 addr, u32 val); ++extern u32 krait_get_l2_indirect_reg(u32 addr); ++ ++#endif diff --git a/target/linux/ipq806x/patches-4.1/134-clk-mux-Split-out-register-accessors-for-reuse.patch b/target/linux/ipq806x/patches-4.1/134-clk-mux-Split-out-register-accessors-for-reuse.patch new file mode 100644 index 0000000..3a475fb --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/134-clk-mux-Split-out-register-accessors-for-reuse.patch @@ -0,0 +1,192 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,02/13] clk: mux: Split out register accessors for reuse +From: Stephen Boyd +X-Patchwork-Id: 6063111 +Message-Id: <1426920332-9340-3-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:21 -0700 + +We want to reuse the logic in clk-mux.c for other clock drivers +that don't use readl as register accessors. Fortunately, there +really isn't much to the mux code besides the table indirection +and quirk flags if you assume any bit shifting and masking has +been done already. Pull that logic out into reusable functions +that operate on an optional table and some flags so that other +drivers can use the same logic. + +Signed-off-by: Stephen Boyd + +--- +drivers/clk/clk-mux.c | 76 +++++++++++++++++++++++++++----------------- + include/linux/clk-provider.h | 9 ++++-- + 2 files changed, 54 insertions(+), 31 deletions(-) + +--- a/drivers/clk/clk-mux.c ++++ b/drivers/clk/clk-mux.c +@@ -29,35 +29,24 @@ + + #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) + +-static u8 clk_mux_get_parent(struct clk_hw *hw) ++unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val, ++ unsigned int *table, unsigned long flags) + { +- struct clk_mux *mux = to_clk_mux(hw); + int num_parents = __clk_get_num_parents(hw->clk); +- u32 val; + +- /* +- * FIXME need a mux-specific flag to determine if val is bitwise or numeric +- * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 +- * to 0x7 (index starts at one) +- * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so +- * val = 0x4 really means "bit 2, index starts at bit 0" +- */ +- val = clk_readl(mux->reg) >> mux->shift; +- val &= mux->mask; +- +- if (mux->table) { ++ if (table) { + int i; + + for (i = 0; i < num_parents; i++) +- if (mux->table[i] == val) ++ if (table[i] == val) + return i; + return -EINVAL; + } + +- if (val && (mux->flags & CLK_MUX_INDEX_BIT)) ++ if (val && (flags & CLK_MUX_INDEX_BIT)) + val = ffs(val) - 1; + +- if (val && (mux->flags & CLK_MUX_INDEX_ONE)) ++ if (val && (flags & CLK_MUX_INDEX_ONE)) + val--; + + if (val >= num_parents) +@@ -65,24 +54,53 @@ static u8 clk_mux_get_parent(struct clk_ + + return val; + } ++EXPORT_SYMBOL_GPL(clk_mux_get_parent); + +-static int clk_mux_set_parent(struct clk_hw *hw, u8 index) ++static u8 _clk_mux_get_parent(struct clk_hw *hw) + { + struct clk_mux *mux = to_clk_mux(hw); + u32 val; +- unsigned long flags = 0; + +- if (mux->table) +- index = mux->table[index]; ++ /* ++ * FIXME need a mux-specific flag to determine if val is bitwise or numeric ++ * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 ++ * to 0x7 (index starts at one) ++ * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so ++ * val = 0x4 really means "bit 2, index starts at bit 0" ++ */ ++ val = clk_readl(mux->reg) >> mux->shift; ++ val &= mux->mask; ++ ++ return clk_mux_get_parent(hw, val, mux->table, mux->flags); ++} + +- else { +- if (mux->flags & CLK_MUX_INDEX_BIT) +- index = 1 << index; ++unsigned int clk_mux_reindex(u8 index, unsigned int *table, ++ unsigned long flags) ++{ ++ unsigned int val = index; + +- if (mux->flags & CLK_MUX_INDEX_ONE) +- index++; ++ if (table) { ++ val = table[val]; ++ } else { ++ if (flags & CLK_MUX_INDEX_BIT) ++ val = 1 << index; ++ ++ if (flags & CLK_MUX_INDEX_ONE) ++ val++; + } + ++ return val; ++} ++EXPORT_SYMBOL_GPL(clk_mux_reindex); ++ ++static int clk_mux_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct clk_mux *mux = to_clk_mux(hw); ++ u32 val; ++ unsigned long flags = 0; ++ ++ index = clk_mux_reindex(index, mux->table, mux->flags); ++ + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + +@@ -102,21 +120,21 @@ static int clk_mux_set_parent(struct clk + } + + const struct clk_ops clk_mux_ops = { +- .get_parent = clk_mux_get_parent, ++ .get_parent = _clk_mux_get_parent, + .set_parent = clk_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, + }; + EXPORT_SYMBOL_GPL(clk_mux_ops); + + const struct clk_ops clk_mux_ro_ops = { +- .get_parent = clk_mux_get_parent, ++ .get_parent = _clk_mux_get_parent, + }; + EXPORT_SYMBOL_GPL(clk_mux_ro_ops); + + struct clk *clk_register_mux_table(struct device *dev, const char *name, + const char **parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u32 mask, +- u8 clk_mux_flags, u32 *table, spinlock_t *lock) ++ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock) + { + struct clk_mux *mux; + struct clk *clk; +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -409,7 +409,7 @@ void clk_unregister_divider(struct clk * + struct clk_mux { + struct clk_hw hw; + void __iomem *reg; +- u32 *table; ++ unsigned int *table; + u32 mask; + u8 shift; + u8 flags; +@@ -425,6 +425,11 @@ struct clk_mux { + extern const struct clk_ops clk_mux_ops; + extern const struct clk_ops clk_mux_ro_ops; + ++unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val, ++ unsigned int *table, unsigned long flags); ++unsigned int clk_mux_reindex(u8 index, unsigned int *table, ++ unsigned long flags); ++ + struct clk *clk_register_mux(struct device *dev, const char *name, + const char **parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, +@@ -433,7 +438,7 @@ struct clk *clk_register_mux(struct devi + struct clk *clk_register_mux_table(struct device *dev, const char *name, + const char **parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u32 mask, +- u8 clk_mux_flags, u32 *table, spinlock_t *lock); ++ u8 clk_mux_flags, unsigned int *table, spinlock_t *lock); + + void clk_unregister_mux(struct clk *clk); + diff --git a/target/linux/ipq806x/patches-4.1/135-clk-Avoid-sending-high-rates-to-downstream-clocks-during-set_rate.patch b/target/linux/ipq806x/patches-4.1/135-clk-Avoid-sending-high-rates-to-downstream-clocks-during-set_rate.patch new file mode 100644 index 0000000..143e079 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/135-clk-Avoid-sending-high-rates-to-downstream-clocks-during-set_rate.patch @@ -0,0 +1,130 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3, 03/13] clk: Avoid sending high rates to downstream clocks during + set_rate +From: Stephen Boyd +X-Patchwork-Id: 6063271 +Message-Id: <1426920332-9340-4-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:22 -0700 + +If a clock is on and we call clk_set_rate() on it we may get into +a situation where the clock temporarily increases in rate +dramatically while we walk the tree and call .set_rate() ops. For +example, consider a case where a PLL feeds into a divider. +Initially the divider is set to divide by 1 and the PLL is +running fairly slow (100MHz). The downstream consumer of the +divider output can only handle rates =< 400 MHz, but the divider +can only choose between divisors of 1 and 4. + + +-----+ +----------------+ + | PLL |-->| div 1 or div 4 |---> consumer device + +-----+ +----------------+ + +To achieve a rate of 400MHz on the output of the divider, we +would have to set the rate of the PLL to 1.6 GHz and then divide +it by 4. The current code would set the PLL to 1.6GHz first while +the divider is still set to 1, thus causing the downstream +consumer of the clock to receive a few clock cycles of 1.6GHz +clock (far beyond it's maximum acceptable rate). We should be +changing the divider first before increasing the PLL rate to +avoid this problem. + +Therefore, set the rate of any child clocks that are increasing +in rate from their current rate so that they can increase their +dividers if necessary. We assume that there isn't such a thing as +minimum rate requirements. + +Signed-off-by: Stephen Boyd + +--- +drivers/clk/clk.c | 34 ++++++++++++++++++++++------------ + 1 file changed, 22 insertions(+), 12 deletions(-) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -1744,21 +1744,24 @@ static struct clk_core *clk_propagate_ra + * walk down a subtree and set the new rates notifying the rate + * change on the way + */ +-static void clk_change_rate(struct clk_core *clk) ++static void ++clk_change_rate(struct clk_core *clk, unsigned long best_parent_rate) + { + struct clk_core *child; + struct hlist_node *tmp; + unsigned long old_rate; +- unsigned long best_parent_rate = 0; + bool skip_set_rate = false; + struct clk_core *old_parent; + +- old_rate = clk->rate; ++ hlist_for_each_entry(child, &clk->children, child_node) { ++ /* Skip children who will be reparented to another clock */ ++ if (child->new_parent && child->new_parent != clk) ++ continue; ++ if (child->new_rate > child->rate) ++ clk_change_rate(child, clk->new_rate); ++ } + +- if (clk->new_parent) +- best_parent_rate = clk->new_parent->rate; +- else if (clk->parent) +- best_parent_rate = clk->parent->rate; ++ old_rate = clk->rate; + + if (clk->new_parent && clk->new_parent != clk->parent) { + old_parent = __clk_set_parent_before(clk, clk->new_parent); +@@ -1784,7 +1787,7 @@ static void clk_change_rate(struct clk_c + + trace_clk_set_rate_complete(clk, clk->new_rate); + +- clk->rate = clk_recalc(clk, best_parent_rate); ++ clk->rate = clk->new_rate; + + if (clk->notifier_count && old_rate != clk->rate) + __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); +@@ -1797,12 +1800,13 @@ static void clk_change_rate(struct clk_c + /* Skip children who will be reparented to another clock */ + if (child->new_parent && child->new_parent != clk) + continue; +- clk_change_rate(child); ++ if (child->new_rate != child->rate) ++ clk_change_rate(child, clk->new_rate); + } + + /* handle the new child who might not be in clk->children yet */ +- if (clk->new_child) +- clk_change_rate(clk->new_child); ++ if (clk->new_child && clk->new_child->new_rate != clk->new_child->rate) ++ clk_change_rate(clk->new_child, clk->new_rate); + } + + static int clk_core_set_rate_nolock(struct clk_core *clk, +@@ -1811,6 +1815,7 @@ static int clk_core_set_rate_nolock(stru + struct clk_core *top, *fail_clk; + unsigned long rate = req_rate; + int ret = 0; ++ unsigned long parent_rate; + + if (!clk) + return 0; +@@ -1836,8 +1841,13 @@ static int clk_core_set_rate_nolock(stru + return -EBUSY; + } + ++ if (top->parent) ++ parent_rate = top->parent->rate; ++ else ++ parent_rate = 0; ++ + /* change the rates */ +- clk_change_rate(top); ++ clk_change_rate(top, parent_rate); + + clk->req_rate = req_rate; + diff --git a/target/linux/ipq806x/patches-4.1/136-clk-Add-safe-switch-hook.patch b/target/linux/ipq806x/patches-4.1/136-clk-Add-safe-switch-hook.patch new file mode 100644 index 0000000..b0d89a9 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/136-clk-Add-safe-switch-hook.patch @@ -0,0 +1,164 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,04/13] clk: Add safe switch hook +From: Stephen Boyd +X-Patchwork-Id: 6063211 +Message-Id: <1426920332-9340-5-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:23 -0700 + +Sometimes clocks can't accept their parent source turning off +while the source is reprogrammed to a different rate. Most +notably CPU clocks require a way to switch away from the current +PLL they're running on, reprogram that PLL to a new rate, and +then switch back to the PLL with the new rate once they're done. +Add a hook that drivers can implement allowing them to return a +'safe parent' that they can switch their parent to while the +upstream source is reprogrammed to support this. + +Signed-off-by: Stephen Boyd + +--- +This patch is good enough for Krait, but soon I'll need to +support a "safe rate" where we ask a clock what rate it needs to be running +at to be sure it's within voltage constraints. Right now safe parent +handles that problem on Krait, but on other platforms it won't work. + + drivers/clk/clk.c | 61 ++++++++++++++++++++++++++++++++++++++------ + include/linux/clk-provider.h | 1 + + 2 files changed, 54 insertions(+), 8 deletions(-) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -56,9 +56,12 @@ struct clk_core { + struct clk_core **parents; + u8 num_parents; + u8 new_parent_index; ++ u8 safe_parent_index; + unsigned long rate; + unsigned long req_rate; ++ unsigned long old_rate; + unsigned long new_rate; ++ struct clk_core *safe_parent; + struct clk_core *new_parent; + struct clk_core *new_child; + unsigned long flags; +@@ -1596,7 +1599,8 @@ out: + static void clk_calc_subtree(struct clk_core *clk, unsigned long new_rate, + struct clk_core *new_parent, u8 p_index) + { +- struct clk_core *child; ++ struct clk_core *child, *parent; ++ struct clk_hw *parent_hw; + + clk->new_rate = new_rate; + clk->new_parent = new_parent; +@@ -1606,6 +1610,18 @@ static void clk_calc_subtree(struct clk_ + if (new_parent && new_parent != clk->parent) + new_parent->new_child = clk; + ++ if (clk->ops->get_safe_parent) { ++ parent_hw = clk->ops->get_safe_parent(clk->hw); ++ if (parent_hw) { ++ parent = parent_hw->core; ++ p_index = clk_fetch_parent_index(clk, parent); ++ clk->safe_parent_index = p_index; ++ clk->safe_parent = parent; ++ } ++ } else { ++ clk->safe_parent = NULL; ++ } ++ + hlist_for_each_entry(child, &clk->children, child_node) { + child->new_rate = clk_recalc(child, new_rate); + clk_calc_subtree(child, child->new_rate, NULL, 0); +@@ -1710,14 +1726,43 @@ static struct clk_core *clk_propagate_ra + unsigned long event) + { + struct clk_core *child, *tmp_clk, *fail_clk = NULL; ++ struct clk_core *old_parent; + int ret = NOTIFY_DONE; + +- if (clk->rate == clk->new_rate) ++ if (clk->rate == clk->new_rate && event != POST_RATE_CHANGE) + return NULL; + ++ switch (event) { ++ case PRE_RATE_CHANGE: ++ if (clk->safe_parent) ++ clk->ops->set_parent(clk->hw, clk->safe_parent_index); ++ clk->old_rate = clk->rate; ++ break; ++ case POST_RATE_CHANGE: ++ if (clk->safe_parent) { ++ old_parent = __clk_set_parent_before(clk, ++ clk->new_parent); ++ if (clk->ops->set_rate_and_parent) { ++ clk->ops->set_rate_and_parent(clk->hw, ++ clk->new_rate, ++ clk->new_parent ? ++ clk->new_parent->rate : 0, ++ clk->new_parent_index); ++ } else if (clk->ops->set_parent) { ++ clk->ops->set_parent(clk->hw, ++ clk->new_parent_index); ++ } ++ __clk_set_parent_after(clk, clk->new_parent, ++ old_parent); ++ } ++ break; ++ } ++ + if (clk->notifier_count) { +- ret = __clk_notify(clk, event, clk->rate, clk->new_rate); +- if (ret & NOTIFY_STOP_MASK) ++ if (event != POST_RATE_CHANGE || clk->old_rate != clk->rate) ++ ret = __clk_notify(clk, event, clk->old_rate, ++ clk->new_rate); ++ if (ret & NOTIFY_STOP_MASK && event != POST_RATE_CHANGE) + fail_clk = clk; + } + +@@ -1763,7 +1808,8 @@ clk_change_rate(struct clk_core *clk, un + + old_rate = clk->rate; + +- if (clk->new_parent && clk->new_parent != clk->parent) { ++ if (clk->new_parent && clk->new_parent != clk->parent && ++ !clk->safe_parent) { + old_parent = __clk_set_parent_before(clk, clk->new_parent); + trace_clk_set_parent(clk, clk->new_parent); + +@@ -1789,9 +1835,6 @@ clk_change_rate(struct clk_core *clk, un + + clk->rate = clk->new_rate; + +- if (clk->notifier_count && old_rate != clk->rate) +- __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate); +- + /* + * Use safe iteration, as change_rate can actually swap parents + * for certain clock types. +@@ -1851,6 +1894,8 @@ static int clk_core_set_rate_nolock(stru + + clk->req_rate = req_rate; + ++ clk_propagate_rate_change(top, POST_RATE_CHANGE); ++ + return ret; + } + +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -183,6 +183,7 @@ struct clk_ops { + struct clk_hw **best_parent_hw); + int (*set_parent)(struct clk_hw *hw, u8 index); + u8 (*get_parent)(struct clk_hw *hw); ++ struct clk_hw *(*get_safe_parent)(struct clk_hw *hw); + int (*set_rate)(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate); + int (*set_rate_and_parent)(struct clk_hw *hw, diff --git a/target/linux/ipq806x/patches-4.1/137-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch b/target/linux/ipq806x/patches-4.1/137-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch new file mode 100644 index 0000000..6fad6e8 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/137-clk-qcom-Add-support-for-High-Frequency-PLLs-HFPLLs.patch @@ -0,0 +1,351 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,05/13] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) +From: Stephen Boyd +X-Patchwork-Id: 6063261 +Message-Id: <1426920332-9340-6-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:24 -0700 + +HFPLLs are the main frequency source for Krait CPU clocks. Add +support for changing the rate of these PLLs. + +Signed-off-by: Stephen Boyd + +--- +I'd really like to get rid of __clk_hfpll_init_once() if possible... + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/clk-hfpll.c | 253 +++++++++++++++++++++++++++++++++++++++++++ + drivers/clk/qcom/clk-hfpll.h | 54 +++++++++ + 3 files changed, 308 insertions(+) + create mode 100644 drivers/clk/qcom/clk-hfpll.c + create mode 100644 drivers/clk/qcom/clk-hfpll.h + +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o + clk-qcom-y += clk-branch.o + clk-qcom-y += clk-regmap-divider.o + clk-qcom-y += clk-regmap-mux.o ++clk-qcom-y += clk-hfpll.o + clk-qcom-y += reset.o + + obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o +--- /dev/null ++++ b/drivers/clk/qcom/clk-hfpll.c +@@ -0,0 +1,253 @@ ++/* ++ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-regmap.h" ++#include "clk-hfpll.h" ++ ++#define PLL_OUTCTRL BIT(0) ++#define PLL_BYPASSNL BIT(1) ++#define PLL_RESET_N BIT(2) ++ ++/* Initialize a HFPLL at a given rate and enable it. */ ++static void __clk_hfpll_init_once(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ ++ if (likely(h->init_done)) ++ return; ++ ++ /* Configure PLL parameters for integer mode. */ ++ if (hd->config_val) ++ regmap_write(regmap, hd->config_reg, hd->config_val); ++ regmap_write(regmap, hd->m_reg, 0); ++ regmap_write(regmap, hd->n_reg, 1); ++ ++ if (hd->user_reg) { ++ u32 regval = hd->user_val; ++ unsigned long rate; ++ ++ rate = __clk_get_rate(hw->clk); ++ ++ /* Pick the right VCO. */ ++ if (hd->user_vco_mask && rate > hd->low_vco_max_rate) ++ regval |= hd->user_vco_mask; ++ regmap_write(regmap, hd->user_reg, regval); ++ } ++ ++ if (hd->droop_reg) ++ regmap_write(regmap, hd->droop_reg, hd->droop_val); ++ ++ h->init_done = true; ++} ++ ++static void __clk_hfpll_enable(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 val; ++ ++ __clk_hfpll_init_once(hw); ++ ++ /* Disable PLL bypass mode. */ ++ regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL); ++ ++ /* ++ * H/W requires a 5us delay between disabling the bypass and ++ * de-asserting the reset. Delay 10us just to be safe. ++ */ ++ udelay(10); ++ ++ /* De-assert active-low PLL reset. */ ++ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); ++ ++ /* Wait for PLL to lock. */ ++ if (hd->status_reg) { ++ do { ++ regmap_read(regmap, hd->status_reg, &val); ++ } while (!(val & BIT(hd->lock_bit))); ++ } else { ++ udelay(60); ++ } ++ ++ /* Enable PLL output. */ ++ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); ++} ++ ++/* Enable an already-configured HFPLL. */ ++static int clk_hfpll_enable(struct clk_hw *hw) ++{ ++ unsigned long flags; ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 mode; ++ ++ spin_lock_irqsave(&h->lock, flags); ++ regmap_read(regmap, hd->mode_reg, &mode); ++ if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) ++ __clk_hfpll_enable(hw); ++ spin_unlock_irqrestore(&h->lock, flags); ++ ++ return 0; ++} ++ ++static void __clk_hfpll_disable(struct clk_hfpll *h) ++{ ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ ++ /* ++ * Disable the PLL output, disable test mode, enable the bypass mode, ++ * and assert the reset. ++ */ ++ regmap_update_bits(regmap, hd->mode_reg, ++ PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); ++} ++ ++static void clk_hfpll_disable(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&h->lock, flags); ++ __clk_hfpll_disable(h); ++ spin_unlock_irqrestore(&h->lock, flags); ++} ++ ++static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ unsigned long rrate; ++ ++ rate = clamp(rate, hd->min_rate, hd->max_rate); ++ ++ rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate; ++ if (rrate > hd->max_rate) ++ rrate -= *parent_rate; ++ ++ return rrate; ++} ++ ++/* ++ * For optimization reasons, assumes no downstream clocks are actively using ++ * it. ++ */ ++static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ unsigned long flags; ++ u32 l_val, val; ++ bool enabled; ++ ++ l_val = rate / parent_rate; ++ ++ spin_lock_irqsave(&h->lock, flags); ++ ++ enabled = __clk_is_enabled(hw->clk); ++ if (enabled) ++ __clk_hfpll_disable(h); ++ ++ /* Pick the right VCO. */ ++ if (hd->user_reg && hd->user_vco_mask) { ++ regmap_read(regmap, hd->user_reg, &val); ++ if (rate <= hd->low_vco_max_rate) ++ val &= ~hd->user_vco_mask; ++ else ++ val |= hd->user_vco_mask; ++ regmap_write(regmap, hd->user_reg, val); ++ } ++ ++ regmap_write(regmap, hd->l_reg, l_val); ++ ++ if (enabled) ++ __clk_hfpll_enable(hw); ++ ++ spin_unlock_irqrestore(&h->lock, flags); ++ ++ return 0; ++} ++ ++static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 l_val; ++ ++ regmap_read(regmap, hd->l_reg, &l_val); ++ ++ return l_val * parent_rate; ++} ++ ++static void clk_hfpll_init(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 mode, status; ++ ++ regmap_read(regmap, hd->mode_reg, &mode); ++ if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { ++ __clk_hfpll_init_once(hw); ++ return; ++ } ++ ++ if (hd->status_reg) { ++ regmap_read(regmap, hd->status_reg, &status); ++ if (!(status & BIT(hd->lock_bit))) { ++ WARN(1, "HFPLL %s is ON, but not locked!\n", ++ __clk_get_name(hw->clk)); ++ clk_hfpll_disable(hw); ++ __clk_hfpll_init_once(hw); ++ } ++ } ++} ++ ++static int hfpll_is_enabled(struct clk_hw *hw) ++{ ++ struct clk_hfpll *h = to_clk_hfpll(hw); ++ struct hfpll_data const *hd = h->d; ++ struct regmap *regmap = h->clkr.regmap; ++ u32 mode; ++ ++ regmap_read(regmap, hd->mode_reg, &mode); ++ mode &= 0x7; ++ return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); ++} ++ ++const struct clk_ops clk_ops_hfpll = { ++ .enable = clk_hfpll_enable, ++ .disable = clk_hfpll_disable, ++ .is_enabled = hfpll_is_enabled, ++ .round_rate = clk_hfpll_round_rate, ++ .set_rate = clk_hfpll_set_rate, ++ .recalc_rate = clk_hfpll_recalc_rate, ++ .init = clk_hfpll_init, ++}; ++EXPORT_SYMBOL_GPL(clk_ops_hfpll); +--- /dev/null ++++ b/drivers/clk/qcom/clk-hfpll.h +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#ifndef __QCOM_CLK_HFPLL_H__ ++#define __QCOM_CLK_HFPLL_H__ ++ ++#include ++#include ++#include "clk-regmap.h" ++ ++struct hfpll_data { ++ u32 mode_reg; ++ u32 l_reg; ++ u32 m_reg; ++ u32 n_reg; ++ u32 user_reg; ++ u32 droop_reg; ++ u32 config_reg; ++ u32 status_reg; ++ u8 lock_bit; ++ ++ u32 droop_val; ++ u32 config_val; ++ u32 user_val; ++ u32 user_vco_mask; ++ unsigned long low_vco_max_rate; ++ ++ unsigned long min_rate; ++ unsigned long max_rate; ++}; ++ ++struct clk_hfpll { ++ struct hfpll_data const *d; ++ int init_done; ++ ++ struct clk_regmap clkr; ++ spinlock_t lock; ++}; ++ ++#define to_clk_hfpll(_hw) \ ++ container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr) ++ ++extern const struct clk_ops clk_ops_hfpll; ++ ++#endif diff --git a/target/linux/ipq806x/patches-4.1/138-clk-qcom-Add-HFPLL-driver.patch b/target/linux/ipq806x/patches-4.1/138-clk-qcom-Add-HFPLL-driver.patch new file mode 100644 index 0000000..4056784 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/138-clk-qcom-Add-HFPLL-driver.patch @@ -0,0 +1,206 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,06/13] clk: qcom: Add HFPLL driver +From: Stephen Boyd +X-Patchwork-Id: 6063231 +Message-Id: <1426920332-9340-7-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , +Date: Fri, 20 Mar 2015 23:45:25 -0700 + +On some devices (MSM8974 for example), the HFPLLs are +instantiated within the Krait processor subsystem as separate +register regions. Add a driver for these PLLs so that we can +provide HFPLL clocks for use by the system. + +Cc: +Signed-off-by: Stephen Boyd + +--- +.../devicetree/bindings/clock/qcom,hfpll.txt | 40 ++++++++ + drivers/clk/qcom/Kconfig | 8 ++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/hfpll.c | 109 +++++++++++++++++++++ + 4 files changed, 158 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt + create mode 100644 drivers/clk/qcom/hfpll.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt +@@ -0,0 +1,40 @@ ++High-Frequency PLL (HFPLL) ++ ++PROPERTIES ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: must be "qcom,hfpll" ++ ++- reg: ++ Usage: required ++ Value type: ++ Definition: address and size of HPLL registers. An optional second ++ element specifies the address and size of the alias ++ register region. ++ ++- clock-output-names: ++ Usage: required ++ Value type: ++ Definition: Name of the PLL. Typically hfpllX where X is a CPU number ++ starting at 0. Otherwise hfpll_Y where Y is more specific ++ such as "l2". ++ ++Example: ++ ++1) An HFPLL for the L2 cache. ++ ++ clock-controller@f9016000 { ++ compatible = "qcom,hfpll"; ++ reg = <0xf9016000 0x30>; ++ clock-output-names = "hfpll_l2"; ++ }; ++ ++2) An HFPLL for CPU0. This HFPLL has the alias register region. ++ ++ clock-controller@f908a000 { ++ compatible = "qcom,hfpll"; ++ reg = <0xf908a000 0x30>, <0xf900a000 0x30>; ++ clock-output-names = "hfpll0"; ++ }; +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -97,3 +97,11 @@ config MSM_MMCC_8974 + Support for the multimedia clock controller on msm8974 devices. + Say Y if you want to support multimedia devices such as display, + graphics, video encode/decode, camera, etc. ++ ++config QCOM_HFPLL ++ tristate "High-Frequency PLL (HFPLL) Clock Controller" ++ depends on COMMON_CLK_QCOM ++ help ++ Support for the high-frequency PLLs present on Qualcomm devices. ++ Say Y if you want to support CPU frequency scaling on devices ++ such as MSM8974, APQ8084, etc. +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -22,3 +22,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm896 + obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o + obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o + obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o ++obj-$(CONFIG_QCOM_HFPLL) += hfpll.o +--- /dev/null ++++ b/drivers/clk/qcom/hfpll.c +@@ -0,0 +1,109 @@ ++/* ++ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-regmap.h" ++#include "clk-hfpll.h" ++ ++static const struct hfpll_data hdata = { ++ .mode_reg = 0x00, ++ .l_reg = 0x04, ++ .m_reg = 0x08, ++ .n_reg = 0x0c, ++ .user_reg = 0x10, ++ .config_reg = 0x14, ++ .config_val = 0x430405d, ++ .status_reg = 0x1c, ++ .lock_bit = 16, ++ ++ .user_val = 0x8, ++ .user_vco_mask = 0x100000, ++ .low_vco_max_rate = 1248000000, ++ .min_rate = 537600000UL, ++ .max_rate = 2900000000UL, ++}; ++ ++static const struct of_device_id qcom_hfpll_match_table[] = { ++ { .compatible = "qcom,hfpll" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table); ++ ++static const struct regmap_config hfpll_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x30, ++ .fast_io = true, ++}; ++ ++static int qcom_hfpll_probe(struct platform_device *pdev) ++{ ++ struct clk *clk; ++ struct resource *res; ++ struct device *dev = &pdev->dev; ++ void __iomem *base; ++ struct regmap *regmap; ++ struct clk_hfpll *h; ++ struct clk_init_data init = { ++ .parent_names = (const char *[]){ "xo" }, ++ .num_parents = 1, ++ .ops = &clk_ops_hfpll, ++ }; ++ ++ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL); ++ if (!h) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ if (of_property_read_string_index(dev->of_node, "clock-output-names", ++ 0, &init.name)) ++ return -ENODEV; ++ ++ h->d = &hdata; ++ h->clkr.hw.init = &init; ++ spin_lock_init(&h->lock); ++ ++ clk = devm_clk_register_regmap(&pdev->dev, &h->clkr); ++ ++ return PTR_ERR_OR_ZERO(clk); ++} ++ ++static struct platform_driver qcom_hfpll_driver = { ++ .probe = qcom_hfpll_probe, ++ .driver = { ++ .name = "qcom-hfpll", ++ .of_match_table = qcom_hfpll_match_table, ++ }, ++}; ++module_platform_driver(qcom_hfpll_driver); ++ ++MODULE_DESCRIPTION("QCOM HFPLL Clock Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:qcom-hfpll"); diff --git a/target/linux/ipq806x/patches-4.1/139-clk-qcom-Add-IPQ806X-s-HFPLLs.patch b/target/linux/ipq806x/patches-4.1/139-clk-qcom-Add-IPQ806X-s-HFPLLs.patch new file mode 100644 index 0000000..ffcd462 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/139-clk-qcom-Add-IPQ806X-s-HFPLLs.patch @@ -0,0 +1,127 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,08/13] clk: qcom: Add IPQ806X's HFPLLs +From: Stephen Boyd +X-Patchwork-Id: 6063241 +Message-Id: <1426920332-9340-9-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:27 -0700 + +Describe the HFPLLs present on IPQ806X devices. + +Signed-off-by: Stephen Boyd + +--- +drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 83 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -30,6 +30,7 @@ + #include "clk-pll.h" + #include "clk-rcg.h" + #include "clk-branch.h" ++#include "clk-hfpll.h" + #include "reset.h" + + static struct clk_pll pll0 = { +@@ -113,6 +114,85 @@ static struct clk_regmap pll8_vote = { + }, + }; + ++static struct hfpll_data hfpll0_data = { ++ .mode_reg = 0x3200, ++ .l_reg = 0x3208, ++ .m_reg = 0x320c, ++ .n_reg = 0x3210, ++ .config_reg = 0x3204, ++ .status_reg = 0x321c, ++ .config_val = 0x7845c665, ++ .droop_reg = 0x3214, ++ .droop_val = 0x0108c000, ++ .min_rate = 600000000UL, ++ .max_rate = 1800000000UL, ++}; ++ ++static struct clk_hfpll hfpll0 = { ++ .d = &hfpll0_data, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .parent_names = (const char *[]){ "pxo" }, ++ .num_parents = 1, ++ .name = "hfpll0", ++ .ops = &clk_ops_hfpll, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock), ++}; ++ ++static struct hfpll_data hfpll1_data = { ++ .mode_reg = 0x3240, ++ .l_reg = 0x3248, ++ .m_reg = 0x324c, ++ .n_reg = 0x3250, ++ .config_reg = 0x3244, ++ .status_reg = 0x325c, ++ .config_val = 0x7845c665, ++ .droop_reg = 0x3314, ++ .droop_val = 0x0108c000, ++ .min_rate = 600000000UL, ++ .max_rate = 1800000000UL, ++}; ++ ++static struct clk_hfpll hfpll1 = { ++ .d = &hfpll1_data, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .parent_names = (const char *[]){ "pxo" }, ++ .num_parents = 1, ++ .name = "hfpll1", ++ .ops = &clk_ops_hfpll, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock), ++}; ++ ++static struct hfpll_data hfpll_l2_data = { ++ .mode_reg = 0x3300, ++ .l_reg = 0x3308, ++ .m_reg = 0x330c, ++ .n_reg = 0x3310, ++ .config_reg = 0x3304, ++ .status_reg = 0x331c, ++ .config_val = 0x7845c665, ++ .droop_reg = 0x3314, ++ .droop_val = 0x0108c000, ++ .min_rate = 600000000UL, ++ .max_rate = 1800000000UL, ++}; ++ ++static struct clk_hfpll hfpll_l2 = { ++ .d = &hfpll_l2_data, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .parent_names = (const char *[]){ "pxo" }, ++ .num_parents = 1, ++ .name = "hfpll_l2", ++ .ops = &clk_ops_hfpll, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock), ++}; ++ ++ + static struct clk_pll pll14 = { + .l_reg = 0x31c4, + .m_reg = 0x31c8, +@@ -2307,6 +2387,9 @@ static struct clk_regmap *gcc_ipq806x_cl + [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, + [EBI2_CLK] = &ebi2_clk.clkr, + [EBI2_AON_CLK] = &ebi2_aon_clk.clkr, ++ [PLL9] = &hfpll0.clkr, ++ [PLL10] = &hfpll1.clkr, ++ [PLL12] = &hfpll_l2.clkr, + }; + + static const struct qcom_reset_map gcc_ipq806x_resets[] = { diff --git a/target/linux/ipq806x/patches-4.1/140-clk-qcom-Add-support-for-Krait-clocks.patch b/target/linux/ipq806x/patches-4.1/140-clk-qcom-Add-support-for-Krait-clocks.patch new file mode 100644 index 0000000..5fcc787 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/140-clk-qcom-Add-support-for-Krait-clocks.patch @@ -0,0 +1,271 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,09/13] clk: qcom: Add support for Krait clocks +From: Stephen Boyd +X-Patchwork-Id: 6063251 +Message-Id: <1426920332-9340-10-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar +Date: Fri, 20 Mar 2015 23:45:28 -0700 + +The Krait clocks are made up of a series of muxes and a divider +that choose between a fixed rate clock and dedicated HFPLLs for +each CPU. Instead of using mmio accesses to remux parents, the +Krait implementation exposes the remux control via cp15 +registers. Support these clocks. + +Signed-off-by: Stephen Boyd + +--- +drivers/clk/qcom/Kconfig | 4 ++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/clk-krait.c | 166 +++++++++++++++++++++++++++++++++++++++++++ + drivers/clk/qcom/clk-krait.h | 49 +++++++++++++ + 4 files changed, 220 insertions(+) + create mode 100644 drivers/clk/qcom/clk-krait.c + create mode 100644 drivers/clk/qcom/clk-krait.h + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -105,3 +105,7 @@ config QCOM_HFPLL + Support for the high-frequency PLLs present on Qualcomm devices. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8974, APQ8084, etc. ++ ++config KRAIT_CLOCKS ++ bool ++ select KRAIT_L2_ACCESSORS +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o + clk-qcom-y += clk-branch.o + clk-qcom-y += clk-regmap-divider.o + clk-qcom-y += clk-regmap-mux.o ++clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o + clk-qcom-y += clk-hfpll.o + clk-qcom-y += reset.o + +--- /dev/null ++++ b/drivers/clk/qcom/clk-krait.c +@@ -0,0 +1,166 @@ ++/* ++ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-krait.h" ++ ++/* Secondary and primary muxes share the same cp15 register */ ++static DEFINE_SPINLOCK(krait_clock_reg_lock); ++ ++#define LPL_SHIFT 8 ++static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) ++{ ++ unsigned long flags; ++ u32 regval; ++ ++ spin_lock_irqsave(&krait_clock_reg_lock, flags); ++ regval = krait_get_l2_indirect_reg(mux->offset); ++ regval &= ~(mux->mask << mux->shift); ++ regval |= (sel & mux->mask) << mux->shift; ++ if (mux->lpl) { ++ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); ++ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); ++ } ++ krait_set_l2_indirect_reg(mux->offset, regval); ++ spin_unlock_irqrestore(&krait_clock_reg_lock, flags); ++ ++ /* Wait for switch to complete. */ ++ mb(); ++ udelay(1); ++} ++ ++static int krait_mux_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ u32 sel; ++ ++ sel = clk_mux_reindex(index, mux->parent_map, 0); ++ mux->en_mask = sel; ++ /* Don't touch mux if CPU is off as it won't work */ ++ if (__clk_is_enabled(hw->clk)) ++ __krait_mux_set_sel(mux, sel); ++ return 0; ++} ++ ++static u8 krait_mux_get_parent(struct clk_hw *hw) ++{ ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ u32 sel; ++ ++ sel = krait_get_l2_indirect_reg(mux->offset); ++ sel >>= mux->shift; ++ sel &= mux->mask; ++ mux->en_mask = sel; ++ ++ return clk_mux_get_parent(hw, sel, mux->parent_map, 0); ++} ++ ++static struct clk_hw *krait_mux_get_safe_parent(struct clk_hw *hw) ++{ ++ int i; ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ int num_parents = __clk_get_num_parents(hw->clk); ++ ++ i = mux->safe_sel; ++ for (i = 0; i < num_parents; i++) ++ if (mux->safe_sel == mux->parent_map[i]) ++ break; ++ ++ return __clk_get_hw(clk_get_parent_by_index(hw->clk, i)); ++} ++ ++static int krait_mux_enable(struct clk_hw *hw) ++{ ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ ++ __krait_mux_set_sel(mux, mux->en_mask); ++ ++ return 0; ++} ++ ++static void krait_mux_disable(struct clk_hw *hw) ++{ ++ struct krait_mux_clk *mux = to_krait_mux_clk(hw); ++ ++ __krait_mux_set_sel(mux, mux->safe_sel); ++} ++ ++const struct clk_ops krait_mux_clk_ops = { ++ .enable = krait_mux_enable, ++ .disable = krait_mux_disable, ++ .set_parent = krait_mux_set_parent, ++ .get_parent = krait_mux_get_parent, ++ .determine_rate = __clk_mux_determine_rate_closest, ++ .get_safe_parent = krait_mux_get_safe_parent, ++}; ++EXPORT_SYMBOL_GPL(krait_mux_clk_ops); ++ ++/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */ ++static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ *parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), rate * 2); ++ return DIV_ROUND_UP(*parent_rate, 2); ++} ++ ++static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct krait_div2_clk *d = to_krait_div2_clk(hw); ++ unsigned long flags; ++ u32 val; ++ u32 mask = BIT(d->width) - 1; ++ ++ if (d->lpl) ++ mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; ++ ++ spin_lock_irqsave(&krait_clock_reg_lock, flags); ++ val = krait_get_l2_indirect_reg(d->offset); ++ val &= ~mask; ++ krait_set_l2_indirect_reg(d->offset, val); ++ spin_unlock_irqrestore(&krait_clock_reg_lock, flags); ++ ++ return 0; ++} ++ ++static unsigned long ++krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ struct krait_div2_clk *d = to_krait_div2_clk(hw); ++ u32 mask = BIT(d->width) - 1; ++ u32 div; ++ ++ div = krait_get_l2_indirect_reg(d->offset); ++ div >>= d->shift; ++ div &= mask; ++ div = (div + 1) * 2; ++ ++ return DIV_ROUND_UP(parent_rate, div); ++} ++ ++const struct clk_ops krait_div2_clk_ops = { ++ .round_rate = krait_div2_round_rate, ++ .set_rate = krait_div2_set_rate, ++ .recalc_rate = krait_div2_recalc_rate, ++}; ++EXPORT_SYMBOL_GPL(krait_div2_clk_ops); +--- /dev/null ++++ b/drivers/clk/qcom/clk-krait.h +@@ -0,0 +1,49 @@ ++/* ++ * Copyright (c) 2013, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __QCOM_CLK_KRAIT_H ++#define __QCOM_CLK_KRAIT_H ++ ++#include ++ ++struct krait_mux_clk { ++ unsigned int *parent_map; ++ bool has_safe_parent; ++ u8 safe_sel; ++ u32 offset; ++ u32 mask; ++ u32 shift; ++ u32 en_mask; ++ bool lpl; ++ ++ struct clk_hw hw; ++}; ++ ++#define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw) ++ ++extern const struct clk_ops krait_mux_clk_ops; ++ ++struct krait_div2_clk { ++ u32 offset; ++ u8 width; ++ u32 shift; ++ bool lpl; ++ ++ struct clk_hw hw; ++}; ++ ++#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw) ++ ++extern const struct clk_ops krait_div2_clk_ops; ++ ++#endif diff --git a/target/linux/ipq806x/patches-4.1/141-clk-qcom-Add-KPSS-ACC-GCC-driver.patch b/target/linux/ipq806x/patches-4.1/141-clk-qcom-Add-KPSS-ACC-GCC-driver.patch new file mode 100644 index 0000000..db43888 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/141-clk-qcom-Add-KPSS-ACC-GCC-driver.patch @@ -0,0 +1,205 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,10/13] clk: qcom: Add KPSS ACC/GCC driver +From: Stephen Boyd +X-Patchwork-Id: 6063201 +Message-Id: <1426920332-9340-11-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , +Date: Fri, 20 Mar 2015 23:45:29 -0700 + +The ACC and GCC regions present in KPSSv1 contain registers to +control clocks and power to each Krait CPU and L2. For CPUfreq +purposes probe these devices and expose a mux clock that chooses +between PXO and PLL8. + +Cc: +Signed-off-by: Stephen Boyd + +--- +.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 ++ + .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 28 +++++++ + drivers/clk/qcom/Kconfig | 8 ++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/kpss-xcc.c | 95 ++++++++++++++++++++++ + 5 files changed, 139 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt + create mode 100644 drivers/clk/qcom/kpss-xcc.c + +--- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt ++++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +@@ -21,10 +21,17 @@ PROPERTIES + the register region. An optional second element specifies + the base address and size of the alias register region. + ++- clock-output-names: ++ Usage: optional ++ Value type: ++ Definition: Name of the output clock. Typically acpuX_aux where X is a ++ CPU number starting at 0. ++ + Example: + + clock-controller@2088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x02088000 0x1000>, + <0x02008000 0x1000>; ++ clock-output-names = "acpu0_aux"; + }; +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt +@@ -0,0 +1,28 @@ ++Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) ++ ++PROPERTIES ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: should be one of: ++ "qcom,kpss-gcc" ++ ++- reg: ++ Usage: required ++ Value type: ++ Definition: base address and size of the register region ++ ++- clock-output-names: ++ Usage: required ++ Value type: ++ Definition: Name of the output clock. Typically acpu_l2_aux indicating ++ an L2 cache auxiliary clock. ++ ++Example: ++ ++ l2cc: clock-controller@2011000 { ++ compatible = "qcom,kpss-gcc"; ++ reg = <0x2011000 0x1000>; ++ clock-output-names = "acpu_l2_aux"; ++ }; +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -106,6 +106,14 @@ config QCOM_HFPLL + Say Y if you want to support CPU frequency scaling on devices + such as MSM8974, APQ8084, etc. + ++config KPSS_XCC ++ tristate "KPSS Clock Controller" ++ depends on COMMON_CLK_QCOM ++ help ++ Support for the Krait ACC and GCC clock controllers. Say Y ++ if you want to support CPU frequency scaling on devices such ++ as MSM8960, APQ8064, etc. ++ + config KRAIT_CLOCKS + bool + select KRAIT_L2_ACCESSORS +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -23,4 +23,5 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm896 + obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o + obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o + obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o ++obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o + obj-$(CONFIG_QCOM_HFPLL) += hfpll.o +--- /dev/null ++++ b/drivers/clk/qcom/kpss-xcc.c +@@ -0,0 +1,95 @@ ++/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const char *aux_parents[] = { ++ "pll8_vote", ++ "pxo", ++}; ++ ++static unsigned int aux_parent_map[] = { ++ 3, ++ 0, ++}; ++ ++static const struct of_device_id kpss_xcc_match_table[] = { ++ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL }, ++ { .compatible = "qcom,kpss-gcc" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, kpss_xcc_match_table); ++ ++static int kpss_xcc_driver_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *id; ++ struct clk *clk; ++ struct resource *res; ++ void __iomem *base; ++ const char *name; ++ ++ id = of_match_device(kpss_xcc_match_table, &pdev->dev); ++ if (!id) ++ return -ENODEV; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ if (id->data) { ++ if (of_property_read_string_index(pdev->dev.of_node, ++ "clock-output-names", 0, &name)) ++ return -ENODEV; ++ base += 0x14; ++ } else { ++ name = "acpu_l2_aux"; ++ base += 0x28; ++ } ++ ++ clk = clk_register_mux_table(&pdev->dev, name, aux_parents, ++ ARRAY_SIZE(aux_parents), 0, base, 0, 0x3, ++ 0, aux_parent_map, NULL); ++ ++ platform_set_drvdata(pdev, clk); ++ ++ return PTR_ERR_OR_ZERO(clk); ++} ++ ++static int kpss_xcc_driver_remove(struct platform_device *pdev) ++{ ++ clk_unregister_mux(platform_get_drvdata(pdev)); ++ return 0; ++} ++ ++static struct platform_driver kpss_xcc_driver = { ++ .probe = kpss_xcc_driver_probe, ++ .remove = kpss_xcc_driver_remove, ++ .driver = { ++ .name = "kpss-xcc", ++ .of_match_table = kpss_xcc_match_table, ++ }, ++}; ++module_platform_driver(kpss_xcc_driver); ++ ++MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:kpss-xcc"); diff --git a/target/linux/ipq806x/patches-4.1/142-clk-qcom-Add-Krait-clock-controller-driver.patch b/target/linux/ipq806x/patches-4.1/142-clk-qcom-Add-Krait-clock-controller-driver.patch new file mode 100644 index 0000000..59fc44f --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/142-clk-qcom-Add-Krait-clock-controller-driver.patch @@ -0,0 +1,435 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,11/13] clk: qcom: Add Krait clock controller driver +From: Stephen Boyd +X-Patchwork-Id: 6063121 +Message-Id: <1426920332-9340-12-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , +Date: Fri, 20 Mar 2015 23:45:30 -0700 + +The Krait CPU clocks are made up of a primary mux and secondary +mux for each CPU and the L2, controlled via cp15 accessors. For +Kraits within KPSSv1 each secondary mux accepts a different aux +source, but on KPSSv2 each secondary mux accepts the same aux +source. + +Cc: +Signed-off-by: Stephen Boyd + +--- +.../devicetree/bindings/clock/qcom,krait-cc.txt | 22 ++ + drivers/clk/qcom/Kconfig | 8 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/krait-cc.c | 352 +++++++++++++++++++++ + 4 files changed, 383 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt + create mode 100644 drivers/clk/qcom/krait-cc.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt +@@ -0,0 +1,22 @@ ++Krait Clock Controller ++ ++PROPERTIES ++ ++- compatible: ++ Usage: required ++ Value type: ++ Definition: must be one of: ++ "qcom,krait-cc-v1" ++ "qcom,krait-cc-v2" ++ ++- #clock-cells: ++ Usage: required ++ Value type: ++ Definition: must be 1 ++ ++Example: ++ ++ kraitcc: clock-controller { ++ compatible = "qcom,krait-cc-v1"; ++ #clock-cells = <1>; ++ }; +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -114,6 +114,14 @@ config KPSS_XCC + if you want to support CPU frequency scaling on devices such + as MSM8960, APQ8064, etc. + ++config KRAITCC ++ tristate "Krait Clock Controller" ++ depends on COMMON_CLK_QCOM && ARM ++ select KRAIT_CLOCKS ++ help ++ Support for the Krait CPU clocks on Qualcomm devices. ++ Say Y if you want to support CPU frequency scaling. ++ + config KRAIT_CLOCKS + bool + select KRAIT_L2_ACCESSORS +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -25,3 +25,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8 + obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o + obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o + obj-$(CONFIG_QCOM_HFPLL) += hfpll.o ++obj-$(CONFIG_KRAITCC) += krait-cc.o +--- /dev/null ++++ b/drivers/clk/qcom/krait-cc.c +@@ -0,0 +1,352 @@ ++/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-krait.h" ++ ++static unsigned int sec_mux_map[] = { ++ 2, ++ 0, ++}; ++ ++static unsigned int pri_mux_map[] = { ++ 1, ++ 2, ++ 0, ++}; ++ ++static int ++krait_add_div(struct device *dev, int id, const char *s, unsigned offset) ++{ ++ struct krait_div2_clk *div; ++ struct clk_init_data init = { ++ .num_parents = 1, ++ .ops = &krait_div2_clk_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }; ++ const char *p_names[1]; ++ struct clk *clk; ++ ++ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); ++ if (!div) ++ return -ENOMEM; ++ ++ div->width = 2; ++ div->shift = 6; ++ div->lpl = id >= 0; ++ div->offset = offset; ++ div->hw.init = &init; ++ ++ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); ++ if (!init.name) ++ return -ENOMEM; ++ ++ init.parent_names = p_names; ++ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); ++ if (!p_names[0]) { ++ kfree(init.name); ++ return -ENOMEM; ++ } ++ ++ clk = devm_clk_register(dev, &div->hw); ++ kfree(p_names[0]); ++ kfree(init.name); ++ ++ return PTR_ERR_OR_ZERO(clk); ++} ++ ++static int ++krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset, ++ bool unique_aux) ++{ ++ struct krait_mux_clk *mux; ++ static const char *sec_mux_list[] = { ++ "acpu_aux", ++ "qsb", ++ }; ++ struct clk_init_data init = { ++ .parent_names = sec_mux_list, ++ .num_parents = ARRAY_SIZE(sec_mux_list), ++ .ops = &krait_mux_clk_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }; ++ struct clk *clk; ++ ++ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); ++ if (!mux) ++ return -ENOMEM; ++ ++ mux->offset = offset; ++ mux->lpl = id >= 0; ++ mux->has_safe_parent = true; ++ mux->safe_sel = 2; ++ mux->mask = 0x3; ++ mux->shift = 2; ++ mux->parent_map = sec_mux_map; ++ mux->hw.init = &init; ++ ++ init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); ++ if (!init.name) ++ return -ENOMEM; ++ ++ if (unique_aux) { ++ sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s); ++ if (!sec_mux_list[0]) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_aux; ++ } ++ } ++ ++ clk = devm_clk_register(dev, &mux->hw); ++ ++ if (unique_aux) ++ kfree(sec_mux_list[0]); ++err_aux: ++ kfree(init.name); ++ return PTR_ERR_OR_ZERO(clk); ++} ++ ++static struct clk * ++krait_add_pri_mux(struct device *dev, int id, const char *s, unsigned offset) ++{ ++ struct krait_mux_clk *mux; ++ const char *p_names[3]; ++ struct clk_init_data init = { ++ .parent_names = p_names, ++ .num_parents = ARRAY_SIZE(p_names), ++ .ops = &krait_mux_clk_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }; ++ struct clk *clk; ++ ++ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); ++ if (!mux) ++ return ERR_PTR(-ENOMEM); ++ ++ mux->has_safe_parent = true; ++ mux->safe_sel = 0; ++ mux->mask = 0x3; ++ mux->shift = 0; ++ mux->offset = offset; ++ mux->lpl = id >= 0; ++ mux->parent_map = pri_mux_map; ++ mux->hw.init = &init; ++ ++ init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s); ++ if (!init.name) ++ return ERR_PTR(-ENOMEM); ++ ++ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s); ++ if (!p_names[0]) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_p0; ++ } ++ ++ p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s); ++ if (!p_names[1]) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_p1; ++ } ++ ++ p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s); ++ if (!p_names[2]) { ++ clk = ERR_PTR(-ENOMEM); ++ goto err_p2; ++ } ++ ++ clk = devm_clk_register(dev, &mux->hw); ++ ++ kfree(p_names[2]); ++err_p2: ++ kfree(p_names[1]); ++err_p1: ++ kfree(p_names[0]); ++err_p0: ++ kfree(init.name); ++ return clk; ++} ++ ++/* id < 0 for L2, otherwise id == physical CPU number */ ++static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux) ++{ ++ int ret; ++ unsigned offset; ++ void *p = NULL; ++ const char *s; ++ struct clk *clk; ++ ++ if (id >= 0) { ++ offset = 0x4501 + (0x1000 * id); ++ s = p = kasprintf(GFP_KERNEL, "%d", id); ++ if (!s) ++ return ERR_PTR(-ENOMEM); ++ } else { ++ offset = 0x500; ++ s = "_l2"; ++ } ++ ++ ret = krait_add_div(dev, id, s, offset); ++ if (ret) { ++ clk = ERR_PTR(ret); ++ goto err; ++ } ++ ++ ret = krait_add_sec_mux(dev, id, s, offset, unique_aux); ++ if (ret) { ++ clk = ERR_PTR(ret); ++ goto err; ++ } ++ ++ clk = krait_add_pri_mux(dev, id, s, offset); ++err: ++ kfree(p); ++ return clk; ++} ++ ++static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) ++{ ++ unsigned int idx = clkspec->args[0]; ++ struct clk **clks = data; ++ ++ if (idx >= 5) { ++ pr_err("%s: invalid clock index %d\n", __func__, idx); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ return clks[idx] ? : ERR_PTR(-ENODEV); ++} ++ ++static const struct of_device_id krait_cc_match_table[] = { ++ { .compatible = "qcom,krait-cc-v1", (void *)1UL }, ++ { .compatible = "qcom,krait-cc-v2" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, krait_cc_match_table); ++ ++static int krait_cc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ const struct of_device_id *id; ++ unsigned long cur_rate, aux_rate; ++ int cpu; ++ struct clk *clk; ++ struct clk **clks; ++ struct clk *l2_pri_mux_clk; ++ ++ id = of_match_device(krait_cc_match_table, dev); ++ if (!id) ++ return -ENODEV; ++ ++ /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ ++ clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ ++ if (!id->data) { ++ clk = clk_register_fixed_factor(dev, "acpu_aux", ++ "gpll0_vote", 0, 1, 2); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ } ++ ++ /* Krait configurations have at most 4 CPUs and one L2 */ ++ clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL); ++ if (!clks) ++ return -ENOMEM; ++ ++ for_each_possible_cpu(cpu) { ++ clk = krait_add_clks(dev, cpu, id->data); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ clks[cpu] = clk; ++ } ++ ++ l2_pri_mux_clk = krait_add_clks(dev, -1, id->data); ++ if (IS_ERR(l2_pri_mux_clk)) ++ return PTR_ERR(l2_pri_mux_clk); ++ clks[4] = l2_pri_mux_clk; ++ ++ /* ++ * We don't want the CPU or L2 clocks to be turned off at late init ++ * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the ++ * refcount of these clocks. Any cpufreq/hotplug manager can assume ++ * that the clocks have already been prepared and enabled by the time ++ * they take over. ++ */ ++ for_each_online_cpu(cpu) { ++ clk_prepare_enable(l2_pri_mux_clk); ++ WARN(clk_prepare_enable(clks[cpu]), ++ "Unable to turn on CPU%d clock", cpu); ++ } ++ ++ /* ++ * Force reinit of HFPLLs and muxes to overwrite any potential ++ * incorrect configuration of HFPLLs and muxes by the bootloader. ++ * While at it, also make sure the cores are running at known rates ++ * and print the current rate. ++ * ++ * The clocks are set to aux clock rate first to make sure the ++ * secondary mux is not sourcing off of QSB. The rate is then set to ++ * two different rates to force a HFPLL reinit under all ++ * circumstances. ++ */ ++ cur_rate = clk_get_rate(l2_pri_mux_clk); ++ aux_rate = 384000000; ++ if (cur_rate == 1) { ++ pr_info("L2 @ QSB rate. Forcing new rate.\n"); ++ cur_rate = aux_rate; ++ } ++ clk_set_rate(l2_pri_mux_clk, aux_rate); ++ clk_set_rate(l2_pri_mux_clk, 2); ++ clk_set_rate(l2_pri_mux_clk, cur_rate); ++ pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000); ++ for_each_possible_cpu(cpu) { ++ clk = clks[cpu]; ++ cur_rate = clk_get_rate(clk); ++ if (cur_rate == 1) { ++ pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu); ++ cur_rate = aux_rate; ++ } ++ clk_set_rate(clk, aux_rate); ++ clk_set_rate(clk, 2); ++ clk_set_rate(clk, cur_rate); ++ pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); ++ } ++ ++ of_clk_add_provider(dev->of_node, krait_of_get, clks); ++ ++ return 0; ++} ++ ++static struct platform_driver krait_cc_driver = { ++ .probe = krait_cc_probe, ++ .driver = { ++ .name = "krait-cc", ++ .of_match_table = krait_cc_match_table, ++ }, ++}; ++module_platform_driver(krait_cc_driver); ++ ++MODULE_DESCRIPTION("Krait CPU Clock Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:krait-cc"); diff --git a/target/linux/ipq806x/patches-4.1/143-cpufreq-Add-module-to-register-cpufreq-on-Krait-CPUs.patch b/target/linux/ipq806x/patches-4.1/143-cpufreq-Add-module-to-register-cpufreq-on-Krait-CPUs.patch new file mode 100644 index 0000000..fd37c05 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/143-cpufreq-Add-module-to-register-cpufreq-on-Krait-CPUs.patch @@ -0,0 +1,304 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,12/13] cpufreq: Add module to register cpufreq on Krait CPUs +From: Stephen Boyd +X-Patchwork-Id: 6063191 +Message-Id: <1426920332-9340-13-git-send-email-sboyd@codeaurora.org> +To: Mike Turquette , Stephen Boyd +Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, + Viresh Kumar , +Date: Fri, 20 Mar 2015 23:45:31 -0700 + +Register a cpufreq-generic device whenever we detect that a +"qcom,krait" compatible CPU is present in DT. + +Cc: +Signed-off-by: Stephen Boyd + +--- +.../devicetree/bindings/arm/msm/qcom,pvs.txt | 38 ++++ + drivers/cpufreq/Kconfig.arm | 9 + + drivers/cpufreq/Makefile | 1 + + drivers/cpufreq/qcom-cpufreq.c | 204 +++++++++++++++++++++ + 4 files changed, 252 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt + create mode 100644 drivers/cpufreq/qcom-cpufreq.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt +@@ -0,0 +1,38 @@ ++Qualcomm Process Voltage Scaling Tables ++ ++The node name is required to be "qcom,pvs". There shall only be one ++such node present in the root of the tree. ++ ++PROPERTIES ++ ++- qcom,pvs-format-a or qcom,pvs-format-b: ++ Usage: required ++ Value type: ++ Definition: Indicates the format of qcom,speedX-pvsY-bin-vZ properties. ++ If qcom,pvs-format-a is used the table is two columns ++ (frequency and voltage in that order). If qcom,pvs-format-b is used the table is three columns (frequency, voltage, ++ and current in that order). ++ ++- qcom,speedX-pvsY-bin-vZ: ++ Usage: required ++ Value type: ++ Definition: The PVS table corresponding to the speed bin X, pvs bin Y, ++ and version Z. ++Example: ++ ++ qcom,pvs { ++ qcom,pvs-format-a; ++ qcom,speed0-pvs0-bin-v0 = ++ < 384000000 950000 >, ++ < 486000000 975000 >, ++ < 594000000 1000000 >, ++ < 702000000 1025000 >, ++ < 810000000 1075000 >, ++ < 918000000 1100000 >, ++ < 1026000000 1125000 >, ++ < 1134000000 1175000 >, ++ < 1242000000 1200000 >, ++ < 1350000000 1225000 >, ++ < 1458000000 1237500 >, ++ < 1512000000 1250000 >; ++ }; +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -146,6 +146,15 @@ config ARM_OMAP2PLUS_CPUFREQ + depends on ARCH_OMAP2PLUS + default ARCH_OMAP2PLUS + ++config ARM_QCOM_CPUFREQ ++ tristate "Qualcomm based" ++ depends on ARCH_QCOM ++ select PM_OPP ++ help ++ This adds the CPUFreq driver for Qualcomm SoC based boards. ++ ++ If in doubt, say N. ++ + config ARM_S3C_CPUFREQ + bool + help +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -66,6 +66,7 @@ obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += ki + obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o + obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o + obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o ++obj-$(CONFIG_ARM_QCOM_CPUFREQ) += qcom-cpufreq.o + obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o + obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o + obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o +--- /dev/null ++++ b/drivers/cpufreq/qcom-cpufreq.c +@@ -0,0 +1,204 @@ ++/* Copyright (c) 2014, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver) ++{ ++ void __iomem *base; ++ u32 pte_efuse; ++ ++ *speed = *pvs = *pvs_ver = 0; ++ ++ base = ioremap(0x007000c0, 4); ++ if (!base) { ++ pr_warn("Unable to read efuse data. Defaulting to 0!\n"); ++ return; ++ } ++ ++ pte_efuse = readl_relaxed(base); ++ iounmap(base); ++ ++ *speed = pte_efuse & 0xf; ++ if (*speed == 0xf) ++ *speed = (pte_efuse >> 4) & 0xf; ++ ++ if (*speed == 0xf) { ++ *speed = 0; ++ pr_warn("Speed bin: Defaulting to %d\n", *speed); ++ } else { ++ pr_info("Speed bin: %d\n", *speed); ++ } ++ ++ *pvs = (pte_efuse >> 10) & 0x7; ++ if (*pvs == 0x7) ++ *pvs = (pte_efuse >> 13) & 0x7; ++ ++ if (*pvs == 0x7) { ++ *pvs = 0; ++ pr_warn("PVS bin: Defaulting to %d\n", *pvs); ++ } else { ++ pr_info("PVS bin: %d\n", *pvs); ++ } ++} ++ ++static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver) ++{ ++ u32 pte_efuse, redundant_sel; ++ void __iomem *base; ++ ++ *speed = 0; ++ *pvs = 0; ++ *pvs_ver = 0; ++ ++ base = ioremap(0xfc4b80b0, 8); ++ if (!base) { ++ pr_warn("Unable to read efuse data. Defaulting to 0!\n"); ++ return; ++ } ++ ++ pte_efuse = readl_relaxed(base); ++ redundant_sel = (pte_efuse >> 24) & 0x7; ++ *speed = pte_efuse & 0x7; ++ /* 4 bits of PVS are in efuse register bits 31, 8-6. */ ++ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7); ++ *pvs_ver = (pte_efuse >> 4) & 0x3; ++ ++ switch (redundant_sel) { ++ case 1: ++ *speed = (pte_efuse >> 27) & 0xf; ++ break; ++ case 2: ++ *pvs = (pte_efuse >> 27) & 0xf; ++ break; ++ } ++ ++ /* Check SPEED_BIN_BLOW_STATUS */ ++ if (pte_efuse & BIT(3)) { ++ pr_info("Speed bin: %d\n", *speed); ++ } else { ++ pr_warn("Speed bin not set. Defaulting to 0!\n"); ++ *speed = 0; ++ } ++ ++ /* Check PVS_BLOW_STATUS */ ++ pte_efuse = readl_relaxed(base + 0x4) & BIT(21); ++ if (pte_efuse) { ++ pr_info("PVS bin: %d\n", *pvs); ++ } else { ++ pr_warn("PVS bin not set. Defaulting to 0!\n"); ++ *pvs = 0; ++ } ++ ++ pr_info("PVS version: %d\n", *pvs_ver); ++ iounmap(base); ++} ++ ++static int __init qcom_cpufreq_populate_opps(void) ++{ ++ int len, rows, cols, i, k, speed, pvs, pvs_ver; ++ char table_name[] = "qcom,speedXX-pvsXX-bin-vXX"; ++ struct device_node *np; ++ struct device *dev; ++ int cpu = 0; ++ ++ np = of_find_node_by_name(NULL, "qcom,pvs"); ++ if (!np) ++ return -ENODEV; ++ ++ if (of_property_read_bool(np, "qcom,pvs-format-a")) { ++ get_krait_bin_format_a(&speed, &pvs, &pvs_ver); ++ cols = 2; ++ } else if (of_property_read_bool(np, "qcom,pvs-format-b")) { ++ get_krait_bin_format_b(&speed, &pvs, &pvs_ver); ++ cols = 3; ++ } else { ++ return -ENODEV; ++ } ++ ++ snprintf(table_name, sizeof(table_name), ++ "qcom,speed%d-pvs%d-bin-v%d", speed, pvs, pvs_ver); ++ ++ if (!of_find_property(np, table_name, &len)) ++ return -EINVAL; ++ ++ len /= sizeof(u32); ++ if (len % cols || len == 0) ++ return -EINVAL; ++ ++ rows = len / cols; ++ ++ for (i = 0, k = 0; i < rows; i++) { ++ u32 freq, volt; ++ ++ of_property_read_u32_index(np, table_name, k++, &freq); ++ of_property_read_u32_index(np, table_name, k++, &volt); ++ while (k % cols) ++ k++; /* Skip uA entries if present */ ++ for (cpu = 0; cpu < num_possible_cpus(); cpu++) { ++ dev = get_cpu_device(cpu); ++ if (!dev) ++ return -ENODEV; ++ if (dev_pm_opp_add(dev, freq, volt)) ++ pr_warn("failed to add OPP %u\n", freq); ++ } ++ } ++ ++ return 0; ++} ++ ++static int __init qcom_cpufreq_driver_init(void) ++{ ++ struct cpufreq_dt_platform_data pdata = { .independent_clocks = true }; ++ struct platform_device_info devinfo = { ++ .name = "cpufreq-dt", ++ .data = &pdata, ++ .size_data = sizeof(pdata), ++ }; ++ struct device *cpu_dev; ++ struct device_node *np; ++ int ret; ++ ++ cpu_dev = get_cpu_device(0); ++ if (!cpu_dev) ++ return -ENODEV; ++ ++ np = of_node_get(cpu_dev->of_node); ++ if (!np) ++ return -ENOENT; ++ ++ if (!of_device_is_compatible(np, "qcom,krait")) { ++ of_node_put(np); ++ return -ENODEV; ++ } ++ of_node_put(np); ++ ++ ret = qcom_cpufreq_populate_opps(); ++ if (ret) ++ return ret; ++ ++ return PTR_ERR_OR_ZERO(platform_device_register_full(&devinfo)); ++} ++module_init(qcom_cpufreq_driver_init); ++ ++MODULE_DESCRIPTION("Qualcomm CPUfreq driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-4.1/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch b/target/linux/ipq806x/patches-4.1/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch new file mode 100644 index 0000000..9435de6 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/144-ARM-dts-qcom-Add-necessary-DT-data-for-Krait-cpufreq.patch @@ -0,0 +1,100 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -25,6 +25,11 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; ++ clocks = <&kraitcc 0>; ++ clock-names = "cpu"; ++ clock-latency = <100000>; ++ core-supply = <&smb208_s2a>; ++ voltage-tolerance = <5>; + }; + + cpu@1 { +@@ -35,11 +40,24 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; ++ clocks = <&kraitcc 1>; ++ clock-names = "cpu"; ++ clock-latency = <100000>; ++ core-supply = <&smb208_s2b>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; ++ clocks = <&kraitcc 4>; ++ clock-names = "cache"; ++ cache-points-kHz = < ++ /* kHz uV CPU kHz */ ++ 1200000 1150000 1200000 ++ 1000000 1100000 600000 ++ 384000 1100000 384000 ++ >; ++ vdd_dig-supply = <&smb208_s1a>; + }; + }; + +@@ -72,6 +90,46 @@ + }; + }; + ++ kraitcc: clock-controller { ++ compatible = "qcom,krait-cc-v1"; ++ #clock-cells = <1>; ++ }; ++ ++ qcom,pvs { ++ qcom,pvs-format-a; ++ qcom,speed0-pvs0-bin-v0 = ++ < 1400000000 1250000 >, ++ < 1200000000 1200000 >, ++ < 1000000000 1150000 >, ++ < 800000000 1100000 >, ++ < 600000000 1050000 >, ++ < 384000000 1000000 >; ++ ++ qcom,speed0-pvs1-bin-v0 = ++ < 1400000000 1175000 >, ++ < 1200000000 1125000 >, ++ < 1000000000 1075000 >, ++ < 800000000 1025000 >, ++ < 600000000 975000 >, ++ < 384000000 925000 >; ++ ++ qcom,speed0-pvs2-bin-v0 = ++ < 1400000000 1125000 >, ++ < 1200000000 1075000 >, ++ < 1000000000 1025000 >, ++ < 800000000 995000 >, ++ < 600000000 925000 >, ++ < 384000000 875000 >; ++ ++ qcom,speed0-pvs3-bin-v0 = ++ < 1400000000 1050000 >, ++ < 1200000000 1000000 >, ++ < 1000000000 950000 >, ++ < 800000000 900000 >, ++ < 600000000 850000 >, ++ < 384000000 800000 >; ++ }; ++ + soc: soc { + #address-cells = <1>; + #size-cells = <1>; +@@ -187,11 +245,13 @@ + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; ++ clock-output-names = "acpu0_aux"; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; ++ clock-output-names = "acpu1_aux"; + }; + + l2cc: clock-controller@2011000 { diff --git a/target/linux/ipq806x/patches-4.1/145-cpufreq-Add-a-cpufreq-krait-based-on-cpufre.patch b/target/linux/ipq806x/patches-4.1/145-cpufreq-Add-a-cpufreq-krait-based-on-cpufre.patch new file mode 100644 index 0000000..84f856b --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/145-cpufreq-Add-a-cpufreq-krait-based-on-cpufre.patch @@ -0,0 +1,461 @@ +From dd77db4143290689d3a5e1ec61627233d0711b66 Mon Sep 17 00:00:00 2001 +From: Stephen Boyd +Date: Fri, 30 May 2014 16:36:11 -0700 +Subject: [PATCH] FROMLIST: cpufreq: Add a cpufreq-krait based on cpufreq-cpu0 + +Krait processors have individual clocks for each CPU that can +scale independently from one another. cpufreq-cpu0 is fairly +close to this, but assumes that there is only one clock for all +CPUs. Add a driver to support the Krait configuration. + +TODO: Merge into cpufreq-cpu0? Or make generic? + +Signed-off-by: Stephen Boyd + +--- + drivers/cpufreq/Kconfig | 13 +++ + drivers/cpufreq/Makefile | 1 + + drivers/cpufreq/cpufreq-krait.c | 190 ++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 204 insertions(+) + create mode 100644 drivers/cpufreq/cpufreq-krait.c + +--- a/drivers/cpufreq/Kconfig ++++ b/drivers/cpufreq/Kconfig +@@ -198,6 +198,19 @@ config CPUFREQ_DT + + If in doubt, say N. + ++config GENERIC_CPUFREQ_KRAIT ++ tristate "Krait cpufreq driver" ++ depends on HAVE_CLK && OF ++ # if CPU_THERMAL is on and THERMAL=m, CPU0 cannot be =y: ++ depends on !CPU_THERMAL || THERMAL ++ select PM_OPP ++ help ++ This adds a generic cpufreq driver for CPU0 frequency management. ++ It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) ++ systems which share clock and voltage across all CPUs. ++ ++ If in doubt, say N. ++ + if X86 + source "drivers/cpufreq/Kconfig.x86" + endif +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -14,6 +14,7 @@ obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE) + obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o + + obj-$(CONFIG_CPUFREQ_DT) += cpufreq-dt.o ++obj-$(CONFIG_GENERIC_CPUFREQ_KRAIT) += cpufreq-krait.o + + ################################################################################## + # x86 drivers. +--- /dev/null ++++ b/drivers/cpufreq/cpufreq-krait.c +@@ -0,0 +1,390 @@ ++/* ++ * Copyright (C) 2012 Freescale Semiconductor, Inc. ++ * Copyright (c) 2014, The Linux Foundation. All rights reserved. ++ * ++ * The OPP code in function krait_set_target() is reused from ++ * drivers/cpufreq/omap-cpufreq.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static unsigned int transition_latency; ++static unsigned int voltage_tolerance; /* in percentage */ ++ ++static struct device *cpu_dev; ++static DEFINE_PER_CPU(struct clk *, krait_cpu_clks); ++static DEFINE_PER_CPU(struct regulator *, krait_supply_core); ++static struct cpufreq_frequency_table *freq_table; ++static struct thermal_cooling_device *cdev; ++ ++struct cache_points { ++ unsigned long cache_freq; ++ unsigned int cache_volt; ++ unsigned long cpu_freq; ++}; ++ ++static struct regulator *krait_l2_reg; ++static struct clk *krait_l2_clk; ++static struct cache_points *krait_l2_points; ++static int nr_krait_l2_points; ++ ++static int krait_parse_cache_points(struct device *dev, ++ struct device_node *of_node) ++{ ++ const struct property *prop; ++ const __be32 *val; ++ int nr, i; ++ ++ prop = of_find_property(of_node, "cache-points-kHz", NULL); ++ if (!prop) ++ return -ENODEV; ++ if (!prop->value) ++ return -ENODATA; ++ ++ /* ++ * Each OPP is a set of tuples consisting of frequency and ++ * cpu-frequency like . ++ */ ++ nr = prop->length / sizeof(u32); ++ if (nr % 3) { ++ dev_err(dev, "%s: Invalid cache points\n", __func__); ++ return -EINVAL; ++ } ++ nr /= 3; ++ ++ krait_l2_points = devm_kcalloc(dev, nr, sizeof(*krait_l2_points), ++ GFP_KERNEL); ++ if (!krait_l2_points) ++ return -ENOMEM; ++ nr_krait_l2_points = nr; ++ ++ for (i = 0, val = prop->value; i < nr; i++) { ++ unsigned long cache_freq = be32_to_cpup(val++) * 1000; ++ unsigned int cache_volt = be32_to_cpup(val++); ++ unsigned long cpu_freq = be32_to_cpup(val++) * 1000; ++ ++ krait_l2_points[i].cache_freq = cache_freq; ++ krait_l2_points[i].cache_volt = cache_volt; ++ krait_l2_points[i].cpu_freq = cpu_freq; ++ } ++ ++ return 0; ++} ++ ++static int krait_set_target(struct cpufreq_policy *policy, unsigned int index) ++{ ++ struct dev_pm_opp *opp; ++ unsigned long volt = 0, volt_old = 0, tol = 0; ++ unsigned long freq, max_cpu_freq = 0; ++ unsigned int old_freq, new_freq; ++ long freq_Hz, freq_exact; ++ int ret, i; ++ struct clk *cpu_clk; ++ struct regulator *core; ++ unsigned int cpu; ++ ++ cpu_clk = per_cpu(krait_cpu_clks, policy->cpu); ++ ++ freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); ++ if (freq_Hz <= 0) ++ freq_Hz = freq_table[index].frequency * 1000; ++ ++ freq_exact = freq_Hz; ++ new_freq = freq_Hz / 1000; ++ old_freq = clk_get_rate(cpu_clk) / 1000; ++ ++ core = per_cpu(krait_supply_core, policy->cpu); ++ ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("failed to find OPP for %ld\n", freq_Hz); ++ return PTR_ERR(opp); ++ } ++ volt = dev_pm_opp_get_voltage(opp); ++ rcu_read_unlock(); ++ tol = volt * voltage_tolerance / 100; ++ volt_old = regulator_get_voltage(core); ++ ++ pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n", ++ old_freq / 1000, volt_old ? volt_old / 1000 : -1, ++ new_freq / 1000, volt ? volt / 1000 : -1); ++ ++ /* scaling up? scale voltage before frequency */ ++ if (new_freq > old_freq) { ++ ret = regulator_set_voltage_tol(core, volt, tol); ++ if (ret) { ++ pr_err("failed to scale voltage up: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ ret = clk_set_rate(cpu_clk, freq_exact); ++ if (ret) { ++ pr_err("failed to set clock rate: %d\n", ret); ++ return ret; ++ } ++ ++ /* scaling down? scale voltage after frequency */ ++ if (new_freq < old_freq) { ++ ret = regulator_set_voltage_tol(core, volt, tol); ++ if (ret) { ++ pr_err("failed to scale voltage down: %d\n", ret); ++ clk_set_rate(cpu_clk, old_freq * 1000); ++ } ++ } ++ ++ for_each_possible_cpu(cpu) { ++ freq = clk_get_rate(per_cpu(krait_cpu_clks, cpu)); ++ max_cpu_freq = max(max_cpu_freq, freq); ++ } ++ ++ for (i = 0; i < nr_krait_l2_points; i++) { ++ if (max_cpu_freq >= krait_l2_points[i].cpu_freq) { ++ if (krait_l2_reg) { ++ ret = regulator_set_voltage_tol(krait_l2_reg, ++ krait_l2_points[i].cache_volt, ++ tol); ++ if (ret) { ++ pr_err("failed to scale l2 voltage: %d\n", ++ ret); ++ } ++ } ++ ret = clk_set_rate(krait_l2_clk, ++ krait_l2_points[i].cache_freq); ++ if (ret) ++ pr_err("failed to scale l2 clk: %d\n", ret); ++ break; ++ } ++ ++ } ++ ++ return ret; ++} ++ ++static int krait_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ int ret; ++ ++ policy->clk = per_cpu(krait_cpu_clks, policy->cpu); ++ ++ ret = cpufreq_table_validate_and_show(policy, freq_table); ++ if (ret) { ++ pr_err("%s: invalid frequency table: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ policy->cpuinfo.transition_latency = transition_latency; ++ ++ return 0; ++} ++ ++static struct cpufreq_driver krait_cpufreq_driver = { ++ .flags = CPUFREQ_STICKY, ++ .verify = cpufreq_generic_frequency_table_verify, ++ .target_index = krait_set_target, ++ .get = cpufreq_generic_get, ++ .init = krait_cpufreq_init, ++ .name = "generic_krait", ++ .attr = cpufreq_generic_attr, ++}; ++ ++static int krait_cpufreq_probe(struct platform_device *pdev) ++{ ++ struct device_node *np, *cache; ++ int ret, i; ++ unsigned int cpu; ++ struct device *dev; ++ struct clk *clk; ++ struct regulator *core; ++ unsigned long freq_Hz, freq, max_cpu_freq = 0; ++ struct dev_pm_opp *opp; ++ unsigned long volt, tol; ++ ++ cpu_dev = get_cpu_device(0); ++ if (!cpu_dev) { ++ pr_err("failed to get krait device\n"); ++ return -ENODEV; ++ } ++ ++ np = of_node_get(cpu_dev->of_node); ++ if (!np) { ++ pr_err("failed to find krait node\n"); ++ return -ENOENT; ++ } ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); ++ if (ret) { ++ pr_err("failed to init cpufreq table: %d\n", ret); ++ goto out_put_node; ++ } ++ ++ of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance); ++ ++ if (of_property_read_u32(np, "clock-latency", &transition_latency)) ++ transition_latency = CPUFREQ_ETERNAL; ++ ++ cache = of_find_next_cache_node(np); ++ if (cache) { ++ struct device_node *vdd; ++ ++ vdd = of_parse_phandle(cache, "vdd_dig-supply", 0); ++ if (vdd) { ++ krait_l2_reg = regulator_get(NULL, vdd->name); ++ if (IS_ERR(krait_l2_reg)) { ++ pr_warn("failed to get l2 vdd_dig supply\n"); ++ krait_l2_reg = NULL; ++ } ++ of_node_put(vdd); ++ } ++ ++ krait_l2_clk = of_clk_get(cache, 0); ++ if (!IS_ERR(krait_l2_clk)) { ++ ret = krait_parse_cache_points(&pdev->dev, cache); ++ if (ret) ++ clk_put(krait_l2_clk); ++ } ++ if (IS_ERR(krait_l2_clk) || ret) ++ krait_l2_clk = NULL; ++ } ++ ++ for_each_possible_cpu(cpu) { ++ dev = get_cpu_device(cpu); ++ if (!dev) { ++ pr_err("failed to get krait device\n"); ++ ret = -ENOENT; ++ goto out_free_table; ++ } ++ per_cpu(krait_cpu_clks, cpu) = clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(clk)) { ++ ret = PTR_ERR(clk); ++ goto out_free_table; ++ } ++ core = devm_regulator_get(dev, "core"); ++ if (IS_ERR(core)) { ++ pr_debug("failed to get core regulator\n"); ++ ret = PTR_ERR(core); ++ goto out_free_table; ++ } ++ per_cpu(krait_supply_core, cpu) = core; ++ ++ freq = freq_Hz = clk_get_rate(clk); ++ ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("failed to find OPP for %ld\n", freq_Hz); ++ ret = PTR_ERR(opp); ++ goto out_free_table; ++ } ++ volt = dev_pm_opp_get_voltage(opp); ++ rcu_read_unlock(); ++ ++ tol = volt * voltage_tolerance / 100; ++ ret = regulator_set_voltage_tol(core, volt, tol); ++ if (ret) { ++ pr_err("failed to scale voltage up: %d\n", ret); ++ goto out_free_table; ++ } ++ ret = regulator_enable(core); ++ if (ret) { ++ pr_err("failed to enable regulator: %d\n", ret); ++ goto out_free_table; ++ } ++ max_cpu_freq = max(max_cpu_freq, freq); ++ } ++ ++ for (i = 0; i < nr_krait_l2_points; i++) { ++ if (max_cpu_freq >= krait_l2_points[i].cpu_freq) { ++ if (krait_l2_reg) { ++ ret = regulator_set_voltage_tol(krait_l2_reg, ++ krait_l2_points[i].cache_volt, ++ tol); ++ if (ret) ++ pr_err("failed to scale l2 voltage: %d\n", ++ ret); ++ ret = regulator_enable(krait_l2_reg); ++ if (ret) ++ pr_err("failed to enable l2 voltage: %d\n", ++ ret); ++ } ++ break; ++ } ++ ++ } ++ ++ ret = cpufreq_register_driver(&krait_cpufreq_driver); ++ if (ret) { ++ pr_err("failed register driver: %d\n", ret); ++ goto out_free_table; ++ } ++ of_node_put(np); ++ ++ /* ++ * For now, just loading the cooling device; ++ * thermal DT code takes care of matching them. ++ */ ++ for_each_possible_cpu(cpu) { ++ dev = get_cpu_device(cpu); ++ np = of_node_get(dev->of_node); ++ if (of_find_property(np, "#cooling-cells", NULL)) { ++ cdev = of_cpufreq_cooling_register(np, cpumask_of(cpu)); ++ if (IS_ERR(cdev)) ++ pr_err("running cpufreq without cooling device: %ld\n", ++ PTR_ERR(cdev)); ++ } ++ of_node_put(np); ++ } ++ ++ return 0; ++ ++out_free_table: ++ regulator_put(krait_l2_reg); ++ clk_put(krait_l2_clk); ++ dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); ++out_put_node: ++ of_node_put(np); ++ return ret; ++} ++ ++static int krait_cpufreq_remove(struct platform_device *pdev) ++{ ++ cpufreq_cooling_unregister(cdev); ++ cpufreq_unregister_driver(&krait_cpufreq_driver); ++ dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); ++ clk_put(krait_l2_clk); ++ regulator_put(krait_l2_reg); ++ ++ return 0; ++} ++ ++static struct platform_driver krait_cpufreq_platdrv = { ++ .driver = { ++ .name = "cpufreq-krait", ++ .owner = THIS_MODULE, ++ }, ++ .probe = krait_cpufreq_probe, ++ .remove = krait_cpufreq_remove, ++}; ++module_platform_driver(krait_cpufreq_platdrv); ++ ++MODULE_DESCRIPTION("Krait CPUfreq driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/cpufreq/qcom-cpufreq.c ++++ b/drivers/cpufreq/qcom-cpufreq.c +@@ -168,11 +168,8 @@ static int __init qcom_cpufreq_populate_ + + static int __init qcom_cpufreq_driver_init(void) + { +- struct cpufreq_dt_platform_data pdata = { .independent_clocks = true }; + struct platform_device_info devinfo = { +- .name = "cpufreq-dt", +- .data = &pdata, +- .size_data = sizeof(pdata), ++ .name = "cpufreq-krait", + }; + struct device *cpu_dev; + struct device_node *np; diff --git a/target/linux/ipq806x/patches-4.1/155-dt-bindings-qcom_adm-Fix-channel-specifiers.patch b/target/linux/ipq806x/patches-4.1/155-dt-bindings-qcom_adm-Fix-channel-specifiers.patch new file mode 100644 index 0000000..4f5c0ef --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/155-dt-bindings-qcom_adm-Fix-channel-specifiers.patch @@ -0,0 +1,76 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v6,1/2] dt/bindings: qcom_adm: Fix channel specifiers +From: Andy Gross +X-Patchwork-Id: 6027361 +Message-Id: <1426571172-9711-2-git-send-email-agross@codeaurora.org> +To: Vinod Koul +Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, + linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, Kumar Gala , + Bjorn Andersson , + Andy Gross +Date: Tue, 17 Mar 2015 00:46:11 -0500 + +This patch removes the crci information from the dma channel property. At least +one client device requires using more than one CRCI value for a channel. This +does not match the current binding and the crci information needs to be removed. + +Instead, the client device will provide this information via other means. + +Signed-off-by: Andy Gross + +--- +Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++---------- + 1 file changed, 6 insertions(+), 10 deletions(-) + +--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt ++++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt +@@ -4,8 +4,7 @@ Required properties: + - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 + - reg: Address range for DMA registers + - interrupts: Should contain one interrupt shared by all channels +-- #dma-cells: must be <2>. First cell denotes the channel number. Second cell +- denotes CRCI (client rate control interface) flow control assignment. ++- #dma-cells: must be <1>. First cell denotes the channel number. + - clocks: Should contain the core clock and interface clock. + - clock-names: Must contain "core" for the core clock and "iface" for the + interface clock. +@@ -22,7 +21,7 @@ Example: + compatible = "qcom,adm"; + reg = <0x18300000 0x100000>; + interrupts = <0 170 0>; +- #dma-cells = <2>; ++ #dma-cells = <1>; + + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; + clock-names = "core", "iface"; +@@ -35,15 +34,12 @@ Example: + qcom,ee = <0>; + }; + +-DMA clients must use the format descripted in the dma.txt file, using a three ++DMA clients must use the format descripted in the dma.txt file, using a two + cell specifier for each channel. + +-Each dmas request consists of 3 cells: ++Each dmas request consists of two cells: + 1. phandle pointing to the DMA controller + 2. channel number +- 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. +- The CRCI is used for flow control. It identifies the peripheral device that +- is the source/destination for the transferred data. + + Example: + +@@ -56,7 +52,7 @@ Example: + + cs-gpios = <&qcom_pinmux 20 0>; + +- dmas = <&adm_dma 6 9>, +- <&adm_dma 5 10>; ++ dmas = <&adm_dma 6>, ++ <&adm_dma 5>; + dma-names = "rx", "tx"; + }; diff --git a/target/linux/ipq806x/patches-4.1/156-dmaengine-Add-ADM-driver.patch b/target/linux/ipq806x/patches-4.1/156-dmaengine-Add-ADM-driver.patch new file mode 100644 index 0000000..29e8eaa --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/156-dmaengine-Add-ADM-driver.patch @@ -0,0 +1,962 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v6,2/2] dmaengine: Add ADM driver +From: Andy Gross +X-Patchwork-Id: 6027351 +Message-Id: <1426571172-9711-3-git-send-email-agross@codeaurora.org> +To: Vinod Koul +Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, + linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, Kumar Gala , + Bjorn Andersson , + Andy Gross +Date: Tue, 17 Mar 2015 00:46:12 -0500 + +Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA +controller found in the MSM8x60 and IPQ/APQ8064 platforms. + +The ADM supports both memory to memory transactions and memory +to/from peripheral device transactions. The controller also provides flow +control capabilities for transactions to/from peripheral devices. + +The initial release of this driver supports slave transfers to/from peripherals +and also incorporates CRCI (client rate control interface) flow control. + +Signed-off-by: Andy Gross +Reviewed-by: sricharan + +--- +drivers/dma/Kconfig | 10 + + drivers/dma/Makefile | 1 + + drivers/dma/qcom_adm.c | 900 ++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 911 insertions(+) + create mode 100644 drivers/dma/qcom_adm.c + +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -492,4 +492,14 @@ config QCOM_BAM_DMA + Enable support for the QCOM BAM DMA controller. This controller + provides DMA capabilities for a variety of on-chip devices. + ++config QCOM_ADM ++ tristate "Qualcomm ADM support" ++ depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) ++ select DMA_ENGINE ++ select DMA_VIRTUAL_CHANNELS ++ ---help--- ++ Enable support for the Qualcomm ADM DMA controller. This controller ++ provides DMA capabilities for both general purpose and on-chip ++ peripheral devices. ++ + endif +--- /dev/null ++++ b/drivers/dma/qcom_adm.c +@@ -0,0 +1,900 @@ ++/* ++ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 and ++ * only version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dmaengine.h" ++#include "virt-dma.h" ++ ++/* ADM registers - calculated from channel number and security domain */ ++#define ADM_CHAN_MULTI 0x4 ++#define ADM_CI_MULTI 0x4 ++#define ADM_CRCI_MULTI 0x4 ++#define ADM_EE_MULTI 0x800 ++#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan) ++#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * ee) ++#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee)) ++#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan) ++#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci)) ++#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan)) ++#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee)) ++#define ADM_CI_CONF(ci) (0x390 + ci * ADM_CI_MULTI) ++#define ADM_GP_CTL 0x3d8 ++#define ADM_CRCI_CTL(crci, ee) (0x400 + crci * ADM_CRCI_MULTI + \ ++ ADM_EE_OFFS(ee)) ++ ++/* channel status */ ++#define ADM_CH_STATUS_VALID BIT(1) ++ ++/* channel result */ ++#define ADM_CH_RSLT_VALID BIT(31) ++#define ADM_CH_RSLT_ERR BIT(3) ++#define ADM_CH_RSLT_FLUSH BIT(2) ++#define ADM_CH_RSLT_TPD BIT(1) ++ ++/* channel conf */ ++#define ADM_CH_CONF_SHADOW_EN BIT(12) ++#define ADM_CH_CONF_MPU_DISABLE BIT(11) ++#define ADM_CH_CONF_PERM_MPU_CONF BIT(9) ++#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7) ++#define ADM_CH_CONF_SEC_DOMAIN(ee) (((ee & 0x3) << 4) | ((ee & 0x4) << 11)) ++ ++/* channel result conf */ ++#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1) ++#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0) ++ ++/* CRCI CTL */ ++#define ADM_CRCI_CTL_MUX_SEL BIT(18) ++#define ADM_CRCI_CTL_RST BIT(17) ++ ++/* CI configuration */ ++#define ADM_CI_RANGE_END(x) (x << 24) ++#define ADM_CI_RANGE_START(x) (x << 16) ++#define ADM_CI_BURST_4_WORDS BIT(2) ++#define ADM_CI_BURST_8_WORDS BIT(3) ++ ++/* GP CTL */ ++#define ADM_GP_CTL_LP_EN BIT(12) ++#define ADM_GP_CTL_LP_CNT(x) (x << 8) ++ ++/* Command pointer list entry */ ++#define ADM_CPLE_LP BIT(31) ++#define ADM_CPLE_CMD_PTR_LIST BIT(29) ++ ++/* Command list entry */ ++#define ADM_CMD_LC BIT(31) ++#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7) ++#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3) ++ ++#define ADM_CMD_TYPE_SINGLE 0x0 ++#define ADM_CMD_TYPE_BOX 0x3 ++ ++#define ADM_CRCI_MUX_SEL BIT(4) ++#define ADM_DESC_ALIGN 8 ++#define ADM_MAX_XFER (SZ_64K-1) ++#define ADM_MAX_ROWS (SZ_64K-1) ++#define ADM_MAX_CHANNELS 16 ++ ++struct adm_desc_hw_box { ++ u32 cmd; ++ u32 src_addr; ++ u32 dst_addr; ++ u32 row_len; ++ u32 num_rows; ++ u32 row_offset; ++}; ++ ++struct adm_desc_hw_single { ++ u32 cmd; ++ u32 src_addr; ++ u32 dst_addr; ++ u32 len; ++}; ++ ++struct adm_async_desc { ++ struct virt_dma_desc vd; ++ struct adm_device *adev; ++ ++ size_t length; ++ enum dma_transfer_direction dir; ++ dma_addr_t dma_addr; ++ size_t dma_len; ++ ++ void *cpl; ++ dma_addr_t cp_addr; ++ u32 crci; ++ u32 mux; ++ u32 blk_size; ++}; ++ ++struct adm_chan { ++ struct virt_dma_chan vc; ++ struct adm_device *adev; ++ ++ /* parsed from DT */ ++ u32 id; /* channel id */ ++ ++ struct adm_async_desc *curr_txd; ++ struct dma_slave_config slave; ++ struct list_head node; ++ ++ int error; ++ int initialized; ++}; ++ ++static inline struct adm_chan *to_adm_chan(struct dma_chan *common) ++{ ++ return container_of(common, struct adm_chan, vc.chan); ++} ++ ++struct adm_device { ++ void __iomem *regs; ++ struct device *dev; ++ struct dma_device common; ++ struct device_dma_parameters dma_parms; ++ struct adm_chan *channels; ++ ++ u32 ee; ++ ++ struct clk *core_clk; ++ struct clk *iface_clk; ++ ++ struct reset_control *clk_reset; ++ struct reset_control *c0_reset; ++ struct reset_control *c1_reset; ++ struct reset_control *c2_reset; ++ int irq; ++}; ++ ++/** ++ * adm_free_chan - Frees dma resources associated with the specific channel ++ * ++ * Free all allocated descriptors associated with this channel ++ * ++ */ ++static void adm_free_chan(struct dma_chan *chan) ++{ ++ /* free all queued descriptors */ ++ vchan_free_chan_resources(to_virt_chan(chan)); ++} ++ ++/** ++ * adm_get_blksize - Get block size from burst value ++ * ++ */ ++static int adm_get_blksize(unsigned int burst) ++{ ++ int ret; ++ ++ switch (burst) { ++ case 16: ++ case 32: ++ case 64: ++ case 128: ++ ret = ffs(burst>>4) - 1; ++ break; ++ case 192: ++ ret = 4; ++ break; ++ case 256: ++ ret = 5; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++/** ++ * adm_process_fc_descriptors - Process descriptors for flow controlled xfers ++ * ++ * @achan: ADM channel ++ * @desc: Descriptor memory pointer ++ * @sg: Scatterlist entry ++ * @crci: CRCI value ++ * @burst: Burst size of transaction ++ * @direction: DMA transfer direction ++ */ ++static void *adm_process_fc_descriptors(struct adm_chan *achan, ++ void *desc, struct scatterlist *sg, u32 crci, u32 burst, ++ enum dma_transfer_direction direction) ++{ ++ struct adm_desc_hw_box *box_desc = NULL; ++ struct adm_desc_hw_single *single_desc; ++ u32 remainder = sg_dma_len(sg); ++ u32 rows, row_offset, crci_cmd; ++ u32 mem_addr = sg_dma_address(sg); ++ u32 *incr_addr = &mem_addr; ++ u32 *src, *dst; ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ crci_cmd = ADM_CMD_SRC_CRCI(crci); ++ row_offset = burst; ++ src = &achan->slave.src_addr; ++ dst = &mem_addr; ++ } else { ++ crci_cmd = ADM_CMD_DST_CRCI(crci); ++ row_offset = burst << 16; ++ src = &mem_addr; ++ dst = &achan->slave.dst_addr; ++ } ++ ++ while (remainder >= burst) { ++ box_desc = desc; ++ box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd; ++ box_desc->row_offset = row_offset; ++ box_desc->src_addr = *src; ++ box_desc->dst_addr = *dst; ++ ++ rows = remainder / burst; ++ rows = min_t(u32, rows, ADM_MAX_ROWS); ++ box_desc->num_rows = rows << 16 | rows; ++ box_desc->row_len = burst << 16 | burst; ++ ++ *incr_addr += burst * rows; ++ remainder -= burst * rows; ++ desc += sizeof(*box_desc); ++ } ++ ++ /* if leftover bytes, do one single descriptor */ ++ if (remainder) { ++ single_desc = desc; ++ single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd; ++ single_desc->len = remainder; ++ single_desc->src_addr = *src; ++ single_desc->dst_addr = *dst; ++ desc += sizeof(*single_desc); ++ ++ if (sg_is_last(sg)) ++ single_desc->cmd |= ADM_CMD_LC; ++ } else { ++ if (box_desc && sg_is_last(sg)) ++ box_desc->cmd |= ADM_CMD_LC; ++ } ++ ++ return desc; ++} ++ ++/** ++ * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers ++ * ++ * @achan: ADM channel ++ * @desc: Descriptor memory pointer ++ * @sg: Scatterlist entry ++ * @direction: DMA transfer direction ++ */ ++static void *adm_process_non_fc_descriptors(struct adm_chan *achan, ++ void *desc, struct scatterlist *sg, ++ enum dma_transfer_direction direction) ++{ ++ struct adm_desc_hw_single *single_desc; ++ u32 remainder = sg_dma_len(sg); ++ u32 mem_addr = sg_dma_address(sg); ++ u32 *incr_addr = &mem_addr; ++ u32 *src, *dst; ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ src = &achan->slave.src_addr; ++ dst = &mem_addr; ++ } else { ++ src = &mem_addr; ++ dst = &achan->slave.dst_addr; ++ } ++ ++ do { ++ single_desc = desc; ++ single_desc->cmd = ADM_CMD_TYPE_SINGLE; ++ single_desc->src_addr = *src; ++ single_desc->dst_addr = *dst; ++ single_desc->len = (remainder > ADM_MAX_XFER) ? ++ ADM_MAX_XFER : remainder; ++ ++ remainder -= single_desc->len; ++ *incr_addr += single_desc->len; ++ desc += sizeof(*single_desc); ++ } while (remainder); ++ ++ /* set last command if this is the end of the whole transaction */ ++ if (sg_is_last(sg)) ++ single_desc->cmd |= ADM_CMD_LC; ++ ++ return desc; ++} ++ ++/** ++ * adm_prep_slave_sg - Prep slave sg transaction ++ * ++ * @chan: dma channel ++ * @sgl: scatter gather list ++ * @sg_len: length of sg ++ * @direction: DMA transfer direction ++ * @flags: DMA flags ++ * @context: transfer context (unused) ++ */ ++static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan, ++ struct scatterlist *sgl, unsigned int sg_len, ++ enum dma_transfer_direction direction, unsigned long flags, ++ void *context) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct adm_device *adev = achan->adev; ++ struct adm_async_desc *async_desc; ++ struct scatterlist *sg; ++ u32 i, burst; ++ u32 single_count = 0, box_count = 0, crci = 0; ++ void *desc; ++ u32 *cple; ++ int blk_size = 0; ++ ++ if (!is_slave_direction(direction)) { ++ dev_err(adev->dev, "invalid dma direction\n"); ++ return NULL; ++ } ++ ++ /* ++ * get burst value from slave configuration ++ */ ++ burst = (direction == DMA_MEM_TO_DEV) ? ++ achan->slave.dst_maxburst : ++ achan->slave.src_maxburst; ++ ++ /* if using flow control, validate burst and crci values */ ++ if (achan->slave.device_fc) { ++ ++ blk_size = adm_get_blksize(burst); ++ if (blk_size < 0) { ++ dev_err(adev->dev, "invalid burst value: %d\n", ++ burst); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ crci = achan->slave.slave_id & 0xf; ++ if (!crci || achan->slave.slave_id > 0x1f) { ++ dev_err(adev->dev, "invalid crci value\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ } ++ ++ /* iterate through sgs and compute allocation size of structures */ ++ for_each_sg(sgl, sg, sg_len, i) { ++ if (achan->slave.device_fc) { ++ box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst, ++ ADM_MAX_ROWS); ++ if (sg_dma_len(sg) % burst) ++ single_count++; ++ } else { ++ single_count += DIV_ROUND_UP(sg_dma_len(sg), ++ ADM_MAX_XFER); ++ } ++ } ++ ++ async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT); ++ if (!async_desc) ++ return ERR_PTR(-ENOMEM); ++ ++ if (crci) ++ async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ? ++ ADM_CRCI_CTL_MUX_SEL : 0; ++ async_desc->crci = crci; ++ async_desc->blk_size = blk_size; ++ async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) + ++ box_count * sizeof(struct adm_desc_hw_box) + ++ sizeof(*cple) + 2 * ADM_DESC_ALIGN; ++ ++ async_desc->cpl = dma_alloc_writecombine(adev->dev, async_desc->dma_len, ++ &async_desc->dma_addr, GFP_NOWAIT); ++ ++ if (!async_desc->cpl) { ++ kfree(async_desc); ++ return ERR_PTR(-ENOMEM); ++ } ++ ++ async_desc->adev = adev; ++ ++ /* both command list entry and descriptors must be 8 byte aligned */ ++ cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN); ++ desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN); ++ ++ /* init cmd list */ ++ *cple = ADM_CPLE_LP; ++ *cple |= (desc - async_desc->cpl + async_desc->dma_addr) >> 3; ++ ++ for_each_sg(sgl, sg, sg_len, i) { ++ async_desc->length += sg_dma_len(sg); ++ ++ if (achan->slave.device_fc) ++ desc = adm_process_fc_descriptors(achan, desc, sg, crci, ++ burst, direction); ++ else ++ desc = adm_process_non_fc_descriptors(achan, desc, sg, ++ direction); ++ } ++ ++ return vchan_tx_prep(&achan->vc, &async_desc->vd, flags); ++} ++ ++/** ++ * adm_terminate_all - terminate all transactions on a channel ++ * @achan: adm dma channel ++ * ++ * Dequeues and frees all transactions, aborts current transaction ++ * No callbacks are done ++ * ++ */ ++static int adm_terminate_all(struct dma_chan *chan) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct adm_device *adev = achan->adev; ++ unsigned long flags; ++ LIST_HEAD(head); ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ vchan_get_all_descriptors(&achan->vc, &head); ++ ++ /* send flush command to terminate current transaction */ ++ writel_relaxed(0x0, ++ adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee)); ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ ++ vchan_dma_desc_free_list(&achan->vc, &head); ++ ++ return 0; ++} ++ ++static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ unsigned long flag; ++ ++ spin_lock_irqsave(&achan->vc.lock, flag); ++ memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config)); ++ spin_unlock_irqrestore(&achan->vc.lock, flag); ++ ++ return 0; ++} ++ ++/** ++ * adm_start_dma - start next transaction ++ * @achan - ADM dma channel ++ */ ++static void adm_start_dma(struct adm_chan *achan) ++{ ++ struct virt_dma_desc *vd = vchan_next_desc(&achan->vc); ++ struct adm_device *adev = achan->adev; ++ struct adm_async_desc *async_desc; ++ ++ lockdep_assert_held(&achan->vc.lock); ++ ++ if (!vd) ++ return; ++ ++ list_del(&vd->node); ++ ++ /* write next command list out to the CMD FIFO */ ++ async_desc = container_of(vd, struct adm_async_desc, vd); ++ achan->curr_txd = async_desc; ++ ++ /* reset channel error */ ++ achan->error = 0; ++ ++ if (!achan->initialized) { ++ /* enable interrupts */ ++ writel(ADM_CH_CONF_SHADOW_EN | ++ ADM_CH_CONF_PERM_MPU_CONF | ++ ADM_CH_CONF_MPU_DISABLE | ++ ADM_CH_CONF_SEC_DOMAIN(adev->ee), ++ adev->regs + ADM_CH_CONF(achan->id)); ++ ++ writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN, ++ adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); ++ ++ achan->initialized = 1; ++ } ++ ++ /* set the crci block size if this transaction requires CRCI */ ++ if (async_desc->crci) { ++ writel(async_desc->mux | async_desc->blk_size, ++ adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee)); ++ } ++ ++ /* make sure IRQ enable doesn't get reordered */ ++ wmb(); ++ ++ /* write next command list out to the CMD FIFO */ ++ writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3, ++ adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee)); ++} ++ ++/** ++ * adm_dma_irq - irq handler for ADM controller ++ * @irq: IRQ of interrupt ++ * @data: callback data ++ * ++ * IRQ handler for the bam controller ++ */ ++static irqreturn_t adm_dma_irq(int irq, void *data) ++{ ++ struct adm_device *adev = data; ++ u32 srcs, i; ++ struct adm_async_desc *async_desc; ++ unsigned long flags; ++ ++ srcs = readl_relaxed(adev->regs + ++ ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee)); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) { ++ struct adm_chan *achan = &adev->channels[i]; ++ u32 status, result; ++ ++ if (srcs & BIT(i)) { ++ status = readl_relaxed(adev->regs + ++ ADM_CH_STATUS_SD(i, adev->ee)); ++ ++ /* if no result present, skip */ ++ if (!(status & ADM_CH_STATUS_VALID)) ++ continue; ++ ++ result = readl_relaxed(adev->regs + ++ ADM_CH_RSLT(i, adev->ee)); ++ ++ /* no valid results, skip */ ++ if (!(result & ADM_CH_RSLT_VALID)) ++ continue; ++ ++ /* flag error if transaction was flushed or failed */ ++ if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH)) ++ achan->error = 1; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ async_desc = achan->curr_txd; ++ ++ achan->curr_txd = NULL; ++ ++ if (async_desc) { ++ vchan_cookie_complete(&async_desc->vd); ++ ++ /* kick off next DMA */ ++ adm_start_dma(achan); ++ } ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/** ++ * adm_tx_status - returns status of transaction ++ * @chan: dma channel ++ * @cookie: transaction cookie ++ * @txstate: DMA transaction state ++ * ++ * Return status of dma transaction ++ */ ++static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie, ++ struct dma_tx_state *txstate) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct virt_dma_desc *vd; ++ enum dma_status ret; ++ unsigned long flags; ++ size_t residue = 0; ++ ++ ret = dma_cookie_status(chan, cookie, txstate); ++ if (ret == DMA_COMPLETE || !txstate) ++ return ret; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ ++ vd = vchan_find_desc(&achan->vc, cookie); ++ if (vd) ++ residue = container_of(vd, struct adm_async_desc, vd)->length; ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ ++ /* ++ * residue is either the full length if it is in the issued list, or 0 ++ * if it is in progress. We have no reliable way of determining ++ * anything inbetween ++ */ ++ dma_set_residue(txstate, residue); ++ ++ if (achan->error) ++ return DMA_ERROR; ++ ++ return ret; ++} ++ ++/** ++ * adm_issue_pending - starts pending transactions ++ * @chan: dma channel ++ * ++ * Issues all pending transactions and starts DMA ++ */ ++static void adm_issue_pending(struct dma_chan *chan) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ ++ if (vchan_issue_pending(&achan->vc) && !achan->curr_txd) ++ adm_start_dma(achan); ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++} ++ ++/** ++ * adm_dma_free_desc - free descriptor memory ++ * @vd: virtual descriptor ++ * ++ */ ++static void adm_dma_free_desc(struct virt_dma_desc *vd) ++{ ++ struct adm_async_desc *async_desc = container_of(vd, ++ struct adm_async_desc, vd); ++ ++ dma_free_writecombine(async_desc->adev->dev, async_desc->dma_len, ++ async_desc->cpl, async_desc->dma_addr); ++ kfree(async_desc); ++} ++ ++static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan, ++ u32 index) ++{ ++ achan->id = index; ++ achan->adev = adev; ++ ++ vchan_init(&achan->vc, &adev->common); ++ achan->vc.desc_free = adm_dma_free_desc; ++} ++ ++static int adm_dma_probe(struct platform_device *pdev) ++{ ++ struct adm_device *adev; ++ struct resource *iores; ++ int ret; ++ u32 i; ++ ++ adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); ++ if (!adev) ++ return -ENOMEM; ++ ++ adev->dev = &pdev->dev; ++ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ adev->regs = devm_ioremap_resource(&pdev->dev, iores); ++ if (IS_ERR(adev->regs)) ++ return PTR_ERR(adev->regs); ++ ++ adev->irq = platform_get_irq(pdev, 0); ++ if (adev->irq < 0) ++ return adev->irq; ++ ++ ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee); ++ if (ret) { ++ dev_err(adev->dev, "Execution environment unspecified\n"); ++ return ret; ++ } ++ ++ adev->core_clk = devm_clk_get(adev->dev, "core"); ++ if (IS_ERR(adev->core_clk)) ++ return PTR_ERR(adev->core_clk); ++ ++ ret = clk_prepare_enable(adev->core_clk); ++ if (ret) { ++ dev_err(adev->dev, "failed to prepare/enable core clock\n"); ++ return ret; ++ } ++ ++ adev->iface_clk = devm_clk_get(adev->dev, "iface"); ++ if (IS_ERR(adev->iface_clk)) { ++ ret = PTR_ERR(adev->iface_clk); ++ goto err_disable_core_clk; ++ } ++ ++ ret = clk_prepare_enable(adev->iface_clk); ++ if (ret) { ++ dev_err(adev->dev, "failed to prepare/enable iface clock\n"); ++ goto err_disable_core_clk; ++ } ++ ++ adev->clk_reset = devm_reset_control_get(&pdev->dev, "clk"); ++ if (IS_ERR(adev->clk_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 reset\n"); ++ ret = PTR_ERR(adev->clk_reset); ++ goto err_disable_clks; ++ } ++ ++ adev->c0_reset = devm_reset_control_get(&pdev->dev, "c0"); ++ if (IS_ERR(adev->c0_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C0 reset\n"); ++ ret = PTR_ERR(adev->c0_reset); ++ goto err_disable_clks; ++ } ++ ++ adev->c1_reset = devm_reset_control_get(&pdev->dev, "c1"); ++ if (IS_ERR(adev->c1_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C1 reset\n"); ++ ret = PTR_ERR(adev->c1_reset); ++ goto err_disable_clks; ++ } ++ ++ adev->c2_reset = devm_reset_control_get(&pdev->dev, "c2"); ++ if (IS_ERR(adev->c2_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C2 reset\n"); ++ ret = PTR_ERR(adev->c2_reset); ++ goto err_disable_clks; ++ } ++ ++ reset_control_assert(adev->clk_reset); ++ reset_control_assert(adev->c0_reset); ++ reset_control_assert(adev->c1_reset); ++ reset_control_assert(adev->c2_reset); ++ ++ reset_control_deassert(adev->clk_reset); ++ reset_control_deassert(adev->c0_reset); ++ reset_control_deassert(adev->c1_reset); ++ reset_control_deassert(adev->c2_reset); ++ ++ adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS, ++ sizeof(*adev->channels), GFP_KERNEL); ++ ++ if (!adev->channels) { ++ ret = -ENOMEM; ++ goto err_disable_clks; ++ } ++ ++ /* allocate and initialize channels */ ++ INIT_LIST_HEAD(&adev->common.channels); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) ++ adm_channel_init(adev, &adev->channels[i], i); ++ ++ /* reset CRCIs */ ++ for (i = 0; i < 16; i++) ++ writel(ADM_CRCI_CTL_RST, adev->regs + ++ ADM_CRCI_CTL(i, adev->ee)); ++ ++ /* configure client interfaces */ ++ writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0)); ++ writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1)); ++ writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2)); ++ writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf), ++ adev->regs + ADM_GP_CTL); ++ ++ ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq, ++ 0, "adm_dma", adev); ++ if (ret) ++ goto err_disable_clks; ++ ++ platform_set_drvdata(pdev, adev); ++ ++ adev->common.dev = adev->dev; ++ adev->common.dev->dma_parms = &adev->dma_parms; ++ ++ /* set capabilities */ ++ dma_cap_zero(adev->common.cap_mask); ++ dma_cap_set(DMA_SLAVE, adev->common.cap_mask); ++ dma_cap_set(DMA_PRIVATE, adev->common.cap_mask); ++ ++ /* initialize dmaengine apis */ ++ adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV); ++ adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; ++ adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ adev->common.device_free_chan_resources = adm_free_chan; ++ adev->common.device_prep_slave_sg = adm_prep_slave_sg; ++ adev->common.device_issue_pending = adm_issue_pending; ++ adev->common.device_tx_status = adm_tx_status; ++ adev->common.device_terminate_all = adm_terminate_all; ++ adev->common.device_config = adm_slave_config; ++ ++ ret = dma_async_device_register(&adev->common); ++ if (ret) { ++ dev_err(adev->dev, "failed to register dma async device\n"); ++ goto err_disable_clks; ++ } ++ ++ ret = of_dma_controller_register(pdev->dev.of_node, ++ of_dma_xlate_by_chan_id, ++ &adev->common); ++ if (ret) ++ goto err_unregister_dma; ++ ++ return 0; ++ ++err_unregister_dma: ++ dma_async_device_unregister(&adev->common); ++err_disable_clks: ++ clk_disable_unprepare(adev->iface_clk); ++err_disable_core_clk: ++ clk_disable_unprepare(adev->core_clk); ++ ++ return ret; ++} ++ ++static int adm_dma_remove(struct platform_device *pdev) ++{ ++ struct adm_device *adev = platform_get_drvdata(pdev); ++ struct adm_chan *achan; ++ u32 i; ++ ++ of_dma_controller_free(pdev->dev.of_node); ++ dma_async_device_unregister(&adev->common); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) { ++ achan = &adev->channels[i]; ++ ++ /* mask IRQs for this channel/EE pair */ ++ writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); ++ ++ adm_terminate_all(&adev->channels[i].vc.chan); ++ } ++ ++ devm_free_irq(adev->dev, adev->irq, adev); ++ ++ clk_disable_unprepare(adev->core_clk); ++ clk_disable_unprepare(adev->iface_clk); ++ ++ return 0; ++} ++ ++static const struct of_device_id adm_of_match[] = { ++ { .compatible = "qcom,adm", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, adm_of_match); ++ ++static struct platform_driver adm_dma_driver = { ++ .probe = adm_dma_probe, ++ .remove = adm_dma_remove, ++ .driver = { ++ .name = "adm-dma-engine", ++ .of_match_table = adm_of_match, ++ }, ++}; ++ ++module_platform_driver(adm_dma_driver); ++ ++MODULE_AUTHOR("Andy Gross "); ++MODULE_DESCRIPTION("QCOM ADM DMA engine driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/dma/Makefile ++++ b/drivers/dma/Makefile +@@ -54,3 +54,4 @@ obj-$(CONFIG_NBPFAXI_DMA) += nbpfaxi.o + obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o + obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o + obj-$(CONFIG_XGENE_DMA) += xgene-dma.o ++obj-$(CONFIG_QCOM_ADM) += qcom_adm.o diff --git a/target/linux/ipq806x/patches-4.1/157-ARM-DT-ipq8064-Add-ADM-device-node.patch b/target/linux/ipq806x/patches-4.1/157-ARM-DT-ipq8064-Add-ADM-device-node.patch new file mode 100644 index 0000000..159d912 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/157-ARM-DT-ipq8064-Add-ADM-device-node.patch @@ -0,0 +1,42 @@ +From 1fb18acab2d71e7e4efd9c10492edb1baf84dcc0 Mon Sep 17 00:00:00 2001 +From: Andy Gross +Date: Wed, 20 May 2015 15:41:07 +0530 +Subject: [PATCH] ARM: DT: ipq8064: Add ADM device node + +This patch adds support for the ADM DMA on the IPQ8064 SOC + +Signed-off-by: Andy Gross +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 4 ++++ + arch/arm/boot/dts/qcom-ipq8064.dtsi | 21 +++++++++++++++++++++ + 2 files changed, 25 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -600,6 +600,26 @@ + + status = "disabled"; + }; ++ ++ adm_dma: dma@18300000 { ++ compatible = "qcom,adm"; ++ reg = <0x18300000 0x100000>; ++ interrupts = <0 170 0>; ++ #dma-cells = <1>; ++ ++ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; ++ clock-names = "core", "iface"; ++ ++ resets = <&gcc ADM0_RESET>, ++ <&gcc ADM0_PBUS_RESET>, ++ <&gcc ADM0_C0_RESET>, ++ <&gcc ADM0_C1_RESET>, ++ <&gcc ADM0_C2_RESET>; ++ reset-names = "clk", "pbus", "c0", "c1", "c2"; ++ qcom,ee = <0>; ++ ++ status = "disabled"; ++ }; + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-4.1/161-mtd-nand-Create-a-BBT-flag-to-access-bad-block-markers-in-raw-mode.patch b/target/linux/ipq806x/patches-4.1/161-mtd-nand-Create-a-BBT-flag-to-access-bad-block-markers-in-raw-mode.patch new file mode 100644 index 0000000..088b8cb --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/161-mtd-nand-Create-a-BBT-flag-to-access-bad-block-markers-in-raw-mode.patch @@ -0,0 +1,84 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3, + 1/5] mtd: nand: Create a BBT flag to access bad block markers in raw + mode +From: Archit Taneja +X-Patchwork-Id: 6927081 +Message-Id: <1438578498-32254-2-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja +Date: Mon, 3 Aug 2015 10:38:14 +0530 + +Some controllers can access the factory bad block marker from OOB only +when they read it in raw mode. When ECC is enabled, these controllers +discard reading/writing bad block markers, preventing access to them +altogether. + +The bbt driver assumes MTD_OPS_PLACE_OOB when scanning for bad blocks. +This results in the nand driver's ecc->read_oob() op to be called, which +works with ECC enabled. + +Create a new BBT option flag that tells nand_bbt to force the mode to +MTD_OPS_RAW. This would result in the correct op being called for the +underlying nand controller driver. + +Reviewed-by: Andy Gross +Signed-off-by: Archit Taneja + +--- +drivers/mtd/nand/nand_base.c | 6 +++++- + drivers/mtd/nand/nand_bbt.c | 6 +++++- + include/linux/mtd/bbm.h | 7 +++++++ + 3 files changed, 17 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -395,7 +395,11 @@ static int nand_default_block_markbad(st + } else { + ops.len = ops.ooblen = 1; + } +- ops.mode = MTD_OPS_PLACE_OOB; ++ ++ if (unlikely(chip->bbt_options & NAND_BBT_ACCESS_BBM_RAW)) ++ ops.mode = MTD_OPS_RAW; ++ else ++ ops.mode = MTD_OPS_PLACE_OOB; + + /* Write to first/last page(s) if necessary */ + if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) +--- a/drivers/mtd/nand/nand_bbt.c ++++ b/drivers/mtd/nand/nand_bbt.c +@@ -423,7 +423,11 @@ static int scan_block_fast(struct mtd_in + ops.oobbuf = buf; + ops.ooboffs = 0; + ops.datbuf = NULL; +- ops.mode = MTD_OPS_PLACE_OOB; ++ ++ if (unlikely(bd->options & NAND_BBT_ACCESS_BBM_RAW)) ++ ops.mode = MTD_OPS_RAW; ++ else ++ ops.mode = MTD_OPS_PLACE_OOB; + + for (j = 0; j < numpages; j++) { + /* +--- a/include/linux/mtd/bbm.h ++++ b/include/linux/mtd/bbm.h +@@ -116,6 +116,13 @@ struct nand_bbt_descr { + #define NAND_BBT_NO_OOB_BBM 0x00080000 + + /* ++ * Force MTD_OPS_RAW mode when trying to access bad block markes from OOB. To ++ * be used by controllers which can access BBM only when ECC is disabled, i.e, ++ * when in RAW access mode ++ */ ++#define NAND_BBT_ACCESS_BBM_RAW 0x00100000 ++ ++/* + * Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr + * was allocated dynamicaly and must be freed in nand_release(). Has no meaning + * in nand_chip.bbt_options. diff --git a/target/linux/ipq806x/patches-4.1/162-mtd-nand-Qualcomm-NAND-controller-driver.patch b/target/linux/ipq806x/patches-4.1/162-mtd-nand-Qualcomm-NAND-controller-driver.patch new file mode 100644 index 0000000..4be7ecb --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/162-mtd-nand-Qualcomm-NAND-controller-driver.patch @@ -0,0 +1,2024 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,2/5] mtd: nand: Qualcomm NAND controller driver +From: Archit Taneja +X-Patchwork-Id: 6927101 +Message-Id: <1438578498-32254-3-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja +Date: Mon, 3 Aug 2015 10:38:15 +0530 + +The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx, +MDM9x15 series. + +It exists as a sub block inside the IPs EBI2 (External Bus Interface 2) +and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a +broader interface for external slow peripheral devices such as LCD and +NAND/NOR flash memory or SRAM like interfaces. + +We add support for the NAND controller found within EBI2. For the SoCs +of our interest, we only use the NAND controller within EBI2. Therefore, +it's safe for us to assume that the NAND controller is a standalone block +within the SoC. + +The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND +flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and +16 bit correction/step) and RS ECC(4 bit correction/step) that covers main +and spare data. The controller contains an internal 512 byte page buffer +to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA +for register read/write and data transfers. The controller performs page +reads and writes at a codeword/step level of 512 bytes. It can support up +to 2 external chips of different configurations. + +The driver prepares register read and write configuration descriptors for +each codeword, followed by data descriptors to read or write data from the +controller's internal buffer. It uses a single ADM DMA channel that we get +via dmaengine API. The controller requires 2 ADM CRCIs for command and +data flow control. These are passed via DT. + +The ecc layout used by the controller is syndrome like, but we can't use +the standard syndrome ecc ops because of several reasons. First, the amount +of data bytes covered by ecc isn't same in each step. Second, writing to +free oob space requires us writing to the entire step in which the oob +lies. This forces us to create our own ecc ops. + +One more difference is how the controller accesses the bad block marker. +The controller ignores reading the marker when ECC is enabled. ECC needs +to be explicity disabled to read or write to the bad block marker. For +this reason, we use the newly created flag NAND_BBT_ACCESS_BBM_RAW to +read the factory provided bad block markers. + +v3: +- Refactor dma functions for maximum reuse +- Use dma_slave_confing on stack +- optimize and clean upempty_page_fixup using memchr_inv +- ensure portability with dma register reads using le32_* funcs +- use NAND_USE_BOUNCE_BUFFER instead of doing it ourselves +- fix handling of return values of dmaengine funcs +- constify wherever possible +- Remove dependency on ADM DMA in Kconfig +- Misc fixes and clean ups + +v2: +- Use new BBT flag that allows us to read BBM in raw mode +- reduce memcpy-s in the driver +- some refactor and clean ups because of above changes + +Reviewed-by: Andy Gross +Signed-off-by: Archit Taneja + +--- +drivers/mtd/nand/Kconfig | 7 + + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/qcom_nandc.c | 1913 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 1921 insertions(+) + create mode 100644 drivers/mtd/nand/qcom_nandc.c + +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -530,4 +530,11 @@ config MTD_NAND_HISI504 + help + Enables support for NAND controller on Hisilicon SoC Hip04. + ++config MTD_NAND_QCOM ++ tristate "Support for NAND on QCOM SoCs" ++ depends on ARCH_QCOM ++ help ++ Enables support for NAND flash chips on SoCs containing the EBI2 NAND ++ controller. This controller is found on IPQ806x SoC. ++ + endif # MTD_NAND +--- /dev/null ++++ b/drivers/mtd/nand/qcom_nandc.c +@@ -0,0 +1,1918 @@ ++/* ++ * Copyright (c) 2015, The Linux Foundation. All rights reserved. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* NANDc reg offsets */ ++#define NAND_FLASH_CMD 0x00 ++#define NAND_ADDR0 0x04 ++#define NAND_ADDR1 0x08 ++#define NAND_FLASH_CHIP_SELECT 0x0c ++#define NAND_EXEC_CMD 0x10 ++#define NAND_FLASH_STATUS 0x14 ++#define NAND_BUFFER_STATUS 0x18 ++#define NAND_DEV0_CFG0 0x20 ++#define NAND_DEV0_CFG1 0x24 ++#define NAND_DEV0_ECC_CFG 0x28 ++#define NAND_DEV1_ECC_CFG 0x2c ++#define NAND_DEV1_CFG0 0x30 ++#define NAND_DEV1_CFG1 0x34 ++#define NAND_READ_ID 0x40 ++#define NAND_READ_STATUS 0x44 ++#define NAND_DEV_CMD0 0xa0 ++#define NAND_DEV_CMD1 0xa4 ++#define NAND_DEV_CMD2 0xa8 ++#define NAND_DEV_CMD_VLD 0xac ++#define SFLASHC_BURST_CFG 0xe0 ++#define NAND_ERASED_CW_DETECT_CFG 0xe8 ++#define NAND_ERASED_CW_DETECT_STATUS 0xec ++#define NAND_EBI2_ECC_BUF_CFG 0xf0 ++#define FLASH_BUF_ACC 0x100 ++ ++#define NAND_CTRL 0xf00 ++#define NAND_VERSION 0xf08 ++#define NAND_READ_LOCATION_0 0xf20 ++#define NAND_READ_LOCATION_1 0xf24 ++ ++/* dummy register offsets, used by write_reg_dma */ ++#define NAND_DEV_CMD1_RESTORE 0xdead ++#define NAND_DEV_CMD_VLD_RESTORE 0xbeef ++ ++/* NAND_FLASH_CMD bits */ ++#define PAGE_ACC BIT(4) ++#define LAST_PAGE BIT(5) ++ ++/* NAND_FLASH_CHIP_SELECT bits */ ++#define NAND_DEV_SEL 0 ++#define DM_EN BIT(2) ++ ++/* NAND_FLASH_STATUS bits */ ++#define FS_OP_ERR BIT(4) ++#define FS_READY_BSY_N BIT(5) ++#define FS_MPU_ERR BIT(8) ++#define FS_DEVICE_STS_ERR BIT(16) ++#define FS_DEVICE_WP BIT(23) ++ ++/* NAND_BUFFER_STATUS bits */ ++#define BS_UNCORRECTABLE_BIT BIT(8) ++#define BS_CORRECTABLE_ERR_MSK 0x1f ++ ++/* NAND_DEVn_CFG0 bits */ ++#define DISABLE_STATUS_AFTER_WRITE 4 ++#define CW_PER_PAGE 6 ++#define UD_SIZE_BYTES 9 ++#define ECC_PARITY_SIZE_BYTES_RS 19 ++#define SPARE_SIZE_BYTES 23 ++#define NUM_ADDR_CYCLES 27 ++#define STATUS_BFR_READ 30 ++#define SET_RD_MODE_AFTER_STATUS 31 ++ ++/* NAND_DEVn_CFG0 bits */ ++#define DEV0_CFG1_ECC_DISABLE 0 ++#define WIDE_FLASH 1 ++#define NAND_RECOVERY_CYCLES 2 ++#define CS_ACTIVE_BSY 5 ++#define BAD_BLOCK_BYTE_NUM 6 ++#define BAD_BLOCK_IN_SPARE_AREA 16 ++#define WR_RD_BSY_GAP 17 ++#define ENABLE_BCH_ECC 27 ++ ++/* NAND_DEV0_ECC_CFG bits */ ++#define ECC_CFG_ECC_DISABLE 0 ++#define ECC_SW_RESET 1 ++#define ECC_MODE 4 ++#define ECC_PARITY_SIZE_BYTES_BCH 8 ++#define ECC_NUM_DATA_BYTES 16 ++#define ECC_FORCE_CLK_OPEN 30 ++ ++/* NAND_DEV_CMD1 bits */ ++#define READ_ADDR 0 ++ ++/* NAND_DEV_CMD_VLD bits */ ++#define READ_START_VLD 0 ++ ++/* NAND_EBI2_ECC_BUF_CFG bits */ ++#define NUM_STEPS 0 ++ ++/* NAND_ERASED_CW_DETECT_CFG bits */ ++#define ERASED_CW_ECC_MASK 1 ++#define AUTO_DETECT_RES 0 ++#define MASK_ECC (1 << ERASED_CW_ECC_MASK) ++#define RESET_ERASED_DET (1 << AUTO_DETECT_RES) ++#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) ++#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) ++#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) ++ ++/* NAND_ERASED_CW_DETECT_STATUS bits */ ++#define PAGE_ALL_ERASED BIT(7) ++#define CODEWORD_ALL_ERASED BIT(6) ++#define PAGE_ERASED BIT(5) ++#define CODEWORD_ERASED BIT(4) ++#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED) ++#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED) ++ ++/* Version Mask */ ++#define NAND_VERSION_MAJOR_MASK 0xf0000000 ++#define NAND_VERSION_MAJOR_SHIFT 28 ++#define NAND_VERSION_MINOR_MASK 0x0fff0000 ++#define NAND_VERSION_MINOR_SHIFT 16 ++ ++/* NAND OP_CMDs */ ++#define PAGE_READ 0x2 ++#define PAGE_READ_WITH_ECC 0x3 ++#define PAGE_READ_WITH_ECC_SPARE 0x4 ++#define PROGRAM_PAGE 0x6 ++#define PAGE_PROGRAM_WITH_ECC 0x7 ++#define PROGRAM_PAGE_SPARE 0x9 ++#define BLOCK_ERASE 0xa ++#define FETCH_ID 0xb ++#define RESET_DEVICE 0xd ++ ++/* ++ * the NAND controller performs reads/writes with ECC in 516 byte chunks. ++ * the driver calls the chunks 'step' or 'codeword' interchangeably ++ */ ++#define NANDC_STEP_SIZE 512 ++ ++/* ++ * the largest page size we support is 8K, this will have 16 steps/codewords ++ * of 512 bytes each ++ */ ++#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE) ++ ++/* we read at most 3 registers per codeword scan */ ++#define MAX_REG_RD (3 * MAX_NUM_STEPS) ++ ++/* ECC modes */ ++#define ECC_NONE BIT(0) ++#define ECC_RS_4BIT BIT(1) ++#define ECC_BCH_4BIT BIT(2) ++#define ECC_BCH_8BIT BIT(3) ++ ++struct desc_info { ++ struct list_head list; ++ ++ enum dma_transfer_direction dir; ++ struct scatterlist sgl; ++ struct dma_async_tx_descriptor *dma_desc; ++}; ++ ++/* ++ * holds the current register values that we want to write. acts as a contiguous ++ * chunk of memory which we use to write the controller registers through DMA. ++ */ ++struct nandc_regs { ++ u32 cmd; ++ u32 addr0; ++ u32 addr1; ++ u32 chip_sel; ++ u32 exec; ++ ++ u32 cfg0; ++ u32 cfg1; ++ u32 ecc_bch_cfg; ++ ++ u32 clrflashstatus; ++ u32 clrreadstatus; ++ ++ u32 cmd1; ++ u32 vld; ++ ++ u32 orig_cmd1; ++ u32 orig_vld; ++ ++ u32 ecc_buf_cfg; ++}; ++ ++/* ++ * @cmd_crci: ADM DMA CRCI for command flow control ++ * @data_crci: ADM DMA CRCI for data flow control ++ * @list: DMA descriptor list (list of desc_infos) ++ * @dma_done: completion param to denote end of last ++ * descriptor in the list ++ * @data_buffer: our local DMA buffer for page read/writes, ++ * used when we can't use the buffer provided ++ * by upper layers directly ++ * @buf_size/count/start: markers for chip->read_buf/write_buf functions ++ * @reg_read_buf: buffer for reading register data via DMA ++ * @reg_read_pos: marker for data read in reg_read_buf ++ * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for ++ * ecc/non-ecc mode for the current nand flash ++ * device ++ * @regs: a contiguous chunk of memory for DMA register ++ * writes ++ * @ecc_strength: 4 bit or 8 bit ecc, received via DT ++ * @bus_width: 8 bit or 16 bit NAND bus width, received via DT ++ * @ecc_modes: supported ECC modes by the current controller, ++ * initialized via DT match data ++ * @cw_size: the number of bytes in a single step/codeword ++ * of a page, consisting of all data, ecc, spare ++ * and reserved bytes ++ * @cw_data: the number of bytes within a codeword protected ++ * by ECC ++ * @bch_enabled: flag to tell whether BCH or RS ECC mode is used ++ * @status: value to be returned if NAND_CMD_STATUS command ++ * is executed ++ */ ++struct qcom_nandc_data { ++ struct platform_device *pdev; ++ struct device *dev; ++ ++ void __iomem *base; ++ struct resource *res; ++ ++ struct clk *core_clk; ++ struct clk *aon_clk; ++ ++ /* DMA stuff */ ++ struct dma_chan *chan; ++ struct dma_slave_config slave_conf; ++ unsigned int cmd_crci; ++ unsigned int data_crci; ++ struct list_head list; ++ struct completion dma_done; ++ ++ /* MTD stuff */ ++ struct nand_chip chip; ++ struct mtd_info mtd; ++ ++ /* local data buffer and markers */ ++ u8 *data_buffer; ++ int buf_size; ++ int buf_count; ++ int buf_start; ++ ++ /* local buffer to read back registers */ ++ u32 *reg_read_buf; ++ int reg_read_pos; ++ ++ /* required configs */ ++ u32 cfg0, cfg1; ++ u32 cfg0_raw, cfg1_raw; ++ u32 ecc_buf_cfg; ++ u32 ecc_bch_cfg; ++ u32 clrflashstatus; ++ u32 clrreadstatus; ++ u32 sflashc_burst_cfg; ++ u32 cmd1, vld; ++ ++ /* register state */ ++ struct nandc_regs *regs; ++ ++ /* things we get from DT */ ++ int ecc_strength; ++ int bus_width; ++ ++ u32 ecc_modes; ++ ++ /* misc params */ ++ int cw_size; ++ int cw_data; ++ bool use_ecc; ++ bool bch_enabled; ++ u8 status; ++ int last_command; ++}; ++ ++static inline u32 nandc_read(struct qcom_nandc_data *this, int offset) ++{ ++ return ioread32(this->base + offset); ++} ++ ++static inline void nandc_write(struct qcom_nandc_data *this, int offset, ++ u32 val) ++{ ++ iowrite32(val, this->base + offset); ++} ++ ++/* helper to configure address register values */ ++static void set_address(struct qcom_nandc_data *this, u16 column, int page) ++{ ++ struct nand_chip *chip = &this->chip; ++ struct nandc_regs *regs = this->regs; ++ ++ if (chip->options & NAND_BUSWIDTH_16) ++ column >>= 1; ++ ++ regs->addr0 = page << 16 | column; ++ regs->addr1 = page >> 16 & 0xff; ++} ++ ++/* ++ * update_rw_regs: set up read/write register values, these will be ++ * written to the NAND controller registers via DMA ++ * ++ * @num_cw: number of steps for the read/write operation ++ * @read: read or write operation ++ */ ++static void update_rw_regs(struct qcom_nandc_data *this, int num_cw, bool read) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ if (read) { ++ if (this->use_ecc) ++ regs->cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE; ++ else ++ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE; ++ } else { ++ regs->cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE; ++ } ++ ++ if (this->use_ecc) { ++ regs->cfg0 = (this->cfg0 & ~(7U << CW_PER_PAGE)) | ++ (num_cw - 1) << CW_PER_PAGE; ++ ++ regs->cfg1 = this->cfg1; ++ regs->ecc_bch_cfg = this->ecc_bch_cfg; ++ } else { ++ regs->cfg0 = (this->cfg0_raw & ~(7U << CW_PER_PAGE)) | ++ (num_cw - 1) << CW_PER_PAGE; ++ ++ regs->cfg1 = this->cfg1_raw; ++ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE; ++ } ++ ++ regs->ecc_buf_cfg = this->ecc_buf_cfg; ++ regs->clrflashstatus = this->clrflashstatus; ++ regs->clrreadstatus = this->clrreadstatus; ++ regs->exec = 1; ++} ++ ++static int prep_dma_desc(struct qcom_nandc_data *this, bool read, int reg_off, ++ const void *vaddr, int size, bool flow_control) ++{ ++ struct desc_info *desc; ++ struct dma_async_tx_descriptor *dma_desc; ++ struct scatterlist *sgl; ++ struct dma_slave_config slave_conf; ++ int r; ++ ++ desc = kzalloc(sizeof(*desc), GFP_KERNEL); ++ if (!desc) ++ return -ENOMEM; ++ ++ list_add_tail(&desc->list, &this->list); ++ ++ sgl = &desc->sgl; ++ ++ sg_init_one(sgl, vaddr, size); ++ ++ desc->dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; ++ ++ r = dma_map_sg(this->dev, sgl, 1, desc->dir); ++ if (r == 0) { ++ r = -ENOMEM; ++ goto err; ++ } ++ ++ memset(&slave_conf, 0x00, sizeof(slave_conf)); ++ ++ slave_conf.device_fc = flow_control; ++ if (read) { ++ slave_conf.src_maxburst = 16; ++ slave_conf.src_addr = this->res->start + reg_off; ++ slave_conf.slave_id = this->data_crci; ++ } else { ++ slave_conf.dst_maxburst = 16; ++ slave_conf.dst_addr = this->res->start + reg_off; ++ slave_conf.slave_id = this->cmd_crci; ++ } ++ ++ r = dmaengine_slave_config(this->chan, &slave_conf); ++ if (r) { ++ dev_err(this->dev, "failed to configure dma channel\n"); ++ goto err; ++ } ++ ++ dma_desc = dmaengine_prep_slave_sg(this->chan, sgl, 1, desc->dir, 0); ++ if (!dma_desc) { ++ dev_err(this->dev, "failed to prepare desc\n"); ++ r = -EINVAL; ++ goto err; ++ } ++ ++ desc->dma_desc = dma_desc; ++ ++ return 0; ++err: ++ kfree(desc); ++ ++ return r; ++} ++ ++/* ++ * read_reg_dma: prepares a descriptor to read a given number of ++ * contiguous registers to the reg_read_buf pointer ++ * ++ * @first: offset of the first register in the contiguous block ++ * @num_regs: number of registers to read ++ */ ++static int read_reg_dma(struct qcom_nandc_data *this, int first, int num_regs) ++{ ++ bool flow_control = false; ++ void *vaddr; ++ int size; ++ ++ if (first == NAND_READ_ID || first == NAND_FLASH_STATUS) ++ flow_control = true; ++ ++ size = num_regs * sizeof(u32); ++ vaddr = this->reg_read_buf + this->reg_read_pos; ++ this->reg_read_pos += num_regs; ++ ++ return prep_dma_desc(this, true, first, vaddr, size, flow_control); ++} ++ ++/* ++ * write_reg_dma: prepares a descriptor to write a given number of ++ * contiguous registers ++ * ++ * @first: offset of the first register in the contiguous block ++ * @num_regs: number of registers to write ++ */ ++static int write_reg_dma(struct qcom_nandc_data *this, int first, int num_regs) ++{ ++ bool flow_control = false; ++ struct nandc_regs *regs = this->regs; ++ void *vaddr; ++ int size; ++ ++ switch (first) { ++ case NAND_FLASH_CMD: ++ vaddr = ®s->cmd; ++ flow_control = true; ++ break; ++ case NAND_EXEC_CMD: ++ vaddr = ®s->exec; ++ break; ++ case NAND_FLASH_STATUS: ++ vaddr = ®s->clrflashstatus; ++ break; ++ case NAND_DEV0_CFG0: ++ vaddr = ®s->cfg0; ++ break; ++ case NAND_READ_STATUS: ++ vaddr = ®s->clrreadstatus; ++ break; ++ case NAND_DEV_CMD1: ++ vaddr = ®s->cmd1; ++ break; ++ case NAND_DEV_CMD1_RESTORE: ++ first = NAND_DEV_CMD1; ++ vaddr = ®s->orig_cmd1; ++ break; ++ case NAND_DEV_CMD_VLD: ++ vaddr = ®s->vld; ++ break; ++ case NAND_DEV_CMD_VLD_RESTORE: ++ first = NAND_DEV_CMD_VLD; ++ vaddr = ®s->orig_vld; ++ break; ++ case NAND_EBI2_ECC_BUF_CFG: ++ vaddr = ®s->ecc_buf_cfg; ++ break; ++ default: ++ dev_err(this->dev, "invalid starting register\n"); ++ return -EINVAL; ++ } ++ ++ size = num_regs * sizeof(u32); ++ ++ return prep_dma_desc(this, false, first, vaddr, size, flow_control); ++} ++ ++/* ++ * read_data_dma: prepares a DMA descriptor to transfer data from the ++ * controller's internal buffer to the buffer 'vaddr' ++ * ++ * @reg_off: offset within the controller's data buffer ++ * @vaddr: virtual address of the buffer we want to write to ++ * @size: DMA transaction size in bytes ++ */ ++static int read_data_dma(struct qcom_nandc_data *this, int reg_off, ++ const u8 *vaddr, int size) ++{ ++ return prep_dma_desc(this, true, reg_off, vaddr, size, false); ++} ++ ++/* ++ * write_data_dma: prepares a DMA descriptor to transfer data from ++ * 'vaddr' to the controller's internal buffer ++ * ++ * @reg_off: offset within the controller's data buffer ++ * @vaddr: virtual address of the buffer we want to read from ++ * @size: DMA transaction size in bytes ++ */ ++static int write_data_dma(struct qcom_nandc_data *this, int reg_off, ++ const u8 *vaddr, int size) ++{ ++ return prep_dma_desc(this, false, reg_off, vaddr, size, false); ++} ++ ++/* ++ * helper to prepare dma descriptors to configure registers needed for reading a ++ * codeword/step in a page ++ */ ++static void config_cw_read(struct qcom_nandc_data *this) ++{ ++ write_reg_dma(this, NAND_FLASH_CMD, 3); ++ write_reg_dma(this, NAND_DEV0_CFG0, 3); ++ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1); ++ ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_FLASH_STATUS, 2); ++ read_reg_dma(this, NAND_ERASED_CW_DETECT_STATUS, 1); ++} ++ ++/* ++ * helpers to prepare dma descriptors used to configure registers needed for ++ * writing a codeword/step in a page ++ */ ++static void config_cw_write_pre(struct qcom_nandc_data *this) ++{ ++ write_reg_dma(this, NAND_FLASH_CMD, 3); ++ write_reg_dma(this, NAND_DEV0_CFG0, 3); ++ write_reg_dma(this, NAND_EBI2_ECC_BUF_CFG, 1); ++} ++ ++static void config_cw_write_post(struct qcom_nandc_data *this) ++{ ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_FLASH_STATUS, 1); ++ ++ write_reg_dma(this, NAND_FLASH_STATUS, 1); ++ write_reg_dma(this, NAND_READ_STATUS, 1); ++} ++ ++/* ++ * the following functions are used within chip->cmdfunc() to perform different ++ * NAND_CMD_* commands ++ */ ++ ++/* sets up descriptors for NAND_CMD_PARAM */ ++static int nandc_param(struct qcom_nandc_data *this) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ /* ++ * NAND_CMD_PARAM is called before we know much about the FLASH chip ++ * in use. we configure the controller to perform a raw read of 512 ++ * bytes to read onfi params ++ */ ++ regs->cmd = PAGE_READ | PAGE_ACC | LAST_PAGE; ++ regs->addr0 = 0; ++ regs->addr1 = 0; ++ regs->cfg0 = 0 << CW_PER_PAGE ++ | 512 << UD_SIZE_BYTES ++ | 5 << NUM_ADDR_CYCLES ++ | 0 << SPARE_SIZE_BYTES; ++ ++ regs->cfg1 = 7 << NAND_RECOVERY_CYCLES ++ | 0 << CS_ACTIVE_BSY ++ | 17 << BAD_BLOCK_BYTE_NUM ++ | 1 << BAD_BLOCK_IN_SPARE_AREA ++ | 2 << WR_RD_BSY_GAP ++ | 0 << WIDE_FLASH ++ | 1 << DEV0_CFG1_ECC_DISABLE; ++ ++ regs->ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE; ++ ++ /* configure CMD1 and VLD for ONFI param probing */ ++ regs->vld = (this->vld & ~(1 << READ_START_VLD)) ++ | 0 << READ_START_VLD; ++ ++ regs->cmd1 = (this->cmd1 & ~(0xFF << READ_ADDR)) ++ | NAND_CMD_PARAM << READ_ADDR; ++ ++ regs->exec = 1; ++ ++ regs->orig_cmd1 = this->cmd1; ++ regs->orig_vld = this->vld; ++ ++ write_reg_dma(this, NAND_DEV_CMD_VLD, 1); ++ write_reg_dma(this, NAND_DEV_CMD1, 1); ++ ++ this->buf_count = 512; ++ memset(this->data_buffer, 0xff, this->buf_count); ++ ++ config_cw_read(this); ++ ++ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->buf_count); ++ ++ /* restore CMD1 and VLD regs */ ++ write_reg_dma(this, NAND_DEV_CMD1_RESTORE, 1); ++ write_reg_dma(this, NAND_DEV_CMD_VLD_RESTORE, 1); ++ ++ return 0; ++} ++ ++/* sets up descriptors for NAND_CMD_ERASE1 */ ++static int erase_block(struct qcom_nandc_data *this, int page_addr) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ regs->cmd = BLOCK_ERASE | PAGE_ACC | LAST_PAGE; ++ regs->addr0 = page_addr; ++ regs->addr1 = 0; ++ regs->cfg0 = this->cfg0_raw & ~(7 << CW_PER_PAGE); ++ regs->cfg1 = this->cfg1_raw; ++ regs->exec = 1; ++ regs->clrflashstatus = this->clrflashstatus; ++ regs->clrreadstatus = this->clrreadstatus; ++ ++ write_reg_dma(this, NAND_FLASH_CMD, 3); ++ write_reg_dma(this, NAND_DEV0_CFG0, 2); ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_FLASH_STATUS, 1); ++ ++ write_reg_dma(this, NAND_FLASH_STATUS, 1); ++ write_reg_dma(this, NAND_READ_STATUS, 1); ++ ++ return 0; ++} ++ ++/* sets up descriptors for NAND_CMD_READID */ ++static int read_id(struct qcom_nandc_data *this, int column) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ if (column == -1) ++ return 0; ++ ++ regs->cmd = FETCH_ID; ++ regs->addr0 = column; ++ regs->addr1 = 0; ++ regs->chip_sel = DM_EN; ++ regs->exec = 1; ++ ++ write_reg_dma(this, NAND_FLASH_CMD, 4); ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_READ_ID, 1); ++ ++ return 0; ++} ++ ++/* sets up descriptors for NAND_CMD_RESET */ ++static int reset(struct qcom_nandc_data *this) ++{ ++ struct nandc_regs *regs = this->regs; ++ ++ regs->cmd = RESET_DEVICE; ++ regs->exec = 1; ++ ++ write_reg_dma(this, NAND_FLASH_CMD, 1); ++ write_reg_dma(this, NAND_EXEC_CMD, 1); ++ ++ read_reg_dma(this, NAND_FLASH_STATUS, 1); ++ ++ return 0; ++} ++ ++/* helpers to submit/free our list of dma descriptors */ ++static void dma_callback(void *param) ++{ ++ struct qcom_nandc_data *this = param; ++ struct completion *c = &this->dma_done; ++ ++ complete(c); ++} ++ ++static int submit_descs(struct qcom_nandc_data *this) ++{ ++ struct completion *c = &this->dma_done; ++ struct desc_info *desc; ++ int r; ++ ++ init_completion(c); ++ ++ list_for_each_entry(desc, &this->list, list) { ++ /* ++ * we add a callback to the last descriptor in our list to ++ * notify completion of command ++ */ ++ if (list_is_last(&desc->list, &this->list)) { ++ desc->dma_desc->callback = dma_callback; ++ desc->dma_desc->callback_param = this; ++ } ++ ++ dmaengine_submit(desc->dma_desc); ++ } ++ ++ dma_async_issue_pending(this->chan); ++ ++ r = wait_for_completion_timeout(c, msecs_to_jiffies(500)); ++ if (!r) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++ ++static void free_descs(struct qcom_nandc_data *this) ++{ ++ struct desc_info *desc, *n; ++ ++ list_for_each_entry_safe(desc, n, &this->list, list) { ++ list_del(&desc->list); ++ dma_unmap_sg(this->dev, &desc->sgl, 1, desc->dir); ++ kfree(desc); ++ } ++} ++ ++/* reset the register read buffer for next NAND operation */ ++static void clear_read_regs(struct qcom_nandc_data *this) ++{ ++ this->reg_read_pos = 0; ++ memset(this->reg_read_buf, 0, MAX_REG_RD * sizeof(*this->reg_read_buf)); ++} ++ ++static void pre_command(struct qcom_nandc_data *this, int command) ++{ ++ this->buf_count = 0; ++ this->buf_start = 0; ++ this->use_ecc = false; ++ this->last_command = command; ++ ++ clear_read_regs(this); ++} ++ ++/* ++ * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our ++ * privately maintained status byte, this status byte can be read after ++ * NAND_CMD_STATUS is called ++ */ ++static void parse_erase_write_errors(struct qcom_nandc_data *this, int command) ++{ ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int num_cw; ++ int i; ++ ++ num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1; ++ ++ for (i = 0; i < num_cw; i++) { ++ __le32 flash_status = le32_to_cpu(this->reg_read_buf[i]); ++ ++ if (flash_status & FS_MPU_ERR) ++ this->status &= ~NAND_STATUS_WP; ++ ++ if (flash_status & FS_OP_ERR || (i == (num_cw - 1) && ++ (flash_status & FS_DEVICE_STS_ERR))) ++ this->status |= NAND_STATUS_FAIL; ++ } ++} ++ ++static void post_command(struct qcom_nandc_data *this, int command) ++{ ++ switch (command) { ++ case NAND_CMD_READID: ++ memcpy(this->data_buffer, this->reg_read_buf, this->buf_count); ++ break; ++ case NAND_CMD_PAGEPROG: ++ case NAND_CMD_ERASE1: ++ parse_erase_write_errors(this, command); ++ break; ++ default: ++ break; ++ } ++} ++ ++/* ++ * Implements chip->cmdfunc. It's only used for a limited set of commands. ++ * The rest of the commands wouldn't be called by upper layers. For example, ++ * NAND_CMD_READOOB would never be called because we have our own versions ++ * of read_oob ops for nand_ecc_ctrl. ++ */ ++static void qcom_nandc_command(struct mtd_info *mtd, unsigned int command, ++ int column, int page_addr) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ struct qcom_nandc_data *this = chip->priv; ++ bool wait = false; ++ int r = 0; ++ ++ pre_command(this, command); ++ ++ switch (command) { ++ case NAND_CMD_RESET: ++ r = reset(this); ++ wait = true; ++ break; ++ ++ case NAND_CMD_READID: ++ this->buf_count = 4; ++ r = read_id(this, column); ++ wait = true; ++ break; ++ ++ case NAND_CMD_PARAM: ++ r = nandc_param(this); ++ wait = true; ++ break; ++ ++ case NAND_CMD_ERASE1: ++ r = erase_block(this, page_addr); ++ wait = true; ++ break; ++ ++ case NAND_CMD_READ0: ++ /* we read the entire page for now */ ++ WARN_ON(column != 0); ++ ++ this->use_ecc = true; ++ set_address(this, 0, page_addr); ++ update_rw_regs(this, ecc->steps, true); ++ break; ++ ++ case NAND_CMD_SEQIN: ++ WARN_ON(column != 0); ++ set_address(this, 0, page_addr); ++ break; ++ ++ case NAND_CMD_PAGEPROG: ++ case NAND_CMD_STATUS: ++ case NAND_CMD_NONE: ++ default: ++ break; ++ } ++ ++ if (r) { ++ dev_err(this->dev, "failure executing command %d\n", ++ command); ++ free_descs(this); ++ return; ++ } ++ ++ if (wait) { ++ r = submit_descs(this); ++ if (r) ++ dev_err(this->dev, ++ "failure submitting descs for command %d\n", ++ command); ++ } ++ ++ free_descs(this); ++ ++ post_command(this, command); ++} ++ ++/* ++ * when using RS ECC, the NAND controller flags an error when reading an ++ * erased page. however, there are special characters at certain offsets when ++ * we read the erased page. we check here if the page is really empty. if so, ++ * we replace the magic characters with 0xffs ++ */ ++static bool empty_page_fixup(struct qcom_nandc_data *this, u8 *data_buf) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int cwperpage = ecc->steps; ++ u8 orig1[MAX_NUM_STEPS], orig2[MAX_NUM_STEPS]; ++ int i, j; ++ ++ /* if BCH is enabled, HW will take care of detecting erased pages */ ++ if (this->bch_enabled || !this->use_ecc) ++ return false; ++ ++ for (i = 0; i < cwperpage; i++) { ++ u8 *empty1, *empty2; ++ __le32 flash_status = le32_to_cpu(this->reg_read_buf[3 * i]); ++ ++ /* ++ * an erased page flags an error in NAND_FLASH_STATUS, check if ++ * the page is erased by looking for 0x54s at offsets 3 and 175 ++ * from the beginning of each codeword ++ */ ++ if (!(flash_status & FS_OP_ERR)) ++ break; ++ ++ empty1 = &data_buf[3 + i * this->cw_data]; ++ empty2 = &data_buf[175 + i * this->cw_data]; ++ ++ /* ++ * if the error wasn't because of an erased page, bail out and ++ * and let someone else do the error checking ++ */ ++ if ((*empty1 == 0x54 && *empty2 == 0xff) || ++ (*empty1 == 0xff && *empty2 == 0x54)) { ++ orig1[i] = *empty1; ++ orig2[i] = *empty2; ++ ++ *empty1 = 0xff; ++ *empty2 = 0xff; ++ } else { ++ break; ++ } ++ } ++ ++ if (i < cwperpage || memchr_inv(data_buf, 0xff, mtd->writesize)) ++ goto not_empty; ++ ++ /* ++ * tell the caller that the page was empty and is fixed up, so that ++ * parse_read_errors() doesn't think it's an error ++ */ ++ return true; ++ ++not_empty: ++ /* restore original values if not empty*/ ++ for (j = 0; j < i; j++) { ++ data_buf[3 + j * this->cw_data] = orig1[j]; ++ data_buf[175 + j * this->cw_data] = orig2[j]; ++ } ++ ++ return false; ++} ++ ++struct read_stats { ++ __le32 flash; ++ __le32 buffer; ++ __le32 erased_cw; ++}; ++ ++/* ++ * reads back status registers set by the controller to notify page read ++ * errors. this is equivalent to what 'ecc->correct()' would do. ++ */ ++static int parse_read_errors(struct qcom_nandc_data *this, bool erased_page) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int cwperpage = ecc->steps; ++ unsigned int max_bitflips = 0; ++ int i; ++ ++ for (i = 0; i < cwperpage; i++) { ++ int stat; ++ struct read_stats *buf; ++ ++ buf = (struct read_stats *) (this->reg_read_buf + 3 * i); ++ ++ buf->flash = le32_to_cpu(buf->flash); ++ buf->buffer = le32_to_cpu(buf->buffer); ++ buf->erased_cw = le32_to_cpu(buf->erased_cw); ++ ++ if (buf->flash & (FS_OP_ERR | FS_MPU_ERR)) { ++ ++ /* ignore erased codeword errors */ ++ if (this->bch_enabled) { ++ if ((buf->erased_cw & ERASED_CW) == ERASED_CW) ++ continue; ++ } else if (erased_page) { ++ continue; ++ } ++ ++ if (buf->buffer & BS_UNCORRECTABLE_BIT) { ++ mtd->ecc_stats.failed++; ++ continue; ++ } ++ } ++ ++ stat = buf->buffer & BS_CORRECTABLE_ERR_MSK; ++ mtd->ecc_stats.corrected += stat; ++ ++ max_bitflips = max_t(unsigned int, max_bitflips, stat); ++ } ++ ++ return max_bitflips; ++} ++ ++/* ++ * helper to perform the actual page read operation, used by ecc->read_page() ++ * and ecc->read_oob() ++ */ ++static int read_page_low(struct qcom_nandc_data *this, u8 *data_buf, ++ u8 *oob_buf) ++{ ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int i, r; ++ ++ /* queue cmd descs for each codeword */ ++ for (i = 0; i < ecc->steps; i++) { ++ int data_size, oob_size; ++ ++ if (i == (ecc->steps - 1)) { ++ data_size = ecc->size - ((ecc->steps - 1) << 2); ++ oob_size = (ecc->steps << 2) + ecc->bytes; ++ } else { ++ data_size = this->cw_data; ++ oob_size = ecc->bytes; ++ } ++ ++ config_cw_read(this); ++ ++ if (data_buf) ++ read_data_dma(this, FLASH_BUF_ACC, data_buf, data_size); ++ ++ if (oob_buf) ++ read_data_dma(this, FLASH_BUF_ACC + data_size, oob_buf, ++ oob_size); ++ ++ if (data_buf) ++ data_buf += data_size; ++ if (oob_buf) ++ oob_buf += oob_size; ++ } ++ ++ r = submit_descs(this); ++ if (r) ++ dev_err(this->dev, "failure to read page/oob\n"); ++ ++ free_descs(this); ++ ++ return r; ++} ++ ++/* ++ * a helper that copies the last step/codeword of a page (containing free oob) ++ * into our local buffer ++ */ ++static int copy_last_cw(struct qcom_nandc_data *this, bool use_ecc, int page) ++{ ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int size; ++ int r; ++ ++ clear_read_regs(this); ++ ++ size = use_ecc ? this->cw_data : this->cw_size; ++ ++ /* prepare a clean read buffer */ ++ memset(this->data_buffer, 0xff, size); ++ ++ this->use_ecc = use_ecc; ++ set_address(this, this->cw_size * (ecc->steps - 1), page); ++ update_rw_regs(this, 1, true); ++ ++ config_cw_read(this); ++ ++ read_data_dma(this, FLASH_BUF_ACC, this->data_buffer, size); ++ ++ r = submit_descs(this); ++ if (r) ++ dev_err(this->dev, "failed to copy last codeword\n"); ++ ++ free_descs(this); ++ ++ return r; ++} ++ ++/* implements ecc->read_page() */ ++static int qcom_nandc_read_page(struct mtd_info *mtd, struct nand_chip *chip, ++ uint8_t *buf, int oob_required, int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ u8 *data_buf, *oob_buf = NULL; ++ bool erased_page; ++ int r; ++ ++ data_buf = buf; ++ oob_buf = oob_required ? chip->oob_poi : NULL; ++ ++ r = read_page_low(this, data_buf, oob_buf); ++ if (r) { ++ dev_err(this->dev, "failure to read page\n"); ++ return r; ++ } ++ ++ erased_page = empty_page_fixup(this, data_buf); ++ ++ return parse_read_errors(this, erased_page); ++} ++ ++/* implements ecc->read_oob() */ ++static int qcom_nandc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int r; ++ ++ clear_read_regs(this); ++ ++ this->use_ecc = true; ++ set_address(this, 0, page); ++ update_rw_regs(this, ecc->steps, true); ++ ++ r = read_page_low(this, NULL, chip->oob_poi); ++ if (r) ++ dev_err(this->dev, "failure to read oob\n"); ++ ++ return r; ++} ++ ++/* implements ecc->read_oob_raw(), used to read the bad block marker flag */ ++static int qcom_nandc_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ uint8_t *oob = chip->oob_poi; ++ int start, length; ++ int r; ++ ++ /* ++ * configure registers for a raw page read, the address is set to the ++ * beginning of the last codeword, we don't care about reading ecc ++ * portion of oob, just the free stuff ++ */ ++ r = copy_last_cw(this, false, page); ++ if (r) ++ return r; ++ ++ /* ++ * reading raw oob has 2 parts, first the bad block byte, then the ++ * actual free oob region. perform a memcpy in two steps ++ */ ++ start = mtd->writesize - (this->cw_size * (ecc->steps - 1)); ++ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1; ++ ++ memcpy(oob, this->data_buffer + start, length); ++ ++ oob += length; ++ ++ start = this->cw_data - (ecc->steps << 2) + 1; ++ length = ecc->steps << 2; ++ ++ memcpy(oob, this->data_buffer + start, length); ++ ++ return 0; ++} ++ ++/* implements ecc->write_page() */ ++static int qcom_nandc_write_page(struct mtd_info *mtd, struct nand_chip *chip, ++ const uint8_t *buf, int oob_required) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ u8 *data_buf, *oob_buf; ++ int i, r = 0; ++ ++ clear_read_regs(this); ++ ++ data_buf = (u8 *) buf; ++ oob_buf = chip->oob_poi; ++ ++ this->use_ecc = true; ++ update_rw_regs(this, ecc->steps, false); ++ ++ for (i = 0; i < ecc->steps; i++) { ++ int data_size, oob_size; ++ ++ if (i == (ecc->steps - 1)) { ++ data_size = ecc->size - ((ecc->steps - 1) << 2); ++ oob_size = (ecc->steps << 2) + ecc->bytes; ++ } else { ++ data_size = this->cw_data; ++ oob_size = ecc->bytes; ++ } ++ ++ config_cw_write_pre(this); ++ write_data_dma(this, FLASH_BUF_ACC, data_buf, data_size); ++ ++ /* ++ * we don't really need to write anything to oob for the ++ * first n - 1 codewords since these oob regions just ++ * contain ecc that's written by the controller itself ++ */ ++ if (i == (ecc->steps - 1)) ++ write_data_dma(this, FLASH_BUF_ACC + data_size, ++ oob_buf, oob_size); ++ config_cw_write_post(this); ++ ++ data_buf += data_size; ++ oob_buf += oob_size; ++ } ++ ++ r = submit_descs(this); ++ if (r) ++ dev_err(this->dev, "failure to write page\n"); ++ ++ free_descs(this); ++ ++ return r; ++} ++ ++/* ++ * implements ecc->write_oob() ++ * ++ * the NAND controller cannot write only data or only oob within a codeword, ++ * since ecc is calculated for the combined codeword. we first copy the ++ * entire contents for the last codeword(data + oob), replace the old oob ++ * with the new one in chip->oob_poi, and then write the entire codeword. ++ * this read-copy-write operation results in a slight perormance loss. ++ */ ++static int qcom_nandc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, ++ int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ uint8_t *oob = chip->oob_poi; ++ int free_boff; ++ int data_size, oob_size; ++ int r, status = 0; ++ ++ r = copy_last_cw(this, true, page); ++ if (r) ++ return r; ++ ++ clear_read_regs(this); ++ ++ /* calculate the data and oob size for the last codeword/step */ ++ data_size = ecc->size - ((ecc->steps - 1) << 2); ++ oob_size = (ecc->steps << 2) + ecc->bytes; ++ ++ /* ++ * the location of spare data in the oob buffer, we could also use ++ * ecc->layout.oobfree here ++ */ ++ free_boff = ecc->bytes * (ecc->steps - 1); ++ ++ /* override new oob content to last codeword */ ++ memcpy(this->data_buffer + data_size, oob + free_boff, oob_size); ++ ++ this->use_ecc = true; ++ set_address(this, this->cw_size * (ecc->steps - 1), page); ++ update_rw_regs(this, 1, false); ++ ++ config_cw_write_pre(this); ++ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, ++ data_size + oob_size); ++ config_cw_write_post(this); ++ ++ r = submit_descs(this); ++ ++ free_descs(this); ++ ++ if (r) { ++ dev_err(this->dev, "failure to write oob\n"); ++ return -EIO; ++ } ++ ++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); ++ ++ status = chip->waitfunc(mtd, chip); ++ ++ return status & NAND_STATUS_FAIL ? -EIO : 0; ++} ++ ++/* implements ecc->write_oob_raw(), used to write bad block marker flag */ ++static int qcom_nandc_write_oob_raw(struct mtd_info *mtd, ++ struct nand_chip *chip, int page) ++{ ++ struct qcom_nandc_data *this = chip->priv; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ uint8_t *oob = chip->oob_poi; ++ int start, length; ++ int r, status = 0; ++ ++ r = copy_last_cw(this, false, page); ++ if (r) ++ return r; ++ ++ clear_read_regs(this); ++ ++ /* ++ * writing raw oob has 2 parts, first the bad block region, then the ++ * actual free region ++ */ ++ start = mtd->writesize - (this->cw_size * (ecc->steps - 1)); ++ length = chip->options & NAND_BUSWIDTH_16 ? 2 : 1; ++ ++ memcpy(this->data_buffer + start, oob, length); ++ ++ oob += length; ++ ++ start = this->cw_data - (ecc->steps << 2) + 1; ++ length = ecc->steps << 2; ++ ++ memcpy(this->data_buffer + start, oob, length); ++ ++ /* prepare write */ ++ this->use_ecc = false; ++ set_address(this, this->cw_size * (ecc->steps - 1), page); ++ update_rw_regs(this, 1, false); ++ ++ config_cw_write_pre(this); ++ write_data_dma(this, FLASH_BUF_ACC, this->data_buffer, this->cw_size); ++ config_cw_write_post(this); ++ ++ r = submit_descs(this); ++ ++ free_descs(this); ++ ++ if (r) { ++ dev_err(this->dev, "failure to write updated oob\n"); ++ return -EIO; ++ } ++ ++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); ++ ++ status = chip->waitfunc(mtd, chip); ++ ++ return status & NAND_STATUS_FAIL ? -EIO : 0; ++} ++ ++/* ++ * the three functions below implement chip->read_byte(), chip->read_buf() ++ * and chip->write_buf() respectively. these aren't used for ++ * reading/writing page data, they are used for smaller data like reading ++ * id, status etc ++ */ ++static uint8_t qcom_nandc_read_byte(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct qcom_nandc_data *this = chip->priv; ++ uint8_t *buf = this->data_buffer; ++ uint8_t ret = 0x0; ++ ++ if (this->last_command == NAND_CMD_STATUS) { ++ ret = this->status; ++ ++ this->status = NAND_STATUS_READY | NAND_STATUS_WP; ++ ++ return ret; ++ } ++ ++ if (this->buf_start < this->buf_count) ++ ret = buf[this->buf_start++]; ++ ++ return ret; ++} ++ ++static void qcom_nandc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct qcom_nandc_data *this = chip->priv; ++ int real_len = min_t(size_t, len, this->buf_count - this->buf_start); ++ ++ memcpy(buf, this->data_buffer + this->buf_start, real_len); ++ this->buf_start += real_len; ++} ++ ++static void qcom_nandc_write_buf(struct mtd_info *mtd, const uint8_t *buf, ++ int len) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct qcom_nandc_data *this = chip->priv; ++ int real_len = min_t(size_t, len, this->buf_count - this->buf_start); ++ ++ memcpy(this->data_buffer + this->buf_start, buf, real_len); ++ ++ this->buf_start += real_len; ++} ++ ++/* we support only one external chip for now */ ++static void qcom_nandc_select_chip(struct mtd_info *mtd, int chipnr) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct qcom_nandc_data *this = chip->priv; ++ ++ if (chipnr <= 0) ++ return; ++ ++ dev_warn(this->dev, "invalid chip select\n"); ++} ++ ++/* ++ * NAND controller page layout info ++ * ++ * |-----------------------| |---------------------------------| ++ * | xx.......xx| | *********xx.......xx| ++ * | DATA xx..ECC..xx| | DATA **SPARE**xx..ECC..xx| ++ * | (516) xx.......xx| | (516-n*4) **(n*4)**xx.......xx| ++ * | xx.......xx| | *********xx.......xx| ++ * |-----------------------| |---------------------------------| ++ * codeword 1,2..n-1 codeword n ++ * <---(528/532 Bytes)----> <-------(528/532 Bytes)----------> ++ * ++ * n = number of codewords in the page ++ * . = ECC bytes ++ * * = spare bytes ++ * x = unused/reserved bytes ++ * ++ * 2K page: n = 4, spare = 16 bytes ++ * 4K page: n = 8, spare = 32 bytes ++ * 8K page: n = 16, spare = 64 bytes ++ * ++ * the qcom nand controller operates at a sub page/codeword level. each ++ * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively. ++ * the number of ECC bytes vary based on the ECC strength and the bus width. ++ * ++ * the first n - 1 codewords contains 516 bytes of user data, the remaining ++ * 12/16 bytes consist of ECC and reserved data. The nth codeword contains ++ * both user data and spare(oobavail) bytes that sum up to 516 bytes. ++ * ++ * the layout described above is used by the controller when the ECC block is ++ * enabled. When we read a page with ECC enabled, the unused/reserved bytes are ++ * skipped and not copied to our internal buffer. therefore, the nand_ecclayout ++ * layouts defined below doesn't consider the positions occupied by the reserved ++ * bytes ++ * ++ * when the ECC block is disabled, one unused byte (or two for 16 bit bus width) ++ * in the last codeword is the position of bad block marker. the bad block ++ * marker cannot be accessed when ECC is enabled. ++ * ++ */ ++ ++/* ++ * Layouts for different page sizes and ecc modes. We skip the eccpos field ++ * since it isn't needed for this driver ++ */ ++ ++/* 2K page, 4 bit ECC */ ++static struct nand_ecclayout layout_oob_64 = { ++ .eccbytes = 40, ++ .oobfree = { ++ { 30, 16 }, ++ }, ++}; ++ ++/* 4K page, 4 bit ECC, 8/16 bit bus width */ ++static struct nand_ecclayout layout_oob_128 = { ++ .eccbytes = 80, ++ .oobfree = { ++ { 70, 32 }, ++ }, ++}; ++ ++/* 4K page, 8 bit ECC, 8 bit bus width */ ++static struct nand_ecclayout layout_oob_224_x8 = { ++ .eccbytes = 104, ++ .oobfree = { ++ { 91, 32 }, ++ }, ++}; ++ ++/* 4K page, 8 bit ECC, 16 bit bus width */ ++static struct nand_ecclayout layout_oob_224_x16 = { ++ .eccbytes = 112, ++ .oobfree = { ++ { 98, 32 }, ++ }, ++}; ++ ++/* 8K page, 4 bit ECC, 8/16 bit bus width */ ++static struct nand_ecclayout layout_oob_256 = { ++ .eccbytes = 160, ++ .oobfree = { ++ { 151, 64 }, ++ }, ++}; ++ ++/* ++ * this is called before scan_ident, we do some minimal configurations so ++ * that reading ID and ONFI params work ++ */ ++static void qcom_nandc_pre_init(struct qcom_nandc_data *this) ++{ ++ /* kill onenand */ ++ nandc_write(this, SFLASHC_BURST_CFG, 0); ++ ++ /* enable ADM DMA */ ++ nandc_write(this, NAND_FLASH_CHIP_SELECT, DM_EN); ++ ++ /* save the original values of these registers */ ++ this->cmd1 = nandc_read(this, NAND_DEV_CMD1); ++ this->vld = nandc_read(this, NAND_DEV_CMD_VLD); ++ ++ /* initial status value */ ++ this->status = NAND_STATUS_READY | NAND_STATUS_WP; ++} ++ ++static int qcom_nandc_ecc_init(struct qcom_nandc_data *this) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int cwperpage; ++ bool wide_bus; ++ ++ /* the nand controller fetches codewords/chunks of 512 bytes */ ++ cwperpage = mtd->writesize >> 9; ++ ++ ecc->strength = this->ecc_strength; ++ ++ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; ++ ++ if (ecc->strength >= 8) { ++ /* 8 bit ECC defaults to BCH ECC on all platforms */ ++ ecc->bytes = wide_bus ? 14 : 13; ++ } else { ++ /* ++ * if the controller supports BCH for 4 bit ECC, the controller ++ * uses lesser bytes for ECC. If RS is used, the ECC bytes is ++ * always 10 bytes ++ */ ++ if (this->ecc_modes & ECC_BCH_4BIT) ++ ecc->bytes = wide_bus ? 8 : 7; ++ else ++ ecc->bytes = 10; ++ } ++ ++ /* each step consists of 512 bytes of data */ ++ ecc->size = NANDC_STEP_SIZE; ++ ++ ecc->read_page = qcom_nandc_read_page; ++ ecc->read_oob = qcom_nandc_read_oob; ++ ecc->write_page = qcom_nandc_write_page; ++ ecc->write_oob = qcom_nandc_write_oob; ++ ++ /* ++ * the bad block marker is readable only when we read the page with ECC ++ * disabled. all the ops above run with ECC enabled. We need raw read ++ * and write function for oob in order to access bad block marker. ++ */ ++ ecc->read_oob_raw = qcom_nandc_read_oob_raw; ++ ecc->write_oob_raw = qcom_nandc_write_oob_raw; ++ ++ switch (mtd->oobsize) { ++ case 64: ++ ecc->layout = &layout_oob_64; ++ break; ++ case 128: ++ ecc->layout = &layout_oob_128; ++ break; ++ case 224: ++ if (wide_bus) ++ ecc->layout = &layout_oob_224_x16; ++ else ++ ecc->layout = &layout_oob_224_x8; ++ break; ++ case 256: ++ ecc->layout = &layout_oob_256; ++ break; ++ default: ++ dev_err(this->dev, "unsupported NAND device, oobsize %d\n", ++ mtd->oobsize); ++ return -ENODEV; ++ } ++ ++ ecc->mode = NAND_ECC_HW; ++ ++ /* enable ecc by default */ ++ this->use_ecc = true; ++ ++ return 0; ++} ++ ++static void qcom_nandc_hw_post_init(struct qcom_nandc_data *this) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct nand_ecc_ctrl *ecc = &chip->ecc; ++ int cwperpage = mtd->writesize / ecc->size; ++ int spare_bytes, bad_block_byte; ++ bool wide_bus; ++ int ecc_mode = 0; ++ ++ wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; ++ ++ if (ecc->strength >= 8) { ++ this->cw_size = 532; ++ ++ spare_bytes = wide_bus ? 0 : 2; ++ ++ this->bch_enabled = true; ++ ecc_mode = 1; ++ } else { ++ this->cw_size = 528; ++ ++ if (this->ecc_modes & ECC_BCH_4BIT) { ++ spare_bytes = wide_bus ? 2 : 4; ++ ++ this->bch_enabled = true; ++ ecc_mode = 0; ++ } else { ++ spare_bytes = wide_bus ? 0 : 1; ++ } ++ } ++ ++ /* ++ * DATA_UD_BYTES varies based on whether the read/write command protects ++ * spare data with ECC too. We protect spare data by default, so we set ++ * it to main + spare data, which are 512 and 4 bytes respectively. ++ */ ++ this->cw_data = 516; ++ ++ bad_block_byte = mtd->writesize - this->cw_size * (cwperpage - 1) + 1; ++ ++ this->cfg0 = (cwperpage - 1) << CW_PER_PAGE ++ | this->cw_data << UD_SIZE_BYTES ++ | 0 << DISABLE_STATUS_AFTER_WRITE ++ | 5 << NUM_ADDR_CYCLES ++ | ecc->bytes << ECC_PARITY_SIZE_BYTES_RS ++ | 0 << STATUS_BFR_READ ++ | 1 << SET_RD_MODE_AFTER_STATUS ++ | spare_bytes << SPARE_SIZE_BYTES; ++ ++ this->cfg1 = 7 << NAND_RECOVERY_CYCLES ++ | 0 << CS_ACTIVE_BSY ++ | bad_block_byte << BAD_BLOCK_BYTE_NUM ++ | 0 << BAD_BLOCK_IN_SPARE_AREA ++ | 2 << WR_RD_BSY_GAP ++ | wide_bus << WIDE_FLASH ++ | this->bch_enabled << ENABLE_BCH_ECC; ++ ++ this->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE ++ | this->cw_size << UD_SIZE_BYTES ++ | 5 << NUM_ADDR_CYCLES ++ | 0 << SPARE_SIZE_BYTES; ++ ++ this->cfg1_raw = 7 << NAND_RECOVERY_CYCLES ++ | 0 << CS_ACTIVE_BSY ++ | 17 << BAD_BLOCK_BYTE_NUM ++ | 1 << BAD_BLOCK_IN_SPARE_AREA ++ | 2 << WR_RD_BSY_GAP ++ | wide_bus << WIDE_FLASH ++ | 1 << DEV0_CFG1_ECC_DISABLE; ++ ++ this->ecc_bch_cfg = this->bch_enabled << ECC_CFG_ECC_DISABLE ++ | 0 << ECC_SW_RESET ++ | this->cw_data << ECC_NUM_DATA_BYTES ++ | 1 << ECC_FORCE_CLK_OPEN ++ | ecc_mode << ECC_MODE ++ | ecc->bytes << ECC_PARITY_SIZE_BYTES_BCH; ++ ++ this->ecc_buf_cfg = 0x203 << NUM_STEPS; ++ ++ this->clrflashstatus = FS_READY_BSY_N; ++ this->clrreadstatus = 0xc0; ++ ++ dev_dbg(this->dev, ++ "cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n", ++ this->cfg0, this->cfg1, this->ecc_buf_cfg, ++ this->ecc_bch_cfg, this->cw_size, this->cw_data, ++ ecc->strength, ecc->bytes, cwperpage); ++} ++ ++static int qcom_nandc_alloc(struct qcom_nandc_data *this) ++{ ++ int r; ++ ++ r = dma_set_coherent_mask(this->dev, DMA_BIT_MASK(32)); ++ if (r) { ++ dev_err(this->dev, "failed to set DMA mask\n"); ++ return r; ++ } ++ ++ /* ++ * we use the internal buffer for reading ONFI params, reading small ++ * data like ID and status, and preforming read-copy-write operations ++ * when writing to a codeword partially. 532 is the maximum possible ++ * size of a codeword for our nand controller ++ */ ++ this->buf_size = 532; ++ ++ this->data_buffer = devm_kzalloc(this->dev, this->buf_size, GFP_KERNEL); ++ if (!this->data_buffer) ++ return -ENOMEM; ++ ++ this->regs = devm_kzalloc(this->dev, sizeof(*this->regs), GFP_KERNEL); ++ if (!this->regs) ++ return -ENOMEM; ++ ++ this->reg_read_buf = devm_kzalloc(this->dev, ++ MAX_REG_RD * sizeof(*this->reg_read_buf), ++ GFP_KERNEL); ++ if (!this->reg_read_buf) ++ return -ENOMEM; ++ ++ INIT_LIST_HEAD(&this->list); ++ ++ this->chan = dma_request_slave_channel(this->dev, "rxtx"); ++ if (!this->chan) { ++ dev_err(this->dev, "failed to request slave channel\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static void qcom_nandc_unalloc(struct qcom_nandc_data *this) ++{ ++ dma_release_channel(this->chan); ++} ++ ++static int qcom_nandc_init(struct qcom_nandc_data *this) ++{ ++ struct mtd_info *mtd = &this->mtd; ++ struct nand_chip *chip = &this->chip; ++ struct device_node *np = this->dev->of_node; ++ struct mtd_part_parser_data ppdata = { .of_node = np }; ++ int r; ++ ++ mtd->priv = chip; ++ mtd->name = "qcom-nandc"; ++ mtd->owner = THIS_MODULE; ++ ++ chip->priv = this; ++ ++ chip->cmdfunc = qcom_nandc_command; ++ chip->select_chip = qcom_nandc_select_chip; ++ chip->read_byte = qcom_nandc_read_byte; ++ chip->read_buf = qcom_nandc_read_buf; ++ chip->write_buf = qcom_nandc_write_buf; ++ ++ chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER; ++ if (this->bus_width == 16) ++ chip->options |= NAND_BUSWIDTH_16; ++ ++ chip->bbt_options = NAND_BBT_ACCESS_BBM_RAW; ++ if (of_get_nand_on_flash_bbt(np)) ++ chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; ++ ++ qcom_nandc_pre_init(this); ++ ++ r = nand_scan_ident(mtd, 1, NULL); ++ if (r) ++ return r; ++ ++ r = qcom_nandc_ecc_init(this); ++ if (r) ++ return r; ++ ++ qcom_nandc_hw_post_init(this); ++ ++ r = nand_scan_tail(mtd); ++ if (r) ++ return r; ++ ++ return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); ++} ++ ++static int qcom_nandc_parse_dt(struct platform_device *pdev) ++{ ++ struct qcom_nandc_data *this = platform_get_drvdata(pdev); ++ struct device_node *np = this->dev->of_node; ++ int r; ++ ++ this->ecc_strength = of_get_nand_ecc_strength(np); ++ if (this->ecc_strength < 0) { ++ dev_warn(this->dev, ++ "incorrect ecc strength, setting to 4 bits/step\n"); ++ this->ecc_strength = 4; ++ } ++ ++ this->bus_width = of_get_nand_bus_width(np); ++ if (this->bus_width < 0) { ++ dev_warn(this->dev, "incorrect bus width, setting to 8\n"); ++ this->bus_width = 8; ++ } ++ ++ r = of_property_read_u32(np, "qcom,cmd-crci", &this->cmd_crci); ++ if (r) { ++ dev_err(this->dev, "command CRCI unspecified\n"); ++ return r; ++ } ++ ++ r = of_property_read_u32(np, "qcom,data-crci", &this->data_crci); ++ if (r) { ++ dev_err(this->dev, "data CRCI unspecified\n"); ++ return r; ++ } ++ ++ return 0; ++} ++ ++static int qcom_nandc_probe(struct platform_device *pdev) ++{ ++ struct qcom_nandc_data *this; ++ const struct of_device_id *match; ++ int r; ++ ++ this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL); ++ if (!this) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, this); ++ ++ this->pdev = pdev; ++ this->dev = &pdev->dev; ++ ++ match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev); ++ if (!match) { ++ dev_err(&pdev->dev, "failed to match device\n"); ++ return -ENODEV; ++ } ++ ++ if (!match->data) { ++ dev_err(&pdev->dev, "failed to get device data\n"); ++ return -ENODEV; ++ } ++ ++ this->ecc_modes = (u32) match->data; ++ ++ this->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ this->base = devm_ioremap_resource(&pdev->dev, this->res); ++ if (IS_ERR(this->base)) ++ return PTR_ERR(this->base); ++ ++ this->core_clk = devm_clk_get(&pdev->dev, "core"); ++ if (IS_ERR(this->core_clk)) ++ return PTR_ERR(this->core_clk); ++ ++ this->aon_clk = devm_clk_get(&pdev->dev, "aon"); ++ if (IS_ERR(this->aon_clk)) ++ return PTR_ERR(this->aon_clk); ++ ++ r = qcom_nandc_parse_dt(pdev); ++ if (r) ++ return r; ++ ++ r = qcom_nandc_alloc(this); ++ if (r) ++ return r; ++ ++ r = clk_prepare_enable(this->core_clk); ++ if (r) ++ goto err_core_clk; ++ ++ r = clk_prepare_enable(this->aon_clk); ++ if (r) ++ goto err_aon_clk; ++ ++ r = qcom_nandc_init(this); ++ if (r) ++ goto err_init; ++ ++ return 0; ++ ++err_init: ++ clk_disable_unprepare(this->aon_clk); ++err_aon_clk: ++ clk_disable_unprepare(this->core_clk); ++err_core_clk: ++ qcom_nandc_unalloc(this); ++ ++ return r; ++} ++ ++static int qcom_nandc_remove(struct platform_device *pdev) ++{ ++ struct qcom_nandc_data *this = platform_get_drvdata(pdev); ++ ++ qcom_nandc_unalloc(this); ++ ++ clk_disable_unprepare(this->aon_clk); ++ clk_disable_unprepare(this->core_clk); ++ ++ return 0; ++} ++ ++#define EBI2_NANDC_ECC_MODES (ECC_RS_4BIT | ECC_BCH_8BIT) ++ ++/* ++ * data will hold a struct pointer containing more differences once we support ++ * more IPs ++ */ ++static const struct of_device_id qcom_nandc_of_match[] = { ++ { .compatible = "qcom,ebi2-nandc", ++ .data = (void *) EBI2_NANDC_ECC_MODES, ++ }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, qcom_nandc_of_match); ++ ++static struct platform_driver qcom_nandc_driver = { ++ .driver = { ++ .name = "qcom-nandc", ++ .of_match_table = qcom_nandc_of_match, ++ }, ++ .probe = qcom_nandc_probe, ++ .remove = qcom_nandc_remove, ++}; ++module_platform_driver(qcom_nandc_driver); ++ ++MODULE_AUTHOR("Archit Taneja "); ++MODULE_DESCRIPTION("Qualcomm NAND Controller driver"); ++MODULE_LICENSE("GPL v2"); +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -52,5 +52,6 @@ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nan + obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ + obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o + obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o ++obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o + + nand-objs := nand_base.o nand_bbt.o nand_timings.o diff --git a/target/linux/ipq806x/patches-4.1/163-dt-bindings-qcom_nandc-Add-DT-bindings.patch b/target/linux/ipq806x/patches-4.1/163-dt-bindings-qcom_nandc-Add-DT-bindings.patch new file mode 100644 index 0000000..6530eb1 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/163-dt-bindings-qcom_nandc-Add-DT-bindings.patch @@ -0,0 +1,82 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,3/5] dt/bindings: qcom_nandc: Add DT bindings +From: Archit Taneja +X-Patchwork-Id: 6927141 +Message-Id: <1438578498-32254-4-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja , devicetree@vger.kernel.org +Date: Mon, 3 Aug 2015 10:38:16 +0530 + +Add DT bindings document for the Qualcomm NAND controller driver. + +Cc: devicetree@vger.kernel.org + +v3: +- Don't use '0x' when specifying nand controller address space +- Add optional property for on-flash bbt usage + +Acked-by: Andy Gross +Signed-off-by: Archit Taneja + +--- +.../devicetree/bindings/mtd/qcom_nandc.txt | 49 ++++++++++++++++++++++ + 1 file changed, 49 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +@@ -0,0 +1,49 @@ ++* Qualcomm NAND controller ++ ++Required properties: ++- compatible: should be "qcom,ebi2-nand" for IPQ806x ++- reg: MMIO address range ++- clocks: must contain core clock and always on clock ++- clock-names: must contain "core" for the core clock and "aon" for the ++ always on clock ++- dmas: DMA specifier, consisting of a phandle to the ADM DMA ++ controller node and the channel number to be used for ++ NAND. Refer to dma.txt and qcom_adm.txt for more details ++- dma-names: must be "rxtx" ++- qcom,cmd-crci: must contain the ADM command type CRCI block instance ++ number specified for the NAND controller on the given ++ platform ++- qcom,data-crci: must contain the ADM data type CRCI block instance ++ number specified for the NAND controller on the given ++ platform ++ ++Optional properties: ++- nand-bus-width: bus width. Must be 8 or 16. If not present, 8 is chosen ++ as default ++ ++- nand-ecc-strength: number of bits to correct per ECC step. Must be 4 or 8 ++ bits. If not present, 4 is chosen as default ++- nand-on-flash-bbt: Create/use on-flash bad block table ++ ++The device tree may optionally contain sub-nodes describing partitions of the ++address space. See partition.txt for more detail. ++ ++Example: ++ ++nand@1ac00000 { ++ compatible = "qcom,ebi2-nandc"; ++ reg = <0x1ac00000 0x800>; ++ ++ clocks = <&gcc EBI2_CLK>, ++ <&gcc EBI2_AON_CLK>; ++ clock-names = "core", "aon"; ++ ++ dmas = <&adm_dma 3>; ++ dma-names = "rxtx"; ++ qcom,cmd-crci = <15>; ++ qcom,data-crci = <3>; ++ ++ partition@0 { ++ ... ++ }; ++}; diff --git a/target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch b/target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch new file mode 100644 index 0000000..5049b60 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch @@ -0,0 +1,51 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,4/5] arm: qcom: dts: Add NAND controller node for ipq806x +From: Archit Taneja +X-Patchwork-Id: 6927121 +Message-Id: <1438578498-32254-5-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja , devicetree@vger.kernel.org +Date: Mon, 3 Aug 2015 10:38:17 +0530 + +The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding +compatible string. + +Cc: devicetree@vger.kernel.org + +Reviewed-by: Andy Gross +Signed-off-by: Archit Taneja + +--- +arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -620,6 +620,22 @@ + + status = "disabled"; + }; ++ ++ nand@1ac00000 { ++ compatible = "qcom,ebi2-nandc"; ++ reg = <0x1ac00000 0x800>; ++ ++ clocks = <&gcc EBI2_CLK>, ++ <&gcc EBI2_AON_CLK>; ++ clock-names = "core", "aon"; ++ ++ dmas = <&adm_dma 3>; ++ dma-names = "rxtx"; ++ qcom,cmd-crci = <15>; ++ qcom,data-crci = <3>; ++ ++ status = "disabled"; ++ }; + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-4.1/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch b/target/linux/ipq806x/patches-4.1/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch new file mode 100644 index 0000000..415bf30 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/165-arm-qcom-dts-Enable-NAND-node-on-IPQ8064-AP148-platform.patch @@ -0,0 +1,76 @@ +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v3,5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform +From: Archit Taneja +X-Patchwork-Id: 6927091 +Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org> +To: linux-mtd@lists.infradead.org, dehrenberg@google.com, + cernekee@gmail.com, computersforpeace@gmail.com +Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org, + sboyd@codeaurora.org, linux-kernel@vger.kernel.org, + Archit Taneja , devicetree@vger.kernel.org +Date: Mon, 3 Aug 2015 10:38:18 +0530 + +Enable the NAND controller node on the AP148 platform. Provide pinmux +information. + +Cc: devicetree@vger.kernel.org + +Signed-off-by: Archit Taneja + +--- +arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -61,6 +61,28 @@ + bias-none; + }; + }; ++ nand_pins: nand_pins { ++ mux { ++ pins = "gpio34", "gpio35", "gpio36", ++ "gpio37", "gpio38", "gpio39", ++ "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ function = "nand"; ++ drive-strength = <10>; ++ bias-disable; ++ }; ++ pullups { ++ pins = "gpio39"; ++ bias-pull-up; ++ }; ++ hold { ++ pins = "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ bias-bus-hold; ++ }; ++ }; + }; + + gsbi@16300000 { +@@ -123,5 +145,19 @@ + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + }; ++ ++ nand@1ac00000 { ++ status = "ok"; ++ ++ pinctrl-0 = <&nand_pins>; ++ pinctrl-names = "default"; ++ ++ nand-ecc-strength = <4>; ++ nand-bus-width = <8>; ++ }; + }; + }; ++ ++&adm_dma { ++ status = "ok"; ++}; diff --git a/target/linux/ipq806x/patches-4.1/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch b/target/linux/ipq806x/patches-4.1/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch new file mode 100644 index 0000000..16df418 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/166-arch-qcom-dts-enable-qcom-smem-on-AP148-NAND.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -154,6 +154,8 @@ + + nand-ecc-strength = <4>; + nand-bus-width = <8>; ++ ++ linux,part-probe = "qcom-smem"; + }; + }; + }; diff --git a/target/linux/ipq806x/patches-4.1/300-arch-arm-force-ZRELADDR-on-arch-qcom.patch b/target/linux/ipq806x/patches-4.1/300-arch-arm-force-ZRELADDR-on-arch-qcom.patch new file mode 100644 index 0000000..18b7a80 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/300-arch-arm-force-ZRELADDR-on-arch-qcom.patch @@ -0,0 +1,62 @@ +From b12e230f09d4481424e6a5d7e2ae566b6954e83f Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Wed, 29 Apr 2015 15:21:46 -0700 +Subject: [PATCH] HACK: arch: arm: force ZRELADDR on arch-qcom + +ARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended +on most ARM architectures. This automatically calculate ZRELADDR by +masking PHYS_OFFSET with 0xf8000000. + +However, on IPQ806x, the first ~20MB of RAM is reserved for the hardware +network accelerators, and the bootloader removes this section from the +layout passed from the ATAGS (when used). + +For newer bootloader, when DT is used, this is not a problem, we just +reserve this memory in the device tree. But if the bootloader doesn't +have DT support, then ATAGS have to be used. In this case, the ARM +decompressor will position the kernel in this low mem, which will not be +in the RAM section mapped by the bootloader, which means the kernel will +freeze in the middle of the boot process trying to map the memory. + +As a work around, this patch allows disabling AUTO_ZRELADDR when +ARCH_QCOM is selected. It makes the zImage usage possible on bootloaders +which don't support device-tree, which is the case on certain early +IPQ806x based designs. + +Signed-off-by: Mathieu Olivari +--- + arch/arm/Kconfig | 2 +- + arch/arm/Makefile | 2 ++ + arch/arm/mach-qcom/Makefile.boot | 1 + + 3 files changed, 4 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/mach-qcom/Makefile.boot + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -320,7 +320,7 @@ config ARCH_MULTIPLATFORM + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_HAS_SG_CHAIN + select ARM_PATCH_PHYS_VIRT +- select AUTO_ZRELADDR ++ select AUTO_ZRELADDR if !ARCH_QCOM + select CLKSRC_OF + select COMMON_CLK + select GENERIC_CLOCKEVENTS +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -248,9 +248,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac + else + MACHINE := + endif ++ifeq ($(CONFIG_ARCH_QCOM),) + ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y) + MACHINE := + endif ++endif + + machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) + platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y))) +--- /dev/null ++++ b/arch/arm/mach-qcom/Makefile.boot +@@ -0,0 +1 @@ ++zreladdr-y+= 0x42208000 diff --git a/target/linux/ipq806x/patches-4.1/301-ARM-qcom-add-Netgear-Nighthawk-X4-R7500-device-tree.patch b/target/linux/ipq806x/patches-4.1/301-ARM-qcom-add-Netgear-Nighthawk-X4-R7500-device-tree.patch new file mode 100644 index 0000000..12e06d2 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/301-ARM-qcom-add-Netgear-Nighthawk-X4-R7500-device-tree.patch @@ -0,0 +1,387 @@ +From 7e77aa188a7a7c4391856a9e5ef5ef58f769e679 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Aug 2015 13:02:38 +0200 +Subject: [PATCH] ARM: qcom: add Netgear Nighthawk X4 R7500 device tree + +Signed-off-by: Jonas Gorski +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 370 +++++++++++++++++++++++++++++++ + 2 files changed, 371 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq8064-r7500.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -452,6 +452,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8084-mtp.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-db149.dtb \ ++ qcom-ipq8064-r7500.dtb \ + qcom-msm8660-surf.dtb \ + qcom-msm8960-cdp.dtb \ + qcom-msm8974-sony-xperia-honami.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +@@ -0,0 +1,362 @@ ++#include "qcom-ipq8064-v1.0.dtsi" ++ ++#include ++ ++/ { ++ model = "Netgear Nighthawk X4 R7500"; ++ compatible = "netgear,r7500", "qcom,ipq8064"; ++ ++ memory@0 { ++ reg = <0x42000000 0xe000000>; ++ device_type = "memory"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ rsvd@41200000 { ++ reg = <0x41200000 0x300000>; ++ no-map; ++ }; ++ }; ++ ++ aliases { ++ serial0 = &uart4; ++ mdio-gpio0 = &mdio0; ++ }; ++ ++ chosen { ++ bootargs = "rootfstype=squashfs noinitrd"; ++ linux,stdout-path = "serial0:115200n8"; ++ }; ++ ++ soc { ++ pinmux@800000 { ++ i2c4_pins: i2c4_pinmux { ++ pins = "gpio12", "gpio13"; ++ function = "gsbi4"; ++ bias-disable; ++ }; ++ ++ pcie0_pins: pcie0_pinmux { ++ mux { ++ pins = "gpio3"; ++ function = "pcie1_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ pcie1_pins: pcie1_pinmux { ++ mux { ++ pins = "gpio48"; ++ function = "pcie2_rst"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ ++ nand_pins: nand_pins { ++ mux { ++ pins = "gpio34", "gpio35", "gpio36", ++ "gpio37", "gpio38", "gpio39", ++ "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ function = "nand"; ++ drive-strength = <10>; ++ bias-disable; ++ }; ++ pullups { ++ pins = "gpio39"; ++ bias-pull-up; ++ }; ++ hold { ++ pins = "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ bias-bus-hold; ++ }; ++ }; ++ ++ mdio0_pins: mdio0_pins { ++ mux { ++ pins = "gpio0", "gpio1"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ rgmii2_pins: rgmii2_pins { ++ mux { ++ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", ++ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; ++ function = "rgmii2"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ }; ++ ++ gsbi@16300000 { ++ qcom,mode = ; ++ status = "ok"; ++ serial@16340000 { ++ status = "ok"; ++ }; ++ /* ++ * The i2c device on gsbi4 should not be enabled. ++ * On ipq806x designs gsbi4 i2c is meant for exclusive ++ * RPM usage. Turning this on in kernel manifests as ++ * i2c failure for the RPM. ++ */ ++ }; ++ ++ sata-phy@1b400000 { ++ status = "ok"; ++ }; ++ ++ sata@29000000 { ++ status = "ok"; ++ }; ++ ++ phy@100f8800 { /* USB3 port 1 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@100f8830 { /* USB3 port 1 SS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8800 { /* USB3 port 0 HS phy */ ++ status = "ok"; ++ }; ++ ++ phy@110f8830 { /* USB3 port 0 SS phy */ ++ status = "ok"; ++ }; ++ ++ usb30@0 { ++ status = "ok"; ++ }; ++ ++ usb30@1 { ++ status = "ok"; ++ }; ++ ++ pcie0: pci@1b500000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 3 0>; ++ pinctrl-0 = <&pcie0_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ pcie1: pci@1b700000 { ++ status = "ok"; ++ reset-gpio = <&qcom_pinmux 48 0>; ++ pinctrl-0 = <&pcie1_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ nand@1ac00000 { ++ status = "ok"; ++ ++ pinctrl-0 = <&nand_pins>; ++ pinctrl-names = "default"; ++ ++ nand-ecc-strength = <4>; ++ nand-bus-width = <8>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ qcadata@0 { ++ label = "qcadata"; ++ reg = <0x0000000 0x0c80000>; ++ read-only; ++ }; ++ ++ APPSBL@c80000 { ++ label = "APPSBL"; ++ reg = <0x0c80000 0x0500000>; ++ read-only; ++ }; ++ ++ APPSBLENV@1180000 { ++ label = "APPSBLENV"; ++ reg = <0x1180000 0x0080000>; ++ read-only; ++ }; ++ ++ art: art@1200000 { ++ label = "art"; ++ reg = <0x1200000 0x0140000>; ++ read-only; ++ }; ++ ++ kernel@1340000 { ++ label = "kernel"; ++ reg = <0x1340000 0x0200000>; ++ }; ++ ++ ubi@1540000 { ++ label = "ubi"; ++ reg = <0x1540000 0x1800000>; ++ }; ++ ++ netgear@2d40000 { ++ label = "netgear"; ++ reg = <0x2d40000 0x0c00000>; ++ read-only; ++ }; ++ ++ reserve@3940000 { ++ label = "reserve"; ++ reg = <0x3940000 0x46c0000>; ++ read-only; ++ }; ++ ++ firmware@1340000 { ++ label = "firmware"; ++ reg = <0x1340000 0x1a00000>; ++ }; ++ ++ }; ++ ++ mdio0: mdio { ++ compatible = "virtual,mdio-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>; ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++ ++ phy0: ethernet-phy@0 { ++ device_type = "ethernet-phy"; ++ reg = <0>; ++ qca,ar8327-initvals = < ++ 0x00004 0x7600000 /* PAD0_MODE */ ++ 0x00008 0x1000000 /* PAD5_MODE */ ++ 0x0000c 0x80 /* PAD6_MODE */ ++ 0x000e4 0xaa545 /* MAC_POWER_SEL */ ++ 0x000e0 0xc74164de /* SGMII_CTRL */ ++ 0x0007c 0x4e /* PORT0_STATUS */ ++ 0x00094 0x4e /* PORT6_STATUS */ ++ >; ++ }; ++ ++ phy4: ethernet-phy@4 { ++ device_type = "ethernet-phy"; ++ reg = <4>; ++ }; ++ }; ++ ++ gmac1: ethernet@37200000 { ++ status = "ok"; ++ phy-mode = "rgmii"; ++ phy-handle = <&phy4>; ++ qcom,id = <1>; ++ ++ pinctrl-0 = <&rgmii2_pins>; ++ pinctrl-names = "default"; ++ ++ mtd-mac-address = <&art 6>; ++ }; ++ ++ gmac2: ethernet@37400000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <2>; ++ ++ mtd-mac-address = <&art 0>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ wifi { ++ label = "wifi"; ++ gpios = <&qcom_pinmux 6 1>; ++ linux,code = ; ++ }; ++ ++ reset { ++ label = "reset"; ++ gpios = <&qcom_pinmux 54 1>; ++ linux,code = ; ++ }; ++ ++ wps { ++ label = "wps"; ++ gpios = <&qcom_pinmux 65 1>; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ ++ usb1 { ++ label = "r7500:amber:usb1"; ++ gpios = <&qcom_pinmux 7 0>; ++ }; ++ ++ usb3 { ++ label = "r7500:amber:usb3"; ++ gpios = <&qcom_pinmux 8 0>; ++ }; ++ ++ status { ++ label = "r7500:amber:status"; ++ gpios = <&qcom_pinmux 9 0>; ++ }; ++ ++ internet { ++ label = "r7500:white:internet"; ++ gpios = <&qcom_pinmux 22 0>; ++ }; ++ ++ wan { ++ label = "r7500:white:wan"; ++ gpios = <&qcom_pinmux 23 0>; ++ }; ++ ++ wps { ++ label = "r7500:white:wps"; ++ gpios = <&qcom_pinmux 24 0>; ++ }; ++ ++ esata { ++ label = "r7500:white:esata"; ++ gpios = <&qcom_pinmux 26 0>; ++ }; ++ ++ power { ++ label = "r7500:white:power"; ++ gpios = <&qcom_pinmux 53 0>; ++ default-state = "on"; ++ }; ++ ++ rfkill { ++ label = "r7500:white:rfkill"; ++ gpios = <&qcom_pinmux 64 0>; ++ }; ++ ++ wifi5g { ++ label = "r7500:white:wifi5g"; ++ gpios = <&qcom_pinmux 67 0>; ++ }; ++ }; ++}; ++ ++&adm_dma { ++ status = "ok"; ++}; diff --git a/target/linux/ipq806x/patches-4.1/302-mtd-qcom-smem-rename-rootfs-ubi.patch b/target/linux/ipq806x/patches-4.1/302-mtd-qcom-smem-rename-rootfs-ubi.patch new file mode 100644 index 0000000..471a87b --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/302-mtd-qcom-smem-rename-rootfs-ubi.patch @@ -0,0 +1,13 @@ +--- a/drivers/mtd/qcom_smem_part.c ++++ b/drivers/mtd/qcom_smem_part.c +@@ -192,6 +192,10 @@ static int parse_qcom_smem_partitions(st + m_part->size = le32_to_cpu(s_part->size) * (*smem_blksz); + m_part->offset = le32_to_cpu(s_part->start) * (*smem_blksz); + ++ /* "rootfs" conflicts with OpenWrt auto mounting */ ++ if (mtd_type_is_nand(master) && !strcmp(m_part->name, "rootfs")) ++ m_part->name = "ubi"; ++ + /* + * The last SMEM partition may have its size marked as + * something like 0xffffffff, which means "until the end of the diff --git a/target/linux/ipq806x/patches-4.1/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch b/target/linux/ipq806x/patches-4.1/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch new file mode 100644 index 0000000..dfe7169 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/700-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch @@ -0,0 +1,734 @@ +From 2fbb18f85826a9ba308fedb2cf90d3a661a39fd7 Mon Sep 17 00:00:00 2001 +From: Stephen Boyd +Date: Fri, 27 Mar 2015 00:16:14 -0700 +Subject: [PATCH] clk: qcom: Add support for NSS/GMAC clocks and resets + +Add the NSS/GMAC clocks and the TCM clock and NSS resets. + +Signed-off-by: Stephen Boyd +--- + drivers/clk/qcom/gcc-ipq806x.c | 594 ++++++++++++++++++++++++++- + drivers/clk/qcom/gcc-ipq806x.c.rej | 50 +++ + include/dt-bindings/clock/qcom,gcc-ipq806x.h | 2 + + include/dt-bindings/reset/qcom,gcc-ipq806x.h | 43 ++ + 4 files changed, 688 insertions(+), 1 deletion(-) + create mode 100644 drivers/clk/qcom/gcc-ipq806x.c.rej + +--- a/drivers/clk/qcom/gcc-ipq806x.c ++++ b/drivers/clk/qcom/gcc-ipq806x.c +@@ -220,12 +220,47 @@ static struct clk_regmap pll14_vote = { + }, + }; + ++#define NSS_PLL_RATE(f, _l, _m, _n, i) \ ++ { \ ++ .freq = f, \ ++ .l = _l, \ ++ .m = _m, \ ++ .n = _n, \ ++ .ibits = i, \ ++ } ++ ++static struct pll_freq_tbl pll18_freq_tbl[] = { ++ NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), ++ NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), ++}; ++ ++static struct clk_pll pll18 = { ++ .l_reg = 0x31a4, ++ .m_reg = 0x31a8, ++ .n_reg = 0x31ac, ++ .config_reg = 0x31b4, ++ .mode_reg = 0x31a0, ++ .status_reg = 0x31b8, ++ .status_bit = 16, ++ .post_div_shift = 16, ++ .post_div_width = 1, ++ .freq_tbl = pll18_freq_tbl, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "pll18", ++ .parent_names = (const char *[]){ "pxo" }, ++ .num_parents = 1, ++ .ops = &clk_pll_ops, ++ }, ++}; ++ + enum { + P_PXO, + P_PLL8, + P_PLL3, + P_PLL0, + P_CXO, ++ P_PLL14, ++ P_PLL18, + }; + + static const struct parent_map gcc_pxo_pll8_map[] = { +@@ -277,6 +312,22 @@ static const char *gcc_pxo_pll8_pll0_map + "pll0_vote", + }; + ++static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { ++ { P_PXO, 0 }, ++ { P_PLL8, 4 }, ++ { P_PLL0, 2 }, ++ { P_PLL14, 5 }, ++ { P_PLL18, 1 }, ++}; ++ ++static const char *gcc_pxo_pll8_pll14_pll18_pll0[] = { ++ "pxo", ++ "pll8_vote", ++ "pll0_vote", ++ "pll14", ++ "pll18", ++}; ++ + static struct freq_tbl clk_tbl_gsbi_uart[] = { + { 1843200, P_PLL8, 2, 6, 625 }, + { 3686400, P_PLL8, 2, 12, 625 }, +@@ -2282,6 +2333,472 @@ static struct clk_branch ebi2_aon_clk = + }, + }; + ++static const struct freq_tbl clk_tbl_gmac[] = { ++ { 133000000, P_PLL0, 1, 50, 301 }, ++ { 266000000, P_PLL0, 1, 127, 382 }, ++ { } ++}; ++ ++static struct clk_dyn_rcg gmac_core1_src = { ++ .ns_reg[0] = 0x3cac, ++ .ns_reg[1] = 0x3cb0, ++ .md_reg[0] = 0x3ca4, ++ .md_reg[1] = 0x3ca8, ++ .bank_reg = 0x3ca0, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_gmac, ++ .clkr = { ++ .enable_reg = 0x3ca0, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core1_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gmac_core1_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 4, ++ .hwcg_reg = 0x3cb4, ++ .hwcg_bit = 6, ++ .clkr = { ++ .enable_reg = 0x3cb4, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core1_clk", ++ .parent_names = (const char *[]){ ++ "gmac_core1_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_dyn_rcg gmac_core2_src = { ++ .ns_reg[0] = 0x3ccc, ++ .ns_reg[1] = 0x3cd0, ++ .md_reg[0] = 0x3cc4, ++ .md_reg[1] = 0x3cc8, ++ .bank_reg = 0x3ca0, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_gmac, ++ .clkr = { ++ .enable_reg = 0x3cc0, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core2_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gmac_core2_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 5, ++ .hwcg_reg = 0x3cd4, ++ .hwcg_bit = 6, ++ .clkr = { ++ .enable_reg = 0x3cd4, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core2_clk", ++ .parent_names = (const char *[]){ ++ "gmac_core2_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_dyn_rcg gmac_core3_src = { ++ .ns_reg[0] = 0x3cec, ++ .ns_reg[1] = 0x3cf0, ++ .md_reg[0] = 0x3ce4, ++ .md_reg[1] = 0x3ce8, ++ .bank_reg = 0x3ce0, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_gmac, ++ .clkr = { ++ .enable_reg = 0x3ce0, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core3_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gmac_core3_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 6, ++ .hwcg_reg = 0x3cf4, ++ .hwcg_bit = 6, ++ .clkr = { ++ .enable_reg = 0x3cf4, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core3_clk", ++ .parent_names = (const char *[]){ ++ "gmac_core3_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_dyn_rcg gmac_core4_src = { ++ .ns_reg[0] = 0x3d0c, ++ .ns_reg[1] = 0x3d10, ++ .md_reg[0] = 0x3d04, ++ .md_reg[1] = 0x3d08, ++ .bank_reg = 0x3d00, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_gmac, ++ .clkr = { ++ .enable_reg = 0x3d00, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core4_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gmac_core4_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 7, ++ .hwcg_reg = 0x3d14, ++ .hwcg_bit = 6, ++ .clkr = { ++ .enable_reg = 0x3d14, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac_core4_clk", ++ .parent_names = (const char *[]){ ++ "gmac_core4_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl clk_tbl_nss_tcm[] = { ++ { 266000000, P_PLL0, 3, 0, 0 }, ++ { 400000000, P_PLL0, 2, 0, 0 }, ++ { } ++}; ++ ++static struct clk_dyn_rcg nss_tcm_src = { ++ .ns_reg[0] = 0x3dc4, ++ .ns_reg[1] = 0x3dc8, ++ .bank_reg = 0x3dc0, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 4, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 4, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_nss_tcm, ++ .clkr = { ++ .enable_reg = 0x3dc0, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "nss_tcm_src", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch nss_tcm_clk = { ++ .halt_reg = 0x3c20, ++ .halt_bit = 14, ++ .clkr = { ++ .enable_reg = 0x3dd0, ++ .enable_mask = BIT(6) | BIT(4), ++ .hw.init = &(struct clk_init_data){ ++ .name = "nss_tcm_clk", ++ .parent_names = (const char *[]){ ++ "nss_tcm_src", ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl clk_tbl_nss[] = { ++ { 110000000, P_PLL18, 1, 1, 5 }, ++ { 275000000, P_PLL18, 2, 0, 0 }, ++ { 550000000, P_PLL18, 1, 0, 0 }, ++ { 733000000, P_PLL18, 1, 0, 0 }, ++ { } ++}; ++ ++static struct clk_dyn_rcg ubi32_core1_src_clk = { ++ .ns_reg[0] = 0x3d2c, ++ .ns_reg[1] = 0x3d30, ++ .md_reg[0] = 0x3d24, ++ .md_reg[1] = 0x3d28, ++ .bank_reg = 0x3d20, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_nss, ++ .clkr = { ++ .enable_reg = 0x3d20, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "ubi32_core1_src_clk", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, ++ }, ++ }, ++}; ++ ++static struct clk_dyn_rcg ubi32_core2_src_clk = { ++ .ns_reg[0] = 0x3d4c, ++ .ns_reg[1] = 0x3d50, ++ .md_reg[0] = 0x3d44, ++ .md_reg[1] = 0x3d48, ++ .bank_reg = 0x3d40, ++ .mn[0] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .mn[1] = { ++ .mnctr_en_bit = 8, ++ .mnctr_reset_bit = 7, ++ .mnctr_mode_shift = 5, ++ .n_val_shift = 16, ++ .m_val_shift = 16, ++ .width = 8, ++ }, ++ .s[0] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .s[1] = { ++ .src_sel_shift = 0, ++ .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map, ++ }, ++ .p[0] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .p[1] = { ++ .pre_div_shift = 3, ++ .pre_div_width = 2, ++ }, ++ .mux_sel_bit = 0, ++ .freq_tbl = clk_tbl_nss, ++ .clkr = { ++ .enable_reg = 0x3d40, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "ubi32_core2_src_clk", ++ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, ++ .num_parents = 5, ++ .ops = &clk_dyn_rcg_ops, ++ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, ++ }, ++ }, ++}; ++ + static struct clk_regmap *gcc_ipq806x_clks[] = { + [PLL0] = &pll0.clkr, + [PLL0_VOTE] = &pll0_vote, +@@ -2291,6 +2808,7 @@ static struct clk_regmap *gcc_ipq806x_cl + [PLL8_VOTE] = &pll8_vote, + [PLL14] = &pll14.clkr, + [PLL14_VOTE] = &pll14_vote, ++ [PLL18] = &pll18.clkr, + [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, + [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, + [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, +@@ -2390,6 +2908,18 @@ static struct clk_regmap *gcc_ipq806x_cl + [PLL9] = &hfpll0.clkr, + [PLL10] = &hfpll1.clkr, + [PLL12] = &hfpll_l2.clkr, ++ [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr, ++ [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr, ++ [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr, ++ [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr, ++ [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr, ++ [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr, ++ [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr, ++ [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr, ++ [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr, ++ [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr, ++ [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr, ++ [NSSTCM_CLK] = &nss_tcm_clk.clkr, + }; + + static const struct qcom_reset_map gcc_ipq806x_resets[] = { +@@ -2508,6 +3038,48 @@ static const struct qcom_reset_map gcc_i + [USB30_1_PHY_RESET] = { 0x3b58, 0 }, + [NSSFB0_RESET] = { 0x3b60, 6 }, + [NSSFB1_RESET] = { 0x3b60, 7 }, ++ [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3}, ++ [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 }, ++ [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 }, ++ [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 }, ++ [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 }, ++ [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 }, ++ [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 }, ++ [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 }, ++ [GMAC_CORE1_RESET] = { 0x3cbc, 0 }, ++ [GMAC_CORE2_RESET] = { 0x3cdc, 0 }, ++ [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, ++ [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, ++ [GMAC_AHB_RESET] = { 0x3e24, 0 }, ++ [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, ++ [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, ++ [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, ++ [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 }, ++ [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 }, ++ [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 }, ++ [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 }, ++ [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 }, ++ [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 }, ++ [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 }, ++ [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 }, ++ [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 }, ++ [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 }, ++ [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 }, ++ [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 }, ++ [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 }, ++ [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 }, ++ [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 }, ++ [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 }, ++ [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 }, ++ [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 }, ++ [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 }, ++ [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 }, ++ [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 }, ++ [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 }, ++ [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 }, ++ [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 }, ++ [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 }, ++ [NSS_SRDS_N_RESET] = { 0x3b60, 28 }, + }; + + static const struct regmap_config gcc_ipq806x_regmap_config = { +@@ -2536,6 +3108,8 @@ static int gcc_ipq806x_probe(struct plat + { + struct clk *clk; + struct device *dev = &pdev->dev; ++ struct regmap *regmap; ++ int ret; + + /* Temporary until RPM clocks supported */ + clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); +@@ -2546,7 +3120,25 @@ static int gcc_ipq806x_probe(struct plat + if (IS_ERR(clk)) + return PTR_ERR(clk); + +- return qcom_cc_probe(pdev, &gcc_ipq806x_desc); ++ ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); ++ if (ret) ++ return ret; ++ ++ regmap = dev_get_regmap(dev, NULL); ++ if (!regmap) ++ return -ENODEV; ++ ++ /* Setup PLL18 static bits */ ++ regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400); ++ regmap_write(regmap, 0x31b0, 0x3080); ++ ++ /* Set GMAC footswitch sleep/wakeup values */ ++ regmap_write(regmap, 0x3cb8, 8); ++ regmap_write(regmap, 0x3cd8, 8); ++ regmap_write(regmap, 0x3cf8, 8); ++ regmap_write(regmap, 0x3d18, 8); ++ ++ return 0; + } + + static int gcc_ipq806x_remove(struct platform_device *pdev) +--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h +@@ -129,4 +129,47 @@ + #define USB30_1_PHY_RESET 112 + #define NSSFB0_RESET 113 + #define NSSFB1_RESET 114 ++#define UBI32_CORE1_CLKRST_CLAMP_RESET 115 ++#define UBI32_CORE1_CLAMP_RESET 116 ++#define UBI32_CORE1_AHB_RESET 117 ++#define UBI32_CORE1_AXI_RESET 118 ++#define UBI32_CORE2_CLKRST_CLAMP_RESET 119 ++#define UBI32_CORE2_CLAMP_RESET 120 ++#define UBI32_CORE2_AHB_RESET 121 ++#define UBI32_CORE2_AXI_RESET 122 ++#define GMAC_CORE1_RESET 123 ++#define GMAC_CORE2_RESET 124 ++#define GMAC_CORE3_RESET 125 ++#define GMAC_CORE4_RESET 126 ++#define GMAC_AHB_RESET 127 ++#define NSS_CH0_RST_RX_CLK_N_RESET 128 ++#define NSS_CH0_RST_TX_CLK_N_RESET 129 ++#define NSS_CH0_RST_RX_125M_N_RESET 130 ++#define NSS_CH0_HW_RST_RX_125M_N_RESET 131 ++#define NSS_CH0_RST_TX_125M_N_RESET 132 ++#define NSS_CH1_RST_RX_CLK_N_RESET 133 ++#define NSS_CH1_RST_TX_CLK_N_RESET 134 ++#define NSS_CH1_RST_RX_125M_N_RESET 135 ++#define NSS_CH1_HW_RST_RX_125M_N_RESET 136 ++#define NSS_CH1_RST_TX_125M_N_RESET 137 ++#define NSS_CH2_RST_RX_CLK_N_RESET 138 ++#define NSS_CH2_RST_TX_CLK_N_RESET 139 ++#define NSS_CH2_RST_RX_125M_N_RESET 140 ++#define NSS_CH2_HW_RST_RX_125M_N_RESET 141 ++#define NSS_CH2_RST_TX_125M_N_RESET 142 ++#define NSS_CH3_RST_RX_CLK_N_RESET 143 ++#define NSS_CH3_RST_TX_CLK_N_RESET 144 ++#define NSS_CH3_RST_RX_125M_N_RESET 145 ++#define NSS_CH3_HW_RST_RX_125M_N_RESET 146 ++#define NSS_CH3_RST_TX_125M_N_RESET 147 ++#define NSS_RST_RX_250M_125M_N_RESET 148 ++#define NSS_RST_TX_250M_125M_N_RESET 149 ++#define NSS_QSGMII_TXPI_RST_N_RESET 150 ++#define NSS_QSGMII_CDR_RST_N_RESET 151 ++#define NSS_SGMII2_CDR_RST_N_RESET 152 ++#define NSS_SGMII3_CDR_RST_N_RESET 153 ++#define NSS_CAL_PRBS_RST_N_RESET 154 ++#define NSS_LCKDT_RST_N_RESET 155 ++#define NSS_SRDS_N_RESET 156 ++ + #endif +--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h ++++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h +@@ -289,5 +289,7 @@ + #define UBI32_CORE1_CLK 279 + #define UBI32_CORE2_CLK 280 + #define EBI2_AON_CLK 281 ++#define NSSTCM_CLK_SRC 282 ++#define NSSTCM_CLK 283 + + #endif diff --git a/target/linux/ipq806x/patches-4.1/701-stmmac-add-phy-handle-support-to-the-platform-layer.patch b/target/linux/ipq806x/patches-4.1/701-stmmac-add-phy-handle-support-to-the-platform-layer.patch new file mode 100644 index 0000000..5c29887 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/701-stmmac-add-phy-handle-support-to-the-platform-layer.patch @@ -0,0 +1,105 @@ +From 4f09499bc1d9bb095caccbcd73ff951ee631e521 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 15:42:40 -0700 +Subject: [PATCH 1/8] stmmac: add phy-handle support to the platform layer + +On stmmac driver, PHY specification in device-tree was done using the +non-standard property "snps,phy-addr". Specifying a PHY on a different +MDIO bus that the one within the stmmac controller doesn't seem to be +possible when device-tree is used. + +This change adds support for the phy-handle property, as specified in +Documentation/devicetree/bindings/net/ethernet.txt. + +Signed-off-by: Mathieu Olivari +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 28 ++++++++++++++-------- + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 6 ++++- + include/linux/stmmac.h | 1 + + 3 files changed, 24 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -52,6 +52,7 @@ + #include "stmmac_ptp.h" + #include "stmmac.h" + #include ++#include + + #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) + +@@ -816,18 +817,25 @@ static int stmmac_init_phy(struct net_de + priv->speed = 0; + priv->oldduplex = -1; + +- if (priv->plat->phy_bus_name) +- snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", +- priv->plat->phy_bus_name, priv->plat->bus_id); +- else +- snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", +- priv->plat->bus_id); +- +- snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, +- priv->plat->phy_addr); +- pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); ++ if (priv->plat->phy_node) { ++ phydev = of_phy_connect(dev, priv->plat->phy_node, ++ &stmmac_adjust_link, 0, interface); ++ } else { ++ if (priv->plat->phy_bus_name) ++ snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", ++ priv->plat->phy_bus_name, priv->plat->bus_id); ++ else ++ snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", ++ priv->plat->bus_id); ++ ++ snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, ++ priv->plat->phy_addr); ++ pr_debug("stmmac_init_phy: trying to attach to %s\n", ++ phy_id_fmt); + +- phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface); ++ phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, ++ interface); ++ } + + if (IS_ERR_OR_NULL(phydev)) { + pr_err("%s: Could not attach to PHY\n", dev->name); +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + + #include "stmmac.h" + #include "stmmac_platform.h" +@@ -168,13 +169,16 @@ static int stmmac_probe_config_dt(struct + /* Default to phy auto-detection */ + plat->phy_addr = -1; + ++ /* If we find a phy-handle property, use it as the PHY */ ++ plat->phy_node = of_parse_phandle(np, "phy-handle", 0); ++ + /* "snps,phy-addr" is not a standard property. Mark it as deprecated + * and warn of its use. Remove this when phy node support is added. + */ + if (of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0) + dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n"); + +- if (plat->phy_bus_name) ++ if (plat->phy_node || plat->phy_bus_name) + plat->mdio_bus_data = NULL; + else + plat->mdio_bus_data = +--- a/include/linux/stmmac.h ++++ b/include/linux/stmmac.h +@@ -99,6 +99,7 @@ struct plat_stmmacenet_data { + int phy_addr; + int interface; + struct stmmac_mdio_bus_data *mdio_bus_data; ++ struct device_node *phy_node; + struct stmmac_dma_cfg *dma_cfg; + int clk_csr; + int has_gmac; diff --git a/target/linux/ipq806x/patches-4.1/702-stmmac-move-error-path-at-the-end-of-stmmac_probe_co.patch b/target/linux/ipq806x/patches-4.1/702-stmmac-move-error-path-at-the-end-of-stmmac_probe_co.patch new file mode 100644 index 0000000..37f1002 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/702-stmmac-move-error-path-at-the-end-of-stmmac_probe_co.patch @@ -0,0 +1,65 @@ +From 0149d275415cd1b2382ce94e5eb32641590097d0 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 15:57:12 -0700 +Subject: [PATCH 2/8] stmmac: move error path at the end of + stmmac_probe_config_dt() + +We will want to do additional clean-up on certain errors. Therefore, +this change moves the error path at the end of the function for better +code readability. + +This patch doesn't change anything functionally. + +Signed-off-by: Mathieu Olivari +--- + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 22 ++++++++++++++++------ + 1 file changed, 16 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -130,13 +130,18 @@ static int stmmac_probe_config_dt(struct + struct device_node *np = pdev->dev.of_node; + struct stmmac_dma_cfg *dma_cfg; + const struct of_device_id *device; ++ int ret; + +- if (!np) +- return -ENODEV; ++ if (!np) { ++ ret = -ENODEV; ++ goto err; ++ } + + device = of_match_device(stmmac_dt_ids, &pdev->dev); +- if (!device) +- return -ENODEV; ++ if (!device) { ++ ret = -ENODEV; ++ goto err; ++ } + + if (device->data) { + const struct stmmac_of_data *data = device->data; +@@ -236,8 +241,10 @@ static int stmmac_probe_config_dt(struct + if (of_find_property(np, "snps,pbl", NULL)) { + dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg), + GFP_KERNEL); +- if (!dma_cfg) +- return -ENOMEM; ++ if (!dma_cfg) { ++ ret = -ENOMEM; ++ goto err; ++ } + plat->dma_cfg = dma_cfg; + of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl); + dma_cfg->fixed_burst = +@@ -255,6 +262,9 @@ static int stmmac_probe_config_dt(struct + } + + return 0; ++ ++err: ++ return ret; + } + #else + static int stmmac_probe_config_dt(struct platform_device *pdev, diff --git a/target/linux/ipq806x/patches-4.1/703-stmmac-add-fixed-link-device-tree-support.patch b/target/linux/ipq806x/patches-4.1/703-stmmac-add-fixed-link-device-tree-support.patch new file mode 100644 index 0000000..f2305ac --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/703-stmmac-add-fixed-link-device-tree-support.patch @@ -0,0 +1,64 @@ +From 3a95f75867be562cb919ff23a738f70357188fbd Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 16:02:03 -0700 +Subject: [PATCH 3/8] stmmac: add fixed-link device-tree support + +In case DT is used, this change adds the ability to the stmmac driver to +detect a fixed-link PHY, instanciate it, and use it during +phy_connect(). + +Fixed link PHYs DT usage is described in: +Documentation/devicetree/bindings/net/fixed-link.txt + +Signed-off-by: Mathieu Olivari +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 +++++++++++- + 2 files changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -859,7 +859,7 @@ static int stmmac_init_phy(struct net_de + * device as well. + * Note: phydev->phy_id is the result of reading the UID PHY registers. + */ +- if (phydev->phy_id == 0) { ++ if (!priv->plat->phy_node && phydev->phy_id == 0) { + phy_disconnect(phydev); + return -ENODEV; + } +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -177,6 +177,14 @@ static int stmmac_probe_config_dt(struct + /* If we find a phy-handle property, use it as the PHY */ + plat->phy_node = of_parse_phandle(np, "phy-handle", 0); + ++ /* If phy-handle is not specified, check if we have a fixed-phy */ ++ if (!plat->phy_node && of_phy_is_fixed_link(np)) { ++ if ((of_phy_register_fixed_link(np) < 0)) ++ return -ENODEV; ++ ++ plat->phy_node = of_node_get(np); ++ } ++ + /* "snps,phy-addr" is not a standard property. Mark it as deprecated + * and warn of its use. Remove this when phy node support is added. + */ +@@ -243,7 +251,7 @@ static int stmmac_probe_config_dt(struct + GFP_KERNEL); + if (!dma_cfg) { + ret = -ENOMEM; +- goto err; ++ goto err2; + } + plat->dma_cfg = dma_cfg; + of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl); +@@ -263,6 +271,8 @@ static int stmmac_probe_config_dt(struct + + return 0; + ++err2: ++ of_node_put(np); + err: + return ret; + } diff --git a/target/linux/ipq806x/patches-4.1/704-stmmac-add-ipq806x-glue-layer.patch b/target/linux/ipq806x/patches-4.1/704-stmmac-add-ipq806x-glue-layer.patch new file mode 100644 index 0000000..7fd72be --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/704-stmmac-add-ipq806x-glue-layer.patch @@ -0,0 +1,407 @@ +From 69fb970ad3fe05af7cb99ea78230c69c7ca0d03b Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 16:10:22 -0700 +Subject: [PATCH 4/8] stmmac: add ipq806x glue layer + +The ethernet controller available in IPQ806x is a Synopsys DesignWare +Gigabit MAC IP core, already supported by the stmmac driver. + +This glue layer implements some platform specific settings required to +get the controller working on an IPQ806x based platform. + +Signed-off-by: Mathieu Olivari +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 + + drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +- + drivers/net/ethernet/stmicro/stmmac/dwmac-ipq.c | 324 +++++++++++++++++++++ + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + + .../net/ethernet/stmicro/stmmac/stmmac_platform.h | 1 + + 5 files changed, 328 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq.c + +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -16,6 +16,7 @@ if STMMAC_ETH + config STMMAC_PLATFORM + tristate "STMMAC Platform bus support" + depends on STMMAC_ETH ++ select MFD_SYSCON + default y + ---help--- + This selects the platform specific bus support for the stmmac driver. +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -6,7 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethto + + obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o + stmmac-platform-objs:= stmmac_platform.o dwmac-meson.o dwmac-sunxi.o \ +- dwmac-sti.o dwmac-socfpga.o dwmac-rk.o ++ dwmac-sti.o dwmac-socfpga.o dwmac-rk.o dwmac-ipq806x.o + + obj-$(CONFIG_STMMAC_PCI) += stmmac-pci.o + stmmac-pci-objs:= stmmac_pci.o +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -43,6 +43,7 @@ static const struct of_device_id stmmac_ + { .compatible = "st,stid127-dwmac", .data = &stid127_dwmac_data}, + { .compatible = "st,stih407-dwmac", .data = &stih4xx_dwmac_data}, + { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gmac_data }, ++ { .compatible = "qcom,ipq806x-gmac", .data = &ipq806x_gmac_data }, + { .compatible = "st,spear600-gmac"}, + { .compatible = "snps,dwmac-3.610"}, + { .compatible = "snps,dwmac-3.70a"}, +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h +@@ -25,5 +25,6 @@ extern const struct stmmac_of_data stih4 + extern const struct stmmac_of_data stid127_dwmac_data; + extern const struct stmmac_of_data socfpga_gmac_data; + extern const struct stmmac_of_data rk3288_gmac_data; ++extern const struct stmmac_of_data ipq806x_gmac_data; + + #endif /* __STMMAC_PLATFORM_H__ */ +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c +@@ -0,0 +1,343 @@ ++/* ++ * Qualcomm Atheros IPQ806x GMAC glue layer ++ * ++ * Copyright (C) 2015 The Linux Foundation ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "stmmac_platform.h" ++ ++#define NSS_COMMON_CLK_GATE 0x8 ++#define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x) ++#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2)) ++#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2)) ++#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x) ++#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x) ++ ++#define NSS_COMMON_CLK_DIV0 0xC ++#define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8) ++#define NSS_COMMON_CLK_DIV_MASK 0x7f ++ ++#define NSS_COMMON_CLK_SRC_CTRL 0x14 ++#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (1 << x) ++/* Mode is coded on 1 bit but is different depending on the MAC ID: ++ * MAC0: QSGMII=0 RGMII=1 ++ * MAC1: QSGMII=0 SGMII=0 RGMII=1 ++ * MAC2 & MAC3: QSGMII=0 SGMII=1 ++ */ ++#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1 ++#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0) ++ ++#define NSS_COMMON_MACSEC_CTL 0x28 ++#define NSS_COMMON_MACSEC_CTL_EXT_BYPASS_EN(x) (1 << x) ++ ++#define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4)) ++#define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19) ++#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16) ++#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET 8 ++#define NSS_COMMON_GMAC_CTL_IFG_OFFSET 0 ++#define NSS_COMMON_GMAC_CTL_IFG_MASK 0x3f ++ ++#define NSS_COMMON_CLK_DIV_RGMII_1000 1 ++#define NSS_COMMON_CLK_DIV_RGMII_100 9 ++#define NSS_COMMON_CLK_DIV_RGMII_10 99 ++#define NSS_COMMON_CLK_DIV_SGMII_1000 0 ++#define NSS_COMMON_CLK_DIV_SGMII_100 4 ++#define NSS_COMMON_CLK_DIV_SGMII_10 49 ++ ++#define QSGMII_PCS_MODE_CTL 0x68 ++#define QSGMII_PCS_MODE_CTL_AUTONEG_EN(x) BIT((x * 8) + 7) ++ ++#define QSGMII_PCS_CAL_LCKDT_CTL 0x120 ++#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) ++ ++/* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */ ++#define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \ ++ (0x13c + (4 * (x - 2)))) ++#define QSGMII_PHY_CDR_EN BIT(0) ++#define QSGMII_PHY_RX_FRONT_EN BIT(1) ++#define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2) ++#define QSGMII_PHY_TX_DRIVER_EN BIT(3) ++#define QSGMII_PHY_QSGMII_EN BIT(7) ++#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12 ++#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK 0x7 ++#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18 ++#define QSGMII_PHY_RX_DC_BIAS_MASK 0x3 ++#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20 ++#define QSGMII_PHY_RX_INPUT_EQU_MASK 0x3 ++#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22 ++#define QSGMII_PHY_CDR_PI_SLEW_MASK 0x3 ++#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28 ++#define QSGMII_PHY_TX_DRV_AMP_MASK 0xf ++ ++struct ipq806x_gmac { ++ struct platform_device *pdev; ++ struct regmap *nss_common; ++ struct regmap *qsgmii_csr; ++ uint32_t id; ++ struct clk *core_clk; ++ phy_interface_t phy_mode; ++}; ++ ++static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed) ++{ ++ struct device *dev = &gmac->pdev->dev; ++ int div; ++ ++ switch (speed) { ++ case SPEED_1000: ++ div = NSS_COMMON_CLK_DIV_SGMII_1000; ++ break; ++ ++ case SPEED_100: ++ div = NSS_COMMON_CLK_DIV_SGMII_100; ++ break; ++ ++ case SPEED_10: ++ div = NSS_COMMON_CLK_DIV_SGMII_10; ++ break; ++ ++ default: ++ dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed); ++ return -EINVAL; ++ } ++ ++ return div; ++} ++ ++static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed) ++{ ++ struct device *dev = &gmac->pdev->dev; ++ int div; ++ ++ switch (speed) { ++ case SPEED_1000: ++ div = NSS_COMMON_CLK_DIV_RGMII_1000; ++ break; ++ ++ case SPEED_100: ++ div = NSS_COMMON_CLK_DIV_RGMII_100; ++ break; ++ ++ case SPEED_10: ++ div = NSS_COMMON_CLK_DIV_RGMII_10; ++ break; ++ ++ default: ++ dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed); ++ return -EINVAL; ++ } ++ ++ return div; ++} ++ ++static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed) ++{ ++ uint32_t clk_bits, val; ++ int div; ++ ++ switch (gmac->phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ div = get_clk_div_rgmii(gmac, speed); ++ clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) | ++ NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id); ++ break; ++ ++ case PHY_INTERFACE_MODE_SGMII: ++ div = get_clk_div_sgmii(gmac, speed); ++ clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) | ++ NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id); ++ break; ++ ++ default: ++ dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n", ++ phy_modes(gmac->phy_mode)); ++ return -EINVAL; ++ } ++ ++ /* Disable the clocks */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); ++ val &= ~clk_bits; ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); ++ ++ /* Set the divider */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val); ++ val &= ~(NSS_COMMON_CLK_DIV_MASK ++ << NSS_COMMON_CLK_DIV_OFFSET(gmac->id)); ++ val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id); ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val); ++ ++ /* Enable the clock back */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); ++ val |= clk_bits; ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); ++ ++ return 0; ++} ++ ++static void *ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac) ++{ ++ struct device *dev = &gmac->pdev->dev; ++ ++ gmac->phy_mode = of_get_phy_mode(dev->of_node); ++ if (gmac->phy_mode < 0) { ++ dev_err(dev, "missing phy mode property\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) { ++ dev_err(dev, "missing qcom id property\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ /* The GMACs are called 1 to 4 in the documentation, but to simplify the ++ * code and keep it consistent with the Linux convention, we'll number ++ * them from 0 to 3 here. ++ */ ++ if (gmac->id < 0 || gmac->id > 3) { ++ dev_err(dev, "invalid gmac id\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ gmac->core_clk = devm_clk_get(dev, "stmmaceth"); ++ if (IS_ERR(gmac->core_clk)) { ++ dev_err(dev, "missing stmmaceth clk property\n"); ++ return gmac->core_clk; ++ } ++ clk_set_rate(gmac->core_clk, 266000000); ++ ++ /* Setup the register map for the nss common registers */ ++ gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node, ++ "qcom,nss-common"); ++ if (IS_ERR(gmac->nss_common)) { ++ dev_err(dev, "missing nss-common node\n"); ++ return gmac->nss_common; ++ } ++ ++ /* Setup the register map for the qsgmii csr registers */ ++ gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node, ++ "qcom,qsgmii-csr"); ++ if (IS_ERR(gmac->qsgmii_csr)) { ++ dev_err(dev, "missing qsgmii-csr node\n"); ++ return gmac->qsgmii_csr; ++ } ++ ++ return NULL; ++} ++ ++static void *ipq806x_gmac_setup(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ipq806x_gmac *gmac; ++ int val; ++ void *err; ++ ++ gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); ++ if (!gmac) ++ return ERR_PTR(-ENOMEM); ++ ++ gmac->pdev = pdev; ++ ++ err = ipq806x_gmac_of_parse(gmac); ++ if (err) { ++ dev_err(dev, "device tree parsing error\n"); ++ return err; ++ } ++ ++ regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL, ++ QSGMII_PCS_CAL_LCKDT_CTL_RST); ++ ++ /* Inter frame gap is set to 12 */ ++ val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET | ++ 12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET; ++ /* We also initiate an AXI low power exit request */ ++ val |= NSS_COMMON_GMAC_CTL_CSYS_REQ; ++ switch (gmac->phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL; ++ break; ++ case PHY_INTERFACE_MODE_SGMII: ++ val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL; ++ break; ++ default: ++ dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n", ++ phy_modes(gmac->phy_mode)); ++ return NULL; ++ } ++ regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val); ++ ++ /* Configure the clock src according to the mode */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val); ++ val &= ~NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); ++ switch (gmac->phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) << ++ NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); ++ break; ++ case PHY_INTERFACE_MODE_SGMII: ++ val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) << ++ NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id); ++ break; ++ default: ++ dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n", ++ phy_modes(gmac->phy_mode)); ++ return NULL; ++ } ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val); ++ ++ /* Enable PTP clock */ ++ regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val); ++ val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id); ++ regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val); ++ ++ if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) { ++ regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id), ++ QSGMII_PHY_CDR_EN | ++ QSGMII_PHY_RX_FRONT_EN | ++ QSGMII_PHY_RX_SIGNAL_DETECT_EN | ++ QSGMII_PHY_TX_DRIVER_EN | ++ QSGMII_PHY_QSGMII_EN | ++ 0x4 << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET | ++ 0x3 << QSGMII_PHY_RX_DC_BIAS_OFFSET | ++ 0x1 << QSGMII_PHY_RX_INPUT_EQU_OFFSET | ++ 0x2 << QSGMII_PHY_CDR_PI_SLEW_OFFSET | ++ 0xC << QSGMII_PHY_TX_DRV_AMP_OFFSET); ++ } ++ ++ return gmac; ++} ++ ++static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed) ++{ ++ struct ipq806x_gmac *gmac = priv; ++ ++ ipq806x_gmac_set_speed(gmac, speed); ++} ++ ++const struct stmmac_of_data ipq806x_gmac_data = { ++ .has_gmac = 1, ++ .setup = ipq806x_gmac_setup, ++ .fix_mac_speed = ipq806x_gmac_fix_mac_speed, ++}; diff --git a/target/linux/ipq806x/patches-4.1/705-net-stmmac-ipq806x-document-device-tree-bindings.patch b/target/linux/ipq806x/patches-4.1/705-net-stmmac-ipq806x-document-device-tree-bindings.patch new file mode 100644 index 0000000..3144fa3 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/705-net-stmmac-ipq806x-document-device-tree-bindings.patch @@ -0,0 +1,52 @@ +From 0f9605d9409b77a89daef91cc68239fc2ff50457 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Fri, 8 May 2015 16:51:25 -0700 +Subject: [PATCH 5/8] net: stmmac: ipq806x: document device tree bindings + +Add the device tree bindings documentation for the QCA IPQ806x +variant of the Synopsys DesignWare MAC. + +Signed-off-by: Mathieu Olivari +--- + .../devicetree/bindings/net/ipq806x-dwmac.txt | 35 ++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt +@@ -0,0 +1,35 @@ ++* IPQ806x DWMAC Ethernet controller ++ ++The device inherits all the properties of the dwmac/stmmac devices ++described in the file net/stmmac.txt with the following changes. ++ ++Required properties: ++ ++- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac" ++ and any applicable more detailed version number ++ described in net/stmmac.txt ++ ++- qcom,nss-common: should contain a phandle to a syscon device mapping the ++ nss-common registers. ++ ++- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the ++ qsgmii-csr registers. ++ ++Example: ++ ++ gmac: ethernet@37000000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37000000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE1_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE1_RESET>; ++ reset-names = "stmmaceth"; ++ }; diff --git a/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch b/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch new file mode 100644 index 0000000..0e2b305 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch @@ -0,0 +1,146 @@ +From e81de9d28bd0421c236df322872e64edf4ee1852 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Mon, 11 May 2015 16:32:09 -0700 +Subject: [PATCH 7/8] ARM: dts: qcom: add mdio nodes to ap148 & db149 + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 40 ++++++++++++++++++++++++++- + arch/arm/boot/dts/qcom-ipq8064-db149.dts | 46 ++++++++++++++++++++++++++++++++ + 2 files changed, 85 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -19,8 +19,9 @@ + }; + }; + +- alias { ++ aliases { + serial0 = &uart4; ++ mdio-gpio0 = &mdio0; + }; + + chosen { +@@ -83,6 +84,15 @@ + bias-bus-hold; + }; + }; ++ ++ mdio0_pins: mdio0_pins { ++ mux { ++ pins = "gpio0", "gpio1"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + gsbi@16300000 { +@@ -157,6 +167,34 @@ + + linux,part-probe = "qcom-smem"; + }; ++ ++ mdio0: mdio { ++ compatible = "virtual,mdio-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>; ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++ ++ phy0: ethernet-phy@0 { ++ device_type = "ethernet-phy"; ++ reg = <0>; ++ qca,ar8327-initvals = < ++ 0x00004 0x7600000 /* PAD0_MODE */ ++ 0x00008 0x1000000 /* PAD5_MODE */ ++ 0x0000c 0x80 /* PAD6_MODE */ ++ 0x000e4 0xaa545 /* MAC_POWER_SEL */ ++ 0x000e0 0xc74164de /* SGMII_CTRL */ ++ 0x0007c 0x4e /* PORT0_STATUS */ ++ 0x00094 0x4e /* PORT6_STATUS */ ++ >; ++ }; ++ ++ phy4: ethernet-phy@4 { ++ device_type = "ethernet-phy"; ++ reg = <4>; ++ }; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts +@@ -16,6 +16,7 @@ + + alias { + serial0 = &uart2; ++ mdio-gpio0 = &mdio0; + }; + + chosen { +@@ -65,6 +66,15 @@ + bias-none; + }; + }; ++ ++ mdio0_pins: mdio0_pins { ++ mux { ++ pins = "gpio0", "gpio1"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + gsbi2: gsbi@12480000 { +@@ -176,5 +186,44 @@ + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; + }; ++ ++ mdio0: mdio { ++ compatible = "virtual,mdio-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>; ++ ++ pinctrl-0 = <&mdio0_pins>; ++ pinctrl-names = "default"; ++ ++ phy0: ethernet-phy@0 { ++ device_type = "ethernet-phy"; ++ reg = <0>; ++ qca,ar8327-initvals = < ++ 0x00004 0x7600000 /* PAD0_MODE */ ++ 0x00008 0x1000000 /* PAD5_MODE */ ++ 0x0000c 0x80 /* PAD6_MODE */ ++ 0x000e4 0xaa545 /* MAC_POWER_SEL */ ++ 0x000e0 0xc74164de /* SGMII_CTRL */ ++ 0x0007c 0x4e /* PORT0_STATUS */ ++ 0x00094 0x4e /* PORT6_STATUS */ ++ >; ++ }; ++ ++ phy4: ethernet-phy@4 { ++ device_type = "ethernet-phy"; ++ reg = <4>; ++ }; ++ ++ phy6: ethernet-phy@6 { ++ device_type = "ethernet-phy"; ++ reg = <6>; ++ }; ++ ++ phy7: ethernet-phy@7 { ++ device_type = "ethernet-phy"; ++ reg = <7>; ++ }; ++ }; + }; + }; diff --git a/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch new file mode 100644 index 0000000..0918634 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch @@ -0,0 +1,212 @@ +From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001 +From: Mathieu Olivari +Date: Mon, 11 May 2015 12:29:18 -0700 +Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms + +Signed-off-by: Mathieu Olivari +--- + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++ + arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++ + arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++ + 3 files changed, 160 insertions(+) + +--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +@@ -93,6 +93,16 @@ + bias-disable; + }; + }; ++ ++ rgmii2_pins: rgmii2_pins { ++ mux { ++ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", ++ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ; ++ function = "rgmii2"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + gsbi@16300000 { +@@ -195,6 +205,27 @@ + reg = <4>; + }; + }; ++ ++ gmac1: ethernet@37200000 { ++ status = "ok"; ++ phy-mode = "rgmii"; ++ phy-handle = <&phy4>; ++ qcom,id = <1>; ++ ++ pinctrl-0 = <&rgmii2_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ gmac2: ethernet@37400000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <2>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; + }; + }; + +--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts ++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts +@@ -75,6 +75,14 @@ + bias-disable; + }; + }; ++ ++ rgmii0_pins: rgmii0_pins { ++ mux { ++ pins = "gpio2", "gpio66"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; + }; + + gsbi2: gsbi@12480000 { +@@ -225,5 +233,40 @@ + reg = <7>; + }; + }; ++ ++ gmac0: ethernet@37000000 { ++ status = "ok"; ++ phy-mode = "rgmii"; ++ qcom,id = <0>; ++ phy-handle = <&phy4>; ++ ++ pinctrl-0 = <&rgmii0_pins>; ++ pinctrl-names = "default"; ++ }; ++ ++ gmac1: ethernet@37200000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <1>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ gmac2: ethernet@37400000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <2>; ++ phy-handle = <&phy6>; ++ }; ++ ++ gmac3: ethernet@37600000 { ++ status = "ok"; ++ phy-mode = "sgmii"; ++ qcom,id = <3>; ++ phy-handle = <&phy7>; ++ }; + }; + }; +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -636,6 +636,92 @@ + + status = "disabled"; + }; ++ ++ nss_common: syscon@03000000 { ++ compatible = "syscon"; ++ reg = <0x03000000 0x0000FFFF>; ++ }; ++ ++ qsgmii_csr: syscon@1bb00000 { ++ compatible = "syscon"; ++ reg = <0x1bb00000 0x000001FF>; ++ }; ++ ++ gmac0: ethernet@37000000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37000000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE1_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE1_RESET>; ++ reset-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ ++ gmac1: ethernet@37200000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37200000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE2_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE2_RESET>; ++ reset-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ ++ gmac2: ethernet@37400000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37400000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE3_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE3_RESET>; ++ reset-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ ++ gmac3: ethernet@37600000 { ++ device_type = "network"; ++ compatible = "qcom,ipq806x-gmac"; ++ reg = <0x37600000 0x200000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ ++ qcom,nss-common = <&nss_common>; ++ qcom,qsgmii-csr = <&qsgmii_csr>; ++ ++ clocks = <&gcc GMAC_CORE4_CLK>; ++ clock-names = "stmmaceth"; ++ ++ resets = <&gcc GMAC_CORE4_RESET>; ++ reset-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; + }; + + sfpb_mutex: sfpb-mutex { diff --git a/target/linux/ipq806x/patches-4.1/709-stmac-platform-add-support-for-retreiving-mac-from-m.patch b/target/linux/ipq806x/patches-4.1/709-stmac-platform-add-support-for-retreiving-mac-from-m.patch new file mode 100644 index 0000000..84c15c7 --- /dev/null +++ b/target/linux/ipq806x/patches-4.1/709-stmac-platform-add-support-for-retreiving-mac-from-m.patch @@ -0,0 +1,35 @@ +From 5bf2dabde1fa3af0c9082b42b6847ef3fd198b13 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 9 Aug 2015 12:53:55 +0200 +Subject: [PATCH] stmac: platform: add support for retreiving mac from mtd + +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -302,6 +302,7 @@ static int stmmac_pltfr_probe(struct pla + struct stmmac_priv *priv = NULL; + struct plat_stmmacenet_data *plat_dat = NULL; + const char *mac = NULL; ++ u8 mtd_mac[ETH_ALEN] = { }; + int irq, wol_irq, lpi_irq; + + /* Get IRQ information early to have an ability to ask for deferred +@@ -362,6 +363,15 @@ static int stmmac_pltfr_probe(struct pla + pr_err("%s: main dt probe failed", __func__); + return ret; + } ++ ++ if (!mac) { ++ ret = of_get_mac_address_mtd(dev->of_node, &mtd_mac); ++ if (ret == -EPROBE_DEFER) ++ return ret; ++ ++ if (is_valid_ether_addr(&mtd_mac)) ++ mac = mtd_mac; ++ } + } + + /* Custom setup (if needed) */ diff --git a/target/linux/ipq806x/profiles/default.mk b/target/linux/ipq806x/profiles/default.mk new file mode 100644 index 0000000..6469bcb --- /dev/null +++ b/target/linux/ipq806x/profiles/default.mk @@ -0,0 +1,19 @@ +# +# Copyright (c) 2014 The Linux Foundation. All rights reserved. +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (minimum package set) + PACKAGES:= \ + kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev \ + kmod-usb3 kmod-usb-dwc3-qcom kmod-usb-phy-qcom-dwc3 +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/ipq806x/profiles/netgear.mk b/target/linux/ipq806x/profiles/netgear.mk new file mode 100644 index 0000000..3402f45 --- /dev/null +++ b/target/linux/ipq806x/profiles/netgear.mk @@ -0,0 +1,20 @@ +# +# Copyright (c) 2014 The Linux Foundation. All rights reserved. +# Copyright (C) 2009 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/R7500 + NAME:=Netgear Nighthawk X4 R7500 + PACKAGES:= \ + kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev \ + kmod-usb3 kmod-usb-dwc3-qcom kmod-usb-phy-qcom-dwc3 \ + kmod-ath10k wpad-mini +endef + +define Profile/R7500/Description + Package set for the Netgear Nighthawk X4 R7500. +endef +$(eval $(call Profile,R7500)) diff --git a/target/linux/ixp4xx/Makefile b/target/linux/ixp4xx/Makefile new file mode 100644 index 0000000..c1874fa --- /dev/null +++ b/target/linux/ixp4xx/Makefile @@ -0,0 +1,23 @@ +# +# Copyright (C) 2006-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=armeb +BOARD:=ixp4xx +BOARDNAME:=Intel IXP4xx +FEATURES:=squashfs +MAINTAINER:=Imre Kaloz +SUBTARGETS=generic harddisk + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += ixp4xx-microcode fconfig +KERNELNAME:=zImage + +$(eval $(call BuildTarget)) diff --git a/target/linux/ixp4xx/base-files/lib/ixp4xx.sh b/target/linux/ixp4xx/base-files/lib/ixp4xx.sh new file mode 100644 index 0000000..f7a6b76 --- /dev/null +++ b/target/linux/ixp4xx/base-files/lib/ixp4xx.sh @@ -0,0 +1,25 @@ +#!/bin/sh +# +# Copyright (C) 2012 OpenWrt.org +# + +ixp4xx_board_name() { + local machine + local name + + machine=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /Hardware/ {print $2}' /proc/cpuinfo) + + case "$machine" in + "Gateworks Cambria"*) + name="cambria" + ;; + "Gateworks Avila"*) + name="avila" + ;; + *) + name="generic"; + ;; + esac + + echo $name +} diff --git a/target/linux/ixp4xx/base-files/lib/preinit/05_set_ether_mac_ixp4xx b/target/linux/ixp4xx/base-files/lib/preinit/05_set_ether_mac_ixp4xx new file mode 100644 index 0000000..adda197 --- /dev/null +++ b/target/linux/ixp4xx/base-files/lib/preinit/05_set_ether_mac_ixp4xx @@ -0,0 +1,32 @@ +#!/bin/sh + +set_ether_mac() { + + RB_CONFIG="$(grep "RedBoot config" /proc/mtd | cut -d: -f1)" + + for npe in eth0 eth1 eth2 + do + if [ "$(ifconfig $npe 2>/dev/null | grep -c 00:00:00:00:00:00)" = "1" ]; then + ifconfig $npe hw ether $(fconfig -s -r -d /dev/$RB_CONFIG -n npe_"$npe"_esa) + fi + done + + # Some developers should be shot on sight at Zcom/Netgear + # -- Fixup for the WG302v1, need someone with a WAG302v1 to fix that, too + + if [ "$(ifconfig eth0 2>/dev/null | grep -c 00:00:00:00:00:00)" = "1" ]; then + ifconfig eth0 hw ether $(fconfig -s -r -d /dev/$RB_CONFIG -n zcom_npe_esa) + fi + + # Others (*cough*, Tonze) are dumb enough to not handle mac addresses at all + + if [ "$(ifconfig eth0 2>/dev/null | grep -c 00:00:00:00:00:00)" = "1" ]; then + ifconfig eth0 hw ether 00:11:22:33:44:55 + fi + if [ "$(ifconfig eth1 2>/dev/null | grep -c 00:00:00:00:00:00)" = "1" ]; then + ifconfig eth1 hw ether 00:11:22:33:44:56 + fi +} + +boot_hook_add preinit_main set_ether_mac + diff --git a/target/linux/ixp4xx/base-files/lib/upgrade/platform.sh b/target/linux/ixp4xx/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000..508a167 --- /dev/null +++ b/target/linux/ixp4xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,153 @@ +. /lib/ixp4xx.sh + +RAMFS_COPY_DATA="/lib/ixp4xx.sh" + +CI_BLKSZ=65536 +CI_LDADR=0x00800000 + +platform_find_partitions() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + case "$name" in + vmlinux.bin.l7|kernel|linux|rootfs) + if [ -z "$first" ]; then + first="$name" + else + echo "$erasesize:$first:$name" + break + fi + ;; + esac + done < /proc/mtd +} + +platform_find_kernelpart() { + local part + for part in "${1%:*}" "${1#*:}"; do + case "$part" in + vmlinux.bin.l7|kernel|linux) + echo "$part" + break + ;; + esac + done +} + +platform_find_part_size() { + local first dev size erasesize name + while read dev size erasesize name; do + name=${name#'"'}; name=${name%'"'} + [ "$name" = "$1" ] && { + echo "$size" + break + } + done < /proc/mtd +} + +platform_do_upgrade_combined() { + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local erase_size=$((0x${partitions%%:*})); partitions="${partitions#*:}" + local kern_part_size=0x$(platform_find_part_size "$kernelpart") + local kern_part_blocks=$(($kern_part_size / $CI_BLKSZ)) + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + local kern_blocks=$(($kern_length / $CI_BLKSZ)) + local root_blocks=$((0x$(dd if="$1" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ)) + + v "platform_do_upgrade_combined" + v "partitions=$partitions" + v "kernelpart=$kernelpart" + v "kernel_part_size=$kern_part_size" + v "kernel_part_blocks=$kern_part_blocks" + v "kern_length=$kern_length" + v "erase_size=$erase_size" + v "kern_blocks=$kern_blocks" + v "root_blocks=$root_blocks" + v "kern_pad_blocks=$(($kern_part_blocks-$kern_blocks))" + + if [ -n "$partitions" ] && [ -n "$kernelpart" ] && \ + [ ${kern_blocks:-0} -gt 0 ] && \ + [ ${root_blocks:-0} -gt 0 ] && \ + [ ${erase_size:-0} -gt 0 ]; + then + local append="" + [ -f "$CONF_TAR" -a "$SAVE_CONFIG" -eq 1 ] && append="-j $CONF_TAR" + + # write the kernel + dd if="$1" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null | \ + mtd -F$kernelpart:$kern_part_size:$CI_LDADR write - $kernelpart + # write the rootfs + dd if="$1" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null | \ + mtd $append write - rootfs + else + echo "invalid image" + fi +} + +platform_check_image() { + local board=$(ixp4xx_board_name) + local magic="$(get_magic_word "$1")" + local partitions=$(platform_find_partitions) + local kernelpart=$(platform_find_kernelpart "${partitions#*:}") + local kern_part_size=0x$(platform_find_part_size "$kernelpart") + local kern_length=0x$(dd if="$1" bs=2 skip=1 count=4 2>/dev/null) + + [ "$#" -gt 1 ] && return 1 + + case "$board" in + avila | cambria ) + [ "$magic" != "4349" ] && { + echo "Invalid image. Use *-sysupgrade.bin files on this board" + return 1 + } + + kern_length_b=$(printf '%d' $kern_length) + kern_part_size_b=$(printf '%d' $kern_part_size) + if [ $kern_length_b -gt $kern_part_size_b ]; then + echo "Invalid image. Kernel size ($kern_length) exceeds kernel partition ($kern_part_size)" + return 1 + fi + + local md5_img=$(dd if="$1" bs=2 skip=9 count=16 2>/dev/null) + local md5_chk=$(dd if="$1" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk="${md5_chk%% *}" + if [ -n "$md5_img" -a -n "$md5_chk" ] && [ "$md5_img" = "$md5_chk" ]; then + return 0 + else + echo "Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)" + return 1 + fi + + return 0 + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_do_upgrade() { + local board=$(ixp4xx_board_name) + + v "board=$board" + case "$board" in + avila | cambria ) + platform_do_upgrade_combined "$ARGV" + ;; + *) + default_do_upgrade "$ARGV" + ;; + esac +} + +disable_watchdog() { + v "killing watchdog" + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +# CONFIG_WATCHDOG_NOWAYOUT=y - can't kill watchdog unless kernel cmdline has a mpcore_wdt.nowayout=0 +#append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/ixp4xx/config-3.18 b/target/linux/ixp4xx/config-3.18 new file mode 100644 index 0000000..e8cbce6 --- /dev/null +++ b/target/linux/ixp4xx/config-3.18 @@ -0,0 +1,237 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ARCH_ADI_COYOTE is not set +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_IXCDP1100=y +CONFIG_ARCH_IXDP425=y +CONFIG_ARCH_IXDP4XX=y +CONFIG_ARCH_IXP4XX=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_ARCH_PRPMC1100 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_NR_BANKS=8 +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_THUMB is not set +CONFIG_ATAGS=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_ENDIAN_BE32=y +# CONFIG_CPU_ENDIAN_BE8 is not set +CONFIG_CPU_IXP43X=y +CONFIG_CPU_IXP46X=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CPU_XSCALE=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xc8000003 +# CONFIG_DEBUG_UART_PL01X is not set +CONFIG_DEBUG_UART_VIRT=0xfef00003 +# CONFIG_DEBUG_USER is not set +CONFIG_DMABOUNCE=y +CONFIG_DNOTIFY=y +CONFIG_EEPROM_AT24=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GW_I2C_PLD=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_IXP4XX=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +# CONFIG_I2C_IOP3XX is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_IXP4XX_ETH=y +# CONFIG_IXP4XX_INDIRECT_PCI is not set +CONFIG_IXP4XX_NPE=y +CONFIG_IXP4XX_QMGR=y +CONFIG_IXP4XX_WATCHDOG=y +CONFIG_KTIME_SCALAR=y +CONFIG_LEDS_FSG=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_LATCH=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_MACH_AP1000=y +CONFIG_MACH_AP42X=y +# CONFIG_MACH_ARCOM_VULCAN is not set +CONFIG_MACH_AVILA=y +CONFIG_MACH_CAMBRIA=y +CONFIG_MACH_COMPEXWP18=y +# CONFIG_MACH_DEVIXP is not set +CONFIG_MACH_DSMG600=y +CONFIG_MACH_FSG=y +CONFIG_MACH_GATEWAY7001=y +# CONFIG_MACH_GORAMO_MLR is not set +# CONFIG_MACH_GTWX5715 is not set +# CONFIG_MACH_IXDP465 is not set +CONFIG_MACH_IXDPG425=y +# CONFIG_MACH_KIXRP435 is not set +CONFIG_MACH_LOFT=y +CONFIG_MACH_MI424WR=y +# CONFIG_MACH_MIC256 is not set +# CONFIG_MACH_MICCPT is not set +CONFIG_MACH_NAS100D=y +CONFIG_MACH_NSLU2=y +CONFIG_MACH_PRONGHORN=y +CONFIG_MACH_PRONGHORNMETRO=y +CONFIG_MACH_SIDEWINDER=y +CONFIG_MACH_TW2662=y +CONFIG_MACH_TW5334=y +CONFIG_MACH_USR8200=y +CONFIG_MACH_WG302V1=y +CONFIG_MACH_WG302V2=y +CONFIG_MACH_WRT300NV2=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_IXP4XX=y +CONFIG_MTD_OTP=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_MACH_IO_H=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_VENDOR_XSCALE=y +CONFIG_NO_BOOTMEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1672=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_X1205=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SENSORS_AD7418=y +CONFIG_SENSORS_GSC=y +CONFIG_SENSORS_MAX6650=y +CONFIG_SENSORS_W83781D=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_SUPPORT=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/ixp4xx/config-4.1 b/target/linux/ixp4xx/config-4.1 new file mode 100644 index 0000000..f05779e --- /dev/null +++ b/target/linux/ixp4xx/config-4.1 @@ -0,0 +1,250 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ARCH_ADI_COYOTE is not set +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_IXCDP1100=y +CONFIG_ARCH_IXDP425=y +CONFIG_ARCH_IXDP4XX=y +CONFIG_ARCH_IXP4XX=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_ARCH_PRPMC1100 is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_THUMB is not set +CONFIG_ATAGS=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_ENDIAN_BE32=y +# CONFIG_CPU_ENDIAN_BE8 is not set +CONFIG_CPU_IXP43X=y +CONFIG_CPU_IXP46X=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CPU_XSCALE=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xc8000003 +CONFIG_DEBUG_UART_VIRT=0xfef00003 +# CONFIG_DEBUG_USER is not set +CONFIG_DMABOUNCE=y +CONFIG_DNOTIFY=y +CONFIG_EEPROM_AT24=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GW_I2C_PLD=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_IXP4XX=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_GPIO=y +# CONFIG_I2C_IOP3XX is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_IXP4XX_ETH=y +# CONFIG_IXP4XX_INDIRECT_PCI is not set +CONFIG_IXP4XX_NPE=y +CONFIG_IXP4XX_QMGR=y +CONFIG_IXP4XX_WATCHDOG=y +CONFIG_LEDS_FSG=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_LATCH=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +CONFIG_MACH_AP1000=y +CONFIG_MACH_AP42X=y +# CONFIG_MACH_ARCOM_VULCAN is not set +CONFIG_MACH_AVILA=y +CONFIG_MACH_CAMBRIA=y +CONFIG_MACH_COMPEXWP18=y +# CONFIG_MACH_DEVIXP is not set +CONFIG_MACH_DSMG600=y +CONFIG_MACH_FSG=y +CONFIG_MACH_GATEWAY7001=y +# CONFIG_MACH_GORAMO_MLR is not set +# CONFIG_MACH_GTWX5715 is not set +# CONFIG_MACH_IXDP465 is not set +CONFIG_MACH_IXDPG425=y +# CONFIG_MACH_KIXRP435 is not set +CONFIG_MACH_LOFT=y +CONFIG_MACH_MI424WR=y +# CONFIG_MACH_MIC256 is not set +# CONFIG_MACH_MICCPT is not set +CONFIG_MACH_NAS100D=y +CONFIG_MACH_NSLU2=y +CONFIG_MACH_PRONGHORN=y +CONFIG_MACH_PRONGHORNMETRO=y +CONFIG_MACH_SIDEWINDER=y +CONFIG_MACH_TW2662=y +CONFIG_MACH_TW5334=y +CONFIG_MACH_USR8200=y +CONFIG_MACH_WG302V1=y +CONFIG_MACH_WG302V2=y +CONFIG_MACH_WRT300NV2=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_IXP4XX=y +CONFIG_MTD_OTP=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_MACH_IO_H=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_VENDOR_XSCALE=y +CONFIG_NO_BOOTMEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +# CONFIG_PCI_DOMAINS_GENERIC is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1672=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_X1205=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SENSORS_AD7418=y +CONFIG_SENSORS_GSC=y +CONFIG_SENSORS_MAX6650=y +CONFIG_SENSORS_W83781D=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SRCU=y +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_SUPPORT=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/target/linux/ixp4xx/generic/profiles/100-Default.mk b/target/linux/ixp4xx/generic/profiles/100-Default.mk new file mode 100644 index 0000000..c881c80 --- /dev/null +++ b/target/linux/ixp4xx/generic/profiles/100-Default.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile + PACKAGES:=kmod-ath5k +endef + +define Profile/Default/Description + Default IXP4xx Profile +endef +$(eval $(call Profile,Default)) + diff --git a/target/linux/ixp4xx/generic/profiles/105-Atheros-ath5k.mk b/target/linux/ixp4xx/generic/profiles/105-Atheros-ath5k.mk new file mode 100644 index 0000000..8f74277 --- /dev/null +++ b/target/linux/ixp4xx/generic/profiles/105-Atheros-ath5k.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2006-2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Atheros-ath5k + NAME:=Atheros WiFi (atk5k) + PACKAGES:=kmod-ath5k +endef + +define Profile/Atheros-ath5k/Description + Package set compatible with hardware using Atheros WiFi cards +endef +$(eval $(call Profile,Atheros-ath5k)) + diff --git a/target/linux/ixp4xx/generic/profiles/200-NSLU2.mk b/target/linux/ixp4xx/generic/profiles/200-NSLU2.mk new file mode 100644 index 0000000..93febb0 --- /dev/null +++ b/target/linux/ixp4xx/generic/profiles/200-NSLU2.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2006-2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/NSLU2 + NAME:=Linksys NSLU2 + PACKAGES:=-wpad-mini -kmod-ath5k kmod-scsi-core \ + kmod-usb-core kmod-usb-ohci-pci kmod-usb2-pci kmod-usb-storage \ + kmod-fs-ext4 +endef + +define Profile/NSLU2/Description + Package set optimized for the Linksys NSLU2 +endef +$(eval $(call Profile,NSLU2)) + diff --git a/target/linux/ixp4xx/generic/profiles/300-NAS100d.mk b/target/linux/ixp4xx/generic/profiles/300-NAS100d.mk new file mode 100644 index 0000000..28ac79c --- /dev/null +++ b/target/linux/ixp4xx/generic/profiles/300-NAS100d.mk @@ -0,0 +1,21 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/NAS100d + NAME:=Iomega NAS 100d + PACKAGES:=kmod-ath5k \ + kmod-scsi-core \ + kmod-ata-core kmod-ata-artop \ + kmod-usb-core kmod-usb2-pci kmod-usb-storage \ + kmod-fs-ext4 +endef + +define Profile/NAS100d/Description + Package set optimized for the Iomega NAS 100d +endef +$(eval $(call Profile,NAS100d)) + diff --git a/target/linux/ixp4xx/generic/profiles/400-DSMG600RevA.mk b/target/linux/ixp4xx/generic/profiles/400-DSMG600RevA.mk new file mode 100644 index 0000000..c8b53a8 --- /dev/null +++ b/target/linux/ixp4xx/generic/profiles/400-DSMG600RevA.mk @@ -0,0 +1,22 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DSMG600RevA + NAME:=DSM-G600 Rev A + PACKAGES:=kmod-via-velocity \ + kmod-ath5k \ + kmod-scsi-core \ + kmod-ata-core kmod-ata-artop \ + kmod-usb-core kmod-usb-uhci kmod-usb2-pci kmod-usb-storage \ + kmod-fs-ext4 +endef + +define Profile/DSMG600RevA/Description + Package set optimized for the DSM-G600 Rev A +endef +$(eval $(call Profile,DSMG600RevA)) + diff --git a/target/linux/ixp4xx/generic/profiles/500-USR8200.mk b/target/linux/ixp4xx/generic/profiles/500-USR8200.mk new file mode 100644 index 0000000..02ee059 --- /dev/null +++ b/target/linux/ixp4xx/generic/profiles/500-USR8200.mk @@ -0,0 +1,19 @@ +# +# Copyright (C) 2006-2008 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/USR8200 + NAME:=USRobotics USR8200 + PACKAGES:=-wpad-mini kmod-scsi-core \ + kmod-usb-core kmod-usb-uhci kmod-usb2-pci kmod-usb-storage \ + kmod-fs-ext4 kmod-firewire kmod-firewire-ohci kmod-firewire-sbp2 +endef + +define Profile/USR8200/Description + Package set optimized for the USRobotics USR8200 +endef +$(eval $(call Profile,USR8200)) + diff --git a/target/linux/ixp4xx/generic/target.mk b/target/linux/ixp4xx/generic/target.mk new file mode 100644 index 0000000..f03e2a8 --- /dev/null +++ b/target/linux/ixp4xx/generic/target.mk @@ -0,0 +1,9 @@ +BOARDNAME:=Generic + +DEFAULT_PACKAGES+= wpad-mini + +define Target/Description + Build firmware images for ixp4xx based boards that boot from internal flash + (e.g : Linksys NSLU2, ...) +endef + diff --git a/target/linux/ixp4xx/harddisk/config-default b/target/linux/ixp4xx/harddisk/config-default new file mode 100644 index 0000000..78e599c --- /dev/null +++ b/target/linux/ixp4xx/harddisk/config-default @@ -0,0 +1,20 @@ +CONFIG_ATA=y +CONFIG_BLK_DEV_SD=y +CONFIG_CMDLINE="root=/dev/sda1 noinitrd console=ttyS0,115200" +CONFIG_EXT4_FS=y +CONFIG_JBD=y +CONFIG_REISERFS_FS=y +CONFIG_SATA_VIA=y +CONFIG_USB=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_SPLIT_ISO=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_STORAGE=y diff --git a/target/linux/ixp4xx/harddisk/profiles/100-FSG3.mk b/target/linux/ixp4xx/harddisk/profiles/100-FSG3.mk new file mode 100644 index 0000000..21f5e1f --- /dev/null +++ b/target/linux/ixp4xx/harddisk/profiles/100-FSG3.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/FSG3 + NAME:=Freecom FSG-3 + PACKAGES:= \ + kmod-ath5k \ + kmod-usb-core kmod-usb-uhci kmod-usb2-pci kmod-usb-storage \ + kmod-fs-ext4 kmod-fs-reiserfs +endef + +define Profile/FSG3/Description + Package set optimized for the Freecom FSG-3 +endef +$(eval $(call Profile,FSG3)) + diff --git a/target/linux/ixp4xx/harddisk/target.mk b/target/linux/ixp4xx/harddisk/target.mk new file mode 100644 index 0000000..c71065e --- /dev/null +++ b/target/linux/ixp4xx/harddisk/target.mk @@ -0,0 +1,6 @@ +BOARDNAME:=Internal Hard-Disk + +define Target/Description + Build firmware images for ixp4xx based boards that boot directly from internal disk storage + (e.g : Freecom FSG-3, ...) +endef diff --git a/target/linux/ixp4xx/image/Makefile b/target/linux/ixp4xx/image/Makefile new file mode 100644 index 0000000..bbd62f0 --- /dev/null +++ b/target/linux/ixp4xx/image/Makefile @@ -0,0 +1,71 @@ +# +# Copyright (C) 2006-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +ifdef CONFIG_PACKAGE_apex + define Image/Build/Linksys + BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/slugimage.pl \ + -L $(KDIR)/apex-$(2)-armeb.bin \ + -k $(BIN_DIR)/$(IMG_PREFIX)-$(2)-zImage \ + -r rootfs:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img \ + -p -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).bin + BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/slugimage.pl \ + -F -L $(KDIR)/apex-$(2)-16mb-armeb.bin \ + -k $(BIN_DIR)/$(IMG_PREFIX)-$(2)-zImage \ + -r rootfs:$(BIN_DIR)/$(IMG_PREFIX)-$(1).img \ + -p -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-16mb.bin + endef +endif + +define Image/Build/Freecom + $(INSTALL_DIR) $(TARGET_DIR)/boot + # TODO: Add special CMDLINE shim for webupgrade image here + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(2)-zImage $(TARGET_DIR)/zImage + $(TAR) cfj $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).img --numeric-owner --owner=0 --group=0 -C $(TARGET_DIR)/ . + $(STAGING_DIR_HOST)/bin/encode_crc $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).img $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-webupgrade.img + rm -f $(TARGET_DIR)/zImage +endef + +define Image/BuildKernel + cp $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage + BIN_DIR=$(BIN_DIR) IMG_PREFIX="$(IMG_PREFIX)" $(TOPDIR)/scripts/arm-magic.sh +endef + +# Build sysupgrade image +define BuildFirmware/Generic + dd if=$(KDIR)/zImage of=$(KDIR)/zImage.pad bs=64k conv=sync; \ + dd if=$(KDIR)/root.$(1) of=$(KDIR)/root.$(1).pad bs=128k conv=sync; \ + sh $(TOPDIR)/scripts/combined-image.sh \ + $(KDIR)/zImage.pad \ + $(KDIR)/root.$(1).pad \ + $(BIN_DIR)/$(IMG_PREFIX)-$(patsubst jffs2-%,jffs2,$(patsubst squashfs-%,squashfs,$(1)))-sysupgrade.bin +endef + +define Image/Build + $(call Image/Build/$(1),$(1)) + $(call BuildFirmware/Generic,$(1)) +endef + +define Image/Build/jffs2-64k + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=65536 conv=sync +endef + +define Image/Build/jffs2-128k + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=131072 conv=sync + $(call Image/Build/Linksys,$(1),nslu2,$(1)) + $(call Image/Build/Freecom,$(1),fsg3,$(1)) +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=131072 conv=sync + $(call Image/Build/Linksys,$(1),nslu2,$(1)) + $(call Image/Build/Freecom,$(1),fsg3,$(1)) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/ixp4xx/modules.mk b/target/linux/ixp4xx/modules.mk new file mode 100644 index 0000000..2d6446c --- /dev/null +++ b/target/linux/ixp4xx/modules.mk @@ -0,0 +1,74 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define KernelPackage/ata-ixp4xx-cf + SUBMENU:=$(BLOCK_MENU) + TITLE:=IXP4XX Compact Flash support + DEPENDS:=@TARGET_ixp4xx + KCONFIG:=CONFIG_PATA_IXP4XX_CF + FILES:=$(LINUX_DIR)/drivers/ata/pata_ixp4xx_cf.ko + AUTOLOAD:=$(call AutoLoad,41,pata_ixp4xx_cf,1) + $(call AddDepends/ata) +endef + +define KernelPackage/ata-ixp4xx-cf/description + IXP4XX Compact Flash support. +endef + +$(eval $(call KernelPackage,ata-ixp4xx-cf)) + + +define KernelPackage/ixp4xx-beeper + SUBMENU:=$(OTHER_MENU) + TITLE:=IXP4XX Beeper support + DEPENDS:=@TARGET_ixp4xx +kmod-input-core + KCONFIG:= \ + CONFIG_INPUT_MISC=y \ + CONFIG_INPUT_IXP4XX_BEEPER + FILES:=$(LINUX_DIR)/drivers/input/misc/ixp4xx-beeper.ko + AUTOLOAD:=$(call AutoLoad,50,ixp4xx-beeper) + $(call AddDepends/input) +endef + +define KernelPackage/ixp4xx-beeper/description + IXP4XX Beeper support +endef + +$(eval $(call KernelPackage,ixp4xx-beeper)) + + +define KernelPackage/crypto-hw-ixp4xx + TITLE:=Intel IXP4xx hardware crypto module + DEPENDS:=@TARGET_ixp4xx + KCONFIG:= \ + CONFIG_CRYPTO_DEV_IXP4XX + FILES:=$(LINUX_DIR)/drivers/crypto/ixp4xx_crypto.ko + AUTOLOAD:=$(call AutoLoad,90,ixp4xx_crypto) + $(call AddDepends/crypto,+kmod-crypto-authenc +kmod-crypto-des) +endef + +define KernelPackage/crypto-hw-ixp4xx/description + Kernel support for the Intel IXP4xx HW crypto engine. +endef + +$(eval $(call KernelPackage,crypto-hw-ixp4xx)) + + +define KernelPackage/ixp4xx-eth + SUBMENU:=$(NETWORK_DEVICES_MENU) + TITLE:=IXP4xxt Ethernet Adapter kernel support + DEPENDS:=@TARGET_ixp4xx + KCONFIG:=CONFIG_IXP4XX_ETH + FILES:=$(LINUX_DIR)/drivers/net/ethernet/xscale/ixp4xx_eth.ko + AUTOLOAD:=$(call AutoLoad,50,ixp4xx_eth) +endef + +define KernelPackage/ixp4xx-eth/description + Kernel modules for Intel IXP4xx Ethernet chipsets. +endef + +$(eval $(call KernelPackage,ixp4xx-eth)) diff --git a/target/linux/ixp4xx/patches-3.18/001-arm-ixp4xx-set-cohorent_dma_mask-for-ethernet-platfo.patch b/target/linux/ixp4xx/patches-3.18/001-arm-ixp4xx-set-cohorent_dma_mask-for-ethernet-platfo.patch new file mode 100644 index 0000000..3ca3eb7 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/001-arm-ixp4xx-set-cohorent_dma_mask-for-ethernet-platfo.patch @@ -0,0 +1,136 @@ +From 7113f56b683c5123df5c20724ac813cee66fa21a Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 1 Jul 2013 16:49:05 +0200 +Subject: [PATCH 1/2] arm: ixp4xx: set cohorent_dma_mask for ethernet platform + devices + +ARM requires the cohorent_dma_mask set, so set it for the platform +devices so that the ethernet driver has access to it. + +Signed-off-by: Jonas Gorski +--- + arch/arm/mach-ixp4xx/fsg-setup.c | 2 ++ + arch/arm/mach-ixp4xx/goramo_mlr.c | 2 ++ + arch/arm/mach-ixp4xx/ixdp425-setup.c | 3 +++ + arch/arm/mach-ixp4xx/nas100d-setup.c | 1 + + arch/arm/mach-ixp4xx/nslu2-setup.c | 1 + + arch/arm/mach-ixp4xx/omixp-setup.c | 3 +++ + arch/arm/mach-ixp4xx/vulcan-setup.c | 2 ++ + 7 files changed, 14 insertions(+) + +--- a/arch/arm/mach-ixp4xx/fsg-setup.c ++++ b/arch/arm/mach-ixp4xx/fsg-setup.c +@@ -142,12 +142,14 @@ static struct platform_device fsg_eth[] + .id = IXP4XX_ETH_NPEB, + .dev = { + .platform_data = fsg_plat_eth, ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev = { + .platform_data = fsg_plat_eth + 1, ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + } + }; +--- a/arch/arm/mach-ixp4xx/goramo_mlr.c ++++ b/arch/arm/mach-ixp4xx/goramo_mlr.c +@@ -295,10 +295,12 @@ static struct platform_device device_eth + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = eth_plat, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = eth_plat + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + } + }; + +--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -196,10 +197,12 @@ static struct platform_device ixdp425_et + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = ixdp425_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = ixdp425_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + } + }; + +--- a/arch/arm/mach-ixp4xx/nas100d-setup.c ++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c +@@ -170,6 +170,7 @@ static struct platform_device nas100d_et + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = nas100d_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + } + }; + +--- a/arch/arm/mach-ixp4xx/nslu2-setup.c ++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c +@@ -182,6 +182,7 @@ static struct platform_device nslu2_eth[ + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = nslu2_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + } + }; + +--- a/arch/arm/mach-ixp4xx/omixp-setup.c ++++ b/arch/arm/mach-ixp4xx/omixp-setup.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -188,10 +189,12 @@ static struct platform_device ixdp425_et + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = ixdp425_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = ixdp425_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + }, + }; + +--- a/arch/arm/mach-ixp4xx/vulcan-setup.c ++++ b/arch/arm/mach-ixp4xx/vulcan-setup.c +@@ -139,6 +139,7 @@ static struct platform_device vulcan_eth + .id = IXP4XX_ETH_NPEB, + .dev = { + .platform_data = &vulcan_plat_eth[0], ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, + [1] = { +@@ -146,6 +147,7 @@ static struct platform_device vulcan_eth + .id = IXP4XX_ETH_NPEC, + .dev = { + .platform_data = &vulcan_plat_eth[1], ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, + }; diff --git a/target/linux/ixp4xx/patches-3.18/002-ixp4xx_eth-use-parent-device-for-dma-allocations.patch b/target/linux/ixp4xx/patches-3.18/002-ixp4xx_eth-use-parent-device-for-dma-allocations.patch new file mode 100644 index 0000000..ceaf21b --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/002-ixp4xx_eth-use-parent-device-for-dma-allocations.patch @@ -0,0 +1,95 @@ +From 1d67040af0144c549f4db8144d2ccc253ff8639c Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 1 Jul 2013 16:39:28 +0200 +Subject: [PATCH 2/2] net: ixp4xx_eth: use parent device for dma allocations + +Now that the platfomr device provides a dma_cohorent_mask, use it for +dma operations. + +This fixes ethernet on ixp4xx which was broken since 3.7. + +Signed-off-by: Jonas Gorski +--- + drivers/net/ethernet/xscale/ixp4xx_eth.c | 23 ++++++++++++----------- + 1 file changed, 12 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -657,10 +657,10 @@ static inline void queue_put_desc(unsign + static inline void dma_unmap_tx(struct port *port, struct desc *desc) + { + #ifdef __ARMEB__ +- dma_unmap_single(&port->netdev->dev, desc->data, ++ dma_unmap_single(port->netdev->dev.parent, desc->data, + desc->buf_len, DMA_TO_DEVICE); + #else +- dma_unmap_single(&port->netdev->dev, desc->data & ~3, ++ dma_unmap_single(port->netdev->dev.parent, desc->data & ~3, + ALIGN((desc->data & 3) + desc->buf_len, 4), + DMA_TO_DEVICE); + #endif +@@ -727,9 +727,9 @@ static int eth_poll(struct napi_struct * + + #ifdef __ARMEB__ + if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { +- phys = dma_map_single(&dev->dev, skb->data, ++ phys = dma_map_single(dev->dev.parent, skb->data, + RX_BUFF_SIZE, DMA_FROM_DEVICE); +- if (dma_mapping_error(&dev->dev, phys)) { ++ if (dma_mapping_error(dev->dev.parent, phys)) { + dev_kfree_skb(skb); + skb = NULL; + } +@@ -752,10 +752,11 @@ static int eth_poll(struct napi_struct * + #ifdef __ARMEB__ + temp = skb; + skb = port->rx_buff_tab[n]; +- dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, ++ dma_unmap_single(dev->dev.parent, desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + #else +- dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, ++ dma_sync_single_for_cpu(dev->dev.parent, ++ desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], + ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); +@@ -874,7 +875,7 @@ static int eth_xmit(struct sk_buff *skb, + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); + #endif + +- phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); ++ phys = dma_map_single(dev->dev.parent, mem, bytes, DMA_TO_DEVICE); + if (dma_mapping_error(&dev->dev, phys)) { + dev_kfree_skb(skb); + #ifndef __ARMEB__ +@@ -1124,7 +1125,7 @@ static int init_queues(struct port *port + int i; + + if (!ports_open) { +- dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, ++ dma_pool = dma_pool_create(DRV_NAME, port->netdev->dev.parent, + POOL_ALLOC_SIZE, 32, 0); + if (!dma_pool) + return -ENOMEM; +@@ -1152,9 +1153,9 @@ static int init_queues(struct port *port + data = buff; + #endif + desc->buf_len = MAX_MRU; +- desc->data = dma_map_single(&port->netdev->dev, data, ++ desc->data = dma_map_single(port->netdev->dev.parent, data, + RX_BUFF_SIZE, DMA_FROM_DEVICE); +- if (dma_mapping_error(&port->netdev->dev, desc->data)) { ++ if (dma_mapping_error(port->netdev->dev.parent, desc->data)) { + free_buffer(buff); + return -EIO; + } +@@ -1174,7 +1175,7 @@ static void destroy_queues(struct port * + struct desc *desc = rx_desc_ptr(port, i); + buffer_t *buff = port->rx_buff_tab[i]; + if (buff) { +- dma_unmap_single(&port->netdev->dev, ++ dma_unmap_single(port->netdev->dev.parent, + desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + free_buffer(buff); diff --git a/target/linux/ixp4xx/patches-3.18/020-gateworks_i2c_pld.patch b/target/linux/ixp4xx/patches-3.18/020-gateworks_i2c_pld.patch new file mode 100644 index 0000000..4732d16 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/020-gateworks_i2c_pld.patch @@ -0,0 +1,421 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -794,6 +794,14 @@ config GPIO_RDC321X + Support for the RDC R321x SoC GPIOs over southbridge + PCI configuration space. + ++config GPIO_GW_I2C_PLD ++ tristate "Gateworks I2C PLD GPIO Expander" ++ depends on I2C ++ help ++ Say yes here to provide access to the Gateworks I2C PLD GPIO ++ Expander. This is used at least on the GW2358-4. ++ ++ + comment "SPI GPIO expanders:" + + config GPIO_MAX7301 +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -106,3 +106,4 @@ obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx + obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o + obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o + obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o ++obj-$(CONFIG_GPIO_GW_I2C_PLD) += gw_i2c_pld.o +--- /dev/null ++++ b/drivers/gpio/gw_i2c_pld.c +@@ -0,0 +1,371 @@ ++/* ++ * Gateworks I2C PLD GPIO expander ++ * ++ * Copyright (C) 2009 Gateworks Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const struct i2c_device_id gw_i2c_pld_id[] = { ++ { "gw_i2c_pld", 8 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, gw_i2c_pld_id); ++ ++/* ++ * The Gateworks I2C PLD chip only expose one read and one ++ * write register. Writing a "one" bit (to match the reset state) lets ++ * that pin be used as an input. It is an open-drain model. ++ */ ++ ++struct gw_i2c_pld { ++ struct gpio_chip chip; ++ struct i2c_client *client; ++ unsigned out; /* software latch */ ++}; ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * The Gateworks I2C PLD chip does not properly send the acknowledge bit ++ * thus we cannot use standard i2c_smbus functions. We have recreated ++ * our own here, but we still use the rt_mutex_lock to lock the i2c_bus ++ * as the device still exists on the I2C bus. ++*/ ++ ++#define PLD_SCL_GPIO 6 ++#define PLD_SDA_GPIO 7 ++ ++#define SCL_LO() gpio_line_set(PLD_SCL_GPIO, IXP4XX_GPIO_LOW) ++#define SCL_HI() gpio_line_set(PLD_SCL_GPIO, IXP4XX_GPIO_HIGH) ++#define SCL_EN() gpio_line_config(PLD_SCL_GPIO, IXP4XX_GPIO_OUT) ++#define SDA_LO() gpio_line_set(PLD_SDA_GPIO, IXP4XX_GPIO_LOW) ++#define SDA_HI() gpio_line_set(PLD_SDA_GPIO, IXP4XX_GPIO_HIGH) ++#define SDA_EN() gpio_line_config(PLD_SDA_GPIO, IXP4XX_GPIO_OUT) ++#define SDA_DIS() gpio_line_config(PLD_SDA_GPIO, IXP4XX_GPIO_IN) ++#define SDA_IN(x) gpio_line_get(PLD_SDA_GPIO, &x); ++ ++static int i2c_pld_write_byte(int address, int byte) ++{ ++ int i; ++ ++ address = (address << 1) & ~0x1; ++ ++ SDA_HI(); ++ SDA_EN(); ++ SCL_EN(); ++ SCL_HI(); ++ SDA_LO(); ++ SCL_LO(); ++ ++ for (i = 7; i >= 0; i--) ++ { ++ if (address & (1 << i)) ++ SDA_HI(); ++ else ++ SDA_LO(); ++ ++ SCL_HI(); ++ SCL_LO(); ++ } ++ ++ SDA_DIS(); ++ SCL_HI(); ++ SDA_IN(i); ++ SCL_LO(); ++ SDA_EN(); ++ ++ for (i = 7; i >= 0; i--) ++ { ++ if (byte & (1 << i)) ++ SDA_HI(); ++ else ++ SDA_LO(); ++ SCL_HI(); ++ SCL_LO(); ++ } ++ ++ SDA_DIS(); ++ SCL_HI(); ++ SDA_IN(i); ++ SCL_LO(); ++ ++ SDA_HI(); ++ SDA_EN(); ++ ++ SDA_LO(); ++ SCL_HI(); ++ SDA_HI(); ++ SCL_LO(); ++ SCL_HI(); ++ ++ return 0; ++} ++ ++static unsigned int i2c_pld_read_byte(int address) ++{ ++ int i = 0, byte = 0; ++ int bit; ++ ++ address = (address << 1) | 0x1; ++ ++ SDA_HI(); ++ SDA_EN(); ++ SCL_EN(); ++ SCL_HI(); ++ SDA_LO(); ++ SCL_LO(); ++ ++ for (i = 7; i >= 0; i--) ++ { ++ if (address & (1 << i)) ++ SDA_HI(); ++ else ++ SDA_LO(); ++ ++ SCL_HI(); ++ SCL_LO(); ++ } ++ ++ SDA_DIS(); ++ SCL_HI(); ++ SDA_IN(i); ++ SCL_LO(); ++ SDA_EN(); ++ ++ SDA_DIS(); ++ for (i = 7; i >= 0; i--) ++ { ++ SCL_HI(); ++ SDA_IN(bit); ++ byte |= bit << i; ++ SCL_LO(); ++ } ++ ++ SDA_LO(); ++ SCL_HI(); ++ SDA_HI(); ++ SCL_LO(); ++ SCL_HI(); ++ ++ return byte; ++} ++ ++ ++static int gw_i2c_pld_input8(struct gpio_chip *chip, unsigned offset) ++{ ++ int ret; ++ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip); ++ struct i2c_adapter *adap = gpio->client->adapter; ++ ++ if (in_atomic() || irqs_disabled()) { ++ ret = rt_mutex_trylock(&adap->bus_lock); ++ if (!ret) ++ /* I2C activity is ongoing. */ ++ return -EAGAIN; ++ } else { ++ rt_mutex_lock(&adap->bus_lock); ++ } ++ ++ gpio->out |= (1 << offset); ++ ++ ret = i2c_pld_write_byte(gpio->client->addr, gpio->out); ++ ++ rt_mutex_unlock(&adap->bus_lock); ++ ++ return ret; ++} ++ ++static int gw_i2c_pld_get8(struct gpio_chip *chip, unsigned offset) ++{ ++ int ret; ++ s32 value; ++ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip); ++ struct i2c_adapter *adap = gpio->client->adapter; ++ ++ if (in_atomic() || irqs_disabled()) { ++ ret = rt_mutex_trylock(&adap->bus_lock); ++ if (!ret) ++ /* I2C activity is ongoing. */ ++ return -EAGAIN; ++ } else { ++ rt_mutex_lock(&adap->bus_lock); ++ } ++ ++ value = i2c_pld_read_byte(gpio->client->addr); ++ ++ rt_mutex_unlock(&adap->bus_lock); ++ ++ return (value < 0) ? 0 : (value & (1 << offset)); ++} ++ ++static int gw_i2c_pld_output8(struct gpio_chip *chip, unsigned offset, int value) ++{ ++ int ret; ++ ++ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip); ++ struct i2c_adapter *adap = gpio->client->adapter; ++ ++ unsigned bit = 1 << offset; ++ ++ if (in_atomic() || irqs_disabled()) { ++ ret = rt_mutex_trylock(&adap->bus_lock); ++ if (!ret) ++ /* I2C activity is ongoing. */ ++ return -EAGAIN; ++ } else { ++ rt_mutex_lock(&adap->bus_lock); ++ } ++ ++ ++ if (value) ++ gpio->out |= bit; ++ else ++ gpio->out &= ~bit; ++ ++ ret = i2c_pld_write_byte(gpio->client->addr, gpio->out); ++ ++ rt_mutex_unlock(&adap->bus_lock); ++ ++ return ret; ++} ++ ++static void gw_i2c_pld_set8(struct gpio_chip *chip, unsigned offset, int value) ++{ ++ gw_i2c_pld_output8(chip, offset, value); ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int gw_i2c_pld_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct gw_i2c_pld_platform_data *pdata; ++ struct gw_i2c_pld *gpio; ++ int status; ++ ++ pdata = client->dev.platform_data; ++ if (!pdata) ++ return -ENODEV; ++ ++ /* Allocate, initialize, and register this gpio_chip. */ ++ gpio = kzalloc(sizeof *gpio, GFP_KERNEL); ++ if (!gpio) ++ return -ENOMEM; ++ ++ gpio->chip.base = pdata->gpio_base; ++ gpio->chip.can_sleep = 1; ++ gpio->chip.dev = &client->dev; ++ gpio->chip.owner = THIS_MODULE; ++ ++ gpio->chip.ngpio = pdata->nr_gpio; ++ gpio->chip.direction_input = gw_i2c_pld_input8; ++ gpio->chip.get = gw_i2c_pld_get8; ++ gpio->chip.direction_output = gw_i2c_pld_output8; ++ gpio->chip.set = gw_i2c_pld_set8; ++ ++ gpio->chip.label = client->name; ++ ++ gpio->client = client; ++ i2c_set_clientdata(client, gpio); ++ ++ gpio->out = 0xFF; ++ ++ status = gpiochip_add(&gpio->chip); ++ if (status < 0) ++ goto fail; ++ ++ dev_info(&client->dev, "gpios %d..%d on a %s%s\n", ++ gpio->chip.base, ++ gpio->chip.base + gpio->chip.ngpio - 1, ++ client->name, ++ client->irq ? " (irq ignored)" : ""); ++ ++ /* Let platform code set up the GPIOs and their users. ++ * Now is the first time anyone could use them. ++ */ ++ if (pdata->setup) { ++ status = pdata->setup(client, ++ gpio->chip.base, gpio->chip.ngpio, ++ pdata->context); ++ if (status < 0) ++ dev_warn(&client->dev, "setup --> %d\n", status); ++ } ++ ++ return 0; ++ ++fail: ++ dev_dbg(&client->dev, "probe error %d for '%s'\n", ++ status, client->name); ++ kfree(gpio); ++ return status; ++} ++ ++static int gw_i2c_pld_remove(struct i2c_client *client) ++{ ++ struct gw_i2c_pld_platform_data *pdata = client->dev.platform_data; ++ struct gw_i2c_pld *gpio = i2c_get_clientdata(client); ++ int status = 0; ++ ++ if (pdata->teardown) { ++ status = pdata->teardown(client, ++ gpio->chip.base, gpio->chip.ngpio, ++ pdata->context); ++ if (status < 0) { ++ dev_err(&client->dev, "%s --> %d\n", ++ "teardown", status); ++ return status; ++ } ++ } ++ ++ gpiochip_remove(&gpio->chip); ++ kfree(gpio); ++ return 0; ++} ++ ++static struct i2c_driver gw_i2c_pld_driver = { ++ .driver = { ++ .name = "gw_i2c_pld", ++ .owner = THIS_MODULE, ++ }, ++ .probe = gw_i2c_pld_probe, ++ .remove = gw_i2c_pld_remove, ++ .id_table = gw_i2c_pld_id, ++}; ++ ++static int __init gw_i2c_pld_init(void) ++{ ++ return i2c_add_driver(&gw_i2c_pld_driver); ++} ++module_init(gw_i2c_pld_init); ++ ++static void __exit gw_i2c_pld_exit(void) ++{ ++ i2c_del_driver(&gw_i2c_pld_driver); ++} ++module_exit(gw_i2c_pld_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chris Lang"); +--- /dev/null ++++ b/include/linux/i2c/gw_i2c_pld.h +@@ -0,0 +1,20 @@ ++#ifndef __LINUX_GW_I2C_PLD_H ++#define __LINUX_GW_I2C_PLD_H ++ ++/** ++ * The Gateworks I2C PLD Implements an additional 8 bits of GPIO through the PLD ++ */ ++ ++struct gw_i2c_pld_platform_data { ++ unsigned gpio_base; ++ unsigned nr_gpio; ++ int (*setup)(struct i2c_client *client, ++ int gpio, unsigned ngpio, ++ void *context); ++ int (*teardown)(struct i2c_client *client, ++ int gpio, unsigned ngpio, ++ void *context); ++ void *context; ++}; ++ ++#endif /* __LINUX_GW_I2C_PLD_H */ diff --git a/target/linux/ixp4xx/patches-3.18/030-gpio_line_config.patch b/target/linux/ixp4xx/patches-3.18/030-gpio_line_config.patch new file mode 100644 index 0000000..0e51793 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/030-gpio_line_config.patch @@ -0,0 +1,73 @@ +--- a/arch/arm/mach-ixp4xx/common.c ++++ b/arch/arm/mach-ixp4xx/common.c +@@ -93,22 +93,7 @@ void __init ixp4xx_map_io(void) + /* + * GPIO-functions + */ +-/* +- * The following converted to the real HW bits the gpio_line_config +- */ +-/* GPIO pin types */ +-#define IXP4XX_GPIO_OUT 0x1 +-#define IXP4XX_GPIO_IN 0x2 +- +-/* GPIO signal types */ +-#define IXP4XX_GPIO_LOW 0 +-#define IXP4XX_GPIO_HIGH 1 +- +-/* GPIO Clocks */ +-#define IXP4XX_GPIO_CLK_0 14 +-#define IXP4XX_GPIO_CLK_1 15 +- +-static void gpio_line_config(u8 line, u32 direction) ++void gpio_line_config(u8 line, u32 direction) + { + if (direction == IXP4XX_GPIO_IN) + *IXP4XX_GPIO_GPOER |= (1 << line); +@@ -116,17 +101,17 @@ static void gpio_line_config(u8 line, u3 + *IXP4XX_GPIO_GPOER &= ~(1 << line); + } + +-static void gpio_line_get(u8 line, int *value) ++void gpio_line_get(u8 line, int *value) + { + *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1; + } + +-static void gpio_line_set(u8 line, int value) ++void gpio_line_set(u8 line, int value) + { +- if (value == IXP4XX_GPIO_HIGH) +- *IXP4XX_GPIO_GPOUTR |= (1 << line); +- else if (value == IXP4XX_GPIO_LOW) ++ if (value == IXP4XX_GPIO_LOW) + *IXP4XX_GPIO_GPOUTR &= ~(1 << line); ++ else ++ *IXP4XX_GPIO_GPOUTR |= (1 << line); + } + + /************************************************************************* +--- a/arch/arm/mach-ixp4xx/include/mach/platform.h ++++ b/arch/arm/mach-ixp4xx/include/mach/platform.h +@@ -131,5 +131,21 @@ struct pci_sys_data; + extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); + extern struct pci_ops ixp4xx_ops; + ++/* GPIO pin types */ ++#define IXP4XX_GPIO_OUT 0x1 ++#define IXP4XX_GPIO_IN 0x2 ++ ++/* GPIO signal types */ ++#define IXP4XX_GPIO_LOW 0 ++#define IXP4XX_GPIO_HIGH 1 ++ ++/* GPIO Clocks */ ++#define IXP4XX_GPIO_CLK_0 14 ++#define IXP4XX_GPIO_CLK_1 15 ++ ++void gpio_line_config(u8 line, u32 direction); ++void gpio_line_get(u8 line, int *value); ++void gpio_line_set(u8 line, int value); ++ + #endif // __ASSEMBLY__ + diff --git a/target/linux/ixp4xx/patches-3.18/090-increase_entropy_pools.patch b/target/linux/ixp4xx/patches-3.18/090-increase_entropy_pools.patch new file mode 100644 index 0000000..285505c --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/090-increase_entropy_pools.patch @@ -0,0 +1,17 @@ +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -285,11 +285,11 @@ + /* + * Configuration information + */ +-#define INPUT_POOL_SHIFT 12 ++#define INPUT_POOL_SHIFT 13 + #define INPUT_POOL_WORDS (1 << (INPUT_POOL_SHIFT-5)) +-#define OUTPUT_POOL_SHIFT 10 ++#define OUTPUT_POOL_SHIFT 11 + #define OUTPUT_POOL_WORDS (1 << (OUTPUT_POOL_SHIFT-5)) +-#define SEC_XFER_SIZE 512 ++#define SEC_XFER_SIZE 1024 + #define EXTRACT_SIZE 10 + + #define DEBUG_RANDOM_BOOT 0 diff --git a/target/linux/ixp4xx/patches-3.18/100-wg302v2_gateway7001_mac_plat_info.patch b/target/linux/ixp4xx/patches-3.18/100-wg302v2_gateway7001_mac_plat_info.patch new file mode 100644 index 0000000..317103f --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/100-wg302v2_gateway7001_mac_plat_info.patch @@ -0,0 +1,78 @@ +--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c ++++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -75,9 +76,37 @@ static struct platform_device gateway700 + .resource = &gateway7001_uart_resource, + }; + ++static struct eth_plat_info gateway7001_plat_eth[] = { ++ { ++ .phy = 1, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 2, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device gateway7001_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = gateway7001_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = gateway7001_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ + static struct platform_device *gateway7001_devices[] __initdata = { + &gateway7001_flash, +- &gateway7001_uart ++ &gateway7001_uart, ++ &gateway7001_eth[0], ++ &gateway7001_eth[1], + }; + + static void __init gateway7001_init(void) +--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c ++++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c +@@ -76,9 +76,26 @@ static struct platform_device wg302v2_ua + .resource = &wg302v2_uart_resource, + }; + ++static struct eth_plat_info wg302v2_plat_eth[] = { ++ { ++ .phy = 8, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device wg302v2_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wg302v2_plat_eth, ++ } ++}; ++ + static struct platform_device *wg302v2_devices[] __initdata = { + &wg302v2_flash, + &wg302v2_uart, ++ &wg302v2_eth[0], + }; + + static void __init wg302v2_init(void) diff --git a/target/linux/ixp4xx/patches-3.18/105-wg302v1_support.patch b/target/linux/ixp4xx/patches-3.18/105-wg302v1_support.patch new file mode 100644 index 0000000..8793549 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/105-wg302v1_support.patch @@ -0,0 +1,261 @@ +--- a/arch/arm/configs/ixp4xx_defconfig ++++ b/arch/arm/configs/ixp4xx_defconfig +@@ -13,6 +13,7 @@ CONFIG_MACH_AVILA=y + CONFIG_MACH_LOFT=y + CONFIG_ARCH_ADI_COYOTE=y + CONFIG_MACH_GATEWAY7001=y ++CONFIG_MACH_WG302V1=y + CONFIG_MACH_WG302V2=y + CONFIG_ARCH_IXDP425=y + CONFIG_MACH_IXDPG425=y +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -45,6 +45,14 @@ config MACH_GATEWAY7001 + 7001 Access Point. For more information on this platform, + see http://openwrt.org + ++config MACH_WG302V1 ++ bool "Netgear WG302 v1 / WAG302 v1" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Netgear's ++ WG302 v1 or WAG302 v1 Access Points. For more information ++ on this platform, see http://openwrt.org ++ + config MACH_WG302V2 + bool "Netgear WG302 v2 / WAG302 v2" + select PCI +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -15,6 +15,7 @@ obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-p + obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o + obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o + obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o ++obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o +@@ -33,6 +34,7 @@ obj-$(CONFIG_MACH_NSLU2) += nslu2-setup. + obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o + obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o + obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o ++obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o + obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o + obj-$(CONFIG_MACH_FSG) += fsg-setup.o + obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/wg302v1-pci.c +@@ -0,0 +1,63 @@ ++/* ++ * arch/arch/mach-ixp4xx/wg302v1-pci.c ++ * ++ * PCI setup routines for the Netgear WG302 v1 and WAG302 v1 ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Software, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init wg302v1_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init wg302v1_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO8; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else ++ return -1; ++} ++ ++struct hw_pci wg302v1_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = wg302v1_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = wg302v1_map_irq, ++}; ++ ++int __init wg302v1_pci_init(void) ++{ ++ if (machine_is_wg302v1()) ++ pci_common_init(&wg302v1_pci); ++ return 0; ++} ++ ++subsys_initcall(wg302v1_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c +@@ -0,0 +1,147 @@ ++/* ++ * arch/arm/mach-ixp4xx/wg302v1-setup.c ++ * ++ * Board setup for the Netgear WG302 v1 and WAG302 v1 ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data wg302v1_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource wg302v1_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device wg302v1_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &wg302v1_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &wg302v1_flash_resource, ++}; ++ ++static struct resource wg302v1_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct plat_serial8250_port wg302v1_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device wg302v1_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = wg302v1_uart_data, ++ }, ++ .num_resources = 2, ++ .resource = wg302v1_uart_resources, ++}; ++ ++static struct eth_plat_info wg302v1_plat_eth[] = { ++ { ++ .phy = 30, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device wg302v1_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wg302v1_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *wg302v1_devices[] __initdata = { ++ &wg302v1_flash, ++ &wg302v1_uart, ++ &wg302v1_eth[0], ++}; ++ ++static void __init wg302v1_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ wg302v1_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ wg302v1_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(wg302v1_devices, ARRAY_SIZE(wg302v1_devices)); ++} ++ ++#ifdef CONFIG_MACH_WG302V1 ++MACHINE_START(WG302V1, "Netgear WG302 v1 / WAG302 v1") ++ /* Maintainer: Imre Kaloz */ ++ .fixup = wg302v1_fixup, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = wg302v1_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-3.18/110-pronghorn_series_support.patch b/target/linux/ixp4xx/patches-3.18/110-pronghorn_series_support.patch new file mode 100644 index 0000000..d1fdfcb --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/110-pronghorn_series_support.patch @@ -0,0 +1,393 @@ +--- a/arch/arm/configs/ixp4xx_defconfig ++++ b/arch/arm/configs/ixp4xx_defconfig +@@ -15,6 +15,8 @@ CONFIG_ARCH_ADI_COYOTE=y + CONFIG_MACH_GATEWAY7001=y + CONFIG_MACH_WG302V1=y + CONFIG_MACH_WG302V2=y ++CONFIG_MACH_PRONGHORN=y ++CONFIG_MACH_PRONGHORNMETRO=y + CONFIG_ARCH_IXDP425=y + CONFIG_MACH_IXDPG425=y + CONFIG_MACH_IXDP465=y +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -61,6 +61,22 @@ config MACH_WG302V2 + WG302 v2 or WAG302 v2 Access Points. For more information + on this platform, see http://openwrt.org + ++config MACH_PRONGHORN ++ bool "ADI Pronghorn series" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the ADI ++ Engineering Pronghorn series. For more ++ information on this platform, see http://www.adiengineering.com ++ ++# ++# There're only minimal differences kernel-wise between the Pronghorn and ++# Pronghorn Metro boards - they use different chip selects to drive the ++# CF slot connected to the expansion bus, so we just enable them together. ++# ++config MACH_PRONGHORNMETRO ++ def_bool MACH_PRONGHORN ++ + config ARCH_IXDP425 + bool "IXDP425" + help +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -19,6 +19,7 @@ obj-pci-$(CONFIG_MACH_WG302V1) += wg302 + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o ++obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o + + obj-y += common.o + +@@ -39,6 +40,7 @@ obj-$(CONFIG_MACH_WG302V2) += wg302v2-se + obj-$(CONFIG_MACH_FSG) += fsg-setup.o + obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o + obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o ++obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -42,7 +42,8 @@ static __inline__ void __arch_decomp_set + */ + if (machine_is_adi_coyote() || machine_is_gtwx5715() || + machine_is_gateway7001() || machine_is_wg302v2() || +- machine_is_devixp() || machine_is_miccpt() || machine_is_mic256()) ++ machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || ++ machine_is_pronghorn() || machine_is_pronghorn_metro()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/pronghorn-pci.c +@@ -0,0 +1,69 @@ ++/* ++ * arch/arch/mach-ixp4xx/pronghorn-pci.c ++ * ++ * PCI setup routines for ADI Engineering Pronghorn series ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init pronghorn_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init pronghorn_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 13) ++ return IRQ_IXP4XX_GPIO4; ++ else if (slot == 14) ++ return IRQ_IXP4XX_GPIO6; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 16) ++ return IRQ_IXP4XX_GPIO1; ++ else ++ return -1; ++} ++ ++struct hw_pci pronghorn_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = pronghorn_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = pronghorn_map_irq, ++}; ++ ++int __init pronghorn_pci_init(void) ++{ ++ if (machine_is_pronghorn() || machine_is_pronghorn_metro()) ++ pci_common_init(&pronghorn_pci); ++ return 0; ++} ++ ++subsys_initcall(pronghorn_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c +@@ -0,0 +1,252 @@ ++/* ++ * arch/arm/mach-ixp4xx/pronghorn-setup.c ++ * ++ * Board setup for the ADI Engineering Pronghorn series ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data pronghorn_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource pronghorn_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device pronghorn_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &pronghorn_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &pronghorn_flash_resource, ++}; ++ ++static struct resource pronghorn_uart_resources [] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port pronghorn_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device pronghorn_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = pronghorn_uart_data, ++ }, ++ .num_resources = 2, ++ .resource = pronghorn_uart_resources, ++}; ++ ++static struct i2c_gpio_platform_data pronghorn_i2c_gpio_data = { ++ .sda_pin = 9, ++ .scl_pin = 10, ++}; ++ ++static struct platform_device pronghorn_i2c_gpio = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &pronghorn_i2c_gpio_data, ++ }, ++}; ++ ++static struct gpio_led pronghorn_led_pin[] = { ++ { ++ .name = "pronghorn:green:status", ++ .gpio = 7, ++ } ++}; ++ ++static struct gpio_led_platform_data pronghorn_led_data = { ++ .num_leds = 1, ++ .leds = pronghorn_led_pin, ++}; ++ ++static struct platform_device pronghorn_led = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &pronghorn_led_data, ++}; ++ ++static struct resource pronghorn_pata_resources[] = { ++ { ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "intrq", ++ .start = IRQ_IXP4XX_GPIO0, ++ .end = IRQ_IXP4XX_GPIO0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct ixp4xx_pata_data pronghorn_pata_data = { ++ .cs0_bits = 0xbfff0043, ++ .cs1_bits = 0xbfff0043, ++}; ++ ++static struct platform_device pronghorn_pata = { ++ .name = "pata_ixp4xx_cf", ++ .id = 0, ++ .dev.platform_data = &pronghorn_pata_data, ++ .num_resources = ARRAY_SIZE(pronghorn_pata_resources), ++ .resource = pronghorn_pata_resources, ++}; ++ ++static struct eth_plat_info pronghorn_plat_eth[] = { ++ { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device pronghorn_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = pronghorn_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = pronghorn_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *pronghorn_devices[] __initdata = { ++ &pronghorn_flash, ++ &pronghorn_uart, ++ &pronghorn_led, ++ &pronghorn_eth[0], ++ &pronghorn_eth[1], ++}; ++ ++static void __init pronghorn_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ pronghorn_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ pronghorn_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(pronghorn_devices, ARRAY_SIZE(pronghorn_devices)); ++ ++ if (machine_is_pronghorn()) { ++ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(2); ++ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(2); ++ ++ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(3); ++ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(3); ++ ++ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS2; ++ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS3; ++ } else { ++ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(3); ++ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(3); ++ ++ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(4); ++ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(4); ++ ++ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS3; ++ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS4; ++ ++ platform_device_register(&pronghorn_i2c_gpio); ++ } ++ ++ platform_device_register(&pronghorn_pata); ++} ++ ++MACHINE_START(PRONGHORN, "ADI Engineering Pronghorn") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = pronghorn_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++ ++MACHINE_START(PRONGHORNMETRO, "ADI Engineering Pronghorn Metro") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = pronghorn_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END diff --git a/target/linux/ixp4xx/patches-3.18/111-pronghorn_swap_uarts.patch b/target/linux/ixp4xx/patches-3.18/111-pronghorn_swap_uarts.patch new file mode 100644 index 0000000..ed9f7a7 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/111-pronghorn_swap_uarts.patch @@ -0,0 +1,44 @@ +--- a/arch/arm/mach-ixp4xx/pronghorn-setup.c ++++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c +@@ -52,31 +52,31 @@ static struct platform_device pronghorn_ + + static struct resource pronghorn_uart_resources [] = { + { +- .start = IXP4XX_UART1_BASE_PHYS, +- .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM + }, + { +- .start = IXP4XX_UART2_BASE_PHYS, +- .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM + } + }; + + static struct plat_serial8250_port pronghorn_uart_data[] = { + { +- .mapbase = IXP4XX_UART1_BASE_PHYS, +- .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, +- .irq = IRQ_IXP4XX_UART1, ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + { +- .mapbase = IXP4XX_UART2_BASE_PHYS, +- .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, +- .irq = IRQ_IXP4XX_UART2, ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, diff --git a/target/linux/ixp4xx/patches-3.18/115-sidewinder_support.patch b/target/linux/ixp4xx/patches-3.18/115-sidewinder_support.patch new file mode 100644 index 0000000..20adbb5 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/115-sidewinder_support.patch @@ -0,0 +1,286 @@ +From 95dac4a842a3c66f69f949b48f9075e16275f77b Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Jun 2013 15:48:47 +0200 +Subject: [PATCH 07/36] 115-sidewinder_support.patch + +--- + arch/arm/mach-ixp4xx/Kconfig | 10 +- + arch/arm/mach-ixp4xx/Makefile | 2 + + arch/arm/mach-ixp4xx/sidewinder-pci.c | 68 ++++++++++++++ + arch/arm/mach-ixp4xx/sidewinder-setup.c | 151 +++++++++++++++++++++++++++++++ + 4 files changed, 230 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/mach-ixp4xx/sidewinder-pci.c + create mode 100644 arch/arm/mach-ixp4xx/sidewinder-setup.c + +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -77,6 +77,14 @@ config MACH_PRONGHORN + config MACH_PRONGHORNMETRO + def_bool MACH_PRONGHORN + ++config MACH_SIDEWINDER ++ bool "ADI Sidewinder" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the ADI ++ Engineering Sidewinder board. For more information on this ++ platform, see http://www.adiengineering.com ++ + config ARCH_IXDP425 + bool "IXDP425" + help +@@ -173,7 +181,7 @@ config MACH_ARCOM_VULCAN + # + config CPU_IXP46X + bool +- depends on MACH_IXDP465 ++ depends on MACH_IXDP465 || MACH_SIDEWINDER + default y + + config CPU_IXP43X +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -20,6 +20,7 @@ obj-pci-$(CONFIG_MACH_WG302V2) += wg302 + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o + obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o ++obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o + + obj-y += common.o + +@@ -41,6 +42,7 @@ obj-$(CONFIG_MACH_FSG) += fsg-setup.o + obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o + obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o + obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o ++obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/sidewinder-pci.c +@@ -0,0 +1,67 @@ ++/* ++ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c ++ * ++ * PCI setup routines for ADI Engineering Sidewinder ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++void __init sidewinder_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init sidewinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else if (slot == 3) ++ return IRQ_IXP4XX_GPIO9; ++ else ++ return -1; ++} ++ ++struct hw_pci sidewinder_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = sidewinder_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = sidewinder_map_irq, ++}; ++ ++int __init sidewinder_pci_init(void) ++{ ++ if (machine_is_sidewinder()) ++ pci_common_init(&sidewinder_pci); ++ return 0; ++} ++ ++subsys_initcall(sidewinder_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/sidewinder-setup.c +@@ -0,0 +1,155 @@ ++/* ++ * arch/arm/mach-ixp4xx/sidewinder-setup.c ++ * ++ * Board setup for the ADI Engineering Sidewinder ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++static struct flash_platform_data sidewinder_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource sidewinder_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device sidewinder_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &sidewinder_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &sidewinder_flash_resource, ++}; ++ ++static struct resource sidewinder_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct plat_serial8250_port sidewinder_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device sidewinder_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = sidewinder_uart_data, ++ }, ++ .num_resources = ARRAY_SIZE(sidewinder_uart_resources), ++ .resource = sidewinder_uart_resources, ++}; ++ ++static struct eth_plat_info sidewinder_plat_eth[] = { ++ { ++ .phy = 5, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, ++ .rxq = 4, ++ .txreadyq = 21, ++ }, { ++ .phy = 31, ++ .rxq = 2, ++ .txreadyq = 19, ++ } ++}; ++ ++static struct platform_device sidewinder_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = sidewinder_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = sidewinder_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEA, ++ .dev.platform_data = sidewinder_plat_eth + 2, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *sidewinder_devices[] __initdata = { ++ &sidewinder_flash, ++ &sidewinder_uart, ++ &sidewinder_eth[0], ++ &sidewinder_eth[1], ++ &sidewinder_eth[2], ++}; ++ ++static void __init sidewinder_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ sidewinder_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ sidewinder_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_64M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(sidewinder_devices, ARRAY_SIZE(sidewinder_devices)); ++} ++ ++MACHINE_START(SIDEWINDER, "ADI Engineering Sidewinder") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = sidewinder_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END diff --git a/target/linux/ixp4xx/patches-3.18/116-sidewinder_fis_location.patch b/target/linux/ixp4xx/patches-3.18/116-sidewinder_fis_location.patch new file mode 100644 index 0000000..7d633f7 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/116-sidewinder_fis_location.patch @@ -0,0 +1,30 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -30,6 +30,8 @@ + #include + #include + ++#include ++ + struct fis_image_desc { + unsigned char name[16]; // Null terminated name + uint32_t flash_base; // Address within FLASH of image +@@ -47,7 +49,8 @@ struct fis_list { + struct fis_list *next; + }; + +-static int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK; ++int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK; ++ + module_param(directory, int, 0); + + static inline int redboot_checksum(struct fis_image_desc *img) +@@ -75,6 +78,8 @@ static int parse_redboot_partitions(stru + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif ++ if (machine_is_sidewinder()) ++ directory = -5; + + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; diff --git a/target/linux/ixp4xx/patches-3.18/120-compex_support.patch b/target/linux/ixp4xx/patches-3.18/120-compex_support.patch new file mode 100644 index 0000000..2abc159 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/120-compex_support.patch @@ -0,0 +1,199 @@ +From 24025a2dcf1248079dd3019fac6ed955252d277f Mon Sep 17 00:00:00 2001 +From: Imre Kaloz +Date: Mon, 14 Jul 2008 21:56:34 +0200 +Subject: [PATCH] Add support for the Compex WP18 / NP18A boards + +Signed-off-by: Imre Kaloz +--- + +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -85,6 +85,14 @@ config MACH_SIDEWINDER + Engineering Sidewinder board. For more information on this + platform, see http://www.adiengineering.com + ++config MACH_COMPEXWP18 ++ bool "Compex WP18 / NP18A" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Compex' ++ WP18 or NP18A boards. For more information on this ++ platform, see http://www.compex.com.sg/home/OEM/product_ap.htm ++ + config ARCH_IXDP425 + bool "IXDP425" + help +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -21,6 +21,7 @@ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o + obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o + obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o ++obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o + + obj-y += common.o + +@@ -43,6 +44,7 @@ obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_ + obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o + obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o + obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o ++obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/compex42x-setup.c +@@ -0,0 +1,141 @@ ++/* ++ * arch/arm/mach-ixp4xx/compex-setup.c ++ * ++ * Compex WP18 / NP18A board-setup ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++static struct flash_platform_data compex42x_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource compex42x_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device compex42x_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &compex42x_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &compex42x_flash_resource, ++}; ++ ++static struct resource compex42x_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port compex42x_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device compex42x_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = compex42x_uart_data, ++ .num_resources = 2, ++ .resource = compex42x_uart_resources, ++}; ++ ++static struct eth_plat_info compex42x_plat_eth[] = { ++ { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0xf0000, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 3, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device compex42x_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = compex42x_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = compex42x_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *compex42x_devices[] __initdata = { ++ &compex42x_flash, ++ &compex42x_uart, ++ &compex42x_eth[0], ++ &compex42x_eth[1], ++}; ++ ++static void __init compex42x_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ compex42x_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ compex42x_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ platform_add_devices(compex42x_devices, ARRAY_SIZE(compex42x_devices)); ++} ++ ++MACHINE_START(COMPEXWP18, "Compex WP18 / NP18A") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = compex42x_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END +--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c +@@ -69,7 +69,8 @@ struct hw_pci ixdp425_pci __initdata = { + int __init ixdp425_pci_init(void) + { + if (machine_is_ixdp425() || machine_is_ixcdp1100() || +- machine_is_ixdp465() || machine_is_kixrp435()) ++ machine_is_ixdp465() || machine_is_kixrp435() || ++ machine_is_compex42x()) + pci_common_init(&ixdp425_pci); + return 0; + } diff --git a/target/linux/ixp4xx/patches-3.18/130-wrt300nv2_support.patch b/target/linux/ixp4xx/patches-3.18/130-wrt300nv2_support.patch new file mode 100644 index 0000000..49359be --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/130-wrt300nv2_support.patch @@ -0,0 +1,227 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -93,6 +93,14 @@ config MACH_COMPEXWP18 + WP18 or NP18A boards. For more information on this + platform, see http://www.compex.com.sg/home/OEM/product_ap.htm + ++config MACH_WRT300NV2 ++ bool "Linksys WRT300N v2" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Linksys' ++ WRT300N v2 router. For more information on this ++ platform, see http://openwrt.org ++ + config ARCH_IXDP425 + bool "IXDP425" + help +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -22,6 +22,7 @@ obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += v + obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o + obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o + obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o ++obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + + obj-y += common.o + +@@ -45,6 +46,7 @@ obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulca + obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o + obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o + obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o ++obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -43,7 +43,8 @@ static __inline__ void __arch_decomp_set + if (machine_is_adi_coyote() || machine_is_gtwx5715() || + machine_is_gateway7001() || machine_is_wg302v2() || + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || +- machine_is_pronghorn() || machine_is_pronghorn_metro()) ++ machine_is_pronghorn() || machine_is_pronghorn_metro() || ++ machine_is_wrt300nv2()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/wrt300nv2-pci.c +@@ -0,0 +1,64 @@ ++/* ++ * arch/arch/mach-ixp4xx/wrt300nv2-pci.c ++ * ++ * PCI setup routines for Linksys WRT300N v2 ++ * ++ * Copyright (C) 2007 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++extern void ixp4xx_pci_preinit(void); ++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); ++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); ++ ++void __init wrt300nv2_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init wrt300nv2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO8; ++ else return -1; ++} ++ ++struct hw_pci wrt300nv2_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = wrt300nv2_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = wrt300nv2_map_irq, ++}; ++ ++int __init wrt300nv2_pci_init(void) ++{ ++ if (machine_is_wrt300nv2()) ++ pci_common_init(&wrt300nv2_pci); ++ return 0; ++} ++ ++subsys_initcall(wrt300nv2_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c +@@ -0,0 +1,110 @@ ++/* ++ * arch/arm/mach-ixp4xx/wrt300nv2-setup.c ++ * ++ * Board setup for the Linksys WRT300N v2 ++ * ++ * Copyright (C) 2007 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data wrt300nv2_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource wrt300nv2_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device wrt300nv2_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &wrt300nv2_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &wrt300nv2_flash_resource, ++}; ++ ++static struct resource wrt300nv2_uart_resource = { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port wrt300nv2_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device wrt300nv2_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = wrt300nv2_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &wrt300nv2_uart_resource, ++}; ++ ++static struct platform_device *wrt300nv2_devices[] __initdata = { ++ &wrt300nv2_flash, ++ &wrt300nv2_uart ++}; ++ ++static void __init wrt300nv2_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ wrt300nv2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices)); ++} ++ ++#ifdef CONFIG_MACH_WRT300NV2 ++MACHINE_START(WRT300NV2, "Linksys WRT300N v2") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = wrt300nv2_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-3.18/131-wrt300nv2_mac_plat_info.patch b/target/linux/ixp4xx/patches-3.18/131-wrt300nv2_mac_plat_info.patch new file mode 100644 index 0000000..5debbf1 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/131-wrt300nv2_mac_plat_info.patch @@ -0,0 +1,42 @@ +--- a/arch/arm/mach-ixp4xx/wrt300nv2-setup.c ++++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c +@@ -76,9 +76,38 @@ static struct platform_device wrt300nv2_ + .resource = &wrt300nv2_uart_resource, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info wrt300nv2_plat_eth[] = { ++ { ++ .phy = -1, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device wrt300nv2_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wrt300nv2_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = wrt300nv2_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ + static struct platform_device *wrt300nv2_devices[] __initdata = { + &wrt300nv2_flash, +- &wrt300nv2_uart ++ &wrt300nv2_uart, ++ &wrt300nv2_eth[0], ++ &wrt300nv2_eth[1], + }; + + static void __init wrt300nv2_init(void) diff --git a/target/linux/ixp4xx/patches-3.18/132-wrt300nv2_mac_fix.patch b/target/linux/ixp4xx/patches-3.18/132-wrt300nv2_mac_fix.patch new file mode 100644 index 0000000..99db267 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/132-wrt300nv2_mac_fix.patch @@ -0,0 +1,72 @@ +--- a/arch/arm/mach-ixp4xx/wrt300nv2-setup.c ++++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c +@@ -3,6 +3,7 @@ + * + * Board setup for the Linksys WRT300N v2 + * ++ * Copyright (C) 2010 Alexandros C. Couloumbis + * Copyright (C) 2007 Imre Kaloz + * + * based on coyote-setup.c: +@@ -18,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -79,7 +81,8 @@ static struct platform_device wrt300nv2_ + /* Built-in 10/100 Ethernet MAC interfaces */ + static struct eth_plat_info wrt300nv2_plat_eth[] = { + { +- .phy = -1, ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x0F0000, + .rxq = 3, + .txreadyq = 20, + }, { +@@ -112,6 +115,10 @@ static struct platform_device *wrt300nv2 + + static void __init wrt300nv2_init(void) + { ++ uint8_t __iomem *f; ++ int offset = 0; ++ int i; ++ + ixp4xx_sys_init(); + + wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); +@@ -121,6 +128,32 @@ static void __init wrt300nv2_init(void) + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; + + platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices)); ++ ++ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x60000); ++ ++ if (f) { ++ for (i = 0; i < 6; i++) { ++#ifdef __ARMEB__ ++ wrt300nv2_plat_eth[0].hwaddr[i] = readb(f + 0x5FFA0 + i); ++ if (i == 5) ++ offset = 1; ++ wrt300nv2_plat_eth[1].hwaddr[i] = (wrt300nv2_plat_eth[0].hwaddr[i] + offset); ++#else ++ wrt300nv2_plat_eth[0].hwaddr[i] = readb(f + 0x5FFA0 + (i^3)); ++ if (i == 5) ++ offset = 1; ++ wrt300nv2_plat_eth[1].hwaddr[i] = (wrt300nv2_plat_eth[0].hwaddr[i] + offset); ++#endif ++ } ++ iounmap(f); ++ } ++ ++ if (!(is_valid_ether_addr(wrt300nv2_plat_eth[0].hwaddr))) ++ random_ether_addr(wrt300nv2_plat_eth[0].hwaddr); ++ if (!(is_valid_ether_addr(wrt300nv2_plat_eth[1].hwaddr))) { ++ memcpy(wrt300nv2_plat_eth[1].hwaddr, wrt300nv2_plat_eth[0].hwaddr, ETH_ALEN); ++ wrt300nv2_plat_eth[1].hwaddr[5] = (wrt300nv2_plat_eth[0].hwaddr[5] + 1); ++ } + } + + #ifdef CONFIG_MACH_WRT300NV2 diff --git a/target/linux/ixp4xx/patches-3.18/150-lanready_ap1000_support.patch b/target/linux/ixp4xx/patches-3.18/150-lanready_ap1000_support.patch new file mode 100644 index 0000000..ad09efd --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/150-lanready_ap1000_support.patch @@ -0,0 +1,203 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -101,6 +101,14 @@ config MACH_WRT300NV2 + WRT300N v2 router. For more information on this + platform, see http://openwrt.org + ++config MACH_AP1000 ++ bool "Lanready AP-1000" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Lanready's ++ AP1000 board. For more information on this ++ platform, see http://openwrt.org ++ + config ARCH_IXDP425 + bool "IXDP425" + help +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -23,6 +23,7 @@ obj-pci-$(CONFIG_MACH_PRONGHORN) += pron + obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o + obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o ++obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o + + obj-y += common.o + +@@ -47,6 +48,7 @@ obj-$(CONFIG_MACH_PRONGHORN) += pronghor + obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o + obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o ++obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/ap1000-setup.c +@@ -0,0 +1,154 @@ ++/* ++ * arch/arm/mach-ixp4xx/ap1000-setup.c ++ * ++ * Lanready AP-1000 ++ * ++ * Copyright (C) 2007 Imre Kaloz ++ * ++ * based on ixdp425-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data ap1000_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource ap1000_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device ap1000_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &ap1000_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &ap1000_flash_resource, ++}; ++ ++static struct resource ap1000_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port ap1000_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device ap1000_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = ap1000_uart_data, ++ .num_resources = 2, ++ .resource = ap1000_uart_resources ++}; ++ ++static struct platform_device *ap1000_devices[] __initdata = { ++ &ap1000_flash, ++ &ap1000_uart ++}; ++ ++static char ap1000_mem_fixup[] __initdata = "mem=64M "; ++ ++static void __init ap1000_fixup(struct machine_desc *desc, ++ struct tag *tags, char **cmdline, struct meminfo *mi) ++ ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(ap1000_mem_fixup) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, ap1000_mem_fixup, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(ap1000_mem_fixup), p, ++ COMMAND_LINE_SIZE - strlen(ap1000_mem_fixup)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ ++static void __init ap1000_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ ap1000_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ ap1000_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ ++ platform_add_devices(ap1000_devices, ARRAY_SIZE(ap1000_devices)); ++} ++ ++#ifdef CONFIG_MACH_AP1000 ++MACHINE_START(AP1000, "Lanready AP-1000") ++ /* Maintainer: Imre Kaloz */ ++ .fixup = ap1000_fixup, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = ap1000_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif +--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c +@@ -70,7 +70,7 @@ int __init ixdp425_pci_init(void) + { + if (machine_is_ixdp425() || machine_is_ixcdp1100() || + machine_is_ixdp465() || machine_is_kixrp435() || +- machine_is_compex42x()) ++ machine_is_compex42x() || machine_is_ap1000()) + pci_common_init(&ixdp425_pci); + return 0; + } diff --git a/target/linux/ixp4xx/patches-3.18/151-lanready_ap1000_mac_plat_info.patch b/target/linux/ixp4xx/patches-3.18/151-lanready_ap1000_mac_plat_info.patch new file mode 100644 index 0000000..2079589 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/151-lanready_ap1000_mac_plat_info.patch @@ -0,0 +1,51 @@ +--- a/arch/arm/mach-ixp4xx/ap1000-setup.c ++++ b/arch/arm/mach-ixp4xx/ap1000-setup.c +@@ -91,15 +91,45 @@ static struct platform_device ap1000_uar + .resource = ap1000_uart_resources + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info ap1000_plat_eth[] = { ++ { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 5, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device ap1000_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = ap1000_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = ap1000_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ + static struct platform_device *ap1000_devices[] __initdata = { + &ap1000_flash, +- &ap1000_uart ++ &ap1000_uart, ++ &ap1000_eth[0], ++ &ap1000_eth[1], + }; + + static char ap1000_mem_fixup[] __initdata = "mem=64M "; + +-static void __init ap1000_fixup(struct machine_desc *desc, +- struct tag *tags, char **cmdline, struct meminfo *mi) ++static void __init ap1000_fixup(struct tag *tags, char **cmdline, ++ struct meminfo *mi) + + { + struct tag *t = tags; diff --git a/target/linux/ixp4xx/patches-3.18/160-delayed_uart_io.patch b/target/linux/ixp4xx/patches-3.18/160-delayed_uart_io.patch new file mode 100644 index 0000000..54dc905 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/160-delayed_uart_io.patch @@ -0,0 +1,121 @@ +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -416,6 +416,20 @@ static void mem_serial_out(struct uart_p + writeb(value, p->membase + offset); + } + ++static unsigned int memdelay_serial_in(struct uart_port *p, int offset) ++{ ++ struct uart_8250_port *up = (struct uart_8250_port *)p; ++ udelay(up->port.rw_delay); ++ return mem_serial_in(p, offset); ++} ++ ++static void memdelay_serial_out(struct uart_port *p, int offset, int value) ++{ ++ struct uart_8250_port *up = (struct uart_8250_port *)p; ++ udelay(up->port.rw_delay); ++ mem_serial_out(p, offset, value); ++} ++ + static void mem32_serial_out(struct uart_port *p, int offset, int value) + { + offset = offset << p->regshift; +@@ -466,6 +480,11 @@ static void set_io_from_upio(struct uart + p->serial_out = mem32_serial_out; + break; + ++ case UPIO_MEM_DELAY: ++ p->serial_in = memdelay_serial_in; ++ p->serial_out = memdelay_serial_out; ++ break; ++ + #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) + case UPIO_AU: + p->serial_in = au_serial_in; +@@ -491,6 +510,7 @@ serial_port_out_sync(struct uart_port *p + switch (p->iotype) { + case UPIO_MEM: + case UPIO_MEM32: ++ case UPIO_MEM_DELAY: + case UPIO_AU: + p->serial_out(p, offset, value); + p->serial_in(p, UART_LCR); /* safe, no side-effects */ +@@ -2655,6 +2675,7 @@ static int serial8250_request_std_resour + case UPIO_TSI: + case UPIO_MEM32: + case UPIO_MEM: ++ case UPIO_MEM_DELAY: + if (!port->mapbase) + break; + +@@ -2691,6 +2712,7 @@ static void serial8250_release_std_resou + case UPIO_TSI: + case UPIO_MEM32: + case UPIO_MEM: ++ case UPIO_MEM_DELAY: + if (!port->mapbase) + break; + +@@ -3424,6 +3446,7 @@ static int serial8250_probe(struct platf + uart.port.set_termios = p->set_termios; + uart.port.pm = p->pm; + uart.port.dev = &dev->dev; ++ uart.port.rw_delay = p->rw_delay; + uart.port.irqflags |= irqflag; + ret = serial8250_register_8250_port(&uart); + if (ret < 0) { +@@ -3580,6 +3603,7 @@ int serial8250_register_8250_port(struct + uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF; + uart->bugs = up->bugs; + uart->port.mapbase = up->port.mapbase; ++ uart->port.rw_delay = up->port.rw_delay; + uart->port.private_data = up->port.private_data; + uart->port.fifosize = up->port.fifosize; + uart->tx_loadsz = up->tx_loadsz; +--- a/drivers/tty/serial/serial_core.c ++++ b/drivers/tty/serial/serial_core.c +@@ -2090,6 +2090,7 @@ uart_report_port(struct uart_driver *drv + snprintf(address, sizeof(address), + "I/O 0x%lx offset 0x%x", port->iobase, port->hub6); + break; ++ case UPIO_MEM_DELAY: + case UPIO_MEM: + case UPIO_MEM32: + case UPIO_AU: +@@ -2736,6 +2737,7 @@ int uart_match_port(struct uart_port *po + case UPIO_HUB6: + return (port1->iobase == port2->iobase) && + (port1->hub6 == port2->hub6); ++ case UPIO_MEM_DELAY: + case UPIO_MEM: + case UPIO_MEM32: + case UPIO_AU: +--- a/include/linux/serial_8250.h ++++ b/include/linux/serial_8250.h +@@ -27,6 +27,7 @@ struct plat_serial8250_port { + void *private_data; + unsigned char regshift; /* register shift */ + unsigned char iotype; /* UPIO_* */ ++ unsigned int rw_delay; /* udelay for slower busses IXP4XX Expansion Bus */ + unsigned char hub6; + upf_t flags; /* UPF_* flags */ + unsigned int type; /* If UPF_FIXED_TYPE */ +--- a/include/linux/serial_core.h ++++ b/include/linux/serial_core.h +@@ -146,6 +146,7 @@ struct uart_port { + #define UPIO_MEM32 (3) + #define UPIO_AU (4) /* Au1x00 and RT288x type IO */ + #define UPIO_TSI (5) /* Tsi108/109 type IO */ ++#define UPIO_MEM_DELAY (6) + + unsigned int read_status_mask; /* driver specific */ + unsigned int ignore_status_mask; /* driver specific */ +@@ -202,6 +203,7 @@ struct uart_port { + int hw_stopped; /* sw-assisted CTS flow state */ + unsigned int mctrl; /* current modem ctrl settings */ + unsigned int timeout; /* character-based timeout */ ++ unsigned int rw_delay; /* udelay for slow busses, IXP4XX Expansion Bus */ + unsigned int type; /* port type */ + const struct uart_ops *ops; + unsigned int custom_divisor; diff --git a/target/linux/ixp4xx/patches-3.18/162-wg302v1_mem_fixup.patch b/target/linux/ixp4xx/patches-3.18/162-wg302v1_mem_fixup.patch new file mode 100644 index 0000000..75212bc --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/162-wg302v1_mem_fixup.patch @@ -0,0 +1,38 @@ +--- a/arch/arm/mach-ixp4xx/wg302v1-setup.c ++++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c +@@ -117,6 +117,35 @@ static struct platform_device *wg302v1_d + &wg302v1_eth[0], + }; + ++static char wg302v1_mem_fixup[] __initdata = " mem=32M"; ++ ++static void __init wg302v1_fixup(struct tag *tags, char **cmdline, ++ struct meminfo *mi) ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ size_t fixlen, cmdlen; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ fixlen = strlen(wg302v1_mem_fixup); ++ cmdlen = strlen(p); ++ if (fixlen + cmdlen >= COMMAND_LINE_SIZE) ++ return; ++ ++ /* append the fixup to the cmdline */ ++ memmove(p + cmdlen, wg302v1_mem_fixup, fixlen + 1); ++ ++ /* Adjust the size of the atag if there was one */ ++ if (t->hdr.size) ++ t->hdr.size += fixlen; ++} ++ + static void __init wg302v1_init(void) + { + ixp4xx_sys_init(); diff --git a/target/linux/ixp4xx/patches-3.18/170-ixdpg425_mac_plat_info.patch b/target/linux/ixp4xx/patches-3.18/170-ixdpg425_mac_plat_info.patch new file mode 100644 index 0000000..f7090cd --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/170-ixdpg425_mac_plat_info.patch @@ -0,0 +1,51 @@ +--- a/arch/arm/mach-ixp4xx/coyote-setup.c ++++ b/arch/arm/mach-ixp4xx/coyote-setup.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -81,9 +82,39 @@ static struct platform_device coyote_uar + .resource = &coyote_uart_resource, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info ixdpg425_plat_eth[] = { ++ { ++ .phy = 5, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 4, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device ixdpg425_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = ixdpg425_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = ixdpg425_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++ + static struct platform_device *coyote_devices[] __initdata = { + &coyote_flash, +- &coyote_uart ++ &coyote_uart, ++ &ixdpg425_eth[0], ++ &ixdpg425_eth[1], + }; + + static void __init coyote_init(void) diff --git a/target/linux/ixp4xx/patches-3.18/175-avila_hss_audio_support.patch b/target/linux/ixp4xx/patches-3.18/175-avila_hss_audio_support.patch new file mode 100644 index 0000000..92342bf --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/175-avila_hss_audio_support.patch @@ -0,0 +1,2090 @@ +--- a/sound/soc/Kconfig ++++ b/sound/soc/Kconfig +@@ -55,6 +55,7 @@ source "sound/soc/spear/Kconfig" + source "sound/soc/tegra/Kconfig" + source "sound/soc/txx9/Kconfig" + source "sound/soc/ux500/Kconfig" ++source "sound/soc/gw-avila/Kconfig" + + # Supported codecs + source "sound/soc/codecs/Kconfig" +--- a/sound/soc/Makefile ++++ b/sound/soc/Makefile +@@ -32,3 +32,4 @@ obj-$(CONFIG_SND_SOC) += spear/ + obj-$(CONFIG_SND_SOC) += tegra/ + obj-$(CONFIG_SND_SOC) += txx9/ + obj-$(CONFIG_SND_SOC) += ux500/ ++obj-$(CONFIG_SND_SOC) += gw-avila/ +--- /dev/null ++++ b/sound/soc/gw-avila/Kconfig +@@ -0,0 +1,17 @@ ++config SND_GW_AVILA_SOC_PCM ++ tristate ++ ++config SND_GW_AVILA_SOC_HSS ++ tristate ++ ++config SND_GW_AVILA_SOC ++ tristate "SoC Audio for the Gateworks AVILA Family" ++ depends on ARCH_IXP4XX && SND_SOC ++ select SND_GW_AVILA_SOC_PCM ++ select SND_GW_AVILA_SOC_HSS ++ select SND_SOC_TLV320AIC3X ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the Gateworks HSS interface. You will also need ++ to select the audio interfaces to support below. ++ +--- /dev/null ++++ b/sound/soc/gw-avila/Makefile +@@ -0,0 +1,8 @@ ++# Gateworks Avila HSS Platform Support ++snd-soc-gw-avila-objs := gw-avila.o ixp4xx_hss.o ++snd-soc-gw-avila-pcm-objs := gw-avila-pcm.o ++snd-soc-gw-avila-hss-objs := gw-avila-hss.o ++ ++obj-$(CONFIG_SND_GW_AVILA_SOC) += snd-soc-gw-avila.o ++obj-$(CONFIG_SND_GW_AVILA_SOC_PCM) += snd-soc-gw-avila-pcm.o ++obj-$(CONFIG_SND_GW_AVILA_SOC_HSS) += snd-soc-gw-avila-hss.o +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila-hss.c +@@ -0,0 +1,103 @@ ++/* ++ * gw-avila-hss.c -- HSS Audio Support for Gateworks Avila ++ * ++ * Author: Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "ixp4xx_hss.h" ++#include "gw-avila-hss.h" ++ ++#define gw_avila_hss_suspend NULL ++#define gw_avila_hss_resume NULL ++ ++struct snd_soc_dai_driver gw_avila_hss_dai = { ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | ++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | ++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | ++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | ++ SNDRV_PCM_RATE_KNOT), ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, }, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | ++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | ++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | ++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | ++ SNDRV_PCM_RATE_KNOT), ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, }, ++}; ++ ++static const struct snd_soc_component_driver gw_avila_hss_component = { ++ .name = "gw_avila_hss", ++}; ++ ++static int gw_avila_hss_probe(struct platform_device *pdev) ++{ ++ int port = (pdev->id < 2) ? 0 : 1; ++ int channel = (pdev->id % 2); ++ ++ hss_handle[pdev->id] = hss_init(port, channel); ++ if (!hss_handle[pdev->id]) { ++ return -ENODEV; ++ } ++ ++ return snd_soc_register_component(&pdev->dev, &gw_avila_hss_component, ++ &gw_avila_hss_dai, 1); ++} ++ ++static int gw_avila_hss_remove(struct platform_device *pdev) ++{ ++ snd_soc_unregister_component(&pdev->dev); ++ ++ return 0; ++} ++ ++static struct platform_driver gw_avila_hss_driver = { ++ .probe = gw_avila_hss_probe, ++ .remove = gw_avila_hss_remove, ++ .driver = { ++ .name = "gw_avila_hss", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init gw_avila_hss_init(void) ++{ ++ return platform_driver_register(&gw_avila_hss_driver); ++} ++module_init(gw_avila_hss_init); ++ ++static void __exit gw_avila_hss_exit(void) ++{ ++ platform_driver_unregister(&gw_avila_hss_driver); ++} ++module_exit(gw_avila_hss_exit); ++ ++MODULE_AUTHOR("Chris Lang"); ++MODULE_DESCRIPTION("HSS Audio Driver for Gateworks Avila"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila-hss.h +@@ -0,0 +1,12 @@ ++/* ++ * Author: Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _GW_AVILA_HSS_H ++#define _GW_AVILA_HSS_H ++ ++#endif +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila-pcm.c +@@ -0,0 +1,327 @@ ++/* ++ * ALSA PCM interface for the TI DAVINCI processor ++ * ++ * Author: Chris Lang, ++ * Copyright: (C) 2009 Gateworks Corporation ++ * ++ * Based On: davinci-evm.c, Author: Vladimir Barinov, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "gw-avila-pcm.h" ++#include "gw-avila-hss.h" ++#include "ixp4xx_hss.h" ++ ++#define GW_AVILA_PCM_DEBUG 0 ++#if GW_AVILA_PCM_DEBUG ++#define DPRINTK(x...) printk(KERN_DEBUG x) ++#else ++#define DPRINTK(x...) ++#endif ++ ++static struct snd_pcm_hardware gw_avila_pcm_hardware = { ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID), ++/* SNDRV_PCM_INFO_PAUSE),*/ ++ .formats = (SNDRV_PCM_FMTBIT_S16_LE), ++ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | ++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | ++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | ++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | ++ SNDRV_PCM_RATE_KNOT), ++ .rate_min = 8000, ++ .rate_max = 8000, ++ .channels_min = 2, ++ .channels_max = 2, ++ .buffer_bytes_max = 64 * 1024, // All of the lines below may need to be changed ++ .period_bytes_min = 128, ++ .period_bytes_max = 4 * 1024, ++ .periods_min = 16, ++ .periods_max = 32, ++ .fifo_size = 0, ++}; ++ ++struct gw_avila_runtime_data { ++ spinlock_t lock; ++ int period; /* current DMA period */ ++ int master_lch; /* Master DMA channel */ ++ int slave_lch; /* Slave DMA channel */ ++ struct gw_avila_pcm_dma_params *params; /* DMA params */ ++}; ++ ++static void gw_avila_dma_irq(void *data) ++{ ++ struct snd_pcm_substream *substream = data; ++ snd_pcm_period_elapsed(substream); ++} ++ ++static int gw_avila_pcm_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct hss_device *hdev = runtime->private_data; ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ hss_tx_start(hdev); ++ else ++ hss_rx_start(hdev); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ hss_tx_stop(hdev); ++ else ++ hss_rx_stop(hdev); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ return ret; ++} ++ ++static int gw_avila_pcm_prepare(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct hss_device *hdev = runtime->private_data; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ hss_set_tx_callback(hdev, gw_avila_dma_irq, substream); ++ hss_config_tx_dma(hdev, runtime->dma_area, runtime->buffer_size, runtime->period_size); ++ } else { ++ hss_set_rx_callback(hdev, gw_avila_dma_irq, substream); ++ hss_config_rx_dma(hdev, runtime->dma_area, runtime->buffer_size, runtime->period_size); ++ } ++ ++ return 0; ++} ++ ++static snd_pcm_uframes_t ++gw_avila_pcm_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct hss_device *hdev = runtime->private_data; ++ ++ unsigned int curr = 0; ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ curr = hss_curr_offset_tx(hdev); ++ else ++ curr = hss_curr_offset_rx(hdev); ++ return curr; ++} ++ ++static int gw_avila_pcm_open(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ snd_soc_set_runtime_hwparams(substream, &gw_avila_pcm_hardware); ++ ++ if (hss_handle[cpu_dai->id] != NULL) ++ runtime->private_data = hss_handle[cpu_dai->id]; ++ else { ++ pr_err("hss_handle is NULL\n"); ++ return -1; ++ } ++ ++ hss_chan_open(hss_handle[cpu_dai->id]); ++ ++ return 0; ++} ++ ++static int gw_avila_pcm_close(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct hss_device *hdev = runtime->private_data; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ memset(hdev->tx_buf, 0, runtime->buffer_size); ++ } else ++ memset(hdev->rx_buf, 0, runtime->buffer_size); ++ ++ hss_chan_close(hdev); ++ ++ return 0; ++} ++ ++static int gw_avila_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *hw_params) ++{ ++ return snd_pcm_lib_malloc_pages(substream, ++ params_buffer_bytes(hw_params)); ++} ++ ++static int gw_avila_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ memset(runtime->dma_area, 0, runtime->buffer_size); ++ ++ return snd_pcm_lib_free_pages(substream); ++} ++ ++static int gw_avila_pcm_mmap(struct snd_pcm_substream *substream, ++ struct vm_area_struct *vma) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ ++ return dma_mmap_writecombine(substream->pcm->card->dev, vma, ++ runtime->dma_area, ++ runtime->dma_addr, ++ runtime->dma_bytes); ++} ++ ++struct snd_pcm_ops gw_avila_pcm_ops = { ++ .open = gw_avila_pcm_open, ++ .close = gw_avila_pcm_close, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = gw_avila_pcm_hw_params, ++ .hw_free = gw_avila_pcm_hw_free, ++ .prepare = gw_avila_pcm_prepare, ++ .trigger = gw_avila_pcm_trigger, ++ .pointer = gw_avila_pcm_pointer, ++ .mmap = gw_avila_pcm_mmap, ++}; ++ ++static int gw_avila_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) ++{ ++ struct snd_pcm_substream *substream = pcm->streams[stream].substream; ++ struct snd_dma_buffer *buf = &substream->dma_buffer; ++ size_t size = gw_avila_pcm_hardware.buffer_bytes_max; ++ ++ buf->dev.type = SNDRV_DMA_TYPE_DEV; ++ buf->dev.dev = pcm->card->dev; ++ buf->private_data = NULL; ++ ++ buf->area = dma_alloc_coherent(pcm->card->dev, size, ++ &buf->addr, GFP_KERNEL); ++ ++ if (!buf->area) { ++ return -ENOMEM; ++ } ++ ++ memset(buf->area, 0xff, size); ++ ++ DPRINTK("preallocate_dma_buffer: area=%p, addr=%p, size=%d\n", ++ (void *) buf->area, (void *) buf->addr, size); ++ ++ buf->bytes = size; ++ ++ return 0; ++} ++ ++static void gw_avila_pcm_free(struct snd_pcm *pcm) ++{ ++ struct snd_pcm_substream *substream; ++ struct snd_dma_buffer *buf; ++ int stream; ++ ++ for (stream = 0; stream < 2; stream++) { ++ substream = pcm->streams[stream].substream; ++ if (!substream) ++ continue; ++ ++ buf = &substream->dma_buffer; ++ if (!buf->area) ++ continue; ++ ++ dma_free_coherent(NULL, buf->bytes, buf->area, 0); ++ buf->area = NULL; ++ } ++} ++ ++static u64 gw_avila_pcm_dmamask = 0xFFFFFFFF; ++ ++static int gw_avila_pcm_new(struct snd_soc_pcm_runtime *rtd) ++{ ++ struct snd_card *card = rtd->card->snd_card; ++ struct snd_pcm *pcm = rtd->pcm; ++ struct snd_soc_dai *dai = rtd->codec_dai; ++ int ret; ++ ++ if (!card->dev->dma_mask) ++ card->dev->dma_mask = &gw_avila_pcm_dmamask; ++ if (!card->dev->coherent_dma_mask) ++ card->dev->coherent_dma_mask = 0xFFFFFFFF; ++ ++ if (dai->driver->playback.channels_min) { ++ ret = gw_avila_pcm_preallocate_dma_buffer(pcm, ++ SNDRV_PCM_STREAM_PLAYBACK); ++ if (ret) ++ return ret; ++ } ++ ++ if (dai->driver->capture.channels_min) { ++ ret = gw_avila_pcm_preallocate_dma_buffer(pcm, ++ SNDRV_PCM_STREAM_CAPTURE); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++struct snd_soc_platform_driver gw_avila_soc_platform = { ++ .ops = &gw_avila_pcm_ops, ++ .pcm_new = gw_avila_pcm_new, ++ .pcm_free = gw_avila_pcm_free, ++}; ++ ++static int gw_avila_pcm_platform_probe(struct platform_device *pdev) ++{ ++ return snd_soc_register_platform(&pdev->dev, &gw_avila_soc_platform); ++} ++ ++static int gw_avila_pcm_platform_remove(struct platform_device *pdev) ++{ ++ snd_soc_unregister_platform(&pdev->dev); ++ return 0; ++} ++ ++static struct platform_driver gw_avila_pcm_driver = { ++ .driver = { ++ .name = "gw_avila-audio", ++ .owner = THIS_MODULE, ++ }, ++ .probe = gw_avila_pcm_platform_probe, ++ .remove = gw_avila_pcm_platform_remove, ++}; ++ ++static int __init gw_avila_soc_platform_init(void) ++{ ++ return platform_driver_register(&gw_avila_pcm_driver); ++} ++module_init(gw_avila_soc_platform_init); ++ ++static void __exit gw_avila_soc_platform_exit(void) ++{ ++ platform_driver_unregister(&gw_avila_pcm_driver); ++} ++module_exit(gw_avila_soc_platform_exit); ++ ++MODULE_AUTHOR("Chris Lang"); ++MODULE_DESCRIPTION("Gateworks Avila PCM DMA module"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila-pcm.h +@@ -0,0 +1,32 @@ ++/* ++ * ALSA PCM interface for the Gateworks Avila platform ++ * ++ * Author: Chris Lang, ++ * Copyright: (C) 2009 Gateworks Corporation ++ * ++ * Based On: davinci-evm.c, Author: Vladimir Barinov, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _GW_AVILA_PCM_H ++#define _GW_AVILA_PCM_H ++ ++#if 0 ++struct gw_avila_pcm_dma_params { ++ char *name; /* stream identifier */ ++ int channel; /* sync dma channel ID */ ++ dma_addr_t dma_addr; /* device physical address for DMA */ ++ unsigned int data_type; /* xfer data type */ ++}; ++ ++struct gw_avila_snd_platform_data { ++ int tx_dma_ch; // XXX Do we need this? ++ int rx_dma_ch; // XXX Do we need this ++}; ++extern struct snd_soc_platform gw_avila_soc_platform[]; ++#endif ++ ++#endif +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila.c +@@ -0,0 +1,244 @@ ++/* ++ * File: sound/soc/gw-avila/gw_avila.c ++ * Author: Chris Lang ++ * ++ * Created: Tue June 06 2008 ++ * Description: Board driver for Gateworks Avila ++ * ++ * Modified: ++ * Copyright 2009 Gateworks Corporation ++ * ++ * Bugs: What Bugs? ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see the file COPYING, or write ++ * to the Free Software Foundation, Inc., ++ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ixp4xx_hss.h" ++#include "gw-avila-hss.h" ++#include "gw-avila-pcm.h" ++ ++#define CODEC_FREQ 33333000 ++ ++static int gw_avila_board_startup(struct snd_pcm_substream *substream) ++{ ++ pr_debug("%s enter\n", __func__); ++ return 0; ++} ++ ++static int gw_avila_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *codec_dai = rtd->codec_dai; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ int ret = 0; ++ ++ /* set codec DAI configuration */ ++ if (cpu_dai->id % 2) { ++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 1, 32); ++ } else { ++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM); ++ snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 0, 32); ++ } ++ ++ if (ret < 0) ++ return ret; ++ ++ /* set the codec system clock */ ++ ret = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_FREQ, SND_SOC_CLOCK_OUT); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { ++ SND_SOC_DAPM_HP("Headphone Jack", NULL), ++ SND_SOC_DAPM_LINE("Line Out", NULL), ++ SND_SOC_DAPM_LINE("Line In", NULL), ++}; ++ ++static const struct snd_soc_dapm_route audio_map[] = { ++ {"Headphone Jack", NULL, "HPLOUT"}, ++ {"Headphone Jack", NULL, "HPROUT"}, ++ ++ /* Line Out connected to LLOUT, RLOUT */ ++ {"Line Out", NULL, "LLOUT"}, ++ {"Line Out", NULL, "RLOUT"}, ++ ++ /* Line In connected to (LINE1L | LINE2L), (LINE1R | LINE2R) */ ++ {"LINE1L", NULL, "Line In"}, ++ {"LINE1R", NULL, "Line In"}, ++}; ++ ++/* Logic for a aic3x as connected on a davinci-evm */ ++static int avila_aic3x_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ struct snd_soc_codec *codec = rtd->codec; ++ struct snd_soc_dapm_context *dapm = &codec->dapm; ++ ++ /* Add davinci-evm specific widgets */ ++ snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, ++ ARRAY_SIZE(aic3x_dapm_widgets)); ++ ++ /* Set up davinci-evm specific audio path audio_map */ ++ snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); ++ ++ /* not connected */ ++ snd_soc_dapm_disable_pin(dapm, "MONO_LOUT"); ++ //snd_soc_dapm_disable_pin(dapm, "HPLCOM"); ++ //snd_soc_dapm_disable_pin(dapm, "HPRCOM"); ++ snd_soc_dapm_disable_pin(dapm, "MIC3L"); ++ snd_soc_dapm_disable_pin(dapm, "MIC3R"); ++ snd_soc_dapm_disable_pin(dapm, "LINE2L"); ++ snd_soc_dapm_disable_pin(dapm, "LINE2R"); ++ ++ /* always connected */ ++ snd_soc_dapm_enable_pin(dapm, "Headphone Jack"); ++ snd_soc_dapm_enable_pin(dapm, "Line Out"); ++ snd_soc_dapm_enable_pin(dapm, "Line In"); ++ ++ snd_soc_dapm_sync(dapm); ++ ++ return 0; ++} ++ ++static struct snd_soc_ops gw_avila_board_ops = { ++ .startup = gw_avila_board_startup, ++ .hw_params = gw_avila_hw_params, ++}; ++ ++static struct snd_soc_dai_link gw_avila_board_dai[] = { ++ { ++ .name = "HSS-0", ++ .stream_name = "HSS-0", ++ .cpu_dai_name = "gw_avila_hss.0", ++ .codec_dai_name = "tlv320aic3x-hifi", ++ .codec_name = "tlv320aic3x-codec.0-001b", ++ .platform_name = "gw_avila-audio.0", ++ .init = avila_aic3x_init, ++ .ops = &gw_avila_board_ops, ++ },{ ++ .name = "HSS-1", ++ .stream_name = "HSS-1", ++ .cpu_dai_name = "gw_avila_hss.1", ++ .codec_dai_name = "tlv320aic3x-hifi", ++ .codec_name = "tlv320aic3x-codec.0-001a", ++ .platform_name = "gw_avila-audio.1", ++ .init = avila_aic3x_init, ++ .ops = &gw_avila_board_ops, ++ },{ ++ .name = "HSS-2", ++ .stream_name = "HSS-2", ++ .cpu_dai_name = "gw_avila_hss.2", ++ .codec_dai_name = "tlv320aic3x-hifi", ++ .codec_name = "tlv320aic3x-codec.0-0019", ++ .platform_name = "gw_avila-audio.2", ++ .init = avila_aic3x_init, ++ .ops = &gw_avila_board_ops, ++ },{ ++ .name = "HSS-3", ++ .stream_name = "HSS-3", ++ .cpu_dai_name = "gw_avila_hss.3", ++ .codec_dai_name = "tlv320aic3x-hifi", ++ .codec_name = "tlv320aic3x-codec.0-0018", ++ .platform_name = "gw_avila-audio.3", ++ .init = avila_aic3x_init, ++ .ops = &gw_avila_board_ops, ++ }, ++}; ++ ++static struct snd_soc_card gw_avila_board[] = { ++ { ++ .name = "gw_avila-board.0", ++ .owner = THIS_MODULE, ++ .dai_link = &gw_avila_board_dai[0], ++ .num_links = 1, ++ },{ ++ .name = "gw_avila-board.1", ++ .owner = THIS_MODULE, ++ .dai_link = &gw_avila_board_dai[1], ++ .num_links = 1, ++ },{ ++ .name = "gw_avila-board.2", ++ .owner = THIS_MODULE, ++ .dai_link = &gw_avila_board_dai[2], ++ .num_links = 1, ++ },{ ++ .name = "gw_avila-board.3", ++ .owner = THIS_MODULE, ++ .dai_link = &gw_avila_board_dai[3], ++ .num_links = 1, ++ } ++}; ++ ++static struct platform_device *gw_avila_board_snd_device[4]; ++ ++static int __init gw_avila_board_init(void) ++{ ++ int ret; ++ struct port *port; ++ int i; ++ ++ if ((hss_port[0] = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL) ++ return -ENOMEM; ++ ++ if ((hss_port[1] = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL) ++ return -ENOMEM; ++ ++ for (i = 0; i < 4; i++) { ++ gw_avila_board_snd_device[i] = platform_device_alloc("soc-audio", i); ++ if (!gw_avila_board_snd_device[i]) { ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(gw_avila_board_snd_device[i], &gw_avila_board[i]); ++ ret = platform_device_add(gw_avila_board_snd_device[i]); ++ ++ if (ret) { ++ platform_device_put(gw_avila_board_snd_device[i]); ++ } ++ } ++ return ret; ++} ++ ++static void __exit gw_avila_board_exit(void) ++{ ++ int i; ++ for (i = 0; i < 4; i++) ++ platform_device_unregister(gw_avila_board_snd_device[i]); ++} ++ ++module_init(gw_avila_board_init); ++module_exit(gw_avila_board_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Chris Lang"); ++MODULE_DESCRIPTION("ALSA SoC HSS Audio gw_avila board"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/gw-avila/ixp4xx_hss.c +@@ -0,0 +1,902 @@ ++/* ++ * Intel IXP4xx HSS (synchronous serial port) driver for Linux ++ * ++ * Copyright (C) 2009 Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "ixp4xx_hss.h" ++ ++/***************************************************************************** ++ * global variables ++ ****************************************************************************/ ++ ++void hss_chan_read(unsigned long data); ++static char lock_init = 0; ++static spinlock_t npe_lock; ++static struct npe *npe; ++ ++static const struct { ++ int tx, txdone, rx, rxfree, chan; ++}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE, ++ HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE}, ++ {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE, ++ HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE}, ++}; ++ ++struct port *hss_port[2]; ++struct hss_device *hss_handle[32]; ++EXPORT_SYMBOL(hss_handle); ++ ++/***************************************************************************** ++ * utility functions ++ ****************************************************************************/ ++ ++#ifndef __ARMEB__ ++static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) ++{ ++ int i; ++ for (i = 0; i < cnt; i++) ++ dest[i] = swab32(src[i]); ++} ++#endif ++ ++static inline unsigned int sub_offset(unsigned int a, unsigned int b, ++ unsigned int modulo) ++{ ++ return (modulo /* make sure the result >= 0 */ + a - b) % modulo; ++} ++ ++/***************************************************************************** ++ * HSS access ++ ****************************************************************************/ ++ ++static void hss_config_load(struct port *port) ++{ ++ struct msg msg; ++ ++ do { ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_LOAD; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "HSS_LOAD_CONFIG")) ++ break; ++ if (npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG")) ++ break; ++ ++ /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ ++ if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) ++ break; ++ ++ /* HDLC may stop working without this */ ++ npe_recv_message(npe, &msg, "FLUSH_IT"); ++ return; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n", ++ port->id); ++ BUG(); ++} ++ ++static void hss_config_set_pcr(struct port *port) ++{ ++ struct msg msg; ++ ++ do { ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_TX_PCR; ++#if 0 ++ msg.data32 = PCR_FRM_SYNC_RISINGEDGE | PCR_MSB_ENDIAN | ++ PCR_TX_DATA_ENABLE | PCR_TX_UNASS_HIGH_IMP | PCR_TX_V56K_HIGH_IMP | PCR_TX_FB_HIGH_IMP; ++#else ++ msg.data32 = PCR_FRM_SYNC_RISINGEDGE | PCR_MSB_ENDIAN | ++ PCR_TX_DATA_ENABLE | PCR_TX_FB_HIGH_IMP | PCR_DCLK_EDGE_RISING; ++#endif ++ if (port->frame_size % 8 == 0) ++ msg.data32 |= PCR_SOF_NO_FBIT; ++ ++ if (npe_send_message(npe, &msg, "HSS_SET_TX_PCR")) ++ break; ++ ++ msg.index = HSS_CONFIG_RX_PCR; ++ msg.data32 &= ~ (PCR_DCLK_EDGE_RISING | PCR_FCLK_EDGE_RISING | PCR_TX_DATA_ENABLE); ++ ++ if (npe_send_message(npe, &msg, "HSS_SET_RX_PCR")) ++ break; ++ return; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id); ++ BUG(); ++} ++ ++static void hss_config_set_core(struct port *port) ++{ ++ struct msg msg; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_CORE_CR; ++#if 0 ++ msg.data32 = 0 | CCR_LOOPBACK | ++ (port->id ? CCR_SECOND_HSS : 0); ++#else ++ msg.data32 = 0 | ++ (port->id ? CCR_SECOND_HSS : 0); ++#endif ++ if (npe_send_message(npe, &msg, "HSS_SET_CORE_CR")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS core control" ++ " register\n", port->id); ++ BUG(); ++ } ++} ++ ++static void hss_config_set_line(struct port *port) ++{ ++ struct msg msg; ++ ++ hss_config_set_pcr(port); ++ hss_config_set_core(port); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_CLOCK_CR; ++ msg.data32 = CLK42X_SPEED_8192KHZ /* FIXME */; ++ if (npe_send_message(npe, &msg, "HSS_SET_CLOCK_CR")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS clock control" ++ " register\n", port->id); ++ BUG(); ++ } ++} ++ ++static void hss_config_set_rx_frame(struct port *port) ++{ ++ struct msg msg; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_RX_FCR; ++ msg.data16a = port->frame_sync_offset; ++ msg.data16b = port->frame_size - 1; ++ if (npe_send_message(npe, &msg, "HSS_SET_RX_FCR")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size" ++ " and offset\n", port->id); ++ BUG(); ++ } ++} ++ ++static void hss_config_set_frame(struct port *port) ++{ ++ struct msg msg; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_TX_FCR; ++ msg.data16a = TX_FRAME_SYNC_OFFSET; ++ msg.data16b = port->frame_size - 1; ++ if (npe_send_message(npe, &msg, "HSS_SET_TX_FCR")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size" ++ " and offset\n", port->id); ++ BUG(); ++ } ++ hss_config_set_rx_frame(port); ++} ++ ++static void hss_config_set_lut(struct port *port) ++{ ++ struct msg msg; ++ int chan_count = 32; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ ++ msg.index = HSS_CONFIG_TX_LUT; ++ msg.data32 = 0xffffffff; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.data32 = 0x0; ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ ++ msg.index = HSS_CONFIG_RX_LUT; ++ msg.data32 = 0xffffffff; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.data32 = 0x0; ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ ++ hss_config_set_frame(port); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_NUM_CHANS_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = chan_count; ++ if (npe_send_message(npe, &msg, "CHAN_NUM_CHANS_WRITE")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n", ++ port->id); ++ BUG(); ++ } ++} ++ ++static u32 hss_config_get_status(struct port *port) ++{ ++ struct msg msg; ++ ++ do { ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_ERROR_READ; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "PORT_ERROR_READ")) ++ break; ++ if (npe_recv_message(npe, &msg, "PORT_ERROR_READ")) ++ break; ++ ++ return msg.data32; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id); ++ BUG(); ++} ++ ++static void hss_config_start_chan(struct port *port) ++{ ++ struct msg msg; ++ ++ port->chan_last_tx = 0; ++ port->chan_last_rx = 0; ++ ++ do { ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_RX_BUF_ADDR_WRITE; ++ msg.hss_port = port->id; ++ msg.data32 = port->chan_rx_buf_phys; ++ if (npe_send_message(npe, &msg, "CHAN_RX_BUF_ADDR_WRITE")) ++ break; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_TX_BUF_ADDR_WRITE; ++ msg.hss_port = port->id; ++ msg.data32 = port->chan_tx_pointers_phys; ++ if (npe_send_message(npe, &msg, "CHAN_TX_BUF_ADDR_WRITE")) ++ break; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_FLOW_ENABLE; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "CHAN_FLOW_ENABLE")) ++ break; ++ port->chan_started = 1; ++ return; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n", ++ port->id); ++ BUG(); ++} ++ ++static void hss_config_stop_chan(struct port *port) ++{ ++ struct msg msg; ++ ++ if (!port->chan_started) ++ return; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_FLOW_DISABLE; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "CHAN_FLOW_DISABLE")) { ++ printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n", ++ port->id); ++ BUG(); ++ } ++ hss_config_get_status(port); /* make sure it's halted */ ++ port->chan_started = 0; ++} ++ ++static int hss_config_load_firmware(struct port *port) ++{ ++ struct msg msg; ++ ++ if (port->initialized) ++ return 0; ++ ++ if (!npe_running(npe)) { ++ int err; ++ if ((err = npe_load_firmware(npe, "NPE-A-HSS", ++ port->dev))) ++ return err; ++ } ++ ++ do { ++ /* HSS main configuration */ ++ hss_config_set_line(port); ++ ++ hss_config_set_frame(port); ++ ++ /* Channelized operation settings */ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_TX_BLK_CFG_WRITE; ++ msg.hss_port = port->id; ++ msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2; ++ msg.data8a = msg.data8b / 4; ++ msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b; ++ msg.data8c = msg.data8d / 4; ++ if (npe_send_message(npe, &msg, "CHAN_TX_BLK_CFG_WRITE")) ++ break; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_RX_BUF_CFG_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = CHAN_RX_TRIGGER / 8; ++ msg.data8b = CHAN_RX_FRAMES; ++ if (npe_send_message(npe, &msg, "CHAN_RX_BUF_CFG_WRITE")) ++ break; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_TX_BUF_SIZE_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = CHAN_TX_LISTS; ++ if (npe_send_message(npe, &msg, "CHAN_TX_BUF_SIZE_WRITE")) ++ break; ++ ++ port->initialized = 1; ++ return 0; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id); ++ BUG(); ++} ++ ++void hss_chan_irq(void *pdev) ++{ ++ struct port *port = pdev; ++ ++ qmgr_disable_irq(queue_ids[port->id].chan); ++ ++ tasklet_hi_schedule(&port->task); ++} ++ ++ ++int hss_prepare_chan(struct port *port) ++{ ++ int err, i, j; ++ u32 *temp; ++ u32 temp2; ++ u8 *temp3; ++ ++ if (port->initialized) ++ return 0; ++ ++ if ((err = hss_config_load_firmware(port))) ++ return err; ++ ++ if ((err = qmgr_request_queue(queue_ids[port->id].chan, ++ CHAN_QUEUE_LEN, 0, 0, "%s:hss", "hss"))) ++ return err; ++ ++ port->chan_tx_buf = dma_alloc_coherent(port->dev, chan_tx_buf_len(port), &port->chan_tx_buf_phys, GFP_DMA); ++ memset(port->chan_tx_buf, 0, chan_tx_buf_len(port)); ++ ++ port->chan_tx_pointers = dma_alloc_coherent(port->dev, chan_tx_buf_len(port) / CHAN_TX_LIST_FRAMES * 4, &port->chan_tx_pointers_phys, GFP_DMA); ++ ++ temp3 = port->chan_tx_buf; ++ for (i = 0; i < CHAN_TX_LISTS; i++) { ++ for (j = 0; j < 8; j++) { ++ port->tx_lists[i][j] = temp3; ++ temp3 += CHAN_TX_LIST_FRAMES * 4; ++ } ++ } ++ ++ temp = port->chan_tx_pointers; ++ temp2 = port->chan_tx_buf_phys; ++ for (i = 0; i < CHAN_TX_LISTS; i++) ++ { ++ for (j = 0; j < 32; j++) ++ { ++ *temp = temp2; ++ temp2 += CHAN_TX_LIST_FRAMES; ++ temp++; ++ } ++ } ++ ++ port->chan_rx_buf = dma_alloc_coherent(port->dev, chan_rx_buf_len(port), &port->chan_rx_buf_phys, GFP_DMA); ++ ++ for (i = 0; i < 8; i++) { ++ temp3 = port->chan_rx_buf + (i * 4 * 128); ++ for (j = 0; j < 8; j++) { ++ port->rx_frames[i][j] = temp3; ++ temp3 += CHAN_RX_TRIGGER; ++ } ++ } ++ ++ qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY, ++ hss_chan_irq, port); ++ ++ return 0; ++ ++} ++ ++int hss_tx_start(struct hss_device *hdev) ++{ ++ unsigned long flags; ++ struct port *port = hdev->port; ++ ++ hdev->tx_loc = 0; ++ hdev->tx_frame = 0; ++ ++ set_bit((1 << hdev->id), &port->chan_tx_bitmap); ++ ++ if (!port->chan_started) ++ { ++ qmgr_enable_irq(queue_ids[port->id].chan); ++ spin_lock_irqsave(&npe_lock, flags); ++ hss_config_start_chan(port); ++ spin_unlock_irqrestore(&npe_lock, flags); ++ hss_chan_irq(port); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_tx_start); ++ ++int hss_rx_start(struct hss_device *hdev) ++{ ++ unsigned long flags; ++ struct port *port = hdev->port; ++ ++ hdev->rx_loc = 0; ++ hdev->rx_frame = 0; ++ ++ set_bit((1 << hdev->id), &port->chan_rx_bitmap); ++ ++ if (!port->chan_started) ++ { ++ qmgr_enable_irq(queue_ids[port->id].chan); ++ spin_lock_irqsave(&npe_lock, flags); ++ hss_config_start_chan(port); ++ spin_unlock_irqrestore(&npe_lock, flags); ++ hss_chan_irq(port); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_rx_start); ++ ++int hss_tx_stop(struct hss_device *hdev) ++{ ++ struct port *port = hdev->port; ++ ++ clear_bit((1 << hdev->id), &port->chan_tx_bitmap); ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_tx_stop); ++ ++int hss_rx_stop(struct hss_device *hdev) ++{ ++ struct port *port = hdev->port; ++ ++ clear_bit((1 << hdev->id), &port->chan_rx_bitmap); ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_rx_stop); ++ ++int hss_chan_open(struct hss_device *hdev) ++{ ++ struct port *port = hdev->port; ++ int i, err = 0; ++ ++ if (port->chan_open) ++ return 0; ++ ++ if (port->mode == MODE_HDLC) { ++ err = -ENOSYS; ++ goto out; ++ } ++ ++ if (port->mode == MODE_G704 && port->channels[0] == hdev->id) { ++ err = -EBUSY; /* channel #0 is used for G.704 signaling */ ++ goto out; ++ } ++ ++ for (i = MAX_CHANNELS; i > port->frame_size / 8; i--) ++ if (port->channels[i - 1] == hdev->id) { ++ err = -ECHRNG; /* frame too short */ ++ goto out; ++ } ++ ++ hdev->rx_loc = hdev->tx_loc = 0; ++ hdev->rx_frame = hdev->tx_frame = 0; ++ ++ //clear_bit((1 << hdev->id), &port->chan_rx_bitmap); ++ //clear_bit((1 << hdev->id), &port->chan_tx_bitmap); ++ ++ if (!port->initialized) { ++ hss_prepare_chan(port); ++ ++ hss_config_stop_chan(port); ++ hdev->open_count++; ++ port->chan_open_count++; ++ ++ hss_config_set_lut(port); ++ hss_config_load(port); ++ ++ } ++ port->chan_open = 1; ++ ++out: ++ return err; ++} ++EXPORT_SYMBOL(hss_chan_open); ++ ++int hss_chan_close(struct hss_device *hdev) ++{ ++ return 0; ++} ++EXPORT_SYMBOL(hss_chan_close); ++ ++void hss_chan_read(unsigned long data) ++{ ++ struct port *port = (void *)data; ++ struct hss_device *hdev; ++ u8 *hw_buf, *save_buf; ++ u8 *buf; ++ u32 v; ++ unsigned int tx_list, rx_frame; ++ int i, j, channel; ++ u8 more_work = 0; ++ ++/* ++ My Data in the hardware buffer is scattered by channels into 4 trunks ++ as follows for rx ++ ++ channel 0 channel 1 channel 2 channel 3 ++Trunk 1 = 0 -> 127 128 -> 255 256 -> 383 384 -> 512 ++Trunk 2 = 513 -> 639 640 -> 768 769 -> 895 896 -> 1023 ++Trunk 3 = 1024 -> 1151 1152 -> 1207 1208 -> 1407 1408 -> 1535 ++Trunk 4 = 1535 -> 1663 1664 -> 1791 1792 -> 1920 1921 -> 2047 ++ ++ I will get CHAN_RX_TRIGGER worth of bytes out of each channel on each trunk ++ with each IRQ ++ ++ For TX Data, it is split into 8 lists with each list containing 16 bytes per ++ channel ++ ++Trunk 1 = 0 -> 16 17 -> 32 33 -> 48 49 -> 64 ++Trunk 2 = 65 -> 80 81 -> 96 97 -> 112 113 -> 128 ++Trunk 3 = 129 -> 144 145 -> 160 161 -> 176 177 -> 192 ++Trunk 4 = 193 -> 208 209 -> 224 225 -> 240 241 -> 256 ++ ++*/ ++ ++ ++ while ((v = qmgr_get_entry(queue_ids[port->id].chan))) ++ { ++ tx_list = (v >> 8) & 0xFF; ++ rx_frame = v & 0xFF; ++ ++ if (tx_list == 7) ++ tx_list = 0; ++ else ++ tx_list++; ++ for (channel = 0; channel < 8; channel++) { ++ ++ hdev = port->chan_devices[channel]; ++ if (!hdev) ++ continue; ++ ++ if (test_bit(1 << channel, &port->chan_tx_bitmap)) { ++ buf = (u8 *)hdev->tx_buf + hdev->tx_loc; ++#if 0 ++ hw_buf = (u8 *)port->chan_tx_buf; ++ hw_buf += (tx_list * CHAN_TX_LIST_FRAMES * 32); ++ hw_buf += (4 * CHAN_TX_LIST_FRAMES * channel); ++ save_buf = hw_buf; ++#else ++ save_buf = port->tx_lists[tx_list][channel]; ++#endif ++ for (i = 0; i < CHAN_TX_LIST_FRAMES; i++) { ++ hw_buf = save_buf + i; ++ for (j = 0; j < 4; j++) { ++ *hw_buf = *(buf++); ++ hw_buf += CHAN_TX_LIST_FRAMES; ++ } ++ ++ hdev->tx_loc += 4; ++ hdev->tx_frame++; ++ if (hdev->tx_loc >= hdev->tx_buffer_size) { ++ hdev->tx_loc = 0; ++ buf = (u8 *)hdev->tx_buf; ++ } ++ } ++ } else { ++#if 0 ++ hw_buf = (u8 *)port->chan_tx_buf; ++ hw_buf += (tx_list * CHAN_TX_LIST_FRAMES * 32); ++ hw_buf += (4 * CHAN_TX_LIST_FRAMES * channel); ++#else ++ hw_buf = port->tx_lists[tx_list][channel]; ++#endif ++ memset(hw_buf, 0, 64); ++ } ++ ++ if (hdev->tx_frame >= hdev->tx_period_size && test_bit(1 << channel, &port->chan_tx_bitmap)) ++ { ++ hdev->tx_frame %= hdev->tx_period_size; ++ if (hdev->tx_callback) ++ hdev->tx_callback(hdev->tx_data); ++ more_work = 1; ++ } ++ ++ if (test_bit(1 << channel, &port->chan_rx_bitmap)) { ++ buf = (u8 *)hdev->rx_buf + hdev->rx_loc; ++#if 0 ++ hw_buf = (u8 *)port->chan_rx_buf; ++ hw_buf += (4 * CHAN_RX_FRAMES * channel); ++ hw_buf += rx_frame; ++ save_buf = hw_buf; ++#else ++ save_buf = port->rx_frames[channel][rx_frame >> 4]; ++#endif ++ for (i = 0; i < CHAN_RX_TRIGGER; i++) { ++ hw_buf = save_buf + i; ++ for (j = 0; j < 4; j++) { ++ *(buf++) = *hw_buf; ++ hw_buf += CHAN_RX_FRAMES; ++ } ++ hdev->rx_loc += 4; ++ hdev->rx_frame++; ++ if (hdev->rx_loc >= hdev->rx_buffer_size) { ++ hdev->rx_loc = 0; ++ buf = (u8 *)hdev->rx_buf; ++ } ++ } ++ } ++ ++ if (hdev->rx_frame >= hdev->rx_period_size && test_bit(1 << channel, &port->chan_rx_bitmap)) ++ { ++ hdev->rx_frame %= hdev->rx_period_size; ++ if (hdev->rx_callback) ++ hdev->rx_callback(hdev->rx_data); ++ more_work = 1; ++ } ++ } ++#if 0 ++ if (more_work) ++ { ++ tasklet_hi_schedule(&port->task); ++ return; ++ } ++#endif ++ } ++ ++ qmgr_enable_irq(queue_ids[port->id].chan); ++ ++ return; ++ ++} ++ ++struct hss_device *hss_chan_create(struct port *port, unsigned int channel) ++{ ++ struct hss_device *chan_dev; ++ unsigned long flags; ++ ++ chan_dev = kzalloc(sizeof(struct hss_device), GFP_KERNEL); ++ ++ spin_lock_irqsave(&npe_lock, flags); ++ ++ chan_dev->id = channel; ++ chan_dev->port = port; ++ ++ port->channels[channel] = channel; ++ ++ port->chan_devices[channel] = chan_dev; ++ ++ spin_unlock_irqrestore(&npe_lock, flags); ++ ++ return chan_dev; ++} ++ ++/***************************************************************************** ++ * initialization ++ ****************************************************************************/ ++ ++static struct platform_device gw_avila_hss_device_0 = { ++ .name = "ixp4xx_hss", ++ .id = 0, ++}; ++ ++static struct platform_device gw_avila_hss_device_1 = { ++ .name = "ixp4xx_hss", ++ .id = 1, ++}; ++ ++static struct platform_device *gw_avila_hss_port_0; ++static struct platform_device *gw_avila_hss_port_1; ++static u64 hss_dmamask = 0xFFFFFFFF; ++ ++struct hss_device *hss_init(int id, int channel) ++{ ++ struct port *port = hss_port[id]; ++ struct hss_device *hdev; ++ int ret; ++ ++ if (!lock_init) ++ { ++ spin_lock_init(&npe_lock); ++ lock_init = 1; ++ npe = npe_request(0); ++ } ++ ++ if (!port->init) { ++ if (id == 0) { ++ gw_avila_hss_port_0 = platform_device_alloc("hss-port", 0); ++ ++ platform_set_drvdata(gw_avila_hss_port_0, &gw_avila_hss_device_0); ++ port->dev = &gw_avila_hss_port_0->dev; ++ ++ if (!port->dev->dma_mask) ++ port->dev->dma_mask = &hss_dmamask; ++ if (!port->dev->coherent_dma_mask) ++ port->dev->coherent_dma_mask = 0xFFFFFFFF; ++ ++ ret = platform_device_add(gw_avila_hss_port_0); ++ ++ if (ret) ++ platform_device_put(gw_avila_hss_port_0); ++ ++ tasklet_init(&port->task, hss_chan_read, (unsigned long) port); ++ } ++ else ++ { ++ gw_avila_hss_port_1 = platform_device_alloc("hss-port", 1); ++ ++ platform_set_drvdata(gw_avila_hss_port_1, &gw_avila_hss_device_1); ++ port->dev = &gw_avila_hss_port_1->dev; ++ ++ if (!port->dev->dma_mask) ++ port->dev->dma_mask = &hss_dmamask; ++ if (!port->dev->coherent_dma_mask) ++ port->dev->coherent_dma_mask = 0xFFFFFFFF; ++ ++ ret = platform_device_add(gw_avila_hss_port_1); ++ ++ if (ret) ++ platform_device_put(gw_avila_hss_port_1); ++ ++ tasklet_init(&port->task, hss_chan_read, (unsigned long) port); ++ } ++ ++ port->init = 1; ++ port->id = id; ++ port->clock_type = CLOCK_EXT; ++ port->clock_rate = 8192000; ++ port->frame_size = 256; /* E1 */ ++ port->mode = MODE_RAW; ++ port->next_rx_frame = 0; ++ memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels)); ++ } ++ ++ hdev = hss_chan_create(port, channel); ++ ++ return hdev; ++} ++EXPORT_SYMBOL(hss_init); ++ ++int hss_set_tx_callback(struct hss_device *hdev, void (*tx_callback)(void *), void *tx_data) ++{ ++ BUG_ON(tx_callback == NULL); ++ hdev->tx_callback = tx_callback; ++ hdev->tx_data = tx_data; ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_set_tx_callback); ++ ++int hss_set_rx_callback(struct hss_device *hdev, void (*rx_callback)(void *), void *rx_data) ++{ ++ BUG_ON(rx_callback == NULL); ++ hdev->rx_callback = rx_callback; ++ hdev->rx_data = rx_data; ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_set_rx_callback); ++ ++int hss_config_rx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size) ++{ ++ /* ++ * Period Size and Buffer Size are in Frames which are u32 ++ * We convert the u32 *buf to u8 in order to make channel reads ++ * and rx_loc easier ++ */ ++ ++ hdev->rx_buf = (u8 *)buf; ++ hdev->rx_buffer_size = buffer_size << 2; ++ hdev->rx_period_size = period_size; ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_config_rx_dma); ++ ++int hss_config_tx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size) ++{ ++ /* ++ * Period Size and Buffer Size are in Frames which are u32 ++ * We convert the u32 *buf to u8 in order to make channel reads ++ * and rx_loc easier ++ */ ++ ++ hdev->tx_buf = (u8 *)buf; ++ hdev->tx_buffer_size = buffer_size << 2; ++ hdev->tx_period_size = period_size; ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_config_tx_dma); ++ ++unsigned long hss_curr_offset_rx(struct hss_device *hdev) ++{ ++ return hdev->rx_loc >> 2; ++} ++EXPORT_SYMBOL(hss_curr_offset_rx); ++ ++unsigned long hss_curr_offset_tx(struct hss_device *hdev) ++{ ++ return hdev->tx_loc >> 2; ++} ++EXPORT_SYMBOL(hss_curr_offset_tx); ++ ++MODULE_AUTHOR("Chris Lang"); ++MODULE_DESCRIPTION("Intel IXP4xx HSS Audio driver"); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/sound/soc/gw-avila/ixp4xx_hss.h +@@ -0,0 +1,401 @@ ++/* ++ * ++ * ++ * Copyright (C) 2009 Gateworks Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include XXX We aren't HDLC ++ ++#define DEBUG_QUEUES 0 ++#define DEBUG_DESC 0 ++#define DEBUG_RX 0 ++#define DEBUG_TX 0 ++#define DEBUG_PKT_BYTES 0 ++#define DEBUG_CLOSE 0 ++#define DEBUG_FRAMER 0 ++ ++#define DRV_NAME "ixp4xx_hss" ++ ++#define PKT_EXTRA_FLAGS 0 /* orig 1 */ ++#define TX_FRAME_SYNC_OFFSET 0 /* channelized */ ++#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */ ++#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */ ++ ++#define RX_DESCS 512 /* also length of all RX queues */ ++#define TX_DESCS 512 /* also length of all TX queues */ ++ ++//#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) ++#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */ ++#define MAX_CLOSE_WAIT 1000 /* microseconds */ ++#define HSS_COUNT 2 ++#define MIN_FRAME_SIZE 16 /* bits */ ++#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */ ++#define MAX_CHANNELS (MAX_FRAME_SIZE / 8) ++#define MAX_CHAN_DEVICES 32 ++#define CHANNEL_HDLC 0xFE ++#define CHANNEL_UNUSED 0xFF ++ ++#define NAPI_WEIGHT 16 ++#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */ ++#define CHAN_RX_FRAMES 128 ++#define CHAN_RX_TRUNKS 1 ++#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3) ++ ++#define CHAN_TX_LIST_FRAMES CHAN_RX_TRIGGER /* bytes/channel per list, 16 - 48 */ ++#define CHAN_TX_LISTS 8 ++#define CHAN_TX_TRUNKS CHAN_RX_TRUNKS ++#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS) ++ ++#define CHAN_QUEUE_LEN 32 /* minimum possible */ ++ ++#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES * CHAN_RX_TRUNKS) ++#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES * CHAN_TX_TRUNKS) ++ ++/* Queue IDs */ ++#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */ ++#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */ ++#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */ ++#define HSS0_PKT_TX1_QUEUE 15 ++#define HSS0_PKT_TX2_QUEUE 16 ++#define HSS0_PKT_TX3_QUEUE 17 ++#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */ ++#define HSS0_PKT_RXFREE1_QUEUE 19 ++#define HSS0_PKT_RXFREE2_QUEUE 20 ++#define HSS0_PKT_RXFREE3_QUEUE 21 ++#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */ ++ ++#define HSS1_CHL_RXTRIG_QUEUE 10 ++#define HSS1_PKT_RX_QUEUE 0 ++#define HSS1_PKT_TX0_QUEUE 5 ++#define HSS1_PKT_TX1_QUEUE 6 ++#define HSS1_PKT_TX2_QUEUE 7 ++#define HSS1_PKT_TX3_QUEUE 8 ++#define HSS1_PKT_RXFREE0_QUEUE 1 ++#define HSS1_PKT_RXFREE1_QUEUE 2 ++#define HSS1_PKT_RXFREE2_QUEUE 3 ++#define HSS1_PKT_RXFREE3_QUEUE 4 ++#define HSS1_PKT_TXDONE_QUEUE 9 ++ ++#define NPE_PKT_MODE_HDLC 0 ++#define NPE_PKT_MODE_RAW 1 ++#define NPE_PKT_MODE_56KMODE 2 ++#define NPE_PKT_MODE_56KENDIAN_MSB 4 ++ ++/* PKT_PIPE_HDLC_CFG_WRITE flags */ ++#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */ ++#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ ++#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */ ++ ++ ++/* hss_config, PCRs */ ++/* Frame sync sampling, default = active low */ ++#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000 ++#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000 ++#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000 ++ ++/* Frame sync pin: input (default) or output generated off a given clk edge */ ++#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000 ++#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000 ++ ++/* Frame and data clock sampling on edge, default = falling */ ++#define PCR_FCLK_EDGE_RISING 0x08000000 ++#define PCR_DCLK_EDGE_RISING 0x04000000 ++ ++/* Clock direction, default = input */ ++#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000 ++ ++/* Generate/Receive frame pulses, default = enabled */ ++#define PCR_FRM_PULSE_DISABLED 0x01000000 ++ ++ /* Data rate is full (default) or half the configured clk speed */ ++#define PCR_HALF_CLK_RATE 0x00200000 ++ ++/* Invert data between NPE and HSS FIFOs? (default = no) */ ++#define PCR_DATA_POLARITY_INVERT 0x00100000 ++ ++/* TX/RX endianness, default = LSB */ ++#define PCR_MSB_ENDIAN 0x00080000 ++ ++/* Normal (default) / open drain mode (TX only) */ ++#define PCR_TX_PINS_OPEN_DRAIN 0x00040000 ++ ++/* No framing bit transmitted and expected on RX? (default = framing bit) */ ++#define PCR_SOF_NO_FBIT 0x00020000 ++ ++/* Drive data pins? */ ++#define PCR_TX_DATA_ENABLE 0x00010000 ++ ++/* Voice 56k type: drive the data pins low (default), high, high Z */ ++#define PCR_TX_V56K_HIGH 0x00002000 ++#define PCR_TX_V56K_HIGH_IMP 0x00004000 ++ ++/* Unassigned type: drive the data pins low (default), high, high Z */ ++#define PCR_TX_UNASS_HIGH 0x00000800 ++#define PCR_TX_UNASS_HIGH_IMP 0x00001000 ++ ++/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */ ++#define PCR_TX_FB_HIGH_IMP 0x00000400 ++ ++/* 56k data endiannes - which bit unused: high (default) or low */ ++#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200 ++ ++/* 56k data transmission type: 32/8 bit data (default) or 56K data */ ++#define PCR_TX_56KS_56K_DATA 0x00000100 ++ ++/* hss_config, cCR */ ++/* Number of packetized clients, default = 1 */ ++#define CCR_NPE_HFIFO_2_HDLC 0x04000000 ++#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000 ++ ++/* default = no loopback */ ++#define CCR_LOOPBACK 0x02000000 ++ ++/* HSS number, default = 0 (first) */ ++#define CCR_SECOND_HSS 0x01000000 ++ ++ ++/* hss_config, clkCR: main:10, num:10, denom:12 */ ++#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/ ++ ++#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15) ++#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47) ++#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192) ++#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63) ++#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127) ++#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255) ++ ++#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127) ++#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383) ++#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385) ++#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511) ++#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023) ++#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047) ++ ++ ++/* hss_config, LUT entries */ ++#define TDMMAP_UNASSIGNED 0 ++#define TDMMAP_HDLC 1 /* HDLC - packetized */ ++#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ ++#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */ ++ ++/* offsets into HSS config */ ++#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */ ++#define HSS_CONFIG_RX_PCR 0x04 ++#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */ ++#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */ ++#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */ ++#define HSS_CONFIG_RX_FCR 0x14 ++#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */ ++#define HSS_CONFIG_RX_LUT 0x38 ++ ++ ++/* NPE command codes */ ++/* writes the ConfigWord value to the location specified by offset */ ++#define PORT_CONFIG_WRITE 0x40 ++ ++/* triggers the NPE to load the contents of the configuration table */ ++#define PORT_CONFIG_LOAD 0x41 ++ ++/* triggers the NPE to return an HssErrorReadResponse message */ ++#define PORT_ERROR_READ 0x42 ++ ++/* reset NPE internal status and enable the HssChannelized operation */ ++#define CHAN_FLOW_ENABLE 0x43 ++#define CHAN_FLOW_DISABLE 0x44 ++#define CHAN_IDLE_PATTERN_WRITE 0x45 ++#define CHAN_NUM_CHANS_WRITE 0x46 ++#define CHAN_RX_BUF_ADDR_WRITE 0x47 ++#define CHAN_RX_BUF_CFG_WRITE 0x48 ++#define CHAN_TX_BLK_CFG_WRITE 0x49 ++#define CHAN_TX_BUF_ADDR_WRITE 0x4A ++#define CHAN_TX_BUF_SIZE_WRITE 0x4B ++#define CHAN_TSLOTSWITCH_ENABLE 0x4C ++#define CHAN_TSLOTSWITCH_DISABLE 0x4D ++ ++/* downloads the gainWord value for a timeslot switching channel associated ++ with bypassNum */ ++#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E ++ ++/* triggers the NPE to reset internal status and enable the HssPacketized ++ operation for the flow specified by pPipe */ ++#define PKT_PIPE_FLOW_ENABLE 0x50 ++#define PKT_PIPE_FLOW_DISABLE 0x51 ++#define PKT_NUM_PIPES_WRITE 0x52 ++#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53 ++#define PKT_PIPE_HDLC_CFG_WRITE 0x54 ++#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55 ++#define PKT_PIPE_RX_SIZE_WRITE 0x56 ++#define PKT_PIPE_MODE_WRITE 0x57 ++ ++/* HDLC packet status values - desc->status */ ++#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */ ++#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ ++#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ ++#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving ++ this packet (if buf_len < pkt_len) */ ++#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */ ++#define ERR_HDLC_ABORT 6 /* abort sequence received */ ++#define ERR_DISCONNECTING 7 /* disconnect is in progress */ ++ ++#define CLOCK_EXT 0 ++#define CLOCK_INT 1 ++ ++enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704}; ++enum rx_tx_bit { ++ TX_BIT = 0, ++ RX_BIT = 1 ++}; ++enum chan_bit { ++ CHAN_0 = (1 << 0), ++ CHAN_1 = (1 << 1), ++ CHAN_2 = (1 << 2), ++ CHAN_3 = (1 << 3), ++ CHAN_4 = (1 << 4), ++ CHAN_5 = (1 << 5), ++ CHAN_6 = (1 << 6), ++ CHAN_7 = (1 << 7), ++ CHAN_8 = (1 << 8), ++ CHAN_9 = (1 << 9), ++ CHAN_10 = (1 << 10), ++ CHAN_11 = (1 << 11), ++ CHAN_12 = (1 << 12), ++ CHAN_13 = (1 << 13), ++ CHAN_14 = (1 << 14), ++ CHAN_15 = (1 << 15) ++}; ++ ++enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST }; ++ ++#ifdef __ARMEB__ ++typedef struct sk_buff buffer_t; ++#define free_buffer dev_kfree_skb ++#define free_buffer_irq dev_kfree_skb_irq ++#else ++typedef void buffer_t; ++#define free_buffer kfree ++#define free_buffer_irq kfree ++#endif ++ ++struct hss_device { ++ struct port *port; ++ unsigned int open_count, excl_open; ++ unsigned long tx_loc, rx_loc; /* bytes */ ++ unsigned long tx_frame, rx_frame; /* Frames */ ++ u8 id, chan_count; ++ u8 log_channels[MAX_CHANNELS]; ++ ++ u8 *rx_buf; ++ u8 *tx_buf; ++ ++ size_t rx_buffer_size; ++ size_t rx_period_size; ++ size_t tx_buffer_size; ++ size_t tx_period_size; ++ ++ void (*rx_callback)(void *data); ++ void *rx_data; ++ void (*tx_callback)(void *data); ++ void *tx_data; ++ void *private_data; ++}; ++ ++extern struct hss_device *hss_handle[32]; ++extern struct port *hss_port[2]; ++ ++struct port { ++ unsigned char init; ++ ++ struct device *dev; ++ ++ struct tasklet_struct task; ++ unsigned int id; ++ unsigned long chan_rx_bitmap; ++ unsigned long chan_tx_bitmap; ++ unsigned char chan_open; ++ ++ /* the following fields must be protected by npe_lock */ ++ enum mode mode; ++ unsigned int clock_type, clock_rate, loopback; ++ unsigned int frame_size, frame_sync_offset; ++ unsigned int next_rx_frame; ++ ++ struct hss_device *chan_devices[MAX_CHAN_DEVICES]; ++ u32 chan_tx_buf_phys, chan_rx_buf_phys; ++ u32 chan_tx_pointers_phys; ++ u32 *chan_tx_pointers; ++ u8 *chan_rx_buf; ++ u8 *chan_tx_buf; ++ u8 *tx_lists[CHAN_TX_LISTS][8]; ++ u8 *rx_frames[8][CHAN_TX_LISTS]; ++ unsigned int chan_open_count, hdlc_open; ++ unsigned int chan_started, initialized, just_set_offset; ++ unsigned int chan_last_rx, chan_last_tx; ++ ++ /* assigned channels, may be invalid with given frame length or mode */ ++ u8 channels[MAX_CHANNELS]; ++ int msg_count; ++}; ++ ++/* NPE message structure */ ++struct msg { ++#ifdef __ARMEB__ ++ u8 cmd, unused, hss_port, index; ++ union { ++ struct { u8 data8a, data8b, data8c, data8d; }; ++ struct { u16 data16a, data16b; }; ++ struct { u32 data32; }; ++ }; ++#else ++ u8 index, hss_port, unused, cmd; ++ union { ++ struct { u8 data8d, data8c, data8b, data8a; }; ++ struct { u16 data16b, data16a; }; ++ struct { u32 data32; }; ++ }; ++#endif ++}; ++ ++#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ ++ (n) * sizeof(struct desc)) ++#define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) ++ ++#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ ++ ((n) + RX_DESCS) * sizeof(struct desc)) ++#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) ++ ++int hss_prepare_chan(struct port *port); ++void hss_chan_stop(struct port *port); ++ ++struct hss_device *hss_init(int id, int channel); ++int hss_chan_open(struct hss_device *hdev); ++int hss_chan_close(struct hss_device *hdev); ++ ++int hss_set_tx_callback(struct hss_device *hdev, void (*tx_callback)(void *), void *tx_data); ++int hss_set_rx_callback(struct hss_device *hdev, void (*rx_callback)(void *), void *rx_data); ++int hss_tx_start(struct hss_device *hdev); ++int hss_tx_stop(struct hss_device *hdev); ++int hss_rx_start(struct hss_device *hdev); ++int hss_rx_stop(struct hss_device *hdev); ++ ++int hss_config_rx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size); ++int hss_config_tx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size); ++unsigned long hss_curr_offset_rx(struct hss_device *hdev); ++unsigned long hss_curr_offset_tx(struct hss_device *hdev); ++ diff --git a/target/linux/ixp4xx/patches-3.18/180-tw5334_support.patch b/target/linux/ixp4xx/patches-3.18/180-tw5334_support.patch new file mode 100644 index 0000000..b56fbb7 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/180-tw5334_support.patch @@ -0,0 +1,287 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -160,6 +160,14 @@ config ARCH_PRPMC1100 + PrPCM1100 Processor Mezanine Module. For more information on + this platform, see . + ++config MACH_TW5334 ++ bool "Titan Wireless TW-533-4" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the Titan ++ Wireless TW533-4. For more information on this platform, ++ see http://openwrt.org ++ + config MACH_NAS100D + bool + prompt "NAS100D" +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -24,6 +24,7 @@ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sid + obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o ++obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o + + obj-y += common.o + +@@ -49,6 +50,7 @@ obj-$(CONFIG_MACH_SIDEWINDER) += sidewin + obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o ++obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -44,7 +44,7 @@ static __inline__ void __arch_decomp_set + machine_is_gateway7001() || machine_is_wg302v2() || + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro() || +- machine_is_wrt300nv2()) ++ machine_is_wrt300nv2() || machine_is_tw5334()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/tw5334-pci.c +@@ -0,0 +1,68 @@ ++/* ++ * arch/arch/mach-ixp4xx/tw5334-pci.c ++ * ++ * PCI setup routines for the Titan Wireless TW-533-4 ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init tw5334_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO0, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init tw5334_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 12) ++ return IRQ_IXP4XX_GPIO6; ++ else if (slot == 13) ++ return IRQ_IXP4XX_GPIO2; ++ else if (slot == 14) ++ return IRQ_IXP4XX_GPIO1; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO0; ++ else return -1; ++} ++ ++struct hw_pci tw5334_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = tw5334_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = tw5334_map_irq, ++}; ++ ++int __init tw5334_pci_init(void) ++{ ++ if (machine_is_tw5334()) ++ pci_common_init(&tw5334_pci); ++ return 0; ++} ++ ++subsys_initcall(tw5334_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/tw5334-setup.c +@@ -0,0 +1,167 @@ ++/* ++ * arch/arm/mach-ixp4xx/tw5334-setup.c ++ * ++ * Board setup for the Titan Wireless TW-533-4 ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data tw5334_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource tw5334_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device tw5334_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &tw5334_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &tw5334_flash_resource, ++}; ++ ++static struct resource tw5334_uart_resource = { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port tw5334_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device tw5334_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = tw5334_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &tw5334_uart_resource, ++}; ++ ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info tw5334_plat_eth[] = { ++ { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device tw5334_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = tw5334_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = tw5334_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *tw5334_devices[] __initdata = { ++ &tw5334_flash, ++ &tw5334_uart, ++ &tw5334_eth[0], ++ &tw5334_eth[1], ++}; ++ ++static void __init tw5334_init(void) ++{ ++ uint8_t __iomem *f; ++ int i; ++ ++ ixp4xx_sys_init(); ++ ++ tw5334_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ tw5334_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(tw5334_devices, ARRAY_SIZE(tw5334_devices)); ++ ++ /* ++ * Map in a portion of the flash and read the MAC addresses. ++ * Since it is stored in BE in the flash itself, we need to ++ * byteswap it if we're in LE mode. ++ */ ++ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000); ++ if (f) { ++ for (i = 0; i < 6; i++) { ++#ifdef __ARMEB__ ++ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + i); ++ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + i); ++#else ++ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + (i^3)); ++ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + (i^3)); ++#endif ++ } ++ iounmap(f); ++ } ++ ++ printk(KERN_INFO "TW-533-4: Using MAC address %pM for port 0\n", ++ tw5334_plat_eth[0].hwaddr); ++ printk(KERN_INFO "TW-533-4: Using MAC address %pM for port 1\n", ++ tw5334_plat_eth[1].hwaddr); ++} ++ ++#ifdef CONFIG_MACH_TW5334 ++MACHINE_START(TW5334, "Titan Wireless TW-533-4") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = tw5334_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-3.18/185-mi424wr_support.patch b/target/linux/ixp4xx/patches-3.18/185-mi424wr_support.patch new file mode 100644 index 0000000..81713b3 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/185-mi424wr_support.patch @@ -0,0 +1,507 @@ +--- a/arch/arm/configs/ixp4xx_defconfig ++++ b/arch/arm/configs/ixp4xx_defconfig +@@ -26,6 +26,7 @@ CONFIG_MACH_NAS100D=y + CONFIG_MACH_DSMG600=y + CONFIG_MACH_FSG=y + CONFIG_MACH_GTWX5715=y ++CONFIG_MACH_MI424WR=y + CONFIG_IXP4XX_QMGR=y + CONFIG_IXP4XX_NPE=y + # CONFIG_ARM_THUMB is not set +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -258,6 +258,13 @@ config MACH_MIC256 + Say 'Y' here if you want your kernel to support the MIC256 + board from OMICRON electronics GmbH. + ++config MACH_MI424WR ++ bool "Actiontec MI424WR" ++ depends on ARCH_IXP4XX ++ select PCI ++ help ++ Add support for the Actiontec MI424-WR. ++ + comment "IXP4xx Options" + + config IXP4XX_INDIRECT_PCI +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixd + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o ++obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o + + obj-y += common.o + +@@ -51,6 +52,7 @@ obj-$(CONFIG_MACH_COMPEXWP18) += compex4 + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o + obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o ++obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/mi424wr-pci.c +@@ -0,0 +1,70 @@ ++/* ++ * arch/arm/mach-ixp4xx/mi424wr-pci.c ++ * ++ * Actiontec MI424WR board-level PCI initialization ++ * ++ * Copyright (C) 2008 Jose Vasconcellos ++ * ++ * Maintainer: Jose Vasconcellos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* PCI controller GPIO to IRQ pin mappings ++ * This information was obtained from Actiontec's GPL release. ++ * ++ * INTA INTB ++ * SLOT 13 8 6 ++ * SLOT 14 7 8 ++ * SLOT 15 6 7 ++ */ ++ ++void __init mi424wr_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init mi424wr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 13) ++ return IRQ_IXP4XX_GPIO8; ++ if (slot == 14) ++ return IRQ_IXP4XX_GPIO7; ++ if (slot == 15) ++ return IRQ_IXP4XX_GPIO6; ++ ++ return -1; ++} ++ ++struct hw_pci mi424wr_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = mi424wr_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = mi424wr_map_irq, ++}; ++ ++int __init mi424wr_pci_init(void) ++{ ++ if (machine_is_mi424wr()) ++ pci_common_init(&mi424wr_pci); ++ return 0; ++} ++ ++subsys_initcall(mi424wr_pci_init); ++ +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/mi424wr-setup.c +@@ -0,0 +1,387 @@ ++/* ++ * arch/arm/mach-ixp4xx/mi424wr-setup.c ++ * ++ * Actiontec MI424-WR board setup ++ * Copyright (c) 2008 Jose Vasconcellos ++ * ++ * Based on Gemtek GTWX5715 by ++ * Copyright (C) 2004 George T. Joseph ++ * Derived from Coyote ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * GPIO 2,3,4 and 9 are hard wired to the Micrel/Kendin KS8995M Switch ++ * and operate as an SPI type interface. The details of the interface ++ * are available on Kendin/Micrel's web site. ++ */ ++ ++#define MI424WR_KSSPI_SELECT 9 ++#define MI424WR_KSSPI_TXD 4 ++#define MI424WR_KSSPI_CLOCK 2 ++#define MI424WR_KSSPI_RXD 3 ++ ++/* ++ * The "reset" button is wired to GPIO 10. ++ * The GPIO is brought "low" when the button is pushed. ++ */ ++ ++#define MI424WR_BUTTON_GPIO 10 ++#define MI424WR_BUTTON_IRQ IRQ_IXP4XX_GPIO10 ++ ++#define MI424WR_MOCA_WAN_LED 11 ++ ++/* Latch on CS1 - taken from Actiontec's 2.4 source code ++ * ++ * default latch value ++ * 0 - power alarm led (red) 0 (off) ++ * 1 - power led (green) 0 (off) ++ * 2 - wireless led (green) 1 (off) ++ * 3 - no internet led (red) 0 (off) ++ * 4 - internet ok led (green) 0 (off) ++ * 5 - moca LAN 0 (off) ++ * 6 - WAN alarm led (red) 0 (off) ++ * 7 - PCI reset 1 (not reset) ++ * 8 - IP phone 1 led (green) 1 (off) ++ * 9 - IP phone 2 led (green) 1 (off) ++ * 10 - VOIP ready led (green) 1 (off) ++ * 11 - PSTN relay 1 control 0 (PSTN) ++ * 12 - PSTN relay 1 control 0 (PSTN) ++ * 13 - N/A ++ * 14 - N/A ++ * 15 - N/A ++ */ ++ ++#define MI424WR_LATCH_MASK 0x04 ++#define MI424WR_LATCH_DEFAULT 0x1f86 ++ ++#define MI424WR_LATCH_ALARM_LED 0x00 ++#define MI424WR_LATCH_POWER_LED 0x01 ++#define MI424WR_LATCH_WIRELESS_LED 0x02 ++#define MI424WR_LATCH_INET_DOWN_LED 0x03 ++#define MI424WR_LATCH_INET_OK_LED 0x04 ++#define MI424WR_LATCH_MOCA_LAN_LED 0x05 ++#define MI424WR_LATCH_WAN_ALARM_LED 0x06 ++#define MI424WR_LATCH_PCI_RESET 0x07 ++#define MI424WR_LATCH_PHONE1_LED 0x08 ++#define MI424WR_LATCH_PHONE2_LED 0x09 ++#define MI424WR_LATCH_VOIP_LED 0x10 ++#define MI424WR_LATCH_PSTN_RELAY1 0x11 ++#define MI424WR_LATCH_PSTN_RELAY2 0x12 ++ ++/* initialize CS1 to default timings, Intel style, 16-bit bus */ ++#define MI424WR_CS1_CONFIG 0x80000002 ++ ++/* Define both UARTs but they are not easily accessible. ++ */ ++ ++static struct resource mi424wr_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++ ++static struct plat_serial8250_port mi424wr_uart_platform_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device mi424wr_uart_device = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = mi424wr_uart_platform_data, ++ .num_resources = ARRAY_SIZE(mi424wr_uart_resources), ++ .resource = mi424wr_uart_resources, ++}; ++ ++static struct flash_platform_data mi424wr_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource mi424wr_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device mi424wr_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev.platform_data = &mi424wr_flash_data, ++ .num_resources = 1, ++ .resource = &mi424wr_flash_resource, ++}; ++ ++static int mi424wr_spi_boardinfo_setup(struct spi_board_info *bi, ++ struct spi_master *master, void *data) ++{ ++ ++ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias)); ++ ++ bi->max_speed_hz = 5000000 /* Hz */; ++ bi->bus_num = master->bus_num; ++ bi->mode = SPI_MODE_0; ++ ++ return 0; ++} ++ ++static struct spi_gpio_platform_data mi424wr_spi_bus_data = { ++ .pin_cs = MI424WR_KSSPI_SELECT, ++ .pin_clk = MI424WR_KSSPI_CLOCK, ++ .pin_miso = MI424WR_KSSPI_RXD, ++ .pin_mosi = MI424WR_KSSPI_TXD, ++ .cs_activelow = 1, ++ .no_spi_delay = 1, ++ .boardinfo_setup = mi424wr_spi_boardinfo_setup, ++}; ++ ++static struct gpio_led mi424wr_gpio_led[] = { ++ { ++ .name = "moca-wan", /* green led */ ++ .gpio = MI424WR_MOCA_WAN_LED, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_led_platform_data mi424wr_gpio_leds_data = { ++ .num_leds = 1, ++ .leds = mi424wr_gpio_led, ++}; ++ ++static struct platform_device mi424wr_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &mi424wr_gpio_leds_data, ++}; ++ ++static uint16_t latch_value = MI424WR_LATCH_DEFAULT; ++static uint16_t __iomem *iobase; ++ ++static void mi424wr_latch_set_led(u8 bit, enum led_brightness value) ++{ ++ ++ if (((MI424WR_LATCH_MASK >> bit) & 1) ^ (value == LED_OFF)) ++ latch_value &= ~(0x1 << bit); ++ else ++ latch_value |= (0x1 << bit); ++ ++ __raw_writew(latch_value, iobase); ++ ++} ++ ++static struct latch_led mi424wr_latch_led[] = { ++ { ++ .name = "power-alarm", ++ .bit = MI424WR_LATCH_ALARM_LED, ++ }, ++ { ++ .name = "power-ok", ++ .bit = MI424WR_LATCH_POWER_LED, ++ }, ++ { ++ .name = "wireless", /* green led */ ++ .bit = MI424WR_LATCH_WIRELESS_LED, ++ }, ++ { ++ .name = "inet-down", /* red led */ ++ .bit = MI424WR_LATCH_INET_DOWN_LED, ++ }, ++ { ++ .name = "inet-up", /* green led */ ++ .bit = MI424WR_LATCH_INET_OK_LED, ++ }, ++ { ++ .name = "moca-lan", /* green led */ ++ .bit = MI424WR_LATCH_MOCA_LAN_LED, ++ }, ++ { ++ .name = "wan-alarm", /* red led */ ++ .bit = MI424WR_LATCH_WAN_ALARM_LED, ++ } ++}; ++ ++static struct latch_led_platform_data mi424wr_latch_leds_data = { ++ .num_leds = ARRAY_SIZE(mi424wr_latch_led), ++ .mem = 0x51000000, ++ .leds = mi424wr_latch_led, ++ .set_led = mi424wr_latch_set_led, ++}; ++ ++static struct platform_device mi424wr_latch_leds = { ++ .name = "leds-latch", ++ .id = -1, ++ .dev.platform_data = &mi424wr_latch_leds_data, ++}; ++ ++static struct platform_device mi424wr_spi_bus = { ++ .name = "spi-gpio", ++ .id = 0, ++ .dev.platform_data = &mi424wr_spi_bus_data, ++}; ++ ++static struct eth_plat_info mi424wr_wan_data = { ++ .phy = 17, /* KS8721 */ ++ .rxq = 3, ++ .txreadyq = 20, ++}; ++ ++static struct eth_plat_info mi424wr_lan_data = { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */ ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct platform_device mi424wr_npe_devices[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = &mi424wr_lan_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = &mi424wr_wan_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct eth_plat_info mi424wr_wanD_data = { ++ .phy = 5, ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct eth_plat_info mi424wr_lanD_data = { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */ ++ .rxq = 3, ++ .txreadyq = 20, ++}; ++ ++static struct platform_device mi424wr_npeD_devices[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = &mi424wr_lanD_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = &mi424wr_wanD_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *mi424wr_devices[] __initdata = { ++ &mi424wr_uart_device, ++ &mi424wr_flash, ++ &mi424wr_gpio_leds, ++ &mi424wr_latch_leds, ++ &mi424wr_spi_bus, ++}; ++ ++static void __init mi424wr_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ mi424wr_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ mi424wr_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = MI424WR_CS1_CONFIG; ++ ++ /* configure button as input ++ */ ++ gpio_line_config(MI424WR_BUTTON_GPIO, IXP4XX_GPIO_IN); ++ ++ /* Initialize LEDs and enables PCI bus. ++ */ ++ iobase = ioremap_nocache(IXP4XX_EXP_BUS_BASE(1), 0x1000); ++ __raw_writew(latch_value, iobase); ++ ++ platform_add_devices(mi424wr_devices, ARRAY_SIZE(mi424wr_devices)); ++ ++ /* Need to figure out how to detect revD. ++ * Look for a revision argument sent by redboot. ++ */ ++#define revD 4 ++ if (system_rev == revD) { ++ platform_device_register(&mi424wr_npeD_devices[0]); ++ platform_device_register(&mi424wr_npeD_devices[1]); ++ } else { ++ platform_device_register(&mi424wr_npe_devices[0]); ++ platform_device_register(&mi424wr_npe_devices[1]); ++ } ++} ++ ++ ++MACHINE_START(MI424WR, "Actiontec MI424WR") ++ /* Maintainer: Jose Vasconcellos */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = mi424wr_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++ diff --git a/target/linux/ixp4xx/patches-3.18/190-cambria_support.patch b/target/linux/ixp4xx/patches-3.18/190-cambria_support.patch new file mode 100644 index 0000000..d6787f4 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/190-cambria_support.patch @@ -0,0 +1,1131 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -21,6 +21,14 @@ config MACH_AVILA + Avila Network Platform. For more information on this platform, + see . + ++config MACH_CAMBRIA ++ bool "Cambria" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the Gateworks ++ Cambria series. For more information on this platform, ++ see . ++ + config MACH_LOFT + bool "Loft" + depends on MACH_AVILA +@@ -218,7 +226,7 @@ config CPU_IXP46X + + config CPU_IXP43X + bool +- depends on MACH_KIXRP435 ++ depends on MACH_KIXRP435 || MACH_CAMBRIA + default y + + config MACH_GTWX5715 +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -7,6 +7,7 @@ obj-pci-n := + + obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o ++obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o + obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o + obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o + obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o +@@ -31,6 +32,7 @@ obj-y += common.o + + obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o + obj-$(CONFIG_MACH_AVILA) += avila-setup.o ++obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o + obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o + obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o + obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/cambria-pci.c +@@ -0,0 +1,78 @@ ++/* ++ * arch/arch/mach-ixp4xx/cambria-pci.c ++ * ++ * PCI setup routines for Gateworks Cambria series ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++extern void ixp4xx_pci_preinit(void); ++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); ++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); ++ ++void __init cambria_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init cambria_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else if (slot == 3) ++ return IRQ_IXP4XX_GPIO9; ++ else if (slot == 4) ++ return IRQ_IXP4XX_GPIO8; ++ else if (slot == 6) ++ return IRQ_IXP4XX_GPIO10; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO8; ++ ++ else return -1; ++} ++ ++struct hw_pci cambria_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = cambria_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = cambria_map_irq, ++}; ++ ++int __init cambria_pci_init(void) ++{ ++ if (machine_is_cambria()) ++ pci_common_init(&cambria_pci); ++ return 0; ++} ++ ++subsys_initcall(cambria_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/cambria-setup.c +@@ -0,0 +1,1003 @@ ++/* ++ * arch/arm/mach-ixp4xx/cambria-setup.c ++ * ++ * Board setup for the Gateworks Cambria series ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * Copyright (C) 2012 Gateworks Corporation ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ * Tim Harvey ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) ++ ++struct cambria_board_info { ++ unsigned char *model; ++ void (*setup)(void); ++}; ++ ++static struct cambria_board_info *cambria_info __initdata; ++ ++static struct flash_platform_data cambria_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource cambria_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device cambria_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &cambria_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &cambria_flash_resource, ++}; ++ ++static struct i2c_gpio_platform_data cambria_i2c_gpio_data = { ++ .sda_pin = 7, ++ .scl_pin = 6, ++}; ++ ++static struct platform_device cambria_i2c_gpio = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &cambria_i2c_gpio_data, ++ }, ++}; ++ ++#ifdef SFP_SERIALID ++static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpa_data = { ++ .sda_pin = 113, ++ .scl_pin = 112, ++ .sda_is_open_drain = 0, ++ .scl_is_open_drain = 0, ++}; ++ ++static struct platform_device cambria_i2c_gpio_sfpa = { ++ .name = "i2c-gpio", ++ .id = 1, ++ .dev = { ++ .platform_data = &cambria_i2c_gpio_sfpa_data, ++ }, ++}; ++ ++static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpb_data = { ++ .sda_pin = 115, ++ .scl_pin = 114, ++ .sda_is_open_drain = 0, ++ .scl_is_open_drain = 0, ++}; ++ ++static struct platform_device cambria_i2c_gpio_sfpb = { ++ .name = "i2c-gpio", ++ .id = 2, ++ .dev = { ++ .platform_data = &cambria_i2c_gpio_sfpb_data, ++ }, ++}; ++#endif // #ifdef SFP_SERIALID ++ ++static struct eth_plat_info cambria_npec_data = { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct eth_plat_info cambria_npea_data = { ++ .phy = 2, ++ .rxq = 2, ++ .txreadyq = 19, ++}; ++ ++static struct platform_device cambria_npec_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = &cambria_npec_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct platform_device cambria_npea_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEA, ++ .dev.platform_data = &cambria_npea_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct resource cambria_uart_resource = { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port cambria_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device cambria_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = cambria_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &cambria_uart_resource, ++}; ++ ++static struct resource cambria_optional_uart_resources[] = { ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x53000000, ++ .end = 0x53000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x53000000, ++ .end = 0x53000fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port cambria_optional_uart_data[] = { ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM_DELAY, ++ .regshift = 0, ++ .uartclk = 1843200, ++ .rw_delay = 10, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM_DELAY, ++ .regshift = 0, ++ .uartclk = 1843200, ++ .rw_delay = 10, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { }, ++}; ++ ++static struct platform_device cambria_optional_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM1, ++ .dev.platform_data = cambria_optional_uart_data, ++ .num_resources = 2, ++ .resource = cambria_optional_uart_resources, ++}; ++ ++static struct resource cambria_pata_resources[] = { ++ { ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "intrq", ++ .start = IRQ_IXP4XX_GPIO12, ++ .end = IRQ_IXP4XX_GPIO12, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct ixp4xx_pata_data cambria_pata_data = { ++ .cs0_bits = 0xbfff3c03, ++ .cs1_bits = 0xbfff3c03, ++}; ++ ++static struct platform_device cambria_pata = { ++ .name = "pata_ixp4xx_cf", ++ .id = 0, ++ .dev.platform_data = &cambria_pata_data, ++ .num_resources = ARRAY_SIZE(cambria_pata_resources), ++ .resource = cambria_pata_resources, ++}; ++ ++static struct gpio_led cambria_gpio_leds[] = { ++ { ++ .name = "user", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "user2", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "user3", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "user4", ++ .gpio = 0, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_led_platform_data cambria_gpio_leds_data = { ++ .num_leds = 1, ++ .leds = cambria_gpio_leds, ++}; ++ ++static struct platform_device cambria_gpio_leds_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &cambria_gpio_leds_data, ++}; ++ ++static struct resource cambria_gpio_resources[] = { ++ { ++ .name = "gpio", ++ .flags = 0, ++ }, ++}; ++ ++static struct gpio cambria_gpios_gw2350[] = { ++ // ARM GPIO ++#if 0 // configured from bootloader ++ { 0, GPIOF_IN, "ARM_DIO0" }, ++ { 1, GPIOF_IN, "ARM_DIO1" }, ++ { 2, GPIOF_IN, "ARM_DIO2" }, ++ { 3, GPIOF_IN, "ARM_DIO3" }, ++ { 4, GPIOF_IN, "ARM_DIO4" }, ++ { 5, GPIOF_IN, "ARM_DIO5" }, ++ { 12, GPIOF_OUT_INIT_HIGH, "WDOGEN#" }, ++#endif ++ { 8, GPIOF_IN, "ARM_DIO8" }, ++ { 9, GPIOF_IN, "ARM_DIO9" }, ++}; ++ ++static struct gpio cambria_gpios_gw2358[] = { ++ // ARM GPIO ++#if 0 // configured from bootloader ++ { 0, GPIOF_IN, "*VINLOW#" }, ++ { 2, GPIOF_IN, "*GPS_PPS" }, ++ { 3, GPIOF_IN, "*GPS_IRQ#" }, ++ { 4, GPIOF_IN, "*RS485_IRQ#" }, ++ { 5, GPIOF_IN, "*SER_EN#" }, ++ { 14, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" }, ++#endif ++}; ++ ++static struct gpio cambria_gpios_gw2359[] = { ++ // ARM GPIO ++#if 0 // configured from bootloader ++ { 0, GPIOF_IN, "*PCA_IRQ#" }, ++ { 1, GPIOF_IN, "ARM_DIO1" }, ++ { 2, GPIOF_IN, "ARM_DIO2" }, ++ { 3, GPIOF_IN, "ARM_DIO3" }, ++ { 4, GPIOF_IN, "ARM_DIO4" }, ++ { 5, GPIOF_IN, "ARM_DIO5" }, ++ { 8, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" }, ++#endif ++ { 11, GPIOF_OUT_INIT_HIGH, "*SER_EN" }, // console serial enable ++ { 12, GPIOF_IN, "*GSC_IRQ#" }, ++ { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"}, ++ // GSC GPIO ++#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) ++ {100, GPIOF_IN, "*USER_PB#" }, ++#endif ++ {103, GPIOF_OUT_INIT_HIGH, "*5V_EN" }, // 5V aux supply enable ++ {108, GPIOF_IN, "*SMUXDA0" }, ++ {109, GPIOF_IN, "*SMUXDA1" }, ++ {110, GPIOF_IN, "*SMUXDA2" }, ++ {111, GPIOF_IN, "*SMUXDB0" }, ++ {112, GPIOF_IN, "*SMUXDB1" }, ++ {113, GPIOF_IN, "*SMUXDB2" }, ++ // PCA GPIO ++ {118, GPIOF_IN, "*USIM2_DET#"}, // USIM2 Detect ++ {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCI, 0=FP) ++ {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCI, 0=FP) ++ {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect ++ {123, GPIOF_OUT_INIT_HIGH, "*COM1_DTR#" }, // J21/J10 ++ {124, GPIOF_IN, "*COM1_DSR#" }, // J21/J10 ++ {127, GPIOF_IN, "PCA_DIO0" }, ++ {128, GPIOF_IN, "PCA_DIO1" }, ++ {129, GPIOF_IN, "PCA_DIO2" }, ++ {130, GPIOF_IN, "PCA_DIO3" }, ++ {131, GPIOF_IN, "PCA_DIO4" }, ++}; ++ ++static struct gpio cambria_gpios_gw2360[] = { ++ // ARM GPIO ++ { 0, GPIOF_IN, "*PCA_IRQ#" }, ++ { 11, GPIOF_OUT_INIT_LOW, "*SER0_EN#" }, ++ { 12, GPIOF_IN, "*GSC_IRQ#" }, ++ { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"}, ++ // GSC GPIO ++#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) ++ {100, GPIOF_IN, "*USER_PB#" }, ++#endif ++ {108, GPIOF_OUT_INIT_LOW, "*ENET1_EN#" }, // ENET1 TX Enable ++ {109, GPIOF_IN, "*ENET1_PRES#" }, // ENET1 Detect (0=SFP present) ++ {110, GPIOF_OUT_INIT_LOW, "*ENET2_EN#" }, // ENET2 TX Enable ++ {111, GPIOF_IN, "*ENET2_PRES#"}, // ENET2 Detect (0=SFP present) ++ // PCA GPIO ++ {116, GPIOF_OUT_INIT_HIGH, "*USIM2_LOC"}, // USIM2 Select (1=Loc, 0=Rem) ++ {117, GPIOF_IN, "*USIM2_DET_LOC#" },// USIM2 Detect (Local Slot) ++ {118, GPIOF_IN, "*USIM2_DET_REM#" },// USIM2 Detect (Remote Slot) ++ {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCIe1, 0=J1) ++ {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCIe2, 0=J1) ++ {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect ++ {127, GPIOF_IN, "DIO0" }, ++ {128, GPIOF_IN, "DIO1" }, ++ {129, GPIOF_IN, "DIO2" }, ++ {130, GPIOF_IN, "DIO3" }, ++ {131, GPIOF_IN, "DIO4" }, ++}; ++ ++static struct latch_led cambria_latch_leds[] = { ++ { ++ .name = "ledA", /* green led */ ++ .bit = 0, ++ }, ++ { ++ .name = "ledB", /* green led */ ++ .bit = 1, ++ }, ++ { ++ .name = "ledC", /* green led */ ++ .bit = 2, ++ }, ++ { ++ .name = "ledD", /* green led */ ++ .bit = 3, ++ }, ++ { ++ .name = "ledE", /* green led */ ++ .bit = 4, ++ }, ++ { ++ .name = "ledF", /* green led */ ++ .bit = 5, ++ }, ++ { ++ .name = "ledG", /* green led */ ++ .bit = 6, ++ }, ++ { ++ .name = "ledH", /* green led */ ++ .bit = 7, ++ } ++}; ++ ++static struct latch_led_platform_data cambria_latch_leds_data = { ++ .num_leds = 8, ++ .leds = cambria_latch_leds, ++ .mem = 0x53F40000, ++}; ++ ++static struct platform_device cambria_latch_leds_device = { ++ .name = "leds-latch", ++ .id = -1, ++ .dev.platform_data = &cambria_latch_leds_data, ++}; ++ ++static struct resource cambria_usb0_resources[] = { ++ { ++ .start = 0xCD000000, ++ .end = 0xCD000300, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = 32, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource cambria_usb1_resources[] = { ++ { ++ .start = 0xCE000000, ++ .end = 0xCE000300, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = 33, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ehci_dma_mask = ~(u32)0; ++ ++static struct usb_ehci_pdata cambria_usb_pdata = { ++ .big_endian_desc = 1, ++ .big_endian_mmio = 1, ++ .has_tt = 1, ++ .caps_offset = 0x100, ++}; ++ ++static struct platform_device cambria_usb0_device = { ++ .name = "ehci-platform", ++ .id = 0, ++ .resource = cambria_usb0_resources, ++ .num_resources = ARRAY_SIZE(cambria_usb0_resources), ++ .dev = { ++ .dma_mask = &ehci_dma_mask, ++ .coherent_dma_mask = 0xffffffff, ++ .platform_data = &cambria_usb_pdata, ++ }, ++}; ++ ++static struct platform_device cambria_usb1_device = { ++ .name = "ehci-platform", ++ .id = 1, ++ .resource = cambria_usb1_resources, ++ .num_resources = ARRAY_SIZE(cambria_usb1_resources), ++ .dev = { ++ .dma_mask = &ehci_dma_mask, ++ .coherent_dma_mask = 0xffffffff, ++ .platform_data = &cambria_usb_pdata, ++ }, ++}; ++ ++static struct gw_i2c_pld_platform_data gw_i2c_pld_data0 = { ++ .gpio_base = 16, ++ .nr_gpio = 8, ++}; ++ ++static struct gw_i2c_pld_platform_data gw_i2c_pld_data1 = { ++ .gpio_base = 24, ++ .nr_gpio = 2, ++}; ++ ++ ++static struct gpio_keys_button cambria_gpio_buttons[] = { ++ { ++ .desc = "user", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = 6, ++ .gpio = 25, ++ } ++}; ++ ++static struct gpio_keys_platform_data cambria_gpio_buttons_data = { ++ .poll_interval = 500, ++ .nbuttons = 1, ++ .buttons = cambria_gpio_buttons, ++}; ++ ++static struct platform_device cambria_gpio_buttons_device = { ++ .name = "gpio-keys-polled", ++ .id = -1, ++ .dev.platform_data = &cambria_gpio_buttons_data, ++}; ++ ++static struct platform_device *cambria_devices[] __initdata = { ++ &cambria_i2c_gpio, ++ &cambria_flash, ++ &cambria_uart, ++}; ++ ++static int cambria_register_gpio(struct gpio *array, size_t num) ++{ ++ int i, err, ret; ++ ++ ret = 0; ++ for (i = 0; i < num; i++, array++) { ++ const char *label = array->label; ++ if (label[0] == '*') ++ label++; ++ err = gpio_request_one(array->gpio, array->flags, label); ++ if (err) ++ ret = err; ++ else { ++ err = gpio_export(array->gpio, array->label[0] != '*'); ++ } ++ } ++ return ret; ++} ++ ++static void __init cambria_gw23xx_setup(void) ++{ ++ cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\ ++ (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12); ++ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; ++ ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++} ++ ++static void __init cambria_gw2350_setup(void) ++{ ++ *IXP4XX_EXP_CS2 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ cambria_optional_uart_data[0].mapbase = 0x52FF0000; ++ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff); ++ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3; ++ ++ *IXP4XX_EXP_CS3 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); ++ cambria_optional_uart_data[1].mapbase = 0x53FF0000; ++ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff); ++ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4; ++ ++ cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\ ++ (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12); ++ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; ++ ++ platform_device_register(&cambria_optional_uart); ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++ ++ platform_device_register(&cambria_usb0_device); ++ platform_device_register(&cambria_usb1_device); ++ ++ platform_device_register(&cambria_gpio_leds_device); ++ ++ /* gpio config (/sys/class/gpio) */ ++ cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2350)); ++} ++ ++static void __init cambria_gw2358_setup(void) ++{ ++ *IXP4XX_EXP_CS3 = 0xBFFF3C43; // bit0 = 16bit vs 8bit bus ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ cambria_optional_uart_data[0].mapbase = 0x53FC0000; ++ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff); ++ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3; ++ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); ++ cambria_optional_uart_data[1].mapbase = 0x53F80000; ++ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff); ++ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4; ++ ++ cambria_gpio_resources[0].start = (1 << 14) | (1 << 16) | (1 << 17) | (1 << 18) |\ ++ (1 << 19) | (1 << 20) | (1 << 24) | (1 << 25); ++ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; ++ ++ platform_device_register(&cambria_optional_uart); ++ ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++ ++ platform_device_register(&cambria_usb0_device); ++ platform_device_register(&cambria_usb1_device); ++ ++ platform_device_register(&cambria_pata); ++ ++ cambria_gpio_leds[0].gpio = 24; ++ platform_device_register(&cambria_gpio_leds_device); ++ ++ platform_device_register(&cambria_latch_leds_device); ++ ++ platform_device_register(&cambria_gpio_buttons_device); ++ ++ /* gpio config (/sys/class/gpio) */ ++ cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2358)); ++} ++ ++static void __init cambria_gw2359_setup(void) ++{ ++#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE) ++ /* The mvswitch driver has some hard-coded values which could ++ * easily be turned into a platform resource if needed. For now they ++ * match our hardware configuration: ++ * MV_BASE 0x10 - phy base address ++ * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module) ++ * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1) ++ * ++ * The mvswitch driver registers a fixup which forces a driver match ++ * if phy_addr matches MV_BASE ++ * ++ * Two static defautl VLAN's are created: WAN port in 1, and all other ports ++ * in the other. ++ */ ++ cambria_npea_data.phy = 0x10; // mvswitch driver catches this ++#else ++ // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the genphy driver ++ cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++ // CPU NPE-C is in bridge bypass mode to Port4 PHY@0x14 ++ cambria_npec_data.phy = 0x14; ++#endif ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++ ++ platform_device_register(&cambria_usb0_device); ++ platform_device_register(&cambria_usb1_device); ++ ++ cambria_gpio_leds_data.num_leds = 3; ++ cambria_gpio_leds[0].name = "user1"; ++ cambria_gpio_leds[0].gpio = 125; // PNLLED1# ++ cambria_gpio_leds[1].gpio = 126; // PNLLED3# ++ cambria_gpio_leds[2].gpio = 119; // PNLLED4# ++ platform_device_register(&cambria_gpio_leds_device); ++ ++#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) ++ cambria_gpio_buttons[0].gpio = 100; ++ platform_device_register(&cambria_gpio_buttons_device); ++#endif ++ ++ /* gpio config (/sys/class/gpio) */ ++ cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2359)); ++} ++ ++static void __init cambria_gw2360_setup(void) ++{ ++ /* The GW2360 has 8 UARTs in addition to the 1 IXP4xxx UART. ++ * The chip-selects are expanded via a 3-to-8 decoder and CS2 ++ * and they are 8bit devices ++ */ ++ *IXP4XX_EXP_CS2 = 0xBFFF3C43; ++ cambria_optional_uart_data[0].mapbase = 0x52000000; ++ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff); ++ cambria_optional_uart_data[0].uartclk = 18432000; ++ cambria_optional_uart_data[0].iotype = UPIO_MEM; ++ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO2; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[1].mapbase = 0x52000008; ++ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x52000008, 0x0fff); ++ cambria_optional_uart_data[1].uartclk = 18432000; ++ cambria_optional_uart_data[1].iotype = UPIO_MEM; ++ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO3; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[2].mapbase = 0x52000010; ++ cambria_optional_uart_data[2].membase = (void __iomem *)ioremap(0x52000010, 0x0fff); ++ cambria_optional_uart_data[2].uartclk = 18432000; ++ cambria_optional_uart_data[2].iotype = UPIO_MEM; ++ cambria_optional_uart_data[2].irq = IRQ_IXP4XX_GPIO4; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[3].mapbase = 0x52000018; ++ cambria_optional_uart_data[3].membase = (void __iomem *)ioremap(0x52000018, 0x0fff); ++ cambria_optional_uart_data[3].uartclk = 18432000; ++ cambria_optional_uart_data[3].iotype = UPIO_MEM; ++ cambria_optional_uart_data[3].irq = IRQ_IXP4XX_GPIO5; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO5, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[4].mapbase = 0x52000020; ++ cambria_optional_uart_data[4].membase = (void __iomem *)ioremap(0x52000020, 0x0fff); ++ cambria_optional_uart_data[4].uartclk = 18432000; ++ cambria_optional_uart_data[4].iotype = UPIO_MEM; ++ cambria_optional_uart_data[4].irq = IRQ_IXP4XX_GPIO8; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[5].mapbase = 0x52000028; ++ cambria_optional_uart_data[5].membase = (void __iomem *)ioremap(0x52000028, 0x0fff); ++ cambria_optional_uart_data[5].uartclk = 18432000; ++ cambria_optional_uart_data[5].iotype = UPIO_MEM; ++ cambria_optional_uart_data[5].irq = IRQ_IXP4XX_GPIO9; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[6].mapbase = 0x52000030; ++ cambria_optional_uart_data[6].membase = (void __iomem *)ioremap(0x52000030, 0x0fff); ++ cambria_optional_uart_data[6].uartclk = 18432000; ++ cambria_optional_uart_data[6].iotype = UPIO_MEM; ++ cambria_optional_uart_data[6].irq = IRQ_IXP4XX_GPIO10; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart.num_resources = 7, ++ platform_device_register(&cambria_optional_uart); ++ ++#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE) ++ /* The mvswitch driver has some hard-coded values which could ++ * easily be turned into a platform resource if needed. For now they ++ * match our hardware configuration: ++ * MV_BASE 0x10 - phy base address ++ * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module) ++ * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1) ++ * ++ * The mvswitch driver registers a fixup which forces a driver match ++ * if phy_addr matches MV_BASE ++ * ++ * Two static defautl VLAN's are created: WAN port in 1, and all other ports ++ * in the other. ++ */ ++ cambria_npea_data.phy = 0x10; // mvswitch driver catches this ++#else ++ // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the generic PHY driver ++ cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++#endif ++ ++ // disable genphy autonegotiation on NPE-C PHY (eth1) as its 100BaseFX ++ //cambria_npec_data.noautoneg = 1; // disable autoneg ++ cambria_npec_data.speed_10 = 0; // 100mbps ++ cambria_npec_data.half_duplex = 0; // full-duplex ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++ ++ platform_device_register(&cambria_usb0_device); ++ platform_device_register(&cambria_usb1_device); ++ ++ cambria_gpio_leds_data.num_leds = 3; ++ cambria_gpio_leds[0].name = "user1"; ++ cambria_gpio_leds[0].gpio = 125; ++ cambria_gpio_leds[1].gpio = 126; ++ cambria_gpio_leds[2].gpio = 119; ++ platform_device_register(&cambria_gpio_leds_device); ++ ++#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) ++ cambria_gpio_buttons[0].gpio = 100; ++ platform_device_register(&cambria_gpio_buttons_device); ++#endif ++ ++#ifdef SFP_SERIALID ++ /* the SFP modules each have an i2c bus for serial ident via GSC GPIO ++ * To use these the i2c-gpio driver must be changed to use the _cansleep ++ * varients of gpio_get_value/gpio_set_value (I don't know why it doesn't ++ * use that anyway as it doesn't operate in an IRQ context). ++ * Additionally the i2c-gpio module must set the gpio to output-high prior ++ * to changing direction to an input to enable internal Pullups ++ */ ++ platform_device_register(&cambria_i2c_gpio_sfpa); ++ platform_device_register(&cambria_i2c_gpio_sfpb); ++#endif ++ ++ /* gpio config (/sys/class/gpio) */ ++ cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2360)); ++} ++ ++static struct cambria_board_info cambria_boards[] __initdata = { ++ { ++ .model = "GW2350", ++ .setup = cambria_gw2350_setup, ++ }, { ++ .model = "GW2351", ++ .setup = cambria_gw2350_setup, ++ }, { ++ .model = "GW2358", ++ .setup = cambria_gw2358_setup, ++ }, { ++ .model = "GW2359", ++ .setup = cambria_gw2359_setup, ++ }, { ++ .model = "GW2360", ++ .setup = cambria_gw2360_setup, ++ }, { ++ .model = "GW2371", ++ .setup = cambria_gw2358_setup, ++ } ++}; ++ ++static struct cambria_board_info * __init cambria_find_board_info(char *model) ++{ ++ int i; ++ model[6] = '\0'; ++ ++ for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) { ++ struct cambria_board_info *info = &cambria_boards[i]; ++ if (strcmp(info->model, model) == 0) ++ return info; ++ } ++ ++ return NULL; ++} ++ ++static struct memory_accessor *at24_mem_acc; ++ ++static void at24_setup(struct memory_accessor *mem_acc, void *context) ++{ ++ char mac_addr[ETH_ALEN]; ++ char model[7]; ++ ++ at24_mem_acc = mem_acc; ++ ++ /* Read MAC addresses */ ++ if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x0, 6) == 6) { ++ memcpy(&cambria_npec_data.hwaddr, mac_addr, ETH_ALEN); ++ } ++ if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x6, 6) == 6) { ++ memcpy(&cambria_npea_data.hwaddr, mac_addr, ETH_ALEN); ++ } ++ ++ /* Read the first 6 bytes of the model number */ ++ if (at24_mem_acc->read(at24_mem_acc, model, 0x20, 6) == 6) { ++ cambria_info = cambria_find_board_info(model); ++ } ++ ++} ++ ++static struct at24_platform_data cambria_eeprom_info = { ++ .byte_len = 1024, ++ .page_size = 16, ++ .flags = AT24_FLAG_READONLY, ++ .setup = at24_setup, ++}; ++ ++static struct pca953x_platform_data cambria_pca_data = { ++ .gpio_base = 100, ++ .irq_base = -1, ++}; ++ ++static struct pca953x_platform_data cambria_pca2_data = { ++ .gpio_base = 116, ++ .irq_base = -1, ++}; ++ ++static struct i2c_board_info __initdata cambria_i2c_board_info[] = { ++ { ++ I2C_BOARD_INFO("pca9555", 0x23), ++ .platform_data = &cambria_pca_data, ++ }, ++ { ++ I2C_BOARD_INFO("pca9555", 0x27), ++ .platform_data = &cambria_pca2_data, ++ }, ++ { ++ I2C_BOARD_INFO("ds1672", 0x68), ++ }, ++ { ++ I2C_BOARD_INFO("gsp", 0x29), ++ }, ++ { ++ I2C_BOARD_INFO("ad7418", 0x28), ++ }, ++ { ++ I2C_BOARD_INFO("24c08", 0x51), ++ .platform_data = &cambria_eeprom_info ++ }, ++ { ++ I2C_BOARD_INFO("gw_i2c_pld", 0x56), ++ .platform_data = &gw_i2c_pld_data0, ++ }, ++ { ++ I2C_BOARD_INFO("gw_i2c_pld", 0x57), ++ .platform_data = &gw_i2c_pld_data1, ++ }, ++}; ++ ++static void __init cambria_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; // make sure window is writable ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(ARRAY_AND_SIZE(cambria_devices)); ++ ++ cambria_pata_resources[0].start = 0x53e00000; ++ cambria_pata_resources[0].end = 0x53e3ffff; ++ ++ cambria_pata_resources[1].start = 0x53e40000; ++ cambria_pata_resources[1].end = 0x53e7ffff; ++ ++ cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3; ++ cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3; ++ ++ i2c_register_board_info(0, ARRAY_AND_SIZE(cambria_i2c_board_info)); ++} ++ ++static int __init cambria_model_setup(void) ++{ ++ if (!machine_is_cambria()) ++ return 0; ++ ++ if (cambria_info) { ++ printk(KERN_DEBUG "Running on Gateworks Cambria %s\n", ++ cambria_info->model); ++ cambria_info->setup(); ++ } else { ++ printk(KERN_INFO "Unknown/missing Cambria model number" ++ " -- defaults will be used\n"); ++ cambria_gw23xx_setup(); ++ } ++ ++ return 0; ++} ++late_initcall(cambria_model_setup); ++ ++MACHINE_START(CAMBRIA, "Gateworks Cambria series") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = cambria_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END diff --git a/target/linux/ixp4xx/patches-3.18/201-npe_driver_print_license_location.patch b/target/linux/ixp4xx/patches-3.18/201-npe_driver_print_license_location.patch new file mode 100644 index 0000000..f46b9c6 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/201-npe_driver_print_license_location.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c ++++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c +@@ -586,6 +586,8 @@ int npe_load_firmware(struct npe *npe, c + npe_reset(npe); + #endif + ++ print_npe(KERN_INFO, npe, "firmware's license can be found in /usr/share/doc/LICENSE.IPL\n"); ++ + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, + (image->id >> 8) & 0xFF, image->id & 0xFF); diff --git a/target/linux/ixp4xx/patches-3.18/203-npe_driver_mask_phy_features.patch b/target/linux/ixp4xx/patches-3.18/203-npe_driver_mask_phy_features.patch new file mode 100644 index 0000000..359873d --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/203-npe_driver_mask_phy_features.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -1474,6 +1474,10 @@ static int eth_init_one(struct platform_ + goto err_free_mem; + } + ++ /* mask with MAC supported features */ ++ port->phydev->supported &= PHY_BASIC_FEATURES; ++ port->phydev->advertising = port->phydev->supported; ++ + port->phydev->irq = PHY_POLL; + + if ((err = register_netdev(dev))) diff --git a/target/linux/ixp4xx/patches-3.18/205-npe_driver_separate_phy_functions.patch b/target/linux/ixp4xx/patches-3.18/205-npe_driver_separate_phy_functions.patch new file mode 100644 index 0000000..6d1eb7b --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/205-npe_driver_separate_phy_functions.patch @@ -0,0 +1,131 @@ +From e3eab80fb5d0a7d7fdb0f2f231b27161d5ec3804 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Jun 2013 15:52:53 +0200 +Subject: [PATCH 23/36] 205-npe_driver_separate_phy_functions.patch + +--- + drivers/net/ethernet/xscale/ixp4xx_eth.c | 70 ++++++++++++++++++++++-------- + 1 file changed, 51 insertions(+), 19 deletions(-) + +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -589,6 +589,51 @@ static void ixp4xx_adjust_link(struct ne + dev->name, port->speed, port->duplex ? "full" : "half"); + } + ++static int ixp4xx_phy_connect(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ struct eth_plat_info *plat = port->plat; ++ char phy_id[MII_BUS_ID_SIZE + 3]; ++ ++ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, ++ mdio_bus->id, plat->phy); ++ port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, ++ PHY_INTERFACE_MODE_MII); ++ if (IS_ERR(port->phydev)) { ++ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); ++ return PTR_ERR(port->phydev); ++ } ++ ++ /* mask with MAC supported features */ ++ port->phydev->supported &= PHY_BASIC_FEATURES; ++ port->phydev->advertising = port->phydev->supported; ++ ++ port->phydev->irq = PHY_POLL; ++ ++ return 0; ++} ++ ++static void ixp4xx_phy_disconnect(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ ++ phy_disconnect(port->phydev); ++} ++ ++static void ixp4xx_phy_start(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ ++ port->speed = 0; /* force "link up" message */ ++ phy_start(port->phydev); ++} ++ ++static void ixp4xx_phy_stop(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ ++ phy_stop(port->phydev); ++} + + static inline void debug_pkt(struct net_device *dev, const char *func, + u8 *data, int len) +@@ -1259,8 +1304,7 @@ static int eth_open(struct net_device *d + return err; + } + +- port->speed = 0; /* force "link up" message */ +- phy_start(port->phydev); ++ ixp4xx_phy_start(dev); + + for (i = 0; i < ETH_ALEN; i++) + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); +@@ -1381,7 +1425,7 @@ static int eth_close(struct net_device * + printk(KERN_CRIT "%s: unable to disable loopback\n", + dev->name); + +- phy_stop(port->phydev); ++ ixp4xx_phy_stop(dev); + + if (!ports_open) + qmgr_disable_irq(TXDONE_QUEUE); +@@ -1407,7 +1451,6 @@ static int eth_init_one(struct platform_ + struct net_device *dev; + struct eth_plat_info *plat = dev_get_platdata(&pdev->dev); + u32 regs_phys; +- char phy_id[MII_BUS_ID_SIZE + 3]; + int err; + + if (!(dev = alloc_etherdev(sizeof(struct port)))) +@@ -1465,20 +1508,9 @@ static int eth_init_one(struct platform_ + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); + udelay(50); + +- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, +- mdio_bus->id, plat->phy); +- port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, +- PHY_INTERFACE_MODE_MII); +- if (IS_ERR(port->phydev)) { +- err = PTR_ERR(port->phydev); ++ err = ixp4xx_phy_connect(dev); ++ if (err) + goto err_free_mem; +- } +- +- /* mask with MAC supported features */ +- port->phydev->supported &= PHY_BASIC_FEATURES; +- port->phydev->advertising = port->phydev->supported; +- +- port->phydev->irq = PHY_POLL; + + if ((err = register_netdev(dev))) + goto err_phy_dis; +@@ -1489,7 +1521,7 @@ static int eth_init_one(struct platform_ + return 0; + + err_phy_dis: +- phy_disconnect(port->phydev); ++ ixp4xx_phy_disconnect(dev); + err_free_mem: + npe_port_tab[NPE_ID(port->id)] = NULL; + release_resource(port->mem_res); +@@ -1506,7 +1538,7 @@ static int eth_remove_one(struct platfor + struct port *port = netdev_priv(dev); + + unregister_netdev(dev); +- phy_disconnect(port->phydev); ++ ixp4xx_phy_disconnect(dev); + npe_port_tab[NPE_ID(port->id)] = NULL; + npe_release(port->npe); + release_resource(port->mem_res); diff --git a/target/linux/ixp4xx/patches-3.18/206-npe_driver_add_update_link_function.patch b/target/linux/ixp4xx/patches-3.18/206-npe_driver_add_update_link_function.patch new file mode 100644 index 0000000..f1a7707 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/206-npe_driver_add_update_link_function.patch @@ -0,0 +1,98 @@ +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -177,7 +177,7 @@ struct port { + struct desc *desc_tab; /* coherent */ + u32 desc_tab_phys; + int id; /* logical port ID */ +- int speed, duplex; ++ int link, speed, duplex; + u8 firmware[4]; + int hwts_tx_en; + int hwts_rx_en; +@@ -558,37 +558,52 @@ static void ixp4xx_mdio_remove(void) + mdiobus_free(mdio_bus); + } + +- +-static void ixp4xx_adjust_link(struct net_device *dev) ++static void ixp4xx_update_link(struct net_device *dev) + { + struct port *port = netdev_priv(dev); +- struct phy_device *phydev = port->phydev; + +- if (!phydev->link) { +- if (port->speed) { +- port->speed = 0; +- printk(KERN_INFO "%s: link down\n", dev->name); +- } ++ if (!port->link) { ++ netif_carrier_off(dev); ++ printk(KERN_INFO "%s: link down\n", dev->name); + return; + } + +- if (port->speed == phydev->speed && port->duplex == phydev->duplex) +- return; +- +- port->speed = phydev->speed; +- port->duplex = phydev->duplex; +- +- if (port->duplex) ++ if (port->duplex == DUPLEX_FULL) + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, + &port->regs->tx_control[0]); + else + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, + &port->regs->tx_control[0]); + ++ netif_carrier_on(dev); + printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n", + dev->name, port->speed, port->duplex ? "full" : "half"); + } + ++static void ixp4xx_adjust_link(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ struct phy_device *phydev = port->phydev; ++ int status_change = 0; ++ ++ if (phydev->link) { ++ if (port->duplex != phydev->duplex ++ || port->speed != phydev->speed) { ++ status_change = 1; ++ } ++ } ++ ++ if (phydev->link != port->link) ++ status_change = 1; ++ ++ port->link = phydev->link; ++ port->speed = phydev->speed; ++ port->duplex = phydev->duplex; ++ ++ if (status_change) ++ ixp4xx_update_link(dev); ++} ++ + static int ixp4xx_phy_connect(struct net_device *dev) + { + struct port *port = netdev_priv(dev); +@@ -624,7 +639,6 @@ static void ixp4xx_phy_start(struct net_ + { + struct port *port = netdev_priv(dev); + +- port->speed = 0; /* force "link up" message */ + phy_start(port->phydev); + } + +@@ -1515,6 +1529,10 @@ static int eth_init_one(struct platform_ + if ((err = register_netdev(dev))) + goto err_phy_dis; + ++ port->link = 0; ++ port->speed = 0; ++ port->duplex = -1; ++ + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, + npe_name(port->npe)); + diff --git a/target/linux/ixp4xx/patches-3.18/207-npe_driver_multiphy_support.patch b/target/linux/ixp4xx/patches-3.18/207-npe_driver_multiphy_support.patch new file mode 100644 index 0000000..32035ab --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/207-npe_driver_multiphy_support.patch @@ -0,0 +1,154 @@ +TODO: take care of additional PHYs through the PHY abstraction layer + +--- a/arch/arm/mach-ixp4xx/include/mach/platform.h ++++ b/arch/arm/mach-ixp4xx/include/mach/platform.h +@@ -74,7 +74,7 @@ extern unsigned long ixp4xx_exp_bus_size + /* + * Clock Speed Definitions. + */ +-#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ ++#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ + #define IXP4XX_UART_XTAL 14745600 + + /* +@@ -95,12 +95,23 @@ struct ixp4xx_pata_data { + #define IXP4XX_ETH_NPEB 0x10 + #define IXP4XX_ETH_NPEC 0x20 + ++#define IXP4XX_ETH_PHY_MAX_ADDR 32 ++ + /* Information about built-in Ethernet MAC interfaces */ + struct eth_plat_info { + u8 phy; /* MII PHY ID, 0 - 31 */ + u8 rxq; /* configurable, currently 0 - 31 only */ + u8 txreadyq; + u8 hwaddr[6]; ++ ++ u32 phy_mask; ++#if 0 ++ int speed; ++ int duplex; ++#else ++ int speed_10; ++ int half_duplex; ++#endif + }; + + /* Information about built-in HSS (synchronous serial) interfaces */ +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -610,6 +610,37 @@ static int ixp4xx_phy_connect(struct net + struct eth_plat_info *plat = port->plat; + char phy_id[MII_BUS_ID_SIZE + 3]; + ++ if (plat->phy == IXP4XX_ETH_PHY_MAX_ADDR) { ++#if 0 ++ switch (plat->speed) { ++ case SPEED_10: ++ case SPEED_100: ++ break; ++ default: ++ printk(KERN_ERR "%s: invalid speed (%d)\n", ++ dev->name, plat->speed); ++ return -EINVAL; ++ } ++ ++ switch (plat->duplex) { ++ case DUPLEX_HALF: ++ case DUPLEX_FULL: ++ break; ++ default: ++ printk(KERN_ERR "%s: invalid duplex mode (%d)\n", ++ dev->name, plat->duplex); ++ return -EINVAL; ++ } ++ port->speed = plat->speed; ++ port->duplex = plat->duplex; ++#else ++ port->speed = plat->speed_10 ? SPEED_10 : SPEED_100; ++ port->duplex = plat->half_duplex ? DUPLEX_HALF : DUPLEX_FULL; ++#endif ++ ++ return 0; ++ } ++ + snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, + mdio_bus->id, plat->phy); + port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, +@@ -632,21 +663,32 @@ static void ixp4xx_phy_disconnect(struct + { + struct port *port = netdev_priv(dev); + +- phy_disconnect(port->phydev); ++ if (port->phydev) ++ phy_disconnect(port->phydev); + } + + static void ixp4xx_phy_start(struct net_device *dev) + { + struct port *port = netdev_priv(dev); + +- phy_start(port->phydev); ++ if (port->phydev) { ++ phy_start(port->phydev); ++ } else { ++ port->link = 1; ++ ixp4xx_update_link(dev); ++ } + } + + static void ixp4xx_phy_stop(struct net_device *dev) + { + struct port *port = netdev_priv(dev); + +- phy_stop(port->phydev); ++ if (port->phydev) { ++ phy_stop(port->phydev); ++ } else { ++ port->link = 0; ++ ixp4xx_update_link(dev); ++ } + } + + static inline void debug_pkt(struct net_device *dev, const char *func, +@@ -1048,6 +1090,9 @@ static int eth_ioctl(struct net_device * + return hwtstamp_get(dev, req); + } + ++ if (!port->phydev) ++ return -EOPNOTSUPP; ++ + return phy_mii_ioctl(port->phydev, req, cmd); + } + +@@ -1068,18 +1113,30 @@ static void ixp4xx_get_drvinfo(struct ne + static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) + { + struct port *port = netdev_priv(dev); ++ ++ if (!port->phydev) ++ return -EOPNOTSUPP; ++ + return phy_ethtool_gset(port->phydev, cmd); + } + + static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) + { + struct port *port = netdev_priv(dev); ++ ++ if (!port->phydev) ++ return -EOPNOTSUPP; ++ + return phy_ethtool_sset(port->phydev, cmd); + } + + static int ixp4xx_nway_reset(struct net_device *dev) + { + struct port *port = netdev_priv(dev); ++ ++ if (!port->phydev) ++ return -EOPNOTSUPP; ++ + return phy_start_aneg(port->phydev); + } + diff --git a/target/linux/ixp4xx/patches-3.18/295-latch_led_driver.patch b/target/linux/ixp4xx/patches-3.18/295-latch_led_driver.patch new file mode 100644 index 0000000..97d4445 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/295-latch_led_driver.patch @@ -0,0 +1,201 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -250,6 +250,12 @@ config LEDS_LP8788 + help + This option enables support for the Keyboard LEDs on the LP8788 PMIC. + ++config LEDS_LATCH ++ tristate "LED Support for Memory Latched LEDs" ++ depends on LEDS_CLASS ++ help ++ -- To Do -- ++ + config LEDS_CLEVO_MAIL + tristate "Mail LED on Clevo notebook" + depends on LEDS_CLASS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -21,6 +21,7 @@ obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunf + obj-$(CONFIG_LEDS_PCA9532) += leds-pca9532.o + obj-$(CONFIG_LEDS_GPIO_REGISTER) += leds-gpio-register.o + obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o ++obj-$(CONFIG_LEDS_LATCH) += leds-latch.o + obj-$(CONFIG_LEDS_LP3944) += leds-lp3944.o + obj-$(CONFIG_LEDS_LP55XX_COMMON) += leds-lp55xx-common.o + obj-$(CONFIG_LEDS_LP5521) += leds-lp5521.o +--- /dev/null ++++ b/drivers/leds/leds-latch.c +@@ -0,0 +1,152 @@ ++/* ++ * LEDs driver for Memory Latched Devices ++ * ++ * Copyright (C) 2008 Gateworks Corp. ++ * Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static unsigned int mem_keep = 0xFF; ++static spinlock_t mem_lock; ++static unsigned char *iobase; ++ ++struct latch_led_data { ++ struct led_classdev cdev; ++ struct work_struct work; ++ u8 new_level; ++ u8 bit; ++ void (*set_led)(u8 bit, enum led_brightness value); ++}; ++ ++static void latch_set_led(u8 bit, enum led_brightness value) ++{ ++ if (value == LED_OFF) ++ mem_keep |= (0x1 << bit); ++ else ++ mem_keep &= ~(0x1 << bit); ++ ++ writeb(mem_keep, iobase); ++} ++ ++static void latch_led_set(struct led_classdev *led_cdev, ++ enum led_brightness value) ++{ ++ struct latch_led_data *led_dat = ++ container_of(led_cdev, struct latch_led_data, cdev); ++ ++ raw_spin_lock(mem_lock); ++ ++ led_dat->set_led(led_dat->bit, value); ++ ++ raw_spin_unlock(mem_lock); ++} ++ ++static int latch_led_probe(struct platform_device *pdev) ++{ ++ struct latch_led_platform_data *pdata = pdev->dev.platform_data; ++ struct latch_led *cur_led; ++ struct latch_led_data *leds_data, *led_dat; ++ int i, ret = 0; ++ ++ if (!pdata) ++ return -EBUSY; ++ ++ leds_data = kzalloc(sizeof(struct latch_led_data) * pdata->num_leds, ++ GFP_KERNEL); ++ if (!leds_data) ++ return -ENOMEM; ++ ++ for (i = 0; i < pdata->num_leds; i++) { ++ cur_led = &pdata->leds[i]; ++ led_dat = &leds_data[i]; ++ ++ led_dat->cdev.name = cur_led->name; ++ led_dat->cdev.default_trigger = cur_led->default_trigger; ++ led_dat->cdev.brightness_set = latch_led_set; ++ led_dat->cdev.brightness = LED_OFF; ++ led_dat->bit = cur_led->bit; ++ led_dat->set_led = pdata->set_led ? pdata->set_led : latch_set_led; ++ ++ ret = led_classdev_register(&pdev->dev, &led_dat->cdev); ++ if (ret < 0) { ++ goto err; ++ } ++ } ++ ++ if (!pdata->set_led) { ++ iobase = ioremap_nocache(pdata->mem, 0x1000); ++ writeb(0xFF, iobase); ++ } ++ platform_set_drvdata(pdev, leds_data); ++ ++ return 0; ++ ++err: ++ if (i > 0) { ++ for (i = i - 1; i >= 0; i--) { ++ led_classdev_unregister(&leds_data[i].cdev); ++ } ++ } ++ ++ kfree(leds_data); ++ ++ return ret; ++} ++ ++static int latch_led_remove(struct platform_device *pdev) ++{ ++ int i; ++ struct latch_led_platform_data *pdata = pdev->dev.platform_data; ++ struct latch_led_data *leds_data; ++ ++ leds_data = platform_get_drvdata(pdev); ++ ++ for (i = 0; i < pdata->num_leds; i++) { ++ led_classdev_unregister(&leds_data[i].cdev); ++ cancel_work_sync(&leds_data[i].work); ++ } ++ ++ kfree(leds_data); ++ ++ return 0; ++} ++ ++static struct platform_driver latch_led_driver = { ++ .probe = latch_led_probe, ++ .remove = latch_led_remove, ++ .driver = { ++ .name = "leds-latch", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init latch_led_init(void) ++{ ++ return platform_driver_register(&latch_led_driver); ++} ++ ++static void __exit latch_led_exit(void) ++{ ++ platform_driver_unregister(&latch_led_driver); ++} ++ ++module_init(latch_led_init); ++module_exit(latch_led_exit); ++ ++MODULE_AUTHOR("Chris Lang "); ++MODULE_DESCRIPTION("Latch LED driver"); +--- a/include/linux/leds.h ++++ b/include/linux/leds.h +@@ -297,4 +297,18 @@ static inline void ledtrig_cpu(enum cpu_ + } + #endif + ++/* For the leds-latch driver */ ++struct latch_led { ++ const char *name; ++ char *default_trigger; ++ unsigned bit; ++}; ++ ++struct latch_led_platform_data { ++ int num_leds; ++ u32 mem; ++ struct latch_led *leds; ++ void (*set_led)(u8 bit, enum led_brightness value); ++}; ++ + #endif /* __LINUX_LEDS_H_INCLUDED */ diff --git a/target/linux/ixp4xx/patches-3.18/300-avila_support.patch b/target/linux/ixp4xx/patches-3.18/300-avila_support.patch new file mode 100644 index 0000000..d2dafaa --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/300-avila_support.patch @@ -0,0 +1,726 @@ +--- a/arch/arm/mach-ixp4xx/avila-pci.c ++++ b/arch/arm/mach-ixp4xx/avila-pci.c +@@ -27,8 +27,8 @@ + #include + #include + +-#define AVILA_MAX_DEV 4 +-#define LOFT_MAX_DEV 6 ++#define AVILA_MAX_DEV 6 ++ + #define IRQ_LINES 4 + + /* PCI controller GPIO to IRQ pin mappings */ +@@ -55,10 +55,8 @@ static int __init avila_map_irq(const st + IXP4XX_GPIO_IRQ(INTD) + }; + +- if (slot >= 1 && +- slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) && +- pin >= 1 && pin <= IRQ_LINES) +- return pci_irq_table[(slot + pin - 2) % 4]; ++ if (slot >= 1 && slot <= AVILA_MAX_DEV && pin >= 1 && pin <= IRQ_LINES) ++ return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; + + return -1; + } +--- a/arch/arm/mach-ixp4xx/avila-setup.c ++++ b/arch/arm/mach-ixp4xx/avila-setup.c +@@ -14,9 +14,16 @@ + #include + #include + #include ++#include ++#include ++#include + #include + #include + #include ++#include ++#include ++#include ++#include + #include + #include + #include +@@ -26,10 +33,25 @@ + #include + #include + #include ++#include + + #define AVILA_SDA_PIN 7 + #define AVILA_SCL_PIN 6 + ++/* User LEDs */ ++#define AVILA_GW23XX_LED_USER_GPIO 3 ++#define AVILA_GW23X7_LED_USER_GPIO 4 ++ ++/* gpio mask used by platform device */ ++#define AVILA_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) | (1 << 9) ++ ++struct avila_board_info { ++ unsigned char *model; ++ void (*setup)(void); ++}; ++ ++static struct avila_board_info *avila_info __initdata; ++ + static struct flash_platform_data avila_flash_data = { + .map_name = "cfi_probe", + .width = 2, +@@ -105,14 +127,69 @@ static struct platform_device avila_uart + .resource = avila_uart_resources + }; + +-static struct resource avila_pata_resources[] = { ++static struct resource avila_optional_uart_resources[] = { + { +- .flags = IORESOURCE_MEM +- }, ++ .start = 0x54000000, ++ .end = 0x54000fff, ++ .flags = IORESOURCE_MEM ++ },{ ++ .start = 0x55000000, ++ .end = 0x55000fff, ++ .flags = IORESOURCE_MEM ++ },{ ++ .start = 0x56000000, ++ .end = 0x56000fff, ++ .flags = IORESOURCE_MEM ++ },{ ++ .start = 0x57000000, ++ .end = 0x57000fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port avila_optional_uart_data[] = { + { +- .flags = IORESOURCE_MEM, ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ .rw_delay = 2, ++ },{ ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ .rw_delay = 2, ++ },{ ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ .rw_delay = 2, ++ },{ ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ .rw_delay = 2, + }, ++ { } ++}; ++ ++static struct platform_device avila_optional_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM1, ++ .dev.platform_data = avila_optional_uart_data, ++ .num_resources = 4, ++ .resource = avila_optional_uart_resources, ++}; ++ ++static struct resource avila_pata_resources[] = { + { ++ .flags = IORESOURCE_MEM ++ },{ ++ .flags = IORESOURCE_MEM, ++ },{ + .name = "intrq", + .start = IRQ_IXP4XX_GPIO12, + .end = IRQ_IXP4XX_GPIO12, +@@ -133,21 +210,237 @@ static struct platform_device avila_pata + .resource = avila_pata_resources, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info avila_npeb_data = { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++}; ++ ++static struct eth_plat_info avila_npec_data = { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct platform_device avila_npeb_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = &avila_npeb_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct platform_device avila_npec_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = &avila_npec_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct gpio_led avila_gpio_leds[] = { ++ { ++ .name = "user", /* green led */ ++ .gpio = AVILA_GW23XX_LED_USER_GPIO, ++ .active_low = 1, ++ }, ++ { ++ .name = "radio1", /* green led */ ++ .gpio = 104, ++ .active_low = 1, ++ }, ++ { ++ .name = "radio2", /* green led */ ++ .gpio = 105, ++ .active_low = 1, ++ }, ++ { ++ .name = "radio3", /* green led */ ++ .gpio = 106, ++ .active_low = 1, ++ }, ++ { ++ .name = "radio4", /* green led */ ++ .gpio = 107, ++ .active_low = 1, ++ }, ++ ++}; ++ ++static struct gpio_led_platform_data avila_gpio_leds_data = { ++ .num_leds = 1, ++ .leds = avila_gpio_leds, ++}; ++ ++static struct platform_device avila_gpio_leds_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &avila_gpio_leds_data, ++}; ++ ++static struct latch_led avila_latch_leds[] = { ++ { ++ .name = "led0", /* green led */ ++ .bit = 0, ++ }, ++ { ++ .name = "led1", /* green led */ ++ .bit = 1, ++ }, ++ { ++ .name = "led2", /* green led */ ++ .bit = 2, ++ }, ++ { ++ .name = "led3", /* green led */ ++ .bit = 3, ++ }, ++ { ++ .name = "led4", /* green led */ ++ .bit = 4, ++ }, ++ { ++ .name = "led5", /* green led */ ++ .bit = 5, ++ }, ++ { ++ .name = "led6", /* green led */ ++ .bit = 6, ++ }, ++ { ++ .name = "led7", /* green led */ ++ .bit = 7, ++ } ++}; ++ ++static struct latch_led_platform_data avila_latch_leds_data = { ++ .num_leds = 8, ++ .leds = avila_latch_leds, ++ .mem = 0x51000000, ++}; ++ ++static struct platform_device avila_latch_leds_device = { ++ .name = "leds-latch", ++ .id = -1, ++ .dev.platform_data = &avila_latch_leds_data, ++}; ++ + static struct platform_device *avila_devices[] __initdata = { + &avila_i2c_gpio, +- &avila_flash, + &avila_uart + }; + +-static void __init avila_init(void) ++/* ++ * Audio Devices ++ */ ++ ++static struct platform_device avila_hss_device[] = { ++ { ++ .name = "gw_avila_hss", ++ .id = 0, ++ },{ ++ .name = "gw_avila_hss", ++ .id = 1, ++ },{ ++ .name = "gw_avila_hss", ++ .id = 2, ++ },{ ++ .name = "gw_avila_hss", ++ .id = 3, ++ }, ++}; ++ ++static struct platform_device avila_pcm_device[] = { ++ { ++ .name = "gw_avila-audio", ++ .id = 0, ++ },{ ++ .name = "gw_avila-audio", ++ .id = 1, ++ },{ ++ .name = "gw_avila-audio", ++ .id = 2, ++ },{ ++ .name = "gw_avila-audio", ++ .id = 3, ++ } ++}; ++ ++static void setup_audio_devices(void) { ++ platform_device_register(&avila_hss_device[0]); ++ platform_device_register(&avila_hss_device[1]); ++ platform_device_register(&avila_hss_device[2]); ++ platform_device_register(&avila_hss_device[3]); ++ ++ platform_device_register(&avila_pcm_device[0]); ++ platform_device_register(&avila_pcm_device[1]); ++ platform_device_register(&avila_pcm_device[2]); ++ platform_device_register(&avila_pcm_device[3]); ++} ++ ++static void __init avila_gw23xx_setup(void) + { +- ixp4xx_sys_init(); ++ platform_device_register(&avila_npeb_device); ++ platform_device_register(&avila_npec_device); + +- avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); +- avila_flash_resource.end = +- IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ platform_device_register(&avila_gpio_leds_device); ++} + +- platform_add_devices(avila_devices, ARRAY_SIZE(avila_devices)); ++static void __init avila_gw2342_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ platform_device_register(&avila_npec_device); ++ ++ platform_device_register(&avila_gpio_leds_device); ++ ++ avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); ++ avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); ++ ++ avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2); ++ avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(2); ++ ++ avila_pata_data.cs0_cfg = IXP4XX_EXP_CS1; ++ avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2; ++ ++ platform_device_register(&avila_pata); ++} ++ ++static void __init avila_gw2345_setup(void) ++{ ++ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */ ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */ ++ platform_device_register(&avila_npec_device); ++ ++ platform_device_register(&avila_gpio_leds_device); ++ ++ avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); ++ avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); ++ ++ avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2); ++ avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(2); ++ ++ avila_pata_data.cs0_cfg = IXP4XX_EXP_CS1; ++ avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2; ++ ++ platform_device_register(&avila_pata); ++} ++ ++static void __init avila_gw2347_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ ++ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO; ++ platform_device_register(&avila_gpio_leds_device); ++} ++ ++static void __init avila_gw2348_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ platform_device_register(&avila_npec_device); ++ ++ platform_device_register(&avila_gpio_leds_device); + + avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); + avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); +@@ -159,8 +452,335 @@ static void __init avila_init(void) + avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2; + + platform_device_register(&avila_pata); ++} ++ ++static void __init avila_gw2353_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ platform_device_register(&avila_gpio_leds_device); ++} ++ ++static void __init avila_gw2355_setup(void) ++{ ++ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */ ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 16; ++ platform_device_register(&avila_npec_device); ++ ++ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO; ++ platform_device_register(&avila_gpio_leds_device); ++ ++ *IXP4XX_EXP_CS4 |= 0xbfff3c03; ++ avila_latch_leds[0].name = "RXD"; ++ avila_latch_leds[1].name = "TXD"; ++ avila_latch_leds[2].name = "POL"; ++ avila_latch_leds[3].name = "LNK"; ++ avila_latch_leds[4].name = "ERR"; ++ avila_latch_leds_data.num_leds = 5; ++ avila_latch_leds_data.mem = 0x54000000; ++ platform_device_register(&avila_latch_leds_device); ++ ++ avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); ++ avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); ++ ++ avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2); ++ avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(2); ++ ++ avila_pata_data.cs0_cfg = IXP4XX_EXP_CS1; ++ avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2; ++ ++ platform_device_register(&avila_pata); ++} ++ ++static void __init avila_gw2357_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ ++ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO; ++ platform_device_register(&avila_gpio_leds_device); ++ ++ *IXP4XX_EXP_CS1 |= 0xbfff3c03; ++ platform_device_register(&avila_latch_leds_device); ++} ++ ++static void __init avila_gw2365_setup(void) ++{ ++ avila_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS4 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO0, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[0].mapbase = 0x54000000; ++ avila_optional_uart_data[0].membase = (void __iomem *)ioremap(0x54000000, 0x0fff); ++ avila_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO0; ++ ++ *IXP4XX_EXP_CS5 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[1].mapbase = 0x55000000; ++ avila_optional_uart_data[1].membase = (void __iomem *)ioremap(0x55000000, 0x0fff); ++ avila_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO1; ++ ++ *IXP4XX_EXP_CS6 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[2].mapbase = 0x56000000; ++ avila_optional_uart_data[2].membase = (void __iomem *)ioremap(0x56000000, 0x0fff); ++ avila_optional_uart_data[2].irq = IRQ_IXP4XX_GPIO2; ++ ++ *IXP4XX_EXP_CS7 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[3].mapbase = 0x57000000; ++ avila_optional_uart_data[3].membase = (void __iomem *)ioremap(0x57000000, 0x0fff); ++ avila_optional_uart_data[3].irq = IRQ_IXP4XX_GPIO3; ++ ++ platform_device_register(&avila_optional_uart); ++ ++ avila_npeb_data.phy = 1; ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 2; ++ platform_device_register(&avila_npec_device); ++ ++ avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(2); ++ avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(2); ++ ++ avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(3); ++ avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(3); ++ ++ avila_pata_data.cs0_cfg = IXP4XX_EXP_CS2; ++ avila_pata_data.cs1_cfg = IXP4XX_EXP_CS3; ++ ++ platform_device_register(&avila_pata); ++ ++ avila_gpio_leds[0].gpio = 109; ++ avila_gpio_leds_data.num_leds = 5; ++ platform_device_register(&avila_gpio_leds_device); ++ ++ setup_audio_devices(); ++} ++ ++static void __init avila_gw2369_setup(void) ++{ ++ avila_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ avila_npeb_data.phy = 1; ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 2; ++ platform_device_register(&avila_npec_device); ++ ++ setup_audio_devices(); ++} ++ ++static void __init avila_gw2370_setup(void) ++{ ++ avila_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ avila_npeb_data.phy = 5; ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++ avila_npec_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */ ++ platform_device_register(&avila_npec_device); ++ ++ *IXP4XX_EXP_CS2 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[0].mapbase = 0x52000000; ++ avila_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff); ++ avila_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO2; ++ ++ *IXP4XX_EXP_CS3 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[1].mapbase = 0x53000000; ++ avila_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53000000, 0x0fff); ++ avila_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO3; ++ ++ avila_optional_uart.num_resources = 2; ++ ++ platform_device_register(&avila_optional_uart); ++ ++ avila_gpio_leds[0].gpio = 101; ++ platform_device_register(&avila_gpio_leds_device); ++ ++ setup_audio_devices(); ++} ++ ++static void __init avila_gw2375_setup(void) ++{ ++ avila_npeb_data.phy = 1; ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 2; ++ platform_device_register(&avila_npec_device); ++ ++ *IXP4XX_EXP_CS2 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[0].mapbase = 0x52000000; ++ avila_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff); ++ avila_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO10; ++ ++ avila_optional_uart.num_resources = 1; ++ ++ platform_device_register(&avila_optional_uart); ++ ++ setup_audio_devices(); ++} ++ ++ ++static struct avila_board_info avila_boards[] __initdata = { ++ { ++ .model = "GW2342", ++ .setup = avila_gw2342_setup, ++ }, { ++ .model = "GW2345", ++ .setup = avila_gw2345_setup, ++ }, { ++ .model = "GW2347", ++ .setup = avila_gw2347_setup, ++ }, { ++ .model = "GW2348", ++ .setup = avila_gw2348_setup, ++ }, { ++ .model = "GW2353", ++ .setup = avila_gw2353_setup, ++ }, { ++ .model = "GW2355", ++ .setup = avila_gw2355_setup, ++ }, { ++ .model = "GW2357", ++ .setup = avila_gw2357_setup, ++ }, { ++ .model = "GW2365", ++ .setup = avila_gw2365_setup, ++ }, { ++ .model = "GW2369", ++ .setup = avila_gw2369_setup, ++ }, { ++ .model = "GW2370", ++ .setup = avila_gw2370_setup, ++ }, { ++ .model = "GW2373", ++ .setup = avila_gw2369_setup, ++ }, { ++ .model = "GW2375", ++ .setup = avila_gw2375_setup, ++ } ++}; ++ ++static struct avila_board_info * __init avila_find_board_info(char *model) ++{ ++ int i; ++ model[6] = '\0'; ++ ++ for (i = 0; i < ARRAY_SIZE(avila_boards); i++) { ++ struct avila_board_info *info = &avila_boards[i]; ++ if (strcmp(info->model, model) == 0) ++ return info; ++ } ++ ++ return NULL; ++} ++ ++static struct memory_accessor *at24_mem_acc; ++ ++static void at24_setup(struct memory_accessor *mem_acc, void *context) ++{ ++ char mac_addr[ETH_ALEN]; ++ char model[7]; ++ ++ at24_mem_acc = mem_acc; ++ ++ /* Read MAC addresses */ ++ if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x0, 6) == 6) { ++ memcpy(&avila_npeb_data.hwaddr, mac_addr, ETH_ALEN); ++ } ++ if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x6, 6) == 6) { ++ memcpy(&avila_npec_data.hwaddr, mac_addr, ETH_ALEN); ++ } ++ ++ /* Read the first 6 bytes of the model number */ ++ if (at24_mem_acc->read(at24_mem_acc, model, 0x20, 6) == 6) { ++ avila_info = avila_find_board_info(model); ++ } ++ ++} ++ ++static struct at24_platform_data avila_eeprom_info = { ++ .byte_len = 1024, ++ .page_size = 16, ++// .flags = AT24_FLAG_READONLY, ++ .setup = at24_setup, ++}; ++ ++static struct pca953x_platform_data avila_pca_data = { ++ .gpio_base = 100, ++}; ++ ++static struct i2c_board_info __initdata avila_i2c_board_info[] = { ++ { ++ I2C_BOARD_INFO("ds1672", 0x68), ++ }, ++ { ++ I2C_BOARD_INFO("gsp", 0x29), ++ }, ++ { ++ I2C_BOARD_INFO("pca9555", 0x23), ++ .platform_data = &avila_pca_data, ++ }, ++ { ++ I2C_BOARD_INFO("ad7418", 0x28), ++ }, ++ { ++ I2C_BOARD_INFO("24c08", 0x51), ++ .platform_data = &avila_eeprom_info ++ }, ++ { ++ I2C_BOARD_INFO("tlv320aic33", 0x1b), ++ }, ++ { ++ I2C_BOARD_INFO("tlv320aic33", 0x1a), ++ }, ++ { ++ I2C_BOARD_INFO("tlv320aic33", 0x19), ++ }, ++ { ++ I2C_BOARD_INFO("tlv320aic33", 0x18), ++ }, ++}; ++ ++static void __init avila_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ platform_add_devices(avila_devices, ARRAY_SIZE(avila_devices)); ++ ++ i2c_register_board_info(0, avila_i2c_board_info, ++ ARRAY_SIZE(avila_i2c_board_info)); ++} ++ ++static int __init avila_model_setup(void) ++{ ++ if (!machine_is_avila()) ++ return 0; ++ ++ /* default 16MB flash */ ++ avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ avila_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_16M - 1; ++ ++ if (avila_info) { ++ printk(KERN_DEBUG "Running on Gateworks Avila %s\n", ++ avila_info->model); ++ avila_info->setup(); ++ } else { ++ printk(KERN_INFO "Unknown/missing Avila model number" ++ " -- defaults will be used\n"); ++ avila_gw23xx_setup(); ++ } ++ platform_device_register(&avila_flash); + ++ return 0; + } ++late_initcall(avila_model_setup); + + MACHINE_START(AVILA, "Gateworks Avila Network Platform") + /* Maintainer: Deepak Saxena */ diff --git a/target/linux/ixp4xx/patches-3.18/304-ixp4xx_eth_jumboframe.patch b/target/linux/ixp4xx/patches-3.18/304-ixp4xx_eth_jumboframe.patch new file mode 100644 index 0000000..b16086b --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/304-ixp4xx_eth_jumboframe.patch @@ -0,0 +1,80 @@ +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -57,7 +57,7 @@ + + #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) + #define REGS_SIZE 0x1000 +-#define MAX_MRU 1536 /* 0x600 */ ++#define MAX_MRU (14320 - ETH_HLEN - ETH_FCS_LEN) + #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) + + #define NAPI_WEIGHT 16 +@@ -1315,6 +1315,32 @@ static void destroy_queues(struct port * + } + } + ++static int eth_do_change_mtu(struct net_device *dev, int mtu) ++{ ++ struct port *port; ++ struct msg msg; ++ /* adjust for ethernet headers */ ++ int framesize = mtu + ETH_HLEN + ETH_FCS_LEN; ++ ++ port = netdev_priv(dev); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = NPE_SETMAXFRAMELENGTHS; ++ msg.eth_id = port->id; ++ ++ /* max rx/tx 64 byte blocks */ ++ msg.byte2 = ((framesize + 63) / 64) << 8; ++ msg.byte3 = ((framesize + 63) / 64) << 8; ++ ++ msg.byte4 = msg.byte6 = framesize >> 8; ++ msg.byte5 = msg.byte7 = framesize & 0xff; ++ ++ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAX_FRAME_LENGTH")) ++ return -EIO; ++ ++ return 0; ++} ++ + static int eth_open(struct net_device *dev) + { + struct port *port = netdev_priv(dev); +@@ -1366,6 +1392,8 @@ static int eth_open(struct net_device *d + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) + return -EIO; + ++ eth_do_change_mtu(dev, dev->mtu); ++ + if ((err = request_queues(port)) != 0) + return err; + +@@ -1505,7 +1533,26 @@ static int eth_close(struct net_device * + return 0; + } + ++static int ixp_eth_change_mtu(struct net_device *dev, int mtu) ++{ ++ int ret; ++ ++ if (mtu > MAX_MRU) ++ return -EINVAL; ++ ++ if (dev->flags & IFF_UP) { ++ ret = eth_do_change_mtu(dev, mtu); ++ if (ret < 0) ++ return ret; ++ } ++ ++ dev->mtu = mtu; ++ ++ return 0; ++} ++ + static const struct net_device_ops ixp4xx_netdev_ops = { ++ .ndo_change_mtu = ixp_eth_change_mtu, + .ndo_open = eth_open, + .ndo_stop = eth_close, + .ndo_start_xmit = eth_xmit, diff --git a/target/linux/ixp4xx/patches-3.18/310-gtwx5717_spi_bus.patch b/target/linux/ixp4xx/patches-3.18/310-gtwx5717_spi_bus.patch new file mode 100644 index 0000000..080b96a --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/310-gtwx5717_spi_bus.patch @@ -0,0 +1,52 @@ +--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c ++++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -146,9 +147,41 @@ static struct platform_device gtwx5715_f + .resource = >wx5715_flash_resource, + }; + ++static int gtwx5715_spi_boardinfo_setup(struct spi_board_info *bi, ++ struct spi_master *master, void *data) ++{ ++ ++ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias)); ++ ++ bi->max_speed_hz = 5000000 /* Hz */; ++ bi->bus_num = master->bus_num; ++ bi->mode = SPI_MODE_0; ++ ++ return 0; ++} ++ ++static struct spi_gpio_platform_data gtwx5715_spi_bus_data = { ++ .pin_cs = GTWX5715_KSSPI_SELECT, ++ .pin_clk = GTWX5715_KSSPI_CLOCK, ++ .pin_miso = GTWX5715_KSSPI_RXD, ++ .pin_mosi = GTWX5715_KSSPI_TXD, ++ .cs_activelow = 1, ++ .no_spi_delay = 1, ++ .boardinfo_setup = gtwx5715_spi_boardinfo_setup, ++}; ++ ++static struct platform_device gtwx5715_spi_bus = { ++ .name = "spi-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = >wx5715_spi_bus_data, ++ }, ++}; ++ + static struct platform_device *gtwx5715_devices[] __initdata = { + >wx5715_uart_device, + >wx5715_flash, ++ >wx5715_spi_bus, + }; + + static void __init gtwx5715_init(void) diff --git a/target/linux/ixp4xx/patches-3.18/311-gtwx5717_mac_plat_info.patch b/target/linux/ixp4xx/patches-3.18/311-gtwx5717_mac_plat_info.patch new file mode 100644 index 0000000..aa7a9e0 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/311-gtwx5717_mac_plat_info.patch @@ -0,0 +1,50 @@ +--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c ++++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -178,10 +179,39 @@ static struct platform_device gtwx5715_s + }, + }; + ++static struct eth_plat_info gtwx5715_npeb_data = { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */ ++ .rxq = 3, ++ .txreadyq = 20, ++}; ++ ++static struct eth_plat_info gtwx5715_npec_data = { ++ .phy = 5, /* port 5 of the KS8995 switch */ ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct platform_device gtwx5715_npeb_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = >wx5715_npeb_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct platform_device gtwx5715_npec_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = >wx5715_npec_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ + static struct platform_device *gtwx5715_devices[] __initdata = { + >wx5715_uart_device, + >wx5715_flash, + >wx5715_spi_bus, ++ >wx5715_npeb_device, ++ >wx5715_npec_device, + }; + + static void __init gtwx5715_init(void) diff --git a/target/linux/ixp4xx/patches-3.18/312-ixp4xx_pata_optimization.patch b/target/linux/ixp4xx/patches-3.18/312-ixp4xx_pata_optimization.patch new file mode 100644 index 0000000..59c2837 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/312-ixp4xx_pata_optimization.patch @@ -0,0 +1,137 @@ +--- a/drivers/ata/pata_ixp4xx_cf.c ++++ b/drivers/ata/pata_ixp4xx_cf.c +@@ -24,16 +24,58 @@ + #include + + #define DRV_NAME "pata_ixp4xx_cf" +-#define DRV_VERSION "0.2" ++#define DRV_VERSION "0.3" + + static int ixp4xx_set_mode(struct ata_link *link, struct ata_device **error) + { ++ struct ixp4xx_pata_data *data = link->ap->host->dev->platform_data; ++ unsigned int pio_mask; + struct ata_device *dev; + + ata_for_each_dev(dev, link, ENABLED) { +- ata_dev_info(dev, "configured for PIO0\n"); +- dev->pio_mode = XFER_PIO_0; +- dev->xfer_mode = XFER_PIO_0; ++ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)) { ++ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03; ++ if (pio_mask & (1 << 1)) { ++ pio_mask = 4; ++ } else { ++ pio_mask = 3; ++ } ++ } else { ++ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8); ++ } ++ ++ switch (pio_mask){ ++ case 0: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO0\n"); ++ dev->pio_mode = XFER_PIO_0; ++ dev->xfer_mode = XFER_PIO_0; ++ *data->cs0_cfg = 0x8a473c03; ++ break; ++ case 1: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO1\n"); ++ dev->pio_mode = XFER_PIO_1; ++ dev->xfer_mode = XFER_PIO_1; ++ *data->cs0_cfg = 0x86433c03; ++ break; ++ case 2: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO2\n"); ++ dev->pio_mode = XFER_PIO_2; ++ dev->xfer_mode = XFER_PIO_2; ++ *data->cs0_cfg = 0x82413c03; ++ break; ++ case 3: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO3\n"); ++ dev->pio_mode = XFER_PIO_3; ++ dev->xfer_mode = XFER_PIO_3; ++ *data->cs0_cfg = 0x80823c03; ++ break; ++ case 4: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO4\n"); ++ dev->pio_mode = XFER_PIO_4; ++ dev->xfer_mode = XFER_PIO_4; ++ *data->cs0_cfg = 0x80403c03; ++ break; ++ } + dev->xfer_shift = ATA_SHIFT_PIO; + dev->flags |= ATA_DFLAG_PIO; + } +@@ -46,6 +88,7 @@ static unsigned int ixp4xx_mmio_data_xfe + unsigned int i; + unsigned int words = buflen >> 1; + u16 *buf16 = (u16 *) buf; ++ unsigned int pio_mask; + struct ata_port *ap = dev->link->ap; + void __iomem *mmio = ap->ioaddr.data_addr; + struct ixp4xx_pata_data *data = dev_get_platdata(ap->host->dev); +@@ -53,8 +96,34 @@ static unsigned int ixp4xx_mmio_data_xfe + /* set the expansion bus in 16bit mode and restore + * 8 bit mode after the transaction. + */ +- *data->cs0_cfg &= ~(0x01); +- udelay(100); ++ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)){ ++ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03; ++ if (pio_mask & (1 << 1)){ ++ pio_mask = 4; ++ }else{ ++ pio_mask = 3; ++ } ++ }else{ ++ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8); ++ } ++ switch (pio_mask){ ++ case 0: ++ *data->cs0_cfg = 0xa9643c42; ++ break; ++ case 1: ++ *data->cs0_cfg = 0x85033c42; ++ break; ++ case 2: ++ *data->cs0_cfg = 0x80b23c42; ++ break; ++ case 3: ++ *data->cs0_cfg = 0x80823c42; ++ break; ++ case 4: ++ *data->cs0_cfg = 0x80403c42; ++ break; ++ } ++ udelay(5); + + /* Transfer multiple of 2 bytes */ + if (rw == READ) +@@ -79,8 +148,24 @@ static unsigned int ixp4xx_mmio_data_xfe + words++; + } + +- udelay(100); +- *data->cs0_cfg |= 0x01; ++ udelay(5); ++ switch (pio_mask){ ++ case 0: ++ *data->cs0_cfg = 0x8a473c03; ++ break; ++ case 1: ++ *data->cs0_cfg = 0x86433c03; ++ break; ++ case 2: ++ *data->cs0_cfg = 0x82413c03; ++ break; ++ case 3: ++ *data->cs0_cfg = 0x80823c03; ++ break; ++ case 4: ++ *data->cs0_cfg = 0x80403c03; ++ break; ++ } + + return words << 1; + } diff --git a/target/linux/ixp4xx/patches-3.18/500-usr8200_support.patch b/target/linux/ixp4xx/patches-3.18/500-usr8200_support.patch new file mode 100644 index 0000000..fb7f03e --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/500-usr8200_support.patch @@ -0,0 +1,347 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -93,6 +93,14 @@ config MACH_SIDEWINDER + Engineering Sidewinder board. For more information on this + platform, see http://www.adiengineering.com + ++config MACH_USR8200 ++ bool "USRobotics USR8200" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the USRobotics ++ USR8200 router board. For more information on this platform, see ++ http://openwrt.org ++ + config MACH_COMPEXWP18 + bool "Compex WP18 / NP18A" + select PCI +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -27,6 +27,7 @@ obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt + obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o + obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o ++obj-pci-$(CONFIG_MACH_USR8200) += usr8200-pci.o + + obj-y += common.o + +@@ -55,6 +56,7 @@ obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv + obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o + obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o + obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o ++obj-$(CONFIG_MACH_USR8200) += usr8200-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -44,7 +44,8 @@ static __inline__ void __arch_decomp_set + machine_is_gateway7001() || machine_is_wg302v2() || + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro() || +- machine_is_wrt300nv2() || machine_is_tw5334()) ++ machine_is_wrt300nv2() || machine_is_tw5334() || ++ machine_is_usr8200()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/usr8200-pci.c +@@ -0,0 +1,77 @@ ++/* ++ * arch/arch/mach-ixp4xx/usr8200-pci.c ++ * ++ * PCI setup routines for USRobotics USR8200 ++ * ++ * Copyright (C) 2008 Peter Denison ++ * ++ * based on pronghorn-pci.c ++ * Copyright (C) 2008 Imre Kaloz ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Peter Denison ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init usr8200_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init usr8200_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 14) ++ return IRQ_IXP4XX_GPIO7; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO8; ++ else if (slot == 16) { ++ if (pin == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (pin == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else if (pin == 3) ++ return IRQ_IXP4XX_GPIO9; ++ else ++ return -1; ++ } else ++ return -1; ++} ++ ++struct hw_pci usr8200_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = usr8200_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = usr8200_map_irq, ++}; ++ ++int __init usr8200_pci_init(void) ++{ ++ if (machine_is_usr8200()) ++ pci_common_init(&usr8200_pci); ++ return 0; ++} ++ ++subsys_initcall(usr8200_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/usr8200-setup.c +@@ -0,0 +1,217 @@ ++/* ++ * arch/arm/mach-ixp4xx/usr8200-setup.c ++ * ++ * Board setup for the USRobotics USR8200 ++ * ++ * Copyright (C) 2008 Peter Denison ++ * ++ * based on pronghorn-setup.c: ++ * Copyright (C) 2008 Imre Kaloz ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Peter Denison ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data usr8200_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource usr8200_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device usr8200_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &usr8200_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &usr8200_flash_resource, ++}; ++ ++static struct resource usr8200_uart_resources [] = { ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port usr8200_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device usr8200_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = usr8200_uart_data, ++ }, ++ .num_resources = 2, ++ .resource = usr8200_uart_resources, ++}; ++ ++static struct gpio_led usr8200_led_pin[] = { ++ { ++ .name = "usr8200:usb1", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "usr8200:usb2", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "usr8200:ieee1394", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "usr8200:internal", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "usr8200:power", ++ .gpio = 14, ++ } ++}; ++ ++static struct gpio_led_platform_data usr8200_led_data = { ++ .num_leds = ARRAY_SIZE(usr8200_led_pin), ++ .leds = usr8200_led_pin, ++}; ++ ++static struct platform_device usr8200_led = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &usr8200_led_data, ++}; ++ ++static struct eth_plat_info usr8200_plat_eth[] = { ++ { /* NPEC - LAN with Marvell 88E6060 switch */ ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x0F0000, ++ .rxq = 4, ++ .txreadyq = 21, ++ }, { /* NPEB - WAN */ ++ .phy = 9, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device usr8200_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = usr8200_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = usr8200_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct resource usr8200_rtc_resources = { ++ .flags = IORESOURCE_MEM ++}; ++ ++static struct platform_device usr8200_rtc = { ++ .name = "rtc7301", ++ .id = 0, ++ .num_resources = 1, ++ .resource = &usr8200_rtc_resources, ++}; ++ ++static struct platform_device *usr8200_devices[] __initdata = { ++ &usr8200_flash, ++ &usr8200_uart, ++ &usr8200_led, ++ &usr8200_eth[0], ++ &usr8200_eth[1], ++ &usr8200_rtc, ++}; ++ ++static void __init usr8200_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ usr8200_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ usr8200_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_16M - 1; ++ ++ usr8200_rtc_resources.start = IXP4XX_EXP_BUS_BASE(2); ++ usr8200_rtc_resources.end = IXP4XX_EXP_BUS_BASE(2) + 0x01ff; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN | ++ IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN; ++ *IXP4XX_GPIO_GPCLKR = 0x01100000; ++ ++ /* configure button as input */ ++ gpio_line_config(12, IXP4XX_GPIO_IN); ++ ++ platform_add_devices(usr8200_devices, ARRAY_SIZE(usr8200_devices)); ++} ++ ++MACHINE_START(USR8200, "USRobotics USR8200") ++ /* Maintainer: Peter Denison */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = usr8200_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END diff --git a/target/linux/ixp4xx/patches-3.18/520-tw2662_support.patch b/target/linux/ixp4xx/patches-3.18/520-tw2662_support.patch new file mode 100644 index 0000000..7cea61f --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/520-tw2662_support.patch @@ -0,0 +1,317 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -176,6 +176,15 @@ config ARCH_PRPMC1100 + PrPCM1100 Processor Mezanine Module. For more information on + this platform, see . + ++config MACH_TW2662 ++ bool "Titan Wireless TW-266-2" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the Titan ++ Wireless TW266-2. For more information on this platform, ++ see http://openwrt.org ++ ++ + config MACH_TW5334 + bool "Titan Wireless TW-533-4" + select PCI +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sid + obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o ++obj-pci-$(CONFIG_MACH_TW2662) += tw2662-pci.o + obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o + obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o + obj-pci-$(CONFIG_MACH_USR8200) += usr8200-pci.o +@@ -54,6 +55,7 @@ obj-$(CONFIG_MACH_SIDEWINDER) += sidewin + obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o ++obj-$(CONFIG_MACH_TW2662) += tw2662-setup.o + obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o + obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o + obj-$(CONFIG_MACH_USR8200) += usr8200-setup.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -45,7 +45,7 @@ static __inline__ void __arch_decomp_set + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro() || + machine_is_wrt300nv2() || machine_is_tw5334() || +- machine_is_usr8200()) ++ machine_is_usr8200() || machine_is_tw2662()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/tw2662-pci.c +@@ -0,0 +1,67 @@ ++/* ++ * arch/arm/mach-ixp4xx/tw2662-pci.c ++ * ++ * PCI setup routines for Tiran Wireless TW-266-2 platform ++ * ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * Copyright (C) 2010 Alexandros C. Couloumbis ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * Maintainer: Deepak Saxena ++ * Maintainer: Alexandros C. Couloumbis ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SLOT0_DEVID 1 ++#define SLOT1_DEVID 3 ++ ++/* PCI controller GPIO to IRQ pin mappings */ ++#define SLOT0_INTA 11 ++#define SLOT1_INTA 9 ++ ++void __init tw2662_pci_preinit(void) ++{ ++ irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init tw2662_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == SLOT0_DEVID) ++ return IXP4XX_GPIO_IRQ(SLOT0_INTA); ++ else if (slot == SLOT1_DEVID) ++ return IXP4XX_GPIO_IRQ(SLOT1_INTA); ++ else return -1; ++} ++ ++struct hw_pci tw2662_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = tw2662_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = tw2662_map_irq, ++}; ++ ++int __init tw2662_pci_init(void) ++{ ++ if (machine_is_tw2662()) ++ pci_common_init(&tw2662_pci); ++ return 0; ++} ++ ++subsys_initcall(tw2662_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/tw2662-setup.c +@@ -0,0 +1,197 @@ ++/* ++ * arch/arm/mach-ixp4xx/tw2662-setup.c ++ * ++ * Titan Wireless TW-266-2 ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * Copyright (C) 2010 Alexandros C. Couloumbis ++ * ++ * based on ap1000-setup.c: ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* gpio mask used by platform device */ ++#define TW2662_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) ++ ++static struct flash_platform_data tw2662_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource tw2662_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device tw2662_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &tw2662_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &tw2662_flash_resource, ++}; ++ ++static struct resource tw2662_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port tw2662_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device tw2662_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = tw2662_uart_data, ++ .num_resources = 2, ++ .resource = tw2662_uart_resources ++}; ++ ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info tw2662_plat_eth[] = { ++ { ++ .phy = 3, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device tw2662_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = tw2662_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = tw2662_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++ ++static struct platform_device *tw2662_devices[] __initdata = { ++ &tw2662_flash, ++ &tw2662_uart, ++ &tw2662_eth[0], ++ &tw2662_eth[1], ++}; ++ ++static char tw2662_mem_fixup[] __initdata = "mem=64M "; ++ ++static void __init tw2662_fixup(struct tag *tags, char **cmdline, ++ struct meminfo *mi) ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(tw2662_mem_fixup) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, tw2662_mem_fixup, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(tw2662_mem_fixup), p, ++ COMMAND_LINE_SIZE - strlen(tw2662_mem_fixup)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ ++static void __init tw2662_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ tw2662_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ tw2662_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ ++ platform_add_devices(tw2662_devices, ARRAY_SIZE(tw2662_devices)); ++ ++ if (!(is_valid_ether_addr(tw2662_plat_eth[0].hwaddr))) ++ random_ether_addr(tw2662_plat_eth[0].hwaddr); ++ if (!(is_valid_ether_addr(tw2662_plat_eth[1].hwaddr))) { ++ memcpy(tw2662_plat_eth[1].hwaddr, tw2662_plat_eth[0].hwaddr, ETH_ALEN); ++ tw2662_plat_eth[1].hwaddr[5] = (tw2662_plat_eth[0].hwaddr[5] + 1); ++ } ++ ++} ++ ++#ifdef CONFIG_MACH_TW2662 ++MACHINE_START(TW2662, "Titan Wireless TW-266-2") ++ /* Maintainer: Alexandros C. Couloumbis */ ++ .fixup = tw2662_fixup, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = tw2662_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-3.18/530-ap42x_support.patch b/target/linux/ixp4xx/patches-3.18/530-ap42x_support.patch new file mode 100644 index 0000000..1afbe3d --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/530-ap42x_support.patch @@ -0,0 +1,282 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -4,6 +4,14 @@ menu "Intel IXP4xx Implementation Option + + comment "IXP4xx Platforms" + ++config MACH_AP42X ++ bool "Tonze AP-422/425" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Tonze's ++ AP-422/425 boards. For more information on this platform, ++ see http://tonze.com.tw ++ + config MACH_NSLU2 + bool + prompt "Linksys NSLU2" +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -5,6 +5,7 @@ + obj-pci-y := + obj-pci-n := + ++obj-pci-$(CONFIG_MACH_AP42X) += ap42x-pci.o + obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o + obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o +@@ -32,6 +33,7 @@ obj-pci-$(CONFIG_MACH_USR8200) += usr82 + + obj-y += common.o + ++obj-$(CONFIG_MACH_AP42X) += ap42x-setup.o + obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o + obj-$(CONFIG_MACH_AVILA) += avila-setup.o + obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/ap42x-pci.c +@@ -0,0 +1,63 @@ ++/* ++ * arch/arch/mach-ixp4xx/ap42x-pci.c ++ * ++ * PCI setup routines for Tonze AP-422/425 ++ * ++ * Copyright (C) 2012 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init ap42x_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init ap42x_map_irq(const struct pci_dev *dev, u8 slot, ++ u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else return -1; ++} ++ ++struct hw_pci ap42x_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = ap42x_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = ap42x_map_irq, ++}; ++ ++int __init ap42x_pci_init(void) ++{ ++ if (machine_is_ap42x()) ++ pci_common_init(&ap42x_pci); ++ return 0; ++} ++ ++subsys_initcall(ap42x_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/ap42x-setup.c +@@ -0,0 +1,166 @@ ++/* ++ * arch/arm/mach-ixp4xx/ap42x-setup.c ++ * ++ * Board setup for the Tonze AP-42x boards ++ * ++ * Copyright (C) 2012 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct mtd_partition ap42x_flash_partitions[] = { ++ { ++ .name = "RedBoot", ++ .offset = 0x00000000, ++ .size = 0x00080000, ++ }, { ++ .name = "linux", ++ .offset = 0x00080000, ++ .size = 0x00100000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x00180000, ++ .size = 0x00660000, ++ }, { ++ .name = "FIS directory", ++ .offset = 0x007f8000, ++ .size = 0x00007000, ++ }, { ++ .name = "RedBoot config", ++ .offset = 0x007ff000, ++ .size = 0x00001000, ++ }, ++}; ++ ++static struct physmap_flash_data ap42x_flash_data = { ++ .width = 2, ++ .parts = ap42x_flash_partitions, ++ .nr_parts = ARRAY_SIZE(ap42x_flash_partitions), ++}; ++ ++static struct resource ap42x_flash_resource = { ++ .flags = IORESOURCE_MEM, ++ .start = IXP4XX_EXP_BUS_BASE_PHYS, ++ .end = IXP4XX_EXP_BUS_BASE_PHYS + SZ_8M - 1, ++}; ++ ++static struct platform_device ap42x_flash = { ++ .name = "physmap-flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &ap42x_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &ap42x_flash_resource, ++}; ++ ++static struct resource ap42x_uart_resource = { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port ap42x_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device ap42x_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = ap42x_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &ap42x_uart_resource, ++}; ++ ++static struct eth_plat_info ap42x_plat_eth[] = { ++ { ++ .phy = 2, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device ap42x_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = ap42x_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = ap42x_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *ap42x_devices[] __initdata = { ++ &ap42x_flash, ++ &ap42x_uart, ++ &ap42x_eth[0], ++ &ap42x_eth[1], ++}; ++ ++static void __init ap42x_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ ap42x_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ ap42x_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(ap42x_devices, ARRAY_SIZE(ap42x_devices)); ++} ++ ++#ifdef CONFIG_MACH_AP42X ++MACHINE_START(AP42X, "Tonze AP-422/425") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x100, ++ .init_machine = ap42x_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -45,7 +45,8 @@ static __inline__ void __arch_decomp_set + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro() || + machine_is_wrt300nv2() || machine_is_tw5334() || +- machine_is_usr8200() || machine_is_tw2662()) ++ machine_is_usr8200() || machine_is_tw2662() || ++ machine_is_ap42x()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; diff --git a/target/linux/ixp4xx/patches-3.18/600-skb_avoid_dmabounce.patch b/target/linux/ixp4xx/patches-3.18/600-skb_avoid_dmabounce.patch new file mode 100644 index 0000000..65b1c1f --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/600-skb_avoid_dmabounce.patch @@ -0,0 +1,23 @@ +--- a/net/core/skbuff.c ++++ b/net/core/skbuff.c +@@ -210,6 +210,9 @@ struct sk_buff *__alloc_skb(unsigned int + + if (sk_memalloc_socks() && (flags & SKB_ALLOC_RX)) + gfp_mask |= __GFP_MEMALLOC; ++#ifdef CONFIG_ARCH_IXP4XX ++ gfp_mask |= GFP_DMA; ++#endif + + /* Get the HEAD */ + skb = kmem_cache_alloc_node(cache, gfp_mask & ~__GFP_DMA, node); +@@ -1096,6 +1099,10 @@ int pskb_expand_head(struct sk_buff *skb + if (skb_shared(skb)) + BUG(); + ++#ifdef CONFIG_ARCH_IXP4XX ++ gfp_mask |= GFP_DMA; ++#endif ++ + size = SKB_DATA_ALIGN(size); + + if (skb_pfmemalloc(skb)) diff --git a/target/linux/ixp4xx/patches-3.18/900-ixp4xx-crypto-include-module.h.patch b/target/linux/ixp4xx/patches-3.18/900-ixp4xx-crypto-include-module.h.patch new file mode 100644 index 0000000..24c93dc --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/900-ixp4xx-crypto-include-module.h.patch @@ -0,0 +1,10 @@ +--- a/drivers/crypto/ixp4xx_crypto.c ++++ b/drivers/crypto/ixp4xx_crypto.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include diff --git a/target/linux/ixp4xx/patches-3.18/910-ixp4xx-nr_irq_lines.patch b/target/linux/ixp4xx/patches-3.18/910-ixp4xx-nr_irq_lines.patch new file mode 100644 index 0000000..06e09f4 --- /dev/null +++ b/target/linux/ixp4xx/patches-3.18/910-ixp4xx-nr_irq_lines.patch @@ -0,0 +1,22 @@ +--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c +@@ -53,7 +53,7 @@ static int __init ixdp425_map_irq(const + }; + + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) +- return pci_irq_table[(slot + pin - 2) % 4]; ++ return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; + + return -1; + } +--- a/arch/arm/mach-ixp4xx/miccpt-pci.c ++++ b/arch/arm/mach-ixp4xx/miccpt-pci.c +@@ -54,7 +54,7 @@ static int __init miccpt_map_irq(const s + }; + + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) +- return pci_irq_table[(slot + pin - 2) % 4]; ++ return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; + + return -1; + } diff --git a/target/linux/ixp4xx/patches-4.1/001-arm-ixp4xx-set-cohorent_dma_mask-for-ethernet-platfo.patch b/target/linux/ixp4xx/patches-4.1/001-arm-ixp4xx-set-cohorent_dma_mask-for-ethernet-platfo.patch new file mode 100644 index 0000000..3ca3eb7 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/001-arm-ixp4xx-set-cohorent_dma_mask-for-ethernet-platfo.patch @@ -0,0 +1,136 @@ +From 7113f56b683c5123df5c20724ac813cee66fa21a Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 1 Jul 2013 16:49:05 +0200 +Subject: [PATCH 1/2] arm: ixp4xx: set cohorent_dma_mask for ethernet platform + devices + +ARM requires the cohorent_dma_mask set, so set it for the platform +devices so that the ethernet driver has access to it. + +Signed-off-by: Jonas Gorski +--- + arch/arm/mach-ixp4xx/fsg-setup.c | 2 ++ + arch/arm/mach-ixp4xx/goramo_mlr.c | 2 ++ + arch/arm/mach-ixp4xx/ixdp425-setup.c | 3 +++ + arch/arm/mach-ixp4xx/nas100d-setup.c | 1 + + arch/arm/mach-ixp4xx/nslu2-setup.c | 1 + + arch/arm/mach-ixp4xx/omixp-setup.c | 3 +++ + arch/arm/mach-ixp4xx/vulcan-setup.c | 2 ++ + 7 files changed, 14 insertions(+) + +--- a/arch/arm/mach-ixp4xx/fsg-setup.c ++++ b/arch/arm/mach-ixp4xx/fsg-setup.c +@@ -142,12 +142,14 @@ static struct platform_device fsg_eth[] + .id = IXP4XX_ETH_NPEB, + .dev = { + .platform_data = fsg_plat_eth, ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev = { + .platform_data = fsg_plat_eth + 1, ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + } + }; +--- a/arch/arm/mach-ixp4xx/goramo_mlr.c ++++ b/arch/arm/mach-ixp4xx/goramo_mlr.c +@@ -295,10 +295,12 @@ static struct platform_device device_eth + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = eth_plat, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = eth_plat + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + } + }; + +--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -196,10 +197,12 @@ static struct platform_device ixdp425_et + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = ixdp425_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = ixdp425_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + } + }; + +--- a/arch/arm/mach-ixp4xx/nas100d-setup.c ++++ b/arch/arm/mach-ixp4xx/nas100d-setup.c +@@ -170,6 +170,7 @@ static struct platform_device nas100d_et + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = nas100d_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + } + }; + +--- a/arch/arm/mach-ixp4xx/nslu2-setup.c ++++ b/arch/arm/mach-ixp4xx/nslu2-setup.c +@@ -182,6 +182,7 @@ static struct platform_device nslu2_eth[ + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = nslu2_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + } + }; + +--- a/arch/arm/mach-ixp4xx/omixp-setup.c ++++ b/arch/arm/mach-ixp4xx/omixp-setup.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -188,10 +189,12 @@ static struct platform_device ixdp425_et + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEB, + .dev.platform_data = ixdp425_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + }, { + .name = "ixp4xx_eth", + .id = IXP4XX_ETH_NPEC, + .dev.platform_data = ixdp425_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), + }, + }; + +--- a/arch/arm/mach-ixp4xx/vulcan-setup.c ++++ b/arch/arm/mach-ixp4xx/vulcan-setup.c +@@ -139,6 +139,7 @@ static struct platform_device vulcan_eth + .id = IXP4XX_ETH_NPEB, + .dev = { + .platform_data = &vulcan_plat_eth[0], ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, + [1] = { +@@ -146,6 +147,7 @@ static struct platform_device vulcan_eth + .id = IXP4XX_ETH_NPEC, + .dev = { + .platform_data = &vulcan_plat_eth[1], ++ .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, + }; diff --git a/target/linux/ixp4xx/patches-4.1/002-ixp4xx_eth-use-parent-device-for-dma-allocations.patch b/target/linux/ixp4xx/patches-4.1/002-ixp4xx_eth-use-parent-device-for-dma-allocations.patch new file mode 100644 index 0000000..ceaf21b --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/002-ixp4xx_eth-use-parent-device-for-dma-allocations.patch @@ -0,0 +1,95 @@ +From 1d67040af0144c549f4db8144d2ccc253ff8639c Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Mon, 1 Jul 2013 16:39:28 +0200 +Subject: [PATCH 2/2] net: ixp4xx_eth: use parent device for dma allocations + +Now that the platfomr device provides a dma_cohorent_mask, use it for +dma operations. + +This fixes ethernet on ixp4xx which was broken since 3.7. + +Signed-off-by: Jonas Gorski +--- + drivers/net/ethernet/xscale/ixp4xx_eth.c | 23 ++++++++++++----------- + 1 file changed, 12 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -657,10 +657,10 @@ static inline void queue_put_desc(unsign + static inline void dma_unmap_tx(struct port *port, struct desc *desc) + { + #ifdef __ARMEB__ +- dma_unmap_single(&port->netdev->dev, desc->data, ++ dma_unmap_single(port->netdev->dev.parent, desc->data, + desc->buf_len, DMA_TO_DEVICE); + #else +- dma_unmap_single(&port->netdev->dev, desc->data & ~3, ++ dma_unmap_single(port->netdev->dev.parent, desc->data & ~3, + ALIGN((desc->data & 3) + desc->buf_len, 4), + DMA_TO_DEVICE); + #endif +@@ -727,9 +727,9 @@ static int eth_poll(struct napi_struct * + + #ifdef __ARMEB__ + if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { +- phys = dma_map_single(&dev->dev, skb->data, ++ phys = dma_map_single(dev->dev.parent, skb->data, + RX_BUFF_SIZE, DMA_FROM_DEVICE); +- if (dma_mapping_error(&dev->dev, phys)) { ++ if (dma_mapping_error(dev->dev.parent, phys)) { + dev_kfree_skb(skb); + skb = NULL; + } +@@ -752,10 +752,11 @@ static int eth_poll(struct napi_struct * + #ifdef __ARMEB__ + temp = skb; + skb = port->rx_buff_tab[n]; +- dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, ++ dma_unmap_single(dev->dev.parent, desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + #else +- dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, ++ dma_sync_single_for_cpu(dev->dev.parent, ++ desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], + ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); +@@ -874,7 +875,7 @@ static int eth_xmit(struct sk_buff *skb, + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); + #endif + +- phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); ++ phys = dma_map_single(dev->dev.parent, mem, bytes, DMA_TO_DEVICE); + if (dma_mapping_error(&dev->dev, phys)) { + dev_kfree_skb(skb); + #ifndef __ARMEB__ +@@ -1124,7 +1125,7 @@ static int init_queues(struct port *port + int i; + + if (!ports_open) { +- dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, ++ dma_pool = dma_pool_create(DRV_NAME, port->netdev->dev.parent, + POOL_ALLOC_SIZE, 32, 0); + if (!dma_pool) + return -ENOMEM; +@@ -1152,9 +1153,9 @@ static int init_queues(struct port *port + data = buff; + #endif + desc->buf_len = MAX_MRU; +- desc->data = dma_map_single(&port->netdev->dev, data, ++ desc->data = dma_map_single(port->netdev->dev.parent, data, + RX_BUFF_SIZE, DMA_FROM_DEVICE); +- if (dma_mapping_error(&port->netdev->dev, desc->data)) { ++ if (dma_mapping_error(port->netdev->dev.parent, desc->data)) { + free_buffer(buff); + return -EIO; + } +@@ -1174,7 +1175,7 @@ static void destroy_queues(struct port * + struct desc *desc = rx_desc_ptr(port, i); + buffer_t *buff = port->rx_buff_tab[i]; + if (buff) { +- dma_unmap_single(&port->netdev->dev, ++ dma_unmap_single(port->netdev->dev.parent, + desc->data - NET_IP_ALIGN, + RX_BUFF_SIZE, DMA_FROM_DEVICE); + free_buffer(buff); diff --git a/target/linux/ixp4xx/patches-4.1/020-gateworks_i2c_pld.patch b/target/linux/ixp4xx/patches-4.1/020-gateworks_i2c_pld.patch new file mode 100644 index 0000000..09b7f42 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/020-gateworks_i2c_pld.patch @@ -0,0 +1,421 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -647,6 +647,14 @@ config GPIO_SX150X + 8 bits: sx1508q + 16 bits: sx1509q + ++config GPIO_GW_I2C_PLD ++ tristate "Gateworks I2C PLD GPIO Expander" ++ depends on I2C ++ help ++ Say yes here to provide access to the Gateworks I2C PLD GPIO ++ Expander. This is used at least on the GW2358-4. ++ ++ + endmenu + + menu "MFD GPIO expanders" +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -112,3 +112,4 @@ obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx + obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o + obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o + obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o ++obj-$(CONFIG_GPIO_GW_I2C_PLD) += gw_i2c_pld.o +--- /dev/null ++++ b/drivers/gpio/gw_i2c_pld.c +@@ -0,0 +1,371 @@ ++/* ++ * Gateworks I2C PLD GPIO expander ++ * ++ * Copyright (C) 2009 Gateworks Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const struct i2c_device_id gw_i2c_pld_id[] = { ++ { "gw_i2c_pld", 8 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, gw_i2c_pld_id); ++ ++/* ++ * The Gateworks I2C PLD chip only expose one read and one ++ * write register. Writing a "one" bit (to match the reset state) lets ++ * that pin be used as an input. It is an open-drain model. ++ */ ++ ++struct gw_i2c_pld { ++ struct gpio_chip chip; ++ struct i2c_client *client; ++ unsigned out; /* software latch */ ++}; ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * The Gateworks I2C PLD chip does not properly send the acknowledge bit ++ * thus we cannot use standard i2c_smbus functions. We have recreated ++ * our own here, but we still use the rt_mutex_lock to lock the i2c_bus ++ * as the device still exists on the I2C bus. ++*/ ++ ++#define PLD_SCL_GPIO 6 ++#define PLD_SDA_GPIO 7 ++ ++#define SCL_LO() gpio_line_set(PLD_SCL_GPIO, IXP4XX_GPIO_LOW) ++#define SCL_HI() gpio_line_set(PLD_SCL_GPIO, IXP4XX_GPIO_HIGH) ++#define SCL_EN() gpio_line_config(PLD_SCL_GPIO, IXP4XX_GPIO_OUT) ++#define SDA_LO() gpio_line_set(PLD_SDA_GPIO, IXP4XX_GPIO_LOW) ++#define SDA_HI() gpio_line_set(PLD_SDA_GPIO, IXP4XX_GPIO_HIGH) ++#define SDA_EN() gpio_line_config(PLD_SDA_GPIO, IXP4XX_GPIO_OUT) ++#define SDA_DIS() gpio_line_config(PLD_SDA_GPIO, IXP4XX_GPIO_IN) ++#define SDA_IN(x) gpio_line_get(PLD_SDA_GPIO, &x); ++ ++static int i2c_pld_write_byte(int address, int byte) ++{ ++ int i; ++ ++ address = (address << 1) & ~0x1; ++ ++ SDA_HI(); ++ SDA_EN(); ++ SCL_EN(); ++ SCL_HI(); ++ SDA_LO(); ++ SCL_LO(); ++ ++ for (i = 7; i >= 0; i--) ++ { ++ if (address & (1 << i)) ++ SDA_HI(); ++ else ++ SDA_LO(); ++ ++ SCL_HI(); ++ SCL_LO(); ++ } ++ ++ SDA_DIS(); ++ SCL_HI(); ++ SDA_IN(i); ++ SCL_LO(); ++ SDA_EN(); ++ ++ for (i = 7; i >= 0; i--) ++ { ++ if (byte & (1 << i)) ++ SDA_HI(); ++ else ++ SDA_LO(); ++ SCL_HI(); ++ SCL_LO(); ++ } ++ ++ SDA_DIS(); ++ SCL_HI(); ++ SDA_IN(i); ++ SCL_LO(); ++ ++ SDA_HI(); ++ SDA_EN(); ++ ++ SDA_LO(); ++ SCL_HI(); ++ SDA_HI(); ++ SCL_LO(); ++ SCL_HI(); ++ ++ return 0; ++} ++ ++static unsigned int i2c_pld_read_byte(int address) ++{ ++ int i = 0, byte = 0; ++ int bit; ++ ++ address = (address << 1) | 0x1; ++ ++ SDA_HI(); ++ SDA_EN(); ++ SCL_EN(); ++ SCL_HI(); ++ SDA_LO(); ++ SCL_LO(); ++ ++ for (i = 7; i >= 0; i--) ++ { ++ if (address & (1 << i)) ++ SDA_HI(); ++ else ++ SDA_LO(); ++ ++ SCL_HI(); ++ SCL_LO(); ++ } ++ ++ SDA_DIS(); ++ SCL_HI(); ++ SDA_IN(i); ++ SCL_LO(); ++ SDA_EN(); ++ ++ SDA_DIS(); ++ for (i = 7; i >= 0; i--) ++ { ++ SCL_HI(); ++ SDA_IN(bit); ++ byte |= bit << i; ++ SCL_LO(); ++ } ++ ++ SDA_LO(); ++ SCL_HI(); ++ SDA_HI(); ++ SCL_LO(); ++ SCL_HI(); ++ ++ return byte; ++} ++ ++ ++static int gw_i2c_pld_input8(struct gpio_chip *chip, unsigned offset) ++{ ++ int ret; ++ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip); ++ struct i2c_adapter *adap = gpio->client->adapter; ++ ++ if (in_atomic() || irqs_disabled()) { ++ ret = rt_mutex_trylock(&adap->bus_lock); ++ if (!ret) ++ /* I2C activity is ongoing. */ ++ return -EAGAIN; ++ } else { ++ rt_mutex_lock(&adap->bus_lock); ++ } ++ ++ gpio->out |= (1 << offset); ++ ++ ret = i2c_pld_write_byte(gpio->client->addr, gpio->out); ++ ++ rt_mutex_unlock(&adap->bus_lock); ++ ++ return ret; ++} ++ ++static int gw_i2c_pld_get8(struct gpio_chip *chip, unsigned offset) ++{ ++ int ret; ++ s32 value; ++ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip); ++ struct i2c_adapter *adap = gpio->client->adapter; ++ ++ if (in_atomic() || irqs_disabled()) { ++ ret = rt_mutex_trylock(&adap->bus_lock); ++ if (!ret) ++ /* I2C activity is ongoing. */ ++ return -EAGAIN; ++ } else { ++ rt_mutex_lock(&adap->bus_lock); ++ } ++ ++ value = i2c_pld_read_byte(gpio->client->addr); ++ ++ rt_mutex_unlock(&adap->bus_lock); ++ ++ return (value < 0) ? 0 : (value & (1 << offset)); ++} ++ ++static int gw_i2c_pld_output8(struct gpio_chip *chip, unsigned offset, int value) ++{ ++ int ret; ++ ++ struct gw_i2c_pld *gpio = container_of(chip, struct gw_i2c_pld, chip); ++ struct i2c_adapter *adap = gpio->client->adapter; ++ ++ unsigned bit = 1 << offset; ++ ++ if (in_atomic() || irqs_disabled()) { ++ ret = rt_mutex_trylock(&adap->bus_lock); ++ if (!ret) ++ /* I2C activity is ongoing. */ ++ return -EAGAIN; ++ } else { ++ rt_mutex_lock(&adap->bus_lock); ++ } ++ ++ ++ if (value) ++ gpio->out |= bit; ++ else ++ gpio->out &= ~bit; ++ ++ ret = i2c_pld_write_byte(gpio->client->addr, gpio->out); ++ ++ rt_mutex_unlock(&adap->bus_lock); ++ ++ return ret; ++} ++ ++static void gw_i2c_pld_set8(struct gpio_chip *chip, unsigned offset, int value) ++{ ++ gw_i2c_pld_output8(chip, offset, value); ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int gw_i2c_pld_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct gw_i2c_pld_platform_data *pdata; ++ struct gw_i2c_pld *gpio; ++ int status; ++ ++ pdata = client->dev.platform_data; ++ if (!pdata) ++ return -ENODEV; ++ ++ /* Allocate, initialize, and register this gpio_chip. */ ++ gpio = kzalloc(sizeof *gpio, GFP_KERNEL); ++ if (!gpio) ++ return -ENOMEM; ++ ++ gpio->chip.base = pdata->gpio_base; ++ gpio->chip.can_sleep = 1; ++ gpio->chip.dev = &client->dev; ++ gpio->chip.owner = THIS_MODULE; ++ ++ gpio->chip.ngpio = pdata->nr_gpio; ++ gpio->chip.direction_input = gw_i2c_pld_input8; ++ gpio->chip.get = gw_i2c_pld_get8; ++ gpio->chip.direction_output = gw_i2c_pld_output8; ++ gpio->chip.set = gw_i2c_pld_set8; ++ ++ gpio->chip.label = client->name; ++ ++ gpio->client = client; ++ i2c_set_clientdata(client, gpio); ++ ++ gpio->out = 0xFF; ++ ++ status = gpiochip_add(&gpio->chip); ++ if (status < 0) ++ goto fail; ++ ++ dev_info(&client->dev, "gpios %d..%d on a %s%s\n", ++ gpio->chip.base, ++ gpio->chip.base + gpio->chip.ngpio - 1, ++ client->name, ++ client->irq ? " (irq ignored)" : ""); ++ ++ /* Let platform code set up the GPIOs and their users. ++ * Now is the first time anyone could use them. ++ */ ++ if (pdata->setup) { ++ status = pdata->setup(client, ++ gpio->chip.base, gpio->chip.ngpio, ++ pdata->context); ++ if (status < 0) ++ dev_warn(&client->dev, "setup --> %d\n", status); ++ } ++ ++ return 0; ++ ++fail: ++ dev_dbg(&client->dev, "probe error %d for '%s'\n", ++ status, client->name); ++ kfree(gpio); ++ return status; ++} ++ ++static int gw_i2c_pld_remove(struct i2c_client *client) ++{ ++ struct gw_i2c_pld_platform_data *pdata = client->dev.platform_data; ++ struct gw_i2c_pld *gpio = i2c_get_clientdata(client); ++ int status = 0; ++ ++ if (pdata->teardown) { ++ status = pdata->teardown(client, ++ gpio->chip.base, gpio->chip.ngpio, ++ pdata->context); ++ if (status < 0) { ++ dev_err(&client->dev, "%s --> %d\n", ++ "teardown", status); ++ return status; ++ } ++ } ++ ++ gpiochip_remove(&gpio->chip); ++ kfree(gpio); ++ return 0; ++} ++ ++static struct i2c_driver gw_i2c_pld_driver = { ++ .driver = { ++ .name = "gw_i2c_pld", ++ .owner = THIS_MODULE, ++ }, ++ .probe = gw_i2c_pld_probe, ++ .remove = gw_i2c_pld_remove, ++ .id_table = gw_i2c_pld_id, ++}; ++ ++static int __init gw_i2c_pld_init(void) ++{ ++ return i2c_add_driver(&gw_i2c_pld_driver); ++} ++module_init(gw_i2c_pld_init); ++ ++static void __exit gw_i2c_pld_exit(void) ++{ ++ i2c_del_driver(&gw_i2c_pld_driver); ++} ++module_exit(gw_i2c_pld_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chris Lang"); +--- /dev/null ++++ b/include/linux/i2c/gw_i2c_pld.h +@@ -0,0 +1,20 @@ ++#ifndef __LINUX_GW_I2C_PLD_H ++#define __LINUX_GW_I2C_PLD_H ++ ++/** ++ * The Gateworks I2C PLD Implements an additional 8 bits of GPIO through the PLD ++ */ ++ ++struct gw_i2c_pld_platform_data { ++ unsigned gpio_base; ++ unsigned nr_gpio; ++ int (*setup)(struct i2c_client *client, ++ int gpio, unsigned ngpio, ++ void *context); ++ int (*teardown)(struct i2c_client *client, ++ int gpio, unsigned ngpio, ++ void *context); ++ void *context; ++}; ++ ++#endif /* __LINUX_GW_I2C_PLD_H */ diff --git a/target/linux/ixp4xx/patches-4.1/030-gpio_line_config.patch b/target/linux/ixp4xx/patches-4.1/030-gpio_line_config.patch new file mode 100644 index 0000000..0e51793 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/030-gpio_line_config.patch @@ -0,0 +1,73 @@ +--- a/arch/arm/mach-ixp4xx/common.c ++++ b/arch/arm/mach-ixp4xx/common.c +@@ -93,22 +93,7 @@ void __init ixp4xx_map_io(void) + /* + * GPIO-functions + */ +-/* +- * The following converted to the real HW bits the gpio_line_config +- */ +-/* GPIO pin types */ +-#define IXP4XX_GPIO_OUT 0x1 +-#define IXP4XX_GPIO_IN 0x2 +- +-/* GPIO signal types */ +-#define IXP4XX_GPIO_LOW 0 +-#define IXP4XX_GPIO_HIGH 1 +- +-/* GPIO Clocks */ +-#define IXP4XX_GPIO_CLK_0 14 +-#define IXP4XX_GPIO_CLK_1 15 +- +-static void gpio_line_config(u8 line, u32 direction) ++void gpio_line_config(u8 line, u32 direction) + { + if (direction == IXP4XX_GPIO_IN) + *IXP4XX_GPIO_GPOER |= (1 << line); +@@ -116,17 +101,17 @@ static void gpio_line_config(u8 line, u3 + *IXP4XX_GPIO_GPOER &= ~(1 << line); + } + +-static void gpio_line_get(u8 line, int *value) ++void gpio_line_get(u8 line, int *value) + { + *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1; + } + +-static void gpio_line_set(u8 line, int value) ++void gpio_line_set(u8 line, int value) + { +- if (value == IXP4XX_GPIO_HIGH) +- *IXP4XX_GPIO_GPOUTR |= (1 << line); +- else if (value == IXP4XX_GPIO_LOW) ++ if (value == IXP4XX_GPIO_LOW) + *IXP4XX_GPIO_GPOUTR &= ~(1 << line); ++ else ++ *IXP4XX_GPIO_GPOUTR |= (1 << line); + } + + /************************************************************************* +--- a/arch/arm/mach-ixp4xx/include/mach/platform.h ++++ b/arch/arm/mach-ixp4xx/include/mach/platform.h +@@ -131,5 +131,21 @@ struct pci_sys_data; + extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); + extern struct pci_ops ixp4xx_ops; + ++/* GPIO pin types */ ++#define IXP4XX_GPIO_OUT 0x1 ++#define IXP4XX_GPIO_IN 0x2 ++ ++/* GPIO signal types */ ++#define IXP4XX_GPIO_LOW 0 ++#define IXP4XX_GPIO_HIGH 1 ++ ++/* GPIO Clocks */ ++#define IXP4XX_GPIO_CLK_0 14 ++#define IXP4XX_GPIO_CLK_1 15 ++ ++void gpio_line_config(u8 line, u32 direction); ++void gpio_line_get(u8 line, int *value); ++void gpio_line_set(u8 line, int value); ++ + #endif // __ASSEMBLY__ + diff --git a/target/linux/ixp4xx/patches-4.1/090-increase_entropy_pools.patch b/target/linux/ixp4xx/patches-4.1/090-increase_entropy_pools.patch new file mode 100644 index 0000000..285505c --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/090-increase_entropy_pools.patch @@ -0,0 +1,17 @@ +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -285,11 +285,11 @@ + /* + * Configuration information + */ +-#define INPUT_POOL_SHIFT 12 ++#define INPUT_POOL_SHIFT 13 + #define INPUT_POOL_WORDS (1 << (INPUT_POOL_SHIFT-5)) +-#define OUTPUT_POOL_SHIFT 10 ++#define OUTPUT_POOL_SHIFT 11 + #define OUTPUT_POOL_WORDS (1 << (OUTPUT_POOL_SHIFT-5)) +-#define SEC_XFER_SIZE 512 ++#define SEC_XFER_SIZE 1024 + #define EXTRACT_SIZE 10 + + #define DEBUG_RANDOM_BOOT 0 diff --git a/target/linux/ixp4xx/patches-4.1/100-wg302v2_gateway7001_mac_plat_info.patch b/target/linux/ixp4xx/patches-4.1/100-wg302v2_gateway7001_mac_plat_info.patch new file mode 100644 index 0000000..317103f --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/100-wg302v2_gateway7001_mac_plat_info.patch @@ -0,0 +1,78 @@ +--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c ++++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -75,9 +76,37 @@ static struct platform_device gateway700 + .resource = &gateway7001_uart_resource, + }; + ++static struct eth_plat_info gateway7001_plat_eth[] = { ++ { ++ .phy = 1, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 2, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device gateway7001_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = gateway7001_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = gateway7001_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ + static struct platform_device *gateway7001_devices[] __initdata = { + &gateway7001_flash, +- &gateway7001_uart ++ &gateway7001_uart, ++ &gateway7001_eth[0], ++ &gateway7001_eth[1], + }; + + static void __init gateway7001_init(void) +--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c ++++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c +@@ -76,9 +76,26 @@ static struct platform_device wg302v2_ua + .resource = &wg302v2_uart_resource, + }; + ++static struct eth_plat_info wg302v2_plat_eth[] = { ++ { ++ .phy = 8, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device wg302v2_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wg302v2_plat_eth, ++ } ++}; ++ + static struct platform_device *wg302v2_devices[] __initdata = { + &wg302v2_flash, + &wg302v2_uart, ++ &wg302v2_eth[0], + }; + + static void __init wg302v2_init(void) diff --git a/target/linux/ixp4xx/patches-4.1/105-wg302v1_support.patch b/target/linux/ixp4xx/patches-4.1/105-wg302v1_support.patch new file mode 100644 index 0000000..8793549 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/105-wg302v1_support.patch @@ -0,0 +1,261 @@ +--- a/arch/arm/configs/ixp4xx_defconfig ++++ b/arch/arm/configs/ixp4xx_defconfig +@@ -13,6 +13,7 @@ CONFIG_MACH_AVILA=y + CONFIG_MACH_LOFT=y + CONFIG_ARCH_ADI_COYOTE=y + CONFIG_MACH_GATEWAY7001=y ++CONFIG_MACH_WG302V1=y + CONFIG_MACH_WG302V2=y + CONFIG_ARCH_IXDP425=y + CONFIG_MACH_IXDPG425=y +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -45,6 +45,14 @@ config MACH_GATEWAY7001 + 7001 Access Point. For more information on this platform, + see http://openwrt.org + ++config MACH_WG302V1 ++ bool "Netgear WG302 v1 / WAG302 v1" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Netgear's ++ WG302 v1 or WAG302 v1 Access Points. For more information ++ on this platform, see http://openwrt.org ++ + config MACH_WG302V2 + bool "Netgear WG302 v2 / WAG302 v2" + select PCI +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -15,6 +15,7 @@ obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-p + obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o + obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o + obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o ++obj-pci-$(CONFIG_MACH_WG302V1) += wg302v1-pci.o + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o +@@ -33,6 +34,7 @@ obj-$(CONFIG_MACH_NSLU2) += nslu2-setup. + obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o + obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o + obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o ++obj-$(CONFIG_MACH_WG302V1) += wg302v1-setup.o + obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o + obj-$(CONFIG_MACH_FSG) += fsg-setup.o + obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/wg302v1-pci.c +@@ -0,0 +1,63 @@ ++/* ++ * arch/arch/mach-ixp4xx/wg302v1-pci.c ++ * ++ * PCI setup routines for the Netgear WG302 v1 and WAG302 v1 ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Software, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init wg302v1_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init wg302v1_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO8; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else ++ return -1; ++} ++ ++struct hw_pci wg302v1_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = wg302v1_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = wg302v1_map_irq, ++}; ++ ++int __init wg302v1_pci_init(void) ++{ ++ if (machine_is_wg302v1()) ++ pci_common_init(&wg302v1_pci); ++ return 0; ++} ++ ++subsys_initcall(wg302v1_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c +@@ -0,0 +1,147 @@ ++/* ++ * arch/arm/mach-ixp4xx/wg302v1-setup.c ++ * ++ * Board setup for the Netgear WG302 v1 and WAG302 v1 ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data wg302v1_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource wg302v1_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device wg302v1_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &wg302v1_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &wg302v1_flash_resource, ++}; ++ ++static struct resource wg302v1_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct plat_serial8250_port wg302v1_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device wg302v1_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = wg302v1_uart_data, ++ }, ++ .num_resources = 2, ++ .resource = wg302v1_uart_resources, ++}; ++ ++static struct eth_plat_info wg302v1_plat_eth[] = { ++ { ++ .phy = 30, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device wg302v1_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wg302v1_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *wg302v1_devices[] __initdata = { ++ &wg302v1_flash, ++ &wg302v1_uart, ++ &wg302v1_eth[0], ++}; ++ ++static void __init wg302v1_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ wg302v1_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ wg302v1_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(wg302v1_devices, ARRAY_SIZE(wg302v1_devices)); ++} ++ ++#ifdef CONFIG_MACH_WG302V1 ++MACHINE_START(WG302V1, "Netgear WG302 v1 / WAG302 v1") ++ /* Maintainer: Imre Kaloz */ ++ .fixup = wg302v1_fixup, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = wg302v1_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-4.1/110-pronghorn_series_support.patch b/target/linux/ixp4xx/patches-4.1/110-pronghorn_series_support.patch new file mode 100644 index 0000000..d1fdfcb --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/110-pronghorn_series_support.patch @@ -0,0 +1,393 @@ +--- a/arch/arm/configs/ixp4xx_defconfig ++++ b/arch/arm/configs/ixp4xx_defconfig +@@ -15,6 +15,8 @@ CONFIG_ARCH_ADI_COYOTE=y + CONFIG_MACH_GATEWAY7001=y + CONFIG_MACH_WG302V1=y + CONFIG_MACH_WG302V2=y ++CONFIG_MACH_PRONGHORN=y ++CONFIG_MACH_PRONGHORNMETRO=y + CONFIG_ARCH_IXDP425=y + CONFIG_MACH_IXDPG425=y + CONFIG_MACH_IXDP465=y +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -61,6 +61,22 @@ config MACH_WG302V2 + WG302 v2 or WAG302 v2 Access Points. For more information + on this platform, see http://openwrt.org + ++config MACH_PRONGHORN ++ bool "ADI Pronghorn series" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the ADI ++ Engineering Pronghorn series. For more ++ information on this platform, see http://www.adiengineering.com ++ ++# ++# There're only minimal differences kernel-wise between the Pronghorn and ++# Pronghorn Metro boards - they use different chip selects to drive the ++# CF slot connected to the expansion bus, so we just enable them together. ++# ++config MACH_PRONGHORNMETRO ++ def_bool MACH_PRONGHORN ++ + config ARCH_IXDP425 + bool "IXDP425" + help +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -19,6 +19,7 @@ obj-pci-$(CONFIG_MACH_WG302V1) += wg302 + obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o ++obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o + + obj-y += common.o + +@@ -39,6 +40,7 @@ obj-$(CONFIG_MACH_WG302V2) += wg302v2-se + obj-$(CONFIG_MACH_FSG) += fsg-setup.o + obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o + obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o ++obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -42,7 +42,8 @@ static __inline__ void __arch_decomp_set + */ + if (machine_is_adi_coyote() || machine_is_gtwx5715() || + machine_is_gateway7001() || machine_is_wg302v2() || +- machine_is_devixp() || machine_is_miccpt() || machine_is_mic256()) ++ machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || ++ machine_is_pronghorn() || machine_is_pronghorn_metro()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/pronghorn-pci.c +@@ -0,0 +1,69 @@ ++/* ++ * arch/arch/mach-ixp4xx/pronghorn-pci.c ++ * ++ * PCI setup routines for ADI Engineering Pronghorn series ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init pronghorn_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init pronghorn_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 13) ++ return IRQ_IXP4XX_GPIO4; ++ else if (slot == 14) ++ return IRQ_IXP4XX_GPIO6; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 16) ++ return IRQ_IXP4XX_GPIO1; ++ else ++ return -1; ++} ++ ++struct hw_pci pronghorn_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = pronghorn_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = pronghorn_map_irq, ++}; ++ ++int __init pronghorn_pci_init(void) ++{ ++ if (machine_is_pronghorn() || machine_is_pronghorn_metro()) ++ pci_common_init(&pronghorn_pci); ++ return 0; ++} ++ ++subsys_initcall(pronghorn_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c +@@ -0,0 +1,252 @@ ++/* ++ * arch/arm/mach-ixp4xx/pronghorn-setup.c ++ * ++ * Board setup for the ADI Engineering Pronghorn series ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data pronghorn_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource pronghorn_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device pronghorn_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &pronghorn_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &pronghorn_flash_resource, ++}; ++ ++static struct resource pronghorn_uart_resources [] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port pronghorn_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device pronghorn_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = pronghorn_uart_data, ++ }, ++ .num_resources = 2, ++ .resource = pronghorn_uart_resources, ++}; ++ ++static struct i2c_gpio_platform_data pronghorn_i2c_gpio_data = { ++ .sda_pin = 9, ++ .scl_pin = 10, ++}; ++ ++static struct platform_device pronghorn_i2c_gpio = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &pronghorn_i2c_gpio_data, ++ }, ++}; ++ ++static struct gpio_led pronghorn_led_pin[] = { ++ { ++ .name = "pronghorn:green:status", ++ .gpio = 7, ++ } ++}; ++ ++static struct gpio_led_platform_data pronghorn_led_data = { ++ .num_leds = 1, ++ .leds = pronghorn_led_pin, ++}; ++ ++static struct platform_device pronghorn_led = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &pronghorn_led_data, ++}; ++ ++static struct resource pronghorn_pata_resources[] = { ++ { ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "intrq", ++ .start = IRQ_IXP4XX_GPIO0, ++ .end = IRQ_IXP4XX_GPIO0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct ixp4xx_pata_data pronghorn_pata_data = { ++ .cs0_bits = 0xbfff0043, ++ .cs1_bits = 0xbfff0043, ++}; ++ ++static struct platform_device pronghorn_pata = { ++ .name = "pata_ixp4xx_cf", ++ .id = 0, ++ .dev.platform_data = &pronghorn_pata_data, ++ .num_resources = ARRAY_SIZE(pronghorn_pata_resources), ++ .resource = pronghorn_pata_resources, ++}; ++ ++static struct eth_plat_info pronghorn_plat_eth[] = { ++ { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device pronghorn_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = pronghorn_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = pronghorn_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *pronghorn_devices[] __initdata = { ++ &pronghorn_flash, ++ &pronghorn_uart, ++ &pronghorn_led, ++ &pronghorn_eth[0], ++ &pronghorn_eth[1], ++}; ++ ++static void __init pronghorn_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ pronghorn_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ pronghorn_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(pronghorn_devices, ARRAY_SIZE(pronghorn_devices)); ++ ++ if (machine_is_pronghorn()) { ++ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(2); ++ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(2); ++ ++ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(3); ++ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(3); ++ ++ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS2; ++ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS3; ++ } else { ++ pronghorn_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(3); ++ pronghorn_pata_resources[0].end = IXP4XX_EXP_BUS_END(3); ++ ++ pronghorn_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(4); ++ pronghorn_pata_resources[1].end = IXP4XX_EXP_BUS_END(4); ++ ++ pronghorn_pata_data.cs0_cfg = IXP4XX_EXP_CS3; ++ pronghorn_pata_data.cs1_cfg = IXP4XX_EXP_CS4; ++ ++ platform_device_register(&pronghorn_i2c_gpio); ++ } ++ ++ platform_device_register(&pronghorn_pata); ++} ++ ++MACHINE_START(PRONGHORN, "ADI Engineering Pronghorn") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = pronghorn_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++ ++MACHINE_START(PRONGHORNMETRO, "ADI Engineering Pronghorn Metro") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = pronghorn_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END diff --git a/target/linux/ixp4xx/patches-4.1/111-pronghorn_swap_uarts.patch b/target/linux/ixp4xx/patches-4.1/111-pronghorn_swap_uarts.patch new file mode 100644 index 0000000..ed9f7a7 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/111-pronghorn_swap_uarts.patch @@ -0,0 +1,44 @@ +--- a/arch/arm/mach-ixp4xx/pronghorn-setup.c ++++ b/arch/arm/mach-ixp4xx/pronghorn-setup.c +@@ -52,31 +52,31 @@ static struct platform_device pronghorn_ + + static struct resource pronghorn_uart_resources [] = { + { +- .start = IXP4XX_UART1_BASE_PHYS, +- .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM + }, + { +- .start = IXP4XX_UART2_BASE_PHYS, +- .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, + .flags = IORESOURCE_MEM + } + }; + + static struct plat_serial8250_port pronghorn_uart_data[] = { + { +- .mapbase = IXP4XX_UART1_BASE_PHYS, +- .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, +- .irq = IRQ_IXP4XX_UART1, ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = IXP4XX_UART_XTAL, + }, + { +- .mapbase = IXP4XX_UART2_BASE_PHYS, +- .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, +- .irq = IRQ_IXP4XX_UART2, ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, diff --git a/target/linux/ixp4xx/patches-4.1/115-sidewinder_support.patch b/target/linux/ixp4xx/patches-4.1/115-sidewinder_support.patch new file mode 100644 index 0000000..20adbb5 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/115-sidewinder_support.patch @@ -0,0 +1,286 @@ +From 95dac4a842a3c66f69f949b48f9075e16275f77b Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Jun 2013 15:48:47 +0200 +Subject: [PATCH 07/36] 115-sidewinder_support.patch + +--- + arch/arm/mach-ixp4xx/Kconfig | 10 +- + arch/arm/mach-ixp4xx/Makefile | 2 + + arch/arm/mach-ixp4xx/sidewinder-pci.c | 68 ++++++++++++++ + arch/arm/mach-ixp4xx/sidewinder-setup.c | 151 +++++++++++++++++++++++++++++++ + 4 files changed, 230 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/mach-ixp4xx/sidewinder-pci.c + create mode 100644 arch/arm/mach-ixp4xx/sidewinder-setup.c + +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -77,6 +77,14 @@ config MACH_PRONGHORN + config MACH_PRONGHORNMETRO + def_bool MACH_PRONGHORN + ++config MACH_SIDEWINDER ++ bool "ADI Sidewinder" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the ADI ++ Engineering Sidewinder board. For more information on this ++ platform, see http://www.adiengineering.com ++ + config ARCH_IXDP425 + bool "IXDP425" + help +@@ -173,7 +181,7 @@ config MACH_ARCOM_VULCAN + # + config CPU_IXP46X + bool +- depends on MACH_IXDP465 ++ depends on MACH_IXDP465 || MACH_SIDEWINDER + default y + + config CPU_IXP43X +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -20,6 +20,7 @@ obj-pci-$(CONFIG_MACH_WG302V2) += wg302 + obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o + obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o ++obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o + + obj-y += common.o + +@@ -41,6 +42,7 @@ obj-$(CONFIG_MACH_FSG) += fsg-setup.o + obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o + obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o + obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o ++obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/sidewinder-pci.c +@@ -0,0 +1,67 @@ ++/* ++ * arch/arch/mach-ixp4xx/pronghornmetro-pci.c ++ * ++ * PCI setup routines for ADI Engineering Sidewinder ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++void __init sidewinder_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init sidewinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else if (slot == 3) ++ return IRQ_IXP4XX_GPIO9; ++ else ++ return -1; ++} ++ ++struct hw_pci sidewinder_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = sidewinder_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = sidewinder_map_irq, ++}; ++ ++int __init sidewinder_pci_init(void) ++{ ++ if (machine_is_sidewinder()) ++ pci_common_init(&sidewinder_pci); ++ return 0; ++} ++ ++subsys_initcall(sidewinder_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/sidewinder-setup.c +@@ -0,0 +1,155 @@ ++/* ++ * arch/arm/mach-ixp4xx/sidewinder-setup.c ++ * ++ * Board setup for the ADI Engineering Sidewinder ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++static struct flash_platform_data sidewinder_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource sidewinder_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device sidewinder_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &sidewinder_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &sidewinder_flash_resource, ++}; ++ ++static struct resource sidewinder_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct plat_serial8250_port sidewinder_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device sidewinder_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = sidewinder_uart_data, ++ }, ++ .num_resources = ARRAY_SIZE(sidewinder_uart_resources), ++ .resource = sidewinder_uart_resources, ++}; ++ ++static struct eth_plat_info sidewinder_plat_eth[] = { ++ { ++ .phy = 5, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, ++ .rxq = 4, ++ .txreadyq = 21, ++ }, { ++ .phy = 31, ++ .rxq = 2, ++ .txreadyq = 19, ++ } ++}; ++ ++static struct platform_device sidewinder_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = sidewinder_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = sidewinder_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEA, ++ .dev.platform_data = sidewinder_plat_eth + 2, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *sidewinder_devices[] __initdata = { ++ &sidewinder_flash, ++ &sidewinder_uart, ++ &sidewinder_eth[0], ++ &sidewinder_eth[1], ++ &sidewinder_eth[2], ++}; ++ ++static void __init sidewinder_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ sidewinder_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ sidewinder_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_64M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(sidewinder_devices, ARRAY_SIZE(sidewinder_devices)); ++} ++ ++MACHINE_START(SIDEWINDER, "ADI Engineering Sidewinder") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = sidewinder_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END diff --git a/target/linux/ixp4xx/patches-4.1/116-sidewinder_fis_location.patch b/target/linux/ixp4xx/patches-4.1/116-sidewinder_fis_location.patch new file mode 100644 index 0000000..7d633f7 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/116-sidewinder_fis_location.patch @@ -0,0 +1,30 @@ +--- a/drivers/mtd/redboot.c ++++ b/drivers/mtd/redboot.c +@@ -30,6 +30,8 @@ + #include + #include + ++#include ++ + struct fis_image_desc { + unsigned char name[16]; // Null terminated name + uint32_t flash_base; // Address within FLASH of image +@@ -47,7 +49,8 @@ struct fis_list { + struct fis_list *next; + }; + +-static int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK; ++int directory = CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK; ++ + module_param(directory, int, 0); + + static inline int redboot_checksum(struct fis_image_desc *img) +@@ -75,6 +78,8 @@ static int parse_redboot_partitions(stru + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif ++ if (machine_is_sidewinder()) ++ directory = -5; + + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; diff --git a/target/linux/ixp4xx/patches-4.1/120-compex_support.patch b/target/linux/ixp4xx/patches-4.1/120-compex_support.patch new file mode 100644 index 0000000..2abc159 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/120-compex_support.patch @@ -0,0 +1,199 @@ +From 24025a2dcf1248079dd3019fac6ed955252d277f Mon Sep 17 00:00:00 2001 +From: Imre Kaloz +Date: Mon, 14 Jul 2008 21:56:34 +0200 +Subject: [PATCH] Add support for the Compex WP18 / NP18A boards + +Signed-off-by: Imre Kaloz +--- + +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -85,6 +85,14 @@ config MACH_SIDEWINDER + Engineering Sidewinder board. For more information on this + platform, see http://www.adiengineering.com + ++config MACH_COMPEXWP18 ++ bool "Compex WP18 / NP18A" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Compex' ++ WP18 or NP18A boards. For more information on this ++ platform, see http://www.compex.com.sg/home/OEM/product_ap.htm ++ + config ARCH_IXDP425 + bool "IXDP425" + help +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -21,6 +21,7 @@ obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o + obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o + obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o + obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o ++obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o + + obj-y += common.o + +@@ -43,6 +44,7 @@ obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_ + obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o + obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o + obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o ++obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/compex42x-setup.c +@@ -0,0 +1,141 @@ ++/* ++ * arch/arm/mach-ixp4xx/compex-setup.c ++ * ++ * Compex WP18 / NP18A board-setup ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++static struct flash_platform_data compex42x_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource compex42x_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device compex42x_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &compex42x_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &compex42x_flash_resource, ++}; ++ ++static struct resource compex42x_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port compex42x_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device compex42x_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = compex42x_uart_data, ++ .num_resources = 2, ++ .resource = compex42x_uart_resources, ++}; ++ ++static struct eth_plat_info compex42x_plat_eth[] = { ++ { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0xf0000, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 3, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device compex42x_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = compex42x_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = compex42x_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *compex42x_devices[] __initdata = { ++ &compex42x_flash, ++ &compex42x_uart, ++ &compex42x_eth[0], ++ &compex42x_eth[1], ++}; ++ ++static void __init compex42x_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ compex42x_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ compex42x_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ platform_add_devices(compex42x_devices, ARRAY_SIZE(compex42x_devices)); ++} ++ ++MACHINE_START(COMPEXWP18, "Compex WP18 / NP18A") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = compex42x_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END +--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c +@@ -69,7 +69,8 @@ struct hw_pci ixdp425_pci __initdata = { + int __init ixdp425_pci_init(void) + { + if (machine_is_ixdp425() || machine_is_ixcdp1100() || +- machine_is_ixdp465() || machine_is_kixrp435()) ++ machine_is_ixdp465() || machine_is_kixrp435() || ++ machine_is_compex42x()) + pci_common_init(&ixdp425_pci); + return 0; + } diff --git a/target/linux/ixp4xx/patches-4.1/130-wrt300nv2_support.patch b/target/linux/ixp4xx/patches-4.1/130-wrt300nv2_support.patch new file mode 100644 index 0000000..49359be --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/130-wrt300nv2_support.patch @@ -0,0 +1,227 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -93,6 +93,14 @@ config MACH_COMPEXWP18 + WP18 or NP18A boards. For more information on this + platform, see http://www.compex.com.sg/home/OEM/product_ap.htm + ++config MACH_WRT300NV2 ++ bool "Linksys WRT300N v2" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Linksys' ++ WRT300N v2 router. For more information on this ++ platform, see http://openwrt.org ++ + config ARCH_IXDP425 + bool "IXDP425" + help +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -22,6 +22,7 @@ obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += v + obj-pci-$(CONFIG_MACH_PRONGHORN) += pronghorn-pci.o + obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o + obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o ++obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + + obj-y += common.o + +@@ -45,6 +46,7 @@ obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulca + obj-$(CONFIG_MACH_PRONGHORN) += pronghorn-setup.o + obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o + obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o ++obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -43,7 +43,8 @@ static __inline__ void __arch_decomp_set + if (machine_is_adi_coyote() || machine_is_gtwx5715() || + machine_is_gateway7001() || machine_is_wg302v2() || + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || +- machine_is_pronghorn() || machine_is_pronghorn_metro()) ++ machine_is_pronghorn() || machine_is_pronghorn_metro() || ++ machine_is_wrt300nv2()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/wrt300nv2-pci.c +@@ -0,0 +1,64 @@ ++/* ++ * arch/arch/mach-ixp4xx/wrt300nv2-pci.c ++ * ++ * PCI setup routines for Linksys WRT300N v2 ++ * ++ * Copyright (C) 2007 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++extern void ixp4xx_pci_preinit(void); ++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); ++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); ++ ++void __init wrt300nv2_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init wrt300nv2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO8; ++ else return -1; ++} ++ ++struct hw_pci wrt300nv2_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = wrt300nv2_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = wrt300nv2_map_irq, ++}; ++ ++int __init wrt300nv2_pci_init(void) ++{ ++ if (machine_is_wrt300nv2()) ++ pci_common_init(&wrt300nv2_pci); ++ return 0; ++} ++ ++subsys_initcall(wrt300nv2_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c +@@ -0,0 +1,110 @@ ++/* ++ * arch/arm/mach-ixp4xx/wrt300nv2-setup.c ++ * ++ * Board setup for the Linksys WRT300N v2 ++ * ++ * Copyright (C) 2007 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data wrt300nv2_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource wrt300nv2_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device wrt300nv2_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &wrt300nv2_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &wrt300nv2_flash_resource, ++}; ++ ++static struct resource wrt300nv2_uart_resource = { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port wrt300nv2_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device wrt300nv2_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = wrt300nv2_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &wrt300nv2_uart_resource, ++}; ++ ++static struct platform_device *wrt300nv2_devices[] __initdata = { ++ &wrt300nv2_flash, ++ &wrt300nv2_uart ++}; ++ ++static void __init wrt300nv2_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ wrt300nv2_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices)); ++} ++ ++#ifdef CONFIG_MACH_WRT300NV2 ++MACHINE_START(WRT300NV2, "Linksys WRT300N v2") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = wrt300nv2_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-4.1/131-wrt300nv2_mac_plat_info.patch b/target/linux/ixp4xx/patches-4.1/131-wrt300nv2_mac_plat_info.patch new file mode 100644 index 0000000..5debbf1 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/131-wrt300nv2_mac_plat_info.patch @@ -0,0 +1,42 @@ +--- a/arch/arm/mach-ixp4xx/wrt300nv2-setup.c ++++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c +@@ -76,9 +76,38 @@ static struct platform_device wrt300nv2_ + .resource = &wrt300nv2_uart_resource, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info wrt300nv2_plat_eth[] = { ++ { ++ .phy = -1, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device wrt300nv2_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = wrt300nv2_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = wrt300nv2_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ + static struct platform_device *wrt300nv2_devices[] __initdata = { + &wrt300nv2_flash, +- &wrt300nv2_uart ++ &wrt300nv2_uart, ++ &wrt300nv2_eth[0], ++ &wrt300nv2_eth[1], + }; + + static void __init wrt300nv2_init(void) diff --git a/target/linux/ixp4xx/patches-4.1/132-wrt300nv2_mac_fix.patch b/target/linux/ixp4xx/patches-4.1/132-wrt300nv2_mac_fix.patch new file mode 100644 index 0000000..99db267 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/132-wrt300nv2_mac_fix.patch @@ -0,0 +1,72 @@ +--- a/arch/arm/mach-ixp4xx/wrt300nv2-setup.c ++++ b/arch/arm/mach-ixp4xx/wrt300nv2-setup.c +@@ -3,6 +3,7 @@ + * + * Board setup for the Linksys WRT300N v2 + * ++ * Copyright (C) 2010 Alexandros C. Couloumbis + * Copyright (C) 2007 Imre Kaloz + * + * based on coyote-setup.c: +@@ -18,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -79,7 +81,8 @@ static struct platform_device wrt300nv2_ + /* Built-in 10/100 Ethernet MAC interfaces */ + static struct eth_plat_info wrt300nv2_plat_eth[] = { + { +- .phy = -1, ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x0F0000, + .rxq = 3, + .txreadyq = 20, + }, { +@@ -112,6 +115,10 @@ static struct platform_device *wrt300nv2 + + static void __init wrt300nv2_init(void) + { ++ uint8_t __iomem *f; ++ int offset = 0; ++ int i; ++ + ixp4xx_sys_init(); + + wrt300nv2_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); +@@ -121,6 +128,32 @@ static void __init wrt300nv2_init(void) + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; + + platform_add_devices(wrt300nv2_devices, ARRAY_SIZE(wrt300nv2_devices)); ++ ++ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x60000); ++ ++ if (f) { ++ for (i = 0; i < 6; i++) { ++#ifdef __ARMEB__ ++ wrt300nv2_plat_eth[0].hwaddr[i] = readb(f + 0x5FFA0 + i); ++ if (i == 5) ++ offset = 1; ++ wrt300nv2_plat_eth[1].hwaddr[i] = (wrt300nv2_plat_eth[0].hwaddr[i] + offset); ++#else ++ wrt300nv2_plat_eth[0].hwaddr[i] = readb(f + 0x5FFA0 + (i^3)); ++ if (i == 5) ++ offset = 1; ++ wrt300nv2_plat_eth[1].hwaddr[i] = (wrt300nv2_plat_eth[0].hwaddr[i] + offset); ++#endif ++ } ++ iounmap(f); ++ } ++ ++ if (!(is_valid_ether_addr(wrt300nv2_plat_eth[0].hwaddr))) ++ random_ether_addr(wrt300nv2_plat_eth[0].hwaddr); ++ if (!(is_valid_ether_addr(wrt300nv2_plat_eth[1].hwaddr))) { ++ memcpy(wrt300nv2_plat_eth[1].hwaddr, wrt300nv2_plat_eth[0].hwaddr, ETH_ALEN); ++ wrt300nv2_plat_eth[1].hwaddr[5] = (wrt300nv2_plat_eth[0].hwaddr[5] + 1); ++ } + } + + #ifdef CONFIG_MACH_WRT300NV2 diff --git a/target/linux/ixp4xx/patches-4.1/150-lanready_ap1000_support.patch b/target/linux/ixp4xx/patches-4.1/150-lanready_ap1000_support.patch new file mode 100644 index 0000000..ad09efd --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/150-lanready_ap1000_support.patch @@ -0,0 +1,203 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -101,6 +101,14 @@ config MACH_WRT300NV2 + WRT300N v2 router. For more information on this + platform, see http://openwrt.org + ++config MACH_AP1000 ++ bool "Lanready AP-1000" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Lanready's ++ AP1000 board. For more information on this ++ platform, see http://openwrt.org ++ + config ARCH_IXDP425 + bool "IXDP425" + help +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -23,6 +23,7 @@ obj-pci-$(CONFIG_MACH_PRONGHORN) += pron + obj-pci-$(CONFIG_MACH_SIDEWINDER) += sidewinder-pci.o + obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o ++obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o + + obj-y += common.o + +@@ -47,6 +48,7 @@ obj-$(CONFIG_MACH_PRONGHORN) += pronghor + obj-$(CONFIG_MACH_SIDEWINDER) += sidewinder-setup.o + obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o ++obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/ap1000-setup.c +@@ -0,0 +1,154 @@ ++/* ++ * arch/arm/mach-ixp4xx/ap1000-setup.c ++ * ++ * Lanready AP-1000 ++ * ++ * Copyright (C) 2007 Imre Kaloz ++ * ++ * based on ixdp425-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data ap1000_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource ap1000_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device ap1000_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &ap1000_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &ap1000_flash_resource, ++}; ++ ++static struct resource ap1000_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port ap1000_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device ap1000_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = ap1000_uart_data, ++ .num_resources = 2, ++ .resource = ap1000_uart_resources ++}; ++ ++static struct platform_device *ap1000_devices[] __initdata = { ++ &ap1000_flash, ++ &ap1000_uart ++}; ++ ++static char ap1000_mem_fixup[] __initdata = "mem=64M "; ++ ++static void __init ap1000_fixup(struct machine_desc *desc, ++ struct tag *tags, char **cmdline, struct meminfo *mi) ++ ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(ap1000_mem_fixup) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, ap1000_mem_fixup, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(ap1000_mem_fixup), p, ++ COMMAND_LINE_SIZE - strlen(ap1000_mem_fixup)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ ++static void __init ap1000_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ ap1000_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ ap1000_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ ++ platform_add_devices(ap1000_devices, ARRAY_SIZE(ap1000_devices)); ++} ++ ++#ifdef CONFIG_MACH_AP1000 ++MACHINE_START(AP1000, "Lanready AP-1000") ++ /* Maintainer: Imre Kaloz */ ++ .fixup = ap1000_fixup, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = ap1000_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif +--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c +@@ -70,7 +70,7 @@ int __init ixdp425_pci_init(void) + { + if (machine_is_ixdp425() || machine_is_ixcdp1100() || + machine_is_ixdp465() || machine_is_kixrp435() || +- machine_is_compex42x()) ++ machine_is_compex42x() || machine_is_ap1000()) + pci_common_init(&ixdp425_pci); + return 0; + } diff --git a/target/linux/ixp4xx/patches-4.1/151-lanready_ap1000_mac_plat_info.patch b/target/linux/ixp4xx/patches-4.1/151-lanready_ap1000_mac_plat_info.patch new file mode 100644 index 0000000..2079589 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/151-lanready_ap1000_mac_plat_info.patch @@ -0,0 +1,51 @@ +--- a/arch/arm/mach-ixp4xx/ap1000-setup.c ++++ b/arch/arm/mach-ixp4xx/ap1000-setup.c +@@ -91,15 +91,45 @@ static struct platform_device ap1000_uar + .resource = ap1000_uart_resources + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info ap1000_plat_eth[] = { ++ { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 5, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device ap1000_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = ap1000_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = ap1000_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ + static struct platform_device *ap1000_devices[] __initdata = { + &ap1000_flash, +- &ap1000_uart ++ &ap1000_uart, ++ &ap1000_eth[0], ++ &ap1000_eth[1], + }; + + static char ap1000_mem_fixup[] __initdata = "mem=64M "; + +-static void __init ap1000_fixup(struct machine_desc *desc, +- struct tag *tags, char **cmdline, struct meminfo *mi) ++static void __init ap1000_fixup(struct tag *tags, char **cmdline, ++ struct meminfo *mi) + + { + struct tag *t = tags; diff --git a/target/linux/ixp4xx/patches-4.1/160-delayed_uart_io.patch b/target/linux/ixp4xx/patches-4.1/160-delayed_uart_io.patch new file mode 100644 index 0000000..9dc184b --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/160-delayed_uart_io.patch @@ -0,0 +1,131 @@ +--- a/drivers/tty/serial/8250/8250_core.c ++++ b/drivers/tty/serial/8250/8250_core.c +@@ -446,6 +446,20 @@ static void mem_serial_out(struct uart_p + writeb(value, p->membase + offset); + } + ++static unsigned int memdelay_serial_in(struct uart_port *p, int offset) ++{ ++ struct uart_8250_port *up = (struct uart_8250_port *)p; ++ udelay(up->port.rw_delay); ++ return mem_serial_in(p, offset); ++} ++ ++static void memdelay_serial_out(struct uart_port *p, int offset, int value) ++{ ++ struct uart_8250_port *up = (struct uart_8250_port *)p; ++ udelay(up->port.rw_delay); ++ mem_serial_out(p, offset, value); ++} ++ + static void mem32_serial_out(struct uart_port *p, int offset, int value) + { + offset = offset << p->regshift; +@@ -513,6 +527,11 @@ static void set_io_from_upio(struct uart + p->serial_out = mem32be_serial_out; + break; + ++ case UPIO_MEM_DELAY: ++ p->serial_in = memdelay_serial_in; ++ p->serial_out = memdelay_serial_out; ++ break; ++ + #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) + case UPIO_AU: + p->serial_in = au_serial_in; +@@ -539,6 +558,7 @@ serial_port_out_sync(struct uart_port *p + case UPIO_MEM: + case UPIO_MEM32: + case UPIO_MEM32BE: ++ case UPIO_MEM_DELAY: + case UPIO_AU: + p->serial_out(p, offset, value); + p->serial_in(p, UART_LCR); /* safe, no side-effects */ +@@ -2776,6 +2796,7 @@ static int serial8250_request_std_resour + case UPIO_MEM32: + case UPIO_MEM32BE: + case UPIO_MEM: ++ case UPIO_MEM_DELAY: + if (!port->mapbase) + break; + +@@ -2813,6 +2834,7 @@ static void serial8250_release_std_resou + case UPIO_MEM32: + case UPIO_MEM32BE: + case UPIO_MEM: ++ case UPIO_MEM_DELAY: + if (!port->mapbase) + break; + +@@ -3701,6 +3723,7 @@ static int serial8250_probe(struct platf + uart.port.set_termios = p->set_termios; + uart.port.pm = p->pm; + uart.port.dev = &dev->dev; ++ uart.port.rw_delay = p->rw_delay; + uart.port.irqflags |= irqflag; + ret = serial8250_register_8250_port(&uart); + if (ret < 0) { +@@ -3857,6 +3880,7 @@ int serial8250_register_8250_port(struct + uart->bugs = up->bugs; + uart->port.mapbase = up->port.mapbase; + uart->port.mapsize = up->port.mapsize; ++ uart->port.rw_delay = up->port.rw_delay; + uart->port.private_data = up->port.private_data; + uart->port.fifosize = up->port.fifosize; + uart->tx_loadsz = up->tx_loadsz; +--- a/drivers/tty/serial/serial_core.c ++++ b/drivers/tty/serial/serial_core.c +@@ -2177,6 +2177,7 @@ uart_report_port(struct uart_driver *drv + snprintf(address, sizeof(address), + "I/O 0x%lx offset 0x%x", port->iobase, port->hub6); + break; ++ case UPIO_MEM_DELAY: + case UPIO_MEM: + case UPIO_MEM32: + case UPIO_MEM32BE: +@@ -2824,6 +2825,7 @@ int uart_match_port(struct uart_port *po + case UPIO_HUB6: + return (port1->iobase == port2->iobase) && + (port1->hub6 == port2->hub6); ++ case UPIO_MEM_DELAY: + case UPIO_MEM: + case UPIO_MEM32: + case UPIO_MEM32BE: +--- a/include/linux/serial_8250.h ++++ b/include/linux/serial_8250.h +@@ -27,6 +27,7 @@ struct plat_serial8250_port { + void *private_data; + unsigned char regshift; /* register shift */ + unsigned char iotype; /* UPIO_* */ ++ unsigned int rw_delay; /* udelay for slower busses IXP4XX Expansion Bus */ + unsigned char hub6; + upf_t flags; /* UPF_* flags */ + unsigned int type; /* If UPF_FIXED_TYPE */ +--- a/include/linux/serial_core.h ++++ b/include/linux/serial_core.h +@@ -150,6 +150,7 @@ struct uart_port { + #define UPIO_AU (SERIAL_IO_AU) /* Au1x00 and RT288x type IO */ + #define UPIO_TSI (SERIAL_IO_TSI) /* Tsi108/109 type IO */ + #define UPIO_MEM32BE (SERIAL_IO_MEM32BE) /* 32b big endian */ ++#define UPIO_MEM_DELAY (SERIAL_IO_MEM_DELAY) + + unsigned int read_status_mask; /* driver specific */ + unsigned int ignore_status_mask; /* driver specific */ +@@ -231,6 +232,7 @@ struct uart_port { + int hw_stopped; /* sw-assisted CTS flow state */ + unsigned int mctrl; /* current modem ctrl settings */ + unsigned int timeout; /* character-based timeout */ ++ unsigned int rw_delay; /* udelay for slow busses, IXP4XX Expansion Bus */ + unsigned int type; /* port type */ + const struct uart_ops *ops; + unsigned int custom_divisor; +--- a/include/uapi/linux/serial.h ++++ b/include/uapi/linux/serial.h +@@ -69,6 +69,7 @@ struct serial_struct { + #define SERIAL_IO_AU 4 + #define SERIAL_IO_TSI 5 + #define SERIAL_IO_MEM32BE 6 ++#define SERIAL_IO_MEM_DELAY 7 + + #define UART_CLEAR_FIFO 0x01 + #define UART_USE_FIFO 0x02 diff --git a/target/linux/ixp4xx/patches-4.1/162-wg302v1_mem_fixup.patch b/target/linux/ixp4xx/patches-4.1/162-wg302v1_mem_fixup.patch new file mode 100644 index 0000000..75212bc --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/162-wg302v1_mem_fixup.patch @@ -0,0 +1,38 @@ +--- a/arch/arm/mach-ixp4xx/wg302v1-setup.c ++++ b/arch/arm/mach-ixp4xx/wg302v1-setup.c +@@ -117,6 +117,35 @@ static struct platform_device *wg302v1_d + &wg302v1_eth[0], + }; + ++static char wg302v1_mem_fixup[] __initdata = " mem=32M"; ++ ++static void __init wg302v1_fixup(struct tag *tags, char **cmdline, ++ struct meminfo *mi) ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ size_t fixlen, cmdlen; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ fixlen = strlen(wg302v1_mem_fixup); ++ cmdlen = strlen(p); ++ if (fixlen + cmdlen >= COMMAND_LINE_SIZE) ++ return; ++ ++ /* append the fixup to the cmdline */ ++ memmove(p + cmdlen, wg302v1_mem_fixup, fixlen + 1); ++ ++ /* Adjust the size of the atag if there was one */ ++ if (t->hdr.size) ++ t->hdr.size += fixlen; ++} ++ + static void __init wg302v1_init(void) + { + ixp4xx_sys_init(); diff --git a/target/linux/ixp4xx/patches-4.1/170-ixdpg425_mac_plat_info.patch b/target/linux/ixp4xx/patches-4.1/170-ixdpg425_mac_plat_info.patch new file mode 100644 index 0000000..f7090cd --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/170-ixdpg425_mac_plat_info.patch @@ -0,0 +1,51 @@ +--- a/arch/arm/mach-ixp4xx/coyote-setup.c ++++ b/arch/arm/mach-ixp4xx/coyote-setup.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -81,9 +82,39 @@ static struct platform_device coyote_uar + .resource = &coyote_uart_resource, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info ixdpg425_plat_eth[] = { ++ { ++ .phy = 5, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 4, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device ixdpg425_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = ixdpg425_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = ixdpg425_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++ + static struct platform_device *coyote_devices[] __initdata = { + &coyote_flash, +- &coyote_uart ++ &coyote_uart, ++ &ixdpg425_eth[0], ++ &ixdpg425_eth[1], + }; + + static void __init coyote_init(void) diff --git a/target/linux/ixp4xx/patches-4.1/175-avila_hss_audio_support.patch b/target/linux/ixp4xx/patches-4.1/175-avila_hss_audio_support.patch new file mode 100644 index 0000000..4bffe42 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/175-avila_hss_audio_support.patch @@ -0,0 +1,2090 @@ +--- a/sound/soc/Kconfig ++++ b/sound/soc/Kconfig +@@ -57,6 +57,7 @@ source "sound/soc/tegra/Kconfig" + source "sound/soc/txx9/Kconfig" + source "sound/soc/ux500/Kconfig" + source "sound/soc/xtensa/Kconfig" ++source "sound/soc/gw-avila/Kconfig" + + # Supported codecs + source "sound/soc/codecs/Kconfig" +--- a/sound/soc/Makefile ++++ b/sound/soc/Makefile +@@ -38,3 +38,4 @@ obj-$(CONFIG_SND_SOC) += tegra/ + obj-$(CONFIG_SND_SOC) += txx9/ + obj-$(CONFIG_SND_SOC) += ux500/ + obj-$(CONFIG_SND_SOC) += xtensa/ ++obj-$(CONFIG_SND_SOC) += gw-avila/ +--- /dev/null ++++ b/sound/soc/gw-avila/Kconfig +@@ -0,0 +1,17 @@ ++config SND_GW_AVILA_SOC_PCM ++ tristate ++ ++config SND_GW_AVILA_SOC_HSS ++ tristate ++ ++config SND_GW_AVILA_SOC ++ tristate "SoC Audio for the Gateworks AVILA Family" ++ depends on ARCH_IXP4XX && SND_SOC ++ select SND_GW_AVILA_SOC_PCM ++ select SND_GW_AVILA_SOC_HSS ++ select SND_SOC_TLV320AIC3X ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the Gateworks HSS interface. You will also need ++ to select the audio interfaces to support below. ++ +--- /dev/null ++++ b/sound/soc/gw-avila/Makefile +@@ -0,0 +1,8 @@ ++# Gateworks Avila HSS Platform Support ++snd-soc-gw-avila-objs := gw-avila.o ixp4xx_hss.o ++snd-soc-gw-avila-pcm-objs := gw-avila-pcm.o ++snd-soc-gw-avila-hss-objs := gw-avila-hss.o ++ ++obj-$(CONFIG_SND_GW_AVILA_SOC) += snd-soc-gw-avila.o ++obj-$(CONFIG_SND_GW_AVILA_SOC_PCM) += snd-soc-gw-avila-pcm.o ++obj-$(CONFIG_SND_GW_AVILA_SOC_HSS) += snd-soc-gw-avila-hss.o +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila-hss.c +@@ -0,0 +1,103 @@ ++/* ++ * gw-avila-hss.c -- HSS Audio Support for Gateworks Avila ++ * ++ * Author: Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "ixp4xx_hss.h" ++#include "gw-avila-hss.h" ++ ++#define gw_avila_hss_suspend NULL ++#define gw_avila_hss_resume NULL ++ ++struct snd_soc_dai_driver gw_avila_hss_dai = { ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | ++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | ++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | ++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | ++ SNDRV_PCM_RATE_KNOT), ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, }, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | ++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | ++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | ++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | ++ SNDRV_PCM_RATE_KNOT), ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, }, ++}; ++ ++static const struct snd_soc_component_driver gw_avila_hss_component = { ++ .name = "gw_avila_hss", ++}; ++ ++static int gw_avila_hss_probe(struct platform_device *pdev) ++{ ++ int port = (pdev->id < 2) ? 0 : 1; ++ int channel = (pdev->id % 2); ++ ++ hss_handle[pdev->id] = hss_init(port, channel); ++ if (!hss_handle[pdev->id]) { ++ return -ENODEV; ++ } ++ ++ return snd_soc_register_component(&pdev->dev, &gw_avila_hss_component, ++ &gw_avila_hss_dai, 1); ++} ++ ++static int gw_avila_hss_remove(struct platform_device *pdev) ++{ ++ snd_soc_unregister_component(&pdev->dev); ++ ++ return 0; ++} ++ ++static struct platform_driver gw_avila_hss_driver = { ++ .probe = gw_avila_hss_probe, ++ .remove = gw_avila_hss_remove, ++ .driver = { ++ .name = "gw_avila_hss", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static int __init gw_avila_hss_init(void) ++{ ++ return platform_driver_register(&gw_avila_hss_driver); ++} ++module_init(gw_avila_hss_init); ++ ++static void __exit gw_avila_hss_exit(void) ++{ ++ platform_driver_unregister(&gw_avila_hss_driver); ++} ++module_exit(gw_avila_hss_exit); ++ ++MODULE_AUTHOR("Chris Lang"); ++MODULE_DESCRIPTION("HSS Audio Driver for Gateworks Avila"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila-hss.h +@@ -0,0 +1,12 @@ ++/* ++ * Author: Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _GW_AVILA_HSS_H ++#define _GW_AVILA_HSS_H ++ ++#endif +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila-pcm.c +@@ -0,0 +1,327 @@ ++/* ++ * ALSA PCM interface for the TI DAVINCI processor ++ * ++ * Author: Chris Lang, ++ * Copyright: (C) 2009 Gateworks Corporation ++ * ++ * Based On: davinci-evm.c, Author: Vladimir Barinov, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "gw-avila-pcm.h" ++#include "gw-avila-hss.h" ++#include "ixp4xx_hss.h" ++ ++#define GW_AVILA_PCM_DEBUG 0 ++#if GW_AVILA_PCM_DEBUG ++#define DPRINTK(x...) printk(KERN_DEBUG x) ++#else ++#define DPRINTK(x...) ++#endif ++ ++static struct snd_pcm_hardware gw_avila_pcm_hardware = { ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID), ++/* SNDRV_PCM_INFO_PAUSE),*/ ++ .formats = (SNDRV_PCM_FMTBIT_S16_LE), ++ .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | ++ SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | ++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | ++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | ++ SNDRV_PCM_RATE_KNOT), ++ .rate_min = 8000, ++ .rate_max = 8000, ++ .channels_min = 2, ++ .channels_max = 2, ++ .buffer_bytes_max = 64 * 1024, // All of the lines below may need to be changed ++ .period_bytes_min = 128, ++ .period_bytes_max = 4 * 1024, ++ .periods_min = 16, ++ .periods_max = 32, ++ .fifo_size = 0, ++}; ++ ++struct gw_avila_runtime_data { ++ spinlock_t lock; ++ int period; /* current DMA period */ ++ int master_lch; /* Master DMA channel */ ++ int slave_lch; /* Slave DMA channel */ ++ struct gw_avila_pcm_dma_params *params; /* DMA params */ ++}; ++ ++static void gw_avila_dma_irq(void *data) ++{ ++ struct snd_pcm_substream *substream = data; ++ snd_pcm_period_elapsed(substream); ++} ++ ++static int gw_avila_pcm_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct hss_device *hdev = runtime->private_data; ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ hss_tx_start(hdev); ++ else ++ hss_rx_start(hdev); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ hss_tx_stop(hdev); ++ else ++ hss_rx_stop(hdev); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ return ret; ++} ++ ++static int gw_avila_pcm_prepare(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct hss_device *hdev = runtime->private_data; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ hss_set_tx_callback(hdev, gw_avila_dma_irq, substream); ++ hss_config_tx_dma(hdev, runtime->dma_area, runtime->buffer_size, runtime->period_size); ++ } else { ++ hss_set_rx_callback(hdev, gw_avila_dma_irq, substream); ++ hss_config_rx_dma(hdev, runtime->dma_area, runtime->buffer_size, runtime->period_size); ++ } ++ ++ return 0; ++} ++ ++static snd_pcm_uframes_t ++gw_avila_pcm_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct hss_device *hdev = runtime->private_data; ++ ++ unsigned int curr = 0; ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ curr = hss_curr_offset_tx(hdev); ++ else ++ curr = hss_curr_offset_rx(hdev); ++ return curr; ++} ++ ++static int gw_avila_pcm_open(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ snd_soc_set_runtime_hwparams(substream, &gw_avila_pcm_hardware); ++ ++ if (hss_handle[cpu_dai->id] != NULL) ++ runtime->private_data = hss_handle[cpu_dai->id]; ++ else { ++ pr_err("hss_handle is NULL\n"); ++ return -1; ++ } ++ ++ hss_chan_open(hss_handle[cpu_dai->id]); ++ ++ return 0; ++} ++ ++static int gw_avila_pcm_close(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ struct hss_device *hdev = runtime->private_data; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ memset(hdev->tx_buf, 0, runtime->buffer_size); ++ } else ++ memset(hdev->rx_buf, 0, runtime->buffer_size); ++ ++ hss_chan_close(hdev); ++ ++ return 0; ++} ++ ++static int gw_avila_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *hw_params) ++{ ++ return snd_pcm_lib_malloc_pages(substream, ++ params_buffer_bytes(hw_params)); ++} ++ ++static int gw_avila_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ memset(runtime->dma_area, 0, runtime->buffer_size); ++ ++ return snd_pcm_lib_free_pages(substream); ++} ++ ++static int gw_avila_pcm_mmap(struct snd_pcm_substream *substream, ++ struct vm_area_struct *vma) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ ++ return dma_mmap_writecombine(substream->pcm->card->dev, vma, ++ runtime->dma_area, ++ runtime->dma_addr, ++ runtime->dma_bytes); ++} ++ ++struct snd_pcm_ops gw_avila_pcm_ops = { ++ .open = gw_avila_pcm_open, ++ .close = gw_avila_pcm_close, ++ .ioctl = snd_pcm_lib_ioctl, ++ .hw_params = gw_avila_pcm_hw_params, ++ .hw_free = gw_avila_pcm_hw_free, ++ .prepare = gw_avila_pcm_prepare, ++ .trigger = gw_avila_pcm_trigger, ++ .pointer = gw_avila_pcm_pointer, ++ .mmap = gw_avila_pcm_mmap, ++}; ++ ++static int gw_avila_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream) ++{ ++ struct snd_pcm_substream *substream = pcm->streams[stream].substream; ++ struct snd_dma_buffer *buf = &substream->dma_buffer; ++ size_t size = gw_avila_pcm_hardware.buffer_bytes_max; ++ ++ buf->dev.type = SNDRV_DMA_TYPE_DEV; ++ buf->dev.dev = pcm->card->dev; ++ buf->private_data = NULL; ++ ++ buf->area = dma_alloc_coherent(pcm->card->dev, size, ++ &buf->addr, GFP_KERNEL); ++ ++ if (!buf->area) { ++ return -ENOMEM; ++ } ++ ++ memset(buf->area, 0xff, size); ++ ++ DPRINTK("preallocate_dma_buffer: area=%p, addr=%p, size=%d\n", ++ (void *) buf->area, (void *) buf->addr, size); ++ ++ buf->bytes = size; ++ ++ return 0; ++} ++ ++static void gw_avila_pcm_free(struct snd_pcm *pcm) ++{ ++ struct snd_pcm_substream *substream; ++ struct snd_dma_buffer *buf; ++ int stream; ++ ++ for (stream = 0; stream < 2; stream++) { ++ substream = pcm->streams[stream].substream; ++ if (!substream) ++ continue; ++ ++ buf = &substream->dma_buffer; ++ if (!buf->area) ++ continue; ++ ++ dma_free_coherent(NULL, buf->bytes, buf->area, 0); ++ buf->area = NULL; ++ } ++} ++ ++static u64 gw_avila_pcm_dmamask = 0xFFFFFFFF; ++ ++static int gw_avila_pcm_new(struct snd_soc_pcm_runtime *rtd) ++{ ++ struct snd_card *card = rtd->card->snd_card; ++ struct snd_pcm *pcm = rtd->pcm; ++ struct snd_soc_dai *dai = rtd->codec_dai; ++ int ret; ++ ++ if (!card->dev->dma_mask) ++ card->dev->dma_mask = &gw_avila_pcm_dmamask; ++ if (!card->dev->coherent_dma_mask) ++ card->dev->coherent_dma_mask = 0xFFFFFFFF; ++ ++ if (dai->driver->playback.channels_min) { ++ ret = gw_avila_pcm_preallocate_dma_buffer(pcm, ++ SNDRV_PCM_STREAM_PLAYBACK); ++ if (ret) ++ return ret; ++ } ++ ++ if (dai->driver->capture.channels_min) { ++ ret = gw_avila_pcm_preallocate_dma_buffer(pcm, ++ SNDRV_PCM_STREAM_CAPTURE); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++struct snd_soc_platform_driver gw_avila_soc_platform = { ++ .ops = &gw_avila_pcm_ops, ++ .pcm_new = gw_avila_pcm_new, ++ .pcm_free = gw_avila_pcm_free, ++}; ++ ++static int gw_avila_pcm_platform_probe(struct platform_device *pdev) ++{ ++ return snd_soc_register_platform(&pdev->dev, &gw_avila_soc_platform); ++} ++ ++static int gw_avila_pcm_platform_remove(struct platform_device *pdev) ++{ ++ snd_soc_unregister_platform(&pdev->dev); ++ return 0; ++} ++ ++static struct platform_driver gw_avila_pcm_driver = { ++ .driver = { ++ .name = "gw_avila-audio", ++ .owner = THIS_MODULE, ++ }, ++ .probe = gw_avila_pcm_platform_probe, ++ .remove = gw_avila_pcm_platform_remove, ++}; ++ ++static int __init gw_avila_soc_platform_init(void) ++{ ++ return platform_driver_register(&gw_avila_pcm_driver); ++} ++module_init(gw_avila_soc_platform_init); ++ ++static void __exit gw_avila_soc_platform_exit(void) ++{ ++ platform_driver_unregister(&gw_avila_pcm_driver); ++} ++module_exit(gw_avila_soc_platform_exit); ++ ++MODULE_AUTHOR("Chris Lang"); ++MODULE_DESCRIPTION("Gateworks Avila PCM DMA module"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila-pcm.h +@@ -0,0 +1,32 @@ ++/* ++ * ALSA PCM interface for the Gateworks Avila platform ++ * ++ * Author: Chris Lang, ++ * Copyright: (C) 2009 Gateworks Corporation ++ * ++ * Based On: davinci-evm.c, Author: Vladimir Barinov, ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _GW_AVILA_PCM_H ++#define _GW_AVILA_PCM_H ++ ++#if 0 ++struct gw_avila_pcm_dma_params { ++ char *name; /* stream identifier */ ++ int channel; /* sync dma channel ID */ ++ dma_addr_t dma_addr; /* device physical address for DMA */ ++ unsigned int data_type; /* xfer data type */ ++}; ++ ++struct gw_avila_snd_platform_data { ++ int tx_dma_ch; // XXX Do we need this? ++ int rx_dma_ch; // XXX Do we need this ++}; ++extern struct snd_soc_platform gw_avila_soc_platform[]; ++#endif ++ ++#endif +--- /dev/null ++++ b/sound/soc/gw-avila/gw-avila.c +@@ -0,0 +1,244 @@ ++/* ++ * File: sound/soc/gw-avila/gw_avila.c ++ * Author: Chris Lang ++ * ++ * Created: Tue June 06 2008 ++ * Description: Board driver for Gateworks Avila ++ * ++ * Modified: ++ * Copyright 2009 Gateworks Corporation ++ * ++ * Bugs: What Bugs? ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, see the file COPYING, or write ++ * to the Free Software Foundation, Inc., ++ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ixp4xx_hss.h" ++#include "gw-avila-hss.h" ++#include "gw-avila-pcm.h" ++ ++#define CODEC_FREQ 33333000 ++ ++static int gw_avila_board_startup(struct snd_pcm_substream *substream) ++{ ++ pr_debug("%s enter\n", __func__); ++ return 0; ++} ++ ++static int gw_avila_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *codec_dai = rtd->codec_dai; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ int ret = 0; ++ ++ /* set codec DAI configuration */ ++ if (cpu_dai->id % 2) { ++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); ++ snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 1, 32); ++ } else { ++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM); ++ snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 0, 32); ++ } ++ ++ if (ret < 0) ++ return ret; ++ ++ /* set the codec system clock */ ++ ret = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_FREQ, SND_SOC_CLOCK_OUT); ++ if (ret < 0) ++ return ret; ++ ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { ++ SND_SOC_DAPM_HP("Headphone Jack", NULL), ++ SND_SOC_DAPM_LINE("Line Out", NULL), ++ SND_SOC_DAPM_LINE("Line In", NULL), ++}; ++ ++static const struct snd_soc_dapm_route audio_map[] = { ++ {"Headphone Jack", NULL, "HPLOUT"}, ++ {"Headphone Jack", NULL, "HPROUT"}, ++ ++ /* Line Out connected to LLOUT, RLOUT */ ++ {"Line Out", NULL, "LLOUT"}, ++ {"Line Out", NULL, "RLOUT"}, ++ ++ /* Line In connected to (LINE1L | LINE2L), (LINE1R | LINE2R) */ ++ {"LINE1L", NULL, "Line In"}, ++ {"LINE1R", NULL, "Line In"}, ++}; ++ ++/* Logic for a aic3x as connected on a davinci-evm */ ++static int avila_aic3x_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ struct snd_soc_codec *codec = rtd->codec; ++ struct snd_soc_dapm_context *dapm = &codec->dapm; ++ ++ /* Add davinci-evm specific widgets */ ++ snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, ++ ARRAY_SIZE(aic3x_dapm_widgets)); ++ ++ /* Set up davinci-evm specific audio path audio_map */ ++ snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); ++ ++ /* not connected */ ++ snd_soc_dapm_disable_pin(dapm, "MONO_LOUT"); ++ //snd_soc_dapm_disable_pin(dapm, "HPLCOM"); ++ //snd_soc_dapm_disable_pin(dapm, "HPRCOM"); ++ snd_soc_dapm_disable_pin(dapm, "MIC3L"); ++ snd_soc_dapm_disable_pin(dapm, "MIC3R"); ++ snd_soc_dapm_disable_pin(dapm, "LINE2L"); ++ snd_soc_dapm_disable_pin(dapm, "LINE2R"); ++ ++ /* always connected */ ++ snd_soc_dapm_enable_pin(dapm, "Headphone Jack"); ++ snd_soc_dapm_enable_pin(dapm, "Line Out"); ++ snd_soc_dapm_enable_pin(dapm, "Line In"); ++ ++ snd_soc_dapm_sync(dapm); ++ ++ return 0; ++} ++ ++static struct snd_soc_ops gw_avila_board_ops = { ++ .startup = gw_avila_board_startup, ++ .hw_params = gw_avila_hw_params, ++}; ++ ++static struct snd_soc_dai_link gw_avila_board_dai[] = { ++ { ++ .name = "HSS-0", ++ .stream_name = "HSS-0", ++ .cpu_dai_name = "gw_avila_hss.0", ++ .codec_dai_name = "tlv320aic3x-hifi", ++ .codec_name = "tlv320aic3x-codec.0-001b", ++ .platform_name = "gw_avila-audio.0", ++ .init = avila_aic3x_init, ++ .ops = &gw_avila_board_ops, ++ },{ ++ .name = "HSS-1", ++ .stream_name = "HSS-1", ++ .cpu_dai_name = "gw_avila_hss.1", ++ .codec_dai_name = "tlv320aic3x-hifi", ++ .codec_name = "tlv320aic3x-codec.0-001a", ++ .platform_name = "gw_avila-audio.1", ++ .init = avila_aic3x_init, ++ .ops = &gw_avila_board_ops, ++ },{ ++ .name = "HSS-2", ++ .stream_name = "HSS-2", ++ .cpu_dai_name = "gw_avila_hss.2", ++ .codec_dai_name = "tlv320aic3x-hifi", ++ .codec_name = "tlv320aic3x-codec.0-0019", ++ .platform_name = "gw_avila-audio.2", ++ .init = avila_aic3x_init, ++ .ops = &gw_avila_board_ops, ++ },{ ++ .name = "HSS-3", ++ .stream_name = "HSS-3", ++ .cpu_dai_name = "gw_avila_hss.3", ++ .codec_dai_name = "tlv320aic3x-hifi", ++ .codec_name = "tlv320aic3x-codec.0-0018", ++ .platform_name = "gw_avila-audio.3", ++ .init = avila_aic3x_init, ++ .ops = &gw_avila_board_ops, ++ }, ++}; ++ ++static struct snd_soc_card gw_avila_board[] = { ++ { ++ .name = "gw_avila-board.0", ++ .owner = THIS_MODULE, ++ .dai_link = &gw_avila_board_dai[0], ++ .num_links = 1, ++ },{ ++ .name = "gw_avila-board.1", ++ .owner = THIS_MODULE, ++ .dai_link = &gw_avila_board_dai[1], ++ .num_links = 1, ++ },{ ++ .name = "gw_avila-board.2", ++ .owner = THIS_MODULE, ++ .dai_link = &gw_avila_board_dai[2], ++ .num_links = 1, ++ },{ ++ .name = "gw_avila-board.3", ++ .owner = THIS_MODULE, ++ .dai_link = &gw_avila_board_dai[3], ++ .num_links = 1, ++ } ++}; ++ ++static struct platform_device *gw_avila_board_snd_device[4]; ++ ++static int __init gw_avila_board_init(void) ++{ ++ int ret; ++ struct port *port; ++ int i; ++ ++ if ((hss_port[0] = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL) ++ return -ENOMEM; ++ ++ if ((hss_port[1] = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL) ++ return -ENOMEM; ++ ++ for (i = 0; i < 4; i++) { ++ gw_avila_board_snd_device[i] = platform_device_alloc("soc-audio", i); ++ if (!gw_avila_board_snd_device[i]) { ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(gw_avila_board_snd_device[i], &gw_avila_board[i]); ++ ret = platform_device_add(gw_avila_board_snd_device[i]); ++ ++ if (ret) { ++ platform_device_put(gw_avila_board_snd_device[i]); ++ } ++ } ++ return ret; ++} ++ ++static void __exit gw_avila_board_exit(void) ++{ ++ int i; ++ for (i = 0; i < 4; i++) ++ platform_device_unregister(gw_avila_board_snd_device[i]); ++} ++ ++module_init(gw_avila_board_init); ++module_exit(gw_avila_board_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Chris Lang"); ++MODULE_DESCRIPTION("ALSA SoC HSS Audio gw_avila board"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/gw-avila/ixp4xx_hss.c +@@ -0,0 +1,902 @@ ++/* ++ * Intel IXP4xx HSS (synchronous serial port) driver for Linux ++ * ++ * Copyright (C) 2009 Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "ixp4xx_hss.h" ++ ++/***************************************************************************** ++ * global variables ++ ****************************************************************************/ ++ ++void hss_chan_read(unsigned long data); ++static char lock_init = 0; ++static spinlock_t npe_lock; ++static struct npe *npe; ++ ++static const struct { ++ int tx, txdone, rx, rxfree, chan; ++}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE, ++ HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE}, ++ {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE, ++ HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE}, ++}; ++ ++struct port *hss_port[2]; ++struct hss_device *hss_handle[32]; ++EXPORT_SYMBOL(hss_handle); ++ ++/***************************************************************************** ++ * utility functions ++ ****************************************************************************/ ++ ++#ifndef __ARMEB__ ++static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) ++{ ++ int i; ++ for (i = 0; i < cnt; i++) ++ dest[i] = swab32(src[i]); ++} ++#endif ++ ++static inline unsigned int sub_offset(unsigned int a, unsigned int b, ++ unsigned int modulo) ++{ ++ return (modulo /* make sure the result >= 0 */ + a - b) % modulo; ++} ++ ++/***************************************************************************** ++ * HSS access ++ ****************************************************************************/ ++ ++static void hss_config_load(struct port *port) ++{ ++ struct msg msg; ++ ++ do { ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_LOAD; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "HSS_LOAD_CONFIG")) ++ break; ++ if (npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG")) ++ break; ++ ++ /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ ++ if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) ++ break; ++ ++ /* HDLC may stop working without this */ ++ npe_recv_message(npe, &msg, "FLUSH_IT"); ++ return; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n", ++ port->id); ++ BUG(); ++} ++ ++static void hss_config_set_pcr(struct port *port) ++{ ++ struct msg msg; ++ ++ do { ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_TX_PCR; ++#if 0 ++ msg.data32 = PCR_FRM_SYNC_RISINGEDGE | PCR_MSB_ENDIAN | ++ PCR_TX_DATA_ENABLE | PCR_TX_UNASS_HIGH_IMP | PCR_TX_V56K_HIGH_IMP | PCR_TX_FB_HIGH_IMP; ++#else ++ msg.data32 = PCR_FRM_SYNC_RISINGEDGE | PCR_MSB_ENDIAN | ++ PCR_TX_DATA_ENABLE | PCR_TX_FB_HIGH_IMP | PCR_DCLK_EDGE_RISING; ++#endif ++ if (port->frame_size % 8 == 0) ++ msg.data32 |= PCR_SOF_NO_FBIT; ++ ++ if (npe_send_message(npe, &msg, "HSS_SET_TX_PCR")) ++ break; ++ ++ msg.index = HSS_CONFIG_RX_PCR; ++ msg.data32 &= ~ (PCR_DCLK_EDGE_RISING | PCR_FCLK_EDGE_RISING | PCR_TX_DATA_ENABLE); ++ ++ if (npe_send_message(npe, &msg, "HSS_SET_RX_PCR")) ++ break; ++ return; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id); ++ BUG(); ++} ++ ++static void hss_config_set_core(struct port *port) ++{ ++ struct msg msg; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_CORE_CR; ++#if 0 ++ msg.data32 = 0 | CCR_LOOPBACK | ++ (port->id ? CCR_SECOND_HSS : 0); ++#else ++ msg.data32 = 0 | ++ (port->id ? CCR_SECOND_HSS : 0); ++#endif ++ if (npe_send_message(npe, &msg, "HSS_SET_CORE_CR")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS core control" ++ " register\n", port->id); ++ BUG(); ++ } ++} ++ ++static void hss_config_set_line(struct port *port) ++{ ++ struct msg msg; ++ ++ hss_config_set_pcr(port); ++ hss_config_set_core(port); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_CLOCK_CR; ++ msg.data32 = CLK42X_SPEED_8192KHZ /* FIXME */; ++ if (npe_send_message(npe, &msg, "HSS_SET_CLOCK_CR")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS clock control" ++ " register\n", port->id); ++ BUG(); ++ } ++} ++ ++static void hss_config_set_rx_frame(struct port *port) ++{ ++ struct msg msg; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_RX_FCR; ++ msg.data16a = port->frame_sync_offset; ++ msg.data16b = port->frame_size - 1; ++ if (npe_send_message(npe, &msg, "HSS_SET_RX_FCR")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size" ++ " and offset\n", port->id); ++ BUG(); ++ } ++} ++ ++static void hss_config_set_frame(struct port *port) ++{ ++ struct msg msg; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ msg.index = HSS_CONFIG_TX_FCR; ++ msg.data16a = TX_FRAME_SYNC_OFFSET; ++ msg.data16b = port->frame_size - 1; ++ if (npe_send_message(npe, &msg, "HSS_SET_TX_FCR")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size" ++ " and offset\n", port->id); ++ BUG(); ++ } ++ hss_config_set_rx_frame(port); ++} ++ ++static void hss_config_set_lut(struct port *port) ++{ ++ struct msg msg; ++ int chan_count = 32; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_CONFIG_WRITE; ++ msg.hss_port = port->id; ++ ++ msg.index = HSS_CONFIG_TX_LUT; ++ msg.data32 = 0xffffffff; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.data32 = 0x0; ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_TX_LUT"); ++ ++ msg.index = HSS_CONFIG_RX_LUT; ++ msg.data32 = 0xffffffff; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.data32 = 0x0; ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ msg.index += 4; ++ npe_send_message(npe, &msg, "HSS_SET_RX_LUT"); ++ ++ hss_config_set_frame(port); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_NUM_CHANS_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = chan_count; ++ if (npe_send_message(npe, &msg, "CHAN_NUM_CHANS_WRITE")) { ++ printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n", ++ port->id); ++ BUG(); ++ } ++} ++ ++static u32 hss_config_get_status(struct port *port) ++{ ++ struct msg msg; ++ ++ do { ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = PORT_ERROR_READ; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "PORT_ERROR_READ")) ++ break; ++ if (npe_recv_message(npe, &msg, "PORT_ERROR_READ")) ++ break; ++ ++ return msg.data32; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id); ++ BUG(); ++} ++ ++static void hss_config_start_chan(struct port *port) ++{ ++ struct msg msg; ++ ++ port->chan_last_tx = 0; ++ port->chan_last_rx = 0; ++ ++ do { ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_RX_BUF_ADDR_WRITE; ++ msg.hss_port = port->id; ++ msg.data32 = port->chan_rx_buf_phys; ++ if (npe_send_message(npe, &msg, "CHAN_RX_BUF_ADDR_WRITE")) ++ break; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_TX_BUF_ADDR_WRITE; ++ msg.hss_port = port->id; ++ msg.data32 = port->chan_tx_pointers_phys; ++ if (npe_send_message(npe, &msg, "CHAN_TX_BUF_ADDR_WRITE")) ++ break; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_FLOW_ENABLE; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "CHAN_FLOW_ENABLE")) ++ break; ++ port->chan_started = 1; ++ return; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n", ++ port->id); ++ BUG(); ++} ++ ++static void hss_config_stop_chan(struct port *port) ++{ ++ struct msg msg; ++ ++ if (!port->chan_started) ++ return; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_FLOW_DISABLE; ++ msg.hss_port = port->id; ++ if (npe_send_message(npe, &msg, "CHAN_FLOW_DISABLE")) { ++ printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n", ++ port->id); ++ BUG(); ++ } ++ hss_config_get_status(port); /* make sure it's halted */ ++ port->chan_started = 0; ++} ++ ++static int hss_config_load_firmware(struct port *port) ++{ ++ struct msg msg; ++ ++ if (port->initialized) ++ return 0; ++ ++ if (!npe_running(npe)) { ++ int err; ++ if ((err = npe_load_firmware(npe, "NPE-A-HSS", ++ port->dev))) ++ return err; ++ } ++ ++ do { ++ /* HSS main configuration */ ++ hss_config_set_line(port); ++ ++ hss_config_set_frame(port); ++ ++ /* Channelized operation settings */ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_TX_BLK_CFG_WRITE; ++ msg.hss_port = port->id; ++ msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2; ++ msg.data8a = msg.data8b / 4; ++ msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b; ++ msg.data8c = msg.data8d / 4; ++ if (npe_send_message(npe, &msg, "CHAN_TX_BLK_CFG_WRITE")) ++ break; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_RX_BUF_CFG_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = CHAN_RX_TRIGGER / 8; ++ msg.data8b = CHAN_RX_FRAMES; ++ if (npe_send_message(npe, &msg, "CHAN_RX_BUF_CFG_WRITE")) ++ break; ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = CHAN_TX_BUF_SIZE_WRITE; ++ msg.hss_port = port->id; ++ msg.data8a = CHAN_TX_LISTS; ++ if (npe_send_message(npe, &msg, "CHAN_TX_BUF_SIZE_WRITE")) ++ break; ++ ++ port->initialized = 1; ++ return 0; ++ } while (0); ++ ++ printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id); ++ BUG(); ++} ++ ++void hss_chan_irq(void *pdev) ++{ ++ struct port *port = pdev; ++ ++ qmgr_disable_irq(queue_ids[port->id].chan); ++ ++ tasklet_hi_schedule(&port->task); ++} ++ ++ ++int hss_prepare_chan(struct port *port) ++{ ++ int err, i, j; ++ u32 *temp; ++ u32 temp2; ++ u8 *temp3; ++ ++ if (port->initialized) ++ return 0; ++ ++ if ((err = hss_config_load_firmware(port))) ++ return err; ++ ++ if ((err = qmgr_request_queue(queue_ids[port->id].chan, ++ CHAN_QUEUE_LEN, 0, 0, "%s:hss", "hss"))) ++ return err; ++ ++ port->chan_tx_buf = dma_alloc_coherent(port->dev, chan_tx_buf_len(port), &port->chan_tx_buf_phys, GFP_DMA); ++ memset(port->chan_tx_buf, 0, chan_tx_buf_len(port)); ++ ++ port->chan_tx_pointers = dma_alloc_coherent(port->dev, chan_tx_buf_len(port) / CHAN_TX_LIST_FRAMES * 4, &port->chan_tx_pointers_phys, GFP_DMA); ++ ++ temp3 = port->chan_tx_buf; ++ for (i = 0; i < CHAN_TX_LISTS; i++) { ++ for (j = 0; j < 8; j++) { ++ port->tx_lists[i][j] = temp3; ++ temp3 += CHAN_TX_LIST_FRAMES * 4; ++ } ++ } ++ ++ temp = port->chan_tx_pointers; ++ temp2 = port->chan_tx_buf_phys; ++ for (i = 0; i < CHAN_TX_LISTS; i++) ++ { ++ for (j = 0; j < 32; j++) ++ { ++ *temp = temp2; ++ temp2 += CHAN_TX_LIST_FRAMES; ++ temp++; ++ } ++ } ++ ++ port->chan_rx_buf = dma_alloc_coherent(port->dev, chan_rx_buf_len(port), &port->chan_rx_buf_phys, GFP_DMA); ++ ++ for (i = 0; i < 8; i++) { ++ temp3 = port->chan_rx_buf + (i * 4 * 128); ++ for (j = 0; j < 8; j++) { ++ port->rx_frames[i][j] = temp3; ++ temp3 += CHAN_RX_TRIGGER; ++ } ++ } ++ ++ qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY, ++ hss_chan_irq, port); ++ ++ return 0; ++ ++} ++ ++int hss_tx_start(struct hss_device *hdev) ++{ ++ unsigned long flags; ++ struct port *port = hdev->port; ++ ++ hdev->tx_loc = 0; ++ hdev->tx_frame = 0; ++ ++ set_bit((1 << hdev->id), &port->chan_tx_bitmap); ++ ++ if (!port->chan_started) ++ { ++ qmgr_enable_irq(queue_ids[port->id].chan); ++ spin_lock_irqsave(&npe_lock, flags); ++ hss_config_start_chan(port); ++ spin_unlock_irqrestore(&npe_lock, flags); ++ hss_chan_irq(port); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_tx_start); ++ ++int hss_rx_start(struct hss_device *hdev) ++{ ++ unsigned long flags; ++ struct port *port = hdev->port; ++ ++ hdev->rx_loc = 0; ++ hdev->rx_frame = 0; ++ ++ set_bit((1 << hdev->id), &port->chan_rx_bitmap); ++ ++ if (!port->chan_started) ++ { ++ qmgr_enable_irq(queue_ids[port->id].chan); ++ spin_lock_irqsave(&npe_lock, flags); ++ hss_config_start_chan(port); ++ spin_unlock_irqrestore(&npe_lock, flags); ++ hss_chan_irq(port); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_rx_start); ++ ++int hss_tx_stop(struct hss_device *hdev) ++{ ++ struct port *port = hdev->port; ++ ++ clear_bit((1 << hdev->id), &port->chan_tx_bitmap); ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_tx_stop); ++ ++int hss_rx_stop(struct hss_device *hdev) ++{ ++ struct port *port = hdev->port; ++ ++ clear_bit((1 << hdev->id), &port->chan_rx_bitmap); ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_rx_stop); ++ ++int hss_chan_open(struct hss_device *hdev) ++{ ++ struct port *port = hdev->port; ++ int i, err = 0; ++ ++ if (port->chan_open) ++ return 0; ++ ++ if (port->mode == MODE_HDLC) { ++ err = -ENOSYS; ++ goto out; ++ } ++ ++ if (port->mode == MODE_G704 && port->channels[0] == hdev->id) { ++ err = -EBUSY; /* channel #0 is used for G.704 signaling */ ++ goto out; ++ } ++ ++ for (i = MAX_CHANNELS; i > port->frame_size / 8; i--) ++ if (port->channels[i - 1] == hdev->id) { ++ err = -ECHRNG; /* frame too short */ ++ goto out; ++ } ++ ++ hdev->rx_loc = hdev->tx_loc = 0; ++ hdev->rx_frame = hdev->tx_frame = 0; ++ ++ //clear_bit((1 << hdev->id), &port->chan_rx_bitmap); ++ //clear_bit((1 << hdev->id), &port->chan_tx_bitmap); ++ ++ if (!port->initialized) { ++ hss_prepare_chan(port); ++ ++ hss_config_stop_chan(port); ++ hdev->open_count++; ++ port->chan_open_count++; ++ ++ hss_config_set_lut(port); ++ hss_config_load(port); ++ ++ } ++ port->chan_open = 1; ++ ++out: ++ return err; ++} ++EXPORT_SYMBOL(hss_chan_open); ++ ++int hss_chan_close(struct hss_device *hdev) ++{ ++ return 0; ++} ++EXPORT_SYMBOL(hss_chan_close); ++ ++void hss_chan_read(unsigned long data) ++{ ++ struct port *port = (void *)data; ++ struct hss_device *hdev; ++ u8 *hw_buf, *save_buf; ++ u8 *buf; ++ u32 v; ++ unsigned int tx_list, rx_frame; ++ int i, j, channel; ++ u8 more_work = 0; ++ ++/* ++ My Data in the hardware buffer is scattered by channels into 4 trunks ++ as follows for rx ++ ++ channel 0 channel 1 channel 2 channel 3 ++Trunk 1 = 0 -> 127 128 -> 255 256 -> 383 384 -> 512 ++Trunk 2 = 513 -> 639 640 -> 768 769 -> 895 896 -> 1023 ++Trunk 3 = 1024 -> 1151 1152 -> 1207 1208 -> 1407 1408 -> 1535 ++Trunk 4 = 1535 -> 1663 1664 -> 1791 1792 -> 1920 1921 -> 2047 ++ ++ I will get CHAN_RX_TRIGGER worth of bytes out of each channel on each trunk ++ with each IRQ ++ ++ For TX Data, it is split into 8 lists with each list containing 16 bytes per ++ channel ++ ++Trunk 1 = 0 -> 16 17 -> 32 33 -> 48 49 -> 64 ++Trunk 2 = 65 -> 80 81 -> 96 97 -> 112 113 -> 128 ++Trunk 3 = 129 -> 144 145 -> 160 161 -> 176 177 -> 192 ++Trunk 4 = 193 -> 208 209 -> 224 225 -> 240 241 -> 256 ++ ++*/ ++ ++ ++ while ((v = qmgr_get_entry(queue_ids[port->id].chan))) ++ { ++ tx_list = (v >> 8) & 0xFF; ++ rx_frame = v & 0xFF; ++ ++ if (tx_list == 7) ++ tx_list = 0; ++ else ++ tx_list++; ++ for (channel = 0; channel < 8; channel++) { ++ ++ hdev = port->chan_devices[channel]; ++ if (!hdev) ++ continue; ++ ++ if (test_bit(1 << channel, &port->chan_tx_bitmap)) { ++ buf = (u8 *)hdev->tx_buf + hdev->tx_loc; ++#if 0 ++ hw_buf = (u8 *)port->chan_tx_buf; ++ hw_buf += (tx_list * CHAN_TX_LIST_FRAMES * 32); ++ hw_buf += (4 * CHAN_TX_LIST_FRAMES * channel); ++ save_buf = hw_buf; ++#else ++ save_buf = port->tx_lists[tx_list][channel]; ++#endif ++ for (i = 0; i < CHAN_TX_LIST_FRAMES; i++) { ++ hw_buf = save_buf + i; ++ for (j = 0; j < 4; j++) { ++ *hw_buf = *(buf++); ++ hw_buf += CHAN_TX_LIST_FRAMES; ++ } ++ ++ hdev->tx_loc += 4; ++ hdev->tx_frame++; ++ if (hdev->tx_loc >= hdev->tx_buffer_size) { ++ hdev->tx_loc = 0; ++ buf = (u8 *)hdev->tx_buf; ++ } ++ } ++ } else { ++#if 0 ++ hw_buf = (u8 *)port->chan_tx_buf; ++ hw_buf += (tx_list * CHAN_TX_LIST_FRAMES * 32); ++ hw_buf += (4 * CHAN_TX_LIST_FRAMES * channel); ++#else ++ hw_buf = port->tx_lists[tx_list][channel]; ++#endif ++ memset(hw_buf, 0, 64); ++ } ++ ++ if (hdev->tx_frame >= hdev->tx_period_size && test_bit(1 << channel, &port->chan_tx_bitmap)) ++ { ++ hdev->tx_frame %= hdev->tx_period_size; ++ if (hdev->tx_callback) ++ hdev->tx_callback(hdev->tx_data); ++ more_work = 1; ++ } ++ ++ if (test_bit(1 << channel, &port->chan_rx_bitmap)) { ++ buf = (u8 *)hdev->rx_buf + hdev->rx_loc; ++#if 0 ++ hw_buf = (u8 *)port->chan_rx_buf; ++ hw_buf += (4 * CHAN_RX_FRAMES * channel); ++ hw_buf += rx_frame; ++ save_buf = hw_buf; ++#else ++ save_buf = port->rx_frames[channel][rx_frame >> 4]; ++#endif ++ for (i = 0; i < CHAN_RX_TRIGGER; i++) { ++ hw_buf = save_buf + i; ++ for (j = 0; j < 4; j++) { ++ *(buf++) = *hw_buf; ++ hw_buf += CHAN_RX_FRAMES; ++ } ++ hdev->rx_loc += 4; ++ hdev->rx_frame++; ++ if (hdev->rx_loc >= hdev->rx_buffer_size) { ++ hdev->rx_loc = 0; ++ buf = (u8 *)hdev->rx_buf; ++ } ++ } ++ } ++ ++ if (hdev->rx_frame >= hdev->rx_period_size && test_bit(1 << channel, &port->chan_rx_bitmap)) ++ { ++ hdev->rx_frame %= hdev->rx_period_size; ++ if (hdev->rx_callback) ++ hdev->rx_callback(hdev->rx_data); ++ more_work = 1; ++ } ++ } ++#if 0 ++ if (more_work) ++ { ++ tasklet_hi_schedule(&port->task); ++ return; ++ } ++#endif ++ } ++ ++ qmgr_enable_irq(queue_ids[port->id].chan); ++ ++ return; ++ ++} ++ ++struct hss_device *hss_chan_create(struct port *port, unsigned int channel) ++{ ++ struct hss_device *chan_dev; ++ unsigned long flags; ++ ++ chan_dev = kzalloc(sizeof(struct hss_device), GFP_KERNEL); ++ ++ spin_lock_irqsave(&npe_lock, flags); ++ ++ chan_dev->id = channel; ++ chan_dev->port = port; ++ ++ port->channels[channel] = channel; ++ ++ port->chan_devices[channel] = chan_dev; ++ ++ spin_unlock_irqrestore(&npe_lock, flags); ++ ++ return chan_dev; ++} ++ ++/***************************************************************************** ++ * initialization ++ ****************************************************************************/ ++ ++static struct platform_device gw_avila_hss_device_0 = { ++ .name = "ixp4xx_hss", ++ .id = 0, ++}; ++ ++static struct platform_device gw_avila_hss_device_1 = { ++ .name = "ixp4xx_hss", ++ .id = 1, ++}; ++ ++static struct platform_device *gw_avila_hss_port_0; ++static struct platform_device *gw_avila_hss_port_1; ++static u64 hss_dmamask = 0xFFFFFFFF; ++ ++struct hss_device *hss_init(int id, int channel) ++{ ++ struct port *port = hss_port[id]; ++ struct hss_device *hdev; ++ int ret; ++ ++ if (!lock_init) ++ { ++ spin_lock_init(&npe_lock); ++ lock_init = 1; ++ npe = npe_request(0); ++ } ++ ++ if (!port->init) { ++ if (id == 0) { ++ gw_avila_hss_port_0 = platform_device_alloc("hss-port", 0); ++ ++ platform_set_drvdata(gw_avila_hss_port_0, &gw_avila_hss_device_0); ++ port->dev = &gw_avila_hss_port_0->dev; ++ ++ if (!port->dev->dma_mask) ++ port->dev->dma_mask = &hss_dmamask; ++ if (!port->dev->coherent_dma_mask) ++ port->dev->coherent_dma_mask = 0xFFFFFFFF; ++ ++ ret = platform_device_add(gw_avila_hss_port_0); ++ ++ if (ret) ++ platform_device_put(gw_avila_hss_port_0); ++ ++ tasklet_init(&port->task, hss_chan_read, (unsigned long) port); ++ } ++ else ++ { ++ gw_avila_hss_port_1 = platform_device_alloc("hss-port", 1); ++ ++ platform_set_drvdata(gw_avila_hss_port_1, &gw_avila_hss_device_1); ++ port->dev = &gw_avila_hss_port_1->dev; ++ ++ if (!port->dev->dma_mask) ++ port->dev->dma_mask = &hss_dmamask; ++ if (!port->dev->coherent_dma_mask) ++ port->dev->coherent_dma_mask = 0xFFFFFFFF; ++ ++ ret = platform_device_add(gw_avila_hss_port_1); ++ ++ if (ret) ++ platform_device_put(gw_avila_hss_port_1); ++ ++ tasklet_init(&port->task, hss_chan_read, (unsigned long) port); ++ } ++ ++ port->init = 1; ++ port->id = id; ++ port->clock_type = CLOCK_EXT; ++ port->clock_rate = 8192000; ++ port->frame_size = 256; /* E1 */ ++ port->mode = MODE_RAW; ++ port->next_rx_frame = 0; ++ memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels)); ++ } ++ ++ hdev = hss_chan_create(port, channel); ++ ++ return hdev; ++} ++EXPORT_SYMBOL(hss_init); ++ ++int hss_set_tx_callback(struct hss_device *hdev, void (*tx_callback)(void *), void *tx_data) ++{ ++ BUG_ON(tx_callback == NULL); ++ hdev->tx_callback = tx_callback; ++ hdev->tx_data = tx_data; ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_set_tx_callback); ++ ++int hss_set_rx_callback(struct hss_device *hdev, void (*rx_callback)(void *), void *rx_data) ++{ ++ BUG_ON(rx_callback == NULL); ++ hdev->rx_callback = rx_callback; ++ hdev->rx_data = rx_data; ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_set_rx_callback); ++ ++int hss_config_rx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size) ++{ ++ /* ++ * Period Size and Buffer Size are in Frames which are u32 ++ * We convert the u32 *buf to u8 in order to make channel reads ++ * and rx_loc easier ++ */ ++ ++ hdev->rx_buf = (u8 *)buf; ++ hdev->rx_buffer_size = buffer_size << 2; ++ hdev->rx_period_size = period_size; ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_config_rx_dma); ++ ++int hss_config_tx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size) ++{ ++ /* ++ * Period Size and Buffer Size are in Frames which are u32 ++ * We convert the u32 *buf to u8 in order to make channel reads ++ * and rx_loc easier ++ */ ++ ++ hdev->tx_buf = (u8 *)buf; ++ hdev->tx_buffer_size = buffer_size << 2; ++ hdev->tx_period_size = period_size; ++ ++ return 0; ++} ++EXPORT_SYMBOL(hss_config_tx_dma); ++ ++unsigned long hss_curr_offset_rx(struct hss_device *hdev) ++{ ++ return hdev->rx_loc >> 2; ++} ++EXPORT_SYMBOL(hss_curr_offset_rx); ++ ++unsigned long hss_curr_offset_tx(struct hss_device *hdev) ++{ ++ return hdev->tx_loc >> 2; ++} ++EXPORT_SYMBOL(hss_curr_offset_tx); ++ ++MODULE_AUTHOR("Chris Lang"); ++MODULE_DESCRIPTION("Intel IXP4xx HSS Audio driver"); ++MODULE_LICENSE("GPL v2"); +--- /dev/null ++++ b/sound/soc/gw-avila/ixp4xx_hss.h +@@ -0,0 +1,401 @@ ++/* ++ * ++ * ++ * Copyright (C) 2009 Gateworks Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License ++ * as published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include XXX We aren't HDLC ++ ++#define DEBUG_QUEUES 0 ++#define DEBUG_DESC 0 ++#define DEBUG_RX 0 ++#define DEBUG_TX 0 ++#define DEBUG_PKT_BYTES 0 ++#define DEBUG_CLOSE 0 ++#define DEBUG_FRAMER 0 ++ ++#define DRV_NAME "ixp4xx_hss" ++ ++#define PKT_EXTRA_FLAGS 0 /* orig 1 */ ++#define TX_FRAME_SYNC_OFFSET 0 /* channelized */ ++#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */ ++#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */ ++ ++#define RX_DESCS 512 /* also length of all RX queues */ ++#define TX_DESCS 512 /* also length of all TX queues */ ++ ++//#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) ++#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */ ++#define MAX_CLOSE_WAIT 1000 /* microseconds */ ++#define HSS_COUNT 2 ++#define MIN_FRAME_SIZE 16 /* bits */ ++#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */ ++#define MAX_CHANNELS (MAX_FRAME_SIZE / 8) ++#define MAX_CHAN_DEVICES 32 ++#define CHANNEL_HDLC 0xFE ++#define CHANNEL_UNUSED 0xFF ++ ++#define NAPI_WEIGHT 16 ++#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */ ++#define CHAN_RX_FRAMES 128 ++#define CHAN_RX_TRUNKS 1 ++#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3) ++ ++#define CHAN_TX_LIST_FRAMES CHAN_RX_TRIGGER /* bytes/channel per list, 16 - 48 */ ++#define CHAN_TX_LISTS 8 ++#define CHAN_TX_TRUNKS CHAN_RX_TRUNKS ++#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS) ++ ++#define CHAN_QUEUE_LEN 32 /* minimum possible */ ++ ++#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES * CHAN_RX_TRUNKS) ++#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES * CHAN_TX_TRUNKS) ++ ++/* Queue IDs */ ++#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */ ++#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */ ++#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */ ++#define HSS0_PKT_TX1_QUEUE 15 ++#define HSS0_PKT_TX2_QUEUE 16 ++#define HSS0_PKT_TX3_QUEUE 17 ++#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */ ++#define HSS0_PKT_RXFREE1_QUEUE 19 ++#define HSS0_PKT_RXFREE2_QUEUE 20 ++#define HSS0_PKT_RXFREE3_QUEUE 21 ++#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */ ++ ++#define HSS1_CHL_RXTRIG_QUEUE 10 ++#define HSS1_PKT_RX_QUEUE 0 ++#define HSS1_PKT_TX0_QUEUE 5 ++#define HSS1_PKT_TX1_QUEUE 6 ++#define HSS1_PKT_TX2_QUEUE 7 ++#define HSS1_PKT_TX3_QUEUE 8 ++#define HSS1_PKT_RXFREE0_QUEUE 1 ++#define HSS1_PKT_RXFREE1_QUEUE 2 ++#define HSS1_PKT_RXFREE2_QUEUE 3 ++#define HSS1_PKT_RXFREE3_QUEUE 4 ++#define HSS1_PKT_TXDONE_QUEUE 9 ++ ++#define NPE_PKT_MODE_HDLC 0 ++#define NPE_PKT_MODE_RAW 1 ++#define NPE_PKT_MODE_56KMODE 2 ++#define NPE_PKT_MODE_56KENDIAN_MSB 4 ++ ++/* PKT_PIPE_HDLC_CFG_WRITE flags */ ++#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */ ++#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ ++#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */ ++ ++ ++/* hss_config, PCRs */ ++/* Frame sync sampling, default = active low */ ++#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000 ++#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000 ++#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000 ++ ++/* Frame sync pin: input (default) or output generated off a given clk edge */ ++#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000 ++#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000 ++ ++/* Frame and data clock sampling on edge, default = falling */ ++#define PCR_FCLK_EDGE_RISING 0x08000000 ++#define PCR_DCLK_EDGE_RISING 0x04000000 ++ ++/* Clock direction, default = input */ ++#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000 ++ ++/* Generate/Receive frame pulses, default = enabled */ ++#define PCR_FRM_PULSE_DISABLED 0x01000000 ++ ++ /* Data rate is full (default) or half the configured clk speed */ ++#define PCR_HALF_CLK_RATE 0x00200000 ++ ++/* Invert data between NPE and HSS FIFOs? (default = no) */ ++#define PCR_DATA_POLARITY_INVERT 0x00100000 ++ ++/* TX/RX endianness, default = LSB */ ++#define PCR_MSB_ENDIAN 0x00080000 ++ ++/* Normal (default) / open drain mode (TX only) */ ++#define PCR_TX_PINS_OPEN_DRAIN 0x00040000 ++ ++/* No framing bit transmitted and expected on RX? (default = framing bit) */ ++#define PCR_SOF_NO_FBIT 0x00020000 ++ ++/* Drive data pins? */ ++#define PCR_TX_DATA_ENABLE 0x00010000 ++ ++/* Voice 56k type: drive the data pins low (default), high, high Z */ ++#define PCR_TX_V56K_HIGH 0x00002000 ++#define PCR_TX_V56K_HIGH_IMP 0x00004000 ++ ++/* Unassigned type: drive the data pins low (default), high, high Z */ ++#define PCR_TX_UNASS_HIGH 0x00000800 ++#define PCR_TX_UNASS_HIGH_IMP 0x00001000 ++ ++/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */ ++#define PCR_TX_FB_HIGH_IMP 0x00000400 ++ ++/* 56k data endiannes - which bit unused: high (default) or low */ ++#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200 ++ ++/* 56k data transmission type: 32/8 bit data (default) or 56K data */ ++#define PCR_TX_56KS_56K_DATA 0x00000100 ++ ++/* hss_config, cCR */ ++/* Number of packetized clients, default = 1 */ ++#define CCR_NPE_HFIFO_2_HDLC 0x04000000 ++#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000 ++ ++/* default = no loopback */ ++#define CCR_LOOPBACK 0x02000000 ++ ++/* HSS number, default = 0 (first) */ ++#define CCR_SECOND_HSS 0x01000000 ++ ++ ++/* hss_config, clkCR: main:10, num:10, denom:12 */ ++#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/ ++ ++#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15) ++#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47) ++#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192) ++#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63) ++#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127) ++#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255) ++ ++#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127) ++#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383) ++#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385) ++#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511) ++#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023) ++#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047) ++ ++ ++/* hss_config, LUT entries */ ++#define TDMMAP_UNASSIGNED 0 ++#define TDMMAP_HDLC 1 /* HDLC - packetized */ ++#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ ++#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */ ++ ++/* offsets into HSS config */ ++#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */ ++#define HSS_CONFIG_RX_PCR 0x04 ++#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */ ++#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */ ++#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */ ++#define HSS_CONFIG_RX_FCR 0x14 ++#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */ ++#define HSS_CONFIG_RX_LUT 0x38 ++ ++ ++/* NPE command codes */ ++/* writes the ConfigWord value to the location specified by offset */ ++#define PORT_CONFIG_WRITE 0x40 ++ ++/* triggers the NPE to load the contents of the configuration table */ ++#define PORT_CONFIG_LOAD 0x41 ++ ++/* triggers the NPE to return an HssErrorReadResponse message */ ++#define PORT_ERROR_READ 0x42 ++ ++/* reset NPE internal status and enable the HssChannelized operation */ ++#define CHAN_FLOW_ENABLE 0x43 ++#define CHAN_FLOW_DISABLE 0x44 ++#define CHAN_IDLE_PATTERN_WRITE 0x45 ++#define CHAN_NUM_CHANS_WRITE 0x46 ++#define CHAN_RX_BUF_ADDR_WRITE 0x47 ++#define CHAN_RX_BUF_CFG_WRITE 0x48 ++#define CHAN_TX_BLK_CFG_WRITE 0x49 ++#define CHAN_TX_BUF_ADDR_WRITE 0x4A ++#define CHAN_TX_BUF_SIZE_WRITE 0x4B ++#define CHAN_TSLOTSWITCH_ENABLE 0x4C ++#define CHAN_TSLOTSWITCH_DISABLE 0x4D ++ ++/* downloads the gainWord value for a timeslot switching channel associated ++ with bypassNum */ ++#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E ++ ++/* triggers the NPE to reset internal status and enable the HssPacketized ++ operation for the flow specified by pPipe */ ++#define PKT_PIPE_FLOW_ENABLE 0x50 ++#define PKT_PIPE_FLOW_DISABLE 0x51 ++#define PKT_NUM_PIPES_WRITE 0x52 ++#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53 ++#define PKT_PIPE_HDLC_CFG_WRITE 0x54 ++#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55 ++#define PKT_PIPE_RX_SIZE_WRITE 0x56 ++#define PKT_PIPE_MODE_WRITE 0x57 ++ ++/* HDLC packet status values - desc->status */ ++#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */ ++#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ ++#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ ++#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving ++ this packet (if buf_len < pkt_len) */ ++#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */ ++#define ERR_HDLC_ABORT 6 /* abort sequence received */ ++#define ERR_DISCONNECTING 7 /* disconnect is in progress */ ++ ++#define CLOCK_EXT 0 ++#define CLOCK_INT 1 ++ ++enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704}; ++enum rx_tx_bit { ++ TX_BIT = 0, ++ RX_BIT = 1 ++}; ++enum chan_bit { ++ CHAN_0 = (1 << 0), ++ CHAN_1 = (1 << 1), ++ CHAN_2 = (1 << 2), ++ CHAN_3 = (1 << 3), ++ CHAN_4 = (1 << 4), ++ CHAN_5 = (1 << 5), ++ CHAN_6 = (1 << 6), ++ CHAN_7 = (1 << 7), ++ CHAN_8 = (1 << 8), ++ CHAN_9 = (1 << 9), ++ CHAN_10 = (1 << 10), ++ CHAN_11 = (1 << 11), ++ CHAN_12 = (1 << 12), ++ CHAN_13 = (1 << 13), ++ CHAN_14 = (1 << 14), ++ CHAN_15 = (1 << 15) ++}; ++ ++enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST }; ++ ++#ifdef __ARMEB__ ++typedef struct sk_buff buffer_t; ++#define free_buffer dev_kfree_skb ++#define free_buffer_irq dev_kfree_skb_irq ++#else ++typedef void buffer_t; ++#define free_buffer kfree ++#define free_buffer_irq kfree ++#endif ++ ++struct hss_device { ++ struct port *port; ++ unsigned int open_count, excl_open; ++ unsigned long tx_loc, rx_loc; /* bytes */ ++ unsigned long tx_frame, rx_frame; /* Frames */ ++ u8 id, chan_count; ++ u8 log_channels[MAX_CHANNELS]; ++ ++ u8 *rx_buf; ++ u8 *tx_buf; ++ ++ size_t rx_buffer_size; ++ size_t rx_period_size; ++ size_t tx_buffer_size; ++ size_t tx_period_size; ++ ++ void (*rx_callback)(void *data); ++ void *rx_data; ++ void (*tx_callback)(void *data); ++ void *tx_data; ++ void *private_data; ++}; ++ ++extern struct hss_device *hss_handle[32]; ++extern struct port *hss_port[2]; ++ ++struct port { ++ unsigned char init; ++ ++ struct device *dev; ++ ++ struct tasklet_struct task; ++ unsigned int id; ++ unsigned long chan_rx_bitmap; ++ unsigned long chan_tx_bitmap; ++ unsigned char chan_open; ++ ++ /* the following fields must be protected by npe_lock */ ++ enum mode mode; ++ unsigned int clock_type, clock_rate, loopback; ++ unsigned int frame_size, frame_sync_offset; ++ unsigned int next_rx_frame; ++ ++ struct hss_device *chan_devices[MAX_CHAN_DEVICES]; ++ u32 chan_tx_buf_phys, chan_rx_buf_phys; ++ u32 chan_tx_pointers_phys; ++ u32 *chan_tx_pointers; ++ u8 *chan_rx_buf; ++ u8 *chan_tx_buf; ++ u8 *tx_lists[CHAN_TX_LISTS][8]; ++ u8 *rx_frames[8][CHAN_TX_LISTS]; ++ unsigned int chan_open_count, hdlc_open; ++ unsigned int chan_started, initialized, just_set_offset; ++ unsigned int chan_last_rx, chan_last_tx; ++ ++ /* assigned channels, may be invalid with given frame length or mode */ ++ u8 channels[MAX_CHANNELS]; ++ int msg_count; ++}; ++ ++/* NPE message structure */ ++struct msg { ++#ifdef __ARMEB__ ++ u8 cmd, unused, hss_port, index; ++ union { ++ struct { u8 data8a, data8b, data8c, data8d; }; ++ struct { u16 data16a, data16b; }; ++ struct { u32 data32; }; ++ }; ++#else ++ u8 index, hss_port, unused, cmd; ++ union { ++ struct { u8 data8d, data8c, data8b, data8a; }; ++ struct { u16 data16b, data16a; }; ++ struct { u32 data32; }; ++ }; ++#endif ++}; ++ ++#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ ++ (n) * sizeof(struct desc)) ++#define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) ++ ++#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ ++ ((n) + RX_DESCS) * sizeof(struct desc)) ++#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) ++ ++int hss_prepare_chan(struct port *port); ++void hss_chan_stop(struct port *port); ++ ++struct hss_device *hss_init(int id, int channel); ++int hss_chan_open(struct hss_device *hdev); ++int hss_chan_close(struct hss_device *hdev); ++ ++int hss_set_tx_callback(struct hss_device *hdev, void (*tx_callback)(void *), void *tx_data); ++int hss_set_rx_callback(struct hss_device *hdev, void (*rx_callback)(void *), void *rx_data); ++int hss_tx_start(struct hss_device *hdev); ++int hss_tx_stop(struct hss_device *hdev); ++int hss_rx_start(struct hss_device *hdev); ++int hss_rx_stop(struct hss_device *hdev); ++ ++int hss_config_rx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size); ++int hss_config_tx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size); ++unsigned long hss_curr_offset_rx(struct hss_device *hdev); ++unsigned long hss_curr_offset_tx(struct hss_device *hdev); ++ diff --git a/target/linux/ixp4xx/patches-4.1/180-tw5334_support.patch b/target/linux/ixp4xx/patches-4.1/180-tw5334_support.patch new file mode 100644 index 0000000..b56fbb7 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/180-tw5334_support.patch @@ -0,0 +1,287 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -160,6 +160,14 @@ config ARCH_PRPMC1100 + PrPCM1100 Processor Mezanine Module. For more information on + this platform, see . + ++config MACH_TW5334 ++ bool "Titan Wireless TW-533-4" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the Titan ++ Wireless TW533-4. For more information on this platform, ++ see http://openwrt.org ++ + config MACH_NAS100D + bool + prompt "NAS100D" +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -24,6 +24,7 @@ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sid + obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o ++obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o + + obj-y += common.o + +@@ -49,6 +50,7 @@ obj-$(CONFIG_MACH_SIDEWINDER) += sidewin + obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o ++obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -44,7 +44,7 @@ static __inline__ void __arch_decomp_set + machine_is_gateway7001() || machine_is_wg302v2() || + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro() || +- machine_is_wrt300nv2()) ++ machine_is_wrt300nv2() || machine_is_tw5334()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/tw5334-pci.c +@@ -0,0 +1,68 @@ ++/* ++ * arch/arch/mach-ixp4xx/tw5334-pci.c ++ * ++ * PCI setup routines for the Titan Wireless TW-533-4 ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init tw5334_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO0, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init tw5334_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 12) ++ return IRQ_IXP4XX_GPIO6; ++ else if (slot == 13) ++ return IRQ_IXP4XX_GPIO2; ++ else if (slot == 14) ++ return IRQ_IXP4XX_GPIO1; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO0; ++ else return -1; ++} ++ ++struct hw_pci tw5334_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = tw5334_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = tw5334_map_irq, ++}; ++ ++int __init tw5334_pci_init(void) ++{ ++ if (machine_is_tw5334()) ++ pci_common_init(&tw5334_pci); ++ return 0; ++} ++ ++subsys_initcall(tw5334_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/tw5334-setup.c +@@ -0,0 +1,167 @@ ++/* ++ * arch/arm/mach-ixp4xx/tw5334-setup.c ++ * ++ * Board setup for the Titan Wireless TW-533-4 ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data tw5334_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource tw5334_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device tw5334_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &tw5334_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &tw5334_flash_resource, ++}; ++ ++static struct resource tw5334_uart_resource = { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port tw5334_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device tw5334_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = tw5334_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &tw5334_uart_resource, ++}; ++ ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info tw5334_plat_eth[] = { ++ { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device tw5334_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = tw5334_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = tw5334_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *tw5334_devices[] __initdata = { ++ &tw5334_flash, ++ &tw5334_uart, ++ &tw5334_eth[0], ++ &tw5334_eth[1], ++}; ++ ++static void __init tw5334_init(void) ++{ ++ uint8_t __iomem *f; ++ int i; ++ ++ ixp4xx_sys_init(); ++ ++ tw5334_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ tw5334_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(tw5334_devices, ARRAY_SIZE(tw5334_devices)); ++ ++ /* ++ * Map in a portion of the flash and read the MAC addresses. ++ * Since it is stored in BE in the flash itself, we need to ++ * byteswap it if we're in LE mode. ++ */ ++ f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x1000000); ++ if (f) { ++ for (i = 0; i < 6; i++) { ++#ifdef __ARMEB__ ++ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + i); ++ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + i); ++#else ++ tw5334_plat_eth[0].hwaddr[i] = readb(f + 0xFC0422 + (i^3)); ++ tw5334_plat_eth[1].hwaddr[i] = readb(f + 0xFC043B + (i^3)); ++#endif ++ } ++ iounmap(f); ++ } ++ ++ printk(KERN_INFO "TW-533-4: Using MAC address %pM for port 0\n", ++ tw5334_plat_eth[0].hwaddr); ++ printk(KERN_INFO "TW-533-4: Using MAC address %pM for port 1\n", ++ tw5334_plat_eth[1].hwaddr); ++} ++ ++#ifdef CONFIG_MACH_TW5334 ++MACHINE_START(TW5334, "Titan Wireless TW-533-4") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = tw5334_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-4.1/185-mi424wr_support.patch b/target/linux/ixp4xx/patches-4.1/185-mi424wr_support.patch new file mode 100644 index 0000000..81713b3 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/185-mi424wr_support.patch @@ -0,0 +1,507 @@ +--- a/arch/arm/configs/ixp4xx_defconfig ++++ b/arch/arm/configs/ixp4xx_defconfig +@@ -26,6 +26,7 @@ CONFIG_MACH_NAS100D=y + CONFIG_MACH_DSMG600=y + CONFIG_MACH_FSG=y + CONFIG_MACH_GTWX5715=y ++CONFIG_MACH_MI424WR=y + CONFIG_IXP4XX_QMGR=y + CONFIG_IXP4XX_NPE=y + # CONFIG_ARM_THUMB is not set +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -258,6 +258,13 @@ config MACH_MIC256 + Say 'Y' here if you want your kernel to support the MIC256 + board from OMICRON electronics GmbH. + ++config MACH_MI424WR ++ bool "Actiontec MI424WR" ++ depends on ARCH_IXP4XX ++ select PCI ++ help ++ Add support for the Actiontec MI424-WR. ++ + comment "IXP4xx Options" + + config IXP4XX_INDIRECT_PCI +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixd + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o ++obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o + + obj-y += common.o + +@@ -51,6 +52,7 @@ obj-$(CONFIG_MACH_COMPEXWP18) += compex4 + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o + obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o ++obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/mi424wr-pci.c +@@ -0,0 +1,70 @@ ++/* ++ * arch/arm/mach-ixp4xx/mi424wr-pci.c ++ * ++ * Actiontec MI424WR board-level PCI initialization ++ * ++ * Copyright (C) 2008 Jose Vasconcellos ++ * ++ * Maintainer: Jose Vasconcellos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* PCI controller GPIO to IRQ pin mappings ++ * This information was obtained from Actiontec's GPL release. ++ * ++ * INTA INTB ++ * SLOT 13 8 6 ++ * SLOT 14 7 8 ++ * SLOT 15 6 7 ++ */ ++ ++void __init mi424wr_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init mi424wr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 13) ++ return IRQ_IXP4XX_GPIO8; ++ if (slot == 14) ++ return IRQ_IXP4XX_GPIO7; ++ if (slot == 15) ++ return IRQ_IXP4XX_GPIO6; ++ ++ return -1; ++} ++ ++struct hw_pci mi424wr_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = mi424wr_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = mi424wr_map_irq, ++}; ++ ++int __init mi424wr_pci_init(void) ++{ ++ if (machine_is_mi424wr()) ++ pci_common_init(&mi424wr_pci); ++ return 0; ++} ++ ++subsys_initcall(mi424wr_pci_init); ++ +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/mi424wr-setup.c +@@ -0,0 +1,387 @@ ++/* ++ * arch/arm/mach-ixp4xx/mi424wr-setup.c ++ * ++ * Actiontec MI424-WR board setup ++ * Copyright (c) 2008 Jose Vasconcellos ++ * ++ * Based on Gemtek GTWX5715 by ++ * Copyright (C) 2004 George T. Joseph ++ * Derived from Coyote ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * GPIO 2,3,4 and 9 are hard wired to the Micrel/Kendin KS8995M Switch ++ * and operate as an SPI type interface. The details of the interface ++ * are available on Kendin/Micrel's web site. ++ */ ++ ++#define MI424WR_KSSPI_SELECT 9 ++#define MI424WR_KSSPI_TXD 4 ++#define MI424WR_KSSPI_CLOCK 2 ++#define MI424WR_KSSPI_RXD 3 ++ ++/* ++ * The "reset" button is wired to GPIO 10. ++ * The GPIO is brought "low" when the button is pushed. ++ */ ++ ++#define MI424WR_BUTTON_GPIO 10 ++#define MI424WR_BUTTON_IRQ IRQ_IXP4XX_GPIO10 ++ ++#define MI424WR_MOCA_WAN_LED 11 ++ ++/* Latch on CS1 - taken from Actiontec's 2.4 source code ++ * ++ * default latch value ++ * 0 - power alarm led (red) 0 (off) ++ * 1 - power led (green) 0 (off) ++ * 2 - wireless led (green) 1 (off) ++ * 3 - no internet led (red) 0 (off) ++ * 4 - internet ok led (green) 0 (off) ++ * 5 - moca LAN 0 (off) ++ * 6 - WAN alarm led (red) 0 (off) ++ * 7 - PCI reset 1 (not reset) ++ * 8 - IP phone 1 led (green) 1 (off) ++ * 9 - IP phone 2 led (green) 1 (off) ++ * 10 - VOIP ready led (green) 1 (off) ++ * 11 - PSTN relay 1 control 0 (PSTN) ++ * 12 - PSTN relay 1 control 0 (PSTN) ++ * 13 - N/A ++ * 14 - N/A ++ * 15 - N/A ++ */ ++ ++#define MI424WR_LATCH_MASK 0x04 ++#define MI424WR_LATCH_DEFAULT 0x1f86 ++ ++#define MI424WR_LATCH_ALARM_LED 0x00 ++#define MI424WR_LATCH_POWER_LED 0x01 ++#define MI424WR_LATCH_WIRELESS_LED 0x02 ++#define MI424WR_LATCH_INET_DOWN_LED 0x03 ++#define MI424WR_LATCH_INET_OK_LED 0x04 ++#define MI424WR_LATCH_MOCA_LAN_LED 0x05 ++#define MI424WR_LATCH_WAN_ALARM_LED 0x06 ++#define MI424WR_LATCH_PCI_RESET 0x07 ++#define MI424WR_LATCH_PHONE1_LED 0x08 ++#define MI424WR_LATCH_PHONE2_LED 0x09 ++#define MI424WR_LATCH_VOIP_LED 0x10 ++#define MI424WR_LATCH_PSTN_RELAY1 0x11 ++#define MI424WR_LATCH_PSTN_RELAY2 0x12 ++ ++/* initialize CS1 to default timings, Intel style, 16-bit bus */ ++#define MI424WR_CS1_CONFIG 0x80000002 ++ ++/* Define both UARTs but they are not easily accessible. ++ */ ++ ++static struct resource mi424wr_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++ ++static struct plat_serial8250_port mi424wr_uart_platform_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device mi424wr_uart_device = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = mi424wr_uart_platform_data, ++ .num_resources = ARRAY_SIZE(mi424wr_uart_resources), ++ .resource = mi424wr_uart_resources, ++}; ++ ++static struct flash_platform_data mi424wr_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource mi424wr_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device mi424wr_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev.platform_data = &mi424wr_flash_data, ++ .num_resources = 1, ++ .resource = &mi424wr_flash_resource, ++}; ++ ++static int mi424wr_spi_boardinfo_setup(struct spi_board_info *bi, ++ struct spi_master *master, void *data) ++{ ++ ++ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias)); ++ ++ bi->max_speed_hz = 5000000 /* Hz */; ++ bi->bus_num = master->bus_num; ++ bi->mode = SPI_MODE_0; ++ ++ return 0; ++} ++ ++static struct spi_gpio_platform_data mi424wr_spi_bus_data = { ++ .pin_cs = MI424WR_KSSPI_SELECT, ++ .pin_clk = MI424WR_KSSPI_CLOCK, ++ .pin_miso = MI424WR_KSSPI_RXD, ++ .pin_mosi = MI424WR_KSSPI_TXD, ++ .cs_activelow = 1, ++ .no_spi_delay = 1, ++ .boardinfo_setup = mi424wr_spi_boardinfo_setup, ++}; ++ ++static struct gpio_led mi424wr_gpio_led[] = { ++ { ++ .name = "moca-wan", /* green led */ ++ .gpio = MI424WR_MOCA_WAN_LED, ++ .active_low = 0, ++ } ++}; ++ ++static struct gpio_led_platform_data mi424wr_gpio_leds_data = { ++ .num_leds = 1, ++ .leds = mi424wr_gpio_led, ++}; ++ ++static struct platform_device mi424wr_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &mi424wr_gpio_leds_data, ++}; ++ ++static uint16_t latch_value = MI424WR_LATCH_DEFAULT; ++static uint16_t __iomem *iobase; ++ ++static void mi424wr_latch_set_led(u8 bit, enum led_brightness value) ++{ ++ ++ if (((MI424WR_LATCH_MASK >> bit) & 1) ^ (value == LED_OFF)) ++ latch_value &= ~(0x1 << bit); ++ else ++ latch_value |= (0x1 << bit); ++ ++ __raw_writew(latch_value, iobase); ++ ++} ++ ++static struct latch_led mi424wr_latch_led[] = { ++ { ++ .name = "power-alarm", ++ .bit = MI424WR_LATCH_ALARM_LED, ++ }, ++ { ++ .name = "power-ok", ++ .bit = MI424WR_LATCH_POWER_LED, ++ }, ++ { ++ .name = "wireless", /* green led */ ++ .bit = MI424WR_LATCH_WIRELESS_LED, ++ }, ++ { ++ .name = "inet-down", /* red led */ ++ .bit = MI424WR_LATCH_INET_DOWN_LED, ++ }, ++ { ++ .name = "inet-up", /* green led */ ++ .bit = MI424WR_LATCH_INET_OK_LED, ++ }, ++ { ++ .name = "moca-lan", /* green led */ ++ .bit = MI424WR_LATCH_MOCA_LAN_LED, ++ }, ++ { ++ .name = "wan-alarm", /* red led */ ++ .bit = MI424WR_LATCH_WAN_ALARM_LED, ++ } ++}; ++ ++static struct latch_led_platform_data mi424wr_latch_leds_data = { ++ .num_leds = ARRAY_SIZE(mi424wr_latch_led), ++ .mem = 0x51000000, ++ .leds = mi424wr_latch_led, ++ .set_led = mi424wr_latch_set_led, ++}; ++ ++static struct platform_device mi424wr_latch_leds = { ++ .name = "leds-latch", ++ .id = -1, ++ .dev.platform_data = &mi424wr_latch_leds_data, ++}; ++ ++static struct platform_device mi424wr_spi_bus = { ++ .name = "spi-gpio", ++ .id = 0, ++ .dev.platform_data = &mi424wr_spi_bus_data, ++}; ++ ++static struct eth_plat_info mi424wr_wan_data = { ++ .phy = 17, /* KS8721 */ ++ .rxq = 3, ++ .txreadyq = 20, ++}; ++ ++static struct eth_plat_info mi424wr_lan_data = { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */ ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct platform_device mi424wr_npe_devices[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = &mi424wr_lan_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = &mi424wr_wan_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct eth_plat_info mi424wr_wanD_data = { ++ .phy = 5, ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct eth_plat_info mi424wr_lanD_data = { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */ ++ .rxq = 3, ++ .txreadyq = 20, ++}; ++ ++static struct platform_device mi424wr_npeD_devices[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = &mi424wr_lanD_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = &mi424wr_wanD_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *mi424wr_devices[] __initdata = { ++ &mi424wr_uart_device, ++ &mi424wr_flash, ++ &mi424wr_gpio_leds, ++ &mi424wr_latch_leds, ++ &mi424wr_spi_bus, ++}; ++ ++static void __init mi424wr_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ mi424wr_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ mi424wr_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = MI424WR_CS1_CONFIG; ++ ++ /* configure button as input ++ */ ++ gpio_line_config(MI424WR_BUTTON_GPIO, IXP4XX_GPIO_IN); ++ ++ /* Initialize LEDs and enables PCI bus. ++ */ ++ iobase = ioremap_nocache(IXP4XX_EXP_BUS_BASE(1), 0x1000); ++ __raw_writew(latch_value, iobase); ++ ++ platform_add_devices(mi424wr_devices, ARRAY_SIZE(mi424wr_devices)); ++ ++ /* Need to figure out how to detect revD. ++ * Look for a revision argument sent by redboot. ++ */ ++#define revD 4 ++ if (system_rev == revD) { ++ platform_device_register(&mi424wr_npeD_devices[0]); ++ platform_device_register(&mi424wr_npeD_devices[1]); ++ } else { ++ platform_device_register(&mi424wr_npe_devices[0]); ++ platform_device_register(&mi424wr_npe_devices[1]); ++ } ++} ++ ++ ++MACHINE_START(MI424WR, "Actiontec MI424WR") ++ /* Maintainer: Jose Vasconcellos */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = mi424wr_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++ diff --git a/target/linux/ixp4xx/patches-4.1/190-cambria_support.patch b/target/linux/ixp4xx/patches-4.1/190-cambria_support.patch new file mode 100644 index 0000000..d6787f4 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/190-cambria_support.patch @@ -0,0 +1,1131 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -21,6 +21,14 @@ config MACH_AVILA + Avila Network Platform. For more information on this platform, + see . + ++config MACH_CAMBRIA ++ bool "Cambria" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the Gateworks ++ Cambria series. For more information on this platform, ++ see . ++ + config MACH_LOFT + bool "Loft" + depends on MACH_AVILA +@@ -218,7 +226,7 @@ config CPU_IXP46X + + config CPU_IXP43X + bool +- depends on MACH_KIXRP435 ++ depends on MACH_KIXRP435 || MACH_CAMBRIA + default y + + config MACH_GTWX5715 +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -7,6 +7,7 @@ obj-pci-n := + + obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o ++obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o + obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o + obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o + obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o +@@ -31,6 +32,7 @@ obj-y += common.o + + obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o + obj-$(CONFIG_MACH_AVILA) += avila-setup.o ++obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o + obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o + obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o + obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/cambria-pci.c +@@ -0,0 +1,78 @@ ++/* ++ * arch/arch/mach-ixp4xx/cambria-pci.c ++ * ++ * PCI setup routines for Gateworks Cambria series ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++extern void ixp4xx_pci_preinit(void); ++extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); ++extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); ++ ++void __init cambria_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init cambria_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else if (slot == 3) ++ return IRQ_IXP4XX_GPIO9; ++ else if (slot == 4) ++ return IRQ_IXP4XX_GPIO8; ++ else if (slot == 6) ++ return IRQ_IXP4XX_GPIO10; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO8; ++ ++ else return -1; ++} ++ ++struct hw_pci cambria_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = cambria_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = cambria_map_irq, ++}; ++ ++int __init cambria_pci_init(void) ++{ ++ if (machine_is_cambria()) ++ pci_common_init(&cambria_pci); ++ return 0; ++} ++ ++subsys_initcall(cambria_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/cambria-setup.c +@@ -0,0 +1,1003 @@ ++/* ++ * arch/arm/mach-ixp4xx/cambria-setup.c ++ * ++ * Board setup for the Gateworks Cambria series ++ * ++ * Copyright (C) 2008 Imre Kaloz ++ * Copyright (C) 2012 Gateworks Corporation ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ * Tim Harvey ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) ++ ++struct cambria_board_info { ++ unsigned char *model; ++ void (*setup)(void); ++}; ++ ++static struct cambria_board_info *cambria_info __initdata; ++ ++static struct flash_platform_data cambria_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource cambria_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device cambria_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &cambria_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &cambria_flash_resource, ++}; ++ ++static struct i2c_gpio_platform_data cambria_i2c_gpio_data = { ++ .sda_pin = 7, ++ .scl_pin = 6, ++}; ++ ++static struct platform_device cambria_i2c_gpio = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &cambria_i2c_gpio_data, ++ }, ++}; ++ ++#ifdef SFP_SERIALID ++static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpa_data = { ++ .sda_pin = 113, ++ .scl_pin = 112, ++ .sda_is_open_drain = 0, ++ .scl_is_open_drain = 0, ++}; ++ ++static struct platform_device cambria_i2c_gpio_sfpa = { ++ .name = "i2c-gpio", ++ .id = 1, ++ .dev = { ++ .platform_data = &cambria_i2c_gpio_sfpa_data, ++ }, ++}; ++ ++static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpb_data = { ++ .sda_pin = 115, ++ .scl_pin = 114, ++ .sda_is_open_drain = 0, ++ .scl_is_open_drain = 0, ++}; ++ ++static struct platform_device cambria_i2c_gpio_sfpb = { ++ .name = "i2c-gpio", ++ .id = 2, ++ .dev = { ++ .platform_data = &cambria_i2c_gpio_sfpb_data, ++ }, ++}; ++#endif // #ifdef SFP_SERIALID ++ ++static struct eth_plat_info cambria_npec_data = { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct eth_plat_info cambria_npea_data = { ++ .phy = 2, ++ .rxq = 2, ++ .txreadyq = 19, ++}; ++ ++static struct platform_device cambria_npec_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = &cambria_npec_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct platform_device cambria_npea_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEA, ++ .dev.platform_data = &cambria_npea_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct resource cambria_uart_resource = { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port cambria_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device cambria_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = cambria_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &cambria_uart_resource, ++}; ++ ++static struct resource cambria_optional_uart_resources[] = { ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x53000000, ++ .end = 0x53000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x52000000, ++ .end = 0x52000fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = 0x53000000, ++ .end = 0x53000fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port cambria_optional_uart_data[] = { ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM_DELAY, ++ .regshift = 0, ++ .uartclk = 1843200, ++ .rw_delay = 10, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM_DELAY, ++ .regshift = 0, ++ .uartclk = 1843200, ++ .rw_delay = 10, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ }, ++ { }, ++}; ++ ++static struct platform_device cambria_optional_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM1, ++ .dev.platform_data = cambria_optional_uart_data, ++ .num_resources = 2, ++ .resource = cambria_optional_uart_resources, ++}; ++ ++static struct resource cambria_pata_resources[] = { ++ { ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "intrq", ++ .start = IRQ_IXP4XX_GPIO12, ++ .end = IRQ_IXP4XX_GPIO12, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct ixp4xx_pata_data cambria_pata_data = { ++ .cs0_bits = 0xbfff3c03, ++ .cs1_bits = 0xbfff3c03, ++}; ++ ++static struct platform_device cambria_pata = { ++ .name = "pata_ixp4xx_cf", ++ .id = 0, ++ .dev.platform_data = &cambria_pata_data, ++ .num_resources = ARRAY_SIZE(cambria_pata_resources), ++ .resource = cambria_pata_resources, ++}; ++ ++static struct gpio_led cambria_gpio_leds[] = { ++ { ++ .name = "user", ++ .gpio = 5, ++ .active_low = 1, ++ }, ++ { ++ .name = "user2", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "user3", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "user4", ++ .gpio = 0, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_led_platform_data cambria_gpio_leds_data = { ++ .num_leds = 1, ++ .leds = cambria_gpio_leds, ++}; ++ ++static struct platform_device cambria_gpio_leds_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &cambria_gpio_leds_data, ++}; ++ ++static struct resource cambria_gpio_resources[] = { ++ { ++ .name = "gpio", ++ .flags = 0, ++ }, ++}; ++ ++static struct gpio cambria_gpios_gw2350[] = { ++ // ARM GPIO ++#if 0 // configured from bootloader ++ { 0, GPIOF_IN, "ARM_DIO0" }, ++ { 1, GPIOF_IN, "ARM_DIO1" }, ++ { 2, GPIOF_IN, "ARM_DIO2" }, ++ { 3, GPIOF_IN, "ARM_DIO3" }, ++ { 4, GPIOF_IN, "ARM_DIO4" }, ++ { 5, GPIOF_IN, "ARM_DIO5" }, ++ { 12, GPIOF_OUT_INIT_HIGH, "WDOGEN#" }, ++#endif ++ { 8, GPIOF_IN, "ARM_DIO8" }, ++ { 9, GPIOF_IN, "ARM_DIO9" }, ++}; ++ ++static struct gpio cambria_gpios_gw2358[] = { ++ // ARM GPIO ++#if 0 // configured from bootloader ++ { 0, GPIOF_IN, "*VINLOW#" }, ++ { 2, GPIOF_IN, "*GPS_PPS" }, ++ { 3, GPIOF_IN, "*GPS_IRQ#" }, ++ { 4, GPIOF_IN, "*RS485_IRQ#" }, ++ { 5, GPIOF_IN, "*SER_EN#" }, ++ { 14, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" }, ++#endif ++}; ++ ++static struct gpio cambria_gpios_gw2359[] = { ++ // ARM GPIO ++#if 0 // configured from bootloader ++ { 0, GPIOF_IN, "*PCA_IRQ#" }, ++ { 1, GPIOF_IN, "ARM_DIO1" }, ++ { 2, GPIOF_IN, "ARM_DIO2" }, ++ { 3, GPIOF_IN, "ARM_DIO3" }, ++ { 4, GPIOF_IN, "ARM_DIO4" }, ++ { 5, GPIOF_IN, "ARM_DIO5" }, ++ { 8, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" }, ++#endif ++ { 11, GPIOF_OUT_INIT_HIGH, "*SER_EN" }, // console serial enable ++ { 12, GPIOF_IN, "*GSC_IRQ#" }, ++ { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"}, ++ // GSC GPIO ++#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) ++ {100, GPIOF_IN, "*USER_PB#" }, ++#endif ++ {103, GPIOF_OUT_INIT_HIGH, "*5V_EN" }, // 5V aux supply enable ++ {108, GPIOF_IN, "*SMUXDA0" }, ++ {109, GPIOF_IN, "*SMUXDA1" }, ++ {110, GPIOF_IN, "*SMUXDA2" }, ++ {111, GPIOF_IN, "*SMUXDB0" }, ++ {112, GPIOF_IN, "*SMUXDB1" }, ++ {113, GPIOF_IN, "*SMUXDB2" }, ++ // PCA GPIO ++ {118, GPIOF_IN, "*USIM2_DET#"}, // USIM2 Detect ++ {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCI, 0=FP) ++ {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCI, 0=FP) ++ {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect ++ {123, GPIOF_OUT_INIT_HIGH, "*COM1_DTR#" }, // J21/J10 ++ {124, GPIOF_IN, "*COM1_DSR#" }, // J21/J10 ++ {127, GPIOF_IN, "PCA_DIO0" }, ++ {128, GPIOF_IN, "PCA_DIO1" }, ++ {129, GPIOF_IN, "PCA_DIO2" }, ++ {130, GPIOF_IN, "PCA_DIO3" }, ++ {131, GPIOF_IN, "PCA_DIO4" }, ++}; ++ ++static struct gpio cambria_gpios_gw2360[] = { ++ // ARM GPIO ++ { 0, GPIOF_IN, "*PCA_IRQ#" }, ++ { 11, GPIOF_OUT_INIT_LOW, "*SER0_EN#" }, ++ { 12, GPIOF_IN, "*GSC_IRQ#" }, ++ { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"}, ++ // GSC GPIO ++#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) ++ {100, GPIOF_IN, "*USER_PB#" }, ++#endif ++ {108, GPIOF_OUT_INIT_LOW, "*ENET1_EN#" }, // ENET1 TX Enable ++ {109, GPIOF_IN, "*ENET1_PRES#" }, // ENET1 Detect (0=SFP present) ++ {110, GPIOF_OUT_INIT_LOW, "*ENET2_EN#" }, // ENET2 TX Enable ++ {111, GPIOF_IN, "*ENET2_PRES#"}, // ENET2 Detect (0=SFP present) ++ // PCA GPIO ++ {116, GPIOF_OUT_INIT_HIGH, "*USIM2_LOC"}, // USIM2 Select (1=Loc, 0=Rem) ++ {117, GPIOF_IN, "*USIM2_DET_LOC#" },// USIM2 Detect (Local Slot) ++ {118, GPIOF_IN, "*USIM2_DET_REM#" },// USIM2 Detect (Remote Slot) ++ {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCIe1, 0=J1) ++ {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCIe2, 0=J1) ++ {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect ++ {127, GPIOF_IN, "DIO0" }, ++ {128, GPIOF_IN, "DIO1" }, ++ {129, GPIOF_IN, "DIO2" }, ++ {130, GPIOF_IN, "DIO3" }, ++ {131, GPIOF_IN, "DIO4" }, ++}; ++ ++static struct latch_led cambria_latch_leds[] = { ++ { ++ .name = "ledA", /* green led */ ++ .bit = 0, ++ }, ++ { ++ .name = "ledB", /* green led */ ++ .bit = 1, ++ }, ++ { ++ .name = "ledC", /* green led */ ++ .bit = 2, ++ }, ++ { ++ .name = "ledD", /* green led */ ++ .bit = 3, ++ }, ++ { ++ .name = "ledE", /* green led */ ++ .bit = 4, ++ }, ++ { ++ .name = "ledF", /* green led */ ++ .bit = 5, ++ }, ++ { ++ .name = "ledG", /* green led */ ++ .bit = 6, ++ }, ++ { ++ .name = "ledH", /* green led */ ++ .bit = 7, ++ } ++}; ++ ++static struct latch_led_platform_data cambria_latch_leds_data = { ++ .num_leds = 8, ++ .leds = cambria_latch_leds, ++ .mem = 0x53F40000, ++}; ++ ++static struct platform_device cambria_latch_leds_device = { ++ .name = "leds-latch", ++ .id = -1, ++ .dev.platform_data = &cambria_latch_leds_data, ++}; ++ ++static struct resource cambria_usb0_resources[] = { ++ { ++ .start = 0xCD000000, ++ .end = 0xCD000300, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = 32, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static struct resource cambria_usb1_resources[] = { ++ { ++ .start = 0xCE000000, ++ .end = 0xCE000300, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = 33, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 ehci_dma_mask = ~(u32)0; ++ ++static struct usb_ehci_pdata cambria_usb_pdata = { ++ .big_endian_desc = 1, ++ .big_endian_mmio = 1, ++ .has_tt = 1, ++ .caps_offset = 0x100, ++}; ++ ++static struct platform_device cambria_usb0_device = { ++ .name = "ehci-platform", ++ .id = 0, ++ .resource = cambria_usb0_resources, ++ .num_resources = ARRAY_SIZE(cambria_usb0_resources), ++ .dev = { ++ .dma_mask = &ehci_dma_mask, ++ .coherent_dma_mask = 0xffffffff, ++ .platform_data = &cambria_usb_pdata, ++ }, ++}; ++ ++static struct platform_device cambria_usb1_device = { ++ .name = "ehci-platform", ++ .id = 1, ++ .resource = cambria_usb1_resources, ++ .num_resources = ARRAY_SIZE(cambria_usb1_resources), ++ .dev = { ++ .dma_mask = &ehci_dma_mask, ++ .coherent_dma_mask = 0xffffffff, ++ .platform_data = &cambria_usb_pdata, ++ }, ++}; ++ ++static struct gw_i2c_pld_platform_data gw_i2c_pld_data0 = { ++ .gpio_base = 16, ++ .nr_gpio = 8, ++}; ++ ++static struct gw_i2c_pld_platform_data gw_i2c_pld_data1 = { ++ .gpio_base = 24, ++ .nr_gpio = 2, ++}; ++ ++ ++static struct gpio_keys_button cambria_gpio_buttons[] = { ++ { ++ .desc = "user", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .debounce_interval = 6, ++ .gpio = 25, ++ } ++}; ++ ++static struct gpio_keys_platform_data cambria_gpio_buttons_data = { ++ .poll_interval = 500, ++ .nbuttons = 1, ++ .buttons = cambria_gpio_buttons, ++}; ++ ++static struct platform_device cambria_gpio_buttons_device = { ++ .name = "gpio-keys-polled", ++ .id = -1, ++ .dev.platform_data = &cambria_gpio_buttons_data, ++}; ++ ++static struct platform_device *cambria_devices[] __initdata = { ++ &cambria_i2c_gpio, ++ &cambria_flash, ++ &cambria_uart, ++}; ++ ++static int cambria_register_gpio(struct gpio *array, size_t num) ++{ ++ int i, err, ret; ++ ++ ret = 0; ++ for (i = 0; i < num; i++, array++) { ++ const char *label = array->label; ++ if (label[0] == '*') ++ label++; ++ err = gpio_request_one(array->gpio, array->flags, label); ++ if (err) ++ ret = err; ++ else { ++ err = gpio_export(array->gpio, array->label[0] != '*'); ++ } ++ } ++ return ret; ++} ++ ++static void __init cambria_gw23xx_setup(void) ++{ ++ cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\ ++ (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12); ++ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; ++ ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++} ++ ++static void __init cambria_gw2350_setup(void) ++{ ++ *IXP4XX_EXP_CS2 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ cambria_optional_uart_data[0].mapbase = 0x52FF0000; ++ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff); ++ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3; ++ ++ *IXP4XX_EXP_CS3 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); ++ cambria_optional_uart_data[1].mapbase = 0x53FF0000; ++ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff); ++ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4; ++ ++ cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\ ++ (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12); ++ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; ++ ++ platform_device_register(&cambria_optional_uart); ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++ ++ platform_device_register(&cambria_usb0_device); ++ platform_device_register(&cambria_usb1_device); ++ ++ platform_device_register(&cambria_gpio_leds_device); ++ ++ /* gpio config (/sys/class/gpio) */ ++ cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2350)); ++} ++ ++static void __init cambria_gw2358_setup(void) ++{ ++ *IXP4XX_EXP_CS3 = 0xBFFF3C43; // bit0 = 16bit vs 8bit bus ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ cambria_optional_uart_data[0].mapbase = 0x53FC0000; ++ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff); ++ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3; ++ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); ++ cambria_optional_uart_data[1].mapbase = 0x53F80000; ++ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff); ++ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4; ++ ++ cambria_gpio_resources[0].start = (1 << 14) | (1 << 16) | (1 << 17) | (1 << 18) |\ ++ (1 << 19) | (1 << 20) | (1 << 24) | (1 << 25); ++ cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; ++ ++ platform_device_register(&cambria_optional_uart); ++ ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++ ++ platform_device_register(&cambria_usb0_device); ++ platform_device_register(&cambria_usb1_device); ++ ++ platform_device_register(&cambria_pata); ++ ++ cambria_gpio_leds[0].gpio = 24; ++ platform_device_register(&cambria_gpio_leds_device); ++ ++ platform_device_register(&cambria_latch_leds_device); ++ ++ platform_device_register(&cambria_gpio_buttons_device); ++ ++ /* gpio config (/sys/class/gpio) */ ++ cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2358)); ++} ++ ++static void __init cambria_gw2359_setup(void) ++{ ++#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE) ++ /* The mvswitch driver has some hard-coded values which could ++ * easily be turned into a platform resource if needed. For now they ++ * match our hardware configuration: ++ * MV_BASE 0x10 - phy base address ++ * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module) ++ * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1) ++ * ++ * The mvswitch driver registers a fixup which forces a driver match ++ * if phy_addr matches MV_BASE ++ * ++ * Two static defautl VLAN's are created: WAN port in 1, and all other ports ++ * in the other. ++ */ ++ cambria_npea_data.phy = 0x10; // mvswitch driver catches this ++#else ++ // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the genphy driver ++ cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++ // CPU NPE-C is in bridge bypass mode to Port4 PHY@0x14 ++ cambria_npec_data.phy = 0x14; ++#endif ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++ ++ platform_device_register(&cambria_usb0_device); ++ platform_device_register(&cambria_usb1_device); ++ ++ cambria_gpio_leds_data.num_leds = 3; ++ cambria_gpio_leds[0].name = "user1"; ++ cambria_gpio_leds[0].gpio = 125; // PNLLED1# ++ cambria_gpio_leds[1].gpio = 126; // PNLLED3# ++ cambria_gpio_leds[2].gpio = 119; // PNLLED4# ++ platform_device_register(&cambria_gpio_leds_device); ++ ++#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) ++ cambria_gpio_buttons[0].gpio = 100; ++ platform_device_register(&cambria_gpio_buttons_device); ++#endif ++ ++ /* gpio config (/sys/class/gpio) */ ++ cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2359)); ++} ++ ++static void __init cambria_gw2360_setup(void) ++{ ++ /* The GW2360 has 8 UARTs in addition to the 1 IXP4xxx UART. ++ * The chip-selects are expanded via a 3-to-8 decoder and CS2 ++ * and they are 8bit devices ++ */ ++ *IXP4XX_EXP_CS2 = 0xBFFF3C43; ++ cambria_optional_uart_data[0].mapbase = 0x52000000; ++ cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff); ++ cambria_optional_uart_data[0].uartclk = 18432000; ++ cambria_optional_uart_data[0].iotype = UPIO_MEM; ++ cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO2; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[1].mapbase = 0x52000008; ++ cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x52000008, 0x0fff); ++ cambria_optional_uart_data[1].uartclk = 18432000; ++ cambria_optional_uart_data[1].iotype = UPIO_MEM; ++ cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO3; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[2].mapbase = 0x52000010; ++ cambria_optional_uart_data[2].membase = (void __iomem *)ioremap(0x52000010, 0x0fff); ++ cambria_optional_uart_data[2].uartclk = 18432000; ++ cambria_optional_uart_data[2].iotype = UPIO_MEM; ++ cambria_optional_uart_data[2].irq = IRQ_IXP4XX_GPIO4; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[3].mapbase = 0x52000018; ++ cambria_optional_uart_data[3].membase = (void __iomem *)ioremap(0x52000018, 0x0fff); ++ cambria_optional_uart_data[3].uartclk = 18432000; ++ cambria_optional_uart_data[3].iotype = UPIO_MEM; ++ cambria_optional_uart_data[3].irq = IRQ_IXP4XX_GPIO5; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO5, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[4].mapbase = 0x52000020; ++ cambria_optional_uart_data[4].membase = (void __iomem *)ioremap(0x52000020, 0x0fff); ++ cambria_optional_uart_data[4].uartclk = 18432000; ++ cambria_optional_uart_data[4].iotype = UPIO_MEM; ++ cambria_optional_uart_data[4].irq = IRQ_IXP4XX_GPIO8; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[5].mapbase = 0x52000028; ++ cambria_optional_uart_data[5].membase = (void __iomem *)ioremap(0x52000028, 0x0fff); ++ cambria_optional_uart_data[5].uartclk = 18432000; ++ cambria_optional_uart_data[5].iotype = UPIO_MEM; ++ cambria_optional_uart_data[5].irq = IRQ_IXP4XX_GPIO9; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart_data[6].mapbase = 0x52000030; ++ cambria_optional_uart_data[6].membase = (void __iomem *)ioremap(0x52000030, 0x0fff); ++ cambria_optional_uart_data[6].uartclk = 18432000; ++ cambria_optional_uart_data[6].iotype = UPIO_MEM; ++ cambria_optional_uart_data[6].irq = IRQ_IXP4XX_GPIO10; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING); ++ ++ cambria_optional_uart.num_resources = 7, ++ platform_device_register(&cambria_optional_uart); ++ ++#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE) ++ /* The mvswitch driver has some hard-coded values which could ++ * easily be turned into a platform resource if needed. For now they ++ * match our hardware configuration: ++ * MV_BASE 0x10 - phy base address ++ * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module) ++ * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1) ++ * ++ * The mvswitch driver registers a fixup which forces a driver match ++ * if phy_addr matches MV_BASE ++ * ++ * Two static defautl VLAN's are created: WAN port in 1, and all other ports ++ * in the other. ++ */ ++ cambria_npea_data.phy = 0x10; // mvswitch driver catches this ++#else ++ // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the generic PHY driver ++ cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++#endif ++ ++ // disable genphy autonegotiation on NPE-C PHY (eth1) as its 100BaseFX ++ //cambria_npec_data.noautoneg = 1; // disable autoneg ++ cambria_npec_data.speed_10 = 0; // 100mbps ++ cambria_npec_data.half_duplex = 0; // full-duplex ++ platform_device_register(&cambria_npec_device); ++ platform_device_register(&cambria_npea_device); ++ ++ platform_device_register(&cambria_usb0_device); ++ platform_device_register(&cambria_usb1_device); ++ ++ cambria_gpio_leds_data.num_leds = 3; ++ cambria_gpio_leds[0].name = "user1"; ++ cambria_gpio_leds[0].gpio = 125; ++ cambria_gpio_leds[1].gpio = 126; ++ cambria_gpio_leds[2].gpio = 119; ++ platform_device_register(&cambria_gpio_leds_device); ++ ++#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) ++ cambria_gpio_buttons[0].gpio = 100; ++ platform_device_register(&cambria_gpio_buttons_device); ++#endif ++ ++#ifdef SFP_SERIALID ++ /* the SFP modules each have an i2c bus for serial ident via GSC GPIO ++ * To use these the i2c-gpio driver must be changed to use the _cansleep ++ * varients of gpio_get_value/gpio_set_value (I don't know why it doesn't ++ * use that anyway as it doesn't operate in an IRQ context). ++ * Additionally the i2c-gpio module must set the gpio to output-high prior ++ * to changing direction to an input to enable internal Pullups ++ */ ++ platform_device_register(&cambria_i2c_gpio_sfpa); ++ platform_device_register(&cambria_i2c_gpio_sfpb); ++#endif ++ ++ /* gpio config (/sys/class/gpio) */ ++ cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2360)); ++} ++ ++static struct cambria_board_info cambria_boards[] __initdata = { ++ { ++ .model = "GW2350", ++ .setup = cambria_gw2350_setup, ++ }, { ++ .model = "GW2351", ++ .setup = cambria_gw2350_setup, ++ }, { ++ .model = "GW2358", ++ .setup = cambria_gw2358_setup, ++ }, { ++ .model = "GW2359", ++ .setup = cambria_gw2359_setup, ++ }, { ++ .model = "GW2360", ++ .setup = cambria_gw2360_setup, ++ }, { ++ .model = "GW2371", ++ .setup = cambria_gw2358_setup, ++ } ++}; ++ ++static struct cambria_board_info * __init cambria_find_board_info(char *model) ++{ ++ int i; ++ model[6] = '\0'; ++ ++ for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) { ++ struct cambria_board_info *info = &cambria_boards[i]; ++ if (strcmp(info->model, model) == 0) ++ return info; ++ } ++ ++ return NULL; ++} ++ ++static struct memory_accessor *at24_mem_acc; ++ ++static void at24_setup(struct memory_accessor *mem_acc, void *context) ++{ ++ char mac_addr[ETH_ALEN]; ++ char model[7]; ++ ++ at24_mem_acc = mem_acc; ++ ++ /* Read MAC addresses */ ++ if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x0, 6) == 6) { ++ memcpy(&cambria_npec_data.hwaddr, mac_addr, ETH_ALEN); ++ } ++ if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x6, 6) == 6) { ++ memcpy(&cambria_npea_data.hwaddr, mac_addr, ETH_ALEN); ++ } ++ ++ /* Read the first 6 bytes of the model number */ ++ if (at24_mem_acc->read(at24_mem_acc, model, 0x20, 6) == 6) { ++ cambria_info = cambria_find_board_info(model); ++ } ++ ++} ++ ++static struct at24_platform_data cambria_eeprom_info = { ++ .byte_len = 1024, ++ .page_size = 16, ++ .flags = AT24_FLAG_READONLY, ++ .setup = at24_setup, ++}; ++ ++static struct pca953x_platform_data cambria_pca_data = { ++ .gpio_base = 100, ++ .irq_base = -1, ++}; ++ ++static struct pca953x_platform_data cambria_pca2_data = { ++ .gpio_base = 116, ++ .irq_base = -1, ++}; ++ ++static struct i2c_board_info __initdata cambria_i2c_board_info[] = { ++ { ++ I2C_BOARD_INFO("pca9555", 0x23), ++ .platform_data = &cambria_pca_data, ++ }, ++ { ++ I2C_BOARD_INFO("pca9555", 0x27), ++ .platform_data = &cambria_pca2_data, ++ }, ++ { ++ I2C_BOARD_INFO("ds1672", 0x68), ++ }, ++ { ++ I2C_BOARD_INFO("gsp", 0x29), ++ }, ++ { ++ I2C_BOARD_INFO("ad7418", 0x28), ++ }, ++ { ++ I2C_BOARD_INFO("24c08", 0x51), ++ .platform_data = &cambria_eeprom_info ++ }, ++ { ++ I2C_BOARD_INFO("gw_i2c_pld", 0x56), ++ .platform_data = &gw_i2c_pld_data0, ++ }, ++ { ++ I2C_BOARD_INFO("gw_i2c_pld", 0x57), ++ .platform_data = &gw_i2c_pld_data1, ++ }, ++}; ++ ++static void __init cambria_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; // make sure window is writable ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(ARRAY_AND_SIZE(cambria_devices)); ++ ++ cambria_pata_resources[0].start = 0x53e00000; ++ cambria_pata_resources[0].end = 0x53e3ffff; ++ ++ cambria_pata_resources[1].start = 0x53e40000; ++ cambria_pata_resources[1].end = 0x53e7ffff; ++ ++ cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3; ++ cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3; ++ ++ i2c_register_board_info(0, ARRAY_AND_SIZE(cambria_i2c_board_info)); ++} ++ ++static int __init cambria_model_setup(void) ++{ ++ if (!machine_is_cambria()) ++ return 0; ++ ++ if (cambria_info) { ++ printk(KERN_DEBUG "Running on Gateworks Cambria %s\n", ++ cambria_info->model); ++ cambria_info->setup(); ++ } else { ++ printk(KERN_INFO "Unknown/missing Cambria model number" ++ " -- defaults will be used\n"); ++ cambria_gw23xx_setup(); ++ } ++ ++ return 0; ++} ++late_initcall(cambria_model_setup); ++ ++MACHINE_START(CAMBRIA, "Gateworks Cambria series") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = cambria_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END diff --git a/target/linux/ixp4xx/patches-4.1/201-npe_driver_print_license_location.patch b/target/linux/ixp4xx/patches-4.1/201-npe_driver_print_license_location.patch new file mode 100644 index 0000000..f46b9c6 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/201-npe_driver_print_license_location.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c ++++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c +@@ -586,6 +586,8 @@ int npe_load_firmware(struct npe *npe, c + npe_reset(npe); + #endif + ++ print_npe(KERN_INFO, npe, "firmware's license can be found in /usr/share/doc/LICENSE.IPL\n"); ++ + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, " + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, + (image->id >> 8) & 0xFF, image->id & 0xFF); diff --git a/target/linux/ixp4xx/patches-4.1/203-npe_driver_mask_phy_features.patch b/target/linux/ixp4xx/patches-4.1/203-npe_driver_mask_phy_features.patch new file mode 100644 index 0000000..359873d --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/203-npe_driver_mask_phy_features.patch @@ -0,0 +1,13 @@ +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -1474,6 +1474,10 @@ static int eth_init_one(struct platform_ + goto err_free_mem; + } + ++ /* mask with MAC supported features */ ++ port->phydev->supported &= PHY_BASIC_FEATURES; ++ port->phydev->advertising = port->phydev->supported; ++ + port->phydev->irq = PHY_POLL; + + if ((err = register_netdev(dev))) diff --git a/target/linux/ixp4xx/patches-4.1/205-npe_driver_separate_phy_functions.patch b/target/linux/ixp4xx/patches-4.1/205-npe_driver_separate_phy_functions.patch new file mode 100644 index 0000000..6d1eb7b --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/205-npe_driver_separate_phy_functions.patch @@ -0,0 +1,131 @@ +From e3eab80fb5d0a7d7fdb0f2f231b27161d5ec3804 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski +Date: Sun, 30 Jun 2013 15:52:53 +0200 +Subject: [PATCH 23/36] 205-npe_driver_separate_phy_functions.patch + +--- + drivers/net/ethernet/xscale/ixp4xx_eth.c | 70 ++++++++++++++++++++++-------- + 1 file changed, 51 insertions(+), 19 deletions(-) + +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -589,6 +589,51 @@ static void ixp4xx_adjust_link(struct ne + dev->name, port->speed, port->duplex ? "full" : "half"); + } + ++static int ixp4xx_phy_connect(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ struct eth_plat_info *plat = port->plat; ++ char phy_id[MII_BUS_ID_SIZE + 3]; ++ ++ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, ++ mdio_bus->id, plat->phy); ++ port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, ++ PHY_INTERFACE_MODE_MII); ++ if (IS_ERR(port->phydev)) { ++ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); ++ return PTR_ERR(port->phydev); ++ } ++ ++ /* mask with MAC supported features */ ++ port->phydev->supported &= PHY_BASIC_FEATURES; ++ port->phydev->advertising = port->phydev->supported; ++ ++ port->phydev->irq = PHY_POLL; ++ ++ return 0; ++} ++ ++static void ixp4xx_phy_disconnect(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ ++ phy_disconnect(port->phydev); ++} ++ ++static void ixp4xx_phy_start(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ ++ port->speed = 0; /* force "link up" message */ ++ phy_start(port->phydev); ++} ++ ++static void ixp4xx_phy_stop(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ ++ phy_stop(port->phydev); ++} + + static inline void debug_pkt(struct net_device *dev, const char *func, + u8 *data, int len) +@@ -1259,8 +1304,7 @@ static int eth_open(struct net_device *d + return err; + } + +- port->speed = 0; /* force "link up" message */ +- phy_start(port->phydev); ++ ixp4xx_phy_start(dev); + + for (i = 0; i < ETH_ALEN; i++) + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); +@@ -1381,7 +1425,7 @@ static int eth_close(struct net_device * + printk(KERN_CRIT "%s: unable to disable loopback\n", + dev->name); + +- phy_stop(port->phydev); ++ ixp4xx_phy_stop(dev); + + if (!ports_open) + qmgr_disable_irq(TXDONE_QUEUE); +@@ -1407,7 +1451,6 @@ static int eth_init_one(struct platform_ + struct net_device *dev; + struct eth_plat_info *plat = dev_get_platdata(&pdev->dev); + u32 regs_phys; +- char phy_id[MII_BUS_ID_SIZE + 3]; + int err; + + if (!(dev = alloc_etherdev(sizeof(struct port)))) +@@ -1465,20 +1508,9 @@ static int eth_init_one(struct platform_ + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); + udelay(50); + +- snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, +- mdio_bus->id, plat->phy); +- port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, +- PHY_INTERFACE_MODE_MII); +- if (IS_ERR(port->phydev)) { +- err = PTR_ERR(port->phydev); ++ err = ixp4xx_phy_connect(dev); ++ if (err) + goto err_free_mem; +- } +- +- /* mask with MAC supported features */ +- port->phydev->supported &= PHY_BASIC_FEATURES; +- port->phydev->advertising = port->phydev->supported; +- +- port->phydev->irq = PHY_POLL; + + if ((err = register_netdev(dev))) + goto err_phy_dis; +@@ -1489,7 +1521,7 @@ static int eth_init_one(struct platform_ + return 0; + + err_phy_dis: +- phy_disconnect(port->phydev); ++ ixp4xx_phy_disconnect(dev); + err_free_mem: + npe_port_tab[NPE_ID(port->id)] = NULL; + release_resource(port->mem_res); +@@ -1506,7 +1538,7 @@ static int eth_remove_one(struct platfor + struct port *port = netdev_priv(dev); + + unregister_netdev(dev); +- phy_disconnect(port->phydev); ++ ixp4xx_phy_disconnect(dev); + npe_port_tab[NPE_ID(port->id)] = NULL; + npe_release(port->npe); + release_resource(port->mem_res); diff --git a/target/linux/ixp4xx/patches-4.1/206-npe_driver_add_update_link_function.patch b/target/linux/ixp4xx/patches-4.1/206-npe_driver_add_update_link_function.patch new file mode 100644 index 0000000..f1a7707 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/206-npe_driver_add_update_link_function.patch @@ -0,0 +1,98 @@ +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -177,7 +177,7 @@ struct port { + struct desc *desc_tab; /* coherent */ + u32 desc_tab_phys; + int id; /* logical port ID */ +- int speed, duplex; ++ int link, speed, duplex; + u8 firmware[4]; + int hwts_tx_en; + int hwts_rx_en; +@@ -558,37 +558,52 @@ static void ixp4xx_mdio_remove(void) + mdiobus_free(mdio_bus); + } + +- +-static void ixp4xx_adjust_link(struct net_device *dev) ++static void ixp4xx_update_link(struct net_device *dev) + { + struct port *port = netdev_priv(dev); +- struct phy_device *phydev = port->phydev; + +- if (!phydev->link) { +- if (port->speed) { +- port->speed = 0; +- printk(KERN_INFO "%s: link down\n", dev->name); +- } ++ if (!port->link) { ++ netif_carrier_off(dev); ++ printk(KERN_INFO "%s: link down\n", dev->name); + return; + } + +- if (port->speed == phydev->speed && port->duplex == phydev->duplex) +- return; +- +- port->speed = phydev->speed; +- port->duplex = phydev->duplex; +- +- if (port->duplex) ++ if (port->duplex == DUPLEX_FULL) + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, + &port->regs->tx_control[0]); + else + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, + &port->regs->tx_control[0]); + ++ netif_carrier_on(dev); + printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n", + dev->name, port->speed, port->duplex ? "full" : "half"); + } + ++static void ixp4xx_adjust_link(struct net_device *dev) ++{ ++ struct port *port = netdev_priv(dev); ++ struct phy_device *phydev = port->phydev; ++ int status_change = 0; ++ ++ if (phydev->link) { ++ if (port->duplex != phydev->duplex ++ || port->speed != phydev->speed) { ++ status_change = 1; ++ } ++ } ++ ++ if (phydev->link != port->link) ++ status_change = 1; ++ ++ port->link = phydev->link; ++ port->speed = phydev->speed; ++ port->duplex = phydev->duplex; ++ ++ if (status_change) ++ ixp4xx_update_link(dev); ++} ++ + static int ixp4xx_phy_connect(struct net_device *dev) + { + struct port *port = netdev_priv(dev); +@@ -624,7 +639,6 @@ static void ixp4xx_phy_start(struct net_ + { + struct port *port = netdev_priv(dev); + +- port->speed = 0; /* force "link up" message */ + phy_start(port->phydev); + } + +@@ -1515,6 +1529,10 @@ static int eth_init_one(struct platform_ + if ((err = register_netdev(dev))) + goto err_phy_dis; + ++ port->link = 0; ++ port->speed = 0; ++ port->duplex = -1; ++ + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, + npe_name(port->npe)); + diff --git a/target/linux/ixp4xx/patches-4.1/207-npe_driver_multiphy_support.patch b/target/linux/ixp4xx/patches-4.1/207-npe_driver_multiphy_support.patch new file mode 100644 index 0000000..32035ab --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/207-npe_driver_multiphy_support.patch @@ -0,0 +1,154 @@ +TODO: take care of additional PHYs through the PHY abstraction layer + +--- a/arch/arm/mach-ixp4xx/include/mach/platform.h ++++ b/arch/arm/mach-ixp4xx/include/mach/platform.h +@@ -74,7 +74,7 @@ extern unsigned long ixp4xx_exp_bus_size + /* + * Clock Speed Definitions. + */ +-#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ ++#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ + #define IXP4XX_UART_XTAL 14745600 + + /* +@@ -95,12 +95,23 @@ struct ixp4xx_pata_data { + #define IXP4XX_ETH_NPEB 0x10 + #define IXP4XX_ETH_NPEC 0x20 + ++#define IXP4XX_ETH_PHY_MAX_ADDR 32 ++ + /* Information about built-in Ethernet MAC interfaces */ + struct eth_plat_info { + u8 phy; /* MII PHY ID, 0 - 31 */ + u8 rxq; /* configurable, currently 0 - 31 only */ + u8 txreadyq; + u8 hwaddr[6]; ++ ++ u32 phy_mask; ++#if 0 ++ int speed; ++ int duplex; ++#else ++ int speed_10; ++ int half_duplex; ++#endif + }; + + /* Information about built-in HSS (synchronous serial) interfaces */ +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -610,6 +610,37 @@ static int ixp4xx_phy_connect(struct net + struct eth_plat_info *plat = port->plat; + char phy_id[MII_BUS_ID_SIZE + 3]; + ++ if (plat->phy == IXP4XX_ETH_PHY_MAX_ADDR) { ++#if 0 ++ switch (plat->speed) { ++ case SPEED_10: ++ case SPEED_100: ++ break; ++ default: ++ printk(KERN_ERR "%s: invalid speed (%d)\n", ++ dev->name, plat->speed); ++ return -EINVAL; ++ } ++ ++ switch (plat->duplex) { ++ case DUPLEX_HALF: ++ case DUPLEX_FULL: ++ break; ++ default: ++ printk(KERN_ERR "%s: invalid duplex mode (%d)\n", ++ dev->name, plat->duplex); ++ return -EINVAL; ++ } ++ port->speed = plat->speed; ++ port->duplex = plat->duplex; ++#else ++ port->speed = plat->speed_10 ? SPEED_10 : SPEED_100; ++ port->duplex = plat->half_duplex ? DUPLEX_HALF : DUPLEX_FULL; ++#endif ++ ++ return 0; ++ } ++ + snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, + mdio_bus->id, plat->phy); + port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, +@@ -632,21 +663,32 @@ static void ixp4xx_phy_disconnect(struct + { + struct port *port = netdev_priv(dev); + +- phy_disconnect(port->phydev); ++ if (port->phydev) ++ phy_disconnect(port->phydev); + } + + static void ixp4xx_phy_start(struct net_device *dev) + { + struct port *port = netdev_priv(dev); + +- phy_start(port->phydev); ++ if (port->phydev) { ++ phy_start(port->phydev); ++ } else { ++ port->link = 1; ++ ixp4xx_update_link(dev); ++ } + } + + static void ixp4xx_phy_stop(struct net_device *dev) + { + struct port *port = netdev_priv(dev); + +- phy_stop(port->phydev); ++ if (port->phydev) { ++ phy_stop(port->phydev); ++ } else { ++ port->link = 0; ++ ixp4xx_update_link(dev); ++ } + } + + static inline void debug_pkt(struct net_device *dev, const char *func, +@@ -1048,6 +1090,9 @@ static int eth_ioctl(struct net_device * + return hwtstamp_get(dev, req); + } + ++ if (!port->phydev) ++ return -EOPNOTSUPP; ++ + return phy_mii_ioctl(port->phydev, req, cmd); + } + +@@ -1068,18 +1113,30 @@ static void ixp4xx_get_drvinfo(struct ne + static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) + { + struct port *port = netdev_priv(dev); ++ ++ if (!port->phydev) ++ return -EOPNOTSUPP; ++ + return phy_ethtool_gset(port->phydev, cmd); + } + + static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) + { + struct port *port = netdev_priv(dev); ++ ++ if (!port->phydev) ++ return -EOPNOTSUPP; ++ + return phy_ethtool_sset(port->phydev, cmd); + } + + static int ixp4xx_nway_reset(struct net_device *dev) + { + struct port *port = netdev_priv(dev); ++ ++ if (!port->phydev) ++ return -EOPNOTSUPP; ++ + return phy_start_aneg(port->phydev); + } + diff --git a/target/linux/ixp4xx/patches-4.1/295-latch_led_driver.patch b/target/linux/ixp4xx/patches-4.1/295-latch_led_driver.patch new file mode 100644 index 0000000..fb08143 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/295-latch_led_driver.patch @@ -0,0 +1,201 @@ +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -271,6 +271,12 @@ config LEDS_LP8860 + on the LP8860 4 channel LED driver using the I2C communication + bus. + ++config LEDS_LATCH ++ tristate "LED Support for Memory Latched LEDs" ++ depends on LEDS_CLASS ++ help ++ -- To Do -- ++ + config LEDS_CLEVO_MAIL + tristate "Mail LED on Clevo notebook" + depends on LEDS_CLASS +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunf + obj-$(CONFIG_LEDS_PCA9532) += leds-pca9532.o + obj-$(CONFIG_LEDS_GPIO_REGISTER) += leds-gpio-register.o + obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o ++obj-$(CONFIG_LEDS_LATCH) += leds-latch.o + obj-$(CONFIG_LEDS_LP3944) += leds-lp3944.o + obj-$(CONFIG_LEDS_LP55XX_COMMON) += leds-lp55xx-common.o + obj-$(CONFIG_LEDS_LP5521) += leds-lp5521.o +--- /dev/null ++++ b/drivers/leds/leds-latch.c +@@ -0,0 +1,152 @@ ++/* ++ * LEDs driver for Memory Latched Devices ++ * ++ * Copyright (C) 2008 Gateworks Corp. ++ * Chris Lang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static unsigned int mem_keep = 0xFF; ++static spinlock_t mem_lock; ++static unsigned char *iobase; ++ ++struct latch_led_data { ++ struct led_classdev cdev; ++ struct work_struct work; ++ u8 new_level; ++ u8 bit; ++ void (*set_led)(u8 bit, enum led_brightness value); ++}; ++ ++static void latch_set_led(u8 bit, enum led_brightness value) ++{ ++ if (value == LED_OFF) ++ mem_keep |= (0x1 << bit); ++ else ++ mem_keep &= ~(0x1 << bit); ++ ++ writeb(mem_keep, iobase); ++} ++ ++static void latch_led_set(struct led_classdev *led_cdev, ++ enum led_brightness value) ++{ ++ struct latch_led_data *led_dat = ++ container_of(led_cdev, struct latch_led_data, cdev); ++ ++ raw_spin_lock(mem_lock); ++ ++ led_dat->set_led(led_dat->bit, value); ++ ++ raw_spin_unlock(mem_lock); ++} ++ ++static int latch_led_probe(struct platform_device *pdev) ++{ ++ struct latch_led_platform_data *pdata = pdev->dev.platform_data; ++ struct latch_led *cur_led; ++ struct latch_led_data *leds_data, *led_dat; ++ int i, ret = 0; ++ ++ if (!pdata) ++ return -EBUSY; ++ ++ leds_data = kzalloc(sizeof(struct latch_led_data) * pdata->num_leds, ++ GFP_KERNEL); ++ if (!leds_data) ++ return -ENOMEM; ++ ++ for (i = 0; i < pdata->num_leds; i++) { ++ cur_led = &pdata->leds[i]; ++ led_dat = &leds_data[i]; ++ ++ led_dat->cdev.name = cur_led->name; ++ led_dat->cdev.default_trigger = cur_led->default_trigger; ++ led_dat->cdev.brightness_set = latch_led_set; ++ led_dat->cdev.brightness = LED_OFF; ++ led_dat->bit = cur_led->bit; ++ led_dat->set_led = pdata->set_led ? pdata->set_led : latch_set_led; ++ ++ ret = led_classdev_register(&pdev->dev, &led_dat->cdev); ++ if (ret < 0) { ++ goto err; ++ } ++ } ++ ++ if (!pdata->set_led) { ++ iobase = ioremap_nocache(pdata->mem, 0x1000); ++ writeb(0xFF, iobase); ++ } ++ platform_set_drvdata(pdev, leds_data); ++ ++ return 0; ++ ++err: ++ if (i > 0) { ++ for (i = i - 1; i >= 0; i--) { ++ led_classdev_unregister(&leds_data[i].cdev); ++ } ++ } ++ ++ kfree(leds_data); ++ ++ return ret; ++} ++ ++static int latch_led_remove(struct platform_device *pdev) ++{ ++ int i; ++ struct latch_led_platform_data *pdata = pdev->dev.platform_data; ++ struct latch_led_data *leds_data; ++ ++ leds_data = platform_get_drvdata(pdev); ++ ++ for (i = 0; i < pdata->num_leds; i++) { ++ led_classdev_unregister(&leds_data[i].cdev); ++ cancel_work_sync(&leds_data[i].work); ++ } ++ ++ kfree(leds_data); ++ ++ return 0; ++} ++ ++static struct platform_driver latch_led_driver = { ++ .probe = latch_led_probe, ++ .remove = latch_led_remove, ++ .driver = { ++ .name = "leds-latch", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init latch_led_init(void) ++{ ++ return platform_driver_register(&latch_led_driver); ++} ++ ++static void __exit latch_led_exit(void) ++{ ++ platform_driver_unregister(&latch_led_driver); ++} ++ ++module_init(latch_led_init); ++module_exit(latch_led_exit); ++ ++MODULE_AUTHOR("Chris Lang "); ++MODULE_DESCRIPTION("Latch LED driver"); +--- a/include/linux/leds.h ++++ b/include/linux/leds.h +@@ -344,4 +344,18 @@ static inline void ledtrig_cpu(enum cpu_ + } + #endif + ++/* For the leds-latch driver */ ++struct latch_led { ++ const char *name; ++ char *default_trigger; ++ unsigned bit; ++}; ++ ++struct latch_led_platform_data { ++ int num_leds; ++ u32 mem; ++ struct latch_led *leds; ++ void (*set_led)(u8 bit, enum led_brightness value); ++}; ++ + #endif /* __LINUX_LEDS_H_INCLUDED */ diff --git a/target/linux/ixp4xx/patches-4.1/300-avila_support.patch b/target/linux/ixp4xx/patches-4.1/300-avila_support.patch new file mode 100644 index 0000000..d2dafaa --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/300-avila_support.patch @@ -0,0 +1,726 @@ +--- a/arch/arm/mach-ixp4xx/avila-pci.c ++++ b/arch/arm/mach-ixp4xx/avila-pci.c +@@ -27,8 +27,8 @@ + #include + #include + +-#define AVILA_MAX_DEV 4 +-#define LOFT_MAX_DEV 6 ++#define AVILA_MAX_DEV 6 ++ + #define IRQ_LINES 4 + + /* PCI controller GPIO to IRQ pin mappings */ +@@ -55,10 +55,8 @@ static int __init avila_map_irq(const st + IXP4XX_GPIO_IRQ(INTD) + }; + +- if (slot >= 1 && +- slot <= (machine_is_loft() ? LOFT_MAX_DEV : AVILA_MAX_DEV) && +- pin >= 1 && pin <= IRQ_LINES) +- return pci_irq_table[(slot + pin - 2) % 4]; ++ if (slot >= 1 && slot <= AVILA_MAX_DEV && pin >= 1 && pin <= IRQ_LINES) ++ return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; + + return -1; + } +--- a/arch/arm/mach-ixp4xx/avila-setup.c ++++ b/arch/arm/mach-ixp4xx/avila-setup.c +@@ -14,9 +14,16 @@ + #include + #include + #include ++#include ++#include ++#include + #include + #include + #include ++#include ++#include ++#include ++#include + #include + #include + #include +@@ -26,10 +33,25 @@ + #include + #include + #include ++#include + + #define AVILA_SDA_PIN 7 + #define AVILA_SCL_PIN 6 + ++/* User LEDs */ ++#define AVILA_GW23XX_LED_USER_GPIO 3 ++#define AVILA_GW23X7_LED_USER_GPIO 4 ++ ++/* gpio mask used by platform device */ ++#define AVILA_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) | (1 << 9) ++ ++struct avila_board_info { ++ unsigned char *model; ++ void (*setup)(void); ++}; ++ ++static struct avila_board_info *avila_info __initdata; ++ + static struct flash_platform_data avila_flash_data = { + .map_name = "cfi_probe", + .width = 2, +@@ -105,14 +127,69 @@ static struct platform_device avila_uart + .resource = avila_uart_resources + }; + +-static struct resource avila_pata_resources[] = { ++static struct resource avila_optional_uart_resources[] = { + { +- .flags = IORESOURCE_MEM +- }, ++ .start = 0x54000000, ++ .end = 0x54000fff, ++ .flags = IORESOURCE_MEM ++ },{ ++ .start = 0x55000000, ++ .end = 0x55000fff, ++ .flags = IORESOURCE_MEM ++ },{ ++ .start = 0x56000000, ++ .end = 0x56000fff, ++ .flags = IORESOURCE_MEM ++ },{ ++ .start = 0x57000000, ++ .end = 0x57000fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port avila_optional_uart_data[] = { + { +- .flags = IORESOURCE_MEM, ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ .rw_delay = 2, ++ },{ ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ .rw_delay = 2, ++ },{ ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ .rw_delay = 2, ++ },{ ++ .flags = UPF_BOOT_AUTOCONF, ++ .iotype = UPIO_MEM, ++ .regshift = 0, ++ .uartclk = 18432000, ++ .rw_delay = 2, + }, ++ { } ++}; ++ ++static struct platform_device avila_optional_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM1, ++ .dev.platform_data = avila_optional_uart_data, ++ .num_resources = 4, ++ .resource = avila_optional_uart_resources, ++}; ++ ++static struct resource avila_pata_resources[] = { + { ++ .flags = IORESOURCE_MEM ++ },{ ++ .flags = IORESOURCE_MEM, ++ },{ + .name = "intrq", + .start = IRQ_IXP4XX_GPIO12, + .end = IRQ_IXP4XX_GPIO12, +@@ -133,21 +210,237 @@ static struct platform_device avila_pata + .resource = avila_pata_resources, + }; + ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info avila_npeb_data = { ++ .phy = 0, ++ .rxq = 3, ++ .txreadyq = 20, ++}; ++ ++static struct eth_plat_info avila_npec_data = { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct platform_device avila_npeb_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = &avila_npeb_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct platform_device avila_npec_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = &avila_npec_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct gpio_led avila_gpio_leds[] = { ++ { ++ .name = "user", /* green led */ ++ .gpio = AVILA_GW23XX_LED_USER_GPIO, ++ .active_low = 1, ++ }, ++ { ++ .name = "radio1", /* green led */ ++ .gpio = 104, ++ .active_low = 1, ++ }, ++ { ++ .name = "radio2", /* green led */ ++ .gpio = 105, ++ .active_low = 1, ++ }, ++ { ++ .name = "radio3", /* green led */ ++ .gpio = 106, ++ .active_low = 1, ++ }, ++ { ++ .name = "radio4", /* green led */ ++ .gpio = 107, ++ .active_low = 1, ++ }, ++ ++}; ++ ++static struct gpio_led_platform_data avila_gpio_leds_data = { ++ .num_leds = 1, ++ .leds = avila_gpio_leds, ++}; ++ ++static struct platform_device avila_gpio_leds_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &avila_gpio_leds_data, ++}; ++ ++static struct latch_led avila_latch_leds[] = { ++ { ++ .name = "led0", /* green led */ ++ .bit = 0, ++ }, ++ { ++ .name = "led1", /* green led */ ++ .bit = 1, ++ }, ++ { ++ .name = "led2", /* green led */ ++ .bit = 2, ++ }, ++ { ++ .name = "led3", /* green led */ ++ .bit = 3, ++ }, ++ { ++ .name = "led4", /* green led */ ++ .bit = 4, ++ }, ++ { ++ .name = "led5", /* green led */ ++ .bit = 5, ++ }, ++ { ++ .name = "led6", /* green led */ ++ .bit = 6, ++ }, ++ { ++ .name = "led7", /* green led */ ++ .bit = 7, ++ } ++}; ++ ++static struct latch_led_platform_data avila_latch_leds_data = { ++ .num_leds = 8, ++ .leds = avila_latch_leds, ++ .mem = 0x51000000, ++}; ++ ++static struct platform_device avila_latch_leds_device = { ++ .name = "leds-latch", ++ .id = -1, ++ .dev.platform_data = &avila_latch_leds_data, ++}; ++ + static struct platform_device *avila_devices[] __initdata = { + &avila_i2c_gpio, +- &avila_flash, + &avila_uart + }; + +-static void __init avila_init(void) ++/* ++ * Audio Devices ++ */ ++ ++static struct platform_device avila_hss_device[] = { ++ { ++ .name = "gw_avila_hss", ++ .id = 0, ++ },{ ++ .name = "gw_avila_hss", ++ .id = 1, ++ },{ ++ .name = "gw_avila_hss", ++ .id = 2, ++ },{ ++ .name = "gw_avila_hss", ++ .id = 3, ++ }, ++}; ++ ++static struct platform_device avila_pcm_device[] = { ++ { ++ .name = "gw_avila-audio", ++ .id = 0, ++ },{ ++ .name = "gw_avila-audio", ++ .id = 1, ++ },{ ++ .name = "gw_avila-audio", ++ .id = 2, ++ },{ ++ .name = "gw_avila-audio", ++ .id = 3, ++ } ++}; ++ ++static void setup_audio_devices(void) { ++ platform_device_register(&avila_hss_device[0]); ++ platform_device_register(&avila_hss_device[1]); ++ platform_device_register(&avila_hss_device[2]); ++ platform_device_register(&avila_hss_device[3]); ++ ++ platform_device_register(&avila_pcm_device[0]); ++ platform_device_register(&avila_pcm_device[1]); ++ platform_device_register(&avila_pcm_device[2]); ++ platform_device_register(&avila_pcm_device[3]); ++} ++ ++static void __init avila_gw23xx_setup(void) + { +- ixp4xx_sys_init(); ++ platform_device_register(&avila_npeb_device); ++ platform_device_register(&avila_npec_device); + +- avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); +- avila_flash_resource.end = +- IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ platform_device_register(&avila_gpio_leds_device); ++} + +- platform_add_devices(avila_devices, ARRAY_SIZE(avila_devices)); ++static void __init avila_gw2342_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ platform_device_register(&avila_npec_device); ++ ++ platform_device_register(&avila_gpio_leds_device); ++ ++ avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); ++ avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); ++ ++ avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2); ++ avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(2); ++ ++ avila_pata_data.cs0_cfg = IXP4XX_EXP_CS1; ++ avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2; ++ ++ platform_device_register(&avila_pata); ++} ++ ++static void __init avila_gw2345_setup(void) ++{ ++ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */ ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 5; /* port 5 of the KS8995 switch */ ++ platform_device_register(&avila_npec_device); ++ ++ platform_device_register(&avila_gpio_leds_device); ++ ++ avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); ++ avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); ++ ++ avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2); ++ avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(2); ++ ++ avila_pata_data.cs0_cfg = IXP4XX_EXP_CS1; ++ avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2; ++ ++ platform_device_register(&avila_pata); ++} ++ ++static void __init avila_gw2347_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ ++ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO; ++ platform_device_register(&avila_gpio_leds_device); ++} ++ ++static void __init avila_gw2348_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ platform_device_register(&avila_npec_device); ++ ++ platform_device_register(&avila_gpio_leds_device); + + avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); + avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); +@@ -159,8 +452,335 @@ static void __init avila_init(void) + avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2; + + platform_device_register(&avila_pata); ++} ++ ++static void __init avila_gw2353_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ platform_device_register(&avila_gpio_leds_device); ++} ++ ++static void __init avila_gw2355_setup(void) ++{ ++ avila_npeb_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++ avila_npeb_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */ ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 16; ++ platform_device_register(&avila_npec_device); ++ ++ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO; ++ platform_device_register(&avila_gpio_leds_device); ++ ++ *IXP4XX_EXP_CS4 |= 0xbfff3c03; ++ avila_latch_leds[0].name = "RXD"; ++ avila_latch_leds[1].name = "TXD"; ++ avila_latch_leds[2].name = "POL"; ++ avila_latch_leds[3].name = "LNK"; ++ avila_latch_leds[4].name = "ERR"; ++ avila_latch_leds_data.num_leds = 5; ++ avila_latch_leds_data.mem = 0x54000000; ++ platform_device_register(&avila_latch_leds_device); ++ ++ avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(1); ++ avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(1); ++ ++ avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(2); ++ avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(2); ++ ++ avila_pata_data.cs0_cfg = IXP4XX_EXP_CS1; ++ avila_pata_data.cs1_cfg = IXP4XX_EXP_CS2; ++ ++ platform_device_register(&avila_pata); ++} ++ ++static void __init avila_gw2357_setup(void) ++{ ++ platform_device_register(&avila_npeb_device); ++ ++ avila_gpio_leds[0].gpio = AVILA_GW23X7_LED_USER_GPIO; ++ platform_device_register(&avila_gpio_leds_device); ++ ++ *IXP4XX_EXP_CS1 |= 0xbfff3c03; ++ platform_device_register(&avila_latch_leds_device); ++} ++ ++static void __init avila_gw2365_setup(void) ++{ ++ avila_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS4 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO0, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[0].mapbase = 0x54000000; ++ avila_optional_uart_data[0].membase = (void __iomem *)ioremap(0x54000000, 0x0fff); ++ avila_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO0; ++ ++ *IXP4XX_EXP_CS5 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO1, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[1].mapbase = 0x55000000; ++ avila_optional_uart_data[1].membase = (void __iomem *)ioremap(0x55000000, 0x0fff); ++ avila_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO1; ++ ++ *IXP4XX_EXP_CS6 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[2].mapbase = 0x56000000; ++ avila_optional_uart_data[2].membase = (void __iomem *)ioremap(0x56000000, 0x0fff); ++ avila_optional_uart_data[2].irq = IRQ_IXP4XX_GPIO2; ++ ++ *IXP4XX_EXP_CS7 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[3].mapbase = 0x57000000; ++ avila_optional_uart_data[3].membase = (void __iomem *)ioremap(0x57000000, 0x0fff); ++ avila_optional_uart_data[3].irq = IRQ_IXP4XX_GPIO3; ++ ++ platform_device_register(&avila_optional_uart); ++ ++ avila_npeb_data.phy = 1; ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 2; ++ platform_device_register(&avila_npec_device); ++ ++ avila_pata_resources[0].start = IXP4XX_EXP_BUS_BASE(2); ++ avila_pata_resources[0].end = IXP4XX_EXP_BUS_END(2); ++ ++ avila_pata_resources[1].start = IXP4XX_EXP_BUS_BASE(3); ++ avila_pata_resources[1].end = IXP4XX_EXP_BUS_END(3); ++ ++ avila_pata_data.cs0_cfg = IXP4XX_EXP_CS2; ++ avila_pata_data.cs1_cfg = IXP4XX_EXP_CS3; ++ ++ platform_device_register(&avila_pata); ++ ++ avila_gpio_leds[0].gpio = 109; ++ avila_gpio_leds_data.num_leds = 5; ++ platform_device_register(&avila_gpio_leds_device); ++ ++ setup_audio_devices(); ++} ++ ++static void __init avila_gw2369_setup(void) ++{ ++ avila_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ avila_npeb_data.phy = 1; ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 2; ++ platform_device_register(&avila_npec_device); ++ ++ setup_audio_devices(); ++} ++ ++static void __init avila_gw2370_setup(void) ++{ ++ avila_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ avila_npeb_data.phy = 5; ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; ++ avila_npec_data.phy_mask = 0x1e; /* ports 1-4 of the KS8995 switch */ ++ platform_device_register(&avila_npec_device); ++ ++ *IXP4XX_EXP_CS2 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[0].mapbase = 0x52000000; ++ avila_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff); ++ avila_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO2; ++ ++ *IXP4XX_EXP_CS3 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[1].mapbase = 0x53000000; ++ avila_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53000000, 0x0fff); ++ avila_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO3; ++ ++ avila_optional_uart.num_resources = 2; ++ ++ platform_device_register(&avila_optional_uart); ++ ++ avila_gpio_leds[0].gpio = 101; ++ platform_device_register(&avila_gpio_leds_device); ++ ++ setup_audio_devices(); ++} ++ ++static void __init avila_gw2375_setup(void) ++{ ++ avila_npeb_data.phy = 1; ++ platform_device_register(&avila_npeb_device); ++ ++ avila_npec_data.phy = 2; ++ platform_device_register(&avila_npec_device); ++ ++ *IXP4XX_EXP_CS2 = 0xBFFF3C43; ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING); ++ avila_optional_uart_data[0].mapbase = 0x52000000; ++ avila_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff); ++ avila_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO10; ++ ++ avila_optional_uart.num_resources = 1; ++ ++ platform_device_register(&avila_optional_uart); ++ ++ setup_audio_devices(); ++} ++ ++ ++static struct avila_board_info avila_boards[] __initdata = { ++ { ++ .model = "GW2342", ++ .setup = avila_gw2342_setup, ++ }, { ++ .model = "GW2345", ++ .setup = avila_gw2345_setup, ++ }, { ++ .model = "GW2347", ++ .setup = avila_gw2347_setup, ++ }, { ++ .model = "GW2348", ++ .setup = avila_gw2348_setup, ++ }, { ++ .model = "GW2353", ++ .setup = avila_gw2353_setup, ++ }, { ++ .model = "GW2355", ++ .setup = avila_gw2355_setup, ++ }, { ++ .model = "GW2357", ++ .setup = avila_gw2357_setup, ++ }, { ++ .model = "GW2365", ++ .setup = avila_gw2365_setup, ++ }, { ++ .model = "GW2369", ++ .setup = avila_gw2369_setup, ++ }, { ++ .model = "GW2370", ++ .setup = avila_gw2370_setup, ++ }, { ++ .model = "GW2373", ++ .setup = avila_gw2369_setup, ++ }, { ++ .model = "GW2375", ++ .setup = avila_gw2375_setup, ++ } ++}; ++ ++static struct avila_board_info * __init avila_find_board_info(char *model) ++{ ++ int i; ++ model[6] = '\0'; ++ ++ for (i = 0; i < ARRAY_SIZE(avila_boards); i++) { ++ struct avila_board_info *info = &avila_boards[i]; ++ if (strcmp(info->model, model) == 0) ++ return info; ++ } ++ ++ return NULL; ++} ++ ++static struct memory_accessor *at24_mem_acc; ++ ++static void at24_setup(struct memory_accessor *mem_acc, void *context) ++{ ++ char mac_addr[ETH_ALEN]; ++ char model[7]; ++ ++ at24_mem_acc = mem_acc; ++ ++ /* Read MAC addresses */ ++ if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x0, 6) == 6) { ++ memcpy(&avila_npeb_data.hwaddr, mac_addr, ETH_ALEN); ++ } ++ if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x6, 6) == 6) { ++ memcpy(&avila_npec_data.hwaddr, mac_addr, ETH_ALEN); ++ } ++ ++ /* Read the first 6 bytes of the model number */ ++ if (at24_mem_acc->read(at24_mem_acc, model, 0x20, 6) == 6) { ++ avila_info = avila_find_board_info(model); ++ } ++ ++} ++ ++static struct at24_platform_data avila_eeprom_info = { ++ .byte_len = 1024, ++ .page_size = 16, ++// .flags = AT24_FLAG_READONLY, ++ .setup = at24_setup, ++}; ++ ++static struct pca953x_platform_data avila_pca_data = { ++ .gpio_base = 100, ++}; ++ ++static struct i2c_board_info __initdata avila_i2c_board_info[] = { ++ { ++ I2C_BOARD_INFO("ds1672", 0x68), ++ }, ++ { ++ I2C_BOARD_INFO("gsp", 0x29), ++ }, ++ { ++ I2C_BOARD_INFO("pca9555", 0x23), ++ .platform_data = &avila_pca_data, ++ }, ++ { ++ I2C_BOARD_INFO("ad7418", 0x28), ++ }, ++ { ++ I2C_BOARD_INFO("24c08", 0x51), ++ .platform_data = &avila_eeprom_info ++ }, ++ { ++ I2C_BOARD_INFO("tlv320aic33", 0x1b), ++ }, ++ { ++ I2C_BOARD_INFO("tlv320aic33", 0x1a), ++ }, ++ { ++ I2C_BOARD_INFO("tlv320aic33", 0x19), ++ }, ++ { ++ I2C_BOARD_INFO("tlv320aic33", 0x18), ++ }, ++}; ++ ++static void __init avila_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ platform_add_devices(avila_devices, ARRAY_SIZE(avila_devices)); ++ ++ i2c_register_board_info(0, avila_i2c_board_info, ++ ARRAY_SIZE(avila_i2c_board_info)); ++} ++ ++static int __init avila_model_setup(void) ++{ ++ if (!machine_is_avila()) ++ return 0; ++ ++ /* default 16MB flash */ ++ avila_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ avila_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_16M - 1; ++ ++ if (avila_info) { ++ printk(KERN_DEBUG "Running on Gateworks Avila %s\n", ++ avila_info->model); ++ avila_info->setup(); ++ } else { ++ printk(KERN_INFO "Unknown/missing Avila model number" ++ " -- defaults will be used\n"); ++ avila_gw23xx_setup(); ++ } ++ platform_device_register(&avila_flash); + ++ return 0; + } ++late_initcall(avila_model_setup); + + MACHINE_START(AVILA, "Gateworks Avila Network Platform") + /* Maintainer: Deepak Saxena */ diff --git a/target/linux/ixp4xx/patches-4.1/304-ixp4xx_eth_jumboframe.patch b/target/linux/ixp4xx/patches-4.1/304-ixp4xx_eth_jumboframe.patch new file mode 100644 index 0000000..b16086b --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/304-ixp4xx_eth_jumboframe.patch @@ -0,0 +1,80 @@ +--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c ++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c +@@ -57,7 +57,7 @@ + + #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) + #define REGS_SIZE 0x1000 +-#define MAX_MRU 1536 /* 0x600 */ ++#define MAX_MRU (14320 - ETH_HLEN - ETH_FCS_LEN) + #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) + + #define NAPI_WEIGHT 16 +@@ -1315,6 +1315,32 @@ static void destroy_queues(struct port * + } + } + ++static int eth_do_change_mtu(struct net_device *dev, int mtu) ++{ ++ struct port *port; ++ struct msg msg; ++ /* adjust for ethernet headers */ ++ int framesize = mtu + ETH_HLEN + ETH_FCS_LEN; ++ ++ port = netdev_priv(dev); ++ ++ memset(&msg, 0, sizeof(msg)); ++ msg.cmd = NPE_SETMAXFRAMELENGTHS; ++ msg.eth_id = port->id; ++ ++ /* max rx/tx 64 byte blocks */ ++ msg.byte2 = ((framesize + 63) / 64) << 8; ++ msg.byte3 = ((framesize + 63) / 64) << 8; ++ ++ msg.byte4 = msg.byte6 = framesize >> 8; ++ msg.byte5 = msg.byte7 = framesize & 0xff; ++ ++ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAX_FRAME_LENGTH")) ++ return -EIO; ++ ++ return 0; ++} ++ + static int eth_open(struct net_device *dev) + { + struct port *port = netdev_priv(dev); +@@ -1366,6 +1392,8 @@ static int eth_open(struct net_device *d + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) + return -EIO; + ++ eth_do_change_mtu(dev, dev->mtu); ++ + if ((err = request_queues(port)) != 0) + return err; + +@@ -1505,7 +1533,26 @@ static int eth_close(struct net_device * + return 0; + } + ++static int ixp_eth_change_mtu(struct net_device *dev, int mtu) ++{ ++ int ret; ++ ++ if (mtu > MAX_MRU) ++ return -EINVAL; ++ ++ if (dev->flags & IFF_UP) { ++ ret = eth_do_change_mtu(dev, mtu); ++ if (ret < 0) ++ return ret; ++ } ++ ++ dev->mtu = mtu; ++ ++ return 0; ++} ++ + static const struct net_device_ops ixp4xx_netdev_ops = { ++ .ndo_change_mtu = ixp_eth_change_mtu, + .ndo_open = eth_open, + .ndo_stop = eth_close, + .ndo_start_xmit = eth_xmit, diff --git a/target/linux/ixp4xx/patches-4.1/310-gtwx5717_spi_bus.patch b/target/linux/ixp4xx/patches-4.1/310-gtwx5717_spi_bus.patch new file mode 100644 index 0000000..080b96a --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/310-gtwx5717_spi_bus.patch @@ -0,0 +1,52 @@ +--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c ++++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -146,9 +147,41 @@ static struct platform_device gtwx5715_f + .resource = >wx5715_flash_resource, + }; + ++static int gtwx5715_spi_boardinfo_setup(struct spi_board_info *bi, ++ struct spi_master *master, void *data) ++{ ++ ++ strlcpy(bi->modalias, "spi-ks8995", sizeof(bi->modalias)); ++ ++ bi->max_speed_hz = 5000000 /* Hz */; ++ bi->bus_num = master->bus_num; ++ bi->mode = SPI_MODE_0; ++ ++ return 0; ++} ++ ++static struct spi_gpio_platform_data gtwx5715_spi_bus_data = { ++ .pin_cs = GTWX5715_KSSPI_SELECT, ++ .pin_clk = GTWX5715_KSSPI_CLOCK, ++ .pin_miso = GTWX5715_KSSPI_RXD, ++ .pin_mosi = GTWX5715_KSSPI_TXD, ++ .cs_activelow = 1, ++ .no_spi_delay = 1, ++ .boardinfo_setup = gtwx5715_spi_boardinfo_setup, ++}; ++ ++static struct platform_device gtwx5715_spi_bus = { ++ .name = "spi-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = >wx5715_spi_bus_data, ++ }, ++}; ++ + static struct platform_device *gtwx5715_devices[] __initdata = { + >wx5715_uart_device, + >wx5715_flash, ++ >wx5715_spi_bus, + }; + + static void __init gtwx5715_init(void) diff --git a/target/linux/ixp4xx/patches-4.1/311-gtwx5717_mac_plat_info.patch b/target/linux/ixp4xx/patches-4.1/311-gtwx5717_mac_plat_info.patch new file mode 100644 index 0000000..aa7a9e0 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/311-gtwx5717_mac_plat_info.patch @@ -0,0 +1,50 @@ +--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c ++++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c +@@ -28,6 +28,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -178,10 +179,39 @@ static struct platform_device gtwx5715_s + }, + }; + ++static struct eth_plat_info gtwx5715_npeb_data = { ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x1e, /* ports 1-4 of the KS8995 switch */ ++ .rxq = 3, ++ .txreadyq = 20, ++}; ++ ++static struct eth_plat_info gtwx5715_npec_data = { ++ .phy = 5, /* port 5 of the KS8995 switch */ ++ .rxq = 4, ++ .txreadyq = 21, ++}; ++ ++static struct platform_device gtwx5715_npeb_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = >wx5715_npeb_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ ++static struct platform_device gtwx5715_npec_device = { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = >wx5715_npec_data, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++}; ++ + static struct platform_device *gtwx5715_devices[] __initdata = { + >wx5715_uart_device, + >wx5715_flash, + >wx5715_spi_bus, ++ >wx5715_npeb_device, ++ >wx5715_npec_device, + }; + + static void __init gtwx5715_init(void) diff --git a/target/linux/ixp4xx/patches-4.1/312-ixp4xx_pata_optimization.patch b/target/linux/ixp4xx/patches-4.1/312-ixp4xx_pata_optimization.patch new file mode 100644 index 0000000..59c2837 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/312-ixp4xx_pata_optimization.patch @@ -0,0 +1,137 @@ +--- a/drivers/ata/pata_ixp4xx_cf.c ++++ b/drivers/ata/pata_ixp4xx_cf.c +@@ -24,16 +24,58 @@ + #include + + #define DRV_NAME "pata_ixp4xx_cf" +-#define DRV_VERSION "0.2" ++#define DRV_VERSION "0.3" + + static int ixp4xx_set_mode(struct ata_link *link, struct ata_device **error) + { ++ struct ixp4xx_pata_data *data = link->ap->host->dev->platform_data; ++ unsigned int pio_mask; + struct ata_device *dev; + + ata_for_each_dev(dev, link, ENABLED) { +- ata_dev_info(dev, "configured for PIO0\n"); +- dev->pio_mode = XFER_PIO_0; +- dev->xfer_mode = XFER_PIO_0; ++ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)) { ++ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03; ++ if (pio_mask & (1 << 1)) { ++ pio_mask = 4; ++ } else { ++ pio_mask = 3; ++ } ++ } else { ++ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8); ++ } ++ ++ switch (pio_mask){ ++ case 0: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO0\n"); ++ dev->pio_mode = XFER_PIO_0; ++ dev->xfer_mode = XFER_PIO_0; ++ *data->cs0_cfg = 0x8a473c03; ++ break; ++ case 1: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO1\n"); ++ dev->pio_mode = XFER_PIO_1; ++ dev->xfer_mode = XFER_PIO_1; ++ *data->cs0_cfg = 0x86433c03; ++ break; ++ case 2: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO2\n"); ++ dev->pio_mode = XFER_PIO_2; ++ dev->xfer_mode = XFER_PIO_2; ++ *data->cs0_cfg = 0x82413c03; ++ break; ++ case 3: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO3\n"); ++ dev->pio_mode = XFER_PIO_3; ++ dev->xfer_mode = XFER_PIO_3; ++ *data->cs0_cfg = 0x80823c03; ++ break; ++ case 4: ++ ata_dev_printk(dev, KERN_INFO, "configured for PIO4\n"); ++ dev->pio_mode = XFER_PIO_4; ++ dev->xfer_mode = XFER_PIO_4; ++ *data->cs0_cfg = 0x80403c03; ++ break; ++ } + dev->xfer_shift = ATA_SHIFT_PIO; + dev->flags |= ATA_DFLAG_PIO; + } +@@ -46,6 +88,7 @@ static unsigned int ixp4xx_mmio_data_xfe + unsigned int i; + unsigned int words = buflen >> 1; + u16 *buf16 = (u16 *) buf; ++ unsigned int pio_mask; + struct ata_port *ap = dev->link->ap; + void __iomem *mmio = ap->ioaddr.data_addr; + struct ixp4xx_pata_data *data = dev_get_platdata(ap->host->dev); +@@ -53,8 +96,34 @@ static unsigned int ixp4xx_mmio_data_xfe + /* set the expansion bus in 16bit mode and restore + * 8 bit mode after the transaction. + */ +- *data->cs0_cfg &= ~(0x01); +- udelay(100); ++ if (dev->id[ATA_ID_FIELD_VALID] & (1 << 1)){ ++ pio_mask = dev->id[ATA_ID_PIO_MODES] & 0x03; ++ if (pio_mask & (1 << 1)){ ++ pio_mask = 4; ++ }else{ ++ pio_mask = 3; ++ } ++ }else{ ++ pio_mask = (dev->id[ATA_ID_OLD_PIO_MODES] >> 8); ++ } ++ switch (pio_mask){ ++ case 0: ++ *data->cs0_cfg = 0xa9643c42; ++ break; ++ case 1: ++ *data->cs0_cfg = 0x85033c42; ++ break; ++ case 2: ++ *data->cs0_cfg = 0x80b23c42; ++ break; ++ case 3: ++ *data->cs0_cfg = 0x80823c42; ++ break; ++ case 4: ++ *data->cs0_cfg = 0x80403c42; ++ break; ++ } ++ udelay(5); + + /* Transfer multiple of 2 bytes */ + if (rw == READ) +@@ -79,8 +148,24 @@ static unsigned int ixp4xx_mmio_data_xfe + words++; + } + +- udelay(100); +- *data->cs0_cfg |= 0x01; ++ udelay(5); ++ switch (pio_mask){ ++ case 0: ++ *data->cs0_cfg = 0x8a473c03; ++ break; ++ case 1: ++ *data->cs0_cfg = 0x86433c03; ++ break; ++ case 2: ++ *data->cs0_cfg = 0x82413c03; ++ break; ++ case 3: ++ *data->cs0_cfg = 0x80823c03; ++ break; ++ case 4: ++ *data->cs0_cfg = 0x80403c03; ++ break; ++ } + + return words << 1; + } diff --git a/target/linux/ixp4xx/patches-4.1/500-usr8200_support.patch b/target/linux/ixp4xx/patches-4.1/500-usr8200_support.patch new file mode 100644 index 0000000..fb7f03e --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/500-usr8200_support.patch @@ -0,0 +1,347 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -93,6 +93,14 @@ config MACH_SIDEWINDER + Engineering Sidewinder board. For more information on this + platform, see http://www.adiengineering.com + ++config MACH_USR8200 ++ bool "USRobotics USR8200" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the USRobotics ++ USR8200 router board. For more information on this platform, see ++ http://openwrt.org ++ + config MACH_COMPEXWP18 + bool "Compex WP18 / NP18A" + select PCI +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -27,6 +27,7 @@ obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt + obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o + obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o ++obj-pci-$(CONFIG_MACH_USR8200) += usr8200-pci.o + + obj-y += common.o + +@@ -55,6 +56,7 @@ obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv + obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o + obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o + obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o ++obj-$(CONFIG_MACH_USR8200) += usr8200-setup.o + + obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o + obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -44,7 +44,8 @@ static __inline__ void __arch_decomp_set + machine_is_gateway7001() || machine_is_wg302v2() || + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro() || +- machine_is_wrt300nv2() || machine_is_tw5334()) ++ machine_is_wrt300nv2() || machine_is_tw5334() || ++ machine_is_usr8200()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/usr8200-pci.c +@@ -0,0 +1,77 @@ ++/* ++ * arch/arch/mach-ixp4xx/usr8200-pci.c ++ * ++ * PCI setup routines for USRobotics USR8200 ++ * ++ * Copyright (C) 2008 Peter Denison ++ * ++ * based on pronghorn-pci.c ++ * Copyright (C) 2008 Imre Kaloz ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Peter Denison ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init usr8200_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init usr8200_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == 14) ++ return IRQ_IXP4XX_GPIO7; ++ else if (slot == 15) ++ return IRQ_IXP4XX_GPIO8; ++ else if (slot == 16) { ++ if (pin == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (pin == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else if (pin == 3) ++ return IRQ_IXP4XX_GPIO9; ++ else ++ return -1; ++ } else ++ return -1; ++} ++ ++struct hw_pci usr8200_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = usr8200_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = usr8200_map_irq, ++}; ++ ++int __init usr8200_pci_init(void) ++{ ++ if (machine_is_usr8200()) ++ pci_common_init(&usr8200_pci); ++ return 0; ++} ++ ++subsys_initcall(usr8200_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/usr8200-setup.c +@@ -0,0 +1,217 @@ ++/* ++ * arch/arm/mach-ixp4xx/usr8200-setup.c ++ * ++ * Board setup for the USRobotics USR8200 ++ * ++ * Copyright (C) 2008 Peter Denison ++ * ++ * based on pronghorn-setup.c: ++ * Copyright (C) 2008 Imre Kaloz ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Peter Denison ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct flash_platform_data usr8200_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource usr8200_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device usr8200_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &usr8200_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &usr8200_flash_resource, ++}; ++ ++static struct resource usr8200_uart_resources [] = { ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port usr8200_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device usr8200_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = usr8200_uart_data, ++ }, ++ .num_resources = 2, ++ .resource = usr8200_uart_resources, ++}; ++ ++static struct gpio_led usr8200_led_pin[] = { ++ { ++ .name = "usr8200:usb1", ++ .gpio = 0, ++ .active_low = 1, ++ }, ++ { ++ .name = "usr8200:usb2", ++ .gpio = 1, ++ .active_low = 1, ++ }, ++ { ++ .name = "usr8200:ieee1394", ++ .gpio = 2, ++ .active_low = 1, ++ }, ++ { ++ .name = "usr8200:internal", ++ .gpio = 3, ++ .active_low = 1, ++ }, ++ { ++ .name = "usr8200:power", ++ .gpio = 14, ++ } ++}; ++ ++static struct gpio_led_platform_data usr8200_led_data = { ++ .num_leds = ARRAY_SIZE(usr8200_led_pin), ++ .leds = usr8200_led_pin, ++}; ++ ++static struct platform_device usr8200_led = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = &usr8200_led_data, ++}; ++ ++static struct eth_plat_info usr8200_plat_eth[] = { ++ { /* NPEC - LAN with Marvell 88E6060 switch */ ++ .phy = IXP4XX_ETH_PHY_MAX_ADDR, ++ .phy_mask = 0x0F0000, ++ .rxq = 4, ++ .txreadyq = 21, ++ }, { /* NPEB - WAN */ ++ .phy = 9, ++ .rxq = 3, ++ .txreadyq = 20, ++ } ++}; ++ ++static struct platform_device usr8200_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = usr8200_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = usr8200_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct resource usr8200_rtc_resources = { ++ .flags = IORESOURCE_MEM ++}; ++ ++static struct platform_device usr8200_rtc = { ++ .name = "rtc7301", ++ .id = 0, ++ .num_resources = 1, ++ .resource = &usr8200_rtc_resources, ++}; ++ ++static struct platform_device *usr8200_devices[] __initdata = { ++ &usr8200_flash, ++ &usr8200_uart, ++ &usr8200_led, ++ &usr8200_eth[0], ++ &usr8200_eth[1], ++ &usr8200_rtc, ++}; ++ ++static void __init usr8200_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ usr8200_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ usr8200_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_16M - 1; ++ ++ usr8200_rtc_resources.start = IXP4XX_EXP_BUS_BASE(2); ++ usr8200_rtc_resources.end = IXP4XX_EXP_BUS_BASE(2) + 0x01ff; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN | ++ IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN; ++ *IXP4XX_GPIO_GPCLKR = 0x01100000; ++ ++ /* configure button as input */ ++ gpio_line_config(12, IXP4XX_GPIO_IN); ++ ++ platform_add_devices(usr8200_devices, ARRAY_SIZE(usr8200_devices)); ++} ++ ++MACHINE_START(USR8200, "USRobotics USR8200") ++ /* Maintainer: Peter Denison */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = usr8200_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END diff --git a/target/linux/ixp4xx/patches-4.1/520-tw2662_support.patch b/target/linux/ixp4xx/patches-4.1/520-tw2662_support.patch new file mode 100644 index 0000000..7cea61f --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/520-tw2662_support.patch @@ -0,0 +1,317 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -176,6 +176,15 @@ config ARCH_PRPMC1100 + PrPCM1100 Processor Mezanine Module. For more information on + this platform, see . + ++config MACH_TW2662 ++ bool "Titan Wireless TW-266-2" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support the Titan ++ Wireless TW266-2. For more information on this platform, ++ see http://openwrt.org ++ ++ + config MACH_TW5334 + bool "Titan Wireless TW-533-4" + select PCI +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -25,6 +25,7 @@ obj-pci-$(CONFIG_MACH_SIDEWINDER) += sid + obj-pci-$(CONFIG_MACH_COMPEXWP18) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-pci.o + obj-pci-$(CONFIG_MACH_AP1000) += ixdp425-pci.o ++obj-pci-$(CONFIG_MACH_TW2662) += tw2662-pci.o + obj-pci-$(CONFIG_MACH_TW5334) += tw5334-pci.o + obj-pci-$(CONFIG_MACH_MI424WR) += mi424wr-pci.o + obj-pci-$(CONFIG_MACH_USR8200) += usr8200-pci.o +@@ -54,6 +55,7 @@ obj-$(CONFIG_MACH_SIDEWINDER) += sidewin + obj-$(CONFIG_MACH_COMPEXWP18) += compex42x-setup.o + obj-$(CONFIG_MACH_WRT300NV2) += wrt300nv2-setup.o + obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o ++obj-$(CONFIG_MACH_TW2662) += tw2662-setup.o + obj-$(CONFIG_MACH_TW5334) += tw5334-setup.o + obj-$(CONFIG_MACH_MI424WR) += mi424wr-setup.o + obj-$(CONFIG_MACH_USR8200) += usr8200-setup.o +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -45,7 +45,7 @@ static __inline__ void __arch_decomp_set + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro() || + machine_is_wrt300nv2() || machine_is_tw5334() || +- machine_is_usr8200()) ++ machine_is_usr8200() || machine_is_tw2662()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/tw2662-pci.c +@@ -0,0 +1,67 @@ ++/* ++ * arch/arm/mach-ixp4xx/tw2662-pci.c ++ * ++ * PCI setup routines for Tiran Wireless TW-266-2 platform ++ * ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * Copyright (C) 2010 Alexandros C. Couloumbis ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * Maintainer: Deepak Saxena ++ * Maintainer: Alexandros C. Couloumbis ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SLOT0_DEVID 1 ++#define SLOT1_DEVID 3 ++ ++/* PCI controller GPIO to IRQ pin mappings */ ++#define SLOT0_INTA 11 ++#define SLOT1_INTA 9 ++ ++void __init tw2662_pci_preinit(void) ++{ ++ irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init tw2662_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ if (slot == SLOT0_DEVID) ++ return IXP4XX_GPIO_IRQ(SLOT0_INTA); ++ else if (slot == SLOT1_DEVID) ++ return IXP4XX_GPIO_IRQ(SLOT1_INTA); ++ else return -1; ++} ++ ++struct hw_pci tw2662_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = tw2662_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = tw2662_map_irq, ++}; ++ ++int __init tw2662_pci_init(void) ++{ ++ if (machine_is_tw2662()) ++ pci_common_init(&tw2662_pci); ++ return 0; ++} ++ ++subsys_initcall(tw2662_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/tw2662-setup.c +@@ -0,0 +1,197 @@ ++/* ++ * arch/arm/mach-ixp4xx/tw2662-setup.c ++ * ++ * Titan Wireless TW-266-2 ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * Copyright (C) 2010 Alexandros C. Couloumbis ++ * ++ * based on ap1000-setup.c: ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* gpio mask used by platform device */ ++#define TW2662_GPIO_MASK (1 << 1) | (1 << 3) | (1 << 5) | (1 << 7) ++ ++static struct flash_platform_data tw2662_flash_data = { ++ .map_name = "cfi_probe", ++ .width = 2, ++}; ++ ++static struct resource tw2662_flash_resource = { ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device tw2662_flash = { ++ .name = "IXP4XX-Flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &tw2662_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &tw2662_flash_resource, ++}; ++ ++static struct resource tw2662_uart_resources[] = { ++ { ++ .start = IXP4XX_UART1_BASE_PHYS, ++ .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM ++ } ++}; ++ ++static struct plat_serial8250_port tw2662_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART1_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART1, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device tw2662_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev.platform_data = tw2662_uart_data, ++ .num_resources = 2, ++ .resource = tw2662_uart_resources ++}; ++ ++/* Built-in 10/100 Ethernet MAC interfaces */ ++static struct eth_plat_info tw2662_plat_eth[] = { ++ { ++ .phy = 3, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device tw2662_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = tw2662_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = tw2662_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++ ++static struct platform_device *tw2662_devices[] __initdata = { ++ &tw2662_flash, ++ &tw2662_uart, ++ &tw2662_eth[0], ++ &tw2662_eth[1], ++}; ++ ++static char tw2662_mem_fixup[] __initdata = "mem=64M "; ++ ++static void __init tw2662_fixup(struct tag *tags, char **cmdline, ++ struct meminfo *mi) ++{ ++ struct tag *t = tags; ++ char *p = *cmdline; ++ ++ /* Find the end of the tags table, taking note of any cmdline tag. */ ++ for (; t->hdr.size; t = tag_next(t)) { ++ if (t->hdr.tag == ATAG_CMDLINE) { ++ p = t->u.cmdline.cmdline; ++ } ++ } ++ ++ /* Overwrite the end of the table with a new cmdline tag. */ ++ t->hdr.tag = ATAG_CMDLINE; ++ t->hdr.size = (sizeof (struct tag_header) + ++ strlen(tw2662_mem_fixup) + strlen(p) + 1 + 4) >> 2; ++ strlcpy(t->u.cmdline.cmdline, tw2662_mem_fixup, COMMAND_LINE_SIZE); ++ strlcpy(t->u.cmdline.cmdline + strlen(tw2662_mem_fixup), p, ++ COMMAND_LINE_SIZE - strlen(tw2662_mem_fixup)); ++ ++ /* Terminate the table. */ ++ t = tag_next(t); ++ t->hdr.tag = ATAG_NONE; ++ t->hdr.size = 0; ++} ++ ++static void __init tw2662_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ tw2662_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ tw2662_flash_resource.end = ++ IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; ++ ++ platform_add_devices(tw2662_devices, ARRAY_SIZE(tw2662_devices)); ++ ++ if (!(is_valid_ether_addr(tw2662_plat_eth[0].hwaddr))) ++ random_ether_addr(tw2662_plat_eth[0].hwaddr); ++ if (!(is_valid_ether_addr(tw2662_plat_eth[1].hwaddr))) { ++ memcpy(tw2662_plat_eth[1].hwaddr, tw2662_plat_eth[0].hwaddr, ETH_ALEN); ++ tw2662_plat_eth[1].hwaddr[5] = (tw2662_plat_eth[0].hwaddr[5] + 1); ++ } ++ ++} ++ ++#ifdef CONFIG_MACH_TW2662 ++MACHINE_START(TW2662, "Titan Wireless TW-266-2") ++ /* Maintainer: Alexandros C. Couloumbis */ ++ .fixup = tw2662_fixup, ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x0100, ++ .init_machine = tw2662_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif diff --git a/target/linux/ixp4xx/patches-4.1/530-ap42x_support.patch b/target/linux/ixp4xx/patches-4.1/530-ap42x_support.patch new file mode 100644 index 0000000..1afbe3d --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/530-ap42x_support.patch @@ -0,0 +1,282 @@ +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -4,6 +4,14 @@ menu "Intel IXP4xx Implementation Option + + comment "IXP4xx Platforms" + ++config MACH_AP42X ++ bool "Tonze AP-422/425" ++ select PCI ++ help ++ Say 'Y' here if you want your kernel to support Tonze's ++ AP-422/425 boards. For more information on this platform, ++ see http://tonze.com.tw ++ + config MACH_NSLU2 + bool + prompt "Linksys NSLU2" +--- a/arch/arm/mach-ixp4xx/Makefile ++++ b/arch/arm/mach-ixp4xx/Makefile +@@ -5,6 +5,7 @@ + obj-pci-y := + obj-pci-n := + ++obj-pci-$(CONFIG_MACH_AP42X) += ap42x-pci.o + obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o + obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o + obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o +@@ -32,6 +33,7 @@ obj-pci-$(CONFIG_MACH_USR8200) += usr82 + + obj-y += common.o + ++obj-$(CONFIG_MACH_AP42X) += ap42x-setup.o + obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o + obj-$(CONFIG_MACH_AVILA) += avila-setup.o + obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/ap42x-pci.c +@@ -0,0 +1,63 @@ ++/* ++ * arch/arch/mach-ixp4xx/ap42x-pci.c ++ * ++ * PCI setup routines for Tonze AP-422/425 ++ * ++ * Copyright (C) 2012 Imre Kaloz ++ * ++ * based on coyote-pci.c: ++ * Copyright (C) 2002 Jungo Software Technologies. ++ * Copyright (C) 2003 MontaVista Softwrae, Inc. ++ * ++ * Maintainer: Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++void __init ap42x_pci_preinit(void) ++{ ++ irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); ++ irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); ++ ++ ixp4xx_pci_preinit(); ++} ++ ++static int __init ap42x_map_irq(const struct pci_dev *dev, u8 slot, ++ u8 pin) ++{ ++ if (slot == 1) ++ return IRQ_IXP4XX_GPIO11; ++ else if (slot == 2) ++ return IRQ_IXP4XX_GPIO10; ++ else return -1; ++} ++ ++struct hw_pci ap42x_pci __initdata = { ++ .nr_controllers = 1, ++ .preinit = ap42x_pci_preinit, ++ .ops = &ixp4xx_ops, ++ .setup = ixp4xx_setup, ++ .map_irq = ap42x_map_irq, ++}; ++ ++int __init ap42x_pci_init(void) ++{ ++ if (machine_is_ap42x()) ++ pci_common_init(&ap42x_pci); ++ return 0; ++} ++ ++subsys_initcall(ap42x_pci_init); +--- /dev/null ++++ b/arch/arm/mach-ixp4xx/ap42x-setup.c +@@ -0,0 +1,166 @@ ++/* ++ * arch/arm/mach-ixp4xx/ap42x-setup.c ++ * ++ * Board setup for the Tonze AP-42x boards ++ * ++ * Copyright (C) 2012 Imre Kaloz ++ * ++ * based on coyote-setup.c: ++ * Copyright (C) 2003-2005 MontaVista Software, Inc. ++ * ++ * Author: Imre Kaloz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct mtd_partition ap42x_flash_partitions[] = { ++ { ++ .name = "RedBoot", ++ .offset = 0x00000000, ++ .size = 0x00080000, ++ }, { ++ .name = "linux", ++ .offset = 0x00080000, ++ .size = 0x00100000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x00180000, ++ .size = 0x00660000, ++ }, { ++ .name = "FIS directory", ++ .offset = 0x007f8000, ++ .size = 0x00007000, ++ }, { ++ .name = "RedBoot config", ++ .offset = 0x007ff000, ++ .size = 0x00001000, ++ }, ++}; ++ ++static struct physmap_flash_data ap42x_flash_data = { ++ .width = 2, ++ .parts = ap42x_flash_partitions, ++ .nr_parts = ARRAY_SIZE(ap42x_flash_partitions), ++}; ++ ++static struct resource ap42x_flash_resource = { ++ .flags = IORESOURCE_MEM, ++ .start = IXP4XX_EXP_BUS_BASE_PHYS, ++ .end = IXP4XX_EXP_BUS_BASE_PHYS + SZ_8M - 1, ++}; ++ ++static struct platform_device ap42x_flash = { ++ .name = "physmap-flash", ++ .id = 0, ++ .dev = { ++ .platform_data = &ap42x_flash_data, ++ }, ++ .num_resources = 1, ++ .resource = &ap42x_flash_resource, ++}; ++ ++static struct resource ap42x_uart_resource = { ++ .start = IXP4XX_UART2_BASE_PHYS, ++ .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct plat_serial8250_port ap42x_uart_data[] = { ++ { ++ .mapbase = IXP4XX_UART2_BASE_PHYS, ++ .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, ++ .irq = IRQ_IXP4XX_UART2, ++ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, ++ .iotype = UPIO_MEM, ++ .regshift = 2, ++ .uartclk = IXP4XX_UART_XTAL, ++ }, ++ { }, ++}; ++ ++static struct platform_device ap42x_uart = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = ap42x_uart_data, ++ }, ++ .num_resources = 1, ++ .resource = &ap42x_uart_resource, ++}; ++ ++static struct eth_plat_info ap42x_plat_eth[] = { ++ { ++ .phy = 2, ++ .rxq = 3, ++ .txreadyq = 20, ++ }, { ++ .phy = 1, ++ .rxq = 4, ++ .txreadyq = 21, ++ } ++}; ++ ++static struct platform_device ap42x_eth[] = { ++ { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEB, ++ .dev.platform_data = ap42x_plat_eth, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ }, { ++ .name = "ixp4xx_eth", ++ .id = IXP4XX_ETH_NPEC, ++ .dev.platform_data = ap42x_plat_eth + 1, ++ .dev.coherent_dma_mask = DMA_BIT_MASK(32), ++ } ++}; ++ ++static struct platform_device *ap42x_devices[] __initdata = { ++ &ap42x_flash, ++ &ap42x_uart, ++ &ap42x_eth[0], ++ &ap42x_eth[1], ++}; ++ ++static void __init ap42x_init(void) ++{ ++ ixp4xx_sys_init(); ++ ++ ap42x_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); ++ ap42x_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; ++ ++ *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; ++ *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; ++ ++ platform_add_devices(ap42x_devices, ARRAY_SIZE(ap42x_devices)); ++} ++ ++#ifdef CONFIG_MACH_AP42X ++MACHINE_START(AP42X, "Tonze AP-422/425") ++ /* Maintainer: Imre Kaloz */ ++ .map_io = ixp4xx_map_io, ++ .init_irq = ixp4xx_init_irq, ++ .init_time = ixp4xx_timer_init, ++ .atag_offset = 0x100, ++ .init_machine = ap42x_init, ++#if defined(CONFIG_PCI) ++ .dma_zone_size = SZ_64M, ++#endif ++ .restart = ixp4xx_restart, ++MACHINE_END ++#endif +--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h ++++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h +@@ -45,7 +45,8 @@ static __inline__ void __arch_decomp_set + machine_is_devixp() || machine_is_miccpt() || machine_is_mic256() || + machine_is_pronghorn() || machine_is_pronghorn_metro() || + machine_is_wrt300nv2() || machine_is_tw5334() || +- machine_is_usr8200() || machine_is_tw2662()) ++ machine_is_usr8200() || machine_is_tw2662() || ++ machine_is_ap42x()) + uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; + else + uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; diff --git a/target/linux/ixp4xx/patches-4.1/600-skb_avoid_dmabounce.patch b/target/linux/ixp4xx/patches-4.1/600-skb_avoid_dmabounce.patch new file mode 100644 index 0000000..5d6809d --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/600-skb_avoid_dmabounce.patch @@ -0,0 +1,23 @@ +--- a/net/core/skbuff.c ++++ b/net/core/skbuff.c +@@ -212,6 +212,9 @@ struct sk_buff *__alloc_skb(unsigned int + + if (sk_memalloc_socks() && (flags & SKB_ALLOC_RX)) + gfp_mask |= __GFP_MEMALLOC; ++#ifdef CONFIG_ARCH_IXP4XX ++ gfp_mask |= GFP_DMA; ++#endif + + /* Get the HEAD */ + skb = kmem_cache_alloc_node(cache, gfp_mask & ~__GFP_DMA, node); +@@ -1192,6 +1195,10 @@ int pskb_expand_head(struct sk_buff *skb + if (skb_shared(skb)) + BUG(); + ++#ifdef CONFIG_ARCH_IXP4XX ++ gfp_mask |= GFP_DMA; ++#endif ++ + size = SKB_DATA_ALIGN(size); + + if (skb_pfmemalloc(skb)) diff --git a/target/linux/ixp4xx/patches-4.1/900-ixp4xx-crypto-include-module.h.patch b/target/linux/ixp4xx/patches-4.1/900-ixp4xx-crypto-include-module.h.patch new file mode 100644 index 0000000..24c93dc --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/900-ixp4xx-crypto-include-module.h.patch @@ -0,0 +1,10 @@ +--- a/drivers/crypto/ixp4xx_crypto.c ++++ b/drivers/crypto/ixp4xx_crypto.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include diff --git a/target/linux/ixp4xx/patches-4.1/910-ixp4xx-nr_irq_lines.patch b/target/linux/ixp4xx/patches-4.1/910-ixp4xx-nr_irq_lines.patch new file mode 100644 index 0000000..06e09f4 --- /dev/null +++ b/target/linux/ixp4xx/patches-4.1/910-ixp4xx-nr_irq_lines.patch @@ -0,0 +1,22 @@ +--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c ++++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c +@@ -53,7 +53,7 @@ static int __init ixdp425_map_irq(const + }; + + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) +- return pci_irq_table[(slot + pin - 2) % 4]; ++ return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; + + return -1; + } +--- a/arch/arm/mach-ixp4xx/miccpt-pci.c ++++ b/arch/arm/mach-ixp4xx/miccpt-pci.c +@@ -54,7 +54,7 @@ static int __init miccpt_map_irq(const s + }; + + if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) +- return pci_irq_table[(slot + pin - 2) % 4]; ++ return pci_irq_table[(slot + pin - 2) % IRQ_LINES]; + + return -1; + } diff --git a/target/linux/kirkwood/Makefile b/target/linux/kirkwood/Makefile new file mode 100644 index 0000000..2fe1c84 --- /dev/null +++ b/target/linux/kirkwood/Makefile @@ -0,0 +1,24 @@ +# +# Copyright (C) 2009-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=kirkwood +BOARDNAME:=Marvell Kirkwood +FEATURES:=targz usb jffs2_nand nand ubifs +CPU_TYPE:=xscale +MAINTAINER:=Luka Perkov + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +KERNELNAME:=zImage dtbs + +DEFAULT_PACKAGES += uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/target/linux/kirkwood/base-files.mk b/target/linux/kirkwood/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/kirkwood/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/kirkwood/base-files/etc/diag.sh b/target/linux/kirkwood/base-files/etc/diag.sh new file mode 100755 index 0000000..716e6c9 --- /dev/null +++ b/target/linux/kirkwood/base-files/etc/diag.sh @@ -0,0 +1,38 @@ +#!/bin/sh +# Copyright (C) 2014 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/kirkwood.sh + +get_status_led() { + case $(kirkwood_board_name) in + dockstar|\ + goflexhome|\ + goflexnet|\ + pogo_e02) + status_led="status:orange:fault" + ;; + ea4500) + status_led="ea4500:white:health" + ;; + esac +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/kirkwood/base-files/etc/uci-defaults/01_leds b/target/linux/kirkwood/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..a8ba1f6 --- /dev/null +++ b/target/linux/kirkwood/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,49 @@ +#!/bin/sh +# +# Copyright (C) 2012-2014 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/kirkwood.sh + +board=$(kirkwood_board_name) + +case "$board" in +"dockstar") + ucidef_set_led_default "health" "health" "status:green:health" "1" + ucidef_set_led_default "fault" "fault" "status:orange:fault" "1" + ;; +"ea3500") + ucidef_set_led_default "power" "power" "ea3500:green:power" "1" + ;; +"ea4500") + ucidef_set_led_default "health" "health" "ea4500:white:health" "1" + ucidef_set_led_default "pulse" "pulse" "ea4500:white:pulse" "1" + ;; +"goflexhome" | \ +"goflexnet") + ucidef_set_led_default "health" "health" "status:green:health" "1" + ucidef_set_led_default "fault" "fault" "status:orange:fault" "0" + ;; +"ib62x0") + ucidef_set_led_default "health" "health" "ib62x0:green:os" "1" + ucidef_set_led_default "fault" "fault" "ib62x0:red:os" "1" + ;; +"pogo_e02") + ucidef_set_led_default "health" "health" "status:green:health" "1" + ucidef_set_led_default "fault" "fault" "status:orange:fault" "1" + ;; +"guruplug-server-plus") + ucidef_set_led_timer "health" "health" "guruplug:red:health" "200" "800" + ;; +"sheevaplug" | \ +"sheevaplug-esata") + ucidef_set_led_timer "health" "health" "sheevaplug:blue:health" "200" "800" + ;; +*) + ;; +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/kirkwood/base-files/etc/uci-defaults/02_network b/target/linux/kirkwood/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..150926e --- /dev/null +++ b/target/linux/kirkwood/base-files/etc/uci-defaults/02_network @@ -0,0 +1,66 @@ +#!/bin/sh +# +# Copyright (C) 2012-2014 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +set_lan_dhcp() { + local ifname=$1 + uci batch < /tmp/sysinfo/board_name + echo "$KIRKWOOD_MODEL" > /tmp/sysinfo/model +} + +kirkwood_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] || kirkwood_board_detect + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/kirkwood/config-3.18 b/target/linux/kirkwood/config-3.18 new file mode 100644 index 0000000..f488e9b --- /dev/null +++ b/target/linux/kirkwood/config-3.18 @@ -0,0 +1,319 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_THUMB is not set +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BLK_DEV_SD=y +CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set +# CONFIG_CACHE_L2X0 is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootdelay=1 root=/dev/mmcblk0p1 noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FEROCEON=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_LZO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MVEBU_UART=y +# CONFIG_DEBUG_MVEBU_UART_ALTERNATE is not set +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xf1012000 +# CONFIG_DEBUG_UART_PL01X is not set +CONFIG_DEBUG_UART_VIRT=0xfed12000 +CONFIG_DEBUG_UNCOMPRESS=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DLCI is not set +CONFIG_DNOTIFY=y +CONFIG_DTC=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_EMAC_ROCKCHIP is not set +CONFIG_EXT4_FS=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_MBCACHE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MVEBU=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KIRKWOOD_CLK=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_NETXBIG=y +CONFIG_LEDS_NS2=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_KIRKWOOD=y +CONFIG_MACH_MVEBU_ANY=y +# CONFIG_MACH_NETXBIG is not set +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_MVSDIO=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MV643XX_ETH=y +CONFIG_MVEBU_CLK_COMMON=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +# CONFIG_MVNETA is not set +CONFIG_MVSW61XX_PHY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MV88E6123_61_65=y +CONFIG_NET_DSA_MV88E6131=y +CONFIG_NET_DSA_MV88E6XXX=y +CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y +CONFIG_NET_DSA_TAG_DSA=y +CONFIG_NET_DSA_TAG_EDSA=y +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_ORION_IRQCHIP=y +CONFIG_ORION_TIMER=y +CONFIG_OUTER_CACHE=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MVEBU_SATA=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_KIRKWOOD=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PLAT_ORION=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +CONFIG_POWER_RESET_GPIO=y +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_QNAP is not set +# CONFIG_POWER_RESET_SYSCON is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_PREEMPT_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_REGMAP=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MV is not set +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +CONFIG_SCSI=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_ORION=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +# CONFIG_UBIFS_FS_XZ is not set +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_ORION=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_XHCI_MVEBU is not set +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFP is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WAN=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/kirkwood/image/Makefile b/target/linux/kirkwood/image/Makefile new file mode 100644 index 0000000..0aa75ff --- /dev/null +++ b/target/linux/kirkwood/image/Makefile @@ -0,0 +1,166 @@ +# +# Copyright (C) 2009-2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +NAND_BLOCKSIZE := 2048-128k + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Image/BuildKernel/Template + + $(CP) $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage + echo -ne '\x00\x00\x00\x00' >> $(BIN_DIR)/$(IMG_PREFIX)-zImage + $(call Image/BuildKernel/MkuImage, \ + none, 0x8000, 0x8000, \ + $(BIN_DIR)/$(IMG_PREFIX)-zImage, \ + $(BIN_DIR)/$(IMG_PREFIX)-uImage \ + ) + + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs + echo -ne '\x00\x00\x00\x00' >> $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs + $(call Image/BuildKernel/MkuImage, \ + none, 0x8000, 0x8000, \ + $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs, \ + $(BIN_DIR)/$(IMG_PREFIX)-uImage-initramfs \ + ) + endif + + ifneq ($(1),) + $(CP) $(DTS_DIR)/kirkwood-$(1).dtb $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb + + $(CP) $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-zImage + cat $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb >> $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-zImage + $(call Image/BuildKernel/MkuImage, \ + none, 0x8000, 0x8000, \ + $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-zImage, \ + $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-uImage \ + ) + + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-zImage-initramfs + cat $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb >> $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-zImage-initramfs + $(call Image/BuildKernel/MkuImage, \ + none, 0x8000, 0x8000, \ + $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-zImage-initramfs, \ + $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-uImage-initramfs \ + ) + endif + endif +endef + +define Image/InstallKernel/Template + + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_KERNEL),) + $(INSTALL_DIR) $(TARGET_DIR)/boot + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_UIMAGE),) + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-uImage $(TARGET_DIR)/boot/ + ln -sf $(IMG_PREFIX)-uImage $(TARGET_DIR)/boot/uImage + endif + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_ZIMAGE),) + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/ + ln -sf $(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/zImage + endif + endif + + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB),) + $(INSTALL_DIR) $(TARGET_DIR)/boot + ifneq ($(1),) + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(1).dtb $(TARGET_DIR)/boot/ + ln -sf $(IMG_PREFIX)-$(1).dtb $(TARGET_DIR)/boot/$(1).dtb + endif + endif +endef + +define Image/Build/jffs2-nand-2048-128k + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-$(1).img \ + bs=2048 conv=sync +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + ( \ + dd if=$(KDIR)/zImage bs=4096k conv=sync; \ + dd if=$(KDIR)/root.$(1) bs=128k conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-$(1).img +endef + +define Image/Build/ubifs + + ifneq ($($(PROFILE)_UBIFS_OPTS),) + $(CP) $(KDIR)/root.ubifs $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-rootfs.ubifs + endif +endef + +define Image/Build/ubi + + ifneq ($($(PROFILE)_UBI_OPTS),) + $(CP) $(KDIR)/root.ubi $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-rootfs.ubi + endif +endef + +Image/BuildKernel/Template/Generic=$(call Image/BuildKernel/Template) +Image/InstallKernel/Template/Generic=$(call Image/InstallKernel/Template) + +Image/BuildKernel/Template/DOCKSTAR=$(call Image/BuildKernel/Template,dockstar) +Image/InstallKernel/Template/DOCKSTAR=$(call Image/InstallKernel/Template,dockstar) + +Image/BuildKernel/Template/EA3500=$(call Image/BuildKernel/Template,ea3500) +Image/InstallKernel/Template/EA3500=$(call Image/InstallKernel/Template,ea3500) + +Image/BuildKernel/Template/EA4500=$(call Image/BuildKernel/Template,ea4500) +Image/InstallKernel/Template/EA4500=$(call Image/InstallKernel/Template,ea4500) + +Image/BuildKernel/Template/GOFLEXHOME=$(call Image/BuildKernel/Template,goflexhome) +Image/InstallKernel/Template/GOFLEXHOME=$(call Image/InstallKernel/Template,goflexhome) + +Image/BuildKernel/Template/GOFLEXNET=$(call Image/BuildKernel/Template,goflexnet) +Image/InstallKernel/Template/GOFLEXNET=$(call Image/InstallKernel/Template,goflexnet) + +Image/BuildKernel/Template/IB62X0=$(call Image/BuildKernel/Template,ib62x0) +Image/InstallKernel/Template/IB62X0=$(call Image/InstallKernel/Template,ib62x0) + +Image/BuildKernel/Template/ICONNECT=$(call Image/BuildKernel/Template,iconnect) +Image/InstallKernel/Template/ICONNECT=$(call Image/InstallKernel/Template,iconnect) + +Image/BuildKernel/Template/IOMEGA_IX2_200=$(call Image/BuildKernel/Template,iomega_ix2_200) +Image/InstallKernel/Template/IOMEGA_IX2_200=$(call Image/InstallKernel/Template,iomega_ix2_200) + +Image/BuildKernel/Template/NSA310S=$(call Image/BuildKernel/Template,nsa310s) +Image/InstallKernel/Template/NSA310S=$(call Image/InstallKernel/Template,nsa310s) + +Image/BuildKernel/Template/POGOE02=$(call Image/BuildKernel/Template,pogo_e02) +Image/InstallKernel/Template/POGOE02=$(call Image/InstallKernel/Template,pogo_e02) + +Image/BuildKernel/Template/SHEEVAPLUG=$(call Image/BuildKernel/Template,sheevaplug) +Image/InstallKernel/Template/SHEEVAPLUG=$(call Image/InstallKernel/Template,sheevaplug) + +Image/BuildKernel/Template/SHEEVAPLUGSATA=$(call Image/BuildKernel/Template,sheevaplug-esata) +Image/InstallKernel/Template/SHEEVAPLUGSATA=$(call Image/InstallKernel/Template,sheevaplug-esata) + +Image/BuildKernel/Template/GuruplugServerPlus=$(call Image/BuildKernel/Template,guruplug-server-plus) +Image/InstallKernel/Template/GuruplugServerPlus=$(call Image/InstallKernel/Template,guruplug-server-plus) + +Image/BuildKernel/Template/Topkick1281P2=$(call Image/BuildKernel/Template,topkick) +Image/InstallKernel/Template/Topkick1281P2=$(call Image/InstallKernel/Template,topkick) + +define Image/BuildKernel + $(call Image/BuildKernel/Template/$(PROFILE)) +endef + +define Image/InstallKernel + $(call Image/InstallKernel/Template/$(PROFILE)) +endef + +define Image/Build + $(if $(Image/Build/$(1)), \ + $(call Image/Build/$(1),$(1)), \ + $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE_SANITIZED)-$(1).img \ + ) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/kirkwood/image/ubinize.cfg b/target/linux/kirkwood/image/ubinize.cfg new file mode 100644 index 0000000..e4149ec --- /dev/null +++ b/target/linux/kirkwood/image/ubinize.cfg @@ -0,0 +1,13 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.ubifs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs +# Autoresize volume at first mount +vol_flags=autoresize diff --git a/target/linux/kirkwood/patches-3.18/110-ib62x0.patch b/target/linux/kirkwood/patches-3.18/110-ib62x0.patch new file mode 100644 index 0000000..153c41b --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/110-ib62x0.patch @@ -0,0 +1,20 @@ +--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts ++++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts +@@ -117,13 +117,13 @@ + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x600000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@700000 { ++ partition@200000 { + label = "root"; +- reg = <0x0700000 0xf900000>; ++ reg = <0x200000 0xfe00000>; + }; + + }; diff --git a/target/linux/kirkwood/patches-3.18/120-iomega_ix2_200.patch b/target/linux/kirkwood/patches-3.18/120-iomega_ix2_200.patch new file mode 100644 index 0000000..33f7004 --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/120-iomega_ix2_200.patch @@ -0,0 +1,13 @@ +--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts ++++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +@@ -192,8 +192,8 @@ + }; + + partition@400000 { +- label = "uInitrd"; +- reg = <0x540000 0x1000000>; ++ label = "rootfs"; ++ reg = <0x400000 0x1C00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-3.18/130-iconnect.patch b/target/linux/kirkwood/patches-3.18/130-iconnect.patch new file mode 100644 index 0000000..c95579d --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/130-iconnect.patch @@ -0,0 +1,41 @@ +--- a/arch/arm/boot/dts/kirkwood-iconnect.dts ++++ b/arch/arm/boot/dts/kirkwood-iconnect.dts +@@ -155,28 +155,23 @@ + status = "okay"; + + partition@0 { +- label = "uboot"; +- reg = <0x0000000 0xc0000>; ++ label = "u-boot"; ++ reg = <0x0000000 0xe0000>; + }; + +- partition@a0000 { +- label = "env"; +- reg = <0xa0000 0x20000>; ++ partition@e0000 { ++ label = "u-boot environment"; ++ reg = <0xe0000 0x100000>; + }; + + partition@100000 { +- label = "zImage"; +- reg = <0x100000 0x300000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@540000 { +- label = "initrd"; +- reg = <0x540000 0x300000>; +- }; +- +- partition@980000 { +- label = "boot"; +- reg = <0x980000 0x1f400000>; ++ partition@200000 { ++ label = "root"; ++ reg = <0x200000 0x1fe00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-3.18/140-dockstar.patch b/target/linux/kirkwood/patches-3.18/140-dockstar.patch new file mode 100644 index 0000000..b1ad669 --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/140-dockstar.patch @@ -0,0 +1,32 @@ +--- a/arch/arm/boot/dts/kirkwood-dockstar.dts ++++ b/arch/arm/boot/dts/kirkwood-dockstar.dts +@@ -77,18 +77,22 @@ + + partition@0 { + label = "u-boot"; +- reg = <0x0000000 0x100000>; +- read-only; ++ reg = <0x0000000 0xe0000>; ++ }; ++ ++ partition@e0000 { ++ label = "u-boot environment"; ++ reg = <0xe0000 0x100000>; + }; + + partition@100000 { +- label = "uImage"; +- reg = <0x0100000 0x400000>; ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; + }; + +- partition@500000 { +- label = "data"; +- reg = <0x0500000 0xfb00000>; ++ partition@200000 { ++ label = "root"; ++ reg = <0x200000 0xfe00000>; + }; + }; + diff --git a/target/linux/kirkwood/patches-3.18/150-pogoplug_e02.patch b/target/linux/kirkwood/patches-3.18/150-pogoplug_e02.patch new file mode 100644 index 0000000..561c07f --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/150-pogoplug_e02.patch @@ -0,0 +1,127 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -147,6 +147,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood- + kirkwood-openrd-base.dtb \ + kirkwood-openrd-client.dtb \ + kirkwood-openrd-ultimate.dtb \ ++ kirkwood-pogo_e02.dtb \ + kirkwood-rd88f6192.dtb \ + kirkwood-rd88f6281-z0.dtb \ + kirkwood-rd88f6281-a.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts +@@ -0,0 +1,114 @@ ++/dts-v1/; ++ ++#include "kirkwood.dtsi" ++#include "kirkwood-6281.dtsi" ++ ++/ { ++ model = "Cloud Engines Pogoplug E02"; ++ compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", "marvell,kirkwood"; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x10000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8 earlyprintk"; ++ }; ++ ++ ocp@f1000000 { ++ pinctrl: pin-controller@10000 { ++ pmx_usb_power_enable: pmx-usb-power-enable { ++ marvell,pins = "mpp29"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_green: pmx-led_green { ++ marvell,pins = "mpp48"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_orange: pmx-led_orange { ++ marvell,pins = "mpp49"; ++ marvell,function = "gpio"; ++ }; ++ }; ++ serial@12000 { ++ status = "ok"; ++ }; ++ }; ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange ++ &pmx_led_green >; ++ pinctrl-names = "default"; ++ ++ health { ++ label = "status:green:health"; ++ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; ++ default-state = "keep"; ++ }; ++ fault { ++ label = "status:orange:fault"; ++ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ regulators { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&pmx_usb_power_enable>; ++ pinctrl-names = "default"; ++ ++ usb_power: regulator@1 { ++ compatible = "regulator-fixed"; ++ reg = <1>; ++ regulator-name = "USB Power"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ regulator-always-on; ++ regulator-boot-on; ++ gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&nand { ++ chip-delay = <40>; ++ status = "okay"; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0x100000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "uImage"; ++ reg = <0x0100000 0x400000>; ++ }; ++ ++ partition@500000 { ++ label = "pogoplug"; ++ reg = <0x0500000 0x2000000>; ++ }; ++ ++ partition@2500000 { ++ label = "root"; ++ reg = <0x02500000 0x5b00000>; ++ }; ++}; ++ ++&mdio { ++ status = "okay"; ++ ++ ethphy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++}; ++ ++ð0 { ++ status = "okay"; ++ ethernet0-port@0 { ++ phy-handle = <ðphy0>; ++ }; ++}; diff --git a/target/linux/kirkwood/patches-3.18/160-ea4500.patch b/target/linux/kirkwood/patches-3.18/160-ea4500.patch new file mode 100644 index 0000000..386b5ea --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/160-ea4500.patch @@ -0,0 +1,180 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -120,6 +120,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood- + kirkwood-ds411.dtb \ + kirkwood-ds411j.dtb \ + kirkwood-ds411slim.dtb \ ++ kirkwood-ea4500.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-guruplug-server-plus.dtb \ + kirkwood-ib62x0.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/kirkwood-ea4500.dts +@@ -0,0 +1,167 @@ ++/* ++ * kirkwood-ea4500.dts - Device Tree file for Linksys EA4500 ++ * ++ * (c) 2013 Jonas Gorski ++ * (c) 2013 Deutsche Telekom Innovation Laboratories ++ * (c) 2014 Luka Perkov ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++ ++#include "kirkwood.dtsi" ++#include "kirkwood-6282.dtsi" ++ ++/ { ++ model = "Linksys EA4500"; ++ compatible = "linksys,ea4500", "marvell,kirkwood-88f6282", "marvell,kirkwood"; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x8000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8 earlyprintk"; ++ }; ++ ++ mbus { ++ pcie-controller { ++ status = "okay"; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; ++ ++ pcie@2,0 { ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ ocp@f1000000 { ++ pinctrl: pin-controller@10000 { ++ pmx_led_white_health: pmx-led-white-health { ++ marvell,pins = "mpp7"; ++ marvell,function = "gpo"; ++ }; ++ pmx_led_white_pulse: pmx-led-white-pulse { ++ marvell,pins = "mpp14"; ++ marvell,function = "gpio"; ++ }; ++ pmx_btn_wps: pmx-btn-wps { ++ marvell,pins = "mpp47"; ++ marvell,function = "gpio"; ++ }; ++ pmx_btn_reset: pmx-btn-reset { ++ marvell,pins = "mpp48"; ++ marvell,function = "gpio"; ++ }; ++ }; ++ ++ rtc@10300 { ++ status = "disabled"; ++ }; ++ ++ serial@12000 { ++ status = "okay"; ++ }; ++ ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; ++ pinctrl-names = "default"; ++ ++ button@15 { ++ label = "WPS Button"; ++ linux,code = ; ++ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button@16 { ++ label = "Reset Button"; ++ linux,code = ; ++ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; ++ pinctrl-names = "default"; ++ ++ white-health { ++ label = "ea4500:white:health"; ++ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ white-pulse { ++ label = "ea4500:white:pulse"; ++ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ mvsw61xx { ++ compatible = "marvell,88e6171"; ++ status = "okay"; ++ reg = <0x10>; ++ ++ mii-bus = <&mdio>; ++ cpu-port-0 = <5>; ++ cpu-port-1 = <6>; ++ is-indirect; ++ }; ++}; ++ ++&nand { ++ status = "okay"; ++ pinctrl-0 = <&pmx_nand>; ++ pinctrl-names = "default"; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0x80000>; ++ }; ++ ++ partition@80000 { ++ label = "u-boot environment"; ++ reg = <0x80000 0x20000>; ++ }; ++ ++ partition@200000 { ++ label = "kernel"; ++ reg = <0x200000 0x200000>; ++ }; ++ ++ partition@400000 { ++ label = "root"; ++ reg = <0x400000 0x1c00000>; ++ }; ++}; ++ ++&mdio { ++ status = "okay"; ++}; ++ ++ð0 { ++ status = "okay"; ++ ethernet0-port@0 { ++ speed = <1000>; ++ duplex = <1>; ++ }; ++}; ++ ++ð1 { ++ status = "okay"; ++ ethernet1-port@0 { ++ speed = <1000>; ++ duplex = <1>; ++ }; ++}; diff --git a/target/linux/kirkwood/patches-3.18/170-ea3500.patch b/target/linux/kirkwood/patches-3.18/170-ea3500.patch new file mode 100644 index 0000000..84645de --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/170-ea3500.patch @@ -0,0 +1,173 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -120,6 +120,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood- + kirkwood-ds411.dtb \ + kirkwood-ds411j.dtb \ + kirkwood-ds411slim.dtb \ ++ kirkwood-ea3500.dtb \ + kirkwood-ea4500.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-guruplug-server-plus.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/kirkwood-ea3500.dts +@@ -0,0 +1,160 @@ ++/* ++ * kirkwood-ea3500.dts - Device Tree file for Linksys EA3500 ++ * ++ * (c) 2013 Jonas Gorski ++ * (c) 2013 Deutsche Telekom Innovation Laboratories ++ * (c) 2014 Luka Perkov ++ * (c) 2014 Dan Walters ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++ ++#include "kirkwood.dtsi" ++#include "kirkwood-6282.dtsi" ++ ++/ { ++ model = "Linksys EA3500"; ++ compatible = "linksys,ea3500", "marvell,kirkwood-88f6282", "marvell,kirkwood"; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x4000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8 earlyprintk"; ++ }; ++ ++ mbus { ++ pcie-controller { ++ status = "okay"; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; ++ ++ pcie@2,0 { ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ ocp@f1000000 { ++ pinctrl: pin-controller@10000 { ++ pmx_led_green_power: pmx-led-green-power { ++ marvell,pins = "mpp7"; ++ marvell,function = "gpo"; ++ }; ++ pmx_btn_wps: pmx-btn-wps { ++ marvell,pins = "mpp47"; ++ marvell,function = "gpio"; ++ }; ++ pmx_btn_reset: pmx-btn-reset { ++ marvell,pins = "mpp48"; ++ marvell,function = "gpio"; ++ }; ++ }; ++ ++ rtc@10300 { ++ status = "disabled"; ++ }; ++ ++ serial@12000 { ++ status = "okay"; ++ }; ++ ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; ++ pinctrl-names = "default"; ++ ++ button@15 { ++ label = "WPS Button"; ++ linux,code = ; ++ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button@16 { ++ label = "Reset Button"; ++ linux,code = ; ++ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = < &pmx_led_green_power >; ++ pinctrl-names = "default"; ++ ++ green-power { ++ label = "ea3500:green:power"; ++ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ mvsw61xx { ++ compatible = "marvell,88e6171"; ++ status = "okay"; ++ reg = <0x10>; ++ ++ mii-bus = <&mdio>; ++ cpu-port-0 = <5>; ++ cpu-port-1 = <6>; ++ is-indirect; ++ }; ++}; ++ ++&nand { ++ status = "okay"; ++ pinctrl-0 = <&pmx_nand>; ++ pinctrl-names = "default"; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0x80000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "u-boot environment"; ++ reg = <0x80000 0x20000>; ++ }; ++ ++ partition@200000 { ++ label = "kernel"; ++ reg = <0x200000 0x200000>; ++ }; ++ ++ partition@400000 { ++ label = "root"; ++ reg = <0x400000 0x1200000>; ++ }; ++}; ++ ++&mdio { ++ status = "okay"; ++}; ++ ++ð0 { ++ status = "okay"; ++ ethernet0-port@0 { ++ speed = <1000>; ++ duplex = <1>; ++ }; ++}; ++ ++ð1 { ++ status = "okay"; ++ ethernet1-port@0 { ++ speed = <1000>; ++ duplex = <1>; ++ }; ++}; diff --git a/target/linux/kirkwood/patches-3.18/180-goflexhome.patch b/target/linux/kirkwood/patches-3.18/180-goflexhome.patch new file mode 100644 index 0000000..e54c853 --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/180-goflexhome.patch @@ -0,0 +1,140 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -122,6 +122,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood- + kirkwood-ds411slim.dtb \ + kirkwood-ea3500.dtb \ + kirkwood-ea4500.dtb \ ++ kirkwood-goflexhome.dtb \ + kirkwood-goflexnet.dtb \ + kirkwood-guruplug-server-plus.dtb \ + kirkwood-ib62x0.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/kirkwood-goflexhome.dts +@@ -0,0 +1,127 @@ ++/dts-v1/; ++ ++#include "kirkwood.dtsi" ++#include "kirkwood-6281.dtsi" ++ ++/ { ++ model = "Seagate GoFlex Home"; ++ compatible = "seagate,goflexhome", "marvell,kirkwood-88f6281", "marvell,kirkwood"; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x8000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; ++ stdout-path = &uart0; ++ }; ++ ++ ocp@f1000000 { ++ pinctrl: pin-controller@10000 { ++ pmx_usb_power_enable: pmx-usb-power-enable { ++ marvell,pins = "mpp29"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_white: pmx-led-white { ++ marvell,pins = "mpp40"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_green: pmx-led_green { ++ marvell,pins = "mpp46"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_orange: pmx-led-orange { ++ marvell,pins = "mpp47"; ++ marvell,function = "gpio"; ++ }; ++ }; ++ serial@12000 { ++ status = "ok"; ++ }; ++ ++ sata@80000 { ++ status = "okay"; ++ nr-ports = <2>; ++ }; ++ ++ }; ++ gpio-leds { ++ compatible = "gpio-leds"; ++ ++ health { ++ label = "status:green:health"; ++ gpios = <&gpio1 14 1>; ++ linux,default-trigger = "default-on"; ++ }; ++ fault { ++ label = "status:orange:fault"; ++ gpios = <&gpio1 15 1>; ++ }; ++ misc { ++ label = "status:white:misc"; ++ gpios = <&gpio1 8 1>; ++ linux,default-trigger = "ide-disk"; ++ }; ++ }; ++ regulators { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&pmx_usb_power_enable>; ++ pinctrl-names = "default"; ++ ++ usb_power: regulator@1 { ++ compatible = "regulator-fixed"; ++ reg = <1>; ++ regulator-name = "USB Power"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ regulator-always-on; ++ regulator-boot-on; ++ gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&nand { ++ chip-delay = <40>; ++ status = "okay"; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0x100000>; ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "uImage"; ++ reg = <0x0100000 0x400000>; ++ }; ++ ++ partition@500000 { ++ label = "pogoplug"; ++ reg = <0x0500000 0x2000000>; ++ }; ++ ++ partition@2500000 { ++ label = "root"; ++ reg = <0x02500000 0xd800000>; ++ }; ++}; ++ ++&mdio { ++ status = "okay"; ++ ++ ethphy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++}; ++ ++ð0 { ++ status = "okay"; ++ ethernet0-port@0 { ++ phy-handle = <ðphy0>; ++ }; ++}; diff --git a/target/linux/kirkwood/patches-3.18/190-nsa310s.patch b/target/linux/kirkwood/patches-3.18/190-nsa310s.patch new file mode 100644 index 0000000..9766455 --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/190-nsa310s.patch @@ -0,0 +1,300 @@ +--- /dev/null ++++ b/arch/arm/boot/dts/kirkwood-nsa310s.dts +@@ -0,0 +1,287 @@ ++/dts-v1/; ++ ++#include "kirkwood.dtsi" ++#include "kirkwood-6281.dtsi" ++ ++/ { ++ model = "ZyXEL NSA310S"; ++ compatible = "zyxel,nsa320s", "marvell,kirkwood-88f6702", "marvell,kirkwood"; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x10000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8 earlyprintk"; ++ stdout-path = &uart0; ++ }; ++ ++ mbus { ++ pcie-controller { ++ status = "okay"; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ ocp@f1000000 { ++ pinctrl: pin-controller@10000 { ++ pinctrl-names = "default"; ++ ++ pmx_sata0: pmx-sata0 { ++ marvell,pins; ++ marvell,function = "sata0"; ++ }; ++ pmx_sata1: pmx-sata1 { ++ marvell,pins; ++ marvell,function = "sata1"; ++ }; ++ pmx_usb_power: pmx-usb-power { ++ marvell,pins = "mpp21"; ++ marvell,function = "gpio"; ++ }; ++ pmx_pwr_off: pmx-pwr-off { ++ marvell,pins = "mpp27"; ++ marvell,function = "gpio"; ++ }; ++ pmx_btn_reset: pmx-btn-reset { ++ marvell,pins = "mpp24"; ++ marvell,function = "gpio"; ++ }; ++ pmx_btn_copy: pmx-btn-copy { ++ marvell,pins = "mpp25"; ++ marvell,function = "gpio"; ++ }; ++ pmx_btn_power: pmx-btn-power { ++ marvell,pins = "mpp26"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_hdd2_green: pmx-led-hdd2-green { ++ marvell,pins = "mpp34"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_hdd2_red: pmx-led-hdd2-red { ++ marvell,pins = "mpp12"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_usb_green: pmx-led-usb-green { ++ marvell,pins = "mpp15"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_copy_green: pmx-led-copy-green { ++ marvell,pins = "mpp22"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_copy_red: pmx-led-copy-red { ++ marvell,pins = "mpp23"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_sys_green: pmx-led-sys-green { ++ marvell,pins = "mpp28"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_sys_orange: pmx-led-sys-orange { ++ marvell,pins = "mpp29"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_hdd1_green: pmx-led-hdd1-green { ++ marvell,pins = "mpp16"; ++ marvell,function = "gpio"; ++ }; ++ pmx_led_hdd1_red: pmx-led-hdd1-red { ++ marvell,pins = "mpp13"; ++ marvell,function = "gpio"; ++ }; ++ pmx_pwr_sata1: pmx-pwr-sata1 { ++ marvell,pins = "mpp33"; ++ marvell,function = "gpio"; ++ }; ++ }; ++ ++ serial@12000 { ++ status = "okay"; ++ }; ++ ++ sata@80000 { ++ status = "okay"; ++ nr-ports = <2>; ++ }; ++ ++ rtc@10300 { ++ status = "disabled"; ++ }; ++ ++ i2c@11000 { ++ status = "okay"; ++ ht1382: rtc@68 { ++ compatible = "htk,ht1382"; ++ reg = <0x68>; ++ }; ++ }; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmx_usb_power &pmx_pwr_sata1>; ++ ++ usb0_power: regulator@1 { ++ compatible = "regulator-fixed"; ++ reg = <1>; ++ regulator-name = "USB Power"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ enable-active-high; ++ gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ sata1_power: regulator@2 { ++ compatible = "regulator-fixed"; ++ reg = <2>; ++ regulator-name = "SATA1 Power"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ enable-active-high; ++ gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; ++ pinctrl-names = "default"; ++ ++ button@1 { ++ label = "Power Button"; ++ linux,code = ; ++ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; ++ }; ++ button@2 { ++ label = "Copy Button"; ++ linux,code = ; ++ gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; ++ }; ++ button@3 { ++ label = "Reset Button"; ++ linux,code = ; ++ gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red ++ &pmx_led_usb_green ++ &pmx_led_sys_green &pmx_led_sys_orange ++ &pmx_led_copy_green &pmx_led_copy_red ++ &pmx_led_hdd1_green &pmx_led_hdd1_red>; ++ pinctrl-names = "default"; ++ ++ green-sys { ++ label = "nsa310s:green:sys"; ++ gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "timer"; ++ }; ++ orange-sys { ++ label = "nsa310s:orange:sys"; ++ gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; ++ }; ++ green-hdd1 { ++ label = "nsa310s:green:hdd1"; ++ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; ++ }; ++ red-hdd1 { ++ label = "nsa310s:red:hdd1"; ++ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; ++ }; ++ green-hdd2 { ++ label = "nsa310s:green:hdd2"; ++ gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ }; ++ red-hdd2 { ++ label = "nsa310s:red:hdd2"; ++ gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; ++ }; ++ green-usb { ++ label = "nsa310s:green:usb"; ++ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; ++ }; ++ green-copy { ++ label = "nsa310s:green:copy"; ++ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "ide-disk"; ++ }; ++ red-copy { ++ label = "nsa310s:red:copy"; ++ gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ gpio_poweroff { ++ compatible = "gpio-poweroff"; ++ pinctrl-0 = <&pmx_pwr_off>; ++ pinctrl-names = "default"; ++ gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&nand { ++ status = "okay"; ++ chip-delay = <35>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0xe0000>; ++ }; ++ ++ partition@e0000 { ++ label = "u-boot environment"; ++ reg = <0xe0000 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "second stage u-boot"; ++ reg = <0x100000 0x200000>; ++ }; ++ ++ partition@200000 { ++ label = "root"; ++ reg = <0x200000 0xfe00000>; ++ }; ++}; ++ ++&mdio { ++ status = "okay"; ++ ethphy0: ethernet-phy@1 { ++ compatible = "marvell,88e1318s"; ++ reg = <1>; ++ marvell,reg-init = <0x1 0x16 0x0 0x3>, ++ <0x1 0x10 0x0 0x1017>, ++ <0x1 0x11 0x0 0x4408>, ++ <0x1 0x16 0x0 0x0>, ++ <0x1 0x4 0x0 0x1e1>, ++ <0x1 0x9 0x0 0x300>, ++ <0x1 0x10 0x0 0x3860>, ++ <0x1 0x0 0x0 0x9140>; ++ }; ++}; ++ ++ð0 { ++ status = "okay"; ++ ++ ethernet0-port@0 { ++ phy-handle = <ðphy0>; ++ }; ++}; +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -145,6 +145,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood- + kirkwood-ns2mini.dtb \ + kirkwood-nsa310.dtb \ + kirkwood-nsa310a.dtb \ ++ kirkwood-nsa310s.dtb \ + kirkwood-openblocks_a6.dtb \ + kirkwood-openblocks_a7.dtb \ + kirkwood-openrd-base.dtb \ diff --git a/target/linux/kirkwood/patches-3.18/200-disable-tso.patch b/target/linux/kirkwood/patches-3.18/200-disable-tso.patch new file mode 100644 index 0000000..4e8126e --- /dev/null +++ b/target/linux/kirkwood/patches-3.18/200-disable-tso.patch @@ -0,0 +1,35 @@ +From: Ezequiel Garcia +Subject: [PATCH] net: mv643xx_eth: Make TSO disabled by default + +Data corruption has been observed to be produced by TSO. For instance, +accessing files on a NFS-server with TSO enabled results in different data +transferred each time. + +This has been observed only on Kirkwood platforms, i.e. with the mv643xx_eth +driver. Same tests on platforms using the mvneta ethernet driver have +passed without errors. + +Make TSO disabled by default for now, until we can found a proper fix +for the regression. + +Fixes: 3ae8f4e0b98 ('net: mv643xx_eth: Implement software TSO') +Reported-by: Slawomir Gajzner gmail.com> +Reported-by: Julien D'Ascenzio yahoo.fr> +Signed-off-by: Ezequiel Garcia free-electrons.com> +--- +--- a/drivers/net/ethernet/marvell/mv643xx_eth.c ++++ b/drivers/net/ethernet/marvell/mv643xx_eth.c +@@ -3112,11 +3112,11 @@ static int mv643xx_eth_probe(struct plat + dev->watchdog_timeo = 2 * HZ; + dev->base_addr = 0; + +- dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; ++ dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; + dev->vlan_features = dev->features; + + dev->features |= NETIF_F_RXCSUM; +- dev->hw_features = dev->features; ++ dev->hw_features = dev->features | NETIF_F_TSO; + + dev->priv_flags |= IFF_UNICAST_FLT; + dev->gso_max_segs = MV643XX_MAX_TSO_SEGS; diff --git a/target/linux/kirkwood/profiles/100-generic.mk b/target/linux/kirkwood/profiles/100-generic.mk new file mode 100644 index 0000000..770bbae --- /dev/null +++ b/target/linux/kirkwood/profiles/100-generic.mk @@ -0,0 +1,21 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Generic + NAME:=Generic (default) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-kirkwood +endef + +define Profile/Generic/Description + Package set compatible with most Marvell Kirkwood based boards. +endef + +$(eval $(call Profile,Generic)) diff --git a/target/linux/kirkwood/profiles/110-nas.mk b/target/linux/kirkwood/profiles/110-nas.mk new file mode 100644 index 0000000..bf97437 --- /dev/null +++ b/target/linux/kirkwood/profiles/110-nas.mk @@ -0,0 +1,132 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/DOCKSTAR + NAME:=Seagate FreeAgent Dockstar + PACKAGES:= \ + kmod-rtc-marvell kmod-usb2 kmod-usb-storage +endef + +define Profile/DOCKSTAR/Description + Package set compatible with Seagate FreeAgent Dockstar board. +endef + +DOCKSTAR_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +DOCKSTAR_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,DOCKSTAR)) + +define Profile/GOFLEXHOME + NAME:=Seagate GoFlexHome + PACKAGES:= \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-usb2 kmod-usb-storage \ + uboot-envtools +endef + +define Profile/GOFLEXHOME/Description + Package set compatible with Seagate GoFlexHome +endef + +GOFLEXHOME_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +GOFLEXHOME_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,GOFLEXHOME)) + +define Profile/GOFLEXNET + NAME:=Seagate GoFlexNet + PACKAGES:= \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-usb2 kmod-usb-storage +endef + +define Profile/GOFLEXNET/Description + Package set compatible with Seagate GoFlexNet +endef + +GOFLEXNET_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +GOFLEXNET_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,GOFLEXNET)) + +define Profile/IB62X0 + NAME:=RaidSonic ICY BOX IB-NAS62x0 + PACKAGES:= \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-usb2 kmod-usb-storage +endef + +define Profile/IB62X0/Description + Package set compatible with RaidSonic ICY BOX IB-NAS62x0 board. +endef + +IB62X0_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +IB62X0_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,IB62X0)) + +define Profile/ICONNECT + NAME:=Iomega Iconnect + PACKAGES:= \ + kmod-usb2 kmod-usb-storage +endef + +define Profile/ICONNECT/Description + Package set compatible with Iomega Iconnect board. +endef + +ICONNECT_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +ICONNECT_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,ICONNECT)) + +define Profile/IOMEGA_IX2_200 + NAME:=Iomega StorCenter ix2-200 + PACKAGES:= \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-usb2 kmod-usb-storage +endef + +define Profile/IOMEGA_IX2_200/Description + Package set compatible with Iomega StorCenter ix2-200 board. +endef + +IOMEGA_IX2_200_UBIFS_OPTS:="-m 512 -e 15872 -c 2048" +IOMEGA_IX2_200_UBI_OPTS:="-m 512 -p 16384 -s 256" + +$(eval $(call Profile,IOMEGA_IX2_200)) + +define Profile/NSA310S + NAME:=ZyXEL NSA310S + PACKAGES:= \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-usb2 kmod-usb-storage +endef + +define Profile/NSA310S/Description + Package set compatible with ZyXEL NSA310S board. +endef + +NSA310S_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +NSA310S_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,NSA310S)) + +define Profile/POGOE02 + NAME:=Cloud Engines Pogoplug E02 + PACKAGES:= \ + kmod-usb2 kmod-usb-storage +endef + +define Profile/POGOE02/Description + Package set compatible with Cloud Engines Pogoplug E02 board. +endef + +POGOE02_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +POGOE02_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,POGOE02)) diff --git a/target/linux/kirkwood/profiles/115-router.mk b/target/linux/kirkwood/profiles/115-router.mk new file mode 100644 index 0000000..f273f36 --- /dev/null +++ b/target/linux/kirkwood/profiles/115-router.mk @@ -0,0 +1,38 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/EA3500 + NAME:=Linksys EA3500 + PACKAGES:= \ + kmod-mwl8k kmod-usb2 kmod-usb-storage \ + swconfig wpad-mini +endef + +define Profile/EA3500/Description + Package set compatible with Linksys EA3500 board. +endef + +EA3500_UBIFS_OPTS:="-m 512 -e 15872 -c 4096" +EA3500_UBI_OPTS:="-m 512 -p 16384 -s 256" + +$(eval $(call Profile,EA3500)) + +define Profile/EA4500 + NAME:=Linksys EA4500 + PACKAGES:= \ + kmod-mwl8k kmod-usb2 kmod-usb-storage \ + swconfig wpad-mini +endef + +define Profile/EA4500/Description + Package set compatible with Linksys EA4500 board. +endef + +EA4500_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +EA4500_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,EA4500)) diff --git a/target/linux/kirkwood/profiles/120-plug.mk b/target/linux/kirkwood/profiles/120-plug.mk new file mode 100644 index 0000000..3f92f89 --- /dev/null +++ b/target/linux/kirkwood/profiles/120-plug.mk @@ -0,0 +1,76 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/SHEEVAPLUG + NAME:=Globalscale Technologies SheevaPlug + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core +endef + +define Profile/SHEEVAPLUG/Description + Package set compatible with Globalscale Technologies SheevaPlug board. +endef + +SHEEVAPLUG_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +SHEEVAPLUG_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,SHEEVAPLUG)) + +define Profile/SHEEVAPLUGSATA + NAME:=Globalscale Technologies eSATA SheevaPlug + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata +endef + +define Profile/SHEEVAPLUGSATA/Description + Package set compatible with Globalscale Technologies eSATA SheevaPlug board. +endef + +SHEEVAPLUGSATA_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +SHEEVAPLUGSATA_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,SHEEVAPLUGSATA)) + +define Profile/GuruplugServerPlus + NAME:=Globalscale Technologies Guruplug Server Plus + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-btmrvl kmod-btmrvl-sdio kmod-libertas kmod-libertas-sdio \ + wpad-mini +endef + +define Profile/GuruplugServerPlus/Description + Package set compatible with Globalscale Technologies Guruplug Server Plus board. +endef + +GuruplugServerPlus_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +GuruplugServerPlus_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,GuruplugServerPlus)) + +define Profile/Topkick1281P2 + NAME:=Univeral Scientific Industrial Co. Topkick-1281P2 + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata +endef + +define Profile/Topkick1281P2/Description + Package set compatible with Univeral Scientific Industrial Co. Topkick-1281P2 board. +endef + +Topkick1281P2_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +Topkick1281P2_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,Topkick1281P2)) diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile new file mode 100644 index 0000000..d19be82 --- /dev/null +++ b/target/linux/lantiq/Makefile @@ -0,0 +1,25 @@ +# +# Copyright (C) 2007-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +BOARD:=lantiq +BOARDNAME:=Lantiq +FEATURES:=squashfs +SUBTARGETS=xway xrx200 +MAINTAINER:=John Crispin + +KERNEL_PATCHVER:=4.1 + +CPU_TYPE:=mips32r2 + +define Target/Description + Build firmware images for Lantiq SoC +endef + +include $(INCLUDE_DIR)/target.mk + +$(eval $(call BuildTarget)) diff --git a/target/linux/lantiq/base-files.mk b/target/linux/lantiq/base-files.mk new file mode 100644 index 0000000..d6682bd --- /dev/null +++ b/target/linux/lantiq/base-files.mk @@ -0,0 +1,5 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef + + diff --git a/target/linux/lantiq/base-files/etc/diag.sh b/target/linux/lantiq/base-files/etc/diag.sh new file mode 100644 index 0000000..26f0a3c --- /dev/null +++ b/target/linux/lantiq/base-files/etc/diag.sh @@ -0,0 +1,42 @@ +#!/bin/sh +# Copyright (C) 2012-2013 OpenWrt.org + +. /lib/functions/leds.sh + +status_led="power" + +set_state() { + [ -d /sys/class/leds/power2/ ] && { + + case "$1" in + preinit) + led_set_attr "power2" "trigger" "heartbeat" + status_led_on + ;; + failsafe) + led_off "power2" + status_led_set_timer 100 100 + ;; + done) + led_off "power2" + ;; + esac + return + } + + case "$1" in + preinit) + status_led_set_heartbeat + ;; + failsafe) + [ -d /sys/class/leds/power1 ] && { + status_led_off + led_timer "power1" 100 100 + } || status_led_set_timer 100 100 + ;; + done) + status_led_on + led_off "power1" + ;; + esac +} diff --git a/target/linux/lantiq/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom b/target/linux/lantiq/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom new file mode 100644 index 0000000..5f1cb00 --- /dev/null +++ b/target/linux/lantiq/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom @@ -0,0 +1,60 @@ +#!/bin/sh +# based on gabors ralink wisoc implementation + +rt2x00_eeprom_die() { + echo "rt2x00 eeprom: " "$*" + exit 1 +} + +rt2x00_eeprom_extract() { + local part=$1 + local offset=$2 + local count=$3 + local swab=$4 + local mtd + + . /lib/functions.sh + + mtd=$(find_mtd_part $part) + [ -n "$mtd" ] || \ + rt2x00_eeprom_die "no mtd device found for partition $part" + + if [ $swab -gt 0 ]; then + dd if=$mtd of=/lib/firmware/$FIRMWARE bs=2 skip=$offset count=$count conv=swab || \ + rt2x00_eeprom_die "failed to extract from $mtd" + else + dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=$count || \ + rt2x00_eeprom_die "failed to extract from $mtd" + fi +} + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 +. /lib/functions/lantiq.sh + +case "$FIRMWARE" in +"RT2860.eeprom" ) + local board=$(lantiq_board_name) + case $board in + ARV7510PW22|ARV7519PW|ARV752DPW|ARV752DPW22|VGV7519) + rt2x00_eeprom_extract "board_config" 520 256 1 + ;; + ARV7525PW) + rt2x00_eeprom_extract "board_config" 1040 512 0 + ;; + *) + rt2x00_eeprom_die "board $board is not supported yet" + ;; + esac + ;; +"RT3062.eeprom" ) + local board=$(lantiq_board_name) + case $board in + VGV7510KW22) + rt2x00_eeprom_extract "board_config" 520 256 1 + ;; + *) + rt2x00_eeprom_die "board $board is not supported yet" + ;; + esac + ;; +esac diff --git a/target/linux/lantiq/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/target/linux/lantiq/base-files/etc/hotplug.d/firmware/11-ath10k-caldata new file mode 100644 index 0000000..0d8084f --- /dev/null +++ b/target/linux/lantiq/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -0,0 +1,51 @@ +#!/bin/sh +# Based on ar71xx 11-ath10k-caldata and 10-rt2x00-eeprom + +ath10k_caldata_die() { + echo "ath10k caldata: " "$*" + exit 1 +} + +ath10k_caldata_extract() { + local part=$1 + local offset=$2 + local mtd + + . /lib/functions.sh + + mtd=$(find_mtd_part $part) + [ -n "$mtd" ] || \ + ath10k_caldata_die "no mtd device found for partition $part" + + dd if=$mtd of=/lib/firmware/$FIRMWARE bs=1 skip=$offset count=2116 || \ + ath10k_caldata_die "failed to extract from $mtd" +} + +ath10k_caldata_set_macaddr() { + local macaddr=$1 + + macaddr_2bin $macaddr | dd of=/lib/firmware/$FIRMWARE \ + conv=notrunc bs=1 seek=6 count=6 +} + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 +. /lib/functions.sh +. /lib/functions/system.sh +. /lib/functions/lantiq.sh + +case "$FIRMWARE" in +"ath10k/cal-pci-0000:02:00.0.bin") + local board=$(lantiq_board_name) + case $board in + BTHOMEHUBV5A) + local lan_mac=$(mtd_get_mac_binary caldata 4364) + local wifi_mac=$(macaddr_add "$lan_mac" 3) + ath10k_caldata_extract "caldata" 20480 + ath10k_caldata_set_macaddr $wifi_mac + ;; + *) + ath10k_caldata_die "board $board is not supported yet" + ;; + esac + ;; +esac diff --git a/target/linux/lantiq/base-files/etc/init.d/dsl_fs b/target/linux/lantiq/base-files/etc/init.d/dsl_fs new file mode 100755 index 0000000..ccba4ae --- /dev/null +++ b/target/linux/lantiq/base-files/etc/init.d/dsl_fs @@ -0,0 +1,35 @@ +#!/bin/sh /etc/rc.common +# Copyright (C) 2014 OpenWrt.org + +. $IPKG_INSTROOT/lib/functions.sh + +START=30 + +boot() { + MTD=$(find_mtd_index dsl_fw) + + grep /lib/firmware/lantiq /proc/mounts && umount /lib/firmware/lantiq + + mkdir -p /lib/firmware/lantiq + [ "$MTD" -gt 0 ] || return 0 + + mount -t tmpfs none /lib/firmware/lantiq + case "$(dd if=/dev/mtd$MTD bs=2 count=1 2>/dev/null | hexdump -n 2 -e '1/1 "%02x"')" in + 1985) + mkdir -p /tmp/fw_mnt + mount -t jffs2 /dev/mtdblock$MTD /tmp/fw_mnt + cp -a /tmp/fw_mnt/*.bin /lib/firmware/lantiq/ + umount /tmp/fw_mnt + rmdir /tmp/fw_mnt + ;; + 1f8b) + tar xz -C /lib/firmware/lantiq < /dev/mtd$MTD + ;; + *) + echo "No DSL firmware detected in /dev/mtd$MTD (dsl_fw)" + return 0 + ;; + esac + + [ -e /lib/firmware/vdsl.bin ] || ln -s /lib/firmware/lantiq/vr9_dsl_fw_annex_b.bin /lib/firmware/vdsl.bin +} diff --git a/target/linux/lantiq/base-files/etc/init.d/esi b/target/linux/lantiq/base-files/etc/init.d/esi new file mode 100755 index 0000000..ca79070 --- /dev/null +++ b/target/linux/lantiq/base-files/etc/init.d/esi @@ -0,0 +1,7 @@ +#!/bin/sh /etc/rc.common +# Copyright (C) 2013 OpenWrt.org + +START=19 +start() { + esi $(printf '%012X' $((1+0x$(tr -d : /dev/console || : +} diff --git a/target/linux/lantiq/base-files/etc/inittab b/target/linux/lantiq/base-files/etc/inittab new file mode 100644 index 0000000..46a1312 --- /dev/null +++ b/target/linux/lantiq/base-files/etc/inittab @@ -0,0 +1,3 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K stop +ttyLTQ0::askfirst:/bin/ash --login diff --git a/target/linux/lantiq/base-files/etc/uci-defaults/01_leds b/target/linux/lantiq/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..b9e5420 --- /dev/null +++ b/target/linux/lantiq/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,77 @@ +#!/bin/sh +# +# Copyright (C) 2011 OpenWrt.org +# based on ar71xx +# + +. /lib/functions/uci-defaults.sh +. /lib/functions/lantiq.sh + +[ -e "/sys/class/leds/wifi" ] && ucidef_set_led_wlan "wifi" "wifi" "wifi" "phy0tpt" +[ -e "/sys/class/leds/usb" ] && ucidef_set_led_usbdev "usb" "usb" "usb" "1-1" +[ -e "/sys/class/leds/usb2" ] && ucidef_set_led_usbdev "usb2" "usb2" "usb2" "2-1" +[ -e "/sys/class/leds/internet" ] && ucidef_set_led_netdev "internet" "internet" "internet" "pppoe-wan" + +board=$(lantiq_board_name) + +case "$board" in +VG3503J) + ucidef_set_led_netdev "vdsl" "vdsl" "bt:green:dsl" "ptm0" + ;; +BTHOMEHUBV2B) + ucidef_set_led_default "power" "power" "soc:blue:power" "1" +# ucidef_set_led_wlan "wifi" "wifi" "soc:blue:wireless" "phy0radio" + ucidef_set_led_wlan "wifi" "wifi" "soc:blue:wireless" "phy0tpt" + ucidef_set_led_netdev "internet" "internet" "soc:blue:broadband" "pppoa-wan" + ucidef_set_led_usbdev "usb" "usb" "soc:blue:phone" "1-1" + ;; +BTHOMEHUBV3A|BTHOMEHUBV5A) + ucidef_set_led_default "power" "power" "soc:blue:power" "1" + ucidef_set_led_wlan "wifi" "wifi" "soc:blue:wireless" "phy0tpt" + ucidef_set_led_netdev "internet" "internet" "soc:blue:broadband" "pppoa-wan" + ;; +VGV7510KW22) + ucidef_set_led_default "power" "power" "power" "1" + ucidef_set_led_default "power2" "power2" "power2" "0" + ucidef_set_led_wlan "wifi" "wifi" "wifi" "phy0radio" + ucidef_set_led_netdev "dsl" "dsl" "dsl" "nas0" + ucidef_set_led_netdev "internet_green" "internet_green" "internet_green" "pppoe-wan" + ;; +VGV7519) + ucidef_set_led_default "power" "power" "power" "0" + ucidef_set_led_default "power2" "power2" "power2" "1" + ucidef_set_led_wlan "wireless_yellow" "wireless_yellow" "wireless_yellow" "phy0radio" + ucidef_set_led_netdev "internet_yellow" "internet_yellow" "internet_yellow" "nas0" + ucidef_set_led_netdev "broadband_yellow" "broadband_yellow" "broadband_yellow" "pppoe-wan" + ;; +P2812HNUF*) + ucidef_set_led_default "power" "power" "power" "0" + ucidef_set_led_default "power2" "power2" "power2" "1" + ucidef_set_led_wlan "wireless_green" "wireless_green" "wireless_green" "phy0radio" + ucidef_set_led_netdev "dsl" "dsl" "dsl" "nas0" + ucidef_set_led_netdev "internet_green" "internet_green" "internet_green" "pppoe-wan" + ;; +ARV7519RW22) + ucidef_set_led_default "power" "power" "power" "1" + ucidef_set_led_netdev "internet_green" "internet_green" "internet_green" "pppoe-wan" + ucidef_set_led_netdev "lan" "lan" "lan" "eth0.1" + ;; +ARV8539PW22) + ucidef_set_led_default "power" "power" "soc:green:power" "1" + ucidef_set_led_default "power2" "power2" "soc:red:power" "0" + ucidef_set_led_wlan "wifi" "wifi" "soc:green:wireless" "phy0tpt" + ucidef_set_led_netdev "dsl" "dsl" "soc:green:dsl" "nas0" + ucidef_set_led_netdev "online" "online" "soc:green:online" "pppoe-wan" + ;; +*) + ;; +esac + +for a in `ls /sys/class/leds/`; do + grep -q "\[none\]" /sys/class/leds/$a/trigger + [ $? -eq 0 ] && ucidef_set_led_default $a $a $a `cat /sys/class/leds/$a/brightness` +done + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/lantiq/base-files/etc/uci-defaults/02_network b/target/linux/lantiq/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..b22060c --- /dev/null +++ b/target/linux/lantiq/base-files/etc/uci-defaults/02_network @@ -0,0 +1,211 @@ +#!/bin/sh +# +# Copyright (C) 2011-2012 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +set_atm_wan() { + local vpi=$1 + local vci=$2 + local encaps=$3 + local payload=$4 + uci batch < /tmp/sysinfo/board_name + echo $model > /tmp/sysinfo/model +} + +lantiq_board_model() { + local model + + [ -f /tmp/sysinfo/model ] && model=$(cat /tmp/sysinfo/model) + [ -z "$model" ] && model="unknown" + + echo "$model" +} + +lantiq_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/lantiq/base-files/lib/functions/lantiq_dsl.sh b/target/linux/lantiq/base-files/lib/functions/lantiq_dsl.sh new file mode 100755 index 0000000..22e65cb --- /dev/null +++ b/target/linux/lantiq/base-files/lib/functions/lantiq_dsl.sh @@ -0,0 +1,640 @@ +#!/bin/sh /etc/rc.common +# Copyright (C) 2012-2014 OpenWrt.org + +if [ "$( which vdsl_cpe_control )" ]; then + XDSL_CTRL=vdsl_cpe_control +else + XDSL_CTRL=dsl_cpe_control +fi + +# +# Basic functions to send CLI commands to the vdsl_cpe_control daemon +# +dsl_cmd() { + killall -0 ${XDSL_CTRL} && ( + lock /var/lock/dsl_pipe + echo "$@" > /tmp/pipe/dsl_cpe0_cmd + cat /tmp/pipe/dsl_cpe0_ack + lock -u /var/lock/dsl_pipe + ) +} +dsl_val() { + echo $(expr "$1" : '.*'$2'=\([-\.[:alnum:]]*\).*') +} +dsl_string() { + echo $(expr "$1" : '.*'$2'=(\([A-Z0-9,]*\))') +} + +# +# Simple divide by 10 routine to cope with one decimal place +# +dbt() { + local a=$(expr $1 / 10) + local b=$(expr $1 % 10) + echo "${a}.${b}" +} +# +# Take a number and convert to k or meg +# +scale() { + local val=$1 + local a + local b + + if [ "$val" -gt 1000000 ]; then + a=$(expr $val / 1000) + b=$(expr $a % 1000) + a=$(expr $a / 1000) + printf "%d.%03d Mb" ${a} ${b} + elif [ "$val" -gt 1000 ]; then + a=$(expr $val / 1000) + printf "%d Kb" ${a} + else + echo "${val} b" + fi +} + +scale_latency() { + local val=$1 + local a + local b + + a=$(expr $val / 100) + b=$(expr $val % 100) + printf "%d.%d ms" ${a} ${b} +} + +# +# Read the data rates for both directions +# +data_rates() { + local csg + local dru + local drd + local sdru + local sdrd + + csg=$(dsl_cmd g997csg 0 1) + drd=$(dsl_val "$csg" ActualDataRate) + + csg=$(dsl_cmd g997csg 0 0) + dru=$(dsl_val "$csg" ActualDataRate) + + [ -z "$drd" ] && drd=0 + [ -z "$dru" ] && dru=0 + + sdrd=$(scale $drd) + sdru=$(scale $dru) + + if [ "$action" = "lucistat" ]; then + echo "dsl.data_rate_down=$drd" + echo "dsl.data_rate_up=$dru" + echo "dsl.data_rate_down_s=\"$sdrd\"" + echo "dsl.data_rate_up_s=\"$sdru\"" + else + echo "Data Rate: Down: ${sdrd}/s / Up: ${sdru}/s" + fi +} + +# +# Chipset +# +chipset() { + local vig + local cs + local csv + + vig=$(dsl_cmd vig) + cs=$(dsl_val "$vig" DSL_ChipSetType) + csv=$(dsl_val "$vig" DSL_ChipSetHWVersion) + csfw=$(dsl_val "$vig" DSL_ChipSetFWVersion) + csapi=$(dsl_val "$vig" DSL_DriverVersionApi) + + if [ "$action" = "lucistat" ]; then + echo "dsl.chipset=\"${cs} ${csv}\"" + echo "dsl.firmware_version=\"${csfw}\"" + echo "dsl.api_version=\"${csapi}\"" + else + echo "Chipset: ${cs} ${csv}" + echo "Firmware Version: ${csfw}" + echo "API Version: ${csapi}" + fi +} + +# +# Vendor information +# +vendor() { + local lig + local vid + local svid + + lig=$(dsl_cmd g997lig 1) + vid=$(dsl_string "$lig" G994VendorID) + svid=$(dsl_string "$lig" SystemVendorID) + + if [ "$action" = "lucistat" ]; then + echo "dsl.atuc_vendor_id=\"${vid}\"" + echo "dsl.atuc_system_vendor_id=\"${svid}\"" + else + echo "ATU-C Vendor ID: ${vid}" + echo "ATU-C System Vendor ID: ${svid}" + fi +} + +# +# XTSE capabilities +# +xtse() { + local xtusesg + local xtse1 + local xtse2 + local xtse3 + local xtse4 + local xtse5 + local xtse6 + local xtse7 + local xtse8 + + local xtse_s="" + + local annex_s="" + local line_mode_s="" + local cmd="" + + xtusesg=$(dsl_cmd g997xtusesg) + xtse1=$(dsl_val "$xtusesg" XTSE1) + xtse2=$(dsl_val "$xtusesg" XTSE2) + xtse3=$(dsl_val "$xtusesg" XTSE3) + xtse4=$(dsl_val "$xtusesg" XTSE4) + xtse5=$(dsl_val "$xtusesg" XTSE5) + xtse6=$(dsl_val "$xtusesg" XTSE6) + xtse7=$(dsl_val "$xtusesg" XTSE7) + xtse8=$(dsl_val "$xtusesg" XTSE8) + + # Evaluate Annex (according to G.997.1, 7.3.1.1.1) + if [ $((xtse1 & 13)) != 0 \ + -o $((xtse2 & 1)) != 0 \ + -o $((xtse3 & 12)) != 0 \ + -o $((xtse4 & 3)) != 0 \ + -o $((xtse6 & 3)) != 0 \ + -o $((xtse8 & 1)) != 0 ]; then + annex_s=" A," + fi + + if [ $((xtse1 & 48)) != 0 \ + -o $((xtse2 & 2)) != 0 \ + -o $((xtse3 & 48)) != 0 \ + -o $((xtse6 & 12)) != 0 \ + -o $((xtse8 & 2)) != 0 ]; then + annex_s="$annex_s B," + fi + + if [ $((xtse1 & 194)) != 0 \ + -o $((xtse2 & 12)) != 0 \ + -o $((xtse8 & 4)) != 0 ]; then + annex_s="$annex_s C," + fi + + if [ $((xtse4 & 48)) != 0 \ + -o $((xtse5 & 3)) != 0 \ + -o $((xtse6 & 192)) != 0 ]; then + annex_s="$annex_s I," + fi + + if [ $((xtse4 & 192)) != 0 \ + -o $((xtse7 & 3)) != 0 ]; then + annex_s="$annex_s J," + fi + + if [ $((xtse5 & 60)) != 0 ]; then + annex_s="$annex_s L," + fi + + if [ $((xtse5 & 192)) != 0 \ + -o $((xtse7 & 12)) != 0 ]; then + annex_s="$annex_s M," + fi + + annex_s=`echo ${annex_s:1}` + annex_s=`echo ${annex_s%?}` + + # Evaluate Line Mode (according to G.997.1, 7.3.1.1.1) + + # Regional standard: ANSI T1.413 + if [ $((xtse1 & 1)) != 0 ]; then + line_mode_s=" T1.413," + fi + + # Regional standard: TS 101 388 + if [ $((xtse1 & 1)) != 0 ]; then + line_mode_s="$line_mode_s TS 101 388," + fi + + if [ $((xtse1 & 252)) != 0 ]; then + line_mode_s="$line_mode_s G.992.1 (ADSL)," + fi + + if [ $((xtse2 & 15)) != 0 ]; then + line_mode_s="$line_mode_s G.992.2 (ADSL lite)," + fi + + if [ $((xtse3 & 60)) != 0 \ + -o $((xtse4 & 240)) != 0 \ + -o $((xtse5 & 252)) != 0 ]; then + line_mode_s="$line_mode_s G.992.3 (ADSL2)," + fi + + if [ $((xtse4 & 3)) != 0 \ + -o $((xtse5 & 3)) != 0 ]; then + line_mode_s="$line_mode_s G.992.4 (ADSL2 lite)," + fi + + if [ $((xtse6 & 199)) != 0 \ + -o $((xtse7 & 15)) != 0 ]; then + line_mode_s="$line_mode_s G.992.5 (ADSL2+)," + fi + + if [ $((xtse8 & 7)) != 0 ]; then + line_mode_s="$line_mode_s G.993.2 (VDSL2)," + fi + + #!!! PROPRIETARY & INTERMEDIATE USE !!! + if [ $((xtse8 & 128)) != 0 ]; then + line_mode_s="$line_mode_s G.993.1 (VDSL)," + fi + + line_mode_s=`echo ${line_mode_s:1}` + line_mode_s=`echo ${line_mode_s%?}` + + xtse_s="${xtse1}, ${xtse2}, ${xtse3}, ${xtse4}, ${xtse5}, ${xtse6}, ${xtse7}, ${xtse8}" + + if [ "$action" = "lucistat" ]; then + echo "dsl.xtse1=${xtse1:-nil}" + echo "dsl.xtse2=${xtse2:-nil}" + echo "dsl.xtse3=${xtse3:-nil}" + echo "dsl.xtse4=${xtse4:-nil}" + echo "dsl.xtse5=${xtse5:-nil}" + echo "dsl.xtse6=${xtse6:-nil}" + echo "dsl.xtse7=${xtse7:-nil}" + echo "dsl.xtse8=${xtse8:-nil}" + echo "dsl.xtse_s=\"$xtse_s\"" + echo "dsl.annex_s=\"${annex_s}\"" + echo "dsl.line_mode_s=\"${line_mode_s}\"" + else + echo "XTSE Capabilities: ${xtse_s}" + echo "Annex: ${annex_s}" + echo "Line Mode: ${line_mode_s}" + fi +} + +# +# Power Management Mode +# +power_mode() { + local pmsg=$(dsl_cmd g997pmsg) + local pm=$(dsl_val "$pmsg" nPowerManagementStatus); + local s; + + case "$pm" in + "-1") s="Power management state is not available" ;; + "0") s="L0 - Synchronized" ;; + "1") s="L1 - Power Down Data transmission (G.992.2)" ;; + "2") s="L2 - Power Down Data transmission (G.992.3 and G.992.4)" ;; + "3") s="L3 - No power" ;; + *) s="unknown" ;; + esac + + if [ "$action" = "lucistat" ]; then + echo "dsl.power_mode_num=${pm:-nil}" + echo "dsl.power_mode_s=\"$s\"" + else + echo "Power Management Mode: $s" + fi +} + +# +# Latency type (interleave delay) +# +latency_delay() { + local csg + + local idu + local idu_s; + local sidu + + local idd + local idd_s; + local sidd + + csg=$(dsl_cmd g997csg 0 1) + idd=$(dsl_val "$csg" ActualInterleaveDelay) + + csg=$(dsl_cmd g997csg 0 0) + idu=$(dsl_val "$csg" ActualInterleaveDelay) + + [ -z "$idd" ] && idd=0 + [ -z "$idu" ] && idu=0 + + if [ "$idd" > 100 ]; then + idd_s="Interleave" + else + idd_s="Fast" + fi + + if [ "$idu" > 100 ]; then + idu_s="Interleave" + else + idu_s="Fast" + fi + + sidu=$(scale_latency $idu) + sidd=$(scale_latency $idd) + + if [ "$action" = "lucistat" ]; then + echo "dsl.latency_num_down=\"$sidu\"" + echo "dsl.latency_num_up=\"$sidd\"" + echo "dsl.latency_s_down=\"$idd_s\"" + echo "dsl.latency_s_up=\"$idu_s\"" + else + echo "Latency / Interleave Delay: Down: ${idd_s} (${sidd}) / Up: ${idu_s} (${sidu})" + fi +} + +# +# Errors +# +errors() { + local lsctg + local dpctg + local ccsg + local esf + local esn + local sesf + local sesn + local lossf + local lossn + local uasf + local uasn + + local crc_pf + local crc_pn + local crcp_pf + local crcp_pn + local hecf + local hecn + + local fecn + local fecf + + lsctg=$(dsl_cmd pmlsctg 1) + esf=$(dsl_val "$lsctg" nES) + sesf=$(dsl_val "$lsctg" nSES) + lossf=$(dsl_val "$lsctg" nLOSS) + uasf=$(dsl_val "$lsctg" nUAS) + + lsctg=$(dsl_cmd pmlsctg 0) + esn=$(dsl_val "$lsctg" nES) + sesn=$(dsl_val "$lsctg" nSES) + lossn=$(dsl_val "$lsctg" nLOSS) + uasn=$(dsl_val "$lsctg" nUAS) + + dpctg=$(dsl_cmd pmdpctg 0 1) + hecf=$(dsl_val "$dpctg" nHEC) + crc_pf=$(dsl_val "$dpctg" nCRC_P) + crcp_pf=$(dsl_val "$dpctg" nCRCP_P) + + dpctg=$(dsl_cmd pmdpctg 0 0) + hecn=$(dsl_val "$dpctg" nHEC) + crc_pn=$(dsl_val "$dpctg" nCRC_P) + crcp_pn=$(dsl_val "$dpctg" nCRCP_P) + + ccsg=$(dsl_cmd pmccsg 0 1 0) + fecf=$(dsl_val "$ccsg" nFEC) + + ccsg=$(dsl_cmd pmccsg 0 0 0) + fecn=$(dsl_val "$ccsg" nFEC) + + if [ "$action" = "lucistat" ]; then + echo "dsl.errors_fec_near=${fecn:-nil}" + echo "dsl.errors_fec_far=${fecf:-nil}" + echo "dsl.errors_es_near=${esn:-nil}" + echo "dsl.errors_es_far=${esf:-nil}" + echo "dsl.errors_ses_near=${sesn:-nil}" + echo "dsl.errors_ses_far=${sesf:-nil}" + echo "dsl.errors_loss_near=${lossn:-nil}" + echo "dsl.errors_loss_far=${lossf:-nil}" + echo "dsl.errors_uas_near=${uasn:-nil}" + echo "dsl.errors_uas_far=${uasf:-nil}" + echo "dsl.errors_hec_near=${hecn:-nil}" + echo "dsl.errors_hec_far=${hecf:-nil}" + echo "dsl.errors_crc_p_near=${crc_pn:-nil}" + echo "dsl.errors_crc_p_far=${crc_pf:-nil}" + echo "dsl.errors_crcp_p_near=${crcp_pn:-nil}" + echo "dsl.errors_crcp_p_far=${crcp_pf:-nil}" + else + echo "Forward Error Correction Seconds (FECS): Near: ${fecn} / Far: ${fecf}" + echo "Errored seconds (ES): Near: ${esn} / Far: ${esf}" + echo "Severely Errored Seconds (SES): Near: ${sesn} / Far: ${sesf}" + echo "Loss of Signal Seconds (LOSS): Near: ${lossn} / Far: ${lossf}" + echo "Unavailable Seconds (UAS): Near: ${uasn} / Far: ${uasf}" + echo "Header Error Code Errors (HEC): Near: ${hecn} / Far: ${hecf}" + echo "Non Pre-emtive CRC errors (CRC_P): Near: ${crc_pn} / Far: ${crc_pf}" + echo "Pre-emtive CRC errors (CRCP_P): Near: ${crcp_pn} / Far: ${crcp_pf}" + fi +} + +# +# Work out how long the line has been up +# +line_uptime() { + local ccsg + local et + local etr + local d + local h + local m + local s + local rc="" + + ccsg=$(dsl_cmd pmccsg 0 0 0) + et=$(dsl_val "$ccsg" nElapsedTime) + + [ -z "$et" ] && et=0 + + d=$(expr $et / 86400) + etr=$(expr $et % 86400) + h=$(expr $etr / 3600) + etr=$(expr $etr % 3600) + m=$(expr $etr / 60) + s=$(expr $etr % 60) + + + [ "${d}${h}${m}${s}" -ne 0 ] && rc="${s}s" + [ "${d}${h}${m}" -ne 0 ] && rc="${m}m ${rc}" + [ "${d}${h}" -ne 0 ] && rc="${h}h ${rc}" + [ "${d}" -ne 0 ] && rc="${d}d ${rc}" + + [ -z "$rc" ] && rc="down" + + + if [ "$action" = "lucistat" ]; then + echo "dsl.line_uptime=${et}" + echo "dsl.line_uptime_s=\"${rc}\"" + else + + echo "Line Uptime Seconds: ${et}" + echo "Line Uptime: ${rc}" + fi +} + +# +# Get noise and attenuation figures +# +line_data() { + local lsg + local latnu + local latnd + local satnu + local satnd + local snru + local snrd + local attndru + local attndrd + local sattndru + local sattndrd + local actatpu + local actatpd + + lsg=$(dsl_cmd g997lsg 1 1) + latnd=$(dsl_val "$lsg" LATN) + satnd=$(dsl_val "$lsg" SATN) + snrd=$(dsl_val "$lsg" SNR) + attndrd=$(dsl_val "$lsg" ATTNDR) + actatpd=$(dsl_val "$lsg" ACTATP) + + lsg=$(dsl_cmd g997lsg 0 1) + latnu=$(dsl_val "$lsg" LATN) + satnu=$(dsl_val "$lsg" SATN) + snru=$(dsl_val "$lsg" SNR) + attndru=$(dsl_val "$lsg" ATTNDR) + actatpu=$(dsl_val "$lsg" ACTATP) + + [ -z "$latnd" ] && latnd=0 + [ -z "$latnu" ] && latnu=0 + [ -z "$satnd" ] && satnd=0 + [ -z "$satnu" ] && satnu=0 + [ -z "$snrd" ] && snrd=0 + [ -z "$snru" ] && snru=0 + [ -z "$actatpd" ] && actatpd=0 + [ -z "$actatpu" ] && actatpu=0 + + latnd=$(dbt $latnd) + latnu=$(dbt $latnu) + satnd=$(dbt $satnd) + satnu=$(dbt $satnu) + snrd=$(dbt $snrd) + snru=$(dbt $snru) + actatpd=$(dbt $actatpd) + actatpu=$(dbt $actatpu) + + [ -z "$attndrd" ] && attndrd=0 + [ -z "$attndru" ] && attndru=0 + + sattndrd=$(scale $attndrd) + sattndru=$(scale $attndru) + + if [ "$action" = "lucistat" ]; then + echo "dsl.line_attenuation_down=$latnd" + echo "dsl.line_attenuation_up=$latnu" + echo "dsl.noise_margin_down=$snrd" + echo "dsl.noise_margin_up=$snru" + echo "dsl.signal_attenuation_down=$satnd" + echo "dsl.signal_attenuation_up=$satnu" + echo "dsl.actatp_down=$actatpd" + echo "dsl.actatp_up=$actatpu" + echo "dsl.max_data_rate_down=$attndrd" + echo "dsl.max_data_rate_up=$attndru" + echo "dsl.max_data_rate_down_s=\"$sattndrd\"" + echo "dsl.max_data_rate_up_s=\"$sattndru\"" + else + echo "Line Attenuation (LATN): Down: ${latnd}dB / Up: ${latnu}dB" + echo "Signal Attenuation (SATN): Down: ${satnd}dB / Up: ${satnu}dB" + echo "Noise Margin (SNR): Down: ${snrd}dB / Up: ${snru}dB" + echo "Aggregate Transmit Power(ACTATP): Down: ${actatpd}dB / Up: ${actatpu}dB" + echo "Max. Attainable Data Rate (ATTNDR): Down: ${sattndrd}/s / Up: ${sattndru}/s" + fi +} + +# +# Is the line up? Or what state is it in? +# +line_state() { + local lsg=$(dsl_cmd lsg) + local ls=$(dsl_val "$lsg" nLineState); + local s; + + case "$ls" in + "0x0") s="not initialized" ;; + "0x1") s="exception" ;; + "0x10") s="not updated" ;; + "0xff") s="idle request" ;; + "0x100") s="idle" ;; + "0x1ff") s="silent request" ;; + "0x200") s="silent" ;; + "0x300") s="handshake" ;; + "0x380") s="full_init" ;; + "0x400") s="discovery" ;; + "0x500") s="training" ;; + "0x600") s="analysis" ;; + "0x700") s="exchange" ;; + "0x800") s="showtime_no_sync" ;; + "0x801") s="showtime_tc_sync" ;; + "0x900") s="fastretrain" ;; + "0xa00") s="lowpower_l2" ;; + "0xb00") s="loopdiagnostic active" ;; + "0xb10") s="loopdiagnostic data exchange" ;; + "0xb20") s="loopdiagnostic data request" ;; + "0xc00") s="loopdiagnostic complete" ;; + "0x1000000") s="test" ;; + "0xd00") s="resync" ;; + "0x3c0") s="short init entry" ;; + "") s="not running daemon"; ls="0xfff" ;; + *) s="unknown" ;; + esac + + if [ "$action" = "lucistat" ]; then + echo "dsl.line_state_num=$ls" + echo "dsl.line_state_detail=\"$s\"" + if [ "$ls" = "0x801" ]; then + echo "dsl.line_state=\"UP\"" + else + echo "dsl.line_state=\"DOWN\"" + fi + else + if [ "$ls" = "0x801" ]; then + echo "Line State: UP [$ls: $s]" + else + echo "Line State: DOWN [$ls: $s]" + fi + fi +} + +status() { + vendor + chipset + xtse + line_state + errors + power_mode + latency_delay + data_rates + line_data + line_uptime +} + +lucistat() { + echo "local dsl={}" + status + echo "return dsl" +} diff --git a/target/linux/lantiq/base-files/lib/preinit/03_preinit_board.sh b/target/linux/lantiq/base-files/lib/preinit/03_preinit_board.sh new file mode 100755 index 0000000..6d4bd67 --- /dev/null +++ b/target/linux/lantiq/base-files/lib/preinit/03_preinit_board.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_lantiq() { + . /lib/functions/lantiq.sh + + lantiq_board_detect +} + +boot_hook_add preinit_main do_lantiq diff --git a/target/linux/lantiq/base-files/lib/preinit/05_set_preinit_iface_lantiq b/target/linux/lantiq/base-files/lib/preinit/05_set_preinit_iface_lantiq new file mode 100644 index 0000000..3d7fabf --- /dev/null +++ b/target/linux/lantiq/base-files/lib/preinit/05_set_preinit_iface_lantiq @@ -0,0 +1,18 @@ +#!/bin/sh + +. /lib/functions/lantiq.sh + +set_preinit_iface() { + + board=$(lantiq_board_name) + + case "$board" in + TDW8970) + ifname=eth0 + ;; + esac + +} + +boot_hook_add preinit_main set_preinit_iface + diff --git a/target/linux/lantiq/base-files/lib/upgrade/platform.sh b/target/linux/lantiq/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000..e876b11 --- /dev/null +++ b/target/linux/lantiq/base-files/lib/upgrade/platform.sh @@ -0,0 +1,47 @@ +. /lib/functions/lantiq.sh + +PART_NAME=firmware + +platform_check_image() { + [ "$#" -gt 1 ] && return 1 + local board=$(lantiq_board_name) + + case "$board" in + BTHOMEHUBV2B|BTHOMEHUBV3A|BTHOMEHUBV5A|P2812HNUF* ) + nand_do_platform_check $board $1 + return $?; + ;; + esac + + case "$(get_magic_word "$1")" in + # uImage + 2705) return 0;; + # tplink + 0200) return 0;; + *) + echo "Invalid image type" + return 1 + ;; + esac +} + +platform_pre_upgrade() { + local board=$(lantiq_board_name) + + case "$board" in + BTHOMEHUBV2B|BTHOMEHUBV3A|BTHOMEHUBV5A|P2812HNUF* ) + nand_do_upgrade $1 + ;; + esac +} + +# use default for platform_do_upgrade() + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/lantiq/base-files/sbin/dsl_notify.sh b/target/linux/lantiq/base-files/sbin/dsl_notify.sh new file mode 100755 index 0000000..b514e25 --- /dev/null +++ b/target/linux/lantiq/base-files/sbin/dsl_notify.sh @@ -0,0 +1,61 @@ +#!/bin/sh +# +# This script is called by dsl_cpe_control whenever there is a DSL event, +# we only actually care about the DSL_INTERFACE_STATUS events as these +# tell us the line has either come up or gone down. +# +# The rest of the code is basically the same at the atm hotplug code +# + +[ "$DSL_NOTIFICATION_TYPE" = "DSL_INTERFACE_STATUS" ] || exit 0 + +. /usr/share/libubox/jshn.sh +. /lib/functions.sh +. /lib/functions/leds.sh + +include /lib/network +scan_interfaces + +local default +config_load system +config_get default led_adsl default +if [ "$default" != 1 ]; then + case "$DSL_INTERFACE_STATUS" in + "HANDSHAKE") led_timer dsl 500 500;; + "TRAINING") led_timer dsl 200 200;; + "UP") led_on dsl;; + *) led_off dsl + esac +fi + +local interfaces=`ubus list network.interface.\* | cut -d"." -f3` +local ifc +for ifc in $interfaces; do + + local up + json_load "$(ifstatus $ifc)" + json_get_var up up + + local auto + config_get_bool auto "$ifc" auto 1 + + local proto + json_get_var proto proto + + if [ "$DSL_INTERFACE_STATUS" = "UP" ]; then + if [ "$proto" = "pppoa" ] && [ "$up" != 1 ] && [ "$auto" = 1 ]; then + ( sleep 1; ifup "$ifc" ) & + fi + else + if [ "$proto" = "pppoa" ] && [ "$up" = 1 ] && [ "$auto" = 1 ]; then + ( sleep 1; ifdown "$ifc" ) & + else + json_get_var autostart autostart + if [ "$proto" = "pppoa" ] && [ "$up" != 1 ] && [ "$autostart" = 1 ]; then + ( sleep 1; ifdown "$ifc" ) & + fi + fi + fi +done + + diff --git a/target/linux/lantiq/config-3.18 b/target/linux/lantiq/config-3.18 new file mode 100644 index 0000000..9824b37 --- /dev/null +++ b/target/linux/lantiq/config-3.18 @@ -0,0 +1,161 @@ +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CSRC_R4K=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_DT_EASY50712=y +CONFIG_EARLY_PRINTK=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_MM_LANTIQ=y +CONFIG_GPIO_STP_XWAY=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_MACH_CLKDEV=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_LANTIQ=y +CONFIG_LANTIQ_ETOP=y +# CONFIG_LANTIQ_PHY is not set +CONFIG_LANTIQ_WDT=y +# CONFIG_LANTIQ_XRX200 is not set +CONFIG_LEDS_GPIO=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_LANTIQ=y +CONFIG_MTD_M25P80=y +# CONFIG_MTD_NAND_XWAY is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_UIMAGE_SPLIT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DEVICE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +# CONFIG_PCIE_LANTIQ is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PERCPU_RWSEM=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_LANTIQ=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_XWAY=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PROC_DEVICETREE=y +CONFIG_PSB6970_PHY=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366_SMI=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_LANTIQ=y +# CONFIG_SOC_AMAZON_SE is not set +# CONFIG_SOC_FALCON is not set +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWCONFIG=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UIDGID_CONVERTED=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USE_OF=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/lantiq/config-4.1 b/target/linux/lantiq/config-4.1 new file mode 100644 index 0000000..a68ad16 --- /dev/null +++ b/target/linux/lantiq/config-4.1 @@ -0,0 +1,162 @@ +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_CEVT_R4K=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CSRC_R4K=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DTC=y +CONFIG_DT_EASY50712=y +CONFIG_EARLY_PRINTK=y +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_MM_LANTIQ=y +CONFIG_GPIO_STP_XWAY=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_MACH_CLKDEV=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_LANTIQ=y +CONFIG_LANTIQ_ETOP=y +# CONFIG_LANTIQ_PHY is not set +CONFIG_LANTIQ_WDT=y +# CONFIG_LANTIQ_XRX200 is not set +CONFIG_LEDS_GPIO=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_LANTIQ=y +CONFIG_MTD_M25P80=y +# CONFIG_MTD_NAND_XWAY is not set +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_UIMAGE_SPLIT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DEVICE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +# CONFIG_PCIE_LANTIQ is not set +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_LANTIQ=y +CONFIG_PERCPU_RWSEM=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_AMD is not set +CONFIG_PINCTRL_LANTIQ=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINCTRL_XWAY=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PROC_DEVICETREE=y +CONFIG_PSB6970_PHY=y +CONFIG_RTL8366RB_PHY=y +CONFIG_RTL8366_SMI=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_LANTIQ=y +# CONFIG_SOC_AMAZON_SE is not set +# CONFIG_SOC_FALCON is not set +CONFIG_SOC_TYPE_XWAY=y +CONFIG_SOC_XWAY=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWCONFIG=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UIDGID_CONVERTED=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USE_OF=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/lantiq/dts/ACMP252.dts b/target/linux/lantiq/dts/ACMP252.dts new file mode 100644 index 0000000..d7d5b32 --- /dev/null +++ b/target/linux/lantiq/dts/ACMP252.dts @@ -0,0 +1,96 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ACMP252 - AudioCodes MediaPack MP-252"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "uboot_env"; + reg = <0x20000 0x20000>; + }; + + partition@40000 { + label = "boardconfig"; + reg = <0x40000 0x60000>; + read-only; + }; + + partition@a0000 { + label = "firmware"; + reg = <0xa0000 0xf20000>; + }; + + partition@fc0000 { + label = "sysconfig"; + reg = <0xfc0000 0x40000>; + }; + + partition@0x1000000 { + label = "rootfs_data"; + reg = <0x1000000 0x1000000>; + }; + + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci { + lantiq,groups = "gnt1", "req1"; + lantiq,function = "pci"; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 3 0>; + }; + + etop@E180000 { + phy-mode = "rmii"; + }; + + pci@E105400 { + status = "okay"; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV4510PW.dts b/target/linux/lantiq/dts/ARV4510PW.dts new file mode 100644 index 0000000..4772495 --- /dev/null +++ b/target/linux/lantiq/dts/ARV4510PW.dts @@ -0,0 +1,211 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV4510PW - Wippies, Elisa"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + lantiq,noxip; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0xfa0000>; + }; + }; + }; + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu a23"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + exin { + lantiq,groups = "exin1", "exin2"; + lantiq,function = "exin"; + lantiq,output = <0>; + }; + pci_in { + lantiq,groups = "req1", "req2"; + lantiq,function = "pci"; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1", "gnt2"; + lantiq,function = "pci"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + buttons { + lantiq,pins = "io3", "io14"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + }; + }; + + gpios: stp@E100BB0 { + status = "okay"; + lantiq,groups = <0x7>; + }; + + etop@E180000 { + phy-mode = "rmii"; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + interrupt-map = < + 0x6000 0 0 1 &icu0 135 + 0x7800 0 0 1 &icu0 66 + 0x7800 0 0 2 &icu0 66 + 0x7800 0 0 3 &icu0 66 + >; + gpio-reset = <&gpio 21 0>; + req-mask = <0x7>; + }; + + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 14 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio 3 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpios 21 0>; + }; + power2 { + label = "power2"; + gpios = <&gpios 20 0>; + }; + lan1 { + label = "lan1"; + gpios = <&gpios 19 0>; + }; + lan2 { + label = "lan2"; + gpios = <&gpios 18 0>; + }; + lan3 { + label = "lan3"; + gpios = <&gpios 17 0>; + }; + lan4 { + label = "lan4"; + gpios = <&gpios 16 0>; + }; + wifi { + label = "wifi"; + gpios = <&gpios 15 0>; + }; + adsl { + label = "adsl"; + gpios = <&gpios 14 0>; + }; + internet { + label = "internet"; + gpios = <&gpios 13 0>; + }; + internet2 { + label = "internet2"; + gpios = <&gpios 12 0>; + }; + voip { + label = "voip"; + gpios = <&gpios 11 0>; + }; + phone { + label = "phone"; + gpios = <&gpios 10 0>; + }; + phone2 { + label = "phone2"; + gpios = <&gpios 9 0>; + }; + usb { + label = "usb"; + gpios = <&gpios 8 0>; + }; + usb2 { + label = "usb2"; + gpios = <&gpios 7 0>; + }; + usb3 { + label = "usb3"; + gpios = <&gpios 6 0>; + }; + unlabeled { + label = "unlabeled"; + gpios = <&gpios 5 0>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV4518PWR01.dts b/target/linux/lantiq/dts/ARV4518PWR01.dts new file mode 100644 index 0000000..f2a2e18 --- /dev/null +++ b/target/linux/lantiq/dts/ARV4518PWR01.dts @@ -0,0 +1,192 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV4518PWR01 - SMC7908A-ISP"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; /* 64 KB */ + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; /* 64 KB */ + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + partition@400000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x0>; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x3f0016 0x6>; + mac-increment = <2>; + }; + + ath5k_eep { + compatible = "ath5k,eeprom"; + reg = <0 0x3f0400 0x1000 + 0 0x3f0016 0x6>; + ath,mac-increment = <1>; + ath,eep-swap; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_in { + lantiq,groups = "req1", "req2"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1", "gnt2"; + lantiq,function = "pci"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 14 0>; + }; + + pci@E105400 { + status = "okay"; + lantiq,internal-clock; + gpio-reset = <&gpio 21 0>; + req-mask = <0xf>; + }; + + }; + +/* +#define ARV4518PW_SWITCH_RESET 13 +*/ + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 28 1>; + linux,code = <0xf7>; + }; + reset { + label = "reset"; + gpios = <&gpio 30 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 3 0>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 4 1>; + }; + online { + label = "online"; + gpios = <&gpio 5 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 6 1>; + }; + wps { + label = "wps"; + gpios = <&gpio 7 1>; + }; + dsl2 { + label = "dsl2"; + gpios = <&gpio 8 1>; + }; + usb { + label = "usb"; + gpios = <&gpio 19 1>; + }; + voice { + label = "voice"; + gpios = <&gpiomm 0 1>; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 1 1>; + }; + fxs2 { + label = "fxs2"; + gpios = <&gpiomm 2 1>; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 3 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV4518PWR01A.dts b/target/linux/lantiq/dts/ARV4518PWR01A.dts new file mode 100644 index 0000000..221e5a0 --- /dev/null +++ b/target/linux/lantiq/dts/ARV4518PWR01A.dts @@ -0,0 +1,192 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV4518PWR01A - SMC7908A-ISP, Airties WAV-221"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; /* 64 KB */ + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; /* 64 KB */ + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + partition@400000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x0>; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x3f0016 0x6>; + mac-increment = <2>; + }; + + ath5k_eep { + compatible = "ath5k,eeprom"; + reg = <0 0x3f0400 0x1000 + 0 0x3f0016 0x6>; + ath,mac-increment = <1>; + ath,eep-swap; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_in { + lantiq,groups = "req1", "req2"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1", "gnt2"; + lantiq,function = "pci"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 14 0>; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + gpio-reset = <&gpio 21 0>; + req-mask = <0xf>; + }; + + }; + +/* +#define ARV4518PW_SWITCH_RESET 13 +*/ + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 28 1>; + linux,code = <0xf7>; + }; + reset { + label = "reset"; + gpios = <&gpio 30 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 3 0>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 4 1>; + }; + online { + label = "online"; + gpios = <&gpio 5 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 6 1>; + }; + wps { + label = "wps"; + gpios = <&gpio 7 1>; + }; + dsl2 { + label = "dsl2"; + gpios = <&gpio 8 1>; + }; + usb { + label = "usb"; + gpios = <&gpio 19 1>; + }; + voice { + label = "voice"; + gpios = <&gpiomm 0 1>; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 1 1>; + }; + fxs2 { + label = "fxs2"; + gpios = <&gpiomm 2 1>; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 3 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV4519PW.dts b/target/linux/lantiq/dts/ARV4519PW.dts new file mode 100644 index 0000000..a0a0803 --- /dev/null +++ b/target/linux/lantiq/dts/ARV4519PW.dts @@ -0,0 +1,178 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV4519PW - Vodafone, Pirelli"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + partition@3f0000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x400>; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x3f0016 0x6>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 14 0>; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + gpio-reset = <&gpio 21 0>; + req-mask = <0xf>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 28 1>; + linux,code = <0xf7>; + }; + reset { + label = "reset"; + gpios = <&gpio 30 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "power"; + gpios = <&gpio 2 1>; + }; + power2 { + label = "power2"; + gpios = <&gpio 7 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 6 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 4 1>; + }; + online { + label = "online"; + gpios = <&gpio 5 1>; + }; + online2 { + label = "online2"; + gpios = <&gpio 8 1>; + }; + usb { + label = "usb"; + gpios = <&gpio 19 1>; + }; + voip { + label = "voip"; + gpios = <&gpiomm 0 1>; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 1 1>; + }; + fxs2 { + label = "fxs2"; + gpios = <&gpiomm 2 1>; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 3 1>; + }; + wps { + label = "wps"; + gpios = <&gpiomm 5 1>; + }; + wps2 { + label = "wps2"; + gpios = <&gpiomm 4 1>; + }; + wps3 { + label = "wps3"; + gpios = <&gpiomm 6 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV4520PW.dts b/target/linux/lantiq/dts/ARV4520PW.dts new file mode 100644 index 0000000..8a5b797 --- /dev/null +++ b/target/linux/lantiq/dts/ARV4520PW.dts @@ -0,0 +1,200 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV4520PW - Easybox 800, WAV-281"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0 + &gpiomm 7 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x20000>; + read-only; + }; + + partition@20000 { + label = "uboot_env"; + reg = <0x20000 0x10000>; + read-only; + }; + + partition@30000 { + label = "firmware"; + reg = <0x30000 0x3c0000>; + }; + + partition@7f0000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x3f0016 0x6>; + mac-increment = <2>; + }; + + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x400>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + }; + + etop@E180000 { + phy-mode = "rmii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 28 0>; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + gpio-reset = <&gpio 21 0>; + }; + + }; + +// gpiomm 10 - switch + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "wps"; + gpios = <&gpio 29 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio 30 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "power"; + gpios = <&gpio 3 1>; + }; + adsl { + label = "adsl"; + gpios = <&gpio 4 1>; + }; + internet { + label = "internet"; + gpios = <&gpio 5 1>; + }; + power2 { + label = "power2"; + gpios = <&gpio 6 1>; + }; + wps { + label = "wps"; + gpios = <&gpio 7 1>; + }; + wps2 { + label = "wps2"; + gpios = <&gpio 9 1>; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 0 1>; + }; + fxs2 { + label = "fxs2"; + gpios = <&gpiomm 1 1>; + }; + isdn { + label = "isdn"; + gpios = <&gpiomm 2 1>; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 3 1>; + }; + voice { + label = "voice"; + gpios = <&gpiomm 4 1>; + }; + usb { + label = "usb"; + gpios = <&gpiomm 5 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpiomm 6 1>; + }; + internet2 { + label = "internet2"; + gpios = <&gpiomm 9 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV4525PW.dts b/target/linux/lantiq/dts/ARV4525PW.dts new file mode 100644 index 0000000..3c420e7 --- /dev/null +++ b/target/linux/lantiq/dts/ARV4525PW.dts @@ -0,0 +1,153 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV4525PW - Speedport W501V Typ A"; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + partition@400000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x3f0016 0x6>; + mac-increment = <2>; + }; + + ath5k_eep { + compatible = "ath5k,eeprom"; + reg = <0 0x3f0400 0x1000>; + ath,mac-offset = <0>; + ath,eep-swap; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + relay { + lantiq,pins = "io31"; + lantiq,output = <1>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + pci@E105400 { + status = "okay"; + gpio-reset = <&gpio 21 0>; + }; + + }; + +/* +#define ARV4525PW_PHYRESET 13 +#define ARV4525PW_RELAY 31 +*/ + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 29 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio 30 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + fxo { + label = "fxo"; + gpios = <&gpio 4 1>; + }; + fxs { + label = "fxs"; + gpios = <&gpio 5 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 6 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 8 1>; + }; + online { + /*label = "online"; - we dont have a power led, lets use this one */ + label = "power"; + gpios = <&gpio 9 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV452CQW.dts b/target/linux/lantiq/dts/ARV452CQW.dts new file mode 100644 index 0000000..fd7759e --- /dev/null +++ b/target/linux/lantiq/dts/ARV452CQW.dts @@ -0,0 +1,219 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV452CQW - Arcor 801"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0 + &gpiomm 7 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + partition@3f0000 { + label = "boardconfig"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x3f0016 0x6>; + mac-increment = <2>; + }; + + ath5k_eep { + compatible = "ath5k,eeprom"; + reg = <0 0x3f0400 0x1000>; + ath,mac-offset = <0>; + ath,eep-swap; + }; + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10>; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x77f>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + leds { + lantiq,pins = "io3", "io5", "io6", "io7", "io9"; + lantiq,output = <1>; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 28 0>; + }; + + etop@E180000 { + phy-mode = "rmii"; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + gpio-reset = <&gpio 21 0>; + }; + + }; + +/* +#define ARV452CPW_SWITCH_RESET 110 +*/ + gpio-keys-polled { + compatible = "gpio-keys-polled1"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 11 1>; + linux,code = <0x101>; + }; + restart { + label = "restart"; + gpios = <&gpio 12 1>; + linux,code = <0x110>; + }; + reset { + label = "reset"; + gpios = <&gpio 28 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power0 { + label = "power0"; + gpios = <&gpio 3 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 4 1>; + }; + isdn { + label = "isdn"; + gpios = <&gpio 5 1>; + }; + power1 { + label = "power1"; + gpios = <&gpio 6 1>; + }; + wps { + label = "wps"; + gpios = <&gpio 7 1>; + }; + wps1 { + label = "wps1"; + gpios = <&gpio 9 1>; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 0 1>; + }; + fxs2 { + label = "fxs2"; + gpios = <&gpiomm 1 1>; + }; + wps2 { + label = "wps2"; + gpios = <&gpiomm 2 1>; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 3 1>; + }; + voice { + label = "voice"; + gpios = <&gpiomm 4 1>; + }; + usb { + label = "usb"; + gpios = <&gpiomm 5 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpiomm 6 1>; + }; + dsl2 { + label = "dsl2"; + gpios = <&gpiomm 8 1>; + }; + dsl3 { + label = "dsl3"; + gpios = <&gpiomm 9 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV7510PW22.dts b/target/linux/lantiq/dts/ARV7510PW22.dts new file mode 100644 index 0000000..24c396d --- /dev/null +++ b/target/linux/lantiq/dts/ARV7510PW22.dts @@ -0,0 +1,179 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV7510PW22 - Astoria Networks"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 9 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0xf80000>; + }; + + partition@fe0000 { + label = "board_config"; + reg = <0xfe0000 0x20000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0xfe0016 0x6>; + mac-increment = <2>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_in { + lantiq,groups = "req1", "req2"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + pins_out { + lantiq,pins = "io2", "io4", "io8", "io9", "io10", "io15", "io20"; + lantiq,output = <1>; + }; + pins_in { + lantiq,pins = "io11", "io12", "io28"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 8 0>; + }; + + etop@E180000 { + phy-mode = "mii"; + /* Switch reset 19 */ + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + interrupt-map = < + 0x7000 0 0 1 &icu0 30 + 0x7800 0 0 1 &icu0 135 + 0x7800 0 0 2 &icu0 135 + 0x7800 0 0 3 &icu0 135 + >; + gpio-reset = <&gpio 21 0>; + req-mask = <0x3>; + }; + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT2860.eeprom"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 11 1>; + linux,code = <0xf7>; + }; + restart { + label = "restart"; + gpios = <&gpio 12 1>; + linux,code = <0x100>; + }; + reset { + label = "reset"; + gpios = <&gpio 28 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 2 1>; + }; + internet { + label = "internet"; + gpios = <&gpio 4 1>; + }; + wlan { + label = "wlan"; + gpios = <&gpio 10 1>; + }; + 3g { + label = "3g"; + gpios = <&gpio 15 1>; + }; + message { + label = "message"; + gpios = <&gpio 20 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV7518PW.dts b/target/linux/lantiq/dts/ARV7518PW.dts new file mode 100644 index 0000000..c6f4759 --- /dev/null +++ b/target/linux/lantiq/dts/ARV7518PW.dts @@ -0,0 +1,218 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV7518PW - Astoria Networks"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7d0000>; + }; + + partition@400000 { + label = "boardconfig"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; + + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x0>; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x7f0016 0x6>; + mac-increment = <2>; + }; + + ath9k_eep { + compatible = "ath9k,eeprom"; + reg = <0 0x7f0400 0x1000 + 0 0x7f0016 0x6>; + ath,mac-increment = <1>; + ath,pci-slot = <14>; + ath,eep-endian; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + leds { + lantiq,pins = "io2", "io4", "io5", "io6", "io7", "io8", "io19"; + lantiq,output = <1>; + }; + keys { + lantiq,pins = "io28", "io30"; + lantiq,output = <0>; + lantiq,pull = <2>; + lantiq,open-drain = <1>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 14 0>; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + gpio-reset = <&gpio 21 0>; + req-mask = <0xf>; + }; + + }; + +/* +#define SWITCH_RESET 13 +*/ + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 28 1>; + linux,code = <0xf7>; + }; + reset { + label = "reset"; + gpios = <&gpio 30 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 2 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 4 1>; + }; + online { + label = "online"; + gpios = <&gpio 5 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 6 1>; + }; + power2 { + label = "power2"; + gpios = <&gpio 7 1>; + }; + online2 { + label = "online2"; + gpios = <&gpio 8 1>; + }; + usb { + label = "usb"; + gpios = <&gpio 19 1>; + }; + voice { + label = "voice"; + gpios = <&gpiomm 0 1>; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 1 1>; + }; + fxs2 { + label = "fxs2"; + gpios = <&gpiomm 2 1>; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 3 1>; + }; + wps { + label = "wps"; + gpios = <&gpiomm 4 1>; + }; + wps2 { + label = "wps2"; + gpios = <&gpiomm 5 1>; + }; + wps3 { + label = "wps3"; + gpios = <&gpiomm 6 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV7519PW.dts b/target/linux/lantiq/dts/ARV7519PW.dts new file mode 100644 index 0000000..1478192 --- /dev/null +++ b/target/linux/lantiq/dts/ARV7519PW.dts @@ -0,0 +1,213 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV7519PW - Astoria Networks"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0xf80000>; + }; + + partition@fe0000 { + label = "board_config"; + reg = <0xfe0000 0x20000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0xfe0016 0x6>; + mac-increment = <2>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + switch_rst { + lantiq,pins = "io19"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + /* warning: passive port + only works with active devices */ + ifxhcd@E101000 { + status = "okay"; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + gpio-reset = <&gpio 21 0>; + req-mask = <0xf>; + }; + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT2860.eeprom"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 11 1>; + linux,code = <0xf7>; + }; + reset { + label = "reset"; + gpios = <&gpio 28 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 2 1>; + default-state = "off"; + }; + power2 { + label = "power2"; + gpios = <&gpio 14 1>; + }; + online { + label = "online"; + gpios = <&gpio 3 1>; + }; + online2 { + label = "online2"; + gpios = <&gpio 30 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 12 1>; + }; + wifi2 { + label = "wifi2"; + gpios = <&gpio 10 1>; + }; + wifi3 { + label = "wifi3"; + gpios = <&gpio 6 1>; + }; + voice { + label = "voice"; + gpios = <&gpio 31 1>; + }; + wps { + label = "wps"; + gpios = <&gpio 15 1>; + }; + wps2 { + label = "wps2"; + gpios = <&gpio 7 1>; + }; + wps3 { + label = "wps3"; + gpios = <&gpio 23 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 4 1>; + }; + lan { + label = "lan"; + gpios = <&gpio 1 1>; + }; + tv { + label = "tv"; + gpios = <&gpio 20 1>; + }; + upgrade { + label = "upgrade"; + gpios = <&gpio 29 1>; + }; + }; + + /* is there another way to "reserve" the GPIO? */ + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + switch { + gpio-export,name = "switch"; + gpio-export,output = <1>; + gpios = <&gpio 19 0>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV7519RW22.dts b/target/linux/lantiq/dts/ARV7519RW22.dts new file mode 100644 index 0000000..d925f86 --- /dev/null +++ b/target/linux/lantiq/dts/ARV7519RW22.dts @@ -0,0 +1,235 @@ +/dts-v1/; + +/include/ "vr9.dtsi" + +/ { + model = "ARV7519RW22 - Astoria Networks ARV7519RW22-A-LT"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x8000000>; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x60000>; + read-only; + }; + + partition@60000 { + label = "uboot-env"; + reg = <0x60000 0x20000>; + read-only; + }; + + partition@80000 { + label = "firmware"; + reg = <0x80000 0x1e00000>; + }; + + partition@1e80000 { + label = "dsl_fw"; + reg = <0x1e80000 0x100000>; + }; + + boardconfig: partition@1f80000 { + label = "boardconfig"; + reg = <0x1f80000 0x80000>; + read-only; + }; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + pcie-rst { + lantiq,pins = "io21"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 /* pmac */ + >; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&boardconfig 0x16>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "mii"; + phy-handle = <&phy14>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "mii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <3>; + phy-mode = "mii"; + phy-handle = <&phy12>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy12: ethernet-phy@12 { + reg = <0x12>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy14: ethernet-phy@14 { + reg = <0x14>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 32 0>; + }; + + ifxhcd@E106000 { + status = "okay"; + gpios = <&gpio 32 0>; + }; + + pcie@d900000 { + status = "disabled"; + compatible = "lantiq,pcie-xway"; + }; + + pci@E105400 { + status = "disabled"; + compatible = "lantiq,pci-xway"; + }; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware1 = "lantiq/vr9_phy22f_a1x.bin"; /*VR9 1.1*/ + firmware2 = "lantiq/vr9_phy22f_a2x.bin"; /*VR9 1.2*/ + phys = [ 00 01 ]; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 20 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio 22 1>; + linux,code = <0x198>; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 45 1>; + linux,code = <0xf7>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + lan_green { + label = "lan"; + gpios = <&gpio 2 1>; + }; + internet_red { + label = "internet_red"; + gpios = <&gpio 10 1>; + }; + power_green { + label = "power"; + gpios = <&gpio 14 1>; + default-state = "on"; + }; + alarm_blue { + label = "alarm"; + gpios = <&gpio 15 1>; + }; + internet_orange { + label = "internet_orange"; + gpios = <&gpio 19 1>; + }; + internet_green { + label = "internet_green"; + gpios = <&gpio 28 1>; + }; + voice_green { + label = "voice"; + gpios = <&gpio 29 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV7525PW.dts b/target/linux/lantiq/dts/ARV7525PW.dts new file mode 100644 index 0000000..57aa59c --- /dev/null +++ b/target/linux/lantiq/dts/ARV7525PW.dts @@ -0,0 +1,142 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV7525PW - Speedport W303V Typ A"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + partition@400000 { + label = "board_config"; + reg = <0x3f0000 0x10000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x3f0016 0x6>; + mac-increment = <2>; + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT2860.eeprom"; + reg = <0 0x3f0410 0x110>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci { + lantiq,groups = "gnt1", "req1"; + lantiq,function = "pci"; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + pci@E105400 { + status = "okay"; + interrupt-map = <0x7000 0 0 1 &icu0 135 1>; + req-mask = <0x1>; + }; + + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 29 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio 30 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 3 1>; + }; + power1 { + label = "power1"; + gpios = <&gpio 4 1>; + }; + online { + label = "online"; + gpios = <&gpio 5 1>; + }; + voice { + label = "voice"; + gpios = <&gpio 6 1>; + }; + voice2 { + label = "voice2"; + gpios = <&gpio 8 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 9 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV752DPW.dts b/target/linux/lantiq/dts/ARV752DPW.dts new file mode 100644 index 0000000..fe478e1 --- /dev/null +++ b/target/linux/lantiq/dts/ARV752DPW.dts @@ -0,0 +1,219 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV752DPW - Arcor 802"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpiomm 1 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7d0000>; + }; + + partition@7f0000 { + label = "board_config"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x7f0016 0x6>; + mac-increment = <2>; + }; + + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x3>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_in { + lantiq,groups = "req2", "req1"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + leds { + lantiq,pins = "io3", "io5", "io6", "io8"; + lantiq,output = <1>; + lantiq,pull = <0>; + }; + keys { + lantiq,pins = "io11", "io12", "io13", "io28"; + lantiq,output = <0>; + lantiq,pull = <2>; + lantiq,open-drain = <1>; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpiomm 0 0>; + }; + + etop@E180000 { + phy-mode = "rmii"; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + gpio-reset = <&gpio 21 0>; + interrupt-map = <0x7000 0 0 1 &icu0 135>; + req-mask = <0x3>; + }; + + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT2860.eeprom"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + /* wps { + label = "wps"; + gpios = <&gpio 11 1>; + linux,code = <0x211>; + }; */ + restart { + label = "restart"; + gpios = <&gpio 12 1>; + linux,code = <0x110>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 13 1>; + linux,code = <0x111>; + }; + reset { + label = "reset"; + gpios = <&gpio 28 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 3 1>; + }; + message { + label = "message"; + gpios = <&gpio 5 1>; + }; + power1 { + label = "power1"; + gpios = <&gpio 6 1>; + }; + voice1 { + label = "voice1"; + gpios = <&gpio 8 1>; + }; + microphone { + /* use this led as te usb led */ + label = "usb"; + gpios = <&gpiomm 3 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpiomm 4 1>; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 5 1>; + }; + fx2 { + label = "fxs2"; + gpios = <&gpiomm 6 1>; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 7 1>; + }; + internet { + label = "internet"; + gpios = <&gpiomm 8 1>; + }; + voice2 { + label = "voice2"; + gpios = <&gpiomm 9 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV752DPW22.dts b/target/linux/lantiq/dts/ARV752DPW22.dts new file mode 100644 index 0000000..ec4a3ab --- /dev/null +++ b/target/linux/lantiq/dts/ARV752DPW22.dts @@ -0,0 +1,253 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV752DPW22 - Arcor 803"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpiomm 1 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x30000>; + read-only; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x40000 0x7b0000>; + }; + + partition@7f0000 { + label = "board_config"; + reg = <0x7f0000 0x10000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x7f0016 0x6>; + mac-increment = <2>; + }; + + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <3>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ebu { + lantiq,groups = "ebu cs1"; + lantiq,function = "ebu"; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,open-drain = <1>; + lantiq,output = <1>; + }; + leds { + lantiq,pins = "io3", "io5", "io6", "io8"; + lantiq,open-drain = <1>; + lantiq,output = <1>; + }; + buttons { + lantiq,pins = "io11", "io12", "io13", "io28"; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpiomm 0 0>; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + pci@E105400 { + status = "okay"; + lantiq,external-clock; + interrupt-map = < + 0x7000 0 0 1 &icu0 30 + 0x7800 0 0 1 &icu0 135 + 0x7800 0 0 2 &icu0 135 + 0x7800 0 0 3 &icu0 135 + >; + gpio-reset = <&gpio 21 0>; + req-mask = <0x3>; + }; + + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT2860.eeprom"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 11 1>; + linux,code = <0x211>; + }; + restart { + label = "restart"; + gpios = <&gpio 12 1>; + linux,code = <0x110>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 13 1>; + linux,code = <0x111>; + }; + reset { + label = "reset"; + gpios = <&gpio 28 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 3 1>; + default-state = "on"; + }; + message { + label = "message"; + gpios = <&gpio 5 1>; + default-state = "on"; + }; + power1 { + label = "power1"; + gpios = <&gpio 6 1>; + default-state = "on"; + }; + voice1 { + label = "voice1"; + gpios = <&gpio 8 1>; + default-state = "on"; + }; + microphone { + label = "microphone"; + gpios = <&gpiomm 3 1>; + default-state = "on"; + }; + wifi { + label = "wifi_rt"; + gpios = <&gpiomm 4 1>; + default-state = "on"; + }; + fxs1 { + label = "fxs1"; + gpios = <&gpiomm 5 1>; + default-state = "on"; + }; + fxs2 { + label = "fxs2"; + gpios = <&gpiomm 6 1>; + default-state = "on"; + }; + fxo { + label = "fxo"; + gpios = <&gpiomm 7 1>; + default-state = "on"; + }; + dsl { + label = "dsl"; + gpios = <&gpiomm 8 1>; + default-state = "on"; + }; + voice2 { + label = "voice2"; + gpios = <&gpiomm 9 1>; + default-state = "on"; + }; + eth1 { + label = "eth1"; + gpios = <&gpiomm 11 1>; + default-state = "on"; + }; + eth2 { + label = "eth2"; + gpios = <&gpiomm 12 1>; + default-state = "on"; + }; + eth3 { + label = "eth3"; + gpios = <&gpiomm 13 1>; + default-state = "on"; + }; + eth4 { + label = "eth4"; + gpios = <&gpiomm 14 1>; + default-state = "on"; + }; + }; +}; diff --git a/target/linux/lantiq/dts/ARV8539PW22.dts b/target/linux/lantiq/dts/ARV8539PW22.dts new file mode 100644 index 0000000..acca47f --- /dev/null +++ b/target/linux/lantiq/dts/ARV8539PW22.dts @@ -0,0 +1,162 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "ARV8539PW22 - Speedport W 504V Typ A"; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x30000>; /* 192 KiB */ + read-only; + }; + + partition@30000 { + label = "uboot"; + reg = <0x30000 0x10000>; /* 64 KiB */ + read-only; + }; + + partition@40000 { + label = "firmware"; + reg = <0x40000 0x7B0000>; /* 7872 KiB */ + }; + + partition@7F0000 { + label = "art"; + reg = <0x7F0000 0x10000>; /* 64 KiB*/ + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x7f0016 0x6>; + mac-increment = <2>; + }; + + ath9k_eep { + compatible = "ath9k,eeprom"; + reg = <0 0x7f0400 0x1000 + 0 0x7f0016 0x6>; + ath,mac-increment = <1>; + ath,pci-slot = <14>; + ath,eep-endian; + ath,arv-ath9k-fix; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + lantiq,output = <0>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <2>; + lantiq,output = <1>; + }; + relay { + lantiq,pins = "io31"; + lantiq,output = <1>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + }; + + pci@E105400 { + status = "okay"; + gpio-reset = <&gpio 21 0>; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 14 0>; + lantiq,portmask = <0x3>; + }; + + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + wlan { + label = "wlan"; + gpios = <&gpio 29 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio 30 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power-green { + label = "power"; + gpios = <&gpio 24 1>; + }; + power-red { + label = "soc:red:power"; + gpios = <&gpio 4 1>; + }; + + dsl-green { + label = "soc:green:dsl"; + gpios = <&gpio 5 1>; + }; + + online-green { + label = "soc:green:online"; + gpios = <&gpio 6 1>; + }; + + wireless-green { + label = "soc:green:wireless"; + gpios = <&gpio 8 1>; + }; + }; +}; + diff --git a/target/linux/lantiq/dts/BTHOMEHUBV2B.dts b/target/linux/lantiq/dts/BTHOMEHUBV2B.dts new file mode 100644 index 0000000..9b3180c --- /dev/null +++ b/target/linux/lantiq/dts/BTHOMEHUBV2B.dts @@ -0,0 +1,280 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "BTHOMEHUBV2B - BT Home Hub 2B"; /* SoC: Lantiq Danube-S PSB 50712 @ 333MHz V1.3/1.5 */ + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { /* RAM: Samsung K4H511638F-LC 64MB */ + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + + nor-boot@0 { /* NOR Flash: Spansion S29AL004D 512KB */ + compatible = "lantiq,nor"; /* "AMD AM29LV400BB" compatible on 3.3.8 */ + lantiq,cs = <0>; + bank-width = <2>; + reg = <0 0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; /* 256KB */ + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x10000>; /* 64KB */ + }; + + partition@50000 { + label = "rg_conf_1"; + reg = <0x50000 0x10000>; + }; + + partition@60000 { + label = "rg_conf_2"; + reg = <0x60000 0x10000>; + }; + + partition@70000 { + label = "rg_conf_factory"; + reg = <0x70000 0x10000>; + }; + }; + + nand-parts@0 { /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */ + compatible = "gen_nand", "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <1 0x0 0x2000000 >; + #address-cells = <1>; + #size-cells = <1>; + req-mask = <0x1>; /* PCI request lines to mask during NAND access */ + + ath9k_cal: partition@0 { + label = "art"; /* Atheros 9160 wifi b/g/n radio EEPROM */ + reg = <0x00000 0x4000>; + read-only; + }; + + partition@4000 { + label = "kernel"; + reg = <0x4000 0x200000>; + }; + + partition@164000 { + label = "ubi"; + reg = <0x204000 0x1DFC000>; + }; + + }; + + + ath9k_eep { + compatible = "ath9k,eeprom"; + ath,eep-flash = <&ath9k_cal 0x0000>; + ath,mac-increment = <1>; + ath,pci-slot = <14>; + ath,eep-endian; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xway"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + nand_out { + lantiq,groups = "nand cle", "nand ale"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + nand_cs1 { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + }; + + btn_in { + lantiq,pins = "io2", "io15", "io22"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + }; + }; + + etop@E180000 { + compatible = "lantiq,etop-xway"; + reg = <0xE180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <73 78>; + phy-mode = "rmii"; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + ifxhcd@E101000 { + status = "okay"; + }; + + stp0: stp@E100BB0 { + status = "okay"; + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xE100BB0 0x40>; + + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + }; + + pci@E105400 { + status = "okay"; + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + gpio-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 2 1>; + linux,code = <0x198>; + }; + findhandset { + label = "findhandset"; + gpios = <&gpio 15 1>; + linux,code = <0x101>; + }; + wps { + label = "wps"; + gpios = <&gpio 22 1>; + linux,code = <0x211>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + upgrading-orange { + label = "soc:orange:upgrading"; + gpios = <&stp0 5 0>; + }; + + phone-orange { + label = "soc:orange:phone"; + gpios = <&stp0 6 0>; + }; + phone-blue { + label = "soc:blue:phone"; + gpios = <&stp0 7 0>; + }; + + wireless-orange { + label = "soc:orange:wireless"; + gpios = <&stp0 8 0>; + }; + wireless-blue { + label = "soc:blue:wireless"; + gpios = <&stp0 9 0>; + }; + + broadband-red { + label = "soc:red:broadband"; + gpios = <&stp0 10 0>; + }; + broadband-orange { + label = "soc:orange:broadband"; + gpios = <&stp0 11 0>; + }; + broadband-blue { + label = "soc:blue:broadband"; + gpios = <&stp0 12 0>; + }; + + power-red { + label = "soc:red:power"; + gpios = <&stp0 13 0>; + }; + power-orange { + label = "soc:orange:power"; + gpios = <&stp0 14 0>; + }; + power-blue { + label = "soc:blue:power"; + gpios = <&stp0 15 0>; + }; + }; + +}; + diff --git a/target/linux/lantiq/dts/BTHOMEHUBV3A.dts b/target/linux/lantiq/dts/BTHOMEHUBV3A.dts new file mode 100644 index 0000000..1ae9840 --- /dev/null +++ b/target/linux/lantiq/dts/BTHOMEHUBV3A.dts @@ -0,0 +1,210 @@ +/dts-v1/; + +/include/ "ar9.dtsi" + +/ { + model = "BTHOMEHUBV3A - BT Home Hub 3A"; /* SoC: Lantiq ar9 @ 333MHz */ + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { /* RAM: Samsung K4H511638F-LC 64MB */ + reg = <0x0 0x4000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpio 31 0>; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + + nand-parts@0 { /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */ + compatible = "gen_nand", "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <1 0x0 0x2000000 >; + #address-cells = <1>; + #size-cells = <1>; + req-mask = <0x1>; /* PCI request lines to mask during NAND access */ + + partition@0 { + label = "preboot"; + reg = <0x00000 0x8000>; + read-only; + }; + partition@8000 { + label = "u-boot"; + reg = <0x8000 0x05c000>; + read-only; + }; + partition@64000 { + label = "uboot-config"; + reg = <0x64000 0x004000>; + read-only; + }; + ath9k_cal: partition@68000 { + label = "art-copy"; + reg = <0x68000 0x004000>; + read-only; + }; + partition@6c000 { + label = "kernel"; + reg = <0x6c000 0x200000>; + }; + partition@26c000 { + label = "ubi"; + reg = <0x26c000 0x1d94000>; + }; + }; + + ath9k_eep { + compatible = "ath9k,eeprom"; + ath,eep-flash = <&ath9k_cal 0x0000>; + ath,mac-offset = <0x10c>; + ath,pci-slot = <14>; + ath,eep-endian; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + nand_out { + lantiq,groups = "nand cle", "nand ale"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + nand_cs1 { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + + pci_in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + pci_out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + }; + }; + }; + + etop@E180000 { + phy-mode = "rgmii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 33 0>; + }; + + pci@E105400 { + status = "okay"; + gpio-reset = <&gpio 21 0>; + }; + + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 54 1>; + linux,code = <0x198>; + }; + restart { + label = "restart"; + gpios = <&gpio 52 1>; + linux,code = <0x198>; + }; + wps { + label = "wps"; + gpios = <&gpio 53 1>; + linux,code = <0x211>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + wireless-red { + label = "soc:red:wireless"; + gpios = <&gpio 2 1>; + }; + wireless-orange { + label = "soc:orange:wireless"; + gpios = <&gpio 6 1>; + }; + wireless-blue { + label = "soc:blue:wireless"; + gpios = <&gpio 9 1>; + }; + + broadband-red { + label = "soc:red:broadband"; + gpios = <&gpio 11 1>; + }; + broadband-orange { + label = "soc:orange:broadband"; + gpios = <&gpio 0 1>; + }; + broadband-blue { + label = "soc:blue:broadband"; + gpios = <&gpio 12 1>; + }; + + power-red { + label = "soc:red:power"; + gpios = <&gpio 14 1>; + }; + power-orange { + label = "soc:orange:power"; + gpios = <&gpio 5 1>; + }; + power-blue { + label = "soc:blue:power"; + gpios = <&gpio 1 1>; + }; + }; + +}; + diff --git a/target/linux/lantiq/dts/BTHOMEHUBV5A.dts b/target/linux/lantiq/dts/BTHOMEHUBV5A.dts new file mode 100644 index 0000000..e8cdbbf --- /dev/null +++ b/target/linux/lantiq/dts/BTHOMEHUBV5A.dts @@ -0,0 +1,287 @@ +/dts-v1/; + +/include/ "vr9.dtsi" + +/ { + model = "BTHOMEHUBV5A - BT Home Hub 5A"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x8000000>; + }; + + fpi@10000000 { + localbus@0 { + nand-parts@0 { + compatible = "gen_nand", "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x40000>; + read-only; + }; + partition@40000 { + label = "uboot-env"; + reg = <0x40000 0x40000>; + }; + caldata: partition@80000 { + label = "caldata"; + reg = <0x80000 0x20000>; + read-only; + }; + partition@a0000 { + label = "kernel"; + reg = <0xa0000 0x200000>; + }; + partition@2a0000 { + label = "ubi"; + reg = <0x2a0000 0x7d60000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + interrupt-parent = <&icu0>; + interrupts = <166 135 66 40 41 42 38>; + + state_default: pinmux { + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain; + }; + pcie_rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + lantiq,open-drain; + }; + usb_vbus { + lantiq,pins = "io33"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + nand_out { + lantiq,groups = "nand cle", "nand ale"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + nand_cs1 { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 >; /* pmac */ + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&caldata 0x110c>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + }; + + wan: interface@1 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + mtd-mac-address = <&caldata 0x110c>; + mtd-mac-address-increment = <4>; + lantiq,wan; + + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 33 0>; + }; + + pci@E105400 { + status = "okay"; + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + gpio-reset = <&gpio 21 0>; + }; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware1 = "lantiq/vr9_phy11g_a1x.bin"; /*VR9 1.1*/ + firmware2 = "lantiq/vr9_phy11g_a2x.bin"; /*VR9 1.2*/ + phys = [ 00 01 ]; + }; + + ath9k_eep { + compatible = "ath9k,eeprom"; + ath,eep-flash = <&caldata 0x1000>; + ath,mac-offset = <0x110c>; + ath,mac-increment = <2>; + ath,pci-slot = <0xe>; /* 14 */ + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 2 1>; + linux,code = <0x198>; + }; + + wps { + label = "wps"; + gpios = <&gpio 25 1>; + linux,code = <0x211>; + }; + + restart { + label = "restart"; + gpios = <&gpio 39 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + broadband-red { + label = "soc:red:broadband"; + gpios = <&gpio 0 1>; + }; + broadband-green { + label = "soc:green:broadband"; + gpios = <&gpio 3 1>; + }; + broadband-blue { + label = "soc:blue:broadband"; + gpios = <&gpio 8 1>; + }; + + wireless-red { + label = "soc:red:wireless"; + gpios = <&gpio 9 1>; + }; + wireless-green { + label = "soc:green:wireless"; + gpios = <&gpio 10 1>; + }; + wireless-blue { + label = "soc:blue:wireless"; + gpios = <&gpio 11 1>; + }; + + power-red { + label = "soc:red:power"; + gpios = <&gpio 12 1>; + }; + power-green { + label = "soc:green:power"; + gpios = <&gpio 14 1>; + }; + power-blue { + label = "soc:blue:power"; + gpios = <&gpio 15 1>; + }; + + dimmed { + label = "dimmed"; + gpios = <&gpio 19 0>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/DGN1000B.dts b/target/linux/lantiq/dts/DGN1000B.dts new file mode 100644 index 0000000..3b522ac --- /dev/null +++ b/target/linux/lantiq/dts/DGN1000B.dts @@ -0,0 +1,138 @@ +/dts-v1/; + +/include/ "amazonse.dtsi" + +/ { + model = "DGN1000B - Netgear DGN1000B"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x1000000>; + }; + + fpi@10000000 { + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + spi { + lantiq,groups = "spi", "spi_cs1"; + lantiq,function = "spi"; + }; + asc { + lantiq,groups = "asc"; + lantiq,function = "asc"; + }; + keys_in { + lantiq,pins = "io0",/* "io25", */"io29"; + lantiq,pull = <2>; + lantiq,open-drain = <1>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + spi@E100800 { + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l3205d"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l64"; + spi-max-frequency = <5000000>; + + partition@0 { + reg = <0x0 0x20000>; + label = "SPI (RO) U-Boot Image"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "ENV_MAC"; + read-only; + }; + + partition@30000 { + reg = <0x30000 0x10000>; + label = "DPF"; + read-only; + }; + + partition@40000 { + reg = <0x40000 0x10000>; + label = "NVRAM"; + read-only; + }; + + partition@500000 { + reg = <0x50000 0x003a0000>; + label = "kernel"; + }; + }; + }; + ifxhcd@E101000 { + status = "okay"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 0 1>; + linux,code = <0x198>; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 25 1>; + linux,code = <0xf7>; + }; + wps { + label = "wps"; + gpios = <&gpio 29 1>; + linux,code = <0x211>; + }; + }; + + gpio-leds { + cmpatible = "gpio-leds"; + dsl { + label = "dsl"; + gpios = <&gpio 1 1>; + default-state = "on"; + }; + online { + label = "online"; + gpios = <&gpio 2 1>; + default-state = "on"; + }; + online2 { + label = "online2"; + gpios = <&gpio 3 1>; + default-state = "on"; + }; + wps { + label = "wps"; + gpios = <&gpio 4 1>; + default-state = "on"; + }; + power { + label = "power"; + gpios = <&gpio 13 1>; + default-state = "on"; + }; + }; +}; diff --git a/target/linux/lantiq/dts/DGN3500.dts b/target/linux/lantiq/dts/DGN3500.dts new file mode 100644 index 0000000..d256871 --- /dev/null +++ b/target/linux/lantiq/dts/DGN3500.dts @@ -0,0 +1,7 @@ +/dts-v1/; + +/include/ "DGN3500.dtsi" + +/ { + model = "DGN3500 - Netgear DGN3500"; +}; diff --git a/target/linux/lantiq/dts/DGN3500.dtsi b/target/linux/lantiq/dts/DGN3500.dtsi new file mode 100644 index 0000000..5d2c456 --- /dev/null +++ b/target/linux/lantiq/dts/DGN3500.dtsi @@ -0,0 +1,183 @@ +/include/ "ar9.dtsi" + +/ { + chosen { + bootargs-append = "root= console=ttyLTQ0,115200"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci { + lantiq,groups = "gnt1", "req1"; + lantiq,function = "pci"; + }; + pci-in { + lantiq,groups = "req1"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + pci-out { + lantiq,groups = "gnt1"; + lantiq,output = <1>; + lantiq,pull = <0>; + }; + spi-in { + lantiq,pins = "io16"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + spi-out { + lantiq,pins = "io10", "io17", "io18", "io21"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + ifxhcd@E101000 { + status = "okay"; + }; + + pci@E105400 { + status = "okay"; + + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + gpio-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "spi-gpio"; + + gpio-miso = <&gpio 16 0>; + gpio-mosi = <&gpio 17 0>; + gpio-sck = <&gpio 18 0>; + num-chipselects = <1>; + cs-gpios = <&gpio 10 1>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fl129p0"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <1000000>; + + partition@0 { + reg = <0x0 0x10000>; + label = "uboot"; + read-only; + }; + + partition@10000 { + reg = <0x10000 0x10000>; + label = "uboot-env"; + read-only; + }; + + ath9k_cal: partition@20000 { + reg = <0x20000 0x10000>; + label = "calibration"; + read-only; + }; + + partition@50000 { + reg = <0x50000 0xfa0000>; + label = "firmware"; + }; + }; + }; + + ath9k_eep { + compatible = "ath9k,eeprom"; + ath,eep-flash = <&ath9k_cal 0xf000>; + ath,pci-slot = <14>; + ath,eep-endian; + ath,eep-swap; + }; + + rtl8366rb { + compatible = "rtl8366rb"; + gpio-sda = <&gpio 35 0>; + gpio-sck = <&gpio 37 0>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 36 1>; + linux,code = <0xf7>; + }; + wps { + label = "wps"; + gpios = <&gpio 54 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio 53 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + internet { + label = "internet"; + gpios = <&gpio 2 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 4 1>; + }; + usb { + label = "usb"; + gpios = <&gpio 22 1>; + }; + power { + label = "power"; + gpios = <&gpio 34 1>; + }; + power2 { + label = "power2"; + gpios = <&gpio 39 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 51 1>; + }; + wps { + label = "wps"; + gpios = <&gpio 52 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/DGN3500B.dts b/target/linux/lantiq/dts/DGN3500B.dts new file mode 100644 index 0000000..71a4e58 --- /dev/null +++ b/target/linux/lantiq/dts/DGN3500B.dts @@ -0,0 +1,7 @@ +/dts-v1/; + +/include/ "DGN3500.dtsi" + +/ { + model = "DGN3500B - Netgear DGN3500B"; +}; diff --git a/target/linux/lantiq/dts/EASY50712.dts b/target/linux/lantiq/dts/EASY50712.dts new file mode 100644 index 0000000..e44267a --- /dev/null +++ b/target/linux/lantiq/dts/EASY50712.dts @@ -0,0 +1,113 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; /* 64 KB */ + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; /* 64 KB */ + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + partition@400000 { + label = "rootfs"; + reg = <0x400000 0x400000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xway"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; /* stp */ + lantiq,open-drain; + lantiq,pull = <0>; + }; + }; + }; + + etop@E180000 { + compatible = "lantiq,etop-xway"; + reg = <0xE180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <73 78>; + phy-mode = "rmii"; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + stp0: stp@E100BB0 { + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xE100BB0 0x40>; + + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + }; + + pci@E105400 { + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29 + >; + gpios-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + + }; +}; diff --git a/target/linux/lantiq/dts/EASY50810.dts b/target/linux/lantiq/dts/EASY50810.dts new file mode 100644 index 0000000..5f4b733 --- /dev/null +++ b/target/linux/lantiq/dts/EASY50810.dts @@ -0,0 +1,114 @@ +/dts-v1/; + +/include/ "ar9.dtsi" + +/ { + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; /* 64 KB */ + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; /* 64 KB */ + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x3d0000>; + }; + + partition@400000 { + label = "rootfs"; + reg = <0x400000 0x400000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; /* stp */ + lantiq,open-drain; + lantiq,pull = <0>; + }; + }; + }; + + etop@E180000 { + compatible = "lantiq,etop-xway"; + reg = <0xE180000 0x40000 + 0xE108000 0x200>; + interrupt-parent = <&icu0>; + interrupts = <72 73>; + phy-mode = "rmii"; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + stp0: stp@E100BB0 { + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xE100BB0 0x40>; + + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + }; + + pci@E105400 { + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29 + >; + gpios-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + + }; +}; diff --git a/target/linux/lantiq/dts/EASY80920.dtsi b/target/linux/lantiq/dts/EASY80920.dtsi new file mode 100644 index 0000000..4013610 --- /dev/null +++ b/target/linux/lantiq/dts/EASY80920.dtsi @@ -0,0 +1,335 @@ +/include/ "vr9.dtsi" + +/ { + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "lantiq,localbus", "simple-bus"; + + }; + + spi@E100800 { + compatible = "lantiq,spi-xway-broken"; + reg = <0xE100800 0x100>; + interrupt-parent = <&icu0>; + interrupts = <22 23 24>; + #address-cells = <1>; + #size-cells = <1>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fl129p0"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l3205d"; + spi-max-frequency = <1000000>; + + partition@0 { + reg = <0x0 0x20000>; + label = "SPI (RO) U-Boot Image"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "ENV_MAC"; + read-only; + }; + + partition@30000 { + reg = <0x30000 0x10000>; + label = "DPF"; + read-only; + }; + + partition@40000 { + reg = <0x40000 0x10000>; + label = "NVRAM"; + read-only; + }; + + partition@500000 { + reg = <0x50000 0x003a0000>; + label = "kernel"; + }; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + interrupt-parent = <&icu0>; + interrupts = <166 135 66 40 41 42 38>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + exin3 { + lantiq,groups = "exin3"; + lantiq,function = "exin"; + }; + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + spi { + lantiq,groups = "spi", "spi_cs4"; + lantiq,function = "spi"; + }; + nand { + lantiq,groups = "nand cle", "nand ale", + "nand rd", "nand rdy"; + lantiq,function = "ebu"; + }; + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + pci { + lantiq,groups = "gnt1", "req1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */ + "io4", "io5", "io6", /* stp */ + "io21", + "io33"; + lantiq,open-drain; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + conf_in { + lantiq,pins = "io39", /* exin3 */ + "io48"; /* nand rdy */ + lantiq,pull = <2>; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 /* pmac */ + >; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mac-address = [ 00 11 22 33 44 55 ]; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + }; + + wan: interface@1 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + mac-address = [ 00 11 22 33 44 56 ]; + lantiq,wan; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; + + test: interface@2 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + mac-address = [ 00 11 22 33 44 57 ]; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phynmode0 = "gmii"; + phy-handle = <&phy13>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + + stp: stp@E100BB0 { + compatible = "lantiq,gpio-stp-xway"; + reg = <0xE100BB0 0x40>; + #gpio-cells = <2>; + gpio-controller; + + lantiq,shadow = <0xffff>; + lantiq,groups = <0x7>; + lantiq,dsl = <0x3>; + lantiq,phy1 = <0x7>; + lantiq,phy2 = <0x7>; + /* lantiq,rising; */ + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 33 0>; + lantiq,portmask = <0x3>; + }; + + pci@E105400 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway1"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xE105400 0x400>; /* pci bridge */ + lantiq,bus-clock = <33333333>; + /*lantiq,external-clock;*/ + lantiq,delay-hi = <0>; /* 0ns delay */ + lantiq,delay-lo = <0>; /* 0.0ns delay */ + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29 + >; + gpios-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware = "lantiq/vr9_phy11g_a2x.bin"; + phys = [ 00 01 ]; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; +/* reset { + label = "reset"; + gpios = <&gpio 7 1>; + linux,code = <0x198>; + };*/ + paging { + label = "paging"; + gpios = <&gpio 11 1>; + linux,code = <0x100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "power"; + gpios = <&stp 9 0>; + default-state = "on"; + }; + warning { + label = "warning"; + gpios = <&stp 22 0>; + }; + fxs1 { + label = "fxs1"; + gpios = <&stp 21 0>; + }; + fxs2 { + label = "fxs2"; + gpios = <&stp 20 0>; + }; + fxo { + label = "fxo"; + gpios = <&stp 19 0>; + }; + usb1 { + label = "usb1"; + gpios = <&stp 18 0>; + }; + usb2 { + label = "usb2"; + gpios = <&stp 15 0>; + }; + sd { + label = "sd"; + gpios = <&stp 14 0>; + }; + wps { + label = "wps"; + gpios = <&stp 12 0>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/EASY80920NAND.dts b/target/linux/lantiq/dts/EASY80920NAND.dts new file mode 100644 index 0000000..88fbcaa --- /dev/null +++ b/target/linux/lantiq/dts/EASY80920NAND.dts @@ -0,0 +1,35 @@ +/dts-v1/; + + +/include/ "EASY80920.dtsi" + +/ { + fpi@10000000 { + localbus@0 { + ranges = <0 0 0x4000000 0x3ffffff>; + nand-parts@0 { + compatible = "gen_nand", "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x40000 0x40000>; + }; + + partition@20000 { + label = "firmware"; + reg = <0x80000 0x3f80000>; + }; + }; + }; + }; +}; diff --git a/target/linux/lantiq/dts/EASY80920NOR.dts b/target/linux/lantiq/dts/EASY80920NOR.dts new file mode 100644 index 0000000..212ad5c --- /dev/null +++ b/target/linux/lantiq/dts/EASY80920NOR.dts @@ -0,0 +1,34 @@ +/dts-v1/; + + +/include/ "EASY80920.dtsi" + +/ { + fpi@10000000 { + localbus@0 { + ranges = <0 0 0x0 0x3ffffff>; + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x10000>; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x10000 0x10000>; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0x7e0000>; + }; + }; + }; + }; +}; diff --git a/target/linux/lantiq/dts/FRITZ3370.dts b/target/linux/lantiq/dts/FRITZ3370.dts new file mode 100644 index 0000000..c0202ba --- /dev/null +++ b/target/linux/lantiq/dts/FRITZ3370.dts @@ -0,0 +1,268 @@ +/dts-v1/; + +/include/ "vr9.dtsi" + +/ { + model = "FRITZ3370 - Fritz!Box WLAN 3370"; + + chosen { + bootargs = "console=ttyLTQ0,115200 ubi.mtd=1,512 root=/dev/mtdblock9"; + }; + + memory@0 { + reg = <0x0 0x8000000>; + }; + + fpi@10000000 { + localbus@0 { + nand-parts@0 { + compatible = "gen_nand", "lantiq,nand-xway"; + bank-width = <2>; + reg = <1 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "rootfs_ubi"; + reg = <0x400000 0x3000000>; + }; + + partition@3400000 { + label = "vr9_firmware"; + reg = <0x3400000 0x400000>; + }; + partition@3800000 { + label = "reserved"; + reg = <0x3800000 0x3000000>; + }; + partition@6800000 { + label = "config"; + reg = <0x6800000 0x200000>; + }; + partition@6a00000 { + label = "nand-filesystem"; + reg = <0x6a00000 0x1600000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + spi { + lantiq,groups = "spi", "spi_cs4"; + lantiq,function = "gpio"; + }; + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + nand { + lantiq,groups = "nand cle", "nand ale", + "nand rd", "nand cs1", "nand rdy"; + lantiq,function = "ebu"; + lantiq,pull = <1>; + }; + phy-rst { + lantiq,pins = "io37", "io44"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 /* pmac */ + >; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mac-address = [ 00 11 22 33 44 55 ]; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + gpios = <&gpio 37 0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + gpios = <&gpio 44 0>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 5 0 + &gpio 14 0>; + lantiq,portmask = <0x3>; + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "spi-gpio"; + + gpio-miso = <&gpio 16 0>; + gpio-mosi = <&gpio 17 0>; + gpio-sck = <&gpio 18 0>; + num-chipselects = <1>; + cs-gpios = <&gpio 10 1>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l2005a"; + reg = <0 0>; + linux,modalias = "m25p80", "mx25l2005a"; + spi-max-frequency = <1000000>; + + ath9k_cal: partition@0 { + reg = <0x0 0x20000>; + label = "urlader"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "tffs (1)"; + read-only; + }; + + partition@30000 { + reg = <0x30000 0x10000>; + label = "tffs (2)"; + read-only; + }; + }; + }; + + ath9k_eep { + compatible = "ath9k,eeprom"; + ath,eep-flash = <&ath9k_cal 0x985>; + ath,eep-endian; + ath,eep-swap; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware = "lantiq/vr9_phy11g_a1x.bin"; + phys = [ 00 01 ]; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + power { + label = "power"; + gpios = <&gpio 1 0>; + linux,code = <0x100>; + }; +/* wifi { + label = "wifi"; + gpios = <&gpio 29 0>; + linux,code = <0x101>; + };*/ + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "power"; + gpios = <&gpio 32 1>; + }; + power2 { + label = "power2"; + gpios = <&gpio 33 1>; + }; + info_red { + label = "info_red"; + gpios = <&gpio 34 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 35 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 36 1>; + }; + lan { + label = "lan"; + gpios = <&gpio 38 1>; + }; + info_green { + label = "info_green"; + gpios = <&gpio 47 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/FRITZ7320.dts b/target/linux/lantiq/dts/FRITZ7320.dts new file mode 100644 index 0000000..1384575 --- /dev/null +++ b/target/linux/lantiq/dts/FRITZ7320.dts @@ -0,0 +1,138 @@ +/dts-v1/; + +/include/ "ar9.dtsi" + +/ { + model = "FRITZ7320 - 1&1 HomeServer"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "urlader"; + reg = <0x00000 0x20000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x20000 0xf60000>; + }; + + partition@f80000 { + label = "tffs (1)"; + reg = <0xf80000 0x40000>; + read-only; + }; + + partition@fc0000 { + label = "tffs (2)"; + reg = <0xfc0000 0x40000>; + read-only; + }; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci { + lantiq,groups = "gnt1", "req1", "req2", "req3", "req4", "gnt2", "gnt3", "gnt4"; + lantiq,function = "pci"; + }; + pci-in { + lantiq,groups = "req1", "req2", "req3", "req4"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + pci-out { + lantiq,groups = "gnt1", "gnt2", "gnt3", "gnt4"; + lantiq,output = <1>; + lantiq,pull = <0>; + }; + }; + }; + + etop@E180000 { + phy-mode = "mii"; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + ifxhcd@E101000 { + status = "okay"; + }; + + pci@E105400 { + status = "okay"; + req-mask = <0xf>; + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + gpio-reset = <&gpio 21 0>; + req-mask = <0xf>; /* GNT1 */ + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + rfkill { + label = "rfkill"; + gpios = <&gpio 1 1>; + linux,code = <0xf7>; + }; + dect { + label = "dect"; + gpios = <&gpio 2 1>; + linux,code = <0x102>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + power { + label = "power"; + gpios = <&gpio 44 1>; + }; + voice { + label = "voice"; + gpios = <&gpio 47 1>; + }; + dect { + label = "dect"; + gpios = <&gpio 38 1>; + }; + wlan { + label = "wlan"; + gpios = <&gpio 37 1>; + }; + online { + label = "online"; + gpios = <&gpio 35 1>; + }; + online2 { + label = "online2"; + gpios = <&gpio 45 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/GIGASX76X.dts b/target/linux/lantiq/dts/GIGASX76X.dts new file mode 100644 index 0000000..b4bb956 --- /dev/null +++ b/target/linux/lantiq/dts/GIGASX76X.dts @@ -0,0 +1,115 @@ +/dts-v1/; + +/include/ "danube.dtsi" + +/ { + model = "GIGASX76X - Gigaset SX761,SX762,SX763"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + sram@1F000000 { + vmmc@107000 { + status = "okay"; + gpios = <&gpiomm 1 0>; + }; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + }; + + partition@10000 { + label = "uboot_env"; + reg = <0x30000 0x10000>; + }; + + partition@40000 { + label = "firmware"; + reg = <0x40000 0x7c0000>; + }; + }; + + gpiomm: gpiomm@4000000 { + compatible = "lantiq,gpio-mm"; + reg = <1 0x0 0x10 >; + #address-cells = <1>; + #size-cells = <1>; + #gpio-cells = <2>; + gpio-controller; + lantiq,shadow = <0x3>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + }; + }; + + gpios: stp@E100BB0 { + status = "okay"; + }; + + etop@E180000 { + phy-mode = "rmii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 29 0>; + }; + + pci@E105400 { + status = "okay"; + lantiq,internal-clock; + gpio-reset = <&gpio 21 0>; + req-mask = <0x1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 14 0>; + linux,code = <0x198>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + switch { + gpio-export,name = "switch"; + gpio-export,output = <1>; + gpios = <&gpio 19 0>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/GR7000.dts b/target/linux/lantiq/dts/GR7000.dts new file mode 100644 index 0000000..fcc27eb --- /dev/null +++ b/target/linux/lantiq/dts/GR7000.dts @@ -0,0 +1,135 @@ +/dts-v1/; + +/include/ "ar9.dtsi" + +/ { + model = "GR7000 - Aztech GR7000"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "uboot_env"; + reg = <0x20000 0x10000>; + read-only; + }; + + partition@30000 { + label = "firmware"; + reg = <0x30000 0x7d0000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + pci-in { + lantiq,groups = "req1"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + pci-out { + lantiq,groups = "gnt1"; + lantiq,output = <1>; + lantiq,pull = <0>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + }; + + pci@E105400 { + status = "okay"; + }; + + stp: stp@E100BB0 { + compatible = "lantiq,gpio-stp-xway"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100BB0 0x40>; + + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 53 1>; + linux,code = <0x198>; + }; + wps { + label = "wps"; + gpios = <&gpio 54 1>; + linux,code = <0x211>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power2 { + label = "power2"; + gpios = <&stp 4 0>; + }; + internet { + label = "internet"; + gpios = <&stp 2 1>; + default-state = "off"; + }; + internet2 { + label = "internet2"; + gpios = <&stp 3 1>; + }; + usb { + label = "usb"; + gpios = <&stp 10 1>; + }; + wifi { + label = "wifi"; + gpios = <&stp 15 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/H201L.dts b/target/linux/lantiq/dts/H201L.dts new file mode 100644 index 0000000..5cb5612 --- /dev/null +++ b/target/linux/lantiq/dts/H201L.dts @@ -0,0 +1,139 @@ +/dts-v1/; + +/include/ "ar9.dtsi" + +/ { + model = "H201L - ZTE H210L"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x20000>; + read-only; + }; + + partition@20000 { + label = "uboot_env"; + reg = <0x20000 0x10000>; + read-only; + }; + + partition@30000 { + label = "firmware"; + reg = <0x30000 0x7d0000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + }; + }; + + etop@E180000 { + phy-mode = "rgmii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 36 0>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 53 1>; + linux,code = <0x198>; + }; + wps { + label = "wps"; + gpios = <&gpio 54 1>; + linux,code = <0x211>; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 55 1>; + linux,code = <0xf7>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "power"; + gpios = <&gpio 19 1>; + default-state = "on"; + }; + online { + label = "online"; + gpios = <&gpio 37 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 4 1>; + }; + phone { + label = "phone"; + gpios = <&gpio 39 1>; + }; + wps { + label = "wps"; + gpios = <&gpio 22 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 6 1>; + }; + usb { + label = "usb"; + gpios = <&gpio 14 1>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + switch { + gpio-export,name = "switch"; + gpio-export,output = <1>; + gpios = <&gpio 38 0>; + }; + usb { + gpio-export,name = "usb"; + gpio-export,output = <1>; + gpios = <&gpio 28 0>; + }; + wifi { + gpio-export,name = "wifi"; + gpio-export,output = <1>; + gpios = <&gpio 7 0>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/P2601HNFX.dts b/target/linux/lantiq/dts/P2601HNFX.dts new file mode 100644 index 0000000..bb9193e --- /dev/null +++ b/target/linux/lantiq/dts/P2601HNFX.dts @@ -0,0 +1,192 @@ +/dts-v1/; + +/include/ "ar9.dtsi" + +/ { + model = "P2601HNFX - ZyXEL P-2601HN-Fx"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff + 1 0 0x4000000 0x4000010>; + compatible = "lantiq,localbus", "simple-bus"; + + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "firmware"; + reg = <0x60000 0xfa0000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <2>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + exin { + lantiq,groups = "exin1"; + lantiq,function = "exin"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; + lantiq,open-drain; + lantiq,pull = <0>; + }; + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + }; + }; + + etop@E180000 { + phy-mode = "rmii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 9 0>; + }; + + stp: stp@E100BB0 { + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xE100BB0 0x40>; + + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + }; + + pci@E105400 { + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 29 1>; + gpios-reset = <&gpio 21 0>; + req-mask = <0x1>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 53 1>; + linux,code = <0x198>; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 54 1>; + linux,code = <0xf7>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "power"; + gpios = <&stp 11 1>; + default-state = "on"; + }; + power2 { + label = "power2"; + gpios = <&gpio 29 1>; + }; + online { + label = "online"; + gpios = <&stp 13 1>; + }; + online2 { + label = "online2"; + gpios = <&stp 12 1>; + }; + dsl { + label = "dsl"; + gpios = <&stp 14 1>; + }; + phone { + label = "phone"; + gpios = <&stp 9 1>; + }; + phone2 { + label = "phone2"; + gpios = <&stp 8 1>; + }; + wifi { + label = "wifi"; + gpios = <&stp 15 1>; + }; + wifi2 { + label = "wifi2"; + gpios = <&stp 10 1>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + switch { + gpio-export,name = "switch"; + gpio-export,output = <1>; + gpios = <&gpio 50 0>; + }; + usb { + gpio-export,name = "wifi"; + gpio-export,output = <1>; + gpios = <&gpio 9 0>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/P2812HNUF1.dts b/target/linux/lantiq/dts/P2812HNUF1.dts new file mode 100644 index 0000000..24ded3e --- /dev/null +++ b/target/linux/lantiq/dts/P2812HNUF1.dts @@ -0,0 +1,106 @@ +/dts-v1/; + +/include/ "P2812HNUFX.dtsi" + +/ { + model = "P2812HNUF1 - ZyXEL P-2812HNU-F1"; + + fpi@10000000 { + localbus@0 { + nand-parts@0 { + compatible = "gen_nand", "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + }; + partition@40000 { + label = "uboot-env"; + reg = <0x40000 0x20000>; + }; + partition@60000 { + label = "kernel"; + reg = <0x60000 0x200000>; + }; + partition@260000 { + label = "ubi"; + reg = <0x260000 0x7da0000>; + }; + }; + }; + pcie@d900000 { + status = "disabled"; + }; + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT3062.eeprom"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + internet_red { /* red */ + label = "internet_red"; + gpios = <&stp 16 1>; + }; + internet_green { + label = "internet_green"; /* green */ + gpios = <&stp 17 1>; + }; + dsl { + label = "dsl"; + gpios = <&stp 18 1>; + }; + dsl2 { + label = "dsl2"; + gpios = <&stp 19 1>; + }; + wireless_red { /* red */ + label = "wireless_red"; + gpios = <&stp 20 1>; + }; + wireless_green { /* green */ + label = "wireless_green"; + gpios = <&stp 21 1>; + }; + power { /* red */ + label = "power"; + gpios = <&stp 22 1>; + }; + power2 { /* green */ + label = "power2"; + gpios = <&stp 23 1>; + }; + usb1 { /* green */ + label = "usb1"; + gpios = <&gpio 38 1>; + }; + usb2 { /* green */ + label = "usb2"; + gpios = <&gpio 44 1>; + }; + phone1 { /* green */ + label = "phone1"; + gpios = <&gpio 11 1>; + }; + phone1warn { /* red */ + label = "phone1warn"; + gpios = <&gpio 12 1>; + }; + phone2warn { /* red */ + label = "phone2warn"; + gpios = <&gpio 26 1>; + }; + phone2 { /* green */ + label = "phone2"; + gpios = <&gpio 28 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/P2812HNUF3.dts b/target/linux/lantiq/dts/P2812HNUF3.dts new file mode 100644 index 0000000..5d25c3c --- /dev/null +++ b/target/linux/lantiq/dts/P2812HNUF3.dts @@ -0,0 +1,109 @@ +/dts-v1/; + +/include/ "P2812HNUFX.dtsi" + +/ { + model = "P2812HNUF3 - ZyXEL P-2812HNU-F3"; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x50000>; + read-only; + }; + partition@50000 { + label = "uboot-env"; + reg = <0x50000 0x10000>; + }; + partition@60000 { + label = "unused"; + reg = <0x60000 0x7a0000>; + }; + }; + + nand-parts@0 { + compatible = "gen_nand", "lantiq,nand-xway"; + lantiq,cs = <1>; + bank-width = <2>; + reg = <1 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x200000>; + }; + partition@200000 { + label = "ubi"; + reg = <0x200000 0x7e00000>; + }; + }; + }; + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT3092.eeprom"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + internet2 { + label = "internet2"; + gpios = <&stp 16 1>; + }; + internet { + label = "internet"; + gpios = <&stp 17 1>; + }; + dsl { + label = "dsl"; + gpios = <&stp 18 1>; + }; + dsl2 { + label = "dsl2"; + gpios = <&stp 19 1>; + }; + wireless_red { + label = "wireless_red"; + gpios = <&stp 20 1>; + }; + wireless_green { + label = "wireless_green"; + gpios = <&stp 21 1>; + }; + power2 { + label = "power2"; + gpios = <&stp 22 1>; + }; + power { + label = "power"; + gpios = <&stp 23 1>; + }; + phone1 { + label = "phone1"; + gpios = <&gpio 11 1>; + }; + phone1warn { + label = "phone1warn"; + gpios = <&gpio 12 1>; + }; + phone2 { + label = "phone2"; + gpios = <&gpio 28 1>; + }; + phone2warn { + label = "phone2warn"; + gpios = <&gpio 26 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/P2812HNUFX.dtsi b/target/linux/lantiq/dts/P2812HNUFX.dtsi new file mode 100644 index 0000000..d93e862 --- /dev/null +++ b/target/linux/lantiq/dts/P2812HNUFX.dtsi @@ -0,0 +1,262 @@ +/include/ "vr9.dtsi" + +/ { + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x8000000>; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + interrupt-parent = <&icu0>; + interrupts = <166 135 66 40 41 42 38>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + exin3 { + lantiq,groups = "exin3"; + lantiq,function = "exin"; + }; + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + gphy-leds { + lantiq,groups = "gphy0 led1", "gphy1 led1", + "gphy0 led2", "gphy1 led2"; + lantiq,function = "gphy"; + lantiq,pull = <2>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <2>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + pci-in { + lantiq,groups = "req1"; + lantiq,function = "pci"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + pci-out { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + ifxhcd-rst { + lantiq,pins = "io33"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + nand_out { + lantiq,groups = "nand cle", "nand ale"; + lantiq,function = "ebu"; + lantiq,output = <1>; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + nand_cs1 { + lantiq,groups = "nand cs1"; + lantiq,function = "ebu"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 >; /* pmac */ + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mac-address = [ 00 11 22 33 44 55 ]; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + + stp: stp@E100BB0 { + compatible = "lantiq,gpio-stp-xway"; + reg = <0xE100BB0 0x40>; + #gpio-cells = <2>; + gpio-controller; + + lantiq,shadow = <0xffffff>; + lantiq,groups = <0x7>; + lantiq,dsl = <0x0>; + lantiq,phy1 = <0x0>; + lantiq,phy2 = <0x0>; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 33 0>; + lantiq,portmask = <0x3>; + }; + + ifxhcd@E106000 { + status = "okay"; + gpios = <&gpio 33 0>; + }; + + pci@E105400 { + status = "okay"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xE105400 0x400>; /* pci bridge */ + lantiq,bus-clock = <33333333>; + /*lantiq,external-clock;*/ + lantiq,delay-hi = <0>; /* 0ns delay */ + lantiq,delay-lo = <0>; /* 0.0ns delay */ + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x7000 0 0 1 &icu0 30 1 // slot 14, irq 30 + >; + gpio-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware1 = "lantiq/vr9_phy11g_a1x.bin"; /*VR9 1.1*/ + firmware2 = "lantiq/vr9_phy11g_a2x.bin"; /*VR9 1.2*/ + phys = [ 00 01 ]; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 39 1>; + linux,code = <0x198>; + }; + + rfkill { + label = "rfkill"; + gpios = <&gpio 1 1>; + linux,code = <0xf7>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/TDW8970.dts b/target/linux/lantiq/dts/TDW8970.dts new file mode 100644 index 0000000..172c46c --- /dev/null +++ b/target/linux/lantiq/dts/TDW8970.dts @@ -0,0 +1,7 @@ +/dts-v1/; + +/include/ "TDW89X0.dtsi" + +/ { + model = "TDW8970 - TP-LINK TD-W8970"; +}; diff --git a/target/linux/lantiq/dts/TDW8980.dts b/target/linux/lantiq/dts/TDW8980.dts new file mode 100644 index 0000000..ad3d182 --- /dev/null +++ b/target/linux/lantiq/dts/TDW8980.dts @@ -0,0 +1,31 @@ +/dts-v1/; + +/include/ "TDW89X0.dtsi" + +/ { + model = "TDW8980 - TP-LINK TD-W8980"; + + fpi@10000000 { + gpio: pinmux@E100B10 { + state_default: pinmux { + pci_rst { + lantiq,pins = "io21"; + lantiq,output = <1>; + lantiq,open-drain; + }; + }; + }; + + pci@E105400 { + status = "okay"; + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + gpio-reset = <&gpio 21 0>; + }; + }; + + ath9k_eep { + ath,pci-slot = <0>; + }; +}; diff --git a/target/linux/lantiq/dts/TDW89X0.dtsi b/target/linux/lantiq/dts/TDW89X0.dtsi new file mode 100644 index 0000000..084aa25 --- /dev/null +++ b/target/linux/lantiq/dts/TDW89X0.dtsi @@ -0,0 +1,252 @@ +/include/ "vr9.dtsi" + +/ { + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + gphy-leds { + lantiq,groups = "gphy0 led1", "gphy1 led1"; + lantiq,function = "gphy"; + lantiq,pull = <2>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + phy-rst { + lantiq,pins = "io42"; + lantiq,pull = <0>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + spi-in { + lantiq,pins = "io16"; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + spi-out { + lantiq,pins = "io10", "io17", "io18", "io21"; + lantiq,open-drain = <0>; + lantiq,pull = <2>; + }; + pcie-rst { + lantiq,pins = "io38"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 /* pmac */ + >; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&ath9k_cal 0xf100>; + lantiq,switch; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + // gpios = <&gpio 42 1>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 33 0>; + lantiq,portmask = <0x3>; + }; + + ifxhcd@E106000 { + status = "okay"; + gpios = <&gpio 33 0>; + }; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware = "lantiq/vr9_phy11g_a2x.bin"; + phys = [ 00 01 ]; + }; + + pcie { + compatible = "lantiq,pcie-xway"; + }; + + spi { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "spi-gpio"; + + gpio-miso = <&gpio 16 0>; + gpio-mosi = <&gpio 17 0>; + gpio-sck = <&gpio 18 0>; + num-chipselects = <1>; + cs-gpios = <&gpio 10 1>; + + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "en25q64", "m25p80"; + reg = <0 0>; + linux,modalias = "en25q64"; + spi-max-frequency = <1000000>; + + partition@0 { + reg = <0x0 0x20000>; + label = "u-boot"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x6a0000>; + label = "firmware"; + }; + + partition@6c0000 { + reg = <0x6c0000 0x100000>; + label = "dsl_fw"; + }; + + partition@7c0000 { + reg = <0x7c0000 0x10000>; + label = "config"; + read-only; + }; + + ath9k_cal: partition@7d0000 { + reg = <0x7d0000 0x30000>; + label = "boardconfig"; + read-only; + }; + }; + }; + + ath9k_eep { + compatible = "ath9k,eeprom"; + ath,eep-flash = <&ath9k_cal 0x21000>; + ath,mac-offset = <0xf100>; + ath,mac-increment; + ath,led-pin = <0>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 0 1>; + linux,code = <0x198>; + }; + + wifi { + label = "wifi"; + gpios = <&gpio 9 0>; + linux,code = <0xf7>; + linux,input-type = <5>; /* EV_SW */ + }; + + wps { + label = "wps"; + gpios = <&gpio 39 1>; + linux,code = <0x211>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + dsl { + label = "dsl"; + gpios = <&gpio 4 0>; + }; + internet { + label = "internet"; + gpios = <&gpio 5 0>; + }; + usb0 { + label = "usb"; + gpios = <&gpio 19 0>; + }; + usb2 { + label = "usb2"; + gpios = <&gpio 20 0>; + }; + wps { + label = "wps"; + gpios = <&gpio 37 0>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/VG3503J.dts b/target/linux/lantiq/dts/VG3503J.dts new file mode 100644 index 0000000..b4b3cf5 --- /dev/null +++ b/target/linux/lantiq/dts/VG3503J.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +/include/ "VG3503J.dtsi" + +/ { + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware = "lantiq/vr9_phy22f_a1x.bin"; + phys = [ 00 01 ]; + }; +}; diff --git a/target/linux/lantiq/dts/VG3503J.dtsi b/target/linux/lantiq/dts/VG3503J.dtsi new file mode 100644 index 0000000..e9a3c70 --- /dev/null +++ b/target/linux/lantiq/dts/VG3503J.dtsi @@ -0,0 +1,164 @@ +/include/ "vr9.dtsi" + +/ { + model = "VG3503J - BT OpenReach VDSL Modem"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x2000000>; + }; + + fpi@10000000 { + localbus@0 { + ranges = <0 0 0x0 0x3ffffff>; + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x20000>; + }; + + partition@20000 { + label = "kernel"; + reg = <0x20000 0x300000>; + }; + + partition@1a0000 { + label = "rootfs"; + reg = <0x320000 0x420000>; + }; + + partition@740000 { + label = "btagent"; + reg = <0x740000 0x80000>; + }; + + partition@7c0000 { + label = "pri_bfocus_cfg"; + reg = <0x7c0000 0x10000>; + }; + + partition@7d0000 { + label = "sec_bfocus_cfg"; + reg = <0x7d0000 0x10000>; + }; + + partition@7e0000 { + label = "sysconfig"; + reg = <0x7e0000 0x10000>; + }; + + partition@7f0000 { + label = "misc_cfg"; + reg = <0x7f0000 0x10000>; + }; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + gphy-leds { + lantiq,groups = "gphy0 led0", "gphy0 led1", + "gphy0 led2", "gphy1 led0", + "gphy1 led1", "gphy1 led2"; + lantiq,function = "gphy"; + lantiq,pull = <2>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 /* pmac */ + >; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mac-address = [ 00 11 22 33 44 55 ]; + lantiq,switch; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "mii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 6 1>; + linux,code = <0x198>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power2 { + label = "power2"; + gpios = <&gpio 14 1>; + }; + dsl { + label = "bt:green:dsl"; + gpios = <&gpio 19 1>; + }; + power { + label = "power"; + gpios = <&gpio 28 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/VG3503J_V2.dts b/target/linux/lantiq/dts/VG3503J_V2.dts new file mode 100644 index 0000000..005d5bc --- /dev/null +++ b/target/linux/lantiq/dts/VG3503J_V2.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +/include/ "VG3503J.dtsi" + +/ { + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware = "lantiq/vr9_phy22f_a2x.bin"; + phys = [ 00 01 ]; + }; +}; diff --git a/target/linux/lantiq/dts/VGV7510KW22.dtsi b/target/linux/lantiq/dts/VGV7510KW22.dtsi new file mode 100644 index 0000000..077ed23 --- /dev/null +++ b/target/linux/lantiq/dts/VGV7510KW22.dtsi @@ -0,0 +1,256 @@ +/include/ "vr9.dtsi" + +/ { + model = "VGV7510KW22 - o2 Box 6431"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + boardconfig: partition@fe0000 { + label = "board_config"; + reg = <0xfe0000 0x20000>; + read-only; + }; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ip101a-rst { + lantiq,pins = "io46"; + lantiq,output = <0>; + lantiq,pull = <1>; + }; + gphy-leds { + lantiq,groups = "gphy0 led1", + "gphy1 led0", "gphy1 led1"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + lantiq,pull = <2>; + lantiq,open-drain = <0>; + lantiq,output = <1>; + }; + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + pci-rst { + lantiq,pins = "io21"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + spi { + lantiq,groups = "spi"; + lantiq,function = "spi"; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 /* pmac */ + >; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mtd-mac-address = <&boardconfig 0x16>; + lantiq,switch; + + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "mii"; + phy-handle = <&phy11>; + }; + ethernet@3 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <3>; + phy-mode = "mii"; + phy-handle = <&phy12>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "mii"; + phy-handle = <&phy14>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy12: ethernet-phy@12 { + reg = <0x12>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + phy14: ethernet-phy@14 { + reg = <0x14>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + }; + }; + + stp: stp@E100BB0 { + compatible = "lantiq,gpio-stp-xway"; + reg = <0xE100BB0 0x40>; + #gpio-cells = <2>; + gpio-controller; + + lantiq,shadow = <0xff>; + lantiq,groups = <0x1>; + lantiq,dsl = <0x0>; + lantiq,phy1 = <0x7>; + lantiq,phy2 = <0x7>; /* enable gphy0 led2 = LAN2 LED */ + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 47 0>; + }; + + pci@E105400 { + status = "okay"; + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x7000 0 0 1 &icu0 30 1 // slot 14, irq 30 + >; + gpio-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + + pcie@d900000 { + status = "disabled"; + }; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware1 = "lantiq/vr9_phy22f_a1x.bin"; /*VR9 1.1*/ + firmware2 = "lantiq/vr9_phy22f_a2x.bin"; /*VR9 1.2*/ + phys = [ 00 01 ]; + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT3062.eeprom"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + reset { + label = "reset"; + gpios = <&gpio 6 1>; + linux,code = <0x198>; + }; + + wps { + label = "wps"; + gpios = <&gpio 9 1>; + linux,code = <0x211>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + dsl { + label = "dsl"; + gpios = <&gpio 2 1>; + }; + + internet_red { + label = "internet_red"; + gpios = <&gpio 10 1>; + }; + + info_red { + label = "info_red"; + gpios = <&gpio 12 1>; + }; + + power { + label = "power"; /* green */ + gpios = <&gpio 14 1>; + }; + + info_green { + label = "info_green"; + gpios = <&gpio 15 1>; + }; + + internet_green { + label = "internet_green"; + gpios = <&gpio 19 1>; + }; + + wifi { + label = "wifi"; + gpios = <&gpio 20 1>; + }; + + power2 { + label = "power2"; /* red */ + gpios = <&gpio 28 1>; + }; + + phone_red { + label = "phone_red"; + gpios = <&gpio 29 1>; + }; + }; +}; diff --git a/target/linux/lantiq/dts/VGV7510KW22BRN.dts b/target/linux/lantiq/dts/VGV7510KW22BRN.dts new file mode 100644 index 0000000..1880c8c --- /dev/null +++ b/target/linux/lantiq/dts/VGV7510KW22BRN.dts @@ -0,0 +1,53 @@ +/dts-v1/; + +/include/ "VGV7510KW22.dtsi" + +/ { + fpi@10000000 { + localbus@0 { + nor-boot@0 { + partition@0 { + label = "Boot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "Configuration"; + reg = <0x40000 0x40000>; + read-only; + }; + + partition@80000 { + label = "Certificate"; + reg = <0x80000 0x20000>; + read-only; + }; + + partition@a0000 { + label = "Special_Area"; + reg = <0xa0000 0x20000>; + read-only; + }; + + partition@c0000 { + label = "Primary_Setting"; + reg = <0xc0000 0x20000>; + read-only; + }; + + partition@e0000 { + label = "firmware"; /* "Code Image 0" in OFW */ + reg = <0xe0000 0x780000>; + read-only; + }; + + partition@860000 { + label = "Code_Image_1"; + reg = <0x860000 0x780000>; + read-only; + }; + }; + }; + }; +}; diff --git a/target/linux/lantiq/dts/VGV7510KW22NOR.dts b/target/linux/lantiq/dts/VGV7510KW22NOR.dts new file mode 100644 index 0000000..57842bb --- /dev/null +++ b/target/linux/lantiq/dts/VGV7510KW22NOR.dts @@ -0,0 +1,33 @@ +/dts-v1/; + +/include/ "VGV7510KW22.dtsi" + +/ { + fpi@10000000 { + localbus@0 { + nor-boot@0 { + partition@0 { + label = "uboot"; + reg = <0x0 0x60000>; /* 384 KiB */ + read-only; + }; + + partition@60000 { + label = "uboot-env"; + reg = <0x60000 0x20000>; /* 128 KiB */ + read-only; + }; + + partition@80000 { + label = "firmware"; + reg = <0x80000 0xe60000>; /* 14720 KiB */ + }; + + partition@1e80000 { + label = "dsl_fw"; + reg = <0xee0000 0x100000>; /* 1024 KiB */ + }; + }; + }; + }; +}; diff --git a/target/linux/lantiq/dts/VGV7519.dtsi b/target/linux/lantiq/dts/VGV7519.dtsi new file mode 100644 index 0000000..7a7fddb --- /dev/null +++ b/target/linux/lantiq/dts/VGV7519.dtsi @@ -0,0 +1,320 @@ +/include/ "vr9.dtsi" + +/ { + + model = "VGV7519 - KPN Experiabox V8"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "lantiq,localbus", "simple-bus"; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + interrupt-parent = <&icu0>; + interrupts = <166 135 66 40 41 42 38>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + spi { + lantiq,groups = "spi"; + lantiq,function = "spi"; + }; + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + gphy-leds_out { + lantiq,pins = "io7", "io44"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + stp_out { + lantiq,pins = "io4", "io5", "io6"; + lantiq,open-drain = <0>; + lantiq,output = <1>; + lantiq,pull = <0>; + }; + pci-rst { + lantiq,pins = "io21"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + gphy-leds { + lantiq,groups = "gphy0 led1", "gphy1 led0"; + lantiq,function = "gphy"; + lantiq,open-drain = <0>; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; + }; + + eth@E108000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-net"; + reg = < 0xE108000 0x3000 /* switch */ + 0xE10B100 0x70 /* mdio */ + 0xE10B1D8 0x30 /* mii */ + 0xE10B308 0x30 /* pmac */ + >; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + mac-address = [ 00 11 22 33 44 55 ]; + + ethernet@0 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <0>; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + }; + ethernet@1 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <1>; + phy-mode = "rgmii"; + phy-handle = <&phy1>; + }; + ethernet@2 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <2>; + phy-mode = "gmii"; + phy-handle = <&phy11>; + }; + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "gmii"; + phy-handle = <&phy13>; + }; + }; + + wan: interface@1 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + mac-address = [ 00 11 22 33 44 56 ]; + lantiq,wan; + ethernet@5 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <5>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + phy0: ethernet-phy@0 { + reg = <0x0>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + lantiq,c45-reg-init = <1 0 0 0>; + }; + phy1: ethernet-phy@1 { + reg = <0x1>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + lantiq,c45-reg-init = <1 0 0 0>; + }; + phy5: ethernet-phy@5 { + reg = <0x5>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + lantiq,c45-reg-init = <1 0 0 0>; + }; + phy11: ethernet-phy@11 { + reg = <0x11>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + lantiq,c45-reg-init = <1 0 0 0>; + }; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; + lantiq,c45-reg-init = <1 0 0 0>; + }; + }; + }; + + stp: stp@E100BB0 { + compatible = "lantiq,gpio-stp-xway"; + reg = <0xE100BB0 0x40>; + #gpio-cells = <2>; + gpio-controller; + + lantiq,shadow = <0xffff>; + lantiq,groups = <0x3>; + lantiq,dsl = <0x0>; + lantiq,phy1 = <0x0>; + lantiq,phy2 = <0x0>; + /* lantiq,rising; */ + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 32 0>; + lantiq,portmask = <0x3>; + }; + + pci@E105400 { + status = "okay"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xE105400 0x400>; /* pci bridge */ + lantiq,bus-clock = <33333333>; + /*lantiq,external-clock;*/ + lantiq,delay-hi = <0>; /* 0ns delay */ + lantiq,delay-lo = <0>; /* 0.0ns delay */ + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x7000 0 0 1 &icu0 30 1 // slot 14, irq 30 + >; + gpio-reset = <&gpio 21 0>; + req-mask = <0x1>; /* GNT1 */ + }; + + pcie@d900000 { + status = "disabled"; + }; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware1 = "lantiq/vr9_phy11g_a1x.bin"; /*VR9 1.1*/ + firmware2 = "lantiq/vr9_phy11g_a2x.bin"; /*VR9 1.2*/ + phys = [ 00 01 ]; + }; + + ralink_eep { + compatible = "ralink,eeprom"; + ralink,eeprom = "RT2860.eeprom"; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 9 1>; + linux,code = <0x198>; + }; + eco { + label = "eco"; + gpios = <&gpio 41 1>; + linux,code = <247>; + }; + rfkill { + label = "rfkill"; + gpios = <&gpio 45 1>; + linux,code = <0xf7>; + }; + wps { + label = "wps"; + gpios = <&gpio 10 1>; + linux,code = <0x211>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + eco { /* blue */ + label = "eco"; + gpios = <&stp 2 1>; + }; + wps_red { /* red */ + label = "wps_red"; + gpios = <&stp 3 1>; + }; + wps_yellow { /* yellow */ + label = "wps_yellow"; + gpios = <&stp 4 1>; + }; + upgrade { /* blue */ + label = "upgrade"; + gpios = <&stp 5 1>; + }; + tv { /* yellow */ + label = "tv"; + gpios = <&stp 6 1>; + }; + internet_yellow { /* yellow */ + label = "internet_yellow"; + gpios = <&stp 7 1>; + }; + internet_red { /* red */ + label = "internet_red"; + gpios = <&stp 8 1>; + }; + broadband_red { /* red */ + label = "broadband_red"; + gpios = <&stp 9 1>; + }; + broadband_yellow { /* yellow */ + label = "broadband_yellow"; + gpios = <&stp 10 1>; + }; + voice { /* yellow */ + label = "voice"; + gpios = <&stp 11 1>; + }; + wireless_red { /* red */ + label = "wireless_red"; + gpios = <&stp 12 1>; + }; + wireless_yellow { /* yellow */ + label = "wireless_yellow"; + gpios = <&stp 13 1>; + }; + power2 { /* yellow */ + label = "power2"; + gpios = <&stp 14 1>; + }; + power { /* red */ + label = "power"; + gpios = <&stp 15 1>; + default-state = "on"; + }; + }; +}; diff --git a/target/linux/lantiq/dts/VGV7519BRN.dts b/target/linux/lantiq/dts/VGV7519BRN.dts new file mode 100644 index 0000000..c90b680 --- /dev/null +++ b/target/linux/lantiq/dts/VGV7519BRN.dts @@ -0,0 +1,33 @@ +/dts-v1/; + + +/include/ "VGV7519.dtsi" + +/ { + fpi@10000000 { + localbus@0 { + nor-flash@0 { + compatible = "lantiq,nor", "cfi-flash"; + bank-width = <2>; + reg = <0 0x0 0x800000>, <1 0x800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@40000 { + label = "board_config"; + reg = <0x40000 0x10000>; + read-only; + }; + partition@80000 { + label = "firmware"; + reg = <0x80000 0x780000>; + read-only; + }; + partition@880000 { + label = "rootfs_data"; + reg = <0x880000 0x780000>; + }; + }; + }; + }; +}; diff --git a/target/linux/lantiq/dts/VGV7519NOR.dts b/target/linux/lantiq/dts/VGV7519NOR.dts new file mode 100644 index 0000000..355a90c --- /dev/null +++ b/target/linux/lantiq/dts/VGV7519NOR.dts @@ -0,0 +1,39 @@ +/dts-v1/; + + +/include/ "VGV7519.dtsi" + +/ { + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x800000>, <1 0x800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + }; + partition@40000 { + label = "board_config"; + reg = <0x40000 0x10000>; + read-only; + }; + partition@60000 { + label = "uboot_env"; + reg = <0x60000 0x10000>; + }; + partition@80000 { + label = "firmware"; + reg = <0x80000 0xf80000>; + // 0x080000 - 0x01b0000 : kernel + // 0x1b0000 - 0x1000000 : rootfs (squashfs) + // 0x390000 - 0x1000000 : rootfs_data + }; + }; + }; + }; +}; diff --git a/target/linux/lantiq/dts/WBMR.dts b/target/linux/lantiq/dts/WBMR.dts new file mode 100644 index 0000000..60a7508 --- /dev/null +++ b/target/linux/lantiq/dts/WBMR.dts @@ -0,0 +1,168 @@ +/dts-v1/; + +/include/ "ar9.dtsi" + +/ { + model = "WBMR - Buffalo WBMR-HP-G300H"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + localbus@0 { + nor-boot@0 { + compatible = "lantiq,nor"; + bank-width = <2>; + reg = <0 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000 0x40000>; + read-only; + }; + + partition@40000 { + label = "uboot_env"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@20000 { + label = "firmware"; + reg = <0x60000 0x1f20000>; + }; + + partition@0x1fc0000 { + label = "board"; + reg = <0x1fc0000 0x20000>; + read-only; + }; + + partition@0x1fe0000 { + label = "calibration"; + reg = <0x1fe0000 0x20000>; + read-only; + }; + }; + + mac_addr { + compatible = "lantiq,eth-mac"; + reg = <0 0x1fd0024 0x6>; + }; + }; + + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + pci-in { + lantiq,groups = "req1"; + lantiq,output = <0>; + lantiq,open-drain = <1>; + lantiq,pull = <2>; + }; + pci-out { + lantiq,groups = "gnt1"; + lantiq,output = <1>; + lantiq,pull = <0>; + }; + pci_rst { + lantiq,pins = "io21"; + lantiq,pull = <0>; + lantiq,output = <1>; + }; + }; + }; + + etop@E180000 { + phy-mode = "rgmii"; + }; + + ifxhcd@E101000 { + status = "okay"; + gpios = <&gpio 36 0>; + }; + + pci@E105400 { + status = "okay"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + wps { + label = "wps"; + gpios = <&gpio 0 1>; + linux,code = <0x211>; + }; + reset { + label = "reset"; + gpios = <&gpio 37 1>; + linux,code = <0x198>; + }; + eject { + label = "eject"; + gpios = <&gpio 34 1>; + linux,code = <0xf7>; + }; + movie { + label = "movie"; + gpios = <&gpio 22 1>; + linux,code = <0x109>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power { + label = "power"; + gpios = <&gpio 1 1>; + }; + power2 { + label = "power2"; + gpios = <&gpio 5 1>; + }; + security { + label = "security"; + gpios = <&gpio 14 1>; + }; + wifi { + label = "wifi"; + gpios = <&gpio 15 1>; + }; + dsl { + label = "dsl"; + gpios = <&gpio 16 1>; + }; + online { + label = "online"; + gpios = <&gpio 17 1>; + }; + online2 { + label = "online2"; + gpios = <&gpio 18 1>; + }; + movie { + label = "movie"; + gpios = <&gpio 20 1>; + }; + usb { + label = "usb"; + gpios = <&gpio 28 1>; + default-state = "on"; + }; + }; +}; diff --git a/target/linux/lantiq/dts/amazonse.dtsi b/target/linux/lantiq/dts/amazonse.dtsi new file mode 100644 index 0000000..13d3e73 --- /dev/null +++ b/target/linux/lantiq/dts/amazonse.dtsi @@ -0,0 +1,148 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,ase"; + + cpus { + cpu@0 { + compatible = "mips,mips4Kc"; + }; + }; + + biu@1F800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1F800000 0x800000>; + ranges = <0x0 0x1F800000 0x7FFFFF>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + reg = <0x80200 0x28 + 0x80228 0x28 + 0x80250 0x28 + 0x80278 0x28 + 0x802a0 0x28>; + }; + + watchdog@803F0 { + compatible = "lantiq,wdt"; + reg = <0x803F0 0x10>; + }; + }; + + sram@1F000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram", "simple-bus"; + reg = <0x1F000000 0x800000>; + ranges = <0x0 0x1F000000 0x7FFFFF>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + interrupt-parent = <&icu0>; + interrupts = <29 30 31>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + #clock-cells = <1>; + }; + + rcu0: rcu@203000 { + compatible = "lantiq,rcu-xway"; + reg = <0x203000 0x1000>; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + spi@E100800 { + compatible = "lantiq,spi-xway"; + reg = <0xE100800 0x100>; + interrupt-parent = <&icu0>; + interrupts = <24 25 26>; + #address-cells = <1>; + #size-cells = <1>; + }; + + gptu@E100A00 { + compatible = "lantiq,gptu-xway"; + reg = <0xE100A00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <97 98 99 100 101 102>; + status = "disabled"; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-ase"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + }; + + serial@E100C00 { + compatible = "lantiq,asc"; + reg = <0xE100C00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <72 74 75>; + }; + + mei@E116000 { + compatible = "lantiq,mei-xway"; + interrupt-parent = <&icu0>; + interrupts = <63>; + }; + + ifxhcd@E101000 { + compatible = "lantiq,ifxhcd-ase"; + reg = <0xE101000 0x1000 + 0xE120000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <39>; + status = "disabled"; + }; + + dma0: dma@E104100 { + compatible = "lantiq,dma-xway"; + reg = <0xE104100 0x800>; + }; + + ebu0: ebu@E105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xE105300 0x100>; + }; + + ppe@E234000 { + compatible = "lantiq,ppe-ase"; + interrupt-parent = <&icu0>; + interrupts = <85>; + }; + + etop@E180000 { + compatible = "lantiq,etop-xway"; + reg = <0xE180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <105 109>; + }; + }; + + adsl { + compatible = "lantiq,adsl-ase"; + }; +}; diff --git a/target/linux/lantiq/dts/ar9.dtsi b/target/linux/lantiq/dts/ar9.dtsi new file mode 100644 index 0000000..ee4e374 --- /dev/null +++ b/target/linux/lantiq/dts/ar9.dtsi @@ -0,0 +1,192 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,ar9"; + + cpus { + cpu@0 { + compatible = "mips,mips34K"; + }; + }; + + memory@0 { + device_type = "memory"; + }; + + biu@1F800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1F800000 0x800000>; + ranges = <0x0 0x1F800000 0x7FFFFF>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + reg = <0x80200 0x28 + 0x80228 0x28 + 0x80250 0x28 + 0x80278 0x28 + 0x802a0 0x28>; + }; + + watchdog@803F0 { + compatible = "lantiq,wdt"; + reg = <0x803F0 0x10>; + }; + }; + + sram@1F000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram"; + reg = <0x1F000000 0x800000>; + ranges = <0x0 0x1F000000 0x7FFFFF>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + interrupt-parent = <&icu0>; + interrupts = <166 135 66 40 41 42>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + #clock-cells = <1>; + }; + + rcu0: rcu@203000 { + compatible = "lantiq,rcu-xway"; + reg = <0x203000 0x1000>; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + }; + + gptu@E100A00 { + compatible = "lantiq,gptu-xway"; + reg = <0xE100A00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <126 127 128 129 130 131>; + }; + + asc0: serial@E100400 { + compatible = "lantiq,asc"; + reg = <0xE100400 0x400>; + interrupt-parent = <&icu0>; + interrupts = <104 105 106>; + status = "disabled"; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + }; + + asc1: serial@E100C00 { + compatible = "lantiq,asc"; + reg = <0xE100C00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + }; + + ifxhcd@E101000 { + compatible = "lantiq,ifxhcd-arx100", "lantiq,ifxhcd-arx100-dwc2"; + reg = <0xE101000 0x1000 + 0xE120000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <62 91>; + status = "disabled"; + }; + + ifxhcd@E106000 { + compatible = "lantiq,ifxhcd-arx100-dwc2"; + reg = <0xE106000 0x1000 + 0xE1E0000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <91>; + status = "disabled"; + }; + + deu@E103100 { + compatible = "lantiq,deu-arx100"; + reg = <0xE103100 0xf00>; + }; + + dma0: dma@E104100 { + compatible = "lantiq,dma-xway"; + reg = <0xE104100 0x800>; + }; + + ebu0: ebu@E105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xE105300 0x100>; + }; + + mei@E116000 { + compatible = "lantiq,mei-xway"; + interrupt-parent = <&icu0>; + interrupts = <63>; + }; + + etop@E180000 { + compatible = "lantiq,etop-xway"; + reg = <0xE180000 0x40000 + 0xE108000 0x200>; + interrupt-parent = <&icu0>; + interrupts = <73 72>; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + ppe@E234000 { + compatible = "lantiq,ppe-arx100"; + interrupt-parent = <&icu0>; + interrupts = <96>; + }; + + pci0: pci@E105400 { + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xE105400 0x400>; /* pci bridge */ + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + req-mask = <0x1>; + }; + }; + + adsl { + compatible = "lantiq,adsl-arx100"; + }; +}; diff --git a/target/linux/lantiq/dts/danube.dtsi b/target/linux/lantiq/dts/danube.dtsi new file mode 100644 index 0000000..698196d --- /dev/null +++ b/target/linux/lantiq/dts/danube.dtsi @@ -0,0 +1,205 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,danube"; + + chosen { + bootargs = "console=ttyLTQ0,115200 init=/etc/preinit"; + }; + + cpus { + cpu@0 { + compatible = "mips,mips24Kc"; + }; + }; + + memory@0 { + device_type = "memory"; + }; + + biu@1F800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1F800000 0x800000>; + ranges = <0x0 0x1F800000 0x7FFFFF>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + reg = <0x80200 0x28 + 0x80228 0x28 + 0x80250 0x28 + 0x80278 0x28 + 0x802a0 0x28>; + }; + + watchdog@803F0 { + compatible = "lantiq,wdt"; + reg = <0x803F0 0x10>; + }; + }; + + sram@1F000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram", "simple-bus"; + reg = <0x1F000000 0x800000>; + ranges = <0x0 0x1F000000 0x7FFFFF>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + interrupt-parent = <&icu0>; + interrupts = <166 135 66>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + #clock-cells = <1>; + }; + + vmmc@107000 { + status = "disabled"; + compatible = "lantiq,vmmc"; + reg = <0x103000 0x400>; + interrupt-parent = <&icu0>; + interrupts = <150 151 152 153 154 155>; + }; + + rcu0: rcu@203000 { + compatible = "lantiq,rcu-xway"; + reg = <0x203000 0x1000>; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + }; + + gptu@E100A00 { + compatible = "lantiq,gptu-xway"; + reg = <0xE100A00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <126 127 128 129 130 131>; + }; + + gpios: stp@E100BB0 { + #gpio-cells = <2>; + compatible = "lantiq,gpio-stp-xway"; + gpio-controller; + reg = <0xE100BB0 0x40>; + lantiq,shadow = <0xfff>; + lantiq,groups = <0x3>; + status = "disabled"; + }; + + asc0: serial@E100400 { + compatible = "lantiq,asc"; + reg = <0xE100400 0x400>; + interrupt-parent = <&icu0>; + interrupts = <104 105 106>; + status = "disabled"; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xway"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + }; + + asc1: serial@E100C00 { + compatible = "lantiq,asc"; + reg = <0xE100C00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + }; + + ifxhcd@E101000 { + compatible = "lantiq,ifxhcd-danube"; + reg = <0xE101000 0x1000 + 0xE120000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <62>; + status = "disabled"; + }; + + deu@E103100 { + compatible = "lantiq,deu-danube"; + reg = <0xE103100 0xf00>; + }; + + dma0: dma@E104100 { + compatible = "lantiq,dma-xway"; + reg = <0xE104100 0x800>; + }; + + ebu0: ebu@E105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xE105300 0x100>; + }; + + mei@E116000 { + compatible = "lantiq,mei-xway"; + interrupt-parent = <&icu0>; + interrupts = <63>; + }; + + etop@E180000 { + compatible = "lantiq,etop-xway"; + reg = <0xE180000 0x40000>; + interrupt-parent = <&icu0>; + interrupts = <73 78>; + mac-address = [ 00 11 22 33 44 55 ]; + }; + + ppe@E234000 { + compatible = "lantiq,ppe-danube"; + interrupt-parent = <&icu0>; + interrupts = <96>; + }; + + pci0: pci@E105400 { + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xE105400 0x400>; /* pci bridge */ + lantiq,bus-clock = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = <0x7000 0 0 1 &icu0 30 1>; + req-mask = <0x1>; + }; + }; + + adsl { + compatible = "lantiq,adsl-danube"; + }; +}; diff --git a/target/linux/lantiq/dts/vr9.dtsi b/target/linux/lantiq/dts/vr9.dtsi new file mode 100644 index 0000000..136483a --- /dev/null +++ b/target/linux/lantiq/dts/vr9.dtsi @@ -0,0 +1,193 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,xway", "lantiq,vr9"; + + cpus { + cpu@0 { + compatible = "mips,mips34Kc"; + }; + }; + + memory@0 { + device_type = "memory"; + }; + + biu@1F800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,biu", "simple-bus"; + reg = <0x1F800000 0x800000>; + ranges = <0x0 0x1F800000 0x7FFFFF>; + + icu0: icu@80200 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,icu"; + reg = <0x80200 0x28 + 0x80228 0x28 + 0x80250 0x28 + 0x80278 0x28 + 0x802a0 0x28>; + }; + + watchdog@803F0 { + compatible = "lantiq,wdt"; + reg = <0x803F0 0x10>; + }; + }; + + sram@1F000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,sram", "simple-bus"; + reg = <0x1F000000 0x800000>; + ranges = <0x0 0x1F000000 0x7FFFFF>; + + eiu0: eiu@101000 { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "lantiq,eiu-xway"; + reg = <0x101000 0x1000>; + interrupt-parent = <&icu0>; + interrupts = <166 135 66 40 41 42>; + }; + + pmu0: pmu@102000 { + compatible = "lantiq,pmu-xway"; + reg = <0x102000 0x1000>; + }; + + cgu0: cgu@103000 { + compatible = "lantiq,cgu-xway"; + reg = <0x103000 0x1000>; + }; + + dcdc@106a00 { + compatible = "lantiq,dcdc-xrx200"; + reg = <0x106a00 0x200>; + }; + + rcu0: rcu@203000 { + compatible = "lantiq,rcu-xrx200"; + reg = <0x203000 0x1000>; + /* irq for thermal sensor */ + interrupt-parent = <&icu0>; + interrupts = <115>; + }; + }; + + fpi@10000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "lantiq,fpi", "simple-bus"; + ranges = <0x0 0x10000000 0xEEFFFFF>; + reg = <0x10000000 0xEF00000>; + + localbus@0 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ + 1 0 0x4000000 0x4000010>; /* addsel1 */ + compatible = "lantiq,localbus", "simple-bus"; + }; + + gptu@E100A00 { + compatible = "lantiq,gptu-xway"; + reg = <0xE100A00 0x100>; + interrupt-parent = <&icu0>; + interrupts = <126 127 128 129 130 131>; + }; + + asc0: serial@E100400 { + compatible = "lantiq,asc"; + reg = <0xE100400 0x400>; + interrupt-parent = <&icu0>; + interrupts = <104 105 106>; + status = "disabled"; + }; + + gpio: pinmux@E100B10 { + compatible = "lantiq,pinctrl-xr9"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + }; + + asc1: serial@E100C00 { + compatible = "lantiq,asc"; + reg = <0xE100C00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; + }; + + deu@E103100 { + compatible = "lantiq,deu-xrx200"; + reg = <0xE103100 0xf00>; + }; + + dma0: dma@E104100 { + compatible = "lantiq,dma-xway"; + reg = <0xE104100 0x800>; + }; + + ebu0: ebu@E105300 { + compatible = "lantiq,ebu-xway"; + reg = <0xE105300 0x100>; + }; + + ifxhcd@E101000 { + status = "disabled"; + compatible = "lantiq,ifxhcd-xrx200", "lantiq,ifxhcd-xrx200-dwc2"; + reg = <0xE101000 0x1000 + 0xE120000 0x3f000>; + interrupt-parent = <&icu0>; + interrupts = <62 91>; + }; + + ifxhcd@E106000 { + status = "disabled"; + compatible = "lantiq,ifxhcd-xrx200-dwc2"; + reg = <0xE106000 0x1000>; + interrupt-parent = <&icu0>; + interrupts = <91>; + }; + + mei@E116000 { + compatible = "lantiq,mei-xrx200"; + reg = <0xE116000 0x9c>; + interrupt-parent = <&icu0>; + interrupts = <63>; + }; + + ppe@E234000 { + compatible = "lantiq,ppe-xrx200"; + interrupt-parent = <&icu0>; + interrupts = <96>; + }; + + pcie@d900000 { + interrupt-parent = <&icu0>; + interrupts = <161 144>; + compatible = "lantiq,pcie-xrx200"; + }; + + pci0: pci@E105400 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "lantiq,pci-xway"; + bus-range = <0x0 0x0>; + ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ + 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ + reg = <0x7000000 0x8000 /* config space */ + 0xE105400 0x400>; /* pci bridge */ + status = "disabled"; + }; + + }; + + vdsl { + compatible = "lantiq,vdsl-vrx200"; + }; +}; diff --git a/target/linux/lantiq/files/firmware/lantiq/vr9_phy11g_a1x.bin b/target/linux/lantiq/files/firmware/lantiq/vr9_phy11g_a1x.bin new file mode 100644 index 0000000..cdf3d30 Binary files /dev/null and b/target/linux/lantiq/files/firmware/lantiq/vr9_phy11g_a1x.bin differ diff --git a/target/linux/lantiq/files/firmware/lantiq/vr9_phy11g_a2x.bin b/target/linux/lantiq/files/firmware/lantiq/vr9_phy11g_a2x.bin new file mode 100644 index 0000000..44fc39e Binary files /dev/null and b/target/linux/lantiq/files/firmware/lantiq/vr9_phy11g_a2x.bin differ diff --git a/target/linux/lantiq/files/firmware/lantiq/vr9_phy22f_a1x.bin b/target/linux/lantiq/files/firmware/lantiq/vr9_phy22f_a1x.bin new file mode 100644 index 0000000..02b88a0 Binary files /dev/null and b/target/linux/lantiq/files/firmware/lantiq/vr9_phy22f_a1x.bin differ diff --git a/target/linux/lantiq/files/firmware/lantiq/vr9_phy22f_a2x.bin b/target/linux/lantiq/files/firmware/lantiq/vr9_phy22f_a2x.bin new file mode 100644 index 0000000..1fed6ad Binary files /dev/null and b/target/linux/lantiq/files/firmware/lantiq/vr9_phy22f_a2x.bin differ diff --git a/target/linux/lantiq/image/Makefile b/target/linux/lantiq/image/Makefile new file mode 100644 index 0000000..686cb6d --- /dev/null +++ b/target/linux/lantiq/image/Makefile @@ -0,0 +1,448 @@ +# +# Copyright (C) 2010-2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +# boards missing since devicetree update +#EASY50712 ARV3527P + +JFFS2_BLOCKSIZE = 64k 128k 256k + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +LOADER_MAKE := $(NO_TRACE_MAKE) -C lzma-loader KDIR=$(KDIR) + +define Image/BuildLoader/Template + -rm -rf $(KDIR)/lzma-loader + $(LOADER_MAKE) LOADER=loader$(2)-$(1).bin\ + LZMA_TEXT_START=0x80a00000 \ + LOADADDR=0x80002000 \ + LOADER_DATA="$(KDIR)/vmlinux$(2)-$(1).lzma" BOARD="$(1)" \ + compile loader.bin +endef + + +define CompressLzma + $(STAGING_DIR_HOST)/bin/lzma e $(1) $(2) +endef + +define PatchKernelLzma + cp $(KDIR)/vmlinux$(2) $(KDIR)/vmlinux$(2)-$(1) + $(LINUX_DIR)/scripts/dtc/dtc -O dtb -o $(KDIR)/$(1).dtb ../dts/$(1).dts + $(STAGING_DIR_HOST)/bin/patch-dtb $(KDIR)/vmlinux$(2)-$(1) $(KDIR)/$(1).dtb + $(call CompressLzma,$(KDIR)/vmlinux$(2)-$(1),$(KDIR)/vmlinux$(2)-$(1).lzma) +endef + +define MkBrnImage + mkbrncmdline -i $(KDIR)/vmlinux-$(5) -o $(KDIR)/vmlinux-$(5)-brn BRN-BOOT $(7) + $(call CompressLzma,$(KDIR)/vmlinux-$(5)-brn,$(KDIR)/vmlinux-$(5)-brn.lzma) + mkbrnimg -s $(1) -m $(2) -p $(3) -o $(4) $(KDIR)/vmlinux-$(5)-brn.lzma $(KDIR)/root.$(6) +endef + +define MkImageLzma + mkimage -A mips -O linux -T kernel -a 0x80002000 -C lzma \ + -e 0x80002000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(KDIR)/vmlinux$(2)-$(1).lzma $(KDIR)/uImage-$(1)$(2) +endef + +define TPLinkImageLzma + mktplinkfw2 -c -B $(2) -s \ + -k $(KDIR)/vmlinux$(3)-$(1).lzma -o $(KDIR)/uImage-$(1)$(3) +endef + +define MkImageEVA + lzma2eva 0x80002000 0x80002000 $(KDIR)/vmlinux$(2)-$(1).lzma $(KDIR)/$(1)$(2).eva.prealign + dd if=$(KDIR)/$(1)$(2).eva.prealign of=$(KDIR)/$(1)$(2).eva.align.64k bs=64k conv=sync + dd if=$(KDIR)/$(1)$(2).eva.prealign of=$(KDIR)/$(1)$(2).eva.align.128k bs=128k conv=sync + cat ./eva.dummy.squashfs >> $(KDIR)/$(1)$(2).eva.align.64k +endef + +define Image/Build/squashfs + cat $(KDIR)/uImage-$(2) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image + $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image) + $(if $(3),$(call MkBrnImage,$(3),$(4),$(5),$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(3)-brnImage,$(2),$(1),$(6))) +endef + +define Image/BuildNAND/squashfs + +ifneq ($($(PROFILE)_UBI_OPTS),) + $(call prepare_generic_squashfs,$(KDIR)/root.$(1)) + $(call Image/Build/UbinizeImage,$(PROFILE),,squashfs,$($(PROFILE)_UBI_OPTS)) + $(call Image/Build/SysupgradeNAND,$(PROFILE),$(1),$(KDIR)/uImage-$(PROFILE)) +endif +endef + +DGN3500_SKERNEL=0x50000 +DGN3500_SKERNEL_DECIMAL=327680 +define Image/BuildDGN3500/squashfs + dd if=/dev/zero of=$(BIN_DIR)/$(IMG_PREFIX)-pad bs=$(DGN3500_SKERNEL_DECIMAL) count=1 + cat $(BIN_DIR)/$(IMG_PREFIX)-pad $(KDIR)/uImage-$(2) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img + rm -r $(BIN_DIR)/$(IMG_PREFIX)-pad + dd if=/dev/zero ibs=16M count=1 | tr "\000" "\377" > $(BIN_DIR)/$(IMG_PREFIX)-pwf + cp $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadNA.img + dgn3500sum $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadNA.img $(DGN3500_SKERNEL) NA + $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadNA.img) + cp $(BIN_DIR)/$(IMG_PREFIX)-pwf $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-NA.img + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadNA.img of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-NA.img conv=notrunc + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadNA.img of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-sysupgrade-NA.image bs=$(DGN3500_SKERNEL_DECIMAL) skip=1 + rm -r $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadNA.img + mv $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadWW.img + dgn3500sum $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadWW.img $(DGN3500_SKERNEL) WW + $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadWW.img) + mv $(BIN_DIR)/$(IMG_PREFIX)-pwf $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-WW.img + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadWW.img of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-WW.img conv=notrunc + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadWW.img of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-sysupgrade-WW.image bs=$(DGN3500_SKERNEL_DECIMAL) skip=1 + rm -r $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepadWW.img +endef + +define Image/BuildDGN3500B/squashfs + dd if=/dev/zero of=$(BIN_DIR)/$(IMG_PREFIX)-pad bs=327680 count=1 + cat $(BIN_DIR)/$(IMG_PREFIX)-pad $(KDIR)/uImage-$(2) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img + rm -r $(BIN_DIR)/$(IMG_PREFIX)-pad + dd if=/dev/zero ibs=16M count=1 | tr "\000" "\377" > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory.img + dgn3500sum $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img $(DGN3500_SKERNEL) DE + $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img) + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory.img conv=notrunc + dd if=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img of=$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-sysupgrade.image bs=$(DGN3500_SKERNEL_DECIMAL) skip=1 + rm -r $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-factory-prepad.img + dgn3500sum $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1)-sysupgrade.image $(DGN3500_SKERNEL) DE +endef + + +define Image/BuildTPLink/squashfs + mktplinkfw2 -B $(3) -s -a 0x4 -j \ + -k $(KDIR)/vmlinux-$(2).lzma -r $(KDIR)/root.$(1) \ + -o $(BIN_DIR)/$(IMG_PREFIX)-$(2)-sysupgrade.image +endef + +define Image/BuildEVA/squashfs + cat $(KDIR)/$(2).eva.align.64k $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image.eva + $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image.eva) +endef + +define Image/BuildEVA/ubifs + +ifneq ($($(PROFILE)_UBIFS_OPTS),) + $(CP) $(KDIR)/root.ubifs $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-rootfs.ubifs +endif +endef + +define Image/BuildEVA/ubi + +ifneq ($($(PROFILE)_UBI_OPTS),) + $(CP) $(KDIR)/root.ubi $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-rootfs.ubi + $(CP) $(KDIR)/root-overlay.ubi $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-rootfs-overlay.ubi +endif +endef + +define Image/BuildLoader/squashfs + dd if=$(KDIR)/loader-$(2).bin of=$(KDIR)/loader-$(2).bin.padded bs=3072k conv=sync + cat $(KDIR)/loader-$(2).bin.padded $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image + $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image) +endef + +define Image/BuildEVA/jffs2-128k + cat $(KDIR)/$(2).eva.align.128k $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image.eva +endef + +define Image/Build/jffs2-64k + dd if=$(KDIR)/uImage-$(2) of=$(KDIR)/uImage-$(2)-$(1) bs=64k conv=sync + cat $(KDIR)/uImage-$(2)-$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image +endef + +define Image/Build/jffs2-128k + dd if=$(KDIR)/uImage-$(2) of=$(KDIR)/uImage-$(2)-$(1) bs=128k conv=sync + cat $(KDIR)/uImage-$(2)-$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image +endef + +define Image/Build/jffs2-256k + dd if=$(KDIR)/uImage-$(2) of=$(KDIR)/uImage-$(2)-$(1) bs=256k conv=sync + cat $(KDIR)/uImage-$(2)-$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image +endef + +define Image/Build/ubifs + +ifneq ($($(PROFILE)_UBIFS_OPTS),) + $(CP) $(KDIR)/root.ubifs $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-rootfs.ubifs +endif +endef + +define Image/Build/ubi + +ifneq ($($(PROFILE)_UBI_OPTS),) + $(CP) $(KDIR)/root.ubi $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-rootfs.ubi + $(CP) $(KDIR)/root-overlay.ubi $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-rootfs-overlay.ubi +endif +endef + + +define Image/BuildNAND/ubifs + +ifneq ($($(PROFILE)_UBIFS_OPTS),) +ifneq ($($(PROFILE)_UBI_OPTS),) + $(call Image/Build/UbinizeImage,$(PROFILE),,ubifs,$($(PROFILE)_UBI_OPTS)) + $(call Image/Build/SysupgradeNAND,$(PROFILE),$(1),$(KDIR)/uImage-$(PROFILE)) +endif +endif +endef + + +define Image/InstallKernel/Template + +ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_KERNEL),) + $(INSTALL_DIR) $(TARGET_DIR)/boot + +ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_UIMAGE),) + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage $(TARGET_DIR)/boot/ + ln -sf $(IMG_PREFIX)-$(1)-uImage $(TARGET_DIR)/boot/uImage +endif + +ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_ZIMAGE),) + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-zImage $(TARGET_DIR)/boot/ + ln -sf $(IMG_PREFIX)-$(1)-zImage $(TARGET_DIR)/boot/zImage +endif +endif + +ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB),) + $(INSTALL_DIR) $(TARGET_DIR)/boot + +ifneq ($(1),) + $(CP) $(KDIR)/$(1).dtb $(TARGET_DIR)/boot/ +endif +endif +endef + +define Image/BuildKernel/Template + $(call PatchKernelLzma,$(1)) + $(call MkImageLzma,$(1)) + $(CP) $(KDIR)/uImage-$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call PatchKernelLzma,$(1),-initramfs) + $(call MkImageLzma,$(1),-initramfs) + $(CP) $(KDIR)/uImage-$(1)-initramfs $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage-initramfs +endif +endef + +define Image/BuildKernelLoader/Template + $(CP) $(KDIR)/loader-$(1).bin $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux-loader + $(CP) $(KDIR)/vmlinux-$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(CP) $(KDIR)/loader-initramfs-$(1).bin $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux-initramfs-loader + $(CP) $(KDIR)/vmlinux-initramfs-$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux-initramfs +endif +endef + +define Image/Prepare/Profile + $(call PatchKernelLzma,$(1)) + $(call Image/BuildLoader/Template,$(1)) +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call PatchKernelLzma,$(1),-initramfs) + $(call Image/BuildLoader/Template,$(1),-initramfs) +endif +endef + +define Image/BuildKernelTPLink/Template + $(call PatchKernelLzma,$(1)) + $(call TPLinkImageLzma,$(1),$(2)) + $(CP) $(KDIR)/uImage-$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call PatchKernelLzma,$(1),-initramfs) + $(call TPLinkImageLzma,$(1),$(2),-initramfs) + $(CP) $(KDIR)/uImage-$(1)-initramfs $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage-initramfs +endif +endef + +define Image/BuildKernelEVA/Template + $(call PatchKernelLzma,$(1)) + $(call MkImageEVA,$(1)) + $(CP) $(KDIR)/$(1).eva.align.64k $(BIN_DIR)/$(IMG_PREFIX)-$(1).eva.align.64k + $(CP) $(KDIR)/$(1).eva.align.128k $(BIN_DIR)/$(IMG_PREFIX)-$(1).eva.align.128k +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call PatchKernelLzma,$(1),-initramfs) + $(call MkImageEVA,$(1),-initramfs) + $(CP) $(KDIR)/$(1)-initramfs.eva.align.64k $(BIN_DIR)/$(IMG_PREFIX)-$(1)-initramfs.eva.align.64k + $(CP) $(KDIR)/$(1)-initramfs.eva.align.128k $(BIN_DIR)/$(IMG_PREFIX)-$(1)-initramfs.eva.align.128k +endif +endef + + +ifeq ($(CONFIG_TARGET_lantiq_falcon),y) + +Image/BuildKernel/Profile/EASY98000NOR=$(call Image/BuildKernel/Template,EASY98000NOR) +Image/Build/Profile/EASY98000NOR=$(call Image/Build/$(1),$(1),EASY98000NOR) + +Image/BuildKernel/Profile/EASY98000SFLASH=$(call Image/BuildKernel/Template,EASY98000SFLASH) +Image/Build/Profile/EASY98000SFLASH=$(call Image/Build/$(1),$(1),EASY98000SFLASH) + +endif + + +ifeq ($(CONFIG_TARGET_lantiq_ase),y) + +Image/BuildKernel/Profile/DGN1000B=$(call Image/BuildKernel/Template,DGN1000B) +Image/Build/Profile/DGN1000B=$(call Image/Build/$(1),$(1),DGN1000B) + +endif + + +ifeq ($(CONFIG_TARGET_lantiq_xway),y) + +# Danube +Image/BuildKernel/Profile/BTHOMEHUBV2B=$(call Image/BuildKernel/Template,BTHOMEHUBV2B) +Image/Build/Profile/BTHOMEHUBV2B=$(call Image/BuildNAND/$(1),$(1),BTHOMEHUBV2B) + +Image/BuildKernel/Profile/EASY50712=$(call Image/BuildKernel/Template,EASY50712) +Image/Build/Profile/EASY50712=$(call Image/Build/$(1),$(1),EASY50712) + +Image/BuildKernel/Profile/ACMP252=$(call Image/BuildKernel/Template,ACMP252) +Image/Build/Profile/ACMP252=$(call Image/Build/$(1),$(1),ACMP252) + +Image/BuildKernel/Profile/ARV4510PW=$(call Image/BuildKernel/Template,ARV4510PW) +Image/Build/Profile/ARV4510PW=$(call Image/Build/$(1),$(1),ARV4510PW) + +Image/BuildKernel/Profile/ARV4525PW=$(call Image/BuildKernel/Template,ARV4525PW) +Image/Build/Profile/ARV4525PW=$(call Image/Build/$(1),$(1),ARV4525PW) + +Image/BuildKernel/Profile/ARV7525PW=$(call Image/BuildKernel/Template,ARV7525PW) +Image/Build/Profile/ARV7525PW=$(call Image/Build/$(1),$(1),ARV7525PW) + +Image/BuildKernel/Profile/ARV4518PWR01=$(call Image/BuildKernel/Template,ARV4518PWR01) +Image/Build/Profile/ARV4518PWR01=$(call Image/Build/$(1),$(1),ARV4518PWR01) + +Image/BuildKernel/Profile/ARV4518PWR01A=$(call Image/BuildKernel/Template,ARV4518PWR01A) +Image/Build/Profile/ARV4518PWR01A=$(call Image/Build/$(1),$(1),ARV4518PWR01A) + +Image/BuildKernel/Profile/ARV4519PW=$(call Image/BuildKernel/Template,ARV4519PW) +Image/Build/Profile/ARV4519PW=$(call Image/Build/$(1),$(1),ARV4519PW) + +Image/BuildKernel/Profile/ARV4520PW=$(call Image/BuildKernel/Template,ARV4520PW) +Image/Build/Profile/ARV4520PW=$(call Image/Build/$(1),$(1),ARV4520PW) + +Image/BuildKernel/Profile/ARV452CQW=$(call Image/BuildKernel/Template,ARV452CQW) +Image/Build/Profile/ARV452CQW=$(call Image/Build/$(1),$(1),ARV452CQW) + +Image/BuildKernel/Profile/ARV7510PW22=$(call Image/BuildKernel/Template,ARV7510PW22) +Image/Build/Profile/ARV7510PW22=$(call Image/Build/$(1),$(1),ARV7510PW22) + +Image/BuildKernel/Profile/ARV7518PW=$(call Image/BuildKernel/Template,ARV7518PW) +Image/Build/Profile/ARV7518PW=$(call Image/Build/$(1),$(1),ARV7518PW) + +Image/BuildKernel/Profile/ARV7519PW=$(call Image/BuildKernel/Template,ARV7519PW) +Image/Build/Profile/ARV7519PW=$(call Image/Build/$(1),$(1),ARV7519PW) + +Image/BuildKernel/Profile/ARV752DPW=$(call Image/BuildKernel/Template,ARV752DPW) +Image/Build/Profile/ARV752DPW=$(call Image/Build/$(1),$(1),ARV752DPW) + +Image/BuildKernel/Profile/ARV752DPW22=$(call Image/BuildKernel/Template,ARV752DPW22) +Image/Build/Profile/ARV752DPW22=$(call Image/Build/$(1),$(1),ARV752DPW22) + +Image/BuildKernel/Profile/ARV8539PW22=$(call Image/BuildKernel/Template,ARV8539PW22) +Image/Build/Profile/ARV8539PW22=$(call Image/Build/$(1),$(1),ARV8539PW22) + +Image/BuildKernel/Profile/GIGASX76X=$(call Image/BuildKernel/Template,GIGASX76X) +Image/Build/Profile/GIGASX76X=$(call Image/Build/$(1),$(1),GIGASX76X) + + +# AR9 +Image/BuildKernel/Profile/BTHOMEHUBV3A=$(call Image/BuildKernel/Template,BTHOMEHUBV3A) +Image/Build/Profile/BTHOMEHUBV3A=$(call Image/BuildNAND/$(1),$(1),BTHOMEHUBV3A) + +Image/BuildKernel/Profile/DGN3500=$(call Image/BuildKernel/Template,DGN3500) +Image/Build/Profile/DGN3500=$(call Image/BuildDGN3500/$(1),$(1),DGN3500) + +Image/BuildKernel/Profile/DGN3500B=$(call Image/BuildKernel/Template,DGN3500B) +Image/Build/Profile/DGN3500B=$(call Image/BuildDGN3500B/$(1),$(1),DGN3500B) + +Image/BuildKernel/Profile/WBMRA=$(call Image/BuildKernel/Template,WBMR) +Image/Build/Profile/WBMRA=$(call Image/Build/$(1),$(1),WBMR) + +Image/BuildKernel/Profile/WBMRB=$(call Image/BuildKernel/Template,WBMR) +Image/Build/Profile/WBMRB=$(call Image/Build/$(1),$(1),WBMR) + +Image/BuildKernel/Profile/FRITZ7320=$(call Image/BuildKernelEVA/Template,FRITZ7320) +Image/Build/Profile/FRITZ7320=$(call Image/BuildEVA/$(1),$(1),FRITZ7320) + +Image/BuildKernel/Profile/GR7000=$(call Image/BuildKernel/Template,GR7000) +Image/Build/Profile/GR7000=$(call Image/Build/$(1),$(1),GR7000) + +Image/BuildKernel/Profile/H201L=$(call Image/BuildKernel/Template,H201L) +Image/Build/Profile/H201L=$(call Image/Build/$(1),$(1),H201L) + +Image/BuildKernel/Profile/P2601HNFX=$(call Image/BuildKernel/Template,P2601HNFX) +Image/Build/Profile/P2601HNFX=$(call Image/Build/$(1),$(1),P2601HNFX) + +endif + + +ifeq ($(CONFIG_TARGET_lantiq_xrx200),y) + +# VR9 +Image/BuildKernel/Profile/P2812HNUF1=$(call Image/BuildKernel/Template,P2812HNUF1) +Image/Build/Profile/P2812HNUF1=$(call Image/BuildNAND/$(1),$(1),P2812HNUF1) + +Image/BuildKernel/Profile/P2812HNUF3=$(call Image/BuildKernel/Template,P2812HNUF3) +Image/Build/Profile/P2812HNUF3=$(call Image/BuildNAND/$(1),$(1),P2812HNUF3) + +Image/BuildKernel/Profile/ARV7519RW22=$(call Image/BuildKernel/Template,ARV7519RW22,$(1)) +Image/Build/Profile/ARV7519RW22=$(call Image/Build/$(1),$(1),ARV7519RW22) + +Image/BuildKernel/Profile/BTHOMEHUBV5A=$(call Image/BuildKernel/Template,BTHOMEHUBV5A) +Image/Build/Profile/BTHOMEHUBV5A=$(call Image/BuildNAND/$(1),$(1),BTHOMEHUBV5A) + +Image/BuildKernel/Profile/EASY80920NAND=$(call Image/BuildKernel/Template,EASY80920NAND) +Image/Build/Profile/EASY80920NAND=$(call Image/Build/$(1),$(1),EASY80920NAND) + +Image/BuildKernel/Profile/EASY80920NOR=$(call Image/BuildKernel/Template,EASY80920NOR) +Image/Build/Profile/EASY80920NOR=$(call Image/Build/$(1),$(1),EASY80920NOR) + +Image/BuildKernel/Profile/FRITZ3370=$(call Image/BuildKernelEVA/Template,FRITZ3370) +Image/Build/Profile/FRITZ3370=$(call Image/BuildEVA/$(1),$(1),FRITZ3370) + +Image/BuildKernel/Profile/VG3503J=$(call Image/BuildKernelLoader/Template,VG3503J) +Image/Build/Profile/VG3503J=$(call Image/BuildLoader/$(1),$(1),VG3503J) + +Image/BuildKernel/Profile/VG3503J_V2=$(call Image/BuildKernelLoader/Template,VG3503J_V2) +Image/Build/Profile/VG3503J_V2=$(call Image/BuildLoader/$(1),$(1),VG3503J_V2) + +Image/BuildKernel/Profile/TDW8970=$(call Image/BuildKernelTPLink/Template,TDW8970,TD-W8970v1,$(1)) +Image/Build/Profile/TDW8970=$(call Image/BuildTPLink/$(1),$(1),TDW8970,TD-W8970v1) + +Image/BuildKernel/Profile/TDW8980=$(call Image/BuildKernelTPLink/Template,TDW8980,TD-W8980v1,$(1)) +Image/Build/Profile/TDW8980=$(call Image/BuildTPLink/$(1),$(1),TDW8980,TD-W8980v1) + +Image/BuildKernel/Profile/VGV7510KW22NOR=$(call Image/BuildKernel/Template,VGV7510KW22NOR,$(1)) +Image/Build/Profile/VGV7510KW22NOR=$(call Image/Build/$(1),$(1),VGV7510KW22NOR) + +Image/BuildKernel/Profile/VGV7510KW22BRN=$(call Image/BuildKernel/Template,VGV7510KW22BRN,$(1)) +Image/Build/Profile/VGV7510KW22BRN=$(call Image/Build/$(1),$(1),VGV7510KW22BRN,5BRNDA6431,0x12345678,0x04c11db7,$(1)) + +Image/BuildKernel/Profile/VGV7519NOR=$(call Image/BuildKernel/Template,VGV7519NOR,$(1)) +Image/Build/Profile/VGV7519NOR=$(call Image/Build/$(1),$(1),VGV7519NOR) + +Image/BuildKernel/Profile/VGV7519BRN=$(call Image/BuildKernel/Template,VGV7519BRN,$(1)) +Image/Build/Profile/VGV7519BRN=$(call Image/Build/$(1),$(1),VGV7519BRN,5D00008000,0x12345678,0x2083b8ed,$(1)) + +define Image/Prepare + $(call Image/Prepare/Profile,VG3503J) + $(call Image/Prepare/Profile,VG3503J_V2) +endef + +endif + + +define Image/BuildKernel + $(call Image/BuildKernel/Profile/$(PROFILE)) +endef + +define Image/InstallKernel + $(call Image/InstallKernel/Template/$(PROFILE)) +endef + +define Image/Build + $(call Image/Build/Profile/$(PROFILE),$(1)) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/lantiq/image/eva.dummy.squashfs b/target/linux/lantiq/image/eva.dummy.squashfs new file mode 100644 index 0000000..71c688c Binary files /dev/null and b/target/linux/lantiq/image/eva.dummy.squashfs differ diff --git a/target/linux/lantiq/image/lzma-loader/Makefile b/target/linux/lantiq/image/lzma-loader/Makefile new file mode 100644 index 0000000..ab6640a --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/Makefile @@ -0,0 +1,65 @@ +# +# Copyright (C) 2011 OpenWrt.org +# Copyright (C) 2011 Gabor Juhos +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +LZMA_TEXT_START := 0x80a00000 +LOADER := loader.bin +LOADER_NAME := $(basename $(notdir $(LOADER))) +LOADER_DATA := +TARGET_DIR := +FLASH_OFFS := +FLASH_MAX := +BOARD := + +ifeq ($(TARGET_DIR),) +TARGET_DIR := $(KDIR) +endif + +LOADER_BIN := $(TARGET_DIR)/$(LOADER_NAME).bin +LOADER_GZ := $(TARGET_DIR)/$(LOADER_NAME).gz +LOADER_ELF := $(TARGET_DIR)/$(LOADER_NAME).elf + +PKG_NAME := lzma-loader +PKG_BUILD_DIR := $(KDIR)/$(PKG_NAME) + +.PHONY : loader-compile loader.bin loader.elf loader.gz + +$(PKG_BUILD_DIR)/.prepared: + mkdir $(PKG_BUILD_DIR) + $(CP) ./src/* $(PKG_BUILD_DIR)/ + touch $@ + +loader-compile: $(PKG_BUILD_DIR)/.prepared + $(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE="$(TARGET_CROSS)" \ + LZMA_TEXT_START=$(LZMA_TEXT_START) \ + LOADER_DATA=$(LOADER_DATA) \ + FLASH_OFFS=$(FLASH_OFFS) \ + FLASH_MAX=$(FLASH_MAX) \ + BOARD="$(BOARD)" \ + PLATFORM="lantiq" \ + clean all + +loader.gz: $(PKG_BUILD_DIR)/loader.bin + gzip -nc9 $< > $(LOADER_GZ) + +loader.elf: $(PKG_BUILD_DIR)/loader.elf + $(CP) $< $(LOADER_ELF) + +loader.bin: $(PKG_BUILD_DIR)/loader.bin + $(CP) $< $(LOADER_BIN) + +download: +prepare: $(PKG_BUILD_DIR)/.prepared +compile: loader-compile + +install: + +clean: + rm -rf $(PKG_BUILD_DIR) + diff --git a/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.c b/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.c new file mode 100644 index 0000000..cb83453 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.c @@ -0,0 +1,584 @@ +/* + LzmaDecode.c + LZMA Decoder (optimized for Speed version) + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this Code, expressly permits you to + statically or dynamically link your Code (or bind by name) to the + interfaces of this file without subjecting your linked Code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#include "LzmaDecode.h" + +#define kNumTopBits 24 +#define kTopValue ((UInt32)1 << kNumTopBits) + +#define kNumBitModelTotalBits 11 +#define kBitModelTotal (1 << kNumBitModelTotalBits) +#define kNumMoveBits 5 + +#define RC_READ_BYTE (*Buffer++) + +#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ + { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} + +#ifdef _LZMA_IN_CB + +#define RC_TEST { if (Buffer == BufferLim) \ + { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \ + BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }} + +#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 + +#else + +#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; } + +#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 + +#endif + +#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } + +#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) +#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; +#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; + +#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ + { UpdateBit0(p); mi <<= 1; A0; } else \ + { UpdateBit1(p); mi = (mi + mi) + 1; A1; } + +#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) + +#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ + { int i = numLevels; res = 1; \ + do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ + res -= (1 << numLevels); } + + +#define kNumPosBitsMax 4 +#define kNumPosStatesMax (1 << kNumPosBitsMax) + +#define kLenNumLowBits 3 +#define kLenNumLowSymbols (1 << kLenNumLowBits) +#define kLenNumMidBits 3 +#define kLenNumMidSymbols (1 << kLenNumMidBits) +#define kLenNumHighBits 8 +#define kLenNumHighSymbols (1 << kLenNumHighBits) + +#define LenChoice 0 +#define LenChoice2 (LenChoice + 1) +#define LenLow (LenChoice2 + 1) +#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) +#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) +#define kNumLenProbs (LenHigh + kLenNumHighSymbols) + + +#define kNumStates 12 +#define kNumLitStates 7 + +#define kStartPosModelIndex 4 +#define kEndPosModelIndex 14 +#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) + +#define kNumPosSlotBits 6 +#define kNumLenToPosStates 4 + +#define kNumAlignBits 4 +#define kAlignTableSize (1 << kNumAlignBits) + +#define kMatchMinLen 2 + +#define IsMatch 0 +#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) +#define IsRepG0 (IsRep + kNumStates) +#define IsRepG1 (IsRepG0 + kNumStates) +#define IsRepG2 (IsRepG1 + kNumStates) +#define IsRep0Long (IsRepG2 + kNumStates) +#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) +#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) +#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) +#define LenCoder (Align + kAlignTableSize) +#define RepLenCoder (LenCoder + kNumLenProbs) +#define Literal (RepLenCoder + kNumLenProbs) + +#if Literal != LZMA_BASE_SIZE +StopCompilingDueBUG +#endif + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) +{ + unsigned char prop0; + if (size < LZMA_PROPERTIES_SIZE) + return LZMA_RESULT_DATA_ERROR; + prop0 = propsData[0]; + if (prop0 >= (9 * 5 * 5)) + return LZMA_RESULT_DATA_ERROR; + { + for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); + for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); + propsRes->lc = prop0; + /* + unsigned char remainder = (unsigned char)(prop0 / 9); + propsRes->lc = prop0 % 9; + propsRes->pb = remainder / 5; + propsRes->lp = remainder % 5; + */ + } + + #ifdef _LZMA_OUT_READ + { + int i; + propsRes->DictionarySize = 0; + for (i = 0; i < 4; i++) + propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); + if (propsRes->DictionarySize == 0) + propsRes->DictionarySize = 1; + } + #endif + return LZMA_RESULT_OK; +} + +#define kLzmaStreamWasFinishedId (-1) + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *InCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) +{ + CProb *p = vs->Probs; + SizeT nowPos = 0; + Byte previousByte = 0; + UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; + UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; + int lc = vs->Properties.lc; + + #ifdef _LZMA_OUT_READ + + UInt32 Range = vs->Range; + UInt32 Code = vs->Code; + #ifdef _LZMA_IN_CB + const Byte *Buffer = vs->Buffer; + const Byte *BufferLim = vs->BufferLim; + #else + const Byte *Buffer = inStream; + const Byte *BufferLim = inStream + inSize; + #endif + int state = vs->State; + UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; + int len = vs->RemainLen; + UInt32 globalPos = vs->GlobalPos; + UInt32 distanceLimit = vs->DistanceLimit; + + Byte *dictionary = vs->Dictionary; + UInt32 dictionarySize = vs->Properties.DictionarySize; + UInt32 dictionaryPos = vs->DictionaryPos; + + Byte tempDictionary[4]; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + if (len == kLzmaStreamWasFinishedId) + return LZMA_RESULT_OK; + + if (dictionarySize == 0) + { + dictionary = tempDictionary; + dictionarySize = 1; + tempDictionary[0] = vs->TempDictionary[0]; + } + + if (len == kLzmaNeedInitId) + { + { + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + UInt32 i; + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + rep0 = rep1 = rep2 = rep3 = 1; + state = 0; + globalPos = 0; + distanceLimit = 0; + dictionaryPos = 0; + dictionary[dictionarySize - 1] = 0; + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + } + len = 0; + } + while(len != 0 && nowPos < outSize) + { + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + len--; + } + if (dictionaryPos == 0) + previousByte = dictionary[dictionarySize - 1]; + else + previousByte = dictionary[dictionaryPos - 1]; + + #else /* if !_LZMA_OUT_READ */ + + int state = 0; + UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; + int len = 0; + const Byte *Buffer; + const Byte *BufferLim; + UInt32 Range; + UInt32 Code; + + #ifndef _LZMA_IN_CB + *inSizeProcessed = 0; + #endif + *outSizeProcessed = 0; + + { + UInt32 i; + UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); + for (i = 0; i < numProbs; i++) + p[i] = kBitModelTotal >> 1; + } + + #ifdef _LZMA_IN_CB + RC_INIT; + #else + RC_INIT(inStream, inSize); + #endif + + #endif /* _LZMA_OUT_READ */ + + while(nowPos < outSize) + { + CProb *prob; + UInt32 bound; + int posState = (int)( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & posStateMask); + + prob = p + IsMatch + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + int symbol = 1; + UpdateBit0(prob) + prob = p + Literal + (LZMA_LIT_SIZE * + ((( + (nowPos + #ifdef _LZMA_OUT_READ + + globalPos + #endif + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + + if (state >= kNumLitStates) + { + int matchByte; + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + matchByte = dictionary[pos]; + #else + matchByte = outStream[nowPos - rep0]; + #endif + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); + } + while (symbol < 0x100) + { + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) + } + previousByte = (Byte)symbol; + + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #endif + if (state < 4) state = 0; + else if (state < 10) state -= 3; + else state -= 6; + } + else + { + UpdateBit1(prob); + prob = p + IsRep + state; + IfBit0(prob) + { + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + #ifdef _LZMA_OUT_READ + UInt32 pos; + #endif + UpdateBit0(prob); + + #ifdef _LZMA_OUT_READ + if (distanceLimit == 0) + #else + if (nowPos == 0) + #endif + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + #ifdef _LZMA_OUT_READ + pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + outStream[nowPos++] = previousByte; + #ifdef _LZMA_OUT_READ + if (distanceLimit < dictionarySize) + distanceLimit++; + #endif + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; + } + { + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; + } + + if (state < 4) + { + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } + } + + len += kMatchMinLen; + #ifdef _LZMA_OUT_READ + if (rep0 > distanceLimit) + #else + if (rep0 > nowPos) + #endif + return LZMA_RESULT_DATA_ERROR; + + #ifdef _LZMA_OUT_READ + if (dictionarySize - distanceLimit > (UInt32)len) + distanceLimit += len; + else + distanceLimit = dictionarySize; + #endif + + do + { + #ifdef _LZMA_OUT_READ + UInt32 pos = dictionaryPos - rep0; + if (pos >= dictionarySize) + pos += dictionarySize; + previousByte = dictionary[pos]; + dictionary[dictionaryPos] = previousByte; + if (++dictionaryPos == dictionarySize) + dictionaryPos = 0; + #else + previousByte = outStream[nowPos - rep0]; + #endif + len--; + outStream[nowPos++] = previousByte; + } + while(len != 0 && nowPos < outSize); + } + } + RC_NORMALIZE; + + #ifdef _LZMA_OUT_READ + vs->Range = Range; + vs->Code = Code; + vs->DictionaryPos = dictionaryPos; + vs->GlobalPos = globalPos + (UInt32)nowPos; + vs->DistanceLimit = distanceLimit; + vs->Reps[0] = rep0; + vs->Reps[1] = rep1; + vs->Reps[2] = rep2; + vs->Reps[3] = rep3; + vs->State = state; + vs->RemainLen = len; + vs->TempDictionary[0] = tempDictionary[0]; + #endif + + #ifdef _LZMA_IN_CB + vs->Buffer = Buffer; + vs->BufferLim = BufferLim; + #else + *inSizeProcessed = (SizeT)(Buffer - inStream); + #endif + *outSizeProcessed = nowPos; + return LZMA_RESULT_OK; +} diff --git a/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.h b/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.h new file mode 100644 index 0000000..2870eeb --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/LzmaDecode.h @@ -0,0 +1,113 @@ +/* + LzmaDecode.h + LZMA Decoder interface + + LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) + http://www.7-zip.org/ + + LZMA SDK is licensed under two licenses: + 1) GNU Lesser General Public License (GNU LGPL) + 2) Common Public License (CPL) + It means that you can select one of these two licenses and + follow rules of that license. + + SPECIAL EXCEPTION: + Igor Pavlov, as the author of this code, expressly permits you to + statically or dynamically link your code (or bind by name) to the + interfaces of this file without subjecting your linked code to the + terms of the CPL or GNU LGPL. Any modifications or additions + to this file, however, are subject to the LGPL or CPL terms. +*/ + +#ifndef __LZMADECODE_H +#define __LZMADECODE_H + +#include "LzmaTypes.h" + +/* #define _LZMA_IN_CB */ +/* Use callback for input data */ + +/* #define _LZMA_OUT_READ */ +/* Use read function for output data */ + +/* #define _LZMA_PROB32 */ +/* It can increase speed on some 32-bit CPUs, + but memory usage will be doubled in that case */ + +/* #define _LZMA_LOC_OPT */ +/* Enable local speed optimizations inside code */ + +#ifdef _LZMA_PROB32 +#define CProb UInt32 +#else +#define CProb UInt16 +#endif + +#define LZMA_RESULT_OK 0 +#define LZMA_RESULT_DATA_ERROR 1 + +#ifdef _LZMA_IN_CB +typedef struct _ILzmaInCallback +{ + int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); +} ILzmaInCallback; +#endif + +#define LZMA_BASE_SIZE 1846 +#define LZMA_LIT_SIZE 768 + +#define LZMA_PROPERTIES_SIZE 5 + +typedef struct _CLzmaProperties +{ + int lc; + int lp; + int pb; + #ifdef _LZMA_OUT_READ + UInt32 DictionarySize; + #endif +}CLzmaProperties; + +int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); + +#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) + +#define kLzmaNeedInitId (-2) + +typedef struct _CLzmaDecoderState +{ + CLzmaProperties Properties; + CProb *Probs; + + #ifdef _LZMA_IN_CB + const unsigned char *Buffer; + const unsigned char *BufferLim; + #endif + + #ifdef _LZMA_OUT_READ + unsigned char *Dictionary; + UInt32 Range; + UInt32 Code; + UInt32 DictionaryPos; + UInt32 GlobalPos; + UInt32 DistanceLimit; + UInt32 Reps[4]; + int State; + int RemainLen; + unsigned char TempDictionary[4]; + #endif +} CLzmaDecoderState; + +#ifdef _LZMA_OUT_READ +#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } +#endif + +int LzmaDecode(CLzmaDecoderState *vs, + #ifdef _LZMA_IN_CB + ILzmaInCallback *inCallback, + #else + const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, + #endif + unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); + +#endif diff --git a/target/linux/lantiq/image/lzma-loader/src/LzmaTypes.h b/target/linux/lantiq/image/lzma-loader/src/LzmaTypes.h new file mode 100644 index 0000000..9c27290 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/LzmaTypes.h @@ -0,0 +1,45 @@ +/* +LzmaTypes.h + +Types for LZMA Decoder + +This file written and distributed to public domain by Igor Pavlov. +This file is part of LZMA SDK 4.40 (2006-05-01) +*/ + +#ifndef __LZMATYPES_H +#define __LZMATYPES_H + +#ifndef _7ZIP_BYTE_DEFINED +#define _7ZIP_BYTE_DEFINED +typedef unsigned char Byte; +#endif + +#ifndef _7ZIP_UINT16_DEFINED +#define _7ZIP_UINT16_DEFINED +typedef unsigned short UInt16; +#endif + +#ifndef _7ZIP_UINT32_DEFINED +#define _7ZIP_UINT32_DEFINED +#ifdef _LZMA_UINT32_IS_ULONG +typedef unsigned long UInt32; +#else +typedef unsigned int UInt32; +#endif +#endif + +/* #define _LZMA_NO_SYSTEM_SIZE_T */ +/* You can use it, if you don't want */ + +#ifndef _7ZIP_SIZET_DEFINED +#define _7ZIP_SIZET_DEFINED +#ifdef _LZMA_NO_SYSTEM_SIZE_T +typedef UInt32 SizeT; +#else +#include +typedef size_t SizeT; +#endif +#endif + +#endif diff --git a/target/linux/lantiq/image/lzma-loader/src/Makefile b/target/linux/lantiq/image/lzma-loader/src/Makefile new file mode 100644 index 0000000..1ea01bf --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/Makefile @@ -0,0 +1,110 @@ +# +# Makefile for the LZMA compressed kernel loader for +# Atheros AR7XXX/AR9XXX based boards +# +# Copyright (C) 2011 Gabor Juhos +# +# Some parts of this file was based on the OpenWrt specific lzma-loader +# for the BCM47xx and ADM5120 based boards: +# Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) +# Copyright (C) 2005 Mineharu Takahara +# Copyright (C) 2005 by Oleg I. Vdovikin +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License version 2 as published +# by the Free Software Foundation. +# + +LOADADDR := +LZMA_TEXT_START := 0x80a00000 +LOADER_DATA := +BOARD := +FLASH_OFFS := +FLASH_MAX := +PLATFORM := + +CC := $(CROSS_COMPILE)gcc +LD := $(CROSS_COMPILE)ld +OBJCOPY := $(CROSS_COMPILE)objcopy +OBJDUMP := $(CROSS_COMPILE)objdump + +BIN_FLAGS := -O binary -R .reginfo -R .note -R .comment -R .mdebug -R .MIPS.abiflags -S + +CFLAGS = -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \ + -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \ + -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \ + -fno-common -ffreestanding -fhonour-copts \ + -mabi=32 -march=mips32r2 \ + -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap +CFLAGS += -D_LZMA_PROB32 -DARCH=$(PLATFORM) + +ASFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +LDFLAGS = -static --gc-sections -no-warn-mismatch +LDFLAGS += -e startup -T loader.lds -Ttext $(LZMA_TEXT_START) + +O_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32) + +OBJECTS := head.o loader.o cache.o board-$(PLATFORM).o printf.o LzmaDecode.o + +include $(PLATFORM).mk +CFLAGS+=$(CACHE_FLAGS) +ASFLAGS+=$(CACHE_FLAGS) + +ifneq ($(strip $(LOADER_DATA)),) +OBJECTS += data.o +CFLAGS += -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR) +endif + +ifneq ($(strip $(KERNEL_CMDLINE)),) +CFLAGS += -DCONFIG_KERNEL_CMDLINE='"$(KERNEL_CMDLINE)"' +endif + +ifneq ($(strip $(FLASH_OFFS)),) +CFLAGS += -DCONFIG_FLASH_OFFS=$(FLASH_OFFS) +endif + +ifneq ($(strip $(FLASH_MAX)),) +CFLAGS += -DCONFIG_FLASH_MAX=$(FLASH_MAX) +endif + +BOARD_DEF := $(shell echo $(strip $(BOARD)) | tr a-z A-Z | tr - _) +ifneq ($(BOARD_DEF),) +CFLAGS += -DCONFIG_BOARD_$(BOARD_DEF) +endif + +all: loader.elf + +# Don't build dependencies, this may die if $(CC) isn't gcc +dep: + +install: + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $< + +%.o : %.S + $(CC) $(ASFLAGS) -c -o $@ $< + +data.o: $(LOADER_DATA) + $(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $< + +loader: $(OBJECTS) + $(LD) $(LDFLAGS) -o $@ $(OBJECTS) + +loader.bin: loader + $(OBJCOPY) $(BIN_FLAGS) $< $@ + +loader2.o: loader.bin + $(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $< + +loader.elf: loader2.o + $(LD) -e startup -T loader2.lds -Ttext $(LOADADDR) -o $@ $< + +mrproper: clean + +clean: + rm -f loader *.elf *.bin *.o + + + diff --git a/target/linux/lantiq/image/lzma-loader/src/ar71xx.mk b/target/linux/lantiq/image/lzma-loader/src/ar71xx.mk new file mode 100644 index 0000000..31541d7 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/ar71xx.mk @@ -0,0 +1 @@ +CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE="(32 * 1024)" -DCONFIG_DCACHE_SIZE="(64 * 1024)" -DCONFIG_CACHELINE_SIZE=32 diff --git a/target/linux/lantiq/image/lzma-loader/src/ar71xx_regs.h b/target/linux/lantiq/image/lzma-loader/src/ar71xx_regs.h new file mode 100644 index 0000000..19a4785 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/ar71xx_regs.h @@ -0,0 +1,725 @@ +/* + * Atheros AR71XX/AR724X/AR913X SoC register definitions + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_AR71XX_REGS_H +#define __ASM_MACH_AR71XX_REGS_H + +#define BIT(_x) (1UL << (_x)) + +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000 + +#define AR71XX_PCI_CFG_BASE \ + (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 + +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 + +#define AR9300_OTP_BASE 0x14000 +#define AR9300_OTP_STATUS 0x15f18 +#define AR9300_OTP_STATUS_TYPE 0x7 +#define AR9300_OTP_STATUS_VALID 0x4 +#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 +#define AR9300_OTP_STATUS_SM_BUSY 0x1 +#define AR9300_OTP_READ_DATA 0x15f1c + +/* + * DDR_CTRL block + */ +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +/* + * PLL block + */ +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +/* + * USB_CONFIG block + */ +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04 + +/* + * RESET block + */ +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \ + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) + +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \ + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ + AR934X_PCIE_WMAC_INT_PCIE_RC3) + +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28) + +#define QCA955X_EXT_INT_WMAC_ALL \ + (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ + QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) + +#define QCA955X_EXT_INT_PCIE_RC1_ALL \ + (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ + QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ + QCA955X_EXT_INT_PCIE_RC1_INT3) + +#define QCA955X_EXT_INT_PCIE_RC2_ALL \ + (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ + QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ + QCA955X_EXT_INT_PCIE_RC2_INT3) + +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9558 0x1130 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 + +#define AR913X_REV_ID_MINOR_MASK 0x3 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 +#define AR913X_REV_ID_REVISION_MASK 0x3 +#define AR913X_REV_ID_REVISION_SHIFT 2 + +#define AR933X_REV_ID_REVISION_MASK 0x3 + +#define AR724X_REV_ID_REVISION_MASK 0x3 + +#define AR934X_REV_ID_REVISION_MASK 0xf + +#define AR944X_REV_ID_REVISION_MASK 0xf + +/* + * SPI block + */ +#define AR71XX_SPI_REG_FS 0x00 /* Function Select */ +#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ +#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ +#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ + +#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + +#define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ +#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ + AR71XX_SPI_IOC_CS2) + +/* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define AR71XX_GPIO_COUNT 16 +#define AR724X_GPIO_COUNT 18 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA955X_GPIO_COUNT 24 + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) +#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) +#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) + +#define AR934X_GPIO_OUT_GPIO 0x00 + +/* + * MII_CTRL block + */ +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04 + +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2 + +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3 + +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1 + +/* + * AR933X GMAC interface + */ +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) + +/* + * AR934X GMAC Interface + */ +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) + +/* + * QCA955X GMAC Interface + */ + +#define QCA955X_GMAC_REG_ETH_CFG 0x00 + +#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6) + +#endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c b/target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c new file mode 100644 index 0000000..2f4dd6b --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c @@ -0,0 +1,56 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include "config.h" +#include "ar71xx_regs.h" + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +#define KSEG1ADDR(_x) (((_x) & 0x1fffffff) | 0xa0000000) + +#define UART_BASE 0xb8020000 + +#define UART_TX 0 +#define UART_LSR 5 + +#define UART_LSR_THRE 0x20 + +#define UART_READ(r) READREG(UART_BASE + 4 * (r)) +#define UART_WRITE(r,v) WRITEREG(UART_BASE + 4 * (r), (v)) + +void board_putc(int ch) +{ + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(UART_TX, ch); + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); +} + +#ifdef CONFIG_BOARD_TL_WR1043ND_V1 +static void tlwr1043nd_init(void) +{ + unsigned int reg = KSEG1ADDR(AR71XX_RESET_BASE); + unsigned int t; + + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); + t |= AR71XX_RESET_GE0_PHY; + WRITEREG(reg + AR913X_RESET_REG_RESET_MODULE, t); + /* flush write */ + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); +} +#else +static inline void tlwr1043nd_init(void) {} +#endif + +void board_init(void) +{ + tlwr1043nd_init(); +} diff --git a/target/linux/lantiq/image/lzma-loader/src/board-lantiq.c b/target/linux/lantiq/image/lzma-loader/src/board-lantiq.c new file mode 100644 index 0000000..b1b4373 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/board-lantiq.c @@ -0,0 +1,33 @@ +/* + * Arch specific code for Lantiq based boards + * + * Copyright (C) 2013 John Crispin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include "config.h" + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +#define UART_BASE 0xbe100c00 +#define ASC_TBUF (UART_BASE | 0x20) +#define ASC_FSTAT (UART_BASE | 0x48) + +#define TXMASK 0x3F00 +#define TXOFFSET 8 + +void board_putc(char c) +{ + while ((READREG(ASC_FSTAT) & TXMASK) >> TXOFFSET); + + WRITEREG(ASC_TBUF, c); +} + +void board_init(void) +{ +} diff --git a/target/linux/lantiq/image/lzma-loader/src/board-ralink.c b/target/linux/lantiq/image/lzma-loader/src/board-ralink.c new file mode 100644 index 0000000..7c947ec --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/board-ralink.c @@ -0,0 +1,42 @@ +/* + * Arch specific code for Ralink based boards + * + * Copyright (C) 2013 John Crispin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include "config.h" + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +#define KSEG1ADDR(_x) (((_x) & 0x1fffffff) | 0xa0000000) + +#ifdef CONFIG_SOC_RT288X +#define UART_BASE 0xb0300c00 +#else +#define UART_BASE 0xb0000c00 +#endif + +#define UART_TX 1 +#define UART_LSR 7 + +#define UART_LSR_THRE 0x20 + +#define UART_READ(r) READREG(UART_BASE + 4 * (r)) +#define UART_WRITE(r,v) WRITEREG(UART_BASE + 4 * (r), (v)) + +void board_putc(int ch) +{ + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(UART_TX, ch); + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); +} + +void board_init(void) +{ +} diff --git a/target/linux/lantiq/image/lzma-loader/src/cache.c b/target/linux/lantiq/image/lzma-loader/src/cache.c new file mode 100644 index 0000000..28cc848 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/cache.c @@ -0,0 +1,43 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * The cache manipulation routine has been taken from the U-Boot project. + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cache.h" +#include "cacheops.h" +#include "config.h" + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} diff --git a/target/linux/lantiq/image/lzma-loader/src/cache.h b/target/linux/lantiq/image/lzma-loader/src/cache.h new file mode 100644 index 0000000..506a235 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/cache.h @@ -0,0 +1,17 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef __CACHE_H +#define __CACHE_H + +void flush_cache(unsigned long start_addr, unsigned long size); + +#endif /* __CACHE_H */ diff --git a/target/linux/lantiq/image/lzma-loader/src/cacheops.h b/target/linux/lantiq/image/lzma-loader/src/cacheops.h new file mode 100644 index 0000000..70bcad7 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/cacheops.h @@ -0,0 +1,85 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#if defined(CONFIG_CPU_LOONGSON2) +#define Hit_Invalidate_I 0x00 +#else +#define Hit_Invalidate_I 0x10 +#endif +#define Hit_Invalidate_D 0x11 +#define Hit_Writeback_Inv_D 0x15 + +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D 0x0d +#define Fill 0x14 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_SD 0x1b +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S 0x17 + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T 0x16 + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S 0x03 +#define Index_Load_Tag_S 0x07 +#define Index_Store_Tag_S 0x0B +#define Hit_Invalidate_S 0x13 +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S 0x17 +#define Index_Load_Data_I 0x18 +#define Index_Load_Data_D 0x19 +#define Index_Load_Data_S 0x1b +#define Index_Store_Data_I 0x1c +#define Index_Store_Data_D 0x1d +#define Index_Store_Data_S 0x1f + +#endif /* __ASM_CACHEOPS_H */ diff --git a/target/linux/lantiq/image/lzma-loader/src/config.h b/target/linux/lantiq/image/lzma-loader/src/config.h new file mode 100644 index 0000000..b7719e9 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/config.h @@ -0,0 +1,27 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#ifndef CONFIG_FLASH_OFFS +#define CONFIG_FLASH_OFFS 0 +#endif + +#ifndef CONFIG_FLASH_MAX +#define CONFIG_FLASH_MAX 0 +#endif + +#ifndef CONFIG_FLASH_STEP +#define CONFIG_FLASH_STEP 0x1000 +#endif + +#endif /* _CONFIG_H_ */ diff --git a/target/linux/lantiq/image/lzma-loader/src/cp0regdef.h b/target/linux/lantiq/image/lzma-loader/src/cp0regdef.h new file mode 100644 index 0000000..c1188ad --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/cp0regdef.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * + * Copyright (C) 2001, Monta Vista Software + * Author: jsun@mvista.com or jsun@junsun.net + */ +#ifndef _cp0regdef_h_ +#define _cp0regdef_h_ + +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 + +#endif diff --git a/target/linux/lantiq/image/lzma-loader/src/head.S b/target/linux/lantiq/image/lzma-loader/src/head.S new file mode 100644 index 0000000..543996a --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/head.S @@ -0,0 +1,118 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include "cp0regdef.h" +#include "cacheops.h" +#include "config.h" + +#define KSEG0 0x80000000 + + .macro ehb + sll zero, 3 + .endm + + .text + +LEAF(startup) + .set noreorder + .set mips32 + + mtc0 zero, CP0_WATCHLO # clear watch registers + mtc0 zero, CP0_WATCHHI + mtc0 zero, CP0_CAUSE # clear before writing status register + + mfc0 t0, CP0_STATUS + li t1, 0x1000001f + or t0, t1 + xori t0, 0x1f + mtc0 t0, CP0_STATUS + ehb + + mtc0 zero, CP0_COUNT + mtc0 zero, CP0_COMPARE + ehb + + la t0, __reloc_label # get linked address of label + bal __reloc_label # branch and link to label to + nop # get actual address +__reloc_label: + subu t0, ra, t0 # get reloc_delta + + beqz t0, __reloc_done # if delta is 0 we are in the right place + nop + + /* Copy our code to the right place */ + la t1, _code_start # get linked address of _code_start + la t2, _code_end # get linked address of _code_end + addu t0, t0, t1 # calculate actual address of _code_start + +__reloc_copy: + lw t3, 0(t0) + sw t3, 0(t1) + add t1, 4 + blt t1, t2, __reloc_copy + add t0, 4 + + /* flush cache */ + la t0, _code_start + la t1, _code_end + + li t2, ~(CONFIG_CACHELINE_SIZE - 1) + and t0, t2 + and t1, t2 + li t2, CONFIG_CACHELINE_SIZE + + b __flush_check + nop + +__flush_line: + cache Hit_Writeback_Inv_D, 0(t0) + cache Hit_Invalidate_I, 0(t0) + add t0, t2 + +__flush_check: + bne t0, t1, __flush_line + nop + + sync + +__reloc_done: + + /* clear bss */ + la t0, _bss_start + la t1, _bss_end + b __bss_check + nop + +__bss_fill: + sw zero, 0(t0) + addi t0, 4 + +__bss_check: + bne t0, t1, __bss_fill + nop + + /* Setup new "C" stack */ + la sp, _stack + + /* jump to the decompressor routine */ + la t0, loader_main + jr t0 + nop + + .set reorder +END(startup) diff --git a/target/linux/lantiq/image/lzma-loader/src/lantiq.mk b/target/linux/lantiq/image/lzma-loader/src/lantiq.mk new file mode 100644 index 0000000..4137645 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/lantiq.mk @@ -0,0 +1 @@ +CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE="(32 * 1024)" -DCONFIG_DCACHE_SIZE="(32 * 1024)" -DCONFIG_CACHELINE_SIZE=32 diff --git a/target/linux/lantiq/image/lzma-loader/src/loader.c b/target/linux/lantiq/image/lzma-loader/src/loader.c new file mode 100644 index 0000000..1d42bfa --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/loader.c @@ -0,0 +1,263 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos + * + * Some parts of this code was based on the OpenWrt specific lzma-loader + * for the BCM47xx and ADM5120 based boards: + * Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org) + * Copyright (C) 2005 Mineharu Takahara + * Copyright (C) 2005 by Oleg I. Vdovikin + * + * The image_header structure has been taken from the U-Boot project. + * (C) Copyright 2008 Semihalf + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include + +#include "config.h" +#include "cache.h" +#include "printf.h" +#include "LzmaDecode.h" + +#define AR71XX_FLASH_START 0x1f000000 +#define AR71XX_FLASH_END 0x1fe00000 + +#define KSEG0 0x80000000 +#define KSEG1 0xa0000000 + +#define KSEG1ADDR(a) ((((unsigned)(a)) & 0x1fffffffU) | KSEG1) + +#undef LZMA_DEBUG + +#ifdef LZMA_DEBUG +# define DBG(f, a...) printf(f, ## a) +#else +# define DBG(f, a...) do {} while (0) +#endif + +#define IH_MAGIC_OKLI 0x4f4b4c49 /* 'OKLI' */ + +#define IH_NMLEN 32 /* Image Name Length */ + +typedef struct image_header { + uint32_t ih_magic; /* Image Header Magic Number */ + uint32_t ih_hcrc; /* Image Header CRC Checksum */ + uint32_t ih_time; /* Image Creation Timestamp */ + uint32_t ih_size; /* Image Data Size */ + uint32_t ih_load; /* Data Load Address */ + uint32_t ih_ep; /* Entry Point Address */ + uint32_t ih_dcrc; /* Image Data CRC Checksum */ + uint8_t ih_os; /* Operating System */ + uint8_t ih_arch; /* CPU architecture */ + uint8_t ih_type; /* Image Type */ + uint8_t ih_comp; /* Compression Type */ + uint8_t ih_name[IH_NMLEN]; /* Image Name */ +} image_header_t; + +/* beyond the image end, size not known in advance */ +extern unsigned char workspace[]; +extern void board_init(void); + +static CLzmaDecoderState lzma_state; +static unsigned char *lzma_data; +static unsigned long lzma_datasize; +static unsigned long lzma_outsize; +static unsigned long kernel_la; + +#ifdef CONFIG_KERNEL_CMDLINE +#define kernel_argc 1 +static const char kernel_cmdline[] = CONFIG_KERNEL_CMDLINE; +static const char *kernel_argv[] = { + kernel_cmdline, + NULL, +}; +#endif /* CONFIG_KERNEL_CMDLINE */ + +static void halt(void) +{ + printf("\nSystem halted!\n"); + for(;;); +} + +static __inline__ unsigned long get_be32(void *buf) +{ + unsigned char *p = buf; + + return (((unsigned long) p[0] << 24) + + ((unsigned long) p[1] << 16) + + ((unsigned long) p[2] << 8) + + (unsigned long) p[3]); +} + +static __inline__ unsigned char lzma_get_byte(void) +{ + unsigned char c; + + lzma_datasize--; + c = *lzma_data++; + + return c; +} + +static int lzma_init_props(void) +{ + unsigned char props[LZMA_PROPERTIES_SIZE]; + int res; + int i; + + /* read lzma properties */ + for (i = 0; i < LZMA_PROPERTIES_SIZE; i++) + props[i] = lzma_get_byte(); + + /* read the lower half of uncompressed size in the header */ + lzma_outsize = ((SizeT) lzma_get_byte()) + + ((SizeT) lzma_get_byte() << 8) + + ((SizeT) lzma_get_byte() << 16) + + ((SizeT) lzma_get_byte() << 24); + + /* skip rest of the header (upper half of uncompressed size) */ + for (i = 0; i < 4; i++) + lzma_get_byte(); + + res = LzmaDecodeProperties(&lzma_state.Properties, props, + LZMA_PROPERTIES_SIZE); + return res; +} + +static int lzma_decompress(unsigned char *outStream) +{ + SizeT ip, op; + int ret; + + lzma_state.Probs = (CProb *) workspace; + + ret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream, + lzma_outsize, &op); + + if (ret != LZMA_RESULT_OK) { + int i; + + DBG("LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\n", + ret, lzma_data + ip, lzma_outsize, ip, op); + + for (i = 0; i < 16; i++) + DBG("%02x ", lzma_data[ip + i]); + + DBG("\n"); + } + + return ret; +} + +#if (LZMA_WRAPPER) +static void lzma_init_data(void) +{ + extern unsigned char _lzma_data_start[]; + extern unsigned char _lzma_data_end[]; + + kernel_la = LOADADDR; + lzma_data = _lzma_data_start; + lzma_datasize = _lzma_data_end - _lzma_data_start; +} +#else +static void lzma_init_data(void) +{ + struct image_header *hdr = NULL; + unsigned char *flash_base; + unsigned long flash_ofs; + unsigned long kernel_ofs; + unsigned long kernel_size; + + flash_base = (unsigned char *) KSEG1ADDR(AR71XX_FLASH_START); + + printf("Looking for OpenWrt image... "); + + for (flash_ofs = CONFIG_FLASH_OFFS; + flash_ofs <= (CONFIG_FLASH_OFFS + CONFIG_FLASH_MAX); + flash_ofs += CONFIG_FLASH_STEP) { + unsigned long magic; + unsigned char *p; + + p = flash_base + flash_ofs; + magic = get_be32(p); + if (magic == IH_MAGIC_OKLI) { + hdr = (struct image_header *) p; + break; + } + } + + if (hdr == NULL) { + printf("not found!\n"); + halt(); + } + + printf("found at 0x%08x\n", flash_base + flash_ofs); + + kernel_ofs = sizeof(struct image_header); + kernel_size = get_be32(&hdr->ih_size); + kernel_la = get_be32(&hdr->ih_load); + + lzma_data = flash_base + flash_ofs + kernel_ofs; + lzma_datasize = kernel_size; +} +#endif /* (LZMA_WRAPPER) */ + +void loader_main(unsigned long reg_a0, unsigned long reg_a1, + unsigned long reg_a2, unsigned long reg_a3) +{ + void (*kernel_entry) (unsigned long, unsigned long, unsigned long, + unsigned long); + int res; + + board_init(); + + printf("\n\nOpenWrt kernel loader for MIPS based SoC\n"); + printf("Copyright (C) 2011 Gabor Juhos \n"); + + lzma_init_data(); + + res = lzma_init_props(); + if (res != LZMA_RESULT_OK) { + printf("Incorrect LZMA stream properties!\n"); + halt(); + } + + printf("Decompressing kernel... "); + + res = lzma_decompress((unsigned char *) kernel_la); + if (res != LZMA_RESULT_OK) { + printf("failed, "); + switch (res) { + case LZMA_RESULT_DATA_ERROR: + printf("data error!\n"); + break; + default: + printf("unknown error %d!\n", res); + } + halt(); + } else { + printf("done!\n"); + } + + flush_cache(kernel_la, lzma_outsize); + + printf("Starting kernel at %08x...\n\n", kernel_la); + +#ifdef CONFIG_KERNEL_CMDLINE + reg_a0 = kernel_argc; + reg_a1 = (unsigned long) kernel_argv; + reg_a2 = 0; + reg_a3 = 0; +#endif + + kernel_entry = (void *) kernel_la; + kernel_entry(reg_a0, reg_a1, reg_a2, reg_a3); +} diff --git a/target/linux/lantiq/image/lzma-loader/src/loader.lds b/target/linux/lantiq/image/lzma-loader/src/loader.lds new file mode 100644 index 0000000..80cc7ca --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/loader.lds @@ -0,0 +1,35 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + _code_start = .; + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.data.lzma) + } + + . = ALIGN(32); + .data : { + *(.data) + *(.data.*) + . = . + 524288; /* workaround for buggy bootloaders */ + } + + . = ALIGN(32); + _code_end = .; + + _bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + } + + . = ALIGN(32); + _bss_end = .; + + . = . + 8192; + _stack = .; + + workspace = .; +} diff --git a/target/linux/lantiq/image/lzma-loader/src/loader2.lds b/target/linux/lantiq/image/lzma-loader/src/loader2.lds new file mode 100644 index 0000000..db0bb46 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/loader2.lds @@ -0,0 +1,10 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .text : { + startup = .; + *(.text) + *(.text.*) + *(.data) + *(.data.*) + } +} diff --git a/target/linux/lantiq/image/lzma-loader/src/lzma-data.lds b/target/linux/lantiq/image/lzma-loader/src/lzma-data.lds new file mode 100644 index 0000000..abf756b --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/lzma-data.lds @@ -0,0 +1,8 @@ +OUTPUT_ARCH(mips) +SECTIONS { + .data.lzma : { + _lzma_data_start = .; + *(.data) + _lzma_data_end = .; + } +} diff --git a/target/linux/lantiq/image/lzma-loader/src/printf.c b/target/linux/lantiq/image/lzma-loader/src/printf.c new file mode 100644 index 0000000..7bb5a86 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/printf.c @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include "printf.h" + +extern void board_putc(int ch); + +/* this is the maximum width for a variable */ +#define LP_MAX_BUF 256 + +/* macros */ +#define IsDigit(x) ( ((x) >= '0') && ((x) <= '9') ) +#define Ctod(x) ( (x) - '0') + +/* forward declaration */ +static int PrintChar(char *, char, int, int); +static int PrintString(char *, char *, int, int); +static int PrintNum(char *, unsigned long, int, int, int, int, char, int); + +/* private variable */ +static const char theFatalMsg[] = "fatal error in lp_Print!"; + +/* -*- + * A low level printf() function. + */ +static void +lp_Print(void (*output)(void *, char *, int), + void * arg, + char *fmt, + va_list ap) +{ + +#define OUTPUT(arg, s, l) \ + { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \ + (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \ + } else { \ + (*output)(arg, s, l); \ + } \ + } + + char buf[LP_MAX_BUF]; + + char c; + char *s; + long int num; + + int longFlag; + int negFlag; + int width; + int prec; + int ladjust; + char padc; + + int length; + + for(;;) { + { + /* scan for the next '%' */ + char *fmtStart = fmt; + while ( (*fmt != '\0') && (*fmt != '%')) { + fmt ++; + } + + /* flush the string found so far */ + OUTPUT(arg, fmtStart, fmt-fmtStart); + + /* are we hitting the end? */ + if (*fmt == '\0') break; + } + + /* we found a '%' */ + fmt ++; + + /* check for long */ + if (*fmt == 'l') { + longFlag = 1; + fmt ++; + } else { + longFlag = 0; + } + + /* check for other prefixes */ + width = 0; + prec = -1; + ladjust = 0; + padc = ' '; + + if (*fmt == '-') { + ladjust = 1; + fmt ++; + } + + if (*fmt == '0') { + padc = '0'; + fmt++; + } + + if (IsDigit(*fmt)) { + while (IsDigit(*fmt)) { + width = 10 * width + Ctod(*fmt++); + } + } + + if (*fmt == '.') { + fmt ++; + if (IsDigit(*fmt)) { + prec = 0; + while (IsDigit(*fmt)) { + prec = prec*10 + Ctod(*fmt++); + } + } + } + + + /* check format flag */ + negFlag = 0; + switch (*fmt) { + case 'b': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'd': + case 'D': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + if (num < 0) { + num = - num; + negFlag = 1; + } + length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'o': + case 'O': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'u': + case 'U': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'x': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0); + OUTPUT(arg, buf, length); + break; + + case 'X': + if (longFlag) { + num = va_arg(ap, long int); + } else { + num = va_arg(ap, int); + } + length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1); + OUTPUT(arg, buf, length); + break; + + case 'c': + c = (char)va_arg(ap, int); + length = PrintChar(buf, c, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case 's': + s = (char*)va_arg(ap, char *); + length = PrintString(buf, s, width, ladjust); + OUTPUT(arg, buf, length); + break; + + case '\0': + fmt --; + break; + + default: + /* output this char as it is */ + OUTPUT(arg, fmt, 1); + } /* switch (*fmt) */ + + fmt ++; + } /* for(;;) */ + + /* special termination call */ + OUTPUT(arg, "\0", 1); +} + + +/* --------------- local help functions --------------------- */ +static int +PrintChar(char * buf, char c, int length, int ladjust) +{ + int i; + + if (length < 1) length = 1; + if (ladjust) { + *buf = c; + for (i=1; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-1; i++) buf[i] = ' '; + buf[length - 1] = c; + } + return length; +} + +static int +PrintString(char * buf, char* s, int length, int ladjust) +{ + int i; + int len=0; + char* s1 = s; + while (*s1++) len++; + if (length < len) length = len; + + if (ladjust) { + for (i=0; i< len; i++) buf[i] = s[i]; + for (i=len; i< length; i++) buf[i] = ' '; + } else { + for (i=0; i< length-len; i++) buf[i] = ' '; + for (i=length-len; i < length; i++) buf[i] = s[i-length+len]; + } + return length; +} + +static int +PrintNum(char * buf, unsigned long u, int base, int negFlag, + int length, int ladjust, char padc, int upcase) +{ + /* algorithm : + * 1. prints the number from left to right in reverse form. + * 2. fill the remaining spaces with padc if length is longer than + * the actual length + * TRICKY : if left adjusted, no "0" padding. + * if negtive, insert "0" padding between "0" and number. + * 3. if (!ladjust) we reverse the whole string including paddings + * 4. otherwise we only reverse the actual string representing the num. + */ + + int actualLength =0; + char *p = buf; + int i; + + do { + int tmp = u %base; + if (tmp <= 9) { + *p++ = '0' + tmp; + } else if (upcase) { + *p++ = 'A' + tmp - 10; + } else { + *p++ = 'a' + tmp - 10; + } + u /= base; + } while (u != 0); + + if (negFlag) { + *p++ = '-'; + } + + /* figure out actual length and adjust the maximum length */ + actualLength = p - buf; + if (length < actualLength) length = actualLength; + + /* add padding */ + if (ladjust) { + padc = ' '; + } + if (negFlag && !ladjust && (padc == '0')) { + for (i = actualLength-1; i< length-1; i++) buf[i] = padc; + buf[length -1] = '-'; + } else { + for (i = actualLength; i< length; i++) buf[i] = padc; + } + + + /* prepare to reverse the string */ + { + int begin = 0; + int end; + if (ladjust) { + end = actualLength - 1; + } else { + end = length -1; + } + + while (end > begin) { + char tmp = buf[begin]; + buf[begin] = buf[end]; + buf[end] = tmp; + begin ++; + end --; + } + } + + /* adjust the string pointer */ + return length; +} + +static void printf_output(void *arg, char *s, int l) +{ + int i; + + // special termination call + if ((l==1) && (s[0] == '\0')) return; + + for (i=0; i< l; i++) { + board_putc(s[i]); + if (s[i] == '\n') board_putc('\r'); + } +} + +void printf(char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + lp_Print(printf_output, 0, fmt, ap); + va_end(ap); +} diff --git a/target/linux/lantiq/image/lzma-loader/src/printf.h b/target/linux/lantiq/image/lzma-loader/src/printf.h new file mode 100644 index 0000000..9b1c1df --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/printf.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef _printf_h_ +#define _printf_h_ + +#include +void printf(char *fmt, ...); + +#endif /* _printf_h_ */ diff --git a/target/linux/lantiq/image/lzma-loader/src/ralink.mk b/target/linux/lantiq/image/lzma-loader/src/ralink.mk new file mode 100644 index 0000000..3ff5fdd --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/ralink.mk @@ -0,0 +1 @@ +CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE="(32 * 1024)" -DCONFIG_DCACHE_SIZE="(16 * 1024)" -DCONFIG_CACHELINE_SIZE=32 diff --git a/target/linux/lantiq/image/ubinize-overlay.cfg b/target/linux/lantiq/image/ubinize-overlay.cfg new file mode 100644 index 0000000..65f0f42 --- /dev/null +++ b/target/linux/lantiq/image/ubinize-overlay.cfg @@ -0,0 +1,23 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.squashfs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs +[rootfs_data] +# Volume mode (other option is static) +mode=ubi +# Volume ID in UBI image +vol_id=1 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs_data +vol_size=1MiB +# Autoresize volume at first mount +vol_flags=autoresize diff --git a/target/linux/lantiq/image/ubinize.cfg b/target/linux/lantiq/image/ubinize.cfg new file mode 100644 index 0000000..49d55b9 --- /dev/null +++ b/target/linux/lantiq/image/ubinize.cfg @@ -0,0 +1,14 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.ubifs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs +# Autoresize volume at first mount +vol_flags=autoresize + diff --git a/target/linux/lantiq/modules.mk b/target/linux/lantiq/modules.mk new file mode 100644 index 0000000..e7fbad3 --- /dev/null +++ b/target/linux/lantiq/modules.mk @@ -0,0 +1,22 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +I2C_LANTIQ_MODULES:= \ + CONFIG_I2C_LANTIQ:drivers/i2c/busses/i2c-lantiq + +define KernelPackage/i2c-lantiq + TITLE:=Lantiq I2C controller + $(call i2c_defaults,$(I2C_LANTIQ_MODULES),52) + DEPENDS:=kmod-i2c-core @TARGET_lantiq_falcon +endef + +define KernelPackage/i2c-lantiq/description + Kernel support for the Lantiq/Falcon I2C controller +endef + +$(eval $(call KernelPackage,i2c-lantiq)) + diff --git a/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch new file mode 100644 index 0000000..e47bfa4 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0001-MIPS-lantiq-add-pcie-driver.patch @@ -0,0 +1,5540 @@ +From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:12:28 +0200 +Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/Kconfig | 10 + + arch/mips/lantiq/xway/sysctrl.c | 2 + + arch/mips/pci/Makefile | 2 + + arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ + arch/mips/pci/fixup-lantiq.c | 5 +- + arch/mips/pci/ifxmips_pci_common.h | 57 ++ + arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie.h | 135 ++++ + arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ + arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ + arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ + arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ + arch/mips/pci/ifxmips_pcie_pm.h | 36 + + arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ + arch/mips/pci/pci.c | 25 + + arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ + drivers/pci/pcie/aer/Kconfig | 2 +- + include/linux/pci.h | 2 + + include/linux/pci_ids.h | 6 + + 20 files changed, 5374 insertions(+), 2 deletions(-) + create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c + create mode 100644 arch/mips/pci/ifxmips_pci_common.h + create mode 100644 arch/mips/pci/ifxmips_pcie.c + create mode 100644 arch/mips/pci/ifxmips_pcie.h + create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h + create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c + create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h + create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h + create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h + create mode 100644 arch/mips/pci/pcie-lantiq.h + +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -17,6 +17,7 @@ config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HW_HAS_PCI ++ select ARCH_SUPPORTS_MSI + + config SOC_FALCON + bool "FALCON" +@@ -37,6 +38,15 @@ config PCI_LANTIQ + bool "PCI Support" + depends on SOC_XWAY && PCI + ++config PCIE_LANTIQ ++ bool "PCIE Support" ++ depends on SOC_XWAY && PCI ++ ++config PCIE_LANTIQ_MSI ++ bool ++ depends on PCIE_LANTIQ && PCI_MSI ++ default y ++ + config XRX200_PHY_FW + bool "XRX200 PHY firmware loader" + depends on SOC_XWAY +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -377,6 +377,8 @@ void __init ltq_soc_init(void) + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB | PMU_PPE_TOP); + clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY); ++ pmu_w32(~0, PMU_PWDSR1); ++ pmu_w32(pmu_r32(PMU_PWDSR) & ~PMU_PCIE_CLK, PMU_PWDSR); + } else if (of_machine_is_compatible("lantiq,ar9")) { + clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), + ltq_ar9_fpi_hz(), CLOCK_250M); +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -43,6 +43,8 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops + obj-$(CONFIG_LANTIQ) += fixup-lantiq.o + obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o + obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o +--- /dev/null ++++ b/arch/mips/pci/fixup-lantiq-pcie.c +@@ -0,0 +1,82 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_fixup_pcie.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_fixup_pcie.c ++ \ingroup IFX_PCIE ++ \brief PCIe Fixup functions source file ++*/ ++#include ++#include ++#include ++ ++#include ++ ++#include "pcie-lantiq.h" ++ ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 ++ ++ ++ ++static void ++ifx_pcie_fixup_resource(struct pci_dev *dev) ++{ ++ u32 reg; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ printk("%s: fixup host controller %s (%04x:%04x)\n", ++ __func__, pci_name(dev), dev->vendor, dev->device); ++ ++ /* Setup COMMAND register */ ++ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | ++ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; ++ pci_write_config_word(dev, PCI_COMMAND, reg); ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); ++ ++static void ++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ if (dev->devfn == PCI_DEVFN(0, 0) && ++ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { ++ ++ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); ++ ++ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); ++ } ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++ mdelay(10); ++} ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ++ ifx_pcie_rc_class_early_fixup); ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, ++ ifx_pcie_rc_class_early_fixup); +--- a/arch/mips/pci/fixup-lantiq.c ++++ b/arch/mips/pci/fixup-lantiq.c +@@ -8,12 +8,18 @@ + + #include + #include ++#include "ifxmips_pci_common.h" + + int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; + int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; + + int pcibios_plat_dev_init(struct pci_dev *dev) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ ifx_pcie_bios_plat_dev_init(dev); ++#endif ++ + if (ltq_pci_plat_arch_init) + return ltq_pci_plat_arch_init(dev); + +@@ -25,5 +31,10 @@ int pcibios_plat_dev_init(struct pci_dev + + int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ return ifx_pcie_bios_map_irq(dev, slot, pin); ++#endif ++ + return of_irq_parse_and_map_pci(dev, slot, pin); + } +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pci_common.h +@@ -0,0 +1,57 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pci_common.h ++** PROJECT : IFX UEIP ++** MODULES : PCI subsystem ++** ++** DATE : 30 June 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 30 June,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++ ++#ifndef IFXMIPS_PCI_COMMON_H ++#define IFXMIPS_PCI_COMMON_H ++#include ++/*! ++ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration ++ \brief PCI/PCIe common parts ++*/ ++ ++/*! ++ \defgroup IFX_PCI_COM_OS OS APIs ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver OS interface functions ++*/ ++/*! ++ \file ifxmips_pci_common.h ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver common OS header file ++*/ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++#define IFX_PCI_CONST ++#else ++#define IFX_PCI_CONST const ++#endif ++#ifdef CONFIG_IFX_PCI ++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); ++#endif /* COFNIG_IFX_PCI */ ++ ++#ifdef CONFIG_PCIE_LANTIQ ++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); ++#endif ++ ++#endif /* IFXMIPS_PCI_COMMON_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -0,0 +1,1092 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2009 Lei Chuanhua ++ * Copyright (C) 2013 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie.h" ++#include "ifxmips_pcie_reg.h" ++ ++/* Enable 32bit io due to its mem mapped io nature */ ++#define IFX_PCIE_ERROR_INT ++#define IFX_PCIE_IO_32BIT ++ ++#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) ++#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) ++#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) ++#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) ++#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) ++#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) ++#define SM(_v, _f) (((_v) << _f##_S) & (_f)) ++#define IFX_REG_SET_BIT(_f, _r) \ ++ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) ++ ++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 ++ ++static DEFINE_SPINLOCK(ifx_pcie_lock); ++ ++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++ ++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .ir_irq = { ++ .irq = IFX_PCIE_IR, ++ .name = "ifx_pcie_rc0", ++ }, ++ ++ .legacy_irq = { ++ { ++ .irq_bit = PCIE_IRN_INTA, ++ .irq = IFX_PCIE_INTA, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTB, ++ .irq = IFX_PCIE_INTB, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTC, ++ .irq = IFX_PCIE_INTC, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTD, ++ .irq = IFX_PCIE_INTD, ++ }, ++ }, ++ }, ++ ++}; ++ ++void ifx_pcie_debug(const char *fmt, ...) ++{ ++ static char buf[256] = {0}; /* XXX */ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ vsnprintf(buf, sizeof(buf), fmt, ap); ++ va_end(ap); ++ ++ printk("%s", buf); ++} ++ ++ ++static inline int pcie_ltssm_enable(int pcie_port) ++{ ++ int i; ++ ++ /* Enable LTSSM */ ++ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); ++ ++ /* Wait for the link to come up */ ++ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) ++ return 0; ++ udelay(10); ++ } ++ ++ printk("%s link timeout!!!!!\n", __func__); ++ return -1; ++} ++ ++static inline void pcie_status_register_clear(int pcie_port) ++{ ++ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); ++ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_UESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_RESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); ++ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_QSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); ++} ++ ++static inline int ifx_pcie_link_up(int pcie_port) ++{ ++ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; ++} ++ ++ ++static inline void pcie_mem_io_setup(int pcie_port) ++{ ++ u32 reg; ++ /* ++ * BAR[0:1] readonly register ++ * RC contains only minimal BARs for packets mapped to this device ++ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that ++ * reside on the downstream side fo the bridge. ++ */ ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); ++ ++ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); ++ ++ ++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) ++ | PCIE_PMBL_64BIT_ADDR; ++ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); ++ ++ /* Must configure upper 32bit */ ++ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); ++ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); ++#else ++ /* PCIe_PBML, same as MBML */ ++ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); ++#endif ++ ++ /* IO Address Range */ ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); ++#ifdef IFX_PCIE_IO_32BIT ++ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; ++#endif /* IFX_PCIE_IO_32BIT */ ++ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); ++ ++#ifdef IFX_PCIE_IO_32BIT ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); ++ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); ++ ++#endif /* IFX_PCIE_IO_32BIT */ ++} ++ ++static inline void ++pcie_device_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Device capability register, set up Maximum payload size */ ++ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); ++ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); ++ ++ /* Only available for EP */ ++ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); ++ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); ++ ++ /* Device control and status register */ ++ /* Set Maximum Read Request size for the device as a Requestor */ ++ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); ++ ++ /* ++ * Request size can be larger than the MPS used, but the completions returned ++ * for the read will be bounded by the MPS size. ++ * In our system, Max request size depends on AHB burst size. It is 64 bytes. ++ * but we set it as 128 as minimum one. ++ */ ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) ++ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); ++ ++ /* Enable relaxed ordering, no snoop, and all kinds of errors */ ++ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; ++ ++ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); ++} ++ ++static inline void ++pcie_link_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM ++ * L0s is reported during link training via TS1 order set by N_FTS ++ */ ++ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); ++ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; ++ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); ++ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); ++ ++ /* Link control and status register */ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ /* Link Enable, ASPM enabled */ ++ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; ++ ++#ifdef CONFIG_PCIEASPM ++ /* ++ * We use the same physical reference clock that the platform provides on the connector ++ * It paved the way for ASPM to calculate the new exit Latency ++ */ ++ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; ++ reg |= PCIE_LCTLSTS_COM_CLK_CFG; ++ /* ++ * We should disable ASPM by default except that we have dedicated power management support ++ * Enable ASPM will cause the system hangup/instability, performance degration ++ */ ++ reg |= PCIE_LCTLSTS_ASPM_ENABLE; ++#else ++ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; ++#endif /* CONFIG_PCIEASPM */ ++ ++ /* ++ * The maximum size of any completion with data packet is bounded by the MPS setting ++ * in device control register ++ */ ++ ++ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ ++ reg &= ~ PCIE_LCTLSTS_RCB128; ++ ++ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); ++} ++ ++static inline void pcie_error_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone ++ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE ++ */ ++ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); ++ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; ++ ++ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); ++ ++ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ ++ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); ++ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); ++ ++ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ ++ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); ++ ++ /* Correctable Error Mask Register, unmask all bits */ ++ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); ++ reg &= ~PCIE_CORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); ++ ++ /* Advanced Error Capabilities and Control Registr */ ++ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); ++ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; ++ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); ++ ++ /* Root Error Command Register, Report all types of errors */ ++ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); ++ reg |= PCIE_RECR_ERR_REPORT_EN; ++ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); ++ ++ /* Clear the Root status register */ ++ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); ++ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); ++} ++ ++static inline void pcie_port_logic_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ ++ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); ++ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); ++ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) ++ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); ++ /* L0s and L1 entry latency */ ++ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); ++ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) ++ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); ++ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); ++ ++ ++ /* Port Link Control Register */ ++ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); ++ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ ++ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); ++ ++ /* Lane Skew Register */ ++ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); ++ /* Enable ACK/NACK and FC */ ++ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); ++ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); ++ ++ /* Symbol Timer Register and Filter Mask Register 1 */ ++ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); ++ ++ /* Default SKP interval is very accurate already, 5us */ ++ /* Enable IO/CFG transaction */ ++ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; ++ /* Disable FC WDT */ ++ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; ++ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); ++ ++ /* Filter Masker Register 2 */ ++ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); ++ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; ++ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); ++ ++ /* VC0 Completion Receive Queue Control Register */ ++ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); ++ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; ++ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); ++ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); ++} ++ ++static inline void pcie_rc_cfg_reg_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Disable LTSSM */ ++ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ ++ ++ pcie_mem_io_setup(pcie_port); ++ ++ /* XXX, MSI stuff should only apply to EP */ ++ /* MSI Capability: Only enable 32-bit addresses */ ++ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); ++ reg &= ~PCIE_MCAPR_ADDR64_CAP; ++ ++ reg |= PCIE_MCAPR_MSI_ENABLE; ++ ++ /* Disable multiple message */ ++ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); ++ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); ++ ++ ++ /* Enable PME, Soft reset enabled */ ++ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); ++ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; ++ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); ++ ++ /* setup the bus */ ++ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); ++ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); ++ ++ ++ pcie_device_setup(pcie_port); ++ pcie_link_setup(pcie_port); ++ pcie_error_setup(pcie_port); ++ ++ /* Root control and capabilities register */ ++ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); ++ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; ++ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); ++ ++ /* Port VC Capability Register 2 */ ++ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); ++ reg &= ~PCIE_PVC2_VC_ARB_WRR; ++ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; ++ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); ++ ++ /* VC0 Resource Capability Register */ ++ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); ++ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; ++ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); ++ ++ pcie_port_logic_setup(pcie_port); ++} ++ ++static int ifx_pcie_wait_phy_link_up(int pcie_port) ++{ ++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ ++ int i; ++ ++ /* Wait for PHY link is up */ ++ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { ++ if (ifx_pcie_link_up(pcie_port)) { ++ break; ++ } ++ udelay(100); ++ } ++ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -1; ++ } ++ ++ /* Check data link up or not */ ++ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { ++ printk(KERN_ERR "%s DLL link is still down\n", __func__); ++ return -1; ++ } ++ ++ /* Check Data link active or not */ ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { ++ printk(KERN_ERR "%s DLL is not active\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static inline int pcie_app_loigc_setup(int pcie_port) ++{ ++ /* supress ahb bus errrors */ ++ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); ++ ++ /* Pull PCIe EP out of reset */ ++ pcie_device_rst_deassert(pcie_port); ++ ++ /* Start LTSSM training between RC and EP */ ++ pcie_ltssm_enable(pcie_port); ++ ++ /* Check PHY status after enabling LTSSM */ ++ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) ++ return -1; ++ ++ return 0; ++} ++ ++/* ++ * The numbers below are directly from the PCIe spec table 3-4/5. ++ */ ++static inline void pcie_replay_time_update(int pcie_port) ++{ ++ u32 reg; ++ int nlw; ++ int rtl; ++ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); ++ switch (nlw) { ++ case PCIE_MAX_LENGTH_WIDTH_X1: ++ rtl = 1677; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X2: ++ rtl = 867; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X4: ++ rtl = 462; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X8: ++ rtl = 258; ++ break; ++ default: ++ rtl = 1677; ++ break; ++ } ++ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); ++ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; ++ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); ++ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); ++} ++ ++/* ++ * Table 359 Enhanced Configuration Address Mapping1) ++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 ++ * Memory Address PCI Express Configuration Space ++ * A[(20+n-1):20] Bus Number 1 < n < 8 ++ * A[19:15] Device Number ++ * A[14:12] Function Number ++ * A[11:8] Extended Register Number ++ * A[7:2] Register Number ++ * A[1:0] Along with size of the access, used to generate Byte Enables ++ * For VR9, only the address bits [22:0] are mapped to the configuration space: ++ * . Address bits [22:20] select the target bus (1-of-8)1) ++ * . Address bits [19:15] select the target device (1-of-32) on the bus ++ * . Address bits [14:12] select the target function (1-of-8) within the device. ++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space ++ * . Address bits [1:0] define the start byte location within the selected dword. ++ */ ++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) ++{ ++ u32 addr; ++ u8 bus; ++ ++ if (!bus_num) { ++ /* type 0 */ ++ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); ++ } else { ++ bus = bus_num; ++ /* type 1, only support 8 buses */ ++ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | ++ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); ++ } ++ return addr; ++} ++ ++static int pcie_valid_config(int pcie_port, int bus, int dev) ++{ ++ /* RC itself */ ++ if ((bus == 0) && (dev == 0)) { ++ return 1; ++ } ++ ++ /* No physical link */ ++ if (!ifx_pcie_link_up(pcie_port)) { ++ return 0; ++ } ++ ++ /* Bus zero only has RC itself ++ * XXX, check if EP will be integrated ++ */ ++ if ((bus == 0) && (dev != 0)) { ++ return 0; ++ } ++ ++ /* Maximum 8 buses supported for VRX */ ++ if (bus > 9) { ++ return 0; ++ } ++ ++ /* ++ * PCIe is PtP link, one bus only supports only one device ++ * except bus zero and PCIe switch which is virtual bus device ++ * The following two conditions really depends on the system design ++ * and attached the device. ++ * XXX, how about more new switch ++ */ ++ if ((bus == 1) && (dev != 0)) { ++ return 0; ++ } ++ ++ if ((bus >= 3) && (dev != 0)) { ++ return 0; ++ } ++ return 1; ++} ++ ++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ primary += pcibios_1st_host_bus_nr(); ++ secondary += pcibios_1st_host_bus_nr(); ++ subordinate += pcibios_1st_host_bus_nr(); ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ return tvalue; ++} ++ ++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ if (primary > 0 && primary != 0xFF) { ++ primary -= pcibios_1st_host_bus_nr(); ++ } ++ ++ if (secondary > 0 && secondary != 0xFF) { ++ secondary -= pcibios_1st_host_bus_nr(); ++ } ++ if (subordinate > 0 && subordinate != 0xFF) { ++ subordinate -= pcibios_1st_host_bus_nr(); ++ } ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ else if (where == PCI_SUBORDINATE_BUS) { ++ u8 subordinate = tvalue & 0xFF; ++ ++ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; ++ tvalue = subordinate; ++ } ++ return tvalue; ++} ++ ++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 *value) ++{ ++ u32 data = 0; ++ int bus_number = bus->number; ++ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ if (unlikely(size != 1 && size != 2 && size != 4)){ ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ /* ++ * PCIe only has a single device connected to it. It is ++ * always device ID 0. Don't bother doing reads for other ++ * device IDs on the first segment. ++ */ ++ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { ++ ret = PCIBIOS_FUNC_NOT_SUPPORTED; ++ goto out; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ *value = 0xffffffff; ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ } ++ /* To get a correct PCI topology, we have to restore the bus number to OS */ ++ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); ++ ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++ ++ *value = (data >> (8 * (where & 3))) & mask[size & 7]; ++out: ++ return ret; ++} ++ ++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) ++{ ++ u32 shift; ++ u32 tdata = data; ++ ++ switch (size) { ++ case 1: ++ shift = (where & 0x3) << 3; ++ tdata &= ~(0xffU << shift); ++ tdata |= ((value & 0xffU) << shift); ++ break; ++ case 2: ++ shift = (where & 3) << 3; ++ tdata &= ~(0xffffU << shift); ++ tdata |= ((value & 0xffffU) << shift); ++ break; ++ case 4: ++ tdata = value; ++ break; ++ } ++ return tdata; ++} ++ ++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 value) ++{ ++ int bus_number = bus->number; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ u32 tvalue = value; ++ u32 data; ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ /* XXX, some PCIe device may need some delay */ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ ++ /* ++ * To configure the correct bus topology using native way, we have to cheat Os so that ++ * it can configure the PCIe hardware correctly. ++ */ ++ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); ++ ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++ ++ ifx_pcie_rc_cfg_wr(pcie_port, t, data); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++#endif ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = cpu_to_le32(data); ++#endif ++ ifx_pcie_cfg_wr(pcie_port, addr, data); ++ } ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++out: ++ return ret; ++} ++ ++static struct resource ifx_pcie_io_resource = { ++ .name = "PCIe0 I/O space", ++ .start = PCIE_IO_PHY_BASE, ++ .end = PCIE_IO_PHY_END, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ifx_pcie_mem_resource = { ++ .name = "PCIe0 Memory space", ++ .start = PCIE_MEM_PHY_BASE, ++ .end = PCIE_MEM_PHY_END, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct pci_ops ifx_pcie_ops = { ++ .read = ifx_pcie_read_config, ++ .write = ifx_pcie_write_config, ++}; ++ ++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { ++ { ++ .pcic = { ++ .pci_ops = &ifx_pcie_ops, ++ .mem_resource = &ifx_pcie_mem_resource, ++ .io_resource = &ifx_pcie_io_resource, ++ }, ++ .port = IFX_PCIE_PORT0, ++ }, ++}; ++ ++#ifdef IFX_PCIE_ERROR_INT ++ ++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) ++{ ++ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; ++ int pcie_port = ctrl->port; ++ u32 reg; ++ ++ pr_debug("PCIe RC error intr %d\n", irq); ++ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); ++ reg &= PCIE_RC_CORE_COMBINED_INT; ++ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++pcie_rc_core_int_init(int pcie_port) ++{ ++ int ret; ++ ++ /* Enable core interrupt */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); ++ ++ /* Clear it first */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); ++ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, ++ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); ++ if (ret) ++ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); ++ ++ return ret; ++} ++#endif ++ ++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ u32 irq_bit = 0; ++ int irq = 0; ++ struct ifx_pci_controller *ctrl = dev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); ++ ++ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { ++ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); ++ return -1; ++ } ++ ++ /* Pin index so minus one */ ++ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; ++ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); ++ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); ++ return irq; ++} ++ ++int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) ++{ ++ u16 config; ++#ifdef IFX_PCIE_ERROR_INT ++ u32 dconfig; ++ int pos; ++#endif ++ ++ /* Enable reporting System errors and parity errors on all devices */ ++ /* Enable parity checking and error reporting */ ++ pci_read_config_word(dev, PCI_COMMAND, &config); ++ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_FAST_BACK*/; ++ pci_write_config_word(dev, PCI_COMMAND, config); ++ ++ if (dev->subordinate) { ++ /* Set latency timers on sub bridges */ ++ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ ++ /* More bridge error detection */ ++ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); ++ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; ++ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); ++ } ++#ifdef IFX_PCIE_ERROR_INT ++ /* Enable the PCIe normal error reporting */ ++ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); ++ if (pos) { ++ ++ /* Disable system error generation in response to error messages */ ++ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); ++ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); ++ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); ++ ++ /* Clear PCIE Capability's Device Status */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); ++ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); ++ ++ /* Update Device Control */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); ++ /* Correctable Error Reporting */ ++ config |= PCI_EXP_DEVCTL_CERE; ++ /* Non-Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_NFERE; ++ /* Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_FERE; ++ /* Unsupported Request */ ++ config |= PCI_EXP_DEVCTL_URRE; ++ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); ++ } ++ ++ /* Find the Advanced Error Reporting capability */ ++ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); ++ if (pos) { ++ /* Clear Uncorrectable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); ++ /* Enable reporting of all uncorrectable errors */ ++ /* Uncorrectable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); ++ /* ++ * Leave severity at HW default. This only controls if ++ * errors are reported as uncorrectable or ++ * correctable, not if the error is reported. ++ */ ++ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ ++ /* Clear Correctable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); ++ /* Enable reporting of all correctable errors */ ++ /* Correctable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); ++ /* Advanced Error Capabilities */ ++ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); ++ /* ECRC Generation Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { ++ dconfig |= PCI_ERR_CAP_ECRC_GENE; ++ } ++ /* ECRC Check Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { ++ dconfig |= PCI_ERR_CAP_ECRC_CHKE; ++ } ++ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); ++ ++ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ ++ /* Enable Root Port's interrupt in response to error messages */ ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, ++ PCI_ERR_ROOT_CMD_COR_EN | ++ PCI_ERR_ROOT_CMD_NONFATAL_EN | ++ PCI_ERR_ROOT_CMD_FATAL_EN); ++ /* Clear the Root status register */ ++ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); ++ } ++#endif /* IFX_PCIE_ERROR_INT */ ++ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ ++ pcie_set_readrq(dev, 128); ++ return 0; ++} ++ ++static int ++pcie_rc_initialize(int pcie_port) ++{ ++ int i; ++#define IFX_PCIE_PHY_LOOP_CNT 5 ++ ++ pcie_rcu_endian_setup(pcie_port); ++ ++ pcie_ep_gpio_rst_init(pcie_port); ++ ++ /* ++ * XXX, PCIe elastic buffer bug will cause not to be detected. One more ++ * reset PCIe PHY will solve this issue ++ */ ++ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { ++ /* Disable PCIe PHY Analog part for sanity check */ ++ pcie_phy_pmu_disable(pcie_port); ++ ++ pcie_phy_rst_assert(pcie_port); ++ pcie_phy_rst_deassert(pcie_port); ++ ++ /* Make sure PHY PLL is stable */ ++ udelay(20); ++ ++ /* PCIe Core reset enabled, low active, sw programmed */ ++ pcie_core_rst_assert(pcie_port); ++ ++ /* Put PCIe EP in reset status */ ++ pcie_device_rst_assert(pcie_port); ++ ++ /* PCI PHY & Core reset disabled, high active, sw programmed */ ++ pcie_core_rst_deassert(pcie_port); ++ ++ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ ++ pcie_phy_clock_mode_setup(pcie_port); ++ ++ /* Enable PCIe PHY and Clock */ ++ pcie_core_pmu_setup(pcie_port); ++ ++ /* Clear status registers */ ++ pcie_status_register_clear(pcie_port); ++ ++#ifdef CONFIG_PCI_MSI ++ pcie_msi_init(pcie_port); ++#endif /* CONFIG_PCI_MSI */ ++ pcie_rc_cfg_reg_setup(pcie_port); ++ ++ /* Once link is up, break out */ ++ if (pcie_app_loigc_setup(pcie_port) == 0) ++ break; ++ } ++ if (i >= IFX_PCIE_PHY_LOOP_CNT) { ++ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); ++ return -EIO; ++ } ++ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ ++ pcie_replay_time_update(pcie_port); ++ return 0; ++} ++ ++static int __init ifx_pcie_bios_init(void) ++{ ++ void __iomem *io_map_base; ++ int pcie_port; ++ int startup_port; ++ ++ /* Enable AHB Master/ Slave */ ++ pcie_ahb_pmu_setup(); ++ ++ startup_port = IFX_PCIE_PORT0; ++ ++ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ ++ if (pcie_rc_initialize(pcie_port) == 0) { ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", ++ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); ++ /* Otherwise, warning will pop up */ ++ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); ++ if (io_map_base == NULL) { ++ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); ++ return -ENOMEM; ++ } ++ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ ++ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); ++ /* XXX, clear error status */ ++ ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", ++ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, ++ &ifx_pcie_controller[pcie_port].pcic.io_resource); ++ ++ #ifdef IFX_PCIE_ERROR_INT ++ pcie_rc_core_int_init(pcie_port); ++ #endif /* IFX_PCIE_ERROR_INT */ ++ } ++ } ++ ++ return 0; ++} ++arch_initcall(ifx_pcie_bios_init); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); ++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.h +@@ -0,0 +1,135 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_H ++#define IFXMIPS_PCIE_H ++#include ++#include ++#include ++#include ++#include "ifxmips_pci_common.h" ++#include "ifxmips_pcie_reg.h" ++ ++/*! ++ \defgroup IFX_PCIE PCI Express bus driver module ++ \brief PCI Express IP module support VRX200 ++*/ ++ ++/*! ++ \defgroup IFX_PCIE_OS OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module common header file ++*/ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++#define CONFIG_VR9 ++ ++#ifdef CONFIG_VR9 ++#include "ifxmips_pcie_vr9.h" ++#elif defined (CONFIG_AR10) ++#include "ifxmips_pcie_ar10.h" ++#else ++#error "PCIE: platform not defined" ++#endif /* CONFIG_VR9 */ ++ ++#endif /* IFXMIPS_PCIE_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_ar10.h +@@ -0,0 +1,290 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_ar10.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver ar10 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_AR10_H ++#define IFXMIPS_PCIE_AR10_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++ ++/* Project header file */ ++#include ++#include ++#include ++#include ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ifx_ebu_led_enable(); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* XXX, moved to CGU to control AHBM */ ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Inbound, big endian */ ++ reg |= IFX_RCU_BE_AHB4S; ++ if (pcie_port == 0) { ++ reg |= IFX_RCU_BE_PCIE0M; ++ ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #endif ++ } ++ else { ++ reg |= IFX_RCU_BE_PCIE1M; ++ #ifdef CONFIG_IFX_PCIE1_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #endif ++ } ++ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ if (pcie_port == 0) { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE0_PDI; ++ } ++ else { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE1_PDI; ++ } ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ /* Enable PDI to access PCIe PHY register */ ++ PDI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PDI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset Core, bit 22 */ ++ if (pcie_port == 0) { ++ reg |= 0x00400000; ++ } ++ else { ++ reg |= 0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00400000; /* bit 22 */ ++ } ++ else { ++ reg &= ~0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg |= 0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg |= 0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg &= ~0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 0); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 0); ++ } ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++ ifx_ebu_led_disable(); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ pcie_msi_pic_init(pcie_port); ++ if (pcie_port == 0) { ++ MSI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ MSI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++ } ++#endif /* CONFIG_IFX_PCI */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ } ++ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_AR10_H */ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_msi.c +@@ -0,0 +1,392 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_msi.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCI MSI sub module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe MSI Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 02 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_MSI MSI OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_msi.c ++ \ingroup IFX_PCIE ++ \brief PCIe MSI OS interface file ++*/ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++#define IFX_MSI_IRQ_NUM 16 ++ ++enum { ++ IFX_PCIE_MSI_IDX0 = 0, ++ IFX_PCIE_MSI_IDX1, ++ IFX_PCIE_MSI_IDX2, ++ IFX_PCIE_MSI_IDX3, ++}; ++ ++typedef struct ifx_msi_irq_idx { ++ const int irq; ++ const int idx; ++}ifx_msi_irq_idx_t; ++ ++struct ifx_msi_pic { ++ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; ++ volatile u32 pic_endian; /* 0x40 */ ++}; ++typedef struct ifx_msi_pic *ifx_msi_pic_t; ++ ++typedef struct ifx_msi_irq { ++ const volatile ifx_msi_pic_t msi_pic_p; ++ const u32 msi_phy_base; ++ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; ++ /* ++ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is ++ * in use. ++ */ ++ u16 msi_free_irq_bitmask; ++ ++ /* ++ * Each bit in msi_multiple_irq_bitmask tells that the device using ++ * this bit in msi_free_irq_bitmask is also using the next bit. This ++ * is used so we can disable all of the MSI interrupts when a device ++ * uses multiple. ++ */ ++ u16 msi_multiple_irq_bitmask; ++}ifx_msi_irq_t; ++ ++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, ++ .msi_phy_base = PCIE_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ }, ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, ++ .msi_phy_base = PCIE1_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ ++ }, ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++}; ++ ++/* ++ * This lock controls updates to msi_free_irq_bitmask, ++ * msi_multiple_irq_bitmask and pic register settting ++ */ ++static DEFINE_SPINLOCK(ifx_pcie_msi_lock); ++ ++void pcie_msi_pic_init(int pcie_port) ++{ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; ++ spin_unlock(&ifx_pcie_msi_lock); ++} ++ ++/** ++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++ * \brief Called when a driver request MSI interrupts instead of the ++ * legacy INT A-D. This routine will allocate multiple interrupts ++ * for MSI devices that support them. A device can override this by ++ * programming the MSI control bits [6:4] before calling ++ * pci_enable_msi(). ++ * ++ * \param[in] pdev Device requesting MSI interrupts ++ * \param[in] desc MSI descriptor ++ * ++ * \return -EINVAL Invalid pcie root port or invalid msi bit ++ * \return 0 OK ++ * \ingroup IFX_PCIE_MSI ++ */ ++int ++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++{ ++ int irq, pos; ++ u16 control; ++ int irq_idx; ++ int irq_step; ++ int configured_private_bits; ++ int request_private_bits; ++ struct msi_msg msg; ++ u16 search_mask; ++ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); ++ ++ /* XXX, skip RC MSI itself */ ++ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Read the MSI config to figure out how many IRQs this device ++ * wants. Most devices only want 1, which will give ++ * configured_private_bits and request_private_bits equal 0. ++ */ ++ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); ++ ++ /* ++ * If the number of private bits has been configured then use ++ * that value instead of the requested number. This gives the ++ * driver the chance to override the number of interrupts ++ * before calling pci_enable_msi(). ++ */ ++ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; ++ if (configured_private_bits == 0) { ++ /* Nothing is configured, so use the hardware requested size */ ++ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; ++ } ++ else { ++ /* ++ * Use the number of configured bits, assuming the ++ * driver wanted to override the hardware request ++ * value. ++ */ ++ request_private_bits = configured_private_bits; ++ } ++ ++ /* ++ * The PCI 2.3 spec mandates that there are at most 32 ++ * interrupts. If this device asks for more, only give it one. ++ */ ++ if (request_private_bits > 5) { ++ request_private_bits = 0; ++ } ++again: ++ /* ++ * The IRQs have to be aligned on a power of two based on the ++ * number being requested. ++ */ ++ irq_step = (1 << request_private_bits); ++ ++ /* Mask with one bit for each IRQ */ ++ search_mask = (1 << irq_step) - 1; ++ ++ /* ++ * We're going to search msi_free_irq_bitmask_lock for zero ++ * bits. This represents an MSI interrupt number that isn't in ++ * use. ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { ++ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; ++ break; ++ } ++ } ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ /* Make sure the search for available interrupts didn't fail */ ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ if (request_private_bits) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " ++ "interrupts, trying just one", __func__, 1 << request_private_bits); ++ request_private_bits = 0; ++ goto again; ++ } ++ else { ++ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ } ++ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; ++ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); ++ ++ /* ++ * Initialize MSI. This has to match the memory-write endianess from the device ++ * Address bits [23:12] ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | ++ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | ++ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ ++ /* Enable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", ++ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); ++ ++ /* Update the number of IRQs the device has available to it */ ++ control &= ~PCI_MSI_FLAGS_QSIZE; ++ control |= (request_private_bits << 4); ++ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); ++ ++ set_irq_msi(irq, desc); ++ msg.address_hi = 0x0; ++ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; ++ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); ++ ++ write_msi_msg(irq, &msg); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++ return 0; ++} ++ ++static int ++pcie_msi_irq_to_port(unsigned int irq, int *port) ++{ ++ int ret = 0; ++ ++ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || ++ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { ++ *port = IFX_PCIE_PORT0; ++ } ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || ++ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { ++ *port = IFX_PCIE_PORT1; ++ } ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ else { ++ printk(KERN_ERR "%s: Attempted to teardown illegal " ++ "MSI interrupt (%d)\n", __func__, irq); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/** ++ * \fn void arch_teardown_msi_irq(unsigned int irq) ++ * \brief Called when a device no longer needs its MSI interrupts. All ++ * MSI interrupts for the device are freed. ++ * ++ * \param irq The devices first irq number. There may be multple in sequence. ++ * \return none ++ * \ingroup IFX_PCIE_MSI ++ */ ++void ++arch_teardown_msi_irq(unsigned int irq) ++{ ++ int pos; ++ int number_irqs; ++ u16 bitmask; ++ int pcie_port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); ++ ++ BUG_ON(irq > INT_NUM_IM4_IRL31); ++ ++ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { ++ return; ++ } ++ ++ /* Shift the mask to the correct bit location, not always correct ++ * Probally, the first match will be chosen. ++ */ ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { ++ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) ++ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { ++ break; ++ } ++ } ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); ++ return; ++ } ++ spin_lock(&ifx_pcie_msi_lock); ++ /* Disable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); ++ spin_unlock(&ifx_pcie_msi_lock); ++ /* ++ * Count the number of IRQs we need to free by looking at the ++ * msi_multiple_irq_bitmask. Each bit set means that the next ++ * IRQ is also owned by this device. ++ */ ++ number_irqs = 0; ++ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && ++ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { ++ number_irqs++; ++ } ++ number_irqs++; ++ ++ /* Mask with one bit for each IRQ */ ++ bitmask = (1 << number_irqs) - 1; ++ ++ bitmask <<= pos; ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { ++ printk(KERN_ERR "%s: Attempted to teardown MSI " ++ "interrupt (%d) not in use\n", __func__, irq); ++ return; ++ } ++ /* Checks are done, update the in use bitmask */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); ++ spin_unlock(&ifx_pcie_msi_lock); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++} ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); ++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_phy.c +@@ -0,0 +1,478 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_phy.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe PHY sub module ++** ++** DATE : 14 May 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 14 May,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_phy.c ++ \ingroup IFX_PCIE ++ \brief PCIe PHY PLL register programming source file ++*/ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++/* PCIe PDI only supports 16 bit operation */ ++ ++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ ++ ((*(volatile u16 *) (__addr)) = (__data)) ++ ++#define IFX_PCIE_PHY_REG_READ16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ ++ u16 read_data; \ ++ u16 write_data; \ ++ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ ++ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ ++ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ ++} while (0) ++ ++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ ++ ++//#define IFX_PCI_PHY_REG_DUMP ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++static void ++pcie_phy_reg_dump(int pcie_port) ++{ ++ printk("PLL REGFILE\n"); ++ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); ++ ++ printk("TX1 REGFILE\n"); ++ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); ++ ++ printk("TX2 REGFILE\n"); ++ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); ++ ++ printk("RX1 REGFILE\n"); ++ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); ++ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); ++ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); ++} ++#endif /* IFX_PCI_PHY_REG_DUMP */ ++ ++static void ++pcie_phy_comm_setup(int pcie_port) ++{ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* Improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* Reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++} ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++static void ++pcie_phy_36mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE ++static void ++pcie_phy_36mhz_ssc_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* Increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* Force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* Predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); ++ ++ /* improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE ++static void ++pcie_phy_25mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); ++ ++ /* en_ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE ++static void ++pcie_phy_100mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ ++ ++static int ++pcie_phy_wait_startup_ready(int pcie_port) ++{ ++ int i; ++ ++ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { ++ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { ++ break; ++ } ++ udelay(10); ++ } ++ if (i >= IFX_PCIE_PLL_TIMEOUT) { ++ printk(KERN_ERR "%s PLL Link timeout\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static void ++pcie_phy_load_enable(int pcie_port, int slice) ++{ ++ /* Set the load_en of tx/rx slice to '1' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_disable(int pcie_port, int slice) ++{ ++ /* set the load_en of tx/rx slice to '0' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_war(int pcie_port) ++{ ++ int slice; ++ ++ for (slice = 1; slice < 4; slice++) { ++ pcie_phy_load_enable(pcie_port, slice); ++ udelay(1); ++ pcie_phy_load_disable(pcie_port, slice); ++ } ++} ++ ++static void ++pcie_phy_tx2_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx1_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx_modulation_war(int pcie_port) ++{ ++ int i; ++ ++#define PCIE_PHY_MODULATION_NUM 5 ++ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { ++ pcie_phy_tx2_modulation(pcie_port); ++ pcie_phy_tx1_modulation(pcie_port); ++ } ++#undef PCIE_PHY_MODULATION_NUM ++} ++ ++void ++pcie_phy_clock_mode_setup(int pcie_port) ++{ ++ pcie_pdi_big_endian(pcie_port); ++ ++ /* Enable PDI to access PCIe PHY register */ ++ pcie_pdi_pmu_enable(pcie_port); ++ ++ /* Configure PLL and PHY clock */ ++ pcie_phy_comm_setup(pcie_port); ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ pcie_phy_36mhz_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) ++ pcie_phy_36mhz_ssc_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) ++ pcie_phy_25mhz_mode_setup(pcie_port); ++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) ++ pcie_phy_100mhz_mode_setup(pcie_port); ++#else ++ #error "PCIE PHY Clock Mode must be chosen first!!!!" ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++ /* Enable PCIe PHY and make PLL setting take effect */ ++ pcie_phy_pmu_enable(pcie_port); ++ ++ /* Check if we are in startup_ready status */ ++ pcie_phy_wait_startup_ready(pcie_port); ++ ++ pcie_phy_load_war(pcie_port); ++ ++ /* Apply TX modulation workarounds */ ++ pcie_phy_tx_modulation_war(pcie_port); ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.c +@@ -0,0 +1,176 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.c ++** PROJECT : IFX UEIP ++** MODULES : PCIE Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIE Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_PM Power Management functions ++ \ingroup IFX_PCIE ++ \brief IFX PCIE Root Complex Driver power management functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_pm.c ++ \ingroup IFX_PCIE ++ \brief source file for PCIE Root Complex Driver Power Management ++*/ ++ ++#ifndef EXPORT_SYMTAB ++#define EXPORT_SYMTAB ++#endif ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++ ++/* Project header */ ++#include ++#include ++#include ++#include ++#include "ifxmips_pcie_pm.h" ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++ * \brief the callback function to request pmcu state in the power management hardware-dependent module ++ * ++ * \param pmcuState This parameter is a PMCU state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++{ ++ switch(pmcuState) ++ { ++ case IFX_PMCU_STATE_D0: ++ return IFX_PMCU_RETURN_SUCCESS; ++ case IFX_PMCU_STATE_D1: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D2: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating ++ return IFX_PMCU_RETURN_SUCCESS; ++ default: ++ return IFX_PMCU_RETURN_DENIED; ++ } ++} ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++ * \brief the callback function to get pmcu state in the power management hardware-dependent module ++ ++ * \param pmcuState Pointer to return power state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_init(void) ++ * \brief Register with central PMCU module ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_init(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuRegister; ++ ++ /* XXX, hook driver context */ ++ ++ /* State function register */ ++ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); ++ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuRegister.pmcuModuleNr = 0; ++ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; ++ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; ++ pmcuRegister.pre = ifx_pcie_pmcu_prechange; ++ pmcuRegister.post= ifx_pcie_pmcu_postchange; ++ ifx_pmcu_register(&pmcuRegister); ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_exit(void) ++ * \brief Unregister with central PMCU module ++ * ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_exit(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuUnRegister; ++ ++ /* XXX, hook driver context */ ++ ++ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuUnRegister.pmcuModuleNr = 0; ++ ifx_pmcu_unregister(&pmcuUnRegister); ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.h ++** PROJECT : IFX UEIP ++** MODULES : PCIe Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_pm.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe Root Complex Driver Power Management ++*/ ++ ++#ifndef IFXMIPS_PCIE_PM_H ++#define IFXMIPS_PCIE_PM_H ++ ++void ifx_pcie_pmcu_init(void); ++void ifx_pcie_pmcu_exit(void); ++ ++#endif /* IFXMIPS_PCIE_PM_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_reg.h +@@ -0,0 +1,1001 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#endif /* IFXMIPS_PCIE_REG_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -0,0 +1,269 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_vr9.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver vr9 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_VR9_H ++#define IFXMIPS_PCIE_VR9_H ++ ++#include ++#include ++ ++#include ++#include ++ ++#define IFX_PCIE_GPIO_RESET 494 ++ ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) ++#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) ++#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) ++#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) ++#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ++ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ ++/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* Enable AHB bus master/slave */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ahb"); ++ clk_enable(clk); ++ ++ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); ++ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_enable(clk); ++ ++ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_disable(clk); ++ ++// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ /* SRAM2PDI endianness control. */ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ /* Enable PDI to access PCIe PHY register */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "pdi"); ++ clk_enable(clk); ++ //PDI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ ++ reg |= 0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ /* Reset PCIe PHY & Core, bit 22 */ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg |= 0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); ++// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ctl"); ++ clk_enable(clk); ++ clk = clk_get_sys("1d900000.pcie", "bus"); ++ clk_enable(clk); ++ ++ /* PCIe Core controller enabled */ ++// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ ++ /* Enable PCIe L0 Clock */ ++// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ struct clk *clk; ++ pcie_msi_pic_init(pcie_port); ++ clk = clk_get_sys("ltq_pcie", "msi"); ++ clk_enable(clk); ++// MSI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/arch/mips/pci/pci.c ++++ b/arch/mips/pci/pci.c +@@ -251,6 +251,31 @@ static int __init pcibios_init(void) + + subsys_initcall(pcibios_init); + ++int pcibios_host_nr(void) ++{ ++ int count; ++ struct pci_controller *hose; ++ for (count = 0, hose = hose_head; hose; hose = hose->next, count++) { ++ ; ++ } ++ return count; ++} ++EXPORT_SYMBOL(pcibios_host_nr); ++ ++int pcibios_1st_host_bus_nr(void) ++{ ++ int bus_nr = 0; ++ struct pci_controller *hose = hose_head; ++ ++ if (hose != NULL) { ++ if (hose->bus != NULL) { ++ bus_nr = hose->bus->number + 1; ++ } ++ } ++ return bus_nr; ++} ++EXPORT_SYMBOL(pcibios_1st_host_bus_nr); ++ + static int pcibios_enable_resources(struct pci_dev *dev, int mask) + { + u16 cmd, old_cmd; +--- /dev/null ++++ b/arch/mips/pci/pcie-lantiq.h +@@ -0,0 +1,1305 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++#include ++#include ++#include ++#include ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++//#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ if (g_pcie_debug_flag & (_m)) { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++ } \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define IFX_PCIE_GPIO_RESET 38 ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "ahb"); ++ clk_enable(clk); ++ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "phy"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1<PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "pdi"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1< 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/drivers/pci/pcie/aer/Kconfig ++++ b/drivers/pci/pcie/aer/Kconfig +@@ -19,6 +19,7 @@ config PCIEAER + config PCIE_ECRC + bool "PCI Express ECRC settings control" + depends on PCIEAER ++ default n + help + Used to override firmware/bios settings for PCI Express ECRC + (transaction layer end-to-end CRC checking). +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -1156,6 +1156,8 @@ void pci_walk_bus(struct pci_bus *top, i + void *userdata); + int pci_cfg_space_size(struct pci_dev *dev); + unsigned char pci_bus_max_busnr(struct pci_bus *bus); ++int pcibios_host_nr(void); ++int pcibios_1st_host_bus_nr(void); + void pci_setup_bridge(struct pci_bus *bus); + resource_size_t pcibios_window_alignment(struct pci_bus *bus, + unsigned long type); +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -1050,6 +1050,12 @@ + #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 + #define PCI_DEVICE_ID_SGI_IOC4 0x100a + ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x00 ++ + #define PCI_VENDOR_ID_WINBOND 0x10ad + #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 + #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-3.18/0002-MIPS-lantiq-dtb-image-hack.patch b/target/linux/lantiq/patches-3.18/0002-MIPS-lantiq-dtb-image-hack.patch new file mode 100644 index 0000000..6919c70 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0002-MIPS-lantiq-dtb-image-hack.patch @@ -0,0 +1,31 @@ +From 17348293f7f8103c97c8d2a6b0ef36eae06ec371 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 13 Mar 2013 09:36:16 +0100 +Subject: [PATCH 02/36] MIPS: lantiq: dtb image hack + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/Makefile | 2 -- + arch/mips/lantiq/prom.c | 4 +++- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -58,6 +58,8 @@ static void __init prom_init_cmdline(voi + } + } + ++extern struct boot_param_header __image_dtb; ++ + void __init plat_mem_setup(void) + { + ioport_resource.start = IOPORT_RESOURCE_START; +@@ -71,7 +73,7 @@ void __init plat_mem_setup(void) + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ +- __dt_setup_arch(__dtb_start); ++ __dt_setup_arch(&__image_dtb); + } + + void __init device_tree_init(void) diff --git a/target/linux/lantiq/patches-3.18/0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch b/target/linux/lantiq/patches-3.18/0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch new file mode 100644 index 0000000..cc281b6 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch @@ -0,0 +1,86 @@ +From 16e315864132b59749faff739230daf4cee9abbb Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 13 Mar 2013 10:04:01 +0100 +Subject: [PATCH 03/36] MIPS: lantiq: handle vmmc memory reservation + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/xway/Makefile | 2 ++ + arch/mips/lantiq/xway/vmmc.c | 63 ++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 65 insertions(+) + create mode 100644 arch/mips/lantiq/xway/vmmc.c + +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,3 +1,5 @@ + obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o + ++obj-y += vmmc.o ++ + obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/vmmc.c +@@ -0,0 +1,63 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2012 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++static unsigned int *cp1_base = 0; ++unsigned int* ltq_get_cp1_base(void) ++{ ++ if (!cp1_base) ++ panic("no cp1 base was set\n"); ++ return cp1_base; ++} ++EXPORT_SYMBOL(ltq_get_cp1_base); ++ ++static int vmmc_probe(struct platform_device *pdev) ++{ ++#define CP1_SIZE (1 << 20) ++ int gpio_count; ++ dma_addr_t dma; ++ cp1_base = ++ (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC)); ++ ++ gpio_count = of_gpio_count(pdev->dev.of_node); ++ while (gpio_count > 0) { ++ enum of_gpio_flags flags; ++ int gpio = of_get_gpio_flags(pdev->dev.of_node, --gpio_count, &flags); ++ if (gpio_request(gpio, "vmmc-relay")) ++ continue; ++ dev_info(&pdev->dev, "requested GPIO %d\n", gpio); ++ gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); ++ } ++ ++ dev_info(&pdev->dev, "reserved %dMB at 0x%p", CP1_SIZE >> 20, cp1_base); ++ ++ return 0; ++} ++ ++static const struct of_device_id vmmc_match[] = { ++ { .compatible = "lantiq,vmmc" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, vmmc_match); ++ ++static struct platform_driver vmmc_driver = { ++ .probe = vmmc_probe, ++ .driver = { ++ .name = "lantiq,vmmc", ++ .owner = THIS_MODULE, ++ .of_match_table = vmmc_match, ++ }, ++}; ++ ++module_platform_driver(vmmc_driver); diff --git a/target/linux/lantiq/patches-3.18/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-3.18/0004-MIPS-lantiq-add-atm-hack.patch new file mode 100644 index 0000000..39b5e5b --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0004-MIPS-lantiq-add-atm-hack.patch @@ -0,0 +1,500 @@ +From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:25 +0200 +Subject: [PATCH 04/36] MIPS: lantiq: add atm hack + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ + arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ + arch/mips/lantiq/irq.c | 2 + + arch/mips/mm/cache.c | 2 + + include/uapi/linux/atm.h | 6 + + net/atm/common.c | 6 + + net/atm/proc.c | 2 +- + 7 files changed, 416 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_atm.h ++** PROJECT : UEIP ++** MODULES : ATM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global ATM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_ATM_H ++#define IFX_ATM_H ++ ++ ++ ++/*! ++ \defgroup IFX_ATM UEIP Project - ATM driver module ++ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_IOCTL IOCTL Commands ++ \ingroup IFX_ATM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_STRUCT Structures ++ \ingroup IFX_ATM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_atm.h ++ \ingroup IFX_ATM ++ \brief ATM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ATM MIB ++ */ ++ ++/*! ++ \struct atm_cell_ifEntry_t ++ \brief Structure used for Cell Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifInErrors; /*!< counter of error ingress cells */ ++ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ ++ __u32 ifOutErrors; /*!< counter of error egress cells */ ++} atm_cell_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_ifEntry_t ++ \brief Structure used for AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifInUcastPkts; /*!< counter of ingress packets */ ++ __u32 ifOutUcastPkts; /*!< counter of egress packets */ ++ __u32 ifInErrors; /*!< counter of error ingress packets */ ++ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ ++ __u32 ifOutErros; /*!< counter of error egress packets */ ++ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ ++} atm_aal5_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_vcc_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ This structure is a part of structure "atm_aal5_vcc_x_t". ++ */ ++typedef struct { ++ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ ++ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet ++ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ ++} atm_aal5_vcc_t; ++ ++/*! ++ \struct atm_aal5_vcc_x_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". ++ */ ++typedef struct { ++ int vpi; /*!< VPI of the VCC to get MIB counters */ ++ int vci; /*!< VCI of the VCC to get MIB counters */ ++ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ ++} atm_aal5_vcc_x_t; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief ATM IOCTL Magic Number ++ */ ++#define PPE_ATM_IOC_MAGIC 'o' ++/*! ++ \brief ATM IOCTL Command - Get Cell Level MIB Counters ++ ++ This command is obsolete. User can get cell level MIB from DSL API. ++ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters ++ ++ Get AAL5 packet counters. ++ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get Per PVC MIB Counters ++ ++ Get AAL5 packet counters for each PVC. ++ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. ++ */ ++#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) ++/*! ++ \brief Total Number of ATM IOCTL Commands ++ */ ++#define PPE_ATM_IOC_MAXNR 3 ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_ATM_H ++ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h +@@ -0,0 +1,203 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ptm.h ++** PROJECT : UEIP ++** MODULES : PTM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global PTM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_PTM_H ++#define IFX_PTM_H ++ ++ ++ ++/*! ++ \defgroup IFX_PTM UEIP Project - PTM driver module ++ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_IOCTL IOCTL Commands ++ \ingroup IFX_PTM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_STRUCT Structures ++ \ingroup IFX_PTM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_ptm.h ++ \ingroup IFX_PTM ++ \brief PTM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_PTM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief PTM IOCTL Command - Get codeword MIB counters. ++ ++ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. ++ */ ++#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 ++/*! ++ \brief PTM IOCTL Command - Get packet MIB counters. ++ ++ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. ++ */ ++#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 ++/*! ++ \brief PTM IOCTL Command - Get firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 ++/*! ++ \brief PTM IOCTL Command - Set firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 ++/*! ++ \brief PTM IOCTL Command - Program priority value to TX queue mapping. ++ ++ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. ++ */ ++#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_PTM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Data Type ++ */ ++ ++/*! ++ \typedef PTM_CW_IF_ENTRY_T ++ \brief Wrapping of structure "ptm_cw_ifEntry_t". ++ */ ++/*! ++ \struct ptm_cw_ifEntry_t ++ \brief Structure used for CodeWord level MIB counters. ++ */ ++typedef struct ptm_cw_ifEntry_t { ++ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ ++ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ ++ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ ++ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ ++ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ ++} PTM_CW_IF_ENTRY_T; ++ ++/*! ++ \typedef PTM_FRAME_MIB_T ++ \brief Wrapping of structure "ptm_frame_mib_t". ++ */ ++/*! ++ \struct ptm_frame_mib_t ++ \brief Structure used for packet level MIB counters. ++ */ ++typedef struct ptm_frame_mib_t { ++ uint32_t RxCorrect; /*!< output, number of ingress packet */ ++ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ ++ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ ++ uint32_t TxSend; /*!< output, number of egress packet */ ++} PTM_FRAME_MIB_T; ++ ++/*! ++ \typedef IFX_PTM_CFG_T ++ \brief Wrapping of structure "ptm_cfg_t". ++ */ ++/*! ++ \struct ptm_cfg_t ++ \brief Structure used for ETH/TC CRC configuration. ++ */ ++typedef struct ptm_cfg_t { ++ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ ++ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ ++ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ ++ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ ++ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ ++ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ ++ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ ++} IFX_PTM_CFG_T; ++ ++/*! ++ \typedef IFX_PTM_PRIO_Q_MAP_T ++ \brief Wrapping of structure "ppe_prio_q_map". ++ */ ++/*! ++ \struct ppe_prio_q_map ++ \brief Structure used for Priority Value to TX Queue mapping. ++ */ ++typedef struct ppe_prio_q_map { ++ int pkt_prio; ++ int qid; ++ int vpi; // ignored in eth interface ++ int vci; // ignored in eth interface ++} IFX_PTM_PRIO_Q_MAP_T; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_PTM_H ++ +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_dat + ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); + ltq_icu_w32(im, BIT(offset), isr); + } ++EXPORT_SYMBOL(ltq_mask_and_ack_irq); + + static void ltq_ack_irq(struct irq_data *d) + { +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -59,6 +59,8 @@ void (*_dma_cache_wback)(unsigned long s + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + + EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_wback); ++EXPORT_SYMBOL(_dma_cache_inv); + + #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ + +--- a/include/uapi/linux/atm.h ++++ b/include/uapi/linux/atm.h +@@ -130,8 +130,14 @@ + #define ATM_ABR 4 + #define ATM_ANYCLASS 5 /* compatible with everything */ + ++#define ATM_VBR_NRT ATM_VBR ++#define ATM_VBR_RT 6 ++#define ATM_UBR_PLUS 7 ++#define ATM_GFR 8 ++ + #define ATM_MAX_PCR -1 /* maximum available PCR */ + ++ + struct atm_trafprm { + unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ + int max_pcr; /* maximum PCR in cells per second */ +--- a/net/atm/common.c ++++ b/net/atm/common.c +@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc + write_unlock_irq(&vcc_sklist_lock); + } + ++struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; ++EXPORT_SYMBOL(ifx_atm_alloc_tx); ++ + static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size) + { + struct sk_buff *skb; + struct sock *sk = sk_atm(vcc); + ++ if (ifx_atm_alloc_tx != NULL) ++ return ifx_atm_alloc_tx(vcc, size); ++ + if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) { + pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", + sk_wmem_alloc_get(sk), size, sk->sk_sndbuf); +--- a/net/atm/proc.c ++++ b/net/atm/proc.c +@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil + static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) + { + static const char *const class_name[] = { +- "off", "UBR", "CBR", "VBR", "ABR"}; ++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; + static const char *const aal_name[] = { + "---", "1", "2", "3/4", /* 0- 3 */ + "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-3.18/0005-MIPS-lantiq-add-reset-controller-api-support.patch b/target/linux/lantiq/patches-3.18/0005-MIPS-lantiq-add-reset-controller-api-support.patch new file mode 100644 index 0000000..3129019 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0005-MIPS-lantiq-add-reset-controller-api-support.patch @@ -0,0 +1,90 @@ +From 223f1c46e109a8420765aee099a5d1dc4ab7ee98 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 3 Sep 2013 13:18:12 +0200 +Subject: [PATCH 05/36] MIPS: lantiq: add reset-controller api support + +Add a reset-controller binding for the reset registers found on the lantiq +SoC. + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/xway/reset.c | 61 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 61 insertions(+) + +--- a/arch/mips/lantiq/xway/reset.c ++++ b/arch/mips/lantiq/xway/reset.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + + #include + +@@ -113,6 +114,66 @@ void ltq_reset_once(unsigned int module, + ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ); + } + ++static int ltq_assert_device(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ u32 val; ++ ++ if (id < 8) ++ return -1; ++ ++ val = ltq_rcu_r32(RCU_RST_REQ); ++ val |= BIT(id); ++ ltq_rcu_w32(val, RCU_RST_REQ); ++ ++ return 0; ++} ++ ++static int ltq_deassert_device(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ u32 val; ++ ++ if (id < 8) ++ return -1; ++ ++ val = ltq_rcu_r32(RCU_RST_REQ); ++ val &= ~BIT(id); ++ ltq_rcu_w32(val, RCU_RST_REQ); ++ ++ return 0; ++} ++ ++static int ltq_reset_device(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ ltq_assert_device(rcdev, id); ++ return ltq_deassert_device(rcdev, id); ++} ++ ++static struct reset_control_ops reset_ops = { ++ .reset = ltq_reset_device, ++ .assert = ltq_assert_device, ++ .deassert = ltq_deassert_device, ++}; ++ ++static struct reset_controller_dev reset_dev = { ++ .ops = &reset_ops, ++ .owner = THIS_MODULE, ++ .nr_resets = 32, ++ .of_reset_n_cells = 1, ++}; ++ ++void ltq_rst_init(void) ++{ ++ reset_dev.of_node = of_find_compatible_node(NULL, NULL, ++ "lantiq,xway-reset"); ++ if (!reset_dev.of_node) ++ pr_err("Failed to find reset controller node"); ++ else ++ reset_controller_register(&reset_dev); ++} ++ + static void ltq_machine_restart(char *command) + { + local_irq_disable(); diff --git a/target/linux/lantiq/patches-3.18/0006-MIPS-lantiq-reboot-gphy-on-restart.patch b/target/linux/lantiq/patches-3.18/0006-MIPS-lantiq-reboot-gphy-on-restart.patch new file mode 100644 index 0000000..1af4fa7 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0006-MIPS-lantiq-reboot-gphy-on-restart.patch @@ -0,0 +1,29 @@ +From f81979f4b297693ac70616feaa4a79bdcb11db35 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:55:57 +0200 +Subject: [PATCH 06/36] MIPS: lantiq: reboot gphy on restart + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/xway/reset.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +--- a/arch/mips/lantiq/xway/reset.c ++++ b/arch/mips/lantiq/xway/reset.c +@@ -176,8 +176,15 @@ void ltq_rst_init(void) + + static void ltq_machine_restart(char *command) + { ++ u32 val = ltq_rcu_r32(RCU_RST_REQ); ++ ++ if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) ++ val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200; ++ ++ val |= RCU_RD_SRST; ++ + local_irq_disable(); +- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ); ++ ltq_rcu_w32(val, RCU_RST_REQ); + unreachable(); + } + diff --git a/target/linux/lantiq/patches-3.18/0007-MIPS-lantiq-add-basic-tffs-driver.patch b/target/linux/lantiq/patches-3.18/0007-MIPS-lantiq-add-basic-tffs-driver.patch new file mode 100644 index 0000000..7081373 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0007-MIPS-lantiq-add-basic-tffs-driver.patch @@ -0,0 +1,111 @@ +From d27ec8bb97db0f60d81ab255d51ac4e967362067 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:34:19 +0200 +Subject: [PATCH 07/36] MIPS: lantiq: add basic tffs driver + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/tffs.c | 87 ++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 88 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/lantiq/xway/tffs.c + +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,5 +1,5 @@ + obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o + +-obj-y += vmmc.o ++obj-y += vmmc.o tffs.o + + obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/tffs.c +@@ -0,0 +1,87 @@ ++#include ++#include ++#include ++#include ++ ++struct tffs_entry { ++ uint16_t id; ++ uint16_t len; ++}; ++ ++static struct tffs_id { ++ uint32_t id; ++ char *name; ++ unsigned char *val; ++ uint32_t offset; ++ uint32_t len; ++} ids[] = { ++ { 0x01A9, "annex" }, ++ { 0x0188, "maca" }, ++ { 0x0189, "macb" }, ++ { 0x018a, "macwlan" }, ++ { 0x0195, "macwlan2" }, ++ { 0x018b, "macdsl" }, ++ { 0x01C2, "webgui_pass" }, ++ { 0x01AB, "wlan_key" }, ++}; ++ ++static struct mtd_info *tffs1, *tffs2; ++ ++static struct tffs_id* tffs_find_id(int id) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(ids); i++) ++ if (id == ids[i].id) ++ return &ids[i]; ++ ++ return NULL; ++} ++ ++static void tffs_index(void) ++{ ++ struct tffs_entry *E = NULL; ++ struct tffs_entry entry; ++ int ret, retlen; ++ ++ while ((unsigned int) E + sizeof(struct tffs_entry) < tffs2->size) { ++ struct tffs_id *id; ++ int len; ++ ++ ret = mtd_read(tffs2, (unsigned int) E, sizeof(struct tffs_entry), &retlen, (unsigned char *)&entry); ++ if (ret) ++ return; ++ ++ if (entry.id == 0xffff) ++ return; ++ ++ id = tffs_find_id(entry.id); ++ if (id) { ++ id->offset = (uint32_t) E; ++ id->len = entry.len; ++ id->val = kzalloc(entry.len + 1, GFP_KERNEL); ++ mtd_read(tffs2, ((unsigned int) E) + sizeof(struct tffs_entry), entry.len, &retlen, id->val); ++ ++ } ++ //printk(KERN_INFO "found entry at 0x%08X-> [<0x%x> %u bytes]\n", (uint32_t) E, entry.id, entry.len); ++ if (id && id->name) ++ printk(KERN_INFO "found entry name -> %s=%s\n", id->name, id->val); ++ ++ len = (entry.len + 3) & ~0x03; ++ E = (struct tffs_entry *)(((unsigned int)E) + sizeof(struct tffs_entry) + len); ++ } ++} ++ ++static int __init tffs_init(void) ++{ ++ tffs1 = get_mtd_device_nm("tffs (1)"); ++ tffs2 = get_mtd_device_nm("tffs (2)"); ++ if (IS_ERR(tffs1) || IS_ERR(tffs2)) ++ return -1; ++ ++ tffs_index(); ++ ++ return 0; ++} ++late_initcall(tffs_init); ++ diff --git a/target/linux/lantiq/patches-3.18/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-3.18/0008-MIPS-lantiq-backport-old-timer-code.patch new file mode 100644 index 0000000..5525503 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0008-MIPS-lantiq-backport-old-timer-code.patch @@ -0,0 +1,1028 @@ +From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:30:56 +0200 +Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ + 3 files changed, 1001 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h + create mode 100644 arch/mips/lantiq/xway/timer.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h +@@ -0,0 +1,155 @@ ++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++ ++ ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * Available Timer/Counter Index ++ */ ++#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) ++#define TIMER_ANY 0x00 ++#define TIMER1A TIMER(1, 0) ++#define TIMER1B TIMER(1, 1) ++#define TIMER2A TIMER(2, 0) ++#define TIMER2B TIMER(2, 1) ++#define TIMER3A TIMER(3, 0) ++#define TIMER3B TIMER(3, 1) ++ ++/* ++ * Flag of Timer/Counter ++ * These flags specify the way in which timer is configured. ++ */ ++/* Bit size of timer/counter. */ ++#define TIMER_FLAG_16BIT 0x0000 ++#define TIMER_FLAG_32BIT 0x0001 ++/* Switch between timer and counter. */ ++#define TIMER_FLAG_TIMER 0x0000 ++#define TIMER_FLAG_COUNTER 0x0002 ++/* Stop or continue when overflowing/underflowing. */ ++#define TIMER_FLAG_ONCE 0x0000 ++#define TIMER_FLAG_CYCLIC 0x0004 ++/* Count up or counter down. */ ++#define TIMER_FLAG_UP 0x0000 ++#define TIMER_FLAG_DOWN 0x0008 ++/* Count on specific level or edge. */ ++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 ++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 ++#define TIMER_FLAG_RISE_EDGE 0x0010 ++#define TIMER_FLAG_FALL_EDGE 0x0020 ++#define TIMER_FLAG_ANY_EDGE 0x0030 ++/* Signal is syncronous to module clock or not. */ ++#define TIMER_FLAG_UNSYNC 0x0000 ++#define TIMER_FLAG_SYNC 0x0080 ++/* Different interrupt handle type. */ ++#define TIMER_FLAG_NO_HANDLE 0x0000 ++#if defined(__KERNEL__) ++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 ++#endif // defined(__KERNEL__) ++#define TIMER_FLAG_SIGNAL 0x0300 ++/* Internal clock source or external clock source */ ++#define TIMER_FLAG_INT_SRC 0x0000 ++#define TIMER_FLAG_EXT_SRC 0x1000 ++ ++ ++/* ++ * ioctl Command ++ */ ++#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ ++#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ ++#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ ++#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ ++#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ ++#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ ++#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ ++#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ ++ ++/* ++ * Data Type Used to Call ioctl ++ */ ++struct gptu_ioctl_param { ++ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field is ID of expected * ++ * timer/counter. If it's zero, a timer/counter would * ++ * be dynamically allocated and ID would be stored in * ++ * this field. * ++ * In command GPTU_GET_COUNT_VALUE, this field is * ++ * ignored. * ++ * In other command, this field is ID of timer/counter * ++ * allocated. */ ++ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field contains flags to * ++ * specify how to configure timer/counter. * ++ * In command GPTU_START_TIMER, zero indicate start * ++ * and non-zero indicate resume timer/counter. * ++ * In other command, this field is ignored. */ ++ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * ++ * init/reload value. * ++ * In command GPTU_SET_TIMER, this field contains * ++ * frequency (0.001Hz) of timer. * ++ * In command GPTU_GET_COUNT_VALUE, current count * ++ * value would be stored in this field. * ++ * In command GPTU_CALCULATE_DIVIDER, this field * ++ * contains frequency wanted, and after calculation, * ++ * divider would be stored in this field to overwrite * ++ * the frequency. * ++ * In other command, this field is ignored. */ ++ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains process * ++ * ID to which signal would be sent. * ++ * In other command, this field is ignored. */ ++ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains signal * ++ * number which would be sent. * ++ * In other command, this field is ignored. */ ++}; ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++typedef void (*timer_callback)(unsigned long arg); ++ ++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); ++extern int lq_free_timer(unsigned int); ++extern int lq_start_timer(unsigned int, int); ++extern int lq_stop_timer(unsigned int); ++extern int lq_reset_counter_flags(u32 timer, u32 flags); ++extern int lq_get_count_value(unsigned int, unsigned long *); ++extern u32 lq_cal_divider(unsigned long); ++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); ++extern int lq_set_counter(unsigned int timer, unsigned int flag, ++ u32 reload, unsigned long arg1, unsigned long arg2); ++ ++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,4 @@ +-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o ++obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o + + obj-y += vmmc.o tffs.o + +--- /dev/null ++++ b/arch/mips/lantiq/xway/timer.c +@@ -0,0 +1,845 @@ ++#ifndef CONFIG_SOC_AMAZON_SE ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "../clk.h" ++ ++#include ++#include ++#include ++ ++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 ++ ++#ifdef TIMER1A ++#define FIRST_TIMER TIMER1A ++#else ++#define FIRST_TIMER 2 ++#endif ++ ++/* ++ * GPTC divider is set or not. ++ */ ++#define GPTU_CLC_RMC_IS_SET 0 ++ ++/* ++ * Timer Interrupt (IRQ) ++ */ ++/* Must be adjusted when ICU driver is available */ ++#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) ++ ++/* ++ * Bits Operation ++ */ ++#define GET_BITS(x, msb, lsb) \ ++ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) ++#define SET_BITS(x, msb, lsb, value) \ ++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ ++ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++ ++/* ++ * GPTU Register Mapping ++ */ ++#define LQ_GPTU (KSEG1 + 0x1E100A00) ++#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) ++#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) ++#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) ++#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) ++#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) ++ ++/* ++ * Clock Control Register ++ */ ++#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) ++#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) ++#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) ++#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) ++#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) ++#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) ++#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) ++ ++#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) ++#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) ++#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) ++ ++/* ++ * ID Register ++ */ ++#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) ++#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) ++#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) ++ ++/* ++ * Control Register of Timer/Counter nX ++ * n is the index of block (1 based index) ++ * X is either A or B ++ */ ++#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) ++#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) ++#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) ++#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) ++#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) ++#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ ++#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) ++#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) ++#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) ++#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) ++ ++#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) ++#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) ++#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) ++#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) ++#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) ++ ++#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) ++#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) ++ ++#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++ ++#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) ++#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) ++#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) ++#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) ++#define TIMER_FLAG_NONE_EDGE 0x0000 ++#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) ++#define TIMER_FLAG_REAL 0x0000 ++#define TIMER_FLAG_INVERT 0x0040 ++#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) ++#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) ++#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) ++#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 ++#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) ++#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) ++ ++struct timer_dev_timer { ++ unsigned int f_irq_on; ++ unsigned int irq; ++ unsigned int flag; ++ unsigned long arg1; ++ unsigned long arg2; ++}; ++ ++struct timer_dev { ++ struct mutex gptu_mutex; ++ unsigned int number_of_timers; ++ unsigned int occupation; ++ unsigned int f_gptu_on; ++ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; ++}; ++ ++ ++unsigned int ltq_get_fpi_bus_clock(int fpi) { ++ struct clk *clk = clk_get_fpi(); ++ return clk_get_rate(clk); ++} ++ ++ ++static long gptu_ioctl(struct file *, unsigned int, unsigned long); ++static int gptu_open(struct inode *, struct file *); ++static int gptu_release(struct inode *, struct file *); ++ ++static struct file_operations gptu_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gptu_ioctl, ++ .open = gptu_open, ++ .release = gptu_release ++}; ++ ++static struct miscdevice gptu_miscdev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "gptu", ++ .fops = &gptu_fops, ++}; ++ ++static struct timer_dev timer_dev; ++ ++static irqreturn_t timer_irq_handler(int irq, void *p) ++{ ++ unsigned int timer; ++ unsigned int flag; ++ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; ++ ++ timer = irq - TIMER_INTERRUPT; ++ if (timer < timer_dev.number_of_timers ++ && dev_timer == &timer_dev.timer[timer]) { ++ /* Clear interrupt. */ ++ ltq_w32(1 << timer, LQ_GPTU_IRNCR); ++ ++ /* Call user hanler or signal. */ ++ flag = dev_timer->flag; ++ if (!(timer & 0x01) ++ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ /* 16-bit timer or timer A of 32-bit timer */ ++ switch (TIMER_FLAG_MASK_HANDLE(flag)) { ++ case TIMER_FLAG_CALLBACK_IN_IRQ: ++ case TIMER_FLAG_CALLBACK_IN_HB: ++ if (dev_timer->arg1) ++ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); ++ break; ++ case TIMER_FLAG_SIGNAL: ++ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); ++ break; ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static inline void lq_enable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ clk_enable(clk); ++ ++ //ltq_pmu_enable(PMU_GPT); ++ ++ /* Set divider as 1, disable write protection for SPEN, enable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x01) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(1) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(0); ++} ++ ++static inline void lq_disable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ ltq_w32(0x00, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ /* Set divider as 0, enable write protection for SPEN, disable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x00) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(0) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(1); ++ ++ clk_enable(clk); ++} ++ ++int lq_request_timer(unsigned int timer, unsigned int flag, ++ unsigned long value, unsigned long arg1, unsigned long arg2) ++{ ++ int ret = 0; ++ unsigned int con_reg, irnen_reg; ++ int n, X; ++ ++ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", ++ timer, flag, value); ++ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) ++ value &= 0xFFFF; ++ else ++ timer &= ~0x01; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ /* ++ * Allocate timer. ++ */ ++ if (timer < FIRST_TIMER) { ++ unsigned int mask; ++ unsigned int shift; ++ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ ++ unsigned int offset = TIMER2A; ++ ++ /* ++ * Pick up a free timer. ++ */ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ mask = 1 << offset; ++ shift = 1; ++ } else { ++ mask = 3 << offset; ++ shift = 2; ++ } ++ for (timer = offset; ++ timer < offset + timer_dev.number_of_timers; ++ timer += shift, mask <<= shift) ++ if (!(timer_dev.occupation & mask)) { ++ timer_dev.occupation |= mask; ++ break; ++ } ++ if (timer >= offset + timer_dev.number_of_timers) { ++ printk("failed![%d]\n", __LINE__); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } else ++ ret = timer; ++ } else { ++ register unsigned int mask; ++ ++ /* ++ * Check if the requested timer is free. ++ */ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if ((timer_dev.occupation & mask)) { ++ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", ++ __LINE__, mask, timer_dev.occupation); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EBUSY; ++ } else { ++ timer_dev.occupation |= mask; ++ ret = 0; ++ } ++ } ++ ++ /* ++ * Prepare control register value. ++ */ ++ switch (TIMER_FLAG_MASK_EDGE(flag)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : ++ GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : ++ GPTU_CON_SRC_EG_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_SYNC(flag) == ++ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : ++ GPTU_CON_SYNC_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_INVERT(flag) == ++ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : ++ GPTU_CON_EXT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_STOP(flag) == ++ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_TYPE(flag) == ++ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : ++ GPTU_CON_CNT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_DIR(flag) == ++ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ /* ++ * Fill up running data. ++ */ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flag; ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; ++ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; ++ ++ /* ++ * Enable GPTU module. ++ */ ++ if (!timer_dev.f_gptu_on) { ++ lq_enable_gptu(); ++ timer_dev.f_gptu_on = 1; ++ } ++ ++ /* ++ * Enable IRQ. ++ */ ++ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = ++ (unsigned long) find_task_by_vpid((int) arg1); ++ ++ irnen_reg = 1 << (timer - FIRST_TIMER); ++ ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL ++ || (TIMER_FLAG_MASK_HANDLE(flag) == ++ TIMER_FLAG_CALLBACK_IN_IRQ ++ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { ++ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; ++ } ++ } else ++ irnen_reg = 0; ++ ++ /* ++ * Write config register, reload value and enable interrupt. ++ */ ++ n = timer >> 1; ++ X = timer & 0x01; ++ *LQ_GPTU_CON(n, X) = con_reg; ++ *LQ_GPTU_RELOAD(n, X) = value; ++ /* printk("reload value = %d\n", (u32)value); */ ++ *LQ_GPTU_IRNEN |= irnen_reg; ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ printk("successful!\n"); ++ return ret; ++} ++EXPORT_SYMBOL(lq_request_timer); ++ ++int lq_free_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ if (GPTU_CON_EN(n, X)) ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); ++ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); ++ ++ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { ++ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; ++ } ++ ++ timer_dev.occupation &= ~mask; ++ if (!timer_dev.occupation && timer_dev.f_gptu_on) { ++ lq_disable_gptu(); ++ timer_dev.f_gptu_on = 0; ++ } ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_free_timer); ++ ++int lq_start_timer(unsigned int timer, int is_resume) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_start_timer); ++ ++int lq_stop_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_stop_timer); ++ ++int lq_reset_counter_flags(u32 timer, u32 flags) ++{ ++ unsigned int oflag; ++ unsigned int mask, con_reg; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ switch (TIMER_FLAG_MASK_EDGE(flags)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); ++ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); ++ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flags; ++ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_CON(n, X) = con_reg; ++ smp_wmb(); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return 0; ++} ++EXPORT_SYMBOL(lq_reset_counter_flags); ++ ++int lq_get_count_value(unsigned int timer, unsigned long *value) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *value = *LQ_GPTU_COUNT(n, X); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_get_count_value); ++ ++u32 lq_cal_divider(unsigned long freq) ++{ ++ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); ++ u32 clock_divider = 1; ++ module_freq = fpi * 1000; ++ do_div(module_freq, clock_divider * freq); ++ return module_freq; ++} ++EXPORT_SYMBOL(lq_cal_divider); ++ ++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, ++ int is_ext_src, unsigned int handle_flag, unsigned long arg1, ++ unsigned long arg2) ++{ ++ unsigned long divider; ++ unsigned int flag; ++ ++ divider = lq_cal_divider(freq); ++ if (divider == 0) ++ return -EINVAL; ++ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) ++ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) ++ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) ++ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN ++ | TIMER_FLAG_MASK_HANDLE(handle_flag); ++ ++ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", ++ timer, freq, divider); ++ return lq_request_timer(timer, flag, divider, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_timer); ++ ++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, ++ unsigned long arg1, unsigned long arg2) ++{ ++ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); ++ return lq_request_timer(timer, flag, reload, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_counter); ++ ++static long gptu_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret; ++ struct gptu_ioctl_param param; ++ ++ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ copy_from_user(¶m, (void *) arg, sizeof(param)); ++ ++ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER ++ || GPTU_SET_COUNTER) && param.timer < 2) ++ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) ++ && !access_ok(VERIFY_WRITE, arg, ++ sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case GPTU_REQUEST_TIMER: ++ ret = lq_request_timer(param.timer, param.flag, param.value, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_FREE_TIMER: ++ ret = lq_free_timer(param.timer); ++ break; ++ case GPTU_START_TIMER: ++ ret = lq_start_timer(param.timer, param.flag); ++ break; ++ case GPTU_STOP_TIMER: ++ ret = lq_stop_timer(param.timer); ++ break; ++ case GPTU_GET_COUNT_VALUE: ++ ret = lq_get_count_value(param.timer, ¶m.value); ++ if (!ret) ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ break; ++ case GPTU_CALCULATE_DIVIDER: ++ param.value = lq_cal_divider(param.value); ++ if (param.value == 0) ++ ret = -EINVAL; ++ else { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_TIMER: ++ ret = lq_set_timer(param.timer, param.value, ++ TIMER_FLAG_MASK_STOP(param.flag) != ++ TIMER_FLAG_ONCE ? 1 : 0, ++ TIMER_FLAG_MASK_SRC(param.flag) == ++ TIMER_FLAG_EXT_SRC ? 1 : 0, ++ TIMER_FLAG_MASK_HANDLE(param.flag) == ++ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : ++ TIMER_FLAG_NO_HANDLE, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_COUNTER: ++ lq_set_counter(param.timer, param.flag, param.value, 0, 0); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ default: ++ ret = -ENOTTY; ++ } ++ ++ return ret; ++} ++ ++static int gptu_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int gptu_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++int __init lq_gptu_init(void) ++{ ++ int ret; ++ unsigned int i; ++ ++ ltq_w32(0, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ memset(&timer_dev, 0, sizeof(timer_dev)); ++ mutex_init(&timer_dev.gptu_mutex); ++ ++ lq_enable_gptu(); ++ timer_dev.number_of_timers = GPTU_ID_CFG * 2; ++ lq_disable_gptu(); ++ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) ++ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; ++ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); ++ ++ ret = misc_register(&gptu_miscdev); ++ if (ret) { ++ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); ++ return ret; ++ } else { ++ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); ++ } ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); ++ if (ret) { ++ for (; i >= 0; i--) ++ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); ++ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); ++ return ret; ++ } else { ++ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; ++ disable_irq(timer_dev.timer[i].irq); ++ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); ++ } ++ } ++ ++ return 0; ++} ++ ++void __exit lq_gptu_exit(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ if (timer_dev.timer[i].f_irq_on) ++ disable_irq(timer_dev.timer[i].irq); ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ } ++ lq_disable_gptu(); ++ misc_deregister(&gptu_miscdev); ++} ++ ++module_init(lq_gptu_init); ++module_exit(lq_gptu_exit); ++ ++#endif diff --git a/target/linux/lantiq/patches-3.18/0009-MIPS-lantiq-command-line-work-around.patch b/target/linux/lantiq/patches-3.18/0009-MIPS-lantiq-command-line-work-around.patch new file mode 100644 index 0000000..88bcbc4 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0009-MIPS-lantiq-command-line-work-around.patch @@ -0,0 +1,21 @@ +From ed348924cd59ef0c8a4bc4e015e2b7e581a00fa8 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 12 Aug 2014 21:40:41 +0200 +Subject: [PATCH 09/36] MIPS: lantiq: command line work around + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/prom.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -74,6 +74,8 @@ void __init plat_mem_setup(void) + * parsed resulting in our memory appearing + */ + __dt_setup_arch(&__image_dtb); ++ ++ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); + } + + void __init device_tree_init(void) diff --git a/target/linux/lantiq/patches-3.18/0010-MIPS-lantiq-export-soc-type.patch b/target/linux/lantiq/patches-3.18/0010-MIPS-lantiq-export-soc-type.patch new file mode 100644 index 0000000..f4cfacf --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0010-MIPS-lantiq-export-soc-type.patch @@ -0,0 +1,39 @@ +From 6804142b47f2634b0657e4dfcec7a34e982b6ddb Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:29:21 +0200 +Subject: [PATCH 10/36] MIPS: lantiq: export soc type +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Ãlvaro Fernández Rojas +--- + arch/mips/include/asm/mach-lantiq/lantiq.h | 2 ++ + arch/mips/lantiq/prom.c | 5 +++++ + 2 files changed, 7 insertions(+) + +--- a/arch/mips/include/asm/mach-lantiq/lantiq.h ++++ b/arch/mips/include/asm/mach-lantiq/lantiq.h +@@ -48,6 +48,8 @@ extern struct clk *clk_get_ppe(void); + extern unsigned char ltq_boot_select(void); + /* find out what caused the last cpu reset */ + extern int ltq_reset_cause(void); ++/* find out the soc type */ ++extern int ltq_soc_type(void); + + #define IOPORT_RESOURCE_START 0x10000000 + #define IOPORT_RESOURCE_END 0xffffffff +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -36,6 +36,11 @@ const char *get_system_type(void) + return soc_info.sys_type; + } + ++int ltq_soc_type(void) ++{ ++ return soc_info.type; ++} ++ + void prom_free_prom_memory(void) + { + } diff --git a/target/linux/lantiq/patches-3.18/0011-lantiq-add-support-for-xrx200-firmware-depending-on-.patch b/target/linux/lantiq/patches-3.18/0011-lantiq-add-support-for-xrx200-firmware-depending-on-.patch new file mode 100644 index 0000000..7a0e1c3 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0011-lantiq-add-support-for-xrx200-firmware-depending-on-.patch @@ -0,0 +1,41 @@ +From 85f0df34dee96048515ef1e01d88524bd579f8e0 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:39:19 +0200 +Subject: [PATCH 11/36] lantiq: add support for xrx200 firmware depending on + soc type +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Ãlvaro Fernández Rojas +--- + arch/mips/lantiq/xway/xrx200_phy_fw.c | 18 +++++++++++++++++- + 1 file changed, 17 insertions(+), 1 deletion(-) + +--- a/arch/mips/lantiq/xway/xrx200_phy_fw.c ++++ b/arch/mips/lantiq/xway/xrx200_phy_fw.c +@@ -24,7 +24,23 @@ static dma_addr_t xway_gphy_load(struct + void *fw_addr; + size_t size; + +- if (of_property_read_string(pdev->dev.of_node, "firmware", &fw_name)) { ++ if (of_get_property(pdev->dev.of_node, "firmware1", NULL) || of_get_property(pdev->dev.of_node, "firmware2", NULL)) { ++ switch(ltq_soc_type()) { ++ case SOC_TYPE_VR9: ++ if (of_property_read_string(pdev->dev.of_node, "firmware1", &fw_name)) { ++ dev_err(&pdev->dev, "failed to load firmware filename\n"); ++ return 0; ++ } ++ break; ++ case SOC_TYPE_VR9_2: ++ if (of_property_read_string(pdev->dev.of_node, "firmware2", &fw_name)) { ++ dev_err(&pdev->dev, "failed to load firmware filename\n"); ++ return 0; ++ } ++ break; ++ } ++ } ++ else if (of_property_read_string(pdev->dev.of_node, "firmware", &fw_name)) { + dev_err(&pdev->dev, "failed to load firmware filename\n"); + return 0; + } diff --git a/target/linux/lantiq/patches-3.18/0012-pinctrl-lantiq-fix-up-pinmux.patch b/target/linux/lantiq/patches-3.18/0012-pinctrl-lantiq-fix-up-pinmux.patch new file mode 100644 index 0000000..ecd143f --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0012-pinctrl-lantiq-fix-up-pinmux.patch @@ -0,0 +1,79 @@ +From 25494c55a4007a1409f53ddbafd661636e47ea34 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 9 Aug 2013 20:38:15 +0200 +Subject: [PATCH 12/36] pinctrl/lantiq: fix up pinmux + +We found out how to set the gphy led pinmuxing. + +Signed-off-by: John Crispin +--- + drivers/pinctrl/pinctrl-xway.c | 28 ++++++++++++++++++++++++++-- + 1 file changed, 26 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/pinctrl-xway.c ++++ b/drivers/pinctrl/pinctrl-xway.c +@@ -609,10 +609,9 @@ static struct pinctrl_desc xway_pctrl_de + .confops = &xway_pinconf_ops, + }; + +-static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, ++static int mux_apply(struct ltq_pinmux_info *info, + int pin, int mux) + { +- struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int port = PORT(pin); + u32 alt1_reg = GPIO_ALT1(pin); + +@@ -632,6 +631,14 @@ static inline int xway_mux_apply(struct + return 0; + } + ++static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, ++ int pin, int mux) ++{ ++ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); ++ ++ return mux_apply(info, pin, mux); ++} ++ + static const struct ltq_cfg_param xway_cfg_params[] = { + {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, + {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN}, +@@ -676,6 +683,10 @@ static int xway_gpio_dir_out(struct gpio + { + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + ++ if (PORT(pin) == PORT3) ++ gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin)); ++ else ++ gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin)); + gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); + xway_gpio_set(chip, pin, val); + +@@ -696,6 +707,18 @@ static void xway_gpio_free(struct gpio_c + pinctrl_free_gpio(gpio); + } + ++static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset) ++{ ++ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); ++ int i; ++ ++ for (i = 0; i < info->num_exin; i++) ++ if (info->exin[i] == offset) ++ return ltq_eiu_get_irq(i); ++ ++ return -1; ++} ++ + static struct gpio_chip xway_chip = { + .label = "gpio-xway", + .direction_input = xway_gpio_dir_in, +@@ -704,6 +727,7 @@ static struct gpio_chip xway_chip = { + .set = xway_gpio_set, + .request = xway_gpio_req, + .free = xway_gpio_free, ++ .to_irq = xway_gpio_to_irq, + .base = -1, + }; + diff --git a/target/linux/lantiq/patches-3.18/0013-MTD-lantiq-xway-fix-invalid-operator.patch b/target/linux/lantiq/patches-3.18/0013-MTD-lantiq-xway-fix-invalid-operator.patch new file mode 100644 index 0000000..c6d3819 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0013-MTD-lantiq-xway-fix-invalid-operator.patch @@ -0,0 +1,24 @@ +From 8e34da603f442624bb70e887d8f42064bb924224 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jul 2013 18:03:54 +0200 +Subject: [PATCH 13/36] MTD: lantiq: xway: fix invalid operator + +xway_read_byte should use a logic or and not an add operator when working out +the nand address. + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -124,7 +124,7 @@ static unsigned char xway_read_byte(stru + int ret; + + spin_lock_irqsave(&ebu_lock, flags); +- ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA)); ++ ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA)); + spin_unlock_irqrestore(&ebu_lock, flags); + + return ret; diff --git a/target/linux/lantiq/patches-3.18/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch b/target/linux/lantiq/patches-3.18/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch new file mode 100644 index 0000000..6a7785b --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch @@ -0,0 +1,44 @@ +From b454cefd675fc1bd3d8c690c1bd1d8f4678e9922 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jul 2013 18:06:39 +0200 +Subject: [PATCH 14/36] MTD: lantiq: xway: the latched command should be + persistent + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -54,6 +54,8 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++static u32 xway_latchcmd; ++ + static void xway_reset_chip(struct nand_chip *chip) + { + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; +@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_inf + unsigned long flags; + + if (ctrl & NAND_CTRL_CHANGE) { +- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR); + if (ctrl & NAND_CLE) +- nandaddr |= NAND_WRITE_CMD; +- else +- nandaddr |= NAND_WRITE_ADDR; +- this->IO_ADDR_W = (void __iomem *) nandaddr; ++ xway_latchcmd = NAND_WRITE_CMD; ++ else if (ctrl & NAND_ALE) ++ xway_latchcmd = NAND_WRITE_ADDR; + } + + if (cmd != NAND_CMD_NONE) { + spin_lock_irqsave(&ebu_lock, flags); +- writeb(cmd, this->IO_ADDR_W); ++ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd)); + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + spin_unlock_irqrestore(&ebu_lock, flags); diff --git a/target/linux/lantiq/patches-3.18/0015-MTD-lantiq-xway-remove-endless-loop.patch b/target/linux/lantiq/patches-3.18/0015-MTD-lantiq-xway-remove-endless-loop.patch new file mode 100644 index 0000000..4bd1668 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0015-MTD-lantiq-xway-remove-endless-loop.patch @@ -0,0 +1,41 @@ +From 76e153079f02d26e3357302d2886a0c8aaaec64d Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jul 2013 18:02:06 +0200 +Subject: [PATCH 15/36] MTD: lantiq: xway: remove endless loop + +The reset loop logic could run into a endless loop. Lets fix it as requested. + +--> http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -59,16 +59,22 @@ static u32 xway_latchcmd; + static void xway_reset_chip(struct nand_chip *chip) + { + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; ++ unsigned long timeout; + unsigned long flags; + + nandaddr &= ~NAND_WRITE_ADDR; + nandaddr |= NAND_WRITE_CMD; + + /* finish with a reset */ ++ timeout = jiffies + msecs_to_jiffies(20); ++ + spin_lock_irqsave(&ebu_lock, flags); + writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr); +- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) +- ; ++ do { ++ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) ++ break; ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); + spin_unlock_irqrestore(&ebu_lock, flags); + } + diff --git a/target/linux/lantiq/patches-3.18/0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch b/target/linux/lantiq/patches-3.18/0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch new file mode 100644 index 0000000..f20878c --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch @@ -0,0 +1,55 @@ +From 65df9d63eaee02c25e879b33dd42aceb78e57842 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jul 2013 17:59:51 +0200 +Subject: [PATCH 16/36] MTD: lantiq: xway: add missing write_buf and read_buf + to nand driver + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -136,6 +136,32 @@ static unsigned char xway_read_byte(stru + return ret; + } + ++static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len) ++{ ++ struct nand_chip *this = mtd->priv; ++ unsigned long nandaddr = (unsigned long) this->IO_ADDR_R; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&ebu_lock, flags); ++ for (i = 0; i < len; i++) ++ buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA)); ++ spin_unlock_irqrestore(&ebu_lock, flags); ++} ++ ++static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ struct nand_chip *this = mtd->priv; ++ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&ebu_lock, flags); ++ for (i = 0; i < len; i++) ++ ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA)); ++ spin_unlock_irqrestore(&ebu_lock, flags); ++} ++ + static int xway_nand_probe(struct platform_device *pdev) + { + struct nand_chip *this = platform_get_drvdata(pdev); +@@ -181,6 +207,8 @@ static struct platform_nand_data xway_na + .dev_ready = xway_dev_ready, + .select_chip = xway_select_chip, + .read_byte = xway_read_byte, ++ .read_buf = xway_read_buf, ++ .write_buf = xway_write_buf, + } + }; + diff --git a/target/linux/lantiq/patches-3.18/0017-MTD-xway-fix-nand-locking.patch b/target/linux/lantiq/patches-3.18/0017-MTD-xway-fix-nand-locking.patch new file mode 100644 index 0000000..737469a --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0017-MTD-xway-fix-nand-locking.patch @@ -0,0 +1,89 @@ +From aa705c1b0860da91f2ed1a4c0b57337e6de689e1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:55:31 +0200 +Subject: [PATCH 17/36] MTD: xway: fix nand locking + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 15 +++------------ + 1 file changed, 3 insertions(+), 12 deletions(-) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -80,13 +80,16 @@ static void xway_reset_chip(struct nand_ + + static void xway_select_chip(struct mtd_info *mtd, int chip) + { ++ static unsigned long csflags; + + switch (chip) { + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); ++ spin_unlock_irqrestore(&ebu_lock, csflags); + break; + case 0: ++ spin_lock_irqsave(&ebu_lock, csflags); + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); + break; +@@ -99,7 +102,6 @@ static void xway_cmd_ctrl(struct mtd_inf + { + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; +- unsigned long flags; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_CLE) +@@ -109,11 +111,9 @@ static void xway_cmd_ctrl(struct mtd_inf + } + + if (cmd != NAND_CMD_NONE) { +- spin_lock_irqsave(&ebu_lock, flags); + writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd)); + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; +- spin_unlock_irqrestore(&ebu_lock, flags); + } + } + +@@ -126,12 +126,9 @@ static unsigned char xway_read_byte(stru + { + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_R; +- unsigned long flags; + int ret; + +- spin_lock_irqsave(&ebu_lock, flags); + ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA)); +- spin_unlock_irqrestore(&ebu_lock, flags); + + return ret; + } +@@ -140,26 +137,20 @@ static void xway_read_buf(struct mtd_inf + { + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_R; +- unsigned long flags; + int i; + +- spin_lock_irqsave(&ebu_lock, flags); + for (i = 0; i < len; i++) + buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA)); +- spin_unlock_irqrestore(&ebu_lock, flags); + } + + static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len) + { + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; +- unsigned long flags; + int i; + +- spin_lock_irqsave(&ebu_lock, flags); + for (i = 0; i < len; i++) + ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA)); +- spin_unlock_irqrestore(&ebu_lock, flags); + } + + static int xway_nand_probe(struct platform_device *pdev) diff --git a/target/linux/lantiq/patches-3.18/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-3.18/0018-MTD-nand-lots-of-xrx200-fixes.patch new file mode 100644 index 0000000..5500861 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0018-MTD-nand-lots-of-xrx200-fixes.patch @@ -0,0 +1,125 @@ +From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 23:12:15 +0200 +Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -54,8 +54,27 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) ++#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) ++#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) ++ + static u32 xway_latchcmd; + ++/* ++ * req_mask provides a mechanism to prevent interference between ++ * nand and pci (probably only relevant for the BT Home Hub 2B). ++ * Setting it causes the corresponding pci req pins to be masked ++ * during nand access, and also moves ebu locking from the read/write ++ * functions to the chip select function to ensure that the whole ++ * operation runs with interrupts disabled. ++ * In addition it switches on some extra waiting in xway_cmd_ctrl(). ++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, ++ * which in turn seems to be necessary for the nor chip to be recognised ++ * reliably, on a board (Home Hub 2B again) which has both nor and nand. ++ */ ++ ++static __be32 req_mask = 0; ++ + static void xway_reset_chip(struct nand_chip *chip) + { + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; +@@ -86,12 +105,24 @@ static void xway_select_chip(struct mtd_ + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); ++ ++ if (req_mask) { ++ /* Unmask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); ++ } + spin_unlock_irqrestore(&ebu_lock, csflags); ++ + break; + case 0: + spin_lock_irqsave(&ebu_lock, csflags); ++ if (req_mask) { ++ /* Mask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); ++ } ++ + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); ++ + break; + default: + BUG(); +@@ -103,6 +134,12 @@ static void xway_cmd_ctrl(struct mtd_inf + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + ++ if (req_mask) { ++ if (cmd != NAND_CMD_STATUS) ++ ltq_ebu_w32(EBU_NAND_WAIT, 0); /* Clear nand ready */ ++ } ++ ++ + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_CLE) + xway_latchcmd = NAND_WRITE_CMD; +@@ -115,6 +152,24 @@ static void xway_cmd_ctrl(struct mtd_inf + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + } ++ ++ if (req_mask) { ++ /* ++ * program and erase have their own busy handlers ++ * status and sequential in needs no delay ++ */ ++ switch (cmd) { ++ case NAND_CMD_ERASE1: ++ case NAND_CMD_SEQIN: ++ case NAND_CMD_STATUS: ++ case NAND_CMD_READID: ++ return; ++ } ++ ++ /* wait until command is processed */ ++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) ++ ; ++ } + } + + static int xway_dev_ready(struct mtd_info *mtd) +@@ -157,6 +212,8 @@ static int xway_nand_probe(struct platfo + { + struct nand_chip *this = platform_get_drvdata(pdev); + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; ++ const __be32 *req_mask_ptr = of_get_property(pdev->dev.of_node, ++ "req-mask", NULL); + const __be32 *cs = of_get_property(pdev->dev.of_node, + "lantiq,cs", NULL); + u32 cs_flag = 0; +@@ -165,6 +222,12 @@ static int xway_nand_probe(struct platfo + if (cs && (*cs == 1)) + cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; + ++ /* ++ * Load the PCI req lines to mask from the device tree. If the ++ * property is not present, setting req_mask to 0 disables masking. ++ */ ++ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); ++ + /* setup the EBU to run in NAND mode on our base addr */ + ltq_ebu_w32(CPHYSADDR(nandaddr) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-3.18/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-3.18/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch new file mode 100644 index 0000000..36a899d --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch @@ -0,0 +1,25 @@ +From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:18:00 +0200 +Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash + +Signed-off-by: John Crispin +--- + drivers/mtd/maps/lantiq-flash.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -139,7 +139,11 @@ ltq_mtd_probe(struct platform_device *pd + if (!ltq_mtd->map) + return -ENOMEM; + +- ltq_mtd->map->phys = ltq_mtd->res->start; ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map->phys = NO_XIP; ++ else ++ ltq_mtd->map->phys = ltq_mtd->res->start; ++ ltq_mtd->res->start; + ltq_mtd->map->size = resource_size(ltq_mtd->res); + ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); + if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch b/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch new file mode 100644 index 0000000..203eb94 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch @@ -0,0 +1,44 @@ +From 4400e1f593ea40a51912128adb4f53d59e62cad8 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:40:18 +0200 +Subject: [PATCH 22/36] MTD: m25p80: allow loading mtd name from OF + +In accordance with the physmap flash we should honour the linux,mtd-name +property when deciding what name the mtd device has. + +Signed-off-by: Thomas Langer +Signed-off-by: John Crispin +--- + drivers/mtd/devices/m25p80.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -198,6 +199,10 @@ static int m25p_probe(struct spi_device + enum read_mode mode = SPI_NOR_NORMAL; + char *flash_name = NULL; + int ret; ++ const char __maybe_unused *of_mtd_name = NULL; ++ ++ of_property_read_string(spi->dev.of_node, ++ "linux,mtd-name", &of_mtd_name); + + data = dev_get_platdata(&spi->dev); + +@@ -229,6 +234,8 @@ static int m25p_probe(struct spi_device + + if (data && data->name) + flash->mtd.name = data->name; ++ else if (of_mtd_name) ++ flash->mtd.name = of_mtd_name; + + /* For some (historical?) reason many platforms provide two different + * names in flash_platform_data: "name" and "type". Quite often name is diff --git a/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch b/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch new file mode 100644 index 0000000..6d1805f --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch @@ -0,0 +1,271 @@ +From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:15:36 +0200 +Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G + +Signed-off-by: John Crispin +--- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 237 insertions(+) + create mode 100644 drivers/net/phy/lantiq.c + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -164,6 +164,11 @@ config RTL8306_PHY + tristate "Driver for Realtek RTL8306S switches" + select SWCONFIG + ++config LANTIQ_PHY ++ tristate "Driver for Lantiq PHYs" ++ ---help--- ++ Supports the 11G and 22E PHYs. ++ + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_DP83640_PHY) += dp83640.o + obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_MICREL_PHY) += micrel.o ++obj-$(CONFIG_LANTIQ_PHY) += lantiq.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_AT803X_PHY) += at803x.o +--- /dev/null ++++ b/drivers/net/phy/lantiq.c +@@ -0,0 +1,231 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2012 Daniel Schwierzeck ++ */ ++ ++#include ++#include ++ ++#define MII_MMDCTRL 0x0d ++#define MII_MMDDATA 0x0e ++ ++#define MII_VR9_11G_IMASK 0x19 /* interrupt mask */ ++#define MII_VR9_11G_ISTAT 0x1a /* interrupt status */ ++ ++#define INT_VR9_11G_WOL BIT(15) /* Wake-On-LAN */ ++#define INT_VR9_11G_ANE BIT(11) /* Auto-Neg error */ ++#define INT_VR9_11G_ANC BIT(10) /* Auto-Neg complete */ ++#define INT_VR9_11G_ADSC BIT(5) /* Link auto-downspeed detect */ ++#define INT_VR9_11G_DXMC BIT(2) /* Duplex mode change */ ++#define INT_VR9_11G_LSPC BIT(1) /* Link speed change */ ++#define INT_VR9_11G_LSTC BIT(0) /* Link state change */ ++#define INT_VR9_11G_MASK (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC) ++ ++#define ADVERTISED_MPD BIT(10) /* Multi-port device */ ++ ++#define MMD_DEVAD 0x1f ++#define MMD_ACTYPE_SHIFT 14 ++#define MMD_ACTYPE_ADDRESS (0 << MMD_ACTYPE_SHIFT) ++#define MMD_ACTYPE_DATA (1 << MMD_ACTYPE_SHIFT) ++#define MMD_ACTYPE_DATA_PI (2 << MMD_ACTYPE_SHIFT) ++#define MMD_ACTYPE_DATA_PIWR (3 << MMD_ACTYPE_SHIFT) ++ ++static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev, ++ u16 regnum) ++{ ++ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD); ++ phy_write(phydev, MII_MMDDATA, regnum); ++ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD); ++ ++ return phy_read(phydev, MII_MMDDATA); ++} ++ ++static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev, ++ u16 regnum, u16 val) ++{ ++ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD); ++ phy_write(phydev, MII_MMDDATA, regnum); ++ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD); ++ phy_write(phydev, MII_MMDDATA, val); ++ ++ return 0; ++} ++ ++static int vr9_gphy_config_init(struct phy_device *phydev) ++{ ++ int err; ++ ++ dev_dbg(&phydev->dev, "%s\n", __func__); ++ ++ /* Mask all interrupts */ ++ err = phy_write(phydev, MII_VR9_11G_IMASK, 0); ++ if (err) ++ return err; ++ ++ /* Clear all pending interrupts */ ++ phy_read(phydev, MII_VR9_11G_ISTAT); ++ ++ vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5); ++ vr9_gphy_mmd_write(phydev, 0x1e1, 0x67); ++ vr9_gphy_mmd_write(phydev, 0x1e2, 0x42); ++ vr9_gphy_mmd_write(phydev, 0x1e3, 0x10); ++ vr9_gphy_mmd_write(phydev, 0x1e4, 0x70); ++ vr9_gphy_mmd_write(phydev, 0x1e5, 0x03); ++ vr9_gphy_mmd_write(phydev, 0x1e6, 0x20); ++ vr9_gphy_mmd_write(phydev, 0x1e7, 0x00); ++ vr9_gphy_mmd_write(phydev, 0x1e8, 0x40); ++ vr9_gphy_mmd_write(phydev, 0x1e9, 0x20); ++ ++ return 0; ++} ++ ++static int vr9_gphy_config_aneg(struct phy_device *phydev) ++{ ++ int reg, err; ++ ++ /* Advertise as multi-port device */ ++ reg = phy_read(phydev, MII_CTRL1000); ++ reg |= ADVERTISED_MPD; ++ err = phy_write(phydev, MII_CTRL1000, reg); ++ if (err) ++ return err; ++ ++ return genphy_config_aneg(phydev); ++} ++ ++static int vr9_gphy_ack_interrupt(struct phy_device *phydev) ++{ ++ int reg; ++ ++ /* ++ * Possible IRQ numbers: ++ * - IM3_IRL18 for GPHY0 ++ * - IM3_IRL17 for GPHY1 ++ * ++ * Due to a silicon bug IRQ lines are not really independent from ++ * each other. Sometimes the two lines are driven at the same time ++ * if only one GPHY core raises the interrupt. ++ */ ++ ++ reg = phy_read(phydev, MII_VR9_11G_ISTAT); ++ ++ return (reg < 0) ? reg : 0; ++} ++ ++static int vr9_gphy_did_interrupt(struct phy_device *phydev) ++{ ++ int reg; ++ ++ reg = phy_read(phydev, MII_VR9_11G_ISTAT); ++ ++ return reg > 0; ++} ++ ++static int vr9_gphy_config_intr(struct phy_device *phydev) ++{ ++ int err; ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) ++ err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK); ++ else ++ err = phy_write(phydev, MII_VR9_11G_IMASK, 0); ++ ++ return err; ++} ++ ++static struct phy_driver lantiq_phy[] = { ++ { ++ .phy_id = 0xd565a400, ++ .phy_id_mask = 0xfffffff8, ++ .name = "Lantiq XWAY PEF7071", ++ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), ++ .flags = 0, /*PHY_HAS_INTERRUPT,*/ ++ .config_init = vr9_gphy_config_init, ++ .config_aneg = vr9_gphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = vr9_gphy_ack_interrupt, ++ .did_interrupt = vr9_gphy_did_interrupt, ++ .config_intr = vr9_gphy_config_intr, ++ .driver = { .owner = THIS_MODULE }, ++ }, { ++ .phy_id = 0x030260D0, ++ .phy_id_mask = 0xfffffff0, ++ .name = "Lantiq XWAY VR9 GPHY 11G v1.3", ++ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), ++ .flags = 0, /*PHY_HAS_INTERRUPT,*/ ++ .config_init = vr9_gphy_config_init, ++ .config_aneg = vr9_gphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = vr9_gphy_ack_interrupt, ++ .did_interrupt = vr9_gphy_did_interrupt, ++ .config_intr = vr9_gphy_config_intr, ++ .driver = { .owner = THIS_MODULE }, ++ }, { ++ .phy_id = 0xd565a408, ++ .phy_id_mask = 0xfffffff8, ++ .name = "Lantiq XWAY VR9 GPHY 11G v1.4", ++ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), ++ .flags = 0, /*PHY_HAS_INTERRUPT,*/ ++ .config_init = vr9_gphy_config_init, ++ .config_aneg = vr9_gphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = vr9_gphy_ack_interrupt, ++ .did_interrupt = vr9_gphy_did_interrupt, ++ .config_intr = vr9_gphy_config_intr, ++ .driver = { .owner = THIS_MODULE }, ++ }, { ++ .phy_id = 0xd565a418, ++ .phy_id_mask = 0xfffffff8, ++ .name = "Lantiq XWAY XRX PHY22F v1.4", ++ .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), ++ .flags = 0, /*PHY_HAS_INTERRUPT,*/ ++ .config_init = vr9_gphy_config_init, ++ .config_aneg = vr9_gphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = vr9_gphy_ack_interrupt, ++ .did_interrupt = vr9_gphy_did_interrupt, ++ .config_intr = vr9_gphy_config_intr, ++ .driver = { .owner = THIS_MODULE }, ++ }, ++}; ++ ++static int __init ltq_phy_init(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) { ++ int err = phy_driver_register(&lantiq_phy[i]); ++ if (err) ++ pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name); ++ } ++ ++ return 0; ++} ++ ++static void __exit ltq_phy_exit(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) ++ phy_driver_unregister(&lantiq_phy[i]); ++} ++ ++module_init(ltq_phy_init); ++module_exit(ltq_phy_exit); ++ ++MODULE_DESCRIPTION("Lantiq PHY drivers"); ++MODULE_AUTHOR("Daniel Schwierzeck "); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/patches-3.18/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch b/target/linux/lantiq/patches-3.18/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch new file mode 100644 index 0000000..b69b2a9 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch @@ -0,0 +1,364 @@ +From 77e89d5a28be35058041c79e9874ab26f222c603 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Mon, 22 Oct 2012 09:26:24 +0200 +Subject: [PATCH 24/36] NET: lantiq: adds PHY11G firmware blobs + +Signed-off-by: John Crispin +--- + firmware/Makefile | 4 + + firmware/lantiq/COPYING | 286 +++++++++++++++++++++++++++++++++++++++++++++++ + firmware/lantiq/README | 45 ++++++++ + 3 files changed, 335 insertions(+) + create mode 100644 firmware/lantiq/COPYING + create mode 100644 firmware/lantiq/README + +--- a/firmware/Makefile ++++ b/firmware/Makefile +@@ -134,6 +134,10 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_P + fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw + fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw + fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin ++fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy11g_a1x.bin ++fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy11g_a2x.bin ++fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy22f_a1x.bin ++fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy22f_a2x.bin + fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin + + fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) +--- /dev/null ++++ b/firmware/lantiq/COPYING +@@ -0,0 +1,286 @@ ++All firmware files are copyrighted by Lantiq Deutschland GmbH. ++The files have been extracted from header files found in Lantiq BSPs. ++If not stated otherwise all files are licensed under GPL. ++ ++======================================================================= ++ ++ GNU GENERAL PUBLIC LICENSE ++ Version 2, June 1991 ++ ++ Copyright (C) 1989, 1991 Free Software Foundation, Inc. ++ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ Everyone is permitted to copy and distribute verbatim copies ++ of this license document, but changing it is not allowed. ++ ++ Preamble ++ ++ The licenses for most software are designed to take away your ++freedom to share and change it. By contrast, the GNU General Public ++License is intended to guarantee your freedom to share and change free ++software--to make sure the software is free for all its users. This ++General Public License applies to most of the Free Software ++Foundation's software and to any other program whose authors commit to ++using it. (Some other Free Software Foundation software is covered by ++the GNU Library General Public License instead.) You can apply it to ++your programs, too. ++ ++ When we speak of free software, we are referring to freedom, not ++price. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING ++WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR ++REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, ++INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING ++OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED ++TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY ++YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER ++PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE ++POSSIBILITY OF SUCH DAMAGES. ++ ++ END OF TERMS AND CONDITIONS +--- /dev/null ++++ b/firmware/lantiq/README +@@ -0,0 +1,45 @@ ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++# (C) Copyright 2007 - 2012 ++# Lantiq Deutschland GmbH ++# ++# (C) Copyright 2012 ++# Daniel Schwierzeck ++# ++ ++# ++# How to use ++# ++Configure kernel with: ++CONFIG_FW_LOADER=y ++CONFIG_EXTRA_FIRMWARE_DIR="FIRMWARE_DIR" ++CONFIG_EXTRA_FIRMWARE="FIRMWARE_FILES" ++ ++where FIRMWARE_DIR should point to this git tree and FIRMWARE_FILES is a list ++of space separated files from list below. ++ ++# ++# Firmware files ++# ++ ++# GPHY core on Lantiq XWAY VR9 v1.1 ++lantiq/vr9_phy11g_a1x.bin ++lantiq/vr9_phy22f_a1x.bin ++ ++# GPHY core on Lantiq XWAY VR9 v1.2 ++lantiq/vr9_phy11g_a2x.bin ++lantiq/vr9_phy22f_a2x.bin diff --git a/target/linux/lantiq/patches-3.18/0025-NET-MIPS-lantiq-adds-xrx200-net.patch b/target/linux/lantiq/patches-3.18/0025-NET-MIPS-lantiq-adds-xrx200-net.patch new file mode 100644 index 0000000..f2a9d1b --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0025-NET-MIPS-lantiq-adds-xrx200-net.patch @@ -0,0 +1,3339 @@ +From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Mon, 22 Oct 2012 12:22:23 +0200 +Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net + +--- + drivers/net/ethernet/Kconfig | 8 +- + drivers/net/ethernet/Makefile | 1 + + drivers/net/ethernet/lantiq_pce.h | 163 +++ + drivers/net/ethernet/lantiq_xrx200.c | 1798 +++++++++++++++++++++++++++++++ + drivers/net/ethernet/lantiq_xrx200_sw.h | 1328 +++++++++++++++++++++++ + 5 files changed, 3297 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/lantiq_pce.h + create mode 100644 drivers/net/ethernet/lantiq_xrx200.c + create mode 100644 drivers/net/ethernet/lantiq_xrx200_sw.h + +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -101,7 +101,13 @@ config LANTIQ_ETOP + tristate "Lantiq SoC ETOP driver" + depends on SOC_TYPE_XWAY + ---help--- +- Support for the MII0 inside the Lantiq SoC ++ Support for the MII0 inside the Lantiq ADSL SoC ++ ++config LANTIQ_XRX200 ++ tristate "Lantiq SoC XRX200 driver" ++ depends on SOC_TYPE_XWAY ++ ---help--- ++ Support for the MII0 inside the Lantiq VDSL SoC + + source "drivers/net/ethernet/marvell/Kconfig" + source "drivers/net/ethernet/mellanox/Kconfig" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -43,6 +43,7 @@ obj-$(CONFIG_IP1000) += icplus/ + obj-$(CONFIG_JME) += jme.o + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o ++obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o + obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ + obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ + obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_pce.h +@@ -0,0 +1,163 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2012 John Crispin ++ * ++ * PCE microcode extracted from UGW5.2 switch api ++ */ ++ ++/* Switch API Micro Code V0.3 */ ++enum { ++ OUT_MAC0 = 0, ++ OUT_MAC1, ++ OUT_MAC2, ++ OUT_MAC3, ++ OUT_MAC4, ++ OUT_MAC5, ++ OUT_ETHTYP, ++ OUT_VTAG0, ++ OUT_VTAG1, ++ OUT_ITAG0, ++ OUT_ITAG1, /*10 */ ++ OUT_ITAG2, ++ OUT_ITAG3, ++ OUT_IP0, ++ OUT_IP1, ++ OUT_IP2, ++ OUT_IP3, ++ OUT_SIP0, ++ OUT_SIP1, ++ OUT_SIP2, ++ OUT_SIP3, /*20*/ ++ OUT_SIP4, ++ OUT_SIP5, ++ OUT_SIP6, ++ OUT_SIP7, ++ OUT_DIP0, ++ OUT_DIP1, ++ OUT_DIP2, ++ OUT_DIP3, ++ OUT_DIP4, ++ OUT_DIP5, /*30*/ ++ OUT_DIP6, ++ OUT_DIP7, ++ OUT_SESID, ++ OUT_PROT, ++ OUT_APP0, ++ OUT_APP1, ++ OUT_IGMP0, ++ OUT_IGMP1, ++ OUT_IPOFF, /*39*/ ++ OUT_NONE = 63 ++}; ++ ++/* parser's microcode length type */ ++#define INSTR 0 ++#define IPV6 1 ++#define LENACCU 2 ++ ++/* parser's microcode flag type */ ++enum { ++ FLAG_ITAG = 0, ++ FLAG_VLAN, ++ FLAG_SNAP, ++ FLAG_PPPOE, ++ FLAG_IPV6, ++ FLAG_IPV6FL, ++ FLAG_IPV4, ++ FLAG_IGMP, ++ FLAG_TU, ++ FLAG_HOP, ++ FLAG_NN1, /*10 */ ++ FLAG_NN2, ++ FLAG_END, ++ FLAG_NO, /*13*/ ++}; ++ ++/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */ ++#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \ ++ { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }} ++struct pce_microcode { ++ unsigned short val[4]; ++/* unsigned short val_2; ++ unsigned short val_1; ++ unsigned short val_0;*/ ++} pce_microcode[] = { ++ /* value mask ns fields L type flags ipv4_len */ ++ MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0), ++ MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0), ++ MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1), ++ MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0), ++ MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0), ++ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0), ++ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0), ++ MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0), ++ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0), ++ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++}; +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -0,0 +1,1796 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland ++ * Copyright (C) 2012 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "lantiq_pce.h" ++#include "lantiq_xrx200_sw.h" ++ ++#define SW_POLLING ++#define SW_ROUTING ++#define SW_PORTMAP ++ ++#ifdef SW_ROUTING ++ #ifdef SW_PORTMAP ++#define XRX200_MAX_DEV 2 ++ #else ++#define XRX200_MAX_DEV 2 ++ #endif ++#else ++#define XRX200_MAX_DEV 1 ++#endif ++ ++#define XRX200_MAX_VLAN 64 ++#define XRX200_PCE_ACTVLAN_IDX 0x01 ++#define XRX200_PCE_VLANMAP_IDX 0x02 ++ ++#define XRX200_MAX_PORT 7 ++#define XRX200_MAX_DMA 8 ++ ++#define XRX200_HEADROOM 4 ++ ++#define XRX200_TX_TIMEOUT (10 * HZ) ++ ++/* port type */ ++#define XRX200_PORT_TYPE_PHY 1 ++#define XRX200_PORT_TYPE_MAC 2 ++ ++/* DMA */ ++#define XRX200_DMA_DATA_LEN 0x600 ++#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0 ++#define XRX200_DMA_RX 0 ++#define XRX200_DMA_TX 1 ++#define XRX200_DMA_IS_TX(x) (x%2) ++#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x)) ++ ++/* fetch / store dma */ ++#define FDMA_PCTRL0 0x2A00 ++#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18)) ++#define SDMA_PCTRL0 0x2F00 ++#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18)) ++ ++/* buffer management */ ++#define BM_PCFG0 0x200 ++#define BM_PCFGx(x) (BM_PCFG0 + (x * 8)) ++ ++/* MDIO */ ++#define MDIO_GLOB 0x0000 ++#define MDIO_CTRL 0x0020 ++#define MDIO_READ 0x0024 ++#define MDIO_WRITE 0x0028 ++#define MDIO_PHY0 0x0054 ++#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned))) ++#define MDIO_CLK_CFG0 0x002C ++#define MDIO_CLK_CFG1 0x0030 ++ ++#define MDIO_GLOB_ENABLE 0x8000 ++#define MDIO_BUSY BIT(12) ++#define MDIO_RD BIT(11) ++#define MDIO_WR BIT(10) ++#define MDIO_MASK 0x1f ++#define MDIO_ADDRSHIFT 5 ++#define MDIO1_25MHZ 9 ++ ++#define MDIO_PHY_LINK_DOWN 0x4000 ++#define MDIO_PHY_LINK_UP 0x2000 ++ ++#define MDIO_PHY_SPEED_M10 0x0000 ++#define MDIO_PHY_SPEED_M100 0x0800 ++#define MDIO_PHY_SPEED_G1 0x1000 ++ ++#define MDIO_PHY_FDUP_EN 0x0200 ++#define MDIO_PHY_FDUP_DIS 0x0600 ++ ++#define MDIO_PHY_LINK_MASK 0x6000 ++#define MDIO_PHY_SPEED_MASK 0x1800 ++#define MDIO_PHY_FDUP_MASK 0x0600 ++#define MDIO_PHY_ADDR_MASK 0x001f ++#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \ ++ MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK ++ ++/* MII */ ++#define MII_CFG(p) (p * 8) ++ ++#define MII_CFG_EN BIT(14) ++ ++#define MII_CFG_MODE_MIIP 0x0 ++#define MII_CFG_MODE_MIIM 0x1 ++#define MII_CFG_MODE_RMIIP 0x2 ++#define MII_CFG_MODE_RMIIM 0x3 ++#define MII_CFG_MODE_RGMII 0x4 ++#define MII_CFG_MODE_MASK 0xf ++ ++#define MII_CFG_RATE_M2P5 0x00 ++#define MII_CFG_RATE_M25 0x10 ++#define MII_CFG_RATE_M125 0x20 ++#define MII_CFG_RATE_M50 0x30 ++#define MII_CFG_RATE_AUTO 0x40 ++#define MII_CFG_RATE_MASK 0x70 ++ ++/* cpu port mac */ ++#define PMAC_HD_CTL 0x0000 ++#define PMAC_RX_IPG 0x0024 ++#define PMAC_EWAN 0x002c ++ ++#define PMAC_IPG_MASK 0xf ++#define PMAC_HD_CTL_AS 0x0008 ++#define PMAC_HD_CTL_AC 0x0004 ++#define PMAC_HD_CTL_RXSH 0x0040 ++#define PMAC_HD_CTL_AST 0x0080 ++#define PMAC_HD_CTL_RST 0x0100 ++ ++/* PCE */ ++#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4)) ++#define PCE_TBL_MASK 0x1120 ++#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4)) ++#define PCE_TBL_ADDR 0x1138 ++#define PCE_TBL_CTRL 0x113c ++#define PCE_PMAP1 0x114c ++#define PCE_PMAP2 0x1150 ++#define PCE_PMAP3 0x1154 ++#define PCE_GCTRL_REG(x) (0x1158 + (x * 4)) ++#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4)) ++ ++#define PCE_TBL_BUSY BIT(15) ++#define PCE_TBL_CFG_ADDR_MASK 0x1f ++#define PCE_TBL_CFG_ADWR 0x20 ++#define PCE_TBL_CFG_ADWR_MASK 0x60 ++#define PCE_INGRESS BIT(11) ++ ++/* MAC */ ++#define MAC_FLEN_REG (0x2314) ++#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4)) ++ ++/* buffer management */ ++#define BM_PCFG(p) (0x200 + (p * 8)) ++ ++/* special tag in TX path header */ ++#define SPID_SHIFT 24 ++#define DPID_SHIFT 16 ++#define DPID_ENABLE 1 ++#define SPID_CPU_PORT 2 ++#define PORT_MAP_SEL BIT(15) ++#define PORT_MAP_EN BIT(14) ++#define PORT_MAP_SHIFT 1 ++#define PORT_MAP_MASK 0x3f ++ ++#define SPPID_MASK 0x7 ++#define SPPID_SHIFT 4 ++ ++/* MII regs not yet in linux */ ++#define MDIO_DEVAD_NONE (-1) ++#define ADVERTIZE_MPD (1 << 10) ++ ++struct xrx200_port { ++ u8 num; ++ u8 phy_addr; ++ u16 flags; ++ phy_interface_t phy_if; ++ ++ int link; ++ int gpio; ++ enum of_gpio_flags gpio_flags; ++ ++ struct phy_device *phydev; ++ struct device_node *phy_node; ++}; ++ ++struct xrx200_chan { ++ int idx; ++ int refcount; ++ int tx_free; ++ ++ struct net_device dummy_dev; ++ struct net_device *devs[XRX200_MAX_DEV]; ++ ++ struct tasklet_struct tasklet; ++ struct napi_struct napi; ++ struct ltq_dma_channel dma; ++ struct sk_buff *skb[LTQ_DESC_NUM]; ++}; ++ ++struct xrx200_hw { ++ struct clk *clk; ++ struct mii_bus *mii_bus; ++ ++ struct xrx200_chan chan[XRX200_MAX_DMA]; ++ ++ struct net_device *devs[XRX200_MAX_DEV]; ++ int num_devs; ++ ++ int port_map[XRX200_MAX_PORT]; ++ unsigned short wan_map; ++ ++ spinlock_t lock; ++ ++ struct switch_dev swdev; ++}; ++ ++struct xrx200_priv { ++ struct net_device_stats stats; ++ int id; ++ ++ struct xrx200_port port[XRX200_MAX_PORT]; ++ int num_port; ++ bool wan; ++ bool sw; ++ unsigned short port_map; ++ unsigned char mac[6]; ++ ++ struct xrx200_hw *hw; ++}; ++ ++static __iomem void *xrx200_switch_membase; ++static __iomem void *xrx200_mii_membase; ++static __iomem void *xrx200_mdio_membase; ++static __iomem void *xrx200_pmac_membase; ++ ++#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x)) ++#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y)) ++#define ltq_switch_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_switch_membase + (z)) ++ ++#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x)) ++#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y)) ++#define ltq_mdio_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_mdio_membase + (z)) ++ ++#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x)) ++#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y)) ++#define ltq_mii_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_mii_membase + (z)) ++ ++#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x)) ++#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y)) ++#define ltq_pmac_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_pmac_membase + (z)) ++ ++#define XRX200_GLOBAL_REGATTR(reg) \ ++ .id = reg, \ ++ .type = SWITCH_TYPE_INT, \ ++ .set = xrx200_set_global_attr, \ ++ .get = xrx200_get_global_attr ++ ++#define XRX200_PORT_REGATTR(reg) \ ++ .id = reg, \ ++ .type = SWITCH_TYPE_INT, \ ++ .set = xrx200_set_port_attr, \ ++ .get = xrx200_get_port_attr ++ ++static int xrx200sw_read_x(int reg, int x) ++{ ++ int value, mask, addr; ++ ++ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); ++ value = ltq_switch_r32(addr); ++ mask = (1 << xrx200sw_reg[reg].size) - 1; ++ value = (value >> xrx200sw_reg[reg].shift); ++ ++ return (value & mask); ++} ++ ++static int xrx200sw_read(int reg) ++{ ++ return xrx200sw_read_x(reg, 0); ++} ++ ++static void xrx200sw_write_x(int value, int reg, int x) ++{ ++ int mask, addr; ++ ++ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); ++ mask = (1 << xrx200sw_reg[reg].size) - 1; ++ mask = (mask << xrx200sw_reg[reg].shift); ++ value = (value << xrx200sw_reg[reg].shift) & mask; ++ ++ ltq_switch_w32_mask(mask, value, addr); ++} ++ ++static void xrx200sw_write(int value, int reg) ++{ ++ xrx200sw_write_x(value, reg, 0); ++} ++ ++struct xrx200_pce_table_entry { ++ int index; // PCE_TBL_ADDR.ADDR = pData->table_index ++ int table; // PCE_TBL_CTRL.ADDR = pData->table ++ unsigned short key[8]; ++ unsigned short val[5]; ++ unsigned short mask; ++ unsigned short type; ++ unsigned short valid; ++ unsigned short gmap; ++}; ++ ++static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl) ++{ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // prepare the table access: ++ // PCE_TBL_ADDR.ADDR = pData->table_index ++ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); ++ // PCE_TBL_CTRL.ADDR = pData->table ++ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); ++ ++ //(address-based read) ++ xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD ++ ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access ++ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // read the keys ++ tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7); ++ tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6); ++ tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5); ++ tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4); ++ tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3); ++ tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2); ++ tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1); ++ tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0); ++ ++ // read the values ++ tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4); ++ tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3); ++ tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2); ++ tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1); ++ tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0); ++ ++ // read the mask ++ tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0); ++ // read the type ++ tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE); ++ // read the valid flag ++ tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD); ++ // read the group map ++ tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP); ++ ++ return 0; ++} ++ ++static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl) ++{ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // prepare the table access: ++ // PCE_TBL_ADDR.ADDR = pData->table_index ++ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); ++ // PCE_TBL_CTRL.ADDR = pData->table ++ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); ++ ++ //(address-based write) ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD ++ ++ // read the keys ++ xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7); ++ xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6); ++ xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5); ++ xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4); ++ xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3); ++ xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2); ++ xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1); ++ xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0); ++ ++ // read the values ++ xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4); ++ xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3); ++ xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2); ++ xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1); ++ xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0); ++ ++ // read the mask ++ xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0); ++ // read the type ++ xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE); ++ // read the valid flag ++ xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD); ++ // read the group map ++ xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP); ++ ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access ++ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ return 0; ++} ++ ++static void xrx200sw_fixup_pvids(void) ++{ ++ int index, p, portmap, untagged; ++ struct xrx200_pce_table_entry tem; ++ struct xrx200_pce_table_entry tev; ++ ++ portmap = 0; ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ portmap |= BIT(p); ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ ++ for (index = XRX200_MAX_VLAN; index-- > 0;) ++ { ++ tev.index = index; ++ xrx200_pce_table_entry_read(&tev); ++ ++ if (tev.valid == 0) ++ continue; ++ ++ tem.index = index; ++ xrx200_pce_table_entry_read(&tem); ++ ++ if (tem.val[0] == 0) ++ continue; ++ ++ untagged = portmap & (tem.val[1] ^ tem.val[2]); ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ if (untagged & BIT(p)) ++ { ++ portmap &= ~BIT(p); ++ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); ++ } ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ if (portmap & BIT(p)) ++ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); ++ } ++} ++ ++// swconfig interface ++static void xrx200_hw_init(struct xrx200_hw *hw); ++ ++// global ++static int xrx200sw_reset_switch(struct switch_dev *dev) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ ++ xrx200_hw_init(hw); ++ ++ return 0; ++} ++ ++static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ int p; ++ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) { ++ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p); ++ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p); ++ } ++ ++ xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN); ++ return 0; ++} ++ ++static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ val->value.i = xrx200sw_read(attr->id); ++ return 0; ++} ++ ++static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ xrx200sw_write(val->value.i, attr->id); ++ return 0; ++} ++ ++static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ val->value.i = xrx200sw_read(attr->id); ++ return 0; ++} ++ ++// vlan ++static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ int i; ++ struct xrx200_pce_table_entry tev; ++ struct xrx200_pce_table_entry tem; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ ++ for (i = 0; i < XRX200_MAX_VLAN; i++) ++ { ++ tev.index = i; ++ xrx200_pce_table_entry_read(&tev); ++ if (tev.key[0] == val->value.i && i != val->port_vlan) ++ return -EINVAL; ++ } ++ ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ tev.key[0] = val->value.i; ++ tev.valid = val->value.i > 0; ++ xrx200_pce_table_entry_write(&tev); ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ tem.val[0] = val->value.i; ++ xrx200_pce_table_entry_write(&tem); ++ ++ xrx200sw_fixup_pvids(); ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry te; ++ ++ te.table = XRX200_PCE_ACTVLAN_IDX; ++ te.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&te); ++ val->value.i = te.key[0]; ++ ++ return 0; ++} ++ ++static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ int i, portmap, tagmap, untagged; ++ struct xrx200_pce_table_entry tem; ++ ++ portmap = 0; ++ tagmap = 0; ++ for (i = 0; i < val->len; i++) ++ { ++ struct switch_port *p = &val->value.ports[i]; ++ ++ portmap |= (1 << p->id); ++ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) ++ tagmap |= (1 << p->id); ++ } ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ ++ untagged = portmap ^ tagmap; ++ for (i = 0; i < XRX200_MAX_VLAN; i++) ++ { ++ tem.index = i; ++ xrx200_pce_table_entry_read(&tem); ++ ++ if (tem.val[0] == 0) ++ continue; ++ ++ if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i)) ++ return -EINVAL; ++ } ++ ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ ++ // auto-enable this vlan if not enabled already ++ if (tem.val[0] == 0) ++ { ++ struct switch_val v; ++ v.port_vlan = val->port_vlan; ++ v.value.i = val->port_vlan; ++ if(xrx200sw_set_vlan_vid(dev, NULL, &v)) ++ return -EINVAL; ++ ++ //read updated tem ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ } ++ ++ tem.val[1] = portmap; ++ tem.val[2] = tagmap; ++ xrx200_pce_table_entry_write(&tem); ++ ++ xrx200sw_fixup_pvids(); ++ ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ int i; ++ unsigned short ports, tags; ++ struct xrx200_pce_table_entry tem; ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ ++ ports = tem.val[1]; ++ tags = tem.val[2]; ++ ++ for (i = 0; i < XRX200_MAX_PORT; i++) { ++ struct switch_port *p; ++ ++ if (!(ports & (1 << i))) ++ continue; ++ ++ p = &val->value.ports[val->len++]; ++ p->id = i; ++ if (tags & (1 << i)) ++ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); ++ else ++ p->flags = 0; ++ } ++ ++ return 0; ++} ++ ++static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ ++ if (tev.key[0] == 0) ++ return -EINVAL; ++ ++ tev.valid = val->value.i; ++ xrx200_pce_table_entry_write(&tev); ++ ++ xrx200sw_fixup_pvids(); ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ val->value.i = tev.valid; ++ ++ return 0; ++} ++ ++// port ++static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ if (port >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port); ++ xrx200_pce_table_entry_read(&tev); ++ ++ *val = tev.key[0]; ++ return 0; ++} ++ ++static int xrx200sw_get_port_link(struct switch_dev *dev, ++ int port, ++ struct switch_port_link *link) ++{ ++ if (port >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port); ++ if (!link->link) ++ return 0; ++ ++ link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port); ++ ++ link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010); ++ link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020); ++ link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port)); ++ ++ link->speed = SWITCH_PORT_SPEED_10; ++ if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port)) ++ link->speed = SWITCH_PORT_SPEED_100; ++ if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port)) ++ link->speed = SWITCH_PORT_SPEED_1000; ++ ++ return 0; ++} ++ ++static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ printk("%s %s(%d)\n", __FILE__, __func__, __LINE__); ++ if (val->port_vlan >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ xrx200sw_write_x(val->value.i, attr->id, val->port_vlan); ++ return 0; ++} ++ ++static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if (val->port_vlan >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ val->value.i = xrx200sw_read_x(attr->id, val->port_vlan); ++ return 0; ++} ++ ++// attributes ++static struct switch_attr xrx200sw_globals[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .set = xrx200_set_vlan_mode_enable, ++ .get = xrx200_get_vlan_mode_enable, ++ .name = "enable_vlan", ++ .description = "Enable VLAN mode", ++ .max = 1}, ++}; ++ ++static struct switch_attr xrx200sw_port[] = { ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR), ++ .name = "uvr", ++ .description = "Unknown VLAN Rule", ++ .max = 1, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR), ++ .name = "vsr", ++ .description = "VLAN Security Rule", ++ .max = 1, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR), ++ .name = "vinr", ++ .description = "VLAN Ingress Tag Rule", ++ .max = 2, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM), ++ .name = "tvm", ++ .description = "Transparent VLAN Mode", ++ .max = 1, ++ }, ++}; ++ ++static struct switch_attr xrx200sw_vlan[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "vid", ++ .description = "VLAN ID (0-4094)", ++ .set = xrx200sw_set_vlan_vid, ++ .get = xrx200sw_get_vlan_vid, ++ .max = 4094, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable", ++ .description = "Enable VLAN", ++ .set = xrx200sw_set_vlan_enable, ++ .get = xrx200sw_get_vlan_enable, ++ .max = 1, ++ }, ++}; ++ ++static const struct switch_dev_ops xrx200sw_ops = { ++ .attr_global = { ++ .attr = xrx200sw_globals, ++ .n_attr = ARRAY_SIZE(xrx200sw_globals), ++ }, ++ .attr_port = { ++ .attr = xrx200sw_port, ++ .n_attr = ARRAY_SIZE(xrx200sw_port), ++ }, ++ .attr_vlan = { ++ .attr = xrx200sw_vlan, ++ .n_attr = ARRAY_SIZE(xrx200sw_vlan), ++ }, ++ .get_vlan_ports = xrx200sw_get_vlan_ports, ++ .set_vlan_ports = xrx200sw_set_vlan_ports, ++ .get_port_pvid = xrx200sw_get_port_pvid, ++ .reset_switch = xrx200sw_reset_switch, ++ .get_port_link = xrx200sw_get_port_link, ++// .get_port_stats = xrx200sw_get_port_stats, //TODO ++}; ++ ++static int xrx200sw_init(struct xrx200_hw *hw) ++{ ++ int netdev_num; ++ ++ for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++) ++ { ++ struct switch_dev *swdev; ++ struct net_device *dev = hw->devs[netdev_num]; ++ struct xrx200_priv *priv = netdev_priv(dev); ++ if (!priv->sw) ++ continue; ++ ++ swdev = &hw->swdev; ++ ++ swdev->name = "Lantiq XRX200 Switch"; ++ swdev->vlans = XRX200_MAX_VLAN; ++ swdev->ports = XRX200_MAX_PORT; ++ swdev->cpu_port = 6; ++ swdev->ops = &xrx200sw_ops; ++ ++ register_switch(swdev, dev); ++ return 0; // enough switches ++ } ++ return 0; ++} ++ ++static int xrx200_open(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ unsigned long flags; ++ int i; ++ ++ for (i = 0; i < XRX200_MAX_DMA; i++) { ++ if (!priv->hw->chan[i].dma.irq) ++ continue; ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ if (!priv->hw->chan[i].refcount) { ++ if (XRX200_DMA_IS_RX(i)) ++ napi_enable(&priv->hw->chan[i].napi); ++ ltq_dma_open(&priv->hw->chan[i].dma); ++ } ++ priv->hw->chan[i].refcount++; ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ } ++ for (i = 0; i < priv->num_port; i++) ++ if (priv->port[i].phydev) ++ phy_start(priv->port[i].phydev); ++ netif_start_queue(dev); ++ ++ return 0; ++} ++ ++static int xrx200_close(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ unsigned long flags; ++ int i; ++ ++ netif_stop_queue(dev); ++ ++ for (i = 0; i < priv->num_port; i++) ++ if (priv->port[i].phydev) ++ phy_stop(priv->port[i].phydev); ++ ++ for (i = 0; i < XRX200_MAX_DMA; i++) { ++ if (!priv->hw->chan[i].dma.irq) ++ continue; ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ priv->hw->chan[i].refcount--; ++ if (!priv->hw->chan[i].refcount) { ++ if (XRX200_DMA_IS_RX(i)) ++ napi_disable(&priv->hw->chan[i].napi); ++ ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma); ++ } ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ } ++ ++ return 0; ++} ++ ++static int xrx200_alloc_skb(struct xrx200_chan *ch) ++{ ++#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD) ++ ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD); ++ if (!ch->skb[ch->dma.desc]) ++ return -ENOMEM; ++ ++ skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD); ++ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, ++ ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN, ++ DMA_FROM_DEVICE); ++ ch->dma.desc_base[ch->dma.desc].addr = ++ CPHYSADDR(ch->skb[ch->dma.desc]->data); ++ ch->dma.desc_base[ch->dma.desc].ctl = ++ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | ++ XRX200_DMA_DATA_LEN; ++ skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); ++ ++ return 0; ++} ++ ++static void xrx200_hw_receive(struct xrx200_chan *ch, int id) ++{ ++ struct net_device *dev = ch->devs[id]; ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; ++ struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ int len = (desc->ctl & LTQ_DMA_SIZE_MASK); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ if (xrx200_alloc_skb(ch)) { ++ netdev_err(dev, ++ "failed to allocate new rx buffer, stopping DMA\n"); ++ ltq_dma_close(&ch->dma); ++ } ++ ++ ch->dma.desc++; ++ ch->dma.desc %= LTQ_DESC_NUM; ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ ++ skb_put(skb, len); ++#ifdef SW_ROUTING ++ skb_pull(skb, 8); ++#endif ++ skb->dev = dev; ++ skb->protocol = eth_type_trans(skb, dev); ++ netif_receive_skb(skb); ++ priv->stats.rx_packets++; ++ priv->stats.rx_bytes+=len; ++} ++ ++static int xrx200_poll_rx(struct napi_struct *napi, int budget) ++{ ++ struct xrx200_chan *ch = container_of(napi, ++ struct xrx200_chan, napi); ++ struct xrx200_priv *priv = netdev_priv(ch->devs[0]); ++ int rx = 0; ++ int complete = 0; ++ unsigned long flags; ++ ++ while ((rx < budget) && !complete) { ++ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++#ifdef SW_ROUTING ++ struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ u32 *special_tag = (u32*)skb->data; ++ int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK; ++ xrx200_hw_receive(ch, priv->hw->port_map[port]); ++#else ++ xrx200_hw_receive(ch, 0); ++#endif ++ rx++; ++ } else { ++ complete = 1; ++ } ++ } ++ if (complete || !rx) { ++ napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ } ++ return rx; ++} ++ ++static void xrx200_tx_housekeeping(unsigned long ptr) ++{ ++ struct xrx200_hw *hw = (struct xrx200_hw *) ptr; ++ struct xrx200_chan *ch = &hw->chan[XRX200_DMA_TX]; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ dev_kfree_skb_any(ch->skb[ch->tx_free]); ++ ch->skb[ch->tx_free] = NULL; ++ memset(&ch->dma.desc_base[ch->tx_free], 0, ++ sizeof(struct ltq_dma_desc)); ++ ch->tx_free++; ++ ch->tx_free %= LTQ_DESC_NUM; ++ } ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) { ++ struct netdev_queue *txq = ++ netdev_get_tx_queue(ch->devs[i], 0); ++ if (netif_tx_queue_stopped(txq)) ++ netif_tx_start_queue(txq); ++ } ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&hw->lock, flags); ++} ++ ++static struct net_device_stats *xrx200_get_stats (struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ ++ return &priv->stats; ++} ++ ++static void xrx200_tx_timeout(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ ++ printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name); ++ ++ priv->stats.tx_errors++; ++ netif_wake_queue(dev); ++} ++ ++static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ int queue = skb_get_queue_mapping(skb); ++ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX]; ++ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; ++ unsigned long flags; ++ u32 byte_offset; ++ int len; ++#ifdef SW_ROUTING ++ #ifdef SW_PORTMAP ++ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | PORT_MAP_SEL | PORT_MAP_EN | DPID_ENABLE; ++ #else ++ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE; ++ #endif ++#endif ++ ++ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; ++ ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { ++ netdev_err(dev, "tx ring full\n"); ++ netif_tx_stop_queue(txq); ++ return NETDEV_TX_BUSY; ++ } ++#ifdef SW_ROUTING ++ #ifdef SW_PORTMAP ++ special_tag |= priv->port_map << PORT_MAP_SHIFT; ++ #else ++ if(priv->id) ++ special_tag |= (1 << DPID_SHIFT); ++ #endif ++ if(skb_headroom(skb) < 4) { ++ struct sk_buff *tmp = skb_realloc_headroom(skb, 4); ++ dev_kfree_skb_any(skb); ++ skb = tmp; ++ } ++ skb_push(skb, 4); ++ memcpy(skb->data, &special_tag, sizeof(u32)); ++ len += 4; ++#endif ++ ++ /* dma needs to start on a 16 byte aligned address */ ++ byte_offset = CPHYSADDR(skb->data) % 16; ++ ch->skb[ch->dma.desc] = skb; ++ ++ dev->trans_start = jiffies; ++ ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, ++ DMA_TO_DEVICE)) - byte_offset; ++ wmb(); ++ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | ++ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); ++ ch->dma.desc++; ++ ch->dma.desc %= LTQ_DESC_NUM; ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ ++ if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ netif_tx_stop_queue(txq); ++ ++ priv->stats.tx_packets++; ++ priv->stats.tx_bytes+=len; ++ ++ return NETDEV_TX_OK; ++} ++ ++static irqreturn_t xrx200_dma_irq(int irq, void *priv) ++{ ++ struct xrx200_hw *hw = priv; ++ int ch = irq - XRX200_DMA_IRQ; ++ ++ if (ch % 2) ++ tasklet_schedule(&hw->chan[ch].tasklet); ++ else ++ napi_schedule(&hw->chan[ch].napi); ++ ++ return IRQ_HANDLED; ++} ++ ++static int xrx200_dma_init(struct xrx200_hw *hw) ++{ ++ int i, err = 0; ++ ++ ltq_dma_init_port(DMA_PORT_ETOP); ++ ++ for (i = 0; i < 8 && !err; i++) { ++ int irq = XRX200_DMA_IRQ + i; ++ struct xrx200_chan *ch = &hw->chan[i]; ++ ++ ch->idx = ch->dma.nr = i; ++ ++ if (i == XRX200_DMA_TX) { ++ ltq_dma_alloc_tx(&ch->dma); ++ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw); ++ } else if (i == XRX200_DMA_RX) { ++ ltq_dma_alloc_rx(&ch->dma); ++ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; ++ ch->dma.desc++) ++ if (xrx200_alloc_skb(ch)) ++ err = -ENOMEM; ++ ch->dma.desc = 0; ++ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw); ++ } else ++ continue; ++ ++ if (!err) ++ ch->dma.irq = irq; ++ } ++ ++ return err; ++} ++ ++#ifdef SW_POLLING ++static void xrx200_gmac_update(struct xrx200_port *port) ++{ ++ u16 phyaddr = port->phydev->addr & MDIO_PHY_ADDR_MASK; ++ u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK; ++ u16 miirate = 0; ++ ++ switch (port->phydev->speed) { ++ case SPEED_1000: ++ phyaddr |= MDIO_PHY_SPEED_G1; ++ miirate = MII_CFG_RATE_M125; ++ break; ++ ++ case SPEED_100: ++ phyaddr |= MDIO_PHY_SPEED_M100; ++ switch (miimode) { ++ case MII_CFG_MODE_RMIIM: ++ case MII_CFG_MODE_RMIIP: ++ miirate = MII_CFG_RATE_M50; ++ break; ++ default: ++ miirate = MII_CFG_RATE_M25; ++ break; ++ } ++ break; ++ ++ default: ++ phyaddr |= MDIO_PHY_SPEED_M10; ++ miirate = MII_CFG_RATE_M2P5; ++ break; ++ } ++ ++ if (port->phydev->link) ++ phyaddr |= MDIO_PHY_LINK_UP; ++ else ++ phyaddr |= MDIO_PHY_LINK_DOWN; ++ ++ if (port->phydev->duplex == DUPLEX_FULL) ++ phyaddr |= MDIO_PHY_FDUP_EN; ++ else ++ phyaddr |= MDIO_PHY_FDUP_DIS; ++ ++ ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num)); ++ ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num)); ++ udelay(1); ++} ++#else ++static void xrx200_gmac_update(struct xrx200_port *port) ++{ ++ ++} ++#endif ++ ++static void xrx200_mdio_link(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ int i; ++ ++ for (i = 0; i < priv->num_port; i++) { ++ if (!priv->port[i].phydev) ++ continue; ++ ++ if (priv->port[i].link != priv->port[i].phydev->link) { ++ xrx200_gmac_update(&priv->port[i]); ++ priv->port[i].link = priv->port[i].phydev->link; ++ netdev_info(dev, "port %d %s link\n", ++ priv->port[i].num, ++ (priv->port[i].link)?("got"):("lost")); ++ } ++ } ++} ++ ++static inline int xrx200_mdio_poll(struct mii_bus *bus) ++{ ++ unsigned cnt = 10000; ++ ++ while (likely(cnt--)) { ++ unsigned ctrl = ltq_mdio_r32(MDIO_CTRL); ++ if ((ctrl & MDIO_BUSY) == 0) ++ return 0; ++ } ++ ++ return 1; ++} ++ ++static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) ++{ ++ if (xrx200_mdio_poll(bus)) ++ return 1; ++ ++ ltq_mdio_w32(val, MDIO_WRITE); ++ ltq_mdio_w32(MDIO_BUSY | MDIO_WR | ++ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | ++ (reg & MDIO_MASK), ++ MDIO_CTRL); ++ ++ return 0; ++} ++ ++static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg) ++{ ++ if (xrx200_mdio_poll(bus)) ++ return -1; ++ ++ ltq_mdio_w32(MDIO_BUSY | MDIO_RD | ++ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | ++ (reg & MDIO_MASK), ++ MDIO_CTRL); ++ ++ if (xrx200_mdio_poll(bus)) ++ return -1; ++ ++ return ltq_mdio_r32(MDIO_READ); ++} ++ ++static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ unsigned val; ++ ++ phydev = priv->hw->mii_bus->phy_map[port->phy_addr]; ++ ++ if (!phydev) { ++ netdev_err(dev, "no PHY found\n"); ++ return -ENODEV; ++ } ++ ++ phydev = phy_connect(dev, dev_name(&phydev->dev), &xrx200_mdio_link, ++ port->phy_if); ++ ++ if (IS_ERR(phydev)) { ++ netdev_err(dev, "Could not attach to PHY\n"); ++ return PTR_ERR(phydev); ++ } ++ ++ phydev->supported &= (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_1000baseT_Half ++ | SUPPORTED_1000baseT_Full ++ | SUPPORTED_Autoneg ++ | SUPPORTED_MII ++ | SUPPORTED_TP); ++ phydev->advertising = phydev->supported; ++ port->phydev = phydev; ++ ++ pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", ++ dev->name, phydev->drv->name, ++ dev_name(&phydev->dev), phydev->irq); ++ ++#ifdef SW_POLLING ++ phy_read_status(phydev); ++ ++ val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000); ++ val |= ADVERTIZE_MPD; ++ xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val); ++ xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040); ++ ++ phy_start_aneg(phydev); ++#endif ++ return 0; ++} ++ ++static void xrx200_port_config(struct xrx200_priv *priv, ++ const struct xrx200_port *port) ++{ ++ u16 miimode = 0; ++ ++ switch (port->num) { ++ case 0: /* xMII0 */ ++ case 1: /* xMII1 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ if (port->flags & XRX200_PORT_TYPE_PHY) ++ /* MII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ else ++ /* MII PHY mode, connected to external MAC */ ++ miimode = MII_CFG_MODE_MIIP; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ if (port->flags & XRX200_PORT_TYPE_PHY) ++ /* RMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RMIIM; ++ else ++ /* RMII PHY mode, connected to external MAC */ ++ miimode = MII_CFG_MODE_RMIIP; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ /* RGMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RGMII; ++ break; ++ default: ++ break; ++ } ++ break; ++ case 2: /* internal GPHY0 */ ++ case 3: /* internal GPHY0 */ ++ case 4: /* internal GPHY1 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ case PHY_INTERFACE_MODE_GMII: ++ /* MII MAC mode, connected to internal GPHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ break; ++ default: ++ break; ++ } ++ break; ++ case 5: /* internal GPHY1 or xMII2 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ /* MII MAC mode, connected to internal GPHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ /* RGMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RGMII; ++ break; ++ default: ++ break; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN, ++ MII_CFG(port->num)); ++} ++ ++static int xrx200_init(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct sockaddr mac; ++ int err, i; ++ ++#ifndef SW_POLLING ++ unsigned int reg = 0; ++ ++ /* enable auto polling */ ++ for (i = 0; i < priv->num_port; i++) ++ reg |= BIT(priv->port[i].num); ++ ltq_mdio_w32(reg, MDIO_CLK_CFG0); ++ ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1); ++#endif ++ ++ /* setup each port */ ++ for (i = 0; i < priv->num_port; i++) ++ xrx200_port_config(priv, &priv->port[i]); ++ ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ if (!is_valid_ether_addr(mac.sa_data)) { ++ pr_warn("net-xrx200: invalid MAC, using random\n"); ++ eth_random_addr(mac.sa_data); ++ dev->addr_assign_type |= NET_ADDR_RANDOM; ++ } ++ ++ err = eth_mac_addr(dev, &mac); ++ if (err) ++ goto err_netdev; ++ ++ for (i = 0; i < priv->num_port; i++) ++ if (xrx200_mdio_probe(dev, &priv->port[i])) ++ pr_warn("xrx200-mdio: probing phy of port %d failed\n", ++ priv->port[i].num); ++ ++ return 0; ++ ++err_netdev: ++ unregister_netdev(dev); ++ free_netdev(dev); ++ return err; ++} ++ ++static void xrx200_pci_microcode(void) ++{ ++ int i; ++ ++ ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK, ++ PCE_TBL_CFG_ADWR, PCE_TBL_CTRL); ++ ltq_switch_w32(0, PCE_TBL_MASK); ++ ++ for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) { ++ ltq_switch_w32(i, PCE_TBL_ADDR); ++ ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0)); ++ ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1)); ++ ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2)); ++ ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3)); ++ ++ // start the table access: ++ ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL); ++ while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY); ++ } ++ ++ /* tell the switch that the microcode is loaded */ ++ ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0)); ++} ++ ++static void xrx200_hw_init(struct xrx200_hw *hw) ++{ ++ int i; ++ ++ /* enable clock gate */ ++ clk_enable(hw->clk); ++ ++ ltq_switch_w32(1, 0); ++ mdelay(100); ++ ltq_switch_w32(0, 0); ++ /* ++ * TODO: we should really disbale all phys/miis here and explicitly ++ * enable them in the device secific init function ++ */ ++ ++ /* disable port fetch/store dma */ ++ for (i = 0; i < 7; i++ ) { ++ ltq_switch_w32(0, FDMA_PCTRLx(i)); ++ ltq_switch_w32(0, SDMA_PCTRLx(i)); ++ } ++ ++ /* enable Switch */ ++ ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB); ++ ++ /* load the pce microcode */ ++ xrx200_pci_microcode(); ++ ++ /* Default unknown Broadcat/Multicast/Unicast port maps */ ++ ltq_switch_w32(0x7f, PCE_PMAP1); ++ ltq_switch_w32(0x7f, PCE_PMAP2); ++ ltq_switch_w32(0x7f, PCE_PMAP3); ++ ++ /* RMON Counter Enable for all physical ports */ ++ for (i = 0; i < 7; i++) ++ ltq_switch_w32(0x1, BM_PCFG(i)); ++ ++ /* disable auto polling */ ++ ltq_mdio_w32(0x0, MDIO_CLK_CFG0); ++ ++ /* enable port statistic counters */ ++ for (i = 0; i < 7; i++) ++ ltq_switch_w32(0x1, BM_PCFGx(i)); ++ ++ /* set IPG to 12 */ ++ ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG); ++ ++#ifdef SW_ROUTING ++ /* enable status header, enable CRC */ ++ ltq_pmac_w32_mask(0, ++ PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC, ++ PMAC_HD_CTL); ++#else ++ /* disable status header, enable CRC */ ++ ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS, ++ PMAC_HD_CTL_AC, ++ PMAC_HD_CTL); ++#endif ++ ++ /* enable port fetch/store dma & VLAN Modification */ ++ for (i = 0; i < 7; i++ ) { ++ ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i)); ++ ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i)); ++ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0)); ++ } ++ ++ /* enable special tag insertion on cpu port */ ++ ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6)); ++ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0)); ++ ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2)); ++ ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG); ++} ++ ++static void xrx200_hw_cleanup(struct xrx200_hw *hw) ++{ ++ int i; ++ ++ /* disable the switch */ ++ ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB); ++ ++ /* free the channels and IRQs */ ++ for (i = 0; i < 2; i++) { ++ ltq_dma_free(&hw->chan[i].dma); ++ if (hw->chan[i].dma.irq) ++ free_irq(hw->chan[i].dma.irq, hw); ++ } ++ ++ /* free the allocated RX ring */ ++ for (i = 0; i < LTQ_DESC_NUM; i++) ++ dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]); ++ ++ /* clear the mdio bus */ ++ mdiobus_unregister(hw->mii_bus); ++ mdiobus_free(hw->mii_bus); ++ ++ /* release the clock */ ++ clk_disable(hw->clk); ++ clk_put(hw->clk); ++} ++ ++static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np) ++{ ++ hw->mii_bus = mdiobus_alloc(); ++ if (!hw->mii_bus) ++ return -ENOMEM; ++ ++ hw->mii_bus->read = xrx200_mdio_rd; ++ hw->mii_bus->write = xrx200_mdio_wr; ++ hw->mii_bus->name = "lantiq,xrx200-mdio"; ++ snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); ++ ++ if (of_mdiobus_register(hw->mii_bus, np)) { ++ mdiobus_free(hw->mii_bus); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port) ++{ ++ const __be32 *addr, *id = of_get_property(port, "reg", NULL); ++ struct xrx200_port *p = &priv->port[priv->num_port]; ++ ++ if (!id) ++ return; ++ ++ memset(p, 0, sizeof(struct xrx200_port)); ++ p->phy_node = of_parse_phandle(port, "phy-handle", 0); ++ addr = of_get_property(p->phy_node, "reg", NULL); ++ if (!addr) ++ return; ++ ++ p->num = *id; ++ p->phy_addr = *addr; ++ p->phy_if = of_get_phy_mode(port); ++ if (p->phy_addr > 0x10) ++ p->flags = XRX200_PORT_TYPE_MAC; ++ else ++ p->flags = XRX200_PORT_TYPE_PHY; ++ priv->num_port++; ++ ++ p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags); ++ if (gpio_is_valid(p->gpio)) ++ if (!gpio_request(p->gpio, "phy-reset")) { ++ gpio_direction_output(p->gpio, ++ (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0)); ++ udelay(100); ++ gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); ++ } ++ /* is this port a wan port ? */ ++ if (priv->wan) ++ priv->hw->wan_map |= BIT(p->num); ++ ++ priv->port_map |= BIT(p->num); ++ ++ /* store the port id in the hw struct so we can map ports -> devices */ ++ priv->hw->port_map[p->num] = priv->hw->num_devs; ++} ++ ++static const struct net_device_ops xrx200_netdev_ops = { ++ .ndo_init = xrx200_init, ++ .ndo_open = xrx200_open, ++ .ndo_stop = xrx200_close, ++ .ndo_start_xmit = xrx200_start_xmit, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_get_stats = xrx200_get_stats, ++ .ndo_tx_timeout = xrx200_tx_timeout, ++}; ++ ++static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface) ++{ ++ struct xrx200_priv *priv; ++ struct device_node *port; ++ const __be32 *wan; ++ ++ /* alloc the network device */ ++ hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv)); ++ if (!hw->devs[hw->num_devs]) ++ return; ++ ++ /* setup the network device */ ++ strcpy(hw->devs[hw->num_devs]->name, "eth%d"); ++ hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops; ++ hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT; ++ hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM; ++ ++ /* setup our private data */ ++ priv = netdev_priv(hw->devs[hw->num_devs]); ++ priv->hw = hw; ++ of_get_mac_address_mtd(iface, priv->mac); ++ priv->id = hw->num_devs; ++ ++ /* is this the wan interface ? */ ++ wan = of_get_property(iface, "lantiq,wan", NULL); ++ if (wan && (*wan == 1)) ++ priv->wan = 1; ++ ++ /* should the switch be enabled on this interface ? */ ++ if (of_find_property(iface, "lantiq,switch", NULL)) ++ priv->sw = 1; ++ ++ /* load the ports that are part of the interface */ ++ for_each_child_of_node(iface, port) ++ if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port")) ++ xrx200_of_port(priv, port); ++ ++ /* register the actual device */ ++ if (!register_netdev(hw->devs[hw->num_devs])) ++ hw->num_devs++; ++} ++ ++static struct xrx200_hw xrx200_hw; ++ ++static int xrx200_probe(struct platform_device *pdev) ++{ ++ struct resource *res[4]; ++ struct device_node *mdio_np, *iface_np; ++ int i; ++ ++ /* load the memory ranges */ ++ for (i = 0; i < 4; i++) { ++ res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ if (!res[i]) { ++ dev_err(&pdev->dev, "failed to get resources\n"); ++ return -ENOENT; ++ } ++ } ++ xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]); ++ xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]); ++ xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]); ++ xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]); ++ if (!xrx200_switch_membase || !xrx200_mdio_membase || ++ !xrx200_mii_membase || !xrx200_pmac_membase) { ++ dev_err(&pdev->dev, "failed to request and remap io ranges \n"); ++ return -ENOMEM; ++ } ++ ++ /* get the clock */ ++ xrx200_hw.clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(xrx200_hw.clk)) { ++ dev_err(&pdev->dev, "failed to get clock\n"); ++ return PTR_ERR(xrx200_hw.clk); ++ } ++ ++ /* bring up the dma engine and IP core */ ++ spin_lock_init(&xrx200_hw.lock); ++ xrx200_dma_init(&xrx200_hw); ++ xrx200_hw_init(&xrx200_hw); ++ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw); ++ ++ /* bring up the mdio bus */ ++ mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL, ++ "lantiq,xrx200-mdio"); ++ if (mdio_np) ++ if (xrx200_of_mdio(&xrx200_hw, mdio_np)) ++ dev_err(&pdev->dev, "mdio probe failed\n"); ++ ++ /* load the interfaces */ ++ for_each_child_of_node(pdev->dev.of_node, iface_np) ++ if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) { ++ if (xrx200_hw.num_devs < XRX200_MAX_DEV) ++ xrx200_of_iface(&xrx200_hw, iface_np); ++ else ++ dev_err(&pdev->dev, ++ "only %d interfaces allowed\n", ++ XRX200_MAX_DEV); ++ } ++ ++ if (!xrx200_hw.num_devs) { ++ xrx200_hw_cleanup(&xrx200_hw); ++ dev_err(&pdev->dev, "failed to load interfaces\n"); ++ return -ENOENT; ++ } ++ ++ xrx200sw_init(&xrx200_hw); ++ ++ /* set wan port mask */ ++ ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN); ++ ++ for (i = 0; i < xrx200_hw.num_devs; i++) { ++ xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i]; ++ xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i]; ++ } ++ ++ /* setup NAPI */ ++ init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev); ++ netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev, ++ &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32); ++ ++ platform_set_drvdata(pdev, &xrx200_hw); ++ ++ return 0; ++} ++ ++static int xrx200_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct xrx200_priv *priv; ++ ++ if (!dev) ++ return 0; ++ ++ priv = netdev_priv(dev); ++ ++ /* free stack related instances */ ++ netif_stop_queue(dev); ++ netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi); ++ ++ /* shut down hardware */ ++ xrx200_hw_cleanup(&xrx200_hw); ++ ++ /* remove the actual device */ ++ unregister_netdev(dev); ++ free_netdev(dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id xrx200_match[] = { ++ { .compatible = "lantiq,xrx200-net" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, xrx200_match); ++ ++static struct platform_driver xrx200_driver = { ++ .probe = xrx200_probe, ++ .remove = xrx200_remove, ++ .driver = { ++ .name = "lantiq,xrx200-net", ++ .of_match_table = xrx200_match, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(xrx200_driver); ++ ++MODULE_AUTHOR("John Crispin "); ++MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_xrx200_sw.h +@@ -0,0 +1,1328 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2013 Antonios Vamporakis ++ * ++ * VR9 switch registers extracted from 310TUJ0 switch api ++ * WARNING mult values of 0x00 may not be correct ++ * ++ */ ++ ++enum { ++// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */ ++// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */ ++// XRX200_ETHSW_SWRES_R0, /* Register Configuration */ ++// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */ ++// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */ ++// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */ ++// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */ ++// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */ ++// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */ ++// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */ ++// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */ ++// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */ ++// XRX200_ETHSW_DBG_MODE, /* Debug Mode */ ++// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */ ++// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */ ++// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */ ++// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */ ++// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */ ++// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */ ++// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */ ++// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */ ++// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */ ++// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */ ++// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */ ++// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */ ++// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */ ++// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */ ++// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */ ++// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */ ++// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */ ++// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */ ++// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */ ++// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */ ++// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */ ++// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */ ++// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */ ++// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */ ++// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */ ++// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */ ++// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */ ++// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */ ++// XRX200_ETHSW_CAP_6_APPL, /* Application table size */ ++// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */ ++// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */ ++// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */ ++// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */ ++// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */ ++// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */ ++// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */ ++// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */ ++// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */ ++// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */ ++// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */ ++// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */ ++// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */ ++// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */ ++// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */ ++// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */ ++// XRX200_ETHSW_IER, /* Interrupt Enable Register */ ++// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */ ++// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */ ++// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */ ++// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */ ++// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */ ++// XRX200_ETHSW_ISR, /* Interrupt Status Register */ ++// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */ ++// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */ ++// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */ ++// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */ ++// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */ ++// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */ ++// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */ ++// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */ ++// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */ ++// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */ ++// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */ ++// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */ ++// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */ ++// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */ ++// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */ ++// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */ ++// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */ ++// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */ ++// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */ ++// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */ ++// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */ ++// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */ ++// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */ ++// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */ ++// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */ ++// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */ ++// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */ ++// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */ ++// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */ ++// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */ ++// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */ ++// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */ ++// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */ ++// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */ ++// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */ ++// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */ ++// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */ ++// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */ ++// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */ ++// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */ ++// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */ ++// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */ ++// XRX200_BM_RAM_ADDR, /* RAM Address Register */ ++// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */ ++// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */ ++// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */ ++// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ ++// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */ ++// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */ ++// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */ ++// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */ ++// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */ ++// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */ ++// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */ ++// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */ ++// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */ ++// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */ ++// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */ ++// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */ ++// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */ ++// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */ ++// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */ ++// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */ ++// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */ ++// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */ ++// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */ ++// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */ ++// XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */ ++// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */ ++// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */ ++// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */ ++// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */ ++// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */ ++// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */ ++// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */ ++// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */ ++// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */ ++// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */ ++// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */ ++// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */ ++// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */ ++// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */ ++// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */ ++// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */ ++// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */ ++// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ ++// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */ ++// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ ++// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */ ++// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */ ++// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */ ++// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */ ++// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */ ++// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */ ++// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */ ++// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */ ++// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */ ++// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */ ++// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */ ++// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */ ++// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */ ++// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */ ++// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */ ++// XRX200_BM_CISEL_PORT, /* Port Number */ ++// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */ ++// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */ ++// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */ ++// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */ ++// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */ ++// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */ ++// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */ ++// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */ ++// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */ ++// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */ ++// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */ ++// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */ ++// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */ ++// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */ ++// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */ ++// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */ ++// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */ ++// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */ ++// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */ ++// XRX200_RS_CBS_CBS, /* Committed Burst Size */ ++// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */ ++// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */ ++// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */ ++// XRX200_RS_CIR_EXP_EXP, /* Exponent */ ++// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */ ++// XRX200_RS_CIR_MANT_MANT, /* Mantissa */ ++ XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */ ++// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */ ++// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */ ++// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */ ++// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */ ++// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */ ++// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */ ++// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */ ++ XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */ ++// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */ ++// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */ ++ XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */ ++// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */ ++// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */ ++// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */ ++// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */ ++// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */ ++// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */ ++ XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */ ++// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */ ++ XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */ ++ XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */ ++ XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */ ++ XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */ ++ XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ ++ XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */ ++// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */ ++// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */ ++// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */ ++// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */ ++// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */ ++// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */ ++// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */ ++// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */ ++// XRX200_PCE_PMAP_1, /* Port Map Register 1 */ ++// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */ ++// XRX200_PCE_PMAP_2, /* Port Map Register 2 */ ++// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */ ++// XRX200_PCE_PMAP_3, /* Port Map Register 3 */ ++// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */ ++// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */ ++// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */ ++ XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */ ++// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */ ++// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */ ++// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */ ++// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */ ++// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */ ++// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */ ++// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */ ++// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */ ++// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */ ++// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */ ++// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */ ++// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */ ++// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */ ++// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */ ++// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */ ++// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */ ++// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */ ++// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */ ++// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */ ++// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */ ++// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */ ++// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */ ++// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */ ++// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */ ++// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */ ++// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */ ++// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */ ++// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */ ++// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */ ++// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */ ++// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */ ++// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */ ++// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */ ++// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */ ++// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */ ++// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */ ++// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */ ++// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */ ++// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */ ++// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */ ++// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */ ++// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */ ++// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */ ++// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */ ++// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */ ++// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */ ++// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */ ++// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */ ++// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */ ++// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */ ++// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */ ++// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */ ++// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */ ++// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */ ++// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */ ++// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */ ++// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */ ++// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */ ++// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */ ++// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */ ++// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */ ++// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */ ++// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */ ++// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */ ++// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */ ++// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */ ++// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */ ++// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */ ++// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */ ++// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */ ++// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */ ++// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */ ++// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */ ++// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */ ++ XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */ ++// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */ ++// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */ ++// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */ ++// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */ ++// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */ ++// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */ ++// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */ ++// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */ ++// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */ ++// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */ ++// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */ ++// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */ ++// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */ ++// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */ ++// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */ ++// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */ ++// XRX200_WOL_CTRL_PORT, /* WoL Enable */ ++// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */ ++ XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */ ++ XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */ ++ XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */ ++ XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */ ++ XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */ ++// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */ ++ XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */ ++// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */ ++// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */ ++// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */ ++// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */ ++// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */ ++// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */ ++// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */ ++// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */ ++// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */ ++// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */ ++// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */ ++// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */ ++// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */ ++// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */ ++// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */ ++// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */ ++// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */ ++// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */ ++// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */ ++// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */ ++// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */ ++// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */ ++// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */ ++// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */ ++// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */ ++// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */ ++// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */ ++// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */ ++// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */ ++// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */ ++// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */ ++// XRX200_MAC_TEST, /* MAC Test Register */ ++// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */ ++// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */ ++// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */ ++// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */ ++// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */ ++// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */ ++// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */ ++// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */ ++// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */ ++// XRX200_MAC_FLEN, /* MAC Frame Length Register */ ++// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */ ++// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */ ++// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */ ++// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */ ++// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */ ++// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */ ++// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */ ++// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */ ++// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */ ++// XRX200_MAC_PSTAT, /* MAC Port Status Register */ ++// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */ ++ XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */ ++ XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */ ++ XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */ ++// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */ ++// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */ ++ XRX200_MAC_PSTAT_LSTAT, /* Link Status */ ++// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */ ++// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */ ++// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */ ++// XRX200_MAC_PISR, /* MAC Interrupt Status Register */ ++// XRX200_MAC_PISR_PACT, /* PHY Active Status */ ++// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */ ++// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */ ++// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */ ++// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */ ++// XRX200_MAC_PISR_JAM, /* Jam Status Detected */ ++// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */ ++// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */ ++// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */ ++// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */ ++// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */ ++// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */ ++// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */ ++// XRX200_MAC_PIER_PACT, /* PHY Active Status */ ++// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */ ++// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */ ++// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */ ++// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */ ++// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */ ++// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */ ++// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */ ++// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */ ++// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */ ++// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */ ++// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */ ++// XRX200_MAC_CTRL_0, /* MAC Control Register0 */ ++// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */ ++// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */ ++// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */ ++// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */ ++ XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */ ++// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */ ++// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */ ++// XRX200_MAC_CTRL_1, /* MAC Control Register1 */ ++// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */ ++// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */ ++// XRX200_MAC_CTRL_2, /* MAC Control Register2 */ ++// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */ ++// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */ ++// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */ ++// XRX200_MAC_CTRL_3, /* MAC Control Register3 */ ++// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */ ++// XRX200_MAC_CTRL_4, /* MAC Control Register4 */ ++// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */ ++// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */ ++// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */ ++// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */ ++// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */ ++// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */ ++// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */ ++// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */ ++// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */ ++// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */ ++// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */ ++// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */ ++// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */ ++// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */ ++// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */ ++// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */ ++// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */ ++// XRX200_MAC_TESTEN, /* MAC Test Enable Register */ ++// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */ ++// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */ ++// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */ ++// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */ ++// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */ ++// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */ ++// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */ ++// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */ ++// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */ ++// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */ ++// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */ ++// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */ ++// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */ ++// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */ ++// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */ ++// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */ ++// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */ ++// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */ ++// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */ ++// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */ ++// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */ ++// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */ ++// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */ ++// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */ ++// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */ ++// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */ ++// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */ ++// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */ ++// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */ ++// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */ ++// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */ ++// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */ ++// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */ ++// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */ ++// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */ ++// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */ ++// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */ ++// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ ++// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */ ++// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ ++// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */ ++// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */ ++// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */ ++// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */ ++// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */ ++// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */ ++// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */ ++// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */ ++// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */ ++// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */ ++// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */ ++// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */ ++// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */ ++// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */ ++// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */ ++// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */ ++// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */ ++// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */ ++// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */ ++// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */ ++// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */ ++// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */ ++// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */ ++// XRX200_SDMA_IER_BFULL, /* Buffer Full */ ++// XRX200_SDMA_IER_FERR, /* Frame Error */ ++// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */ ++// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */ ++// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */ ++// XRX200_SDMA_ISR_BFULL, /* Buffer Full */ ++// XRX200_SDMA_ISR_FERR, /* Frame Error */ ++// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */ ++// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */ ++// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */ ++// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */ ++// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */ ++// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */ ++// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */ ++// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */ ++// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */ ++// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */ ++// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */ ++// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */ ++// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */ ++// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */ ++// XRX200_SDMA_PCTRL_PEN, /* Port Enable */ ++// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */ ++// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */ ++// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */ ++// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */ ++// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */ ++// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */ ++// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */ ++// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ ++// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */ ++// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ ++}; ++ ++ ++struct xrx200sw_reg { ++ int offset; ++ int shift; ++ int size; ++ int mult; ++} xrx200sw_reg[] = { ++// offeset shift size mult ++// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */ ++// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */ ++// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */ ++// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */ ++// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */ ++// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */ ++// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */ ++// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */ ++// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */ ++// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */ ++// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */ ++// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */ ++// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */ ++// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */ ++// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */ ++// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */ ++// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */ ++// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */ ++// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */ ++// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */ ++// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */ ++// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */ ++// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */ ++// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */ ++// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */ ++// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */ ++// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */ ++// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */ ++// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */ ++// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */ ++// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */ ++// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */ ++// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */ ++// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */ ++// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */ ++// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */ ++// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */ ++// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */ ++// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */ ++// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */ ++// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */ ++// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */ ++// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */ ++// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */ ++// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */ ++// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */ ++// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */ ++// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */ ++// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */ ++// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */ ++// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */ ++// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */ ++// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */ ++// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */ ++// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */ ++// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */ ++// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */ ++// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */ ++// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */ ++// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */ ++// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */ ++// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */ ++// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */ ++// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */ ++// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */ ++// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */ ++// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */ ++// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */ ++// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */ ++// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */ ++// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */ ++// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */ ++// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */ ++// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */ ++// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */ ++// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */ ++// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */ ++// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */ ++// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */ ++// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */ ++// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */ ++// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */ ++// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */ ++// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */ ++// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */ ++// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */ ++// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */ ++// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */ ++// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */ ++// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */ ++// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */ ++// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */ ++// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */ ++// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */ ++// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */ ++// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */ ++// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */ ++// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */ ++// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */ ++// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */ ++// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */ ++// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */ ++// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */ ++// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */ ++// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */ ++// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */ ++// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */ ++// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */ ++// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */ ++// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */ ++// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */ ++// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */ ++// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */ ++// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */ ++// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */ ++// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */ ++// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */ ++// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */ ++// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */ ++// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */ ++// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */ ++// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */ ++// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */ ++// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */ ++// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */ ++// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */ ++// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */ ++// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */ ++// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */ ++// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */ ++// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */ ++// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */ ++// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */ ++// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */ ++// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */ ++// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */ ++// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */ ++// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */ ++// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */ ++// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */ ++// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */ ++// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */ ++// {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */ ++// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */ ++// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */ ++// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */ ++// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */ ++// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */ ++// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */ ++// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */ ++// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */ ++// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */ ++// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */ ++// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */ ++// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */ ++// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */ ++// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */ ++// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */ ++// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */ ++// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */ ++// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */ ++// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */ ++// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */ ++// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */ ++// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */ ++// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */ ++// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ ++// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */ ++// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ ++// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */ ++// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */ ++// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */ ++// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */ ++// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */ ++// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */ ++// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */ ++// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */ ++// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */ ++// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */ ++// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */ ++// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */ ++// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */ ++// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */ ++// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */ ++// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */ ++// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */ ++// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */ ++// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */ ++// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */ ++// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */ ++// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */ ++// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */ ++// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */ ++// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */ ++// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */ ++// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */ ++// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */ ++// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */ ++// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */ ++// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */ ++// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */ ++// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */ ++// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */ ++// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */ ++// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */ ++// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */ ++// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */ ++// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */ ++// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */ ++// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */ ++// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */ ++ {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */ ++// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */ ++ {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */ ++// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */ ++ {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */ ++// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */ ++ {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */ ++// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */ ++ {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */ ++// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */ ++ {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */ ++// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */ ++ {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */ ++// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */ ++ {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */ ++// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */ ++ {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */ ++// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */ ++ {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */ ++// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */ ++ {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */ ++// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */ ++ {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */ ++// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */ ++ {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */ ++// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */ ++ {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */ ++// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */ ++// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */ ++ {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */ ++// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */ ++ {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */ ++ {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */ ++ {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */ ++ {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */ ++ {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */ ++ {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */ ++// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */ ++// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */ ++// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */ ++// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */ ++// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */ ++// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */ ++// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */ ++// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */ ++// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */ ++// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */ ++// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */ ++// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */ ++// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */ ++// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */ ++// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */ ++// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */ ++ {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */ ++// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */ ++// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */ ++// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */ ++// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */ ++// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */ ++// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */ ++// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */ ++// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */ ++// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */ ++// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */ ++// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */ ++// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */ ++// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */ ++// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */ ++// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */ ++// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */ ++// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */ ++// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */ ++// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */ ++// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */ ++// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */ ++// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */ ++// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */ ++// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */ ++// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */ ++// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */ ++// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */ ++// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */ ++// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */ ++// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */ ++// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */ ++// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */ ++// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */ ++// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */ ++// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */ ++// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */ ++// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */ ++// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */ ++// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */ ++// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */ ++// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */ ++// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */ ++// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */ ++// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */ ++// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */ ++// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */ ++// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */ ++// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */ ++// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */ ++// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */ ++// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */ ++// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */ ++// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */ ++// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */ ++// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */ ++// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */ ++// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */ ++// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */ ++// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */ ++// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */ ++// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */ ++// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */ ++// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */ ++// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */ ++// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */ ++// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */ ++// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */ ++// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */ ++// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */ ++// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */ ++// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */ ++// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */ ++// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */ ++// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */ ++// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */ ++// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */ ++// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */ ++// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */ ++// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */ ++// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */ ++// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */ ++// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */ ++// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */ ++// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */ ++// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */ ++// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */ ++// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */ ++// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */ ++// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */ ++// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */ ++// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */ ++// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */ ++// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */ ++// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */ ++// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */ ++// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */ ++// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */ ++// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */ ++// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */ ++// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */ ++// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */ ++// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */ ++// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */ ++// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */ ++// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */ ++// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */ ++// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */ ++// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */ ++// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */ ++// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */ ++// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */ ++// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */ ++// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */ ++// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */ ++// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */ ++// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */ ++ {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */ ++// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */ ++// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */ ++// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */ ++// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */ ++// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */ ++// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */ ++// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */ ++// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */ ++// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */ ++// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */ ++// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */ ++// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */ ++// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */ ++// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */ ++// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */ ++// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */ ++// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */ ++// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */ ++// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */ ++// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */ ++// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */ ++// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */ ++// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */ ++// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */ ++// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */ ++// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */ ++ {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */ ++ {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */ ++ {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */ ++ {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */ ++ {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */ ++// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */ ++ {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */ ++// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */ ++// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */ ++// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */ ++// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */ ++// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */ ++// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */ ++// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */ ++// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */ ++// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */ ++// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */ ++// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */ ++// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */ ++// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */ ++// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */ ++// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */ ++// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */ ++// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */ ++// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */ ++// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */ ++// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */ ++// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */ ++// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */ ++// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */ ++// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */ ++// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */ ++// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */ ++// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */ ++// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */ ++// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */ ++// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */ ++// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */ ++// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */ ++// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */ ++// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */ ++// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */ ++// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */ ++// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */ ++// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */ ++// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */ ++// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */ ++// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */ ++// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */ ++// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */ ++// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */ ++// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */ ++// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */ ++// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */ ++// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */ ++// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */ ++// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */ ++// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */ ++// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */ ++// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */ ++ {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */ ++ {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */ ++ {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */ ++// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */ ++// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */ ++// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */ ++// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */ ++ {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */ ++// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */ ++// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */ ++// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */ ++// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */ ++// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */ ++// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */ ++// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */ ++// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */ ++// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */ ++// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */ ++// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */ ++// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */ ++// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */ ++// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */ ++// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */ ++// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */ ++// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */ ++// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */ ++// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */ ++// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */ ++// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */ ++// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */ ++// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */ ++// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */ ++// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */ ++// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */ ++// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */ ++// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */ ++// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */ ++// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */ ++// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */ ++// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */ ++// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */ ++// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */ ++// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */ ++// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */ ++// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */ ++// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */ ++// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */ ++// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */ ++// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */ ++ {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */ ++// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */ ++// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */ ++// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */ ++// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */ ++// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */ ++// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */ ++// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */ ++// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */ ++// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */ ++// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */ ++// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */ ++// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */ ++// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */ ++// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */ ++// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */ ++// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */ ++// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */ ++// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */ ++// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */ ++// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */ ++// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */ ++// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */ ++// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */ ++// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */ ++// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */ ++// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */ ++// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */ ++// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */ ++// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */ ++// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */ ++// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */ ++// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */ ++// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */ ++// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */ ++// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */ ++// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */ ++// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */ ++// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */ ++// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */ ++// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */ ++// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */ ++// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */ ++// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */ ++// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */ ++// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */ ++// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */ ++// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */ ++// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */ ++// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */ ++// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */ ++// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */ ++// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */ ++// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */ ++// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */ ++// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */ ++// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */ ++// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */ ++// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */ ++// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */ ++// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */ ++// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */ ++// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */ ++// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */ ++// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */ ++// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */ ++// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */ ++// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */ ++// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */ ++// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */ ++// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */ ++// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */ ++// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */ ++// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */ ++// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */ ++// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */ ++// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */ ++// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */ ++// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */ ++// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */ ++// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */ ++// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */ ++// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */ ++// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */ ++// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */ ++// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */ ++// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */ ++// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */ ++// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */ ++// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */ ++// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */ ++// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */ ++// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */ ++// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */ ++// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */ ++// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */ ++// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */ ++// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */ ++// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */ ++// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */ ++// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */ ++// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */ ++// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */ ++// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */ ++// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */ ++// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */ ++// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */ ++// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */ ++// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */ ++// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */ ++// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */ ++// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */ ++// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */ ++// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */ ++// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */ ++// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */ ++// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */ ++// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */ ++// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */ ++// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */ ++// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */ ++// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */ ++// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */ ++// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */ ++// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */ ++// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */ ++// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */ ++// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */ ++// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */ ++}; ++ ++ diff --git a/target/linux/lantiq/patches-3.18/0026-NET-multi-phy-support.patch b/target/linux/lantiq/patches-3.18/0026-NET-multi-phy-support.patch new file mode 100644 index 0000000..5943602 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0026-NET-multi-phy-support.patch @@ -0,0 +1,53 @@ +From c6feeeb407a3b8a6597ae377ba4dd138e185e3dd Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 27 Jul 2014 09:38:50 +0100 +Subject: [PATCH 26/36] NET: multi phy support + +Signed-off-by: John Crispin +--- + drivers/net/phy/phy.c | 9 ++++++--- + include/linux/phy.h | 1 + + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -838,7 +838,8 @@ void phy_state_machine(struct work_struc + /* If the link is down, give up on negotiation for now */ + if (!phydev->link) { + phydev->state = PHY_NOLINK; +- netif_carrier_off(phydev->attached_dev); ++ if (!phydev->no_auto_carrier_off) ++ netif_carrier_off(phydev->attached_dev); + phydev->adjust_link(phydev->attached_dev); + break; + } +@@ -911,7 +912,8 @@ void phy_state_machine(struct work_struc + netif_carrier_on(phydev->attached_dev); + } else { + phydev->state = PHY_NOLINK; +- netif_carrier_off(phydev->attached_dev); ++ if (!phydev->no_auto_carrier_off) ++ netif_carrier_off(phydev->attached_dev); + } + + phydev->adjust_link(phydev->attached_dev); +@@ -923,7 +925,8 @@ void phy_state_machine(struct work_struc + case PHY_HALTED: + if (phydev->link) { + phydev->link = 0; +- netif_carrier_off(phydev->attached_dev); ++ if (!phydev->no_auto_carrier_off) ++ netif_carrier_off(phydev->attached_dev); + phydev->adjust_link(phydev->attached_dev); + do_suspend = true; + } +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -364,6 +364,7 @@ struct phy_device { + bool is_c45; + bool is_internal; + bool has_fixups; ++ bool no_auto_carrier_off; + + enum phy_state state; + diff --git a/target/linux/lantiq/patches-3.18/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-3.18/0028-NET-lantiq-various-etop-fixes.patch new file mode 100644 index 0000000..6a752f9 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0028-NET-lantiq-various-etop-fixes.patch @@ -0,0 +1,908 @@ +From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 22:45:34 +0200 +Subject: [PATCH 28/36] NET: lantiq: various etop fixes + +Signed-off-by: John Crispin +--- + drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- + 1 file changed, 389 insertions(+), 166 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -11,7 +11,7 @@ + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * +- * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011-12 John Crispin + */ + + #include +@@ -30,11 +30,16 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include ++#include ++#include ++#include ++#include + + #include + +@@ -42,7 +47,7 @@ + #include + #include + +-#define LTQ_ETOP_MDIO 0x11804 ++#define LTQ_ETOP_MDIO_ACC 0x11804 + #define MDIO_REQUEST 0x80000000 + #define MDIO_READ 0x40000000 + #define MDIO_ADDR_MASK 0x1f +@@ -51,44 +56,91 @@ + #define MDIO_REG_OFFSET 0x10 + #define MDIO_VAL_MASK 0xffff + +-#define PPE32_CGEN 0x800 +-#define LQ_PPE32_ENET_MAC_CFG 0x1840 ++#define LTQ_ETOP_MDIO_CFG 0x11800 ++#define MDIO_CFG_MASK 0x6 ++ ++#define LTQ_ETOP_CFG 0x11808 ++#define LTQ_ETOP_IGPLEN 0x11820 ++#define LTQ_ETOP_MAC_CFG 0x11840 + + #define LTQ_ETOP_ENETS0 0x11850 + #define LTQ_ETOP_MAC_DA0 0x1186C + #define LTQ_ETOP_MAC_DA1 0x11870 +-#define LTQ_ETOP_CFG 0x16020 +-#define LTQ_ETOP_IGPLEN 0x16080 ++ ++#define MAC_CFG_MASK 0xfff ++#define MAC_CFG_CGEN (1 << 11) ++#define MAC_CFG_DUPLEX (1 << 2) ++#define MAC_CFG_SPEED (1 << 1) ++#define MAC_CFG_LINK (1 << 0) + + #define MAX_DMA_CHAN 0x8 + #define MAX_DMA_CRC_LEN 0x4 + #define MAX_DMA_DATA_LEN 0x600 + + #define ETOP_FTCU BIT(28) +-#define ETOP_MII_MASK 0xf +-#define ETOP_MII_NORMAL 0xd +-#define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 +-#define ETOP_CGEN 0x800 ++#define ETOP_CFG_MII0 0x01 + +-/* use 2 static channels for TX/RX */ +-#define LTQ_ETOP_TX_CHANNEL 1 +-#define LTQ_ETOP_RX_CHANNEL 6 +-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) ++#define ETOP_CFG_MASK 0xfff ++#define ETOP_CFG_FEN0 (1 << 8) ++#define ETOP_CFG_SEN0 (1 << 6) ++#define ETOP_CFG_OFF1 (1 << 3) ++#define ETOP_CFG_REMII0 (1 << 1) ++#define ETOP_CFG_OFF0 (1 << 0) ++ ++#define LTQ_GBIT_MDIO_CTL 0xCC ++#define LTQ_GBIT_MDIO_DATA 0xd0 ++#define LTQ_GBIT_GCTL0 0x68 ++#define LTQ_GBIT_PMAC_HD_CTL 0x8c ++#define LTQ_GBIT_P0_CTL 0x4 ++#define LTQ_GBIT_PMAC_RX_IPG 0xa8 ++#define LTQ_GBIT_RGMII_CTL 0x78 ++ ++#define PMAC_HD_CTL_AS (1 << 19) ++#define PMAC_HD_CTL_RXSH (1 << 22) ++ ++/* Switch Enable (0=disable, 1=enable) */ ++#define GCTL0_SE 0x80000000 ++/* Disable MDIO auto polling (0=disable, 1=enable) */ ++#define PX_CTL_DMDIO 0x00400000 ++ ++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ ++#define MDC_CLOCK_MASK 0xff000000 ++#define MDC_CLOCK_OFFSET 24 ++ ++/* register information for the gbit's MDIO bus */ ++#define MDIO_XR9_REQUEST 0x00008000 ++#define MDIO_XR9_READ 0x00000800 ++#define MDIO_XR9_WRITE 0x00000400 ++#define MDIO_XR9_REG_MASK 0x1f ++#define MDIO_XR9_ADDR_MASK 0x1f ++#define MDIO_XR9_RD_MASK 0xffff ++#define MDIO_XR9_REG_OFFSET 0 ++#define MDIO_XR9_ADDR_OFFSET 5 ++#define MDIO_XR9_WR_OFFSET 16 + ++#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ ++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) ++ ++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ + #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) + #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) + #define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +-#define DRV_VERSION "1.0" ++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) ++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) ++#define ltq_gbit_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) ++ ++#define DRV_VERSION "1.2" + + static void __iomem *ltq_etop_membase; ++static void __iomem *ltq_gbit_membase; + + struct ltq_etop_chan { +- int idx; + int tx_free; ++ int irq; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; +@@ -98,22 +150,35 @@ struct ltq_etop_chan { + struct ltq_etop_priv { + struct net_device *netdev; + struct platform_device *pdev; +- struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + struct phy_device *phydev; + +- struct ltq_etop_chan ch[MAX_DMA_CHAN]; +- int tx_free[MAX_DMA_CHAN >> 1]; ++ struct ltq_etop_chan txch; ++ struct ltq_etop_chan rxch; ++ ++ int tx_irq; ++ int rx_irq; ++ ++ unsigned char mac[6]; ++ int mii_mode; + + spinlock_t lock; ++ ++ struct clk *clk_ppe; ++ struct clk *clk_switch; ++ struct clk *clk_ephy; ++ struct clk *clk_ephycgu; + }; + ++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data); ++ + static int + ltq_etop_alloc_skb(struct ltq_etop_chan *ch) + { +- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); ++ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, +@@ -148,8 +213,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); ++ skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); ++ ch->netdev->stats.rx_packets++; ++ ch->netdev->stats.rx_bytes += len; + } + + static int +@@ -157,8 +225,10 @@ ltq_etop_poll_rx(struct napi_struct *nap + { + struct ltq_etop_chan *ch = container_of(napi, + struct ltq_etop_chan, napi); ++ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + int rx = 0; + int complete = 0; ++ unsigned long flags; + + while ((rx < budget) && !complete) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +@@ -172,7 +242,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + } + if (complete || !rx) { + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + } + return rx; + } +@@ -184,12 +256,14 @@ ltq_etop_poll_tx(struct napi_struct *nap + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = +- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); ++ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ ch->netdev->stats.tx_packets++; ++ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, +@@ -202,7 +276,9 @@ ltq_etop_poll_tx(struct napi_struct *nap + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + return 1; + } + +@@ -210,9 +286,10 @@ static irqreturn_t + ltq_etop_dma_irq(int irq, void *_priv) + { + struct ltq_etop_priv *priv = _priv; +- int ch = irq - LTQ_DMA_CH0_INT; +- +- napi_schedule(&priv->ch[ch].napi); ++ if (irq == priv->txch.dma.irq) ++ napi_schedule(&priv->txch.napi); ++ else ++ napi_schedule(&priv->rxch.napi); + return IRQ_HANDLED; + } + +@@ -224,7 +301,7 @@ ltq_etop_free_channel(struct net_device + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); +- if (IS_RX(ch->idx)) { ++ if (ch == &priv->txch) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); +@@ -235,65 +312,133 @@ static void + ltq_etop_hw_exit(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; + +- ltq_pmu_disable(PMU_PPE); +- for (i = 0; i < MAX_DMA_CHAN; i++) +- if (IS_TX(i) || IS_RX(i)) +- ltq_etop_free_channel(dev, &priv->ch[i]); ++ clk_disable(priv->clk_ppe); ++ ++ if (of_machine_is_compatible("lantiq,ar9")) ++ clk_disable(priv->clk_switch); ++ ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_disable(priv->clk_ephy); ++ clk_disable(priv->clk_ephycgu); ++ } ++ ++ ltq_etop_free_channel(dev, &priv->txch); ++ ltq_etop_free_channel(dev, &priv->rxch); ++} ++ ++static void ++ltq_etop_gbit_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ ++ clk_enable(priv->clk_switch); ++ ++ /* enable gbit port0 on the SoC */ ++ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); ++ ++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); ++ /* disable MDIO auto polling mode */ ++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); ++ /* set 1522 packet size */ ++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); ++ /* disable pmac & dmac headers */ ++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, ++ LTQ_GBIT_PMAC_HD_CTL); ++ /* Due to traffic halt when burst length 8, ++ replace default IPG value with 0x3B */ ++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); ++ /* set mdc clock to 2.5 MHz */ ++ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, ++ LTQ_GBIT_RGMII_CTL); + } + + static int + ltq_etop_hw_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ int mii_mode = priv->mii_mode; + +- ltq_pmu_enable(PMU_PPE); ++ clk_enable(priv->clk_ppe); ++ ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ ltq_etop_gbit_init(dev); ++ /* force the etops link to the gbit to MII */ ++ mii_mode = PHY_INTERFACE_MODE_MII; ++ } ++ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); ++ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | ++ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); + +- switch (priv->pldata->mii_mode) { ++ switch (mii_mode) { + case PHY_INTERFACE_MODE_RMII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_REVERSE, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + case PHY_INTERFACE_MODE_MII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_NORMAL, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + default: ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_enable(priv->clk_ephy); ++ /* disable external MII */ ++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); ++ /* enable clock for internal PHY */ ++ clk_enable(priv->clk_ephycgu); ++ /* we need to write this magic to the internal phy to ++ make it work */ ++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); ++ pr_info("Selected EPHY mode\n"); ++ break; ++ } + netdev_err(dev, "unknown mii mode %d\n", +- priv->pldata->mii_mode); ++ mii_mode); + return -ENOTSUPP; + } + +- /* enable crc generation */ +- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); ++ return 0; ++} ++ ++static int ++ltq_etop_dma_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ int tx = priv->tx_irq - LTQ_DMA_ETOP; ++ int rx = priv->rx_irq - LTQ_DMA_ETOP; ++ int err; + + ltq_dma_init_port(DMA_PORT_ETOP); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- int irq = LTQ_DMA_CH0_INT + i; +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- ch->idx = ch->dma.nr = i; +- +- if (IS_TX(i)) { +- ltq_dma_alloc_tx(&ch->dma); +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); +- } else if (IS_RX(i)) { +- ltq_dma_alloc_rx(&ch->dma); +- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; +- ch->dma.desc++) +- if (ltq_etop_alloc_skb(ch)) +- return -ENOMEM; +- ch->dma.desc = 0; +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); ++ priv->txch.dma.nr = tx; ++ ltq_dma_alloc_tx(&priv->txch.dma); ++ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); ++ if (err) { ++ netdev_err(dev, "failed to allocate tx irq\n"); ++ goto err_out; ++ } ++ priv->txch.dma.irq = priv->tx_irq; ++ ++ priv->rxch.dma.nr = rx; ++ ltq_dma_alloc_rx(&priv->rxch.dma); ++ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; ++ priv->rxch.dma.desc++) { ++ if (ltq_etop_alloc_skb(&priv->rxch)) { ++ netdev_err(dev, "failed to allocate skbs\n"); ++ err = -ENOMEM; ++ goto err_out; + } +- ch->dma.irq = irq; + } +- return 0; ++ priv->rxch.dma.desc = 0; ++ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); ++ if (err) ++ netdev_err(dev, "failed to allocate rx irq\n"); ++ else ++ priv->rxch.dma.irq = priv->rx_irq; ++err_out: ++ return err; + } + + static void +@@ -309,7 +454,10 @@ ltq_etop_get_settings(struct net_device + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_ethtool_gset(priv->phydev, cmd); ++ if (priv->phydev) ++ return phy_ethtool_gset(priv->phydev, cmd); ++ else ++ return 0; + } + + static int +@@ -317,7 +465,10 @@ ltq_etop_set_settings(struct net_device + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_ethtool_sset(priv->phydev, cmd); ++ if (priv->phydev) ++ return phy_ethtool_sset(priv->phydev, cmd); ++ else ++ return 0; + } + + static int +@@ -325,7 +476,10 @@ ltq_etop_nway_reset(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_start_aneg(priv->phydev); ++ if (priv->phydev) ++ return phy_start_aneg(priv->phydev); ++ else ++ return 0; + } + + static const struct ethtool_ops ltq_etop_ethtool_ops = { +@@ -336,6 +490,39 @@ static const struct ethtool_ops ltq_etop + }; + + static int ++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | ++ (phy_data << MDIO_XR9_WR_OFFSET) | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ return 0; ++} ++ ++static int ++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; ++ return val; ++} ++ ++static int + ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) + { + u32 val = MDIO_REQUEST | +@@ -343,9 +530,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); + return 0; + } + +@@ -356,12 +543,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; ++ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; + return val; + } + +@@ -376,14 +563,18 @@ ltq_etop_mdio_probe(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; +- int phy_addr; ++ u32 phy_supported = (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_Autoneg ++ | SUPPORTED_MII ++ | SUPPORTED_TP); + +- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { +- if (priv->mii_bus->phy_map[phy_addr]) { +- phydev = priv->mii_bus->phy_map[phy_addr]; +- break; +- } +- } ++ if (of_machine_is_compatible("lantiq,ase")) ++ phydev = priv->mii_bus->phy_map[8]; ++ else ++ phydev = priv->mii_bus->phy_map[0]; + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); +@@ -391,21 +582,18 @@ ltq_etop_mdio_probe(struct net_device *d + } + + phydev = phy_connect(dev, dev_name(&phydev->dev), +- <q_etop_mdio_link, priv->pldata->mii_mode); ++ <q_etop_mdio_link, priv->mii_mode); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + +- phydev->supported &= (SUPPORTED_10baseT_Half +- | SUPPORTED_10baseT_Full +- | SUPPORTED_100baseT_Half +- | SUPPORTED_100baseT_Full +- | SUPPORTED_Autoneg +- | SUPPORTED_MII +- | SUPPORTED_TP); ++ if (of_machine_is_compatible("lantiq,ar9")) ++ phy_supported |= SUPPORTED_1000baseT_Half ++ | SUPPORTED_1000baseT_Full; + ++ phydev->supported &= phy_supported; + phydev->advertising = phydev->supported; + priv->phydev = phydev; + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", +@@ -430,8 +618,13 @@ ltq_etop_mdio_init(struct net_device *de + } + + priv->mii_bus->priv = dev; +- priv->mii_bus->read = ltq_etop_mdio_rd; +- priv->mii_bus->write = ltq_etop_mdio_wr; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; ++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; ++ } else { ++ priv->mii_bus->read = ltq_etop_mdio_rd; ++ priv->mii_bus->write = ltq_etop_mdio_wr; ++ } + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +@@ -480,17 +673,19 @@ static int + ltq_etop_open(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; ++ napi_enable(&priv->txch.napi); ++ napi_enable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_open(&priv->txch.dma); ++ ltq_dma_open(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (priv->phydev) ++ phy_start(priv->phydev); + +- if (!IS_TX(i) && (!IS_RX(i))) +- continue; +- ltq_dma_open(&ch->dma); +- napi_enable(&ch->napi); +- } +- phy_start(priv->phydev); + netif_tx_start_all_queues(dev); + return 0; + } +@@ -499,18 +694,19 @@ static int + ltq_etop_stop(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + + netif_tx_stop_all_queues(dev); +- phy_stop(priv->phydev); +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- if (!IS_RX(i) && !IS_TX(i)) +- continue; +- napi_disable(&ch->napi); +- ltq_dma_close(&ch->dma); +- } ++ if (priv->phydev) ++ phy_stop(priv->phydev); ++ napi_disable(&priv->txch.napi); ++ napi_disable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_close(&priv->txch.dma); ++ ltq_dma_close(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ + return 0; + } + +@@ -520,16 +716,16 @@ ltq_etop_tx(struct sk_buff *skb, struct + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); +- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; +- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- int len; ++ struct ltq_dma_desc *desc = ++ &priv->txch.dma.desc_base[priv->txch.dma.desc]; + unsigned long flags; + u32 byte_offset; ++ int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + +- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { +- dev_kfree_skb_any(skb); ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ++ priv->txch.skb[priv->txch.dma.desc]) { + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; +@@ -537,7 +733,7 @@ ltq_etop_tx(struct sk_buff *skb, struct + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; +- ch->skb[ch->dma.desc] = skb; ++ priv->txch.skb[priv->txch.dma.desc] = skb; + + dev->trans_start = jiffies; + +@@ -547,11 +743,11 @@ ltq_etop_tx(struct sk_buff *skb, struct + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); +- ch->dma.desc++; +- ch->dma.desc %= LTQ_DESC_NUM; ++ priv->txch.dma.desc++; ++ priv->txch.dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + +- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +@@ -566,8 +762,10 @@ ltq_etop_change_mtu(struct net_device *d + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; + ++ int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; ++ + spin_lock_irqsave(&priv->lock, flags); +- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, ++ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, + LTQ_ETOP_IGPLEN); + spin_unlock_irqrestore(&priv->lock, flags); + } +@@ -638,6 +836,9 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + if (!is_valid_ether_addr(mac.sa_data)) { +@@ -655,9 +856,10 @@ ltq_etop_init(struct net_device *dev) + dev->addr_assign_type = NET_ADDR_RANDOM; + + ltq_etop_set_multicast_list(dev); +- err = ltq_etop_mdio_init(dev); +- if (err) +- goto err_netdev; ++ if (!ltq_etop_mdio_init(dev)) ++ dev->ethtool_ops = <q_etop_ethtool_ops; ++ else ++ pr_warn("etop: mdio probe failed\n");; + return 0; + + err_netdev: +@@ -677,6 +879,9 @@ ltq_etop_tx_timeout(struct net_device *d + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + dev->trans_start = jiffies; + netif_wake_queue(dev); + return; +@@ -700,14 +905,18 @@ static const struct net_device_ops ltq_e + .ndo_tx_timeout = ltq_etop_tx_timeout, + }; + +-static int __init +-ltq_etop_probe(struct platform_device *pdev) ++static int ltq_etop_probe(struct platform_device *pdev) + { + struct net_device *dev; + struct ltq_etop_priv *priv; +- struct resource *res; ++ struct resource *res, *gbit_res, irqres[2]; + int err; +- int i; ++ ++ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); ++ if (err != 2) { ++ dev_err(&pdev->dev, "failed to get etop irqs\n"); ++ return -EINVAL; ++ } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -733,30 +942,58 @@ ltq_etop_probe(struct platform_device *p + goto err_out; + } + +- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); +- if (!dev) { +- err = -ENOMEM; +- goto err_out; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!gbit_res) { ++ dev_err(&pdev->dev, "failed to get gbit resource\n"); ++ err = -ENOENT; ++ goto err_out; ++ } ++ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, ++ gbit_res->start, resource_size(gbit_res)); ++ if (!ltq_gbit_membase) { ++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", ++ pdev->id); ++ err = -ENOMEM; ++ goto err_out; ++ } + } ++ ++ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; +- dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pdev = pdev; +- priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; ++ priv->tx_irq = irqres[0].start; ++ priv->rx_irq = irqres[1].start; ++ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node); ++ of_get_mac_address_mtd(pdev->dev.of_node, priv->mac); ++ ++ priv->clk_ppe = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_ppe)) ++ return PTR_ERR(priv->clk_ppe); ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->clk_switch = clk_get(&pdev->dev, "switch"); ++ if (IS_ERR(priv->clk_switch)) ++ return PTR_ERR(priv->clk_switch); ++ } ++ if (of_machine_is_compatible("lantiq,ase")) { ++ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); ++ if (IS_ERR(priv->clk_ephy)) ++ return PTR_ERR(priv->clk_ephy); ++ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); ++ if (IS_ERR(priv->clk_ephycgu)) ++ return PTR_ERR(priv->clk_ephycgu); ++ } ++ + spin_lock_init(&priv->lock); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- if (IS_TX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_tx, 8); +- else if (IS_RX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_rx, 32); +- priv->ch[i].netdev = dev; +- } ++ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); ++ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); ++ priv->txch.netdev = dev; ++ priv->rxch.netdev = dev; + + err = register_netdev(dev); + if (err) +@@ -785,32 +1022,23 @@ ltq_etop_remove(struct platform_device * + return 0; + } + ++static const struct of_device_id ltq_etop_match[] = { ++ { .compatible = "lantiq,etop-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_etop_match); ++ + static struct platform_driver ltq_mii_driver = { ++ .probe = ltq_etop_probe, + .remove = ltq_etop_remove, + .driver = { + .name = "ltq_etop", + .owner = THIS_MODULE, ++ .of_match_table = ltq_etop_match, + }, + }; + +-int __init +-init_ltq_etop(void) +-{ +- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); +- +- if (ret) +- pr_err("ltq_etop: Error registering platform driver!"); +- return ret; +-} +- +-static void __exit +-exit_ltq_etop(void) +-{ +- platform_driver_unregister(<q_mii_driver); +-} +- +-module_init(init_ltq_etop); +-module_exit(exit_ltq_etop); ++module_platform_driver(ltq_mii_driver); + + MODULE_AUTHOR("John Crispin "); + MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-3.18/0030-GPIO-add-named-gpio-exports.patch b/target/linux/lantiq/patches-3.18/0030-GPIO-add-named-gpio-exports.patch new file mode 100644 index 0000000..855da68 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0030-GPIO-add-named-gpio-exports.patch @@ -0,0 +1,166 @@ +From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 12 Aug 2014 20:49:27 +0200 +Subject: [PATCH 30/36] GPIO: add named gpio exports + +Signed-off-by: John Crispin +--- + drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++ + drivers/gpio/gpiolib.c | 11 +++++-- + include/asm-generic/gpio.h | 5 +++ + include/linux/gpio/consumer.h | 8 +++++ + 4 files changed, 90 insertions(+), 2 deletions(-) + +--- a/drivers/gpio/gpiolib-of.c ++++ b/drivers/gpio/gpiolib-of.c +@@ -22,6 +22,8 @@ + #include + #include + #include ++#include ++#include + + #include "gpiolib.h" + +@@ -316,3 +318,69 @@ void of_gpiochip_remove(struct gpio_chip + gpiochip_remove_pin_ranges(chip); + of_node_put(chip->of_node); + } ++ ++static struct of_device_id gpio_export_ids[] = { ++ { .compatible = "gpio-export" }, ++ { /* sentinel */ } ++}; ++ ++static int __init of_gpio_export_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct device_node *cnp; ++ u32 val; ++ int nb = 0; ++ ++ for_each_child_of_node(np, cnp) { ++ const char *name = NULL; ++ int gpio; ++ bool dmc; ++ int max_gpio = 1; ++ int i; ++ ++ of_property_read_string(cnp, "gpio-export,name", &name); ++ ++ if (!name) ++ max_gpio = of_gpio_count(cnp); ++ ++ for (i = 0; i < max_gpio; i++) { ++ unsigned flags = 0; ++ enum of_gpio_flags of_flags; ++ ++ gpio = of_get_gpio_flags(cnp, i, &of_flags); ++ ++ if (of_flags == OF_GPIO_ACTIVE_LOW) ++ flags |= GPIOF_ACTIVE_LOW; ++ ++ if (!of_property_read_u32(cnp, "gpio-export,output", &val)) ++ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; ++ else ++ flags |= GPIOF_IN; ++ ++ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np))) ++ continue; ++ ++ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change"); ++ gpio_export_with_name(gpio, dmc, name); ++ nb++; ++ } ++ } ++ ++ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb); ++ ++ return 0; ++} ++ ++static struct platform_driver gpio_export_driver = { ++ .driver = { ++ .name = "gpio-export", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(gpio_export_ids), ++ }, ++}; ++ ++static int __init of_gpio_export_init(void) ++{ ++ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe); ++} ++device_initcall(of_gpio_export_init); +--- a/include/asm-generic/gpio.h ++++ b/include/asm-generic/gpio.h +@@ -123,6 +123,12 @@ static inline int gpio_export(unsigned g + return gpiod_export(gpio_to_desc(gpio), direction_may_change); + } + ++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); ++static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name) ++{ ++ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name); ++} ++ + static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) + { +--- a/include/linux/gpio/consumer.h ++++ b/include/linux/gpio/consumer.h +@@ -323,6 +323,7 @@ static inline int desc_to_gpio(const str + + #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) + ++int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); + int gpiod_export(struct gpio_desc *desc, bool direction_may_change); + int gpiod_export_link(struct device *dev, const char *name, + struct gpio_desc *desc); +@@ -331,6 +332,13 @@ void gpiod_unexport(struct gpio_desc *de + + #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ + ++static inline int _gpiod_export(struct gpio_desc *desc, ++ bool direction_may_change, ++ const char *name) ++{ ++ return -ENOSYS; ++} ++ + static inline int gpiod_export(struct gpio_desc *desc, + bool direction_may_change) + { +--- a/drivers/gpio/gpiolib-sysfs.c ++++ b/drivers/gpio/gpiolib-sysfs.c +@@ -517,7 +517,7 @@ static struct class gpio_class = { + * + * Returns zero on success, else an error. + */ +-int gpiod_export(struct gpio_desc *desc, bool direction_may_change) ++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) + { + struct gpio_chip *chip; + unsigned long flags; +@@ -566,6 +566,8 @@ int gpiod_export(struct gpio_desc *desc, + offset = gpio_chip_hwgpio(desc); + if (desc->chip->names && desc->chip->names[offset]) + ioname = desc->chip->names[offset]; ++ if (name) ++ ioname = name; + + dev = device_create_with_groups(&gpio_class, desc->chip->dev, + MKDEV(0, 0), desc, gpio_groups, +@@ -602,6 +604,12 @@ fail_unlock: + gpiod_dbg(desc, "%s: status %d\n", __func__, status); + return status; + } ++EXPORT_SYMBOL_GPL(__gpiod_export); ++ ++int gpiod_export(struct gpio_desc *desc, bool direction_may_change) ++{ ++ return __gpiod_export(desc, direction_may_change, NULL); ++} + EXPORT_SYMBOL_GPL(gpiod_export); + + static int match_export(struct device *dev, const void *data) diff --git a/target/linux/lantiq/patches-3.18/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-3.18/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch new file mode 100644 index 0000000..4f655db --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch @@ -0,0 +1,1034 @@ +From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:26:42 +0200 +Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master + +This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. + +Signed-off-by: Thomas Langer +Signed-off-by: John Crispin +--- + drivers/i2c/busses/Kconfig | 10 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ + drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ + 4 files changed, 992 insertions(+) + create mode 100644 drivers/i2c/busses/i2c-lantiq.c + create mode 100644 drivers/i2c/busses/i2c-lantiq.h + +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -554,6 +554,16 @@ config I2C_KEMPLD + This driver can also be built as a module. If so, the module + will be called i2c-kempld. + ++config I2C_LANTIQ ++ tristate "Lantiq I2C interface" ++ depends on LANTIQ && SOC_FALCON ++ help ++ If you say yes to this option, support will be included for the ++ Lantiq I2C core. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-lantiq. ++ + config I2C_MPC + tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" + depends on PPC +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -53,6 +53,7 @@ obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic + obj-$(CONFIG_I2C_IMX) += i2c-imx.o + obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o + obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o ++obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o + obj-$(CONFIG_I2C_MPC) += i2c-mpc.o + obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o + obj-$(CONFIG_I2C_MXS) += i2c-mxs.o +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.c +@@ -0,0 +1,747 @@ ++ ++/* ++ * Lantiq I2C bus adapter ++ * ++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * Copyright (C) 2012 Thomas Langer ++ */ ++ ++#include ++#include ++#include ++#include /* for kzalloc, kfree */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "i2c-lantiq.h" ++ ++/* ++ * CURRENT ISSUES: ++ * - no high speed support ++ * - ten bit mode is not tested (no slave devices) ++ */ ++ ++/* access macros */ ++#define i2c_r32(reg) \ ++ __raw_readl(&(priv->membase)->reg) ++#define i2c_w32(val, reg) \ ++ __raw_writel(val, &(priv->membase)->reg) ++#define i2c_w32_mask(clear, set, reg) \ ++ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) ++ ++#define DRV_NAME "i2c-lantiq" ++#define DRV_VERSION "1.00" ++ ++#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ ++ ++#ifdef DEBUG ++#define LTQ_I2C_XFER_TIMEOUT (25*HZ) ++#else ++#define LTQ_I2C_XFER_TIMEOUT HZ ++#endif ++ ++#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ ++ I2C_IMSC_I2C_ERR_INT_EN) ++ ++#define LTQ_I2C_ARB_LOST (1 << 0) ++#define LTQ_I2C_NACK (1 << 1) ++#define LTQ_I2C_RX_UFL (1 << 2) ++#define LTQ_I2C_RX_OFL (1 << 3) ++#define LTQ_I2C_TX_UFL (1 << 4) ++#define LTQ_I2C_TX_OFL (1 << 5) ++ ++struct ltq_i2c { ++ struct mutex mutex; ++ ++ ++ /* active clock settings */ ++ unsigned int input_clock; /* clock input for i2c hardware block */ ++ unsigned int i2c_clock; /* approximated bus clock in kHz */ ++ ++ struct clk *clk_gate; ++ struct clk *clk_input; ++ ++ ++ /* resources (memory and interrupts) */ ++ int irq_lb; /* last burst irq */ ++ ++ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ ++ ++ struct i2c_adapter adap; ++ struct device *dev; ++ ++ struct completion cmd_complete; ++ ++ ++ /* message transfer data */ ++ struct i2c_msg *current_msg; /* current message */ ++ int msgs_num; /* number of messages to handle */ ++ u8 *msg_buf; /* current buffer */ ++ u32 msg_buf_len; /* remaining length of current buffer */ ++ int msg_err; /* error status of the current transfer */ ++ ++ ++ /* master status codes */ ++ enum { ++ STATUS_IDLE, ++ STATUS_ADDR, /* address phase */ ++ STATUS_WRITE, ++ STATUS_READ, ++ STATUS_READ_END, ++ STATUS_STOP ++ } status; ++}; ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); ++ ++static inline void enable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); ++} ++static inline void disable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); ++} ++ ++static void prepare_msg_send_addr(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ ++ u16 addr = msg->addr; ++ ++ /* new i2c_msg */ ++ priv->msg_buf = msg->buf; ++ priv->msg_buf_len = msg->len; ++ if (rd) ++ priv->status = STATUS_READ; ++ else ++ priv->status = STATUS_WRITE; ++ ++ /* send slave address */ ++ if (msg->flags & I2C_M_TEN) { ++ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); ++ i2c_w32(addr & 0xff, txd); ++ } else { ++ i2c_w32((addr & 0x7f) << 1 | rd, txd); ++ } ++} ++ ++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; ++ ++ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); ++ ++ priv->status = STATUS_ADDR; ++ ++ if (!(msg->flags & I2C_M_RD)) ++ len += msg->len; ++ else ++ /* set maximum received packet size (before rx int!) */ ++ i2c_w32(msg->len, mrps_ctrl); ++ i2c_w32(len, tps_ctrl); ++ enable_burst_irq(priv); ++} ++ ++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ unsigned int input_clock = clk_get_rate(priv->clk_input); ++ u32 dec, inc = 1; ++ ++ /* clock changed? */ ++ if (priv->input_clock == input_clock) ++ return 0; ++ ++ /* ++ * this formula is only an approximation, found by the recommended ++ * values in the "I2C Architecture Specification 1.7.1" ++ */ ++ dec = input_clock / (priv->i2c_clock * 2); ++ if (dec <= 6) ++ return -ENXIO; ++ ++ i2c_w32(0, fdiv_high_cfg); ++ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | ++ (dec << I2C_FDIV_CFG_DEC_OFFSET), ++ fdiv_cfg); ++ ++ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", ++ input_clock, priv->i2c_clock, dec); ++ ++ priv->input_clock = input_clock; ++ return 0; ++} ++ ++static int ltq_i2c_hw_init(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++#ifndef DEBUG ++ /* set normal operation clock divider */ ++ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); ++#else ++ /* for debugging a higher divider value! */ ++ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); ++#endif ++ ++ /* setup clock */ ++ ret = ltq_i2c_hw_set_clock(adap); ++ if (ret != 0) { ++ dev_warn(priv->dev, "invalid clock settings\n"); ++ return ret; ++ } ++ ++ /* configure fifo */ ++ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ ++ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ ++ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ ++ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ ++ fifo_cfg); ++ ++ /* configure address */ ++ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in ++ the fifo */ ++ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ ++ I2C_ADDR_CFG_MnS_EN | /* we are master device */ ++ 0, /* our slave address (not used!) */ ++ addr_cfg); ++ ++ /* enable bus */ ++ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); ++ ++ return 0; ++} ++ ++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); ++ ++ do { ++ u32 stat = i2c_r32(bus_stat); ++ ++ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(priv->dev, "timeout waiting for bus ready\n"); ++ return -ETIMEDOUT; ++} ++ ++static void ltq_i2c_tx(struct ltq_i2c *priv, int last) ++{ ++ if (priv->msg_buf_len && priv->msg_buf) { ++ i2c_w32(*priv->msg_buf, txd); ++ ++ if (--priv->msg_buf_len) ++ priv->msg_buf++; ++ else ++ priv->msg_buf = NULL; ++ } else { ++ last = 1; ++ } ++ ++ if (last) ++ disable_burst_irq(priv); ++} ++ ++static void ltq_i2c_rx(struct ltq_i2c *priv, int last) ++{ ++ u32 fifo_stat, timeout; ++ if (priv->msg_buf_len && priv->msg_buf) { ++ timeout = 5000000; ++ do { ++ fifo_stat = i2c_r32(ffs_stat); ++ } while (!fifo_stat && --timeout); ++ if (!timeout) { ++ last = 1; ++ pr_debug("\nrx timeout\n"); ++ goto err; ++ } ++ while (fifo_stat) { ++ *priv->msg_buf = i2c_r32(rxd); ++ if (--priv->msg_buf_len) { ++ priv->msg_buf++; ++ } else { ++ priv->msg_buf = NULL; ++ last = 1; ++ break; ++ } ++ /* ++ * do not read more than burst size, otherwise no "last ++ * burst" is generated and the transaction is blocked! ++ */ ++ fifo_stat = 0; ++ } ++ } else { ++ last = 1; ++ } ++err: ++ if (last) { ++ disable_burst_irq(priv); ++ ++ if (priv->status == STATUS_READ_END) { ++ /* ++ * do the STATUS_STOP and complete() here, as sometimes ++ * the tx_end is already seen before this is finished ++ */ ++ priv->status = STATUS_STOP; ++ complete(&priv->cmd_complete); ++ } else { ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++ priv->status = STATUS_READ_END; ++ } ++ } ++} ++ ++static void ltq_i2c_xfer_init(struct ltq_i2c *priv) ++{ ++ /* enable interrupts */ ++ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); ++ ++ /* trigger transfer of first msg */ ++ ltq_i2c_set_tx_len(priv); ++} ++ ++static void dump_msgs(struct i2c_msg msgs[], int num, int rx) ++{ ++#if defined(DEBUG) ++ int i, j; ++ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); ++ for (i = 0; i < num; i++) { ++ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, ++ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', ++ msgs[i].len, msgs[i].addr); ++ if (!(msgs[i].flags & I2C_M_RD) || rx) { ++ for (j = 0; j < msgs[i].len; j++) ++ pr_debug("%02X ", msgs[i].buf[j]); ++ } ++ pr_debug("\n"); ++ } ++#endif ++} ++ ++static void ltq_i2c_release_bus(struct ltq_i2c *priv) ++{ ++ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++} ++ ++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], ++ int num) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ int ret; ++ ++ dev_dbg(priv->dev, "xfer %u messages\n", num); ++ dump_msgs(msgs, num, 0); ++ ++ mutex_lock(&priv->mutex); ++ ++ init_completion(&priv->cmd_complete); ++ priv->current_msg = msgs; ++ priv->msgs_num = num; ++ priv->msg_err = 0; ++ priv->status = STATUS_IDLE; ++ ++ /* wait for the bus to become ready */ ++ ret = ltq_i2c_wait_bus_not_busy(priv); ++ if (ret) ++ goto done; ++ ++ while (priv->msgs_num) { ++ /* start the transfers */ ++ ltq_i2c_xfer_init(priv); ++ ++ /* wait for transfers to complete */ ++ ret = wait_for_completion_interruptible_timeout( ++ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); ++ if (ret == 0) { ++ dev_err(priv->dev, "controller timed out\n"); ++ ltq_i2c_hw_init(adap); ++ ret = -ETIMEDOUT; ++ goto done; ++ } else if (ret < 0) ++ goto done; ++ ++ if (priv->msg_err) { ++ if (priv->msg_err & LTQ_I2C_NACK) ++ ret = -ENXIO; ++ else ++ ret = -EREMOTEIO; ++ goto done; ++ } ++ if (--priv->msgs_num) ++ priv->current_msg++; ++ } ++ /* no error? */ ++ ret = num; ++ ++done: ++ ltq_i2c_release_bus(priv); ++ ++ mutex_unlock(&priv->mutex); ++ ++ if (ret >= 0) ++ dump_msgs(msgs, num, 1); ++ ++ pr_debug("XFER ret %d\n", ret); ++ return ret; ++} ++ ++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) ++{ ++ struct ltq_i2c *priv = dev_id; ++ struct i2c_msg *msg = priv->current_msg; ++ int last = (irq == priv->irq_lb); ++ ++ if (last) ++ pr_debug("LB "); ++ else ++ pr_debug("B "); ++ ++ if (msg->flags & I2C_M_RD) { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("X"); ++ prepare_msg_send_addr(priv); ++ disable_burst_irq(priv); ++ break; ++ case STATUS_READ: ++ case STATUS_READ_END: ++ pr_debug("R"); ++ ltq_i2c_rx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status R %d\n", priv->status); ++ break; ++ } ++ } else { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("x"); ++ prepare_msg_send_addr(priv); ++ break; ++ case STATUS_WRITE: ++ pr_debug("w"); ++ ltq_i2c_tx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status W %d\n", priv->status); ++ break; ++ } ++ } ++ ++ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); ++ return IRQ_HANDLED; ++} ++ ++static void ltq_i2c_isr_prot(struct ltq_i2c *priv) ++{ ++ u32 i_pro = i2c_r32(p_irqss); ++ ++ pr_debug("i2c-p"); ++ ++ /* not acknowledge */ ++ if (i_pro & I2C_P_IRQSS_NACK) { ++ priv->msg_err |= LTQ_I2C_NACK; ++ pr_debug(" nack"); ++ } ++ ++ /* arbitration lost */ ++ if (i_pro & I2C_P_IRQSS_AL) { ++ priv->msg_err |= LTQ_I2C_ARB_LOST; ++ pr_debug(" arb-lost"); ++ } ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) ++ pr_debug(" rx"); ++ ++ /* tx end */ ++ if (i_pro & I2C_P_IRQSS_TX_END) ++ pr_debug(" txend"); ++ pr_debug("\n"); ++ ++ if (!priv->msg_err) { ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) { ++ priv->status = STATUS_READ; ++ enable_burst_irq(priv); ++ } ++ if (i_pro & I2C_P_IRQSS_TX_END) { ++ if (priv->status == STATUS_READ) ++ priv->status = STATUS_READ_END; ++ else { ++ disable_burst_irq(priv); ++ priv->status = STATUS_STOP; ++ } ++ } ++ } ++ ++ i2c_w32(i_pro, p_irqsc); ++} ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) ++{ ++ u32 i_raw, i_err = 0; ++ struct ltq_i2c *priv = dev_id; ++ ++ i_raw = i2c_r32(mis); ++ pr_debug("i_raw 0x%08X\n", i_raw); ++ ++ /* error interrupt */ ++ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { ++ i_err = i2c_r32(err_irqss); ++ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", ++ i_err, i2c_r32(bus_stat)); ++ ++ /* tx fifo overflow (8) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_OFL) ++ priv->msg_err |= LTQ_I2C_TX_OFL; ++ ++ /* tx fifo underflow (4) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_UFL) ++ priv->msg_err |= LTQ_I2C_TX_UFL; ++ ++ /* rx fifo overflow (2) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_OFL) ++ priv->msg_err |= LTQ_I2C_RX_OFL; ++ ++ /* rx fifo underflow (1) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_UFL) ++ priv->msg_err |= LTQ_I2C_RX_UFL; ++ ++ i2c_w32(i_err, err_irqsc); ++ } ++ ++ /* protocol interrupt */ ++ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) ++ ltq_i2c_isr_prot(priv); ++ ++ if ((priv->msg_err) || (priv->status == STATUS_STOP)) ++ complete(&priv->cmd_complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 ltq_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | ++ I2C_FUNC_10BIT_ADDR | ++ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm ltq_i2c_algorithm = { ++ .master_xfer = ltq_i2c_xfer, ++ .functionality = ltq_i2c_functionality, ++}; ++ ++static int __devinit ltq_i2c_probe(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct ltq_i2c *priv; ++ struct i2c_adapter *adap; ++ struct resource *mmres, irqres[4]; ++ int ret = 0; ++ ++ dev_dbg(&pdev->dev, "probing\n"); ++ ++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ret = of_irq_to_resource_table(node, irqres, 4); ++ if (!mmres || (ret != 4)) { ++ dev_err(&pdev->dev, "no resources\n"); ++ return -ENODEV; ++ } ++ ++ /* allocate private data */ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(&pdev->dev, "can't allocate private data\n"); ++ return -ENOMEM; ++ } ++ ++ adap = &priv->adap; ++ i2c_set_adapdata(adap, priv); ++ adap->owner = THIS_MODULE; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); ++ adap->algo = <q_i2c_algorithm; ++ ++ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { ++ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); ++ priv->i2c_clock = 100000; ++ } ++ ++ init_completion(&priv->cmd_complete); ++ mutex_init(&priv->mutex); ++ ++ priv->membase = devm_request_and_ioremap(&pdev->dev, mmres); ++ if (priv->membase == NULL) ++ return -ENOMEM; ++ ++ priv->dev = &pdev->dev; ++ priv->irq_lb = irqres[0].start; ++ ++ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, ++ IRQF_DISABLED, "i2c lb", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", ++ irqres[0].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, ++ IRQF_DISABLED, "i2c b", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get burst IRQ %d\n", ++ irqres[1].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, ++ IRQF_DISABLED, "i2c err", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get error IRQ %d\n", ++ irqres[2].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, ++ IRQF_DISABLED, "i2c p", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", ++ irqres[3].start); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); ++ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, ++ irqres[1].start, irqres[2].start, irqres[3].start); ++ ++ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_gate)) { ++ dev_err(&pdev->dev, "failed to get i2c clk\n"); ++ return -ENOENT; ++ } ++ ++ /* this is a static clock, which has no refcounting */ ++ priv->clk_input = clk_get_fpi(); ++ if (IS_ERR(priv->clk_input)) { ++ dev_err(&pdev->dev, "failed to get fpi clk\n"); ++ return -ENOENT; ++ } ++ ++ clk_activate(priv->clk_gate); ++ ++ /* add our adapter to the i2c stack */ ++ ret = i2c_add_numbered_adapter(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't register I2C adapter\n"); ++ goto out; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ i2c_set_adapdata(adap, priv); ++ ++ /* print module version information */ ++ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", ++ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, ++ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); ++ ++ /* initialize HW */ ++ ret = ltq_i2c_hw_init(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't configure adapter\n"); ++ i2c_del_adapter(adap); ++ platform_set_drvdata(pdev, NULL); ++ } else { ++ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); ++ } ++ ++ of_i2c_register_devices(adap); ++ ++out: ++ /* if init failed, we need to deactivate the clock gate */ ++ if (ret) ++ clk_deactivate(priv->clk_gate); ++ ++ return ret; ++} ++ ++static int __devexit ltq_i2c_remove(struct platform_device *pdev) ++{ ++ struct ltq_i2c *priv = platform_get_drvdata(pdev); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++ /* power down the core */ ++ clk_deactivate(priv->clk_gate); ++ ++ /* remove driver */ ++ i2c_del_adapter(&priv->adap); ++ kfree(priv); ++ ++ dev_dbg(&pdev->dev, "removed\n"); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++static const struct of_device_id ltq_i2c_match[] = { ++ { .compatible = "lantiq,lantiq-i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_i2c_match); ++ ++static struct platform_driver ltq_i2c_driver = { ++ .probe = ltq_i2c_probe, ++ .remove = __devexit_p(ltq_i2c_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = ltq_i2c_match, ++ }, ++}; ++ ++module_platform_driver(ltq_i2c_driver); ++ ++MODULE_DESCRIPTION("Lantiq I2C bus adapter"); ++MODULE_AUTHOR("Thomas Langer "); ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.h +@@ -0,0 +1,234 @@ ++#ifndef I2C_LANTIQ_H ++#define I2C_LANTIQ_H ++ ++/* I2C register structure */ ++struct lantiq_reg_i2c { ++ /* I2C Kernel Clock Control Register */ ++ unsigned int clc; /* 0x00000000 */ ++ /* Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /* I2C Identification Register */ ++ unsigned int id; /* 0x00000008 */ ++ /* Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /* ++ * I2C RUN Control Register ++ * This register enables and disables the I2C peripheral. Before ++ * enabling, the I2C has to be configured properly. After enabling ++ * no configuration is possible ++ */ ++ unsigned int run_ctrl; /* 0x00000010 */ ++ /* ++ * I2C End Data Control Register ++ * This register is used to either turn around the data transmission ++ * direction or to address another slave without sending a stop ++ * condition. Also the software can stop the slave-transmitter by ++ * sending a not-accolade when working as master-receiver or even ++ * stop data transmission immediately when operating as ++ * master-transmitter. The writing to the bits of this control ++ * register is only effective when in MASTER RECEIVES BYTES, MASTER ++ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state ++ */ ++ unsigned int endd_ctrl; /* 0x00000014 */ ++ /* ++ * I2C Fractional Divider Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_HIGH_CFG has ++ * the same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_cfg; /* 0x00000018 */ ++ /* ++ * I2C Fractional Divider (highspeed mode) Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_CFG has the ++ * same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_high_cfg; /* 0x0000001C */ ++ /* I2C Address Configuration Register */ ++ unsigned int addr_cfg; /* 0x00000020 */ ++ /* I2C Bus Status Register ++ * This register gives a status information of the I2C. This additional ++ * information can be used by the software to start proper actions. ++ */ ++ unsigned int bus_stat; /* 0x00000024 */ ++ /* I2C FIFO Configuration Register */ ++ unsigned int fifo_cfg; /* 0x00000028 */ ++ /* I2C Maximum Received Packet Size Register */ ++ unsigned int mrps_ctrl; /* 0x0000002C */ ++ /* I2C Received Packet Size Status Register */ ++ unsigned int rps_stat; /* 0x00000030 */ ++ /* I2C Transmit Packet Size Register */ ++ unsigned int tps_ctrl; /* 0x00000034 */ ++ /* I2C Filled FIFO Stages Status Register */ ++ unsigned int ffs_stat; /* 0x00000038 */ ++ /* Reserved */ ++ unsigned int res_2; /* 0x0000003C */ ++ /* I2C Timing Configuration Register */ ++ unsigned int tim_cfg; /* 0x00000040 */ ++ /* Reserved */ ++ unsigned int res_3[7]; /* 0x00000044 */ ++ /* I2C Error Interrupt Request Source Mask Register */ ++ unsigned int err_irqsm; /* 0x00000060 */ ++ /* I2C Error Interrupt Request Source Status Register */ ++ unsigned int err_irqss; /* 0x00000064 */ ++ /* I2C Error Interrupt Request Source Clear Register */ ++ unsigned int err_irqsc; /* 0x00000068 */ ++ /* Reserved */ ++ unsigned int res_4; /* 0x0000006C */ ++ /* I2C Protocol Interrupt Request Source Mask Register */ ++ unsigned int p_irqsm; /* 0x00000070 */ ++ /* I2C Protocol Interrupt Request Source Status Register */ ++ unsigned int p_irqss; /* 0x00000074 */ ++ /* I2C Protocol Interrupt Request Source Clear Register */ ++ unsigned int p_irqsc; /* 0x00000078 */ ++ /* Reserved */ ++ unsigned int res_5; /* 0x0000007C */ ++ /* I2C Raw Interrupt Status Register */ ++ unsigned int ris; /* 0x00000080 */ ++ /* I2C Interrupt Mask Control Register */ ++ unsigned int imsc; /* 0x00000084 */ ++ /* I2C Masked Interrupt Status Register */ ++ unsigned int mis; /* 0x00000088 */ ++ /* I2C Interrupt Clear Register */ ++ unsigned int icr; /* 0x0000008C */ ++ /* I2C Interrupt Set Register */ ++ unsigned int isr; /* 0x00000090 */ ++ /* I2C DMA Enable Register */ ++ unsigned int dmae; /* 0x00000094 */ ++ /* Reserved */ ++ unsigned int res_6[8154]; /* 0x00000098 */ ++ /* I2C Transmit Data Register */ ++ unsigned int txd; /* 0x00008000 */ ++ /* Reserved */ ++ unsigned int res_7[4095]; /* 0x00008004 */ ++ /* I2C Receive Data Register */ ++ unsigned int rxd; /* 0x0000C000 */ ++ /* Reserved */ ++ unsigned int res_8[4095]; /* 0x0000C004 */ ++}; ++ ++/* ++ * Clock Divider for Normal Run Mode ++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long ++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx ++ * on reading. ++ */ ++#define I2C_CLC_RMC_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_CLC_RMC_OFFSET 8 ++ ++/* Fields of "I2C Identification Register" */ ++/* Module ID */ ++#define I2C_ID_ID_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_ID_ID_OFFSET 8 ++/* Revision */ ++#define I2C_ID_REV_MASK 0x000000FF ++/* field offset */ ++#define I2C_ID_REV_OFFSET 0 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_BREQ_INT_EN 0x00000008 ++/* Enable */ ++#define I2C_IMSC_LBREQ_INT_EN 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_INC_OFFSET 16 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_I2C_P_INT_EN 0x00000020 ++/* Enable */ ++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 ++ ++/* Fields of "I2C Error Interrupt Request Source Status Register" */ ++/* TXF_OFL */ ++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 ++/* TXF_UFL */ ++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 ++/* RXF_OFL */ ++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 ++/* RXF_UFL */ ++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 ++ ++/* Fields of "I2C Raw Interrupt Status Register" */ ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* TX FIFO Flow Control */ ++#define I2C_FIFO_CFG_TXFC 0x00020000 ++/* RX FIFO Flow Control */ ++#define I2C_FIFO_CFG_RXFC 0x00010000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 ++/* 1 word */ ++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* 1 word */ ++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 ++/* Stop on Packet End Enable */ ++#define I2C_ADDR_CFG_SOPE_EN 0x00200000 ++/* Stop on Not Acknowledge Enable */ ++#define I2C_ADDR_CFG_SONA_EN 0x00100000 ++/* Enable */ ++#define I2C_ADDR_CFG_MnS_EN 0x00080000 ++ ++/* Fields of "I2C Interrupt Clear Register" */ ++/* Clear */ ++#define I2C_ICR_BREQ_INT_CLR 0x00000008 ++/* Clear */ ++#define I2C_ICR_LBREQ_INT_CLR 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Bus Status Register" */ ++/* Bus Status */ ++#define I2C_BUS_STAT_BS_MASK 0x00000003 ++/* Read from I2C Bus. */ ++#define I2C_BUS_STAT_RNW_READ 0x00000004 ++/* I2C Bus is free. */ ++#define I2C_BUS_STAT_BS_FREE 0x00000000 ++/* ++ * The device is working as master and has claimed the control on the ++ * I2C-bus (busy master). ++ */ ++#define I2C_BUS_STAT_BS_BM 0x00000002 ++ ++/* Fields of "I2C RUN Control Register" */ ++/* Enable */ ++#define I2C_RUN_CTRL_RUN_EN 0x00000001 ++ ++/* Fields of "I2C End Data Control Register" */ ++/* ++ * Set End of Transmission ++ * Note:Do not write '1' to this bit when bus is free. This will cause an ++ * abort after the first byte when a new transfer is started. ++ */ ++#define I2C_ENDD_CTRL_SETEND 0x00000002 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ ++/* NACK */ ++#define I2C_P_IRQSS_NACK 0x00000010 ++/* AL */ ++#define I2C_P_IRQSS_AL 0x00000008 ++/* RX */ ++#define I2C_P_IRQSS_RX 0x00000040 ++/* TX_END */ ++#define I2C_P_IRQSS_TX_END 0x00000020 ++ ++ ++#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-3.18/0032-USB-fix-roothub-for-IFXHCD.patch b/target/linux/lantiq/patches-3.18/0032-USB-fix-roothub-for-IFXHCD.patch new file mode 100644 index 0000000..cf2c5cb --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0032-USB-fix-roothub-for-IFXHCD.patch @@ -0,0 +1,31 @@ +From 326714a47233e4a524afa0c8398276fddf0dbd4d Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 6 Dec 2012 19:59:53 +0100 +Subject: [PATCH 32/36] USB: fix roothub for IFXHCD + +--- + arch/mips/lantiq/Kconfig | 1 + + drivers/usb/core/hub.c | 2 +- + 2 files changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -3,6 +3,7 @@ if LANTIQ + config SOC_TYPE_XWAY + bool + select PINCTRL_XWAY ++ select USB_ARCH_HAS_HCD + default n + + choice +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -4303,7 +4303,7 @@ hub_port_init (struct usb_hub *hub, stru + udev->ttport = hdev->ttport; + } else if (udev->speed != USB_SPEED_HIGH + && hdev->speed == USB_SPEED_HIGH) { +- if (!hub->tt.hub) { ++ if (hdev->parent && !hub->tt.hub) { + dev_err(&udev->dev, "parent hub has no TT\n"); + retval = -EINVAL; + goto fail; diff --git a/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch b/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch new file mode 100644 index 0000000..81e5d39 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch @@ -0,0 +1,1022 @@ +From e75df4f96373e5d16f8ca13aa031e54cdcfeda62 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 13 Mar 2013 09:29:37 +0100 +Subject: [PATCH 33/36] SPI: MIPS: lantiq: adds spi-xway + +This patch adds support for the SPI core found on several Lantiq SoCs. +The Driver has been runtime tested in combination with m25p80 Flash Devices +on Amazon_SE and VR9. + +Signed-off-by: Daniel Schwierzeck +Signed-off-by: John Crispin +--- + drivers/spi/Kconfig | 8 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-xway.c | 977 ++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 986 insertions(+) + create mode 100644 drivers/spi/spi-xway.c + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -597,6 +597,14 @@ config SPI_NUC900 + help + SPI driver for Nuvoton NUC900 series ARM SoCs + ++config SPI_XWAY ++ tristate "Lantiq XWAY SPI controller" ++ depends on LANTIQ && SOC_TYPE_XWAY ++ select SPI_BITBANG ++ help ++ This driver supports the Lantiq SoC SPI controller in master ++ mode. ++ + # + # Add new SPI master controllers in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -86,3 +86,4 @@ obj-$(CONFIG_SPI_TXX9) += spi-txx9.o + obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o + obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o ++obj-$(CONFIG_SPI_XWAY) += spi-xway.o +--- /dev/null ++++ b/drivers/spi/spi-xway.c +@@ -0,0 +1,977 @@ ++/* ++ * Lantiq SoC SPI controller ++ * ++ * Copyright (C) 2011 Daniel Schwierzeck ++ * Copyright (C) 2012 John Crispin ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define LTQ_SPI_CLC 0x00 /* Clock control */ ++#define LTQ_SPI_PISEL 0x04 /* Port input select */ ++#define LTQ_SPI_ID 0x08 /* Identification */ ++#define LTQ_SPI_CON 0x10 /* Control */ ++#define LTQ_SPI_STAT 0x14 /* Status */ ++#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */ ++#define LTQ_SPI_TB 0x20 /* Transmit buffer */ ++#define LTQ_SPI_RB 0x24 /* Receive buffer */ ++#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */ ++#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */ ++#define LTQ_SPI_FSTAT 0x38 /* FIFO status */ ++#define LTQ_SPI_BRT 0x40 /* Baudrate timer */ ++#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */ ++#define LTQ_SPI_SFCON 0x60 /* Serial frame control */ ++#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */ ++#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */ ++#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */ ++#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */ ++#define LTQ_SPI_RXREQ 0x80 /* Receive request */ ++#define LTQ_SPI_RXCNT 0x84 /* Receive count */ ++#define LTQ_SPI_DMACON 0xEC /* DMA control */ ++#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */ ++#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */ ++#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */ ++ ++#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */ ++#define LTQ_SPI_CLC_SMC_MASK 0xFF ++#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */ ++#define LTQ_SPI_CLC_RMC_MASK 0xFF ++#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ ++#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ ++ ++#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */ ++#define LTQ_SPI_ID_TXFS_MASK 0x3F ++#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */ ++#define LTQ_SPI_ID_RXFS_MASK 0x3F ++#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */ ++#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */ ++ ++#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */ ++#define LTQ_SPI_CON_BM_MASK 0x1F ++#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ ++#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ ++#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ ++#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ ++#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ ++#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ ++#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ ++#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ ++#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ ++#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ ++#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ ++#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ ++#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ ++#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ ++ ++#define LTQ_SPI_STAT_RXBV_MASK 0x7 ++#define LTQ_SPI_STAT_RXBV_SHIFT 28 ++#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ ++#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ ++#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ ++#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ ++#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ ++#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ ++#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ ++#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ ++ ++#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ ++#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ ++#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ ++#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ ++#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error ++ flag */ ++#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ ++#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ ++#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ ++#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ ++#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ ++#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ ++#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ ++#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ ++#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ ++#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ ++#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ ++#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50 ++ ++#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */ ++#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F ++#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ ++#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ ++ ++#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */ ++#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F ++#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ ++#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ ++ ++#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f ++#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0 ++#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f ++#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8 ++ ++#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8 ++#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0 ++ ++#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8 ++#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0 ++ ++#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */ ++#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */ ++ ++#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ ++#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ ++#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */ ++#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */ ++#define LTQ_SPI_IRNEN_ALL 0xF ++ ++struct ltq_spi { ++ struct spi_bitbang bitbang; ++ struct completion done; ++ spinlock_t lock; ++ ++ struct device *dev; ++ void __iomem *base; ++ struct clk *fpiclk; ++ struct clk *spiclk; ++ ++ int status; ++ int irq[3]; ++ ++ const u8 *tx; ++ u8 *rx; ++ u32 tx_cnt; ++ u32 rx_cnt; ++ u32 len; ++ struct spi_transfer *curr_transfer; ++ ++ u32 (*get_tx) (struct ltq_spi *); ++ ++ u16 txfs; ++ u16 rxfs; ++ unsigned dma_support:1; ++ unsigned cfg_mode:1; ++}; ++ ++static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} ++ ++static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg) ++{ ++ return ioread32be(hw->base + reg); ++} ++ ++static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg) ++{ ++ iowrite32be(val, hw->base + reg); ++} ++ ++static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg) ++{ ++ u32 val; ++ ++ val = ltq_spi_reg_read(hw, reg); ++ val |= bits; ++ ltq_spi_reg_write(hw, val, reg); ++} ++ ++static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg) ++{ ++ u32 val; ++ ++ val = ltq_spi_reg_read(hw, reg); ++ val &= ~bits; ++ ltq_spi_reg_write(hw, val, reg); ++} ++ ++static void ltq_spi_hw_enable(struct ltq_spi *hw) ++{ ++ u32 clc; ++ ++ /* Power-up module */ ++ clk_enable(hw->spiclk); ++ ++ /* ++ * Set clock divider for run mode to 1 to ++ * run at same frequency as FPI bus ++ */ ++ clc = (1 << LTQ_SPI_CLC_RMC_SHIFT); ++ ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC); ++} ++ ++static void ltq_spi_hw_disable(struct ltq_spi *hw) ++{ ++ /* Set clock divider to 0 and set module disable bit */ ++ ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC); ++ ++ /* Power-down module */ ++ clk_disable(hw->spiclk); ++} ++ ++static void ltq_spi_reset_fifos(struct ltq_spi *hw) ++{ ++ u32 val; ++ ++ /* ++ * Enable and flush FIFOs. Set interrupt trigger level to ++ * half of FIFO count implemented in hardware. ++ */ ++ if (hw->txfs > 1) { ++ val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1); ++ val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; ++ ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON); ++ } ++ ++ if (hw->rxfs > 1) { ++ val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1); ++ val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; ++ ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON); ++ } ++} ++ ++static inline int ltq_spi_wait_ready(struct ltq_spi *hw) ++{ ++ u32 stat; ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(200); ++ ++ do { ++ stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT); ++ if (!(stat & LTQ_SPI_STAT_BSY)) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat); ++ ++ return -ETIMEDOUT; ++} ++ ++static void ltq_spi_config_mode_set(struct ltq_spi *hw) ++{ ++ if (hw->cfg_mode) ++ return; ++ ++ /* ++ * Putting the SPI module in config mode is only safe if no ++ * transfer is in progress as indicated by busy flag STATE.BSY. ++ */ ++ if (ltq_spi_wait_ready(hw)) { ++ ltq_spi_reset_fifos(hw); ++ hw->status = -ETIMEDOUT; ++ } ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); ++ ++ hw->cfg_mode = 1; ++} ++ ++static void ltq_spi_run_mode_set(struct ltq_spi *hw) ++{ ++ if (!hw->cfg_mode) ++ return; ++ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); ++ ++ hw->cfg_mode = 0; ++} ++ ++static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw) ++{ ++ const u8 *tx = hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt++; ++ hw->tx++; ++ ++ return data; ++} ++ ++static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw) ++{ ++ const u16 *tx = (u16 *) hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt += 2; ++ hw->tx += 2; ++ ++ return data; ++} ++ ++static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw) ++{ ++ const u32 *tx = (u32 *) hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt += 4; ++ hw->tx += 4; ++ ++ return data; ++} ++ ++static void ltq_spi_bits_per_word_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 bm; ++ u8 bits_per_word = spi->bits_per_word; ++ ++ /* ++ * Use either default value of SPI device or value ++ * from current transfer. ++ */ ++ if (hw->curr_transfer && hw->curr_transfer->bits_per_word) ++ bits_per_word = hw->curr_transfer->bits_per_word; ++ ++ if (bits_per_word <= 8) ++ hw->get_tx = ltq_spi_tx_word_u8; ++ else if (bits_per_word <= 16) ++ hw->get_tx = ltq_spi_tx_word_u16; ++ else if (bits_per_word <= 32) ++ hw->get_tx = ltq_spi_tx_word_u32; ++ ++ /* CON.BM value = bits_per_word - 1 */ ++ bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT; ++ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK << ++ LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON); ++ ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_speed_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 br, max_speed_hz, spi_clk; ++ u32 speed_hz = spi->max_speed_hz; ++ ++ /* ++ * Use either default value of SPI device or value ++ * from current transfer. ++ */ ++ if (hw->curr_transfer && hw->curr_transfer->speed_hz) ++ speed_hz = hw->curr_transfer->speed_hz; ++ ++ /* ++ * SPI module clock is derived from FPI bus clock dependent on ++ * divider value in CLC.RMS which is always set to 1. ++ */ ++ spi_clk = clk_get_rate(hw->fpiclk); ++ ++ /* ++ * Maximum SPI clock frequency in master mode is half of ++ * SPI module clock frequency. Maximum reload value of ++ * baudrate generator BR is 2^16. ++ */ ++ max_speed_hz = spi_clk / 2; ++ if (speed_hz >= max_speed_hz) ++ br = 0; ++ else ++ br = (max_speed_hz / speed_hz) - 1; ++ ++ if (br > 0xFFFF) ++ br = 0xFFFF; ++ ++ ltq_spi_reg_write(hw, br, LTQ_SPI_BRT); ++} ++ ++static void ltq_spi_clockmode_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 con; ++ ++ con = ltq_spi_reg_read(hw, LTQ_SPI_CON); ++ ++ /* ++ * SPI mode mapping in CON register: ++ * Mode CPOL CPHA CON.PO CON.PH ++ * 0 0 0 0 1 ++ * 1 0 1 0 0 ++ * 2 1 0 1 1 ++ * 3 1 1 1 0 ++ */ ++ if (spi->mode & SPI_CPHA) ++ con &= ~LTQ_SPI_CON_PH; ++ else ++ con |= LTQ_SPI_CON_PH; ++ ++ if (spi->mode & SPI_CPOL) ++ con |= LTQ_SPI_CON_PO; ++ else ++ con &= ~LTQ_SPI_CON_PO; ++ ++ /* Set heading control */ ++ if (spi->mode & SPI_LSB_FIRST) ++ con &= ~LTQ_SPI_CON_HB; ++ else ++ con |= LTQ_SPI_CON_HB; ++ ++ ltq_spi_reg_write(hw, con, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t) ++{ ++ u32 con; ++ ++ con = ltq_spi_reg_read(hw, LTQ_SPI_CON); ++ ++ if (t) { ++ if (t->tx_buf && t->rx_buf) { ++ con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); ++ } else if (t->rx_buf) { ++ con &= ~LTQ_SPI_CON_RXOFF; ++ con |= LTQ_SPI_CON_TXOFF; ++ } else if (t->tx_buf) { ++ con &= ~LTQ_SPI_CON_TXOFF; ++ con |= LTQ_SPI_CON_RXOFF; ++ } ++ } else ++ con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); ++ ++ ltq_spi_reg_write(hw, con, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_internal_cs_activate(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 fgpo; ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT)); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++} ++ ++static void ltq_spi_internal_cs_deactivate(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 fgpo; ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++} ++ ++static void ltq_spi_chipselect(struct spi_device *spi, int cs) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ ++ switch (cs) { ++ case BITBANG_CS_ACTIVE: ++ ltq_spi_bits_per_word_set(spi); ++ ltq_spi_speed_set(spi); ++ ltq_spi_clockmode_set(spi); ++ ltq_spi_run_mode_set(hw); ++ ltq_spi_internal_cs_activate(spi); ++ break; ++ ++ case BITBANG_CS_INACTIVE: ++ ltq_spi_internal_cs_deactivate(spi); ++ ltq_spi_config_mode_set(hw); ++ break; ++ } ++} ++ ++static int ltq_spi_setup_transfer(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u8 bits_per_word = spi->bits_per_word; ++ ++ hw->curr_transfer = t; ++ ++ if (t && t->bits_per_word) ++ bits_per_word = t->bits_per_word; ++ ++ if (bits_per_word > 32) ++ return -EINVAL; ++ ++ ltq_spi_config_mode_set(hw); ++ ++ return 0; ++} ++ ++static int ltq_spi_setup(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 gpocon, fgpo; ++ ++ /* Set default word length to 8 if not set */ ++ if (!spi->bits_per_word) ++ spi->bits_per_word = 8; ++ ++ if (spi->bits_per_word > 32) ++ return -EINVAL; ++ ++ /* ++ * Up to six GPIOs can be connected to the SPI module ++ * via GPIO alternate function to control the chip select lines. ++ */ ++ gpocon = (1 << (spi->chip_select + ++ LTQ_SPI_GPOCON_ISCSBN_SHIFT)); ++ ++ if (spi->mode & SPI_CS_HIGH) ++ gpocon |= (1 << spi->chip_select); ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); ++ ++ ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++ ++ return 0; ++} ++ ++static void ltq_spi_cleanup(struct spi_device *spi) ++{ ++ ++} ++ ++static void ltq_spi_txfifo_write(struct ltq_spi *hw) ++{ ++ u32 fstat, data; ++ u16 fifo_space; ++ ++ /* Determine how much FIFOs are free for TX data */ ++ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); ++ fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) & ++ LTQ_SPI_FSTAT_TXFFL_MASK); ++ ++ if (!fifo_space) ++ return; ++ ++ while (hw->tx_cnt < hw->len && fifo_space) { ++ data = hw->get_tx(hw); ++ ltq_spi_reg_write(hw, data, LTQ_SPI_TB); ++ fifo_space--; ++ } ++} ++ ++static void ltq_spi_rxfifo_read(struct ltq_spi *hw) ++{ ++ u32 fstat, data, *rx32; ++ u16 fifo_fill; ++ u8 rxbv, shift, *rx8; ++ ++ /* Determine how much FIFOs are filled with RX data */ ++ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); ++ fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT) ++ & LTQ_SPI_FSTAT_RXFFL_MASK); ++ ++ if (!fifo_fill) ++ return; ++ ++ /* ++ * The 32 bit FIFO is always used completely independent from the ++ * bits_per_word value. Thus four bytes have to be read at once ++ * per FIFO. ++ */ ++ rx32 = (u32 *) hw->rx; ++ while (hw->len - hw->rx_cnt >= 4 && fifo_fill) { ++ *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB); ++ hw->rx_cnt += 4; ++ hw->rx += 4; ++ fifo_fill--; ++ } ++ ++ /* ++ * If there are remaining bytes, read byte count from STAT.RXBV ++ * register and read the data byte-wise. ++ */ ++ while (fifo_fill && hw->rx_cnt < hw->len) { ++ rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >> ++ LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK; ++ data = ltq_spi_reg_read(hw, LTQ_SPI_RB); ++ ++ shift = (rxbv - 1) * 8; ++ rx8 = hw->rx; ++ ++ while (rxbv) { ++ *rx8++ = (data >> shift) & 0xFF; ++ rxbv--; ++ shift -= 8; ++ hw->rx_cnt++; ++ hw->rx++; ++ } ++ ++ fifo_fill--; ++ } ++} ++ ++static void ltq_spi_rxreq_set(struct ltq_spi *hw) ++{ ++ u32 rxreq, rxreq_max, rxtodo; ++ ++ rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK; ++ ++ /* ++ * In RX-only mode the serial clock is activated only after writing ++ * the expected amount of RX bytes into RXREQ register. ++ * To avoid receive overflows at high clocks it is better to request ++ * only the amount of bytes that fits into all FIFOs. This value ++ * depends on the FIFO size implemented in hardware. ++ */ ++ rxreq = hw->len - hw->rx_cnt; ++ rxreq_max = hw->rxfs << 2; ++ rxreq = min(rxreq_max, rxreq); ++ ++ if (!rxtodo && rxreq) ++ ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ); ++} ++ ++static inline void ltq_spi_complete(struct ltq_spi *hw) ++{ ++ complete(&hw->done); ++} ++ ++irqreturn_t ltq_spi_tx_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ int completed = 0; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ if (hw->tx_cnt < hw->len) ++ ltq_spi_txfifo_write(hw); ++ ++ if (hw->tx_cnt == hw->len) ++ completed = 1; ++ ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ if (completed) ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ltq_spi_rx_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ int completed = 0; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ if (hw->rx_cnt < hw->len) { ++ ltq_spi_rxfifo_read(hw); ++ ++ if (hw->tx && hw->tx_cnt < hw->len) ++ ltq_spi_txfifo_write(hw); ++ } ++ ++ if (hw->rx_cnt == hw->len) ++ completed = 1; ++ else if (!hw->tx) ++ ltq_spi_rxreq_set(hw); ++ ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ if (completed) ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ltq_spi_err_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ /* Disable all interrupts */ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); ++ ++ dev_err(hw->dev, "error %x\n", ltq_spi_reg_read(hw, LTQ_SPI_STAT)); ++ ++ /* Clear all error flags */ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); ++ ++ /* Flush FIFOs */ ++ ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); ++ ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); ++ ++ hw->status = -EIO; ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 irq_flags = 0; ++ ++ hw->tx = t->tx_buf; ++ hw->rx = t->rx_buf; ++ hw->len = t->len; ++ hw->tx_cnt = 0; ++ hw->rx_cnt = 0; ++ hw->status = 0; ++ init_completion(&hw->done); ++ ++ ltq_spi_xmit_set(hw, t); ++ ++ /* Enable error interrupts */ ++ ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); ++ ++ if (hw->tx) { ++ /* Initially fill TX FIFO with as much data as possible */ ++ ltq_spi_txfifo_write(hw); ++ irq_flags |= LTQ_SPI_IRNEN_T; ++ ++ /* Always enable RX interrupt in Full Duplex mode */ ++ if (hw->rx) ++ irq_flags |= LTQ_SPI_IRNEN_R; ++ } else if (hw->rx) { ++ /* Start RX clock */ ++ ltq_spi_rxreq_set(hw); ++ ++ /* Enable RX interrupt to receive data from RX FIFOs */ ++ irq_flags |= LTQ_SPI_IRNEN_R; ++ } ++ ++ /* Enable TX or RX interrupts */ ++ ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN); ++ wait_for_completion_interruptible(&hw->done); ++ ++ /* Disable all interrupts */ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); ++ ++ /* ++ * Return length of current transfer for bitbang utility code if ++ * no errors occured during transmission. ++ */ ++ if (!hw->status) ++ hw->status = hw->len; ++ ++ return hw->status; ++} ++ ++static const struct ltq_spi_irq_map { ++ char *name; ++ irq_handler_t handler; ++} ltq_spi_irqs[] = { ++ { "spi_rx", ltq_spi_rx_irq }, ++ { "spi_tx", ltq_spi_tx_irq }, ++ { "spi_err", ltq_spi_err_irq }, ++}; ++ ++static int ltq_spi_probe(struct platform_device *pdev) ++{ ++ struct resource irqres[3]; ++ struct spi_master *master; ++ struct resource *r; ++ struct ltq_spi *hw; ++ int ret, i; ++ u32 data, id; ++ ++ if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 3) != 3) { ++ dev_err(&pdev->dev, "IRQ settings missing in device tree\n"); ++ return -EINVAL; ++ } ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi)); ++ if (!master) { ++ dev_err(&pdev->dev, "spi_alloc_master\n"); ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ hw = spi_master_get_devdata(master); ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ dev_err(&pdev->dev, "platform_get_resource\n"); ++ ret = -ENOENT; ++ goto err_master; ++ } ++ ++ r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r), ++ pdev->name); ++ if (!r) { ++ dev_err(&pdev->dev, "failed to request memory region\n"); ++ ret = -ENXIO; ++ goto err_master; ++ } ++ ++ hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r)); ++ if (!hw->base) { ++ dev_err(&pdev->dev, "failed to remap memory region\n"); ++ ret = -ENXIO; ++ goto err_master; ++ } ++ ++ memset(hw->irq, 0, sizeof(hw->irq)); ++ for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) { ++ hw->irq[i] = irqres[i].start; ++ ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler, ++ 0, ltq_spi_irqs[i].name, hw); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request %s irq (%d)\n", ++ ltq_spi_irqs[i].name, hw->irq[i]); ++ goto err_irq; ++ } ++ } ++ ++ hw->fpiclk = clk_get_fpi(); ++ if (IS_ERR(hw->fpiclk)) { ++ dev_err(&pdev->dev, "failed to get fpi clock\n"); ++ ret = PTR_ERR(hw->fpiclk); ++ goto err_clk; ++ } ++ ++ hw->spiclk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(hw->spiclk)) { ++ dev_err(&pdev->dev, "failed to get spi clock gate\n"); ++ ret = PTR_ERR(hw->spiclk); ++ goto err_clk; ++ } ++ ++ hw->bitbang.master = spi_master_get(master); ++ hw->bitbang.chipselect = ltq_spi_chipselect; ++ hw->bitbang.setup_transfer = ltq_spi_setup_transfer; ++ hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs; ++ ++ if (of_machine_is_compatible("lantiq,ase")) ++ master->num_chipselect = 3; ++ else ++ master->num_chipselect = 6; ++ master->bus_num = pdev->id; ++ master->setup = ltq_spi_setup; ++ master->cleanup = ltq_spi_cleanup; ++ master->dev.of_node = pdev->dev.of_node; ++ ++ hw->dev = &pdev->dev; ++ init_completion(&hw->done); ++ spin_lock_init(&hw->lock); ++ ++ ltq_spi_hw_enable(hw); ++ ++ /* Read module capabilities */ ++ id = ltq_spi_reg_read(hw, LTQ_SPI_ID); ++ hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; ++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK; ++ hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0; ++ ++ ltq_spi_config_mode_set(hw); ++ ++ /* Enable error checking, disable TX/RX, set idle value high */ ++ data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | ++ LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | ++ LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE; ++ ltq_spi_reg_write(hw, data, LTQ_SPI_CON); ++ ++ /* Enable master mode and clear error flags */ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS | ++ LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); ++ ++ /* Reset GPIO/CS registers */ ++ ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON); ++ ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO); ++ ++ /* Enable and flush FIFOs */ ++ ltq_spi_reset_fifos(hw); ++ ++ ret = spi_bitbang_start(&hw->bitbang); ++ if (ret) { ++ dev_err(&pdev->dev, "spi_bitbang_start failed\n"); ++ goto err_bitbang; ++ } ++ ++ platform_set_drvdata(pdev, hw); ++ ++ pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n", ++ id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support); ++ ++ return 0; ++ ++err_bitbang: ++ ltq_spi_hw_disable(hw); ++ ++err_clk: ++ if (hw->fpiclk) ++ clk_put(hw->fpiclk); ++ if (hw->spiclk) ++ clk_put(hw->spiclk); ++ ++err_irq: ++ clk_put(hw->fpiclk); ++ ++ for (; i > 0; i--) ++ free_irq(hw->irq[i], hw); ++ ++err_master: ++ spi_master_put(master); ++ ++err: ++ return ret; ++} ++ ++static int ltq_spi_remove(struct platform_device *pdev) ++{ ++ struct ltq_spi *hw = platform_get_drvdata(pdev); ++ int i; ++ ++ spi_bitbang_stop(&hw->bitbang); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ ltq_spi_config_mode_set(hw); ++ ltq_spi_hw_disable(hw); ++ ++ for (i = 0; i < ARRAY_SIZE(hw->irq); i++) ++ if (0 < hw->irq[i]) ++ free_irq(hw->irq[i], hw); ++ ++ if (hw->fpiclk) ++ clk_put(hw->fpiclk); ++ if (hw->spiclk) ++ clk_put(hw->spiclk); ++ ++ spi_master_put(hw->bitbang.master); ++ ++ return 0; ++} ++ ++static const struct of_device_id ltq_spi_match[] = { ++ { .compatible = "lantiq,spi-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_spi_match); ++ ++static struct platform_driver ltq_spi_driver = { ++ .probe = ltq_spi_probe, ++ .remove = ltq_spi_remove, ++ .driver = { ++ .name = "spi-xway", ++ .owner = THIS_MODULE, ++ .of_match_table = ltq_spi_match, ++ }, ++}; ++ ++module_platform_driver(ltq_spi_driver); ++ ++MODULE_DESCRIPTION("Lantiq SoC SPI controller driver"); ++MODULE_AUTHOR("Daniel Schwierzeck "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:spi-xway"); diff --git a/target/linux/lantiq/patches-3.18/0034-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch b/target/linux/lantiq/patches-3.18/0034-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch new file mode 100644 index 0000000..6590b7b --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0034-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch @@ -0,0 +1,45 @@ +From b1b9fca8c317afc3f2b78bb54f877e8a830a819d Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 9 Aug 2013 18:47:27 +0200 +Subject: [PATCH 34/36] reset: Fix compile when reset RESET_CONTROLLER is not + selected + +Drivers need to protect their reset api calls with #ifdef to avoid compile +errors. + +This patch adds dummy wrappers in the same way that linux/of.h does it. + +Cc: linux-kernel@vger.kernel.org +Cc: Philipp Zabel +Cc: Gabor Juhos +--- + include/linux/reset-controller.h | 16 ++++++++++++++ + include/linux/reset.h | 43 ++++++++++++++++++++++++++++++++++++++ + 2 files changed, 59 insertions(+) + +--- a/include/linux/reset-controller.h ++++ b/include/linux/reset-controller.h +@@ -46,7 +46,23 @@ struct reset_controller_dev { + unsigned int nr_resets; + }; + ++#if defined(CONFIG_RESET_CONTROLLER) ++ + int reset_controller_register(struct reset_controller_dev *rcdev); + void reset_controller_unregister(struct reset_controller_dev *rcdev); + ++#else ++ ++static inline int reset_controller_register(struct reset_controller_dev *rcdev) ++{ ++ return -ENOSYS; ++} ++ ++void reset_controller_unregister(struct reset_controller_dev *rcdev) ++{ ++ ++} ++ ++#endif ++ + #endif diff --git a/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch new file mode 100644 index 0000000..2fc4db3 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -0,0 +1,614 @@ +From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:42:14 +0200 +Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h | 6 + + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + + arch/mips/lantiq/xway/Makefile | 3 + + arch/mips/lantiq/xway/ath_eep.c | 282 ++++++++++++++++++++ + arch/mips/lantiq/xway/eth_mac.c | 76 ++++++ + arch/mips/lantiq/xway/pci-ath-fixup.c | 109 ++++++++ + arch/mips/lantiq/xway/rt_eep.c | 60 +++++ + 7 files changed, 539 insertions(+) + create mode 100644 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h + create mode 100644 arch/mips/lantiq/xway/ath_eep.c + create mode 100644 arch/mips/lantiq/xway/eth_mac.c + create mode 100644 arch/mips/lantiq/xway/pci-ath-fixup.c + create mode 100644 arch/mips/lantiq/xway/rt_eep.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h +@@ -0,0 +1,6 @@ ++#ifndef _PCI_ATH_FIXUP ++#define _PCI_ATH_FIXUP ++ ++void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init; ++ ++#endif /* _PCI_ATH_FIXUP */ +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -90,5 +90,8 @@ int xrx200_gphy_boot(struct device *dev, + extern void ltq_pmu_enable(unsigned int module); + extern void ltq_pmu_disable(unsigned int module); + ++/* allow the ethernet driver to load a flash mapped mac addr */ ++const u8* ltq_get_eth_mac(void); ++ + #endif /* CONFIG_SOC_TYPE_XWAY */ + #endif /* _LTQ_XWAY_H__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -2,4 +2,7 @@ obj-y := prom.o sysctrl.o clk.o reset.o + + obj-y += vmmc.o tffs.o + ++obj-y += eth_mac.o ++obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o ++ + obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/ath_eep.c +@@ -0,0 +1,282 @@ ++/* ++ * Copyright (C) 2011 Luca Olivetti ++ * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011 Andrej VlaÅ¡ić ++ * Copyright (C) 2013 Ãlvaro Fernández Rojas ++ * Copyright (C) 2013 Daniel Gimpelevich ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); ++struct ath5k_platform_data ath5k_pdata; ++struct ath9k_platform_data ath9k_pdata = { ++ .led_pin = -1, ++}; ++static u8 athxk_eeprom_mac[6]; ++ ++static int ath9k_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &ath9k_pdata; ++ return 0; ++} ++ ++static int ath9k_eep_load; ++int __init of_ath9k_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node, *mtd_np; ++ struct resource *eep_res, *mac_res = NULL; ++ void __iomem *eep, *mac; ++ int mac_offset, led_pin; ++ u32 mac_inc = 0, pci_slot = 0; ++ int i; ++ struct mtd_info *the_mtd; ++ size_t flash_readlen; ++ const __be32 *list; ++ const char *part; ++ phandle phandle; ++ ++ if ((list = of_get_property(np, "ath,eep-flash", &i)) && i == 2 * ++ sizeof(*list) && (phandle = be32_to_cpup(list++)) && ++ (mtd_np = of_find_node_by_phandle(phandle)) && ((part = ++ of_get_property(mtd_np, "label", NULL)) || (part = ++ mtd_np->name)) && (the_mtd = get_mtd_device_nm(part)) ++ != ERR_PTR(-ENODEV)) { ++ i = mtd_read(the_mtd, be32_to_cpup(list), ++ ATH9K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen, ++ (void *) ath9k_pdata.eeprom_data); ++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { ++ size_t mac_readlen; ++ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, ++ (void *) athxk_eeprom_mac); ++ } ++ put_mtd_device(the_mtd); ++ if ((sizeof(ath9k_pdata.eeprom_data) != flash_readlen) || i) { ++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); ++ return -ENODEV; ++ } ++ } else { ++ eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ ++ if (!eep_res) { ++ dev_err(&pdev->dev, "failed to load eeprom address\n"); ++ return -ENODEV; ++ } ++ if (resource_size(eep_res) != ATH9K_PLAT_EEP_MAX_WORDS << 1) { ++ dev_err(&pdev->dev, "eeprom has an invalid size\n"); ++ return -EINVAL; ++ } ++ ++ eep = ioremap(eep_res->start, resource_size(eep_res)); ++ memcpy_fromio(ath9k_pdata.eeprom_data, eep, ++ ATH9K_PLAT_EEP_MAX_WORDS << 1); ++ } ++ ++ if (of_find_property(np, "ath,eep-swap", NULL)) ++ for (i = 0; i < ATH9K_PLAT_EEP_MAX_WORDS; i++) ++ ath9k_pdata.eeprom_data[i] = swab16(ath9k_pdata.eeprom_data[i]); ++ ++ if (of_find_property(np, "ath,eep-endian", NULL)) { ++ ath9k_pdata.endian_check = true; ++ ++ dev_info(&pdev->dev, "endian check enabled.\n"); ++ } ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac)) { ++ if (mac_res) { ++ if (resource_size(mac_res) != 6) { ++ dev_err(&pdev->dev, "mac has an invalid size\n"); ++ return -EINVAL; ++ } ++ mac = ioremap(mac_res->start, resource_size(mac_res)); ++ memcpy_fromio(athxk_eeprom_mac, mac, 6); ++ } else if (ltq_get_eth_mac()) { ++ memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6); ++ } ++ } ++ if (!is_valid_ether_addr(athxk_eeprom_mac)) { ++ dev_warn(&pdev->dev, "using random mac\n"); ++ random_ether_addr(athxk_eeprom_mac); ++ } ++ ++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) ++ athxk_eeprom_mac[5] += mac_inc; ++ ++ ath9k_pdata.macaddr = athxk_eeprom_mac; ++ ltq_pci_plat_dev_init = ath9k_pci_plat_dev_init; ++ ++ if (!of_property_read_u32(np, "ath,pci-slot", &pci_slot)) { ++ ltq_pci_ath_fixup(pci_slot, ath9k_pdata.eeprom_data); ++ ++ dev_info(&pdev->dev, "pci slot: %u\n", pci_slot); ++ if (ath9k_eep_load) { ++ struct pci_dev *d = NULL; ++ while ((d = pci_get_device(PCI_VENDOR_ID_ATHEROS, ++ PCI_ANY_ID, d)) != NULL) ++ pci_fixup_device(pci_fixup_early, d); ++ } ++ ++ } ++ ++ if (!of_property_read_u32(np, "ath,led-pin", &led_pin)) { ++ ath9k_pdata.led_pin = led_pin; ++ dev_info(&pdev->dev, "using led pin %d.\n", led_pin); ++ } ++ ++ dev_info(&pdev->dev, "loaded ath9k eeprom\n"); ++ ++ return 0; ++} ++ ++static struct of_device_id ath9k_eeprom_ids[] = { ++ { .compatible = "ath9k,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ath9k_eeprom_driver = { ++ .driver = { ++ .name = "ath9k,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ath9k_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ath9k_eeprom_init(void) ++{ ++ int ret = platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe); ++ ++ if (ret) ++ ath9k_eep_load = 1; ++ ++ return ret; ++} ++ ++static int __init of_ath9k_eeprom_init_late(void) ++{ ++ if (!ath9k_eep_load) ++ return 0; ++ return platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe); ++} ++late_initcall(of_ath9k_eeprom_init_late); ++subsys_initcall(of_ath9k_eeprom_init); ++ ++ ++static int ath5k_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &ath5k_pdata; ++ return 0; ++} ++ ++int __init of_ath5k_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node, *mtd_np; ++ struct resource *eep_res, *mac_res = NULL; ++ void __iomem *eep, *mac; ++ int mac_offset; ++ u32 mac_inc = 0; ++ int i; ++ struct mtd_info *the_mtd; ++ size_t flash_readlen; ++ const __be32 *list; ++ const char *part; ++ phandle phandle; ++ ++ if ((list = of_get_property(np, "ath,eep-flash", &i)) && i == 2 * ++ sizeof(*list) && (phandle = be32_to_cpup(list++)) && ++ (mtd_np = of_find_node_by_phandle(phandle)) && ((part = ++ of_get_property(mtd_np, "label", NULL)) || (part = ++ mtd_np->name)) && (the_mtd = get_mtd_device_nm(part)) ++ != ERR_PTR(-ENODEV)) { ++ i = mtd_read(the_mtd, be32_to_cpup(list), ++ ATH5K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen, ++ (void *) ath5k_pdata.eeprom_data); ++ put_mtd_device(the_mtd); ++ if ((sizeof(ATH5K_PLAT_EEP_MAX_WORDS << 1) != flash_readlen) ++ || i) { ++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); ++ return -ENODEV; ++ } ++ } else { ++ eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ ++ if (!eep_res) { ++ dev_err(&pdev->dev, "failed to load eeprom address\n"); ++ return -ENODEV; ++ } ++ if (resource_size(eep_res) != ATH5K_PLAT_EEP_MAX_WORDS << 1) { ++ dev_err(&pdev->dev, "eeprom has an invalid size\n"); ++ return -EINVAL; ++ } ++ ++ eep = ioremap(eep_res->start, resource_size(eep_res)); ++ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, ++ GFP_KERNEL); ++ memcpy_fromio(ath5k_pdata.eeprom_data, eep, ++ ATH5K_PLAT_EEP_MAX_WORDS << 1); ++ } ++ ++ if (of_find_property(np, "ath,eep-swap", NULL)) ++ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) ++ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); ++ ++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { ++ memcpy_fromio(athxk_eeprom_mac, (void*) ath5k_pdata.eeprom_data + mac_offset, 6); ++ } else if (mac_res) { ++ if (resource_size(mac_res) != 6) { ++ dev_err(&pdev->dev, "mac has an invalid size\n"); ++ return -EINVAL; ++ } ++ mac = ioremap(mac_res->start, resource_size(mac_res)); ++ memcpy_fromio(athxk_eeprom_mac, mac, 6); ++ } else if (ltq_get_eth_mac()) ++ memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6); ++ else { ++ dev_warn(&pdev->dev, "using random mac\n"); ++ random_ether_addr(athxk_eeprom_mac); ++ } ++ ++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) ++ athxk_eeprom_mac[5] += mac_inc; ++ ++ ath5k_pdata.macaddr = athxk_eeprom_mac; ++ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; ++ ++ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); ++ ++ return 0; ++} ++ ++static struct of_device_id ath5k_eeprom_ids[] = { ++ { .compatible = "ath5k,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ath5k_eeprom_driver = { ++ .driver = { ++ .name = "ath5k,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ath5k_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ath5k_eeprom_init(void) ++{ ++ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++} ++device_initcall(of_ath5k_eeprom_init); +--- /dev/null ++++ b/arch/mips/lantiq/xway/eth_mac.c +@@ -0,0 +1,76 @@ ++/* ++ * Copyright (C) 2012 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++static u8 eth_mac[6]; ++static int eth_mac_set; ++ ++const u8* ltq_get_eth_mac(void) ++{ ++ return eth_mac; ++} ++ ++static int __init setup_ethaddr(char *str) ++{ ++ eth_mac_set = mac_pton(str, eth_mac); ++ return !eth_mac_set; ++} ++__setup("ethaddr=", setup_ethaddr); ++ ++int __init of_eth_mac_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct resource *mac_res; ++ void __iomem *mac; ++ u32 mac_inc = 0; ++ ++ if (eth_mac_set) { ++ dev_err(&pdev->dev, "mac was already set by bootloader\n"); ++ return -EINVAL; ++ } ++ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ if (!mac_res) { ++ dev_err(&pdev->dev, "failed to load mac\n"); ++ return -EINVAL; ++ } ++ if (resource_size(mac_res) != 6) { ++ dev_err(&pdev->dev, "mac has an invalid size\n"); ++ return -EINVAL; ++ } ++ mac = ioremap(mac_res->start, resource_size(mac_res)); ++ memcpy_fromio(eth_mac, mac, 6); ++ ++ if (!of_property_read_u32(np, "mac-increment", &mac_inc)) ++ eth_mac[5] += mac_inc; ++ ++ return 0; ++} ++ ++static struct of_device_id eth_mac_ids[] = { ++ { .compatible = "lantiq,eth-mac" }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver eth_mac_driver = { ++ .driver = { ++ .name = "lantiq,eth-mac", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(eth_mac_ids), ++ }, ++}; ++ ++static int __init of_eth_mac_init(void) ++{ ++ return platform_driver_probe(ð_mac_driver, of_eth_mac_probe); ++} ++device_initcall(of_eth_mac_init); +--- /dev/null ++++ b/arch/mips/lantiq/xway/pci-ath-fixup.c +@@ -0,0 +1,118 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++struct ath_fixup { ++ u16 *cal_data; ++ unsigned slot; ++}; ++ ++static int ath_num_fixups; ++static struct ath_fixup ath_fixups[2]; ++ ++static void ath_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ struct pci_dev *bridge = pci_upstream_bridge(dev); ++ u16 *cal_data = NULL; ++ u16 cmd; ++ u32 bar0; ++ u32 val; ++ u32 base; ++ unsigned i; ++ ++ for (i = 0; i < ath_num_fixups; i++) { ++ if (ath_fixups[i].cal_data == NULL) ++ continue; ++ ++ if (ath_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ cal_data = ath_fixups[i].cal_data; ++ break; ++ } ++ ++ if (cal_data == NULL) ++ return; ++ ++ if (*cal_data != 0xa55a) { ++ pr_err("pci %s: invalid calibration data\n", pci_name(dev)); ++ return; ++ } ++ ++ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); ++ ++ base = dev->resource[0].start; ++ mem = ioremap(base, 0x10000); ++ if (!mem) { ++ pr_err("pci %s: ioremap error\n", pci_name(dev)); ++ return; ++ } ++ ++ if (bridge) { ++ pci_enable_device(dev); ++ } ++ ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base); ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ /* set pointer to first reg address */ ++ cal_data += 3; ++ while (*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; ++ ++ ltq_w32(swab32(val), mem + reg); ++ udelay(100); ++ } ++ ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; ++ ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ ++ ++ pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n", ++ pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class); ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); ++ ++ if (bridge) { ++ pci_disable_device(dev); ++ } ++ ++ iounmap(mem); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup); ++ ++void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) ++{ ++ if (ath_num_fixups >= ARRAY_SIZE(ath_fixups)) ++ return; ++ ++ ath_fixups[ath_num_fixups].slot = slot; ++ ath_fixups[ath_num_fixups].cal_data = cal_data; ++ ath_num_fixups++; ++} +--- /dev/null ++++ b/arch/mips/lantiq/xway/rt_eep.c +@@ -0,0 +1,60 @@ ++/* ++ * Copyright (C) 2011 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); ++static struct rt2x00_platform_data rt2x00_pdata; ++ ++static int rt2x00_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &rt2x00_pdata; ++ return 0; ++} ++ ++int __init of_ralink_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ const char *eeprom; ++ ++ if (of_property_read_string(np, "ralink,eeprom", &eeprom)) { ++ dev_err(&pdev->dev, "failed to load eeprom filename\n"); ++ return 0; ++ } ++ ++ rt2x00_pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL); ++// rt2x00_pdata.mac_address = mac; ++ ltq_pci_plat_dev_init = rt2x00_pci_plat_dev_init; ++ ++ dev_info(&pdev->dev, "using %s as eeprom\n", eeprom); ++ ++ return 0; ++} ++ ++static struct of_device_id ralink_eeprom_ids[] = { ++ { .compatible = "ralink,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ralink_eeprom_driver = { ++ .driver = { ++ .name = "ralink,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ralink_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ralink_eeprom_init(void) ++{ ++ return platform_driver_probe(&ralink_eeprom_driver, of_ralink_eeprom_probe); ++} ++device_initcall(of_ralink_eeprom_init); +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -840,7 +840,11 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + +- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); ++ if (priv->mac) ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ else ++ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); ++ + if (!is_valid_ether_addr(mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-3.18/0036-owrt-generic-dtb-image-hack.patch b/target/linux/lantiq/patches-3.18/0036-owrt-generic-dtb-image-hack.patch new file mode 100644 index 0000000..7a306b3 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0036-owrt-generic-dtb-image-hack.patch @@ -0,0 +1,32 @@ +From dba8578e06aedf1e67312ebfc6162e2fadc9448d Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:32:12 +0200 +Subject: [PATCH 36/36] owrt: generic dtb image hack + +Signed-off-by: John Crispin +--- + arch/mips/kernel/head.S | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -86,6 +86,9 @@ EXPORT(__image_cmdline) + .fill 0x400 + #endif /* CONFIG_IMAGE_CMDLINE_HACK */ + ++ .ascii "OWRTDTB:" ++ EXPORT(__image_dtb) ++ .fill 0x4000 + __REF + + NESTED(kernel_entry, 16, sp) # kernel entry point +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -32,7 +32,6 @@ choice + config DT_EASY50712 + bool "Easy50712" + depends on SOC_XWAY +- select BUILTIN_DTB + endchoice + + config PCI_LANTIQ diff --git a/target/linux/lantiq/patches-3.18/0037-MIPS-lantiq-move-eiu-init-after-irq_domain-register.patch b/target/linux/lantiq/patches-3.18/0037-MIPS-lantiq-move-eiu-init-after-irq_domain-register.patch new file mode 100644 index 0000000..32e4ab8 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0037-MIPS-lantiq-move-eiu-init-after-irq_domain-register.patch @@ -0,0 +1,74 @@ +From baea71233ed1796651cab6ead484a18666a765aa Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 11 Sep 2014 19:25:25 +0200 +Subject: [PATCH] MIPS: lantiq: move eiu init after irq_domain register + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/irq.c | 48 ++++++++++++++++++++++++------------------------ + 1 file changed, 24 insertions(+), 24 deletions(-) + +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -380,30 +380,6 @@ int __init icu_of_init(struct device_nod + panic("Failed to remap icu memory"); + } + +- /* the external interrupts are optional and xway only */ +- eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway"); +- if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) { +- /* find out how many external irq sources we have */ +- exin_avail = of_irq_count(eiu_node); +- +- if (exin_avail > MAX_EIU) +- exin_avail = MAX_EIU; +- +- ret = of_irq_to_resource_table(eiu_node, +- ltq_eiu_irq, exin_avail); +- if (ret != exin_avail) +- panic("failed to load external irq resources"); +- +- if (request_mem_region(res.start, resource_size(&res), +- res.name) < 0) +- pr_err("Failed to request eiu memory"); +- +- ltq_eiu_membase = ioremap_nocache(res.start, +- resource_size(&res)); +- if (!ltq_eiu_membase) +- panic("Failed to remap eiu memory"); +- } +- + /* turn off all irqs by default */ + for (i = 0; i < MAX_IM; i++) { + /* make sure all irqs are turned off by default */ +@@ -460,6 +436,30 @@ int __init icu_of_init(struct device_nod + if (MIPS_CPU_TIMER_IRQ != 7) + irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ); + ++ /* the external interrupts are optional and xway only */ ++ eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway"); ++ if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) { ++ /* find out how many external irq sources we have */ ++ exin_avail = of_irq_count(eiu_node); ++ ++ if (exin_avail > MAX_EIU) ++ exin_avail = MAX_EIU; ++ ++ ret = of_irq_to_resource_table(eiu_node, ++ ltq_eiu_irq, exin_avail); ++ if (ret != exin_avail) ++ panic("failed to load external irq resources"); ++ ++ if (request_mem_region(res.start, resource_size(&res), ++ res.name) < 0) ++ pr_err("Failed to request eiu memory"); ++ ++ ltq_eiu_membase = ioremap_nocache(res.start, ++ resource_size(&res)); ++ if (!ltq_eiu_membase) ++ panic("Failed to remap eiu memory"); ++ } ++ + return 0; + } + diff --git a/target/linux/lantiq/patches-3.18/0038-MIPS-lantiq-fpi-on-ar9.patch b/target/linux/lantiq/patches-3.18/0038-MIPS-lantiq-fpi-on-ar9.patch new file mode 100644 index 0000000..5fbe0a1 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0038-MIPS-lantiq-fpi-on-ar9.patch @@ -0,0 +1,21 @@ +Return correct value for fpi clock on ar9. + +Signed-off-by: Ben Mulvihill +--- + arch/mips/lantiq/xway/clk.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/arch/mips/lantiq/xway/clk.c ++++ b/arch/mips/lantiq/xway/clk.c +@@ -87,8 +87,9 @@ unsigned long ltq_ar9_fpi_hz(void) + unsigned long sys = ltq_ar9_sys_hz(); + + if (ltq_cgu_r32(CGU_SYS) & BIT(0)) +- return sys; +- return sys >> 1; ++ return sys / 3; ++ else ++ return sys / 2; + } + + unsigned long ltq_ar9_cpu_hz(void) diff --git a/target/linux/lantiq/patches-3.18/0039-MIPS-lantiq-initialize-usb-on-boot.patch b/target/linux/lantiq/patches-3.18/0039-MIPS-lantiq-initialize-usb-on-boot.patch new file mode 100644 index 0000000..fd0da8e --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0039-MIPS-lantiq-initialize-usb-on-boot.patch @@ -0,0 +1,97 @@ +--- a/arch/mips/lantiq/xway/reset.c ++++ b/arch/mips/lantiq/xway/reset.c +@@ -44,6 +44,37 @@ + #define RCU_BOOT_SEL(x) ((x >> 18) & 0x7) + #define RCU_BOOT_SEL_XRX200(x) (((x >> 17) & 0xf) | ((x >> 8) & 0x10)) + ++/* dwc2 USB configuration registers */ ++#define RCU_USB1CFG 0x0018 ++#define RCU_USB2CFG 0x0034 ++ ++/* USB DMA endianness bits */ ++#define RCU_USBCFG_HDSEL_BIT BIT(11) ++#define RCU_USBCFG_HOST_END_BIT BIT(10) ++#define RCU_USBCFG_SLV_END_BIT BIT(9) ++ ++/* USB reset bits */ ++#define RCU_USBRESET 0x0010 ++ ++#define USBRESET_BIT BIT(4) ++ ++#define RCU_USBRESET2 0x0048 ++ ++#define USB1RESET_BIT BIT(4) ++#define USB2RESET_BIT BIT(5) ++ ++#define RCU_CFG1A 0x0038 ++#define RCU_CFG1B 0x003C ++ ++/* USB PMU devices */ ++#define PMU_AHBM BIT(15) ++#define PMU_USB0 BIT(6) ++#define PMU_USB1 BIT(27) ++ ++/* USB PHY PMU devices */ ++#define PMU_USB0_P BIT(0) ++#define PMU_USB1_P BIT(26) ++ + /* remapped base addr of the reset control unit */ + static void __iomem *ltq_rcu_membase; + static struct device_node *ltq_rcu_np; +@@ -200,6 +231,45 @@ static void ltq_machine_power_off(void) + unreachable(); + } + ++static void ltq_usb_init(void) ++{ ++ /* Power for USB cores 1 & 2 */ ++ ltq_pmu_enable(PMU_AHBM); ++ ltq_pmu_enable(PMU_USB0); ++ ltq_pmu_enable(PMU_USB1); ++ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B); ++ ++ /* Enable USB PHY power for cores 1 & 2 */ ++ ltq_pmu_enable(PMU_USB0_P); ++ ltq_pmu_enable(PMU_USB1_P); ++ ++ /* Configure cores to host mode */ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT, ++ RCU_USB1CFG); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT, ++ RCU_USB2CFG); ++ ++ /* Select DMA endianness (Host-endian: big-endian) */ ++ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT) ++ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG); ++ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT) ++ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG); ++ ++ /* Hard reset USB state machines */ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET); ++ udelay(50 * 1000); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET); ++ ++ /* Soft reset USB state machines */ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2) ++ | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2); ++ udelay(50 * 1000); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2) ++ & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2); ++} ++ + static int __init mips_reboot_setup(void) + { + struct resource res; +@@ -223,6 +293,10 @@ static int __init mips_reboot_setup(void + if (!ltq_rcu_membase) + panic("Failed to remap core memory"); + ++ if (of_machine_is_compatible("lantiq,ar9") || ++ of_machine_is_compatible("lantiq,vr9")) ++ ltq_usb_init(); ++ + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; diff --git a/target/linux/lantiq/patches-3.18/0040-USB-DWC2-enable-usb-power-gpio.patch b/target/linux/lantiq/patches-3.18/0040-USB-DWC2-enable-usb-power-gpio.patch new file mode 100644 index 0000000..76fbb7b --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0040-USB-DWC2-enable-usb-power-gpio.patch @@ -0,0 +1,35 @@ +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -40,6 +40,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -154,6 +155,7 @@ static int dwc2_driver_probe(struct plat + struct resource *res; + int retval; + int irq; ++ int gpio_count; + + if (usb_disabled()) + return -ENODEV; +@@ -173,6 +175,16 @@ static int dwc2_driver_probe(struct plat + defparams.dma_desc_enable = 0; + } + ++ gpio_count = of_gpio_count(dev->dev.of_node); ++ while (gpio_count > 0) { ++ enum of_gpio_flags flags; ++ int gpio = of_get_gpio_flags(dev->dev.of_node, --gpio_count, &flags); ++ if (gpio_request(gpio, "usb")) ++ continue; ++ dev_info(&dev->dev, "requested GPIO %d\n", gpio); ++ gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); ++ } ++ + hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); + if (!hsotg) + return -ENOMEM; diff --git a/target/linux/lantiq/patches-3.18/0041-USB-DWC2-add-ltq-params.patch b/target/linux/lantiq/patches-3.18/0041-USB-DWC2-add-ltq-params.patch new file mode 100644 index 0000000..a0af123 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0041-USB-DWC2-add-ltq-params.patch @@ -0,0 +1,46 @@ +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -106,6 +106,34 @@ static const struct dwc2_core_params par + .uframe_sched = -1, + }; + ++static const struct dwc2_core_params params_ltq = { ++ .otg_cap = 2, /* non-HNP/non-SRP */ ++ .otg_ver = -1, ++ .dma_enable = -1, ++ .dma_desc_enable = -1, ++ .speed = -1, ++ .enable_dynamic_fifo = -1, ++ .en_multiple_tx_fifo = -1, ++ .host_rx_fifo_size = 240, /* 240 DWORDs */ ++ .host_nperio_tx_fifo_size = 240, /* 240 DWORDs */ ++ .host_perio_tx_fifo_size = 32, /* 32 DWORDs */ ++ .max_transfer_size = -1, ++ .max_packet_count = -1, ++ .host_channels = -1, ++ .phy_type = -1, ++ .phy_utmi_width = -1, ++ .phy_ulpi_ddr = -1, ++ .phy_ulpi_ext_vbus = -1, ++ .i2c_enable = -1, ++ .ulpi_fs_ls = -1, ++ .host_support_fs_ls_low_power = -1, ++ .host_ls_low_power_phy_clk = -1, ++ .ts_dline = -1, ++ .reload_ctl = -1, ++ .ahbcfg = -1, ++ .uframe_sched = -1, ++}; ++ + /** + * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the + * DWC_otg driver +@@ -129,6 +157,8 @@ static int dwc2_driver_remove(struct pla + static const struct of_device_id dwc2_of_match_table[] = { + { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, + { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, ++ { .compatible = "lantiq,ifxhcd-arx100-dwc2", .data = ¶ms_ltq }, ++ { .compatible = "lantiq,ifxhcd-xrx200-dwc2", .data = ¶ms_ltq }, + { .compatible = "snps,dwc2", .data = NULL }, + {}, + }; diff --git a/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch b/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch new file mode 100644 index 0000000..0455d35 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch @@ -0,0 +1,3184 @@ +--- a/drivers/usb/dwc2/core.c ++++ b/drivers/usb/dwc2/core.c +@@ -67,10 +67,10 @@ static void dwc2_enable_common_interrupt + u32 intmsk; + + /* Clear any pending OTG Interrupts */ +- writel(0xffffffff, hsotg->regs + GOTGINT); ++ dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + + /* Clear any pending interrupts */ +- writel(0xffffffff, hsotg->regs + GINTSTS); ++ dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + + /* Enable the interrupts in the GINTMSK */ + intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; +@@ -81,7 +81,7 @@ static void dwc2_enable_common_interrupt + intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP | + GINTSTS_SESSREQINT; + +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /* +@@ -104,10 +104,10 @@ static void dwc2_init_fs_ls_pclk_sel(str + } + + dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + + /* +@@ -125,7 +125,7 @@ static int dwc2_core_reset(struct dwc2_h + /* Wait for AHB master IDLE state */ + do { + usleep_range(20000, 40000); +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 50) { + dev_warn(hsotg->dev, + "%s() HANG! AHB Idle GRSTCTL=%0x\n", +@@ -137,10 +137,10 @@ static int dwc2_core_reset(struct dwc2_h + /* Core Soft Reset */ + count = 0; + greset |= GRSTCTL_CSFTRST; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + do { + usleep_range(20000, 40000); +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 50) { + dev_warn(hsotg->dev, + "%s() HANG! Soft Reset GRSTCTL=%0x\n", +@@ -150,20 +150,20 @@ static int dwc2_core_reset(struct dwc2_h + } while (greset & GRSTCTL_CSFTRST); + + if (hsotg->dr_mode == USB_DR_MODE_HOST) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEDEVMODE; + gusbcfg |= GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; + gusbcfg |= GUSBCFG_FORCEDEVMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } else if (hsotg->dr_mode == USB_DR_MODE_OTG) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; + gusbcfg &= ~GUSBCFG_FORCEDEVMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } + + /* +@@ -186,9 +186,9 @@ static int dwc2_fs_phy_init(struct dwc2_ + */ + if (select_phy) { + dev_dbg(hsotg->dev, "FS PHY selected\n"); +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_PHYSEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset after a PHY select */ + retval = dwc2_core_reset(hsotg); +@@ -211,18 +211,18 @@ static int dwc2_fs_phy_init(struct dwc2_ + dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); + + /* Program GUSBCFG.OtgUtmiFsSel to I2C */ +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Program GI2CCTL.I2CEn */ +- i2cctl = readl(hsotg->regs + GI2CCTL); ++ i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); + i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; + i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; + i2cctl &= ~GI2CCTL_I2CEN; +- writel(i2cctl, hsotg->regs + GI2CCTL); ++ dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); + i2cctl |= GI2CCTL_I2CEN; +- writel(i2cctl, hsotg->regs + GI2CCTL); ++ dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); + } + + return retval; +@@ -236,7 +236,7 @@ static int dwc2_hs_phy_init(struct dwc2_ + if (!select_phy) + return 0; + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + + /* + * HS PHY parameters. These parameters are preserved during soft reset +@@ -264,7 +264,7 @@ static int dwc2_hs_phy_init(struct dwc2_ + break; + } + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset after setting the PHY parameters */ + retval = dwc2_core_reset(hsotg); +@@ -299,15 +299,15 @@ static int dwc2_phy_init(struct dwc2_hso + hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && + hsotg->core_params->ulpi_fs_ls > 0) { + dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_ULPI_FS_LS; + usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } else { +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg &= ~GUSBCFG_ULPI_FS_LS; + usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } + + return retval; +@@ -315,7 +315,7 @@ static int dwc2_phy_init(struct dwc2_hso + + static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + switch (hsotg->hw_params.arch) { + case GHWCFG2_EXT_DMA_ARCH: +@@ -354,7 +354,7 @@ static int dwc2_gahbcfg_init(struct dwc2 + if (hsotg->core_params->dma_enable > 0) + ahbcfg |= GAHBCFG_DMA_EN; + +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + + return 0; + } +@@ -363,7 +363,7 @@ static void dwc2_gusbcfg_init(struct dwc + { + u32 usbcfg; + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); + + switch (hsotg->hw_params.op_mode) { +@@ -391,7 +391,7 @@ static void dwc2_gusbcfg_init(struct dwc + break; + } + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } + + /** +@@ -409,7 +409,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs + + dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + + /* Set ULPI External VBUS bit if needed */ + usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; +@@ -422,7 +422,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs + if (hsotg->core_params->ts_dline > 0) + usbcfg |= GUSBCFG_TERMSELDLPULSE; + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset the Controller */ + retval = dwc2_core_reset(hsotg); +@@ -448,11 +448,11 @@ int dwc2_core_init(struct dwc2_hsotg *hs + dwc2_gusbcfg_init(hsotg); + + /* Program the GOTGCTL register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_OTGVER; + if (hsotg->core_params->otg_ver > 0) + otgctl |= GOTGCTL_OTGVER; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); + + /* Clear the SRP success bit for FS-I2c */ +@@ -498,16 +498,16 @@ void dwc2_enable_host_interrupts(struct + dev_dbg(hsotg->dev, "%s()\n", __func__); + + /* Disable all interrupts */ +- writel(0, hsotg->regs + GINTMSK); +- writel(0, hsotg->regs + HAINTMSK); ++ dwc2_writel(0, hsotg->regs + GINTMSK); ++ dwc2_writel(0, hsotg->regs + HAINTMSK); + + /* Enable the common interrupts */ + dwc2_enable_common_interrupts(hsotg); + + /* Enable host mode interrupts without disturbing common interrupts */ +- intmsk = readl(hsotg->regs + GINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /** +@@ -517,12 +517,12 @@ void dwc2_enable_host_interrupts(struct + */ + void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 intmsk = readl(hsotg->regs + GINTMSK); ++ u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); + + /* Disable host mode interrupts without disturbing common interrupts */ + intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | + GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /* +@@ -602,36 +602,36 @@ static void dwc2_config_fifos(struct dwc + dwc2_calculate_dynamic_fifo(hsotg); + + /* Rx FIFO */ +- grxfsiz = readl(hsotg->regs + GRXFSIZ); ++ grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); + grxfsiz &= ~GRXFSIZ_DEPTH_MASK; + grxfsiz |= params->host_rx_fifo_size << + GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; +- writel(grxfsiz, hsotg->regs + GRXFSIZ); +- dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ)); ++ dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); ++ dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", dwc2_readl(hsotg->regs + GRXFSIZ)); + + /* Non-periodic Tx FIFO */ + dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + nptxfsiz = params->host_nperio_tx_fifo_size << + FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; + nptxfsiz |= params->host_rx_fifo_size << + FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; +- writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); ++ dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); + dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + + /* Periodic Tx FIFO */ + dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", +- readl(hsotg->regs + HPTXFSIZ)); ++ dwc2_readl(hsotg->regs + HPTXFSIZ)); + hptxfsiz = params->host_perio_tx_fifo_size << + FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; + hptxfsiz |= (params->host_rx_fifo_size + + params->host_nperio_tx_fifo_size) << + FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; +- writel(hptxfsiz, hsotg->regs + HPTXFSIZ); ++ dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); + dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", +- readl(hsotg->regs + HPTXFSIZ)); ++ dwc2_readl(hsotg->regs + HPTXFSIZ)); + + if (hsotg->core_params->en_multiple_tx_fifo > 0 && + hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { +@@ -639,14 +639,14 @@ static void dwc2_config_fifos(struct dwc + * Global DFIFOCFG calculation for Host mode - + * include RxFIFO, NPTXFIFO and HPTXFIFO + */ +- dfifocfg = readl(hsotg->regs + GDFIFOCFG); ++ dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); + dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; + dfifocfg |= (params->host_rx_fifo_size + + params->host_nperio_tx_fifo_size + + params->host_perio_tx_fifo_size) << + GDFIFOCFG_EPINFOBASE_SHIFT & + GDFIFOCFG_EPINFOBASE_MASK; +- writel(dfifocfg, hsotg->regs + GDFIFOCFG); ++ dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); + } + } + +@@ -667,14 +667,14 @@ void dwc2_core_host_init(struct dwc2_hso + dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + /* Restart the Phy Clock */ +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + + /* Initialize Host Configuration Register */ + dwc2_init_fs_ls_pclk_sel(hsotg); + if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg |= HCFG_FSLSSUPP; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + + /* +@@ -683,9 +683,9 @@ void dwc2_core_host_init(struct dwc2_hso + * and its value must not be changed during runtime. + */ + if (hsotg->core_params->reload_ctl > 0) { +- hfir = readl(hsotg->regs + HFIR); ++ hfir = dwc2_readl(hsotg->regs + HFIR); + hfir |= HFIR_RLDCTRL; +- writel(hfir, hsotg->regs + HFIR); ++ dwc2_writel(hfir, hsotg->regs + HFIR); + } + + if (hsotg->core_params->dma_desc_enable > 0) { +@@ -701,9 +701,9 @@ void dwc2_core_host_init(struct dwc2_hso + "falling back to buffer DMA mode.\n"); + hsotg->core_params->dma_desc_enable = 0; + } else { +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg |= HCFG_DESCDMA; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + } + +@@ -712,18 +712,18 @@ void dwc2_core_host_init(struct dwc2_hso + + /* TODO - check this */ + /* Clear Host Set HNP Enable in the OTG Control Register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_HSTSETHNPEN; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + /* Make sure the FIFOs are flushed */ + dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); + dwc2_flush_rx_fifo(hsotg); + + /* Clear Host Set HNP Enable in the OTG Control Register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_HSTSETHNPEN; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + if (hsotg->core_params->dma_desc_enable <= 0) { + int num_channels, i; +@@ -732,25 +732,25 @@ void dwc2_core_host_init(struct dwc2_hso + /* Flush out any leftover queued requests */ + num_channels = hsotg->core_params->host_channels; + for (i = 0; i < num_channels; i++) { +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar &= ~HCCHAR_CHENA; + hcchar |= HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + + /* Halt all channels to put them into a known state */ + for (i = 0; i < num_channels; i++) { + int count = 0; + +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dev_dbg(hsotg->dev, "%s: Halt channel %d\n", + __func__, i); + do { +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (++count > 1000) { + dev_err(hsotg->dev, + "Unable to clear enable on channel %d\n", +@@ -771,7 +771,7 @@ void dwc2_core_host_init(struct dwc2_hso + !!(hprt0 & HPRT0_PWR)); + if (!(hprt0 & HPRT0_PWR)) { + hprt0 |= HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + } + +@@ -851,7 +851,7 @@ static void dwc2_hc_enable_slave_ints(st + break; + } + +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); + } +@@ -888,7 +888,7 @@ static void dwc2_hc_enable_dma_ints(stru + } + } + +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); + } +@@ -909,16 +909,16 @@ static void dwc2_hc_enable_ints(struct d + } + + /* Enable the top level host channel interrupt */ +- intmsk = readl(hsotg->regs + HAINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + HAINTMSK); + intmsk |= 1 << chan->hc_num; +- writel(intmsk, hsotg->regs + HAINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + HAINTMSK); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); + + /* Make sure host channel interrupts are enabled */ +- intmsk = readl(hsotg->regs + GINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk |= GINTSTS_HCHINT; +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); + } +@@ -947,7 +947,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso + /* Clear old interrupt conditions for this host channel */ + hcintmsk = 0xffffffff; + hcintmsk &= ~HCINTMSK_RESERVED14_31; +- writel(hcintmsk, hsotg->regs + HCINT(hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); + + /* Enable channel interrupts required for this transfer */ + dwc2_hc_enable_ints(hsotg, chan); +@@ -964,7 +964,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso + hcchar |= HCCHAR_LSPDDEV; + hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; + hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; +- writel(hcchar, hsotg->regs + HCCHAR(hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", + hc_num, hcchar); +@@ -1018,7 +1018,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso + } + } + +- writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); ++ dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); + } + + /** +@@ -1070,14 +1070,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + u32 hcintmsk = HCINTMSK_CHHLTD; + + dev_vdbg(hsotg->dev, "dequeue/error\n"); +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + + /* + * Make sure no other interrupts besides halt are currently + * pending. Handling another interrupt could cause a crash due + * to the QTD and QH state. + */ +- writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); ++ dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + + /* + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR +@@ -1086,7 +1086,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + */ + chan->halt_status = halt_status; + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + if (!(hcchar & HCCHAR_CHENA)) { + /* + * The channel is either already halted or it hasn't +@@ -1114,7 +1114,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + return; + } + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + + /* No need to set the bit in DDMA for disabling the channel */ + /* TODO check it everywhere channel is disabled */ +@@ -1137,7 +1137,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || + chan->ep_type == USB_ENDPOINT_XFER_BULK) { + dev_vdbg(hsotg->dev, "control/bulk\n"); +- nptxsts = readl(hsotg->regs + GNPTXSTS); ++ nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { + dev_vdbg(hsotg->dev, "Disabling channel\n"); + hcchar &= ~HCCHAR_CHENA; +@@ -1145,7 +1145,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + } else { + if (dbg_perio()) + dev_vdbg(hsotg->dev, "isoc/intr\n"); +- hptxsts = readl(hsotg->regs + HPTXSTS); ++ hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); + if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || + hsotg->queuing_high_bandwidth) { + if (dbg_perio()) +@@ -1158,7 +1158,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + dev_vdbg(hsotg->dev, "DMA enabled\n"); + } + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + chan->halt_status = halt_status; + + if (hcchar & HCCHAR_CHENA) { +@@ -1205,10 +1205,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg * + * Clear channel interrupt enables and any unhandled channel interrupt + * conditions + */ +- writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); + hcintmsk = 0xffffffff; + hcintmsk &= ~HCINTMSK_RESERVED14_31; +- writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + } + + /** +@@ -1294,13 +1294,13 @@ static void dwc2_hc_write_packet(struct + if (((unsigned long)data_buf & 0x3) == 0) { + /* xfer_buf is DWORD aligned */ + for (i = 0; i < dword_count; i++, data_buf++) +- writel(*data_buf, data_fifo); ++ dwc2_writel(*data_buf, data_fifo); + } else { + /* xfer_buf is not DWORD aligned */ + for (i = 0; i < dword_count; i++, data_buf++) { + u32 data = data_buf[0] | data_buf[1] << 8 | + data_buf[2] << 16 | data_buf[3] << 24; +- writel(data, data_fifo); ++ dwc2_writel(data, data_fifo); + } + } + +@@ -1453,7 +1453,7 @@ void dwc2_hc_start_transfer(struct dwc2_ + hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; + hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & + TSIZ_SC_MC_PID_MASK; +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", + hctsiz, chan->hc_num); +@@ -1481,7 +1481,7 @@ void dwc2_hc_start_transfer(struct dwc2_ + } else { + dma_addr = chan->xfer_dma; + } +- writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); ++ dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", + (unsigned long)dma_addr, chan->hc_num); +@@ -1489,13 +1489,13 @@ void dwc2_hc_start_transfer(struct dwc2_ + + /* Start the split */ + if (chan->do_split) { +- u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); ++ u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); + + hcsplt |= HCSPLT_SPLTENA; +- writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); ++ dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); + } + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar &= ~HCCHAR_MULTICNT_MASK; + hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & + HCCHAR_MULTICNT_MASK; +@@ -1515,7 +1515,7 @@ void dwc2_hc_start_transfer(struct dwc2_ + (hcchar & HCCHAR_MULTICNT_MASK) >> + HCCHAR_MULTICNT_SHIFT); + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, + chan->hc_num); +@@ -1574,18 +1574,18 @@ void dwc2_hc_start_transfer_ddma(struct + dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); + } + +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + + hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK; + + /* Always start from first descriptor */ + hc_dma &= ~HCDMA_CTD_MASK; +- writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); ++ dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", + hc_dma, chan->hc_num); + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar &= ~HCCHAR_MULTICNT_MASK; + hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & + HCCHAR_MULTICNT_MASK; +@@ -1604,7 +1604,7 @@ void dwc2_hc_start_transfer_ddma(struct + (hcchar & HCCHAR_MULTICNT_MASK) >> + HCCHAR_MULTICNT_SHIFT); + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, + chan->hc_num); +@@ -1661,7 +1661,7 @@ int dwc2_hc_continue_transfer(struct dwc + * transfer completes, the extra requests for the channel will + * be flushed. + */ +- u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + + dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); + hcchar |= HCCHAR_CHENA; +@@ -1669,7 +1669,7 @@ int dwc2_hc_continue_transfer(struct dwc + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", + hcchar); +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + chan->requests++; + return 1; + } +@@ -1679,7 +1679,7 @@ int dwc2_hc_continue_transfer(struct dwc + if (chan->xfer_count < chan->xfer_len) { + if (chan->ep_type == USB_ENDPOINT_XFER_INT || + chan->ep_type == USB_ENDPOINT_XFER_ISOC) { +- u32 hcchar = readl(hsotg->regs + ++ u32 hcchar = dwc2_readl(hsotg->regs + + HCCHAR(chan->hc_num)); + + dwc2_hc_set_even_odd_frame(hsotg, chan, +@@ -1716,12 +1716,12 @@ void dwc2_hc_do_ping(struct dwc2_hsotg * + + hctsiz = TSIZ_DOPNG; + hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar |= HCCHAR_CHENA; + hcchar &= ~HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + } + + /** +@@ -1740,8 +1740,8 @@ u32 dwc2_calc_frame_interval(struct dwc2 + u32 hprt0; + int clock = 60; /* default value */ + +- usbcfg = readl(hsotg->regs + GUSBCFG); +- hprt0 = readl(hsotg->regs + HPRT0); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && + !(usbcfg & GUSBCFG_PHYIF16)) +@@ -1797,7 +1797,7 @@ void dwc2_read_packet(struct dwc2_hsotg + dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); + + for (i = 0; i < word_count; i++, data_buf++) +- *data_buf = readl(fifo); ++ *data_buf = dwc2_readl(fifo); + } + + /** +@@ -1817,56 +1817,56 @@ void dwc2_dump_host_registers(struct dwc + dev_dbg(hsotg->dev, "Host Global Registers\n"); + addr = hsotg->regs + HCFG; + dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HFIR; + dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HFNUM; + dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HPTXSTS; + dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HAINT; + dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HAINTMSK; + dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + if (hsotg->core_params->dma_desc_enable > 0) { + addr = hsotg->regs + HFLBADDR; + dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + } + + addr = hsotg->regs + HPRT0; + dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + + for (i = 0; i < hsotg->core_params->host_channels; i++) { + dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); + addr = hsotg->regs + HCCHAR(i); + dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCSPLT(i); + dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCINT(i); + dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCINTMSK(i); + dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCTSIZ(i); + dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCDMA(i); + dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + if (hsotg->core_params->dma_desc_enable > 0) { + addr = hsotg->regs + HCDMAB(i); + dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + } + } + #endif +@@ -1888,80 +1888,80 @@ void dwc2_dump_global_registers(struct d + dev_dbg(hsotg->dev, "Core Global Registers\n"); + addr = hsotg->regs + GOTGCTL; + dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GOTGINT; + dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GAHBCFG; + dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GUSBCFG; + dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRSTCTL; + dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GINTSTS; + dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GINTMSK; + dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRXSTSR; + dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRXFSIZ; + dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GNPTXFSIZ; + dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GNPTXSTS; + dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GI2CCTL; + dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GPVNDCTL; + dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GGPIO; + dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GUID; + dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GSNPSID; + dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG1; + dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG2; + dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG3; + dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG4; + dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GLPMCFG; + dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GPWRDN; + dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GDFIFOCFG; + dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HPTXFSIZ; + dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + + addr = hsotg->regs + PCGCTL; + dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + #endif + } + +@@ -1980,15 +1980,15 @@ void dwc2_flush_tx_fifo(struct dwc2_hsot + + greset = GRSTCTL_TXFFLSH; + greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + + do { +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 10000) { + dev_warn(hsotg->dev, + "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", + __func__, greset, +- readl(hsotg->regs + GNPTXSTS)); ++ dwc2_readl(hsotg->regs + GNPTXSTS)); + break; + } + udelay(1); +@@ -2011,10 +2011,10 @@ void dwc2_flush_rx_fifo(struct dwc2_hsot + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + greset = GRSTCTL_RXFFLSH; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + + do { +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 10000) { + dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", + __func__, greset); +@@ -2676,7 +2676,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg + * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", + * as in "OTG version 2.xx" or "OTG version 3.xx". + */ +- hw->snpsid = readl(hsotg->regs + GSNPSID); ++ hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); + if ((hw->snpsid & 0xfffff000) != 0x4f542000 && + (hw->snpsid & 0xfffff000) != 0x4f543000) { + dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", +@@ -2688,11 +2688,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg + hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, + hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); + +- hwcfg1 = readl(hsotg->regs + GHWCFG1); +- hwcfg2 = readl(hsotg->regs + GHWCFG2); +- hwcfg3 = readl(hsotg->regs + GHWCFG3); +- hwcfg4 = readl(hsotg->regs + GHWCFG4); +- grxfsiz = readl(hsotg->regs + GRXFSIZ); ++ hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); ++ hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); ++ hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); ++ hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); ++ grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + + dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); + dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); +@@ -2701,18 +2701,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg + dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); + + /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */ +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg |= GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + usleep_range(100000, 150000); + +- gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ); +- hptxfsiz = readl(hsotg->regs + HPTXFSIZ); ++ gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); ++ hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); + dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); + dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + usleep_range(100000, 150000); + + /* hwcfg2 */ +@@ -2831,7 +2831,7 @@ u16 dwc2_get_otg_version(struct dwc2_hso + + bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) + { +- if (readl(hsotg->regs + GSNPSID) == 0xffffffff) ++ if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) + return false; + else + return true; +@@ -2845,10 +2845,10 @@ bool dwc2_is_controller_alive(struct dwc + */ + void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + ahbcfg |= GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + } + + /** +@@ -2859,10 +2859,10 @@ void dwc2_enable_global_interrupts(struc + */ + void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + } + + MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -44,16 +44,28 @@ + #include + #include "hw.h" + +-#ifdef DWC2_LOG_WRITES +-static inline void do_write(u32 value, void *addr) ++static inline u32 dwc2_readl(const void __iomem *addr) + { +- writel(value, addr); +- pr_info("INFO:: wrote %08x to %p\n", value, addr); ++ u32 value = __raw_readl(addr); ++ ++ /* In order to preserve endianness __raw_* operation is used. Therefore ++ a barrier is needed to ensure IO access is not re-ordered across ++ reads or writes */ ++ mb(); ++ return value; + } + +-#undef writel +-#define writel(v, a) do_write(v, a) ++static inline void dwc2_writel(u32 value, void __iomem *addr) ++{ ++ __raw_writel(value, addr); ++ /* In order to preserve endianness __raw_* operation is used. Therefore ++ a barrier is needed to ensure IO access is not re-ordered across ++ reads or writes */ ++ mb(); ++#ifdef DWC2_LOG_WRITES ++ pr_info("INFO:: wrote %08x to %p\n", value, addr); + #endif ++} + + /* Maximum number of Endpoints/HostChannels */ + #define MAX_EPS_CHANNELS 16 +--- a/drivers/usb/dwc2/core_intr.c ++++ b/drivers/usb/dwc2/core_intr.c +@@ -80,15 +80,15 @@ static const char *dwc2_op_state_str(str + */ + static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) + { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + if (hprt0 & HPRT0_ENACHG) { + hprt0 &= ~HPRT0_ENA; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + /* Clear interrupt */ +- writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); + } + + /** +@@ -102,7 +102,7 @@ static void dwc2_handle_mode_mismatch_in + dwc2_is_host_mode(hsotg) ? "Host" : "Device"); + + /* Clear interrupt */ +- writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); + } + + /** +@@ -117,8 +117,8 @@ static void dwc2_handle_otg_intr(struct + u32 gotgctl; + u32 gintmsk; + +- gotgint = readl(hsotg->regs + GOTGINT); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgint = dwc2_readl(hsotg->regs + GOTGINT); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, + dwc2_op_state_str(hsotg)); + +@@ -126,7 +126,7 @@ static void dwc2_handle_otg_intr(struct + dev_dbg(hsotg->dev, + " ++OTG Interrupt: Session End Detected++ (%s)\n", + dwc2_op_state_str(hsotg)); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + + if (hsotg->op_state == OTG_STATE_B_HOST) { + hsotg->op_state = OTG_STATE_B_PERIPHERAL; +@@ -149,15 +149,15 @@ static void dwc2_handle_otg_intr(struct + hsotg->lx_state = DWC2_L0; + } + +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~GOTGCTL_DEVHNPEN; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + } + + if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { + dev_dbg(hsotg->dev, + " ++OTG Interrupt: Session Request Success Status Change++\n"); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + if (gotgctl & GOTGCTL_SESREQSCS) { + if (hsotg->core_params->phy_type == + DWC2_PHY_TYPE_PARAM_FS +@@ -165,9 +165,9 @@ static void dwc2_handle_otg_intr(struct + hsotg->srp_success = 1; + } else { + /* Clear Session Request */ +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~GOTGCTL_SESREQ; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + } + } + } +@@ -177,7 +177,7 @@ static void dwc2_handle_otg_intr(struct + * Print statements during the HNP interrupt handling + * can cause it to fail + */ +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + /* + * WA for 3.00a- HW is not setting cur_mode, even sometimes + * this does not help +@@ -197,9 +197,9 @@ static void dwc2_handle_otg_intr(struct + * interrupt does not get handled and Linux + * complains loudly. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + + /* + * Call callback function with spin lock +@@ -213,9 +213,9 @@ static void dwc2_handle_otg_intr(struct + hsotg->op_state = OTG_STATE_B_HOST; + } + } else { +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "HNP Failed\n"); + dev_err(hsotg->dev, + "Device Not Connected/Responding\n"); +@@ -241,9 +241,9 @@ static void dwc2_handle_otg_intr(struct + hsotg->op_state = OTG_STATE_A_PERIPHERAL; + } else { + /* Need to disable SOF interrupt immediately */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + spin_unlock(&hsotg->lock); + dwc2_hcd_start(hsotg); + spin_lock(&hsotg->lock); +@@ -258,7 +258,7 @@ static void dwc2_handle_otg_intr(struct + dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); + + /* Clear GOTGINT */ +- writel(gotgint, hsotg->regs + GOTGINT); ++ dwc2_writel(gotgint, hsotg->regs + GOTGINT); + } + + /** +@@ -273,11 +273,11 @@ static void dwc2_handle_otg_intr(struct + */ + static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) + { +- u32 gintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + /* Need to disable SOF interrupt immediately */ + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + + dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", + dwc2_is_host_mode(hsotg) ? "Host" : "Device"); +@@ -292,7 +292,7 @@ static void dwc2_handle_conn_id_status_c + spin_lock(&hsotg->lock); + + /* Clear interrupt */ +- writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); + } + + /** +@@ -311,7 +311,7 @@ static void dwc2_handle_session_req_intr + dev_dbg(hsotg->dev, "++Session Request Interrupt++\n"); + + /* Clear interrupt */ +- writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); + } + + /* +@@ -327,23 +327,23 @@ static void dwc2_handle_wakeup_detected_ + dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); + + if (dwc2_is_device_mode(hsotg)) { +- dev_dbg(hsotg->dev, "DSTS=0x%0x\n", readl(hsotg->regs + DSTS)); ++ dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dwc2_readl(hsotg->regs + DSTS)); + if (hsotg->lx_state == DWC2_L2) { +- u32 dctl = readl(hsotg->regs + DCTL); ++ u32 dctl = dwc2_readl(hsotg->regs + DCTL); + + /* Clear Remote Wakeup Signaling */ + dctl &= ~DCTL_RMTWKUPSIG; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + /* Change to L0 state */ + hsotg->lx_state = DWC2_L0; + } else { + if (hsotg->lx_state != DWC2_L1) { +- u32 pcgcctl = readl(hsotg->regs + PCGCTL); ++ u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + + /* Restart the Phy Clock */ + pcgcctl &= ~PCGCTL_STOPPCLK; +- writel(pcgcctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + mod_timer(&hsotg->wkp_timer, + jiffies + msecs_to_jiffies(71)); + } else { +@@ -353,7 +353,7 @@ static void dwc2_handle_wakeup_detected_ + } + + /* Clear interrupt */ +- writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); + } + + /* +@@ -369,7 +369,7 @@ static void dwc2_handle_disconnect_intr( + /* Change to L3 (OFF) state */ + hsotg->lx_state = DWC2_L3; + +- writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); + } + + /* +@@ -391,7 +391,7 @@ static void dwc2_handle_usb_suspend_intr + * Check the Device status register to determine if the Suspend + * state is active + */ +- dsts = readl(hsotg->regs + DSTS); ++ dsts = dwc2_readl(hsotg->regs + DSTS); + dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); + dev_dbg(hsotg->dev, + "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", +@@ -413,7 +413,7 @@ static void dwc2_handle_usb_suspend_intr + hsotg->lx_state = DWC2_L2; + + /* Clear interrupt */ +- writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); + } + + #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ +@@ -431,9 +431,9 @@ static u32 dwc2_read_common_intr(struct + u32 gahbcfg; + u32 gintmsk_common = GINTMSK_COMMON; + +- gintsts = readl(hsotg->regs + GINTSTS); +- gintmsk = readl(hsotg->regs + GINTMSK); +- gahbcfg = readl(hsotg->regs + GAHBCFG); ++ gintsts = dwc2_readl(hsotg->regs + GINTSTS); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); ++ gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + /* If any common interrupts set */ + if (gintsts & gintmsk_common) +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -55,12 +55,12 @@ static inline struct s3c_hsotg *to_hsotg + + static inline void __orr32(void __iomem *ptr, u32 val) + { +- writel(readl(ptr) | val, ptr); ++ dwc2_writel(dwc2_readl(ptr) | val, ptr); + } + + static inline void __bic32(void __iomem *ptr, u32 val) + { +- writel(readl(ptr) & ~val, ptr); ++ dwc2_writel(dwc2_readl(ptr) & ~val, ptr); + } + + /* forward decleration of functions */ +@@ -97,14 +97,14 @@ static inline bool using_dma(struct s3c_ + */ + static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints) + { +- u32 gsintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 new_gsintmsk; + + new_gsintmsk = gsintmsk | ints; + + if (new_gsintmsk != gsintmsk) { + dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); +- writel(new_gsintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); + } + } + +@@ -115,13 +115,13 @@ static void s3c_hsotg_en_gsint(struct s3 + */ + static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints) + { +- u32 gsintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 new_gsintmsk; + + new_gsintmsk = gsintmsk & ~ints; + + if (new_gsintmsk != gsintmsk) +- writel(new_gsintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); + } + + /** +@@ -146,12 +146,12 @@ static void s3c_hsotg_ctrl_epint(struct + bit <<= 16; + + local_irq_save(flags); +- daint = readl(hsotg->regs + DAINTMSK); ++ daint = dwc2_readl(hsotg->regs + DAINTMSK); + if (en) + daint |= bit; + else + daint &= ~bit; +- writel(daint, hsotg->regs + DAINTMSK); ++ dwc2_writel(daint, hsotg->regs + DAINTMSK); + local_irq_restore(flags); + } + +@@ -169,8 +169,8 @@ static void s3c_hsotg_init_fifo(struct s + + /* set FIFO sizes to 2048/1024 */ + +- writel(2048, hsotg->regs + GRXFSIZ); +- writel((2048 << FIFOSIZE_STARTADDR_SHIFT) | ++ dwc2_writel(2048, hsotg->regs + GRXFSIZ); ++ dwc2_writel((2048 << FIFOSIZE_STARTADDR_SHIFT) | + (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ); + + /* +@@ -200,7 +200,7 @@ static void s3c_hsotg_init_fifo(struct s + "insufficient fifo memory"); + addr += size; + +- writel(val, hsotg->regs + DPTXFSIZN(ep)); ++ dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); + } + /* 768*4=3072 bytes FIFO length */ + size = 768; +@@ -211,7 +211,7 @@ static void s3c_hsotg_init_fifo(struct s + "insufficient fifo memory"); + addr += size; + +- writel(val, hsotg->regs + DPTXFSIZN(ep)); ++ dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); + } + + /* +@@ -219,13 +219,13 @@ static void s3c_hsotg_init_fifo(struct s + * all fifos are flushed before continuing + */ + +- writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | ++ dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | + GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); + + /* wait until the fifos are both flushed */ + timeout = 100; + while (1) { +- val = readl(hsotg->regs + GRSTCTL); ++ val = dwc2_readl(hsotg->regs + GRSTCTL); + + if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) + break; +@@ -317,7 +317,7 @@ static int s3c_hsotg_write_fifo(struct s + struct s3c_hsotg_req *hs_req) + { + bool periodic = is_ep_periodic(hs_ep); +- u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); ++ u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + int buf_pos = hs_req->req.actual; + int to_write = hs_ep->size_loaded; + void *data; +@@ -332,7 +332,7 @@ static int s3c_hsotg_write_fifo(struct s + return 0; + + if (periodic && !hsotg->dedicated_fifos) { +- u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); ++ u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); + int size_left; + int size_done; + +@@ -373,7 +373,7 @@ static int s3c_hsotg_write_fifo(struct s + return -ENOSPC; + } + } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { +- can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); ++ can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index)); + + can_write &= 0xffff; + can_write *= 4; +@@ -550,11 +550,11 @@ static void s3c_hsotg_start_req(struct s + epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", +- __func__, readl(hsotg->regs + epctrl_reg), index, ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, + hs_ep->dir_in ? "in" : "out"); + + /* If endpoint is stalled, we will restart request later */ +- ctrl = readl(hsotg->regs + epctrl_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctrl_reg); + + if (ctrl & DXEPCTL_STALL) { + dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); +@@ -622,7 +622,7 @@ static void s3c_hsotg_start_req(struct s + hs_ep->req = hs_req; + + /* write size / packets */ +- writel(epsize, hsotg->regs + epsize_reg); ++ dwc2_writel(epsize, hsotg->regs + epsize_reg); + + if (using_dma(hsotg) && !continuing) { + unsigned int dma_reg; +@@ -633,7 +633,7 @@ static void s3c_hsotg_start_req(struct s + */ + + dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); +- writel(ureq->dma, hsotg->regs + dma_reg); ++ dwc2_writel(ureq->dma, hsotg->regs + dma_reg); + + dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", + __func__, &ureq->dma, dma_reg); +@@ -652,7 +652,7 @@ static void s3c_hsotg_start_req(struct s + + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); +- writel(ctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctrl_reg); + + /* + * set these, it seems that DMA support increments past the end +@@ -674,7 +674,7 @@ static void s3c_hsotg_start_req(struct s + * to debugging to see what is going on. + */ + if (dir_in) +- writel(DIEPMSK_INTKNTXFEMPMSK, ++ dwc2_writel(DIEPMSK_INTKNTXFEMPMSK, + hsotg->regs + DIEPINT(index)); + + /* +@@ -683,13 +683,13 @@ static void s3c_hsotg_start_req(struct s + */ + + /* check ep is enabled */ +- if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) ++ if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) + dev_warn(hsotg->dev, + "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", +- index, readl(hsotg->regs + epctrl_reg)); ++ index, dwc2_readl(hsotg->regs + epctrl_reg)); + + dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", +- __func__, readl(hsotg->regs + epctrl_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg)); + + /* enable ep interrupts */ + s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); +@@ -1051,14 +1051,14 @@ static void s3c_hsotg_stall_ep0(struct s + * taken effect, so no need to clear later. + */ + +- ctrl = readl(hsotg->regs + reg); ++ ctrl = dwc2_readl(hsotg->regs + reg); + ctrl |= DXEPCTL_STALL; + ctrl |= DXEPCTL_CNAK; +- writel(ctrl, hsotg->regs + reg); ++ dwc2_writel(ctrl, hsotg->regs + reg); + + dev_dbg(hsotg->dev, + "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", +- ctrl, reg, readl(hsotg->regs + reg)); ++ ctrl, reg, dwc2_readl(hsotg->regs + reg)); + + /* + * complete won't be called, so we enqueue +@@ -1108,11 +1108,11 @@ static void s3c_hsotg_process_control(st + switch (ctrl->bRequest) { + case USB_REQ_SET_ADDRESS: + s3c_hsotg_disconnect(hsotg); +- dcfg = readl(hsotg->regs + DCFG); ++ dcfg = dwc2_readl(hsotg->regs + DCFG); + dcfg &= ~DCFG_DEVADDR_MASK; + dcfg |= (le16_to_cpu(ctrl->wValue) << + DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; +- writel(dcfg, hsotg->regs + DCFG); ++ dwc2_writel(dcfg, hsotg->regs + DCFG); + + dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); + +@@ -1302,7 +1302,7 @@ static void s3c_hsotg_rx_data(struct s3c + + + if (!hs_req) { +- u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); ++ u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); + int ptr; + + dev_warn(hsotg->dev, +@@ -1311,7 +1311,7 @@ static void s3c_hsotg_rx_data(struct s3c + + /* dump the data from the FIFO, we've nothing we can do */ + for (ptr = 0; ptr < size; ptr += 4) +- (void)readl(fifo); ++ (void)dwc2_readl(fifo); + + return; + } +@@ -1378,14 +1378,14 @@ static void s3c_hsotg_send_zlp(struct s3 + dev_dbg(hsotg->dev, "sending zero-length packet\n"); + + /* issue a zero-sized packet to terminate this */ +- writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | ++ dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0)); + +- ctrl = readl(hsotg->regs + DIEPCTL0); ++ ctrl = dwc2_readl(hsotg->regs + DIEPCTL0); + ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ + ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ + ctrl |= DXEPCTL_USBACTEP; +- writel(ctrl, hsotg->regs + DIEPCTL0); ++ dwc2_writel(ctrl, hsotg->regs + DIEPCTL0); + } + + /** +@@ -1401,7 +1401,7 @@ static void s3c_hsotg_send_zlp(struct s3 + static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg, + int epnum, bool was_setup) + { +- u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); ++ u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); + struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum]; + struct s3c_hsotg_req *hs_req = hs_ep->req; + struct usb_request *req = &hs_req->req; +@@ -1475,7 +1475,7 @@ static u32 s3c_hsotg_read_frameno(struct + { + u32 dsts; + +- dsts = readl(hsotg->regs + DSTS); ++ dsts = dwc2_readl(hsotg->regs + DSTS); + dsts &= DSTS_SOFFN_MASK; + dsts >>= DSTS_SOFFN_SHIFT; + +@@ -1500,7 +1500,7 @@ static u32 s3c_hsotg_read_frameno(struct + */ + static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg) + { +- u32 grxstsr = readl(hsotg->regs + GRXSTSP); ++ u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); + u32 epnum, status, size; + + WARN_ON(using_dma(hsotg)); +@@ -1532,7 +1532,7 @@ static void s3c_hsotg_handle_rx(struct s + dev_dbg(hsotg->dev, + "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", + s3c_hsotg_read_frameno(hsotg), +- readl(hsotg->regs + DOEPCTL(0))); ++ dwc2_readl(hsotg->regs + DOEPCTL(0))); + + s3c_hsotg_handle_outdone(hsotg, epnum, true); + break; +@@ -1545,7 +1545,7 @@ static void s3c_hsotg_handle_rx(struct s + dev_dbg(hsotg->dev, + "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", + s3c_hsotg_read_frameno(hsotg), +- readl(hsotg->regs + DOEPCTL(0))); ++ dwc2_readl(hsotg->regs + DOEPCTL(0))); + + s3c_hsotg_rx_data(hsotg, epnum, size); + break; +@@ -1622,16 +1622,16 @@ static void s3c_hsotg_set_ep_maxpacket(s + * if one of the directions may not be in use. + */ + +- reg = readl(regs + DIEPCTL(ep)); ++ reg = dwc2_readl(regs + DIEPCTL(ep)); + reg &= ~DXEPCTL_MPS_MASK; + reg |= mpsval; +- writel(reg, regs + DIEPCTL(ep)); ++ dwc2_writel(reg, regs + DIEPCTL(ep)); + + if (ep) { +- reg = readl(regs + DOEPCTL(ep)); ++ reg = dwc2_readl(regs + DOEPCTL(ep)); + reg &= ~DXEPCTL_MPS_MASK; + reg |= mpsval; +- writel(reg, regs + DOEPCTL(ep)); ++ dwc2_writel(reg, regs + DOEPCTL(ep)); + } + + return; +@@ -1650,14 +1650,14 @@ static void s3c_hsotg_txfifo_flush(struc + int timeout; + int val; + +- writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, ++ dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, + hsotg->regs + GRSTCTL); + + /* wait until the fifo is flushed */ + timeout = 100; + + while (1) { +- val = readl(hsotg->regs + GRSTCTL); ++ val = dwc2_readl(hsotg->regs + GRSTCTL); + + if ((val & (GRSTCTL_TXFFLSH)) == 0) + break; +@@ -1718,7 +1718,7 @@ static void s3c_hsotg_complete_in(struct + struct s3c_hsotg_ep *hs_ep) + { + struct s3c_hsotg_req *hs_req = hs_ep->req; +- u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); ++ u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); + int size_left, size_done; + + if (!hs_req) { +@@ -1801,11 +1801,11 @@ static void s3c_hsotg_epint(struct s3c_h + u32 ints; + u32 ctrl; + +- ints = readl(hsotg->regs + epint_reg); +- ctrl = readl(hsotg->regs + epctl_reg); ++ ints = dwc2_readl(hsotg->regs + epint_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctl_reg); + + /* Clear endpoint interrupts */ +- writel(ints, hsotg->regs + epint_reg); ++ dwc2_writel(ints, hsotg->regs + epint_reg); + + dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", + __func__, idx, dir_in ? "in" : "out", ints); +@@ -1816,13 +1816,13 @@ static void s3c_hsotg_epint(struct s3c_h + ctrl |= DXEPCTL_SETEVENFR; + else + ctrl |= DXEPCTL_SETODDFR; +- writel(ctrl, hsotg->regs + epctl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctl_reg); + } + + dev_dbg(hsotg->dev, + "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", +- __func__, readl(hsotg->regs + epctl_reg), +- readl(hsotg->regs + epsiz_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctl_reg), ++ dwc2_readl(hsotg->regs + epsiz_reg)); + + /* + * we get OutDone from the FIFO, so we only need to look +@@ -1847,16 +1847,16 @@ static void s3c_hsotg_epint(struct s3c_h + dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); + + if (dir_in) { +- int epctl = readl(hsotg->regs + epctl_reg); ++ int epctl = dwc2_readl(hsotg->regs + epctl_reg); + + s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); + + if ((epctl & DXEPCTL_STALL) && + (epctl & DXEPCTL_EPTYPE_BULK)) { +- int dctl = readl(hsotg->regs + DCTL); ++ int dctl = dwc2_readl(hsotg->regs + DCTL); + + dctl |= DCTL_CGNPINNAK; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + } + } +@@ -1918,7 +1918,7 @@ static void s3c_hsotg_epint(struct s3c_h + */ + static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg) + { +- u32 dsts = readl(hsotg->regs + DSTS); ++ u32 dsts = dwc2_readl(hsotg->regs + DSTS); + int ep0_mps = 0, ep_mps = 8; + + /* +@@ -1979,8 +1979,8 @@ static void s3c_hsotg_irq_enumdone(struc + s3c_hsotg_enqueue_setup(hsotg); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + } + + /** +@@ -2014,7 +2014,7 @@ static void kill_all_requests(struct s3c + } + if (!hsotg->dedicated_fifos) + return; +- size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; ++ size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; + if (size < ep->fifo_size) + s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index); + } +@@ -2084,11 +2084,11 @@ static int s3c_hsotg_corereset(struct s3 + dev_dbg(hsotg->dev, "resetting core\n"); + + /* issue soft reset */ +- writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); ++ dwc2_writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); + + timeout = 10000; + do { +- grstctl = readl(hsotg->regs + GRSTCTL); ++ grstctl = dwc2_readl(hsotg->regs + GRSTCTL); + } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); + + if (grstctl & GRSTCTL_CSFTRST) { +@@ -2099,7 +2099,7 @@ static int s3c_hsotg_corereset(struct s3 + timeout = 10000; + + while (1) { +- u32 grstctl = readl(hsotg->regs + GRSTCTL); ++ u32 grstctl = dwc2_readl(hsotg->regs + GRSTCTL); + + if (timeout-- < 0) { + dev_info(hsotg->dev, +@@ -2134,22 +2134,22 @@ static void s3c_hsotg_core_init(struct s + */ + + /* set the PLL on, remove the HNP/SRP and set the PHY */ +- writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | ++ dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | + (0x5 << 10), hsotg->regs + GUSBCFG); + + s3c_hsotg_init_fifo(hsotg); + + __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); + +- writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); ++ dwc2_writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); + + /* Clear any pending OTG interrupts */ +- writel(0xffffffff, hsotg->regs + GOTGINT); ++ dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + + /* Clear any pending interrupts */ +- writel(0xffffffff, hsotg->regs + GINTSTS); ++ dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + +- writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | ++ dwc2_writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | + GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | + GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | + GINTSTS_ENUMDONE | GINTSTS_OTGINT | +@@ -2157,11 +2157,11 @@ static void s3c_hsotg_core_init(struct s + hsotg->regs + GINTMSK); + + if (using_dma(hsotg)) +- writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | ++ dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | + GAHBCFG_HBSTLEN_INCR4, + hsotg->regs + GAHBCFG); + else +- writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | ++ dwc2_writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | + GAHBCFG_P_TXF_EMP_LVL) : 0) | + GAHBCFG_GLBL_INTR_EN, + hsotg->regs + GAHBCFG); +@@ -2172,7 +2172,7 @@ static void s3c_hsotg_core_init(struct s + * interrupts. + */ + +- writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY | ++ dwc2_writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY | + DIEPMSK_INTKNTXFEMPMSK : 0) | + DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | + DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | +@@ -2183,17 +2183,17 @@ static void s3c_hsotg_core_init(struct s + * don't need XferCompl, we get that from RXFIFO in slave mode. In + * DMA mode we may need this. + */ +- writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | ++ dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | + DIEPMSK_TIMEOUTMSK) : 0) | + DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | + DOEPMSK_SETUPMSK, + hsotg->regs + DOEPMSK); + +- writel(0, hsotg->regs + DAINTMSK); ++ dwc2_writel(0, hsotg->regs + DAINTMSK); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + + /* enable in and out endpoint interrupts */ + s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); +@@ -2214,7 +2214,7 @@ static void s3c_hsotg_core_init(struct s + udelay(10); /* see openiboot */ + __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); + +- dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); ++ dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); + + /* + * DxEPCTL_USBActEp says RO in manual, but seems to be set by +@@ -2222,26 +2222,26 @@ static void s3c_hsotg_core_init(struct s + */ + + /* set to read 1 8byte packet */ +- writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | ++ dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); + +- writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | ++ dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | + DXEPCTL_CNAK | DXEPCTL_EPENA | + DXEPCTL_USBACTEP, + hsotg->regs + DOEPCTL0); + + /* enable, but don't activate EP0in */ +- writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | ++ dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | + DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); + + s3c_hsotg_enqueue_setup(hsotg); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + + /* clear global NAKs */ +- writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK, ++ dwc2_writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK, + hsotg->regs + DCTL); + + /* must be at-least 3ms to allow bus to see disconnect */ +@@ -2265,8 +2265,8 @@ static irqreturn_t s3c_hsotg_irq(int irq + + spin_lock(&hsotg->lock); + irq_retry: +- gintsts = readl(hsotg->regs + GINTSTS); +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintsts = dwc2_readl(hsotg->regs + GINTSTS); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", + __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); +@@ -2274,35 +2274,35 @@ irq_retry: + gintsts &= gintmsk; + + if (gintsts & GINTSTS_OTGINT) { +- u32 otgint = readl(hsotg->regs + GOTGINT); ++ u32 otgint = dwc2_readl(hsotg->regs + GOTGINT); + + dev_info(hsotg->dev, "OTGInt: %08x\n", otgint); + +- writel(otgint, hsotg->regs + GOTGINT); ++ dwc2_writel(otgint, hsotg->regs + GOTGINT); + } + + if (gintsts & GINTSTS_SESSREQINT) { + dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__); +- writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); + } + + if (gintsts & GINTSTS_ENUMDONE) { +- writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); + + s3c_hsotg_irq_enumdone(hsotg); + } + + if (gintsts & GINTSTS_CONIDSTSCHNG) { + dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n", +- readl(hsotg->regs + DSTS), +- readl(hsotg->regs + GOTGCTL)); ++ dwc2_readl(hsotg->regs + DSTS), ++ dwc2_readl(hsotg->regs + GOTGCTL)); + +- writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); + } + + if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { +- u32 daint = readl(hsotg->regs + DAINT); +- u32 daintmsk = readl(hsotg->regs + DAINTMSK); ++ u32 daint = dwc2_readl(hsotg->regs + DAINT); ++ u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); + u32 daint_out, daint_in; + int ep; + +@@ -2325,13 +2325,13 @@ irq_retry: + + if (gintsts & GINTSTS_USBRST) { + +- u32 usb_status = readl(hsotg->regs + GOTGCTL); ++ u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); + + dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); + dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", +- readl(hsotg->regs + GNPTXSTS)); ++ dwc2_readl(hsotg->regs + GNPTXSTS)); + +- writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); + + if (usb_status & GOTGCTL_BSESVLD) { + if (time_after(jiffies, hsotg->last_rst + +@@ -2382,26 +2382,26 @@ irq_retry: + + if (gintsts & GINTSTS_MODEMIS) { + dev_warn(hsotg->dev, "warning, mode mismatch triggered\n"); +- writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); + } + + if (gintsts & GINTSTS_USBSUSP) { + dev_info(hsotg->dev, "GINTSTS_USBSusp\n"); +- writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); + + call_gadget(hsotg, suspend); + } + + if (gintsts & GINTSTS_WKUPINT) { + dev_info(hsotg->dev, "GINTSTS_WkUpIn\n"); +- writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); + + call_gadget(hsotg, resume); + } + + if (gintsts & GINTSTS_ERLYSUSP) { + dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); +- writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); + } + + /* +@@ -2413,7 +2413,7 @@ irq_retry: + if (gintsts & GINTSTS_GOUTNAKEFF) { + dev_info(hsotg->dev, "GOUTNakEff triggered\n"); + +- writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); ++ dwc2_writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); + + s3c_hsotg_dump(hsotg); + } +@@ -2421,7 +2421,7 @@ irq_retry: + if (gintsts & GINTSTS_GINNAKEFF) { + dev_info(hsotg->dev, "GINNakEff triggered\n"); + +- writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); ++ dwc2_writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); + + s3c_hsotg_dump(hsotg); + } +@@ -2479,7 +2479,7 @@ static int s3c_hsotg_ep_enable(struct us + /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ + + epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); +- epctrl = readl(hsotg->regs + epctrl_reg); ++ epctrl = dwc2_readl(hsotg->regs + epctrl_reg); + + dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", + __func__, epctrl, epctrl_reg); +@@ -2550,7 +2550,7 @@ static int s3c_hsotg_ep_enable(struct us + for (i = 1; i <= 8; ++i) { + if (hsotg->fifo_map & (1<regs + DPTXFSIZN(i)); ++ val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); + val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; + if (val < size) + continue; +@@ -2574,9 +2574,9 @@ static int s3c_hsotg_ep_enable(struct us + dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", + __func__, epctrl); + +- writel(epctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(epctrl, hsotg->regs + epctrl_reg); + dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", +- __func__, readl(hsotg->regs + epctrl_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg)); + + /* enable the endpoint interrupt */ + s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); +@@ -2617,13 +2617,13 @@ static int s3c_hsotg_ep_disable(struct u + hs_ep->fifo_index = 0; + hs_ep->fifo_size = 0; + +- ctrl = readl(hsotg->regs + epctrl_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctrl_reg); + ctrl &= ~DXEPCTL_EPENA; + ctrl &= ~DXEPCTL_USBACTEP; + ctrl |= DXEPCTL_SNAK; + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); +- writel(ctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctrl_reg); + + /* disable endpoint interrupts */ + s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); +@@ -2704,7 +2704,7 @@ static int s3c_hsotg_ep_sethalt(struct u + /* write both IN and OUT control registers */ + + epreg = DIEPCTL(index); +- epctl = readl(hs->regs + epreg); ++ epctl = dwc2_readl(hs->regs + epreg); + + if (value) { + epctl |= DXEPCTL_STALL + DXEPCTL_SNAK; +@@ -2718,10 +2718,10 @@ static int s3c_hsotg_ep_sethalt(struct u + epctl |= DXEPCTL_SETD0PID; + } + +- writel(epctl, hs->regs + epreg); ++ dwc2_writel(epctl, hs->regs + epreg); + + epreg = DOEPCTL(index); +- epctl = readl(hs->regs + epreg); ++ epctl = dwc2_readl(hs->regs + epreg); + + if (value) + epctl |= DXEPCTL_STALL; +@@ -2733,7 +2733,7 @@ static int s3c_hsotg_ep_sethalt(struct u + epctl |= DXEPCTL_SETD0PID; + } + +- writel(epctl, hs->regs + epreg); ++ dwc2_writel(epctl, hs->regs + epreg); + + hs_ep->halted = value; + +@@ -2822,38 +2822,38 @@ static void s3c_hsotg_init(struct s3c_hs + { + /* unmask subset of endpoint interrupts */ + +- writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | ++ dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | + DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, + hsotg->regs + DIEPMSK); + +- writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | ++ dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | + DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, + hsotg->regs + DOEPMSK); + +- writel(0, hsotg->regs + DAINTMSK); ++ dwc2_writel(0, hsotg->regs + DAINTMSK); + + /* Be in disconnected state until gadget is registered */ + __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); + + if (0) { + /* post global nak until we're ready */ +- writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK, ++ dwc2_writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK, + hsotg->regs + DCTL); + } + + /* setup fifos */ + + dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", +- readl(hsotg->regs + GRXFSIZ), +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GRXFSIZ), ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + + s3c_hsotg_init_fifo(hsotg); + + /* set the PLL on, remove the HNP/SRP and set the PHY */ +- writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), ++ dwc2_writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), + hsotg->regs + GUSBCFG); + +- writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0, ++ dwc2_writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0, + hsotg->regs + GAHBCFG); + } + +@@ -3045,8 +3045,8 @@ static void s3c_hsotg_initep(struct s3c_ + + if (using_dma(hsotg)) { + u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); +- writel(next, hsotg->regs + DIEPCTL(epnum)); +- writel(next, hsotg->regs + DOEPCTL(epnum)); ++ dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); ++ dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); + } + } + +@@ -3061,13 +3061,13 @@ static void s3c_hsotg_hw_cfg(struct s3c_ + u32 cfg2, cfg3, cfg4; + /* check hardware configuration */ + +- cfg2 = readl(hsotg->regs + 0x48); ++ cfg2 = dwc2_readl(hsotg->regs + 0x48); + hsotg->num_of_eps = (cfg2 >> 10) & 0xF; + +- cfg3 = readl(hsotg->regs + 0x4C); ++ cfg3 = dwc2_readl(hsotg->regs + 0x4C); + hsotg->fifo_mem = (cfg3 >> 16); + +- cfg4 = readl(hsotg->regs + 0x50); ++ cfg4 = dwc2_readl(hsotg->regs + 0x50); + hsotg->dedicated_fifos = (cfg4 >> 25) & 1; + + dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", +@@ -3089,19 +3089,19 @@ static void s3c_hsotg_dump(struct s3c_hs + int idx; + + dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", +- readl(regs + DCFG), readl(regs + DCTL), +- readl(regs + DIEPMSK)); ++ dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), ++ dwc2_readl(regs + DIEPMSK)); + + dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", +- readl(regs + GAHBCFG), readl(regs + 0x44)); ++ dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + 0x44)); + + dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", +- readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); ++ dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); + + /* show periodic fifo settings */ + + for (idx = 1; idx <= 15; idx++) { +- val = readl(regs + DPTXFSIZN(idx)); ++ val = dwc2_readl(regs + DPTXFSIZN(idx)); + dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, + val >> FIFOSIZE_DEPTH_SHIFT, + val & FIFOSIZE_STARTADDR_MASK); +@@ -3110,21 +3110,21 @@ static void s3c_hsotg_dump(struct s3c_hs + for (idx = 0; idx < 15; idx++) { + dev_info(dev, + "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, +- readl(regs + DIEPCTL(idx)), +- readl(regs + DIEPTSIZ(idx)), +- readl(regs + DIEPDMA(idx))); ++ dwc2_readl(regs + DIEPCTL(idx)), ++ dwc2_readl(regs + DIEPTSIZ(idx)), ++ dwc2_readl(regs + DIEPDMA(idx))); + +- val = readl(regs + DOEPCTL(idx)); ++ val = dwc2_readl(regs + DOEPCTL(idx)); + dev_info(dev, + "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", +- idx, readl(regs + DOEPCTL(idx)), +- readl(regs + DOEPTSIZ(idx)), +- readl(regs + DOEPDMA(idx))); ++ idx, dwc2_readl(regs + DOEPCTL(idx)), ++ dwc2_readl(regs + DOEPTSIZ(idx)), ++ dwc2_readl(regs + DOEPDMA(idx))); + + } + + dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", +- readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); ++ dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); + #endif + } + +@@ -3144,38 +3144,38 @@ static int state_show(struct seq_file *s + int idx; + + seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", +- readl(regs + DCFG), +- readl(regs + DCTL), +- readl(regs + DSTS)); ++ dwc2_readl(regs + DCFG), ++ dwc2_readl(regs + DCTL), ++ dwc2_readl(regs + DSTS)); + + seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", +- readl(regs + DIEPMSK), readl(regs + DOEPMSK)); ++ dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK)); + + seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", +- readl(regs + GINTMSK), +- readl(regs + GINTSTS)); ++ dwc2_readl(regs + GINTMSK), ++ dwc2_readl(regs + GINTSTS)); + + seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", +- readl(regs + DAINTMSK), +- readl(regs + DAINT)); ++ dwc2_readl(regs + DAINTMSK), ++ dwc2_readl(regs + DAINT)); + + seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", +- readl(regs + GNPTXSTS), +- readl(regs + GRXSTSR)); ++ dwc2_readl(regs + GNPTXSTS), ++ dwc2_readl(regs + GRXSTSR)); + + seq_puts(seq, "\nEndpoint status:\n"); + + for (idx = 0; idx < 15; idx++) { + u32 in, out; + +- in = readl(regs + DIEPCTL(idx)); +- out = readl(regs + DOEPCTL(idx)); ++ in = dwc2_readl(regs + DIEPCTL(idx)); ++ out = dwc2_readl(regs + DOEPCTL(idx)); + + seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", + idx, in, out); + +- in = readl(regs + DIEPTSIZ(idx)); +- out = readl(regs + DOEPTSIZ(idx)); ++ in = dwc2_readl(regs + DIEPTSIZ(idx)); ++ out = dwc2_readl(regs + DOEPTSIZ(idx)); + + seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", + in, out); +@@ -3215,9 +3215,9 @@ static int fifo_show(struct seq_file *se + int idx; + + seq_puts(seq, "Non-periodic FIFOs:\n"); +- seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); ++ seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ)); + +- val = readl(regs + GNPTXFSIZ); ++ val = dwc2_readl(regs + GNPTXFSIZ); + seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", + val >> FIFOSIZE_DEPTH_SHIFT, + val & FIFOSIZE_DEPTH_MASK); +@@ -3225,7 +3225,7 @@ static int fifo_show(struct seq_file *se + seq_puts(seq, "\nPeriodic TXFIFOs:\n"); + + for (idx = 1; idx <= 15; idx++) { +- val = readl(regs + DPTXFSIZN(idx)); ++ val = dwc2_readl(regs + DPTXFSIZN(idx)); + + seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, + val >> FIFOSIZE_DEPTH_SHIFT, +@@ -3278,20 +3278,20 @@ static int ep_show(struct seq_file *seq, + /* first show the register state */ + + seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", +- readl(regs + DIEPCTL(index)), +- readl(regs + DOEPCTL(index))); ++ dwc2_readl(regs + DIEPCTL(index)), ++ dwc2_readl(regs + DOEPCTL(index))); + + seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", +- readl(regs + DIEPDMA(index)), +- readl(regs + DOEPDMA(index))); ++ dwc2_readl(regs + DIEPDMA(index)), ++ dwc2_readl(regs + DOEPDMA(index))); + + seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", +- readl(regs + DIEPINT(index)), +- readl(regs + DOEPINT(index))); ++ dwc2_readl(regs + DIEPINT(index)), ++ dwc2_readl(regs + DOEPINT(index))); + + seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", +- readl(regs + DIEPTSIZ(index)), +- readl(regs + DOEPTSIZ(index))); ++ dwc2_readl(regs + DIEPTSIZ(index)), ++ dwc2_readl(regs + DOEPTSIZ(index))); + + seq_puts(seq, "\n"); + seq_printf(seq, "mps %d\n", ep->ep.maxpacket); +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -80,10 +80,10 @@ static void dwc2_dump_channel_info(struc + if (chan == NULL) + return; + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); +- hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num)); +- hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); ++ hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); + + dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); + dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", +@@ -207,7 +207,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *h + */ + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, +@@ -228,11 +228,11 @@ static void dwc2_hcd_cleanup_channels(st + channel = hsotg->hc_ptr_array[i]; + if (!list_empty(&channel->hc_list_entry)) + continue; +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); + hcchar |= HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + } + } +@@ -241,11 +241,11 @@ static void dwc2_hcd_cleanup_channels(st + channel = hsotg->hc_ptr_array[i]; + if (!list_empty(&channel->hc_list_entry)) + continue; +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + /* Halt the channel */ + hcchar |= HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + + dwc2_hc_cleanup(hsotg, channel); +@@ -279,11 +279,11 @@ void dwc2_hcd_disconnect(struct dwc2_hso + * interrupt mask and status bits and disabling subsequent host + * channel interrupts. + */ +- intr = readl(hsotg->regs + GINTMSK); ++ intr = dwc2_readl(hsotg->regs + GINTMSK); + intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); +- writel(intr, hsotg->regs + GINTMSK); ++ dwc2_writel(intr, hsotg->regs + GINTMSK); + intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; +- writel(intr, hsotg->regs + GINTSTS); ++ dwc2_writel(intr, hsotg->regs + GINTSTS); + + /* + * Turn off the vbus power only if the core has transitioned to device +@@ -293,7 +293,7 @@ void dwc2_hcd_disconnect(struct dwc2_hso + if (dwc2_is_device_mode(hsotg)) { + if (hsotg->op_state != OTG_STATE_A_SUSPEND) { + dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); +- writel(0, hsotg->regs + HPRT0); ++ dwc2_writel(0, hsotg->regs + HPRT0); + } + + dwc2_disable_host_interrupts(hsotg); +@@ -344,7 +344,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hs + + /* Turn off the vbus power */ + dev_dbg(hsotg->dev, "PortPower off\n"); +- writel(0, hsotg->regs + HPRT0); ++ dwc2_writel(0, hsotg->regs + HPRT0); + } + + static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, +@@ -369,7 +369,7 @@ static int dwc2_hcd_urb_enqueue(struct d + if ((dev_speed == USB_SPEED_LOW) && + (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && + (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + + if (prtspd == HPRT0_SPD_FULL_SPEED) +@@ -391,7 +391,7 @@ static int dwc2_hcd_urb_enqueue(struct d + return retval; + } + +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + if (!(intr_mask & GINTSTS_SOF)) { + enum dwc2_transaction_type tr_type; + +@@ -1059,7 +1059,7 @@ static void dwc2_process_periodic_channe + if (dbg_perio()) + dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); + +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1074,7 +1074,7 @@ static void dwc2_process_periodic_channe + + qh_ptr = hsotg->periodic_sched_assigned.next; + while (qh_ptr != &hsotg->periodic_sched_assigned) { +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + if (qspcavail == 0) { +@@ -1134,7 +1134,7 @@ static void dwc2_process_periodic_channe + } + + if (hsotg->core_params->dma_enable <= 0) { +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1157,9 +1157,9 @@ static void dwc2_process_periodic_channe + * level to ensure that new requests are loaded as + * soon as possible.) + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are +@@ -1168,9 +1168,9 @@ static void dwc2_process_periodic_channe + * handlers to queue more transactions as transfer + * states change. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1199,7 +1199,7 @@ static void dwc2_process_non_periodic_ch + + dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); + +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1222,7 +1222,7 @@ static void dwc2_process_non_periodic_ch + * available in the request queue or the Tx FIFO + */ + do { +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { +@@ -1259,7 +1259,7 @@ next: + } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); + + if (hsotg->core_params->dma_enable <= 0) { +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1279,9 +1279,9 @@ next: + * level to ensure that new requests are loaded as + * soon as possible.) + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are +@@ -1290,9 +1290,9 @@ next: + * handlers to queue more transactions as transfer + * states change. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1330,10 +1330,10 @@ void dwc2_hcd_queue_transactions(struct + * Ensure NP Tx FIFO empty interrupt is disabled when + * there are no non-periodic transfers to process + */ +- u32 gintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + gintmsk &= ~GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1347,7 +1347,7 @@ static void dwc2_conn_id_status_change(s + + dev_dbg(hsotg->dev, "%s()\n", __func__); + +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); + dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", + !!(gotgctl & GOTGCTL_CONID_B)); +@@ -1408,9 +1408,9 @@ static void dwc2_wakeup_detected(unsigne + hprt0 = dwc2_read_hprt0(hsotg); + dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); + hprt0 &= ~HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", +- readl(hsotg->regs + HPRT0)); ++ dwc2_readl(hsotg->regs + HPRT0)); + + dwc2_hcd_rem_wakeup(hsotg); + +@@ -1438,30 +1438,30 @@ static void dwc2_port_suspend(struct dwc + spin_lock_irqsave(&hsotg->lock, flags); + + if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl |= GOTGCTL_HSTSETHNPEN; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + hsotg->op_state = OTG_STATE_A_SUSPEND; + } + + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_SUSP; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + + /* Update lx_state */ + hsotg->lx_state = DWC2_L2; + + /* Suspend the Phy Clock */ +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl |= PCGCTL_STOPPCLK; +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + udelay(10); + + /* For HNP the bus must be suspended for at least 200ms */ + if (dwc2_host_is_b_hnp_enabled(hsotg)) { +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~PCGCTL_STOPPCLK; +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + + spin_unlock_irqrestore(&hsotg->lock, flags); + +@@ -1510,23 +1510,23 @@ static int dwc2_hcd_hub_control(struct d + "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_ENA; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_SUSPEND: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + msleep(USB_RESUME_TIMEOUT); + + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hprt0 &= ~HPRT0_SUSP; + usleep_range(100000, 150000); + + hprt0 &= ~HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_POWER: +@@ -1534,7 +1534,7 @@ static int dwc2_hcd_hub_control(struct d + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 &= ~HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_INDICATOR: +@@ -1653,7 +1653,7 @@ static int dwc2_hcd_hub_control(struct d + break; + } + +- hprt0 = readl(hsotg->regs + HPRT0); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); + + if (hprt0 & HPRT0_CONNSTS) +@@ -1718,18 +1718,18 @@ static int dwc2_hcd_hub_control(struct d + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_RESET: + hprt0 = dwc2_read_hprt0(hsotg); + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_RESET\n"); +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + /* ??? Original driver does this */ +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + + hprt0 = dwc2_read_hprt0(hsotg); + /* Clear suspend bit if resetting from suspend state */ +@@ -1744,13 +1744,13 @@ static int dwc2_hcd_hub_control(struct d + hprt0 |= HPRT0_PWR | HPRT0_RST; + dev_dbg(hsotg->dev, + "In host mode, hprt0=%08x\n", hprt0); +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ + usleep_range(50000, 70000); + hprt0 &= ~HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hsotg->lx_state = DWC2_L0; /* Now back to On state */ + break; + +@@ -1814,7 +1814,7 @@ static int dwc2_hcd_is_status_changed(st + + int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) + { +- u32 hfnum = readl(hsotg->regs + HFNUM); ++ u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); + + #ifdef DWC2_DEBUG_SOF + dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", +@@ -1917,11 +1917,11 @@ void dwc2_hcd_dump_state(struct dwc2_hso + if (chan->xfer_started) { + u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; + +- hfnum = readl(hsotg->regs + HFNUM); +- hcchar = readl(hsotg->regs + HCCHAR(i)); +- hctsiz = readl(hsotg->regs + HCTSIZ(i)); +- hcint = readl(hsotg->regs + HCINT(i)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(i)); ++ hfnum = dwc2_readl(hsotg->regs + HFNUM); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); ++ hcint = dwc2_readl(hsotg->regs + HCINT(i)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); + dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); + dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); + dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); +@@ -1969,12 +1969,12 @@ void dwc2_hcd_dump_state(struct dwc2_hso + dev_dbg(hsotg->dev, " periodic_channels: %d\n", + hsotg->periodic_channels); + dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); +- np_tx_status = readl(hsotg->regs + GNPTXSTS); ++ np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", + (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); + dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", + (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); +- p_tx_status = readl(hsotg->regs + HPTXSTS); ++ p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", + (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); + dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", +@@ -2238,7 +2238,7 @@ static void dwc2_hcd_reset_func(struct w + dev_dbg(hsotg->dev, "USB RESET function called\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 &= ~HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hsotg->flags.b.port_reset_change = 1; + } + +@@ -2715,17 +2715,17 @@ static void dwc2_hcd_free(struct dwc2_hs + hsotg->status_buf = NULL; + } + +- ahbcfg = readl(hsotg->regs + GAHBCFG); ++ ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + /* Disable all interrupts */ + ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); +- writel(0, hsotg->regs + GINTMSK); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(0, hsotg->regs + GINTMSK); + + if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { +- dctl = readl(hsotg->regs + DCTL); ++ dctl = dwc2_readl(hsotg->regs + DCTL); + dctl |= DCTL_SFTDISCON; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + + if (hsotg->wq_otg) { +@@ -2788,7 +2788,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso + + retval = -ENOMEM; + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); + + #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS +--- a/drivers/usb/dwc2/hcd_ddma.c ++++ b/drivers/usb/dwc2/hcd_ddma.c +@@ -169,19 +169,19 @@ static void dwc2_per_sched_enable(struct + + spin_lock_irqsave(&hsotg->lock, flags); + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + if (hcfg & HCFG_PERSCHEDENA) { + /* already enabled */ + spin_unlock_irqrestore(&hsotg->lock, flags); + return; + } + +- writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); ++ dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); + + hcfg &= ~HCFG_FRLISTEN_MASK; + hcfg |= fr_list_en | HCFG_PERSCHEDENA; + dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + + spin_unlock_irqrestore(&hsotg->lock, flags); + } +@@ -193,7 +193,7 @@ static void dwc2_per_sched_disable(struc + + spin_lock_irqsave(&hsotg->lock, flags); + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + if (!(hcfg & HCFG_PERSCHEDENA)) { + /* already disabled */ + spin_unlock_irqrestore(&hsotg->lock, flags); +@@ -202,7 +202,7 @@ static void dwc2_per_sched_disable(struc + + hcfg &= ~HCFG_PERSCHEDENA; + dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + + spin_unlock_irqrestore(&hsotg->lock, flags); + } +--- a/drivers/usb/dwc2/hcd.h ++++ b/drivers/usb/dwc2/hcd.h +@@ -371,10 +371,10 @@ static inline struct usb_hcd *dwc2_hsotg + */ + static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) + { +- u32 mask = readl(hsotg->regs + HCINTMSK(chnum)); ++ u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + + mask &= ~intr; +- writel(mask, hsotg->regs + HCINTMSK(chnum)); ++ dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); + } + + /* +@@ -382,11 +382,11 @@ static inline void disable_hc_int(struct + */ + static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) + { +- return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; ++ return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; + } + static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) + { +- return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; ++ return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; + } + + /* +@@ -395,7 +395,7 @@ static inline int dwc2_is_device_mode(st + */ + static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) + { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); + return hprt0; +@@ -582,7 +582,7 @@ static inline u16 dwc2_micro_frame_num(u + */ + static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) + { +- return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK); ++ return dwc2_readl(hsotg->regs + GINTSTS) & dwc2_readl(hsotg->regs + GINTMSK); + } + + static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) +@@ -744,7 +744,7 @@ do { \ + qtd_list_entry); \ + if (usb_pipeint(_qtd_->urb->pipe) && \ + (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ +- _hfnum_.d32 = readl((_hcd_)->regs + HFNUM); \ ++ _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \ + switch (_hfnum_.b.frnum & 0x7) { \ + case 7: \ + (_hcd_)->hfnum_7_samples_##_letter_++; \ +--- a/drivers/usb/dwc2/hcd_intr.c ++++ b/drivers/usb/dwc2/hcd_intr.c +@@ -148,7 +148,7 @@ static void dwc2_sof_intr(struct dwc2_hs + dwc2_hcd_queue_transactions(hsotg, tr_type); + + /* Clear interrupt */ +- writel(GINTSTS_SOF, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS); + } + + /* +@@ -164,7 +164,7 @@ static void dwc2_rx_fifo_level_intr(stru + if (dbg_perio()) + dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); + +- grxsts = readl(hsotg->regs + GRXSTSP); ++ grxsts = dwc2_readl(hsotg->regs + GRXSTSP); + chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; + chan = hsotg->hc_ptr_array[chnum]; + if (!chan) { +@@ -247,11 +247,11 @@ static void dwc2_hprt0_enable(struct dwc + dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + /* Every time when port enables calculate HFIR.FrInterval */ +- hfir = readl(hsotg->regs + HFIR); ++ hfir = dwc2_readl(hsotg->regs + HFIR); + hfir &= ~HFIR_FRINT_MASK; + hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & + HFIR_FRINT_MASK; +- writel(hfir, hsotg->regs + HFIR); ++ dwc2_writel(hfir, hsotg->regs + HFIR); + + /* Check if we need to adjust the PHY clock speed for low power */ + if (!params->host_support_fs_ls_low_power) { +@@ -260,7 +260,7 @@ static void dwc2_hprt0_enable(struct dwc + return; + } + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + + if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { +@@ -268,11 +268,11 @@ static void dwc2_hprt0_enable(struct dwc + if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { + /* Set PHY low power clock select for FS/LS devices */ + usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + do_reset = 1; + } + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> + HCFG_FSLSPCLKSEL_SHIFT; + +@@ -286,7 +286,7 @@ static void dwc2_hprt0_enable(struct dwc + fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + do_reset = 1; + } + } else { +@@ -297,7 +297,7 @@ static void dwc2_hprt0_enable(struct dwc + fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + do_reset = 1; + } + } +@@ -305,7 +305,7 @@ static void dwc2_hprt0_enable(struct dwc + /* Not low power */ + if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { + usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + do_reset = 1; + } + } +@@ -332,7 +332,7 @@ static void dwc2_port_intr(struct dwc2_h + + dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); + +- hprt0 = readl(hsotg->regs + HPRT0); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0_modify = hprt0; + + /* +@@ -385,7 +385,7 @@ static void dwc2_port_intr(struct dwc2_h + } + + /* Clear Port Interrupts */ +- writel(hprt0_modify, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0_modify, hsotg->regs + HPRT0); + } + + /* +@@ -405,7 +405,7 @@ static u32 dwc2_get_actual_xfer_length(s + { + u32 hctsiz, count, length; + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + + if (halt_status == DWC2_HC_XFER_COMPLETE) { + if (chan->ep_is_in) { +@@ -483,7 +483,7 @@ static int dwc2_update_urb_state(struct + urb->status = 0; + } + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", + __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); + dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); +@@ -506,7 +506,7 @@ void dwc2_hcd_save_data_toggle(struct dw + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) + { +- u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; + + if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { +@@ -753,9 +753,9 @@ cleanup: + } + } + +- haintmsk = readl(hsotg->regs + HAINTMSK); ++ haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); + haintmsk &= ~(1 << chan->hc_num); +- writel(haintmsk, hsotg->regs + HAINTMSK); ++ dwc2_writel(haintmsk, hsotg->regs + HAINTMSK); + + /* Try to queue more transfers now that there's a free channel */ + tr_type = dwc2_hcd_select_transactions(hsotg); +@@ -802,9 +802,9 @@ static void dwc2_halt_channel(struct dwc + * is enabled so that the non-periodic schedule will + * be processed + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + dev_vdbg(hsotg->dev, "isoc/intr\n"); + /* +@@ -821,9 +821,9 @@ static void dwc2_halt_channel(struct dwc + * enabled so that the periodic schedule will be + * processed + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -888,7 +888,7 @@ static void dwc2_complete_periodic_xfer( + struct dwc2_qtd *qtd, + enum dwc2_halt_status halt_status) + { +- u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + + qtd->error_count = 0; + +@@ -1158,7 +1158,7 @@ static void dwc2_update_urb_state_abn(st + + urb->actual_length += xfer_length; + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", + __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); + dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", +@@ -1469,10 +1469,10 @@ static void dwc2_hc_ahberr_intr(struct d + + dwc2_hc_handle_tt_clear(hsotg, chan, qtd); + +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); +- hcsplt = readl(hsotg->regs + HCSPLT(chnum)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); +- hc_dma = readl(hsotg->regs + HCDMA(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); ++ hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum)); + + dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); + dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); +@@ -1685,10 +1685,10 @@ static bool dwc2_halt_status_ok(struct d + * This code is here only as a check. This condition should + * never happen. Ignore the halt if it does occur. + */ +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); +- hcsplt = readl(hsotg->regs + HCSPLT(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); + dev_dbg(hsotg->dev, + "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", + __func__); +@@ -1712,7 +1712,7 @@ static bool dwc2_halt_status_ok(struct d + * when the halt interrupt occurs. Halt the channel again if it does + * occur. + */ +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); + if (hcchar & HCCHAR_CHDIS) { + dev_warn(hsotg->dev, + "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", +@@ -1772,7 +1772,7 @@ static void dwc2_hc_chhltd_intr_dma(stru + return; + } + +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + + if (chan->hcint & HCINTMSK_XFERCOMPL) { + /* +@@ -1867,7 +1867,7 @@ static void dwc2_hc_chhltd_intr_dma(stru + dev_err(hsotg->dev, + "hcint 0x%08x, intsts 0x%08x\n", + chan->hcint, +- readl(hsotg->regs + GINTSTS)); ++ dwc2_readl(hsotg->regs + GINTSTS)); + goto error; + } + } +@@ -1922,11 +1922,11 @@ static void dwc2_hc_n_intr(struct dwc2_h + + chan = hsotg->hc_ptr_array[chnum]; + +- hcint = readl(hsotg->regs + HCINT(chnum)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); ++ hcint = dwc2_readl(hsotg->regs + HCINT(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + if (!chan) { + dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); +- writel(hcint, hsotg->regs + HCINT(chnum)); ++ dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + return; + } + +@@ -1938,7 +1938,7 @@ static void dwc2_hc_n_intr(struct dwc2_h + hcint, hcintmsk, hcint & hcintmsk); + } + +- writel(hcint, hsotg->regs + HCINT(chnum)); ++ dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + chan->hcint = hcint; + hcint &= hcintmsk; + +@@ -2030,7 +2030,7 @@ static void dwc2_hc_intr(struct dwc2_hso + u32 haint; + int i; + +- haint = readl(hsotg->regs + HAINT); ++ haint = dwc2_readl(hsotg->regs + HAINT); + if (dbg_perio()) { + dev_vdbg(hsotg->dev, "%s()\n", __func__); + +@@ -2098,8 +2098,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct + "DWC OTG HCD Finished Servicing Interrupts\n"); + dev_vdbg(hsotg->dev, + "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", +- readl(hsotg->regs + GINTSTS), +- readl(hsotg->regs + GINTMSK)); ++ dwc2_readl(hsotg->regs + GINTSTS), ++ dwc2_readl(hsotg->regs + GINTMSK)); + } + } + +--- a/drivers/usb/dwc2/hcd_queue.c ++++ b/drivers/usb/dwc2/hcd_queue.c +@@ -115,7 +115,7 @@ static void dwc2_qh_init(struct dwc2_hso + if (qh->ep_type == USB_ENDPOINT_XFER_INT) + qh->interval = 8; + #endif +- hprt = readl(hsotg->regs + HPRT0); ++ hprt = dwc2_readl(hsotg->regs + HPRT0); + prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + if (prtspd == HPRT0_SPD_HIGH_SPEED && + (dev_speed == USB_SPEED_LOW || +@@ -593,9 +593,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *h + if (status) + return status; + if (!hsotg->periodic_qh_count) { +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask |= GINTSTS_SOF; +- writel(intr_mask, hsotg->regs + GINTMSK); ++ dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + } + hsotg->periodic_qh_count++; + +@@ -630,9 +630,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsot + dwc2_deschedule_periodic(hsotg, qh); + hsotg->periodic_qh_count--; + if (!hsotg->periodic_qh_count) { +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask &= ~GINTSTS_SOF; +- writel(intr_mask, hsotg->regs + GINTMSK); ++ dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + } + } + diff --git a/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch b/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch new file mode 100644 index 0000000..d43cdf3 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0043-gpio-stp-xway-fix-phy-mask.patch @@ -0,0 +1,23 @@ +From 08b085a07efe12568d86dff064e6f089e2971744 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 25 May 2015 22:39:50 +0200 +Subject: gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs + +0x3 only masks two bits, but three bits have to be allowed. This fixes +GPHY0 LED2 (which is the highest bit of phy2) on my board. + +Signed-off-by: Martin Blumenstingl +Acked-by: John Crispin +Signed-off-by: Linus Walleij + +--- a/drivers/gpio/gpio-stp-xway.c ++++ b/drivers/gpio/gpio-stp-xway.c +@@ -58,7 +58,7 @@ + #define XWAY_STP_ADSL_MASK 0x3 + + /* 2 groups of 3 bits can be driven by the phys */ +-#define XWAY_STP_PHY_MASK 0x3 ++#define XWAY_STP_PHY_MASK 0x7 + #define XWAY_STP_PHY1_SHIFT 27 + #define XWAY_STP_PHY2_SHIFT 15 + diff --git a/target/linux/lantiq/patches-3.18/0100-lantiq-xrx200-enable-remove-crc.patch b/target/linux/lantiq/patches-3.18/0100-lantiq-xrx200-enable-remove-crc.patch new file mode 100644 index 0000000..60a1937 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0100-lantiq-xrx200-enable-remove-crc.patch @@ -0,0 +1,25 @@ +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -143,6 +143,7 @@ + #define PMAC_IPG_MASK 0xf + #define PMAC_HD_CTL_AS 0x0008 + #define PMAC_HD_CTL_AC 0x0004 ++#define PMAC_HD_CTL_RC 0x0010 + #define PMAC_HD_CTL_RXSH 0x0040 + #define PMAC_HD_CTL_AST 0x0080 + #define PMAC_HD_CTL_RST 0x0100 +@@ -1502,12 +1503,12 @@ static void xrx200_hw_init(struct xrx200 + #ifdef SW_ROUTING + /* enable status header, enable CRC */ + ltq_pmac_w32_mask(0, +- PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC, ++ PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, + PMAC_HD_CTL); + #else + /* disable status header, enable CRC */ + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS, +- PMAC_HD_CTL_AC, ++ PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, + PMAC_HD_CTL); + #endif + diff --git a/target/linux/lantiq/patches-3.18/0101-mtd-split.patch b/target/linux/lantiq/patches-3.18/0101-mtd-split.patch new file mode 100644 index 0000000..6152e0e --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0101-mtd-split.patch @@ -0,0 +1,192 @@ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,6 +1,6 @@ + obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o + +-obj-y += vmmc.o tffs.o ++obj-y += vmmc.o tffs.o mtd_split.o + + obj-y += eth_mac.o + obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/mtd_split.c +@@ -0,0 +1,129 @@ ++#include ++#include ++#include ++#include ++ ++#define ROOTFS_SPLIT_NAME "rootfs_data" ++ ++struct squashfs_super_block { ++ __le32 s_magic; ++ __le32 pad0[9]; ++ __le64 bytes_used; ++}; ++ ++static void split_brnimage_kernel(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++ unsigned long buf[4]; ++ // Assume at most 2MB of kernel image ++ unsigned long end = offset + (2 << 20); ++ unsigned long part_size = offset + 0x400 - 12; ++ size_t len; ++ int ret; ++ ++ if (strcmp(name, "firmware") != 0) ++ return; ++ while (part_size < end) { ++ long size_min = part_size - 0x400 - 12 - offset; ++ long size_max = part_size + 12 - offset; ++ ret = mtd_read(master, part_size, 16, &len, (void *)buf); ++ if (ret || len != 16) ++ return; ++ ++ if (le32_to_cpu(buf[0]) < size_min || ++ le32_to_cpu(buf[0]) > size_max) { ++ part_size += 0x400; ++ continue; ++ } ++ ++ if (le32_to_cpu(buf[3]) == SQUASHFS_MAGIC) { ++ part_size += 12 - offset; ++ __mtd_add_partition(master, "rootfs", offset + part_size, ++ size - part_size, false); ++ return; ++ } ++ part_size += 0x400; ++ } ++} ++ ++static void split_eva_kernel(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++#define EVA_MAGIC 0xfeed1281 ++ unsigned long magic = 0; ++ unsigned long part_size = 0, p; ++ size_t len; ++ int ret; ++ ++ if (strcmp(name, CONFIG_MTD_SPLIT_FIRMWARE_NAME) != 0) ++ return; ++ ++ ret = mtd_read(master, offset, 4, &len, (void *)&magic); ++ if (ret || len != sizeof(magic)) ++ return; ++ ++ if (le32_to_cpu(magic) != EVA_MAGIC) ++ return; ++ ++ ret = mtd_read(master, offset + 4, 4, &len, (void *)&part_size); ++ if (ret || len != sizeof(part_size)) ++ return; ++ ++ p = part_size = le32_to_cpu(part_size) + 0x18; ++ p &= ~0xffff; ++ p += 0x10000; ++ ++ ret = mtd_read(master, offset + p, 4, &len, (void *)&magic); ++ if (ret || len != sizeof(magic)) ++ return; ++ ++ if (magic == SQUASHFS_MAGIC) ++ part_size = p + 0x100; ++ else ++ part_size = mtd_pad_erasesize(master, offset, len); ++ ++ if (part_size + master->erasesize > size) ++ return; ++ ++ __mtd_add_partition(master, "rootfs", offset + part_size, ++ size - part_size, false); ++} ++ ++static void split_tplink_kernel(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++#define TPLINK_MAGIC 0x00000002 ++ unsigned long magic = 0; ++ unsigned long part_size = 0; ++ size_t len; ++ int ret; ++ ++ if (strcmp(name, CONFIG_MTD_SPLIT_FIRMWARE_NAME) != 0) ++ return; ++ ++ ret = mtd_read(master, offset, 4, &len, (void *)&magic); ++ if (ret || len != sizeof(magic)) ++ return; ++ ++ if (le32_to_cpu(magic) != TPLINK_MAGIC) ++ return; ++ ++ ret = mtd_read(master, offset + 0x78, 4, &len, (void *)&part_size); ++ if (ret || len != sizeof(part_size)) ++ return; ++ ++ part_size = be32_to_cpu(part_size) + 0x200; ++ if (part_size + master->erasesize > size) ++ return; ++ ++ __mtd_add_partition(master, "rootfs", offset + part_size, ++ size - part_size, false); ++} ++ ++void arch_split_mtd_part(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++ split_tplink_kernel(master, name, offset, size); ++ split_eva_kernel(master, name, offset, size); ++ split_brnimage_kernel(master, name, offset, size); ++} +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -89,12 +89,17 @@ extern void deregister_mtd_parser(struct + int mtd_is_partition(const struct mtd_info *mtd); + int mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length); ++int __mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length, bool dup_check); ++ + int mtd_del_partition(struct mtd_info *master, int partno); + struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd); + uint64_t mtdpart_get_offset(const struct mtd_info *mtd); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); +-extern void __weak arch_split_mtd_part(struct mtd_info *master, +- const char *name, int offset, int size); ++void __weak arch_split_mtd_part(struct mtd_info *master, ++ const char *name, int offset, int size); ++unsigned long ++mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len); + + int parse_mtd_partitions_by_type(struct mtd_info *master, + enum mtd_parser_type type, +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -628,7 +628,7 @@ out_register: + } + + +-static int ++int + __mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length, bool dup_check) + { +@@ -749,7 +749,7 @@ run_parsers_by_type(struct mtd_part *sla + return nr_parts; + } + +-static inline unsigned long ++unsigned long + mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len) + { + unsigned long mask = mtd->erasesize - 1; +@@ -819,7 +819,6 @@ static void split_uimage(struct mtd_info + return; + + len = be32_to_cpu(hdr.size) + 0x40; +- len = mtd_pad_erasesize(master, part->offset, len); + if (len + master->erasesize > part->mtd.size) + return; + diff --git a/target/linux/lantiq/patches-3.18/0150-lantiq-pinctrl-xway.patch b/target/linux/lantiq/patches-3.18/0150-lantiq-pinctrl-xway.patch new file mode 100644 index 0000000..84adbe6 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0150-lantiq-pinctrl-xway.patch @@ -0,0 +1,15 @@ +--- a/drivers/pinctrl/pinctrl-xway.c ++++ b/drivers/pinctrl/pinctrl-xway.c +@@ -152,10 +152,10 @@ static const struct ltq_mfp_pin xway_mfp + MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), +- MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN), ++ MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY), + MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN), + MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), +- MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN), ++ MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN), + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), diff --git a/target/linux/lantiq/patches-3.18/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-3.18/0151-lantiq-ifxmips_pcie-use-of.patch new file mode 100644 index 0000000..26a3a65 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0151-lantiq-ifxmips_pcie-use-of.patch @@ -0,0 +1,51 @@ +--- a/arch/mips/pci/ifxmips_pcie.c ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -18,6 +18,8 @@ + #include + #include + ++#include ++ + #include "ifxmips_pcie.h" + #include "ifxmips_pcie_reg.h" + +@@ -1045,7 +1047,7 @@ pcie_rc_initialize(int pcie_port) + return 0; + } + +-static int __init ifx_pcie_bios_init(void) ++static int __init ifx_pcie_bios_probe(struct platform_device *pdev) + { + void __iomem *io_map_base; + int pcie_port; +@@ -1083,6 +1085,30 @@ static int __init ifx_pcie_bios_init(voi + + return 0; + } ++ ++static const struct of_device_id ifxmips_pcie_match[] = { ++ { .compatible = "lantiq,pcie-xrx200" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); ++ ++static struct platform_driver ltq_pci_driver = { ++ .probe = ifx_pcie_bios_probe, ++ .driver = { ++ .name = "pcie-xrx200", ++ .owner = THIS_MODULE, ++ .of_match_table = ifxmips_pcie_match, ++ }, ++}; ++ ++int __init ifx_pcie_bios_init(void) ++{ ++ int ret = platform_driver_register(<q_pci_driver); ++ if (ret) ++ pr_info("pcie-xrx200: Error registering platform driver!"); ++ return ret; ++} ++ + arch_initcall(ifx_pcie_bios_init); + + MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/patches-3.18/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-3.18/0160-owrt-lantiq-multiple-flash.patch new file mode 100644 index 0000000..c093231 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0160-owrt-lantiq-multiple-flash.patch @@ -0,0 +1,217 @@ +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -38,10 +39,12 @@ enum { + LTQ_NOR_NORMAL + }; + ++#define MAX_RESOURCES 4 ++ + struct ltq_mtd { +- struct resource *res; +- struct mtd_info *mtd; +- struct map_info *map; ++ struct mtd_info *mtd[MAX_RESOURCES]; ++ struct mtd_info *cmtd; ++ struct map_info map[MAX_RESOURCES]; + }; + + static const char ltq_map_name[] = "ltq_nor"; +@@ -109,12 +112,44 @@ ltq_copy_to(struct map_info *map, unsign + } + + static int ++ltq_mtd_remove(struct platform_device *pdev) ++{ ++ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); ++ int i; ++ ++ if (ltq_mtd == NULL) ++ return 0; ++ ++ if (ltq_mtd->cmtd) { ++ mtd_device_unregister(ltq_mtd->cmtd); ++ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) ++ mtd_concat_destroy(ltq_mtd->cmtd); ++ } ++ ++ for (i = 0; i < MAX_RESOURCES; i++) { ++ if (ltq_mtd->mtd[i] != NULL) ++ map_destroy(ltq_mtd->mtd[i]); ++ } ++ ++ kfree(ltq_mtd); ++ ++ return 0; ++} ++ ++static int + ltq_mtd_probe(struct platform_device *pdev) + { + struct mtd_part_parser_data ppdata; + struct ltq_mtd *ltq_mtd; + struct cfi_private *cfi; +- int err; ++ int err = 0; ++ int i; ++ int devices_found = 0; ++ ++ static const char *rom_probe_types[] = { ++ "cfi_probe", "jedec_probe", NULL ++ }; ++ const char **type; + + if (of_machine_is_compatible("lantiq,falcon") && + (ltq_boot_select() != BS_FLASH)) { +@@ -128,76 +163,88 @@ ltq_mtd_probe(struct platform_device *pd + + platform_set_drvdata(pdev, ltq_mtd); + +- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!ltq_mtd->res) { +- dev_err(&pdev->dev, "failed to get memory resource\n"); +- return -ENOENT; ++ for (i = 0; i < pdev->num_resources; i++) { ++ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", ++ (unsigned long long)resource_size(&pdev->resource[i]), ++ (unsigned long long)pdev->resource[i].start); ++ ++ if (!devm_request_mem_region(&pdev->dev, ++ pdev->resource[i].start, ++ resource_size(&pdev->resource[i]), ++ dev_name(&pdev->dev))) { ++ dev_err(&pdev->dev, "Could not reserve memory region\n"); ++ return -ENOMEM; ++ } ++ ++ ltq_mtd->map[i].name = ltq_map_name; ++ ltq_mtd->map[i].bankwidth = 2; ++ ltq_mtd->map[i].read = ltq_read16; ++ ltq_mtd->map[i].write = ltq_write16; ++ ltq_mtd->map[i].copy_from = ltq_copy_from; ++ ltq_mtd->map[i].copy_to = ltq_copy_to; ++ ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map[i].phys = NO_XIP; ++ else ++ ltq_mtd->map[i].phys = pdev->resource[i].start; ++ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); ++ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, ++ ltq_mtd->map[i].size); ++ if (IS_ERR(ltq_mtd->map[i].virt)) ++ return PTR_ERR(ltq_mtd->map[i].virt); ++ ++ if (ltq_mtd->map[i].virt == NULL) { ++ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); ++ err = PTR_ERR(ltq_mtd->map[i].virt); ++ goto err_out; ++ } ++ ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; ++ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) ++ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; ++ ++ if (!ltq_mtd->mtd[i]) { ++ dev_err(&pdev->dev, "probing failed\n"); ++ return -ENXIO; ++ } else { ++ devices_found++; ++ } ++ ++ ltq_mtd->mtd[i]->owner = THIS_MODULE; ++ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; ++ ++ cfi = ltq_mtd->map[i].fldrv_priv; ++ cfi->addr_unlock1 ^= 1; ++ cfi->addr_unlock2 ^= 1; + } + +- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), +- GFP_KERNEL); +- if (!ltq_mtd->map) +- return -ENOMEM; +- +- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) +- ltq_mtd->map->phys = NO_XIP; +- else +- ltq_mtd->map->phys = ltq_mtd->res->start; +- ltq_mtd->res->start; +- ltq_mtd->map->size = resource_size(ltq_mtd->res); +- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); +- if (IS_ERR(ltq_mtd->map->virt)) +- return PTR_ERR(ltq_mtd->map->virt); +- +- ltq_mtd->map->name = ltq_map_name; +- ltq_mtd->map->bankwidth = 2; +- ltq_mtd->map->read = ltq_read16; +- ltq_mtd->map->write = ltq_write16; +- ltq_mtd->map->copy_from = ltq_copy_from; +- ltq_mtd->map->copy_to = ltq_copy_to; +- +- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; +- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); +- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; +- +- if (!ltq_mtd->mtd) { +- dev_err(&pdev->dev, "probing failed\n"); +- return -ENXIO; +- } +- +- ltq_mtd->mtd->owner = THIS_MODULE; +- +- cfi = ltq_mtd->map->fldrv_priv; +- cfi->addr_unlock1 ^= 1; +- cfi->addr_unlock2 ^= 1; ++ if (devices_found == 1) { ++ ltq_mtd->cmtd = ltq_mtd->mtd[0]; ++ } else if (devices_found > 1) { ++ /* ++ * We detected multiple devices. Concatenate them together. ++ */ ++ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); ++ if (ltq_mtd->cmtd == NULL) ++ err = -ENXIO; ++ } + + ppdata.of_node = pdev->dev.of_node; +- err = mtd_device_parse_register(ltq_mtd->mtd, ltq_probe_types, ++ err = mtd_device_parse_register(ltq_mtd->cmtd, ltq_probe_types, + &ppdata, NULL, 0); + if (err) { + dev_err(&pdev->dev, "failed to add partitions\n"); +- goto err_destroy; ++ goto err_out; + } + + return 0; + +-err_destroy: +- map_destroy(ltq_mtd->mtd); ++err_out: ++ ltq_mtd_remove(pdev); + return err; + } + +-static int +-ltq_mtd_remove(struct platform_device *pdev) +-{ +- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); +- +- if (ltq_mtd && ltq_mtd->mtd) { +- mtd_device_unregister(ltq_mtd->mtd); +- map_destroy(ltq_mtd->mtd); +- } +- return 0; +-} +- + static const struct of_device_id ltq_mtd_match[] = { + { .compatible = "lantiq,nor" }, + {}, diff --git a/target/linux/lantiq/patches-3.18/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-3.18/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch new file mode 100644 index 0000000..d153c52 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0001.c ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c +@@ -39,7 +39,7 @@ + /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ + + // debugging, turns off buffer write mode if set to 1 +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + /* Intel chips */ + #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-4.1/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-4.1/0001-MIPS-lantiq-add-pcie-driver.patch new file mode 100644 index 0000000..e65e982 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0001-MIPS-lantiq-add-pcie-driver.patch @@ -0,0 +1,5540 @@ +From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:12:28 +0200 +Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/Kconfig | 10 + + arch/mips/lantiq/xway/sysctrl.c | 2 + + arch/mips/pci/Makefile | 2 + + arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ + arch/mips/pci/fixup-lantiq.c | 5 +- + arch/mips/pci/ifxmips_pci_common.h | 57 ++ + arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie.h | 135 ++++ + arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ + arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ + arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ + arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ + arch/mips/pci/ifxmips_pcie_pm.h | 36 + + arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ + arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ + arch/mips/pci/pci.c | 25 + + arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ + drivers/pci/pcie/aer/Kconfig | 2 +- + include/linux/pci.h | 2 + + include/linux/pci_ids.h | 6 + + 20 files changed, 5374 insertions(+), 2 deletions(-) + create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c + create mode 100644 arch/mips/pci/ifxmips_pci_common.h + create mode 100644 arch/mips/pci/ifxmips_pcie.c + create mode 100644 arch/mips/pci/ifxmips_pcie.h + create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h + create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c + create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c + create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h + create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h + create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h + create mode 100644 arch/mips/pci/pcie-lantiq.h + +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -17,6 +17,7 @@ config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HW_HAS_PCI ++ select ARCH_SUPPORTS_MSI + + config SOC_FALCON + bool "FALCON" +@@ -37,6 +38,15 @@ config PCI_LANTIQ + bool "PCI Support" + depends on SOC_XWAY && PCI + ++config PCIE_LANTIQ ++ bool "PCIE Support" ++ depends on SOC_XWAY && PCI ++ ++config PCIE_LANTIQ_MSI ++ bool ++ depends on PCIE_LANTIQ && PCI_MSI ++ default y ++ + config XRX200_PHY_FW + bool "XRX200 PHY firmware loader" + depends on SOC_XWAY +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -377,6 +377,8 @@ void __init ltq_soc_init(void) + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB | PMU_PPE_TOP); + clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY); ++ pmu_w32(~0, PMU_PWDSR1); ++ pmu_w32(pmu_r32(PMU_PWDSR) & ~PMU_PCIE_CLK, PMU_PWDSR); + } else if (of_machine_is_compatible("lantiq,ar9")) { + clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), + ltq_ar9_fpi_hz(), CLOCK_250M); +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -45,6 +45,8 @@ obj-$(CONFIG_LANTIQ) += fixup-lantiq.o + obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o + obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o ++obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o + obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o +--- /dev/null ++++ b/arch/mips/pci/fixup-lantiq-pcie.c +@@ -0,0 +1,82 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_fixup_pcie.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_fixup_pcie.c ++ \ingroup IFX_PCIE ++ \brief PCIe Fixup functions source file ++*/ ++#include ++#include ++#include ++ ++#include ++ ++#include "pcie-lantiq.h" ++ ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 ++ ++ ++ ++static void ++ifx_pcie_fixup_resource(struct pci_dev *dev) ++{ ++ u32 reg; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ printk("%s: fixup host controller %s (%04x:%04x)\n", ++ __func__, pci_name(dev), dev->vendor, dev->device); ++ ++ /* Setup COMMAND register */ ++ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | ++ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; ++ pci_write_config_word(dev, PCI_COMMAND, reg); ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); ++ ++static void ++ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); ++ ++ if (dev->devfn == PCI_DEVFN(0, 0) && ++ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { ++ ++ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); ++ ++ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); ++ } ++ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); ++ mdelay(10); ++} ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ++ ifx_pcie_rc_class_early_fixup); ++ ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, ++ ifx_pcie_rc_class_early_fixup); +--- a/arch/mips/pci/fixup-lantiq.c ++++ b/arch/mips/pci/fixup-lantiq.c +@@ -8,12 +8,18 @@ + + #include + #include ++#include "ifxmips_pci_common.h" + + int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; + int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; + + int pcibios_plat_dev_init(struct pci_dev *dev) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ ifx_pcie_bios_plat_dev_init(dev); ++#endif ++ + if (ltq_pci_plat_arch_init) + return ltq_pci_plat_arch_init(dev); + +@@ -25,5 +31,10 @@ int pcibios_plat_dev_init(struct pci_dev + + int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) + { ++#ifdef CONFIG_PCIE_LANTIQ ++ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) ++ return ifx_pcie_bios_map_irq(dev, slot, pin); ++#endif ++ + return of_irq_parse_and_map_pci(dev, slot, pin); + } +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pci_common.h +@@ -0,0 +1,57 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pci_common.h ++** PROJECT : IFX UEIP ++** MODULES : PCI subsystem ++** ++** DATE : 30 June 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 30 June,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++ ++#ifndef IFXMIPS_PCI_COMMON_H ++#define IFXMIPS_PCI_COMMON_H ++#include ++/*! ++ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration ++ \brief PCI/PCIe common parts ++*/ ++ ++/*! ++ \defgroup IFX_PCI_COM_OS OS APIs ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver OS interface functions ++*/ ++/*! ++ \file ifxmips_pci_common.h ++ \ingroup IFX_PCI_COM ++ \brief PCI/PCIe bus driver common OS header file ++*/ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++#define IFX_PCI_CONST ++#else ++#define IFX_PCI_CONST const ++#endif ++#ifdef CONFIG_IFX_PCI ++extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); ++#endif /* COFNIG_IFX_PCI */ ++ ++#ifdef CONFIG_PCIE_LANTIQ ++extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); ++extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); ++#endif ++ ++#endif /* IFXMIPS_PCI_COMMON_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -0,0 +1,1092 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2009 Lei Chuanhua ++ * Copyright (C) 2013 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie.h" ++#include "ifxmips_pcie_reg.h" ++ ++/* Enable 32bit io due to its mem mapped io nature */ ++#define IFX_PCIE_ERROR_INT ++#define IFX_PCIE_IO_32BIT ++ ++#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) ++#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) ++#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) ++#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) ++#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) ++#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) ++#define SM(_v, _f) (((_v) << _f##_S) & (_f)) ++#define IFX_REG_SET_BIT(_f, _r) \ ++ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) ++ ++#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 ++ ++static DEFINE_SPINLOCK(ifx_pcie_lock); ++ ++u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); ++ ++static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .ir_irq = { ++ .irq = IFX_PCIE_IR, ++ .name = "ifx_pcie_rc0", ++ }, ++ ++ .legacy_irq = { ++ { ++ .irq_bit = PCIE_IRN_INTA, ++ .irq = IFX_PCIE_INTA, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTB, ++ .irq = IFX_PCIE_INTB, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTC, ++ .irq = IFX_PCIE_INTC, ++ }, ++ { ++ .irq_bit = PCIE_IRN_INTD, ++ .irq = IFX_PCIE_INTD, ++ }, ++ }, ++ }, ++ ++}; ++ ++void ifx_pcie_debug(const char *fmt, ...) ++{ ++ static char buf[256] = {0}; /* XXX */ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ vsnprintf(buf, sizeof(buf), fmt, ap); ++ va_end(ap); ++ ++ printk("%s", buf); ++} ++ ++ ++static inline int pcie_ltssm_enable(int pcie_port) ++{ ++ int i; ++ ++ /* Enable LTSSM */ ++ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); ++ ++ /* Wait for the link to come up */ ++ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) ++ return 0; ++ udelay(10); ++ } ++ ++ printk("%s link timeout!!!!!\n", __func__); ++ return -1; ++} ++ ++static inline void pcie_status_register_clear(int pcie_port) ++{ ++ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); ++ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); ++ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_UESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); ++ IFX_REG_W32(0, PCIE_RESR(pcie_port)); ++ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); ++ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); ++ IFX_REG_W32(0, PCIE_QSR(pcie_port)); ++ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); ++} ++ ++static inline int ifx_pcie_link_up(int pcie_port) ++{ ++ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; ++} ++ ++ ++static inline void pcie_mem_io_setup(int pcie_port) ++{ ++ u32 reg; ++ /* ++ * BAR[0:1] readonly register ++ * RC contains only minimal BARs for packets mapped to this device ++ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that ++ * reside on the downstream side fo the bridge. ++ */ ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); ++ ++ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); ++ ++ ++#ifdef IFX_PCIE_PREFETCH_MEM_64BIT ++ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) ++ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) ++ | PCIE_PMBL_64BIT_ADDR; ++ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); ++ ++ /* Must configure upper 32bit */ ++ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); ++ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); ++#else ++ /* PCIe_PBML, same as MBML */ ++ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); ++#endif ++ ++ /* IO Address Range */ ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); ++#ifdef IFX_PCIE_IO_32BIT ++ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; ++#endif /* IFX_PCIE_IO_32BIT */ ++ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); ++ ++#ifdef IFX_PCIE_IO_32BIT ++ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) ++ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); ++ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); ++ ++#endif /* IFX_PCIE_IO_32BIT */ ++} ++ ++static inline void ++pcie_device_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Device capability register, set up Maximum payload size */ ++ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); ++ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); ++ ++ /* Only available for EP */ ++ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); ++ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); ++ ++ /* Device control and status register */ ++ /* Set Maximum Read Request size for the device as a Requestor */ ++ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); ++ ++ /* ++ * Request size can be larger than the MPS used, but the completions returned ++ * for the read will be bounded by the MPS size. ++ * In our system, Max request size depends on AHB burst size. It is 64 bytes. ++ * but we set it as 128 as minimum one. ++ */ ++ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) ++ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); ++ ++ /* Enable relaxed ordering, no snoop, and all kinds of errors */ ++ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; ++ ++ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); ++} ++ ++static inline void ++pcie_link_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM ++ * L0s is reported during link training via TS1 order set by N_FTS ++ */ ++ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); ++ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; ++ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); ++ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); ++ ++ /* Link control and status register */ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ /* Link Enable, ASPM enabled */ ++ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; ++ ++#ifdef CONFIG_PCIEASPM ++ /* ++ * We use the same physical reference clock that the platform provides on the connector ++ * It paved the way for ASPM to calculate the new exit Latency ++ */ ++ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; ++ reg |= PCIE_LCTLSTS_COM_CLK_CFG; ++ /* ++ * We should disable ASPM by default except that we have dedicated power management support ++ * Enable ASPM will cause the system hangup/instability, performance degration ++ */ ++ reg |= PCIE_LCTLSTS_ASPM_ENABLE; ++#else ++ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; ++#endif /* CONFIG_PCIEASPM */ ++ ++ /* ++ * The maximum size of any completion with data packet is bounded by the MPS setting ++ * in device control register ++ */ ++ ++ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ ++ reg &= ~ PCIE_LCTLSTS_RCB128; ++ ++ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); ++} ++ ++static inline void pcie_error_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* ++ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone ++ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE ++ */ ++ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); ++ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; ++ ++ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); ++ ++ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ ++ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); ++ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); ++ ++ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ ++ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); ++ ++ /* Correctable Error Mask Register, unmask all bits */ ++ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); ++ reg &= ~PCIE_CORRECTABLE_ERR; ++ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); ++ ++ /* Advanced Error Capabilities and Control Registr */ ++ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); ++ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; ++ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); ++ ++ /* Root Error Command Register, Report all types of errors */ ++ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); ++ reg |= PCIE_RECR_ERR_REPORT_EN; ++ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); ++ ++ /* Clear the Root status register */ ++ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); ++ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); ++} ++ ++static inline void pcie_port_logic_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ ++ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); ++ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); ++ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) ++ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); ++ /* L0s and L1 entry latency */ ++ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); ++ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) ++ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); ++ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); ++ ++ ++ /* Port Link Control Register */ ++ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); ++ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ ++ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); ++ ++ /* Lane Skew Register */ ++ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); ++ /* Enable ACK/NACK and FC */ ++ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); ++ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); ++ ++ /* Symbol Timer Register and Filter Mask Register 1 */ ++ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); ++ ++ /* Default SKP interval is very accurate already, 5us */ ++ /* Enable IO/CFG transaction */ ++ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; ++ /* Disable FC WDT */ ++ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; ++ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); ++ ++ /* Filter Masker Register 2 */ ++ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); ++ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; ++ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); ++ ++ /* VC0 Completion Receive Queue Control Register */ ++ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); ++ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; ++ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); ++ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); ++} ++ ++static inline void pcie_rc_cfg_reg_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Disable LTSSM */ ++ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ ++ ++ pcie_mem_io_setup(pcie_port); ++ ++ /* XXX, MSI stuff should only apply to EP */ ++ /* MSI Capability: Only enable 32-bit addresses */ ++ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); ++ reg &= ~PCIE_MCAPR_ADDR64_CAP; ++ ++ reg |= PCIE_MCAPR_MSI_ENABLE; ++ ++ /* Disable multiple message */ ++ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); ++ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); ++ ++ ++ /* Enable PME, Soft reset enabled */ ++ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); ++ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; ++ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); ++ ++ /* setup the bus */ ++ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); ++ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); ++ ++ ++ pcie_device_setup(pcie_port); ++ pcie_link_setup(pcie_port); ++ pcie_error_setup(pcie_port); ++ ++ /* Root control and capabilities register */ ++ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); ++ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; ++ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); ++ ++ /* Port VC Capability Register 2 */ ++ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); ++ reg &= ~PCIE_PVC2_VC_ARB_WRR; ++ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; ++ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); ++ ++ /* VC0 Resource Capability Register */ ++ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); ++ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; ++ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); ++ ++ pcie_port_logic_setup(pcie_port); ++} ++ ++static int ifx_pcie_wait_phy_link_up(int pcie_port) ++{ ++#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ ++ int i; ++ ++ /* Wait for PHY link is up */ ++ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { ++ if (ifx_pcie_link_up(pcie_port)) { ++ break; ++ } ++ udelay(100); ++ } ++ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { ++ printk(KERN_ERR "%s timeout\n", __func__); ++ return -1; ++ } ++ ++ /* Check data link up or not */ ++ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { ++ printk(KERN_ERR "%s DLL link is still down\n", __func__); ++ return -1; ++ } ++ ++ /* Check Data link active or not */ ++ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { ++ printk(KERN_ERR "%s DLL is not active\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static inline int pcie_app_loigc_setup(int pcie_port) ++{ ++ /* supress ahb bus errrors */ ++ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); ++ ++ /* Pull PCIe EP out of reset */ ++ pcie_device_rst_deassert(pcie_port); ++ ++ /* Start LTSSM training between RC and EP */ ++ pcie_ltssm_enable(pcie_port); ++ ++ /* Check PHY status after enabling LTSSM */ ++ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) ++ return -1; ++ ++ return 0; ++} ++ ++/* ++ * The numbers below are directly from the PCIe spec table 3-4/5. ++ */ ++static inline void pcie_replay_time_update(int pcie_port) ++{ ++ u32 reg; ++ int nlw; ++ int rtl; ++ ++ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); ++ ++ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); ++ switch (nlw) { ++ case PCIE_MAX_LENGTH_WIDTH_X1: ++ rtl = 1677; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X2: ++ rtl = 867; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X4: ++ rtl = 462; ++ break; ++ case PCIE_MAX_LENGTH_WIDTH_X8: ++ rtl = 258; ++ break; ++ default: ++ rtl = 1677; ++ break; ++ } ++ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); ++ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; ++ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); ++ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); ++} ++ ++/* ++ * Table 359 Enhanced Configuration Address Mapping1) ++ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 ++ * Memory Address PCI Express Configuration Space ++ * A[(20+n-1):20] Bus Number 1 < n < 8 ++ * A[19:15] Device Number ++ * A[14:12] Function Number ++ * A[11:8] Extended Register Number ++ * A[7:2] Register Number ++ * A[1:0] Along with size of the access, used to generate Byte Enables ++ * For VR9, only the address bits [22:0] are mapped to the configuration space: ++ * . Address bits [22:20] select the target bus (1-of-8)1) ++ * . Address bits [19:15] select the target device (1-of-32) on the bus ++ * . Address bits [14:12] select the target function (1-of-8) within the device. ++ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space ++ * . Address bits [1:0] define the start byte location within the selected dword. ++ */ ++static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) ++{ ++ u32 addr; ++ u8 bus; ++ ++ if (!bus_num) { ++ /* type 0 */ ++ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); ++ } else { ++ bus = bus_num; ++ /* type 1, only support 8 buses */ ++ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | ++ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); ++ } ++ return addr; ++} ++ ++static int pcie_valid_config(int pcie_port, int bus, int dev) ++{ ++ /* RC itself */ ++ if ((bus == 0) && (dev == 0)) { ++ return 1; ++ } ++ ++ /* No physical link */ ++ if (!ifx_pcie_link_up(pcie_port)) { ++ return 0; ++ } ++ ++ /* Bus zero only has RC itself ++ * XXX, check if EP will be integrated ++ */ ++ if ((bus == 0) && (dev != 0)) { ++ return 0; ++ } ++ ++ /* Maximum 8 buses supported for VRX */ ++ if (bus > 9) { ++ return 0; ++ } ++ ++ /* ++ * PCIe is PtP link, one bus only supports only one device ++ * except bus zero and PCIe switch which is virtual bus device ++ * The following two conditions really depends on the system design ++ * and attached the device. ++ * XXX, how about more new switch ++ */ ++ if ((bus == 1) && (dev != 0)) { ++ return 0; ++ } ++ ++ if ((bus >= 3) && (dev != 0)) { ++ return 0; ++ } ++ return 1; ++} ++ ++static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) ++{ ++ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) ++{ ++ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); ++} ++ ++u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ primary += pcibios_1st_host_bus_nr(); ++ secondary += pcibios_1st_host_bus_nr(); ++ subordinate += pcibios_1st_host_bus_nr(); ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ return tvalue; ++} ++ ++u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) ++{ ++ u32 tvalue = value; ++ ++ if (where == PCI_PRIMARY_BUS) { ++ u8 primary, secondary, subordinate; ++ ++ primary = tvalue & 0xFF; ++ secondary = (tvalue >> 8) & 0xFF; ++ subordinate = (tvalue >> 16) & 0xFF; ++ if (primary > 0 && primary != 0xFF) { ++ primary -= pcibios_1st_host_bus_nr(); ++ } ++ ++ if (secondary > 0 && secondary != 0xFF) { ++ secondary -= pcibios_1st_host_bus_nr(); ++ } ++ if (subordinate > 0 && subordinate != 0xFF) { ++ subordinate -= pcibios_1st_host_bus_nr(); ++ } ++ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); ++ } ++ else if (where == PCI_SUBORDINATE_BUS) { ++ u8 subordinate = tvalue & 0xFF; ++ ++ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; ++ tvalue = subordinate; ++ } ++ return tvalue; ++} ++ ++static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 *value) ++{ ++ u32 data = 0; ++ int bus_number = bus->number; ++ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ if (unlikely(size != 1 && size != 2 && size != 4)){ ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ /* ++ * PCIe only has a single device connected to it. It is ++ * always device ID 0. Don't bother doing reads for other ++ * device IDs on the first segment. ++ */ ++ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { ++ ret = PCIBIOS_FUNC_NOT_SUPPORTED; ++ goto out; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ *value = 0xffffffff; ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ } ++ /* To get a correct PCI topology, we have to restore the bus number to OS */ ++ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); ++ ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++ ++ *value = (data >> (8 * (where & 3))) & mask[size & 7]; ++out: ++ return ret; ++} ++ ++static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) ++{ ++ u32 shift; ++ u32 tdata = data; ++ ++ switch (size) { ++ case 1: ++ shift = (where & 0x3) << 3; ++ tdata &= ~(0xffU << shift); ++ tdata |= ((value & 0xffU) << shift); ++ break; ++ case 2: ++ shift = (where & 3) << 3; ++ tdata &= ~(0xffffU << shift); ++ tdata |= ((value & 0xffffU) << shift); ++ break; ++ case 4: ++ tdata = value; ++ break; ++ } ++ return tdata; ++} ++ ++static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 value) ++{ ++ int bus_number = bus->number; ++ int ret = PCIBIOS_SUCCESSFUL; ++ struct ifx_pci_controller *ctrl = bus->sysdata; ++ int pcie_port = ctrl->port; ++ u32 tvalue = value; ++ u32 data; ++ ++ /* Make sure the address is aligned to natural boundary */ ++ if (unlikely(((size - 1) & where))) { ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ goto out; ++ } ++ /* ++ * If we are second controller, we have to cheat OS so that it assume ++ * its bus number starts from 0 in host controller ++ */ ++ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); ++ ++ /* ++ * We need to force the bus number to be zero on the root ++ * bus. Linux numbers the 2nd root bus to start after all ++ * busses on root 0. ++ */ ++ if (bus->parent == NULL) { ++ bus_number = 0; ++ } ++ ++ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ goto out; ++ } ++ ++ /* XXX, some PCIe device may need some delay */ ++ PCIE_IRQ_LOCK(ifx_pcie_lock); ++ ++ /* ++ * To configure the correct bus topology using native way, we have to cheat Os so that ++ * it can configure the PCIe hardware correctly. ++ */ ++ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); ++ ++ if (bus_number == 0) { /* RC itself */ ++ u32 t; ++ ++ t = (where & ~3); ++ data = ifx_pcie_rc_cfg_rd(pcie_port, t); ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++ ++ ifx_pcie_rc_cfg_wr(pcie_port, t, data); ++ } else { ++ u32 addr = pcie_bus_addr(bus_number, devfn, where); ++ ++ data = ifx_pcie_cfg_rd(pcie_port, addr); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = le32_to_cpu(data); ++#endif ++ ++ data = ifx_pcie_size_to_value(where, size, data, tvalue); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ data = cpu_to_le32(data); ++#endif ++ ifx_pcie_cfg_wr(pcie_port, addr, data); ++ } ++ PCIE_IRQ_UNLOCK(ifx_pcie_lock); ++out: ++ return ret; ++} ++ ++static struct resource ifx_pcie_io_resource = { ++ .name = "PCIe0 I/O space", ++ .start = PCIE_IO_PHY_BASE, ++ .end = PCIE_IO_PHY_END, ++ .flags = IORESOURCE_IO, ++}; ++ ++static struct resource ifx_pcie_mem_resource = { ++ .name = "PCIe0 Memory space", ++ .start = PCIE_MEM_PHY_BASE, ++ .end = PCIE_MEM_PHY_END, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct pci_ops ifx_pcie_ops = { ++ .read = ifx_pcie_read_config, ++ .write = ifx_pcie_write_config, ++}; ++ ++static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { ++ { ++ .pcic = { ++ .pci_ops = &ifx_pcie_ops, ++ .mem_resource = &ifx_pcie_mem_resource, ++ .io_resource = &ifx_pcie_io_resource, ++ }, ++ .port = IFX_PCIE_PORT0, ++ }, ++}; ++ ++#ifdef IFX_PCIE_ERROR_INT ++ ++static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) ++{ ++ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; ++ int pcie_port = ctrl->port; ++ u32 reg; ++ ++ pr_debug("PCIe RC error intr %d\n", irq); ++ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); ++ reg &= PCIE_RC_CORE_COMBINED_INT; ++ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ++pcie_rc_core_int_init(int pcie_port) ++{ ++ int ret; ++ ++ /* Enable core interrupt */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); ++ ++ /* Clear it first */ ++ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); ++ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, ++ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); ++ if (ret) ++ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); ++ ++ return ret; ++} ++#endif ++ ++int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ u32 irq_bit = 0; ++ int irq = 0; ++ struct ifx_pci_controller *ctrl = dev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); ++ ++ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { ++ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); ++ return -1; ++ } ++ ++ /* Pin index so minus one */ ++ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; ++ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); ++ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); ++ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); ++ return irq; ++} ++ ++int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) ++{ ++ u16 config; ++#ifdef IFX_PCIE_ERROR_INT ++ u32 dconfig; ++ int pos; ++#endif ++ ++ /* Enable reporting System errors and parity errors on all devices */ ++ /* Enable parity checking and error reporting */ ++ pci_read_config_word(dev, PCI_COMMAND, &config); ++ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_FAST_BACK*/; ++ pci_write_config_word(dev, PCI_COMMAND, config); ++ ++ if (dev->subordinate) { ++ /* Set latency timers on sub bridges */ ++ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ ++ /* More bridge error detection */ ++ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); ++ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; ++ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); ++ } ++#ifdef IFX_PCIE_ERROR_INT ++ /* Enable the PCIe normal error reporting */ ++ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); ++ if (pos) { ++ ++ /* Disable system error generation in response to error messages */ ++ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); ++ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); ++ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); ++ ++ /* Clear PCIE Capability's Device Status */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); ++ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); ++ ++ /* Update Device Control */ ++ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); ++ /* Correctable Error Reporting */ ++ config |= PCI_EXP_DEVCTL_CERE; ++ /* Non-Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_NFERE; ++ /* Fatal Error Reporting */ ++ config |= PCI_EXP_DEVCTL_FERE; ++ /* Unsupported Request */ ++ config |= PCI_EXP_DEVCTL_URRE; ++ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); ++ } ++ ++ /* Find the Advanced Error Reporting capability */ ++ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); ++ if (pos) { ++ /* Clear Uncorrectable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); ++ /* Enable reporting of all uncorrectable errors */ ++ /* Uncorrectable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); ++ /* ++ * Leave severity at HW default. This only controls if ++ * errors are reported as uncorrectable or ++ * correctable, not if the error is reported. ++ */ ++ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ ++ /* Clear Correctable Error Status */ ++ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); ++ /* Enable reporting of all correctable errors */ ++ /* Correctable Error Mask - turned on bits disable errors */ ++ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); ++ /* Advanced Error Capabilities */ ++ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); ++ /* ECRC Generation Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { ++ dconfig |= PCI_ERR_CAP_ECRC_GENE; ++ } ++ /* ECRC Check Enable */ ++ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { ++ dconfig |= PCI_ERR_CAP_ECRC_CHKE; ++ } ++ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); ++ ++ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ ++ /* Enable Root Port's interrupt in response to error messages */ ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, ++ PCI_ERR_ROOT_CMD_COR_EN | ++ PCI_ERR_ROOT_CMD_NONFATAL_EN | ++ PCI_ERR_ROOT_CMD_FATAL_EN); ++ /* Clear the Root status register */ ++ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); ++ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); ++ } ++#endif /* IFX_PCIE_ERROR_INT */ ++ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ ++ pcie_set_readrq(dev, 128); ++ return 0; ++} ++ ++static int ++pcie_rc_initialize(int pcie_port) ++{ ++ int i; ++#define IFX_PCIE_PHY_LOOP_CNT 5 ++ ++ pcie_rcu_endian_setup(pcie_port); ++ ++ pcie_ep_gpio_rst_init(pcie_port); ++ ++ /* ++ * XXX, PCIe elastic buffer bug will cause not to be detected. One more ++ * reset PCIe PHY will solve this issue ++ */ ++ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { ++ /* Disable PCIe PHY Analog part for sanity check */ ++ pcie_phy_pmu_disable(pcie_port); ++ ++ pcie_phy_rst_assert(pcie_port); ++ pcie_phy_rst_deassert(pcie_port); ++ ++ /* Make sure PHY PLL is stable */ ++ udelay(20); ++ ++ /* PCIe Core reset enabled, low active, sw programmed */ ++ pcie_core_rst_assert(pcie_port); ++ ++ /* Put PCIe EP in reset status */ ++ pcie_device_rst_assert(pcie_port); ++ ++ /* PCI PHY & Core reset disabled, high active, sw programmed */ ++ pcie_core_rst_deassert(pcie_port); ++ ++ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ ++ pcie_phy_clock_mode_setup(pcie_port); ++ ++ /* Enable PCIe PHY and Clock */ ++ pcie_core_pmu_setup(pcie_port); ++ ++ /* Clear status registers */ ++ pcie_status_register_clear(pcie_port); ++ ++#ifdef CONFIG_PCI_MSI ++ pcie_msi_init(pcie_port); ++#endif /* CONFIG_PCI_MSI */ ++ pcie_rc_cfg_reg_setup(pcie_port); ++ ++ /* Once link is up, break out */ ++ if (pcie_app_loigc_setup(pcie_port) == 0) ++ break; ++ } ++ if (i >= IFX_PCIE_PHY_LOOP_CNT) { ++ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); ++ return -EIO; ++ } ++ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ ++ pcie_replay_time_update(pcie_port); ++ return 0; ++} ++ ++static int __init ifx_pcie_bios_init(void) ++{ ++ void __iomem *io_map_base; ++ int pcie_port; ++ int startup_port; ++ ++ /* Enable AHB Master/ Slave */ ++ pcie_ahb_pmu_setup(); ++ ++ startup_port = IFX_PCIE_PORT0; ++ ++ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ ++ if (pcie_rc_initialize(pcie_port) == 0) { ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", ++ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); ++ /* Otherwise, warning will pop up */ ++ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); ++ if (io_map_base == NULL) { ++ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); ++ return -ENOMEM; ++ } ++ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; ++ ++ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); ++ /* XXX, clear error status */ ++ ++ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", ++ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, ++ &ifx_pcie_controller[pcie_port].pcic.io_resource); ++ ++ #ifdef IFX_PCIE_ERROR_INT ++ pcie_rc_core_int_init(pcie_port); ++ #endif /* IFX_PCIE_ERROR_INT */ ++ } ++ } ++ ++ return 0; ++} ++arch_initcall(ifx_pcie_bios_init); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); ++MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie.h +@@ -0,0 +1,135 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_H ++#define IFXMIPS_PCIE_H ++#include ++#include ++#include ++#include ++#include "ifxmips_pci_common.h" ++#include "ifxmips_pcie_reg.h" ++ ++/*! ++ \defgroup IFX_PCIE PCI Express bus driver module ++ \brief PCI Express IP module support VRX200 ++*/ ++ ++/*! ++ \defgroup IFX_PCIE_OS OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module common header file ++*/ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++#define CONFIG_VR9 ++ ++#ifdef CONFIG_VR9 ++#include "ifxmips_pcie_vr9.h" ++#elif defined (CONFIG_AR10) ++#include "ifxmips_pcie_ar10.h" ++#else ++#error "PCIE: platform not defined" ++#endif /* CONFIG_VR9 */ ++ ++#endif /* IFXMIPS_PCIE_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_ar10.h +@@ -0,0 +1,290 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_ar10.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver ar10 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_AR10_H ++#define IFXMIPS_PCIE_AR10_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++ ++/* Project header file */ ++#include ++#include ++#include ++#include ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ifx_ebu_led_enable(); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* XXX, moved to CGU to control AHBM */ ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Inbound, big endian */ ++ reg |= IFX_RCU_BE_AHB4S; ++ if (pcie_port == 0) { ++ reg |= IFX_RCU_BE_PCIE0M; ++ ++ #ifdef CONFIG_IFX_PCIE_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE0S; ++ #endif ++ } ++ else { ++ reg |= IFX_RCU_BE_PCIE1M; ++ #ifdef CONFIG_IFX_PCIE1_HW_SWAP ++ /* Outbound, software swap needed */ ++ reg |= IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #else ++ /* Outbound little endian */ ++ reg &= ~IFX_RCU_BE_AHB3M; ++ reg &= ~IFX_RCU_BE_PCIE1S; ++ #endif ++ } ++ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ if (pcie_port == 0) { /* XXX, should use macro*/ ++ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++ else { ++ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++ } ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ if (pcie_port == 0) { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE0_PDI; ++ } ++ else { ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_BE_PCIE1_PDI; ++ } ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ /* Enable PDI to access PCIe PHY register */ ++ PDI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PDI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset Core, bit 22 */ ++ if (pcie_port == 0) { ++ reg |= 0x00400000; ++ } ++ else { ++ reg |= 0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00400000; /* bit 22 */ ++ } ++ else { ++ reg &= ~0x08000000; /* Bit 27 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg |= 0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg |= 0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ if (pcie_port == 0) { ++ reg &= ~0x00001000; /* Bit 12 */ ++ } ++ else { ++ reg &= ~0x00002000; /* Bit 13 */ ++ } ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 0); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 0); ++ } ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ if (pcie_port == 0) { ++ ifx_ebu_led_set_data(11, 1); ++ } ++ else { ++ ifx_ebu_led_set_data(12, 1); ++ } ++ ifx_ebu_led_disable(); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ if (pcie_port == 0) { ++ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ pcie_msi_pic_init(pcie_port); ++ if (pcie_port == 0) { ++ MSI0_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++ else { ++ MSI1_PMU_SETUP(IFX_PMU_ENABLE); ++ } ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++ } ++#endif /* CONFIG_IFX_PCI */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ } ++ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_IFX_PCIE_2ND_CORE ++ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_AR10_H */ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_msi.c +@@ -0,0 +1,392 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_msi.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCI MSI sub module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe MSI Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 02 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_MSI MSI OS APIs ++ \ingroup IFX_PCIE ++ \brief PCIe bus driver OS interface functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_msi.c ++ \ingroup IFX_PCIE ++ \brief PCIe MSI OS interface file ++*/ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++#define IFX_MSI_IRQ_NUM 16 ++ ++enum { ++ IFX_PCIE_MSI_IDX0 = 0, ++ IFX_PCIE_MSI_IDX1, ++ IFX_PCIE_MSI_IDX2, ++ IFX_PCIE_MSI_IDX3, ++}; ++ ++typedef struct ifx_msi_irq_idx { ++ const int irq; ++ const int idx; ++}ifx_msi_irq_idx_t; ++ ++struct ifx_msi_pic { ++ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; ++ volatile u32 pic_endian; /* 0x40 */ ++}; ++typedef struct ifx_msi_pic *ifx_msi_pic_t; ++ ++typedef struct ifx_msi_irq { ++ const volatile ifx_msi_pic_t msi_pic_p; ++ const u32 msi_phy_base; ++ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; ++ /* ++ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is ++ * in use. ++ */ ++ u16 msi_free_irq_bitmask; ++ ++ /* ++ * Each bit in msi_multiple_irq_bitmask tells that the device using ++ * this bit in msi_free_irq_bitmask is also using the next bit. This ++ * is used so we can disable all of the MSI interrupts when a device ++ * uses multiple. ++ */ ++ u16 msi_multiple_irq_bitmask; ++}ifx_msi_irq_t; ++ ++static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, ++ .msi_phy_base = PCIE_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ }, ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ { ++ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, ++ .msi_phy_base = PCIE1_MSI_PHY_BASE, ++ .msi_irq_idx = { ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, ++ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, ++ }, ++ .msi_free_irq_bitmask = 0, ++ .msi_multiple_irq_bitmask= 0, ++ ++ }, ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++}; ++ ++/* ++ * This lock controls updates to msi_free_irq_bitmask, ++ * msi_multiple_irq_bitmask and pic register settting ++ */ ++static DEFINE_SPINLOCK(ifx_pcie_msi_lock); ++ ++void pcie_msi_pic_init(int pcie_port) ++{ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; ++ spin_unlock(&ifx_pcie_msi_lock); ++} ++ ++/** ++ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++ * \brief Called when a driver request MSI interrupts instead of the ++ * legacy INT A-D. This routine will allocate multiple interrupts ++ * for MSI devices that support them. A device can override this by ++ * programming the MSI control bits [6:4] before calling ++ * pci_enable_msi(). ++ * ++ * \param[in] pdev Device requesting MSI interrupts ++ * \param[in] desc MSI descriptor ++ * ++ * \return -EINVAL Invalid pcie root port or invalid msi bit ++ * \return 0 OK ++ * \ingroup IFX_PCIE_MSI ++ */ ++int ++arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ++{ ++ int irq, pos; ++ u16 control; ++ int irq_idx; ++ int irq_step; ++ int configured_private_bits; ++ int request_private_bits; ++ struct msi_msg msg; ++ u16 search_mask; ++ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; ++ int pcie_port = ctrl->port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); ++ ++ /* XXX, skip RC MSI itself */ ++ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Read the MSI config to figure out how many IRQs this device ++ * wants. Most devices only want 1, which will give ++ * configured_private_bits and request_private_bits equal 0. ++ */ ++ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); ++ ++ /* ++ * If the number of private bits has been configured then use ++ * that value instead of the requested number. This gives the ++ * driver the chance to override the number of interrupts ++ * before calling pci_enable_msi(). ++ */ ++ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; ++ if (configured_private_bits == 0) { ++ /* Nothing is configured, so use the hardware requested size */ ++ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; ++ } ++ else { ++ /* ++ * Use the number of configured bits, assuming the ++ * driver wanted to override the hardware request ++ * value. ++ */ ++ request_private_bits = configured_private_bits; ++ } ++ ++ /* ++ * The PCI 2.3 spec mandates that there are at most 32 ++ * interrupts. If this device asks for more, only give it one. ++ */ ++ if (request_private_bits > 5) { ++ request_private_bits = 0; ++ } ++again: ++ /* ++ * The IRQs have to be aligned on a power of two based on the ++ * number being requested. ++ */ ++ irq_step = (1 << request_private_bits); ++ ++ /* Mask with one bit for each IRQ */ ++ search_mask = (1 << irq_step) - 1; ++ ++ /* ++ * We're going to search msi_free_irq_bitmask_lock for zero ++ * bits. This represents an MSI interrupt number that isn't in ++ * use. ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { ++ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; ++ break; ++ } ++ } ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ /* Make sure the search for available interrupts didn't fail */ ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ if (request_private_bits) { ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " ++ "interrupts, trying just one", __func__, 1 << request_private_bits); ++ request_private_bits = 0; ++ goto again; ++ } ++ else { ++ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); ++ return -EINVAL; ++ } ++ } ++ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; ++ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); ++ ++ /* ++ * Initialize MSI. This has to match the memory-write endianess from the device ++ * Address bits [23:12] ++ */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | ++ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | ++ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ ++ /* Enable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; ++ spin_unlock(&ifx_pcie_msi_lock); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", ++ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); ++ ++ /* Update the number of IRQs the device has available to it */ ++ control &= ~PCI_MSI_FLAGS_QSIZE; ++ control |= (request_private_bits << 4); ++ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); ++ ++ set_irq_msi(irq, desc); ++ msg.address_hi = 0x0; ++ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; ++ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); ++ ++ write_msi_msg(irq, &msg); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++ return 0; ++} ++ ++static int ++pcie_msi_irq_to_port(unsigned int irq, int *port) ++{ ++ int ret = 0; ++ ++ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || ++ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { ++ *port = IFX_PCIE_PORT0; ++ } ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || ++ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { ++ *port = IFX_PCIE_PORT1; ++ } ++#endif /* CONFIG_IFX_PCIE_2ND_CORE */ ++ else { ++ printk(KERN_ERR "%s: Attempted to teardown illegal " ++ "MSI interrupt (%d)\n", __func__, irq); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/** ++ * \fn void arch_teardown_msi_irq(unsigned int irq) ++ * \brief Called when a device no longer needs its MSI interrupts. All ++ * MSI interrupts for the device are freed. ++ * ++ * \param irq The devices first irq number. There may be multple in sequence. ++ * \return none ++ * \ingroup IFX_PCIE_MSI ++ */ ++void ++arch_teardown_msi_irq(unsigned int irq) ++{ ++ int pos; ++ int number_irqs; ++ u16 bitmask; ++ int pcie_port; ++ ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); ++ ++ BUG_ON(irq > INT_NUM_IM4_IRL31); ++ ++ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { ++ return; ++ } ++ ++ /* Shift the mask to the correct bit location, not always correct ++ * Probally, the first match will be chosen. ++ */ ++ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { ++ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) ++ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { ++ break; ++ } ++ } ++ if (pos >= IFX_MSI_IRQ_NUM) { ++ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); ++ return; ++ } ++ spin_lock(&ifx_pcie_msi_lock); ++ /* Disable this entry */ ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; ++ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); ++ spin_unlock(&ifx_pcie_msi_lock); ++ /* ++ * Count the number of IRQs we need to free by looking at the ++ * msi_multiple_irq_bitmask. Each bit set means that the next ++ * IRQ is also owned by this device. ++ */ ++ number_irqs = 0; ++ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && ++ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { ++ number_irqs++; ++ } ++ number_irqs++; ++ ++ /* Mask with one bit for each IRQ */ ++ bitmask = (1 << number_irqs) - 1; ++ ++ bitmask <<= pos; ++ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { ++ printk(KERN_ERR "%s: Attempted to teardown MSI " ++ "interrupt (%d) not in use\n", __func__, irq); ++ return; ++ } ++ /* Checks are done, update the in use bitmask */ ++ spin_lock(&ifx_pcie_msi_lock); ++ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; ++ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); ++ spin_unlock(&ifx_pcie_msi_lock); ++ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); ++} ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); ++MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); ++MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_phy.c +@@ -0,0 +1,478 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_phy.c ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe PHY sub module ++** ++** DATE : 14 May 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 14 May,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_phy.c ++ \ingroup IFX_PCIE ++ \brief PCIe PHY PLL register programming source file ++*/ ++#include ++#include ++#include ++#include ++ ++#include "ifxmips_pcie_reg.h" ++#include "ifxmips_pcie.h" ++ ++/* PCIe PDI only supports 16 bit operation */ ++ ++#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ ++ ((*(volatile u16 *) (__addr)) = (__data)) ++ ++#define IFX_PCIE_PHY_REG_READ16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG16(__addr) \ ++ (*(volatile u16 *) (__addr)) ++ ++#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ ++ u16 read_data; \ ++ u16 write_data; \ ++ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ ++ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ ++ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ ++} while (0) ++ ++#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ ++ ++//#define IFX_PCI_PHY_REG_DUMP ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++static void ++pcie_phy_reg_dump(int pcie_port) ++{ ++ printk("PLL REGFILE\n"); ++ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); ++ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); ++ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); ++ ++ printk("TX1 REGFILE\n"); ++ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); ++ ++ printk("TX2 REGFILE\n"); ++ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); ++ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); ++ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); ++ ++ printk("RX1 REGFILE\n"); ++ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); ++ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); ++ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); ++ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); ++ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); ++} ++#endif /* IFX_PCI_PHY_REG_DUMP */ ++ ++static void ++pcie_phy_comm_setup(int pcie_port) ++{ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* Improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* Reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++} ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++static void ++pcie_phy_36mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE ++static void ++pcie_phy_36mhz_ssc_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ ++ /* PLL Setting */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); ++ ++ /* Increase the bias reference voltage */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); ++ ++ /* Endcnt */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); ++ ++ /* Force */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); ++ ++ /* Predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); ++ ++ /* ctrl_lim */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); ++ ++ /* ctrl */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); ++ ++ /* predrv_ser_en */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); ++ ++ /* RTERM*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); ++ ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); ++ ++ /* improved 100MHz clock output */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); ++ ++ /* reduced CDR BW to avoid glitches */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE ++static void ++pcie_phy_25mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); ++ ++ /* en_ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ ++ ++#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE ++static void ++pcie_phy_100mhz_mode_setup(int pcie_port) ++{ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++ /* en_ext_mmd_div_ratio */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); ++ ++ /* ext_mmd_div_ratio*/ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); ++ ++ /* pll_ensdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); ++ ++ /* en_const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); ++ ++ /* mmd */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); ++ ++ /* lf_mode */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); ++ ++ /* const_sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); ++ ++ /* const sdm */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); ++ ++ /* pllmod */ ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); ++ ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); ++} ++#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ ++ ++static int ++pcie_phy_wait_startup_ready(int pcie_port) ++{ ++ int i; ++ ++ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { ++ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { ++ break; ++ } ++ udelay(10); ++ } ++ if (i >= IFX_PCIE_PLL_TIMEOUT) { ++ printk(KERN_ERR "%s PLL Link timeout\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ ++static void ++pcie_phy_load_enable(int pcie_port, int slice) ++{ ++ /* Set the load_en of tx/rx slice to '1' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_disable(int pcie_port, int slice) ++{ ++ /* set the load_en of tx/rx slice to '0' */ ++ switch (slice) { ++ case 1: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 2: ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); ++ break; ++ case 3: ++ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); ++ break; ++ } ++} ++ ++static void ++pcie_phy_load_war(int pcie_port) ++{ ++ int slice; ++ ++ for (slice = 1; slice < 4; slice++) { ++ pcie_phy_load_enable(pcie_port, slice); ++ udelay(1); ++ pcie_phy_load_disable(pcie_port, slice); ++ } ++} ++ ++static void ++pcie_phy_tx2_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx1_modulation(int pcie_port) ++{ ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); ++ mdelay(1); ++ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); ++} ++ ++static void ++pcie_phy_tx_modulation_war(int pcie_port) ++{ ++ int i; ++ ++#define PCIE_PHY_MODULATION_NUM 5 ++ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { ++ pcie_phy_tx2_modulation(pcie_port); ++ pcie_phy_tx1_modulation(pcie_port); ++ } ++#undef PCIE_PHY_MODULATION_NUM ++} ++ ++void ++pcie_phy_clock_mode_setup(int pcie_port) ++{ ++ pcie_pdi_big_endian(pcie_port); ++ ++ /* Enable PDI to access PCIe PHY register */ ++ pcie_pdi_pmu_enable(pcie_port); ++ ++ /* Configure PLL and PHY clock */ ++ pcie_phy_comm_setup(pcie_port); ++ ++#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ pcie_phy_36mhz_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) ++ pcie_phy_36mhz_ssc_mode_setup(pcie_port); ++#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) ++ pcie_phy_25mhz_mode_setup(pcie_port); ++#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) ++ pcie_phy_100mhz_mode_setup(pcie_port); ++#else ++ #error "PCIE PHY Clock Mode must be chosen first!!!!" ++#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ ++ ++ /* Enable PCIe PHY and make PLL setting take effect */ ++ pcie_phy_pmu_enable(pcie_port); ++ ++ /* Check if we are in startup_ready status */ ++ pcie_phy_wait_startup_ready(pcie_port); ++ ++ pcie_phy_load_war(pcie_port); ++ ++ /* Apply TX modulation workarounds */ ++ pcie_phy_tx_modulation_war(pcie_port); ++ ++#ifdef IFX_PCI_PHY_REG_DUMP ++ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); ++ pcie_phy_reg_dump(pcie_port); ++#endif ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.c +@@ -0,0 +1,176 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.c ++** PROJECT : IFX UEIP ++** MODULES : PCIE Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIE Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \defgroup IFX_PCIE_PM Power Management functions ++ \ingroup IFX_PCIE ++ \brief IFX PCIE Root Complex Driver power management functions ++*/ ++ ++/*! ++ \file ifxmips_pcie_pm.c ++ \ingroup IFX_PCIE ++ \brief source file for PCIE Root Complex Driver Power Management ++*/ ++ ++#ifndef EXPORT_SYMTAB ++#define EXPORT_SYMTAB ++#endif ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++ ++/* Project header */ ++#include ++#include ++#include ++#include ++#include "ifxmips_pcie_pm.h" ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++ * \brief the callback function to request pmcu state in the power management hardware-dependent module ++ * ++ * \param pmcuState This parameter is a PMCU state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) ++{ ++ switch(pmcuState) ++ { ++ case IFX_PMCU_STATE_D0: ++ return IFX_PMCU_RETURN_SUCCESS; ++ case IFX_PMCU_STATE_D1: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D2: // Not Applicable ++ return IFX_PMCU_RETURN_DENIED; ++ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating ++ return IFX_PMCU_RETURN_SUCCESS; ++ default: ++ return IFX_PMCU_RETURN_DENIED; ++ } ++} ++ ++/** ++ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++ * \brief the callback function to get pmcu state in the power management hardware-dependent module ++ ++ * \param pmcuState Pointer to return power state. ++ * ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule ++ * ++ * \param pmcuModule Module ++ * \param newState New state ++ * \param oldState Old state ++ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully ++ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. ++ * \ingroup IFX_PCIE_PM ++ */ ++static IFX_PMCU_RETURN_t ++ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) ++{ ++ return IFX_PMCU_RETURN_SUCCESS; ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_init(void) ++ * \brief Register with central PMCU module ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_init(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuRegister; ++ ++ /* XXX, hook driver context */ ++ ++ /* State function register */ ++ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); ++ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuRegister.pmcuModuleNr = 0; ++ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; ++ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; ++ pmcuRegister.pre = ifx_pcie_pmcu_prechange; ++ pmcuRegister.post= ifx_pcie_pmcu_postchange; ++ ifx_pmcu_register(&pmcuRegister); ++} ++ ++/** ++ * \fn static void ifx_pcie_pmcu_exit(void) ++ * \brief Unregister with central PMCU module ++ * ++ * \return none ++ * \ingroup IFX_PCIE_PM ++ */ ++void ++ifx_pcie_pmcu_exit(void) ++{ ++ IFX_PMCU_REGISTER_t pmcuUnRegister; ++ ++ /* XXX, hook driver context */ ++ ++ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; ++ pmcuUnRegister.pmcuModuleNr = 0; ++ ifx_pmcu_unregister(&pmcuUnRegister); ++} ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_pm.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_pm.h ++** PROJECT : IFX UEIP ++** MODULES : PCIe Root Complex Driver ++** ++** DATE : 21 Dec 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver Power Managment ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 Dec,2009 Lei Chuanhua First UEIP release ++*******************************************************************************/ ++/*! ++ \file ifxmips_pcie_pm.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe Root Complex Driver Power Management ++*/ ++ ++#ifndef IFXMIPS_PCIE_PM_H ++#define IFXMIPS_PCIE_PM_H ++ ++void ifx_pcie_pmcu_init(void); ++void ifx_pcie_pmcu_exit(void); ++ ++#endif /* IFXMIPS_PCIE_PM_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_reg.h +@@ -0,0 +1,1001 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#endif /* IFXMIPS_PCIE_REG_H */ ++ +--- /dev/null ++++ b/arch/mips/pci/ifxmips_pcie_vr9.h +@@ -0,0 +1,269 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++/*! ++ \file ifxmips_pcie_vr9.h ++ \ingroup IFX_PCIE ++ \brief PCIe RC driver vr9 specific file ++*/ ++ ++#ifndef IFXMIPS_PCIE_VR9_H ++#define IFXMIPS_PCIE_VR9_H ++ ++#include ++#include ++ ++#include ++#include ++ ++#define IFX_PCIE_GPIO_RESET 494 ++ ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) ++#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) ++#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) ++#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) ++#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++ ++ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ ++/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ /* Enable AHB bus master/slave */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ahb"); ++ clk_enable(clk); ++ ++ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); ++ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_enable(clk); ++ ++ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_phy_pmu_disable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "phy"); ++ clk_disable(clk); ++ ++// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); ++} ++ ++static inline void pcie_pdi_big_endian(int pcie_port) ++{ ++ u32 reg; ++ ++ /* SRAM2PDI endianness control. */ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++ /* Config AHB->PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ /* Enable PDI to access PCIe PHY register */ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "pdi"); ++ clk_enable(clk); ++ //PDI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_core_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ ++ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ ++ reg |= 0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_core_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ /* Reset PCIe PHY & Core, bit 22 */ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00400000; ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_assert(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg |= 0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_phy_rst_deassert(int pcie_port) ++{ ++ u32 reg; ++ ++ /* Make sure one micro-second delay */ ++ udelay(1); ++ ++ reg = IFX_REG_R32(IFX_RCU_RST_REQ); ++ reg &= ~0x00001000; /* Bit 12 */ ++ IFX_REG_W32(reg, IFX_RCU_RST_REQ); ++} ++ ++static inline void pcie_device_rst_assert(int pcie_port) ++{ ++ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); ++// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_device_rst_deassert(int pcie_port) ++{ ++ mdelay(100); ++ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); ++// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); ++ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); ++} ++ ++static inline void pcie_core_pmu_setup(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("1d900000.pcie", "ctl"); ++ clk_enable(clk); ++ clk = clk_get_sys("1d900000.pcie", "bus"); ++ clk_enable(clk); ++ ++ /* PCIe Core controller enabled */ ++// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); ++ ++ /* Enable PCIe L0 Clock */ ++// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline void pcie_msi_init(int pcie_port) ++{ ++ struct clk *clk; ++ pcie_msi_pic_init(pcie_port); ++ clk = clk_get_sys("ltq_pcie", "msi"); ++ clk_enable(clk); ++// MSI_PMU_SETUP(IFX_PMU_ENABLE); ++} ++ ++static inline u32 ++ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) ++{ ++ u32 tbus_number = bus_number; ++ ++#ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/arch/mips/pci/pci.c ++++ b/arch/mips/pci/pci.c +@@ -256,6 +256,31 @@ static int __init pcibios_init(void) + + subsys_initcall(pcibios_init); + ++int pcibios_host_nr(void) ++{ ++ int count; ++ struct pci_controller *hose; ++ for (count = 0, hose = hose_head; hose; hose = hose->next, count++) { ++ ; ++ } ++ return count; ++} ++EXPORT_SYMBOL(pcibios_host_nr); ++ ++int pcibios_1st_host_bus_nr(void) ++{ ++ int bus_nr = 0; ++ struct pci_controller *hose = hose_head; ++ ++ if (hose != NULL) { ++ if (hose->bus != NULL) { ++ bus_nr = hose->bus->number + 1; ++ } ++ } ++ return bus_nr; ++} ++EXPORT_SYMBOL(pcibios_1st_host_bus_nr); ++ + static int pcibios_enable_resources(struct pci_dev *dev, int mask) + { + u16 cmd, old_cmd; +--- /dev/null ++++ b/arch/mips/pci/pcie-lantiq.h +@@ -0,0 +1,1305 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifxmips_pcie_reg.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : PCIe module ++** ++** DATE : 02 Mar 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : PCIe Root Complex Driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Version $Date $Author $Comment ++** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++#ifndef IFXMIPS_PCIE_REG_H ++#define IFXMIPS_PCIE_REG_H ++#include ++#include ++#include ++#include ++/*! ++ \file ifxmips_pcie_reg.h ++ \ingroup IFX_PCIE ++ \brief header file for PCIe module register definition ++*/ ++/* PCIe Address Mapping Base */ ++#define PCIE_CFG_PHY_BASE 0x1D000000UL ++#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) ++#define PCIE_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE_MEM_PHY_BASE 0x1C000000UL ++#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) ++#define PCIE_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) ++ ++#define PCIE_IO_PHY_BASE 0x1D800000UL ++#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) ++#define PCIE_IO_SIZE (1 * 1024 * 1024) ++#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) ++ ++#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) ++#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) ++#define PCIE_MSI_PHY_BASE 0x1F600000UL ++ ++#define PCIE_PDI_PHY_BASE 0x1F106800UL ++#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) ++#define PCIE_PDI_SIZE 0x400 ++ ++#define PCIE1_CFG_PHY_BASE 0x19000000UL ++#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) ++#define PCIE1_CFG_SIZE (8 * 1024 * 1024) ++ ++#define PCIE1_MEM_PHY_BASE 0x18000000UL ++#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) ++#define PCIE1_MEM_SIZE (16 * 1024 * 1024) ++#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) ++ ++#define PCIE1_IO_PHY_BASE 0x19800000UL ++#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) ++#define PCIE1_IO_SIZE (1 * 1024 * 1024) ++#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) ++ ++#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) ++#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) ++#define PCIE1_MSI_PHY_BASE 0x1F400000UL ++ ++#define PCIE1_PDI_PHY_BASE 0x1F700400UL ++#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) ++#define PCIE1_PDI_SIZE 0x400 ++ ++#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) ++#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) ++#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) ++#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) ++#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) ++#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) ++#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) ++#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) ++#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) ++ ++/* PCIe Application Logic Register */ ++/* RC Core Control Register */ ++#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) ++/* This should be enabled after initializing configuratin registers ++ * Also should check link status retraining bit ++ */ ++#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ ++ ++/* RC Core Debug Register */ ++#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) ++#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ ++#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ ++#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 ++ ++#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ ++#define PCIE_RC_DR_PM_DEV_STATE_S 9 ++ ++#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ ++#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ ++#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ ++ ++/* Current Power State Definition */ ++enum { ++ PCIE_RC_DR_D0 = 0, ++ PCIE_RC_DR_D1, /* Not supported */ ++ PCIE_RC_DR_D2, /* Not supported */ ++ PCIE_RC_DR_D3, ++ PCIE_RC_DR_UN, ++}; ++ ++/* PHY Link Status Register */ ++#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) ++#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ ++ ++/* Electromechanical Control Register */ ++#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) ++#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ ++#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ ++#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ ++#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ ++#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ ++#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ ++#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ ++#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ ++ ++/* Interrupt Status Register */ ++#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) ++#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ ++#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ ++#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ ++#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ ++#define PCIE_IR_SR_AHB_LU_ERR_S 4 ++#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ ++#define PCIE_IR_SR_INT_MSG_NUM_S 9 ++#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 ++ ++/* Message Control Register */ ++#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) ++#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ ++#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ ++ ++#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) ++ ++/* Vendor-Defined Message Requester ID Register */ ++#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) ++#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF ++#define PCIE_VDM_RID_VDMRID_S 0 ++ ++/* ASPM Control Register */ ++#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) ++#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ ++#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ ++#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ ++ ++/* Vendor Message DW0 Register */ ++#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) ++#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ ++#define PCIE_VM_MSG_DW0_TYPE_S 0 ++#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ ++#define PCIE_VM_MSG_DW0_FORMAT_S 5 ++#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ ++#define PCIE_VM_MSG_DW0_TC_S 12 ++#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ ++#define PCIE_VM_MSG_DW0_ATTR_S 18 ++#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ ++#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ ++#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ ++#define PCIE_VM_MSG_DW0_LEN_S 22 ++ ++/* Format Definition */ ++enum { ++ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ ++ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ ++ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ ++ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ ++}; ++ ++/* Traffic Class Definition */ ++enum { ++ PCIE_VM_MSG_TC0 = 0, ++ PCIE_VM_MSG_TC1, ++ PCIE_VM_MSG_TC2, ++ PCIE_VM_MSG_TC3, ++ PCIE_VM_MSG_TC4, ++ PCIE_VM_MSG_TC5, ++ PCIE_VM_MSG_TC6, ++ PCIE_VM_MSG_TC7, ++}; ++ ++/* Attributes Definition */ ++enum { ++ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ ++ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ ++ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ ++ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ ++}; ++ ++/* Payload Size Definition */ ++#define PCIE_VM_MSG_LEN_MIN 0 ++#define PCIE_VM_MSG_LEN_MAX 1024 ++ ++/* Vendor Message DW1 Register */ ++#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) ++#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ ++#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 ++#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ ++#define PCIE_VM_MSG_DW1_CODE_S 16 ++#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ ++#define PCIE_VM_MSG_DW1_TAG_S 24 ++ ++#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) ++#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) ++ ++/* Vendor Message Request Register */ ++#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) ++#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ ++ ++ ++/* AHB Slave Side Band Control Register */ ++#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) ++#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ ++#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ ++#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ ++#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ ++#define PCIE_AHB_SSB_REQ_ATTR_S 3 ++#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ ++#define PCIE_AHB_SSB_REQ_TC_S 5 ++ ++/* AHB Master SideBand Ctrl Register */ ++#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) ++#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ ++#define PCIE_AHB_MSB_RESP_ATTR_S 0 ++#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ ++#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ ++#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ ++#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ ++#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 ++ ++/* AHB Control Register, fixed bus enumeration exception */ ++#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) ++#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 ++ ++/* Interrupt Enalbe Register */ ++#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) ++#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) ++#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) ++ ++/* PCIe interrupt enable/control/capture register definition */ ++#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ ++#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ ++#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ ++#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ ++#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ ++#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ ++#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ ++#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ ++#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ ++#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ ++#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ ++#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ ++#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ ++#define PCIE_IRN_INTA 0x00002000 /* INTA */ ++#define PCIE_IRN_INTB 0x00004000 /* INTB */ ++#define PCIE_IRN_INTC 0x00008000 /* INTC */ ++#define PCIE_IRN_INTD 0x00010000 /* INTD */ ++#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ ++ ++#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ ++ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ ++ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ ++ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ ++ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) ++/* PCIe RC Configuration Register */ ++#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) ++ ++/* Bit definition from pci_reg.h */ ++#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) ++#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) ++#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ ++/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ ++#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ ++#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ ++ ++#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ ++/* Bus Number Register bits */ ++#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF ++#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 ++#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 ++#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 ++#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 ++#define PCIE_PNR_SUB_BUS_NUM_S 16 ++ ++/* IO Base/Limit Register bits */ ++#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ ++#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 ++#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 ++#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 ++#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 ++#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 ++ ++/* Non-prefetchable Memory Base/Limit Register bit */ ++#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ ++#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 ++#define PCIE_MBML_MEM_BASE_ADDR_S 4 ++#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 ++#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 ++ ++/* Prefetchable Memory Base/Limit Register bit */ ++#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ ++#define PCIE_PMBL_64BIT_ADDR 0x00000001 ++#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 ++#define PCIE_PMBL_UPPER_12BIT_S 4 ++#define PCIE_PMBL_E64MA 0x00010000 ++#define PCIE_PMBL_END_ADDR 0xFFF00000 ++#define PCIE_PMBL_END_ADDR_S 20 ++#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ ++#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ ++ ++/* I/O Base/Limit Upper 16 bits register */ ++#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 ++#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 ++ ++#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) ++#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) ++ ++/* Interrupt and Secondary Bridge Control Register */ ++#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) ++ ++#define PCIE_INTRBCTRL_INT_LINE 0x000000FF ++#define PCIE_INTRBCTRL_INT_LINE_S 0 ++#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 ++#define PCIE_INTRBCTRL_INT_PIN_S 8 ++#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ ++#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ ++#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ ++#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ ++#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ ++#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ ++/* Others are read only */ ++enum { ++ PCIE_INTRBCTRL_INT_NON = 0, ++ PCIE_INTRBCTRL_INTA, ++ PCIE_INTRBCTRL_INTB, ++ PCIE_INTRBCTRL_INTC, ++ PCIE_INTRBCTRL_INTD, ++}; ++ ++#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) ++ ++/* Power Management Control and Status Register */ ++#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) ++ ++#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ ++#define PCIE_PM_CSR_POWER_STATE_S 0 ++#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ ++#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ ++#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ ++ ++/* MSI Capability Register for EP */ ++#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) ++ ++#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ ++#define PCIE_MCAPR_MSI_CAP_ID_S 0 ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 ++#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ ++#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 ++#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ ++#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 ++#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ ++ ++/* MSI Message Address Register */ ++#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) ++ ++#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ ++ ++/* MSI Message Upper Address Register */ ++#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) ++ ++/* MSI Message Data Register */ ++#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) ++ ++#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ ++#define PCIE_MD_DATA_S 0 ++ ++/* PCI Express Capability Register */ ++#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) ++ ++#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ ++#define PCIE_XCAP_ID_S 0 ++#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ ++#define PCIE_XCAP_NEXT_CAP_S 8 ++#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ ++#define PCIE_XCAP_VER_S 16 ++#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ ++#define PCIE_XCAP_DEV_PORT_TYPE_S 20 ++#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ ++#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ ++#define PCIE_XCAP_MSG_INT_NUM_S 25 ++ ++/* Device Capability Register */ ++#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) ++ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ ++#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 ++#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ ++#define PCIE_DCAP_PHANTOM_FUNC_S 3 ++#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ ++#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ ++#define PCIE_DCAP_EP_L0S_LATENCY_S 6 ++#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ ++#define PCIE_DCAP_EP_L1_LATENCY_S 9 ++#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ ++ ++/* Maximum payload size supported */ ++enum { ++ PCIE_MAX_PAYLOAD_128 = 0, ++ PCIE_MAX_PAYLOAD_256, ++ PCIE_MAX_PAYLOAD_512, ++ PCIE_MAX_PAYLOAD_1024, ++ PCIE_MAX_PAYLOAD_2048, ++ PCIE_MAX_PAYLOAD_4096, ++}; ++ ++/* Device Control and Status Register */ ++#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) ++ ++#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ ++#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ ++#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ ++#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ ++#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 ++#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ ++#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ ++#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ ++#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ ++#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 ++#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ ++#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ ++#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ ++#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ ++#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ ++#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ ++ ++#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ ++ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ ++ PCIE_DCTLSYS_UR_REQ_EN) ++ ++/* Link Capability Register */ ++#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) ++#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ ++#define PCIE_LCAP_MAX_LINK_SPEED_S 0 ++#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ ++#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 ++#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ ++#define PCIE_LCAP_ASPM_LEVEL_S 10 ++#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ ++#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 ++#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ ++#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 ++#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ ++#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ ++#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ ++#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ ++#define PCIE_LCAP_PORT_NUM_S 24 ++ ++/* Maximum Length width definition */ ++#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 ++#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ ++#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 ++#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 ++#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 ++#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C ++#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 ++#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 ++ ++/* Active State Link PM definition */ ++enum { ++ PCIE_ASPM_RES0 = 0, ++ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ ++ PCIE_ASPM_RES1, ++ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ ++}; ++ ++/* L0s Exit Latency definition */ ++enum { ++ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ ++ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ ++ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ ++ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ ++ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ ++ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ ++ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ ++ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ ++}; ++ ++/* L1 Exit Latency definition */ ++enum { ++ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ ++ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ ++ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ ++ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ ++ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ ++ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ ++ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ ++ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ ++}; ++ ++/* Link Control and Status Register */ ++#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) ++#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ ++#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 ++#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ ++#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ ++#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ ++#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ ++#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ ++#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ ++#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ ++#define PCIE_LCTLSTS_LINK_SPEED_S 16 ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ ++#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 ++#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ ++#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ ++#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ ++ ++/* Slot Capabilities Register */ ++#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) ++ ++/* Slot Capabilities */ ++#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) ++ ++/* Root Control and Capability Register */ ++#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) ++#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ ++#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ ++#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ ++#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ ++#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ ++ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) ++/* Root Status Register */ ++#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) ++#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ ++#define PCIE_RSTS_PME_REQ_ID_S 0 ++#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ ++#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ ++ ++/* PCI Express Enhanced Capability Header */ ++#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) ++#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ ++#define PCIE_ENHANCED_CAP_ID_S 0 ++#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ ++#define PCIE_ENHANCED_CAP_VER_S 16 ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ ++#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 ++ ++/* Uncorrectable Error Status Register */ ++#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) ++#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ ++#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ ++#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ ++#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ ++#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ ++#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ ++#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ ++#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ ++#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ ++#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ ++#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ ++#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ ++ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ ++ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ ++ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) ++ ++/* Uncorrectable Error Mask Register, Mask means no report */ ++#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) ++ ++/* Uncorrectable Error Severity Register */ ++#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) ++ ++/* Correctable Error Status Register */ ++#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) ++#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ ++#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ ++#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ ++#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ ++#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ ++#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ ++#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ ++ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) ++ ++/* Correctable Error Mask Register */ ++#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) ++ ++/* Advanced Error Capabilities and Control Register */ ++#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) ++#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ ++#define PCIE_AECCR_FIRST_ERR_PTR_S 0 ++#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ ++#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ ++#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ ++#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ ++ ++/* Header Log Register 1 */ ++#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) ++ ++/* Header Log Register 2 */ ++#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) ++ ++/* Header Log Register 3 */ ++#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) ++ ++/* Header Log Register 4 */ ++#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) ++ ++/* Root Error Command Register */ ++#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) ++#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ ++#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ ++#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ ++#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ ++ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) ++ ++/* Root Error Status Register */ ++#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) ++#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ ++#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ ++#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ ++#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ ++#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ ++#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ ++#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ ++#define PCIE_RESR_AER_INT_MSG_NUM_S 27 ++ ++/* Error Source Indentification Register */ ++#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF ++#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 ++#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 ++ ++/* VC Enhanced Capability Header */ ++#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) ++ ++/* Port VC Capability Register */ ++#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) ++#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ ++#define PCIE_PVC1_EXT_VC_CNT_S 0 ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ ++#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 ++#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ ++#define PCIE_PVC1_REF_CLK_S 8 ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ ++#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 ++ ++/* Extended Virtual Channel Count Defintion */ ++#define PCIE_EXT_VC_CNT_MIN 0 ++#define PCIE_EXT_VC_CNT_MAX 7 ++ ++/* Port Arbitration Table Entry Size Definition */ ++enum { ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, ++ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, ++}; ++ ++/* Port VC Capability Register 2 */ ++#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) ++#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ ++#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_PVC2_VC_ARB_WRR 0x0000000F ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ ++#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 ++ ++/* Port VC Control and Status Register */ ++#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) ++#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ ++#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ ++#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 ++#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ ++ ++/* VC0 Resource Capability Register */ ++#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) ++#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ ++#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ ++#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ ++ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ ++ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) ++ ++#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ ++#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ ++#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 ++ ++/* VC0 Resource Control Register */ ++#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) ++#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ ++#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ ++#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ ++#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ ++#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ ++#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ ++#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ ++#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ ++#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ ++ ++#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ ++#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 ++#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ ++#define PCIE_VC0_RC0_VC_ID_S 24 ++#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ ++ ++/* VC0 Resource Status Register */ ++#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) ++#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ ++#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ ++ ++/* Ack Latency Timer and Replay Timer Register */ ++#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ ++#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ ++#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 ++ ++/* Other Message Register */ ++#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) ++ ++/* Port Force Link Register */ ++#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) ++#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ ++#define PCIE_PFLR_LINK_NUM_S 0 ++#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ ++#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ ++#define PCIE_PFLR_LINK_STATE_S 16 ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ ++#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 ++ ++/* Ack Frequency Register */ ++#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) ++#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ ++#define PCIE_AFR_AF_S 0 ++#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ ++#define PCIE_AFR_FTS_NUM_S 8 ++#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ ++#define PCIE_AFR_COM_FTS_NUM_S 16 ++#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ ++#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 ++#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ ++#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 ++#define PCIE_AFR_FTS_NUM_DEFAULT 32 ++#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 ++#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 ++ ++/* Port Link Control Register */ ++#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) ++#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ ++#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ ++#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ ++#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ ++#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ ++#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ ++#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ ++#define PCIE_PLCR_LINK_MODE_S 16 ++#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ ++ ++/* Lane Skew Register */ ++#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) ++#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ ++#define PCIE_LSR_LANE_SKEW_NUM_S 0 ++#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ ++#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ ++#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ ++ ++/* Symbol Number Register */ ++#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) ++#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ ++#define PCIE_SNR_TS_S 0 ++#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ ++#define PCIE_SNR_SKP_S 8 ++#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ ++#define PCIE_SNR_REPLAY_TIMER_S 14 ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ ++#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 ++#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ ++#define PCIE_SNR_FC_TIMER_S 28 ++ ++/* Symbol Timer Register and Filter Mask Register 1 */ ++#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) ++#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ ++#define PCIE_STRFMR_SKP_INTERVAL_S 0 ++#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ ++#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ ++#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ ++#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ ++#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ ++#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ ++#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ ++#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ ++#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ ++#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ ++#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ ++#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ ++#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ ++ ++#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ ++ ++/* Filter Masker Register 2 */ ++#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) ++#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ ++#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ ++ ++/* Debug Register 0 */ ++#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) ++ ++/* Debug Register 1 */ ++#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) ++ ++/* Transmit Posted FC Credit Status Register */ ++#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ ++#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ ++#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Non-Posted FC Credit Status */ ++#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ ++#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ ++#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 ++ ++/* Transmit Complete FC Credit Status Register */ ++#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ ++#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ ++#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 ++ ++/* Queue Status Register */ ++#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) ++#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ ++#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ ++#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ ++ ++/* VC Transmit Arbitration Register 1 */ ++#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) ++#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ ++#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ ++ ++/* VC Transmit Arbitration Register 2 */ ++#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) ++#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ ++#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ ++ ++/* VC0 Posted Receive Queue Control Register */ ++#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ ++#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ ++#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ ++#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 ++#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ ++#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ ++ ++/* VC0 Non-Posted Receive Queue Control */ ++#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ ++#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ ++#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ ++#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 ++ ++/* VC0 Completion Receive Queue Control */ ++#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ ++#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ ++#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ ++#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 ++ ++/* Applicable to the above three registers */ ++enum { ++ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, ++ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, ++ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, ++}; ++ ++/* VC0 Posted Buffer Depth Register */ ++#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ ++#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ ++#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Non-Posted Buffer Depth Register */ ++#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ ++#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ ++#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 ++ ++/* VC0 Completion Buffer Depth Register */ ++#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ ++#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ ++#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 ++ ++/* PHY Status Register, all zeros in VR9 */ ++#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) ++ ++/* PHY Control Register, all zeros in VR9 */ ++#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) ++ ++/* ++ * PCIe PDI PHY register definition, suppose all the following ++ * stuff is confidential. ++ * XXX, detailed bit definition ++ */ ++#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) ++#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) ++#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) ++#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) ++#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) ++#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) ++#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) ++#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) ++#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) ++#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) ++#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) ++ ++#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) ++#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) ++#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) ++#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) ++#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) ++#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) ++#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) ++#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) ++ ++#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) ++#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) ++#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) ++#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) ++#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) ++#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) ++#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) ++ ++#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) ++#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) ++#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) ++#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) ++#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) ++ ++/* Interrupt related stuff */ ++#define PCIE_LEGACY_DISABLE 0 ++#define PCIE_LEGACY_INTA 1 ++#define PCIE_LEGACY_INTB 2 ++#define PCIE_LEGACY_INTC 3 ++#define PCIE_LEGACY_INTD 4 ++#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD ++ ++#define PCIE_IRQ_LOCK(lock) do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(&(lock), flags); ++#define PCIE_IRQ_UNLOCK(lock) \ ++ spin_unlock_irqrestore(&(lock), flags); \ ++} while (0) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#define PCIE_MSG_MSI 0x00000001 ++#define PCIE_MSG_ISR 0x00000002 ++#define PCIE_MSG_FIXUP 0x00000004 ++#define PCIE_MSG_READ_CFG 0x00000008 ++#define PCIE_MSG_WRITE_CFG 0x00000010 ++#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) ++#define PCIE_MSG_REG 0x00000020 ++#define PCIE_MSG_INIT 0x00000040 ++#define PCIE_MSG_ERR 0x00000080 ++#define PCIE_MSG_PHY 0x00000100 ++#define PCIE_MSG_ANY 0x000001ff ++ ++#define IFX_PCIE_PORT0 0 ++#define IFX_PCIE_PORT1 1 ++ ++#ifdef CONFIG_IFX_PCIE_2ND_CORE ++#define IFX_PCIE_CORE_NR 2 ++#else ++#define IFX_PCIE_CORE_NR 1 ++#endif ++ ++//#define IFX_PCIE_ERROR_INT ++ ++//#define IFX_PCIE_DBG ++ ++#if defined(IFX_PCIE_DBG) ++#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ ++ if (g_pcie_debug_flag & (_m)) { \ ++ ifx_pcie_debug((_fmt), ##args); \ ++ } \ ++} while (0) ++ ++#define INLINE ++#else ++#define IFX_PCIE_PRINT(_m, _fmt, args...) \ ++ do {} while(0) ++#define INLINE inline ++#endif ++ ++struct ifx_pci_controller { ++ struct pci_controller pcic; ++ ++ /* RC specific, per host bus information */ ++ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ ++}; ++ ++typedef struct ifx_pcie_ir_irq { ++ const unsigned int irq; ++ const char name[16]; ++}ifx_pcie_ir_irq_t; ++ ++typedef struct ifx_pcie_legacy_irq{ ++ const u32 irq_bit; ++ const int irq; ++}ifx_pcie_legacy_irq_t; ++ ++typedef struct ifx_pcie_irq { ++ ifx_pcie_ir_irq_t ir_irq; ++ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; ++}ifx_pcie_irq_t; ++ ++extern u32 g_pcie_debug_flag; ++extern void ifx_pcie_debug(const char *fmt, ...); ++extern void pcie_phy_clock_mode_setup(int pcie_port); ++extern void pcie_msi_pic_init(int pcie_port); ++extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); ++extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); ++ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define IFX_PCIE_GPIO_RESET 38 ++#define IFX_REG_R32 ltq_r32 ++#define IFX_REG_W32 ltq_w32 ++#define CONFIG_IFX_PCIE_HW_SWAP ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE ++ ++#define IFX_PMU1_MODULE_PCIE_PHY (0) ++#define IFX_PMU1_MODULE_PCIE_CTRL (1) ++#define IFX_PMU1_MODULE_PDI (4) ++#define IFX_PMU1_MODULE_MSI (5) ++ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++ ++static inline void pcie_ep_gpio_rst_init(int pcie_port) ++{ ++} ++ ++static inline void pcie_ahb_pmu_setup(void) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "ahb"); ++ clk_enable(clk); ++ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); ++} ++ ++static inline void pcie_rcu_endian_setup(int pcie_port) ++{ ++ u32 reg; ++ ++ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); ++#ifdef CONFIG_IFX_PCIE_HW_SWAP ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg |= IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#else ++ reg |= IFX_RCU_AHB_BE_PCIE_M; ++ reg &= ~IFX_RCU_AHB_BE_PCIE_S; ++ reg &= ~IFX_RCU_AHB_BE_XBAR_M; ++#endif /* CONFIG_IFX_PCIE_HW_SWAP */ ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); ++} ++ ++static inline void pcie_phy_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "phy"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1<PCIe and PDI endianness */ ++ reg |= IFX_RCU_AHB_BE_PCIE_PDI; ++ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); ++} ++ ++static inline void pcie_pdi_pmu_enable(int pcie_port) ++{ ++ struct clk *clk; ++ clk = clk_get_sys("ltq_pcie", "pdi"); ++ clk_enable(clk); ++ //ltq_pmu1_enable(1< 1) { ++ tbus_number -= pcibios_1st_host_bus_nr(); ++ } ++#endif /* CONFIG_PCI_LANTIQ */ ++ return tbus_number; ++} ++ ++static inline u32 ++ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) ++{ ++ struct pci_dev *pdev; ++ u32 tvalue = value; ++ ++ /* Sanity check */ ++ pdev = pci_get_slot(bus, devfn); ++ if (pdev == NULL) { ++ return tvalue; ++ } ++ ++ /* Only care about PCI bridge */ ++ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { ++ return tvalue; ++ } ++ ++ if (read) { /* Read hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); ++ } ++ #endif /* CONFIG_PCI_LANTIQ */ ++ } ++ else { /* Write hack */ ++ #ifdef CONFIG_PCI_LANTIQ ++ if (pcibios_host_nr() > 1) { ++ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); ++ } ++ #endif ++ } ++ return tvalue; ++} ++ ++#endif /* IFXMIPS_PCIE_VR9_H */ ++ +--- a/drivers/pci/pcie/aer/Kconfig ++++ b/drivers/pci/pcie/aer/Kconfig +@@ -19,6 +19,7 @@ config PCIEAER + config PCIE_ECRC + bool "PCI Express ECRC settings control" + depends on PCIEAER ++ default n + help + Used to override firmware/bios settings for PCI Express ECRC + (transaction layer end-to-end CRC checking). +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -1179,6 +1179,8 @@ void pci_walk_bus(struct pci_bus *top, i + void *userdata); + int pci_cfg_space_size(struct pci_dev *dev); + unsigned char pci_bus_max_busnr(struct pci_bus *bus); ++int pcibios_host_nr(void); ++int pcibios_1st_host_bus_nr(void); + void pci_setup_bridge(struct pci_bus *bus); + resource_size_t pcibios_window_alignment(struct pci_bus *bus, + unsigned long type); +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -1053,6 +1053,12 @@ + #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 + #define PCI_DEVICE_ID_SGI_IOC4 0x100a + ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x00 ++ + #define PCI_VENDOR_ID_WINBOND 0x10ad + #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 + #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-4.1/0002-MIPS-lantiq-dtb-image-hack.patch b/target/linux/lantiq/patches-4.1/0002-MIPS-lantiq-dtb-image-hack.patch new file mode 100644 index 0000000..a68607c --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0002-MIPS-lantiq-dtb-image-hack.patch @@ -0,0 +1,31 @@ +From 17348293f7f8103c97c8d2a6b0ef36eae06ec371 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 13 Mar 2013 09:36:16 +0100 +Subject: [PATCH 02/36] MIPS: lantiq: dtb image hack + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/Makefile | 2 -- + arch/mips/lantiq/prom.c | 4 +++- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -63,6 +63,8 @@ static void __init prom_init_cmdline(voi + } + } + ++extern struct boot_param_header __image_dtb; ++ + void __init plat_mem_setup(void) + { + ioport_resource.start = IOPORT_RESOURCE_START; +@@ -76,7 +78,7 @@ void __init plat_mem_setup(void) + * Load the builtin devicetree. This causes the chosen node to be + * parsed resulting in our memory appearing + */ +- __dt_setup_arch(__dtb_start); ++ __dt_setup_arch(&__image_dtb); + + strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); + } diff --git a/target/linux/lantiq/patches-4.1/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-4.1/0004-MIPS-lantiq-add-atm-hack.patch new file mode 100644 index 0000000..53809d0 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0004-MIPS-lantiq-add-atm-hack.patch @@ -0,0 +1,500 @@ +From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:25 +0200 +Subject: [PATCH 04/36] MIPS: lantiq: add atm hack + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ + arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ + arch/mips/lantiq/irq.c | 2 + + arch/mips/mm/cache.c | 2 + + include/uapi/linux/atm.h | 6 + + net/atm/common.c | 6 + + net/atm/proc.c | 2 +- + 7 files changed, 416 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_atm.h ++** PROJECT : UEIP ++** MODULES : ATM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global ATM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_ATM_H ++#define IFX_ATM_H ++ ++ ++ ++/*! ++ \defgroup IFX_ATM UEIP Project - ATM driver module ++ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_IOCTL IOCTL Commands ++ \ingroup IFX_ATM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_STRUCT Structures ++ \ingroup IFX_ATM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_atm.h ++ \ingroup IFX_ATM ++ \brief ATM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ATM MIB ++ */ ++ ++/*! ++ \struct atm_cell_ifEntry_t ++ \brief Structure used for Cell Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifInErrors; /*!< counter of error ingress cells */ ++ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ ++ __u32 ifOutErrors; /*!< counter of error egress cells */ ++} atm_cell_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_ifEntry_t ++ \brief Structure used for AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifInUcastPkts; /*!< counter of ingress packets */ ++ __u32 ifOutUcastPkts; /*!< counter of egress packets */ ++ __u32 ifInErrors; /*!< counter of error ingress packets */ ++ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ ++ __u32 ifOutErros; /*!< counter of error egress packets */ ++ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ ++} atm_aal5_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_vcc_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ This structure is a part of structure "atm_aal5_vcc_x_t". ++ */ ++typedef struct { ++ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ ++ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet ++ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ ++} atm_aal5_vcc_t; ++ ++/*! ++ \struct atm_aal5_vcc_x_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". ++ */ ++typedef struct { ++ int vpi; /*!< VPI of the VCC to get MIB counters */ ++ int vci; /*!< VCI of the VCC to get MIB counters */ ++ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ ++} atm_aal5_vcc_x_t; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief ATM IOCTL Magic Number ++ */ ++#define PPE_ATM_IOC_MAGIC 'o' ++/*! ++ \brief ATM IOCTL Command - Get Cell Level MIB Counters ++ ++ This command is obsolete. User can get cell level MIB from DSL API. ++ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters ++ ++ Get AAL5 packet counters. ++ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get Per PVC MIB Counters ++ ++ Get AAL5 packet counters for each PVC. ++ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. ++ */ ++#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) ++/*! ++ \brief Total Number of ATM IOCTL Commands ++ */ ++#define PPE_ATM_IOC_MAXNR 3 ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_ATM_H ++ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h +@@ -0,0 +1,203 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ptm.h ++** PROJECT : UEIP ++** MODULES : PTM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global PTM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_PTM_H ++#define IFX_PTM_H ++ ++ ++ ++/*! ++ \defgroup IFX_PTM UEIP Project - PTM driver module ++ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_IOCTL IOCTL Commands ++ \ingroup IFX_PTM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_STRUCT Structures ++ \ingroup IFX_PTM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_ptm.h ++ \ingroup IFX_PTM ++ \brief PTM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_PTM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief PTM IOCTL Command - Get codeword MIB counters. ++ ++ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. ++ */ ++#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 ++/*! ++ \brief PTM IOCTL Command - Get packet MIB counters. ++ ++ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. ++ */ ++#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 ++/*! ++ \brief PTM IOCTL Command - Get firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 ++/*! ++ \brief PTM IOCTL Command - Set firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 ++/*! ++ \brief PTM IOCTL Command - Program priority value to TX queue mapping. ++ ++ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. ++ */ ++#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_PTM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Data Type ++ */ ++ ++/*! ++ \typedef PTM_CW_IF_ENTRY_T ++ \brief Wrapping of structure "ptm_cw_ifEntry_t". ++ */ ++/*! ++ \struct ptm_cw_ifEntry_t ++ \brief Structure used for CodeWord level MIB counters. ++ */ ++typedef struct ptm_cw_ifEntry_t { ++ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ ++ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ ++ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ ++ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ ++ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ ++} PTM_CW_IF_ENTRY_T; ++ ++/*! ++ \typedef PTM_FRAME_MIB_T ++ \brief Wrapping of structure "ptm_frame_mib_t". ++ */ ++/*! ++ \struct ptm_frame_mib_t ++ \brief Structure used for packet level MIB counters. ++ */ ++typedef struct ptm_frame_mib_t { ++ uint32_t RxCorrect; /*!< output, number of ingress packet */ ++ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ ++ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ ++ uint32_t TxSend; /*!< output, number of egress packet */ ++} PTM_FRAME_MIB_T; ++ ++/*! ++ \typedef IFX_PTM_CFG_T ++ \brief Wrapping of structure "ptm_cfg_t". ++ */ ++/*! ++ \struct ptm_cfg_t ++ \brief Structure used for ETH/TC CRC configuration. ++ */ ++typedef struct ptm_cfg_t { ++ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ ++ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ ++ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ ++ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ ++ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ ++ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ ++ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ ++} IFX_PTM_CFG_T; ++ ++/*! ++ \typedef IFX_PTM_PRIO_Q_MAP_T ++ \brief Wrapping of structure "ppe_prio_q_map". ++ */ ++/*! ++ \struct ppe_prio_q_map ++ \brief Structure used for Priority Value to TX Queue mapping. ++ */ ++typedef struct ppe_prio_q_map { ++ int pkt_prio; ++ int qid; ++ int vpi; // ignored in eth interface ++ int vci; // ignored in eth interface ++} IFX_PTM_PRIO_Q_MAP_T; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_PTM_H ++ +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -100,6 +101,7 @@ void ltq_mask_and_ack_irq(struct irq_dat + ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); + ltq_icu_w32(im, BIT(offset), isr); + } ++EXPORT_SYMBOL(ltq_mask_and_ack_irq); + + static void ltq_ack_irq(struct irq_data *d) + { +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -59,6 +59,8 @@ void (*_dma_cache_wback)(unsigned long s + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + + EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_wback); ++EXPORT_SYMBOL(_dma_cache_inv); + + #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ + +--- a/include/uapi/linux/atm.h ++++ b/include/uapi/linux/atm.h +@@ -130,8 +130,14 @@ + #define ATM_ABR 4 + #define ATM_ANYCLASS 5 /* compatible with everything */ + ++#define ATM_VBR_NRT ATM_VBR ++#define ATM_VBR_RT 6 ++#define ATM_UBR_PLUS 7 ++#define ATM_GFR 8 ++ + #define ATM_MAX_PCR -1 /* maximum available PCR */ + ++ + struct atm_trafprm { + unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ + int max_pcr; /* maximum PCR in cells per second */ +--- a/net/atm/common.c ++++ b/net/atm/common.c +@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc + write_unlock_irq(&vcc_sklist_lock); + } + ++struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; ++EXPORT_SYMBOL(ifx_atm_alloc_tx); ++ + static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size) + { + struct sk_buff *skb; + struct sock *sk = sk_atm(vcc); + ++ if (ifx_atm_alloc_tx != NULL) ++ return ifx_atm_alloc_tx(vcc, size); ++ + if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) { + pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", + sk_wmem_alloc_get(sk), size, sk->sk_sndbuf); +--- a/net/atm/proc.c ++++ b/net/atm/proc.c +@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil + static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) + { + static const char *const class_name[] = { +- "off", "UBR", "CBR", "VBR", "ABR"}; ++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; + static const char *const aal_name[] = { + "---", "1", "2", "3/4", /* 0- 3 */ + "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-4.1/0007-MIPS-lantiq-add-basic-tffs-driver.patch b/target/linux/lantiq/patches-4.1/0007-MIPS-lantiq-add-basic-tffs-driver.patch new file mode 100644 index 0000000..7081373 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0007-MIPS-lantiq-add-basic-tffs-driver.patch @@ -0,0 +1,111 @@ +From d27ec8bb97db0f60d81ab255d51ac4e967362067 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:34:19 +0200 +Subject: [PATCH 07/36] MIPS: lantiq: add basic tffs driver + +Signed-off-by: John Crispin +--- + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/tffs.c | 87 ++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 88 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/lantiq/xway/tffs.c + +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,5 +1,5 @@ + obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o + +-obj-y += vmmc.o ++obj-y += vmmc.o tffs.o + + obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/tffs.c +@@ -0,0 +1,87 @@ ++#include ++#include ++#include ++#include ++ ++struct tffs_entry { ++ uint16_t id; ++ uint16_t len; ++}; ++ ++static struct tffs_id { ++ uint32_t id; ++ char *name; ++ unsigned char *val; ++ uint32_t offset; ++ uint32_t len; ++} ids[] = { ++ { 0x01A9, "annex" }, ++ { 0x0188, "maca" }, ++ { 0x0189, "macb" }, ++ { 0x018a, "macwlan" }, ++ { 0x0195, "macwlan2" }, ++ { 0x018b, "macdsl" }, ++ { 0x01C2, "webgui_pass" }, ++ { 0x01AB, "wlan_key" }, ++}; ++ ++static struct mtd_info *tffs1, *tffs2; ++ ++static struct tffs_id* tffs_find_id(int id) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(ids); i++) ++ if (id == ids[i].id) ++ return &ids[i]; ++ ++ return NULL; ++} ++ ++static void tffs_index(void) ++{ ++ struct tffs_entry *E = NULL; ++ struct tffs_entry entry; ++ int ret, retlen; ++ ++ while ((unsigned int) E + sizeof(struct tffs_entry) < tffs2->size) { ++ struct tffs_id *id; ++ int len; ++ ++ ret = mtd_read(tffs2, (unsigned int) E, sizeof(struct tffs_entry), &retlen, (unsigned char *)&entry); ++ if (ret) ++ return; ++ ++ if (entry.id == 0xffff) ++ return; ++ ++ id = tffs_find_id(entry.id); ++ if (id) { ++ id->offset = (uint32_t) E; ++ id->len = entry.len; ++ id->val = kzalloc(entry.len + 1, GFP_KERNEL); ++ mtd_read(tffs2, ((unsigned int) E) + sizeof(struct tffs_entry), entry.len, &retlen, id->val); ++ ++ } ++ //printk(KERN_INFO "found entry at 0x%08X-> [<0x%x> %u bytes]\n", (uint32_t) E, entry.id, entry.len); ++ if (id && id->name) ++ printk(KERN_INFO "found entry name -> %s=%s\n", id->name, id->val); ++ ++ len = (entry.len + 3) & ~0x03; ++ E = (struct tffs_entry *)(((unsigned int)E) + sizeof(struct tffs_entry) + len); ++ } ++} ++ ++static int __init tffs_init(void) ++{ ++ tffs1 = get_mtd_device_nm("tffs (1)"); ++ tffs2 = get_mtd_device_nm("tffs (2)"); ++ if (IS_ERR(tffs1) || IS_ERR(tffs2)) ++ return -1; ++ ++ tffs_index(); ++ ++ return 0; ++} ++late_initcall(tffs_init); ++ diff --git a/target/linux/lantiq/patches-4.1/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-4.1/0008-MIPS-lantiq-backport-old-timer-code.patch new file mode 100644 index 0000000..5525503 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0008-MIPS-lantiq-backport-old-timer-code.patch @@ -0,0 +1,1028 @@ +From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:30:56 +0200 +Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ + 3 files changed, 1001 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h + create mode 100644 arch/mips/lantiq/xway/timer.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h +@@ -0,0 +1,155 @@ ++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++ ++ ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * Available Timer/Counter Index ++ */ ++#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) ++#define TIMER_ANY 0x00 ++#define TIMER1A TIMER(1, 0) ++#define TIMER1B TIMER(1, 1) ++#define TIMER2A TIMER(2, 0) ++#define TIMER2B TIMER(2, 1) ++#define TIMER3A TIMER(3, 0) ++#define TIMER3B TIMER(3, 1) ++ ++/* ++ * Flag of Timer/Counter ++ * These flags specify the way in which timer is configured. ++ */ ++/* Bit size of timer/counter. */ ++#define TIMER_FLAG_16BIT 0x0000 ++#define TIMER_FLAG_32BIT 0x0001 ++/* Switch between timer and counter. */ ++#define TIMER_FLAG_TIMER 0x0000 ++#define TIMER_FLAG_COUNTER 0x0002 ++/* Stop or continue when overflowing/underflowing. */ ++#define TIMER_FLAG_ONCE 0x0000 ++#define TIMER_FLAG_CYCLIC 0x0004 ++/* Count up or counter down. */ ++#define TIMER_FLAG_UP 0x0000 ++#define TIMER_FLAG_DOWN 0x0008 ++/* Count on specific level or edge. */ ++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 ++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 ++#define TIMER_FLAG_RISE_EDGE 0x0010 ++#define TIMER_FLAG_FALL_EDGE 0x0020 ++#define TIMER_FLAG_ANY_EDGE 0x0030 ++/* Signal is syncronous to module clock or not. */ ++#define TIMER_FLAG_UNSYNC 0x0000 ++#define TIMER_FLAG_SYNC 0x0080 ++/* Different interrupt handle type. */ ++#define TIMER_FLAG_NO_HANDLE 0x0000 ++#if defined(__KERNEL__) ++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 ++#endif // defined(__KERNEL__) ++#define TIMER_FLAG_SIGNAL 0x0300 ++/* Internal clock source or external clock source */ ++#define TIMER_FLAG_INT_SRC 0x0000 ++#define TIMER_FLAG_EXT_SRC 0x1000 ++ ++ ++/* ++ * ioctl Command ++ */ ++#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ ++#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ ++#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ ++#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ ++#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ ++#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ ++#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ ++#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ ++ ++/* ++ * Data Type Used to Call ioctl ++ */ ++struct gptu_ioctl_param { ++ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field is ID of expected * ++ * timer/counter. If it's zero, a timer/counter would * ++ * be dynamically allocated and ID would be stored in * ++ * this field. * ++ * In command GPTU_GET_COUNT_VALUE, this field is * ++ * ignored. * ++ * In other command, this field is ID of timer/counter * ++ * allocated. */ ++ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field contains flags to * ++ * specify how to configure timer/counter. * ++ * In command GPTU_START_TIMER, zero indicate start * ++ * and non-zero indicate resume timer/counter. * ++ * In other command, this field is ignored. */ ++ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * ++ * init/reload value. * ++ * In command GPTU_SET_TIMER, this field contains * ++ * frequency (0.001Hz) of timer. * ++ * In command GPTU_GET_COUNT_VALUE, current count * ++ * value would be stored in this field. * ++ * In command GPTU_CALCULATE_DIVIDER, this field * ++ * contains frequency wanted, and after calculation, * ++ * divider would be stored in this field to overwrite * ++ * the frequency. * ++ * In other command, this field is ignored. */ ++ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains process * ++ * ID to which signal would be sent. * ++ * In other command, this field is ignored. */ ++ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains signal * ++ * number which would be sent. * ++ * In other command, this field is ignored. */ ++}; ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++typedef void (*timer_callback)(unsigned long arg); ++ ++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); ++extern int lq_free_timer(unsigned int); ++extern int lq_start_timer(unsigned int, int); ++extern int lq_stop_timer(unsigned int); ++extern int lq_reset_counter_flags(u32 timer, u32 flags); ++extern int lq_get_count_value(unsigned int, unsigned long *); ++extern u32 lq_cal_divider(unsigned long); ++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); ++extern int lq_set_counter(unsigned int timer, unsigned int flag, ++ u32 reload, unsigned long arg1, unsigned long arg2); ++ ++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,4 @@ +-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o ++obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o + + obj-y += vmmc.o tffs.o + +--- /dev/null ++++ b/arch/mips/lantiq/xway/timer.c +@@ -0,0 +1,845 @@ ++#ifndef CONFIG_SOC_AMAZON_SE ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "../clk.h" ++ ++#include ++#include ++#include ++ ++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 ++ ++#ifdef TIMER1A ++#define FIRST_TIMER TIMER1A ++#else ++#define FIRST_TIMER 2 ++#endif ++ ++/* ++ * GPTC divider is set or not. ++ */ ++#define GPTU_CLC_RMC_IS_SET 0 ++ ++/* ++ * Timer Interrupt (IRQ) ++ */ ++/* Must be adjusted when ICU driver is available */ ++#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) ++ ++/* ++ * Bits Operation ++ */ ++#define GET_BITS(x, msb, lsb) \ ++ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) ++#define SET_BITS(x, msb, lsb, value) \ ++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ ++ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++ ++/* ++ * GPTU Register Mapping ++ */ ++#define LQ_GPTU (KSEG1 + 0x1E100A00) ++#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) ++#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) ++#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) ++#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) ++#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) ++ ++/* ++ * Clock Control Register ++ */ ++#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) ++#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) ++#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) ++#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) ++#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) ++#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) ++#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) ++ ++#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) ++#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) ++#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) ++ ++/* ++ * ID Register ++ */ ++#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) ++#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) ++#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) ++ ++/* ++ * Control Register of Timer/Counter nX ++ * n is the index of block (1 based index) ++ * X is either A or B ++ */ ++#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) ++#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) ++#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) ++#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) ++#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) ++#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ ++#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) ++#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) ++#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) ++#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) ++ ++#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) ++#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) ++#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) ++#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) ++#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) ++ ++#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) ++#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) ++ ++#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++ ++#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) ++#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) ++#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) ++#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) ++#define TIMER_FLAG_NONE_EDGE 0x0000 ++#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) ++#define TIMER_FLAG_REAL 0x0000 ++#define TIMER_FLAG_INVERT 0x0040 ++#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) ++#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) ++#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) ++#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 ++#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) ++#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) ++ ++struct timer_dev_timer { ++ unsigned int f_irq_on; ++ unsigned int irq; ++ unsigned int flag; ++ unsigned long arg1; ++ unsigned long arg2; ++}; ++ ++struct timer_dev { ++ struct mutex gptu_mutex; ++ unsigned int number_of_timers; ++ unsigned int occupation; ++ unsigned int f_gptu_on; ++ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; ++}; ++ ++ ++unsigned int ltq_get_fpi_bus_clock(int fpi) { ++ struct clk *clk = clk_get_fpi(); ++ return clk_get_rate(clk); ++} ++ ++ ++static long gptu_ioctl(struct file *, unsigned int, unsigned long); ++static int gptu_open(struct inode *, struct file *); ++static int gptu_release(struct inode *, struct file *); ++ ++static struct file_operations gptu_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gptu_ioctl, ++ .open = gptu_open, ++ .release = gptu_release ++}; ++ ++static struct miscdevice gptu_miscdev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "gptu", ++ .fops = &gptu_fops, ++}; ++ ++static struct timer_dev timer_dev; ++ ++static irqreturn_t timer_irq_handler(int irq, void *p) ++{ ++ unsigned int timer; ++ unsigned int flag; ++ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; ++ ++ timer = irq - TIMER_INTERRUPT; ++ if (timer < timer_dev.number_of_timers ++ && dev_timer == &timer_dev.timer[timer]) { ++ /* Clear interrupt. */ ++ ltq_w32(1 << timer, LQ_GPTU_IRNCR); ++ ++ /* Call user hanler or signal. */ ++ flag = dev_timer->flag; ++ if (!(timer & 0x01) ++ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ /* 16-bit timer or timer A of 32-bit timer */ ++ switch (TIMER_FLAG_MASK_HANDLE(flag)) { ++ case TIMER_FLAG_CALLBACK_IN_IRQ: ++ case TIMER_FLAG_CALLBACK_IN_HB: ++ if (dev_timer->arg1) ++ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); ++ break; ++ case TIMER_FLAG_SIGNAL: ++ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); ++ break; ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static inline void lq_enable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ clk_enable(clk); ++ ++ //ltq_pmu_enable(PMU_GPT); ++ ++ /* Set divider as 1, disable write protection for SPEN, enable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x01) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(1) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(0); ++} ++ ++static inline void lq_disable_gptu(void) ++{ ++ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); ++ ltq_w32(0x00, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ /* Set divider as 0, enable write protection for SPEN, disable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x00) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(0) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(1); ++ ++ clk_enable(clk); ++} ++ ++int lq_request_timer(unsigned int timer, unsigned int flag, ++ unsigned long value, unsigned long arg1, unsigned long arg2) ++{ ++ int ret = 0; ++ unsigned int con_reg, irnen_reg; ++ int n, X; ++ ++ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", ++ timer, flag, value); ++ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) ++ value &= 0xFFFF; ++ else ++ timer &= ~0x01; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ /* ++ * Allocate timer. ++ */ ++ if (timer < FIRST_TIMER) { ++ unsigned int mask; ++ unsigned int shift; ++ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ ++ unsigned int offset = TIMER2A; ++ ++ /* ++ * Pick up a free timer. ++ */ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ mask = 1 << offset; ++ shift = 1; ++ } else { ++ mask = 3 << offset; ++ shift = 2; ++ } ++ for (timer = offset; ++ timer < offset + timer_dev.number_of_timers; ++ timer += shift, mask <<= shift) ++ if (!(timer_dev.occupation & mask)) { ++ timer_dev.occupation |= mask; ++ break; ++ } ++ if (timer >= offset + timer_dev.number_of_timers) { ++ printk("failed![%d]\n", __LINE__); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } else ++ ret = timer; ++ } else { ++ register unsigned int mask; ++ ++ /* ++ * Check if the requested timer is free. ++ */ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if ((timer_dev.occupation & mask)) { ++ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", ++ __LINE__, mask, timer_dev.occupation); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EBUSY; ++ } else { ++ timer_dev.occupation |= mask; ++ ret = 0; ++ } ++ } ++ ++ /* ++ * Prepare control register value. ++ */ ++ switch (TIMER_FLAG_MASK_EDGE(flag)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : ++ GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : ++ GPTU_CON_SRC_EG_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_SYNC(flag) == ++ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : ++ GPTU_CON_SYNC_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_INVERT(flag) == ++ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : ++ GPTU_CON_EXT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_STOP(flag) == ++ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_TYPE(flag) == ++ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : ++ GPTU_CON_CNT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_DIR(flag) == ++ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ /* ++ * Fill up running data. ++ */ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flag; ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; ++ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; ++ ++ /* ++ * Enable GPTU module. ++ */ ++ if (!timer_dev.f_gptu_on) { ++ lq_enable_gptu(); ++ timer_dev.f_gptu_on = 1; ++ } ++ ++ /* ++ * Enable IRQ. ++ */ ++ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = ++ (unsigned long) find_task_by_vpid((int) arg1); ++ ++ irnen_reg = 1 << (timer - FIRST_TIMER); ++ ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL ++ || (TIMER_FLAG_MASK_HANDLE(flag) == ++ TIMER_FLAG_CALLBACK_IN_IRQ ++ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { ++ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; ++ } ++ } else ++ irnen_reg = 0; ++ ++ /* ++ * Write config register, reload value and enable interrupt. ++ */ ++ n = timer >> 1; ++ X = timer & 0x01; ++ *LQ_GPTU_CON(n, X) = con_reg; ++ *LQ_GPTU_RELOAD(n, X) = value; ++ /* printk("reload value = %d\n", (u32)value); */ ++ *LQ_GPTU_IRNEN |= irnen_reg; ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ printk("successful!\n"); ++ return ret; ++} ++EXPORT_SYMBOL(lq_request_timer); ++ ++int lq_free_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ if (GPTU_CON_EN(n, X)) ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); ++ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); ++ ++ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { ++ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; ++ } ++ ++ timer_dev.occupation &= ~mask; ++ if (!timer_dev.occupation && timer_dev.f_gptu_on) { ++ lq_disable_gptu(); ++ timer_dev.f_gptu_on = 0; ++ } ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_free_timer); ++ ++int lq_start_timer(unsigned int timer, int is_resume) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_start_timer); ++ ++int lq_stop_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_stop_timer); ++ ++int lq_reset_counter_flags(u32 timer, u32 flags) ++{ ++ unsigned int oflag; ++ unsigned int mask, con_reg; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ switch (TIMER_FLAG_MASK_EDGE(flags)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); ++ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); ++ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flags; ++ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_CON(n, X) = con_reg; ++ smp_wmb(); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return 0; ++} ++EXPORT_SYMBOL(lq_reset_counter_flags); ++ ++int lq_get_count_value(unsigned int timer, unsigned long *value) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *value = *LQ_GPTU_COUNT(n, X); ++ ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_get_count_value); ++ ++u32 lq_cal_divider(unsigned long freq) ++{ ++ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); ++ u32 clock_divider = 1; ++ module_freq = fpi * 1000; ++ do_div(module_freq, clock_divider * freq); ++ return module_freq; ++} ++EXPORT_SYMBOL(lq_cal_divider); ++ ++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, ++ int is_ext_src, unsigned int handle_flag, unsigned long arg1, ++ unsigned long arg2) ++{ ++ unsigned long divider; ++ unsigned int flag; ++ ++ divider = lq_cal_divider(freq); ++ if (divider == 0) ++ return -EINVAL; ++ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) ++ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) ++ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) ++ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN ++ | TIMER_FLAG_MASK_HANDLE(handle_flag); ++ ++ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", ++ timer, freq, divider); ++ return lq_request_timer(timer, flag, divider, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_timer); ++ ++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, ++ unsigned long arg1, unsigned long arg2) ++{ ++ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); ++ return lq_request_timer(timer, flag, reload, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_counter); ++ ++static long gptu_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret; ++ struct gptu_ioctl_param param; ++ ++ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ copy_from_user(¶m, (void *) arg, sizeof(param)); ++ ++ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER ++ || GPTU_SET_COUNTER) && param.timer < 2) ++ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) ++ && !access_ok(VERIFY_WRITE, arg, ++ sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case GPTU_REQUEST_TIMER: ++ ret = lq_request_timer(param.timer, param.flag, param.value, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_FREE_TIMER: ++ ret = lq_free_timer(param.timer); ++ break; ++ case GPTU_START_TIMER: ++ ret = lq_start_timer(param.timer, param.flag); ++ break; ++ case GPTU_STOP_TIMER: ++ ret = lq_stop_timer(param.timer); ++ break; ++ case GPTU_GET_COUNT_VALUE: ++ ret = lq_get_count_value(param.timer, ¶m.value); ++ if (!ret) ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ break; ++ case GPTU_CALCULATE_DIVIDER: ++ param.value = lq_cal_divider(param.value); ++ if (param.value == 0) ++ ret = -EINVAL; ++ else { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_TIMER: ++ ret = lq_set_timer(param.timer, param.value, ++ TIMER_FLAG_MASK_STOP(param.flag) != ++ TIMER_FLAG_ONCE ? 1 : 0, ++ TIMER_FLAG_MASK_SRC(param.flag) == ++ TIMER_FLAG_EXT_SRC ? 1 : 0, ++ TIMER_FLAG_MASK_HANDLE(param.flag) == ++ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : ++ TIMER_FLAG_NO_HANDLE, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_COUNTER: ++ lq_set_counter(param.timer, param.flag, param.value, 0, 0); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ default: ++ ret = -ENOTTY; ++ } ++ ++ return ret; ++} ++ ++static int gptu_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int gptu_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++int __init lq_gptu_init(void) ++{ ++ int ret; ++ unsigned int i; ++ ++ ltq_w32(0, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ memset(&timer_dev, 0, sizeof(timer_dev)); ++ mutex_init(&timer_dev.gptu_mutex); ++ ++ lq_enable_gptu(); ++ timer_dev.number_of_timers = GPTU_ID_CFG * 2; ++ lq_disable_gptu(); ++ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) ++ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; ++ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); ++ ++ ret = misc_register(&gptu_miscdev); ++ if (ret) { ++ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); ++ return ret; ++ } else { ++ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); ++ } ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); ++ if (ret) { ++ for (; i >= 0; i--) ++ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); ++ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); ++ return ret; ++ } else { ++ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; ++ disable_irq(timer_dev.timer[i].irq); ++ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); ++ } ++ } ++ ++ return 0; ++} ++ ++void __exit lq_gptu_exit(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ if (timer_dev.timer[i].f_irq_on) ++ disable_irq(timer_dev.timer[i].irq); ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ } ++ lq_disable_gptu(); ++ misc_deregister(&gptu_miscdev); ++} ++ ++module_init(lq_gptu_init); ++module_exit(lq_gptu_exit); ++ ++#endif diff --git a/target/linux/lantiq/patches-4.1/0012-pinctrl-lantiq-fix-up-pinmux.patch b/target/linux/lantiq/patches-4.1/0012-pinctrl-lantiq-fix-up-pinmux.patch new file mode 100644 index 0000000..ecd143f --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0012-pinctrl-lantiq-fix-up-pinmux.patch @@ -0,0 +1,79 @@ +From 25494c55a4007a1409f53ddbafd661636e47ea34 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 9 Aug 2013 20:38:15 +0200 +Subject: [PATCH 12/36] pinctrl/lantiq: fix up pinmux + +We found out how to set the gphy led pinmuxing. + +Signed-off-by: John Crispin +--- + drivers/pinctrl/pinctrl-xway.c | 28 ++++++++++++++++++++++++++-- + 1 file changed, 26 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/pinctrl-xway.c ++++ b/drivers/pinctrl/pinctrl-xway.c +@@ -609,10 +609,9 @@ static struct pinctrl_desc xway_pctrl_de + .confops = &xway_pinconf_ops, + }; + +-static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, ++static int mux_apply(struct ltq_pinmux_info *info, + int pin, int mux) + { +- struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); + int port = PORT(pin); + u32 alt1_reg = GPIO_ALT1(pin); + +@@ -632,6 +631,14 @@ static inline int xway_mux_apply(struct + return 0; + } + ++static inline int xway_mux_apply(struct pinctrl_dev *pctrldev, ++ int pin, int mux) ++{ ++ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); ++ ++ return mux_apply(info, pin, mux); ++} ++ + static const struct ltq_cfg_param xway_cfg_params[] = { + {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, + {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN}, +@@ -676,6 +683,10 @@ static int xway_gpio_dir_out(struct gpio + { + struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); + ++ if (PORT(pin) == PORT3) ++ gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin)); ++ else ++ gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin)); + gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin)); + xway_gpio_set(chip, pin, val); + +@@ -696,6 +707,18 @@ static void xway_gpio_free(struct gpio_c + pinctrl_free_gpio(gpio); + } + ++static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset) ++{ ++ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev); ++ int i; ++ ++ for (i = 0; i < info->num_exin; i++) ++ if (info->exin[i] == offset) ++ return ltq_eiu_get_irq(i); ++ ++ return -1; ++} ++ + static struct gpio_chip xway_chip = { + .label = "gpio-xway", + .direction_input = xway_gpio_dir_in, +@@ -704,6 +727,7 @@ static struct gpio_chip xway_chip = { + .set = xway_gpio_set, + .request = xway_gpio_req, + .free = xway_gpio_free, ++ .to_irq = xway_gpio_to_irq, + .base = -1, + }; + diff --git a/target/linux/lantiq/patches-4.1/0013-MTD-lantiq-xway-fix-invalid-operator.patch b/target/linux/lantiq/patches-4.1/0013-MTD-lantiq-xway-fix-invalid-operator.patch new file mode 100644 index 0000000..c6d3819 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0013-MTD-lantiq-xway-fix-invalid-operator.patch @@ -0,0 +1,24 @@ +From 8e34da603f442624bb70e887d8f42064bb924224 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jul 2013 18:03:54 +0200 +Subject: [PATCH 13/36] MTD: lantiq: xway: fix invalid operator + +xway_read_byte should use a logic or and not an add operator when working out +the nand address. + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -124,7 +124,7 @@ static unsigned char xway_read_byte(stru + int ret; + + spin_lock_irqsave(&ebu_lock, flags); +- ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA)); ++ ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA)); + spin_unlock_irqrestore(&ebu_lock, flags); + + return ret; diff --git a/target/linux/lantiq/patches-4.1/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch b/target/linux/lantiq/patches-4.1/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch new file mode 100644 index 0000000..6a7785b --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch @@ -0,0 +1,44 @@ +From b454cefd675fc1bd3d8c690c1bd1d8f4678e9922 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jul 2013 18:06:39 +0200 +Subject: [PATCH 14/36] MTD: lantiq: xway: the latched command should be + persistent + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -54,6 +54,8 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++static u32 xway_latchcmd; ++ + static void xway_reset_chip(struct nand_chip *chip) + { + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; +@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_inf + unsigned long flags; + + if (ctrl & NAND_CTRL_CHANGE) { +- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR); + if (ctrl & NAND_CLE) +- nandaddr |= NAND_WRITE_CMD; +- else +- nandaddr |= NAND_WRITE_ADDR; +- this->IO_ADDR_W = (void __iomem *) nandaddr; ++ xway_latchcmd = NAND_WRITE_CMD; ++ else if (ctrl & NAND_ALE) ++ xway_latchcmd = NAND_WRITE_ADDR; + } + + if (cmd != NAND_CMD_NONE) { + spin_lock_irqsave(&ebu_lock, flags); +- writeb(cmd, this->IO_ADDR_W); ++ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd)); + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + spin_unlock_irqrestore(&ebu_lock, flags); diff --git a/target/linux/lantiq/patches-4.1/0015-MTD-lantiq-xway-remove-endless-loop.patch b/target/linux/lantiq/patches-4.1/0015-MTD-lantiq-xway-remove-endless-loop.patch new file mode 100644 index 0000000..4bd1668 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0015-MTD-lantiq-xway-remove-endless-loop.patch @@ -0,0 +1,41 @@ +From 76e153079f02d26e3357302d2886a0c8aaaec64d Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jul 2013 18:02:06 +0200 +Subject: [PATCH 15/36] MTD: lantiq: xway: remove endless loop + +The reset loop logic could run into a endless loop. Lets fix it as requested. + +--> http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -59,16 +59,22 @@ static u32 xway_latchcmd; + static void xway_reset_chip(struct nand_chip *chip) + { + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; ++ unsigned long timeout; + unsigned long flags; + + nandaddr &= ~NAND_WRITE_ADDR; + nandaddr |= NAND_WRITE_CMD; + + /* finish with a reset */ ++ timeout = jiffies + msecs_to_jiffies(20); ++ + spin_lock_irqsave(&ebu_lock, flags); + writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr); +- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) +- ; ++ do { ++ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) ++ break; ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); + spin_unlock_irqrestore(&ebu_lock, flags); + } + diff --git a/target/linux/lantiq/patches-4.1/0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch b/target/linux/lantiq/patches-4.1/0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch new file mode 100644 index 0000000..f20878c --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0016-MTD-lantiq-xway-add-missing-write_buf-and-read_buf-t.patch @@ -0,0 +1,55 @@ +From 65df9d63eaee02c25e879b33dd42aceb78e57842 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jul 2013 17:59:51 +0200 +Subject: [PATCH 16/36] MTD: lantiq: xway: add missing write_buf and read_buf + to nand driver + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -136,6 +136,32 @@ static unsigned char xway_read_byte(stru + return ret; + } + ++static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len) ++{ ++ struct nand_chip *this = mtd->priv; ++ unsigned long nandaddr = (unsigned long) this->IO_ADDR_R; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&ebu_lock, flags); ++ for (i = 0; i < len; i++) ++ buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA)); ++ spin_unlock_irqrestore(&ebu_lock, flags); ++} ++ ++static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ struct nand_chip *this = mtd->priv; ++ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&ebu_lock, flags); ++ for (i = 0; i < len; i++) ++ ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA)); ++ spin_unlock_irqrestore(&ebu_lock, flags); ++} ++ + static int xway_nand_probe(struct platform_device *pdev) + { + struct nand_chip *this = platform_get_drvdata(pdev); +@@ -181,6 +207,8 @@ static struct platform_nand_data xway_na + .dev_ready = xway_dev_ready, + .select_chip = xway_select_chip, + .read_byte = xway_read_byte, ++ .read_buf = xway_read_buf, ++ .write_buf = xway_write_buf, + } + }; + diff --git a/target/linux/lantiq/patches-4.1/0017-MTD-xway-fix-nand-locking.patch b/target/linux/lantiq/patches-4.1/0017-MTD-xway-fix-nand-locking.patch new file mode 100644 index 0000000..737469a --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0017-MTD-xway-fix-nand-locking.patch @@ -0,0 +1,89 @@ +From aa705c1b0860da91f2ed1a4c0b57337e6de689e1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:55:31 +0200 +Subject: [PATCH 17/36] MTD: xway: fix nand locking + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 15 +++------------ + 1 file changed, 3 insertions(+), 12 deletions(-) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -80,13 +80,16 @@ static void xway_reset_chip(struct nand_ + + static void xway_select_chip(struct mtd_info *mtd, int chip) + { ++ static unsigned long csflags; + + switch (chip) { + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); ++ spin_unlock_irqrestore(&ebu_lock, csflags); + break; + case 0: ++ spin_lock_irqsave(&ebu_lock, csflags); + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); + break; +@@ -99,7 +102,6 @@ static void xway_cmd_ctrl(struct mtd_inf + { + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; +- unsigned long flags; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_CLE) +@@ -109,11 +111,9 @@ static void xway_cmd_ctrl(struct mtd_inf + } + + if (cmd != NAND_CMD_NONE) { +- spin_lock_irqsave(&ebu_lock, flags); + writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd)); + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; +- spin_unlock_irqrestore(&ebu_lock, flags); + } + } + +@@ -126,12 +126,9 @@ static unsigned char xway_read_byte(stru + { + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_R; +- unsigned long flags; + int ret; + +- spin_lock_irqsave(&ebu_lock, flags); + ret = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA)); +- spin_unlock_irqrestore(&ebu_lock, flags); + + return ret; + } +@@ -140,26 +137,20 @@ static void xway_read_buf(struct mtd_inf + { + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_R; +- unsigned long flags; + int i; + +- spin_lock_irqsave(&ebu_lock, flags); + for (i = 0; i < len; i++) + buf[i] = ltq_r8((void __iomem *)(nandaddr | NAND_READ_DATA)); +- spin_unlock_irqrestore(&ebu_lock, flags); + } + + static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len) + { + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; +- unsigned long flags; + int i; + +- spin_lock_irqsave(&ebu_lock, flags); + for (i = 0; i < len; i++) + ltq_w8(buf[i], (void __iomem *)(nandaddr | NAND_WRITE_DATA)); +- spin_unlock_irqrestore(&ebu_lock, flags); + } + + static int xway_nand_probe(struct platform_device *pdev) diff --git a/target/linux/lantiq/patches-4.1/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-4.1/0018-MTD-nand-lots-of-xrx200-fixes.patch new file mode 100644 index 0000000..5500861 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0018-MTD-nand-lots-of-xrx200-fixes.patch @@ -0,0 +1,125 @@ +From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 23:12:15 +0200 +Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes + +Signed-off-by: John Crispin +--- + drivers/mtd/nand/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 63 insertions(+) + +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -54,8 +54,27 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) ++#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) ++#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) ++ + static u32 xway_latchcmd; + ++/* ++ * req_mask provides a mechanism to prevent interference between ++ * nand and pci (probably only relevant for the BT Home Hub 2B). ++ * Setting it causes the corresponding pci req pins to be masked ++ * during nand access, and also moves ebu locking from the read/write ++ * functions to the chip select function to ensure that the whole ++ * operation runs with interrupts disabled. ++ * In addition it switches on some extra waiting in xway_cmd_ctrl(). ++ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, ++ * which in turn seems to be necessary for the nor chip to be recognised ++ * reliably, on a board (Home Hub 2B again) which has both nor and nand. ++ */ ++ ++static __be32 req_mask = 0; ++ + static void xway_reset_chip(struct nand_chip *chip) + { + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; +@@ -86,12 +105,24 @@ static void xway_select_chip(struct mtd_ + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); ++ ++ if (req_mask) { ++ /* Unmask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); ++ } + spin_unlock_irqrestore(&ebu_lock, csflags); ++ + break; + case 0: + spin_lock_irqsave(&ebu_lock, csflags); ++ if (req_mask) { ++ /* Mask all external PCI request */ ++ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); ++ } ++ + ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); ++ + break; + default: + BUG(); +@@ -103,6 +134,12 @@ static void xway_cmd_ctrl(struct mtd_inf + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + ++ if (req_mask) { ++ if (cmd != NAND_CMD_STATUS) ++ ltq_ebu_w32(EBU_NAND_WAIT, 0); /* Clear nand ready */ ++ } ++ ++ + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_CLE) + xway_latchcmd = NAND_WRITE_CMD; +@@ -115,6 +152,24 @@ static void xway_cmd_ctrl(struct mtd_inf + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + } ++ ++ if (req_mask) { ++ /* ++ * program and erase have their own busy handlers ++ * status and sequential in needs no delay ++ */ ++ switch (cmd) { ++ case NAND_CMD_ERASE1: ++ case NAND_CMD_SEQIN: ++ case NAND_CMD_STATUS: ++ case NAND_CMD_READID: ++ return; ++ } ++ ++ /* wait until command is processed */ ++ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) ++ ; ++ } + } + + static int xway_dev_ready(struct mtd_info *mtd) +@@ -157,6 +212,8 @@ static int xway_nand_probe(struct platfo + { + struct nand_chip *this = platform_get_drvdata(pdev); + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; ++ const __be32 *req_mask_ptr = of_get_property(pdev->dev.of_node, ++ "req-mask", NULL); + const __be32 *cs = of_get_property(pdev->dev.of_node, + "lantiq,cs", NULL); + u32 cs_flag = 0; +@@ -165,6 +222,12 @@ static int xway_nand_probe(struct platfo + if (cs && (*cs == 1)) + cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; + ++ /* ++ * Load the PCI req lines to mask from the device tree. If the ++ * property is not present, setting req_mask to 0 disables masking. ++ */ ++ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); ++ + /* setup the EBU to run in NAND mode on our base addr */ + ltq_ebu_w32(CPHYSADDR(nandaddr) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-4.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-4.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch new file mode 100644 index 0000000..36a899d --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch @@ -0,0 +1,25 @@ +From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:18:00 +0200 +Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash + +Signed-off-by: John Crispin +--- + drivers/mtd/maps/lantiq-flash.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -139,7 +139,11 @@ ltq_mtd_probe(struct platform_device *pd + if (!ltq_mtd->map) + return -ENOMEM; + +- ltq_mtd->map->phys = ltq_mtd->res->start; ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map->phys = NO_XIP; ++ else ++ ltq_mtd->map->phys = ltq_mtd->res->start; ++ ltq_mtd->res->start; + ltq_mtd->map->size = resource_size(ltq_mtd->res); + ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); + if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-4.1/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch b/target/linux/lantiq/patches-4.1/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch new file mode 100644 index 0000000..1f0ffe1 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch @@ -0,0 +1,44 @@ +From 4400e1f593ea40a51912128adb4f53d59e62cad8 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:40:18 +0200 +Subject: [PATCH 22/36] MTD: m25p80: allow loading mtd name from OF + +In accordance with the physmap flash we should honour the linux,mtd-name +property when deciding what name the mtd device has. + +Signed-off-by: Thomas Langer +Signed-off-by: John Crispin +--- + drivers/mtd/devices/m25p80.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -184,6 +185,10 @@ static int m25p_probe(struct spi_device + enum read_mode mode = SPI_NOR_NORMAL; + char *flash_name = NULL; + int ret; ++ const char __maybe_unused *of_mtd_name = NULL; ++ ++ of_property_read_string(spi->dev.of_node, ++ "linux,mtd-name", &of_mtd_name); + + data = dev_get_platdata(&spi->dev); + +@@ -215,6 +220,8 @@ static int m25p_probe(struct spi_device + + if (data && data->name) + flash->mtd.name = data->name; ++ else if (of_mtd_name) ++ flash->mtd.name = of_mtd_name; + + /* For some (historical?) reason many platforms provide two different + * names in flash_platform_data: "name" and "type". Quite often name is diff --git a/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch b/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch new file mode 100644 index 0000000..08e6b64 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch @@ -0,0 +1,271 @@ +From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:15:36 +0200 +Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G + +Signed-off-by: John Crispin +--- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 237 insertions(+) + create mode 100644 drivers/net/phy/lantiq.c + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -165,6 +165,11 @@ config RTL8306_PHY + tristate "Driver for Realtek RTL8306S switches" + select SWCONFIG + ++config LANTIQ_PHY ++ tristate "Driver for Lantiq PHYs" ++ ---help--- ++ Supports the 11G and 22E PHYs. ++ + config FIXED_PHY + tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o + obj-$(CONFIG_DP83640_PHY) += dp83640.o + obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_MICREL_PHY) += micrel.o ++obj-$(CONFIG_LANTIQ_PHY) += lantiq.o + obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o + obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o + obj-$(CONFIG_AT803X_PHY) += at803x.o +--- /dev/null ++++ b/drivers/net/phy/lantiq.c +@@ -0,0 +1,231 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2012 Daniel Schwierzeck ++ */ ++ ++#include ++#include ++ ++#define MII_MMDCTRL 0x0d ++#define MII_MMDDATA 0x0e ++ ++#define MII_VR9_11G_IMASK 0x19 /* interrupt mask */ ++#define MII_VR9_11G_ISTAT 0x1a /* interrupt status */ ++ ++#define INT_VR9_11G_WOL BIT(15) /* Wake-On-LAN */ ++#define INT_VR9_11G_ANE BIT(11) /* Auto-Neg error */ ++#define INT_VR9_11G_ANC BIT(10) /* Auto-Neg complete */ ++#define INT_VR9_11G_ADSC BIT(5) /* Link auto-downspeed detect */ ++#define INT_VR9_11G_DXMC BIT(2) /* Duplex mode change */ ++#define INT_VR9_11G_LSPC BIT(1) /* Link speed change */ ++#define INT_VR9_11G_LSTC BIT(0) /* Link state change */ ++#define INT_VR9_11G_MASK (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC) ++ ++#define ADVERTISED_MPD BIT(10) /* Multi-port device */ ++ ++#define MMD_DEVAD 0x1f ++#define MMD_ACTYPE_SHIFT 14 ++#define MMD_ACTYPE_ADDRESS (0 << MMD_ACTYPE_SHIFT) ++#define MMD_ACTYPE_DATA (1 << MMD_ACTYPE_SHIFT) ++#define MMD_ACTYPE_DATA_PI (2 << MMD_ACTYPE_SHIFT) ++#define MMD_ACTYPE_DATA_PIWR (3 << MMD_ACTYPE_SHIFT) ++ ++static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev, ++ u16 regnum) ++{ ++ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD); ++ phy_write(phydev, MII_MMDDATA, regnum); ++ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD); ++ ++ return phy_read(phydev, MII_MMDDATA); ++} ++ ++static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev, ++ u16 regnum, u16 val) ++{ ++ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD); ++ phy_write(phydev, MII_MMDDATA, regnum); ++ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD); ++ phy_write(phydev, MII_MMDDATA, val); ++ ++ return 0; ++} ++ ++static int vr9_gphy_config_init(struct phy_device *phydev) ++{ ++ int err; ++ ++ dev_dbg(&phydev->dev, "%s\n", __func__); ++ ++ /* Mask all interrupts */ ++ err = phy_write(phydev, MII_VR9_11G_IMASK, 0); ++ if (err) ++ return err; ++ ++ /* Clear all pending interrupts */ ++ phy_read(phydev, MII_VR9_11G_ISTAT); ++ ++ vr9_gphy_mmd_write(phydev, 0x1e0, 0xc5); ++ vr9_gphy_mmd_write(phydev, 0x1e1, 0x67); ++ vr9_gphy_mmd_write(phydev, 0x1e2, 0x42); ++ vr9_gphy_mmd_write(phydev, 0x1e3, 0x10); ++ vr9_gphy_mmd_write(phydev, 0x1e4, 0x70); ++ vr9_gphy_mmd_write(phydev, 0x1e5, 0x03); ++ vr9_gphy_mmd_write(phydev, 0x1e6, 0x20); ++ vr9_gphy_mmd_write(phydev, 0x1e7, 0x00); ++ vr9_gphy_mmd_write(phydev, 0x1e8, 0x40); ++ vr9_gphy_mmd_write(phydev, 0x1e9, 0x20); ++ ++ return 0; ++} ++ ++static int vr9_gphy_config_aneg(struct phy_device *phydev) ++{ ++ int reg, err; ++ ++ /* Advertise as multi-port device */ ++ reg = phy_read(phydev, MII_CTRL1000); ++ reg |= ADVERTISED_MPD; ++ err = phy_write(phydev, MII_CTRL1000, reg); ++ if (err) ++ return err; ++ ++ return genphy_config_aneg(phydev); ++} ++ ++static int vr9_gphy_ack_interrupt(struct phy_device *phydev) ++{ ++ int reg; ++ ++ /* ++ * Possible IRQ numbers: ++ * - IM3_IRL18 for GPHY0 ++ * - IM3_IRL17 for GPHY1 ++ * ++ * Due to a silicon bug IRQ lines are not really independent from ++ * each other. Sometimes the two lines are driven at the same time ++ * if only one GPHY core raises the interrupt. ++ */ ++ ++ reg = phy_read(phydev, MII_VR9_11G_ISTAT); ++ ++ return (reg < 0) ? reg : 0; ++} ++ ++static int vr9_gphy_did_interrupt(struct phy_device *phydev) ++{ ++ int reg; ++ ++ reg = phy_read(phydev, MII_VR9_11G_ISTAT); ++ ++ return reg > 0; ++} ++ ++static int vr9_gphy_config_intr(struct phy_device *phydev) ++{ ++ int err; ++ ++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) ++ err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK); ++ else ++ err = phy_write(phydev, MII_VR9_11G_IMASK, 0); ++ ++ return err; ++} ++ ++static struct phy_driver lantiq_phy[] = { ++ { ++ .phy_id = 0xd565a400, ++ .phy_id_mask = 0xfffffff8, ++ .name = "Lantiq XWAY PEF7071", ++ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), ++ .flags = 0, /*PHY_HAS_INTERRUPT,*/ ++ .config_init = vr9_gphy_config_init, ++ .config_aneg = vr9_gphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = vr9_gphy_ack_interrupt, ++ .did_interrupt = vr9_gphy_did_interrupt, ++ .config_intr = vr9_gphy_config_intr, ++ .driver = { .owner = THIS_MODULE }, ++ }, { ++ .phy_id = 0x030260D0, ++ .phy_id_mask = 0xfffffff0, ++ .name = "Lantiq XWAY VR9 GPHY 11G v1.3", ++ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), ++ .flags = 0, /*PHY_HAS_INTERRUPT,*/ ++ .config_init = vr9_gphy_config_init, ++ .config_aneg = vr9_gphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = vr9_gphy_ack_interrupt, ++ .did_interrupt = vr9_gphy_did_interrupt, ++ .config_intr = vr9_gphy_config_intr, ++ .driver = { .owner = THIS_MODULE }, ++ }, { ++ .phy_id = 0xd565a408, ++ .phy_id_mask = 0xfffffff8, ++ .name = "Lantiq XWAY VR9 GPHY 11G v1.4", ++ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), ++ .flags = 0, /*PHY_HAS_INTERRUPT,*/ ++ .config_init = vr9_gphy_config_init, ++ .config_aneg = vr9_gphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = vr9_gphy_ack_interrupt, ++ .did_interrupt = vr9_gphy_did_interrupt, ++ .config_intr = vr9_gphy_config_intr, ++ .driver = { .owner = THIS_MODULE }, ++ }, { ++ .phy_id = 0xd565a418, ++ .phy_id_mask = 0xfffffff8, ++ .name = "Lantiq XWAY XRX PHY22F v1.4", ++ .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), ++ .flags = 0, /*PHY_HAS_INTERRUPT,*/ ++ .config_init = vr9_gphy_config_init, ++ .config_aneg = vr9_gphy_config_aneg, ++ .read_status = genphy_read_status, ++ .ack_interrupt = vr9_gphy_ack_interrupt, ++ .did_interrupt = vr9_gphy_did_interrupt, ++ .config_intr = vr9_gphy_config_intr, ++ .driver = { .owner = THIS_MODULE }, ++ }, ++}; ++ ++static int __init ltq_phy_init(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) { ++ int err = phy_driver_register(&lantiq_phy[i]); ++ if (err) ++ pr_err("lantiq_phy: failed to load %s\n", lantiq_phy[i].name); ++ } ++ ++ return 0; ++} ++ ++static void __exit ltq_phy_exit(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(lantiq_phy); i++) ++ phy_driver_unregister(&lantiq_phy[i]); ++} ++ ++module_init(ltq_phy_init); ++module_exit(ltq_phy_exit); ++ ++MODULE_DESCRIPTION("Lantiq PHY drivers"); ++MODULE_AUTHOR("Daniel Schwierzeck "); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/patches-4.1/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch b/target/linux/lantiq/patches-4.1/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch new file mode 100644 index 0000000..b69b2a9 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch @@ -0,0 +1,364 @@ +From 77e89d5a28be35058041c79e9874ab26f222c603 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Mon, 22 Oct 2012 09:26:24 +0200 +Subject: [PATCH 24/36] NET: lantiq: adds PHY11G firmware blobs + +Signed-off-by: John Crispin +--- + firmware/Makefile | 4 + + firmware/lantiq/COPYING | 286 +++++++++++++++++++++++++++++++++++++++++++++++ + firmware/lantiq/README | 45 ++++++++ + 3 files changed, 335 insertions(+) + create mode 100644 firmware/lantiq/COPYING + create mode 100644 firmware/lantiq/README + +--- a/firmware/Makefile ++++ b/firmware/Makefile +@@ -134,6 +134,10 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_P + fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw + fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw + fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin ++fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy11g_a1x.bin ++fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy11g_a2x.bin ++fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy22f_a1x.bin ++fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/vr9_phy22f_a2x.bin + fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin + + fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) +--- /dev/null ++++ b/firmware/lantiq/COPYING +@@ -0,0 +1,286 @@ ++All firmware files are copyrighted by Lantiq Deutschland GmbH. ++The files have been extracted from header files found in Lantiq BSPs. ++If not stated otherwise all files are licensed under GPL. ++ ++======================================================================= ++ ++ GNU GENERAL PUBLIC LICENSE ++ Version 2, June 1991 ++ ++ Copyright (C) 1989, 1991 Free Software Foundation, Inc. ++ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ Everyone is permitted to copy and distribute verbatim copies ++ of this license document, but changing it is not allowed. ++ ++ Preamble ++ ++ The licenses for most software are designed to take away your ++freedom to share and change it. By contrast, the GNU General Public ++License is intended to guarantee your freedom to share and change free ++software--to make sure the software is free for all its users. This ++General Public License applies to most of the Free Software ++Foundation's software and to any other program whose authors commit to ++using it. (Some other Free Software Foundation software is covered by ++the GNU Library General Public License instead.) You can apply it to ++your programs, too. ++ ++ When we speak of free software, we are referring to freedom, not ++price. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING ++WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR ++REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, ++INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING ++OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED ++TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY ++YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER ++PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE ++POSSIBILITY OF SUCH DAMAGES. ++ ++ END OF TERMS AND CONDITIONS +--- /dev/null ++++ b/firmware/lantiq/README +@@ -0,0 +1,45 @@ ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++# (C) Copyright 2007 - 2012 ++# Lantiq Deutschland GmbH ++# ++# (C) Copyright 2012 ++# Daniel Schwierzeck ++# ++ ++# ++# How to use ++# ++Configure kernel with: ++CONFIG_FW_LOADER=y ++CONFIG_EXTRA_FIRMWARE_DIR="FIRMWARE_DIR" ++CONFIG_EXTRA_FIRMWARE="FIRMWARE_FILES" ++ ++where FIRMWARE_DIR should point to this git tree and FIRMWARE_FILES is a list ++of space separated files from list below. ++ ++# ++# Firmware files ++# ++ ++# GPHY core on Lantiq XWAY VR9 v1.1 ++lantiq/vr9_phy11g_a1x.bin ++lantiq/vr9_phy22f_a1x.bin ++ ++# GPHY core on Lantiq XWAY VR9 v1.2 ++lantiq/vr9_phy11g_a2x.bin ++lantiq/vr9_phy22f_a2x.bin diff --git a/target/linux/lantiq/patches-4.1/0025-NET-MIPS-lantiq-adds-xrx200-net.patch b/target/linux/lantiq/patches-4.1/0025-NET-MIPS-lantiq-adds-xrx200-net.patch new file mode 100644 index 0000000..f2a9d1b --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0025-NET-MIPS-lantiq-adds-xrx200-net.patch @@ -0,0 +1,3339 @@ +From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Mon, 22 Oct 2012 12:22:23 +0200 +Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net + +--- + drivers/net/ethernet/Kconfig | 8 +- + drivers/net/ethernet/Makefile | 1 + + drivers/net/ethernet/lantiq_pce.h | 163 +++ + drivers/net/ethernet/lantiq_xrx200.c | 1798 +++++++++++++++++++++++++++++++ + drivers/net/ethernet/lantiq_xrx200_sw.h | 1328 +++++++++++++++++++++++ + 5 files changed, 3297 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/lantiq_pce.h + create mode 100644 drivers/net/ethernet/lantiq_xrx200.c + create mode 100644 drivers/net/ethernet/lantiq_xrx200_sw.h + +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -101,7 +101,13 @@ config LANTIQ_ETOP + tristate "Lantiq SoC ETOP driver" + depends on SOC_TYPE_XWAY + ---help--- +- Support for the MII0 inside the Lantiq SoC ++ Support for the MII0 inside the Lantiq ADSL SoC ++ ++config LANTIQ_XRX200 ++ tristate "Lantiq SoC XRX200 driver" ++ depends on SOC_TYPE_XWAY ++ ---help--- ++ Support for the MII0 inside the Lantiq VDSL SoC + + source "drivers/net/ethernet/marvell/Kconfig" + source "drivers/net/ethernet/mellanox/Kconfig" +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -43,6 +43,7 @@ obj-$(CONFIG_IP1000) += icplus/ + obj-$(CONFIG_JME) += jme.o + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o ++obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o + obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ + obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ + obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_pce.h +@@ -0,0 +1,163 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2012 John Crispin ++ * ++ * PCE microcode extracted from UGW5.2 switch api ++ */ ++ ++/* Switch API Micro Code V0.3 */ ++enum { ++ OUT_MAC0 = 0, ++ OUT_MAC1, ++ OUT_MAC2, ++ OUT_MAC3, ++ OUT_MAC4, ++ OUT_MAC5, ++ OUT_ETHTYP, ++ OUT_VTAG0, ++ OUT_VTAG1, ++ OUT_ITAG0, ++ OUT_ITAG1, /*10 */ ++ OUT_ITAG2, ++ OUT_ITAG3, ++ OUT_IP0, ++ OUT_IP1, ++ OUT_IP2, ++ OUT_IP3, ++ OUT_SIP0, ++ OUT_SIP1, ++ OUT_SIP2, ++ OUT_SIP3, /*20*/ ++ OUT_SIP4, ++ OUT_SIP5, ++ OUT_SIP6, ++ OUT_SIP7, ++ OUT_DIP0, ++ OUT_DIP1, ++ OUT_DIP2, ++ OUT_DIP3, ++ OUT_DIP4, ++ OUT_DIP5, /*30*/ ++ OUT_DIP6, ++ OUT_DIP7, ++ OUT_SESID, ++ OUT_PROT, ++ OUT_APP0, ++ OUT_APP1, ++ OUT_IGMP0, ++ OUT_IGMP1, ++ OUT_IPOFF, /*39*/ ++ OUT_NONE = 63 ++}; ++ ++/* parser's microcode length type */ ++#define INSTR 0 ++#define IPV6 1 ++#define LENACCU 2 ++ ++/* parser's microcode flag type */ ++enum { ++ FLAG_ITAG = 0, ++ FLAG_VLAN, ++ FLAG_SNAP, ++ FLAG_PPPOE, ++ FLAG_IPV6, ++ FLAG_IPV6FL, ++ FLAG_IPV4, ++ FLAG_IGMP, ++ FLAG_TU, ++ FLAG_HOP, ++ FLAG_NN1, /*10 */ ++ FLAG_NN2, ++ FLAG_END, ++ FLAG_NO, /*13*/ ++}; ++ ++/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */ ++#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \ ++ { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }} ++struct pce_microcode { ++ unsigned short val[4]; ++/* unsigned short val_2; ++ unsigned short val_1; ++ unsigned short val_0;*/ ++} pce_microcode[] = { ++ /* value mask ns fields L type flags ipv4_len */ ++ MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0), ++ MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), ++ MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0), ++ MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1), ++ MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0), ++ MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0), ++ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0), ++ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0), ++ MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0), ++ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0), ++ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), ++}; +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -0,0 +1,1796 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland ++ * Copyright (C) 2012 John Crispin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "lantiq_pce.h" ++#include "lantiq_xrx200_sw.h" ++ ++#define SW_POLLING ++#define SW_ROUTING ++#define SW_PORTMAP ++ ++#ifdef SW_ROUTING ++ #ifdef SW_PORTMAP ++#define XRX200_MAX_DEV 2 ++ #else ++#define XRX200_MAX_DEV 2 ++ #endif ++#else ++#define XRX200_MAX_DEV 1 ++#endif ++ ++#define XRX200_MAX_VLAN 64 ++#define XRX200_PCE_ACTVLAN_IDX 0x01 ++#define XRX200_PCE_VLANMAP_IDX 0x02 ++ ++#define XRX200_MAX_PORT 7 ++#define XRX200_MAX_DMA 8 ++ ++#define XRX200_HEADROOM 4 ++ ++#define XRX200_TX_TIMEOUT (10 * HZ) ++ ++/* port type */ ++#define XRX200_PORT_TYPE_PHY 1 ++#define XRX200_PORT_TYPE_MAC 2 ++ ++/* DMA */ ++#define XRX200_DMA_DATA_LEN 0x600 ++#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0 ++#define XRX200_DMA_RX 0 ++#define XRX200_DMA_TX 1 ++#define XRX200_DMA_IS_TX(x) (x%2) ++#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x)) ++ ++/* fetch / store dma */ ++#define FDMA_PCTRL0 0x2A00 ++#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18)) ++#define SDMA_PCTRL0 0x2F00 ++#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18)) ++ ++/* buffer management */ ++#define BM_PCFG0 0x200 ++#define BM_PCFGx(x) (BM_PCFG0 + (x * 8)) ++ ++/* MDIO */ ++#define MDIO_GLOB 0x0000 ++#define MDIO_CTRL 0x0020 ++#define MDIO_READ 0x0024 ++#define MDIO_WRITE 0x0028 ++#define MDIO_PHY0 0x0054 ++#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned))) ++#define MDIO_CLK_CFG0 0x002C ++#define MDIO_CLK_CFG1 0x0030 ++ ++#define MDIO_GLOB_ENABLE 0x8000 ++#define MDIO_BUSY BIT(12) ++#define MDIO_RD BIT(11) ++#define MDIO_WR BIT(10) ++#define MDIO_MASK 0x1f ++#define MDIO_ADDRSHIFT 5 ++#define MDIO1_25MHZ 9 ++ ++#define MDIO_PHY_LINK_DOWN 0x4000 ++#define MDIO_PHY_LINK_UP 0x2000 ++ ++#define MDIO_PHY_SPEED_M10 0x0000 ++#define MDIO_PHY_SPEED_M100 0x0800 ++#define MDIO_PHY_SPEED_G1 0x1000 ++ ++#define MDIO_PHY_FDUP_EN 0x0200 ++#define MDIO_PHY_FDUP_DIS 0x0600 ++ ++#define MDIO_PHY_LINK_MASK 0x6000 ++#define MDIO_PHY_SPEED_MASK 0x1800 ++#define MDIO_PHY_FDUP_MASK 0x0600 ++#define MDIO_PHY_ADDR_MASK 0x001f ++#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \ ++ MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK ++ ++/* MII */ ++#define MII_CFG(p) (p * 8) ++ ++#define MII_CFG_EN BIT(14) ++ ++#define MII_CFG_MODE_MIIP 0x0 ++#define MII_CFG_MODE_MIIM 0x1 ++#define MII_CFG_MODE_RMIIP 0x2 ++#define MII_CFG_MODE_RMIIM 0x3 ++#define MII_CFG_MODE_RGMII 0x4 ++#define MII_CFG_MODE_MASK 0xf ++ ++#define MII_CFG_RATE_M2P5 0x00 ++#define MII_CFG_RATE_M25 0x10 ++#define MII_CFG_RATE_M125 0x20 ++#define MII_CFG_RATE_M50 0x30 ++#define MII_CFG_RATE_AUTO 0x40 ++#define MII_CFG_RATE_MASK 0x70 ++ ++/* cpu port mac */ ++#define PMAC_HD_CTL 0x0000 ++#define PMAC_RX_IPG 0x0024 ++#define PMAC_EWAN 0x002c ++ ++#define PMAC_IPG_MASK 0xf ++#define PMAC_HD_CTL_AS 0x0008 ++#define PMAC_HD_CTL_AC 0x0004 ++#define PMAC_HD_CTL_RXSH 0x0040 ++#define PMAC_HD_CTL_AST 0x0080 ++#define PMAC_HD_CTL_RST 0x0100 ++ ++/* PCE */ ++#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4)) ++#define PCE_TBL_MASK 0x1120 ++#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4)) ++#define PCE_TBL_ADDR 0x1138 ++#define PCE_TBL_CTRL 0x113c ++#define PCE_PMAP1 0x114c ++#define PCE_PMAP2 0x1150 ++#define PCE_PMAP3 0x1154 ++#define PCE_GCTRL_REG(x) (0x1158 + (x * 4)) ++#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4)) ++ ++#define PCE_TBL_BUSY BIT(15) ++#define PCE_TBL_CFG_ADDR_MASK 0x1f ++#define PCE_TBL_CFG_ADWR 0x20 ++#define PCE_TBL_CFG_ADWR_MASK 0x60 ++#define PCE_INGRESS BIT(11) ++ ++/* MAC */ ++#define MAC_FLEN_REG (0x2314) ++#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4)) ++ ++/* buffer management */ ++#define BM_PCFG(p) (0x200 + (p * 8)) ++ ++/* special tag in TX path header */ ++#define SPID_SHIFT 24 ++#define DPID_SHIFT 16 ++#define DPID_ENABLE 1 ++#define SPID_CPU_PORT 2 ++#define PORT_MAP_SEL BIT(15) ++#define PORT_MAP_EN BIT(14) ++#define PORT_MAP_SHIFT 1 ++#define PORT_MAP_MASK 0x3f ++ ++#define SPPID_MASK 0x7 ++#define SPPID_SHIFT 4 ++ ++/* MII regs not yet in linux */ ++#define MDIO_DEVAD_NONE (-1) ++#define ADVERTIZE_MPD (1 << 10) ++ ++struct xrx200_port { ++ u8 num; ++ u8 phy_addr; ++ u16 flags; ++ phy_interface_t phy_if; ++ ++ int link; ++ int gpio; ++ enum of_gpio_flags gpio_flags; ++ ++ struct phy_device *phydev; ++ struct device_node *phy_node; ++}; ++ ++struct xrx200_chan { ++ int idx; ++ int refcount; ++ int tx_free; ++ ++ struct net_device dummy_dev; ++ struct net_device *devs[XRX200_MAX_DEV]; ++ ++ struct tasklet_struct tasklet; ++ struct napi_struct napi; ++ struct ltq_dma_channel dma; ++ struct sk_buff *skb[LTQ_DESC_NUM]; ++}; ++ ++struct xrx200_hw { ++ struct clk *clk; ++ struct mii_bus *mii_bus; ++ ++ struct xrx200_chan chan[XRX200_MAX_DMA]; ++ ++ struct net_device *devs[XRX200_MAX_DEV]; ++ int num_devs; ++ ++ int port_map[XRX200_MAX_PORT]; ++ unsigned short wan_map; ++ ++ spinlock_t lock; ++ ++ struct switch_dev swdev; ++}; ++ ++struct xrx200_priv { ++ struct net_device_stats stats; ++ int id; ++ ++ struct xrx200_port port[XRX200_MAX_PORT]; ++ int num_port; ++ bool wan; ++ bool sw; ++ unsigned short port_map; ++ unsigned char mac[6]; ++ ++ struct xrx200_hw *hw; ++}; ++ ++static __iomem void *xrx200_switch_membase; ++static __iomem void *xrx200_mii_membase; ++static __iomem void *xrx200_mdio_membase; ++static __iomem void *xrx200_pmac_membase; ++ ++#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x)) ++#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y)) ++#define ltq_switch_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_switch_membase + (z)) ++ ++#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x)) ++#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y)) ++#define ltq_mdio_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_mdio_membase + (z)) ++ ++#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x)) ++#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y)) ++#define ltq_mii_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_mii_membase + (z)) ++ ++#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x)) ++#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y)) ++#define ltq_pmac_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, xrx200_pmac_membase + (z)) ++ ++#define XRX200_GLOBAL_REGATTR(reg) \ ++ .id = reg, \ ++ .type = SWITCH_TYPE_INT, \ ++ .set = xrx200_set_global_attr, \ ++ .get = xrx200_get_global_attr ++ ++#define XRX200_PORT_REGATTR(reg) \ ++ .id = reg, \ ++ .type = SWITCH_TYPE_INT, \ ++ .set = xrx200_set_port_attr, \ ++ .get = xrx200_get_port_attr ++ ++static int xrx200sw_read_x(int reg, int x) ++{ ++ int value, mask, addr; ++ ++ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); ++ value = ltq_switch_r32(addr); ++ mask = (1 << xrx200sw_reg[reg].size) - 1; ++ value = (value >> xrx200sw_reg[reg].shift); ++ ++ return (value & mask); ++} ++ ++static int xrx200sw_read(int reg) ++{ ++ return xrx200sw_read_x(reg, 0); ++} ++ ++static void xrx200sw_write_x(int value, int reg, int x) ++{ ++ int mask, addr; ++ ++ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); ++ mask = (1 << xrx200sw_reg[reg].size) - 1; ++ mask = (mask << xrx200sw_reg[reg].shift); ++ value = (value << xrx200sw_reg[reg].shift) & mask; ++ ++ ltq_switch_w32_mask(mask, value, addr); ++} ++ ++static void xrx200sw_write(int value, int reg) ++{ ++ xrx200sw_write_x(value, reg, 0); ++} ++ ++struct xrx200_pce_table_entry { ++ int index; // PCE_TBL_ADDR.ADDR = pData->table_index ++ int table; // PCE_TBL_CTRL.ADDR = pData->table ++ unsigned short key[8]; ++ unsigned short val[5]; ++ unsigned short mask; ++ unsigned short type; ++ unsigned short valid; ++ unsigned short gmap; ++}; ++ ++static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl) ++{ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // prepare the table access: ++ // PCE_TBL_ADDR.ADDR = pData->table_index ++ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); ++ // PCE_TBL_CTRL.ADDR = pData->table ++ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); ++ ++ //(address-based read) ++ xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD ++ ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access ++ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // read the keys ++ tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7); ++ tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6); ++ tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5); ++ tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4); ++ tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3); ++ tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2); ++ tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1); ++ tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0); ++ ++ // read the values ++ tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4); ++ tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3); ++ tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2); ++ tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1); ++ tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0); ++ ++ // read the mask ++ tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0); ++ // read the type ++ tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE); ++ // read the valid flag ++ tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD); ++ // read the group map ++ tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP); ++ ++ return 0; ++} ++ ++static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl) ++{ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ // prepare the table access: ++ // PCE_TBL_ADDR.ADDR = pData->table_index ++ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); ++ // PCE_TBL_CTRL.ADDR = pData->table ++ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); ++ ++ //(address-based write) ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD ++ ++ // read the keys ++ xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7); ++ xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6); ++ xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5); ++ xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4); ++ xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3); ++ xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2); ++ xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1); ++ xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0); ++ ++ // read the values ++ xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4); ++ xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3); ++ xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2); ++ xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1); ++ xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0); ++ ++ // read the mask ++ xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0); ++ // read the type ++ xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE); ++ // read the valid flag ++ xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD); ++ // read the group map ++ xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP); ++ ++ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access ++ ++ // wait until hardware is ready ++ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; ++ ++ return 0; ++} ++ ++static void xrx200sw_fixup_pvids(void) ++{ ++ int index, p, portmap, untagged; ++ struct xrx200_pce_table_entry tem; ++ struct xrx200_pce_table_entry tev; ++ ++ portmap = 0; ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ portmap |= BIT(p); ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ ++ for (index = XRX200_MAX_VLAN; index-- > 0;) ++ { ++ tev.index = index; ++ xrx200_pce_table_entry_read(&tev); ++ ++ if (tev.valid == 0) ++ continue; ++ ++ tem.index = index; ++ xrx200_pce_table_entry_read(&tem); ++ ++ if (tem.val[0] == 0) ++ continue; ++ ++ untagged = portmap & (tem.val[1] ^ tem.val[2]); ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ if (untagged & BIT(p)) ++ { ++ portmap &= ~BIT(p); ++ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); ++ } ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) ++ if (portmap & BIT(p)) ++ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); ++ } ++} ++ ++// swconfig interface ++static void xrx200_hw_init(struct xrx200_hw *hw); ++ ++// global ++static int xrx200sw_reset_switch(struct switch_dev *dev) ++{ ++ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); ++ ++ xrx200_hw_init(hw); ++ ++ return 0; ++} ++ ++static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ int p; ++ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ for (p = 0; p < XRX200_MAX_PORT; p++) { ++ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p); ++ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p); ++ } ++ ++ xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN); ++ return 0; ++} ++ ++static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ val->value.i = xrx200sw_read(attr->id); ++ return 0; ++} ++ ++static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ xrx200sw_write(val->value.i, attr->id); ++ return 0; ++} ++ ++static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ val->value.i = xrx200sw_read(attr->id); ++ return 0; ++} ++ ++// vlan ++static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ int i; ++ struct xrx200_pce_table_entry tev; ++ struct xrx200_pce_table_entry tem; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ ++ for (i = 0; i < XRX200_MAX_VLAN; i++) ++ { ++ tev.index = i; ++ xrx200_pce_table_entry_read(&tev); ++ if (tev.key[0] == val->value.i && i != val->port_vlan) ++ return -EINVAL; ++ } ++ ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ tev.key[0] = val->value.i; ++ tev.valid = val->value.i > 0; ++ xrx200_pce_table_entry_write(&tev); ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ tem.val[0] = val->value.i; ++ xrx200_pce_table_entry_write(&tem); ++ ++ xrx200sw_fixup_pvids(); ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry te; ++ ++ te.table = XRX200_PCE_ACTVLAN_IDX; ++ te.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&te); ++ val->value.i = te.key[0]; ++ ++ return 0; ++} ++ ++static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ int i, portmap, tagmap, untagged; ++ struct xrx200_pce_table_entry tem; ++ ++ portmap = 0; ++ tagmap = 0; ++ for (i = 0; i < val->len; i++) ++ { ++ struct switch_port *p = &val->value.ports[i]; ++ ++ portmap |= (1 << p->id); ++ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) ++ tagmap |= (1 << p->id); ++ } ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ ++ untagged = portmap ^ tagmap; ++ for (i = 0; i < XRX200_MAX_VLAN; i++) ++ { ++ tem.index = i; ++ xrx200_pce_table_entry_read(&tem); ++ ++ if (tem.val[0] == 0) ++ continue; ++ ++ if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i)) ++ return -EINVAL; ++ } ++ ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ ++ // auto-enable this vlan if not enabled already ++ if (tem.val[0] == 0) ++ { ++ struct switch_val v; ++ v.port_vlan = val->port_vlan; ++ v.value.i = val->port_vlan; ++ if(xrx200sw_set_vlan_vid(dev, NULL, &v)) ++ return -EINVAL; ++ ++ //read updated tem ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ } ++ ++ tem.val[1] = portmap; ++ tem.val[2] = tagmap; ++ xrx200_pce_table_entry_write(&tem); ++ ++ xrx200sw_fixup_pvids(); ++ ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) ++{ ++ int i; ++ unsigned short ports, tags; ++ struct xrx200_pce_table_entry tem; ++ ++ tem.table = XRX200_PCE_VLANMAP_IDX; ++ tem.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tem); ++ ++ ports = tem.val[1]; ++ tags = tem.val[2]; ++ ++ for (i = 0; i < XRX200_MAX_PORT; i++) { ++ struct switch_port *p; ++ ++ if (!(ports & (1 << i))) ++ continue; ++ ++ p = &val->value.ports[val->len++]; ++ p->id = i; ++ if (tags & (1 << i)) ++ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); ++ else ++ p->flags = 0; ++ } ++ ++ return 0; ++} ++ ++static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ ++ if (tev.key[0] == 0) ++ return -EINVAL; ++ ++ tev.valid = val->value.i; ++ xrx200_pce_table_entry_write(&tev); ++ ++ xrx200sw_fixup_pvids(); ++ return 0; ++} ++ ++static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, ++ struct switch_val *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = val->port_vlan; ++ xrx200_pce_table_entry_read(&tev); ++ val->value.i = tev.valid; ++ ++ return 0; ++} ++ ++// port ++static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val) ++{ ++ struct xrx200_pce_table_entry tev; ++ ++ if (port >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ tev.table = XRX200_PCE_ACTVLAN_IDX; ++ tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port); ++ xrx200_pce_table_entry_read(&tev); ++ ++ *val = tev.key[0]; ++ return 0; ++} ++ ++static int xrx200sw_get_port_link(struct switch_dev *dev, ++ int port, ++ struct switch_port_link *link) ++{ ++ if (port >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port); ++ if (!link->link) ++ return 0; ++ ++ link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port); ++ ++ link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010); ++ link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020); ++ link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port)); ++ ++ link->speed = SWITCH_PORT_SPEED_10; ++ if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port)) ++ link->speed = SWITCH_PORT_SPEED_100; ++ if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port)) ++ link->speed = SWITCH_PORT_SPEED_1000; ++ ++ return 0; ++} ++ ++static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ printk("%s %s(%d)\n", __FILE__, __func__, __LINE__); ++ if (val->port_vlan >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ if ((attr->max > 0) && (val->value.i > attr->max)) ++ return -EINVAL; ++ ++ xrx200sw_write_x(val->value.i, attr->id, val->port_vlan); ++ return 0; ++} ++ ++static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) ++{ ++ if (val->port_vlan >= XRX200_MAX_PORT) ++ return -EINVAL; ++ ++ val->value.i = xrx200sw_read_x(attr->id, val->port_vlan); ++ return 0; ++} ++ ++// attributes ++static struct switch_attr xrx200sw_globals[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .set = xrx200_set_vlan_mode_enable, ++ .get = xrx200_get_vlan_mode_enable, ++ .name = "enable_vlan", ++ .description = "Enable VLAN mode", ++ .max = 1}, ++}; ++ ++static struct switch_attr xrx200sw_port[] = { ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR), ++ .name = "uvr", ++ .description = "Unknown VLAN Rule", ++ .max = 1, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR), ++ .name = "vsr", ++ .description = "VLAN Security Rule", ++ .max = 1, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR), ++ .name = "vinr", ++ .description = "VLAN Ingress Tag Rule", ++ .max = 2, ++ }, ++ { ++ XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM), ++ .name = "tvm", ++ .description = "Transparent VLAN Mode", ++ .max = 1, ++ }, ++}; ++ ++static struct switch_attr xrx200sw_vlan[] = { ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "vid", ++ .description = "VLAN ID (0-4094)", ++ .set = xrx200sw_set_vlan_vid, ++ .get = xrx200sw_get_vlan_vid, ++ .max = 4094, ++ }, ++ { ++ .type = SWITCH_TYPE_INT, ++ .name = "enable", ++ .description = "Enable VLAN", ++ .set = xrx200sw_set_vlan_enable, ++ .get = xrx200sw_get_vlan_enable, ++ .max = 1, ++ }, ++}; ++ ++static const struct switch_dev_ops xrx200sw_ops = { ++ .attr_global = { ++ .attr = xrx200sw_globals, ++ .n_attr = ARRAY_SIZE(xrx200sw_globals), ++ }, ++ .attr_port = { ++ .attr = xrx200sw_port, ++ .n_attr = ARRAY_SIZE(xrx200sw_port), ++ }, ++ .attr_vlan = { ++ .attr = xrx200sw_vlan, ++ .n_attr = ARRAY_SIZE(xrx200sw_vlan), ++ }, ++ .get_vlan_ports = xrx200sw_get_vlan_ports, ++ .set_vlan_ports = xrx200sw_set_vlan_ports, ++ .get_port_pvid = xrx200sw_get_port_pvid, ++ .reset_switch = xrx200sw_reset_switch, ++ .get_port_link = xrx200sw_get_port_link, ++// .get_port_stats = xrx200sw_get_port_stats, //TODO ++}; ++ ++static int xrx200sw_init(struct xrx200_hw *hw) ++{ ++ int netdev_num; ++ ++ for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++) ++ { ++ struct switch_dev *swdev; ++ struct net_device *dev = hw->devs[netdev_num]; ++ struct xrx200_priv *priv = netdev_priv(dev); ++ if (!priv->sw) ++ continue; ++ ++ swdev = &hw->swdev; ++ ++ swdev->name = "Lantiq XRX200 Switch"; ++ swdev->vlans = XRX200_MAX_VLAN; ++ swdev->ports = XRX200_MAX_PORT; ++ swdev->cpu_port = 6; ++ swdev->ops = &xrx200sw_ops; ++ ++ register_switch(swdev, dev); ++ return 0; // enough switches ++ } ++ return 0; ++} ++ ++static int xrx200_open(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ unsigned long flags; ++ int i; ++ ++ for (i = 0; i < XRX200_MAX_DMA; i++) { ++ if (!priv->hw->chan[i].dma.irq) ++ continue; ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ if (!priv->hw->chan[i].refcount) { ++ if (XRX200_DMA_IS_RX(i)) ++ napi_enable(&priv->hw->chan[i].napi); ++ ltq_dma_open(&priv->hw->chan[i].dma); ++ } ++ priv->hw->chan[i].refcount++; ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ } ++ for (i = 0; i < priv->num_port; i++) ++ if (priv->port[i].phydev) ++ phy_start(priv->port[i].phydev); ++ netif_start_queue(dev); ++ ++ return 0; ++} ++ ++static int xrx200_close(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ unsigned long flags; ++ int i; ++ ++ netif_stop_queue(dev); ++ ++ for (i = 0; i < priv->num_port; i++) ++ if (priv->port[i].phydev) ++ phy_stop(priv->port[i].phydev); ++ ++ for (i = 0; i < XRX200_MAX_DMA; i++) { ++ if (!priv->hw->chan[i].dma.irq) ++ continue; ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ priv->hw->chan[i].refcount--; ++ if (!priv->hw->chan[i].refcount) { ++ if (XRX200_DMA_IS_RX(i)) ++ napi_disable(&priv->hw->chan[i].napi); ++ ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma); ++ } ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ } ++ ++ return 0; ++} ++ ++static int xrx200_alloc_skb(struct xrx200_chan *ch) ++{ ++#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD) ++ ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD); ++ if (!ch->skb[ch->dma.desc]) ++ return -ENOMEM; ++ ++ skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD); ++ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, ++ ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN, ++ DMA_FROM_DEVICE); ++ ch->dma.desc_base[ch->dma.desc].addr = ++ CPHYSADDR(ch->skb[ch->dma.desc]->data); ++ ch->dma.desc_base[ch->dma.desc].ctl = ++ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | ++ XRX200_DMA_DATA_LEN; ++ skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); ++ ++ return 0; ++} ++ ++static void xrx200_hw_receive(struct xrx200_chan *ch, int id) ++{ ++ struct net_device *dev = ch->devs[id]; ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; ++ struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ int len = (desc->ctl & LTQ_DMA_SIZE_MASK); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ if (xrx200_alloc_skb(ch)) { ++ netdev_err(dev, ++ "failed to allocate new rx buffer, stopping DMA\n"); ++ ltq_dma_close(&ch->dma); ++ } ++ ++ ch->dma.desc++; ++ ch->dma.desc %= LTQ_DESC_NUM; ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ ++ skb_put(skb, len); ++#ifdef SW_ROUTING ++ skb_pull(skb, 8); ++#endif ++ skb->dev = dev; ++ skb->protocol = eth_type_trans(skb, dev); ++ netif_receive_skb(skb); ++ priv->stats.rx_packets++; ++ priv->stats.rx_bytes+=len; ++} ++ ++static int xrx200_poll_rx(struct napi_struct *napi, int budget) ++{ ++ struct xrx200_chan *ch = container_of(napi, ++ struct xrx200_chan, napi); ++ struct xrx200_priv *priv = netdev_priv(ch->devs[0]); ++ int rx = 0; ++ int complete = 0; ++ unsigned long flags; ++ ++ while ((rx < budget) && !complete) { ++ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++#ifdef SW_ROUTING ++ struct sk_buff *skb = ch->skb[ch->dma.desc]; ++ u32 *special_tag = (u32*)skb->data; ++ int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK; ++ xrx200_hw_receive(ch, priv->hw->port_map[port]); ++#else ++ xrx200_hw_receive(ch, 0); ++#endif ++ rx++; ++ } else { ++ complete = 1; ++ } ++ } ++ if (complete || !rx) { ++ napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ } ++ return rx; ++} ++ ++static void xrx200_tx_housekeeping(unsigned long ptr) ++{ ++ struct xrx200_hw *hw = (struct xrx200_hw *) ptr; ++ struct xrx200_chan *ch = &hw->chan[XRX200_DMA_TX]; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ dev_kfree_skb_any(ch->skb[ch->tx_free]); ++ ch->skb[ch->tx_free] = NULL; ++ memset(&ch->dma.desc_base[ch->tx_free], 0, ++ sizeof(struct ltq_dma_desc)); ++ ch->tx_free++; ++ ch->tx_free %= LTQ_DESC_NUM; ++ } ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) { ++ struct netdev_queue *txq = ++ netdev_get_tx_queue(ch->devs[i], 0); ++ if (netif_tx_queue_stopped(txq)) ++ netif_tx_start_queue(txq); ++ } ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&hw->lock, flags); ++} ++ ++static struct net_device_stats *xrx200_get_stats (struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ ++ return &priv->stats; ++} ++ ++static void xrx200_tx_timeout(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ ++ printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name); ++ ++ priv->stats.tx_errors++; ++ netif_wake_queue(dev); ++} ++ ++static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ int queue = skb_get_queue_mapping(skb); ++ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX]; ++ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; ++ unsigned long flags; ++ u32 byte_offset; ++ int len; ++#ifdef SW_ROUTING ++ #ifdef SW_PORTMAP ++ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | PORT_MAP_SEL | PORT_MAP_EN | DPID_ENABLE; ++ #else ++ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE; ++ #endif ++#endif ++ ++ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; ++ ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { ++ netdev_err(dev, "tx ring full\n"); ++ netif_tx_stop_queue(txq); ++ return NETDEV_TX_BUSY; ++ } ++#ifdef SW_ROUTING ++ #ifdef SW_PORTMAP ++ special_tag |= priv->port_map << PORT_MAP_SHIFT; ++ #else ++ if(priv->id) ++ special_tag |= (1 << DPID_SHIFT); ++ #endif ++ if(skb_headroom(skb) < 4) { ++ struct sk_buff *tmp = skb_realloc_headroom(skb, 4); ++ dev_kfree_skb_any(skb); ++ skb = tmp; ++ } ++ skb_push(skb, 4); ++ memcpy(skb->data, &special_tag, sizeof(u32)); ++ len += 4; ++#endif ++ ++ /* dma needs to start on a 16 byte aligned address */ ++ byte_offset = CPHYSADDR(skb->data) % 16; ++ ch->skb[ch->dma.desc] = skb; ++ ++ dev->trans_start = jiffies; ++ ++ spin_lock_irqsave(&priv->hw->lock, flags); ++ desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, ++ DMA_TO_DEVICE)) - byte_offset; ++ wmb(); ++ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | ++ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); ++ ch->dma.desc++; ++ ch->dma.desc %= LTQ_DESC_NUM; ++ spin_unlock_irqrestore(&priv->hw->lock, flags); ++ ++ if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ netif_tx_stop_queue(txq); ++ ++ priv->stats.tx_packets++; ++ priv->stats.tx_bytes+=len; ++ ++ return NETDEV_TX_OK; ++} ++ ++static irqreturn_t xrx200_dma_irq(int irq, void *priv) ++{ ++ struct xrx200_hw *hw = priv; ++ int ch = irq - XRX200_DMA_IRQ; ++ ++ if (ch % 2) ++ tasklet_schedule(&hw->chan[ch].tasklet); ++ else ++ napi_schedule(&hw->chan[ch].napi); ++ ++ return IRQ_HANDLED; ++} ++ ++static int xrx200_dma_init(struct xrx200_hw *hw) ++{ ++ int i, err = 0; ++ ++ ltq_dma_init_port(DMA_PORT_ETOP); ++ ++ for (i = 0; i < 8 && !err; i++) { ++ int irq = XRX200_DMA_IRQ + i; ++ struct xrx200_chan *ch = &hw->chan[i]; ++ ++ ch->idx = ch->dma.nr = i; ++ ++ if (i == XRX200_DMA_TX) { ++ ltq_dma_alloc_tx(&ch->dma); ++ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw); ++ } else if (i == XRX200_DMA_RX) { ++ ltq_dma_alloc_rx(&ch->dma); ++ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; ++ ch->dma.desc++) ++ if (xrx200_alloc_skb(ch)) ++ err = -ENOMEM; ++ ch->dma.desc = 0; ++ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw); ++ } else ++ continue; ++ ++ if (!err) ++ ch->dma.irq = irq; ++ } ++ ++ return err; ++} ++ ++#ifdef SW_POLLING ++static void xrx200_gmac_update(struct xrx200_port *port) ++{ ++ u16 phyaddr = port->phydev->addr & MDIO_PHY_ADDR_MASK; ++ u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK; ++ u16 miirate = 0; ++ ++ switch (port->phydev->speed) { ++ case SPEED_1000: ++ phyaddr |= MDIO_PHY_SPEED_G1; ++ miirate = MII_CFG_RATE_M125; ++ break; ++ ++ case SPEED_100: ++ phyaddr |= MDIO_PHY_SPEED_M100; ++ switch (miimode) { ++ case MII_CFG_MODE_RMIIM: ++ case MII_CFG_MODE_RMIIP: ++ miirate = MII_CFG_RATE_M50; ++ break; ++ default: ++ miirate = MII_CFG_RATE_M25; ++ break; ++ } ++ break; ++ ++ default: ++ phyaddr |= MDIO_PHY_SPEED_M10; ++ miirate = MII_CFG_RATE_M2P5; ++ break; ++ } ++ ++ if (port->phydev->link) ++ phyaddr |= MDIO_PHY_LINK_UP; ++ else ++ phyaddr |= MDIO_PHY_LINK_DOWN; ++ ++ if (port->phydev->duplex == DUPLEX_FULL) ++ phyaddr |= MDIO_PHY_FDUP_EN; ++ else ++ phyaddr |= MDIO_PHY_FDUP_DIS; ++ ++ ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num)); ++ ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num)); ++ udelay(1); ++} ++#else ++static void xrx200_gmac_update(struct xrx200_port *port) ++{ ++ ++} ++#endif ++ ++static void xrx200_mdio_link(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ int i; ++ ++ for (i = 0; i < priv->num_port; i++) { ++ if (!priv->port[i].phydev) ++ continue; ++ ++ if (priv->port[i].link != priv->port[i].phydev->link) { ++ xrx200_gmac_update(&priv->port[i]); ++ priv->port[i].link = priv->port[i].phydev->link; ++ netdev_info(dev, "port %d %s link\n", ++ priv->port[i].num, ++ (priv->port[i].link)?("got"):("lost")); ++ } ++ } ++} ++ ++static inline int xrx200_mdio_poll(struct mii_bus *bus) ++{ ++ unsigned cnt = 10000; ++ ++ while (likely(cnt--)) { ++ unsigned ctrl = ltq_mdio_r32(MDIO_CTRL); ++ if ((ctrl & MDIO_BUSY) == 0) ++ return 0; ++ } ++ ++ return 1; ++} ++ ++static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) ++{ ++ if (xrx200_mdio_poll(bus)) ++ return 1; ++ ++ ltq_mdio_w32(val, MDIO_WRITE); ++ ltq_mdio_w32(MDIO_BUSY | MDIO_WR | ++ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | ++ (reg & MDIO_MASK), ++ MDIO_CTRL); ++ ++ return 0; ++} ++ ++static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg) ++{ ++ if (xrx200_mdio_poll(bus)) ++ return -1; ++ ++ ltq_mdio_w32(MDIO_BUSY | MDIO_RD | ++ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | ++ (reg & MDIO_MASK), ++ MDIO_CTRL); ++ ++ if (xrx200_mdio_poll(bus)) ++ return -1; ++ ++ return ltq_mdio_r32(MDIO_READ); ++} ++ ++static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ unsigned val; ++ ++ phydev = priv->hw->mii_bus->phy_map[port->phy_addr]; ++ ++ if (!phydev) { ++ netdev_err(dev, "no PHY found\n"); ++ return -ENODEV; ++ } ++ ++ phydev = phy_connect(dev, dev_name(&phydev->dev), &xrx200_mdio_link, ++ port->phy_if); ++ ++ if (IS_ERR(phydev)) { ++ netdev_err(dev, "Could not attach to PHY\n"); ++ return PTR_ERR(phydev); ++ } ++ ++ phydev->supported &= (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_1000baseT_Half ++ | SUPPORTED_1000baseT_Full ++ | SUPPORTED_Autoneg ++ | SUPPORTED_MII ++ | SUPPORTED_TP); ++ phydev->advertising = phydev->supported; ++ port->phydev = phydev; ++ ++ pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", ++ dev->name, phydev->drv->name, ++ dev_name(&phydev->dev), phydev->irq); ++ ++#ifdef SW_POLLING ++ phy_read_status(phydev); ++ ++ val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000); ++ val |= ADVERTIZE_MPD; ++ xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val); ++ xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040); ++ ++ phy_start_aneg(phydev); ++#endif ++ return 0; ++} ++ ++static void xrx200_port_config(struct xrx200_priv *priv, ++ const struct xrx200_port *port) ++{ ++ u16 miimode = 0; ++ ++ switch (port->num) { ++ case 0: /* xMII0 */ ++ case 1: /* xMII1 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ if (port->flags & XRX200_PORT_TYPE_PHY) ++ /* MII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ else ++ /* MII PHY mode, connected to external MAC */ ++ miimode = MII_CFG_MODE_MIIP; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ if (port->flags & XRX200_PORT_TYPE_PHY) ++ /* RMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RMIIM; ++ else ++ /* RMII PHY mode, connected to external MAC */ ++ miimode = MII_CFG_MODE_RMIIP; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ /* RGMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RGMII; ++ break; ++ default: ++ break; ++ } ++ break; ++ case 2: /* internal GPHY0 */ ++ case 3: /* internal GPHY0 */ ++ case 4: /* internal GPHY1 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ case PHY_INTERFACE_MODE_GMII: ++ /* MII MAC mode, connected to internal GPHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ break; ++ default: ++ break; ++ } ++ break; ++ case 5: /* internal GPHY1 or xMII2 */ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_MII: ++ /* MII MAC mode, connected to internal GPHY */ ++ miimode = MII_CFG_MODE_MIIM; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ /* RGMII MAC mode, connected to external PHY */ ++ miimode = MII_CFG_MODE_RGMII; ++ break; ++ default: ++ break; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN, ++ MII_CFG(port->num)); ++} ++ ++static int xrx200_init(struct net_device *dev) ++{ ++ struct xrx200_priv *priv = netdev_priv(dev); ++ struct sockaddr mac; ++ int err, i; ++ ++#ifndef SW_POLLING ++ unsigned int reg = 0; ++ ++ /* enable auto polling */ ++ for (i = 0; i < priv->num_port; i++) ++ reg |= BIT(priv->port[i].num); ++ ltq_mdio_w32(reg, MDIO_CLK_CFG0); ++ ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1); ++#endif ++ ++ /* setup each port */ ++ for (i = 0; i < priv->num_port; i++) ++ xrx200_port_config(priv, &priv->port[i]); ++ ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ if (!is_valid_ether_addr(mac.sa_data)) { ++ pr_warn("net-xrx200: invalid MAC, using random\n"); ++ eth_random_addr(mac.sa_data); ++ dev->addr_assign_type |= NET_ADDR_RANDOM; ++ } ++ ++ err = eth_mac_addr(dev, &mac); ++ if (err) ++ goto err_netdev; ++ ++ for (i = 0; i < priv->num_port; i++) ++ if (xrx200_mdio_probe(dev, &priv->port[i])) ++ pr_warn("xrx200-mdio: probing phy of port %d failed\n", ++ priv->port[i].num); ++ ++ return 0; ++ ++err_netdev: ++ unregister_netdev(dev); ++ free_netdev(dev); ++ return err; ++} ++ ++static void xrx200_pci_microcode(void) ++{ ++ int i; ++ ++ ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK, ++ PCE_TBL_CFG_ADWR, PCE_TBL_CTRL); ++ ltq_switch_w32(0, PCE_TBL_MASK); ++ ++ for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) { ++ ltq_switch_w32(i, PCE_TBL_ADDR); ++ ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0)); ++ ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1)); ++ ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2)); ++ ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3)); ++ ++ // start the table access: ++ ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL); ++ while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY); ++ } ++ ++ /* tell the switch that the microcode is loaded */ ++ ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0)); ++} ++ ++static void xrx200_hw_init(struct xrx200_hw *hw) ++{ ++ int i; ++ ++ /* enable clock gate */ ++ clk_enable(hw->clk); ++ ++ ltq_switch_w32(1, 0); ++ mdelay(100); ++ ltq_switch_w32(0, 0); ++ /* ++ * TODO: we should really disbale all phys/miis here and explicitly ++ * enable them in the device secific init function ++ */ ++ ++ /* disable port fetch/store dma */ ++ for (i = 0; i < 7; i++ ) { ++ ltq_switch_w32(0, FDMA_PCTRLx(i)); ++ ltq_switch_w32(0, SDMA_PCTRLx(i)); ++ } ++ ++ /* enable Switch */ ++ ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB); ++ ++ /* load the pce microcode */ ++ xrx200_pci_microcode(); ++ ++ /* Default unknown Broadcat/Multicast/Unicast port maps */ ++ ltq_switch_w32(0x7f, PCE_PMAP1); ++ ltq_switch_w32(0x7f, PCE_PMAP2); ++ ltq_switch_w32(0x7f, PCE_PMAP3); ++ ++ /* RMON Counter Enable for all physical ports */ ++ for (i = 0; i < 7; i++) ++ ltq_switch_w32(0x1, BM_PCFG(i)); ++ ++ /* disable auto polling */ ++ ltq_mdio_w32(0x0, MDIO_CLK_CFG0); ++ ++ /* enable port statistic counters */ ++ for (i = 0; i < 7; i++) ++ ltq_switch_w32(0x1, BM_PCFGx(i)); ++ ++ /* set IPG to 12 */ ++ ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG); ++ ++#ifdef SW_ROUTING ++ /* enable status header, enable CRC */ ++ ltq_pmac_w32_mask(0, ++ PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC, ++ PMAC_HD_CTL); ++#else ++ /* disable status header, enable CRC */ ++ ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS, ++ PMAC_HD_CTL_AC, ++ PMAC_HD_CTL); ++#endif ++ ++ /* enable port fetch/store dma & VLAN Modification */ ++ for (i = 0; i < 7; i++ ) { ++ ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i)); ++ ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i)); ++ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0)); ++ } ++ ++ /* enable special tag insertion on cpu port */ ++ ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6)); ++ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0)); ++ ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2)); ++ ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG); ++} ++ ++static void xrx200_hw_cleanup(struct xrx200_hw *hw) ++{ ++ int i; ++ ++ /* disable the switch */ ++ ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB); ++ ++ /* free the channels and IRQs */ ++ for (i = 0; i < 2; i++) { ++ ltq_dma_free(&hw->chan[i].dma); ++ if (hw->chan[i].dma.irq) ++ free_irq(hw->chan[i].dma.irq, hw); ++ } ++ ++ /* free the allocated RX ring */ ++ for (i = 0; i < LTQ_DESC_NUM; i++) ++ dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]); ++ ++ /* clear the mdio bus */ ++ mdiobus_unregister(hw->mii_bus); ++ mdiobus_free(hw->mii_bus); ++ ++ /* release the clock */ ++ clk_disable(hw->clk); ++ clk_put(hw->clk); ++} ++ ++static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np) ++{ ++ hw->mii_bus = mdiobus_alloc(); ++ if (!hw->mii_bus) ++ return -ENOMEM; ++ ++ hw->mii_bus->read = xrx200_mdio_rd; ++ hw->mii_bus->write = xrx200_mdio_wr; ++ hw->mii_bus->name = "lantiq,xrx200-mdio"; ++ snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); ++ ++ if (of_mdiobus_register(hw->mii_bus, np)) { ++ mdiobus_free(hw->mii_bus); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port) ++{ ++ const __be32 *addr, *id = of_get_property(port, "reg", NULL); ++ struct xrx200_port *p = &priv->port[priv->num_port]; ++ ++ if (!id) ++ return; ++ ++ memset(p, 0, sizeof(struct xrx200_port)); ++ p->phy_node = of_parse_phandle(port, "phy-handle", 0); ++ addr = of_get_property(p->phy_node, "reg", NULL); ++ if (!addr) ++ return; ++ ++ p->num = *id; ++ p->phy_addr = *addr; ++ p->phy_if = of_get_phy_mode(port); ++ if (p->phy_addr > 0x10) ++ p->flags = XRX200_PORT_TYPE_MAC; ++ else ++ p->flags = XRX200_PORT_TYPE_PHY; ++ priv->num_port++; ++ ++ p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags); ++ if (gpio_is_valid(p->gpio)) ++ if (!gpio_request(p->gpio, "phy-reset")) { ++ gpio_direction_output(p->gpio, ++ (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0)); ++ udelay(100); ++ gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); ++ } ++ /* is this port a wan port ? */ ++ if (priv->wan) ++ priv->hw->wan_map |= BIT(p->num); ++ ++ priv->port_map |= BIT(p->num); ++ ++ /* store the port id in the hw struct so we can map ports -> devices */ ++ priv->hw->port_map[p->num] = priv->hw->num_devs; ++} ++ ++static const struct net_device_ops xrx200_netdev_ops = { ++ .ndo_init = xrx200_init, ++ .ndo_open = xrx200_open, ++ .ndo_stop = xrx200_close, ++ .ndo_start_xmit = xrx200_start_xmit, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_get_stats = xrx200_get_stats, ++ .ndo_tx_timeout = xrx200_tx_timeout, ++}; ++ ++static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface) ++{ ++ struct xrx200_priv *priv; ++ struct device_node *port; ++ const __be32 *wan; ++ ++ /* alloc the network device */ ++ hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv)); ++ if (!hw->devs[hw->num_devs]) ++ return; ++ ++ /* setup the network device */ ++ strcpy(hw->devs[hw->num_devs]->name, "eth%d"); ++ hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops; ++ hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT; ++ hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM; ++ ++ /* setup our private data */ ++ priv = netdev_priv(hw->devs[hw->num_devs]); ++ priv->hw = hw; ++ of_get_mac_address_mtd(iface, priv->mac); ++ priv->id = hw->num_devs; ++ ++ /* is this the wan interface ? */ ++ wan = of_get_property(iface, "lantiq,wan", NULL); ++ if (wan && (*wan == 1)) ++ priv->wan = 1; ++ ++ /* should the switch be enabled on this interface ? */ ++ if (of_find_property(iface, "lantiq,switch", NULL)) ++ priv->sw = 1; ++ ++ /* load the ports that are part of the interface */ ++ for_each_child_of_node(iface, port) ++ if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port")) ++ xrx200_of_port(priv, port); ++ ++ /* register the actual device */ ++ if (!register_netdev(hw->devs[hw->num_devs])) ++ hw->num_devs++; ++} ++ ++static struct xrx200_hw xrx200_hw; ++ ++static int xrx200_probe(struct platform_device *pdev) ++{ ++ struct resource *res[4]; ++ struct device_node *mdio_np, *iface_np; ++ int i; ++ ++ /* load the memory ranges */ ++ for (i = 0; i < 4; i++) { ++ res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ if (!res[i]) { ++ dev_err(&pdev->dev, "failed to get resources\n"); ++ return -ENOENT; ++ } ++ } ++ xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]); ++ xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]); ++ xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]); ++ xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]); ++ if (!xrx200_switch_membase || !xrx200_mdio_membase || ++ !xrx200_mii_membase || !xrx200_pmac_membase) { ++ dev_err(&pdev->dev, "failed to request and remap io ranges \n"); ++ return -ENOMEM; ++ } ++ ++ /* get the clock */ ++ xrx200_hw.clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(xrx200_hw.clk)) { ++ dev_err(&pdev->dev, "failed to get clock\n"); ++ return PTR_ERR(xrx200_hw.clk); ++ } ++ ++ /* bring up the dma engine and IP core */ ++ spin_lock_init(&xrx200_hw.lock); ++ xrx200_dma_init(&xrx200_hw); ++ xrx200_hw_init(&xrx200_hw); ++ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw); ++ ++ /* bring up the mdio bus */ ++ mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL, ++ "lantiq,xrx200-mdio"); ++ if (mdio_np) ++ if (xrx200_of_mdio(&xrx200_hw, mdio_np)) ++ dev_err(&pdev->dev, "mdio probe failed\n"); ++ ++ /* load the interfaces */ ++ for_each_child_of_node(pdev->dev.of_node, iface_np) ++ if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) { ++ if (xrx200_hw.num_devs < XRX200_MAX_DEV) ++ xrx200_of_iface(&xrx200_hw, iface_np); ++ else ++ dev_err(&pdev->dev, ++ "only %d interfaces allowed\n", ++ XRX200_MAX_DEV); ++ } ++ ++ if (!xrx200_hw.num_devs) { ++ xrx200_hw_cleanup(&xrx200_hw); ++ dev_err(&pdev->dev, "failed to load interfaces\n"); ++ return -ENOENT; ++ } ++ ++ xrx200sw_init(&xrx200_hw); ++ ++ /* set wan port mask */ ++ ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN); ++ ++ for (i = 0; i < xrx200_hw.num_devs; i++) { ++ xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i]; ++ xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i]; ++ } ++ ++ /* setup NAPI */ ++ init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev); ++ netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev, ++ &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32); ++ ++ platform_set_drvdata(pdev, &xrx200_hw); ++ ++ return 0; ++} ++ ++static int xrx200_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct xrx200_priv *priv; ++ ++ if (!dev) ++ return 0; ++ ++ priv = netdev_priv(dev); ++ ++ /* free stack related instances */ ++ netif_stop_queue(dev); ++ netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi); ++ ++ /* shut down hardware */ ++ xrx200_hw_cleanup(&xrx200_hw); ++ ++ /* remove the actual device */ ++ unregister_netdev(dev); ++ free_netdev(dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id xrx200_match[] = { ++ { .compatible = "lantiq,xrx200-net" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, xrx200_match); ++ ++static struct platform_driver xrx200_driver = { ++ .probe = xrx200_probe, ++ .remove = xrx200_remove, ++ .driver = { ++ .name = "lantiq,xrx200-net", ++ .of_match_table = xrx200_match, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(xrx200_driver); ++ ++MODULE_AUTHOR("John Crispin "); ++MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/drivers/net/ethernet/lantiq_xrx200_sw.h +@@ -0,0 +1,1328 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2013 Antonios Vamporakis ++ * ++ * VR9 switch registers extracted from 310TUJ0 switch api ++ * WARNING mult values of 0x00 may not be correct ++ * ++ */ ++ ++enum { ++// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */ ++// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */ ++// XRX200_ETHSW_SWRES_R0, /* Register Configuration */ ++// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */ ++// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */ ++// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */ ++// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */ ++// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */ ++// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */ ++// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */ ++// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */ ++// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */ ++// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */ ++// XRX200_ETHSW_DBG_MODE, /* Debug Mode */ ++// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */ ++// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */ ++// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */ ++// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */ ++// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */ ++// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */ ++// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */ ++// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */ ++// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */ ++// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */ ++// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */ ++// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */ ++// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */ ++// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */ ++// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */ ++// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */ ++// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */ ++// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */ ++// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */ ++// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */ ++// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */ ++// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */ ++// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */ ++// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */ ++// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */ ++// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */ ++// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */ ++// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */ ++// XRX200_ETHSW_CAP_6_APPL, /* Application table size */ ++// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */ ++// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */ ++// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */ ++// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */ ++// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */ ++// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */ ++// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */ ++// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */ ++// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */ ++// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */ ++// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */ ++// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */ ++// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */ ++// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */ ++// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */ ++// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */ ++// XRX200_ETHSW_IER, /* Interrupt Enable Register */ ++// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */ ++// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */ ++// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */ ++// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */ ++// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */ ++// XRX200_ETHSW_ISR, /* Interrupt Status Register */ ++// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */ ++// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */ ++// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */ ++// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */ ++// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */ ++// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */ ++// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */ ++// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */ ++// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */ ++// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */ ++// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */ ++// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */ ++// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */ ++// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */ ++// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */ ++// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */ ++// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */ ++// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */ ++// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */ ++// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */ ++// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */ ++// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */ ++// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */ ++// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */ ++// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */ ++// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */ ++// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */ ++// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */ ++// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */ ++// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */ ++// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */ ++// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */ ++// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */ ++// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */ ++// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */ ++// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */ ++// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */ ++// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */ ++// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */ ++// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */ ++// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */ ++// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */ ++// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */ ++// XRX200_BM_RAM_ADDR, /* RAM Address Register */ ++// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */ ++// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */ ++// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */ ++// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ ++// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */ ++// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */ ++// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */ ++// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */ ++// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */ ++// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */ ++// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */ ++// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */ ++// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */ ++// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */ ++// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */ ++// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */ ++// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */ ++// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */ ++// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */ ++// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */ ++// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */ ++// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */ ++// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */ ++// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */ ++// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */ ++// XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */ ++// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */ ++// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */ ++// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */ ++// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */ ++// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */ ++// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */ ++// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */ ++// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */ ++// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */ ++// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */ ++// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */ ++// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */ ++// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */ ++// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */ ++// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */ ++// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */ ++// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */ ++// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */ ++// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */ ++// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ ++// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */ ++// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ ++// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */ ++// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */ ++// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */ ++// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */ ++// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */ ++// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */ ++// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */ ++// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */ ++// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */ ++// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */ ++// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */ ++// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */ ++// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */ ++// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */ ++// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */ ++// XRX200_BM_CISEL_PORT, /* Port Number */ ++// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */ ++// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */ ++// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */ ++// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */ ++// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */ ++// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */ ++// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */ ++// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */ ++// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */ ++// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */ ++// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */ ++// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */ ++// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */ ++// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */ ++// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */ ++// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */ ++// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */ ++// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */ ++// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */ ++// XRX200_RS_CBS_CBS, /* Committed Burst Size */ ++// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */ ++// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */ ++// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */ ++// XRX200_RS_CIR_EXP_EXP, /* Exponent */ ++// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */ ++// XRX200_RS_CIR_MANT_MANT, /* Mantissa */ ++ XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */ ++// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */ ++// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */ ++// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */ ++// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */ ++// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */ ++// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */ ++// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */ ++ XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */ ++// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */ ++ XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */ ++// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */ ++ XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */ ++// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */ ++// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */ ++// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */ ++// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */ ++ XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */ ++// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */ ++// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */ ++ XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */ ++// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */ ++ XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */ ++ XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */ ++ XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */ ++ XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */ ++ XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ ++ XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */ ++// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */ ++// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */ ++// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */ ++// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */ ++// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */ ++// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */ ++// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */ ++// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */ ++// XRX200_PCE_PMAP_1, /* Port Map Register 1 */ ++// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */ ++// XRX200_PCE_PMAP_2, /* Port Map Register 2 */ ++// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */ ++// XRX200_PCE_PMAP_3, /* Port Map Register 3 */ ++// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */ ++// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */ ++// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */ ++ XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */ ++// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */ ++// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */ ++// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */ ++// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */ ++// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */ ++// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */ ++// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */ ++// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */ ++// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */ ++// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */ ++// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */ ++// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */ ++// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */ ++// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */ ++// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */ ++// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */ ++// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */ ++// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */ ++// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */ ++// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */ ++// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */ ++// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */ ++// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */ ++// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */ ++// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */ ++// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */ ++// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */ ++// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */ ++// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */ ++// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */ ++// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */ ++// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */ ++// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */ ++// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */ ++// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */ ++// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */ ++// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */ ++// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */ ++// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */ ++// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */ ++// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */ ++// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */ ++// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */ ++// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */ ++// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */ ++// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */ ++// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */ ++// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */ ++// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */ ++// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */ ++// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */ ++// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */ ++// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */ ++// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */ ++// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */ ++// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */ ++// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */ ++// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */ ++// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */ ++// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */ ++// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */ ++// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */ ++// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */ ++// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */ ++// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */ ++// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */ ++// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */ ++// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */ ++// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */ ++// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */ ++// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */ ++// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */ ++// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */ ++// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */ ++// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */ ++// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */ ++// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */ ++// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */ ++// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */ ++ XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */ ++// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */ ++// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */ ++// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */ ++// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */ ++// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */ ++// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */ ++// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */ ++// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */ ++// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */ ++// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */ ++// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */ ++// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */ ++// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */ ++// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */ ++// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */ ++// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */ ++// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */ ++// XRX200_WOL_CTRL_PORT, /* WoL Enable */ ++// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */ ++ XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */ ++ XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */ ++ XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */ ++ XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */ ++ XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */ ++// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */ ++ XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */ ++// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */ ++// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */ ++// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */ ++// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */ ++// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */ ++// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */ ++// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */ ++// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */ ++// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */ ++// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */ ++// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */ ++// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */ ++// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */ ++// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */ ++// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */ ++// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */ ++// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */ ++// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */ ++// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */ ++// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */ ++// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */ ++// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */ ++// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */ ++// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */ ++// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */ ++// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */ ++// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */ ++// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */ ++// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */ ++// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */ ++// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */ ++// XRX200_MAC_TEST, /* MAC Test Register */ ++// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */ ++// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */ ++// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */ ++// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */ ++// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */ ++// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */ ++// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */ ++// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */ ++// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */ ++// XRX200_MAC_FLEN, /* MAC Frame Length Register */ ++// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */ ++// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */ ++// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */ ++// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */ ++// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */ ++// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */ ++// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */ ++// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */ ++// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */ ++// XRX200_MAC_PSTAT, /* MAC Port Status Register */ ++// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */ ++ XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */ ++ XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */ ++ XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */ ++// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */ ++// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */ ++ XRX200_MAC_PSTAT_LSTAT, /* Link Status */ ++// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */ ++// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */ ++// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */ ++// XRX200_MAC_PISR, /* MAC Interrupt Status Register */ ++// XRX200_MAC_PISR_PACT, /* PHY Active Status */ ++// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */ ++// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */ ++// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */ ++// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */ ++// XRX200_MAC_PISR_JAM, /* Jam Status Detected */ ++// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */ ++// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */ ++// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */ ++// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */ ++// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */ ++// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */ ++// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */ ++// XRX200_MAC_PIER_PACT, /* PHY Active Status */ ++// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */ ++// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */ ++// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */ ++// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */ ++// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */ ++// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */ ++// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */ ++// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */ ++// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */ ++// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */ ++// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */ ++// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */ ++// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */ ++// XRX200_MAC_CTRL_0, /* MAC Control Register0 */ ++// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */ ++// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */ ++// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */ ++// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */ ++// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */ ++ XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */ ++// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */ ++// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */ ++// XRX200_MAC_CTRL_1, /* MAC Control Register1 */ ++// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */ ++// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */ ++// XRX200_MAC_CTRL_2, /* MAC Control Register2 */ ++// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */ ++// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */ ++// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */ ++// XRX200_MAC_CTRL_3, /* MAC Control Register3 */ ++// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */ ++// XRX200_MAC_CTRL_4, /* MAC Control Register4 */ ++// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */ ++// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */ ++// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */ ++// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */ ++// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */ ++// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */ ++// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */ ++// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */ ++// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */ ++// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */ ++// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */ ++// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */ ++// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */ ++// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */ ++// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */ ++// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */ ++// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */ ++// XRX200_MAC_TESTEN, /* MAC Test Enable Register */ ++// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */ ++// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */ ++// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */ ++// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */ ++// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */ ++// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */ ++// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */ ++// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */ ++// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */ ++// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */ ++// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */ ++// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */ ++// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */ ++// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */ ++// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */ ++// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */ ++// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */ ++// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */ ++// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */ ++// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */ ++// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */ ++// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */ ++// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */ ++// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */ ++// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */ ++// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */ ++// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */ ++// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */ ++// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */ ++// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */ ++// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */ ++// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */ ++// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */ ++// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */ ++// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */ ++// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */ ++// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */ ++// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ ++// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */ ++// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ ++// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */ ++// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */ ++// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */ ++// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */ ++// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */ ++// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */ ++// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */ ++// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */ ++// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */ ++// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */ ++// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */ ++// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */ ++// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */ ++// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */ ++// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */ ++// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */ ++// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */ ++// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */ ++// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */ ++// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */ ++// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */ ++// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */ ++// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */ ++// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */ ++// XRX200_SDMA_IER_BFULL, /* Buffer Full */ ++// XRX200_SDMA_IER_FERR, /* Frame Error */ ++// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */ ++// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */ ++// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */ ++// XRX200_SDMA_ISR_BFULL, /* Buffer Full */ ++// XRX200_SDMA_ISR_FERR, /* Frame Error */ ++// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */ ++// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */ ++// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */ ++// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */ ++// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */ ++// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */ ++// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */ ++// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */ ++// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */ ++// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */ ++// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */ ++// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */ ++// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */ ++// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */ ++// XRX200_SDMA_PCTRL_PEN, /* Port Enable */ ++// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */ ++// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */ ++// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */ ++// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */ ++// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */ ++// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */ ++// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */ ++// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ ++// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */ ++// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ ++}; ++ ++ ++struct xrx200sw_reg { ++ int offset; ++ int shift; ++ int size; ++ int mult; ++} xrx200sw_reg[] = { ++// offeset shift size mult ++// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */ ++// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */ ++// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */ ++// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */ ++// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */ ++// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */ ++// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */ ++// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */ ++// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */ ++// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */ ++// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */ ++// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */ ++// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */ ++// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */ ++// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */ ++// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */ ++// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */ ++// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */ ++// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */ ++// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */ ++// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */ ++// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */ ++// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */ ++// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */ ++// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */ ++// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */ ++// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */ ++// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */ ++// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */ ++// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */ ++// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */ ++// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */ ++// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */ ++// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */ ++// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */ ++// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */ ++// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */ ++// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */ ++// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */ ++// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */ ++// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */ ++// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */ ++// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */ ++// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */ ++// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */ ++// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */ ++// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */ ++// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */ ++// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */ ++// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */ ++// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */ ++// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */ ++// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */ ++// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */ ++// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */ ++// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */ ++// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */ ++// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */ ++// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */ ++// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */ ++// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */ ++// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */ ++// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */ ++// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */ ++// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */ ++// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */ ++// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */ ++// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */ ++// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */ ++// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */ ++// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */ ++// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */ ++// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */ ++// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */ ++// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */ ++// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */ ++// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */ ++// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */ ++// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */ ++// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */ ++// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */ ++// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */ ++// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */ ++// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */ ++// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */ ++// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */ ++// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */ ++// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */ ++// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */ ++// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */ ++// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */ ++// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */ ++// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */ ++// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */ ++// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */ ++// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */ ++// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */ ++// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */ ++// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */ ++// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */ ++// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */ ++// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */ ++// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */ ++// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */ ++// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */ ++// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */ ++// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */ ++// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */ ++// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */ ++// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */ ++// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */ ++// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */ ++// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */ ++// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */ ++// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */ ++// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */ ++// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */ ++// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */ ++// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */ ++// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */ ++// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */ ++// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */ ++// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */ ++// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */ ++// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */ ++// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */ ++// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */ ++// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */ ++// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */ ++// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */ ++// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */ ++// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */ ++// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */ ++// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */ ++// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */ ++// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */ ++// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */ ++// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */ ++// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */ ++// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */ ++// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */ ++// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */ ++// {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */ ++// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */ ++// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */ ++// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */ ++// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */ ++// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */ ++// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */ ++// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */ ++// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */ ++// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */ ++// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */ ++// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */ ++// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */ ++// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */ ++// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */ ++// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */ ++// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */ ++// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */ ++// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */ ++// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */ ++// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */ ++// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */ ++// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */ ++// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */ ++// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ ++// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */ ++// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ ++// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */ ++// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */ ++// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */ ++// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */ ++// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */ ++// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */ ++// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */ ++// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */ ++// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */ ++// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */ ++// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */ ++// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */ ++// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */ ++// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */ ++// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */ ++// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */ ++// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */ ++// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */ ++// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */ ++// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */ ++// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */ ++// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */ ++// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */ ++// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */ ++// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */ ++// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */ ++// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */ ++// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */ ++// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */ ++// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */ ++// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */ ++// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */ ++// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */ ++// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */ ++// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */ ++// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */ ++// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */ ++// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */ ++// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */ ++// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */ ++// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */ ++// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */ ++ {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */ ++// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */ ++ {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */ ++// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */ ++ {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */ ++// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */ ++ {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */ ++// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */ ++ {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */ ++// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */ ++ {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */ ++// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */ ++ {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */ ++// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */ ++ {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */ ++// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */ ++ {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */ ++// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */ ++ {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */ ++// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */ ++ {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */ ++// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */ ++ {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */ ++// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */ ++ {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */ ++// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */ ++ {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */ ++// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */ ++// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */ ++ {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */ ++// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */ ++ {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */ ++ {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */ ++ {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */ ++ {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */ ++ {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */ ++ {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */ ++// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */ ++// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */ ++// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */ ++// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */ ++// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */ ++// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */ ++// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */ ++// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */ ++// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */ ++// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */ ++// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */ ++// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */ ++// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */ ++// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */ ++// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */ ++// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */ ++ {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */ ++// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */ ++// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */ ++// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */ ++// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */ ++// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */ ++// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */ ++// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */ ++// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */ ++// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */ ++// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */ ++// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */ ++// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */ ++// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */ ++// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */ ++// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */ ++// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */ ++// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */ ++// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */ ++// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */ ++// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */ ++// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */ ++// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */ ++// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */ ++// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */ ++// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */ ++// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */ ++// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */ ++// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */ ++// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */ ++// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */ ++// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */ ++// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */ ++// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */ ++// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */ ++// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */ ++// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */ ++// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */ ++// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */ ++// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */ ++// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */ ++// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */ ++// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */ ++// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */ ++// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */ ++// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */ ++// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */ ++// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */ ++// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */ ++// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */ ++// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */ ++// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */ ++// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */ ++// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */ ++// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */ ++// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */ ++// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */ ++// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */ ++// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */ ++// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */ ++// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */ ++// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */ ++// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */ ++// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */ ++// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */ ++// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */ ++// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */ ++// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */ ++// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */ ++// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */ ++// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */ ++// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */ ++// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */ ++// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */ ++// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */ ++// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */ ++// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */ ++// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */ ++// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */ ++// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */ ++// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */ ++// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */ ++// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */ ++// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */ ++// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */ ++// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */ ++// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */ ++// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */ ++// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */ ++// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */ ++// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */ ++// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */ ++// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */ ++// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */ ++// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */ ++// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */ ++// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */ ++// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */ ++// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */ ++// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */ ++// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */ ++// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */ ++// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */ ++// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */ ++// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */ ++// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */ ++// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */ ++// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */ ++// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */ ++// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */ ++// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */ ++// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */ ++// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */ ++// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */ ++// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */ ++// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */ ++// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */ ++ {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */ ++// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */ ++// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */ ++// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */ ++// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */ ++// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */ ++// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */ ++// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */ ++// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */ ++// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */ ++// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */ ++// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */ ++// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */ ++// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */ ++// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */ ++// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */ ++// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */ ++// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */ ++// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */ ++// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */ ++// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */ ++// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */ ++// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */ ++// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */ ++// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */ ++// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */ ++// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */ ++ {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */ ++ {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */ ++ {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */ ++ {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */ ++ {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */ ++// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */ ++ {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */ ++// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */ ++// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */ ++// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */ ++// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */ ++// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */ ++// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */ ++// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */ ++// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */ ++// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */ ++// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */ ++// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */ ++// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */ ++// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */ ++// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */ ++// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */ ++// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */ ++// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */ ++// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */ ++// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */ ++// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */ ++// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */ ++// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */ ++// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */ ++// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */ ++// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */ ++// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */ ++// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */ ++// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */ ++// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */ ++// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */ ++// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */ ++// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */ ++// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */ ++// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */ ++// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */ ++// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */ ++// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */ ++// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */ ++// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */ ++// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */ ++// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */ ++// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */ ++// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */ ++// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */ ++// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */ ++// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */ ++// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */ ++// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */ ++// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */ ++// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */ ++// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */ ++// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */ ++// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */ ++ {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */ ++ {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */ ++ {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */ ++// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */ ++// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */ ++// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */ ++// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */ ++ {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */ ++// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */ ++// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */ ++// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */ ++// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */ ++// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */ ++// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */ ++// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */ ++// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */ ++// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */ ++// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */ ++// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */ ++// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */ ++// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */ ++// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */ ++// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */ ++// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */ ++// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */ ++// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */ ++// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */ ++// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */ ++// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */ ++// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */ ++// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */ ++// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */ ++// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */ ++// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */ ++// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */ ++// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */ ++// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */ ++// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */ ++// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */ ++// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */ ++// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */ ++// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */ ++// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */ ++// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */ ++// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */ ++// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */ ++// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */ ++// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */ ++// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */ ++ {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */ ++// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */ ++// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */ ++// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */ ++// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */ ++// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */ ++// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */ ++// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */ ++// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */ ++// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */ ++// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */ ++// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */ ++// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */ ++// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */ ++// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */ ++// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */ ++// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */ ++// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */ ++// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */ ++// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */ ++// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */ ++// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */ ++// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */ ++// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */ ++// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */ ++// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */ ++// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */ ++// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */ ++// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */ ++// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */ ++// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */ ++// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */ ++// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */ ++// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */ ++// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */ ++// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */ ++// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */ ++// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */ ++// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */ ++// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */ ++// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */ ++// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */ ++// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */ ++// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */ ++// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */ ++// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */ ++// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */ ++// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */ ++// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */ ++// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */ ++// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */ ++// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */ ++// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */ ++// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */ ++// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */ ++// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */ ++// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */ ++// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */ ++// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */ ++// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */ ++// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */ ++// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */ ++// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */ ++// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */ ++// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */ ++// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */ ++// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */ ++// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */ ++// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */ ++// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */ ++// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */ ++// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */ ++// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */ ++// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */ ++// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */ ++// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */ ++// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */ ++// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */ ++// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */ ++// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */ ++// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */ ++// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */ ++// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */ ++// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */ ++// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */ ++// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */ ++// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */ ++// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */ ++// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */ ++// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */ ++// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */ ++// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */ ++// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */ ++// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */ ++// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */ ++// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */ ++// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */ ++// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */ ++// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */ ++// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */ ++// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */ ++// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */ ++// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */ ++// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */ ++// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */ ++// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */ ++// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */ ++// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */ ++// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */ ++// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */ ++// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */ ++// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */ ++// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */ ++// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */ ++// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */ ++// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */ ++// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */ ++// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */ ++// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */ ++// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */ ++// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */ ++// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */ ++// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */ ++// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */ ++// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */ ++// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */ ++// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */ ++// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */ ++// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */ ++}; ++ ++ diff --git a/target/linux/lantiq/patches-4.1/0026-NET-multi-phy-support.patch b/target/linux/lantiq/patches-4.1/0026-NET-multi-phy-support.patch new file mode 100644 index 0000000..2967bae --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0026-NET-multi-phy-support.patch @@ -0,0 +1,53 @@ +From c6feeeb407a3b8a6597ae377ba4dd138e185e3dd Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 27 Jul 2014 09:38:50 +0100 +Subject: [PATCH 26/36] NET: multi phy support + +Signed-off-by: John Crispin +--- + drivers/net/phy/phy.c | 9 ++++++--- + include/linux/phy.h | 1 + + 2 files changed, 7 insertions(+), 3 deletions(-) + +--- a/drivers/net/phy/phy.c ++++ b/drivers/net/phy/phy.c +@@ -855,7 +855,8 @@ void phy_state_machine(struct work_struc + /* If the link is down, give up on negotiation for now */ + if (!phydev->link) { + phydev->state = PHY_NOLINK; +- netif_carrier_off(phydev->attached_dev); ++ if (!phydev->no_auto_carrier_off) ++ netif_carrier_off(phydev->attached_dev); + phydev->adjust_link(phydev->attached_dev); + break; + } +@@ -928,7 +929,8 @@ void phy_state_machine(struct work_struc + netif_carrier_on(phydev->attached_dev); + } else { + phydev->state = PHY_NOLINK; +- netif_carrier_off(phydev->attached_dev); ++ if (!phydev->no_auto_carrier_off) ++ netif_carrier_off(phydev->attached_dev); + } + + phydev->adjust_link(phydev->attached_dev); +@@ -940,7 +942,8 @@ void phy_state_machine(struct work_struc + case PHY_HALTED: + if (phydev->link) { + phydev->link = 0; +- netif_carrier_off(phydev->attached_dev); ++ if (!phydev->no_auto_carrier_off) ++ netif_carrier_off(phydev->attached_dev); + phydev->adjust_link(phydev->attached_dev); + do_suspend = true; + } +--- a/include/linux/phy.h ++++ b/include/linux/phy.h +@@ -367,6 +367,7 @@ struct phy_device { + bool is_internal; + bool has_fixups; + bool suspended; ++ bool no_auto_carrier_off; + + enum phy_state state; + diff --git a/target/linux/lantiq/patches-4.1/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-4.1/0028-NET-lantiq-various-etop-fixes.patch new file mode 100644 index 0000000..3301264 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0028-NET-lantiq-various-etop-fixes.patch @@ -0,0 +1,907 @@ +From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 9 Sep 2014 22:45:34 +0200 +Subject: [PATCH 28/36] NET: lantiq: various etop fixes + +Signed-off-by: John Crispin +--- + drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- + 1 file changed, 389 insertions(+), 166 deletions(-) + +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -11,7 +11,7 @@ + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * +- * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011-12 John Crispin + */ + + #include +@@ -30,11 +30,16 @@ + #include + #include + #include ++#include + #include + #include + #include + #include + #include ++#include ++#include ++#include ++#include + + #include + +@@ -42,7 +47,7 @@ + #include + #include + +-#define LTQ_ETOP_MDIO 0x11804 ++#define LTQ_ETOP_MDIO_ACC 0x11804 + #define MDIO_REQUEST 0x80000000 + #define MDIO_READ 0x40000000 + #define MDIO_ADDR_MASK 0x1f +@@ -51,44 +56,91 @@ + #define MDIO_REG_OFFSET 0x10 + #define MDIO_VAL_MASK 0xffff + +-#define PPE32_CGEN 0x800 +-#define LQ_PPE32_ENET_MAC_CFG 0x1840 ++#define LTQ_ETOP_MDIO_CFG 0x11800 ++#define MDIO_CFG_MASK 0x6 ++ ++#define LTQ_ETOP_CFG 0x11808 ++#define LTQ_ETOP_IGPLEN 0x11820 ++#define LTQ_ETOP_MAC_CFG 0x11840 + + #define LTQ_ETOP_ENETS0 0x11850 + #define LTQ_ETOP_MAC_DA0 0x1186C + #define LTQ_ETOP_MAC_DA1 0x11870 +-#define LTQ_ETOP_CFG 0x16020 +-#define LTQ_ETOP_IGPLEN 0x16080 ++ ++#define MAC_CFG_MASK 0xfff ++#define MAC_CFG_CGEN (1 << 11) ++#define MAC_CFG_DUPLEX (1 << 2) ++#define MAC_CFG_SPEED (1 << 1) ++#define MAC_CFG_LINK (1 << 0) + + #define MAX_DMA_CHAN 0x8 + #define MAX_DMA_CRC_LEN 0x4 + #define MAX_DMA_DATA_LEN 0x600 + + #define ETOP_FTCU BIT(28) +-#define ETOP_MII_MASK 0xf +-#define ETOP_MII_NORMAL 0xd +-#define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 +-#define ETOP_CGEN 0x800 ++#define ETOP_CFG_MII0 0x01 + +-/* use 2 static channels for TX/RX */ +-#define LTQ_ETOP_TX_CHANNEL 1 +-#define LTQ_ETOP_RX_CHANNEL 6 +-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) ++#define ETOP_CFG_MASK 0xfff ++#define ETOP_CFG_FEN0 (1 << 8) ++#define ETOP_CFG_SEN0 (1 << 6) ++#define ETOP_CFG_OFF1 (1 << 3) ++#define ETOP_CFG_REMII0 (1 << 1) ++#define ETOP_CFG_OFF0 (1 << 0) ++ ++#define LTQ_GBIT_MDIO_CTL 0xCC ++#define LTQ_GBIT_MDIO_DATA 0xd0 ++#define LTQ_GBIT_GCTL0 0x68 ++#define LTQ_GBIT_PMAC_HD_CTL 0x8c ++#define LTQ_GBIT_P0_CTL 0x4 ++#define LTQ_GBIT_PMAC_RX_IPG 0xa8 ++#define LTQ_GBIT_RGMII_CTL 0x78 ++ ++#define PMAC_HD_CTL_AS (1 << 19) ++#define PMAC_HD_CTL_RXSH (1 << 22) ++ ++/* Switch Enable (0=disable, 1=enable) */ ++#define GCTL0_SE 0x80000000 ++/* Disable MDIO auto polling (0=disable, 1=enable) */ ++#define PX_CTL_DMDIO 0x00400000 ++ ++/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ ++#define MDC_CLOCK_MASK 0xff000000 ++#define MDC_CLOCK_OFFSET 24 ++ ++/* register information for the gbit's MDIO bus */ ++#define MDIO_XR9_REQUEST 0x00008000 ++#define MDIO_XR9_READ 0x00000800 ++#define MDIO_XR9_WRITE 0x00000400 ++#define MDIO_XR9_REG_MASK 0x1f ++#define MDIO_XR9_ADDR_MASK 0x1f ++#define MDIO_XR9_RD_MASK 0xffff ++#define MDIO_XR9_REG_OFFSET 0 ++#define MDIO_XR9_ADDR_OFFSET 5 ++#define MDIO_XR9_WR_OFFSET 16 + ++#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ ++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) ++ ++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ + #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) + #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) + #define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + +-#define DRV_VERSION "1.0" ++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) ++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) ++#define ltq_gbit_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) ++ ++#define DRV_VERSION "1.2" + + static void __iomem *ltq_etop_membase; ++static void __iomem *ltq_gbit_membase; + + struct ltq_etop_chan { +- int idx; + int tx_free; ++ int irq; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; +@@ -98,22 +150,35 @@ struct ltq_etop_chan { + struct ltq_etop_priv { + struct net_device *netdev; + struct platform_device *pdev; +- struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + struct phy_device *phydev; + +- struct ltq_etop_chan ch[MAX_DMA_CHAN]; +- int tx_free[MAX_DMA_CHAN >> 1]; ++ struct ltq_etop_chan txch; ++ struct ltq_etop_chan rxch; ++ ++ int tx_irq; ++ int rx_irq; ++ ++ unsigned char mac[6]; ++ int mii_mode; + + spinlock_t lock; ++ ++ struct clk *clk_ppe; ++ struct clk *clk_switch; ++ struct clk *clk_ephy; ++ struct clk *clk_ephycgu; + }; + ++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data); ++ + static int + ltq_etop_alloc_skb(struct ltq_etop_chan *ch) + { +- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); ++ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, +@@ -148,8 +213,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); ++ skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); ++ ch->netdev->stats.rx_packets++; ++ ch->netdev->stats.rx_bytes += len; + } + + static int +@@ -157,8 +225,10 @@ ltq_etop_poll_rx(struct napi_struct *nap + { + struct ltq_etop_chan *ch = container_of(napi, + struct ltq_etop_chan, napi); ++ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + int rx = 0; + int complete = 0; ++ unsigned long flags; + + while ((rx < budget) && !complete) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +@@ -172,7 +242,9 @@ ltq_etop_poll_rx(struct napi_struct *nap + } + if (complete || !rx) { + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + } + return rx; + } +@@ -184,12 +256,14 @@ ltq_etop_poll_tx(struct napi_struct *nap + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = +- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); ++ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { ++ ch->netdev->stats.tx_packets++; ++ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, +@@ -202,7 +276,9 @@ ltq_etop_poll_tx(struct napi_struct *nap + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + return 1; + } + +@@ -210,9 +286,10 @@ static irqreturn_t + ltq_etop_dma_irq(int irq, void *_priv) + { + struct ltq_etop_priv *priv = _priv; +- int ch = irq - LTQ_DMA_CH0_INT; +- +- napi_schedule(&priv->ch[ch].napi); ++ if (irq == priv->txch.dma.irq) ++ napi_schedule(&priv->txch.napi); ++ else ++ napi_schedule(&priv->rxch.napi); + return IRQ_HANDLED; + } + +@@ -224,7 +301,7 @@ ltq_etop_free_channel(struct net_device + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); +- if (IS_RX(ch->idx)) { ++ if (ch == &priv->txch) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); +@@ -235,65 +312,133 @@ static void + ltq_etop_hw_exit(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; + +- ltq_pmu_disable(PMU_PPE); +- for (i = 0; i < MAX_DMA_CHAN; i++) +- if (IS_TX(i) || IS_RX(i)) +- ltq_etop_free_channel(dev, &priv->ch[i]); ++ clk_disable(priv->clk_ppe); ++ ++ if (of_machine_is_compatible("lantiq,ar9")) ++ clk_disable(priv->clk_switch); ++ ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_disable(priv->clk_ephy); ++ clk_disable(priv->clk_ephycgu); ++ } ++ ++ ltq_etop_free_channel(dev, &priv->txch); ++ ltq_etop_free_channel(dev, &priv->rxch); ++} ++ ++static void ++ltq_etop_gbit_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ ++ clk_enable(priv->clk_switch); ++ ++ /* enable gbit port0 on the SoC */ ++ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); ++ ++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); ++ /* disable MDIO auto polling mode */ ++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); ++ /* set 1522 packet size */ ++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); ++ /* disable pmac & dmac headers */ ++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, ++ LTQ_GBIT_PMAC_HD_CTL); ++ /* Due to traffic halt when burst length 8, ++ replace default IPG value with 0x3B */ ++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); ++ /* set mdc clock to 2.5 MHz */ ++ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, ++ LTQ_GBIT_RGMII_CTL); + } + + static int + ltq_etop_hw_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ int mii_mode = priv->mii_mode; + +- ltq_pmu_enable(PMU_PPE); ++ clk_enable(priv->clk_ppe); ++ ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ ltq_etop_gbit_init(dev); ++ /* force the etops link to the gbit to MII */ ++ mii_mode = PHY_INTERFACE_MODE_MII; ++ } ++ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); ++ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | ++ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); + +- switch (priv->pldata->mii_mode) { ++ switch (mii_mode) { + case PHY_INTERFACE_MODE_RMII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_REVERSE, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + case PHY_INTERFACE_MODE_MII: +- ltq_etop_w32_mask(ETOP_MII_MASK, +- ETOP_MII_NORMAL, LTQ_ETOP_CFG); ++ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | ++ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); + break; + + default: ++ if (of_machine_is_compatible("lantiq,ase")) { ++ clk_enable(priv->clk_ephy); ++ /* disable external MII */ ++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); ++ /* enable clock for internal PHY */ ++ clk_enable(priv->clk_ephycgu); ++ /* we need to write this magic to the internal phy to ++ make it work */ ++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); ++ pr_info("Selected EPHY mode\n"); ++ break; ++ } + netdev_err(dev, "unknown mii mode %d\n", +- priv->pldata->mii_mode); ++ mii_mode); + return -ENOTSUPP; + } + +- /* enable crc generation */ +- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); ++ return 0; ++} ++ ++static int ++ltq_etop_dma_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ int tx = priv->tx_irq - LTQ_DMA_ETOP; ++ int rx = priv->rx_irq - LTQ_DMA_ETOP; ++ int err; + + ltq_dma_init_port(DMA_PORT_ETOP); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- int irq = LTQ_DMA_CH0_INT + i; +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- ch->idx = ch->dma.nr = i; +- +- if (IS_TX(i)) { +- ltq_dma_alloc_tx(&ch->dma); +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); +- } else if (IS_RX(i)) { +- ltq_dma_alloc_rx(&ch->dma); +- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; +- ch->dma.desc++) +- if (ltq_etop_alloc_skb(ch)) +- return -ENOMEM; +- ch->dma.desc = 0; +- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); ++ priv->txch.dma.nr = tx; ++ ltq_dma_alloc_tx(&priv->txch.dma); ++ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); ++ if (err) { ++ netdev_err(dev, "failed to allocate tx irq\n"); ++ goto err_out; ++ } ++ priv->txch.dma.irq = priv->tx_irq; ++ ++ priv->rxch.dma.nr = rx; ++ ltq_dma_alloc_rx(&priv->rxch.dma); ++ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; ++ priv->rxch.dma.desc++) { ++ if (ltq_etop_alloc_skb(&priv->rxch)) { ++ netdev_err(dev, "failed to allocate skbs\n"); ++ err = -ENOMEM; ++ goto err_out; + } +- ch->dma.irq = irq; + } +- return 0; ++ priv->rxch.dma.desc = 0; ++ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); ++ if (err) ++ netdev_err(dev, "failed to allocate rx irq\n"); ++ else ++ priv->rxch.dma.irq = priv->rx_irq; ++err_out: ++ return err; + } + + static void +@@ -309,7 +454,10 @@ ltq_etop_get_settings(struct net_device + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_ethtool_gset(priv->phydev, cmd); ++ if (priv->phydev) ++ return phy_ethtool_gset(priv->phydev, cmd); ++ else ++ return 0; + } + + static int +@@ -317,7 +465,10 @@ ltq_etop_set_settings(struct net_device + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_ethtool_sset(priv->phydev, cmd); ++ if (priv->phydev) ++ return phy_ethtool_sset(priv->phydev, cmd); ++ else ++ return 0; + } + + static int +@@ -325,7 +476,10 @@ ltq_etop_nway_reset(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_start_aneg(priv->phydev); ++ if (priv->phydev) ++ return phy_start_aneg(priv->phydev); ++ else ++ return 0; + } + + static const struct ethtool_ops ltq_etop_ethtool_ops = { +@@ -336,6 +490,39 @@ static const struct ethtool_ops ltq_etop + }; + + static int ++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | ++ (phy_data << MDIO_XR9_WR_OFFSET) | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ return 0; ++} ++ ++static int ++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; ++ return val; ++} ++ ++static int + ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) + { + u32 val = MDIO_REQUEST | +@@ -343,9 +530,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | + phy_data; + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); + return 0; + } + +@@ -356,12 +543,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in + ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | + ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); + +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- ltq_etop_w32(val, LTQ_ETOP_MDIO); +- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) ++ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); ++ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) + ; +- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; ++ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; + return val; + } + +@@ -376,14 +563,18 @@ ltq_etop_mdio_probe(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; +- int phy_addr; ++ u32 phy_supported = (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_Autoneg ++ | SUPPORTED_MII ++ | SUPPORTED_TP); + +- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { +- if (priv->mii_bus->phy_map[phy_addr]) { +- phydev = priv->mii_bus->phy_map[phy_addr]; +- break; +- } +- } ++ if (of_machine_is_compatible("lantiq,ase")) ++ phydev = priv->mii_bus->phy_map[8]; ++ else ++ phydev = priv->mii_bus->phy_map[0]; + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); +@@ -391,21 +582,18 @@ ltq_etop_mdio_probe(struct net_device *d + } + + phydev = phy_connect(dev, dev_name(&phydev->dev), +- <q_etop_mdio_link, priv->pldata->mii_mode); ++ <q_etop_mdio_link, priv->mii_mode); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + +- phydev->supported &= (SUPPORTED_10baseT_Half +- | SUPPORTED_10baseT_Full +- | SUPPORTED_100baseT_Half +- | SUPPORTED_100baseT_Full +- | SUPPORTED_Autoneg +- | SUPPORTED_MII +- | SUPPORTED_TP); ++ if (of_machine_is_compatible("lantiq,ar9")) ++ phy_supported |= SUPPORTED_1000baseT_Half ++ | SUPPORTED_1000baseT_Full; + ++ phydev->supported &= phy_supported; + phydev->advertising = phydev->supported; + priv->phydev = phydev; + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", +@@ -430,8 +618,13 @@ ltq_etop_mdio_init(struct net_device *de + } + + priv->mii_bus->priv = dev; +- priv->mii_bus->read = ltq_etop_mdio_rd; +- priv->mii_bus->write = ltq_etop_mdio_wr; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; ++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; ++ } else { ++ priv->mii_bus->read = ltq_etop_mdio_rd; ++ priv->mii_bus->write = ltq_etop_mdio_wr; ++ } + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +@@ -480,17 +673,19 @@ static int + ltq_etop_open(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; ++ napi_enable(&priv->txch.napi); ++ napi_enable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_open(&priv->txch.dma); ++ ltq_dma_open(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (priv->phydev) ++ phy_start(priv->phydev); + +- if (!IS_TX(i) && (!IS_RX(i))) +- continue; +- ltq_dma_open(&ch->dma); +- napi_enable(&ch->napi); +- } +- phy_start(priv->phydev); + netif_tx_start_all_queues(dev); + return 0; + } +@@ -499,18 +694,19 @@ static int + ltq_etop_stop(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + + netif_tx_stop_all_queues(dev); +- phy_stop(priv->phydev); +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- if (!IS_RX(i) && !IS_TX(i)) +- continue; +- napi_disable(&ch->napi); +- ltq_dma_close(&ch->dma); +- } ++ if (priv->phydev) ++ phy_stop(priv->phydev); ++ napi_disable(&priv->txch.napi); ++ napi_disable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_close(&priv->txch.dma); ++ ltq_dma_close(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ + return 0; + } + +@@ -520,16 +716,16 @@ ltq_etop_tx(struct sk_buff *skb, struct + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); +- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; +- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- int len; ++ struct ltq_dma_desc *desc = ++ &priv->txch.dma.desc_base[priv->txch.dma.desc]; + unsigned long flags; + u32 byte_offset; ++ int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + +- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { +- dev_kfree_skb_any(skb); ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ++ priv->txch.skb[priv->txch.dma.desc]) { + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; +@@ -537,7 +733,7 @@ ltq_etop_tx(struct sk_buff *skb, struct + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; +- ch->skb[ch->dma.desc] = skb; ++ priv->txch.skb[priv->txch.dma.desc] = skb; + + dev->trans_start = jiffies; + +@@ -547,11 +743,11 @@ ltq_etop_tx(struct sk_buff *skb, struct + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); +- ch->dma.desc++; +- ch->dma.desc %= LTQ_DESC_NUM; ++ priv->txch.dma.desc++; ++ priv->txch.dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + +- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +@@ -566,8 +762,10 @@ ltq_etop_change_mtu(struct net_device *d + struct ltq_etop_priv *priv = netdev_priv(dev); + unsigned long flags; + ++ int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; ++ + spin_lock_irqsave(&priv->lock, flags); +- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, ++ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, + LTQ_ETOP_IGPLEN); + spin_unlock_irqrestore(&priv->lock, flags); + } +@@ -638,6 +836,9 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + if (!is_valid_ether_addr(mac.sa_data)) { +@@ -655,9 +856,10 @@ ltq_etop_init(struct net_device *dev) + dev->addr_assign_type = NET_ADDR_RANDOM; + + ltq_etop_set_multicast_list(dev); +- err = ltq_etop_mdio_init(dev); +- if (err) +- goto err_netdev; ++ if (!ltq_etop_mdio_init(dev)) ++ dev->ethtool_ops = <q_etop_ethtool_ops; ++ else ++ pr_warn("etop: mdio probe failed\n");; + return 0; + + err_netdev: +@@ -677,6 +879,9 @@ ltq_etop_tx_timeout(struct net_device *d + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + dev->trans_start = jiffies; + netif_wake_queue(dev); + return; +@@ -700,14 +905,18 @@ static const struct net_device_ops ltq_e + .ndo_tx_timeout = ltq_etop_tx_timeout, + }; + +-static int __init +-ltq_etop_probe(struct platform_device *pdev) ++static int ltq_etop_probe(struct platform_device *pdev) + { + struct net_device *dev; + struct ltq_etop_priv *priv; +- struct resource *res; ++ struct resource *res, *gbit_res, irqres[2]; + int err; +- int i; ++ ++ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); ++ if (err != 2) { ++ dev_err(&pdev->dev, "failed to get etop irqs\n"); ++ return -EINVAL; ++ } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -733,30 +942,58 @@ ltq_etop_probe(struct platform_device *p + goto err_out; + } + +- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); +- if (!dev) { +- err = -ENOMEM; +- goto err_out; ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!gbit_res) { ++ dev_err(&pdev->dev, "failed to get gbit resource\n"); ++ err = -ENOENT; ++ goto err_out; ++ } ++ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, ++ gbit_res->start, resource_size(gbit_res)); ++ if (!ltq_gbit_membase) { ++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", ++ pdev->id); ++ err = -ENOMEM; ++ goto err_out; ++ } + } ++ ++ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; +- dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pdev = pdev; +- priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; ++ priv->tx_irq = irqres[0].start; ++ priv->rx_irq = irqres[1].start; ++ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node); ++ of_get_mac_address_mtd(pdev->dev.of_node, priv->mac); ++ ++ priv->clk_ppe = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_ppe)) ++ return PTR_ERR(priv->clk_ppe); ++ if (of_machine_is_compatible("lantiq,ar9")) { ++ priv->clk_switch = clk_get(&pdev->dev, "switch"); ++ if (IS_ERR(priv->clk_switch)) ++ return PTR_ERR(priv->clk_switch); ++ } ++ if (of_machine_is_compatible("lantiq,ase")) { ++ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); ++ if (IS_ERR(priv->clk_ephy)) ++ return PTR_ERR(priv->clk_ephy); ++ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); ++ if (IS_ERR(priv->clk_ephycgu)) ++ return PTR_ERR(priv->clk_ephycgu); ++ } ++ + spin_lock_init(&priv->lock); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- if (IS_TX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_tx, 8); +- else if (IS_RX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_rx, 32); +- priv->ch[i].netdev = dev; +- } ++ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); ++ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); ++ priv->txch.netdev = dev; ++ priv->rxch.netdev = dev; + + err = register_netdev(dev); + if (err) +@@ -785,31 +1022,22 @@ ltq_etop_remove(struct platform_device * + return 0; + } + ++static const struct of_device_id ltq_etop_match[] = { ++ { .compatible = "lantiq,etop-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_etop_match); ++ + static struct platform_driver ltq_mii_driver = { ++ .probe = ltq_etop_probe, + .remove = ltq_etop_remove, + .driver = { + .name = "ltq_etop", ++ .of_match_table = ltq_etop_match, + }, + }; + +-int __init +-init_ltq_etop(void) +-{ +- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); +- +- if (ret) +- pr_err("ltq_etop: Error registering platform driver!"); +- return ret; +-} +- +-static void __exit +-exit_ltq_etop(void) +-{ +- platform_driver_unregister(<q_mii_driver); +-} +- +-module_init(init_ltq_etop); +-module_exit(exit_ltq_etop); ++module_platform_driver(ltq_mii_driver); + + MODULE_AUTHOR("John Crispin "); + MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-4.1/0030-GPIO-add-named-gpio-exports.patch b/target/linux/lantiq/patches-4.1/0030-GPIO-add-named-gpio-exports.patch new file mode 100644 index 0000000..6badfe3 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0030-GPIO-add-named-gpio-exports.patch @@ -0,0 +1,166 @@ +From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 12 Aug 2014 20:49:27 +0200 +Subject: [PATCH 30/36] GPIO: add named gpio exports + +Signed-off-by: John Crispin +--- + drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++ + drivers/gpio/gpiolib.c | 11 +++++-- + include/asm-generic/gpio.h | 5 +++ + include/linux/gpio/consumer.h | 8 +++++ + 4 files changed, 90 insertions(+), 2 deletions(-) + +--- a/drivers/gpio/gpiolib-of.c ++++ b/drivers/gpio/gpiolib-of.c +@@ -23,6 +23,8 @@ + #include + #include + #include ++#include ++#include + + #include "gpiolib.h" + +@@ -444,3 +446,69 @@ void of_gpiochip_remove(struct gpio_chip + gpiochip_remove_pin_ranges(chip); + of_node_put(chip->of_node); + } ++ ++static struct of_device_id gpio_export_ids[] = { ++ { .compatible = "gpio-export" }, ++ { /* sentinel */ } ++}; ++ ++static int __init of_gpio_export_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct device_node *cnp; ++ u32 val; ++ int nb = 0; ++ ++ for_each_child_of_node(np, cnp) { ++ const char *name = NULL; ++ int gpio; ++ bool dmc; ++ int max_gpio = 1; ++ int i; ++ ++ of_property_read_string(cnp, "gpio-export,name", &name); ++ ++ if (!name) ++ max_gpio = of_gpio_count(cnp); ++ ++ for (i = 0; i < max_gpio; i++) { ++ unsigned flags = 0; ++ enum of_gpio_flags of_flags; ++ ++ gpio = of_get_gpio_flags(cnp, i, &of_flags); ++ ++ if (of_flags == OF_GPIO_ACTIVE_LOW) ++ flags |= GPIOF_ACTIVE_LOW; ++ ++ if (!of_property_read_u32(cnp, "gpio-export,output", &val)) ++ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; ++ else ++ flags |= GPIOF_IN; ++ ++ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np))) ++ continue; ++ ++ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change"); ++ gpio_export_with_name(gpio, dmc, name); ++ nb++; ++ } ++ } ++ ++ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb); ++ ++ return 0; ++} ++ ++static struct platform_driver gpio_export_driver = { ++ .driver = { ++ .name = "gpio-export", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(gpio_export_ids), ++ }, ++}; ++ ++static int __init of_gpio_export_init(void) ++{ ++ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe); ++} ++device_initcall(of_gpio_export_init); +--- a/include/asm-generic/gpio.h ++++ b/include/asm-generic/gpio.h +@@ -122,6 +122,12 @@ static inline int gpio_export(unsigned g + return gpiod_export(gpio_to_desc(gpio), direction_may_change); + } + ++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); ++static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name) ++{ ++ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name); ++} ++ + static inline int gpio_export_link(struct device *dev, const char *name, + unsigned gpio) + { +--- a/include/linux/gpio/consumer.h ++++ b/include/linux/gpio/consumer.h +@@ -461,6 +461,7 @@ static inline struct gpio_desc *devm_get + + #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) + ++int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); + int gpiod_export(struct gpio_desc *desc, bool direction_may_change); + int gpiod_export_link(struct device *dev, const char *name, + struct gpio_desc *desc); +@@ -469,6 +470,13 @@ void gpiod_unexport(struct gpio_desc *de + + #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ + ++static inline int _gpiod_export(struct gpio_desc *desc, ++ bool direction_may_change, ++ const char *name) ++{ ++ return -ENOSYS; ++} ++ + static inline int gpiod_export(struct gpio_desc *desc, + bool direction_may_change) + { +--- a/drivers/gpio/gpiolib-sysfs.c ++++ b/drivers/gpio/gpiolib-sysfs.c +@@ -549,7 +549,7 @@ static struct class gpio_class = { + * + * Returns zero on success, else an error. + */ +-int gpiod_export(struct gpio_desc *desc, bool direction_may_change) ++int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) + { + struct gpio_chip *chip; + unsigned long flags; +@@ -601,6 +601,8 @@ int gpiod_export(struct gpio_desc *desc, + offset = gpio_chip_hwgpio(desc); + if (desc->chip->names && desc->chip->names[offset]) + ioname = desc->chip->names[offset]; ++ if (name) ++ ioname = name; + + dev = device_create_with_groups(&gpio_class, desc->chip->dev, + MKDEV(0, 0), desc, gpio_groups, +@@ -620,6 +622,12 @@ fail_unlock: + gpiod_dbg(desc, "%s: status %d\n", __func__, status); + return status; + } ++EXPORT_SYMBOL_GPL(__gpiod_export); ++ ++int gpiod_export(struct gpio_desc *desc, bool direction_may_change) ++{ ++ return __gpiod_export(desc, direction_may_change, NULL); ++} + EXPORT_SYMBOL_GPL(gpiod_export); + + static int match_export(struct device *dev, const void *data) diff --git a/target/linux/lantiq/patches-4.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-4.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch new file mode 100644 index 0000000..0fe9f04 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch @@ -0,0 +1,1034 @@ +From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:26:42 +0200 +Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master + +This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. + +Signed-off-by: Thomas Langer +Signed-off-by: John Crispin +--- + drivers/i2c/busses/Kconfig | 10 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ + drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ + 4 files changed, 992 insertions(+) + create mode 100644 drivers/i2c/busses/i2c-lantiq.c + create mode 100644 drivers/i2c/busses/i2c-lantiq.h + +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -609,6 +609,16 @@ config I2C_MESON + If you say yes to this option, support will be included for the + I2C interface on the Amlogic Meson family of SoCs. + ++config I2C_LANTIQ ++ tristate "Lantiq I2C interface" ++ depends on LANTIQ && SOC_FALCON ++ help ++ If you say yes to this option, support will be included for the ++ Lantiq I2C core. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-lantiq. ++ + config I2C_MPC + tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" + depends on PPC +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -58,6 +58,7 @@ obj-$(CONFIG_I2C_IMX) += i2c-imx.o + obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o + obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o + obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o ++obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o + obj-$(CONFIG_I2C_MESON) += i2c-meson.o + obj-$(CONFIG_I2C_MPC) += i2c-mpc.o + obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.c +@@ -0,0 +1,747 @@ ++ ++/* ++ * Lantiq I2C bus adapter ++ * ++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * Copyright (C) 2012 Thomas Langer ++ */ ++ ++#include ++#include ++#include ++#include /* for kzalloc, kfree */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "i2c-lantiq.h" ++ ++/* ++ * CURRENT ISSUES: ++ * - no high speed support ++ * - ten bit mode is not tested (no slave devices) ++ */ ++ ++/* access macros */ ++#define i2c_r32(reg) \ ++ __raw_readl(&(priv->membase)->reg) ++#define i2c_w32(val, reg) \ ++ __raw_writel(val, &(priv->membase)->reg) ++#define i2c_w32_mask(clear, set, reg) \ ++ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) ++ ++#define DRV_NAME "i2c-lantiq" ++#define DRV_VERSION "1.00" ++ ++#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ ++ ++#ifdef DEBUG ++#define LTQ_I2C_XFER_TIMEOUT (25*HZ) ++#else ++#define LTQ_I2C_XFER_TIMEOUT HZ ++#endif ++ ++#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ ++ I2C_IMSC_I2C_ERR_INT_EN) ++ ++#define LTQ_I2C_ARB_LOST (1 << 0) ++#define LTQ_I2C_NACK (1 << 1) ++#define LTQ_I2C_RX_UFL (1 << 2) ++#define LTQ_I2C_RX_OFL (1 << 3) ++#define LTQ_I2C_TX_UFL (1 << 4) ++#define LTQ_I2C_TX_OFL (1 << 5) ++ ++struct ltq_i2c { ++ struct mutex mutex; ++ ++ ++ /* active clock settings */ ++ unsigned int input_clock; /* clock input for i2c hardware block */ ++ unsigned int i2c_clock; /* approximated bus clock in kHz */ ++ ++ struct clk *clk_gate; ++ struct clk *clk_input; ++ ++ ++ /* resources (memory and interrupts) */ ++ int irq_lb; /* last burst irq */ ++ ++ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ ++ ++ struct i2c_adapter adap; ++ struct device *dev; ++ ++ struct completion cmd_complete; ++ ++ ++ /* message transfer data */ ++ struct i2c_msg *current_msg; /* current message */ ++ int msgs_num; /* number of messages to handle */ ++ u8 *msg_buf; /* current buffer */ ++ u32 msg_buf_len; /* remaining length of current buffer */ ++ int msg_err; /* error status of the current transfer */ ++ ++ ++ /* master status codes */ ++ enum { ++ STATUS_IDLE, ++ STATUS_ADDR, /* address phase */ ++ STATUS_WRITE, ++ STATUS_READ, ++ STATUS_READ_END, ++ STATUS_STOP ++ } status; ++}; ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); ++ ++static inline void enable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); ++} ++static inline void disable_burst_irq(struct ltq_i2c *priv) ++{ ++ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); ++} ++ ++static void prepare_msg_send_addr(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ ++ u16 addr = msg->addr; ++ ++ /* new i2c_msg */ ++ priv->msg_buf = msg->buf; ++ priv->msg_buf_len = msg->len; ++ if (rd) ++ priv->status = STATUS_READ; ++ else ++ priv->status = STATUS_WRITE; ++ ++ /* send slave address */ ++ if (msg->flags & I2C_M_TEN) { ++ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); ++ i2c_w32(addr & 0xff, txd); ++ } else { ++ i2c_w32((addr & 0x7f) << 1 | rd, txd); ++ } ++} ++ ++static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; ++ ++ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); ++ ++ priv->status = STATUS_ADDR; ++ ++ if (!(msg->flags & I2C_M_RD)) ++ len += msg->len; ++ else ++ /* set maximum received packet size (before rx int!) */ ++ i2c_w32(msg->len, mrps_ctrl); ++ i2c_w32(len, tps_ctrl); ++ enable_burst_irq(priv); ++} ++ ++static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ unsigned int input_clock = clk_get_rate(priv->clk_input); ++ u32 dec, inc = 1; ++ ++ /* clock changed? */ ++ if (priv->input_clock == input_clock) ++ return 0; ++ ++ /* ++ * this formula is only an approximation, found by the recommended ++ * values in the "I2C Architecture Specification 1.7.1" ++ */ ++ dec = input_clock / (priv->i2c_clock * 2); ++ if (dec <= 6) ++ return -ENXIO; ++ ++ i2c_w32(0, fdiv_high_cfg); ++ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | ++ (dec << I2C_FDIV_CFG_DEC_OFFSET), ++ fdiv_cfg); ++ ++ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", ++ input_clock, priv->i2c_clock, dec); ++ ++ priv->input_clock = input_clock; ++ return 0; ++} ++ ++static int ltq_i2c_hw_init(struct i2c_adapter *adap) ++{ ++ int ret = 0; ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++#ifndef DEBUG ++ /* set normal operation clock divider */ ++ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); ++#else ++ /* for debugging a higher divider value! */ ++ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); ++#endif ++ ++ /* setup clock */ ++ ret = ltq_i2c_hw_set_clock(adap); ++ if (ret != 0) { ++ dev_warn(priv->dev, "invalid clock settings\n"); ++ return ret; ++ } ++ ++ /* configure fifo */ ++ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ ++ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ ++ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ ++ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ ++ fifo_cfg); ++ ++ /* configure address */ ++ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in ++ the fifo */ ++ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ ++ I2C_ADDR_CFG_MnS_EN | /* we are master device */ ++ 0, /* our slave address (not used!) */ ++ addr_cfg); ++ ++ /* enable bus */ ++ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); ++ ++ return 0; ++} ++ ++static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); ++ ++ do { ++ u32 stat = i2c_r32(bus_stat); ++ ++ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(priv->dev, "timeout waiting for bus ready\n"); ++ return -ETIMEDOUT; ++} ++ ++static void ltq_i2c_tx(struct ltq_i2c *priv, int last) ++{ ++ if (priv->msg_buf_len && priv->msg_buf) { ++ i2c_w32(*priv->msg_buf, txd); ++ ++ if (--priv->msg_buf_len) ++ priv->msg_buf++; ++ else ++ priv->msg_buf = NULL; ++ } else { ++ last = 1; ++ } ++ ++ if (last) ++ disable_burst_irq(priv); ++} ++ ++static void ltq_i2c_rx(struct ltq_i2c *priv, int last) ++{ ++ u32 fifo_stat, timeout; ++ if (priv->msg_buf_len && priv->msg_buf) { ++ timeout = 5000000; ++ do { ++ fifo_stat = i2c_r32(ffs_stat); ++ } while (!fifo_stat && --timeout); ++ if (!timeout) { ++ last = 1; ++ pr_debug("\nrx timeout\n"); ++ goto err; ++ } ++ while (fifo_stat) { ++ *priv->msg_buf = i2c_r32(rxd); ++ if (--priv->msg_buf_len) { ++ priv->msg_buf++; ++ } else { ++ priv->msg_buf = NULL; ++ last = 1; ++ break; ++ } ++ /* ++ * do not read more than burst size, otherwise no "last ++ * burst" is generated and the transaction is blocked! ++ */ ++ fifo_stat = 0; ++ } ++ } else { ++ last = 1; ++ } ++err: ++ if (last) { ++ disable_burst_irq(priv); ++ ++ if (priv->status == STATUS_READ_END) { ++ /* ++ * do the STATUS_STOP and complete() here, as sometimes ++ * the tx_end is already seen before this is finished ++ */ ++ priv->status = STATUS_STOP; ++ complete(&priv->cmd_complete); ++ } else { ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++ priv->status = STATUS_READ_END; ++ } ++ } ++} ++ ++static void ltq_i2c_xfer_init(struct ltq_i2c *priv) ++{ ++ /* enable interrupts */ ++ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); ++ ++ /* trigger transfer of first msg */ ++ ltq_i2c_set_tx_len(priv); ++} ++ ++static void dump_msgs(struct i2c_msg msgs[], int num, int rx) ++{ ++#if defined(DEBUG) ++ int i, j; ++ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); ++ for (i = 0; i < num; i++) { ++ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, ++ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', ++ msgs[i].len, msgs[i].addr); ++ if (!(msgs[i].flags & I2C_M_RD) || rx) { ++ for (j = 0; j < msgs[i].len; j++) ++ pr_debug("%02X ", msgs[i].buf[j]); ++ } ++ pr_debug("\n"); ++ } ++#endif ++} ++ ++static void ltq_i2c_release_bus(struct ltq_i2c *priv) ++{ ++ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++} ++ ++static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], ++ int num) ++{ ++ struct ltq_i2c *priv = i2c_get_adapdata(adap); ++ int ret; ++ ++ dev_dbg(priv->dev, "xfer %u messages\n", num); ++ dump_msgs(msgs, num, 0); ++ ++ mutex_lock(&priv->mutex); ++ ++ init_completion(&priv->cmd_complete); ++ priv->current_msg = msgs; ++ priv->msgs_num = num; ++ priv->msg_err = 0; ++ priv->status = STATUS_IDLE; ++ ++ /* wait for the bus to become ready */ ++ ret = ltq_i2c_wait_bus_not_busy(priv); ++ if (ret) ++ goto done; ++ ++ while (priv->msgs_num) { ++ /* start the transfers */ ++ ltq_i2c_xfer_init(priv); ++ ++ /* wait for transfers to complete */ ++ ret = wait_for_completion_interruptible_timeout( ++ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); ++ if (ret == 0) { ++ dev_err(priv->dev, "controller timed out\n"); ++ ltq_i2c_hw_init(adap); ++ ret = -ETIMEDOUT; ++ goto done; ++ } else if (ret < 0) ++ goto done; ++ ++ if (priv->msg_err) { ++ if (priv->msg_err & LTQ_I2C_NACK) ++ ret = -ENXIO; ++ else ++ ret = -EREMOTEIO; ++ goto done; ++ } ++ if (--priv->msgs_num) ++ priv->current_msg++; ++ } ++ /* no error? */ ++ ret = num; ++ ++done: ++ ltq_i2c_release_bus(priv); ++ ++ mutex_unlock(&priv->mutex); ++ ++ if (ret >= 0) ++ dump_msgs(msgs, num, 1); ++ ++ pr_debug("XFER ret %d\n", ret); ++ return ret; ++} ++ ++static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) ++{ ++ struct ltq_i2c *priv = dev_id; ++ struct i2c_msg *msg = priv->current_msg; ++ int last = (irq == priv->irq_lb); ++ ++ if (last) ++ pr_debug("LB "); ++ else ++ pr_debug("B "); ++ ++ if (msg->flags & I2C_M_RD) { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("X"); ++ prepare_msg_send_addr(priv); ++ disable_burst_irq(priv); ++ break; ++ case STATUS_READ: ++ case STATUS_READ_END: ++ pr_debug("R"); ++ ltq_i2c_rx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status R %d\n", priv->status); ++ break; ++ } ++ } else { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ pr_debug("x"); ++ prepare_msg_send_addr(priv); ++ break; ++ case STATUS_WRITE: ++ pr_debug("w"); ++ ltq_i2c_tx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ pr_warn("Status W %d\n", priv->status); ++ break; ++ } ++ } ++ ++ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); ++ return IRQ_HANDLED; ++} ++ ++static void ltq_i2c_isr_prot(struct ltq_i2c *priv) ++{ ++ u32 i_pro = i2c_r32(p_irqss); ++ ++ pr_debug("i2c-p"); ++ ++ /* not acknowledge */ ++ if (i_pro & I2C_P_IRQSS_NACK) { ++ priv->msg_err |= LTQ_I2C_NACK; ++ pr_debug(" nack"); ++ } ++ ++ /* arbitration lost */ ++ if (i_pro & I2C_P_IRQSS_AL) { ++ priv->msg_err |= LTQ_I2C_ARB_LOST; ++ pr_debug(" arb-lost"); ++ } ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) ++ pr_debug(" rx"); ++ ++ /* tx end */ ++ if (i_pro & I2C_P_IRQSS_TX_END) ++ pr_debug(" txend"); ++ pr_debug("\n"); ++ ++ if (!priv->msg_err) { ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) { ++ priv->status = STATUS_READ; ++ enable_burst_irq(priv); ++ } ++ if (i_pro & I2C_P_IRQSS_TX_END) { ++ if (priv->status == STATUS_READ) ++ priv->status = STATUS_READ_END; ++ else { ++ disable_burst_irq(priv); ++ priv->status = STATUS_STOP; ++ } ++ } ++ } ++ ++ i2c_w32(i_pro, p_irqsc); ++} ++ ++static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) ++{ ++ u32 i_raw, i_err = 0; ++ struct ltq_i2c *priv = dev_id; ++ ++ i_raw = i2c_r32(mis); ++ pr_debug("i_raw 0x%08X\n", i_raw); ++ ++ /* error interrupt */ ++ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { ++ i_err = i2c_r32(err_irqss); ++ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", ++ i_err, i2c_r32(bus_stat)); ++ ++ /* tx fifo overflow (8) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_OFL) ++ priv->msg_err |= LTQ_I2C_TX_OFL; ++ ++ /* tx fifo underflow (4) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_UFL) ++ priv->msg_err |= LTQ_I2C_TX_UFL; ++ ++ /* rx fifo overflow (2) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_OFL) ++ priv->msg_err |= LTQ_I2C_RX_OFL; ++ ++ /* rx fifo underflow (1) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_UFL) ++ priv->msg_err |= LTQ_I2C_RX_UFL; ++ ++ i2c_w32(i_err, err_irqsc); ++ } ++ ++ /* protocol interrupt */ ++ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) ++ ltq_i2c_isr_prot(priv); ++ ++ if ((priv->msg_err) || (priv->status == STATUS_STOP)) ++ complete(&priv->cmd_complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 ltq_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | ++ I2C_FUNC_10BIT_ADDR | ++ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm ltq_i2c_algorithm = { ++ .master_xfer = ltq_i2c_xfer, ++ .functionality = ltq_i2c_functionality, ++}; ++ ++static int __devinit ltq_i2c_probe(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct ltq_i2c *priv; ++ struct i2c_adapter *adap; ++ struct resource *mmres, irqres[4]; ++ int ret = 0; ++ ++ dev_dbg(&pdev->dev, "probing\n"); ++ ++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ret = of_irq_to_resource_table(node, irqres, 4); ++ if (!mmres || (ret != 4)) { ++ dev_err(&pdev->dev, "no resources\n"); ++ return -ENODEV; ++ } ++ ++ /* allocate private data */ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(&pdev->dev, "can't allocate private data\n"); ++ return -ENOMEM; ++ } ++ ++ adap = &priv->adap; ++ i2c_set_adapdata(adap, priv); ++ adap->owner = THIS_MODULE; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); ++ adap->algo = <q_i2c_algorithm; ++ ++ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { ++ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); ++ priv->i2c_clock = 100000; ++ } ++ ++ init_completion(&priv->cmd_complete); ++ mutex_init(&priv->mutex); ++ ++ priv->membase = devm_request_and_ioremap(&pdev->dev, mmres); ++ if (priv->membase == NULL) ++ return -ENOMEM; ++ ++ priv->dev = &pdev->dev; ++ priv->irq_lb = irqres[0].start; ++ ++ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, ++ 0x0, "i2c lb", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", ++ irqres[0].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, ++ 0x0, "i2c b", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get burst IRQ %d\n", ++ irqres[1].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, ++ 0x0, "i2c err", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get error IRQ %d\n", ++ irqres[2].start); ++ return -ENODEV; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, ++ 0x0, "i2c p", priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", ++ irqres[3].start); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); ++ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, ++ irqres[1].start, irqres[2].start, irqres[3].start); ++ ++ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_gate)) { ++ dev_err(&pdev->dev, "failed to get i2c clk\n"); ++ return -ENOENT; ++ } ++ ++ /* this is a static clock, which has no refcounting */ ++ priv->clk_input = clk_get_fpi(); ++ if (IS_ERR(priv->clk_input)) { ++ dev_err(&pdev->dev, "failed to get fpi clk\n"); ++ return -ENOENT; ++ } ++ ++ clk_activate(priv->clk_gate); ++ ++ /* add our adapter to the i2c stack */ ++ ret = i2c_add_numbered_adapter(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't register I2C adapter\n"); ++ goto out; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ i2c_set_adapdata(adap, priv); ++ ++ /* print module version information */ ++ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", ++ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, ++ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); ++ ++ /* initialize HW */ ++ ret = ltq_i2c_hw_init(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't configure adapter\n"); ++ i2c_del_adapter(adap); ++ platform_set_drvdata(pdev, NULL); ++ } else { ++ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); ++ } ++ ++ of_i2c_register_devices(adap); ++ ++out: ++ /* if init failed, we need to deactivate the clock gate */ ++ if (ret) ++ clk_deactivate(priv->clk_gate); ++ ++ return ret; ++} ++ ++static int __devexit ltq_i2c_remove(struct platform_device *pdev) ++{ ++ struct ltq_i2c *priv = platform_get_drvdata(pdev); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++ /* power down the core */ ++ clk_deactivate(priv->clk_gate); ++ ++ /* remove driver */ ++ i2c_del_adapter(&priv->adap); ++ kfree(priv); ++ ++ dev_dbg(&pdev->dev, "removed\n"); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++static const struct of_device_id ltq_i2c_match[] = { ++ { .compatible = "lantiq,lantiq-i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_i2c_match); ++ ++static struct platform_driver ltq_i2c_driver = { ++ .probe = ltq_i2c_probe, ++ .remove = __devexit_p(ltq_i2c_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = ltq_i2c_match, ++ }, ++}; ++ ++module_platform_driver(ltq_i2c_driver); ++ ++MODULE_DESCRIPTION("Lantiq I2C bus adapter"); ++MODULE_AUTHOR("Thomas Langer "); ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); +--- /dev/null ++++ b/drivers/i2c/busses/i2c-lantiq.h +@@ -0,0 +1,234 @@ ++#ifndef I2C_LANTIQ_H ++#define I2C_LANTIQ_H ++ ++/* I2C register structure */ ++struct lantiq_reg_i2c { ++ /* I2C Kernel Clock Control Register */ ++ unsigned int clc; /* 0x00000000 */ ++ /* Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /* I2C Identification Register */ ++ unsigned int id; /* 0x00000008 */ ++ /* Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /* ++ * I2C RUN Control Register ++ * This register enables and disables the I2C peripheral. Before ++ * enabling, the I2C has to be configured properly. After enabling ++ * no configuration is possible ++ */ ++ unsigned int run_ctrl; /* 0x00000010 */ ++ /* ++ * I2C End Data Control Register ++ * This register is used to either turn around the data transmission ++ * direction or to address another slave without sending a stop ++ * condition. Also the software can stop the slave-transmitter by ++ * sending a not-accolade when working as master-receiver or even ++ * stop data transmission immediately when operating as ++ * master-transmitter. The writing to the bits of this control ++ * register is only effective when in MASTER RECEIVES BYTES, MASTER ++ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state ++ */ ++ unsigned int endd_ctrl; /* 0x00000014 */ ++ /* ++ * I2C Fractional Divider Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_HIGH_CFG has ++ * the same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_cfg; /* 0x00000018 */ ++ /* ++ * I2C Fractional Divider (highspeed mode) Configuration Register ++ * These register is used to program the fractional divider of the I2C ++ * bus. Before the peripheral is switched on by setting the RUN-bit the ++ * two (fixed) values for the two operating frequencies are programmed ++ * into these (configuration) registers. The Register FDIV_CFG has the ++ * same layout as I2C_FDIV_CFG. ++ */ ++ unsigned int fdiv_high_cfg; /* 0x0000001C */ ++ /* I2C Address Configuration Register */ ++ unsigned int addr_cfg; /* 0x00000020 */ ++ /* I2C Bus Status Register ++ * This register gives a status information of the I2C. This additional ++ * information can be used by the software to start proper actions. ++ */ ++ unsigned int bus_stat; /* 0x00000024 */ ++ /* I2C FIFO Configuration Register */ ++ unsigned int fifo_cfg; /* 0x00000028 */ ++ /* I2C Maximum Received Packet Size Register */ ++ unsigned int mrps_ctrl; /* 0x0000002C */ ++ /* I2C Received Packet Size Status Register */ ++ unsigned int rps_stat; /* 0x00000030 */ ++ /* I2C Transmit Packet Size Register */ ++ unsigned int tps_ctrl; /* 0x00000034 */ ++ /* I2C Filled FIFO Stages Status Register */ ++ unsigned int ffs_stat; /* 0x00000038 */ ++ /* Reserved */ ++ unsigned int res_2; /* 0x0000003C */ ++ /* I2C Timing Configuration Register */ ++ unsigned int tim_cfg; /* 0x00000040 */ ++ /* Reserved */ ++ unsigned int res_3[7]; /* 0x00000044 */ ++ /* I2C Error Interrupt Request Source Mask Register */ ++ unsigned int err_irqsm; /* 0x00000060 */ ++ /* I2C Error Interrupt Request Source Status Register */ ++ unsigned int err_irqss; /* 0x00000064 */ ++ /* I2C Error Interrupt Request Source Clear Register */ ++ unsigned int err_irqsc; /* 0x00000068 */ ++ /* Reserved */ ++ unsigned int res_4; /* 0x0000006C */ ++ /* I2C Protocol Interrupt Request Source Mask Register */ ++ unsigned int p_irqsm; /* 0x00000070 */ ++ /* I2C Protocol Interrupt Request Source Status Register */ ++ unsigned int p_irqss; /* 0x00000074 */ ++ /* I2C Protocol Interrupt Request Source Clear Register */ ++ unsigned int p_irqsc; /* 0x00000078 */ ++ /* Reserved */ ++ unsigned int res_5; /* 0x0000007C */ ++ /* I2C Raw Interrupt Status Register */ ++ unsigned int ris; /* 0x00000080 */ ++ /* I2C Interrupt Mask Control Register */ ++ unsigned int imsc; /* 0x00000084 */ ++ /* I2C Masked Interrupt Status Register */ ++ unsigned int mis; /* 0x00000088 */ ++ /* I2C Interrupt Clear Register */ ++ unsigned int icr; /* 0x0000008C */ ++ /* I2C Interrupt Set Register */ ++ unsigned int isr; /* 0x00000090 */ ++ /* I2C DMA Enable Register */ ++ unsigned int dmae; /* 0x00000094 */ ++ /* Reserved */ ++ unsigned int res_6[8154]; /* 0x00000098 */ ++ /* I2C Transmit Data Register */ ++ unsigned int txd; /* 0x00008000 */ ++ /* Reserved */ ++ unsigned int res_7[4095]; /* 0x00008004 */ ++ /* I2C Receive Data Register */ ++ unsigned int rxd; /* 0x0000C000 */ ++ /* Reserved */ ++ unsigned int res_8[4095]; /* 0x0000C004 */ ++}; ++ ++/* ++ * Clock Divider for Normal Run Mode ++ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long ++ * as the new divider value RMC is not valid, the register returns 0x0000 00xx ++ * on reading. ++ */ ++#define I2C_CLC_RMC_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_CLC_RMC_OFFSET 8 ++ ++/* Fields of "I2C Identification Register" */ ++/* Module ID */ ++#define I2C_ID_ID_MASK 0x0000FF00 ++/* field offset */ ++#define I2C_ID_ID_OFFSET 8 ++/* Revision */ ++#define I2C_ID_REV_MASK 0x000000FF ++/* field offset */ ++#define I2C_ID_REV_OFFSET 0 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_BREQ_INT_EN 0x00000008 ++/* Enable */ ++#define I2C_IMSC_LBREQ_INT_EN 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_INC_OFFSET 16 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/* Enable */ ++#define I2C_IMSC_I2C_P_INT_EN 0x00000020 ++/* Enable */ ++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 ++ ++/* Fields of "I2C Error Interrupt Request Source Status Register" */ ++/* TXF_OFL */ ++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 ++/* TXF_UFL */ ++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 ++/* RXF_OFL */ ++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 ++/* RXF_UFL */ ++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 ++ ++/* Fields of "I2C Raw Interrupt Status Register" */ ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 ++/* Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* TX FIFO Flow Control */ ++#define I2C_FIFO_CFG_TXFC 0x00020000 ++/* RX FIFO Flow Control */ ++#define I2C_FIFO_CFG_RXFC 0x00010000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 ++/* Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 ++/* 1 word */ ++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/* 1 word */ ++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 ++/* Stop on Packet End Enable */ ++#define I2C_ADDR_CFG_SOPE_EN 0x00200000 ++/* Stop on Not Acknowledge Enable */ ++#define I2C_ADDR_CFG_SONA_EN 0x00100000 ++/* Enable */ ++#define I2C_ADDR_CFG_MnS_EN 0x00080000 ++ ++/* Fields of "I2C Interrupt Clear Register" */ ++/* Clear */ ++#define I2C_ICR_BREQ_INT_CLR 0x00000008 ++/* Clear */ ++#define I2C_ICR_LBREQ_INT_CLR 0x00000004 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/* field offset */ ++#define I2C_FDIV_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Bus Status Register" */ ++/* Bus Status */ ++#define I2C_BUS_STAT_BS_MASK 0x00000003 ++/* Read from I2C Bus. */ ++#define I2C_BUS_STAT_RNW_READ 0x00000004 ++/* I2C Bus is free. */ ++#define I2C_BUS_STAT_BS_FREE 0x00000000 ++/* ++ * The device is working as master and has claimed the control on the ++ * I2C-bus (busy master). ++ */ ++#define I2C_BUS_STAT_BS_BM 0x00000002 ++ ++/* Fields of "I2C RUN Control Register" */ ++/* Enable */ ++#define I2C_RUN_CTRL_RUN_EN 0x00000001 ++ ++/* Fields of "I2C End Data Control Register" */ ++/* ++ * Set End of Transmission ++ * Note:Do not write '1' to this bit when bus is free. This will cause an ++ * abort after the first byte when a new transfer is started. ++ */ ++#define I2C_ENDD_CTRL_SETEND 0x00000002 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ ++/* NACK */ ++#define I2C_P_IRQSS_NACK 0x00000010 ++/* AL */ ++#define I2C_P_IRQSS_AL 0x00000008 ++/* RX */ ++#define I2C_P_IRQSS_RX 0x00000040 ++/* TX_END */ ++#define I2C_P_IRQSS_TX_END 0x00000020 ++ ++ ++#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-4.1/0032-USB-fix-roothub-for-IFXHCD.patch b/target/linux/lantiq/patches-4.1/0032-USB-fix-roothub-for-IFXHCD.patch new file mode 100644 index 0000000..79c8117 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0032-USB-fix-roothub-for-IFXHCD.patch @@ -0,0 +1,31 @@ +From 326714a47233e4a524afa0c8398276fddf0dbd4d Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 6 Dec 2012 19:59:53 +0100 +Subject: [PATCH 32/36] USB: fix roothub for IFXHCD + +--- + arch/mips/lantiq/Kconfig | 1 + + drivers/usb/core/hub.c | 2 +- + 2 files changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -3,6 +3,7 @@ if LANTIQ + config SOC_TYPE_XWAY + bool + select PINCTRL_XWAY ++ select USB_ARCH_HAS_HCD + default n + + choice +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -4298,7 +4298,7 @@ hub_port_init (struct usb_hub *hub, stru + udev->ttport = hdev->ttport; + } else if (udev->speed != USB_SPEED_HIGH + && hdev->speed == USB_SPEED_HIGH) { +- if (!hub->tt.hub) { ++ if (hdev->parent && !hub->tt.hub) { + dev_err(&udev->dev, "parent hub has no TT\n"); + retval = -EINVAL; + goto fail; diff --git a/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch b/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch new file mode 100644 index 0000000..7806f64 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch @@ -0,0 +1,1036 @@ +From e75df4f96373e5d16f8ca13aa031e54cdcfeda62 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 13 Mar 2013 09:29:37 +0100 +Subject: [PATCH 33/36] SPI: MIPS: lantiq: adds spi-xway + +This patch adds support for the SPI core found on several Lantiq SoCs. +The Driver has been runtime tested in combination with m25p80 Flash Devices +on Amazon_SE and VR9. + +Signed-off-by: Daniel Schwierzeck +Signed-off-by: John Crispin +--- + drivers/spi/Kconfig | 8 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-xway.c | 977 ++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 986 insertions(+) + create mode 100644 drivers/spi/spi-xway.c + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -626,6 +626,14 @@ config SPI_NUC900 + help + SPI driver for Nuvoton NUC900 series ARM SoCs + ++config SPI_XWAY ++ tristate "Lantiq SPI controller" ++ depends on LANTIQ ++ select SPI_BITBANG ++ help ++ This driver supports the Lantiq SoC SPI controller in master ++ mode. ++ + # + # Add new SPI master controllers in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -90,3 +90,4 @@ obj-$(CONFIG_SPI_TXX9) += spi-txx9.o + obj-$(CONFIG_SPI_XCOMM) += spi-xcomm.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o + obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o ++obj-$(CONFIG_SPI_XWAY) += spi-xway.o +--- /dev/null ++++ b/drivers/spi/spi-xway.c +@@ -0,0 +1,991 @@ ++/* ++ * Lantiq SoC SPI controller ++ * ++ * Copyright (C) 2011 Daniel Schwierzeck ++ * Copyright (C) 2012 John Crispin ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define LTQ_SPI_CLC 0x00 /* Clock control */ ++#define LTQ_SPI_PISEL 0x04 /* Port input select */ ++#define LTQ_SPI_ID 0x08 /* Identification */ ++#define LTQ_SPI_CON 0x10 /* Control */ ++#define LTQ_SPI_STAT 0x14 /* Status */ ++#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */ ++#define LTQ_SPI_TB 0x20 /* Transmit buffer */ ++#define LTQ_SPI_RB 0x24 /* Receive buffer */ ++#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */ ++#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */ ++#define LTQ_SPI_FSTAT 0x38 /* FIFO status */ ++#define LTQ_SPI_BRT 0x40 /* Baudrate timer */ ++#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */ ++#define LTQ_SPI_SFCON 0x60 /* Serial frame control */ ++#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */ ++#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */ ++#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */ ++#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */ ++#define LTQ_SPI_RXREQ 0x80 /* Receive request */ ++#define LTQ_SPI_RXCNT 0x84 /* Receive count */ ++#define LTQ_SPI_DMACON 0xEC /* DMA control */ ++#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */ ++#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */ ++#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */ ++ ++#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */ ++#define LTQ_SPI_CLC_SMC_MASK 0xFF ++#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */ ++#define LTQ_SPI_CLC_RMC_MASK 0xFF ++#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ ++#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ ++ ++#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */ ++#define LTQ_SPI_ID_TXFS_MASK 0x3F ++#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */ ++#define LTQ_SPI_ID_RXFS_MASK 0x3F ++#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */ ++#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */ ++ ++#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */ ++#define LTQ_SPI_CON_BM_MASK 0x1F ++#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ ++#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ ++#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ ++#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ ++#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ ++#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ ++#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ ++#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ ++#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ ++#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ ++#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ ++#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ ++#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ ++#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ ++ ++#define LTQ_SPI_STAT_RXBV_MASK 0x7 ++#define LTQ_SPI_STAT_RXBV_SHIFT 28 ++#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ ++#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ ++#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ ++#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ ++#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ ++#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ ++#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ ++#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ ++ ++#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ ++#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ ++#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ ++#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ ++#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error ++ flag */ ++#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ ++#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ ++#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ ++#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ ++#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ ++#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ ++#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ ++#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ ++#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ ++#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ ++#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ ++#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50 ++ ++#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */ ++#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F ++#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ ++#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ ++ ++#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */ ++#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F ++#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ ++#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ ++ ++#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f ++#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0 ++#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f ++#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8 ++ ++#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8 ++#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0 ++ ++#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8 ++#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0 ++ ++#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */ ++#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */ ++ ++#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ ++#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ ++#define LTQ_SPI_IRNEN_T BIT(0) /* Transmit end interrupt request */ ++#define LTQ_SPI_IRNEN_R BIT(1) /* Receive end interrupt request */ ++#define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ ++#define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ ++#define LTQ_SPI_IRNEN_ALL 0xF ++ ++struct ltq_spi { ++ struct spi_bitbang bitbang; ++ struct completion done; ++ spinlock_t lock; ++ ++ struct device *dev; ++ void __iomem *base; ++ struct clk *fpiclk; ++ struct clk *spiclk; ++ ++ int status; ++ int irq[3]; ++ ++ const u8 *tx; ++ u8 *rx; ++ u32 tx_cnt; ++ u32 rx_cnt; ++ u32 len; ++ struct spi_transfer *curr_transfer; ++ ++ u32 (*get_tx) (struct ltq_spi *); ++ ++ u16 txfs; ++ u16 rxfs; ++ unsigned dma_support:1; ++ unsigned cfg_mode:1; ++ ++ u32 irnen_t; ++ u32 irnen_r; ++}; ++ ++static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} ++ ++static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg) ++{ ++ return ioread32be(hw->base + reg); ++} ++ ++static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg) ++{ ++ iowrite32be(val, hw->base + reg); ++} ++ ++static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg) ++{ ++ u32 val; ++ ++ val = ltq_spi_reg_read(hw, reg); ++ val |= bits; ++ ltq_spi_reg_write(hw, val, reg); ++} ++ ++static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg) ++{ ++ u32 val; ++ ++ val = ltq_spi_reg_read(hw, reg); ++ val &= ~bits; ++ ltq_spi_reg_write(hw, val, reg); ++} ++ ++static void ltq_spi_hw_enable(struct ltq_spi *hw) ++{ ++ u32 clc; ++ ++ /* Power-up module */ ++ clk_enable(hw->spiclk); ++ ++ /* ++ * Set clock divider for run mode to 1 to ++ * run at same frequency as FPI bus ++ */ ++ clc = (1 << LTQ_SPI_CLC_RMC_SHIFT); ++ ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC); ++} ++ ++static void ltq_spi_hw_disable(struct ltq_spi *hw) ++{ ++ /* Set clock divider to 0 and set module disable bit */ ++ ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC); ++ ++ /* Power-down module */ ++ clk_disable(hw->spiclk); ++} ++ ++static void ltq_spi_reset_fifos(struct ltq_spi *hw) ++{ ++ u32 val; ++ ++ /* ++ * Enable and flush FIFOs. Set interrupt trigger level to ++ * half of FIFO count implemented in hardware. ++ */ ++ if (hw->txfs > 1) { ++ val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1); ++ val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; ++ ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON); ++ } ++ ++ if (hw->rxfs > 1) { ++ val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1); ++ val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; ++ ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON); ++ } ++} ++ ++static inline int ltq_spi_wait_ready(struct ltq_spi *hw) ++{ ++ u32 stat; ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(200); ++ ++ do { ++ stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT); ++ if (!(stat & LTQ_SPI_STAT_BSY)) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat); ++ ++ return -ETIMEDOUT; ++} ++ ++static void ltq_spi_config_mode_set(struct ltq_spi *hw) ++{ ++ if (hw->cfg_mode) ++ return; ++ ++ /* ++ * Putting the SPI module in config mode is only safe if no ++ * transfer is in progress as indicated by busy flag STATE.BSY. ++ */ ++ if (ltq_spi_wait_ready(hw)) { ++ ltq_spi_reset_fifos(hw); ++ hw->status = -ETIMEDOUT; ++ } ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); ++ ++ hw->cfg_mode = 1; ++} ++ ++static void ltq_spi_run_mode_set(struct ltq_spi *hw) ++{ ++ if (!hw->cfg_mode) ++ return; ++ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); ++ ++ hw->cfg_mode = 0; ++} ++ ++static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw) ++{ ++ const u8 *tx = hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt++; ++ hw->tx++; ++ ++ return data; ++} ++ ++static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw) ++{ ++ const u16 *tx = (u16 *) hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt += 2; ++ hw->tx += 2; ++ ++ return data; ++} ++ ++static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw) ++{ ++ const u32 *tx = (u32 *) hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt += 4; ++ hw->tx += 4; ++ ++ return data; ++} ++ ++static void ltq_spi_bits_per_word_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 bm; ++ u8 bits_per_word = spi->bits_per_word; ++ ++ /* ++ * Use either default value of SPI device or value ++ * from current transfer. ++ */ ++ if (hw->curr_transfer && hw->curr_transfer->bits_per_word) ++ bits_per_word = hw->curr_transfer->bits_per_word; ++ ++ if (bits_per_word <= 8) ++ hw->get_tx = ltq_spi_tx_word_u8; ++ else if (bits_per_word <= 16) ++ hw->get_tx = ltq_spi_tx_word_u16; ++ else if (bits_per_word <= 32) ++ hw->get_tx = ltq_spi_tx_word_u32; ++ ++ /* CON.BM value = bits_per_word - 1 */ ++ bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT; ++ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK << ++ LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON); ++ ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_speed_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 br, max_speed_hz, spi_clk; ++ u32 speed_hz = spi->max_speed_hz; ++ ++ /* ++ * Use either default value of SPI device or value ++ * from current transfer. ++ */ ++ if (hw->curr_transfer && hw->curr_transfer->speed_hz) ++ speed_hz = hw->curr_transfer->speed_hz; ++ ++ /* ++ * SPI module clock is derived from FPI bus clock dependent on ++ * divider value in CLC.RMS which is always set to 1. ++ */ ++ spi_clk = clk_get_rate(hw->fpiclk); ++ ++ /* ++ * Maximum SPI clock frequency in master mode is half of ++ * SPI module clock frequency. Maximum reload value of ++ * baudrate generator BR is 2^16. ++ */ ++ max_speed_hz = spi_clk / 2; ++ if (speed_hz >= max_speed_hz) ++ br = 0; ++ else ++ br = (max_speed_hz / speed_hz) - 1; ++ ++ if (br > 0xFFFF) ++ br = 0xFFFF; ++ ++ ltq_spi_reg_write(hw, br, LTQ_SPI_BRT); ++} ++ ++static void ltq_spi_clockmode_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 con; ++ ++ con = ltq_spi_reg_read(hw, LTQ_SPI_CON); ++ ++ /* ++ * SPI mode mapping in CON register: ++ * Mode CPOL CPHA CON.PO CON.PH ++ * 0 0 0 0 1 ++ * 1 0 1 0 0 ++ * 2 1 0 1 1 ++ * 3 1 1 1 0 ++ */ ++ if (spi->mode & SPI_CPHA) ++ con &= ~LTQ_SPI_CON_PH; ++ else ++ con |= LTQ_SPI_CON_PH; ++ ++ if (spi->mode & SPI_CPOL) ++ con |= LTQ_SPI_CON_PO; ++ else ++ con &= ~LTQ_SPI_CON_PO; ++ ++ /* Set heading control */ ++ if (spi->mode & SPI_LSB_FIRST) ++ con &= ~LTQ_SPI_CON_HB; ++ else ++ con |= LTQ_SPI_CON_HB; ++ ++ ltq_spi_reg_write(hw, con, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t) ++{ ++ u32 con; ++ ++ con = ltq_spi_reg_read(hw, LTQ_SPI_CON); ++ ++ if (t) { ++ if (t->tx_buf && t->rx_buf) { ++ con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); ++ } else if (t->rx_buf) { ++ con &= ~LTQ_SPI_CON_RXOFF; ++ con |= LTQ_SPI_CON_TXOFF; ++ } else if (t->tx_buf) { ++ con &= ~LTQ_SPI_CON_TXOFF; ++ con |= LTQ_SPI_CON_RXOFF; ++ } ++ } else ++ con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); ++ ++ ltq_spi_reg_write(hw, con, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_internal_cs_activate(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 fgpo; ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT)); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++} ++ ++static void ltq_spi_internal_cs_deactivate(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 fgpo; ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++} ++ ++static void ltq_spi_chipselect(struct spi_device *spi, int cs) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ ++ if (ltq_spi_wait_ready(hw)) ++ dev_err(&spi->dev, "wait failed\n"); ++ ++ switch (cs) { ++ case BITBANG_CS_ACTIVE: ++ ltq_spi_bits_per_word_set(spi); ++ ltq_spi_speed_set(spi); ++ ltq_spi_clockmode_set(spi); ++ ltq_spi_run_mode_set(hw); ++ ltq_spi_internal_cs_activate(spi); ++ break; ++ ++ case BITBANG_CS_INACTIVE: ++ ltq_spi_internal_cs_deactivate(spi); ++ ltq_spi_config_mode_set(hw); ++ break; ++ } ++} ++ ++static int ltq_spi_setup_transfer(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u8 bits_per_word = spi->bits_per_word; ++ ++ hw->curr_transfer = t; ++ ++ if (t && t->bits_per_word) ++ bits_per_word = t->bits_per_word; ++ ++ if (bits_per_word > 32) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int ltq_spi_setup(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 gpocon, fgpo; ++ ++ /* Set default word length to 8 if not set */ ++ if (!spi->bits_per_word) ++ spi->bits_per_word = 8; ++ ++ if (spi->bits_per_word > 32) ++ return -EINVAL; ++ ++ /* ++ * Up to six GPIOs can be connected to the SPI module ++ * via GPIO alternate function to control the chip select lines. ++ */ ++ gpocon = (1 << (spi->chip_select + ++ LTQ_SPI_GPOCON_ISCSBN_SHIFT)); ++ ++ if (spi->mode & SPI_CS_HIGH) ++ gpocon |= (1 << spi->chip_select); ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); ++ ++ ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++ ++ return 0; ++} ++ ++static void ltq_spi_cleanup(struct spi_device *spi) ++{ ++ ++} ++ ++static void ltq_spi_txfifo_write(struct ltq_spi *hw) ++{ ++ u32 fstat, data; ++ u16 fifo_space; ++ ++ /* Determine how much FIFOs are free for TX data */ ++ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); ++ fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) & ++ LTQ_SPI_FSTAT_TXFFL_MASK); ++ ++ if (!fifo_space) ++ return; ++ ++ while (hw->tx_cnt < hw->len && fifo_space) { ++ data = hw->get_tx(hw); ++ ltq_spi_reg_write(hw, data, LTQ_SPI_TB); ++ fifo_space--; ++ } ++} ++ ++static void ltq_spi_rxfifo_read(struct ltq_spi *hw) ++{ ++ u32 fstat, data, *rx32; ++ u16 fifo_fill; ++ u8 rxbv, shift, *rx8; ++ ++ /* Determine how much FIFOs are filled with RX data */ ++ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); ++ fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT) ++ & LTQ_SPI_FSTAT_RXFFL_MASK); ++ ++ if (!fifo_fill) ++ return; ++ ++ /* ++ * The 32 bit FIFO is always used completely independent from the ++ * bits_per_word value. Thus four bytes have to be read at once ++ * per FIFO. ++ */ ++ rx32 = (u32 *) hw->rx; ++ while (hw->len - hw->rx_cnt >= 4 && fifo_fill) { ++ *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB); ++ hw->rx_cnt += 4; ++ hw->rx += 4; ++ fifo_fill--; ++ } ++ ++ /* ++ * If there are remaining bytes, read byte count from STAT.RXBV ++ * register and read the data byte-wise. ++ */ ++ while (fifo_fill && hw->rx_cnt < hw->len) { ++ rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >> ++ LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK; ++ data = ltq_spi_reg_read(hw, LTQ_SPI_RB); ++ ++ shift = (rxbv - 1) * 8; ++ rx8 = hw->rx; ++ ++ while (rxbv) { ++ *rx8++ = (data >> shift) & 0xFF; ++ rxbv--; ++ shift -= 8; ++ hw->rx_cnt++; ++ hw->rx++; ++ } ++ ++ fifo_fill--; ++ } ++} ++ ++static void ltq_spi_rxreq_set(struct ltq_spi *hw) ++{ ++ u32 rxreq, rxreq_max, rxtodo; ++ ++ rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK; ++ ++ /* ++ * In RX-only mode the serial clock is activated only after writing ++ * the expected amount of RX bytes into RXREQ register. ++ * To avoid receive overflows at high clocks it is better to request ++ * only the amount of bytes that fits into all FIFOs. This value ++ * depends on the FIFO size implemented in hardware. ++ */ ++ rxreq = hw->len - hw->rx_cnt; ++ rxreq_max = hw->rxfs << 2; ++ rxreq = min(rxreq_max, rxreq); ++ ++ if (!rxtodo && rxreq) ++ ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ); ++} ++ ++static inline void ltq_spi_complete(struct ltq_spi *hw) ++{ ++ complete(&hw->done); ++} ++ ++irqreturn_t ltq_spi_tx_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ int completed = 0; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ if (hw->tx_cnt < hw->len) ++ ltq_spi_txfifo_write(hw); ++ ++ if (hw->tx_cnt == hw->len) ++ completed = 1; ++ ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ if (completed) ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ltq_spi_rx_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ int completed = 0; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ if (hw->rx_cnt < hw->len) { ++ ltq_spi_rxfifo_read(hw); ++ ++ if (hw->tx && hw->tx_cnt < hw->len) ++ ltq_spi_txfifo_write(hw); ++ } ++ ++ if (hw->rx_cnt == hw->len) ++ completed = 1; ++ else if (!hw->tx) ++ ltq_spi_rxreq_set(hw); ++ ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ if (completed) ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ltq_spi_err_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ /* Disable all interrupts */ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); ++ ++ dev_err(hw->dev, "error %x\n", ltq_spi_reg_read(hw, LTQ_SPI_STAT)); ++ ++ /* Clear all error flags */ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); ++ ++ /* Flush FIFOs */ ++ ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); ++ ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); ++ ++ hw->status = -EIO; ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 irq_flags = 0; ++ ++ hw->tx = t->tx_buf; ++ hw->rx = t->rx_buf; ++ hw->len = t->len; ++ hw->tx_cnt = 0; ++ hw->rx_cnt = 0; ++ hw->status = 0; ++ init_completion(&hw->done); ++ ++ ltq_spi_xmit_set(hw, t); ++ ++ /* Enable error interrupts */ ++ ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); ++ ++ if (hw->tx) { ++ /* Initially fill TX FIFO with as much data as possible */ ++ ltq_spi_txfifo_write(hw); ++ irq_flags |= hw->irnen_t; ++ ++ /* Always enable RX interrupt in Full Duplex mode */ ++ if (hw->rx) ++ irq_flags |= hw->irnen_r; ++ } else if (hw->rx) { ++ /* Start RX clock */ ++ ltq_spi_rxreq_set(hw); ++ ++ /* Enable RX interrupt to receive data from RX FIFOs */ ++ irq_flags |= hw->irnen_r; ++ } ++ ++ /* Enable TX or RX interrupts */ ++ ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN); ++ wait_for_completion_interruptible(&hw->done); ++ ++ /* Disable all interrupts */ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); ++ ++ /* ++ * Return length of current transfer for bitbang utility code if ++ * no errors occured during transmission. ++ */ ++ if (!hw->status) ++ hw->status = hw->len; ++ ++ return hw->status; ++} ++ ++static const struct ltq_spi_irq_map { ++ char *name; ++ irq_handler_t handler; ++} ltq_spi_irqs[] = { ++ { "spi_rx", ltq_spi_rx_irq }, ++ { "spi_tx", ltq_spi_tx_irq }, ++ { "spi_err", ltq_spi_err_irq }, ++}; ++ ++static int ltq_spi_probe(struct platform_device *pdev) ++{ ++ struct resource irqres[3]; ++ struct spi_master *master; ++ struct resource *r; ++ struct ltq_spi *hw; ++ int ret, i; ++ u32 data, id; ++ ++ if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 3) != 3) { ++ dev_err(&pdev->dev, "IRQ settings missing in device tree\n"); ++ return -EINVAL; ++ } ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi)); ++ if (!master) { ++ dev_err(&pdev->dev, "spi_alloc_master\n"); ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ hw = spi_master_get_devdata(master); ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ dev_err(&pdev->dev, "platform_get_resource\n"); ++ ret = -ENOENT; ++ goto err_master; ++ } ++ ++ r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r), ++ pdev->name); ++ if (!r) { ++ dev_err(&pdev->dev, "failed to request memory region\n"); ++ ret = -ENXIO; ++ goto err_master; ++ } ++ ++ hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r)); ++ if (!hw->base) { ++ dev_err(&pdev->dev, "failed to remap memory region\n"); ++ ret = -ENXIO; ++ goto err_master; ++ } ++ ++ memset(hw->irq, 0, sizeof(hw->irq)); ++ for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) { ++ hw->irq[i] = irqres[i].start; ++ ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler, ++ 0, ltq_spi_irqs[i].name, hw); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to request %s irq (%d)\n", ++ ltq_spi_irqs[i].name, hw->irq[i]); ++ goto err_irq; ++ } ++ } ++ ++ hw->fpiclk = clk_get_fpi(); ++ if (IS_ERR(hw->fpiclk)) { ++ dev_err(&pdev->dev, "failed to get fpi clock\n"); ++ ret = PTR_ERR(hw->fpiclk); ++ goto err_clk; ++ } ++ ++ hw->spiclk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(hw->spiclk)) { ++ dev_err(&pdev->dev, "failed to get spi clock gate\n"); ++ ret = PTR_ERR(hw->spiclk); ++ goto err_clk; ++ } ++ ++ hw->bitbang.master = spi_master_get(master); ++ hw->bitbang.chipselect = ltq_spi_chipselect; ++ hw->bitbang.setup_transfer = ltq_spi_setup_transfer; ++ hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs; ++ ++ if (of_machine_is_compatible("lantiq,ase")) { ++ master->num_chipselect = 3; ++ ++ hw->irnen_t = LTQ_SPI_IRNEN_T_XWAY; ++ hw->irnen_r = LTQ_SPI_IRNEN_R_XWAY; ++ } else { ++ master->num_chipselect = 6; ++ ++ hw->irnen_t = LTQ_SPI_IRNEN_T; ++ hw->irnen_r = LTQ_SPI_IRNEN_R; ++ } ++ ++ master->bus_num = pdev->id; ++ master->setup = ltq_spi_setup; ++ master->cleanup = ltq_spi_cleanup; ++ master->dev.of_node = pdev->dev.of_node; ++ ++ hw->dev = &pdev->dev; ++ init_completion(&hw->done); ++ spin_lock_init(&hw->lock); ++ ++ ltq_spi_hw_enable(hw); ++ ++ /* Read module capabilities */ ++ id = ltq_spi_reg_read(hw, LTQ_SPI_ID); ++ hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; ++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK; ++ hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0; ++ ++ ltq_spi_config_mode_set(hw); ++ ++ /* Enable error checking, disable TX/RX, set idle value high */ ++ data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | ++ LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | ++ LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE; ++ ltq_spi_reg_write(hw, data, LTQ_SPI_CON); ++ ++ /* Enable master mode and clear error flags */ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS | ++ LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); ++ ++ /* Reset GPIO/CS registers */ ++ ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON); ++ ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO); ++ ++ /* Enable and flush FIFOs */ ++ ltq_spi_reset_fifos(hw); ++ ++ ret = spi_bitbang_start(&hw->bitbang); ++ if (ret) { ++ dev_err(&pdev->dev, "spi_bitbang_start failed\n"); ++ goto err_bitbang; ++ } ++ ++ platform_set_drvdata(pdev, hw); ++ ++ pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n", ++ id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support); ++ ++ return 0; ++ ++err_bitbang: ++ ltq_spi_hw_disable(hw); ++ ++err_clk: ++ if (hw->fpiclk) ++ clk_put(hw->fpiclk); ++ if (hw->spiclk) ++ clk_put(hw->spiclk); ++ ++err_irq: ++ clk_put(hw->fpiclk); ++ ++ for (; i > 0; i--) ++ free_irq(hw->irq[i], hw); ++ ++err_master: ++ spi_master_put(master); ++ ++err: ++ return ret; ++} ++ ++static int ltq_spi_remove(struct platform_device *pdev) ++{ ++ struct ltq_spi *hw = platform_get_drvdata(pdev); ++ int i; ++ ++ spi_bitbang_stop(&hw->bitbang); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ ltq_spi_config_mode_set(hw); ++ ltq_spi_hw_disable(hw); ++ ++ for (i = 0; i < ARRAY_SIZE(hw->irq); i++) ++ if (0 < hw->irq[i]) ++ free_irq(hw->irq[i], hw); ++ ++ if (hw->fpiclk) ++ clk_put(hw->fpiclk); ++ if (hw->spiclk) ++ clk_put(hw->spiclk); ++ ++ spi_master_put(hw->bitbang.master); ++ ++ return 0; ++} ++ ++static const struct of_device_id ltq_spi_match[] = { ++ { .compatible = "lantiq,spi-xway" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ltq_spi_match); ++ ++static struct platform_driver ltq_spi_driver = { ++ .probe = ltq_spi_probe, ++ .remove = ltq_spi_remove, ++ .driver = { ++ .name = "spi-xway", ++ .owner = THIS_MODULE, ++ .of_match_table = ltq_spi_match, ++ }, ++}; ++ ++module_platform_driver(ltq_spi_driver); ++ ++MODULE_DESCRIPTION("Lantiq SoC SPI controller driver"); ++MODULE_AUTHOR("Daniel Schwierzeck "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:spi-xway"); diff --git a/target/linux/lantiq/patches-4.1/0034-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch b/target/linux/lantiq/patches-4.1/0034-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch new file mode 100644 index 0000000..ddbe134 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0034-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch @@ -0,0 +1,45 @@ +From b1b9fca8c317afc3f2b78bb54f877e8a830a819d Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 9 Aug 2013 18:47:27 +0200 +Subject: [PATCH 34/36] reset: Fix compile when reset RESET_CONTROLLER is not + selected + +Drivers need to protect their reset api calls with #ifdef to avoid compile +errors. + +This patch adds dummy wrappers in the same way that linux/of.h does it. + +Cc: linux-kernel@vger.kernel.org +Cc: Philipp Zabel +Cc: Gabor Juhos +--- + include/linux/reset-controller.h | 16 ++++++++++++++ + include/linux/reset.h | 43 ++++++++++++++++++++++++++++++++++++++ + 2 files changed, 59 insertions(+) + +--- a/include/linux/reset-controller.h ++++ b/include/linux/reset-controller.h +@@ -48,7 +48,23 @@ struct reset_controller_dev { + unsigned int nr_resets; + }; + ++#if defined(CONFIG_RESET_CONTROLLER) ++ + int reset_controller_register(struct reset_controller_dev *rcdev); + void reset_controller_unregister(struct reset_controller_dev *rcdev); + ++#else ++ ++static inline int reset_controller_register(struct reset_controller_dev *rcdev) ++{ ++ return -ENOSYS; ++} ++ ++void reset_controller_unregister(struct reset_controller_dev *rcdev) ++{ ++ ++} ++ ++#endif ++ + #endif diff --git a/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch new file mode 100644 index 0000000..2fc4db3 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch @@ -0,0 +1,614 @@ +From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 10 Sep 2014 22:42:14 +0200 +Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling + +Signed-off-by: John Crispin +--- + arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h | 6 + + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + + arch/mips/lantiq/xway/Makefile | 3 + + arch/mips/lantiq/xway/ath_eep.c | 282 ++++++++++++++++++++ + arch/mips/lantiq/xway/eth_mac.c | 76 ++++++ + arch/mips/lantiq/xway/pci-ath-fixup.c | 109 ++++++++ + arch/mips/lantiq/xway/rt_eep.c | 60 +++++ + 7 files changed, 539 insertions(+) + create mode 100644 arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h + create mode 100644 arch/mips/lantiq/xway/ath_eep.c + create mode 100644 arch/mips/lantiq/xway/eth_mac.c + create mode 100644 arch/mips/lantiq/xway/pci-ath-fixup.c + create mode 100644 arch/mips/lantiq/xway/rt_eep.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/pci-ath-fixup.h +@@ -0,0 +1,6 @@ ++#ifndef _PCI_ATH_FIXUP ++#define _PCI_ATH_FIXUP ++ ++void ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) __init; ++ ++#endif /* _PCI_ATH_FIXUP */ +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -90,5 +90,8 @@ int xrx200_gphy_boot(struct device *dev, + extern void ltq_pmu_enable(unsigned int module); + extern void ltq_pmu_disable(unsigned int module); + ++/* allow the ethernet driver to load a flash mapped mac addr */ ++const u8* ltq_get_eth_mac(void); ++ + #endif /* CONFIG_SOC_TYPE_XWAY */ + #endif /* _LTQ_XWAY_H__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -2,4 +2,7 @@ obj-y := prom.o sysctrl.o clk.o reset.o + + obj-y += vmmc.o tffs.o + ++obj-y += eth_mac.o ++obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o ++ + obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/ath_eep.c +@@ -0,0 +1,282 @@ ++/* ++ * Copyright (C) 2011 Luca Olivetti ++ * Copyright (C) 2011 John Crispin ++ * Copyright (C) 2011 Andrej VlaÅ¡ić ++ * Copyright (C) 2013 Ãlvaro Fernández Rojas ++ * Copyright (C) 2013 Daniel Gimpelevich ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); ++struct ath5k_platform_data ath5k_pdata; ++struct ath9k_platform_data ath9k_pdata = { ++ .led_pin = -1, ++}; ++static u8 athxk_eeprom_mac[6]; ++ ++static int ath9k_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &ath9k_pdata; ++ return 0; ++} ++ ++static int ath9k_eep_load; ++int __init of_ath9k_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node, *mtd_np; ++ struct resource *eep_res, *mac_res = NULL; ++ void __iomem *eep, *mac; ++ int mac_offset, led_pin; ++ u32 mac_inc = 0, pci_slot = 0; ++ int i; ++ struct mtd_info *the_mtd; ++ size_t flash_readlen; ++ const __be32 *list; ++ const char *part; ++ phandle phandle; ++ ++ if ((list = of_get_property(np, "ath,eep-flash", &i)) && i == 2 * ++ sizeof(*list) && (phandle = be32_to_cpup(list++)) && ++ (mtd_np = of_find_node_by_phandle(phandle)) && ((part = ++ of_get_property(mtd_np, "label", NULL)) || (part = ++ mtd_np->name)) && (the_mtd = get_mtd_device_nm(part)) ++ != ERR_PTR(-ENODEV)) { ++ i = mtd_read(the_mtd, be32_to_cpup(list), ++ ATH9K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen, ++ (void *) ath9k_pdata.eeprom_data); ++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { ++ size_t mac_readlen; ++ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, ++ (void *) athxk_eeprom_mac); ++ } ++ put_mtd_device(the_mtd); ++ if ((sizeof(ath9k_pdata.eeprom_data) != flash_readlen) || i) { ++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); ++ return -ENODEV; ++ } ++ } else { ++ eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ ++ if (!eep_res) { ++ dev_err(&pdev->dev, "failed to load eeprom address\n"); ++ return -ENODEV; ++ } ++ if (resource_size(eep_res) != ATH9K_PLAT_EEP_MAX_WORDS << 1) { ++ dev_err(&pdev->dev, "eeprom has an invalid size\n"); ++ return -EINVAL; ++ } ++ ++ eep = ioremap(eep_res->start, resource_size(eep_res)); ++ memcpy_fromio(ath9k_pdata.eeprom_data, eep, ++ ATH9K_PLAT_EEP_MAX_WORDS << 1); ++ } ++ ++ if (of_find_property(np, "ath,eep-swap", NULL)) ++ for (i = 0; i < ATH9K_PLAT_EEP_MAX_WORDS; i++) ++ ath9k_pdata.eeprom_data[i] = swab16(ath9k_pdata.eeprom_data[i]); ++ ++ if (of_find_property(np, "ath,eep-endian", NULL)) { ++ ath9k_pdata.endian_check = true; ++ ++ dev_info(&pdev->dev, "endian check enabled.\n"); ++ } ++ ++ if (!is_valid_ether_addr(athxk_eeprom_mac)) { ++ if (mac_res) { ++ if (resource_size(mac_res) != 6) { ++ dev_err(&pdev->dev, "mac has an invalid size\n"); ++ return -EINVAL; ++ } ++ mac = ioremap(mac_res->start, resource_size(mac_res)); ++ memcpy_fromio(athxk_eeprom_mac, mac, 6); ++ } else if (ltq_get_eth_mac()) { ++ memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6); ++ } ++ } ++ if (!is_valid_ether_addr(athxk_eeprom_mac)) { ++ dev_warn(&pdev->dev, "using random mac\n"); ++ random_ether_addr(athxk_eeprom_mac); ++ } ++ ++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) ++ athxk_eeprom_mac[5] += mac_inc; ++ ++ ath9k_pdata.macaddr = athxk_eeprom_mac; ++ ltq_pci_plat_dev_init = ath9k_pci_plat_dev_init; ++ ++ if (!of_property_read_u32(np, "ath,pci-slot", &pci_slot)) { ++ ltq_pci_ath_fixup(pci_slot, ath9k_pdata.eeprom_data); ++ ++ dev_info(&pdev->dev, "pci slot: %u\n", pci_slot); ++ if (ath9k_eep_load) { ++ struct pci_dev *d = NULL; ++ while ((d = pci_get_device(PCI_VENDOR_ID_ATHEROS, ++ PCI_ANY_ID, d)) != NULL) ++ pci_fixup_device(pci_fixup_early, d); ++ } ++ ++ } ++ ++ if (!of_property_read_u32(np, "ath,led-pin", &led_pin)) { ++ ath9k_pdata.led_pin = led_pin; ++ dev_info(&pdev->dev, "using led pin %d.\n", led_pin); ++ } ++ ++ dev_info(&pdev->dev, "loaded ath9k eeprom\n"); ++ ++ return 0; ++} ++ ++static struct of_device_id ath9k_eeprom_ids[] = { ++ { .compatible = "ath9k,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ath9k_eeprom_driver = { ++ .driver = { ++ .name = "ath9k,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ath9k_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ath9k_eeprom_init(void) ++{ ++ int ret = platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe); ++ ++ if (ret) ++ ath9k_eep_load = 1; ++ ++ return ret; ++} ++ ++static int __init of_ath9k_eeprom_init_late(void) ++{ ++ if (!ath9k_eep_load) ++ return 0; ++ return platform_driver_probe(&ath9k_eeprom_driver, of_ath9k_eeprom_probe); ++} ++late_initcall(of_ath9k_eeprom_init_late); ++subsys_initcall(of_ath9k_eeprom_init); ++ ++ ++static int ath5k_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &ath5k_pdata; ++ return 0; ++} ++ ++int __init of_ath5k_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node, *mtd_np; ++ struct resource *eep_res, *mac_res = NULL; ++ void __iomem *eep, *mac; ++ int mac_offset; ++ u32 mac_inc = 0; ++ int i; ++ struct mtd_info *the_mtd; ++ size_t flash_readlen; ++ const __be32 *list; ++ const char *part; ++ phandle phandle; ++ ++ if ((list = of_get_property(np, "ath,eep-flash", &i)) && i == 2 * ++ sizeof(*list) && (phandle = be32_to_cpup(list++)) && ++ (mtd_np = of_find_node_by_phandle(phandle)) && ((part = ++ of_get_property(mtd_np, "label", NULL)) || (part = ++ mtd_np->name)) && (the_mtd = get_mtd_device_nm(part)) ++ != ERR_PTR(-ENODEV)) { ++ i = mtd_read(the_mtd, be32_to_cpup(list), ++ ATH5K_PLAT_EEP_MAX_WORDS << 1, &flash_readlen, ++ (void *) ath5k_pdata.eeprom_data); ++ put_mtd_device(the_mtd); ++ if ((sizeof(ATH5K_PLAT_EEP_MAX_WORDS << 1) != flash_readlen) ++ || i) { ++ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); ++ return -ENODEV; ++ } ++ } else { ++ eep_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ ++ if (!eep_res) { ++ dev_err(&pdev->dev, "failed to load eeprom address\n"); ++ return -ENODEV; ++ } ++ if (resource_size(eep_res) != ATH5K_PLAT_EEP_MAX_WORDS << 1) { ++ dev_err(&pdev->dev, "eeprom has an invalid size\n"); ++ return -EINVAL; ++ } ++ ++ eep = ioremap(eep_res->start, resource_size(eep_res)); ++ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, ++ GFP_KERNEL); ++ memcpy_fromio(ath5k_pdata.eeprom_data, eep, ++ ATH5K_PLAT_EEP_MAX_WORDS << 1); ++ } ++ ++ if (of_find_property(np, "ath,eep-swap", NULL)) ++ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) ++ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); ++ ++ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { ++ memcpy_fromio(athxk_eeprom_mac, (void*) ath5k_pdata.eeprom_data + mac_offset, 6); ++ } else if (mac_res) { ++ if (resource_size(mac_res) != 6) { ++ dev_err(&pdev->dev, "mac has an invalid size\n"); ++ return -EINVAL; ++ } ++ mac = ioremap(mac_res->start, resource_size(mac_res)); ++ memcpy_fromio(athxk_eeprom_mac, mac, 6); ++ } else if (ltq_get_eth_mac()) ++ memcpy(athxk_eeprom_mac, ltq_get_eth_mac(), 6); ++ else { ++ dev_warn(&pdev->dev, "using random mac\n"); ++ random_ether_addr(athxk_eeprom_mac); ++ } ++ ++ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) ++ athxk_eeprom_mac[5] += mac_inc; ++ ++ ath5k_pdata.macaddr = athxk_eeprom_mac; ++ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; ++ ++ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); ++ ++ return 0; ++} ++ ++static struct of_device_id ath5k_eeprom_ids[] = { ++ { .compatible = "ath5k,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ath5k_eeprom_driver = { ++ .driver = { ++ .name = "ath5k,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ath5k_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ath5k_eeprom_init(void) ++{ ++ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); ++} ++device_initcall(of_ath5k_eeprom_init); +--- /dev/null ++++ b/arch/mips/lantiq/xway/eth_mac.c +@@ -0,0 +1,76 @@ ++/* ++ * Copyright (C) 2012 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++static u8 eth_mac[6]; ++static int eth_mac_set; ++ ++const u8* ltq_get_eth_mac(void) ++{ ++ return eth_mac; ++} ++ ++static int __init setup_ethaddr(char *str) ++{ ++ eth_mac_set = mac_pton(str, eth_mac); ++ return !eth_mac_set; ++} ++__setup("ethaddr=", setup_ethaddr); ++ ++int __init of_eth_mac_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct resource *mac_res; ++ void __iomem *mac; ++ u32 mac_inc = 0; ++ ++ if (eth_mac_set) { ++ dev_err(&pdev->dev, "mac was already set by bootloader\n"); ++ return -EINVAL; ++ } ++ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ if (!mac_res) { ++ dev_err(&pdev->dev, "failed to load mac\n"); ++ return -EINVAL; ++ } ++ if (resource_size(mac_res) != 6) { ++ dev_err(&pdev->dev, "mac has an invalid size\n"); ++ return -EINVAL; ++ } ++ mac = ioremap(mac_res->start, resource_size(mac_res)); ++ memcpy_fromio(eth_mac, mac, 6); ++ ++ if (!of_property_read_u32(np, "mac-increment", &mac_inc)) ++ eth_mac[5] += mac_inc; ++ ++ return 0; ++} ++ ++static struct of_device_id eth_mac_ids[] = { ++ { .compatible = "lantiq,eth-mac" }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver eth_mac_driver = { ++ .driver = { ++ .name = "lantiq,eth-mac", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(eth_mac_ids), ++ }, ++}; ++ ++static int __init of_eth_mac_init(void) ++{ ++ return platform_driver_probe(ð_mac_driver, of_eth_mac_probe); ++} ++device_initcall(of_eth_mac_init); +--- /dev/null ++++ b/arch/mips/lantiq/xway/pci-ath-fixup.c +@@ -0,0 +1,118 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++struct ath_fixup { ++ u16 *cal_data; ++ unsigned slot; ++}; ++ ++static int ath_num_fixups; ++static struct ath_fixup ath_fixups[2]; ++ ++static void ath_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ struct pci_dev *bridge = pci_upstream_bridge(dev); ++ u16 *cal_data = NULL; ++ u16 cmd; ++ u32 bar0; ++ u32 val; ++ u32 base; ++ unsigned i; ++ ++ for (i = 0; i < ath_num_fixups; i++) { ++ if (ath_fixups[i].cal_data == NULL) ++ continue; ++ ++ if (ath_fixups[i].slot != PCI_SLOT(dev->devfn)) ++ continue; ++ ++ cal_data = ath_fixups[i].cal_data; ++ break; ++ } ++ ++ if (cal_data == NULL) ++ return; ++ ++ if (*cal_data != 0xa55a) { ++ pr_err("pci %s: invalid calibration data\n", pci_name(dev)); ++ return; ++ } ++ ++ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); ++ ++ base = dev->resource[0].start; ++ mem = ioremap(base, 0x10000); ++ if (!mem) { ++ pr_err("pci %s: ioremap error\n", pci_name(dev)); ++ return; ++ } ++ ++ if (bridge) { ++ pci_enable_device(dev); ++ } ++ ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, base); ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ /* set pointer to first reg address */ ++ cal_data += 3; ++ while (*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; ++ ++ ltq_w32(swab32(val), mem + reg); ++ udelay(100); ++ } ++ ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; ++ ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ ++ ++ pr_info("pci %s: fixup info: [%04x:%04x] revision %02x class %#08x\n", ++ pci_name(dev), dev->vendor, dev->device, dev->revision, dev->class); ++ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); ++ ++ if (bridge) { ++ pci_disable_device(dev); ++ } ++ ++ iounmap(mem); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath_pci_fixup); ++ ++void __init ltq_pci_ath_fixup(unsigned slot, u16 *cal_data) ++{ ++ if (ath_num_fixups >= ARRAY_SIZE(ath_fixups)) ++ return; ++ ++ ath_fixups[ath_num_fixups].slot = slot; ++ ath_fixups[ath_num_fixups].cal_data = cal_data; ++ ath_num_fixups++; ++} +--- /dev/null ++++ b/arch/mips/lantiq/xway/rt_eep.c +@@ -0,0 +1,60 @@ ++/* ++ * Copyright (C) 2011 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); ++static struct rt2x00_platform_data rt2x00_pdata; ++ ++static int rt2x00_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ dev->dev.platform_data = &rt2x00_pdata; ++ return 0; ++} ++ ++int __init of_ralink_eeprom_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ const char *eeprom; ++ ++ if (of_property_read_string(np, "ralink,eeprom", &eeprom)) { ++ dev_err(&pdev->dev, "failed to load eeprom filename\n"); ++ return 0; ++ } ++ ++ rt2x00_pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL); ++// rt2x00_pdata.mac_address = mac; ++ ltq_pci_plat_dev_init = rt2x00_pci_plat_dev_init; ++ ++ dev_info(&pdev->dev, "using %s as eeprom\n", eeprom); ++ ++ return 0; ++} ++ ++static struct of_device_id ralink_eeprom_ids[] = { ++ { .compatible = "ralink,eeprom" }, ++ { } ++}; ++ ++static struct platform_driver ralink_eeprom_driver = { ++ .driver = { ++ .name = "ralink,eeprom", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ralink_eeprom_ids), ++ }, ++}; ++ ++static int __init of_ralink_eeprom_init(void) ++{ ++ return platform_driver_probe(&ralink_eeprom_driver, of_ralink_eeprom_probe); ++} ++device_initcall(of_ralink_eeprom_init); +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -840,7 +840,11 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_hw; + +- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); ++ if (priv->mac) ++ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); ++ else ++ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); ++ + if (!is_valid_ether_addr(mac.sa_data)) { + pr_warn("etop: invalid MAC, using random\n"); + eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-4.1/0036-owrt-generic-dtb-image-hack.patch b/target/linux/lantiq/patches-4.1/0036-owrt-generic-dtb-image-hack.patch new file mode 100644 index 0000000..7a306b3 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0036-owrt-generic-dtb-image-hack.patch @@ -0,0 +1,32 @@ +From dba8578e06aedf1e67312ebfc6162e2fadc9448d Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 7 Aug 2014 18:32:12 +0200 +Subject: [PATCH 36/36] owrt: generic dtb image hack + +Signed-off-by: John Crispin +--- + arch/mips/kernel/head.S | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/arch/mips/kernel/head.S ++++ b/arch/mips/kernel/head.S +@@ -86,6 +86,9 @@ EXPORT(__image_cmdline) + .fill 0x400 + #endif /* CONFIG_IMAGE_CMDLINE_HACK */ + ++ .ascii "OWRTDTB:" ++ EXPORT(__image_dtb) ++ .fill 0x4000 + __REF + + NESTED(kernel_entry, 16, sp) # kernel entry point +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -32,7 +32,6 @@ choice + config DT_EASY50712 + bool "Easy50712" + depends on SOC_XWAY +- select BUILTIN_DTB + endchoice + + config PCI_LANTIQ diff --git a/target/linux/lantiq/patches-4.1/0038-MIPS-lantiq-fpi-on-ar9.patch b/target/linux/lantiq/patches-4.1/0038-MIPS-lantiq-fpi-on-ar9.patch new file mode 100644 index 0000000..5fbe0a1 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0038-MIPS-lantiq-fpi-on-ar9.patch @@ -0,0 +1,21 @@ +Return correct value for fpi clock on ar9. + +Signed-off-by: Ben Mulvihill +--- + arch/mips/lantiq/xway/clk.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/arch/mips/lantiq/xway/clk.c ++++ b/arch/mips/lantiq/xway/clk.c +@@ -87,8 +87,9 @@ unsigned long ltq_ar9_fpi_hz(void) + unsigned long sys = ltq_ar9_sys_hz(); + + if (ltq_cgu_r32(CGU_SYS) & BIT(0)) +- return sys; +- return sys >> 1; ++ return sys / 3; ++ else ++ return sys / 2; + } + + unsigned long ltq_ar9_cpu_hz(void) diff --git a/target/linux/lantiq/patches-4.1/0039-MIPS-lantiq-initialize-usb-on-boot.patch b/target/linux/lantiq/patches-4.1/0039-MIPS-lantiq-initialize-usb-on-boot.patch new file mode 100644 index 0000000..fd0da8e --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0039-MIPS-lantiq-initialize-usb-on-boot.patch @@ -0,0 +1,97 @@ +--- a/arch/mips/lantiq/xway/reset.c ++++ b/arch/mips/lantiq/xway/reset.c +@@ -44,6 +44,37 @@ + #define RCU_BOOT_SEL(x) ((x >> 18) & 0x7) + #define RCU_BOOT_SEL_XRX200(x) (((x >> 17) & 0xf) | ((x >> 8) & 0x10)) + ++/* dwc2 USB configuration registers */ ++#define RCU_USB1CFG 0x0018 ++#define RCU_USB2CFG 0x0034 ++ ++/* USB DMA endianness bits */ ++#define RCU_USBCFG_HDSEL_BIT BIT(11) ++#define RCU_USBCFG_HOST_END_BIT BIT(10) ++#define RCU_USBCFG_SLV_END_BIT BIT(9) ++ ++/* USB reset bits */ ++#define RCU_USBRESET 0x0010 ++ ++#define USBRESET_BIT BIT(4) ++ ++#define RCU_USBRESET2 0x0048 ++ ++#define USB1RESET_BIT BIT(4) ++#define USB2RESET_BIT BIT(5) ++ ++#define RCU_CFG1A 0x0038 ++#define RCU_CFG1B 0x003C ++ ++/* USB PMU devices */ ++#define PMU_AHBM BIT(15) ++#define PMU_USB0 BIT(6) ++#define PMU_USB1 BIT(27) ++ ++/* USB PHY PMU devices */ ++#define PMU_USB0_P BIT(0) ++#define PMU_USB1_P BIT(26) ++ + /* remapped base addr of the reset control unit */ + static void __iomem *ltq_rcu_membase; + static struct device_node *ltq_rcu_np; +@@ -200,6 +231,45 @@ static void ltq_machine_power_off(void) + unreachable(); + } + ++static void ltq_usb_init(void) ++{ ++ /* Power for USB cores 1 & 2 */ ++ ltq_pmu_enable(PMU_AHBM); ++ ltq_pmu_enable(PMU_USB0); ++ ltq_pmu_enable(PMU_USB1); ++ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B); ++ ++ /* Enable USB PHY power for cores 1 & 2 */ ++ ltq_pmu_enable(PMU_USB0_P); ++ ltq_pmu_enable(PMU_USB1_P); ++ ++ /* Configure cores to host mode */ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT, ++ RCU_USB1CFG); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT, ++ RCU_USB2CFG); ++ ++ /* Select DMA endianness (Host-endian: big-endian) */ ++ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT) ++ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG); ++ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT) ++ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG); ++ ++ /* Hard reset USB state machines */ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET); ++ udelay(50 * 1000); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET); ++ ++ /* Soft reset USB state machines */ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2) ++ | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2); ++ udelay(50 * 1000); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2) ++ & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2); ++} ++ + static int __init mips_reboot_setup(void) + { + struct resource res; +@@ -223,6 +293,10 @@ static int __init mips_reboot_setup(void + if (!ltq_rcu_membase) + panic("Failed to remap core memory"); + ++ if (of_machine_is_compatible("lantiq,ar9") || ++ of_machine_is_compatible("lantiq,vr9")) ++ ltq_usb_init(); ++ + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; diff --git a/target/linux/lantiq/patches-4.1/0040-USB-DWC2-enable-usb-power-gpio.patch b/target/linux/lantiq/patches-4.1/0040-USB-DWC2-enable-usb-power-gpio.patch new file mode 100644 index 0000000..9c6f11c --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0040-USB-DWC2-enable-usb-power-gpio.patch @@ -0,0 +1,35 @@ +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -41,6 +41,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -161,6 +162,7 @@ static int dwc2_driver_probe(struct plat + struct usb_phy *uphy; + int retval; + int irq; ++ int gpio_count; + + match = of_match_device(dwc2_of_match_table, &dev->dev); + if (match && match->data) { +@@ -177,6 +179,16 @@ static int dwc2_driver_probe(struct plat + defparams.dma_desc_enable = 0; + } + ++ gpio_count = of_gpio_count(dev->dev.of_node); ++ while (gpio_count > 0) { ++ enum of_gpio_flags flags; ++ int gpio = of_get_gpio_flags(dev->dev.of_node, --gpio_count, &flags); ++ if (gpio_request(gpio, "usb")) ++ continue; ++ dev_info(&dev->dev, "requested GPIO %d\n", gpio); ++ gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); ++ } ++ + hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); + if (!hsotg) + return -ENOMEM; diff --git a/target/linux/lantiq/patches-4.1/0041-USB-DWC2-add-ltq-params.patch b/target/linux/lantiq/patches-4.1/0041-USB-DWC2-add-ltq-params.patch new file mode 100644 index 0000000..c55f5b6 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0041-USB-DWC2-add-ltq-params.patch @@ -0,0 +1,46 @@ +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -107,6 +107,34 @@ static const struct dwc2_core_params par + .uframe_sched = -1, + }; + ++static const struct dwc2_core_params params_ltq = { ++ .otg_cap = 2, /* non-HNP/non-SRP */ ++ .otg_ver = -1, ++ .dma_enable = -1, ++ .dma_desc_enable = -1, ++ .speed = -1, ++ .enable_dynamic_fifo = -1, ++ .en_multiple_tx_fifo = -1, ++ .host_rx_fifo_size = 240, /* 240 DWORDs */ ++ .host_nperio_tx_fifo_size = 240, /* 240 DWORDs */ ++ .host_perio_tx_fifo_size = 32, /* 32 DWORDs */ ++ .max_transfer_size = -1, ++ .max_packet_count = -1, ++ .host_channels = -1, ++ .phy_type = -1, ++ .phy_utmi_width = -1, ++ .phy_ulpi_ddr = -1, ++ .phy_ulpi_ext_vbus = -1, ++ .i2c_enable = -1, ++ .ulpi_fs_ls = -1, ++ .host_support_fs_ls_low_power = -1, ++ .host_ls_low_power_phy_clk = -1, ++ .ts_dline = -1, ++ .reload_ctl = -1, ++ .ahbcfg = -1, ++ .uframe_sched = -1, ++}; ++ + /** + * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the + * DWC_otg driver +@@ -133,6 +161,8 @@ static int dwc2_driver_remove(struct pla + static const struct of_device_id dwc2_of_match_table[] = { + { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, + { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, ++ { .compatible = "lantiq,ifxhcd-arx100-dwc2", .data = ¶ms_ltq }, ++ { .compatible = "lantiq,ifxhcd-xrx200-dwc2", .data = ¶ms_ltq }, + { .compatible = "snps,dwc2", .data = NULL }, + { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, + {}, diff --git a/target/linux/lantiq/patches-4.1/0042-USB-DWC2-big-endian-support.patch b/target/linux/lantiq/patches-4.1/0042-USB-DWC2-big-endian-support.patch new file mode 100644 index 0000000..2d8ccab --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0042-USB-DWC2-big-endian-support.patch @@ -0,0 +1,3156 @@ +--- a/drivers/usb/dwc2/core.c ++++ b/drivers/usb/dwc2/core.c +@@ -67,10 +67,10 @@ static void dwc2_enable_common_interrupt + u32 intmsk; + + /* Clear any pending OTG Interrupts */ +- writel(0xffffffff, hsotg->regs + GOTGINT); ++ dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + + /* Clear any pending interrupts */ +- writel(0xffffffff, hsotg->regs + GINTSTS); ++ dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + + /* Enable the interrupts in the GINTMSK */ + intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; +@@ -81,7 +81,7 @@ static void dwc2_enable_common_interrupt + intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP | + GINTSTS_SESSREQINT; + +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /* +@@ -104,10 +104,10 @@ static void dwc2_init_fs_ls_pclk_sel(str + } + + dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + + /* +@@ -125,7 +125,7 @@ static int dwc2_core_reset(struct dwc2_h + /* Wait for AHB master IDLE state */ + do { + usleep_range(20000, 40000); +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 50) { + dev_warn(hsotg->dev, + "%s() HANG! AHB Idle GRSTCTL=%0x\n", +@@ -137,10 +137,10 @@ static int dwc2_core_reset(struct dwc2_h + /* Core Soft Reset */ + count = 0; + greset |= GRSTCTL_CSFTRST; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + do { + usleep_range(20000, 40000); +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 50) { + dev_warn(hsotg->dev, + "%s() HANG! Soft Reset GRSTCTL=%0x\n", +@@ -150,20 +150,20 @@ static int dwc2_core_reset(struct dwc2_h + } while (greset & GRSTCTL_CSFTRST); + + if (hsotg->dr_mode == USB_DR_MODE_HOST) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEDEVMODE; + gusbcfg |= GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; + gusbcfg |= GUSBCFG_FORCEDEVMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } else if (hsotg->dr_mode == USB_DR_MODE_OTG) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; + gusbcfg &= ~GUSBCFG_FORCEDEVMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } + + /* +@@ -186,9 +186,9 @@ static int dwc2_fs_phy_init(struct dwc2_ + */ + if (select_phy) { + dev_dbg(hsotg->dev, "FS PHY selected\n"); +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_PHYSEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset after a PHY select */ + retval = dwc2_core_reset(hsotg); +@@ -211,18 +211,18 @@ static int dwc2_fs_phy_init(struct dwc2_ + dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); + + /* Program GUSBCFG.OtgUtmiFsSel to I2C */ +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Program GI2CCTL.I2CEn */ +- i2cctl = readl(hsotg->regs + GI2CCTL); ++ i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); + i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; + i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; + i2cctl &= ~GI2CCTL_I2CEN; +- writel(i2cctl, hsotg->regs + GI2CCTL); ++ dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); + i2cctl |= GI2CCTL_I2CEN; +- writel(i2cctl, hsotg->regs + GI2CCTL); ++ dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); + } + + return retval; +@@ -236,7 +236,7 @@ static int dwc2_hs_phy_init(struct dwc2_ + if (!select_phy) + return 0; + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + + /* + * HS PHY parameters. These parameters are preserved during soft reset +@@ -264,7 +264,7 @@ static int dwc2_hs_phy_init(struct dwc2_ + break; + } + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset after setting the PHY parameters */ + retval = dwc2_core_reset(hsotg); +@@ -299,15 +299,15 @@ static int dwc2_phy_init(struct dwc2_hso + hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && + hsotg->core_params->ulpi_fs_ls > 0) { + dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_ULPI_FS_LS; + usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } else { +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg &= ~GUSBCFG_ULPI_FS_LS; + usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } + + return retval; +@@ -315,7 +315,7 @@ static int dwc2_phy_init(struct dwc2_hso + + static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + switch (hsotg->hw_params.arch) { + case GHWCFG2_EXT_DMA_ARCH: +@@ -354,7 +354,7 @@ static int dwc2_gahbcfg_init(struct dwc2 + if (hsotg->core_params->dma_enable > 0) + ahbcfg |= GAHBCFG_DMA_EN; + +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + + return 0; + } +@@ -363,7 +363,7 @@ static void dwc2_gusbcfg_init(struct dwc + { + u32 usbcfg; + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); + + switch (hsotg->hw_params.op_mode) { +@@ -391,7 +391,7 @@ static void dwc2_gusbcfg_init(struct dwc + break; + } + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } + + /** +@@ -409,7 +409,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs + + dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + + /* Set ULPI External VBUS bit if needed */ + usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; +@@ -422,7 +422,7 @@ int dwc2_core_init(struct dwc2_hsotg *hs + if (hsotg->core_params->ts_dline > 0) + usbcfg |= GUSBCFG_TERMSELDLPULSE; + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset the Controller */ + retval = dwc2_core_reset(hsotg); +@@ -448,11 +448,11 @@ int dwc2_core_init(struct dwc2_hsotg *hs + dwc2_gusbcfg_init(hsotg); + + /* Program the GOTGCTL register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_OTGVER; + if (hsotg->core_params->otg_ver > 0) + otgctl |= GOTGCTL_OTGVER; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); + + /* Clear the SRP success bit for FS-I2c */ +@@ -488,16 +488,16 @@ void dwc2_enable_host_interrupts(struct + dev_dbg(hsotg->dev, "%s()\n", __func__); + + /* Disable all interrupts */ +- writel(0, hsotg->regs + GINTMSK); +- writel(0, hsotg->regs + HAINTMSK); ++ dwc2_writel(0, hsotg->regs + GINTMSK); ++ dwc2_writel(0, hsotg->regs + HAINTMSK); + + /* Enable the common interrupts */ + dwc2_enable_common_interrupts(hsotg); + + /* Enable host mode interrupts without disturbing common interrupts */ +- intmsk = readl(hsotg->regs + GINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /** +@@ -507,12 +507,12 @@ void dwc2_enable_host_interrupts(struct + */ + void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 intmsk = readl(hsotg->regs + GINTMSK); ++ u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); + + /* Disable host mode interrupts without disturbing common interrupts */ + intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | + GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /* +@@ -592,36 +592,36 @@ static void dwc2_config_fifos(struct dwc + dwc2_calculate_dynamic_fifo(hsotg); + + /* Rx FIFO */ +- grxfsiz = readl(hsotg->regs + GRXFSIZ); ++ grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); + grxfsiz &= ~GRXFSIZ_DEPTH_MASK; + grxfsiz |= params->host_rx_fifo_size << + GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; +- writel(grxfsiz, hsotg->regs + GRXFSIZ); +- dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ)); ++ dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); ++ dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", dwc2_readl(hsotg->regs + GRXFSIZ)); + + /* Non-periodic Tx FIFO */ + dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + nptxfsiz = params->host_nperio_tx_fifo_size << + FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; + nptxfsiz |= params->host_rx_fifo_size << + FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; +- writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); ++ dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); + dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + + /* Periodic Tx FIFO */ + dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", +- readl(hsotg->regs + HPTXFSIZ)); ++ dwc2_readl(hsotg->regs + HPTXFSIZ)); + hptxfsiz = params->host_perio_tx_fifo_size << + FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; + hptxfsiz |= (params->host_rx_fifo_size + + params->host_nperio_tx_fifo_size) << + FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; +- writel(hptxfsiz, hsotg->regs + HPTXFSIZ); ++ dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); + dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", +- readl(hsotg->regs + HPTXFSIZ)); ++ dwc2_readl(hsotg->regs + HPTXFSIZ)); + + if (hsotg->core_params->en_multiple_tx_fifo > 0 && + hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { +@@ -629,14 +629,14 @@ static void dwc2_config_fifos(struct dwc + * Global DFIFOCFG calculation for Host mode - + * include RxFIFO, NPTXFIFO and HPTXFIFO + */ +- dfifocfg = readl(hsotg->regs + GDFIFOCFG); ++ dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); + dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; + dfifocfg |= (params->host_rx_fifo_size + + params->host_nperio_tx_fifo_size + + params->host_perio_tx_fifo_size) << + GDFIFOCFG_EPINFOBASE_SHIFT & + GDFIFOCFG_EPINFOBASE_MASK; +- writel(dfifocfg, hsotg->regs + GDFIFOCFG); ++ dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); + } + } + +@@ -657,14 +657,14 @@ void dwc2_core_host_init(struct dwc2_hso + dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + /* Restart the Phy Clock */ +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + + /* Initialize Host Configuration Register */ + dwc2_init_fs_ls_pclk_sel(hsotg); + if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg |= HCFG_FSLSSUPP; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + + /* +@@ -673,9 +673,9 @@ void dwc2_core_host_init(struct dwc2_hso + * and its value must not be changed during runtime. + */ + if (hsotg->core_params->reload_ctl > 0) { +- hfir = readl(hsotg->regs + HFIR); ++ hfir = dwc2_readl(hsotg->regs + HFIR); + hfir |= HFIR_RLDCTRL; +- writel(hfir, hsotg->regs + HFIR); ++ dwc2_writel(hfir, hsotg->regs + HFIR); + } + + if (hsotg->core_params->dma_desc_enable > 0) { +@@ -691,9 +691,9 @@ void dwc2_core_host_init(struct dwc2_hso + "falling back to buffer DMA mode.\n"); + hsotg->core_params->dma_desc_enable = 0; + } else { +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg |= HCFG_DESCDMA; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + } + +@@ -702,18 +702,18 @@ void dwc2_core_host_init(struct dwc2_hso + + /* TODO - check this */ + /* Clear Host Set HNP Enable in the OTG Control Register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_HSTSETHNPEN; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + /* Make sure the FIFOs are flushed */ + dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); + dwc2_flush_rx_fifo(hsotg); + + /* Clear Host Set HNP Enable in the OTG Control Register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_HSTSETHNPEN; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + if (hsotg->core_params->dma_desc_enable <= 0) { + int num_channels, i; +@@ -722,25 +722,25 @@ void dwc2_core_host_init(struct dwc2_hso + /* Flush out any leftover queued requests */ + num_channels = hsotg->core_params->host_channels; + for (i = 0; i < num_channels; i++) { +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar &= ~HCCHAR_CHENA; + hcchar |= HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + + /* Halt all channels to put them into a known state */ + for (i = 0; i < num_channels; i++) { + int count = 0; + +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dev_dbg(hsotg->dev, "%s: Halt channel %d\n", + __func__, i); + do { +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (++count > 1000) { + dev_err(hsotg->dev, + "Unable to clear enable on channel %d\n", +@@ -761,7 +761,7 @@ void dwc2_core_host_init(struct dwc2_hso + !!(hprt0 & HPRT0_PWR)); + if (!(hprt0 & HPRT0_PWR)) { + hprt0 |= HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + } + +@@ -841,7 +841,7 @@ static void dwc2_hc_enable_slave_ints(st + break; + } + +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); + } +@@ -878,7 +878,7 @@ static void dwc2_hc_enable_dma_ints(stru + } + } + +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); + } +@@ -899,16 +899,16 @@ static void dwc2_hc_enable_ints(struct d + } + + /* Enable the top level host channel interrupt */ +- intmsk = readl(hsotg->regs + HAINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + HAINTMSK); + intmsk |= 1 << chan->hc_num; +- writel(intmsk, hsotg->regs + HAINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + HAINTMSK); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); + + /* Make sure host channel interrupts are enabled */ +- intmsk = readl(hsotg->regs + GINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk |= GINTSTS_HCHINT; +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); + } +@@ -937,7 +937,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso + /* Clear old interrupt conditions for this host channel */ + hcintmsk = 0xffffffff; + hcintmsk &= ~HCINTMSK_RESERVED14_31; +- writel(hcintmsk, hsotg->regs + HCINT(hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); + + /* Enable channel interrupts required for this transfer */ + dwc2_hc_enable_ints(hsotg, chan); +@@ -954,7 +954,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso + hcchar |= HCCHAR_LSPDDEV; + hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; + hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; +- writel(hcchar, hsotg->regs + HCCHAR(hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", + hc_num, hcchar); +@@ -1008,7 +1008,7 @@ void dwc2_hc_init(struct dwc2_hsotg *hso + } + } + +- writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); ++ dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); + } + + /** +@@ -1060,14 +1060,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + u32 hcintmsk = HCINTMSK_CHHLTD; + + dev_vdbg(hsotg->dev, "dequeue/error\n"); +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + + /* + * Make sure no other interrupts besides halt are currently + * pending. Handling another interrupt could cause a crash due + * to the QTD and QH state. + */ +- writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); ++ dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + + /* + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR +@@ -1076,7 +1076,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + */ + chan->halt_status = halt_status; + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + if (!(hcchar & HCCHAR_CHENA)) { + /* + * The channel is either already halted or it hasn't +@@ -1104,7 +1104,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + return; + } + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + + /* No need to set the bit in DDMA for disabling the channel */ + /* TODO check it everywhere channel is disabled */ +@@ -1127,7 +1127,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || + chan->ep_type == USB_ENDPOINT_XFER_BULK) { + dev_vdbg(hsotg->dev, "control/bulk\n"); +- nptxsts = readl(hsotg->regs + GNPTXSTS); ++ nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { + dev_vdbg(hsotg->dev, "Disabling channel\n"); + hcchar &= ~HCCHAR_CHENA; +@@ -1135,7 +1135,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + } else { + if (dbg_perio()) + dev_vdbg(hsotg->dev, "isoc/intr\n"); +- hptxsts = readl(hsotg->regs + HPTXSTS); ++ hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); + if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || + hsotg->queuing_high_bandwidth) { + if (dbg_perio()) +@@ -1148,7 +1148,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hso + dev_vdbg(hsotg->dev, "DMA enabled\n"); + } + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + chan->halt_status = halt_status; + + if (hcchar & HCCHAR_CHENA) { +@@ -1195,10 +1195,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg * + * Clear channel interrupt enables and any unhandled channel interrupt + * conditions + */ +- writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); + hcintmsk = 0xffffffff; + hcintmsk &= ~HCINTMSK_RESERVED14_31; +- writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + } + + /** +@@ -1284,13 +1284,13 @@ static void dwc2_hc_write_packet(struct + if (((unsigned long)data_buf & 0x3) == 0) { + /* xfer_buf is DWORD aligned */ + for (i = 0; i < dword_count; i++, data_buf++) +- writel(*data_buf, data_fifo); ++ dwc2_writel(*data_buf, data_fifo); + } else { + /* xfer_buf is not DWORD aligned */ + for (i = 0; i < dword_count; i++, data_buf++) { + u32 data = data_buf[0] | data_buf[1] << 8 | + data_buf[2] << 16 | data_buf[3] << 24; +- writel(data, data_fifo); ++ dwc2_writel(data, data_fifo); + } + } + +@@ -1443,7 +1443,7 @@ void dwc2_hc_start_transfer(struct dwc2_ + hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; + hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & + TSIZ_SC_MC_PID_MASK; +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", + hctsiz, chan->hc_num); +@@ -1471,7 +1471,7 @@ void dwc2_hc_start_transfer(struct dwc2_ + } else { + dma_addr = chan->xfer_dma; + } +- writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); ++ dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", + (unsigned long)dma_addr, chan->hc_num); +@@ -1479,13 +1479,13 @@ void dwc2_hc_start_transfer(struct dwc2_ + + /* Start the split */ + if (chan->do_split) { +- u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); ++ u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); + + hcsplt |= HCSPLT_SPLTENA; +- writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); ++ dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); + } + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar &= ~HCCHAR_MULTICNT_MASK; + hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & + HCCHAR_MULTICNT_MASK; +@@ -1505,7 +1505,7 @@ void dwc2_hc_start_transfer(struct dwc2_ + (hcchar & HCCHAR_MULTICNT_MASK) >> + HCCHAR_MULTICNT_SHIFT); + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, + chan->hc_num); +@@ -1564,18 +1564,18 @@ void dwc2_hc_start_transfer_ddma(struct + dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); + } + +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + + hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK; + + /* Always start from first descriptor */ + hc_dma &= ~HCDMA_CTD_MASK; +- writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); ++ dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", + hc_dma, chan->hc_num); + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar &= ~HCCHAR_MULTICNT_MASK; + hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & + HCCHAR_MULTICNT_MASK; +@@ -1594,7 +1594,7 @@ void dwc2_hc_start_transfer_ddma(struct + (hcchar & HCCHAR_MULTICNT_MASK) >> + HCCHAR_MULTICNT_SHIFT); + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, + chan->hc_num); +@@ -1651,7 +1651,7 @@ int dwc2_hc_continue_transfer(struct dwc + * transfer completes, the extra requests for the channel will + * be flushed. + */ +- u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + + dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); + hcchar |= HCCHAR_CHENA; +@@ -1659,7 +1659,7 @@ int dwc2_hc_continue_transfer(struct dwc + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", + hcchar); +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + chan->requests++; + return 1; + } +@@ -1669,7 +1669,7 @@ int dwc2_hc_continue_transfer(struct dwc + if (chan->xfer_count < chan->xfer_len) { + if (chan->ep_type == USB_ENDPOINT_XFER_INT || + chan->ep_type == USB_ENDPOINT_XFER_ISOC) { +- u32 hcchar = readl(hsotg->regs + ++ u32 hcchar = dwc2_readl(hsotg->regs + + HCCHAR(chan->hc_num)); + + dwc2_hc_set_even_odd_frame(hsotg, chan, +@@ -1706,12 +1706,12 @@ void dwc2_hc_do_ping(struct dwc2_hsotg * + + hctsiz = TSIZ_DOPNG; + hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar |= HCCHAR_CHENA; + hcchar &= ~HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + } + + /** +@@ -1730,8 +1730,8 @@ u32 dwc2_calc_frame_interval(struct dwc2 + u32 hprt0; + int clock = 60; /* default value */ + +- usbcfg = readl(hsotg->regs + GUSBCFG); +- hprt0 = readl(hsotg->regs + HPRT0); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && + !(usbcfg & GUSBCFG_PHYIF16)) +@@ -1787,7 +1787,7 @@ void dwc2_read_packet(struct dwc2_hsotg + dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); + + for (i = 0; i < word_count; i++, data_buf++) +- *data_buf = readl(fifo); ++ *data_buf = dwc2_readl(fifo); + } + + /** +@@ -1807,56 +1807,56 @@ void dwc2_dump_host_registers(struct dwc + dev_dbg(hsotg->dev, "Host Global Registers\n"); + addr = hsotg->regs + HCFG; + dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HFIR; + dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HFNUM; + dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HPTXSTS; + dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HAINT; + dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HAINTMSK; + dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + if (hsotg->core_params->dma_desc_enable > 0) { + addr = hsotg->regs + HFLBADDR; + dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + } + + addr = hsotg->regs + HPRT0; + dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + + for (i = 0; i < hsotg->core_params->host_channels; i++) { + dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); + addr = hsotg->regs + HCCHAR(i); + dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCSPLT(i); + dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCINT(i); + dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCINTMSK(i); + dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCTSIZ(i); + dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCDMA(i); + dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + if (hsotg->core_params->dma_desc_enable > 0) { + addr = hsotg->regs + HCDMAB(i); + dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + } + } + #endif +@@ -1878,80 +1878,80 @@ void dwc2_dump_global_registers(struct d + dev_dbg(hsotg->dev, "Core Global Registers\n"); + addr = hsotg->regs + GOTGCTL; + dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GOTGINT; + dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GAHBCFG; + dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GUSBCFG; + dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRSTCTL; + dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GINTSTS; + dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GINTMSK; + dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRXSTSR; + dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRXFSIZ; + dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GNPTXFSIZ; + dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GNPTXSTS; + dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GI2CCTL; + dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GPVNDCTL; + dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GGPIO; + dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GUID; + dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GSNPSID; + dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG1; + dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG2; + dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG3; + dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG4; + dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GLPMCFG; + dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GPWRDN; + dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GDFIFOCFG; + dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HPTXFSIZ; + dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + + addr = hsotg->regs + PCGCTL; + dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + #endif + } + +@@ -1970,15 +1970,15 @@ void dwc2_flush_tx_fifo(struct dwc2_hsot + + greset = GRSTCTL_TXFFLSH; + greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + + do { +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 10000) { + dev_warn(hsotg->dev, + "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", + __func__, greset, +- readl(hsotg->regs + GNPTXSTS)); ++ dwc2_readl(hsotg->regs + GNPTXSTS)); + break; + } + udelay(1); +@@ -2001,10 +2001,10 @@ void dwc2_flush_rx_fifo(struct dwc2_hsot + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + greset = GRSTCTL_RXFFLSH; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + + do { +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 10000) { + dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", + __func__, greset); +@@ -2666,7 +2666,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg + * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", + * as in "OTG version 2.xx" or "OTG version 3.xx". + */ +- hw->snpsid = readl(hsotg->regs + GSNPSID); ++ hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); + if ((hw->snpsid & 0xfffff000) != 0x4f542000 && + (hw->snpsid & 0xfffff000) != 0x4f543000) { + dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", +@@ -2678,11 +2678,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg + hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, + hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); + +- hwcfg1 = readl(hsotg->regs + GHWCFG1); +- hwcfg2 = readl(hsotg->regs + GHWCFG2); +- hwcfg3 = readl(hsotg->regs + GHWCFG3); +- hwcfg4 = readl(hsotg->regs + GHWCFG4); +- grxfsiz = readl(hsotg->regs + GRXFSIZ); ++ hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); ++ hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); ++ hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); ++ hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); ++ grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + + dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); + dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); +@@ -2691,18 +2691,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg + dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); + + /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */ +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg |= GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + usleep_range(100000, 150000); + +- gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ); +- hptxfsiz = readl(hsotg->regs + HPTXFSIZ); ++ gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); ++ hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); + dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); + dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + usleep_range(100000, 150000); + + /* hwcfg2 */ +@@ -2821,7 +2821,7 @@ u16 dwc2_get_otg_version(struct dwc2_hso + + bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) + { +- if (readl(hsotg->regs + GSNPSID) == 0xffffffff) ++ if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) + return false; + else + return true; +@@ -2835,10 +2835,10 @@ bool dwc2_is_controller_alive(struct dwc + */ + void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + ahbcfg |= GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + } + + /** +@@ -2849,10 +2849,10 @@ void dwc2_enable_global_interrupts(struc + */ + void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + } + + MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); +--- a/drivers/usb/dwc2/core.h ++++ b/drivers/usb/dwc2/core.h +@@ -44,16 +44,28 @@ + #include + #include "hw.h" + +-#ifdef DWC2_LOG_WRITES +-static inline void do_write(u32 value, void *addr) ++static inline u32 dwc2_readl(const void __iomem *addr) + { +- writel(value, addr); +- pr_info("INFO:: wrote %08x to %p\n", value, addr); ++ u32 value = __raw_readl(addr); ++ ++ /* In order to preserve endianness __raw_* operation is used. Therefore ++ a barrier is needed to ensure IO access is not re-ordered across ++ reads or writes */ ++ mb(); ++ return value; + } + +-#undef writel +-#define writel(v, a) do_write(v, a) ++static inline void dwc2_writel(u32 value, void __iomem *addr) ++{ ++ __raw_writel(value, addr); ++ /* In order to preserve endianness __raw_* operation is used. Therefore ++ a barrier is needed to ensure IO access is not re-ordered across ++ reads or writes */ ++ mb(); ++#ifdef DWC2_LOG_WRITES ++ pr_info("INFO:: wrote %08x to %p\n", value, addr); + #endif ++} + + /* Maximum number of Endpoints/HostChannels */ + #define MAX_EPS_CHANNELS 16 +--- a/drivers/usb/dwc2/core_intr.c ++++ b/drivers/usb/dwc2/core_intr.c +@@ -80,15 +80,15 @@ static const char *dwc2_op_state_str(str + */ + static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) + { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + if (hprt0 & HPRT0_ENACHG) { + hprt0 &= ~HPRT0_ENA; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + /* Clear interrupt */ +- writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); + } + + /** +@@ -102,7 +102,7 @@ static void dwc2_handle_mode_mismatch_in + dwc2_is_host_mode(hsotg) ? "Host" : "Device"); + + /* Clear interrupt */ +- writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); + } + + /** +@@ -117,8 +117,8 @@ static void dwc2_handle_otg_intr(struct + u32 gotgctl; + u32 gintmsk; + +- gotgint = readl(hsotg->regs + GOTGINT); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgint = dwc2_readl(hsotg->regs + GOTGINT); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, + dwc2_op_state_str(hsotg)); + +@@ -126,7 +126,7 @@ static void dwc2_handle_otg_intr(struct + dev_dbg(hsotg->dev, + " ++OTG Interrupt: Session End Detected++ (%s)\n", + dwc2_op_state_str(hsotg)); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + + if (dwc2_is_device_mode(hsotg)) + s3c_hsotg_disconnect(hsotg); +@@ -152,15 +152,15 @@ static void dwc2_handle_otg_intr(struct + hsotg->lx_state = DWC2_L0; + } + +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~GOTGCTL_DEVHNPEN; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + } + + if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { + dev_dbg(hsotg->dev, + " ++OTG Interrupt: Session Request Success Status Change++\n"); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + if (gotgctl & GOTGCTL_SESREQSCS) { + if (hsotg->core_params->phy_type == + DWC2_PHY_TYPE_PARAM_FS +@@ -168,9 +168,9 @@ static void dwc2_handle_otg_intr(struct + hsotg->srp_success = 1; + } else { + /* Clear Session Request */ +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~GOTGCTL_SESREQ; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + } + } + } +@@ -180,7 +180,7 @@ static void dwc2_handle_otg_intr(struct + * Print statements during the HNP interrupt handling + * can cause it to fail + */ +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + /* + * WA for 3.00a- HW is not setting cur_mode, even sometimes + * this does not help +@@ -200,9 +200,9 @@ static void dwc2_handle_otg_intr(struct + * interrupt does not get handled and Linux + * complains loudly. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + + /* + * Call callback function with spin lock +@@ -216,9 +216,9 @@ static void dwc2_handle_otg_intr(struct + hsotg->op_state = OTG_STATE_B_HOST; + } + } else { +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "HNP Failed\n"); + dev_err(hsotg->dev, + "Device Not Connected/Responding\n"); +@@ -244,9 +244,9 @@ static void dwc2_handle_otg_intr(struct + hsotg->op_state = OTG_STATE_A_PERIPHERAL; + } else { + /* Need to disable SOF interrupt immediately */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + spin_unlock(&hsotg->lock); + dwc2_hcd_start(hsotg); + spin_lock(&hsotg->lock); +@@ -261,7 +261,7 @@ static void dwc2_handle_otg_intr(struct + dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); + + /* Clear GOTGINT */ +- writel(gotgint, hsotg->regs + GOTGINT); ++ dwc2_writel(gotgint, hsotg->regs + GOTGINT); + } + + /** +@@ -276,11 +276,11 @@ static void dwc2_handle_otg_intr(struct + */ + static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) + { +- u32 gintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + /* Need to disable SOF interrupt immediately */ + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + + dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", + dwc2_is_host_mode(hsotg) ? "Host" : "Device"); +@@ -297,7 +297,7 @@ static void dwc2_handle_conn_id_status_c + } + + /* Clear interrupt */ +- writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); + } + + /** +@@ -316,7 +316,7 @@ static void dwc2_handle_session_req_intr + dev_dbg(hsotg->dev, "++Session Request Interrupt++\n"); + + /* Clear interrupt */ +- writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); + + /* + * Report disconnect if there is any previous session established +@@ -338,23 +338,23 @@ static void dwc2_handle_wakeup_detected_ + dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); + + if (dwc2_is_device_mode(hsotg)) { +- dev_dbg(hsotg->dev, "DSTS=0x%0x\n", readl(hsotg->regs + DSTS)); ++ dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dwc2_readl(hsotg->regs + DSTS)); + if (hsotg->lx_state == DWC2_L2) { +- u32 dctl = readl(hsotg->regs + DCTL); ++ u32 dctl = dwc2_readl(hsotg->regs + DCTL); + + /* Clear Remote Wakeup Signaling */ + dctl &= ~DCTL_RMTWKUPSIG; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + /* Change to L0 state */ + hsotg->lx_state = DWC2_L0; + } else { + if (hsotg->lx_state != DWC2_L1) { +- u32 pcgcctl = readl(hsotg->regs + PCGCTL); ++ u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + + /* Restart the Phy Clock */ + pcgcctl &= ~PCGCTL_STOPPCLK; +- writel(pcgcctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + mod_timer(&hsotg->wkp_timer, + jiffies + msecs_to_jiffies(71)); + } else { +@@ -364,7 +364,7 @@ static void dwc2_handle_wakeup_detected_ + } + + /* Clear interrupt */ +- writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); + } + + /* +@@ -383,7 +383,7 @@ static void dwc2_handle_disconnect_intr( + /* Change to L3 (OFF) state */ + hsotg->lx_state = DWC2_L3; + +- writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); + } + + /* +@@ -405,7 +405,7 @@ static void dwc2_handle_usb_suspend_intr + * Check the Device status register to determine if the Suspend + * state is active + */ +- dsts = readl(hsotg->regs + DSTS); ++ dsts = dwc2_readl(hsotg->regs + DSTS); + dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); + dev_dbg(hsotg->dev, + "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", +@@ -427,7 +427,7 @@ static void dwc2_handle_usb_suspend_intr + hsotg->lx_state = DWC2_L2; + + /* Clear interrupt */ +- writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); + } + + #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ +@@ -445,9 +445,9 @@ static u32 dwc2_read_common_intr(struct + u32 gahbcfg; + u32 gintmsk_common = GINTMSK_COMMON; + +- gintsts = readl(hsotg->regs + GINTSTS); +- gintmsk = readl(hsotg->regs + GINTMSK); +- gahbcfg = readl(hsotg->regs + GAHBCFG); ++ gintsts = dwc2_readl(hsotg->regs + GINTSTS); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); ++ gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + /* If any common interrupts set */ + if (gintsts & gintmsk_common) +--- a/drivers/usb/dwc2/gadget.c ++++ b/drivers/usb/dwc2/gadget.c +@@ -58,12 +58,12 @@ static inline struct dwc2_hsotg *to_hsot + + static inline void __orr32(void __iomem *ptr, u32 val) + { +- writel(readl(ptr) | val, ptr); ++ dwc2_writel(dwc2_readl(ptr) | val, ptr); + } + + static inline void __bic32(void __iomem *ptr, u32 val) + { +- writel(readl(ptr) & ~val, ptr); ++ dwc2_writel(dwc2_readl(ptr) & ~val, ptr); + } + + static inline struct s3c_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, +@@ -109,14 +109,14 @@ static inline bool using_dma(struct dwc2 + */ + static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) + { +- u32 gsintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 new_gsintmsk; + + new_gsintmsk = gsintmsk | ints; + + if (new_gsintmsk != gsintmsk) { + dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); +- writel(new_gsintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); + } + } + +@@ -127,13 +127,13 @@ static void s3c_hsotg_en_gsint(struct dw + */ + static void s3c_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) + { +- u32 gsintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 new_gsintmsk; + + new_gsintmsk = gsintmsk & ~ints; + + if (new_gsintmsk != gsintmsk) +- writel(new_gsintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); + } + + /** +@@ -158,12 +158,12 @@ static void s3c_hsotg_ctrl_epint(struct + bit <<= 16; + + local_irq_save(flags); +- daint = readl(hsotg->regs + DAINTMSK); ++ daint = dwc2_readl(hsotg->regs + DAINTMSK); + if (en) + daint |= bit; + else + daint &= ~bit; +- writel(daint, hsotg->regs + DAINTMSK); ++ dwc2_writel(daint, hsotg->regs + DAINTMSK); + local_irq_restore(flags); + } + +@@ -183,8 +183,8 @@ static void s3c_hsotg_init_fifo(struct d + hsotg->fifo_map = 0; + + /* set RX/NPTX FIFO sizes */ +- writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); +- writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | ++ dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ); ++ dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) | + (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT), + hsotg->regs + GNPTXFSIZ); + +@@ -212,7 +212,7 @@ static void s3c_hsotg_init_fifo(struct d + "insufficient fifo memory"); + addr += hsotg->g_tx_fifo_sz[ep]; + +- writel(val, hsotg->regs + DPTXFSIZN(ep)); ++ dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); + } + + /* +@@ -220,13 +220,13 @@ static void s3c_hsotg_init_fifo(struct d + * all fifos are flushed before continuing + */ + +- writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | ++ dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | + GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); + + /* wait until the fifos are both flushed */ + timeout = 100; + while (1) { +- val = readl(hsotg->regs + GRSTCTL); ++ val = dwc2_readl(hsotg->regs + GRSTCTL); + + if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) + break; +@@ -319,7 +319,7 @@ static int s3c_hsotg_write_fifo(struct d + struct s3c_hsotg_req *hs_req) + { + bool periodic = is_ep_periodic(hs_ep); +- u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); ++ u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + int buf_pos = hs_req->req.actual; + int to_write = hs_ep->size_loaded; + void *data; +@@ -334,7 +334,7 @@ static int s3c_hsotg_write_fifo(struct d + return 0; + + if (periodic && !hsotg->dedicated_fifos) { +- u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); ++ u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); + int size_left; + int size_done; + +@@ -375,7 +375,7 @@ static int s3c_hsotg_write_fifo(struct d + return -ENOSPC; + } + } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { +- can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); ++ can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index)); + + can_write &= 0xffff; + can_write *= 4; +@@ -552,11 +552,11 @@ static void s3c_hsotg_start_req(struct d + epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", +- __func__, readl(hsotg->regs + epctrl_reg), index, ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, + hs_ep->dir_in ? "in" : "out"); + + /* If endpoint is stalled, we will restart request later */ +- ctrl = readl(hsotg->regs + epctrl_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctrl_reg); + + if (ctrl & DXEPCTL_STALL) { + dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); +@@ -620,7 +620,7 @@ static void s3c_hsotg_start_req(struct d + hs_ep->req = hs_req; + + /* write size / packets */ +- writel(epsize, hsotg->regs + epsize_reg); ++ dwc2_writel(epsize, hsotg->regs + epsize_reg); + + if (using_dma(hsotg) && !continuing) { + unsigned int dma_reg; +@@ -631,7 +631,7 @@ static void s3c_hsotg_start_req(struct d + */ + + dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); +- writel(ureq->dma, hsotg->regs + dma_reg); ++ dwc2_writel(ureq->dma, hsotg->regs + dma_reg); + + dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", + __func__, &ureq->dma, dma_reg); +@@ -647,7 +647,7 @@ static void s3c_hsotg_start_req(struct d + ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); +- writel(ctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctrl_reg); + + /* + * set these, it seems that DMA support increments past the end +@@ -669,7 +669,7 @@ static void s3c_hsotg_start_req(struct d + * to debugging to see what is going on. + */ + if (dir_in) +- writel(DIEPMSK_INTKNTXFEMPMSK, ++ dwc2_writel(DIEPMSK_INTKNTXFEMPMSK, + hsotg->regs + DIEPINT(index)); + + /* +@@ -678,13 +678,13 @@ static void s3c_hsotg_start_req(struct d + */ + + /* check ep is enabled */ +- if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) ++ if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) + dev_dbg(hsotg->dev, + "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", +- index, readl(hsotg->regs + epctrl_reg)); ++ index, dwc2_readl(hsotg->regs + epctrl_reg)); + + dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", +- __func__, readl(hsotg->regs + epctrl_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg)); + + /* enable ep interrupts */ + s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); +@@ -896,7 +896,7 @@ static struct s3c_hsotg_ep *ep_from_wind + */ + static int s3c_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) + { +- int dctl = readl(hsotg->regs + DCTL); ++ int dctl = dwc2_readl(hsotg->regs + DCTL); + + dctl &= ~DCTL_TSTCTL_MASK; + switch (testmode) { +@@ -910,7 +910,7 @@ static int s3c_hsotg_set_test_mode(struc + default: + return -EINVAL; + } +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + return 0; + } + +@@ -1169,14 +1169,14 @@ static void s3c_hsotg_stall_ep0(struct d + * taken effect, so no need to clear later. + */ + +- ctrl = readl(hsotg->regs + reg); ++ ctrl = dwc2_readl(hsotg->regs + reg); + ctrl |= DXEPCTL_STALL; + ctrl |= DXEPCTL_CNAK; +- writel(ctrl, hsotg->regs + reg); ++ dwc2_writel(ctrl, hsotg->regs + reg); + + dev_dbg(hsotg->dev, + "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", +- ctrl, reg, readl(hsotg->regs + reg)); ++ ctrl, reg, dwc2_readl(hsotg->regs + reg)); + + /* + * complete won't be called, so we enqueue +@@ -1220,11 +1220,11 @@ static void s3c_hsotg_process_control(st + switch (ctrl->bRequest) { + case USB_REQ_SET_ADDRESS: + hsotg->connected = 1; +- dcfg = readl(hsotg->regs + DCFG); ++ dcfg = dwc2_readl(hsotg->regs + DCFG); + dcfg &= ~DCFG_DEVADDR_MASK; + dcfg |= (le16_to_cpu(ctrl->wValue) << + DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; +- writel(dcfg, hsotg->regs + DCFG); ++ dwc2_writel(dcfg, hsotg->regs + DCFG); + + dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); + +@@ -1342,15 +1342,15 @@ static void s3c_hsotg_program_zlp(struct + dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n", + index); + +- writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | ++ dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(0), hsotg->regs + + epsiz_reg); + +- ctrl = readl(hsotg->regs + epctl_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctl_reg); + ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ + ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ + ctrl |= DXEPCTL_USBACTEP; +- writel(ctrl, hsotg->regs + epctl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctl_reg); + } + + /** +@@ -1444,7 +1444,7 @@ static void s3c_hsotg_rx_data(struct dwc + + + if (!hs_req) { +- u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); ++ u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); + int ptr; + + dev_dbg(hsotg->dev, +@@ -1453,7 +1453,7 @@ static void s3c_hsotg_rx_data(struct dwc + + /* dump the data from the FIFO, we've nothing we can do */ + for (ptr = 0; ptr < size; ptr += 4) +- (void)readl(fifo); ++ (void)dwc2_readl(fifo); + + return; + } +@@ -1518,7 +1518,7 @@ static void s3c_hsotg_ep0_zlp(struct dwc + */ + static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) + { +- u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); ++ u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); + struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; + struct s3c_hsotg_req *hs_req = hs_ep->req; + struct usb_request *req = &hs_req->req; +@@ -1590,7 +1590,7 @@ static u32 s3c_hsotg_read_frameno(struct + { + u32 dsts; + +- dsts = readl(hsotg->regs + DSTS); ++ dsts = dwc2_readl(hsotg->regs + DSTS); + dsts &= DSTS_SOFFN_MASK; + dsts >>= DSTS_SOFFN_SHIFT; + +@@ -1615,7 +1615,7 @@ static u32 s3c_hsotg_read_frameno(struct + */ + static void s3c_hsotg_handle_rx(struct dwc2_hsotg *hsotg) + { +- u32 grxstsr = readl(hsotg->regs + GRXSTSP); ++ u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); + u32 epnum, status, size; + + WARN_ON(using_dma(hsotg)); +@@ -1646,7 +1646,7 @@ static void s3c_hsotg_handle_rx(struct d + dev_dbg(hsotg->dev, + "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", + s3c_hsotg_read_frameno(hsotg), +- readl(hsotg->regs + DOEPCTL(0))); ++ dwc2_readl(hsotg->regs + DOEPCTL(0))); + /* + * Call s3c_hsotg_handle_outdone here if it was not called from + * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't +@@ -1664,7 +1664,7 @@ static void s3c_hsotg_handle_rx(struct d + dev_dbg(hsotg->dev, + "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", + s3c_hsotg_read_frameno(hsotg), +- readl(hsotg->regs + DOEPCTL(0))); ++ dwc2_readl(hsotg->regs + DOEPCTL(0))); + + WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); + +@@ -1743,15 +1743,15 @@ static void s3c_hsotg_set_ep_maxpacket(s + } + + if (dir_in) { +- reg = readl(regs + DIEPCTL(ep)); ++ reg = dwc2_readl(regs + DIEPCTL(ep)); + reg &= ~DXEPCTL_MPS_MASK; + reg |= mpsval; +- writel(reg, regs + DIEPCTL(ep)); ++ dwc2_writel(reg, regs + DIEPCTL(ep)); + } else { +- reg = readl(regs + DOEPCTL(ep)); ++ reg = dwc2_readl(regs + DOEPCTL(ep)); + reg &= ~DXEPCTL_MPS_MASK; + reg |= mpsval; +- writel(reg, regs + DOEPCTL(ep)); ++ dwc2_writel(reg, regs + DOEPCTL(ep)); + } + + return; +@@ -1770,14 +1770,14 @@ static void s3c_hsotg_txfifo_flush(struc + int timeout; + int val; + +- writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, ++ dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, + hsotg->regs + GRSTCTL); + + /* wait until the fifo is flushed */ + timeout = 100; + + while (1) { +- val = readl(hsotg->regs + GRSTCTL); ++ val = dwc2_readl(hsotg->regs + GRSTCTL); + + if ((val & (GRSTCTL_TXFFLSH)) == 0) + break; +@@ -1838,7 +1838,7 @@ static void s3c_hsotg_complete_in(struct + struct s3c_hsotg_ep *hs_ep) + { + struct s3c_hsotg_req *hs_req = hs_ep->req; +- u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); ++ u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); + int size_left, size_done; + + if (!hs_req) { +@@ -1929,11 +1929,11 @@ static void s3c_hsotg_epint(struct dwc2_ + u32 ints; + u32 ctrl; + +- ints = readl(hsotg->regs + epint_reg); +- ctrl = readl(hsotg->regs + epctl_reg); ++ ints = dwc2_readl(hsotg->regs + epint_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctl_reg); + + /* Clear endpoint interrupts */ +- writel(ints, hsotg->regs + epint_reg); ++ dwc2_writel(ints, hsotg->regs + epint_reg); + + if (!hs_ep) { + dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", +@@ -1954,13 +1954,13 @@ static void s3c_hsotg_epint(struct dwc2_ + ctrl |= DXEPCTL_SETEVENFR; + else + ctrl |= DXEPCTL_SETODDFR; +- writel(ctrl, hsotg->regs + epctl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctl_reg); + } + + dev_dbg(hsotg->dev, + "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", +- __func__, readl(hsotg->regs + epctl_reg), +- readl(hsotg->regs + epsiz_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctl_reg), ++ dwc2_readl(hsotg->regs + epsiz_reg)); + + /* + * we get OutDone from the FIFO, so we only need to look +@@ -1985,16 +1985,16 @@ static void s3c_hsotg_epint(struct dwc2_ + dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); + + if (dir_in) { +- int epctl = readl(hsotg->regs + epctl_reg); ++ int epctl = dwc2_readl(hsotg->regs + epctl_reg); + + s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); + + if ((epctl & DXEPCTL_STALL) && + (epctl & DXEPCTL_EPTYPE_BULK)) { +- int dctl = readl(hsotg->regs + DCTL); ++ int dctl = dwc2_readl(hsotg->regs + DCTL); + + dctl |= DCTL_CGNPINNAK; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + } + } +@@ -2056,7 +2056,7 @@ static void s3c_hsotg_epint(struct dwc2_ + */ + static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) + { +- u32 dsts = readl(hsotg->regs + DSTS); ++ u32 dsts = dwc2_readl(hsotg->regs + DSTS); + int ep0_mps = 0, ep_mps = 8; + + /* +@@ -2123,8 +2123,8 @@ static void s3c_hsotg_irq_enumdone(struc + s3c_hsotg_enqueue_setup(hsotg); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + } + + /** +@@ -2151,7 +2151,7 @@ static void kill_all_requests(struct dwc + + if (!hsotg->dedicated_fifos) + return; +- size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; ++ size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; + if (size < ep->fifo_size) + s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index); + } +@@ -2236,11 +2236,11 @@ static int s3c_hsotg_corereset(struct dw + dev_dbg(hsotg->dev, "resetting core\n"); + + /* issue soft reset */ +- writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); ++ dwc2_writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); + + timeout = 10000; + do { +- grstctl = readl(hsotg->regs + GRSTCTL); ++ grstctl = dwc2_readl(hsotg->regs + GRSTCTL); + } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); + + if (grstctl & GRSTCTL_CSFTRST) { +@@ -2251,7 +2251,7 @@ static int s3c_hsotg_corereset(struct dw + timeout = 10000; + + while (1) { +- u32 grstctl = readl(hsotg->regs + GRSTCTL); ++ u32 grstctl = dwc2_readl(hsotg->regs + GRSTCTL); + + if (timeout-- < 0) { + dev_info(hsotg->dev, +@@ -2291,7 +2291,7 @@ void s3c_hsotg_core_init_disconnected(st + + /* set the PLL on, remove the HNP/SRP and set the PHY */ + val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; +- writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | ++ dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | + (val << GUSBCFG_USBTRDTIM_SHIFT), hsotg->regs + GUSBCFG); + + s3c_hsotg_init_fifo(hsotg); +@@ -2299,15 +2299,15 @@ void s3c_hsotg_core_init_disconnected(st + if (!is_usb_reset) + __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); + +- writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); ++ dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG); + + /* Clear any pending OTG interrupts */ +- writel(0xffffffff, hsotg->regs + GOTGINT); ++ dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + + /* Clear any pending interrupts */ +- writel(0xffffffff, hsotg->regs + GINTSTS); ++ dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + +- writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | ++ dwc2_writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | + GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | + GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | + GINTSTS_ENUMDONE | GINTSTS_OTGINT | +@@ -2315,11 +2315,11 @@ void s3c_hsotg_core_init_disconnected(st + hsotg->regs + GINTMSK); + + if (using_dma(hsotg)) +- writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | ++ dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | + (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT), + hsotg->regs + GAHBCFG); + else +- writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | ++ dwc2_writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | + GAHBCFG_P_TXF_EMP_LVL) : 0) | + GAHBCFG_GLBL_INTR_EN, + hsotg->regs + GAHBCFG); +@@ -2330,7 +2330,7 @@ void s3c_hsotg_core_init_disconnected(st + * interrupts. + */ + +- writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? ++ dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? + DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | + DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | + DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | +@@ -2341,17 +2341,17 @@ void s3c_hsotg_core_init_disconnected(st + * don't need XferCompl, we get that from RXFIFO in slave mode. In + * DMA mode we may need this. + */ +- writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | ++ dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | + DIEPMSK_TIMEOUTMSK) : 0) | + DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | + DOEPMSK_SETUPMSK, + hsotg->regs + DOEPMSK); + +- writel(0, hsotg->regs + DAINTMSK); ++ dwc2_writel(0, hsotg->regs + DAINTMSK); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + + /* enable in and out endpoint interrupts */ + s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); +@@ -2374,7 +2374,7 @@ void s3c_hsotg_core_init_disconnected(st + __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); + } + +- dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); ++ dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); + + /* + * DxEPCTL_USBActEp says RO in manual, but seems to be set by +@@ -2382,23 +2382,23 @@ void s3c_hsotg_core_init_disconnected(st + */ + + /* set to read 1 8byte packet */ +- writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | ++ dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); + +- writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | ++ dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | + DXEPCTL_CNAK | DXEPCTL_EPENA | + DXEPCTL_USBACTEP, + hsotg->regs + DOEPCTL0); + + /* enable, but don't activate EP0in */ +- writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | ++ dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | + DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); + + s3c_hsotg_enqueue_setup(hsotg); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + + /* clear global NAKs */ + val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; +@@ -2438,8 +2438,8 @@ static irqreturn_t s3c_hsotg_irq(int irq + + spin_lock(&hsotg->lock); + irq_retry: +- gintsts = readl(hsotg->regs + GINTSTS); +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintsts = dwc2_readl(hsotg->regs + GINTSTS); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", + __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); +@@ -2447,14 +2447,14 @@ irq_retry: + gintsts &= gintmsk; + + if (gintsts & GINTSTS_ENUMDONE) { +- writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); + + s3c_hsotg_irq_enumdone(hsotg); + } + + if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { +- u32 daint = readl(hsotg->regs + DAINT); +- u32 daintmsk = readl(hsotg->regs + DAINTMSK); ++ u32 daint = dwc2_readl(hsotg->regs + DAINT); ++ u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); + u32 daint_out, daint_in; + int ep; + +@@ -2479,13 +2479,13 @@ irq_retry: + + if (gintsts & GINTSTS_USBRST) { + +- u32 usb_status = readl(hsotg->regs + GOTGCTL); ++ u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); + + dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); + dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", +- readl(hsotg->regs + GNPTXSTS)); ++ dwc2_readl(hsotg->regs + GNPTXSTS)); + +- writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); + + /* Report disconnection if it is not already done. */ + s3c_hsotg_disconnect(hsotg); +@@ -2538,7 +2538,7 @@ irq_retry: + + if (gintsts & GINTSTS_ERLYSUSP) { + dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); +- writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); + } + + /* +@@ -2550,7 +2550,7 @@ irq_retry: + if (gintsts & GINTSTS_GOUTNAKEFF) { + dev_info(hsotg->dev, "GOUTNakEff triggered\n"); + +- writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); ++ dwc2_writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); + + s3c_hsotg_dump(hsotg); + } +@@ -2558,7 +2558,7 @@ irq_retry: + if (gintsts & GINTSTS_GINNAKEFF) { + dev_info(hsotg->dev, "GINNakEff triggered\n"); + +- writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); ++ dwc2_writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); + + s3c_hsotg_dump(hsotg); + } +@@ -2616,7 +2616,7 @@ static int s3c_hsotg_ep_enable(struct us + /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ + + epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); +- epctrl = readl(hsotg->regs + epctrl_reg); ++ epctrl = dwc2_readl(hsotg->regs + epctrl_reg); + + dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", + __func__, epctrl, epctrl_reg); +@@ -2700,7 +2700,7 @@ static int s3c_hsotg_ep_enable(struct us + for (i = 1; i < hsotg->num_of_eps; ++i) { + if (hsotg->fifo_map & (1<regs + DPTXFSIZN(i)); ++ val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); + val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; + if (val < size) + continue; +@@ -2729,9 +2729,9 @@ static int s3c_hsotg_ep_enable(struct us + dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", + __func__, epctrl); + +- writel(epctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(epctrl, hsotg->regs + epctrl_reg); + dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", +- __func__, readl(hsotg->regs + epctrl_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg)); + + /* enable the endpoint interrupt */ + s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); +@@ -2770,13 +2770,13 @@ static int s3c_hsotg_ep_disable_force(st + hs_ep->fifo_index = 0; + hs_ep->fifo_size = 0; + +- ctrl = readl(hsotg->regs + epctrl_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctrl_reg); + ctrl &= ~DXEPCTL_EPENA; + ctrl &= ~DXEPCTL_USBACTEP; + ctrl |= DXEPCTL_SNAK; + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); +- writel(ctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctrl_reg); + + /* disable endpoint interrupts */ + s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); +@@ -2863,7 +2863,7 @@ static int s3c_hsotg_ep_sethalt(struct u + + if (hs_ep->dir_in) { + epreg = DIEPCTL(index); +- epctl = readl(hs->regs + epreg); ++ epctl = dwc2_readl(hs->regs + epreg); + + if (value) { + epctl |= DXEPCTL_STALL + DXEPCTL_SNAK; +@@ -2876,11 +2876,11 @@ static int s3c_hsotg_ep_sethalt(struct u + xfertype == DXEPCTL_EPTYPE_INTERRUPT) + epctl |= DXEPCTL_SETD0PID; + } +- writel(epctl, hs->regs + epreg); ++ dwc2_writel(epctl, hs->regs + epreg); + } else { + + epreg = DOEPCTL(index); +- epctl = readl(hs->regs + epreg); ++ epctl = dwc2_readl(hs->regs + epreg); + + if (value) + epctl |= DXEPCTL_STALL; +@@ -2891,7 +2891,7 @@ static int s3c_hsotg_ep_sethalt(struct u + xfertype == DXEPCTL_EPTYPE_INTERRUPT) + epctl |= DXEPCTL_SETD0PID; + } +- writel(epctl, hs->regs + epreg); ++ dwc2_writel(epctl, hs->regs + epreg); + } + + hs_ep->halted = value; +@@ -2982,15 +2982,15 @@ static void s3c_hsotg_init(struct dwc2_h + u32 trdtim; + /* unmask subset of endpoint interrupts */ + +- writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | ++ dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | + DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, + hsotg->regs + DIEPMSK); + +- writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | ++ dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | + DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, + hsotg->regs + DOEPMSK); + +- writel(0, hsotg->regs + DAINTMSK); ++ dwc2_writel(0, hsotg->regs + DAINTMSK); + + /* Be in disconnected state until gadget is registered */ + __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); +@@ -2998,14 +2998,14 @@ static void s3c_hsotg_init(struct dwc2_h + /* setup fifos */ + + dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", +- readl(hsotg->regs + GRXFSIZ), +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GRXFSIZ), ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + + s3c_hsotg_init_fifo(hsotg); + + /* set the PLL on, remove the HNP/SRP and set the PHY */ + trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; +- writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | ++ dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | + (trdtim << GUSBCFG_USBTRDTIM_SHIFT), + hsotg->regs + GUSBCFG); + +@@ -3275,9 +3275,9 @@ static void s3c_hsotg_initep(struct dwc2 + if (using_dma(hsotg)) { + u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); + if (dir_in) +- writel(next, hsotg->regs + DIEPCTL(epnum)); ++ dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); + else +- writel(next, hsotg->regs + DOEPCTL(epnum)); ++ dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); + } + } + +@@ -3295,7 +3295,7 @@ static int s3c_hsotg_hw_cfg(struct dwc2_ + + /* check hardware configuration */ + +- cfg = readl(hsotg->regs + GHWCFG2); ++ cfg = dwc2_readl(hsotg->regs + GHWCFG2); + hsotg->num_of_eps = (cfg >> GHWCFG2_NUM_DEV_EP_SHIFT) & 0xF; + /* Add ep0 */ + hsotg->num_of_eps++; +@@ -3307,7 +3307,7 @@ static int s3c_hsotg_hw_cfg(struct dwc2_ + /* Same s3c_hsotg_ep is used in both directions for ep0 */ + hsotg->eps_out[0] = hsotg->eps_in[0]; + +- cfg = readl(hsotg->regs + GHWCFG1); ++ cfg = dwc2_readl(hsotg->regs + GHWCFG1); + for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) { + ep_type = cfg & 3; + /* Direction in or both */ +@@ -3326,10 +3326,10 @@ static int s3c_hsotg_hw_cfg(struct dwc2_ + } + } + +- cfg = readl(hsotg->regs + GHWCFG3); ++ cfg = dwc2_readl(hsotg->regs + GHWCFG3); + hsotg->fifo_mem = (cfg >> GHWCFG3_DFIFO_DEPTH_SHIFT); + +- cfg = readl(hsotg->regs + GHWCFG4); ++ cfg = dwc2_readl(hsotg->regs + GHWCFG4); + hsotg->dedicated_fifos = (cfg >> GHWCFG4_DED_FIFO_SHIFT) & 1; + + dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", +@@ -3352,19 +3352,19 @@ static void s3c_hsotg_dump(struct dwc2_h + int idx; + + dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", +- readl(regs + DCFG), readl(regs + DCTL), +- readl(regs + DIEPMSK)); ++ dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), ++ dwc2_readl(regs + DIEPMSK)); + + dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", +- readl(regs + GAHBCFG), readl(regs + GHWCFG1)); ++ dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); + + dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", +- readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); ++ dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); + + /* show periodic fifo settings */ + + for (idx = 1; idx < hsotg->num_of_eps; idx++) { +- val = readl(regs + DPTXFSIZN(idx)); ++ val = dwc2_readl(regs + DPTXFSIZN(idx)); + dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, + val >> FIFOSIZE_DEPTH_SHIFT, + val & FIFOSIZE_STARTADDR_MASK); +@@ -3373,21 +3373,21 @@ static void s3c_hsotg_dump(struct dwc2_h + for (idx = 0; idx < hsotg->num_of_eps; idx++) { + dev_info(dev, + "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, +- readl(regs + DIEPCTL(idx)), +- readl(regs + DIEPTSIZ(idx)), +- readl(regs + DIEPDMA(idx))); ++ dwc2_readl(regs + DIEPCTL(idx)), ++ dwc2_readl(regs + DIEPTSIZ(idx)), ++ dwc2_readl(regs + DIEPDMA(idx))); + +- val = readl(regs + DOEPCTL(idx)); ++ val = dwc2_readl(regs + DOEPCTL(idx)); + dev_info(dev, + "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", +- idx, readl(regs + DOEPCTL(idx)), +- readl(regs + DOEPTSIZ(idx)), +- readl(regs + DOEPDMA(idx))); ++ idx, dwc2_readl(regs + DOEPCTL(idx)), ++ dwc2_readl(regs + DOEPTSIZ(idx)), ++ dwc2_readl(regs + DOEPDMA(idx))); + + } + + dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", +- readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); ++ dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); + #endif + } + +@@ -3443,7 +3443,7 @@ static int testmode_show(struct seq_file + int dctl; + + spin_lock_irqsave(&hsotg->lock, flags); +- dctl = readl(hsotg->regs + DCTL); ++ dctl = dwc2_readl(hsotg->regs + DCTL); + dctl &= DCTL_TSTCTL_MASK; + dctl >>= DCTL_TSTCTL_SHIFT; + spin_unlock_irqrestore(&hsotg->lock, flags); +@@ -3504,38 +3504,38 @@ static int state_show(struct seq_file *s + int idx; + + seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", +- readl(regs + DCFG), +- readl(regs + DCTL), +- readl(regs + DSTS)); ++ dwc2_readl(regs + DCFG), ++ dwc2_readl(regs + DCTL), ++ dwc2_readl(regs + DSTS)); + + seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", +- readl(regs + DIEPMSK), readl(regs + DOEPMSK)); ++ dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK)); + + seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", +- readl(regs + GINTMSK), +- readl(regs + GINTSTS)); ++ dwc2_readl(regs + GINTMSK), ++ dwc2_readl(regs + GINTSTS)); + + seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", +- readl(regs + DAINTMSK), +- readl(regs + DAINT)); ++ dwc2_readl(regs + DAINTMSK), ++ dwc2_readl(regs + DAINT)); + + seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", +- readl(regs + GNPTXSTS), +- readl(regs + GRXSTSR)); ++ dwc2_readl(regs + GNPTXSTS), ++ dwc2_readl(regs + GRXSTSR)); + + seq_puts(seq, "\nEndpoint status:\n"); + + for (idx = 0; idx < hsotg->num_of_eps; idx++) { + u32 in, out; + +- in = readl(regs + DIEPCTL(idx)); +- out = readl(regs + DOEPCTL(idx)); ++ in = dwc2_readl(regs + DIEPCTL(idx)); ++ out = dwc2_readl(regs + DOEPCTL(idx)); + + seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", + idx, in, out); + +- in = readl(regs + DIEPTSIZ(idx)); +- out = readl(regs + DOEPTSIZ(idx)); ++ in = dwc2_readl(regs + DIEPTSIZ(idx)); ++ out = dwc2_readl(regs + DOEPTSIZ(idx)); + + seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", + in, out); +@@ -3575,9 +3575,9 @@ static int fifo_show(struct seq_file *se + int idx; + + seq_puts(seq, "Non-periodic FIFOs:\n"); +- seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); ++ seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ)); + +- val = readl(regs + GNPTXFSIZ); ++ val = dwc2_readl(regs + GNPTXFSIZ); + seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", + val >> FIFOSIZE_DEPTH_SHIFT, + val & FIFOSIZE_DEPTH_MASK); +@@ -3585,7 +3585,7 @@ static int fifo_show(struct seq_file *se + seq_puts(seq, "\nPeriodic TXFIFOs:\n"); + + for (idx = 1; idx < hsotg->num_of_eps; idx++) { +- val = readl(regs + DPTXFSIZN(idx)); ++ val = dwc2_readl(regs + DPTXFSIZN(idx)); + + seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, + val >> FIFOSIZE_DEPTH_SHIFT, +@@ -3638,20 +3638,20 @@ static int ep_show(struct seq_file *seq, + /* first show the register state */ + + seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", +- readl(regs + DIEPCTL(index)), +- readl(regs + DOEPCTL(index))); ++ dwc2_readl(regs + DIEPCTL(index)), ++ dwc2_readl(regs + DOEPCTL(index))); + + seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", +- readl(regs + DIEPDMA(index)), +- readl(regs + DOEPDMA(index))); ++ dwc2_readl(regs + DIEPDMA(index)), ++ dwc2_readl(regs + DOEPDMA(index))); + + seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", +- readl(regs + DIEPINT(index)), +- readl(regs + DOEPINT(index))); ++ dwc2_readl(regs + DIEPINT(index)), ++ dwc2_readl(regs + DOEPINT(index))); + + seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", +- readl(regs + DIEPTSIZ(index)), +- readl(regs + DOEPTSIZ(index))); ++ dwc2_readl(regs + DIEPTSIZ(index)), ++ dwc2_readl(regs + DOEPTSIZ(index))); + + seq_puts(seq, "\n"); + seq_printf(seq, "mps %d\n", ep->ep.maxpacket); +--- a/drivers/usb/dwc2/hcd.c ++++ b/drivers/usb/dwc2/hcd.c +@@ -80,10 +80,10 @@ static void dwc2_dump_channel_info(struc + if (chan == NULL) + return; + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); +- hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num)); +- hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); ++ hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); + + dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); + dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", +@@ -207,7 +207,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *h + */ + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, +@@ -228,11 +228,11 @@ static void dwc2_hcd_cleanup_channels(st + channel = hsotg->hc_ptr_array[i]; + if (!list_empty(&channel->hc_list_entry)) + continue; +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); + hcchar |= HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + } + } +@@ -241,11 +241,11 @@ static void dwc2_hcd_cleanup_channels(st + channel = hsotg->hc_ptr_array[i]; + if (!list_empty(&channel->hc_list_entry)) + continue; +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + /* Halt the channel */ + hcchar |= HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + + dwc2_hc_cleanup(hsotg, channel); +@@ -287,11 +287,11 @@ void dwc2_hcd_disconnect(struct dwc2_hso + * interrupt mask and status bits and disabling subsequent host + * channel interrupts. + */ +- intr = readl(hsotg->regs + GINTMSK); ++ intr = dwc2_readl(hsotg->regs + GINTMSK); + intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); +- writel(intr, hsotg->regs + GINTMSK); ++ dwc2_writel(intr, hsotg->regs + GINTMSK); + intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; +- writel(intr, hsotg->regs + GINTSTS); ++ dwc2_writel(intr, hsotg->regs + GINTSTS); + + /* + * Turn off the vbus power only if the core has transitioned to device +@@ -301,7 +301,7 @@ void dwc2_hcd_disconnect(struct dwc2_hso + if (dwc2_is_device_mode(hsotg)) { + if (hsotg->op_state != OTG_STATE_A_SUSPEND) { + dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); +- writel(0, hsotg->regs + HPRT0); ++ dwc2_writel(0, hsotg->regs + HPRT0); + } + + dwc2_disable_host_interrupts(hsotg); +@@ -354,7 +354,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hs + + /* Turn off the vbus power */ + dev_dbg(hsotg->dev, "PortPower off\n"); +- writel(0, hsotg->regs + HPRT0); ++ dwc2_writel(0, hsotg->regs + HPRT0); + } + + static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, +@@ -379,7 +379,7 @@ static int dwc2_hcd_urb_enqueue(struct d + if ((dev_speed == USB_SPEED_LOW) && + (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && + (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + + if (prtspd == HPRT0_SPD_FULL_SPEED) +@@ -401,7 +401,7 @@ static int dwc2_hcd_urb_enqueue(struct d + return retval; + } + +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + if (!(intr_mask & GINTSTS_SOF)) { + enum dwc2_transaction_type tr_type; + +@@ -1069,7 +1069,7 @@ static void dwc2_process_periodic_channe + if (dbg_perio()) + dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); + +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1084,7 +1084,7 @@ static void dwc2_process_periodic_channe + + qh_ptr = hsotg->periodic_sched_assigned.next; + while (qh_ptr != &hsotg->periodic_sched_assigned) { +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + if (qspcavail == 0) { +@@ -1144,7 +1144,7 @@ static void dwc2_process_periodic_channe + } + + if (hsotg->core_params->dma_enable <= 0) { +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1167,9 +1167,9 @@ static void dwc2_process_periodic_channe + * level to ensure that new requests are loaded as + * soon as possible.) + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are +@@ -1178,9 +1178,9 @@ static void dwc2_process_periodic_channe + * handlers to queue more transactions as transfer + * states change. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1209,7 +1209,7 @@ static void dwc2_process_non_periodic_ch + + dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); + +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1232,7 +1232,7 @@ static void dwc2_process_non_periodic_ch + * available in the request queue or the Tx FIFO + */ + do { +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { +@@ -1269,7 +1269,7 @@ next: + } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); + + if (hsotg->core_params->dma_enable <= 0) { +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1289,9 +1289,9 @@ next: + * level to ensure that new requests are loaded as + * soon as possible.) + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are +@@ -1300,9 +1300,9 @@ next: + * handlers to queue more transactions as transfer + * states change. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1340,10 +1340,10 @@ void dwc2_hcd_queue_transactions(struct + * Ensure NP Tx FIFO empty interrupt is disabled when + * there are no non-periodic transfers to process + */ +- u32 gintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + gintmsk &= ~GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1357,7 +1357,7 @@ static void dwc2_conn_id_status_change(s + + dev_dbg(hsotg->dev, "%s()\n", __func__); + +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); + dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", + !!(gotgctl & GOTGCTL_CONID_B)); +@@ -1420,9 +1420,9 @@ static void dwc2_wakeup_detected(unsigne + hprt0 = dwc2_read_hprt0(hsotg); + dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); + hprt0 &= ~HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", +- readl(hsotg->regs + HPRT0)); ++ dwc2_readl(hsotg->regs + HPRT0)); + + dwc2_hcd_rem_wakeup(hsotg); + +@@ -1450,30 +1450,30 @@ static void dwc2_port_suspend(struct dwc + spin_lock_irqsave(&hsotg->lock, flags); + + if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl |= GOTGCTL_HSTSETHNPEN; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + hsotg->op_state = OTG_STATE_A_SUSPEND; + } + + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_SUSP; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + + /* Update lx_state */ + hsotg->lx_state = DWC2_L2; + + /* Suspend the Phy Clock */ +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl |= PCGCTL_STOPPCLK; +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + udelay(10); + + /* For HNP the bus must be suspended for at least 200ms */ + if (dwc2_host_is_b_hnp_enabled(hsotg)) { +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~PCGCTL_STOPPCLK; +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + + spin_unlock_irqrestore(&hsotg->lock, flags); + +@@ -1522,23 +1522,23 @@ static int dwc2_hcd_hub_control(struct d + "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_ENA; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_SUSPEND: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + usleep_range(20000, 40000); + + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hprt0 &= ~HPRT0_SUSP; + msleep(USB_RESUME_TIMEOUT); + + hprt0 &= ~HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_POWER: +@@ -1546,7 +1546,7 @@ static int dwc2_hcd_hub_control(struct d + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 &= ~HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_INDICATOR: +@@ -1667,7 +1667,7 @@ static int dwc2_hcd_hub_control(struct d + break; + } + +- hprt0 = readl(hsotg->regs + HPRT0); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); + + if (hprt0 & HPRT0_CONNSTS) +@@ -1732,18 +1732,18 @@ static int dwc2_hcd_hub_control(struct d + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_RESET: + hprt0 = dwc2_read_hprt0(hsotg); + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_RESET\n"); +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + /* ??? Original driver does this */ +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + + hprt0 = dwc2_read_hprt0(hsotg); + /* Clear suspend bit if resetting from suspend state */ +@@ -1758,13 +1758,13 @@ static int dwc2_hcd_hub_control(struct d + hprt0 |= HPRT0_PWR | HPRT0_RST; + dev_dbg(hsotg->dev, + "In host mode, hprt0=%08x\n", hprt0); +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ + usleep_range(50000, 70000); + hprt0 &= ~HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hsotg->lx_state = DWC2_L0; /* Now back to On state */ + break; + +@@ -1828,7 +1828,7 @@ static int dwc2_hcd_is_status_changed(st + + int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) + { +- u32 hfnum = readl(hsotg->regs + HFNUM); ++ u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); + + #ifdef DWC2_DEBUG_SOF + dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", +@@ -1931,11 +1931,11 @@ void dwc2_hcd_dump_state(struct dwc2_hso + if (chan->xfer_started) { + u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; + +- hfnum = readl(hsotg->regs + HFNUM); +- hcchar = readl(hsotg->regs + HCCHAR(i)); +- hctsiz = readl(hsotg->regs + HCTSIZ(i)); +- hcint = readl(hsotg->regs + HCINT(i)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(i)); ++ hfnum = dwc2_readl(hsotg->regs + HFNUM); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); ++ hcint = dwc2_readl(hsotg->regs + HCINT(i)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); + dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); + dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); + dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); +@@ -1983,12 +1983,12 @@ void dwc2_hcd_dump_state(struct dwc2_hso + dev_dbg(hsotg->dev, " periodic_channels: %d\n", + hsotg->periodic_channels); + dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); +- np_tx_status = readl(hsotg->regs + GNPTXSTS); ++ np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", + (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); + dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", + (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); +- p_tx_status = readl(hsotg->regs + HPTXSTS); ++ p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", + (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); + dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", +@@ -2252,7 +2252,7 @@ static void dwc2_hcd_reset_func(struct w + dev_dbg(hsotg->dev, "USB RESET function called\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 &= ~HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hsotg->flags.b.port_reset_change = 1; + } + +@@ -2729,17 +2729,17 @@ static void dwc2_hcd_free(struct dwc2_hs + hsotg->status_buf = NULL; + } + +- ahbcfg = readl(hsotg->regs + GAHBCFG); ++ ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + /* Disable all interrupts */ + ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); +- writel(0, hsotg->regs + GINTMSK); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(0, hsotg->regs + GINTMSK); + + if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { +- dctl = readl(hsotg->regs + DCTL); ++ dctl = dwc2_readl(hsotg->regs + DCTL); + dctl |= DCTL_SFTDISCON; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + + if (hsotg->wq_otg) { +@@ -2805,7 +2805,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso + + retval = -ENOMEM; + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); + + #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS +--- a/drivers/usb/dwc2/hcd_ddma.c ++++ b/drivers/usb/dwc2/hcd_ddma.c +@@ -169,19 +169,19 @@ static void dwc2_per_sched_enable(struct + + spin_lock_irqsave(&hsotg->lock, flags); + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + if (hcfg & HCFG_PERSCHEDENA) { + /* already enabled */ + spin_unlock_irqrestore(&hsotg->lock, flags); + return; + } + +- writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); ++ dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); + + hcfg &= ~HCFG_FRLISTEN_MASK; + hcfg |= fr_list_en | HCFG_PERSCHEDENA; + dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + + spin_unlock_irqrestore(&hsotg->lock, flags); + } +@@ -193,7 +193,7 @@ static void dwc2_per_sched_disable(struc + + spin_lock_irqsave(&hsotg->lock, flags); + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + if (!(hcfg & HCFG_PERSCHEDENA)) { + /* already disabled */ + spin_unlock_irqrestore(&hsotg->lock, flags); +@@ -202,7 +202,7 @@ static void dwc2_per_sched_disable(struc + + hcfg &= ~HCFG_PERSCHEDENA; + dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + + spin_unlock_irqrestore(&hsotg->lock, flags); + } +--- a/drivers/usb/dwc2/hcd.h ++++ b/drivers/usb/dwc2/hcd.h +@@ -371,10 +371,10 @@ static inline struct usb_hcd *dwc2_hsotg + */ + static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) + { +- u32 mask = readl(hsotg->regs + HCINTMSK(chnum)); ++ u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + + mask &= ~intr; +- writel(mask, hsotg->regs + HCINTMSK(chnum)); ++ dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); + } + + /* +@@ -382,11 +382,11 @@ static inline void disable_hc_int(struct + */ + static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) + { +- return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; ++ return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; + } + static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) + { +- return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; ++ return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; + } + + /* +@@ -395,7 +395,7 @@ static inline int dwc2_is_device_mode(st + */ + static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) + { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); + return hprt0; +@@ -582,7 +582,7 @@ static inline u16 dwc2_micro_frame_num(u + */ + static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) + { +- return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK); ++ return dwc2_readl(hsotg->regs + GINTSTS) & dwc2_readl(hsotg->regs + GINTMSK); + } + + static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) +@@ -734,7 +734,7 @@ do { \ + qtd_list_entry); \ + if (usb_pipeint(_qtd_->urb->pipe) && \ + (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ +- _hfnum_.d32 = readl((_hcd_)->regs + HFNUM); \ ++ _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \ + switch (_hfnum_.b.frnum & 0x7) { \ + case 7: \ + (_hcd_)->hfnum_7_samples_##_letter_++; \ +--- a/drivers/usb/dwc2/hcd_intr.c ++++ b/drivers/usb/dwc2/hcd_intr.c +@@ -148,7 +148,7 @@ static void dwc2_sof_intr(struct dwc2_hs + dwc2_hcd_queue_transactions(hsotg, tr_type); + + /* Clear interrupt */ +- writel(GINTSTS_SOF, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS); + } + + /* +@@ -164,7 +164,7 @@ static void dwc2_rx_fifo_level_intr(stru + if (dbg_perio()) + dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); + +- grxsts = readl(hsotg->regs + GRXSTSP); ++ grxsts = dwc2_readl(hsotg->regs + GRXSTSP); + chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; + chan = hsotg->hc_ptr_array[chnum]; + if (!chan) { +@@ -247,11 +247,11 @@ static void dwc2_hprt0_enable(struct dwc + dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + /* Every time when port enables calculate HFIR.FrInterval */ +- hfir = readl(hsotg->regs + HFIR); ++ hfir = dwc2_readl(hsotg->regs + HFIR); + hfir &= ~HFIR_FRINT_MASK; + hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & + HFIR_FRINT_MASK; +- writel(hfir, hsotg->regs + HFIR); ++ dwc2_writel(hfir, hsotg->regs + HFIR); + + /* Check if we need to adjust the PHY clock speed for low power */ + if (!params->host_support_fs_ls_low_power) { +@@ -260,7 +260,7 @@ static void dwc2_hprt0_enable(struct dwc + return; + } + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + + if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { +@@ -268,11 +268,11 @@ static void dwc2_hprt0_enable(struct dwc + if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { + /* Set PHY low power clock select for FS/LS devices */ + usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + do_reset = 1; + } + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> + HCFG_FSLSPCLKSEL_SHIFT; + +@@ -286,7 +286,7 @@ static void dwc2_hprt0_enable(struct dwc + fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + do_reset = 1; + } + } else { +@@ -297,7 +297,7 @@ static void dwc2_hprt0_enable(struct dwc + fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + do_reset = 1; + } + } +@@ -305,7 +305,7 @@ static void dwc2_hprt0_enable(struct dwc + /* Not low power */ + if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { + usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + do_reset = 1; + } + } +@@ -332,7 +332,7 @@ static void dwc2_port_intr(struct dwc2_h + + dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); + +- hprt0 = readl(hsotg->regs + HPRT0); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0_modify = hprt0; + + /* +@@ -385,7 +385,7 @@ static void dwc2_port_intr(struct dwc2_h + } + + /* Clear Port Interrupts */ +- writel(hprt0_modify, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0_modify, hsotg->regs + HPRT0); + } + + /* +@@ -405,7 +405,7 @@ static u32 dwc2_get_actual_xfer_length(s + { + u32 hctsiz, count, length; + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + + if (halt_status == DWC2_HC_XFER_COMPLETE) { + if (chan->ep_is_in) { +@@ -483,7 +483,7 @@ static int dwc2_update_urb_state(struct + urb->status = 0; + } + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", + __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); + dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); +@@ -506,7 +506,7 @@ void dwc2_hcd_save_data_toggle(struct dw + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) + { +- u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; + + if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { +@@ -753,9 +753,9 @@ cleanup: + } + } + +- haintmsk = readl(hsotg->regs + HAINTMSK); ++ haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); + haintmsk &= ~(1 << chan->hc_num); +- writel(haintmsk, hsotg->regs + HAINTMSK); ++ dwc2_writel(haintmsk, hsotg->regs + HAINTMSK); + + /* Try to queue more transfers now that there's a free channel */ + tr_type = dwc2_hcd_select_transactions(hsotg); +@@ -802,9 +802,9 @@ static void dwc2_halt_channel(struct dwc + * is enabled so that the non-periodic schedule will + * be processed + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + dev_vdbg(hsotg->dev, "isoc/intr\n"); + /* +@@ -821,9 +821,9 @@ static void dwc2_halt_channel(struct dwc + * enabled so that the periodic schedule will be + * processed + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -888,7 +888,7 @@ static void dwc2_complete_periodic_xfer( + struct dwc2_qtd *qtd, + enum dwc2_halt_status halt_status) + { +- u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + + qtd->error_count = 0; + +@@ -1158,7 +1158,7 @@ static void dwc2_update_urb_state_abn(st + + urb->actual_length += xfer_length; + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", + __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); + dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", +@@ -1469,10 +1469,10 @@ static void dwc2_hc_ahberr_intr(struct d + + dwc2_hc_handle_tt_clear(hsotg, chan, qtd); + +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); +- hcsplt = readl(hsotg->regs + HCSPLT(chnum)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); +- hc_dma = readl(hsotg->regs + HCDMA(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); ++ hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum)); + + dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); + dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); +@@ -1685,10 +1685,10 @@ static bool dwc2_halt_status_ok(struct d + * This code is here only as a check. This condition should + * never happen. Ignore the halt if it does occur. + */ +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); +- hcsplt = readl(hsotg->regs + HCSPLT(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); + dev_dbg(hsotg->dev, + "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", + __func__); +@@ -1712,7 +1712,7 @@ static bool dwc2_halt_status_ok(struct d + * when the halt interrupt occurs. Halt the channel again if it does + * occur. + */ +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); + if (hcchar & HCCHAR_CHDIS) { + dev_warn(hsotg->dev, + "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", +@@ -1772,7 +1772,7 @@ static void dwc2_hc_chhltd_intr_dma(stru + return; + } + +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + + if (chan->hcint & HCINTMSK_XFERCOMPL) { + /* +@@ -1867,7 +1867,7 @@ static void dwc2_hc_chhltd_intr_dma(stru + dev_err(hsotg->dev, + "hcint 0x%08x, intsts 0x%08x\n", + chan->hcint, +- readl(hsotg->regs + GINTSTS)); ++ dwc2_readl(hsotg->regs + GINTSTS)); + goto error; + } + } +@@ -1922,11 +1922,11 @@ static void dwc2_hc_n_intr(struct dwc2_h + + chan = hsotg->hc_ptr_array[chnum]; + +- hcint = readl(hsotg->regs + HCINT(chnum)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); ++ hcint = dwc2_readl(hsotg->regs + HCINT(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + if (!chan) { + dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); +- writel(hcint, hsotg->regs + HCINT(chnum)); ++ dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + return; + } + +@@ -1938,7 +1938,7 @@ static void dwc2_hc_n_intr(struct dwc2_h + hcint, hcintmsk, hcint & hcintmsk); + } + +- writel(hcint, hsotg->regs + HCINT(chnum)); ++ dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + chan->hcint = hcint; + hcint &= hcintmsk; + +@@ -2030,7 +2030,7 @@ static void dwc2_hc_intr(struct dwc2_hso + u32 haint; + int i; + +- haint = readl(hsotg->regs + HAINT); ++ haint = dwc2_readl(hsotg->regs + HAINT); + if (dbg_perio()) { + dev_vdbg(hsotg->dev, "%s()\n", __func__); + +@@ -2098,8 +2098,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct + "DWC OTG HCD Finished Servicing Interrupts\n"); + dev_vdbg(hsotg->dev, + "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", +- readl(hsotg->regs + GINTSTS), +- readl(hsotg->regs + GINTMSK)); ++ dwc2_readl(hsotg->regs + GINTSTS), ++ dwc2_readl(hsotg->regs + GINTMSK)); + } + } + +--- a/drivers/usb/dwc2/hcd_queue.c ++++ b/drivers/usb/dwc2/hcd_queue.c +@@ -115,7 +115,7 @@ static void dwc2_qh_init(struct dwc2_hso + if (qh->ep_type == USB_ENDPOINT_XFER_INT) + qh->interval = 8; + #endif +- hprt = readl(hsotg->regs + HPRT0); ++ hprt = dwc2_readl(hsotg->regs + HPRT0); + prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + if (prtspd == HPRT0_SPD_HIGH_SPEED && + (dev_speed == USB_SPEED_LOW || +@@ -593,9 +593,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *h + if (status) + return status; + if (!hsotg->periodic_qh_count) { +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask |= GINTSTS_SOF; +- writel(intr_mask, hsotg->regs + GINTMSK); ++ dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + } + hsotg->periodic_qh_count++; + +@@ -630,9 +630,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsot + dwc2_deschedule_periodic(hsotg, qh); + hsotg->periodic_qh_count--; + if (!hsotg->periodic_qh_count) { +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask &= ~GINTSTS_SOF; +- writel(intr_mask, hsotg->regs + GINTMSK); ++ dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + } + } + diff --git a/target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch b/target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch new file mode 100644 index 0000000..d43cdf3 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0043-gpio-stp-xway-fix-phy-mask.patch @@ -0,0 +1,23 @@ +From 08b085a07efe12568d86dff064e6f089e2971744 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 25 May 2015 22:39:50 +0200 +Subject: gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs + +0x3 only masks two bits, but three bits have to be allowed. This fixes +GPHY0 LED2 (which is the highest bit of phy2) on my board. + +Signed-off-by: Martin Blumenstingl +Acked-by: John Crispin +Signed-off-by: Linus Walleij + +--- a/drivers/gpio/gpio-stp-xway.c ++++ b/drivers/gpio/gpio-stp-xway.c +@@ -58,7 +58,7 @@ + #define XWAY_STP_ADSL_MASK 0x3 + + /* 2 groups of 3 bits can be driven by the phys */ +-#define XWAY_STP_PHY_MASK 0x3 ++#define XWAY_STP_PHY_MASK 0x7 + #define XWAY_STP_PHY1_SHIFT 27 + #define XWAY_STP_PHY2_SHIFT 15 + diff --git a/target/linux/lantiq/patches-4.1/0050-MIPS-lantiq-add-clk_round_rate.patch b/target/linux/lantiq/patches-4.1/0050-MIPS-lantiq-add-clk_round_rate.patch new file mode 100644 index 0000000..b2cd356 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0050-MIPS-lantiq-add-clk_round_rate.patch @@ -0,0 +1,43 @@ +From b3c10c6c19a9a0ad2b967b6afc8d8302ff4e10f9 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens +Date: Sun, 25 Oct 2015 21:47:23 +0100 +Subject: [PATCH] MIPS: lantiq: add clk_round_rate() + +This adds a basic implementation of clk_round_rate() +The clk_round_rate() function is called by multiple drivers and +subsystems now and the lantiq clk driver is supposed to export this, +but doesn't do so, this causes linking problems like this one: +ERROR: "clk_round_rate" [drivers/media/v4l2-core/videodev.ko] undefined! + +Signed-off-by: Hauke Mehrtens +Cc: # 4.1+ +--- + arch/mips/lantiq/clk.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/mips/lantiq/clk.c ++++ b/arch/mips/lantiq/clk.c +@@ -99,6 +99,23 @@ int clk_set_rate(struct clk *clk, unsign + } + EXPORT_SYMBOL(clk_set_rate); + ++long clk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ if (unlikely(!clk_good(clk))) ++ return 0; ++ if (clk->rates && *clk->rates) { ++ unsigned long *r = clk->rates; ++ ++ while (*r && (*r != rate)) ++ r++; ++ if (!*r) { ++ return clk->rate; ++ } ++ } ++ return rate; ++} ++EXPORT_SYMBOL(clk_round_rate); ++ + int clk_enable(struct clk *clk) + { + if (unlikely(!clk_good(clk))) diff --git a/target/linux/lantiq/patches-4.1/0100-lantiq-xrx200-enable-remove-crc.patch b/target/linux/lantiq/patches-4.1/0100-lantiq-xrx200-enable-remove-crc.patch new file mode 100644 index 0000000..60a1937 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0100-lantiq-xrx200-enable-remove-crc.patch @@ -0,0 +1,25 @@ +--- a/drivers/net/ethernet/lantiq_xrx200.c ++++ b/drivers/net/ethernet/lantiq_xrx200.c +@@ -143,6 +143,7 @@ + #define PMAC_IPG_MASK 0xf + #define PMAC_HD_CTL_AS 0x0008 + #define PMAC_HD_CTL_AC 0x0004 ++#define PMAC_HD_CTL_RC 0x0010 + #define PMAC_HD_CTL_RXSH 0x0040 + #define PMAC_HD_CTL_AST 0x0080 + #define PMAC_HD_CTL_RST 0x0100 +@@ -1502,12 +1503,12 @@ static void xrx200_hw_init(struct xrx200 + #ifdef SW_ROUTING + /* enable status header, enable CRC */ + ltq_pmac_w32_mask(0, +- PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC, ++ PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, + PMAC_HD_CTL); + #else + /* disable status header, enable CRC */ + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS, +- PMAC_HD_CTL_AC, ++ PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, + PMAC_HD_CTL); + #endif + diff --git a/target/linux/lantiq/patches-4.1/0101-mtd-split.patch b/target/linux/lantiq/patches-4.1/0101-mtd-split.patch new file mode 100644 index 0000000..e3c3633 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0101-mtd-split.patch @@ -0,0 +1,192 @@ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,6 +1,6 @@ + obj-y := prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o + +-obj-y += vmmc.o tffs.o ++obj-y += vmmc.o tffs.o mtd_split.o + + obj-y += eth_mac.o + obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o pci-ath-fixup.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/mtd_split.c +@@ -0,0 +1,129 @@ ++#include ++#include ++#include ++#include ++ ++#define ROOTFS_SPLIT_NAME "rootfs_data" ++ ++struct squashfs_super_block { ++ __le32 s_magic; ++ __le32 pad0[9]; ++ __le64 bytes_used; ++}; ++ ++static void split_brnimage_kernel(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++ unsigned long buf[4]; ++ // Assume at most 2MB of kernel image ++ unsigned long end = offset + (2 << 20); ++ unsigned long part_size = offset + 0x400 - 12; ++ size_t len; ++ int ret; ++ ++ if (strcmp(name, "firmware") != 0) ++ return; ++ while (part_size < end) { ++ long size_min = part_size - 0x400 - 12 - offset; ++ long size_max = part_size + 12 - offset; ++ ret = mtd_read(master, part_size, 16, &len, (void *)buf); ++ if (ret || len != 16) ++ return; ++ ++ if (le32_to_cpu(buf[0]) < size_min || ++ le32_to_cpu(buf[0]) > size_max) { ++ part_size += 0x400; ++ continue; ++ } ++ ++ if (le32_to_cpu(buf[3]) == SQUASHFS_MAGIC) { ++ part_size += 12 - offset; ++ __mtd_add_partition(master, "rootfs", offset + part_size, ++ size - part_size, false); ++ return; ++ } ++ part_size += 0x400; ++ } ++} ++ ++static void split_eva_kernel(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++#define EVA_MAGIC 0xfeed1281 ++ unsigned long magic = 0; ++ unsigned long part_size = 0, p; ++ size_t len; ++ int ret; ++ ++ if (strcmp(name, CONFIG_MTD_SPLIT_FIRMWARE_NAME) != 0) ++ return; ++ ++ ret = mtd_read(master, offset, 4, &len, (void *)&magic); ++ if (ret || len != sizeof(magic)) ++ return; ++ ++ if (le32_to_cpu(magic) != EVA_MAGIC) ++ return; ++ ++ ret = mtd_read(master, offset + 4, 4, &len, (void *)&part_size); ++ if (ret || len != sizeof(part_size)) ++ return; ++ ++ p = part_size = le32_to_cpu(part_size) + 0x18; ++ p &= ~0xffff; ++ p += 0x10000; ++ ++ ret = mtd_read(master, offset + p, 4, &len, (void *)&magic); ++ if (ret || len != sizeof(magic)) ++ return; ++ ++ if (magic == SQUASHFS_MAGIC) ++ part_size = p + 0x100; ++ else ++ part_size = mtd_pad_erasesize(master, offset, len); ++ ++ if (part_size + master->erasesize > size) ++ return; ++ ++ __mtd_add_partition(master, "rootfs", offset + part_size, ++ size - part_size, false); ++} ++ ++static void split_tplink_kernel(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++#define TPLINK_MAGIC 0x00000002 ++ unsigned long magic = 0; ++ unsigned long part_size = 0; ++ size_t len; ++ int ret; ++ ++ if (strcmp(name, CONFIG_MTD_SPLIT_FIRMWARE_NAME) != 0) ++ return; ++ ++ ret = mtd_read(master, offset, 4, &len, (void *)&magic); ++ if (ret || len != sizeof(magic)) ++ return; ++ ++ if (le32_to_cpu(magic) != TPLINK_MAGIC) ++ return; ++ ++ ret = mtd_read(master, offset + 0x78, 4, &len, (void *)&part_size); ++ if (ret || len != sizeof(part_size)) ++ return; ++ ++ part_size = be32_to_cpu(part_size) + 0x200; ++ if (part_size + master->erasesize > size) ++ return; ++ ++ __mtd_add_partition(master, "rootfs", offset + part_size, ++ size - part_size, false); ++} ++ ++void arch_split_mtd_part(struct mtd_info *master, const char *name, ++ int offset, int size) ++{ ++ split_tplink_kernel(master, name, offset, size); ++ split_eva_kernel(master, name, offset, size); ++ split_brnimage_kernel(master, name, offset, size); ++} +--- a/include/linux/mtd/partitions.h ++++ b/include/linux/mtd/partitions.h +@@ -89,12 +89,17 @@ extern void deregister_mtd_parser(struct + int mtd_is_partition(const struct mtd_info *mtd); + int mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length); ++int __mtd_add_partition(struct mtd_info *master, const char *name, ++ long long offset, long long length, bool dup_check); ++ + int mtd_del_partition(struct mtd_info *master, int partno); + struct mtd_info *mtdpart_get_master(const struct mtd_info *mtd); + uint64_t mtdpart_get_offset(const struct mtd_info *mtd); + uint64_t mtd_get_device_size(const struct mtd_info *mtd); +-extern void __weak arch_split_mtd_part(struct mtd_info *master, +- const char *name, int offset, int size); ++void __weak arch_split_mtd_part(struct mtd_info *master, ++ const char *name, int offset, int size); ++unsigned long ++mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len); + + int parse_mtd_partitions_by_type(struct mtd_info *master, + enum mtd_parser_type type, +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -659,7 +659,7 @@ static int mtd_add_partition_attrs(struc + } + + +-static int ++int + __mtd_add_partition(struct mtd_info *master, const char *name, + long long offset, long long length, bool dup_check) + { +@@ -763,7 +763,7 @@ run_parsers_by_type(struct mtd_part *sla + return nr_parts; + } + +-static inline unsigned long ++unsigned long + mtd_pad_erasesize(struct mtd_info *mtd, int offset, int len) + { + unsigned long mask = mtd->erasesize - 1; +@@ -792,7 +792,6 @@ static void split_uimage(struct mtd_info + return; + + len = be32_to_cpu(hdr.size) + 0x40; +- len = mtd_pad_erasesize(master, part->offset, len); + if (len + master->erasesize > part->mtd.size) + return; + diff --git a/target/linux/lantiq/patches-4.1/0150-lantiq-pinctrl-xway.patch b/target/linux/lantiq/patches-4.1/0150-lantiq-pinctrl-xway.patch new file mode 100644 index 0000000..84adbe6 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0150-lantiq-pinctrl-xway.patch @@ -0,0 +1,15 @@ +--- a/drivers/pinctrl/pinctrl-xway.c ++++ b/drivers/pinctrl/pinctrl-xway.c +@@ -152,10 +152,10 @@ static const struct ltq_mfp_pin xway_mfp + MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), +- MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN), ++ MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY), + MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN), + MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), +- MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN), ++ MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN), + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE), + MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE), diff --git a/target/linux/lantiq/patches-4.1/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-4.1/0151-lantiq-ifxmips_pcie-use-of.patch new file mode 100644 index 0000000..26a3a65 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0151-lantiq-ifxmips_pcie-use-of.patch @@ -0,0 +1,51 @@ +--- a/arch/mips/pci/ifxmips_pcie.c ++++ b/arch/mips/pci/ifxmips_pcie.c +@@ -18,6 +18,8 @@ + #include + #include + ++#include ++ + #include "ifxmips_pcie.h" + #include "ifxmips_pcie_reg.h" + +@@ -1045,7 +1047,7 @@ pcie_rc_initialize(int pcie_port) + return 0; + } + +-static int __init ifx_pcie_bios_init(void) ++static int __init ifx_pcie_bios_probe(struct platform_device *pdev) + { + void __iomem *io_map_base; + int pcie_port; +@@ -1083,6 +1085,30 @@ static int __init ifx_pcie_bios_init(voi + + return 0; + } ++ ++static const struct of_device_id ifxmips_pcie_match[] = { ++ { .compatible = "lantiq,pcie-xrx200" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); ++ ++static struct platform_driver ltq_pci_driver = { ++ .probe = ifx_pcie_bios_probe, ++ .driver = { ++ .name = "pcie-xrx200", ++ .owner = THIS_MODULE, ++ .of_match_table = ifxmips_pcie_match, ++ }, ++}; ++ ++int __init ifx_pcie_bios_init(void) ++{ ++ int ret = platform_driver_register(<q_pci_driver); ++ if (ret) ++ pr_info("pcie-xrx200: Error registering platform driver!"); ++ return ret; ++} ++ + arch_initcall(ifx_pcie_bios_init); + + MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/patches-4.1/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-4.1/0160-owrt-lantiq-multiple-flash.patch new file mode 100644 index 0000000..c093231 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0160-owrt-lantiq-multiple-flash.patch @@ -0,0 +1,217 @@ +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -38,10 +39,12 @@ enum { + LTQ_NOR_NORMAL + }; + ++#define MAX_RESOURCES 4 ++ + struct ltq_mtd { +- struct resource *res; +- struct mtd_info *mtd; +- struct map_info *map; ++ struct mtd_info *mtd[MAX_RESOURCES]; ++ struct mtd_info *cmtd; ++ struct map_info map[MAX_RESOURCES]; + }; + + static const char ltq_map_name[] = "ltq_nor"; +@@ -109,12 +112,44 @@ ltq_copy_to(struct map_info *map, unsign + } + + static int ++ltq_mtd_remove(struct platform_device *pdev) ++{ ++ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); ++ int i; ++ ++ if (ltq_mtd == NULL) ++ return 0; ++ ++ if (ltq_mtd->cmtd) { ++ mtd_device_unregister(ltq_mtd->cmtd); ++ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) ++ mtd_concat_destroy(ltq_mtd->cmtd); ++ } ++ ++ for (i = 0; i < MAX_RESOURCES; i++) { ++ if (ltq_mtd->mtd[i] != NULL) ++ map_destroy(ltq_mtd->mtd[i]); ++ } ++ ++ kfree(ltq_mtd); ++ ++ return 0; ++} ++ ++static int + ltq_mtd_probe(struct platform_device *pdev) + { + struct mtd_part_parser_data ppdata; + struct ltq_mtd *ltq_mtd; + struct cfi_private *cfi; +- int err; ++ int err = 0; ++ int i; ++ int devices_found = 0; ++ ++ static const char *rom_probe_types[] = { ++ "cfi_probe", "jedec_probe", NULL ++ }; ++ const char **type; + + if (of_machine_is_compatible("lantiq,falcon") && + (ltq_boot_select() != BS_FLASH)) { +@@ -128,76 +163,88 @@ ltq_mtd_probe(struct platform_device *pd + + platform_set_drvdata(pdev, ltq_mtd); + +- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!ltq_mtd->res) { +- dev_err(&pdev->dev, "failed to get memory resource\n"); +- return -ENOENT; ++ for (i = 0; i < pdev->num_resources; i++) { ++ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", ++ (unsigned long long)resource_size(&pdev->resource[i]), ++ (unsigned long long)pdev->resource[i].start); ++ ++ if (!devm_request_mem_region(&pdev->dev, ++ pdev->resource[i].start, ++ resource_size(&pdev->resource[i]), ++ dev_name(&pdev->dev))) { ++ dev_err(&pdev->dev, "Could not reserve memory region\n"); ++ return -ENOMEM; ++ } ++ ++ ltq_mtd->map[i].name = ltq_map_name; ++ ltq_mtd->map[i].bankwidth = 2; ++ ltq_mtd->map[i].read = ltq_read16; ++ ltq_mtd->map[i].write = ltq_write16; ++ ltq_mtd->map[i].copy_from = ltq_copy_from; ++ ltq_mtd->map[i].copy_to = ltq_copy_to; ++ ++ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) ++ ltq_mtd->map[i].phys = NO_XIP; ++ else ++ ltq_mtd->map[i].phys = pdev->resource[i].start; ++ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); ++ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, ++ ltq_mtd->map[i].size); ++ if (IS_ERR(ltq_mtd->map[i].virt)) ++ return PTR_ERR(ltq_mtd->map[i].virt); ++ ++ if (ltq_mtd->map[i].virt == NULL) { ++ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); ++ err = PTR_ERR(ltq_mtd->map[i].virt); ++ goto err_out; ++ } ++ ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; ++ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) ++ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); ++ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; ++ ++ if (!ltq_mtd->mtd[i]) { ++ dev_err(&pdev->dev, "probing failed\n"); ++ return -ENXIO; ++ } else { ++ devices_found++; ++ } ++ ++ ltq_mtd->mtd[i]->owner = THIS_MODULE; ++ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; ++ ++ cfi = ltq_mtd->map[i].fldrv_priv; ++ cfi->addr_unlock1 ^= 1; ++ cfi->addr_unlock2 ^= 1; + } + +- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), +- GFP_KERNEL); +- if (!ltq_mtd->map) +- return -ENOMEM; +- +- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) +- ltq_mtd->map->phys = NO_XIP; +- else +- ltq_mtd->map->phys = ltq_mtd->res->start; +- ltq_mtd->res->start; +- ltq_mtd->map->size = resource_size(ltq_mtd->res); +- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); +- if (IS_ERR(ltq_mtd->map->virt)) +- return PTR_ERR(ltq_mtd->map->virt); +- +- ltq_mtd->map->name = ltq_map_name; +- ltq_mtd->map->bankwidth = 2; +- ltq_mtd->map->read = ltq_read16; +- ltq_mtd->map->write = ltq_write16; +- ltq_mtd->map->copy_from = ltq_copy_from; +- ltq_mtd->map->copy_to = ltq_copy_to; +- +- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; +- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); +- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; +- +- if (!ltq_mtd->mtd) { +- dev_err(&pdev->dev, "probing failed\n"); +- return -ENXIO; +- } +- +- ltq_mtd->mtd->owner = THIS_MODULE; +- +- cfi = ltq_mtd->map->fldrv_priv; +- cfi->addr_unlock1 ^= 1; +- cfi->addr_unlock2 ^= 1; ++ if (devices_found == 1) { ++ ltq_mtd->cmtd = ltq_mtd->mtd[0]; ++ } else if (devices_found > 1) { ++ /* ++ * We detected multiple devices. Concatenate them together. ++ */ ++ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); ++ if (ltq_mtd->cmtd == NULL) ++ err = -ENXIO; ++ } + + ppdata.of_node = pdev->dev.of_node; +- err = mtd_device_parse_register(ltq_mtd->mtd, ltq_probe_types, ++ err = mtd_device_parse_register(ltq_mtd->cmtd, ltq_probe_types, + &ppdata, NULL, 0); + if (err) { + dev_err(&pdev->dev, "failed to add partitions\n"); +- goto err_destroy; ++ goto err_out; + } + + return 0; + +-err_destroy: +- map_destroy(ltq_mtd->mtd); ++err_out: ++ ltq_mtd_remove(pdev); + return err; + } + +-static int +-ltq_mtd_remove(struct platform_device *pdev) +-{ +- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); +- +- if (ltq_mtd && ltq_mtd->mtd) { +- mtd_device_unregister(ltq_mtd->mtd); +- map_destroy(ltq_mtd->mtd); +- } +- return 0; +-} +- + static const struct of_device_id ltq_mtd_match[] = { + { .compatible = "lantiq,nor" }, + {}, diff --git a/target/linux/lantiq/patches-4.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-4.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch new file mode 100644 index 0000000..d153c52 --- /dev/null +++ b/target/linux/lantiq/patches-4.1/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0001.c ++++ b/drivers/mtd/chips/cfi_cmdset_0001.c +@@ -39,7 +39,7 @@ + /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ + + // debugging, turns off buffer write mode if set to 1 +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + + /* Intel chips */ + #define I82802AB 0x00ad diff --git a/target/linux/lantiq/xrx200/config-default b/target/linux/lantiq/xrx200/config-default new file mode 100644 index 0000000..c18ad1f --- /dev/null +++ b/target/linux/lantiq/xrx200/config-default @@ -0,0 +1,76 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_GPIO_DEVRES=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HZ_PERIODIC=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_PHY=y +CONFIG_LANTIQ_XRX200=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LIBFDT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_NAND_XWAY=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NLS=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_OF_ADDRESS_PCI=y +CONFIG_PCIE_LANTIQ=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366S_PHY=y +CONFIG_RTL8367B_PHY=y +CONFIG_RTL8367_PHY=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_XWAY=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +# CONFIG_UBIFS_FS_XZ is not set +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_XRX200_PHY_FW=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/xrx200/profiles/arv.mk b/target/linux/lantiq/xrx200/profiles/arv.mk new file mode 100644 index 0000000..3dc22c0 --- /dev/null +++ b/target/linux/lantiq/xrx200/profiles/arv.mk @@ -0,0 +1,46 @@ +define Profile/VG3503J + NAME:=BT Openreach - ECI VDSL Modem +endef + +$(eval $(call Profile,VG3503J)) + +define Profile/VG3503J_V2 + NAME:=BT Openreach - ECI VDSL Modem v2 +endef + +$(eval $(call Profile,VG3503J_V2)) + +define Profile/VGV7510KW22NOR + NAME:=o2 Box 6431 / Arcadyan VGV7510KW22 (NOR) + PACKAGES:=kmod-rt2800-pci wpad-mini kmod-usb-dwc2 +endef + +$(eval $(call Profile,VGV7510KW22NOR)) + +define Profile/VGV7510KW22BRN + NAME:=o2 Box 6431 / Arcadyan VGV7510KW22 (BRN) + PACKAGES:=kmod-rt2800-pci wpad-mini kmod-usb-dwc2 +endef + +$(eval $(call Profile,VGV7510KW22BRN)) + +define Profile/VGV7519NOR + NAME:=Experiabox 8 VGV7519 + PACKAGES:=kmod-rt2800-pci wpad-mini kmod-usb-dwc2 +endef + +$(eval $(call Profile,VGV7519NOR)) + +define Profile/VGV7519BRN + NAME:=Experiabox 8 VGV7519 (BRN) + PACKAGES:=kmod-rt2800-pci wpad-mini kmod-usb-dwc2 +endef + +$(eval $(call Profile,VGV7519BRN)) + +define Profile/ARV7519RW22 + NAME:=Livebox Astoria ARV7519RW22 + PACKAGES:=kmod-usb-dwc2 +endef + +$(eval $(call Profile,ARV7519RW22)) diff --git a/target/linux/lantiq/xrx200/profiles/avm.mk b/target/linux/lantiq/xrx200/profiles/avm.mk new file mode 100644 index 0000000..89909b9 --- /dev/null +++ b/target/linux/lantiq/xrx200/profiles/avm.mk @@ -0,0 +1,9 @@ +define Profile/FRITZ3370 + NAME:=Fritz!Box WLan - FRITZ3370 + PACKAGES:=kmod-ath9k wpad-mini kmod-usb-dwc2 +endef + +FRITZ3370_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +FRITZ3370_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,FRITZ3370)) diff --git a/target/linux/lantiq/xrx200/profiles/bt.mk b/target/linux/lantiq/xrx200/profiles/bt.mk new file mode 100644 index 0000000..a1083bb --- /dev/null +++ b/target/linux/lantiq/xrx200/profiles/bt.mk @@ -0,0 +1,9 @@ +define Profile/BTHOMEHUBV5A + NAME:=BT Home Hub 5A + PACKAGES:=kmod-ath9k kmod-ath10k wpad-mini kmod-usb-dwc2 +endef + +BTHOMEHUBV5A_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +BTHOMEHUBV5A_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,BTHOMEHUBV5A)) diff --git a/target/linux/lantiq/xrx200/profiles/lantiq.mk b/target/linux/lantiq/xrx200/profiles/lantiq.mk new file mode 100644 index 0000000..0ec6be4 --- /dev/null +++ b/target/linux/lantiq/xrx200/profiles/lantiq.mk @@ -0,0 +1,13 @@ +define Profile/EASY80920NOR + NAME:=Lantiq VR9 - EASY80920NOR + PACKAGES:=kmod-ath9k wpad-mini kmod-usb-dwc2 +endef + +$(eval $(call Profile,EASY80920NOR)) + +define Profile/EASY80920NAND + NAME:=Lantiq VR9 - EASY80920NAND + PACKAGES:=kmod-ath9k wpad-mini kmod-usb-dwc2 +endef + +$(eval $(call Profile,EASY80920NAND)) diff --git a/target/linux/lantiq/xrx200/profiles/tplink.mk b/target/linux/lantiq/xrx200/profiles/tplink.mk new file mode 100644 index 0000000..6ae9399 --- /dev/null +++ b/target/linux/lantiq/xrx200/profiles/tplink.mk @@ -0,0 +1,13 @@ +define Profile/TDW8970 + NAME:=TP-LINK TD-W8970 + PACKAGES:=kmod-ath9k wpad-mini kmod-usb-dwc2 kmod-ledtrig-usbdev +endef + +$(eval $(call Profile,TDW8970)) + +define Profile/TDW8980 + NAME:=TP-LINK TD-W8980 + PACKAGES:=kmod-ath9k wpad-mini kmod-usb-dwc2 kmod-ledtrig-usbdev +endef + +$(eval $(call Profile,TDW8980)) diff --git a/target/linux/lantiq/xrx200/profiles/zyxel.mk b/target/linux/lantiq/xrx200/profiles/zyxel.mk new file mode 100644 index 0000000..f6995f9 --- /dev/null +++ b/target/linux/lantiq/xrx200/profiles/zyxel.mk @@ -0,0 +1,20 @@ +define Profile/P2812HNUF1 + NAME:=ZyXEL P-2812HNU-F1 + PACKAGES:=kmod-rt2800-pci wpad-mini kmod-usb-dwc2 +endef + +P2812HNUF1_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +P2812HNUF1_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,P2812HNUF1)) + +define Profile/P2812HNUF3 + NAME:=ZyXEL P-2812HNU-F3 + PACKAGES:=kmod-rt2800-pci wpad-mini kmod-usb-dwc2 +endef + +P2812HNUF3_UBIFS_OPTS:="-m 2048 -e 126KiB -c 4096" +P2812HNUF3_UBI_OPTS:="-m 2048 -p 128KiB -s 512" + +$(eval $(call Profile,P2812HNUF3)) + diff --git a/target/linux/lantiq/xrx200/target.mk b/target/linux/lantiq/xrx200/target.mk new file mode 100644 index 0000000..a235015 --- /dev/null +++ b/target/linux/lantiq/xrx200/target.mk @@ -0,0 +1,23 @@ +ARCH:=mips +SUBTARGET:=xrx200 +BOARDNAME:=XRX200 +FEATURES:=squashfs atm mips16 jffs2 nand ubifs +CPU_TYPE:=34kc +CPU_SUBTYPE:=dsp + +DEFAULT_PACKAGES+=kmod-leds-gpio \ + kmod-gpio-button-hotplug \ + ltq-vdsl-vr9-fw-installer \ + kmod-ltq-vdsl-vr9-mei \ + kmod-ltq-vdsl-vr9 \ + kmod-ltq-atm-vr9 \ + kmod-ltq-ptm-vr9 \ + kmod-ltq-deu-vr9 \ + ltq-vdsl-app \ + ppp-mod-pppoa \ + swconfig \ + atm-esi + +define Target/Description + Lantiq XRX200 +endef diff --git a/target/linux/lantiq/xway/config-default b/target/linux/lantiq/xway/config-default new file mode 100644 index 0000000..7334c97 --- /dev/null +++ b/target/linux/lantiq/xway/config-default @@ -0,0 +1,74 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_SUPPORTS_MSA=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_GPIO_DEVRES=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HZ_PERIODIC=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LIBFDT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_NAND_XWAY=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_NLS=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_OF_ADDRESS_PCI=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RTL8306_PHY=y +CONFIG_RTL8366S_PHY=y +CONFIG_RTL8367B_PHY=y +CONFIG_RTL8367_PHY=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_XWAY=y +CONFIG_SYS_SUPPORTS_MIPS16=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +# CONFIG_UBIFS_FS_XZ is not set +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_XRX200_PHY_FW is not set +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/xway/profiles/arv.mk b/target/linux/lantiq/xway/profiles/arv.mk new file mode 100644 index 0000000..976cd19 --- /dev/null +++ b/target/linux/lantiq/xway/profiles/arv.mk @@ -0,0 +1,167 @@ +define Profile/ARV4525PW + NAME:=Speedport W502V Typ A - ARV4525PW + PACKAGES:=kmod-ath5k wpad-mini \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa +endef + +$(eval $(call Profile,ARV4525PW)) + +define Profile/ARV8539PW22 + NAME:=Speedport W504V Typ A - ARV8539PW22 + PACKAGES:=kmod-ltq-hcd-danube \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV8539PW22)) + +define Profile/ARV7525PW + NAME:=Speedport W303V Typ A - ARV7525PW + PACKAGES:=kmod-rt2800-pci wpad-mini \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa +endef + +$(eval $(call Profile,ARV7525PW)) + +define Profile/ARV4518PWR01 + NAME:=ARV4518PWR01 + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath5k wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV4518PWR01)) + +define Profile/ARV4518PWR01A + NAME:=ARV4518PWR01A + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath5k wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV4518PWR01A)) + +define Profile/ARV4510PW + NAME:=Wippies, Elisa - ARV4510PW + PACKAGES:=kmod-ledtrig-usbdev kmod-usb2-pci kmod-usb-uhci \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-rt2800-pci kmod-ath5k wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV4510PW)) + +define Profile/ARV4519PW + NAME:=Vodafone, Pirelli - ARV4519PW + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + swconfig +endef + +$(eval $(call Profile,ARV4519PW)) + +define Profile/ARV7510PW22 + NAME:=Astoria - ARV7510PW22 + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-rt2800-pci wpad-mini \ + kmod-usb-uhci kmod-usb2 kmod-usb2-pci \ + swconfig +endef + +$(eval $(call Profile,ARV7510PW22)) + +define Profile/ARV7518PW + NAME:=Astoria - ARV7518PW + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV7518PW)) + +define Profile/ARV7519PW + NAME:=Astoria - ARV7519PW + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-rt2800-pci wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV7519PW)) + +define Profile/ARV4520PW + NAME:=Easybox 800, WAV-281 - ARV4520PW + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-rt61-pci wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV4520PW)) + +define Profile/ARV452CQW + NAME:=Easybox 801 - ARV452CQW + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ath5k wpad-mini \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + swconfig +endef + +$(eval $(call Profile,ARV452CQW)) + +define Profile/ARV752DPW + NAME:=Easybox 802 - ARV752DPW + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-rt2800-pci wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV752DPW)) + +define Profile/ARV752DPW22 + NAME:=Easybox 803 - ARV752DPW22 + PACKAGES:=kmod-usb2-pci kmod-usb-uhci kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-tapi kmod-ltq-vmmc \ + kmod-rt2800-pci wpad-mini \ + swconfig +endef + +$(eval $(call Profile,ARV752DPW22)) diff --git a/target/linux/lantiq/xway/profiles/audiocodes.mk b/target/linux/lantiq/xway/profiles/audiocodes.mk new file mode 100644 index 0000000..006cc50 --- /dev/null +++ b/target/linux/lantiq/xway/profiles/audiocodes.mk @@ -0,0 +1,9 @@ +define Profile/ACMP252 + NAME:=AudioCodes MediaPack MP-252 + PACKAGES:=kmod-rt2x00-pci wpad-mini \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-ptm-danube \ + ltq-adsl-app +endef + +$(eval $(call Profile,ACMP252)) diff --git a/target/linux/lantiq/xway/profiles/avm.mk b/target/linux/lantiq/xway/profiles/avm.mk new file mode 100644 index 0000000..1ca963b --- /dev/null +++ b/target/linux/lantiq/xway/profiles/avm.mk @@ -0,0 +1,10 @@ +define Profile/FRITZ7320 + NAME:=1&1 HomeServer - FRITZ7320 + PACKAGES:=kmod-ath9k wpad-mini \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-deu-ar9 kmod-ltq-hcd-ar9 +endef + +$(eval $(call Profile,FRITZ7320)) diff --git a/target/linux/lantiq/xway/profiles/aztech.mk b/target/linux/lantiq/xway/profiles/aztech.mk new file mode 100644 index 0000000..3b9e92d --- /dev/null +++ b/target/linux/lantiq/xway/profiles/aztech.mk @@ -0,0 +1,7 @@ +define Profile/GR7000 + NAME:=Aztech GR7000 + PACKAGES:= \ + kmod-ltq-deu-ar9 kmod-ltq-hcd-ar9 \ + swconfig +endef +$(eval $(call Profile,GR7000)) diff --git a/target/linux/lantiq/xway/profiles/bt.mk b/target/linux/lantiq/xway/profiles/bt.mk new file mode 100644 index 0000000..e04a607 --- /dev/null +++ b/target/linux/lantiq/xway/profiles/bt.mk @@ -0,0 +1,34 @@ +define Profile/BTHOMEHUBV2B + NAME:=BT Home Hub 2B + PACKAGES:=kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \ + kmod-ltq-deu-danube \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k wpad-mini \ + swconfig +endef + + +BTHOMEHUBV2B_UBIFS_OPTS:="-m 512 -e 15872 -c 1959" +BTHOMEHUBV2B_UBI_OPTS:="-m 512 -p 16KiB -s 256" + + +$(eval $(call Profile,BTHOMEHUBV2B)) + +define Profile/BTHOMEHUBV3A + NAME:=BT Home Hub 3A + PACKAGES:=kmod-ltq-hcd-ar9 kmod-ledtrig-usbdev \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ + kmod-ltq-deu-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k wpad-mini \ + swconfig +endef + +BTHOMEHUBV3A_UBIFS_OPTS:="-m 512 -e 15872 -c 1959" +BTHOMEHUBV3A_UBI_OPTS:="-m 512 -p 16KiB -s 256" + + +$(eval $(call Profile,BTHOMEHUBV3A)) diff --git a/target/linux/lantiq/xway/profiles/buffalo.mk b/target/linux/lantiq/xway/profiles/buffalo.mk new file mode 100644 index 0000000..3567d5f --- /dev/null +++ b/target/linux/lantiq/xway/profiles/buffalo.mk @@ -0,0 +1,23 @@ +define Profile/WBMRA + NAME:=Buffalo WBMR-HP-G300H (A) - WBMR + PACKAGES:=kmod-ltq-hcd-ar9 kmod-ledtrig-usbdev \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k wpad hostapd-utils \ + swconfig +endef + +$(eval $(call Profile,WBMRA)) + +define Profile/WBMRB + NAME:=Buffalo WBMR-HP-G300H (B) - WBMR + PACKAGES:=kmod-ltq-hcd-ar9 kmod-ledtrig-usbdev \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ath9k wpad hostapd-utils \ + swconfig +endef + +$(eval $(call Profile,WBMRB)) diff --git a/target/linux/lantiq/xway/profiles/gigaset.mk b/target/linux/lantiq/xway/profiles/gigaset.mk new file mode 100644 index 0000000..c6259af --- /dev/null +++ b/target/linux/lantiq/xway/profiles/gigaset.mk @@ -0,0 +1,11 @@ +define Profile/GIGASX76X + NAME:=Gigaset sx76x + PACKAGES:= kmod-ltq-hcd-danube kmod-ledtrig-usbdev \ + kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \ + kmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \ + ltq-adsl-app ppp-mod-pppoe \ + kmod-ath5k wpad-mini \ + swconfig +endef + +$(eval $(call Profile,GIGASX76X)) diff --git a/target/linux/lantiq/xway/profiles/lantiq.mk b/target/linux/lantiq/xway/profiles/lantiq.mk new file mode 100644 index 0000000..800a9f6 --- /dev/null +++ b/target/linux/lantiq/xway/profiles/lantiq.mk @@ -0,0 +1,5 @@ +define Profile/EASY50712 + NAME:=Lantiq Danube - EASY50712 +endef + +$(eval $(call Profile,EASY50712)) diff --git a/target/linux/lantiq/xway/profiles/netgear.mk b/target/linux/lantiq/xway/profiles/netgear.mk new file mode 100644 index 0000000..e29f711 --- /dev/null +++ b/target/linux/lantiq/xway/profiles/netgear.mk @@ -0,0 +1,23 @@ +define Profile/DGN3500 + NAME:=Netgear DGN3500 + PACKAGES:=kmod-ltq-hcd-ar9 kmod-ledtrig-usbdev \ + kmod-ath9k wpad-mini \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-deu-ar9 swconfig +endef + +$(eval $(call Profile,DGN3500)) + +define Profile/DGN3500B + NAME:=Netgear DGN3500B + PACKAGES:=kmod-ltq-hcd-ar9 kmod-ledtrig-usbdev \ + kmod-ath9k wpad-mini \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoa \ + kmod-ltq-deu-ar9 swconfig +endef + +$(eval $(call Profile,DGN3500B)) diff --git a/target/linux/lantiq/xway/profiles/zte.mk b/target/linux/lantiq/xway/profiles/zte.mk new file mode 100644 index 0000000..d6e70f2 --- /dev/null +++ b/target/linux/lantiq/xway/profiles/zte.mk @@ -0,0 +1,12 @@ +define Profile/H201L + NAME:=ZTE H201L - H201L + PACKAGES:=kmod-ath9k-htc wpad-mini \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoe \ + kmod-ltq-deu-ar9 kmod-ltq-hcd-ar9 \ + kmod-ltq-tapi kmod-ltq-vmmc \ + swconfig +endef + +$(eval $(call Profile,H201L)) diff --git a/target/linux/lantiq/xway/profiles/zyxel.mk b/target/linux/lantiq/xway/profiles/zyxel.mk new file mode 100644 index 0000000..b2c6ef5 --- /dev/null +++ b/target/linux/lantiq/xway/profiles/zyxel.mk @@ -0,0 +1,10 @@ +define Profile/P2601HNFX + NAME:=ZyXEL P-2601HN-Fx + PACKAGES:= kmod-rt2800-usb wpad-mini \ + kmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \ + kmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \ + ltq-adsl-app ppp-mod-pppoe \ + kmod-ltq-deu-ar9 kmod-ltq-hcd-ar9 \ + swconfig +endef +$(eval $(call Profile,P2601HNFX)) diff --git a/target/linux/lantiq/xway/target.mk b/target/linux/lantiq/xway/target.mk new file mode 100644 index 0000000..9434cc9 --- /dev/null +++ b/target/linux/lantiq/xway/target.mk @@ -0,0 +1,12 @@ +ARCH:=mips +SUBTARGET:=xway +BOARDNAME:=XWAY +FEATURES:=squashfs atm mips16 nand ubifs ramdisk +CPU_TYPE:=34kc +CPU_SUBTYPE:=dsp + +DEFAULT_PACKAGES+=kmod-leds-gpio kmod-gpio-button-hotplug atm-esi + +define Target/Description + Lantiq XWAY +endef diff --git a/target/linux/malta/Makefile b/target/linux/malta/Makefile new file mode 100644 index 0000000..8392738 --- /dev/null +++ b/target/linux/malta/Makefile @@ -0,0 +1,22 @@ +# +# Copyright (C) 2010-2011 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +BOARD:=malta +BOARDNAME:=MIPS Malta CoreLV board (qemu) +CPU_TYPE:=24kc +SUBTARGETS:=le be #le64 be64 +INITRAMFS_EXTRA_FILES:= +MAINTAINER:=Florian Fainelli + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += wpad-mini kmod-mac80211-hwsim kmod-pcnet32 + +$(eval $(call BuildTarget)) diff --git a/target/linux/malta/README b/target/linux/malta/README new file mode 100644 index 0000000..22bdff5 --- /dev/null +++ b/target/linux/malta/README @@ -0,0 +1,13 @@ +This Malta target is intended to be used with the Qemu emulator. It can be used +to prototype an OpenWrt firmware for MIPS processors. One could also use it to +troubleshoot MIPS applications without access to real hardware. + +To use the images built by OpenWrt with qemu, use the following commands: + +For the little-endian image: +qemu-system-mipsel -kernel bin/malta/openwrt-malta-le-vmlinux-initramfs.elf -nographic -m 256 + +For the big-endian image: +qemu-system-mips -kernel bin/malta/openwrt-malta-be-vmlinux-initramfs.elf -nographic -m 256 + +and enjoy the system bootin. diff --git a/target/linux/malta/base-files/etc/inittab b/target/linux/malta/base-files/etc/inittab new file mode 100644 index 0000000..88567b2 --- /dev/null +++ b/target/linux/malta/base-files/etc/inittab @@ -0,0 +1,7 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +tts/0::askfirst:/bin/ash --login +ttyS0::askfirst:/bin/ash --login +ttyS1::askfirst:/bin/ash --login +ttyS2::askfirst:/bin/ash --login +tty1::askfirst:/bin/ash --login diff --git a/target/linux/malta/base-files/etc/uci-defaults/02-network b/target/linux/malta/base-files/etc/uci-defaults/02-network new file mode 100644 index 0000000..7b3e225 --- /dev/null +++ b/target/linux/malta/base-files/etc/uci-defaults/02-network @@ -0,0 +1,9 @@ +#!/bin/sh + +. /lib/functions/uci-defaults.sh + +ucidef_set_interface_loopback +ucidef_set_interface_wan "eth0" +if [ -d "/sys/class/net/eth1" ]; then + ucidef_set_interface_lan "eth1" +fi diff --git a/target/linux/malta/be/config-default b/target/linux/malta/be/config-default new file mode 100644 index 0000000..2772ed7 --- /dev/null +++ b/target/linux/malta/be/config-default @@ -0,0 +1,9 @@ +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set diff --git a/target/linux/malta/be/target.mk b/target/linux/malta/be/target.mk new file mode 100644 index 0000000..92ae58e --- /dev/null +++ b/target/linux/malta/be/target.mk @@ -0,0 +1,10 @@ +ARCH:=mips +ARCH_PACKAGES:=malta_mips +SUBTARGET:=be +BOARDNAME:=Big Endian +FEATURES:=ramdisk mips16 + +define Target/Description + Build BE firmware images for MIPS Malta CoreLV board running in + big-endian mode +endef diff --git a/target/linux/malta/be64/config-default b/target/linux/malta/be64/config-default new file mode 100644 index 0000000..b424c3e --- /dev/null +++ b/target/linux/malta/be64/config-default @@ -0,0 +1,30 @@ +# CONFIG_32BIT is not set +CONFIG_64BIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_BINFMT_ELF32=y +CONFIG_BLOCK_COMPAT=y +CONFIG_COMPAT=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +CONFIG_CPU_MIPS64=y +CONFIG_CPU_MIPS64_R1=y +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +# CONFIG_HUGETLBFS is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_MIPS32_N32=y +CONFIG_MIPS32_O32=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y diff --git a/target/linux/malta/be64/target.mk b/target/linux/malta/be64/target.mk new file mode 100644 index 0000000..dad3a1c --- /dev/null +++ b/target/linux/malta/be64/target.mk @@ -0,0 +1,10 @@ +ARCH:=mips64 +ARCH_PACKAGES:=malta_mips64 +SUBTARGET:=be64 +BOARDNAME:=Big Endian (64-bits) +FEATURES:=ramdisk + +define Target/Description + Build BE firmware images for MIPS Malta CoreLV board running in + big-endian and 64-bits mode +endef diff --git a/target/linux/malta/config-3.18 b/target/linux/malta/config-3.18 new file mode 100644 index 0000000..09d3ab3 --- /dev/null +++ b/target/linux/malta/config-3.18 @@ -0,0 +1,256 @@ +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +# CONFIG_AX88796_93CX6 is not set +CONFIG_ATA=y +CONFIG_ATA_PIIX=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_DM is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_SD=y +CONFIG_BOARD_SCACHE=y +CONFIG_BOOT_ELF32=y +CONFIG_BOUNCE=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_CEVT_GIC is not set +CONFIG_CEVT_R4K=y +CONFIG_CLKBLD_I8253=y +CONFIG_CLKEVT_I8253=y +CONFIG_CLKSRC_I8253=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_CPU_HAS_SMARTMIPS is not set +CONFIG_CPU_HAS_SYNC=y +# CONFIG_CPU_MIPS32_3_5_FEATURES is not set +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +# CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS is not set +# CONFIG_CPU_NEVADA is not set +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CSRC_GIC=y +CONFIG_CSRC_R4K=y +# CONFIG_DEBUG_FS is not set +CONFIG_DEVKMEM=y +CONFIG_DMA_MAYBE_COHERENT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DNOTIFY=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EARLY_PRINTK=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIO_DEVRES=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KVM=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_HAS_PCI=y +CONFIG_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_I8259=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_INPUT=y +# CONFIG_INPUT_MISC is not set +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_IPC_NS=y +# CONFIG_IP_MROUTE is not set +CONFIG_IRQ_CPU=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_GIC=y +CONFIG_IRQ_WORK=y +CONFIG_ISA_DMA_API=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_KALLSYMS=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KERNEL_GZIP=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_MD=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS=y +CONFIG_MIPS_BONITO64=y +# CONFIG_MIPS_CMP is not set +# CONFIG_MIPS_CPS is not set +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_EXTERNAL_TIMER=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=6 +CONFIG_MIPS_L1_CACHE_SHIFT_6=y +# CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_MALTA=y +CONFIG_MIPS_MSC=y +CONFIG_MIPS_MT=y +# CONFIG_MIPS_MT_DISABLED is not set +CONFIG_MIPS_MT_FPAFF=y +CONFIG_MIPS_MT_SMP=y +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y +# CONFIG_MIPS_VPE_LOADER is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MTD_CFI_STAA=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NAMESPACES=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_FLOW_LIMIT=y +# CONFIG_NET_NS is not set +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_NR_CPUS_DEFAULT_2=y +CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_GT64XXX_PCI0=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PID_NS=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTA=y +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_QUOTA_TREE=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RELAY=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_SCSI=y +CONFIG_SCSI_NETLINK=y +CONFIG_SECCOMP=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SMP=y +CONFIG_SMP_UP=y +CONFIG_SOCK_DIAG=y +# CONFIG_STAGING is not set +CONFIG_STOP_MACHINE=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SYNC_R4K=y +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_SYS_HAS_CPU_MIPS64_R1=y +CONFIG_SYS_HAS_CPU_MIPS64_R2=y +CONFIG_SYS_HAS_CPU_NEVADA=y +CONFIG_SYS_HAS_CPU_RM7000=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_MIPS_CMP=y +CONFIG_SYS_SUPPORTS_MULTITHREADING=y +CONFIG_SYS_SUPPORTS_SCHED_SMT=y +CONFIG_SYS_SUPPORTS_SMARTMIPS=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +# CONFIG_UBIFS_FS is not set +CONFIG_UIDGID_CONVERTED=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_SUPPORT=y +# CONFIG_USER_NS is not set +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_UTS_NS=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_VXFS_FS=y +# CONFIG_WATCHDOG is not set +CONFIG_XPS=y diff --git a/target/linux/malta/image/Makefile b/target/linux/malta/image/Makefile new file mode 100644 index 0000000..180e045 --- /dev/null +++ b/target/linux/malta/image/Makefile @@ -0,0 +1,55 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define get_kernel_entry +0x$(shell $(TARGET_CROSS)nm $(1) 2>/dev/null | grep " kernel_entry" | cut -f1 -d ' ') +endef + +define CompressLzma + $(STAGING_DIR_HOST)/bin/lzma e $(1) -lc1 -lp2 -pb2 $(2) +endef + +define CompressGzip + gzip -9n -c $(1) > $(2) +endef + +define MkuImage + mkimage -A mips -O linux -T kernel -a 0x80100000 -C $(1) $(2) \ + -e $(call get_kernel_entry,$(KDIR)/vmlinux.debug) -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(3) $(4) +endef + +define Image/Prepare + cp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf + $(call CompressLzma,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.lzma) + $(call MkuImage,lzma,,$(KDIR)/vmlinux.bin.lzma,$(KDIR)/uImage.lzma) + $(call CompressGzip,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.gz) + $(call MkuImage,gzip,,$(KDIR)/vmlinux.bin.gz,$(KDIR)/uImage.gz) +endef + +define Image/BuildKernel + cp $(KDIR)/uImage.lzma $(BIN_DIR)/$(IMG_PREFIX)-uImage-lzma + cp $(KDIR)/uImage.gz $(BIN_DIR)/$(IMG_PREFIX)-uImage-gzip +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +endef + +define Image/Build/Initramfs + cp $(KDIR)/vmlinux-initramfs.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.elf + cp $(KDIR)/vmlinux-initramfs $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.bin +endef + +define Image/Build + $(call Image/Build/$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/malta/le/config-default b/target/linux/malta/le/config-default new file mode 100644 index 0000000..b5634c6 --- /dev/null +++ b/target/linux/malta/le/config-default @@ -0,0 +1,9 @@ +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32=y +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set diff --git a/target/linux/malta/le/target.mk b/target/linux/malta/le/target.mk new file mode 100644 index 0000000..35fcf4c --- /dev/null +++ b/target/linux/malta/le/target.mk @@ -0,0 +1,10 @@ +ARCH:=mipsel +ARCH_PACKAGES:=malta_mipsel +SUBTARGET:=le +BOARDNAME:=Little Endian +FEATURES:=ramdisk mips16 + +define Target/Description + Build LE firmware images for MIPS Malta CoreLV board running in + little-endian mode +endef diff --git a/target/linux/malta/le64/config-default b/target/linux/malta/le64/config-default new file mode 100644 index 0000000..8b5731e --- /dev/null +++ b/target/linux/malta/le64/config-default @@ -0,0 +1,30 @@ +# CONFIG_32BIT is not set +CONFIG_64BIT=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_BINFMT_ELF32=y +CONFIG_BLOCK_COMPAT=y +CONFIG_COMPAT=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +CONFIG_CPU_MIPS64=y +CONFIG_CPU_MIPS64_R1=y +# CONFIG_CPU_MIPS64_R2 is not set +CONFIG_CPU_MIPSR1=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +# CONFIG_HUGETLBFS is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_MIPS32_N32=y +CONFIG_MIPS32_O32=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y diff --git a/target/linux/malta/le64/target.mk b/target/linux/malta/le64/target.mk new file mode 100644 index 0000000..26b53c1 --- /dev/null +++ b/target/linux/malta/le64/target.mk @@ -0,0 +1,10 @@ +ARCH:=mips64el +ARCH_PACKAGES:=malta_mipsel64 +SUBTARGET:=le64 +BOARDNAME:=Little Endian (64-bits) +FEATURES:=ramdisk + +define Target/Description + Build LE firmware images for MIPS Malta CoreLV board running in + little-endian and 64-bits mode +endef diff --git a/target/linux/malta/patches/330-MIPS-Malta-Mark-kernel-code-and-kernel-data-segments.patch b/target/linux/malta/patches/330-MIPS-Malta-Mark-kernel-code-and-kernel-data-segments.patch new file mode 100644 index 0000000..789be50 --- /dev/null +++ b/target/linux/malta/patches/330-MIPS-Malta-Mark-kernel-code-and-kernel-data-segments.patch @@ -0,0 +1,34 @@ +From 79c7301c922f5023f85805a4ba969ce55f51d0ca Mon Sep 17 00:00:00 2001 +From: Yousong Zhou +Date: Sat, 31 Jan 2015 15:13:12 +0800 +Subject: [PATCH 330/331] MIPS: Malta: Mark kernel code and kernel data + segments as BOOT_MEM_RAM. + +Kexec-tools requires those segments listed as "System RAM" in +/proc/iomem, otherwise, an error message of "Invalid memory segment" +will be emitted when trying to load the ELF kernel image. + +Signed-off-by: Yousong Zhou +--- + arch/mips/mti-malta/malta-memory.c | 9 ++------- + 1 file changed, 2 insertions(+), 7 deletions(-) + +--- a/arch/mips/mti-malta/malta-memory.c ++++ b/arch/mips/mti-malta/malta-memory.c +@@ -112,14 +112,9 @@ fw_memblock_t * __init fw_getmdesc(int e + mdesc[2].base = mdesc[0].base + 0x000f0000UL; + mdesc[2].size = 0x00010000; + +- mdesc[3].type = fw_dontuse; ++ mdesc[3].type = fw_free; + mdesc[3].base = mdesc[0].base + 0x00100000UL; +- mdesc[3].size = CPHYSADDR(PFN_ALIGN((unsigned long)&_end)) - +- 0x00100000UL; +- +- mdesc[4].type = fw_free; +- mdesc[4].base = mdesc[0].base + CPHYSADDR(PFN_ALIGN(&_end)); +- mdesc[4].size = memsize - CPHYSADDR(mdesc[4].base); ++ mdesc[3].size = memsize - CPHYSADDR(mdesc[3].base); + + return &mdesc[0]; + } diff --git a/target/linux/mcs814x/Makefile b/target/linux/mcs814x/Makefile new file mode 100644 index 0000000..af1548f --- /dev/null +++ b/target/linux/mcs814x/Makefile @@ -0,0 +1,31 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=mcs814x +BOARDNAME:=Moschip MCS814x +FEATURES:=usb squashfs low_mem +CPU_TYPE:=arm926ej-s +MAINTAINER:=Florian Fainelli + +KERNEL_PATCHVER:=3.18 + +DEVICE_TYPE:=other + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES := $(filter-out ppp%,$(DEFAULT_PACKAGES)) \ + kmod-usb-core kmod-usb2 kmod-usb-ohci \ + kmod-usb-storage kmod-fs-vfat \ + kmod-nls-cp437 kmod-nls-iso8859-1 kmod-nls-iso8859-15 \ + kmod-nls-utf8 \ + kmod-mcs814x-wdt kmod-ledtrig-usbdev + +KERNELNAME:=zImage dtbs + +$(eval $(call BuildTarget)) diff --git a/target/linux/mcs814x/base-files/etc/config/network b/target/linux/mcs814x/base-files/etc/config/network new file mode 100644 index 0000000..cec7b25 --- /dev/null +++ b/target/linux/mcs814x/base-files/etc/config/network @@ -0,0 +1,21 @@ +# Copyright (C) 2012 OpenWrt.org + +config interface loopback + option ifname lo + option proto static + option ipaddr 127.0.0.1 + option netmask 255.0.0.0 + +config interface lan + option ifname eth0 + option proto static + option ipaddr 192.168.1.1 + option netmask 255.255.255.0 + option ip6assign 60 + +config interface wan6 + option ifname eth0 + option proto dhcpv6 + +config globals globals + option ula_prefix auto diff --git a/target/linux/mcs814x/base-files/etc/uci-defaults/01_leds b/target/linux/mcs814x/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..0c6972d --- /dev/null +++ b/target/linux/mcs814x/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,26 @@ +#!/bin/sh +# +# Copyright (C) 2012 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/mcs814x.sh + +board=$(mcs814x_board_name) + +case "$board" in +dlan-usb-extender) + ucidef_set_led_usbdev "usb" "USB" "dlan-usb-extender:green:usb" "2-1" + ;; +rbt-832) + ucidef_set_led_usbdev "usb1" "USB1" "rbt-832:red:usb0" "1-1" + ucidef_set_led_usbdev "usb2" "USB2" "rbt-832:red:usb1" "1-2" + ucidef_set_led_usbdev "usb3" "USB3" "rbt-832:red:usb2" "1-3" + ucidef_set_led_usbdev "usb4" "USB4" "rbt-832:red:usb3" "1-4" + ucidef_set_led_netdev "eth" "eth" "rbt-832:red:ethernet" "eth0" + ;; +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/mcs814x/base-files/lib/mcs814x.sh b/target/linux/mcs814x/base-files/lib/mcs814x.sh new file mode 100644 index 0000000..e4360fd --- /dev/null +++ b/target/linux/mcs814x/base-files/lib/mcs814x.sh @@ -0,0 +1,42 @@ +#!/bin/sh +# +# Copyright (C) 2012 OpenWrt.org +# + +MCS814X_BOARD_NAME= +MCS814X_MODEL= + +mcs814x_board_detect() { + local machine + local name + + machine=$(cat /proc/device-tree/model) + + case "$machine" in + *"Devolo dLAN USB Extender") + name="dlan-usb-extender" + ;; + *"Tigal RBT-832") + name="rbt-832" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$MCS814X_BOARD_NAME" ] && MCS814X_BOARD_NAME="$name" + [ -z "$MCS814X_MODEL" ] && MCS814X_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$MCS814X_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$MCS814X_MODEL" > /tmp/sysinfo/model +} + +mcs814x_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/mcs814x/base-files/lib/preinit/03_preinit_do_mcs814x.sh b/target/linux/mcs814x/base-files/lib/preinit/03_preinit_do_mcs814x.sh new file mode 100755 index 0000000..d509770 --- /dev/null +++ b/target/linux/mcs814x/base-files/lib/preinit/03_preinit_do_mcs814x.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_mcs814x() { + . /lib/mcs814x.sh + + mcs814x_board_detect +} + +boot_hook_add preinit_main do_mcs814x diff --git a/target/linux/mcs814x/config-3.18 b/target/linux/mcs814x/config-3.18 new file mode 100644 index 0000000..427a7c9 --- /dev/null +++ b/target/linux/mcs814x/config-3.18 @@ -0,0 +1,237 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MCS814X=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USES_GETTIMEOFFSET=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_THUMB is not set +CONFIG_BINFMT_MISC=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="earlyprintk" +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_LL_UART_NONE=y +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0x400dc000 +# CONFIG_DEBUG_UART_PL01X is not set +CONFIG_DEBUG_UART_VIRT=0xf00dc000 +# CONFIG_DEBUG_USER is not set +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_FIQ=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_MCS814X=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MCS814X=y +CONFIG_HZ_FIXED=0 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_KALLSYMS=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LIBCRC32C=y +CONFIG_LIBFDT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_DLAN_USB_EXT=y +CONFIG_MACH_RBT_832=y +CONFIG_MCS8140=y +CONFIG_MCS814X_PHY=y +# CONFIG_MCS814X_WATCHDOG is not set +CONFIG_MDIO_BOARDINFO=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_IMPA7 is not set +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_ROOTFS_SPLIT is not set +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" +CONFIG_MTD_SPLIT_UIMAGE_FW=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_KEY=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-15" +CONFIG_NO_BOOTMEM=y +CONFIG_NUPORT_ETHERNET_DRIVER=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PARTITION_ADVANCED is not set +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PHYS_OFFSET=0x00000000 +# CONFIG_PREEMPT_RCU is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +# CONFIG_SCHED_HRTICK is not set +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_SWAP is not set +CONFIG_SWIOTLB=y +# CONFIG_SYN_COOKIES is not set +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFP is not set +# CONFIG_VLAN_8021Q is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y +# CONFIG_WEXT_PRIV is not set +# CONFIG_WEXT_SPY is not set +# CONFIG_WIRELESS_EXT is not set +CONFIG_XFRM_ALGO=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/dlan-usb-extender.dts b/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/dlan-usb-extender.dts new file mode 100644 index 0000000..59830e8 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/dlan-usb-extender.dts @@ -0,0 +1,68 @@ +/* + * dlan-usb-extender.dts - Device Tree file for Devolo dLAN USB Extender + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2 + */ + +/dts-v1/; +/include/ "mcs8140.dtsi" + +/ { + model = "Devolo dLAN USB Extender"; + compatible = "devolo,dlan-usb-extender", "moschip,mcs8140", "moschip,mcs814x"; + + chosen { + bootargs = "mem=16M console=ttyS0,57600 earlyprintk"; + }; + + ahb { + vci { + eth0: ethernet@40084000 { + phy = <&phy0>; + phy-mode = "mii"; + + phy0: ethernet-phy@0 { + reg = <8>; + }; + }; + + adc { + sdram: memory@0,0 { + reg = <0 0 0x1000000>; + }; + + nor: flash@7,0 { + + partition@0 { + label = "ArmBoot"; + reg = <0 0x30000>; + }; + partition@30000 { + label = "Config1"; + reg = <0x30000 0x10000>; + }; + partition@40000 { + label = "Config2"; + reg = <0x40000 0x10000>; + }; + partition@50000 { + label = "linux"; + reg = <0x50000 0x4C0000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + usb { + label = "dlan-usb-extender:green:usb"; + gpios = <&gpio 19 0>; // gpio 19 active high + }; + }; + }; + }; +}; + diff --git a/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/mcs8140.dtsi b/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/mcs8140.dtsi new file mode 100644 index 0000000..b7e8eb4 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/mcs8140.dtsi @@ -0,0 +1,189 @@ +/* + * mcs8140.dtsi - Device Tree Include file for Moschip MCS8140 family SoC + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Moschip MCS8140 family SoC"; + compatible = "moschip,mcs8140"; + interrupt-parent = <&intc>; + + aliases { + serial0 = &uart0; + eth0 = ð0; + }; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vci { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + eth0: ethernet@40084000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "moschip,nuport-mac"; + reg = <0x40084000 0xd8 // mac + 0x40080000 0x58>; // dma channels + interrupts = <4 5 29>; /* tx, rx, link */ + nuport-mac,buffer-shifting; + nuport-mac,link-activity = <0>; + }; + + tso@40088000 { + reg = <0x40088000 0x1c>; + interrupts = <7>; + }; + + i2s@4008c000 { + compatible = "moschip,mcs814x-i2s"; + reg = <0x4008c000 0x18>; + interrupts = <8>; + }; + + ipsec@40094000 { + compatible = "moschip,mcs814x-ipsec"; + reg = <0x40094000 0x1d8>; + interrupts = <16>; + }; + + rng@4009c000 { + compatible = "moschip,mcs814x-rng"; + reg = <0x4009c000 0x8>; + }; + + memc@400a8000 { + reg = <0x400a8000 0x58>; + }; + + list-proc@400ac0c0 { + reg = <0x400ac0c0 0x38>; + interrupts = <19 27>; // done, error + }; + + gpio: gpio@400d0000 { + compatible = "moschip,mcs814x-gpio"; + reg = <0x400d0000 0x670>; + interrupts = <10>; + #gpio-cells = <2>; + gpio-controller; + num-gpios = <20>; + }; + + eepio: gpio@400d4000 { + compatible = "moschip,mcs814x-gpio"; + reg = <0x400d4000 0x470>; + #gpio-cells = <2>; + gpio-controller; + num-gpios = <4>; + }; + + uart0: serial@400dc000 { + compatible = "ns16550"; + reg = <0x400dc000 0x20>; + clock-frequency = <50000000>; + reg-shift = <2>; + interrupts = <21>; + status = "okay"; + }; + + intc: interrupt-controller@400e4000 { + #interrupt-cells = <1>; + compatible = "moschip,mcs814x-intc"; + interrupt-controller; + interrupt-parent; + reg = <0x400e4000 0x48>; + }; + + m2m@400e8000 { + reg = <0x400e8000 0x24>; + interrupts = <17>; + }; + + eth-filters@400ec000 { + reg = <0x400ec000 0x80>; + }; + + timer: timer@400f800c { + compatible = "moschip,mcs814x-timer"; + interrupts = <0>; + reg = <0x400f800c 0x8>; + }; + + watchdog@400f8014 { + compatible = "moschip,mcs814x-wdt"; + reg = <0x400f8014 0x8>; + }; + + adc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + // 8 64MB chip-selects + ranges = <0 0 0x00000000 0x4000000 // sdram + 1 0 0x04000000 0x4000000 // sdram + 2 0 0x08000000 0x4000000 // reserved + 3 0 0x0c000000 0x4000000 // flash/localbus + 4 0 0x10000000 0x4000000 // flash/localbus + 5 0 0x14000000 0x4000000 // flash/localbus + 6 0 0x18000000 0x4000000 // flash/localbus + 7 0 0x1c000000 0x4000000>; // flash/localbus + + sdram: memory@0,0 { + reg = <0 0 0>; + }; + + nor: flash@7,0 { + reg = <7 0 0x4000000>; + compatible = "cfi-flash"; + bank-width = <1>; // 8-bit external flash + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + usb0: ehci@400fc000 { + compatible = "moschip,mcs814x-ehci", "usb-ehci"; + reg = <0x400fc000 0x74>; + interrupts = <2>; + }; + + usb1: ohci@400fd000 { + compatible = "moschip,mcs814x-ohci", "ohci-le"; + reg = <0x400fd000 0x74>; + interrupts = <11>; + }; + + usb2: ohci@400fe000 { + compatible = "moschip,mcs814x-ohci", "ohci-le"; + reg = <0x400fe000 0x74>; + interrupts = <12>; + }; + + usb3: otg@400ff000 { + compatible = "moschip,msc814x-otg", "usb-otg"; + reg = <0x400ff000 0x1000>; + interrupts = <13>; + }; + }; + + }; +}; diff --git a/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/rbt-832.dts b/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/rbt-832.dts new file mode 100644 index 0000000..9949c8e --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/boot/dts/rbt-832.dts @@ -0,0 +1,89 @@ +/* + * rbt-832.dts - Device Tree file for Tigal RBT-832 + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2 + */ + +/dts-v1/; +/include/ "mcs8140.dtsi" + +/ { + model = "Tigal RBT-832"; + compatible = "tigal,rbt-832", "moschip,mcs8140", "moschip,mcs814x"; + + chosen { + bootargs = "mem=32M console=ttyS0,115200 earlyprintk"; + }; + + ahb { + vci { + eth0: ethernet@40084000 { + nuport-mac,link-activity = <0x01>; + phy = <&phy0>; + phy-mode = "mii"; + + phy0: ethernet-phy@0 { + reg = <1>; + }; + }; + + adc { + sdram: memory@0,0 { + reg = <0 0 0x2000000>; + }; + + nor: flash@7,0 { + + partition@0 { + label = "ArmBoot"; + reg = <0 0x40000>; + }; + partition@30000 { + label = "Enviroment"; + reg = <0x40000 0x20000>; + }; + partition@50000 { + label = "bZimage"; + reg = <0x60000 0x1a0000>; + }; + partition@150000 { + label = "UserFS"; + reg = <0x200000 0x600000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + ethernet { + label = "rbt-832:red:ethernet"; + gpios = <&gpio 0 0>; // gpio 0 active high + }; + + usb0 { + label = "rbt-832:red:usb0"; + gpios = <&gpio 4 0>; // gpio 4 active high + }; + + usb1 { + label = "rbt-832:red:usb1"; + gpios = <&gpio 3 0>; // gpio 3 active high + }; + + usb2 { + label = "rbt-832:red:usb2"; + gpios = <&gpio 2 0>; // gpio 2 active high + }; + + usb3 { + label = "rbt-832:red:usb3"; + gpios = <&gpio 1 0>; // gpio 1 active high + }; + }; + }; + }; +}; + diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Kconfig b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Kconfig new file mode 100644 index 0000000..372c9b8 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Kconfig @@ -0,0 +1,29 @@ +if ARCH_MCS814X + +config MCS8140 + bool + select CPU_ARM926T + +menu "Moschip MCS8140 boards" + +config MACH_DLAN_USB_EXT + bool "Devolo dLAN USB Extender" + select MCS8140 + select NEW_LEDS + select LEDS_CLASS + select LEDS_GPIO + help + Machine support for the Devolo dLAN USB Extender + +config MACH_RBT_832 + bool "Tigal RBT-832" + select MCS8140 + select NEW_LEDS + select LEDS_CLASS + select LEDS_GPIO + help + Machine support for the Tigal RBT-832 board + +endmenu + +endif diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Makefile b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Makefile new file mode 100644 index 0000000..68c5f4a --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Makefile @@ -0,0 +1,5 @@ +obj-y += clock.o +obj-y += common.o +obj-y += irq.o +obj-y += timer.o +obj-y += board-mcs8140-dt.o diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Makefile.boot b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Makefile.boot new file mode 100644 index 0000000..b572507 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/Makefile.boot @@ -0,0 +1,4 @@ + zreladdr-y := 0x00008000 + +dtb-$(CONFIG_MACH_DLAN_USB_EXT) += dlan-usb-extender.dtb +dtb-$(CONFIG_MACH_RBT_832) += rbt-832.dtb diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/board-mcs8140-dt.c b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/board-mcs8140-dt.c new file mode 100644 index 0000000..0d11450 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/board-mcs8140-dt.c @@ -0,0 +1,45 @@ +/* + * Setup code for Moschip MCS8140-based board using Device Tree + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2. + */ +#include +#include +#include +#include +#include +#include + +#include "common.h" + +#include +#include +#include +#include +#include + +static void __init mcs814x_dt_device_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + mcs814x_init_machine(); +} + +static const char *mcs8140_dt_board_compat[] __initdata = { + "moschip,mcs8140", + NULL, /* sentinel */ +}; + +DT_MACHINE_START(mcs8140_dt, "Moschip MCS8140 board") + /* Maintainer: Florian Fainelli */ + .map_io = mcs814x_map_io, + .init_early = mcs814x_clk_init, + .init_irq = mcs814x_of_irq_init, + .init_time = mcs814x_timer_init, + .init_machine = mcs814x_dt_device_init, + .restart = mcs814x_restart, + .dt_compat = mcs8140_dt_board_compat, + .handle_irq = mcs814x_handle_irq, +MACHINE_END + diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/clock.c b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/clock.c new file mode 100644 index 0000000..413bfec --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/clock.c @@ -0,0 +1,271 @@ +/* + * Moschip MCS814x clock routines + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2 + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" + +#define KHZ 1000 +#define MHZ (KHZ * KHZ) + +struct clk_ops { + unsigned long (*get_rate)(struct clk *clk); + int (*set_rate)(struct clk *clk, unsigned long rate); + struct clk *(*get_parent)(struct clk *clk); + int (*enable)(struct clk *clk, int enable); +}; + +struct clk { + struct clk *parent; /* parent clk */ + unsigned long rate; /* clock rate in Hz */ + unsigned long divider; /* clock divider */ + u32 usecount; /* reference count */ + struct clk_ops *ops; /* clock operation */ + u32 enable_reg; /* clock enable register */ + u32 enable_mask; /* clock enable mask */ +}; + +static unsigned long clk_divide_parent(struct clk *clk) +{ + if (clk->parent && clk->divider) + return clk_get_rate(clk->parent) / clk->divider; + else + return 0; +} + +static int clk_local_onoff_enable(struct clk *clk, int enable) +{ + u32 tmp; + + /* no enable_reg means the clock is always enabled */ + if (!clk->enable_reg) + return 0; + + tmp = readl_relaxed(mcs814x_sysdbg_base + clk->enable_reg); + if (!enable) + tmp &= ~clk->enable_mask; + else + tmp |= clk->enable_mask; + + writel_relaxed(tmp, mcs814x_sysdbg_base + clk->enable_reg); + + return 0; +} + +static struct clk_ops default_clk_ops = { + .get_rate = clk_divide_parent, + .enable = clk_local_onoff_enable, +}; + +static DEFINE_SPINLOCK(clocks_lock); + +static const unsigned long cpu_freq_table[] = { + 175000, + 300000, + 125000, + 137500, + 212500, + 250000, + 162500, + 187500, + 162500, + 150000, + 225000, + 237500, + 200000, + 262500, + 275000, + 287500 +}; + +static struct clk clk_cpu; + +/* System clock is fixed at 50Mhz */ +static struct clk clk_sys = { + .rate = 50 * MHZ, +}; + +static struct clk clk_sdram; + +static struct clk clk_timer0 = { + .parent = &clk_sdram, + .divider = 2, + .ops = &default_clk_ops, +}; + +static struct clk clk_timer1_2 = { + .parent = &clk_sys, +}; + +/* Watchdog clock is system clock / 128 */ +static struct clk clk_wdt = { + .parent = &clk_sys, + .divider = 128, + .ops = &default_clk_ops, +}; + +static struct clk clk_emac = { + .ops = &default_clk_ops, + .enable_reg = SYSDBG_SYSCTL, + .enable_mask = SYSCTL_EMAC, +}; + +static struct clk clk_ephy = { + .ops = &default_clk_ops, + .enable_reg = SYSDBG_PLL_CTL, + .enable_mask = ~SYSCTL_EPHY, /* active low */ +}; + +static struct clk clk_cipher = { + .ops = &default_clk_ops, + .enable_reg = SYSDBG_SYSCTL, + .enable_mask = SYSCTL_CIPHER, +}; + +#define CLK(_dev, _con, _clk) \ +{ .dev_id = (_dev), .con_id = (_con), .clk = (_clk) }, + +static struct clk_lookup mcs814x_chip_clks[] = { + CLK("cpu", NULL, &clk_cpu) + CLK("sys", NULL, &clk_sys) + CLK("sdram", NULL, &clk_sdram) + /* 32-bits timer0 */ + CLK("timer0", NULL, &clk_timer0) + /* 16-bits timer1 */ + CLK("timer1", NULL, &clk_timer1_2) + /* 64-bits timer2, same as timer 1 */ + CLK("timer2", NULL, &clk_timer1_2) + CLK(NULL, "wdt", &clk_wdt) + CLK(NULL, "emac", &clk_emac) + CLK(NULL, "ephy", &clk_ephy) + CLK(NULL, "cipher", &clk_cipher) +}; + +static void local_clk_disable(struct clk *clk) +{ + WARN_ON(!clk->usecount); + + if (clk->usecount > 0) { + clk->usecount--; + + if ((clk->usecount == 0) && (clk->ops->enable)) + clk->ops->enable(clk, 0); + + if (clk->parent) + local_clk_disable(clk->parent); + } +} + +static int local_clk_enable(struct clk *clk) +{ + int ret = 0; + + if (clk->parent) + ret = local_clk_enable(clk->parent); + + if (ret) + return ret; + + if ((clk->usecount == 0) && (clk->ops->enable)) + ret = clk->ops->enable(clk, 1); + + if (!ret) + clk->usecount++; + else if (clk->parent && clk->parent->ops->enable) + local_clk_disable(clk->parent); + + return ret; +} + +int clk_enable(struct clk *clk) +{ + int ret; + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + ret = local_clk_enable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + local_clk_disable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + if (unlikely(IS_ERR_OR_NULL(clk))) + return 0; + + if (clk->rate) + return clk->rate; + + if (clk->ops && clk->ops->get_rate) + return clk->ops->get_rate(clk); + + return clk_get_rate(clk->parent); +} +EXPORT_SYMBOL(clk_get_rate); + +struct clk *clk_get_parent(struct clk *clk) +{ + unsigned long flags; + + if (unlikely(IS_ERR_OR_NULL(clk))) + return NULL; + + if (!clk->ops || !clk->ops->get_parent) + return clk->parent; + + spin_lock_irqsave(&clocks_lock, flags); + clk->parent = clk->ops->get_parent(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + + return clk->parent; +} +EXPORT_SYMBOL(clk_get_parent); + +void __init mcs814x_clk_init(void) +{ + u32 bs1; + u8 cpu_freq; + + clkdev_add_table(mcs814x_chip_clks, ARRAY_SIZE(mcs814x_chip_clks)); + + /* read the bootstrap registers to know the exact clocking scheme */ + bs1 = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS1); + cpu_freq = (bs1 >> CPU_FREQ_SHIFT) & CPU_FREQ_MASK; + + pr_info("CPU frequency: %lu (kHz)\n", cpu_freq_table[cpu_freq]); + clk_cpu.rate = cpu_freq * KHZ; + + /* read SDRAM frequency */ + if (bs1 & SDRAM_FREQ_BIT) + clk_sdram.rate = 100 * MHZ; + else + clk_sdram.rate = 133 * MHZ; + + pr_info("SDRAM frequency: %lu (MHz)\n", clk_sdram.rate / MHZ); +} + diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/common.c b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/common.c new file mode 100644 index 0000000..3f1be1f --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/common.c @@ -0,0 +1,166 @@ +/* + * arch/arm/mach-mcs814x/common.c + * + * Core functions for Moschip MCS814x SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +void __iomem *mcs814x_sysdbg_base; + +static struct map_desc mcs814x_io_desc[] __initdata = { + { + .virtual = MCS814X_IO_BASE, + .pfn = __phys_to_pfn(MCS814X_IO_START), + .length = MCS814X_IO_SIZE, + .type = MT_DEVICE + }, +}; + +struct cpu_mode { + const char *name; + int gpio_start; + int gpio_end; +}; + +static const struct cpu_mode cpu_modes[] = { + { + .name = "I2S", + .gpio_start = 4, + .gpio_end = 8, + }, + { + .name = "UART", + .gpio_start = 4, + .gpio_end = 9, + }, + { + .name = "External MII", + .gpio_start = 0, + .gpio_end = 16, + }, + { + .name = "Normal", + .gpio_start = -1, + .gpio_end = -1, + }, +}; + +static void mcs814x_eth_hardware_filter_set(u8 value) +{ + u32 reg; + + reg = readl_relaxed(MCS814X_VIRT_BASE + MCS814X_DBGLED); + if (value) + reg |= 0x80; + else + reg &= ~0x80; + writel_relaxed(reg, MCS814X_VIRT_BASE + MCS814X_DBGLED); +} + +static void mcs814x_eth_led_cfg_set(u8 cfg) +{ + u32 reg; + + reg = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS2); + reg &= ~LED_CFG_MASK; + reg |= cfg; + writel_relaxed(reg, mcs814x_sysdbg_base + SYSDBG_BS2); +} + +static void mcs814x_eth_buffer_shifting_set(u8 value) +{ + u8 reg; + + reg = readb_relaxed(mcs814x_sysdbg_base + SYSDBG_SYSCTL_MAC); + if (value) + reg |= BUF_SHIFT_BIT; + else + reg &= ~BUF_SHIFT_BIT; + writeb_relaxed(reg, mcs814x_sysdbg_base + SYSDBG_SYSCTL_MAC); +} + +static struct of_device_id mcs814x_eth_ids[] __initdata = { + { .compatible = "moschip,nuport-mac", }, + { /* sentinel */ }, +}; + +/* Configure platform specific knobs based on ethernet device node + * properties */ +static void mcs814x_eth_init(void) +{ + struct device_node *np; + const unsigned int *intspec; + + np = of_find_matching_node(NULL, mcs814x_eth_ids); + if (!np) + return; + + /* hardware filter must always be enabled */ + mcs814x_eth_hardware_filter_set(1); + + intspec = of_get_property(np, "nuport-mac,buffer-shifting", NULL); + if (!intspec) + mcs814x_eth_buffer_shifting_set(0); + else + mcs814x_eth_buffer_shifting_set(1); + + intspec = of_get_property(np, "nuport-mac,link-activity", NULL); + if (intspec) + mcs814x_eth_led_cfg_set(be32_to_cpup(intspec)); + + of_node_put(np); +} + +void __init mcs814x_init_machine(void) +{ + u32 bs2, cpu_mode; + int gpio; + + bs2 = readl_relaxed(mcs814x_sysdbg_base + SYSDBG_BS2); + cpu_mode = (bs2 >> CPU_MODE_SHIFT) & CPU_MODE_MASK; + + pr_info("CPU mode: %s\n", cpu_modes[cpu_mode].name); + + /* request the gpios since the pins are muxed for functionnality */ + for (gpio = cpu_modes[cpu_mode].gpio_start; + gpio == cpu_modes[cpu_mode].gpio_end; gpio++) { + if (gpio != -1) + gpio_request(gpio, cpu_modes[cpu_mode].name); + } + + mcs814x_eth_init(); +} + +void __init mcs814x_map_io(void) +{ + iotable_init(mcs814x_io_desc, ARRAY_SIZE(mcs814x_io_desc)); + + mcs814x_sysdbg_base = ioremap(MCS814X_IO_START + MCS814X_SYSDBG, + MCS814X_SYSDBG_SIZE); + if (!mcs814x_sysdbg_base) + panic("unable to remap sysdbg base"); +} + +void mcs814x_restart(enum reboot_mode mode, const char *cmd) +{ + writel_relaxed(~(1 << 31), mcs814x_sysdbg_base); +} diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/common.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/common.h new file mode 100644 index 0000000..4a6c9ad --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/common.h @@ -0,0 +1,16 @@ +#ifndef __ARCH_MCS814X_COMMON_H +#define __ARCH_MCS814X_COMMON_H + +#include +#include + +void mcs814x_map_io(void); +void mcs814x_clk_init(void); +void mcs814x_of_irq_init(void); +void mcs814x_init_machine(void); +void mcs814x_handle_irq(struct pt_regs *regs); +void mcs814x_restart(enum reboot_mode mode, const char *cmd); +void mcs814x_timer_init(void); +extern void __iomem *mcs814x_sysdbg_base; + +#endif /* __ARCH_MCS814X_COMMON_H */ diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/cpu.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/cpu.h new file mode 100644 index 0000000..1ef3c4a --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/cpu.h @@ -0,0 +1,16 @@ +#ifndef __ASM_ARCH_CPU_H__ +#define __ASM_ARCH_CPU_H__ + +#include + +#define MCS8140_ID 0x41069260 /* ARM926EJ-S */ +#define MCS814X_MASK 0xff0ffff0 + +#ifdef CONFIG_MCS8140 +/* Moschip MCS8140 is based on an ARM926EJ-S core */ +#define soc_is_mcs8140() ((read_cpuid_id() & MCS814X_MASK) == MCS8140_ID) +#else +#define soc_is_mcs8140() (0) +#endif /* !CONFIG_MCS8140 */ + +#endif /* __ASM_ARCH_CPU_H__ */ diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/debug-macro.S b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/debug-macro.S new file mode 100644 index 0000000..93ecea4 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/debug-macro.S @@ -0,0 +1,11 @@ +#include + + .macro addruart, rp, rv, tmp + ldr \rp, =MCS814X_PHYS_BASE + ldr \rv, =MCS814X_VIRT_BASE + orr \rp, \rp, #MCS814X_UART + orr \rv, \rv, #MCS814X_UART + .endm + +#define UART_SHIFT 2 +#include diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/entry-macro.S b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/entry-macro.S new file mode 100644 index 0000000..16d2d6d --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/entry-macro.S @@ -0,0 +1,6 @@ +#include + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/gpio.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/gpio.h new file mode 100644 index 0000000..20240c2 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/gpio.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +/* new generic GPIO API */ +#include + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep + +static inline int gpio_to_irq(unsigned gpio) +{ + return -EINVAL; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return -EINVAL; +} + +#endif diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/hardware.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/hardware.h new file mode 100644 index 0000000..529f648 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/hardware.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2003 Artec Design Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include "mcs814x.h" + +#endif + diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/io.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/io.h new file mode 100644 index 0000000..80e56f6 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/io.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2003 Artec Design Ltd. + * Copyright (C) 2012, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * We don't support ins[lb]/outs[lb]. Make them fault. + */ +#define __raw_readsb(p, d, l) do { *(int *)0 = 0; } while (0) +#define __raw_readsl(p, d, l) do { *(int *)0 = 0; } while (0) +#define __raw_writesb(p, d, l) do { *(int *)0 = 0; } while (0) +#define __raw_writesl(p, d, l) do { *(int *)0 = 0; } while (0) + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/irqs.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/irqs.h new file mode 100644 index 0000000..7b9e07c --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/irqs.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2003 Artec Design Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#define FIQ_START 0 + +#define NR_IRQS 32 + +#endif diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/mcs814x.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/mcs814x.h new file mode 100644 index 0000000..8252d33 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/mcs814x.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2003 Artec Design Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_MCS814X_H +#define __ASM_ARCH_MCS814X_H + +#define MCS814X_IO_BASE 0xF0000000 +#define MCS814X_IO_START 0x40000000 +#define MCS814X_IO_SIZE 0x00100000 + +/* IRQ controller register offset */ +#define MCS814X_IRQ_ICR 0x00 +#define MCS814X_IRQ_ISR 0x04 +#define MCS814X_IRQ_MASK 0x20 +#define MCS814X_IRQ_STS0 0x40 + +#define MCS814X_PHYS_BASE 0x40000000 +#define MCS814X_VIRT_BASE MCS814X_IO_BASE + +#define MCS814X_UART 0x000DC000 +#define MCS814X_DBGLED 0x000EC000 +#define MCS814X_SYSDBG 0x000F8000 +#define MCS814X_SYSDBG_SIZE 0x50 + +/* System configuration and bootstrap registers */ +#define SYSDBG_BS1 0x00 +#define CPU_FREQ_SHIFT 27 +#define CPU_FREQ_MASK 0x0F +#define SDRAM_FREQ_BIT (1 << 22) + +#define SYSDBG_BS2 0x04 +#define LED_CFG_MASK 0x03 +#define CPU_MODE_SHIFT 23 +#define CPU_MODE_MASK 0x03 + +#define SYSDBG_SYSCTL_MAC 0x1d +#define BUF_SHIFT_BIT (1 << 0) + +#define SYSDBG_SYSCTL 0x08 +#define SYSCTL_EMAC (1 << 0) +#define SYSCTL_EPHY (1 << 0) /* active low */ +#define SYSCTL_CIPHER (1 << 16) + +#define SYSDBG_PLL_CTL 0x3C + +#endif /* __ASM_ARCH_MCS814X_H */ + diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/param.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/param.h new file mode 100644 index 0000000..7ffe70b --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/param.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2003 Artec Design Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_PARAM_H +#define __ASM_ARCH_PARAM_H + +#define HZ 100 + +#endif diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/system.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/system.h new file mode 100644 index 0000000..cf5453d --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/system.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2003 Artec Design Ltd. + * Copyright (C) 2012 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} +#endif diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/timex.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/timex.h new file mode 100644 index 0000000..f05c8ee --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/timex.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2003 Artec Design Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* + * Timex specification for MCS814X + */ +#define CLOCK_TICK_RATE 100 + +#endif diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/uncompress.h b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/uncompress.h new file mode 100644 index 0000000..cf3ed9a --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/include/mach/uncompress.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include +#include +#include +#include + +#define UART_SHIFT (2) + +/* cannot be static because the code will be inlined */ +void __iomem *uart_base; + +static inline void putc(int c) +{ + while (!(__raw_readb(uart_base + (UART_LSR << UART_SHIFT)) & UART_LSR_TEMT)); + __raw_writeb(c, uart_base + (UART_TX << UART_SHIFT)); +} + +static inline void flush(void) +{ +} + +static inline void arch_decomp_setup(void) +{ + if (soc_is_mcs8140()) + uart_base = (void __iomem *)(MCS814X_PHYS_BASE +MCS814X_UART); +} + +#define arch_decomp_wdog() + +#endif diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/irq.c b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/irq.c new file mode 100644 index 0000000..d1cab68 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/irq.c @@ -0,0 +1,94 @@ +/* + * Moschip MCS814x generic interrupt controller routines + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under the GPLv2 + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static void __iomem *mcs814x_intc_base; +static struct irq_domain *domain; + +static void __init mcs814x_alloc_gc(void __iomem *base, unsigned int irq_start, + unsigned int num) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + if (irq_alloc_domain_generic_chips(domain, num, 1, "mcs814x-intc", handle_level_irq, + IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0)) + panic("unable to allocate domain generic irq chip"); + + gc = irq_get_domain_generic_chip(domain, irq_start); + if (!gc) + panic("unable to get generic irq chip"); + + gc->reg_base = base; + ct = gc->chip_types; + ct->chip.irq_ack = irq_gc_unmask_enable_reg; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->regs.mask = MCS814X_IRQ_MASK; + ct->regs.enable = MCS814X_IRQ_ICR; + + /* Clear all interrupts */ + writel_relaxed(0xffffffff, base + MCS814X_IRQ_ICR); +} + +asmlinkage void __exception_irq_entry mcs814x_handle_irq(struct pt_regs *regs) +{ + u32 status, irq; + + do { + /* read the status register */ + status = __raw_readl(mcs814x_intc_base + MCS814X_IRQ_STS0); + if (!status) + break; + + irq = ffs(status) - 1; + status |= (1 << irq); + /* clear the interrupt */ + __raw_writel(status, mcs814x_intc_base + MCS814X_IRQ_STS0); + /* call the generic handler */ + handle_domain_irq(domain, irq, regs); + + } while (1); +} + +static const struct of_device_id mcs814x_intc_ids[] = { + { .compatible = "moschip,mcs814x-intc" }, + { /* sentinel */ }, +}; + +void __init mcs814x_of_irq_init(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, mcs814x_intc_ids); + if (!np) + panic("unable to find compatible intc node in dtb\n"); + + mcs814x_intc_base = of_iomap(np, 0); + if (!mcs814x_intc_base) + panic("unable to map intc cpu registers\n"); + + domain = irq_domain_add_linear(np, 32, &irq_generic_chip_ops, NULL); + if (!domain) + panic("unable to add irq domain\n"); + irq_set_default_host(domain); + + of_node_put(np); + + mcs814x_alloc_gc(mcs814x_intc_base, 0, 32); +} + diff --git a/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/timer.c b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/timer.c new file mode 100644 index 0000000..31d0ba6 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/timer.c @@ -0,0 +1,132 @@ +/* + * Moschip MCS814x timer routines + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2 + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Timer block registers */ +#define TIMER_VAL 0x00 +#define TIMER_CTL 0x04 +#define TIMER_CTL_EN 0x01 +#define TIMER_CTL_DBG 0x02 + +static u32 last_reload; +static u32 timer_correct; +static u32 clock_rate; +static u32 timer_reload_value; +static void __iomem *mcs814x_timer_base; + +static inline u32 ticks2usecs(u32 x) +{ + return x / (clock_rate / 1000000); +} + +/* + * Returns number of ms since last clock interrupt. Note that interrupts + * will have been disabled by do_gettimeoffset() + */ +static u32 mcs814x_gettimeoffset(void) +{ + u32 ticks = readl_relaxed(mcs814x_timer_base + TIMER_VAL); + + if (ticks < last_reload) + return ticks2usecs(ticks + (u32)(0xffffffff - last_reload)); + else + return ticks2usecs(ticks - last_reload); +} + + +static irqreturn_t mcs814x_timer_interrupt(int irq, void *dev_id) +{ + u32 count = readl_relaxed(mcs814x_timer_base + TIMER_VAL); + + /* take into account delay up to this moment */ + last_reload = count + timer_correct + timer_reload_value; + + if (last_reload < timer_reload_value) { + last_reload = timer_reload_value; + } else { + if (timer_correct == 0) + timer_correct = readl_relaxed(mcs814x_timer_base + TIMER_VAL) - count; + } + writel_relaxed(last_reload, mcs814x_timer_base + TIMER_VAL); + + timer_tick(); + + return IRQ_HANDLED; +} + +static struct of_device_id mcs814x_timer_ids[] = { + { .compatible = "moschip,mcs814x-timer" }, + { /* sentinel */ }, +}; + +static int __init mcs814x_of_timer_init(void) +{ + struct device_node *np; + int irq; + + np = of_find_matching_node(NULL, mcs814x_timer_ids); + if (!np) + panic("unable to find compatible timer node in dtb"); + + mcs814x_timer_base = of_iomap(np, 0); + if (!mcs814x_timer_base) + panic("unable to remap timer cpu registers"); + + irq = irq_of_parse_and_map(np, 0); + if (!irq) + panic("no interrupts property/mapping failed for timer"); + + return irq; +} + +void __init mcs814x_timer_init(void) +{ + struct clk *clk; + int irq; + + arch_gettimeoffset = mcs814x_gettimeoffset; + + clk = clk_get_sys("timer0", NULL); + if (IS_ERR_OR_NULL(clk)) + panic("unable to get timer0 clock"); + + clock_rate = clk_get_rate(clk); + + irq = mcs814x_of_timer_init(); + + pr_info("Timer frequency: %d (kHz)\n", clock_rate / 1000); + + timer_reload_value = 0xffffffff - (clock_rate / HZ); + + /* disable timer */ + writel_relaxed(~TIMER_CTL_EN, mcs814x_timer_base + TIMER_CTL); + writel_relaxed(timer_reload_value, mcs814x_timer_base + TIMER_VAL); + last_reload = timer_reload_value; + + if (request_irq(irq, mcs814x_timer_interrupt, + IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + "mcs814x-timer", NULL)) + panic("unable to request timer0 irq %d", irq); + + /* enable timer, stop timer in debug mode */ + writel_relaxed(TIMER_CTL_EN | TIMER_CTL_DBG, + mcs814x_timer_base + TIMER_CTL); +} diff --git a/target/linux/mcs814x/files-3.18/drivers/char/hw_random/mcs814x-rng.c b/target/linux/mcs814x/files-3.18/drivers/char/hw_random/mcs814x-rng.c new file mode 100644 index 0000000..cb3f339 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/char/hw_random/mcs814x-rng.c @@ -0,0 +1,121 @@ +/* + * RNG driver for Moschip MCS814x SoC + * + * Copyright 2012 (C), Florian Fainelli + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define STAT 0x00 +#define RND 0x04 + +struct mcs814x_rng_priv { + void __iomem *regs; +}; + +static int mcs814x_rng_data_read(struct hwrng *rng, u32 *buffer) +{ + struct mcs814x_rng_priv *priv = (struct mcs814x_rng_priv *)rng->priv; + + *buffer = readl_relaxed(priv->regs + RND); + + return 4; +} + +static int mcs814x_rng_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mcs814x_rng_priv *priv; + struct hwrng *rng; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto out; + } + + rng = kzalloc(sizeof(*rng), GFP_KERNEL); + if (!rng) { + ret = -ENOMEM; + goto out_priv; + } + + platform_set_drvdata(pdev, rng); + rng->priv = (unsigned long)priv; + rng->name = pdev->name; + rng->data_read = mcs814x_rng_data_read; + + priv->regs = devm_ioremap_resource(&pdev->dev, res); + if (!priv->regs) { + ret = -ENOMEM; + goto out_rng; + } + + ret = hwrng_register(rng); + if (ret) { + dev_err(&pdev->dev, "failed to register hwrng driver\n"); + goto out; + } + + dev_info(&pdev->dev, "registered\n"); + + return ret; + +out_rng: + platform_set_drvdata(pdev, NULL); + kfree(rng); +out_priv: + kfree(priv); +out: + return ret; +} + +static int mcs814x_rng_remove(struct platform_device *pdev) +{ + struct hwrng *rng = platform_get_drvdata(pdev); + struct mcs814x_rng_priv *priv = (struct mcs814x_rng_priv *)rng->priv; + + hwrng_unregister(rng); + kfree(priv); + kfree(rng); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static const struct of_device_id mcs814x_rng_ids[] = { + { .compatible = "moschip,mcs814x-rng", }, + { /* sentinel */ }, +}; + +static struct platform_driver mcs814x_rng_driver = { + .driver = { + .name = "mcs814x-rng", + .owner = THIS_MODULE, + .of_match_table = mcs814x_rng_ids, + }, + .probe = mcs814x_rng_probe, + .remove = mcs814x_rng_remove, +}; + +module_platform_driver(mcs814x_rng_driver); + +MODULE_AUTHOR("Florian Fainelli "); +MODULE_DESCRIPTION("H/W Random Number Generator (RNG) for Moschip MCS814x"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mcs814x/files-3.18/drivers/gpio/gpio-mcs814x.c b/target/linux/mcs814x/files-3.18/drivers/gpio/gpio-mcs814x.c new file mode 100644 index 0000000..c8a6509 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/gpio/gpio-mcs814x.c @@ -0,0 +1,148 @@ +/* + * Moschip MCS814x GPIO support + * + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under the GPLv2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mcs814x_gpio_chip { + void __iomem *regs; + struct gpio_chip chip; +}; + +#define GPIO_PIN 0x00 +#define GPIO_DIR 0x04 + +#define to_mcs814x_gpio_chip(x) container_of(x, struct mcs814x_gpio_chip, chip) + +static int mcs814x_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip); + + return readl_relaxed(mcs814x->regs + GPIO_PIN) & (1 << offset); +} + +static void mcs814x_gpio_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip); + u32 mask; + + mask = readl_relaxed(mcs814x->regs + GPIO_PIN); + if (value) + mask |= (1 << offset); + else + mask &= ~(1 << offset); + writel_relaxed(mask, mcs814x->regs + GPIO_PIN); +} + +static int mcs814x_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip); + u32 mask; + + mask = readl_relaxed(mcs814x->regs + GPIO_DIR); + mask &= ~(1 << offset); + writel_relaxed(mask, mcs814x->regs + GPIO_DIR); + + return 0; +} + +static int mcs814x_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + struct mcs814x_gpio_chip *mcs814x = to_mcs814x_gpio_chip(chip); + u32 mask; + + mask = readl_relaxed(mcs814x->regs + GPIO_DIR); + mask |= (1 << offset); + writel_relaxed(mask, mcs814x->regs + GPIO_DIR); + + return 0; +} + +static int mcs814x_gpio_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mcs814x_gpio_chip *mcs814x_chip; + int ret; + const unsigned int *num_gpios; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + num_gpios = of_get_property(pdev->dev.of_node, "num-gpios", NULL); + if (!num_gpios) + dev_err(&pdev->dev, "FIXME: no num-gpios property\n"); + + mcs814x_chip = kzalloc(sizeof(*mcs814x_chip), GFP_KERNEL); + if (!mcs814x_chip) + return -ENOMEM; + + mcs814x_chip->regs = devm_ioremap_resource(&pdev->dev, res); + if (!mcs814x_chip->regs) { + ret = -ENOMEM; + goto out; + } + + platform_set_drvdata(pdev, mcs814x_chip); + +#ifdef CONFIG_OF_GPIO + mcs814x_chip->chip.of_node = pdev->dev.of_node; +#endif + + mcs814x_chip->chip.label = pdev->name; + mcs814x_chip->chip.get = mcs814x_gpio_get; + mcs814x_chip->chip.set = mcs814x_gpio_set; + mcs814x_chip->chip.direction_input = mcs814x_gpio_direction_input; + mcs814x_chip->chip.direction_output = mcs814x_gpio_direction_output; + mcs814x_chip->chip.ngpio = be32_to_cpup(num_gpios); + /* we want dynamic base allocation */ + mcs814x_chip->chip.base = -1; + + ret = gpiochip_add(&mcs814x_chip->chip); + if (ret) { + dev_err(&pdev->dev, "failed to register gpiochip\n"); + goto out; + } + + return 0; + +out: + platform_set_drvdata(pdev, NULL); + kfree(mcs814x_chip); + return ret; +} + +static struct of_device_id mcs814x_gpio_ids[] = { + { .compatible = "moschip,mcs814x-gpio" }, + { /* sentinel */ }, +}; + +static struct platform_driver mcs814x_gpio_driver = { + .driver = { + .name = "mcs814x-gpio", + .owner = THIS_MODULE, + .of_match_table = mcs814x_gpio_ids, + }, + .probe = mcs814x_gpio_probe, +}; + +int __init mcs814x_gpio_init(void) +{ + return platform_driver_register(&mcs814x_gpio_driver); +} +postcore_initcall(mcs814x_gpio_init); diff --git a/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/Kconfig b/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/Kconfig new file mode 100644 index 0000000..8fa38a4 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/Kconfig @@ -0,0 +1,4 @@ +config NUPORT_ETHERNET_DRIVER + tristate "MCS8140 Ethernet driver" + depends on ETHERNET && ARCH_MCS814X + help diff --git a/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/Makefile b/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/Makefile new file mode 100644 index 0000000..9719c51 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_NUPORT_ETHERNET_DRIVER) += mcs8140.o + +mcs8140-objs := nuport_mac.o diff --git a/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/nuport_mac.c b/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/nuport_mac.c new file mode 100644 index 0000000..a02144e --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/net/ethernet/mcs8140/nuport_mac.c @@ -0,0 +1,1206 @@ +/* + * Moschip MCS8140 Ethernet MAC driver + * + * Copyright (C) 2003, Moschip Semiconductors + * Copyright (C) 2012, Florian Fainelli + * + * Licensed under GPLv2 + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Hardware registers */ +#define MAC_BASE_ADDR ((priv->mac_base)) + +#define CTRL_REG (MAC_BASE_ADDR) +#define MII_BUSY (1 << 0) +#define MII_WRITE (1 << 1) +#define RX_ENABLE (1 << 2) +#define TX_ENABLE (1 << 3) +#define DEFER_CHECK (1 << 5) +#define STRIP_PAD (1 << 8) +#define DRTRY_DISABLE (1 << 10) +#define FULL_DUPLEX (1 << 20) +#define HBD_DISABLE (1 << 28) +#define MAC_ADDR_HIGH_REG (MAC_BASE_ADDR + 0x04) +#define MAC_ADDR_LOW_REG (MAC_BASE_ADDR + 0x08) +#define MII_ADDR_REG (MAC_BASE_ADDR + 0x14) +#define MII_ADDR_SHIFT (11) +#define MII_REG_SHIFT (6) +#define MII_DATA_REG (MAC_BASE_ADDR + 0x18) +/* Link interrupt registers */ +#define LINK_INT_CSR (MAC_BASE_ADDR + 0xD0) +#define LINK_INT_EN (1 << 0) +#define LINK_PHY_ADDR_SHIFT (1) +#define LINK_PHY_REG_SHIFT (6) +#define LINK_BIT_UP_SHIFT (11) +#define LINK_UP (1 << 16) +#define LINK_INT_POLL_TIME (MAC_BASE_ADDR + 0xD4) +#define LINK_POLL_MASK ((1 << 20) - 1) + +#define DMA_CHAN_WIDTH 32 +#define DMA_RX_CHAN 0 +#define DMA_TX_CHAN 2 + +/* Receive DMA registers */ +#define RX_DMA_BASE ((priv->dma_base) + \ + (DMA_CHAN_WIDTH * DMA_RX_CHAN)) +#define RX_BUFFER_ADDR (RX_DMA_BASE + 0x00) +#define RX_MAX_BYTES (RX_DMA_BASE + 0x04) +#define RX_ACT_BYTES (RX_DMA_BASE + 0x08) +#define RX_START_DMA (RX_DMA_BASE + 0x0C) +#define RX_DMA_ENABLE (1 << 0) +#define RX_DMA_RESET (1 << 1) +#define RX_DMA_STATUS_FIFO (1 << 12) +#define RX_DMA_ENH (RX_DMA_BASE + 0x14) +#define RX_DMA_INT_ENABLE (1 << 1) + +/* Transmit DMA registers */ +#define TX_DMA_BASE ((priv->dma_base) + \ + (DMA_CHAN_WIDTH * DMA_TX_CHAN)) +#define TX_BUFFER_ADDR (TX_DMA_BASE + 0x00) +#define TX_PKT_BYTES (TX_DMA_BASE + 0x04) +#define TX_BYTES_SENT (TX_DMA_BASE + 0x08) +#define TX_START_DMA (TX_DMA_BASE + 0x0C) +#define TX_DMA_ENABLE (1 << 0) +#define TX_DMA_START_FRAME (1 << 2) +#define TX_DMA_END_FRAME (1 << 3) +#define TX_DMA_PAD_DISABLE (1 << 8) +#define TX_DMA_CRC_DISABLE (1 << 9) +#define TX_DMA_FIFO_FULL (1 << 16) +#define TX_DMA_FIFO_EMPTY (1 << 17) +#define TX_DMA_STATUS_AVAIL (1 << 18) +#define TX_DMA_RESET (1 << 24) +#define TX_DMA_STATUS (TX_DMA_BASE + 0x10) +#define TX_DMA_ENH (TX_DMA_BASE + 0x14) +#define TX_DMA_ENH_ENABLE (1 << 0) +#define TX_DMA_INT_FIFO (1 << 1) + +#define RX_ALLOC_SIZE SZ_2K +#define MAX_ETH_FRAME_SIZE 1536 +#define RX_SKB_TAILROOM 128 +#define RX_SKB_HEADROOM (RX_ALLOC_SIZE - \ + (MAX_ETH_FRAME_SIZE + RX_SKB_TAILROOM) + 0) + + /* WDT Late COL Lenght COL Type */ +#define ERROR_FILTER_MASK ((1<<14) | (1<<15) | (1<<16) | (1<<17) | (0<<18) | \ + /* MII Dribbling CRC Len/type Control */\ + (1<<19) | (1<<20) | (1<<21) | (0<<24) | (1<<25) | \ + /* Unsup Missed */\ + (1<<26) | (0<<31)) +#define TX_RING_SIZE 30 +#define RX_RING_SIZE 30 + +static inline u32 nuport_mac_readl(void __iomem *reg) +{ + return readl_relaxed(reg); +} + +static inline u8 nuport_mac_readb(void __iomem *reg) +{ + return readb_relaxed(reg); +} + +static inline void nuport_mac_writel(u32 value, void __iomem *reg) +{ + writel_relaxed(value, reg); +} + +static inline void nuport_mac_writeb(u8 value, void __iomem *reg) +{ + writel_relaxed(value, reg); +} + +/* MAC private data */ +struct nuport_mac_priv { + spinlock_t lock; + + void __iomem *mac_base; + void __iomem *dma_base; + + int rx_irq; + int tx_irq; + int link_irq; + struct clk *emac_clk; + struct clk *ephy_clk; + + /* Transmit buffers */ + struct sk_buff *tx_skb[TX_RING_SIZE]; + dma_addr_t tx_addr; + unsigned int valid_txskb[TX_RING_SIZE]; + unsigned int cur_tx; + unsigned int dma_tx; + unsigned int tx_full; + + /* Receive buffers */ + struct sk_buff *rx_skb[RX_RING_SIZE]; + dma_addr_t rx_addr; + unsigned int irq_rxskb[RX_RING_SIZE]; + int pkt_len[RX_RING_SIZE]; + unsigned int cur_rx; + unsigned int dma_rx; + unsigned int rx_full; + + unsigned int first_pkt; + + /* Private data */ + struct napi_struct napi; + struct net_device *dev; + struct platform_device *pdev; + struct mii_bus *mii_bus; + struct phy_device *phydev; + struct device_node *phy_node; + phy_interface_t phy_interface; + int old_link; + int old_duplex; + u32 msg_level; + unsigned int buffer_shifting_len; +}; + +static inline int nuport_mac_mii_busy_wait(struct nuport_mac_priv *priv) +{ + unsigned long curr; + unsigned long finish = jiffies + 3 * HZ; + + do { + curr = jiffies; + if (!(nuport_mac_readl(MII_ADDR_REG) & MII_BUSY)) + return 0; + cpu_relax(); + } while (!time_after_eq(curr, finish)); + + return -EBUSY; +} + +/* Read from PHY registers */ +static int nuport_mac_mii_read(struct mii_bus *bus, + int mii_id, int regnum) +{ + struct net_device *dev = bus->priv; + struct nuport_mac_priv *priv = netdev_priv(dev); + int ret; + u32 val = 0; + + ret = nuport_mac_mii_busy_wait(priv); + if (ret) + return ret; + + val |= (mii_id << MII_ADDR_SHIFT) | (regnum << MII_REG_SHIFT) | MII_BUSY; + nuport_mac_writel(val, MII_ADDR_REG); + ret = nuport_mac_mii_busy_wait(priv); + if (ret) + return ret; + + return nuport_mac_readl(MII_DATA_REG); +} + +static int nuport_mac_mii_write(struct mii_bus *bus, int mii_id, + int regnum, u16 value) +{ + struct net_device *dev = bus->priv; + struct nuport_mac_priv *priv = netdev_priv(dev); + int ret; + u32 val = 0; + + ret = nuport_mac_mii_busy_wait(priv); + if (ret) + return ret; + + val |= (mii_id << MII_ADDR_SHIFT) | (regnum << MII_REG_SHIFT); + val |= MII_BUSY | MII_WRITE; + nuport_mac_writel(value, MII_DATA_REG); + nuport_mac_writel(val, MII_ADDR_REG); + + return nuport_mac_mii_busy_wait(priv); +} + +static int nuport_mac_mii_reset(struct mii_bus *bus) +{ + return 0; +} + +static int nuport_mac_start_tx_dma(struct nuport_mac_priv *priv, + struct sk_buff *skb) +{ + u32 reg; + unsigned int timeout = 2048; + + while (timeout--) { + reg = nuport_mac_readl(TX_START_DMA); + if (!(reg & TX_DMA_ENABLE)) { + netdev_dbg(priv->dev, "dma ready\n"); + break; + } + cpu_relax(); + } + + if (!timeout) + return -EBUSY; + + priv->tx_addr = dma_map_single(&priv->pdev->dev, skb->data, + skb->len, DMA_TO_DEVICE); + if (dma_mapping_error(&priv->pdev->dev, priv->tx_addr)) + return -ENOMEM; + + /* enable enhanced mode */ + nuport_mac_writel(TX_DMA_ENH_ENABLE, TX_DMA_ENH); + nuport_mac_writel(priv->tx_addr, TX_BUFFER_ADDR); + nuport_mac_writel((skb->len) - 1, TX_PKT_BYTES); + wmb(); + reg = TX_DMA_ENABLE | TX_DMA_START_FRAME | TX_DMA_END_FRAME; + nuport_mac_writel(reg, TX_START_DMA); + + return 0; +} + +static void nuport_mac_reset_tx_dma(struct nuport_mac_priv *priv) +{ + u32 reg; + + reg = nuport_mac_readl(TX_START_DMA); + reg |= TX_DMA_RESET; + nuport_mac_writel(reg, TX_START_DMA); +} + +static int nuport_mac_start_rx_dma(struct nuport_mac_priv *priv, + struct sk_buff *skb) +{ + u32 reg; + unsigned int timeout = 2048; + + while (timeout--) { + reg = nuport_mac_readl(RX_START_DMA); + if (!(reg & RX_DMA_ENABLE)) { + netdev_dbg(priv->dev, "dma ready\n"); + break; + } + cpu_relax(); + } + + if (!timeout) + return -EBUSY; + + priv->rx_addr = dma_map_single(&priv->pdev->dev, skb->data, + RX_ALLOC_SIZE, DMA_FROM_DEVICE); + if (dma_mapping_error(&priv->pdev->dev, priv->rx_addr)) + return -ENOMEM; + + nuport_mac_writel(priv->rx_addr, RX_BUFFER_ADDR); + wmb(); + nuport_mac_writel(RX_DMA_ENABLE, RX_START_DMA); + + return 0; +} + +static void nuport_mac_reset_rx_dma(struct nuport_mac_priv *priv) +{ + u32 reg; + + reg = nuport_mac_readl(RX_START_DMA); + reg |= RX_DMA_RESET; + nuport_mac_writel(reg, RX_START_DMA); +} + +/* I suppose this might do something, but I am not sure actually */ +static void nuport_mac_disable_rx_dma(struct nuport_mac_priv *priv) +{ + u32 reg; + + reg = nuport_mac_readl(RX_DMA_ENH); + reg &= ~RX_DMA_INT_ENABLE; + nuport_mac_writel(reg, RX_DMA_ENH); +} + +static void nuport_mac_enable_rx_dma(struct nuport_mac_priv *priv) +{ + u32 reg; + + reg = nuport_mac_readl(RX_DMA_ENH); + reg |= RX_DMA_INT_ENABLE; + nuport_mac_writel(reg, RX_DMA_ENH); +} + +/* Add packets to the transmit queue */ +static int nuport_mac_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + unsigned long flags; + struct nuport_mac_priv *priv = netdev_priv(dev); + int ret; + + if (netif_queue_stopped(dev)) { + netdev_warn(dev, "netif queue was stopped, restarting\n"); + netif_start_queue(dev); + } + + spin_lock_irqsave(&priv->lock, flags); + if (priv->first_pkt) { + ret = nuport_mac_start_tx_dma(priv, skb); + if (ret) { + netif_stop_queue(dev); + spin_unlock_irqrestore(&priv->lock, flags); + netdev_err(dev, "transmit path busy\n"); + return NETDEV_TX_BUSY; + } + priv->first_pkt = 0; + } + + priv->tx_skb[priv->cur_tx] = skb; + dev->stats.tx_bytes += skb->len; + dev->stats.tx_packets++; + priv->valid_txskb[priv->cur_tx] = 1; + priv->cur_tx++; + dev->trans_start = jiffies; + + if (priv->cur_tx >= TX_RING_SIZE) + priv->cur_tx = 0; + + spin_unlock_irqrestore(&priv->lock, flags); + + if (priv->valid_txskb[priv->cur_tx]) { + priv->tx_full = 1; + netdev_err(dev, "stopping queue\n"); + netif_stop_queue(dev); + } + + return NETDEV_TX_OK; +} + +static void nuport_mac_adjust_link(struct net_device *dev) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + struct phy_device *phydev = priv->phydev; + unsigned int status_changed = 0; + u32 reg; + + BUG_ON(!phydev); + + if (priv->old_link != phydev->link) { + status_changed = 1; + priv->old_link = phydev->link; + } + + if (phydev->link && (priv->old_duplex != phydev->duplex)) { + reg = nuport_mac_readl(CTRL_REG); + if (phydev->duplex == DUPLEX_FULL) + reg |= DUPLEX_FULL; + else + reg &= ~DUPLEX_FULL; + nuport_mac_writel(reg, CTRL_REG); + + status_changed = 1; + priv->old_duplex = phydev->duplex; + } + + if (!status_changed) + return; + + pr_info("%s: link %s", dev->name, phydev->link ? + "UP" : "DOWN"); + if (phydev->link) { + pr_cont(" - %d/%s", phydev->speed, + phydev->duplex == DUPLEX_FULL ? "full" : "half"); + } + pr_cont("\n"); +} + +static irqreturn_t nuport_mac_link_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct nuport_mac_priv *priv = netdev_priv(dev); + u32 reg; + u8 phy_addr; + unsigned long flags; + irqreturn_t ret = IRQ_HANDLED; + + spin_lock_irqsave(&priv->lock, flags); + reg = nuport_mac_readl(LINK_INT_CSR); + phy_addr = (reg >> LINK_PHY_ADDR_SHIFT) & (PHY_MAX_ADDR - 1); + + if (phy_addr != priv->phydev->addr) { + netdev_err(dev, "spurious PHY irq (phy: %d)\n", phy_addr); + ret = IRQ_NONE; + goto out; + } + + priv->phydev->link = (reg & LINK_UP); + nuport_mac_adjust_link(dev); + +out: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static irqreturn_t nuport_mac_tx_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct nuport_mac_priv *priv = netdev_priv(dev); + struct sk_buff *skb; + unsigned long flags; + int ret; + u32 reg; + + spin_lock_irqsave(&priv->lock, flags); + /* clear status word available if ready */ + reg = nuport_mac_readl(TX_START_DMA); + if (reg & TX_DMA_STATUS_AVAIL) { + nuport_mac_writel(reg, TX_START_DMA); + reg = nuport_mac_readl(TX_DMA_STATUS); + + if (reg & 1) + dev->stats.tx_errors++; + } else + netdev_dbg(dev, "no status word: %08x\n", reg); + + skb = priv->tx_skb[priv->dma_tx]; + priv->tx_skb[priv->dma_tx] = NULL; + priv->valid_txskb[priv->dma_tx] = 0; + dma_unmap_single(&priv->pdev->dev, priv->rx_addr, skb->len, + DMA_TO_DEVICE); + dev_kfree_skb_irq(skb); + + priv->dma_tx++; + if (priv->dma_tx >= TX_RING_SIZE) + priv->dma_tx = 0; + + if (!priv->valid_txskb[priv->dma_tx]) + priv->first_pkt = 1; + else { + ret = nuport_mac_start_tx_dma(priv, priv->tx_skb[priv->dma_tx]); + if (ret) + netdev_err(dev, "failed to restart TX dma\n"); + } + + if (priv->tx_full) { + netdev_dbg(dev, "restarting transmit queue\n"); + netif_wake_queue(dev); + priv->tx_full = 0; + } + + spin_unlock_irqrestore(&priv->lock, flags); + + return IRQ_HANDLED; +} + +static unsigned int nuport_mac_has_work(struct nuport_mac_priv *priv) +{ + unsigned int i; + + for (i = 0; i < RX_RING_SIZE; i++) + if (priv->rx_skb[i]) + return 1; + + return 0; +} + +static irqreturn_t nuport_mac_rx_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct nuport_mac_priv *priv = netdev_priv(dev); + unsigned long flags; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + if (!priv->rx_full) { + priv->pkt_len[priv->dma_rx] = nuport_mac_readl(RX_ACT_BYTES) - 4; + priv->irq_rxskb[priv->dma_rx] = 0; + priv->dma_rx++; + + if (priv->dma_rx >= RX_RING_SIZE) + priv->dma_rx = 0; + } else + priv->rx_full = 0; + + if (priv->irq_rxskb[priv->dma_rx] == 1) { + ret = nuport_mac_start_rx_dma(priv, priv->rx_skb[priv->dma_rx]); + if (ret) + netdev_err(dev, "failed to start rx dma\n"); + } else { + priv->rx_full = 1; + netdev_dbg(dev, "RX ring full\n"); + } + + if (likely(nuport_mac_has_work(priv))) { + /* find a way to disable DMA rx irq */ + nuport_mac_disable_rx_dma(priv); + napi_schedule(&priv->napi); + } + spin_unlock_irqrestore(&priv->lock, flags); + + return IRQ_HANDLED; +} + +/* Process received packets in tasklet */ +static int nuport_mac_rx(struct net_device *dev, int limit) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + struct sk_buff *skb; + int len, status; + int count = 0; + + while (count < limit && !priv->irq_rxskb[priv->cur_rx]) { + skb = priv->rx_skb[priv->cur_rx]; + len = priv->pkt_len[priv->cur_rx]; + + /* Remove 2 bytes added by RX buffer shifting */ + len = len - priv->buffer_shifting_len; + skb->data = skb->data + priv->buffer_shifting_len; + + /* Get packet status */ + status = get_unaligned((u32 *) (skb->data + len)); + + dma_unmap_single(&priv->pdev->dev, priv->rx_addr, skb->len, + DMA_FROM_DEVICE); + + /* packet filter failed */ + if (!(status & (1 << 30))) { + dev_kfree_skb_irq(skb); + goto exit; + } + + /* missed frame */ + if (status & (1 << 31)) { + dev->stats.rx_missed_errors++; + dev_kfree_skb_irq(skb); + goto exit; + } + + /* Not ethernet type */ + if ((!(status & (1 << 18))) || (status & ERROR_FILTER_MASK)) + dev->stats.rx_errors++; + + if (len > MAX_ETH_FRAME_SIZE) { + dev_kfree_skb_irq(skb); + goto exit; + } else + skb_put(skb, len); + + skb->protocol = eth_type_trans(skb, dev); + dev->stats.rx_packets++; + + if (status & (1 << 29)) + skb->pkt_type = PACKET_OTHERHOST; + if (status & (1 << 27)) + skb->pkt_type = PACKET_MULTICAST; + if (status & (1 << 28)) + skb->pkt_type = PACKET_BROADCAST; + + skb->ip_summed = CHECKSUM_UNNECESSARY; + + /* Pass the received packet to network layer */ + status = netif_receive_skb(skb); + if (status != NET_RX_DROP) + dev->stats.rx_bytes += len - 4; /* Without CRC */ + else + dev->stats.rx_dropped++; + + dev->last_rx = jiffies; + +exit: + skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE); + if (!skb) + goto out; + + skb_reserve(skb, RX_SKB_HEADROOM); + priv->rx_skb[priv->cur_rx] = skb; + priv->irq_rxskb[priv->cur_rx] = 1; + priv->cur_rx++; + + if (priv->cur_rx >= RX_RING_SIZE) + priv->cur_rx = 0; + count++; + } +out: + return count; +} + +static int nuport_mac_poll(struct napi_struct *napi, int budget) +{ + struct nuport_mac_priv *priv = + container_of(napi, struct nuport_mac_priv, napi); + struct net_device *dev = priv->dev; + int work_done; + + work_done = nuport_mac_rx(dev, budget); + + if (work_done < budget) { + napi_complete(napi); + nuport_mac_enable_rx_dma(priv); + } + + return work_done; +} + +static void nuport_mac_init_tx_ring(struct nuport_mac_priv *priv) +{ + int i; + + priv->cur_tx = priv->dma_tx = priv->tx_full = 0; + for (i = 0; i < TX_RING_SIZE; i++) { + priv->tx_skb[i] = NULL; + priv->valid_txskb[i] = 0; + } + priv->first_pkt = 1; +} + +static int nuport_mac_init_rx_ring(struct net_device *dev) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + struct sk_buff *skb; + int i; + + priv->cur_rx = priv->dma_rx = priv->rx_full = 0; + + for (i = 0; i < RX_RING_SIZE; i++) { + skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE); + if (!skb) + return -ENOMEM; + skb_reserve(skb, RX_SKB_HEADROOM); + priv->rx_skb[i] = skb; + priv->irq_rxskb[i] = 1; + } + + return 0; +} + +static void nuport_mac_free_rx_ring(struct nuport_mac_priv *priv) +{ + int i; + + for (i = 0; i < RX_RING_SIZE; i++) { + if (!priv->rx_skb[i]) + continue; + + dev_kfree_skb(priv->rx_skb[i]); + priv->rx_skb[i] = NULL; + } + + if (priv->rx_addr) + dma_unmap_single(&priv->pdev->dev, priv->rx_addr, RX_ALLOC_SIZE, + DMA_TO_DEVICE); +} + +static void nuport_mac_read_mac_address(struct net_device *dev) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + int i; + + for (i = 0; i < 4; i++) + dev->dev_addr[i] = nuport_mac_readb(MAC_ADDR_LOW_REG + i); + dev->dev_addr[4] = nuport_mac_readb(MAC_ADDR_HIGH_REG); + dev->dev_addr[5] = nuport_mac_readb(MAC_ADDR_HIGH_REG + 1); + + if (!is_valid_ether_addr(dev->dev_addr)) { + dev_info(&priv->pdev->dev, "using random address\n"); + random_ether_addr(dev->dev_addr); + } +} + +static int nuport_mac_change_mac_address(struct net_device *dev, void *mac_addr) +{ + struct sockaddr *addr = mac_addr; + struct nuport_mac_priv *priv = netdev_priv(dev); + unsigned long *temp = (unsigned long *)dev->dev_addr; + u32 high, low; + + if (netif_running(dev)) + return -EBUSY; + + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); + + spin_lock_irq(&priv->lock); + + nuport_mac_writel(*temp, MAC_ADDR_LOW_REG); + temp = (unsigned long *)(dev->dev_addr + 4); + nuport_mac_writel(*temp, MAC_ADDR_HIGH_REG); + + low = nuport_mac_readl(MAC_ADDR_LOW_REG); + high = nuport_mac_readl(MAC_ADDR_HIGH_REG); + + spin_unlock_irq(&priv->lock); + + return 0; +} + +static int nuport_mac_open(struct net_device *dev) +{ + int ret; + struct nuport_mac_priv *priv = netdev_priv(dev); + unsigned long flags; + u32 reg = 0; + + ret = clk_enable(priv->emac_clk); + if (ret) { + netdev_err(dev, "failed to enable EMAC clock\n"); + return ret; + } + + /* Set MAC into full duplex mode by default */ + reg |= RX_ENABLE | TX_ENABLE; + reg |= DEFER_CHECK | STRIP_PAD | DRTRY_DISABLE; + reg |= FULL_DUPLEX | HBD_DISABLE; + nuport_mac_writel(reg, CTRL_REG); + + /* set mac address in hardware in case it was not already */ + nuport_mac_change_mac_address(dev, dev->dev_addr); + + ret = request_irq(priv->link_irq, &nuport_mac_link_interrupt, + 0, dev->name, dev); + if (ret) { + netdev_err(dev, "unable to request link interrupt\n"); + goto out_emac_clk; + } + + ret = request_irq(priv->tx_irq, &nuport_mac_tx_interrupt, + 0, dev->name, dev); + if (ret) { + netdev_err(dev, "unable to request rx interrupt\n"); + goto out_link_irq; + } + + /* Enable link interrupt monitoring for our PHY address */ + reg = LINK_INT_EN | (priv->phydev->addr << LINK_PHY_ADDR_SHIFT); + /* MII_BMSR register to be watched */ + reg |= (1 << LINK_PHY_REG_SHIFT); + /* BMSR_STATUS to be watched in particular */ + reg |= (2 << LINK_BIT_UP_SHIFT); + + spin_lock_irqsave(&priv->lock, flags); + nuport_mac_writel(reg, LINK_INT_CSR); + nuport_mac_writel(LINK_POLL_MASK, LINK_INT_POLL_TIME); + spin_unlock_irqrestore(&priv->lock, flags); + + phy_start(priv->phydev); + + ret = request_irq(priv->rx_irq, &nuport_mac_rx_interrupt, + 0, dev->name, dev); + if (ret) { + netdev_err(dev, "unable to request tx interrupt\n"); + goto out_tx_irq; + } + + netif_start_queue(dev); + + nuport_mac_init_tx_ring(priv); + + ret = nuport_mac_init_rx_ring(dev); + if (ret) { + netdev_err(dev, "rx ring init failed\n"); + goto out_rx_skb; + } + + nuport_mac_reset_tx_dma(priv); + nuport_mac_reset_rx_dma(priv); + + /* Start RX DMA */ + spin_lock_irqsave(&priv->lock, flags); + ret = nuport_mac_start_rx_dma(priv, priv->rx_skb[0]); + spin_unlock_irqrestore(&priv->lock, flags); + + napi_enable(&priv->napi); + + return ret; + +out_rx_skb: + nuport_mac_free_rx_ring(priv); + free_irq(priv->rx_irq, dev); +out_tx_irq: + free_irq(priv->tx_irq, dev); +out_link_irq: + free_irq(priv->link_irq, dev); +out_emac_clk: + clk_disable(priv->emac_clk); + return ret; +} + +static int nuport_mac_close(struct net_device *dev) +{ + u32 reg; + struct nuport_mac_priv *priv = netdev_priv(dev); + + spin_lock_irq(&priv->lock); + reg = nuport_mac_readl(CTRL_REG); + reg &= ~(RX_ENABLE | TX_ENABLE); + nuport_mac_writel(reg, CTRL_REG); + + napi_disable(&priv->napi); + netif_stop_queue(dev); + + free_irq(priv->link_irq, dev); + /* disable PHY polling */ + nuport_mac_writel(0, LINK_INT_CSR); + nuport_mac_writel(0, LINK_INT_POLL_TIME); + phy_stop(priv->phydev); + + free_irq(priv->tx_irq, dev); + free_irq(priv->rx_irq, dev); + spin_unlock_irq(&priv->lock); + + nuport_mac_free_rx_ring(priv); + + clk_disable(priv->emac_clk); + + return 0; +} + +static void nuport_mac_tx_timeout(struct net_device *dev) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + unsigned int i; + + netdev_warn(dev, "transmit timeout, attempting recovery\n"); + + netdev_info(dev, "TX DMA regs\n"); + for (i = 0; i < DMA_CHAN_WIDTH; i += 4) + netdev_info(dev, "[%02x]: 0x%08x\n", i, nuport_mac_readl(TX_DMA_BASE + i)); + netdev_info(dev, "RX DMA regs\n"); + for (i = 0; i < DMA_CHAN_WIDTH; i += 4) + netdev_info(dev, "[%02x]: 0x%08x\n", i, nuport_mac_readl(RX_DMA_BASE + i)); + + nuport_mac_init_tx_ring(priv); + nuport_mac_reset_tx_dma(priv); + + netif_wake_queue(dev); +} + +static int nuport_mac_mii_probe(struct net_device *dev) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; + int ret; + + ret = clk_enable(priv->ephy_clk); + if (ret) { + netdev_err(dev, "unable to enable ePHY clk\n"); + return ret; + } + + phydev = phy_find_first(priv->mii_bus); + if (!phydev) { + netdev_err(dev, "no PHYs found\n"); + ret = -ENODEV; + goto out; + } + + phydev = of_phy_connect(dev, priv->phy_node, + nuport_mac_adjust_link, 0, + priv->phy_interface); + if (IS_ERR(phydev)) { + netdev_err(dev, "could not attach PHY\n"); + ret = PTR_ERR(phydev); + goto out; + } + + phydev->supported &= PHY_BASIC_FEATURES; + phydev->advertising = phydev->supported; + priv->phydev = phydev; + priv->old_link = 1; + priv->old_duplex = DUPLEX_FULL; + + dev_info(&priv->pdev->dev, "attached PHY driver [%s] " + "(mii_bus:phy_addr=%d)\n", + phydev->drv->name, phydev->addr); + + return 0; + +out: + /* disable the Ethernet PHY clock for the moment */ + clk_disable(priv->ephy_clk); + + return ret; +} + +static void nuport_mac_ethtool_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + strncpy(info->driver, "nuport-mac", sizeof(info->driver)); + strncpy(info->version, "0.1", sizeof(info->version)); + strncpy(info->fw_version, "N/A", sizeof(info->fw_version)); + strncpy(info->bus_info, "internal", sizeof(info->bus_info)); + info->n_stats = 0; + info->testinfo_len = 0; + info->regdump_len = 0; + info->eedump_len = 0; +} + +static int nuport_mac_ethtool_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + + if (priv->phydev) + return phy_ethtool_gset(priv->phydev, cmd); + + return -EINVAL; +} + +static int nuport_mac_ethtool_set_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + + if (priv->phydev) + return phy_ethtool_sset(priv->phydev, cmd); + + return -EINVAL; +} + +static void nuport_mac_set_msglevel(struct net_device *dev, u32 msg_level) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + + priv->msg_level = msg_level; +} + +static u32 nuport_mac_get_msglevel(struct net_device *dev) +{ + struct nuport_mac_priv *priv = netdev_priv(dev); + + return priv->msg_level; +} + +static const struct ethtool_ops nuport_mac_ethtool_ops = { + .get_drvinfo = nuport_mac_ethtool_drvinfo, + .get_link = ethtool_op_get_link, + .get_settings = nuport_mac_ethtool_get_settings, + .set_settings = nuport_mac_ethtool_set_settings, + .set_msglevel = nuport_mac_set_msglevel, + .get_msglevel = nuport_mac_get_msglevel, +}; + +static const struct net_device_ops nuport_mac_ops = { + .ndo_open = nuport_mac_open, + .ndo_stop = nuport_mac_close, + .ndo_start_xmit = nuport_mac_start_xmit, + .ndo_change_mtu = eth_change_mtu, + .ndo_validate_addr = eth_validate_addr, + .ndo_set_mac_address = nuport_mac_change_mac_address, + .ndo_tx_timeout = nuport_mac_tx_timeout, +}; + +static int __init nuport_mac_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct nuport_mac_priv *priv = NULL; + struct resource *regs, *dma; + int ret = 0; + int rx_irq, tx_irq, link_irq; + int i; + const unsigned int *intspec; + + dev = alloc_etherdev(sizeof(struct nuport_mac_priv)); + if (!dev) { + dev_err(&pdev->dev, "no memory for net_device\n"); + return -ENOMEM; + } + + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dma = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!regs || !dma) { + dev_err(&pdev->dev, "failed to get regs resources\n"); + ret = -ENODEV; + goto out; + } + + rx_irq = platform_get_irq(pdev, 0); + tx_irq = platform_get_irq(pdev, 1); + link_irq = platform_get_irq(pdev, 2); + if (rx_irq < 0 || tx_irq < 0 || link_irq < 0) { + ret = -ENODEV; + goto out; + } + + platform_set_drvdata(pdev, dev); + SET_NETDEV_DEV(dev, &pdev->dev); + priv = netdev_priv(dev); + priv->pdev = pdev; + priv->dev = dev; + spin_lock_init(&priv->lock); + + intspec = of_get_property(pdev->dev.of_node, + "nuport-mac,buffer-shifting", NULL); + if (!intspec) + priv->buffer_shifting_len = 0; + else + priv->buffer_shifting_len = 2; + + priv->mac_base = devm_ioremap_resource(&pdev->dev, regs); + if (!priv->mac_base) { + dev_err(&pdev->dev, "failed to remap regs\n"); + ret = -ENOMEM; + goto out_platform; + } + + priv->dma_base = devm_ioremap_resource(&pdev->dev, dma); + if (!priv->dma_base) { + dev_err(&pdev->dev, "failed to remap dma-regs\n"); + ret = -ENOMEM; + goto out_platform; + } + + priv->emac_clk = clk_get(&pdev->dev, "emac"); + if (IS_ERR_OR_NULL(priv->emac_clk)) { + dev_err(&pdev->dev, "failed to get emac clk\n"); + ret = PTR_ERR(priv->emac_clk); + goto out_platform; + } + + priv->ephy_clk = clk_get(&pdev->dev, "ephy"); + if (IS_ERR_OR_NULL(priv->ephy_clk)) { + dev_err(&pdev->dev, "failed to get ephy clk\n"); + ret = PTR_ERR(priv->ephy_clk); + goto out_platform; + } + + priv->link_irq = link_irq; + priv->rx_irq = rx_irq; + priv->tx_irq = tx_irq; + priv->msg_level = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK; + dev->netdev_ops = &nuport_mac_ops; + dev->ethtool_ops = &nuport_mac_ethtool_ops; + dev->watchdog_timeo = HZ; + dev->flags = IFF_BROADCAST; /* Supports Broadcast */ + dev->tx_queue_len = TX_RING_SIZE / 2; + + netif_napi_add(dev, &priv->napi, nuport_mac_poll, 64); + + priv->phy_node = of_parse_phandle(pdev->dev.of_node, "phy", 0); + if (!priv->phy_node) { + dev_err(&pdev->dev, "no associated PHY\n"); + ret = -ENODEV; + goto out; + } + + priv->phy_interface = of_get_phy_mode(pdev->dev.of_node); + if (priv->phy_interface < 0) { + dev_err(&pdev->dev, "invalid PHY mode\n"); + ret = -EINVAL; + goto out; + } + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { + dev_err(&pdev->dev, "mii bus allocation failed\n"); + goto out; + } + + priv->mii_bus->priv = dev; + priv->mii_bus->read = nuport_mac_mii_read; + priv->mii_bus->write = nuport_mac_mii_write; + priv->mii_bus->reset = nuport_mac_mii_reset; + priv->mii_bus->name = "nuport-mac-mii"; + priv->mii_bus->phy_mask = (1 << 0); + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", pdev->name); + priv->mii_bus->irq = kzalloc(PHY_MAX_ADDR * sizeof(int), GFP_KERNEL); + if (!priv->mii_bus->irq) { + dev_err(&pdev->dev, "failed to allocate mii_bus irqs\n"); + ret = -ENOMEM; + goto out_mdio; + } + + /* We support PHY interrupts routed back to the MAC */ + for (i = 0; i < PHY_MAX_ADDR; i++) + priv->mii_bus->irq[i] = PHY_IGNORE_INTERRUPT; + + ret = of_mdiobus_register(priv->mii_bus, pdev->dev.of_node); + if (ret) { + dev_err(&pdev->dev, "failed to register mii_bus\n"); + goto out_mdio_irq; + } + + ret = nuport_mac_mii_probe(dev); + if (ret) { + dev_err(&pdev->dev, "failed to probe MII bus\n"); + goto out_mdio_unregister; + } + + ret = register_netdev(dev); + if (ret) { + dev_err(&pdev->dev, "failed to register net_device\n"); + goto out_mdio_probe; + } + + /* read existing mac address */ + nuport_mac_read_mac_address(dev); + + dev_info(&pdev->dev, "registered (MAC: %pM)\n", dev->dev_addr); + + return ret; + +out_mdio_probe: + phy_disconnect(priv->phydev); +out_mdio_unregister: + mdiobus_unregister(priv->mii_bus); +out_mdio_irq: + kfree(priv->mii_bus->irq); +out_mdio: + mdiobus_free(priv->mii_bus); +out_platform: + platform_set_drvdata(pdev, NULL); +out: + clk_put(priv->ephy_clk); + clk_put(priv->emac_clk); + free_netdev(dev); + platform_set_drvdata(pdev, NULL); + return ret; +} + +static int nuport_mac_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct nuport_mac_priv *priv = netdev_priv(dev); + + unregister_netdev(dev); + phy_disconnect(priv->phydev); + mdiobus_unregister(priv->mii_bus); + kfree(priv->mii_bus->irq); + mdiobus_free(priv->mii_bus); + clk_put(priv->ephy_clk); + clk_put(priv->emac_clk); + free_netdev(dev); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct of_device_id nuport_eth_ids[] __initdata = { + {.compatible = "moschip,nuport-mac",}, + { /* sentinel */ }, +}; + +static struct platform_driver nuport_eth_driver = { + .driver = { + .name = "nuport-mac", + .owner = THIS_MODULE, + .of_match_table = nuport_eth_ids, + }, + .probe = nuport_mac_probe, + .remove = nuport_mac_remove, +}; + +module_platform_driver(nuport_eth_driver); + +MODULE_AUTHOR("Moschip Semiconductors Ltd."); +MODULE_DESCRIPTION("Moschip MCS8140 Ethernet MAC driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/mcs814x/files-3.18/drivers/net/phy/mcs814x.c b/target/linux/mcs814x/files-3.18/drivers/net/phy/mcs814x.c new file mode 100644 index 0000000..e92176e --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/net/phy/mcs814x.c @@ -0,0 +1,64 @@ +/* + * Driver for Moschip MCS814x internal PHY + * + * Copyright (c) 2012 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +MODULE_DESCRIPTION("Moschip MCS814x PHY driver"); +MODULE_AUTHOR("Florian Fainelli "); +MODULE_LICENSE("GPL"); + +/* Nothing special about this PHY but its OUI (O) */ +static struct phy_driver mcs8140_driver = { + .phy_id = 0, + .name = "Moschip MCS8140", + .phy_id_mask = 0x02, + .features = PHY_BASIC_FEATURES, + .config_aneg = &genphy_config_aneg, + .read_status = &genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + .driver = { .owner = THIS_MODULE,}, +}; + +static int __init mcs814x_phy_init(void) +{ + return phy_driver_register(&mcs8140_driver); +} + +static void __exit mcs814x_phy_exit(void) +{ + phy_driver_unregister(&mcs8140_driver); +} + +module_init(mcs814x_phy_init); +module_exit(mcs814x_phy_exit); + +static struct mdio_device_id __maybe_unused mcs814x_phy_tbl[] = { + { 0x0, 0x0ffffff0 }, + { } +}; + +MODULE_DEVICE_TABLE(mdio, mcs814x_phy_tbl); diff --git a/target/linux/mcs814x/files-3.18/drivers/usb/host/ehci-mcs814x.c b/target/linux/mcs814x/files-3.18/drivers/usb/host/ehci-mcs814x.c new file mode 100644 index 0000000..23928f2 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/usb/host/ehci-mcs814x.c @@ -0,0 +1,163 @@ +/* + * MCS814X EHCI Host Controller Driver + * + * Based on "ehci-fsl.c" by Randy Vinson + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include +#include + +#define MCS814X_EHCI_CAPS_OFFSET 0x68 + +static int mcs814x_ehci_init(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval = 0; + + ehci->caps = hcd->regs + MCS814X_EHCI_CAPS_OFFSET; + ehci->regs = hcd->regs + + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + ehci_reset(ehci); + + retval = ehci_init(hcd); + if (retval) { + pr_err("ehci_init failed\n"); + return retval; + } + + return retval; +} + +static const struct hc_driver mcs814x_ehci_hc_driver = { + .description = hcd_name, + .product_desc = "MCS814X EHCI Host Controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + .reset = mcs814x_ehci_init, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + .get_frame_number = ehci_get_frame, + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, +#if defined(CONFIG_PM) + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, +#endif + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, + + .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, +}; + +static int mcs814x_ehci_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + const struct hc_driver *driver = &mcs814x_ehci_hc_driver; + struct resource *res; + int irq; + int retval; + + if (usb_disabled()) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no IRQ. Check %s setup!\n", + dev_name(&pdev->dev)); + return -ENODEV; + } + irq = res->start; + + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + + hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); + if (!hcd) { + retval = -ENOMEM; + goto fail_create_hcd; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, + "Found HC with no register addr. Check %s setup!\n", + dev_name(&pdev->dev)); + retval = -ENODEV; + goto fail_request_resource; + } + hcd->rsrc_start = res->start; + hcd->rsrc_len = resource_size(res); + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, + driver->description)) { + dev_dbg(&pdev->dev, "controller already in use\n"); + retval = -EBUSY; + goto fail_request_resource; + } + + hcd->regs = ioremap_nocache(hcd->rsrc_start, hcd->rsrc_len); + if (hcd->regs == NULL) { + dev_dbg(&pdev->dev, "error mapping memory\n"); + retval = -EFAULT; + goto fail_ioremap; + } + + retval = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (retval) + goto fail_add_hcd; + + dev_info(&pdev->dev, "added MCS814X EHCI driver\n"); + + return retval; + +fail_add_hcd: + iounmap(hcd->regs); +fail_ioremap: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +fail_request_resource: + usb_put_hcd(hcd); +fail_create_hcd: + dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); + return retval; +} + +static int mcs814x_ehci_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + + return 0; +} + +MODULE_ALIAS("platform:mcs814x-ehci"); + +static const struct of_device_id mcs814x_ehci_id[] = { + { .compatible = "moschip,mcs814x-ehci" }, + { .compatible = "usb-ehci" }, + { /* sentinel */ }, +}; + +static struct platform_driver mcs814x_ehci_driver = { + .probe = mcs814x_ehci_probe, + .remove = mcs814x_ehci_remove, + .driver = { + .name = "mcs814x-ehci", + .of_match_table = mcs814x_ehci_id, + }, +}; diff --git a/target/linux/mcs814x/files-3.18/drivers/usb/host/ohci-mcs814x.c b/target/linux/mcs814x/files-3.18/drivers/usb/host/ohci-mcs814x.c new file mode 100644 index 0000000..161176b --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/usb/host/ohci-mcs814x.c @@ -0,0 +1,202 @@ +/* + * OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * (C) Copyright 2002 Hewlett-Packard Company + * + * Bus Glue for Moschip MCS814x. + * + * Written by Christopher Hoover + * Based on fragments of previous driver by Russell King et al. + * + * Modified for LH7A404 from ohci-sa1111.c + * by Durgesh Pattamatta + * + * Modified for pxa27x from ohci-lh7a404.c + * by Nick Bane 26-8-2004 + * + * Modified for mcs814x from ohci-mcs814x.c + * by Lennert Buytenhek 28-2-2006 + * Based on an earlier driver by Ray Lehtiniemi + * + * This file is licenced under the GPL. + */ + +#include +#include +#include +#include + +static int usb_hcd_mcs814x_probe(const struct hc_driver *driver, + struct platform_device *pdev) +{ + int retval; + struct usb_hcd *hcd; + + if (pdev->resource[1].flags != IORESOURCE_IRQ) { + pr_debug("resource[1] is not IORESOURCE_IRQ"); + return -ENOMEM; + } + + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + + hcd = usb_create_hcd(driver, &pdev->dev, "mcs814x"); + if (hcd == NULL) + return -ENOMEM; + + hcd->rsrc_start = pdev->resource[0].start; + hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + usb_put_hcd(hcd); + retval = -EBUSY; + goto err1; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (hcd->regs == NULL) { + pr_debug("ioremap failed"); + retval = -ENOMEM; + goto err2; + } + + ohci_hcd_init(hcd_to_ohci(hcd)); + + retval = usb_add_hcd(hcd, pdev->resource[1].start, IRQF_DISABLED); + if (retval == 0) + return retval; + + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + + return retval; +} + +static void usb_hcd_mcs814x_remove(struct usb_hcd *hcd, + struct platform_device *pdev) +{ + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); +} + +static int ohci_mcs814x_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int ret; + + ret = ohci_init(ohci); + if (ret < 0) + return ret; + + ret = ohci_run(ohci); + if (ret < 0) { + ohci_err(ohci, "can't start %s", hcd->self.bus_name); + ohci_stop(hcd); + return ret; + } + + return 0; +} + +static struct hc_driver ohci_mcs814x_hc_driver = { + .description = hcd_name, + .product_desc = "MCS814X OHCI", + .hcd_priv_size = sizeof(struct ohci_hcd), + .irq = ohci_irq, + .flags = HCD_USB11 | HCD_MEMORY, + .start = ohci_mcs814x_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + .get_frame_number = ohci_get_frame, + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, +#ifdef CONFIG_PM + .bus_suspend = ohci_bus_suspend, + .bus_resume = ohci_bus_resume, +#endif + .start_port_reset = ohci_start_port_reset, +}; + +extern int usb_disabled(void); + +static int ohci_hcd_mcs814x_drv_probe(struct platform_device *pdev) +{ + int ret; + + ret = -ENODEV; + if (!usb_disabled()) + ret = usb_hcd_mcs814x_probe(&ohci_mcs814x_hc_driver, pdev); + + return ret; +} + +static int ohci_hcd_mcs814x_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_hcd_mcs814x_remove(hcd, pdev); + + return 0; +} + +#ifdef CONFIG_PM +static int ohci_hcd_mcs814x_drv_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + + if (time_before(jiffies, ohci->next_statechange)) + msleep(5); + ohci->next_statechange = jiffies; + + hcd->state = HC_STATE_SUSPENDED; + + return 0; +} + +static int ohci_hcd_mcs814x_drv_resume(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int status; + + if (time_before(jiffies, ohci->next_statechange)) + msleep(5); + ohci->next_statechange = jiffies; + + ohci_finish_controller_resume(hcd); + return 0; +} +#endif + +static const struct of_device_id mcs814x_ohci_id[] = { + { .compatible = "moschip,mcs814x-ohci" }, + { .compatible = "ohci-le" }, + { /* sentinel */ }, +}; + +static struct platform_driver ohci_hcd_mcs814x_driver = { + .probe = ohci_hcd_mcs814x_drv_probe, + .remove = ohci_hcd_mcs814x_drv_remove, + .shutdown = usb_hcd_platform_shutdown, +#ifdef CONFIG_PM + .suspend = ohci_hcd_mcs814x_drv_suspend, + .resume = ohci_hcd_mcs814x_drv_resume, +#endif + .driver = { + .name = "mcs814x-ohci", + .owner = THIS_MODULE, + .of_match_table = mcs814x_ohci_id, + }, +}; + +MODULE_ALIAS("platform:mcs814x-ohci"); diff --git a/target/linux/mcs814x/files-3.18/drivers/watchdog/mcs814x_wdt.c b/target/linux/mcs814x/files-3.18/drivers/watchdog/mcs814x_wdt.c new file mode 100644 index 0000000..7bcded5 --- /dev/null +++ b/target/linux/mcs814x/files-3.18/drivers/watchdog/mcs814x_wdt.c @@ -0,0 +1,207 @@ +/* + * Moschip MCS814x Watchdog driver + * + * Copyright (C) 2012, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WDT_COUNT 0x00 +#define WDT_CTRL 0x04 +#define WDT_CTRL_EN 0x1 + +/* watchdog frequency */ +#define WDT_MAX_VALUE (0xffffffff) + +struct mcs814x_wdt { + void __iomem *regs; + spinlock_t lock; + struct watchdog_device wdt_dev; + struct clk *clk; +}; + +static int mcs814x_wdt_start(struct watchdog_device *dev) +{ + struct mcs814x_wdt *wdt = watchdog_get_drvdata(dev); + u32 reg; + + spin_lock(&wdt->lock); + reg = readl_relaxed(wdt->regs + WDT_CTRL); + reg |= WDT_CTRL_EN; + writel_relaxed(reg, wdt->regs + WDT_CTRL); + spin_unlock(&wdt->lock); + + return 0; +} + +static int mcs814x_wdt_stop(struct watchdog_device *dev) +{ + struct mcs814x_wdt *wdt = watchdog_get_drvdata(dev); + u32 reg; + + spin_lock(&wdt->lock); + reg = readl_relaxed(wdt->regs + WDT_CTRL); + reg &= ~WDT_CTRL_EN; + writel_relaxed(reg, wdt->regs + WDT_CTRL); + spin_unlock(&wdt->lock); + + return 0; +} + +static int mcs814x_wdt_set_timeout(struct watchdog_device *dev, + unsigned int new_timeout) +{ + struct mcs814x_wdt *wdt = watchdog_get_drvdata(dev); + + spin_lock(&wdt->lock); + /* watchdog counts upward and rollover (0xfffffff -> 0) + * triggers the reboot + */ + writel_relaxed(WDT_MAX_VALUE - (new_timeout * clk_get_rate(wdt->clk)), + wdt->regs + WDT_COUNT); + spin_unlock(&wdt->lock); + + return 0; +} + +static int mcs814x_wdt_ping(struct watchdog_device *dev) +{ + /* restart the watchdog */ + mcs814x_wdt_stop(dev); + mcs814x_wdt_set_timeout(dev, dev->timeout); + mcs814x_wdt_start(dev); + + return 0; +} + +static const struct watchdog_info mcs814x_wdt_ident = { + .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, + .identity = "MCS814x Watchdog", +}; + +static struct watchdog_ops mcs814x_wdt_ops = { + .owner = THIS_MODULE, + .start = mcs814x_wdt_start, + .stop = mcs814x_wdt_stop, + .set_timeout = mcs814x_wdt_set_timeout, + .ping = mcs814x_wdt_ping, +}; + +static int mcs814x_wdt_probe(struct platform_device *pdev) +{ + struct resource *res; + struct mcs814x_wdt *wdt; + int ret; + struct clk *clk; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + clk = clk_get(NULL, "wdt"); + if (IS_ERR_OR_NULL(clk)) { + dev_err(&pdev->dev, "failed to get watchdog clock\n"); + return PTR_ERR(clk); + } + + wdt = kzalloc(sizeof(*wdt), GFP_KERNEL); + if (!wdt) { + ret = -ENOMEM; + goto out_clk; + } + + spin_lock_init(&wdt->lock); + wdt->clk = clk; + wdt->wdt_dev.info = &mcs814x_wdt_ident; + wdt->wdt_dev.ops = &mcs814x_wdt_ops; + wdt->wdt_dev.min_timeout = 1; + /* approximately 10995 secs */ + wdt->wdt_dev.max_timeout = (WDT_MAX_VALUE / clk_get_rate(clk)); + + platform_set_drvdata(pdev, wdt); + + /* only ioremap registers, because the register is shared */ + wdt->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!wdt->regs) { + ret = -ENOMEM; + goto out; + } + + watchdog_set_drvdata(&wdt->wdt_dev, wdt); + + ret = watchdog_register_device(&wdt->wdt_dev); + if (ret) { + dev_err(&pdev->dev, "cannot register watchdog: %d\n", ret); + goto out; + } + + dev_info(&pdev->dev, "registered\n"); + return 0; + +out: + platform_set_drvdata(pdev, NULL); + kfree(wdt); +out_clk: + clk_put(clk); + return ret; +} + +static int mcs814x_wdt_remove(struct platform_device *pdev) +{ + struct mcs814x_wdt *wdt = platform_get_drvdata(pdev); + + clk_put(wdt->clk); + watchdog_unregister_device(&wdt->wdt_dev); + watchdog_set_drvdata(&wdt->wdt_dev, NULL); + kfree(wdt); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static const struct of_device_id mcs814x_wdt_ids[] = { + { .compatible = "moschip,mcs814x-wdt", }, + { /* sentinel */ }, +}; + +static struct platform_driver mcs814x_wdt_driver = { + .driver = { + .name = "mcs814x-wdt", + .owner = THIS_MODULE, + .of_match_table = mcs814x_wdt_ids, + }, + .probe = mcs814x_wdt_probe, + .remove = mcs814x_wdt_remove, +}; + +module_platform_driver(mcs814x_wdt_driver); + +MODULE_AUTHOR("Florian Fainelli "); +MODULE_DESCRIPTION("Moschip MCS814x Watchdog driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); +MODULE_ALIAS("platform:mcs814x-wdt"); diff --git a/target/linux/mcs814x/image/Makefile b/target/linux/mcs814x/image/Makefile new file mode 100644 index 0000000..3afd660 --- /dev/null +++ b/target/linux/mcs814x/image/Makefile @@ -0,0 +1,60 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +JFFS2_BLOCKSIZE = 128k + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +TARGET_DTBS := rbt-832 dlan-usb-extender + +DTBS_DIR:=dts/ + +LOADADDR:=0x00008000 + +UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage + +define Image/Build/MkuImage + mkimage -A arm -O linux -T kernel -a $(LOADADDR) -C none -e $(LOADADDR) \ + -n 'ARM OpenWrt Linux-$(LINUX_VERSION)' -d $(1) $(2); +endef + +define Image/Build/DTB + cp $(KDIR)/zImage$(2) $(KDIR)/zImage-$(1); + cat $(LINUX_DIR)/arch/$(ARCH)/boot/$(DTBS_DIR)$(1).dtb >> $(KDIR)/zImage$(2)-$(1); + $(call Image/Build/MkuImage,$(KDIR)/zImage$(2)-$(1),$(KDIR)/uImage$(2)-$(1)) + cp $(KDIR)/uImage$(2)-$(1) $(UIMAGE)$(2)-$(1); +endef + +define Image/Build/Profile/dLAN_USB_Extender + dd if=$(KDIR)/uImage-dlan-usb-extender bs=64k conv=sync of=$(KDIR)/$(IMG_PREFIX)-dlan-usb-extender-upgrade-$(1).bin + cat $(KDIR)/root.$(1) >> $(KDIR)/$(IMG_PREFIX)-dlan-usb-extender-upgrade-$(1).bin + cp $(KDIR)/$(IMG_PREFIX)-dlan-usb-extender-upgrade-$(1).bin $(BIN_DIR)/ +endef + +define Image/BuildKernel + $(foreach dtb,$(TARGET_DTBS),$(call Image/Build/DTB,$(dtb))) +endef + +define Image/Build/Initramfs + $(foreach dtb,$(TARGET_DTBS),$(call Image/Build/DTB,$(dtb),-initramfs)) +endef + +define Image/Build/squashfs + $(STAGING_DIR_HOST)/bin/padjffs2 $(KDIR)/root.squashfs 128 +endef + +define Image/Build + $(call Image/Build/$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync + $(call Image/Build/Profile/$(PROFILE),$(1)) +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Initramfs) +endif +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/mcs814x/modules.mk b/target/linux/mcs814x/modules.mk new file mode 100644 index 0000000..c29ca86 --- /dev/null +++ b/target/linux/mcs814x/modules.mk @@ -0,0 +1,20 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. + +define KernelPackage/mcs814x-wdt + SUBMENU:=$(OTHER_MENU) + DEPENDS:=@TARGET_mcs814x + TITLE:=MCS814x watchdog driver + KCONFIG:=CONFIG_MCS814X_WATCHDOG + FILES:=$(LINUX_DIR)/drivers/$(WATCHDOG_DIR)/mcs814x_wdt.ko + AUTOLOAD:=$(call AutoLoad,50,mcs814x_wdt) +endef + +define KernelPackage/mcs814x-wdt/description + Kernel module for the Moschip MCS814x watchdog timer. +endef + +$(eval $(call KernelPackage,mcs814x-wdt)) diff --git a/target/linux/mcs814x/patches-3.18/001-platform.patch b/target/linux/mcs814x/patches-3.18/001-platform.patch new file mode 100644 index 0000000..83f1683 --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/001-platform.patch @@ -0,0 +1,64 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -267,7 +267,8 @@ config PHYS_OFFSET + ARCH_INTEGRATOR || \ + ARCH_IOP13XX || \ + ARCH_KS8695 || \ +- (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) ++ (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) || \ ++ ARCH_MCS814X + default 0x10000000 if ARCH_OMAP1 || ARCH_RPC + default 0x20000000 if ARCH_S5PV210 + default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET +@@ -786,6 +787,21 @@ config ARCH_OMAP1 + help + Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) + ++config ARCH_MCS814X ++ bool "Moschip MCS814x" ++ select FIQ ++ select GENERIC_IRQ_CHIP ++ select GENERIC_GPIO ++ select ARCH_REQUIRE_GPIOLIB ++ select CLKDEV_LOOKUP ++ select ARCH_USES_GETTIMEOFFSET ++ select USB_ARCH_HAS_OHCI ++ select USB_ARCH_HAS_EHCI ++ select MULTI_IRQ_HANDLER ++ help ++ Support for Moschip MCS814x SoCs (MCS8140). ++ ++ + endchoice + + menu "Multiple platform selection" +@@ -927,6 +943,8 @@ source "arch/arm/mach-picoxcell/Kconfig" + source "arch/arm/mach-pxa/Kconfig" + source "arch/arm/plat-pxa/Kconfig" + ++source "arch/arm/mach-mcs814x/Kconfig" ++ + source "arch/arm/mach-mmp/Kconfig" + + source "arch/arm/mach-qcom/Kconfig" +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx + machine-$(CONFIG_ARCH_KEYSTONE) += keystone + machine-$(CONFIG_ARCH_KS8695) += ks8695 + machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx ++machine-$(CONFIG_ARCH_MCS814X) += mcs814x + machine-$(CONFIG_ARCH_MESON) += meson + machine-$(CONFIG_ARCH_MMP) += mmp + machine-$(CONFIG_ARCH_MOXART) += moxart +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -163,6 +163,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood- + kirkwood-ts419-6282.dtb + dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb + dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb ++dtb-$(CONFIG_ARCH_MCS814X) += dlan-usb-extender.dtb \ ++ rbt-832.dtb + dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb + dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb + dtb-$(CONFIG_ARCH_MXC) += \ diff --git a/target/linux/mcs814x/patches-3.18/003-ethernet.patch b/target/linux/mcs814x/patches-3.18/003-ethernet.patch new file mode 100644 index 0000000..3ee8cd6 --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/003-ethernet.patch @@ -0,0 +1,16 @@ +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -186,4 +186,6 @@ source "drivers/net/ethernet/wiznet/Kcon + source "drivers/net/ethernet/xilinx/Kconfig" + source "drivers/net/ethernet/xircom/Kconfig" + ++source "drivers/net/ethernet/mcs8140/Kconfig" ++ + endif # ETHERNET +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -84,3 +84,4 @@ obj-$(CONFIG_NET_VENDOR_VIA) += via/ + obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/ + obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/ + obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/ ++obj-$(CONFIG_NUPORT_ETHERNET_DRIVER) += mcs8140/ diff --git a/target/linux/mcs814x/patches-3.18/004-usb.patch b/target/linux/mcs814x/patches-3.18/004-usb.patch new file mode 100644 index 0000000..d69ec21 --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/004-usb.patch @@ -0,0 +1,28 @@ +--- a/drivers/usb/host/ehci-hcd.c ++++ b/drivers/usb/host/ehci-hcd.c +@@ -1298,6 +1298,11 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ehci_hcd_sead3_driver + #endif + ++#ifdef CONFIG_ARCH_MCS814X ++#include "ehci-mcs814x.c" ++#define PLATFORM_DRIVER mcs814x_ehci_driver ++#endif ++ + static int __init ehci_hcd_init(void) + { + int retval = 0; +--- a/drivers/usb/host/ohci-hcd.c ++++ b/drivers/usb/host/ohci-hcd.c +@@ -1259,6 +1259,11 @@ MODULE_LICENSE ("GPL"); + #define PLATFORM_DRIVER ohci_hcd_tilegx_driver + #endif + ++#ifdef CONFIG_ARCH_MCS814X ++#include "ohci-mcs814x.c" ++#define PLATFORM_DRIVER ohci_hcd_mcs814x_driver ++#endif ++ + static int __init ohci_hcd_mod_init(void) + { + int retval = 0; diff --git a/target/linux/mcs814x/patches-3.18/005-mcs814x_rng.patch b/target/linux/mcs814x/patches-3.18/005-mcs814x_rng.patch new file mode 100644 index 0000000..4af3d86 --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/005-mcs814x_rng.patch @@ -0,0 +1,31 @@ +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -229,6 +229,18 @@ config HW_RANDOM_TX4939 + + If unsure, say Y. + ++config HW_RANDOM_MCS814X ++ tristate "Moschip MCS814x Random Number Generator" ++ depends on HW_RANDOM && ARCH_MCS814X ++ ---help--- ++ This driver provides kernel-side support for the Random Number ++ Generator hardware found on Moschip MCS814x processors. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called mcs814x-rng. ++ ++ If unusure, say Y. ++ + config HW_RANDOM_MXC_RNGA + tristate "Freescale i.MX RNGA Random Number Generator" + depends on ARCH_HAS_RNGA +--- a/drivers/char/hw_random/Makefile ++++ b/drivers/char/hw_random/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_HW_RANDOM_OMAP3_ROM) += oma + obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o + obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o + obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o ++obj-$(CONFIG_HW_RANDOM_MCS814X) += mcs814x-rng.o + obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o + obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o + obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o diff --git a/target/linux/mcs814x/patches-3.18/006-mcs814x_wdt.patch b/target/linux/mcs814x/patches-3.18/006-mcs814x_wdt.patch new file mode 100644 index 0000000..72481f6 --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/006-mcs814x_wdt.patch @@ -0,0 +1,25 @@ +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -505,6 +505,12 @@ config MESON_WATCHDOG + To compile this driver as a module, choose M here: the + module will be called meson_wdt. + ++config MCS814X_WATCHDOG ++ tristate "Moschip MCS814x watchdog" ++ depends on WATCHDOG_CORE && ARCH_MCS814X ++ help ++ Support for the Moschip MCS814x SoCs on-chip watchdog timer. ++ + # AVR32 Architecture + + config AT32AP700X_WDT +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -63,6 +63,7 @@ obj-$(CONFIG_QCOM_WDT) += qcom-wdt.o + obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o + obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o + obj-$(CONFIG_MESON_WATCHDOG) += meson_wdt.o ++obj-$(CONFIG_MCS814X_WATCHDOG) += mcs814x_wdt.o + + # AVR32 Architecture + obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o diff --git a/target/linux/mcs814x/patches-3.18/008-mcs814x_gpio.patch b/target/linux/mcs814x/patches-3.18/008-mcs814x_gpio.patch new file mode 100644 index 0000000..92c85a7 --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/008-mcs814x_gpio.patch @@ -0,0 +1,25 @@ +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -819,6 +819,12 @@ config GPIO_MC33880 + SPI driver for Freescale MC33880 high-side/low-side switch. + This provides GPIO interface supporting inputs and outputs. + ++config GPIO_MCS814X ++ tristate "Moschip MCS814x GPIO support" ++ depends on ARCH_MCS814X ++ help ++ GPIO driver for Moschip MCS814x SoC gpio controllers. ++ + config GPIO_74X164 + tristate "74x164 serial-in/parallel-out 8-bits shift register" + depends on SPI_MASTER && OF +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -49,6 +49,7 @@ obj-$(CONFIG_GPIO_MAX732X) += gpio-max73 + obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o + obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o + obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o ++obj-$(CONFIG_GPIO_MCS814X) += gpio-mcs814x.o + obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o + obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o + obj-$(CONFIG_GPIO_MOXART) += gpio-moxart.o diff --git a/target/linux/mcs814x/patches-3.18/011-mcs814x_internal_phy.patch b/target/linux/mcs814x/patches-3.18/011-mcs814x_internal_phy.patch new file mode 100644 index 0000000..20d5add --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/011-mcs814x_internal_phy.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -164,6 +164,10 @@ config RTL8306_PHY + tristate "Driver for Realtek RTL8306S switches" + select SWCONFIG + ++config MCS814X_PHY ++ tristate "Driver for the Moschip MCS814x internal PHY" ++ depends on ARCH_MCS814X ++ + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -51,3 +51,4 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o + obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o + obj-$(CONFIG_AMD_XGBE_PHY) += amd-xgbe-phy.o + obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o ++obj-$(CONFIG_MCS814X_PHY) += mcs814x.o diff --git a/target/linux/mcs814x/patches-3.18/012-mtd-cfi_cmdset_0002-force-word-write.patch b/target/linux/mcs814x/patches-3.18/012-mtd-cfi_cmdset_0002-force-word-write.patch new file mode 100644 index 0000000..10593ce --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/012-mtd-cfi_cmdset_0002-force-word-write.patch @@ -0,0 +1,14 @@ +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -40,9 +40,9 @@ + #include + + #define AMD_BOOTLOC_BUG +-#define FORCE_WORD_WRITE 0 ++#define FORCE_WORD_WRITE 1 + +-#define MAX_WORD_RETRIES 3 ++#define MAX_WORD_RETRIES 10 + + #define SST49LF004B 0x0060 + #define SST49LF040B 0x0050 diff --git a/target/linux/mcs814x/patches-3.18/013-ohci_workarounds.patch b/target/linux/mcs814x/patches-3.18/013-ohci_workarounds.patch new file mode 100644 index 0000000..8697f03 --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/013-ohci_workarounds.patch @@ -0,0 +1,64 @@ +--- a/drivers/usb/host/ohci.h ++++ b/drivers/usb/host/ohci.h +@@ -122,7 +122,7 @@ struct td { + /* PSW is only for ISO. Only 1 PSW entry is used, but on + * big-endian PPC hardware that's the second entry. + */ +-#define MAXPSW 2 ++#define MAXPSW 8 + __hc16 hwPSW [MAXPSW]; + + /* rest are purely for the driver's use */ +--- a/drivers/usb/host/ohci-hcd.c ++++ b/drivers/usb/host/ohci-hcd.c +@@ -441,6 +441,7 @@ static int ohci_init (struct ohci_hcd *o + { + int ret; + struct usb_hcd *hcd = ohci_to_hcd(ohci); ++ u32 hcca_area; + + /* Accept arbitrarily long scatter-gather lists */ + hcd->self.sg_tablesize = ~0; +@@ -501,11 +502,13 @@ static int ohci_init (struct ohci_hcd *o + (unsigned long) ohci); + set_timer_slack(&ohci->io_watchdog, msecs_to_jiffies(20)); + +- ohci->hcca = dma_alloc_coherent (hcd->self.controller, +- sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL); ++ hcca_area = ohci_readl(ohci, &ohci->regs->hcca); ++ ohci->hcca = ioremap_nocache(hcca_area, sizeof *ohci->hcca); + if (!ohci->hcca) + return -ENOMEM; + ++ ohci->hcca_dma = hcca_area; ++ + if ((ret = ohci_mem_init (ohci)) < 0) + ohci_stop (hcd); + else { +@@ -523,6 +526,7 @@ static int ohci_init (struct ohci_hcd *o + */ + static int ohci_run (struct ohci_hcd *ohci) + { ++ int i = 0; + u32 mask, val; + int first = ohci->fminterval == 0; + struct usb_hcd *hcd = ohci_to_hcd(ohci); +@@ -573,6 +577,8 @@ static int ohci_run (struct ohci_hcd *oh + msleep(val); + + memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); ++ for (i = 0; i < NUM_INTS; i++) ++ ohci->hcca->int_table[i] = 0; + + /* 2msec timelimit here means no irqs/preempt */ + spin_lock_irq (&ohci->lock); +@@ -984,9 +990,6 @@ static void ohci_stop (struct usb_hcd *h + remove_debug_files (ohci); + ohci_mem_cleanup (ohci); + if (ohci->hcca) { +- dma_free_coherent (hcd->self.controller, +- sizeof *ohci->hcca, +- ohci->hcca, ohci->hcca_dma); + ohci->hcca = NULL; + ohci->hcca_dma = 0; + } diff --git a/target/linux/mcs814x/patches-3.18/014-debuguart.patch b/target/linux/mcs814x/patches-3.18/014-debuguart.patch new file mode 100644 index 0000000..5f1b67f --- /dev/null +++ b/target/linux/mcs814x/patches-3.18/014-debuguart.patch @@ -0,0 +1,41 @@ +--- a/arch/arm/mach-mcs814x/include/mach/debug-macro.S ++++ /dev/null +@@ -1,11 +0,0 @@ +-#include +- +- .macro addruart, rp, rv, tmp +- ldr \rp, =MCS814X_PHYS_BASE +- ldr \rv, =MCS814X_VIRT_BASE +- orr \rp, \rp, #MCS814X_UART +- orr \rv, \rv, #MCS814X_UART +- .endm +- +-#define UART_SHIFT 2 +-#include +--- a/arch/arm/Kconfig.debug ++++ b/arch/arm/Kconfig.debug +@@ -1089,7 +1089,7 @@ config DEBUG_UART_8250 + (FOOTBRIDGE && !DEBUG_DC21285_PORT) || \ + ARCH_GEMINI || ARCH_IOP13XX || ARCH_IOP32X || \ + ARCH_IOP33X || ARCH_IXP4XX || \ +- ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC ++ ARCH_LPC32XX || ARCH_MCS814X || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC + + # Compatibility options for BCM63xx + config DEBUG_UART_BCM63XX +@@ -1124,6 +1124,7 @@ config DEBUG_UART_PHYS + default 0x3e000000 if DEBUG_BCM_KONA_UART + default 0x4000e400 if DEBUG_LL_UART_EFM32 + default 0x40090000 if ARCH_LPC32XX ++ default 0x400dc000 if ARCH_MCS814X + default 0x40100000 if DEBUG_PXA_UART1 + default 0x42000000 if ARCH_GEMINI + default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \ +@@ -1178,6 +1179,7 @@ config DEBUG_UART_VIRT + default 0xe0010fe0 if ARCH_RPC + default 0xe1000000 if DEBUG_MSM_UART + default 0xf0000be0 if ARCH_EBSA110 ++ default 0xf00dc000 if ARCH_MCS814X + default 0xf01fb000 if DEBUG_NOMADIK_UART + default 0xf0201000 if DEBUG_BCM2835 + default 0xf1000300 if DEBUG_BCM_5301X diff --git a/target/linux/mcs814x/profiles/000-Generic.mk b/target/linux/mcs814x/profiles/000-Generic.mk new file mode 100644 index 0000000..a6d0f30 --- /dev/null +++ b/target/linux/mcs814x/profiles/000-Generic.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Generic + NAME:=Generic profile +endef + +define Profile/Generic/Description + Default profile for Moschip MCS814x targets +endef +$(eval $(call Profile,Generic)) + diff --git a/target/linux/mcs814x/profiles/100-dLAN-USB-Extender.mk b/target/linux/mcs814x/profiles/100-dLAN-USB-Extender.mk new file mode 100644 index 0000000..168bfa1 --- /dev/null +++ b/target/linux/mcs814x/profiles/100-dLAN-USB-Extender.mk @@ -0,0 +1,25 @@ +# +# Copyright (C) 2012 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/dLAN_USB_Extender + NAME:=Devolo dLAN USB Extender + PACKAGES:=kmod-usb-serial kmod-usb-serial-ftdi +endef + +define Profile/dLAN_USB_Extender/Description + Package set specifically tuned for the Devolo dLAN USB Extender device. + + Binary packages are required to enable the power line portion of the + device, these packages can be found in the following package feed: + + src-git dlan https://github.com/ffainelli/dlan-usb-extender-3rd-party.git + + Instructions are available here: + http://ffainelli.github.io/dlan-usb-extender-3rd-party/ +endef +$(eval $(call Profile,dLAN_USB_Extender)) + diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile new file mode 100644 index 0000000..d0b266b --- /dev/null +++ b/target/linux/mediatek/Makefile @@ -0,0 +1,20 @@ +# Copyright (c) 2015 OpenWrt.org +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=mediatek +BOARDNAME:=Mediatek Ralink ARM +FEATURES:=squashfs +CPU_TYPE:=cortex-a7 +MAINTAINER:=John Crispin + +KERNEL_PATCHVER:=4.1 + +KERNELNAME:=Image dtbs zImage + +include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += \ + kmod-leds-gpio kmod-gpio-button-hotplug swconfig + +$(eval $(call BuildTarget)) diff --git a/target/linux/mediatek/base-files.mk b/target/linux/mediatek/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/mediatek/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/mediatek/base-files/etc/inittab b/target/linux/mediatek/base-files/etc/inittab new file mode 100644 index 0000000..870b3cc --- /dev/null +++ b/target/linux/mediatek/base-files/etc/inittab @@ -0,0 +1,3 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttyS0::askfirst:/bin/ash --login diff --git a/target/linux/mediatek/base-files/lib/mediatek.sh b/target/linux/mediatek/base-files/lib/mediatek.sh new file mode 100644 index 0000000..8466c72 --- /dev/null +++ b/target/linux/mediatek/base-files/lib/mediatek.sh @@ -0,0 +1,33 @@ +#!/bin/sh +# +# Copyright (C) 2015 OpenWrt.org +# + +mediatek_board_detect() { + local machine + local name + + machine=$(cat /proc/device-tree/model) + + case "$machine" in + "MediaTek MT7623 Evaluation Board") + name="mt7623_evb" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$name" > /tmp/sysinfo/board_name + echo "$machine" > /tmp/sysinfo/model +} + +mediatek_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/mediatek/base-files/lib/preinit/03_preinit_do_mediatek.sh b/target/linux/mediatek/base-files/lib/preinit/03_preinit_do_mediatek.sh new file mode 100644 index 0000000..9e5a18d --- /dev/null +++ b/target/linux/mediatek/base-files/lib/preinit/03_preinit_do_mediatek.sh @@ -0,0 +1,12 @@ +#!/bin/sh +# +# Copyright (c) 2014 The Linux Foundation. All rights reserved. +# + +do_mediatek() { + . /lib/mediatek.sh + + mediatek_board_detect +} + +boot_hook_add preinit_main do_mediatek diff --git a/target/linux/mediatek/config-4.1 b/target/linux/mediatek/config-4.1 new file mode 100644 index 0000000..5df3c2d --- /dev/null +++ b/target/linux/mediatek/config-4.1 @@ -0,0 +1,430 @@ +# CONFIG_AIO is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_APM_EMULATION is not set +# CONFIG_ARCH_ALPINE is not set +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MT7623=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +CONFIG_ARM_CPU_SUSPEND=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +# CONFIG_ARM_CRYPTO is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_AVERAGE=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_BOUNCE=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CLEANCACHE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="earlyprintk console=ttyS0,115200" +CONFIG_COMMON_CLK=y +CONFIG_COMPACTION=y +CONFIG_COREDUMP=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_GPIO=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +# CONFIG_DEBUG_MT6589_UART0 is not set +CONFIG_DEBUG_MT8127_UART0=y +# CONFIG_DEBUG_MT8135_UART3 is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0x11004000 +CONFIG_DEBUG_UART_VIRT=0xf1004000 +CONFIG_DEBUG_UNCOMPRESS=y +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DEVMEM=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_PCI is not set +CONFIG_EARLY_PRINTK=y +CONFIG_ELF_CORE=y +CONFIG_ESW_DOUBLE_VLAN_TAG=y +CONFIG_FREEZER=y +CONFIG_GE1_RGMII_AN=y +# CONFIG_GE1_RGMII_FORCE_1000 is not set +# CONFIG_GE1_RGMII_NONE is not set +# CONFIG_GE1_TRGMII_FORCE_2000 is not set +# CONFIG_GE1_TRGMII_FORCE_2600 is not set +CONFIG_GE2_INTERNAL_GPHY=y +# CONFIG_GE2_MII_AN is not set +# CONFIG_GE2_MII_FORCE_100 is not set +# CONFIG_GE2_RGMII_AN is not set +# CONFIG_GE2_RGMII_FORCE_1000 is not set +# CONFIG_GE2_RVMII_FORCE_100 is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GE_RGMII_INTERNAL_P0_AN=y +CONFIG_GIGAPHY=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HOTPLUG_CPU=y +# CONFIG_HSU_DMA_PCI is not set +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +# CONFIG_HW_SFQ is not set +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MT65XX=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_KALLSYMS=y +CONFIG_LAN_WAN_SUPPORT=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LIBFDT=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOCK_SPIN_ON_OWNER=y +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_MACH_MT6589 is not set +# CONFIG_MACH_MT6592 is not set +CONFIG_MACH_MT7623=y +CONFIG_MACH_MT8127=y +# CONFIG_MACH_MT8135 is not set +CONFIG_MAC_TO_GIGAPHY_MODE_ADDR=0x1F +CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2=0 +CONFIG_MAGIC_SYSRQ=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MDIO_GPIO=y +CONFIG_MEDIATEK_WATCHDOG=y +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MT6323 is not set +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_MTK=y +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTK_INFRACFG=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_SCPSYS=y +# CONFIG_MTK_SMB_HOOK is not set +CONFIG_MTK_THERMAL=y +CONFIG_MTK_TIMER=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +# CONFIG_NEON is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +# CONFIG_PCIE_IPROC is not set +# CONFIG_PCI_DOMAINS_GENERIC is not set +CONFIG_PCI_MSI=y +CONFIG_PDMA_NEW=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MT6397 is not set +CONFIG_PINCTRL_MT7623=y +CONFIG_PINCTRL_MT8127=y +# CONFIG_PINCTRL_MT8135 is not set +CONFIG_PINCTRL_MTK_COMMON=y +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +CONFIG_POWER_SUPPLY=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +CONFIG_PRINTK_TIME=y +CONFIG_RAETH=y +CONFIG_RAETH_CHECKSUM_OFFLOAD=y +# CONFIG_RAETH_DVT is not set +CONFIG_RAETH_GMAC2=y +# CONFIG_RAETH_HW_LRO is not set +# CONFIG_RAETH_HW_VLAN_TX is not set +# CONFIG_RAETH_LRO is not set +# CONFIG_RAETH_NAPI is not set +CONFIG_RAETH_QDMA=y +CONFIG_RAETH_QDMATX_QDMARX=y +CONFIG_RAETH_SCATTER_GATHER_RX_DMA=y +# CONFIG_RAETH_SKB_RECYCLE_2K is not set +# CONFIG_RAETH_SPECIAL_TAG is not set +# CONFIG_RAETH_TSO is not set +CONFIG_RA_NAT_NONE=y +# CONFIG_RA_NETWORK_TASKLET_BH is not set +CONFIG_RA_NETWORK_WORKQUEUE_BH=y +# CONFIG_RCU_BOOST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_EXPEDITE_BOOT is not set +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_GZIP=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_CMOS is not set +CONFIG_RT_3052_ESW=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SMP=y +# CONFIG_SMP_ON_UP is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MT65XX=y +CONFIG_SPMI=y +CONFIG_SRCU=y +CONFIG_STOP_MACHINE=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_MT65XX_USB3_PHY=y +CONFIG_USB_PHY=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USE_OF=y +# CONFIG_VDSO is not set +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WAN_AT_P0=y +# CONFIG_WAN_AT_P4 is not set +CONFIG_WATCHDOG_CORE=y +# CONFIG_XEN is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/mediatek/image/Makefile b/target/linux/mediatek/image/Makefile new file mode 100644 index 0000000..82525c9 --- /dev/null +++ b/target/linux/mediatek/image/Makefile @@ -0,0 +1,28 @@ +# Copyright (c) 2014 The Linux Foundation. All rights reserved. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Image/BuilduImage + cat $(LINUX_DIR)/arch/arm/boot/dts/mt7623-evb.dtb >> $(KDIR)/zImage$(1) + $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/zImage$(1) $(KDIR)/zImage$(1).lzma + mkimage -A arm -O linux -T kernel -C lzma -a 0x80008000 -e 0x80008000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' -d $(KDIR)/zImage$(1).lzma $(KDIR)/uImage$(1) + $(CP) $(KDIR)/uImage$(1) $(BIN_DIR)/$(IMG_PREFIX)-uImage$(1) +endef + +define Image/BuildKernel + $(call Image/BuilduImage) +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/BuilduImage,-initramfs) +endif +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +endef + +define Image/Build + $(call Image/Build/$(1),$(1)) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/mediatek/patches/0001-clk-make-strings-in-parent-name-arrays-const.patch b/target/linux/mediatek/patches/0001-clk-make-strings-in-parent-name-arrays-const.patch new file mode 100644 index 0000000..3dca509 --- /dev/null +++ b/target/linux/mediatek/patches/0001-clk-make-strings-in-parent-name-arrays-const.patch @@ -0,0 +1,100 @@ +From a38e86708141d75c643ffd58865c50a925134e4f Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Thu, 23 Apr 2015 10:35:38 +0200 +Subject: [PATCH 01/76] clk: make strings in parent name arrays const +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The clk functions and structs declare the parent_name arrays as +'const char **parent_names' which means the parent name strings +are const, but the array itself is not. Use +'const char * const * parent_names' instead which also makes +the array const. This allows us to put the parent_name arrays into +the __initconst section. + +Signed-off-by: Sascha Hauer +Reviewed-by: Krzysztof Kozlowski +Tested-by: Krzysztof Kozlowski +Acked-by: Uwe Kleine-König +--- + drivers/clk/clk-composite.c | 2 +- + drivers/clk/clk-mux.c | 4 ++-- + include/linux/clk-provider.h | 8 ++++---- + 3 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c +index 956b7e5..077f4c7 100644 +--- a/drivers/clk/clk-composite.c ++++ b/drivers/clk/clk-composite.c +@@ -188,7 +188,7 @@ static void clk_composite_disable(struct clk_hw *hw) + } + + struct clk *clk_register_composite(struct device *dev, const char *name, +- const char **parent_names, int num_parents, ++ const char * const *parent_names, int num_parents, + struct clk_hw *mux_hw, const struct clk_ops *mux_ops, + struct clk_hw *rate_hw, const struct clk_ops *rate_ops, + struct clk_hw *gate_hw, const struct clk_ops *gate_ops, +diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c +index 69a094c..1fa2a8d 100644 +--- a/drivers/clk/clk-mux.c ++++ b/drivers/clk/clk-mux.c +@@ -114,7 +114,7 @@ const struct clk_ops clk_mux_ro_ops = { + EXPORT_SYMBOL_GPL(clk_mux_ro_ops); + + struct clk *clk_register_mux_table(struct device *dev, const char *name, +- const char **parent_names, u8 num_parents, unsigned long flags, ++ const char * const *parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u32 mask, + u8 clk_mux_flags, u32 *table, spinlock_t *lock) + { +@@ -166,7 +166,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, + EXPORT_SYMBOL_GPL(clk_register_mux_table); + + struct clk *clk_register_mux(struct device *dev, const char *name, +- const char **parent_names, u8 num_parents, unsigned long flags, ++ const char * const *parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags, spinlock_t *lock) + { +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index df69531..ec609e5 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -209,7 +209,7 @@ struct clk_ops { + struct clk_init_data { + const char *name; + const struct clk_ops *ops; +- const char **parent_names; ++ const char * const *parent_names; + u8 num_parents; + unsigned long flags; + }; +@@ -426,12 +426,12 @@ extern const struct clk_ops clk_mux_ops; + extern const struct clk_ops clk_mux_ro_ops; + + struct clk *clk_register_mux(struct device *dev, const char *name, +- const char **parent_names, u8 num_parents, unsigned long flags, ++ const char * const *parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_mux_flags, spinlock_t *lock); + + struct clk *clk_register_mux_table(struct device *dev, const char *name, +- const char **parent_names, u8 num_parents, unsigned long flags, ++ const char * const *parent_names, u8 num_parents, unsigned long flags, + void __iomem *reg, u8 shift, u32 mask, + u8 clk_mux_flags, u32 *table, spinlock_t *lock); + +@@ -518,7 +518,7 @@ struct clk_composite { + }; + + struct clk *clk_register_composite(struct device *dev, const char *name, +- const char **parent_names, int num_parents, ++ const char * const *parent_names, int num_parents, + struct clk_hw *mux_hw, const struct clk_ops *mux_ops, + struct clk_hw *rate_hw, const struct clk_ops *rate_ops, + struct clk_hw *gate_hw, const struct clk_ops *gate_ops, +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0002-clk-mediatek-Add-initial-common-clock-support-for-Me.patch b/target/linux/mediatek/patches/0002-clk-mediatek-Add-initial-common-clock-support-for-Me.patch new file mode 100644 index 0000000..d5f52d1 --- /dev/null +++ b/target/linux/mediatek/patches/0002-clk-mediatek-Add-initial-common-clock-support-for-Me.patch @@ -0,0 +1,977 @@ +From f851b4ea6cae9fd5875036b6d3968375882ce56b Mon Sep 17 00:00:00 2001 +From: James Liao +Date: Thu, 23 Apr 2015 10:35:39 +0200 +Subject: [PATCH 02/76] clk: mediatek: Add initial common clock support for + Mediatek SoCs. + +This patch adds common clock support for Mediatek SoCs, including plls, +muxes and clock gates. + +Signed-off-by: James Liao +Signed-off-by: Henry Chen +Signed-off-by: Sascha Hauer +--- + drivers/clk/Makefile | 1 + + drivers/clk/mediatek/Makefile | 1 + + drivers/clk/mediatek/clk-gate.c | 137 ++++++++++++++++ + drivers/clk/mediatek/clk-gate.h | 49 ++++++ + drivers/clk/mediatek/clk-mtk.c | 220 ++++++++++++++++++++++++++ + drivers/clk/mediatek/clk-mtk.h | 159 +++++++++++++++++++ + drivers/clk/mediatek/clk-pll.c | 332 +++++++++++++++++++++++++++++++++++++++ + 7 files changed, 899 insertions(+) + create mode 100644 drivers/clk/mediatek/Makefile + create mode 100644 drivers/clk/mediatek/clk-gate.c + create mode 100644 drivers/clk/mediatek/clk-gate.h + create mode 100644 drivers/clk/mediatek/clk-mtk.c + create mode 100644 drivers/clk/mediatek/clk-mtk.h + create mode 100644 drivers/clk/mediatek/clk-pll.c + +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index 3d00c25..d965b3f 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -51,6 +51,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/ + obj-$(CONFIG_ARCH_HIP04) += hisilicon/ + obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/ + obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ ++obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ + ifeq ($(CONFIG_COMMON_CLK), y) + obj-$(CONFIG_ARCH_MMP) += mmp/ + endif +diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile +new file mode 100644 +index 0000000..c384e97 +--- /dev/null ++++ b/drivers/clk/mediatek/Makefile +@@ -0,0 +1 @@ ++obj-y += clk-mtk.o clk-pll.o clk-gate.o +diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c +new file mode 100644 +index 0000000..9d77ee3 +--- /dev/null ++++ b/drivers/clk/mediatek/clk-gate.c +@@ -0,0 +1,137 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++static int mtk_cg_bit_is_cleared(struct clk_hw *hw) ++{ ++ struct mtk_clk_gate *cg = to_clk_gate(hw); ++ u32 val; ++ ++ regmap_read(cg->regmap, cg->sta_ofs, &val); ++ ++ val &= BIT(cg->bit); ++ ++ return val == 0; ++} ++ ++static int mtk_cg_bit_is_set(struct clk_hw *hw) ++{ ++ struct mtk_clk_gate *cg = to_clk_gate(hw); ++ u32 val; ++ ++ regmap_read(cg->regmap, cg->sta_ofs, &val); ++ ++ val &= BIT(cg->bit); ++ ++ return val != 0; ++} ++ ++static void mtk_cg_set_bit(struct clk_hw *hw) ++{ ++ struct mtk_clk_gate *cg = to_clk_gate(hw); ++ ++ regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); ++} ++ ++static void mtk_cg_clr_bit(struct clk_hw *hw) ++{ ++ struct mtk_clk_gate *cg = to_clk_gate(hw); ++ ++ regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); ++} ++ ++static int mtk_cg_enable(struct clk_hw *hw) ++{ ++ mtk_cg_clr_bit(hw); ++ ++ return 0; ++} ++ ++static void mtk_cg_disable(struct clk_hw *hw) ++{ ++ mtk_cg_set_bit(hw); ++} ++ ++static int mtk_cg_enable_inv(struct clk_hw *hw) ++{ ++ mtk_cg_set_bit(hw); ++ ++ return 0; ++} ++ ++static void mtk_cg_disable_inv(struct clk_hw *hw) ++{ ++ mtk_cg_clr_bit(hw); ++} ++ ++const struct clk_ops mtk_clk_gate_ops_setclr = { ++ .is_enabled = mtk_cg_bit_is_cleared, ++ .enable = mtk_cg_enable, ++ .disable = mtk_cg_disable, ++}; ++ ++const struct clk_ops mtk_clk_gate_ops_setclr_inv = { ++ .is_enabled = mtk_cg_bit_is_set, ++ .enable = mtk_cg_enable_inv, ++ .disable = mtk_cg_disable_inv, ++}; ++ ++struct clk *mtk_clk_register_gate( ++ const char *name, ++ const char *parent_name, ++ struct regmap *regmap, ++ int set_ofs, ++ int clr_ofs, ++ int sta_ofs, ++ u8 bit, ++ const struct clk_ops *ops) ++{ ++ struct mtk_clk_gate *cg; ++ struct clk *clk; ++ struct clk_init_data init; ++ ++ cg = kzalloc(sizeof(*cg), GFP_KERNEL); ++ if (!cg) ++ return ERR_PTR(-ENOMEM); ++ ++ init.name = name; ++ init.flags = CLK_SET_RATE_PARENT; ++ init.parent_names = parent_name ? &parent_name : NULL; ++ init.num_parents = parent_name ? 1 : 0; ++ init.ops = ops; ++ ++ cg->regmap = regmap; ++ cg->set_ofs = set_ofs; ++ cg->clr_ofs = clr_ofs; ++ cg->sta_ofs = sta_ofs; ++ cg->bit = bit; ++ ++ cg->hw.init = &init; ++ ++ clk = clk_register(NULL, &cg->hw); ++ if (IS_ERR(clk)) ++ kfree(cg); ++ ++ return clk; ++} +diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h +new file mode 100644 +index 0000000..6b6780b +--- /dev/null ++++ b/drivers/clk/mediatek/clk-gate.h +@@ -0,0 +1,49 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __DRV_CLK_GATE_H ++#define __DRV_CLK_GATE_H ++ ++#include ++#include ++#include ++ ++struct mtk_clk_gate { ++ struct clk_hw hw; ++ struct regmap *regmap; ++ int set_ofs; ++ int clr_ofs; ++ int sta_ofs; ++ u8 bit; ++}; ++ ++static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw) ++{ ++ return container_of(hw, struct mtk_clk_gate, hw); ++} ++ ++extern const struct clk_ops mtk_clk_gate_ops_setclr; ++extern const struct clk_ops mtk_clk_gate_ops_setclr_inv; ++ ++struct clk *mtk_clk_register_gate( ++ const char *name, ++ const char *parent_name, ++ struct regmap *regmap, ++ int set_ofs, ++ int clr_ofs, ++ int sta_ofs, ++ u8 bit, ++ const struct clk_ops *ops); ++ ++#endif /* __DRV_CLK_GATE_H */ +diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c +new file mode 100644 +index 0000000..18444ae +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mtk.c +@@ -0,0 +1,220 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num) ++{ ++ int i; ++ struct clk_onecell_data *clk_data; ++ ++ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); ++ if (!clk_data) ++ return NULL; ++ ++ clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL); ++ if (!clk_data->clks) ++ goto err_out; ++ ++ clk_data->clk_num = clk_num; ++ ++ for (i = 0; i < clk_num; i++) ++ clk_data->clks[i] = ERR_PTR(-ENOENT); ++ ++ return clk_data; ++err_out: ++ kfree(clk_data); ++ ++ return NULL; ++} ++ ++void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, ++ struct clk_onecell_data *clk_data) ++{ ++ int i; ++ struct clk *clk; ++ ++ for (i = 0; i < num; i++) { ++ const struct mtk_fixed_factor *ff = &clks[i]; ++ ++ clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name, ++ CLK_SET_RATE_PARENT, ff->mult, ff->div); ++ ++ if (IS_ERR(clk)) { ++ pr_err("Failed to register clk %s: %ld\n", ++ ff->name, PTR_ERR(clk)); ++ continue; ++ } ++ ++ if (clk_data) ++ clk_data->clks[ff->id] = clk; ++ } ++} ++ ++int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, ++ int num, struct clk_onecell_data *clk_data) ++{ ++ int i; ++ struct clk *clk; ++ struct regmap *regmap; ++ ++ if (!clk_data) ++ return -ENOMEM; ++ ++ regmap = syscon_node_to_regmap(node); ++ if (IS_ERR(regmap)) { ++ pr_err("Cannot find regmap for %s: %ld\n", node->full_name, ++ PTR_ERR(regmap)); ++ return PTR_ERR(regmap); ++ } ++ ++ for (i = 0; i < num; i++) { ++ const struct mtk_gate *gate = &clks[i]; ++ ++ clk = mtk_clk_register_gate(gate->name, gate->parent_name, ++ regmap, ++ gate->regs->set_ofs, ++ gate->regs->clr_ofs, ++ gate->regs->sta_ofs, ++ gate->shift, gate->ops); ++ ++ if (IS_ERR(clk)) { ++ pr_err("Failed to register clk %s: %ld\n", ++ gate->name, PTR_ERR(clk)); ++ continue; ++ } ++ ++ clk_data->clks[gate->id] = clk; ++ } ++ ++ return 0; ++} ++ ++struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, ++ void __iomem *base, spinlock_t *lock) ++{ ++ struct clk *clk; ++ struct clk_mux *mux = NULL; ++ struct clk_gate *gate = NULL; ++ struct clk_divider *div = NULL; ++ struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL; ++ const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL; ++ const char * const *parent_names; ++ const char *parent; ++ int num_parents; ++ int ret; ++ ++ if (mc->mux_shift >= 0) { ++ mux = kzalloc(sizeof(*mux), GFP_KERNEL); ++ if (!mux) ++ return ERR_PTR(-ENOMEM); ++ ++ mux->reg = base + mc->mux_reg; ++ mux->mask = BIT(mc->mux_width) - 1; ++ mux->shift = mc->mux_shift; ++ mux->lock = lock; ++ ++ mux_hw = &mux->hw; ++ mux_ops = &clk_mux_ops; ++ ++ parent_names = mc->parent_names; ++ num_parents = mc->num_parents; ++ } else { ++ parent = mc->parent; ++ parent_names = &parent; ++ num_parents = 1; ++ } ++ ++ if (mc->gate_shift >= 0) { ++ gate = kzalloc(sizeof(*gate), GFP_KERNEL); ++ if (!gate) { ++ ret = -ENOMEM; ++ goto err_out; ++ } ++ ++ gate->reg = base + mc->gate_reg; ++ gate->bit_idx = mc->gate_shift; ++ gate->flags = CLK_GATE_SET_TO_DISABLE; ++ gate->lock = lock; ++ ++ gate_hw = &gate->hw; ++ gate_ops = &clk_gate_ops; ++ } ++ ++ if (mc->divider_shift >= 0) { ++ div = kzalloc(sizeof(*div), GFP_KERNEL); ++ if (!div) { ++ ret = -ENOMEM; ++ goto err_out; ++ } ++ ++ div->reg = base + mc->divider_reg; ++ div->shift = mc->divider_shift; ++ div->width = mc->divider_width; ++ div->lock = lock; ++ ++ div_hw = &div->hw; ++ div_ops = &clk_divider_ops; ++ } ++ ++ clk = clk_register_composite(NULL, mc->name, parent_names, num_parents, ++ mux_hw, mux_ops, ++ div_hw, div_ops, ++ gate_hw, gate_ops, ++ mc->flags); ++ ++ if (IS_ERR(clk)) { ++ kfree(gate); ++ kfree(mux); ++ } ++ ++ return clk; ++err_out: ++ kfree(mux); ++ ++ return ERR_PTR(ret); ++} ++ ++void mtk_clk_register_composites(const struct mtk_composite *mcs, ++ int num, void __iomem *base, spinlock_t *lock, ++ struct clk_onecell_data *clk_data) ++{ ++ struct clk *clk; ++ int i; ++ ++ for (i = 0; i < num; i++) { ++ const struct mtk_composite *mc = &mcs[i]; ++ ++ clk = mtk_clk_register_composite(mc, base, lock); ++ ++ if (IS_ERR(clk)) { ++ pr_err("Failed to register clk %s: %ld\n", ++ mc->name, PTR_ERR(clk)); ++ continue; ++ } ++ ++ if (clk_data) ++ clk_data->clks[mc->id] = clk; ++ } ++} +diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h +new file mode 100644 +index 0000000..694fc39 +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -0,0 +1,159 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __DRV_CLK_MTK_H ++#define __DRV_CLK_MTK_H ++ ++#include ++#include ++#include ++#include ++ ++#define MAX_MUX_GATE_BIT 31 ++#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) ++ ++#define MHZ (1000 * 1000) ++ ++struct mtk_fixed_factor { ++ int id; ++ const char *name; ++ const char *parent_name; ++ int mult; ++ int div; ++}; ++ ++#define FACTOR(_id, _name, _parent, _mult, _div) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .mult = _mult, \ ++ .div = _div, \ ++ } ++ ++extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, ++ int num, struct clk_onecell_data *clk_data); ++ ++struct mtk_composite { ++ int id; ++ const char *name; ++ const char * const * parent_names; ++ const char *parent; ++ unsigned flags; ++ ++ uint32_t mux_reg; ++ uint32_t divider_reg; ++ uint32_t gate_reg; ++ ++ signed char mux_shift; ++ signed char mux_width; ++ signed char gate_shift; ++ ++ signed char divider_shift; ++ signed char divider_width; ++ ++ signed char num_parents; ++}; ++ ++#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .mux_reg = _reg, \ ++ .mux_shift = _shift, \ ++ .mux_width = _width, \ ++ .gate_reg = _reg, \ ++ .gate_shift = _gate, \ ++ .divider_shift = -1, \ ++ .parent_names = _parents, \ ++ .num_parents = ARRAY_SIZE(_parents), \ ++ .flags = CLK_SET_RATE_PARENT, \ ++ } ++ ++#define MUX(_id, _name, _parents, _reg, _shift, _width) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .mux_reg = _reg, \ ++ .mux_shift = _shift, \ ++ .mux_width = _width, \ ++ .gate_shift = -1, \ ++ .divider_shift = -1, \ ++ .parent_names = _parents, \ ++ .num_parents = ARRAY_SIZE(_parents), \ ++ .flags = CLK_SET_RATE_PARENT, \ ++ } ++ ++#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \ ++ .id = _id, \ ++ .parent = _parent, \ ++ .name = _name, \ ++ .divider_reg = _div_reg, \ ++ .divider_shift = _div_shift, \ ++ .divider_width = _div_width, \ ++ .gate_reg = _gate_reg, \ ++ .gate_shift = _gate_shift, \ ++ .mux_shift = -1, \ ++ .flags = 0, \ ++ } ++ ++struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, ++ void __iomem *base, spinlock_t *lock); ++ ++void mtk_clk_register_composites(const struct mtk_composite *mcs, ++ int num, void __iomem *base, spinlock_t *lock, ++ struct clk_onecell_data *clk_data); ++ ++struct mtk_gate_regs { ++ u32 sta_ofs; ++ u32 clr_ofs; ++ u32 set_ofs; ++}; ++ ++struct mtk_gate { ++ int id; ++ const char *name; ++ const char *parent_name; ++ const struct mtk_gate_regs *regs; ++ int shift; ++ const struct clk_ops *ops; ++}; ++ ++int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, ++ int num, struct clk_onecell_data *clk_data); ++ ++struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); ++ ++#define HAVE_RST_BAR BIT(0) ++ ++struct mtk_pll_data { ++ int id; ++ const char *name; ++ uint32_t reg; ++ uint32_t pwr_reg; ++ uint32_t en_mask; ++ uint32_t pd_reg; ++ uint32_t tuner_reg; ++ int pd_shift; ++ unsigned int flags; ++ const struct clk_ops *ops; ++ u32 rst_bar_mask; ++ unsigned long fmax; ++ int pcwbits; ++ uint32_t pcw_reg; ++ int pcw_shift; ++}; ++ ++void __init mtk_clk_register_plls(struct device_node *node, ++ const struct mtk_pll_data *plls, int num_plls, ++ struct clk_onecell_data *clk_data); ++ ++#endif /* __DRV_CLK_MTK_H */ +diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c +new file mode 100644 +index 0000000..66154ca +--- /dev/null ++++ b/drivers/clk/mediatek/clk-pll.c +@@ -0,0 +1,332 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++ ++#define REG_CON0 0 ++#define REG_CON1 4 ++ ++#define CON0_BASE_EN BIT(0) ++#define CON0_PWR_ON BIT(0) ++#define CON0_ISO_EN BIT(1) ++#define CON0_PCW_CHG BIT(31) ++ ++#define AUDPLL_TUNER_EN BIT(31) ++ ++#define POSTDIV_MASK 0x7 ++#define INTEGER_BITS 7 ++ ++/* ++ * MediaTek PLLs are configured through their pcw value. The pcw value describes ++ * a divider in the PLL feedback loop which consists of 7 bits for the integer ++ * part and the remaining bits (if present) for the fractional part. Also they ++ * have a 3 bit power-of-two post divider. ++ */ ++ ++struct mtk_clk_pll { ++ struct clk_hw hw; ++ void __iomem *base_addr; ++ void __iomem *pd_addr; ++ void __iomem *pwr_addr; ++ void __iomem *tuner_addr; ++ void __iomem *pcw_addr; ++ const struct mtk_pll_data *data; ++}; ++ ++static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) ++{ ++ return container_of(hw, struct mtk_clk_pll, hw); ++} ++ ++static int mtk_pll_is_prepared(struct clk_hw *hw) ++{ ++ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); ++ ++ return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; ++} ++ ++static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, ++ u32 pcw, int postdiv) ++{ ++ int pcwbits = pll->data->pcwbits; ++ int pcwfbits; ++ u64 vco; ++ u8 c = 0; ++ ++ /* The fractional part of the PLL divider. */ ++ pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; ++ ++ vco = (u64)fin * pcw; ++ ++ if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) ++ c = 1; ++ ++ vco >>= pcwfbits; ++ ++ if (c) ++ vco++; ++ ++ return ((unsigned long)vco + postdiv - 1) / postdiv; ++} ++ ++static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, ++ int postdiv) ++{ ++ u32 con1, pd, val; ++ int pll_en; ++ ++ /* set postdiv */ ++ pd = readl(pll->pd_addr); ++ pd &= ~(POSTDIV_MASK << pll->data->pd_shift); ++ pd |= (ffs(postdiv) - 1) << pll->data->pd_shift; ++ writel(pd, pll->pd_addr); ++ ++ pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; ++ ++ /* set pcw */ ++ val = readl(pll->pcw_addr); ++ ++ val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1, ++ pll->data->pcw_shift); ++ val |= pcw << pll->data->pcw_shift; ++ writel(val, pll->pcw_addr); ++ ++ con1 = readl(pll->base_addr + REG_CON1); ++ ++ if (pll_en) ++ con1 |= CON0_PCW_CHG; ++ ++ writel(con1, pll->base_addr + REG_CON1); ++ if (pll->tuner_addr) ++ writel(con1 + 1, pll->tuner_addr); ++ ++ if (pll_en) ++ udelay(20); ++} ++ ++/* ++ * mtk_pll_calc_values - calculate good values for a given input frequency. ++ * @pll: The pll ++ * @pcw: The pcw value (output) ++ * @postdiv: The post divider (output) ++ * @freq: The desired target frequency ++ * @fin: The input frequency ++ * ++ */ ++static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, ++ u32 freq, u32 fin) ++{ ++ unsigned long fmin = 1000 * MHZ; ++ u64 _pcw; ++ u32 val; ++ ++ if (freq > pll->data->fmax) ++ freq = pll->data->fmax; ++ ++ for (val = 0; val < 4; val++) { ++ *postdiv = 1 << val; ++ if (freq * *postdiv >= fmin) ++ break; ++ } ++ ++ /* _pcw = freq * postdiv / fin * 2^pcwfbits */ ++ _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); ++ do_div(_pcw, fin); ++ ++ *pcw = (u32)_pcw; ++} ++ ++static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); ++ u32 pcw = 0; ++ u32 postdiv; ++ ++ mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); ++ mtk_pll_set_rate_regs(pll, pcw, postdiv); ++ ++ return 0; ++} ++ ++static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); ++ u32 postdiv; ++ u32 pcw; ++ ++ postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; ++ postdiv = 1 << postdiv; ++ ++ pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; ++ pcw &= GENMASK(pll->data->pcwbits - 1, 0); ++ ++ return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); ++} ++ ++static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *prate) ++{ ++ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); ++ u32 pcw = 0; ++ int postdiv; ++ ++ mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate); ++ ++ return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); ++} ++ ++static int mtk_pll_prepare(struct clk_hw *hw) ++{ ++ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); ++ u32 r; ++ ++ r = readl(pll->pwr_addr) | CON0_PWR_ON; ++ writel(r, pll->pwr_addr); ++ udelay(1); ++ ++ r = readl(pll->pwr_addr) & ~CON0_ISO_EN; ++ writel(r, pll->pwr_addr); ++ udelay(1); ++ ++ r = readl(pll->base_addr + REG_CON0); ++ r |= pll->data->en_mask; ++ writel(r, pll->base_addr + REG_CON0); ++ ++ if (pll->tuner_addr) { ++ r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; ++ writel(r, pll->tuner_addr); ++ } ++ ++ udelay(20); ++ ++ if (pll->data->flags & HAVE_RST_BAR) { ++ r = readl(pll->base_addr + REG_CON0); ++ r |= pll->data->rst_bar_mask; ++ writel(r, pll->base_addr + REG_CON0); ++ } ++ ++ return 0; ++} ++ ++static void mtk_pll_unprepare(struct clk_hw *hw) ++{ ++ struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); ++ u32 r; ++ ++ if (pll->data->flags & HAVE_RST_BAR) { ++ r = readl(pll->base_addr + REG_CON0); ++ r &= ~pll->data->rst_bar_mask; ++ writel(r, pll->base_addr + REG_CON0); ++ } ++ ++ if (pll->tuner_addr) { ++ r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; ++ writel(r, pll->tuner_addr); ++ } ++ ++ r = readl(pll->base_addr + REG_CON0); ++ r &= ~CON0_BASE_EN; ++ writel(r, pll->base_addr + REG_CON0); ++ ++ r = readl(pll->pwr_addr) | CON0_ISO_EN; ++ writel(r, pll->pwr_addr); ++ ++ r = readl(pll->pwr_addr) & ~CON0_PWR_ON; ++ writel(r, pll->pwr_addr); ++} ++ ++static const struct clk_ops mtk_pll_ops = { ++ .is_prepared = mtk_pll_is_prepared, ++ .prepare = mtk_pll_prepare, ++ .unprepare = mtk_pll_unprepare, ++ .recalc_rate = mtk_pll_recalc_rate, ++ .round_rate = mtk_pll_round_rate, ++ .set_rate = mtk_pll_set_rate, ++}; ++ ++static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, ++ void __iomem *base) ++{ ++ struct mtk_clk_pll *pll; ++ struct clk_init_data init; ++ struct clk *clk; ++ const char *parent_name = "clk26m"; ++ ++ pll = kzalloc(sizeof(*pll), GFP_KERNEL); ++ if (!pll) ++ return ERR_PTR(-ENOMEM); ++ ++ pll->base_addr = base + data->reg; ++ pll->pwr_addr = base + data->pwr_reg; ++ pll->pd_addr = base + data->pd_reg; ++ pll->pcw_addr = base + data->pcw_reg; ++ if (data->tuner_reg) ++ pll->tuner_addr = base + data->tuner_reg; ++ pll->hw.init = &init; ++ pll->data = data; ++ ++ init.name = data->name; ++ init.ops = &mtk_pll_ops; ++ init.parent_names = &parent_name; ++ init.num_parents = 1; ++ ++ clk = clk_register(NULL, &pll->hw); ++ ++ if (IS_ERR(clk)) ++ kfree(pll); ++ ++ return clk; ++} ++ ++void __init mtk_clk_register_plls(struct device_node *node, ++ const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) ++{ ++ void __iomem *base; ++ int r, i; ++ struct clk *clk; ++ ++ base = of_iomap(node, 0); ++ if (!base) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return; ++ } ++ ++ for (i = 0; i < num_plls; i++) { ++ const struct mtk_pll_data *pll = &plls[i]; ++ ++ clk = mtk_clk_register_pll(pll, base); ++ ++ if (IS_ERR(clk)) { ++ pr_err("Failed to register clk %s: %ld\n", ++ pll->name, PTR_ERR(clk)); ++ continue; ++ } ++ ++ clk_data->clks[pll->id] = clk; ++ } ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++} +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0003-clk-mediatek-Add-reset-controller-support.patch b/target/linux/mediatek/patches/0003-clk-mediatek-Add-reset-controller-support.patch new file mode 100644 index 0000000..bb6f64b --- /dev/null +++ b/target/linux/mediatek/patches/0003-clk-mediatek-Add-reset-controller-support.patch @@ -0,0 +1,155 @@ +From c91e8490e45c68ea517f70f24568034b7735e8b9 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Thu, 23 Apr 2015 10:35:40 +0200 +Subject: [PATCH 03/76] clk: mediatek: Add reset controller support + +The pericfg and infracfg units also provide reset lines to several +other SoC internal units. This adds a function which can be called +from the pericfg and infracfg initialization functions which will +register the reset controller using reset_controller_register. The +reset controller will provide support for resetting the units +connected to the pericfg and infracfg controller. The units resetted +by this controller can use the standard reset device tree binding +to gain access to the reset lines. + +Signed-off-by: Sascha Hauer +Acked-by: Philipp Zabel +--- + drivers/clk/mediatek/Makefile | 1 + + drivers/clk/mediatek/clk-mtk.h | 10 +++++ + drivers/clk/mediatek/reset.c | 97 ++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 108 insertions(+) + create mode 100644 drivers/clk/mediatek/reset.c + +diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile +index c384e97..0b6f1c3 100644 +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -1 +1,2 @@ + obj-y += clk-mtk.o clk-pll.o clk-gate.o ++obj-$(CONFIG_RESET_CONTROLLER) += reset.o +diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h +index 694fc39..61035b9 100644 +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -156,4 +156,14 @@ void __init mtk_clk_register_plls(struct device_node *node, + const struct mtk_pll_data *plls, int num_plls, + struct clk_onecell_data *clk_data); + ++#ifdef CONFIG_RESET_CONTROLLER ++void mtk_register_reset_controller(struct device_node *np, ++ unsigned int num_regs, int regofs); ++#else ++static inline void mtk_register_reset_controller(struct device_node *np, ++ unsigned int num_regs, int regofs) ++{ ++} ++#endif ++ + #endif /* __DRV_CLK_MTK_H */ +diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c +new file mode 100644 +index 0000000..9e9fe4b +--- /dev/null ++++ b/drivers/clk/mediatek/reset.c +@@ -0,0 +1,97 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++ ++struct mtk_reset { ++ struct regmap *regmap; ++ int regofs; ++ struct reset_controller_dev rcdev; ++}; ++ ++static int mtk_reset_assert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); ++ ++ return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), ++ BIT(id % 32), ~0); ++} ++ ++static int mtk_reset_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev); ++ ++ return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2), ++ BIT(id % 32), 0); ++} ++ ++static int mtk_reset(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ int ret; ++ ++ ret = mtk_reset_assert(rcdev, id); ++ if (ret) ++ return ret; ++ ++ return mtk_reset_deassert(rcdev, id); ++} ++ ++static struct reset_control_ops mtk_reset_ops = { ++ .assert = mtk_reset_assert, ++ .deassert = mtk_reset_deassert, ++ .reset = mtk_reset, ++}; ++ ++void mtk_register_reset_controller(struct device_node *np, ++ unsigned int num_regs, int regofs) ++{ ++ struct mtk_reset *data; ++ int ret; ++ struct regmap *regmap; ++ ++ regmap = syscon_node_to_regmap(np); ++ if (IS_ERR(regmap)) { ++ pr_err("Cannot find regmap for %s: %ld\n", np->full_name, ++ PTR_ERR(regmap)); ++ return; ++ } ++ ++ data = kzalloc(sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return; ++ ++ data->regmap = regmap; ++ data->regofs = regofs; ++ data->rcdev.owner = THIS_MODULE; ++ data->rcdev.nr_resets = num_regs * 32; ++ data->rcdev.ops = &mtk_reset_ops; ++ data->rcdev.of_node = np; ++ ++ ret = reset_controller_register(&data->rcdev); ++ if (ret) { ++ pr_err("could not register reset controller: %d\n", ret); ++ kfree(data); ++ return; ++ } ++} +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0004-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8135.patch b/target/linux/mediatek/patches/0004-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8135.patch new file mode 100644 index 0000000..8666128 --- /dev/null +++ b/target/linux/mediatek/patches/0004-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8135.patch @@ -0,0 +1,952 @@ +From 242572135fdb513cba0506415c7e26a0909eb4b5 Mon Sep 17 00:00:00 2001 +From: James Liao +Date: Thu, 23 Apr 2015 10:35:41 +0200 +Subject: [PATCH 04/76] clk: mediatek: Add basic clocks for Mediatek MT8135. + +This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, +INFRA and PERI clocks. + +Signed-off-by: James Liao +Signed-off-by: Henry Chen +Signed-off-by: Sascha Hauer +--- + drivers/clk/mediatek/Makefile | 1 + + drivers/clk/mediatek/clk-mt8135.c | 644 ++++++++++++++++++++ + include/dt-bindings/clock/mt8135-clk.h | 194 ++++++ + .../dt-bindings/reset-controller/mt8135-resets.h | 64 ++ + 4 files changed, 903 insertions(+) + create mode 100644 drivers/clk/mediatek/clk-mt8135.c + create mode 100644 include/dt-bindings/clock/mt8135-clk.h + create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h + +diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile +index 0b6f1c3..12ce576 100644 +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -1,2 +1,3 @@ + obj-y += clk-mtk.o clk-pll.o clk-gate.o + obj-$(CONFIG_RESET_CONTROLLER) += reset.o ++obj-y += clk-mt8135.o +diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c +new file mode 100644 +index 0000000..a63435b +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt8135.c +@@ -0,0 +1,644 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++static DEFINE_SPINLOCK(mt8135_clk_lock); ++ ++static const struct mtk_fixed_factor root_clk_alias[] __initconst = { ++ FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), ++}; ++ ++static const struct mtk_fixed_factor top_divs[] __initconst = { ++ FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2), ++ FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3), ++ FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5), ++ FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7), ++ ++ FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3), ++ FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5), ++ FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7), ++ FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26), ++ ++ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), ++ FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3), ++ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), ++ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), ++ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2), ++ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2), ++ ++ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1), ++ FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3), ++ FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5), ++ FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6), ++ FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8), ++ FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12), ++ ++ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1), ++ ++ FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1), ++ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1), ++ ++ FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1), ++ ++ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6), ++ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), ++ FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10), ++ ++ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6), ++ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8), ++ ++ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1), ++ ++ FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1), ++ FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4), ++ FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8), ++ FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16), ++ FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24), ++ ++ FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), ++ FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), ++ FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), ++ ++ FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1), ++ FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1), ++ ++ FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1), ++ ++ FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2), ++ FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3), ++ ++ FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2), ++ FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4), ++ ++ FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), ++}; ++ ++static const char * const axi_parents[] __initconst = { ++ "clk26m", ++ "syspll_d3", ++ "syspll_d4", ++ "syspll_d6", ++ "univpll_d5", ++ "univpll2_d2", ++ "syspll_d3p5" ++}; ++ ++static const char * const smi_parents[] __initconst = { ++ "clk26m", ++ "clkph_mck", ++ "syspll_d2p5", ++ "syspll_d3", ++ "syspll_d8", ++ "univpll_d5", ++ "univpll1_d2", ++ "univpll1_d6", ++ "mmpll_d3", ++ "mmpll_d4", ++ "mmpll_d5", ++ "mmpll_d6", ++ "mmpll_d7", ++ "vdecpll", ++ "lvdspll" ++}; ++ ++static const char * const mfg_parents[] __initconst = { ++ "clk26m", ++ "univpll1_d4", ++ "syspll_d2", ++ "syspll_d2p5", ++ "syspll_d3", ++ "univpll_d5", ++ "univpll1_d2", ++ "mmpll_d2", ++ "mmpll_d3", ++ "mmpll_d4", ++ "mmpll_d5", ++ "mmpll_d6", ++ "mmpll_d7" ++}; ++ ++static const char * const irda_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d8", ++ "univpll1_d6" ++}; ++ ++static const char * const cam_parents[] __initconst = { ++ "clk26m", ++ "syspll_d3", ++ "syspll_d3p5", ++ "syspll_d4", ++ "univpll_d5", ++ "univpll2_d2", ++ "univpll_d7", ++ "univpll1_d4" ++}; ++ ++static const char * const aud_intbus_parents[] __initconst = { ++ "clk26m", ++ "syspll_d6", ++ "univpll_d10" ++}; ++ ++static const char * const jpg_parents[] __initconst = { ++ "clk26m", ++ "syspll_d5", ++ "syspll_d4", ++ "syspll_d3", ++ "univpll_d7", ++ "univpll2_d2", ++ "univpll_d5" ++}; ++ ++static const char * const disp_parents[] __initconst = { ++ "clk26m", ++ "syspll_d3p5", ++ "syspll_d3", ++ "univpll2_d2", ++ "univpll_d5", ++ "univpll1_d2", ++ "lvdspll", ++ "vdecpll" ++}; ++ ++static const char * const msdc30_parents[] __initconst = { ++ "clk26m", ++ "syspll_d6", ++ "syspll_d5", ++ "univpll1_d4", ++ "univpll2_d4", ++ "msdcpll" ++}; ++ ++static const char * const usb20_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d6", ++ "univpll1_d10" ++}; ++ ++static const char * const venc_parents[] __initconst = { ++ "clk26m", ++ "syspll_d3", ++ "syspll_d8", ++ "univpll_d5", ++ "univpll1_d6", ++ "mmpll_d4", ++ "mmpll_d5", ++ "mmpll_d6" ++}; ++ ++static const char * const spi_parents[] __initconst = { ++ "clk26m", ++ "syspll_d6", ++ "syspll_d8", ++ "syspll_d10", ++ "univpll1_d6", ++ "univpll1_d8" ++}; ++ ++static const char * const uart_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d8" ++}; ++ ++static const char * const mem_parents[] __initconst = { ++ "clk26m", ++ "clkph_mck" ++}; ++ ++static const char * const camtg_parents[] __initconst = { ++ "clk26m", ++ "univpll_d26", ++ "univpll1_d6", ++ "syspll_d16", ++ "syspll_d8" ++}; ++ ++static const char * const audio_parents[] __initconst = { ++ "clk26m", ++ "syspll_d24" ++}; ++ ++static const char * const fix_parents[] __initconst = { ++ "rtc32k", ++ "clk26m", ++ "univpll_d5", ++ "univpll_d7", ++ "univpll1_d2", ++ "univpll1_d4", ++ "univpll1_d6", ++ "univpll1_d8" ++}; ++ ++static const char * const vdec_parents[] __initconst = { ++ "clk26m", ++ "vdecpll", ++ "clkph_mck", ++ "syspll_d2p5", ++ "syspll_d3", ++ "syspll_d3p5", ++ "syspll_d4", ++ "syspll_d5", ++ "syspll_d6", ++ "syspll_d8", ++ "univpll1_d2", ++ "univpll2_d2", ++ "univpll_d7", ++ "univpll_d10", ++ "univpll2_d4", ++ "lvdspll" ++}; ++ ++static const char * const ddrphycfg_parents[] __initconst = { ++ "clk26m", ++ "axi_sel", ++ "syspll_d12" ++}; ++ ++static const char * const dpilvds_parents[] __initconst = { ++ "clk26m", ++ "lvdspll", ++ "lvdspll_d2", ++ "lvdspll_d4", ++ "lvdspll_d8" ++}; ++ ++static const char * const pmicspi_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d6", ++ "syspll_d8", ++ "syspll_d10", ++ "univpll1_d10", ++ "mempll_mck_d4", ++ "univpll_d26", ++ "syspll_d24" ++}; ++ ++static const char * const smi_mfg_as_parents[] __initconst = { ++ "clk26m", ++ "smi_sel", ++ "mfg_sel", ++ "mem_sel" ++}; ++ ++static const char * const gcpu_parents[] __initconst = { ++ "clk26m", ++ "syspll_d4", ++ "univpll_d7", ++ "syspll_d5", ++ "syspll_d6" ++}; ++ ++static const char * const dpi1_parents[] __initconst = { ++ "clk26m", ++ "tvhdmi_h_ck", ++ "tvhdmi_d2", ++ "tvhdmi_d4" ++}; ++ ++static const char * const cci_parents[] __initconst = { ++ "clk26m", ++ "mainpll_537p3m", ++ "univpll_d3", ++ "syspll_d2p5", ++ "syspll_d3", ++ "syspll_d5" ++}; ++ ++static const char * const apll_parents[] __initconst = { ++ "clk26m", ++ "apll_ck", ++ "apll_d4", ++ "apll_d8", ++ "apll_d16", ++ "apll_d24" ++}; ++ ++static const char * const hdmipll_parents[] __initconst = { ++ "clk26m", ++ "hdmitx_clkdig_cts", ++ "hdmitx_clkdig_d2", ++ "hdmitx_clkdig_d3" ++}; ++ ++static const struct mtk_composite top_muxes[] __initconst = { ++ /* CLK_CFG_0 */ ++ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, ++ 0x0140, 0, 3, INVALID_MUX_GATE_BIT), ++ MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15), ++ MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23), ++ MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31), ++ /* CLK_CFG_1 */ ++ MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7), ++ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, ++ 0x0144, 8, 2, 15), ++ MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23), ++ MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31), ++ /* CLK_CFG_2 */ ++ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15), ++ MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23), ++ MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31), ++ /* CLK_CFG_3 */ ++ MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7), ++ /* CLK_CFG_4 */ ++ MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15), ++ MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23), ++ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31), ++ /* CLK_CFG_6 */ ++ MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7), ++ MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15), ++ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31), ++ /* CLK_CFG_7 */ ++ MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7), ++ MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15), ++ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, ++ 0x015c, 16, 2, 23), ++ MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31), ++ /* CLK_CFG_8 */ ++ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15), ++ MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents, ++ 0x0164, 16, 2, 23), ++ MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31), ++ /* CLK_CFG_9 */ ++ MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7), ++ MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15), ++ MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23), ++ MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31), ++}; ++ ++static const struct mtk_gate_regs infra_cg_regs = { ++ .set_ofs = 0x0040, ++ .clr_ofs = 0x0044, ++ .sta_ofs = 0x0048, ++}; ++ ++#define GATE_ICG(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &infra_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate infra_clks[] __initconst = { ++ GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), ++ GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), ++ GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21), ++ GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20), ++ GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), ++ GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), ++ GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), ++ GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7), ++ GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6), ++ GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), ++ GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2), ++ GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1), ++ GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0), ++}; ++ ++static const struct mtk_gate_regs peri0_cg_regs = { ++ .set_ofs = 0x0008, ++ .clr_ofs = 0x0010, ++ .sta_ofs = 0x0018, ++}; ++ ++static const struct mtk_gate_regs peri1_cg_regs = { ++ .set_ofs = 0x000c, ++ .clr_ofs = 0x0014, ++ .sta_ofs = 0x001c, ++}; ++ ++#define GATE_PERI0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_PERI1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate peri_gates[] __initconst = { ++ /* PERI0 */ ++ GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31), ++ GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30), ++ GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29), ++ GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28), ++ GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27), ++ GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26), ++ GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25), ++ GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24), ++ GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23), ++ GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22), ++ GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21), ++ GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20), ++ GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19), ++ GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18), ++ GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17), ++ GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16), ++ GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15), ++ GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14), ++ GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13), ++ GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), ++ GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), ++ GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), ++ GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), ++ GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8), ++ GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7), ++ GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6), ++ GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5), ++ GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4), ++ GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3), ++ GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2), ++ GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), ++ GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0), ++ /* PERI1 */ ++ GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8), ++ GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7), ++ GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6), ++ GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5), ++ GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4), ++ GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3), ++ GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2), ++ GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1), ++ GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0), ++}; ++ ++static const char * const uart_ck_sel_parents[] __initconst = { ++ "clk26m", ++ "uart_sel", ++}; ++ ++static const struct mtk_composite peri_clks[] __initconst = { ++ MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), ++ MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), ++ MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), ++ MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), ++}; ++ ++static void __init mtk_topckgen_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ void __iomem *base; ++ int r; ++ ++ base = of_iomap(node, 0); ++ if (!base) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return; ++ } ++ ++ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ ++ mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); ++ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); ++ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, ++ &mt8135_clk_lock, clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++} ++CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init); ++ ++static void __init mtk_infrasys_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); ++ ++ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), ++ clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 2, 0x30); ++} ++CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init); ++ ++static void __init mtk_pericfg_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ void __iomem *base; ++ ++ base = of_iomap(node, 0); ++ if (!base) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return; ++ } ++ ++ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); ++ ++ mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), ++ clk_data); ++ mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, ++ &mt8135_clk_lock, clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 2, 0); ++} ++CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init); ++ ++#define MT8135_PLL_FMAX (2000 * MHZ) ++#define CON0_MT8135_RST_BAR BIT(27) ++ ++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .reg = _reg, \ ++ .pwr_reg = _pwr_reg, \ ++ .en_mask = _en_mask, \ ++ .flags = _flags, \ ++ .rst_bar_mask = CON0_MT8135_RST_BAR, \ ++ .fmax = MT8135_PLL_FMAX, \ ++ .pcwbits = _pcwbits, \ ++ .pd_reg = _pd_reg, \ ++ .pd_shift = _pd_shift, \ ++ .tuner_reg = _tuner_reg, \ ++ .pcw_reg = _pcw_reg, \ ++ .pcw_shift = _pcw_shift, \ ++ } ++ ++static const struct mtk_pll_data plls[] = { ++ PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0), ++ PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0), ++ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0), ++ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9), ++ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0), ++ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0), ++ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0), ++ PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), ++ PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0), ++ PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0), ++}; ++ ++static void __init mtk_apmixedsys_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ ++ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); ++ if (!clk_data) ++ return; ++ ++ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); ++} ++CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys", ++ mtk_apmixedsys_init); +diff --git a/include/dt-bindings/clock/mt8135-clk.h b/include/dt-bindings/clock/mt8135-clk.h +new file mode 100644 +index 0000000..6dac6c0 +--- /dev/null ++++ b/include/dt-bindings/clock/mt8135-clk.h +@@ -0,0 +1,194 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT8135_H ++#define _DT_BINDINGS_CLK_MT8135_H ++ ++/* TOPCKGEN */ ++ ++#define CLK_TOP_DSI0_LNTC_DSICLK 1 ++#define CLK_TOP_HDMITX_CLKDIG_CTS 2 ++#define CLK_TOP_CLKPH_MCK 3 ++#define CLK_TOP_CPUM_TCK_IN 4 ++#define CLK_TOP_MAINPLL_806M 5 ++#define CLK_TOP_MAINPLL_537P3M 6 ++#define CLK_TOP_MAINPLL_322P4M 7 ++#define CLK_TOP_MAINPLL_230P3M 8 ++#define CLK_TOP_UNIVPLL_624M 9 ++#define CLK_TOP_UNIVPLL_416M 10 ++#define CLK_TOP_UNIVPLL_249P6M 11 ++#define CLK_TOP_UNIVPLL_178P3M 12 ++#define CLK_TOP_UNIVPLL_48M 13 ++#define CLK_TOP_MMPLL_D2 14 ++#define CLK_TOP_MMPLL_D3 15 ++#define CLK_TOP_MMPLL_D5 16 ++#define CLK_TOP_MMPLL_D7 17 ++#define CLK_TOP_MMPLL_D4 18 ++#define CLK_TOP_MMPLL_D6 19 ++#define CLK_TOP_SYSPLL_D2 20 ++#define CLK_TOP_SYSPLL_D4 21 ++#define CLK_TOP_SYSPLL_D6 22 ++#define CLK_TOP_SYSPLL_D8 23 ++#define CLK_TOP_SYSPLL_D10 24 ++#define CLK_TOP_SYSPLL_D12 25 ++#define CLK_TOP_SYSPLL_D16 26 ++#define CLK_TOP_SYSPLL_D24 27 ++#define CLK_TOP_SYSPLL_D3 28 ++#define CLK_TOP_SYSPLL_D2P5 29 ++#define CLK_TOP_SYSPLL_D5 30 ++#define CLK_TOP_SYSPLL_D3P5 31 ++#define CLK_TOP_UNIVPLL1_D2 32 ++#define CLK_TOP_UNIVPLL1_D4 33 ++#define CLK_TOP_UNIVPLL1_D6 34 ++#define CLK_TOP_UNIVPLL1_D8 35 ++#define CLK_TOP_UNIVPLL1_D10 36 ++#define CLK_TOP_UNIVPLL2_D2 37 ++#define CLK_TOP_UNIVPLL2_D4 38 ++#define CLK_TOP_UNIVPLL2_D6 39 ++#define CLK_TOP_UNIVPLL2_D8 40 ++#define CLK_TOP_UNIVPLL_D3 41 ++#define CLK_TOP_UNIVPLL_D5 42 ++#define CLK_TOP_UNIVPLL_D7 43 ++#define CLK_TOP_UNIVPLL_D10 44 ++#define CLK_TOP_UNIVPLL_D26 45 ++#define CLK_TOP_APLL 46 ++#define CLK_TOP_APLL_D4 47 ++#define CLK_TOP_APLL_D8 48 ++#define CLK_TOP_APLL_D16 49 ++#define CLK_TOP_APLL_D24 50 ++#define CLK_TOP_LVDSPLL_D2 51 ++#define CLK_TOP_LVDSPLL_D4 52 ++#define CLK_TOP_LVDSPLL_D8 53 ++#define CLK_TOP_LVDSTX_CLKDIG_CT 54 ++#define CLK_TOP_VPLL_DPIX 55 ++#define CLK_TOP_TVHDMI_H 56 ++#define CLK_TOP_HDMITX_CLKDIG_D2 57 ++#define CLK_TOP_HDMITX_CLKDIG_D3 58 ++#define CLK_TOP_TVHDMI_D2 59 ++#define CLK_TOP_TVHDMI_D4 60 ++#define CLK_TOP_MEMPLL_MCK_D4 61 ++#define CLK_TOP_AXI_SEL 62 ++#define CLK_TOP_SMI_SEL 63 ++#define CLK_TOP_MFG_SEL 64 ++#define CLK_TOP_IRDA_SEL 65 ++#define CLK_TOP_CAM_SEL 66 ++#define CLK_TOP_AUD_INTBUS_SEL 67 ++#define CLK_TOP_JPG_SEL 68 ++#define CLK_TOP_DISP_SEL 69 ++#define CLK_TOP_MSDC30_1_SEL 70 ++#define CLK_TOP_MSDC30_2_SEL 71 ++#define CLK_TOP_MSDC30_3_SEL 72 ++#define CLK_TOP_MSDC30_4_SEL 73 ++#define CLK_TOP_USB20_SEL 74 ++#define CLK_TOP_VENC_SEL 75 ++#define CLK_TOP_SPI_SEL 76 ++#define CLK_TOP_UART_SEL 77 ++#define CLK_TOP_MEM_SEL 78 ++#define CLK_TOP_CAMTG_SEL 79 ++#define CLK_TOP_AUDIO_SEL 80 ++#define CLK_TOP_FIX_SEL 81 ++#define CLK_TOP_VDEC_SEL 82 ++#define CLK_TOP_DDRPHYCFG_SEL 83 ++#define CLK_TOP_DPILVDS_SEL 84 ++#define CLK_TOP_PMICSPI_SEL 85 ++#define CLK_TOP_MSDC30_0_SEL 86 ++#define CLK_TOP_SMI_MFG_AS_SEL 87 ++#define CLK_TOP_GCPU_SEL 88 ++#define CLK_TOP_DPI1_SEL 89 ++#define CLK_TOP_CCI_SEL 90 ++#define CLK_TOP_APLL_SEL 91 ++#define CLK_TOP_HDMIPLL_SEL 92 ++#define CLK_TOP_NR_CLK 93 ++ ++/* APMIXED_SYS */ ++ ++#define CLK_APMIXED_ARMPLL1 1 ++#define CLK_APMIXED_ARMPLL2 2 ++#define CLK_APMIXED_MAINPLL 3 ++#define CLK_APMIXED_UNIVPLL 4 ++#define CLK_APMIXED_MMPLL 5 ++#define CLK_APMIXED_MSDCPLL 6 ++#define CLK_APMIXED_TVDPLL 7 ++#define CLK_APMIXED_LVDSPLL 8 ++#define CLK_APMIXED_AUDPLL 9 ++#define CLK_APMIXED_VDECPLL 10 ++#define CLK_APMIXED_NR_CLK 11 ++ ++/* INFRA_SYS */ ++ ++#define CLK_INFRA_PMIC_WRAP 1 ++#define CLK_INFRA_PMICSPI 2 ++#define CLK_INFRA_CCIF1_AP_CTRL 3 ++#define CLK_INFRA_CCIF0_AP_CTRL 4 ++#define CLK_INFRA_KP 5 ++#define CLK_INFRA_CPUM 6 ++#define CLK_INFRA_M4U 7 ++#define CLK_INFRA_MFGAXI 8 ++#define CLK_INFRA_DEVAPC 9 ++#define CLK_INFRA_AUDIO 10 ++#define CLK_INFRA_MFG_BUS 11 ++#define CLK_INFRA_SMI 12 ++#define CLK_INFRA_DBGCLK 13 ++#define CLK_INFRA_NR_CLK 14 ++ ++/* PERI_SYS */ ++ ++#define CLK_PERI_I2C5 1 ++#define CLK_PERI_I2C4 2 ++#define CLK_PERI_I2C3 3 ++#define CLK_PERI_I2C2 4 ++#define CLK_PERI_I2C1 5 ++#define CLK_PERI_I2C0 6 ++#define CLK_PERI_UART3 7 ++#define CLK_PERI_UART2 8 ++#define CLK_PERI_UART1 9 ++#define CLK_PERI_UART0 10 ++#define CLK_PERI_IRDA 11 ++#define CLK_PERI_NLI 12 ++#define CLK_PERI_MD_HIF 13 ++#define CLK_PERI_AP_HIF 14 ++#define CLK_PERI_MSDC30_3 15 ++#define CLK_PERI_MSDC30_2 16 ++#define CLK_PERI_MSDC30_1 17 ++#define CLK_PERI_MSDC20_2 18 ++#define CLK_PERI_MSDC20_1 19 ++#define CLK_PERI_AP_DMA 20 ++#define CLK_PERI_USB1 21 ++#define CLK_PERI_USB0 22 ++#define CLK_PERI_PWM 23 ++#define CLK_PERI_PWM7 24 ++#define CLK_PERI_PWM6 25 ++#define CLK_PERI_PWM5 26 ++#define CLK_PERI_PWM4 27 ++#define CLK_PERI_PWM3 28 ++#define CLK_PERI_PWM2 29 ++#define CLK_PERI_PWM1 30 ++#define CLK_PERI_THERM 31 ++#define CLK_PERI_NFI 32 ++#define CLK_PERI_USBSLV 33 ++#define CLK_PERI_USB1_MCU 34 ++#define CLK_PERI_USB0_MCU 35 ++#define CLK_PERI_GCPU 36 ++#define CLK_PERI_FHCTL 37 ++#define CLK_PERI_SPI1 38 ++#define CLK_PERI_AUXADC 39 ++#define CLK_PERI_PERI_PWRAP 40 ++#define CLK_PERI_I2C6 41 ++#define CLK_PERI_UART0_SEL 42 ++#define CLK_PERI_UART1_SEL 43 ++#define CLK_PERI_UART2_SEL 44 ++#define CLK_PERI_UART3_SEL 45 ++#define CLK_PERI_NR_CLK 46 ++ ++#endif /* _DT_BINDINGS_CLK_MT8135_H */ +diff --git a/include/dt-bindings/reset-controller/mt8135-resets.h b/include/dt-bindings/reset-controller/mt8135-resets.h +new file mode 100644 +index 0000000..1fb6295 +--- /dev/null ++++ b/include/dt-bindings/reset-controller/mt8135-resets.h +@@ -0,0 +1,64 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Flora Fu, MediaTek ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 ++#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 ++ ++/* INFRACFG resets */ ++#define MT8135_INFRA_EMI_REG_RST 0 ++#define MT8135_INFRA_DRAMC0_A0_RST 1 ++#define MT8135_INFRA_CCIF0_RST 2 ++#define MT8135_INFRA_APCIRQ_EINT_RST 3 ++#define MT8135_INFRA_APXGPT_RST 4 ++#define MT8135_INFRA_SCPSYS_RST 5 ++#define MT8135_INFRA_CCIF1_RST 6 ++#define MT8135_INFRA_PMIC_WRAP_RST 7 ++#define MT8135_INFRA_KP_RST 8 ++#define MT8135_INFRA_EMI_RST 32 ++#define MT8135_INFRA_DRAMC0_RST 34 ++#define MT8135_INFRA_SMI_RST 35 ++#define MT8135_INFRA_M4U_RST 36 ++ ++/* PERICFG resets */ ++#define MT8135_PERI_UART0_SW_RST 0 ++#define MT8135_PERI_UART1_SW_RST 1 ++#define MT8135_PERI_UART2_SW_RST 2 ++#define MT8135_PERI_UART3_SW_RST 3 ++#define MT8135_PERI_IRDA_SW_RST 4 ++#define MT8135_PERI_PTP_SW_RST 5 ++#define MT8135_PERI_AP_HIF_SW_RST 6 ++#define MT8135_PERI_GPCU_SW_RST 7 ++#define MT8135_PERI_MD_HIF_SW_RST 8 ++#define MT8135_PERI_NLI_SW_RST 9 ++#define MT8135_PERI_AUXADC_SW_RST 10 ++#define MT8135_PERI_DMA_SW_RST 11 ++#define MT8135_PERI_NFI_SW_RST 14 ++#define MT8135_PERI_PWM_SW_RST 15 ++#define MT8135_PERI_THERM_SW_RST 16 ++#define MT8135_PERI_MSDC0_SW_RST 17 ++#define MT8135_PERI_MSDC1_SW_RST 18 ++#define MT8135_PERI_MSDC2_SW_RST 19 ++#define MT8135_PERI_MSDC3_SW_RST 20 ++#define MT8135_PERI_I2C0_SW_RST 22 ++#define MT8135_PERI_I2C1_SW_RST 23 ++#define MT8135_PERI_I2C2_SW_RST 24 ++#define MT8135_PERI_I2C3_SW_RST 25 ++#define MT8135_PERI_I2C4_SW_RST 26 ++#define MT8135_PERI_I2C5_SW_RST 27 ++#define MT8135_PERI_I2C6_SW_RST 28 ++#define MT8135_PERI_USB_SW_RST 29 ++#define MT8135_PERI_SPI1_SW_RST 33 ++#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 ++ ++#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0005-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8173.patch b/target/linux/mediatek/patches/0005-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8173.patch new file mode 100644 index 0000000..9c0e289 --- /dev/null +++ b/target/linux/mediatek/patches/0005-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8173.patch @@ -0,0 +1,1179 @@ +From 0efcd47787019284a334186fce134ee475c79211 Mon Sep 17 00:00:00 2001 +From: James Liao +Date: Thu, 23 Apr 2015 10:35:42 +0200 +Subject: [PATCH 05/76] clk: mediatek: Add basic clocks for Mediatek MT8173. + +This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs, +INFRA and PERI clocks. + +Signed-off-by: James Liao +Signed-off-by: Henry Chen +Signed-off-by: Sascha Hauer +--- + drivers/clk/mediatek/Makefile | 1 + + drivers/clk/mediatek/clk-mt8173.c | 830 ++++++++++++++++++++ + include/dt-bindings/clock/mt8173-clk.h | 235 ++++++ + .../dt-bindings/reset-controller/mt8173-resets.h | 63 ++ + 4 files changed, 1129 insertions(+) + create mode 100644 drivers/clk/mediatek/clk-mt8173.c + create mode 100644 include/dt-bindings/clock/mt8173-clk.h + create mode 100644 include/dt-bindings/reset-controller/mt8173-resets.h + +diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile +index 12ce576..8e4b2a4 100644 +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -1,3 +1,4 @@ + obj-y += clk-mtk.o clk-pll.o clk-gate.o + obj-$(CONFIG_RESET_CONTROLLER) += reset.o + obj-y += clk-mt8135.o ++obj-y += clk-mt8173.o +diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c +new file mode 100644 +index 0000000..357b080 +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt8173.c +@@ -0,0 +1,830 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static DEFINE_SPINLOCK(mt8173_clk_lock); ++ ++static const struct mtk_fixed_factor root_clk_alias[] __initconst = { ++ FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_DPI, "dpi_ck", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1), ++}; ++ ++static const struct mtk_fixed_factor top_divs[] __initconst = { ++ FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2), ++ FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3), ++ ++ FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2), ++ FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3), ++ FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5), ++ FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7), ++ ++ FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4), ++ FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3), ++ ++ FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2), ++ FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3), ++ FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5), ++ FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7), ++ FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26), ++ ++ FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1), ++ FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793), ++ FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1), ++ ++ FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2), ++ FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3), ++ ++ FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1), ++ FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1), ++ ++ FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), ++ FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), ++ ++ FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1), ++ FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2), ++ FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4), ++ FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8), ++ FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16), ++ ++ FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), ++ FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), ++ FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), ++ ++ FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), ++ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), ++ ++ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), ++ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), ++ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), ++ FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), ++ FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2), ++ FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4), ++ ++ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1), ++ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8), ++ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16), ++ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1), ++ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1), ++ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1), ++ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4), ++ ++ FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1), ++ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2), ++ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4), ++ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8), ++ FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16), ++ ++ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8), ++ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8), ++ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8), ++ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2), ++ ++ FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3), ++ FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4), ++ ++ FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), ++ FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2), ++ FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4), ++}; ++ ++static const char * const axi_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d2", ++ "syspll_d5", ++ "syspll1_d4", ++ "univpll_d5", ++ "univpll2_d2", ++ "dmpll_d2", ++ "dmpll_d4" ++}; ++ ++static const char * const mem_parents[] __initconst = { ++ "clk26m", ++ "dmpll_ck" ++}; ++ ++static const char * const ddrphycfg_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d8" ++}; ++ ++static const char * const mm_parents[] __initconst = { ++ "clk26m", ++ "vencpll_d2", ++ "main_h364m", ++ "syspll1_d2", ++ "syspll_d5", ++ "syspll1_d4", ++ "univpll1_d2", ++ "univpll2_d2", ++ "dmpll_d2" ++}; ++ ++static const char * const pwm_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d4", ++ "univpll3_d2", ++ "univpll1_d4" ++}; ++ ++static const char * const vdec_parents[] __initconst = { ++ "clk26m", ++ "vcodecpll_ck", ++ "tvdpll_445p5m", ++ "univpll_d3", ++ "vencpll_d2", ++ "syspll_d3", ++ "univpll1_d2", ++ "mmpll_d2", ++ "dmpll_d2", ++ "dmpll_d4" ++}; ++ ++static const char * const venc_parents[] __initconst = { ++ "clk26m", ++ "vcodecpll_ck", ++ "tvdpll_445p5m", ++ "univpll_d3", ++ "vencpll_d2", ++ "syspll_d3", ++ "univpll1_d2", ++ "univpll2_d2", ++ "dmpll_d2", ++ "dmpll_d4" ++}; ++ ++static const char * const mfg_parents[] __initconst = { ++ "clk26m", ++ "mmpll_ck", ++ "dmpll_ck", ++ "clk26m", ++ "clk26m", ++ "clk26m", ++ "clk26m", ++ "clk26m", ++ "clk26m", ++ "syspll_d3", ++ "syspll1_d2", ++ "syspll_d5", ++ "univpll_d3", ++ "univpll1_d2", ++ "univpll_d5", ++ "univpll2_d2" ++}; ++ ++static const char * const camtg_parents[] __initconst = { ++ "clk26m", ++ "univpll_d26", ++ "univpll2_d2", ++ "syspll3_d2", ++ "syspll3_d4", ++ "univpll1_d4" ++}; ++ ++static const char * const uart_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d8" ++}; ++ ++static const char * const spi_parents[] __initconst = { ++ "clk26m", ++ "syspll3_d2", ++ "syspll1_d4", ++ "syspll4_d2", ++ "univpll3_d2", ++ "univpll2_d4", ++ "univpll1_d8" ++}; ++ ++static const char * const usb20_parents[] __initconst = { ++ "clk26m", ++ "univpll1_d8", ++ "univpll3_d4" ++}; ++ ++static const char * const usb30_parents[] __initconst = { ++ "clk26m", ++ "univpll3_d2", ++ "usb_syspll_125m", ++ "univpll2_d4" ++}; ++ ++static const char * const msdc50_0_h_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d2", ++ "syspll2_d2", ++ "syspll4_d2", ++ "univpll_d5", ++ "univpll1_d4" ++}; ++ ++static const char * const msdc50_0_parents[] __initconst = { ++ "clk26m", ++ "msdcpll_ck", ++ "msdcpll_d2", ++ "univpll1_d4", ++ "syspll2_d2", ++ "syspll_d7", ++ "msdcpll_d4", ++ "vencpll_d4", ++ "tvdpll_ck", ++ "univpll_d2", ++ "univpll1_d2", ++ "mmpll_ck", ++ "msdcpll2_ck", ++ "msdcpll2_d2", ++ "msdcpll2_d4" ++}; ++ ++static const char * const msdc30_1_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d2", ++ "msdcpll_d4", ++ "univpll1_d4", ++ "syspll2_d2", ++ "syspll_d7", ++ "univpll_d7", ++ "vencpll_d4" ++}; ++ ++static const char * const msdc30_2_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d2", ++ "msdcpll_d4", ++ "univpll1_d4", ++ "syspll2_d2", ++ "syspll_d7", ++ "univpll_d7", ++ "vencpll_d2" ++}; ++ ++static const char * const msdc30_3_parents[] __initconst = { ++ "clk26m", ++ "msdcpll2_ck", ++ "msdcpll2_d2", ++ "univpll2_d2", ++ "msdcpll2_d4", ++ "msdcpll_d4", ++ "univpll1_d4", ++ "syspll2_d2", ++ "syspll_d7", ++ "univpll_d7", ++ "vencpll_d4", ++ "msdcpll_ck", ++ "msdcpll_d2", ++ "msdcpll_d4" ++}; ++ ++static const char * const audio_parents[] __initconst = { ++ "clk26m", ++ "syspll3_d4", ++ "syspll4_d4", ++ "syspll1_d16" ++}; ++ ++static const char * const aud_intbus_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d4", ++ "syspll4_d2", ++ "univpll3_d2", ++ "univpll2_d8", ++ "dmpll_d4", ++ "dmpll_d8" ++}; ++ ++static const char * const pmicspi_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d8", ++ "syspll3_d4", ++ "syspll1_d16", ++ "univpll3_d4", ++ "univpll_d26", ++ "dmpll_d8", ++ "dmpll_d16" ++}; ++ ++static const char * const scp_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d2", ++ "univpll_d5", ++ "syspll_d5", ++ "dmpll_d2", ++ "dmpll_d4" ++}; ++ ++static const char * const atb_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d2", ++ "univpll_d5", ++ "dmpll_d2" ++}; ++ ++static const char * const venc_lt_parents[] __initconst = { ++ "clk26m", ++ "univpll_d3", ++ "vcodecpll_ck", ++ "tvdpll_445p5m", ++ "vencpll_d2", ++ "syspll_d3", ++ "univpll1_d2", ++ "univpll2_d2", ++ "syspll1_d2", ++ "univpll_d5", ++ "vcodecpll_370p5", ++ "dmpll_ck" ++}; ++ ++static const char * const dpi0_parents[] __initconst = { ++ "clk26m", ++ "tvdpll_d2", ++ "tvdpll_d4", ++ "clk26m", ++ "clk26m", ++ "tvdpll_d8", ++ "tvdpll_d16" ++}; ++ ++static const char * const irda_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d4", ++ "syspll2_d4" ++}; ++ ++static const char * const cci400_parents[] __initconst = { ++ "clk26m", ++ "vencpll_ck", ++ "armca7pll_754m", ++ "armca7pll_502m", ++ "univpll_d2", ++ "syspll_d2", ++ "msdcpll_ck", ++ "dmpll_ck" ++}; ++ ++static const char * const aud_1_parents[] __initconst = { ++ "clk26m", ++ "apll1_ck", ++ "univpll2_d4", ++ "univpll2_d8" ++}; ++ ++static const char * const aud_2_parents[] __initconst = { ++ "clk26m", ++ "apll2_ck", ++ "univpll2_d4", ++ "univpll2_d8" ++}; ++ ++static const char * const mem_mfg_in_parents[] __initconst = { ++ "clk26m", ++ "mmpll_ck", ++ "dmpll_ck", ++ "clk26m" ++}; ++ ++static const char * const axi_mfg_in_parents[] __initconst = { ++ "clk26m", ++ "axi_sel", ++ "dmpll_d2" ++}; ++ ++static const char * const scam_parents[] __initconst = { ++ "clk26m", ++ "syspll3_d2", ++ "univpll2_d4", ++ "dmpll_d4" ++}; ++ ++static const char * const spinfi_ifr_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d8", ++ "univpll3_d4", ++ "syspll4_d2", ++ "univpll2_d4", ++ "univpll3_d2", ++ "syspll1_d4", ++ "univpll1_d4" ++}; ++ ++static const char * const hdmi_parents[] __initconst = { ++ "clk26m", ++ "hdmitx_dig_cts", ++ "hdmitxpll_d2", ++ "hdmitxpll_d3" ++}; ++ ++static const char * const dpilvds_parents[] __initconst = { ++ "clk26m", ++ "lvdspll", ++ "lvdspll_d2", ++ "lvdspll_d4", ++ "lvdspll_d8", ++ "fpc_ck" ++}; ++ ++static const char * const msdc50_2_h_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d2", ++ "syspll2_d2", ++ "syspll4_d2", ++ "univpll_d5", ++ "univpll1_d4" ++}; ++ ++static const char * const hdcp_parents[] __initconst = { ++ "clk26m", ++ "syspll4_d2", ++ "syspll3_d4", ++ "univpll2_d4" ++}; ++ ++static const char * const hdcp_24m_parents[] __initconst = { ++ "clk26m", ++ "univpll_d26", ++ "univpll_d52", ++ "univpll2_d8" ++}; ++ ++static const char * const rtc_parents[] __initconst = { ++ "clkrtc_int", ++ "clkrtc_ext", ++ "clk26m", ++ "univpll3_d8" ++}; ++ ++static const char * const i2s0_m_ck_parents[] __initconst = { ++ "apll1_div1", ++ "apll2_div1" ++}; ++ ++static const char * const i2s1_m_ck_parents[] __initconst = { ++ "apll1_div2", ++ "apll2_div2" ++}; ++ ++static const char * const i2s2_m_ck_parents[] __initconst = { ++ "apll1_div3", ++ "apll2_div3" ++}; ++ ++static const char * const i2s3_m_ck_parents[] __initconst = { ++ "apll1_div4", ++ "apll2_div4" ++}; ++ ++static const char * const i2s3_b_ck_parents[] __initconst = { ++ "apll1_div5", ++ "apll2_div5" ++}; ++ ++static const struct mtk_composite top_muxes[] __initconst = { ++ /* CLK_CFG_0 */ ++ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), ++ MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1), ++ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23), ++ MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31), ++ /* CLK_CFG_1 */ ++ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), ++ MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15), ++ MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23), ++ MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31), ++ /* CLK_CFG_2 */ ++ MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7), ++ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15), ++ MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23), ++ MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31), ++ /* CLK_CFG_3 */ ++ MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7), ++ MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15), ++ MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23), ++ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31), ++ /* CLK_CFG_4 */ ++ MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15), ++ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23), ++ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31), ++ /* CLK_CFG_5 */ ++ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */), ++ MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15), ++ MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23), ++ MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31), ++ /* CLK_CFG_6 */ ++ MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7), ++ MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23), ++ MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31), ++ /* CLK_CFG_7 */ ++ MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7), ++ MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23), ++ MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31), ++ /* CLK_CFG_12 */ ++ MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7), ++ MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31), ++ /* CLK_CFG_13 */ ++ MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7), ++ MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23), ++ MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2), ++ ++ DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24), ++ DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0), ++ DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8), ++ DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16), ++ DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24), ++ DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0), ++ ++ DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28), ++ DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0), ++ DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8), ++ DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16), ++ DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24), ++ DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4), ++ ++ MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1), ++ MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1), ++ MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1), ++ MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1), ++ MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), ++}; ++ ++static const struct mtk_gate_regs infra_cg_regs = { ++ .set_ofs = 0x0040, ++ .clr_ofs = 0x0044, ++ .sta_ofs = 0x0048, ++}; ++ ++#define GATE_ICG(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &infra_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate infra_clks[] __initconst = { ++ GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), ++ GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1), ++ GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5), ++ GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), ++ GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7), ++ GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), ++ GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "clk_null", 15), ++ GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), ++ GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18), ++ GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), ++ GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), ++}; ++ ++static const struct mtk_gate_regs peri0_cg_regs = { ++ .set_ofs = 0x0008, ++ .clr_ofs = 0x0010, ++ .sta_ofs = 0x0018, ++}; ++ ++static const struct mtk_gate_regs peri1_cg_regs = { ++ .set_ofs = 0x000c, ++ .clr_ofs = 0x0014, ++ .sta_ofs = 0x001c, ++}; ++ ++#define GATE_PERI0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_PERI1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate peri_gates[] __initconst = { ++ /* PERI0 */ ++ GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0), ++ GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1), ++ GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2), ++ GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3), ++ GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4), ++ GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5), ++ GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6), ++ GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7), ++ GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8), ++ GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9), ++ GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10), ++ GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11), ++ GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12), ++ GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13), ++ GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14), ++ GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15), ++ GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16), ++ GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17), ++ GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18), ++ GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19), ++ GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20), ++ GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21), ++ GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22), ++ GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23), ++ GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24), ++ GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25), ++ GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26), ++ GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27), ++ GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28), ++ GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29), ++ GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30), ++ GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31), ++ /* PERI1 */ ++ GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0), ++ GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1), ++ GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2), ++}; ++ ++static const char * const uart_ck_sel_parents[] __initconst = { ++ "clk26m", ++ "uart_sel", ++}; ++ ++static const struct mtk_composite peri_clks[] __initconst = { ++ MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), ++ MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), ++ MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), ++ MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), ++}; ++ ++static void __init mtk_topckgen_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ void __iomem *base; ++ int r; ++ ++ base = of_iomap(node, 0); ++ if (!base) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return; ++ } ++ ++ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ ++ mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); ++ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); ++ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, ++ &mt8173_clk_lock, clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_TOP_CCI400_SEL]); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++} ++CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init); ++ ++static void __init mtk_infrasys_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); ++ ++ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 2, 0x30); ++} ++CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); ++ ++static void __init mtk_pericfg_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ void __iomem *base; ++ ++ base = of_iomap(node, 0); ++ if (!base) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return; ++ } ++ ++ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); ++ ++ mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), ++ clk_data); ++ mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, ++ &mt8173_clk_lock, clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 2, 0); ++} ++CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); ++ ++#define MT8173_PLL_FMAX (3000UL * MHZ) ++ ++#define CON0_MT8173_RST_BAR BIT(24) ++ ++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, \ ++ _tuner_reg, _pcw_reg, _pcw_shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .reg = _reg, \ ++ .pwr_reg = _pwr_reg, \ ++ .en_mask = _en_mask, \ ++ .flags = _flags, \ ++ .rst_bar_mask = CON0_MT8173_RST_BAR, \ ++ .fmax = MT8173_PLL_FMAX, \ ++ .pcwbits = _pcwbits, \ ++ .pd_reg = _pd_reg, \ ++ .pd_shift = _pd_shift, \ ++ .tuner_reg = _tuner_reg, \ ++ .pcw_reg = _pcw_reg, \ ++ .pcw_shift = _pcw_shift, \ ++ } ++ ++static const struct mtk_pll_data plls[] = { ++ PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0), ++ PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0), ++ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0), ++ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14), ++ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0), ++ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0), ++ PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0), ++ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0), ++ PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0), ++ PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0), ++ PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0), ++ PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0), ++ PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0), ++ PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0), ++}; ++ ++static void __init mtk_apmixedsys_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ ++ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); ++ if (!clk_data) ++ return; ++ ++ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMCA15PLL]); ++} ++CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys", ++ mtk_apmixedsys_init); +diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h +new file mode 100644 +index 0000000..4ad76ed +--- /dev/null ++++ b/include/dt-bindings/clock/mt8173-clk.h +@@ -0,0 +1,235 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT8173_H ++#define _DT_BINDINGS_CLK_MT8173_H ++ ++/* TOPCKGEN */ ++ ++#define CLK_TOP_CLKPH_MCK_O 1 ++#define CLK_TOP_DPI 2 ++#define CLK_TOP_USB_SYSPLL_125M 3 ++#define CLK_TOP_HDMITX_DIG_CTS 4 ++#define CLK_TOP_ARMCA7PLL_754M 5 ++#define CLK_TOP_ARMCA7PLL_502M 6 ++#define CLK_TOP_MAIN_H546M 7 ++#define CLK_TOP_MAIN_H364M 8 ++#define CLK_TOP_MAIN_H218P4M 9 ++#define CLK_TOP_MAIN_H156M 10 ++#define CLK_TOP_TVDPLL_445P5M 11 ++#define CLK_TOP_TVDPLL_594M 12 ++#define CLK_TOP_UNIV_624M 13 ++#define CLK_TOP_UNIV_416M 14 ++#define CLK_TOP_UNIV_249P6M 15 ++#define CLK_TOP_UNIV_178P3M 16 ++#define CLK_TOP_UNIV_48M 17 ++#define CLK_TOP_CLKRTC_EXT 18 ++#define CLK_TOP_CLKRTC_INT 19 ++#define CLK_TOP_FPC 20 ++#define CLK_TOP_HDMITXPLL_D2 21 ++#define CLK_TOP_HDMITXPLL_D3 22 ++#define CLK_TOP_ARMCA7PLL_D2 23 ++#define CLK_TOP_ARMCA7PLL_D3 24 ++#define CLK_TOP_APLL1 25 ++#define CLK_TOP_APLL2 26 ++#define CLK_TOP_DMPLL 27 ++#define CLK_TOP_DMPLL_D2 28 ++#define CLK_TOP_DMPLL_D4 29 ++#define CLK_TOP_DMPLL_D8 30 ++#define CLK_TOP_DMPLL_D16 31 ++#define CLK_TOP_LVDSPLL_D2 32 ++#define CLK_TOP_LVDSPLL_D4 33 ++#define CLK_TOP_LVDSPLL_D8 34 ++#define CLK_TOP_MMPLL 35 ++#define CLK_TOP_MMPLL_D2 36 ++#define CLK_TOP_MSDCPLL 37 ++#define CLK_TOP_MSDCPLL_D2 38 ++#define CLK_TOP_MSDCPLL_D4 39 ++#define CLK_TOP_MSDCPLL2 40 ++#define CLK_TOP_MSDCPLL2_D2 41 ++#define CLK_TOP_MSDCPLL2_D4 42 ++#define CLK_TOP_SYSPLL_D2 43 ++#define CLK_TOP_SYSPLL1_D2 44 ++#define CLK_TOP_SYSPLL1_D4 45 ++#define CLK_TOP_SYSPLL1_D8 46 ++#define CLK_TOP_SYSPLL1_D16 47 ++#define CLK_TOP_SYSPLL_D3 48 ++#define CLK_TOP_SYSPLL2_D2 49 ++#define CLK_TOP_SYSPLL2_D4 50 ++#define CLK_TOP_SYSPLL_D5 51 ++#define CLK_TOP_SYSPLL3_D2 52 ++#define CLK_TOP_SYSPLL3_D4 53 ++#define CLK_TOP_SYSPLL_D7 54 ++#define CLK_TOP_SYSPLL4_D2 55 ++#define CLK_TOP_SYSPLL4_D4 56 ++#define CLK_TOP_TVDPLL 57 ++#define CLK_TOP_TVDPLL_D2 58 ++#define CLK_TOP_TVDPLL_D4 59 ++#define CLK_TOP_TVDPLL_D8 60 ++#define CLK_TOP_TVDPLL_D16 61 ++#define CLK_TOP_UNIVPLL_D2 62 ++#define CLK_TOP_UNIVPLL1_D2 63 ++#define CLK_TOP_UNIVPLL1_D4 64 ++#define CLK_TOP_UNIVPLL1_D8 65 ++#define CLK_TOP_UNIVPLL_D3 66 ++#define CLK_TOP_UNIVPLL2_D2 67 ++#define CLK_TOP_UNIVPLL2_D4 68 ++#define CLK_TOP_UNIVPLL2_D8 69 ++#define CLK_TOP_UNIVPLL_D5 70 ++#define CLK_TOP_UNIVPLL3_D2 71 ++#define CLK_TOP_UNIVPLL3_D4 72 ++#define CLK_TOP_UNIVPLL3_D8 73 ++#define CLK_TOP_UNIVPLL_D7 74 ++#define CLK_TOP_UNIVPLL_D26 75 ++#define CLK_TOP_UNIVPLL_D52 76 ++#define CLK_TOP_VCODECPLL 77 ++#define CLK_TOP_VCODECPLL_370P5 78 ++#define CLK_TOP_VENCPLL 79 ++#define CLK_TOP_VENCPLL_D2 80 ++#define CLK_TOP_VENCPLL_D4 81 ++#define CLK_TOP_AXI_SEL 82 ++#define CLK_TOP_MEM_SEL 83 ++#define CLK_TOP_DDRPHYCFG_SEL 84 ++#define CLK_TOP_MM_SEL 85 ++#define CLK_TOP_PWM_SEL 86 ++#define CLK_TOP_VDEC_SEL 87 ++#define CLK_TOP_VENC_SEL 88 ++#define CLK_TOP_MFG_SEL 89 ++#define CLK_TOP_CAMTG_SEL 90 ++#define CLK_TOP_UART_SEL 91 ++#define CLK_TOP_SPI_SEL 92 ++#define CLK_TOP_USB20_SEL 93 ++#define CLK_TOP_USB30_SEL 94 ++#define CLK_TOP_MSDC50_0_H_SEL 95 ++#define CLK_TOP_MSDC50_0_SEL 96 ++#define CLK_TOP_MSDC30_1_SEL 97 ++#define CLK_TOP_MSDC30_2_SEL 98 ++#define CLK_TOP_MSDC30_3_SEL 99 ++#define CLK_TOP_AUDIO_SEL 100 ++#define CLK_TOP_AUD_INTBUS_SEL 101 ++#define CLK_TOP_PMICSPI_SEL 102 ++#define CLK_TOP_SCP_SEL 103 ++#define CLK_TOP_ATB_SEL 104 ++#define CLK_TOP_VENC_LT_SEL 105 ++#define CLK_TOP_DPI0_SEL 106 ++#define CLK_TOP_IRDA_SEL 107 ++#define CLK_TOP_CCI400_SEL 108 ++#define CLK_TOP_AUD_1_SEL 109 ++#define CLK_TOP_AUD_2_SEL 110 ++#define CLK_TOP_MEM_MFG_IN_SEL 111 ++#define CLK_TOP_AXI_MFG_IN_SEL 112 ++#define CLK_TOP_SCAM_SEL 113 ++#define CLK_TOP_SPINFI_IFR_SEL 114 ++#define CLK_TOP_HDMI_SEL 115 ++#define CLK_TOP_DPILVDS_SEL 116 ++#define CLK_TOP_MSDC50_2_H_SEL 117 ++#define CLK_TOP_HDCP_SEL 118 ++#define CLK_TOP_HDCP_24M_SEL 119 ++#define CLK_TOP_RTC_SEL 120 ++#define CLK_TOP_APLL1_DIV0 121 ++#define CLK_TOP_APLL1_DIV1 122 ++#define CLK_TOP_APLL1_DIV2 123 ++#define CLK_TOP_APLL1_DIV3 124 ++#define CLK_TOP_APLL1_DIV4 125 ++#define CLK_TOP_APLL1_DIV5 126 ++#define CLK_TOP_APLL2_DIV0 127 ++#define CLK_TOP_APLL2_DIV1 128 ++#define CLK_TOP_APLL2_DIV2 129 ++#define CLK_TOP_APLL2_DIV3 130 ++#define CLK_TOP_APLL2_DIV4 131 ++#define CLK_TOP_APLL2_DIV5 132 ++#define CLK_TOP_I2S0_M_SEL 133 ++#define CLK_TOP_I2S1_M_SEL 134 ++#define CLK_TOP_I2S2_M_SEL 135 ++#define CLK_TOP_I2S3_M_SEL 136 ++#define CLK_TOP_I2S3_B_SEL 137 ++#define CLK_TOP_NR_CLK 138 ++ ++/* APMIXED_SYS */ ++ ++#define CLK_APMIXED_ARMCA15PLL 1 ++#define CLK_APMIXED_ARMCA7PLL 2 ++#define CLK_APMIXED_MAINPLL 3 ++#define CLK_APMIXED_UNIVPLL 4 ++#define CLK_APMIXED_MMPLL 5 ++#define CLK_APMIXED_MSDCPLL 6 ++#define CLK_APMIXED_VENCPLL 7 ++#define CLK_APMIXED_TVDPLL 8 ++#define CLK_APMIXED_MPLL 9 ++#define CLK_APMIXED_VCODECPLL 10 ++#define CLK_APMIXED_APLL1 11 ++#define CLK_APMIXED_APLL2 12 ++#define CLK_APMIXED_LVDSPLL 13 ++#define CLK_APMIXED_MSDCPLL2 14 ++#define CLK_APMIXED_NR_CLK 15 ++ ++/* INFRA_SYS */ ++ ++#define CLK_INFRA_DBGCLK 1 ++#define CLK_INFRA_SMI 2 ++#define CLK_INFRA_AUDIO 3 ++#define CLK_INFRA_GCE 4 ++#define CLK_INFRA_L2C_SRAM 5 ++#define CLK_INFRA_M4U 6 ++#define CLK_INFRA_CPUM 7 ++#define CLK_INFRA_KP 8 ++#define CLK_INFRA_CEC 9 ++#define CLK_INFRA_PMICSPI 10 ++#define CLK_INFRA_PMICWRAP 11 ++#define CLK_INFRA_NR_CLK 12 ++ ++/* PERI_SYS */ ++ ++#define CLK_PERI_NFI 1 ++#define CLK_PERI_THERM 2 ++#define CLK_PERI_PWM1 3 ++#define CLK_PERI_PWM2 4 ++#define CLK_PERI_PWM3 5 ++#define CLK_PERI_PWM4 6 ++#define CLK_PERI_PWM5 7 ++#define CLK_PERI_PWM6 8 ++#define CLK_PERI_PWM7 9 ++#define CLK_PERI_PWM 10 ++#define CLK_PERI_USB0 11 ++#define CLK_PERI_USB1 12 ++#define CLK_PERI_AP_DMA 13 ++#define CLK_PERI_MSDC30_0 14 ++#define CLK_PERI_MSDC30_1 15 ++#define CLK_PERI_MSDC30_2 16 ++#define CLK_PERI_MSDC30_3 17 ++#define CLK_PERI_NLI_ARB 18 ++#define CLK_PERI_IRDA 19 ++#define CLK_PERI_UART0 20 ++#define CLK_PERI_UART1 21 ++#define CLK_PERI_UART2 22 ++#define CLK_PERI_UART3 23 ++#define CLK_PERI_I2C0 24 ++#define CLK_PERI_I2C1 25 ++#define CLK_PERI_I2C2 26 ++#define CLK_PERI_I2C3 27 ++#define CLK_PERI_I2C4 28 ++#define CLK_PERI_AUXADC 29 ++#define CLK_PERI_SPI0 30 ++#define CLK_PERI_I2C5 31 ++#define CLK_PERI_NFIECC 32 ++#define CLK_PERI_SPI 33 ++#define CLK_PERI_IRRX 34 ++#define CLK_PERI_I2C6 35 ++#define CLK_PERI_UART0_SEL 36 ++#define CLK_PERI_UART1_SEL 37 ++#define CLK_PERI_UART2_SEL 38 ++#define CLK_PERI_UART3_SEL 39 ++#define CLK_PERI_NR_CLK 40 ++ ++#endif /* _DT_BINDINGS_CLK_MT8173_H */ +diff --git a/include/dt-bindings/reset-controller/mt8173-resets.h b/include/dt-bindings/reset-controller/mt8173-resets.h +new file mode 100644 +index 0000000..9464b37 +--- /dev/null ++++ b/include/dt-bindings/reset-controller/mt8173-resets.h +@@ -0,0 +1,63 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Flora Fu, MediaTek ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 ++#define _DT_BINDINGS_RESET_CONTROLLER_MT8173 ++ ++/* INFRACFG resets */ ++#define MT8173_INFRA_EMI_REG_RST 0 ++#define MT8173_INFRA_DRAMC0_A0_RST 1 ++#define MT8173_INFRA_APCIRQ_EINT_RST 3 ++#define MT8173_INFRA_APXGPT_RST 4 ++#define MT8173_INFRA_SCPSYS_RST 5 ++#define MT8173_INFRA_KP_RST 6 ++#define MT8173_INFRA_PMIC_WRAP_RST 7 ++#define MT8173_INFRA_MPIP_RST 8 ++#define MT8173_INFRA_CEC_RST 9 ++#define MT8173_INFRA_EMI_RST 32 ++#define MT8173_INFRA_DRAMC0_RST 34 ++#define MT8173_INFRA_APMIXEDSYS_RST 35 ++#define MT8173_INFRA_MIPI_DSI_RST 36 ++#define MT8173_INFRA_TRNG_RST 37 ++#define MT8173_INFRA_SYSIRQ_RST 38 ++#define MT8173_INFRA_MIPI_CSI_RST 39 ++#define MT8173_INFRA_GCE_FAXI_RST 40 ++#define MT8173_INFRA_MMIOMMURST 47 ++ ++ ++/* PERICFG resets */ ++#define MT8173_PERI_UART0_SW_RST 0 ++#define MT8173_PERI_UART1_SW_RST 1 ++#define MT8173_PERI_UART2_SW_RST 2 ++#define MT8173_PERI_UART3_SW_RST 3 ++#define MT8173_PERI_IRRX_SW_RST 4 ++#define MT8173_PERI_PWM_SW_RST 8 ++#define MT8173_PERI_AUXADC_SW_RST 10 ++#define MT8173_PERI_DMA_SW_RST 11 ++#define MT8173_PERI_I2C6_SW_RST 13 ++#define MT8173_PERI_NFI_SW_RST 14 ++#define MT8173_PERI_THERM_SW_RST 16 ++#define MT8173_PERI_MSDC2_SW_RST 17 ++#define MT8173_PERI_MSDC3_SW_RST 18 ++#define MT8173_PERI_MSDC0_SW_RST 19 ++#define MT8173_PERI_MSDC1_SW_RST 20 ++#define MT8173_PERI_I2C0_SW_RST 22 ++#define MT8173_PERI_I2C1_SW_RST 23 ++#define MT8173_PERI_I2C2_SW_RST 24 ++#define MT8173_PERI_I2C3_SW_RST 25 ++#define MT8173_PERI_I2C4_SW_RST 26 ++#define MT8173_PERI_HDMI_SW_RST 29 ++#define MT8173_PERI_SPI0_SW_RST 33 ++ ++#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0006-soc-mediatek-Add-infracfg-misc-driver-support.patch b/target/linux/mediatek/patches/0006-soc-mediatek-Add-infracfg-misc-driver-support.patch new file mode 100644 index 0000000..f47c193 --- /dev/null +++ b/target/linux/mediatek/patches/0006-soc-mediatek-Add-infracfg-misc-driver-support.patch @@ -0,0 +1,179 @@ +From d6d7a7dc1b7db2e3d496bf67b30abc894edbc4bd Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Tue, 9 Jun 2015 10:46:59 +0200 +Subject: [PATCH 06/76] soc: mediatek: Add infracfg misc driver support + +This adds support for some miscellaneous bits of the infracfg controller. +The mtk_infracfg_set/clear_bus_protection functions are necessary for +the scpsys power domain driver to handle the bus protection bits which +are contained in the infacfg register space. + +Signed-off-by: Sascha Hauer +--- + drivers/soc/mediatek/Kconfig | 9 ++++ + drivers/soc/mediatek/Makefile | 1 + + drivers/soc/mediatek/mtk-infracfg.c | 91 +++++++++++++++++++++++++++++++++ + include/linux/soc/mediatek/infracfg.h | 26 ++++++++++ + 4 files changed, 127 insertions(+) + create mode 100644 drivers/soc/mediatek/mtk-infracfg.c + create mode 100644 include/linux/soc/mediatek/infracfg.h + +diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig +index 3c18503..09da41e 100644 +--- a/drivers/soc/mediatek/Kconfig ++++ b/drivers/soc/mediatek/Kconfig +@@ -1,6 +1,15 @@ + # + # MediaTek SoC drivers + # ++config MTK_INFRACFG ++ bool "MediaTek INFRACFG Support" ++ depends on ARCH_MEDIATEK ++ select REGMAP ++ help ++ Say yes here to add support for the MediaTek INFRACFG controller. The ++ INFRACFG controller contains various infrastructure registers not ++ directly associated to any device. ++ + config MTK_PMIC_WRAP + tristate "MediaTek PMIC Wrapper Support" + depends on ARCH_MEDIATEK +diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile +index ecaf4de..3fa940f 100644 +--- a/drivers/soc/mediatek/Makefile ++++ b/drivers/soc/mediatek/Makefile +@@ -1 +1,2 @@ ++obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o + obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o +diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c +new file mode 100644 +index 0000000..ca786e0 +--- /dev/null ++++ b/drivers/soc/mediatek/mtk-infracfg.c +@@ -0,0 +1,91 @@ ++/* ++ * Copyright (c) 2015 Pengutronix, Sascha Hauer ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define INFRA_TOPAXI_PROTECTEN 0x0220 ++#define INFRA_TOPAXI_PROTECTSTA1 0x0228 ++ ++/** ++ * mtk_infracfg_set_bus_protection - enable bus protection ++ * @regmap: The infracfg regmap ++ * @mask: The mask containing the protection bits to be enabled. ++ * ++ * This function enables the bus protection bits for disabled power ++ * domains so that the system does not hanf when some unit accesses the ++ * bus while in power down. ++ */ ++int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask) ++{ ++ unsigned long expired; ++ u32 val; ++ int ret; ++ ++ regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask); ++ ++ expired = jiffies + HZ; ++ ++ while (1) { ++ ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val); ++ if (ret) ++ return ret; ++ ++ if ((val & mask) == mask) ++ break; ++ ++ cpu_relax(); ++ if (time_after(jiffies, expired)) ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++/** ++ * mtk_infracfg_clear_bus_protection - disable bus protection ++ * @regmap: The infracfg regmap ++ * @mask: The mask containing the protection bits to be disabled. ++ * ++ * This function disables the bus protection bits previously enabled with ++ * mtk_infracfg_set_bus_protection. ++ */ ++int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask) ++{ ++ unsigned long expired; ++ int ret; ++ ++ regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); ++ ++ expired = jiffies + HZ; ++ ++ while (1) { ++ u32 val; ++ ++ ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1, &val); ++ if (ret) ++ return ret; ++ ++ if (!(val & mask)) ++ break; ++ ++ cpu_relax(); ++ if (time_after(jiffies, expired)) ++ return -EIO; ++ } ++ ++ return 0; ++} +diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h +new file mode 100644 +index 0000000..a5714e9 +--- /dev/null ++++ b/include/linux/soc/mediatek/infracfg.h +@@ -0,0 +1,26 @@ ++#ifndef __SOC_MEDIATEK_INFRACFG_H ++#define __SOC_MEDIATEK_INFRACFG_H ++ ++#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) ++#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) ++#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) ++#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) ++#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) ++#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) ++#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) ++#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) ++#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) ++#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) ++#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) ++#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) ++#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) ++#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) ++#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) ++#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) ++#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) ++#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) ++ ++int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask); ++int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask); ++ ++#endif /* __SOC_MEDIATEK_INFRACFG_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0007-dt-bindings-soc-Add-documentation-for-the-MediaTek-S.patch b/target/linux/mediatek/patches/0007-dt-bindings-soc-Add-documentation-for-the-MediaTek-S.patch new file mode 100644 index 0000000..f7bdbd6 --- /dev/null +++ b/target/linux/mediatek/patches/0007-dt-bindings-soc-Add-documentation-for-the-MediaTek-S.patch @@ -0,0 +1,57 @@ +From 06a1fd8a198771abc7c5badcf43a49a715ba4c76 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Tue, 9 Jun 2015 10:47:00 +0200 +Subject: [PATCH 07/76] dt-bindings: soc: Add documentation for the MediaTek + SCPSYS unit + +This adds documentation for the MediaTek SCPSYS unit found in MT8173 SoCs. + +Signed-off-by: Sascha Hauer +--- + .../devicetree/bindings/soc/mediatek/scpsys.txt | 34 ++++++++++++++++++++ + 1 file changed, 34 insertions(+) + create mode 100644 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt + +diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +new file mode 100644 +index 0000000..87f2091 +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +@@ -0,0 +1,34 @@ ++MediaTek SCPSYS ++=============== ++ ++The System Control Processor System (SCPSYS) has several power management ++related tasks in the system. The tasks include thermal measurement, dynamic ++voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control. ++The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power ++domain control. ++ ++The driver implements the Generic PM domain bindings described in ++power/power_domain.txt. It provides the power domains defined in ++include/dt-bindings/power/mt8173-power.h. ++ ++Required properties: ++- compatible: Must be "mediatek,mt8173-scpsys" ++- #power-domain-cells: Must be 1 ++- reg: Address range of the SCPSYS unit ++- infracfg: must contain a phandle to the infracfg controller ++ ++Example: ++ ++ scpsys: scpsys@10006000 { ++ #power-domain-cells = <1>; ++ compatible = "mediatek,mt8173-scpsys"; ++ reg = <0 0x10006000 0 0x1000>; ++ infracfg = <&infracfg>; ++ }; ++ ++Example consumer: ++ ++ afe: mt8173-afe-pcm@11220000 { ++ compatible = "mediatek,mt8173-afe-pcm"; ++ power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; ++ }; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0008-soc-Mediatek-Add-SCPSYS-power-domain-driver.patch b/target/linux/mediatek/patches/0008-soc-Mediatek-Add-SCPSYS-power-domain-driver.patch new file mode 100644 index 0000000..bbf5ad1 --- /dev/null +++ b/target/linux/mediatek/patches/0008-soc-Mediatek-Add-SCPSYS-power-domain-driver.patch @@ -0,0 +1,573 @@ +From 04e2e2a895a95dc9e75403c2e8ea190dce9dc387 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Tue, 9 Jun 2015 10:47:01 +0200 +Subject: [PATCH 08/76] soc: Mediatek: Add SCPSYS power domain driver + +This adds a power domain driver for the Mediatek SCPSYS unit. + +The System Control Processor System (SCPSYS) has several power +management related tasks in the system. The tasks include thermal +measurement, dynamic voltage frequency scaling (DVFS), interrupt +filter and lowlevel sleep control. The System Power Manager (SPM) +inside the SCPSYS is for the MTCMOS power domain control. + +For now this driver only adds power domain support, the more +advanced features are not yet supported. The driver implements +the generic PM domain device tree bindings, the first user will +most likely be the Mediatek AFE audio driver. + +Signed-off-by: Sascha Hauer +--- + drivers/soc/mediatek/Kconfig | 9 + + drivers/soc/mediatek/Makefile | 1 + + drivers/soc/mediatek/mtk-scpsys.c | 490 ++++++++++++++++++++++++++++++ + include/dt-bindings/power/mt8173-power.h | 15 + + 4 files changed, 515 insertions(+) + create mode 100644 drivers/soc/mediatek/mtk-scpsys.c + create mode 100644 include/dt-bindings/power/mt8173-power.h + +diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig +index 09da41e..2dc5d90 100644 +--- a/drivers/soc/mediatek/Kconfig ++++ b/drivers/soc/mediatek/Kconfig +@@ -19,3 +19,12 @@ config MTK_PMIC_WRAP + Say yes here to add support for MediaTek PMIC Wrapper found + on different MediaTek SoCs. The PMIC wrapper is a proprietary + hardware to connect the PMIC. ++ ++config MTK_SCPSYS ++ bool "MediaTek SCPSYS Support" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select REGMAP ++ select MTK_INFRACFG ++ help ++ Say yes here to add support for the MediaTek SCPSYS power domain ++ driver. +diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile +index 3fa940f..12998b0 100644 +--- a/drivers/soc/mediatek/Makefile ++++ b/drivers/soc/mediatek/Makefile +@@ -1,2 +1,3 @@ + obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o + obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o ++obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o +diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c +new file mode 100644 +index 0000000..b9eed37 +--- /dev/null ++++ b/drivers/soc/mediatek/mtk-scpsys.c +@@ -0,0 +1,490 @@ ++/* ++ * Copyright (c) 2015 Pengutronix, Sascha Hauer ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SPM_VDE_PWR_CON 0x0210 ++#define SPM_MFG_PWR_CON 0x0214 ++#define SPM_VEN_PWR_CON 0x0230 ++#define SPM_ISP_PWR_CON 0x0238 ++#define SPM_DIS_PWR_CON 0x023c ++#define SPM_VEN2_PWR_CON 0x0298 ++#define SPM_AUDIO_PWR_CON 0x029c ++#define SPM_MFG_2D_PWR_CON 0x02c0 ++#define SPM_MFG_ASYNC_PWR_CON 0x02c4 ++#define SPM_USB_PWR_CON 0x02cc ++#define SPM_PWR_STATUS 0x060c ++#define SPM_PWR_STATUS_2ND 0x0610 ++ ++#define PWR_RST_B_BIT BIT(0) ++#define PWR_ISO_BIT BIT(1) ++#define PWR_ON_BIT BIT(2) ++#define PWR_ON_2ND_BIT BIT(3) ++#define PWR_CLK_DIS_BIT BIT(4) ++ ++#define PWR_STATUS_DISP BIT(3) ++#define PWR_STATUS_MFG BIT(4) ++#define PWR_STATUS_ISP BIT(5) ++#define PWR_STATUS_VDEC BIT(7) ++#define PWR_STATUS_VENC_LT BIT(20) ++#define PWR_STATUS_VENC BIT(21) ++#define PWR_STATUS_MFG_2D BIT(22) ++#define PWR_STATUS_MFG_ASYNC BIT(23) ++#define PWR_STATUS_AUDIO BIT(24) ++#define PWR_STATUS_USB BIT(25) ++ ++enum clk_id { ++ MT8173_CLK_NONE, ++ MT8173_CLK_MM, ++ MT8173_CLK_MFG, ++ MT8173_CLK_MAX = MT8173_CLK_MFG, ++}; ++ ++struct scp_domain_data { ++ const char *name; ++ u32 sta_mask; ++ int ctl_offs; ++ u32 sram_pdn_bits; ++ u32 sram_pdn_ack_bits; ++ u32 bus_prot_mask; ++ enum clk_id clk_id; ++}; ++ ++static const struct scp_domain_data scp_domain_data[] __initconst = { ++ [MT8173_POWER_DOMAIN_VDEC] = { ++ .name = "vdec", ++ .sta_mask = PWR_STATUS_VDEC, ++ .ctl_offs = SPM_VDE_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = GENMASK(12, 12), ++ .clk_id = MT8173_CLK_MM, ++ }, ++ [MT8173_POWER_DOMAIN_VENC] = { ++ .name = "venc", ++ .sta_mask = PWR_STATUS_VENC, ++ .ctl_offs = SPM_VEN_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = GENMASK(15, 12), ++ .clk_id = MT8173_CLK_MM, ++ }, ++ [MT8173_POWER_DOMAIN_ISP] = { ++ .name = "isp", ++ .sta_mask = PWR_STATUS_ISP, ++ .ctl_offs = SPM_ISP_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = GENMASK(13, 12), ++ .clk_id = MT8173_CLK_MM, ++ }, ++ [MT8173_POWER_DOMAIN_MM] = { ++ .name = "mm", ++ .sta_mask = PWR_STATUS_DISP, ++ .ctl_offs = SPM_DIS_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = GENMASK(12, 12), ++ .clk_id = MT8173_CLK_MM, ++ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | ++ MT8173_TOP_AXI_PROT_EN_MM_M1, ++ }, ++ [MT8173_POWER_DOMAIN_VENC_LT] = { ++ .name = "venc_lt", ++ .sta_mask = PWR_STATUS_VENC_LT, ++ .ctl_offs = SPM_VEN2_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = GENMASK(15, 12), ++ .clk_id = MT8173_CLK_MM, ++ }, ++ [MT8173_POWER_DOMAIN_AUDIO] = { ++ .name = "audio", ++ .sta_mask = PWR_STATUS_AUDIO, ++ .ctl_offs = SPM_AUDIO_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = GENMASK(15, 12), ++ .clk_id = MT8173_CLK_NONE, ++ }, ++ [MT8173_POWER_DOMAIN_USB] = { ++ .name = "usb", ++ .sta_mask = PWR_STATUS_USB, ++ .ctl_offs = SPM_USB_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = GENMASK(15, 12), ++ .clk_id = MT8173_CLK_NONE, ++ }, ++ [MT8173_POWER_DOMAIN_MFG_ASYNC] = { ++ .name = "mfg_async", ++ .sta_mask = PWR_STATUS_MFG_ASYNC, ++ .ctl_offs = SPM_MFG_ASYNC_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = 0, ++ .clk_id = MT8173_CLK_MFG, ++ }, ++ [MT8173_POWER_DOMAIN_MFG_2D] = { ++ .name = "mfg_2d", ++ .sta_mask = PWR_STATUS_MFG_2D, ++ .ctl_offs = SPM_MFG_2D_PWR_CON, ++ .sram_pdn_bits = GENMASK(11, 8), ++ .sram_pdn_ack_bits = GENMASK(13, 12), ++ .clk_id = MT8173_CLK_NONE, ++ }, ++ [MT8173_POWER_DOMAIN_MFG] = { ++ .name = "mfg", ++ .sta_mask = PWR_STATUS_MFG, ++ .ctl_offs = SPM_MFG_PWR_CON, ++ .sram_pdn_bits = GENMASK(13, 8), ++ .sram_pdn_ack_bits = GENMASK(21, 16), ++ .clk_id = MT8173_CLK_NONE, ++ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | ++ MT8173_TOP_AXI_PROT_EN_MFG_M0 | ++ MT8173_TOP_AXI_PROT_EN_MFG_M1 | ++ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT, ++ }, ++}; ++ ++#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data) ++ ++struct scp; ++ ++struct scp_domain { ++ struct generic_pm_domain genpd; ++ struct scp *scp; ++ struct clk *clk; ++ u32 sta_mask; ++ void __iomem *ctl_addr; ++ u32 sram_pdn_bits; ++ u32 sram_pdn_ack_bits; ++ u32 bus_prot_mask; ++}; ++ ++struct scp { ++ struct scp_domain domains[NUM_DOMAINS]; ++ struct genpd_onecell_data pd_data; ++ struct device *dev; ++ void __iomem *base; ++ struct regmap *infracfg; ++ struct clk *clk[MT8173_CLK_MAX]; ++}; ++ ++static int scpsys_domain_is_on(struct scp_domain *scpd) ++{ ++ struct scp *scp = scpd->scp; ++ ++ u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->sta_mask; ++ u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) & scpd->sta_mask; ++ ++ /* ++ * A domain is on when both status bits are set. If only one is set ++ * return an error. This happens while powering up a domain ++ */ ++ ++ if (status && status2) ++ return true; ++ if (!status && !status2) ++ return false; ++ ++ return -EINVAL; ++} ++ ++static int scpsys_power_on(struct generic_pm_domain *genpd) ++{ ++ struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd); ++ struct scp *scp = scpd->scp; ++ unsigned long timeout; ++ bool expired; ++ void __iomem *ctl_addr = scpd->ctl_addr; ++ u32 sram_pdn_ack = scpd->sram_pdn_ack_bits; ++ u32 val; ++ int ret; ++ ++ if (scpd->clk) { ++ ret = clk_prepare_enable(scpd->clk); ++ if (ret) ++ return ret; ++ } ++ ++ val = readl(ctl_addr); ++ val |= PWR_ON_BIT; ++ writel(val, ctl_addr); ++ val |= PWR_ON_2ND_BIT; ++ writel(val, ctl_addr); ++ ++ /* wait until PWR_ACK = 1 */ ++ timeout = jiffies + HZ; ++ expired = false; ++ while (1) { ++ ret = scpsys_domain_is_on(scpd); ++ if (ret > 0) ++ break; ++ ++ if (expired) { ++ ret = -ETIMEDOUT; ++ goto out; ++ } ++ ++ cpu_relax(); ++ ++ if (time_after(jiffies, timeout)) ++ expired = true; ++ } ++ ++ val &= ~PWR_CLK_DIS_BIT; ++ writel(val, ctl_addr); ++ ++ val &= ~PWR_ISO_BIT; ++ writel(val, ctl_addr); ++ ++ val |= PWR_RST_B_BIT; ++ writel(val, ctl_addr); ++ ++ val &= ~scpd->sram_pdn_bits; ++ writel(val, ctl_addr); ++ ++ /* wait until SRAM_PDN_ACK all 0 */ ++ timeout = jiffies + HZ; ++ expired = false; ++ while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) { ++ ++ if (expired) { ++ ret = -ETIMEDOUT; ++ goto out; ++ } ++ ++ cpu_relax(); ++ ++ if (time_after(jiffies, timeout)) ++ expired = true; ++ } ++ ++ if (scpd->bus_prot_mask) { ++ ret = mtk_infracfg_clear_bus_protection(scp->infracfg, ++ scpd->bus_prot_mask); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++out: ++ dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name); ++ ++ return ret; ++} ++ ++static int scpsys_power_off(struct generic_pm_domain *genpd) ++{ ++ struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd); ++ struct scp *scp = scpd->scp; ++ unsigned long timeout; ++ bool expired; ++ void __iomem *ctl_addr = scpd->ctl_addr; ++ u32 pdn_ack = scpd->sram_pdn_ack_bits; ++ u32 val; ++ int ret; ++ ++ if (scpd->bus_prot_mask) { ++ ret = mtk_infracfg_set_bus_protection(scp->infracfg, ++ scpd->bus_prot_mask); ++ if (ret) ++ return ret; ++ } ++ ++ val = readl(ctl_addr); ++ val |= scpd->sram_pdn_bits; ++ writel(val, ctl_addr); ++ ++ /* wait until SRAM_PDN_ACK all 1 */ ++ timeout = jiffies + HZ; ++ expired = false; ++ while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) { ++ if (expired) { ++ ret = -ETIMEDOUT; ++ goto out; ++ } ++ ++ cpu_relax(); ++ ++ if (time_after(jiffies, timeout)) ++ expired = true; ++ } ++ ++ val |= PWR_ISO_BIT; ++ writel(val, ctl_addr); ++ ++ val &= ~PWR_RST_B_BIT; ++ writel(val, ctl_addr); ++ ++ val |= PWR_CLK_DIS_BIT; ++ writel(val, ctl_addr); ++ ++ val &= ~PWR_ON_BIT; ++ writel(val, ctl_addr); ++ ++ val &= ~PWR_ON_2ND_BIT; ++ writel(val, ctl_addr); ++ ++ /* wait until PWR_ACK = 0 */ ++ timeout = jiffies + HZ; ++ expired = false; ++ while (1) { ++ ret = scpsys_domain_is_on(scpd); ++ if (ret == 0) ++ break; ++ ++ if (expired) { ++ ret = -ETIMEDOUT; ++ goto out; ++ } ++ ++ cpu_relax(); ++ ++ if (time_after(jiffies, timeout)) ++ expired = true; ++ } ++ ++ if (scpd->clk) ++ clk_disable_unprepare(scpd->clk); ++ ++ return 0; ++ ++out: ++ dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name); ++ ++ return ret; ++} ++ ++static int __init scpsys_probe(struct platform_device *pdev) ++{ ++ struct genpd_onecell_data *pd_data; ++ struct resource *res; ++ int i, ret; ++ struct scp *scp; ++ ++ scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL); ++ if (!scp) ++ return -ENOMEM; ++ ++ scp->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ scp->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(scp->base)) ++ return PTR_ERR(scp->base); ++ ++ pd_data = &scp->pd_data; ++ ++ pd_data->domains = devm_kzalloc(&pdev->dev, ++ sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL); ++ if (!pd_data->domains) ++ return -ENOMEM; ++ ++ scp->clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm"); ++ if (IS_ERR(scp->clk[MT8173_CLK_MM])) { ++ dev_err(&pdev->dev, "Failed to get mm clk: %ld\n", ++ PTR_ERR(scp->clk[MT8173_CLK_MM])); ++ return PTR_ERR(scp->clk[MT8173_CLK_MM]); ++ } ++ ++ scp->clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg"); ++ if (IS_ERR(scp->clk[MT8173_CLK_MFG])) { ++ dev_err(&pdev->dev, "Failed to get mfg clk: %ld\n", ++ PTR_ERR(scp->clk[MT8173_CLK_MFG])); ++ return PTR_ERR(scp->clk[MT8173_CLK_MFG]); ++ } ++ ++ scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, ++ "infracfg"); ++ if (IS_ERR(scp->infracfg)) { ++ dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n", ++ PTR_ERR(scp->infracfg)); ++ return PTR_ERR(scp->infracfg); ++ } ++ ++ pd_data->num_domains = NUM_DOMAINS; ++ ++ for (i = 0; i < NUM_DOMAINS; i++) { ++ struct scp_domain *scpd = &scp->domains[i]; ++ struct generic_pm_domain *genpd = &scpd->genpd; ++ const struct scp_domain_data *data = &scp_domain_data[i]; ++ ++ pd_data->domains[i] = genpd; ++ scpd->scp = scp; ++ ++ scpd->sta_mask = data->sta_mask; ++ scpd->ctl_addr = scp->base + data->ctl_offs; ++ scpd->sram_pdn_bits = data->sram_pdn_bits; ++ scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits; ++ scpd->bus_prot_mask = data->bus_prot_mask; ++ if (data->clk_id != MT8173_CLK_NONE) ++ scpd->clk = scp->clk[data->clk_id]; ++ ++ genpd->name = data->name; ++ genpd->power_off = scpsys_power_off; ++ genpd->power_on = scpsys_power_on; ++ ++ /* ++ * Initially turn on all domains to make the domains usable ++ * with !CONFIG_PM and to get the hardware in sync with the ++ * software. The unused domains will be switched off during ++ * late_init time. ++ */ ++ genpd->power_on(genpd); ++ ++ pm_genpd_init(genpd, NULL, false); ++ } ++ ++ /* ++ * We are not allowed to fail here since there is no way to unregister ++ * a power domain. Once registered above we have to keep the domains ++ * valid. ++ */ ++ ++ ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC], ++ pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]); ++ if (ret && IS_ENABLED(CONFIG_PM)) ++ dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); ++ ++ ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D], ++ pd_data->domains[MT8173_POWER_DOMAIN_MFG]); ++ if (ret && IS_ENABLED(CONFIG_PM)) ++ dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); ++ ++ ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data); ++ if (ret) ++ dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret); ++ ++ return 0; ++} ++ ++static const struct of_device_id of_scpsys_match_tbl[] = { ++ { ++ .compatible = "mediatek,mt8173-scpsys", ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static struct platform_driver scpsys_drv = { ++ .driver = { ++ .name = "mtk-scpsys", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(of_scpsys_match_tbl), ++ }, ++}; ++ ++module_platform_driver_probe(scpsys_drv, scpsys_probe); +diff --git a/include/dt-bindings/power/mt8173-power.h b/include/dt-bindings/power/mt8173-power.h +new file mode 100644 +index 0000000..b34cee9 +--- /dev/null ++++ b/include/dt-bindings/power/mt8173-power.h +@@ -0,0 +1,15 @@ ++#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H ++#define _DT_BINDINGS_POWER_MT8183_POWER_H ++ ++#define MT8173_POWER_DOMAIN_VDEC 0 ++#define MT8173_POWER_DOMAIN_VENC 1 ++#define MT8173_POWER_DOMAIN_ISP 2 ++#define MT8173_POWER_DOMAIN_MM 3 ++#define MT8173_POWER_DOMAIN_VENC_LT 4 ++#define MT8173_POWER_DOMAIN_AUDIO 5 ++#define MT8173_POWER_DOMAIN_USB 6 ++#define MT8173_POWER_DOMAIN_MFG_ASYNC 7 ++#define MT8173_POWER_DOMAIN_MFG_2D 8 ++#define MT8173_POWER_DOMAIN_MFG 9 ++ ++#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0009-dt-bindings-ARM-Mediatek-Document-devicetree-binding.patch b/target/linux/mediatek/patches/0009-dt-bindings-ARM-Mediatek-Document-devicetree-binding.patch new file mode 100644 index 0000000..6d7fd47 --- /dev/null +++ b/target/linux/mediatek/patches/0009-dt-bindings-ARM-Mediatek-Document-devicetree-binding.patch @@ -0,0 +1,154 @@ +From 87043a64dd5185dc076b3c3ab2e421b3a8c47798 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Thu, 23 Apr 2015 10:35:43 +0200 +Subject: [PATCH 09/76] dt-bindings: ARM: Mediatek: Document devicetree + bindings for clock/reset controllers + +This adds the binding documentation for the apmixedsys, perisys and +infracfg controllers found on Mediatek SoCs. + +Signed-off-by: Sascha Hauer +--- + .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 23 +++++++++++++++ + .../bindings/arm/mediatek/mediatek,infracfg.txt | 30 ++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,pericfg.txt | 30 ++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,topckgen.txt | 23 +++++++++++++++ + 4 files changed, 106 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt + +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +new file mode 100644 +index 0000000..5af6d73 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +@@ -0,0 +1,23 @@ ++Mediatek apmixedsys controller ++============================== ++ ++The Mediatek apmixedsys controller provides the PLLs to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt8135-apmixedsys" ++ - "mediatek,mt8173-apmixedsys" ++- #clock-cells: Must be 1 ++ ++The apmixedsys controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++apmixedsys: apmixedsys@10209000 { ++ compatible = "mediatek,mt8173-apmixedsys"; ++ reg = <0 0x10209000 0 0x1000>; ++ #clock-cells = <1>; ++}; +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +new file mode 100644 +index 0000000..684da473 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +@@ -0,0 +1,30 @@ ++Mediatek infracfg controller ++============================ ++ ++The Mediatek infracfg controller provides various clocks and reset ++outputs to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt8135-infracfg", "syscon" ++ - "mediatek,mt8173-infracfg", "syscon" ++- #clock-cells: Must be 1 ++- #reset-cells: Must be 1 ++ ++The infracfg controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++Also it uses the common reset controller binding from ++Documentation/devicetree/bindings/reset/reset.txt. ++The available reset outputs are defined in ++dt-bindings/reset-controller/mt*-resets.h ++ ++Example: ++ ++infracfg: infracfg@10001000 { ++ compatible = "mediatek,mt8173-infracfg", "syscon"; ++ reg = <0 0x10001000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++}; +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +new file mode 100644 +index 0000000..fdb45c6 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +@@ -0,0 +1,30 @@ ++Mediatek pericfg controller ++=========================== ++ ++The Mediatek pericfg controller provides various clocks and reset ++outputs to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt8135-pericfg", "syscon" ++ - "mediatek,mt8173-pericfg", "syscon" ++- #clock-cells: Must be 1 ++- #reset-cells: Must be 1 ++ ++The pericfg controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++Also it uses the common reset controller binding from ++Documentation/devicetree/bindings/reset/reset.txt. ++The available reset outputs are defined in ++dt-bindings/reset-controller/mt*-resets.h ++ ++Example: ++ ++pericfg: pericfg@10003000 { ++ compatible = "mediatek,mt8173-pericfg", "syscon"; ++ reg = <0 0x10003000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++}; +diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +new file mode 100644 +index 0000000..a425248 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +@@ -0,0 +1,23 @@ ++Mediatek topckgen controller ++============================ ++ ++The Mediatek topckgen controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt8135-topckgen" ++ - "mediatek,mt8173-topckgen" ++- #clock-cells: Must be 1 ++ ++The topckgen controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++topckgen: topckgen@10000000 { ++ compatible = "mediatek,mt8173-topckgen"; ++ reg = <0 0x10000000 0 0x1000>; ++ #clock-cells = <1>; ++}; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0010-thermal-consistently-use-int-for-temperatures.patch b/target/linux/mediatek/patches/0010-thermal-consistently-use-int-for-temperatures.patch new file mode 100644 index 0000000..2aa83ab --- /dev/null +++ b/target/linux/mediatek/patches/0010-thermal-consistently-use-int-for-temperatures.patch @@ -0,0 +1,1155 @@ +From 29e6031548373b9e7ec0c17e85da6a4cf4fee7f5 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:29 +0200 +Subject: [PATCH 10/76] thermal: consistently use int for temperatures + +The thermal code uses int, long and unsigned long for temperatures +in different places. Using an unsigned type limits the thermal framework +to positive temperatures without need. 'long' is 64bit on several +architectures which is not needed. Consistently use a plain 'int' +for temperatures. + +Signed-off-by: Sascha Hauer +--- + drivers/acpi/thermal.c | 12 ++++----- + drivers/hwmon/lm75.c | 2 +- + drivers/hwmon/ntc_thermistor.c | 2 +- + drivers/hwmon/tmp102.c | 2 +- + drivers/input/touchscreen/sun4i-ts.c | 8 +++--- + drivers/platform/x86/acerhdf.c | 9 +++---- + drivers/power/power_supply_core.c | 2 +- + drivers/thermal/armada_thermal.c | 2 +- + drivers/thermal/db8500_thermal.c | 7 +++-- + drivers/thermal/dove_thermal.c | 2 +- + drivers/thermal/fair_share.c | 2 +- + drivers/thermal/gov_bang_bang.c | 5 ++-- + drivers/thermal/imx_thermal.c | 27 ++++++++++---------- + .../thermal/int340x_thermal/int340x_thermal_zone.c | 10 ++++---- + .../thermal/int340x_thermal/int340x_thermal_zone.h | 8 +++--- + drivers/thermal/intel_soc_dts_thermal.c | 7 +++-- + drivers/thermal/of-thermal.c | 14 +++++----- + drivers/thermal/rcar_thermal.c | 7 +++-- + drivers/thermal/rockchip_thermal.c | 10 ++++---- + drivers/thermal/samsung/exynos_tmu.c | 19 +++++++------- + drivers/thermal/spear_thermal.c | 2 +- + drivers/thermal/st/st_thermal.c | 5 ++-- + drivers/thermal/step_wise.c | 4 +-- + drivers/thermal/tegra_soctherm.c | 4 +-- + drivers/thermal/thermal_core.c | 26 +++++++++---------- + drivers/thermal/thermal_hwmon.c | 10 ++++---- + drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 10 ++++---- + drivers/thermal/x86_pkg_temp_thermal.c | 10 ++++---- + include/linux/thermal.h | 26 ++++++++----------- + 29 files changed, 120 insertions(+), 134 deletions(-) + +diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c +index d24fa19..68bff60 100644 +--- a/drivers/acpi/thermal.c ++++ b/drivers/acpi/thermal.c +@@ -529,8 +529,7 @@ static void acpi_thermal_check(void *data) + + /* sys I/F for generic thermal sysfs support */ + +-static int thermal_get_temp(struct thermal_zone_device *thermal, +- unsigned long *temp) ++static int thermal_get_temp(struct thermal_zone_device *thermal, int *temp) + { + struct acpi_thermal *tz = thermal->devdata; + int result; +@@ -637,7 +636,7 @@ static int thermal_get_trip_type(struct thermal_zone_device *thermal, + } + + static int thermal_get_trip_temp(struct thermal_zone_device *thermal, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + struct acpi_thermal *tz = thermal->devdata; + int i; +@@ -690,7 +689,8 @@ static int thermal_get_trip_temp(struct thermal_zone_device *thermal, + } + + static int thermal_get_crit_temp(struct thermal_zone_device *thermal, +- unsigned long *temperature) { ++ int *temperature) ++{ + struct acpi_thermal *tz = thermal->devdata; + + if (tz->trips.critical.flags.valid) { +@@ -713,8 +713,8 @@ static int thermal_get_trend(struct thermal_zone_device *thermal, + return -EINVAL; + + if (type == THERMAL_TRIP_ACTIVE) { +- unsigned long trip_temp; +- unsigned long temp = DECI_KELVIN_TO_MILLICELSIUS_WITH_OFFSET( ++ int trip_temp; ++ int temp = DECI_KELVIN_TO_MILLICELSIUS_WITH_OFFSET( + tz->temperature, tz->kelvin_offset); + if (thermal_get_trip_temp(thermal, trip, &trip_temp)) + return -EINVAL; +diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c +index fe41d5a..e4e57bb 100644 +--- a/drivers/hwmon/lm75.c ++++ b/drivers/hwmon/lm75.c +@@ -104,7 +104,7 @@ static inline long lm75_reg_to_mc(s16 temp, u8 resolution) + + /* sysfs attributes for hwmon */ + +-static int lm75_read_temp(void *dev, long *temp) ++static int lm75_read_temp(void *dev, int *temp) + { + struct lm75_data *data = lm75_update_device(dev); + +diff --git a/drivers/hwmon/ntc_thermistor.c b/drivers/hwmon/ntc_thermistor.c +index 6880011..3d9eab9 100644 +--- a/drivers/hwmon/ntc_thermistor.c ++++ b/drivers/hwmon/ntc_thermistor.c +@@ -439,7 +439,7 @@ static int ntc_thermistor_get_ohm(struct ntc_data *data) + return -EINVAL; + } + +-static int ntc_read_temp(void *dev, long *temp) ++static int ntc_read_temp(void *dev, int *temp) + { + struct ntc_data *data = dev_get_drvdata(dev); + int ohm; +diff --git a/drivers/hwmon/tmp102.c b/drivers/hwmon/tmp102.c +index 9da2735..6548262 100644 +--- a/drivers/hwmon/tmp102.c ++++ b/drivers/hwmon/tmp102.c +@@ -98,7 +98,7 @@ static struct tmp102 *tmp102_update_device(struct device *dev) + return tmp102; + } + +-static int tmp102_read_temp(void *dev, long *temp) ++static int tmp102_read_temp(void *dev, int *temp) + { + struct tmp102 *tmp102 = tmp102_update_device(dev); + +diff --git a/drivers/input/touchscreen/sun4i-ts.c b/drivers/input/touchscreen/sun4i-ts.c +index c011699..4857943 100644 +--- a/drivers/input/touchscreen/sun4i-ts.c ++++ b/drivers/input/touchscreen/sun4i-ts.c +@@ -191,7 +191,7 @@ static void sun4i_ts_close(struct input_dev *dev) + writel(TEMP_IRQ_EN(1), ts->base + TP_INT_FIFOC); + } + +-static int sun4i_get_temp(const struct sun4i_ts_data *ts, long *temp) ++static int sun4i_get_temp(const struct sun4i_ts_data *ts, int *temp) + { + /* No temp_data until the first irq */ + if (ts->temp_data == -1) +@@ -202,7 +202,7 @@ static int sun4i_get_temp(const struct sun4i_ts_data *ts, long *temp) + return 0; + } + +-static int sun4i_get_tz_temp(void *data, long *temp) ++static int sun4i_get_tz_temp(void *data, int *temp) + { + return sun4i_get_temp(data, temp); + } +@@ -215,14 +215,14 @@ static ssize_t show_temp(struct device *dev, struct device_attribute *devattr, + char *buf) + { + struct sun4i_ts_data *ts = dev_get_drvdata(dev); +- long temp; ++ int temp; + int error; + + error = sun4i_get_temp(ts, &temp); + if (error) + return error; + +- return sprintf(buf, "%ld\n", temp); ++ return sprintf(buf, "%d\n", temp); + } + + static ssize_t show_temp_label(struct device *dev, +diff --git a/drivers/platform/x86/acerhdf.c b/drivers/platform/x86/acerhdf.c +index 594c918..f2ce63c 100644 +--- a/drivers/platform/x86/acerhdf.c ++++ b/drivers/platform/x86/acerhdf.c +@@ -346,8 +346,7 @@ static void acerhdf_check_param(struct thermal_zone_device *thermal) + * as late as the polling interval is since we can't do that in the respective + * accessors of the module parameters. + */ +-static int acerhdf_get_ec_temp(struct thermal_zone_device *thermal, +- unsigned long *t) ++static int acerhdf_get_ec_temp(struct thermal_zone_device *thermal, int *t) + { + int temp, err = 0; + +@@ -452,7 +451,7 @@ static int acerhdf_get_trip_type(struct thermal_zone_device *thermal, int trip, + } + + static int acerhdf_get_trip_hyst(struct thermal_zone_device *thermal, int trip, +- unsigned long *temp) ++ int *temp) + { + if (trip != 0) + return -EINVAL; +@@ -463,7 +462,7 @@ static int acerhdf_get_trip_hyst(struct thermal_zone_device *thermal, int trip, + } + + static int acerhdf_get_trip_temp(struct thermal_zone_device *thermal, int trip, +- unsigned long *temp) ++ int *temp) + { + if (trip == 0) + *temp = fanon; +@@ -476,7 +475,7 @@ static int acerhdf_get_trip_temp(struct thermal_zone_device *thermal, int trip, + } + + static int acerhdf_get_crit_temp(struct thermal_zone_device *thermal, +- unsigned long *temperature) ++ int *temperature) + { + *temperature = ACERHDF_TEMP_CRIT; + return 0; +diff --git a/drivers/power/power_supply_core.c b/drivers/power/power_supply_core.c +index 2ed4a4a..87e2fd1 100644 +--- a/drivers/power/power_supply_core.c ++++ b/drivers/power/power_supply_core.c +@@ -492,7 +492,7 @@ EXPORT_SYMBOL_GPL(power_supply_unreg_notifier); + + #ifdef CONFIG_THERMAL + static int power_supply_read_temp(struct thermal_zone_device *tzd, +- unsigned long *temp) ++ int *temp) + { + struct power_supply *psy; + union power_supply_propval val; +diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c +index 01255fd..26b8d32 100644 +--- a/drivers/thermal/armada_thermal.c ++++ b/drivers/thermal/armada_thermal.c +@@ -155,7 +155,7 @@ static bool armada_is_valid(struct armada_thermal_priv *priv) + } + + static int armada_get_temp(struct thermal_zone_device *thermal, +- unsigned long *temp) ++ int *temp) + { + struct armada_thermal_priv *priv = thermal->devdata; + unsigned long reg; +diff --git a/drivers/thermal/db8500_thermal.c b/drivers/thermal/db8500_thermal.c +index 20adfbe..b3eca71 100644 +--- a/drivers/thermal/db8500_thermal.c ++++ b/drivers/thermal/db8500_thermal.c +@@ -107,8 +107,7 @@ static int db8500_cdev_unbind(struct thermal_zone_device *thermal, + } + + /* Callback to get current temperature */ +-static int db8500_sys_get_temp(struct thermal_zone_device *thermal, +- unsigned long *temp) ++static int db8500_sys_get_temp(struct thermal_zone_device *thermal, int *temp) + { + struct db8500_thermal_zone *pzone = thermal->devdata; + +@@ -180,7 +179,7 @@ static int db8500_sys_get_trip_type(struct thermal_zone_device *thermal, + + /* Callback to get trip point temperature */ + static int db8500_sys_get_trip_temp(struct thermal_zone_device *thermal, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + struct db8500_thermal_zone *pzone = thermal->devdata; + struct db8500_thsens_platform_data *ptrips = pzone->trip_tab; +@@ -195,7 +194,7 @@ static int db8500_sys_get_trip_temp(struct thermal_zone_device *thermal, + + /* Callback to get critical trip point temperature */ + static int db8500_sys_get_crit_temp(struct thermal_zone_device *thermal, +- unsigned long *temp) ++ int *temp) + { + struct db8500_thermal_zone *pzone = thermal->devdata; + struct db8500_thsens_platform_data *ptrips = pzone->trip_tab; +diff --git a/drivers/thermal/dove_thermal.c b/drivers/thermal/dove_thermal.c +index 09f6e30..a0bc9de 100644 +--- a/drivers/thermal/dove_thermal.c ++++ b/drivers/thermal/dove_thermal.c +@@ -93,7 +93,7 @@ static int dove_init_sensor(const struct dove_thermal_priv *priv) + } + + static int dove_get_temp(struct thermal_zone_device *thermal, +- unsigned long *temp) ++ int *temp) + { + unsigned long reg; + struct dove_thermal_priv *priv = thermal->devdata; +diff --git a/drivers/thermal/fair_share.c b/drivers/thermal/fair_share.c +index 6e0a3fb..efad70e 100644 +--- a/drivers/thermal/fair_share.c ++++ b/drivers/thermal/fair_share.c +@@ -34,7 +34,7 @@ + static int get_trip_level(struct thermal_zone_device *tz) + { + int count = 0; +- unsigned long trip_temp; ++ int trip_temp; + enum thermal_trip_type trip_type; + + if (tz->trips == 0 || !tz->ops->get_trip_temp) +diff --git a/drivers/thermal/gov_bang_bang.c b/drivers/thermal/gov_bang_bang.c +index c5dd76b..70836c5 100644 +--- a/drivers/thermal/gov_bang_bang.c ++++ b/drivers/thermal/gov_bang_bang.c +@@ -25,14 +25,13 @@ + + static void thermal_zone_trip_update(struct thermal_zone_device *tz, int trip) + { +- long trip_temp; +- unsigned long trip_hyst; ++ int trip_temp, trip_hyst; + struct thermal_instance *instance; + + tz->ops->get_trip_temp(tz, trip, &trip_temp); + tz->ops->get_trip_hyst(tz, trip, &trip_hyst); + +- dev_dbg(&tz->device, "Trip%d[temp=%ld]:temp=%d:hyst=%ld\n", ++ dev_dbg(&tz->device, "Trip%d[temp=%d]:temp=%d:hyst=%d\n", + trip, trip_temp, tz->temperature, + trip_hyst); + +diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c +index 2ccbc07..f1424f0 100644 +--- a/drivers/thermal/imx_thermal.c ++++ b/drivers/thermal/imx_thermal.c +@@ -98,10 +98,10 @@ struct imx_thermal_data { + enum thermal_device_mode mode; + struct regmap *tempmon; + u32 c1, c2; /* See formula in imx_get_sensor_data() */ +- unsigned long temp_passive; +- unsigned long temp_critical; +- unsigned long alarm_temp; +- unsigned long last_temp; ++ int temp_passive; ++ int temp_critical; ++ int alarm_temp; ++ int last_temp; + bool irq_enabled; + int irq; + struct clk *thermal_clk; +@@ -109,7 +109,7 @@ struct imx_thermal_data { + }; + + static void imx_set_panic_temp(struct imx_thermal_data *data, +- signed long panic_temp) ++ int panic_temp) + { + struct regmap *map = data->tempmon; + int critical_value; +@@ -121,7 +121,7 @@ static void imx_set_panic_temp(struct imx_thermal_data *data, + } + + static void imx_set_alarm_temp(struct imx_thermal_data *data, +- signed long alarm_temp) ++ int alarm_temp) + { + struct regmap *map = data->tempmon; + int alarm_value; +@@ -133,7 +133,7 @@ static void imx_set_alarm_temp(struct imx_thermal_data *data, + TEMPSENSE0_ALARM_VALUE_SHIFT); + } + +-static int imx_get_temp(struct thermal_zone_device *tz, unsigned long *temp) ++static int imx_get_temp(struct thermal_zone_device *tz, int *temp) + { + struct imx_thermal_data *data = tz->devdata; + struct regmap *map = data->tempmon; +@@ -189,13 +189,13 @@ static int imx_get_temp(struct thermal_zone_device *tz, unsigned long *temp) + if (data->alarm_temp == data->temp_critical && + *temp < data->temp_passive) { + imx_set_alarm_temp(data, data->temp_passive); +- dev_dbg(&tz->device, "thermal alarm off: T < %lu\n", ++ dev_dbg(&tz->device, "thermal alarm off: T < %d\n", + data->alarm_temp / 1000); + } + } + + if (*temp != data->last_temp) { +- dev_dbg(&tz->device, "millicelsius: %ld\n", *temp); ++ dev_dbg(&tz->device, "millicelsius: %d\n", *temp); + data->last_temp = *temp; + } + +@@ -262,8 +262,7 @@ static int imx_get_trip_type(struct thermal_zone_device *tz, int trip, + return 0; + } + +-static int imx_get_crit_temp(struct thermal_zone_device *tz, +- unsigned long *temp) ++static int imx_get_crit_temp(struct thermal_zone_device *tz, int *temp) + { + struct imx_thermal_data *data = tz->devdata; + +@@ -272,7 +271,7 @@ static int imx_get_crit_temp(struct thermal_zone_device *tz, + } + + static int imx_get_trip_temp(struct thermal_zone_device *tz, int trip, +- unsigned long *temp) ++ int *temp) + { + struct imx_thermal_data *data = tz->devdata; + +@@ -282,7 +281,7 @@ static int imx_get_trip_temp(struct thermal_zone_device *tz, int trip, + } + + static int imx_set_trip_temp(struct thermal_zone_device *tz, int trip, +- unsigned long temp) ++ int temp) + { + struct imx_thermal_data *data = tz->devdata; + +@@ -433,7 +432,7 @@ static irqreturn_t imx_thermal_alarm_irq_thread(int irq, void *dev) + { + struct imx_thermal_data *data = dev; + +- dev_dbg(&data->tz->device, "THERMAL ALARM: T > %lu\n", ++ dev_dbg(&data->tz->device, "THERMAL ALARM: T > %d\n", + data->alarm_temp / 1000); + + thermal_zone_device_update(data->tz); +diff --git a/drivers/thermal/int340x_thermal/int340x_thermal_zone.c b/drivers/thermal/int340x_thermal/int340x_thermal_zone.c +index 1e25133..b9b2666 100644 +--- a/drivers/thermal/int340x_thermal/int340x_thermal_zone.c ++++ b/drivers/thermal/int340x_thermal/int340x_thermal_zone.c +@@ -20,7 +20,7 @@ + #include "int340x_thermal_zone.h" + + static int int340x_thermal_get_zone_temp(struct thermal_zone_device *zone, +- unsigned long *temp) ++ int *temp) + { + struct int34x_thermal_zone *d = zone->devdata; + unsigned long long tmp; +@@ -49,7 +49,7 @@ static int int340x_thermal_get_zone_temp(struct thermal_zone_device *zone, + } + + static int int340x_thermal_get_trip_temp(struct thermal_zone_device *zone, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + struct int34x_thermal_zone *d = zone->devdata; + int i; +@@ -114,7 +114,7 @@ static int int340x_thermal_get_trip_type(struct thermal_zone_device *zone, + } + + static int int340x_thermal_set_trip_temp(struct thermal_zone_device *zone, +- int trip, unsigned long temp) ++ int trip, int temp) + { + struct int34x_thermal_zone *d = zone->devdata; + acpi_status status; +@@ -136,7 +136,7 @@ static int int340x_thermal_set_trip_temp(struct thermal_zone_device *zone, + + + static int int340x_thermal_get_trip_hyst(struct thermal_zone_device *zone, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + struct int34x_thermal_zone *d = zone->devdata; + acpi_status status; +@@ -163,7 +163,7 @@ static struct thermal_zone_device_ops int340x_thermal_zone_ops = { + }; + + static int int340x_thermal_get_trip_config(acpi_handle handle, char *name, +- unsigned long *temp) ++ int *temp) + { + unsigned long long r; + acpi_status status; +diff --git a/drivers/thermal/int340x_thermal/int340x_thermal_zone.h b/drivers/thermal/int340x_thermal/int340x_thermal_zone.h +index 9f38ab7..aaadf72 100644 +--- a/drivers/thermal/int340x_thermal/int340x_thermal_zone.h ++++ b/drivers/thermal/int340x_thermal/int340x_thermal_zone.h +@@ -21,7 +21,7 @@ + #define INT340X_THERMAL_MAX_ACT_TRIP_COUNT 10 + + struct active_trip { +- unsigned long temp; ++ int temp; + int id; + bool valid; + }; +@@ -31,11 +31,11 @@ struct int34x_thermal_zone { + struct active_trip act_trips[INT340X_THERMAL_MAX_ACT_TRIP_COUNT]; + unsigned long *aux_trips; + int aux_trip_nr; +- unsigned long psv_temp; ++ int psv_temp; + int psv_trip_id; +- unsigned long crt_temp; ++ int crt_temp; + int crt_trip_id; +- unsigned long hot_temp; ++ int hot_temp; + int hot_trip_id; + struct thermal_zone_device *zone; + struct thermal_zone_device_ops *override_ops; +diff --git a/drivers/thermal/intel_soc_dts_thermal.c b/drivers/thermal/intel_soc_dts_thermal.c +index 9013505..fd550b9 100644 +--- a/drivers/thermal/intel_soc_dts_thermal.c ++++ b/drivers/thermal/intel_soc_dts_thermal.c +@@ -106,7 +106,7 @@ err_ret: + } + + static int sys_get_trip_temp(struct thermal_zone_device *tzd, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + int status; + u32 out; +@@ -224,7 +224,7 @@ err_restore_ptps: + } + + static int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip, +- unsigned long temp) ++ int temp) + { + struct soc_sensor_entry *aux_entry = tzd->devdata; + int status; +@@ -250,8 +250,7 @@ static int sys_get_trip_type(struct thermal_zone_device *thermal, + return 0; + } + +-static int sys_get_curr_temp(struct thermal_zone_device *tzd, +- unsigned long *temp) ++static int sys_get_curr_temp(struct thermal_zone_device *tzd, int *temp) + { + int status; + u32 out; +diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c +index 668fb1b..03839df 100644 +--- a/drivers/thermal/of-thermal.c ++++ b/drivers/thermal/of-thermal.c +@@ -87,7 +87,7 @@ struct __thermal_zone { + /*** DT thermal zone device callbacks ***/ + + static int of_thermal_get_temp(struct thermal_zone_device *tz, +- unsigned long *temp) ++ int *temp) + { + struct __thermal_zone *data = tz->devdata; + +@@ -173,7 +173,7 @@ EXPORT_SYMBOL_GPL(of_thermal_get_trip_points); + * Return: zero on success, error code otherwise + */ + static int of_thermal_set_emul_temp(struct thermal_zone_device *tz, +- unsigned long temp) ++ int temp) + { + struct __thermal_zone *data = tz->devdata; + +@@ -306,7 +306,7 @@ static int of_thermal_get_trip_type(struct thermal_zone_device *tz, int trip, + } + + static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip, +- unsigned long *temp) ++ int *temp) + { + struct __thermal_zone *data = tz->devdata; + +@@ -319,7 +319,7 @@ static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip, + } + + static int of_thermal_set_trip_temp(struct thermal_zone_device *tz, int trip, +- unsigned long temp) ++ int temp) + { + struct __thermal_zone *data = tz->devdata; + +@@ -333,7 +333,7 @@ static int of_thermal_set_trip_temp(struct thermal_zone_device *tz, int trip, + } + + static int of_thermal_get_trip_hyst(struct thermal_zone_device *tz, int trip, +- unsigned long *hyst) ++ int *hyst) + { + struct __thermal_zone *data = tz->devdata; + +@@ -346,7 +346,7 @@ static int of_thermal_get_trip_hyst(struct thermal_zone_device *tz, int trip, + } + + static int of_thermal_set_trip_hyst(struct thermal_zone_device *tz, int trip, +- unsigned long hyst) ++ int hyst) + { + struct __thermal_zone *data = tz->devdata; + +@@ -360,7 +360,7 @@ static int of_thermal_set_trip_hyst(struct thermal_zone_device *tz, int trip, + } + + static int of_thermal_get_crit_temp(struct thermal_zone_device *tz, +- unsigned long *temp) ++ int *temp) + { + struct __thermal_zone *data = tz->devdata; + int i; +diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c +index fe4e767..5d4ae7d 100644 +--- a/drivers/thermal/rcar_thermal.c ++++ b/drivers/thermal/rcar_thermal.c +@@ -200,8 +200,7 @@ err_out_unlock: + return ret; + } + +-static int rcar_thermal_get_temp(struct thermal_zone_device *zone, +- unsigned long *temp) ++static int rcar_thermal_get_temp(struct thermal_zone_device *zone, int *temp) + { + struct rcar_thermal_priv *priv = rcar_zone_to_priv(zone); + +@@ -235,7 +234,7 @@ static int rcar_thermal_get_trip_type(struct thermal_zone_device *zone, + } + + static int rcar_thermal_get_trip_temp(struct thermal_zone_device *zone, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + struct rcar_thermal_priv *priv = rcar_zone_to_priv(zone); + struct device *dev = rcar_priv_to_dev(priv); +@@ -299,7 +298,7 @@ static void _rcar_thermal_irq_ctrl(struct rcar_thermal_priv *priv, int enable) + static void rcar_thermal_work(struct work_struct *work) + { + struct rcar_thermal_priv *priv; +- unsigned long cctemp, nctemp; ++ int cctemp, nctemp; + + priv = container_of(work, struct rcar_thermal_priv, work.work); + +diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c +index cd8f5f93..c89ffb2 100644 +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -64,7 +64,7 @@ struct rockchip_tsadc_chip { + void (*control)(void __iomem *reg, bool on); + + /* Per-sensor methods */ +- int (*get_temp)(int chn, void __iomem *reg, long *temp); ++ int (*get_temp)(int chn, void __iomem *reg, int *temp); + void (*set_tshut_temp)(int chn, void __iomem *reg, long temp); + void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); + }; +@@ -191,7 +191,7 @@ static u32 rk_tsadcv2_temp_to_code(long temp) + return 0; + } + +-static long rk_tsadcv2_code_to_temp(u32 code) ++static int rk_tsadcv2_code_to_temp(u32 code) + { + unsigned int low = 0; + unsigned int high = ARRAY_SIZE(v2_code_table) - 1; +@@ -277,7 +277,7 @@ static void rk_tsadcv2_control(void __iomem *regs, bool enable) + writel_relaxed(val, regs + TSADCV2_AUTO_CON); + } + +-static int rk_tsadcv2_get_temp(int chn, void __iomem *regs, long *temp) ++static int rk_tsadcv2_get_temp(int chn, void __iomem *regs, int *temp) + { + u32 val; + +@@ -366,7 +366,7 @@ static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) + return IRQ_HANDLED; + } + +-static int rockchip_thermal_get_temp(void *_sensor, long *out_temp) ++static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) + { + struct rockchip_thermal_sensor *sensor = _sensor; + struct rockchip_thermal_data *thermal = sensor->thermal; +@@ -374,7 +374,7 @@ static int rockchip_thermal_get_temp(void *_sensor, long *out_temp) + int retval; + + retval = tsadc->get_temp(sensor->id, thermal->regs, out_temp); +- dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %ld, retval: %d\n", ++ dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", + sensor->id, *out_temp, retval); + + return retval; +diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c +index 1d30b09..29eaf4d 100644 +--- a/drivers/thermal/samsung/exynos_tmu.c ++++ b/drivers/thermal/samsung/exynos_tmu.c +@@ -181,8 +181,7 @@ struct exynos_tmu_data { + int (*tmu_initialize)(struct platform_device *pdev); + void (*tmu_control)(struct platform_device *pdev, bool on); + int (*tmu_read)(struct exynos_tmu_data *data); +- void (*tmu_set_emulation)(struct exynos_tmu_data *data, +- unsigned long temp); ++ void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); + void (*tmu_clear_irqs)(struct exynos_tmu_data *data); + }; + +@@ -190,7 +189,7 @@ static void exynos_report_trigger(struct exynos_tmu_data *p) + { + char data[10], *envp[] = { data, NULL }; + struct thermal_zone_device *tz = p->tzd; +- unsigned long temp; ++ int temp; + unsigned int i; + + if (!tz) { +@@ -489,7 +488,7 @@ static int exynos5440_tmu_initialize(struct platform_device *pdev) + struct exynos_tmu_data *data = platform_get_drvdata(pdev); + unsigned int trim_info = 0, con, rising_threshold; + int ret = 0, threshold_code; +- unsigned long crit_temp = 0; ++ int crit_temp = 0; + + /* + * For exynos5440 soc triminfo value is swapped between TMU0 and +@@ -542,7 +541,7 @@ static int exynos7_tmu_initialize(struct platform_device *pdev) + unsigned int status, trim_info; + unsigned int rising_threshold = 0, falling_threshold = 0; + int ret = 0, threshold_code, i; +- unsigned long temp, temp_hist; ++ int temp, temp_hist; + unsigned int reg_off, bit_off; + + status = readb(data->base + EXYNOS_TMU_REG_STATUS); +@@ -713,7 +712,7 @@ static void exynos7_tmu_control(struct platform_device *pdev, bool on) + writel(con, data->base + EXYNOS_TMU_REG_CONTROL); + } + +-static int exynos_get_temp(void *p, long *temp) ++static int exynos_get_temp(void *p, int *temp) + { + struct exynos_tmu_data *data = p; + +@@ -733,7 +732,7 @@ static int exynos_get_temp(void *p, long *temp) + + #ifdef CONFIG_THERMAL_EMULATION + static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, +- unsigned long temp) ++ int temp) + { + if (temp) { + temp /= MCELSIUS; +@@ -763,7 +762,7 @@ static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, + } + + static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, +- unsigned long temp) ++ int temp) + { + unsigned int val; + u32 emul_con; +@@ -781,7 +780,7 @@ static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, + } + + static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data, +- unsigned long temp) ++ int temp) + { + unsigned int val; + +@@ -790,7 +789,7 @@ static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data, + writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG); + } + +-static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) ++static int exynos_tmu_set_emulation(void *drv_data, int temp) + { + struct exynos_tmu_data *data = drv_data; + int ret = -EINVAL; +diff --git a/drivers/thermal/spear_thermal.c b/drivers/thermal/spear_thermal.c +index bddb717..534dd91 100644 +--- a/drivers/thermal/spear_thermal.c ++++ b/drivers/thermal/spear_thermal.c +@@ -38,7 +38,7 @@ struct spear_thermal_dev { + }; + + static inline int thermal_get_temp(struct thermal_zone_device *thermal, +- unsigned long *temp) ++ int *temp) + { + struct spear_thermal_dev *stdev = thermal->devdata; + +diff --git a/drivers/thermal/st/st_thermal.c b/drivers/thermal/st/st_thermal.c +index 76c515d..44cbba9 100644 +--- a/drivers/thermal/st/st_thermal.c ++++ b/drivers/thermal/st/st_thermal.c +@@ -111,8 +111,7 @@ static int st_thermal_calibration(struct st_thermal_sensor *sensor) + } + + /* Callback to get temperature from HW*/ +-static int st_thermal_get_temp(struct thermal_zone_device *th, +- unsigned long *temperature) ++static int st_thermal_get_temp(struct thermal_zone_device *th, int *temperature) + { + struct st_thermal_sensor *sensor = th->devdata; + struct device *dev = sensor->dev; +@@ -159,7 +158,7 @@ static int st_thermal_get_trip_type(struct thermal_zone_device *th, + } + + static int st_thermal_get_trip_temp(struct thermal_zone_device *th, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + struct st_thermal_sensor *sensor = th->devdata; + struct device *dev = sensor->dev; +diff --git a/drivers/thermal/step_wise.c b/drivers/thermal/step_wise.c +index 5a0f12d..2f9f708 100644 +--- a/drivers/thermal/step_wise.c ++++ b/drivers/thermal/step_wise.c +@@ -113,7 +113,7 @@ static void update_passive_instance(struct thermal_zone_device *tz, + + static void thermal_zone_trip_update(struct thermal_zone_device *tz, int trip) + { +- long trip_temp; ++ int trip_temp; + enum thermal_trip_type trip_type; + enum thermal_trend trend; + struct thermal_instance *instance; +@@ -135,7 +135,7 @@ static void thermal_zone_trip_update(struct thermal_zone_device *tz, int trip) + trace_thermal_zone_trip(tz, trip, trip_type); + } + +- dev_dbg(&tz->device, "Trip%d[type=%d,temp=%ld]:trend=%d,throttle=%d\n", ++ dev_dbg(&tz->device, "Trip%d[type=%d,temp=%d]:trend=%d,throttle=%d\n", + trip, trip_type, trip_temp, trend, throttle); + + mutex_lock(&tz->lock); +diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra_soctherm.c +index 9197fc0..74ea576 100644 +--- a/drivers/thermal/tegra_soctherm.c ++++ b/drivers/thermal/tegra_soctherm.c +@@ -293,7 +293,7 @@ static int enable_tsensor(struct tegra_soctherm *tegra, + * H denotes an addition of 0.5 Celsius and N denotes negation + * of the final value. + */ +-static long translate_temp(u16 val) ++static int translate_temp(u16 val) + { + long t; + +@@ -306,7 +306,7 @@ static long translate_temp(u16 val) + return t; + } + +-static int tegra_thermctl_get_temp(void *data, long *out_temp) ++static int tegra_thermctl_get_temp(void *data, int *out_temp) + { + struct tegra_thermctl_zone *zone = data; + u32 val; +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index 4108db7..62cc82a 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -363,7 +363,7 @@ static void handle_non_critical_trips(struct thermal_zone_device *tz, + static void handle_critical_trips(struct thermal_zone_device *tz, + int trip, enum thermal_trip_type trip_type) + { +- long trip_temp; ++ int trip_temp; + + tz->ops->get_trip_temp(tz, trip, &trip_temp); + +@@ -411,12 +411,12 @@ static void handle_thermal_trip(struct thermal_zone_device *tz, int trip) + * + * Return: On success returns 0, an error code otherwise + */ +-int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp) ++int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp) + { + int ret = -EINVAL; + #ifdef CONFIG_THERMAL_EMULATION + int count; +- unsigned long crit_temp = -1UL; ++ int crit_temp = INT_MAX; + enum thermal_trip_type type; + #endif + +@@ -453,8 +453,7 @@ EXPORT_SYMBOL_GPL(thermal_zone_get_temp); + + static void update_temperature(struct thermal_zone_device *tz) + { +- long temp; +- int ret; ++ int temp, ret; + + ret = thermal_zone_get_temp(tz, &temp); + if (ret) { +@@ -514,15 +513,14 @@ static ssize_t + temp_show(struct device *dev, struct device_attribute *attr, char *buf) + { + struct thermal_zone_device *tz = to_thermal_zone(dev); +- long temperature; +- int ret; ++ int temperature, ret; + + ret = thermal_zone_get_temp(tz, &temperature); + + if (ret) + return ret; + +- return sprintf(buf, "%ld\n", temperature); ++ return sprintf(buf, "%d\n", temperature); + } + + static ssize_t +@@ -626,7 +624,7 @@ trip_point_temp_show(struct device *dev, struct device_attribute *attr, + { + struct thermal_zone_device *tz = to_thermal_zone(dev); + int trip, ret; +- long temperature; ++ int temperature; + + if (!tz->ops->get_trip_temp) + return -EPERM; +@@ -639,7 +637,7 @@ trip_point_temp_show(struct device *dev, struct device_attribute *attr, + if (ret) + return ret; + +- return sprintf(buf, "%ld\n", temperature); ++ return sprintf(buf, "%d\n", temperature); + } + + static ssize_t +@@ -648,7 +646,7 @@ trip_point_hyst_store(struct device *dev, struct device_attribute *attr, + { + struct thermal_zone_device *tz = to_thermal_zone(dev); + int trip, ret; +- unsigned long temperature; ++ int temperature; + + if (!tz->ops->set_trip_hyst) + return -EPERM; +@@ -656,7 +654,7 @@ trip_point_hyst_store(struct device *dev, struct device_attribute *attr, + if (!sscanf(attr->attr.name, "trip_point_%d_hyst", &trip)) + return -EINVAL; + +- if (kstrtoul(buf, 10, &temperature)) ++ if (kstrtoint(buf, 10, &temperature)) + return -EINVAL; + + /* +@@ -675,7 +673,7 @@ trip_point_hyst_show(struct device *dev, struct device_attribute *attr, + { + struct thermal_zone_device *tz = to_thermal_zone(dev); + int trip, ret; +- unsigned long temperature; ++ int temperature; + + if (!tz->ops->get_trip_hyst) + return -EPERM; +@@ -685,7 +683,7 @@ trip_point_hyst_show(struct device *dev, struct device_attribute *attr, + + ret = tz->ops->get_trip_hyst(tz, trip, &temperature); + +- return ret ? ret : sprintf(buf, "%ld\n", temperature); ++ return ret ? ret : sprintf(buf, "%d\n", temperature); + } + + static ssize_t +diff --git a/drivers/thermal/thermal_hwmon.c b/drivers/thermal/thermal_hwmon.c +index 1967bee..06fd2ed9 100644 +--- a/drivers/thermal/thermal_hwmon.c ++++ b/drivers/thermal/thermal_hwmon.c +@@ -69,7 +69,7 @@ static DEVICE_ATTR(name, 0444, name_show, NULL); + static ssize_t + temp_input_show(struct device *dev, struct device_attribute *attr, char *buf) + { +- long temperature; ++ int temperature; + int ret; + struct thermal_hwmon_attr *hwmon_attr + = container_of(attr, struct thermal_hwmon_attr, attr); +@@ -83,7 +83,7 @@ temp_input_show(struct device *dev, struct device_attribute *attr, char *buf) + if (ret) + return ret; + +- return sprintf(buf, "%ld\n", temperature); ++ return sprintf(buf, "%d\n", temperature); + } + + static ssize_t +@@ -95,14 +95,14 @@ temp_crit_show(struct device *dev, struct device_attribute *attr, char *buf) + = container_of(hwmon_attr, struct thermal_hwmon_temp, + temp_crit); + struct thermal_zone_device *tz = temp->tz; +- long temperature; ++ int temperature; + int ret; + + ret = tz->ops->get_trip_temp(tz, 0, &temperature); + if (ret) + return ret; + +- return sprintf(buf, "%ld\n", temperature); ++ return sprintf(buf, "%d\n", temperature); + } + + +@@ -142,7 +142,7 @@ thermal_hwmon_lookup_temp(const struct thermal_hwmon_device *hwmon, + + static bool thermal_zone_crit_temp_valid(struct thermal_zone_device *tz) + { +- unsigned long temp; ++ int temp; + return tz->ops->get_crit_temp && !tz->ops->get_crit_temp(tz, &temp); + } + +diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +index a38c175..d3a42bf 100644 +--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c ++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +@@ -76,14 +76,14 @@ static inline int ti_thermal_hotspot_temperature(int t, int s, int c) + + /* thermal zone ops */ + /* Get temperature callback function for thermal zone*/ +-static inline int __ti_thermal_get_temp(void *devdata, long *temp) ++static inline int __ti_thermal_get_temp(void *devdata, int *temp) + { + struct thermal_zone_device *pcb_tz = NULL; + struct ti_thermal_data *data = devdata; + struct ti_bandgap *bgp; + const struct ti_temp_sensor *s; + int ret, tmp, slope, constant; +- unsigned long pcb_temp; ++ int pcb_temp; + + if (!data) + return 0; +@@ -119,7 +119,7 @@ static inline int __ti_thermal_get_temp(void *devdata, long *temp) + } + + static inline int ti_thermal_get_temp(struct thermal_zone_device *thermal, +- unsigned long *temp) ++ int *temp) + { + struct ti_thermal_data *data = thermal->devdata; + +@@ -228,7 +228,7 @@ static int ti_thermal_get_trip_type(struct thermal_zone_device *thermal, + + /* Get trip temperature callback functions for thermal zone */ + static int ti_thermal_get_trip_temp(struct thermal_zone_device *thermal, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + if (!ti_thermal_is_valid_trip(trip)) + return -EINVAL; +@@ -279,7 +279,7 @@ static int ti_thermal_get_trend(struct thermal_zone_device *thermal, + + /* Get critical temperature callback functions for thermal zone */ + static int ti_thermal_get_crit_temp(struct thermal_zone_device *thermal, +- unsigned long *temp) ++ int *temp) + { + /* shutdown zone */ + return ti_thermal_get_trip_temp(thermal, OMAP_TRIP_NUMBER - 1, temp); +diff --git a/drivers/thermal/x86_pkg_temp_thermal.c b/drivers/thermal/x86_pkg_temp_thermal.c +index 9ea3d9d..054c6d45 100644 +--- a/drivers/thermal/x86_pkg_temp_thermal.c ++++ b/drivers/thermal/x86_pkg_temp_thermal.c +@@ -164,7 +164,7 @@ err_ret: + return err; + } + +-static int sys_get_curr_temp(struct thermal_zone_device *tzd, unsigned long *temp) ++static int sys_get_curr_temp(struct thermal_zone_device *tzd, int *temp) + { + u32 eax, edx; + struct phy_dev_entry *phy_dev_entry; +@@ -175,7 +175,7 @@ static int sys_get_curr_temp(struct thermal_zone_device *tzd, unsigned long *tem + if (eax & 0x80000000) { + *temp = phy_dev_entry->tj_max - + ((eax >> 16) & 0x7f) * 1000; +- pr_debug("sys_get_curr_temp %ld\n", *temp); ++ pr_debug("sys_get_curr_temp %d\n", *temp); + return 0; + } + +@@ -183,7 +183,7 @@ static int sys_get_curr_temp(struct thermal_zone_device *tzd, unsigned long *tem + } + + static int sys_get_trip_temp(struct thermal_zone_device *tzd, +- int trip, unsigned long *temp) ++ int trip, int *temp) + { + u32 eax, edx; + struct phy_dev_entry *phy_dev_entry; +@@ -214,13 +214,13 @@ static int sys_get_trip_temp(struct thermal_zone_device *tzd, + *temp = phy_dev_entry->tj_max - thres_reg_value * 1000; + else + *temp = 0; +- pr_debug("sys_get_trip_temp %ld\n", *temp); ++ pr_debug("sys_get_trip_temp %d\n", *temp); + + return 0; + } + + static int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip, +- unsigned long temp) ++ int temp) + { + u32 l, h; + struct phy_dev_entry *phy_dev_entry; +diff --git a/include/linux/thermal.h b/include/linux/thermal.h +index 5eac316..e9f2863 100644 +--- a/include/linux/thermal.h ++++ b/include/linux/thermal.h +@@ -86,23 +86,19 @@ struct thermal_zone_device_ops { + struct thermal_cooling_device *); + int (*unbind) (struct thermal_zone_device *, + struct thermal_cooling_device *); +- int (*get_temp) (struct thermal_zone_device *, unsigned long *); ++ int (*get_temp) (struct thermal_zone_device *, int *); + int (*get_mode) (struct thermal_zone_device *, + enum thermal_device_mode *); + int (*set_mode) (struct thermal_zone_device *, + enum thermal_device_mode); + int (*get_trip_type) (struct thermal_zone_device *, int, + enum thermal_trip_type *); +- int (*get_trip_temp) (struct thermal_zone_device *, int, +- unsigned long *); +- int (*set_trip_temp) (struct thermal_zone_device *, int, +- unsigned long); +- int (*get_trip_hyst) (struct thermal_zone_device *, int, +- unsigned long *); +- int (*set_trip_hyst) (struct thermal_zone_device *, int, +- unsigned long); +- int (*get_crit_temp) (struct thermal_zone_device *, unsigned long *); +- int (*set_emul_temp) (struct thermal_zone_device *, unsigned long); ++ int (*get_trip_temp) (struct thermal_zone_device *, int, int *); ++ int (*set_trip_temp) (struct thermal_zone_device *, int, int); ++ int (*get_trip_hyst) (struct thermal_zone_device *, int, int *); ++ int (*set_trip_hyst) (struct thermal_zone_device *, int, int); ++ int (*get_crit_temp) (struct thermal_zone_device *, int *); ++ int (*set_emul_temp) (struct thermal_zone_device *, int); + int (*get_trend) (struct thermal_zone_device *, int, + enum thermal_trend *); + int (*notify) (struct thermal_zone_device *, int, +@@ -272,9 +268,9 @@ struct thermal_genl_event { + * temperature. + */ + struct thermal_zone_of_device_ops { +- int (*get_temp)(void *, long *); ++ int (*get_temp)(void *, int *); + int (*get_trend)(void *, long *); +- int (*set_emul_temp)(void *, unsigned long); ++ int (*set_emul_temp)(void *, int); + }; + + /** +@@ -335,7 +331,7 @@ thermal_of_cooling_device_register(struct device_node *np, char *, void *, + const struct thermal_cooling_device_ops *); + void thermal_cooling_device_unregister(struct thermal_cooling_device *); + struct thermal_zone_device *thermal_zone_get_zone_by_name(const char *name); +-int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp); ++int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp); + + int get_tz_trend(struct thermal_zone_device *, int); + struct thermal_instance *get_thermal_instance(struct thermal_zone_device *, +@@ -378,7 +374,7 @@ static inline struct thermal_zone_device *thermal_zone_get_zone_by_name( + const char *name) + { return ERR_PTR(-ENODEV); } + static inline int thermal_zone_get_temp( +- struct thermal_zone_device *tz, unsigned long *temp) ++ struct thermal_zone_device *tz, int *temp) + { return -ENODEV; } + static inline int get_tz_trend(struct thermal_zone_device *tz, int trip) + { return -ENODEV; } +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0011-thermal-trivial-fix-typo-in-comment.patch b/target/linux/mediatek/patches/0011-thermal-trivial-fix-typo-in-comment.patch new file mode 100644 index 0000000..4b9e0f9 --- /dev/null +++ b/target/linux/mediatek/patches/0011-thermal-trivial-fix-typo-in-comment.patch @@ -0,0 +1,27 @@ +From a2214b951a1102ad2a2a72b6ae6e71c148f8249f Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:30 +0200 +Subject: [PATCH 11/76] thermal: trivial: fix typo in comment + +Signed-off-by: Sascha Hauer +Acked-by: Eduardo Valentin +--- + drivers/thermal/thermal_core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index 62cc82a..244784f 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -402,7 +402,7 @@ static void handle_thermal_trip(struct thermal_zone_device *tz, int trip) + } + + /** +- * thermal_zone_get_temp() - returns its the temperature of thermal zone ++ * thermal_zone_get_temp() - returns the temperature of a thermal zone + * @tz: a valid pointer to a struct thermal_zone_device + * @temp: a valid pointer to where to store the resulting temperature. + * +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0012-thermal-remove-useless-call-to-thermal_zone_device_s.patch b/target/linux/mediatek/patches/0012-thermal-remove-useless-call-to-thermal_zone_device_s.patch new file mode 100644 index 0000000..2d64f49 --- /dev/null +++ b/target/linux/mediatek/patches/0012-thermal-remove-useless-call-to-thermal_zone_device_s.patch @@ -0,0 +1,34 @@ +From 41adcc8cf217dfb4b70c2da061e70034b3c9add0 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:31 +0200 +Subject: [PATCH 12/76] thermal: remove useless call to + thermal_zone_device_set_polling + +When the thermal zone has no get_temp callback then thermal_zone_device_register() +calls thermal_zone_device_set_polling() with a polling delay of 0. This +only cancels the poll_queue. Since the poll_queue hasn't been scheduled this +is a no-op. Remove it. + +Signed-off-by: Sascha Hauer +Acked-by: Eduardo Valentin +--- + drivers/thermal/thermal_core.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index 244784f..1b68d20 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -1571,9 +1571,6 @@ struct thermal_zone_device *thermal_zone_device_register(const char *type, + + INIT_DELAYED_WORK(&(tz->poll_queue), thermal_zone_device_check); + +- if (!tz->ops->get_temp) +- thermal_zone_device_set_polling(tz, 0); +- + thermal_zone_device_update(tz); + + return tz; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0013-thermal-Use-IS_ENABLED-instead-of-ifdef.patch b/target/linux/mediatek/patches/0013-thermal-Use-IS_ENABLED-instead-of-ifdef.patch new file mode 100644 index 0000000..0b033d6 --- /dev/null +++ b/target/linux/mediatek/patches/0013-thermal-Use-IS_ENABLED-instead-of-ifdef.patch @@ -0,0 +1,106 @@ +From bddcae2b66a23bfb6d381d089b0b862235480a9b Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:32 +0200 +Subject: [PATCH 13/76] thermal: Use IS_ENABLED instead of #ifdef + +Use IS_ENABLED(CONFIG_THERMAL_EMULATION) to make the code more readable +and to get rid of the addtional #ifdef around the variable definitions +in thermal_zone_get_temp(). + +Signed-off-by: Sascha Hauer +--- + drivers/thermal/thermal_core.c | 45 +++++++++++++++++----------------------- + 1 file changed, 19 insertions(+), 26 deletions(-) + +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index 1b68d20..3e0fe55 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -414,11 +414,9 @@ static void handle_thermal_trip(struct thermal_zone_device *tz, int trip) + int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp) + { + int ret = -EINVAL; +-#ifdef CONFIG_THERMAL_EMULATION + int count; + int crit_temp = INT_MAX; + enum thermal_trip_type type; +-#endif + + if (!tz || IS_ERR(tz) || !tz->ops->get_temp) + goto exit; +@@ -426,25 +424,21 @@ int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp) + mutex_lock(&tz->lock); + + ret = tz->ops->get_temp(tz, temp); +-#ifdef CONFIG_THERMAL_EMULATION +- if (!tz->emul_temperature) +- goto skip_emul; +- +- for (count = 0; count < tz->trips; count++) { +- ret = tz->ops->get_trip_type(tz, count, &type); +- if (!ret && type == THERMAL_TRIP_CRITICAL) { +- ret = tz->ops->get_trip_temp(tz, count, &crit_temp); +- break; +- } +- } + +- if (ret) +- goto skip_emul; ++ if (IS_ENABLED(CONFIG_THERMAL_EMULATION) && tz->emul_temperature) { ++ for (count = 0; count < tz->trips; count++) { ++ ret = tz->ops->get_trip_type(tz, count, &type); ++ if (!ret && type == THERMAL_TRIP_CRITICAL) { ++ ret = tz->ops->get_trip_temp(tz, count, ++ &crit_temp); ++ break; ++ } ++ } + +- if (*temp < crit_temp) +- *temp = tz->emul_temperature; +-skip_emul: +-#endif ++ if (!ret && *temp < crit_temp) ++ *temp = tz->emul_temperature; ++ } ++ + mutex_unlock(&tz->lock); + exit: + return ret; +@@ -780,7 +774,6 @@ policy_show(struct device *dev, struct device_attribute *devattr, char *buf) + return sprintf(buf, "%s\n", tz->governor->name); + } + +-#ifdef CONFIG_THERMAL_EMULATION + static ssize_t + emul_temp_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +@@ -806,7 +799,6 @@ emul_temp_store(struct device *dev, struct device_attribute *attr, + return ret ? ret : count; + } + static DEVICE_ATTR(emul_temp, S_IWUSR, NULL, emul_temp_store); +-#endif/*CONFIG_THERMAL_EMULATION*/ + + static DEVICE_ATTR(type, 0444, type_show, NULL); + static DEVICE_ATTR(temp, 0444, temp_show, NULL); +@@ -1536,11 +1528,12 @@ struct thermal_zone_device *thermal_zone_device_register(const char *type, + goto unregister; + } + +-#ifdef CONFIG_THERMAL_EMULATION +- result = device_create_file(&tz->device, &dev_attr_emul_temp); +- if (result) +- goto unregister; +-#endif ++ if (IS_ENABLED(CONFIG_THERMAL_EMULATION)) { ++ result = device_create_file(&tz->device, &dev_attr_emul_temp); ++ if (result) ++ goto unregister; ++ } ++ + /* Create policy attribute */ + result = device_create_file(&tz->device, &dev_attr_policy); + if (result) +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0014-thermal-Add-comment-explaining-test-for-critical-tem.patch b/target/linux/mediatek/patches/0014-thermal-Add-comment-explaining-test-for-critical-tem.patch new file mode 100644 index 0000000..56d3e4f --- /dev/null +++ b/target/linux/mediatek/patches/0014-thermal-Add-comment-explaining-test-for-critical-tem.patch @@ -0,0 +1,34 @@ +From 18f50eae474edc716b01959fad6898c8553b131c Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:33 +0200 +Subject: [PATCH 14/76] thermal: Add comment explaining test for critical + temperature + +The code testing if a temperature should be emulated or not is +not obvious. Add a comment explaining why this test is done. + +Signed-off-by: Sascha Hauer +Reviewed-by: Mikko Perttunen +--- + drivers/thermal/thermal_core.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index 3e0fe55..e204deb 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -435,6 +435,11 @@ int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp) + } + } + ++ /* ++ * Only allow emulating a temperature when the real temperature ++ * is below the critical temperature so that the emulation code ++ * cannot hide critical conditions. ++ */ + if (!ret && *temp < crit_temp) + *temp = tz->emul_temperature; + } +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0015-thermal-inline-only-once-used-function.patch b/target/linux/mediatek/patches/0015-thermal-inline-only-once-used-function.patch new file mode 100644 index 0000000..e050ae7 --- /dev/null +++ b/target/linux/mediatek/patches/0015-thermal-inline-only-once-used-function.patch @@ -0,0 +1,53 @@ +From 0b729a98127ef045096edf20dfe5c4eadac21d44 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:34 +0200 +Subject: [PATCH 15/76] thermal: inline only once used function + +Inline update_temperature into its only caller to make the code +more readable. + +Signed-off-by: Sascha Hauer +Reviewed-by: Mikko Perttunen +--- + drivers/thermal/thermal_core.c | 17 +++++------------ + 1 file changed, 5 insertions(+), 12 deletions(-) + +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index e204deb..19da022 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -450,9 +450,12 @@ exit: + } + EXPORT_SYMBOL_GPL(thermal_zone_get_temp); + +-static void update_temperature(struct thermal_zone_device *tz) ++void thermal_zone_device_update(struct thermal_zone_device *tz) + { +- int temp, ret; ++ int temp, ret, count; ++ ++ if (!tz->ops->get_temp) ++ return; + + ret = thermal_zone_get_temp(tz, &temp); + if (ret) { +@@ -471,16 +474,6 @@ static void update_temperature(struct thermal_zone_device *tz) + trace_thermal_temperature(tz); + dev_dbg(&tz->device, "last_temperature=%d, current_temperature=%d\n", + tz->last_temperature, tz->temperature); +-} +- +-void thermal_zone_device_update(struct thermal_zone_device *tz) +-{ +- int count; +- +- if (!tz->ops->get_temp) +- return; +- +- update_temperature(tz); + + for (count = 0; count < tz->trips; count++) + handle_thermal_trip(tz, count); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0016-thermal-streamline-get_trend-callbacks.patch b/target/linux/mediatek/patches/0016-thermal-streamline-get_trend-callbacks.patch new file mode 100644 index 0000000..99d490f --- /dev/null +++ b/target/linux/mediatek/patches/0016-thermal-streamline-get_trend-callbacks.patch @@ -0,0 +1,123 @@ +From 5da86f6a2b4c2c318e153649dc8fd34fe73f8292 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:35 +0200 +Subject: [PATCH 16/76] thermal: streamline get_trend callbacks + +The .get_trend callback in struct thermal_zone_device_ops has the prototype: + + int (*get_trend) (struct thermal_zone_device *, int, + enum thermal_trend *); + +whereas the .get_trend callback in struct thermal_zone_of_device_ops has: + + int (*get_trend)(void *, long *); + +Streamline both prototypes and add the trip argument to the OF callback +aswell and use enum thermal_trend * instead of an integer pointer. + +While the OF prototype may be the better one, this should be decided at +framework level and not on OF level. + +Signed-off-by: Sascha Hauer +--- + drivers/thermal/of-thermal.c | 11 +-------- + drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 25 +++++++------------- + include/linux/thermal.h | 2 +- + 3 files changed, 10 insertions(+), 28 deletions(-) + +diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c +index 03839df..c84404d 100644 +--- a/drivers/thermal/of-thermal.c ++++ b/drivers/thermal/of-thermal.c +@@ -187,24 +187,15 @@ static int of_thermal_get_trend(struct thermal_zone_device *tz, int trip, + enum thermal_trend *trend) + { + struct __thermal_zone *data = tz->devdata; +- long dev_trend; + int r; + + if (!data->ops->get_trend) + return -EINVAL; + +- r = data->ops->get_trend(data->sensor_data, &dev_trend); ++ r = data->ops->get_trend(data->sensor_data, trip, trend); + if (r) + return r; + +- /* TODO: These intervals might have some thresholds, but in core code */ +- if (dev_trend > 0) +- *trend = THERMAL_TREND_RAISING; +- else if (dev_trend < 0) +- *trend = THERMAL_TREND_DROPPING; +- else +- *trend = THERMAL_TREND_STABLE; +- + return 0; + } + +diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +index d3a42bf..ade78eb 100644 +--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c ++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +@@ -238,7 +238,7 @@ static int ti_thermal_get_trip_temp(struct thermal_zone_device *thermal, + return 0; + } + +-static int __ti_thermal_get_trend(void *p, long *trend) ++static int __ti_thermal_get_trend(void *p, int trip, enum thermal_trend *trend) + { + struct ti_thermal_data *data = p; + struct ti_bandgap *bgp; +@@ -251,22 +251,6 @@ static int __ti_thermal_get_trend(void *p, long *trend) + if (ret) + return ret; + +- *trend = tr; +- +- return 0; +-} +- +-/* Get the temperature trend callback functions for thermal zone */ +-static int ti_thermal_get_trend(struct thermal_zone_device *thermal, +- int trip, enum thermal_trend *trend) +-{ +- int ret; +- long tr; +- +- ret = __ti_thermal_get_trend(thermal->devdata, &tr); +- if (ret) +- return ret; +- + if (tr > 0) + *trend = THERMAL_TREND_RAISING; + else if (tr < 0) +@@ -277,6 +261,13 @@ static int ti_thermal_get_trend(struct thermal_zone_device *thermal, + return 0; + } + ++/* Get the temperature trend callback functions for thermal zone */ ++static int ti_thermal_get_trend(struct thermal_zone_device *thermal, ++ int trip, enum thermal_trend *trend) ++{ ++ return __ti_thermal_get_trend(thermal->devdata, trip, trend); ++} ++ + /* Get critical temperature callback functions for thermal zone */ + static int ti_thermal_get_crit_temp(struct thermal_zone_device *thermal, + int *temp) +diff --git a/include/linux/thermal.h b/include/linux/thermal.h +index e9f2863..5c6a589 100644 +--- a/include/linux/thermal.h ++++ b/include/linux/thermal.h +@@ -269,7 +269,7 @@ struct thermal_genl_event { + */ + struct thermal_zone_of_device_ops { + int (*get_temp)(void *, int *); +- int (*get_trend)(void *, long *); ++ int (*get_trend)(void *, int, enum thermal_trend *); + int (*set_emul_temp)(void *, int); + }; + +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0017-thermal-Allow-sensor-ops-to-fail-with-ENOSYS.patch b/target/linux/mediatek/patches/0017-thermal-Allow-sensor-ops-to-fail-with-ENOSYS.patch new file mode 100644 index 0000000..f533a88 --- /dev/null +++ b/target/linux/mediatek/patches/0017-thermal-Allow-sensor-ops-to-fail-with-ENOSYS.patch @@ -0,0 +1,90 @@ +From 5b622cb2d6ff44b1fb0750beee61f93f2c00548a Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:36 +0200 +Subject: [PATCH 17/76] thermal: Allow sensor ops to fail with -ENOSYS + +The thermal core uses the existence of the .get_temp, .get_trend and +.set_emul_temp to detect whether this operation exists and should be +used or whether it should be emulated in software. This makes problems +for of-thermal which has to modify the struct thermal_zone_device_ops +during runtime whenever a sensor is registered or unregistered. + +Let the core test for -ENOSYS from these callbacks and treat it like +if the callbacks were not present. + +This allows of-thermal to always set the sensor related callbacks and +to make struct thermal_zone_device_ops const again. + +Signed-off-by: Sascha Hauer +--- + drivers/thermal/thermal_core.c | 24 +++++++++++++++++------- + 1 file changed, 17 insertions(+), 7 deletions(-) + +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index 19da022..3d8f9f9 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -413,13 +413,16 @@ static void handle_thermal_trip(struct thermal_zone_device *tz, int trip) + */ + int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp) + { +- int ret = -EINVAL; ++ int ret; + int count; + int crit_temp = INT_MAX; + enum thermal_trip_type type; + +- if (!tz || IS_ERR(tz) || !tz->ops->get_temp) +- goto exit; ++ if (!tz || IS_ERR(tz)) ++ return -EINVAL; ++ ++ if (!tz->ops->get_temp) ++ return -ENOSYS; + + mutex_lock(&tz->lock); + +@@ -445,7 +448,7 @@ int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp) + } + + mutex_unlock(&tz->lock); +-exit: ++ + return ret; + } + EXPORT_SYMBOL_GPL(thermal_zone_get_temp); +@@ -454,10 +457,11 @@ void thermal_zone_device_update(struct thermal_zone_device *tz) + { + int temp, ret, count; + +- if (!tz->ops->get_temp) ++ ret = thermal_zone_get_temp(tz, &temp); ++ ++ if (ret == -ENOSYS) + return; + +- ret = thermal_zone_get_temp(tz, &temp); + if (ret) { + if (ret != -EAGAIN) + dev_warn(&tz->device, +@@ -783,10 +787,16 @@ emul_temp_store(struct device *dev, struct device_attribute *attr, + if (kstrtoul(buf, 10, &temperature)) + return -EINVAL; + +- if (!tz->ops->set_emul_temp) { ++ if (tz->ops->set_emul_temp) ++ ret = tz->ops->set_emul_temp(tz, temperature); ++ else ++ ret = -ENOSYS; ++ ++ if (ret == -ENOSYS) { + mutex_lock(&tz->lock); + tz->emul_temperature = temperature; + mutex_unlock(&tz->lock); ++ ret = 0; + } else { + ret = tz->ops->set_emul_temp(tz, temperature); + } +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0018-thermal-of-always-set-sensor-related-callbacks.patch b/target/linux/mediatek/patches/0018-thermal-of-always-set-sensor-related-callbacks.patch new file mode 100644 index 0000000..e47e8a2 --- /dev/null +++ b/target/linux/mediatek/patches/0018-thermal-of-always-set-sensor-related-callbacks.patch @@ -0,0 +1,129 @@ +From 8c9c4ed500e92c10dc4965dcd00692b3102a328a Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:37 +0200 +Subject: [PATCH 18/76] thermal: of: always set sensor related callbacks + +Now that the thermal core treats -ENOSYS like the callbacks were +not present at all we no longer have to overwrite the ops during +runtime but instead can always set them and return -ENOSYS if no +sensor is registered. + +Signed-off-by: Sascha Hauer +--- + drivers/thermal/of-thermal.c | 33 +++++++++++++-------------------- + 1 file changed, 13 insertions(+), 20 deletions(-) + +diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c +index c84404d..b9c35bd 100644 +--- a/drivers/thermal/of-thermal.c ++++ b/drivers/thermal/of-thermal.c +@@ -91,7 +91,7 @@ static int of_thermal_get_temp(struct thermal_zone_device *tz, + { + struct __thermal_zone *data = tz->devdata; + +- if (!data->ops->get_temp) ++ if (!data->ops) + return -EINVAL; + + return data->ops->get_temp(data->sensor_data, temp); +@@ -178,7 +178,7 @@ static int of_thermal_set_emul_temp(struct thermal_zone_device *tz, + struct __thermal_zone *data = tz->devdata; + + if (!data->ops || !data->ops->set_emul_temp) +- return -EINVAL; ++ return -ENOSYS; + + return data->ops->set_emul_temp(data->sensor_data, temp); + } +@@ -189,8 +189,8 @@ static int of_thermal_get_trend(struct thermal_zone_device *tz, int trip, + struct __thermal_zone *data = tz->devdata; + int r; + +- if (!data->ops->get_trend) +- return -EINVAL; ++ if (!data->ops || !data->ops->get_trend) ++ return -ENOSYS; + + r = data->ops->get_trend(data->sensor_data, trip, trend); + if (r) +@@ -366,6 +366,10 @@ static int of_thermal_get_crit_temp(struct thermal_zone_device *tz, + } + + static struct thermal_zone_device_ops of_thermal_ops = { ++ .get_temp = of_thermal_get_temp, ++ .get_trend = of_thermal_get_trend, ++ .set_emul_temp = of_thermal_set_emul_temp, ++ + .get_mode = of_thermal_get_mode, + .set_mode = of_thermal_set_mode, + +@@ -399,13 +403,13 @@ thermal_zone_of_add_sensor(struct device_node *zone, + if (!ops) + return ERR_PTR(-EINVAL); + ++ if (!ops->get_temp) ++ return ERR_PTR(-EINVAL); ++ + mutex_lock(&tzd->lock); + tz->ops = ops; + tz->sensor_data = data; + +- tzd->ops->get_temp = of_thermal_get_temp; +- tzd->ops->get_trend = of_thermal_get_trend; +- tzd->ops->set_emul_temp = of_thermal_set_emul_temp; + mutex_unlock(&tzd->lock); + + return tzd; +@@ -535,9 +539,6 @@ void thermal_zone_of_sensor_unregister(struct device *dev, + return; + + mutex_lock(&tzd->lock); +- tzd->ops->get_temp = NULL; +- tzd->ops->get_trend = NULL; +- tzd->ops->set_emul_temp = NULL; + + tz->ops = NULL; + tz->sensor_data = NULL; +@@ -845,7 +846,6 @@ int __init of_parse_thermal_zones(void) + { + struct device_node *np, *child; + struct __thermal_zone *tz; +- struct thermal_zone_device_ops *ops; + + np = of_find_node_by_name(NULL, "thermal-zones"); + if (!np) { +@@ -869,29 +869,22 @@ int __init of_parse_thermal_zones(void) + continue; + } + +- ops = kmemdup(&of_thermal_ops, sizeof(*ops), GFP_KERNEL); +- if (!ops) +- goto exit_free; +- + tzp = kzalloc(sizeof(*tzp), GFP_KERNEL); +- if (!tzp) { +- kfree(ops); ++ if (!tzp) + goto exit_free; +- } + + /* No hwmon because there might be hwmon drivers registering */ + tzp->no_hwmon = true; + + zone = thermal_zone_device_register(child->name, tz->ntrips, + 0, tz, +- ops, tzp, ++ &of_thermal_ops, tzp, + tz->passive_delay, + tz->polling_delay); + if (IS_ERR(zone)) { + pr_err("Failed to build %s zone %ld\n", child->name, + PTR_ERR(zone)); + kfree(tzp); +- kfree(ops); + of_thermal_free_zone(tz); + /* attempting to build remaining zones still */ + } +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0019-thermal-Make-struct-thermal_zone_device_ops-const.patch b/target/linux/mediatek/patches/0019-thermal-Make-struct-thermal_zone_device_ops-const.patch new file mode 100644 index 0000000..1ca9ab8 --- /dev/null +++ b/target/linux/mediatek/patches/0019-thermal-Make-struct-thermal_zone_device_ops-const.patch @@ -0,0 +1,327 @@ +From 7cbee588bc6eee59c025f89cf9324943fda98934 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:38 +0200 +Subject: [PATCH 19/76] thermal: Make struct thermal_zone_device_ops const + +Now that the of thermal support no longer changes the +thermal_zone_device_ops it can be const again. + +Signed-off-by: Sascha Hauer +--- + Documentation/thermal/sysfs-api.txt | 2 +- + drivers/acpi/thermal.c | 2 +- + drivers/platform/x86/acerhdf.c | 2 +- + drivers/platform/x86/intel_mid_thermal.c | 2 +- + drivers/power/power_supply_core.c | 2 +- + drivers/thermal/armada_thermal.c | 2 +- + drivers/thermal/db8500_thermal.c | 2 +- + drivers/thermal/dove_thermal.c | 2 +- + drivers/thermal/imx_thermal.c | 2 +- + drivers/thermal/int340x_thermal/int3400_thermal.c | 2 +- + drivers/thermal/int340x_thermal/int340x_thermal_zone.c | 2 +- + drivers/thermal/intel_soc_dts_thermal.c | 2 +- + drivers/thermal/kirkwood_thermal.c | 2 +- + drivers/thermal/of-thermal.c | 2 +- + drivers/thermal/rcar_thermal.c | 2 +- + drivers/thermal/spear_thermal.c | 2 +- + drivers/thermal/st/st_thermal.c | 2 +- + drivers/thermal/thermal_core.c | 2 +- + drivers/thermal/ti-soc-thermal/ti-thermal-common.c | 2 +- + drivers/thermal/x86_pkg_temp_thermal.c | 2 +- + include/linux/thermal.h | 6 +++--- + 21 files changed, 23 insertions(+), 23 deletions(-) + +diff --git a/Documentation/thermal/sysfs-api.txt b/Documentation/thermal/sysfs-api.txt +index 87519cb..bb346a2 100644 +--- a/Documentation/thermal/sysfs-api.txt ++++ b/Documentation/thermal/sysfs-api.txt +@@ -33,7 +33,7 @@ temperature) and throttle appropriate devices. + 1.1 thermal zone device interface + 1.1.1 struct thermal_zone_device *thermal_zone_device_register(char *type, + int trips, int mask, void *devdata, +- struct thermal_zone_device_ops *ops, ++ const struct thermal_zone_device_ops *ops, + const struct thermal_zone_params *tzp, + int passive_delay, int polling_delay)) + +diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c +index 68bff60..6b11462 100644 +--- a/drivers/acpi/thermal.c ++++ b/drivers/acpi/thermal.c +@@ -869,7 +869,7 @@ acpi_thermal_unbind_cooling_device(struct thermal_zone_device *thermal, + return acpi_thermal_cooling_device_cb(thermal, cdev, false); + } + +-static struct thermal_zone_device_ops acpi_thermal_zone_ops = { ++static const struct thermal_zone_device_ops acpi_thermal_zone_ops = { + .bind = acpi_thermal_bind_cooling_device, + .unbind = acpi_thermal_unbind_cooling_device, + .get_temp = thermal_get_temp, +diff --git a/drivers/platform/x86/acerhdf.c b/drivers/platform/x86/acerhdf.c +index f2ce63c..bae9ca0 100644 +--- a/drivers/platform/x86/acerhdf.c ++++ b/drivers/platform/x86/acerhdf.c +@@ -482,7 +482,7 @@ static int acerhdf_get_crit_temp(struct thermal_zone_device *thermal, + } + + /* bind callback functions to thermalzone */ +-static struct thermal_zone_device_ops acerhdf_dev_ops = { ++static const struct thermal_zone_device_ops acerhdf_dev_ops = { + .bind = acerhdf_bind, + .unbind = acerhdf_unbind, + .get_temp = acerhdf_get_ec_temp, +diff --git a/drivers/platform/x86/intel_mid_thermal.c b/drivers/platform/x86/intel_mid_thermal.c +index 0944e83..069d36b 100644 +--- a/drivers/platform/x86/intel_mid_thermal.c ++++ b/drivers/platform/x86/intel_mid_thermal.c +@@ -460,7 +460,7 @@ static int read_curr_temp(struct thermal_zone_device *tzd, unsigned long *temp) + } + + /* Can't be const */ +-static struct thermal_zone_device_ops tzd_ops = { ++static const struct thermal_zone_device_ops tzd_ops = { + .get_temp = read_curr_temp, + }; + +diff --git a/drivers/power/power_supply_core.c b/drivers/power/power_supply_core.c +index 87e2fd1..878cb4e 100644 +--- a/drivers/power/power_supply_core.c ++++ b/drivers/power/power_supply_core.c +@@ -509,7 +509,7 @@ static int power_supply_read_temp(struct thermal_zone_device *tzd, + return ret; + } + +-static struct thermal_zone_device_ops psy_tzd_ops = { ++static const struct thermal_zone_device_ops psy_tzd_ops = { + .get_temp = power_supply_read_temp, + }; + +diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c +index 26b8d32..3f59c8b 100644 +--- a/drivers/thermal/armada_thermal.c ++++ b/drivers/thermal/armada_thermal.c +@@ -183,7 +183,7 @@ static int armada_get_temp(struct thermal_zone_device *thermal, + return 0; + } + +-static struct thermal_zone_device_ops ops = { ++static const struct thermal_zone_device_ops ops = { + .get_temp = armada_get_temp, + }; + +diff --git a/drivers/thermal/db8500_thermal.c b/drivers/thermal/db8500_thermal.c +index b3eca71..38d6aab9 100644 +--- a/drivers/thermal/db8500_thermal.c ++++ b/drivers/thermal/db8500_thermal.c +@@ -210,7 +210,7 @@ static int db8500_sys_get_crit_temp(struct thermal_zone_device *thermal, + return -EINVAL; + } + +-static struct thermal_zone_device_ops thdev_ops = { ++static const struct thermal_zone_device_ops thdev_ops = { + .bind = db8500_cdev_bind, + .unbind = db8500_cdev_unbind, + .get_temp = db8500_sys_get_temp, +diff --git a/drivers/thermal/dove_thermal.c b/drivers/thermal/dove_thermal.c +index a0bc9de..e8fd627 100644 +--- a/drivers/thermal/dove_thermal.c ++++ b/drivers/thermal/dove_thermal.c +@@ -118,7 +118,7 @@ static int dove_get_temp(struct thermal_zone_device *thermal, + return 0; + } + +-static struct thermal_zone_device_ops ops = { ++static const struct thermal_zone_device_ops ops = { + .get_temp = dove_get_temp, + }; + +diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c +index f1424f0..8a3cfed 100644 +--- a/drivers/thermal/imx_thermal.c ++++ b/drivers/thermal/imx_thermal.c +@@ -332,7 +332,7 @@ static int imx_unbind(struct thermal_zone_device *tz, + return 0; + } + +-static struct thermal_zone_device_ops imx_tz_ops = { ++static const struct thermal_zone_device_ops imx_tz_ops = { + .bind = imx_bind, + .unbind = imx_unbind, + .get_temp = imx_get_temp, +diff --git a/drivers/thermal/int340x_thermal/int3400_thermal.c b/drivers/thermal/int340x_thermal/int3400_thermal.c +index 031018e..96bdf8a 100644 +--- a/drivers/thermal/int340x_thermal/int3400_thermal.c ++++ b/drivers/thermal/int340x_thermal/int3400_thermal.c +@@ -231,7 +231,7 @@ static int int3400_thermal_set_mode(struct thermal_zone_device *thermal, + return result; + } + +-static struct thermal_zone_device_ops int3400_thermal_ops = { ++static const struct thermal_zone_device_ops int3400_thermal_ops = { + .get_temp = int3400_thermal_get_temp, + }; + +diff --git a/drivers/thermal/int340x_thermal/int340x_thermal_zone.c b/drivers/thermal/int340x_thermal/int340x_thermal_zone.c +index b9b2666..bd9f9e8 100644 +--- a/drivers/thermal/int340x_thermal/int340x_thermal_zone.c ++++ b/drivers/thermal/int340x_thermal/int340x_thermal_zone.c +@@ -154,7 +154,7 @@ static int int340x_thermal_get_trip_hyst(struct thermal_zone_device *zone, + return 0; + } + +-static struct thermal_zone_device_ops int340x_thermal_zone_ops = { ++static const struct thermal_zone_device_ops int340x_thermal_zone_ops = { + .get_temp = int340x_thermal_get_zone_temp, + .get_trip_temp = int340x_thermal_get_trip_temp, + .get_trip_type = int340x_thermal_get_trip_type, +diff --git a/drivers/thermal/intel_soc_dts_thermal.c b/drivers/thermal/intel_soc_dts_thermal.c +index fd550b9..625ba6f 100644 +--- a/drivers/thermal/intel_soc_dts_thermal.c ++++ b/drivers/thermal/intel_soc_dts_thermal.c +@@ -270,7 +270,7 @@ static int sys_get_curr_temp(struct thermal_zone_device *tzd, int *temp) + return 0; + } + +-static struct thermal_zone_device_ops tzone_ops = { ++static const struct thermal_zone_device_ops tzone_ops = { + .get_temp = sys_get_curr_temp, + .get_trip_temp = sys_get_trip_temp, + .get_trip_type = sys_get_trip_type, +diff --git a/drivers/thermal/kirkwood_thermal.c b/drivers/thermal/kirkwood_thermal.c +index 11041fe..abba3e2 100644 +--- a/drivers/thermal/kirkwood_thermal.c ++++ b/drivers/thermal/kirkwood_thermal.c +@@ -60,7 +60,7 @@ static int kirkwood_get_temp(struct thermal_zone_device *thermal, + return 0; + } + +-static struct thermal_zone_device_ops ops = { ++static const struct thermal_zone_device_ops ops = { + .get_temp = kirkwood_get_temp, + }; + +diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c +index b9c35bd..bd3185e 100644 +--- a/drivers/thermal/of-thermal.c ++++ b/drivers/thermal/of-thermal.c +@@ -365,7 +365,7 @@ static int of_thermal_get_crit_temp(struct thermal_zone_device *tz, + return -EINVAL; + } + +-static struct thermal_zone_device_ops of_thermal_ops = { ++static const struct thermal_zone_device_ops of_thermal_ops = { + .get_temp = of_thermal_get_temp, + .get_trend = of_thermal_get_trend, + .set_emul_temp = of_thermal_set_emul_temp, +diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c +index 5d4ae7d..320ceac 100644 +--- a/drivers/thermal/rcar_thermal.c ++++ b/drivers/thermal/rcar_thermal.c +@@ -270,7 +270,7 @@ static int rcar_thermal_notify(struct thermal_zone_device *zone, + return 0; + } + +-static struct thermal_zone_device_ops rcar_thermal_zone_ops = { ++static const struct thermal_zone_device_ops rcar_thermal_zone_ops = { + .get_temp = rcar_thermal_get_temp, + .get_trip_type = rcar_thermal_get_trip_type, + .get_trip_temp = rcar_thermal_get_trip_temp, +diff --git a/drivers/thermal/spear_thermal.c b/drivers/thermal/spear_thermal.c +index 534dd91..ec07743 100644 +--- a/drivers/thermal/spear_thermal.c ++++ b/drivers/thermal/spear_thermal.c +@@ -50,7 +50,7 @@ static inline int thermal_get_temp(struct thermal_zone_device *thermal, + return 0; + } + +-static struct thermal_zone_device_ops ops = { ++static const struct thermal_zone_device_ops ops = { + .get_temp = thermal_get_temp, + }; + +diff --git a/drivers/thermal/st/st_thermal.c b/drivers/thermal/st/st_thermal.c +index 44cbba9..0cb5c19 100644 +--- a/drivers/thermal/st/st_thermal.c ++++ b/drivers/thermal/st/st_thermal.c +@@ -175,7 +175,7 @@ static int st_thermal_get_trip_temp(struct thermal_zone_device *th, + return 0; + } + +-static struct thermal_zone_device_ops st_tz_ops = { ++static const struct thermal_zone_device_ops st_tz_ops = { + .get_temp = st_thermal_get_temp, + .get_trip_type = st_thermal_get_trip_type, + .get_trip_temp = st_thermal_get_trip_temp, +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index 3d8f9f9..6bbf61f 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -1451,7 +1451,7 @@ static void remove_trip_attrs(struct thermal_zone_device *tz) + */ + struct thermal_zone_device *thermal_zone_device_register(const char *type, + int trips, int mask, void *devdata, +- struct thermal_zone_device_ops *ops, ++ const struct thermal_zone_device_ops *ops, + const struct thermal_zone_params *tzp, + int passive_delay, int polling_delay) + { +diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +index ade78eb..e9c82fc 100644 +--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c ++++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c +@@ -281,7 +281,7 @@ static const struct thermal_zone_of_device_ops ti_of_thermal_ops = { + .get_trend = __ti_thermal_get_trend, + }; + +-static struct thermal_zone_device_ops ti_thermal_ops = { ++static const struct thermal_zone_device_ops ti_thermal_ops = { + .get_temp = ti_thermal_get_temp, + .get_trend = ti_thermal_get_trend, + .bind = ti_thermal_bind, +diff --git a/drivers/thermal/x86_pkg_temp_thermal.c b/drivers/thermal/x86_pkg_temp_thermal.c +index 054c6d45..bb2b975 100644 +--- a/drivers/thermal/x86_pkg_temp_thermal.c ++++ b/drivers/thermal/x86_pkg_temp_thermal.c +@@ -274,7 +274,7 @@ static int sys_get_trip_type(struct thermal_zone_device *thermal, + } + + /* Thermal zone callback registry */ +-static struct thermal_zone_device_ops tzone_ops = { ++static const struct thermal_zone_device_ops tzone_ops = { + .get_temp = sys_get_curr_temp, + .get_trip_temp = sys_get_trip_temp, + .get_trip_type = sys_get_trip_type, +diff --git a/include/linux/thermal.h b/include/linux/thermal.h +index 5c6a589..07bd5e8 100644 +--- a/include/linux/thermal.h ++++ b/include/linux/thermal.h +@@ -181,7 +181,7 @@ struct thermal_zone_device { + int emul_temperature; + int passive; + unsigned int forced_passive; +- struct thermal_zone_device_ops *ops; ++ const struct thermal_zone_device_ops *ops; + const struct thermal_zone_params *tzp; + struct thermal_governor *governor; + struct list_head thermal_instances; +@@ -313,7 +313,7 @@ void thermal_zone_of_sensor_unregister(struct device *dev, + + #if IS_ENABLED(CONFIG_THERMAL) + struct thermal_zone_device *thermal_zone_device_register(const char *, int, int, +- void *, struct thermal_zone_device_ops *, ++ void *, const struct thermal_zone_device_ops *, + const struct thermal_zone_params *, int, int); + void thermal_zone_device_unregister(struct thermal_zone_device *); + +@@ -341,7 +341,7 @@ void thermal_notify_framework(struct thermal_zone_device *, int); + #else + static inline struct thermal_zone_device *thermal_zone_device_register( + const char *type, int trips, int mask, void *devdata, +- struct thermal_zone_device_ops *ops, ++ const struct thermal_zone_device_ops *ops, + const struct thermal_zone_params *tzp, + int passive_delay, int polling_delay) + { return ERR_PTR(-ENODEV); } +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0020-thermal-thermal-Add-support-for-hardware-tracked-tri.patch b/target/linux/mediatek/patches/0020-thermal-thermal-Add-support-for-hardware-tracked-tri.patch new file mode 100644 index 0000000..6a48350 --- /dev/null +++ b/target/linux/mediatek/patches/0020-thermal-thermal-Add-support-for-hardware-tracked-tri.patch @@ -0,0 +1,124 @@ +From 346632bc00fe71c269709702fecb474bb22e933e Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:39 +0200 +Subject: [PATCH 20/76] thermal: thermal: Add support for hardware-tracked + trip points + +This adds support for hardware-tracked trip points to the device tree +thermal sensor framework. + +The framework supports an arbitrary number of trip points. Whenever +the current temperature is updated, the trip points immediately +below and above the current temperature are found. A .set_trips +callback is then called with the temperatures. If there is no trip +point above or below the current temperature, the passed trip +temperature will be -INT_MAX or INT_MAX respectively. In this callback, +the driver should program the hardware such that it is notified +when either of these trip points are triggered. When a trip point +is triggered, the driver should call `thermal_zone_device_update' +for the respective thermal zone. This will cause the trip points +to be updated again. + +If .set_trips is not implemented, the framework behaves as before. + +This patch is based on an earlier version from Mikko Perttunen + + +Signed-off-by: Sascha Hauer +--- + drivers/thermal/thermal_core.c | 43 ++++++++++++++++++++++++++++++++++++++++ + include/linux/thermal.h | 3 +++ + 2 files changed, 46 insertions(+) + +diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c +index 6bbf61f..3ae1795 100644 +--- a/drivers/thermal/thermal_core.c ++++ b/drivers/thermal/thermal_core.c +@@ -453,6 +453,45 @@ int thermal_zone_get_temp(struct thermal_zone_device *tz, int *temp) + } + EXPORT_SYMBOL_GPL(thermal_zone_get_temp); + ++static void thermal_zone_set_trips(struct thermal_zone_device *tz) ++{ ++ int low = -INT_MAX; ++ int high = INT_MAX; ++ int trip_temp, hysteresis; ++ int temp = tz->temperature; ++ int i; ++ ++ if (!tz->ops->set_trips) ++ return; ++ ++ /* No need to change trip points */ ++ if (temp > tz->prev_low_trip && temp < tz->prev_high_trip) ++ return; ++ ++ for (i = 0; i < tz->trips; i++) { ++ int trip_low; ++ ++ tz->ops->get_trip_temp(tz, i, &trip_temp); ++ tz->ops->get_trip_hyst(tz, i, &hysteresis); ++ ++ trip_low = trip_temp - hysteresis; ++ ++ if (trip_low < temp && trip_low > low) ++ low = trip_low; ++ ++ if (trip_temp > temp && trip_temp < high) ++ high = trip_temp; ++ } ++ ++ tz->prev_low_trip = low; ++ tz->prev_high_trip = high; ++ ++ dev_dbg(&tz->device, "new temperature boundaries: %d < x < %d\n", ++ low, high); ++ ++ tz->ops->set_trips(tz, low, high); ++} ++ + void thermal_zone_device_update(struct thermal_zone_device *tz) + { + int temp, ret, count; +@@ -479,6 +518,8 @@ void thermal_zone_device_update(struct thermal_zone_device *tz) + dev_dbg(&tz->device, "last_temperature=%d, current_temperature=%d\n", + tz->last_temperature, tz->temperature); + ++ thermal_zone_set_trips(tz); ++ + for (count = 0; count < tz->trips; count++) + handle_thermal_trip(tz, count); + } +@@ -1494,6 +1535,8 @@ struct thermal_zone_device *thermal_zone_device_register(const char *type, + tz->trips = trips; + tz->passive_delay = passive_delay; + tz->polling_delay = polling_delay; ++ tz->prev_low_trip = INT_MAX; ++ tz->prev_high_trip = -INT_MAX; + + dev_set_name(&tz->device, "thermal_zone%d", tz->id); + result = device_register(&tz->device); +diff --git a/include/linux/thermal.h b/include/linux/thermal.h +index 07bd5e8..aef6e13 100644 +--- a/include/linux/thermal.h ++++ b/include/linux/thermal.h +@@ -87,6 +87,7 @@ struct thermal_zone_device_ops { + int (*unbind) (struct thermal_zone_device *, + struct thermal_cooling_device *); + int (*get_temp) (struct thermal_zone_device *, int *); ++ int (*set_trips) (struct thermal_zone_device *, int, int); + int (*get_mode) (struct thermal_zone_device *, + enum thermal_device_mode *); + int (*set_mode) (struct thermal_zone_device *, +@@ -180,6 +181,8 @@ struct thermal_zone_device { + int last_temperature; + int emul_temperature; + int passive; ++ int prev_low_trip; ++ int prev_high_trip; + unsigned int forced_passive; + const struct thermal_zone_device_ops *ops; + const struct thermal_zone_params *tzp; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0021-thermal-of-implement-.set_trips-for-device-tree-ther.patch b/target/linux/mediatek/patches/0021-thermal-of-implement-.set_trips-for-device-tree-ther.patch new file mode 100644 index 0000000..81b5043 --- /dev/null +++ b/target/linux/mediatek/patches/0021-thermal-of-implement-.set_trips-for-device-tree-ther.patch @@ -0,0 +1,65 @@ +From 525f68bb9d9f6334dbcd2b5ec99f9d797ff53618 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:40 +0200 +Subject: [PATCH 21/76] thermal: of: implement .set_trips for device tree + thermal zones + +Signed-off-by: Sascha Hauer +--- + drivers/thermal/of-thermal.c | 12 ++++++++++++ + include/linux/thermal.h | 3 +++ + 2 files changed, 15 insertions(+) + +diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c +index bd3185e..f8dd847 100644 +--- a/drivers/thermal/of-thermal.c ++++ b/drivers/thermal/of-thermal.c +@@ -97,6 +97,17 @@ static int of_thermal_get_temp(struct thermal_zone_device *tz, + return data->ops->get_temp(data->sensor_data, temp); + } + ++static int of_thermal_set_trips(struct thermal_zone_device *tz, ++ int low, int high) ++{ ++ struct __thermal_zone *data = tz->devdata; ++ ++ if (!data->ops || !data->ops->set_trips) ++ return -ENOSYS; ++ ++ return data->ops->set_trips(data->sensor_data, low, high); ++} ++ + /** + * of_thermal_get_ntrips - function to export number of available trip + * points. +@@ -367,6 +378,7 @@ static int of_thermal_get_crit_temp(struct thermal_zone_device *tz, + + static const struct thermal_zone_device_ops of_thermal_ops = { + .get_temp = of_thermal_get_temp, ++ .set_trips = of_thermal_set_trips, + .get_trend = of_thermal_get_trend, + .set_emul_temp = of_thermal_set_emul_temp, + +diff --git a/include/linux/thermal.h b/include/linux/thermal.h +index aef6e13..b751f6b 100644 +--- a/include/linux/thermal.h ++++ b/include/linux/thermal.h +@@ -267,12 +267,15 @@ struct thermal_genl_event { + * + * Optional: + * @get_trend: a pointer to a function that reads the sensor temperature trend. ++ * @set_trips: a pointer to a function that sets a temperature window which shall ++ * trigger an interrupt when it is left. + * @set_emul_temp: a pointer to a function that sets sensor emulated + * temperature. + */ + struct thermal_zone_of_device_ops { + int (*get_temp)(void *, int *); + int (*get_trend)(void *, int, enum thermal_trend *); ++ int (*set_trips)(void *, int, int); + int (*set_emul_temp)(void *, int); + }; + +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0022-dt-bindings-thermal-Add-binding-document-for-Mediate.patch b/target/linux/mediatek/patches/0022-dt-bindings-thermal-Add-binding-document-for-Mediate.patch new file mode 100644 index 0000000..c556ac0 --- /dev/null +++ b/target/linux/mediatek/patches/0022-dt-bindings-thermal-Add-binding-document-for-Mediate.patch @@ -0,0 +1,57 @@ +From 9b799b8a4ecbf560f8fb996e8e5147a8f7b9a1b3 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:41 +0200 +Subject: [PATCH 22/76] dt-bindings: thermal: Add binding document for + Mediatek thermal controller + +Signed-off-by: Sascha Hauer +--- + .../bindings/thermal/mediatek-thermal.txt | 36 ++++++++++++++++++++ + 1 file changed, 36 insertions(+) + create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt + +diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +new file mode 100644 +index 0000000..adf5d2c +--- /dev/null ++++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +@@ -0,0 +1,36 @@ ++* Mediatek Thermal ++ ++This describes the device tree binding for the Mediatek thermal controller ++which measures the on-SoC temperatures. This device does not have its own ADC, ++instead it directly controls the AUXADC via AHB bus accesses. For this reason ++this device needs phandles to the AUXADC. ++ ++Required properties: ++- compatible: "mediatek,mt8173-thermal" ++- reg: Address range of the thermal controller ++- interrupts: IRQ for the thermal controller ++- clocks, clock-names: Clocks needed for the thermal controller. required ++ clocks are: ++ "therm": Main clock needed for register access ++ "auxadc": The AUXADC clock ++- resets, reset-names: Reference to the reset controller controlling the thermal ++ controller. Required reset-names: ++ "therm": The main reset line ++- auxadc: A phandle to the AUXADC which the thermal controller uses ++- apmixedsys: A phandle to the APMIXEDSYS controller. ++- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description ++ ++Example: ++ ++ thermal: thermal@1100b000 { ++ #thermal-sensor-cells = <1>; ++ compatible = "mediatek,mt8173-thermal"; ++ reg = <0 0x1100b000 0 0x1000>; ++ interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; ++ clock-names = "therm", "auxadc"; ++ resets = <&pericfg MT8173_PERI_THERM_SW_RST>; ++ reset-names = "therm"; ++ auxadc = <&auxadc>; ++ apmixedsys = <&apmixedsys>; ++ }; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0023-thermal-Add-Mediatek-thermal-controller-support.patch b/target/linux/mediatek/patches/0023-thermal-Add-Mediatek-thermal-controller-support.patch new file mode 100644 index 0000000..827d721 --- /dev/null +++ b/target/linux/mediatek/patches/0023-thermal-Add-Mediatek-thermal-controller-support.patch @@ -0,0 +1,785 @@ +From 014330a304100782a26bc7df02778c8c386b2857 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:42 +0200 +Subject: [PATCH 23/76] thermal: Add Mediatek thermal controller support + +This adds support for the Mediatek thermal controller found on MT8173 +and likely other SoCs. +The controller is a bit special. It does not have its own ADC, instead +it controls the on-SoC AUXADC via AHB bus accesses. For this reason +we need the physical address of the AUXADC. Also it controls a mux +using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. + +Signed-off-by: Sascha Hauer +--- + drivers/thermal/Kconfig | 8 + + drivers/thermal/Makefile | 1 + + drivers/thermal/mtk_thermal.c | 728 +++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 737 insertions(+) + create mode 100644 drivers/thermal/mtk_thermal.c + +diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig +index af40db0..3aa5500 100644 +--- a/drivers/thermal/Kconfig ++++ b/drivers/thermal/Kconfig +@@ -285,6 +285,14 @@ config ACPI_THERMAL_REL + tristate + depends on ACPI + ++config MTK_THERMAL ++ tristate "Temperature sensor driver for mediatek SoCs" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ default y ++ help ++ Enable this option if you want to have support for thermal management ++ controller present in Mediatek SoCs ++ + menu "Texas Instruments thermal drivers" + source "drivers/thermal/ti-soc-thermal/Kconfig" + endmenu +diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile +index fa0dc48..51cfab7 100644 +--- a/drivers/thermal/Makefile ++++ b/drivers/thermal/Makefile +@@ -39,3 +39,4 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/ + obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ + obj-$(CONFIG_ST_THERMAL) += st/ + obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o ++obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o +diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c +new file mode 100644 +index 0000000..27aab12 +--- /dev/null ++++ b/drivers/thermal/mtk_thermal.c +@@ -0,0 +1,728 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Hanyi.Wu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* AUXADC Registers */ ++#define AUXADC_CON0_V 0x000 ++#define AUXADC_CON1_V 0x004 ++#define AUXADC_CON1_SET_V 0x008 ++#define AUXADC_CON1_CLR_V 0x00c ++#define AUXADC_CON2_V 0x010 ++#define AUXADC_DATA(channel) (0x14 + (channel) * 4) ++#define AUXADC_MISC_V 0x094 ++ ++#define AUXADC_CON1_CHANNEL(x) (1 << (x)) ++ ++/* Thermal Controller Registers */ ++#define TEMPMONCTL0 0x000 ++#define TEMPMONCTL1 0x004 ++#define TEMPMONCTL2 0x008 ++#define TEMPMONINT 0x00c ++#define TEMPMONINTSTS 0x010 ++#define TEMPMONIDET0 0x014 ++#define TEMPMONIDET1 0x018 ++#define TEMPMONIDET2 0x01c ++#define TEMPH2NTHRE 0x024 ++#define TEMPHTHRE 0x028 ++#define TEMPCTHRE 0x02c ++#define TEMPOFFSETH 0x030 ++#define TEMPOFFSETL 0x034 ++#define TEMPMSRCTL0 0x038 ++#define TEMPMSRCTL1 0x03c ++#define TEMPAHBPOLL 0x040 ++#define TEMPAHBTO 0x044 ++#define TEMPADCPNP0 0x048 ++#define TEMPADCPNP1 0x04c ++#define TEMPADCPNP2 0x050 ++#define TEMPADCPNP3 0x0b4 ++ ++#define TEMPADCMUX 0x054 ++#define TEMPADCEXT 0x058 ++#define TEMPADCEXT1 0x05c ++#define TEMPADCEN 0x060 ++#define TEMPPNPMUXADDR 0x064 ++#define TEMPADCMUXADDR 0x068 ++#define TEMPADCEXTADDR 0x06c ++#define TEMPADCEXT1ADDR 0x070 ++#define TEMPADCENADDR 0x074 ++#define TEMPADCVALIDADDR 0x078 ++#define TEMPADCVOLTADDR 0x07c ++#define TEMPRDCTRL 0x080 ++#define TEMPADCVALIDMASK 0x084 ++#define TEMPADCVOLTAGESHIFT 0x088 ++#define TEMPADCWRITECTRL 0x08c ++#define TEMPMSR0 0x090 ++#define TEMPMSR1 0x094 ++#define TEMPMSR2 0x098 ++#define TEMPMSR3 0x0B8 ++ ++#define TEMPIMMD0 0x0a0 ++#define TEMPIMMD1 0x0a4 ++#define TEMPIMMD2 0x0a8 ++ ++#define TEMPPROTCTL 0x0c0 ++#define TEMPPROTTA 0x0c4 ++#define TEMPPROTTB 0x0c8 ++#define TEMPPROTTC 0x0cc ++ ++#define TEMPSPARE0 0x0f0 ++#define TEMPSPARE1 0x0f4 ++#define TEMPSPARE2 0x0f8 ++#define TEMPSPARE3 0x0fc ++ ++#define PTPCORESEL 0x400 ++#define THERMINTST 0x404 ++#define PTPODINTST 0x408 ++#define THSTAGE0ST 0x40c ++#define THSTAGE1ST 0x410 ++#define THSTAGE2ST 0x414 ++#define THAHBST0 0x418 ++#define THAHBST1 0x41c /* Only for DE debug */ ++#define PTPSPARE0 0x420 ++#define PTPSPARE1 0x424 ++#define PTPSPARE2 0x428 ++#define PTPSPARE3 0x42c ++#define THSLPEVEB 0x430 ++ ++#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5)) ++#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5)) ++#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5)) ++#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5)) ++#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5)) ++#define TEMPMONINT_TIMEOUT (1 << 15) ++#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp))) ++#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp))) ++ ++#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0) ++#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1) ++#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2) ++#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3) ++ ++#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5) ++#define TEMPADCVALIDMASK_VALID_POS(bit) (bit) ++ ++#define TEMPPROTCTL_AVERAGE (0 << 16) ++#define TEMPPROTCTL_MAXIMUM (1 << 16) ++#define TEMPPROTCTL_SELECTED (2 << 16) ++ ++#define MT8173_THERMAL_ZONE_CA57 0 ++#define MT8173_THERMAL_ZONE_CA53 1 ++#define MT8173_THERMAL_ZONE_GPU 2 ++#define MT8173_THERMAL_ZONE_CORE 3 ++ ++#define MT8173_TS1 0 ++#define MT8173_TS2 1 ++#define MT8173_TS3 2 ++#define MT8173_TS4 3 ++#define MT8173_TSABB 4 ++ ++/* AUXADC channel 11 is used for the temperature sensors */ ++#define MT8173_TEMP_AUXADC_CHANNEL 11 ++ ++/* The total number of temperature sensors in the MT8173 */ ++#define MT8173_NUM_SENSORS 5 ++ ++/* The number of banks in the MT8173 */ ++#define MT8173_NUM_BANKS 4 ++ ++/* The number of sensing points per bank */ ++#define MT8173_NUM_SENSING_POINTS 4 ++ ++#define THERMAL_NAME "mtk-thermal" ++ ++struct mtk_thermal; ++ ++struct mtk_thermal_bank { ++ struct mtk_thermal *mt; ++ struct thermal_zone_device *tz; ++ int id; ++}; ++ ++struct mtk_thermal { ++ struct device *dev; ++ void __iomem *thermal_base; ++ void __iomem *auxadc_base; ++ ++ u64 auxadc_phys_base; ++ u64 apmixed_phys_base; ++ struct reset_control *reset; ++ struct clk *clk_peri_therm; ++ struct clk *clk_auxadc; ++ ++ struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; ++ ++ struct mutex lock; ++ ++ /* Calibration values */ ++ s32 adc_ge; ++ s32 adc_oe; ++ s32 degc_cali; ++ s32 o_slope; ++ s32 vts; ++}; ++ ++struct mtk_thermal_bank_cfg { ++ unsigned int enable_mask; ++ unsigned int sensors[4]; ++}; ++ ++static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; ++ ++/* ++ * The MT8173 thermal controller has four banks. Each bank can read up to ++ * four temperature sensors simultaneously. The MT8173 has a total of 5 ++ * temperature sensors. We use each bank to measure a certain area of the ++ * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple ++ * areas, hence is used in different banks. ++ */ ++static struct mtk_thermal_bank_cfg bank_data[] = { ++ { ++ .enable_mask = 3, ++ .sensors = { MT8173_TS2, MT8173_TS3 }, ++ }, { ++ .enable_mask = 3, ++ .sensors = { MT8173_TS2, MT8173_TS4 }, ++ }, { ++ .enable_mask = 7, ++ .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, ++ }, { ++ .enable_mask = 1, ++ .sensors = { MT8173_TS2 }, ++ }, ++}; ++ ++static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = { ++ TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3 ++}; ++ ++static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = { ++ TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3 ++}; ++ ++/** ++ * raw_to_mcelsius - convert a raw ADC value to mcelsius ++ * @mt: The thermal controller ++ * @raw: raw ADC value ++ * ++ * This converts the raw ADC value to mcelsius using the SoC specific ++ * calibration constants ++ */ ++static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) ++{ ++ s32 format_1, format_2, format_3, format_4; ++ s32 xtoomt; ++ s32 gain; ++ ++ raw &= 0xfff; ++ ++ gain = (10000 + mt->adc_ge); ++ ++ xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / ++ gain; ++ ++ format_1 = ((mt->degc_cali * 10) >> 1); ++ format_2 = (raw - mt->adc_oe); ++ format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; ++ format_3 = format_3 * 15 / 18; ++ format_4 = ((format_3 * 100) / (165 + mt->o_slope)); ++ format_4 = format_4 - (format_4 << 1); ++ ++ return (format_1 + format_4) * 100; ++} ++ ++/** ++ * mcelsius_to_raw - convert mcelsius to raw ADC value ++ * @mt: The thermal controller ++ * @temp: The temperature in mcelsius ++ * ++ * This converts a temperature in mcelsius to a raw ADC value, needed to ++ * calculate the trigger values for interrupt generation. ++ */ ++static u32 mcelsius_to_raw(struct mtk_thermal *mt, int temp) ++{ ++ s32 format_1, format_2, format_3, format_4; ++ s32 xtoomt; ++ s32 gain; ++ ++ gain = (10000 + mt->adc_ge); ++ ++ xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / ++ gain; ++ ++ format_1 = temp - (mt->degc_cali * 1000 / 2); ++ format_2 = format_1 * (165 + mt->o_slope) * 18 / 15; ++ format_2 = format_2 - 2 * format_2; ++ format_3 = format_2 / 1000 + xtoomt * 10; ++ format_4 = (format_3 * 4096 / 10000 * gain) / 100000 + mt->adc_oe; ++ ++ return format_4; ++} ++ ++/** ++ * mtk_thermal_get_bank - get bank ++ * @bank: The bank ++ * ++ * The bank registers are banked, we have to select a bank in the ++ * PTPCORESEL register to access it. ++ */ ++static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) ++{ ++ struct mtk_thermal *mt = bank->mt; ++ u32 val; ++ ++ mutex_lock(&mt->lock); ++ ++ val = readl(mt->thermal_base + PTPCORESEL); ++ val &= ~0xf; ++ val |= bank->id; ++ writel(val, mt->thermal_base + PTPCORESEL); ++} ++ ++/** ++ * mtk_thermal_put_bank - release bank ++ * @bank: The bank ++ * ++ * release a bank previously taken with mtk_thermal_get_bank, ++ */ ++static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) ++{ ++ struct mtk_thermal *mt = bank->mt; ++ ++ mutex_unlock(&mt->lock); ++} ++ ++/** ++ * mtk_thermal_bank_temperature - get the temperature of a bank ++ * @bank: The bank ++ * ++ * The temperature of a bank is considered the maximum temperature of ++ * the sensors associated to the bank. ++ */ ++static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) ++{ ++ struct mtk_thermal *mt = bank->mt; ++ int temp, i, max; ++ u32 raw; ++ ++ temp = max = -INT_MAX; ++ ++ for (i = 0; i < 4; i++) { ++ int sensno; ++ ++ if (!(bank_data[bank->id].enable_mask & (1 << i))) ++ continue; ++ ++ raw = readl(mt->thermal_base + tempmsr_ofs[i]); ++ ++ sensno = bank_data[bank->id].sensors[i]; ++ temp = raw_to_mcelsius(mt, raw); ++ ++ if (temp > max) ++ max = temp; ++ } ++ ++ return max; ++} ++ ++static void mtk_thermal_irq_bank(struct mtk_thermal_bank *bank) ++{ ++ struct mtk_thermal *mt = bank->mt; ++ int sp; ++ u32 irqstat; ++ bool update = false; ++ ++ mtk_thermal_get_bank(bank); ++ ++ irqstat = readl(mt->thermal_base + TEMPMONINTSTS); ++ ++ mtk_thermal_put_bank(bank); ++ ++ for (sp = 0; sp < 3; sp++) { ++ if (irqstat & TEMPMONINT_LOW_OFS(sp)) { ++ update = true; ++ dev_vdbg(mt->dev, "bank %d sensor %d low offset interrupt\n", ++ bank->id, sp); ++ } ++ ++ if (irqstat & TEMPMONINT_HIGH_OFS(sp)) { ++ update = true; ++ dev_vdbg(mt->dev, "bank %d sensor %d high offset interrupt\n", ++ bank->id, sp); ++ } ++ } ++ ++ if (update) ++ thermal_zone_device_update(bank->tz); ++} ++ ++static irqreturn_t mtk_thermal_irq(int irq, void *dev_id) ++{ ++ struct mtk_thermal *mt = dev_id; ++ u32 irqstat = 0; ++ int i; ++ ++ irqstat = readl(mt->thermal_base + THERMINTST); ++ ++ dev_vdbg(mt->dev, "thermal_interrupt_handler : THERMINTST = 0x%x\n", ++ irqstat); ++ ++ for (i = 0; i < MT8173_NUM_BANKS; i++) { ++ if (!(irqstat & (1 << i))) ++ mtk_thermal_irq_bank(&mt->banks[i]); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int mtk_read_temp(void *data, int *temp) ++{ ++ struct mtk_thermal_bank *bank = data; ++ ++ mtk_thermal_get_bank(bank); ++ ++ *temp = mtk_thermal_bank_temperature(bank); ++ ++ mtk_thermal_put_bank(bank); ++ ++ return 0; ++} ++ ++static int mtk_set_trips(void *data, int low, int high) ++{ ++ struct mtk_thermal_bank *bank = data; ++ struct mtk_thermal *mt = bank->mt; ++ int i; ++ u32 val, enable_mask; ++ u32 raw_low, raw_high; ++ ++ raw_low = mcelsius_to_raw(mt, low); ++ raw_high = mcelsius_to_raw(mt, high); ++ ++ mtk_thermal_get_bank(bank); ++ ++ writel(0x0, mt->thermal_base + TEMPMONINT); ++ ++ writel(TEMPPROTCTL_SELECTED, mt->thermal_base + TEMPPROTCTL); ++ ++ writel(raw_low, mt->thermal_base + TEMPOFFSETL); ++ writel(raw_high, mt->thermal_base + TEMPOFFSETH); ++ ++ enable_mask = readl(mt->thermal_base + TEMPMONCTL0); ++ ++ val = 0; ++ for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) ++ if (enable_mask & (1 << i)) ++ val |= TEMPMONINT_LOW_OFS(i) | TEMPMONINT_HIGH_OFS(i); ++ ++ writel(val, mt->thermal_base + TEMPMONINT); ++ ++ mtk_thermal_put_bank(bank); ++ ++ dev_dbg(mt->dev, "new boundaries: %d (0x%04x) < x < %d (0x%04x)\n", ++ low, mcelsius_to_raw(mt, low), ++ high, mcelsius_to_raw(mt, high)); ++ ++ return 0; ++} ++ ++static const struct thermal_zone_of_device_ops mtk_thermal_ops = { ++ .get_temp = mtk_read_temp, ++ .set_trips = mtk_set_trips, ++}; ++ ++static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank) ++{ ++ struct mtk_thermal *mt = bank->mt; ++ struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id]; ++ int i; ++ ++ mtk_thermal_get_bank(bank); ++ ++ /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ ++ writel(0x0000000c, mt->thermal_base + TEMPMONCTL1); ++ ++ /* ++ * filt interval is 1 * 46.540us = 46.54us, ++ * sen interval is 429 * 46.540us = 19.96ms ++ */ ++ writel(0x000101ad, mt->thermal_base + TEMPMONCTL2); ++ ++ /* poll is set to 10u */ ++ writel(0x00000300, mt->thermal_base + TEMPAHBPOLL); ++ ++ /* temperature sampling control, 1 sample */ ++ writel(0x00000000, mt->thermal_base + TEMPMSRCTL0); ++ ++ /* exceed this polling time, IRQ would be inserted */ ++ writel(0xffffffff, mt->thermal_base + TEMPAHBTO); ++ ++ /* number of interrupts per event, 1 is enough */ ++ writel(0x0, mt->thermal_base + TEMPMONIDET0); ++ writel(0x0, mt->thermal_base + TEMPMONIDET1); ++ ++ /* ++ * The MT8173 thermal controller does not have its own ADC. Instead it ++ * uses AHB bus accesses to control the AUXADC. To do this the thermal ++ * controller has to be programmed with the physical addresses of the ++ * AUXADC registers and with the various bit positions in the AUXADC. ++ * Also the thermal controller controls a mux in the APMIXEDSYS register ++ * space. ++ */ ++ ++ /* ++ * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0) ++ * automatically by hw ++ */ ++ writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX); ++ ++ /* AHB address for auxadc mux selection */ ++ writel(mt->auxadc_phys_base + 0x00c, ++ mt->thermal_base + TEMPADCMUXADDR); ++ ++ /* AHB address for pnp sensor mux selection */ ++ writel(mt->apmixed_phys_base + 0x0604, ++ mt->thermal_base + TEMPPNPMUXADDR); ++ ++ /* AHB value for auxadc enable */ ++ writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN); ++ ++ /* AHB address for auxadc enable (channel 0 immediate mode selected) */ ++ writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V, ++ mt->thermal_base + TEMPADCENADDR); ++ ++ /* AHB address for auxadc valid bit */ ++ writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), ++ mt->thermal_base + TEMPADCVALIDADDR); ++ ++ /* AHB address for auxadc voltage output */ ++ writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), ++ mt->thermal_base + TEMPADCVOLTADDR); ++ ++ /* read valid & voltage are at the same register */ ++ writel(0x0, mt->thermal_base + TEMPRDCTRL); ++ ++ /* indicate where the valid bit is */ ++ writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12), ++ mt->thermal_base + TEMPADCVALIDMASK); ++ ++ /* no shift */ ++ writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT); ++ ++ /* enable auxadc mux write transaction */ ++ writel(TEMPADCWRITECTRL_ADC_MUX_WRITE, ++ mt->thermal_base + TEMPADCWRITECTRL); ++ ++ for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) ++ writel(sensor_mux_values[cfg->sensors[i]], ++ mt->thermal_base + tempadcpnp_ofs[i]); ++ ++ writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0); ++ ++ writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE, ++ mt->thermal_base + TEMPADCWRITECTRL); ++ ++ mtk_thermal_put_bank(bank); ++} ++ ++static u64 of_get_phys_base(struct device_node *np) ++{ ++ u64 size64; ++ const __be32 *regaddr_p; ++ ++ regaddr_p = of_get_address(np, 0, &size64, NULL); ++ if (!regaddr_p) ++ return OF_BAD_ADDR; ++ ++ return of_translate_address(np, regaddr_p); ++} ++ ++static int mtk_thermal_probe(struct platform_device *pdev) ++{ ++ int ret, i; ++ struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; ++ int irq; ++ struct mtk_thermal *mt; ++ struct resource *res; ++ ++ mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); ++ if (!mt) ++ return -ENOMEM; ++ ++ mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); ++ if (IS_ERR(mt->clk_peri_therm)) ++ return PTR_ERR(mt->clk_peri_therm); ++ ++ mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); ++ if (IS_ERR(mt->clk_auxadc)) ++ return PTR_ERR(mt->clk_auxadc); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(mt->thermal_base)) ++ return PTR_ERR(mt->thermal_base); ++ ++ mt->reset = devm_reset_control_get(&pdev->dev, "therm"); ++ if (IS_ERR(mt->reset)) { ++ ret = PTR_ERR(mt->reset); ++ dev_err(&pdev->dev, "cannot get reset: %d\n", ret); ++ return ret; ++ } ++ ++ mutex_init(&mt->lock); ++ ++ mt->dev = &pdev->dev; ++ ++ auxadc = of_parse_phandle(np, "auxadc", 0); ++ if (!auxadc) { ++ dev_err(&pdev->dev, "missing auxadc node\n"); ++ return -ENODEV; ++ } ++ ++ mt->auxadc_phys_base = of_get_phys_base(auxadc); ++ if (mt->auxadc_phys_base == OF_BAD_ADDR) { ++ dev_err(&pdev->dev, "Can't get auxadc phys address\n"); ++ return -EINVAL; ++ } ++ ++ apmixedsys = of_parse_phandle(np, "apmixedsys", 0); ++ if (!apmixedsys) { ++ dev_err(&pdev->dev, "missing apmixedsys node\n"); ++ return -ENODEV; ++ } ++ ++ mt->apmixed_phys_base = of_get_phys_base(apmixedsys); ++ if (mt->apmixed_phys_base == OF_BAD_ADDR) { ++ dev_err(&pdev->dev, "Can't get auxadc phys address\n"); ++ return -EINVAL; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (!irq) { ++ dev_err(&pdev->dev, "Can't find irq\n"); ++ return -EINVAL; ++ } ++ ++ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, mtk_thermal_irq, ++ IRQF_ONESHOT, THERMAL_NAME, mt); ++ if (ret) { ++ dev_err(&pdev->dev, "Can't request irq %d: %d\n", irq, ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(mt->clk_auxadc); ++ if (ret) { ++ dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); ++ return ret; ++ } ++ ++ reset_control_reset(mt->reset); ++ ++ ret = clk_prepare_enable(mt->clk_peri_therm); ++ if (ret) { ++ dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); ++ goto err_enable_clk; ++ } ++ ++ /* ++ * These calibration values should finally be provided by the ++ * firmware or fuses. For now use default values. ++ */ ++ mt->adc_ge = ((512 - 512) * 10000) / 4096; ++ mt->adc_oe = 512 - 512; ++ mt->degc_cali = 40; ++ mt->o_slope = 0; ++ mt->vts = 260; ++ ++ for (i = 0; i < MT8173_NUM_BANKS; i++) { ++ struct mtk_thermal_bank *bank = &mt->banks[i]; ++ ++ bank->id = i; ++ bank->mt = mt; ++ mtk_thermal_init_bank(&mt->banks[i]); ++ } ++ ++ platform_set_drvdata(pdev, mt); ++ ++ /* ++ * This is needed after initialising the banks because otherwise ++ * the first temperature read contains bogus high temperatures which ++ * immediately cause a system shutdown. ++ */ ++ msleep(100); ++ ++ for (i = 0; i < MT8173_NUM_BANKS; i++) { ++ struct mtk_thermal_bank *bank = &mt->banks[i]; ++ ++ bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, ++ &mtk_thermal_ops); ++ } ++ ++ return 0; ++ ++err_enable_clk: ++ clk_disable_unprepare(mt->clk_peri_therm); ++ ++ return ret; ++} ++ ++static int mtk_thermal_remove(struct platform_device *pdev) ++{ ++ struct mtk_thermal *mt = platform_get_drvdata(pdev); ++ int i; ++ ++ for (i = 0; i < MT8173_NUM_BANKS; i++) { ++ struct mtk_thermal_bank *bank = &mt->banks[i]; ++ ++ if (!IS_ERR(bank)) ++ thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); ++ } ++ ++ clk_disable_unprepare(mt->clk_peri_therm); ++ clk_disable_unprepare(mt->clk_auxadc); ++ ++ return 0; ++} ++ ++static const struct of_device_id mtk_thermal_of_match[] = { ++ { ++ .compatible = "mediatek,mt8173-thermal", ++ }, { ++ }, ++}; ++ ++static struct platform_driver mtk_thermal_driver = { ++ .probe = mtk_thermal_probe, ++ .remove = mtk_thermal_remove, ++ .driver = { ++ .name = THERMAL_NAME, ++ .of_match_table = mtk_thermal_of_match, ++ }, ++}; ++ ++module_platform_driver(mtk_thermal_driver); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0024-ARM64-dts-mt8173-Add-thermal-auxadc-device-nodes.patch b/target/linux/mediatek/patches/0024-ARM64-dts-mt8173-Add-thermal-auxadc-device-nodes.patch new file mode 100644 index 0000000..ef80497 --- /dev/null +++ b/target/linux/mediatek/patches/0024-ARM64-dts-mt8173-Add-thermal-auxadc-device-nodes.patch @@ -0,0 +1,49 @@ +From 720e25e5c821336f7fa0c5fb564475c791c00340 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer +Date: Wed, 13 May 2015 10:52:43 +0200 +Subject: [PATCH 24/76] ARM64: dts: mt8173: Add thermal/auxadc device nodes + +Signed-off-by: Sascha Hauer +--- + arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi +index 924fdb6..50d424f 100644 +--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi +@@ -147,6 +147,11 @@ + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + ++ auxadc: auxadc@11001000 { ++ compatible = "mediatek,mt8173-auxadc"; ++ reg = <0 0x11001000 0 0x1000>; ++ }; ++ + uart0: serial@11002000 { + compatible = "mediatek,mt8173-uart", + "mediatek,mt6577-uart"; +@@ -182,6 +187,19 @@ + clocks = <&uart_clk>; + status = "disabled"; + }; ++ ++ thermal: thermal@1100b000 { ++ #thermal-sensor-cells = <1>; ++ compatible = "mediatek,mt8173-thermal"; ++ reg = <0 0x1100b000 0 0x1000>; ++ interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; ++ clock-names = "therm", "auxadc"; ++ resets = <&pericfg MT8173_PERI_THERM_SW_RST>; ++ reset-names = "therm"; ++ auxadc = <&auxadc>; ++ apmixedsys = <&apmixedsys>; ++ }; + }; + + }; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0025-dt-bindings-ARM-Mediatek-Document-devicetree-binding.patch b/target/linux/mediatek/patches/0025-dt-bindings-ARM-Mediatek-Document-devicetree-binding.patch new file mode 100644 index 0000000..ab8f2d5 --- /dev/null +++ b/target/linux/mediatek/patches/0025-dt-bindings-ARM-Mediatek-Document-devicetree-binding.patch @@ -0,0 +1,53 @@ +From a6de66d3cf5add25f2b8913332117f3334db506e Mon Sep 17 00:00:00 2001 +From: Leilk Liu +Date: Fri, 8 May 2015 16:55:41 +0800 +Subject: [PATCH 25/76] dt-bindings: ARM: Mediatek: Document devicetree + bindings for spi bus + +Signed-off-by: Leilk Liu +--- + .../devicetree/bindings/spi/spi-mt65xx.txt | 32 ++++++++++++++++++++ + 1 file changed, 32 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/spi-mt65xx.txt + +diff --git a/Documentation/devicetree/bindings/spi/spi-mt65xx.txt b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt +new file mode 100644 +index 0000000..04c28fd +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/spi-mt65xx.txt +@@ -0,0 +1,32 @@ ++MTK SPI device ++ ++Required properties: ++- compatible: should be one of the following. ++ - mediatek,mt8173-spi: for mt8173 platforms ++ - mediatek,mt8135-spi: for mt8135 platforms ++ - mediatek,mt6589-spi: for mt6589 platforms ++ ++- reg: Address and length of the register set for the device ++ ++- interrupts: Should contain spi interrupt ++ ++- clock-names: tuple listing input clock names. ++ Required elements: "main" ++ ++- clocks: phandles to input clocks. ++ ++- pad-select: should specify spi pad used, only required for MT8173. ++ This value should be 0~3. ++ ++Example: ++ ++- SoC Specific Portion: ++spi: spi@1100a000 { ++ compatible = "mediatek,mt8173-spi"; ++ reg = <0 0x1100a000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg PERI_SPI0>; ++ clock-names = "main"; ++ pad-select = <1>; ++ status = "disabled"; ++}; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0026-spi-mediatek-Add-spi-bus-for-Mediatek-MT8173.patch b/target/linux/mediatek/patches/0026-spi-mediatek-Add-spi-bus-for-Mediatek-MT8173.patch new file mode 100644 index 0000000..3466581 --- /dev/null +++ b/target/linux/mediatek/patches/0026-spi-mediatek-Add-spi-bus-for-Mediatek-MT8173.patch @@ -0,0 +1,679 @@ +From 047222cfefe97ef8706f03117bc8deada4cb4ddd Mon Sep 17 00:00:00 2001 +From: Leilk Liu +Date: Fri, 8 May 2015 16:55:42 +0800 +Subject: [PATCH 26/76] spi: mediatek: Add spi bus for Mediatek MT8173 + +This patch adds basic spi bus for MT8173. + +Signed-off-by: Leilk Liu +--- + drivers/spi/Kconfig | 10 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-mt65xx.c | 622 ++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 633 insertions(+) + create mode 100644 drivers/spi/spi-mt65xx.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index 72b0590..53dbea3 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -325,6 +325,16 @@ config SPI_MESON_SPIFC + This enables master mode support for the SPIFC (SPI flash + controller) available in Amlogic Meson SoCs. + ++config SPI_MT65XX ++ tristate "MediaTek SPI controller" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select SPI_BITBANG ++ help ++ This selects the MediaTek(R) SPI bus driver. ++ If you want to use MediaTek(R) SPI interface, ++ say Y or M here.If you are not sure, say N. ++ SPI drivers for Mediatek mt65XX series ARM SoCs. ++ + config SPI_OC_TINY + tristate "OpenCores tiny SPI" + depends on GPIOLIB +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index d8cbf65..ab332ef 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o + obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o + obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o + obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o ++obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o + obj-$(CONFIG_SPI_MXS) += spi-mxs.o + obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o + obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o +diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c +new file mode 100644 +index 0000000..92c119d +--- /dev/null ++++ b/drivers/spi/spi-mt65xx.c +@@ -0,0 +1,622 @@ ++/* ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: Leilk Liu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SPI_CFG0_REG 0x0000 ++#define SPI_CFG1_REG 0x0004 ++#define SPI_TX_SRC_REG 0x0008 ++#define SPI_RX_DST_REG 0x000c ++#define SPI_CMD_REG 0x0018 ++#define SPI_STATUS0_REG 0x001c ++#define SPI_PAD_SEL_REG 0x0024 ++ ++#define SPI_CFG0_SCK_HIGH_OFFSET 0 ++#define SPI_CFG0_SCK_LOW_OFFSET 8 ++#define SPI_CFG0_CS_HOLD_OFFSET 16 ++#define SPI_CFG0_CS_SETUP_OFFSET 24 ++ ++#define SPI_CFG0_SCK_HIGH_MASK 0xff ++#define SPI_CFG0_SCK_LOW_MASK 0xff00 ++#define SPI_CFG0_CS_HOLD_MASK 0xff0000 ++#define SPI_CFG0_CS_SETUP_MASK 0xff000000 ++ ++#define SPI_CFG1_CS_IDLE_OFFSET 0 ++#define SPI_CFG1_PACKET_LOOP_OFFSET 8 ++#define SPI_CFG1_PACKET_LENGTH_OFFSET 16 ++#define SPI_CFG1_GET_TICK_DLY_OFFSET 30 ++ ++#define SPI_CFG1_CS_IDLE_MASK 0xff ++#define SPI_CFG1_PACKET_LOOP_MASK 0xff00 ++#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 ++#define SPI_CFG1_GET_TICK_DLY_MASK 0xc0000000 ++ ++#define SPI_CMD_ACT_OFFSET 0 ++#define SPI_CMD_RESUME_OFFSET 1 ++#define SPI_CMD_RST_OFFSET 2 ++#define SPI_CMD_PAUSE_EN_OFFSET 4 ++#define SPI_CMD_DEASSERT_OFFSET 5 ++#define SPI_CMD_CPHA_OFFSET 8 ++#define SPI_CMD_CPOL_OFFSET 9 ++#define SPI_CMD_RX_DMA_OFFSET 10 ++#define SPI_CMD_TX_DMA_OFFSET 11 ++#define SPI_CMD_TXMSBF_OFFSET 12 ++#define SPI_CMD_RXMSBF_OFFSET 13 ++#define SPI_CMD_RX_ENDIAN_OFFSET 14 ++#define SPI_CMD_TX_ENDIAN_OFFSET 15 ++#define SPI_CMD_FINISH_IE_OFFSET 16 ++#define SPI_CMD_PAUSE_IE_OFFSET 17 ++ ++#define SPI_CMD_RESUME_MASK 0x2 ++#define SPI_CMD_RST_MASK 0x4 ++#define SPI_CMD_PAUSE_EN_MASK 0x10 ++#define SPI_CMD_DEASSERT_MASK 0x20 ++#define SPI_CMD_CPHA_MASK 0x100 ++#define SPI_CMD_CPOL_MASK 0x200 ++#define SPI_CMD_RX_DMA_MASK 0x400 ++#define SPI_CMD_TX_DMA_MASK 0x800 ++#define SPI_CMD_TXMSBF_MASK 0x1000 ++#define SPI_CMD_RXMSBF_MASK 0x2000 ++#define SPI_CMD_RX_ENDIAN_MASK 0x4000 ++#define SPI_CMD_TX_ENDIAN_MASK 0x8000 ++#define SPI_CMD_FINISH_IE_MASK 0x10000 ++ ++#define COMPAT_MT6589 (0x1 << 0) ++#define COMPAT_MT8173 (0x1 << 1) ++ ++#define MT8173_MAX_PAD_SEL 3 ++ ++#define IDLE 0 ++#define INPROGRESS 1 ++#define PAUSED 2 ++ ++#define PACKET_SIZE 1024 ++ ++struct mtk_chip_config { ++ u32 setuptime; ++ u32 holdtime; ++ u32 high_time; ++ u32 low_time; ++ u32 cs_idletime; ++ u32 tx_mlsb; ++ u32 rx_mlsb; ++ u32 tx_endian; ++ u32 rx_endian; ++ u32 pause; ++ u32 finish_intr; ++ u32 deassert; ++ u32 tckdly; ++}; ++ ++struct mtk_spi_ddata { ++ struct spi_bitbang bitbang; ++ void __iomem *base; ++ u32 irq; ++ u32 state; ++ u32 platform_compat; ++ u32 pad_sel; ++ struct clk *clk; ++ ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ u32 tx_len, rx_len; ++ struct completion done; ++}; ++ ++/* ++ * A piece of default chip info unless the platform ++ * supplies it. ++ */ ++static const struct mtk_chip_config mtk_default_chip_info = { ++ .setuptime = 10, ++ .holdtime = 12, ++ .high_time = 6, ++ .low_time = 6, ++ .cs_idletime = 12, ++ .rx_mlsb = 1, ++ .tx_mlsb = 1, ++ .tx_endian = 0, ++ .rx_endian = 0, ++ .pause = 0, ++ .finish_intr = 1, ++ .deassert = 0, ++ .tckdly = 0, ++}; ++ ++static const struct of_device_id mtk_spi_of_match[] = { ++ { .compatible = "mediatek,mt6589-spi", .data = (void *)COMPAT_MT6589}, ++ { .compatible = "mediatek,mt8173-spi", .data = (void *)COMPAT_MT8173}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mtk_spi_of_match); ++ ++static void mtk_spi_reset(struct mtk_spi_ddata *mdata) ++{ ++ u32 reg_val; ++ ++ /*set the software reset bit in SPI_CMD_REG.*/ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~SPI_CMD_RST_MASK; ++ reg_val |= 1 << SPI_CMD_RST_OFFSET; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~SPI_CMD_RST_MASK; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++} ++ ++static void mtk_set_pause_bit(struct mtk_spi_ddata *mdata) ++{ ++ u32 reg_val; ++ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val |= 1 << SPI_CMD_PAUSE_EN_OFFSET; ++ reg_val |= 1 << SPI_CMD_PAUSE_IE_OFFSET; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++} ++ ++static void mtk_clear_pause_bit(struct mtk_spi_ddata *mdata) ++{ ++ u32 reg_val; ++ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~SPI_CMD_PAUSE_EN_MASK; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++} ++ ++static int mtk_spi_config(struct mtk_spi_ddata *mdata, ++ struct mtk_chip_config *chip_config) ++{ ++ u32 reg_val; ++ ++ /* set the timing */ ++ reg_val = readl(mdata->base + SPI_CFG0_REG); ++ reg_val &= ~(SPI_CFG0_SCK_HIGH_MASK | SPI_CFG0_SCK_LOW_MASK); ++ reg_val &= ~(SPI_CFG0_CS_HOLD_MASK | SPI_CFG0_CS_SETUP_MASK); ++ reg_val |= ((chip_config->high_time - 1) << SPI_CFG0_SCK_HIGH_OFFSET); ++ reg_val |= ((chip_config->low_time - 1) << SPI_CFG0_SCK_LOW_OFFSET); ++ reg_val |= ((chip_config->holdtime - 1) << SPI_CFG0_CS_HOLD_OFFSET); ++ reg_val |= ((chip_config->setuptime - 1) << SPI_CFG0_CS_SETUP_OFFSET); ++ writel(reg_val, mdata->base + SPI_CFG0_REG); ++ ++ reg_val = readl(mdata->base + SPI_CFG1_REG); ++ reg_val &= ~SPI_CFG1_CS_IDLE_MASK; ++ reg_val |= ((chip_config->cs_idletime - 1) << SPI_CFG1_CS_IDLE_OFFSET); ++ reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; ++ reg_val |= ((chip_config->tckdly) << SPI_CFG1_GET_TICK_DLY_OFFSET); ++ writel(reg_val, mdata->base + SPI_CFG1_REG); ++ ++ /* set the mlsbx and mlsbtx */ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~(SPI_CMD_TX_ENDIAN_MASK | SPI_CMD_RX_ENDIAN_MASK); ++ reg_val &= ~(SPI_CMD_TXMSBF_MASK | SPI_CMD_RXMSBF_MASK); ++ reg_val |= (chip_config->tx_mlsb << SPI_CMD_TXMSBF_OFFSET); ++ reg_val |= (chip_config->rx_mlsb << SPI_CMD_RXMSBF_OFFSET); ++ reg_val |= (chip_config->tx_endian << SPI_CMD_TX_ENDIAN_OFFSET); ++ reg_val |= (chip_config->rx_endian << SPI_CMD_RX_ENDIAN_OFFSET); ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ ++ /* set finish and pause interrupt always enable */ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~SPI_CMD_FINISH_IE_MASK; ++ reg_val |= (chip_config->finish_intr << SPI_CMD_FINISH_IE_OFFSET); ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val |= 1 << SPI_CMD_TX_DMA_OFFSET; ++ reg_val |= 1 << SPI_CMD_RX_DMA_OFFSET; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ ++ /* set deassert mode */ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~SPI_CMD_DEASSERT_MASK; ++ reg_val |= (chip_config->deassert << SPI_CMD_DEASSERT_OFFSET); ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ ++ /* pad select */ ++ if (mdata->platform_compat & COMPAT_MT8173) ++ writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG); ++ ++ return 0; ++} ++ ++static int mtk_spi_setup_transfer(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ u32 reg_val; ++ struct spi_master *master = spi->master; ++ struct mtk_spi_ddata *mdata = spi_master_get_devdata(master); ++ struct spi_message *m = master->cur_msg; ++ struct mtk_chip_config *chip_config; ++ ++ u8 cpha = spi->mode & SPI_CPHA ? 1 : 0; ++ u8 cpol = spi->mode & SPI_CPOL ? 1 : 0; ++ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~(SPI_CMD_CPHA_MASK | SPI_CMD_CPOL_MASK); ++ reg_val |= (cpha << SPI_CMD_CPHA_OFFSET); ++ reg_val |= (cpol << SPI_CMD_CPOL_OFFSET); ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++ ++ if (t->cs_change) { ++ if (!(list_is_last(&t->transfer_list, &m->transfers))) ++ mdata->state = IDLE; ++ } else { ++ mdata->state = IDLE; ++ mtk_spi_reset(mdata); ++ } ++ ++ chip_config = (struct mtk_chip_config *)spi->controller_data; ++ if (!chip_config) { ++ chip_config = (void *)&mtk_default_chip_info; ++ spi->controller_data = chip_config; ++ mdata->state = IDLE; ++ } ++ ++ mtk_spi_config(mdata, chip_config); ++ ++ return 0; ++} ++ ++static void mtk_spi_chipselect(struct spi_device *spi, int is_on) ++{ ++ struct mtk_spi_ddata *mdata = spi_master_get_devdata(spi->master); ++ ++ switch (is_on) { ++ case BITBANG_CS_ACTIVE: ++ mtk_set_pause_bit(mdata); ++ break; ++ case BITBANG_CS_INACTIVE: ++ mtk_clear_pause_bit(mdata); ++ break; ++ } ++} ++ ++static void mtk_spi_start_transfer(struct mtk_spi_ddata *mdata) ++{ ++ u32 reg_val; ++ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val |= 1 << SPI_CMD_ACT_OFFSET; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++} ++ ++static void mtk_spi_resume_transfer(struct mtk_spi_ddata *mdata) ++{ ++ u32 reg_val; ++ ++ reg_val = readl(mdata->base + SPI_CMD_REG); ++ reg_val &= ~SPI_CMD_RESUME_MASK; ++ reg_val |= 1 << SPI_CMD_RESUME_OFFSET; ++ writel(reg_val, mdata->base + SPI_CMD_REG); ++} ++ ++static int mtk_spi_setup_packet(struct mtk_spi_ddata *mdata, ++ struct spi_transfer *xfer) ++{ ++ struct device *dev = &mdata->bitbang.master->dev; ++ u32 packet_size, packet_loop, reg_val; ++ ++ packet_size = min_t(unsigned, xfer->len, PACKET_SIZE); ++ ++ /* mtk hw has the restriction that xfer len must be a multiple of 1024, ++ * when it is greater than 1024bytes. ++ */ ++ if (xfer->len % packet_size) { ++ dev_err(dev, "ERROR!The lens must be a multiple of %d, your len %d\n", ++ PACKET_SIZE, xfer->len); ++ return -EINVAL; ++ } ++ ++ packet_loop = xfer->len / packet_size; ++ ++ reg_val = readl(mdata->base + SPI_CFG1_REG); ++ reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK + SPI_CFG1_PACKET_LOOP_MASK); ++ reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; ++ reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; ++ writel(reg_val, mdata->base + SPI_CFG1_REG); ++ ++ return 0; ++} ++ ++static int mtk_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *xfer) ++{ ++ struct spi_master *master = spi->master; ++ struct mtk_spi_ddata *mdata = spi_master_get_devdata(master); ++ struct device *dev = &mdata->bitbang.master->dev; ++ int cmd, ret; ++ ++ /* mtk spi hw tx/rx have 4bytes aligned restriction, ++ * so kmalloc tx/rx buffer to workaround here. ++ */ ++ mdata->tx_buf = NULL; ++ mdata->rx_buf = NULL; ++ if (xfer->tx_buf) { ++ mdata->tx_buf = kmalloc(xfer->len, GFP_KERNEL); ++ if (!mdata->tx_buf) { ++ dev_err(dev, "malloc tx_buf failed.\n"); ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ memcpy((void *)mdata->tx_buf, xfer->tx_buf, xfer->len); ++ } ++ if (xfer->rx_buf) { ++ mdata->rx_buf = kmalloc(xfer->len, GFP_KERNEL); ++ if (!mdata->rx_buf) { ++ dev_err(dev, "malloc rx_buf failed.\n"); ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ } ++ ++ reinit_completion(&mdata->done); ++ ++ xfer->tx_dma = DMA_ERROR_CODE; ++ xfer->rx_dma = DMA_ERROR_CODE; ++ if (xfer->tx_buf) { ++ xfer->tx_dma = dma_map_single(dev, (void *)mdata->tx_buf, ++ xfer->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(dev, xfer->tx_dma)) { ++ dev_err(dev, "dma mapping tx_buf error.\n"); ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ } ++ if (xfer->rx_buf) { ++ xfer->rx_dma = dma_map_single(dev, mdata->rx_buf, ++ xfer->len, DMA_FROM_DEVICE); ++ if (dma_mapping_error(dev, xfer->rx_dma)) { ++ if (xfer->tx_buf) ++ dma_unmap_single(dev, xfer->tx_dma, ++ xfer->len, DMA_TO_DEVICE); ++ dev_err(dev, "dma mapping rx_buf error.\n"); ++ ret = -ENOMEM; ++ goto err_free; ++ } ++ } ++ ++ ret = mtk_spi_setup_packet(mdata, xfer); ++ if (ret != 0) ++ goto err_free; ++ ++ /* Here is mt8173 HW issue: RX must enable TX, then TX transfer ++ * dummy data; TX don't need to enable RX. so enable TX dma for ++ * RX to workaround. ++ */ ++ cmd = readl(mdata->base + SPI_CMD_REG); ++ if (xfer->tx_buf || (mdata->platform_compat & COMPAT_MT8173)) ++ cmd |= 1 << SPI_CMD_TX_DMA_OFFSET; ++ if (xfer->rx_buf) ++ cmd |= 1 << SPI_CMD_RX_DMA_OFFSET; ++ writel(cmd, mdata->base + SPI_CMD_REG); ++ ++ /* set up the DMA bus address */ ++ if (xfer->tx_dma != DMA_ERROR_CODE) ++ writel(cpu_to_le32(xfer->tx_dma), mdata->base + SPI_TX_SRC_REG); ++ if (xfer->rx_dma != DMA_ERROR_CODE) ++ writel(cpu_to_le32(xfer->rx_dma), mdata->base + SPI_RX_DST_REG); ++ ++ if (mdata->state == IDLE) ++ mtk_spi_start_transfer(mdata); ++ else if (mdata->state == PAUSED) ++ mtk_spi_resume_transfer(mdata); ++ else ++ mdata->state = INPROGRESS; ++ ++ wait_for_completion(&mdata->done); ++ ++ if (xfer->tx_dma != DMA_ERROR_CODE) { ++ dma_unmap_single(dev, xfer->tx_dma, xfer->len, DMA_TO_DEVICE); ++ xfer->tx_dma = DMA_ERROR_CODE; ++ } ++ if (xfer->rx_dma != DMA_ERROR_CODE) { ++ dma_unmap_single(dev, xfer->rx_dma, xfer->len, DMA_FROM_DEVICE); ++ xfer->rx_dma = DMA_ERROR_CODE; ++ } ++ ++ /* spi disable dma */ ++ cmd = readl(mdata->base + SPI_CMD_REG); ++ cmd &= ~SPI_CMD_TX_DMA_MASK; ++ cmd &= ~SPI_CMD_RX_DMA_MASK; ++ writel(cmd, mdata->base + SPI_CMD_REG); ++ ++ if (xfer->rx_buf) ++ memcpy(xfer->rx_buf, mdata->rx_buf, xfer->len); ++ ++ ret = xfer->len; ++ ++err_free: ++ kfree(mdata->tx_buf); ++ kfree(mdata->rx_buf); ++ return ret; ++} ++ ++static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) ++{ ++ struct mtk_spi_ddata *mdata = dev_id; ++ u32 reg_val; ++ ++ reg_val = readl(mdata->base + SPI_STATUS0_REG); ++ if (reg_val & 0x2) ++ mdata->state = PAUSED; ++ else ++ mdata->state = IDLE; ++ complete(&mdata->done); ++ ++ return IRQ_HANDLED; ++} ++ ++static unsigned long mtk_get_device_prop(struct platform_device *pdev) ++{ ++ const struct of_device_id *match; ++ ++ match = of_match_node(mtk_spi_of_match, pdev->dev.of_node); ++ return (unsigned long)match->data; ++} ++ ++static int mtk_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct mtk_spi_ddata *mdata; ++ struct resource *res; ++ int ret; ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(struct mtk_spi_ddata)); ++ if (!master) { ++ dev_err(&pdev->dev, "failed to alloc spi master\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, master); ++ ++ master->dev.of_node = pdev->dev.of_node; ++ master->bus_num = pdev->id; ++ master->num_chipselect = 1; ++ master->mode_bits = SPI_CPOL | SPI_CPHA; ++ ++ mdata = spi_master_get_devdata(master); ++ ++ mdata->bitbang.master = master; ++ mdata->bitbang.chipselect = mtk_spi_chipselect; ++ mdata->bitbang.setup_transfer = mtk_spi_setup_transfer; ++ mdata->bitbang.txrx_bufs = mtk_spi_txrx_bufs; ++ mdata->platform_compat = mtk_get_device_prop(pdev); ++ ++ if (mdata->platform_compat & COMPAT_MT8173) { ++ ret = of_property_read_u32(pdev->dev.of_node, "pad-select", ++ &mdata->pad_sel); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to read pad select: %d\n", ++ ret); ++ goto err; ++ } ++ ++ if (mdata->pad_sel > MT8173_MAX_PAD_SEL) { ++ dev_err(&pdev->dev, "wrong pad-select: %u\n", ++ mdata->pad_sel); ++ goto err; ++ } ++ } ++ ++ init_completion(&mdata->done); ++ ++ mdata->clk = devm_clk_get(&pdev->dev, "main"); ++ if (IS_ERR(mdata->clk)) { ++ ret = PTR_ERR(mdata->clk); ++ dev_err(&pdev->dev, "failed to get clock: %d\n", ret); ++ goto err; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ ret = -ENODEV; ++ dev_err(&pdev->dev, "failed to determine base address\n"); ++ goto err; ++ } ++ ++ mdata->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(mdata->base)) { ++ ret = PTR_ERR(mdata->base); ++ goto err; ++ } ++ ++ ret = platform_get_irq(pdev, 0); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to get irq (%d)\n", ret); ++ goto err; ++ } ++ ++ mdata->irq = ret; ++ ++ if (!pdev->dev.dma_mask) ++ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; ++ ++ mdata->bitbang.master->dev.dma_mask = pdev->dev.dma_mask; ++ ++ ret = clk_prepare_enable(mdata->clk); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret); ++ goto err; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, mdata->irq, mtk_spi_interrupt, ++ IRQF_TRIGGER_NONE, dev_name(&pdev->dev), mdata); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); ++ goto err_disable_clk; ++ } ++ ++ ret = spi_bitbang_start(&mdata->bitbang); ++ if (ret) { ++ dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret); ++err_disable_clk: ++ clk_disable_unprepare(mdata->clk); ++err: ++ spi_master_put(master); ++ } ++ ++ return ret; ++} ++ ++static int mtk_spi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct mtk_spi_ddata *mdata = spi_master_get_devdata(master); ++ ++ spi_bitbang_stop(&mdata->bitbang); ++ mtk_spi_reset(mdata); ++ clk_disable_unprepare(mdata->clk); ++ spi_master_put(master); ++ ++ return 0; ++} ++ ++struct platform_driver mtk_spi_driver = { ++ .driver = { ++ .name = "mtk-spi", ++ .of_match_table = mtk_spi_of_match, ++ }, ++ .probe = mtk_spi_probe, ++ .remove = mtk_spi_remove, ++}; ++ ++module_platform_driver(mtk_spi_driver); ++ ++MODULE_DESCRIPTION("MTK SPI Controller driver"); ++MODULE_AUTHOR("Leilk Liu "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform: mtk_spi"); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch b/target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch new file mode 100644 index 0000000..1236a96 --- /dev/null +++ b/target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch @@ -0,0 +1,47 @@ +From 908a87b47af8303c9aa8fb6aa183ca9f8b544d78 Mon Sep 17 00:00:00 2001 +From: YH Huang +Date: Mon, 11 May 2015 17:26:21 +0800 +Subject: [PATCH 27/76] dt-bindings: pwm: add Mediatek display PWM bindings + +Document the device-tree binding of Mediatek display PWM. + +Signed-off-by: YH Huang +--- + .../devicetree/bindings/pwm/pwm-disp-mediatek.txt | 25 ++++++++++++++++++++ + 1 file changed, 25 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt + +diff --git a/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt +new file mode 100644 +index 0000000..ef54e9d +--- /dev/null ++++ b/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt +@@ -0,0 +1,25 @@ ++Mediatek display PWM controller ++ ++Required properties: ++ - compatible: should be "mediatek,-disp-pwm" ++ - "mediatek,mt8173-disp-pwm": found on mt8173 SoC ++ - "mediatek,mt6595-disp-pwm": found on mt6595 SoC ++ - reg: physical base address and length of the controller's registers ++ - #pwm-cells: must be 2. See pwm.txt in this directory ++ for a description of the cell format ++ - clocks: phandle and clock specifier of the PWM reference clock ++ - clock-names: must contain the following ++ - "main": clock used to generate PWM signals ++ - "mm": sync signals from the modules of mmsys ++ ++Example: ++ pwm0: pwm@1401e000 { ++ compatible = "mediatek,mt8173-disp-pwm", ++ "mediatek,mt6595-disp-pwm"; ++ reg = <0 0x1401e000 0 0x1000>; ++ #pwm-cells = <2>; ++ clocks = <&mmsys MM_DISP_PWM026M>, ++ <&mmsys MM_DISP_PWM0MM>; ++ clock-names = "main", ++ "mm"; ++ }; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0028-pwm-add-Mediatek-display-PWM-driver-support.patch b/target/linux/mediatek/patches/0028-pwm-add-Mediatek-display-PWM-driver-support.patch new file mode 100644 index 0000000..dbcca3e --- /dev/null +++ b/target/linux/mediatek/patches/0028-pwm-add-Mediatek-display-PWM-driver-support.patch @@ -0,0 +1,281 @@ +From 77e664940f6daa86965d16a2047188519341a31a Mon Sep 17 00:00:00 2001 +From: YH Huang +Date: Mon, 11 May 2015 17:26:22 +0800 +Subject: [PATCH 28/76] pwm: add Mediatek display PWM driver support + +Add display PWM driver support to modify backlight for MT8173/MT6595. + +Signed-off-by: YH Huang +--- + drivers/pwm/Kconfig | 9 ++ + drivers/pwm/Makefile | 1 + + drivers/pwm/pwm-disp-mediatek.c | 225 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 235 insertions(+) + create mode 100644 drivers/pwm/pwm-disp-mediatek.c + +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index b1541f4..9edbb5a 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -111,6 +111,15 @@ config PWM_CLPS711X + To compile this driver as a module, choose M here: the module + will be called pwm-clps711x. + ++config PWM_DISP_MEDIATEK ++ tristate "MEDIATEK display PWM driver" ++ depends on OF ++ help ++ Generic PWM framework driver for mediatek disp-pwm device. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called pwm-disp-mediatek. ++ + config PWM_EP93XX + tristate "Cirrus Logic EP93xx PWM support" + depends on ARCH_EP93XX +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index ec50eb5..c5ff72a 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o + obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o + obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o + obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o ++obj-$(CONFIG_PWM_DISP_MEDIATEK) += pwm-disp-mediatek.o + obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o + obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o + obj-$(CONFIG_PWM_IMG) += pwm-img.o +diff --git a/drivers/pwm/pwm-disp-mediatek.c b/drivers/pwm/pwm-disp-mediatek.c +new file mode 100644 +index 0000000..38293af +--- /dev/null ++++ b/drivers/pwm/pwm-disp-mediatek.c +@@ -0,0 +1,225 @@ ++/* ++ * Mediatek display pulse-width-modulation controller driver. ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: YH Huang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DISP_PWM_EN_OFF (0x0) ++#define PWM_ENABLE_SHIFT (0x0) ++#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) ++ ++#define DISP_PWM_COMMIT_OFF (0x08) ++#define PWM_COMMIT_SHIFT (0x0) ++#define PWM_COMMIT_MASK (0x1 << PWM_COMMIT_SHIFT) ++ ++#define DISP_PWM_CON_0_OFF (0x10) ++#define PWM_CLKDIV_SHIFT (0x10) ++#define PWM_CLKDIV_MASK (0x3ff << PWM_CLKDIV_SHIFT) ++#define PWM_CLKDIV_MAX (0x000003ff) ++ ++#define DISP_PWM_CON_1_OFF (0x14) ++#define PWM_PERIOD_SHIFT (0x0) ++#define PWM_PERIOD_MASK (0xfff << PWM_PERIOD_SHIFT) ++#define PWM_PERIOD_MAX (0x00000fff) ++/* Shift log2(PWM_PERIOD_MAX + 1) as divisor */ ++#define PWM_PERIOD_BIT_SHIFT 12 ++ ++#define PWM_HIGH_WIDTH_SHIFT (0x10) ++#define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT) ++ ++#define NUM_PWM 1 ++ ++struct mtk_disp_pwm_chip { ++ struct pwm_chip chip; ++ struct device *dev; ++ struct clk *clk_main; ++ struct clk *clk_mm; ++ void __iomem *mmio_base; ++}; ++ ++static void mtk_disp_pwm_setting(void __iomem *address, u32 value, u32 mask) ++{ ++ u32 val; ++ ++ val = readl(address); ++ val &= ~mask; ++ val |= value; ++ writel(val, address); ++} ++ ++static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, ++ int duty_ns, int period_ns) ++{ ++ struct mtk_disp_pwm_chip *mpc; ++ u64 div, rate; ++ u32 clk_div, period, high_width, rem; ++ ++ /* ++ * Find period, high_width and clk_div to suit duty_ns and period_ns. ++ * Calculate proper div value to keep period value in the bound. ++ * ++ * period_ns = 10^9 * (clk_div + 1) * (period +1) / PWM_CLK_RATE ++ * duty_ns = 10^9 * (clk_div + 1) * (high_width + 1) / PWM_CLK_RATE ++ * ++ * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 ++ * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) - 1 ++ */ ++ mpc = container_of(chip, struct mtk_disp_pwm_chip, chip); ++ rate = clk_get_rate(mpc->clk_main); ++ clk_div = div_u64_rem(rate * period_ns, NSEC_PER_SEC, &rem) >> ++ PWM_PERIOD_BIT_SHIFT; ++ if (clk_div > PWM_CLKDIV_MAX) ++ return -EINVAL; ++ ++ div = clk_div + 1; ++ period = div64_u64(rate * period_ns, NSEC_PER_SEC * div); ++ if (period > 0) ++ period--; ++ high_width = div64_u64(rate * duty_ns, NSEC_PER_SEC * div); ++ if (high_width > 0) ++ high_width--; ++ ++ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_CON_0_OFF, ++ clk_div << PWM_CLKDIV_SHIFT, PWM_CLKDIV_MASK); ++ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_CON_1_OFF, ++ (period << PWM_PERIOD_SHIFT) | ++ (high_width << PWM_HIGH_WIDTH_SHIFT), ++ PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK); ++ ++ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_COMMIT_OFF, ++ 1 << PWM_COMMIT_SHIFT, PWM_COMMIT_MASK); ++ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_COMMIT_OFF, ++ 0 << PWM_COMMIT_SHIFT, PWM_COMMIT_MASK); ++ ++ return 0; ++} ++ ++static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mtk_disp_pwm_chip *mpc; ++ ++ mpc = container_of(chip, struct mtk_disp_pwm_chip, chip); ++ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_EN_OFF, ++ 1 << PWM_ENABLE_SHIFT, PWM_ENABLE_MASK); ++ ++ return 0; ++} ++ ++static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mtk_disp_pwm_chip *mpc; ++ ++ mpc = container_of(chip, struct mtk_disp_pwm_chip, chip); ++ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_EN_OFF, ++ 0 << PWM_ENABLE_SHIFT, PWM_ENABLE_MASK); ++} ++ ++static const struct pwm_ops mtk_disp_pwm_ops = { ++ .config = mtk_disp_pwm_config, ++ .enable = mtk_disp_pwm_enable, ++ .disable = mtk_disp_pwm_disable, ++ .owner = THIS_MODULE, ++}; ++ ++static int mtk_disp_pwm_probe(struct platform_device *pdev) ++{ ++ struct mtk_disp_pwm_chip *pwm; ++ struct resource *r; ++ int ret; ++ ++ pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); ++ if (!pwm) ++ return -ENOMEM; ++ ++ pwm->dev = &pdev->dev; ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r); ++ if (IS_ERR(pwm->mmio_base)) ++ return PTR_ERR(pwm->mmio_base); ++ ++ pwm->clk_main = devm_clk_get(&pdev->dev, "main"); ++ if (IS_ERR(pwm->clk_main)) ++ return PTR_ERR(pwm->clk_main); ++ pwm->clk_mm = devm_clk_get(&pdev->dev, "mm"); ++ if (IS_ERR(pwm->clk_mm)) ++ return PTR_ERR(pwm->clk_mm); ++ ++ ret = clk_prepare_enable(pwm->clk_main); ++ if (ret < 0) ++ return ret; ++ ret = clk_prepare_enable(pwm->clk_mm); ++ if (ret < 0) { ++ clk_disable_unprepare(pwm->clk_main); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, pwm); ++ ++ pwm->chip.dev = &pdev->dev; ++ pwm->chip.ops = &mtk_disp_pwm_ops; ++ pwm->chip.base = -1; ++ pwm->chip.npwm = NUM_PWM; ++ ++ ret = pwmchip_add(&pwm->chip); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int mtk_disp_pwm_remove(struct platform_device *pdev) ++{ ++ struct mtk_disp_pwm_chip *pc = platform_get_drvdata(pdev); ++ ++ if (WARN_ON(!pc)) ++ return -ENODEV; ++ ++ clk_disable_unprepare(pc->clk_main); ++ clk_disable_unprepare(pc->clk_mm); ++ ++ return pwmchip_remove(&pc->chip); ++} ++ ++static const struct of_device_id mtk_disp_pwm_of_match[] = { ++ { .compatible = "mediatek,mt6595-disp-pwm" }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match); ++ ++static struct platform_driver mtk_disp_pwm_driver = { ++ .driver = { ++ .name = "mediatek-disp-pwm", ++ .owner = THIS_MODULE, ++ .of_match_table = mtk_disp_pwm_of_match, ++ }, ++ .probe = mtk_disp_pwm_probe, ++ .remove = mtk_disp_pwm_remove, ++}; ++ ++module_platform_driver(mtk_disp_pwm_driver); ++ ++MODULE_AUTHOR("YH Huang "); ++MODULE_DESCRIPTION("MediaTek SoC display PWM driver"); ++MODULE_LICENSE("GPL v2"); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0029-dt-bindings-Add-I2C-bindings-for-mt65xx-mt81xx.patch b/target/linux/mediatek/patches/0029-dt-bindings-Add-I2C-bindings-for-mt65xx-mt81xx.patch new file mode 100644 index 0000000..03f03fb --- /dev/null +++ b/target/linux/mediatek/patches/0029-dt-bindings-Add-I2C-bindings-for-mt65xx-mt81xx.patch @@ -0,0 +1,64 @@ +From d1447a6815913823ef5e75d70efc6f08f288ee40 Mon Sep 17 00:00:00 2001 +From: Xudong Chen +Date: Wed, 6 May 2015 16:37:05 +0800 +Subject: [PATCH 29/76] dt-bindings: Add I2C bindings for mt65xx/mt81xx. + +Add devicetree bindings for Mediatek Soc I2C driver. + +Signed-off-by: Xudong Chen +Signed-off-by: Eddie Huang +--- + .../devicetree/bindings/i2c/i2c-mt6577.txt | 41 ++++++++++++++++++++ + 1 file changed, 41 insertions(+) + create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt + +diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt +new file mode 100644 +index 0000000..0ce6fa3 +--- /dev/null ++++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt +@@ -0,0 +1,41 @@ ++* Mediatek's I2C controller ++ ++The Mediatek's I2C controller is used to interface with I2C devices. ++ ++Required properties: ++ - compatible: value should be either of the following. ++ (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c. ++ (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c. ++ (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c. ++ (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c. ++ (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c. ++ - reg: physical base address of the controller and dma base, length of memory ++ mapped region. ++ - interrupts: interrupt number to the cpu. ++ - clock-div: the fixed value for frequency divider of clock source in i2c ++ module. Each IC may be different. ++ - clocks: clock name from clock manager ++ - clock-names: Must include "main" and "dma", if enable have-pmic need include ++ "pmic" extra. ++ ++Optional properties: ++ - clock-frequency: Frequency in Hz of the bus when transfer, the default value ++ is 100000. ++ - mediatek,have-pmic: platform can control i2c form special pmic side. ++ Only mt6589 and mt8135 support this feature. ++ - mediatek,use-push-pull: IO config use push-pull mode. ++ ++Example: ++ ++ i2c0: i2c@1100d000 { ++ compatible = "mediatek,mt6577-i2c"; ++ reg = <0x1100d000 0x70>, ++ <0x11000300 0x80>; ++ interrupts = ; ++ clock-frequency = <400000>; ++ mediatek,have-pmic; ++ clock-div = <16>; ++ clocks = <&i2c0_ck>, <&ap_dma_ck>; ++ clock-names = "main", "dma"; ++ }; ++ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0030-I2C-mediatek-Add-driver-for-MediaTek-I2C-controller.patch b/target/linux/mediatek/patches/0030-I2C-mediatek-Add-driver-for-MediaTek-I2C-controller.patch new file mode 100644 index 0000000..df22f08 --- /dev/null +++ b/target/linux/mediatek/patches/0030-I2C-mediatek-Add-driver-for-MediaTek-I2C-controller.patch @@ -0,0 +1,760 @@ +From 2471bc43c6079ab956a04f29ffd1ab8371b7bd73 Mon Sep 17 00:00:00 2001 +From: Xudong Chen +Date: Wed, 6 May 2015 16:37:06 +0800 +Subject: [PATCH 30/76] I2C: mediatek: Add driver for MediaTek I2C controller + +The mediatek SoCs have I2C controller that handle I2C transfer. +This patch include common I2C bus driver. +This driver is compatible with I2C controller on mt65xx/mt81xx. + +Signed-off-by: Xudong Chen +Signed-off-by: Liguo Zhang +Signed-off-by: Eddie Huang +--- + drivers/i2c/busses/Kconfig | 9 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-mt65xx.c | 700 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 710 insertions(+) + create mode 100644 drivers/i2c/busses/i2c-mt65xx.c + +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 2255af2..14c7266 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -620,6 +620,15 @@ config I2C_MPC + This driver can also be built as a module. If so, the module + will be called i2c-mpc. + ++config I2C_MT65XX ++ tristate "MediaTek I2C adapter" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ help ++ This selects the MediaTek(R) Integrated Inter Circuit bus driver ++ for MT65xx and MT81xx. ++ If you want to use MediaTek(R) I2C interface, say Y or M here. ++ If unsure, say N. ++ + config I2C_MV64XXX + tristate "Marvell mv64xxx I2C Controller" + depends on MV64X60 || PLAT_ORION || ARCH_SUNXI +diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile +index cdf941d..abbf422 100644 +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -60,6 +60,7 @@ obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o + obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o + obj-$(CONFIG_I2C_MESON) += i2c-meson.o + obj-$(CONFIG_I2C_MPC) += i2c-mpc.o ++obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o + obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o + obj-$(CONFIG_I2C_MXS) += i2c-mxs.o + obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o +diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c +new file mode 100644 +index 0000000..faecf7e +--- /dev/null ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -0,0 +1,700 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Xudong.chen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define I2C_HS_NACKERR (1 << 2) ++#define I2C_ACKERR (1 << 1) ++#define I2C_TRANSAC_COMP (1 << 0) ++#define I2C_TRANSAC_START (1 << 0) ++#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0) ++#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0) ++#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8) ++#define I2C_TIMING_DATA_READ_MASK (0x7 << 12) ++#define I2C_DCM_DISABLE 0x0000 ++#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 ++#define I2C_IO_CONFIG_PUSH_PULL 0x0000 ++#define I2C_SOFT_RST 0x0001 ++#define I2C_FIFO_ADDR_CLR 0x0001 ++#define I2C_DELAY_LEN 0x0002 ++#define I2C_ST_START_CON 0x8001 ++#define I2C_FS_START_CON 0x1800 ++#define I2C_TIME_CLR_VALUE 0x0000 ++#define I2C_TIME_DEFAULT_VALUE 0x0003 ++#define I2C_FS_TIME_INIT_VALUE 0x1303 ++#define I2C_WRRD_TRANAC_VALUE 0x0002 ++#define I2C_RD_TRANAC_VALUE 0x0001 ++ ++#define I2C_DMA_CON_TX 0x0000 ++#define I2C_DMA_CON_RX 0x0001 ++#define I2C_DMA_START_EN 0x0001 ++#define I2C_DMA_INT_FLAG_NONE 0x0000 ++#define I2C_DMA_CLR_FLAG 0x0000 ++ ++#define I2C_DEFAUT_SPEED 100000 /* hz */ ++#define MAX_FS_MODE_SPEED 400000 ++#define MAX_HS_MODE_SPEED 3400000 ++#define MAX_MSG_NUM_MT6577 1 ++#define MAX_DMA_TRANS_SIZE_MT6577 255 ++#define MAX_WRRD_TRANS_SIZE_MT6577 31 ++#define MAX_SAMPLE_CNT_DIV 8 ++#define MAX_STEP_CNT_DIV 64 ++#define MAX_HS_STEP_CNT_DIV 8 ++ ++#define I2C_CONTROL_RS (0x1 << 1) ++#define I2C_CONTROL_DMA_EN (0x1 << 2) ++#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3) ++#define I2C_CONTROL_DIR_CHANGE (0x1 << 4) ++#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5) ++#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6) ++#define I2C_CONTROL_WRAPPER (0x1 << 0) ++ ++#define I2C_DRV_NAME "mt-i2c" ++ ++enum DMA_REGS_OFFSET { ++ OFFSET_INT_FLAG = 0x0, ++ OFFSET_INT_EN = 0x04, ++ OFFSET_EN = 0x08, ++ OFFSET_CON = 0x18, ++ OFFSET_TX_MEM_ADDR = 0x1c, ++ OFFSET_RX_MEM_ADDR = 0x20, ++ OFFSET_TX_LEN = 0x24, ++ OFFSET_RX_LEN = 0x28, ++}; ++ ++enum i2c_trans_st_rs { ++ I2C_TRANS_STOP = 0, ++ I2C_TRANS_REPEATED_START, ++}; ++ ++enum mtk_trans_op { ++ I2C_MASTER_WR = 1, ++ I2C_MASTER_RD, ++ I2C_MASTER_WRRD, ++}; ++ ++enum I2C_REGS_OFFSET { ++ OFFSET_DATA_PORT = 0x0, ++ OFFSET_SLAVE_ADDR = 0x04, ++ OFFSET_INTR_MASK = 0x08, ++ OFFSET_INTR_STAT = 0x0c, ++ OFFSET_CONTROL = 0x10, ++ OFFSET_TRANSFER_LEN = 0x14, ++ OFFSET_TRANSAC_LEN = 0x18, ++ OFFSET_DELAY_LEN = 0x1c, ++ OFFSET_TIMING = 0x20, ++ OFFSET_START = 0x24, ++ OFFSET_EXT_CONF = 0x28, ++ OFFSET_FIFO_STAT = 0x30, ++ OFFSET_FIFO_THRESH = 0x34, ++ OFFSET_FIFO_ADDR_CLR = 0x38, ++ OFFSET_IO_CONFIG = 0x40, ++ OFFSET_RSV_DEBUG = 0x44, ++ OFFSET_HS = 0x48, ++ OFFSET_SOFTRESET = 0x50, ++ OFFSET_DCM_EN = 0x54, ++ OFFSET_PATH_DIR = 0x60, ++ OFFSET_DEBUGSTAT = 0x64, ++ OFFSET_DEBUGCTRL = 0x68, ++ OFFSET_TRANSFER_LEN_AUX = 0x6c, ++}; ++ ++struct mtk_i2c_data { ++ unsigned int clk_frequency; /* bus speed in Hz */ ++ unsigned int flags; ++ unsigned int clk_src_div; ++}; ++ ++struct mtk_i2c_compatible { ++ const struct i2c_adapter_quirks *quirks; ++ unsigned char pmic_i2c; ++ unsigned char dcm; ++}; ++ ++struct mtk_i2c { ++ struct i2c_adapter adap; /* i2c host adapter */ ++ struct device *dev; ++ struct completion msg_complete; ++ ++ /* set in i2c probe */ ++ void __iomem *base; /* i2c base addr */ ++ void __iomem *pdmabase; /* dma base address*/ ++ struct clk *clk_main; /* main clock for i2c bus */ ++ struct clk *clk_dma; /* DMA clock for i2c via DMA */ ++ struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */ ++ bool have_pmic; /* can use i2c pins from PMIC */ ++ bool use_push_pull; /* IO config push-pull mode */ ++ ++ u16 irq_stat; /* interrupt status */ ++ unsigned int speed_hz; /* The speed in transfer */ ++ enum mtk_trans_op op; ++ u16 timing_reg; ++ u16 high_speed_reg; ++ const struct mtk_i2c_compatible *dev_comp; ++}; ++ ++static const struct i2c_adapter_quirks mt6577_i2c_quirks = { ++ .flags = I2C_AQ_COMB_WRITE_THEN_READ, ++ .max_num_msgs = MAX_MSG_NUM_MT6577, ++ .max_write_len = MAX_DMA_TRANS_SIZE_MT6577, ++ .max_read_len = MAX_DMA_TRANS_SIZE_MT6577, ++ .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT6577, ++ .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577, ++}; ++ ++static const struct mtk_i2c_compatible mt6577_compat = { ++ .quirks = &mt6577_i2c_quirks, ++ .pmic_i2c = 0, ++ .dcm = 1, ++}; ++ ++static const struct mtk_i2c_compatible mt6589_compat = { ++ .quirks = &mt6577_i2c_quirks, ++ .pmic_i2c = 1, ++ .dcm = 0, ++}; ++ ++static const struct of_device_id mtk_i2c_of_match[] = { ++ { .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat }, ++ { .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); ++ ++static inline void mtk_i2c_writew(u16 value, struct mtk_i2c *i2c, u8 offset) ++{ ++ writew(value, i2c->base + offset); ++} ++ ++static inline u16 mtk_i2c_readw(struct mtk_i2c *i2c, u8 offset) ++{ ++ return readw(i2c->base + offset); ++} ++ ++static inline void mtk_i2c_writel_dma(u32 value, struct mtk_i2c *i2c, u8 offset) ++{ ++ writel(value, i2c->pdmabase + offset); ++} ++ ++static int mtk_i2c_clock_enable(struct mtk_i2c *i2c) ++{ ++ int ret; ++ ++ ret = clk_prepare_enable(i2c->clk_dma); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(i2c->clk_main); ++ if (ret) ++ goto err_main; ++ ++ if (i2c->have_pmic) { ++ ret = clk_prepare_enable(i2c->clk_pmic); ++ if (ret) ++ goto err_pmic; ++ } ++ return 0; ++ ++err_pmic: ++ clk_disable_unprepare(i2c->clk_main); ++err_main: ++ clk_disable_unprepare(i2c->clk_dma); ++ ++ return ret; ++} ++ ++static void mtk_i2c_clock_disable(struct mtk_i2c *i2c) ++{ ++ if (i2c->have_pmic) ++ clk_disable_unprepare(i2c->clk_pmic); ++ ++ clk_disable_unprepare(i2c->clk_main); ++ clk_disable_unprepare(i2c->clk_dma); ++} ++ ++static void mtk_i2c_init_hw(struct mtk_i2c *i2c) ++{ ++ u16 control_reg; ++ ++ mtk_i2c_writew(I2C_SOFT_RST, i2c, OFFSET_SOFTRESET); ++ /* Set ioconfig */ ++ if (i2c->use_push_pull) ++ mtk_i2c_writew(I2C_IO_CONFIG_PUSH_PULL, i2c, OFFSET_IO_CONFIG); ++ else ++ mtk_i2c_writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c, OFFSET_IO_CONFIG); ++ ++ if (i2c->dev_comp->dcm) ++ mtk_i2c_writew(I2C_DCM_DISABLE, i2c, OFFSET_DCM_EN); ++ ++ mtk_i2c_writew(i2c->timing_reg, i2c, OFFSET_TIMING); ++ mtk_i2c_writew(i2c->high_speed_reg, i2c, OFFSET_HS); ++ ++ /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ ++ if (i2c->have_pmic) ++ mtk_i2c_writew(I2C_CONTROL_WRAPPER, i2c, OFFSET_PATH_DIR); ++ ++ control_reg = I2C_CONTROL_ACKERR_DET_EN | ++ I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; ++ mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL); ++ mtk_i2c_writew(I2C_DELAY_LEN, i2c, OFFSET_DELAY_LEN); ++} ++ ++/* calculate i2c port speed */ ++static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int clk_src_in_hz) ++{ ++ unsigned int khz; ++ unsigned int step_cnt; ++ unsigned int sample_cnt; ++ unsigned int sclk; ++ unsigned int hclk; ++ unsigned int max_step_cnt; ++ unsigned int sample_div = MAX_SAMPLE_CNT_DIV; ++ unsigned int step_div; ++ unsigned int min_div; ++ unsigned int best_mul; ++ unsigned int cnt_mul; ++ ++ if (i2c->speed_hz > MAX_HS_MODE_SPEED) ++ return -EINVAL; ++ else if (i2c->speed_hz > MAX_FS_MODE_SPEED) ++ max_step_cnt = MAX_HS_STEP_CNT_DIV; ++ else ++ max_step_cnt = MAX_STEP_CNT_DIV; ++ ++ step_div = max_step_cnt; ++ /* Find the best combination */ ++ khz = i2c->speed_hz / 1000; ++ hclk = clk_src_in_hz / 1000; ++ min_div = ((hclk >> 1) + khz - 1) / khz; ++ best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt; ++ ++ for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) { ++ step_cnt = (min_div + sample_cnt - 1) / sample_cnt; ++ cnt_mul = step_cnt * sample_cnt; ++ if (step_cnt > max_step_cnt) ++ continue; ++ ++ if (cnt_mul < best_mul) { ++ best_mul = cnt_mul; ++ sample_div = sample_cnt; ++ step_div = step_cnt; ++ if (best_mul == min_div) ++ break; ++ } ++ } ++ ++ sample_cnt = sample_div; ++ step_cnt = step_div; ++ sclk = hclk / (2 * sample_cnt * step_cnt); ++ if (sclk > khz) { ++ dev_dbg(i2c->dev, "%s mode: unsupported speed (%ldkhz)\n", ++ (i2c->speed_hz > MAX_HS_MODE_SPEED) ? "HS" : "ST/FT", ++ (long int)khz); ++ return -ENOTSUPP; ++ } ++ ++ step_cnt--; ++ sample_cnt--; ++ ++ if (i2c->speed_hz > MAX_FS_MODE_SPEED) { ++ /* Set the hign speed mode register */ ++ i2c->timing_reg = I2C_FS_TIME_INIT_VALUE; ++ i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE | ++ (sample_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 12 | ++ (step_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 8; ++ } else { ++ i2c->timing_reg = ++ (sample_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 8 | ++ (step_cnt & I2C_TIMING_STEP_DIV_MASK) << 0; ++ /* Disable the high speed transaction */ ++ i2c->high_speed_reg = I2C_TIME_CLR_VALUE; ++ } ++ ++ return 0; ++} ++ ++static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs) ++{ ++ u16 addr_reg; ++ u16 control_reg; ++ dma_addr_t rpaddr = 0; ++ dma_addr_t wpaddr = 0; ++ int ret; ++ ++ i2c->irq_stat = 0; ++ ++ reinit_completion(&i2c->msg_complete); ++ ++ control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) & ++ ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS); ++ if (i2c->speed_hz > 400000) ++ control_reg |= I2C_CONTROL_RS; ++ if (i2c->op == I2C_MASTER_WRRD) ++ control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; ++ mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL); ++ ++ /* set start condition */ ++ if (i2c->speed_hz <= 100000) ++ mtk_i2c_writew(I2C_ST_START_CON, i2c, OFFSET_EXT_CONF); ++ else ++ mtk_i2c_writew(I2C_FS_START_CON, i2c, OFFSET_EXT_CONF); ++ ++ addr_reg = msgs->addr << 1; ++ if (i2c->op == I2C_MASTER_RD) ++ addr_reg |= 0x1; ++ mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR); ++ ++ /* Clear interrupt status */ ++ mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP, ++ i2c, OFFSET_INTR_STAT); ++ mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR); ++ ++ /* Enable interrupt */ ++ mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP, ++ i2c, OFFSET_INTR_MASK); ++ ++ /* Set transfer and transaction len */ ++ if (i2c->op == I2C_MASTER_WRRD) { ++ mtk_i2c_writew(msgs->len | ((msgs + 1)->len) << 8, ++ i2c, OFFSET_TRANSFER_LEN); ++ mtk_i2c_writew(I2C_WRRD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN); ++ } else { ++ mtk_i2c_writew(msgs->len, i2c, OFFSET_TRANSFER_LEN); ++ mtk_i2c_writew(I2C_RD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN); ++ } ++ ++ /* Prepare buffer data to start transfer */ ++ if (i2c->op == I2C_MASTER_RD) { ++ mtk_i2c_writel_dma(I2C_DMA_INT_FLAG_NONE, i2c, OFFSET_INT_FLAG); ++ mtk_i2c_writel_dma(I2C_DMA_CON_RX, i2c, OFFSET_CON); ++ rpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf, ++ msgs->len, DMA_FROM_DEVICE); ++ if (dma_mapping_error(i2c->adap.dev.parent, rpaddr)) ++ return -ENOMEM; ++ mtk_i2c_writel_dma((u32)rpaddr, i2c, OFFSET_RX_MEM_ADDR); ++ mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_RX_LEN); ++ } else if (i2c->op == I2C_MASTER_WR) { ++ mtk_i2c_writel_dma(I2C_DMA_INT_FLAG_NONE, i2c, OFFSET_INT_FLAG); ++ mtk_i2c_writel_dma(I2C_DMA_CON_TX, i2c, OFFSET_CON); ++ wpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf, ++ msgs->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(i2c->adap.dev.parent, wpaddr)) ++ return -ENOMEM; ++ mtk_i2c_writel_dma((u32)wpaddr, i2c, OFFSET_TX_MEM_ADDR); ++ mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_TX_LEN); ++ } else { ++ mtk_i2c_writel_dma(I2C_DMA_CLR_FLAG, i2c, OFFSET_INT_FLAG); ++ mtk_i2c_writel_dma(I2C_DMA_CLR_FLAG, i2c, OFFSET_CON); ++ wpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf, ++ msgs->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(i2c->adap.dev.parent, wpaddr)) ++ return -ENOMEM; ++ rpaddr = dma_map_single(i2c->adap.dev.parent, (msgs + 1)->buf, ++ (msgs + 1)->len, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(i2c->adap.dev.parent, rpaddr)) { ++ dma_unmap_single(i2c->adap.dev.parent, wpaddr, ++ msgs->len, DMA_TO_DEVICE); ++ return -ENOMEM; ++ } ++ mtk_i2c_writel_dma((u32)wpaddr, i2c, OFFSET_TX_MEM_ADDR); ++ mtk_i2c_writel_dma((u32)rpaddr, i2c, OFFSET_RX_MEM_ADDR); ++ mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_TX_LEN); ++ mtk_i2c_writel_dma((msgs + 1)->len, i2c, OFFSET_RX_LEN); ++ } ++ ++ /* flush before sending start */ ++ mb(); ++ mtk_i2c_writel_dma(I2C_DMA_START_EN, i2c, OFFSET_EN); ++ mtk_i2c_writew(I2C_TRANSAC_START, i2c, OFFSET_START); ++ ++ ret = wait_for_completion_timeout(&i2c->msg_complete, ++ i2c->adap.timeout); ++ ++ /* Clear interrupt mask */ ++ mtk_i2c_writew(~(I2C_HS_NACKERR | I2C_ACKERR ++ | I2C_TRANSAC_COMP), i2c, OFFSET_INTR_MASK); ++ ++ if (i2c->op == I2C_MASTER_WR) { ++ dma_unmap_single(i2c->adap.dev.parent, wpaddr, ++ msgs->len, DMA_TO_DEVICE); ++ } else if (i2c->op == I2C_MASTER_RD) { ++ dma_unmap_single(i2c->adap.dev.parent, rpaddr, ++ msgs->len, DMA_FROM_DEVICE); ++ } else { ++ dma_unmap_single(i2c->adap.dev.parent, wpaddr, msgs->len, ++ DMA_TO_DEVICE); ++ dma_unmap_single(i2c->adap.dev.parent, rpaddr, (msgs + 1)->len, ++ DMA_FROM_DEVICE); ++ } ++ ++ if (ret == 0) { ++ dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr); ++ mtk_i2c_init_hw(i2c); ++ return -ETIMEDOUT; ++ } ++ ++ completion_done(&i2c->msg_complete); ++ ++ if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) { ++ dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr); ++ mtk_i2c_init_hw(i2c); ++ return -EREMOTEIO; ++ } ++ ++ return 0; ++} ++ ++static int mtk_i2c_transfer(struct i2c_adapter *adap, ++ struct i2c_msg msgs[], int num) ++{ ++ int ret; ++ int left_num = num; ++ struct mtk_i2c *i2c = i2c_get_adapdata(adap); ++ ++ ret = mtk_i2c_clock_enable(i2c); ++ if (ret) ++ return ret; ++ ++ if (msgs->buf == NULL) { ++ dev_dbg(i2c->dev, "data buffer is NULL.\n"); ++ ret = -EINVAL; ++ goto err_exit; ++ } ++ ++ if (msgs->flags & I2C_M_RD) ++ i2c->op = I2C_MASTER_RD; ++ else ++ i2c->op = I2C_MASTER_WR; ++ ++ if (num > 1) { ++ /* combined two messages into one transaction */ ++ i2c->op = I2C_MASTER_WRRD; ++ left_num--; ++ } ++ ++ /* always use DMA mode. */ ++ ret = mtk_i2c_do_transfer(i2c, msgs); ++ if (ret < 0) ++ goto err_exit; ++ ++ /* the return value is number of executed messages */ ++ ret = num; ++ ++err_exit: ++ mtk_i2c_clock_disable(i2c); ++ return ret; ++} ++ ++static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) ++{ ++ struct mtk_i2c *i2c = dev_id; ++ ++ i2c->irq_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); ++ mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR ++ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT); ++ ++ complete(&i2c->msg_complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 mtk_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; ++} ++ ++static const struct i2c_algorithm mtk_i2c_algorithm = { ++ .master_xfer = mtk_i2c_transfer, ++ .functionality = mtk_i2c_functionality, ++}; ++ ++static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c, ++ unsigned int *clk_src_div) ++{ ++ int ret; ++ ++ ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz); ++ if (ret < 0) ++ i2c->speed_hz = I2C_DEFAUT_SPEED; ++ ++ ret = of_property_read_u32(np, "clock-div", clk_src_div); ++ if (ret < 0) ++ return ret; ++ ++ if (*clk_src_div == 0) ++ return -EINVAL; ++ ++ i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic"); ++ i2c->use_push_pull = ++ of_property_read_bool(np, "mediatek,use-push-pull"); ++ ++ return 0; ++} ++ ++static int mtk_i2c_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *of_id; ++ int ret = 0; ++ struct mtk_i2c *i2c; ++ struct clk *clk; ++ unsigned int clk_src_in_hz; ++ unsigned int clk_src_div; ++ struct resource *res; ++ int irq; ++ ++ i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); ++ if (i2c == NULL) ++ return -ENOMEM; ++ ++ ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div); ++ if (ret) ++ return -EINVAL; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ i2c->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(i2c->base)) ++ return PTR_ERR(i2c->base); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(i2c->pdmabase)) ++ return PTR_ERR(i2c->pdmabase); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq <= 0) ++ return irq; ++ ++ init_completion(&i2c->msg_complete); ++ ++ of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node); ++ if (!of_id) ++ return -EINVAL; ++ ++ i2c->dev_comp = of_id->data; ++ i2c->adap.dev.of_node = pdev->dev.of_node; ++ i2c->dev = &i2c->adap.dev; ++ i2c->adap.dev.parent = &pdev->dev; ++ i2c->adap.owner = THIS_MODULE; ++ i2c->adap.algo = &mtk_i2c_algorithm; ++ i2c->adap.quirks = i2c->dev_comp->quirks; ++ i2c->adap.timeout = 2 * HZ; ++ i2c->adap.retries = 1; ++ ++ if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c) ++ return -EINVAL; ++ ++ i2c->clk_main = devm_clk_get(&pdev->dev, "main"); ++ if (IS_ERR(i2c->clk_main)) { ++ dev_err(&pdev->dev, "cannot get main clock\n"); ++ return PTR_ERR(i2c->clk_main); ++ } ++ ++ i2c->clk_dma = devm_clk_get(&pdev->dev, "dma"); ++ if (IS_ERR(i2c->clk_dma)) { ++ dev_err(&pdev->dev, "cannot get dma clock\n"); ++ return PTR_ERR(i2c->clk_dma); ++ } ++ ++ clk = i2c->clk_main; ++ if (i2c->have_pmic) { ++ i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic"); ++ if (IS_ERR(i2c->clk_pmic)) { ++ dev_err(&pdev->dev, "cannot get pmic clock\n"); ++ return PTR_ERR(i2c->clk_pmic); ++ } ++ clk = i2c->clk_pmic; ++ } ++ clk_src_in_hz = clk_get_rate(clk) / clk_src_div; ++ ++ dev_dbg(&pdev->dev, "clock source %p,clock src frequency %d\n", ++ i2c->clk_main, clk_src_in_hz); ++ strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name)); ++ ++ ret = mtk_i2c_set_speed(i2c, clk_src_in_hz); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to set the speed.\n"); ++ return -EINVAL; ++ } ++ ++ ret = mtk_i2c_clock_enable(i2c); ++ if (ret) { ++ dev_err(&pdev->dev, "clock enable failed!\n"); ++ return ret; ++ } ++ mtk_i2c_init_hw(i2c); ++ mtk_i2c_clock_disable(i2c); ++ ++ ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq, ++ IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c); ++ if (ret < 0) { ++ dev_err(&pdev->dev, ++ "Request I2C IRQ %d fail\n", irq); ++ return ret; ++ } ++ ++ i2c_set_adapdata(&i2c->adap, i2c); ++ ret = i2c_add_adapter(&i2c->adap); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n"); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, i2c); ++ ++ return 0; ++} ++ ++static int mtk_i2c_remove(struct platform_device *pdev) ++{ ++ struct mtk_i2c *i2c = platform_get_drvdata(pdev); ++ ++ i2c_del_adapter(&i2c->adap); ++ ++ return 0; ++} ++ ++static struct platform_driver mtk_i2c_driver = { ++ .probe = mtk_i2c_probe, ++ .remove = mtk_i2c_remove, ++ .driver = { ++ .name = I2C_DRV_NAME, ++ .of_match_table = of_match_ptr(mtk_i2c_of_match), ++ }, ++}; ++ ++module_platform_driver(mtk_i2c_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); ++MODULE_AUTHOR("Xudong Chen "); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0031-I2C-mediatek-Add-driver-for-MediaTek-MT8173-I2C-cont.patch b/target/linux/mediatek/patches/0031-I2C-mediatek-Add-driver-for-MediaTek-MT8173-I2C-cont.patch new file mode 100644 index 0000000..25ea23e --- /dev/null +++ b/target/linux/mediatek/patches/0031-I2C-mediatek-Add-driver-for-MediaTek-MT8173-I2C-cont.patch @@ -0,0 +1,244 @@ +From 5f33206ebe4fb4a2cc8634f29c3e3c9bc01e3416 Mon Sep 17 00:00:00 2001 +From: Eddie Huang +Date: Wed, 6 May 2015 16:37:07 +0800 +Subject: [PATCH 31/76] I2C: mediatek: Add driver for MediaTek MT8173 I2C + controller + +Add mediatek MT8173 I2C controller driver. Compare to I2C controller +of earlier mediatek SoC, MT8173 fix write-then-read limitation, and +also increase message size to 64kb. + +Signed-off-by: Xudong Chen +Signed-off-by: Liguo Zhang +Signed-off-by: Eddie Huang +--- + drivers/i2c/busses/i2c-mt65xx.c | 104 ++++++++++++++++++++++++++++----------- + 1 file changed, 76 insertions(+), 28 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c +index faecf7e..c501421 100644 +--- a/drivers/i2c/busses/i2c-mt65xx.c ++++ b/drivers/i2c/busses/i2c-mt65xx.c +@@ -33,10 +33,13 @@ + #include + #include + ++#define I2C_RS_TRANSFER (1 << 4) + #define I2C_HS_NACKERR (1 << 2) + #define I2C_ACKERR (1 << 1) + #define I2C_TRANSAC_COMP (1 << 0) + #define I2C_TRANSAC_START (1 << 0) ++#define I2C_RS_MUL_CNFG (1 << 15) ++#define I2C_RS_MUL_TRIG (1 << 14) + #define I2C_TIMING_STEP_DIV_MASK (0x3f << 0) + #define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0) + #define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8) +@@ -67,6 +70,9 @@ + #define MAX_MSG_NUM_MT6577 1 + #define MAX_DMA_TRANS_SIZE_MT6577 255 + #define MAX_WRRD_TRANS_SIZE_MT6577 31 ++#define MAX_MSG_NUM_MT8173 65535 ++#define MAX_DMA_TRANS_SIZE_MT8173 65535 ++#define MAX_WRRD_TRANS_SIZE_MT8173 65535 + #define MAX_SAMPLE_CNT_DIV 8 + #define MAX_STEP_CNT_DIV 64 + #define MAX_HS_STEP_CNT_DIV 8 +@@ -139,6 +145,7 @@ struct mtk_i2c_compatible { + const struct i2c_adapter_quirks *quirks; + unsigned char pmic_i2c; + unsigned char dcm; ++ unsigned char auto_restart; + }; + + struct mtk_i2c { +@@ -172,21 +179,39 @@ static const struct i2c_adapter_quirks mt6577_i2c_quirks = { + .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577, + }; + ++static const struct i2c_adapter_quirks mt8173_i2c_quirks = { ++ .max_num_msgs = MAX_MSG_NUM_MT8173, ++ .max_write_len = MAX_DMA_TRANS_SIZE_MT8173, ++ .max_read_len = MAX_DMA_TRANS_SIZE_MT8173, ++ .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT8173, ++ .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT8173, ++}; ++ + static const struct mtk_i2c_compatible mt6577_compat = { + .quirks = &mt6577_i2c_quirks, + .pmic_i2c = 0, + .dcm = 1, ++ .auto_restart = 0, + }; + + static const struct mtk_i2c_compatible mt6589_compat = { + .quirks = &mt6577_i2c_quirks, + .pmic_i2c = 1, + .dcm = 0, ++ .auto_restart = 0, ++}; ++ ++static const struct mtk_i2c_compatible mt8173_compat = { ++ .quirks = &mt8173_i2c_quirks, ++ .pmic_i2c = 0, ++ .dcm = 1, ++ .auto_restart = 1, + }; + + static const struct of_device_id mtk_i2c_of_match[] = { + { .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat }, + { .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat }, ++ { .compatible = "mediatek,mt8173-i2c", .data = (void *)&mt8173_compat }, + {} + }; + MODULE_DEVICE_TABLE(of, mtk_i2c_of_match); +@@ -343,9 +368,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int clk_src_in_hz) + return 0; + } + +-static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs) ++static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, ++ int num, int left_num) + { + u16 addr_reg; ++ u16 start_reg; + u16 control_reg; + dma_addr_t rpaddr = 0; + dma_addr_t wpaddr = 0; +@@ -361,6 +388,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs) + control_reg |= I2C_CONTROL_RS; + if (i2c->op == I2C_MASTER_WRRD) + control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS; ++ if (left_num >= 1) ++ control_reg |= I2C_CONTROL_RS; + mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL); + + /* set start condition */ +@@ -375,13 +404,13 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs) + mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR); + + /* Clear interrupt status */ +- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP, +- i2c, OFFSET_INTR_STAT); ++ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR ++ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT); + mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR); + + /* Enable interrupt */ +- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP, +- i2c, OFFSET_INTR_MASK); ++ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR ++ | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_MASK); + + /* Set transfer and transaction len */ + if (i2c->op == I2C_MASTER_WRRD) { +@@ -390,7 +419,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs) + mtk_i2c_writew(I2C_WRRD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN); + } else { + mtk_i2c_writew(msgs->len, i2c, OFFSET_TRANSFER_LEN); +- mtk_i2c_writew(I2C_RD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN); ++ mtk_i2c_writew(num, i2c, OFFSET_TRANSAC_LEN); + } + + /* Prepare buffer data to start transfer */ +@@ -436,13 +465,23 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs) + /* flush before sending start */ + mb(); + mtk_i2c_writel_dma(I2C_DMA_START_EN, i2c, OFFSET_EN); +- mtk_i2c_writew(I2C_TRANSAC_START, i2c, OFFSET_START); ++ ++ if (!i2c->dev_comp->auto_restart) { ++ start_reg = I2C_TRANSAC_START; ++ } else { ++ if (left_num >= 1) ++ start_reg = I2C_TRANSAC_START | I2C_RS_MUL_CNFG ++ | I2C_RS_MUL_TRIG; ++ else ++ start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG; ++ } ++ mtk_i2c_writew(start_reg, i2c, OFFSET_START); + + ret = wait_for_completion_timeout(&i2c->msg_complete, + i2c->adap.timeout); + + /* Clear interrupt mask */ +- mtk_i2c_writew(~(I2C_HS_NACKERR | I2C_ACKERR ++ mtk_i2c_writew(~(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR + | I2C_TRANSAC_COMP), i2c, OFFSET_INTR_MASK); + + if (i2c->op == I2C_MASTER_WR) { +@@ -472,6 +511,10 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs) + return -EREMOTEIO; + } + ++ if (i2c->irq_stat & I2C_RS_TRANSFER) ++ dev_dbg(i2c->dev, "addr: %x, restart transfer interrupt.\n", ++ msgs->addr); ++ + return 0; + } + +@@ -486,28 +529,33 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap, + if (ret) + return ret; + +- if (msgs->buf == NULL) { +- dev_dbg(i2c->dev, "data buffer is NULL.\n"); +- ret = -EINVAL; +- goto err_exit; +- } +- +- if (msgs->flags & I2C_M_RD) +- i2c->op = I2C_MASTER_RD; +- else +- i2c->op = I2C_MASTER_WR; ++ while (left_num--) { ++ if (msgs->buf == NULL) { ++ dev_dbg(i2c->dev, "data buffer is NULL.\n"); ++ ret = -EINVAL; ++ goto err_exit; ++ } + +- if (num > 1) { +- /* combined two messages into one transaction */ +- i2c->op = I2C_MASTER_WRRD; +- left_num--; +- } ++ if (msgs->flags & I2C_M_RD) ++ i2c->op = I2C_MASTER_RD; ++ else ++ i2c->op = I2C_MASTER_WR; ++ ++ if (!i2c->dev_comp->auto_restart) { ++ if (num > 1) { ++ /* combined two messages into one transaction */ ++ i2c->op = I2C_MASTER_WRRD; ++ left_num--; ++ } ++ } + +- /* always use DMA mode. */ +- ret = mtk_i2c_do_transfer(i2c, msgs); +- if (ret < 0) +- goto err_exit; ++ /* always use DMA mode. */ ++ ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num); ++ if (ret < 0) ++ goto err_exit; + ++ msgs++; ++ } + /* the return value is number of executed messages */ + ret = num; + +@@ -521,7 +569,7 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) + struct mtk_i2c *i2c = dev_id; + + i2c->irq_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); +- mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR ++ mtk_i2c_writew(I2C_RS_TRANSFER | I2C_HS_NACKERR | I2C_ACKERR + | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT); + + complete(&i2c->msg_complete); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0032-dt-bindings-mediatek-Add-MT8173-cpufreq-driver-bindi.patch b/target/linux/mediatek/patches/0032-dt-bindings-mediatek-Add-MT8173-cpufreq-driver-bindi.patch new file mode 100644 index 0000000..7f3b249 --- /dev/null +++ b/target/linux/mediatek/patches/0032-dt-bindings-mediatek-Add-MT8173-cpufreq-driver-bindi.patch @@ -0,0 +1,150 @@ +From d83532fe7eb9cc7b8cc39dd9f2bbd9873d4e390b Mon Sep 17 00:00:00 2001 +From: "pi-cheng.chen" +Date: Mon, 8 Jun 2015 20:29:20 +0800 +Subject: [PATCH 32/76] dt-bindings: mediatek: Add MT8173 cpufreq driver + binding + +This patch adds device tree binding document for MT8173 cpufreq driver. + +Signed-off-by: Pi-Cheng Chen +--- + .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt | 127 ++++++++++++++++++++ + 1 file changed, 127 insertions(+) + create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt + +diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt +new file mode 100644 +index 0000000..7708a65 +--- /dev/null ++++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt +@@ -0,0 +1,127 @@ ++ ++Mediatek MT8173 cpufreq driver ++------------------- ++ ++Mediatek MT8173 cpufreq driver for CPU frequency scaling. ++ ++Required properties: ++- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. ++- clock-names: Should contain the following: ++ "cpu" - The multiplexer for clock input of CPU cluster. ++ "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock ++ source (usually MAINPLL) when the original CPU PLL is under ++ transition and not stable yet. ++- operating-points: Table of frequencies and voltage CPU could be transitioned into, ++ Frequency should be in KHz units and voltage should be in microvolts. ++- proc-supply: Regulator for Vproc of CPU cluster. ++ ++Optional properties: ++- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver ++ needs to do "voltage trace" to step by step scale up/down Vproc and ++ Vsram to fit SoC specific needs. When absent, the voltage scaling ++ flow is handled by hardware, hence no software "voltage trace" is ++ needed. ++ ++Example: ++-------- ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x000>; ++ enable-method = "psci"; ++ cpu-idle-states = <&CPU_SLEEP_0>; ++ clocks = <&infracfg CLK_INFRA_CA53SEL>, ++ <&apmixedsys CLK_APMIXED_MAINPLL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points = < ++ 507000 859000 ++ 702000 908000 ++ 1001000 983000 ++ 1105000 1009000 ++ 1183000 1028000 ++ 1404000 1083000 ++ 1508000 1109000 ++ 1573000 1125000 ++ >; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x001>; ++ enable-method = "psci"; ++ cpu-idle-states = <&CPU_SLEEP_0>; ++ clocks = <&infracfg CLK_INFRA_CA53SEL>, ++ <&apmixedsys CLK_APMIXED_MAINPLL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points = < ++ 507000 859000 ++ 702000 908000 ++ 1001000 983000 ++ 1105000 1009000 ++ 1183000 1028000 ++ 1404000 1083000 ++ 1508000 1109000 ++ 1573000 1125000 ++ >; ++ }; ++ ++ cpu2: cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a57"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ cpu-idle-states = <&CPU_SLEEP_0>; ++ clocks = <&infracfg CLK_INFRA_CA57SEL>, ++ <&apmixedsys CLK_APMIXED_MAINPLL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points = < ++ 507000 828000 ++ 702000 867000 ++ 1001000 927000 ++ 1209000 968000 ++ 1404000 1007000 ++ 1612000 1049000 ++ 1807000 1089000 ++ 1989000 1125000 ++ >; ++ }; ++ ++ cpu3: cpu@101 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a57"; ++ reg = <0x101>; ++ enable-method = "psci"; ++ cpu-idle-states = <&CPU_SLEEP_0>; ++ clocks = <&infracfg CLK_INFRA_CA57SEL>, ++ <&apmixedsys CLK_APMIXED_MAINPLL>; ++ clock-names = "cpu", "intermediate"; ++ operating-points = < ++ 507000 828000 ++ 702000 867000 ++ 1001000 927000 ++ 1209000 968000 ++ 1404000 1007000 ++ 1612000 1049000 ++ 1807000 1089000 ++ 1989000 1125000 ++ >; ++ }; ++ ++ &cpu0 { ++ proc-supply = <&mt6397_vpca15_reg>; ++ }; ++ ++ &cpu1 { ++ proc-supply = <&mt6397_vpca15_reg>; ++ }; ++ ++ &cpu2 { ++ proc-supply = <&da9211_vcpu_reg>; ++ sram-supply = <&mt6397_vsramca7_reg>; ++ }; ++ ++ &cpu3 { ++ proc-supply = <&da9211_vcpu_reg>; ++ sram-supply = <&mt6397_vsramca7_reg>; ++ }; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0033-cpufreq-mediatek-Add-MT8173-cpufreq-driver.patch b/target/linux/mediatek/patches/0033-cpufreq-mediatek-Add-MT8173-cpufreq-driver.patch new file mode 100644 index 0000000..81ae4f8 --- /dev/null +++ b/target/linux/mediatek/patches/0033-cpufreq-mediatek-Add-MT8173-cpufreq-driver.patch @@ -0,0 +1,604 @@ +From 2028cb37c941014f6a817d27a867ee1d37ccf2b6 Mon Sep 17 00:00:00 2001 +From: "pi-cheng.chen" +Date: Mon, 8 Jun 2015 20:29:21 +0800 +Subject: [PATCH 33/76] cpufreq: mediatek: Add MT8173 cpufreq driver + +This patch implements MT8173 cpufreq driver. + +Signed-off-by: Pi-Cheng Chen +--- + drivers/cpufreq/Kconfig.arm | 7 + + drivers/cpufreq/Makefile | 1 + + drivers/cpufreq/mt8173-cpufreq.c | 550 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 558 insertions(+) + create mode 100644 drivers/cpufreq/mt8173-cpufreq.c + +diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm +index 4f3dbc8..350752b 100644 +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -141,6 +141,13 @@ config ARM_KIRKWOOD_CPUFREQ + This adds the CPUFreq driver for Marvell Kirkwood + SoCs. + ++config ARM_MT8173_CPUFREQ ++ bool "Mediatek MT8173 CPUFreq support" ++ depends on ARCH_MEDIATEK && REGULATOR ++ select PM_OPP ++ help ++ This adds the CPUFreq driver support for Mediatek MT8173 SoC. ++ + config ARM_OMAP2PLUS_CPUFREQ + bool "TI OMAP2+" + depends on ARCH_OMAP2PLUS +diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile +index cdce92a..97f9a9b 100644 +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_HISI_ACPU_CPUFREQ) += hisi-acpu-cpufreq.o + obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o + obj-$(CONFIG_ARM_INTEGRATOR) += integrator-cpufreq.o + obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o ++obj-$(CONFIG_ARM_MT8173_CPUFREQ) += mt8173-cpufreq.o + obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o + obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o + obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o +diff --git a/drivers/cpufreq/mt8173-cpufreq.c b/drivers/cpufreq/mt8173-cpufreq.c +new file mode 100644 +index 0000000..d539e7b +--- /dev/null ++++ b/drivers/cpufreq/mt8173-cpufreq.c +@@ -0,0 +1,550 @@ ++/* ++ * Copyright (c) 2015 Linaro Ltd. ++ * Author: Pi-Cheng Chen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MIN_VOLT_SHIFT (100000) ++#define MAX_VOLT_SHIFT (200000) ++#define MAX_VOLT_LIMIT (1150000) ++#define VOLT_TOL (10000) ++ ++/* ++ * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS ++ * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in ++ * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two ++ * voltage inputs need to be controlled under a hardware limitation: ++ * 100mV < Vsram - Vproc < 200mV ++ * ++ * When scaling the clock frequency of a CPU clock domain, the clock source ++ * needs to be switched to another stable PLL clock temporarily until ++ * the original PLL becomes stable at target frequency. ++ */ ++struct mtk_cpu_dvfs_info { ++ struct list_head node; ++ cpumask_var_t cpus; ++ struct cpufreq_frequency_table *freq_table; ++ struct device *cpu_dev; ++ struct regulator *proc_reg; ++ struct regulator *sram_reg; ++ struct clk *cpu_clk; ++ struct clk *inter_clk; ++ int intermediate_voltage; ++ bool need_voltage_trace; ++}; ++ ++static LIST_HEAD(cpu_dvfs_info_list); ++ ++static inline struct mtk_cpu_dvfs_info *to_mtk_cpu_dvfs_info( ++ struct list_head *list) ++{ ++ return list_entry(list, struct mtk_cpu_dvfs_info, node); ++} ++ ++static inline void mtk_cpu_dvfs_info_add(struct mtk_cpu_dvfs_info *info) ++{ ++ list_add(&info->node, &cpu_dvfs_info_list); ++} ++ ++static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_get(int cpu) ++{ ++ struct mtk_cpu_dvfs_info *info; ++ struct list_head *list; ++ ++ list_for_each(list, &cpu_dvfs_info_list) { ++ info = to_mtk_cpu_dvfs_info(list); ++ ++ if (cpumask_test_cpu(cpu, info->cpus)) ++ return info; ++ } ++ ++ return NULL; ++} ++ ++static void mtk_cpu_dvfs_info_release(void) ++{ ++ struct list_head *list, *tmp; ++ struct mtk_cpu_dvfs_info *info; ++ ++ list_for_each_safe(list, tmp, &cpu_dvfs_info_list) { ++ info = to_mtk_cpu_dvfs_info(list); ++ ++ dev_pm_opp_free_cpufreq_table(info->cpu_dev, ++ &info->freq_table); ++ ++ if (!IS_ERR(info->proc_reg)) ++ regulator_put(info->proc_reg); ++ if (!IS_ERR(info->sram_reg)) ++ regulator_put(info->sram_reg); ++ if (!IS_ERR(info->cpu_clk)) ++ clk_put(info->cpu_clk); ++ if (!IS_ERR(info->inter_clk)) ++ clk_put(info->inter_clk); ++ ++ of_free_opp_table(info->cpu_dev); ++ ++ list_del(list); ++ kfree(info); ++ } ++} ++ ++#define MIN(a, b) ((a) < (b) ? (a) : (b)) ++#define MAX(a, b) ((a) > (b) ? (a) : (b)) ++ ++static int mtk_cpufreq_voltage_trace(struct mtk_cpu_dvfs_info *info, ++ int new_vproc) ++{ ++ struct regulator *proc_reg = info->proc_reg; ++ struct regulator *sram_reg = info->sram_reg; ++ int old_vproc, old_vsram, new_vsram, vsram, vproc, ret; ++ ++ old_vproc = regulator_get_voltage(proc_reg); ++ old_vsram = regulator_get_voltage(sram_reg); ++ /* Vsram should not exceed the maximum allowed voltage of SoC. */ ++ new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); ++ ++ if (old_vproc < new_vproc) { ++ /* ++ * When scaling up voltages, Vsram and Vproc scale up step ++ * by step. At each step, set Vsram to (Vproc + 200mV) first, ++ * then set Vproc to (Vsram - 100mV). ++ * Keep doing it until Vsram and Vproc hit target voltages. ++ */ ++ do { ++ old_vsram = regulator_get_voltage(sram_reg); ++ old_vproc = regulator_get_voltage(proc_reg); ++ ++ vsram = MIN(new_vsram, old_vproc + MAX_VOLT_SHIFT); ++ ++ if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { ++ vsram = MAX_VOLT_LIMIT; ++ ++ /* ++ * If the target Vsram hits the maximum voltage, ++ * try to set the exact voltage value first. ++ */ ++ ret = regulator_set_voltage(sram_reg, vsram, ++ vsram); ++ if (ret) ++ ret = regulator_set_voltage(sram_reg, ++ vsram - VOLT_TOL, ++ vsram); ++ ++ vproc = new_vproc; ++ } else { ++ ret = regulator_set_voltage(sram_reg, vsram, ++ vsram + VOLT_TOL); ++ ++ vproc = vsram - MIN_VOLT_SHIFT; ++ } ++ if (ret) ++ return ret; ++ ++ ret = regulator_set_voltage(proc_reg, vproc, ++ vproc + VOLT_TOL); ++ if (ret) { ++ regulator_set_voltage(sram_reg, old_vsram, ++ old_vsram); ++ return ret; ++ } ++ } while (vproc < new_vproc || vsram < new_vsram); ++ } else if (old_vproc > new_vproc) { ++ /* ++ * When scaling down voltages, Vsram and Vproc scale down step ++ * by step. At each step, set Vproc to (Vsram - 200mV) first, ++ * then set Vproc to (Vproc + 100mV). ++ * Keep doing it until Vsram and Vproc hit target voltages. ++ */ ++ do { ++ old_vproc = regulator_get_voltage(proc_reg); ++ old_vsram = regulator_get_voltage(sram_reg); ++ ++ vproc = MAX(new_vproc, old_vsram - MAX_VOLT_SHIFT); ++ ret = regulator_set_voltage(proc_reg, vproc, ++ vproc + VOLT_TOL); ++ if (ret) ++ return ret; ++ ++ if (vproc == new_vproc) ++ vsram = new_vsram; ++ else ++ vsram = MAX(new_vsram, vproc + MIN_VOLT_SHIFT); ++ ++ if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { ++ vsram = MAX_VOLT_LIMIT; ++ ++ /* ++ * If the target Vsram hits the maximum voltage, ++ * try to set the exact voltage value first. ++ */ ++ ret = regulator_set_voltage(sram_reg, vsram, ++ vsram); ++ if (ret) ++ ret = regulator_set_voltage(sram_reg, ++ vsram - VOLT_TOL, ++ vsram); ++ } else { ++ ret = regulator_set_voltage(sram_reg, vsram, ++ vsram + VOLT_TOL); ++ } ++ ++ if (ret) { ++ regulator_set_voltage(proc_reg, old_vproc, ++ old_vproc); ++ return ret; ++ } ++ } while (vproc > new_vproc + VOLT_TOL || ++ vsram > new_vsram + VOLT_TOL); ++ } ++ ++ return 0; ++} ++ ++static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) ++{ ++ if (info->need_voltage_trace) ++ return mtk_cpufreq_voltage_trace(info, vproc); ++ else ++ return regulator_set_voltage(info->proc_reg, vproc, ++ vproc + VOLT_TOL); ++} ++ ++static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, ++ unsigned int index) ++{ ++ struct cpufreq_frequency_table *freq_table = policy->freq_table; ++ struct clk *cpu_clk = policy->clk; ++ struct clk *armpll = clk_get_parent(cpu_clk); ++ struct mtk_cpu_dvfs_info *info = policy->driver_data; ++ struct device *cpu_dev = info->cpu_dev; ++ struct dev_pm_opp *opp; ++ long freq_hz, old_freq_hz; ++ int vproc, old_vproc, inter_vproc, target_vproc, ret; ++ ++ inter_vproc = info->intermediate_voltage; ++ ++ old_freq_hz = clk_get_rate(cpu_clk); ++ old_vproc = regulator_get_voltage(info->proc_reg); ++ ++ freq_hz = freq_table[index].frequency * 1000; ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); ++ if (IS_ERR(opp)) { ++ rcu_read_unlock(); ++ pr_err("cpu%d: failed to find OPP for %ld\n", ++ policy->cpu, freq_hz); ++ return PTR_ERR(opp); ++ } ++ vproc = dev_pm_opp_get_voltage(opp); ++ rcu_read_unlock(); ++ ++ /* ++ * If the new voltage or the intermediate voltage is higher than the ++ * current voltage, scale up voltage first. ++ */ ++ target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; ++ if (old_vproc < target_vproc) { ++ ret = mtk_cpufreq_set_voltage(info, target_vproc); ++ if (ret) { ++ pr_err("cpu%d: failed to scale up voltage!\n", ++ policy->cpu); ++ mtk_cpufreq_set_voltage(info, old_vproc); ++ return ret; ++ } ++ } ++ ++ /* Reparent the CPU clock to intermediate clock. */ ++ ret = clk_set_parent(cpu_clk, info->inter_clk); ++ if (ret) { ++ pr_err("cpu%d: failed to re-parent cpu clock!\n", ++ policy->cpu); ++ mtk_cpufreq_set_voltage(info, old_vproc); ++ WARN_ON(1); ++ return ret; ++ } ++ ++ /* Set the original PLL to target rate. */ ++ ret = clk_set_rate(armpll, freq_hz); ++ if (ret) { ++ pr_err("cpu%d: failed to scale cpu clock rate!\n", ++ policy->cpu); ++ clk_set_parent(cpu_clk, armpll); ++ mtk_cpufreq_set_voltage(info, old_vproc); ++ return ret; ++ } ++ ++ /* Set parent of CPU clock back to the original PLL. */ ++ ret = clk_set_parent(cpu_clk, armpll); ++ if (ret) { ++ pr_err("cpu%d: failed to re-parent cpu clock!\n", ++ policy->cpu); ++ mtk_cpufreq_set_voltage(info, inter_vproc); ++ WARN_ON(1); ++ return ret; ++ } ++ ++ /* ++ * If the new voltage is lower than the intermediate voltage or the ++ * original voltage, scale down to the new voltage. ++ */ ++ if (vproc < inter_vproc || vproc < old_vproc) { ++ ret = mtk_cpufreq_set_voltage(info, vproc); ++ if (ret) { ++ pr_err("cpu%d: failed to scale down voltage!\n", ++ policy->cpu); ++ clk_set_parent(cpu_clk, info->inter_clk); ++ clk_set_rate(armpll, old_freq_hz); ++ clk_set_parent(cpu_clk, armpll); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int mtk_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ struct mtk_cpu_dvfs_info *info; ++ int ret; ++ ++ info = mtk_cpu_dvfs_info_get(policy->cpu); ++ if (!info) { ++ pr_err("%s: mtk cpu dvfs info for cpu%d is not initialized\n", ++ __func__, policy->cpu); ++ return -ENODEV; ++ } ++ ++ ret = cpufreq_table_validate_and_show(policy, info->freq_table); ++ if (ret) { ++ pr_err("%s: invalid frequency table: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ cpumask_copy(policy->cpus, info->cpus); ++ policy->driver_data = info; ++ policy->clk = info->cpu_clk; ++ ++ return 0; ++} ++ ++static struct cpufreq_driver mt8173_cpufreq_driver = { ++ .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, ++ .verify = cpufreq_generic_frequency_table_verify, ++ .target_index = mtk_cpufreq_set_target, ++ .get = cpufreq_generic_get, ++ .init = mtk_cpufreq_init, ++ .name = "mtk-cpufreq", ++ .attr = cpufreq_generic_attr, ++}; ++ ++static int mtk_cpu_dvfs_info_init(int cpu) ++{ ++ struct device *cpu_dev; ++ struct regulator *proc_reg = ERR_PTR(-ENODEV); ++ struct regulator *sram_reg = ERR_PTR(-ENODEV); ++ struct clk *cpu_clk = ERR_PTR(-ENODEV); ++ struct clk *inter_clk = ERR_PTR(-ENODEV); ++ struct mtk_cpu_dvfs_info *info; ++ struct cpufreq_frequency_table *freq_table; ++ struct dev_pm_opp *opp; ++ unsigned long rate; ++ int ret; ++ ++ cpu_dev = get_cpu_device(cpu); ++ if (!cpu_dev) { ++ pr_err("failed to get cpu%d device\n", cpu); ++ return -ENODEV; ++ } ++ ++ ret = of_init_opp_table(cpu_dev); ++ if (ret) { ++ pr_warn("no OPP table for cpu%d\n", cpu); ++ return ret; ++ } ++ ++ cpu_clk = clk_get(cpu_dev, "cpu"); ++ if (IS_ERR(cpu_clk)) { ++ if (PTR_ERR(cpu_clk) == -EPROBE_DEFER) ++ pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu); ++ else ++ pr_err("failed to get cpu clk for cpu%d\n", cpu); ++ ++ ret = PTR_ERR(cpu_clk); ++ goto out_free_opp_table; ++ } ++ ++ inter_clk = clk_get(cpu_dev, "intermediate"); ++ if (IS_ERR(inter_clk)) { ++ if (PTR_ERR(inter_clk) == -EPROBE_DEFER) ++ pr_warn("intermediate clk for cpu%d not ready, retry.\n", ++ cpu); ++ else ++ pr_err("failed to get intermediate clk for cpu%d\n", ++ cpu); ++ ++ ret = PTR_ERR(cpu_clk); ++ goto out_free_resources; ++ } ++ ++ proc_reg = regulator_get_exclusive(cpu_dev, "proc"); ++ if (IS_ERR(proc_reg)) { ++ if (PTR_ERR(proc_reg) == -EPROBE_DEFER) ++ pr_warn("proc regulator for cpu%d not ready, retry.\n", ++ cpu); ++ else ++ pr_err("failed to get proc regulator for cpu%d\n", ++ cpu); ++ ++ ret = PTR_ERR(proc_reg); ++ goto out_free_resources; ++ } ++ ++ /* Both presence and absence of sram regulator are valid cases. */ ++ sram_reg = regulator_get_exclusive(cpu_dev, "sram"); ++ ++ info = kzalloc(sizeof(*info), GFP_KERNEL); ++ if (!info) { ++ ret = -ENOMEM; ++ goto out_free_resources; ++ } ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); ++ if (ret) { ++ pr_err("failed to init cpufreq table for cpu%d: %d\n", ++ cpu, ret); ++ goto out_free_mtk_cpu_dvfs_info; ++ } ++ ++ if (!alloc_cpumask_var(&info->cpus, GFP_KERNEL)) ++ goto out_free_cpufreq_table; ++ ++ /* Search a safe voltage for intermediate frequency. */ ++ rate = clk_get_rate(inter_clk); ++ rcu_read_lock(); ++ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); ++ if (IS_ERR(opp)) { ++ pr_err("failed to get intermediate opp for cpu%d\n", cpu); ++ ret = PTR_ERR(opp); ++ goto out_free_cpumask; ++ } ++ info->intermediate_voltage = dev_pm_opp_get_voltage(opp); ++ rcu_read_unlock(); ++ ++ /* CPUs in the same cluster share a clock and power domain. */ ++ cpumask_copy(info->cpus, &cpu_topology[cpu].core_sibling); ++ ++ info->cpu_dev = cpu_dev; ++ info->proc_reg = proc_reg; ++ info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg; ++ info->cpu_clk = cpu_clk; ++ info->inter_clk = inter_clk; ++ info->freq_table = freq_table; ++ ++ /* ++ * If SRAM regulator is present, software "voltage trace" is needed ++ * for this CPU power domain. ++ */ ++ info->need_voltage_trace = !IS_ERR(sram_reg); ++ ++ mtk_cpu_dvfs_info_add(info); ++ ++ return 0; ++ ++out_free_cpumask: ++ free_cpumask_var(info->cpus); ++ ++out_free_cpufreq_table: ++ dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); ++ ++out_free_mtk_cpu_dvfs_info: ++ kfree(info); ++ ++out_free_resources: ++ if (!IS_ERR(proc_reg)) ++ regulator_put(proc_reg); ++ if (!IS_ERR(sram_reg)) ++ regulator_put(sram_reg); ++ if (!IS_ERR(cpu_clk)) ++ clk_put(cpu_clk); ++ if (!IS_ERR(inter_clk)) ++ clk_put(inter_clk); ++ ++out_free_opp_table: ++ of_free_opp_table(cpu_dev); ++ ++ return ret; ++} ++ ++static int mt8173_cpufreq_probe(struct platform_device *pdev) ++{ ++ int cpu, ret; ++ ++ for_each_possible_cpu(cpu) { ++ /* ++ * If the struct mtk_cpu_dvfs_info for the cpu power domain ++ * is already initialized, skip this CPU. ++ */ ++ if (!mtk_cpu_dvfs_info_get(cpu)) { ++ ret = mtk_cpu_dvfs_info_init(cpu); ++ if (ret) { ++ if (ret != -EPROBE_DEFER) ++ pr_err("%s probe fail\n", __func__); ++ ++ mtk_cpu_dvfs_info_release(); ++ return ret; ++ } ++ } ++ } ++ ++ ret = cpufreq_register_driver(&mt8173_cpufreq_driver); ++ if (ret) { ++ pr_err("failed to register mtk cpufreq driver\n"); ++ mtk_cpu_dvfs_info_release(); ++ } ++ ++ return ret; ++} ++ ++static struct platform_driver mt8173_cpufreq_platdrv = { ++ .driver = { ++ .name = "mt8173-cpufreq", ++ }, ++ .probe = mt8173_cpufreq_probe, ++}; ++module_platform_driver(mt8173_cpufreq_platdrv); ++ ++static int mt8173_cpufreq_driver_init(void) ++{ ++ struct platform_device *pdev; ++ ++ if (!of_machine_is_compatible("mediatek,mt8173")) ++ return -ENODEV; ++ ++ pdev = platform_device_register_simple("mt8173-cpufreq", -1, NULL, 0); ++ if (IS_ERR(pdev)) { ++ pr_err("failed to register mtk-cpufreq platform device\n"); ++ return PTR_ERR(pdev); ++ } ++ ++ return 0; ++} ++module_init(mt8173_cpufreq_driver_init); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0034-mmc-dt-bindings-add-Mediatek-MMC-bindings.patch b/target/linux/mediatek/patches/0034-mmc-dt-bindings-add-Mediatek-MMC-bindings.patch new file mode 100644 index 0000000..02a153d --- /dev/null +++ b/target/linux/mediatek/patches/0034-mmc-dt-bindings-add-Mediatek-MMC-bindings.patch @@ -0,0 +1,54 @@ +From fe43da8836dbf8e48377d208000877a17e465f3f Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 15 Jun 2015 19:20:47 +0800 +Subject: [PATCH 34/76] mmc: dt-bindings: add Mediatek MMC bindings + +Document the device-tree binding of Mediatek MMC host + +Signed-off-by: Chaotian Jing +--- + Documentation/devicetree/bindings/mmc/mtk-sd.txt | 32 ++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt + +diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt +new file mode 100644 +index 0000000..a1adfa4 +--- /dev/null ++++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt +@@ -0,0 +1,32 @@ ++* MTK MMC controller ++ ++The MTK MSDC can act as a MMC controller ++to support MMC, SD, and SDIO types of memory cards. ++ ++This file documents differences between the core properties in mmc.txt ++and the properties used by the msdc driver. ++ ++Required properties: ++- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc" ++- interrupts: Should contain MSDC interrupt number ++- clocks: MSDC source clock, HCLK ++- clock-names: "source", "hclk" ++- pinctrl-names: should be "default", "state_uhs" ++- pinctrl-0: should contain default/high speed pin ctrl ++- pinctrl-1: should contain uhs mode pin ctrl ++- vmmc-supply: power to the Core ++- vqmmc-supply: power to the IO ++ ++Examples: ++mmc0: mmc@11230000 { ++ compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc"; ++ reg = <0 0x11230000 0 0x108>; ++ interrupts = ; ++ vmmc-supply = <&mt6397_vemc_3v3_reg>; ++ vqmmc-supply = <&mt6397_vio18_reg>; ++ clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>; ++ clock-names = "source", "hclk"; ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ pinctrl-1 = <&mmc0_pins_uhs>; ++}; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0035-mmc-mediatek-Add-Mediatek-MMC-driver.patch b/target/linux/mediatek/patches/0035-mmc-mediatek-Add-Mediatek-MMC-driver.patch new file mode 100644 index 0000000..d135ad0 --- /dev/null +++ b/target/linux/mediatek/patches/0035-mmc-mediatek-Add-Mediatek-MMC-driver.patch @@ -0,0 +1,1422 @@ +From 0b71d2f1ee40313f58a3c6e9ed95add6f5a8192d Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 15 Jun 2015 19:20:48 +0800 +Subject: [PATCH 35/76] mmc: mediatek: Add Mediatek MMC driver + +Add Mediatek MMC driver code +Support eMMC/SD/SDIO + +Signed-off-by: Chaotian Jing +--- + drivers/mmc/host/Kconfig | 8 + + drivers/mmc/host/Makefile | 1 + + drivers/mmc/host/mtk-sd.c | 1378 +++++++++++++++++++++++++++++++++++++++++++++ + include/linux/mmc/core.h | 1 + + 4 files changed, 1388 insertions(+) + create mode 100644 drivers/mmc/host/mtk-sd.c + +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -800,3 +800,11 @@ + tristate "Toshiba Type A SD/MMC Card Interface Driver" + depends on PCI + help ++ ++config MMC_MTK ++ tristate "MediaTek SD/MMC Card Interface support" ++ help ++ This selects the MediaTek(R) Secure digital and Multimedia card Interface. ++ If you have a machine with a integrated SD/MMC card reader, say Y or M here. ++ This is needed if support for any SD/SDIO/MMC devices is required. ++ If unsure, say N. +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -20,6 +20,7 @@ + obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o + obj-$(CONFIG_MMC_WBSD) += wbsd.o + obj-$(CONFIG_MMC_AU1X) += au1xmmc.o ++obj-$(CONFIG_MMC_MTK) += mtk-sd.o + obj-$(CONFIG_MMC_OMAP) += omap.o + obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o + obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o +--- /dev/null ++++ b/drivers/mmc/host/mtk-sd.c +@@ -0,0 +1,1378 @@ ++/* ++ * Copyright (c) 2014-2015 MediaTek Inc. ++ * Author: Chaotian.Jing ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MAX_BD_NUM 1024 ++ ++/*--------------------------------------------------------------------------*/ ++/* Common Definition */ ++/*--------------------------------------------------------------------------*/ ++#define MSDC_BUS_1BITS 0x0 ++#define MSDC_BUS_4BITS 0x1 ++#define MSDC_BUS_8BITS 0x2 ++ ++#define MSDC_BURST_64B 0x6 ++ ++/*--------------------------------------------------------------------------*/ ++/* Register Offset */ ++/*--------------------------------------------------------------------------*/ ++#define MSDC_CFG 0x0 ++#define MSDC_IOCON 0x04 ++#define MSDC_PS 0x08 ++#define MSDC_INT 0x0c ++#define MSDC_INTEN 0x10 ++#define MSDC_FIFOCS 0x14 ++#define SDC_CFG 0x30 ++#define SDC_CMD 0x34 ++#define SDC_ARG 0x38 ++#define SDC_STS 0x3c ++#define SDC_RESP0 0x40 ++#define SDC_RESP1 0x44 ++#define SDC_RESP2 0x48 ++#define SDC_RESP3 0x4c ++#define SDC_BLK_NUM 0x50 ++#define SDC_ACMD_RESP 0x80 ++#define MSDC_DMA_SA 0x90 ++#define MSDC_DMA_CTRL 0x98 ++#define MSDC_DMA_CFG 0x9c ++#define MSDC_PATCH_BIT 0xb0 ++#define MSDC_PATCH_BIT1 0xb4 ++#define MSDC_PAD_TUNE 0xec ++ ++/*--------------------------------------------------------------------------*/ ++/* Register Mask */ ++/*--------------------------------------------------------------------------*/ ++ ++/* MSDC_CFG mask */ ++#define MSDC_CFG_MODE (0x1 << 0) /* RW */ ++#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ ++#define MSDC_CFG_RST (0x1 << 2) /* RW */ ++#define MSDC_CFG_PIO (0x1 << 3) /* RW */ ++#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ ++#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ ++#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ ++#define MSDC_CFG_CKSTB (0x1 << 7) /* R */ ++#define MSDC_CFG_CKDIV (0xff << 8) /* RW */ ++#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ ++ ++/* MSDC_IOCON mask */ ++#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ ++#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ ++#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ ++#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ ++#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ ++#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ ++#define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ ++#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ ++#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ ++#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ ++#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ ++#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ ++#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ ++#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ ++#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ ++#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ ++ ++/* MSDC_PS mask */ ++#define MSDC_PS_CDEN (0x1 << 0) /* RW */ ++#define MSDC_PS_CDSTS (0x1 << 1) /* R */ ++#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ ++#define MSDC_PS_DAT (0xff << 16) /* R */ ++#define MSDC_PS_CMD (0x1 << 24) /* R */ ++#define MSDC_PS_WP (0x1 << 31) /* R */ ++ ++/* MSDC_INT mask */ ++#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ ++#define MSDC_INT_CDSC (0x1 << 1) /* W1C */ ++#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ ++#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ ++#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ ++#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ ++#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ ++#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ ++#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ ++#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ ++#define MSDC_INT_CSTA (0x1 << 11) /* R */ ++#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ ++#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ ++#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ ++#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ ++#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ ++#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ ++#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ ++#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ ++ ++/* MSDC_INTEN mask */ ++#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ ++#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ ++#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ ++#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ ++#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ ++#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ ++#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ ++#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ ++#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ ++#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ ++#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ ++#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ ++#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ ++#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ ++#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ ++#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ ++#define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ ++#define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ ++#define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ ++ ++/* MSDC_FIFOCS mask */ ++#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ ++#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ ++#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ ++ ++/* SDC_CFG mask */ ++#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ ++#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ ++#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ ++#define SDC_CFG_SDIO (0x1 << 19) /* RW */ ++#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ ++#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ ++#define SDC_CFG_DTOC (0xff << 24) /* RW */ ++ ++/* SDC_STS mask */ ++#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ ++#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ ++#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ ++ ++/* MSDC_DMA_CTRL mask */ ++#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ ++#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ ++#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ ++#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ ++#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ ++#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ ++ ++/* MSDC_DMA_CFG mask */ ++#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ ++#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ ++#define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ ++#define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ ++#define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ ++ ++/* MSDC_PATCH_BIT mask */ ++#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ ++#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) ++#define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) ++#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ ++#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ ++#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ ++#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ ++#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ ++#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ ++#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ ++#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ ++#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ ++ ++#define REQ_CMD_EIO (0x1 << 0) ++#define REQ_CMD_TMO (0x1 << 1) ++#define REQ_DAT_ERR (0x1 << 2) ++#define REQ_STOP_EIO (0x1 << 3) ++#define REQ_STOP_TMO (0x1 << 4) ++#define REQ_CMD_BUSY (0x1 << 5) ++ ++#define MSDC_PREPARE_FLAG (0x1 << 0) ++#define MSDC_ASYNC_FLAG (0x1 << 1) ++#define MSDC_MMAP_FLAG (0x1 << 2) ++ ++#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ ++#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ ++ ++/*--------------------------------------------------------------------------*/ ++/* Descriptor Structure */ ++/*--------------------------------------------------------------------------*/ ++struct mt_gpdma_desc { ++ u32 gpd_info; ++#define GPDMA_DESC_HWO (0x1 << 0) ++#define GPDMA_DESC_BDP (0x1 << 1) ++#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ ++#define GPDMA_DESC_INT (0x1 << 16) ++ u32 next; ++ u32 ptr; ++ u32 gpd_data_len; ++#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ ++#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ ++ u32 arg; ++ u32 blknum; ++ u32 cmd; ++}; ++ ++struct mt_bdma_desc { ++ u32 bd_info; ++#define BDMA_DESC_EOL (0x1 << 0) ++#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ ++#define BDMA_DESC_BLKPAD (0x1 << 17) ++#define BDMA_DESC_DWPAD (0x1 << 18) ++ u32 next; ++ u32 ptr; ++ u32 bd_data_len; ++#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ ++}; ++ ++struct msdc_dma { ++ struct scatterlist *sg; /* I/O scatter list */ ++ struct mt_gpdma_desc *gpd; /* pointer to gpd array */ ++ struct mt_bdma_desc *bd; /* pointer to bd array */ ++ dma_addr_t gpd_addr; /* the physical address of gpd array */ ++ dma_addr_t bd_addr; /* the physical address of bd array */ ++}; ++ ++struct msdc_host { ++ struct device *dev; ++ struct mmc_host *mmc; /* mmc structure */ ++ int cmd_rsp; ++ ++ spinlock_t lock; ++ struct mmc_request *mrq; ++ struct mmc_command *cmd; ++ struct mmc_data *data; ++ int error; ++ ++ void __iomem *base; /* host base address */ ++ ++ struct msdc_dma dma; /* dma channel */ ++ u64 dma_mask; ++ ++ u32 timeout_ns; /* data timeout ns */ ++ u32 timeout_clks; /* data timeout clks */ ++ ++ struct pinctrl *pinctrl; ++ struct pinctrl_state *pins_default; ++ struct pinctrl_state *pins_uhs; ++ struct delayed_work req_timeout; ++ int irq; /* host interrupt */ ++ ++ struct clk *src_clk; /* msdc source clock */ ++ struct clk *h_clk; /* msdc h_clk */ ++ u32 mclk; /* mmc subsystem clock frequency */ ++ u32 src_clk_freq; /* source clock frequency */ ++ u32 sclk; /* SD/MS bus clock frequency */ ++ bool ddr; ++ bool vqmmc_enabled; ++}; ++ ++static void sdr_set_bits(void __iomem *reg, u32 bs) ++{ ++ u32 val = readl(reg); ++ ++ val |= bs; ++ writel(val, reg); ++} ++ ++static void sdr_clr_bits(void __iomem *reg, u32 bs) ++{ ++ u32 val = readl(reg); ++ ++ val &= ~bs; ++ writel(val, reg); ++} ++ ++static void sdr_set_field(void __iomem *reg, u32 field, u32 val) ++{ ++ unsigned int tv = readl(reg); ++ ++ tv &= ~field; ++ tv |= ((val) << (ffs((unsigned int)field) - 1)); ++ writel(tv, reg); ++} ++ ++static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) ++{ ++ unsigned int tv = readl(reg); ++ ++ *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); ++} ++ ++static void msdc_reset_hw(struct msdc_host *host) ++{ ++ u32 val; ++ ++ sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); ++ while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) ++ cpu_relax(); ++ ++ sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); ++ while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) ++ cpu_relax(); ++ ++ val = readl(host->base + MSDC_INT); ++ writel(val, host->base + MSDC_INT); ++} ++ ++static void msdc_cmd_next(struct msdc_host *host, ++ struct mmc_request *mrq, struct mmc_command *cmd); ++ ++static u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | ++ MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | ++ MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; ++ ++static u8 msdc_dma_calcs(u8 *buf, u32 len) ++{ ++ u32 i, sum = 0; ++ ++ for (i = 0; i < len; i++) ++ sum += buf[i]; ++ return 0xff - (u8) sum; ++} ++ ++static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, ++ struct mmc_data *data) ++{ ++ unsigned int j, dma_len; ++ dma_addr_t dma_address; ++ u32 dma_ctrl; ++ struct scatterlist *sg; ++ struct mt_gpdma_desc *gpd; ++ struct mt_bdma_desc *bd; ++ ++ sg = data->sg; ++ ++ gpd = dma->gpd; ++ bd = dma->bd; ++ ++ /* modify gpd */ ++ gpd->gpd_info |= GPDMA_DESC_HWO; ++ gpd->gpd_info |= GPDMA_DESC_BDP; ++ /* need to clear first. use these bits to calc checksum */ ++ gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; ++ gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; ++ ++ /* modify bd */ ++ for_each_sg(data->sg, sg, data->sg_count, j) { ++ dma_address = sg_dma_address(sg); ++ dma_len = sg_dma_len(sg); ++ ++ /* init bd */ ++ bd[j].bd_info &= ~BDMA_DESC_BLKPAD; ++ bd[j].bd_info &= ~BDMA_DESC_DWPAD; ++ bd[j].ptr = (u32)dma_address; ++ bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; ++ bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); ++ ++ if (j == data->sg_count - 1) /* the last bd */ ++ bd[j].bd_info |= BDMA_DESC_EOL; ++ else ++ bd[j].bd_info &= ~BDMA_DESC_EOL; ++ ++ /* checksume need to clear first */ ++ bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; ++ bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; ++ } ++ ++ sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); ++ dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); ++ dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); ++ dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); ++ writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); ++ writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); ++} ++ ++static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) ++{ ++ struct mmc_data *data = mrq->data; ++ ++ if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { ++ bool read = (data->flags & MMC_DATA_READ) != 0; ++ ++ data->host_cookie |= MSDC_PREPARE_FLAG; ++ data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, ++ read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ } ++} ++ ++static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) ++{ ++ struct mmc_data *data = mrq->data; ++ ++ if (data->host_cookie & MSDC_ASYNC_FLAG) ++ return; ++ ++ if (data->host_cookie & MSDC_PREPARE_FLAG) { ++ bool read = (data->flags & MMC_DATA_READ) != 0; ++ ++ dma_unmap_sg(host->dev, data->sg, data->sg_len, ++ read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ data->host_cookie &= ~MSDC_PREPARE_FLAG; ++ } ++} ++ ++/* clock control primitives */ ++static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) ++{ ++ u32 timeout, clk_ns; ++ u32 mode = 0; ++ ++ host->timeout_ns = ns; ++ host->timeout_clks = clks; ++ if (host->sclk == 0) { ++ timeout = 0; ++ } else { ++ clk_ns = 1000000000UL / host->sclk; ++ timeout = (ns + clk_ns - 1) / clk_ns + clks; ++ /* in 1048576 sclk cycle unit */ ++ timeout = (timeout + (0x1 << 20) - 1) >> 20; ++ sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); ++ /*DDR mode will double the clk cycles for data timeout */ ++ timeout = mode >= 2 ? timeout * 2 : timeout; ++ timeout = timeout > 1 ? timeout - 1 : 0; ++ timeout = timeout > 255 ? 255 : timeout; ++ } ++ sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); ++} ++ ++static void msdc_gate_clock(struct msdc_host *host) ++{ ++ clk_disable_unprepare(host->src_clk); ++ clk_disable_unprepare(host->h_clk); ++} ++ ++static void msdc_ungate_clock(struct msdc_host *host) ++{ ++ clk_prepare_enable(host->h_clk); ++ clk_prepare_enable(host->src_clk); ++ while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) ++ cpu_relax(); ++} ++ ++static void msdc_set_mclk(struct msdc_host *host, int ddr, u32 hz) ++{ ++ u32 mode; ++ u32 flags; ++ u32 div; ++ u32 sclk; ++ ++ if (!hz) { ++ dev_dbg(host->dev, "set mclk to 0\n"); ++ host->mclk = 0; ++ sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); ++ return; ++ } ++ ++ flags = readl(host->base + MSDC_INTEN); ++ sdr_clr_bits(host->base + MSDC_INTEN, flags); ++ if (ddr) { /* may need to modify later */ ++ mode = 0x2; /* ddr mode and use divisor */ ++ if (hz >= (host->src_clk_freq >> 2)) { ++ div = 0; /* mean div = 1/4 */ ++ sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ ++ } else { ++ div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); ++ sclk = (host->src_clk_freq >> 2) / div; ++ div = (div >> 1); ++ } ++ } else if (hz >= host->src_clk_freq) { ++ mode = 0x1; /* no divisor */ ++ div = 0; ++ sclk = host->src_clk_freq; ++ } else { ++ mode = 0x0; /* use divisor */ ++ if (hz >= (host->src_clk_freq >> 1)) { ++ div = 0; /* mean div = 1/2 */ ++ sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ ++ } else { ++ div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); ++ sclk = (host->src_clk_freq >> 2) / div; ++ } ++ } ++ sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, ++ (mode << 8) | (div % 0xff)); ++ sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); ++ while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) ++ cpu_relax(); ++ host->sclk = sclk; ++ host->mclk = hz; ++ host->ddr = ddr; ++ /* need because clk changed. */ ++ msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); ++ sdr_set_bits(host->base + MSDC_INTEN, flags); ++ ++ dev_dbg(host->dev, "sclk: %d, ddr: %d\n", host->sclk, ddr); ++} ++ ++static inline u32 msdc_cmd_find_resp(struct msdc_host *host, ++ struct mmc_request *mrq, struct mmc_command *cmd) ++{ ++ u32 resp; ++ ++ switch (mmc_resp_type(cmd)) { ++ /* Actually, R1, R5, R6, R7 are the same */ ++ case MMC_RSP_R1: ++ resp = 0x1; ++ break; ++ case MMC_RSP_R1B: ++ resp = 0x7; ++ break; ++ case MMC_RSP_R2: ++ resp = 0x2; ++ break; ++ case MMC_RSP_R3: ++ resp = 0x3; ++ break; ++ case MMC_RSP_NONE: ++ default: ++ resp = 0x0; ++ break; ++ } ++ ++ return resp; ++} ++ ++static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, ++ struct mmc_request *mrq, struct mmc_command *cmd) ++{ ++ /* rawcmd : ++ * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | ++ * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode ++ */ ++ u32 opcode = cmd->opcode; ++ u32 resp = msdc_cmd_find_resp(host, mrq, cmd); ++ u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); ++ ++ host->cmd_rsp = resp; ++ ++ if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || ++ opcode == MMC_STOP_TRANSMISSION) ++ rawcmd |= (0x1 << 14); ++ else if (opcode == SD_SWITCH_VOLTAGE) ++ rawcmd |= (0x1 << 30); ++ else if (opcode == SD_APP_SEND_SCR || ++ opcode == SD_APP_SEND_NUM_WR_BLKS || ++ (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || ++ (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || ++ (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ++ rawcmd |= (0x1 << 11); ++ ++ if (cmd->data) { ++ struct mmc_data *data = cmd->data; ++ ++ if (mmc_op_multi(opcode)) { ++ if (mmc_card_mmc(host->mmc->card) && mrq->sbc && ++ !(mrq->sbc->arg & 0xFFFF0000)) ++ rawcmd |= 0x2 << 28; /* AutoCMD23 */ ++ } ++ ++ rawcmd |= ((data->blksz & 0xFFF) << 16); ++ if (data->flags & MMC_DATA_WRITE) ++ rawcmd |= (0x1 << 13); ++ if (data->blocks > 1) ++ rawcmd |= (0x2 << 11); ++ else ++ rawcmd |= (0x1 << 11); ++ /* Always use dma mode */ ++ sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); ++ ++ if (host->timeout_ns != data->timeout_ns || ++ host->timeout_clks != data->timeout_clks) ++ msdc_set_timeout(host, data->timeout_ns, ++ data->timeout_clks); ++ ++ writel(data->blocks, host->base + SDC_BLK_NUM); ++ } ++ return rawcmd; ++} ++ ++static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, ++ struct mmc_command *cmd, struct mmc_data *data) ++{ ++ bool read; ++ ++ WARN_ON(host->data); ++ host->data = data; ++ read = data->flags & MMC_DATA_READ; ++ ++ mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); ++ msdc_dma_setup(host, &host->dma, data); ++ sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); ++ sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); ++ dev_dbg(host->dev, "DMA start\n"); ++ dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", ++ __func__, cmd->opcode, data->blocks, read); ++} ++ ++static int msdc_auto_cmd_done(struct msdc_host *host, int events, ++ struct mmc_command *cmd) ++{ ++ u32 *rsp = cmd->resp; ++ ++ rsp[0] = readl(host->base + SDC_ACMD_RESP); ++ ++ if (events & MSDC_INT_ACMDRDY) { ++ cmd->error = 0; ++ } else { ++ msdc_reset_hw(host); ++ if (events & MSDC_INT_ACMDCRCERR) { ++ cmd->error = -EILSEQ; ++ host->error |= REQ_STOP_EIO; ++ } else if (events & MSDC_INT_ACMDTMO) { ++ cmd->error = -ETIMEDOUT; ++ host->error |= REQ_STOP_TMO; ++ } ++ dev_err(host->dev, ++ "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", ++ __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); ++ } ++ return cmd->error; ++} ++ ++static void msdc_track_cmd_data(struct msdc_host *host, ++ struct mmc_command *cmd, struct mmc_data *data) ++{ ++ if (host->error) ++ dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", ++ __func__, cmd->opcode, cmd->arg, host->error); ++} ++ ++static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) ++{ ++ unsigned long flags; ++ bool ret; ++ ++ ret = cancel_delayed_work(&host->req_timeout); ++ if (!ret) { ++ /* delay work already running */ ++ return; ++ } ++ spin_lock_irqsave(&host->lock, flags); ++ host->mrq = NULL; ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ msdc_track_cmd_data(host, mrq->cmd, mrq->data); ++ if (mrq->data) ++ msdc_unprepare_data(host, mrq); ++ mmc_request_done(host->mmc, mrq); ++} ++ ++/* returns true if command is fully handled; returns false otherwise */ ++static bool msdc_cmd_done(struct msdc_host *host, int events, ++ struct mmc_request *mrq, struct mmc_command *cmd) ++{ ++ bool done = false; ++ bool sbc_error; ++ unsigned long flags; ++ u32 *rsp = cmd->resp; ++ ++ if (mrq->sbc && cmd == mrq->cmd && ++ (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR ++ | MSDC_INT_ACMDTMO))) ++ msdc_auto_cmd_done(host, events, mrq->sbc); ++ ++ sbc_error = mrq->sbc && mrq->sbc->error; ++ ++ if (!sbc_error && !(events & (MSDC_INT_CMDRDY ++ | MSDC_INT_RSPCRCERR ++ | MSDC_INT_CMDTMO))) ++ return done; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ done = !host->cmd; ++ host->cmd = NULL; ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (done) ++ return true; ++ ++ sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY | ++ MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO | ++ MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR | ++ MSDC_INTEN_ACMDTMO); ++ writel(cmd->arg, host->base + SDC_ARG); ++ ++ if (cmd->flags & MMC_RSP_PRESENT) { ++ if (cmd->flags & MMC_RSP_136) { ++ rsp[0] = readl(host->base + SDC_RESP3); ++ rsp[1] = readl(host->base + SDC_RESP2); ++ rsp[2] = readl(host->base + SDC_RESP1); ++ rsp[3] = readl(host->base + SDC_RESP0); ++ } else { ++ rsp[0] = readl(host->base + SDC_RESP0); ++ } ++ } ++ ++ if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { ++ msdc_reset_hw(host); ++ if (events & MSDC_INT_RSPCRCERR) { ++ cmd->error = -EILSEQ; ++ host->error |= REQ_CMD_EIO; ++ } else if (events & MSDC_INT_CMDTMO) { ++ cmd->error = -ETIMEDOUT; ++ host->error |= REQ_CMD_TMO; ++ } ++ } ++ if (cmd->error) ++ dev_dbg(host->dev, ++ "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", ++ __func__, cmd->opcode, cmd->arg, rsp[0], ++ cmd->error); ++ ++ msdc_cmd_next(host, mrq, cmd); ++ return true; ++} ++ ++/* It is the core layer's responsibility to ensure card status ++ * is correct before issue a request. but host design do below ++ * checks recommended. ++ */ ++static inline bool msdc_cmd_is_ready(struct msdc_host *host, ++ struct mmc_request *mrq, struct mmc_command *cmd) ++{ ++ /* The max busy time we can endure is 20ms */ ++ unsigned long tmo = jiffies + msecs_to_jiffies(20); ++ ++ while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && ++ time_before(jiffies, tmo)) ++ cpu_relax(); ++ if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { ++ dev_err(host->dev, "CMD bus busy detected\n"); ++ host->error |= REQ_CMD_BUSY; ++ msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); ++ return false; ++ } ++ ++ if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { ++ tmo = jiffies + msecs_to_jiffies(20); ++ /* R1B or with data, should check SDCBUSY */ ++ while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && ++ time_before(jiffies, tmo)) ++ cpu_relax(); ++ if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { ++ dev_err(host->dev, "Controller busy detected\n"); ++ host->error |= REQ_CMD_BUSY; ++ msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); ++ return false; ++ } ++ } ++ return true; ++} ++ ++static void msdc_start_command(struct msdc_host *host, ++ struct mmc_request *mrq, struct mmc_command *cmd) ++{ ++ u32 rawcmd; ++ ++ WARN_ON(host->cmd); ++ host->cmd = cmd; ++ ++ if (!msdc_cmd_is_ready(host, mrq, cmd)) ++ return; ++ ++ if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || ++ readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { ++ dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); ++ msdc_reset_hw(host); ++ } ++ ++ cmd->error = 0; ++ rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); ++ mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); ++ ++ sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY | ++ MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO | ++ MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR | ++ MSDC_INTEN_ACMDTMO); ++ writel(cmd->arg, host->base + SDC_ARG); ++ writel(rawcmd, host->base + SDC_CMD); ++} ++ ++static void msdc_cmd_next(struct msdc_host *host, ++ struct mmc_request *mrq, struct mmc_command *cmd) ++{ ++ if (cmd->error || (mrq->sbc && mrq->sbc->error)) ++ msdc_request_done(host, mrq); ++ else if (cmd == mrq->sbc) ++ msdc_start_command(host, mrq, mrq->cmd); ++ else if (!cmd->data) ++ msdc_request_done(host, mrq); ++ else ++ msdc_start_data(host, mrq, cmd, cmd->data); ++} ++ ++static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct msdc_host *host = mmc_priv(mmc); ++ ++ host->error = 0; ++ WARN_ON(host->mrq); ++ host->mrq = mrq; ++ ++ if (mrq->data) ++ msdc_prepare_data(host, mrq); ++ ++ /* if SBC is required, we have HW option and SW option. ++ * if HW option is enabled, and SBC does not have "special" flags, ++ * use HW option, otherwise use SW option ++ */ ++ if (mrq->sbc && (!mmc_card_mmc(mmc->card) || ++ (mrq->sbc->arg & 0xFFFF0000))) ++ msdc_start_command(host, mrq, mrq->sbc); ++ else ++ msdc_start_command(host, mrq, mrq->cmd); ++} ++ ++static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, ++ bool is_first_req) ++{ ++ struct msdc_host *host = mmc_priv(mmc); ++ struct mmc_data *data = mrq->data; ++ ++ if (!data) ++ return; ++ ++ msdc_prepare_data(host, mrq); ++ data->host_cookie |= MSDC_ASYNC_FLAG; ++} ++ ++static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, ++ int err) ++{ ++ struct msdc_host *host = mmc_priv(mmc); ++ struct mmc_data *data; ++ ++ data = mrq->data; ++ if (!data) ++ return; ++ if (data->host_cookie) { ++ data->host_cookie &= ~MSDC_ASYNC_FLAG; ++ msdc_unprepare_data(host, mrq); ++ } ++} ++ ++static void msdc_data_xfer_next(struct msdc_host *host, ++ struct mmc_request *mrq, struct mmc_data *data) ++{ ++ if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && ++ (!data->bytes_xfered || !mrq->sbc)) ++ msdc_start_command(host, mrq, mrq->stop); ++ else ++ msdc_request_done(host, mrq); ++} ++ ++static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, ++ struct mmc_request *mrq, struct mmc_data *data) ++{ ++ struct mmc_command *stop = data->stop; ++ unsigned long flags; ++ bool done; ++ unsigned int check_data = events & ++ (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO ++ | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR ++ | MSDC_INT_DMA_PROTECT); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ done = !host->data; ++ if (check_data) ++ host->data = NULL; ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (done) ++ return true; ++ ++ if (check_data || (stop && stop->error)) { ++ dev_dbg(host->dev, "DMA status: 0x%8X\n", ++ readl(host->base + MSDC_DMA_CFG)); ++ sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, ++ 1); ++ while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) ++ cpu_relax(); ++ sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); ++ dev_dbg(host->dev, "DMA stop\n"); ++ ++ if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { ++ data->bytes_xfered = data->blocks * data->blksz; ++ } else { ++ dev_err(host->dev, "interrupt events: %x\n", events); ++ msdc_reset_hw(host); ++ host->error |= REQ_DAT_ERR; ++ data->bytes_xfered = 0; ++ ++ if (events & MSDC_INT_DATTMO) ++ data->error = -ETIMEDOUT; ++ ++ dev_err(host->dev, "%s: cmd=%d; blocks=%d", ++ __func__, mrq->cmd->opcode, data->blocks); ++ dev_err(host->dev, "data_error=%d xfer_size=%d\n", ++ (int)data->error, data->bytes_xfered); ++ } ++ ++ msdc_data_xfer_next(host, mrq, data); ++ done = true; ++ } ++ return done; ++} ++ ++static void msdc_set_buswidth(struct msdc_host *host, u32 width) ++{ ++ u32 val = readl(host->base + SDC_CFG); ++ ++ val &= ~SDC_CFG_BUSWIDTH; ++ ++ switch (width) { ++ default: ++ case MMC_BUS_WIDTH_1: ++ val |= (MSDC_BUS_1BITS << 16); ++ break; ++ case MMC_BUS_WIDTH_4: ++ val |= (MSDC_BUS_4BITS << 16); ++ break; ++ case MMC_BUS_WIDTH_8: ++ val |= (MSDC_BUS_8BITS << 16); ++ break; ++ } ++ ++ writel(val, host->base + SDC_CFG); ++ dev_dbg(host->dev, "Bus Width = %d", width); ++} ++ ++static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct msdc_host *host = mmc_priv(mmc); ++ int min_uv, max_uv; ++ int ret = 0; ++ ++ if (!IS_ERR(mmc->supply.vqmmc)) { ++ if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { ++ min_uv = 3300000; ++ max_uv = 3300000; ++ } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { ++ min_uv = 1800000; ++ max_uv = 1800000; ++ } else { ++ dev_err(host->dev, "Unsupported signal voltage!\n"); ++ return -EINVAL; ++ } ++ ++ ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); ++ if (ret) { ++ dev_err(host->dev, ++ "Regulator set error %d: %d - %d\n", ++ ret, min_uv, max_uv); ++ } else { ++ /* Apply different pinctrl settings for different signal voltage */ ++ if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) ++ pinctrl_select_state(host->pinctrl, host->pins_uhs); ++ else ++ pinctrl_select_state(host->pinctrl, host->pins_default); ++ } ++ } ++ return ret; ++} ++ ++static int msdc_card_busy(struct mmc_host *mmc) ++{ ++ struct msdc_host *host = mmc_priv(mmc); ++ u32 status = readl(host->base + MSDC_PS); ++ ++ /* check if any pin between dat[0:3] is low */ ++ if (((status >> 16) & 0xf) != 0xf) ++ return 1; ++ ++ return 0; ++} ++ ++static void msdc_request_timeout(struct work_struct *work) ++{ ++ struct msdc_host *host = container_of(work, struct msdc_host, ++ req_timeout.work); ++ ++ /* simulate HW timeout status */ ++ dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); ++ if (host->mrq) { ++ dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, ++ host->mrq, host->mrq->cmd->opcode); ++ if (host->cmd) { ++ dev_err(host->dev, "%s: aborting cmd=%d\n", ++ __func__, host->cmd->opcode); ++ msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, ++ host->cmd); ++ } else if (host->data) { ++ dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", ++ __func__, host->mrq->cmd->opcode, ++ host->data->blocks); ++ msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, ++ host->data); ++ } ++ } ++} ++ ++static irqreturn_t msdc_irq(int irq, void *dev_id) ++{ ++ struct msdc_host *host = (struct msdc_host *) dev_id; ++ ++ while (true) { ++ unsigned long flags; ++ struct mmc_request *mrq; ++ struct mmc_command *cmd; ++ struct mmc_data *data; ++ u32 events, event_mask; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ events = readl(host->base + MSDC_INT); ++ event_mask = readl(host->base + MSDC_INTEN); ++ /* clear interrupts */ ++ writel(events & event_mask, host->base + MSDC_INT); ++ ++ mrq = host->mrq; ++ cmd = host->cmd; ++ data = host->data; ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (!(events & event_mask)) ++ break; ++ ++ if (!mrq) { ++ dev_err(host->dev, ++ "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", ++ __func__, events, event_mask); ++ WARN_ON(1); ++ break; ++ } ++ ++ dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); ++ ++ if (cmd) ++ msdc_cmd_done(host, events, mrq, cmd); ++ else if (data) ++ msdc_data_xfer_done(host, events, mrq, data); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void msdc_init_hw(struct msdc_host *host) ++{ ++ u32 val; ++ ++ /* Configure to MMC/SD mode, clock free running */ ++ sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); ++ ++ /* Reset */ ++ msdc_reset_hw(host); ++ ++ /* Disable card detection */ ++ sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); ++ ++ /* Disable and clear all interrupts */ ++ writel(0, host->base + MSDC_INTEN); ++ val = readl(host->base + MSDC_INT); ++ writel(val, host->base + MSDC_INT); ++ ++ writel(0, host->base + MSDC_PAD_TUNE); ++ writel(0, host->base + MSDC_IOCON); ++ sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); ++ writel(0x403c004f, host->base + MSDC_PATCH_BIT); ++ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); ++ writel(0xffff0089, host->base + MSDC_PATCH_BIT1); ++ /* Configure to enable SDIO mode. ++ * it's must otherwise sdio cmd5 failed ++ */ ++ sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); ++ ++ /* disable detect SDIO device interrupt function */ ++ sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); ++ ++ /* Configure to default data timeout */ ++ sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); ++ ++ dev_dbg(host->dev, "init hardware done!"); ++} ++ ++static void msdc_deinit_hw(struct msdc_host *host) ++{ ++ u32 val; ++ /* Disable and clear all interrupts */ ++ writel(0, host->base + MSDC_INTEN); ++ ++ val = readl(host->base + MSDC_INT); ++ writel(val, host->base + MSDC_INT); ++} ++ ++/* init gpd and bd list in msdc_drv_probe */ ++static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) ++{ ++ struct mt_gpdma_desc *gpd = dma->gpd; ++ struct mt_bdma_desc *bd = dma->bd; ++ int i; ++ ++ memset(gpd, 0, sizeof(struct mt_gpdma_desc)); ++ ++ gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ ++ gpd->ptr = (u32)dma->bd_addr; /* physical address */ ++ ++ memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); ++ for (i = 0; i < (MAX_BD_NUM - 1); i++) ++ bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); ++} ++ ++static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct msdc_host *host = mmc_priv(mmc); ++ int ret; ++ u32 ddr = 0; ++ ++ if (ios->timing == MMC_TIMING_UHS_DDR50 || ++ ios->timing == MMC_TIMING_MMC_DDR52) ++ ddr = 1; ++ ++ msdc_set_buswidth(host, ios->bus_width); ++ ++ /* Suspend/Resume will do power off/on */ ++ switch (ios->power_mode) { ++ case MMC_POWER_UP: ++ if (!IS_ERR(mmc->supply.vmmc)) { ++ ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ++ ios->vdd); ++ if (ret) { ++ dev_err(host->dev, "Failed to set vmmc power!\n"); ++ return; ++ } ++ } ++ break; ++ case MMC_POWER_ON: ++ if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { ++ ret = regulator_enable(mmc->supply.vqmmc); ++ if (ret) ++ dev_err(host->dev, "Failed to set vqmmc power!\n"); ++ else ++ host->vqmmc_enabled = true; ++ } ++ break; ++ case MMC_POWER_OFF: ++ if (!IS_ERR(mmc->supply.vmmc)) ++ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); ++ ++ if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { ++ regulator_disable(mmc->supply.vqmmc); ++ host->vqmmc_enabled = false; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ if (host->mclk != ios->clock || host->ddr != ddr) ++ msdc_set_mclk(host, ddr, ios->clock); ++} ++ ++static struct mmc_host_ops mt_msdc_ops = { ++ .post_req = msdc_post_req, ++ .pre_req = msdc_pre_req, ++ .request = msdc_ops_request, ++ .set_ios = msdc_ops_set_ios, ++ .start_signal_voltage_switch = msdc_ops_switch_volt, ++ .card_busy = msdc_card_busy, ++}; ++ ++static int msdc_drv_probe(struct platform_device *pdev) ++{ ++ struct mmc_host *mmc; ++ struct msdc_host *host; ++ struct resource *res; ++ int ret; ++ ++ if (!pdev->dev.of_node) { ++ dev_err(&pdev->dev, "No DT found\n"); ++ return -EINVAL; ++ } ++ /* Allocate MMC host for this device */ ++ mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); ++ if (!mmc) ++ return -ENOMEM; ++ ++ host = mmc_priv(mmc); ++ ret = mmc_of_parse(mmc); ++ if (ret) ++ goto host_free; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ host->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(host->base)) { ++ ret = PTR_ERR(host->base); ++ goto host_free; ++ } ++ ++ ret = mmc_regulator_get_supply(mmc); ++ if (ret == -EPROBE_DEFER) ++ goto host_free; ++ ++ host->src_clk = devm_clk_get(&pdev->dev, "source"); ++ if (IS_ERR(host->src_clk)) { ++ ret = PTR_ERR(host->src_clk); ++ goto host_free; ++ } ++ ++ host->h_clk = devm_clk_get(&pdev->dev, "hclk"); ++ if (IS_ERR(host->h_clk)) { ++ ret = PTR_ERR(host->h_clk); ++ goto host_free; ++ } ++ ++ host->irq = platform_get_irq(pdev, 0); ++ if (host->irq < 0) { ++ ret = -EINVAL; ++ goto host_free; ++ } ++ ++ host->pinctrl = devm_pinctrl_get(&pdev->dev); ++ if (IS_ERR(host->pinctrl)) { ++ ret = PTR_ERR(host->pinctrl); ++ dev_err(&pdev->dev, "Cannot find pinctrl!\n"); ++ goto host_free; ++ } ++ ++ host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); ++ if (IS_ERR(host->pins_default)) { ++ ret = PTR_ERR(host->pins_default); ++ dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); ++ goto host_free; ++ } ++ ++ host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); ++ if (IS_ERR(host->pins_uhs)) { ++ ret = PTR_ERR(host->pins_uhs); ++ dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); ++ goto host_free; ++ } ++ ++ host->dev = &pdev->dev; ++ host->mmc = mmc; ++ host->src_clk_freq = clk_get_rate(host->src_clk); ++ /* Set host parameters to mmc */ ++ mmc->ops = &mt_msdc_ops; ++ mmc->f_min = host->src_clk_freq / (4 * 255); ++ ++ mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; ++ /* MMC core transfer sizes tunable parameters */ ++ mmc->max_segs = MAX_BD_NUM; ++ mmc->max_seg_size = BDMA_DESC_BUFLEN; ++ mmc->max_blk_size = 2048; ++ mmc->max_req_size = 512 * 1024; ++ mmc->max_blk_count = mmc->max_req_size / 512; ++ host->dma_mask = DMA_BIT_MASK(32); ++ mmc_dev(mmc)->dma_mask = &host->dma_mask; ++ ++ host->timeout_clks = 3 * 1048576; ++ host->dma.gpd = dma_alloc_coherent(&pdev->dev, ++ sizeof(struct mt_gpdma_desc), ++ &host->dma.gpd_addr, GFP_KERNEL); ++ host->dma.bd = dma_alloc_coherent(&pdev->dev, ++ MAX_BD_NUM * sizeof(struct mt_bdma_desc), ++ &host->dma.bd_addr, GFP_KERNEL); ++ if (!host->dma.gpd || !host->dma.bd) { ++ ret = -ENOMEM; ++ goto release_mem; ++ } ++ msdc_init_gpd_bd(host, &host->dma); ++ INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); ++ spin_lock_init(&host->lock); ++ ++ platform_set_drvdata(pdev, mmc); ++ msdc_ungate_clock(host); ++ msdc_init_hw(host); ++ ++ ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, ++ IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); ++ if (ret) ++ goto release; ++ ++ ret = mmc_add_host(mmc); ++ if (ret) ++ goto release; ++ ++ return 0; ++ ++release: ++ platform_set_drvdata(pdev, NULL); ++ msdc_deinit_hw(host); ++ msdc_gate_clock(host); ++release_mem: ++ if (host->dma.gpd) ++ dma_free_coherent(&pdev->dev, ++ sizeof(struct mt_gpdma_desc), ++ host->dma.gpd, host->dma.gpd_addr); ++ if (host->dma.bd) ++ dma_free_coherent(&pdev->dev, ++ MAX_BD_NUM * sizeof(struct mt_bdma_desc), ++ host->dma.bd, host->dma.bd_addr); ++host_free: ++ mmc_free_host(mmc); ++ ++ return ret; ++} ++ ++static int msdc_drv_remove(struct platform_device *pdev) ++{ ++ struct mmc_host *mmc; ++ struct msdc_host *host; ++ ++ mmc = platform_get_drvdata(pdev); ++ host = mmc_priv(mmc); ++ ++ platform_set_drvdata(pdev, NULL); ++ mmc_remove_host(host->mmc); ++ msdc_deinit_hw(host); ++ msdc_gate_clock(host); ++ ++ dma_free_coherent(&pdev->dev, ++ sizeof(struct mt_gpdma_desc), ++ host->dma.gpd, host->dma.gpd_addr); ++ dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), ++ host->dma.bd, host->dma.bd_addr); ++ ++ mmc_free_host(host->mmc); ++ ++ return 0; ++} ++ ++static const struct of_device_id msdc_of_ids[] = { ++ { .compatible = "mediatek,mt8135-mmc", }, ++ {} ++}; ++ ++static struct platform_driver mt_msdc_driver = { ++ .probe = msdc_drv_probe, ++ .remove = msdc_drv_remove, ++ .driver = { ++ .name = "mtk-msdc", ++ .of_match_table = msdc_of_ids, ++ }, ++}; ++ ++module_platform_driver(mt_msdc_driver); ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); diff --git a/target/linux/mediatek/patches/0036-mmc-mediatek-Add-PM-support-for-MMC-driver.patch b/target/linux/mediatek/patches/0036-mmc-mediatek-Add-PM-support-for-MMC-driver.patch new file mode 100644 index 0000000..e9ba31d --- /dev/null +++ b/target/linux/mediatek/patches/0036-mmc-mediatek-Add-PM-support-for-MMC-driver.patch @@ -0,0 +1,209 @@ +From 4ca0e8a959569852b520b607d39ce6ceeeb0f518 Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 15 Jun 2015 19:20:49 +0800 +Subject: [PATCH 36/76] mmc: mediatek: Add PM support for MMC driver + +Add PM support for Mediatek MMC driver +Save/restore registers when PM + +Signed-off-by: Chaotian Jing +--- + drivers/mmc/host/mtk-sd.c | 89 +++++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 86 insertions(+), 3 deletions(-) + +diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c +index 952be2e..7c20f28 100644 +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -22,6 +22,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + +@@ -212,6 +214,7 @@ + #define MSDC_ASYNC_FLAG (0x1 << 1) + #define MSDC_MMAP_FLAG (0x1 << 2) + ++#define MTK_MMC_AUTOSUSPEND_DELAY 50 + #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ + #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ + +@@ -254,6 +257,15 @@ struct msdc_dma { + dma_addr_t bd_addr; /* the physical address of bd array */ + }; + ++struct msdc_save_para { ++ u32 msdc_cfg; ++ u32 iocon; ++ u32 sdc_cfg; ++ u32 pad_tune; ++ u32 patch_bit0; ++ u32 patch_bit1; ++}; ++ + struct msdc_host { + struct device *dev; + struct mmc_host *mmc; /* mmc structure */ +@@ -286,6 +298,7 @@ struct msdc_host { + u32 sclk; /* SD/MS bus clock frequency */ + bool ddr; + bool vqmmc_enabled; ++ struct msdc_save_para save_para; /* used when gate HCLK */ + }; + + static void sdr_set_bits(void __iomem *reg, u32 bs) +@@ -677,6 +690,9 @@ static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) + if (mrq->data) + msdc_unprepare_data(host, mrq); + mmc_request_done(host->mmc, mrq); ++ ++ pm_runtime_mark_last_busy(host->dev); ++ pm_runtime_put_autosuspend(host->dev); + } + + /* returns true if command is fully handled; returns false otherwise */ +@@ -831,6 +847,8 @@ static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) + WARN_ON(host->mrq); + host->mrq = mrq; + ++ pm_runtime_get_sync(host->dev); ++ + if (mrq->data) + msdc_prepare_data(host, mrq); + +@@ -1145,6 +1163,8 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) + int ret; + u32 ddr = 0; + ++ pm_runtime_get_sync(host->dev); ++ + if (ios->timing == MMC_TIMING_UHS_DDR50 || + ios->timing == MMC_TIMING_MMC_DDR52) + ddr = 1; +@@ -1159,7 +1179,7 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) + ios->vdd); + if (ret) { + dev_err(host->dev, "Failed to set vmmc power!\n"); +- return; ++ goto end; + } + } + break; +@@ -1187,6 +1207,10 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) + + if (host->mclk != ios->clock || host->ddr != ddr) + msdc_set_mclk(host, ddr, ios->clock); ++ ++end: ++ pm_runtime_mark_last_busy(host->dev); ++ pm_runtime_put_autosuspend(host->dev); + } + + static struct mmc_host_ops mt_msdc_ops = { +@@ -1310,12 +1334,18 @@ static int msdc_drv_probe(struct platform_device *pdev) + if (ret) + goto release; + ++ pm_runtime_set_active(host->dev); ++ pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); ++ pm_runtime_use_autosuspend(host->dev); ++ pm_runtime_enable(host->dev); + ret = mmc_add_host(mmc); ++ + if (ret) +- goto release; ++ goto end; + + return 0; +- ++end: ++ pm_runtime_disable(host->dev); + release: + platform_set_drvdata(pdev, NULL); + msdc_deinit_hw(host); +@@ -1343,11 +1373,15 @@ static int msdc_drv_remove(struct platform_device *pdev) + mmc = platform_get_drvdata(pdev); + host = mmc_priv(mmc); + ++ pm_runtime_get_sync(host->dev); ++ + platform_set_drvdata(pdev, NULL); + mmc_remove_host(host->mmc); + msdc_deinit_hw(host); + msdc_gate_clock(host); + ++ pm_runtime_disable(host->dev); ++ pm_runtime_put_noidle(host->dev); + dma_free_coherent(&pdev->dev, + sizeof(struct mt_gpdma_desc), + host->dma.gpd, host->dma.gpd_addr); +@@ -1359,6 +1393,54 @@ static int msdc_drv_remove(struct platform_device *pdev) + return 0; + } + ++#ifdef CONFIG_PM ++static void msdc_save_reg(struct msdc_host *host) ++{ ++ host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); ++ host->save_para.iocon = readl(host->base + MSDC_IOCON); ++ host->save_para.sdc_cfg = readl(host->base + SDC_CFG); ++ host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); ++ host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); ++ host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); ++} ++ ++static void msdc_restore_reg(struct msdc_host *host) ++{ ++ writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); ++ writel(host->save_para.iocon, host->base + MSDC_IOCON); ++ writel(host->save_para.sdc_cfg, host->base + SDC_CFG); ++ writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); ++ writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); ++ writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); ++} ++ ++static int msdc_runtime_suspend(struct device *dev) ++{ ++ struct mmc_host *mmc = dev_get_drvdata(dev); ++ struct msdc_host *host = mmc_priv(mmc); ++ ++ msdc_save_reg(host); ++ msdc_gate_clock(host); ++ return 0; ++} ++ ++static int msdc_runtime_resume(struct device *dev) ++{ ++ struct mmc_host *mmc = dev_get_drvdata(dev); ++ struct msdc_host *host = mmc_priv(mmc); ++ ++ msdc_ungate_clock(host); ++ msdc_restore_reg(host); ++ return 0; ++} ++#endif ++ ++static const struct dev_pm_ops msdc_dev_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++ SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) ++}; ++ + static const struct of_device_id msdc_of_ids[] = { + { .compatible = "mediatek,mt8135-mmc", }, + {} +@@ -1370,6 +1452,7 @@ static struct platform_driver mt_msdc_driver = { + .driver = { + .name = "mtk-msdc", + .of_match_table = msdc_of_ids, ++ .pm = &msdc_dev_pm_ops, + }, + }; + +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0037-arm64-mediatek-Add-Mediatek-MMC-support-in-defconfig.patch b/target/linux/mediatek/patches/0037-arm64-mediatek-Add-Mediatek-MMC-support-in-defconfig.patch new file mode 100644 index 0000000..7d9143f --- /dev/null +++ b/target/linux/mediatek/patches/0037-arm64-mediatek-Add-Mediatek-MMC-support-in-defconfig.patch @@ -0,0 +1,28 @@ +From 0435517df474d830711b7e1dc56e2d47ae5083b5 Mon Sep 17 00:00:00 2001 +From: Eddie Huang +Date: Mon, 15 Jun 2015 19:20:52 +0800 +Subject: [PATCH 37/76] arm64: mediatek: Add Mediatek MMC support in defconfig + +Add CONFIG_MMC_MTK=y in defconfig + +Signed-off-by: Chaotian Jing +Signed-off-by: Eddie Huang +--- + arch/arm64/configs/defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 2ed7449..e03288a 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -138,6 +138,7 @@ CONFIG_MMC_ARMMMCI=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_PLTFM=y + CONFIG_MMC_SPI=y ++CONFIG_MMC_MTK=y + CONFIG_RTC_CLASS=y + CONFIG_RTC_DRV_EFI=y + CONFIG_RTC_DRV_XGENE=y +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0038-ARM-multi_v7_defconfig-Enable-Mediatek-MMC-support-m.patch b/target/linux/mediatek/patches/0038-ARM-multi_v7_defconfig-Enable-Mediatek-MMC-support-m.patch new file mode 100644 index 0000000..35dc99f --- /dev/null +++ b/target/linux/mediatek/patches/0038-ARM-multi_v7_defconfig-Enable-Mediatek-MMC-support-m.patch @@ -0,0 +1,29 @@ +From 3069c2bfe0da7c6c13a61b0e1d457fd0e021e27b Mon Sep 17 00:00:00 2001 +From: Yingjoe Chen +Date: Mon, 15 Jun 2015 19:20:53 +0800 +Subject: [PATCH 38/76] ARM: multi_v7_defconfig: Enable Mediatek MMC support + multi-v7 + +Add CONFIG_MMC_MTK=y in defconfig + +Signed-off-by: Yingjoe Chen +Signed-off-by: Chaotian Jing +--- + arch/arm/configs/multi_v7_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig +index fbbb191..bfa09ab 100644 +--- a/arch/arm/configs/multi_v7_defconfig ++++ b/arch/arm/configs/multi_v7_defconfig +@@ -477,6 +477,7 @@ CONFIG_MMC_DW_EXYNOS=y + CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SH_MMCIF=y + CONFIG_MMC_SUNXI=y ++CONFIG_MMC_MTK=y + CONFIG_NEW_LEDS=y + CONFIG_LEDS_CLASS=y + CONFIG_LEDS_GPIO=y +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0039-clocksource-mediatek-Don-t-run-event_handler-if-it-i.patch b/target/linux/mediatek/patches/0039-clocksource-mediatek-Don-t-run-event_handler-if-it-i.patch new file mode 100644 index 0000000..aabe849 --- /dev/null +++ b/target/linux/mediatek/patches/0039-clocksource-mediatek-Don-t-run-event_handler-if-it-i.patch @@ -0,0 +1,32 @@ +From 9d4cba66a74cbdf25f43a7a8cc360370214ba5fc Mon Sep 17 00:00:00 2001 +From: "Joe.C" +Date: Fri, 1 May 2015 15:43:24 +0800 +Subject: [PATCH 39/76] clocksource: mediatek: Don't run event_handler if it + is NULL + +Spurious timer interrupt is noticed in mtk timer and cause kernel +crash. In mtk_timer_interrupt(), only run event_handler if it is +not NULL. + +Signed-off-by: Yingjoe Chen +--- + drivers/clocksource/mtk_timer.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c +index 68ab423..85e0ab5 100644 +--- a/drivers/clocksource/mtk_timer.c ++++ b/drivers/clocksource/mtk_timer.c +@@ -143,7 +143,8 @@ static irqreturn_t mtk_timer_interrupt(int irq, void *dev_id) + + /* Acknowledge timer0 irq */ + writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); +- evt->dev.event_handler(&evt->dev); ++ if (evt->dev.event_handler) ++ evt->dev.event_handler(&evt->dev); + + return IRQ_HANDLED; + } +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0040-clocksource-mediatek-Use-GPT-as-sched-clock-source.patch b/target/linux/mediatek/patches/0040-clocksource-mediatek-Use-GPT-as-sched-clock-source.patch new file mode 100644 index 0000000..c6b66af --- /dev/null +++ b/target/linux/mediatek/patches/0040-clocksource-mediatek-Use-GPT-as-sched-clock-source.patch @@ -0,0 +1,51 @@ +From 3b3c2406dd9797bc806e0ce756142a33d209c4e8 Mon Sep 17 00:00:00 2001 +From: "Joe.C" +Date: Fri, 1 May 2015 15:43:25 +0800 +Subject: [PATCH 40/76] clocksource: mediatek: Use GPT as sched clock source + +When cpu is in deep idle, arch timer will stop counting. Setup GPT as +sched clock source so it can keep counting in idle. + +Signed-off-by: Yingjoe Chen +--- + drivers/clocksource/mtk_timer.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c +index 85e0ab5..9a90c7b 100644 +--- a/drivers/clocksource/mtk_timer.c ++++ b/drivers/clocksource/mtk_timer.c +@@ -24,6 +24,7 @@ + #include + #include + #include ++#include + #include + + #define GPT_IRQ_EN_REG 0x00 +@@ -59,6 +60,13 @@ struct mtk_clock_event_device { + struct clock_event_device dev; + }; + ++static void __iomem *gpt_base __read_mostly; ++ ++static u64 notrace mtk_read_sched_clock(void) ++{ ++ return readl_relaxed(gpt_base + TIMER_CNT_REG(GPT_CLK_SRC)); ++} ++ + static inline struct mtk_clock_event_device *to_mtk_clk( + struct clock_event_device *c) + { +@@ -239,6 +247,8 @@ static void __init mtk_timer_init(struct device_node *node) + mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); + clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), + node->name, rate, 300, 32, clocksource_mmio_readl_up); ++ gpt_base = evt->gpt_base; ++ sched_clock_register(mtk_read_sched_clock, 32, rate); + + /* Configure clock event */ + mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0041-arm-mediatek-enable-gpt6-on-boot-up-to-make-arch-tim.patch b/target/linux/mediatek/patches/0041-arm-mediatek-enable-gpt6-on-boot-up-to-make-arch-tim.patch new file mode 100644 index 0000000..728792c --- /dev/null +++ b/target/linux/mediatek/patches/0041-arm-mediatek-enable-gpt6-on-boot-up-to-make-arch-tim.patch @@ -0,0 +1,63 @@ +From eec99287ace37015ed313b4fc27ba205a158b66c Mon Sep 17 00:00:00 2001 +From: Matthias Brugger +Date: Fri, 1 May 2015 15:43:26 +0800 +Subject: [PATCH 41/76] arm: mediatek: enable gpt6 on boot up to make arch + timer working + +We enable GTP6 which ungates the arch timer clock. +In the future this should be done in the bootloader. + +Signed-off-by: Matthias Brugger +Signed-off-by: Yingjoe Chen +--- + arch/arm/mach-mediatek/mediatek.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c +index a954900..6b38d67 100644 +--- a/arch/arm/mach-mediatek/mediatek.c ++++ b/arch/arm/mach-mediatek/mediatek.c +@@ -16,6 +16,34 @@ + */ + #include + #include ++#include ++#include ++#include ++ ++ ++#define GPT6_CON_MT65xx 0x10008060 ++#define GPT_ENABLE 0x31 ++ ++static void __init mediatek_timer_init(void) ++{ ++ void __iomem *gpt_base = 0; ++ ++ if (of_machine_is_compatible("mediatek,mt6589") || ++ of_machine_is_compatible("mediatek,mt8135") || ++ of_machine_is_compatible("mediatek,mt8127")) { ++ /* turn on GPT6 which ungates arch timer clocks */ ++ gpt_base = ioremap(GPT6_CON_MT65xx, 0x04); ++ } ++ ++ /* enabel clock and set to free-run */ ++ if (gpt_base) { ++ writel(GPT_ENABLE, gpt_base); ++ iounmap(gpt_base); ++ } ++ ++ of_clk_init(NULL); ++ clocksource_of_init(); ++}; + + static const char * const mediatek_board_dt_compat[] = { + "mediatek,mt6589", +@@ -27,4 +55,5 @@ static const char * const mediatek_board_dt_compat[] = { + + DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)") + .dt_compat = mediatek_board_dt_compat, ++ .init_time = mediatek_timer_init, + MACHINE_END +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0042-ARM-mediatek-add-smp-bringup-code.patch b/target/linux/mediatek/patches/0042-ARM-mediatek-add-smp-bringup-code.patch new file mode 100644 index 0000000..8910532 --- /dev/null +++ b/target/linux/mediatek/patches/0042-ARM-mediatek-add-smp-bringup-code.patch @@ -0,0 +1,178 @@ +From daa2c1f9202f08628d4f91a1cf4dafb44c9bcafe Mon Sep 17 00:00:00 2001 +From: "Joe.C" +Date: Fri, 1 May 2015 15:43:28 +0800 +Subject: [PATCH 42/76] ARM: mediatek: add smp bringup code + +Add support for booting secondary CPUs on mt6589, mt8127 +and mt8135. + +Signed-off-by: Yingjoe Chen +--- + arch/arm/mach-mediatek/Makefile | 3 + + arch/arm/mach-mediatek/platsmp.c | 145 ++++++++++++++++++++++++++++++++++++++ + 2 files changed, 148 insertions(+) + create mode 100644 arch/arm/mach-mediatek/platsmp.c + +diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile +index 43e619f..2116460 100644 +--- a/arch/arm/mach-mediatek/Makefile ++++ b/arch/arm/mach-mediatek/Makefile +@@ -1 +1,4 @@ ++ifeq ($(CONFIG_SMP),y) ++obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o ++endif + obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o +diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c +new file mode 100644 +index 0000000..e266b3d +--- /dev/null ++++ b/arch/arm/mach-mediatek/platsmp.c +@@ -0,0 +1,145 @@ ++/* ++ * arch/arm/mach-mediatek/platsmp.c ++ * ++ * Copyright (c) 2014 Mediatek Inc. ++ * Author: Shunli Wang ++ * Yingjoe Chen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MTK_MAX_CPU 8 ++#define MTK_SMP_REG_SIZE 0x1000 ++ ++struct mtk_smp_boot_info { ++ unsigned long smp_base; ++ unsigned int jump_reg; ++ unsigned int boot_reg; ++ unsigned int core_keys[MTK_MAX_CPU - 1]; ++ unsigned int core_regs[MTK_MAX_CPU - 1]; ++}; ++ ++static const struct mtk_smp_boot_info mtk_mt8135_tz_boot = { ++ 0x80002000, 1020, 1012, ++ { 0x534c4131, 0x4c415332, 0x41534c33 }, ++ { 1016, 1016, 1016}, ++}; ++ ++static const struct mtk_smp_boot_info mtk_mt6589_boot = { ++ 0x10002000, 0x34, 0x30, ++ { 0x534c4131, 0x4c415332, 0x41534c33 }, ++ { 0x38, 0x3c, 0x40 }, ++}; ++ ++static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = { ++ { .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot }, ++ { .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot }, ++}; ++ ++static const struct of_device_id mtk_smp_boot_infos[] __initconst = { ++ { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot }, ++}; ++ ++static void __iomem *mtk_smp_base; ++static const struct mtk_smp_boot_info *mtk_smp_info; ++ ++static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ if (!mtk_smp_base) ++ return -EINVAL; ++ ++ if (!mtk_smp_info->core_keys[cpu-1]) ++ return -EINVAL; ++ ++ writel_relaxed(mtk_smp_info->core_keys[cpu-1], ++ mtk_smp_base + mtk_smp_info->core_regs[cpu-1]); ++ ++ arch_send_wakeup_ipi_mask(cpumask_of(cpu)); ++ ++ return 0; ++} ++ ++static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone) ++{ ++ int i, num; ++ const struct of_device_id *infos; ++ ++ if (trustzone) { ++ num = ARRAY_SIZE(mtk_tz_smp_boot_infos); ++ infos = mtk_tz_smp_boot_infos; ++ } else { ++ num = ARRAY_SIZE(mtk_smp_boot_infos); ++ infos = mtk_smp_boot_infos; ++ } ++ ++ /* Find smp boot info for this SoC */ ++ for (i = 0; i < num; i++) { ++ if (of_machine_is_compatible(infos[i].compatible)) { ++ mtk_smp_info = infos[i].data; ++ break; ++ } ++ } ++ ++ if (!mtk_smp_info) { ++ pr_err("%s: Device is not supported\n", __func__); ++ return; ++ } ++ ++ if (trustzone) { ++ if (memblock_reserve(mtk_smp_info->smp_base, MTK_SMP_REG_SIZE)) { ++ pr_err("%s: Can't reserve smp memory\n", __func__); ++ return; ++ } ++ mtk_smp_base = phys_to_virt(mtk_smp_info->smp_base); ++ } else { ++ mtk_smp_base = ioremap(mtk_smp_info->smp_base, MTK_SMP_REG_SIZE); ++ if (!mtk_smp_base) { ++ pr_err("%s: Can't remap %lx\n", __func__, ++ mtk_smp_info->smp_base); ++ return; ++ } ++ } ++ ++ /* ++ * write the address of slave startup address into the system-wide ++ * jump register ++ */ ++ writel_relaxed(virt_to_phys(secondary_startup), ++ mtk_smp_base + mtk_smp_info->jump_reg); ++} ++ ++static void __init mtk_tz_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ __mtk_smp_prepare_cpus(max_cpus, 1); ++} ++ ++static void __init mtk_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ __mtk_smp_prepare_cpus(max_cpus, 0); ++} ++ ++static struct smp_operations mt81xx_tz_smp_ops __initdata = { ++ .smp_prepare_cpus = mtk_tz_smp_prepare_cpus, ++ .smp_boot_secondary = mtk_boot_secondary, ++}; ++CPU_METHOD_OF_DECLARE(mt81xx_tz_smp, "mediatek,mt81xx-tz-smp", &mt81xx_tz_smp_ops); ++ ++static struct smp_operations mt65xx_smp_ops __initdata = { ++ .smp_prepare_cpus = mtk_smp_prepare_cpus, ++ .smp_boot_secondary = mtk_boot_secondary, ++}; ++CPU_METHOD_OF_DECLARE(mt65xx_smp, "mediatek,mt65xx-smp", &mt65xx_smp_ops); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0043-ARM-dts-mt8127-enable-basic-SMP-bringup-for-mt8127.patch b/target/linux/mediatek/patches/0043-ARM-dts-mt8127-enable-basic-SMP-bringup-for-mt8127.patch new file mode 100644 index 0000000..60990c3 --- /dev/null +++ b/target/linux/mediatek/patches/0043-ARM-dts-mt8127-enable-basic-SMP-bringup-for-mt8127.patch @@ -0,0 +1,53 @@ +From e75f8b666c976aff2aa30b967f74df021d800993 Mon Sep 17 00:00:00 2001 +From: "Joe.C" +Date: Fri, 1 May 2015 15:43:30 +0800 +Subject: [PATCH 43/76] ARM: dts: mt8127: enable basic SMP bringup for mt8127 + +Add arch timer node to enable arch-timer support. MT8127 firmware +doesn't correctly setup arch-timer frequency and CNTVOFF, add +properties to workaround this. + +This also set cpu enable-method to enable SMP. + +Signed-off-by: Yingjoe Chen +--- + arch/arm/boot/dts/mt8127.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi +index aaa7862..7c2090d 100644 +--- a/arch/arm/boot/dts/mt8127.dtsi ++++ b/arch/arm/boot/dts/mt8127.dtsi +@@ -23,6 +23,7 @@ + cpus { + #address-cells = <1>; + #size-cells = <0>; ++ enable-method = "mediatek,mt81xx-tz-smp"; + + cpu@0 { + device_type = "cpu"; +@@ -72,6 +73,21 @@ + }; + }; + ++ timer { ++ compatible = "arm,armv7-timer"; ++ interrupt-parent = <&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <13000000>; ++ arm,cpu-registers-not-fw-configured; ++ }; ++ + soc { + #address-cells = <2>; + #size-cells = <2>; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch b/target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch new file mode 100644 index 0000000..1783e08 --- /dev/null +++ b/target/linux/mediatek/patches/0044-dt-bindings-Add-usb3.0-phy-binding-for-MT65xx-SoCs.patch @@ -0,0 +1,60 @@ +From 8d61eb953496aba51b94dac07c31c7e069c784bd Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 27 May 2015 19:47:58 +0800 +Subject: [PATCH 44/76] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs + +add a DT binding documentation of usb3.0 phy for MT65xx +SoCs from Mediatek. + +Signed-off-by: Chunfeng Yun +--- + .../devicetree/bindings/usb/mt65xx-u3phy.txt | 37 ++++++++++++++++++++ + 1 file changed, 37 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt + +diff --git a/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt +new file mode 100644 +index 0000000..b0b91b0 +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/mt65xx-u3phy.txt +@@ -0,0 +1,37 @@ ++MT65xx U3PHY ++ ++The device node for Mediatek SOC usb3.0 phy ++ ++Required properties: ++ - compatible : Should be "mediatek,mt8173-u3phy" ++ - reg : Offset and length of registers, the first is for mac domain, ++ another for phy domain ++ - power-domains: to enable usb's mtcmos ++ - reg-vusb33-supply: regulator of usb avdd3.3v ++ - clocks : must support all clocks that phy need ++ - clock-names: should be "wakeup_deb_p0", "wakeup_deb_p1" for wakeup ++ debounce control clocks, "sys_mac" for sys and mac clocks and ++ "u3phya_ref" for u3phya reference clock. ++ ++Optional properties: ++ - disable-usb2-p1 : disable port1 of usb2.0 which has two ports. ++ - reg-p1-vbus-supply : regulator of port1's vbus; ++ ++Example: ++ ++u3phy: usb-phy@11271000 { ++ compatible = "mediatek,mt8173-u3phy"; ++ reg = <0 0x11271000 0 0x3000>, ++ <0 0x11280000 0 0x20000>; ++ power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; ++ reg-vusb33-supply = <&mt6397_usb_reg>; ++ clocks = <&perisys PERI_USB0>, ++ <&perisys PERI_USB1>, ++ <&topckgen CLK_TOP_USB30_SEL>, ++ <&apmixedsys CLK_APMIXED_REF2USB_TX>; ++ clock-names = "wakeup_deb_p0", ++ "wakeup_deb_p1", ++ "sys_mac", ++ "u3phya_ref"; ++ disable-usb2-p1; ++}; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0045-dt-bindings-Add-a-binding-for-Mediatek-xHCI-host-con.patch b/target/linux/mediatek/patches/0045-dt-bindings-Add-a-binding-for-Mediatek-xHCI-host-con.patch new file mode 100644 index 0000000..6c1d7b3 --- /dev/null +++ b/target/linux/mediatek/patches/0045-dt-bindings-Add-a-binding-for-Mediatek-xHCI-host-con.patch @@ -0,0 +1,43 @@ +From 8629bcb28208ef5b9f5eeb6d4b669651c9521b30 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 27 May 2015 19:47:59 +0800 +Subject: [PATCH 45/76] dt-bindings: Add a binding for Mediatek xHCI host + controller + +add a DT binding documentation of xHCI host controller for +the MT8173 SoC from Mediatek. + +Signed-off-by: Chunfeng Yun +--- + .../devicetree/bindings/usb/mt8173-xhci.txt | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/mt8173-xhci.txt + +diff --git a/Documentation/devicetree/bindings/usb/mt8173-xhci.txt b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt +new file mode 100644 +index 0000000..da28570 +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/mt8173-xhci.txt +@@ -0,0 +1,19 @@ ++MT65XX xhci ++ ++The device node for Mediatek SOC usb3.0 host controller ++ ++Required properties: ++ - compatible : supports "mediatek,mt8173-xhci", "generic-xhci" ++ - reg : Offset and length of registers ++ - interrupts : Interrupt; mode, number and trigger ++ - usb-phy : the phy that xhci will bind ++ - usb3-lpm-capable: suppots USB3 LPM ++ ++Example: ++usb: usb30@11270000 { ++ compatible = "mediatek,mt8173-xhci", "generic-xhci"; ++ reg = <0 0x11270000 0 0x1000>; ++ interrupts = ; ++ usb-phy = <&u3phy>; ++ usb3-lpm-capable; ++}; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0046-usb-phy-add-usb3.0-phy-driver-for-mt65xx-SoCs.patch b/target/linux/mediatek/patches/0046-usb-phy-add-usb3.0-phy-driver-for-mt65xx-SoCs.patch new file mode 100644 index 0000000..40ba24d --- /dev/null +++ b/target/linux/mediatek/patches/0046-usb-phy-add-usb3.0-phy-driver-for-mt65xx-SoCs.patch @@ -0,0 +1,779 @@ +From cee7c5a343bdecf407c876289327c567bfd34fd4 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 27 May 2015 19:48:01 +0800 +Subject: [PATCH 46/76] usb: phy: add usb3.0 phy driver for mt65xx SoCs + +Signed-off-by: Chunfeng Yun +--- + drivers/usb/phy/Kconfig | 10 + + drivers/usb/phy/Makefile | 1 + + drivers/usb/phy/phy-mt65xx-usb3.c | 724 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 735 insertions(+) + create mode 100644 drivers/usb/phy/phy-mt65xx-usb3.c + +diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig +index 2175678..dfca566 100644 +--- a/drivers/usb/phy/Kconfig ++++ b/drivers/usb/phy/Kconfig +@@ -151,6 +151,16 @@ config USB_MSM_OTG + This driver is not supported on boards like trout which + has an external PHY. + ++config USB_MT65XX_USB3_PHY ++ tristate "Mediatek USB3.0 PHY controller Driver" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select USB_PHY ++ help ++ Say 'Y' here to add support for Mediatek USB3.0 PHY driver ++ for mt65xx SoCs. it supports two usb2.0 ports and ++ one usb3.0 port. ++ To compile this driver as a module, choose M here ++ + config USB_MV_OTG + tristate "Marvell USB OTG support" + depends on USB_EHCI_MV && USB_MV_UDC && PM +diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile +index 75f2bba..d6113a4 100644 +--- a/drivers/usb/phy/Makefile ++++ b/drivers/usb/phy/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += phy-tegra-usb.o + obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio-vbus-usb.o + obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o + obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o ++obj-$(CONFIG_USB_MT65XX_USB3_PHY) += phy-mt65xx-usb3.o + obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o + obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o + obj-$(CONFIG_USB_RCAR_PHY) += phy-rcar-usb.o +diff --git a/drivers/usb/phy/phy-mt65xx-usb3.c b/drivers/usb/phy/phy-mt65xx-usb3.c +new file mode 100644 +index 0000000..ec5cf24 +--- /dev/null ++++ b/drivers/usb/phy/phy-mt65xx-usb3.c +@@ -0,0 +1,724 @@ ++/* ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: Chunfeng.Yun ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * relative to MAC base address ++ */ ++#define SSUSB_USB3_MAC_CSR_BASE (0x1400) ++#define SSUSB_USB3_SYS_CSR_BASE (0x1400) ++#define SSUSB_USB2_CSR_BASE (0x2400) ++ ++/* ++ * for sifslv1 register ++ * relative to USB3_SIF_BASE base address ++ */ ++#define SSUSB_SIFSLV_IPPC_BASE (0x700) ++ ++/* ++ * for sifslv2 register ++ * relative to USB3_SIF_BASE base address ++ */ ++#define SSUSB_SIFSLV_U2PHY_COM_BASE (0x10800) ++#define SSUSB_SIFSLV_U3PHYD_BASE (0x10900) ++#define SSUSB_SIFSLV_U2FREQ_BASE (0x10f00) ++#define SSUSB_USB30_PHYA_SIV_B_BASE (0x10b00) ++#define SSUSB_SIFSLV_U3PHYA_DA_BASE (0x10c00) ++#define SSUSB_SIFSLV_SPLLC (0x10000) ++ ++/*port1 refs. +0x800(refer to port0)*/ ++#define U3P_PORT_OFFSET (0x800) /*based on port0 */ ++#define U3P_PHY_BASE(index) ((U3P_PORT_OFFSET) * (index)) ++ ++#define U3P_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE+0x0000) ++#define CTRL0_IP_SW_RST (0x1<<0) ++ ++#define U3P_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE+0x0004) ++#define CTRL1_IP_HOST_PDN (0x1<<0) ++ ++#define U3P_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE+0x0010) ++#define STS1_U3_MAC_RST (0x1 << 16) ++#define STS1_SYS125_RST (0x1 << 10) ++#define STS1_REF_RST (0x1 << 8) ++#define STS1_SYSPLL_STABLE (0x1 << 0) ++ ++#define U3P_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE+0x0014) ++#define STS2_U2_MAC_RST (0x1 << 0) ++ ++#define U3P_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x24) ++#define CAP_U3_PORT_NUM(p) ((p) & 0xff) ++#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) ++ ++#define U3P_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE+0x0030) ++#define CTRL_U3_PORT_HOST_SEL (0x1<<2) ++#define CTRL_U3_PORT_PDN (0x1<<1) ++#define CTRL_U3_PORT_DIS (0x1<<0) ++ ++#define U3P_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE+0x0050) ++#define CTRL_U2_PORT_HOST_SEL (0x1<<2) ++#define CTRL_U2_PORT_PDN (0x1<<1) ++#define CTRL_U2_PORT_DIS (0x1<<0) ++ ++#define U3P_U3_CTRL(p) (U3P_U3_CTRL_0P + ((p) * 0x08)) ++#define U3P_U2_CTRL(p) (U3P_U2_CTRL_0P + ((p) * 0x08)) ++ ++#define U3P_USBPHYACR5 (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0014) ++#define PA5_RG_U2_HSTX_SRCTRL (0x7<<12) ++#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12) ++#define PA5_RG_U2_HS_100U_U3_EN (0x1<<11) ++ ++#define U3P_USBPHYACR6 (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0018) ++#define PA6_RG_U2_ISO_EN (0x1<<31) ++#define PA6_RG_U2_BC11_SW_EN (0x1<<23) ++#define PA6_RG_U2_OTG_VBUSCMP_EN (0x1<<20) ++ ++#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0020) ++#define P2C_RG_USB20_GPIO_CTL (0x1<<9) ++#define P2C_USB20_GPIO_MODE (0x1<<8) ++#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) ++ ++#define U3P_U2PHYDTM0 (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0068) ++#define P2C_FORCE_UART_EN (0x1<<26) ++#define P2C_FORCE_DATAIN (0x1<<23) ++#define P2C_FORCE_DM_PULLDOWN (0x1<<21) ++#define P2C_FORCE_DP_PULLDOWN (0x1<<20) ++#define P2C_FORCE_XCVRSEL (0x1<<19) ++#define P2C_FORCE_SUSPENDM (0x1<<18) ++#define P2C_FORCE_TERMSEL (0x1<<17) ++#define P2C_RG_DATAIN (0xf<<10) ++#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10) ++#define P2C_RG_DMPULLDOWN (0x1<<7) ++#define P2C_RG_DPPULLDOWN (0x1<<6) ++#define P2C_RG_XCVRSEL (0x3<<4) ++#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4) ++#define P2C_RG_SUSPENDM (0x1<<3) ++#define P2C_RG_TERMSEL (0x1<<2) ++#define P2C_DTM0_PART_MASK \ ++ (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ ++ P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ ++ P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ ++ P2C_RG_TERMSEL) ++ ++#define U3P_U2PHYDTM1 (SSUSB_SIFSLV_U2PHY_COM_BASE+0x006C) ++#define P2C_RG_UART_EN (0x1<<16) ++#define P2C_RG_VBUSVALID (0x1<<5) ++#define P2C_RG_SESSEND (0x1<<4) ++#define P2C_RG_AVALID (0x1<<2) ++ ++#define U3P_U3_PHYA_REG0 (SSUSB_USB30_PHYA_SIV_B_BASE+0x0000) ++#define P3A_RG_U3_VUSB10_ON (1<<5) ++ ++#define U3P_U3_PHYA_REG6 (SSUSB_USB30_PHYA_SIV_B_BASE+0x0018) ++#define P3A_RG_TX_EIDLE_CM (0xf<<28) ++#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28) ++ ++#define U3P_U3_PHYA_REG9 (SSUSB_USB30_PHYA_SIV_B_BASE+0x0024) ++#define P3A_RG_RX_DAC_MUX (0x1f<<1) ++#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1) ++ ++#define U3P_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_DA_BASE + 0x0) ++#define P3A_RG_XTAL_EXT_EN_U3 (0x3<<10) ++#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10) ++ ++#define U3P_PHYD_CDR1 (SSUSB_SIFSLV_U3PHYD_BASE+0x5c) ++#define P3D_RG_CDR_BIR_LTD1 (0x1f<<24) ++#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24) ++#define P3D_RG_CDR_BIR_LTD0 (0x1f<<8) ++#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8) ++ ++#define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x18) ++#define XC3_RG_U3_XTAL_RX_PWD (0x1<<9) ++#define XC3_RG_U3_FRC_XTAL_RX_PWD (0x1<<8) ++ ++#define U3P_UX_EXIT_LFPS_PARAM (SSUSB_USB3_MAC_CSR_BASE+0x00A0) ++#define RX_UX_EXIT_REF (0xff<<8) ++#define RX_UX_EXIT_REF_VAL (0x3 << 8) ++ ++#define U3P_REF_CLK_PARAM (SSUSB_USB3_MAC_CSR_BASE+0x00B0) ++#define REF_CLK_1000NS (0xff << 0) ++#define REF_CLK_VAL_DEF (0xa << 0) ++ ++#define U3P_LINK_PM_TIMER (SSUSB_USB3_SYS_CSR_BASE+0x0208) ++#define PM_LC_TIMEOUT (0xf<<0) ++#define PM_LC_TIMEOUT_VAL (0x3 << 0) ++ ++#define U3P_TIMING_PULSE_CTRL (SSUSB_USB3_SYS_CSR_BASE+0x02B4) ++#define U3T_CNT_1US (0xff << 0) ++#define U3T_CNT_1US_VAL (0x3f << 0) /* 62.5MHz: 63 */ ++ ++#define U3P_U2_TIMING_PARAM (SSUSB_USB2_CSR_BASE+0x0040) ++#define U2T_VAL_1US (0xff<<0) ++#define U2T_VAL_1US_VAL (0x3f << 0) /* 62.5MHz: 63 */ ++ ++ ++struct mt65xx_u3phy { ++ struct usb_phy phy; ++ struct device *dev; ++ struct regulator *vusb33; ++ struct regulator *p1_vbus; ++ void __iomem *mac_base; /* only device-mac regs, exclude xhci's */ ++ void __iomem *sif_base; /* include sif & sif2 */ ++ struct clk *wk_deb_p0; /* port0's wakeup debounce clock */ ++ struct clk *wk_deb_p1; ++ struct clk *sys_mac; /* sys and mac clock */ ++ struct clk *u3phya_ref; /* reference clock of usb3 anolog phy */ ++ bool enable_usb2_p1; ++}; ++ ++ ++static void u3p_writel(void __iomem *base, u32 offset, u32 data) ++{ ++ writel(data, base + offset); ++} ++ ++static u32 u3p_readl(void __iomem *base, u32 offset) ++{ ++ return readl(base + offset); ++} ++ ++static void u3p_setmsk(void __iomem *base, u32 offset, u32 msk) ++{ ++ void __iomem *addr = base + offset; ++ ++ writel((readl(addr) | msk), addr); ++} ++ ++static void u3p_clrmsk(void __iomem *base, u32 offset, u32 msk) ++{ ++ void __iomem *addr = base + offset; ++ ++ writel((readl(addr) & ~msk), addr); ++} ++ ++static void u3p_setval(void __iomem *base, u32 offset, ++ u32 mask, u32 value) ++{ ++ void __iomem *addr = base + offset; ++ unsigned int new_value; ++ ++ new_value = (readl(addr) & ~mask) | value; ++ writel(new_value, addr); ++} ++ ++static void phy_index_power_on(struct mt65xx_u3phy *u3phy, int index) ++{ ++ void __iomem *sif_base = u3phy->sif_base + U3P_PHY_BASE(index); ++ ++ if (!index) { ++ /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */ ++ u3p_setmsk(sif_base, U3P_U3_PHYA_REG0, P3A_RG_U3_VUSB10_ON); ++ /* power domain iso disable */ ++ u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_ISO_EN); ++ } ++ ++ /* switch to USB function. (system register, force ip into usb mode) */ ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_UART_EN); ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_UART_EN); ++ if (!index) ++ u3p_clrmsk(sif_base, U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); ++ ++ /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM); ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, ++ P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); ++ ++ /* DP/DM BC1.1 path Disable */ ++ u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN); ++ /* OTG Enable */ ++ u3p_setmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); ++ u3p_setval(sif_base, U3P_U3PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, ++ P3A_RG_XTAL_EXT_EN_U3_VAL(2)); ++ u3p_setval(sif_base, U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, ++ P3A_RG_RX_DAC_MUX_VAL(4)); ++ ++ if (!index) { ++ u3p_setmsk(sif_base, U3P_XTALCTL3, XC3_RG_U3_XTAL_RX_PWD); ++ u3p_setmsk(sif_base, U3P_XTALCTL3, XC3_RG_U3_FRC_XTAL_RX_PWD); ++ /* [mt8173]disable Change 100uA current from SSUSB */ ++ u3p_clrmsk(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); ++ } ++ u3p_setval(sif_base, U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, ++ P3A_RG_TX_EIDLE_CM_VAL(0xe)); ++ u3p_setval(sif_base, U3P_PHYD_CDR1, P3D_RG_CDR_BIR_LTD0, ++ P3D_RG_CDR_BIR_LTD0_VAL(0xc)); ++ u3p_setval(sif_base, U3P_PHYD_CDR1, P3D_RG_CDR_BIR_LTD1, ++ P3D_RG_CDR_BIR_LTD1_VAL(0x3)); ++ ++ udelay(800); ++ u3p_setmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_SESSEND); ++ ++ /* USB 2.0 slew rate calibration */ ++ u3p_setval(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, ++ PA5_RG_U2_HSTX_SRCTRL_VAL(4)); ++ ++ dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); ++} ++ ++ ++static void phy_index_power_off(struct mt65xx_u3phy *u3phy, int index) ++{ ++ void __iomem *sif_base = u3phy->sif_base + U3P_PHY_BASE(index); ++ ++ /* switch to USB function. (system register, force ip into usb mode) */ ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_UART_EN); ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_UART_EN); ++ if (!index) ++ u3p_clrmsk(sif_base, U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); ++ ++ u3p_setmsk(sif_base, U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM); ++ u3p_setval(sif_base, U3P_U2PHYDTM0, ++ P2C_RG_XCVRSEL, P2C_RG_XCVRSEL_VAL(1)); ++ u3p_setval(sif_base, U3P_U2PHYDTM0, ++ P2C_RG_DATAIN, P2C_RG_DATAIN_VAL(0)); ++ u3p_setmsk(sif_base, U3P_U2PHYDTM0, P2C_DTM0_PART_MASK); ++ /* DP/DM BC1.1 path Disable */ ++ u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN); ++ /* OTG Disable */ ++ u3p_clrmsk(sif_base, U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); ++ if (!index) { ++ /* Change 100uA current switch to USB2.0 */ ++ u3p_clrmsk(sif_base, U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); ++ } ++ udelay(800); ++ ++ /* let suspendm=0, set utmi into analog power down */ ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM0, P2C_RG_SUSPENDM); ++ udelay(1); ++ ++ u3p_clrmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); ++ u3p_setmsk(sif_base, U3P_U2PHYDTM1, P2C_RG_SESSEND); ++ if (!index) { ++ /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */ ++ u3p_clrmsk(sif_base, U3P_U3_PHYA_REG0, P3A_RG_U3_VUSB10_ON); ++ } ++ dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index); ++} ++ ++ ++static int check_ip_clk_status(struct mt65xx_u3phy *u3phy) ++{ ++ int ret; ++ int u3_port_num; ++ int u2_port_num; ++ u32 xhci_cap; ++ u32 val; ++ void __iomem *sif_base = u3phy->sif_base; ++ ++ xhci_cap = u3p_readl(sif_base, U3P_IP_XHCI_CAP); ++ u3_port_num = CAP_U3_PORT_NUM(xhci_cap); ++ u2_port_num = CAP_U2_PORT_NUM(xhci_cap); ++ ++ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val, ++ (val & STS1_SYSPLL_STABLE), 100, 10000); ++ if (ret) { ++ dev_err(u3phy->dev, "sypll is not stable!!!\n"); ++ return ret; ++ } ++ ++ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val, ++ (val & STS1_REF_RST), 100, 10000); ++ if (ret) { ++ dev_err(u3phy->dev, "ref_clk is still active!!!\n"); ++ return ret; ++ } ++ ++ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val, ++ (val & STS1_SYS125_RST), 100, 10000); ++ if (ret) { ++ dev_err(u3phy->dev, "sys125_ck is still active!!!\n"); ++ return ret; ++ } ++ ++ if (u3_port_num) { ++ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS1, val, ++ (val & STS1_U3_MAC_RST), 100, 10000); ++ if (ret) { ++ dev_err(u3phy->dev, "mac3_mac_ck is still active!!!\n"); ++ return ret; ++ } ++ } ++ ++ if (u2_port_num) { ++ ret = readl_poll_timeout(sif_base + U3P_IP_PW_STS2, val, ++ (val & STS2_U2_MAC_RST), 100, 10000); ++ if (ret) { ++ dev_err(u3phy->dev, "mac2_sys_ck is still active!!!\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int u3phy_ports_enable(struct mt65xx_u3phy *u3phy) ++{ ++ int i; ++ u32 temp; ++ int u3_port_num; ++ int u2_port_num; ++ void __iomem *sif_base = u3phy->sif_base; ++ ++ temp = u3p_readl(sif_base, U3P_IP_XHCI_CAP); ++ u3_port_num = CAP_U3_PORT_NUM(temp); ++ u2_port_num = CAP_U2_PORT_NUM(temp); ++ dev_dbg(u3phy->dev, "%s u2p:%d, u3p:%d\n", ++ __func__, u2_port_num, u3_port_num); ++ ++ /* power on host ip */ ++ u3p_clrmsk(sif_base, U3P_IP_PW_CTRL1, CTRL1_IP_HOST_PDN); ++ ++ /* power on and enable all u3 ports */ ++ for (i = 0; i < u3_port_num; i++) { ++ temp = u3p_readl(sif_base, U3P_U3_CTRL(i)); ++ temp &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); ++ temp |= CTRL_U3_PORT_HOST_SEL; ++ u3p_writel(sif_base, U3P_U3_CTRL(i), temp); ++ } ++ ++ /* power on and enable all u2 ports */ ++ for (i = 0; i < u2_port_num; i++) { ++ temp = u3p_readl(sif_base, U3P_U2_CTRL(i)); ++ temp &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); ++ temp |= CTRL_U2_PORT_HOST_SEL; ++ u3p_writel(sif_base, U3P_U2_CTRL(i), temp); ++ } ++ return check_ip_clk_status(u3phy); ++} ++ ++ ++static void u3phy_timing_init(struct mt65xx_u3phy *u3phy) ++{ ++ void __iomem *mbase = u3phy->mac_base; ++ int u3_port_num; ++ u32 temp; ++ ++ temp = u3p_readl(u3phy->sif_base, U3P_IP_XHCI_CAP); ++ u3_port_num = CAP_U3_PORT_NUM(temp); ++ ++ if (u3_port_num) { ++ /* set MAC reference clock speed */ ++ u3p_setval(mbase, U3P_UX_EXIT_LFPS_PARAM, ++ RX_UX_EXIT_REF, RX_UX_EXIT_REF_VAL); ++ /* set REF_CLK */ ++ u3p_setval(mbase, U3P_REF_CLK_PARAM, ++ REF_CLK_1000NS, REF_CLK_VAL_DEF); ++ /* set SYS_CLK */ ++ u3p_setval(mbase, U3P_TIMING_PULSE_CTRL, ++ U3T_CNT_1US, U3T_CNT_1US_VAL); ++ /* set LINK_PM_TIMER=3 */ ++ u3p_setval(mbase, U3P_LINK_PM_TIMER, ++ PM_LC_TIMEOUT, PM_LC_TIMEOUT_VAL); ++ } ++ u3p_setval(mbase, U3P_U2_TIMING_PARAM, U2T_VAL_1US, U2T_VAL_1US_VAL); ++} ++ ++ ++static int u3phy_clks_enable(struct mt65xx_u3phy *u3phy) ++{ ++ int ret; ++ ++ ret = clk_prepare_enable(u3phy->sys_mac); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to enable sys_mac\n"); ++ goto sys_mac_err; ++ } ++ ++ ret = clk_prepare_enable(u3phy->u3phya_ref); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to enable u3phya_ref\n"); ++ goto u3phya_ref_err; ++ } ++ ret = clk_prepare_enable(u3phy->wk_deb_p0); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to enable wk_deb_p0\n"); ++ goto usb_p0_err; ++ } ++ if (u3phy->enable_usb2_p1) { ++ ret = clk_prepare_enable(u3phy->wk_deb_p1); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to enable wk_deb_p1\n"); ++ goto usb_p1_err; ++ } ++ } ++ udelay(50); ++ ++ return 0; ++ ++usb_p1_err: ++ clk_disable_unprepare(u3phy->wk_deb_p0); ++usb_p0_err: ++ clk_disable_unprepare(u3phy->u3phya_ref); ++u3phya_ref_err: ++ clk_disable_unprepare(u3phy->sys_mac); ++sys_mac_err: ++ return -EINVAL; ++} ++ ++static void u3phy_clks_disable(struct mt65xx_u3phy *u3phy) ++{ ++ if (u3phy->enable_usb2_p1) ++ clk_disable_unprepare(u3phy->wk_deb_p1); ++ clk_disable_unprepare(u3phy->wk_deb_p0); ++ clk_disable_unprepare(u3phy->u3phya_ref); ++ clk_disable_unprepare(u3phy->sys_mac); ++} ++ ++ ++static int mt65xx_u3phy_init(struct usb_phy *phy) ++{ ++ struct mt65xx_u3phy *u3phy; ++ int ret; ++ ++ u3phy = container_of(phy, struct mt65xx_u3phy, phy); ++ dev_dbg(u3phy->dev, "%s+\n", __func__); ++ ++ if (u3phy->enable_usb2_p1) { ++ ret = regulator_enable(u3phy->p1_vbus); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to enable p1-vbus\n"); ++ goto reg_p1_err; ++ } ++ } ++ ++ ret = regulator_enable(u3phy->vusb33); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to enable vusb33\n"); ++ goto reg_err; ++ } ++ ++ ret = pm_runtime_get_sync(u3phy->dev); ++ if (ret < 0) ++ goto pm_err; ++ ++ ret = u3phy_clks_enable(u3phy); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to enable clks\n"); ++ goto clks_err; ++ } ++ ++ /* reset whole ip */ ++ u3p_setmsk(u3phy->sif_base, U3P_IP_PW_CTRL0, CTRL0_IP_SW_RST); ++ u3p_clrmsk(u3phy->sif_base, U3P_IP_PW_CTRL0, CTRL0_IP_SW_RST); ++ ++ ret = u3phy_ports_enable(u3phy); ++ if (ret) { ++ dev_err(u3phy->dev, "failed to enable ports\n"); ++ goto port_err; ++ } ++ u3phy_timing_init(u3phy); ++ phy_index_power_on(u3phy, 0); ++ if (u3phy->enable_usb2_p1) ++ phy_index_power_on(u3phy, 1); ++ ++ return 0; ++ ++port_err: ++ u3phy_clks_disable(u3phy); ++clks_err: ++ pm_runtime_put_sync(u3phy->dev); ++pm_err: ++ regulator_disable(u3phy->vusb33); ++reg_err: ++ if (u3phy->enable_usb2_p1) ++ regulator_disable(u3phy->p1_vbus); ++reg_p1_err: ++ return ret; ++} ++ ++ ++static void mt65xx_u3phy_shutdown(struct usb_phy *phy) ++{ ++ struct mt65xx_u3phy *u3phy; ++ ++ u3phy = container_of(phy, struct mt65xx_u3phy, phy); ++ dev_dbg(u3phy->dev, "%s+\n", __func__); ++ ++ phy_index_power_off(u3phy, 0); ++ if (u3phy->enable_usb2_p1) { ++ phy_index_power_off(u3phy, 1); ++ regulator_disable(u3phy->p1_vbus); ++ } ++ u3phy_clks_disable(u3phy); ++ pm_runtime_put_sync(u3phy->dev); ++ regulator_disable(u3phy->vusb33); ++} ++ ++ ++static int mt65xx_u3phy_suspend(struct usb_phy *x, int suspend) ++{ ++ struct mt65xx_u3phy *u3phy = container_of(x, struct mt65xx_u3phy, phy); ++ ++ if (suspend) { ++ mt65xx_u3phy_shutdown(&u3phy->phy); ++ return 0; ++ } else { ++ return mt65xx_u3phy_init(&u3phy->phy); ++ } ++} ++ ++ ++static const struct of_device_id mt65xx_u3phy_id_table[] = { ++ { .compatible = "mediatek,mt8173-u3phy",}, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, mt65xx_u3phy_id_table); ++ ++ ++static int mt65xx_u3phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct resource *mac_res; ++ struct resource *sif_res; ++ struct mt65xx_u3phy *u3phy; ++ int retval = -ENOMEM; ++ ++ u3phy = devm_kzalloc(&pdev->dev, sizeof(*u3phy), GFP_KERNEL); ++ if (!u3phy) ++ goto err; ++ ++ u3phy->dev = &pdev->dev; ++ ++ mac_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ u3phy->mac_base = devm_ioremap_resource(dev, mac_res); ++ if (IS_ERR(u3phy->mac_base)) { ++ dev_err(dev, "failed to remap mac regs\n"); ++ retval = PTR_ERR(u3phy->mac_base); ++ goto err; ++ } ++ ++ sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ u3phy->sif_base = devm_ioremap_resource(dev, sif_res); ++ if (IS_ERR(u3phy->sif_base)) { ++ dev_err(dev, "failed to remap sif regs\n"); ++ retval = PTR_ERR(u3phy->sif_base); ++ goto err; ++ } ++ ++ u3phy->enable_usb2_p1 = !of_property_read_bool(np, "disable-usb2-p1"); ++ dev_dbg(dev, "enable_usb2_p1 - %d\n", u3phy->enable_usb2_p1); ++ ++ u3phy->sys_mac = devm_clk_get(u3phy->dev, "sys_mac"); ++ if (IS_ERR(u3phy->sys_mac)) { ++ dev_err(dev, "error to get sys_mac\n"); ++ retval = PTR_ERR(u3phy->sys_mac); ++ goto err; ++ } ++ ++ u3phy->u3phya_ref = devm_clk_get(u3phy->dev, "u3phya_ref"); ++ if (IS_ERR(u3phy->u3phya_ref)) { ++ dev_err(dev, "error to get u3phya_ref\n"); ++ retval = PTR_ERR(u3phy->u3phya_ref); ++ goto err; ++ } ++ ++ u3phy->wk_deb_p0 = devm_clk_get(u3phy->dev, "wakeup_deb_p0"); ++ if (IS_ERR(u3phy->wk_deb_p0)) { ++ dev_err(dev, "error to get wakeup_deb_p0\n"); ++ retval = PTR_ERR(u3phy->wk_deb_p0); ++ goto err; ++ } ++ ++ if (u3phy->enable_usb2_p1) { ++ u3phy->wk_deb_p1 = devm_clk_get(u3phy->dev, "wakeup_deb_p1"); ++ if (IS_ERR(u3phy->wk_deb_p1)) { ++ dev_err(dev, "error to get wakeup_deb_p1\n"); ++ retval = PTR_ERR(u3phy->wk_deb_p1); ++ goto err; ++ } ++ ++ u3phy->p1_vbus = devm_regulator_get(u3phy->dev, "reg-p1-vbus"); ++ if (IS_ERR_OR_NULL(u3phy->p1_vbus)) { ++ dev_err(dev, "fail to get p1-vbus\n"); ++ retval = PTR_ERR(u3phy->p1_vbus); ++ goto err; ++ } ++ } ++ ++ u3phy->vusb33 = devm_regulator_get(u3phy->dev, "reg-vusb33"); ++ if (IS_ERR_OR_NULL(u3phy->vusb33)) { ++ dev_err(dev, "fail to get vusb33\n"); ++ retval = PTR_ERR(u3phy->vusb33); ++ goto err; ++ } ++ ++ pm_runtime_enable(dev); ++ u3phy->phy.dev = u3phy->dev; ++ u3phy->phy.label = "mt65xx-usb3phy"; ++ u3phy->phy.type = USB_PHY_TYPE_USB3; ++ u3phy->phy.init = mt65xx_u3phy_init; ++ u3phy->phy.shutdown = mt65xx_u3phy_shutdown; ++ u3phy->phy.set_suspend = mt65xx_u3phy_suspend; ++ ++ platform_set_drvdata(pdev, u3phy); ++ retval = usb_add_phy_dev(&u3phy->phy); ++ if (retval) { ++ dev_err(dev, "failed to add phy\n"); ++ goto add_phy_err; ++ } ++ ++ return 0; ++ ++add_phy_err: ++ pm_runtime_disable(dev); ++err: ++ return retval; ++} ++ ++static int mt65xx_u3phy_remove(struct platform_device *pdev) ++{ ++ struct mt65xx_u3phy *u3phy = platform_get_drvdata(pdev); ++ ++ mt65xx_u3phy_shutdown(&u3phy->phy); ++ pm_runtime_disable(&pdev->dev); ++ usb_remove_phy(&u3phy->phy); ++ ++ return 0; ++} ++ ++static struct platform_driver mt65xx_u3phy_driver = { ++ .probe = mt65xx_u3phy_probe, ++ .remove = mt65xx_u3phy_remove, ++ .driver = { ++ .name = "mt65xx-u3phy", ++ .of_match_table = mt65xx_u3phy_id_table, ++ }, ++}; ++ ++module_platform_driver(mt65xx_u3phy_driver); ++ ++MODULE_DESCRIPTION("Mt65xx USB PHY driver"); ++MODULE_LICENSE("GPL v2"); +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0047-xhci-mediatek-support-MTK-xHCI-host-controller.patch b/target/linux/mediatek/patches/0047-xhci-mediatek-support-MTK-xHCI-host-controller.patch new file mode 100644 index 0000000..ea3289e --- /dev/null +++ b/target/linux/mediatek/patches/0047-xhci-mediatek-support-MTK-xHCI-host-controller.patch @@ -0,0 +1,832 @@ +From e604b6c864f2e3b6fe0706c4bef886533d92f67a Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 27 May 2015 19:48:02 +0800 +Subject: [PATCH 47/76] xhci: mediatek: support MTK xHCI host controller + +MTK xhci host controller defines some extra SW scheduling +parameters for HW to minimize the scheduling effort for +synchronous and interrupt endpoints. The parameters are +put into reseved DWs of slot context and endpoint context. + +Signed-off-by: Chunfeng Yun +--- + drivers/usb/host/Kconfig | 9 + + drivers/usb/host/Makefile | 3 + + drivers/usb/host/xhci-mtk.c | 470 ++++++++++++++++++++++++++++++++++++++++++ + drivers/usb/host/xhci-mtk.h | 119 +++++++++++ + drivers/usb/host/xhci-plat.c | 22 +- + drivers/usb/host/xhci-ring.c | 35 +++- + drivers/usb/host/xhci.c | 16 +- + drivers/usb/host/xhci.h | 1 + + 8 files changed, 667 insertions(+), 8 deletions(-) + create mode 100644 drivers/usb/host/xhci-mtk.c + create mode 100644 drivers/usb/host/xhci-mtk.h + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -41,6 +41,15 @@ + + If unsure, say N. + ++config USB_XHCI_MTK ++ tristate "xHCI support for Mediatek MT65xx" ++ select USB_XHCI_PLATFORM ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ ---help--- ++ Say 'Y' to enable the support for the xHCI host controller ++ found in Mediatek MT65xx SoCs. ++ If unsure, say N. ++ + config USB_XHCI_MVEBU + tristate "xHCI support for Marvell Armada 375/38x" + select USB_XHCI_PLATFORM +--- a/drivers/usb/host/Makefile ++++ b/drivers/usb/host/Makefile +@@ -15,6 +15,9 @@ + xhci-hcd-y += xhci-trace.o + + xhci-plat-hcd-y := xhci-plat.o ++ifneq ($(CONFIG_USB_XHCI_MTK), ) ++ xhci-plat-hcd-y += xhci-mtk.o ++endif + ifneq ($(CONFIG_USB_XHCI_MVEBU), ) + xhci-plat-hcd-y += xhci-mvebu.o + endif +--- /dev/null ++++ b/drivers/usb/host/xhci-mtk.c +@@ -0,0 +1,470 @@ ++/* ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: ++ * Zhigang.Wei ++ * Chunfeng.Yun ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include ++#include ++#include "xhci-mtk.h" ++ ++ ++#define SS_BW_BOUNDARY 51000 ++/* table 5-5. High-speed Isoc Transaction Limits in usb_20 spec */ ++#define HS_BW_BOUNDARY 6144 ++/* usb2 spec section11.18.1: at most 188 FS bytes per microframe */ ++#define FS_PAYLOAD_MAX 188 ++ ++/* mtk scheduler bitmasks */ ++#define EP_BPKTS(p) ((p) & 0x3f) ++#define EP_BCSCOUNT(p) (((p) & 0x7) << 8) ++#define EP_BBM(p) ((p) << 11) ++#define EP_BOFFSET(p) ((p) & 0x3fff) ++#define EP_BREPEAT(p) (((p) & 0x7fff) << 16) ++ ++static int is_fs_or_ls(enum usb_device_speed speed) ++{ ++ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW; ++} ++ ++static int get_bw_index(struct xhci_hcd *xhci, struct usb_device *udev, ++ struct usb_host_endpoint *ep) ++{ ++ int bw_index; ++ int port_id; ++ struct xhci_virt_device *virt_dev; ++ ++ virt_dev = xhci->devs[udev->slot_id]; ++ port_id = virt_dev->real_port; ++ ++ if (udev->speed == USB_SPEED_SUPER) { ++ if (usb_endpoint_dir_out(&ep->desc)) ++ bw_index = (port_id - 1) * 2; ++ else ++ bw_index = (port_id - 1) * 2 + 1; ++ } else { ++ bw_index = port_id + xhci->num_usb3_ports - 1; ++ } ++ ++ return bw_index; ++} ++ ++ ++static void setup_sch_info(struct usb_device *udev, ++ struct xhci_ep_ctx *ep_ctx, struct mu3h_sch_ep_info *sch_ep) ++{ ++ u32 ep_type; ++ u32 ep_interval; ++ u32 max_packet_size; ++ u32 max_burst; ++ u32 mult; ++ u32 esit_pkts; ++ ++ ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2)); ++ ep_interval = CTX_TO_EP_INTERVAL(le32_to_cpu(ep_ctx->ep_info)); ++ max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); ++ max_burst = CTX_TO_MAX_BURST(le32_to_cpu(ep_ctx->ep_info2)); ++ mult = CTX_TO_EP_MULT(le32_to_cpu(ep_ctx->ep_info)); ++ pr_debug("%s: max_burst = %d, mult = %d\n", __func__, max_burst, mult); ++ ++ sch_ep->ep_type = ep_type; ++ sch_ep->max_packet_size = max_packet_size; ++ sch_ep->esit = 1 << ep_interval; ++ sch_ep->offset = 0; ++ sch_ep->burst_mode = 0; ++ ++ if (udev->speed == USB_SPEED_HIGH) { ++ sch_ep->cs_count = 0; ++ /* ++ * usb_20 spec section5.9 ++ * a single microframe is enough for HS synchromous endpoints ++ * in a interval ++ */ ++ sch_ep->num_budget_microframes = 1; ++ sch_ep->repeat = 0; ++ /* ++ * xHCI spec section6.2.3.4 ++ * @max_busrt is the number of additional transactions opportunities ++ * per microframe ++ */ ++ sch_ep->pkts = max_burst + 1; ++ sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts; ++ } else if (udev->speed == USB_SPEED_SUPER) { ++ /* usb3_r1 spec section4.4.7 & 4.4.8 */ ++ sch_ep->cs_count = 0; ++ esit_pkts = (mult + 1) * (max_burst + 1); ++ if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) { ++ sch_ep->pkts = esit_pkts; ++ sch_ep->num_budget_microframes = 1; ++ sch_ep->repeat = 0; ++ } ++ ++ if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) { ++ if (esit_pkts <= sch_ep->esit) ++ sch_ep->pkts = 1; ++ else ++ sch_ep->pkts = roundup_pow_of_two(esit_pkts) ++ / sch_ep->esit; ++ ++ sch_ep->num_budget_microframes = ++ DIV_ROUND_UP(esit_pkts, sch_ep->pkts); ++ ++ if (sch_ep->num_budget_microframes > 1) ++ sch_ep->repeat = 1; ++ else ++ sch_ep->repeat = 0; ++ } ++ sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts; ++ } else if (is_fs_or_ls(udev->speed)) { ++ /* ++ * usb_20 spec section11.18.4 ++ * assume worst cases ++ */ ++ sch_ep->repeat = 0; ++ sch_ep->pkts = 1; /* at most one packet for each microframe */ ++ if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) { ++ sch_ep->cs_count = 3; /* at most need 3 CS*/ ++ /* one for SS and one for budgeted transaction */ ++ sch_ep->num_budget_microframes = sch_ep->cs_count + 2; ++ sch_ep->bw_cost_per_microframe = max_packet_size; ++ } ++ if (ep_type == ISOC_OUT_EP) { ++ /* must never schedule a cs ISOC OUT ep */ ++ sch_ep->cs_count = 0; ++ /* ++ * the best case FS budget assumes that 188 FS bytes ++ * occur in each microframe ++ */ ++ sch_ep->num_budget_microframes = DIV_ROUND_UP( ++ sch_ep->max_packet_size, FS_PAYLOAD_MAX); ++ sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX; ++ } ++ if (ep_type == ISOC_IN_EP) { ++ /* at most need additional two CS. */ ++ sch_ep->cs_count = DIV_ROUND_UP( ++ sch_ep->max_packet_size, FS_PAYLOAD_MAX) + 2; ++ sch_ep->num_budget_microframes = sch_ep->cs_count + 2; ++ sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX; ++ } ++ } ++} ++ ++/* Get maximum bandwidth when we schedule at offset slot. */ ++static u32 get_max_bw(struct mu3h_sch_bw_info *sch_bw, ++ struct mu3h_sch_ep_info *sch_ep, u32 offset) ++{ ++ u32 num_esit; ++ u32 max_bw = 0; ++ int i; ++ int j; ++ ++ num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit; ++ for (i = 0; i < num_esit; i++) { ++ u32 base = offset + i * sch_ep->esit; ++ ++ for (j = 0; j < sch_ep->num_budget_microframes; j++) { ++ if (sch_bw->bus_bw[base + j] > max_bw) ++ max_bw = sch_bw->bus_bw[base + j]; ++ } ++ } ++ return max_bw; ++} ++ ++static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw, ++ struct mu3h_sch_ep_info *sch_ep, int bw_cost) ++{ ++ u32 num_esit; ++ u32 base; ++ int i; ++ int j; ++ ++ num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit; ++ for (i = 0; i < num_esit; i++) { ++ base = sch_ep->offset + i * sch_ep->esit; ++ for (j = 0; j < sch_ep->num_budget_microframes; j++) ++ sch_bw->bus_bw[base + j] += bw_cost; ++ } ++ ++} ++ ++static void debug_sch_ep(struct mu3h_sch_ep_info *sch_ep) ++{ ++ pr_debug("sch_ep->ep_type = %d\n", sch_ep->ep_type); ++ pr_debug("sch_ep->max_packet_size = %d\n", sch_ep->max_packet_size); ++ pr_debug("sch_ep->esit = %d\n", sch_ep->esit); ++ pr_debug("sch_ep->num_budget_microframes = %d\n", ++ sch_ep->num_budget_microframes); ++ pr_debug("sch_ep->bw_cost_per_microframe = %d\n", ++ sch_ep->bw_cost_per_microframe); ++ pr_debug("sch_ep->ep = %p\n", sch_ep->ep); ++ pr_debug("sch_ep->offset = %d\n", sch_ep->offset); ++ pr_debug("sch_ep->repeat = %d\n", sch_ep->repeat); ++ pr_debug("sch_ep->pkts = %d\n", sch_ep->pkts); ++ pr_debug("sch_ep->cs_count = %d\n", sch_ep->cs_count); ++} ++ ++static int check_sch_bw(struct usb_device *udev, ++ struct mu3h_sch_bw_info *sch_bw, struct mu3h_sch_ep_info *sch_ep) ++{ ++ u32 offset; ++ u32 esit; ++ u32 num_budget_microframes; ++ u32 min_bw; ++ u32 min_index; ++ u32 worst_bw; ++ u32 bw_boundary; ++ ++ if (sch_ep->esit > XHCI_MTK_MAX_ESIT) ++ sch_ep->esit = XHCI_MTK_MAX_ESIT; ++ ++ esit = sch_ep->esit; ++ num_budget_microframes = sch_ep->num_budget_microframes; ++ ++ /* ++ * Search through all possible schedule microframes. ++ * and find a microframe where its worst bandwidth is minimum. ++ */ ++ min_bw = ~0; ++ min_index = 0; ++ for (offset = 0; offset < esit; offset++) { ++ if ((offset + num_budget_microframes) > sch_ep->esit) ++ break; ++ /* ++ * usb_20 spec section11.18: ++ * must never schedule Start-Split in Y6 ++ */ ++ if (is_fs_or_ls(udev->speed) && (offset % 8 == 6)) ++ continue; ++ ++ worst_bw = get_max_bw(sch_bw, sch_ep, offset); ++ if (min_bw > worst_bw) { ++ min_bw = worst_bw; ++ min_index = offset; ++ } ++ if (min_bw == 0) ++ break; ++ } ++ sch_ep->offset = min_index; ++ ++ debug_sch_ep(sch_ep); ++ ++ bw_boundary = (udev->speed == USB_SPEED_SUPER) ++ ? SS_BW_BOUNDARY : HS_BW_BOUNDARY; ++ ++ /* check bandwidth */ ++ if (min_bw + sch_ep->bw_cost_per_microframe > bw_boundary) ++ return -1; ++ ++ /* update bus bandwidth info */ ++ update_bus_bw(sch_bw, sch_ep, sch_ep->bw_cost_per_microframe); ++ ++ return 0; ++} ++ ++static void debug_sch_bw(struct mu3h_sch_bw_info *sch_bw) ++{ ++ int i; ++ ++ pr_debug("xhci_mtk_scheduler :bus_bw_info\n"); ++ for (i = 0; i < XHCI_MTK_MAX_ESIT; i++) ++ pr_debug("%d ", sch_bw->bus_bw[i]); ++ ++ pr_debug("\n"); ++} ++ ++ ++static int need_bw_sch(struct usb_host_endpoint *ep, ++ enum usb_device_speed speed, int has_tt) ++{ ++ /* only for synchronous endpoints */ ++ if (usb_endpoint_xfer_control(&ep->desc) ++ || usb_endpoint_xfer_bulk(&ep->desc)) ++ return 0; ++ /* ++ * for LS & FS synchronous endpoints which its device don't attach ++ * to TT are also ignored, root-hub will schedule them directly ++ */ ++ if (is_fs_or_ls(speed) && !has_tt) ++ return 0; ++ ++ return 1; ++} ++ ++int xhci_mtk_init_quirk(struct xhci_hcd *xhci) ++{ ++ struct usb_hcd *hcd = xhci_to_hcd(xhci); ++ struct device *dev = hcd->self.controller; ++ struct mu3h_sch_bw_info *sch_array; ++ size_t array_size; ++ int num_usb_bus; ++ int i; ++ ++ /* ss IN and OUT are separated */ ++ num_usb_bus = xhci->num_usb3_ports * 2 + xhci->num_usb2_ports; ++ array_size = sizeof(*sch_array) * num_usb_bus; ++ ++ sch_array = kzalloc(array_size, GFP_KERNEL); ++ if (sch_array == NULL) ++ return -ENOMEM; ++ ++ for (i = 0; i < num_usb_bus; i++) ++ INIT_LIST_HEAD(&sch_array[i].bw_ep_list); ++ ++ dev->platform_data = sch_array; ++ xhci->quirks |= XHCI_MTK_HOST; ++ /* ++ * MTK host controller gives a spurious successful event after a ++ * short transfer. Ignore it. ++ */ ++ xhci->quirks |= XHCI_SPURIOUS_SUCCESS; ++ ++ return 0; ++} ++ ++ ++void xhci_mtk_exit_quirk(struct xhci_hcd *xhci) ++{ ++ struct usb_hcd *hcd = xhci_to_hcd(xhci); ++ struct mu3h_sch_bw_info *sch_array; ++ ++ sch_array = dev_get_platdata(hcd->self.controller); ++ kfree(sch_array); ++} ++ ++ ++int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev, ++ struct usb_host_endpoint *ep) ++{ ++ int ret = 0; ++ int port_id; ++ int bw_index; ++ struct xhci_hcd *xhci; ++ unsigned int ep_index; ++ struct xhci_ep_ctx *ep_ctx; ++ struct xhci_slot_ctx *slot_ctx; ++ struct xhci_virt_device *virt_dev; ++ struct mu3h_sch_bw_info *sch_bw; ++ struct mu3h_sch_ep_info *sch_ep; ++ struct mu3h_sch_bw_info *sch_array; ++ ++ xhci = hcd_to_xhci(hcd); ++ virt_dev = xhci->devs[udev->slot_id]; ++ ep_index = xhci_get_endpoint_index(&ep->desc); ++ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); ++ ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); ++ sch_array = dev_get_platdata(hcd->self.controller); ++ ++ port_id = virt_dev->real_port; ++ xhci_dbg(xhci, "%s() xfer_type: %d, speed:%d, ep:%p\n", __func__, ++ usb_endpoint_type(&ep->desc), udev->speed, ep); ++ ++ if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT)) ++ return 0; ++ ++ bw_index = get_bw_index(xhci, udev, ep); ++ sch_bw = &sch_array[bw_index]; ++ ++ sch_ep = kzalloc(sizeof(struct mu3h_sch_ep_info), GFP_KERNEL); ++ if (!sch_ep) ++ return -ENOMEM; ++ ++ setup_sch_info(udev, ep_ctx, sch_ep); ++ ++ ret = check_sch_bw(udev, sch_bw, sch_ep); ++ if (ret) { ++ xhci_err(xhci, "Not enough bandwidth!\n"); ++ kfree(sch_ep); ++ return -ENOSPC; ++ } ++ ++ list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list); ++ sch_ep->ep = ep; ++ ++ ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts) ++ | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode)); ++ ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset) ++ | EP_BREPEAT(sch_ep->repeat)); ++ ++ debug_sch_bw(sch_bw); ++ return 0; ++} ++ ++void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev, ++ struct usb_host_endpoint *ep) ++{ ++ int bw_index; ++ struct xhci_hcd *xhci; ++ struct xhci_slot_ctx *slot_ctx; ++ struct xhci_virt_device *virt_dev; ++ struct mu3h_sch_bw_info *sch_array; ++ struct mu3h_sch_bw_info *sch_bw; ++ struct mu3h_sch_ep_info *sch_ep; ++ ++ xhci = hcd_to_xhci(hcd); ++ virt_dev = xhci->devs[udev->slot_id]; ++ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); ++ sch_array = dev_get_platdata(hcd->self.controller); ++ ++ xhci_dbg(xhci, "%s() xfer_type: %d, speed:%d, ep:%p\n", __func__, ++ usb_endpoint_type(&ep->desc), udev->speed, ep); ++ ++ if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT)) ++ return; ++ ++ bw_index = get_bw_index(xhci, udev, ep); ++ sch_bw = &sch_array[bw_index]; ++ ++ list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) { ++ if (sch_ep->ep == ep) { ++ update_bus_bw(sch_bw, sch_ep, ++ -sch_ep->bw_cost_per_microframe); ++ list_del(&sch_ep->endpoint); ++ kfree(sch_ep); ++ break; ++ } ++ } ++ debug_sch_bw(sch_bw); ++} ++ ++ ++/* ++ * The TD size is the number of bytes remaining in the TD (including this TRB), ++ * right shifted by 10. ++ * It must fit in bits 21:17, so it can't be bigger than 31. ++ */ ++u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total, ++ unsigned trb_buffer_length, struct urb *urb) ++{ ++ u32 max = 31; ++ int remainder, td_packet_count, packet_transferred; ++ unsigned int td_transfer_size = urb->transfer_buffer_length; ++ unsigned int maxp; ++ ++ maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); ++ ++ /* 0 for the last TRB */ ++ if (td_running_total + trb_buffer_length == td_transfer_size) ++ return 0; ++ ++ packet_transferred = td_running_total / maxp; ++ td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp); ++ remainder = td_packet_count - packet_transferred; ++ ++ if (remainder > max) ++ return max << 17; ++ else ++ return remainder << 17; ++} ++ ++ +--- /dev/null ++++ b/drivers/usb/host/xhci-mtk.h +@@ -0,0 +1,119 @@ ++/* ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: ++ * Zhigang.Wun ++ * Chunfeng.Yun ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef _XHCI_MTK_H_ ++#define _XHCI_MTK_H_ ++ ++#include "xhci.h" ++ ++/** ++ * To simplify scheduler algorithm, set a upper limit for ESIT, ++ * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT, ++ * round down to the limit value, that means allocating more ++ * bandwidth to it. ++ */ ++#define XHCI_MTK_MAX_ESIT 64 ++ ++/** ++ * struct mu3h_sch_bw_info ++ * @bus_bw: array to keep track of bandwidth already used at each uframes ++ * @bw_ep_list: eps in the bandwidth domain ++ * ++ * treat a HS root port as a bandwidth domain, but treat a SS root port as ++ * two bandwidth domains, one for IN eps and another for OUT eps. ++ */ ++struct mu3h_sch_bw_info { ++ u32 bus_bw[XHCI_MTK_MAX_ESIT]; ++ struct list_head bw_ep_list; ++}; ++ ++/** ++ * struct mu3h_sch_ep_info ++ * @esit: unit is 125us, equal to 2 << Interval field in ep-context ++ * @num_budget_microframes: number of continuous uframes ++ * (@repeat==1) scheduled within the interval ++ * @ep: address of usb_host_endpoint ++ * @offset: which uframe of the interval that transfer should be ++ * scheduled first time within the interval ++ * @repeat: the time gap between two uframes that transfers are ++ * scheduled within a interval. in the simple algorithm, only ++ * assign 0 or 1 to it; 0 means using only one uframe in a ++ * interval, and1 means using @num_budget_microframes ++ * continuous uframes ++ * @pkts: number of packets to be transferred in the scheduled uframes ++ * @cs_count: number of CS that host will trigger ++ */ ++struct mu3h_sch_ep_info { ++ u32 ep_type; ++ u32 max_packet_size; ++ u32 esit; ++ u32 num_budget_microframes; ++ u32 bw_cost_per_microframe; ++ void *ep; ++ struct list_head endpoint; ++ ++ /* mtk xhci scheduling info */ ++ u32 offset; ++ u32 repeat; ++ u32 pkts; ++ u32 cs_count; ++ u32 burst_mode; ++}; ++ ++ ++#if IS_ENABLED(CONFIG_USB_XHCI_MTK) ++ ++int xhci_mtk_init_quirk(struct xhci_hcd *xhci); ++void xhci_mtk_exit_quirk(struct xhci_hcd *xhci); ++int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev, ++ struct usb_host_endpoint *ep); ++void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev, ++ struct usb_host_endpoint *ep); ++u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total, ++ unsigned trb_buffer_length, struct urb *urb); ++ ++#else ++static inline int xhci_mtk_init_quirk(struct xhci_hcd *xhci) ++{ ++ return 0; ++} ++ ++static inline void xhci_mtk_exit_quirk(struct xhci_hcd *xhci) ++{ ++} ++ ++static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, ++ struct usb_device *udev, struct usb_host_endpoint *ep) ++{ ++ return 0; ++} ++ ++static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, ++ struct usb_device *udev, struct usb_host_endpoint *ep) ++{ ++ return 0; ++} ++ ++static inline u32 xhci_mtk_td_remainder_quirk(unsigned int td_running_total, ++ unsigned trb_buffer_length, struct urb *urb) ++{ ++ return 0; ++} ++ ++#endif ++ ++#endif /* _XHCI_MTK_H_ */ +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -23,6 +23,7 @@ + #include "xhci.h" + #include "xhci-mvebu.h" + #include "xhci-rcar.h" ++#include "xhci-mtk.h" + + static struct hc_driver __read_mostly xhci_plat_hc_driver; + +@@ -49,7 +50,23 @@ + return ret; + } + +- return xhci_gen_setup(hcd, xhci_plat_quirks); ++ ret = xhci_gen_setup(hcd, xhci_plat_quirks); ++ if (ret) ++ return ret; ++ ++ if (of_device_is_compatible(of_node, "mediatek,mt8173-xhci")) { ++ struct xhci_hcd *xhci = hcd_to_xhci(hcd); ++ ++ if (!usb_hcd_is_primary_hcd(hcd)) ++ return 0; ++ ret = xhci_mtk_init_quirk(xhci); ++ if (ret) { ++ kfree(xhci); ++ return ret; ++ } ++ } ++ ++ return ret; + } + + static int xhci_plat_start(struct usb_hcd *hcd) +@@ -207,6 +224,8 @@ + if (!IS_ERR(clk)) + clk_disable_unprepare(clk); + usb_put_hcd(hcd); ++ if (xhci->quirks & XHCI_MTK_HOST) ++ xhci_mtk_exit_quirk(xhci); + kfree(xhci); + + return 0; +@@ -253,6 +272,7 @@ + { .compatible = "marvell,armada-380-xhci"}, + { .compatible = "renesas,xhci-r8a7790"}, + { .compatible = "renesas,xhci-r8a7791"}, ++ { .compatible = "mediatek,mt8173-xhci"}, + { }, + }; + MODULE_DEVICE_TABLE(of, usb_xhci_of_match); +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -68,6 +68,7 @@ + #include + #include "xhci.h" + #include "xhci-trace.h" ++#include "xhci-mtk.h" + + /* + * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA +@@ -3163,9 +3164,14 @@ + + /* Set the TRB length, TD size, and interrupter fields. */ + if (xhci->hci_version < 0x100) { +- remainder = xhci_td_remainder( ++ if (xhci->quirks & XHCI_MTK_HOST) { ++ remainder = xhci_mtk_td_remainder_quirk( ++ running_total, trb_buff_len, urb); ++ } else { ++ remainder = xhci_td_remainder( + urb->transfer_buffer_length - + running_total); ++ } + } else { + remainder = xhci_v1_0_td_remainder(running_total, + trb_buff_len, total_packet_count, urb, +@@ -3336,9 +3342,14 @@ + + /* Set the TRB length, TD size, and interrupter fields. */ + if (xhci->hci_version < 0x100) { +- remainder = xhci_td_remainder( ++ if (xhci->quirks & XHCI_MTK_HOST) { ++ remainder = xhci_mtk_td_remainder_quirk( ++ running_total, trb_buff_len, urb); ++ } else { ++ remainder = xhci_td_remainder( + urb->transfer_buffer_length - + running_total); ++ } + } else { + remainder = xhci_v1_0_td_remainder(running_total, + trb_buff_len, total_packet_count, urb, +@@ -3457,8 +3468,14 @@ + field = TRB_TYPE(TRB_DATA); + + length_field = TRB_LEN(urb->transfer_buffer_length) | +- xhci_td_remainder(urb->transfer_buffer_length) | + TRB_INTR_TARGET(0); ++ ++ if (xhci->quirks & XHCI_MTK_HOST) ++ length_field |= xhci_mtk_td_remainder_quirk(0, ++ urb->transfer_buffer_length, urb); ++ else ++ length_field |= xhci_td_remainder(urb->transfer_buffer_length); ++ + if (urb->transfer_buffer_length > 0) { + if (setup->bRequestType & USB_DIR_IN) + field |= TRB_DIR_IN; +@@ -3682,8 +3699,14 @@ + + /* Set the TRB length, TD size, & interrupter fields. */ + if (xhci->hci_version < 0x100) { +- remainder = xhci_td_remainder( +- td_len - running_total); ++ if (xhci->quirks & XHCI_MTK_HOST) { ++ remainder = xhci_mtk_td_remainder_quirk( ++ running_total, trb_buff_len, ++ urb); ++ } else { ++ remainder = xhci_td_remainder( ++ td_len - running_total); ++ } + } else { + remainder = xhci_v1_0_td_remainder( + running_total, trb_buff_len, +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -31,6 +31,7 @@ + + #include "xhci.h" + #include "xhci-trace.h" ++#include "xhci-mtk.h" + + #define DRIVER_AUTHOR "Sarah Sharp" + #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" +@@ -624,7 +625,11 @@ + "// Set the interrupt modulation register"); + temp = readl(&xhci->ir_set->irq_control); + temp &= ~ER_IRQ_INTERVAL_MASK; +- temp |= (u32) 160; ++ /* ++ * the increment interval is 8 times as much as that defined ++ * in xHCI spec on MTK's controller ++ */ ++ temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160); + writel(temp, &xhci->ir_set->irq_control); + + /* Set the HCD state before we enable the irqs */ +@@ -1698,6 +1703,9 @@ + + xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); + ++ if (xhci->quirks & XHCI_MTK_HOST) ++ xhci_mtk_drop_ep_quirk(hcd, udev, ep); ++ + xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", + (unsigned int) ep->desc.bEndpointAddress, + udev->slot_id, +@@ -1793,6 +1801,12 @@ + return -ENOMEM; + } + ++ if (xhci->quirks & XHCI_MTK_HOST) { ++ ret = xhci_mtk_add_ep_quirk(hcd, udev, ep); ++ if (ret < 0) ++ return ret; ++ } ++ + ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); + new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); + +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1568,6 +1568,7 @@ + /* For controllers with a broken beyond repair streams implementation */ + #define XHCI_BROKEN_STREAMS (1 << 19) + #define XHCI_PME_STUCK_QUIRK (1 << 20) ++#define XHCI_MTK_HOST (1 << 21) + unsigned int num_active_eps; + unsigned int limit_active_eps; + /* There are two roothubs to keep track of bus suspend info for */ diff --git a/target/linux/mediatek/patches/0048-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt6.patch b/target/linux/mediatek/patches/0048-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt6.patch new file mode 100644 index 0000000..40303c0 --- /dev/null +++ b/target/linux/mediatek/patches/0048-dt-bindings-mediatek-Modify-pinctrl-bindings-for-mt6.patch @@ -0,0 +1,46 @@ +From 69b78182d6d7777153323abe3cff8e533ca01143 Mon Sep 17 00:00:00 2001 +From: Hongzhou Yang +Date: Mon, 18 May 2015 23:11:12 -0700 +Subject: [PATCH 48/76] dt-bindings: mediatek: Modify pinctrl bindings for + mt6397. + +Since 6397 is no need to support interrupt controller, +moving interrupt controller relate property to optional list. +Also adding mt8173 and mt8127 to bindings. + +Signed-off-by: Hongzhou Yang +--- + Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +index 5868a0f..0480bc3 100644 +--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt ++++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +@@ -3,9 +3,11 @@ + The Mediatek's Pin controller is used to control SoC pins. + + Required properties: +-- compatible: value should be either of the following. ++- compatible: value should be one of the following. + (a) "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. +-- mediatek,pctl-regmap: Should be a phandle of the syscfg node. ++ (b) "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. ++ (c) "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl. ++ (d) "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. + - pins-are-numbered: Specify the subnodes are using numbered pinmux to + specify pins. + - gpio-controller : Marks the device node as a gpio controller. +@@ -24,6 +26,9 @@ Required properties: + Only the following flags are supported: + 0 - GPIO_ACTIVE_HIGH + 1 - GPIO_ACTIVE_LOW ++ ++Optional properties: ++- mediatek,pctl-regmap: Should be a phandle of the syscfg node. + - reg: physicall address base for EINT registers + - interrupt-controller: Marks the device node as an interrupt controller + - #interrupt-cells: Should be two. +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0049-pinctrl-dt-bindings-mt6397-Add-pinfunc-header-file-f.patch b/target/linux/mediatek/patches/0049-pinctrl-dt-bindings-mt6397-Add-pinfunc-header-file-f.patch new file mode 100644 index 0000000..8178761 --- /dev/null +++ b/target/linux/mediatek/patches/0049-pinctrl-dt-bindings-mt6397-Add-pinfunc-header-file-f.patch @@ -0,0 +1,279 @@ +From 54596fafa4ce2723314d0381c7c1a525bda148ef Mon Sep 17 00:00:00 2001 +From: Hongzhou Yang +Date: Mon, 18 May 2015 23:11:13 -0700 +Subject: [PATCH 49/76] pinctrl: dt bindings: mt6397: Add pinfunc header file + for mt6397. + +Add pinfunc header file, mt8135/mt8173 relate dts will include it. + +Signed-off-by: Hongzhou Yang +--- + include/dt-bindings/pinctrl/mt6397-pinfunc.h | 256 ++++++++++++++++++++++++++ + 1 file changed, 256 insertions(+) + create mode 100644 include/dt-bindings/pinctrl/mt6397-pinfunc.h + +diff --git a/include/dt-bindings/pinctrl/mt6397-pinfunc.h b/include/dt-bindings/pinctrl/mt6397-pinfunc.h +new file mode 100644 +index 0000000..85739b3 +--- /dev/null ++++ b/include/dt-bindings/pinctrl/mt6397-pinfunc.h +@@ -0,0 +1,256 @@ ++#ifndef __DTS_MT6397_PINFUNC_H ++#define __DTS_MT6397_PINFUNC_H ++ ++#include ++ ++#define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) ++#define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1) ++ ++#define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) ++#define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1) ++#define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6) ++ ++#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) ++#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1) ++#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6) ++ ++#define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) ++#define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1) ++#define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6) ++ ++#define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) ++#define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1) ++ ++#define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) ++#define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1) ++ ++#define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) ++#define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1) ++ ++#define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) ++#define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1) ++ ++#define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) ++#define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1) ++ ++#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) ++#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1) ++#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6) ++#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7) ++ ++#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) ++#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1) ++#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6) ++#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7) ++ ++#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) ++#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1) ++#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6) ++#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7) ++ ++#define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) ++#define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1) ++#define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2) ++#define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3) ++#define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6) ++#define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7) ++ ++#define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) ++#define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1) ++#define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2) ++#define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3) ++#define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6) ++#define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7) ++ ++#define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) ++#define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1) ++#define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2) ++#define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3) ++#define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6) ++#define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7) ++ ++#define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) ++#define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1) ++#define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2) ++#define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3) ++#define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6) ++#define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7) ++ ++#define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) ++#define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1) ++#define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2) ++#define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3) ++#define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6) ++#define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7) ++ ++#define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) ++#define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1) ++#define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2) ++#define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3) ++#define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6) ++#define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7) ++ ++#define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) ++#define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1) ++#define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2) ++#define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3) ++#define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4) ++#define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5) ++#define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6) ++#define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7) ++ ++#define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) ++#define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1) ++#define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2) ++#define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3) ++#define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4) ++#define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5) ++#define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6) ++#define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7) ++ ++#define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) ++#define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1) ++#define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2) ++#define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3) ++#define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6) ++#define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7) ++ ++#define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) ++#define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1) ++#define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2) ++#define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3) ++#define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4) ++#define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6) ++#define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7) ++ ++#define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) ++#define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1) ++#define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2) ++#define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3) ++#define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6) ++#define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7) ++ ++#define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) ++#define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1) ++#define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2) ++#define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3) ++#define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6) ++#define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7) ++ ++#define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) ++#define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1) ++#define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2) ++#define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3) ++#define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6) ++#define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7) ++ ++#define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) ++#define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1) ++#define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2) ++#define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3) ++#define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6) ++#define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7) ++ ++#define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) ++#define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1) ++#define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2) ++#define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3) ++#define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4) ++#define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5) ++#define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6) ++#define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7) ++ ++#define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) ++#define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1) ++#define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2) ++#define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3) ++#define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4) ++#define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5) ++#define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6) ++#define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7) ++ ++#define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) ++#define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1) ++#define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2) ++#define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4) ++#define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5) ++#define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6) ++#define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7) ++ ++#define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) ++#define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1) ++#define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2) ++#define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4) ++#define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5) ++#define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6) ++#define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7) ++ ++#define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) ++#define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1) ++#define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2) ++#define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3) ++#define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4) ++#define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5) ++#define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6) ++#define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7) ++ ++#define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) ++#define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1) ++#define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2) ++#define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3) ++#define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6) ++#define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7) ++ ++#define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) ++#define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1) ++#define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2) ++#define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6) ++#define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7) ++ ++#define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) ++#define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1) ++#define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2) ++#define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3) ++#define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6) ++#define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7) ++ ++#define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) ++#define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1) ++#define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2) ++#define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6) ++#define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7) ++ ++#define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) ++#define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1) ++#define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2) ++#define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3) ++#define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6) ++#define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7) ++ ++#define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) ++#define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1) ++#define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2) ++#define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6) ++#define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7) ++ ++#define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) ++#define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1) ++#define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6) ++#define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7) ++ ++#define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) ++#define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1) ++#define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6) ++#define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7) ++ ++#define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) ++#define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1) ++#define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6) ++#define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7) ++ ++#define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) ++#define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1) ++#define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6) ++#define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7) ++ ++#endif /* __DTS_MT6397_PINFUNC_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0050-pinctrl-mediatek-data-struct-optimize-and-remove-unu.patch b/target/linux/mediatek/patches/0050-pinctrl-mediatek-data-struct-optimize-and-remove-unu.patch new file mode 100644 index 0000000..7399746 --- /dev/null +++ b/target/linux/mediatek/patches/0050-pinctrl-mediatek-data-struct-optimize-and-remove-unu.patch @@ -0,0 +1,116 @@ +From 3eeb897a627e26083472f14e7512f53276a5e7ce Mon Sep 17 00:00:00 2001 +From: Yingjoe Chen +Date: Mon, 18 May 2015 23:11:14 -0700 +Subject: [PATCH 50/76] pinctrl: mediatek: data struct optimize and remove + unused member + +struct mtk_desc_pin.chip, mtk_pinctrl_devdata.invser_offset +and mtk_pinctrl_devdata.chip_type are never used in code. +Remove them. + +Some per-pin data are using int for pin number and offsets. +Change to short and rearrange to reduce const data size. + +Signed-off-by: Yingjoe Chen +Signed-off-by: Hongzhou Yang +--- + drivers/pinctrl/mediatek/pinctrl-mt8135.c | 10 ++++------ + drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 10 ++-------- + 2 files changed, 6 insertions(+), 14 deletions(-) + +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c +index f1e1e18..8e6abd5 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c +@@ -32,12 +32,12 @@ + #define R1_BASE2 0x250 + + struct mtk_spec_pull_set { +- unsigned int pin; +- unsigned int pupd_offset; ++ unsigned char pin; + unsigned char pupd_bit; +- unsigned int r0_offset; ++ unsigned short pupd_offset; ++ unsigned short r0_offset; ++ unsigned short r1_offset; + unsigned char r0_bit; +- unsigned int r1_offset; + unsigned char r1_bit; + }; + +@@ -305,7 +305,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { + .pullen_offset = 0x0200, + .smt_offset = 0x0300, + .pullsel_offset = 0x0400, +- .invser_offset = 0x0600, + .dout_offset = 0x0800, + .din_offset = 0x0A00, + .pinmux_offset = 0x0C00, +@@ -314,7 +313,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { + .port_shf = 4, + .port_mask = 0xf, + .port_align = 4, +- .chip_type = MTK_CHIP_TYPE_BASE, + .eint_offsets = { + .name = "mt8135_eint", + .stat = 0x000, +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +index 375771d..1508849 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +@@ -19,8 +19,6 @@ + #include + + #define NO_EINT_SUPPORT 255 +-#define MTK_CHIP_TYPE_BASE 0 +-#define MTK_CHIP_TYPE_PMIC 1 + #define MT_EDGE_SENSITIVE 0 + #define MT_LEVEL_SENSITIVE 1 + #define EINT_DBNC_SET_DBNC_BITS 4 +@@ -39,7 +37,6 @@ struct mtk_desc_eint { + + struct mtk_desc_pin { + struct pinctrl_pin_desc pin; +- const char *chip; + const struct mtk_desc_eint eint; + const struct mtk_desc_function *functions; + }; +@@ -47,7 +44,6 @@ struct mtk_desc_pin { + #define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ + { \ + .pin = _pin, \ +- .chip = _chip, \ + .eint = _eint, \ + .functions = (struct mtk_desc_function[]){ \ + __VA_ARGS__, { } }, \ +@@ -107,8 +103,8 @@ struct mtk_drv_group_desc { + * @grp: The group for this pin belongs to. + */ + struct mtk_pin_drv_grp { +- unsigned int pin; +- unsigned int offset; ++ unsigned short pin; ++ unsigned short offset; + unsigned char bit; + unsigned char grp; + }; +@@ -193,7 +189,6 @@ struct mtk_pinctrl_devdata { + unsigned int pullen_offset; + unsigned int pullsel_offset; + unsigned int drv_offset; +- unsigned int invser_offset; + unsigned int dout_offset; + unsigned int din_offset; + unsigned int pinmux_offset; +@@ -202,7 +197,6 @@ struct mtk_pinctrl_devdata { + unsigned char port_shf; + unsigned char port_mask; + unsigned char port_align; +- unsigned char chip_type; + struct mtk_eint_offsets eint_offsets; + unsigned int ap_num; + unsigned int db_cnt; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0051-pinctrl-mediatek-add-mtk_pctrl_spec_pull_set_samereg.patch b/target/linux/mediatek/patches/0051-pinctrl-mediatek-add-mtk_pctrl_spec_pull_set_samereg.patch new file mode 100644 index 0000000..2e9eb60 --- /dev/null +++ b/target/linux/mediatek/patches/0051-pinctrl-mediatek-add-mtk_pctrl_spec_pull_set_samereg.patch @@ -0,0 +1,328 @@ +From aefbeb75a32e080445d72ddd4b9ab28c258597d0 Mon Sep 17 00:00:00 2001 +From: Yingjoe Chen +Date: Mon, 18 May 2015 23:11:15 -0700 +Subject: [PATCH 51/76] pinctrl: mediatek: add mtk_pctrl_spec_pull_set_samereg + common code + +Several mediatek soc use similar pull setting procedure as mt8173, +the pupd enable and resistance setting are in the same register. +Add common code mtk_pctrl_spec_pull_set_samereg out of spec_pull_set +in mt8173 to handle this case, so future soc driver can use it. + +Signed-off-by: Yingjoe Chen +Signed-off-by: Hongzhou Yang +--- + drivers/pinctrl/mediatek/pinctrl-mt8173.c | 166 +++++++------------------ + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 60 +++++++++ + drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 31 +++++ + 3 files changed, 136 insertions(+), 121 deletions(-) + +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c +index 412ea84..cc44b27 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c +@@ -47,130 +47,54 @@ struct mtk_pin_ies_smt_set { + .offset = _offset, \ + } + +-/** +- * struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting. +- * @pin: The pin number. +- * @offset: The offset of special pull up/down setting register. +- * @pupd_bit: The pull up/down bit in this register. +- * @r0_bit: The r0 bit of pull resistor. +- * @r1_bit: The r1 bit of pull resistor. +- */ +-struct mtk_pin_spec_pupd_set { +- unsigned int pin; +- unsigned int offset; +- unsigned char pupd_bit; +- unsigned char r1_bit; +- unsigned char r0_bit; +-}; +- +-#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \ +- { \ +- .pin = _pin, \ +- .offset = _offset, \ +- .pupd_bit = _pupd, \ +- .r1_bit = _r1, \ +- .r0_bit = _r0, \ +- } +- +-static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = { +- MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */ +- MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */ +- MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */ +- MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */ +- MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */ +- MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */ +- +- MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */ +- MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */ +- MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */ +- MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */ +- MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */ +- MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */ +- MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */ +- MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */ +- MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */ +- MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */ +- MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */ +- MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */ +- +- MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */ +- MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ +- MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ +- MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ +- MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ +- MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */ +- +- MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */ +- MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */ +- MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */ +- MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */ +- MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */ +- MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */ +- +- MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */ +- MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */ +- MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */ +- MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */ +- MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */ +- MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ ++static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { ++ MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */ ++ MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */ ++ MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */ ++ MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */ ++ MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */ ++ MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */ ++ ++ MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */ ++ MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */ ++ MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */ ++ MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */ ++ MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */ ++ MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */ ++ MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */ ++ MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */ ++ MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */ ++ MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */ ++ MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */ ++ MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */ ++ ++ MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */ ++ MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ ++ MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ ++ MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ ++ MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ ++ MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */ ++ ++ MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */ ++ MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */ ++ MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */ ++ MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */ ++ MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */ ++ MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */ ++ ++ MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */ ++ MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */ ++ MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */ ++ MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */ ++ MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */ ++ MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ + }; + +-static int spec_pull_set(struct regmap *regmap, unsigned int pin, ++static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) + { +- unsigned int i; +- unsigned int reg_pupd, reg_set, reg_rst; +- unsigned int bit_pupd, bit_r0, bit_r1; +- const struct mtk_pin_spec_pupd_set *spec_pupd_pin; +- bool find = false; +- +- for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) { +- if (pin == mt8173_spec_pupd[i].pin) { +- find = true; +- break; +- } +- } +- +- if (!find) +- return -EINVAL; +- +- spec_pupd_pin = mt8173_spec_pupd + i; +- reg_set = spec_pupd_pin->offset + align; +- reg_rst = spec_pupd_pin->offset + (align << 1); +- +- if (isup) +- reg_pupd = reg_rst; +- else +- reg_pupd = reg_set; +- +- bit_pupd = BIT(spec_pupd_pin->pupd_bit); +- regmap_write(regmap, reg_pupd, bit_pupd); +- +- bit_r0 = BIT(spec_pupd_pin->r0_bit); +- bit_r1 = BIT(spec_pupd_pin->r1_bit); +- +- switch (r1r0) { +- case MTK_PUPD_SET_R1R0_00: +- regmap_write(regmap, reg_rst, bit_r0); +- regmap_write(regmap, reg_rst, bit_r1); +- break; +- case MTK_PUPD_SET_R1R0_01: +- regmap_write(regmap, reg_set, bit_r0); +- regmap_write(regmap, reg_rst, bit_r1); +- break; +- case MTK_PUPD_SET_R1R0_10: +- regmap_write(regmap, reg_rst, bit_r0); +- regmap_write(regmap, reg_set, bit_r1); +- break; +- case MTK_PUPD_SET_R1R0_11: +- regmap_write(regmap, reg_set, bit_r0); +- regmap_write(regmap, reg_set, bit_r1); +- break; +- default: +- return -EINVAL; +- } +- +- return 0; ++ return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd, ++ ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0); + } + + static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = { +@@ -382,7 +306,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { + .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), + .pin_drv_grp = mt8173_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), +- .spec_pull_set = spec_pull_set, ++ .spec_pull_set = mt8173_spec_pull_set, + .spec_ies_smt_set = spec_ies_smt_set, + .dir_offset = 0x0000, + .pullen_offset = 0x0100, +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +index 474812e..0d51145 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +@@ -186,6 +186,66 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, + return -EINVAL; + } + ++int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, ++ const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, ++ unsigned int info_num, unsigned int pin, ++ unsigned char align, bool isup, unsigned int r1r0) ++{ ++ unsigned int i; ++ unsigned int reg_pupd, reg_set, reg_rst; ++ unsigned int bit_pupd, bit_r0, bit_r1; ++ const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; ++ bool find = false; ++ ++ for (i = 0; i < info_num; i++) { ++ if (pin == pupd_infos[i].pin) { ++ find = true; ++ break; ++ } ++ } ++ ++ if (!find) ++ return -EINVAL; ++ ++ spec_pupd_pin = pupd_infos + i; ++ reg_set = spec_pupd_pin->offset + align; ++ reg_rst = spec_pupd_pin->offset + (align << 1); ++ ++ if (isup) ++ reg_pupd = reg_rst; ++ else ++ reg_pupd = reg_set; ++ ++ bit_pupd = BIT(spec_pupd_pin->pupd_bit); ++ regmap_write(regmap, reg_pupd, bit_pupd); ++ ++ bit_r0 = BIT(spec_pupd_pin->r0_bit); ++ bit_r1 = BIT(spec_pupd_pin->r1_bit); ++ ++ switch (r1r0) { ++ case MTK_PUPD_SET_R1R0_00: ++ regmap_write(regmap, reg_rst, bit_r0); ++ regmap_write(regmap, reg_rst, bit_r1); ++ break; ++ case MTK_PUPD_SET_R1R0_01: ++ regmap_write(regmap, reg_set, bit_r0); ++ regmap_write(regmap, reg_rst, bit_r1); ++ break; ++ case MTK_PUPD_SET_R1R0_10: ++ regmap_write(regmap, reg_rst, bit_r0); ++ regmap_write(regmap, reg_set, bit_r1); ++ break; ++ case MTK_PUPD_SET_R1R0_11: ++ regmap_write(regmap, reg_set, bit_r0); ++ regmap_write(regmap, reg_set, bit_r1); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, + unsigned int pin, bool enable, bool isup, unsigned int arg) + { +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +index 1508849..2a4b7be 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +@@ -117,6 +117,32 @@ struct mtk_pin_drv_grp { + .grp = _grp, \ + } + ++/** ++ * struct mtk_pin_spec_pupd_set_samereg ++ * - For special pins' pull up/down setting which resides in same register ++ * @pin: The pin number. ++ * @offset: The offset of special pull up/down setting register. ++ * @pupd_bit: The pull up/down bit in this register. ++ * @r0_bit: The r0 bit of pull resistor. ++ * @r1_bit: The r1 bit of pull resistor. ++ */ ++struct mtk_pin_spec_pupd_set_samereg { ++ unsigned short pin; ++ unsigned short offset; ++ unsigned char pupd_bit; ++ unsigned char r1_bit; ++ unsigned char r0_bit; ++}; ++ ++#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ ++ { \ ++ .pin = _pin, \ ++ .offset = _offset, \ ++ .pupd_bit = _pupd, \ ++ .r1_bit = _r1, \ ++ .r0_bit = _r0, \ ++ } ++ + struct mtk_eint_offsets { + const char *name; + unsigned int stat; +@@ -220,4 +246,9 @@ struct mtk_pinctrl { + int mtk_pctrl_init(struct platform_device *pdev, + const struct mtk_pinctrl_devdata *data); + ++int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, ++ const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, ++ unsigned int info_num, unsigned int pin, ++ unsigned char align, bool isup, unsigned int r1r0); ++ + #endif /* __PINCTRL_MTK_COMMON_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0052-pinctrl-mediatek-add-ies-smt-control-to-common-code.patch b/target/linux/mediatek/patches/0052-pinctrl-mediatek-add-ies-smt-control-to-common-code.patch new file mode 100644 index 0000000..5467c21 --- /dev/null +++ b/target/linux/mediatek/patches/0052-pinctrl-mediatek-add-ies-smt-control-to-common-code.patch @@ -0,0 +1,479 @@ +From 32ea3b91046bea40cd1a7a4f16a24d75f53ca92a Mon Sep 17 00:00:00 2001 +From: Hongzhou Yang +Date: Mon, 18 May 2015 23:11:16 -0700 +Subject: [PATCH 52/76] pinctrl: mediatek: add ies/smt control to common code. + +Input enable and smt setting have different register, +modify code to fix it. + +Several mediatek soc use similar input enable/smt setting +procedure as mt8173, some soc use generic input enable/smt +setting, some soc has no input enable/smt setting. Adding +common code to handle all those cases, so future soc driver +can use it. + +Signed-off-by: Hongzhou Yang +--- + drivers/pinctrl/mediatek/pinctrl-mt8173.c | 201 +++++++++++++------------ + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 82 +++++++--- + drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 31 +++- + 3 files changed, 198 insertions(+), 116 deletions(-) + +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c +index cc44b27..a7e5b24 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + #include + + #include "pinctrl-mtk-common.h" +@@ -25,28 +26,6 @@ + + #define DRV_BASE 0xb00 + +-/** +- * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting. +- * @start: The start pin number of those special pins. +- * @end: The end pin number of those special pins. +- * @offset: The offset of special setting register. +- * @bit: The bit of special setting register. +- */ +-struct mtk_pin_ies_smt_set { +- unsigned int start; +- unsigned int end; +- unsigned int offset; +- unsigned char bit; +-}; +- +-#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \ +- { \ +- .start = _start, \ +- .end = _end, \ +- .bit = _bit, \ +- .offset = _offset, \ +- } +- + static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */ + MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */ +@@ -97,80 +76,114 @@ static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin, + ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0); + } + +-static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = { +- MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1), +- MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2), +- MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10), +- MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10), +- MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0), +- MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2), +- MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3), +- MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3), +- MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4), +- MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5), +- MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6), +- MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7), +- MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9), +- MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0), +- MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11), +- MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12), +- MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13), +- MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13), +- MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13), +- MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13), +- MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13), +- MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14), +- MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13), +- MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13), +- MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13), +- MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15), +- MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0), +- MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1), +- MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2), +- MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13), +- MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14), +- MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15), +- MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13), +- MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13), +- MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13), +- MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4), +- MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1), +- MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2), +- MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5), +- MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6), +- MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7), +- MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0), +- MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8), +- MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9), +- MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8), +- MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8) ++static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = { ++ MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1), ++ MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2), ++ MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10), ++ MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10), ++ MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0), ++ MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2), ++ MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3), ++ MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3), ++ MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4), ++ MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5), ++ MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6), ++ MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7), ++ MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9), ++ MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0), ++ MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11), ++ MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12), ++ MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13), ++ MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13), ++ MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13), ++ MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13), ++ MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13), ++ MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14), ++ MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13), ++ MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13), ++ MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13), ++ MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15), ++ MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0), ++ MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1), ++ MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2), ++ MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13), ++ MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14), ++ MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15), ++ MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13), ++ MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13), ++ MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13), ++ MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4), ++ MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1), ++ MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2), ++ MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5), ++ MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6), ++ MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7), ++ MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0), ++ MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8), ++ MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9), ++ MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8), ++ MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) + }; + +-static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin, +- unsigned char align, int value) +-{ +- unsigned int i, reg_addr, bit; +- bool find = false; +- +- for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) { +- if (pin >= mt8173_ies_smt_set[i].start && +- pin <= mt8173_ies_smt_set[i].end) { +- find = true; +- break; +- } +- } +- +- if (!find) +- return -EINVAL; +- +- if (value) +- reg_addr = mt8173_ies_smt_set[i].offset + align; +- else +- reg_addr = mt8173_ies_smt_set[i].offset + (align << 1); ++static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { ++ MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1), ++ MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2), ++ MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10), ++ MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10), ++ MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0), ++ MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2), ++ MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3), ++ MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), ++ MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4), ++ MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5), ++ MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6), ++ MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7), ++ MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9), ++ MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0), ++ MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11), ++ MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12), ++ MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14), ++ MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14), ++ MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14), ++ MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14), ++ MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14), ++ MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14), ++ MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14), ++ MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14), ++ MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14), ++ MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15), ++ MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0), ++ MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1), ++ MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2), ++ MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13), ++ MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14), ++ MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15), ++ MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14), ++ MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14), ++ MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14), ++ MTK_PIN_IES_SMT_SPEC(106, 107, 0x91, 4), ++ MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1), ++ MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2), ++ MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5), ++ MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6), ++ MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7), ++ MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0), ++ MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8), ++ MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9), ++ MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8), ++ MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) ++}; + +- bit = BIT(mt8173_ies_smt_set[i].bit); +- regmap_write(regmap, reg_addr, bit); +- return 0; ++static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin, ++ unsigned char align, int value, enum pin_config_param arg) ++{ ++ if (arg == PIN_CONFIG_INPUT_ENABLE) ++ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set, ++ ARRAY_SIZE(mt8173_ies_set), pin, align, value); ++ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) ++ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set, ++ ARRAY_SIZE(mt8173_smt_set), pin, align, value); ++ return -EINVAL; + } + + static const struct mtk_drv_group_desc mt8173_drv_grp[] = { +@@ -307,7 +320,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { + .pin_drv_grp = mt8173_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), + .spec_pull_set = mt8173_spec_pull_set, +- .spec_ies_smt_set = spec_ies_smt_set, ++ .spec_ies_smt_set = mt8173_ies_smt_set, + .dir_offset = 0x0000, + .pullen_offset = 0x0100, + .pullsel_offset = 0x0200, +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +index 0d51145..97fe2ab 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +@@ -107,28 +107,38 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) + regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); + } + +-static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, +- int value, enum pin_config_param param) ++static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, ++ int value, enum pin_config_param arg) + { + unsigned int reg_addr, offset; + unsigned int bit; +- int ret; ++ ++ /** ++ * Due to some soc are not support ies/smt config, add this special ++ * control to handle it. ++ */ ++ if (!pctl->devdata->spec_ies_smt_set && ++ pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && ++ arg == PIN_CONFIG_INPUT_ENABLE) ++ return -EINVAL; ++ ++ if (!pctl->devdata->spec_ies_smt_set && ++ pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && ++ arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) ++ return -EINVAL; + + /* + * Due to some pins are irregular, their input enable and smt +- * control register are discontinuous, but they are mapping together. +- * So we need this special handle. ++ * control register are discontinuous, so we need this special handle. + */ + if (pctl->devdata->spec_ies_smt_set) { +- ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), +- pin, pctl->devdata->port_align, value); +- if (!ret) +- return; ++ return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), ++ pin, pctl->devdata->port_align, value, arg); + } + + bit = BIT(pin & 0xf); + +- if (param == PIN_CONFIG_INPUT_ENABLE) ++ if (arg == PIN_CONFIG_INPUT_ENABLE) + offset = pctl->devdata->ies_offset; + else + offset = pctl->devdata->smt_offset; +@@ -139,6 +149,33 @@ static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, + reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); + + regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); ++ return 0; ++} ++ ++int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, ++ const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, ++ unsigned int pin, unsigned char align, int value) ++{ ++ unsigned int i, reg_addr, bit; ++ ++ for (i = 0; i < info_num; i++) { ++ if (pin >= ies_smt_infos[i].start && ++ pin <= ies_smt_infos[i].end) { ++ break; ++ } ++ } ++ ++ if (i == info_num) ++ return -EINVAL; ++ ++ if (value) ++ reg_addr = ies_smt_infos[i].offset + align; ++ else ++ reg_addr = ies_smt_infos[i].offset + (align << 1); ++ ++ bit = BIT(ies_smt_infos[i].bit); ++ regmap_write(regmap, reg_addr, bit); ++ return 0; + } + + static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( +@@ -295,36 +332,37 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, + unsigned int pin, enum pin_config_param param, + enum pin_config_param arg) + { ++ int ret = 0; + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: +- mtk_pconf_set_pull_select(pctl, pin, false, false, arg); ++ ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); + break; + case PIN_CONFIG_BIAS_PULL_UP: +- mtk_pconf_set_pull_select(pctl, pin, true, true, arg); ++ ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: +- mtk_pconf_set_pull_select(pctl, pin, true, false, arg); ++ ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); + break; + case PIN_CONFIG_INPUT_ENABLE: +- mtk_pconf_set_ies_smt(pctl, pin, arg, param); ++ ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); + break; + case PIN_CONFIG_OUTPUT: + mtk_gpio_set(pctl->chip, pin, arg); +- mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); ++ ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: +- mtk_pconf_set_ies_smt(pctl, pin, arg, param); ++ ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); + break; + case PIN_CONFIG_DRIVE_STRENGTH: +- mtk_pconf_set_driving(pctl, pin, arg); ++ ret = mtk_pconf_set_driving(pctl, pin, arg); + break; + default: +- return -EINVAL; ++ ret = -EINVAL; + } + +- return 0; ++ return ret; + } + + static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, +@@ -343,12 +381,14 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + { + struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct mtk_pinctrl_group *g = &pctl->groups[group]; +- int i; ++ int i, ret; + + for (i = 0; i < num_configs; i++) { +- mtk_pconf_parse_conf(pctldev, g->pin, ++ ret = mtk_pconf_parse_conf(pctldev, g->pin, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); ++ if (ret < 0) ++ return ret; + + g->config = configs[i]; + } +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +index 2a4b7be..c703e7d 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +@@ -17,6 +17,7 @@ + + #include + #include ++#include + + #define NO_EINT_SUPPORT 255 + #define MT_EDGE_SENSITIVE 0 +@@ -25,6 +26,8 @@ + #define EINT_DBNC_RST_BIT (0x1 << 1) + #define EINT_DBNC_SET_EN (0x1 << 0) + ++#define MTK_PINCTRL_NOT_SUPPORT (0xffff) ++ + struct mtk_desc_function { + const char *name; + unsigned char muxval; +@@ -143,6 +146,28 @@ struct mtk_pin_spec_pupd_set_samereg { + .r0_bit = _r0, \ + } + ++/** ++ * struct mtk_pin_ies_set - For special pins' ies and smt setting. ++ * @start: The start pin number of those special pins. ++ * @end: The end pin number of those special pins. ++ * @offset: The offset of special setting register. ++ * @bit: The bit of special setting register. ++ */ ++struct mtk_pin_ies_smt_set { ++ unsigned short start; ++ unsigned short end; ++ unsigned short offset; ++ unsigned char bit; ++}; ++ ++#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ ++ { \ ++ .start = _start, \ ++ .end = _end, \ ++ .bit = _bit, \ ++ .offset = _offset, \ ++ } ++ + struct mtk_eint_offsets { + const char *name; + unsigned int stat; +@@ -208,7 +233,7 @@ struct mtk_pinctrl_devdata { + int (*spec_pull_set)(struct regmap *reg, unsigned int pin, + unsigned char align, bool isup, unsigned int arg); + int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, +- unsigned char align, int value); ++ unsigned char align, int value, enum pin_config_param arg); + unsigned int dir_offset; + unsigned int ies_offset; + unsigned int smt_offset; +@@ -251,4 +276,8 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, + unsigned int info_num, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0); + ++int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, ++ const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, ++ unsigned int pin, unsigned char align, int value); ++ + #endif /* __PINCTRL_MTK_COMMON_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0053-pinctrl-mediatek-Add-Pinctrl-GPIO-driver-for-mt6397.patch b/target/linux/mediatek/patches/0053-pinctrl-mediatek-Add-Pinctrl-GPIO-driver-for-mt6397.patch new file mode 100644 index 0000000..2813f40 --- /dev/null +++ b/target/linux/mediatek/patches/0053-pinctrl-mediatek-Add-Pinctrl-GPIO-driver-for-mt6397.patch @@ -0,0 +1,654 @@ +From 3031cefd8cd323e04be11a8058616d8cf21c1313 Mon Sep 17 00:00:00 2001 +From: Hongzhou Yang +Date: Mon, 18 May 2015 23:11:17 -0700 +Subject: [PATCH 53/76] pinctrl: mediatek: Add Pinctrl/GPIO driver for mt6397. + +Add mt6397 support using mediatek common pinctrl driver. + +mt6397 is a PMIC, and pinctrl/GPIO is part of 6397 chip. +Pinctrl/GPIO driver should obtain regmap from PMIC, +so adding this support to common code. + +Also, mt6397 is no need to support interrupt controller, +so changing common code to skip it. + +Signed-off-by: Hongzhou Yang +--- + drivers/pinctrl/mediatek/Kconfig | 6 + + drivers/pinctrl/mediatek/Makefile | 1 + + drivers/pinctrl/mediatek/pinctrl-mt6397.c | 78 +++++ + drivers/pinctrl/mediatek/pinctrl-mt8135.c | 2 +- + drivers/pinctrl/mediatek/pinctrl-mt8173.c | 2 +- + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 13 +- + drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 3 +- + drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h | 424 +++++++++++++++++++++++++ + 8 files changed, 524 insertions(+), 5 deletions(-) + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6397.c + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h + +diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig +index 6b3551c..ddae479 100644 +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -23,4 +23,10 @@ config PINCTRL_MT8173 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_COMMON + ++# For PMIC ++config PINCTRL_MT6397 ++ bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397 ++ default MFD_MT6397 ++ select PINCTRL_MTK_COMMON ++ + endif +diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile +index d8606a2..ad0180c 100644 +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o + # SoC Drivers + obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o ++obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c +new file mode 100644 +index 0000000..767bbdf +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c +@@ -0,0 +1,78 @@ ++/* ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: Hongzhou.Yang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pinctrl-mtk-common.h" ++#include "pinctrl-mtk-mt6397.h" ++ ++#define MT6397_PIN_REG_BASE 0xc000 ++ ++static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = { ++ .pins = mtk_pins_mt6397, ++ .npins = ARRAY_SIZE(mtk_pins_mt6397), ++ .dir_offset = (MT6397_PIN_REG_BASE + 0x000), ++ .ies_offset = MTK_PINCTRL_NOT_SUPPORT, ++ .smt_offset = MTK_PINCTRL_NOT_SUPPORT, ++ .pullen_offset = (MT6397_PIN_REG_BASE + 0x020), ++ .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040), ++ .dout_offset = (MT6397_PIN_REG_BASE + 0x080), ++ .din_offset = (MT6397_PIN_REG_BASE + 0x0a0), ++ .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0), ++ .type1_start = 41, ++ .type1_end = 41, ++ .port_shf = 3, ++ .port_mask = 0x3, ++ .port_align = 2, ++}; ++ ++static int mt6397_pinctrl_probe(struct platform_device *pdev) ++{ ++ struct mt6397_chip *mt6397; ++ ++ mt6397 = dev_get_drvdata(pdev->dev.parent); ++ return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap); ++} ++ ++static const struct of_device_id mt6397_pctrl_match[] = { ++ { .compatible = "mediatek,mt6397-pinctrl", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, mt6397_pctrl_match); ++ ++static struct platform_driver mtk_pinctrl_driver = { ++ .probe = mt6397_pinctrl_probe, ++ .driver = { ++ .name = "mediatek-mt6397-pinctrl", ++ .owner = THIS_MODULE, ++ .of_match_table = mt6397_pctrl_match, ++ }, ++}; ++ ++static int __init mtk_pinctrl_init(void) ++{ ++ return platform_driver_register(&mtk_pinctrl_driver); ++} ++ ++module_init(mtk_pinctrl_init); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver"); ++MODULE_AUTHOR("Hongzhou Yang "); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c +index 8e6abd5..203bd2a 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c +@@ -342,7 +342,7 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { + + static int mt8135_pinctrl_probe(struct platform_device *pdev) + { +- return mtk_pctrl_init(pdev, &mt8135_pinctrl_data); ++ return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL); + } + + static const struct of_device_id mt8135_pctrl_match[] = { +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c +index a7e5b24..cf4ed6e 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c +@@ -361,7 +361,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { + + static int mt8173_pinctrl_probe(struct platform_device *pdev) + { +- return mtk_pctrl_init(pdev, &mt8173_pinctrl_data); ++ return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL); + } + + static const struct of_device_id mt8173_pctrl_match[] = { +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +index 97fe2ab..e772cef 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +@@ -1209,7 +1209,8 @@ static struct pinctrl_desc mtk_pctrl_desc = { + }; + + int mtk_pctrl_init(struct platform_device *pdev, +- const struct mtk_pinctrl_devdata *data) ++ const struct mtk_pinctrl_devdata *data, ++ struct regmap *regmap) + { + struct pinctrl_pin_desc *pins; + struct mtk_pinctrl *pctl; +@@ -1235,6 +1236,11 @@ int mtk_pctrl_init(struct platform_device *pdev, + pctl->regmap1 = syscon_node_to_regmap(node); + if (IS_ERR(pctl->regmap1)) + return PTR_ERR(pctl->regmap1); ++ } else if (regmap) { ++ pctl->regmap1 = regmap; ++ } else { ++ dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); ++ return -EINVAL; + } + + /* Only 8135 has two base addr, other SoCs have only one. */ +@@ -1280,7 +1286,7 @@ int mtk_pctrl_init(struct platform_device *pdev, + pctl->chip->ngpio = pctl->devdata->npins; + pctl->chip->label = dev_name(&pdev->dev); + pctl->chip->dev = &pdev->dev; +- pctl->chip->base = 0; ++ pctl->chip->base = -1; + + ret = gpiochip_add(pctl->chip); + if (ret) { +@@ -1296,6 +1302,9 @@ int mtk_pctrl_init(struct platform_device *pdev, + goto chip_error; + } + ++ if (of_find_property(np, "interrupt-controller", NULL)) ++ return 0; ++ + /* Get EINT register base from dts. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +index c703e7d..30213e5 100644 +--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +@@ -269,7 +269,8 @@ struct mtk_pinctrl { + }; + + int mtk_pctrl_init(struct platform_device *pdev, +- const struct mtk_pinctrl_devdata *data); ++ const struct mtk_pinctrl_devdata *data, ++ struct regmap *regmap); + + int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, + const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h +new file mode 100644 +index 0000000..4eb98dd +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h +@@ -0,0 +1,424 @@ ++#ifndef __PINCTRL_MTK_MT6397_H ++#define __PINCTRL_MTK_MT6397_H ++ ++#include ++#include "pinctrl-mtk-common.h" ++ ++static const struct mtk_desc_pin mtk_pins_mt6397[] = { ++ MTK_PIN( ++ PINCTRL_PIN(0, "INT"), ++ "N2", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO0"), ++ MTK_FUNCTION(1, "INT") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(1, "SRCVOLTEN"), ++ "M4", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO1"), ++ MTK_FUNCTION(1, "SRCVOLTEN"), ++ MTK_FUNCTION(6, "TEST_CK1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(2, "SRCLKEN_PERI"), ++ "M2", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO2"), ++ MTK_FUNCTION(1, "SRCLKEN_PERI"), ++ MTK_FUNCTION(6, "TEST_CK2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(3, "RTC_32K1V8"), ++ "K3", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO3"), ++ MTK_FUNCTION(1, "RTC_32K1V8"), ++ MTK_FUNCTION(6, "TEST_CK3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(4, "WRAP_EVENT"), ++ "J2", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO4"), ++ MTK_FUNCTION(1, "WRAP_EVENT") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(5, "SPI_CLK"), ++ "L4", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO5"), ++ MTK_FUNCTION(1, "SPI_CLK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(6, "SPI_CSN"), ++ "J3", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO6"), ++ MTK_FUNCTION(1, "SPI_CSN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(7, "SPI_MOSI"), ++ "J1", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO7"), ++ MTK_FUNCTION(1, "SPI_MOSI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(8, "SPI_MISO"), ++ "L3", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO8"), ++ MTK_FUNCTION(1, "SPI_MISO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(9, "AUD_CLK_MOSI"), ++ "H2", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO9"), ++ MTK_FUNCTION(1, "AUD_CLK"), ++ MTK_FUNCTION(6, "TEST_IN0"), ++ MTK_FUNCTION(7, "TEST_OUT0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(10, "AUD_DAT_MISO"), ++ "H3", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO10"), ++ MTK_FUNCTION(1, "AUD_MISO"), ++ MTK_FUNCTION(6, "TEST_IN1"), ++ MTK_FUNCTION(7, "TEST_OUT1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(11, "AUD_DAT_MOSI"), ++ "H1", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO11"), ++ MTK_FUNCTION(1, "AUD_MOSI"), ++ MTK_FUNCTION(6, "TEST_IN2"), ++ MTK_FUNCTION(7, "TEST_OUT2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(12, "COL0"), ++ "F3", "mt6397", ++ MTK_EINT_FUNCTION(2, 10), ++ MTK_FUNCTION(0, "GPIO12"), ++ MTK_FUNCTION(1, "COL0_USBDL"), ++ MTK_FUNCTION(2, "EINT10_1X"), ++ MTK_FUNCTION(3, "PWM1_3X"), ++ MTK_FUNCTION(6, "TEST_IN3"), ++ MTK_FUNCTION(7, "TEST_OUT3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(13, "COL1"), ++ "G8", "mt6397", ++ MTK_EINT_FUNCTION(2, 11), ++ MTK_FUNCTION(0, "GPIO13"), ++ MTK_FUNCTION(1, "COL1"), ++ MTK_FUNCTION(2, "EINT11_1X"), ++ MTK_FUNCTION(3, "SCL0_2X"), ++ MTK_FUNCTION(6, "TEST_IN4"), ++ MTK_FUNCTION(7, "TEST_OUT4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(14, "COL2"), ++ "H4", "mt6397", ++ MTK_EINT_FUNCTION(2, 12), ++ MTK_FUNCTION(0, "GPIO14"), ++ MTK_FUNCTION(1, "COL2"), ++ MTK_FUNCTION(2, "EINT12_1X"), ++ MTK_FUNCTION(3, "SDA0_2X"), ++ MTK_FUNCTION(6, "TEST_IN5"), ++ MTK_FUNCTION(7, "TEST_OUT5") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(15, "COL3"), ++ "G2", "mt6397", ++ MTK_EINT_FUNCTION(2, 13), ++ MTK_FUNCTION(0, "GPIO15"), ++ MTK_FUNCTION(1, "COL3"), ++ MTK_FUNCTION(2, "EINT13_1X"), ++ MTK_FUNCTION(3, "SCL1_2X"), ++ MTK_FUNCTION(6, "TEST_IN6"), ++ MTK_FUNCTION(7, "TEST_OUT6") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(16, "COL4"), ++ "F2", "mt6397", ++ MTK_EINT_FUNCTION(2, 14), ++ MTK_FUNCTION(0, "GPIO16"), ++ MTK_FUNCTION(1, "COL4"), ++ MTK_FUNCTION(2, "EINT14_1X"), ++ MTK_FUNCTION(3, "SDA1_2X"), ++ MTK_FUNCTION(6, "TEST_IN7"), ++ MTK_FUNCTION(7, "TEST_OUT7") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(17, "COL5"), ++ "G7", "mt6397", ++ MTK_EINT_FUNCTION(2, 15), ++ MTK_FUNCTION(0, "GPIO17"), ++ MTK_FUNCTION(1, "COL5"), ++ MTK_FUNCTION(2, "EINT15_1X"), ++ MTK_FUNCTION(3, "SCL2_2X"), ++ MTK_FUNCTION(6, "TEST_IN8"), ++ MTK_FUNCTION(7, "TEST_OUT8") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(18, "COL6"), ++ "J6", "mt6397", ++ MTK_EINT_FUNCTION(2, 16), ++ MTK_FUNCTION(0, "GPIO18"), ++ MTK_FUNCTION(1, "COL6"), ++ MTK_FUNCTION(2, "EINT16_1X"), ++ MTK_FUNCTION(3, "SDA2_2X"), ++ MTK_FUNCTION(4, "GPIO32K_0"), ++ MTK_FUNCTION(5, "GPIO26M_0"), ++ MTK_FUNCTION(6, "TEST_IN9"), ++ MTK_FUNCTION(7, "TEST_OUT9") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(19, "COL7"), ++ "J5", "mt6397", ++ MTK_EINT_FUNCTION(2, 17), ++ MTK_FUNCTION(0, "GPIO19"), ++ MTK_FUNCTION(1, "COL7"), ++ MTK_FUNCTION(2, "EINT17_1X"), ++ MTK_FUNCTION(3, "PWM2_3X"), ++ MTK_FUNCTION(4, "GPIO32K_1"), ++ MTK_FUNCTION(5, "GPIO26M_1"), ++ MTK_FUNCTION(6, "TEST_IN10"), ++ MTK_FUNCTION(7, "TEST_OUT10") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(20, "ROW0"), ++ "L7", "mt6397", ++ MTK_EINT_FUNCTION(2, 18), ++ MTK_FUNCTION(0, "GPIO20"), ++ MTK_FUNCTION(1, "ROW0"), ++ MTK_FUNCTION(2, "EINT18_1X"), ++ MTK_FUNCTION(3, "SCL0_3X"), ++ MTK_FUNCTION(6, "TEST_IN11"), ++ MTK_FUNCTION(7, "TEST_OUT11") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(21, "ROW1"), ++ "P1", "mt6397", ++ MTK_EINT_FUNCTION(2, 19), ++ MTK_FUNCTION(0, "GPIO21"), ++ MTK_FUNCTION(1, "ROW1"), ++ MTK_FUNCTION(2, "EINT19_1X"), ++ MTK_FUNCTION(3, "SDA0_3X"), ++ MTK_FUNCTION(4, "AUD_TSTCK"), ++ MTK_FUNCTION(6, "TEST_IN12"), ++ MTK_FUNCTION(7, "TEST_OUT12") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(22, "ROW2"), ++ "J8", "mt6397", ++ MTK_EINT_FUNCTION(2, 20), ++ MTK_FUNCTION(0, "GPIO22"), ++ MTK_FUNCTION(1, "ROW2"), ++ MTK_FUNCTION(2, "EINT20_1X"), ++ MTK_FUNCTION(3, "SCL1_3X"), ++ MTK_FUNCTION(6, "TEST_IN13"), ++ MTK_FUNCTION(7, "TEST_OUT13") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(23, "ROW3"), ++ "J7", "mt6397", ++ MTK_EINT_FUNCTION(2, 21), ++ MTK_FUNCTION(0, "GPIO23"), ++ MTK_FUNCTION(1, "ROW3"), ++ MTK_FUNCTION(2, "EINT21_1X"), ++ MTK_FUNCTION(3, "SDA1_3X"), ++ MTK_FUNCTION(6, "TEST_IN14"), ++ MTK_FUNCTION(7, "TEST_OUT14") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(24, "ROW4"), ++ "L5", "mt6397", ++ MTK_EINT_FUNCTION(2, 22), ++ MTK_FUNCTION(0, "GPIO24"), ++ MTK_FUNCTION(1, "ROW4"), ++ MTK_FUNCTION(2, "EINT22_1X"), ++ MTK_FUNCTION(3, "SCL2_3X"), ++ MTK_FUNCTION(6, "TEST_IN15"), ++ MTK_FUNCTION(7, "TEST_OUT15") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(25, "ROW5"), ++ "N6", "mt6397", ++ MTK_EINT_FUNCTION(2, 23), ++ MTK_FUNCTION(0, "GPIO25"), ++ MTK_FUNCTION(1, "ROW5"), ++ MTK_FUNCTION(2, "EINT23_1X"), ++ MTK_FUNCTION(3, "SDA2_3X"), ++ MTK_FUNCTION(6, "TEST_IN16"), ++ MTK_FUNCTION(7, "TEST_OUT16") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(26, "ROW6"), ++ "L6", "mt6397", ++ MTK_EINT_FUNCTION(2, 24), ++ MTK_FUNCTION(0, "GPIO26"), ++ MTK_FUNCTION(1, "ROW6"), ++ MTK_FUNCTION(2, "EINT24_1X"), ++ MTK_FUNCTION(3, "PWM3_3X"), ++ MTK_FUNCTION(4, "GPIO32K_2"), ++ MTK_FUNCTION(5, "GPIO26M_2"), ++ MTK_FUNCTION(6, "TEST_IN17"), ++ MTK_FUNCTION(7, "TEST_OUT17") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(27, "ROW7"), ++ "P2", "mt6397", ++ MTK_EINT_FUNCTION(2, 3), ++ MTK_FUNCTION(0, "GPIO27"), ++ MTK_FUNCTION(1, "ROW7"), ++ MTK_FUNCTION(2, "EINT3_1X"), ++ MTK_FUNCTION(3, "CBUS"), ++ MTK_FUNCTION(4, "GPIO32K_3"), ++ MTK_FUNCTION(5, "GPIO26M_3"), ++ MTK_FUNCTION(6, "TEST_IN18"), ++ MTK_FUNCTION(7, "TEST_OUT18") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(28, "PWM1(VMSEL1)"), ++ "J4", "mt6397", ++ MTK_EINT_FUNCTION(2, 4), ++ MTK_FUNCTION(0, "GPIO28"), ++ MTK_FUNCTION(1, "PWM1"), ++ MTK_FUNCTION(2, "EINT4_1X"), ++ MTK_FUNCTION(4, "GPIO32K_4"), ++ MTK_FUNCTION(5, "GPIO26M_4"), ++ MTK_FUNCTION(6, "TEST_IN19"), ++ MTK_FUNCTION(7, "TEST_OUT19") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(29, "PWM2(VMSEL2)"), ++ "N5", "mt6397", ++ MTK_EINT_FUNCTION(2, 5), ++ MTK_FUNCTION(0, "GPIO29"), ++ MTK_FUNCTION(1, "PWM2"), ++ MTK_FUNCTION(2, "EINT5_1X"), ++ MTK_FUNCTION(4, "GPIO32K_5"), ++ MTK_FUNCTION(5, "GPIO26M_5"), ++ MTK_FUNCTION(6, "TEST_IN20"), ++ MTK_FUNCTION(7, "TEST_OUT20") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(30, "PWM3(PWM)"), ++ "R3", "mt6397", ++ MTK_EINT_FUNCTION(2, 6), ++ MTK_FUNCTION(0, "GPIO30"), ++ MTK_FUNCTION(1, "PWM3"), ++ MTK_FUNCTION(2, "EINT6_1X"), ++ MTK_FUNCTION(3, "COL0"), ++ MTK_FUNCTION(4, "GPIO32K_6"), ++ MTK_FUNCTION(5, "GPIO26M_6"), ++ MTK_FUNCTION(6, "TEST_IN21"), ++ MTK_FUNCTION(7, "TEST_OUT21") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(31, "SCL0"), ++ "N1", "mt6397", ++ MTK_EINT_FUNCTION(2, 7), ++ MTK_FUNCTION(0, "GPIO31"), ++ MTK_FUNCTION(1, "SCL0"), ++ MTK_FUNCTION(2, "EINT7_1X"), ++ MTK_FUNCTION(3, "PWM1_2X"), ++ MTK_FUNCTION(6, "TEST_IN22"), ++ MTK_FUNCTION(7, "TEST_OUT22") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(32, "SDA0"), ++ "N3", "mt6397", ++ MTK_EINT_FUNCTION(2, 8), ++ MTK_FUNCTION(0, "GPIO32"), ++ MTK_FUNCTION(1, "SDA0"), ++ MTK_FUNCTION(2, "EINT8_1X"), ++ MTK_FUNCTION(6, "TEST_IN23"), ++ MTK_FUNCTION(7, "TEST_OUT23") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(33, "SCL1"), ++ "T1", "mt6397", ++ MTK_EINT_FUNCTION(2, 9), ++ MTK_FUNCTION(0, "GPIO33"), ++ MTK_FUNCTION(1, "SCL1"), ++ MTK_FUNCTION(2, "EINT9_1X"), ++ MTK_FUNCTION(3, "PWM2_2X"), ++ MTK_FUNCTION(6, "TEST_IN24"), ++ MTK_FUNCTION(7, "TEST_OUT24") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(34, "SDA1"), ++ "T2", "mt6397", ++ MTK_EINT_FUNCTION(2, 0), ++ MTK_FUNCTION(0, "GPIO34"), ++ MTK_FUNCTION(1, "SDA1"), ++ MTK_FUNCTION(2, "EINT0_1X"), ++ MTK_FUNCTION(6, "TEST_IN25"), ++ MTK_FUNCTION(7, "TEST_OUT25") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(35, "SCL2"), ++ "T3", "mt6397", ++ MTK_EINT_FUNCTION(2, 1), ++ MTK_FUNCTION(0, "GPIO35"), ++ MTK_FUNCTION(1, "SCL2"), ++ MTK_FUNCTION(2, "EINT1_1X"), ++ MTK_FUNCTION(3, "PWM3_2X"), ++ MTK_FUNCTION(6, "TEST_IN26"), ++ MTK_FUNCTION(7, "TEST_OUT26") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(36, "SDA2"), ++ "U2", "mt6397", ++ MTK_EINT_FUNCTION(2, 2), ++ MTK_FUNCTION(0, "GPIO36"), ++ MTK_FUNCTION(1, "SDA2"), ++ MTK_FUNCTION(2, "EINT2_1X"), ++ MTK_FUNCTION(6, "TEST_IN27"), ++ MTK_FUNCTION(7, "TEST_OUT27") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(37, "HDMISD"), ++ "H6", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO37"), ++ MTK_FUNCTION(1, "HDMISD"), ++ MTK_FUNCTION(6, "TEST_IN28"), ++ MTK_FUNCTION(7, "TEST_OUT28") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(38, "HDMISCK"), ++ "H5", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO38"), ++ MTK_FUNCTION(1, "HDMISCK"), ++ MTK_FUNCTION(6, "TEST_IN29"), ++ MTK_FUNCTION(7, "TEST_OUT29") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(39, "HTPLG"), ++ "H7", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO39"), ++ MTK_FUNCTION(1, "HTPLG"), ++ MTK_FUNCTION(6, "TEST_IN30"), ++ MTK_FUNCTION(7, "TEST_OUT30") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(40, "CEC"), ++ "J9", "mt6397", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO40"), ++ MTK_FUNCTION(1, "CEC"), ++ MTK_FUNCTION(6, "TEST_IN31"), ++ MTK_FUNCTION(7, "TEST_OUT31") ++ ), ++}; ++ ++#endif /* __PINCTRL_MTK_MT6397_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0054-pinctrl-mediatek-add-pinctrl-GPIO-EINT-driver-for-mt.patch b/target/linux/mediatek/patches/0054-pinctrl-mediatek-add-pinctrl-GPIO-EINT-driver-for-mt.patch new file mode 100644 index 0000000..763037c --- /dev/null +++ b/target/linux/mediatek/patches/0054-pinctrl-mediatek-add-pinctrl-GPIO-EINT-driver-for-mt.patch @@ -0,0 +1,1740 @@ +From 0fabcb34ad6506e9d8dadf373f4ebfe1b5129765 Mon Sep 17 00:00:00 2001 +From: Yingjoe Chen +Date: Mon, 18 May 2015 23:11:18 -0700 +Subject: [PATCH 54/76] pinctrl: mediatek: add pinctrl/GPIO/EINT driver for + mt8127 + +MT8127 pinctrl/eint are similar to mt8135 and mt8173, add +support for mt8127 using mediatek common pinctrl driver. + +Signed-off-by: Yingjoe Chen +Signed-off-by: Hongzhou Yang +--- + drivers/pinctrl/mediatek/Kconfig | 6 + + drivers/pinctrl/mediatek/Makefile | 1 + + drivers/pinctrl/mediatek/pinctrl-mt8127.c | 359 +++++++ + drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h | 1318 +++++++++++++++++++++++++ + 4 files changed, 1684 insertions(+) + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8127.c + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h + +diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig +index ddae479..0bc84fb 100644 +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -15,6 +15,12 @@ config PINCTRL_MT8135 + default MACH_MT8135 + select PINCTRL_MTK_COMMON + ++config PINCTRL_MT8127 ++ bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127 ++ depends on OF ++ default MACH_MT8127 ++ select PINCTRL_MTK_COMMON ++ + # For ARMv8 SoCs + config PINCTRL_MT8173 + bool "Mediatek MT8173 pin control" +diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile +index ad0180c..eb923d6 100644 +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -3,5 +3,6 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o + + # SoC Drivers + obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o ++obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o + obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c +new file mode 100644 +index 0000000..6a26cfa +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c +@@ -0,0 +1,359 @@ ++/* ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: Hongzhou.Yang ++ * Yingjoe Chen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pinctrl-mtk-common.h" ++#include "pinctrl-mtk-mt8127.h" ++ ++static const struct mtk_drv_group_desc mt8127_drv_grp[] = { ++ /* 0E4E8SR 4/8/12/16 */ ++ MTK_DRV_GRP(4, 16, 1, 2, 4), ++ /* 0E2E4SR 2/4/6/8 */ ++ MTK_DRV_GRP(2, 8, 1, 2, 2), ++ /* E8E4E2 2/4/6/8/10/12/14/16 */ ++ MTK_DRV_GRP(2, 16, 0, 2, 2) ++}; ++ ++static const struct mtk_pin_drv_grp mt8127_pin_drv[] = { ++ MTK_PIN_DRV_GRP(0, 0xb00, 0, 1), ++ MTK_PIN_DRV_GRP(1, 0xb00, 0, 1), ++ MTK_PIN_DRV_GRP(2, 0xb00, 0, 1), ++ MTK_PIN_DRV_GRP(3, 0xb00, 0, 1), ++ MTK_PIN_DRV_GRP(4, 0xb00, 0, 1), ++ MTK_PIN_DRV_GRP(5, 0xb00, 0, 1), ++ MTK_PIN_DRV_GRP(6, 0xb00, 0, 1), ++ MTK_PIN_DRV_GRP(7, 0xb00, 12, 1), ++ MTK_PIN_DRV_GRP(8, 0xb00, 12, 1), ++ MTK_PIN_DRV_GRP(9, 0xb00, 12, 1), ++ MTK_PIN_DRV_GRP(10, 0xb00, 8, 1), ++ MTK_PIN_DRV_GRP(11, 0xb00, 8, 1), ++ MTK_PIN_DRV_GRP(12, 0xb00, 8, 1), ++ MTK_PIN_DRV_GRP(13, 0xb00, 8, 1), ++ MTK_PIN_DRV_GRP(14, 0xb10, 4, 0), ++ MTK_PIN_DRV_GRP(15, 0xb10, 4, 0), ++ MTK_PIN_DRV_GRP(16, 0xb10, 4, 0), ++ MTK_PIN_DRV_GRP(17, 0xb10, 4, 0), ++ MTK_PIN_DRV_GRP(18, 0xb10, 8, 0), ++ MTK_PIN_DRV_GRP(19, 0xb10, 8, 0), ++ MTK_PIN_DRV_GRP(20, 0xb10, 8, 0), ++ MTK_PIN_DRV_GRP(21, 0xb10, 8, 0), ++ MTK_PIN_DRV_GRP(22, 0xb20, 0, 0), ++ MTK_PIN_DRV_GRP(23, 0xb20, 0, 0), ++ MTK_PIN_DRV_GRP(24, 0xb20, 0, 0), ++ MTK_PIN_DRV_GRP(25, 0xb20, 0, 0), ++ MTK_PIN_DRV_GRP(26, 0xb20, 0, 0), ++ MTK_PIN_DRV_GRP(27, 0xb20, 4, 0), ++ MTK_PIN_DRV_GRP(28, 0xb20, 4, 0), ++ MTK_PIN_DRV_GRP(29, 0xb20, 4, 0), ++ MTK_PIN_DRV_GRP(30, 0xb20, 4, 0), ++ MTK_PIN_DRV_GRP(31, 0xb20, 4, 0), ++ MTK_PIN_DRV_GRP(32, 0xb20, 4, 0), ++ MTK_PIN_DRV_GRP(33, 0xb30, 4, 1), ++ MTK_PIN_DRV_GRP(34, 0xb30, 8, 1), ++ MTK_PIN_DRV_GRP(35, 0xb30, 8, 1), ++ MTK_PIN_DRV_GRP(36, 0xb30, 8, 1), ++ MTK_PIN_DRV_GRP(37, 0xb30, 8, 1), ++ MTK_PIN_DRV_GRP(38, 0xb30, 8, 1), ++ MTK_PIN_DRV_GRP(39, 0xb30, 12, 1), ++ MTK_PIN_DRV_GRP(40, 0xb30, 12, 1), ++ MTK_PIN_DRV_GRP(41, 0xb30, 12, 1), ++ MTK_PIN_DRV_GRP(42, 0xb30, 12, 1), ++ MTK_PIN_DRV_GRP(43, 0xb40, 12, 0), ++ MTK_PIN_DRV_GRP(44, 0xb40, 12, 0), ++ MTK_PIN_DRV_GRP(45, 0xb40, 12, 0), ++ MTK_PIN_DRV_GRP(46, 0xb50, 0, 2), ++ MTK_PIN_DRV_GRP(47, 0xb50, 0, 2), ++ MTK_PIN_DRV_GRP(48, 0xb50, 0, 2), ++ MTK_PIN_DRV_GRP(49, 0xb50, 0, 2), ++ MTK_PIN_DRV_GRP(50, 0xb70, 0, 1), ++ MTK_PIN_DRV_GRP(51, 0xb70, 0, 1), ++ MTK_PIN_DRV_GRP(52, 0xb70, 0, 1), ++ MTK_PIN_DRV_GRP(53, 0xb50, 12, 1), ++ MTK_PIN_DRV_GRP(54, 0xb50, 12, 1), ++ MTK_PIN_DRV_GRP(55, 0xb50, 12, 1), ++ MTK_PIN_DRV_GRP(56, 0xb50, 12, 1), ++ MTK_PIN_DRV_GRP(59, 0xb40, 4, 1), ++ MTK_PIN_DRV_GRP(60, 0xb40, 0, 1), ++ MTK_PIN_DRV_GRP(61, 0xb40, 0, 1), ++ MTK_PIN_DRV_GRP(62, 0xb40, 0, 1), ++ MTK_PIN_DRV_GRP(63, 0xb40, 4, 1), ++ MTK_PIN_DRV_GRP(64, 0xb40, 4, 1), ++ MTK_PIN_DRV_GRP(65, 0xb40, 4, 1), ++ MTK_PIN_DRV_GRP(66, 0xb40, 8, 1), ++ MTK_PIN_DRV_GRP(67, 0xb40, 8, 1), ++ MTK_PIN_DRV_GRP(68, 0xb40, 8, 1), ++ MTK_PIN_DRV_GRP(69, 0xb40, 8, 1), ++ MTK_PIN_DRV_GRP(70, 0xb40, 8, 1), ++ MTK_PIN_DRV_GRP(71, 0xb40, 8, 1), ++ MTK_PIN_DRV_GRP(72, 0xb50, 4, 1), ++ MTK_PIN_DRV_GRP(73, 0xb50, 4, 1), ++ MTK_PIN_DRV_GRP(74, 0xb50, 4, 1), ++ MTK_PIN_DRV_GRP(79, 0xb50, 8, 1), ++ MTK_PIN_DRV_GRP(80, 0xb50, 8, 1), ++ MTK_PIN_DRV_GRP(81, 0xb50, 8, 1), ++ MTK_PIN_DRV_GRP(82, 0xb50, 8, 1), ++ MTK_PIN_DRV_GRP(83, 0xb50, 8, 1), ++ MTK_PIN_DRV_GRP(84, 0xb50, 8, 1), ++ MTK_PIN_DRV_GRP(85, 0xce0, 0, 2), ++ MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2), ++ MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2), ++ MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2), ++ MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2), ++ MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2), ++ MTK_PIN_DRV_GRP(117, 0xb60, 12, 1), ++ MTK_PIN_DRV_GRP(118, 0xb60, 12, 1), ++ MTK_PIN_DRV_GRP(119, 0xb60, 12, 1), ++ MTK_PIN_DRV_GRP(120, 0xb60, 12, 1), ++ MTK_PIN_DRV_GRP(121, 0xc80, 0, 2), ++ MTK_PIN_DRV_GRP(122, 0xc70, 0, 2), ++ MTK_PIN_DRV_GRP(123, 0xc90, 0, 2), ++ MTK_PIN_DRV_GRP(124, 0xc90, 0, 2), ++ MTK_PIN_DRV_GRP(125, 0xc90, 0, 2), ++ MTK_PIN_DRV_GRP(126, 0xc90, 0, 2), ++ MTK_PIN_DRV_GRP(127, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(128, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(129, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(130, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(131, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(132, 0xc10, 0, 2), ++ MTK_PIN_DRV_GRP(133, 0xc00, 0, 2), ++ MTK_PIN_DRV_GRP(134, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(135, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(136, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(137, 0xc20, 0, 2), ++ MTK_PIN_DRV_GRP(142, 0xb50, 0, 2), ++}; ++ ++static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = { ++ MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1), /* KPROW0 */ ++ MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5), /* KPROW1 */ ++ MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9), /* KPROW2 */ ++ MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1), /* KPCOL0 */ ++ MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5), /* KPCOL1 */ ++ MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9), /* KPCOL2 */ ++ MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1), /* EINT14 */ ++ MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5), /* EINT15 */ ++ MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9), /* EINT16 */ ++ MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13), /* EINT17 */ ++ MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9), /* MSDC2_CMD */ ++ MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9), /* MSDC2_CLK */ ++ MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1), /* MSDC2_DAT0 */ ++ MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5), /* MSDC2_DAT1 */ ++ MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9), /* MSDC2_DAT2 */ ++ MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13), /* MSDC2_DAT3 */ ++ MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */ ++ MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */ ++ MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1), /* MSDC1_DAT0 */ ++ MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5), /* MSDC1_DAT1 */ ++ MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */ ++ MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13), /* MSDC1_DAT3 */ ++ MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13), /* MSDC0_DAT7 */ ++ MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */ ++ MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5), /* MSDC0_DAT5 */ ++ MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1), /* MSDC0_DAT4 */ ++ MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1), /* MSDC0_RSTB */ ++ MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */ ++ MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */ ++ MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13), /* MSDC0_DAT3 */ ++ MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */ ++ MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5), /* MSDC0_DAT1 */ ++ MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1), /* MSDC0_DAT0 */ ++ MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */ ++}; ++ ++static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin, ++ unsigned char align, bool isup, unsigned int r1r0) ++{ ++ return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd, ++ ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0); ++} ++ ++static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = { ++ MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0), ++ MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1), ++ MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2), ++ MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), ++ MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11), ++ MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10), ++ MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11), ++ MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12), ++ MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13), ++ MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10), ++ MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14), ++ MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0), ++ MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2), ++ MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3), ++ MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4), ++ MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15), ++ MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1), ++ MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5), ++ MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6), ++ MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7), ++ MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4), ++ MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4), ++ MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4), ++ MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4), ++ MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4), ++ MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4), ++ MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4), ++ MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9), ++ MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13), ++}; ++ ++static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = { ++ MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0), ++ MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1), ++ MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2), ++ MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3), ++ MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11), ++ MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10), ++ MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11), ++ MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12), ++ MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13), ++ MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10), ++ MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14), ++ MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0), ++ MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2), ++ MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3), ++ MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4), ++ MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15), ++ MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1), ++ MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5), ++ MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6), ++ MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11), ++ MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11), ++ MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3), ++ MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7), ++ MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11), ++ MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15), ++ MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7), ++ MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11), ++ MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11), ++ MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3), ++ MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7), ++ MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11), ++ MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15), ++ MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15), ++ MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11), ++ MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7), ++ MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3), ++ MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3), ++ MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11), ++ MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11), ++ MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15), ++ MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11), ++ MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7), ++ MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3), ++ MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9), ++ MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13), ++}; ++ ++static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin, ++ unsigned char align, int value, enum pin_config_param arg) ++{ ++ if (arg == PIN_CONFIG_INPUT_ENABLE) ++ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set, ++ ARRAY_SIZE(mt8127_ies_set), pin, align, value); ++ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) ++ return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set, ++ ARRAY_SIZE(mt8127_smt_set), pin, align, value); ++ return -EINVAL; ++} ++ ++ ++static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { ++ .pins = mtk_pins_mt8127, ++ .npins = ARRAY_SIZE(mtk_pins_mt8127), ++ .grp_desc = mt8127_drv_grp, ++ .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp), ++ .pin_drv_grp = mt8127_pin_drv, ++ .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv), ++ .spec_pull_set = mt8127_spec_pull_set, ++ .spec_ies_smt_set = mt8127_ies_smt_set, ++ .dir_offset = 0x0000, ++ .pullen_offset = 0x0100, ++ .pullsel_offset = 0x0200, ++ .dout_offset = 0x0400, ++ .din_offset = 0x0500, ++ .pinmux_offset = 0x0600, ++ .type1_start = 143, ++ .type1_end = 143, ++ .port_shf = 4, ++ .port_mask = 0xf, ++ .port_align = 4, ++ .eint_offsets = { ++ .name = "mt8127_eint", ++ .stat = 0x000, ++ .ack = 0x040, ++ .mask = 0x080, ++ .mask_set = 0x0c0, ++ .mask_clr = 0x100, ++ .sens = 0x140, ++ .sens_set = 0x180, ++ .sens_clr = 0x1c0, ++ .soft = 0x200, ++ .soft_set = 0x240, ++ .soft_clr = 0x280, ++ .pol = 0x300, ++ .pol_set = 0x340, ++ .pol_clr = 0x380, ++ .dom_en = 0x400, ++ .dbnc_ctrl = 0x500, ++ .dbnc_set = 0x600, ++ .dbnc_clr = 0x700, ++ .port_mask = 7, ++ .ports = 6, ++ }, ++ .ap_num = 143, ++ .db_cnt = 16, ++}; ++ ++static int mt8127_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL); ++} ++ ++static const struct of_device_id mt8127_pctrl_match[] = { ++ { .compatible = "mediatek,mt8127-pinctrl", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, mt8127_pctrl_match); ++ ++static struct platform_driver mtk_pinctrl_driver = { ++ .probe = mt8127_pinctrl_probe, ++ .driver = { ++ .name = "mediatek-mt8127-pinctrl", ++ .owner = THIS_MODULE, ++ .of_match_table = mt8127_pctrl_match, ++ }, ++}; ++ ++static int __init mtk_pinctrl_init(void) ++{ ++ return platform_driver_register(&mtk_pinctrl_driver); ++} ++ ++module_init(mtk_pinctrl_init); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver"); ++MODULE_AUTHOR("Yingjoe Chen "); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h +new file mode 100644 +index 0000000..212559c +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h +@@ -0,0 +1,1318 @@ ++#ifndef __PINCTRL_MTK_MT8127_H ++#define __PINCTRL_MTK_MT8127_H ++ ++#include ++#include "pinctrl-mtk-common.h" ++ ++static const struct mtk_desc_pin mtk_pins_mt8127[] = { ++ MTK_PIN( ++ PINCTRL_PIN(0, "PWRAP_SPI0_MI"), ++ "P22", "mt8127", ++ MTK_EINT_FUNCTION(0, 22), ++ MTK_FUNCTION(0, "GPIO0"), ++ MTK_FUNCTION(1, "PWRAP_SPIDO"), ++ MTK_FUNCTION(2, "PWRAP_SPIDI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(1, "PWRAP_SPI0_MO"), ++ "M22", "mt8127", ++ MTK_EINT_FUNCTION(0, 23), ++ MTK_FUNCTION(0, "GPIO1"), ++ MTK_FUNCTION(1, "PWRAP_SPIDI"), ++ MTK_FUNCTION(2, "PWRAP_SPIDO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(2, "PWRAP_INT"), ++ "L23", "mt8127", ++ MTK_EINT_FUNCTION(0, 24), ++ MTK_FUNCTION(0, "GPIO2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(3, "PWRAP_SPI0_CK"), ++ "N23", "mt8127", ++ MTK_EINT_FUNCTION(0, 25), ++ MTK_FUNCTION(0, "GPIO3"), ++ MTK_FUNCTION(1, "PWRAP_SPICK_I") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(4, "PWRAP_SPI0_CSN"), ++ "N22", "mt8127", ++ MTK_EINT_FUNCTION(0, 26), ++ MTK_FUNCTION(0, "GPIO4"), ++ MTK_FUNCTION(1, "PWRAP_SPICS_B_I") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(5, "PWRAP_SPI0_CK2"), ++ "L19", "mt8127", ++ MTK_EINT_FUNCTION(0, 27), ++ MTK_FUNCTION(0, "GPIO5"), ++ MTK_FUNCTION(1, "PWRAP_SPICK2_I"), ++ MTK_FUNCTION(2, "ANT_SEL1"), ++ MTK_FUNCTION(3, "VDEC_TEST_CK"), ++ MTK_FUNCTION(7, "DBG_MON_B[0]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"), ++ "M23", "mt8127", ++ MTK_EINT_FUNCTION(0, 28), ++ MTK_FUNCTION(0, "GPIO6"), ++ MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"), ++ MTK_FUNCTION(2, "ANT_SEL0"), ++ MTK_FUNCTION(3, "MM_TEST_CK"), ++ MTK_FUNCTION(7, "DBG_MON_B[1]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(7, "AUD_CLK_MOSI"), ++ "K23", "mt8127", ++ MTK_EINT_FUNCTION(0, 29), ++ MTK_FUNCTION(0, "GPIO7"), ++ MTK_FUNCTION(1, "AUD_CLK"), ++ MTK_FUNCTION(2, "ADC_CK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(8, "AUD_DAT_MISO"), ++ "K24", "mt8127", ++ MTK_EINT_FUNCTION(0, 30), ++ MTK_FUNCTION(0, "GPIO8"), ++ MTK_FUNCTION(1, "AUD_MISO"), ++ MTK_FUNCTION(2, "ADC_DAT_IN"), ++ MTK_FUNCTION(3, "AUD_MOSI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(9, "AUD_DAT_MOSI"), ++ "K22", "mt8127", ++ MTK_EINT_FUNCTION(0, 31), ++ MTK_FUNCTION(0, "GPIO9"), ++ MTK_FUNCTION(1, "AUD_MOSI"), ++ MTK_FUNCTION(2, "ADC_WS"), ++ MTK_FUNCTION(3, "AUD_MISO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(10, "RTC32K_CK"), ++ "R21", "mt8127", ++ MTK_EINT_FUNCTION(0, 32), ++ MTK_FUNCTION(0, "GPIO10"), ++ MTK_FUNCTION(1, "RTC32K_CK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(11, "WATCHDOG"), ++ "P24", "mt8127", ++ MTK_EINT_FUNCTION(0, 33), ++ MTK_FUNCTION(0, "GPIO11"), ++ MTK_FUNCTION(1, "WATCHDOG") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(12, "SRCLKENA"), ++ "R22", "mt8127", ++ MTK_EINT_FUNCTION(0, 34), ++ MTK_FUNCTION(0, "GPIO12"), ++ MTK_FUNCTION(1, "SRCLKENA") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(13, "SRCLKENAI"), ++ "P23", "mt8127", ++ MTK_EINT_FUNCTION(0, 35), ++ MTK_FUNCTION(0, "GPIO13"), ++ MTK_FUNCTION(1, "SRCLKENAI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(14, "URXD2"), ++ "U19", "mt8127", ++ MTK_EINT_FUNCTION(0, 36), ++ MTK_FUNCTION(0, "GPIO14"), ++ MTK_FUNCTION(1, "URXD2"), ++ MTK_FUNCTION(2, "DPI_D5"), ++ MTK_FUNCTION(3, "UTXD2"), ++ MTK_FUNCTION(5, "SRCCLKENAI2"), ++ MTK_FUNCTION(6, "KROW4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(15, "UTXD2"), ++ "U20", "mt8127", ++ MTK_EINT_FUNCTION(0, 37), ++ MTK_FUNCTION(0, "GPIO15"), ++ MTK_FUNCTION(1, "UTXD2"), ++ MTK_FUNCTION(2, "DPI_HSYNC"), ++ MTK_FUNCTION(3, "URXD2"), ++ MTK_FUNCTION(6, "KROW5") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(16, "URXD3"), ++ "U18", "mt8127", ++ MTK_EINT_FUNCTION(0, 38), ++ MTK_FUNCTION(0, "GPIO16"), ++ MTK_FUNCTION(1, "URXD3"), ++ MTK_FUNCTION(2, "DPI_DE"), ++ MTK_FUNCTION(3, "UTXD3"), ++ MTK_FUNCTION(4, "UCTS2"), ++ MTK_FUNCTION(5, "PWM3"), ++ MTK_FUNCTION(6, "KROW6") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(17, "UTXD3"), ++ "R18", "mt8127", ++ MTK_EINT_FUNCTION(0, 39), ++ MTK_FUNCTION(0, "GPIO17"), ++ MTK_FUNCTION(1, "UTXD3"), ++ MTK_FUNCTION(2, "DPI_VSYNC"), ++ MTK_FUNCTION(3, "URXD3"), ++ MTK_FUNCTION(4, "URTS2"), ++ MTK_FUNCTION(5, "PWM4"), ++ MTK_FUNCTION(6, "KROW7") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(18, "PCM_CLK"), ++ "U22", "mt8127", ++ MTK_EINT_FUNCTION(0, 40), ++ MTK_FUNCTION(0, "GPIO18"), ++ MTK_FUNCTION(1, "PCM_CLK0"), ++ MTK_FUNCTION(2, "DPI_D4"), ++ MTK_FUNCTION(3, "I2SIN1_BCK0"), ++ MTK_FUNCTION(4, "I2SOUT_BCK"), ++ MTK_FUNCTION(5, "CONN_DSP_JCK"), ++ MTK_FUNCTION(6, "IR"), ++ MTK_FUNCTION(7, "DBG_MON_A[0]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(19, "PCM_SYNC"), ++ "U23", "mt8127", ++ MTK_EINT_FUNCTION(0, 41), ++ MTK_FUNCTION(0, "GPIO19"), ++ MTK_FUNCTION(1, "PCM_SYNC"), ++ MTK_FUNCTION(2, "DPI_D3"), ++ MTK_FUNCTION(3, "I2SIN1_LRCK"), ++ MTK_FUNCTION(4, "I2SOUT_LRCK"), ++ MTK_FUNCTION(5, "CONN_DSP_JINTP"), ++ MTK_FUNCTION(6, "EXT_COL"), ++ MTK_FUNCTION(7, "DBG_MON_A[1]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(20, "PCM_RX"), ++ "V22", "mt8127", ++ MTK_EINT_FUNCTION(0, 42), ++ MTK_FUNCTION(0, "GPIO20"), ++ MTK_FUNCTION(1, "PCM_RX"), ++ MTK_FUNCTION(2, "DPI_D1"), ++ MTK_FUNCTION(3, "I2SIN1_DATA_IN"), ++ MTK_FUNCTION(4, "PCM_TX"), ++ MTK_FUNCTION(5, "CONN_DSP_JDI"), ++ MTK_FUNCTION(6, "EXT_MDIO"), ++ MTK_FUNCTION(7, "DBG_MON_A[2]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(21, "PCM_TX"), ++ "U21", "mt8127", ++ MTK_EINT_FUNCTION(0, 43), ++ MTK_FUNCTION(0, "GPIO21"), ++ MTK_FUNCTION(1, "PCM_TX"), ++ MTK_FUNCTION(2, "DPI_D2"), ++ MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), ++ MTK_FUNCTION(4, "PCM_RX"), ++ MTK_FUNCTION(5, "CONN_DSP_JMS"), ++ MTK_FUNCTION(6, "EXT_MDC"), ++ MTK_FUNCTION(7, "DBG_MON_A[3]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(22, "EINT0"), ++ "AB19", "mt8127", ++ MTK_EINT_FUNCTION(0, 0), ++ MTK_FUNCTION(0, "GPIO22"), ++ MTK_FUNCTION(1, "PWM1"), ++ MTK_FUNCTION(2, "DPI_CK"), ++ MTK_FUNCTION(4, "EXT_TXD0"), ++ MTK_FUNCTION(5, "CONN_DSP_JDO"), ++ MTK_FUNCTION(7, "DBG_MON_A[4]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(23, "EINT1"), ++ "AA21", "mt8127", ++ MTK_EINT_FUNCTION(0, 1), ++ MTK_FUNCTION(0, "GPIO23"), ++ MTK_FUNCTION(1, "PWM2"), ++ MTK_FUNCTION(2, "DPI_D12"), ++ MTK_FUNCTION(4, "EXT_TXD1"), ++ MTK_FUNCTION(5, "CONN_MCU_TDO"), ++ MTK_FUNCTION(7, "DBG_MON_A[5]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(24, "EINT2"), ++ "AA19", "mt8127", ++ MTK_EINT_FUNCTION(0, 2), ++ MTK_FUNCTION(0, "GPIO24"), ++ MTK_FUNCTION(1, "CLKM0"), ++ MTK_FUNCTION(2, "DPI_D13"), ++ MTK_FUNCTION(4, "EXT_TXD2"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(6, "KCOL4"), ++ MTK_FUNCTION(7, "DBG_MON_A[6]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(25, "EINT3"), ++ "Y19", "mt8127", ++ MTK_EINT_FUNCTION(0, 3), ++ MTK_FUNCTION(0, "GPIO25"), ++ MTK_FUNCTION(1, "CLKM1"), ++ MTK_FUNCTION(2, "DPI_D14"), ++ MTK_FUNCTION(3, "SPI_MI"), ++ MTK_FUNCTION(4, "EXT_TXD3"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(6, "KCOL5"), ++ MTK_FUNCTION(7, "DBG_MON_A[7]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(26, "EINT4"), ++ "V21", "mt8127", ++ MTK_EINT_FUNCTION(0, 4), ++ MTK_FUNCTION(0, "GPIO26"), ++ MTK_FUNCTION(1, "CLKM2"), ++ MTK_FUNCTION(2, "DPI_D15"), ++ MTK_FUNCTION(3, "SPI_MO"), ++ MTK_FUNCTION(4, "EXT_TXC"), ++ MTK_FUNCTION(5, "CONN_MCU_TCK0"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"), ++ MTK_FUNCTION(7, "DBG_MON_A[8]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(27, "EINT5"), ++ "AB22", "mt8127", ++ MTK_EINT_FUNCTION(0, 5), ++ MTK_FUNCTION(0, "GPIO27"), ++ MTK_FUNCTION(1, "UCTS2"), ++ MTK_FUNCTION(2, "DPI_D16"), ++ MTK_FUNCTION(3, "SPI_CS"), ++ MTK_FUNCTION(4, "EXT_RXER"), ++ MTK_FUNCTION(5, "CONN_MCU_TDI"), ++ MTK_FUNCTION(6, "KCOL6"), ++ MTK_FUNCTION(7, "DBG_MON_A[9]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(28, "EINT6"), ++ "AA23", "mt8127", ++ MTK_EINT_FUNCTION(0, 6), ++ MTK_FUNCTION(0, "GPIO28"), ++ MTK_FUNCTION(1, "URTS2"), ++ MTK_FUNCTION(2, "DPI_D17"), ++ MTK_FUNCTION(3, "SPI_CK"), ++ MTK_FUNCTION(4, "EXT_RXC"), ++ MTK_FUNCTION(5, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(6, "KCOL7"), ++ MTK_FUNCTION(7, "DBG_MON_A[10]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(29, "EINT7"), ++ "Y23", "mt8127", ++ MTK_EINT_FUNCTION(0, 7), ++ MTK_FUNCTION(0, "GPIO29"), ++ MTK_FUNCTION(1, "UCTS3"), ++ MTK_FUNCTION(2, "DPI_D6"), ++ MTK_FUNCTION(3, "SDA1"), ++ MTK_FUNCTION(4, "EXT_RXDV"), ++ MTK_FUNCTION(5, "CONN_MCU_TMS"), ++ MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"), ++ MTK_FUNCTION(7, "DBG_MON_A[11]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(30, "EINT8"), ++ "Y24", "mt8127", ++ MTK_EINT_FUNCTION(0, 8), ++ MTK_FUNCTION(0, "GPIO30"), ++ MTK_FUNCTION(1, "URTS3"), ++ MTK_FUNCTION(2, "CLKM3"), ++ MTK_FUNCTION(3, "SCL1"), ++ MTK_FUNCTION(4, "EXT_RXD0"), ++ MTK_FUNCTION(5, "ANT_SEL0"), ++ MTK_FUNCTION(6, "DPI_D7"), ++ MTK_FUNCTION(7, "DBG_MON_B[2]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(31, "EINT9"), ++ "W23", "mt8127", ++ MTK_EINT_FUNCTION(0, 9), ++ MTK_FUNCTION(0, "GPIO31"), ++ MTK_FUNCTION(1, "CLKM4"), ++ MTK_FUNCTION(2, "SDA2"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "EXT_RXD1"), ++ MTK_FUNCTION(5, "ANT_SEL1"), ++ MTK_FUNCTION(6, "DPI_D8"), ++ MTK_FUNCTION(7, "DBG_MON_B[3]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(32, "EINT10"), ++ "W24", "mt8127", ++ MTK_EINT_FUNCTION(0, 10), ++ MTK_FUNCTION(0, "GPIO32"), ++ MTK_FUNCTION(1, "CLKM5"), ++ MTK_FUNCTION(2, "SCL2"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "EXT_RXD2"), ++ MTK_FUNCTION(5, "ANT_SEL2"), ++ MTK_FUNCTION(6, "DPI_D9"), ++ MTK_FUNCTION(7, "DBG_MON_B[4]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(33, "KPROW0"), ++ "AB24", "mt8127", ++ MTK_EINT_FUNCTION(0, 44), ++ MTK_FUNCTION(0, "GPIO33"), ++ MTK_FUNCTION(1, "KROW0"), ++ MTK_FUNCTION(4, "IMG_TEST_CK"), ++ MTK_FUNCTION(7, "DBG_MON_A[12]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(34, "KPROW1"), ++ "AC24", "mt8127", ++ MTK_EINT_FUNCTION(0, 45), ++ MTK_FUNCTION(0, "GPIO34"), ++ MTK_FUNCTION(1, "KROW1"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "MFG_TEST_CK"), ++ MTK_FUNCTION(7, "DBG_MON_B[5]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(35, "KPROW2"), ++ "AD24", "mt8127", ++ MTK_EINT_FUNCTION(0, 46), ++ MTK_FUNCTION(0, "GPIO35"), ++ MTK_FUNCTION(1, "KROW2"), ++ MTK_FUNCTION(2, "DRV_VBUS"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(4, "CONN_TEST_CK"), ++ MTK_FUNCTION(7, "DBG_MON_B[6]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(36, "KPCOL0"), ++ "AB23", "mt8127", ++ MTK_EINT_FUNCTION(0, 47), ++ MTK_FUNCTION(0, "GPIO36"), ++ MTK_FUNCTION(1, "KCOL0"), ++ MTK_FUNCTION(7, "DBG_MON_A[13]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(37, "KPCOL1"), ++ "AC22", "mt8127", ++ MTK_EINT_FUNCTION(0, 48), ++ MTK_FUNCTION(0, "GPIO37"), ++ MTK_FUNCTION(1, "KCOL1"), ++ MTK_FUNCTION(7, "DBG_MON_B[7]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(38, "KPCOL2"), ++ "AC23", "mt8127", ++ MTK_EINT_FUNCTION(0, 49), ++ MTK_FUNCTION(0, "GPIO38"), ++ MTK_FUNCTION(1, "KCOL2"), ++ MTK_FUNCTION(2, "IDDIG"), ++ MTK_FUNCTION(3, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(7, "DBG_MON_B[8]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(39, "JTMS"), ++ "V18", "mt8127", ++ MTK_EINT_FUNCTION(0, 50), ++ MTK_FUNCTION(0, "GPIO39"), ++ MTK_FUNCTION(1, "JTMS"), ++ MTK_FUNCTION(2, "CONN_MCU_TMS"), ++ MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(40, "JTCK"), ++ "AA18", "mt8127", ++ MTK_EINT_FUNCTION(0, 51), ++ MTK_FUNCTION(0, "GPIO40"), ++ MTK_FUNCTION(1, "JTCK"), ++ MTK_FUNCTION(2, "CONN_MCU_TCK1"), ++ MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(41, "JTDI"), ++ "W18", "mt8127", ++ MTK_EINT_FUNCTION(0, 52), ++ MTK_FUNCTION(0, "GPIO41"), ++ MTK_FUNCTION(1, "JTDI"), ++ MTK_FUNCTION(2, "CONN_MCU_TDI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(42, "JTDO"), ++ "Y18", "mt8127", ++ MTK_EINT_FUNCTION(0, 53), ++ MTK_FUNCTION(0, "GPIO42"), ++ MTK_FUNCTION(1, "JTDO"), ++ MTK_FUNCTION(2, "CONN_MCU_TDO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(43, "EINT11"), ++ "W22", "mt8127", ++ MTK_EINT_FUNCTION(0, 11), ++ MTK_FUNCTION(0, "GPIO43"), ++ MTK_FUNCTION(1, "CLKM4"), ++ MTK_FUNCTION(2, "PWM2"), ++ MTK_FUNCTION(3, "KROW3"), ++ MTK_FUNCTION(4, "ANT_SEL3"), ++ MTK_FUNCTION(5, "DPI_D10"), ++ MTK_FUNCTION(6, "EXT_RXD3"), ++ MTK_FUNCTION(7, "DBG_MON_B[9]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(44, "EINT12"), ++ "V23", "mt8127", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO44"), ++ MTK_FUNCTION(1, "CLKM5"), ++ MTK_FUNCTION(2, "PWM0"), ++ MTK_FUNCTION(3, "KCOL3"), ++ MTK_FUNCTION(4, "ANT_SEL4"), ++ MTK_FUNCTION(5, "DPI_D11"), ++ MTK_FUNCTION(6, "EXT_TXEN"), ++ MTK_FUNCTION(7, "DBG_MON_B[10]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(45, "EINT13"), ++ "Y21", "mt8127", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO45"), ++ MTK_FUNCTION(4, "ANT_SEL5"), ++ MTK_FUNCTION(5, "DPI_D0"), ++ MTK_FUNCTION(6, "SPDIF"), ++ MTK_FUNCTION(7, "DBG_MON_B[11]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(46, "EINT14"), ++ "F23", "mt8127", ++ MTK_EINT_FUNCTION(0, 14), ++ MTK_FUNCTION(0, "GPIO46"), ++ MTK_FUNCTION(2, "DAC_DAT_OUT"), ++ MTK_FUNCTION(4, "ANT_SEL1"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), ++ MTK_FUNCTION(6, "NCLE"), ++ MTK_FUNCTION(7, "DBG_MON_A[14]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(47, "EINT15"), ++ "G23", "mt8127", ++ MTK_EINT_FUNCTION(0, 15), ++ MTK_FUNCTION(0, "GPIO47"), ++ MTK_FUNCTION(2, "DAC_WS"), ++ MTK_FUNCTION(4, "ANT_SEL2"), ++ MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), ++ MTK_FUNCTION(6, "NCEB1"), ++ MTK_FUNCTION(7, "DBG_MON_A[15]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(48, "EINT16"), ++ "H23", "mt8127", ++ MTK_EINT_FUNCTION(0, 16), ++ MTK_FUNCTION(0, "GPIO48"), ++ MTK_FUNCTION(2, "DAC_CK"), ++ MTK_FUNCTION(4, "ANT_SEL3"), ++ MTK_FUNCTION(5, "CONN_MCU_TRST_B"), ++ MTK_FUNCTION(6, "NCEB0"), ++ MTK_FUNCTION(7, "DBG_MON_A[16]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(49, "EINT17"), ++ "J22", "mt8127", ++ MTK_EINT_FUNCTION(0, 17), ++ MTK_FUNCTION(0, "GPIO49"), ++ MTK_FUNCTION(1, "UCTS0"), ++ MTK_FUNCTION(3, "CLKM0"), ++ MTK_FUNCTION(4, "IDDIG"), ++ MTK_FUNCTION(5, "ANT_SEL4"), ++ MTK_FUNCTION(6, "NREB"), ++ MTK_FUNCTION(7, "DBG_MON_A[17]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(50, "EINT18"), ++ "AD20", "mt8127", ++ MTK_EINT_FUNCTION(0, 18), ++ MTK_FUNCTION(0, "GPIO50"), ++ MTK_FUNCTION(1, "URTS0"), ++ MTK_FUNCTION(2, "CLKM3"), ++ MTK_FUNCTION(3, "I2SOUT_LRCK"), ++ MTK_FUNCTION(4, "DRV_VBUS"), ++ MTK_FUNCTION(5, "ANT_SEL3"), ++ MTK_FUNCTION(6, "ADC_CK"), ++ MTK_FUNCTION(7, "DBG_MON_B[12]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(51, "EINT19"), ++ "AC21", "mt8127", ++ MTK_EINT_FUNCTION(0, 19), ++ MTK_FUNCTION(0, "GPIO51"), ++ MTK_FUNCTION(1, "UCTS1"), ++ MTK_FUNCTION(3, "I2SOUT_BCK"), ++ MTK_FUNCTION(4, "CLKM1"), ++ MTK_FUNCTION(5, "ANT_SEL4"), ++ MTK_FUNCTION(6, "ADC_DAT_IN"), ++ MTK_FUNCTION(7, "DBG_MON_B[13]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(52, "EINT20"), ++ "V20", "mt8127", ++ MTK_EINT_FUNCTION(0, 20), ++ MTK_FUNCTION(0, "GPIO52"), ++ MTK_FUNCTION(1, "URTS1"), ++ MTK_FUNCTION(2, "PCM_TX"), ++ MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), ++ MTK_FUNCTION(4, "CLKM2"), ++ MTK_FUNCTION(5, "ANT_SEL5"), ++ MTK_FUNCTION(6, "ADC_WS"), ++ MTK_FUNCTION(7, "DBG_MON_B[14]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(53, "SPI_CS"), ++ "AD19", "mt8127", ++ MTK_EINT_FUNCTION(0, 54), ++ MTK_FUNCTION(0, "GPIO53"), ++ MTK_FUNCTION(1, "SPI_CS"), ++ MTK_FUNCTION(3, "I2SIN1_DATA_IN"), ++ MTK_FUNCTION(4, "ADC_CK"), ++ MTK_FUNCTION(7, "DBG_MON_B[15]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(54, "SPI_CK"), ++ "AC18", "mt8127", ++ MTK_EINT_FUNCTION(0, 55), ++ MTK_FUNCTION(0, "GPIO54"), ++ MTK_FUNCTION(1, "SPI_CK"), ++ MTK_FUNCTION(3, "I2SIN1_LRCK"), ++ MTK_FUNCTION(4, "ADC_DAT_IN"), ++ MTK_FUNCTION(7, "DBG_MON_B[16]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(55, "SPI_MI"), ++ "AC19", "mt8127", ++ MTK_EINT_FUNCTION(0, 56), ++ MTK_FUNCTION(0, "GPIO55"), ++ MTK_FUNCTION(1, "SPI_MI"), ++ MTK_FUNCTION(2, "SPI_MO"), ++ MTK_FUNCTION(3, "I2SIN1_BCK1"), ++ MTK_FUNCTION(4, "ADC_WS"), ++ MTK_FUNCTION(7, "DBG_MON_B[17]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(56, "SPI_MO"), ++ "AD18", "mt8127", ++ MTK_EINT_FUNCTION(0, 57), ++ MTK_FUNCTION(0, "GPIO56"), ++ MTK_FUNCTION(1, "SPI_MO"), ++ MTK_FUNCTION(2, "SPI_MI"), ++ MTK_FUNCTION(7, "DBG_MON_B[18]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(57, "SDA1"), ++ "AE23", "mt8127", ++ MTK_EINT_FUNCTION(0, 58), ++ MTK_FUNCTION(0, "GPIO57"), ++ MTK_FUNCTION(1, "SDA1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(58, "SCL1"), ++ "AD23", "mt8127", ++ MTK_EINT_FUNCTION(0, 59), ++ MTK_FUNCTION(0, "GPIO58"), ++ MTK_FUNCTION(1, "SCL1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(59, "DISP_PWM"), ++ "AC20", "mt8127", ++ MTK_EINT_FUNCTION(0, 60), ++ MTK_FUNCTION(0, "GPIO59"), ++ MTK_FUNCTION(1, "DISP_PWM"), ++ MTK_FUNCTION(2, "PWM1"), ++ MTK_FUNCTION(7, "DBG_MON_A[18]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(60, "WB_RSTB"), ++ "AD7", "mt8127", ++ MTK_EINT_FUNCTION(0, 61), ++ MTK_FUNCTION(0, "GPIO60"), ++ MTK_FUNCTION(1, "WB_RSTB"), ++ MTK_FUNCTION(7, "DBG_MON_A[19]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(61, "F2W_DATA"), ++ "Y10", "mt8127", ++ MTK_EINT_FUNCTION(0, 62), ++ MTK_FUNCTION(0, "GPIO61"), ++ MTK_FUNCTION(1, "F2W_DATA"), ++ MTK_FUNCTION(7, "DBG_MON_A[20]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(62, "F2W_CLK"), ++ "W10", "mt8127", ++ MTK_EINT_FUNCTION(0, 63), ++ MTK_FUNCTION(0, "GPIO62"), ++ MTK_FUNCTION(1, "F2W_CK"), ++ MTK_FUNCTION(7, "DBG_MON_A[21]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(63, "WB_SCLK"), ++ "AB7", "mt8127", ++ MTK_EINT_FUNCTION(0, 64), ++ MTK_FUNCTION(0, "GPIO63"), ++ MTK_FUNCTION(1, "WB_SCLK"), ++ MTK_FUNCTION(7, "DBG_MON_A[22]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(64, "WB_SDATA"), ++ "AA7", "mt8127", ++ MTK_EINT_FUNCTION(0, 65), ++ MTK_FUNCTION(0, "GPIO64"), ++ MTK_FUNCTION(1, "WB_SDATA"), ++ MTK_FUNCTION(7, "DBG_MON_A[23]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(65, "WB_SEN"), ++ "Y7", "mt8127", ++ MTK_EINT_FUNCTION(0, 66), ++ MTK_FUNCTION(0, "GPIO65"), ++ MTK_FUNCTION(1, "WB_SEN"), ++ MTK_FUNCTION(7, "DBG_MON_A[24]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(66, "WB_CRTL0"), ++ "AA1", "mt8127", ++ MTK_EINT_FUNCTION(0, 67), ++ MTK_FUNCTION(0, "GPIO66"), ++ MTK_FUNCTION(1, "WB_CRTL0"), ++ MTK_FUNCTION(2, "DFD_NTRST_XI"), ++ MTK_FUNCTION(7, "DBG_MON_A[25]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(67, "WB_CRTL1"), ++ "AA2", "mt8127", ++ MTK_EINT_FUNCTION(0, 68), ++ MTK_FUNCTION(0, "GPIO67"), ++ MTK_FUNCTION(1, "WB_CRTL1"), ++ MTK_FUNCTION(2, "DFD_TMS_XI"), ++ MTK_FUNCTION(7, "DBG_MON_A[26]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(68, "WB_CRTL2"), ++ "Y1", "mt8127", ++ MTK_EINT_FUNCTION(0, 69), ++ MTK_FUNCTION(0, "GPIO68"), ++ MTK_FUNCTION(1, "WB_CRTL2"), ++ MTK_FUNCTION(2, "DFD_TCK_XI"), ++ MTK_FUNCTION(7, "DBG_MON_A[27]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(69, "WB_CRTL3"), ++ "Y2", "mt8127", ++ MTK_EINT_FUNCTION(0, 70), ++ MTK_FUNCTION(0, "GPIO69"), ++ MTK_FUNCTION(1, "WB_CRTL3"), ++ MTK_FUNCTION(2, "DFD_TDI_XI"), ++ MTK_FUNCTION(7, "DBG_MON_A[28]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(70, "WB_CRTL4"), ++ "Y3", "mt8127", ++ MTK_EINT_FUNCTION(0, 71), ++ MTK_FUNCTION(0, "GPIO70"), ++ MTK_FUNCTION(1, "WB_CRTL4"), ++ MTK_FUNCTION(2, "DFD_TDO"), ++ MTK_FUNCTION(7, "DBG_MON_A[29]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(71, "WB_CRTL5"), ++ "Y4", "mt8127", ++ MTK_EINT_FUNCTION(0, 72), ++ MTK_FUNCTION(0, "GPIO71"), ++ MTK_FUNCTION(1, "WB_CRTL5"), ++ MTK_FUNCTION(7, "DBG_MON_A[30]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(72, "I2S_DATA_IN"), ++ "K21", "mt8127", ++ MTK_EINT_FUNCTION(0, 73), ++ MTK_FUNCTION(0, "GPIO72"), ++ MTK_FUNCTION(1, "I2SIN1_DATA_IN"), ++ MTK_FUNCTION(2, "PCM_RX"), ++ MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), ++ MTK_FUNCTION(4, "DAC_DAT_OUT"), ++ MTK_FUNCTION(5, "PWM0"), ++ MTK_FUNCTION(6, "ADC_CK"), ++ MTK_FUNCTION(7, "DBG_MON_B[19]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(73, "I2S_LRCK"), ++ "L21", "mt8127", ++ MTK_EINT_FUNCTION(0, 74), ++ MTK_FUNCTION(0, "GPIO73"), ++ MTK_FUNCTION(1, "I2SIN1_LRCK"), ++ MTK_FUNCTION(2, "PCM_SYNC"), ++ MTK_FUNCTION(3, "I2SOUT_LRCK"), ++ MTK_FUNCTION(4, "DAC_WS"), ++ MTK_FUNCTION(5, "PWM3"), ++ MTK_FUNCTION(6, "ADC_DAT_IN"), ++ MTK_FUNCTION(7, "DBG_MON_B[20]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(74, "I2S_BCK"), ++ "L20", "mt8127", ++ MTK_EINT_FUNCTION(0, 75), ++ MTK_FUNCTION(0, "GPIO74"), ++ MTK_FUNCTION(1, "I2SIN1_BCK2"), ++ MTK_FUNCTION(2, "PCM_CLK1"), ++ MTK_FUNCTION(3, "I2SOUT_BCK"), ++ MTK_FUNCTION(4, "DAC_CK"), ++ MTK_FUNCTION(5, "PWM4"), ++ MTK_FUNCTION(6, "ADC_WS"), ++ MTK_FUNCTION(7, "DBG_MON_B[21]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(75, "SDA0"), ++ "W3", "mt8127", ++ MTK_EINT_FUNCTION(0, 76), ++ MTK_FUNCTION(0, "GPIO75"), ++ MTK_FUNCTION(1, "SDA0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(76, "SCL0"), ++ "W4", "mt8127", ++ MTK_EINT_FUNCTION(0, 77), ++ MTK_FUNCTION(0, "GPIO76"), ++ MTK_FUNCTION(1, "SCL0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(77, "SDA2"), ++ "K19", "mt8127", ++ MTK_EINT_FUNCTION(0, 78), ++ MTK_FUNCTION(0, "GPIO77"), ++ MTK_FUNCTION(1, "SDA2"), ++ MTK_FUNCTION(2, "PWM1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(78, "SCL2"), ++ "K20", "mt8127", ++ MTK_EINT_FUNCTION(0, 79), ++ MTK_FUNCTION(0, "GPIO78"), ++ MTK_FUNCTION(1, "SCL2"), ++ MTK_FUNCTION(2, "PWM2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(79, "URXD0"), ++ "K18", "mt8127", ++ MTK_EINT_FUNCTION(0, 80), ++ MTK_FUNCTION(0, "GPIO79"), ++ MTK_FUNCTION(1, "URXD0"), ++ MTK_FUNCTION(2, "UTXD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(80, "UTXD0"), ++ "K17", "mt8127", ++ MTK_EINT_FUNCTION(0, 81), ++ MTK_FUNCTION(0, "GPIO80"), ++ MTK_FUNCTION(1, "UTXD0"), ++ MTK_FUNCTION(2, "URXD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(81, "URXD1"), ++ "L17", "mt8127", ++ MTK_EINT_FUNCTION(0, 82), ++ MTK_FUNCTION(0, "GPIO81"), ++ MTK_FUNCTION(1, "URXD1"), ++ MTK_FUNCTION(2, "UTXD1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(82, "UTXD1"), ++ "L18", "mt8127", ++ MTK_EINT_FUNCTION(0, 83), ++ MTK_FUNCTION(0, "GPIO82"), ++ MTK_FUNCTION(1, "UTXD1"), ++ MTK_FUNCTION(2, "URXD1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(83, "LCM_RST"), ++ "W5", "mt8127", ++ MTK_EINT_FUNCTION(0, 84), ++ MTK_FUNCTION(0, "GPIO83"), ++ MTK_FUNCTION(1, "LCM_RST"), ++ MTK_FUNCTION(2, "VDAC_CK_XI"), ++ MTK_FUNCTION(7, "DBG_MON_A[31]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(84, "DSI_TE"), ++ "W6", "mt8127", ++ MTK_EINT_FUNCTION(0, 85), ++ MTK_FUNCTION(0, "GPIO84"), ++ MTK_FUNCTION(1, "DSI_TE"), ++ MTK_FUNCTION(7, "DBG_MON_A[32]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(85, "MSDC2_CMD"), ++ "U7", "mt8127", ++ MTK_EINT_FUNCTION(0, 86), ++ MTK_FUNCTION(0, "GPIO85"), ++ MTK_FUNCTION(1, "MSDC2_CMD"), ++ MTK_FUNCTION(2, "ANT_SEL0"), ++ MTK_FUNCTION(3, "SDA1"), ++ MTK_FUNCTION(6, "I2SOUT_BCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[22]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(86, "MSDC2_CLK"), ++ "T8", "mt8127", ++ MTK_EINT_FUNCTION(0, 87), ++ MTK_FUNCTION(0, "GPIO86"), ++ MTK_FUNCTION(1, "MSDC2_CLK"), ++ MTK_FUNCTION(2, "ANT_SEL1"), ++ MTK_FUNCTION(3, "SCL1"), ++ MTK_FUNCTION(6, "I2SOUT_LRCK"), ++ MTK_FUNCTION(7, "DBG_MON_B[23]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(87, "MSDC2_DAT0"), ++ "V3", "mt8127", ++ MTK_EINT_FUNCTION(0, 88), ++ MTK_FUNCTION(0, "GPIO87"), ++ MTK_FUNCTION(1, "MSDC2_DAT0"), ++ MTK_FUNCTION(2, "ANT_SEL2"), ++ MTK_FUNCTION(5, "UTXD0"), ++ MTK_FUNCTION(6, "I2SOUT_DATA_OUT"), ++ MTK_FUNCTION(7, "DBG_MON_B[24]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(88, "MSDC2_DAT1"), ++ "V4", "mt8127", ++ MTK_EINT_FUNCTION(0, 89), ++ MTK_FUNCTION(0, "GPIO88"), ++ MTK_FUNCTION(1, "MSDC2_DAT1"), ++ MTK_FUNCTION(2, "ANT_SEL3"), ++ MTK_FUNCTION(3, "PWM0"), ++ MTK_FUNCTION(5, "URXD0"), ++ MTK_FUNCTION(6, "PWM1"), ++ MTK_FUNCTION(7, "DBG_MON_B[25]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(89, "MSDC2_DAT2"), ++ "U5", "mt8127", ++ MTK_EINT_FUNCTION(0, 90), ++ MTK_FUNCTION(0, "GPIO89"), ++ MTK_FUNCTION(1, "MSDC2_DAT2"), ++ MTK_FUNCTION(2, "ANT_SEL4"), ++ MTK_FUNCTION(3, "SDA2"), ++ MTK_FUNCTION(5, "UTXD1"), ++ MTK_FUNCTION(6, "PWM2"), ++ MTK_FUNCTION(7, "DBG_MON_B[26]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(90, "MSDC2_DAT3"), ++ "U6", "mt8127", ++ MTK_EINT_FUNCTION(0, 91), ++ MTK_FUNCTION(0, "GPIO90"), ++ MTK_FUNCTION(1, "MSDC2_DAT3"), ++ MTK_FUNCTION(2, "ANT_SEL5"), ++ MTK_FUNCTION(3, "SCL2"), ++ MTK_FUNCTION(4, "EXT_FRAME_SYNC"), ++ MTK_FUNCTION(5, "URXD1"), ++ MTK_FUNCTION(6, "PWM3"), ++ MTK_FUNCTION(7, "DBG_MON_B[27]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(91, "TDN3"), ++ "U2", "mt8127", ++ MTK_EINT_FUNCTION(0, 92), ++ MTK_FUNCTION(0, "GPI91"), ++ MTK_FUNCTION(1, "TDN3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(92, "TDP3"), ++ "U1", "mt8127", ++ MTK_EINT_FUNCTION(0, 93), ++ MTK_FUNCTION(0, "GPI92"), ++ MTK_FUNCTION(1, "TDP3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(93, "TDN2"), ++ "T2", "mt8127", ++ MTK_EINT_FUNCTION(0, 94), ++ MTK_FUNCTION(0, "GPI93"), ++ MTK_FUNCTION(1, "TDN2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(94, "TDP2"), ++ "T1", "mt8127", ++ MTK_EINT_FUNCTION(0, 95), ++ MTK_FUNCTION(0, "GPI94"), ++ MTK_FUNCTION(1, "TDP2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(95, "TCN"), ++ "R5", "mt8127", ++ MTK_EINT_FUNCTION(0, 96), ++ MTK_FUNCTION(0, "GPI95"), ++ MTK_FUNCTION(1, "TCN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(96, "TCP"), ++ "R4", "mt8127", ++ MTK_EINT_FUNCTION(0, 97), ++ MTK_FUNCTION(0, "GPI96"), ++ MTK_FUNCTION(1, "TCP") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(97, "TDN1"), ++ "R3", "mt8127", ++ MTK_EINT_FUNCTION(0, 98), ++ MTK_FUNCTION(0, "GPI97"), ++ MTK_FUNCTION(1, "TDN1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(98, "TDP1"), ++ "R2", "mt8127", ++ MTK_EINT_FUNCTION(0, 99), ++ MTK_FUNCTION(0, "GPI98"), ++ MTK_FUNCTION(1, "TDP1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(99, "TDN0"), ++ "P3", "mt8127", ++ MTK_EINT_FUNCTION(0, 100), ++ MTK_FUNCTION(0, "GPI99"), ++ MTK_FUNCTION(1, "TDN0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(100, "TDP0"), ++ "P2", "mt8127", ++ MTK_EINT_FUNCTION(0, 101), ++ MTK_FUNCTION(0, "GPI100"), ++ MTK_FUNCTION(1, "TDP0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(101, "RDN0"), ++ "K1", "mt8127", ++ MTK_EINT_FUNCTION(0, 102), ++ MTK_FUNCTION(0, "GPI101"), ++ MTK_FUNCTION(1, "RDN0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(102, "RDP0"), ++ "K2", "mt8127", ++ MTK_EINT_FUNCTION(0, 103), ++ MTK_FUNCTION(0, "GPI102"), ++ MTK_FUNCTION(1, "RDP0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(103, "RDN1"), ++ "L2", "mt8127", ++ MTK_EINT_FUNCTION(0, 104), ++ MTK_FUNCTION(0, "GPI103"), ++ MTK_FUNCTION(1, "RDN1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(104, "RDP1"), ++ "L3", "mt8127", ++ MTK_EINT_FUNCTION(0, 105), ++ MTK_FUNCTION(0, "GPI104"), ++ MTK_FUNCTION(1, "RDP1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(105, "RCN"), ++ "M4", "mt8127", ++ MTK_EINT_FUNCTION(0, 106), ++ MTK_FUNCTION(0, "GPI105"), ++ MTK_FUNCTION(1, "RCN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(106, "RCP"), ++ "M5", "mt8127", ++ MTK_EINT_FUNCTION(0, 107), ++ MTK_FUNCTION(0, "GPI106"), ++ MTK_FUNCTION(1, "RCP") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(107, "RDN2"), ++ "M2", "mt8127", ++ MTK_EINT_FUNCTION(0, 108), ++ MTK_FUNCTION(0, "GPI107"), ++ MTK_FUNCTION(1, "RDN2"), ++ MTK_FUNCTION(2, "CMDAT8") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(108, "RDP2"), ++ "M3", "mt8127", ++ MTK_EINT_FUNCTION(0, 109), ++ MTK_FUNCTION(0, "GPI108"), ++ MTK_FUNCTION(1, "RDP2"), ++ MTK_FUNCTION(2, "CMDAT9") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(109, "RDN3"), ++ "N2", "mt8127", ++ MTK_EINT_FUNCTION(0, 110), ++ MTK_FUNCTION(0, "GPI109"), ++ MTK_FUNCTION(1, "RDN3"), ++ MTK_FUNCTION(2, "CMDAT4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(110, "RDP3"), ++ "N3", "mt8127", ++ MTK_EINT_FUNCTION(0, 111), ++ MTK_FUNCTION(0, "GPI110"), ++ MTK_FUNCTION(1, "RDP3"), ++ MTK_FUNCTION(2, "CMDAT5") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(111, "RCN_A"), ++ "J5", "mt8127", ++ MTK_EINT_FUNCTION(0, 112), ++ MTK_FUNCTION(0, "GPI111"), ++ MTK_FUNCTION(1, "RCN_A"), ++ MTK_FUNCTION(2, "CMDAT6") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(112, "RCP_A"), ++ "J4", "mt8127", ++ MTK_EINT_FUNCTION(0, 113), ++ MTK_FUNCTION(0, "GPI112"), ++ MTK_FUNCTION(1, "RCP_A"), ++ MTK_FUNCTION(2, "CMDAT7") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(113, "RDN1_A"), ++ "J2", "mt8127", ++ MTK_EINT_FUNCTION(0, 114), ++ MTK_FUNCTION(0, "GPI113"), ++ MTK_FUNCTION(1, "RDN1_A"), ++ MTK_FUNCTION(2, "CMDAT2"), ++ MTK_FUNCTION(3, "CMCSD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(114, "RDP1_A"), ++ "J3", "mt8127", ++ MTK_EINT_FUNCTION(0, 115), ++ MTK_FUNCTION(0, "GPI114"), ++ MTK_FUNCTION(1, "RDP1_A"), ++ MTK_FUNCTION(2, "CMDAT3"), ++ MTK_FUNCTION(3, "CMCSD3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(115, "RDN0_A"), ++ "H2", "mt8127", ++ MTK_EINT_FUNCTION(0, 116), ++ MTK_FUNCTION(0, "GPI115"), ++ MTK_FUNCTION(1, "RDN0_A"), ++ MTK_FUNCTION(2, "CMHSYNC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(116, "RDP0_A"), ++ "H3", "mt8127", ++ MTK_EINT_FUNCTION(0, 117), ++ MTK_FUNCTION(0, "GPI116"), ++ MTK_FUNCTION(1, "RDP0_A"), ++ MTK_FUNCTION(2, "CMVSYNC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(117, "CMDAT0"), ++ "G5", "mt8127", ++ MTK_EINT_FUNCTION(0, 118), ++ MTK_FUNCTION(0, "GPIO117"), ++ MTK_FUNCTION(1, "CMDAT0"), ++ MTK_FUNCTION(2, "CMCSD0"), ++ MTK_FUNCTION(3, "ANT_SEL2"), ++ MTK_FUNCTION(7, "DBG_MON_B[28]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(118, "CMDAT1"), ++ "G4", "mt8127", ++ MTK_EINT_FUNCTION(0, 119), ++ MTK_FUNCTION(0, "GPIO118"), ++ MTK_FUNCTION(1, "CMDAT1"), ++ MTK_FUNCTION(2, "CMCSD1"), ++ MTK_FUNCTION(3, "ANT_SEL3"), ++ MTK_FUNCTION(7, "DBG_MON_B[29]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(119, "CMMCLK"), ++ "F3", "mt8127", ++ MTK_EINT_FUNCTION(0, 120), ++ MTK_FUNCTION(0, "GPIO119"), ++ MTK_FUNCTION(1, "CMMCLK"), ++ MTK_FUNCTION(3, "ANT_SEL4"), ++ MTK_FUNCTION(7, "DBG_MON_B[30]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(120, "CMPCLK"), ++ "G6", "mt8127", ++ MTK_EINT_FUNCTION(0, 121), ++ MTK_FUNCTION(0, "GPIO120"), ++ MTK_FUNCTION(1, "CMPCLK"), ++ MTK_FUNCTION(2, "CMCSK"), ++ MTK_FUNCTION(3, "ANT_SEL5"), ++ MTK_FUNCTION(7, "DBG_MON_B[31]") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(121, "MSDC1_CMD"), ++ "E3", "mt8127", ++ MTK_EINT_FUNCTION(0, 122), ++ MTK_FUNCTION(0, "GPIO121"), ++ MTK_FUNCTION(1, "MSDC1_CMD") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(122, "MSDC1_CLK"), ++ "D1", "mt8127", ++ MTK_EINT_FUNCTION(0, 123), ++ MTK_FUNCTION(0, "GPIO122"), ++ MTK_FUNCTION(1, "MSDC1_CLK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(123, "MSDC1_DAT0"), ++ "D2", "mt8127", ++ MTK_EINT_FUNCTION(0, 124), ++ MTK_FUNCTION(0, "GPIO123"), ++ MTK_FUNCTION(1, "MSDC1_DAT0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(124, "MSDC1_DAT1"), ++ "D3", "mt8127", ++ MTK_EINT_FUNCTION(0, 125), ++ MTK_FUNCTION(0, "GPIO124"), ++ MTK_FUNCTION(1, "MSDC1_DAT1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(125, "MSDC1_DAT2"), ++ "F2", "mt8127", ++ MTK_EINT_FUNCTION(0, 126), ++ MTK_FUNCTION(0, "GPIO125"), ++ MTK_FUNCTION(1, "MSDC1_DAT2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(126, "MSDC1_DAT3"), ++ "E2", "mt8127", ++ MTK_EINT_FUNCTION(0, 127), ++ MTK_FUNCTION(0, "GPIO126"), ++ MTK_FUNCTION(1, "MSDC1_DAT3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(127, "MSDC0_DAT7"), ++ "C23", "mt8127", ++ MTK_EINT_FUNCTION(0, 128), ++ MTK_FUNCTION(0, "GPIO127"), ++ MTK_FUNCTION(1, "MSDC0_DAT7"), ++ MTK_FUNCTION(4, "NLD7") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(128, "MSDC0_DAT6"), ++ "C24", "mt8127", ++ MTK_EINT_FUNCTION(0, 129), ++ MTK_FUNCTION(0, "GPIO128"), ++ MTK_FUNCTION(1, "MSDC0_DAT6"), ++ MTK_FUNCTION(4, "NLD6") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(129, "MSDC0_DAT5"), ++ "D22", "mt8127", ++ MTK_EINT_FUNCTION(0, 130), ++ MTK_FUNCTION(0, "GPIO129"), ++ MTK_FUNCTION(1, "MSDC0_DAT5"), ++ MTK_FUNCTION(4, "NLD4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(130, "MSDC0_DAT4"), ++ "D24", "mt8127", ++ MTK_EINT_FUNCTION(0, 131), ++ MTK_FUNCTION(0, "GPIO130"), ++ MTK_FUNCTION(1, "MSDC0_DAT4"), ++ MTK_FUNCTION(4, "NLD3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(131, "MSDC0_RSTB"), ++ "F24", "mt8127", ++ MTK_EINT_FUNCTION(0, 132), ++ MTK_FUNCTION(0, "GPIO131"), ++ MTK_FUNCTION(1, "MSDC0_RSTB"), ++ MTK_FUNCTION(4, "NLD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(132, "MSDC0_CMD"), ++ "G20", "mt8127", ++ MTK_EINT_FUNCTION(0, 133), ++ MTK_FUNCTION(0, "GPIO132"), ++ MTK_FUNCTION(1, "MSDC0_CMD"), ++ MTK_FUNCTION(4, "NALE") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(133, "MSDC0_CLK"), ++ "G21", "mt8127", ++ MTK_EINT_FUNCTION(0, 134), ++ MTK_FUNCTION(0, "GPIO133"), ++ MTK_FUNCTION(1, "MSDC0_CLK"), ++ MTK_FUNCTION(4, "NWEB") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(134, "MSDC0_DAT3"), ++ "D23", "mt8127", ++ MTK_EINT_FUNCTION(0, 135), ++ MTK_FUNCTION(0, "GPIO134"), ++ MTK_FUNCTION(1, "MSDC0_DAT3"), ++ MTK_FUNCTION(4, "NLD1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(135, "MSDC0_DAT2"), ++ "E22", "mt8127", ++ MTK_EINT_FUNCTION(0, 136), ++ MTK_FUNCTION(0, "GPIO135"), ++ MTK_FUNCTION(1, "MSDC0_DAT2"), ++ MTK_FUNCTION(4, "NLD5") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(136, "MSDC0_DAT1"), ++ "E23", "mt8127", ++ MTK_EINT_FUNCTION(0, 137), ++ MTK_FUNCTION(0, "GPIO136"), ++ MTK_FUNCTION(1, "MSDC0_DAT1"), ++ MTK_FUNCTION(4, "NLD8") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(137, "MSDC0_DAT0"), ++ "F22", "mt8127", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO137"), ++ MTK_FUNCTION(1, "MSDC0_DAT0"), ++ MTK_FUNCTION(4, "WATCHDOG"), ++ MTK_FUNCTION(5, "NLD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(138, "CEC"), ++ "AE21", "mt8127", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO138"), ++ MTK_FUNCTION(1, "CEC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(139, "HTPLG"), ++ "AD21", "mt8127", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO139"), ++ MTK_FUNCTION(1, "HTPLG") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(140, "HDMISCK"), ++ "AE22", "mt8127", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO140"), ++ MTK_FUNCTION(1, "HDMISCK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(141, "HDMISD"), ++ "AD22", "mt8127", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO141"), ++ MTK_FUNCTION(1, "HDMISD") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(142, "EINT21"), ++ "J23", "mt8127", ++ MTK_EINT_FUNCTION(0, 21), ++ MTK_FUNCTION(0, "GPIO142"), ++ MTK_FUNCTION(1, "NRNB"), ++ MTK_FUNCTION(2, "ANT_SEL0"), ++ MTK_FUNCTION(7, "DBG_MON_B[32]") ++ ), ++}; ++ ++#endif /* __PINCTRL_MTK_MT8127_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0055-mfd-mediatek-Add-GPIO-sub-module-support-into-mfd.patch b/target/linux/mediatek/patches/0055-mfd-mediatek-Add-GPIO-sub-module-support-into-mfd.patch new file mode 100644 index 0000000..d9c0676 --- /dev/null +++ b/target/linux/mediatek/patches/0055-mfd-mediatek-Add-GPIO-sub-module-support-into-mfd.patch @@ -0,0 +1,30 @@ +From e5de6556a25d4b2e2d30683d629095bce102c792 Mon Sep 17 00:00:00 2001 +From: Hongzhou Yang +Date: Mon, 18 May 2015 23:11:19 -0700 +Subject: [PATCH 55/76] mfd: mediatek: Add GPIO sub module support into mfd. + +Register pinctrl subnode into 6397 mfd cell. + +Signed-off-by: Hongzhou Yang +Acked-by: Linus Walleij +--- + drivers/mfd/mt6397-core.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c +index 09bc780..012c620 100644 +--- a/drivers/mfd/mt6397-core.c ++++ b/drivers/mfd/mt6397-core.c +@@ -34,6 +34,9 @@ static const struct mfd_cell mt6397_devs[] = { + }, { + .name = "mt6397-clk", + .of_compatible = "mediatek,mt6397-clk", ++ }, { ++ .name = "mediatek-mt6397-pinctrl", ++ .of_compatible = "mediatek,mt6397-pinctrl", + }, + }; + +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0056-ARM-dts-mt8127-add-pinctrl-GPIO-EINT-node-for-mt8127.patch b/target/linux/mediatek/patches/0056-ARM-dts-mt8127-add-pinctrl-GPIO-EINT-node-for-mt8127.patch new file mode 100644 index 0000000..a59d2c6 --- /dev/null +++ b/target/linux/mediatek/patches/0056-ARM-dts-mt8127-add-pinctrl-GPIO-EINT-node-for-mt8127.patch @@ -0,0 +1,809 @@ +From 619e31dbd73885249f3db545ed0b7678ca98c248 Mon Sep 17 00:00:00 2001 +From: Yingjoe Chen +Date: Mon, 18 May 2015 23:11:20 -0700 +Subject: [PATCH 56/76] ARM: dts: mt8127: add pinctrl/GPIO/EINT node for + mt8127 + +Add pinctrl,GPIO and EINT node to mt8127.dtsi. + +Signed-off-by: Yingjoe Chen +Signed-off-by: Hongzhou Yang +Acked-by: Linus Walleij +Acked-by: Matthias Brugger +--- + arch/arm/boot/dts/mt8127-pinfunc.h | 742 ++++++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/mt8127.dtsi | 22 ++ + 2 files changed, 764 insertions(+) + create mode 100644 arch/arm/boot/dts/mt8127-pinfunc.h + +diff --git a/arch/arm/boot/dts/mt8127-pinfunc.h b/arch/arm/boot/dts/mt8127-pinfunc.h +new file mode 100644 +index 0000000..9198331 +--- /dev/null ++++ b/arch/arm/boot/dts/mt8127-pinfunc.h +@@ -0,0 +1,742 @@ ++#ifndef __DTS_MT8127_PINFUNC_H ++#define __DTS_MT8127_PINFUNC_H ++ ++#include ++ ++#define MT8127_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) ++#define MT8127_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) ++#define MT8127_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) ++ ++#define MT8127_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) ++#define MT8127_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) ++#define MT8127_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) ++ ++#define MT8127_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) ++ ++#define MT8127_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) ++#define MT8127_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) ++ ++#define MT8127_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) ++#define MT8127_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) ++ ++#define MT8127_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) ++#define MT8127_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) ++#define MT8127_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 2) ++#define MT8127_PIN_5_PWRAP_SPI0_CK2__FUNC_VDEC_TEST_CK (MTK_PIN_NO(5) | 3) ++#define MT8127_PIN_5_PWRAP_SPI0_CK2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(5) | 7) ++ ++#define MT8127_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) ++#define MT8127_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) ++#define MT8127_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 2) ++#define MT8127_PIN_6_PWRAP_SPI0_CSN2__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 3) ++#define MT8127_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(6) | 7) ++ ++#define MT8127_PIN_7_AUD_CLK_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) ++#define MT8127_PIN_7_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(7) | 1) ++#define MT8127_PIN_7_AUD_CLK_MOSI__FUNC_ADC_CK (MTK_PIN_NO(7) | 2) ++ ++#define MT8127_PIN_8_AUD_DAT_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) ++#define MT8127_PIN_8_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(8) | 1) ++#define MT8127_PIN_8_AUD_DAT_MISO__FUNC_ADC_DAT_IN (MTK_PIN_NO(8) | 2) ++#define MT8127_PIN_8_AUD_DAT_MISO__FUNC_AUD_MOSI (MTK_PIN_NO(8) | 3) ++ ++#define MT8127_PIN_9_AUD_DAT_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) ++#define MT8127_PIN_9_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(9) | 1) ++#define MT8127_PIN_9_AUD_DAT_MOSI__FUNC_ADC_WS (MTK_PIN_NO(9) | 2) ++#define MT8127_PIN_9_AUD_DAT_MOSI__FUNC_AUD_MISO (MTK_PIN_NO(9) | 3) ++ ++#define MT8127_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) ++#define MT8127_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) ++ ++#define MT8127_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) ++#define MT8127_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) ++ ++#define MT8127_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) ++#define MT8127_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) ++ ++#define MT8127_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) ++#define MT8127_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) ++ ++#define MT8127_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) ++#define MT8127_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1) ++#define MT8127_PIN_14_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(14) | 2) ++#define MT8127_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 3) ++#define MT8127_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) ++#define MT8127_PIN_14_URXD2__FUNC_KROW4 (MTK_PIN_NO(14) | 6) ++ ++#define MT8127_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) ++#define MT8127_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1) ++#define MT8127_PIN_15_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 2) ++#define MT8127_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 3) ++#define MT8127_PIN_15_UTXD2__FUNC_KROW5 (MTK_PIN_NO(15) | 6) ++ ++#define MT8127_PIN_16_URXD3__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) ++#define MT8127_PIN_16_URXD3__FUNC_URXD3 (MTK_PIN_NO(16) | 1) ++#define MT8127_PIN_16_URXD3__FUNC_DPI_DE (MTK_PIN_NO(16) | 2) ++#define MT8127_PIN_16_URXD3__FUNC_UTXD3 (MTK_PIN_NO(16) | 3) ++#define MT8127_PIN_16_URXD3__FUNC_UCTS2 (MTK_PIN_NO(16) | 4) ++#define MT8127_PIN_16_URXD3__FUNC_PWM3 (MTK_PIN_NO(16) | 5) ++#define MT8127_PIN_16_URXD3__FUNC_KROW6 (MTK_PIN_NO(16) | 6) ++ ++#define MT8127_PIN_17_UTXD3__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) ++#define MT8127_PIN_17_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(17) | 1) ++#define MT8127_PIN_17_UTXD3__FUNC_DPI_VSYNC (MTK_PIN_NO(17) | 2) ++#define MT8127_PIN_17_UTXD3__FUNC_URXD3 (MTK_PIN_NO(17) | 3) ++#define MT8127_PIN_17_UTXD3__FUNC_URTS2 (MTK_PIN_NO(17) | 4) ++#define MT8127_PIN_17_UTXD3__FUNC_PWM4 (MTK_PIN_NO(17) | 5) ++#define MT8127_PIN_17_UTXD3__FUNC_KROW7 (MTK_PIN_NO(17) | 6) ++ ++#define MT8127_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) ++#define MT8127_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) ++#define MT8127_PIN_18_PCM_CLK__FUNC_DPI_D4 (MTK_PIN_NO(18) | 2) ++#define MT8127_PIN_18_PCM_CLK__FUNC_I2SIN1_BCK0 (MTK_PIN_NO(18) | 3) ++#define MT8127_PIN_18_PCM_CLK__FUNC_I2SOUT_BCK (MTK_PIN_NO(18) | 4) ++#define MT8127_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) ++#define MT8127_PIN_18_PCM_CLK__FUNC_IR (MTK_PIN_NO(18) | 6) ++#define MT8127_PIN_18_PCM_CLK__FUNC_DBG_MON_A_0 (MTK_PIN_NO(18) | 7) ++ ++#define MT8127_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) ++#define MT8127_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) ++#define MT8127_PIN_19_PCM_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(19) | 2) ++#define MT8127_PIN_19_PCM_SYNC__FUNC_I2SIN1_LRCK (MTK_PIN_NO(19) | 3) ++#define MT8127_PIN_19_PCM_SYNC__FUNC_I2SOUT_LRCK (MTK_PIN_NO(19) | 4) ++#define MT8127_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) ++#define MT8127_PIN_19_PCM_SYNC__FUNC_EXT_COL (MTK_PIN_NO(19) | 6) ++#define MT8127_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_1 (MTK_PIN_NO(19) | 7) ++ ++#define MT8127_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) ++#define MT8127_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1) ++#define MT8127_PIN_20_PCM_RX__FUNC_DPI_D1 (MTK_PIN_NO(20) | 2) ++#define MT8127_PIN_20_PCM_RX__FUNC_I2SIN1_DATA_IN (MTK_PIN_NO(20) | 3) ++#define MT8127_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4) ++#define MT8127_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) ++#define MT8127_PIN_20_PCM_RX__FUNC_EXT_MDIO (MTK_PIN_NO(20) | 6) ++#define MT8127_PIN_20_PCM_RX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(20) | 7) ++ ++#define MT8127_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) ++#define MT8127_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1) ++#define MT8127_PIN_21_PCM_TX__FUNC_DPI_D2 (MTK_PIN_NO(21) | 2) ++#define MT8127_PIN_21_PCM_TX__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(21) | 3) ++#define MT8127_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4) ++#define MT8127_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) ++#define MT8127_PIN_21_PCM_TX__FUNC_EXT_MDC (MTK_PIN_NO(21) | 6) ++#define MT8127_PIN_21_PCM_TX__FUNC_DBG_MON_A_3 (MTK_PIN_NO(21) | 7) ++ ++#define MT8127_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) ++#define MT8127_PIN_22_EINT0__FUNC_PWM1 (MTK_PIN_NO(22) | 1) ++#define MT8127_PIN_22_EINT0__FUNC_DPI_CK (MTK_PIN_NO(22) | 2) ++#define MT8127_PIN_22_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(22) | 4) ++#define MT8127_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 5) ++#define MT8127_PIN_22_EINT0__FUNC_DBG_MON_A_4 (MTK_PIN_NO(22) | 7) ++ ++#define MT8127_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) ++#define MT8127_PIN_23_EINT1__FUNC_PWM2 (MTK_PIN_NO(23) | 1) ++#define MT8127_PIN_23_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(23) | 2) ++#define MT8127_PIN_23_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(23) | 4) ++#define MT8127_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 5) ++#define MT8127_PIN_23_EINT1__FUNC_DBG_MON_A_5 (MTK_PIN_NO(23) | 7) ++ ++#define MT8127_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) ++#define MT8127_PIN_24_EINT2__FUNC_CLKM0 (MTK_PIN_NO(24) | 1) ++#define MT8127_PIN_24_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(24) | 2) ++#define MT8127_PIN_24_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(24) | 4) ++#define MT8127_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 5) ++#define MT8127_PIN_24_EINT2__FUNC_KCOL4 (MTK_PIN_NO(24) | 6) ++#define MT8127_PIN_24_EINT2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(24) | 7) ++ ++#define MT8127_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) ++#define MT8127_PIN_25_EINT3__FUNC_CLKM1 (MTK_PIN_NO(25) | 1) ++#define MT8127_PIN_25_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(25) | 2) ++#define MT8127_PIN_25_EINT3__FUNC_SPI_MI (MTK_PIN_NO(25) | 3) ++#define MT8127_PIN_25_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(25) | 4) ++#define MT8127_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 5) ++#define MT8127_PIN_25_EINT3__FUNC_KCOL5 (MTK_PIN_NO(25) | 6) ++#define MT8127_PIN_25_EINT3__FUNC_DBG_MON_A_7 (MTK_PIN_NO(25) | 7) ++ ++#define MT8127_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) ++#define MT8127_PIN_26_EINT4__FUNC_CLKM2 (MTK_PIN_NO(26) | 1) ++#define MT8127_PIN_26_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(26) | 2) ++#define MT8127_PIN_26_EINT4__FUNC_SPI_MO (MTK_PIN_NO(26) | 3) ++#define MT8127_PIN_26_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(26) | 4) ++#define MT8127_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 5) ++#define MT8127_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 6) ++#define MT8127_PIN_26_EINT4__FUNC_DBG_MON_A_8 (MTK_PIN_NO(26) | 7) ++ ++#define MT8127_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) ++#define MT8127_PIN_27_EINT5__FUNC_UCTS2 (MTK_PIN_NO(27) | 1) ++#define MT8127_PIN_27_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(27) | 2) ++#define MT8127_PIN_27_EINT5__FUNC_SPI_CS (MTK_PIN_NO(27) | 3) ++#define MT8127_PIN_27_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(27) | 4) ++#define MT8127_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 5) ++#define MT8127_PIN_27_EINT5__FUNC_KCOL6 (MTK_PIN_NO(27) | 6) ++#define MT8127_PIN_27_EINT5__FUNC_DBG_MON_A_9 (MTK_PIN_NO(27) | 7) ++ ++#define MT8127_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) ++#define MT8127_PIN_28_EINT6__FUNC_URTS2 (MTK_PIN_NO(28) | 1) ++#define MT8127_PIN_28_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(28) | 2) ++#define MT8127_PIN_28_EINT6__FUNC_SPI_CK (MTK_PIN_NO(28) | 3) ++#define MT8127_PIN_28_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(28) | 4) ++#define MT8127_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 5) ++#define MT8127_PIN_28_EINT6__FUNC_KCOL7 (MTK_PIN_NO(28) | 6) ++#define MT8127_PIN_28_EINT6__FUNC_DBG_MON_A_10 (MTK_PIN_NO(28) | 7) ++ ++#define MT8127_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) ++#define MT8127_PIN_29_EINT7__FUNC_UCTS3 (MTK_PIN_NO(29) | 1) ++#define MT8127_PIN_29_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(29) | 2) ++#define MT8127_PIN_29_EINT7__FUNC_SDA1 (MTK_PIN_NO(29) | 3) ++#define MT8127_PIN_29_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(29) | 4) ++#define MT8127_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 5) ++#define MT8127_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 6) ++#define MT8127_PIN_29_EINT7__FUNC_DBG_MON_A_11 (MTK_PIN_NO(29) | 7) ++ ++#define MT8127_PIN_30_EINT8__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) ++#define MT8127_PIN_30_EINT8__FUNC_URTS3 (MTK_PIN_NO(30) | 1) ++#define MT8127_PIN_30_EINT8__FUNC_CLKM3 (MTK_PIN_NO(30) | 2) ++#define MT8127_PIN_30_EINT8__FUNC_SCL1 (MTK_PIN_NO(30) | 3) ++#define MT8127_PIN_30_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(30) | 4) ++#define MT8127_PIN_30_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(30) | 5) ++#define MT8127_PIN_30_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(30) | 6) ++#define MT8127_PIN_30_EINT8__FUNC_DBG_MON_B_2 (MTK_PIN_NO(30) | 7) ++ ++#define MT8127_PIN_31_EINT9__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) ++#define MT8127_PIN_31_EINT9__FUNC_CLKM4 (MTK_PIN_NO(31) | 1) ++#define MT8127_PIN_31_EINT9__FUNC_SDA2 (MTK_PIN_NO(31) | 2) ++#define MT8127_PIN_31_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(31) | 3) ++#define MT8127_PIN_31_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(31) | 4) ++#define MT8127_PIN_31_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(31) | 5) ++#define MT8127_PIN_31_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(31) | 6) ++#define MT8127_PIN_31_EINT9__FUNC_DBG_MON_B_3 (MTK_PIN_NO(31) | 7) ++ ++#define MT8127_PIN_32_EINT10__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) ++#define MT8127_PIN_32_EINT10__FUNC_CLKM5 (MTK_PIN_NO(32) | 1) ++#define MT8127_PIN_32_EINT10__FUNC_SCL2 (MTK_PIN_NO(32) | 2) ++#define MT8127_PIN_32_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(32) | 3) ++#define MT8127_PIN_32_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(32) | 4) ++#define MT8127_PIN_32_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(32) | 5) ++#define MT8127_PIN_32_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(32) | 6) ++#define MT8127_PIN_32_EINT10__FUNC_DBG_MON_B_4 (MTK_PIN_NO(32) | 7) ++ ++#define MT8127_PIN_33_KPROW0__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) ++#define MT8127_PIN_33_KPROW0__FUNC_KROW0 (MTK_PIN_NO(33) | 1) ++#define MT8127_PIN_33_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) ++#define MT8127_PIN_33_KPROW0__FUNC_DBG_MON_A_12 (MTK_PIN_NO(33) | 7) ++ ++#define MT8127_PIN_34_KPROW1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) ++#define MT8127_PIN_34_KPROW1__FUNC_KROW1 (MTK_PIN_NO(34) | 1) ++#define MT8127_PIN_34_KPROW1__FUNC_IDDIG (MTK_PIN_NO(34) | 2) ++#define MT8127_PIN_34_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(34) | 3) ++#define MT8127_PIN_34_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(34) | 4) ++#define MT8127_PIN_34_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(34) | 7) ++ ++#define MT8127_PIN_35_KPROW2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) ++#define MT8127_PIN_35_KPROW2__FUNC_KROW2 (MTK_PIN_NO(35) | 1) ++#define MT8127_PIN_35_KPROW2__FUNC_DRV_VBUS (MTK_PIN_NO(35) | 2) ++#define MT8127_PIN_35_KPROW2__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(35) | 3) ++#define MT8127_PIN_35_KPROW2__FUNC_CONN_TEST_CK (MTK_PIN_NO(35) | 4) ++#define MT8127_PIN_35_KPROW2__FUNC_DBG_MON_B_6 (MTK_PIN_NO(35) | 7) ++ ++#define MT8127_PIN_36_KPCOL0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) ++#define MT8127_PIN_36_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(36) | 1) ++#define MT8127_PIN_36_KPCOL0__FUNC_DBG_MON_A_13 (MTK_PIN_NO(36) | 7) ++ ++#define MT8127_PIN_37_KPCOL1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) ++#define MT8127_PIN_37_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(37) | 1) ++#define MT8127_PIN_37_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(37) | 7) ++ ++#define MT8127_PIN_38_KPCOL2__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) ++#define MT8127_PIN_38_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(38) | 1) ++#define MT8127_PIN_38_KPCOL2__FUNC_IDDIG (MTK_PIN_NO(38) | 2) ++#define MT8127_PIN_38_KPCOL2__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(38) | 3) ++#define MT8127_PIN_38_KPCOL2__FUNC_DBG_MON_B_8 (MTK_PIN_NO(38) | 7) ++ ++#define MT8127_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) ++#define MT8127_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1) ++#define MT8127_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) ++#define MT8127_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) ++ ++#define MT8127_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) ++#define MT8127_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1) ++#define MT8127_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) ++#define MT8127_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) ++ ++#define MT8127_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) ++#define MT8127_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1) ++#define MT8127_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) ++ ++#define MT8127_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) ++#define MT8127_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1) ++#define MT8127_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) ++ ++#define MT8127_PIN_43_EINT11__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) ++#define MT8127_PIN_43_EINT11__FUNC_CLKM4 (MTK_PIN_NO(43) | 1) ++#define MT8127_PIN_43_EINT11__FUNC_PWM2 (MTK_PIN_NO(43) | 2) ++#define MT8127_PIN_43_EINT11__FUNC_KROW3 (MTK_PIN_NO(43) | 3) ++#define MT8127_PIN_43_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(43) | 4) ++#define MT8127_PIN_43_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(43) | 5) ++#define MT8127_PIN_43_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(43) | 6) ++#define MT8127_PIN_43_EINT11__FUNC_DBG_MON_B_9 (MTK_PIN_NO(43) | 7) ++ ++#define MT8127_PIN_44_EINT12__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) ++#define MT8127_PIN_44_EINT12__FUNC_CLKM5 (MTK_PIN_NO(44) | 1) ++#define MT8127_PIN_44_EINT12__FUNC_PWM0 (MTK_PIN_NO(44) | 2) ++#define MT8127_PIN_44_EINT12__FUNC_KCOL3 (MTK_PIN_NO(44) | 3) ++#define MT8127_PIN_44_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(44) | 4) ++#define MT8127_PIN_44_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(44) | 5) ++#define MT8127_PIN_44_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(44) | 6) ++#define MT8127_PIN_44_EINT12__FUNC_DBG_MON_B_10 (MTK_PIN_NO(44) | 7) ++ ++#define MT8127_PIN_45_EINT13__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) ++#define MT8127_PIN_45_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(45) | 4) ++#define MT8127_PIN_45_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(45) | 5) ++#define MT8127_PIN_45_EINT13__FUNC_SPDIF (MTK_PIN_NO(45) | 6) ++#define MT8127_PIN_45_EINT13__FUNC_DBG_MON_B_11 (MTK_PIN_NO(45) | 7) ++ ++#define MT8127_PIN_46_EINT14__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) ++#define MT8127_PIN_46_EINT14__FUNC_DAC_DAT_OUT (MTK_PIN_NO(46) | 2) ++#define MT8127_PIN_46_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(46) | 4) ++#define MT8127_PIN_46_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(46) | 5) ++#define MT8127_PIN_46_EINT14__FUNC_NCLE (MTK_PIN_NO(46) | 6) ++#define MT8127_PIN_46_EINT14__FUNC_DBG_MON_A_14 (MTK_PIN_NO(46) | 7) ++ ++#define MT8127_PIN_47_EINT15__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) ++#define MT8127_PIN_47_EINT15__FUNC_DAC_WS (MTK_PIN_NO(47) | 2) ++#define MT8127_PIN_47_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(47) | 4) ++#define MT8127_PIN_47_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(47) | 5) ++#define MT8127_PIN_47_EINT15__FUNC_NCEB1 (MTK_PIN_NO(47) | 6) ++#define MT8127_PIN_47_EINT15__FUNC_DBG_MON_A_15 (MTK_PIN_NO(47) | 7) ++ ++#define MT8127_PIN_48_EINT16__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) ++#define MT8127_PIN_48_EINT16__FUNC_DAC_CK (MTK_PIN_NO(48) | 2) ++#define MT8127_PIN_48_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(48) | 4) ++#define MT8127_PIN_48_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(48) | 5) ++#define MT8127_PIN_48_EINT16__FUNC_NCEB0 (MTK_PIN_NO(48) | 6) ++#define MT8127_PIN_48_EINT16__FUNC_DBG_MON_A_16 (MTK_PIN_NO(48) | 7) ++ ++#define MT8127_PIN_49_EINT17__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) ++#define MT8127_PIN_49_EINT17__FUNC_UCTS0 (MTK_PIN_NO(49) | 1) ++#define MT8127_PIN_49_EINT17__FUNC_CLKM0 (MTK_PIN_NO(49) | 3) ++#define MT8127_PIN_49_EINT17__FUNC_IDDIG (MTK_PIN_NO(49) | 4) ++#define MT8127_PIN_49_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(49) | 5) ++#define MT8127_PIN_49_EINT17__FUNC_NREB (MTK_PIN_NO(49) | 6) ++#define MT8127_PIN_49_EINT17__FUNC_DBG_MON_A_17 (MTK_PIN_NO(49) | 7) ++ ++#define MT8127_PIN_50_EINT18__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) ++#define MT8127_PIN_50_EINT18__FUNC_URTS0 (MTK_PIN_NO(50) | 1) ++#define MT8127_PIN_50_EINT18__FUNC_CLKM3 (MTK_PIN_NO(50) | 2) ++#define MT8127_PIN_50_EINT18__FUNC_I2SOUT_LRCK (MTK_PIN_NO(50) | 3) ++#define MT8127_PIN_50_EINT18__FUNC_DRV_VBUS (MTK_PIN_NO(50) | 4) ++#define MT8127_PIN_50_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(50) | 5) ++#define MT8127_PIN_50_EINT18__FUNC_ADC_CK (MTK_PIN_NO(50) | 6) ++#define MT8127_PIN_50_EINT18__FUNC_DBG_MON_B_12 (MTK_PIN_NO(50) | 7) ++ ++#define MT8127_PIN_51_EINT19__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) ++#define MT8127_PIN_51_EINT19__FUNC_UCTS1 (MTK_PIN_NO(51) | 1) ++#define MT8127_PIN_51_EINT19__FUNC_I2SOUT_BCK (MTK_PIN_NO(51) | 3) ++#define MT8127_PIN_51_EINT19__FUNC_CLKM1 (MTK_PIN_NO(51) | 4) ++#define MT8127_PIN_51_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(51) | 5) ++#define MT8127_PIN_51_EINT19__FUNC_ADC_DAT_IN (MTK_PIN_NO(51) | 6) ++#define MT8127_PIN_51_EINT19__FUNC_DBG_MON_B_13 (MTK_PIN_NO(51) | 7) ++ ++#define MT8127_PIN_52_EINT20__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) ++#define MT8127_PIN_52_EINT20__FUNC_URTS1 (MTK_PIN_NO(52) | 1) ++#define MT8127_PIN_52_EINT20__FUNC_PCM_TX (MTK_PIN_NO(52) | 2) ++#define MT8127_PIN_52_EINT20__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(52) | 3) ++#define MT8127_PIN_52_EINT20__FUNC_CLKM2 (MTK_PIN_NO(52) | 4) ++#define MT8127_PIN_52_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(52) | 5) ++#define MT8127_PIN_52_EINT20__FUNC_ADC_WS (MTK_PIN_NO(52) | 6) ++#define MT8127_PIN_52_EINT20__FUNC_DBG_MON_B_14 (MTK_PIN_NO(52) | 7) ++ ++#define MT8127_PIN_53_SPI_CS__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) ++#define MT8127_PIN_53_SPI_CS__FUNC_SPI_CS (MTK_PIN_NO(53) | 1) ++#define MT8127_PIN_53_SPI_CS__FUNC_I2SIN1_DATA_IN (MTK_PIN_NO(53) | 3) ++#define MT8127_PIN_53_SPI_CS__FUNC_ADC_CK (MTK_PIN_NO(53) | 4) ++#define MT8127_PIN_53_SPI_CS__FUNC_DBG_MON_B_15 (MTK_PIN_NO(53) | 7) ++ ++#define MT8127_PIN_54_SPI_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) ++#define MT8127_PIN_54_SPI_CK__FUNC_SPI_CK (MTK_PIN_NO(54) | 1) ++#define MT8127_PIN_54_SPI_CK__FUNC_I2SIN1_LRCK (MTK_PIN_NO(54) | 3) ++#define MT8127_PIN_54_SPI_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) ++#define MT8127_PIN_54_SPI_CK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(54) | 7) ++ ++#define MT8127_PIN_55_SPI_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) ++#define MT8127_PIN_55_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(55) | 1) ++#define MT8127_PIN_55_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(55) | 2) ++#define MT8127_PIN_55_SPI_MI__FUNC_I2SIN1_BCK1 (MTK_PIN_NO(55) | 3) ++#define MT8127_PIN_55_SPI_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4) ++#define MT8127_PIN_55_SPI_MI__FUNC_DBG_MON_B_17 (MTK_PIN_NO(55) | 7) ++ ++#define MT8127_PIN_56_SPI_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) ++#define MT8127_PIN_56_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(56) | 1) ++#define MT8127_PIN_56_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(56) | 2) ++#define MT8127_PIN_56_SPI_MO__FUNC_DBG_MON_B_18 (MTK_PIN_NO(56) | 7) ++ ++#define MT8127_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) ++#define MT8127_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1) ++ ++#define MT8127_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) ++#define MT8127_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1) ++ ++#define MT8127_PIN_59_DISP_PWM__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) ++#define MT8127_PIN_59_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(59) | 1) ++#define MT8127_PIN_59_DISP_PWM__FUNC_PWM1 (MTK_PIN_NO(59) | 2) ++#define MT8127_PIN_59_DISP_PWM__FUNC_DBG_MON_A_18 (MTK_PIN_NO(59) | 7) ++ ++#define MT8127_PIN_60_WB_RSTB__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) ++#define MT8127_PIN_60_WB_RSTB__FUNC_WB_RSTB (MTK_PIN_NO(60) | 1) ++#define MT8127_PIN_60_WB_RSTB__FUNC_DBG_MON_A_19 (MTK_PIN_NO(60) | 7) ++ ++#define MT8127_PIN_61_F2W_DATA__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) ++#define MT8127_PIN_61_F2W_DATA__FUNC_F2W_DATA (MTK_PIN_NO(61) | 1) ++#define MT8127_PIN_61_F2W_DATA__FUNC_DBG_MON_A_20 (MTK_PIN_NO(61) | 7) ++ ++#define MT8127_PIN_62_F2W_CLK__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) ++#define MT8127_PIN_62_F2W_CLK__FUNC_F2W_CK (MTK_PIN_NO(62) | 1) ++#define MT8127_PIN_62_F2W_CLK__FUNC_DBG_MON_A_21 (MTK_PIN_NO(62) | 7) ++ ++#define MT8127_PIN_63_WB_SCLK__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) ++#define MT8127_PIN_63_WB_SCLK__FUNC_WB_SCLK (MTK_PIN_NO(63) | 1) ++#define MT8127_PIN_63_WB_SCLK__FUNC_DBG_MON_A_22 (MTK_PIN_NO(63) | 7) ++ ++#define MT8127_PIN_64_WB_SDATA__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) ++#define MT8127_PIN_64_WB_SDATA__FUNC_WB_SDATA (MTK_PIN_NO(64) | 1) ++#define MT8127_PIN_64_WB_SDATA__FUNC_DBG_MON_A_23 (MTK_PIN_NO(64) | 7) ++ ++#define MT8127_PIN_65_WB_SEN__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) ++#define MT8127_PIN_65_WB_SEN__FUNC_WB_SEN (MTK_PIN_NO(65) | 1) ++#define MT8127_PIN_65_WB_SEN__FUNC_DBG_MON_A_24 (MTK_PIN_NO(65) | 7) ++ ++#define MT8127_PIN_66_WB_CRTL0__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) ++#define MT8127_PIN_66_WB_CRTL0__FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1) ++#define MT8127_PIN_66_WB_CRTL0__FUNC_DFD_NTRST_XI (MTK_PIN_NO(66) | 2) ++#define MT8127_PIN_66_WB_CRTL0__FUNC_DBG_MON_A_25 (MTK_PIN_NO(66) | 7) ++ ++#define MT8127_PIN_67_WB_CRTL1__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) ++#define MT8127_PIN_67_WB_CRTL1__FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1) ++#define MT8127_PIN_67_WB_CRTL1__FUNC_DFD_TMS_XI (MTK_PIN_NO(67) | 2) ++#define MT8127_PIN_67_WB_CRTL1__FUNC_DBG_MON_A_26 (MTK_PIN_NO(67) | 7) ++ ++#define MT8127_PIN_68_WB_CRTL2__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) ++#define MT8127_PIN_68_WB_CRTL2__FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1) ++#define MT8127_PIN_68_WB_CRTL2__FUNC_DFD_TCK_XI (MTK_PIN_NO(68) | 2) ++#define MT8127_PIN_68_WB_CRTL2__FUNC_DBG_MON_A_27 (MTK_PIN_NO(68) | 7) ++ ++#define MT8127_PIN_69_WB_CRTL3__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) ++#define MT8127_PIN_69_WB_CRTL3__FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1) ++#define MT8127_PIN_69_WB_CRTL3__FUNC_DFD_TDI_XI (MTK_PIN_NO(69) | 2) ++#define MT8127_PIN_69_WB_CRTL3__FUNC_DBG_MON_A_28 (MTK_PIN_NO(69) | 7) ++ ++#define MT8127_PIN_70_WB_CRTL4__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) ++#define MT8127_PIN_70_WB_CRTL4__FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1) ++#define MT8127_PIN_70_WB_CRTL4__FUNC_DFD_TDO (MTK_PIN_NO(70) | 2) ++#define MT8127_PIN_70_WB_CRTL4__FUNC_DBG_MON_A_29 (MTK_PIN_NO(70) | 7) ++ ++#define MT8127_PIN_71_WB_CRTL5__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) ++#define MT8127_PIN_71_WB_CRTL5__FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1) ++#define MT8127_PIN_71_WB_CRTL5__FUNC_DBG_MON_A_30 (MTK_PIN_NO(71) | 7) ++ ++#define MT8127_PIN_72_I2S_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) ++#define MT8127_PIN_72_I2S_DATA_IN__FUNC_I2SIN1_DATA_IN (MTK_PIN_NO(72) | 1) ++#define MT8127_PIN_72_I2S_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 2) ++#define MT8127_PIN_72_I2S_DATA_IN__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(72) | 3) ++#define MT8127_PIN_72_I2S_DATA_IN__FUNC_DAC_DAT_OUT (MTK_PIN_NO(72) | 4) ++#define MT8127_PIN_72_I2S_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 5) ++#define MT8127_PIN_72_I2S_DATA_IN__FUNC_ADC_CK (MTK_PIN_NO(72) | 6) ++#define MT8127_PIN_72_I2S_DATA_IN__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) ++ ++#define MT8127_PIN_73_I2S_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) ++#define MT8127_PIN_73_I2S_LRCK__FUNC_I2SIN1_LRCK (MTK_PIN_NO(73) | 1) ++#define MT8127_PIN_73_I2S_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 2) ++#define MT8127_PIN_73_I2S_LRCK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(73) | 3) ++#define MT8127_PIN_73_I2S_LRCK__FUNC_DAC_WS (MTK_PIN_NO(73) | 4) ++#define MT8127_PIN_73_I2S_LRCK__FUNC_PWM3 (MTK_PIN_NO(73) | 5) ++#define MT8127_PIN_73_I2S_LRCK__FUNC_ADC_DAT_IN (MTK_PIN_NO(73) | 6) ++#define MT8127_PIN_73_I2S_LRCK__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) ++ ++#define MT8127_PIN_74_I2S_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) ++#define MT8127_PIN_74_I2S_BCK__FUNC_I2SIN1_BCK2 (MTK_PIN_NO(74) | 1) ++#define MT8127_PIN_74_I2S_BCK__FUNC_PCM_CLK1 (MTK_PIN_NO(74) | 2) ++#define MT8127_PIN_74_I2S_BCK__FUNC_I2SOUT_BCK (MTK_PIN_NO(74) | 3) ++#define MT8127_PIN_74_I2S_BCK__FUNC_DAC_CK (MTK_PIN_NO(74) | 4) ++#define MT8127_PIN_74_I2S_BCK__FUNC_PWM4 (MTK_PIN_NO(74) | 5) ++#define MT8127_PIN_74_I2S_BCK__FUNC_ADC_WS (MTK_PIN_NO(74) | 6) ++#define MT8127_PIN_74_I2S_BCK__FUNC_DBG_MON_B_21 (MTK_PIN_NO(74) | 7) ++ ++#define MT8127_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) ++#define MT8127_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1) ++ ++#define MT8127_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) ++#define MT8127_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1) ++ ++#define MT8127_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) ++#define MT8127_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1) ++#define MT8127_PIN_77_SDA2__FUNC_PWM1 (MTK_PIN_NO(77) | 2) ++ ++#define MT8127_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) ++#define MT8127_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1) ++#define MT8127_PIN_78_SCL2__FUNC_PWM2 (MTK_PIN_NO(78) | 2) ++ ++#define MT8127_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) ++#define MT8127_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1) ++#define MT8127_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2) ++ ++#define MT8127_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) ++#define MT8127_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1) ++#define MT8127_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2) ++ ++#define MT8127_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) ++#define MT8127_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1) ++#define MT8127_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2) ++ ++#define MT8127_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) ++#define MT8127_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1) ++#define MT8127_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2) ++ ++#define MT8127_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) ++#define MT8127_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1) ++#define MT8127_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) ++#define MT8127_PIN_83_LCM_RST__FUNC_DBG_MON_A_31 (MTK_PIN_NO(83) | 7) ++ ++#define MT8127_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) ++#define MT8127_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1) ++#define MT8127_PIN_84_DSI_TE__FUNC_DBG_MON_A_32 (MTK_PIN_NO(84) | 7) ++ ++#define MT8127_PIN_85_MSDC2_CMD__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) ++#define MT8127_PIN_85_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(85) | 1) ++#define MT8127_PIN_85_MSDC2_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(85) | 2) ++#define MT8127_PIN_85_MSDC2_CMD__FUNC_SDA1 (MTK_PIN_NO(85) | 3) ++#define MT8127_PIN_85_MSDC2_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(85) | 6) ++#define MT8127_PIN_85_MSDC2_CMD__FUNC_DBG_MON_B_22 (MTK_PIN_NO(85) | 7) ++ ++#define MT8127_PIN_86_MSDC2_CLK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) ++#define MT8127_PIN_86_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(86) | 1) ++#define MT8127_PIN_86_MSDC2_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(86) | 2) ++#define MT8127_PIN_86_MSDC2_CLK__FUNC_SCL1 (MTK_PIN_NO(86) | 3) ++#define MT8127_PIN_86_MSDC2_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(86) | 6) ++#define MT8127_PIN_86_MSDC2_CLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(86) | 7) ++ ++#define MT8127_PIN_87_MSDC2_DAT0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) ++#define MT8127_PIN_87_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(87) | 1) ++#define MT8127_PIN_87_MSDC2_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(87) | 2) ++#define MT8127_PIN_87_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(87) | 5) ++#define MT8127_PIN_87_MSDC2_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(87) | 6) ++#define MT8127_PIN_87_MSDC2_DAT0__FUNC_DBG_MON_B_24 (MTK_PIN_NO(87) | 7) ++ ++#define MT8127_PIN_88_MSDC2_DAT1__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) ++#define MT8127_PIN_88_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(88) | 1) ++#define MT8127_PIN_88_MSDC2_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(88) | 2) ++#define MT8127_PIN_88_MSDC2_DAT1__FUNC_PWM0 (MTK_PIN_NO(88) | 3) ++#define MT8127_PIN_88_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(88) | 5) ++#define MT8127_PIN_88_MSDC2_DAT1__FUNC_PWM1 (MTK_PIN_NO(88) | 6) ++#define MT8127_PIN_88_MSDC2_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(88) | 7) ++ ++#define MT8127_PIN_89_MSDC2_DAT2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) ++#define MT8127_PIN_89_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(89) | 1) ++#define MT8127_PIN_89_MSDC2_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(89) | 2) ++#define MT8127_PIN_89_MSDC2_DAT2__FUNC_SDA2 (MTK_PIN_NO(89) | 3) ++#define MT8127_PIN_89_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(89) | 5) ++#define MT8127_PIN_89_MSDC2_DAT2__FUNC_PWM2 (MTK_PIN_NO(89) | 6) ++#define MT8127_PIN_89_MSDC2_DAT2__FUNC_DBG_MON_B_26 (MTK_PIN_NO(89) | 7) ++ ++#define MT8127_PIN_90_MSDC2_DAT3__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) ++#define MT8127_PIN_90_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(90) | 1) ++#define MT8127_PIN_90_MSDC2_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(90) | 2) ++#define MT8127_PIN_90_MSDC2_DAT3__FUNC_SCL2 (MTK_PIN_NO(90) | 3) ++#define MT8127_PIN_90_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(90) | 4) ++#define MT8127_PIN_90_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(90) | 5) ++#define MT8127_PIN_90_MSDC2_DAT3__FUNC_PWM3 (MTK_PIN_NO(90) | 6) ++#define MT8127_PIN_90_MSDC2_DAT3__FUNC_DBG_MON_B_27 (MTK_PIN_NO(90) | 7) ++ ++#define MT8127_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0) ++#define MT8127_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1) ++ ++#define MT8127_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) ++#define MT8127_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1) ++ ++#define MT8127_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0) ++#define MT8127_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1) ++ ++#define MT8127_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0) ++#define MT8127_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1) ++ ++#define MT8127_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0) ++#define MT8127_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1) ++ ++#define MT8127_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0) ++#define MT8127_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1) ++ ++#define MT8127_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0) ++#define MT8127_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1) ++ ++#define MT8127_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0) ++#define MT8127_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1) ++ ++#define MT8127_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0) ++#define MT8127_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1) ++ ++#define MT8127_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0) ++#define MT8127_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1) ++ ++#define MT8127_PIN_101_RDN0__FUNC_GPI101 (MTK_PIN_NO(101) | 0) ++#define MT8127_PIN_101_RDN0__FUNC_RDN0 (MTK_PIN_NO(101) | 1) ++ ++#define MT8127_PIN_102_RDP0__FUNC_GPI102 (MTK_PIN_NO(102) | 0) ++#define MT8127_PIN_102_RDP0__FUNC_RDP0 (MTK_PIN_NO(102) | 1) ++ ++#define MT8127_PIN_103_RDN1__FUNC_GPI103 (MTK_PIN_NO(103) | 0) ++#define MT8127_PIN_103_RDN1__FUNC_RDN1 (MTK_PIN_NO(103) | 1) ++ ++#define MT8127_PIN_104_RDP1__FUNC_GPI104 (MTK_PIN_NO(104) | 0) ++#define MT8127_PIN_104_RDP1__FUNC_RDP1 (MTK_PIN_NO(104) | 1) ++ ++#define MT8127_PIN_105_RCN__FUNC_GPI105 (MTK_PIN_NO(105) | 0) ++#define MT8127_PIN_105_RCN__FUNC_RCN (MTK_PIN_NO(105) | 1) ++ ++#define MT8127_PIN_106_RCP__FUNC_GPI106 (MTK_PIN_NO(106) | 0) ++#define MT8127_PIN_106_RCP__FUNC_RCP (MTK_PIN_NO(106) | 1) ++ ++#define MT8127_PIN_107_RDN2__FUNC_GPI107 (MTK_PIN_NO(107) | 0) ++#define MT8127_PIN_107_RDN2__FUNC_RDN2 (MTK_PIN_NO(107) | 1) ++#define MT8127_PIN_107_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(107) | 2) ++ ++#define MT8127_PIN_108_RDP2__FUNC_GPI108 (MTK_PIN_NO(108) | 0) ++#define MT8127_PIN_108_RDP2__FUNC_RDP2 (MTK_PIN_NO(108) | 1) ++#define MT8127_PIN_108_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(108) | 2) ++ ++#define MT8127_PIN_109_RDN3__FUNC_GPI109 (MTK_PIN_NO(109) | 0) ++#define MT8127_PIN_109_RDN3__FUNC_RDN3 (MTK_PIN_NO(109) | 1) ++#define MT8127_PIN_109_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(109) | 2) ++ ++#define MT8127_PIN_110_RDP3__FUNC_GPI110 (MTK_PIN_NO(110) | 0) ++#define MT8127_PIN_110_RDP3__FUNC_RDP3 (MTK_PIN_NO(110) | 1) ++#define MT8127_PIN_110_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(110) | 2) ++ ++#define MT8127_PIN_111_RCN_A__FUNC_GPI111 (MTK_PIN_NO(111) | 0) ++#define MT8127_PIN_111_RCN_A__FUNC_RCN_A (MTK_PIN_NO(111) | 1) ++#define MT8127_PIN_111_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(111) | 2) ++ ++#define MT8127_PIN_112_RCP_A__FUNC_GPI112 (MTK_PIN_NO(112) | 0) ++#define MT8127_PIN_112_RCP_A__FUNC_RCP_A (MTK_PIN_NO(112) | 1) ++#define MT8127_PIN_112_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(112) | 2) ++ ++#define MT8127_PIN_113_RDN1_A__FUNC_GPI113 (MTK_PIN_NO(113) | 0) ++#define MT8127_PIN_113_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(113) | 1) ++#define MT8127_PIN_113_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(113) | 2) ++#define MT8127_PIN_113_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(113) | 3) ++ ++#define MT8127_PIN_114_RDP1_A__FUNC_GPI114 (MTK_PIN_NO(114) | 0) ++#define MT8127_PIN_114_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(114) | 1) ++#define MT8127_PIN_114_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(114) | 2) ++#define MT8127_PIN_114_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(114) | 3) ++ ++#define MT8127_PIN_115_RDN0_A__FUNC_GPI115 (MTK_PIN_NO(115) | 0) ++#define MT8127_PIN_115_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(115) | 1) ++#define MT8127_PIN_115_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(115) | 2) ++ ++#define MT8127_PIN_116_RDP0_A__FUNC_GPI116 (MTK_PIN_NO(116) | 0) ++#define MT8127_PIN_116_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(116) | 1) ++#define MT8127_PIN_116_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(116) | 2) ++ ++#define MT8127_PIN_117_CMDAT0__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) ++#define MT8127_PIN_117_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(117) | 1) ++#define MT8127_PIN_117_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(117) | 2) ++#define MT8127_PIN_117_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(117) | 3) ++#define MT8127_PIN_117_CMDAT0__FUNC_DBG_MON_B_28 (MTK_PIN_NO(117) | 7) ++ ++#define MT8127_PIN_118_CMDAT1__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) ++#define MT8127_PIN_118_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(118) | 1) ++#define MT8127_PIN_118_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(118) | 2) ++#define MT8127_PIN_118_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(118) | 3) ++#define MT8127_PIN_118_CMDAT1__FUNC_DBG_MON_B_29 (MTK_PIN_NO(118) | 7) ++ ++#define MT8127_PIN_119_CMMCLK__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) ++#define MT8127_PIN_119_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(119) | 1) ++#define MT8127_PIN_119_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(119) | 3) ++#define MT8127_PIN_119_CMMCLK__FUNC_DBG_MON_B_30 (MTK_PIN_NO(119) | 7) ++ ++#define MT8127_PIN_120_CMPCLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) ++#define MT8127_PIN_120_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(120) | 1) ++#define MT8127_PIN_120_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(120) | 2) ++#define MT8127_PIN_120_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(120) | 3) ++#define MT8127_PIN_120_CMPCLK__FUNC_DBG_MON_B_31 (MTK_PIN_NO(120) | 7) ++ ++#define MT8127_PIN_121_MSDC1_CMD__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) ++#define MT8127_PIN_121_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(121) | 1) ++ ++#define MT8127_PIN_122_MSDC1_CLK__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) ++#define MT8127_PIN_122_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(122) | 1) ++ ++#define MT8127_PIN_123_MSDC1_DAT0__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) ++#define MT8127_PIN_123_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(123) | 1) ++ ++#define MT8127_PIN_124_MSDC1_DAT1__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) ++#define MT8127_PIN_124_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(124) | 1) ++ ++#define MT8127_PIN_125_MSDC1_DAT2__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) ++#define MT8127_PIN_125_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(125) | 1) ++ ++#define MT8127_PIN_126_MSDC1_DAT3__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) ++#define MT8127_PIN_126_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(126) | 1) ++ ++#define MT8127_PIN_127_MSDC0_DAT7__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) ++#define MT8127_PIN_127_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(127) | 1) ++#define MT8127_PIN_127_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(127) | 4) ++ ++#define MT8127_PIN_128_MSDC0_DAT6__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) ++#define MT8127_PIN_128_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(128) | 1) ++#define MT8127_PIN_128_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(128) | 4) ++ ++#define MT8127_PIN_129_MSDC0_DAT5__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) ++#define MT8127_PIN_129_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(129) | 1) ++#define MT8127_PIN_129_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(129) | 4) ++ ++#define MT8127_PIN_130_MSDC0_DAT4__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) ++#define MT8127_PIN_130_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(130) | 1) ++#define MT8127_PIN_130_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(130) | 4) ++ ++#define MT8127_PIN_131_MSDC0_RSTB__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) ++#define MT8127_PIN_131_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(131) | 1) ++#define MT8127_PIN_131_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(131) | 4) ++ ++#define MT8127_PIN_132_MSDC0_CMD__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) ++#define MT8127_PIN_132_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(132) | 1) ++#define MT8127_PIN_132_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(132) | 4) ++ ++#define MT8127_PIN_133_MSDC0_CLK__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) ++#define MT8127_PIN_133_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(133) | 1) ++#define MT8127_PIN_133_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(133) | 4) ++ ++#define MT8127_PIN_134_MSDC0_DAT3__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) ++#define MT8127_PIN_134_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(134) | 1) ++#define MT8127_PIN_134_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(134) | 4) ++ ++#define MT8127_PIN_135_MSDC0_DAT2__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) ++#define MT8127_PIN_135_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(135) | 1) ++#define MT8127_PIN_135_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(135) | 4) ++ ++#define MT8127_PIN_136_MSDC0_DAT1__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) ++#define MT8127_PIN_136_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(136) | 1) ++#define MT8127_PIN_136_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(136) | 4) ++ ++#define MT8127_PIN_137_MSDC0_DAT0__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) ++#define MT8127_PIN_137_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(137) | 1) ++#define MT8127_PIN_137_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(137) | 4) ++#define MT8127_PIN_137_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(137) | 5) ++ ++#define MT8127_PIN_138_CEC__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) ++#define MT8127_PIN_138_CEC__FUNC_CEC (MTK_PIN_NO(138) | 1) ++ ++#define MT8127_PIN_139_HTPLG__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) ++#define MT8127_PIN_139_HTPLG__FUNC_HTPLG (MTK_PIN_NO(139) | 1) ++ ++#define MT8127_PIN_140_HDMISCK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) ++#define MT8127_PIN_140_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(140) | 1) ++ ++#define MT8127_PIN_141_HDMISD__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) ++#define MT8127_PIN_141_HDMISD__FUNC_HDMISD (MTK_PIN_NO(141) | 1) ++ ++#define MT8127_PIN_142_EINT21__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) ++#define MT8127_PIN_142_EINT21__FUNC_NRNB (MTK_PIN_NO(142) | 1) ++#define MT8127_PIN_142_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(142) | 2) ++#define MT8127_PIN_142_EINT21__FUNC_DBG_MON_B_32 (MTK_PIN_NO(142) | 7) ++ ++#endif /* __DTS_MT8127_PINFUNC_H */ +diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi +index 7c2090d..1d429ed 100644 +--- a/arch/arm/boot/dts/mt8127.dtsi ++++ b/arch/arm/boot/dts/mt8127.dtsi +@@ -14,6 +14,7 @@ + + #include + #include ++#include "mt8127-pinfunc.h" + #include "skeleton64.dtsi" + + / { +@@ -94,6 +95,27 @@ + compatible = "simple-bus"; + ranges; + ++ /* ++ * Pinctrl access register at 0x10005000 through regmap. ++ * Register 0x1000b000 is used by EINT. ++ */ ++ pio: pinctrl@10005000 { ++ compatible = "mediatek,mt8127-pinctrl"; ++ reg = <0 0x1000b000 0 0x1000>; ++ mediatek,pctl-regmap = <&syscfg_pctl_a>; ++ pins-are-numbered; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupts = ; ++ }; ++ ++ syscfg_pctl_a: syscfg_pctl_a@10005000 { ++ compatible = "mediatek,mt8127-pctl-a-syscfg", "syscon"; ++ reg = <0 0x10005000 0 0x1000>; ++ }; ++ + timer: timer@10008000 { + compatible = "mediatek,mt8127-timer", + "mediatek,mt6577-timer"; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0057-thermal-oops.patch b/target/linux/mediatek/patches/0057-thermal-oops.patch new file mode 100644 index 0000000..e7684f1 --- /dev/null +++ b/target/linux/mediatek/patches/0057-thermal-oops.patch @@ -0,0 +1,27 @@ +From d1a856804b84affae30274b391b3c685e901093f Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 11:35:29 +0200 +Subject: [PATCH 57/76] thermal oops + +Signed-off-by: John Crispin +--- + drivers/thermal/mtk_thermal.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c +index 27aab12..5fdcbf6 100644 +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -394,7 +394,8 @@ static irqreturn_t mtk_thermal_irq(int irq, void *dev_id) + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + if (!(irqstat & (1 << i))) +- mtk_thermal_irq_bank(&mt->banks[i]); ++ if (!IS_ERR(mt->banks[i].tz)) ++ mtk_thermal_irq_bank(&mt->banks[i]); + } + + return IRQ_HANDLED; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0058-dont-disable-clocks.patch b/target/linux/mediatek/patches/0058-dont-disable-clocks.patch new file mode 100644 index 0000000..e30d5dc --- /dev/null +++ b/target/linux/mediatek/patches/0058-dont-disable-clocks.patch @@ -0,0 +1,25 @@ +From b1c69201563ae3ff878abf4ba192e73031de8653 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Tue, 23 Jun 2015 23:46:00 +0200 +Subject: [PATCH 58/76] dont disable clocks + +--- + drivers/clk/clk.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c +index 5b0f418..360e6e4 100644 +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -541,7 +541,7 @@ unlock_out: + clk_enable_unlock(flags); + } + +-static bool clk_ignore_unused; ++static bool clk_ignore_unused = true; + static int __init clk_ignore_unused_setup(char *__unused) + { + clk_ignore_unused = true; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0059-arm-mediatek-basic-mt6323-pmic-support.patch b/target/linux/mediatek/patches/0059-arm-mediatek-basic-mt6323-pmic-support.patch new file mode 100644 index 0000000..ca28251 --- /dev/null +++ b/target/linux/mediatek/patches/0059-arm-mediatek-basic-mt6323-pmic-support.patch @@ -0,0 +1,1099 @@ +From 7f157285f2a01921917e0eed79b5d8cf734f5d27 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 24 Jun 2015 15:24:45 +0200 +Subject: [PATCH 59/76] arm: mediatek: basic mt6323 pmic support + +Signed-off-by: John Crispin +--- + drivers/mfd/Kconfig | 10 + + drivers/mfd/Makefile | 1 + + drivers/mfd/mt6323-core.c | 230 +++++++++++++++++++++ + drivers/regulator/Kconfig | 9 + + drivers/regulator/Makefile | 1 + + drivers/regulator/mt6323-regulator.c | 332 +++++++++++++++++++++++++++++++ + include/linux/mfd/mt6323/core.h | 64 ++++++ + include/linux/mfd/mt6323/registers.h | 362 ++++++++++++++++++++++++++++++++++ + 8 files changed, 1009 insertions(+) + create mode 100644 drivers/mfd/mt6323-core.c + create mode 100644 drivers/regulator/mt6323-regulator.c + create mode 100644 include/linux/mfd/mt6323/core.h + create mode 100644 include/linux/mfd/mt6323/registers.h + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index d5ad04d..ff2c14e 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -529,6 +529,16 @@ config MFD_MAX8998 + additional drivers must be enabled in order to use the functionality + of the device. + ++config MFD_MT6323 ++ tristate "MediaTek MT6323 PMIC Support" ++ select MFD_CORE ++ select IRQ_DOMAIN ++ help ++ Say yes here to add support for MediaTek MT6323 PMIC. This is ++ a Power Management IC. This driver provides common support for ++ accessing the device; additional drivers must be enabled in order ++ to use the functionality of the device. ++ + config MFD_MT6397 + tristate "MediaTek MT6397 PMIC Support" + select MFD_CORE +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index 0e5cfeb..6e91123 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -184,4 +184,5 @@ obj-$(CONFIG_MFD_SKY81452) += sky81452.o + + intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o + obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o ++obj-$(CONFIG_MFD_MT6323) += mt6323-core.o + obj-$(CONFIG_MFD_MT6397) += mt6397-core.o +diff --git a/drivers/mfd/mt6323-core.c b/drivers/mfd/mt6323-core.c +new file mode 100644 +index 0000000..012c620 +--- /dev/null ++++ b/drivers/mfd/mt6323-core.c +@@ -0,0 +1,230 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Flora Fu, MediaTek ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static const struct mfd_cell mt6397_devs[] = { ++ { ++ .name = "mt6397-rtc", ++ .of_compatible = "mediatek,mt6397-rtc", ++ }, { ++ .name = "mt6397-regulator", ++ .of_compatible = "mediatek,mt6397-regulator", ++ }, { ++ .name = "mt6397-codec", ++ .of_compatible = "mediatek,mt6397-codec", ++ }, { ++ .name = "mt6397-clk", ++ .of_compatible = "mediatek,mt6397-clk", ++ }, { ++ .name = "mediatek-mt6397-pinctrl", ++ .of_compatible = "mediatek,mt6397-pinctrl", ++ }, ++}; ++ ++static void mt6397_irq_lock(struct irq_data *data) ++{ ++ struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); ++ ++ mutex_lock(&mt6397->irqlock); ++} ++ ++static void mt6397_irq_sync_unlock(struct irq_data *data) ++{ ++ struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); ++ ++ regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]); ++ regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]); ++ ++ mutex_unlock(&mt6397->irqlock); ++} ++ ++static void mt6397_irq_disable(struct irq_data *data) ++{ ++ struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); ++ int shift = data->hwirq & 0xf; ++ int reg = data->hwirq >> 4; ++ ++ mt6397->irq_masks_cur[reg] &= ~BIT(shift); ++} ++ ++static void mt6397_irq_enable(struct irq_data *data) ++{ ++ struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); ++ int shift = data->hwirq & 0xf; ++ int reg = data->hwirq >> 4; ++ ++ mt6397->irq_masks_cur[reg] |= BIT(shift); ++} ++ ++static struct irq_chip mt6397_irq_chip = { ++ .name = "mt6397-irq", ++ .irq_bus_lock = mt6397_irq_lock, ++ .irq_bus_sync_unlock = mt6397_irq_sync_unlock, ++ .irq_enable = mt6397_irq_enable, ++ .irq_disable = mt6397_irq_disable, ++}; ++ ++static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg, ++ int irqbase) ++{ ++ unsigned int status; ++ int i, irq, ret; ++ ++ ret = regmap_read(mt6397->regmap, reg, &status); ++ if (ret) { ++ dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret); ++ return; ++ } ++ ++ for (i = 0; i < 16; i++) { ++ if (status & BIT(i)) { ++ irq = irq_find_mapping(mt6397->irq_domain, irqbase + i); ++ if (irq) ++ handle_nested_irq(irq); ++ } ++ } ++ ++ regmap_write(mt6397->regmap, reg, status); ++} ++ ++static irqreturn_t mt6397_irq_thread(int irq, void *data) ++{ ++ struct mt6397_chip *mt6397 = data; ++ ++ mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0); ++ mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16); ++ ++ return IRQ_HANDLED; ++} ++ ++static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq, ++ irq_hw_number_t hw) ++{ ++ struct mt6397_chip *mt6397 = d->host_data; ++ ++ irq_set_chip_data(irq, mt6397); ++ irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq); ++ irq_set_nested_thread(irq, 1); ++#ifdef CONFIG_ARM ++ set_irq_flags(irq, IRQF_VALID); ++#else ++ irq_set_noprobe(irq); ++#endif ++ ++ return 0; ++} ++ ++static struct irq_domain_ops mt6397_irq_domain_ops = { ++ .map = mt6397_irq_domain_map, ++}; ++ ++static int mt6397_irq_init(struct mt6397_chip *mt6397) ++{ ++ int ret; ++ ++ mutex_init(&mt6397->irqlock); ++ ++ /* Mask all interrupt sources */ ++ regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0); ++ regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0); ++ ++ mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node, ++ MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397); ++ if (!mt6397->irq_domain) { ++ dev_err(mt6397->dev, "could not create irq domain\n"); ++ return -ENOMEM; ++ } ++ ++ ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL, ++ mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397); ++ if (ret) { ++ dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n", ++ mt6397->irq, ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int mt6397_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct mt6397_chip *mt6397; ++ ++ mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL); ++ if (!mt6397) ++ return -ENOMEM; ++ ++ mt6397->dev = &pdev->dev; ++ /* ++ * mt6397 MFD is child device of soc pmic wrapper. ++ * Regmap is set from its parent. ++ */ ++ mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL); ++ if (!mt6397->regmap) ++ return -ENODEV; ++ ++ platform_set_drvdata(pdev, mt6397); ++ ++ mt6397->irq = platform_get_irq(pdev, 0); ++ if (mt6397->irq > 0) { ++ ret = mt6397_irq_init(mt6397); ++ if (ret) ++ return ret; ++ } ++ ++ ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs, ++ ARRAY_SIZE(mt6397_devs), NULL, 0, NULL); ++ if (ret) ++ dev_err(&pdev->dev, "failed to add child devices: %d\n", ret); ++ ++ return ret; ++} ++ ++static int mt6397_remove(struct platform_device *pdev) ++{ ++ mfd_remove_devices(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id mt6397_of_match[] = { ++ { .compatible = "mediatek,mt6397" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, mt6397_of_match); ++ ++static struct platform_driver mt6397_driver = { ++ .probe = mt6397_probe, ++ .remove = mt6397_remove, ++ .driver = { ++ .name = "mt6397", ++ .of_match_table = of_match_ptr(mt6397_of_match), ++ }, ++}; ++ ++module_platform_driver(mt6397_driver); ++ ++MODULE_AUTHOR("Flora Fu, MediaTek"); ++MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:mt6397"); +diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig +index a6f116a..336d4c6 100644 +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -441,6 +441,15 @@ config REGULATOR_MC13892 + Say y here to support the regulators found on the Freescale MC13892 + PMIC. + ++config REGULATOR_MT6323 ++ tristate "MediaTek MT6323 PMIC" ++ depends on MFD_MT6323 ++ help ++ Say y here to select this option to enable the power regulator of ++ MediaTek MT6323 PMIC. ++ This driver supports the control of different power rails of device ++ through regulator interface. ++ + config REGULATOR_MT6397 + tristate "MediaTek MT6397 PMIC" + depends on MFD_MT6397 +diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile +index 2c4da15..ac6a9da 100644 +--- a/drivers/regulator/Makefile ++++ b/drivers/regulator/Makefile +@@ -59,6 +59,7 @@ obj-$(CONFIG_REGULATOR_MAX77843) += max77843.o + obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o + obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o + obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o ++obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o + obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o + obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o + obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o +diff --git a/drivers/regulator/mt6323-regulator.c b/drivers/regulator/mt6323-regulator.c +new file mode 100644 +index 0000000..a5b2f47 +--- /dev/null ++++ b/drivers/regulator/mt6323-regulator.c +@@ -0,0 +1,332 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Flora Fu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * MT6397 regulators' information ++ * ++ * @desc: standard fields of regulator description. ++ * @qi: Mask for query enable signal status of regulators ++ * @vselon_reg: Register sections for hardware control mode of bucks ++ * @vselctrl_reg: Register for controlling the buck control mode. ++ * @vselctrl_mask: Mask for query buck's voltage control mode. ++ */ ++struct mt6397_regulator_info { ++ struct regulator_desc desc; ++ u32 qi; ++ u32 vselon_reg; ++ u32 vselctrl_reg; ++ u32 vselctrl_mask; ++}; ++ ++#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ ++ vosel, vosel_mask, voselon, vosel_ctrl) \ ++[MT6397_ID_##vreg] = { \ ++ .desc = { \ ++ .name = #vreg, \ ++ .of_match = of_match_ptr(match), \ ++ .ops = &mt6397_volt_range_ops, \ ++ .type = REGULATOR_VOLTAGE, \ ++ .id = MT6397_ID_##vreg, \ ++ .owner = THIS_MODULE, \ ++ .n_voltages = (max - min)/step + 1, \ ++ .linear_ranges = volt_ranges, \ ++ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ ++ .vsel_reg = vosel, \ ++ .vsel_mask = vosel_mask, \ ++ .enable_reg = enreg, \ ++ .enable_mask = BIT(0), \ ++ }, \ ++ .qi = BIT(13), \ ++ .vselon_reg = voselon, \ ++ .vselctrl_reg = vosel_ctrl, \ ++ .vselctrl_mask = BIT(1), \ ++} ++ ++#define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ ++ vosel_mask) \ ++[MT6397_ID_##vreg] = { \ ++ .desc = { \ ++ .name = #vreg, \ ++ .of_match = of_match_ptr(match), \ ++ .ops = &mt6397_volt_table_ops, \ ++ .type = REGULATOR_VOLTAGE, \ ++ .id = MT6397_ID_##vreg, \ ++ .owner = THIS_MODULE, \ ++ .n_voltages = ARRAY_SIZE(ldo_volt_table), \ ++ .volt_table = ldo_volt_table, \ ++ .vsel_reg = vosel, \ ++ .vsel_mask = vosel_mask, \ ++ .enable_reg = enreg, \ ++ .enable_mask = BIT(enbit), \ ++ }, \ ++ .qi = BIT(15), \ ++} ++ ++#define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \ ++[MT6397_ID_##vreg] = { \ ++ .desc = { \ ++ .name = #vreg, \ ++ .of_match = of_match_ptr(match), \ ++ .ops = &mt6397_volt_fixed_ops, \ ++ .type = REGULATOR_VOLTAGE, \ ++ .id = MT6397_ID_##vreg, \ ++ .owner = THIS_MODULE, \ ++ .n_voltages = 1, \ ++ .enable_reg = enreg, \ ++ .enable_mask = BIT(enbit), \ ++ .min_uV = volt, \ ++ }, \ ++ .qi = BIT(15), \ ++} ++ ++static const struct regulator_linear_range buck_volt_range1[] = { ++ REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), ++}; ++ ++static const struct regulator_linear_range buck_volt_range2[] = { ++ REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250), ++}; ++ ++static const struct regulator_linear_range buck_volt_range3[] = { ++ REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000), ++}; ++ ++static const u32 ldo_volt_table1[] = { ++ 1500000, 1800000, 2500000, 2800000, ++}; ++ ++static const u32 ldo_volt_table2[] = { ++ 1800000, 3300000, ++}; ++ ++static const u32 ldo_volt_table3[] = { ++ 3000000, 3300000, ++}; ++ ++static const u32 ldo_volt_table4[] = { ++ 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, ++}; ++ ++static const u32 ldo_volt_table5[] = { ++ 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, ++}; ++ ++static const u32 ldo_volt_table5_v2[] = { ++ 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, ++}; ++ ++static const u32 ldo_volt_table6[] = { ++ 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000, ++}; ++ ++static const u32 ldo_volt_table7[] = { ++ 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000, ++}; ++ ++static int mt6397_get_status(struct regulator_dev *rdev) ++{ ++ int ret; ++ u32 regval; ++ struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); ++ ++ ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); ++ if (ret != 0) { ++ dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); ++ return ret; ++ } ++ ++ return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; ++} ++ ++static struct regulator_ops mt6397_volt_range_ops = { ++ .list_voltage = regulator_list_voltage_linear_range, ++ .map_voltage = regulator_map_voltage_linear_range, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .get_status = mt6397_get_status, ++}; ++ ++static struct regulator_ops mt6397_volt_table_ops = { ++ .list_voltage = regulator_list_voltage_table, ++ .map_voltage = regulator_map_voltage_iterate, ++ .set_voltage_sel = regulator_set_voltage_sel_regmap, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .set_voltage_time_sel = regulator_set_voltage_time_sel, ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .get_status = mt6397_get_status, ++}; ++ ++static struct regulator_ops mt6397_volt_fixed_ops = { ++ .list_voltage = regulator_list_voltage_linear, ++ .enable = regulator_enable_regmap, ++ .disable = regulator_disable_regmap, ++ .is_enabled = regulator_is_enabled_regmap, ++ .get_status = mt6397_get_status, ++}; ++ ++/* The array is indexed by id(MT6397_ID_XXX) */ ++static struct mt6397_regulator_info mt6397_regulators[] = { ++ MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250, ++ buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f, ++ MT6397_VCA15_CON10, MT6397_VCA15_CON5), ++ MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250, ++ buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f, ++ MT6397_VPCA7_CON10, MT6397_VPCA7_CON5), ++ MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250, ++ buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9, ++ 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5), ++ MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250, ++ buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9, ++ 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5), ++ MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, ++ buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f, ++ MT6397_VCORE_CON10, MT6397_VCORE_CON5), ++ MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1, ++ MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f, ++ MT6397_VGPU_CON10, MT6397_VGPU_CON5), ++ MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2, ++ MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f, ++ MT6397_VDRM_CON10, MT6397_VDRM_CON5), ++ MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000, ++ buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f, ++ MT6397_VIO18_CON10, MT6397_VIO18_CON5), ++ MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000), ++ MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000), ++ MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1, ++ MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0), ++ MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000), ++ MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000), ++ MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2, ++ MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10), ++ MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3, ++ MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80), ++ MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3, ++ MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10), ++ MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4, ++ MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0), ++ MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5, ++ MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0), ++ MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5, ++ MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0), ++ MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5, ++ MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0), ++ MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6, ++ MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0), ++ MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5, ++ MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0), ++ MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7, ++ MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00), ++}; ++ ++static int mt6397_set_buck_vosel_reg(struct platform_device *pdev) ++{ ++ struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); ++ int i; ++ u32 regval; ++ ++ for (i = 0; i < MT6397_MAX_REGULATOR; i++) { ++ if (mt6397_regulators[i].vselctrl_reg) { ++ if (regmap_read(mt6397->regmap, ++ mt6397_regulators[i].vselctrl_reg, ++ ®val) < 0) { ++ dev_err(&pdev->dev, ++ "Failed to read buck ctrl\n"); ++ return -EIO; ++ } ++ ++ if (regval & mt6397_regulators[i].vselctrl_mask) { ++ mt6397_regulators[i].desc.vsel_reg = ++ mt6397_regulators[i].vselon_reg; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++static int mt6397_regulator_probe(struct platform_device *pdev) ++{ ++ struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); ++ struct regulator_config config = {}; ++ struct regulator_dev *rdev; ++ int i; ++ u32 reg_value, version; ++ ++ /* Query buck controller to select activated voltage register part */ ++ if (mt6397_set_buck_vosel_reg(pdev)) ++ return -EIO; ++ ++ /* Read PMIC chip revision to update constraints and voltage table */ ++ if (regmap_read(mt6397->regmap, MT6397_CID, ®_value) < 0) { ++ dev_err(&pdev->dev, "Failed to read Chip ID\n"); ++ return -EIO; ++ } ++ dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); ++ ++ version = (reg_value & 0xFF); ++ switch (version) { ++ case MT6397_REGULATOR_ID91: ++ mt6397_regulators[MT6397_ID_VGP2].desc.volt_table = ++ ldo_volt_table5_v2; ++ break; ++ default: ++ break; ++ } ++ ++ for (i = 0; i < MT6397_MAX_REGULATOR; i++) { ++ config.dev = &pdev->dev; ++ config.driver_data = &mt6397_regulators[i]; ++ config.regmap = mt6397->regmap; ++ rdev = devm_regulator_register(&pdev->dev, ++ &mt6397_regulators[i].desc, &config); ++ if (IS_ERR(rdev)) { ++ dev_err(&pdev->dev, "failed to register %s\n", ++ mt6397_regulators[i].desc.name); ++ return PTR_ERR(rdev); ++ } ++ } ++ ++ return 0; ++} ++ ++static struct platform_driver mt6397_regulator_driver = { ++ .driver = { ++ .name = "mt6397-regulator", ++ }, ++ .probe = mt6397_regulator_probe, ++}; ++ ++module_platform_driver(mt6397_regulator_driver); ++ ++MODULE_AUTHOR("Flora Fu "); ++MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:mt6397-regulator"); +diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h +new file mode 100644 +index 0000000..cf5265b +--- /dev/null ++++ b/include/linux/mfd/mt6323/core.h +@@ -0,0 +1,64 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Flora Fu, MediaTek ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MFD_MT6397_CORE_H__ ++#define __MFD_MT6397_CORE_H__ ++ ++enum mt6397_irq_numbers { ++ MT6397_IRQ_SPKL_AB = 0, ++ MT6397_IRQ_SPKR_AB, ++ MT6397_IRQ_SPKL, ++ MT6397_IRQ_SPKR, ++ MT6397_IRQ_BAT_L, ++ MT6397_IRQ_BAT_H, ++ MT6397_IRQ_FG_BAT_L, ++ MT6397_IRQ_FG_BAT_H, ++ MT6397_IRQ_WATCHDOG, ++ MT6397_IRQ_PWRKEY, ++ MT6397_IRQ_THR_L, ++ MT6397_IRQ_THR_H, ++ MT6397_IRQ_VBATON_UNDET, ++ MT6397_IRQ_BVALID_DET, ++ MT6397_IRQ_CHRDET, ++ MT6397_IRQ_OV, ++ MT6397_IRQ_LDO, ++ MT6397_IRQ_HOMEKEY, ++ MT6397_IRQ_ACCDET, ++ MT6397_IRQ_AUDIO, ++ MT6397_IRQ_RTC, ++ MT6397_IRQ_PWRKEY_RSTB, ++ MT6397_IRQ_HDMI_SIFM, ++ MT6397_IRQ_HDMI_CEC, ++ MT6397_IRQ_VCA15, ++ MT6397_IRQ_VSRMCA15, ++ MT6397_IRQ_VCORE, ++ MT6397_IRQ_VGPU, ++ MT6397_IRQ_VIO18, ++ MT6397_IRQ_VPCA7, ++ MT6397_IRQ_VSRMCA7, ++ MT6397_IRQ_VDRM, ++ MT6397_IRQ_NR, ++}; ++ ++struct mt6397_chip { ++ struct device *dev; ++ struct regmap *regmap; ++ int irq; ++ struct irq_domain *irq_domain; ++ struct mutex irqlock; ++ u16 irq_masks_cur[2]; ++ u16 irq_masks_cache[2]; ++}; ++ ++#endif /* __MFD_MT6397_CORE_H__ */ +diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h +new file mode 100644 +index 0000000..f23a0a6 +--- /dev/null ++++ b/include/linux/mfd/mt6323/registers.h +@@ -0,0 +1,362 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Flora Fu, MediaTek ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MFD_MT6397_REGISTERS_H__ ++#define __MFD_MT6397_REGISTERS_H__ ++ ++/* PMIC Registers */ ++#define MT6397_CID 0x0100 ++#define MT6397_TOP_CKPDN 0x0102 ++#define MT6397_TOP_CKPDN_SET 0x0104 ++#define MT6397_TOP_CKPDN_CLR 0x0106 ++#define MT6397_TOP_CKPDN2 0x0108 ++#define MT6397_TOP_CKPDN2_SET 0x010A ++#define MT6397_TOP_CKPDN2_CLR 0x010C ++#define MT6397_TOP_GPIO_CKPDN 0x010E ++#define MT6397_TOP_RST_CON 0x0114 ++#define MT6397_WRP_CKPDN 0x011A ++#define MT6397_WRP_RST_CON 0x0120 ++#define MT6397_TOP_RST_MISC 0x0126 ++#define MT6397_TOP_CKCON1 0x0128 ++#define MT6397_TOP_CKCON2 0x012A ++#define MT6397_TOP_CKTST1 0x012C ++#define MT6397_TOP_CKTST2 0x012E ++#define MT6397_OC_DEG_EN 0x0130 ++#define MT6397_OC_CTL0 0x0132 ++#define MT6397_OC_CTL1 0x0134 ++#define MT6397_OC_CTL2 0x0136 ++#define MT6397_INT_RSV 0x0138 ++#define MT6397_TEST_CON0 0x013A ++#define MT6397_TEST_CON1 0x013C ++#define MT6397_STATUS0 0x013E ++#define MT6397_STATUS1 0x0140 ++#define MT6397_PGSTATUS 0x0142 ++#define MT6397_CHRSTATUS 0x0144 ++#define MT6397_OCSTATUS0 0x0146 ++#define MT6397_OCSTATUS1 0x0148 ++#define MT6397_OCSTATUS2 0x014A ++#define MT6397_HDMI_PAD_IE 0x014C ++#define MT6397_TEST_OUT_L 0x014E ++#define MT6397_TEST_OUT_H 0x0150 ++#define MT6397_TDSEL_CON 0x0152 ++#define MT6397_RDSEL_CON 0x0154 ++#define MT6397_GPIO_SMT_CON0 0x0156 ++#define MT6397_GPIO_SMT_CON1 0x0158 ++#define MT6397_GPIO_SMT_CON2 0x015A ++#define MT6397_GPIO_SMT_CON3 0x015C ++#define MT6397_DRV_CON0 0x015E ++#define MT6397_DRV_CON1 0x0160 ++#define MT6397_DRV_CON2 0x0162 ++#define MT6397_DRV_CON3 0x0164 ++#define MT6397_DRV_CON4 0x0166 ++#define MT6397_DRV_CON5 0x0168 ++#define MT6397_DRV_CON6 0x016A ++#define MT6397_DRV_CON7 0x016C ++#define MT6397_DRV_CON8 0x016E ++#define MT6397_DRV_CON9 0x0170 ++#define MT6397_DRV_CON10 0x0172 ++#define MT6397_DRV_CON11 0x0174 ++#define MT6397_DRV_CON12 0x0176 ++#define MT6397_INT_CON0 0x0178 ++#define MT6397_INT_CON1 0x017E ++#define MT6397_INT_STATUS0 0x0184 ++#define MT6397_INT_STATUS1 0x0186 ++#define MT6397_FQMTR_CON0 0x0188 ++#define MT6397_FQMTR_CON1 0x018A ++#define MT6397_FQMTR_CON2 0x018C ++#define MT6397_EFUSE_DOUT_0_15 0x01C4 ++#define MT6397_EFUSE_DOUT_16_31 0x01C6 ++#define MT6397_EFUSE_DOUT_32_47 0x01C8 ++#define MT6397_EFUSE_DOUT_48_63 0x01CA ++#define MT6397_SPI_CON 0x01CC ++#define MT6397_TOP_CKPDN3 0x01CE ++#define MT6397_TOP_CKCON3 0x01D4 ++#define MT6397_EFUSE_DOUT_64_79 0x01D6 ++#define MT6397_EFUSE_DOUT_80_95 0x01D8 ++#define MT6397_EFUSE_DOUT_96_111 0x01DA ++#define MT6397_EFUSE_DOUT_112_127 0x01DC ++#define MT6397_EFUSE_DOUT_128_143 0x01DE ++#define MT6397_EFUSE_DOUT_144_159 0x01E0 ++#define MT6397_EFUSE_DOUT_160_175 0x01E2 ++#define MT6397_EFUSE_DOUT_176_191 0x01E4 ++#define MT6397_EFUSE_DOUT_192_207 0x01E6 ++#define MT6397_EFUSE_DOUT_208_223 0x01E8 ++#define MT6397_EFUSE_DOUT_224_239 0x01EA ++#define MT6397_EFUSE_DOUT_240_255 0x01EC ++#define MT6397_EFUSE_DOUT_256_271 0x01EE ++#define MT6397_EFUSE_DOUT_272_287 0x01F0 ++#define MT6397_EFUSE_DOUT_288_300 0x01F2 ++#define MT6397_EFUSE_DOUT_304_319 0x01F4 ++#define MT6397_BUCK_CON0 0x0200 ++#define MT6397_BUCK_CON1 0x0202 ++#define MT6397_BUCK_CON2 0x0204 ++#define MT6397_BUCK_CON3 0x0206 ++#define MT6397_BUCK_CON4 0x0208 ++#define MT6397_BUCK_CON5 0x020A ++#define MT6397_BUCK_CON6 0x020C ++#define MT6397_BUCK_CON7 0x020E ++#define MT6397_BUCK_CON8 0x0210 ++#define MT6397_BUCK_CON9 0x0212 ++#define MT6397_VCA15_CON0 0x0214 ++#define MT6397_VCA15_CON1 0x0216 ++#define MT6397_VCA15_CON2 0x0218 ++#define MT6397_VCA15_CON3 0x021A ++#define MT6397_VCA15_CON4 0x021C ++#define MT6397_VCA15_CON5 0x021E ++#define MT6397_VCA15_CON6 0x0220 ++#define MT6397_VCA15_CON7 0x0222 ++#define MT6397_VCA15_CON8 0x0224 ++#define MT6397_VCA15_CON9 0x0226 ++#define MT6397_VCA15_CON10 0x0228 ++#define MT6397_VCA15_CON11 0x022A ++#define MT6397_VCA15_CON12 0x022C ++#define MT6397_VCA15_CON13 0x022E ++#define MT6397_VCA15_CON14 0x0230 ++#define MT6397_VCA15_CON15 0x0232 ++#define MT6397_VCA15_CON16 0x0234 ++#define MT6397_VCA15_CON17 0x0236 ++#define MT6397_VCA15_CON18 0x0238 ++#define MT6397_VSRMCA15_CON0 0x023A ++#define MT6397_VSRMCA15_CON1 0x023C ++#define MT6397_VSRMCA15_CON2 0x023E ++#define MT6397_VSRMCA15_CON3 0x0240 ++#define MT6397_VSRMCA15_CON4 0x0242 ++#define MT6397_VSRMCA15_CON5 0x0244 ++#define MT6397_VSRMCA15_CON6 0x0246 ++#define MT6397_VSRMCA15_CON7 0x0248 ++#define MT6397_VSRMCA15_CON8 0x024A ++#define MT6397_VSRMCA15_CON9 0x024C ++#define MT6397_VSRMCA15_CON10 0x024E ++#define MT6397_VSRMCA15_CON11 0x0250 ++#define MT6397_VSRMCA15_CON12 0x0252 ++#define MT6397_VSRMCA15_CON13 0x0254 ++#define MT6397_VSRMCA15_CON14 0x0256 ++#define MT6397_VSRMCA15_CON15 0x0258 ++#define MT6397_VSRMCA15_CON16 0x025A ++#define MT6397_VSRMCA15_CON17 0x025C ++#define MT6397_VSRMCA15_CON18 0x025E ++#define MT6397_VSRMCA15_CON19 0x0260 ++#define MT6397_VSRMCA15_CON20 0x0262 ++#define MT6397_VSRMCA15_CON21 0x0264 ++#define MT6397_VCORE_CON0 0x0266 ++#define MT6397_VCORE_CON1 0x0268 ++#define MT6397_VCORE_CON2 0x026A ++#define MT6397_VCORE_CON3 0x026C ++#define MT6397_VCORE_CON4 0x026E ++#define MT6397_VCORE_CON5 0x0270 ++#define MT6397_VCORE_CON6 0x0272 ++#define MT6397_VCORE_CON7 0x0274 ++#define MT6397_VCORE_CON8 0x0276 ++#define MT6397_VCORE_CON9 0x0278 ++#define MT6397_VCORE_CON10 0x027A ++#define MT6397_VCORE_CON11 0x027C ++#define MT6397_VCORE_CON12 0x027E ++#define MT6397_VCORE_CON13 0x0280 ++#define MT6397_VCORE_CON14 0x0282 ++#define MT6397_VCORE_CON15 0x0284 ++#define MT6397_VCORE_CON16 0x0286 ++#define MT6397_VCORE_CON17 0x0288 ++#define MT6397_VCORE_CON18 0x028A ++#define MT6397_VGPU_CON0 0x028C ++#define MT6397_VGPU_CON1 0x028E ++#define MT6397_VGPU_CON2 0x0290 ++#define MT6397_VGPU_CON3 0x0292 ++#define MT6397_VGPU_CON4 0x0294 ++#define MT6397_VGPU_CON5 0x0296 ++#define MT6397_VGPU_CON6 0x0298 ++#define MT6397_VGPU_CON7 0x029A ++#define MT6397_VGPU_CON8 0x029C ++#define MT6397_VGPU_CON9 0x029E ++#define MT6397_VGPU_CON10 0x02A0 ++#define MT6397_VGPU_CON11 0x02A2 ++#define MT6397_VGPU_CON12 0x02A4 ++#define MT6397_VGPU_CON13 0x02A6 ++#define MT6397_VGPU_CON14 0x02A8 ++#define MT6397_VGPU_CON15 0x02AA ++#define MT6397_VGPU_CON16 0x02AC ++#define MT6397_VGPU_CON17 0x02AE ++#define MT6397_VGPU_CON18 0x02B0 ++#define MT6397_VIO18_CON0 0x0300 ++#define MT6397_VIO18_CON1 0x0302 ++#define MT6397_VIO18_CON2 0x0304 ++#define MT6397_VIO18_CON3 0x0306 ++#define MT6397_VIO18_CON4 0x0308 ++#define MT6397_VIO18_CON5 0x030A ++#define MT6397_VIO18_CON6 0x030C ++#define MT6397_VIO18_CON7 0x030E ++#define MT6397_VIO18_CON8 0x0310 ++#define MT6397_VIO18_CON9 0x0312 ++#define MT6397_VIO18_CON10 0x0314 ++#define MT6397_VIO18_CON11 0x0316 ++#define MT6397_VIO18_CON12 0x0318 ++#define MT6397_VIO18_CON13 0x031A ++#define MT6397_VIO18_CON14 0x031C ++#define MT6397_VIO18_CON15 0x031E ++#define MT6397_VIO18_CON16 0x0320 ++#define MT6397_VIO18_CON17 0x0322 ++#define MT6397_VIO18_CON18 0x0324 ++#define MT6397_VPCA7_CON0 0x0326 ++#define MT6397_VPCA7_CON1 0x0328 ++#define MT6397_VPCA7_CON2 0x032A ++#define MT6397_VPCA7_CON3 0x032C ++#define MT6397_VPCA7_CON4 0x032E ++#define MT6397_VPCA7_CON5 0x0330 ++#define MT6397_VPCA7_CON6 0x0332 ++#define MT6397_VPCA7_CON7 0x0334 ++#define MT6397_VPCA7_CON8 0x0336 ++#define MT6397_VPCA7_CON9 0x0338 ++#define MT6397_VPCA7_CON10 0x033A ++#define MT6397_VPCA7_CON11 0x033C ++#define MT6397_VPCA7_CON12 0x033E ++#define MT6397_VPCA7_CON13 0x0340 ++#define MT6397_VPCA7_CON14 0x0342 ++#define MT6397_VPCA7_CON15 0x0344 ++#define MT6397_VPCA7_CON16 0x0346 ++#define MT6397_VPCA7_CON17 0x0348 ++#define MT6397_VPCA7_CON18 0x034A ++#define MT6397_VSRMCA7_CON0 0x034C ++#define MT6397_VSRMCA7_CON1 0x034E ++#define MT6397_VSRMCA7_CON2 0x0350 ++#define MT6397_VSRMCA7_CON3 0x0352 ++#define MT6397_VSRMCA7_CON4 0x0354 ++#define MT6397_VSRMCA7_CON5 0x0356 ++#define MT6397_VSRMCA7_CON6 0x0358 ++#define MT6397_VSRMCA7_CON7 0x035A ++#define MT6397_VSRMCA7_CON8 0x035C ++#define MT6397_VSRMCA7_CON9 0x035E ++#define MT6397_VSRMCA7_CON10 0x0360 ++#define MT6397_VSRMCA7_CON11 0x0362 ++#define MT6397_VSRMCA7_CON12 0x0364 ++#define MT6397_VSRMCA7_CON13 0x0366 ++#define MT6397_VSRMCA7_CON14 0x0368 ++#define MT6397_VSRMCA7_CON15 0x036A ++#define MT6397_VSRMCA7_CON16 0x036C ++#define MT6397_VSRMCA7_CON17 0x036E ++#define MT6397_VSRMCA7_CON18 0x0370 ++#define MT6397_VSRMCA7_CON19 0x0372 ++#define MT6397_VSRMCA7_CON20 0x0374 ++#define MT6397_VSRMCA7_CON21 0x0376 ++#define MT6397_VDRM_CON0 0x0378 ++#define MT6397_VDRM_CON1 0x037A ++#define MT6397_VDRM_CON2 0x037C ++#define MT6397_VDRM_CON3 0x037E ++#define MT6397_VDRM_CON4 0x0380 ++#define MT6397_VDRM_CON5 0x0382 ++#define MT6397_VDRM_CON6 0x0384 ++#define MT6397_VDRM_CON7 0x0386 ++#define MT6397_VDRM_CON8 0x0388 ++#define MT6397_VDRM_CON9 0x038A ++#define MT6397_VDRM_CON10 0x038C ++#define MT6397_VDRM_CON11 0x038E ++#define MT6397_VDRM_CON12 0x0390 ++#define MT6397_VDRM_CON13 0x0392 ++#define MT6397_VDRM_CON14 0x0394 ++#define MT6397_VDRM_CON15 0x0396 ++#define MT6397_VDRM_CON16 0x0398 ++#define MT6397_VDRM_CON17 0x039A ++#define MT6397_VDRM_CON18 0x039C ++#define MT6397_BUCK_K_CON0 0x039E ++#define MT6397_BUCK_K_CON1 0x03A0 ++#define MT6397_ANALDO_CON0 0x0400 ++#define MT6397_ANALDO_CON1 0x0402 ++#define MT6397_ANALDO_CON2 0x0404 ++#define MT6397_ANALDO_CON3 0x0406 ++#define MT6397_ANALDO_CON4 0x0408 ++#define MT6397_ANALDO_CON5 0x040A ++#define MT6397_ANALDO_CON6 0x040C ++#define MT6397_ANALDO_CON7 0x040E ++#define MT6397_DIGLDO_CON0 0x0410 ++#define MT6397_DIGLDO_CON1 0x0412 ++#define MT6397_DIGLDO_CON2 0x0414 ++#define MT6397_DIGLDO_CON3 0x0416 ++#define MT6397_DIGLDO_CON4 0x0418 ++#define MT6397_DIGLDO_CON5 0x041A ++#define MT6397_DIGLDO_CON6 0x041C ++#define MT6397_DIGLDO_CON7 0x041E ++#define MT6397_DIGLDO_CON8 0x0420 ++#define MT6397_DIGLDO_CON9 0x0422 ++#define MT6397_DIGLDO_CON10 0x0424 ++#define MT6397_DIGLDO_CON11 0x0426 ++#define MT6397_DIGLDO_CON12 0x0428 ++#define MT6397_DIGLDO_CON13 0x042A ++#define MT6397_DIGLDO_CON14 0x042C ++#define MT6397_DIGLDO_CON15 0x042E ++#define MT6397_DIGLDO_CON16 0x0430 ++#define MT6397_DIGLDO_CON17 0x0432 ++#define MT6397_DIGLDO_CON18 0x0434 ++#define MT6397_DIGLDO_CON19 0x0436 ++#define MT6397_DIGLDO_CON20 0x0438 ++#define MT6397_DIGLDO_CON21 0x043A ++#define MT6397_DIGLDO_CON22 0x043C ++#define MT6397_DIGLDO_CON23 0x043E ++#define MT6397_DIGLDO_CON24 0x0440 ++#define MT6397_DIGLDO_CON25 0x0442 ++#define MT6397_DIGLDO_CON26 0x0444 ++#define MT6397_DIGLDO_CON27 0x0446 ++#define MT6397_DIGLDO_CON28 0x0448 ++#define MT6397_DIGLDO_CON29 0x044A ++#define MT6397_DIGLDO_CON30 0x044C ++#define MT6397_DIGLDO_CON31 0x044E ++#define MT6397_DIGLDO_CON32 0x0450 ++#define MT6397_DIGLDO_CON33 0x045A ++#define MT6397_SPK_CON0 0x0600 ++#define MT6397_SPK_CON1 0x0602 ++#define MT6397_SPK_CON2 0x0604 ++#define MT6397_SPK_CON3 0x0606 ++#define MT6397_SPK_CON4 0x0608 ++#define MT6397_SPK_CON5 0x060A ++#define MT6397_SPK_CON6 0x060C ++#define MT6397_SPK_CON7 0x060E ++#define MT6397_SPK_CON8 0x0610 ++#define MT6397_SPK_CON9 0x0612 ++#define MT6397_SPK_CON10 0x0614 ++#define MT6397_SPK_CON11 0x0616 ++#define MT6397_AUDDAC_CON0 0x0700 ++#define MT6397_AUDBUF_CFG0 0x0702 ++#define MT6397_AUDBUF_CFG1 0x0704 ++#define MT6397_AUDBUF_CFG2 0x0706 ++#define MT6397_AUDBUF_CFG3 0x0708 ++#define MT6397_AUDBUF_CFG4 0x070A ++#define MT6397_IBIASDIST_CFG0 0x070C ++#define MT6397_AUDACCDEPOP_CFG0 0x070E ++#define MT6397_AUD_IV_CFG0 0x0710 ++#define MT6397_AUDCLKGEN_CFG0 0x0712 ++#define MT6397_AUDLDO_CFG0 0x0714 ++#define MT6397_AUDLDO_CFG1 0x0716 ++#define MT6397_AUDNVREGGLB_CFG0 0x0718 ++#define MT6397_AUD_NCP0 0x071A ++#define MT6397_AUDPREAMP_CON0 0x071C ++#define MT6397_AUDADC_CON0 0x071E ++#define MT6397_AUDADC_CON1 0x0720 ++#define MT6397_AUDADC_CON2 0x0722 ++#define MT6397_AUDADC_CON3 0x0724 ++#define MT6397_AUDADC_CON4 0x0726 ++#define MT6397_AUDADC_CON5 0x0728 ++#define MT6397_AUDADC_CON6 0x072A ++#define MT6397_AUDDIGMI_CON0 0x072C ++#define MT6397_AUDLSBUF_CON0 0x072E ++#define MT6397_AUDLSBUF_CON1 0x0730 ++#define MT6397_AUDENCSPARE_CON0 0x0732 ++#define MT6397_AUDENCCLKSQ_CON0 0x0734 ++#define MT6397_AUDPREAMPGAIN_CON0 0x0736 ++#define MT6397_ZCD_CON0 0x0738 ++#define MT6397_ZCD_CON1 0x073A ++#define MT6397_ZCD_CON2 0x073C ++#define MT6397_ZCD_CON3 0x073E ++#define MT6397_ZCD_CON4 0x0740 ++#define MT6397_ZCD_CON5 0x0742 ++#define MT6397_NCP_CLKDIV_CON0 0x0744 ++#define MT6397_NCP_CLKDIV_CON1 0x0746 ++ ++#endif /* __MFD_MT6397_REGISTERS_H__ */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0060-arm-mediatek-select-the-arm-timer-by-default.patch b/target/linux/mediatek/patches/0060-arm-mediatek-select-the-arm-timer-by-default.patch new file mode 100644 index 0000000..2b64186 --- /dev/null +++ b/target/linux/mediatek/patches/0060-arm-mediatek-select-the-arm-timer-by-default.patch @@ -0,0 +1,26 @@ +From 46c695d8285b73d39b0e16fcfd7da332fd2398d4 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:00:27 +0200 +Subject: [PATCH 60/76] arm: mediatek: select the arm timer by default + +select ARM_ARCH_TIMER inside the Kconfig + +Signed-off-by: John Crispin +--- + arch/arm/mach-mediatek/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig +index 9f59e58..7704818 100644 +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -1,5 +1,6 @@ + menuconfig ARCH_MEDIATEK + bool "Mediatek MT65xx & MT81xx SoC" if ARCH_MULTI_V7 ++ select ARM_ARCH_TIMER + select ARM_GIC + select PINCTRL + select MTK_TIMER +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0061-arm-mediatek-add-mt7623-clock.patch b/target/linux/mediatek/patches/0061-arm-mediatek-add-mt7623-clock.patch new file mode 100644 index 0000000..f12ebb1 --- /dev/null +++ b/target/linux/mediatek/patches/0061-arm-mediatek-add-mt7623-clock.patch @@ -0,0 +1,846 @@ +From 7342787e992a70443081b9203d2131cbf6bc3562 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:12:38 +0200 +Subject: [PATCH 61/76] arm: mediatek: add mt7623 clock + +Signed-off-by: John Crispin +--- + drivers/clk/mediatek/Makefile | 1 + + drivers/clk/mediatek/clk-mt7623.c | 634 ++++++++++++++++++++++++++++++++ + include/dt-bindings/clock/mt7623-clk.h | 173 +++++++++ + 3 files changed, 808 insertions(+) + create mode 100644 drivers/clk/mediatek/clk-mt7623.c + create mode 100644 include/dt-bindings/clock/mt7623-clk.h + +diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile +index 8e4b2a4..19a3763 100644 +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -1,4 +1,5 @@ + obj-y += clk-mtk.o clk-pll.o clk-gate.o + obj-$(CONFIG_RESET_CONTROLLER) += reset.o ++obj-y += clk-mt7623.o + obj-y += clk-mt8135.o + obj-y += clk-mt8173.o +diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c +new file mode 100644 +index 0000000..07843bb +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7623.c +@@ -0,0 +1,634 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++static DEFINE_SPINLOCK(mt7623_clk_lock); ++ ++static struct clk_onecell_data *mt7623_top_clk_data; ++static struct clk_onecell_data *mt7623_pll_clk_data; ++ ++static void mtk_clk_enable_critical(void) ++{ ++ if (!mt7623_top_clk_data || !mt7623_pll_clk_data) ++ return; ++ ++ clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]); ++ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]); ++ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDR_SEL]); ++ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]); ++} ++ ++static const struct mtk_fixed_factor root_clk_alias[] __initconst = { ++ FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), ++ FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), ++}; ++ ++static const struct mtk_fixed_factor top_divs[] __initconst = { ++ FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_650m", "mainpll", 1, 2), ++ FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_433p3m", "mainpll", 1, 3), ++ FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_260m", "mainpll", 1, 5), ++ FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_185p6m", "mainpll", 1, 7), ++ ++ FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3), ++ FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5), ++ FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7), ++ FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26), ++ ++ FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll", 1, 4), ++ FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll", 1, 8), ++ FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll", 1, 16), ++ FACTOR(CLK_TOP_AUDPLL_24, "audpll_d24", "audpll", 1, 24), ++ ++ FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), ++ FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), ++ FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), ++ FACTOR(CLK_TOP_LVDS_ETH, "lvdspll_eth", "lvdspll", 1, 16), ++ ++ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), ++ ++ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), ++ ++ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll_650m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll_650m", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll_650m", 1, 8), ++ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll_650m", 1, 16), ++ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll_650m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll_650m", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll_650m", 1, 8), ++ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll_650m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll_650m", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll_650m", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll_650m", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_433p3m", 1, 1), ++ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_260m", 1, 1), ++ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll_185p6m", 1, 1), ++ ++ FACTOR(CLK_TOP_TVDPLL_d2, "tvdpll_d2", "tvdpll", 1, 2), ++ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), ++ ++ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), ++ FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10), ++ ++ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8), ++ ++ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6), ++ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), ++ FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10), ++ ++ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6), ++ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8), ++ ++ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1), ++ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1), ++ ++ ++ FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), ++}; ++ ++static const char * const axi_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d2", ++ "syspll_d5", ++ "syspll1_d4", ++ "univpll_d5", ++ "univpll2_d2", ++ "dmpll_ck", ++ "dmpll_d2" ++}; ++ ++static const char * const mem_parents[] __initconst = { ++ "clk26m", ++ "dmpll_ck", ++}; ++ ++static const char * const ddr_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d8", ++}; ++ ++static const char * const mm_parents[] __initconst = { ++ "clk26m", ++ "clk26m", ++ "vencpll_ck", ++ "syspll1_d2", ++ "syspll1_d4", ++ "univpll_d5", ++ "univpll1_d2", ++ "univpll2_d2", ++ "dmpll_ck" ++}; ++ ++static const char * const pwm_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d4", ++ "univpll3_d2", ++ "univpll1_d4", ++}; ++ ++static const char * const vdec_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d2", ++ "syspll_d5", ++ "syspll1_d4", ++ "univpll_d5", ++ "univpll2_d2", ++ "univpll2_d4", ++ "msdcpll_d2", ++ "mmpll_d2", ++}; ++ ++static const char * const mfg_parents[] __initconst = { ++ "clk26m", ++ "mmpll_ck", ++ "dmpll_x2_ck", ++ "msdcpll_ck", ++ "clk26m", ++ "syspll_d3", ++ "univpll_d3", ++ "univpll1_d2", ++}; ++ ++static const char * const cam_parents[] __initconst = { ++ "clk26m", ++ "univpll_d26", ++ "univpll2_d2", ++ "syspll3_d2", ++ "syspll3_d4", ++ "msdcpll_d2", ++ "mmpll_d2", ++ "clk26m", ++}; ++ ++static const char * const uart_parents[] __initconst = { ++ "clk26m", ++ "univpll2_d8", ++}; ++ ++static const char * const spi_parents[] __initconst = { ++ "clk26m", ++ "syspll3_d2", ++ "syspll4_d2", ++ "univpll2_d4", ++ "univpll1_d8", ++}; ++ ++static const char * const usb20_parents[] __initconst = { ++ "clk26m", ++ "univpll1_d8", ++ "univpll3_d4", ++ "clk26m", ++}; ++ ++static const char * const msdc_30_0_parents[] __initconst = { ++ "clk26m", ++ "msdcpll_d2", ++ "syspll2_d2", ++ "syspll1_d4", ++ "univpll1_d4", ++ "univpll2_d4", ++ "clk26m", ++ "clk26m", ++}; ++ ++static const char * const msdc_30_1_parents[] __initconst = { ++ "clk26m", ++ "msdcpll_d2", ++ "syspll2_d2", ++ "syspll1_d4", ++ "univpll1_d4", ++ "univpll2_d4", ++ "clk26m", ++ "clk26m", ++}; ++ ++static const char * const msdc_30_2_parents[] __initconst = { ++ "clk26m", ++ "msdcpll_d2", ++ "syspll2_d2", ++ "syspll1_d4", ++ "univpll1_d4", ++ "univpll2_d4", ++ "clk26m", ++ "clk26m", ++}; ++ ++static const char * const audio_parents[] __initconst = { ++ "f_f26m_ck", ++ "syspll1_d16", ++}; ++ ++static const char * const audio_intbus_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d4", ++ "syspll3_d2", ++ "syspll4_d2", ++ "univpll3_d2", ++ "univpll2_d4", ++}; ++ ++static const char * const pmic_spi_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d8", ++ "syspll2_d4", ++ "syspll4_d2", ++ "syspll3_d4", ++ "syspll2_d8", ++ "syspll1_d16", ++ "univpll3_d4", ++ "univpll_d26", ++ "dmpll_d2", ++ "dmpll_d4", ++}; ++ ++static const char * const scp_parents[] __initconst = { ++ "clk26m", ++ "syspll1_d8", ++ "dmpll_d2", ++ "dmpll_d4", ++}; ++ ++static const char * const dpi0_parents[] __initconst = { ++ "clk26m", ++ "mipipll", ++ "mipipll_d2", ++ "mipipll_d4", ++ "lvdspll", ++ "lvdspll_d2", ++ "lvdspll_d4", ++ "lvdspll_d8", ++}; ++ ++static const char * const dpi1_parents[] __initconst = { ++ "clk26m", ++ "tvdpll", ++ "tvdpll_d2", ++ "tvdpll_d4", ++}; ++ ++static const char * const tve_parents[] __initconst = { ++ "clk26m", ++ "mipipll", ++ "mipipll_d2", ++ "mipipll_d4", ++ "clk26m", ++ "tvdpll", ++ "tvdpll_d2", ++ "tvdpll_d4", ++}; ++ ++static const char * const apll_parents[] __initconst = { ++ "clk26m", ++ "audpll", ++ "audpll_d4", ++ "audpll_d8", ++ "audpll_d16", ++ "audpll_d24", ++ "clk26m", ++ "clk26m", ++}; ++ ++static const char * const dpilvds_parents[] __initconst = { ++ "clk26m", ++ "lvdspll", ++ "lvdspll_d2", ++ "lvdspll_d4", ++ "lvdspll_d8", ++ "fpc_ck", ++ "clk26m", ++ "clk26m", ++}; ++ ++static const char * const rtc_parents[] __initconst = { ++ "clk32k", ++ "external_32k", ++ "clk26m", ++ "univpll3_d8", ++}; ++ ++static const char * const nfi2x_parents[] __initconst = { ++ "clk26m", ++ "syspll2_d2", ++ "syspll_d7", ++ "univpll3_d2", ++ "syspll2_d4", ++ "univpll3_d4", ++ "syspll4_d4", ++ "clk26m", ++}; ++ ++static const char * const eth_parents[] __initconst = { ++ "clk26m", ++ "syspll3_d4", ++ "univpll2_d8", ++ "lvdspll_eth", ++ "univpll_d26", ++ "syspll2_d8", ++ "syspll4_d4", ++ "univpll3_d8", ++}; ++ ++static const struct mtk_composite top_muxes[] __initconst = { ++ /* CLK_CFG_0 */ ++ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, ++ 0x0140, 0, 3, INVALID_MUX_GATE_BIT), ++ MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 2, 15), ++ MUX_GATE(CLK_TOP_DDR_SEL, "ddr_sel", ddr_parents, 0x0040, 16, 2, 23), ++ MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, ++ 0x0140, 24, 3, INVALID_MUX_GATE_BIT), ++ /* CLK_CFG_1 */ ++ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), ++ MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15), ++ MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 16, 3, 23), ++ MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0050, 24, 3, 31), ++ /* CLK_CFG_2 */ ++ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7), ++ MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 8, 3, 15), ++ MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 16, 2, 23), ++ MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc_30_0_sel", msdc_30_0_parents, 0x0060, 24, 3, 31), ++ /* CLK_CFG_3 */ ++ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc_30_1_sel", msdc_30_1_parents, 0x0070, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc_30_2_sel", msdc_30_2_parents, 0x0070, 8, 3, 15), ++ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0070, 16, 1, 23), ++ MUX_GATE(CLK_TOP_AUDIO_INTBUS_SEL, ++ "audio_intbus_sel", audio_intbus_parents, 0x0070, 24, 3, 31), ++ /* CLK_CFG_4 */ ++ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmic_spi_parents, 0x0080, 0, 4, 7), ++ MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15), ++ MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23), ++ MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0080, 24, 2, 31), ++ /* CLK_CFG_5 */ ++ MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7), ++ MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0090, 16, 3, 23), ++ MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0090, 24, 3, 31), ++ /* CLK_CFG_6 */ ++ MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00a0, 0, 2, 7), ++ MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00a0, 8, 3, 15), ++ MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x00a0, 16, 3, 23), ++}; ++ ++static const struct mtk_gate_regs infra_cg_regs = { ++ .set_ofs = 0x0040, ++ .clr_ofs = 0x0044, ++ .sta_ofs = 0x0048, ++}; ++ ++#define GATE_ICG(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &infra_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate infra_clks[] __initconst = { ++ GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0), ++ GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1), ++ GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), ++ GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "axi_sel", 5), ++ GATE_ICG(CLK_INFRA_EFUSE, "l2c_sram_ck", "axi_sel", 5), ++ GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), ++ GATE_ICG(CLK_INFRA_CONNMCU, "connmcu_ck", "axi_sel", 8), ++ GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 8), ++ GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), ++ GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), ++ GATE_ICG(CLK_INFRA_CEC, "cec_ck", "axi_sel", 16), ++ GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 16), ++ GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), ++ GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), ++}; ++ ++static const struct mtk_gate_regs peri0_cg_regs = { ++ .set_ofs = 0x0008, ++ .clr_ofs = 0x0010, ++ .sta_ofs = 0x0018, ++}; ++ ++static const struct mtk_gate_regs peri1_cg_regs = { ++ .set_ofs = 0x000c, ++ .clr_ofs = 0x0014, ++ .sta_ofs = 0x001c, ++}; ++ ++#define GATE_PERI0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_PERI1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate peri_gates[] __initconst = { ++ /* PERI0 */ ++ GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0), ++ GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1), ++ GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2), ++ GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3), ++ GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4), ++ GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5), ++ GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6), ++ GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7), ++ GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8), ++ GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9), ++ GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10), ++ GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11), ++ GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12), ++ GATE_PERI0(CLK_PERI_MSDC20_1, "msdc_20_1_ck", "msdc_30_0_sel", 13), ++ GATE_PERI0(CLK_PERI_MSDC20_2, "msdc_20_2_ck", "msdc_30_1_sel", 14), ++ GATE_PERI0(CLK_PERI_MSDC30_1, "msdc_30_1_ck", "msdc_30_2_sel", 15), ++ GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 16), ++ GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 17), ++ GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 18), ++ GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 19), ++ GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 20), ++ GATE_PERI0(CLK_PERI_BTIF, "btif_ck", "axi_sel", 21), ++ GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 22), ++ GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 23), ++ GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 24), ++ GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 25), ++ GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "axi_sel", 26), ++ GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 27), ++ GATE_PERI0(CLK_PERI_ETH, "eth_ck", "eth_sel", 28), ++ GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu", "axi_sel", 29), ++ GATE_PERI0(CLK_PERI_USB1_MCU, "usb1_mcu","axi_sel", 30), ++ GATE_PERI0(CLK_PERI_USB_SLV, "usb_slv", "axi_sel", 31), ++ ++ /* PERI1 */ ++ GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 0), ++ GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "axi_sel", 1), ++ GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "axi_sel", 2), ++}; ++ ++static const char * const uart_ck_sel_parents[] __initconst = { ++ "clk26m", ++ "uart_sel", ++}; ++ ++static const struct mtk_composite peri_clks[] __initconst = { ++ MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), ++ MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), ++ MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), ++ MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), ++}; ++ ++static void __init mtk_topckgen_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ void __iomem *base; ++ int r; ++ ++ base = of_iomap(node, 0); ++ if (!base) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return; ++ } ++ ++ mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ ++ mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); ++ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); ++ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, ++ &mt7623_clk_lock, clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_clk_enable_critical(); ++} ++CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7623-topckgen", mtk_topckgen_init); ++ ++static void __init mtk_infrasys_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); ++ ++ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), ++ clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 2, 0x30); ++} ++CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt7623-infracfg", mtk_infrasys_init); ++ ++static void __init mtk_pericfg_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ void __iomem *base; ++ ++ base = of_iomap(node, 0); ++ if (!base) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return; ++ } ++ ++ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); ++ ++ mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), ++ clk_data); ++ mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, ++ &mt7623_clk_lock, clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 2, 0); ++} ++CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt7623-pericfg", mtk_pericfg_init); ++ ++#define MT7623_PLL_FMAX (2000 * MHZ) ++#define CON0_MT7623_RST_BAR BIT(27) ++ ++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .reg = _reg, \ ++ .pwr_reg = _pwr_reg, \ ++ .en_mask = _en_mask, \ ++ .flags = _flags, \ ++ .rst_bar_mask = CON0_MT7623_RST_BAR, \ ++ .fmax = MT7623_PLL_FMAX, \ ++ .pcwbits = _pcwbits, \ ++ .pd_reg = _pd_reg, \ ++ .pd_shift = _pd_shift, \ ++ .tuner_reg = _tuner_reg, \ ++ .pcw_reg = _pcw_reg, \ ++ .pcw_shift = _pcw_shift, \ ++ } ++ ++static const struct mtk_pll_data plls[] = { ++ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0), ++ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0x214, 6, 0x0, 0x214, 0), ++ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 0x224, 6, 0x0, 0x224, 0), ++ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 21, 0x254, 6, 0x0, 0x258, 0), ++ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 6, 0x0, 0x244, 0), ++ PLL(CLK_APMIXED_AUDPLL, "audpll", 0x250, 0x25c, 0x00000001, 0, 31, 0x2e8, 6, 0x2f8, 0x254, 0), ++ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x260, 0x26c, 0x00000001, 0, 31, 0x294, 6, 0x0, 0x298, 0), ++ PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x270, 0x27c, 0x00000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), ++}; ++ ++static void __init mtk_apmixedsys_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ ++ mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); ++ if (!clk_data) ++ return; ++ ++ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); ++ mtk_clk_enable_critical(); ++} ++CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7623-apmixedsys", ++ mtk_apmixedsys_init); +diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h +new file mode 100644 +index 0000000..cb1e8a9 +--- /dev/null ++++ b/include/dt-bindings/clock/mt7623-clk.h +@@ -0,0 +1,173 @@ ++/* ++ * Copyright c 2014 MediaTek Inc. ++ * Author: James Liao ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT7623_H ++#define _DT_BINDINGS_CLK_MT7623_H ++ ++/* TOPCKGEN */ ++ ++#define CLK_TOP_AUDPLL_24 1 ++#define CLK_TOP_AUDPLL_D16 2 ++#define CLK_TOP_AUDPLL_D4 3 ++#define CLK_TOP_AUDPLL_D8 4 ++#define CLK_TOP_CLKPH_MCK 5 ++#define CLK_TOP_CPUM_TCK_IN 6 ++#define CLK_TOP_DSI0_LNTC_DSICLK 7 ++#define CLK_TOP_HDMITX_CLKDIG_CTS 8 ++#define CLK_TOP_LVDS_ETH 9 ++#define CLK_TOP_LVDSPLL_D2 10 ++#define CLK_TOP_LVDSPLL_D4 11 ++#define CLK_TOP_LVDSPLL_D8 12 ++#define CLK_TOP_MAINPLL_230P3M 13 ++#define CLK_TOP_MAINPLL_322P4M 14 ++#define CLK_TOP_MAINPLL_537P3M 15 ++#define CLK_TOP_MAINPLL_806M 16 ++#define CLK_TOP_MEMPLL_MCK_D4 17 ++#define CLK_TOP_MMPLL_D2 18 ++#define CLK_TOP_MSDCPLL_D2 19 ++#define CLK_TOP_SYSPLL1_D16 20 ++#define CLK_TOP_SYSPLL1_D2 21 ++#define CLK_TOP_SYSPLL1_D4 22 ++#define CLK_TOP_SYSPLL1_D8 23 ++#define CLK_TOP_SYSPLL2_D2 24 ++#define CLK_TOP_SYSPLL2_D4 25 ++#define CLK_TOP_SYSPLL2_D8 26 ++#define CLK_TOP_SYSPLL3_D2 27 ++#define CLK_TOP_SYSPLL3_D4 28 ++#define CLK_TOP_SYSPLL4_D2 29 ++#define CLK_TOP_SYSPLL4_D4 30 ++#define CLK_TOP_SYSPLL_D3 31 ++#define CLK_TOP_SYSPLL_D5 32 ++#define CLK_TOP_SYSPLL_D7 33 ++#define CLK_TOP_TVDPLL_d2 34 ++#define CLK_TOP_TVDPLL_D4 35 ++#define CLK_TOP_UNIVPLL_178P3M 36 ++#define CLK_TOP_UNIVPLL1_D10 37 ++#define CLK_TOP_UNIVPLL1_D2 38 ++#define CLK_TOP_UNIVPLL1_D4 39 ++#define CLK_TOP_UNIVPLL1_D6 40 ++#define CLK_TOP_UNIVPLL1_D8 41 ++#define CLK_TOP_UNIVPLL_249P6M 42 ++#define CLK_TOP_UNIVPLL2_D2 43 ++#define CLK_TOP_UNIVPLL2_D4 44 ++#define CLK_TOP_UNIVPLL2_D6 45 ++#define CLK_TOP_UNIVPLL2_D8 46 ++#define CLK_TOP_UNIVPLL_416M 47 ++#define CLK_TOP_UNIVPLL_48M 48 ++#define CLK_TOP_UNIVPLL_624M 49 ++#define CLK_TOP_UNIVPLL_D26 50 ++#define CLK_TOP_UNIVPLL_D5 51 ++#define CLK_TOP_APLL_SEL 52 ++#define CLK_TOP_AUDIO_INTBUS_SEL 53 ++#define CLK_TOP_AUDIO_SEL 54 ++#define CLK_TOP_AXI_SEL 55 ++#define CLK_TOP_CAM_SEL 56 ++#define CLK_TOP_DDR_SEL 57 ++#define CLK_TOP_DPI0_SEL 58 ++#define CLK_TOP_DPI1_SEL 59 ++#define CLK_TOP_DPILVDS_SEL 60 ++#define CLK_TOP_ETH_SEL 61 ++#define CLK_TOP_MEM_SEL 62 ++#define CLK_TOP_MFG_SEL 63 ++#define CLK_TOP_MM_SEL 64 ++#define CLK_TOP_MSDC30_0_SEL 65 ++#define CLK_TOP_MSDC30_1_SEL 66 ++#define CLK_TOP_MSDC30_2_SEL 67 ++#define CLK_TOP_NFI2X_SEL 68 ++#define CLK_TOP_PMICSPI_SEL 69 ++#define CLK_TOP_PWM_SEL 70 ++#define CLK_TOP_RTC_SEL 71 ++#define CLK_TOP_SCP_SEL 72 ++#define CLK_TOP_SPI_SEL 73 ++#define CLK_TOP_TVE_SEL 74 ++#define CLK_TOP_UART_SEL 75 ++#define CLK_TOP_USB20_SEL 76 ++#define CLK_TOP_VDEC_SEL 77 ++#define CLK_TOP_NR_CLK 78 ++ ++/* APMIXED_SYS */ ++ ++#define CLK_APMIXED_ARMPLL 1 ++#define CLK_APMIXED_MAINPLL 2 ++#define CLK_APMIXED_MSDCPLL 3 ++#define CLK_APMIXED_UNIVPLL 4 ++#define CLK_APMIXED_MMPLL 5 ++#define CLK_APMIXED_VENCPLL 6 ++#define CLK_APMIXED_TVDPLL 7 ++#define CLK_APMIXED_LVDSPLL 8 ++#define CLK_APMIXED_AUDPLL 9 ++ ++/* INFRA_SYS */ ++ ++#define CLK_INFRA_DBGCLK 0 ++#define CLK_INFRA_SMI 1 ++#define CLK_INFRA_AUDIO 5 ++#define CLK_INFRA_EFUSE 6 ++#define CLK_INFRA_L2C_SRAM 7 ++#define CLK_INFRA_M4U 8 ++#define CLK_INFRA_CONNMCU 12 ++#define CLK_INFRA_TRNG 13 ++#define CLK_INFRA_CPUM 15 ++#define CLK_INFRA_KP 16 ++#define CLK_INFRA_CEC 18 ++#define CLK_INFRA_IRRX 19 ++#define CLK_INFRA_PMICSPI 22 ++#define CLK_INFRA_PMIC_WRAP 23 ++#define CLK_INFRA_NR_CLK 24 ++ ++/* PERI_SYS */ ++ ++#define CLK_PERI_NFI 0 ++#define CLK_PERI_THERM 1 ++#define CLK_PERI_PWM1 2 ++#define CLK_PERI_PWM2 3 ++#define CLK_PERI_PWM3 4 ++#define CLK_PERI_PWM4 5 ++#define CLK_PERI_PWM5 6 ++#define CLK_PERI_PWM6 7 ++#define CLK_PERI_PWM7 8 ++#define CLK_PERI_PWM 9 ++#define CLK_PERI_USB0 10 ++#define CLK_PERI_USB1 11 ++#define CLK_PERI_AP_DMA 12 ++#define CLK_PERI_MSDC20_1 13 ++#define CLK_PERI_MSDC20_2 14 ++#define CLK_PERI_MSDC30_1 15 ++#define CLK_PERI_NLI 16 ++#define CLK_PERI_UART0 17 ++#define CLK_PERI_UART1 18 ++#define CLK_PERI_UART2 19 ++#define CLK_PERI_UART3 20 ++#define CLK_PERI_BTIF 21 ++#define CLK_PERI_I2C0 22 ++#define CLK_PERI_I2C1 23 ++#define CLK_PERI_I2C2 24 ++#define CLK_PERI_I2C3 25 ++#define CLK_PERI_AUXADC 26 ++#define CLK_PERI_SPI0 27 ++#define CLK_PERI_ETH 28 ++#define CLK_PERI_USB0_MCU 29 ++#define CLK_PERI_USB1_MCU 30 ++#define CLK_PERI_USB_SLV 31 ++#define CLK_PERI_GCPU 32 ++#define CLK_PERI_NFI_ECC 33 ++#define CLK_PERI_NFI_PAD 34 ++#define CLK_PERI_UART0_SEL 35 ++#define CLK_PERI_UART1_SEL 36 ++#define CLK_PERI_UART2_SEL 37 ++#define CLK_PERI_UART3_SEL 38 ++#define CLK_PERI_NR_CLK 39 ++ ++#endif /* _DT_BINDINGS_CLK_MT7623_H */ ++ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0062-arm-mediatek-add-mt7623-pinctrl-supoort.patch b/target/linux/mediatek/patches/0062-arm-mediatek-add-mt7623-pinctrl-supoort.patch new file mode 100644 index 0000000..c9ea40e --- /dev/null +++ b/target/linux/mediatek/patches/0062-arm-mediatek-add-mt7623-pinctrl-supoort.patch @@ -0,0 +1,2889 @@ +From 718f377d37a737b133a3d904f5a038d6aa55c23e Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:13:05 +0200 +Subject: [PATCH 62/76] arm: mediatek: add mt7623 pinctrl supoort + +Signed-off-by: John Crispin +--- + drivers/pinctrl/mediatek/Kconfig | 6 + + drivers/pinctrl/mediatek/Makefile | 1 + + drivers/pinctrl/mediatek/pinctrl-mt7623.c | 368 +++++ + drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h | 1926 +++++++++++++++++++++++++ + include/dt-bindings/pinctrl/mt7623-pinfunc.h | 526 +++++++ + 5 files changed, 2827 insertions(+) + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h + create mode 100644 include/dt-bindings/pinctrl/mt7623-pinfunc.h + +diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig +index 0bc84fb..27c5673 100644 +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -9,6 +9,12 @@ config PINCTRL_MTK_COMMON + select OF_GPIO + + # For ARMv7 SoCs ++config PINCTRL_MT7623 ++ bool "Mediatek MT7623 pin control" if COMPILE_TEST && !MACH_MT7623 ++ depends on OF ++ default MACH_MT7623 ++ select PINCTRL_MTK_COMMON ++ + config PINCTRL_MT8135 + bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135 + depends on OF +diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile +index eb923d6..8998433 100644 +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -2,6 +2,7 @@ + obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o + + # SoC Drivers ++obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o + obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o + obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o +diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c +new file mode 100644 +index 0000000..77e1a66 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c +@@ -0,0 +1,368 @@ ++/* ++ * Copyright (c) 2014-2015 MediaTek Inc. ++ * Author: Hongzhou.Yang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pinctrl-mtk-common.h" ++#include "pinctrl-mtk-mt7623.h" ++ ++#define DRV_BASE 0xb00 ++ ++static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = { ++ MTK_PIN_PUPD_SPEC_SR(65, 0xcc0, 8, 9, 10), /* ms0 clk */ ++ MTK_PIN_PUPD_SPEC_SR(57, 0xcd0, 8, 9, 10), /* ms0 cmd */ ++ MTK_PIN_PUPD_SPEC_SR(60, 0xcf0, 0, 1, 2), /* ms0 data0 */ ++ MTK_PIN_PUPD_SPEC_SR(59, 0xcf0, 4, 5, 6), /* ms0 data1 */ ++ MTK_PIN_PUPD_SPEC_SR(58, 0xcf0, 8, 9, 10), /* ms0 data2 */ ++ MTK_PIN_PUPD_SPEC_SR(57, 0xcf0, 12, 13, 14), /* ms0 data3 */ ++ MTK_PIN_PUPD_SPEC_SR(61, 0xd00, 0, 1, 2), /* ms0 data4 */ ++ MTK_PIN_PUPD_SPEC_SR(62, 0xd00, 4, 5, 6), /* ms0 data5 */ ++ MTK_PIN_PUPD_SPEC_SR(63, 0xd00, 8, 9, 10), /* ms0 data6 */ ++ MTK_PIN_PUPD_SPEC_SR(64, 0xd00, 12, 13, 14), /* ms0 data7 */ ++ MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 0, 1, 2), /* ms0 RST */ ++ ++ MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */ ++ MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ ++ MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ ++ MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ ++ MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ ++ MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */ ++}; ++ ++static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin, ++ unsigned char align, bool isup, unsigned int r1r0) ++{ ++ return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd, ++ ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0); ++} ++ ++/*static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = { ++ MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1), ++ MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2), ++ MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10), ++ MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10), ++ MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0), ++ MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2), ++ MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3), ++ MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3), ++ MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4), ++ MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5), ++ MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6), ++ MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7), ++ MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9), ++ MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0), ++ MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11), ++ MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12), ++ MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13), ++ MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13), ++ MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13), ++ MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13), ++ MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13), ++ MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14), ++ MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13), ++ MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13), ++ MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13), ++ MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15), ++ MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0), ++ MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1), ++ MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2), ++ MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13), ++ MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14), ++ MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15), ++ MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13), ++ MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13), ++ MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13), ++ MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4), ++ MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1), ++ MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2), ++ MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5), ++ MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6), ++ MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7), ++ MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0), ++ MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8), ++ MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9), ++ MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8), ++ MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) ++}; ++ ++static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = { ++ MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1), ++ MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2), ++ MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10), ++ MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10), ++ MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0), ++ MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2), ++ MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3), ++ MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), ++ MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4), ++ MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5), ++ MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6), ++ MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7), ++ MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9), ++ MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0), ++ MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11), ++ MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12), ++ MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14), ++ MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14), ++ MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14), ++ MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14), ++ MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14), ++ MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14), ++ MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14), ++ MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14), ++ MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14), ++ MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15), ++ MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0), ++ MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1), ++ MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2), ++ MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13), ++ MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14), ++ MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15), ++ MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14), ++ MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14), ++ MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14), ++ MTK_PIN_IES_SMT_SPEC(106, 107, 0x91, 4), ++ MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1), ++ MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2), ++ MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5), ++ MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6), ++ MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7), ++ MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0), ++ MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8), ++ MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9), ++ MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8), ++ MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) ++}; ++ ++static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin, ++ unsigned char align, int value, enum pin_config_param arg) ++{ ++ if (arg == PIN_CONFIG_INPUT_ENABLE) ++ return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set, ++ ARRAY_SIZE(mt7623_ies_set), pin, align, value); ++ else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) ++ return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set, ++ ARRAY_SIZE(mt7623_smt_set), pin, align, value); ++ return -EINVAL; ++} ++*/ ++static const struct mtk_drv_group_desc mt7623_drv_grp[] = { ++ /* 0E4E8SR 4/8/12/16 */ ++ MTK_DRV_GRP(4, 16, 1, 2, 4), ++ /* 0E2E4SR 2/4/6/8 */ ++ MTK_DRV_GRP(2, 8, 1, 2, 2), ++ /* E8E4E2 2/4/6/8/10/12/14/16 */ ++ MTK_DRV_GRP(2, 16, 0, 2, 2) ++}; ++ ++/*static const struct mtk_pin_drv_grp mt7623_pin_drv[] = { ++ MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0), ++ MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0), ++ MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0), ++ MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0), ++ MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0), ++ MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0), ++ MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0), ++ MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0), ++ MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0), ++ MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0), ++ MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1), ++ MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1), ++ MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1), ++ MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1), ++ MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1), ++ MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1), ++ MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1), ++ MTK_PIN_DRV_GRP(17, 0xce0, 8, 2), ++ MTK_PIN_DRV_GRP(22, 0xce0, 8, 2), ++ MTK_PIN_DRV_GRP(23, 0xce0, 8, 2), ++ MTK_PIN_DRV_GRP(24, 0xce0, 8, 2), ++ MTK_PIN_DRV_GRP(25, 0xce0, 8, 2), ++ MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2), ++ MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2), ++ MTK_PIN_DRV_GRP(28, 0xd70, 8, 2), ++ MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1), ++ MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1), ++ MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1), ++ MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1), ++ MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1), ++ MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1), ++ MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1), ++ MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1), ++ MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1), ++ MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1), ++ MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0), ++ MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0), ++ MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0), ++ MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1), ++ MTK_PIN_DRV_GRP(57, 0xc20, 8, 2), ++ MTK_PIN_DRV_GRP(58, 0xc20, 8, 2), ++ MTK_PIN_DRV_GRP(59, 0xc20, 8, 2), ++ MTK_PIN_DRV_GRP(60, 0xc20, 8, 2), ++ MTK_PIN_DRV_GRP(61, 0xc20, 8, 2), ++ MTK_PIN_DRV_GRP(62, 0xc20, 8, 2), ++ MTK_PIN_DRV_GRP(63, 0xc20, 8, 2), ++ MTK_PIN_DRV_GRP(64, 0xc20, 8, 2), ++ MTK_PIN_DRV_GRP(65, 0xc00, 8, 2), ++ MTK_PIN_DRV_GRP(66, 0xc10, 8, 2), ++ MTK_PIN_DRV_GRP(67, 0xd10, 8, 2), ++ MTK_PIN_DRV_GRP(68, 0xd00, 8, 2), ++ MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1), ++ MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1), ++ MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1), ++ MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1), ++ MTK_PIN_DRV_GRP(73, 0xc60, 8, 2), ++ MTK_PIN_DRV_GRP(74, 0xc60, 8, 2), ++ MTK_PIN_DRV_GRP(75, 0xc60, 8, 2), ++ MTK_PIN_DRV_GRP(76, 0xc60, 8, 2), ++ MTK_PIN_DRV_GRP(77, 0xc40, 8, 2), ++ MTK_PIN_DRV_GRP(78, 0xc50, 8, 2), ++ MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1), ++ MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1), ++ MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1), ++ MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1), ++ MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1), ++ MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1), ++ MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1), ++ MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1), ++ MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1), ++ MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1), ++ MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1), ++ MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1), ++ MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1), ++ MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1), ++ MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0), ++ MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0), ++ MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0), ++ MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0), ++ MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1), ++ MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1), ++ MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1), ++ MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1), ++ MTK_PIN_DRV_GRP(100, 0xca0, 8, 2), ++ MTK_PIN_DRV_GRP(101, 0xca0, 8, 2), ++ MTK_PIN_DRV_GRP(102, 0xca0, 8, 2), ++ MTK_PIN_DRV_GRP(103, 0xca0, 8, 2), ++ MTK_PIN_DRV_GRP(104, 0xc80, 8, 2), ++ MTK_PIN_DRV_GRP(105, 0xc90, 8, 2), ++ MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1), ++ MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1), ++ MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1), ++ MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1), ++ MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1), ++ MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1), ++ MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1), ++ MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1), ++ MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1), ++ MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1), ++ MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1), ++ MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1), ++ MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1), ++ MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1), ++ MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1), ++ MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1), ++ MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1), ++ MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1), ++ MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1), ++ MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1), ++ MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1), ++ MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1), ++ MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1), ++ MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1), ++ MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1) ++}; ++*/ ++static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = { ++ .pins = mtk_pins_mt7623, ++ .npins = ARRAY_SIZE(mtk_pins_mt7623), ++ .grp_desc = mt7623_drv_grp, ++ .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp), ++// .pin_drv_grp = mt7623_pin_drv, ++// .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv), ++ .spec_pull_set = mt7623_spec_pull_set, ++ //.spec_ies_smt_set = mt7623_ies_smt_set, ++ .dir_offset = 0x0000, ++ .pullen_offset = 0x0150, ++ .pullsel_offset = 0x0280, ++ .dout_offset = 0x0550, ++ .din_offset = 0x0630, ++ .pinmux_offset = 0x0760, ++ .port_shf = 4, ++ .port_mask = 0xf, ++ .port_align = 4, ++ .eint_offsets = { ++ .name = "mt7623_eint", ++ .stat = 0x000, ++ .ack = 0x040, ++ .mask = 0x080, ++ .mask_set = 0x0c0, ++ .mask_clr = 0x100, ++ .sens = 0x140, ++ .sens_set = 0x180, ++ .sens_clr = 0x1c0, ++ .soft = 0x200, ++ .soft_set = 0x240, ++ .soft_clr = 0x280, ++ .pol = 0x300, ++ .pol_set = 0x340, ++ .pol_clr = 0x380, ++ .dom_en = 0x400, ++ .dbnc_ctrl = 0x500, ++ .dbnc_set = 0x600, ++ .dbnc_clr = 0x700, ++ .port_mask = 7, ++ .ports = 6, ++ }, ++ .ap_num = 224, ++ .db_cnt = 16, ++}; ++ ++static int mt7623_pinctrl_probe(struct platform_device *pdev) ++{ ++ return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL); ++} ++ ++static const struct of_device_id mt7623_pctrl_match[] = { ++ { ++ .compatible = "mediatek,mt7623-pinctrl", ++ }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, mt7623_pctrl_match); ++ ++static struct platform_driver mtk_pinctrl_driver = { ++ .probe = mt7623_pinctrl_probe, ++ .driver = { ++ .name = "mediatek-mt7623-pinctrl", ++ .of_match_table = mt7623_pctrl_match, ++ }, ++}; ++ ++static int __init mtk_pinctrl_init(void) ++{ ++ return platform_driver_register(&mtk_pinctrl_driver); ++} ++ ++module_init(mtk_pinctrl_init); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); ++MODULE_AUTHOR("John Crispin "); +diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h +new file mode 100644 +index 0000000..4b65668 +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h +@@ -0,0 +1,1926 @@ ++#ifndef __PINCTRL_MTK_MT7623_H ++#define __PINCTRL_MTK_MT7623_H ++ ++#include ++#include "pinctrl-mtk-common.h" ++ ++static const struct mtk_desc_pin mtk_pins_mt7623[] = { ++ MTK_PIN( ++ PINCTRL_PIN(0, "PWRAP_SPI0_MI"), ++ "F11", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO0"), ++ MTK_FUNCTION(1, "PWRAP_SPIDO"), ++ MTK_FUNCTION(2, "PWRAP_SPIDI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(1, "PWRAP_SPI0_MO"), ++ "D10", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO1"), ++ MTK_FUNCTION(1, "PWRAP_SPIDI"), ++ MTK_FUNCTION(2, "PWRAP_SPIDO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(2, "PWRAP_INT"), ++ "E11", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO2"), ++ MTK_FUNCTION(1, "PWRAP_INT") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(3, "PWRAP_SPI0_CK"), ++ "H12", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO3"), ++ MTK_FUNCTION(1, "PWRAP_SPICK_I") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(4, "PWRAP_SPI0_CSN"), ++ "E12", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO4"), ++ MTK_FUNCTION(1, "PWRAP_SPICS_B_I") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(5, "PWRAP_SPI0_CK2"), ++ "H11", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO5"), ++ MTK_FUNCTION(1, "PWRAP_SPICK2_I") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"), ++ "G11", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO6"), ++ MTK_FUNCTION(1, "PWRAP_SPICS2_B_I") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(7, "SPI1_CSN"), ++ "G19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO7"), ++ MTK_FUNCTION(1, "SPI1_CS") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(8, "SPI1_MI"), ++ "F19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO8"), ++ MTK_FUNCTION(1, "SPI1_MI"), ++ MTK_FUNCTION(2, "SPI1_MO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(9, "SPI1_MO"), ++ "G20", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO9"), ++ MTK_FUNCTION(1, "SPI1_MO"), ++ MTK_FUNCTION(2, "SPI1_MI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(10, "RTC32K_CK"), ++ "A13", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO10"), ++ MTK_FUNCTION(1, "RTC32K_CK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(11, "WATCHDOG"), ++ "D14", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO11"), ++ MTK_FUNCTION(1, "WATCHDOG") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(12, "SRCLKENA"), ++ "C13", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO12"), ++ MTK_FUNCTION(1, "SRCLKENA") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(13, "SRCLKENAI"), ++ "B13", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO13"), ++ MTK_FUNCTION(1, "SRCLKENAI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(14, "GPIO14"), ++ "E18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO14"), ++ MTK_FUNCTION(1, "URXD2"), ++ MTK_FUNCTION(2, "UTXD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(15, "GPIO15"), ++ "E17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO15"), ++ MTK_FUNCTION(1, "UTXD2"), ++ MTK_FUNCTION(2, "URXD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(16, "GPIO16"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO16") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(17, "GPIO17"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO17") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(18, "PCM_CLK"), ++ "C19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO18"), ++ MTK_FUNCTION(1, "PCM_CLK0"), ++ MTK_FUNCTION(6, "AP_PCM_CLKO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(19, "PCM_SYNC"), ++ "D19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO19"), ++ MTK_FUNCTION(1, "PCM_SYNC"), ++ MTK_FUNCTION(6, "AP_PCM_SYNC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(20, "PCM_RX"), ++ "D18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO20"), ++ MTK_FUNCTION(1, "PCM_RX"), ++ MTK_FUNCTION(4, "PCM_TX"), ++ MTK_FUNCTION(6, "AP_PCM_RX") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(21, "PCM_TX"), ++ "C18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO21"), ++ MTK_FUNCTION(1, "PCM_TX"), ++ MTK_FUNCTION(4, "PCM_RX"), ++ MTK_FUNCTION(6, "AP_PCM_TX") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(22, "EINT0"), ++ "H15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO22"), ++ MTK_FUNCTION(1, "UCTS0"), ++ MTK_FUNCTION(2, "PCIE0_PERST_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(23, "EINT1"), ++ "J16", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO23"), ++ MTK_FUNCTION(1, "URTS0"), ++ MTK_FUNCTION(2, "PCIE1_PERST_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(24, "EINT2"), ++ "H16", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO24"), ++ MTK_FUNCTION(1, "UCTS1"), ++ MTK_FUNCTION(2, "PCIE2_PERST_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(25, "EINT3"), ++ "K15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO25"), ++ MTK_FUNCTION(1, "URTS1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(26, "EINT4"), ++ "G15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO26"), ++ MTK_FUNCTION(1, "UCTS3"), ++ MTK_FUNCTION(6, "PCIE2_WAKE_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(27, "EINT5"), ++ "F15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO27"), ++ MTK_FUNCTION(1, "URTS3"), ++ MTK_FUNCTION(6, "PCIE1_WAKE_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(28, "EINT6"), ++ "J15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO28"), ++ MTK_FUNCTION(1, "DRV_VBUS"), ++ MTK_FUNCTION(6, "PCIE0_WAKE_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(29, "EINT7"), ++ "E15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO29"), ++ MTK_FUNCTION(1, "IDDIG"), ++ MTK_FUNCTION(2, "MSDC1_WP"), ++ MTK_FUNCTION(6, "PCIE2_PERST_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(30, "GPIO30"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO30") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(31, "GPIO31"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO31") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(32, "GPIO32"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO32") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(33, "I2S1_DATA"), ++ "Y18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO33"), ++ MTK_FUNCTION(1, "I2S1_DATA"), ++ MTK_FUNCTION(3, "PCM_TX"), ++ MTK_FUNCTION(6, "AP_PCM_TX") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(34, "I2S1_DATA_IN"), ++ "Y17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO34"), ++ MTK_FUNCTION(1, "I2S1_DATA_IN"), ++ MTK_FUNCTION(3, "PCM_RX"), ++ MTK_FUNCTION(6, "AP_PCM_RX") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(35, "I2S1_BCK"), ++ "V17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO35"), ++ MTK_FUNCTION(1, "I2S1_BCK"), ++ MTK_FUNCTION(3, "PCM_CLK0"), ++ MTK_FUNCTION(6, "AP_PCM_CLKO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(36, "I2S1_LRCK"), ++ "W17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO36"), ++ MTK_FUNCTION(1, "I2S1_LRCK"), ++ MTK_FUNCTION(3, "PCM_SYNC"), ++ MTK_FUNCTION(6, "AP_PCM_SYNC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(37, "I2S1_MCLK"), ++ "AA18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO37"), ++ MTK_FUNCTION(1, "I2S1_MCLK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(38, "GPIO38"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO38") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(39, "JTMS"), ++ "G21", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO39"), ++ MTK_FUNCTION(1, "JTMS") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(40, "JTCK"), ++ "J20", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO40"), ++ MTK_FUNCTION(1, "JTCK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(41, "JTDI"), ++ "H22", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO41"), ++ MTK_FUNCTION(1, "JTDI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(42, "JTDO"), ++ "H21", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO42"), ++ MTK_FUNCTION(1, "JTDO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(43, "NCLE"), ++ "C7", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO43"), ++ MTK_FUNCTION(1, "NCLE"), ++ MTK_FUNCTION(2, "EXT_XCS2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(44, "NCEB1"), ++ "C6", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO44"), ++ MTK_FUNCTION(1, "NCEB1"), ++ MTK_FUNCTION(2, "IDDIG") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(45, "NCEB0"), ++ "D7", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO45"), ++ MTK_FUNCTION(1, "NCEB0"), ++ MTK_FUNCTION(2, "DRV_VBUS") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(46, "IR"), ++ "D15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO46"), ++ MTK_FUNCTION(1, "IR") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(47, "NREB"), ++ "A6", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO47"), ++ MTK_FUNCTION(1, "NREB") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(48, "NRNB"), ++ "B6", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO48"), ++ MTK_FUNCTION(1, "NRNB") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(49, "I2S0_DATA"), ++ "AB18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO49"), ++ MTK_FUNCTION(1, "I2S0_DATA"), ++ MTK_FUNCTION(3, "PCM_TX"), ++ MTK_FUNCTION(6, "AP_I2S_DO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(50, "GPIO50"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO50") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(51, "GPIO51"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO51") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(52, "GPIO52"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO52") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(53, "SPI0_CSN"), ++ "E7", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO53"), ++ MTK_FUNCTION(1, "SPI0_CS"), ++ MTK_FUNCTION(5, "PWM1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(54, "SPI0_CK"), ++ "F7", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO54"), ++ MTK_FUNCTION(1, "SPI0_CK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(55, "SPI0_MI"), ++ "E6", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO55"), ++ MTK_FUNCTION(1, "SPI0_MI"), ++ MTK_FUNCTION(2, "SPI0_MO"), ++ MTK_FUNCTION(3, "MSDC1_WP"), ++ MTK_FUNCTION(5, "PWM2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(56, "SPI0_MO"), ++ "G7", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO56"), ++ MTK_FUNCTION(1, "SPI0_MO"), ++ MTK_FUNCTION(2, "SPI0_MI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(57, "GPIO57"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO57") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(58, "GPIO58"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO58") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(59, "GPIO59"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO59") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(60, "WB_RSTB"), ++ "Y21", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO60"), ++ MTK_FUNCTION(1, "WB_RSTB") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(61, "GPIO61"), ++ "AA21", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO61"), ++ MTK_FUNCTION(1, "TEST_FD") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(62, "GPIO62"), ++ "AB22", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO62"), ++ MTK_FUNCTION(1, "TEST_FC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(63, "WB_SCLK"), ++ "AC23", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO63"), ++ MTK_FUNCTION(1, "WB_SCLK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(64, "WB_SDATA"), ++ "AB21", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO64"), ++ MTK_FUNCTION(1, "WB_SDATA") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(65, "WB_SEN"), ++ "AB24", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO65"), ++ MTK_FUNCTION(1, "WB_SEN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(66, "WB_CRTL0"), ++ "AB20", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO66"), ++ MTK_FUNCTION(1, "WB_CRTL0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(67, "WB_CRTL1"), ++ "AC20", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO67"), ++ MTK_FUNCTION(1, "WB_CRTL1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(68, "WB_CRTL2"), ++ "AB19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO68"), ++ MTK_FUNCTION(1, "WB_CRTL2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(69, "WB_CRTL3"), ++ "AC19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO69"), ++ MTK_FUNCTION(1, "WB_CRTL3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(70, "WB_CRTL4"), ++ "AD19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO70"), ++ MTK_FUNCTION(1, "WB_CRTL4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(71, "WB_CRTL5"), ++ "AE19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO71"), ++ MTK_FUNCTION(1, "WB_CRTL5") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(72, "I2S0_DATA_IN"), ++ "AA20", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO72"), ++ MTK_FUNCTION(1, "I2S0_DATA_IN"), ++ MTK_FUNCTION(3, "PCM_RX"), ++ MTK_FUNCTION(4, "PWM0"), ++ MTK_FUNCTION(5, "DISP_PWM"), ++ MTK_FUNCTION(6, "AP_I2S_DI") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(73, "I2S0_LRCK"), ++ "Y20", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO73"), ++ MTK_FUNCTION(1, "I2S0_LRCK"), ++ MTK_FUNCTION(3, "PCM_SYNC"), ++ MTK_FUNCTION(6, "AP_I2S_LRCK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(74, "I2S0_BCK"), ++ "Y19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO74"), ++ MTK_FUNCTION(1, "I2S0_BCK"), ++ MTK_FUNCTION(3, "PCM_CLK0"), ++ MTK_FUNCTION(6, "AP_I2S_BCK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(75, "SDA0"), ++ "K19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO75"), ++ MTK_FUNCTION(1, "SDA0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(76, "SCL0"), ++ "K20", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO76"), ++ MTK_FUNCTION(1, "SCL0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(77, "GPIO77"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO77") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(78, "GPIO78"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO78") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(79, "GPIO79"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO79") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(80, "GPIO80"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO80") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(81, "GPIO81"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO81") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(82, "GPIO82"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO82") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(83, "LCM_RST"), ++ "V16", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO83"), ++ MTK_FUNCTION(1, "LCM_RST") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(84, "DSI_TE"), ++ "V14", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO84"), ++ MTK_FUNCTION(1, "DSI_TE") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(85, "GPIO85"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO85") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(86, "GPIO86"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO86") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(87, "GPIO87"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO87") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(88, "GPIO88"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO88") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(89, "GPIO89"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO89") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(90, "GPIO90"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO90") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(91, "GPIO91"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO91") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(92, "GPIO92"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO92") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(93, "GPIO93"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO93") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(94, "GPIO94"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO94") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(95, "MIPI_TCN"), ++ "AB14", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO95"), ++ MTK_FUNCTION(1, "TCN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(96, "MIPI_TCP"), ++ "AC14", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO96"), ++ MTK_FUNCTION(1, "TCP") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(97, "MIPI_TDN1"), ++ "AE15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO97"), ++ MTK_FUNCTION(1, "TDN1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(98, "MIPI_TDP1"), ++ "AD15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO98"), ++ MTK_FUNCTION(1, "TDP1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(99, "MIPI_TDN0"), ++ "AB15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO99"), ++ MTK_FUNCTION(1, "TDN0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(100, "MIPI_TDP0"), ++ "AC15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO100"), ++ MTK_FUNCTION(1, "TDP0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(101, "GPIO101"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO101") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(102, "GPIO102"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO102") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(103, "GPIO103"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO103") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(104, "GPIO104"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO104") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(105, "MSDC1_CMD"), ++ "AD2", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO105"), ++ MTK_FUNCTION(1, "MSDC1_CMD"), ++ MTK_FUNCTION(3, "SDA1"), ++ MTK_FUNCTION(6, "I2SOUT_BCK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(106, "MSDC1_CLK"), ++ "AD3", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO106"), ++ MTK_FUNCTION(1, "MSDC1_CLK"), ++ MTK_FUNCTION(3, "SCL1"), ++ MTK_FUNCTION(6, "I2SOUT_LRCK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(107, "MSDC1_DAT0"), ++ "AE2", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO107"), ++ MTK_FUNCTION(1, "MSDC1_DAT0"), ++ MTK_FUNCTION(5, "UTXD0"), ++ MTK_FUNCTION(6, "I2SOUT_DATA_OUT") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(108, "MSDC1_DAT1"), ++ "AC1", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO108"), ++ MTK_FUNCTION(1, "MSDC1_DAT1"), ++ MTK_FUNCTION(3, "PWM0"), ++ MTK_FUNCTION(5, "URXD0"), ++ MTK_FUNCTION(6, "PWM1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(109, "MSDC1_DAT2"), ++ "AC3", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO109"), ++ MTK_FUNCTION(1, "MSDC1_DAT2"), ++ MTK_FUNCTION(3, "SDA2"), ++ MTK_FUNCTION(5, "UTXD1"), ++ MTK_FUNCTION(6, "PWM2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(110, "MSDC1_DAT3"), ++ "AC4", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO110"), ++ MTK_FUNCTION(1, "MSDC1_DAT3"), ++ MTK_FUNCTION(3, "SCL2"), ++ MTK_FUNCTION(5, "URXD1"), ++ MTK_FUNCTION(6, "PWM3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(111, "MSDC0_DAT7"), ++ "A2", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO111"), ++ MTK_FUNCTION(1, "MSDC0_DAT7"), ++ MTK_FUNCTION(4, "NLD7") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(112, "MSDC0_DAT6"), ++ "B3", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO112"), ++ MTK_FUNCTION(1, "MSDC0_DAT6"), ++ MTK_FUNCTION(4, "NLD6") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(113, "MSDC0_DAT5"), ++ "C4", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO113"), ++ MTK_FUNCTION(1, "MSDC0_DAT5"), ++ MTK_FUNCTION(4, "NLD5") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(114, "MSDC0_DAT4"), ++ "A4", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO114"), ++ MTK_FUNCTION(1, "MSDC0_DAT4"), ++ MTK_FUNCTION(4, "NLD4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(115, "MSDC0_RSTB"), ++ "C5", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO115"), ++ MTK_FUNCTION(1, "MSDC0_RSTB"), ++ MTK_FUNCTION(4, "NLD8") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(116, "MSDC0_CMD"), ++ "D5", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO116"), ++ MTK_FUNCTION(1, "MSDC0_CMD"), ++ MTK_FUNCTION(4, "NALE") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(117, "MSDC0_CLK"), ++ "B1", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO117"), ++ MTK_FUNCTION(1, "MSDC0_CLK"), ++ MTK_FUNCTION(4, "NWEB") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(118, "MSDC0_DAT3"), ++ "D6", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO118"), ++ MTK_FUNCTION(1, "MSDC0_DAT3"), ++ MTK_FUNCTION(4, "NLD3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(119, "MSDC0_DAT2"), ++ "B2", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO119"), ++ MTK_FUNCTION(1, "MSDC0_DAT2"), ++ MTK_FUNCTION(4, "NLD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(120, "MSDC0_DAT1"), ++ "A3", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO120"), ++ MTK_FUNCTION(1, "MSDC0_DAT1"), ++ MTK_FUNCTION(4, "NLD1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(121, "MSDC0_DAT0"), ++ "B4", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO121"), ++ MTK_FUNCTION(1, "MSDC0_DAT0"), ++ MTK_FUNCTION(4, "NLD0"), ++ MTK_FUNCTION(5, "WATCHDOG") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(122, "GPIO122"), ++ "H17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO122"), ++ MTK_FUNCTION(1, "TEST"), ++ MTK_FUNCTION(4, "SDA2"), ++ MTK_FUNCTION(5, "URXD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(123, "GPIO123"), ++ "F17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO123"), ++ MTK_FUNCTION(1, "TEST"), ++ MTK_FUNCTION(4, "SCL2"), ++ MTK_FUNCTION(5, "UTXD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(124, "GPIO124"), ++ "H18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO124"), ++ MTK_FUNCTION(1, "TEST"), ++ MTK_FUNCTION(4, "SDA1"), ++ MTK_FUNCTION(5, "PWM3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(125, "GPIO125"), ++ "G17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO125"), ++ MTK_FUNCTION(1, "TEST"), ++ MTK_FUNCTION(4, "SCL1"), ++ MTK_FUNCTION(5, "PWM4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(126, "I2S0_MCLK"), ++ "AA19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO126"), ++ MTK_FUNCTION(1, "I2S0_MCLK"), ++ MTK_FUNCTION(6, "AP_I2S_MCLK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(127, "GPIO127"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO127") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(128, "GPIO128"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO128") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(129, "GPIO129"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO129") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(130, "GPIO130"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO130") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(131, "GPIO131"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO131") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(132, "GPIO132"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO132") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(133, "GPIO133"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO133") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(134, "GPIO134"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO134") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(135, "GPIO135"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO135") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(136, "GPIO136"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO136") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(137, "GPIO137"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO137") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(138, "GPIO138"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO138") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(139, "GPIO139"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO139") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(140, "GPIO140"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO140") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(141, "GPIO141"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO141") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(142, "GPIO142"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO142") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(143, "GPIO143"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO143") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(144, "GPIO144"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO144") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(145, "GPIO145"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO145") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(146, "GPIO146"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO146") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(147, "GPIO147"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO147") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(148, "GPIO148"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO148") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(149, "GPIO149"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO149") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(150, "GPIO150"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO150") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(151, "GPIO151"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO151") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(152, "GPIO152"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO152") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(153, "GPIO153"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO153") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(154, "GPIO154"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO154") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(155, "GPIO155"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO155") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(156, "GPIO156"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO156") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(157, "GPIO157"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO157") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(158, "GPIO158"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO158") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(159, "GPIO159"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO159") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(160, "GPIO160"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO160") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(161, "GPIO161"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO161") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(162, "GPIO162"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO162") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(163, "GPIO163"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO163") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(164, "GPIO164"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO164") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(165, "GPIO165"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO165") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(166, "GPIO166"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO166") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(167, "GPIO167"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO167") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(168, "GPIO168"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO168") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(169, "GPIO169"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO169") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(170, "GPIO170"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO170") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(171, "GPIO171"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO171") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(172, "GPIO172"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO172") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(173, "GPIO173"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO173") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(174, "GPIO174"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO174") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(175, "GPIO175"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO175") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(176, "GPIO176"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO176") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(177, "GPIO177"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO177") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(178, "GPIO178"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO178") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(179, "GPIO179"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO179") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(180, "GPIO180"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO180") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(181, "GPIO181"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO181") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(182, "GPIO182"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO182") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(183, "GPIO183"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO183") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(184, "GPIO184"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO184") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(185, "GPIO185"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO185") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(186, "GPIO186"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO186") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(187, "GPIO187"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO187") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(188, "GPIO188"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO188") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(189, "GPIO189"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO189") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(190, "GPIO190"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO190") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(191, "GPIO191"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO191") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(192, "GPIO192"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO192") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(193, "GPIO193"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO193") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(194, "GPIO194"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO194") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(195, "GPIO195"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO195") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(196, "GPIO196"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO196") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(197, "GPIO197"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO197") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(198, "GPIO198"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO198") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(199, "SPI1_CK"), ++ "E19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO199"), ++ MTK_FUNCTION(1, "SPI1_CK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(200, "URXD2"), ++ "K18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO200"), ++ MTK_FUNCTION(6, "URXD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(201, "UTXD2"), ++ "L18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO201"), ++ MTK_FUNCTION(6, "UTXD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(202, "GPIO202"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO202") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(203, "PWM0"), ++ "AA16", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO203"), ++ MTK_FUNCTION(1, "PWM0"), ++ MTK_FUNCTION(2, "DISP_PWM") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(204, "PWM1"), ++ "Y16", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO204"), ++ MTK_FUNCTION(1, "PWM1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(205, "PWM2"), ++ "AA15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO205"), ++ MTK_FUNCTION(1, "PWM2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(206, "PWM3"), ++ "AA17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO206"), ++ MTK_FUNCTION(1, "PWM3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(207, "PWM4"), ++ "Y15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO207"), ++ MTK_FUNCTION(1, "PWM4") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(208, "AUD_EXT_CK1"), ++ "W14", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO208"), ++ MTK_FUNCTION(1, "AUD_EXT_CK1"), ++ MTK_FUNCTION(2, "PWM0"), ++ MTK_FUNCTION(3, "PCIE0_PERST_N"), ++ MTK_FUNCTION(5, "DISP_PWM") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(209, "AUD_EXT_CK2"), ++ "V15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO209"), ++ MTK_FUNCTION(1, "AUD_EXT_CK2"), ++ MTK_FUNCTION(2, "MSDC1_WP"), ++ MTK_FUNCTION(3, "PCIE1_PERST_N"), ++ MTK_FUNCTION(5, "PWM1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(210, "GPIO210"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO210") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(211, "GPIO211"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO211") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(212, "GPIO212"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO212") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(213, "GPIO213"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO213") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(214, "GPIO214"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO214") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(215, "GPIO215"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO215") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(216, "GPIO216"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO216") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(217, "GPIO217"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO217") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(218, "GPIO218"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO218") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(219, "GPIO219"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO219") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(220, "GPIO220"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO220") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(221, "GPIO221"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO221") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(222, "GPIO222"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO222") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(223, "GPIO223"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO223") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(224, "GPIO224"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO224") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(225, "GPIO225"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO225") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(226, "GPIO226"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO226") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(227, "GPIO227"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO227") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(228, "GPIO228"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO228") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(229, "GPIO229"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO229") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(230, "GPIO230"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO230") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(231, "GPIO231"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO231") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(232, "GPIO232"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO232") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(233, "GPIO233"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO233") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(234, "GPIO234"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO234") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(235, "GPIO235"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO235") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(236, "EXT_SDIO3"), ++ "A8", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO236"), ++ MTK_FUNCTION(1, "EXT_SDIO3"), ++ MTK_FUNCTION(2, "IDDIG") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(237, "EXT_SDIO2"), ++ "D8", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO237"), ++ MTK_FUNCTION(1, "EXT_SDIO2"), ++ MTK_FUNCTION(2, "DRV_VBUS") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(238, "EXT_SDIO1"), ++ "D9", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO238"), ++ MTK_FUNCTION(1, "EXT_SDIO1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(239, "EXT_SDIO0"), ++ "B8", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO239"), ++ MTK_FUNCTION(1, "EXT_SDIO0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(240, "EXT_XCS"), ++ "C9", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO240"), ++ MTK_FUNCTION(1, "EXT_XCS") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(241, "EXT_SCK"), ++ "C8", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO241"), ++ MTK_FUNCTION(1, "EXT_SCK") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(242, "URTS2"), ++ "G18", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO242"), ++ MTK_FUNCTION(1, "URTS2"), ++ MTK_FUNCTION(2, "UTXD3"), ++ MTK_FUNCTION(3, "URXD3"), ++ MTK_FUNCTION(4, "SCL1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(243, "UCTS2"), ++ "H19", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO243"), ++ MTK_FUNCTION(1, "UCTS2"), ++ MTK_FUNCTION(2, "URXD3"), ++ MTK_FUNCTION(3, "UTXD3"), ++ MTK_FUNCTION(4, "SDA1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(244, "GPIO244"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO244") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(245, "GPIO245"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO245") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(246, "GPIO246"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO246") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(247, "GPIO247"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO247") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(248, "GPIO248"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO248") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(249, "GPIO249"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO249") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(250, "GPIO250"), ++ "A15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO250"), ++ MTK_FUNCTION(1, "TEST_MD7"), ++ MTK_FUNCTION(6, "PCIE0_CLKREQ_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(251, "GPIO251"), ++ "B15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO251"), ++ MTK_FUNCTION(1, "TEST_MD6"), ++ MTK_FUNCTION(6, "PCIE0_WAKE_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(252, "GPIO252"), ++ "C16", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO252"), ++ MTK_FUNCTION(1, "TEST_MD5"), ++ MTK_FUNCTION(6, "PCIE1_CLKREQ_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(253, "GPIO253"), ++ "D17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO253"), ++ MTK_FUNCTION(1, "TEST_MD4"), ++ MTK_FUNCTION(6, "PCIE1_WAKE_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(254, "GPIO254"), ++ "D16", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO254"), ++ MTK_FUNCTION(1, "TEST_MD3"), ++ MTK_FUNCTION(6, "PCIE2_CLKREQ_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(255, "GPIO255"), ++ "C17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO255"), ++ MTK_FUNCTION(1, "TEST_MD2"), ++ MTK_FUNCTION(6, "PCIE2_WAKE_N") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(256, "GPIO256"), ++ "B17", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO256"), ++ MTK_FUNCTION(1, "TEST_MD1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(257, "GPIO257"), ++ "C15", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO257"), ++ MTK_FUNCTION(1, "TEST_MD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(258, "GPIO258"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO258") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(259, "GPIO259"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO259") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(260, "GPIO260"), ++ "N/C", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), MTK_FUNCTION(0, "GPIO260") ++ ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(261, "MSDC1_INS"), ++ "AD1", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO261"), ++ MTK_FUNCTION(1, "MSDC1_INS") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(262, "G2_TXEN"), ++ "A23", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO262"), ++ MTK_FUNCTION(1, "G2_TXEN") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(263, "G2_TXD3"), ++ "N/A", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO263"), ++ MTK_FUNCTION(1, "G2_TXD3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(264, "G2_TXD2"), ++ "C24", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO264"), ++ MTK_FUNCTION(1, "G2_TXD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(265, "G2_TXD1"), ++ "B25", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO265"), ++ MTK_FUNCTION(1, "G2_TXD1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(266, "G2_TXD0"), ++ "A24", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO266"), ++ MTK_FUNCTION(1, "G2_TXD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(267, "G2_TXCLK"), ++ "C23", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO267"), ++ MTK_FUNCTION(1, "G2_TXC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(268, "G2_RXCLK"), ++ "B23", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO268"), ++ MTK_FUNCTION(1, "G2_RXC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(269, "G2_RXD0"), ++ "D21", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO269"), ++ MTK_FUNCTION(1, "G2_RXD0") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(270, "G2_RXD1"), ++ "B22", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO270"), ++ MTK_FUNCTION(1, "G2_RXD1") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(271, "G2_RXD2"), ++ "A22", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO271"), ++ MTK_FUNCTION(1, "G2_RXD2") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(272, "G2_RXD3"), ++ "C22", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO272"), ++ MTK_FUNCTION(1, "G2_RXD3") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(273, "D2D_ESW_INT"), ++ "N/A", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO273"), ++ MTK_FUNCTION(1, "ESW_INT") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(274, "G2_RXDV"), ++ "C21", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO274"), ++ MTK_FUNCTION(1, "G2_RXDV") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(275, "G2_MDC"), ++ "N/A", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO275"), ++ MTK_FUNCTION(1, "MDC") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(276, "G2_MDIO"), ++ "N/A", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO276"), ++ MTK_FUNCTION(1, "MDIO") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(277, "D2D_ESW_RSTN"), ++ "N/A", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO277"), ++ MTK_FUNCTION(1, "ESW_RST") ++ ), ++ MTK_PIN( ++ PINCTRL_PIN(278, "JTAG_RESET"), ++ "H20", "mt7623", ++ MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), ++ MTK_FUNCTION(0, "GPIO278"), ++ MTK_FUNCTION(1, "JTAG_RESET") ++ ), ++}; ++ ++#endif /* __PINCTRL_MTK_MT7623_H */ +\ No newline at end of file +diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h +new file mode 100644 +index 0000000..826835c +--- /dev/null ++++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h +@@ -0,0 +1,526 @@ ++#ifndef __DTS_MT7623_PINFUNC_H ++#define __DTS_MT7623_PINFUNC_H ++ ++#include ++ ++#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_GPIO0 (MTK_PIN_NO(0) | 0) ++#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1) ++#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2) ++ ++#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_GPIO1 (MTK_PIN_NO(1) | 0) ++#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1) ++#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2) ++ ++#define MT7623_PIN_2_PWRAP_INT_FUNC_GPIO2 (MTK_PIN_NO(2) | 0) ++#define MT7623_PIN_2_PWRAP_INT_FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1) ++ ++#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_GPIO3 (MTK_PIN_NO(3) | 0) ++#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1) ++ ++#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_GPIO4 (MTK_PIN_NO(4) | 0) ++#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1) ++ ++#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0) ++#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) ++ ++#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0) ++#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) ++ ++#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0) ++#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) ++ ++#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0) ++#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) ++#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) ++ ++#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0) ++#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) ++#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) ++ ++#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0) ++#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) ++ ++#define MT7623_PIN_11_WATCHDOG_FUNC_GPIO11 (MTK_PIN_NO(11) | 0) ++#define MT7623_PIN_11_WATCHDOG_FUNC_WATCHDOG (MTK_PIN_NO(11) | 1) ++ ++#define MT7623_PIN_12_SRCLKENA_FUNC_GPIO12 (MTK_PIN_NO(12) | 0) ++#define MT7623_PIN_12_SRCLKENA_FUNC_SRCLKENA (MTK_PIN_NO(12) | 1) ++ ++#define MT7623_PIN_13_SRCLKENAI_FUNC_GPIO13 (MTK_PIN_NO(13) | 0) ++#define MT7623_PIN_13_SRCLKENAI_FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1) ++ ++#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0) ++#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1) ++#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2) ++ ++#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0) ++#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1) ++#define MT7623_PIN_15_GPIO15_FUNC_URXD2 (MTK_PIN_NO(15) | 2) ++ ++#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0) ++#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) ++#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6) ++ ++#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0) ++#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) ++#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6) ++ ++#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0) ++#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1) ++#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4) ++#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6) ++ ++#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0) ++#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1) ++#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4) ++#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6) ++ ++#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0) ++#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1) ++#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2) ++ ++#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0) ++#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1) ++#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2) ++ ++#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0) ++#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1) ++#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2) ++ ++#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0) ++#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1) ++ ++#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0) ++#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1) ++#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) ++ ++#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0) ++#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1) ++#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) ++ ++#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0) ++#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) ++#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) ++ ++#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0) ++#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1) ++#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) ++#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6) ++ ++#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0) ++#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) ++#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3) ++#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6) ++ ++#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0) ++#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) ++#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3) ++#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6) ++ ++#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0) ++#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) ++#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) ++#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6) ++ ++#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0) ++#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) ++#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) ++#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6) ++ ++#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0) ++#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) ++ ++#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0) ++#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1) ++ ++#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0) ++#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1) ++ ++#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0) ++#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1) ++ ++#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0) ++#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1) ++ ++#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0) ++#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1) ++#define MT7623_PIN_43_NCLE_FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2) ++ ++#define MT7623_PIN_44_NCEB1_FUNC_GPIO44 (MTK_PIN_NO(44) | 0) ++#define MT7623_PIN_44_NCEB1_FUNC_NCEB1 (MTK_PIN_NO(44) | 1) ++#define MT7623_PIN_44_NCEB1_FUNC_IDDIG (MTK_PIN_NO(44) | 2) ++ ++#define MT7623_PIN_45_NCEB0_FUNC_GPIO45 (MTK_PIN_NO(45) | 0) ++#define MT7623_PIN_45_NCEB0_FUNC_NCEB0 (MTK_PIN_NO(45) | 1) ++#define MT7623_PIN_45_NCEB0_FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2) ++ ++#define MT7623_PIN_46_IR_FUNC_GPIO46 (MTK_PIN_NO(46) | 0) ++#define MT7623_PIN_46_IR_FUNC_IR (MTK_PIN_NO(46) | 1) ++ ++#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0) ++#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1) ++ ++#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0) ++#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1) ++ ++#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0) ++#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) ++#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3) ++#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6) ++ ++#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0) ++#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) ++#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5) ++ ++#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0) ++#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) ++ ++#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0) ++#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) ++#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) ++#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) ++#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5) ++ ++#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0) ++#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) ++#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) ++ ++#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0) ++#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1) ++ ++#define MT7623_PIN_61_GPIO61_FUNC_GPIO61 (MTK_PIN_NO(61) | 0) ++#define MT7623_PIN_61_GPIO61_FUNC_TEST_FD (MTK_PIN_NO(61) | 1) ++ ++#define MT7623_PIN_62_GPIO62_FUNC_GPIO62 (MTK_PIN_NO(62) | 0) ++#define MT7623_PIN_62_GPIO62_FUNC_TEST_FC (MTK_PIN_NO(62) | 1) ++ ++#define MT7623_PIN_63_WB_SCLK_FUNC_GPIO63 (MTK_PIN_NO(63) | 0) ++#define MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK (MTK_PIN_NO(63) | 1) ++ ++#define MT7623_PIN_64_WB_SDATA_FUNC_GPIO64 (MTK_PIN_NO(64) | 0) ++#define MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA (MTK_PIN_NO(64) | 1) ++ ++#define MT7623_PIN_65_WB_SEN_FUNC_GPIO65 (MTK_PIN_NO(65) | 0) ++#define MT7623_PIN_65_WB_SEN_FUNC_WB_SEN (MTK_PIN_NO(65) | 1) ++ ++#define MT7623_PIN_66_WB_CRTL0_FUNC_GPIO66 (MTK_PIN_NO(66) | 0) ++#define MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1) ++ ++#define MT7623_PIN_67_WB_CRTL1_FUNC_GPIO67 (MTK_PIN_NO(67) | 0) ++#define MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1) ++ ++#define MT7623_PIN_68_WB_CRTL2_FUNC_GPIO68 (MTK_PIN_NO(68) | 0) ++#define MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1) ++ ++#define MT7623_PIN_69_WB_CRTL3_FUNC_GPIO69 (MTK_PIN_NO(69) | 0) ++#define MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1) ++ ++#define MT7623_PIN_70_WB_CRTL4_FUNC_GPIO70 (MTK_PIN_NO(70) | 0) ++#define MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1) ++ ++#define MT7623_PIN_71_WB_CRTL5_FUNC_GPIO71 (MTK_PIN_NO(71) | 0) ++#define MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1) ++ ++#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_GPIO72 (MTK_PIN_NO(72) | 0) ++#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1) ++#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(72) | 3) ++#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PWM0 (MTK_PIN_NO(72) | 4) ++#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_DISP_PWM (MTK_PIN_NO(72) | 5) ++#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_AP_I2S_DI (MTK_PIN_NO(72) | 6) ++ ++#define MT7623_PIN_73_I2S0_LRCK_FUNC_GPIO73 (MTK_PIN_NO(73) | 0) ++#define MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1) ++#define MT7623_PIN_73_I2S0_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3) ++#define MT7623_PIN_73_I2S0_LRCK_FUNC_AP_I2S_LRCK (MTK_PIN_NO(73) | 6) ++ ++#define MT7623_PIN_74_I2S0_BCK_FUNC_GPIO74 (MTK_PIN_NO(74) | 0) ++#define MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1) ++#define MT7623_PIN_74_I2S0_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3) ++#define MT7623_PIN_74_I2S0_BCK_FUNC_AP_I2S_BCK (MTK_PIN_NO(74) | 6) ++ ++#define MT7623_PIN_75_SDA0_FUNC_GPIO75 (MTK_PIN_NO(75) | 0) ++#define MT7623_PIN_75_SDA0_FUNC_SDA0 (MTK_PIN_NO(75) | 1) ++ ++#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0) ++#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1) ++ ++#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0) ++#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1) ++ ++#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0) ++#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1) ++ ++#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0) ++#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1) ++ ++#define MT7623_PIN_96_MIPI_TCP_FUNC_GPIO96 (MTK_PIN_NO(96) | 0) ++#define MT7623_PIN_96_MIPI_TCP_FUNC_TCP (MTK_PIN_NO(96) | 1) ++ ++#define MT7623_PIN_97_MIPI_TDN1_FUNC_GPIO97 (MTK_PIN_NO(97) | 0) ++#define MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1 (MTK_PIN_NO(97) | 1) ++ ++#define MT7623_PIN_98_MIPI_TDP1_FUNC_GPIO98 (MTK_PIN_NO(98) | 0) ++#define MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1 (MTK_PIN_NO(98) | 1) ++ ++#define MT7623_PIN_99_MIPI_TDN0_FUNC_GPIO99 (MTK_PIN_NO(99) | 0) ++#define MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0 (MTK_PIN_NO(99) | 1) ++ ++#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0) ++#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1) ++ ++#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0) ++#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) ++#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3) ++#define MT7623_PIN_105_MSDC1_CMD_FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6) ++ ++#define MT7623_PIN_106_MSDC1_CLK_FUNC_GPIO106 (MTK_PIN_NO(106) | 0) ++#define MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1) ++#define MT7623_PIN_106_MSDC1_CLK_FUNC_SCL1 (MTK_PIN_NO(106) | 3) ++#define MT7623_PIN_106_MSDC1_CLK_FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6) ++ ++#define MT7623_PIN_107_MSDC1_DAT0_FUNC_GPIO107 (MTK_PIN_NO(107) | 0) ++#define MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1) ++#define MT7623_PIN_107_MSDC1_DAT0_FUNC_UTXD0 (MTK_PIN_NO(107) | 5) ++#define MT7623_PIN_107_MSDC1_DAT0_FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6) ++ ++#define MT7623_PIN_108_MSDC1_DAT1_FUNC_GPIO108 (MTK_PIN_NO(108) | 0) ++#define MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1) ++#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM0 (MTK_PIN_NO(108) | 3) ++#define MT7623_PIN_108_MSDC1_DAT1_FUNC_URXD0 (MTK_PIN_NO(108) | 5) ++#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM1 (MTK_PIN_NO(108) | 6) ++ ++#define MT7623_PIN_109_MSDC1_DAT2_FUNC_GPIO109 (MTK_PIN_NO(109) | 0) ++#define MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1) ++#define MT7623_PIN_109_MSDC1_DAT2_FUNC_SDA2 (MTK_PIN_NO(109) | 3) ++#define MT7623_PIN_109_MSDC1_DAT2_FUNC_UTXD1 (MTK_PIN_NO(109) | 5) ++#define MT7623_PIN_109_MSDC1_DAT2_FUNC_PWM2 (MTK_PIN_NO(109) | 6) ++ ++#define MT7623_PIN_110_MSDC1_DAT3_FUNC_GPIO110 (MTK_PIN_NO(110) | 0) ++#define MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1) ++#define MT7623_PIN_110_MSDC1_DAT3_FUNC_SCL2 (MTK_PIN_NO(110) | 3) ++#define MT7623_PIN_110_MSDC1_DAT3_FUNC_URXD1 (MTK_PIN_NO(110) | 5) ++#define MT7623_PIN_110_MSDC1_DAT3_FUNC_PWM3 (MTK_PIN_NO(110) | 6) ++ ++#define MT7623_PIN_111_MSDC0_DAT7_FUNC_GPIO111 (MTK_PIN_NO(111) | 0) ++#define MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1) ++#define MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7 (MTK_PIN_NO(111) | 4) ++ ++#define MT7623_PIN_112_MSDC0_DAT6_FUNC_GPIO112 (MTK_PIN_NO(112) | 0) ++#define MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1) ++#define MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6 (MTK_PIN_NO(112) | 4) ++ ++#define MT7623_PIN_113_MSDC0_DAT5_FUNC_GPIO113 (MTK_PIN_NO(113) | 0) ++#define MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1) ++#define MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5 (MTK_PIN_NO(113) | 4) ++ ++#define MT7623_PIN_114_MSDC0_DAT4_FUNC_GPIO114 (MTK_PIN_NO(114) | 0) ++#define MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1) ++#define MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4 (MTK_PIN_NO(114) | 4) ++ ++#define MT7623_PIN_115_MSDC0_RSTB_FUNC_GPIO115 (MTK_PIN_NO(115) | 0) ++#define MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1) ++#define MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8 (MTK_PIN_NO(115) | 4) ++ ++#define MT7623_PIN_116_MSDC0_CMD_FUNC_GPIO116 (MTK_PIN_NO(116) | 0) ++#define MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1) ++#define MT7623_PIN_116_MSDC0_CMD_FUNC_NALE (MTK_PIN_NO(116) | 4) ++ ++#define MT7623_PIN_117_MSDC0_CLK_FUNC_GPIO117 (MTK_PIN_NO(117) | 0) ++#define MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1) ++#define MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB (MTK_PIN_NO(117) | 4) ++ ++#define MT7623_PIN_118_MSDC0_DAT3_FUNC_GPIO118 (MTK_PIN_NO(118) | 0) ++#define MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1) ++#define MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3 (MTK_PIN_NO(118) | 4) ++ ++#define MT7623_PIN_119_MSDC0_DAT2_FUNC_GPIO119 (MTK_PIN_NO(119) | 0) ++#define MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1) ++#define MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2 (MTK_PIN_NO(119) | 4) ++ ++#define MT7623_PIN_120_MSDC0_DAT1_FUNC_GPIO120 (MTK_PIN_NO(120) | 0) ++#define MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1) ++#define MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1 (MTK_PIN_NO(120) | 4) ++ ++#define MT7623_PIN_121_MSDC0_DAT0_FUNC_GPIO121 (MTK_PIN_NO(121) | 0) ++#define MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1) ++#define MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0 (MTK_PIN_NO(121) | 4) ++#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) ++ ++#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0) ++#define MT7623_PIN_122_GPIO122_FUNC_TEST (MTK_PIN_NO(122) | 1) ++#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4) ++#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5) ++ ++#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0) ++#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1) ++#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4) ++#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5) ++ ++#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0) ++#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1) ++#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4) ++#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5) ++ ++#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0) ++#define MT7623_PIN_125_GPIO125_FUNC_TEST (MTK_PIN_NO(125) | 1) ++#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4) ++#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5) ++ ++#define MT7623_PIN_126_I2S0_MCLK_FUNC_GPIO126 (MTK_PIN_NO(126) | 0) ++#define MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1) ++#define MT7623_PIN_126_I2S0_MCLK_FUNC_AP_I2S_MCLK (MTK_PIN_NO(126) | 6) ++ ++#define MT7623_PIN_199_SPI1_CK_FUNC_GPIO199 (MTK_PIN_NO(199) | 0) ++#define MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK (MTK_PIN_NO(199) | 1) ++ ++#define MT7623_PIN_200_URXD2_FUNC_GPIO200 (MTK_PIN_NO(200) | 0) ++#define MT7623_PIN_200_URXD2_FUNC_URXD2 (MTK_PIN_NO(200) | 6) ++ ++#define MT7623_PIN_201_UTXD2_FUNC_GPIO201 (MTK_PIN_NO(201) | 0) ++#define MT7623_PIN_201_UTXD2_FUNC_UTXD2 (MTK_PIN_NO(201) | 6) ++ ++#define MT7623_PIN_203_PWM0_FUNC_GPIO203 (MTK_PIN_NO(203) | 0) ++#define MT7623_PIN_203_PWM0_FUNC_PWM0 (MTK_PIN_NO(203) | 1) ++#define MT7623_PIN_203_PWM0_FUNC_DISP_PWM (MTK_PIN_NO(203) | 2) ++ ++#define MT7623_PIN_204_PWM1_FUNC_GPIO204 (MTK_PIN_NO(204) | 0) ++#define MT7623_PIN_204_PWM1_FUNC_PWM1 (MTK_PIN_NO(204) | 1) ++ ++#define MT7623_PIN_205_PWM2_FUNC_GPIO205 (MTK_PIN_NO(205) | 0) ++#define MT7623_PIN_205_PWM2_FUNC_PWM2 (MTK_PIN_NO(205) | 1) ++ ++#define MT7623_PIN_206_PWM3_FUNC_GPIO206 (MTK_PIN_NO(206) | 0) ++#define MT7623_PIN_206_PWM3_FUNC_PWM3 (MTK_PIN_NO(206) | 1) ++ ++#define MT7623_PIN_207_PWM4_FUNC_GPIO207 (MTK_PIN_NO(207) | 0) ++#define MT7623_PIN_207_PWM4_FUNC_PWM4 (MTK_PIN_NO(207) | 1) ++ ++#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_GPIO208 (MTK_PIN_NO(208) | 0) ++#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1) ++#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PWM0 (MTK_PIN_NO(208) | 2) ++#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 3) ++#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_DISP_PWM (MTK_PIN_NO(208) | 5) ++ ++#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_GPIO209 (MTK_PIN_NO(209) | 0) ++#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1) ++#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2) ++#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 3) ++#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PWM1 (MTK_PIN_NO(209) | 5) ++ ++#define MT7623_PIN_236_EXT_SDIO3_FUNC_GPIO236 (MTK_PIN_NO(236) | 0) ++#define MT7623_PIN_236_EXT_SDIO3_FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1) ++#define MT7623_PIN_236_EXT_SDIO3_FUNC_IDDIG (MTK_PIN_NO(236) | 2) ++ ++#define MT7623_PIN_237_EXT_SDIO2_FUNC_GPIO237 (MTK_PIN_NO(237) | 0) ++#define MT7623_PIN_237_EXT_SDIO2_FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1) ++#define MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2) ++ ++#define MT7623_PIN_238_EXT_SDIO1_FUNC_GPIO238 (MTK_PIN_NO(238) | 0) ++#define MT7623_PIN_238_EXT_SDIO1_FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1) ++ ++#define MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239 (MTK_PIN_NO(239) | 0) ++#define MT7623_PIN_239_EXT_SDIO0_FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1) ++ ++#define MT7623_PIN_240_EXT_XCS_FUNC_GPIO240 (MTK_PIN_NO(240) | 0) ++#define MT7623_PIN_240_EXT_XCS_FUNC_EXT_XCS (MTK_PIN_NO(240) | 1) ++ ++#define MT7623_PIN_241_EXT_SCK_FUNC_GPIO241 (MTK_PIN_NO(241) | 0) ++#define MT7623_PIN_241_EXT_SCK_FUNC_EXT_SCK (MTK_PIN_NO(241) | 1) ++ ++#define MT7623_PIN_242_URTS2_FUNC_GPIO242 (MTK_PIN_NO(242) | 0) ++#define MT7623_PIN_242_URTS2_FUNC_URTS2 (MTK_PIN_NO(242) | 1) ++#define MT7623_PIN_242_URTS2_FUNC_UTXD3 (MTK_PIN_NO(242) | 2) ++#define MT7623_PIN_242_URTS2_FUNC_URXD3 (MTK_PIN_NO(242) | 3) ++#define MT7623_PIN_242_URTS2_FUNC_SCL1 (MTK_PIN_NO(242) | 4) ++ ++#define MT7623_PIN_243_UCTS2_FUNC_GPIO243 (MTK_PIN_NO(243) | 0) ++#define MT7623_PIN_243_UCTS2_FUNC_UCTS2 (MTK_PIN_NO(243) | 1) ++#define MT7623_PIN_243_UCTS2_FUNC_URXD3 (MTK_PIN_NO(243) | 2) ++#define MT7623_PIN_243_UCTS2_FUNC_UTXD3 (MTK_PIN_NO(243) | 3) ++#define MT7623_PIN_243_UCTS2_FUNC_SDA1 (MTK_PIN_NO(243) | 4) ++ ++#define MT7623_PIN_250_GPIO250_FUNC_GPIO250 (MTK_PIN_NO(250) | 0) ++#define MT7623_PIN_250_GPIO250_FUNC_TEST_MD7 (MTK_PIN_NO(250) | 1) ++#define MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 6) ++ ++#define MT7623_PIN_251_GPIO251_FUNC_GPIO251 (MTK_PIN_NO(251) | 0) ++#define MT7623_PIN_251_GPIO251_FUNC_TEST_MD6 (MTK_PIN_NO(251) | 1) ++#define MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 6) ++ ++#define MT7623_PIN_252_GPIO252_FUNC_GPIO252 (MTK_PIN_NO(252) | 0) ++#define MT7623_PIN_252_GPIO252_FUNC_TEST_MD5 (MTK_PIN_NO(252) | 1) ++#define MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 6) ++ ++#define MT7623_PIN_253_GPIO253_FUNC_GPIO253 (MTK_PIN_NO(253) | 0) ++#define MT7623_PIN_253_GPIO253_FUNC_TEST_MD4 (MTK_PIN_NO(253) | 1) ++#define MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 6) ++ ++#define MT7623_PIN_254_GPIO254_FUNC_GPIO254 (MTK_PIN_NO(254) | 0) ++#define MT7623_PIN_254_GPIO254_FUNC_TEST_MD3 (MTK_PIN_NO(254) | 1) ++#define MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 6) ++ ++#define MT7623_PIN_255_GPIO255_FUNC_GPIO255 (MTK_PIN_NO(255) | 0) ++#define MT7623_PIN_255_GPIO255_FUNC_TEST_MD2 (MTK_PIN_NO(255) | 1) ++#define MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 6) ++ ++#define MT7623_PIN_256_GPIO256_FUNC_GPIO256 (MTK_PIN_NO(256) | 0) ++#define MT7623_PIN_256_GPIO256_FUNC_TEST_MD1 (MTK_PIN_NO(256) | 1) ++ ++#define MT7623_PIN_257_GPIO257_FUNC_GPIO257 (MTK_PIN_NO(257) | 0) ++#define MT7623_PIN_257_GPIO257_FUNC_TEST_MD0 (MTK_PIN_NO(257) | 1) ++ ++#define MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261 (MTK_PIN_NO(261) | 0) ++#define MT7623_PIN_261_MSDC1_INS_FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1) ++ ++#define MT7623_PIN_262_G2_TXEN_FUNC_GPIO262 (MTK_PIN_NO(262) | 0) ++#define MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN (MTK_PIN_NO(262) | 1) ++ ++#define MT7623_PIN_263_G2_TXD3_FUNC_GPIO263 (MTK_PIN_NO(263) | 0) ++#define MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1) ++ ++#define MT7623_PIN_264_G2_TXD2_FUNC_GPIO264 (MTK_PIN_NO(264) | 0) ++#define MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1) ++ ++#define MT7623_PIN_265_G2_TXD1_FUNC_GPIO265 (MTK_PIN_NO(265) | 0) ++#define MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1) ++ ++#define MT7623_PIN_266_G2_TXD0_FUNC_GPIO266 (MTK_PIN_NO(266) | 0) ++#define MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1) ++ ++#define MT7623_PIN_267_G2_TXCLK_FUNC_GPIO267 (MTK_PIN_NO(267) | 0) ++#define MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC (MTK_PIN_NO(267) | 1) ++ ++#define MT7623_PIN_268_G2_RXCLK_FUNC_GPIO268 (MTK_PIN_NO(268) | 0) ++#define MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC (MTK_PIN_NO(268) | 1) ++ ++#define MT7623_PIN_269_G2_RXD0_FUNC_GPIO269 (MTK_PIN_NO(269) | 0) ++#define MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1) ++ ++#define MT7623_PIN_270_G2_RXD1_FUNC_GPIO270 (MTK_PIN_NO(270) | 0) ++#define MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1) ++ ++#define MT7623_PIN_271_G2_RXD2_FUNC_GPIO271 (MTK_PIN_NO(271) | 0) ++#define MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1) ++ ++#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0) ++#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1) ++ ++#define MT7623_PIN_273_D2D_ESW_INT_FUNC_GPIO273 (MTK_PIN_NO(273) | 0) ++#define MT7623_PIN_273_D2D_ESW_INT_FUNC_ESW_INT (MTK_PIN_NO(273) | 1) ++ ++#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0) ++#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1) ++ ++#define MT7623_PIN_275_G2_MDC_FUNC_GPIO275 (MTK_PIN_NO(275) | 0) ++#define MT7623_PIN_275_G2_MDC_FUNC_MDC (MTK_PIN_NO(275) | 1) ++ ++#define MT7623_PIN_276_G2_MDIO_FUNC_GPIO276 (MTK_PIN_NO(276) | 0) ++#define MT7623_PIN_276_G2_MDIO_FUNC_MDIO (MTK_PIN_NO(276) | 1) ++ ++#define MT7623_PIN_277_D2D_ESW_RSTN_FUNC_GPIO277 (MTK_PIN_NO(277) | 0) ++#define MT7623_PIN_277_D2D_ESW_RSTN_FUNC_ESW_RST (MTK_PIN_NO(277) | 1) ++ ++#define MT7623_PIN_278_JTAG_RESET_FUNC_GPIO278 (MTK_PIN_NO(278) | 0) ++#define MT7623_PIN_278_JTAG_RESET_FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1) ++ ++#endif /* __DTS_MT7623_PINFUNC_H */ +\ No newline at end of file +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0063-arm-mediatek-add-SDK-ethernet.patch b/target/linux/mediatek/patches/0063-arm-mediatek-add-SDK-ethernet.patch new file mode 100644 index 0000000..7263bb2 --- /dev/null +++ b/target/linux/mediatek/patches/0063-arm-mediatek-add-SDK-ethernet.patch @@ -0,0 +1,20654 @@ +From e3aece79d5003b6879298b05551e113117d5cdd8 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:13:36 +0200 +Subject: [PATCH 63/76] arm: mediatek: add SDK ethernet + +Signed-off-by: John Crispin +--- + drivers/net/ethernet/Kconfig | 1 + + drivers/net/ethernet/Makefile | 1 + + drivers/net/ethernet/raeth/Kconfig | 415 ++ + drivers/net/ethernet/raeth/Makefile | 67 + + drivers/net/ethernet/raeth/Makefile.release | 60 + + drivers/net/ethernet/raeth/csr_netlink.h | 27 + + drivers/net/ethernet/raeth/dvt/pkt_gen.c | 88 + + drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c | 138 + + drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c | 191 + + drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c | 1527 +++++ + drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h | 75 + + drivers/net/ethernet/raeth/ethtool_readme.txt | 44 + + drivers/net/ethernet/raeth/mcast.c | 187 + + drivers/net/ethernet/raeth/mii_mgr.c | 603 ++ + drivers/net/ethernet/raeth/ra2882ethreg.h | 1985 +++++++ + drivers/net/ethernet/raeth/ra_ethtool.c | 515 ++ + drivers/net/ethernet/raeth/ra_ethtool.h | 13 + + drivers/net/ethernet/raeth/ra_ioctl.h | 102 + + drivers/net/ethernet/raeth/ra_mac.c | 2645 +++++++++ + drivers/net/ethernet/raeth/ra_mac.h | 57 + + drivers/net/ethernet/raeth/ra_netlink.c | 142 + + drivers/net/ethernet/raeth/ra_netlink.h | 10 + + drivers/net/ethernet/raeth/ra_qos.c | 655 +++ + drivers/net/ethernet/raeth/ra_qos.h | 18 + + drivers/net/ethernet/raeth/ra_rfrw.c | 66 + + drivers/net/ethernet/raeth/ra_rfrw.h | 6 + + drivers/net/ethernet/raeth/raether.c | 6401 +++++++++++++++++++++ + drivers/net/ethernet/raeth/raether.h | 126 + + drivers/net/ethernet/raeth/raether_hwlro.c | 347 ++ + drivers/net/ethernet/raeth/raether_pdma.c | 1121 ++++ + drivers/net/ethernet/raeth/raether_qdma.c | 1407 +++++ + drivers/net/ethernet/raeth/raether_qdma_mt7623.c | 1020 ++++ + drivers/net/ethernet/raeth/smb_hook.c | 17 + + drivers/net/ethernet/raeth/smb_nf.c | 177 + + drivers/net/ethernet/raeth/sync_write.h | 103 + + 35 files changed, 20357 insertions(+) + create mode 100644 drivers/net/ethernet/raeth/Kconfig + create mode 100644 drivers/net/ethernet/raeth/Makefile + create mode 100644 drivers/net/ethernet/raeth/Makefile.release + create mode 100644 drivers/net/ethernet/raeth/csr_netlink.h + create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen.c + create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c + create mode 100755 drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c + create mode 100755 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c + create mode 100755 drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h + create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt + create mode 100644 drivers/net/ethernet/raeth/mcast.c + create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c + create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h + create mode 100644 drivers/net/ethernet/raeth/ra_ethtool.c + create mode 100644 drivers/net/ethernet/raeth/ra_ethtool.h + create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h + create mode 100644 drivers/net/ethernet/raeth/ra_mac.c + create mode 100644 drivers/net/ethernet/raeth/ra_mac.h + create mode 100644 drivers/net/ethernet/raeth/ra_netlink.c + create mode 100644 drivers/net/ethernet/raeth/ra_netlink.h + create mode 100644 drivers/net/ethernet/raeth/ra_qos.c + create mode 100644 drivers/net/ethernet/raeth/ra_qos.h + create mode 100644 drivers/net/ethernet/raeth/ra_rfrw.c + create mode 100644 drivers/net/ethernet/raeth/ra_rfrw.h + create mode 100644 drivers/net/ethernet/raeth/raether.c + create mode 100644 drivers/net/ethernet/raeth/raether.h + create mode 100755 drivers/net/ethernet/raeth/raether_hwlro.c + create mode 100755 drivers/net/ethernet/raeth/raether_pdma.c + create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c + create mode 100644 drivers/net/ethernet/raeth/raether_qdma_mt7623.c + create mode 100644 drivers/net/ethernet/raeth/smb_hook.c + create mode 100644 drivers/net/ethernet/raeth/smb_nf.c + create mode 100644 drivers/net/ethernet/raeth/sync_write.h + +diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig +index eadcb05..627e1d4 100644 +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -17,6 +17,7 @@ config MDIO + config SUNGEM_PHY + tristate + ++source "drivers/net/ethernet/raeth/Kconfig" + source "drivers/net/ethernet/3com/Kconfig" + source "drivers/net/ethernet/adaptec/Kconfig" + source "drivers/net/ethernet/aeroflex/Kconfig" +diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile +index 1367afc..abdd636 100644 +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -84,3 +84,4 @@ obj-$(CONFIG_NET_VENDOR_VIA) += via/ + obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/ + obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/ + obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/ ++obj-$(CONFIG_RAETH) += raeth/ +diff --git a/drivers/net/ethernet/raeth/Kconfig b/drivers/net/ethernet/raeth/Kconfig +new file mode 100644 +index 0000000..c252c85 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/Kconfig +@@ -0,0 +1,415 @@ ++config ARCH_MT7623 ++ bool ++ default y ++ ++config RA_NAT_NONE ++ bool ++ default y ++ ++config RAETH ++ tristate "Ralink GMAC" ++ ---help--- ++ This driver supports Ralink gigabit ethernet family of ++ adapters. ++ ++config PDMA_NEW ++ bool ++ default y if (RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623) ++ depends on RAETH ++ ++config RAETH_SCATTER_GATHER_RX_DMA ++ bool ++ default y if (RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623) ++ depends on RAETH ++ ++ ++choice ++ prompt "Network BottomHalves" ++ depends on RAETH ++ default RA_NETWORK_WORKQUEUE_BH ++ ++ config RA_NETWORK_TASKLET_BH ++ bool "Tasklet" ++ ++ config RA_NETWORK_WORKQUEUE_BH ++ bool "Work Queue" ++ ++ config RAETH_NAPI ++ bool "NAPI" ++ ++endchoice ++ ++#config TASKLET_WORKQUEUE_SW ++# bool "Tasklet and Workqueue switch" ++# depends on RA_NETWORK_TASKLET_BH ++ ++config RAETH_SKB_RECYCLE_2K ++ bool "SKB Recycling" ++ depends on RAETH ++ ++config RAETH_SPECIAL_TAG ++ bool "Ralink Special Tag (0x810x)" ++ depends on RAETH && RT_3052_ESW ++ ++#config RAETH_JUMBOFRAME ++# bool "Jumbo Frame up to 4K bytes" ++# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628) ++ ++config RAETH_CHECKSUM_OFFLOAD ++ bool "TCP/UDP/IP checksum offload" ++ default y ++ depends on RAETH && !RALINK_RT2880 ++ ++#config RAETH_SW_FC ++# bool "When TX ring is full, inform kernel stop transmit and stop RX handler" ++# default n ++# depends on RAETH ++ ++#config RAETH_8023AZ_EEE ++# bool "Enable Embeded Switch EEE" ++# default n ++# depends on RAETH && (RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628) ++ ++ ++ ++config 32B_DESC ++ bool "32bytes TX/RX description" ++ default n ++ depends on RAETH && (RALINK_MT7620 || RALINK_MT7621) ++ ---help--- ++ At this moment, you cannot enable 32B description with Multiple RX ring at the same time. ++ ++config RAETH_LRO ++ bool "LRO (Large Receive Offload )" ++ select INET_LRO ++ depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || ARCH_MT7623) ++ ++config RAETH_HW_LRO ++ bool "HW LRO (Large Receive Offload)" ++ default n ++ depends on RAETH ++ ++config RAETH_HW_LRO_DBG ++ bool "HW LRO Debug" ++ default n ++ depends on RAETH_HW_LRO ++ ++config RAETH_HW_LRO_AUTO_ADJ_DBG ++ bool "HW LRO Auto Adjustment Debug" ++ default y ++ depends on RAETH_HW_LRO ++ ++config RAETH_HW_LRO_REASON_DBG ++ bool "HW LRO Flush Reason Debug" ++ default n ++ depends on RAETH_HW_LRO ++ ++config RAETH_HW_VLAN_TX ++ bool "Transmit VLAN HW (DoubleVLAN is not supported)" ++ depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628) ++ ---help--- ++ Please disable HW_VLAN_TX if you need double vlan ++ ++config RAETH_HW_VLAN_RX ++ bool "Receive VLAN HW (DoubleVLAN is not supported)" ++ depends on RAETH && RALINK_MT7621 ++ ---help--- ++ Please disable HW_VLAN_RX if you need double vlan ++ ++config RAETH_TSO ++ bool "TSOV4 (Tcp Segmentaton Offload)" ++ depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620))||((RALINK_MT7621 || ARCH_MT7623) &&(RAETH_HW_VLAN_TX || RAETH_GMAC2 )) ++ ++config RAETH_TSOV6 ++ bool "TSOV6 (Tcp Segmentaton Offload)" ++ depends on RAETH_TSO ++ ++config RAETH_RW_PDMAPTR_FROM_VAR ++ bool ++ default y if RALINK_RT6855A || RALINK_MT7620 ++ depends on RAETH ++ ++config MTK_SMB_HOOK ++ bool "Samba Speedup Module" ++ depends on RAETH ++ ++config SPLICE_NET_SUPPORT ++ default y if MTK_SMB_HOOK ++ depends on MTK_SMB_HOOK ++ bool ++ ++ ++config RAETH_DVT ++ bool "RAETH DVT" ++ depends on RAETH && (RALINK_MT7621 || ARCH_MT7623) ++ ++config RAETH_PDMA_DVT ++ bool "PDMA DVT" ++ depends on RAETH_DVT ++ ++config RAETH_PDMA_LEGACY_MODE ++ bool "PDMA legacy mode" ++ depends on RAETH_PDMA_DVT ++ ++#config RAETH_QOS ++# bool "QoS Feature" ++# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO ++ ++choice ++ prompt "QoS Type" ++ depends on RAETH_QOS ++ default DSCP_QOS_DSCP ++ ++config RAETH_QOS_DSCP_BASED ++ bool "DSCP-based" ++ depends on RAETH_QOS ++ ++config RAETH_QOS_VPRI_BASED ++ bool "VPRI-based" ++ depends on RAETH_QOS ++ ++endchoice ++ ++config RAETH_QDMA ++ bool "Choose QDMA instead PDMA" ++ default n ++ depends on RAETH && (RALINK_MT7621 || ARCH_MT7623) ++ ++config RAETH_QDMATX_QDMARX ++ bool "Choose QDMA RX instead PDMA RX" ++ default n ++ depends on RAETH_QDMA && !RALINK_MT7621 ++ ++ ++ ++choice ++ prompt "GMAC is connected to" ++ depends on RAETH ++ default GE1_RGMII_FORCE_1000 ++ ++config GE1_MII_FORCE_100 ++ bool "MII_FORCE_100 (10/100M Switch)" ++ depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621) ++ ++config GE1_MII_AN ++ bool "MII_AN (100Phy)" ++ depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621) ++ ++config GE1_RVMII_FORCE_100 ++ bool "RvMII_FORCE_100 (CPU)" ++ depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621) ++ ++config GE1_RGMII_FORCE_1000 ++ bool "RGMII_FORCE_1000 (GigaSW, CPU)" ++ depends on (RALINK_RT2880 || RALINK_RT3883) ++ select RALINK_SPI ++ ++config GE1_RGMII_FORCE_1000 ++ bool "RGMII_FORCE_1000 (GigaSW, CPU)" ++ depends on (RALINK_MT7621 || ARCH_MT7623) ++ select RT_3052_ESW ++ ++config GE1_TRGMII_FORCE_1200 ++ bool "TRGMII_FORCE_1200 (GigaSW, CPU)" ++ depends on (RALINK_MT7621) ++ select RT_3052_ESW ++ ++config GE1_TRGMII_FORCE_2000 ++ bool "TRGMII_FORCE_2000 (GigaSW, CPU, for MT7623 and MT7683)" ++ depends on (ARCH_MT7623) ++ select RT_3052_ESW ++ ++config GE1_TRGMII_FORCE_2600 ++ bool "TRGMII_FORCE_2600 (GigaSW, CPU, MT7623 only)" ++ depends on (ARCH_MT7623) ++ select RT_3052_ESW ++ ++config GE1_RGMII_AN ++ bool "RGMII_AN (GigaPhy)" ++ depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621 || ARCH_MT7623) ++ ++config GE1_RGMII_NONE ++ bool "NONE (NO CONNECT)" ++ depends on (RALINK_MT7621 || ARCH_MT7623) ++ ++endchoice ++ ++config HW_SFQ ++ bool "HW_SFQ" ++ default n ++ depends on RAETH_QDMA && (ARCH_MT7623) ++ ++ ++config RT_3052_ESW ++ bool "Ralink Embedded Switch" ++ default y ++ depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628 || ARCH_MT7623) ++ ++config LAN_WAN_SUPPORT ++ bool "LAN/WAN Partition" ++ depends on RAETH && (RAETH_ROUTER || RT_3052_ESW) ++ ++config ETH_MEMORY_OPTIMIZATION ++ bool "Ethernet memory optimization" ++ depends on RALINK_MT7628 ++ ++config ETH_ONE_PORT_ONLY ++ bool "One Port Only" ++ depends on RALINK_MT7628 ++ ++choice ++ prompt "Switch Board Layout Type" ++ depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000 ++ default WAN_AT_P0 ++ ++ config WAN_AT_P4 ++ bool "LLLL/W" ++ ++ config WAN_AT_P0 ++ bool "W/LLLL" ++endchoice ++ ++config RALINK_VISTA_BASIC ++ bool 'Vista Basic Logo for IC+ 175C' ++ depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883) ++ ++config ESW_DOUBLE_VLAN_TAG ++ bool ++ default y if RT_3052_ESW ++ ++config RAETH_HAS_PORT4 ++ bool "Port 4 Support" ++ depends on RAETH && RALINK_MT7620 ++choice ++ prompt "Target Mode" ++ depends on RAETH_HAS_PORT4 ++ default P4_RGMII_TO_MAC_MODE ++ ++ config P4_MAC_TO_PHY_MODE ++ bool "Giga_Phy (RGMII)" ++ config GE_RGMII_MT7530_P0_AN ++ bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)" ++ config GE_RGMII_MT7530_P4_AN ++ bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)" ++ config P4_RGMII_TO_MAC_MODE ++ bool "Giga_SW/iNIC (RGMII)" ++ config P4_MII_TO_MAC_MODE ++ bool "External_CPU (MII_RvMII)" ++ config P4_RMII_TO_MAC_MODE ++ bool "External_CPU (RvMII_MII)" ++endchoice ++ ++config MAC_TO_GIGAPHY_MODE_ADDR2 ++ hex "Port4 Phy Address" ++ default 0x4 ++ depends on P4_MAC_TO_PHY_MODE ++ ++config RAETH_HAS_PORT5 ++ bool "Port 5 Support" ++ depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620) ++choice ++ prompt "Target Mode" ++ depends on RAETH_HAS_PORT5 ++ default P5_RGMII_TO_MAC_MODE ++ ++ config P5_MAC_TO_PHY_MODE ++ bool "Giga_Phy (RGMII)" ++ config P5_RGMII_TO_MAC_MODE ++ bool "Giga_SW/iNIC (RGMII)" ++ config P5_RGMII_TO_MT7530_MODE ++ bool "MT7530 Giga_SW (RGMII)" ++ depends on RALINK_MT7620 ++ config P5_MII_TO_MAC_MODE ++ bool "External_CPU (MII_RvMII)" ++ config P5_RMII_TO_MAC_MODE ++ bool "External_CPU (RvMII_MII)" ++endchoice ++ ++config MAC_TO_GIGAPHY_MODE_ADDR ++ hex "GE1 Phy Address" ++ default 0x1F ++ depends on GE1_MII_AN || GE1_RGMII_AN ++ ++config MAC_TO_GIGAPHY_MODE_ADDR ++ hex "Port5 Phy Address" ++ default 0x5 ++ depends on P5_MAC_TO_PHY_MODE ++ ++config RAETH_GMAC2 ++ bool "GMAC2 Support" ++ depends on RAETH && (RALINK_RT3883 || RALINK_MT7621 || ARCH_MT7623) ++ ++choice ++ prompt "GMAC2 is connected to" ++ depends on RAETH_GMAC2 ++ default GE2_RGMII_AN ++ ++config GE2_MII_FORCE_100 ++ bool "MII_FORCE_100 (10/100M Switch)" ++ depends on RAETH_GMAC2 ++ ++config GE2_MII_AN ++ bool "MII_AN (100Phy)" ++ depends on RAETH_GMAC2 ++ ++config GE2_RVMII_FORCE_100 ++ bool "RvMII_FORCE_100 (CPU)" ++ depends on RAETH_GMAC2 ++ ++config GE2_RGMII_FORCE_1000 ++ bool "RGMII_FORCE_1000 (GigaSW, CPU)" ++ depends on RAETH_GMAC2 ++ select RALINK_SPI ++ ++config GE2_RGMII_AN ++ bool "RGMII_AN (External GigaPhy)" ++ depends on RAETH_GMAC2 ++ ++config GE2_INTERNAL_GPHY ++ bool "RGMII_AN (Internal GigaPny)" ++ depends on RAETH_GMAC2 ++ select LAN_WAN_SUPPORT ++ ++endchoice ++ ++config GE_RGMII_INTERNAL_P0_AN ++ bool ++ depends on GE2_INTERNAL_GPHY ++ default y if WAN_AT_P0 ++ ++config GE_RGMII_INTERNAL_P4_AN ++ bool ++ depends on GE2_INTERNAL_GPHY ++ default y if WAN_AT_P4 ++ ++config MAC_TO_GIGAPHY_MODE_ADDR2 ++ hex ++ default 0 if GE_RGMII_INTERNAL_P0_AN ++ default 4 if GE_RGMII_INTERNAL_P4_AN ++ depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN ++ ++config MAC_TO_GIGAPHY_MODE_ADDR2 ++ hex "GE2 Phy Address" ++ default 0x1E ++ depends on GE2_MII_AN || GE2_RGMII_AN ++ ++#force 100M ++config RAETH_ROUTER ++bool ++default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100 ++ ++#force 1000M ++config MAC_TO_MAC_MODE ++bool ++default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000 ++depends on (RALINK_RT2880 || RALINK_RT3883) ++ ++#AN ++config GIGAPHY ++bool ++default y if GE1_RGMII_AN || GE2_RGMII_AN ++ ++#AN ++config 100PHY ++bool ++default y if GE1_MII_AN || GE2_MII_AN +diff --git a/drivers/net/ethernet/raeth/Makefile b/drivers/net/ethernet/raeth/Makefile +new file mode 100644 +index 0000000..563af05 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/Makefile +@@ -0,0 +1,67 @@ ++obj-$(CONFIG_RAETH) += raeth.o ++raeth-objs := ra_mac.o mii_mgr.o ra_rfrw.o ++ ++ifeq ($(CONFIG_MTK_SMB_HOOK),y) ++obj-y += smb_hook.o ++obj-m += smb.o ++smb-objs := smb_nf.o ++endif ++ ++#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING ++ ++ifeq ($(CONFIG_RAETH_QOS),y) ++raeth-objs += ra_qos.o ++endif ++ ++ifeq ($(CONFIG_RAETH_QDMA),y) ++raeth-objs += raether_qdma.o ++endif ++ ++ifneq ($(CONFIG_RAETH_QDMA),y) ++raeth-objs += raether_pdma.o ++endif ++ ++raeth-objs += raether.o ++ ++ifeq ($(CONFIG_ETHTOOL),y) ++raeth-objs += ra_ethtool.o ++endif ++ ++ifeq ($(CONFIG_RALINK_RT3052_MP2),y) ++raeth-objs += mcast.o ++endif ++ ++ifeq ($(CONFIG_RAETH_NETLINK),y) ++raeth-objs += ra_netlink.o ++endif ++ ++ifeq ($(CONFIG_RAETH_PDMA_DVT),y) ++raeth-objs += dvt/raether_pdma_dvt.o ++obj-m += dvt/pkt_gen.o ++obj-m += dvt/pkt_gen_udp_frag.o ++obj-m += dvt/pkt_gen_tcp_frag.o ++endif ++ ++ifeq ($(CONFIG_RAETH_HW_LRO),y) ++raeth-objs += raether_hwlro.o ++endif ++ ++ifeq ($(CONFIG_RAETH_GMAC2),y) ++EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT ++endif ++ ++ifeq ($(CONFIG_ETH_MEMORY_OPTIMIZATION),y) ++EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION ++endif ++ ++ifeq ($(CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION),y) ++EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION ++endif ++ ++ifeq ($(CONFIG_RA_NETWORK_WORKQUEUE_BH),y) ++EXTRA_CFLAGS += -DWORKQUEUE_BH ++endif ++ ++ifeq ($(CONFIG_TASKLET_WORKQUEUE_SW),y) ++EXTRA_CFLAGS += -DTASKLET_WORKQUEUE_SW ++endif +diff --git a/drivers/net/ethernet/raeth/Makefile.release b/drivers/net/ethernet/raeth/Makefile.release +new file mode 100644 +index 0000000..ecdeeda +--- /dev/null ++++ b/drivers/net/ethernet/raeth/Makefile.release +@@ -0,0 +1,60 @@ ++obj-$(CONFIG_RAETH) += raeth.o ++raeth-objs := ra_mac.o mii_mgr.o ra_rfrw.o ++ ++ifeq ($(CONFIG_MTK_SMB_HOOK),y) ++obj-y += smb_hook.o ++obj-m += smb.o ++smb-objs := smb_nf.o ++endif ++ ++#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING ++ ++ifeq ($(CONFIG_RAETH_QOS),y) ++raeth-objs += ra_qos.o ++endif ++ ++ifeq ($(CONFIG_RAETH_QDMA),y) ++raeth-objs += raether_qdma.o ++endif ++ ++ifneq ($(CONFIG_RAETH_QDMA),y) ++raeth-objs += raether_pdma.o ++endif ++ ++raeth-objs += raether.o ++ ++ifeq ($(CONFIG_ETHTOOL),y) ++raeth-objs += ra_ethtool.o ++endif ++ ++ifeq ($(CONFIG_RALINK_RT3052_MP2),y) ++raeth-objs += mcast.o ++endif ++ ++ifeq ($(CONFIG_RAETH_NETLINK),y) ++raeth-objs += ra_netlink.o ++endif ++ ++ifeq ($(CONFIG_RAETH_HW_LRO),y) ++raeth-objs += raether_hwlro.o ++endif ++ ++ifeq ($(CONFIG_RAETH_GMAC2),y) ++EXTRA_CFLAGS += -DCONFIG_PSEUDO_SUPPORT ++endif ++ ++ifeq ($(CONFIG_ETH_MEMORY_OPTIMIZATION),y) ++EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION ++endif ++ ++ifeq ($(CONFIG_RT2860V2_AP_MEMORY_OPTIMIZATION),y) ++EXTRA_CFLAGS += -DMEMORY_OPTIMIZATION ++endif ++ ++ifeq ($(CONFIG_RA_NETWORK_WORKQUEUE_BH),y) ++EXTRA_CFLAGS += -DWORKQUEUE_BH ++endif ++ ++ifeq ($(CONFIG_TASKLET_WORKQUEUE_SW),y) ++EXTRA_CFLAGS += -DTASKLET_WORKQUEUE_SW ++endif +diff --git a/drivers/net/ethernet/raeth/csr_netlink.h b/drivers/net/ethernet/raeth/csr_netlink.h +new file mode 100644 +index 0000000..add7745 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/csr_netlink.h +@@ -0,0 +1,27 @@ ++#ifndef CSR_NETLINK_H ++#define CSR_NETLINK_H ++ ++#define CSR_NETLINK 30 ++#define CSR_READ 0 ++#define CSR_WRITE 1 ++#define CSR_TEST 2 ++ ++#define RALINK_CSR_GROUP 2882 ++ ++typedef struct rt2880_csr_msg { ++ int enable; ++ char reg_name[32]; ++ unsigned long address; ++ unsigned long default_value; ++ unsigned long reserved_bits; /* 1 : not reserved, 0 : reserved */ ++ unsigned long write_mask; ++ unsigned long write_value; ++ int status; ++} CSR_MSG; ++ ++int csr_msg_send(CSR_MSG* msg); ++int csr_msg_recv(void); ++ ++// static CSR_MSG input_csr_msg; ++ ++#endif +diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen.c b/drivers/net/ethernet/raeth/dvt/pkt_gen.c +new file mode 100755 +index 0000000..b351b21 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/dvt/pkt_gen.c +@@ -0,0 +1,88 @@ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++char *ifname="eth3"; ++ ++static int32_t PktGenInitMod(void) ++{ ++ ++ struct net_dev *dev; ++ struct sk_buff *skb; ++ int i=0; ++ ++ unsigned char pkt[]={ ++ //0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // dest bcast mac ++ 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest macA ++ //0x00, 0x30, 0xdb, 0x02, 0x02, 0x01, // dest macB ++ 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac ++ 0x81, 0x00, // vlan tag ++ //0x81, 0x10, // vlan tag ++ //0x87, 0x39, // do not learn ++ //0xc1, 0x03, // vlan tag SA=0, VID=2, LV=1 ++ 0x00, 0x03, // pri=0, vlan=3 ++ 0x08, 0x00, // eth type=ip ++ 0x45, 0x00, 0x00, 0x30, 0x12, 0x34, 0x40, 0x00, 0xff, 0x06, ++ 0x40, 0x74, 0x0a, 0x0a, 0x1e, 0x0a, 0x0a, 0x0a, 0x1e, 0x0b, ++ 0x00, 0x1e, 0x00, 0x28, 0x00, 0x1c, 0x81, 0x06, 0x00, 0x00, ++ 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ ++ skb = alloc_skb(256, GFP_ATOMIC); ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ if((dev=dev_get_by_name(&init_net,ifname))){ ++#else ++ if((dev=dev_get_by_name(ifname))){ ++#endif ++ ++ ++ ++ skb->dev=dev; ++ skb_put(skb,sizeof(pkt)); ++ memcpy(skb->data, pkt, sizeof(pkt)); ++ ++ printk("send pkt(len=%d) to %s\n", skb->len, skb->dev->name); ++ ++ ++ for(i=0;idata[i]); ++ } ++ ++ dev_queue_xmit(skb); ++ }else{ ++ printk("interface %s not found\n",ifname); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++static void PktGenCleanupMod(void) ++{ ++} ++ ++module_init(PktGenInitMod); ++module_exit(PktGenCleanupMod); ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12) ++MODULE_PARM (ifname, "s"); ++#else ++module_param (ifname, charp, 0); ++#endif ++ ++MODULE_DESCRIPTION("Ralink PktGen Module"); ++MODULE_AUTHOR("Steven Liu"); ++MODULE_LICENSE("Proprietary"); ++MODULE_PARM_DESC (ifname, "interface name"); ++ +diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c b/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c +new file mode 100755 +index 0000000..e78c65a +--- /dev/null ++++ b/drivers/net/ethernet/raeth/dvt/pkt_gen_tcp_frag.c +@@ -0,0 +1,138 @@ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++char *ifname="eth3"; ++ ++ ++static int32_t PktGenInitMod(void) ++{ ++ unsigned char pkt_1[]={ ++ 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac ++ 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac ++ 0x08, 0x00, // type: ip ++ 0x45, 0x00, 0x00, 0x34, // ip: ..., total len (0x034 = 52) ++ 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset ++ 0x80, 0x06, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307) ++ 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123) ++ 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5) ++ 0x0d, 0xd5, //tcp src port ++ 0x13, 0x89, //tcp dst port ++ 0x40, 0xf5, 0x15, 0x04, //tcp sequence number ++ 0xf6, 0x4f, 0x1e, 0x31, //tcp ack number ++ 0x50, 0x10, 0xfc, 0x00, //tcp flags, win size ++ 0xf1, 0xfe, 0x00, 0x00, //tcp checksum (0xf1fe) ++ 0x01, 0x02, 0x03, 0x04, 0x05, //payload (12 bytes) ++ 0x06, 0x07, 0x08, 0x09, 0x0a, ++ 0x0b, 0x0c ++ }; ++ ++ unsigned char pkt_2[]={ ++ 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac ++ 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac ++ 0x08, 0x00, // type: ip ++ 0x45, 0x00, 0x00, 0x20, // ip: ..., total len (0x020 = 32) ++ 0xa1, 0x78, 0x00, 0x04, // ip: id, frag, frag offset (32) ++ 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307) ++ 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123) ++ 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5) ++ 0x11, 0x12, 0x13, 0x14, 0x15, //payload (12 bytes) ++ 0x16, 0x17, 0x18, 0x19, 0x1a, ++ 0x1b, 0x1c ++ }; ++ ++ struct net_dev *dev; ++ struct sk_buff *skb_1; ++ struct sk_buff *skb_2; ++ int i=0; ++ ++ skb_1 = alloc_skb(256, GFP_ATOMIC); ++ skb_2 = alloc_skb(256, GFP_ATOMIC); ++ ++ ++#if 1 ++/* send packet 1 */ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ if((dev=dev_get_by_name(&init_net,ifname))){ ++#else ++ if((dev=dev_get_by_name(ifname))){ ++#endif ++ ++ skb_1->dev=dev; ++ skb_put(skb_1,sizeof(pkt_1)); ++ memcpy(skb_1->data, pkt_1, sizeof(pkt_1)); ++ ++ printk("send pkt(len=%d) to %s\n", skb_1->len, skb_1->dev->name); ++ ++ ++ for(i=0;idata[i]); ++ } ++ ++ dev_queue_xmit(skb_1); ++ }else{ ++ printk("interface %s not found\n",ifname); ++ return 1; ++ } ++#endif ++ ++#if 1 ++/* send packet 2 */ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ if((dev=dev_get_by_name(&init_net,ifname))){ ++#else ++ if((dev=dev_get_by_name(ifname))){ ++#endif ++ ++ skb_2->dev=dev; ++ skb_put(skb_2,sizeof(pkt_2)); ++ memcpy(skb_2->data, pkt_2, sizeof(pkt_2)); ++ ++ printk("send pkt(len=%d) to %s\n", skb_2->len, skb_2->dev->name); ++ ++ ++ for(i=0;idata[i]); ++ } ++ ++ dev_queue_xmit(skb_2); ++ }else{ ++ printk("interface %s not found\n",ifname); ++ return 1; ++ } ++#endif ++ ++ return 0; ++} ++ ++static void PktGenCleanupMod(void) ++{ ++} ++ ++module_init(PktGenInitMod); ++module_exit(PktGenCleanupMod); ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12) ++MODULE_PARM (ifname, "s"); ++#else ++module_param (ifname, charp, 0); ++#endif ++ ++MODULE_DESCRIPTION("Ralink PktGen Module"); ++MODULE_AUTHOR("Steven Liu"); ++MODULE_LICENSE("Proprietary"); ++MODULE_PARM_DESC (ifname, "interface name"); ++ +diff --git a/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c b/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c +new file mode 100755 +index 0000000..917e7ad +--- /dev/null ++++ b/drivers/net/ethernet/raeth/dvt/pkt_gen_udp_frag.c +@@ -0,0 +1,191 @@ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++char *ifname="eth3"; ++ ++ ++static int32_t PktGenInitMod(void) ++{ ++#if 0 ++ unsigned char pkt_0[]={ ++// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac ++ 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac ++ 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac ++ 0x08, 0x00, // type: ip ++ 0x45, 0x00, 0x00, 0x26, // ip: ..., total len (0x026 = 38) ++// 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset ++ 0xa1, 0x78, 0x40, 0x00, // ip: id, frag, frag offset ++ 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307) ++ 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123) ++// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3) ++ 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5) ++ 0xca, 0x7b, //udp src port ++ 0x13, 0x89, //udp dst port ++ 0x00, 0x12, //udp len (0x01c = 18) ++ 0x2f, 0x96, //udp checksum (0x2f96) ++ 0x01, 0x02, 0x03, 0x04, 0x05, //payload (10 bytes) ++ 0x06, 0x07, 0x08, 0x09, 0x0a ++ }; ++#endif ++ ++ unsigned char pkt_1[]={ ++// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac ++ 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac ++ 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac ++ 0x08, 0x00, // type: ip ++ 0x45, 0x00, 0x00, 0x24, // ip: ..., total len (0x024 = 36) ++ 0xa1, 0x78, 0x20, 0x00, // ip: id, frag, frag offset ++// 0xa1, 0x78, 0x40, 0x00, // ip: id, frag, frag offset ++ 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307) ++ 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123) ++// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3) ++ 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5) ++ 0xca, 0x7b, //udp src port ++ 0x13, 0x89, //udp dst port ++ 0x00, 0x1a, //udp len (0x01a = 26) ++ 0x2f, 0x96, //udp checksum (0x2f96) ++ 0x01, 0x02, 0x03, 0x04, 0x05, //payload (8 bytes) ++ 0x06, 0x07, 0x08 ++ }; ++ ++ unsigned char pkt_2[]={ ++// 0x00, 0x21, 0x86, 0xee, 0xe3, 0x95, // dest mac ++ 0x00, 0x21, 0x86, 0xee, 0xe3, 0x90, // dest mac ++ 0x00, 0x0c, 0x43, 0x28, 0x80, 0x33, // src mac ++ 0x08, 0x00, // type: ip ++ 0x45, 0x00, 0x00, 0x1e, // ip: ..., total len (0x01e = 30) ++ 0xa1, 0x78, 0x00, 0x02, // ip: id, frag, frag offset (16) ++ 0x40, 0x11, 0x63, 0x07, // ip: ttl, protocol, hdr checksum (0x6307) ++ 0x0a, 0x0a, 0x1e, 0x7b, // src ip (10.10.30.123) ++// 0x0a, 0x0a, 0x1e, 0x03, // dst ip (10.10.30.3) ++ 0x0a, 0x0a, 0x1e, 0x05, // dst ip (10.10.30.5) ++ 0x11, 0x12, 0x13, 0x14, 0x15, //payload (10 bytes) ++ 0x16, 0x17, 0x18, 0x19, 0x1a ++ }; ++ ++ struct net_dev *dev; ++// struct sk_buff *skb_0; ++ struct sk_buff *skb_1; ++ struct sk_buff *skb_2; ++ int i=0; ++ ++// skb_0 = alloc_skb(256, GFP_ATOMIC); ++ skb_1 = alloc_skb(256, GFP_ATOMIC); ++ skb_2 = alloc_skb(256, GFP_ATOMIC); ++ ++#if 0 ++/* send packet 0 */ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ if((dev=dev_get_by_name(&init_net,ifname))){ ++#else ++ if((dev=dev_get_by_name(ifname))){ ++#endif ++ ++ skb_0->dev=dev; ++ skb_put(skb_0,sizeof(pkt_0)); ++ memcpy(skb_0->data, pkt_0, sizeof(pkt_0)); ++ ++ printk("send pkt(len=%d) to %s\n", skb_0->len, skb_0->dev->name); ++ ++ ++ for(i=0;idata[i]); ++ } ++ ++ dev_queue_xmit(skb_0); ++ }else{ ++ printk("interface %s not found\n",ifname); ++ return 1; ++ } ++#endif ++ ++#if 1 ++/* send packet 1 */ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ if((dev=dev_get_by_name(&init_net,ifname))){ ++#else ++ if((dev=dev_get_by_name(ifname))){ ++#endif ++ ++ skb_1->dev=dev; ++ skb_put(skb_1,sizeof(pkt_1)); ++ memcpy(skb_1->data, pkt_1, sizeof(pkt_1)); ++ ++ printk("send pkt(len=%d) to %s\n", skb_1->len, skb_1->dev->name); ++ ++ ++ for(i=0;idata[i]); ++ } ++ ++ dev_queue_xmit(skb_1); ++ }else{ ++ printk("interface %s not found\n",ifname); ++ return 1; ++ } ++#endif ++ ++#if 1 ++/* send packet 2 */ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ if((dev=dev_get_by_name(&init_net,ifname))){ ++#else ++ if((dev=dev_get_by_name(ifname))){ ++#endif ++ ++ skb_2->dev=dev; ++ skb_put(skb_2,sizeof(pkt_2)); ++ memcpy(skb_2->data, pkt_2, sizeof(pkt_2)); ++ ++ printk("send pkt(len=%d) to %s\n", skb_2->len, skb_2->dev->name); ++ ++ ++ for(i=0;idata[i]); ++ } ++ ++ dev_queue_xmit(skb_2); ++ }else{ ++ printk("interface %s not found\n",ifname); ++ return 1; ++ } ++#endif ++ ++ return 0; ++} ++ ++static void PktGenCleanupMod(void) ++{ ++} ++ ++module_init(PktGenInitMod); ++module_exit(PktGenCleanupMod); ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12) ++MODULE_PARM (ifname, "s"); ++#else ++module_param (ifname, charp, 0); ++#endif ++ ++MODULE_DESCRIPTION("Ralink PktGen Module"); ++MODULE_AUTHOR("Steven Liu"); ++MODULE_LICENSE("Proprietary"); ++MODULE_PARM_DESC (ifname, "interface name"); ++ +diff --git a/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c +new file mode 100755 +index 0000000..971a821 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.c +@@ -0,0 +1,1527 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined(CONFIG_RAETH_TSO) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++#if defined(CONFIG_RAETH_LRO) ++#include ++#endif ++#include ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0) ++#include ++#else ++#include ++#endif ++ ++#include "../ra2882ethreg.h" ++#include "../raether.h" ++#include "../ra_mac.h" ++#include "../ra_ioctl.h" ++#include "../ra_rfrw.h" ++#ifdef CONFIG_RAETH_NETLINK ++#include "../ra_netlink.h" ++#endif ++#if defined(CONFIG_RAETH_QOS) ++#include "../ra_qos.h" ++#endif ++#include "raether_pdma_dvt.h" ++ ++/* Global variables */ ++static unsigned int g_pdma_dvt_show_config; ++static unsigned int g_pdma_dvt_rx_test_config; ++static unsigned int g_pdma_dvt_tx_test_config; ++static unsigned int g_pdma_dvt_debug_test_config; ++static unsigned int g_pdma_dvt_lro_test_config; ++ ++unsigned int g_pdma_dev_lanport = 0; ++unsigned int g_pdma_dev_wanport = 0; ++ ++void skb_dump(struct sk_buff *sk) ++{ ++ unsigned int i; ++ ++ printk("skb_dump: from %s with len %d (%d) headroom=%d tailroom=%d\n", ++ sk->dev ? sk->dev->name : "ip stack", sk->len, sk->truesize, ++ skb_headroom(sk), skb_tailroom(sk)); ++ ++ /* for(i=(unsigned int)sk->head;i<=(unsigned int)sk->tail;i++) { */ ++ /* for(i=(unsigned int)sk->head;i<=(unsigned int)sk->data+20;i++) { */ ++ for (i = (unsigned int)sk->head; i <= (unsigned int)sk->data + 60; i++) { ++ if ((i % 20) == 0) ++ printk("\n"); ++ if (i == (unsigned int)sk->data) ++ printk("{"); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 21) ++ if (i == (unsigned int)sk->transport_header) ++ printk("#"); ++ if (i == (unsigned int)sk->network_header) ++ printk("|"); ++ if (i == (unsigned int)sk->mac_header) ++ printk("*"); ++#else ++ if (i == (unsigned int)sk->h.raw) ++ printk("#"); ++ if (i == (unsigned int)sk->nh.raw) ++ printk("|"); ++ if (i == (unsigned int)sk->mac.raw) ++ printk("*"); ++#endif ++ printk("%02X-", *((unsigned char *)i)); ++ if (i == (unsigned int)sk->tail) ++ printk("}"); ++ } ++ printk("\n"); ++} ++ ++#if defined(CONFIG_RAETH_HW_LRO) ++/* PDMA LRO test functions start */ ++int pdma_lro_disable_dvt(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_lro_disable_dvt()\n"); ++ ++ /* 1. Invalid LRO ring1~3 */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0); ++ ++ /* 2 Polling relinguish */ ++ while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {; ++ } ++ ++ /* 3. Disable LRO */ ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW0); ++ regVal &= ~(PDMA_LRO_EN); ++ sysRegWrite(ADMA_LRO_CTRL_DW0, regVal); ++ ++#if 0 ++ /* 4. Disable non-lro multiple rx */ ++ SET_PDMA_NON_LRO_MULTI_EN(0); ++ ++ /* 5.1. Set GDM1 to ring0 */ ++ SET_GDM_PID1_RXID_SEL(0); ++ /* 5.2. Set GDM2 to ring0 */ ++ SET_GDM_PID2_RXID_SEL(0); ++#endif ++ ++ return 0; ++} ++ ++int pdma_lro_force_aggre_dvt(void) ++{ ++ unsigned int regVal = 0; ++ unsigned int ip; ++ ++ printk("pdma_lro_force_aggre_dvt()\n"); ++ ++/* pdma rx ring1 */ ++ /* 1. Set RX ring mode to force port */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT); ++ ++ /* 2. Configure lro ring */ ++ /* 2.1 set src/destination TCP ports */ ++ SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 3423); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 2301); ++ /* 2.2 set src/destination IPs */ ++ str_to_ip(&ip, "10.10.10.3"); ++ sysRegWrite(LRO_RX_RING1_SIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.100"); ++ sysRegWrite(LRO_RX_RING1_DIP_DW0, ip); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1); ++ ++ /* 2.3 Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ ++ /* 2.4 Set AGE timer */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, 0); ++ ++ /* 2.5 Set max AGG timer */ ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, 0); ++ ++ /* 2.6 Set max LRO agg count */ ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT); ++ ++ /* 3. IPv4 checksum update enable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 4. Polling relinguish */ ++ while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {; ++ } ++ ++ /* 5. Enable LRO */ ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW0); ++ regVal |= PDMA_LRO_EN; ++ sysRegWrite(ADMA_LRO_CTRL_DW0, regVal); ++ ++ return 0; ++} ++ ++int pdma_lro_auto_aggre_dvt(void) ++{ ++ unsigned int regVal = 0; ++ unsigned int ip; ++ ++ printk("pdma_lro_auto_aggre_dvt()\n"); ++ ++ /* 1.1 Set my IP_1 */ ++ str_to_ip(&ip, "10.10.10.254"); ++ sysRegWrite(LRO_RX_RING0_DIP_DW0, ip); ++ sysRegWrite(LRO_RX_RING0_DIP_DW1, 0); ++ sysRegWrite(LRO_RX_RING0_DIP_DW2, 0); ++ sysRegWrite(LRO_RX_RING0_DIP_DW3, 0); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1); ++ ++ /* 1.2 Set my IP_2 */ ++ str_to_ip(&ip, "10.10.20.254"); ++ sysRegWrite(LRO_RX_RING1_DIP_DW0, ip); ++ sysRegWrite(LRO_RX_RING1_DIP_DW1, 0); ++ sysRegWrite(LRO_RX_RING1_DIP_DW2, 0); ++ sysRegWrite(LRO_RX_RING1_DIP_DW3, 0); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1); ++ ++ /* 1.3 Set my IP_3 */ ++ sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238); ++ sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000); ++ sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000); ++ sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1); ++ ++ /* 1.4 Set my IP_4 */ ++ sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238); ++ sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000); ++ sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000); ++ sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1); ++ ++ /* 2.1 Set RX ring1~3 to auto-learn modes */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN); ++ ++ /* 2.2 Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1); ++ ++ /* 2.3 Set AGE timer */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, 0); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, 0); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, 0); ++ ++ /* 2.4 Set max AGG timer */ ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, 0); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, 0); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, 0); ++ ++ /* 2.5 Set max LRO agg count */ ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, HW_LRO_MAX_AGG_CNT); ++ ++ /* 3.0 IPv6 LRO enable */ ++ SET_PDMA_LRO_IPV6_EN(1); ++ ++ /* 3.1 IPv4 checksum update disable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 3.2 switch priority comparision to byte count mode */ ++ SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE); ++ ++ /* 3.3 bandwidth threshold setting */ ++ SET_PDMA_LRO_BW_THRESHOLD(0); ++ ++ /* 3.4 auto-learn score delta setting */ ++ sysRegWrite(LRO_ALT_SCORE_DELTA, 0); ++ ++ /* 3.5 Set ALT timer to 20us: (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT); ++ /* 3.6 Set ALT refresh timer to 1 sec. (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME); ++ ++ /* 4. Polling relinguish */ ++ while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {; ++ } ++ ++ /* 5. Enable LRO */ ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW0); ++ regVal |= PDMA_LRO_EN; ++ sysRegWrite(ADMA_LRO_CTRL_DW0, regVal); ++ ++ return 0; ++} ++ ++int pdma_lro_auto_ipv6_dvt(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_lro_auto_ipv6_dvt()\n"); ++ ++ /* 1. Set my IP */ ++ sysRegWrite(LRO_RX_RING1_DIP_DW3, 0x20010238); ++ sysRegWrite(LRO_RX_RING1_DIP_DW2, 0x08000000); ++ sysRegWrite(LRO_RX_RING1_DIP_DW1, 0x00000000); ++ sysRegWrite(LRO_RX_RING1_DIP_DW0, 0x00000254); ++ ++ /* 2.1 Set RX ring1~3 to auto-learn modes */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN); ++ ++ /* 2.2 Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1); ++ ++ /* 2.3 Set AGE timer */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME); ++ ++ /* 3.0 IPv6 LRO enable */ ++ SET_PDMA_LRO_IPV6_EN(1); ++ ++ /* 3.1 IPv4 checksum update disable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 3.2 switch priority comparision to byte count mode */ ++ SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE); ++ ++ /* 3.3 bandwidth threshold setting */ ++ SET_PDMA_LRO_BW_THRESHOLD(0); ++ ++ /* 3.4 auto-learn score delta setting */ ++ sysRegWrite(LRO_ALT_SCORE_DELTA, 0); ++ ++ /* 3.5 Set ALT timer to 500us: (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25); ++ /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER(2000); ++ ++ /* 3.7 Set max AGG timer: 10 msec. */ ++ SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME); ++ ++ /* 4. Polling relinguish */ ++ while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {; ++ } ++ ++ /* 5. Enable LRO */ ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW0); ++ regVal |= PDMA_LRO_EN; ++ sysRegWrite(ADMA_LRO_CTRL_DW0, regVal); ++ ++ return 0; ++} ++ ++int pdma_lro_auto_myIP_dvt(void) ++{ ++ unsigned int regVal = 0; ++ unsigned int ip; ++ ++ printk("pdma_lro_auto_myIP_dvt()\n"); ++ ++ /* 1.1 Set my IP_1 */ ++ str_to_ip(&ip, "10.10.10.254"); ++ sysRegWrite(LRO_RX_RING0_DIP_DW0, ip); ++ sysRegWrite(LRO_RX_RING0_DIP_DW1, 0); ++ sysRegWrite(LRO_RX_RING0_DIP_DW2, 0); ++ sysRegWrite(LRO_RX_RING0_DIP_DW3, 0); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1); ++ /* 1.2 Set my IP_2 */ ++ str_to_ip(&ip, "10.10.20.254"); ++ sysRegWrite(LRO_RX_RING1_DIP_DW0, ip); ++ sysRegWrite(LRO_RX_RING1_DIP_DW1, 0); ++ sysRegWrite(LRO_RX_RING1_DIP_DW2, 0); ++ sysRegWrite(LRO_RX_RING1_DIP_DW3, 0); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1); ++ /* 1.3 Set my IP_3 */ ++ sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238); ++ sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000); ++ sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000); ++ sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1); ++ /* 1.4 Set my IP_4 */ ++ sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238); ++ sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000); ++ sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000); ++ sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1); ++ ++ /* 2.1 Set RX ring1~3 to auto-learn modes */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN); ++ ++ /* 2.2 Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1); ++ ++ /* 2.3 Set AGE timer */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME); ++ ++ /* 3.0 IPv6 LRO enable */ ++ SET_PDMA_LRO_IPV6_EN(1); ++ ++ /* 3.1 IPv4 checksum update disable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 3.2 switch priority comparision to byte count mode */ ++ SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE); ++ ++ /* 3.3 bandwidth threshold setting */ ++ SET_PDMA_LRO_BW_THRESHOLD(0); ++ ++ /* 3.4 auto-learn score delta setting */ ++ sysRegWrite(LRO_ALT_SCORE_DELTA, 0); ++ ++ /* 3.5 Set ALT timer to 500us: (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25); ++ /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER(2000); ++ ++ /* 3.7 Set max AGG timer: 10 msec. */ ++ SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME); ++ ++ /* 4. Polling relinguish */ ++ while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {; ++ } ++ ++ /* 5. Enable LRO */ ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW0); ++ regVal |= PDMA_LRO_EN; ++ sysRegWrite(ADMA_LRO_CTRL_DW0, regVal); ++ ++ return 0; ++} ++ ++int pdma_lro_dly_int_dvt(int index) ++{ ++ unsigned int regVal = 0; ++ unsigned int ip; ++ ++ printk("pdma_lro_dly_int_dvt(%d)\n", index); ++ ++#if 0 ++ /* 1.1 Set my IP_1 */ ++ /* str_to_ip( &ip, "10.10.10.254" ); */ ++ str_to_ip(&ip, "10.10.10.100"); ++ sysRegWrite(LRO_RX_RING0_DIP_DW0, ip); ++ sysRegWrite(LRO_RX_RING0_DIP_DW1, 0); ++ sysRegWrite(LRO_RX_RING0_DIP_DW2, 0); ++ sysRegWrite(LRO_RX_RING0_DIP_DW3, 0); ++#else ++ /* 1.1 set src/destination TCP ports */ ++ SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 3423); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 2301); ++ SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING2, 3423); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING2, 2301); ++ SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING3, 3423); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING3, 2301); ++ /* 1.2 set src/destination IPs */ ++ str_to_ip(&ip, "10.10.10.3"); ++ sysRegWrite(LRO_RX_RING1_SIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.100"); ++ sysRegWrite(LRO_RX_RING1_DIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.3"); ++ sysRegWrite(LRO_RX_RING2_SIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.100"); ++ sysRegWrite(LRO_RX_RING2_DIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.3"); ++ sysRegWrite(LRO_RX_RING3_SIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.100"); ++ sysRegWrite(LRO_RX_RING3_DIP_DW0, ip); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1); ++#endif ++ ++ if (index == 0) { ++ /* 1.2 Disable DLY_INT for lro ring */ ++ SET_PDMA_LRO_DLY_INT_EN(0); ++ } else { ++ /* 1.2 Enable DLY_INT for lro ring */ ++ SET_PDMA_LRO_DLY_INT_EN(1); ++ } ++ ++ /* 1.3 LRO ring DLY_INT setting */ ++ if (index == 1) { ++ sysRegWrite(LRO_RX1_DLY_INT, DELAY_INT_INIT); ++ } else if (index == 2) { ++ sysRegWrite(LRO_RX2_DLY_INT, DELAY_INT_INIT); ++ } else if (index == 3) { ++ sysRegWrite(LRO_RX3_DLY_INT, DELAY_INT_INIT); ++ } ++#if 0 ++ /* 2.1 Set RX rings to auto-learn modes */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN); ++#else ++ /* 2.0 set rx ring mode */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_FORCE_PORT); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_FORCE_PORT); ++ ++ /* 2.1 IPv4 force port mode */ ++ SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING3, 1); ++#endif ++ ++ /* 2.2 Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1); ++ if ((index == 0) || (index == 1)) { ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0); ++ } else if (index == 2) { ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 0); ++ } else { ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 0); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1); ++ } ++ ++ /* 2.3 Set AGE timer */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME); ++ ++ /* 3.1 IPv4 checksum update enable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 3.2 switch priority comparision to byte count mode */ ++ SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE); ++ ++ /* 3.3 bandwidth threshold setting */ ++ SET_PDMA_LRO_BW_THRESHOLD(0); ++ ++ /* 3.4 auto-learn score delta setting */ ++ sysRegWrite(LRO_ALT_SCORE_DELTA, 0); ++ ++ /* 3.5 Set ALT timer to 500us: (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(25); ++ /* 3.6 Set ALT refresh timer to 1 sec. (unit: 500us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER(2000); ++ ++ /* 3.7 Set max AGG timer */ ++ SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME); ++ ++ /* 4. Polling relinguish */ ++ while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) {; ++ } ++ ++ /* 5. Enable LRO */ ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW0); ++ regVal |= PDMA_LRO_EN; ++ sysRegWrite(ADMA_LRO_CTRL_DW0, regVal); ++ ++ return 0; ++} ++ ++int pdma_lro_dly_int0_dvt(void) ++{ ++ return pdma_lro_dly_int_dvt(0); ++} ++ ++int pdma_lro_dly_int1_dvt(void) ++{ ++ return pdma_lro_dly_int_dvt(1); ++} ++ ++int pdma_lro_dly_int2_dvt(void) ++{ ++ return pdma_lro_dly_int_dvt(2); ++} ++ ++int pdma_lro_dly_int3_dvt(void) ++{ ++ return pdma_lro_dly_int_dvt(3); ++} ++ ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if defined(CONFIG_RAETH_MULTIPLE_RX_RING) ++int pdma_gdm_rxid_config(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_gdm_rxid_config()\n"); ++ ++ /* 1. Set RX ring1~3 to pse modes */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_PSE_MODE); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_PSE_MODE); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_PSE_MODE); ++ ++ /* 2. Enable non-lro multiple rx */ ++ SET_PDMA_NON_LRO_MULTI_EN(1); ++ ++ return 0; ++} ++ ++int pdma_non_lro_portid_dvt(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_non_lro_portid_dvt()\n"); ++ ++ /* 1. Set GDM1 to ring3 */ ++ SET_GDM_PID1_RXID_SEL(3); ++#if 0 ++ /* 2. Set GDM2 to ring1 */ ++ SET_GDM_PID2_RXID_SEL(1); ++#endif ++ ++ /* 3. Set priority rule: pid */ ++ SET_GDM_RXID_PRI_SEL(GDM_PRI_PID); ++ ++ /* PDMA multi-rx enable */ ++ pdma_gdm_rxid_config(); ++ ++ return 0; ++} ++ ++int pdma_non_lro_stag_dvt(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_non_lro_stag_dvt()\n"); ++ ++ /* 1. Set STAG4 to ring0 */ ++ GDM_STAG_RXID_SEL(4, 0); ++ /* 2. Set STAG3 to ring1 */ ++ GDM_STAG_RXID_SEL(3, 1); ++ /* 3. Set STAG2 to ring2 */ ++ GDM_STAG_RXID_SEL(2, 2); ++ /* 4. Set STAG1 to ring3 */ ++ GDM_STAG_RXID_SEL(1, 3); ++ ++ /* 5. Set priority rule: stag/pid */ ++ SET_GDM_RXID_PRI_SEL(GDM_PRI_PID); ++ ++ /* PDMA multi-rx enable */ ++ pdma_gdm_rxid_config(); ++ ++ return 0; ++} ++ ++int pdma_non_lro_vlan_dvt(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_non_lro_vlan_dvt()\n"); ++ ++ /* 1. Set vlan priority=3 to ring1 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(3, 1); ++ /* 2. Set vlan priority=2 to ring2 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(2, 2); ++ /* 3. Set vlan priority=1 to ring3 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(1, 3); ++ /* 4. Set vlan priority=0 to ring3 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(0, 3); ++ ++ /* 1. Set vlan priority=4 to ring1 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(4, 1); ++ /* 2. Set vlan priority=5 to ring2 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(5, 2); ++ /* 3. Set vlan priority=6 to ring3 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(6, 3); ++ /* 4. Set vlan priority=7 to ring3 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(7, 3); ++ ++ /* 4. Set priority rule: vlan > pid */ ++ SET_GDM_RXID_PRI_SEL(GDM_PRI_VLAN_PID); ++ ++ /* PDMA multi-rx enable */ ++ pdma_gdm_rxid_config(); ++ ++ return 0; ++} ++ ++int pdma_non_lro_tcpack_dvt(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_non_lro_tcpack_dvt()\n"); ++ ++ /* 1. Enable TCP ACK with zero payload check */ ++ SET_GDM_TCP_ACK_WZPC(1); ++ /* 2. Set TCP ACK to ring3 */ ++ SET_GDM_TCP_ACK_RXID_SEL(3); ++ ++ /* 3. Set priority rule: ack > pid */ ++ SET_GDM_RXID_PRI_SEL(GDM_PRI_ACK_PID); ++ ++ /* PDMA multi-rx enable */ ++ pdma_gdm_rxid_config(); ++ ++ return 0; ++} ++ ++int pdma_non_lro_pri1_dvt(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_non_lro_pri1_dvt()\n"); ++ ++ /* 1. Set GDM1 to ring0 */ ++ SET_GDM_PID1_RXID_SEL(0); ++ ++ /* 2.1 Disable TCP ACK with zero payload check */ ++ SET_GDM_TCP_ACK_WZPC(0); ++ /* 2.2 Set TCP ACK to ring1 */ ++ SET_GDM_TCP_ACK_RXID_SEL(1); ++ ++ /* 3. Set vlan priority=1 to ring2 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(1, 2); ++ ++ /* 4. Set priority rule: vlan > ack > pid */ ++ SET_GDM_RXID_PRI_SEL(GDM_PRI_VLAN_ACK_PID); ++ ++ /* PDMA multi-rx enable */ ++ pdma_gdm_rxid_config(); ++ ++ return 0; ++} ++ ++int pdma_non_lro_pri2_dvt(void) ++{ ++ unsigned int regVal = 0; ++ ++ printk("pdma_non_lro_pri2_dvt()\n"); ++ ++ /* 1. Set GDM1 to ring0 */ ++ SET_GDM_PID1_RXID_SEL(0); ++ ++ /* 2.1 Disable TCP ACK with zero payload check */ ++ SET_GDM_TCP_ACK_WZPC(0); ++ /* 2.2 Set TCP ACK to ring1 */ ++ SET_GDM_TCP_ACK_RXID_SEL(1); ++ ++ /* 3. Set vlan priority=1 to ring2 */ ++ SET_GDM_VLAN_PRI_RXID_SEL(1, 2); ++ ++ /* 4. Set priority rule: ack > vlan > pid */ ++ SET_GDM_RXID_PRI_SEL(GDM_PRI_ACK_VLAN_PID); ++ ++ /* PDMA multi-rx enable */ ++ pdma_gdm_rxid_config(); ++ ++ return 0; ++} ++#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */ ++const static PDMA_LRO_DVT_FUNC pdma_dvt_lro_func[] = { ++#if defined(CONFIG_RAETH_HW_LRO) ++ [0] = pdma_lro_disable_dvt, /* PDMA_TEST_LRO_DISABLE */ ++ [1] = pdma_lro_force_aggre_dvt, /* PDMA_TEST_LRO_FORCE_PORT */ ++ [2] = pdma_lro_auto_aggre_dvt, /* PDMA_TEST_LRO_AUTO_LEARN */ ++ [3] = pdma_lro_auto_ipv6_dvt, /* PDMA_TEST_LRO_AUTO_IPV6 */ ++ [4] = pdma_lro_auto_myIP_dvt, /* PDMA_TEST_LRO_AUTO_MYIP */ ++ [5] = pdma_lro_force_aggre_dvt, /* PDMA_TEST_LRO_FORCE_AGGREGATE */ ++#endif /* CONFIG_RAETH_HW_LRO */ ++#if defined(CONFIG_RAETH_MULTIPLE_RX_RING) ++ [6] = pdma_non_lro_portid_dvt, /* PDMA_TEST_NON_LRO_PORT_ID */ ++ [7] = pdma_non_lro_stag_dvt, /* PDMA_TEST_NON_LRO_STAG */ ++ [8] = pdma_non_lro_vlan_dvt, /* PDMA_TEST_NON_LRO_VLAN */ ++ [9] = pdma_non_lro_tcpack_dvt, /* PDMA_TEST_NON_LRO_TCP_ACK */ ++ [10] = pdma_non_lro_pri1_dvt, /* PDMA_TEST_NON_LRO_PRI1 */ ++ [11] = pdma_non_lro_pri2_dvt, /* PDMA_TEST_NON_LRO_PRI2 */ ++#endif /* CONFIG_RAETH_MULTIPLE_RX_RING */ ++#if defined(CONFIG_RAETH_HW_LRO) ++ [12] = pdma_lro_dly_int0_dvt, /* PDMA_TEST_LRO_DLY_INT0 */ ++ [13] = pdma_lro_dly_int1_dvt, /* PDMA_TEST_LRO_DLY_INT1 */ ++ [14] = pdma_lro_dly_int2_dvt, /* PDMA_TEST_LRO_DLY_INT2 */ ++ [15] = pdma_lro_dly_int3_dvt, /* PDMA_TEST_LRO_DLY_INT3 */ ++#endif /* CONFIG_RAETH_HW_LRO */ ++}; ++ ++/* PDMA LRO test functions end */ ++ ++#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING) ++void raeth_pdma_lro_dvt(int rx_ring_no, END_DEVICE *ei_local, ++ int rx_dma_owner_idx0) ++{ ++ if (pdma_dvt_get_show_config() & PDMA_SHOW_RX_DESC) { ++ if (rx_ring_no == 1) { ++ printk("------- rt2880_eth_recv (ring1) --------\n"); ++ printk("rx_info1=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info1); ++ printk("rx_info2=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2); ++ printk("rx_info3=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info3); ++ printk("rx_info4=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4); ++ printk("-------------------------------\n"); ++ } else if (rx_ring_no == 2) { ++ printk("------- rt2880_eth_recv (ring2) --------\n"); ++ printk("rx_info1=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info1); ++ printk("rx_info2=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2); ++ printk("rx_info3=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info3); ++ printk("rx_info4=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4); ++ printk("-------------------------------\n"); ++ } else if (rx_ring_no == 3) { ++ printk("------- rt2880_eth_recv (ring3) --------\n"); ++ printk("rx_info1=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info1); ++ printk("rx_info2=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2); ++ printk("rx_info3=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info3); ++ printk("rx_info4=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4); ++ printk("-------------------------------\n"); ++ } ++#if 0 ++ else { ++ printk("------- rt2880_eth_recv (ring0) --------\n"); ++ printk("rx_info1=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info1); ++ printk("rx_info2=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2); ++ printk("rx_info3=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info3); ++ printk("rx_info4=0x%x\n", ++ *(unsigned int *) ++ &ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4); ++ printk("-------------------------------\n"); ++ } ++#endif ++ } ++ if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_RX_DESC) || ++ (pdma_dvt_get_lro_test_config()==PDMA_TEST_LRO_FORCE_PORT)) { ++ if (rx_ring_no == 1) { ++ printk("------- rt2880_eth_recv (ring1) --------\n"); ++ printk("rx_info1.PDP0=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info1.PDP0); ++ printk("rx_info2.DDONE_bit=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2.DDONE_bit); ++ printk("rx_info2.LS0=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2.LS0); ++ printk("rx_info2.PLEN0=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2.PLEN0); ++ printk("rx_info2.TAG=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2.TAG); ++#if defined(CONFIG_ARCH_MT7623) ++ printk("rx_info2.LRO_AGG_CNT=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2.LRO_AGG_CNT); ++ printk("rx_info2.REV=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2.REV); ++#else ++ printk("rx_info2.LS1=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2.LS1); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ printk("rx_info2.PLEN1=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info2.PLEN1); ++ printk("rx_info3.TPID=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info3.TPID); ++ printk("rx_info3.VID=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info3.VID); ++ printk("rx_info4.IP6=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.IP6); ++ printk("rx_info4.IP4=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.IP4); ++ printk("rx_info4.IP4F=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.IP4F); ++ printk("rx_info4.TACK=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.TACK); ++ printk("rx_info4.L4VLD=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.L4VLD); ++ printk("rx_info4.L4F=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.L4F); ++ printk("rx_info4.SPORT=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.SP); ++ printk("rx_info4.CRSN=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.CRSN); ++ printk("rx_info4.FOE_Entry=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info4.FOE_Entry); ++ printk("-------------------------------\n"); ++ } else if (rx_ring_no == 2) { ++ printk("------- rt2880_eth_recv (ring2) --------\n"); ++ printk("rx_info1.PDP0=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info1.PDP0); ++ printk("rx_info2.DDONE_bit=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2.DDONE_bit); ++ printk("rx_info2.LS0=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2.LS0); ++ printk("rx_info2.PLEN0=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2.PLEN0); ++ printk("rx_info2.TAG=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2.TAG); ++#if defined(CONFIG_ARCH_MT7623) ++ printk("rx_info2.LRO_AGG_CNT=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2.LRO_AGG_CNT); ++ printk("rx_info2.REV=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2.REV); ++#else ++ printk("rx_info2.LS1=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2.LS1); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ printk("rx_info2.PLEN1=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info2.PLEN1); ++ printk("rx_info3.TPID=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info3.TPID); ++ printk("rx_info3.VID=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info3.VID); ++ printk("rx_info4.IP6=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.IP6); ++ printk("rx_info4.IP4=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.IP4); ++ printk("rx_info4.IP4F=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.IP4F); ++ printk("rx_info4.TACK=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.TACK); ++ printk("rx_info4.L4VLD=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.L4VLD); ++ printk("rx_info4.L4F=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.L4F); ++ printk("rx_info4.SPORT=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.SP); ++ printk("rx_info4.CRSN=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.CRSN); ++ printk("rx_info4.FOE_Entry=0x%x\n", ++ ei_local->rx_ring2[rx_dma_owner_idx0]. ++ rxd_info4.FOE_Entry); ++ printk("-------------------------------\n"); ++ } else if (rx_ring_no == 3) { ++ printk("------- rt2880_eth_recv (ring3) --------\n"); ++ printk("rx_info1.PDP0=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info1.PDP0); ++ printk("rx_info2.DDONE_bit=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2.DDONE_bit); ++ printk("rx_info2.LS0=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2.LS0); ++ printk("rx_info2.PLEN0=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2.PLEN0); ++ printk("rx_info2.TAG=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2.TAG); ++#if defined(CONFIG_ARCH_MT7623) ++ printk("rx_info2.LRO_AGG_CNT=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2.LRO_AGG_CNT); ++ printk("rx_info2.REV=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2.REV); ++#else ++ printk("rx_info2.LS1=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2.LS1); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ printk("rx_info2.PLEN1=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info2.PLEN1); ++ printk("rx_info3.TPID=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info3.TPID); ++ printk("rx_info3.VID=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info3.VID); ++ printk("rx_info4.IP6=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.IP6); ++ printk("rx_info4.IP4=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.IP4); ++ printk("rx_info4.IP4F=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.IP4F); ++ printk("rx_info4.TACK=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.TACK); ++ printk("rx_info4.L4VLD=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.L4VLD); ++ printk("rx_info4.L4F=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.L4F); ++ printk("rx_info4.SPORT=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.SP); ++ printk("rx_info4.CRSN=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.CRSN); ++ printk("rx_info4.FOE_Entry=0x%x\n", ++ ei_local->rx_ring3[rx_dma_owner_idx0]. ++ rxd_info4.FOE_Entry); ++ printk("-------------------------------\n"); ++ } ++#if 0 ++ else { ++ printk("------- rt2880_eth_recv (ring0) --------\n"); ++ printk("rx_info1.PDP0=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info1.PDP0); ++ printk("rx_info2.DDONE_bit=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.DDONE_bit); ++ printk("rx_info2.LS0=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.LS0); ++ printk("rx_info2.PLEN0=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.PLEN0); ++ printk("rx_info2.TAG=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.TAG); ++ printk("rx_info2.LS1=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.LS1); ++ printk("rx_info2.PLEN1=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.PLEN1); ++ printk("rx_info3.TPID=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info3.TPID); ++ printk("rx_info3.VID=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info3.VID); ++ printk("rx_info4.IP6=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.IP6); ++ printk("rx_info4.IP4=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.IP4); ++ printk("rx_info4.IP4F=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.IP4F); ++ printk("rx_info4.TACK=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.TACK); ++ printk("rx_info4.L4VLD=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.L4VLD); ++ printk("rx_info4.L4F=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.L4F); ++ printk("rx_info4.SPORT=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.SP); ++ printk("rx_info4.CRSN=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.CRSN); ++ printk("rx_info4.FOE_Entry=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.FOE_Entry); ++ printk("-------------------------------\n"); ++ } ++#endif ++ } ++ if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_FORCE_AGGREGATE) { ++ if (rx_ring_no == 1) { ++ printk("PASS!!! => RING1: rxd_info1.PDP0=0x%x\n", ++ ei_local->rx_ring1[rx_dma_owner_idx0]. ++ rxd_info1.PDP0); ++ skb_dump(ei_local->netrx1_skbuf[rx_dma_owner_idx0]); ++ pdma_dvt_reset_config(); ++ } ++ } ++} ++#endif ++ ++int pdma_dvt_show_ctrl(int par1, int par2) ++{ ++ if (par2 == 0) ++ g_pdma_dvt_show_config = 0; ++ else ++ g_pdma_dvt_show_config |= (1 << par2); ++ ++ return 0; ++} ++ ++int pdma_dvt_test_rx_ctrl(int par1, int par2) ++{ ++ if (par2 == 0) ++ g_pdma_dvt_rx_test_config = 0; ++ else ++ g_pdma_dvt_rx_test_config |= (1 << par2); ++ ++ return 0; ++} ++ ++int pdma_dvt_test_tx_ctrl(int par1, int par2) ++{ ++ if (par2 == 0) ++ g_pdma_dvt_tx_test_config = 0; ++ else ++ g_pdma_dvt_tx_test_config |= (1 << par2); ++ ++ return 0; ++} ++ ++int pdma_dvt_test_debug_ctrl(int par1, int par2) ++{ ++ if (par2 == 0) ++ g_pdma_dvt_debug_test_config = 0; ++ else ++ g_pdma_dvt_debug_test_config |= (1 << par2); ++ ++ return 0; ++} ++ ++int pdma_dvt_test_lro_ctrl(int par1, int par2) ++{ ++ g_pdma_dvt_lro_test_config = par2; ++ ++#if defined(CONFIG_RAETH_HW_LRO) || defined(CONFIG_RAETH_MULTIPLE_RX_RING) ++ if (pdma_dvt_lro_func[par2]) ++ (*pdma_dvt_lro_func[par2]) (); ++#endif /* #if defined (CONFIG_RAETH_HW_LRO) */ ++ ++ return 0; ++} ++ ++unsigned int pdma_dvt_get_show_config() ++{ ++ return g_pdma_dvt_show_config; ++} ++ ++unsigned int pdma_dvt_get_rx_test_config() ++{ ++ return g_pdma_dvt_rx_test_config; ++} ++ ++unsigned int pdma_dvt_get_tx_test_config() ++{ ++ return g_pdma_dvt_tx_test_config; ++} ++ ++unsigned int pdma_dvt_get_debug_test_config() ++{ ++ return g_pdma_dvt_debug_test_config; ++} ++ ++unsigned int pdma_dvt_get_lro_test_config() ++{ ++ return g_pdma_dvt_lro_test_config; ++} ++ ++void pdma_dvt_reset_config() ++{ ++ g_pdma_dvt_show_config = 0; ++ g_pdma_dvt_rx_test_config = 0; ++ g_pdma_dvt_tx_test_config = 0; ++ g_pdma_dvt_lro_test_config = 0; ++} ++ ++void raeth_pdma_rx_desc_dvt(END_DEVICE *ei_local, int rx_dma_owner_idx0) ++{ ++#if 0 ++ unsigned int udf = 0; ++#endif ++ ++ if (pdma_dvt_get_show_config() & PDMA_SHOW_RX_DESC) { ++ printk("------- rt2880_eth_recv --------\n"); ++ printk("rx_info1=0x%x\n", ++ *(unsigned int *)&ei_local-> ++ rx_ring0[rx_dma_owner_idx0].rxd_info1); ++ printk("rx_info2=0x%x\n", ++ *(unsigned int *)&ei_local-> ++ rx_ring0[rx_dma_owner_idx0].rxd_info2); ++ printk("rx_info3=0x%x\n", ++ *(unsigned int *)&ei_local-> ++ rx_ring0[rx_dma_owner_idx0].rxd_info3); ++ printk("rx_info4=0x%x\n", ++ *(unsigned int *)&ei_local-> ++ rx_ring0[rx_dma_owner_idx0].rxd_info4); ++ printk("-------------------------------\n"); ++ } ++ if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_RX_DESC) || ++ pdma_dvt_get_rx_test_config()) { ++#if 0 ++ udf = ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6 << 5 | ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4 << 4 | ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F << 3 | ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.TACK << 2 | ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD << 1 | ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F; ++#endif ++ printk("------- rt2880_eth_recv --------\n"); ++ printk("rx_info1.PDP0=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info1.PDP0); ++ printk("rx_info2.DDONE_bit=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.DDONE_bit); ++ printk("rx_info2.LS0=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.LS0); ++ printk("rx_info2.PLEN0=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.PLEN0); ++ printk("rx_info2.TAG=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.TAG); ++#if defined(CONFIG_ARCH_MT7623) ++ printk("rx_info2.LRO_AGG_CNT=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.LRO_AGG_CNT); ++#else ++ printk("rx_info2.LS1=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.LS1); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ printk("rx_info2.PLEN1=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.PLEN1); ++ printk("rx_info3.TPID=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.TPID); ++ printk("rx_info3.VID=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID); ++#if 0 ++ printk("rx_info4.UDF=0x%x\n", udf); ++#endif ++ printk("rx_info4.IP6=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6); ++ printk("rx_info4.IP4=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4); ++ printk("rx_info4.IP4F=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F); ++ printk("rx_info4.TACK=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.TACK); ++ printk("rx_info4.L4VLD=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD); ++ printk("rx_info4.L4F=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F); ++ printk("rx_info4.SPORT=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP); ++ printk("rx_info4.CRSN=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.CRSN); ++ printk("rx_info4.FOE_Entry=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.FOE_Entry); ++ printk("-------------------------------\n"); ++ } ++ if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV6)) { ++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP6) { ++ printk("PASS!!! => rx_info4.IP6=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.IP6); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV4)) { ++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4) { ++ printk("PASS!!! => rx_info4.IP4=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.IP4); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_IPV4F)) { ++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.IP4F) { ++ printk("PASS!!! => rx_info4.IP4F=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.IP4F); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_L4VLD)) { ++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4VLD) { ++ printk("PASS!!! => rx_info4.L4VLD=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.L4VLD); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_L4F)) { ++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.L4F) { ++ printk("PASS!!! => rx_info4.L4F=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info4.L4F); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_SPORT)) { ++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP == 1) { ++ g_pdma_dev_lanport++; ++ } else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info4.SP == ++ 2) { ++ g_pdma_dev_wanport++; ++ } ++ if (g_pdma_dev_lanport && g_pdma_dev_wanport) { ++ printk ++ ("PASS!!! => g_pdma_dev_lanport=0x%x, g_pdma_dev_wanport=0x%x", ++ g_pdma_dev_lanport, g_pdma_dev_wanport); ++ ++ g_pdma_dev_lanport = 0; ++ g_pdma_dev_wanport = 0; ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_VID_OFF)) { ++ if (!ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID) { ++ printk("PASS!!! => rxd_info3.VID=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info3.VID); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_rx_test_config() & PDMA_TEST_RX_VID_ON)) { ++ printk("RX data: (PDP0=%x)\n", ++ (unsigned int)ei_local-> ++ netrx0_skbuf[rx_dma_owner_idx0]->data); ++ ++ skb_dump(ei_local->netrx0_skbuf[rx_dma_owner_idx0]); ++ ++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info3.VID && ++ ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.TAG) { ++ printk("PASS!!! => rxd_info2.TAG=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info2.TAG); ++ printk("PASS!!! => rxd_info3.VID=0x%x\n", ++ ei_local->rx_ring0[rx_dma_owner_idx0]. ++ rxd_info3.VID); ++ pdma_dvt_reset_config(); ++ } ++ } ++} ++ ++void raeth_pdma_tx_vlan_dvt(END_DEVICE *ei_local, ++ unsigned long tx_cpu_owner_idx0) ++{ ++ if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ON)) { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0xE007; /* VLAN_TAG = 0x1E007 */ ++ } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ZERO)) { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0x0000; /* VLAN_TAG = 0x10000 */ ++ } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_MAX)) { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | 0xFFFF; /* VLAN_TAG = 0x1FFFF */ ++ } ++} ++ ++void raeth_pdma_tx_desc_dvt(END_DEVICE *ei_local, ++ unsigned long tx_cpu_owner_idx0) ++{ ++ if (PDMA_TEST_RX_UDF == pdma_dvt_get_rx_test_config()) { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 4; /* PPE */ ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UDF = 0x2F; ++ } ++ if (pdma_dvt_get_show_config() & PDMA_SHOW_TX_DESC) { ++ printk("------- rt2880_eth_send --------\n"); ++ printk("tx_info1=%x\n", ++ *(unsigned int *)&ei_local-> ++ tx_ring0[tx_cpu_owner_idx0].txd_info1); ++ printk("tx_info2=%x\n", ++ *(unsigned int *)&ei_local-> ++ tx_ring0[tx_cpu_owner_idx0].txd_info2); ++ printk("tx_info3=%x\n", ++ *(unsigned int *)&ei_local-> ++ tx_ring0[tx_cpu_owner_idx0].txd_info3); ++ printk("tx_info4=%x\n", ++ *(unsigned int *)&ei_local-> ++ tx_ring0[tx_cpu_owner_idx0].txd_info4); ++ printk("--------------------------------\n"); ++ } ++ if ((pdma_dvt_get_show_config() & PDMA_SHOW_DETAIL_TX_DESC) || ++ pdma_dvt_get_tx_test_config()) { ++ printk("------- rt2880_eth_send --------\n"); ++ printk("tx_info1.SDP0=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0); ++ printk("tx_info2.DDONE_bit=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info2.DDONE_bit); ++ printk("tx_info2.LS0_bit=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit); ++ printk("tx_info2.SDL0=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0); ++ printk("tx_info2.BURST_bit=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info2.BURST_bit); ++ printk("tx_info2.LS1_bit=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS1_bit); ++ printk("tx_info2.SDL1=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL1); ++ printk("tx_info3.SDP1=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3.SDP1); ++ printk("tx_info4.TUI_CO=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO); ++ printk("tx_info4.TSO=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TSO); ++ printk("tx_info4.FPORT=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT); ++ printk("tx_info4.UDF=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.UDF); ++ printk("tx_info4.RESV=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.RESV); ++ printk("tx_info4.VLAN_TAG=%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info4.VLAN_TAG); ++ printk("--------------------------------\n"); ++ } ++ if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_LAN_SPORT)) { ++ if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT == 1) { ++ printk("PASS!!! => txd_info4.FPORT=0x%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info4.FPORT); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_WAN_SPORT)) { ++ if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT == 2) { ++ printk("PASS!!! => txd_info4.FPORT=0x%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info4.FPORT); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ON)) { ++ if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) { ++ printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info4.VLAN_TAG); ++ /* pdma_dvt_reset_config(); */ ++ } ++ } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_OFF)) { ++ if (!ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) { ++ printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info4.VLAN_TAG); ++ pdma_dvt_reset_config(); ++ } ++ } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_ZERO)) { ++ if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) { ++ printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info4.VLAN_TAG); ++ /* pdma_dvt_reset_config(); */ ++ } ++ } else if ((pdma_dvt_get_tx_test_config() & PDMA_TEST_TX_VLAN_MAX)) { ++ if (ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG) { ++ printk("PASS!!! => txd_info4.VLAN_TAG=0x%x\n", ++ ei_local->tx_ring0[tx_cpu_owner_idx0]. ++ txd_info4.VLAN_TAG); ++ /* pdma_dvt_reset_config(); */ ++ } ++ } ++} ++ ++void raeth_pdma_lro_dly_int_dvt(void) ++{ ++ unsigned int reg_int_val; ++ ++ reg_int_val = sysRegRead(RAETH_FE_INT_STATUS); ++ ++ if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT0) { ++ if ((reg_int_val & RX_DLY_INT)) { ++ printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val); ++ pdma_dvt_reset_config(); ++ } ++ } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT1) { ++ if ((reg_int_val & RING1_RX_DLY_INT)) { ++ printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val); ++ pdma_dvt_reset_config(); ++ } ++ } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT2) { ++ if ((reg_int_val & RING2_RX_DLY_INT)) { ++ printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val); ++ pdma_dvt_reset_config(); ++ } ++ } else if (pdma_dvt_get_lro_test_config() == PDMA_TEST_LRO_DLY_INT3) { ++ if ((reg_int_val & RING3_RX_DLY_INT)) { ++ printk("PASS!!! => reg_int_val=0x%x\n", reg_int_val); ++ pdma_dvt_reset_config(); ++ } ++ } ++} ++ ++void pdma_dvt_set_dma_mode(void) ++{ ++#if defined(CONFIG_RAETH_PDMA_LEGACY_MODE) ++ unsigned int regVal; ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW3); ++ regVal &= ~(BIT(15)); ++ sysRegWrite(ADMA_LRO_CTRL_DW3, regVal); ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++} ++ +diff --git a/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h +new file mode 100755 +index 0000000..600aab7 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/dvt/raether_pdma_dvt.h +@@ -0,0 +1,75 @@ ++/* Show controls */ ++#define PDMA_SHOW_RX_DESC (1 << 1) ++#define PDMA_SHOW_TX_DESC (1 << 2) ++#define PDMA_SHOW_DETAIL_RX_DESC (1 << 3) ++#define PDMA_SHOW_DETAIL_TX_DESC (1 << 4) ++ ++/* Rx test controls */ ++#define PDMA_TEST_RX_UDF (1 << 1) ++#define PDMA_TEST_RX_IPV6 (1 << 2) ++#define PDMA_TEST_RX_IPV4 (1 << 3) ++#define PDMA_TEST_RX_IPV4F (1 << 4) ++#define PDMA_TEST_RX_L4VLD (1 << 5) ++#define PDMA_TEST_RX_L4F (1 << 6) ++#define PDMA_TEST_RX_SPORT (1 << 7) ++#define PDMA_TEST_RX_VID_ON (1 << 8) ++#define PDMA_TEST_RX_VID_OFF (1 << 9) ++ ++/* Tx test controls */ ++#define PDMA_TEST_TX_LAN_SPORT (1 << 1) ++#define PDMA_TEST_TX_WAN_SPORT (1 << 2) ++#define PDMA_TEST_TX_VLAN_ON (1 << 3) ++#define PDMA_TEST_TX_VLAN_OFF (1 << 4) ++#define PDMA_TEST_TX_VLAN_ZERO (1 << 5) ++#define PDMA_TEST_TX_VLAN_MAX (1 << 6) ++#define PDMA_TEST_TX_PDMA_LPK (1 << 31) ++ ++/* Debug controls */ ++#define PDMA_TEST_TSO_DEBUG (1 << 1) ++ ++/* LRO test controls */ ++typedef int (*PDMA_LRO_DVT_FUNC) (void); ++ ++#define PDMA_TEST_LRO_DISABLE (0) ++#define PDMA_TEST_LRO_FORCE_PORT (1) ++#define PDMA_TEST_LRO_AUTO_LEARN (2) ++#define PDMA_TEST_LRO_AUTO_IPV6 (3) ++#define PDMA_TEST_LRO_AUTO_MYIP (4) ++#define PDMA_TEST_LRO_FORCE_AGGREGATE (5) ++#define PDMA_TEST_NON_LRO_PORT_ID (6) ++#define PDMA_TEST_NON_LRO_STAG (7) ++#define PDMA_TEST_NON_LRO_VLAN (8) ++#define PDMA_TEST_NON_LRO_TCP_ACK (9) ++#define PDMA_TEST_NON_LRO_PRI1 (10) ++#define PDMA_TEST_NON_LRO_PRI2 (11) ++#define PDMA_TEST_LRO_DLY_INT0 (12) ++#define PDMA_TEST_LRO_DLY_INT1 (13) ++#define PDMA_TEST_LRO_DLY_INT2 (14) ++#define PDMA_TEST_LRO_DLY_INT3 (15) ++ ++void skb_dump(struct sk_buff *sk); ++ ++int pdma_dvt_show_ctrl(int par1, int par2); ++int pdma_dvt_test_rx_ctrl(int par1, int par2); ++int pdma_dvt_test_tx_ctrl(int par1, int par2); ++int pdma_dvt_test_debug_ctrl(int par1, int par2); ++int pdma_dvt_test_lro_ctrl(int par1, int par2); ++ ++unsigned int pdma_dvt_get_show_config(void); ++unsigned int pdma_dvt_get_rx_test_config(void); ++unsigned int pdma_dvt_get_tx_test_config(void); ++unsigned int pdma_dvt_get_debug_test_config(void); ++unsigned int pdma_dvt_get_lro_test_config(void); ++void pdma_dvt_reset_config(void); ++ ++void raeth_pdma_rx_desc_dvt(END_DEVICE *ei_local, int rx_dma_owner_idx0); ++void raeth_pdma_tx_vlan_dvt(END_DEVICE *ei_local, ++ unsigned long tx_cpu_owner_idx0); ++void raeth_pdma_tx_desc_dvt(END_DEVICE *ei_local, ++ unsigned long tx_cpu_owner_idx0); ++ ++void raeth_pdma_lro_dvt(int rx_ring_no, END_DEVICE *ei_local, ++ int rx_dma_owner_idx0); ++void raeth_pdma_lro_dly_int_dvt(void); ++void pdma_dvt_set_dma_mode(void); ++ +diff --git a/drivers/net/ethernet/raeth/ethtool_readme.txt b/drivers/net/ethernet/raeth/ethtool_readme.txt +new file mode 100644 +index 0000000..10e918b +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ethtool_readme.txt +@@ -0,0 +1,44 @@ ++ ++Ethtool readme for selecting different PHY address. ++ ++Before doing any ethtool command you should make sure the current PHY ++address is expected. The default PHY address is 1(port 1). ++ ++You can change current PHY address to X(0~4) by doing follow command: ++# echo X > /proc/rt2880/gmac ++ ++Ethtool command also would show the current PHY address as following. ++ ++# ethtool eth2 ++Settings for eth2: ++ Supported ports: [ TP MII ] ++ Supported link modes: 10baseT/Half 10baseT/Full ++ 100baseT/Half 100baseT/Full ++ Supports auto-negotiation: Yes ++ Advertised link modes: 10baseT/Half 10baseT/Full ++ 100baseT/Half 100baseT/Full ++ Advertised auto-negotiation: No ++ Speed: 10Mb/s ++ Duplex: Full ++ Port: MII ++ PHYAD: 1 ++ Transceiver: internal ++ Auto-negotiation: off ++ Current message level: 0x00000000 (0) ++ Link detected: no ++ ++ ++The "PHYAD" field shows the current PHY address. ++ ++ ++ ++Usage example ++1) show port1 info ++# echo 1 > /proc/rt2880/gmac # change phy address to 1 ++# ethtool eth2 ++ ++2) show port0 info ++# echo 0 > /proc/rt2880/gmac # change phy address to 0 ++# ethtool eth2 ++ ++ +diff --git a/drivers/net/ethernet/raeth/mcast.c b/drivers/net/ethernet/raeth/mcast.c +new file mode 100644 +index 0000000..d796b03 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/mcast.c +@@ -0,0 +1,187 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#define MAX_MCAST_ENTRY 16 ++#define AGEING_TIME 5 //Unit: Sec ++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2], \ ++ ((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] ++ ++//#define MCAST_DEBUG ++#ifdef MCAST_DEBUG ++#define MCAST_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args) ++#else ++#define MCAST_PRINT(fmt, args...) { } ++#endif ++ ++typedef struct { ++ uint8_t src_mac[6]; ++ uint8_t dst_mac[6]; ++ uint16_t vlan_id; ++ uint32_t valid; ++ uint32_t use_count; ++ unsigned long ageout; ++} mcast_entry; ++ ++mcast_entry mcast_tbl[MAX_MCAST_ENTRY]; ++atomic_t mcast_entry_num=ATOMIC_INIT(0); ++DECLARE_MUTEX(mtbl_lock); ++ ++uint32_t inline is_multicast_pkt(uint8_t *mac) ++{ ++ if(mac[0]==0x01 && mac[1]==0x00 && mac[2]==0x5E) { ++ return 1; ++ }else{ ++ return 0; ++ } ++} ++ ++int32_t inline mcast_entry_get(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac) ++{ ++ int i=0; ++ ++ for(i=0;i=0) { ++ mcast_tbl[entry_num].use_count++; ++ mcast_tbl[entry_num].ageout=jiffies + AGEING_TIME * HZ; ++ MCAST_PRINT("%s: Update %0X:%0X:%0X:%0X:%0X:%0X's use_count=%d\n" \ ++ ,__FUNCTION__, MAC_ARG(dst_mac), mcast_tbl[entry_num].use_count); ++ ret = 1; ++ }else { //if entry not found, create new entry. ++ MCAST_PRINT("%s: Create new entry %0X:%0X:%0X:%0X:%0X:%0X\n", \ ++ __FUNCTION__, MAC_ARG(dst_mac)); ++ ret = __add_mcast_entry(vlan_id, src_mac,dst_mac); ++ } ++ ++ up(&mtbl_lock); ++ return ret; ++ ++} ++ ++ ++/* ++ * Return: ++ * 0: entry found ++ * 1: entry not found ++ */ ++int inline mcast_entry_del(uint16_t vlan_id, uint8_t *src_mac, uint8_t *dst_mac) ++{ ++ int entry_num; ++ ++ down(&mtbl_lock); ++ if((entry_num = mcast_entry_get(vlan_id, src_mac, dst_mac)) >=0) { ++ if((--mcast_tbl[entry_num].use_count)==0) { ++ MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X (entry_num=%d)\n", \ ++ __FUNCTION__, MAC_ARG(dst_mac), entry_num); ++ mcast_tbl[entry_num].valid=0; ++ atomic_dec(&mcast_entry_num); ++ } ++ up(&mtbl_lock); ++ return 0; ++ }else { ++ /* this multicast packet was not sent by meself, just ignore it */ ++ up(&mtbl_lock); ++ return 1; ++ } ++} ++ ++/* ++ * Return ++ * 0: drop packet ++ * 1: continue ++ */ ++int32_t mcast_rx(struct sk_buff * skb) ++{ ++ struct vlan_ethhdr *eth = (struct vlan_ethhdr *)(skb->data-ETH_HLEN); ++ ++ /* if we do not send multicast packet before, ++ * we don't need to check re-inject multicast packet. ++ */ ++ if (atomic_read(&mcast_entry_num)==0) { ++ return 1; ++ } ++ ++ ++ if(is_multicast_pkt(eth->h_dest)) { ++ MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X\n", __FUNCTION__, \ ++ MAC_ARG(eth->h_dest)); ++ ++ if(ntohs(eth->h_vlan_proto)==0x8100) { ++ return mcast_entry_del(eth->h_vlan_TCI, eth->h_source, eth->h_dest); ++ } else { ++ return mcast_entry_del(0, eth->h_source, eth->h_dest); ++ } ++ } ++ ++ return 1; ++} ++ ++ ++int32_t mcast_tx(struct sk_buff *skb) ++{ ++ struct vlan_ethhdr *eth = (struct vlan_ethhdr *)(skb->data); ++ ++ ++ if(is_multicast_pkt(eth->h_dest)) { ++ MCAST_PRINT("%s: %0X:%0X:%0X:%0X:%0X:%0X\n", __FUNCTION__,\ ++ MAC_ARG(eth->h_dest)); ++ ++ if(ntohs(eth->h_vlan_proto)==0x8100) { ++ mcast_entry_ins(eth->h_vlan_TCI, eth->h_source, eth->h_dest); ++ } else { ++ mcast_entry_ins(0, eth->h_source, eth->h_dest); ++ } ++ } ++ ++ return 1; ++} ++ +diff --git a/drivers/net/ethernet/raeth/mii_mgr.c b/drivers/net/ethernet/raeth/mii_mgr.c +new file mode 100644 +index 0000000..77a47f1 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/mii_mgr.c +@@ -0,0 +1,603 @@ ++#include ++#include ++#include ++ ++#include ++#include ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) ++#include ++#endif ++ ++#include "ra2882ethreg.h" ++#include "raether.h" ++ ++ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++#define PHY_CONTROL_0 0xC0 ++#define PHY_CONTROL_1 0xC4 ++#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0) ++#define MDIO_PHY_CONTROL_1 (RALINK_ETH_SW_BASE + PHY_CONTROL_1) ++ ++#define GPIO_MDIO_BIT (1<<7) ++#define GPIO_PURPOSE_SELECT 0x60 ++#define GPIO_PRUPOSE (RALINK_SYSCTL_BASE + GPIO_PURPOSE_SELECT) ++ ++#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) ++ ++#define PHY_CONTROL_0 0x7004 ++#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0) ++#define enable_mdio(x) ++ ++#elif defined (CONFIG_RALINK_MT7620) ++ ++#define PHY_CONTROL_0 0x7004 ++#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0) ++#define enable_mdio(x) ++ ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ++#define PHY_CONTROL_0 0x0004 ++#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0) ++#define enable_mdio(x) ++ ++#else ++#define PHY_CONTROL_0 0x00 ++#define PHY_CONTROL_1 0x04 ++#define MDIO_PHY_CONTROL_0 (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_0) ++#define MDIO_PHY_CONTROL_1 (RALINK_FRAME_ENGINE_BASE + PHY_CONTROL_1) ++#define enable_mdio(x) ++#endif ++ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++void enable_mdio(int enable) ++{ ++#if !defined (CONFIG_P5_MAC_TO_PHY_MODE) && !defined(CONFIG_GE1_RGMII_AN) && !defined(CONFIG_GE2_RGMII_AN) && \ ++ !defined (CONFIG_GE1_MII_AN) && !defined (CONFIG_GE2_MII_AN) && !defined (CONFIG_RALINK_MT7628) ++ u32 data = sysRegRead(GPIO_PRUPOSE); ++ if (enable) ++ data &= ~GPIO_MDIO_BIT; ++ else ++ data |= GPIO_MDIO_BIT; ++ sysRegWrite(GPIO_PRUPOSE, data); ++#endif ++} ++#endif ++ ++#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) ++ ++u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data) ++{ ++ u32 volatile status = 0; ++ u32 rc = 0; ++ unsigned long volatile t_start = jiffies; ++ u32 volatile data = 0; ++ ++ /* We enable mdio gpio purpose register, and disable it when exit. */ ++ enable_mdio(1); ++ ++ // make sure previous read operation is complete ++ while (1) { ++ // 0 : Read/write operation complete ++ if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing !!\n"); ++ return rc; ++ } ++ } ++ ++ data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); ++ ++ ++ // make sure read operation is complete ++ t_start = jiffies; ++ while (1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ status = sysRegRead(MDIO_PHY_CONTROL_0); ++ *read_data = (u32)(status & 0x0000FFFF); ++ ++ enable_mdio(0); ++ return 1; ++ } ++ else if (time_after(jiffies, t_start+5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing and Time Out!!\n"); ++ return 0; ++ } ++ } ++} ++ ++u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data) ++{ ++ unsigned long volatile t_start=jiffies; ++ u32 volatile data; ++ ++ enable_mdio(1); ++ ++ // make sure previous write operation is complete ++ while(1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Write operation ongoing\n"); ++ return 0; ++ } ++ } ++ ++ data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data; ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation ++ //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); ++ ++ t_start = jiffies; ++ ++ // make sure write operation is complete ++ while (1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete ++ { ++ enable_mdio(0); ++ return 1; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Write operation Time Out\n"); ++ return 0; ++ } ++ } ++} ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_ARCH_MT7623) ++ ++u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data) ++{ ++ u32 volatile status = 0; ++ u32 rc = 0; ++ unsigned long volatile t_start = jiffies; ++ u32 volatile data = 0; ++ ++ /* We enable mdio gpio purpose register, and disable it when exit. */ ++ enable_mdio(1); ++ ++ // make sure previous read operation is complete ++ while (1) { ++ // 0 : Read/write operation complete ++ if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing !!\n"); ++ return rc; ++ } ++ } ++ ++ data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ //printk("\n Set Command [0x%08X] = [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0, data); ++ ++ ++ // make sure read operation is complete ++ t_start = jiffies; ++ while (1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ status = sysRegRead(MDIO_PHY_CONTROL_0); ++ *read_data = (u32)(status & 0x0000FFFF); ++ ++ enable_mdio(0); ++ return 1; ++ } ++ else if (time_after(jiffies, t_start+5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing and Time Out!!\n"); ++ return 0; ++ } ++ } ++} ++ ++u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data) ++{ ++ unsigned long volatile t_start=jiffies; ++ u32 volatile data; ++ ++ enable_mdio(1); ++ ++ // make sure previous write operation is complete ++ while(1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Write operation ongoing\n"); ++ return 0; ++ } ++ } ++ ++ data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data; ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation ++ //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); ++ ++ t_start = jiffies; ++ ++ // make sure write operation is complete ++ while (1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete ++ { ++ enable_mdio(0); ++ return 1; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Write operation Time Out\n"); ++ return 0; ++ } ++ } ++} ++ ++u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data) ++{ ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE) ++ u32 low_word; ++ u32 high_word; ++ u32 an_status = 0; ++ ++ if(phy_addr==31) ++ { ++ an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1<<31)); ++ if(an_status){ ++ *(unsigned long *)(ESW_PHY_POLLING) &= ~(1<<31);//(AN polling off) ++ } ++ //phase1: write page address phase ++ if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) { ++ //phase2: write address & read low word phase ++ if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) { ++ //phase3: write address & read high word phase ++ if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) { ++ *read_data = (high_word << 16) | (low_word & 0xFFFF); ++ if(an_status){ ++ *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on) ++ } ++ return 1; ++ } ++ } ++ } ++ if(an_status){ ++ *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on) ++ } ++ } else ++#endif ++ { ++ if(__mii_mgr_read(phy_addr, phy_register, read_data)) { ++ return 1; ++ } ++ } ++ ++ return 0; ++} ++ ++u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data) ++{ ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE) ++ u32 an_status = 0; ++ ++ if(phy_addr == 31) ++ { ++ an_status = (*(unsigned long *)(ESW_PHY_POLLING) & (1<<31)); ++ if(an_status){ ++ *(unsigned long *)(ESW_PHY_POLLING) &= ~(1<<31);//(AN polling off) ++ } ++ //phase1: write page address phase ++ if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) { ++ //phase2: write address & read low word phase ++ if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) { ++ //phase3: write address & read high word phase ++ if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) { ++ if(an_status){ ++ *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on) ++ } ++ return 1; ++ } ++ } ++ } ++ if(an_status){ ++ *(unsigned long *)(ESW_PHY_POLLING) |= (1<<31);//(AN polling on) ++ } ++ } else ++#endif ++ { ++ if(__mii_mgr_write(phy_addr, phy_register, write_data)) { ++ return 1; ++ } ++ } ++ ++ return 0; ++} ++ ++u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr) ++{ ++ u32 rc = 0; ++ unsigned long volatile t_start = jiffies; ++ u32 volatile data = 0; ++ ++ enable_mdio(1); ++ ++ while (1) { ++ if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing !!\n"); ++ return rc; ++ } ++ } ++ data = (dev_addr << 25) | (port_num << 20) | (0x00 << 18) | (0x00 << 16) | reg_addr; ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ ++ t_start = jiffies; ++ while (1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete ++ { ++ enable_mdio(0); ++ return 1; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Write operation Time Out\n"); ++ return 0; ++ } ++ } ++ ++} ++ ++ ++u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data) ++{ ++ u32 volatile status = 0; ++ u32 rc = 0; ++ unsigned long volatile t_start = jiffies; ++ u32 volatile data = 0; ++ ++ // set address first ++ mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr); ++ //udelay(10); ++ ++ enable_mdio(1); ++ ++ while (1) { ++ if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing !!\n"); ++ return rc; ++ } ++ } ++ data = (dev_addr << 25) | (port_num << 20) | (0x03 << 18) | (0x00 << 16) | reg_addr; ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ t_start = jiffies; ++ while (1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ *read_data = (sysRegRead(MDIO_PHY_CONTROL_0) & 0x0000FFFF); ++ enable_mdio(0); ++ return 1; ++ } ++ else if (time_after(jiffies, t_start+5*HZ)) { ++ enable_mdio(0); ++ printk("\n Set Operation: MDIO Read operation is ongoing and Time Out!!\n"); ++ return 0; ++ } ++ status = sysRegRead(MDIO_PHY_CONTROL_0); ++ } ++ ++} ++ ++u32 mii_mgr_write_cl45 (u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data) ++{ ++ u32 rc = 0; ++ unsigned long volatile t_start = jiffies; ++ u32 volatile data = 0; ++ ++ // set address first ++ mii_mgr_cl45_set_address(port_num, dev_addr, reg_addr); ++ //udelay(10); ++ ++ enable_mdio(1); ++ while (1) { ++ if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing !!\n"); ++ return rc; ++ } ++ } ++ ++ data = (dev_addr << 25) | (port_num << 20) | (0x01 << 18) | (0x00 << 16) | write_data; ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ ++ t_start = jiffies; ++ ++ while (1) { ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++ { ++ enable_mdio(0); ++ return 1; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Write operation Time Out\n"); ++ return 0; ++ } ++ ++ } ++} ++ ++#else // not rt6855 ++ ++u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data) ++{ ++ u32 volatile status = 0; ++ u32 rc = 0; ++ unsigned long volatile t_start = jiffies; ++#if !defined (CONFIG_RALINK_RT3052) && !defined (CONFIG_RALINK_RT3352) && !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628) ++ u32 volatile data = 0; ++#endif ++ ++ /* We enable mdio gpio purpose register, and disable it when exit. */ ++ enable_mdio(1); ++ ++ // make sure previous read operation is complete ++ while (1) { ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ // rd_rdy: read operation is complete ++ if(!( sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1))) ++#else ++ // 0 : Read/write operation complet ++ if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++#endif ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing !!\n"); ++ return rc; ++ } ++ } ++ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ sysRegWrite(MDIO_PHY_CONTROL_0 , (1<<14) | (phy_register << 8) | (phy_addr)); ++#else ++ data = (phy_addr << 24) | (phy_register << 16); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++#endif ++ //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); ++ ++ ++ // make sure read operation is complete ++ t_start = jiffies; ++ while (1) { ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ if (sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 1)) { ++ status = sysRegRead(MDIO_PHY_CONTROL_1); ++ *read_data = (u32)(status >>16); ++ ++ enable_mdio(0); ++ return 1; ++ } ++#else ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { ++ status = sysRegRead(MDIO_PHY_CONTROL_0); ++ *read_data = (u32)(status & 0x0000FFFF); ++ ++ enable_mdio(0); ++ return 1; ++ } ++#endif ++ else if (time_after(jiffies, t_start+5*HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Read operation is ongoing and Time Out!!\n"); ++ return 0; ++ } ++ } ++} ++ ++ ++u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data) ++{ ++ unsigned long volatile t_start=jiffies; ++ u32 volatile data; ++ ++ enable_mdio(1); ++ ++ // make sure previous write operation is complete ++ while(1) { ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ if (!(sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 0))) ++#else ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) ++#endif ++ { ++ break; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Write operation ongoing\n"); ++ return 0; ++ } ++ } ++ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ data = ((write_data & 0xFFFF) << 16); ++ data |= (phy_register << 8) | (phy_addr); ++ data |= (1<<13); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++#else ++ data = (1<<30) | (phy_addr << 24) | (phy_register << 16) | write_data; ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); ++ data |= (1<<31); ++ sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation ++#endif ++ //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); ++ ++ t_start = jiffies; ++ ++ // make sure write operation is complete ++ while (1) { ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ if (sysRegRead(MDIO_PHY_CONTROL_1) & (0x1 << 0)) //wt_done ?= 1 ++#else ++ if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete ++#endif ++ { ++ enable_mdio(0); ++ return 1; ++ } ++ else if (time_after(jiffies, t_start + 5 * HZ)) { ++ enable_mdio(0); ++ printk("\n MDIO Write operation Time Out\n"); ++ return 0; ++ } ++ } ++} ++ ++ ++ ++ ++#endif ++ ++ ++ ++ ++EXPORT_SYMBOL(mii_mgr_write); ++EXPORT_SYMBOL(mii_mgr_read); +diff --git a/drivers/net/ethernet/raeth/ra2882ethreg.h b/drivers/net/ethernet/raeth/ra2882ethreg.h +new file mode 100644 +index 0000000..c67a042 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra2882ethreg.h +@@ -0,0 +1,1985 @@ ++#ifndef RA2882ETHREG_H ++#define RA2882ETHREG_H ++ ++#include // for struct mii_if_info in ra2882ethreg.h ++#include /* check linux version for 2.4 and 2.6 compatibility */ ++#include /* for "struct tasklet_struct" in linux-3.10.14 */ ++#if defined (CONFIG_HW_SFQ) ++#include ++#include ++#endif ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ++#include ++#endif ++#include "raether.h" ++ ++#ifdef WORKQUEUE_BH ++#include ++#endif // WORKQUEUE_BH // ++#ifdef CONFIG_RAETH_LRO ++#include ++#endif ++ ++#define MAX_PACKET_SIZE 1514 ++#define MIN_PACKET_SIZE 60 ++#define MAX_TXD_LEN 0x3fff ++ ++#if defined (CONFIG_ARCH_MT7623) ++#define phys_to_bus(a) (a) ++#else ++#define phys_to_bus(a) (a & 0x1FFFFFFF) ++#endif ++ ++ ++ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++#define BIT(x) ((1 << x)) ++#endif ++/* bits range: for example BITS(16,23) = 0xFF0000 ++ * ==> (BIT(m)-1) = 0x0000FFFF ~(BIT(m)-1) => 0xFFFF0000 ++ * ==> (BIT(n+1)-1) = 0x00FFFFFF ++ */ ++#define BITS(m,n) (~(BIT(m)-1) & ((BIT(n) - 1) | BIT(n))) ++ ++#define ETHER_ADDR_LEN 6 ++ ++/* Phy Vender ID list */ ++ ++#define EV_ICPLUS_PHY_ID0 0x0243 ++#define EV_ICPLUS_PHY_ID1 0x0D90 ++#define EV_MARVELL_PHY_ID0 0x0141 ++#define EV_MARVELL_PHY_ID1 0x0CC2 ++#define EV_VTSS_PHY_ID0 0x0007 ++#define EV_VTSS_PHY_ID1 0x0421 ++ ++/* ++ FE_INT_STATUS ++*/ ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || \ ++ defined (CONFIG_ARCH_MT7623) ++ ++#define RX_COHERENT BIT(31) ++#define RX_DLY_INT BIT(30) ++#define TX_COHERENT BIT(29) ++#define TX_DLY_INT BIT(28) ++#define RING3_RX_DLY_INT BIT(27) ++#define RING2_RX_DLY_INT BIT(26) ++#define RING1_RX_DLY_INT BIT(25) ++ ++#define ALT_RPLC_INT3 BIT(23) ++#define ALT_RPLC_INT2 BIT(22) ++#define ALT_RPLC_INT1 BIT(21) ++ ++#define RX_DONE_INT3 BIT(19) ++#define RX_DONE_INT2 BIT(18) ++#define RX_DONE_INT1 BIT(17) ++#define RX_DONE_INT0 BIT(16) ++ ++#define TX_DONE_INT3 BIT(3) ++#define TX_DONE_INT2 BIT(2) ++#define TX_DONE_INT1 BIT(1) ++#define TX_DONE_INT0 BIT(0) ++ ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++#define RLS_COHERENT BIT(29) ++#define RLS_DLY_INT BIT(28) ++#define RLS_DONE_INT BIT(0) ++#endif ++ ++#else ++//#define CNT_PPE_AF BIT(31) ++//#define CNT_GDM_AF BIT(29) ++#define PSE_P2_FC BIT(26) ++#define GDM_CRC_DROP BIT(25) ++#define PSE_BUF_DROP BIT(24) ++#define GDM_OTHER_DROP BIT(23) ++#define PSE_P1_FC BIT(22) ++#define PSE_P0_FC BIT(21) ++#define PSE_FQ_EMPTY BIT(20) ++#define GE1_STA_CHG BIT(18) ++#define TX_COHERENT BIT(17) ++#define RX_COHERENT BIT(16) ++ ++#define TX_DONE_INT3 BIT(11) ++#define TX_DONE_INT2 BIT(10) ++#define TX_DONE_INT1 BIT(9) ++#define TX_DONE_INT0 BIT(8) ++#define RX_DONE_INT1 RX_DONE_INT0 ++#define RX_DONE_INT0 BIT(2) ++#define TX_DLY_INT BIT(1) ++#define RX_DLY_INT BIT(0) ++#endif ++ ++#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \ ++ TX_DONE_INT1 | TX_DONE_INT0 | \ ++ RX_DONE_INT0 | RX_DONE_INT1 | \ ++ RX_DONE_INT2 | RX_DONE_INT3) ++ ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1) ++#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT) ++ ++#define NUM_QDMA_PAGE 512 ++#define QDMA_PAGE_SIZE 2048 ++#endif ++/* ++ * SW_INT_STATUS ++ */ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++#define PORT0_QUEUE_FULL BIT(14) //port0 queue full ++#define PORT1_QUEUE_FULL BIT(15) //port1 queue full ++#define PORT2_QUEUE_FULL BIT(16) //port2 queue full ++#define PORT3_QUEUE_FULL BIT(17) //port3 queue full ++#define PORT4_QUEUE_FULL BIT(18) //port4 queue full ++#define PORT5_QUEUE_FULL BIT(19) //port5 queue full ++#define PORT6_QUEUE_FULL BIT(20) //port6 queue full ++#define SHARED_QUEUE_FULL BIT(23) //shared queue full ++#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped ++#define BC_STROM BIT(25) //the device is undergoing broadcast storm ++#define PORT_ST_CHG BIT(26) //Port status change ++#define UNSECURED_ALERT BIT(27) //Intruder alert ++#define ABNORMAL_ALERT BIT(28) //Abnormal ++ ++#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00) ++#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04) ++#define ESW_INT_ALL (PORT_ST_CHG) ++ ++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) ++#define MIB_INT BIT(25) ++#define ACL_INT BIT(24) ++#define P5_LINK_CH BIT(5) ++#define P4_LINK_CH BIT(4) ++#define P3_LINK_CH BIT(3) ++#define P2_LINK_CH BIT(2) ++#define P1_LINK_CH BIT(1) ++#define P0_LINK_CH BIT(0) ++ ++#define RX_GOCT_CNT BIT(4) ++#define RX_GOOD_CNT BIT(6) ++#define TX_GOCT_CNT BIT(17) ++#define TX_GOOD_CNT BIT(19) ++ ++#define MSK_RX_GOCT_CNT BIT(4) ++#define MSK_RX_GOOD_CNT BIT(6) ++#define MSK_TX_GOCT_CNT BIT(17) ++#define MSK_TX_GOOD_CNT BIT(19) ++#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT) ++//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT) ++ ++ ++#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8) ++#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC) ++#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT) ++#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8) ++#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004) ++#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104) ++#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204) ++#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304) ++#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404) ++#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504) ++#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604) ++#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008) ++#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108) ++#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208) ++#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308) ++#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408) ++#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508) ++#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608) ++ ++#if defined (CONFIG_RALINK_MT7620) ++#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704) ++#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708) ++#endif ++ ++ ++#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000) ++ ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ++#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000) ++ ++#define P5_LINK_CH BIT(5) ++#define P4_LINK_CH BIT(4) ++#define P3_LINK_CH BIT(3) ++#define P2_LINK_CH BIT(2) ++#define P1_LINK_CH BIT(1) ++#define P0_LINK_CH BIT(0) ++ ++ ++#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)// ++ ++#define RX_BUF_ALLOC_SIZE 2000 ++#define FASTPATH_HEADROOM 64 ++ ++#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line ++ ++#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \ ++ ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \ ++ ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr)) ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++typedef struct _PSEUDO_ADAPTER { ++ struct net_device *RaethDev; ++ struct net_device *PseudoDev; ++ struct net_device_stats stat; ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++ struct mii_if_info mii_info; ++#endif ++ ++} PSEUDO_ADAPTER, PPSEUDO_ADAPTER; ++ ++#define MAX_PSEUDO_ENTRY 1 ++#endif ++ ++ ++ ++/* Register Categories Definition */ ++#define RAFRAMEENGINE_OFFSET 0x0000 ++#define RAGDMA_OFFSET 0x0020 ++#define RAPSE_OFFSET 0x0040 ++#define RAGDMA2_OFFSET 0x0060 ++#define RACDMA_OFFSET 0x0080 ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) || \ ++ defined (CONFIG_ARCH_MT7623) ++ ++#define RAPDMA_OFFSET 0x0800 ++#define SDM_OFFSET 0x0C00 ++#else ++#define RAPDMA_OFFSET 0x0100 ++#endif ++#define RAPPE_OFFSET 0x0200 ++#define RACMTABLE_OFFSET 0x0400 ++#define RAPOLICYTABLE_OFFSET 0x1000 ++ ++ ++/* Register Map Detail */ ++/* RT3883 */ ++#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14) ++ ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ ++/* 1. PDMA */ ++#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000) ++#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004) ++#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008) ++#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C) ++ ++#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010) ++#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014) ++#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018) ++#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C) ++ ++#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020) ++#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024) ++#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028) ++#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C) ++ ++#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030) ++#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034) ++#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038) ++#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C) ++ ++#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100) ++#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104) ++#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108) ++#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C) ++ ++#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110) ++#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114) ++#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118) ++#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C) ++ ++#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200) ++#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204) ++#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208) ++#define PDMA_RST_CFG (PDMA_RST_IDX) ++#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C) ++#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210) ++#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220) ++#define FE_INT_STATUS (INT_STATUS) ++#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228) ++#define FE_INT_ENABLE (INT_MASK) ++#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280) ++#define PDMA_SCH_CFG (PDMA_WRR) ++ ++#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration ++#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring ++#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring ++#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB ++#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB ++#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count ++#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count ++#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count ++#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count ++#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count ++ ++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || \ ++ defined (CONFIG_ARCH_MT7623) ++ ++/* Old FE with New PDMA */ ++#define PDMA_RELATED 0x0800 ++/* 1. PDMA */ ++#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000) ++#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004) ++#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008) ++#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C) ++ ++#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010) ++#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014) ++#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018) ++#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C) ++ ++#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020) ++#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024) ++#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028) ++#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C) ++ ++#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030) ++#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034) ++#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038) ++#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C) ++ ++#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100) ++#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104) ++#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108) ++#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C) ++ ++#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110) ++#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114) ++#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118) ++#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C) ++ ++#define RX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x120) ++#define RX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x124) ++#define RX_CALC_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x128) ++#define RX_DRX_IDX12 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x12C) ++ ++#define RX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x130) ++#define RX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x134) ++#define RX_CALC_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x138) ++#define RX_DRX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x13C) ++ ++#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200) ++#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204) ++#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208) ++#define PDMA_RST_CFG (PDMA_RST_IDX) ++#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C) ++#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210) ++#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220) ++#define FE_INT_STATUS (INT_STATUS) ++#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228) ++#define FE_INT_ENABLE (INT_MASK) ++#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280) ++#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284) ++ ++#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00 ++#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04 ++#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08 ++#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c ++//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18 ++#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10 ++ ++#if defined (CONFIG_RALINK_MT7620) ++#define GDMA1_RELATED 0x0600 ++#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00) ++#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04) ++#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08) ++#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C) ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++#define GDMA1_RELATED 0x0500 ++#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00) ++#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04) ++#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08) ++#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C) ++ ++#define GDMA2_RELATED 0x1500 ++#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00) ++#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04) ++#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08) ++#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C) ++#else ++#define GDMA1_RELATED 0x0020 ++#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00) ++#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04) ++#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08) ++#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C) ++#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10) ++ ++#define GDMA2_RELATED 0x0060 ++#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00) ++#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04) ++#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08) ++#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C) ++#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10) ++#endif ++ ++#if defined (CONFIG_RALINK_MT7620) ++#define PSE_RELATED 0x0500 ++#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00) ++#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04) ++#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08) ++#else ++#define PSE_RELATED 0x0040 ++#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00) ++#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04) ++#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08) ++#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C) ++#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10) ++#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14) ++#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18) ++#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C) ++#endif ++ ++ ++#if defined (CONFIG_RALINK_MT7620) ++#define CDMA_RELATED 0x0400 ++#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) ++#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4) ++#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8) ++#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0) ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++#define CDMA_RELATED 0x0400 ++#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition ++#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) ++#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04) ++#else ++#define CDMA_RELATED 0x0080 ++#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) ++#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04) ++#define SMACCR0 (RALINK_ETH_SW_BASE + 0x30E4) ++#define SMACCR1 (RALINK_ETH_SW_BASE + 0x30E8) ++#define CKGCR (RALINK_ETH_SW_BASE + 0x30F0) ++#endif ++ ++#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x100) ++ ++ ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++/*kurtis: add QDMA define*/ ++ ++#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C) ++#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58) ++ ++#define QDMA_RELATED 0x1800 ++#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000) ++#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004) ++#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008) ++#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C) ++#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010) ++#define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014) ++#define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018) ++#define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C) ++#define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020) ++#define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024) ++#define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028) ++#define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C) ++#define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030) ++#define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034) ++#define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038) ++#define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C) ++#define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040) ++#define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044) ++#define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048) ++#define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C) ++#define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050) ++#define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054) ++#define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058) ++#define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C) ++#define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060) ++#define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064) ++#define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068) ++#define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C) ++#define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070) ++#define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074) ++#define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078) ++#define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C) ++#define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080) ++#define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084) ++#define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088) ++#define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C) ++#define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090) ++#define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094) ++#define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098) ++#define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C) ++#define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0) ++#define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4) ++#define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8) ++#define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC) ++#define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0) ++#define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4) ++#define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8) ++#define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC) ++#define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0) ++#define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4) ++#define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8) ++#define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC) ++#define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0) ++#define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4) ++#define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8) ++#define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC) ++#define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0) ++#define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4) ++#define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8) ++#define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC) ++#define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0) ++#define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4) ++#define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8) ++#define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC) ++#define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100) ++#define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104) ++#define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108) ++#define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C) ++#define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110) ++#define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114) ++#define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118) ++#define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C) ++#if defined (CONFIG_ARCH_MT7623) ++#define VQTX_TB_BASE_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x180) ++#define VQTX_TB_BASE_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x184) ++#define VQTX_TB_BASE_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x188) ++#define VQTX_TB_BASE_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x18C) ++#endif ++#define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200) ++#define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204) ++#define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208) ++#define QDMA_RST_CFG (QDMA_RST_IDX) ++#define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C) ++#define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210) ++#define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214) ++#define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218) ++#define QFE_INT_STATUS (QDMA_INT_STS) ++#define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C) ++#define QFE_INT_ENABLE (QDMA_INT_MASK) ++#define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220) ++#define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224) ++#define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228) ++#define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C) ++#define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230) ++#define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234) ++#define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238) ++#define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240) ++#define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244) ++#define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248) ++#define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C) ++#define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300) ++#define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304) ++#define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308) ++#define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310) ++#define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314) ++#define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318) ++#define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320) ++#define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324) ++#define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328) ++#define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C) ++#define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350) ++#define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354) ++#define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358) ++#define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C) ++#define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360) ++#define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364) ++#define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368) ++#define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C) ++ ++ ++#endif/*MT7621 QDMA*/ ++ ++#else ++ ++/* 1. Frame Engine Global Registers */ ++#define MDIO_ACCESS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00) ++#define MDIO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04) ++#define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08) ++#define FE_RST_GL (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C) ++#define FE_INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10) ++#define FE_INT_ENABLE (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14) ++#define MDIO_CFG2 (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA ++#define FOC_TS_T (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C) ++ ++ ++/* 2. GDMA Registers */ ++#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00) ++#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04) ++#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08) ++#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C) ++#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10) ++ ++#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00) ++#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04) ++#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08) ++#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C) ++#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10) ++ ++/* 3. PSE */ ++#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00) ++#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04) ++#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08) ++#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C) ++#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x1f0) ++ ++/* 4. CDMA */ ++#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00) ++#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04) ++/* skip ppoe sid and vlan id definition */ ++ ++ ++/* 5. PDMA */ ++#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00) ++#define PDMA_RST_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04) ++#define PDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08) ++ ++#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C) ++ ++#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10) ++#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14) ++#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18) ++#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C) ++ ++#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20) ++#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24) ++#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28) ++#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C) ++ ++#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40) ++#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44) ++#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48) ++#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C) ++ ++#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50) ++#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54) ++#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58) ++#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C) ++ ++#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30) ++#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34) ++#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38) ++#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C) ++ ++#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40) ++#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44) ++#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48) ++#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C) ++ ++#endif ++ ++#define DELAY_INT_INIT 0x84048404 ++#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT) ++ ++ ++#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628) ++ ++/* 6. Counter and Meter Table */ ++#define PPE_AC_BCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */ ++#define PPE_AC_PCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */ ++/* 0 ~ 63 */ ++ ++#define PPE_MTR_CNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */ ++/* skip... */ ++#define PPE_MTR_CNT63 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC) ++ ++#define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */ ++#define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */ ++#define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */ ++#define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */ ++ ++/* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */ ++#define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320) ++#define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324) ++#define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328) ++#define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C) ++#define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330) ++#define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334) ++#define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338) ++#define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C) ++ ++#endif ++ ++/* LRO global control */ ++/* Bits [15:0]:LRO_ALT_RFSH_TIMER, Bits [20:16]:LRO_ALT_TICK_TIMER */ ++#define LRO_ALT_REFRESH_TIMER (RALINK_FRAME_ENGINE_BASE+0x001C) ++ ++/* LRO auto-learn table info */ ++#define PDMA_FE_ALT_CF8 (RALINK_FRAME_ENGINE_BASE+0x0300) ++#define PDMA_FE_ALT_SGL_CFC (RALINK_FRAME_ENGINE_BASE+0x0304) ++#define PDMA_FE_ALT_SEQ_CFC (RALINK_FRAME_ENGINE_BASE+0x0308) ++ ++/* LRO controls */ ++#define ADMA_LRO_CTRL_OFFSET 0x0980 ++/* ++ * Bit [0]:LRO_EN, Bit [1]:LRO_IPv6_EN, Bit [2]:MULTIPLE_NON_LRO_RX_RING_EN, Bit [3]:MULTIPLE_RXD_PREFETCH_EN, ++ * Bit [4]:RXD_PREFETCH_EN, Bit [5]:LRO_DLY_INT_EN, Bit [6]:LRO_CRSN_BNW, Bit [7]:L3_CKS_UPD_EN, ++ * Bit [20]:first_ineligible_pkt_redirect_en, Bit [21]:cr_lro_alt_score_mode, Bit [22]:cr_lro_alt_rplc_mode, ++ * Bit [23]:cr_lro_l4_ctrl_psh_en, Bits [28:26]:LRO_RING_RELINGUISH_REQ, Bits [31:29]:LRO_RING_RELINGUISH_DONE ++ */ ++#define ADMA_LRO_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE+ADMA_LRO_CTRL_OFFSET+0x00) ++/* Bits [31:0]:LRO_CPU_REASON */ ++#define ADMA_LRO_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE+ADMA_LRO_CTRL_OFFSET+0x04) ++/* Bits [31:0]:AUTO_LEARN_LRO_ELIGIBLE_THRESHOLD */ ++#define ADMA_LRO_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE+ADMA_LRO_CTRL_OFFSET+0x08) ++/* ++ * Bits [7:0]:LRO_MAX_AGGREGATED_CNT, Bits [11:8]:LRO_VLAN_EN, Bits [13:12]:LRO_VLAN_VID_CMP_DEPTH, ++ * Bit [14]:ADMA_FW_RSTN_REQ, Bit [15]:ADMA_MODE, Bits [31:16]:LRO_MIN_RXD_SDL0 ++ */ ++#define ADMA_LRO_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE+ADMA_LRO_CTRL_OFFSET+0x0C) ++ ++/* LRO RX delay interrupt configurations */ ++#define LRO_RX1_DLY_INT (RALINK_FRAME_ENGINE_BASE+0x0a70) ++#define LRO_RX2_DLY_INT (RALINK_FRAME_ENGINE_BASE+0x0a74) ++#define LRO_RX3_DLY_INT (RALINK_FRAME_ENGINE_BASE+0x0a78) ++ ++/* LRO auto-learn configurations */ ++#define PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET 0x0990 ++#define PDMA_LRO_ATL_OVERFLOW_ADJ (RALINK_FRAME_ENGINE_BASE+PDMA_LRO_ATL_OVERFLOW_ADJ_OFFSET) ++#define LRO_ALT_SCORE_DELTA (RALINK_FRAME_ENGINE_BASE+0x0a4c) ++ ++/* LRO agg timer configurations */ ++#define LRO_MAX_AGG_TIME (RALINK_FRAME_ENGINE_BASE+0x0a5c) ++ ++/* LRO configurations of RX ring #0 */ ++#define LRO_RXRING0_OFFSET 0x0b00 ++#define LRO_RX_RING0_DIP_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x04) ++#define LRO_RX_RING0_DIP_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x08) ++#define LRO_RX_RING0_DIP_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x0C) ++#define LRO_RX_RING0_DIP_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x10) ++#define LRO_RX_RING0_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x28) ++/* Bit [8]:RING0_VLD, Bit [9]:RING0_MYIP_VLD */ ++#define LRO_RX_RING0_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x2C) ++#define LRO_RX_RING0_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING0_OFFSET+0x30) ++/* LRO configurations of RX ring #1 */ ++#define LRO_RXRING1_OFFSET 0x0b40 ++#define LRO_RX_RING1_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x00) ++#define LRO_RX_RING1_DIP_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x04) ++#define LRO_RX_RING1_DIP_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x08) ++#define LRO_RX_RING1_DIP_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x0C) ++#define LRO_RX_RING1_DIP_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x10) ++#define LRO_RX_RING1_SIP_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x14) ++#define LRO_RX_RING1_SIP_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x18) ++#define LRO_RX_RING1_SIP_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x1C) ++#define LRO_RX_RING1_SIP_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x20) ++#define LRO_RX_RING1_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x24) ++#define LRO_RX_RING1_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x28) ++#define LRO_RX_RING1_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x2C) ++#define LRO_RX_RING1_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING1_OFFSET+0x30) ++#define LRO_RXRING2_OFFSET 0x0b80 ++#define LRO_RX_RING2_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x00) ++#define LRO_RX_RING2_DIP_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x04) ++#define LRO_RX_RING2_DIP_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x08) ++#define LRO_RX_RING2_DIP_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x0C) ++#define LRO_RX_RING2_DIP_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x10) ++#define LRO_RX_RING2_SIP_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x14) ++#define LRO_RX_RING2_SIP_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x18) ++#define LRO_RX_RING2_SIP_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x1C) ++#define LRO_RX_RING2_SIP_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x20) ++#define LRO_RX_RING2_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x24) ++#define LRO_RX_RING2_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x28) ++#define LRO_RX_RING2_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x2C) ++#define LRO_RX_RING2_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING2_OFFSET+0x30) ++#define LRO_RXRING3_OFFSET 0x0bc0 ++#define LRO_RX_RING3_STP_DTP_DW (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x00) ++#define LRO_RX_RING3_DIP_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x04) ++#define LRO_RX_RING3_DIP_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x08) ++#define LRO_RX_RING3_DIP_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x0C) ++#define LRO_RX_RING3_DIP_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x10) ++#define LRO_RX_RING3_SIP_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x14) ++#define LRO_RX_RING3_SIP_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x18) ++#define LRO_RX_RING3_SIP_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x1C) ++#define LRO_RX_RING3_SIP_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x20) ++#define LRO_RX_RING3_CTRL_DW0 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x24) ++#define LRO_RX_RING3_CTRL_DW1 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x28) ++#define LRO_RX_RING3_CTRL_DW2 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x2C) ++#define LRO_RX_RING3_CTRL_DW3 (RALINK_FRAME_ENGINE_BASE+LRO_RXRING3_OFFSET+0x30) ++ ++/* LRO RX ring mode */ ++#define PDMA_RX_NORMAL_MODE (0x0) ++#define PDMA_RX_PSE_MODE (0x1) ++#define PDMA_RX_FORCE_PORT (0x2) ++#define PDMA_RX_AUTO_LEARN (0x3) ++ ++#define ADMA_RX_RING0 (0) ++#define ADMA_RX_RING1 (1) ++#define ADMA_RX_RING2 (2) ++#define ADMA_RX_RING3 (3) ++ ++#define ADMA_RX_LEN0_MASK (0x3fff) ++#define ADMA_RX_LEN1_MASK (0x3) ++ ++#define PDMA_LRO_EN BIT(0) ++#define PDMA_LRO_IPV6_EN BIT(1) ++#define PDMA_LRO_IPV4_CSUM_UPDATE_EN BIT(7) ++#define PDMA_LRO_IPV4_CTRL_PUSH_EN BIT(23) ++#define PDMA_LRO_RXD_PREFETCH_EN BITS(3,4) ++#define PDMA_NON_LRO_MULTI_EN BIT(2) ++#define PDMA_LRO_DLY_INT_EN BIT(5) ++#define PDMA_LRO_FUSH_REQ BITS(26,28) ++#define PDMA_LRO_RELINGUISH BITS(29,31) ++#define PDMA_LRO_FREQ_PRI_ADJ BITS(16,19) ++#define PDMA_LRO_TPUT_PRE_ADJ BITS(8,11) ++#define PDMA_LRO_TPUT_PRI_ADJ BITS(12,15) ++#define PDMA_LRO_ALT_SCORE_MODE BIT(21) ++#define PDMA_LRO_RING_AGE1 BITS(22,31) ++#define PDMA_LRO_RING_AGE2 BITS(0,5) ++#define PDMA_LRO_RING_AGG BITS(10,25) ++#define PDMA_LRO_RING_AGG_CNT1 BITS(26,31) ++#define PDMA_LRO_RING_AGG_CNT2 BITS(0,1) ++#define PDMA_LRO_ALT_TICK_TIMER BITS(16,20) ++#define PDMA_LRO_LRO_MIN_RXD_SDL0 BITS(16,31) ++ ++#define PDMA_LRO_DLY_INT_EN_OFFSET (5) ++#define PDMA_LRO_TPUT_PRE_ADJ_OFFSET (8) ++#define PDMA_LRO_FREQ_PRI_ADJ_OFFSET (16) ++#define PDMA_LRO_LRO_MIN_RXD_SDL0_OFFSET (16) ++#define PDMA_LRO_TPUT_PRI_ADJ_OFFSET (12) ++#define PDMA_LRO_ALT_SCORE_MODE_OFFSET (21) ++#define PDMA_LRO_FUSH_REQ_OFFSET (26) ++#define PDMA_NON_LRO_MULTI_EN_OFFSET (2) ++#define PDMA_LRO_IPV6_EN_OFFSET (1) ++#define PDMA_LRO_RXD_PREFETCH_EN_OFFSET (3) ++#define PDMA_LRO_IPV4_CSUM_UPDATE_EN_OFFSET (7) ++#define PDMA_LRO_IPV4_CTRL_PUSH_EN_OFFSET (23) ++#define PDMA_LRO_ALT_TICK_TIMER_OFFSET (16) ++ ++#define PDMA_LRO_TPUT_OVERFLOW_ADJ BITS(12,31) ++#define PDMA_LRO_CNT_OVERFLOW_ADJ BITS(0,11) ++ ++#define PDMA_LRO_TPUT_OVERFLOW_ADJ_OFFSET (12) ++#define PDMA_LRO_CNT_OVERFLOW_ADJ_OFFSET (0) ++ ++#define PDMA_LRO_ALT_BYTE_CNT_MODE (0) ++#define PDMA_LRO_ALT_PKT_CNT_MODE (1) ++ ++/* LRO_RX_RING1_CTRL_DW1 offsets */ ++#define PDMA_LRO_AGE_H_OFFSET (10) ++#define PDMA_LRO_RING_AGE1_OFFSET (22) ++#define PDMA_LRO_RING_AGG_CNT1_OFFSET (26) ++/* LRO_RX_RING1_CTRL_DW2 offsets */ ++#define PDMA_RX_MODE_OFFSET (6) ++#define PDMA_RX_PORT_VALID_OFFSET (8) ++#define PDMA_RX_MYIP_VALID_OFFSET (9) ++#define PDMA_LRO_RING_AGE2_OFFSET (0) ++#define PDMA_LRO_RING_AGG_OFFSET (10) ++#define PDMA_LRO_RING_AGG_CNT2_OFFSET (0) ++/* LRO_RX_RING1_CTRL_DW3 offsets */ ++#define PDMA_LRO_AGG_CNT_H_OFFSET (6) ++/* LRO_RX_RING1_STP_DTP_DW offsets */ ++#define PDMA_RX_TCP_SRC_PORT_OFFSET (16) ++#define PDMA_RX_TCP_DEST_PORT_OFFSET (0) ++/* LRO_RX_RING1_CTRL_DW0 offsets */ ++#define PDMA_RX_IPV4_FORCE_OFFSET (1) ++#define PDMA_RX_IPV6_FORCE_OFFSET (0) ++ ++#define SET_ADMA_RX_LEN0(x) ((x)&ADMA_RX_LEN0_MASK) ++#define SET_ADMA_RX_LEN1(x) ((x)&ADMA_RX_LEN1_MASK) ++ ++#define SET_PDMA_LRO_MAX_AGG_CNT(x) \ ++ { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW3; \ ++ *addr &= ~0xff; \ ++ *addr |= ((x) & 0xff); \ ++ } ++#define SET_PDMA_LRO_FLUSH_REQ(x) \ ++ { volatile unsigned int *addr = (unsigned int*)ADMA_LRO_CTRL_DW0; \ ++ *addr &= ~PDMA_LRO_FUSH_REQ; \ ++ *addr |= ((x) & 0x7)<>PDMA_LRO_AGE_H_OFFSET) & 0x03f)<>PDMA_LRO_AGG_CNT_H_OFFSET) & 0x03)< KERNEL_VERSION(2,6,35) ++ struct napi_struct napi; ++#endif ++#endif ++#ifdef CONFIG_PSEUDO_SUPPORT ++ struct net_device *PseudoDev; ++ unsigned int isPseudo; ++#endif ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++ struct mii_if_info mii_info; ++#endif ++#ifdef CONFIG_RAETH_LRO ++ struct lro_counters lro_counters; ++ struct net_lro_mgr lro_mgr; ++ struct net_lro_desc lro_arr[8]; ++#endif ++#ifdef CONFIG_RAETH_HW_VLAN_RX ++ struct vlan_group *vlgrp; ++#endif ++#if defined (CONFIG_RAETH_HW_LRO) ++ struct work_struct hw_lro_wq; ++ unsigned int hw_lro_pkt_interval[3]; ++ unsigned int hw_lro_alpha; /* 0 < packet interval alpha <= 10 */ ++ unsigned int hw_lro_fix_setting; /* 0: dynamical AGG/AGE time, 1: fixed AGG/AGE time */ ++#endif /* CONFIG_RAETH_HW_LRO */ ++} END_DEVICE, *pEND_DEVICE; ++ ++ ++#define RAETH_VERSION "v3.1" ++ ++#endif ++ ++#define DMA_GLO_CFG PDMA_GLO_CFG ++ ++#if defined(CONFIG_RAETH_QDMATX_QDMARX) ++#define GDMA1_FWD_PORT 0x5555 ++#define GDMA2_FWD_PORT 0x5555 ++#elif defined(CONFIG_RAETH_PDMATX_QDMARX) ++#define GDMA1_FWD_PORT 0x5555 ++#define GDMA2_FWD_PORT 0x5555 ++#else ++#define GDMA1_FWD_PORT 0x0000 ++#define GDMA2_FWD_PORT 0x0000 ++#endif ++ ++#if defined(CONFIG_RAETH_QDMATX_QDMARX) ++#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0 ++#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1 ++#elif defined(CONFIG_RAETH_PDMATX_QDMARX) ++#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0 ++#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1 ++#else ++#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0 ++#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1 ++#endif ++#define RAETH_RX_CALC_IDX2 RX_CALC_IDX2 ++#define RAETH_RX_CALC_IDX3 RX_CALC_IDX3 ++#define RAETH_FE_INT_STATUS FE_INT_STATUS ++#define RAETH_FE_INT_ALL FE_INT_ALL ++#define RAETH_FE_INT_ENABLE FE_INT_ENABLE ++#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT ++#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3 ++#define QFE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3 ++#define RAETH_TX_DLY_INT TX_DLY_INT ++#define RAETH_TX_DONE_INT0 TX_DONE_INT0 ++#define RAETH_DLY_INT_CFG DLY_INT_CFG +diff --git a/drivers/net/ethernet/raeth/ra_ethtool.c b/drivers/net/ethernet/raeth/ra_ethtool.c +new file mode 100644 +index 0000000..ff13e59 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_ethtool.c +@@ -0,0 +1,515 @@ ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "ra2882ethreg.h" ++#include "raether.h" ++#include "ra_mac.h" ++#include "ra_ethtool.h" ++ ++#define RAETHER_DRIVER_NAME "raether" ++#define RA_NUM_STATS 4 ++ ++ ++static struct { ++ const char str[ETH_GSTRING_LEN]; ++} ethtool_stats_keys[] = { ++ { "statistic1" }, ++ { "statistic2" }, ++ { "statistic3" }, ++ { "statistic4" }, ++}; ++ ++unsigned char get_current_phy_address(void) ++{ ++ struct net_device *cur_dev_p; ++ END_DEVICE *ei_local; ++#if 0 ++ for(cur_dev_p=dev_base; cur_dev_p!=NULL; cur_dev_p=cur_dev_p->next){ ++ if (strncmp(cur_dev_p->name, DEV_NAME /* "eth2" usually */, 4) == 0) ++ break; ++ } ++#else ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ cur_dev_p = dev_get_by_name(&init_net, DEV_NAME); ++#else ++ cur_dev_p = dev_get_by_name(DEV_NAME); ++#endif ++#endif ++ if(!cur_dev_p) ++ return 0; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ ei_local = netdev_priv(cur_dev_p); ++#else ++ ei_local = cur_dev_p->priv; ++#endif ++ return ei_local->mii_info.phy_id; ++} ++#if 0 ++static u32 et_get_tx_csum(struct net_device *dev) ++{ ++ return (sysRegRead(GDMA1_FWD_CFG) & GDM1_DISCRC) ? 0 : 1; // a pitfall here, "0" means to enable. ++} ++ ++static u32 et_get_rx_csum(struct net_device *dev) ++{ ++ return (sysRegRead(GDMA1_FWD_CFG) & GDM1_STRPCRC) ? 1 : 0; ++} ++ ++static int et_set_tx_csum(struct net_device *dev, u32 data) ++{ ++ int value; ++ //printk("et_set_tx_csum(): data = %d\n", data); ++ ++ value = sysRegRead(GDMA1_FWD_CFG); ++ if(data) ++ value |= GDM1_DISCRC; ++ else ++ value &= ~GDM1_DISCRC; ++ ++ sysRegWrite(GDMA1_FWD_CFG, value); ++ return 0; ++} ++ ++static int et_set_rx_csum(struct net_device *dev, u32 data) ++{ ++ int value; ++ //printk("et_set_rx_csum(): data = %d\n", data); ++ ++ value = sysRegRead(GDMA1_FWD_CFG); ++ if(data) ++ value |= GDM1_STRPCRC; ++ else ++ value &= ~GDM1_STRPCRC; ++ ++ sysRegWrite(GDMA1_FWD_CFG, value); ++ return 0; ++} ++#endif ++ ++#define MII_CR_ADDR 0x00 ++#define MII_CR_MR_AUTONEG_ENABLE (1 << 12) ++#define MII_CR_MR_RESTART_NEGOTIATION (1 << 9) ++ ++#define AUTO_NEGOTIATION_ADVERTISEMENT 0x04 ++#define AN_PAUSE (1 << 10) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++static void et_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) ++{ ++ int mii_an_reg; ++ int mdio_cfg_reg; ++ END_DEVICE *ei_local = dev->priv; ++ ++ // get mii auto-negotiation register ++ mii_mgr_read(ei_local->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg); ++ epause->autoneg = (mii_an_reg & AN_PAUSE) ? 1 : 0; //get autonet_enable flag bit ++ ++ mdio_cfg_reg = sysRegRead(MDIO_CFG); ++ epause->tx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_TX) ? 1 : 0; ++ epause->rx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_RX) ? 1 : 0; ++ ++ //printk("et_get_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause); ++} ++ ++static int et_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) ++{ ++ int mdio_cfg_reg; ++ int mii_an_reg; ++ END_DEVICE *ei_local = dev->priv; ++ ++ //printk("et_set_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause); ++ ++ // auto-neg pause ++ mii_mgr_read(ei_local->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg); ++ if(epause->autoneg) ++ mii_an_reg |= AN_PAUSE; ++ else ++ mii_an_reg &= ~AN_PAUSE; ++ mii_mgr_write(ei_local->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, mii_an_reg); ++ ++ // tx/rx pause ++ mdio_cfg_reg = sysRegRead(MDIO_CFG); ++ if(epause->tx_pause) ++ mdio_cfg_reg |= MDIO_CFG_GP1_FC_TX; ++ else ++ mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_TX; ++ if(epause->rx_pause) ++ mdio_cfg_reg |= MDIO_CFG_GP1_FC_RX; ++ else ++ mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_RX; ++ sysRegWrite(MDIO_CFG, mdio_cfg_reg); ++ ++ return 0; ++} ++ ++static int et_nway_reset(struct net_device *dev) ++{ ++ END_DEVICE *ei_local = dev->priv; ++ return mii_nway_restart(&ei_local->mii_info); ++} ++#endif ++ ++static u32 et_get_link(struct net_device *dev) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ END_DEVICE *ei_local = netdev_priv(dev); ++#else ++ END_DEVICE *ei_local = dev->priv; ++#endif ++ return mii_link_ok(&ei_local->mii_info); ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++static int et_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ END_DEVICE *ei_local = dev->priv; ++ int rc; ++ rc = mii_ethtool_sset(&ei_local->mii_info, cmd); ++ return rc; ++} ++#endif ++ ++static int et_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ END_DEVICE *ei_local = netdev_priv(dev); ++#else ++ END_DEVICE *ei_local = dev->priv; ++#endif ++ mii_ethtool_gset(&ei_local->mii_info, cmd); ++ return 0; ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++static u32 et_get_msglevel(struct net_device *dev) ++{ ++ return 0; ++} ++ ++static void et_set_msglevel(struct net_device *dev, u32 datum) ++{ ++ return; ++} ++ ++static void et_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) ++{ ++ //END_DEVICE *ei_local = dev->priv; ++ strcpy(info->driver, RAETHER_DRIVER_NAME); ++ strcpy(info->version, RAETH_VERSION); ++ strcpy(info->bus_info, "n/a"); ++ info->n_stats = RA_NUM_STATS; ++ info->eedump_len = 0; ++ info->regdump_len = 0; ++} ++ ++static int et_get_stats_count(struct net_device *dev) ++{ ++ return RA_NUM_STATS; ++} ++ ++static void et_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) ++{ ++// END_DEVICE *ei_local = dev->priv; ++ data[0] = 0;//np->xstats.early_rx; ++ data[1] = 0;//np->xstats.tx_buf_mapped; ++ data[2] = 0;//np->xstats.tx_timeouts; ++ data[3] = 0;//np->xstats.rx_lost_in_ring; ++} ++ ++static void et_get_strings(struct net_device *dev, u32 stringset, u8 *data) ++{ ++ memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); ++} ++#endif ++ ++/* ++ * mii_mgr_read wrapper for mii.o ethtool ++ */ ++int mdio_read(struct net_device *dev, int phy_id, int location) ++{ ++ unsigned int result; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ END_DEVICE *ei_local = netdev_priv(dev); ++#else ++ END_DEVICE *ei_local = dev->priv; ++#endif ++ mii_mgr_read( (unsigned int) ei_local->mii_info.phy_id, (unsigned int)location, &result); ++ //printk("\n%s mii.o query= phy_id:%d, address:%d retval:%x\n", dev->name, phy_id, location, result); ++ return (int)result; ++} ++ ++/* ++ * mii_mgr_write wrapper for mii.o ethtool ++ */ ++void mdio_write(struct net_device *dev, int phy_id, int location, int value) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ END_DEVICE *ei_local = netdev_priv(dev); ++#else ++ END_DEVICE *ei_local = dev->priv; ++#endif ++ //printk("mii.o write= phy_id:%d, address:%d value:%x\n", phy_id, location, value); ++ mii_mgr_write( (unsigned int) ei_local->mii_info.phy_id, (unsigned int)location, (unsigned int)value); ++ return; ++} ++ ++struct ethtool_ops ra_ethtool_ops = { ++ ++ .get_settings = et_get_settings, ++ .get_link = et_get_link, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++ .get_drvinfo = et_get_drvinfo, ++ .set_settings = et_set_settings, ++ .get_pauseparam = et_get_pauseparam, ++ .set_pauseparam = et_set_pauseparam, ++// .get_rx_csum = et_get_rx_csum, ++// .set_rx_csum = et_set_rx_csum, ++// .get_tx_csum = et_get_tx_csum, ++// .set_tx_csum = et_set_tx_csum, ++ .nway_reset = et_nway_reset, ++ .get_msglevel = et_get_msglevel, ++ .set_msglevel = et_set_msglevel, ++ .get_strings = et_get_strings, ++ .get_stats_count = et_get_stats_count, ++ .get_ethtool_stats = et_get_ethtool_stats, ++/* .get_regs_len = et_get_regs_len, ++ .get_regs = et_get_regs, ++*/ ++#endif ++}; ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++/* ++ * We unable to re-use the Raether functions because it is hard to tell ++ * where the calling from is. From eth2 or eth3? ++ * ++ * These code size is around 950 bytes. ++ */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++static void et_virt_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) ++{ ++ // PSEUDO_ADAPTER *pseudo = dev->priv; ++ return et_get_drvinfo(dev, info); ++} ++ ++static void et_virt_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) ++{ ++ int mii_an_reg, mdio_cfg_reg; ++ PSEUDO_ADAPTER *pseudo = dev->priv; ++ ++ // get mii auto-negotiation register ++ mii_mgr_read(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg); ++ epause->autoneg = (mii_an_reg & AN_PAUSE) ? 1 : 0; //get autonet_enable flag bit ++ ++ mdio_cfg_reg = sysRegRead(MDIO_CFG); ++ epause->tx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_TX) ? 1 : 0; ++ epause->rx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_RX) ? 1 : 0; ++ ++ //printk("et_get_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause); ++} ++ ++static int et_virt_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) ++{ ++ int mdio_cfg_reg; ++ int mii_an_reg; ++ PSEUDO_ADAPTER *pseudo = dev->priv; ++ ++ //printk("et_set_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause); ++ // auto-neg pause ++ mii_mgr_read(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg); ++ if(epause->autoneg) ++ mii_an_reg |= AN_PAUSE; ++ else ++ mii_an_reg &= ~AN_PAUSE; ++ mii_mgr_write(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, mii_an_reg); ++ ++ // tx/rx pause ++ mdio_cfg_reg = sysRegRead(MDIO_CFG); ++ if(epause->tx_pause) ++ mdio_cfg_reg |= MDIO_CFG_GP1_FC_TX; ++ else ++ mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_TX; ++ if(epause->rx_pause) ++ mdio_cfg_reg |= MDIO_CFG_GP1_FC_RX; ++ else ++ mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_RX; ++ sysRegWrite(MDIO_CFG, mdio_cfg_reg); ++ ++ return 0; ++} ++ ++static u32 et_virt_get_tx_csum(struct net_device *dev) ++{ ++ return (sysRegRead(GDMA2_FWD_CFG) & GDM1_DISCRC) ? 0 : 1; // a pitfall here, "0" means to enable. ++} ++ ++static u32 et_virt_get_rx_csum(struct net_device *dev) ++{ ++ return (sysRegRead(GDMA2_FWD_CFG) & GDM1_STRPCRC) ? 1 : 0; ++} ++ ++static int et_virt_set_tx_csum(struct net_device *dev, u32 data) ++{ ++ int value; ++ //printk("et_set_tx_csum(): data = %d\n", data); ++ value = sysRegRead(GDMA2_FWD_CFG); ++ if(data) ++ value |= GDM1_DISCRC; ++ else ++ value &= ~GDM1_DISCRC; ++ sysRegWrite(GDMA1_FWD_CFG, value); ++ return 0; ++} ++ ++static int et_virt_set_rx_csum(struct net_device *dev, u32 data) ++{ ++ int value; ++ //printk("et_set_rx_csum(): data = %d\n", data); ++ value = sysRegRead(GDMA2_FWD_CFG); ++ if(data) ++ value |= GDM1_STRPCRC; ++ else ++ value &= ~GDM1_STRPCRC; ++ sysRegWrite(GDMA1_FWD_CFG, value); ++ return 0; ++} ++ ++static int et_virt_nway_reset(struct net_device *dev) ++{ ++ PSEUDO_ADAPTER *pseudo = dev->priv; ++ return mii_nway_restart(&pseudo->mii_info); ++} ++#endif ++ ++static u32 et_virt_get_link(struct net_device *dev) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++#else ++ PSEUDO_ADAPTER *pseudo = dev->priv; ++#endif ++ return mii_link_ok(&pseudo->mii_info); ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++static int et_virt_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ PSEUDO_ADAPTER *pseudo = dev->priv; ++ int rc = mii_ethtool_sset(&pseudo->mii_info, cmd); ++ return rc; ++} ++#endif ++ ++static int et_virt_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++#else ++ PSEUDO_ADAPTER *pseudo = dev->priv; ++#endif ++ mii_ethtool_gset(&pseudo->mii_info, cmd); ++ return 0; ++} ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++static u32 et_virt_get_msglevel(struct net_device *dev) ++{ ++ return 0; ++} ++ ++static void et_virt_set_msglevel(struct net_device *dev, u32 datum) ++{ ++ return; ++} ++ ++static void et_virt_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) ++{ ++// PSEUDO_ADAPTER *pseudo = dev->priv; ++ data[0] = 0;//np->xstats.early_rx; ++ data[1] = 0;//np->xstats.tx_buf_mapped; ++ data[2] = 0;//np->xstats.tx_timeouts; ++ data[3] = 0;//np->xstats.rx_lost_in_ring; ++} ++ ++/* for virtual interface dedicated */ ++#define RA_VIRT_NUM_STATS 4 ++static struct { ++ const char str[ETH_GSTRING_LEN]; ++} ethtool_stats_keys_2[] = { ++ { "statistic1" }, ++ { "statistic2" }, ++ { "statistic3" }, ++ { "statistic4" }, ++}; ++ ++static int et_virt_get_stats_count(struct net_device *dev) ++{ ++ return RA_VIRT_NUM_STATS; ++} ++ ++static void et_virt_get_strings(struct net_device *dev, u32 stringset, u8 *data) ++{ ++ memcpy(data, ethtool_stats_keys_2, sizeof(ethtool_stats_keys_2)); ++} ++#endif ++ ++struct ethtool_ops ra_virt_ethtool_ops = { ++ .get_settings = et_virt_get_settings, ++ .get_link = et_virt_get_link, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++ .get_drvinfo = et_virt_get_drvinfo, ++ .set_settings = et_virt_set_settings, ++ .get_pauseparam = et_virt_get_pauseparam, ++ .set_pauseparam = et_virt_set_pauseparam, ++ .get_rx_csum = et_virt_get_rx_csum, ++ .set_rx_csum = et_virt_set_rx_csum, ++ .get_tx_csum = et_virt_get_tx_csum, ++ .set_tx_csum = et_virt_set_tx_csum, ++ .nway_reset = et_virt_nway_reset, ++ .get_msglevel = et_virt_get_msglevel, ++ .set_msglevel = et_virt_set_msglevel, ++ .get_strings = et_virt_get_strings, ++ .get_stats_count = et_virt_get_stats_count, ++ .get_ethtool_stats = et_virt_get_ethtool_stats, ++/* .get_regs_len = et_virt_get_regs_len, ++ .get_regs = et_virt_get_regs, ++*/ ++#endif ++}; ++ ++int mdio_virt_read(struct net_device *dev, int phy_id, int location) ++{ ++ unsigned int result; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++#else ++ PSEUDO_ADAPTER *pseudo = dev->priv; ++#endif ++ mii_mgr_read( (unsigned int) pseudo->mii_info.phy_id, (unsigned int)location, &result); ++// printk("%s mii.o query= phy_id:%d, address:%d retval:%d\n", dev->name, phy_id, location, result); ++ return (int)result; ++} ++ ++void mdio_virt_write(struct net_device *dev, int phy_id, int location, int value) ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ PSEUDO_ADAPTER *pseudo = netdev_priv(dev); ++#else ++ PSEUDO_ADAPTER *pseudo = dev->priv; ++#endif ++// printk("mii.o write= phy_id:%d, address:%d value:%d\n", phy_id, location, value); ++ mii_mgr_write( (unsigned int) pseudo->mii_info.phy_id, (unsigned int)location, (unsigned int)value); ++ return; ++} ++ ++#endif /* CONFIG_PSEUDO_SUPPORT */ ++ ++ +diff --git a/drivers/net/ethernet/raeth/ra_ethtool.h b/drivers/net/ethernet/raeth/ra_ethtool.h +new file mode 100644 +index 0000000..d64a1ab +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_ethtool.h +@@ -0,0 +1,13 @@ ++#ifndef RA_ETHTOOL_H ++#define RA_ETHTOOL_H ++ ++/* ethtool related */ ++unsigned char get_current_phy_address(void); ++int mdio_read(struct net_device *dev, int phy_id, int location); ++void mdio_write(struct net_device *dev, int phy_id, int location, int value); ++ ++/* for pseudo interface */ ++int mdio_virt_read(struct net_device *dev, int phy_id, int location); ++void mdio_virt_write(struct net_device *dev, int phy_id, int location, int value); ++ ++#endif +diff --git a/drivers/net/ethernet/raeth/ra_ioctl.h b/drivers/net/ethernet/raeth/ra_ioctl.h +new file mode 100644 +index 0000000..83b806a +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_ioctl.h +@@ -0,0 +1,102 @@ ++#ifndef _RAETH_IOCTL_H ++#define _RAETH_IOCTL_H ++ ++/* ioctl commands */ ++#define RAETH_ESW_REG_READ 0x89F1 ++#define RAETH_ESW_REG_WRITE 0x89F2 ++#define RAETH_MII_READ 0x89F3 ++#define RAETH_MII_WRITE 0x89F4 ++#define RAETH_ESW_INGRESS_RATE 0x89F5 ++#define RAETH_ESW_EGRESS_RATE 0x89F6 ++#define RAETH_ESW_PHY_DUMP 0x89F7 ++#define RAETH_QDMA_REG_READ 0x89F8 ++#define RAETH_QDMA_REG_WRITE 0x89F9 ++#define RAETH_QDMA_QUEUE_MAPPING 0x89FA ++#define RAETH_QDMA_READ_CPU_CLK 0x89FB ++#define RAETH_MII_READ_CL45 0x89FC ++#define RAETH_MII_WRITE_CL45 0x89FD ++#if defined(CONFIG_HW_SFQ) ++#define RAETH_QDMA_SFQ_WEB_ENABLE 0x89FE ++#endif ++ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \ ++ defined (CONFIG_ARCH_MT7623) ++ ++#define REG_ESW_WT_MAC_MFC 0x10 ++#define REG_ESW_ISC 0x18 ++#define REG_ESW_WT_MAC_ATA1 0x74 ++#define REG_ESW_WT_MAC_ATA2 0x78 ++#define REG_ESW_WT_MAC_ATWD 0x7C ++#define REG_ESW_WT_MAC_ATC 0x80 ++ ++#define REG_ESW_TABLE_TSRA1 0x84 ++#define REG_ESW_TABLE_TSRA2 0x88 ++#define REG_ESW_TABLE_ATRD 0x8C ++ ++ ++#define REG_ESW_VLAN_VTCR 0x90 ++#define REG_ESW_VLAN_VAWD1 0x94 ++#define REG_ESW_VLAN_VAWD2 0x98 ++ ++ ++#define REG_ESW_VLAN_ID_BASE 0x100 ++ ++//#define REG_ESW_VLAN_ID_BASE 0x50 ++#define REG_ESW_VLAN_MEMB_BASE 0x70 ++#define REG_ESW_TABLE_SEARCH 0x24 ++#define REG_ESW_TABLE_STATUS0 0x28 ++#define REG_ESW_TABLE_STATUS1 0x2C ++#define REG_ESW_TABLE_STATUS2 0x30 ++#define REG_ESW_WT_MAC_AD0 0x34 ++#define REG_ESW_WT_MAC_AD1 0x38 ++#define REG_ESW_WT_MAC_AD2 0x3C ++ ++#else ++/* rt3052 embedded ethernet switch registers */ ++#define REG_ESW_VLAN_ID_BASE 0x50 ++#define REG_ESW_VLAN_MEMB_BASE 0x70 ++#define REG_ESW_TABLE_SEARCH 0x24 ++#define REG_ESW_TABLE_STATUS0 0x28 ++#define REG_ESW_TABLE_STATUS1 0x2C ++#define REG_ESW_TABLE_STATUS2 0x30 ++#define REG_ESW_WT_MAC_AD0 0x34 ++#define REG_ESW_WT_MAC_AD1 0x38 ++#define REG_ESW_WT_MAC_AD2 0x3C ++#endif ++ ++ ++#if defined(CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++#define REG_ESW_MAX 0x16C ++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) ++#define REG_ESW_MAX 0x7FFFF ++#else //RT305x, RT3350 ++#define REG_ESW_MAX 0xFC ++#endif ++#define REG_HQOS_MAX 0x3FFF ++ ++ ++typedef struct rt3052_esw_reg { ++ unsigned int off; ++ unsigned int val; ++} esw_reg; ++ ++typedef struct ralink_mii_ioctl_data { ++ __u32 phy_id; ++ __u32 reg_num; ++ __u32 val_in; ++ __u32 val_out; ++ __u32 port_num; ++ __u32 dev_addr; ++ __u32 reg_addr; ++} ra_mii_ioctl_data; ++ ++typedef struct rt335x_esw_reg { ++ unsigned int on_off; ++ unsigned int port; ++ unsigned int bw;/*Mbps*/ ++} esw_rate; ++ ++ ++#endif +diff --git a/drivers/net/ethernet/raeth/ra_mac.c b/drivers/net/ethernet/raeth/ra_mac.c +new file mode 100644 +index 0000000..e8e978d +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_mac.c +@@ -0,0 +1,2645 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,4) ++#include ++#include ++#endif ++#include ++#include ++#include ++#include ++ ++#include /* for cp0 reg access, added by bobtseng */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++ ++#if defined(CONFIG_RAETH_LRO) ++#include ++#endif ++ ++#include "ra2882ethreg.h" ++#include "raether.h" ++#include "ra_mac.h" ++#include "ra_ethtool.h" ++#if defined(CONFIG_RAETH_PDMA_DVT) ++#include "dvt/raether_pdma_dvt.h" ++#endif //#if defined(CONFIG_RAETH_PDMA_DVT) ++ ++extern struct net_device *dev_raether; ++ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) ++extern unsigned short p0_rx_good_cnt; ++extern unsigned short p0_tx_good_cnt; ++extern unsigned short p1_rx_good_cnt; ++extern unsigned short p1_tx_good_cnt; ++extern unsigned short p2_rx_good_cnt; ++extern unsigned short p2_tx_good_cnt; ++extern unsigned short p3_rx_good_cnt; ++extern unsigned short p3_tx_good_cnt; ++extern unsigned short p4_rx_good_cnt; ++extern unsigned short p4_tx_good_cnt; ++extern unsigned short p5_rx_good_cnt; ++extern unsigned short p5_tx_good_cnt; ++extern unsigned short p6_rx_good_cnt; ++extern unsigned short p6_tx_good_cnt; ++ ++extern unsigned short p0_rx_byte_cnt; ++extern unsigned short p1_rx_byte_cnt; ++extern unsigned short p2_rx_byte_cnt; ++extern unsigned short p3_rx_byte_cnt; ++extern unsigned short p4_rx_byte_cnt; ++extern unsigned short p5_rx_byte_cnt; ++extern unsigned short p6_rx_byte_cnt; ++extern unsigned short p0_tx_byte_cnt; ++extern unsigned short p1_tx_byte_cnt; ++extern unsigned short p2_tx_byte_cnt; ++extern unsigned short p3_tx_byte_cnt; ++extern unsigned short p4_tx_byte_cnt; ++extern unsigned short p5_tx_byte_cnt; ++extern unsigned short p6_tx_byte_cnt; ++ ++#if defined(CONFIG_RALINK_MT7620) ++extern unsigned short p7_rx_good_cnt; ++extern unsigned short p7_tx_good_cnt; ++extern unsigned short p7_rx_byte_cnt; ++extern unsigned short p7_tx_byte_cnt; ++#endif ++#endif ++ ++ ++ ++#if defined(CONFIG_RAETH_TSO) ++int txd_cnt[MAX_SKB_FRAGS/2 + 1]; ++int tso_cnt[16]; ++#endif ++ ++#if defined(CONFIG_RAETH_LRO) ++#define MAX_AGGR 64 ++#define MAX_DESC 8 ++int lro_stats_cnt[MAX_AGGR + 1]; ++int lro_flush_cnt[MAX_AGGR + 1]; ++int lro_len_cnt1[16]; ++//int lro_len_cnt2[16]; ++int aggregated[MAX_DESC]; ++int lro_aggregated; ++int lro_flushed; ++int lro_nodesc; ++int force_flush; ++int tot_called1; ++int tot_called2; ++#endif ++ ++#if defined(CONFIG_RAETH_HW_LRO) ++#define HW_LRO_RING_NUM 3 ++#define MAX_HW_LRO_AGGR 64 ++unsigned int hw_lro_agg_num_cnt[HW_LRO_RING_NUM][MAX_HW_LRO_AGGR + 1]; ++unsigned int hw_lro_agg_size_cnt[HW_LRO_RING_NUM][16]; ++unsigned int hw_lro_tot_agg_cnt[HW_LRO_RING_NUM]; ++unsigned int hw_lro_tot_flush_cnt[HW_LRO_RING_NUM]; ++#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG) ++unsigned int hw_lro_agg_flush_cnt[HW_LRO_RING_NUM]; ++unsigned int hw_lro_age_flush_cnt[HW_LRO_RING_NUM]; ++unsigned int hw_lro_seq_flush_cnt[HW_LRO_RING_NUM]; ++unsigned int hw_lro_timestamp_flush_cnt[HW_LRO_RING_NUM]; ++unsigned int hw_lro_norule_flush_cnt[HW_LRO_RING_NUM]; ++#endif /* CONFIG_RAETH_HW_LRO_REASON_DBG */ ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if defined(CONFIG_RAETH_QDMA) ++extern unsigned int M2Q_table[64]; ++extern struct QDMA_txdesc *free_head; ++#endif ++#if defined (CONFIG_ARCH_MT7623) ++extern struct SFQ_table *sfq0; ++extern struct SFQ_table *sfq1; ++extern struct SFQ_table *sfq2; ++extern struct SFQ_table *sfq3; ++#endif ++ ++#if defined(CONFIG_USER_SNMPD) ++ ++static int ra_snmp_seq_show(struct seq_file *seq, void *v) ++{ ++#if !defined(CONFIG_RALINK_RT5350) && !defined(CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7628) ++ ++ seq_printf(seq, "rx counters: %x %x %x %x %x %x %x\n", sysRegRead(GDMA_RX_GBCNT0), sysRegRead(GDMA_RX_GPCNT0),sysRegRead(GDMA_RX_OERCNT0), sysRegRead(GDMA_RX_FERCNT0), sysRegRead(GDMA_RX_SERCNT0), sysRegRead(GDMA_RX_LERCNT0), sysRegRead(GDMA_RX_CERCNT0)); ++ ++ seq_printf(seq, "fc config: %x %x %x %x\n", sysRegRead(CDMA_FC_CFG), sysRegRead(GDMA1_FC_CFG), PDMA_FC_CFG, sysRegRead(PDMA_FC_CFG)); ++ ++ seq_printf(seq, "scheduler: %x %x %x\n", sysRegRead(GDMA1_SCH_CFG), sysRegRead(GDMA2_SCH_CFG), sysRegRead(PDMA_SCH_CFG)); ++ ++#endif ++ seq_printf(seq, "ports: %x %x %x %x %x %x\n", sysRegRead(PORT0_PKCOUNT), sysRegRead(PORT1_PKCOUNT), sysRegRead(PORT2_PKCOUNT), sysRegRead(PORT3_PKCOUNT), sysRegRead(PORT4_PKCOUNT), sysRegRead(PORT5_PKCOUNT)); ++ ++ return 0; ++} ++ ++static int ra_snmp_seq_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ra_snmp_seq_show, NULL); ++} ++ ++static const struct file_operations ra_snmp_seq_fops = { ++ .owner = THIS_MODULE, ++ .open = ra_snmp_seq_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++#endif ++ ++ ++#if defined (CONFIG_GIGAPHY) || defined (CONFIG_100PHY) || \ ++ defined (CONFIG_P5_MAC_TO_PHY_MODE) || defined (CONFIG_RAETH_GMAC2) ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \ ++ defined (CONFIG_ARCH_MT7623) ++void enable_auto_negotiate(int unused) ++{ ++ u32 regValue; ++#if !defined (CONFIG_RALINK_MT7621) && !defined (CONFIG_ARCH_MT7623) ++ u32 addr = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR; ++#endif ++ ++#if defined (CONFIG_RALINK_MT7621) ++ //enable MDIO mode all the time ++ regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60)); ++ regValue &= ~(0x3 << 12); ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue; ++#endif ++ ++ /* FIXME: we don't know how to deal with PHY end addr */ ++ regValue = sysRegRead(ESW_PHY_POLLING); ++ regValue |= (1<<31); ++ regValue &= ~(0x1f); ++ regValue &= ~(0x1f<<8); ++#if defined (CONFIG_RALINK_MT7620) ++ regValue |= ((addr-1) << 0);//setup PHY address for auto polling (Start Addr). ++ regValue |= (addr << 8);// setup PHY address for auto polling (End Addr). ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN)|| defined (CONFIG_GE_RGMII_INTERNAL_P4_AN) || defined (CONFIG_GE2_RGMII_AN) ++ regValue |= ((CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2-1)&0x1f << 0);//setup PHY address for auto polling (Start Addr). ++ regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 << 8);// setup PHY address for auto polling (End Addr). ++#else ++ regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR << 0);//setup PHY address for auto polling (Start Addr). ++ regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 << 8);// setup PHY address for auto polling (End Addr). ++#endif ++#else ++ regValue |= (addr << 0);// setup PHY address for auto polling (start Addr). ++ regValue |= (addr << 8);// setup PHY address for auto polling (End Addr). ++#endif ++ ++ /*kurtis: AN is strange*/ ++ sysRegWrite(ESW_PHY_POLLING, regValue); ++ ++#if defined (CONFIG_P4_MAC_TO_PHY_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x56330; ++#endif ++#if defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x56330; ++#endif ++} ++#elif defined (CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT3883) || \ ++ defined (CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) ++ ++void enable_auto_negotiate(int ge) ++{ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) ++ u32 regValue = sysRegRead(0xb01100C8); ++#else ++ u32 regValue; ++ regValue = (ge == 2)? sysRegRead(MDIO_CFG2) : sysRegRead(MDIO_CFG); ++#endif ++ ++ regValue &= 0xe0ff7fff; // clear auto polling related field: ++ // (MD_PHY1ADDR & GP1_FRC_EN). ++ regValue |= 0x20000000; // force to enable MDC/MDIO auto polling. ++ ++#if defined (CONFIG_GE2_RGMII_AN) || defined (CONFIG_GE2_MII_AN) ++ if(ge==2) { ++ regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 << 24); // setup PHY address for auto polling. ++ } ++#endif ++#if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_GE1_MII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ if(ge==1) { ++ regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR << 24); // setup PHY address for auto polling. ++ } ++#endif ++ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) ++ sysRegWrite(0xb01100C8, regValue); ++#else ++ if (ge == 2) ++ sysRegWrite(MDIO_CFG2, regValue); ++ else ++ sysRegWrite(MDIO_CFG, regValue); ++#endif ++} ++#endif ++#endif ++void ra2880stop(END_DEVICE *ei_local) ++{ ++ unsigned int regValue; ++ printk("ra2880stop()..."); ++ ++ regValue = sysRegRead(DMA_GLO_CFG); ++ regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); ++ sysRegWrite(DMA_GLO_CFG, regValue); ++ ++ printk("Done\n"); ++ // printk("Done0x%x...\n", readreg(DMA_GLO_CFG)); ++} ++ ++void ei_irq_clear(void) ++{ ++ sysRegWrite(FE_INT_STATUS, 0xFFFFFFFF); ++} ++ ++void rt2880_gmac_hard_reset(void) ++{ ++#if !defined (CONFIG_RALINK_RT6855A) ++ //FIXME ++ sysRegWrite(RSTCTRL, RALINK_FE_RST); ++ sysRegWrite(RSTCTRL, 0); ++#endif ++} ++ ++void ra2880EnableInterrupt() ++{ ++ unsigned int regValue = sysRegRead(FE_INT_ENABLE); ++ RAETH_PRINT("FE_INT_ENABLE -- : 0x%08x\n", regValue); ++// regValue |= (RX_DONE_INT0 | TX_DONE_INT0); ++ ++ sysRegWrite(FE_INT_ENABLE, regValue); ++} ++ ++void ra2880MacAddressSet(unsigned char p[6]) ++{ ++ unsigned long regValue; ++ ++ regValue = (p[0] << 8) | (p[1]); ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ sysRegWrite(SDM_MAC_ADRH, regValue); ++ printk("GMAC1_MAC_ADRH -- : 0x%08x\n", sysRegRead(SDM_MAC_ADRH)); ++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) ++ sysRegWrite(GDMA1_MAC_ADRH, regValue); ++ printk("GMAC1_MAC_ADRH -- : 0x%08x\n", sysRegRead(GDMA1_MAC_ADRH)); ++ ++ /* To keep the consistence between RT6855 and RT62806, GSW should keep the register. */ ++ sysRegWrite(SMACCR1, regValue); ++ printk("SMACCR1 -- : 0x%08x\n", sysRegRead(SMACCR1)); ++#elif defined (CONFIG_RALINK_MT7620) ++ sysRegWrite(SMACCR1, regValue); ++ printk("SMACCR1 -- : 0x%08x\n", sysRegRead(SMACCR1)); ++#else ++ sysRegWrite(GDMA1_MAC_ADRH, regValue); ++ printk("GMAC1_MAC_ADRH -- : 0x%08x\n", sysRegRead(GDMA1_MAC_ADRH)); ++#endif ++ ++ regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5]; ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ sysRegWrite(SDM_MAC_ADRL, regValue); ++ printk("GMAC1_MAC_ADRL -- : 0x%08x\n", sysRegRead(SDM_MAC_ADRL)); ++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) ++ sysRegWrite(GDMA1_MAC_ADRL, regValue); ++ printk("GMAC1_MAC_ADRL -- : 0x%08x\n", sysRegRead(GDMA1_MAC_ADRL)); ++ ++ /* To keep the consistence between RT6855 and RT62806, GSW should keep the register. */ ++ sysRegWrite(SMACCR0, regValue); ++ printk("SMACCR0 -- : 0x%08x\n", sysRegRead(SMACCR0)); ++#elif defined (CONFIG_RALINK_MT7620) ++ sysRegWrite(SMACCR0, regValue); ++ printk("SMACCR0 -- : 0x%08x\n", sysRegRead(SMACCR0)); ++#else ++ sysRegWrite(GDMA1_MAC_ADRL, regValue); ++ printk("GMAC1_MAC_ADRL -- : 0x%08x\n", sysRegRead(GDMA1_MAC_ADRL)); ++#endif ++ ++ return; ++} ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++void ra2880Mac2AddressSet(unsigned char p[6]) ++{ ++ unsigned long regValue; ++ ++ regValue = (p[0] << 8) | (p[1]); ++ sysRegWrite(GDMA2_MAC_ADRH, regValue); ++ ++ regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5]; ++ sysRegWrite(GDMA2_MAC_ADRL, regValue); ++ ++ printk("GDMA2_MAC_ADRH -- : 0x%08x\n", sysRegRead(GDMA2_MAC_ADRH)); ++ printk("GDMA2_MAC_ADRL -- : 0x%08x\n", sysRegRead(GDMA2_MAC_ADRL)); ++ return; ++} ++#endif ++ ++/** ++ * hard_init - Called by raeth_probe to inititialize network device ++ * @dev: device pointer ++ * ++ * ethdev_init initilize dev->priv and set to END_DEVICE structure ++ * ++ */ ++void ethtool_init(struct net_device *dev) ++{ ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++ // init mii structure ++ ei_local->mii_info.dev = dev; ++ ei_local->mii_info.mdio_read = mdio_read; ++ ei_local->mii_info.mdio_write = mdio_write; ++ ei_local->mii_info.phy_id_mask = 0x1f; ++ ei_local->mii_info.reg_num_mask = 0x1f; ++ ei_local->mii_info.supports_gmii = mii_check_gmii_support(&ei_local->mii_info); ++ // TODO: phy_id: 0~4 ++ ei_local->mii_info.phy_id = 1; ++#endif ++ return; ++} ++ ++/* ++ * Routine Name : get_idx(mode, index) ++ * Description: calculate ring usage for tx/rx rings ++ * Mode 1 : Tx Ring ++ * Mode 2 : Rx Ring ++ */ ++int get_ring_usage(int mode, int i) ++{ ++ unsigned long tx_ctx_idx, tx_dtx_idx, tx_usage; ++ unsigned long rx_calc_idx, rx_drx_idx, rx_usage; ++ ++ struct PDMA_rxdesc* rxring; ++ struct PDMA_txdesc* txring; ++ ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ ++ ++ if (mode == 2 ) { ++ /* cpu point to the next descriptor of rx dma ring */ ++ rx_calc_idx = *(unsigned long*)RX_CALC_IDX0; ++ rx_drx_idx = *(unsigned long*)RX_DRX_IDX0; ++ rxring = (struct PDMA_rxdesc*)RX_BASE_PTR0; ++ ++ rx_usage = (rx_drx_idx - rx_calc_idx -1 + NUM_RX_DESC) % NUM_RX_DESC; ++ if ( rx_calc_idx == rx_drx_idx ) { ++ if ( rxring[rx_drx_idx].rxd_info2.DDONE_bit == 1) ++ tx_usage = NUM_RX_DESC; ++ else ++ tx_usage = 0; ++ } ++ return rx_usage; ++ } ++ ++ ++ switch (i) { ++ case 0: ++ tx_ctx_idx = *(unsigned long*)TX_CTX_IDX0; ++ tx_dtx_idx = *(unsigned long*)TX_DTX_IDX0; ++ txring = ei_local->tx_ring0; ++ break; ++#if defined(CONFIG_RAETH_QOS) ++ case 1: ++ tx_ctx_idx = *(unsigned long*)TX_CTX_IDX1; ++ tx_dtx_idx = *(unsigned long*)TX_DTX_IDX1; ++ txring = ei_local->tx_ring1; ++ break; ++ case 2: ++ tx_ctx_idx = *(unsigned long*)TX_CTX_IDX2; ++ tx_dtx_idx = *(unsigned long*)TX_DTX_IDX2; ++ txring = ei_local->tx_ring2; ++ break; ++ case 3: ++ tx_ctx_idx = *(unsigned long*)TX_CTX_IDX3; ++ tx_dtx_idx = *(unsigned long*)TX_DTX_IDX3; ++ txring = ei_local->tx_ring3; ++ break; ++#endif ++ default: ++ printk("get_tx_idx failed %d %d\n", mode, i); ++ return 0; ++ }; ++ ++ tx_usage = (tx_ctx_idx - tx_dtx_idx + NUM_TX_DESC) % NUM_TX_DESC; ++ if ( tx_ctx_idx == tx_dtx_idx ) { ++ if ( txring[tx_ctx_idx].txd_info2.DDONE_bit == 1) ++ tx_usage = 0; ++ else ++ tx_usage = NUM_TX_DESC; ++ } ++ return tx_usage; ++ ++} ++ ++#if defined(CONFIG_RAETH_QOS) ++void dump_qos(struct seq_file *s) ++{ ++ int usage; ++ int i; ++ ++ seq_printf(s, "\n-----Raeth QOS -----\n\n"); ++ ++ for ( i = 0; i < 4; i++) { ++ usage = get_ring_usage(1,i); ++ seq_printf(s, "Tx Ring%d Usage : %d/%d\n", i, usage, NUM_TX_DESC); ++ } ++ ++ usage = get_ring_usage(2,0); ++ seq_printf(s, "RX Usage : %d/%d\n\n", usage, NUM_RX_DESC); ++#if defined (CONFIG_RALINK_MT7620) ++ seq_printf(s, "PSE_FQFC_CFG(0x%08x) : 0x%08x\n", PSE_FQFC_CFG, sysRegRead(PSE_FQFC_CFG)); ++ seq_printf(s, "PSE_IQ_CFG(0x%08x) : 0x%08x\n", PSE_IQ_CFG, sysRegRead(PSE_IQ_CFG)); ++ seq_printf(s, "PSE_QUE_STA(0x%08x) : 0x%08x\n", PSE_QUE_STA, sysRegRead(PSE_QUE_STA)); ++#elif defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ ++#else ++ seq_printf(s, "GDMA1_FC_CFG(0x%08x) : 0x%08x\n", GDMA1_FC_CFG, sysRegRead(GDMA1_FC_CFG)); ++ seq_printf(s, "GDMA2_FC_CFG(0x%08x) : 0x%08x\n", GDMA2_FC_CFG, sysRegRead(GDMA2_FC_CFG)); ++ seq_printf(s, "PDMA_FC_CFG(0x%08x) : 0x%08x\n", PDMA_FC_CFG, sysRegRead(PDMA_FC_CFG)); ++ seq_printf(s, "PSE_FQ_CFG(0x%08x) : 0x%08x\n", PSE_FQ_CFG, sysRegRead(PSE_FQ_CFG)); ++#endif ++ seq_printf(s, "\n\nTX_CTX_IDX0 : 0x%08x\n", sysRegRead(TX_CTX_IDX0)); ++ seq_printf(s, "TX_DTX_IDX0 : 0x%08x\n", sysRegRead(TX_DTX_IDX0)); ++ seq_printf(s, "TX_CTX_IDX1 : 0x%08x\n", sysRegRead(TX_CTX_IDX1)); ++ seq_printf(s, "TX_DTX_IDX1 : 0x%08x\n", sysRegRead(TX_DTX_IDX1)); ++ seq_printf(s, "TX_CTX_IDX2 : 0x%08x\n", sysRegRead(TX_CTX_IDX2)); ++ seq_printf(s, "TX_DTX_IDX2 : 0x%08x\n", sysRegRead(TX_DTX_IDX2)); ++ seq_printf(s, "TX_CTX_IDX3 : 0x%08x\n", sysRegRead(TX_CTX_IDX3)); ++ seq_printf(s, "TX_DTX_IDX3 : 0x%08x\n", sysRegRead(TX_DTX_IDX3)); ++ seq_printf(s, "RX_CALC_IDX0 : 0x%08x\n", sysRegRead(RX_CALC_IDX0)); ++ seq_printf(s, "RX_DRX_IDX0 : 0x%08x\n", sysRegRead(RX_DRX_IDX0)); ++ ++ seq_printf(s, "\n------------------------------\n\n"); ++} ++#endif ++ ++void dump_reg(struct seq_file *s) ++{ ++ int fe_int_enable; ++ int rx_usage; ++ int dly_int_cfg; ++ int rx_base_ptr0; ++ int rx_max_cnt0; ++ int rx_calc_idx0; ++ int rx_drx_idx0; ++#if !defined (CONFIG_RAETH_QDMA) ++ int tx_usage; ++ int tx_base_ptr[4]; ++ int tx_max_cnt[4]; ++ int tx_ctx_idx[4]; ++ int tx_dtx_idx[4]; ++ int i; ++#endif ++ ++ fe_int_enable = sysRegRead(FE_INT_ENABLE); ++ rx_usage = get_ring_usage(2,0); ++ ++ dly_int_cfg = sysRegRead(DLY_INT_CFG); ++ ++#if !defined (CONFIG_RAETH_QDMA) ++ tx_usage = get_ring_usage(1,0); ++ ++ tx_base_ptr[0] = sysRegRead(TX_BASE_PTR0); ++ tx_max_cnt[0] = sysRegRead(TX_MAX_CNT0); ++ tx_ctx_idx[0] = sysRegRead(TX_CTX_IDX0); ++ tx_dtx_idx[0] = sysRegRead(TX_DTX_IDX0); ++ ++ tx_base_ptr[1] = sysRegRead(TX_BASE_PTR1); ++ tx_max_cnt[1] = sysRegRead(TX_MAX_CNT1); ++ tx_ctx_idx[1] = sysRegRead(TX_CTX_IDX1); ++ tx_dtx_idx[1] = sysRegRead(TX_DTX_IDX1); ++ ++ tx_base_ptr[2] = sysRegRead(TX_BASE_PTR2); ++ tx_max_cnt[2] = sysRegRead(TX_MAX_CNT2); ++ tx_ctx_idx[2] = sysRegRead(TX_CTX_IDX2); ++ tx_dtx_idx[2] = sysRegRead(TX_DTX_IDX2); ++ ++ tx_base_ptr[3] = sysRegRead(TX_BASE_PTR3); ++ tx_max_cnt[3] = sysRegRead(TX_MAX_CNT3); ++ tx_ctx_idx[3] = sysRegRead(TX_CTX_IDX3); ++ tx_dtx_idx[3] = sysRegRead(TX_DTX_IDX3); ++#endif ++ ++ rx_base_ptr0 = sysRegRead(RX_BASE_PTR0); ++ rx_max_cnt0 = sysRegRead(RX_MAX_CNT0); ++ rx_calc_idx0 = sysRegRead(RX_CALC_IDX0); ++ rx_drx_idx0 = sysRegRead(RX_DRX_IDX0); ++ ++ seq_printf(s, "\n\nFE_INT_ENABLE : 0x%08x\n", fe_int_enable); ++#if !defined (CONFIG_RAETH_QDMA) ++ seq_printf(s, "TxRing PktCnt: %d/%d\n", tx_usage, NUM_TX_DESC); ++#endif ++ seq_printf(s, "RxRing PktCnt: %d/%d\n\n", rx_usage, NUM_RX_DESC); ++ seq_printf(s, "DLY_INT_CFG : 0x%08x\n", dly_int_cfg); ++ ++#if !defined (CONFIG_RAETH_QDMA) ++ for(i=0;i<4;i++) { ++ seq_printf(s, "TX_BASE_PTR%d : 0x%08x\n", i, tx_base_ptr[i]); ++ seq_printf(s, "TX_MAX_CNT%d : 0x%08x\n", i, tx_max_cnt[i]); ++ seq_printf(s, "TX_CTX_IDX%d : 0x%08x\n", i, tx_ctx_idx[i]); ++ seq_printf(s, "TX_DTX_IDX%d : 0x%08x\n", i, tx_dtx_idx[i]); ++ } ++#endif ++ ++ seq_printf(s, "RX_BASE_PTR0 : 0x%08x\n", rx_base_ptr0); ++ seq_printf(s, "RX_MAX_CNT0 : 0x%08x\n", rx_max_cnt0); ++ seq_printf(s, "RX_CALC_IDX0 : 0x%08x\n", rx_calc_idx0); ++ seq_printf(s, "RX_DRX_IDX0 : 0x%08x\n", rx_drx_idx0); ++ ++#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER) ++ seq_printf(s, "The current PHY address selected by ethtool is %d\n", get_current_phy_address()); ++#endif ++ ++#if defined (CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883) ++ seq_printf(s, "GDMA_RX_FCCNT1(0x%08x) : 0x%08x\n\n", GDMA_RX_FCCNT1, sysRegRead(GDMA_RX_FCCNT1)); ++#endif ++} ++ ++#if 0 ++void dump_cp0(void) ++{ ++ printk("CP0 Register dump --\n"); ++ printk("CP0_INDEX\t: 0x%08x\n", read_32bit_cp0_register(CP0_INDEX)); ++ printk("CP0_RANDOM\t: 0x%08x\n", read_32bit_cp0_register(CP0_RANDOM)); ++ printk("CP0_ENTRYLO0\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYLO0)); ++ printk("CP0_ENTRYLO1\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYLO1)); ++ printk("CP0_CONF\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONF)); ++ printk("CP0_CONTEXT\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONTEXT)); ++ printk("CP0_PAGEMASK\t: 0x%08x\n", read_32bit_cp0_register(CP0_PAGEMASK)); ++ printk("CP0_WIRED\t: 0x%08x\n", read_32bit_cp0_register(CP0_WIRED)); ++ printk("CP0_INFO\t: 0x%08x\n", read_32bit_cp0_register(CP0_INFO)); ++ printk("CP0_BADVADDR\t: 0x%08x\n", read_32bit_cp0_register(CP0_BADVADDR)); ++ printk("CP0_COUNT\t: 0x%08x\n", read_32bit_cp0_register(CP0_COUNT)); ++ printk("CP0_ENTRYHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYHI)); ++ printk("CP0_COMPARE\t: 0x%08x\n", read_32bit_cp0_register(CP0_COMPARE)); ++ printk("CP0_STATUS\t: 0x%08x\n", read_32bit_cp0_register(CP0_STATUS)); ++ printk("CP0_CAUSE\t: 0x%08x\n", read_32bit_cp0_register(CP0_CAUSE)); ++ printk("CP0_EPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_EPC)); ++ printk("CP0_PRID\t: 0x%08x\n", read_32bit_cp0_register(CP0_PRID)); ++ printk("CP0_CONFIG\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONFIG)); ++ printk("CP0_LLADDR\t: 0x%08x\n", read_32bit_cp0_register(CP0_LLADDR)); ++ printk("CP0_WATCHLO\t: 0x%08x\n", read_32bit_cp0_register(CP0_WATCHLO)); ++ printk("CP0_WATCHHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_WATCHHI)); ++ printk("CP0_XCONTEXT\t: 0x%08x\n", read_32bit_cp0_register(CP0_XCONTEXT)); ++ printk("CP0_FRAMEMASK\t: 0x%08x\n", read_32bit_cp0_register(CP0_FRAMEMASK)); ++ printk("CP0_DIAGNOSTIC\t: 0x%08x\n", read_32bit_cp0_register(CP0_DIAGNOSTIC)); ++ printk("CP0_DEBUG\t: 0x%08x\n", read_32bit_cp0_register(CP0_DEBUG)); ++ printk("CP0_DEPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_DEPC)); ++ printk("CP0_PERFORMANCE\t: 0x%08x\n", read_32bit_cp0_register(CP0_PERFORMANCE)); ++ printk("CP0_ECC\t: 0x%08x\n", read_32bit_cp0_register(CP0_ECC)); ++ printk("CP0_CACHEERR\t: 0x%08x\n", read_32bit_cp0_register(CP0_CACHEERR)); ++ printk("CP0_TAGLO\t: 0x%08x\n", read_32bit_cp0_register(CP0_TAGLO)); ++ printk("CP0_TAGHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_TAGHI)); ++ printk("CP0_ERROREPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_ERROREPC)); ++ printk("CP0_DESAVE\t: 0x%08x\n\n", read_32bit_cp0_register(CP0_DESAVE)); ++} ++#endif ++ ++struct proc_dir_entry *procRegDir; ++static struct proc_dir_entry *procGmac, *procSysCP0, *procTxRing, *procRxRing, *procSkbFree; ++#if defined(CONFIG_PSEUDO_SUPPORT) && defined(CONFIG_ETHTOOL) ++static struct proc_dir_entry *procGmac2; ++#endif ++#if defined(CONFIG_USER_SNMPD) ++static struct proc_dir_entry *procRaSnmp; ++#endif ++#if defined(CONFIG_RAETH_TSO) ++static struct proc_dir_entry *procNumOfTxd, *procTsoLen; ++#endif ++ ++#if defined(CONFIG_RAETH_LRO) ++static struct proc_dir_entry *procLroStats; ++#endif ++#if defined(CONFIG_RAETH_HW_LRO) || defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++static struct proc_dir_entry *procRxRing1, *procRxRing2, *procRxRing3; ++static struct proc_dir_entry *procHwLroStats, *procHwLroAutoTlb; ++const static HWLRO_DBG_FUNC hw_lro_dbg_func[] = ++{ ++ [0] = hwlro_agg_cnt_ctrl, ++ [1] = hwlro_agg_time_ctrl, ++ [2] = hwlro_age_time_ctrl, ++ [3] = hwlro_pkt_int_alpha_ctrl, ++ [4] = hwlro_threshold_ctrl, ++ [5] = hwlro_fix_setting_switch_ctrl, ++}; ++#endif /* CONFIG_RAETH_HW_LRO */ ++#if defined (TASKLET_WORKQUEUE_SW) ++static struct proc_dir_entry *procSCHE; ++#endif ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++static struct proc_dir_entry *procPdmaDvt; ++ ++const static PDMA_DBG_FUNC pdma_dvt_dbg_func[] = ++{ ++ [0] = pdma_dvt_show_ctrl, ++ [1] = pdma_dvt_test_rx_ctrl, ++ [2] = pdma_dvt_test_tx_ctrl, ++ [3] = pdma_dvt_test_debug_ctrl, ++ [4] = pdma_dvt_test_lro_ctrl, ++}; ++#endif //#if defined(CONFIG_RAETH_PDMA_DVT) ++ ++int RegReadMain(struct seq_file *seq, void *v) ++{ ++ dump_reg(seq); ++ return 0; ++} ++ ++static void *seq_SkbFree_start(struct seq_file *seq, loff_t *pos) ++{ ++ if (*pos < NUM_TX_DESC) ++ return pos; ++ return NULL; ++} ++ ++static void *seq_SkbFree_next(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ (*pos)++; ++ if (*pos >= NUM_TX_DESC) ++ return NULL; ++ return pos; ++} ++ ++static void seq_SkbFree_stop(struct seq_file *seq, void *v) ++{ ++ /* Nothing to do */ ++} ++ ++static int seq_SkbFree_show(struct seq_file *seq, void *v) ++{ ++ int i = *(loff_t *) v; ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ ++ seq_printf(seq, "%d: %08x\n",i, *(int *)&ei_local->skb_free[i]); ++ ++ return 0; ++} ++ ++static const struct seq_operations seq_skb_free_ops = { ++ .start = seq_SkbFree_start, ++ .next = seq_SkbFree_next, ++ .stop = seq_SkbFree_stop, ++ .show = seq_SkbFree_show ++}; ++ ++static int skb_free_open(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &seq_skb_free_ops); ++} ++ ++static const struct file_operations skb_free_fops = { ++ .owner = THIS_MODULE, ++ .open = skb_free_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release ++}; ++ ++#if defined (CONFIG_RAETH_QDMA) ++int QDMARead(struct seq_file *seq, void *v) ++{ ++ unsigned int temp,i; ++ unsigned int sw_fq, hw_fq; ++ unsigned int min_en, min_rate, max_en, max_rate, sch, weight; ++ unsigned int queue, tx_des_cnt, hw_resv, sw_resv, queue_head, queue_tail; ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++ seq_printf(seq, "==== General Information ====\n"); ++ temp = sysRegRead(QDMA_FQ_CNT); ++ sw_fq = (temp&0xFFFF0000)>>16; ++ hw_fq = (temp&0x0000FFFF); ++ seq_printf(seq, "SW TXD: %d/%d; HW TXD: %d/%d\n", sw_fq, NUM_TX_DESC, hw_fq,NUM_QDMA_PAGE); ++ seq_printf(seq, "SW TXD virtual start address: 0x%08x\n", ei_local->txd_pool); ++ seq_printf(seq, "HW TXD virtual start address: 0x%08x\n\n", free_head); ++ ++ seq_printf(seq, "==== Scheduler Information ====\n"); ++ temp = sysRegRead(QDMA_TX_SCH); ++ max_en = (temp&0x00000800)>>11; ++ max_rate = (temp&0x000007F0)>>4; ++ for(i=0;i<(temp&0x0000000F);i++) ++ max_rate *= 10; ++ seq_printf(seq, "SCH1 rate control:%d. Rate is %dKbps.\n", max_en, max_rate); ++ max_en = (temp&0x08000000)>>27; ++ max_rate = (temp&0x07F00000)>>20; ++ for(i=0;i<(temp&0x000F0000);i++) ++ max_rate *= 10; ++ seq_printf(seq, "SCH2 rate control:%d. Rate is %dKbps.\n\n", max_en, max_rate); ++ ++ seq_printf(seq, "==== Physical Queue Information ====\n"); ++ for (queue = 0; queue < 16; queue++){ ++ temp = sysRegRead(QTX_CFG_0 + 0x10 * queue); ++ tx_des_cnt = (temp & 0xffff0000) >> 16; ++ hw_resv = (temp & 0xff00) >> 8; ++ sw_resv = (temp & 0xff); ++ temp = sysRegRead(QTX_CFG_0 +(0x10 * queue) + 0x4); ++ sch = (temp >> 31) + 1 ; ++ min_en = (temp & 0x8000000) >> 27; ++ min_rate = (temp & 0x7f00000) >> 20; ++ for (i = 0; i< (temp & 0xf0000) >> 16; i++) ++ min_rate *= 10; ++ max_en = (temp & 0x800) >> 11; ++ max_rate = (temp & 0x7f0) >> 4; ++ for (i = 0; i< (temp & 0xf); i++) ++ max_rate *= 10; ++ weight = (temp & 0xf000) >> 12; ++ queue_head = sysRegRead(QTX_HEAD_0 + 0x10 * queue); ++ queue_tail = sysRegRead(QTX_TAIL_0 + 0x10 * queue); ++ ++ seq_printf(seq, "Queue#%d Information:\n", queue); ++ seq_printf(seq, "%d packets in the queue; head address is 0x%08x, tail address is 0x%08x.\n", tx_des_cnt, queue_head, queue_tail); ++ seq_printf(seq, "HW_RESV: %d; SW_RESV: %d; SCH: %d; Weighting: %d\n", hw_resv, sw_resv, sch, weight); ++ seq_printf(seq, "Min_Rate_En is %d, Min_Rate is %dKbps; Max_Rate_En is %d, Max_Rate is %dKbps.\n\n", min_en, min_rate, max_en, max_rate); ++ } ++#if defined (CONFIG_ARCH_MT7623) && defined(CONFIG_HW_SFQ) ++ seq_printf(seq, "==== Virtual Queue Information ====\n"); ++ seq_printf(seq, "VQTX_TB_BASE_0:0x%08x;VQTX_TB_BASE_1:0x%08x;VQTX_TB_BASE_2:0x%08x;VQTX_TB_BASE_3:0x%08x\n", \ ++ sfq0, sfq1, sfq2, sfq3); ++ temp = sysRegRead(VQTX_NUM); ++ seq_printf(seq, "VQTX_NUM_0:0x%01x;VQTX_NUM_1:0x%01x;VQTX_NUM_2:0x%01x;VQTX_NUM_3:0x%01x\n\n", \ ++ temp&0xF, (temp&0xF0)>>4, (temp&0xF00)>>8, (temp&0xF000)>>12); ++ ++#endif ++ ++ seq_printf(seq, "==== Flow Control Information ====\n"); ++ temp = sysRegRead(QDMA_FC_THRES); ++ seq_printf(seq, "SW_DROP_EN:%x; SW_DROP_FFA:%d; SW_DROP_MODE:%d\n", \ ++ (temp&0x1000000)>>24, (temp&0x200000)>>25, (temp&0x30000000)>>28); ++ seq_printf(seq, "WH_DROP_EN:%x; HW_DROP_FFA:%d; HW_DROP_MODE:%d\n", \ ++ (temp&0x10000)>>16, (temp&0x2000)>>17, (temp&0x300000)>>20); ++#if defined (CONFIG_ARCH_MT7623) ++ seq_printf(seq, "SW_DROP_FSTVQ_MODE:%d;SW_DROP_FSTVQ:%d\n", \ ++ (temp&0xC0000000)>>30, (temp&0x08000000)>>27); ++ seq_printf(seq, "HW_DROP_FSTVQ_MODE:%d;HW_DROP_FSTVQ:%d\n", \ ++ (temp&0xC00000)>>22, (temp&0x080000)>>19); ++#endif ++ ++ seq_printf(seq, "\n==== FSM Information\n"); ++ temp = sysRegRead(QDMA_DMA); ++#if defined (CONFIG_ARCH_MT7623) ++ seq_printf(seq, "VQTB_FSM:0x%01x\n", (temp&0x0F000000)>>24); ++#endif ++ seq_printf(seq, "FQ_FSM:0x%01x\n", (temp&0x000F0000)>>16); ++ seq_printf(seq, "TX_FSM:0x%01x\n", (temp&0x00000F00)>>12); ++ seq_printf(seq, "RX_FSM:0x%01x\n\n", (temp&0x0000000f)); ++ ++ seq_printf(seq, "==== M2Q Information ====\n"); ++ for (i = 0; i < 64; i+=8){ ++ seq_printf(seq, " (%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)(%d,%d)\n", ++ i, M2Q_table[i], i+1, M2Q_table[i+1], i+2, M2Q_table[i+2], i+3, M2Q_table[i+3], ++ i+4, M2Q_table[i+4], i+5, M2Q_table[i+5], i+6, M2Q_table[i+6], i+7, M2Q_table[i+7]); ++ } ++ ++ return 0; ++ ++} ++ ++static int qdma_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, QDMARead, NULL); ++} ++ ++static const struct file_operations qdma_fops = { ++ .owner = THIS_MODULE, ++ .open = qdma_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++#endif ++ ++int TxRingRead(struct seq_file *seq, void *v) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ struct PDMA_txdesc *tx_ring; ++ int i = 0; ++ ++ tx_ring = kmalloc(sizeof(struct PDMA_txdesc) * NUM_TX_DESC, GFP_KERNEL); ++ if(tx_ring==NULL){ ++ seq_printf(seq, " allocate temp tx_ring fail.\n"); ++ return 0; ++ } ++ ++ for (i=0; i < NUM_TX_DESC; i++) { ++ tx_ring[i] = ei_local->tx_ring0[i]; ++ } ++ ++ for (i=0; i < NUM_TX_DESC; i++) { ++#ifdef CONFIG_32B_DESC ++ seq_printf(seq, "%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",i, *(int *)&tx_ring[i].txd_info1, ++ *(int *)&tx_ring[i].txd_info2, *(int *)&tx_ring[i].txd_info3, ++ *(int *)&tx_ring[i].txd_info4, *(int *)&tx_ring[i].txd_info5, ++ *(int *)&tx_ring[i].txd_info6, *(int *)&tx_ring[i].txd_info7, ++ *(int *)&tx_ring[i].txd_info8); ++#else ++ seq_printf(seq, "%d: %08x %08x %08x %08x\n",i, *(int *)&tx_ring[i].txd_info1, *(int *)&tx_ring[i].txd_info2, ++ *(int *)&tx_ring[i].txd_info3, *(int *)&tx_ring[i].txd_info4); ++#endif ++ } ++ ++ kfree(tx_ring); ++ return 0; ++} ++ ++static int tx_ring_open(struct inode *inode, struct file *file) ++{ ++#if !defined (CONFIG_RAETH_QDMA) ++ return single_open(file, TxRingRead, NULL); ++#else ++ return single_open(file, QDMARead, NULL); ++#endif ++} ++ ++static const struct file_operations tx_ring_fops = { ++ .owner = THIS_MODULE, ++ .open = tx_ring_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++ ++int RxRingRead(struct seq_file *seq, void *v) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ struct PDMA_rxdesc *rx_ring; ++ int i = 0; ++ ++ rx_ring = kmalloc(sizeof(struct PDMA_rxdesc) * NUM_RX_DESC, GFP_KERNEL); ++ if(rx_ring==NULL){ ++ seq_printf(seq, " allocate temp rx_ring fail.\n"); ++ return 0; ++ } ++ ++ for (i=0; i < NUM_RX_DESC; i++) { ++ memcpy(&rx_ring[i], &ei_local->rx_ring0[i], sizeof(struct PDMA_rxdesc)); ++ } ++ ++ for (i=0; i < NUM_RX_DESC; i++) { ++#ifdef CONFIG_32B_DESC ++ seq_printf(seq, "%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",i, *(int *)&rx_ring[i].rxd_info1, ++ *(int *)&rx_ring[i].rxd_info2, *(int *)&rx_ring[i].rxd_info3, ++ *(int *)&rx_ring[i].rxd_info4, *(int *)&rx_ring[i].rxd_info5, ++ *(int *)&rx_ring[i].rxd_info6, *(int *)&rx_ring[i].rxd_info7, ++ *(int *)&rx_ring[i].rxd_info8); ++#else ++ seq_printf(seq, "%d: %08x %08x %08x %08x\n",i, *(int *)&rx_ring[i].rxd_info1, *(int *)&rx_ring[i].rxd_info2, ++ *(int *)&rx_ring[i].rxd_info3, *(int *)&rx_ring[i].rxd_info4); ++#endif ++ } ++ ++ kfree(rx_ring); ++ return 0; ++} ++ ++static int rx_ring_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, RxRingRead, NULL); ++} ++ ++static const struct file_operations rx_ring_fops = { ++ .owner = THIS_MODULE, ++ .open = rx_ring_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++ ++#if defined(CONFIG_RAETH_HW_LRO) || defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++int RxLRORingRead(struct seq_file *seq, void *v, struct PDMA_rxdesc *rx_ring_p) ++{ ++ struct PDMA_rxdesc *rx_ring; ++ int i = 0; ++ ++ rx_ring = kmalloc(sizeof(struct PDMA_rxdesc) * NUM_LRO_RX_DESC, GFP_KERNEL); ++ if(rx_ring==NULL){ ++ seq_printf(seq, " allocate temp rx_ring fail.\n"); ++ return 0; ++ } ++ ++ for (i=0; i < NUM_LRO_RX_DESC; i++) { ++ memcpy(&rx_ring[i], &rx_ring_p[i], sizeof(struct PDMA_rxdesc)); ++ } ++ ++ for (i=0; i < NUM_LRO_RX_DESC; i++) { ++#ifdef CONFIG_32B_DESC ++ seq_printf(seq, "%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",i, *(int *)&rx_ring[i].rxd_info1, ++ *(int *)&rx_ring[i].rxd_info2, *(int *)&rx_ring[i].rxd_info3, ++ *(int *)&rx_ring[i].rxd_info4, *(int *)&rx_ring[i].rxd_info5, ++ *(int *)&rx_ring[i].rxd_info6, *(int *)&rx_ring[i].rxd_info7, ++ *(int *)&rx_ring[i].rxd_info8); ++#else ++ seq_printf(seq, "%d: %08x %08x %08x %08x\n",i, *(int *)&rx_ring[i].rxd_info1, *(int *)&rx_ring[i].rxd_info2, ++ *(int *)&rx_ring[i].rxd_info3, *(int *)&rx_ring[i].rxd_info4); ++#endif ++ } ++ ++ kfree(rx_ring); ++ return 0; ++} ++ ++int RxRing1Read(struct seq_file *seq, void *v) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ RxLRORingRead(seq, v, ei_local->rx_ring1); ++ ++ return 0; ++} ++ ++int RxRing2Read(struct seq_file *seq, void *v) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ RxLRORingRead(seq, v, ei_local->rx_ring2); ++ ++ return 0; ++} ++ ++int RxRing3Read(struct seq_file *seq, void *v) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ RxLRORingRead(seq, v, ei_local->rx_ring3); ++ ++ return 0; ++} ++ ++static int rx_ring1_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, RxRing1Read, NULL); ++} ++ ++static int rx_ring2_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, RxRing2Read, NULL); ++} ++ ++static int rx_ring3_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, RxRing3Read, NULL); ++} ++ ++static const struct file_operations rx_ring1_fops = { ++ .owner = THIS_MODULE, ++ .open = rx_ring1_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++ ++static const struct file_operations rx_ring2_fops = { ++ .owner = THIS_MODULE, ++ .open = rx_ring2_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++ ++static const struct file_operations rx_ring3_fops = { ++ .owner = THIS_MODULE, ++ .open = rx_ring3_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if defined(CONFIG_RAETH_TSO) ++ ++int NumOfTxdUpdate(int num_of_txd) ++{ ++ ++ txd_cnt[num_of_txd]++; ++ ++ return 0; ++} ++ ++static void *seq_TsoTxdNum_start(struct seq_file *seq, loff_t *pos) ++{ ++ seq_printf(seq, "TXD | Count\n"); ++ if (*pos < (MAX_SKB_FRAGS/2 + 1)) ++ return pos; ++ return NULL; ++} ++ ++static void *seq_TsoTxdNum_next(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ (*pos)++; ++ if (*pos >= (MAX_SKB_FRAGS/2 + 1)) ++ return NULL; ++ return pos; ++} ++ ++static void seq_TsoTxdNum_stop(struct seq_file *seq, void *v) ++{ ++ /* Nothing to do */ ++} ++ ++static int seq_TsoTxdNum_show(struct seq_file *seq, void *v) ++{ ++ int i = *(loff_t *) v; ++ seq_printf(seq, "%d: %d\n",i , txd_cnt[i]); ++ ++ return 0; ++} ++ ++ssize_t NumOfTxdWrite(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ memset(txd_cnt, 0, sizeof(txd_cnt)); ++ printk("clear txd cnt table\n"); ++ ++ return count; ++} ++ ++int TsoLenUpdate(int tso_len) ++{ ++ ++ if(tso_len > 70000) { ++ tso_cnt[14]++; ++ }else if(tso_len > 65000) { ++ tso_cnt[13]++; ++ }else if(tso_len > 60000) { ++ tso_cnt[12]++; ++ }else if(tso_len > 55000) { ++ tso_cnt[11]++; ++ }else if(tso_len > 50000) { ++ tso_cnt[10]++; ++ }else if(tso_len > 45000) { ++ tso_cnt[9]++; ++ }else if(tso_len > 40000) { ++ tso_cnt[8]++; ++ }else if(tso_len > 35000) { ++ tso_cnt[7]++; ++ }else if(tso_len > 30000) { ++ tso_cnt[6]++; ++ }else if(tso_len > 25000) { ++ tso_cnt[5]++; ++ }else if(tso_len > 20000) { ++ tso_cnt[4]++; ++ }else if(tso_len > 15000) { ++ tso_cnt[3]++; ++ }else if(tso_len > 10000) { ++ tso_cnt[2]++; ++ }else if(tso_len > 5000) { ++ tso_cnt[1]++; ++ }else { ++ tso_cnt[0]++; ++ } ++ ++ return 0; ++} ++ ++ssize_t TsoLenWrite(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ memset(tso_cnt, 0, sizeof(tso_cnt)); ++ printk("clear tso cnt table\n"); ++ ++ return count; ++} ++ ++static void *seq_TsoLen_start(struct seq_file *seq, loff_t *pos) ++{ ++ seq_printf(seq, " Length | Count\n"); ++ if (*pos < 15) ++ return pos; ++ return NULL; ++} ++ ++static void *seq_TsoLen_next(struct seq_file *seq, void *v, loff_t *pos) ++{ ++ (*pos)++; ++ if (*pos >= 15) ++ return NULL; ++ return pos; ++} ++ ++static void seq_TsoLen_stop(struct seq_file *seq, void *v) ++{ ++ /* Nothing to do */ ++} ++ ++static int seq_TsoLen_show(struct seq_file *seq, void *v) ++{ ++ int i = *(loff_t *) v; ++ ++ seq_printf(seq, "%d~%d: %d\n", i*5000, (i+1)*5000, tso_cnt[i]); ++ ++ return 0; ++} ++ ++static const struct seq_operations seq_tso_txd_num_ops = { ++ .start = seq_TsoTxdNum_start, ++ .next = seq_TsoTxdNum_next, ++ .stop = seq_TsoTxdNum_stop, ++ .show = seq_TsoTxdNum_show ++}; ++ ++static int tso_txd_num_open(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &seq_tso_txd_num_ops); ++} ++ ++static struct file_operations tso_txd_num_fops = { ++ .owner = THIS_MODULE, ++ .open = tso_txd_num_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = NumOfTxdWrite, ++ .release = seq_release ++}; ++ ++static const struct seq_operations seq_tso_len_ops = { ++ .start = seq_TsoLen_start, ++ .next = seq_TsoLen_next, ++ .stop = seq_TsoLen_stop, ++ .show = seq_TsoLen_show ++}; ++ ++static int tso_len_open(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &seq_tso_len_ops); ++} ++ ++static struct file_operations tso_len_fops = { ++ .owner = THIS_MODULE, ++ .open = tso_len_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = TsoLenWrite, ++ .release = seq_release ++}; ++#endif ++ ++#if defined(CONFIG_RAETH_LRO) ++static int LroLenUpdate(struct net_lro_desc *lro_desc) ++{ ++ int len_idx; ++ ++ if(lro_desc->ip_tot_len > 65000) { ++ len_idx = 13; ++ }else if(lro_desc->ip_tot_len > 60000) { ++ len_idx = 12; ++ }else if(lro_desc->ip_tot_len > 55000) { ++ len_idx = 11; ++ }else if(lro_desc->ip_tot_len > 50000) { ++ len_idx = 10; ++ }else if(lro_desc->ip_tot_len > 45000) { ++ len_idx = 9; ++ }else if(lro_desc->ip_tot_len > 40000) { ++ len_idx = 8; ++ }else if(lro_desc->ip_tot_len > 35000) { ++ len_idx = 7; ++ }else if(lro_desc->ip_tot_len > 30000) { ++ len_idx = 6; ++ }else if(lro_desc->ip_tot_len > 25000) { ++ len_idx = 5; ++ }else if(lro_desc->ip_tot_len > 20000) { ++ len_idx = 4; ++ }else if(lro_desc->ip_tot_len > 15000) { ++ len_idx = 3; ++ }else if(lro_desc->ip_tot_len > 10000) { ++ len_idx = 2; ++ }else if(lro_desc->ip_tot_len > 5000) { ++ len_idx = 1; ++ }else { ++ len_idx = 0; ++ } ++ ++ return len_idx; ++} ++int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed) ++{ ++ struct net_lro_desc *tmp; ++ int len_idx; ++ int i, j; ++ ++ if (all_flushed) { ++ for (i=0; i< MAX_DESC; i++) { ++ tmp = & lro_mgr->lro_arr[i]; ++ if (tmp->pkt_aggr_cnt !=0) { ++ for(j=0; j<=MAX_AGGR; j++) { ++ if(tmp->pkt_aggr_cnt == j) { ++ lro_flush_cnt[j]++; ++ } ++ } ++ len_idx = LroLenUpdate(tmp); ++ lro_len_cnt1[len_idx]++; ++ tot_called1++; ++ } ++ aggregated[i] = 0; ++ } ++ } else { ++ if (lro_flushed != lro_mgr->stats.flushed) { ++ if (lro_aggregated != lro_mgr->stats.aggregated) { ++ for (i=0; ilro_arr[i]; ++ if ((aggregated[i]!= tmp->pkt_aggr_cnt) ++ && (tmp->pkt_aggr_cnt == 0)) { ++ aggregated[i] ++; ++ for (j=0; j<=MAX_AGGR; j++) { ++ if (aggregated[i] == j) { ++ lro_stats_cnt[j] ++; ++ } ++ } ++ aggregated[i] = 0; ++ //len_idx = LroLenUpdate(tmp); ++ //lro_len_cnt2[len_idx]++; ++ tot_called2++; ++ } ++ } ++ } else { ++ for (i=0; ilro_arr[i]; ++ if ((aggregated[i] != 0) && (tmp->pkt_aggr_cnt==0)) { ++ for (j=0; j<=MAX_AGGR; j++) { ++ if (aggregated[i] == j) { ++ lro_stats_cnt[j] ++; ++ } ++ } ++ aggregated[i] = 0; ++ //len_idx = LroLenUpdate(tmp); ++ //lro_len_cnt2[len_idx]++; ++ force_flush ++; ++ tot_called2++; ++ } ++ } ++ } ++ } else { ++ if (lro_aggregated != lro_mgr->stats.aggregated) { ++ for (i=0; ilro_arr[i]; ++ if (tmp->active) { ++ if (aggregated[i] != tmp->pkt_aggr_cnt) ++ aggregated[i] = tmp->pkt_aggr_cnt; ++ } else ++ aggregated[i] = 0; ++ } ++ } ++ } ++ ++ } ++ ++ lro_aggregated = lro_mgr->stats.aggregated; ++ lro_flushed = lro_mgr->stats.flushed; ++ lro_nodesc = lro_mgr->stats.no_desc; ++ ++ return 0; ++ ++} ++ ++ ++ssize_t LroStatsWrite(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ memset(lro_stats_cnt, 0, sizeof(lro_stats_cnt)); ++ memset(lro_flush_cnt, 0, sizeof(lro_flush_cnt)); ++ memset(lro_len_cnt1, 0, sizeof(lro_len_cnt1)); ++ //memset(lro_len_cnt2, 0, sizeof(lro_len_cnt2)); ++ memset(aggregated, 0, sizeof(aggregated)); ++ lro_aggregated = 0; ++ lro_flushed = 0; ++ lro_nodesc = 0; ++ force_flush = 0; ++ tot_called1 = 0; ++ tot_called2 = 0; ++ printk("clear lro cnt table\n"); ++ ++ return count; ++} ++ ++int LroStatsRead(struct seq_file *seq, void *v) ++{ ++ int i; ++ int tot_cnt=0; ++ int tot_aggr=0; ++ int ave_aggr=0; ++ ++ seq_printf(seq, "LRO statistic dump:\n"); ++ seq_printf(seq, "Cnt: Kernel | Driver\n"); ++ for(i=0; i<=MAX_AGGR; i++) { ++ tot_cnt = tot_cnt + lro_stats_cnt[i] + lro_flush_cnt[i]; ++ seq_printf(seq, " %d : %d %d\n", i, lro_stats_cnt[i], lro_flush_cnt[i]); ++ tot_aggr = tot_aggr + i * (lro_stats_cnt[i] + lro_flush_cnt[i]); ++ } ++ ave_aggr = lro_aggregated/lro_flushed; ++ seq_printf(seq, "Total aggregated pkt: %d\n", lro_aggregated); ++ seq_printf(seq, "Flushed pkt: %d %d\n", lro_flushed, force_flush); ++ seq_printf(seq, "Average flush cnt: %d\n", ave_aggr); ++ seq_printf(seq, "No descriptor pkt: %d\n\n\n", lro_nodesc); ++ ++ seq_printf(seq, "Driver flush pkt len:\n"); ++ seq_printf(seq, " Length | Count\n"); ++ for(i=0; i<15; i++) { ++ seq_printf(seq, "%d~%d: %d\n", i*5000, (i+1)*5000, lro_len_cnt1[i]); ++ } ++ seq_printf(seq, "Kernel flush: %d; Driver flush: %d\n", tot_called2, tot_called1); ++ return 0; ++} ++ ++static int lro_stats_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, LroStatsRead, NULL); ++} ++ ++static struct file_operations lro_stats_fops = { ++ .owner = THIS_MODULE, ++ .open = lro_stats_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = LroStatsWrite, ++ .release = single_release ++}; ++#endif ++ ++int getnext(const char *src, int separator, char *dest) ++{ ++ char *c; ++ int len; ++ ++ if ( (src == NULL) || (dest == NULL) ) { ++ return -1; ++ } ++ ++ c = strchr(src, separator); ++ if (c == NULL) { ++ strcpy(dest, src); ++ return -1; ++ } ++ len = c - src; ++ strncpy(dest, src, len); ++ dest[len] = '\0'; ++ return len + 1; ++} ++ ++int str_to_ip(unsigned int *ip, const char *str) ++{ ++ int len; ++ const char *ptr = str; ++ char buf[128]; ++ unsigned char c[4]; ++ int i; ++ ++ for (i = 0; i < 3; ++i) { ++ if ((len = getnext(ptr, '.', buf)) == -1) { ++ return 1; /* parse error */ ++ } ++ c[i] = simple_strtoul(buf, NULL, 10); ++ ptr += len; ++ } ++ c[3] = simple_strtoul(ptr, NULL, 0); ++ *ip = (c[0]<<24) + (c[1]<<16) + (c[2]<<8) + c[3]; ++ return 0; ++} ++ ++#if defined(CONFIG_RAETH_HW_LRO) ++static int HwLroLenUpdate(unsigned int agg_size) ++{ ++ int len_idx; ++ ++ if(agg_size > 65000) { ++ len_idx = 13; ++ }else if(agg_size > 60000) { ++ len_idx = 12; ++ }else if(agg_size > 55000) { ++ len_idx = 11; ++ }else if(agg_size > 50000) { ++ len_idx = 10; ++ }else if(agg_size > 45000) { ++ len_idx = 9; ++ }else if(agg_size > 40000) { ++ len_idx = 8; ++ }else if(agg_size > 35000) { ++ len_idx = 7; ++ }else if(agg_size > 30000) { ++ len_idx = 6; ++ }else if(agg_size > 25000) { ++ len_idx = 5; ++ }else if(agg_size > 20000) { ++ len_idx = 4; ++ }else if(agg_size > 15000) { ++ len_idx = 3; ++ }else if(agg_size > 10000) { ++ len_idx = 2; ++ }else if(agg_size > 5000) { ++ len_idx = 1; ++ }else { ++ len_idx = 0; ++ } ++ ++ return len_idx; ++} ++ ++int HwLroStatsUpdate(unsigned int ring_num, unsigned int agg_cnt, unsigned int agg_size) ++{ ++ if( (ring_num > 0) && (ring_num < 4) ) ++ { ++ hw_lro_agg_size_cnt[ring_num-1][HwLroLenUpdate(agg_size)]++; ++ hw_lro_agg_num_cnt[ring_num-1][agg_cnt]++; ++ hw_lro_tot_flush_cnt[ring_num-1]++; ++ hw_lro_tot_agg_cnt[ring_num-1] += agg_cnt; ++ } ++ ++ return 0; ++} ++ ++#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG) ++int HwLroFlushStatsUpdate(unsigned int ring_num, unsigned int flush_reason) ++{ ++ if( (ring_num > 0) && (ring_num < 4) ) ++ { ++#if 1 ++ if ( (flush_reason & 0x7) == HW_LRO_AGG_FLUSH ) ++ hw_lro_agg_flush_cnt[ring_num-1]++; ++ else if ( (flush_reason & 0x7) == HW_LRO_AGE_FLUSH ) ++ hw_lro_age_flush_cnt[ring_num-1]++; ++ else if ( (flush_reason & 0x7) == HW_LRO_NOT_IN_SEQ_FLUSH ) ++ hw_lro_seq_flush_cnt[ring_num-1]++; ++ else if ( (flush_reason & 0x7) == HW_LRO_TIMESTAMP_FLUSH ) ++ hw_lro_timestamp_flush_cnt[ring_num-1]++; ++ else if ( (flush_reason & 0x7) == HW_LRO_NON_RULE_FLUSH ) ++ hw_lro_norule_flush_cnt[ring_num-1]++; ++#else ++ if ( flush_reason & BIT(4) ) ++ hw_lro_agg_flush_cnt[ring_num-1]++; ++ else if ( flush_reason & BIT(3) ) ++ hw_lro_age_flush_cnt[ring_num-1]++; ++ else if ( flush_reason & BIT(2) ) ++ hw_lro_seq_flush_cnt[ring_num-1]++; ++ else if ( flush_reason & BIT(1) ) ++ hw_lro_timestamp_flush_cnt[ring_num-1]++; ++ else if ( flush_reason & BIT(0) ) ++ hw_lro_norule_flush_cnt[ring_num-1]++; ++#endif ++ } ++ ++ return 0; ++} ++#endif /* CONFIG_RAETH_HW_LRO_REASON_DBG */ ++ ++ssize_t HwLroStatsWrite(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ memset(hw_lro_agg_num_cnt, 0, sizeof(hw_lro_agg_num_cnt)); ++ memset(hw_lro_agg_size_cnt, 0, sizeof(hw_lro_agg_size_cnt)); ++ memset(hw_lro_tot_agg_cnt, 0, sizeof(hw_lro_tot_agg_cnt)); ++ memset(hw_lro_tot_flush_cnt, 0, sizeof(hw_lro_tot_flush_cnt)); ++#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG) ++ memset(hw_lro_agg_flush_cnt, 0, sizeof(hw_lro_agg_flush_cnt)); ++ memset(hw_lro_age_flush_cnt, 0, sizeof(hw_lro_age_flush_cnt)); ++ memset(hw_lro_seq_flush_cnt, 0, sizeof(hw_lro_seq_flush_cnt)); ++ memset(hw_lro_timestamp_flush_cnt, 0, sizeof(hw_lro_timestamp_flush_cnt)); ++ memset(hw_lro_norule_flush_cnt, 0, sizeof(hw_lro_norule_flush_cnt)); ++#endif /* CONFIG_RAETH_HW_LRO_REASON_DBG */ ++ ++ printk("clear hw lro cnt table\n"); ++ ++ return count; ++} ++ ++int HwLroStatsRead(struct seq_file *seq, void *v) ++{ ++ int i; ++ ++ seq_printf(seq, "HW LRO statistic dump:\n"); ++ ++ /* Agg number count */ ++ seq_printf(seq, "Cnt: RING1 | RING2 | RING3 | Total\n"); ++ for(i=0; i<=MAX_HW_LRO_AGGR; i++) { ++ seq_printf(seq, " %d : %d %d %d %d\n", ++ i, hw_lro_agg_num_cnt[0][i], hw_lro_agg_num_cnt[1][i], hw_lro_agg_num_cnt[2][i], ++ hw_lro_agg_num_cnt[0][i]+hw_lro_agg_num_cnt[1][i]+hw_lro_agg_num_cnt[2][i]); ++ } ++ ++ /* Total agg count */ ++ seq_printf(seq, "Total agg: RING1 | RING2 | RING3 | Total\n"); ++ seq_printf(seq, " %d %d %d %d\n", ++ hw_lro_tot_agg_cnt[0], hw_lro_tot_agg_cnt[1], hw_lro_tot_agg_cnt[2], ++ hw_lro_tot_agg_cnt[0]+hw_lro_tot_agg_cnt[1]+hw_lro_tot_agg_cnt[2]); ++ ++ /* Total flush count */ ++ seq_printf(seq, "Total flush: RING1 | RING2 | RING3 | Total\n"); ++ seq_printf(seq, " %d %d %d %d\n", ++ hw_lro_tot_flush_cnt[0], hw_lro_tot_flush_cnt[1], hw_lro_tot_flush_cnt[2], ++ hw_lro_tot_flush_cnt[0]+hw_lro_tot_flush_cnt[1]+hw_lro_tot_flush_cnt[2]); ++ ++ /* Avg agg count */ ++ seq_printf(seq, "Avg agg: RING1 | RING2 | RING3 | Total\n"); ++ seq_printf(seq, " %d %d %d %d\n", ++ (hw_lro_tot_flush_cnt[0]) ? hw_lro_tot_agg_cnt[0]/hw_lro_tot_flush_cnt[0] : 0, ++ (hw_lro_tot_flush_cnt[1]) ? hw_lro_tot_agg_cnt[1]/hw_lro_tot_flush_cnt[1] : 0, ++ (hw_lro_tot_flush_cnt[2]) ? hw_lro_tot_agg_cnt[2]/hw_lro_tot_flush_cnt[2] : 0, ++ (hw_lro_tot_flush_cnt[0]+hw_lro_tot_flush_cnt[1]+hw_lro_tot_flush_cnt[2]) ? \ ++ ((hw_lro_tot_agg_cnt[0]+hw_lro_tot_agg_cnt[1]+hw_lro_tot_agg_cnt[2])/(hw_lro_tot_flush_cnt[0]+hw_lro_tot_flush_cnt[1]+hw_lro_tot_flush_cnt[2])) : 0 ++ ); ++ ++ /* Statistics of aggregation size counts */ ++ seq_printf(seq, "HW LRO flush pkt len:\n"); ++ seq_printf(seq, " Length | RING1 | RING2 | RING3 | Total\n"); ++ for(i=0; i<15; i++) { ++ seq_printf(seq, "%d~%d: %d %d %d %d\n", i*5000, (i+1)*5000, ++ hw_lro_agg_size_cnt[0][i], hw_lro_agg_size_cnt[1][i], hw_lro_agg_size_cnt[2][i], ++ hw_lro_agg_size_cnt[0][i]+hw_lro_agg_size_cnt[1][i]+hw_lro_agg_size_cnt[2][i]); ++ } ++#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG) ++ seq_printf(seq, "Flush reason: RING1 | RING2 | RING3 | Total\n"); ++ seq_printf(seq, "AGG timeout: %d %d %d %d\n", ++ hw_lro_agg_flush_cnt[0], hw_lro_agg_flush_cnt[1], hw_lro_agg_flush_cnt[2], ++ (hw_lro_agg_flush_cnt[0]+hw_lro_agg_flush_cnt[1]+hw_lro_agg_flush_cnt[2]) ++ ); ++ seq_printf(seq, "AGE timeout: %d %d %d %d\n", ++ hw_lro_age_flush_cnt[0], hw_lro_age_flush_cnt[1], hw_lro_age_flush_cnt[2], ++ (hw_lro_age_flush_cnt[0]+hw_lro_age_flush_cnt[1]+hw_lro_age_flush_cnt[2]) ++ ); ++ seq_printf(seq, "Not in-sequence: %d %d %d %d\n", ++ hw_lro_seq_flush_cnt[0], hw_lro_seq_flush_cnt[1], hw_lro_seq_flush_cnt[2], ++ (hw_lro_seq_flush_cnt[0]+hw_lro_seq_flush_cnt[1]+hw_lro_seq_flush_cnt[2]) ++ ); ++ seq_printf(seq, "Timestamp: %d %d %d %d\n", ++ hw_lro_timestamp_flush_cnt[0], hw_lro_timestamp_flush_cnt[1], hw_lro_timestamp_flush_cnt[2], ++ (hw_lro_timestamp_flush_cnt[0]+hw_lro_timestamp_flush_cnt[1]+hw_lro_timestamp_flush_cnt[2]) ++ ); ++ seq_printf(seq, "No LRO rule: %d %d %d %d\n", ++ hw_lro_norule_flush_cnt[0], hw_lro_norule_flush_cnt[1], hw_lro_norule_flush_cnt[2], ++ (hw_lro_norule_flush_cnt[0]+hw_lro_norule_flush_cnt[1]+hw_lro_norule_flush_cnt[2]) ++ ); ++#endif /* CONFIG_RAETH_HW_LRO_REASON_DBG */ ++ ++ return 0; ++} ++ ++static int hw_lro_stats_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, HwLroStatsRead, NULL); ++} ++ ++static struct file_operations hw_lro_stats_fops = { ++ .owner = THIS_MODULE, ++ .open = hw_lro_stats_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = HwLroStatsWrite, ++ .release = single_release ++}; ++ ++int hwlro_agg_cnt_ctrl(int par1, int par2) ++{ ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, par2); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, par2); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, par2); ++ return 0; ++} ++ ++int hwlro_agg_time_ctrl(int par1, int par2) ++{ ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, par2); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, par2); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, par2); ++ return 0; ++} ++ ++int hwlro_age_time_ctrl(int par1, int par2) ++{ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, par2); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, par2); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, par2); ++ return 0; ++} ++ ++int hwlro_pkt_int_alpha_ctrl(int par1, int par2) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ ++ ei_local->hw_lro_alpha = par2; ++ printk("[hwlro_pkt_int_alpha_ctrl]ei_local->hw_lro_alpha = %d\n", ei_local->hw_lro_alpha); ++ ++ return 0; ++} ++ ++int hwlro_threshold_ctrl(int par1, int par2) ++{ ++ /* bandwidth threshold setting */ ++ SET_PDMA_LRO_BW_THRESHOLD(par2); ++ return 0; ++} ++ ++int hwlro_fix_setting_switch_ctrl(int par1, int par2) ++{ ++#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG) ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ ++ ei_local->hw_lro_fix_setting = par2; ++ printk("[hwlro_pkt_int_alpha_ctrl]ei_local->hw_lro_fix_setting = %d\n", ei_local->hw_lro_fix_setting); ++#endif /* CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG */ ++ ++ return 0; ++} ++ ++ssize_t HwLroAutoTlbWrite(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ char buf[32]; ++ char *pBuf; ++ int len = count; ++ int x = 0,y = 0; ++ char *pToken = NULL; ++ char *pDelimiter = " \t"; ++ ++ printk("[HwLroAutoTlbWrite]write parameter len = %d\n\r", (int)len); ++ if(len >= sizeof(buf)){ ++ printk("input handling fail!\n"); ++ len = sizeof(buf) - 1; ++ return -1; ++ } ++ ++ if(copy_from_user(buf, buffer, len)){ ++ return -EFAULT; ++ } ++ buf[len] = '\0'; ++ printk("[HwLroAutoTlbWrite]write parameter data = %s\n\r", buf); ++ ++ pBuf = buf; ++ pToken = strsep(&pBuf, pDelimiter); ++ x = NULL != pToken ? simple_strtol(pToken, NULL, 16) : 0; ++ ++ pToken = strsep(&pBuf, "\t\n "); ++ if(pToken != NULL){ ++ y = NULL != pToken ? simple_strtol(pToken, NULL, 16) : 0; ++ printk("y = 0x%08x \n\r", y); ++ } ++ ++ if ( (sizeof(hw_lro_dbg_func)/sizeof(hw_lro_dbg_func[0]) > x) && NULL != hw_lro_dbg_func[x]) ++ { ++ (*hw_lro_dbg_func[x])(x, y); ++ } ++ ++ return count; ++} ++ ++void HwLroAutoTlbDump(struct seq_file *seq, unsigned int index) ++{ ++ int i; ++ struct PDMA_LRO_AUTO_TLB_INFO pdma_lro_auto_tlb; ++ unsigned int tlb_info[9]; ++ unsigned int dw_len, cnt, priority; ++ unsigned int entry; ++ ++ if( index > 4 ) ++ index = index - 1; ++ entry = (index * 9) + 1; ++ ++ /* read valid entries of the auto-learn table */ ++ sysRegWrite( PDMA_FE_ALT_CF8, entry ); ++ ++ //seq_printf(seq, "\nEntry = %d\n", entry); ++ for(i=0; i<9; i++){ ++ tlb_info[i] = sysRegRead(PDMA_FE_ALT_SEQ_CFC); ++ //seq_printf(seq, "tlb_info[%d] = 0x%x\n", i, tlb_info[i]); ++ } ++ memcpy(&pdma_lro_auto_tlb, tlb_info, sizeof(struct PDMA_LRO_AUTO_TLB_INFO)); ++ ++ dw_len = pdma_lro_auto_tlb.auto_tlb_info7.DW_LEN; ++ cnt = pdma_lro_auto_tlb.auto_tlb_info6.CNT; ++ ++ if ( sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_ALT_SCORE_MODE ) /* packet count */ ++ priority = cnt; ++ else /* byte count */ ++ priority = dw_len; ++ ++ /* dump valid entries of the auto-learn table */ ++ if( index >= 4 ) ++ seq_printf(seq, "\n===== TABLE Entry: %d (Act) =====\n", index); ++ else ++ seq_printf(seq, "\n===== TABLE Entry: %d (LRU) =====\n", index); ++ if( pdma_lro_auto_tlb.auto_tlb_info8.IPV4 ){ ++ seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv4)\n", ++ pdma_lro_auto_tlb.auto_tlb_info4.SIP3, ++ pdma_lro_auto_tlb.auto_tlb_info3.SIP2, ++ pdma_lro_auto_tlb.auto_tlb_info2.SIP1, ++ pdma_lro_auto_tlb.auto_tlb_info1.SIP0); ++ } ++ else{ ++ seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv6)\n", ++ pdma_lro_auto_tlb.auto_tlb_info4.SIP3, ++ pdma_lro_auto_tlb.auto_tlb_info3.SIP2, ++ pdma_lro_auto_tlb.auto_tlb_info2.SIP1, ++ pdma_lro_auto_tlb.auto_tlb_info1.SIP0); ++ } ++ seq_printf(seq, "DIP_ID = %d\n", pdma_lro_auto_tlb.auto_tlb_info8.DIP_ID); ++ seq_printf(seq, "TCP SPORT = %d | TCP DPORT = %d\n", ++ pdma_lro_auto_tlb.auto_tlb_info0.STP, ++ pdma_lro_auto_tlb.auto_tlb_info0.DTP); ++ seq_printf(seq, "VLAN1 = %d | VLAN2 = %d | VLAN3 = %d | VLAN4 =%d \n", ++ pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0, ++ (pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 << 12), ++ (pdma_lro_auto_tlb.auto_tlb_info5.VLAN_VID0 << 24), ++ pdma_lro_auto_tlb.auto_tlb_info6.VLAN_VID1); ++ seq_printf(seq, "TPUT = %d | FREQ = %d\n", dw_len, cnt); ++ seq_printf(seq, "PRIORITY = %d\n", priority); ++} ++ ++int HwLroAutoTlbRead(struct seq_file *seq, void *v) ++{ ++ int i; ++ unsigned int regVal; ++ unsigned int regOp1, regOp2, regOp3, regOp4; ++ unsigned int agg_cnt, agg_time, age_time; ++ ++ /* Read valid entries of the auto-learn table */ ++ sysRegWrite(PDMA_FE_ALT_CF8, 0); ++ regVal = sysRegRead(PDMA_FE_ALT_SEQ_CFC); ++ ++ seq_printf(seq, "HW LRO Auto-learn Table: (PDMA_LRO_ALT_CFC_RSEQ_DBG=0x%x)\n", regVal); ++ ++ for(i = 7; i >= 0; i--) ++ { ++ if( regVal & (1 << i) ) ++ HwLroAutoTlbDump(seq, i); ++ } ++ ++ /* Read the agg_time/age_time/agg_cnt of LRO rings */ ++ seq_printf(seq, "\nHW LRO Ring Settings\n"); ++ for(i = 1; i <= 3; i++) ++ { ++ regOp1 = sysRegRead( LRO_RX_RING0_CTRL_DW1 + (i * 0x40) ); ++ regOp2 = sysRegRead( LRO_RX_RING0_CTRL_DW2 + (i * 0x40) ); ++ regOp3 = sysRegRead( LRO_RX_RING0_CTRL_DW3 + (i * 0x40) ); ++ regOp4 = sysRegRead( ADMA_LRO_CTRL_DW2 ); ++ agg_cnt = ((regOp3 & 0x03) << PDMA_LRO_AGG_CNT_H_OFFSET) | ((regOp2 >> PDMA_LRO_RING_AGG_CNT1_OFFSET) & 0x3f); ++ agg_time = (regOp2 >> PDMA_LRO_RING_AGG_OFFSET) & 0xffff; ++ age_time = ((regOp2 & 0x03f) << PDMA_LRO_AGE_H_OFFSET) | ((regOp1 >> PDMA_LRO_RING_AGE1_OFFSET) & 0x3ff); ++ seq_printf(seq, "Ring[%d]: MAX_AGG_CNT=%d, AGG_TIME=%d, AGE_TIME=%d, Threshold=%d\n", ++ i, agg_cnt, agg_time, age_time, regOp4); ++ } ++ ++ return 0; ++} ++ ++static int hw_lro_auto_tlb_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, HwLroAutoTlbRead, NULL); ++} ++ ++static struct file_operations hw_lro_auto_tlb_fops = { ++ .owner = THIS_MODULE, ++ .open = hw_lro_auto_tlb_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .write = HwLroAutoTlbWrite, ++ .release = single_release ++}; ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if defined (CONFIG_MIPS) ++int CP0RegRead(struct seq_file *seq, void *v) ++{ ++ seq_printf(seq, "CP0 Register dump --\n"); ++ seq_printf(seq, "CP0_INDEX\t: 0x%08x\n", read_32bit_cp0_register(CP0_INDEX)); ++ seq_printf(seq, "CP0_RANDOM\t: 0x%08x\n", read_32bit_cp0_register(CP0_RANDOM)); ++ seq_printf(seq, "CP0_ENTRYLO0\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYLO0)); ++ seq_printf(seq, "CP0_ENTRYLO1\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYLO1)); ++ seq_printf(seq, "CP0_CONF\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONF)); ++ seq_printf(seq, "CP0_CONTEXT\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONTEXT)); ++ seq_printf(seq, "CP0_PAGEMASK\t: 0x%08x\n", read_32bit_cp0_register(CP0_PAGEMASK)); ++ seq_printf(seq, "CP0_WIRED\t: 0x%08x\n", read_32bit_cp0_register(CP0_WIRED)); ++ seq_printf(seq, "CP0_INFO\t: 0x%08x\n", read_32bit_cp0_register(CP0_INFO)); ++ seq_printf(seq, "CP0_BADVADDR\t: 0x%08x\n", read_32bit_cp0_register(CP0_BADVADDR)); ++ seq_printf(seq, "CP0_COUNT\t: 0x%08x\n", read_32bit_cp0_register(CP0_COUNT)); ++ seq_printf(seq, "CP0_ENTRYHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_ENTRYHI)); ++ seq_printf(seq, "CP0_COMPARE\t: 0x%08x\n", read_32bit_cp0_register(CP0_COMPARE)); ++ seq_printf(seq, "CP0_STATUS\t: 0x%08x\n", read_32bit_cp0_register(CP0_STATUS)); ++ seq_printf(seq, "CP0_CAUSE\t: 0x%08x\n", read_32bit_cp0_register(CP0_CAUSE)); ++ seq_printf(seq, "CP0_EPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_EPC)); ++ seq_printf(seq, "CP0_PRID\t: 0x%08x\n", read_32bit_cp0_register(CP0_PRID)); ++ seq_printf(seq, "CP0_CONFIG\t: 0x%08x\n", read_32bit_cp0_register(CP0_CONFIG)); ++ seq_printf(seq, "CP0_LLADDR\t: 0x%08x\n", read_32bit_cp0_register(CP0_LLADDR)); ++ seq_printf(seq, "CP0_WATCHLO\t: 0x%08x\n", read_32bit_cp0_register(CP0_WATCHLO)); ++ seq_printf(seq, "CP0_WATCHHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_WATCHHI)); ++ seq_printf(seq, "CP0_XCONTEXT\t: 0x%08x\n", read_32bit_cp0_register(CP0_XCONTEXT)); ++ seq_printf(seq, "CP0_FRAMEMASK\t: 0x%08x\n", read_32bit_cp0_register(CP0_FRAMEMASK)); ++ seq_printf(seq, "CP0_DIAGNOSTIC\t: 0x%08x\n", read_32bit_cp0_register(CP0_DIAGNOSTIC)); ++ seq_printf(seq, "CP0_DEBUG\t: 0x%08x\n", read_32bit_cp0_register(CP0_DEBUG)); ++ seq_printf(seq, "CP0_DEPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_DEPC)); ++ seq_printf(seq, "CP0_PERFORMANCE\t: 0x%08x\n", read_32bit_cp0_register(CP0_PERFORMANCE)); ++ seq_printf(seq, "CP0_ECC\t: 0x%08x\n", read_32bit_cp0_register(CP0_ECC)); ++ seq_printf(seq, "CP0_CACHEERR\t: 0x%08x\n", read_32bit_cp0_register(CP0_CACHEERR)); ++ seq_printf(seq, "CP0_TAGLO\t: 0x%08x\n", read_32bit_cp0_register(CP0_TAGLO)); ++ seq_printf(seq, "CP0_TAGHI\t: 0x%08x\n", read_32bit_cp0_register(CP0_TAGHI)); ++ seq_printf(seq, "CP0_ERROREPC\t: 0x%08x\n", read_32bit_cp0_register(CP0_ERROREPC)); ++ seq_printf(seq, "CP0_DESAVE\t: 0x%08x\n\n", read_32bit_cp0_register(CP0_DESAVE)); ++ ++ return 0; ++} ++ ++static int cp0_reg_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, CP0RegRead, NULL); ++} ++ ++static const struct file_operations cp0_reg_fops = { ++ .owner = THIS_MODULE, ++ .open = cp0_reg_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++#endif ++ ++#if defined(CONFIG_RAETH_QOS) ++static struct proc_dir_entry *procRaQOS, *procRaFeIntr, *procRaEswIntr; ++extern uint32_t num_of_rxdone_intr; ++extern uint32_t num_of_esw_intr; ++ ++int RaQOSRegRead(struct seq_file *seq, void *v) ++{ ++ dump_qos(seq); ++ return 0; ++} ++ ++static int raeth_qos_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, RaQOSRegRead, NULL); ++} ++ ++static const struct file_operations raeth_qos_fops = { ++ .owner = THIS_MODULE, ++ .open = raeth_qos_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++#endif ++ ++static struct proc_dir_entry *procEswCnt; ++ ++int EswCntRead(struct seq_file *seq, void *v) ++{ ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE) || defined (CONFIG_ARCH_MT7623) ++ unsigned int pkt_cnt = 0; ++ int i = 0; ++#endif ++ seq_printf(seq, "\n <> \n"); ++ seq_printf(seq, " | \n"); ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ seq_printf(seq, "+-----------------------------------------------+\n"); ++ seq_printf(seq, "| <> |\n"); ++ seq_printf(seq, "+-----------------------------------------------+\n"); ++#else ++ seq_printf(seq, "+-----------------------------------------------+\n"); ++ seq_printf(seq, "| <> |\n"); ++ seq_printf(seq, "+-----------------------------------------------+\n"); ++ seq_printf(seq, " | \n"); ++ seq_printf(seq, "+-----------------------------------------------+\n"); ++ seq_printf(seq, "| <> |\n"); ++#if defined (CONFIG_RALINK_MT7620) ++ seq_printf(seq, "| GDMA1_TX_GPCNT : %010u (Tx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1304)); ++ seq_printf(seq, "| GDMA1_RX_GPCNT : %010u (Rx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1324)); ++ seq_printf(seq, "| |\n"); ++ seq_printf(seq, "| GDMA1_TX_SKIPCNT: %010u (skip) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1308)); ++ seq_printf(seq, "| GDMA1_TX_COLCNT : %010u (collision) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x130c)); ++ seq_printf(seq, "| GDMA1_RX_OERCNT : %010u (overflow) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1328)); ++ seq_printf(seq, "| GDMA1_RX_FERCNT : %010u (FCS error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x132c)); ++ seq_printf(seq, "| GDMA1_RX_SERCNT : %010u (too short) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1330)); ++ seq_printf(seq, "| GDMA1_RX_LERCNT : %010u (too long) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1334)); ++ seq_printf(seq, "| GDMA1_RX_CERCNT : %010u (l3/l4 checksum) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1338)); ++ seq_printf(seq, "| GDMA1_RX_FCCNT : %010u (flow control) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x133c)); ++ ++ seq_printf(seq, "| |\n"); ++ seq_printf(seq, "| GDMA2_TX_GPCNT : %010u (Tx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1344)); ++ seq_printf(seq, "| GDMA2_RX_GPCNT : %010u (Rx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1364)); ++ seq_printf(seq, "| |\n"); ++ seq_printf(seq, "| GDMA2_TX_SKIPCNT: %010u (skip) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1348)); ++ seq_printf(seq, "| GDMA2_TX_COLCNT : %010u (collision) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x134c)); ++ seq_printf(seq, "| GDMA2_RX_OERCNT : %010u (overflow) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1368)); ++ seq_printf(seq, "| GDMA2_RX_FERCNT : %010u (FCS error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x136c)); ++ seq_printf(seq, "| GDMA2_RX_SERCNT : %010u (too short) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1370)); ++ seq_printf(seq, "| GDMA2_RX_LERCNT : %010u (too long) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1374)); ++ seq_printf(seq, "| GDMA2_RX_CERCNT : %010u (l3/l4 checksum) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x1378)); ++ seq_printf(seq, "| GDMA2_RX_FCCNT : %010u (flow control) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x137c)); ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ seq_printf(seq, "| GDMA1_RX_GBCNT : %010u (Rx Good Bytes) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2400)); ++ seq_printf(seq, "| GDMA1_RX_GPCNT : %010u (Rx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2408)); ++ seq_printf(seq, "| GDMA1_RX_OERCNT : %010u (overflow error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2410)); ++ seq_printf(seq, "| GDMA1_RX_FERCNT : %010u (FCS error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2414)); ++ seq_printf(seq, "| GDMA1_RX_SERCNT : %010u (too short) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2418)); ++ seq_printf(seq, "| GDMA1_RX_LERCNT : %010u (too long) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x241C)); ++ seq_printf(seq, "| GDMA1_RX_CERCNT : %010u (checksum error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2420)); ++ seq_printf(seq, "| GDMA1_RX_FCCNT : %010u (flow control) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2424)); ++ seq_printf(seq, "| GDMA1_TX_SKIPCNT: %010u (about count) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2428)); ++ seq_printf(seq, "| GDMA1_TX_COLCNT : %010u (collision count) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x242C)); ++ seq_printf(seq, "| GDMA1_TX_GBCNT : %010u (Tx Good Bytes) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2430)); ++ seq_printf(seq, "| GDMA1_TX_GPCNT : %010u (Tx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2438)); ++ seq_printf(seq, "| |\n"); ++ seq_printf(seq, "| GDMA2_RX_GBCNT : %010u (Rx Good Bytes) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2440)); ++ seq_printf(seq, "| GDMA2_RX_GPCNT : %010u (Rx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2448)); ++ seq_printf(seq, "| GDMA2_RX_OERCNT : %010u (overflow error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2450)); ++ seq_printf(seq, "| GDMA2_RX_FERCNT : %010u (FCS error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2454)); ++ seq_printf(seq, "| GDMA2_RX_SERCNT : %010u (too short) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2458)); ++ seq_printf(seq, "| GDMA2_RX_LERCNT : %010u (too long) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x245C)); ++ seq_printf(seq, "| GDMA2_RX_CERCNT : %010u (checksum error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2460)); ++ seq_printf(seq, "| GDMA2_RX_FCCNT : %010u (flow control) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2464)); ++ seq_printf(seq, "| GDMA2_TX_SKIPCNT: %010u (skip) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2468)); ++ seq_printf(seq, "| GDMA2_TX_COLCNT : %010u (collision) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x246C)); ++ seq_printf(seq, "| GDMA2_TX_GBCNT : %010u (Tx Good Bytes) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2470)); ++ seq_printf(seq, "| GDMA2_TX_GPCNT : %010u (Tx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x2478)); ++#else ++ seq_printf(seq, "| GDMA_TX_GPCNT1 : %010u (Tx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x704)); ++ seq_printf(seq, "| GDMA_RX_GPCNT1 : %010u (Rx Good Pkts) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x724)); ++ seq_printf(seq, "| |\n"); ++ seq_printf(seq, "| GDMA_TX_SKIPCNT1: %010u (skip) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x708)); ++ seq_printf(seq, "| GDMA_TX_COLCNT1 : %010u (collision) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x70c)); ++ seq_printf(seq, "| GDMA_RX_OERCNT1 : %010u (overflow) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x728)); ++ seq_printf(seq, "| GDMA_RX_FERCNT1 : %010u (FCS error) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x72c)); ++ seq_printf(seq, "| GDMA_RX_SERCNT1 : %010u (too short) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x730)); ++ seq_printf(seq, "| GDMA_RX_LERCNT1 : %010u (too long) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x734)); ++ seq_printf(seq, "| GDMA_RX_CERCNT1 : %010u (l3/l4 checksum) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x738)); ++ seq_printf(seq, "| GDMA_RX_FCCNT1 : %010u (flow control) |\n", sysRegRead(RALINK_FRAME_ENGINE_BASE+0x73c)); ++ ++#endif ++ seq_printf(seq, "+-----------------------------------------------+\n"); ++#endif ++ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) ++ ++ seq_printf(seq, " ^ \n"); ++ seq_printf(seq, " | Port6 Rx:%010u Good Pkt \n", ((p6_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4620)&0xFFFF))); ++ seq_printf(seq, " | Port6 Rx:%010u Bad Pkt \n", sysRegRead(RALINK_ETH_SW_BASE+0x4620)>>16); ++ seq_printf(seq, " | Port6 Tx:%010u Good Pkt \n", ((p6_tx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4610)&0xFFFF))); ++ seq_printf(seq, " | Port6 Tx:%010u Bad Pkt \n", sysRegRead(RALINK_ETH_SW_BASE+0x4610)>>16); ++#if defined (CONFIG_RALINK_MT7620) ++ ++ seq_printf(seq, " | Port7 Rx:%010u Good Pkt \n", ((p7_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4720)&0xFFFF))); ++ seq_printf(seq, " | Port7 Rx:%010u Bad Pkt \n", sysRegRead(RALINK_ETH_SW_BASE+0x4720)>>16); ++ seq_printf(seq, " | Port7 Tx:%010u Good Pkt \n", ((p7_tx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4710)&0xFFFF))); ++ seq_printf(seq, " | Port7 Tx:%010u Bad Pkt \n", sysRegRead(RALINK_ETH_SW_BASE+0x4710)>>16); ++#endif ++ seq_printf(seq, "+---------------------v-------------------------+\n"); ++ seq_printf(seq, "| P6 |\n"); ++ seq_printf(seq, "| <<10/100/1000 Embedded Switch>> |\n"); ++ seq_printf(seq, "| P0 P1 P2 P3 P4 P5 |\n"); ++ seq_printf(seq, "+-----------------------------------------------+\n"); ++ seq_printf(seq, " | | | | | | \n"); ++#elif defined (CONFIG_RALINK_RT3883) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ /* no built-in switch */ ++#else ++ seq_printf(seq, " ^ \n"); ++ seq_printf(seq, " | Port6 Rx:%08u Good Pkt \n", sysRegRead(RALINK_ETH_SW_BASE+0xE0)&0xFFFF); ++ seq_printf(seq, " | Port6 Tx:%08u Good Pkt \n", sysRegRead(RALINK_ETH_SW_BASE+0xE0)>>16); ++ seq_printf(seq, "+---------------------v-------------------------+\n"); ++ seq_printf(seq, "| P6 |\n"); ++ seq_printf(seq, "| <<10/100 Embedded Switch>> |\n"); ++ seq_printf(seq, "| P0 P1 P2 P3 P4 P5 |\n"); ++ seq_printf(seq, "+-----------------------------------------------+\n"); ++ seq_printf(seq, " | | | | | | \n"); ++#endif ++ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) ++ ++ seq_printf(seq, "Port0 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p0_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4020)&0xFFFF)), ((p0_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4010)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4020)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4010)>>16); ++ ++ seq_printf(seq, "Port1 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p1_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4120)&0xFFFF)), ((p1_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4110)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4120)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4110)>>16); ++ ++ seq_printf(seq, "Port2 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p2_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4220)&0xFFFF)), ((p2_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4210)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4220)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4210)>>16); ++ ++ seq_printf(seq, "Port3 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p3_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4320)&0xFFFF)), ((p3_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4310)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4320)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4310)>>16); ++ ++ seq_printf(seq, "Port4 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p4_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4420)&0xFFFF)), ((p4_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4410)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4420)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4410)>>16); ++ ++ seq_printf(seq, "Port5 Good RX=%010u Tx=%010u (Bad Rx=%010u Tx=%010u)\n", ((p5_rx_good_cnt << 16) | (sysRegRead(RALINK_ETH_SW_BASE+0x4520)&0xFFFF)), ((p5_tx_good_cnt << 16)| (sysRegRead(RALINK_ETH_SW_BASE+0x4510)&0xFFFF)), sysRegRead(RALINK_ETH_SW_BASE+0x4520)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x4510)>>16); ++ ++ seq_printf(seq, "Port0 KBytes RX=%010u Tx=%010u \n", ((p0_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4028) >> 10)), ((p0_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4018) >> 10))); ++ ++ seq_printf(seq, "Port1 KBytes RX=%010u Tx=%010u \n", ((p1_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4128) >> 10)), ((p1_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4118) >> 10))); ++ ++ seq_printf(seq, "Port2 KBytes RX=%010u Tx=%010u \n", ((p2_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4228) >> 10)), ((p2_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4218) >> 10))); ++ ++ seq_printf(seq, "Port3 KBytes RX=%010u Tx=%010u \n", ((p3_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4328) >> 10)), ((p3_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4318) >> 10))); ++ ++ seq_printf(seq, "Port4 KBytes RX=%010u Tx=%010u \n", ((p4_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4428) >> 10)), ((p4_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4418) >> 10))); ++ ++ seq_printf(seq, "Port5 KBytes RX=%010u Tx=%010u \n", ((p5_rx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4528) >> 10)), ((p5_tx_byte_cnt << 22) + (sysRegRead(RALINK_ETH_SW_BASE+0x4518) >> 10))); ++ ++#if defined (CONFIG_P5_RGMII_TO_MT7530_MODE) ++#define DUMP_EACH_PORT(base) \ ++ for(i=0; i < 7;i++) { \ ++ mii_mgr_read(31, (base) + (i*0x100), &pkt_cnt); \ ++ seq_printf(seq, "%8u ", pkt_cnt); \ ++ } \ ++ seq_printf(seq, "\n"); ++ seq_printf(seq, "========================================[MT7530] READ CLEAR========================\n"); ++ ++ seq_printf(seq, "===================== %8s %8s %8s %8s %8s %8s %8s\n","Port0", "Port1", "Port2", "Port3", "Port4", "Port5", "Port6"); ++ seq_printf(seq, "Tx Drop Packet :"); DUMP_EACH_PORT(0x4000); ++ //seq_printf(seq, "Tx CRC Error :"); DUMP_EACH_PORT(0x4004); ++ seq_printf(seq, "Tx Unicast Packet :"); DUMP_EACH_PORT(0x4008); ++ seq_printf(seq, "Tx Multicast Packet :"); DUMP_EACH_PORT(0x400C); ++ seq_printf(seq, "Tx Broadcast Packet :"); DUMP_EACH_PORT(0x4010); ++ //seq_printf(seq, "Tx Collision Event :"); DUMP_EACH_PORT(0x4014); ++ seq_printf(seq, "Tx Pause Packet :"); DUMP_EACH_PORT(0x402C); ++ seq_printf(seq, "Rx Drop Packet :"); DUMP_EACH_PORT(0x4060); ++ seq_printf(seq, "Rx Filtering Packet :"); DUMP_EACH_PORT(0x4064); ++ seq_printf(seq, "Rx Unicast Packet :"); DUMP_EACH_PORT(0x4068); ++ seq_printf(seq, "Rx Multicast Packet :"); DUMP_EACH_PORT(0x406C); ++ seq_printf(seq, "Rx Broadcast Packet :"); DUMP_EACH_PORT(0x4070); ++ seq_printf(seq, "Rx Alignment Error :"); DUMP_EACH_PORT(0x4074); ++ seq_printf(seq, "Rx CRC Error :"); DUMP_EACH_PORT(0x4078); ++ seq_printf(seq, "Rx Undersize Error :"); DUMP_EACH_PORT(0x407C); ++ //seq_printf(seq, "Rx Fragment Error :"); DUMP_EACH_PORT(0x4080); ++ //seq_printf(seq, "Rx Oversize Error :"); DUMP_EACH_PORT(0x4084); ++ //seq_printf(seq, "Rx Jabber Error :"); DUMP_EACH_PORT(0x4088); ++ seq_printf(seq, "Rx Pause Packet :"); DUMP_EACH_PORT(0x408C); ++ mii_mgr_write(31, 0x4fe0, 0xf0); ++ mii_mgr_write(31, 0x4fe0, 0x800000f0); ++#endif ++ ++ ++#elif defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ seq_printf(seq, "Port0 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xE8)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x150)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xE8)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x150)>>16); ++ ++ seq_printf(seq, "Port1 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xEC)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x154)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xEC)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x154)>>16); ++ ++ seq_printf(seq, "Port2 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF0)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x158)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF0)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x158)>>16); ++ ++ seq_printf(seq, "Port3 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF4)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x15C)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF4)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x15c)>>16); ++ ++ seq_printf(seq, "Port4 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF8)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x160)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF8)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x160)>>16); ++ ++ seq_printf(seq, "Port5 Good Pkt Cnt: RX=%08u Tx=%08u (Bad Pkt Cnt: Rx=%08u Tx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xFC)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0x164)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xFC)>>16, sysRegRead(RALINK_ETH_SW_BASE+0x164)>>16); ++#elif defined (CONFIG_RALINK_RT3883) ++ /* no built-in switch */ ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ++#define DUMP_EACH_PORT(base) \ ++ for(i=0; i < 7;i++) { \ ++ mii_mgr_read(31, (base) + (i*0x100), &pkt_cnt); \ ++ seq_printf(seq, "%8u ", pkt_cnt); \ ++ } \ ++ seq_printf(seq, "\n"); ++ ++#if defined (CONFIG_RALINK_MT7621) /* TODO: need to update to use MT7530 compiler flag */ ++ if(sysRegRead(0xbe00000c & (1<<16)))//MCM ++#endif ++ { ++ seq_printf(seq, "===================== %8s %8s %8s %8s %8s %8s %8s\n","Port0", "Port1", "Port2", "Port3", "Port4", "Port5", "Port6"); ++ seq_printf(seq, "Tx Drop Packet :"); DUMP_EACH_PORT(0x4000); ++ seq_printf(seq, "Tx CRC Error :"); DUMP_EACH_PORT(0x4004); ++ seq_printf(seq, "Tx Unicast Packet :"); DUMP_EACH_PORT(0x4008); ++ seq_printf(seq, "Tx Multicast Packet :"); DUMP_EACH_PORT(0x400C); ++ seq_printf(seq, "Tx Broadcast Packet :"); DUMP_EACH_PORT(0x4010); ++ seq_printf(seq, "Tx Collision Event :"); DUMP_EACH_PORT(0x4014); ++ seq_printf(seq, "Tx Pause Packet :"); DUMP_EACH_PORT(0x402C); ++ seq_printf(seq, "Rx Drop Packet :"); DUMP_EACH_PORT(0x4060); ++ seq_printf(seq, "Rx Filtering Packet :"); DUMP_EACH_PORT(0x4064); ++ seq_printf(seq, "Rx Unicast Packet :"); DUMP_EACH_PORT(0x4068); ++ seq_printf(seq, "Rx Multicast Packet :"); DUMP_EACH_PORT(0x406C); ++ seq_printf(seq, "Rx Broadcast Packet :"); DUMP_EACH_PORT(0x4070); ++ seq_printf(seq, "Rx Alignment Error :"); DUMP_EACH_PORT(0x4074); ++ seq_printf(seq, "Rx CRC Error :"); DUMP_EACH_PORT(0x4078); ++ seq_printf(seq, "Rx Undersize Error :"); DUMP_EACH_PORT(0x407C); ++ seq_printf(seq, "Rx Fragment Error :"); DUMP_EACH_PORT(0x4080); ++ seq_printf(seq, "Rx Oversize Error :"); DUMP_EACH_PORT(0x4084); ++ seq_printf(seq, "Rx Jabber Error :"); DUMP_EACH_PORT(0x4088); ++ seq_printf(seq, "Rx Pause Packet :"); DUMP_EACH_PORT(0x408C); ++ mii_mgr_write(31, 0x4fe0, 0xf0); ++ mii_mgr_write(31, 0x4fe0, 0x800000f0); ++ } ++#if defined (CONFIG_RALINK_MT7621) /* TODO: need to update to use MT7530 compiler flag */ ++ else { ++ seq_printf(seq, "no built-in switch\n"); ++ } ++#endif ++ ++#else /* RT305x, RT3352 */ ++ seq_printf(seq, "Port0: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xE8)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xE8)>>16); ++ seq_printf(seq, "Port1: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xEC)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xEC)>>16); ++ seq_printf(seq, "Port2: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF0)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF0)>>16); ++ seq_printf(seq, "Port3: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF4)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF4)>>16); ++ seq_printf(seq, "Port4: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xF8)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xF8)>>16); ++ seq_printf(seq, "Port5: Good Pkt Cnt: RX=%08u (Bad Pkt Cnt: Rx=%08u)\n", sysRegRead(RALINK_ETH_SW_BASE+0xFC)&0xFFFF,sysRegRead(RALINK_ETH_SW_BASE+0xFC)>>16); ++#endif ++ seq_printf(seq, "\n"); ++ ++ return 0; ++} ++ ++static int switch_count_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, EswCntRead, NULL); ++} ++ ++static const struct file_operations switch_count_fops = { ++ .owner = THIS_MODULE, ++ .open = switch_count_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++ ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++/* ++ * proc write procedure ++ */ ++static ssize_t change_phyid(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ char buf[32]; ++ struct net_device *cur_dev_p; ++ END_DEVICE *ei_local; ++ char if_name[64]; ++ unsigned int phy_id; ++ ++ if (count > 32) ++ count = 32; ++ memset(buf, 0, 32); ++ if (copy_from_user(buf, buffer, count)) ++ return -EFAULT; ++ ++ /* determine interface name */ ++ strcpy(if_name, DEV_NAME); /* "eth2" by default */ ++ if(isalpha(buf[0])) ++ sscanf(buf, "%s %d", if_name, &phy_id); ++ else ++ phy_id = simple_strtol(buf, 0, 10); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ cur_dev_p = dev_get_by_name(&init_net, DEV_NAME); ++#else ++ cur_dev_p = dev_get_by_name(DEV_NAME); ++#endif ++ if (cur_dev_p == NULL) ++ return -EFAULT; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ ei_local = netdev_priv(cur_dev_p); ++#else ++ ei_local = cur_dev_p->priv; ++#endif ++ ei_local->mii_info.phy_id = (unsigned char)phy_id; ++ return count; ++} ++ ++#if defined(CONFIG_PSEUDO_SUPPORT) ++static ssize_t change_gmac2_phyid(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ char buf[32]; ++ struct net_device *cur_dev_p; ++ PSEUDO_ADAPTER *pPseudoAd; ++ char if_name[64]; ++ unsigned int phy_id; ++ ++ if (count > 32) ++ count = 32; ++ memset(buf, 0, 32); ++ if (copy_from_user(buf, buffer, count)) ++ return -EFAULT; ++ /* determine interface name */ ++ strcpy(if_name, DEV2_NAME); /* "eth3" by default */ ++ if(isalpha(buf[0])) ++ sscanf(buf, "%s %d", if_name, &phy_id); ++ else ++ phy_id = simple_strtol(buf, 0, 10); ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ cur_dev_p = dev_get_by_name(&init_net, DEV2_NAME); ++#else ++ cur_dev_p = dev_get_by_name(DEV2_NAMEj); ++#endif ++ if (cur_dev_p == NULL) ++ return -EFAULT; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ pPseudoAd = netdev_priv(cur_dev_p); ++#else ++ pPseudoAd = cur_dev_p->priv; ++#endif ++ pPseudoAd->mii_info.phy_id = (unsigned char)phy_id; ++ return count; ++} ++ ++static struct file_operations gmac2_fops = { ++ .owner = THIS_MODULE, ++ .write = change_gmac2_phyid ++}; ++#endif ++#endif ++ ++static int gmac_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, RegReadMain, NULL); ++} ++ ++static struct file_operations gmac_fops = { ++ .owner = THIS_MODULE, ++ .open = gmac_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++#if defined (CONFIG_ETHTOOL) ++ .write = change_phyid, ++#endif ++ .release = single_release ++}; ++ ++#if defined (TASKLET_WORKQUEUE_SW) ++extern int init_schedule; ++extern int working_schedule; ++static int ScheduleRead(struct seq_file *seq, void *v) ++{ ++ if (init_schedule == 1) ++ seq_printf(seq, "Initialize Raeth with workqueque<%d>\n", init_schedule); ++ else ++ seq_printf(seq, "Initialize Raeth with tasklet<%d>\n", init_schedule); ++ if (working_schedule == 1) ++ seq_printf(seq, "Raeth is running at workqueque<%d>\n", working_schedule); ++ else ++ seq_printf(seq, "Raeth is running at tasklet<%d>\n", working_schedule); ++ ++ return 0; ++} ++ ++static ssize_t ScheduleWrite(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ char buf[2]; ++ int old; ++ ++ if (copy_from_user(buf, buffer, count)) ++ return -EFAULT; ++ old = init_schedule; ++ init_schedule = simple_strtol(buf, 0, 10); ++ printk("Change Raeth initial schedule from <%d> to <%d>\n! Not running schedule at present !\n", ++ old, init_schedule); ++ ++ return count; ++} ++ ++static int schedule_switch_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, ScheduleRead, NULL); ++} ++ ++static const struct file_operations schedule_sw_fops = { ++ .owner = THIS_MODULE, ++ .open = schedule_switch_open, ++ .read = seq_read, ++ .write = ScheduleWrite, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++#endif ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++static int PdmaDvtRead(struct seq_file *seq, void *v) ++{ ++ seq_printf(seq, "g_pdma_dvt_show_config = 0x%x\n", pdma_dvt_get_show_config()); ++ seq_printf(seq, "g_pdma_dvt_rx_test_config = 0x%x\n", pdma_dvt_get_rx_test_config()); ++ seq_printf(seq, "g_pdma_dvt_tx_test_config = 0x%x\n", pdma_dvt_get_tx_test_config()); ++ ++ return 0; ++} ++ ++static int PdmaDvtOpen(struct inode *inode, struct file *file) ++{ ++ return single_open(file, PdmaDvtRead, NULL); ++} ++ ++static ssize_t PdmaDvtWrite(struct file *file, const char __user *buffer, ++ size_t count, loff_t *data) ++{ ++ char buf[32]; ++ char *pBuf; ++ int len = count; ++ int x = 0,y = 0; ++ char *pToken = NULL; ++ char *pDelimiter = " \t"; ++ ++ printk("write parameter len = %d\n\r", (int)len); ++ if(len >= sizeof(buf)){ ++ printk("input handling fail!\n"); ++ len = sizeof(buf) - 1; ++ return -1; ++ } ++ ++ if(copy_from_user(buf, buffer, len)){ ++ return -EFAULT; ++ } ++ buf[len] = '\0'; ++ printk("write parameter data = %s\n\r", buf); ++ ++ pBuf = buf; ++ pToken = strsep(&pBuf, pDelimiter); ++ x = NULL != pToken ? simple_strtol(pToken, NULL, 16) : 0; ++ ++ pToken = strsep(&pBuf, "\t\n "); ++ if(pToken != NULL){ ++ y = NULL != pToken ? simple_strtol(pToken, NULL, 16) : 0; ++ printk("y = 0x%08x \n\r", y); ++ } ++ ++ if ( (sizeof(pdma_dvt_dbg_func)/sizeof(pdma_dvt_dbg_func[0]) > x) && NULL != pdma_dvt_dbg_func[x]) ++ { ++ (*pdma_dvt_dbg_func[x])(x, y); ++ } ++ else ++ { ++ printk("no handler defined for command id(0x%08x)\n\r", x); ++ } ++ ++ printk("x(0x%08x), y(0x%08x)\n", x, y); ++ ++ return len; ++} ++ ++static const struct file_operations pdma_dev_sw_fops = { ++ .owner = THIS_MODULE, ++ .open = PdmaDvtOpen, ++ .read = seq_read, ++ .write = PdmaDvtWrite ++}; ++#endif //#if defined(CONFIG_RAETH_PDMA_DVT) ++ ++int debug_proc_init(void) ++{ ++ if (procRegDir == NULL) ++ procRegDir = proc_mkdir(PROCREG_DIR, NULL); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procGmac = create_proc_entry(PROCREG_GMAC, 0, procRegDir))) ++ procGmac->proc_fops = &gmac_fops; ++ else ++#else ++ if (!(procGmac = proc_create(PROCREG_GMAC, 0, procRegDir, &gmac_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_GMAC); ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++#if defined(CONFIG_PSEUDO_SUPPORT) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procGmac2 = create_proc_entry(PROCREG_GMAC2, 0, procRegDir))) ++ procGmac2->proc_fops = &gmac2_fops; ++ else ++#else ++ if (!(procGmac2 = proc_create(PROCREG_GMAC2, 0, procRegDir, &gmac2_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_GMAC2); ++#endif ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procSkbFree = create_proc_entry(PROCREG_SKBFREE, 0, procRegDir))) ++ procSkbFree->proc_fops = &skb_free_fops; ++ else ++#else ++ if (!(procSkbFree = proc_create(PROCREG_SKBFREE, 0, procRegDir, &skb_free_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_SKBFREE); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procTxRing = create_proc_entry(PROCREG_TXRING, 0, procRegDir))) ++ procTxRing->proc_fops = &tx_ring_fops; ++ else ++#else ++ if (!(procTxRing = proc_create(PROCREG_TXRING, 0, procRegDir, &tx_ring_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_TXRING); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procRxRing = create_proc_entry(PROCREG_RXRING, 0, procRegDir))) ++ procRxRing->proc_fops = &rx_ring_fops; ++ else ++#else ++ if (!(procRxRing = proc_create(PROCREG_RXRING, 0, procRegDir, &rx_ring_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_RXRING); ++ ++#if defined (CONFIG_RAETH_HW_LRO) || defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procRxRing1 = create_proc_entry(PROCREG_RXRING1, 0, procRegDir))) ++ procRxRing1->proc_fops = &rx_ring1_fops; ++ else ++#else ++ if (!(procRxRing1 = proc_create(PROCREG_RXRING1, 0, procRegDir, &rx_ring1_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_RXRING1); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procRxRing2 = create_proc_entry(PROCREG_RXRING2, 0, procRegDir))) ++ procRxRing2->proc_fops = &rx_ring2_fops; ++ else ++#else ++ if (!(procRxRing2 = proc_create(PROCREG_RXRING2, 0, procRegDir, &rx_ring2_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_RXRING2); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procRxRing3 = create_proc_entry(PROCREG_RXRING3, 0, procRegDir))) ++ procRxRing3->proc_fops = &rx_ring3_fops; ++ else ++#else ++ if (!(procRxRing3 = proc_create(PROCREG_RXRING3, 0, procRegDir, &rx_ring3_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_RXRING3); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if defined (CONFIG_MIPS) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procSysCP0 = create_proc_entry(PROCREG_CP0, 0, procRegDir))) ++ procSysCP0->proc_fops = &cp0_reg_fops; ++ else ++#else ++ if (!(procSysCP0 = proc_create(PROCREG_CP0, 0, procRegDir, &cp0_reg_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_CP0); ++#endif ++ ++#if defined(CONFIG_RAETH_TSO) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procNumOfTxd = create_proc_entry(PROCREG_NUM_OF_TXD, 0, procRegDir))) ++ procNumOfTxd->proc_fops = &tso_txd_num_fops; ++ else ++#else ++ if (!(procNumOfTxd = proc_create(PROCREG_NUM_OF_TXD, 0, procRegDir, &tso_txd_num_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_NUM_OF_TXD); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procTsoLen = create_proc_entry(PROCREG_TSO_LEN, 0, procRegDir))) ++ procTsoLen->proc_fops = &tso_len_fops; ++ else ++#else ++ if (!(procTsoLen = proc_create(PROCREG_TSO_LEN, 0, procRegDir, &tso_len_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_TSO_LEN); ++#endif ++ ++#if defined(CONFIG_RAETH_LRO) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procLroStats = create_proc_entry(PROCREG_LRO_STATS, 0, procRegDir))) ++ procLroStats->proc_fops = &lro_stats_fops; ++ else ++#else ++ if (!(procLroStats = proc_create(PROCREG_LRO_STATS, 0, procRegDir, &lro_stats_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_LRO_STATS); ++#endif ++ ++#if defined(CONFIG_RAETH_HW_LRO) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procHwLroStats = create_proc_entry(PROCREG_HW_LRO_STATS, 0, procRegDir))) ++ procHwLroStats->proc_fops = &hw_lro_stats_fops; ++ else ++#else ++ if (!(procHwLroStats = proc_create(PROCREG_HW_LRO_STATS, 0, procRegDir, &hw_lro_stats_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_HW_LRO_STATS); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procHwLroAutoTlb = create_proc_entry(PROCREG_HW_LRO_AUTO_TLB, 0, procRegDir))) ++ procHwLroAutoTlb->proc_fops = &hw_lro_auto_tlb_fops; ++ else ++#else ++ if (!(procHwLroAutoTlb = proc_create(PROCREG_HW_LRO_AUTO_TLB, 0, procRegDir, &hw_lro_auto_tlb_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_HW_LRO_AUTO_TLB); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if defined(CONFIG_RAETH_QOS) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procRaQOS = create_proc_entry(PROCREG_RAQOS, 0, procRegDir))) ++ procRaQOS->proc_fops = &raeth_qos_fops; ++ else ++#else ++ if (!(procRaQOS = proc_create(PROCREG_RAQOS, 0, procRegDir, &raeth_qos_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_RAQOS); ++#endif ++ ++#if defined(CONFIG_USER_SNMPD) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procRaSnmp = create_proc_entry(PROCREG_SNMP, S_IRUGO, procRegDir))) ++ procRaSnmp->proc_fops = &ra_snmp_seq_fops; ++ else ++#else ++ if (!(procRaSnmp = proc_create(PROCREG_SNMP, S_IRUGO, procRegDir, &ra_snmp_seq_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_SNMP); ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procEswCnt = create_proc_entry(PROCREG_ESW_CNT, 0, procRegDir))) ++ procEswCnt->proc_fops = &switch_count_fops; ++ else ++#else ++ if (!(procEswCnt = proc_create(PROCREG_ESW_CNT, 0, procRegDir, &switch_count_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_ESW_CNT); ++ ++#if defined (TASKLET_WORKQUEUE_SW) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procSCHE = create_proc_entry(PROCREG_SCHE, 0, procRegDir))) ++ procSCHE->proc_fops = &schedule_sw_fops; ++ else ++#else ++ if (!(procSCHE = proc_create(PROCREG_SCHE, 0, procRegDir, &schedule_sw_fops))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_SCHE); ++#endif ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ if ((procPdmaDvt = create_proc_entry(PROCREG_PDMA_DVT, 0, procRegDir))) ++ procPdmaDvt->proc_fops = &pdma_dev_sw_fops; ++ else ++#else ++ if (!(procPdmaDvt = proc_create(PROCREG_PDMA_DVT, 0, procRegDir, &pdma_dev_sw_fops ))) ++#endif ++ printk("!! FAIL to create %s PROC !!\n", PROCREG_PDMA_DVT); ++#endif //#if defined(CONFIG_RAETH_PDMA_DVT) ++ ++ printk(KERN_ALERT "PROC INIT OK!\n"); ++ return 0; ++} ++ ++void debug_proc_exit(void) ++{ ++ ++ if (procSysCP0) ++ remove_proc_entry(PROCREG_CP0, procRegDir); ++ ++ if (procGmac) ++ remove_proc_entry(PROCREG_GMAC, procRegDir); ++#if defined(CONFIG_PSEUDO_SUPPORT) && defined(CONFIG_ETHTOOL) ++ if (procGmac) ++ remove_proc_entry(PROCREG_GMAC, procRegDir); ++#endif ++ if (procSkbFree) ++ remove_proc_entry(PROCREG_SKBFREE, procRegDir); ++ ++ if (procTxRing) ++ remove_proc_entry(PROCREG_TXRING, procRegDir); ++ ++ if (procRxRing) ++ remove_proc_entry(PROCREG_RXRING, procRegDir); ++ ++#if defined(CONFIG_RAETH_TSO) ++ if (procNumOfTxd) ++ remove_proc_entry(PROCREG_NUM_OF_TXD, procRegDir); ++ ++ if (procTsoLen) ++ remove_proc_entry(PROCREG_TSO_LEN, procRegDir); ++#endif ++ ++#if defined(CONFIG_RAETH_LRO) ++ if (procLroStats) ++ remove_proc_entry(PROCREG_LRO_STATS, procRegDir); ++#endif ++ ++#if defined(CONFIG_RAETH_QOS) ++ if (procRaQOS) ++ remove_proc_entry(PROCREG_RAQOS, procRegDir); ++ if (procRaFeIntr) ++ remove_proc_entry(PROCREG_RXDONE_INTR, procRegDir); ++ if (procRaEswIntr) ++ remove_proc_entry(PROCREG_ESW_INTR, procRegDir); ++#endif ++ ++#if defined(CONFIG_USER_SNMPD) ++ if (procRaSnmp) ++ remove_proc_entry(PROCREG_SNMP, procRegDir); ++#endif ++ ++ if (procEswCnt) ++ remove_proc_entry(PROCREG_ESW_CNT, procRegDir); ++ ++ //if (procRegDir) ++ //remove_proc_entry(PROCREG_DIR, 0); ++ ++ printk(KERN_ALERT "proc exit\n"); ++} ++EXPORT_SYMBOL(procRegDir); +diff --git a/drivers/net/ethernet/raeth/ra_mac.h b/drivers/net/ethernet/raeth/ra_mac.h +new file mode 100644 +index 0000000..66b32d3 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_mac.h +@@ -0,0 +1,57 @@ ++#ifndef RA_MAC_H ++#define RA_MAC_H ++ ++void ra2880stop(END_DEVICE *ei_local); ++void ra2880MacAddressSet(unsigned char p[6]); ++void ra2880Mac2AddressSet(unsigned char p[6]); ++void ethtool_init(struct net_device *dev); ++ ++void ra2880EnableInterrupt(void); ++ ++void dump_qos(void); ++void dump_reg(struct seq_file *s); ++void dump_cp0(void); ++ ++int debug_proc_init(void); ++void debug_proc_exit(void); ++ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) ++void enable_auto_negotiate(int unused); ++#else ++void enable_auto_negotiate(int ge); ++#endif ++ ++void rt2880_gmac_hard_reset(void); ++ ++int TsoLenUpdate(int tso_len); ++int NumOfTxdUpdate(int num_of_txd); ++ ++#ifdef CONFIG_RAETH_LRO ++int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed); ++#endif ++#ifdef CONFIG_RAETH_HW_LRO ++int HwLroStatsUpdate(unsigned int ring_num, unsigned int agg_cnt, unsigned int agg_size); ++#if defined(CONFIG_RAETH_HW_LRO_REASON_DBG) ++#define HW_LRO_AGG_FLUSH (1) ++#define HW_LRO_AGE_FLUSH (2) ++#define HW_LRO_NOT_IN_SEQ_FLUSH (3) ++#define HW_LRO_TIMESTAMP_FLUSH (4) ++#define HW_LRO_NON_RULE_FLUSH (5) ++int HwLroFlushStatsUpdate(unsigned int ring_num, unsigned int flush_reason); ++#endif /* CONFIG_RAETH_HW_LRO_REASON_DBG */ ++typedef int (*HWLRO_DBG_FUNC)(int par1, int par2); ++int hwlro_agg_cnt_ctrl(int par1, int par2); ++int hwlro_agg_time_ctrl(int par1, int par2); ++int hwlro_age_time_ctrl(int par1, int par2); ++int hwlro_pkt_int_alpha_ctrl(int par1, int par2); ++int hwlro_threshold_ctrl(int par1, int par2); ++int hwlro_fix_setting_switch_ctrl(int par1, int par2); ++#endif /* CONFIG_RAETH_HW_LRO */ ++int getnext(const char *src, int separator, char *dest); ++int str_to_ip(unsigned int *ip, const char *str); ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++typedef int (*PDMA_DBG_FUNC)(int par1, int par2); ++#endif //#if defined(CONFIG_RAETH_PDMA_DVT) ++#endif +diff --git a/drivers/net/ethernet/raeth/ra_netlink.c b/drivers/net/ethernet/raeth/ra_netlink.c +new file mode 100644 +index 0000000..f7c3650 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_netlink.c +@@ -0,0 +1,142 @@ ++// for netlink header ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "csr_netlink.h" ++#include "ra2882ethreg.h" ++#include "ra_netlink.h" ++ ++static struct sock *csr_msg_socket = NULL; // synchronize socket for netlink use ++unsigned int flags; ++ ++void rt2880_csr_receiver(struct sock *sk, int len) ++{ ++ struct sk_buff *skb; ++ int err; ++ struct nlmsghdr *nlh; ++ unsigned int reg_value = 0; ++ CSR_MSG *csrmsg; ++ RAETH_PRINT("csr netlink receiver!\n"); ++ skb = skb_recv_datagram(sk, 0, 1, &err); ++ ++ RAETH_PRINT("error no : %d\n", err); ++ ++ if (skb == NULL) { ++ printk("rt2880_csr_receiver(): No data received, error!\n"); ++ return; ++ } ++ ++ nlh = (struct nlmsghdr*)skb->data; ++ ++ csrmsg = NLMSG_DATA(nlh); ++ ++ if (csrmsg->enable == CSR_READ ) { ++ reg_value = sysRegRead(csrmsg->address); ++#if 0 ++ printk("raeth -- 0x%08x: 0x%08x\n", csrmsg->address, reg_value); ++#endif ++ } else if ( csrmsg->enable == CSR_WRITE ) { ++ sysRegWrite(csrmsg->address, csrmsg->default_value); ++ reg_value = sysRegRead(csrmsg->address); ++ } else if ( csrmsg->enable == CSR_TEST ) { ++ reg_value = sysRegRead(csrmsg->address); ++ printk("0x%08x: 0x%08x\n", (unsigned int)csrmsg->address, reg_value); ++ } ++ else ++ printk("drv: Command format error!\n"); ++ ++ csrmsg->default_value = reg_value; ++ ++ RAETH_PRINT("drv: rt2880_csr_msgsend() - msg to send!\n"); ++ ++ err = rt2880_csr_msgsend(csrmsg); ++ ++ if ( err == -2 ) ++ printk("drv: msg send error!\n"); ++ ++ skb_free_datagram(sk, skb); ++} ++ ++int rt2880_csr_msgsend(CSR_MSG* csrmsg) ++{ ++ struct sk_buff *skb; ++ struct nlmsghdr *nlh = NULL; ++ size_t size = 0; ++ struct sock *send_syncnl = csr_msg_socket; ++ ++ CSR_MSG* csr_reg; ++ if (send_syncnl == NULL) { ++ printk("drv: netlink_kernel_create() failed!\n"); ++ return -1; ++ } ++ ++ size = NLMSG_SPACE(sizeof(CSR_MSG)); ++ skb = alloc_skb(size, GFP_ATOMIC); ++ ++ if(!skb) ++ { ++ printk("rt2880_csr_msgsend() : error! msg structure not available\n"); ++ return -1; ++ } ++ ++ nlh = NLMSG_PUT(skb, 0, 0, RALINK_CSR_GROUP, size - sizeof(struct nlmsghdr)); ++ ++ if (!nlh) ++ { ++ printk("rt2880_csr_msgsend() : error! nlh structure not available\n"); ++ return -1; ++ } ++ ++ csr_reg = NLMSG_DATA(nlh); ++ if (!csr_reg) ++ { ++ printk("rt2880_csr_msgsend() : error! nlh structure not available\n"); ++ return -1; ++ } ++ ++ csr_reg->address = csrmsg->address; ++ csr_reg->default_value = csrmsg->default_value; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++ NETLINK_CB(skb).dst_group = RALINK_CSR_GROUP; ++#else ++ NETLINK_CB(skb).dst_groups = RALINK_CSR_GROUP; ++#endif ++ netlink_broadcast(send_syncnl, skb, 0, RALINK_CSR_GROUP, GFP_ATOMIC); ++ return 0; ++ ++nlmsg_failure: ++ return -2; ++} ++ ++int csr_netlink_init() ++{ ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++ csr_msg_socket = netlink_kernel_create(NETLINK_CSR, RALINK_CSR_GROUP, rt2880_csr_receiver, THIS_MODULE); ++#else ++ csr_msg_socket = netlink_kernel_create(NETLINK_CSR, rt2880_csr_receiver); ++#endif ++ ++ if ( csr_msg_socket == NULL ) ++ printk("unable to create netlink socket!\n"); ++ else ++ printk("Netlink init ok!\n"); ++ return 0; ++} ++ ++void csr_netlink_end() ++{ ++ if (csr_msg_socket != NULL){ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++ sock_release(csr_msg_socket->sk_socket); ++#else ++ sock_release(csr_msg_socket->socket); ++#endif ++ printk("Netlink end...\n"); ++ } ++} +diff --git a/drivers/net/ethernet/raeth/ra_netlink.h b/drivers/net/ethernet/raeth/ra_netlink.h +new file mode 100644 +index 0000000..19ca71f +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_netlink.h +@@ -0,0 +1,10 @@ ++#ifndef RA_NETLINK ++#define RA_NETLINK ++ ++#include "csr_netlink.h" ++int rt2880_csr_msgsend(CSR_MSG* csrmsg); ++void rt2880_csr_receiver(struct sock *sk, int len); ++int csr_netlink_init(void); ++void csr_netlink_end(void); ++ ++#endif +diff --git a/drivers/net/ethernet/raeth/ra_qos.c b/drivers/net/ethernet/raeth/ra_qos.c +new file mode 100644 +index 0000000..0a7d9c5 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_qos.c +@@ -0,0 +1,655 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ra_qos.h" ++#include "raether.h" ++#include "ra2882ethreg.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++#include "../../../net/nat/hw_nat/ra_nat.h" ++#endif ++ ++#define CONTI_TX_SEND_MAX_SIZE 1440 ++ ++/* ++ * set tx queue # to descriptor ++ */ ++void rt3052_tx_queue_init(unsigned long data) ++{ ++ /* define qos p */ ++ ++} ++ ++void rt3052_pse_port0_fc_clear(unsigned long data) ++{ ++ /* clear FE_INT_STATUS.PSE_P0_FC */ ++ ++} ++ ++inline int get_tx_ctx_idx(unsigned int ring_no, unsigned long *idx) ++{ ++ switch (ring_no) { ++ case RING0: ++ *idx = *(unsigned long*)TX_CTX_IDX0; ++ break; ++ case RING1: ++ *idx = *(unsigned long*)TX_CTX_IDX1; ++ break; ++ case RING2: ++ *idx = *(unsigned long*)TX_CTX_IDX2; ++ break; ++ case RING3: ++ *idx = *(unsigned long*)TX_CTX_IDX3; ++ break; ++ default: ++ printk("set_tx_ctx_idex error\n"); ++ return -1; ++ }; ++ return 0; ++} ++ ++inline int set_tx_ctx_idx(unsigned int ring_no, unsigned int idx) ++{ ++ switch (ring_no ) { ++ case RING0: ++ *(unsigned long*)TX_CTX_IDX0 = cpu_to_le32((u32)idx); ++ break; ++ case RING1: ++ *(unsigned long*)TX_CTX_IDX1 = cpu_to_le32((u32)idx); ++ break; ++ case RING2: ++ *(unsigned long*)TX_CTX_IDX2 = cpu_to_le32((u32)idx); ++ break; ++ case RING3: ++ *(unsigned long*)TX_CTX_IDX3 = cpu_to_le32((u32)idx); ++ break; ++ default: ++ printk("set_tx_ctx_idex error\n"); ++ return -1; ++ }; ++ ++ return 1; ++} ++ ++void get_tx_desc_and_dtx_idx(END_DEVICE* ei_local, int ring_no, unsigned long *tx_dtx_idx, struct PDMA_txdesc **tx_desc) ++{ ++ switch (ring_no) { ++ case RING0: ++ *tx_desc = ei_local->tx_ring0; ++ *tx_dtx_idx = *(unsigned long*)TX_DTX_IDX0; ++ break; ++ case RING1: ++ *tx_desc = ei_local->tx_ring1; ++ *tx_dtx_idx = *(unsigned long*)TX_DTX_IDX1; ++ break; ++ case RING2: ++ *tx_desc = ei_local->tx_ring2; ++ *tx_dtx_idx = *(unsigned long*)TX_DTX_IDX2; ++ break; ++ case RING3: ++ *tx_desc = ei_local->tx_ring3; ++ *tx_dtx_idx = *(unsigned long*)TX_DTX_IDX3; ++ break; ++ default: ++ printk("ring_no input error... %d\n", ring_no); ++ }; ++} ++ ++int fe_qos_packet_send(struct net_device *dev, struct sk_buff* skb, unsigned int ring_no, unsigned int qn, unsigned pn) ++{ ++ END_DEVICE* ei_local = netdev_priv(dev); ++ struct PDMA_txdesc* tx_desc; ++ unsigned int tx_cpu_owner_idx, tx_dtx_idx; ++ ++ unsigned int length=skb->len; ++ int ret; ++ unsigned long flags; ++ ++ //printk("fe_qos_packet_send: ring_no=%d qn=%d pn=%d\n", ring_no, qn, pn); ++ ++ switch ( ring_no ) { ++ case 0: ++ tx_desc = ei_local->tx_ring0; ++ tx_cpu_owner_idx = *(unsigned long*)TX_CTX_IDX0; ++ tx_dtx_idx = *(unsigned long*)TX_DTX_IDX0; ++ break; ++ case 1: ++ tx_desc = ei_local->tx_ring1; ++ tx_cpu_owner_idx = *(unsigned long*)TX_CTX_IDX1; ++ tx_dtx_idx = *(unsigned long*)TX_DTX_IDX1; ++ break; ++ case 2: ++ tx_desc = ei_local->tx_ring2; ++ tx_cpu_owner_idx = *(unsigned long*)TX_CTX_IDX2; ++ tx_dtx_idx = *(unsigned long*)TX_DTX_IDX2; ++ break; ++ case 3: ++ tx_desc = ei_local->tx_ring3; ++ tx_cpu_owner_idx = *(unsigned long*)TX_CTX_IDX3; ++ tx_dtx_idx = *(unsigned long*)TX_DTX_IDX3; ++ break; ++ default: ++ printk("ring_no input error... %d\n", ring_no); ++ return -1; ++ }; ++ ++ //printk("tx_cpu_owner_idx=%d tx_dtx_idx=%d\n", tx_cpu_owner_idx, tx_dtx_idx); ++ ++ if(tx_desc == NULL) { ++ printk("%s : txdesc is NULL\n", dev->name); ++ return -1; ++ } ++ ++ tx_desc[tx_cpu_owner_idx].txd_info1.SDP0 = virt_to_phys(skb->data); ++ tx_desc[tx_cpu_owner_idx].txd_info2.SDL0 = length; ++ tx_desc[tx_cpu_owner_idx].txd_info2.DDONE_bit = 0; ++ tx_desc[tx_cpu_owner_idx].txd_info4.PN = pn; ++ tx_desc[tx_cpu_owner_idx].txd_info4.QN = qn; ++ ++#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD ++ ei_local->tx_ring0[tx_cpu_owner_idx].txd_info4.TCO = 1; ++ ei_local->tx_ring0[tx_cpu_owner_idx].txd_info4.UCO = 1; ++ ei_local->tx_ring0[tx_cpu_owner_idx].txd_info4.ICO = 1; ++#endif ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ tx_desc[tx_cpu_owner_idx].txd_info4.PN = 6; /* PPE */ ++ } else { ++ tx_desc[tx_cpu_owner_idx].txd_info4.PN = pn; ++ } ++ ++#endif ++ ++ spin_lock_irqsave(&ei_local->page_lock, flags); ++ ei_local->skb_free[ring_no][tx_cpu_owner_idx] = skb; ++ tx_cpu_owner_idx = (tx_cpu_owner_idx +1) % NUM_TX_DESC; ++ ret = set_tx_ctx_idx(ring_no, tx_cpu_owner_idx); ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += length; ++ ++#ifdef CONFIG_RAETH_NAPI ++ switch ( ring_no ) { ++ case 0: ++ if ( ei_local->tx0_full == 1) { ++ ei_local->tx0_full = 0; ++ netif_wake_queue(dev); ++ } ++ break; ++ case 1: ++ if ( ei_local->tx1_full == 1) { ++ ei_local->tx1_full = 0; ++ netif_wake_queue(dev); ++ } ++ break; ++ case 2: ++ if ( ei_local->tx2_full == 1) { ++ ei_local->tx2_full = 0; ++ netif_wake_queue(dev); ++ } ++ break; ++ case 3: ++ if ( ei_local->tx3_full == 1) { ++ ei_local->tx3_full = 0; ++ netif_wake_queue(dev); ++ } ++ break; ++ default : ++ printk("ring_no input error %d\n", ring_no); ++ }; ++#endif ++ return length; ++} ++ ++int fe_tx_desc_init(struct net_device *dev, unsigned int ring_no, unsigned int qn, unsigned int pn) ++{ ++ END_DEVICE* ei_local = netdev_priv(dev); ++ struct PDMA_txdesc *tx_desc; ++ unsigned int tx_cpu_owner_idx = 0; ++ int i; ++ unsigned int phy_tx_ring; ++ ++ // sanity check ++ if ( ring_no > 3 ){ ++ printk("%s : ring_no - %d, please under 4...\n", dev->name, ring_no); ++ return 0; ++ } ++ ++ if ( pn > 2 ){ ++ printk("%s : pn - %d, please under 2...\n", dev->name, pn); ++ return 0; ++ } ++ ++ tx_desc = pci_alloc_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), &phy_tx_ring); ++ ei_local->tx_cpu_owner_idx0 = tx_cpu_owner_idx; ++ ++ switch (ring_no) { ++ case 0: ++ ei_local->tx_ring0 = tx_desc; ++ ei_local->phy_tx_ring0 = phy_tx_ring; ++ break; ++ case 1: ++ ei_local->phy_tx_ring1 = phy_tx_ring; ++ ei_local->tx_ring1 = tx_desc; ++ break; ++ case 2: ++ ei_local->phy_tx_ring2 = phy_tx_ring; ++ ei_local->tx_ring2 = tx_desc; ++ break; ++ case 3: ++ ei_local->phy_tx_ring3 = phy_tx_ring; ++ ei_local->tx_ring3 = tx_desc; ++ break; ++ default: ++ printk("ring_no input error! %d\n", ring_no); ++ pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), tx_desc, phy_tx_ring); ++ return 0; ++ }; ++ ++ if ( tx_desc == NULL) ++ { ++ printk("tx desc allocation failed!\n"); ++ return 0; ++ } ++ ++ for( i = 0; i < NUM_TX_DESC; i++) { ++ memset( &tx_desc[i], 0, sizeof(struct PDMA_txdesc)); ++ tx_desc[i].txd_info2.LS0_bit = 1; ++ tx_desc[i].txd_info2.DDONE_bit = 1; ++ tx_desc[i].txd_info4.PN = pn; ++ tx_desc[i].txd_info4.QN = qn; ++ } ++ ++ switch ( ring_no ) { ++ case 0 : ++ *(unsigned long*)TX_BASE_PTR0 = phys_to_bus((u32) phy_tx_ring); ++ *(unsigned long*)TX_MAX_CNT0 = cpu_to_le32((u32)NUM_TX_DESC); ++ *(unsigned long*)TX_CTX_IDX0 = cpu_to_le32((u32) tx_cpu_owner_idx); ++ sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0); ++ break; ++ case 1 : ++ *(unsigned long*)TX_BASE_PTR1 = phys_to_bus((u32) phy_tx_ring); ++ *(unsigned long*)TX_MAX_CNT1 = cpu_to_le32((u32)NUM_TX_DESC); ++ *(unsigned long*)TX_CTX_IDX1 = cpu_to_le32((u32) tx_cpu_owner_idx); ++ sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX1); ++ break; ++ case 2 : ++ *(unsigned long*)TX_BASE_PTR2 = phys_to_bus((u32) phy_tx_ring); ++ *(unsigned long*)TX_MAX_CNT2 = cpu_to_le32((u32)NUM_TX_DESC); ++ *(unsigned long*)TX_CTX_IDX2 = cpu_to_le32((u32) tx_cpu_owner_idx); ++ sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX2); ++ break; ++ case 3 : ++ *(unsigned long*)TX_BASE_PTR3 = phys_to_bus((u32) phy_tx_ring); ++ *(unsigned long*)TX_MAX_CNT3 = cpu_to_le32((u32)NUM_TX_DESC); ++ *(unsigned long*)TX_CTX_IDX3 = cpu_to_le32((u32) tx_cpu_owner_idx); ++ sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX3); ++ break; ++ default : ++ printk("tx descriptor init failed %d\n", ring_no); ++ return 0; ++ }; ++ return 1; ++} ++ ++/* ++ DSCP | AC | WMM_AC (Access Category) ++ ------+----+-------- ++ 00-07| 1 | BE ++ 24-31| 1 | BE ++ 08-15| 0 | BG ++ 16-23| 0 | BG ++ 32-39| 2 | VI ++ 40-47| 2 | VI ++ 48-55| 3 | VO ++ 56-63| 3 | VO ++ ++ | TOS | ++ DSCP |(bit5~bit7)| WMM ++ -------+-----------+------- ++ 0x00 | 000 | BE ++ 0x18 | 011 | BE ++ 0x08 | 001 | BG ++ 0x10 | 010 | BG ++ 0x20 | 100 | VI ++ 0x28 | 101 | VI ++ 0x30 | 110 | VO ++ 0x38 | 111 | VO ++ ++ Notes: BE should be mapped to AC1, but mapped to AC0 in linux kernel. ++ ++ */ ++ ++int pkt_classifier(struct sk_buff *skb,int gmac_no, int *ring_no, int *queue_no, int *port_no) ++{ ++#if defined(CONFIG_RALINK_RT2880) ++ /* RT2880 -- Assume using 1 Ring (Ring0), Queue 0, and Port 0 */ ++ *port_no = 0; ++ *ring_no = 0; ++ *queue_no = 0; ++#else ++ unsigned int ac=0; ++ unsigned int bridge_traffic=0, lan_traffic=0; ++ struct iphdr *iph=NULL; ++ struct vlan_ethhdr *veth=NULL; ++ unsigned int vlan_id=0; ++#if defined (CONFIG_RAETH_QOS_DSCP_BASED) ++ static char DscpToAcMap[8]={1,0,0,1,2,2,3,3}; ++#elif defined (CONFIG_RAETH_QOS_VPRI_BASED) ++ static char VlanPriToAcMap[8]={1,0,0,1,2,2,3,3}; ++#endif ++ ++ /* Bridge:: {BG,BE,VI,VO} */ ++ /* GateWay:: WAN: {BG,BE,VI,VO}, LAN: {BG,BE,VI,VO} */ ++#if defined (CONFIG_RALINK_RT3883) && defined (CONFIG_RAETH_GMAC2) ++ /* ++ * 1) Bridge: ++ * 1.1) GMAC1 ONLY: ++ * VO/VI->Ring3, BG/BE->Ring2 ++ * 1.2) GMAC1+GMAC2: ++ * GMAC1:: VO/VI->Ring3, BG/BE->Ring2 ++ * GMAC2:: VO/VI->Ring1, BG/BE->Ring0 ++ * 2) GateWay: ++ * 2.1) GMAC1 ONLY: ++ * GMAC1:: LAN:VI/VO->Ring2, BE/BK->Ring2 ++ * WAN:VI/VO->Ring3, BE/BK->Ring3 ++ * 2.2)GMAC1+GMAC2: ++ * GMAC1:: LAN:VI/VO/BE/BK->Ring2, WAN:VI/VO/BE/BK->Ring3 ++ * GMAC2:: VI/VO->Ring1, BE/BK->Ring0 ++ */ ++ static unsigned char AcToRing_BridgeMap[4] = {2, 2, 3, 3}; ++ static unsigned char AcToRing_GE1Map[2][4] = {{3, 3, 3, 3},{2, 2, 2, 2}}; ++ static unsigned char AcToRing_GE2Map[4] = {0, 0, 1, 1}; ++#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT2883) || \ ++ defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || \ ++ defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \ ++ defined (CONFIG_RALINK_MT7628) || \ ++ (defined (CONFIG_RALINK_RT3883) && !defined(CONFIG_RAETH_GMAC2)) ++ /* ++ * 1) Bridge: VO->Ring3, VI->Ring2, BG->Ring1, BE->Ring0 ++ * 2) GateWay: ++ * 2.1) GMAC1:: LAN:VI/VO->Ring1, BE/BK->Ring0 ++ * WAN:VI/VO->Ring3, BE/BK->Ring2 ++ */ ++ static unsigned char AcToRing_BridgeMap[4] = {0, 1, 2, 3}; ++ static unsigned char AcToRing_GE1Map[2][4] = {{2, 2, 3, 3},{0, 0, 1, 1}}; ++#endif // CONFIG_RALINK_RT2883 ++ ++ /* ++ * Set queue no - QN field in TX Descriptor ++ * always use queue 3 for the packet from CPU to GMAC ++ */ ++ *queue_no = 3; ++ ++ /* Get access category */ ++ veth = (struct vlan_ethhdr *)(skb->data); ++ if(veth->h_vlan_proto == htons(ETH_P_8021Q)) { // VLAN traffic ++ iph= (struct iphdr *)(skb->data + VLAN_ETH_HLEN); ++ ++ vlan_id = ntohs(veth->h_vlan_TCI & VLAN_VID_MASK); ++ if(vlan_id==1) { //LAN ++ lan_traffic = 1; ++ } else { //WAN ++ lan_traffic = 0; ++ } ++ ++ if (veth->h_vlan_encapsulated_proto == htons(ETH_P_IP)) { //IPv4 ++#if defined (CONFIG_RAETH_QOS_DSCP_BASED) ++ ac = DscpToAcMap[(iph->tos & 0xe0) >> 5]; ++#elif defined (CONFIG_RAETH_QOS_VPRI_BASED) ++ ac = VlanPriToAcMap[skb->priority]; ++#endif ++ }else { //Ipv6, ARP ...etc ++ ac = 0; ++ } ++ }else { // non-VLAN traffic ++ if (veth->h_vlan_proto == htons(ETH_P_IP)) { //IPv4 ++#if defined (CONFIG_RAETH_QOS_DSCP_BASED) ++ iph= (struct iphdr *)(skb->data + ETH_HLEN); ++ ac = DscpToAcMap[(iph->tos & 0xe0) >> 5]; ++#elif defined (CONFIG_RAETH_QOS_VPRI_BASED) ++ ac= VlanPriToAcMap[skb->priority]; ++#endif ++ }else { // IPv6, ARP ...etc ++ ac = 0; ++ } ++ ++ bridge_traffic=1; ++ } ++ ++ ++ /* Set Tx Ring no */ ++ if(gmac_no==1) { //GMAC1 ++ if(bridge_traffic) { //Bridge Mode ++ *ring_no = AcToRing_BridgeMap[ac]; ++ }else { //GateWay Mode ++ *ring_no = AcToRing_GE1Map[lan_traffic][ac]; ++ } ++ }else { //GMAC2 ++#if defined (CONFIG_RALINK_RT3883) && defined (CONFIG_RAETH_GMAC2) ++ *ring_no = AcToRing_GE2Map[ac]; ++#endif ++ } ++ ++ ++ /* Set Port No - PN field in Tx Descriptor*/ ++#if defined(CONFIG_RAETH_GMAC2) ++ *port_no = gmac_no; ++#else ++ if(bridge_traffic) { ++ *port_no = 1; ++ }else { ++ if(lan_traffic==1) { //LAN use VP1 ++ *port_no = 1; ++ }else { //WAN use VP2 ++ *port_no = 2; ++ } ++ } ++#endif // CONFIG_RAETH_GMAC2 // ++ ++#endif ++ ++ return 1; ++ ++} ++ ++ ++/* ++ * Routine Description : ++ * Hi/Li Rings and Queues definition for QoS Purpose ++ * ++ * Related registers: (Detail information refer to pp106 of RT3052_DS_20080226.doc) ++ * Priority High/Low Definition - PDMA_FC_CFG, GDMA1_FC_CFG, GDMA2_FC_CFG ++ * Bit 28 - Allows high priority Q to share low priority Q's reserved pages ++ * Bit 27:24 - Px high priority definition bitmap ++ * Weight Configuration - GDMA1_SCH_CFG, GDMA2_SCH_CFG, PDMA_SCH_CFG -> default 3210 ++ * ++ * Parameter: ++ * NONE ++ * ++*/ ++#define PSE_P1_LQ_FULL (1<<2) ++#define PSE_P1_HQ_FULL (1<<3) ++#define PSE_P2_LQ_FULL (1<<4) ++#define PSE_P2_HQ_FULL (1<<5) ++ ++#define HIGH_QUEUE(queue) (1<<(queue)) ++#define LOW_QUEUE(queue) (0<<(queue)) ++#define PAGES_SHARING (1<<28) ++#define RSEV_PAGE_COUNT_HQ 0x10 /* Reserved page count for high priority Q */ ++#define RSEV_PAGE_COUNT_LQ 0x10 /* Reserved page count for low priority Q */ ++#define VIQ_FC_ASRT 0x10 /* Virtual input Q FC assertion threshold */ ++ ++#define QUEUE_WEIGHT_1 0 ++#define QUEUE_WEIGHT_2 1 ++#define QUEUE_WEIGHT_4 2 ++#define QUEUE_WEIGHT_8 3 ++#define QUEUE_WEIGHT_16 4 ++ ++#define WRR_SCH 0 /*WRR */ ++#define STRICT_PRI_SCH 1 /* Strict Priority */ ++#define MIX_SCH 2 /* Mixed : Q3>WRR(Q2,Q1,Q0) */ ++ ++/* ++ * Ring3 Ring2 Ring1 Ring0 ++ * | | | | | | | | ++ * | | | | | | | | ++ * -------------------------------- ++ * | WRR Scheduler | ++ * -------------------------------- ++ * | ++ * --------------------------------------- ++ * | PDMA | ++ * --------------------------------------- ++ * |Q3||Q2||Q1||Q0| |Q3||Q2||Q1||Q0| ++ * | || || || | | || || || | ++ * ------------------- ------------------- ++ * | GDMA2 | | GDMA1 | ++ * ------------------- ------------------- ++ * | | ++ * ------------------------------------ ++ * | GMAC | ++ * ------------------------------------ ++ * | ++ * ++ */ ++void set_scheduler_weight(void) ++{ ++#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628) ++ /* ++ * STEP1: Queue scheduling configuration ++ */ ++ *(unsigned long *)GDMA1_SCH_CFG = (WRR_SCH << 24) | ++ (QUEUE_WEIGHT_16 << 12) | /* queue 3 weight */ ++ (QUEUE_WEIGHT_8 << 8) | /* queue 2 weight */ ++ (QUEUE_WEIGHT_4 << 4) | /* queue 1 weight */ ++ (QUEUE_WEIGHT_2 << 0); /* queue 0 weight */ ++ ++ *(unsigned long *)GDMA2_SCH_CFG = (WRR_SCH << 24) | ++ (QUEUE_WEIGHT_16 << 12) | /* queue 3 weight */ ++ (QUEUE_WEIGHT_8 << 8) | /* queue 2 weight */ ++ (QUEUE_WEIGHT_4 << 4) | /* queue 1 weight */ ++ (QUEUE_WEIGHT_2 << 0); /* queue 0 weight */ ++ ++#endif ++ /* ++ * STEP2: Ring scheduling configuration ++ */ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) ++ /* MIN_RATE_RATIO0=0, MAX_RATE_ULMT0=1, Weight0=1 */ ++ *(unsigned long *)SCH_Q01_CFG = (0 << 10) | (1<<14) | (0 << 12); ++ /* MIN_RATE_RATIO1=0, MAX_RATE_ULMT1=1, Weight1=4 */ ++ *(unsigned long *)SCH_Q01_CFG |= (0 << 26) | (1<<30) | (2 << 28); ++ ++ /* MIN_RATE_RATIO2=0, MAX_RATE_ULMT2=1, Weight0=1 */ ++ *(unsigned long *)SCH_Q23_CFG = (0 << 10) | (1<<14) | (0 << 12); ++ /* MIN_RATE_RATIO3=0, MAX_RATE_ULMT3=1, Weight1=4 */ ++ *(unsigned long *)SCH_Q23_CFG |= (0 << 26) | (1<<30) | (2 << 28); ++#else ++ *(unsigned long *)PDMA_SCH_CFG = (WRR_SCH << 24) | ++ (QUEUE_WEIGHT_16 << 12) | /* ring 3 weight */ ++ (QUEUE_WEIGHT_4 << 8) | /* ring 2 weight */ ++ (QUEUE_WEIGHT_16 << 4) | /* ring 1 weight */ ++ (QUEUE_WEIGHT_4 << 0); /* ring 0 weight */ ++#endif ++} ++ ++/* ++ * Routine Description : ++ * Bucket size and related information from ASIC Designer, ++ * please check Max Lee to update these values ++ * ++ * Related Registers ++ * FE_GLO_CFG - initialize clock rate for rate limiting ++ * PDMA_FC_CFG - Pause mechanism for Rings (Ref to pp116 in datasheet) ++ * : ++ * Parameter: ++ * NONE ++ */ ++/* ++ * Bit 29:24 - Q3 flow control pause condition ++ * Bit 21:16 - Q2 flow control pause condition ++ * Bit 13:8 - Q1 flow control pause condition ++ * Bit 5:0 - Q0 flow control pause condition ++ * ++ * detail bitmap - ++ * Bit[5] - Pause Qx when PSE p2 HQ full ++ * Bit[4] - Pause Qx when PSE p2 LQ full ++ * Bit[3] - Pause Qx when PSE p1 HQ full ++ * Bit[2] - Pause Qx when PSE p1 LQ full ++ * Bit[1] - Pause Qx when PSE p0 HQ full ++ * Bit[0] - Pause Qx when PSE p0 LQ full ++ */ ++void set_schedule_pause_condition(void) ++{ ++#if defined (CONFIG_RALINK_MT7620) ++ ++#elif defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ *(unsigned long *)SDM_TRING = (0xC << 28) | (0x3 << 24) | (0xC << 4) | 0x3; ++#else ++ /* ++ * STEP1: Set queue priority is high or low ++ * ++ * Set queue 3 as high queue in GMAC1/GMAC2 ++ */ ++ *(unsigned long *)GDMA1_FC_CFG = ((HIGH_QUEUE(3)|LOW_QUEUE(2) | ++ LOW_QUEUE(1)|LOW_QUEUE(0))<<24) | ++ (RSEV_PAGE_COUNT_HQ << 16) | ++ (RSEV_PAGE_COUNT_LQ <<8) | ++ VIQ_FC_ASRT | PAGES_SHARING; ++ ++ *(unsigned long *)GDMA2_FC_CFG = ((HIGH_QUEUE(3)|LOW_QUEUE(2) | ++ LOW_QUEUE(1)|LOW_QUEUE(0))<<24) | ++ (RSEV_PAGE_COUNT_HQ << 16) | ++ (RSEV_PAGE_COUNT_LQ <<8) | ++ VIQ_FC_ASRT | PAGES_SHARING; ++ ++ /* ++ * STEP2: Set flow control pause condition ++ * ++ * CPU always use queue 3, and queue3 is high queue. ++ * If P2(GMAC2) high queue is full, pause ring3/ring2 ++ * If P1(GMAC1) high queue is full, pause ring1/ring0 ++ */ ++ *(unsigned long *)PDMA_FC_CFG = ( PSE_P2_HQ_FULL << 24 ) | /* queue 3 */ ++ ( PSE_P2_HQ_FULL << 16 ) | /* queue 2 */ ++ ( PSE_P1_HQ_FULL << 8 ) | /* queue 1 */ ++ ( PSE_P1_HQ_FULL << 0 ); /* queue 0 */ ++#endif ++ ++} ++ ++ ++void set_output_shaper(void) ++{ ++#define GDMA1_TOKEN_RATE 16 /* unit=64bits/ms */ ++#define GDMA2_TOKEN_RATE 16 /* unit=64bits/ms */ ++ ++#if 0 ++ *(unsigned long *)GDMA1_SHPR_CFG = (1 << 24) | /* output shaper enable */ ++ (128 << 16) | /* bucket size (unit=1KB) */ ++ (GDMA1_TOKEN_RATE << 0); /* token rate (unit=8B/ms) */ ++#endif ++ ++#if 0 ++ *(unsigned long *)GDMA2_SHPR_CFG = (1 << 24) | /* output shaper enable */ ++ (128 << 16) | /* bucket size (unit=1KB) */ ++ (GDMA2_TOKEN_RATE << 0); /* token rate (unit=8B/ms) */ ++#endif ++} +diff --git a/drivers/net/ethernet/raeth/ra_qos.h b/drivers/net/ethernet/raeth/ra_qos.h +new file mode 100644 +index 0000000..7f2a8a1 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_qos.h +@@ -0,0 +1,18 @@ ++#ifndef RA_QOS_H ++#define RA_QOS_H ++ ++#include "ra2882ethreg.h" ++#define RING0 0 ++#define RING1 1 ++#define RING2 2 ++#define RING3 3 ++void get_tx_desc_and_dtx_idx(END_DEVICE* ei_local, int ring_no, unsigned long *tx_dtx_idx, struct PDMA_txdesc **tx_desc); ++int get_tx_ctx_idx(unsigned int ring_no, unsigned long *idx); ++int fe_tx_desc_init(struct net_device *dev, unsigned int ring_no, unsigned int qn, unsigned int pn); ++int fe_qos_packet_send(struct net_device *dev, struct sk_buff* skb, unsigned int ring_no, unsigned int qn, unsigned int pn); ++ ++int pkt_classifier(struct sk_buff *skb,int gmac_no, int *ring_no, int *queue_no, int *port_no); ++void set_schedule_pause_condition(void); ++void set_scheduler_weight(void); ++void set_output_shaper(void); ++#endif +diff --git a/drivers/net/ethernet/raeth/ra_rfrw.c b/drivers/net/ethernet/raeth/ra_rfrw.c +new file mode 100644 +index 0000000..d73db01 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_rfrw.c +@@ -0,0 +1,66 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ra2882ethreg.h" ++#include "raether.h" ++#include "ra_mac.h" ++ ++#define RF_CSR_CFG 0xb0180500 ++#define RF_CSR_KICK (1<<17) ++int rw_rf_reg(int write, int reg, int *data) ++{ ++ unsigned long rfcsr, i = 0; ++ ++ while (1) { ++ rfcsr = sysRegRead(RF_CSR_CFG); ++ if (! (rfcsr & (u32)RF_CSR_KICK) ) ++ break; ++ if (++i > 10000) { ++ printk("Warning: Abort rw rf register: too busy\n"); ++ return -1; ++ } ++ } ++ ++ rfcsr = (u32)(RF_CSR_KICK | ((reg&0x3f) << 8) | (*data & 0xff)); ++ if (write) ++ rfcsr |= 0x10000; ++ ++ sysRegRead(RF_CSR_CFG) = cpu_to_le32(rfcsr); ++ ++ i = 0; ++ while (1) { ++ rfcsr = sysRegRead(RF_CSR_CFG); ++ if (! (rfcsr & (u32)RF_CSR_KICK) ) ++ break; ++ if (++i > 10000) { ++ printk("Warning: still busy\n"); ++ return -1; ++ } ++ } ++ ++ rfcsr = sysRegRead(RF_CSR_CFG); ++ ++ if (((rfcsr&0x1f00) >> 8) != (reg & 0x1f)) { ++ printk("Error: rw register failed\n"); ++ return -1; ++ } ++ *data = (int)(rfcsr & 0xff); ++ ++ return 0; ++} ++ +diff --git a/drivers/net/ethernet/raeth/ra_rfrw.h b/drivers/net/ethernet/raeth/ra_rfrw.h +new file mode 100644 +index 0000000..da5a371 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/ra_rfrw.h +@@ -0,0 +1,6 @@ ++#ifndef RA_RFRW_H ++#define RA_RFRW_H ++ ++int rw_rf_reg(int write, int reg, int *data); ++ ++#endif +diff --git a/drivers/net/ethernet/raeth/raether.c b/drivers/net/ethernet/raeth/raether.c +new file mode 100644 +index 0000000..328285a +--- /dev/null ++++ b/drivers/net/ethernet/raeth/raether.c +@@ -0,0 +1,6401 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined (CONFIG_RAETH_TSO) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++#if defined (CONFIG_RAETH_LRO) ++#include ++#endif ++#include ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) ++#include ++#else ++#include ++#endif ++ ++#include "ra2882ethreg.h" ++#include "raether.h" ++#include "ra_mac.h" ++#include "ra_ioctl.h" ++#include "ra_rfrw.h" ++#ifdef CONFIG_RAETH_NETLINK ++#include "ra_netlink.h" ++#endif ++#if defined (CONFIG_RAETH_QOS) ++#include "ra_qos.h" ++#endif ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++#include "../../../net/nat/hw_nat/ra_nat.h" ++#endif ++#if defined(CONFIG_RAETH_PDMA_DVT) ++#include "dvt/raether_pdma_dvt.h" ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ ++static int fe_irq = 0; ++ ++#if defined (TASKLET_WORKQUEUE_SW) ++int init_schedule; ++int working_schedule; ++#endif ++ ++#ifdef CONFIG_RAETH_NAPI ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++static int raeth_clean(struct napi_struct *napi, int budget); ++#else ++static int raeth_clean(struct net_device *dev, int *budget); ++#endif ++ ++static int rt2880_eth_recv(struct net_device* dev, int *work_done, int work_to_do); ++#else ++static int rt2880_eth_recv(struct net_device* dev); ++#endif ++ ++#if !defined(CONFIG_RA_NAT_NONE) ++/* bruce+ ++ */ ++extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb); ++extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no); ++#endif ++ ++#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE) ++/* Qwert+ ++ */ ++#include ++extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle); ++extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle); ++#endif /* CONFIG_RA_CLASSIFIER */ ++ ++#if defined (CONFIG_RALINK_RT3052_MP2) ++int32_t mcast_rx(struct sk_buff * skb); ++int32_t mcast_tx(struct sk_buff * skb); ++#endif ++ ++int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf) ++{ ++ /* TODO */ ++ return 0; ++} ++ ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE) || defined (CONFIG_ARCH_MT7623) ++void setup_internal_gsw(void); ++#if defined (CONFIG_GE1_TRGMII_FORCE_1200) ++void apll_xtal_enable(void); ++#define REGBIT(x, n) (x << n) ++#endif ++#endif ++ ++#if defined (CONFIG_MT7623_FPGA) ++void setup_fpga_gsw(void); ++#endif ++ ++/* gmac driver feature set config */ ++#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS) ++#undef DELAY_INT ++#else ++#if defined (CONFIG_ARCH_MT7623) ++#undef DELAY_INT ++#else ++#define DELAY_INT 1 ++#endif ++#endif ++ ++//#define CONFIG_UNH_TEST ++/* end of config */ ++ ++#if defined (CONFIG_RAETH_JUMBOFRAME) ++#define MAX_RX_LENGTH 4096 ++#else ++#define MAX_RX_LENGTH 1536 ++#endif ++ ++struct net_device *dev_raether; ++ ++static int rx_dma_owner_idx; ++static int rx_dma_owner_idx0; ++#if defined (CONFIG_RAETH_HW_LRO) ++static int rx_dma_owner_lro1; ++static int rx_dma_owner_lro2; ++static int rx_dma_owner_lro3; ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++static int rx_dma_owner_idx1; ++#if defined(CONFIG_ARCH_MT7623) ++static int rx_dma_owner_idx2; ++static int rx_dma_owner_idx3; ++#endif /* CONFIG_ARCH_MT7623 */ ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++int rx_calc_idx1; ++#endif ++#endif ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++int rx_calc_idx0; ++#endif ++static int pending_recv; ++static struct PDMA_rxdesc *rx_ring; ++unsigned long tx_ring_full=0; ++ ++#if defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined(CONFIG_RALINK_MT7620) ++unsigned short p0_rx_good_cnt = 0; ++unsigned short p1_rx_good_cnt = 0; ++unsigned short p2_rx_good_cnt = 0; ++unsigned short p3_rx_good_cnt = 0; ++unsigned short p4_rx_good_cnt = 0; ++unsigned short p5_rx_good_cnt = 0; ++unsigned short p6_rx_good_cnt = 0; ++unsigned short p0_tx_good_cnt = 0; ++unsigned short p1_tx_good_cnt = 0; ++unsigned short p2_tx_good_cnt = 0; ++unsigned short p3_tx_good_cnt = 0; ++unsigned short p4_tx_good_cnt = 0; ++unsigned short p5_tx_good_cnt = 0; ++unsigned short p6_tx_good_cnt = 0; ++ ++unsigned short p0_rx_byte_cnt = 0; ++unsigned short p1_rx_byte_cnt = 0; ++unsigned short p2_rx_byte_cnt = 0; ++unsigned short p3_rx_byte_cnt = 0; ++unsigned short p4_rx_byte_cnt = 0; ++unsigned short p5_rx_byte_cnt = 0; ++unsigned short p6_rx_byte_cnt = 0; ++unsigned short p0_tx_byte_cnt = 0; ++unsigned short p1_tx_byte_cnt = 0; ++unsigned short p2_tx_byte_cnt = 0; ++unsigned short p3_tx_byte_cnt = 0; ++unsigned short p4_tx_byte_cnt = 0; ++unsigned short p5_tx_byte_cnt = 0; ++unsigned short p6_tx_byte_cnt = 0; ++ ++#if defined(CONFIG_RALINK_MT7620) ++unsigned short p7_rx_good_cnt = 0; ++unsigned short p7_tx_good_cnt = 0; ++ ++unsigned short p7_rx_byte_cnt = 0; ++unsigned short p7_tx_byte_cnt = 0; ++#endif ++#endif ++ ++ ++ ++ ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++#include "ra_ethtool.h" ++extern struct ethtool_ops ra_ethtool_ops; ++#ifdef CONFIG_PSEUDO_SUPPORT ++extern struct ethtool_ops ra_virt_ethtool_ops; ++#endif // CONFIG_PSEUDO_SUPPORT // ++#endif // (CONFIG_ETHTOOL // ++ ++#ifdef CONFIG_RALINK_VISTA_BASIC ++int is_switch_175c = 1; ++#endif ++ ++unsigned int M2Q_table[64] = {0}; ++unsigned int lan_wan_separate = 0; ++ ++#if defined(CONFIG_HW_SFQ) ++unsigned int web_sfq_enable = 0; ++EXPORT_SYMBOL(web_sfq_enable); ++#endif ++ ++EXPORT_SYMBOL(M2Q_table); ++EXPORT_SYMBOL(lan_wan_separate); ++#if defined (CONFIG_RAETH_LRO) ++unsigned int lan_ip; ++struct lro_para_struct lro_para; ++int lro_flush_needed; ++extern char const *nvram_get(int index, char *name); ++#endif ++ ++#define KSEG1 0xa0000000 ++#if defined (CONFIG_MIPS) ++#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1)) ++#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1) ++#else ++#define PHYS_TO_VIRT(x) phys_to_virt(x) ++#define VIRT_TO_PHYS(x) virt_to_phys(x) ++#endif ++ ++extern int fe_dma_init(struct net_device *dev); ++extern int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no); ++extern void ei_xmit_housekeeping(unsigned long unused); ++extern inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no); ++#if defined (CONFIG_RAETH_HW_LRO) ++extern int fe_hw_lro_init(struct net_device *dev); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if 0 ++void skb_dump(struct sk_buff* sk) { ++ unsigned int i; ++ ++ printk("skb_dump: from %s with len %d (%d) headroom=%d tailroom=%d\n", ++ sk->dev?sk->dev->name:"ip stack",sk->len,sk->truesize, ++ skb_headroom(sk),skb_tailroom(sk)); ++ ++ //for(i=(unsigned int)sk->head;i<=(unsigned int)sk->tail;i++) { ++ for(i=(unsigned int)sk->head;i<=(unsigned int)sk->data+20;i++) { ++ if((i % 20) == 0) ++ printk("\n"); ++ if(i==(unsigned int)sk->data) printk("{"); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21) ++ if(i==(unsigned int)sk->transport_header) printk("#"); ++ if(i==(unsigned int)sk->network_header) printk("|"); ++ if(i==(unsigned int)sk->mac_header) printk("*"); ++#else ++ if(i==(unsigned int)sk->h.raw) printk("#"); ++ if(i==(unsigned int)sk->nh.raw) printk("|"); ++ if(i==(unsigned int)sk->mac.raw) printk("*"); ++#endif ++ printk("%02X-",*((unsigned char*)i)); ++ if(i==(unsigned int)sk->tail) printk("}"); ++ } ++ printk("\n"); ++} ++#endif ++ ++ ++ ++#if defined (CONFIG_GIGAPHY) || defined (CONFIG_P5_MAC_TO_PHY_MODE) ++int isICPlusGigaPHY(int ge) ++{ ++ u32 phy_id0 = 0, phy_id1 = 0; ++ ++#ifdef CONFIG_GE2_RGMII_AN ++ if (ge == 2) { ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) { ++ printk("\n Read PhyID 1 is Fail!!\n"); ++ phy_id0 =0; ++ } ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) { ++ printk("\n Read PhyID 1 is Fail!!\n"); ++ phy_id1 = 0; ++ } ++ } ++ else ++#endif ++#if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ { ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) { ++ printk("\n Read PhyID 0 is Fail!!\n"); ++ phy_id0 =0; ++ } ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) { ++ printk("\n Read PhyID 0 is Fail!!\n"); ++ phy_id1 = 0; ++ } ++ } ++#endif ++ ++ if ((phy_id0 == EV_ICPLUS_PHY_ID0) && ((phy_id1 & 0xfff0) == EV_ICPLUS_PHY_ID1)) ++ return 1; ++ return 0; ++} ++ ++ ++int isMarvellGigaPHY(int ge) ++{ ++ u32 phy_id0 = 0, phy_id1 = 0; ++ ++#if defined (CONFIG_GE2_RGMII_AN) || defined (CONFIG_P4_MAC_TO_PHY_MODE) ++ if (ge == 2) { ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) { ++ printk("\n Read PhyID 1 is Fail!!\n"); ++ phy_id0 =0; ++ } ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) { ++ printk("\n Read PhyID 1 is Fail!!\n"); ++ phy_id1 = 0; ++ } ++ } ++ else ++#endif ++#if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ { ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) { ++ printk("\n Read PhyID 0 is Fail!!\n"); ++ phy_id0 =0; ++ } ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) { ++ printk("\n Read PhyID 0 is Fail!!\n"); ++ phy_id1 = 0; ++ } ++ } ++#endif ++ ; ++ if ((phy_id0 == EV_MARVELL_PHY_ID0) && (phy_id1 == EV_MARVELL_PHY_ID1)) ++ return 1; ++ return 0; ++} ++ ++int isVtssGigaPHY(int ge) ++{ ++ u32 phy_id0 = 0, phy_id1 = 0; ++ ++#if defined (CONFIG_GE2_RGMII_AN) || defined (CONFIG_P4_MAC_TO_PHY_MODE) ++ if (ge == 2) { ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 2, &phy_id0)) { ++ printk("\n Read PhyID 1 is Fail!!\n"); ++ phy_id0 =0; ++ } ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 3, &phy_id1)) { ++ printk("\n Read PhyID 1 is Fail!!\n"); ++ phy_id1 = 0; ++ } ++ } ++ else ++#endif ++#if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ { ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 2, &phy_id0)) { ++ printk("\n Read PhyID 0 is Fail!!\n"); ++ phy_id0 =0; ++ } ++ if (!mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 3, &phy_id1)) { ++ printk("\n Read PhyID 0 is Fail!!\n"); ++ phy_id1 = 0; ++ } ++ } ++#endif ++ ; ++ if ((phy_id0 == EV_VTSS_PHY_ID0) && (phy_id1 == EV_VTSS_PHY_ID1)) ++ return 1; ++ return 0; ++} ++#endif ++ ++/* ++ * Set the hardware MAC address. ++ */ ++static int ei_set_mac_addr(struct net_device *dev, void *p) ++{ ++ struct sockaddr *addr = p; ++ ++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ++ ++ if(netif_running(dev)) ++ return -EBUSY; ++ ++ ra2880MacAddressSet(addr->sa_data); ++ return 0; ++} ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++static int ei_set_mac2_addr(struct net_device *dev, void *p) ++{ ++ struct sockaddr *addr = p; ++ ++ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); ++ ++ if(netif_running(dev)) ++ return -EBUSY; ++ ++ ra2880Mac2AddressSet(addr->sa_data); ++ return 0; ++} ++#endif ++ ++void set_fe_dma_glo_cfg(void) ++{ ++ int dma_glo_cfg=0; ++#if defined (CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883) || \ ++ defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883) ++ int fe_glo_cfg=0; ++#endif ++ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) ++ dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_32DWORDS); ++#elif defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) ++ dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS); ++#elif defined (CONFIG_ARCH_MT7623) ++ dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS | ADMA_RX_BT_SIZE_32DWORDS); ++#else ++ dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_4DWORDS); ++#endif ++ ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ dma_glo_cfg |= (RX_2B_OFFSET); ++#endif ++ ++#if defined (CONFIG_32B_DESC) ++ dma_glo_cfg |= (DESC_32B_EN); ++#endif ++ sysRegWrite(DMA_GLO_CFG, dma_glo_cfg); ++#ifdef CONFIG_RAETH_QDMA ++ sysRegWrite(QDMA_GLO_CFG, dma_glo_cfg); ++#endif ++ ++ /* only the following chipset need to set it */ ++#if defined (CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883) || \ ++ defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883) ++ //set 1us timer count in unit of clock cycle ++ fe_glo_cfg = sysRegRead(FE_GLO_CFG); ++ fe_glo_cfg &= ~(0xff << 8); //clear bit8-bit15 ++ fe_glo_cfg |= (((get_surfboard_sysclk()/1000000)) << 8); ++ sysRegWrite(FE_GLO_CFG, fe_glo_cfg); ++#endif ++} ++ ++int forward_config(struct net_device *dev) ++{ ++ ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ ++ /* RT5350: No GDMA, PSE, CDMA, PPE */ ++ unsigned int sdmVal; ++ sdmVal = sysRegRead(SDM_CON); ++ ++#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD ++ sdmVal |= 0x7<<16; // UDPCS, TCPCS, IPCS=1 ++#endif // CONFIG_RAETH_CHECKSUM_OFFLOAD // ++ ++#if defined (CONFIG_RAETH_SPECIAL_TAG) ++ sdmVal |= 0x1<<20; // TCI_81XX ++#endif // CONFIG_RAETH_SPECIAL_TAG // ++ ++ sysRegWrite(SDM_CON, sdmVal); ++ ++#else //Non RT5350 chipset ++ ++ unsigned int regVal, regCsg; ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ unsigned int regVal2; ++#endif ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++#if defined(CONFIG_RALINK_MT7620) ++ /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */ ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x430) = 0x00010000; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x434) = 0x00030002; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x438) = 0x00050004; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x43C) = 0x00070006; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x440) = 0x00090008; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x444) = 0x000b000a; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x448) = 0x000d000c; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0x44C) = 0x000f000e; ++#else ++ /* ++ * VLAN_IDX 0 = VLAN_ID 0 ++ * ......... ++ * VLAN_IDX 15 = VLAN ID 15 ++ * ++ */ ++ /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */ ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xa8) = 0x00010000; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xac) = 0x00030002; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xb0) = 0x00050004; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xb4) = 0x00070006; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xb8) = 0x00090008; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xbc) = 0x000b000a; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xc0) = 0x000d000c; ++ *(unsigned long *)(RALINK_FRAME_ENGINE_BASE + 0xc4) = 0x000f000e; ++#endif ++#endif ++ ++ regVal = sysRegRead(GDMA1_FWD_CFG); ++ regCsg = sysRegRead(CDMA_CSG_CFG); ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ regVal2 = sysRegRead(GDMA2_FWD_CFG); ++#endif ++ ++ //set unicast/multicast/broadcast frame to cpu ++#if defined (CONFIG_RALINK_MT7620) ++ /* GDMA1 frames destination port is port0 CPU*/ ++ regVal &= ~0x7; ++#else ++ regVal &= ~0xFFFF; ++ regVal |= GDMA1_FWD_PORT; ++#endif ++ regCsg &= ~0x7; ++ ++#if defined (CONFIG_RAETH_SPECIAL_TAG) ++ regVal |= (1 << 24); //GDM1_TCI_81xx ++#endif ++ ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) ++ dev->features |= NETIF_F_HW_VLAN_TX; ++#else ++ dev->features |= NETIF_F_HW_VLAN_CTAG_TX; ++#endif ++#endif ++#ifdef CONFIG_RAETH_HW_VLAN_RX ++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) ++ dev->features |= NETIF_F_HW_VLAN_RX; ++#else ++ dev->features |= NETIF_F_HW_VLAN_CTAG_RX; ++#endif ++#endif ++ ++#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD ++ //enable ipv4 header checksum check ++ regVal |= GDM1_ICS_EN; ++ regCsg |= ICS_GEN_EN; ++ ++ //enable tcp checksum check ++ regVal |= GDM1_TCS_EN; ++ regCsg |= TCS_GEN_EN; ++ ++ //enable udp checksum check ++ regVal |= GDM1_UCS_EN; ++ regCsg |= UCS_GEN_EN; ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ regVal2 &= ~0xFFFF; ++ regVal2 |= GDMA2_FWD_PORT; ++ ++ regVal2 |= GDM1_ICS_EN; ++ regVal2 |= GDM1_TCS_EN; ++ regVal2 |= GDM1_UCS_EN; ++#endif ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ dev->features |= NETIF_F_HW_CSUM; ++#else ++ dev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4 */ ++#endif /* CONFIG_RAETH_HW_LRO */ ++//#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0) ++// dev->vlan_features |= NETIF_F_IP_CSUM; ++//#endif ++ ++#if defined(CONFIG_RALINK_MT7620) ++#if defined (CONFIG_RAETH_TSO) ++ if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) { ++ dev->features |= NETIF_F_SG; ++ dev->features |= NETIF_F_TSO; ++ } ++#endif // CONFIG_RAETH_TSO // ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) { ++ dev->features |= NETIF_F_TSO6; ++ dev->features |= NETIF_F_IPV6_CSUM; /* Can checksum TCP/UDP over IPv6 */ ++ } ++#endif // CONFIG_RAETH_TSOV6 // ++#else ++#if defined (CONFIG_RAETH_TSO) ++ dev->features |= NETIF_F_SG; ++ dev->features |= NETIF_F_TSO; ++#endif // CONFIG_RAETH_TSO // ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ dev->features |= NETIF_F_TSO6; ++ dev->features |= NETIF_F_IPV6_CSUM; /* Can checksum TCP/UDP over IPv6 */ ++#endif // CONFIG_RAETH_TSOV6 // ++#endif // CONFIG_RALINK_MT7620 // ++#else // Checksum offload disabled ++ ++ //disable ipv4 header checksum check ++ regVal &= ~GDM1_ICS_EN; ++ regCsg &= ~ICS_GEN_EN; ++ ++ //disable tcp checksum check ++ regVal &= ~GDM1_TCS_EN; ++ regCsg &= ~TCS_GEN_EN; ++ ++ //disable udp checksum check ++ regVal &= ~GDM1_UCS_EN; ++ regCsg &= ~UCS_GEN_EN; ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ regVal2 &= ~GDM1_ICS_EN; ++ regVal2 &= ~GDM1_TCS_EN; ++ regVal2 &= ~GDM1_UCS_EN; ++#endif ++ ++ dev->features &= ~NETIF_F_IP_CSUM; /* disable checksum TCP/UDP over IPv4 */ ++#endif // CONFIG_RAETH_CHECKSUM_OFFLOAD // ++ ++#ifdef CONFIG_RAETH_JUMBOFRAME ++ regVal |= GDM1_JMB_EN; ++#ifdef CONFIG_PSEUDO_SUPPORT ++ regVal2 |= GDM1_JMB_EN; ++#endif ++#endif ++ ++ sysRegWrite(GDMA1_FWD_CFG, regVal); ++ sysRegWrite(CDMA_CSG_CFG, regCsg); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ sysRegWrite(GDMA2_FWD_CFG, regVal2); ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0) ++ dev->vlan_features = dev->features; ++#endif ++ ++/* ++ * PSE_FQ_CFG register definition - ++ * ++ * Define max free queue page count in PSE. (31:24) ++ * RT2883/RT3883 - 0xff908000 (255 pages) ++ * RT3052 - 0x80504000 (128 pages) ++ * RT2880 - 0x80504000 (128 pages) ++ * ++ * In each page, there are 128 bytes in each page. ++ * ++ * 23:16 - free queue flow control release threshold ++ * 15:8 - free queue flow control assertion threshold ++ * 7:0 - free queue empty threshold ++ * ++ * The register affects QOS correctness in frame engine! ++ */ ++ ++#if defined(CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883) ++ sysRegWrite(PSE_FQ_CFG, cpu_to_le32(INIT_VALUE_OF_RT2883_PSE_FQ_CFG)); ++#elif defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350) || \ ++ defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \ ++ defined (CONFIG_RALINK_MT7628) || defined(CONFIG_ARCH_MT7623) ++ /*use default value*/ ++#else ++ sysRegWrite(PSE_FQ_CFG, cpu_to_le32(INIT_VALUE_OF_PSE_FQFC_CFG)); ++#endif ++ ++ /* ++ *FE_RST_GLO register definition - ++ *Bit 0: PSE Rest ++ *Reset PSE after re-programming PSE_FQ_CFG. ++ */ ++ regVal = 0x1; ++ sysRegWrite(FE_RST_GL, regVal); ++ sysRegWrite(FE_RST_GL, 0); // update for RSTCTL issue ++ ++ regCsg = sysRegRead(CDMA_CSG_CFG); ++ printk("CDMA_CSG_CFG = %0X\n",regCsg); ++ regVal = sysRegRead(GDMA1_FWD_CFG); ++ printk("GDMA1_FWD_CFG = %0X\n",regVal); ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ regVal = sysRegRead(GDMA2_FWD_CFG); ++ printk("GDMA2_FWD_CFG = %0X\n",regVal); ++#endif ++#endif ++ return 1; ++} ++ ++#ifdef CONFIG_RAETH_LRO ++static int ++rt_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph, ++ u64 *hdr_flags, void *priv) ++{ ++ struct iphdr *iph = NULL; ++ int vhdr_len = 0; ++ ++ /* ++ * Make sure that this packet is Ethernet II, is not VLAN ++ * tagged, is IPv4, has a valid IP header, and is TCP. ++ */ ++ if (skb->protocol == 0x0081) { ++ vhdr_len = VLAN_HLEN; ++ } ++ ++ iph = (struct iphdr *)(skb->data + vhdr_len); ++ if (iph->daddr != lro_para.lan_ip1) { ++ return -1; ++ } ++ ++ if(iph->protocol != IPPROTO_TCP) { ++ return -1; ++ } else { ++ *iphdr = iph; ++ *tcph = skb->data + (iph->ihl << 2) + vhdr_len; ++ *hdr_flags = LRO_IPV4 | LRO_TCP; ++ ++ lro_flush_needed = 1; ++ return 0; ++ } ++} ++#endif // CONFIG_RAETH_LRO // ++ ++#ifdef CONFIG_RAETH_NAPI ++static int rt2880_eth_recv(struct net_device* dev, int *work_done, int work_to_do) ++#else ++static int rt2880_eth_recv(struct net_device* dev) ++#endif ++{ ++ struct sk_buff *skb, *rx_skb; ++ unsigned int length = 0; ++ unsigned long RxProcessed; ++ ++ int bReschedule = 0; ++ END_DEVICE* ei_local = netdev_priv(dev); ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) || defined (CONFIG_RAETH_HW_LRO) ++ int rx_ring_no=0; ++#endif ++ ++#if defined (CONFIG_RAETH_SPECIAL_TAG) ++ struct vlan_ethhdr *veth=NULL; ++#endif ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ PSEUDO_ADAPTER *pAd; ++#endif ++ ++ RxProcessed = 0; ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_dma_owner_idx0 = (rx_calc_idx0 + 1) % NUM_RX_DESC; ++#else ++ rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC; ++#endif ++ ++#if defined (CONFIG_32B_DESC) ++ dma_cache_sync(NULL, &ei_local->rx_ring0[rx_dma_owner_idx0], sizeof(struct PDMA_rxdesc), DMA_FROM_DEVICE); ++#endif ++#if defined (CONFIG_RAETH_HW_LRO) ++ rx_dma_owner_lro1 = (sysRegRead(RX_CALC_IDX1) + 1) % NUM_LRO_RX_DESC; ++ rx_dma_owner_lro2 = (sysRegRead(RX_CALC_IDX2) + 1) % NUM_LRO_RX_DESC; ++ rx_dma_owner_lro3 = (sysRegRead(RX_CALC_IDX3) + 1) % NUM_LRO_RX_DESC; ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_dma_owner_idx1 = (rx_calc_idx1 + 1) % NUM_RX_DESC; ++#else ++ rx_dma_owner_idx1 = (sysRegRead(RX_CALC_IDX1) + 1) % NUM_RX_DESC; ++#endif /* CONFIG_RAETH_RW_PDMAPTR_FROM_VAR */ ++#if defined(CONFIG_ARCH_MT7623) ++ rx_dma_owner_idx2 = (sysRegRead(RX_CALC_IDX2) + 1) % NUM_RX_DESC; ++ rx_dma_owner_idx3 = (sysRegRead(RX_CALC_IDX3) + 1) % NUM_RX_DESC; ++#endif ++#if defined (CONFIG_32B_DESC) ++ dma_cache_sync(NULL, &ei_local->rx_ring1[rx_dma_owner_idx1], sizeof(struct PDMA_rxdesc), DMA_FROM_DEVICE); ++#endif ++#endif ++ for ( ; ; ) { ++ ++ ++#ifdef CONFIG_RAETH_NAPI ++ if(*work_done >= work_to_do) ++ break; ++ (*work_done)++; ++#else ++ if (RxProcessed++ > NUM_RX_MAX_PROCESS) ++ { ++ // need to reschedule rx handle ++ bReschedule = 1; ++ break; ++ } ++#endif ++ ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ if (ei_local->rx_ring3[rx_dma_owner_lro3].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring3; ++ rx_dma_owner_idx = rx_dma_owner_lro3; ++ // printk("rx_dma_owner_lro3=%x\n",rx_dma_owner_lro3); ++ rx_ring_no=3; ++ } ++ else if (ei_local->rx_ring2[rx_dma_owner_lro2].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring2; ++ rx_dma_owner_idx = rx_dma_owner_lro2; ++ // printk("rx_dma_owner_lro2=%x\n",rx_dma_owner_lro2); ++ rx_ring_no=2; ++ } ++ else if (ei_local->rx_ring1[rx_dma_owner_lro1].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring1; ++ rx_dma_owner_idx = rx_dma_owner_lro1; ++ // printk("rx_dma_owner_lro1=%x\n",rx_dma_owner_lro1); ++ rx_ring_no=1; ++ } ++ else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring0; ++ rx_dma_owner_idx = rx_dma_owner_idx0; ++ // printk("rx_dma_owner_idx0=%x\n",rx_dma_owner_idx0); ++ rx_ring_no=0; ++ } else { ++ break; ++ } ++ #if defined (CONFIG_RAETH_HW_LRO_DBG) ++ HwLroStatsUpdate(rx_ring_no, rx_ring[rx_dma_owner_idx].rxd_info2.LRO_AGG_CNT, \ ++ (rx_ring[rx_dma_owner_idx].rxd_info2.PLEN1 << 14) | rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0); ++ #endif ++ #if defined(CONFIG_RAETH_HW_LRO_REASON_DBG) ++ HwLroFlushStatsUpdate(rx_ring_no, rx_ring[rx_dma_owner_idx].rxd_info2.REV); ++ #endif ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++ if (ei_local->rx_ring1[rx_dma_owner_idx1].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring1; ++ rx_dma_owner_idx = rx_dma_owner_idx1; ++ // printk("rx_dma_owner_idx1=%x\n",rx_dma_owner_idx1); ++ rx_ring_no=1; ++ } ++#if defined(CONFIG_ARCH_MT7623) ++ else if (ei_local->rx_ring2[rx_dma_owner_idx2].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring2; ++ rx_dma_owner_idx = rx_dma_owner_idx2; ++ // printk("rx_dma_owner_idx2=%x\n",rx_dma_owner_idx2); ++ rx_ring_no=2; ++ } ++ else if (ei_local->rx_ring3[rx_dma_owner_idx3].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring3; ++ rx_dma_owner_idx = rx_dma_owner_idx3; ++ // printk("rx_dma_owner_idx3=%x\n",rx_dma_owner_idx3); ++ rx_ring_no=3; ++ } ++#endif /* CONFIG_ARCH_MT7623 */ ++ else if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring0; ++ rx_dma_owner_idx = rx_dma_owner_idx0; ++ // printk("rx_dma_owner_idx0=%x\n",rx_dma_owner_idx0); ++ rx_ring_no=0; ++ } else { ++ break; ++ } ++#else ++ ++ if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) { ++ rx_ring = ei_local->rx_ring0; ++ rx_dma_owner_idx = rx_dma_owner_idx0; ++ } else { ++ break; ++ } ++#endif ++ ++#if defined (CONFIG_32B_DESC) ++ prefetch(&rx_ring[(rx_dma_owner_idx + 1) % NUM_RX_DESC]); ++#endif ++ /* skb processing */ ++#if defined (CONFIG_RAETH_HW_LRO) ++ length = (rx_ring[rx_dma_owner_idx].rxd_info2.PLEN1 << 14) | rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0; ++#else ++ length = rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0; ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if defined (CONFIG_ARCH_MT7623) ++ dma_unmap_single(NULL, rx_ring[rx_dma_owner_idx].rxd_info1.PDP0, length, DMA_FROM_DEVICE); ++#endif ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ if(rx_ring_no==3) { ++ rx_skb = ei_local->netrx3_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx3_skbuf[rx_dma_owner_idx]->data; ++ } ++ else if(rx_ring_no==2) { ++ rx_skb = ei_local->netrx2_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx2_skbuf[rx_dma_owner_idx]->data; ++ } ++ else if(rx_ring_no==1) { ++ rx_skb = ei_local->netrx1_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx1_skbuf[rx_dma_owner_idx]->data; ++ } ++ else { ++ rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data; ++ } ++ #if defined(CONFIG_RAETH_PDMA_DVT) ++ raeth_pdma_lro_dvt( rx_ring_no, ei_local, rx_dma_owner_idx ); ++ #endif /* CONFIG_RAETH_PDMA_DVT */ ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++ if(rx_ring_no==1) { ++ rx_skb = ei_local->netrx1_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx1_skbuf[rx_dma_owner_idx]->data; ++ } ++#if defined(CONFIG_ARCH_MT7623) ++ else if(rx_ring_no==2) { ++ rx_skb = ei_local->netrx2_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx2_skbuf[rx_dma_owner_idx]->data; ++ } ++ else if(rx_ring_no==3) { ++ rx_skb = ei_local->netrx3_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx3_skbuf[rx_dma_owner_idx]->data; ++ } ++#endif /* CONFIG_ARCH_MT7623 */ ++ else { ++ rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data; ++ } ++ #if defined(CONFIG_RAETH_PDMA_DVT) ++ raeth_pdma_lro_dvt( rx_ring_no, ei_local, rx_dma_owner_idx ); ++ #endif /* CONFIG_RAETH_PDMA_DVT */ ++#else ++ rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx]; ++ rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data; ++ #if defined(CONFIG_RAETH_PDMA_DVT) ++ raeth_pdma_rx_desc_dvt( ei_local, rx_dma_owner_idx0 ); ++ #endif /* CONFIG_RAETH_PDMA_DVT */ ++#endif ++ rx_skb->len = length; ++/*TODO*/ ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ rx_skb->data += NET_IP_ALIGN; ++#endif ++ rx_skb->tail = rx_skb->data + length; ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if(rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) { ++ if(ei_local->PseudoDev!=NULL) { ++ rx_skb->dev = ei_local->PseudoDev; ++ rx_skb->protocol = eth_type_trans(rx_skb,ei_local->PseudoDev); ++ }else { ++ printk("ERROR: PseudoDev is still not initialize but receive packet from GMAC2\n"); ++ } ++ }else{ ++ rx_skb->dev = dev; ++ rx_skb->protocol = eth_type_trans(rx_skb,dev); ++ } ++#else ++ rx_skb->dev = dev; ++ rx_skb->protocol = eth_type_trans(rx_skb,dev); ++#endif ++ ++#ifdef CONFIG_RAETH_CHECKSUM_OFFLOAD ++#if defined (CONFIG_PDMA_NEW) ++ if(rx_ring[rx_dma_owner_idx].rxd_info4.L4VLD) { ++ rx_skb->ip_summed = CHECKSUM_UNNECESSARY; ++ }else { ++ rx_skb->ip_summed = CHECKSUM_NONE; ++ } ++#else ++ if(rx_ring[rx_dma_owner_idx].rxd_info4.IPFVLD_bit) { ++ rx_skb->ip_summed = CHECKSUM_UNNECESSARY; ++ }else { ++ rx_skb->ip_summed = CHECKSUM_NONE; ++ } ++#endif ++#else ++ rx_skb->ip_summed = CHECKSUM_NONE; ++#endif ++ ++#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE) ++ /* Qwert+ ++ */ ++ if(ra_classifier_hook_rx!= NULL) ++ { ++#if defined(CONFIG_RALINK_EXTERNAL_TIMER) ++ ra_classifier_hook_rx(rx_skb, (*((volatile u32 *)(0xB0000D08))&0x0FFFF)); ++#else ++ ra_classifier_hook_rx(rx_skb, read_c0_count()); ++#endif ++ } ++#endif /* CONFIG_RA_CLASSIFIER */ ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(ra_sw_nat_hook_rx != NULL) { ++ FOE_MAGIC_TAG(rx_skb)= FOE_MAGIC_GE; ++ *(uint32_t *)(FOE_INFO_START_ADDR(rx_skb)+2) = *(uint32_t *)&rx_ring[rx_dma_owner_idx].rxd_info4; ++ FOE_ALG(rx_skb) = 0; ++ } ++#endif ++ ++ /* We have to check the free memory size is big enough ++ * before pass the packet to cpu*/ ++#if defined (CONFIG_RAETH_SKB_RECYCLE_2K) ++#if defined (CONFIG_RAETH_HW_LRO) ++ if( rx_ring != ei_local->rx_ring0 ) ++ skb = __dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC); ++ else ++#endif /* CONFIG_RAETH_HW_LRO */ ++ skb = skbmgr_dev_alloc_skb2k(); ++#else ++#if defined (CONFIG_RAETH_HW_LRO) ++ if( rx_ring != ei_local->rx_ring0 ) ++ skb = __dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC); ++ else ++#endif /* CONFIG_RAETH_HW_LRO */ ++ skb = __dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC); ++#endif ++ ++ if (unlikely(skb == NULL)) ++ { ++ printk(KERN_ERR "skb not available...\n"); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) { ++ if (ei_local->PseudoDev != NULL) { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.rx_dropped++; ++ } ++ } else ++#endif ++ ei_local->stat.rx_dropped++; ++ bReschedule = 1; ++ break; ++ } ++#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ skb_reserve(skb, NET_IP_ALIGN); ++#endif ++ ++#if defined (CONFIG_RAETH_SPECIAL_TAG) ++ // port0: 0x8100 => 0x8100 0001 ++ // port1: 0x8101 => 0x8100 0002 ++ // port2: 0x8102 => 0x8100 0003 ++ // port3: 0x8103 => 0x8100 0004 ++ // port4: 0x8104 => 0x8100 0005 ++ // port5: 0x8105 => 0x8100 0006 ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,21) ++ veth = (struct vlan_ethhdr *)(rx_skb->mac_header); ++#else ++ veth = (struct vlan_ethhdr *)(rx_skb->mac.raw); ++#endif ++ /*donot check 0x81 due to MT7530 SPEC*/ ++ //if((veth->h_vlan_proto & 0xFF) == 0x81) ++ { ++ veth->h_vlan_TCI = htons( (((veth->h_vlan_proto >> 8) & 0xF) + 1) ); ++ rx_skb->protocol = veth->h_vlan_proto = htons(ETH_P_8021Q); ++ } ++#endif ++ ++/* ra_sw_nat_hook_rx return 1 --> continue ++ * ra_sw_nat_hook_rx return 0 --> FWD & without netif_rx ++ */ ++#if !defined(CONFIG_RA_NAT_NONE) ++ if((ra_sw_nat_hook_rx == NULL) || ++ (ra_sw_nat_hook_rx!= NULL && ra_sw_nat_hook_rx(rx_skb))) ++#endif ++ { ++#if defined (CONFIG_RALINK_RT3052_MP2) ++ if(mcast_rx(rx_skb)==0) { ++ kfree_skb(rx_skb); ++ }else ++#endif ++#if defined (CONFIG_RAETH_LRO) ++ if (rx_skb->ip_summed == CHECKSUM_UNNECESSARY) { ++ lro_receive_skb(&ei_local->lro_mgr, rx_skb, NULL); ++ //LroStatsUpdate(&ei_local->lro_mgr,0); ++ } else ++#endif ++#ifdef CONFIG_RAETH_NAPI ++ netif_receive_skb(rx_skb); ++#else ++#ifdef CONFIG_RAETH_HW_VLAN_RX ++ if(ei_local->vlgrp && rx_ring[rx_dma_owner_idx].rxd_info2.TAG) { ++ vlan_hwaccel_rx(rx_skb, ei_local->vlgrp, rx_ring[rx_dma_owner_idx].rxd_info3.VID); ++ } else { ++ netif_rx(rx_skb); ++ } ++#else ++#ifdef CONFIG_RAETH_CPU_LOOPBACK ++ skb_push(rx_skb,ETH_HLEN); ++ ei_start_xmit(rx_skb, dev, 1); ++#else ++ netif_rx(rx_skb); ++#endif ++#endif ++#endif ++ } ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (rx_ring[rx_dma_owner_idx].rxd_info4.SP == 2) { ++ if (ei_local->PseudoDev != NULL) { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.rx_packets++; ++ pAd->stat.rx_bytes += length; ++ } ++ } else ++#endif ++ { ++ ei_local->stat.rx_packets++; ++ ei_local->stat.rx_bytes += length; ++ } ++ ++ ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++#if defined (CONFIG_RAETH_HW_LRO) ++ if( rx_ring != ei_local->rx_ring0 ){ ++ rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH); ++ rx_ring[rx_dma_owner_idx].rxd_info2.PLEN1 = SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14); ++ } ++ else ++#endif /* CONFIG_RAETH_HW_LRO */ ++ rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++ rx_ring[rx_dma_owner_idx].rxd_info2.LS0 = 0; ++#endif ++ rx_ring[rx_dma_owner_idx].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_HW_LRO) ++ if( rx_ring != ei_local->rx_ring0 ) ++ rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_LRO_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ else ++#endif /* CONFIG_RAETH_HW_LRO */ ++ rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++#ifdef CONFIG_32B_DESC ++ dma_cache_sync(NULL, &rx_ring[rx_dma_owner_idx], sizeof(struct PDMA_rxdesc), DMA_TO_DEVICE); ++#endif ++ /* Move point to next RXD which wants to alloc*/ ++#if defined (CONFIG_RAETH_HW_LRO) ++ if(rx_ring_no==3) { ++ sysRegWrite(RAETH_RX_CALC_IDX3, rx_dma_owner_idx); ++ ei_local->netrx3_skbuf[rx_dma_owner_idx] = skb; ++ } ++ else if(rx_ring_no==2) { ++ sysRegWrite(RAETH_RX_CALC_IDX2, rx_dma_owner_idx); ++ ei_local->netrx2_skbuf[rx_dma_owner_idx] = skb; ++ } ++ else if(rx_ring_no==1) { ++ sysRegWrite(RAETH_RX_CALC_IDX1, rx_dma_owner_idx); ++ ei_local->netrx1_skbuf[rx_dma_owner_idx] = skb; ++ } ++ else if(rx_ring_no==0) { ++ sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx); ++ ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb; ++ } ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++ if(rx_ring_no==0) { ++ sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx); ++ ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb; ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = rx_dma_owner_idx; ++#endif ++ } ++#if defined(CONFIG_ARCH_MT7623) ++ else if(rx_ring_no==3) { ++ sysRegWrite(RAETH_RX_CALC_IDX3, rx_dma_owner_idx); ++ ei_local->netrx3_skbuf[rx_dma_owner_idx] = skb; ++ } ++ else if(rx_ring_no==2) { ++ sysRegWrite(RAETH_RX_CALC_IDX2, rx_dma_owner_idx); ++ ei_local->netrx2_skbuf[rx_dma_owner_idx] = skb; ++ } ++#endif /* CONFIG_ARCH_MT7623 */ ++ else { ++ sysRegWrite(RAETH_RX_CALC_IDX1, rx_dma_owner_idx); ++ ei_local->netrx1_skbuf[rx_dma_owner_idx] = skb; ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx1 = rx_dma_owner_idx; ++#endif ++ } ++#else ++ sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx); ++ ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb; ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = rx_dma_owner_idx; ++#endif ++#endif ++ ++ ++ /* Update to Next packet point that was received. ++ */ ++#if defined (CONFIG_RAETH_HW_LRO) ++ if(rx_ring_no==3) ++ rx_dma_owner_lro3 = (sysRegRead(RAETH_RX_CALC_IDX3) + 1) % NUM_LRO_RX_DESC; ++ else if(rx_ring_no==2) ++ rx_dma_owner_lro2 = (sysRegRead(RAETH_RX_CALC_IDX2) + 1) % NUM_LRO_RX_DESC; ++ else if(rx_ring_no==1) ++ rx_dma_owner_lro1 = (sysRegRead(RAETH_RX_CALC_IDX1) + 1) % NUM_LRO_RX_DESC; ++ else if(rx_ring_no==0) ++ rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC; ++ else { ++ } ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++ if(rx_ring_no==0) { ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_dma_owner_idx0 = (rx_dma_owner_idx + 1) % NUM_RX_DESC; ++#else ++ rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC; ++#endif ++#if defined(CONFIG_ARCH_MT7623) ++ }else if(rx_ring_no==3) { ++ rx_dma_owner_idx3 = (sysRegRead(RAETH_RX_CALC_IDX3) + 1) % NUM_RX_DESC; ++ }else if(rx_ring_no==2) { ++ rx_dma_owner_idx2 = (sysRegRead(RAETH_RX_CALC_IDX2) + 1) % NUM_RX_DESC; ++#endif /* CONFIG_ARCH_MT7623 */ ++ }else { ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_dma_owner_idx1 = (rx_dma_owner_idx + 1) % NUM_RX_DESC; ++#else ++ rx_dma_owner_idx1 = (sysRegRead(RAETH_RX_CALC_IDX1) + 1) % NUM_RX_DESC; ++#endif ++ } ++#else ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_dma_owner_idx0 = (rx_dma_owner_idx + 1) % NUM_RX_DESC; ++#else ++ rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC; ++#endif ++#endif ++ } /* for */ ++ ++#if defined (CONFIG_RAETH_LRO) ++ if (lro_flush_needed) { ++ //LroStatsUpdate(&ei_local->lro_mgr,1); ++ lro_flush_all(&ei_local->lro_mgr); ++ lro_flush_needed = 0; ++ } ++#endif ++ return bReschedule; ++} ++ ++ ++/////////////////////////////////////////////////////////////////// ++///// ++///// ra_get_stats - gather packet information for management plane ++///// ++///// Pass net_device_stats to the upper layer. ++///// ++///// ++///// RETURNS: pointer to net_device_stats ++/////////////////////////////////////////////////////////////////// ++ ++struct net_device_stats *ra_get_stats(struct net_device *dev) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev); ++ return &ei_local->stat; ++} ++ ++#if defined (CONFIG_RT_3052_ESW) ++void kill_sig_workq(struct work_struct *work) ++{ ++ struct file *fp; ++ char pid[8]; ++ struct task_struct *p = NULL; ++ ++ //read udhcpc pid from file, and send signal USR2,USR1 to get a new IP ++ fp = filp_open("/var/run/udhcpc.pid", O_RDONLY, 0); ++ if (IS_ERR(fp)) ++ return; ++ ++ if (fp->f_op && fp->f_op->read) { ++ if (fp->f_op->read(fp, pid, 8, &fp->f_pos) > 0) { ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ p = pid_task(find_get_pid(simple_strtoul(pid, NULL, 10)), PIDTYPE_PID); ++#else ++ p = find_task_by_pid(simple_strtoul(pid, NULL, 10)); ++#endif ++ ++ if (NULL != p) { ++ send_sig(SIGUSR2, p, 0); ++ send_sig(SIGUSR1, p, 0); ++ } ++ } ++ } ++ filp_close(fp, NULL); ++ ++} ++#endif ++ ++ ++/////////////////////////////////////////////////////////////////// ++///// ++///// ra2880Recv - process the next incoming packet ++///// ++///// Handle one incoming packet. The packet is checked for errors and sent ++///// to the upper layer. ++///// ++///// RETURNS: OK on success or ERROR. ++/////////////////////////////////////////////////////////////////// ++ ++#ifndef CONFIG_RAETH_NAPI ++#if defined WORKQUEUE_BH || defined (TASKLET_WORKQUEUE_SW) ++void ei_receive_workq(struct work_struct *work) ++#else ++void ei_receive(unsigned long unused) // device structure ++#endif // WORKQUEUE_BH // ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned long reg_int_mask=0; ++ int bReschedule=0; ++ ++ ++ if(tx_ring_full==0){ ++ bReschedule = rt2880_eth_recv(dev); ++ if(bReschedule) ++ { ++#ifdef WORKQUEUE_BH ++ schedule_work(&ei_local->rx_wq); ++#else ++#if defined (TASKLET_WORKQUEUE_SW) ++ if (working_schedule == 1) ++ schedule_work(&ei_local->rx_wq); ++ else ++#endif ++ tasklet_hi_schedule(&ei_local->rx_tasklet); ++#endif // WORKQUEUE_BH // ++ }else{ ++ reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE); ++#if defined(DELAY_INT) ++ sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT); ++#else ++ sysRegWrite(RAETH_FE_INT_ENABLE, (reg_int_mask | RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3)); ++#endif ++#ifdef CONFIG_RAETH_QDMA ++ reg_int_mask=sysRegRead(QFE_INT_ENABLE); ++#if defined(DELAY_INT) ++ sysRegWrite(QFE_INT_ENABLE, reg_int_mask| RX_DLY_INT); ++#else ++ sysRegWrite(QFE_INT_ENABLE, (reg_int_mask | RX_DONE_INT0 | RX_DONE_INT1)); ++#endif ++ ++#endif ++ ++ } ++ }else{ ++#ifdef WORKQUEUE_BH ++ schedule_work(&ei_local->rx_wq); ++#else ++#if defined (TASKLET_WORKQUEUE_SW) ++ if (working_schedule == 1) ++ schedule_work(&ei_local->rx_wq); ++ else ++#endif ++ tasklet_schedule(&ei_local->rx_tasklet); ++#endif // WORKQUEUE_BH // ++ } ++} ++#endif ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++void ei_hw_lro_auto_adj(unsigned int index, END_DEVICE* ei_local) ++{ ++ unsigned int entry; ++ unsigned int pkt_cnt; ++ unsigned int tick_cnt; ++ unsigned int duration_us; ++ unsigned int byte_cnt; ++ ++ /* read packet count statitics of the auto-learn table */ ++ entry = index + 68; ++ sysRegWrite( PDMA_FE_ALT_CF8, entry ); ++ pkt_cnt = sysRegRead(PDMA_FE_ALT_SGL_CFC) & 0xfff; ++ tick_cnt = (sysRegRead(PDMA_FE_ALT_SGL_CFC) >> 16) & 0xffff; ++#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG) ++ printk("[HW LRO] ei_hw_lro_auto_adj(): pkt_cnt[%d]=%d, tick_cnt[%d]=%d\n", index, pkt_cnt, index, tick_cnt); ++ printk("[HW LRO] ei_hw_lro_auto_adj(): packet_interval[%d]=%d (ticks/pkt)\n", index, tick_cnt/pkt_cnt); ++#endif ++ ++ /* read byte count statitics of the auto-learn table */ ++ entry = index + 64; ++ sysRegWrite( PDMA_FE_ALT_CF8, entry ); ++ byte_cnt = sysRegRead(PDMA_FE_ALT_SGL_CFC); ++#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG) ++ printk("[HW LRO] ei_hw_lro_auto_adj(): byte_cnt[%d]=%d\n", index, byte_cnt); ++#endif ++ ++ /* calculate the packet interval of the rx flow */ ++ duration_us = tick_cnt * HW_LRO_TIMER_UNIT; ++ ei_local->hw_lro_pkt_interval[index - 1] = (duration_us/pkt_cnt) * ei_local->hw_lro_alpha / 100; ++#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG) ++ printk("[HW LRO] ei_hw_lro_auto_adj(): packet_interval[%d]=%d (20us)\n", index, duration_us/pkt_cnt); ++#endif ++ ++ if ( !ei_local->hw_lro_fix_setting ){ ++ /* adjust age_time, agg_time for the lro ring */ ++ if(ei_local->hw_lro_pkt_interval[index - 1] > 0){ ++ SET_PDMA_RXRING_AGE_TIME(index, (ei_local->hw_lro_pkt_interval[index - 1] * HW_LRO_MAX_AGG_CNT)); ++ SET_PDMA_RXRING_AGG_TIME(index, (ei_local->hw_lro_pkt_interval[index - 1] * HW_LRO_AGG_DELTA)); ++ } ++ else{ ++ SET_PDMA_RXRING_AGE_TIME(index, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_AGG_TIME(index, HW_LRO_AGG_DELTA); ++ } ++ } ++} ++ ++void ei_hw_lro_workq(struct work_struct *work) ++{ ++ END_DEVICE *ei_local; ++ unsigned int reg_int_val; ++ unsigned int reg_int_mask; ++ ++ ei_local = container_of(work, struct end_device, hw_lro_wq); ++ ++ reg_int_val = sysRegRead(RAETH_FE_INT_STATUS); ++#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG) ++ printk("[HW LRO] ei_hw_lro_workq(): RAETH_FE_INT_STATUS=0x%x\n", reg_int_val); ++#endif ++ if((reg_int_val & ALT_RPLC_INT3)){ ++#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG) ++ printk("[HW LRO] ALT_RPLC_INT3 occurred!\n"); ++#endif ++ sysRegWrite(RAETH_FE_INT_STATUS, ALT_RPLC_INT3); ++ ei_hw_lro_auto_adj(3, ei_local); ++ } ++ if((reg_int_val & ALT_RPLC_INT2)){ ++#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG) ++ printk("[HW LRO] ALT_RPLC_INT2 occurred!\n"); ++#endif ++ sysRegWrite(RAETH_FE_INT_STATUS, ALT_RPLC_INT2); ++ ei_hw_lro_auto_adj(2, ei_local); ++ } ++ if((reg_int_val & ALT_RPLC_INT1)){ ++#if defined (CONFIG_RAETH_HW_LRO_AUTO_ADJ_DBG) ++ printk("[HW LRO] ALT_RPLC_INT1 occurred!\n"); ++#endif ++ sysRegWrite(RAETH_FE_INT_STATUS, ALT_RPLC_INT1); ++ ei_hw_lro_auto_adj(1, ei_local); ++ } ++ ++ /* unmask interrupts of rx flow to hw lor rings */ ++ reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE); ++ sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask | ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1); ++} ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#ifdef CONFIG_RAETH_NAPI ++static int ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++raeth_clean(struct napi_struct *napi, int budget) ++#else ++raeth_clean(struct net_device *netdev, int *budget) ++#endif ++{ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ struct net_device *netdev=dev_raether; ++ int work_to_do = budget; ++#else ++ int work_to_do = min(*budget, netdev->quota); ++#endif ++ END_DEVICE *ei_local =netdev_priv(netdev); ++ int work_done = 0; ++ unsigned long reg_int_mask=0; ++ ++ ei_xmit_housekeeping(0); ++ ++ rt2880_eth_recv(netdev, &work_done, work_to_do); ++ ++ /* this could control when to re-enable interrupt, 0-> mean never enable interrupt*/ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++ *budget -= work_done; ++ netdev->quota -= work_done; ++#endif ++ /* if no Tx and not enough Rx work done, exit the polling mode */ ++ if(( (work_done < work_to_do)) || !netif_running(netdev)) { ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ napi_complete(&ei_local->napi); ++#else ++ netif_rx_complete(netdev); ++#endif ++ atomic_dec_and_test(&ei_local->irq_sem); ++ ++ sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_ALL); // ack all fe interrupts ++ reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE); ++ ++#ifdef DELAY_INT ++ sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask |RAETH_FE_INT_DLY_INIT); // init delay interrupt only ++#else ++ sysRegWrite(RAETH_FE_INT_ENABLE,reg_int_mask | RAETH_FE_INT_SETTING); ++#endif ++ ++#ifdef CONFIG_RAETH_QDMA ++ sysRegWrite(QFE_INT_STATUS, QFE_INT_ALL); ++ reg_int_mask=sysRegRead(QFE_INT_ENABLE); ++#ifdef DELAY_INT ++ sysRegWrite(QFE_INT_ENABLE, reg_int_mask |QFE_INT_DLY_INIT); // init delay interrupt only ++#else ++ sysRegWrite(QFE_INT_ENABLE,reg_int_mask | (RX_DONE_INT0 | RX_DONE_INT1 | RLS_DONE_INT)); ++#endif ++#endif // CONFIG_RAETH_QDMA // ++ ++ return 0; ++ } ++ ++ return 1; ++} ++ ++#endif ++ ++ ++void gsw_delay_setting(void) ++{ ++#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN) || defined (CONFIG_GE_RGMII_INTERNAL_P4_AN) ++ END_DEVICE *ei_local = netdev_priv(dev_raether); ++ int reg_int_val = 0; ++ int link_speed = 0; ++ ++ reg_int_val = sysRegRead(FE_INT_STATUS2); ++#if defined (CONFIG_RALINK_MT7621) ++ if( reg_int_val & BIT(25)) ++ { ++ if(sysRegRead(RALINK_ETH_SW_BASE+0x0208) & 0x1) // link up ++ { ++ link_speed = (sysRegRead(RALINK_ETH_SW_BASE+0x0208)>>2 & 0x3); ++ if(link_speed == 1) ++ { ++ // delay setting for 100M ++ if((sysRegRead(0xbe00000c)&0xFFFF)==0x0101) ++ mii_mgr_write(31, 0x7b00, 8); ++ printk("MT7621 GE2 link rate to 100M\n"); ++ } else ++ { ++ //delay setting for 10/1000M ++ if((sysRegRead(0xbe00000c)&0xFFFF)==0x0101) ++ mii_mgr_write(31, 0x7b00, 0x102); ++ printk("MT7621 GE2 link rate to 10M/1G\n"); ++ } ++ schedule_work(&ei_local->kill_sig_wq); ++ } ++ } ++#endif ++ sysRegWrite(FE_INT_STATUS2, reg_int_val); ++#endif ++} ++ ++/** ++ * ei_interrupt - handle controler interrupt ++ * ++ * This routine is called at interrupt level in response to an interrupt from ++ * the controller. ++ * ++ * RETURNS: N/A. ++ */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++static irqreturn_t ei_interrupt(int irq, void *dev_id) ++#else ++static irqreturn_t ei_interrupt(int irq, void *dev_id, struct pt_regs * regs) ++#endif ++{ ++#if !defined(CONFIG_RAETH_NAPI) ++ unsigned long reg_int_val; ++ unsigned long reg_int_mask=0; ++ unsigned int recv = 0; ++ unsigned int transmit __maybe_unused = 0; ++ unsigned long flags; ++#endif ++ ++ struct net_device *dev = (struct net_device *) dev_id; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++ //Qwert ++ /* ++ unsigned long old,cur,dcycle; ++ static int cnt = 0; ++ static unsigned long max_dcycle = 0,tcycle = 0; ++ old = read_c0_count(); ++ */ ++ if (dev == NULL) ++ { ++ printk (KERN_ERR "net_interrupt(): irq %x for unknown device.\n", IRQ_ENET0); ++ return IRQ_NONE; ++ } ++ ++#ifdef CONFIG_RAETH_NAPI ++ gsw_delay_setting(); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ if(napi_schedule_prep(&ei_local->napi)) { ++#else ++ if(netif_rx_schedule_prep(dev)) { ++#endif ++ atomic_inc(&ei_local->irq_sem); ++ sysRegWrite(RAETH_FE_INT_ENABLE, 0); ++#ifdef CONFIG_RAETH_QDMA ++ sysRegWrite(QFE_INT_ENABLE, 0); ++#endif ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ __napi_schedule(&ei_local->napi); ++#else ++ __netif_rx_schedule(dev); ++#endif ++ } ++#else ++ ++ spin_lock_irqsave(&(ei_local->page_lock), flags); ++ reg_int_val = sysRegRead(RAETH_FE_INT_STATUS); ++#ifdef CONFIG_RAETH_QDMA ++ reg_int_val |= sysRegRead(QFE_INT_STATUS); ++#endif ++#if defined (DELAY_INT) ++ if((reg_int_val & RX_DLY_INT)) ++ recv = 1; ++ ++ if (reg_int_val & RAETH_TX_DLY_INT) ++ transmit = 1; ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++ raeth_pdma_lro_dly_int_dvt(); ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ ++#else ++ if((reg_int_val & (RX_DONE_INT0 | RX_DONE_INT3 | RX_DONE_INT2 | RX_DONE_INT1))) ++ recv = 1; ++ ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++#if defined(CONFIG_ARCH_MT7623) ++ if((reg_int_val & RX_DONE_INT3)) ++ recv = 3; ++ if((reg_int_val & RX_DONE_INT2)) ++ recv = 2; ++#endif /* CONFIG_ARCH_MT7623 */ ++ if((reg_int_val & RX_DONE_INT1)) ++ recv = 1; ++#endif ++ ++ if (reg_int_val & RAETH_TX_DONE_INT0) ++ transmit |= RAETH_TX_DONE_INT0; ++#if defined (CONFIG_RAETH_QOS) ++ if (reg_int_val & TX_DONE_INT1) ++ transmit |= TX_DONE_INT1; ++ if (reg_int_val & TX_DONE_INT2) ++ transmit |= TX_DONE_INT2; ++ if (reg_int_val & TX_DONE_INT3) ++ transmit |= TX_DONE_INT3; ++#endif //CONFIG_RAETH_QOS ++ ++#endif //DELAY_INT ++ ++#if defined (DELAY_INT) ++ sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT); ++#else ++ sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_ALL); ++#endif ++#ifdef CONFIG_RAETH_QDMA ++#if defined (DELAY_INT) ++ sysRegWrite(QFE_INT_STATUS, QFE_INT_DLY_INIT); ++#else ++ sysRegWrite(QFE_INT_STATUS, QFE_INT_ALL); ++#endif ++#endif ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ if( reg_int_val & (ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1) ){ ++ /* mask interrupts of rx flow to hw lor rings */ ++ reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE); ++ sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1)); ++ schedule_work(&ei_local->hw_lro_wq); ++ } ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0) ++ if(transmit) ++ ei_xmit_housekeeping(0); ++#else ++ ei_xmit_housekeeping(0); ++#endif ++ ++ if (((recv == 1) || (pending_recv ==1)) && (tx_ring_full==0)) ++ { ++ reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE); ++#if defined (DELAY_INT) ++ sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT)); ++#else ++ sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3)); ++#endif //DELAY_INT ++#ifdef CONFIG_RAETH_QDMA ++ reg_int_mask = sysRegRead(QFE_INT_ENABLE); ++#if defined (DELAY_INT) ++ sysRegWrite(QFE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT)); ++#else ++ sysRegWrite(QFE_INT_ENABLE, reg_int_mask & ~(RX_DONE_INT0 | RX_DONE_INT1 | RX_DONE_INT2 | RX_DONE_INT3)); ++#endif //DELAY_INT ++#endif ++ ++ pending_recv=0; ++#ifdef WORKQUEUE_BH ++ schedule_work(&ei_local->rx_wq); ++#else ++#if defined (TASKLET_WORKQUEUE_SW) ++ if (working_schedule == 1) ++ schedule_work(&ei_local->rx_wq); ++ else ++#endif ++ tasklet_hi_schedule(&ei_local->rx_tasklet); ++#endif // WORKQUEUE_BH // ++ } ++ else if (recv == 1 && tx_ring_full==1) ++ { ++ pending_recv=1; ++ } ++ else if((recv == 0) && (transmit == 0)) ++ { ++ gsw_delay_setting(); ++ } ++ spin_unlock_irqrestore(&(ei_local->page_lock), flags); ++#endif ++ ++ return IRQ_HANDLED; ++} ++ ++#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620)|| defined (CONFIG_RALINK_MT7621) ++static void esw_link_status_changed(int port_no, void *dev_id) ++{ ++ unsigned int reg_val; ++ struct net_device *dev = (struct net_device *) dev_id; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) ++ reg_val = *((volatile u32 *)(RALINK_ETH_SW_BASE+ 0x3008 + (port_no*0x100))); ++#elif defined (CONFIG_RALINK_MT7621) ++ mii_mgr_read(31, (0x3008 + (port_no*0x100)), ®_val); ++#endif ++ if(reg_val & 0x1) { ++ printk("ESW: Link Status Changed - Port%d Link UP\n", port_no); ++#if defined (CONFIG_RALINK_MT7621) && defined (CONFIG_RAETH_8023AZ_EEE) ++ mii_mgr_write(port_no, 31, 0x52b5); ++ mii_mgr_write(port_no, 16, 0xb780); ++ mii_mgr_write(port_no, 17, 0x00e0); ++ mii_mgr_write(port_no, 16, 0x9780); ++#endif ++ ++#if defined (CONFIG_WAN_AT_P0) ++ if(port_no==0) { ++ schedule_work(&ei_local->kill_sig_wq); ++ } ++#elif defined (CONFIG_WAN_AT_P4) ++ if(port_no==4) { ++ schedule_work(&ei_local->kill_sig_wq); ++ } ++#endif ++ } else { ++ printk("ESW: Link Status Changed - Port%d Link Down\n", port_no); ++#if defined (CONFIG_RALINK_MT7621) && defined (CONFIG_RAETH_8023AZ_EEE) ++ mii_mgr_write(port_no, 31, 0x52b5); ++ mii_mgr_write(port_no, 16, 0xb780); ++ mii_mgr_write(port_no, 17, 0x0000); ++ mii_mgr_write(port_no, 16, 0x9780); ++#endif ++ ++ } ++} ++#endif ++ ++#if defined (CONFIG_RT_3052_ESW) && ! defined(CONFIG_RALINK_MT7621) && ! defined(CONFIG_ARCH_MT7623) ++static irqreturn_t esw_interrupt(int irq, void *dev_id) ++{ ++ unsigned long flags; ++ unsigned long reg_int_val; ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined(CONFIG_RALINK_MT7620) ++ unsigned long acl_int_val; ++ unsigned long mib_int_val; ++#else ++ static unsigned long stat; ++ unsigned long stat_curr; ++#endif ++ ++ struct net_device *dev = (struct net_device *) dev_id; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++ ++ spin_lock_irqsave(&(ei_local->page_lock), flags); ++ reg_int_val = (*((volatile u32 *)(ESW_ISR))); //Interrupt Status Register ++ ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined(CONFIG_RALINK_MT7620) ++ if (reg_int_val & P5_LINK_CH) { ++ esw_link_status_changed(5, dev_id); ++ } ++ if (reg_int_val & P4_LINK_CH) { ++ esw_link_status_changed(4, dev_id); ++ } ++ if (reg_int_val & P3_LINK_CH) { ++ esw_link_status_changed(3, dev_id); ++ } ++ if (reg_int_val & P2_LINK_CH) { ++ esw_link_status_changed(2, dev_id); ++ } ++ if (reg_int_val & P1_LINK_CH) { ++ esw_link_status_changed(1, dev_id); ++ } ++ if (reg_int_val & P0_LINK_CH) { ++ esw_link_status_changed(0, dev_id); ++ } ++ if (reg_int_val & ACL_INT) { ++ acl_int_val = sysRegRead(ESW_AISR); ++ sysRegWrite(ESW_AISR, acl_int_val); ++ } ++ if (reg_int_val & MIB_INT) { ++ ++ mib_int_val = sysRegRead(ESW_P0_IntSn); ++ if(mib_int_val){ ++ sysRegWrite(ESW_P0_IntSn, mib_int_val); ++ if(mib_int_val & RX_GOOD_CNT) ++ p0_rx_good_cnt ++; ++ if(mib_int_val & TX_GOOD_CNT) ++ p0_tx_good_cnt ++; ++ if(mib_int_val & RX_GOCT_CNT) ++ p0_rx_byte_cnt ++; ++ if(mib_int_val & TX_GOCT_CNT) ++ p0_tx_byte_cnt ++; ++ } ++ ++ mib_int_val = sysRegRead(ESW_P1_IntSn); ++ if(mib_int_val){ ++ sysRegWrite(ESW_P1_IntSn, mib_int_val); ++ if(mib_int_val & RX_GOOD_CNT) ++ p1_rx_good_cnt ++; ++ if(mib_int_val & TX_GOOD_CNT) ++ p1_tx_good_cnt ++; ++ if(mib_int_val & RX_GOCT_CNT) ++ p1_rx_byte_cnt ++; ++ if(mib_int_val & TX_GOCT_CNT) ++ p1_tx_byte_cnt ++; ++ } ++ ++ mib_int_val = sysRegRead(ESW_P2_IntSn); ++ if(mib_int_val){ ++ sysRegWrite(ESW_P2_IntSn, mib_int_val); ++ if(mib_int_val & RX_GOOD_CNT) ++ p2_rx_good_cnt ++; ++ if(mib_int_val & TX_GOOD_CNT) ++ p2_tx_good_cnt ++; ++ if(mib_int_val & RX_GOCT_CNT) ++ p2_rx_byte_cnt ++; ++ if(mib_int_val & TX_GOCT_CNT) ++ p2_tx_byte_cnt ++; ++ } ++ ++ ++ mib_int_val = sysRegRead(ESW_P3_IntSn); ++ if(mib_int_val){ ++ sysRegWrite(ESW_P3_IntSn, mib_int_val); ++ if(mib_int_val & RX_GOOD_CNT) ++ p3_rx_good_cnt ++; ++ if(mib_int_val & TX_GOOD_CNT) ++ p3_tx_good_cnt ++; ++ if(mib_int_val & RX_GOCT_CNT) ++ p3_rx_byte_cnt ++; ++ if(mib_int_val & TX_GOCT_CNT) ++ p3_tx_byte_cnt ++; ++ } ++ ++ mib_int_val = sysRegRead(ESW_P4_IntSn); ++ if(mib_int_val){ ++ sysRegWrite(ESW_P4_IntSn, mib_int_val); ++ if(mib_int_val & RX_GOOD_CNT) ++ p4_rx_good_cnt ++; ++ if(mib_int_val & TX_GOOD_CNT) ++ p4_tx_good_cnt ++; ++ if(mib_int_val & RX_GOCT_CNT) ++ p4_rx_byte_cnt ++; ++ if(mib_int_val & TX_GOCT_CNT) ++ p4_tx_byte_cnt ++; ++ } ++ ++ mib_int_val = sysRegRead(ESW_P5_IntSn); ++ if(mib_int_val){ ++ sysRegWrite(ESW_P5_IntSn, mib_int_val); ++ if(mib_int_val & RX_GOOD_CNT) ++ p5_rx_good_cnt ++; ++ if(mib_int_val & TX_GOOD_CNT) ++ p5_tx_good_cnt ++; ++ if(mib_int_val & RX_GOCT_CNT) ++ p5_rx_byte_cnt ++; ++ if(mib_int_val & TX_GOCT_CNT) ++ p5_tx_byte_cnt ++; ++ } ++ ++ mib_int_val = sysRegRead(ESW_P6_IntSn); ++ if(mib_int_val){ ++ sysRegWrite(ESW_P6_IntSn, mib_int_val); ++ if(mib_int_val & RX_GOOD_CNT) ++ p6_rx_good_cnt ++; ++ if(mib_int_val & TX_GOOD_CNT) ++ p6_tx_good_cnt ++; ++ if(mib_int_val & RX_GOCT_CNT) ++ p6_rx_byte_cnt ++; ++ if(mib_int_val & TX_GOCT_CNT) ++ p6_tx_byte_cnt ++; ++ } ++#if defined (CONFIG_RALINK_MT7620) ++ mib_int_val = sysRegRead(ESW_P7_IntSn); ++ if(mib_int_val){ ++ sysRegWrite(ESW_P7_IntSn, mib_int_val); ++ if(mib_int_val & RX_GOOD_CNT) ++ p7_rx_good_cnt ++; ++ if(mib_int_val & TX_GOOD_CNT) ++ p7_tx_good_cnt ++; ++ if(mib_int_val & RX_GOCT_CNT) ++ p7_rx_byte_cnt ++; ++ if(mib_int_val & TX_GOCT_CNT) ++ p7_tx_byte_cnt ++; ++ ++ } ++#endif ++ } ++ ++#else // not RT6855 ++ if (reg_int_val & PORT_ST_CHG) { ++ printk("RT305x_ESW: Link Status Changed\n"); ++ ++ stat_curr = *((volatile u32 *)(RALINK_ETH_SW_BASE+0x80)); ++#ifdef CONFIG_WAN_AT_P0 ++ //link down --> link up : send signal to user application ++ //link up --> link down : ignore ++ if ((stat & (1<<25)) || !(stat_curr & (1<<25))) ++#else ++ if ((stat & (1<<29)) || !(stat_curr & (1<<29))) ++#endif ++ goto out; ++ ++ schedule_work(&ei_local->kill_sig_wq); ++out: ++ stat = stat_curr; ++ } ++ ++#endif // defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A)// ++ ++ sysRegWrite(ESW_ISR, reg_int_val); ++ ++ spin_unlock_irqrestore(&(ei_local->page_lock), flags); ++ return IRQ_HANDLED; ++} ++ ++ ++ ++#elif defined (CONFIG_RT_3052_ESW) && defined(CONFIG_RALINK_MT7621) ++ ++static irqreturn_t esw_interrupt(int irq, void *dev_id) ++{ ++ unsigned long flags; ++ unsigned int reg_int_val; ++ struct net_device *dev = (struct net_device *) dev_id; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++ spin_lock_irqsave(&(ei_local->page_lock), flags); ++ mii_mgr_read(31, 0x700c, ®_int_val); ++ ++ if (reg_int_val & P4_LINK_CH) { ++ esw_link_status_changed(4, dev_id); ++ } ++ ++ if (reg_int_val & P3_LINK_CH) { ++ esw_link_status_changed(3, dev_id); ++ } ++ if (reg_int_val & P2_LINK_CH) { ++ esw_link_status_changed(2, dev_id); ++ } ++ if (reg_int_val & P1_LINK_CH) { ++ esw_link_status_changed(1, dev_id); ++ } ++ if (reg_int_val & P0_LINK_CH) { ++ esw_link_status_changed(0, dev_id); ++ } ++ ++ mii_mgr_write(31, 0x700c, 0x1f); //ack switch link change ++ ++ spin_unlock_irqrestore(&(ei_local->page_lock), flags); ++ return IRQ_HANDLED; ++} ++ ++#endif ++ ++ ++static int ei_start_xmit_fake(struct sk_buff* skb, struct net_device *dev) ++{ ++ return ei_start_xmit(skb, dev, 1); ++} ++ ++ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) ++void dump_phy_reg(int port_no, int from, int to, int is_local) ++{ ++ u32 i=0; ++ u32 temp=0; ++ ++ if(is_local==0) { ++ printk("Global Register\n"); ++ printk("==============="); ++ mii_mgr_write(0, 31, 0); //select global register ++ for(i=from;i<=to;i++) { ++ if(i%8==0) { ++ printk("\n"); ++ } ++ mii_mgr_read(port_no,i, &temp); ++ printk("%02d: %04X ",i, temp); ++ } ++ } else { ++ mii_mgr_write(0, 31, 0x8000); //select local register ++ printk("\n\nLocal Register Port %d\n",port_no); ++ printk("==============="); ++ for(i=from;i<=to;i++) { ++ if(i%8==0) { ++ printk("\n"); ++ } ++ mii_mgr_read(port_no,i, &temp); ++ printk("%02d: %04X ",i, temp); ++ } ++ } ++ printk("\n"); ++} ++#else ++void dump_phy_reg(int port_no, int from, int to, int is_local, int page_no) ++{ ++ ++ u32 i=0; ++ u32 temp=0; ++ u32 r31=0; ++ ++ ++ if(is_local==0) { ++ ++ printk("\n\nGlobal Register Page %d\n",page_no); ++ printk("==============="); ++ r31 |= 0 << 15; //global ++ r31 |= ((page_no&0x7) << 12); //page no ++ mii_mgr_write(port_no, 31, r31); //select global page x ++ for(i=16;i<32;i++) { ++ if(i%8==0) { ++ printk("\n"); ++ } ++ mii_mgr_read(port_no,i, &temp); ++ printk("%02d: %04X ",i, temp); ++ } ++ }else { ++ printk("\n\nLocal Register Port %d Page %d\n",port_no, page_no); ++ printk("==============="); ++ r31 |= 1 << 15; //local ++ r31 |= ((page_no&0x7) << 12); //page no ++ mii_mgr_write(port_no, 31, r31); //select local page x ++ for(i=16;i<32;i++) { ++ if(i%8==0) { ++ printk("\n"); ++ } ++ mii_mgr_read(port_no,i, &temp); ++ printk("%02d: %04X ",i, temp); ++ } ++ } ++ printk("\n"); ++} ++ ++#endif ++ ++int ei_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++#if defined(CONFIG_RT_3052_ESW) || defined(CONFIG_RAETH_QDMA) ++ esw_reg reg; ++#endif ++#if defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350) || \ ++ defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || \ ++ defined (CONFIG_RALINK_MT7628) || defined (CONFIG_ARCH_MT7623) ++ esw_rate ratelimit; ++#endif ++#if defined(CONFIG_RT_3052_ESW) ++ unsigned int offset = 0; ++ unsigned int value = 0; ++#endif ++ ++ int ret = 0; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ra_mii_ioctl_data mii; ++ spin_lock_irq(&ei_local->page_lock); ++ ++ switch (cmd) { ++#if defined(CONFIG_RAETH_QDMA) ++#define _HQOS_REG(x) (*((volatile u32 *)(RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + x))) ++ case RAETH_QDMA_REG_READ: ++ copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if (reg.off > REG_HQOS_MAX) { ++ ret = -EINVAL; ++ break; ++ } ++ reg.val = _HQOS_REG(reg.off); ++ //printk("read reg off:%x val:%x\n", reg.off, reg.val); ++ copy_to_user(ifr->ifr_data, ®, sizeof(reg)); ++ break; ++ case RAETH_QDMA_REG_WRITE: ++ copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if (reg.off > REG_HQOS_MAX) { ++ ret = -EINVAL; ++ break; ++ } ++ _HQOS_REG(reg.off) = reg.val; ++ //printk("write reg off:%x val:%x\n", reg.off, reg.val); ++ break; ++#if 0 ++ case RAETH_QDMA_READ_CPU_CLK: ++ copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ reg.val = get_surfboard_sysclk(); ++ //printk("read reg off:%x val:%x\n", reg.off, reg.val); ++ copy_to_user(ifr->ifr_data, ®, sizeof(reg)); ++ break; ++#endif ++ case RAETH_QDMA_QUEUE_MAPPING: ++ copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if((reg.off&0x100) == 0x100){ ++ lan_wan_separate = 1; ++ reg.off &= 0xff; ++ }else{ ++ lan_wan_separate = 0; ++ } ++ M2Q_table[reg.off] = reg.val; ++ break; ++#if defined(CONFIG_HW_SFQ) ++ case RAETH_QDMA_SFQ_WEB_ENABLE: ++ copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if((reg.val) == 0x1){ ++ web_sfq_enable = 1; ++ ++ }else{ ++ web_sfq_enable = 0; ++ } ++ break; ++#endif ++ ++ ++#endif ++ case RAETH_MII_READ: ++ copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ mii_mgr_read(mii.phy_id, mii.reg_num, &mii.val_out); ++ //printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_out); ++ copy_to_user(ifr->ifr_data, &mii, sizeof(mii)); ++ break; ++ ++ case RAETH_MII_WRITE: ++ copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ //printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_in); ++ mii_mgr_write(mii.phy_id, mii.reg_num, mii.val_in); ++ break; ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_ARCH_MT7623) ++ case RAETH_MII_READ_CL45: ++ copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ //mii_mgr_cl45_set_address(mii.port_num, mii.dev_addr, mii.reg_addr); ++ mii_mgr_read_cl45(mii.port_num, mii.dev_addr, mii.reg_addr, &mii.val_out); ++ copy_to_user(ifr->ifr_data, &mii, sizeof(mii)); ++ break; ++ case RAETH_MII_WRITE_CL45: ++ copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ //mii_mgr_cl45_set_address(mii.port_num, mii.dev_addr, mii.reg_addr); ++ mii_mgr_write_cl45(mii.port_num, mii.dev_addr, mii.reg_addr, mii.val_in); ++ break; ++#endif ++ ++#if defined(CONFIG_RT_3052_ESW) ++#define _ESW_REG(x) (*((volatile u32 *)(RALINK_ETH_SW_BASE + x))) ++ case RAETH_ESW_REG_READ: ++ copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if (reg.off > REG_ESW_MAX) { ++ ret = -EINVAL; ++ break; ++ } ++ reg.val = _ESW_REG(reg.off); ++ //printk("read reg off:%x val:%x\n", reg.off, reg.val); ++ copy_to_user(ifr->ifr_data, ®, sizeof(reg)); ++ break; ++ case RAETH_ESW_REG_WRITE: ++ copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++ if (reg.off > REG_ESW_MAX) { ++ ret = -EINVAL; ++ break; ++ } ++ _ESW_REG(reg.off) = reg.val; ++ //printk("write reg off:%x val:%x\n", reg.off, reg.val); ++ break; ++ case RAETH_ESW_PHY_DUMP: ++ copy_from_user(®, ifr->ifr_data, sizeof(reg)); ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) ++ if (reg.val ==32 ) {//dump all phy register ++ /* Global Register 0~31 ++ * Local Register 0~31 ++ */ ++ dump_phy_reg(0, 0, 31, 0); //dump global register ++ for(offset=0;offset<5;offset++) { ++ dump_phy_reg(offset, 0, 31, 1); //dump local register ++ } ++ } else { ++ dump_phy_reg(reg.val, 0, 31, 0); //dump global register ++ dump_phy_reg(reg.val, 0, 31, 1); //dump local register ++ } ++#else ++ /* SPEC defined Register 0~15 ++ * Global Register 16~31 for each page ++ * Local Register 16~31 for each page ++ */ ++ printk("SPEC defined Register"); ++ if (reg.val ==32 ) {//dump all phy register ++ int i = 0; ++ for(i=0; i<5; i++){ ++ printk("\n[Port %d]===============",i); ++ for(offset=0;offset<16;offset++) { ++ if(offset%8==0) { ++ printk("\n"); ++ } ++ mii_mgr_read(i,offset, &value); ++ printk("%02d: %04X ",offset, value); ++ } ++ } ++ } ++ else{ ++ printk("\n[Port %d]===============",reg.val); ++ for(offset=0;offset<16;offset++) { ++ if(offset%8==0) { ++ printk("\n"); ++ } ++ mii_mgr_read(reg.val,offset, &value); ++ printk("%02d: %04X ",offset, value); ++ } ++ } ++ ++#if defined (CONFIG_RALINK_MT7628) ++ for(offset=0;offset<7;offset++) { //global register page 0~6 ++#else ++ for(offset=0;offset<5;offset++) { //global register page 0~4 ++#endif ++ if(reg.val == 32) //dump all phy register ++ dump_phy_reg(0, 16, 31, 0, offset); ++ else ++ dump_phy_reg(reg.val, 16, 31, 0, offset); ++ } ++ ++ if (reg.val == 32) {//dump all phy register ++#if !defined (CONFIG_RAETH_HAS_PORT4) ++ for(offset=0;offset<5;offset++) { //local register port 0-port4 ++#else ++ for(offset=0;offset<4;offset++) { //local register port 0-port3 ++#endif ++ dump_phy_reg(offset, 16, 31, 1, 0); //dump local page 0 ++ dump_phy_reg(offset, 16, 31, 1, 1); //dump local page 1 ++ dump_phy_reg(offset, 16, 31, 1, 2); //dump local page 2 ++ dump_phy_reg(offset, 16, 31, 1, 3); //dump local page 3 ++ } ++ }else { ++ dump_phy_reg(reg.val, 16, 31, 1, 0); //dump local page 0 ++ dump_phy_reg(reg.val, 16, 31, 1, 1); //dump local page 1 ++ dump_phy_reg(reg.val, 16, 31, 1, 2); //dump local page 2 ++ dump_phy_reg(reg.val, 16, 31, 1, 3); //dump local page 3 ++ } ++#endif ++ break; ++ ++#if defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++#define _ESW_REG(x) (*((volatile u32 *)(RALINK_ETH_SW_BASE + x))) ++ case RAETH_ESW_INGRESS_RATE: ++ copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit)); ++ offset = 0x11c + (4 * (ratelimit.port / 2)); ++ value = _ESW_REG(offset); ++ ++ if((ratelimit.port % 2) == 0) ++ { ++ value &= 0xffff0000; ++ if(ratelimit.on_off == 1) ++ { ++ value |= (ratelimit.on_off << 14); ++ value |= (0x07 << 10); ++ value |= ratelimit.bw; ++ } ++ } ++ else if((ratelimit.port % 2) == 1) ++ { ++ value &= 0x0000ffff; ++ if(ratelimit.on_off == 1) ++ { ++ value |= (ratelimit.on_off << 30); ++ value |= (0x07 << 26); ++ value |= (ratelimit.bw << 16); ++ } ++ } ++ printk("offset = 0x%4x value=0x%x\n\r", offset, value); ++ ++ _ESW_REG(offset) = value; ++ break; ++ ++ case RAETH_ESW_EGRESS_RATE: ++ copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit)); ++ offset = 0x140 + (4 * (ratelimit.port / 2)); ++ value = _ESW_REG(offset); ++ ++ if((ratelimit.port % 2) == 0) ++ { ++ value &= 0xffff0000; ++ if(ratelimit.on_off == 1) ++ { ++ value |= (ratelimit.on_off << 12); ++ value |= (0x03 << 10); ++ value |= ratelimit.bw; ++ } ++ } ++ else if((ratelimit.port % 2) == 1) ++ { ++ value &= 0x0000ffff; ++ if(ratelimit.on_off == 1) ++ { ++ value |= (ratelimit.on_off << 28); ++ value |= (0x03 << 26); ++ value |= (ratelimit.bw << 16); ++ } ++ } ++ printk("offset = 0x%4x value=0x%x\n\r", offset, value); ++ _ESW_REG(offset) = value; ++ break; ++#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \ ++ defined(CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++#define _ESW_REG(x) (*((volatile u32 *)(RALINK_ETH_SW_BASE + x))) ++ case RAETH_ESW_INGRESS_RATE: ++ copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit)); ++#if defined(CONFIG_RALINK_RT6855A) || defined(CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ offset = 0x1800 + (0x100 * ratelimit.port); ++#else ++ offset = 0x1080 + (0x100 * ratelimit.port); ++#endif ++ value = _ESW_REG(offset); ++ ++ value &= 0xffff0000; ++ if(ratelimit.on_off == 1) ++ { ++ value |= (ratelimit.on_off << 15); ++ if (ratelimit.bw < 100) ++ { ++ value |= (0x0 << 8); ++ value |= ratelimit.bw; ++ }else if(ratelimit.bw < 1000) ++ { ++ value |= (0x1 << 8); ++ value |= ratelimit.bw/10; ++ }else if(ratelimit.bw < 10000) ++ { ++ value |= (0x2 << 8); ++ value |= ratelimit.bw/100; ++ }else if(ratelimit.bw < 100000) ++ { ++ value |= (0x3 << 8); ++ value |= ratelimit.bw/1000; ++ }else ++ { ++ value |= (0x4 << 8); ++ value |= ratelimit.bw/10000; ++ } ++ } ++ printk("offset = 0x%4x value=0x%x\n\r", offset, value); ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ mii_mgr_write(0x1f, offset, value); ++#else ++ _ESW_REG(offset) = value; ++#endif ++ break; ++ ++ case RAETH_ESW_EGRESS_RATE: ++ copy_from_user(&ratelimit, ifr->ifr_data, sizeof(ratelimit)); ++ offset = 0x1040 + (0x100 * ratelimit.port); ++ value = _ESW_REG(offset); ++ ++ value &= 0xffff0000; ++ if(ratelimit.on_off == 1) ++ { ++ value |= (ratelimit.on_off << 15); ++ if (ratelimit.bw < 100) ++ { ++ value |= (0x0 << 8); ++ value |= ratelimit.bw; ++ }else if(ratelimit.bw < 1000) ++ { ++ value |= (0x1 << 8); ++ value |= ratelimit.bw/10; ++ }else if(ratelimit.bw < 10000) ++ { ++ value |= (0x2 << 8); ++ value |= ratelimit.bw/100; ++ }else if(ratelimit.bw < 100000) ++ { ++ value |= (0x3 << 8); ++ value |= ratelimit.bw/1000; ++ }else ++ { ++ value |= (0x4 << 8); ++ value |= ratelimit.bw/10000; ++ } ++ } ++ printk("offset = 0x%4x value=0x%x\n\r", offset, value); ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ mii_mgr_write(0x1f, offset, value); ++#else ++ _ESW_REG(offset) = value; ++#endif ++ break; ++#endif ++#endif // CONFIG_RT_3052_ESW ++ default: ++ ret = -EOPNOTSUPP; ++ break; ++ ++ } ++ ++ spin_unlock_irq(&ei_local->page_lock); ++ return ret; ++} ++ ++/* ++ * Set new MTU size ++ * Change the mtu of Raeth Ethernet Device ++ */ ++static int ei_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev); // get priv ei_local pointer from net_dev structure ++ ++ if ( ei_local == NULL ) { ++ printk(KERN_EMERG "%s: ei_change_mtu passed a non-existent private pointer from net_dev!\n", dev->name); ++ return -ENXIO; ++ } ++ ++ ++ if ( (new_mtu > 4096) || (new_mtu < 64)) { ++ return -EINVAL; ++ } ++ ++#ifndef CONFIG_RAETH_JUMBOFRAME ++ if ( new_mtu > 1500 ) { ++ return -EINVAL; ++ } ++#endif ++ ++ dev->mtu = new_mtu; ++ ++ return 0; ++} ++ ++#ifdef CONFIG_RAETH_HW_VLAN_RX ++static void ei_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++ ei_local->vlgrp = grp; ++ ++ /* enable HW VLAN RX */ ++ sysRegWrite(CDMP_EG_CTRL, 1); ++ ++} ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++static const struct net_device_ops ei_netdev_ops = { ++ .ndo_init = rather_probe, ++ .ndo_open = ei_open, ++ .ndo_stop = ei_close, ++ .ndo_start_xmit = ei_start_xmit_fake, ++ .ndo_get_stats = ra_get_stats, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_change_mtu = ei_change_mtu, ++ .ndo_do_ioctl = ei_ioctl, ++ .ndo_validate_addr = eth_validate_addr, ++#ifdef CONFIG_RAETH_HW_VLAN_RX ++ .ndo_vlan_rx_register = ei_vlan_rx_register, ++#endif ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = raeth_clean, ++#endif ++// .ndo_tx_timeout = ei_tx_timeout, ++}; ++#endif ++ ++void ra2880_setup_dev_fptable(struct net_device *dev) ++{ ++ RAETH_PRINT(__FUNCTION__ "is called!\n"); ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ dev->netdev_ops = &ei_netdev_ops; ++#else ++ dev->open = ei_open; ++ dev->stop = ei_close; ++ dev->hard_start_xmit = ei_start_xmit_fake; ++ dev->get_stats = ra_get_stats; ++ dev->set_mac_address = ei_set_mac_addr; ++ dev->change_mtu = ei_change_mtu; ++ dev->mtu = 1500; ++ dev->do_ioctl = ei_ioctl; ++// dev->tx_timeout = ei_tx_timeout; ++ ++#ifdef CONFIG_RAETH_NAPI ++ dev->poll = &raeth_clean; ++#if defined (CONFIG_RAETH_ROUTER) ++ dev->weight = 32; ++#elif defined (CONFIG_RT_3052_ESW) ++ dev->weight = 32; ++#else ++ dev->weight = 128; ++#endif ++#endif ++#endif ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++ dev->ethtool_ops = &ra_ethtool_ops; ++#endif ++#define TX_TIMEOUT (5*HZ) ++ dev->watchdog_timeo = TX_TIMEOUT; ++ ++} ++ ++/* reset frame engine */ ++void fe_reset(void) ++{ ++#if defined (CONFIG_RALINK_RT6855A) ++ /* FIXME */ ++#else ++ u32 val; ++ ++ //val = *(volatile u32 *)(0x1b000000); ++ //printk("0x1b000000 is 0x%x\n", val); ++ //val = sysRegRead(0xFB110100); ++ //val = 0x8000; ++ //sysRegWrite(0xFB110100, val); ++ ++ ++ ++ val = sysRegRead(RSTCTRL); ++ ++// RT5350 need to reset ESW and FE at the same to avoid PDMA panic // ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ val = val | RALINK_FE_RST | RALINK_ESW_RST ; ++#else ++ val = val | RALINK_FE_RST; ++#endif ++ sysRegWrite(RSTCTRL, val); ++#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7628) ++ val = val & ~(RALINK_FE_RST | RALINK_ESW_RST); ++#else ++ val = val & ~(RALINK_FE_RST); ++#endif ++ ++ sysRegWrite(RSTCTRL, val); ++#endif ++} ++ ++/* set TRGMII */ ++#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC) ++void trgmii_set_7621(void) ++{ ++ u32 val = 0; ++ u32 val_0 = 0; ++ ++ val = sysRegRead(RSTCTRL); ++// MT7621 need to reset GMAC and FE first // ++ val = val | RALINK_FE_RST | RALINK_ETH_RST ; ++ sysRegWrite(RSTCTRL, val); ++ ++//set TRGMII clock// ++ val_0 = sysRegRead(CLK_CFG_0); ++ val_0 &= 0xffffff9f; ++ val_0 |= (0x1 << 5); ++ sysRegWrite(CLK_CFG_0, val_0); ++ mdelay(1); ++ val_0 = sysRegRead(CLK_CFG_0); ++ printk("set CLK_CFG_0 = 0x%x!!!!!!!!!!!!!!!!!!1\n",val_0); ++ val = val & ~(RALINK_FE_RST | RALINK_ETH_RST); ++ sysRegWrite(RSTCTRL, val); ++} ++ ++void trgmii_set_7530(void) ++{ ++// set MT7530 // ++#if 0 ++ ++ mii_mgr_write(31, 103, 0x0020); ++ ++ ++ //disable EEE ++ mii_mgr_write(0, 0x16, 0); ++ mii_mgr_write(1, 0x16, 0); ++ mii_mgr_write(2, 0x16, 0); ++ mii_mgr_write(3, 0x16, 0); ++ mii_mgr_write(4, 0x16, 0); ++ ++ ++ //PLL reset for E2 ++ mii_mgr_write(31, 104, 0x0608); ++ mii_mgr_write(31, 104, 0x2608); ++ ++ mii_mgr_write(31, 0x7808, 0x0); ++ mdelay(1); ++ mii_mgr_write(31, 0x7804, 0x01017e8f); ++ mdelay(1); ++ mii_mgr_write(31, 0x7808, 0x1); ++ mdelay(1); ++ ++#endif ++#if 1 ++ //CL45 command ++ //PLL to 150Mhz ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x404); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_read(31, 0x7800, ®Value); ++ regValue = (regValue >> 9) & 0x3; ++ if(regValue == 0x3) { //25Mhz Xtal ++ mii_mgr_write(0, 14, 0x0A00);//25Mhz XTAL for 150Mhz CLK ++ } else if(regValue == 0x2) { //40Mhz ++ mii_mgr_write(0, 14, 0x0780);//40Mhz XTAL for 150Mhz CLK ++ } ++ //mii_mgr_write(0, 14, 0x0C00);//ori ++ mdelay(1); ++ ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x409); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x57); ++ mdelay(1); ++ ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x40a); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x57); ++ ++//PLL BIAS en ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x403); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x1800); ++ mdelay(1); ++ ++//BIAS LPF en ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x403); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x1c00); ++ ++//sys PLL en ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x401); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0xc020); ++ ++//LCDDDS PWDS ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x406); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0xa030); ++ mdelay(1); ++ ++//GSW_2X_CLK ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x410); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x0003); ++ ++//enable P6 ++ mii_mgr_write(31, 0x3600, 0x5e33b); ++ ++//enable TRGMII ++ mii_mgr_write(31, 0x7830, 0x1); ++#endif ++ ++} ++#endif ++ ++void ei_reset_task(struct work_struct *work) ++{ ++ struct net_device *dev = dev_raether; ++ ++ ei_close(dev); ++ ei_open(dev); ++ ++ return; ++} ++ ++void ei_tx_timeout(struct net_device *dev) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++ schedule_work(&ei_local->reset_task); ++} ++ ++void setup_statistics(END_DEVICE* ei_local) ++{ ++ ei_local->stat.tx_packets = 0; ++ ei_local->stat.tx_bytes = 0; ++ ei_local->stat.tx_dropped = 0; ++ ei_local->stat.tx_errors = 0; ++ ei_local->stat.tx_aborted_errors= 0; ++ ei_local->stat.tx_carrier_errors= 0; ++ ei_local->stat.tx_fifo_errors = 0; ++ ei_local->stat.tx_heartbeat_errors = 0; ++ ei_local->stat.tx_window_errors = 0; ++ ++ ei_local->stat.rx_packets = 0; ++ ei_local->stat.rx_bytes = 0; ++ ei_local->stat.rx_dropped = 0; ++ ei_local->stat.rx_errors = 0; ++ ei_local->stat.rx_length_errors = 0; ++ ei_local->stat.rx_over_errors = 0; ++ ei_local->stat.rx_crc_errors = 0; ++ ei_local->stat.rx_frame_errors = 0; ++ ei_local->stat.rx_fifo_errors = 0; ++ ei_local->stat.rx_missed_errors = 0; ++ ++ ei_local->stat.collisions = 0; ++#if defined (CONFIG_RAETH_QOS) ++ ei_local->tx3_full = 0; ++ ei_local->tx2_full = 0; ++ ei_local->tx1_full = 0; ++ ei_local->tx0_full = 0; ++#else ++ ei_local->tx_full = 0; ++#endif ++#ifdef CONFIG_RAETH_NAPI ++ atomic_set(&ei_local->irq_sem, 1); ++#endif ++ ++} ++ ++/** ++ * rather_probe - pick up ethernet port at boot time ++ * @dev: network device to probe ++ * ++ * This routine probe the ethernet port at boot time. ++ * ++ * ++ */ ++ ++int __init rather_probe(struct net_device *dev) ++{ ++ int i; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ struct sockaddr addr; ++ unsigned char zero1[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; ++ unsigned char zero2[6]={0x00,0x00,0x00,0x00,0x00,0x00}; ++ ++ fe_reset(); ++ ++ //Get mac0 address from flash ++#ifdef RA_MTD_RW_BY_NUM ++ i = ra_mtd_read(2, GMAC0_OFFSET, 6, addr.sa_data); ++#else ++ i = ra_mtd_read_nm("Factory", GMAC0_OFFSET, 6, addr.sa_data); ++#endif ++ //If reading mtd failed or mac0 is empty, generate a mac address ++ if (i < 0 || ((memcmp(addr.sa_data, zero1, 6) == 0) || (addr.sa_data[0] & 0x1)) || ++ (memcmp(addr.sa_data, zero2, 6) == 0)) { ++ unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80}; ++ // net_srandom(jiffies); ++ memcpy(addr.sa_data, mac_addr01234, 5); ++ // addr.sa_data[5] = net_random()&0xFF; ++ } ++ ++#ifdef CONFIG_RAETH_NAPI ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ netif_napi_add(dev, &ei_local->napi, raeth_clean, 128); ++#endif ++#endif ++ ei_set_mac_addr(dev, &addr); ++ spin_lock_init(&ei_local->page_lock); ++ ether_setup(dev); ++ ++#ifdef CONFIG_RAETH_LRO ++ ei_local->lro_mgr.dev = dev; ++ memset(&ei_local->lro_mgr.stats, 0, sizeof(ei_local->lro_mgr.stats)); ++ ei_local->lro_mgr.features = LRO_F_NAPI; ++ ei_local->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; ++ ei_local->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; ++ ei_local->lro_mgr.max_desc = ARRAY_SIZE(ei_local->lro_arr); ++ ei_local->lro_mgr.max_aggr = 64; ++ ei_local->lro_mgr.frag_align_pad = 0; ++ ei_local->lro_mgr.lro_arr = ei_local->lro_arr; ++ ei_local->lro_mgr.get_skb_header = rt_get_skb_header; ++#endif ++ ++ setup_statistics(ei_local); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++int VirtualIF_ioctl(struct net_device * net_dev, ++ struct ifreq * ifr, int cmd) ++{ ++ ra_mii_ioctl_data mii; ++ ++ switch (cmd) { ++ case RAETH_MII_READ: ++ copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ mii_mgr_read(mii.phy_id, mii.reg_num, &mii.val_out); ++ //printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_out); ++ copy_to_user(ifr->ifr_data, &mii, sizeof(mii)); ++ break; ++ ++ case RAETH_MII_WRITE: ++ copy_from_user(&mii, ifr->ifr_data, sizeof(mii)); ++ //printk("phy %d, reg %d, val 0x%x\n", mii.phy_id, mii.reg_num, mii.val_in); ++ mii_mgr_write(mii.phy_id, mii.reg_num, mii.val_in); ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return 0; ++} ++ ++struct net_device_stats *VirtualIF_get_stats(struct net_device *dev) ++{ ++ PSEUDO_ADAPTER *pAd = netdev_priv(dev); ++ return &pAd->stat; ++} ++ ++int VirtualIF_open(struct net_device * dev) ++{ ++ PSEUDO_ADAPTER *pPesueoAd = netdev_priv(dev); ++ ++ printk("%s: ===> VirtualIF_open\n", dev->name); ++ ++#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN) || defined (CONFIG_GE_RGMII_INTERNAL_P4_AN) ++ *((volatile u32 *)(FE_INT_ENABLE2)) |= (1<<25); //enable GE2 link change intr for MT7530 delay setting ++#endif ++ ++ netif_start_queue(pPesueoAd->PseudoDev); ++ ++ return 0; ++} ++ ++int VirtualIF_close(struct net_device * dev) ++{ ++ PSEUDO_ADAPTER *pPesueoAd = netdev_priv(dev); ++ ++ printk("%s: ===> VirtualIF_close\n", dev->name); ++ ++ netif_stop_queue(pPesueoAd->PseudoDev); ++ ++ return 0; ++} ++ ++int VirtualIFSendPackets(struct sk_buff * pSkb, ++ struct net_device * dev) ++{ ++ PSEUDO_ADAPTER *pPesueoAd = netdev_priv(dev); ++ END_DEVICE *ei_local __maybe_unused; ++ ++ ++ //printk("VirtualIFSendPackets --->\n"); ++ ++ ei_local = netdev_priv(dev); ++ if (!(pPesueoAd->RaethDev->flags & IFF_UP)) { ++ dev_kfree_skb_any(pSkb); ++ return 0; ++ } ++ //pSkb->cb[40]=0x5a; ++ pSkb->dev = pPesueoAd->RaethDev; ++ ei_start_xmit(pSkb, pPesueoAd->RaethDev, 2); ++ return 0; ++} ++ ++void virtif_setup_statistics(PSEUDO_ADAPTER* pAd) ++{ ++ pAd->stat.tx_packets = 0; ++ pAd->stat.tx_bytes = 0; ++ pAd->stat.tx_dropped = 0; ++ pAd->stat.tx_errors = 0; ++ pAd->stat.tx_aborted_errors= 0; ++ pAd->stat.tx_carrier_errors= 0; ++ pAd->stat.tx_fifo_errors = 0; ++ pAd->stat.tx_heartbeat_errors = 0; ++ pAd->stat.tx_window_errors = 0; ++ ++ pAd->stat.rx_packets = 0; ++ pAd->stat.rx_bytes = 0; ++ pAd->stat.rx_dropped = 0; ++ pAd->stat.rx_errors = 0; ++ pAd->stat.rx_length_errors = 0; ++ pAd->stat.rx_over_errors = 0; ++ pAd->stat.rx_crc_errors = 0; ++ pAd->stat.rx_frame_errors = 0; ++ pAd->stat.rx_fifo_errors = 0; ++ pAd->stat.rx_missed_errors = 0; ++ ++ pAd->stat.collisions = 0; ++} ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++static const struct net_device_ops VirtualIF_netdev_ops = { ++ .ndo_open = VirtualIF_open, ++ .ndo_stop = VirtualIF_close, ++ .ndo_start_xmit = VirtualIFSendPackets, ++ .ndo_get_stats = VirtualIF_get_stats, ++ .ndo_set_mac_address = ei_set_mac2_addr, ++ .ndo_change_mtu = ei_change_mtu, ++ .ndo_do_ioctl = VirtualIF_ioctl, ++ .ndo_validate_addr = eth_validate_addr, ++}; ++#endif ++// Register pseudo interface ++void RAETH_Init_PSEUDO(pEND_DEVICE pAd, struct net_device *net_dev) ++{ ++ int index; ++ struct net_device *dev; ++ PSEUDO_ADAPTER *pPseudoAd; ++ int i = 0; ++ struct sockaddr addr; ++ unsigned char zero1[6]={0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; ++ unsigned char zero2[6]={0x00,0x00,0x00,0x00,0x00,0x00}; ++ ++ for (index = 0; index < MAX_PSEUDO_ENTRY; index++) { ++ ++ dev = alloc_etherdev(sizeof(PSEUDO_ADAPTER)); ++ if (NULL == dev) ++ { ++ printk(" alloc_etherdev for PSEUDO_ADAPTER failed.\n"); ++ return; ++ } ++ strcpy(dev->name, DEV2_NAME); ++ ++ //Get mac2 address from flash ++#ifdef RA_MTD_RW_BY_NUM ++ i = ra_mtd_read(2, GMAC2_OFFSET, 6, addr.sa_data); ++#else ++ i = ra_mtd_read_nm("Factory", GMAC2_OFFSET, 6, addr.sa_data); ++#endif ++ ++ //If reading mtd failed or mac0 is empty, generate a mac address ++ if (i < 0 || ((memcmp(addr.sa_data, zero1, 6) == 0) || (addr.sa_data[0] & 0x1)) || ++ (memcmp(addr.sa_data, zero2, 6) == 0)) { ++ unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80}; ++ // net_srandom(jiffies); ++ memcpy(addr.sa_data, mac_addr01234, 5); ++ // addr.sa_data[5] = net_random()&0xFF; ++ } ++ ++ ei_set_mac2_addr(dev, &addr); ++ ether_setup(dev); ++ pPseudoAd = netdev_priv(dev); ++ ++ pPseudoAd->PseudoDev = dev; ++ pPseudoAd->RaethDev = net_dev; ++ virtif_setup_statistics(pPseudoAd); ++ pAd->PseudoDev = dev; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ dev->netdev_ops = &VirtualIF_netdev_ops; ++#else ++ dev->hard_start_xmit = VirtualIFSendPackets; ++ dev->stop = VirtualIF_close; ++ dev->open = VirtualIF_open; ++ dev->do_ioctl = VirtualIF_ioctl; ++ dev->set_mac_address = ei_set_mac2_addr; ++ dev->get_stats = VirtualIF_get_stats; ++ dev->change_mtu = ei_change_mtu; ++ dev->mtu = 1500; ++#endif ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ dev->features |= NETIF_F_HW_CSUM; ++#else ++ dev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4 */ ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++#if defined(CONFIG_RALINK_MT7620) ++#if defined (CONFIG_RAETH_TSO) ++ if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) { ++ dev->features |= NETIF_F_SG; ++ dev->features |= NETIF_F_TSO; ++ } ++#endif // CONFIG_RAETH_TSO // ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) { ++ dev->features |= NETIF_F_TSO6; ++ dev->features |= NETIF_F_IPV6_CSUM; /* Can checksum TCP/UDP over IPv6 */ ++ } ++#endif ++#else ++#if defined (CONFIG_RAETH_TSO) ++ dev->features |= NETIF_F_SG; ++ dev->features |= NETIF_F_TSO; ++#endif // CONFIG_RAETH_TSO // ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ dev->features |= NETIF_F_TSO6; ++ dev->features |= NETIF_F_IPV6_CSUM; /* Can checksum TCP/UDP over IPv6 */ ++#endif ++#endif // CONFIG_RALINK_MT7620 // ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0) ++ dev->vlan_features = dev->features; ++#endif ++ ++ ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++ dev->ethtool_ops = &ra_virt_ethtool_ops; ++ // init mii structure ++ pPseudoAd->mii_info.dev = dev; ++ pPseudoAd->mii_info.mdio_read = mdio_virt_read; ++ pPseudoAd->mii_info.mdio_write = mdio_virt_write; ++ pPseudoAd->mii_info.phy_id_mask = 0x1f; ++ pPseudoAd->mii_info.reg_num_mask = 0x1f; ++ pPseudoAd->mii_info.phy_id = 0x1e; ++ pPseudoAd->mii_info.supports_gmii = mii_check_gmii_support(&pPseudoAd->mii_info); ++#endif ++ ++ // Register this device ++ register_netdevice(dev); ++ } ++} ++#endif ++ ++/** ++ * ei_open - Open/Initialize the ethernet port. ++ * @dev: network device to initialize ++ * ++ * This routine goes all-out, setting everything ++ * up a new at each open, even though many of these registers should only need to be set once at boot. ++ */ ++int ei_open(struct net_device *dev) ++{ ++ int i, err; ++#if !defined (CONFIG_MT7623_FPGA) ++ unsigned long flags; ++#endif ++ END_DEVICE *ei_local; ++ ++#ifdef CONFIG_RAETH_LRO ++ const char *lan_ip_tmp; ++#ifdef CONFIG_DUAL_IMAGE ++#define RT2860_NVRAM 1 ++#else ++#define RT2860_NVRAM 0 ++#endif ++#endif // CONFIG_RAETH_LRO // ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ++ if (!try_module_get(THIS_MODULE)) ++ { ++ printk("%s: Cannot reserve module\n", __FUNCTION__); ++ return -1; ++ } ++#else ++ MOD_INC_USE_COUNT; ++#endif ++ ++ printk("Raeth %s (",RAETH_VERSION); ++#if defined (CONFIG_RAETH_NAPI) ++ printk("NAPI\n"); ++#elif defined (CONFIG_RA_NETWORK_TASKLET_BH) ++ printk("Tasklet"); ++#elif defined (CONFIG_RA_NETWORK_WORKQUEUE_BH) ++ printk("Workqueue"); ++#endif ++ ++#if defined (CONFIG_RAETH_SKB_RECYCLE_2K) ++ printk(",SkbRecycle"); ++#endif ++ printk(")\n"); ++ ++ ++ ei_local = netdev_priv(dev); // get device pointer from System ++ // unsigned int flags; ++ ++ if (ei_local == NULL) ++ { ++ printk(KERN_EMERG "%s: ei_open passed a non-existent device!\n", dev->name); ++ return -ENXIO; ++ } ++ ++ /* receiving packet buffer allocation - NUM_RX_DESC x MAX_RX_LENGTH */ ++ for ( i = 0; i < NUM_RX_DESC; i++) ++ { ++#if defined (CONFIG_RAETH_SKB_RECYCLE_2K) ++ ei_local->netrx0_skbuf[i] = skbmgr_dev_alloc_skb2k(); ++#else ++ ei_local->netrx0_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN); ++#endif ++ if (ei_local->netrx0_skbuf[i] == NULL ) { ++ printk("rx skbuff buffer allocation failed!"); ++ } else { ++#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ skb_reserve(ei_local->netrx0_skbuf[i], NET_IP_ALIGN); ++#endif ++ } ++ ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ ei_local->netrx3_skbuf[i] = dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN); ++ if (ei_local->netrx3_skbuf[i] == NULL ) { ++ printk("rx3 skbuff buffer allocation failed!"); ++ } else { ++#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ skb_reserve(ei_local->netrx3_skbuf[i], NET_IP_ALIGN); ++#endif ++ } ++ ei_local->netrx2_skbuf[i] = dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN); ++ if (ei_local->netrx2_skbuf[i] == NULL ) { ++ printk("rx2 skbuff buffer allocation failed!"); ++ } else { ++#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ skb_reserve(ei_local->netrx2_skbuf[i], NET_IP_ALIGN); ++#endif ++ } ++ ei_local->netrx1_skbuf[i] = dev_alloc_skb(MAX_LRO_RX_LENGTH + NET_IP_ALIGN); ++ if (ei_local->netrx1_skbuf[i] == NULL ) { ++ printk("rx1 skbuff buffer allocation failed!"); ++ } else { ++#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ skb_reserve(ei_local->netrx1_skbuf[i], NET_IP_ALIGN); ++#endif ++ } ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++#if defined(CONFIG_ARCH_MT7623) ++ ei_local->netrx3_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN); ++ if (ei_local->netrx3_skbuf[i] == NULL ) { ++ printk("rx3 skbuff buffer allocation failed!"); ++ } else { ++#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ skb_reserve(ei_local->netrx3_skbuf[i], NET_IP_ALIGN); ++#endif ++ } ++ ei_local->netrx2_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN); ++ if (ei_local->netrx2_skbuf[i] == NULL ) { ++ printk("rx2 skbuff buffer allocation failed!"); ++ } else { ++#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ skb_reserve(ei_local->netrx2_skbuf[i], NET_IP_ALIGN); ++#endif ++ } ++#endif /* CONFIG_ARCH_MT7623 */ ++ ei_local->netrx1_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN); ++ if (ei_local->netrx1_skbuf[i] == NULL ) { ++ printk("rx1 skbuff buffer allocation failed!"); ++ } else { ++#if !defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ skb_reserve(ei_local->netrx1_skbuf[i], NET_IP_ALIGN); ++#endif ++ } ++#endif ++ } ++#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC) ++ trgmii_set_7621(); //reset FE/GMAC in this function ++#endif ++ ++ fe_dma_init(dev); ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ fe_hw_lro_init(dev); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++ fe_sw_init(); //initialize fe and switch register ++#if defined (CONFIG_MIPS) ++ err = request_irq( dev->irq, ei_interrupt, IRQF_DISABLED, dev->name, dev); // try to fix irq in open ++#else ++ err = request_irq(dev->irq, ei_interrupt, /*IRQF_TRIGGER_LOW*/ 0, dev->name, dev); // try to fix irq in open ++#endif ++ if (err) ++ return err; ++ ++ if ( dev->dev_addr != NULL) { ++ ra2880MacAddressSet((void *)(dev->dev_addr)); ++ } else { ++ printk("dev->dev_addr is empty !\n"); ++ } ++/*TODO: MT7623 MCM INT */ ++#if defined (CONFIG_RT_3052_ESW) && !defined(CONFIG_ARCH_MT7623) ++ err = request_irq(SURFBOARDINT_ESW, esw_interrupt, IRQF_DISABLED, "Ralink_ESW", dev); ++ if (err) ++ return err; ++ INIT_WORK(&ei_local->kill_sig_wq, kill_sig_workq); ++#if defined (CONFIG_RALINK_MT7621) ++ mii_mgr_write(31, 0x7008, 0x1f); //enable switch link change intr ++ ++#else ++ *((volatile u32 *)(RALINK_INTCL_BASE + 0x34)) = (1<<17); ++ *((volatile u32 *)(ESW_IMR)) &= ~(ESW_INT_ALL); ++ ++#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \ ++ defined (CONFIG_RALINK_MT7620) ++ *((volatile u32 *)(ESW_P0_IntMn)) &= ~(MSK_CNT_INT_ALL); ++ *((volatile u32 *)(ESW_P1_IntMn)) &= ~(MSK_CNT_INT_ALL); ++ *((volatile u32 *)(ESW_P2_IntMn)) &= ~(MSK_CNT_INT_ALL); ++ *((volatile u32 *)(ESW_P3_IntMn)) &= ~(MSK_CNT_INT_ALL); ++ *((volatile u32 *)(ESW_P4_IntMn)) &= ~(MSK_CNT_INT_ALL); ++ *((volatile u32 *)(ESW_P5_IntMn)) &= ~(MSK_CNT_INT_ALL); ++ *((volatile u32 *)(ESW_P6_IntMn)) &= ~(MSK_CNT_INT_ALL); ++#endif ++#if defined(CONFIG_RALINK_MT7620) ++ *((volatile u32 *)(ESW_P7_IntMn)) &= ~(MSK_CNT_INT_ALL); ++#endif ++ ++#endif ++#endif // CONFIG_RT_3052_ESW // ++ ++/*TODO*/ ++#if !defined (CONFIG_MT7623_FPGA) ++ spin_lock_irqsave(&(ei_local->page_lock), flags); ++#endif ++ ++ ++#ifdef DELAY_INT ++ sysRegWrite(RAETH_DLY_INT_CFG, DELAY_INT_INIT); ++ sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT); ++ #if defined (CONFIG_RAETH_HW_LRO) ++ sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT | ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1); ++ #endif /* CONFIG_RAETH_HW_LRO */ ++#else ++ sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_ALL); ++ #if defined (CONFIG_RAETH_HW_LRO) ++ sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_ALL | ALT_RPLC_INT3 | ALT_RPLC_INT2 | ALT_RPLC_INT1); ++ #endif /* CONFIG_RAETH_HW_LRO */ ++#endif ++ ++#ifdef CONFIG_RAETH_QDMA ++#ifdef DELAY_INT ++ sysRegWrite(QDMA_DELAY_INT, DELAY_INT_INIT); ++ sysRegWrite(QFE_INT_ENABLE, QFE_INT_DLY_INIT); ++#else ++ sysRegWrite(QFE_INT_ENABLE, QFE_INT_ALL); ++ ++#endif ++#endif ++ ++ INIT_WORK(&ei_local->reset_task, ei_reset_task); ++ ++#ifdef WORKQUEUE_BH ++#ifndef CONFIG_RAETH_NAPI ++ INIT_WORK(&ei_local->rx_wq, ei_receive_workq); ++#endif // CONFIG_RAETH_NAPI // ++#else ++#ifndef CONFIG_RAETH_NAPI ++#if defined (TASKLET_WORKQUEUE_SW) ++ working_schedule = init_schedule; ++ INIT_WORK(&ei_local->rx_wq, ei_receive_workq); ++ tasklet_init(&ei_local->rx_tasklet, ei_receive_workq, 0); ++#else ++ tasklet_init(&ei_local->rx_tasklet, ei_receive, 0); ++#endif ++#endif // CONFIG_RAETH_NAPI // ++#endif // WORKQUEUE_BH // ++ ++ netif_start_queue(dev); ++ ++#ifdef CONFIG_RAETH_NAPI ++ atomic_dec(&ei_local->irq_sem); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ napi_enable(&ei_local->napi); ++#else ++ netif_poll_enable(dev); ++#endif ++#endif ++//*TODO*/ ++#if !defined (CONFIG_MT7623_FPGA) ++ spin_unlock_irqrestore(&(ei_local->page_lock), flags); ++#endif ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if(ei_local->PseudoDev == NULL) { ++ RAETH_Init_PSEUDO(ei_local, dev); ++ } ++ ++ if(ei_local->PseudoDev == NULL) ++ printk("Open PseudoDev failed.\n"); ++ else ++ VirtualIF_open(ei_local->PseudoDev); ++ ++#endif ++ ++#ifdef CONFIG_RAETH_LRO ++ lan_ip_tmp = nvram_get(RT2860_NVRAM, "lan_ipaddr"); ++ str_to_ip(&lan_ip, lan_ip_tmp); ++ lro_para.lan_ip1 = lan_ip = htonl(lan_ip); ++#endif // CONFIG_RAETH_LRO // ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ INIT_WORK(&ei_local->hw_lro_wq, ei_hw_lro_workq); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++ forward_config(dev); ++ return 0; ++} ++ ++/** ++ * ei_close - shut down network device ++ * @dev: network device to clear ++ * ++ * This routine shut down network device. ++ * ++ * ++ */ ++int ei_close(struct net_device *dev) ++{ ++ int i; ++ END_DEVICE *ei_local = netdev_priv(dev); // device pointer ++ ++ netif_stop_queue(dev); ++ ra2880stop(ei_local); ++ ++ free_irq(dev->irq, dev); ++ ++/*TODO: MT7623 MCM INT */ ++#if defined (CONFIG_RT_3052_ESW) && !defined(CONFIG_ARCH_MT7623) ++ free_irq(SURFBOARDINT_ESW, dev); ++#endif ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ cancel_work_sync(&ei_local->reset_task); ++#endif ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ VirtualIF_close(ei_local->PseudoDev); ++#endif ++ ++ ++#ifdef WORKQUEUE_BH ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ cancel_work_sync(&ei_local->rx_wq); ++#endif ++#else ++#if defined (TASKLET_WORKQUEUE_SW) ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ cancel_work_sync(&ei_local->rx_wq); ++#endif ++#endif ++ tasklet_kill(&ei_local->tx_tasklet); ++ tasklet_kill(&ei_local->rx_tasklet); ++#endif // WORKQUEUE_BH // ++ ++#ifdef CONFIG_RAETH_NAPI ++ atomic_inc(&ei_local->irq_sem); ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ napi_disable(&ei_local->napi); ++#else ++ netif_poll_disable(dev); ++#endif ++#endif ++ ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++ cancel_work_sync(&ei_local->hw_lro_wq); ++#endif /* CONFIG_RAETH_HW_LRO */ ++ ++ for ( i = 0; i < NUM_RX_DESC; i++) ++ { ++ if (ei_local->netrx0_skbuf[i] != NULL) { ++ dev_kfree_skb(ei_local->netrx0_skbuf[i]); ++ ei_local->netrx0_skbuf[i] = NULL; ++ } ++#if defined (CONFIG_RAETH_HW_LRO) ++ if (ei_local->netrx3_skbuf[i] != NULL) { ++ dev_kfree_skb(ei_local->netrx3_skbuf[i]); ++ ei_local->netrx3_skbuf[i] = NULL; ++ } ++ if (ei_local->netrx2_skbuf[i] != NULL) { ++ dev_kfree_skb(ei_local->netrx2_skbuf[i]); ++ ei_local->netrx2_skbuf[i] = NULL; ++ } ++ if (ei_local->netrx1_skbuf[i] != NULL) { ++ dev_kfree_skb(ei_local->netrx1_skbuf[i]); ++ ei_local->netrx1_skbuf[i] = NULL; ++ } ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++#if defined(CONFIG_ARCH_MT7623) ++ if (ei_local->netrx3_skbuf[i] != NULL) { ++ dev_kfree_skb(ei_local->netrx3_skbuf[i]); ++ ei_local->netrx3_skbuf[i] = NULL; ++ } ++ if (ei_local->netrx2_skbuf[i] != NULL) { ++ dev_kfree_skb(ei_local->netrx2_skbuf[i]); ++ ei_local->netrx2_skbuf[i] = NULL; ++ } ++#endif /* CONFIG_ARCH_MT7623 */ ++ if (ei_local->netrx1_skbuf[i] != NULL) { ++ dev_kfree_skb(ei_local->netrx1_skbuf[i]); ++ ei_local->netrx1_skbuf[i] = NULL; ++ } ++#endif ++ } ++ ++ for ( i = 0; i < NUM_TX_DESC; i++) ++ { ++ if((ei_local->skb_free[i]!=(struct sk_buff *)0xFFFFFFFF) && (ei_local->skb_free[i]!= 0)) ++ { ++ dev_kfree_skb_any(ei_local->skb_free[i]); ++ } ++ } ++ ++ /* TX Ring */ ++#ifdef CONFIG_RAETH_QDMA ++ if (ei_local->txd_pool != NULL) { ++ pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct QDMA_txdesc), ei_local->txd_pool, ei_local->phy_txd_pool); ++ } ++ if (ei_local->free_head != NULL){ ++ pci_free_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), ei_local->free_head, ei_local->phy_free_head); ++ } ++ if (ei_local->free_page_head != NULL){ ++ pci_free_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, ei_local->free_page_head, ei_local->phy_free_page_head); ++ } ++#else ++ if (ei_local->tx_ring0 != NULL) { ++ pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0); ++ } ++#endif ++ ++#if defined (CONFIG_RAETH_QOS) ++ if (ei_local->tx_ring1 != NULL) { ++ pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring1, ei_local->phy_tx_ring1); ++ } ++ ++#if !defined (CONFIG_RALINK_RT2880) ++ if (ei_local->tx_ring2 != NULL) { ++ pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring2, ei_local->phy_tx_ring2); ++ } ++ ++ if (ei_local->tx_ring3 != NULL) { ++ pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring3, ei_local->phy_tx_ring3); ++ } ++#endif ++#endif ++ /* RX Ring */ ++#ifdef CONFIG_32B_DESC ++ kfree(ei_local->rx_ring0); ++#else ++ pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring0, ei_local->phy_rx_ring0); ++#endif ++#if defined CONFIG_RAETH_QDMA && !defined(CONFIG_RAETH_QDMATX_QDMARX) ++#ifdef CONFIG_32B_DESC ++ kfree(ei_local->qrx_ring); ++#else ++ pci_free_consistent(NULL, NUM_QRX_DESC*sizeof(struct PDMA_rxdesc), ei_local->qrx_ring, ei_local->phy_qrx_ring); ++#endif ++#endif ++#if defined (CONFIG_RAETH_HW_LRO) ++ pci_free_consistent(NULL, NUM_LRO_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring3, ei_local->phy_rx_ring3); ++ pci_free_consistent(NULL, NUM_LRO_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring2, ei_local->phy_rx_ring2); ++ pci_free_consistent(NULL, NUM_LRO_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring1, ei_local->phy_rx_ring1); ++#elif defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++#ifdef CONFIG_32B_DESC ++ kfree(ei_local->rx_ring1); ++#else ++#if defined(CONFIG_ARCH_MT7623) ++ pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring3, ei_local->phy_rx_ring3); ++ pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring2, ei_local->phy_rx_ring2); ++#endif /* CONFIG_ARCH_MT7623 */ ++ pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring1, ei_local->phy_rx_ring1); ++#endif ++#endif ++ ++ printk("Free TX/RX Ring Memory!\n"); ++ ++ fe_reset(); ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) ++ module_put(THIS_MODULE); ++#else ++ MOD_DEC_USE_COUNT; ++#endif ++ return 0; ++} ++ ++#if defined (CONFIG_RT6855A_FPGA) ++void rt6855A_eth_gpio_reset(void) ++{ ++ u8 ether_gpio = 12; ++ ++ /* Load the ethernet gpio value to reset Ethernet PHY */ ++ *(unsigned long *)(RALINK_PIO_BASE + 0x00) |= 1<<(ether_gpio<<1); ++ *(unsigned long *)(RALINK_PIO_BASE + 0x14) |= 1<<(ether_gpio); ++ *(unsigned long *)(RALINK_PIO_BASE + 0x04) &= ~(1< PortPageSel, 1=local, 0=global ++ * Bit 14:12 => PageSel, local:0~3, global:0~4 ++ * ++ *Reg16~30:Local/Global registers ++ * ++ */ ++ /*correct PHY setting J8.0*/ ++ mii_mgr_read(0, 31, &rev); ++ rev &= (0x0f); ++ ++ mii_mgr_write(1, 31, 0x4000); //global, page 4 ++ ++ mii_mgr_write(1, 16, 0xd4cc); ++ mii_mgr_write(1, 17, 0x7444); ++ mii_mgr_write(1, 19, 0x0112); ++ mii_mgr_write(1, 21, 0x7160); ++ mii_mgr_write(1, 22, 0x10cf); ++ mii_mgr_write(1, 26, 0x0777); ++ ++ if(rev == 0){ ++ mii_mgr_write(1, 25, 0x0102); ++ mii_mgr_write(1, 29, 0x8641); ++ } ++ else{ ++ mii_mgr_write(1, 25, 0x0212); ++ mii_mgr_write(1, 29, 0x4640); ++ } ++ ++ mii_mgr_write(1, 31, 0x2000); //global, page 2 ++ mii_mgr_write(1, 21, 0x0655); ++ mii_mgr_write(1, 22, 0x0fd3); ++ mii_mgr_write(1, 23, 0x003d); ++ mii_mgr_write(1, 24, 0x096e); ++ mii_mgr_write(1, 25, 0x0fed); ++ mii_mgr_write(1, 26, 0x0fc4); ++ ++ mii_mgr_write(1, 31, 0x1000); //global, page 1 ++ mii_mgr_write(1, 17, 0xe7f8); ++ ++ ++ mii_mgr_write(1, 31, 0xa000); //local, page 2 ++ ++ mii_mgr_write(0, 16, 0x0e0e); ++ mii_mgr_write(1, 16, 0x0c0c); ++ mii_mgr_write(2, 16, 0x0f0f); ++ mii_mgr_write(3, 16, 0x1010); ++ mii_mgr_write(4, 16, 0x0909); ++ ++ mii_mgr_write(0, 17, 0x0000); ++ mii_mgr_write(1, 17, 0x0000); ++ mii_mgr_write(2, 17, 0x0000); ++ mii_mgr_write(3, 17, 0x0000); ++ mii_mgr_write(4, 17, 0x0000); ++#endif ++ ++#if defined (CONFIG_RT6855A_ASIC) ++ ++#if defined (CONFIG_P5_RGMII_TO_MAC_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e33b;//(P5, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x7014) = 0x1f0c000c;//disable port0-port4 internal phy, set phy base address to 12 ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x250c) = 0x000fff10;//disable port5 mac learning ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x260c) = 0x000fff10;//disable port6 mac learning ++ ++#elif defined (CONFIG_P5_MII_TO_MAC_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++#elif defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ //rt6855/6 need to modify TX/RX phase ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x7014) = 0xc;//TX/RX CLOCK Phase select ++ ++ enable_auto_negotiate(1); ++ ++ if (isICPlusGigaPHY(1)) { ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, &phy_val); ++ phy_val |= 1<<10; //enable pause ability ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, phy_val); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val); ++ phy_val |= 1<<9; //restart AN ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val); ++ } ++ ++ if (isMarvellGigaPHY(1)) { ++ printk("Reset MARVELL phy1\n"); ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &phy_val); ++ phy_val |= 1<<7; //Add delay to RX_CLK for RXD Outputs ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, phy_val); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val); ++ phy_val |= 1<<15; //PHY Software Reset ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val); ++ } ++ if (isVtssGigaPHY(1)) { ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0001); //extended page ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &phy_val); ++ printk("Vitesse phy skew: %x --> ", phy_val); ++ phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns ++ phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns ++ printk("%x\n", phy_val); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, phy_val); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0000); //main registers ++ } ++#elif defined (CONFIG_P5_RMII_TO_MAC_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++#else // Port 5 Disabled // ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x8000;//link down ++#endif ++#endif ++} ++#endif ++ ++ ++ ++ ++#if defined (CONFIG_MT7623_FPGA) ++void setup_fpga_gsw(void) ++{ ++ u32 i; ++ u32 regValue; ++ ++ /* reduce RGMII2 PAD driving strength */ ++ *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4); ++ ++ //RGMII1=Normal mode ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14); ++ ++ //GMAC1= RGMII mode ++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12); ++ ++ //enable MDIO to control MT7530 ++ regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60)); ++ regValue &= ~(0x3 << 12); ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue; ++ ++ for(i=0;i<=4;i++) ++ { ++ //turn off PHY ++ mii_mgr_read(i, 0x0 ,®Value); ++ regValue |= (0x1<<11); ++ mii_mgr_write(i, 0x0, regValue); ++ } ++ mii_mgr_write(31, 0x7000, 0x3); //reset switch ++ udelay(10); ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e337);//(GE1, Force 100M/FD, FC ON) ++ mii_mgr_write(31, 0x3600, 0x5e337); ++ ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down) ++ mii_mgr_write(31, 0x3500, 0x8000); ++ ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/ ++ mii_mgr_read(31, 0x7804 ,®Value); ++ regValue &= ~(1<<8); //Enable Port 6 ++ regValue |= (1<<6); //Disable Port 5 ++ regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY ++ ++#if defined (CONFIG_RAETH_GMAC2) ++ //RGMII2=Normal mode ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15); ++ ++ //GMAC2= RGMII mode ++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14); ++ ++ mii_mgr_write(31, 0x3500, 0x56300); //MT7530 P5 AN, we can ignore this setting?????? ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(GE2, auto-polling) ++ ++ enable_auto_negotiate(0);//set polling address ++ /* set MT7530 Port 5 to PHY 0/4 mode */ ++#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN) ++ regValue &= ~((1<<13)|(1<<6)); ++ regValue |= ((1<<7)|(1<<16)|(1<<20)); ++#elif defined (CONFIG_GE_RGMII_INTERNAL_P4_AN) ++ regValue &= ~((1<<13)|(1<<6)|((1<<20))); ++ regValue |= ((1<<7)|(1<<16)); ++#endif ++ ++ //sysRegWrite(GDMA2_FWD_CFG, 0x20710000); ++#endif ++ regValue |= (1<<16);//change HW-TRAP ++ printk("change HW-TRAP to 0x%x\n",regValue); ++ mii_mgr_write(31, 0x7804 ,regValue); ++#endif ++ mii_mgr_write(0, 14, 0x1); /*RGMII*/ ++/* set MT7530 central align */ ++ mii_mgr_read(31, 0x7830, ®Value); ++ regValue &= ~1; ++ regValue |= 1<<1; ++ mii_mgr_write(31, 0x7830, regValue); ++ ++ mii_mgr_read(31, 0x7a40, ®Value); ++ regValue &= ~(1<<30); ++ mii_mgr_write(31, 0x7a40, regValue); ++ ++ regValue = 0x855; ++ mii_mgr_write(31, 0x7a78, regValue); ++ ++/*to check!!*/ ++ mii_mgr_write(31, 0x7b00, 0x102); //delay setting for 10/1000M ++ mii_mgr_write(31, 0x7b04, 0x14); //delay setting for 10/1000M ++ ++ for(i=0;i<=4;i++) { ++ mii_mgr_read(i, 4, ®Value); ++ regValue |= (3<<7); //turn on 100Base-T Advertisement ++ //regValue &= ~(3<<7); //turn off 100Base-T Advertisement ++ mii_mgr_write(i, 4, regValue); ++ ++ mii_mgr_read(i, 9, ®Value); ++ //regValue |= (3<<8); //turn on 1000Base-T Advertisement ++ regValue &= ~(3<<8); //turn off 1000Base-T Advertisement ++ mii_mgr_write(i, 9, regValue); ++ ++ //restart AN ++ mii_mgr_read(i, 0, ®Value); ++ regValue |= (1 << 9); ++ mii_mgr_write(i, 0, regValue); ++ } ++ ++ /*Tx Driving*/ ++ mii_mgr_write(31, 0x7a54, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a5c, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a64, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a6c, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a74, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a7c, 0x44); //lower driving ++ ++ for(i=0;i<=4;i++) ++ { ++ //turn on PHY ++ mii_mgr_read(i, 0x0 ,®Value); ++ regValue &= ~(0x1<<11); ++ mii_mgr_write(i, 0x0, regValue); ++ } ++} ++#endif ++ ++ ++#if defined (CONFIG_RALINK_MT7621) ++ ++ ++void setup_external_gsw(void) ++{ ++ u32 regValue; ++ ++ /* reduce RGMII2 PAD driving strength */ ++ *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4); ++ //enable MDIO ++ regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60)); ++ regValue &= ~(0x3 << 12); ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue; ++ ++ //RGMII1=Normal mode ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14); ++ //GMAC1= RGMII mode ++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12); ++ ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x00008000);//(GE1, Link down) ++ ++ //RGMII2=Normal mode ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15); ++ //GMAC2= RGMII mode ++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14); ++ ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x2105e33b);//(GE2, Force 1000M/FD, FC ON) ++ ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++void IsSwitchVlanTableBusy(void) ++{ ++ int j = 0; ++ unsigned int value = 0; ++ ++ for (j = 0; j < 20; j++) { ++ mii_mgr_read(31, 0x90, &value); ++ if ((value & 0x80000000) == 0 ){ //table busy ++ break; ++ } ++ udelay(70000); ++ } ++ if (j == 20) ++ printk("set vlan timeout value=0x%x.\n", value); ++} ++ ++void LANWANPartition(void) ++{ ++/*Set MT7530 */ ++#ifdef CONFIG_WAN_AT_P0 ++ printk("set LAN/WAN WLLLL\n"); ++ //WLLLL, wan at P0 ++ //LAN/WAN ports as security mode ++ mii_mgr_write(31, 0x2004, 0xff0003);//port0 ++ mii_mgr_write(31, 0x2104, 0xff0003);//port1 ++ mii_mgr_write(31, 0x2204, 0xff0003);//port2 ++ mii_mgr_write(31, 0x2304, 0xff0003);//port3 ++ mii_mgr_write(31, 0x2404, 0xff0003);//port4 ++ ++ //set PVID ++ mii_mgr_write(31, 0x2014, 0x10002);//port0 ++ mii_mgr_write(31, 0x2114, 0x10001);//port1 ++ mii_mgr_write(31, 0x2214, 0x10001);//port2 ++ mii_mgr_write(31, 0x2314, 0x10001);//port3 ++ mii_mgr_write(31, 0x2414, 0x10001);//port4 ++ /*port6 */ ++ //VLAN member ++ IsSwitchVlanTableBusy(); ++ mii_mgr_write(31, 0x94, 0x407e0001);//VAWD1 ++ mii_mgr_write(31, 0x90, 0x80001001);//VTCR, VID=1 ++ IsSwitchVlanTableBusy(); ++ ++ mii_mgr_write(31, 0x94, 0x40610001);//VAWD1 ++ mii_mgr_write(31, 0x90, 0x80001002);//VTCR, VID=2 ++ IsSwitchVlanTableBusy(); ++#endif ++#ifdef CONFIG_WAN_AT_P4 ++ printk("set LAN/WAN LLLLW\n"); ++ //LLLLW, wan at P4 ++ //LAN/WAN ports as security mode ++ mii_mgr_write(31, 0x2004, 0xff0003);//port0 ++ mii_mgr_write(31, 0x2104, 0xff0003);//port1 ++ mii_mgr_write(31, 0x2204, 0xff0003);//port2 ++ mii_mgr_write(31, 0x2304, 0xff0003);//port3 ++ mii_mgr_write(31, 0x2404, 0xff0003);//port4 ++ ++ //set PVID ++ mii_mgr_write(31, 0x2014, 0x10001);//port0 ++ mii_mgr_write(31, 0x2114, 0x10001);//port1 ++ mii_mgr_write(31, 0x2214, 0x10001);//port2 ++ mii_mgr_write(31, 0x2314, 0x10001);//port3 ++ mii_mgr_write(31, 0x2414, 0x10002);//port4 ++ ++ //VLAN member ++ IsSwitchVlanTableBusy(); ++ mii_mgr_write(31, 0x94, 0x404f0001);//VAWD1 ++ mii_mgr_write(31, 0x90, 0x80001001);//VTCR, VID=1 ++ IsSwitchVlanTableBusy(); ++ mii_mgr_write(31, 0x94, 0x40500001);//VAWD1 ++ mii_mgr_write(31, 0x90, 0x80001002);//VTCR, VID=2 ++ IsSwitchVlanTableBusy(); ++#endif ++} ++ ++#if defined (CONFIG_RAETH_8023AZ_EEE) && defined (CONFIG_RALINK_MT7621) ++void mt7621_eee_patch(void) ++{ ++ u32 i; ++ ++ for(i=0;i<5;i++) ++ { ++ /* Enable EEE */ ++ mii_mgr_write(i, 13, 0x07); ++ mii_mgr_write(i, 14, 0x3c); ++ mii_mgr_write(i, 13, 0x4007); ++ mii_mgr_write(i, 14, 0x6); ++ ++ /* Forced Slave mode */ ++ mii_mgr_write(i, 31, 0x0); ++ mii_mgr_write(i, 9, 0x1600); ++ /* Increase SlvDPSready time */ ++ mii_mgr_write(i, 31, 0x52b5); ++ mii_mgr_write(i, 16, 0xafae); ++ mii_mgr_write(i, 18, 0x2f); ++ mii_mgr_write(i, 16, 0x8fae); ++ /* Incease post_update_timer */ ++ mii_mgr_write(i, 31, 0x3); ++ mii_mgr_write(i, 17, 0x4b); ++ /* Adjust 100_mse_threshold */ ++ mii_mgr_write(i, 13, 0x1e); ++ mii_mgr_write(i, 14, 0x123); ++ mii_mgr_write(i, 13, 0x401e); ++ mii_mgr_write(i, 14, 0xffff); ++ /* Disable mcc ++ mii_mgr_write(i, 13, 0x1e); ++ mii_mgr_write(i, 14, 0xa6); ++ mii_mgr_write(i, 13, 0x401e); ++ mii_mgr_write(i, 14, 0x300); ++ */ ++ } ++ ++} ++#endif ++ ++ ++#if defined (CONFIG_RALINK_MT7621) ++void setup_internal_gsw(void) ++{ ++ u32 i; ++ u32 regValue; ++ ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ /*Hardware reset Switch*/ ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x34) |= (0x1 << 2); ++ udelay(1000); ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x34) &= ~(0x1 << 2); ++ udelay(10000); ++ ++ /* reduce RGMII2 PAD driving strength */ ++ *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4); ++ ++ //RGMII1=Normal mode ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14); ++ ++ //GMAC1= RGMII mode ++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12); ++ ++ //enable MDIO to control MT7530 ++ regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60)); ++ regValue &= ~(0x3 << 12); ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue; ++ ++ for(i=0;i<=4;i++) ++ { ++ //turn off PHY ++ mii_mgr_read(i, 0x0 ,®Value); ++ regValue |= (0x1<<11); ++ mii_mgr_write(i, 0x0, regValue); ++ } ++ mii_mgr_write(31, 0x7000, 0x3); //reset switch ++ udelay(100); ++ ++ ++#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC) ++ trgmii_set_7530(); //reset FE, config MDIO again ++ ++ //enable MDIO to control MT7530 ++ regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60)); ++ regValue &= ~(0x3 << 12); ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue; ++ ++ // switch to APLL if TRGMII and DDR2 ++ if ((sysRegRead(0xBE000010)>>4)&0x1) ++ { ++ apll_xtal_enable(); ++ } ++#endif ++ ++#if defined (CONFIG_MT7621_ASIC) ++ if((sysRegRead(0xbe00000c)&0xFFFF)==0x0101) { ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e30b);//(GE1, Force 1000M/FD, FC ON) ++ mii_mgr_write(31, 0x3600, 0x5e30b); ++ } else { ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e33b);//(GE1, Force 1000M/FD, FC ON) ++ mii_mgr_write(31, 0x3600, 0x5e33b); ++ } ++#elif defined (CONFIG_MT7621_FPGA) ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e337);//(GE1, Force 100M/FD, FC ON) ++ mii_mgr_write(31, 0x3600, 0x5e337); ++#endif ++ ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down) ++#endif ++ ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/ ++ mii_mgr_read(31, 0x7804 ,®Value); ++ regValue &= ~(1<<8); //Enable Port 6 ++ regValue |= (1<<6); //Disable Port 5 ++ regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY ++ ++#if defined (CONFIG_RAETH_GMAC2) ++ //RGMII2=Normal mode ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15); ++ ++ //GMAC2= RGMII mode ++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14); ++#if !defined (CONFIG_RAETH_8023AZ_EEE) ++ mii_mgr_write(31, 0x3500, 0x56300); //MT7530 P5 AN, we can ignore this setting?????? ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(GE2, auto-polling) ++ ++ enable_auto_negotiate(0);//set polling address ++#endif ++#if defined (CONFIG_RAETH_8023AZ_EEE) ++ mii_mgr_write(31, 0x3500, 0x5e33b); //MT7530 P5 Force 1000, we can ignore this setting?????? ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x2105e33b);//(GE2, Force 1000) ++#endif ++ ++ ++ ++ /* set MT7530 Port 5 to PHY 0/4 mode */ ++#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN) ++ regValue &= ~((1<<13)|(1<<6)); ++ regValue |= ((1<<7)|(1<<16)|(1<<20)); ++#elif defined (CONFIG_GE_RGMII_INTERNAL_P4_AN) ++ regValue &= ~((1<<13)|(1<<6)|(1<<20)); ++ regValue |= ((1<<7)|(1<<16)); ++#endif ++ ++#if defined (CONFIG_RAETH_8023AZ_EEE) ++ regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY ++#endif ++ //sysRegWrite(GDMA2_FWD_CFG, 0x20710000); ++#endif ++ regValue |= (1<<16);//change HW-TRAP ++ //printk("change HW-TRAP to 0x%x\n",regValue); ++ mii_mgr_write(31, 0x7804 ,regValue); ++#endif ++ mii_mgr_read(31, 0x7800, ®Value); ++ regValue = (regValue >> 9) & 0x3; ++ if(regValue == 0x3) { //25Mhz Xtal ++ /* do nothing */ ++ } else if(regValue == 0x2) { //40Mhz ++ ++ mii_mgr_write(0, 13, 0x1f); // disable MT7530 core clock ++ mii_mgr_write(0, 14, 0x410); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x0); ++ ++ mii_mgr_write(0, 13, 0x1f); // disable MT7530 PLL ++ mii_mgr_write(0, 14, 0x40d); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x2020); ++ ++ mii_mgr_write(0, 13, 0x1f); // for MT7530 core clock = 500Mhz ++ mii_mgr_write(0, 14, 0x40e); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x119); ++ ++ mii_mgr_write(0, 13, 0x1f); // enable MT7530 PLL ++ mii_mgr_write(0, 14, 0x40d); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x2820); ++ ++ udelay(20); //suggest by CD ++ ++ mii_mgr_write(0, 13, 0x1f); // enable MT7530 core clock ++ mii_mgr_write(0, 14, 0x410); ++ mii_mgr_write(0, 13, 0x401f); ++ }else { //20Mhz Xtal ++ ++ /* TODO */ ++ ++ } ++#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC) ++ mii_mgr_write(0, 14, 0x3); /*TRGMII*/ ++#else ++ mii_mgr_write(0, 14, 0x1); /*RGMII*/ ++/* set MT7530 central align */ ++ mii_mgr_read(31, 0x7830, ®Value); ++ regValue &= ~1; ++ regValue |= 1<<1; ++ mii_mgr_write(31, 0x7830, regValue); ++ ++ mii_mgr_read(31, 0x7a40, ®Value); ++ regValue &= ~(1<<30); ++ mii_mgr_write(31, 0x7a40, regValue); ++ ++ regValue = 0x855; ++ mii_mgr_write(31, 0x7a78, regValue); ++ ++#endif ++#if !defined (CONFIG_RAETH_8023AZ_EEE) ++ mii_mgr_write(31, 0x7b00, 0x102); //delay setting for 10/1000M ++ mii_mgr_write(31, 0x7b04, 0x14); //delay setting for 10/1000M ++#endif ++#if 0 ++ for(i=0;i<=4;i++) { ++ mii_mgr_read(i, 4, ®Value); ++ regValue |= (3<<7); //turn on 100Base-T Advertisement ++ //regValue &= ~(3<<7); //turn off 100Base-T Advertisement ++ mii_mgr_write(i, 4, regValue); ++ ++ mii_mgr_read(i, 9, ®Value); ++ regValue |= (3<<8); //turn on 1000Base-T Advertisement ++ //regValue &= ~(3<<8); //turn off 1000Base-T Advertisement ++ mii_mgr_write(i, 9, regValue); ++ ++ //restart AN ++ mii_mgr_read(i, 0, ®Value); ++ regValue |= (1 << 9); ++ mii_mgr_write(i, 0, regValue); ++ } ++#endif ++ ++ /*Tx Driving*/ ++ mii_mgr_write(31, 0x7a54, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a5c, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a64, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a6c, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a74, 0x44); //lower driving ++ mii_mgr_write(31, 0x7a7c, 0x44); //lower driving ++ ++ ++ LANWANPartition(); ++ ++#if !defined (CONFIG_RAETH_8023AZ_EEE) ++ //disable EEE ++ for(i=0;i<=4;i++) ++ { ++ mii_mgr_write(i, 13, 0x7); ++ mii_mgr_write(i, 14, 0x3C); ++ mii_mgr_write(i, 13, 0x4007); ++ mii_mgr_write(i, 14, 0x0); ++ } ++ ++ //Disable EEE 10Base-Te: ++ for(i=0;i<=4;i++) ++ { ++ mii_mgr_write(i, 13, 0x1f); ++ mii_mgr_write(i, 14, 0x027b); ++ mii_mgr_write(i, 13, 0x401f); ++ mii_mgr_write(i, 14, 0x1177); ++ } ++#endif ++ ++ for(i=0;i<=4;i++) ++ { ++ //turn on PHY ++ mii_mgr_read(i, 0x0 ,®Value); ++ regValue &= ~(0x1<<11); ++ mii_mgr_write(i, 0x0, regValue); ++ } ++ ++ mii_mgr_read(31, 0x7808 ,®Value); ++ regValue |= (3<<16); //Enable INTR ++ mii_mgr_write(31, 0x7808 ,regValue); ++#if defined (CONFIG_RAETH_8023AZ_EEE) && defined (CONFIG_RALINK_MT7621) ++ mt7621_eee_patch(); ++#endif ++} ++#endif ++ ++#if defined (CONFIG_GE1_TRGMII_FORCE_1200) ++void apll_xtal_enable(void) ++{ ++ unsigned long data = 0; ++ unsigned long regValue = 0; ++ ++ /* Firstly, reset all required register to default value */ ++ sysRegWrite(RALINK_ANA_CTRL_BASE, 0x00008000); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x0014, 0x01401d61); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x0018, 0x38233d0e); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, 0x80120004); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48); ++ ++ /* toggle RG_XPTL_CHG */ ++ sysRegWrite(RALINK_ANA_CTRL_BASE, 0x00008800); ++ sysRegWrite(RALINK_ANA_CTRL_BASE, 0x00008c00); ++ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x0014); ++ data &= ~(0x0000ffc0); ++ ++ regValue = *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x10); ++ regValue = (regValue >> 6) & 0x7; ++ if(regValue < 6) { //20/40Mhz Xtal ++ data |= REGBIT(0x1d, 8); ++ }else { ++ data |= REGBIT(0x17, 8); ++ } ++ ++ if(regValue < 6) { //20/40Mhz Xtal ++ data |= REGBIT(0x1, 6); ++ } ++ ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x0014, data); ++ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x0018); ++ data &= ~(0xf0773f00); ++ data |= REGBIT(0x3, 28); ++ data |= REGBIT(0x2, 20); ++ if(regValue < 6) { //20/40Mhz Xtal ++ data |= REGBIT(0x3, 16); ++ }else { ++ data |= REGBIT(0x2, 16); ++ } ++ data |= REGBIT(0x3, 12); ++ ++ if(regValue < 6) { //20/40Mhz Xtal ++ data |= REGBIT(0xd, 8); ++ }else { ++ data |= REGBIT(0x7, 8); ++ } ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x0018, data); ++ ++ if(regValue < 6) { //20/40Mhz Xtal ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x0020, 0x1c7dbf48); ++ }else { ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x0020, 0x1697cc39); ++ } ++ //*Common setting - Set PLLGP_CTRL_4 *// ++ ///* 1. Bit 31 */ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c); ++ data &= ~(REGBIT(0x1, 31)); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data); ++ ++ /* 2. Bit 0 */ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c); ++ data |= REGBIT(0x1, 0); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data); ++ ++ /* 3. Bit 3 */ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c); ++ data |= REGBIT(0x1, 3); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data); ++ ++ /* 4. Bit 8 */ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c); ++ data |= REGBIT(0x1, 8); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data); ++ ++ /* 5. Bit 6 */ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c); ++ data |= REGBIT(0x1, 6); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data); ++ ++ /* 6. Bit 7 */ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c); ++ data |= REGBIT(0x1, 5); ++ data |= REGBIT(0x1, 7); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data); ++ ++ /* 7. Bit 17 */ ++ data = sysRegRead(RALINK_ANA_CTRL_BASE+0x001c); ++ data &= ~REGBIT(0x1, 17); ++ sysRegWrite(RALINK_ANA_CTRL_BASE+0x001c, data); ++ ++ /* 8. TRGMII TX CLK SEL APLL */ ++ data = sysRegRead(0xbe00002c); ++ data &= 0xffffff9f; ++ data |= 0x40; ++ sysRegWrite(0xbe00002c, data); ++ ++} ++#endif ++ ++#endif ++#if defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_MT7620) ++void rt_gsw_init(void) ++{ ++#if defined (CONFIG_P4_MAC_TO_PHY_MODE) || defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ u32 phy_val=0; ++#endif ++#if defined (CONFIG_RT6855_FPGA) || defined (CONFIG_MT7620_FPGA) ++ u32 i=0; ++#elif defined (CONFIG_MT7620_ASIC) ++ u32 is_BGA=0; ++#endif ++#if defined (CONFIG_P5_RGMII_TO_MT7530_MODE) ++ unsigned int regValue = 0; ++#endif ++#if defined (CONFIG_RT6855_FPGA) || defined (CONFIG_MT7620_FPGA) ++ /*keep dump switch mode */ ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3000) = 0x5e333;//(P0, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3100) = 0x5e333;//(P1, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3200) = 0x5e333;//(P2, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3300) = 0x5e333;//(P3, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON) ++#if defined (CONFIG_RAETH_HAS_PORT4) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x5e337;//(P4, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++#else ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x5e333;//(P4, Force mode, Link Up, 10Mbps, Full-Duplex, FC ON) ++#endif ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++ ++ /* In order to use 10M/Full on FPGA board. We configure phy capable to ++ * 10M Full/Half duplex, so we can use auto-negotiation on PC side */ ++#if defined (CONFIG_RAETH_HAS_PORT4) ++ for(i=0;i<4;i++){ ++#else ++ for(i=0;i<5;i++){ ++#endif ++ mii_mgr_write(i, 4, 0x0461); //Capable of 10M Full/Half Duplex, flow control on/off ++ mii_mgr_write(i, 0, 0xB100); //reset all digital logic, except phy_reg ++ } ++ ++#endif ++ ++#if defined (CONFIG_PDMA_NEW) ++ *(unsigned long *)(SYSCFG1) |= (0x1 << 8); //PCIE_RC_MODE=1 ++#endif ++ ++ ++#if defined (CONFIG_MT7620_ASIC) && !defined (CONFIG_P5_RGMII_TO_MT7530_MODE) ++ is_BGA = (sysRegRead(RALINK_SYSCTL_BASE + 0xc) >> 16) & 0x1; ++ /* ++ * Reg 31: Page Control ++ * Bit 15 => PortPageSel, 1=local, 0=global ++ * Bit 14:12 => PageSel, local:0~3, global:0~4 ++ * ++ * Reg16~30:Local/Global registers ++ * ++ */ ++ /*correct PHY setting L3.0 BGA*/ ++ mii_mgr_write(1, 31, 0x4000); //global, page 4 ++ ++ mii_mgr_write(1, 17, 0x7444); ++ if(is_BGA){ ++ mii_mgr_write(1, 19, 0x0114); ++ }else{ ++ mii_mgr_write(1, 19, 0x0117); ++ } ++ ++ mii_mgr_write(1, 22, 0x10cf); ++ mii_mgr_write(1, 25, 0x6212); ++ mii_mgr_write(1, 26, 0x0777); ++ mii_mgr_write(1, 29, 0x4000); ++ mii_mgr_write(1, 28, 0xc077); ++ mii_mgr_write(1, 24, 0x0000); ++ ++ mii_mgr_write(1, 31, 0x3000); //global, page 3 ++ mii_mgr_write(1, 17, 0x4838); ++ ++ mii_mgr_write(1, 31, 0x2000); //global, page 2 ++ if(is_BGA){ ++ mii_mgr_write(1, 21, 0x0515); ++ mii_mgr_write(1, 22, 0x0053); ++ mii_mgr_write(1, 23, 0x00bf); ++ mii_mgr_write(1, 24, 0x0aaf); ++ mii_mgr_write(1, 25, 0x0fad); ++ mii_mgr_write(1, 26, 0x0fc1); ++ }else{ ++ mii_mgr_write(1, 21, 0x0517); ++ mii_mgr_write(1, 22, 0x0fd2); ++ mii_mgr_write(1, 23, 0x00bf); ++ mii_mgr_write(1, 24, 0x0aab); ++ mii_mgr_write(1, 25, 0x00ae); ++ mii_mgr_write(1, 26, 0x0fff); ++ } ++ mii_mgr_write(1, 31, 0x1000); //global, page 1 ++ mii_mgr_write(1, 17, 0xe7f8); ++ ++ mii_mgr_write(1, 31, 0x8000); //local, page 0 ++ mii_mgr_write(0, 30, 0xa000); ++ mii_mgr_write(1, 30, 0xa000); ++ mii_mgr_write(2, 30, 0xa000); ++ mii_mgr_write(3, 30, 0xa000); ++#if !defined (CONFIG_RAETH_HAS_PORT4) ++ mii_mgr_write(4, 30, 0xa000); ++#endif ++ ++ mii_mgr_write(0, 4, 0x05e1); ++ mii_mgr_write(1, 4, 0x05e1); ++ mii_mgr_write(2, 4, 0x05e1); ++ mii_mgr_write(3, 4, 0x05e1); ++#if !defined (CONFIG_RAETH_HAS_PORT4) ++ mii_mgr_write(4, 4, 0x05e1); ++#endif ++ ++ mii_mgr_write(1, 31, 0xa000); //local, page 2 ++ mii_mgr_write(0, 16, 0x1111); ++ mii_mgr_write(1, 16, 0x1010); ++ mii_mgr_write(2, 16, 0x1515); ++ mii_mgr_write(3, 16, 0x0f0f); ++#if !defined (CONFIG_RAETH_HAS_PORT4) ++ mii_mgr_write(4, 16, 0x1313); ++#endif ++ ++#if !defined (CONFIG_RAETH_8023AZ_EEE) ++ mii_mgr_write(1, 31, 0xb000); //local, page 3 ++ mii_mgr_write(0, 17, 0x0); ++ mii_mgr_write(1, 17, 0x0); ++ mii_mgr_write(2, 17, 0x0); ++ mii_mgr_write(3, 17, 0x0); ++#if !defined (CONFIG_RAETH_HAS_PORT4) ++ mii_mgr_write(4, 17, 0x0); ++#endif ++#endif ++ ++ ++ ++#if 0 ++ // for ethernet extended mode ++ mii_mgr_write(1, 31, 0x3000); ++ mii_mgr_write(1, 19, 0x122); ++ mii_mgr_write(1, 20, 0x0044); ++ mii_mgr_write(1, 23, 0xa80c); ++ mii_mgr_write(1, 24, 0x129d); ++ mii_mgr_write(1, 31, 9000); ++ mii_mgr_write(0, 18, 0x140c); ++ mii_mgr_write(1, 18, 0x140c); ++ mii_mgr_write(2, 18, 0x140c); ++ mii_mgr_write(3, 18, 0x140c); ++ mii_mgr_write(0, 0, 0x3300); ++ mii_mgr_write(1, 0, 0x3300); ++ mii_mgr_write(2, 0, 0x3300); ++ mii_mgr_write(3, 0, 0x3300); ++#if !defined (CONFIG_RAETH_HAS_PORT4) ++ mii_mgr_write(4, 18, 0x140c); ++ mii_mgr_write(4, 0, 0x3300); ++#endif ++#endif ++ ++#endif ++ ++#if defined(CONFIG_RALINK_MT7620) ++ if ((sysRegRead(0xB000000C) & 0xf) >= 0x5) { ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x701c) = 0x800000c; //enlarge FE2SW_IPG ++ } ++#endif // CONFIG_RAETH_7620 // ++ ++ ++ ++#if defined (CONFIG_MT7620_FPGA)|| defined (CONFIG_MT7620_ASIC) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3600) = 0x5e33b;//CPU Port6 Force Link 1G, FC ON ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0010) = 0x7f7f7fe0;//Set Port6 CPU Port ++ ++#if defined (CONFIG_P5_RGMII_TO_MAC_MODE) || defined (CONFIG_P5_RGMII_TO_MT7530_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e33b;//(P5, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x7014) = 0x1f0c000c; //disable port 0 ~ 4 internal phy, set phy base address to 12 ++ /*MT7620 need mac learning for PPE*/ ++ //*(unsigned long *)(RALINK_ETH_SW_BASE+0x250c) = 0x000fff10;//disable port5 mac learning ++ //*(unsigned long *)(RALINK_ETH_SW_BASE+0x260c) = 0x000fff10;//disable port6 mac learning ++ *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode ++ //rxclk_skew, txclk_skew = 0 ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=RGMii Mode ++#if defined (CONFIG_P5_RGMII_TO_MT7530_MODE) ++ ++ *(unsigned long *)(0xb0000060) &= ~(3 << 7); //set MDIO to Normal mode ++ ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x56330;//(P4, AN) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode ++ //rxclk_skew, txclk_skew = 0 ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE2_MODE=RGMii Mode ++ ++ ++ /* set MT7530 Port 0 to PHY mode */ ++ mii_mgr_read(31, 0x7804 ,®Value); ++#if defined (CONFIG_GE_RGMII_MT7530_P0_AN) ++ regValue &= ~((1<<13)|(1<<6)|(1<<5)|(1<<15)); ++ regValue |= ((1<<7)|(1<<16)|(1<<20)|(1<<24)); ++ //mii_mgr_write(31, 0x7804 ,0x115c8f); ++#elif defined (CONFIG_GE_RGMII_MT7530_P4_AN) ++ regValue &= ~((1<<13)|(1<<6)|(1<<20)|(1<<5)|(1<<15)); ++ regValue |= ((1<<7)|(1<<16)|(1<<24)); ++#endif ++ regValue &= ~(1<<8); //Enable Port 6 ++ mii_mgr_write(31, 0x7804 ,regValue); //bit 24 standalone switch ++ ++/* set MT7530 central align */ ++ mii_mgr_read(31, 0x7830, ®Value); ++ regValue &= ~1; ++ regValue |= 1<<1; ++ mii_mgr_write(31, 0x7830, regValue); ++ ++ mii_mgr_read(31, 0x7a40, ®Value); ++ regValue &= ~(1<<30); ++ mii_mgr_write(31, 0x7a40, regValue); ++ ++ regValue = 0x855; ++ mii_mgr_write(31, 0x7a78, regValue); ++ ++ /*AN should be set after MT7530 HWSTRAP*/ ++#if defined (CONFIG_GE_RGMII_MT7530_P0_AN) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x7000) = 0xc5000100;//(P0, AN polling) ++#elif defined (CONFIG_GE_RGMII_MT7530_P4_AN) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x7000) = 0xc5000504;//(P4, AN polling) ++#endif ++#endif ++ ++#elif defined (CONFIG_P5_MII_TO_MAC_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=Mii Mode ++ *(unsigned long *)(SYSCFG1) |= (0x1 << 12); ++ ++#elif defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode ++ *(unsigned long *)(0xb0000060) &= ~(3 << 7); //set MDIO to Normal mode ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=RGMii Mode ++ ++ enable_auto_negotiate(1); ++ ++ if (isICPlusGigaPHY(1)) { ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, &phy_val); ++ phy_val |= 1<<10; //enable pause ability ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, phy_val); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val); ++ phy_val |= 1<<9; //restart AN ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val); ++ }else if (isMarvellGigaPHY(1)) { ++#if defined (CONFIG_MT7620_FPGA) ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, &phy_val); ++ phy_val &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half) ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, phy_val); ++#endif ++ printk("Reset MARVELL phy1\n"); ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &phy_val); ++ phy_val |= 1<<7; //Add delay to RX_CLK for RXD Outputs ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, phy_val); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val); ++ phy_val |= 1<<15; //PHY Software Reset ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val); ++ }else if (isVtssGigaPHY(1)) { ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0001); //extended page ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &phy_val); ++ printk("Vitesse phy skew: %x --> ", phy_val); ++ phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns ++ phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns ++ printk("%x\n", phy_val); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, phy_val); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0000); //main registers ++ } ++ ++ ++#elif defined (CONFIG_P5_RMII_TO_MAC_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=RvMii Mode ++ *(unsigned long *)(SYSCFG1) |= (0x2 << 12); ++ ++#else // Port 5 Disabled // ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3500) = 0x8000;//link down ++ *(unsigned long *)(0xb0000060) |= (1 << 9); //set RGMII to GPIO mode ++#endif ++#endif ++ ++#if defined (CONFIG_P4_RGMII_TO_MAC_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x5e33b;//(P4, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode ++ //rxclk_skew, txclk_skew = 0 ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE2_MODE=RGMii Mode ++ ++#elif defined (CONFIG_P4_MII_TO_MAC_MODE) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE2_MODE=Mii Mode ++ *(unsigned long *)(SYSCFG1) |= (0x1 << 14); ++ ++#elif defined (CONFIG_P4_MAC_TO_PHY_MODE) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode ++ *(unsigned long *)(0xb0000060) &= ~(3 << 7); //set MDIO to Normal mode ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE2_MODE=RGMii Mode ++ ++ enable_auto_negotiate(1); ++ ++ if (isICPlusGigaPHY(2)) { ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 4, &phy_val); ++ phy_val |= 1<<10; //enable pause ability ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 4, phy_val); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, &phy_val); ++ phy_val |= 1<<9; //restart AN ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, phy_val); ++ }else if (isMarvellGigaPHY(2)) { ++#if defined (CONFIG_MT7620_FPGA) ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, &phy_val); ++ phy_val &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half) ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, phy_val); ++#endif ++ printk("Reset MARVELL phy2\n"); ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, &phy_val); ++ phy_val |= 1<<7; //Add delay to RX_CLK for RXD Outputs ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, phy_val); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, &phy_val); ++ phy_val |= 1<<15; //PHY Software Reset ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, phy_val); ++ }else if (isVtssGigaPHY(2)) { ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 0x0001); //extended page ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, &phy_val); ++ printk("Vitesse phy skew: %x --> ", phy_val); ++ phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns ++ phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns ++ printk("%x\n", phy_val); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, phy_val); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 0x0000); //main registers ++ } ++ ++#elif defined (CONFIG_P4_RMII_TO_MAC_MODE) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x3400) = 0x5e337;//(P5, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 10); //set GE2 to Normal mode ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 14); //GE1_MODE=RvMii Mode ++ *(unsigned long *)(SYSCFG1) |= (0x2 << 14); ++#elif defined (CONFIG_GE_RGMII_MT7530_P0_AN) || defined (CONFIG_GE_RGMII_MT7530_P4_AN) ++#else // Port 4 Disabled // ++ *(unsigned long *)(SYSCFG1) |= (0x3 << 14); //GE2_MODE=RJ45 Mode ++ *(unsigned long *)(0xb0000060) |= (1 << 10); //set RGMII2 to GPIO mode ++#endif ++ ++} ++#endif ++ ++#if defined (CONFIG_RALINK_MT7628) ++ ++void mt7628_ephy_init(void) ++{ ++ int i; ++ u32 phy_val; ++ mii_mgr_write(0, 31, 0x2000); //change G2 page ++ mii_mgr_write(0, 26, 0x0000); ++ ++ for(i=0; i<5; i++){ ++ mii_mgr_write(i, 31, 0x8000); //change L0 page ++ mii_mgr_write(i, 0, 0x3100); ++ ++#if defined (CONFIG_RAETH_8023AZ_EEE) ++ mii_mgr_read(i, 26, &phy_val);// EEE setting ++ phy_val |= (1 << 5); ++ mii_mgr_write(i, 26, phy_val); ++#else ++ //disable EEE ++ mii_mgr_write(i, 13, 0x7); ++ mii_mgr_write(i, 14, 0x3C); ++ mii_mgr_write(i, 13, 0x4007); ++ mii_mgr_write(i, 14, 0x0); ++#endif ++ mii_mgr_write(i, 30, 0xa000); ++ mii_mgr_write(i, 31, 0xa000); // change L2 page ++ mii_mgr_write(i, 16, 0x0606); ++ mii_mgr_write(i, 23, 0x0f0e); ++ mii_mgr_write(i, 24, 0x1610); ++ mii_mgr_write(i, 30, 0x1f15); ++ mii_mgr_write(i, 28, 0x6111); ++ ++ mii_mgr_read(i, 4, &phy_val); ++ phy_val |= (1 << 10); ++ mii_mgr_write(i, 4, phy_val); ++ } ++ ++ //100Base AOI setting ++ mii_mgr_write(0, 31, 0x5000); //change G5 page ++ mii_mgr_write(0, 19, 0x004a); ++ mii_mgr_write(0, 20, 0x015a); ++ mii_mgr_write(0, 21, 0x00ee); ++ mii_mgr_write(0, 22, 0x0033); ++ mii_mgr_write(0, 23, 0x020a); ++ mii_mgr_write(0, 24, 0x0000); ++ mii_mgr_write(0, 25, 0x024a); ++ mii_mgr_write(0, 26, 0x035a); ++ mii_mgr_write(0, 27, 0x02ee); ++ mii_mgr_write(0, 28, 0x0233); ++ mii_mgr_write(0, 29, 0x000a); ++ mii_mgr_write(0, 30, 0x0000); ++ /* Fix EPHY idle state abnormal behavior */ ++ mii_mgr_write(0, 31, 0x4000); //change G4 page ++ mii_mgr_write(0, 29, 0x000d); ++ mii_mgr_write(0, 30, 0x0500); ++ ++} ++ ++#endif ++ ++ ++#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++void rt305x_esw_init(void) ++{ ++ int i=0; ++ u32 phy_val=0, val=0; ++#if defined (CONFIG_RT3052_ASIC) ++ u32 phy_val2; ++#endif ++ ++#if defined (CONFIG_RT5350_ASIC) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0168) = 0x17; ++#endif ++ ++ /* ++ * FC_RLS_TH=200, FC_SET_TH=160 ++ * DROP_RLS=120, DROP_SET_TH=80 ++ */ ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0008) = 0xC8A07850; ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00E4) = 0x00000000; ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0014) = 0x00405555; ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0050) = 0x00002001; ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0090) = 0x00007f7f; ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0098) = 0x00007f3f; //disable VLAN ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00CC) = 0x0002500c; ++#ifndef CONFIG_UNH_TEST ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x009C) = 0x0008a301; //hashing algorithm=XOR48, aging interval=300sec ++#else ++ /* ++ * bit[30]:1 Backoff Algorithm Option: The latest one to pass UNH test ++ * bit[29]:1 Length of Received Frame Check Enable ++ * bit[8]:0 Enable collision 16 packet abort and late collision abort ++ * bit[7:6]:01 Maximum Packet Length: 1518 ++ */ ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x009C) = 0x6008a241; ++#endif ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x008C) = 0x02404040; ++#if defined (CONFIG_RT3052_ASIC) || defined (CONFIG_RT3352_ASIC) || defined (CONFIG_RT5350_ASIC) || defined (CONFIG_MT7628_ASIC) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) = 0x3f502b28; //Change polling Ext PHY Addr=0x1F ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0084) = 0x00000000; ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0110) = 0x7d000000; //1us cycle number=125 (FE's clock=125Mhz) ++#elif defined (CONFIG_RT3052_FPGA) || defined (CONFIG_RT3352_FPGA) || defined (CONFIG_RT5350_FPGA) || defined (CONFIG_MT7628_FPGA) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) = 0x00f03ff9; //polling Ext PHY Addr=0x0, force port5 as 100F/D (disable auto-polling) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0084) = 0xffdf1f00; ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x0110) = 0x0d000000; //1us cycle number=13 (FE's clock=12.5Mhz) ++ ++ /* In order to use 10M/Full on FPGA board. We configure phy capable to ++ * 10M Full/Half duplex, so we can use auto-negotiation on PC side */ ++ for(i=0;i<5;i++){ ++ mii_mgr_write(i, 4, 0x0461); //Capable of 10M Full/Half Duplex, flow control on/off ++ mii_mgr_write(i, 0, 0xB100); //reset all digital logic, except phy_reg ++ } ++#endif ++ ++ /* ++ * set port 5 force to 1000M/Full when connecting to switch or iNIC ++ */ ++#if defined (CONFIG_P5_RGMII_TO_MAC_MODE) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1<<29); //disable port 5 auto-polling ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) |= 0x3fff; //force 1000M full duplex ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(0xf<<20); //rxclk_skew, txclk_skew = 0 ++#elif defined (CONFIG_P5_MII_TO_MAC_MODE) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1<<29); //disable port 5 auto-polling ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(0x3fff); ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) |= 0x3ffd; //force 100M full duplex ++ ++#if defined (CONFIG_RALINK_RT3352) ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=Mii Mode ++ *(unsigned long *)(SYSCFG1) |= (0x1 << 12); ++#endif ++ ++#elif defined (CONFIG_P5_MAC_TO_PHY_MODE) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode ++ *(unsigned long *)(0xb0000060) &= ~(1 << 7); //set MDIO to Normal mode ++#if defined (CONFIG_RT3052_ASIC) || defined (CONFIG_RT3352_ASIC) ++ enable_auto_negotiate(1); ++#endif ++ if (isMarvellGigaPHY(1)) { ++#if defined (CONFIG_RT3052_FPGA) || defined (CONFIG_RT3352_FPGA) ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, &phy_val); ++ phy_val &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half) ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, phy_val); ++#endif ++ printk("\n Reset MARVELL phy\n"); ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, &phy_val); ++ phy_val |= 1<<7; //Add delay to RX_CLK for RXD Outputs ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, phy_val); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, &phy_val); ++ phy_val |= 1<<15; //PHY Software Reset ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, phy_val); ++ } ++ if (isVtssGigaPHY(1)) { ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0001); //extended page ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, &phy_val); ++ printk("Vitesse phy skew: %x --> ", phy_val); ++ phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns ++ phy_val &= ~(0x3<<14);// RGMII TX skew compensation= 0 ns ++ printk("%x\n", phy_val); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, phy_val); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0x0000); //main registers ++ } ++ ++#elif defined (CONFIG_P5_RMII_TO_MAC_MODE) ++ *(unsigned long *)(0xb0000060) &= ~(1 << 9); //set RGMII to Normal mode ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1<<29); //disable port 5 auto-polling ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(0x3fff); ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) |= 0x3ffd; //force 100M full duplex ++ ++#if defined (CONFIG_RALINK_RT3352) ++ *(unsigned long *)(SYSCFG1) &= ~(0x3 << 12); //GE1_MODE=RvMii Mode ++ *(unsigned long *)(SYSCFG1) |= (0x2 << 12); ++#endif ++#else // Port 5 Disabled // ++ ++#if defined (CONFIG_RALINK_RT3052) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1 << 29); //port5 auto polling disable ++ *(unsigned long *)(0xb0000060) |= (1 << 7); //set MDIO to GPIO mode (GPIO22-GPIO23) ++ *(unsigned long *)(0xb0000060) |= (1 << 9); //set RGMII to GPIO mode (GPIO41-GPIO50) ++ *(unsigned long *)(0xb0000674) = 0xFFF; //GPIO41-GPIO50 output mode ++ *(unsigned long *)(0xb000067C) = 0x0; //GPIO41-GPIO50 output low ++#elif defined (CONFIG_RALINK_RT3352) ++ *(unsigned long *)(RALINK_ETH_SW_BASE+0x00C8) &= ~(1 << 29); //port5 auto polling disable ++ *(unsigned long *)(0xb0000060) |= (1 << 7); //set MDIO to GPIO mode (GPIO22-GPIO23) ++ *(unsigned long *)(0xb0000624) = 0xC0000000; //GPIO22-GPIO23 output mode ++ *(unsigned long *)(0xb000062C) = 0xC0000000; //GPIO22-GPIO23 output high ++ ++ *(unsigned long *)(0xb0000060) |= (1 << 9); //set RGMII to GPIO mode (GPIO24-GPIO35) ++ *(unsigned long *)(0xb000064C) = 0xFFF; //GPIO24-GPIO35 output mode ++ *(unsigned long *)(0xb0000654) = 0xFFF; //GPIO24-GPIO35 output high ++#elif defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) ++ /* do nothing */ ++#endif ++#endif // CONFIG_P5_RGMII_TO_MAC_MODE // ++ ++ ++#if defined (CONFIG_RT3052_ASIC) ++ rw_rf_reg(0, 0, &phy_val); ++ phy_val = phy_val >> 4; ++ ++ if(phy_val > 0x5) { ++ ++ rw_rf_reg(0, 26, &phy_val); ++ phy_val2 = (phy_val | (0x3 << 5)); ++ rw_rf_reg(1, 26, &phy_val2); ++ ++ // reset EPHY ++ val = sysRegRead(RSTCTRL); ++ val = val | RALINK_EPHY_RST; ++ sysRegWrite(RSTCTRL, val); ++ val = val & ~(RALINK_EPHY_RST); ++ sysRegWrite(RSTCTRL, val); ++ ++ rw_rf_reg(1, 26, &phy_val); ++ ++ //select local register ++ mii_mgr_write(0, 31, 0x8000); ++ for(i=0;i<5;i++){ ++ mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY ++ mii_mgr_write(i, 29, 0x7058); //TX100/TX10 AD/DA current bias ++ mii_mgr_write(i, 30, 0x0018); //TX100 slew rate control ++ } ++ ++ //select global register ++ mii_mgr_write(0, 31, 0x0); ++ mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2 ++ mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4 ++ mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6 ++//#define ENABLE_LDPS ++#if defined (ENABLE_LDPS) ++ mii_mgr_write(0, 12, 0x7eaa); ++ mii_mgr_write(0, 22, 0x252f); //tune TP_IDL tail and head waveform, enable power down slew rate control ++#else ++ mii_mgr_write(0, 12, 0x0); ++ mii_mgr_write(0, 22, 0x052f); ++#endif ++ mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length ++ mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold. ++ mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum ++ mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold ++ mii_mgr_write(0, 27, 0x2fce); //set PLL/Receive bias current are calibrated ++ mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350) ++ mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3) ++ mii_mgr_write(0, 31, 0x8000); //select local register ++ ++ for(i=0;i<5;i++){ ++ //LSB=1 enable PHY ++ mii_mgr_read(i, 26, &phy_val); ++ phy_val |= 0x0001; ++ mii_mgr_write(i, 26, phy_val); ++ } ++ } else { ++ //select local register ++ mii_mgr_write(0, 31, 0x8000); ++ for(i=0;i<5;i++){ ++ mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY ++ mii_mgr_write(i, 29, 0x7058); //TX100/TX10 AD/DA current bias ++ mii_mgr_write(i, 30, 0x0018); //TX100 slew rate control ++ } ++ ++ //select global register ++ mii_mgr_write(0, 31, 0x0); ++ mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2 ++ mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4 ++ mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6 ++ mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length ++ mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold. ++ mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum ++ mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold ++ mii_mgr_write(0, 22, 0x052f); //tune TP_IDL tail and head waveform ++ mii_mgr_write(0, 27, 0x2fce); //set PLL/Receive bias current are calibrated ++ mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350) ++ mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3) ++ mii_mgr_write(0, 31, 0x8000); //select local register ++ ++ for(i=0;i<5;i++){ ++ //LSB=1 enable PHY ++ mii_mgr_read(i, 26, &phy_val); ++ phy_val |= 0x0001; ++ mii_mgr_write(i, 26, phy_val); ++ } ++ } ++#elif defined (CONFIG_RT3352_ASIC) ++ //PHY IOT ++ // reset EPHY ++ val = sysRegRead(RSTCTRL); ++ val = val | RALINK_EPHY_RST; ++ sysRegWrite(RSTCTRL, val); ++ val = val & ~(RALINK_EPHY_RST); ++ sysRegWrite(RSTCTRL, val); ++ ++ //select local register ++ mii_mgr_write(0, 31, 0x8000); ++ for(i=0;i<5;i++){ ++ mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY ++ mii_mgr_write(i, 29, 0x7016); //TX100/TX10 AD/DA current bias ++ mii_mgr_write(i, 30, 0x0038); //TX100 slew rate control ++ } ++ ++ //select global register ++ mii_mgr_write(0, 31, 0x0); ++ mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2 ++ mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4 ++ mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6 ++ mii_mgr_write(0, 12, 0x7eaa); ++ mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length ++ mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold. ++ mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum ++ mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold ++ mii_mgr_write(0, 22, 0x253f); //tune TP_IDL tail and head waveform, enable power down slew rate control ++ mii_mgr_write(0, 27, 0x2fda); //set PLL/Receive bias current are calibrated ++ mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350) ++ mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3) ++ mii_mgr_write(0, 31, 0x8000); //select local register ++ ++ for(i=0;i<5;i++){ ++ //LSB=1 enable PHY ++ mii_mgr_read(i, 26, &phy_val); ++ phy_val |= 0x0001; ++ mii_mgr_write(i, 26, phy_val); ++ } ++ ++#elif defined (CONFIG_RT5350_ASIC) ++ //PHY IOT ++ // reset EPHY ++ val = sysRegRead(RSTCTRL); ++ val = val | RALINK_EPHY_RST; ++ sysRegWrite(RSTCTRL, val); ++ val = val & ~(RALINK_EPHY_RST); ++ sysRegWrite(RSTCTRL, val); ++ ++ //select local register ++ mii_mgr_write(0, 31, 0x8000); ++ for(i=0;i<5;i++){ ++ mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY ++ mii_mgr_write(i, 29, 0x7015); //TX100/TX10 AD/DA current bias ++ mii_mgr_write(i, 30, 0x0038); //TX100 slew rate control ++ } ++ ++ //select global register ++ mii_mgr_write(0, 31, 0x0); ++ mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2 ++ mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4 ++ mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6 ++ mii_mgr_write(0, 12, 0x7eaa); ++ mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length ++ mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold. ++ mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum ++ mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold ++ mii_mgr_write(0, 22, 0x253f); //tune TP_IDL tail and head waveform, enable power down slew rate control ++ mii_mgr_write(0, 27, 0x2fda); //set PLL/Receive bias current are calibrated ++ mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350) ++ mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3) ++ mii_mgr_write(0, 31, 0x8000); //select local register ++ ++ for(i=0;i<5;i++){ ++ //LSB=1 enable PHY ++ mii_mgr_read(i, 26, &phy_val); ++ phy_val |= 0x0001; ++ mii_mgr_write(i, 26, phy_val); ++ } ++#elif defined (CONFIG_MT7628_ASIC) ++/*INIT MT7628 PHY HERE*/ ++ val = sysRegRead(RT2880_AGPIOCFG_REG); ++#if defined (CONFIG_ETH_ONE_PORT_ONLY) ++ val |= (MT7628_P0_EPHY_AIO_EN | MT7628_P1_EPHY_AIO_EN | MT7628_P2_EPHY_AIO_EN | MT7628_P3_EPHY_AIO_EN | MT7628_P4_EPHY_AIO_EN); ++ val = val & ~(MT7628_P0_EPHY_AIO_EN); ++#else ++ val = val & ~(MT7628_P0_EPHY_AIO_EN | MT7628_P1_EPHY_AIO_EN | MT7628_P2_EPHY_AIO_EN | MT7628_P3_EPHY_AIO_EN | MT7628_P4_EPHY_AIO_EN); ++#endif ++ if ((*((volatile u32 *)(RALINK_SYSCTL_BASE + 0x8))) & 0x10000) ++ val &= ~0x1f0000; ++ sysRegWrite(RT2880_AGPIOCFG_REG, val); ++ ++ val = sysRegRead(RSTCTRL); ++ val = val | RALINK_EPHY_RST; ++ sysRegWrite(RSTCTRL, val); ++ val = val & ~(RALINK_EPHY_RST); ++ sysRegWrite(RSTCTRL, val); ++ ++ ++ val = sysRegRead(RALINK_SYSCTL_BASE + 0x64); ++#if defined (CONFIG_ETH_ONE_PORT_ONLY) ++ val &= 0xf003f003; ++ val |= 0x05540554; ++ sysRegWrite(RALINK_SYSCTL_BASE + 0x64, val); // set P0 EPHY LED mode ++#else ++ val &= 0xf003f003; ++ sysRegWrite(RALINK_SYSCTL_BASE + 0x64, val); // set P0~P4 EPHY LED mode ++#endif ++ ++ udelay(5000); ++ mt7628_ephy_init(); ++ ++#endif ++} ++#endif ++ ++#if defined (CONFIG_ARCH_MT7623) /* TODO: just for bring up, should be removed!!! */ ++void mt7623_pinmux_set(void) ++{ ++ unsigned long regValue; ++ ++ //printk("[mt7623_pinmux_set]start\n"); ++ /* Pin277: ESW_RST (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ad0)); ++ regValue &= ~(BITS(6,8)); ++ regValue |= BIT(6); ++ *(volatile u_long *)(0xf0005ad0) = regValue; ++ ++ /* Pin262: G2_TXEN (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005aa0)); ++ regValue &= ~(BITS(6,8)); ++ regValue |= BIT(6); ++ *(volatile u_long *)(0xf0005aa0) = regValue; ++ /* Pin263: G2_TXD3 (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005aa0)); ++ regValue &= ~(BITS(9,11)); ++ regValue |= BIT(9); ++ *(volatile u_long *)(0xf0005aa0) = regValue; ++ /* Pin264: G2_TXD2 (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005aa0)); ++ regValue &= ~(BITS(12,14)); ++ regValue |= BIT(12); ++ *(volatile u_long *)(0xf0005aa0) = regValue; ++ /* Pin265: G2_TXD1 (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0)); ++ regValue &= ~(BITS(0,2)); ++ regValue |= BIT(0); ++ *(volatile u_long *)(0xf0005ab0) = regValue; ++ /* Pin266: G2_TXD0 (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0)); ++ regValue &= ~(BITS(3,5)); ++ regValue |= BIT(3); ++ *(volatile u_long *)(0xf0005ab0) = regValue; ++ /* Pin267: G2_TXC (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0)); ++ regValue &= ~(BITS(6,8)); ++ regValue |= BIT(6); ++ *(volatile u_long *)(0xf0005ab0) = regValue; ++ /* Pin268: G2_RXC (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0)); ++ regValue &= ~(BITS(9,11)); ++ regValue |= BIT(9); ++ *(volatile u_long *)(0xf0005ab0) = regValue; ++ /* Pin269: G2_RXD0 (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ab0)); ++ regValue &= ~(BITS(12,14)); ++ regValue |= BIT(12); ++ *(volatile u_long *)(0xf0005ab0) = regValue; ++ /* Pin270: G2_RXD1 (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ac0)); ++ regValue &= ~(BITS(0,2)); ++ regValue |= BIT(0); ++ *(volatile u_long *)(0xf0005ac0) = regValue; ++ /* Pin271: G2_RXD2 (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ac0)); ++ regValue &= ~(BITS(3,5)); ++ regValue |= BIT(3); ++ *(volatile u_long *)(0xf0005ac0) = regValue; ++ /* Pin272: G2_RXD3 (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ac0)); ++ regValue &= ~(BITS(6,8)); ++ regValue |= BIT(6); ++ *(volatile u_long *)(0xf0005ac0) = regValue; ++ /* Pin274: G2_RXDV (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ac0)); ++ regValue &= ~(BITS(12,14)); ++ regValue |= BIT(12); ++ *(volatile u_long *)(0xf0005ac0) = regValue; ++ ++ /* Pin275: MDC (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ad0)); ++ regValue &= ~(BITS(0,2)); ++ regValue |= BIT(0); ++ *(volatile u_long *)(0xf0005ad0) = regValue; ++ /* Pin276: MDIO (1) */ ++ regValue = le32_to_cpu(*(volatile u_long *)(0xf0005ad0)); ++ regValue &= ~(BITS(3,5)); ++ regValue |= BIT(3); ++ *(volatile u_long *)(0xf0005ad0) = regValue; ++ //printk("[mt7623_pinmux_set]end\n"); ++} ++ ++void wait_loop(void) { ++ int i,j; ++ int read_data; ++ j =0; ++ while (j< 10) { ++ for(i = 0; i<32; i = i+1){ ++ read_data = *(volatile u_long *)(0xFB110610); ++ } ++ j++; ++ } ++} ++ ++void trgmii_calibration_7623(void) { ++ ++ unsigned int tap_a[5]; // minumum delay for all correct ++ unsigned int tap_b[5]; // maximum delay for all correct ++ unsigned int final_tap[5]; ++ unsigned int bslip_en; ++ unsigned int rxc_step_size; ++ unsigned int rxd_step_size; ++ unsigned int read_data; ++ unsigned int tmp; ++ unsigned int rd_wd; ++ int i; ++ unsigned int err_cnt[5]; ++ unsigned int init_toggle_data; ++ unsigned int err_flag[5]; ++ unsigned int err_total_flag; ++ unsigned int training_word; ++ unsigned int rd_tap; ++ ++ u32 TRGMII_7623_base; ++ u32 TRGMII_7623_RD_0; ++ u32 TRGMII_RD_1; ++ u32 TRGMII_RD_2; ++ u32 TRGMII_RD_3; ++ u32 TRGMII_RXCTL; ++ u32 TRGMII_RCK_CTRL; ++ u32 TRGMII_7530_base; ++ TRGMII_7623_base = 0xFB110300; ++ TRGMII_7623_RD_0 = TRGMII_7623_base + 0x10; ++ TRGMII_RCK_CTRL = TRGMII_7623_base; ++ rxd_step_size =0x1; ++ rxc_step_size =0x4; ++ init_toggle_data = 0x00000055; ++ training_word = 0x000000AC; ++ ++ //printk("Calibration begin ........"); ++ *(volatile u_long *)(TRGMII_7623_base +0x04) &= 0x3fffffff; // RX clock gating in MT7623 ++ *(volatile u_long *)(TRGMII_7623_base +0x00) |= 0x80000000; // Assert RX reset in MT7623 ++ *(volatile u_long *)(TRGMII_7623_base +0x78) |= 0x00002000; // Set TX OE edge in MT7623 ++ *(volatile u_long *)(TRGMII_7623_base +0x04) |= 0xC0000000; // Disable RX clock gating in MT7623 ++ *(volatile u_long *)(TRGMII_7623_base ) &= 0x7fffffff; // Release RX reset in MT7623 ++ //printk("Check Point 1 .....\n"); ++ for (i = 0 ; i<5 ; i++) { ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) |= 0x80000000; // Set bslip_en = 1 ++ } ++ ++ //printk("Enable Training Mode in MT7530\n"); ++ mii_mgr_read(0x1F,0x7A40,&read_data); ++ read_data |= 0xc0000000; ++ mii_mgr_write(0x1F,0x7A40,read_data); //Enable Training Mode in MT7530 ++ err_total_flag = 0; ++ //printk("Adjust RXC delay in MT7623\n"); ++ read_data =0x0; ++ while (err_total_flag == 0 && read_data != 0x68) { ++ //printk("2nd Enable EDGE CHK in MT7623\n"); ++ /* Enable EDGE CHK in MT7623*/ ++ for (i = 0 ; i<5 ; i++) { ++ tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++ tmp |= 0x40000000; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff; ++ } ++ wait_loop(); ++ err_total_flag = 1; ++ for (i = 0 ; i<5 ; i++) { ++ err_cnt[i] = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 8) & 0x0000000f; ++ rd_wd = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 16) & 0x000000ff; ++ //printk("ERR_CNT = %d, RD_WD =%x\n",err_cnt[i],rd_wd); ++ if ( err_cnt[i] !=0 ) { ++ err_flag[i] = 1; ++ } ++ else if (rd_wd != 0x55) { ++ err_flag[i] = 1; ++ } ++ else { ++ err_flag[i] = 0; ++ } ++ err_total_flag = err_flag[i] & err_total_flag; ++ } ++ ++ //printk("2nd Disable EDGE CHK in MT7623\n"); ++ /* Disable EDGE CHK in MT7623*/ ++ for (i = 0 ; i<5 ; i++) { ++ tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++ tmp |= 0x40000000; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff; ++ } ++ wait_loop(); ++ //printk("2nd Disable EDGE CHK in MT7623\n"); ++ /* Adjust RXC delay */ ++ *(volatile u_long *)(TRGMII_7623_base +0x00) |= 0x80000000; // Assert RX reset in MT7623 ++ *(volatile u_long *)(TRGMII_7623_base +0x04) &= 0x3fffffff; // RX clock gating in MT7623 ++ read_data = *(volatile u_long *)(TRGMII_7623_base); ++ if (err_total_flag == 0) { ++ tmp = (read_data & 0x0000007f) + rxc_step_size; ++ //printk(" RXC delay = %d\n", tmp); ++ read_data >>= 8; ++ read_data &= 0xffffff80; ++ read_data |= tmp; ++ read_data <<=8; ++ read_data &= 0xffffff80; ++ read_data |=tmp; ++ *(volatile u_long *)(TRGMII_7623_base) = read_data; ++ } ++ read_data &=0x000000ff; ++ *(volatile u_long *)(TRGMII_7623_base ) &= 0x7fffffff; // Release RX reset in MT7623 ++ *(volatile u_long *)(TRGMII_7623_base +0x04) |= 0xC0000000; // Disable RX clock gating in MT7623 ++ for (i = 0 ; i<5 ; i++) { ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = (*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) | 0x80000000; // Set bslip_en = ~bit_slip_en ++ } ++ } ++ //printk("Finish RXC Adjustment while loop\n"); ++ //printk("Read RD_WD MT7623\n"); ++ /* Read RD_WD MT7623*/ ++ for (i = 0 ; i<5 ; i++) { ++ rd_tap=0; ++ while (err_flag[i] != 0) { ++ /* Enable EDGE CHK in MT7623*/ ++ tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++ tmp |= 0x40000000; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff; ++ wait_loop(); ++ read_data = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++ err_cnt[i] = (read_data >> 8) & 0x0000000f; // Read MT7623 Errcnt ++ rd_wd = (read_data >> 16) & 0x000000ff; ++ if (err_cnt[i] != 0 || rd_wd !=0x55){ ++ err_flag [i] = 1; ++ } ++ else { ++ err_flag[i] =0; ++ } ++ /* Disable EDGE CHK in MT7623*/ ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) &= 0x4fffffff; ++ tmp |= 0x40000000; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff; ++ wait_loop(); ++ //err_cnt[i] = ((read_data) >> 8) & 0x0000000f; // Read MT7623 Errcnt ++ if (err_flag[i] !=0) { ++ rd_tap = (read_data & 0x0000007f) + rxd_step_size; // Add RXD delay in MT7623 ++ read_data = (read_data & 0xffffff80) | rd_tap; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data; ++ tap_a[i] = rd_tap; ++ } else { ++ rd_tap = (read_data & 0x0000007f) + 4; ++ read_data = (read_data & 0xffffff80) | rd_tap; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data; ++ } ++ //err_cnt[i] = (*(volatile u_long *)(TRGMII_7623_RD_0 + i*8) >> 8) & 0x0000000f; // Read MT7623 Errcnt ++ ++ } ++ //printk("%dth bit Tap_a = %d\n", i, tap_a[i]); ++ } ++ //printk("Last While Loop\n"); ++ for (i = 0 ; i<5 ; i++) { ++ //printk(" Bit%d\n", i); ++ rd_tap =0; ++ while ((err_cnt[i] == 0) && (rd_tap !=128)) { ++ read_data = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++ rd_tap = (read_data & 0x0000007f) + rxd_step_size; // Add RXD delay in MT7623 ++ read_data = (read_data & 0xffffff80) | rd_tap; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data; ++ /* Enable EDGE CHK in MT7623*/ ++ tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++ tmp |= 0x40000000; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff; ++ wait_loop(); ++ err_cnt[i] = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 8) & 0x0000000f; // Read MT7623 Errcnt ++ /* Disable EDGE CHK in MT7623*/ ++ tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++ tmp |= 0x40000000; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff; ++ wait_loop(); ++ //err_cnt[i] = ((*(volatile u_long *)(TRGMII_7623_RD_0 + i*8)) >> 8) & 0x0000000f; // Read MT7623 Errcnt ++ ++ } ++ tap_b[i] = rd_tap;// -rxd_step_size; // Record the max delay TAP_B ++ //printk("tap_b[%d] is %d \n", i,tap_b[i]); ++ final_tap[i] = (tap_a[i]+tap_b[i])/2; // Calculate RXD delay = (TAP_A + TAP_B)/2 ++ //printk("%dth bit Final Tap = %d\n", i, final_tap[i]); ++ read_data = (read_data & 0xffffff80) | final_tap[i]; ++ *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = read_data; ++ } ++// /*word alignment*/ ++// mii_mgr_read(0x1F,0x7A50,&read_data); ++// read_data &= ~(0xff); ++// read_data |= 0xac; ++// mii_mgr_write(0x1F,0x7A50,read_data); ++// while (i <10) { ++// i++; ++// wait_loop(); ++// } ++// /* Enable EDGE CHK in MT7623*/ ++// for (i=0; i<5; i++) { ++// tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++// tmp |= 0x40000000; ++// *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff; ++// wait_loop(); ++// /* Disable EDGE CHK in MT7623*/ ++// tmp = *(volatile u_long *)(TRGMII_7623_RD_0 + i*8); ++// tmp |= 0x40000000; ++// *(volatile u_long *)(TRGMII_7623_RD_0 + i*8) = tmp & 0x4fffffff; ++// wait_loop(); ++// read_data = *(volatile u_long *)(TRGMII_7623_RD_0+i*8); ++// printk(" MT7623 training word = %x\n", read_data); ++// } ++ ++ ++ mii_mgr_read(0x1F,0x7A40,&read_data); ++ //printk(" MT7530 0x7A40 = %x\n", read_data); ++ read_data &=0x3fffffff; ++ mii_mgr_write(0x1F,0x7A40,read_data); ++} ++ ++ ++void trgmii_calibration_7530(void){ ++ ++ unsigned int tap_a[5]; ++ unsigned int tap_b[5]; ++ unsigned int final_tap[5]; ++ unsigned int bslip_en; ++ unsigned int rxc_step_size; ++ unsigned int rxd_step_size; ++ unsigned int read_data; ++ unsigned int tmp; ++ int i,j; ++ unsigned int err_cnt[5]; ++ unsigned int rd_wd; ++ unsigned int init_toggle_data; ++ unsigned int err_flag[5]; ++ unsigned int err_total_flag; ++ unsigned int training_word; ++ unsigned int rd_tap; ++ ++ u32 TRGMII_7623_base; ++ u32 TRGMII_7530_RD_0; ++ u32 TRGMII_RD_1; ++ u32 TRGMII_RD_2; ++ u32 TRGMII_RD_3; ++ u32 TRGMII_RXCTL; ++ u32 TRGMII_RCK_CTRL; ++ u32 TRGMII_7530_base; ++ u32 TRGMII_7530_TX_base; ++ TRGMII_7623_base = 0xFB110300; ++ TRGMII_7530_base = 0x7A00; ++ TRGMII_7530_RD_0 = TRGMII_7530_base + 0x10; ++ TRGMII_RCK_CTRL = TRGMII_7623_base; ++ rxd_step_size = 0x1; ++ rxc_step_size = 0x8; ++ init_toggle_data = 0x00000055; ++ training_word = 0x000000AC; ++ ++ TRGMII_7530_TX_base = TRGMII_7530_base + 0x50; ++ ++ //printk("Calibration begin ........\n"); ++ *(volatile u_long *)(TRGMII_7623_base + 0x40) |= 0x80000000; ++ mii_mgr_read(0x1F, 0x7a10, &read_data); ++ //printk("TRGMII_7530_RD_0 is %x\n", read_data); ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base+0x04,&read_data); ++ read_data &= 0x3fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_base+0x04,read_data); // RX clock gating in MT7530 ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base+0x78,&read_data); ++ read_data |= 0x00002000; ++ mii_mgr_write(0x1F,TRGMII_7530_base+0x78,read_data); // Set TX OE edge in MT7530 ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base,&read_data); ++ read_data |= 0x80000000; ++ mii_mgr_write(0x1F,TRGMII_7530_base,read_data); // Assert RX reset in MT7530 ++ ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base,&read_data); ++ read_data &= 0x7fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_base,read_data); // Release RX reset in MT7530 ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base+0x04,&read_data); ++ read_data |= 0xC0000000; ++ mii_mgr_write(0x1F,TRGMII_7530_base+0x04,read_data); // Disable RX clock gating in MT7530 ++ ++ //printk("Enable Training Mode in MT7623\n"); ++ /*Enable Training Mode in MT7623*/ ++ *(volatile u_long *)(TRGMII_7623_base + 0x40) &= 0xbfffffff; ++ *(volatile u_long *)(TRGMII_7623_base + 0x40) |= 0x80000000; ++ *(volatile u_long *)(TRGMII_7623_base + 0x78) &= 0xfffff0ff; ++ *(volatile u_long *)(TRGMII_7623_base + 0x78) |= 0x00000400; ++ ++ err_total_flag =0; ++ //printk("Adjust RXC delay in MT7530\n"); ++ read_data =0x0; ++ while (err_total_flag == 0 && (read_data != 0x68)) { ++ //printk("2nd Enable EDGE CHK in MT7530\n"); ++ /* Enable EDGE CHK in MT7530*/ ++ for (i = 0 ; i<5 ; i++) { ++ mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data); ++ read_data |= 0x40000000; ++ read_data &= 0x4fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ wait_loop(); ++ //printk("2nd Disable EDGE CHK in MT7530\n"); ++ mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&err_cnt[i]); ++ //printk("***** MT7530 %dth bit ERR_CNT =%x\n",i, err_cnt[i]); ++ //printk("MT7530 %dth bit ERR_CNT =%x\n",i, err_cnt[i]); ++ err_cnt[i] >>= 8; ++ err_cnt[i] &= 0x0000ff0f; ++ rd_wd = err_cnt[i] >> 8; ++ rd_wd &= 0x000000ff; ++ err_cnt[i] &= 0x0000000f; ++ //mii_mgr_read(0x1F,0x7a10,&read_data); ++ if ( err_cnt[i] !=0 ) { ++ err_flag[i] = 1; ++ } ++ else if (rd_wd != 0x55) { ++ err_flag[i] = 1; ++ } else { ++ err_flag[i] = 0; ++ } ++ if (i==0) { ++ err_total_flag = err_flag[i]; ++ } else { ++ err_total_flag = err_flag[i] & err_total_flag; ++ } ++ /* Disable EDGE CHK in MT7530*/ ++ mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data); ++ read_data |= 0x40000000; ++ read_data &= 0x4fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ wait_loop(); ++ } ++ /*Adjust RXC delay*/ ++ if (err_total_flag ==0) { ++ mii_mgr_read(0x1F,TRGMII_7530_base,&read_data); ++ read_data |= 0x80000000; ++ mii_mgr_write(0x1F,TRGMII_7530_base,read_data); // Assert RX reset in MT7530 ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base+0x04,&read_data); ++ read_data &= 0x3fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_base+0x04,read_data); // RX clock gating in MT7530 ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base,&read_data); ++ tmp = read_data; ++ tmp &= 0x0000007f; ++ tmp += rxc_step_size; ++ //printk("Current rxc delay = %d\n", tmp); ++ read_data &= 0xffffff80; ++ read_data |= tmp; ++ mii_mgr_write (0x1F,TRGMII_7530_base,read_data); ++ mii_mgr_read(0x1F,TRGMII_7530_base,&read_data); ++ //printk("Current RXC delay = %x\n", read_data); ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base,&read_data); ++ read_data &= 0x7fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_base,read_data); // Release RX reset in MT7530 ++ ++ mii_mgr_read(0x1F,TRGMII_7530_base+0x04,&read_data); ++ read_data |= 0xc0000000; ++ mii_mgr_write(0x1F,TRGMII_7530_base+0x04,read_data); // Disable RX clock gating in MT7530 ++ } ++ read_data = tmp; ++ } ++ //printk("RXC delay is %d\n", tmp); ++ //printk("Finish RXC Adjustment while loop\n"); ++ ++ //printk("Read RD_WD MT7530\n"); ++ /* Read RD_WD MT7530*/ ++ for (i = 0 ; i<5 ; i++) { ++ rd_tap = 0; ++ while (err_flag[i] != 0) { ++ /* Enable EDGE CHK in MT7530*/ ++ mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data); ++ read_data |= 0x40000000; ++ read_data &= 0x4fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ wait_loop(); ++ err_cnt[i] = (read_data >> 8) & 0x0000000f; ++ rd_wd = (read_data >> 16) & 0x000000ff; ++ //printk("##### %dth bit ERR_CNT = %x RD_WD =%x ######\n", i, err_cnt[i],rd_wd); ++ if (err_cnt[i] != 0 || rd_wd !=0x55){ ++ err_flag [i] = 1; ++ } ++ else { ++ err_flag[i] =0; ++ } ++ if (err_flag[i] !=0 ) { ++ rd_tap = (read_data & 0x0000007f) + rxd_step_size; // Add RXD delay in MT7530 ++ read_data = (read_data & 0xffffff80) | rd_tap; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ tap_a[i] = rd_tap; ++ } else { ++ tap_a[i] = (read_data & 0x0000007f); // Record the min delay TAP_A ++ rd_tap = tap_a[i] + 0x4; ++ read_data = (read_data & 0xffffff80) | rd_tap ; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ } ++ ++ /* Disable EDGE CHK in MT7530*/ ++ mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data); ++ read_data |= 0x40000000; ++ read_data &= 0x4fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ wait_loop(); ++ ++ } ++ //printk("%dth bit Tap_a = %d\n", i, tap_a[i]); ++ } ++ //printk("Last While Loop\n"); ++ for (i = 0 ; i<5 ; i++) { ++ rd_tap =0; ++ while (err_cnt[i] == 0 && (rd_tap!=128)) { ++ /* Enable EDGE CHK in MT7530*/ ++ mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data); ++ read_data |= 0x40000000; ++ read_data &= 0x4fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ wait_loop(); ++ err_cnt[i] = (read_data >> 8) & 0x0000000f; ++ //rd_tap = (read_data & 0x0000007f) + 0x4; // Add RXD delay in MT7530 ++ if (err_cnt[i] == 0 && (rd_tap!=128)) { ++ rd_tap = (read_data & 0x0000007f) + rxd_step_size; // Add RXD delay in MT7530 ++ read_data = (read_data & 0xffffff80) | rd_tap; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ } ++ /* Disable EDGE CHK in MT7530*/ ++ mii_mgr_read(0x1F,TRGMII_7530_RD_0+i*8,&read_data); ++ read_data |= 0x40000000; ++ read_data &= 0x4fffffff; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ wait_loop(); ++ } ++ tap_b[i] = rd_tap;// - rxd_step_size; // Record the max delay TAP_B ++ //printk("%dth bit Tap_b = %d, ERR_CNT=%d\n", i, tap_b[i],err_cnt[i]); ++ final_tap[i] = (tap_a[i]+tap_b[i])/2; // Calculate RXD delay = (TAP_A + TAP_B)/2 ++ //printk("%dth bit Final Tap = %d\n", i, final_tap[i]); ++ ++ read_data = ( read_data & 0xffffff80) | final_tap[i]; ++ mii_mgr_write(0x1F,TRGMII_7530_RD_0+i*8,read_data); ++ } ++ *(volatile u_long *)(TRGMII_7623_base + 0x40) &=0x3fffffff; ++ ++} ++ ++void set_trgmii_325_delay_setting(void) ++{ ++ /*mt7530 side*/ ++ *(volatile u_long *)(0xfb110300) = 0x80020050; ++ *(volatile u_long *)(0xfb110304) = 0x00980000; ++ *(volatile u_long *)(0xfb110300) = 0x40020050; ++ *(volatile u_long *)(0xfb110304) = 0xc0980000; ++ *(volatile u_long *)(0xfb110310) = 0x00000028; ++ *(volatile u_long *)(0xfb110318) = 0x0000002e; ++ *(volatile u_long *)(0xfb110320) = 0x0000002d; ++ *(volatile u_long *)(0xfb110328) = 0x0000002b; ++ *(volatile u_long *)(0xfb110330) = 0x0000002a; ++ *(volatile u_long *)(0xfb110340) = 0x00020000; ++ /*mt7530 side*/ ++ mii_mgr_write(31, 0x7a00, 0x10); ++ mii_mgr_write(31, 0x7a10, 0x23); ++ mii_mgr_write(31, 0x7a18, 0x27); ++ mii_mgr_write(31, 0x7a20, 0x24); ++ mii_mgr_write(31, 0x7a28, 0x29); ++ mii_mgr_write(31, 0x7a30, 0x24); ++ ++} ++ ++ ++void setup_internal_gsw(void) ++{ ++ u32 i; ++ u32 regValue; ++ u32 xtal_mode; ++ ++ mt7623_pinmux_set(); /* TODO: just for bring up, should be removed!!! */ ++ ++#if 0 ++ /* GE1: RGMII mode setting */ ++ *(volatile u_long *)(0xfb110300) = 0x80020000; ++ *(volatile u_long *)(0xfb110304) = 0x00980000; ++ *(volatile u_long *)(0xfb110300) = 0x40020000; ++ *(volatile u_long *)(0xfb110304) = 0xc0980000; ++ *(volatile u_long *)(0xfb110310) = 0x00000041; ++ *(volatile u_long *)(0xfb110318) = 0x00000044; ++ *(volatile u_long *)(0xfb110320) = 0x00000043; ++ *(volatile u_long *)(0xfb110328) = 0x00000042; ++ *(volatile u_long *)(0xfb110330) = 0x00000042; ++ *(volatile u_long *)(0xfb110340) = 0x00020000; ++ *(volatile u_long *)(0xfb110390) &= 0xfffffff8; //RGMII mode ++#else ++ /* GE1: TRGMII mode setting */ ++ *(volatile u_long *)(0xfb110390) |= 0x00000002; //TRGMII mode ++#endif ++ ++ /*Todo: Hardware reset Switch*/ ++ /*Hardware reset Switch*/ ++#if defined(CONFIG_ARCH_MT7623) ++ regValue = *(volatile u_long *)(0xfb00000c); ++ /*MT7530 Reset. Flows for MT7623 and MT7683 are both excuted.*/ ++ /* Should Modify this section if EFUSE is ready*/ ++ /*For MT7683 reset MT7530*/ ++ if(!(regValue & (1<<16))) ++ { ++ *(volatile u_long *)(0xf0005520) &= ~(1<<1); ++ udelay(1000); ++ *(volatile u_long *)(0xf0005520) |= (1<<1); ++ mdelay(100); ++ } ++ //printk("Assert MT7623 RXC reset\n"); ++ *(volatile u_long *)(0xfb110300) |= 0x80000000; // Assert MT7623 RXC reset ++ /*For MT7623 reset MT7530*/ ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x34) |= (0x1 << 2); ++ udelay(1000); ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x34) &= ~(0x1 << 2); ++ mdelay(100); ++#endif ++ ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ for(i=0;i<=4;i++) ++ { ++ //turn off PHY ++ mii_mgr_read(i, 0x0 ,®Value); ++ regValue |= (0x1<<11); ++ mii_mgr_write(i, 0x0, regValue); ++ } ++ mii_mgr_write(31, 0x7000, 0x3); //reset switch ++ udelay(100); ++ ++#if defined (CONFIG_MT7621_ASIC) || defined (CONFIG_ARCH_MT7623) ++#if 0 ++ if((sysRegRead(0xbe00000c)&0xFFFF)==0x0101) { ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e30b);//(GE1, Force 1000M/FD, FC ON) ++ mii_mgr_write(31, 0x3600, 0x5e30b); ++ } else ++#endif ++ { ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2105e33b);//(GE1, Force 1000M/FD, FC ON) ++ mii_mgr_write(31, 0x3600, 0x5e33b); ++ mii_mgr_read(31, 0x3600 ,®Value); ++ } ++#endif ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down) ++#endif ++ ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/ ++ mii_mgr_read(31, 0x7804 ,®Value); ++ regValue &= ~(1<<8); //Enable Port 6 ++ regValue |= (1<<6); //Disable Port 5 ++ regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY ++ ++#if defined (CONFIG_RAETH_GMAC2) ++ //RGMII2=Normal mode ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15); ++ ++ //GMAC2= RGMII mode ++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14); ++ mii_mgr_write(31, 0x3500, 0x56300); //MT7530 P5 AN, we can ignore this setting?????? ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(GE2, auto-polling) ++ enable_auto_negotiate(0);//set polling address ++ ++ /* set MT7530 Port 5 to PHY 0/4 mode */ ++#if defined (CONFIG_GE_RGMII_INTERNAL_P0_AN) ++ regValue &= ~((1<<13)|(1<<6)); ++ regValue |= ((1<<7)|(1<<16)|(1<<20)); ++#elif defined (CONFIG_GE_RGMII_INTERNAL_P4_AN) ++ regValue &= ~((1<<13)|(1<<6)|(1<<20)); ++ regValue |= ((1<<7)|(1<<16)); ++#endif ++ /*Set MT7530 phy direct access mode**/ ++ regValue &= ~(1<<5); ++ ++ //sysRegWrite(GDMA2_FWD_CFG, 0x20710000); ++#endif ++ regValue |= (1<<16);//change HW-TRAP ++ printk("change HW-TRAP to 0x%x\n",regValue); ++ mii_mgr_write(31, 0x7804 ,regValue); ++#endif ++ mii_mgr_read(31, 0x7800, ®Value); ++ regValue = (regValue >> 9) & 0x3; ++ if(regValue == 0x3)//25Mhz Xtal ++ xtal_mode = 1; ++ else if(regValue == 0x2) //40Mhz ++ xtal_mode = 2; ++ else ++ xtal_mode = 3; ++ ++ if(xtal_mode == 1) { //25Mhz Xtal ++ /* do nothing */ ++ } else if(xtal_mode = 2) { //40Mhz ++ mii_mgr_write(0, 13, 0x1f); // disable MT7530 core clock ++ mii_mgr_write(0, 14, 0x410); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x0); ++ ++ mii_mgr_write(0, 13, 0x1f); // disable MT7530 PLL ++ mii_mgr_write(0, 14, 0x40d); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x2020); ++ ++ mii_mgr_write(0, 13, 0x1f); // for MT7530 core clock = 500Mhz ++ mii_mgr_write(0, 14, 0x40e); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x119); ++ ++ mii_mgr_write(0, 13, 0x1f); // enable MT7530 PLL ++ mii_mgr_write(0, 14, 0x40d); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x2820); ++ ++ udelay(20); //suggest by CD ++ ++ mii_mgr_write(0, 13, 0x1f); // enable MT7530 core clock ++ mii_mgr_write(0, 14, 0x410); ++ mii_mgr_write(0, 13, 0x401f); ++ }else {//20MHz ++ /*TODO*/ ++ } ++ ++#if defined (CONFIG_GE1_TRGMII_FORCE_1200) && defined (CONFIG_MT7621_ASIC) ++ mii_mgr_write(0, 14, 0x3); /*TRGMII*/ ++#else ++ mii_mgr_write(0, 14, 0x1); /*RGMII*/ ++/* set MT7530 central align */ ++ mii_mgr_read(31, 0x7830, ®Value); ++ regValue &= ~1; ++ regValue |= 1<<1; ++ mii_mgr_write(31, 0x7830, regValue); ++ ++ mii_mgr_read(31, 0x7a40, ®Value); ++ regValue &= ~(1<<30); ++ mii_mgr_write(31, 0x7a40, regValue); ++ ++ regValue = 0x855; ++ mii_mgr_write(31, 0x7a78, regValue); ++ ++#endif ++ mii_mgr_write(31, 0x7b00, 0x104); //delay setting for 10/1000M ++ mii_mgr_write(31, 0x7b04, 0x10); //delay setting for 10/1000M ++ ++ /*Tx Driving*/ ++ mii_mgr_write(31, 0x7a54, 0x88); //lower GE1 driving ++ mii_mgr_write(31, 0x7a5c, 0x88); //lower GE1 driving ++ mii_mgr_write(31, 0x7a64, 0x88); //lower GE1 driving ++ mii_mgr_write(31, 0x7a6c, 0x88); //lower GE1 driving ++ mii_mgr_write(31, 0x7a74, 0x88); //lower GE1 driving ++ mii_mgr_write(31, 0x7a7c, 0x88); //lower GE1 driving ++ mii_mgr_write(31, 0x7810, 0x11); //lower GE2 driving ++ /*Set MT7623/MT7683 TX Driving*/ ++ *(volatile u_long *)(0xfb110354) = 0x88; ++ *(volatile u_long *)(0xfb11035c) = 0x88; ++ *(volatile u_long *)(0xfb110364) = 0x88; ++ *(volatile u_long *)(0xfb11036c) = 0x88; ++ *(volatile u_long *)(0xfb110374) = 0x88; ++ *(volatile u_long *)(0xfb11037c) = 0x88; ++#if defined (CONFIG_GE2_RGMII_AN) ++ *(volatile u_long *)(0xf0005f00) = 0xe00; //Set GE2 driving and slew rate ++#else ++ *(volatile u_long *)(0xf0005f00) = 0xa00; //Set GE2 driving and slew rate ++#endif ++ *(volatile u_long *)(0xf00054c0) = 0x5; //set GE2 TDSEL ++ *(volatile u_long *)(0xf0005ed0) = 0; //set GE2 TUNE ++ ++ /* TRGMII Clock */ ++// printk("Set TRGMII mode clock stage 1\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x404); ++ mii_mgr_write(0, 13, 0x401f); ++ if (xtal_mode == 1){ //25MHz ++#if defined (CONFIG_GE1_TRGMII_FORCE_2900) ++ mii_mgr_write(0, 14, 0x1d00); // 362.5MHz ++#elif defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ mii_mgr_write(0, 14, 0x1a00); // 325MHz ++#elif defined (CONFIG_GE1_TRGMII_FORCE_2000) ++ mii_mgr_write(0, 14, 0x1400); //250MHz ++#elif defined (CONFIG_GE1_RGMII_FORCE_1000) ++ mii_mgr_write(0, 14, 0x00a0); //125MHz ++#endif ++ }else if(xtal_mode == 2){//40MHz ++#if defined (CONFIG_GE1_TRGMII_FORCE_2900) ++ mii_mgr_write(0, 14, 0x1220); // 362.5MHz ++#elif defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ mii_mgr_write(0, 14, 0x1040); // 325MHz ++#elif defined (CONFIG_GE1_TRGMII_FORCE_2000) ++ mii_mgr_write(0, 14, 0x0c80); //250MHz ++#elif defined (CONFIG_GE1_RGMII_FORCE_1000) ++ mii_mgr_write(0, 14, 0x0640); //125MHz ++#endif ++ } ++// printk("Set TRGMII mode clock stage 2\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x405); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x0); ++ ++// printk("Set TRGMII mode clock stage 3\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x409); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x0087); ++ ++// printk("Set TRGMII mode clock stage 4\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x40a); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x0087); ++ ++// printk("Set TRGMII mode clock stage 5\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x403); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x1800); ++ ++// printk("Set TRGMII mode clock stage 6\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x403); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x1c00); ++ ++// printk("Set TRGMII mode clock stage 7\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x401); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0xc020); ++ ++// printk("Set TRGMII mode clock stage 8\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x406); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0xa030); ++ ++// printk("Set TRGMII mode clock stage 9\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x406); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0xa038); ++ ++ udelay(120); // for MT7623 bring up test ++ ++// printk("Set TRGMII mode clock stage 10\n"); ++ mii_mgr_write(0, 13, 0x1f); ++ mii_mgr_write(0, 14, 0x410); ++ mii_mgr_write(0, 13, 0x401f); ++ mii_mgr_write(0, 14, 0x3); ++ ++// printk("Set TRGMII mode clock stage 11\n"); ++ ++ mii_mgr_read(31, 0x7830 ,®Value); ++ regValue &=0xFFFFFFFC; ++ regValue |=0x00000001; ++ mii_mgr_write(31, 0x7830, regValue); ++ ++// printk("Set TRGMII mode clock stage 12\n"); ++ mii_mgr_read(31, 0x7a40 ,®Value); ++ regValue &= ~(0x1<<30); ++ regValue &= ~(0x1<<28); ++ mii_mgr_write(31, 0x7a40, regValue); ++ ++ //mii_mgr_write(31, 0x7a78, 0x855); ++ mii_mgr_write(31, 0x7a78, 0x55); ++// printk(" Adjust MT7530 TXC delay\n"); ++ udelay(100); // for mt7623 bring up test ++ ++// printk(" Release MT7623 RXC Reset\n"); ++ *(volatile u_long *)(0xfb110300) &= 0x7fffffff; // Release MT7623 RXC reset ++ //disable EEE ++ for(i=0;i<=4;i++) ++ { ++ mii_mgr_write(i, 13, 0x7); ++ mii_mgr_write(i, 14, 0x3C); ++ mii_mgr_write(i, 13, 0x4007); ++ mii_mgr_write(i, 14, 0x0); ++ } ++ ++ //Disable EEE 10Base-Te: ++ for(i=0;i<=4;i++) ++ { ++ mii_mgr_write(i, 13, 0x1f); ++ mii_mgr_write(i, 14, 0x027b); ++ mii_mgr_write(i, 13, 0x401f); ++ mii_mgr_write(i, 14, 0x1177); ++ } ++ ++ for(i=0;i<=4;i++) ++ { ++ //turn on PHY ++ mii_mgr_read(i, 0x0 ,®Value); ++ regValue &= ~(0x1<<11); ++ mii_mgr_write(i, 0x0, regValue); ++ } ++ ++ for(i=0;i<=4;i++) { ++ mii_mgr_read(i, 4, ®Value); ++ regValue |= (3<<7); //turn on 100Base-T Advertisement ++ mii_mgr_write(i, 4, regValue); ++ ++ mii_mgr_read(i, 9, ®Value); ++ regValue |= (3<<8); //turn on 1000Base-T Advertisement ++ mii_mgr_write(i, 9, regValue); ++ ++ //restart AN ++ mii_mgr_read(i, 0, ®Value); ++ regValue |= (1 << 9); ++ mii_mgr_write(i, 0, regValue); ++ } ++ ++ mii_mgr_read(31, 0x7808 ,®Value); ++ regValue |= (3<<16); //Enable INTR ++ mii_mgr_write(31, 0x7808 ,regValue); ++} ++ ++void mt7623_ethifsys_init(void) ++{ ++#define TRGPLL_CON0 (0xF0209280) ++#define TRGPLL_CON1 (0xF0209284) ++#define TRGPLL_CON2 (0xF0209288) ++#define TRGPLL_PWR_CON0 (0xF020928C) ++#define ETHPLL_CON0 (0xF0209290) ++#define ETHPLL_CON1 (0xF0209294) ++#define ETHPLL_CON2 (0xF0209298) ++#define ETHPLL_PWR_CON0 (0xF020929C) ++#define ETH_PWR_CON (0xF00062A0) ++#define HIF_PWR_CON (0xF00062A4) ++ ++ u32 temp, pwr_ack_status; ++ /*=========================================================================*/ ++ /* Enable ETHPLL & TRGPLL*/ ++ /*=========================================================================*/ ++ /* xPLL PWR ON*/ ++ temp = sysRegRead(ETHPLL_PWR_CON0); ++ sysRegWrite(ETHPLL_PWR_CON0, temp | 0x1); ++ ++ temp = sysRegRead(TRGPLL_PWR_CON0); ++ sysRegWrite(TRGPLL_PWR_CON0, temp | 0x1); ++ ++ udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us)*/ ++ ++ /* xPLL ISO Disable*/ ++ temp = sysRegRead(ETHPLL_PWR_CON0); ++ sysRegWrite(ETHPLL_PWR_CON0, temp & ~0x2); ++ ++ temp = sysRegRead(TRGPLL_PWR_CON0); ++ sysRegWrite(TRGPLL_PWR_CON0, temp & ~0x2); ++ ++ /* xPLL Frequency Set*/ ++ temp = sysRegRead(ETHPLL_CON0); ++ sysRegWrite(ETHPLL_CON0, temp | 0x1); ++#if defined (CONFIG_GE1_TRGMII_FORCE_2900) ++ temp = sysRegRead(TRGPLL_CON0); ++ sysRegWrite(TRGPLL_CON0, temp | 0x1); ++#elif defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ sysRegWrite(TRGPLL_CON1, 0xB2000000); ++ temp = sysRegRead(TRGPLL_CON0); ++ sysRegWrite(TRGPLL_CON0, temp | 0x1); ++#elif defined (CONFIG_GE1_TRGMII_FORCE_2000) ++ sysRegWrite(TRGPLL_CON1, 0xCCEC4EC5); ++ sysRegWrite(TRGPLL_CON0, 0x121); ++#endif ++ udelay(40); /* wait for PLL stable (min delay is 20us)*/ ++ ++ ++ /*=========================================================================*/ ++ /* Power on ETHDMASYS and HIFSYS*/ ++ /*=========================================================================*/ ++ /* Power on ETHDMASYS*/ ++ sysRegWrite(0xF0006000, 0x0b160001); ++ pwr_ack_status = (sysRegRead(ETH_PWR_CON) & 0x0000f000) >> 12; ++ ++ if(pwr_ack_status == 0x0) { ++ printk("ETH already turn on and power on flow will be skipped...\n"); ++ }else { ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp | 0x4); /* PWR_ON*/ ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp | 0x8); /* PWR_ON_S*/ ++ ++ udelay(5); /* wait power settle time (min delay is 1us)*/ ++ ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp & ~0x10); /* PWR_CLK_DIS*/ ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp & ~0x2); /* PWR_ISO*/ ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp & ~0x100); /* SRAM_PDN 0*/ ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp & ~0x200); /* SRAM_PDN 1*/ ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp & ~0x400); /* SRAM_PDN 2*/ ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp & ~0x800); /* SRAM_PDN 3*/ ++ ++ udelay(5); /* wait SRAM settle time (min delay is 1Us)*/ ++ ++ temp = sysRegRead(ETH_PWR_CON) ; ++ sysRegWrite(ETH_PWR_CON, temp | 0x1); /* PWR_RST_B*/ ++ } ++ ++ /* Power on HIFSYS*/ ++ pwr_ack_status = (sysRegRead(HIF_PWR_CON) & 0x0000f000) >> 12; ++ if(pwr_ack_status == 0x0) { ++ printk("HIF already turn on and power on flow will be skipped...\n"); ++ } ++ else { ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp | 0x4); /* PWR_ON*/ ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp | 0x8); /* PWR_ON_S*/ ++ ++ udelay(5); /* wait power settle time (min delay is 1us)*/ ++ ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp & ~0x10); /* PWR_CLK_DIS*/ ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp & ~0x2); /* PWR_ISO*/ ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp & ~0x100); /* SRAM_PDN 0*/ ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp & ~0x200); /* SRAM_PDN 1*/ ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp & ~0x400); /* SRAM_PDN 2*/ ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp & ~0x800); /* SRAM_PDN 3*/ ++ ++ udelay(5); /* wait SRAM settle time (min delay is 1Us)*/ ++ ++ temp = sysRegRead(HIF_PWR_CON) ; ++ sysRegWrite(HIF_PWR_CON, temp | 0x1); /* PWR_RST_B*/ ++ } ++ ++ /* Release mt7530 reset */ ++ temp = le32_to_cpu(*(volatile u_long *)(0xfb000034)); ++ temp &= ~(BIT(2)); ++ *(volatile u_long *)(0xfb000034) = temp; ++} ++#endif ++ ++/** ++ * ra2882eth_init - Module Init code ++ * ++ * Called by kernel to register net_device ++ * ++ */ ++ ++static int fe_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct net_device *dev = alloc_etherdev(sizeof(END_DEVICE)); ++ ++ fe_irq = platform_get_irq(pdev, 0); ++ ++#ifdef CONFIG_RALINK_VISTA_BASIC ++ int sw_id=0; ++ mii_mgr_read(29, 31, &sw_id); ++ is_switch_175c = (sw_id == 0x175c) ? 1:0; ++#endif ++ ++ if (!dev) ++ return -ENOMEM; ++ ++ strcpy(dev->name, DEV_NAME); ++ printk("%s:%s[%d]%d\n", __FILE__, __func__, __LINE__, fe_irq); ++ dev->irq = fe_irq; ++ dev->addr_len = 6; ++ dev->base_addr = RALINK_FRAME_ENGINE_BASE; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ rather_probe(dev); ++#else ++ dev->init = rather_probe; ++#endif ++ ra2880_setup_dev_fptable(dev); ++ ++ /* net_device structure Init */ ++ ethtool_init(dev); ++ printk("Ralink APSoC Ethernet Driver Initilization. %s %d rx/tx descriptors allocated, mtu = %d!\n", RAETH_VERSION, NUM_RX_DESC, dev->mtu); ++#ifdef CONFIG_RAETH_NAPI ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ printk("NAPI enable, Tx Ring = %d, Rx Ring = %d\n", NUM_TX_DESC, NUM_RX_DESC); ++#else ++ printk("NAPI enable, weight = %d, Tx Ring = %d, Rx Ring = %d\n", dev->weight, NUM_TX_DESC, NUM_RX_DESC); ++#endif ++#endif ++ ++ /* Register net device for the driver */ ++ if ( register_netdev(dev) != 0) { ++ printk(KERN_WARNING " " __FILE__ ": No ethernet port found.\n"); ++ return -ENXIO; ++ } ++ ++ ++#ifdef CONFIG_RAETH_NETLINK ++ csr_netlink_init(); ++#endif ++ ret = debug_proc_init(); ++ ++ dev_raether = dev; ++#ifdef CONFIG_ARCH_MT7623 ++ mt7623_ethifsys_init(); ++#endif ++ return ret; ++} ++ ++ ++ ++ ++ ++ ++ ++void fe_sw_init(void) ++{ ++#if defined (CONFIG_GIGAPHY) || defined (CONFIG_RAETH_ROUTER) || defined (CONFIG_100PHY) ++ unsigned int regValue = 0; ++#endif ++ ++ // Case1: RT288x/RT3883/MT7621 GE1 + GigaPhy ++#if defined (CONFIG_GE1_RGMII_AN) ++ enable_auto_negotiate(1); ++ if (isMarvellGigaPHY(1)) { ++#if defined (CONFIG_RT3883_FPGA) ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, ®Value); ++ regValue &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half) ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, regValue); ++ ++ printk("\n Reset MARVELL phy\n"); ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, ®Value); ++ regValue |= 1<<7; //Add delay to RX_CLK for RXD Outputs ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 20, regValue); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, ®Value); ++ regValue |= 1<<15; //PHY Software Reset ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, regValue); ++#elif defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7623_FPGA) ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, ®Value); ++ regValue &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half) ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 9, regValue); ++ ++ /*10Mbps, debug*/ ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 4, 0x461); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, ®Value); ++ regValue |= 1<<9; //restart AN ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 0, regValue); ++#endif ++ ++ } ++ if (isVtssGigaPHY(1)) { ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 1); ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, ®Value); ++ printk("Vitesse phy skew: %x --> ", regValue); ++ regValue |= (0x3<<12); ++ regValue &= ~(0x3<<14); ++ printk("%x\n", regValue); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 28, regValue); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR, 31, 0); ++ } ++#if defined (CONFIG_RALINK_MT7621) ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x21056300);//(P0, Auto mode) ++#endif ++#endif // CONFIG_GE1_RGMII_AN // ++ ++ // Case2: RT3883/MT7621 GE2 + GigaPhy ++#if defined (CONFIG_GE2_RGMII_AN) ++ enable_auto_negotiate(2); ++ if (isMarvellGigaPHY(2)) { ++#if defined (CONFIG_RT3883_FPGA) ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, ®Value); ++ regValue &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half) ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, regValue); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, ®Value); ++ regValue |= 1<<7; //Add delay to RX_CLK for RXD Outputs ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 20, regValue); ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, ®Value); ++ regValue |= 1<<15; //PHY Software Reset ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, regValue); ++#elif defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7623_FPGA) ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, ®Value); ++ regValue &= ~(3<<8); //turn off 1000Base-T Advertisement (9.9=1000Full, 9.8=1000Half) ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 9, regValue); ++ ++ /*10Mbps, debug*/ ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 4, 0x461); ++ ++ ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, ®Value); ++ regValue |= 1<<9; //restart AN ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 0, regValue); ++#endif ++ ++ } ++ if (isVtssGigaPHY(2)) { ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 1); ++ mii_mgr_read(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, ®Value); ++ printk("Vitesse phy skew: %x --> ", regValue); ++ regValue |= (0x3<<12); ++ regValue &= ~(0x3<<14); ++ printk("%x\n", regValue); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 28, regValue); ++ mii_mgr_write(CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2, 31, 0); ++ } ++#if defined (CONFIG_RALINK_MT7621) ++ //RGMII2=Normal mode ++ *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 15); ++ //GMAC2= RGMII mode ++ *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 14); ++ ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(P1, Auto mode) ++#endif ++#endif // CONFIG_GE2_RGMII_AN // ++ ++ // Case3: RT305x/RT335x/RT6855/RT6855A/MT7620 + EmbeddedSW ++#if defined (CONFIG_RT_3052_ESW) && !defined(CONFIG_RALINK_MT7621) && !defined(CONFIG_ARCH_MT7623) ++#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_MT7620) ++ rt_gsw_init(); ++#elif defined(CONFIG_RALINK_RT6855A) ++ rt6855A_gsw_init(); ++#else ++ rt305x_esw_init(); ++#endif ++#endif ++ // Case4: RT288x/RT388x/MT7621 GE1 + Internal GigaSW ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) || defined (CONFIG_GE1_TRGMII_FORCE_1200) || defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) ++#if defined (CONFIG_RALINK_MT7621) ++ setup_internal_gsw(); ++ /*MT7530 Init*/ ++#elif defined (CONFIG_ARCH_MT7623) ++#if defined (CONFIG_GE1_TRGMII_FORCE_2000) || defined (CONFIG_GE1_TRGMII_FORCE_2600) ++ *(volatile u_long *)(0xfb00002c) |= (1<<11); ++#else ++ *(volatile u_long *)(0xfb00002c) &= ~(1<<11); ++#endif ++ setup_internal_gsw(); ++ trgmii_calibration_7623(); ++ trgmii_calibration_7530(); ++ //*(volatile u_long *)(0xfb110300) |= (0x1f << 24); //Just only for 312.5/325MHz ++ *(volatile u_long *)(0xfb110340) = 0x00020000; ++ *(volatile u_long *)(0xfb110304) &= 0x3fffffff; // RX clock gating in MT7623 ++ *(volatile u_long *)(0xfb110300) |= 0x80000000; // Assert RX reset in MT7623 ++ *(volatile u_long *)(0xfb110300 ) &= 0x7fffffff; // Release RX reset in MT7623 ++ *(volatile u_long *)(0xfb110300 +0x04) |= 0xC0000000; // Disable RX clock gating in MT7623 ++/*GE1@125MHz(RGMII mode) TX delay adjustment*/ ++#if defined (CONFIG_GE1_RGMII_FORCE_1000) ++ *(volatile u_long *)(0xfb110350) = 0x55; ++ *(volatile u_long *)(0xfb110358) = 0x55; ++ *(volatile u_long *)(0xfb110360) = 0x55; ++ *(volatile u_long *)(0xfb110368) = 0x55; ++ *(volatile u_long *)(0xfb110370) = 0x55; ++ *(volatile u_long *)(0xfb110378) = 0x855; ++#endif ++ ++ ++#elif defined (CONFIG_MT7623_FPGA) /* Nelson: remove for bring up, should be added!!! */ ++ setup_fpga_gsw(); ++#else ++ sysRegWrite(MDIO_CFG, INIT_VALUE_OF_FORCE_1000_FD); ++#endif ++#endif ++ ++ // Case5: RT388x/MT7621 GE2 + GigaSW ++#if defined (CONFIG_GE2_RGMII_FORCE_1000) ++#if defined (CONFIG_RALINK_MT7621) ++ setup_external_gsw(); ++#else ++ sysRegWrite(MDIO_CFG2, INIT_VALUE_OF_FORCE_1000_FD); ++#endif ++#endif ++ ++ // Case6: RT288x GE1 /RT388x,MT7621 GE1/GE2 + (10/100 Switch or 100PHY) ++#if defined (CONFIG_RAETH_ROUTER) || defined (CONFIG_100PHY) ++ ++ //set GMAC to MII or RvMII mode ++#if defined (CONFIG_RALINK_RT3883) ++ regValue = sysRegRead(SYSCFG1); ++#if defined (CONFIG_GE1_MII_FORCE_100) || defined (CONFIG_GE1_MII_AN) ++ regValue &= ~(0x3 << 12); ++ regValue |= 0x1 << 12; // GE1 MII Mode ++#elif defined (CONFIG_GE1_RVMII_FORCE_100) ++ regValue &= ~(0x3 << 12); ++ regValue |= 0x2 << 12; // GE1 RvMII Mode ++#endif ++ ++#if defined (CONFIG_GE2_MII_FORCE_100) || defined (CONFIG_GE2_MII_AN) ++ regValue &= ~(0x3 << 14); ++ regValue |= 0x1 << 14; // GE2 MII Mode ++#elif defined (CONFIG_GE2_RVMII_FORCE_100) ++ regValue &= ~(0x3 << 14); ++ regValue |= 0x2 << 14; // GE2 RvMII Mode ++#endif ++ sysRegWrite(SYSCFG1, regValue); ++#endif // CONFIG_RALINK_RT3883 // ++ ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ++#if defined (CONFIG_GE1_MII_FORCE_100) ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x5e337);//(P0, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++#endif ++#if defined (CONFIG_GE2_MII_FORCE_100) ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x5e337);//(P1, Force mode, Link Up, 100Mbps, Full-Duplex, FC ON) ++#endif ++#if defined (CONFIG_GE1_MII_AN) || defined (CONFIG_GE1_RGMII_AN) ++ enable_auto_negotiate(1); ++#if defined (CONFIG_RALINK_MT7621) ++ sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x21056300);//(P0, Auto mode) ++#endif ++#endif ++#if defined (CONFIG_GE2_MII_AN) || defined (CONFIG_GE1_RGMII_AN) ++ enable_auto_negotiate(2); ++#if defined (CONFIG_RALINK_MT7621) ++ sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x21056300);//(P1, Auto mode) ++#endif ++#endif ++ ++#else ++#if defined (CONFIG_GE1_MII_FORCE_100) ++#if defined (CONFIG_RALINK_MT7621) ++#else ++ sysRegWrite(MDIO_CFG, INIT_VALUE_OF_FORCE_100_FD); ++#endif ++#endif ++#if defined (CONFIG_GE2_MII_FORCE_100) ++#if defined (CONFIG_RALINK_MT7621) ++#else ++ sysRegWrite(MDIO_CFG2, INIT_VALUE_OF_FORCE_100_FD); ++#endif ++#endif ++ //add switch configuration here for other switch chips. ++#if defined (CONFIG_GE1_MII_FORCE_100) || defined (CONFIG_GE2_MII_FORCE_100) ++ // IC+ 175x: force IC+ switch cpu port is 100/FD ++ mii_mgr_write(29, 22, 0x8420); ++#endif ++ ++ ++#endif // defined (CONFIG_RAETH_ROUTER) || defined (CONFIG_100PHY) // ++ ++} ++ ++ ++/** ++ * ra2882eth_cleanup_module - Module Exit code ++ * ++ * Cmd 'rmmod' will invode the routine to exit the module ++ * ++ */ ++#if 0 ++ void ra2882eth_cleanup_module(void) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local; ++ ++ ei_local = netdev_priv(dev); ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ unregister_netdev(ei_local->PseudoDev); ++ free_netdev(ei_local->PseudoDev); ++#endif ++ unregister_netdev(dev); ++ RAETH_PRINT("Free ei_local and unregister netdev...\n"); ++ ++ free_netdev(dev); ++ debug_proc_exit(); ++#ifdef CONFIG_RAETH_NETLINK ++ csr_netlink_end(); ++#endif ++} ++#endif ++EXPORT_SYMBOL(set_fe_dma_glo_cfg); ++//module_init(ra2882eth_init); ++//module_exit(ra2882eth_cleanup_module); ++ ++const struct of_device_id of_fe_match[] = { ++ { .compatible = "mediatek,mt7623-net", }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, of_fe_match); ++ ++static struct platform_driver fe_driver = { ++ .probe = fe_probe, ++// .remove = ra2882eth_cleanup_module, ++ .driver = { ++ .name = "ralink_soc_eth", ++ .owner = THIS_MODULE, ++ .of_match_table = of_fe_match, ++ }, ++}; ++ ++static int __init init_rtfe(void) ++{ ++ int ret; ++ ret = platform_driver_register(&fe_driver); ++ return ret; ++} ++ ++static void __exit exit_rtfe(void) ++{ ++ platform_driver_unregister(&fe_driver); ++} ++ ++module_init(init_rtfe); ++module_exit(exit_rtfe); ++ ++ ++MODULE_LICENSE("GPL"); +diff --git a/drivers/net/ethernet/raeth/raether.h b/drivers/net/ethernet/raeth/raether.h +new file mode 100644 +index 0000000..7a97109 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/raether.h +@@ -0,0 +1,126 @@ ++#ifndef RA2882ETHEND_H ++#define RA2882ETHEND_H ++ ++#ifdef DSP_VIA_NONCACHEABLE ++#define ESRAM_BASE 0xa0800000 /* 0x0080-0000 ~ 0x00807FFF */ ++#else ++#define ESRAM_BASE 0x80800000 /* 0x0080-0000 ~ 0x00807FFF */ ++#endif ++ ++#define RX_RING_BASE ((int)(ESRAM_BASE + 0x7000)) ++#define TX_RING_BASE ((int)(ESRAM_BASE + 0x7800)) ++ ++#if defined(CONFIG_RALINK_RT2880) ++#define NUM_TX_RINGS 1 ++#else ++#define NUM_TX_RINGS 4 ++#endif ++#ifdef MEMORY_OPTIMIZATION ++#ifdef CONFIG_RAETH_ROUTER ++#define NUM_RX_DESC 32 //128 ++#define NUM_TX_DESC 32 //128 ++#elif CONFIG_RT_3052_ESW ++#define NUM_RX_DESC 16 //64 ++#define NUM_TX_DESC 16 //64 ++#else ++#define NUM_RX_DESC 32 //128 ++#define NUM_TX_DESC 32 //128 ++#endif ++//#define NUM_RX_MAX_PROCESS 32 ++#define NUM_RX_MAX_PROCESS 32 ++#else ++#if defined (CONFIG_RAETH_ROUTER) ++#define NUM_RX_DESC 256 ++#define NUM_TX_DESC 256 ++#elif defined (CONFIG_RT_3052_ESW) ++#if defined (CONFIG_RALINK_MT7621) ++#define NUM_RX_DESC 512 ++#define NUM_QRX_DESC 16 ++#define NUM_TX_DESC 512 ++#else ++#define NUM_RX_DESC 256 ++#define NUM_QRX_DESC NUM_RX_DESC ++#define NUM_TX_DESC 256 ++#endif ++#else ++#define NUM_RX_DESC 256 ++#define NUM_QRX_DESC NUM_RX_DESC ++#define NUM_TX_DESC 256 ++#endif ++#if defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_MT7620) ++#define NUM_RX_MAX_PROCESS 2 ++#else ++#define NUM_RX_MAX_PROCESS 16 ++#endif ++#endif ++#define NUM_LRO_RX_DESC 16 ++ ++#if defined (CONFIG_SUPPORT_OPENWRT) ++#define DEV_NAME "eth0" ++#define DEV2_NAME "eth1" ++#else ++#define DEV_NAME "eth2" ++#define DEV2_NAME "eth3" ++#endif ++ ++#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621) ++#define GMAC0_OFFSET 0xE000 ++#define GMAC2_OFFSET 0xE006 ++#else ++#define GMAC0_OFFSET 0x28 ++#define GMAC2_OFFSET 0x22 ++#endif ++ ++#if defined(CONFIG_RALINK_RT6855A) ++#define IRQ_ENET0 22 ++#elif defined(CONFIG_ARCH_MT7623) ++#define IRQ_ENET0 232 ++#else ++#define IRQ_ENET0 3 /* hardware interrupt #3, defined in RT2880 Soc Design Spec Rev 0.03, pp43 */ ++#endif ++ ++#if defined (CONFIG_RAETH_HW_LRO) ++#define HW_LRO_TIMER_UNIT 1 ++#define HW_LRO_REFRESH_TIME 50000 ++#define HW_LRO_MAX_AGG_CNT 64 ++#define HW_LRO_AGG_DELTA 1 ++#if defined(CONFIG_RAETH_PDMA_DVT) ++#define MAX_LRO_RX_LENGTH 10240 ++#else ++#define MAX_LRO_RX_LENGTH (PAGE_SIZE - SKB_DATA_ALIGN(NET_SKB_PAD + sizeof(struct skb_shared_info))) ++#endif ++#define HW_LRO_AGG_TIME 10 /* 200us */ ++#define HW_LRO_AGE_TIME 50 ++#define HW_LRO_BW_THRE 3000 ++#define HW_LRO_PKT_INT_ALPHA 100 ++#endif /* CONFIG_RAETH_HW_LRO */ ++#define FE_INT_STATUS_REG (*(volatile unsigned long *)(FE_INT_STATUS)) ++#define FE_INT_STATUS_CLEAN(reg) (*(volatile unsigned long *)(FE_INT_STATUS)) = reg ++ ++//#define RAETH_DEBUG ++#ifdef RAETH_DEBUG ++#define RAETH_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args) ++#else ++#define RAETH_PRINT(fmt, args...) { } ++#endif ++ ++struct net_device_stats *ra_get_stats(struct net_device *dev); ++ ++void ei_tx_timeout(struct net_device *dev); ++int rather_probe(struct net_device *dev); ++int ei_open(struct net_device *dev); ++int ei_close(struct net_device *dev); ++ ++int ra2882eth_init(void); ++void ra2882eth_cleanup_module(void); ++ ++void ei_xmit_housekeeping(unsigned long data); ++ ++u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data); ++u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data); ++u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr); ++u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 *read_data); ++u32 mii_mgr_write_cl45(u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data); ++void fe_sw_init(void); ++ ++#endif +diff --git a/drivers/net/ethernet/raeth/raether_hwlro.c b/drivers/net/ethernet/raeth/raether_hwlro.c +new file mode 100755 +index 0000000..5fc4f36 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/raether_hwlro.c +@@ -0,0 +1,347 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ra2882ethreg.h" ++#include "raether.h" ++#include "ra_mac.h" ++#include "ra_ioctl.h" ++#include "ra_rfrw.h" ++ ++#if defined(CONFIG_RAETH_HW_LRO_FORCE) ++int set_fe_lro_ring1_cfg(struct net_device *dev) ++{ ++ unsigned int ip; ++ ++ netdev_printk(KERN_CRIT, dev, "set_fe_lro_ring1_cfg()\n"); ++ ++ /* 1. Set RX ring mode to force port */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_FORCE_PORT); ++ ++ /* 2. Configure lro ring */ ++ /* 2.1 set src/destination TCP ports */ ++ SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING1, 1122); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING1, 3344); ++ /* 2.2 set src/destination IPs */ ++ str_to_ip(&ip, "10.10.10.3"); ++ sysRegWrite(LRO_RX_RING1_SIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.254"); ++ sysRegWrite(LRO_RX_RING1_DIP_DW0, ip); ++ /* 2.3 IPv4 force port mode */ ++ SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING1, 1); ++ /* 2.4 IPv6 force port mode */ ++ SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING1, 1); ++ ++ /* 3. Set Age timer: 10 msec. */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME); ++ ++ /* 4. Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ ++ return 0; ++} ++ ++int set_fe_lro_ring2_cfg(struct net_device *dev) ++{ ++ unsigned int ip; ++ ++ netdev_printk(KERN_CRIT, dev, "set_fe_lro_ring2_cfg()\n"); ++ ++ /* 1. Set RX ring mode to force port */ ++ SET_PDMA_RXRING2_MODE(PDMA_RX_FORCE_PORT); ++ ++ /* 2. Configure lro ring */ ++ /* 2.1 set src/destination TCP ports */ ++ SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING2, 5566); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING2, 7788); ++ /* 2.2 set src/destination IPs */ ++ str_to_ip(&ip, "10.10.10.3"); ++ sysRegWrite(LRO_RX_RING2_SIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.254"); ++ sysRegWrite(LRO_RX_RING2_DIP_DW0, ip); ++ /* 2.3 IPv4 force port mode */ ++ SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING2, 1); ++ /* 2.4 IPv6 force port mode */ ++ SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING2, 1); ++ ++ /* 3. Set Age timer: 10 msec. */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME); ++ ++ /* 4. Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1); ++ ++ return 0; ++} ++ ++int set_fe_lro_ring3_cfg(struct net_device *dev) ++{ ++ unsigned int ip; ++ ++ netdev_printk(KERN_CRIT, dev, "set_fe_lro_ring3_cfg()\n"); ++ ++ /* 1. Set RX ring mode to force port */ ++ SET_PDMA_RXRING3_MODE(PDMA_RX_FORCE_PORT); ++ ++ /* 2. Configure lro ring */ ++ /* 2.1 set src/destination TCP ports */ ++ SET_PDMA_RXRING_TCP_SRC_PORT(ADMA_RX_RING3, 9900); ++ SET_PDMA_RXRING_TCP_DEST_PORT(ADMA_RX_RING3, 99); ++ /* 2.2 set src/destination IPs */ ++ str_to_ip(&ip, "10.10.10.3"); ++ sysRegWrite(LRO_RX_RING3_SIP_DW0, ip); ++ str_to_ip(&ip, "10.10.10.254"); ++ sysRegWrite(LRO_RX_RING3_DIP_DW0, ip); ++ /* 2.3 IPv4 force port mode */ ++ SET_PDMA_RXRING_IPV4_FORCE_MODE(ADMA_RX_RING3, 1); ++ /* 2.4 IPv6 force port mode */ ++ SET_PDMA_RXRING_IPV6_FORCE_MODE(ADMA_RX_RING3, 1); ++ ++ /* 3. Set Age timer: 10 msec. */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME); ++ ++ /* 4. Valid LRO ring */ ++ SET_PDMA_RXRING3_VALID(1); ++ ++ return 0; ++} ++ ++int set_fe_lro_glo_cfg(struct net_device *dev) ++{ ++ unsigned int regVal = 0; ++ ++ netdev_printk(KERN_CRIT, dev, "set_fe_lro_glo_cfg()\n"); ++ ++ /* 1 Set max AGG timer: 10 msec. */ ++ SET_PDMA_LRO_MAX_AGG_TIME(HW_LRO_AGG_TIME); ++ ++ /* 2. Set max LRO agg count */ ++ SET_PDMA_LRO_MAX_AGG_CNT(HW_LRO_MAX_AGG_CNT); ++ ++ /* PDMA prefetch enable setting */ ++ SET_PDMA_LRO_RXD_PREFETCH_EN(0x3); ++ ++ /* 2.1 IPv4 checksum update enable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 3. Polling relinguish */ ++ while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) ++ ; ++ ++ /* 4. Enable LRO */ ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW0); ++ regVal |= PDMA_LRO_EN; ++ sysRegWrite(ADMA_LRO_CTRL_DW0, regVal); ++ ++ return 0; ++} ++#else ++int set_fe_lro_auto_cfg(struct net_device *dev) ++{ ++ unsigned int regVal = 0; ++ unsigned int ip; ++ ++ netdev_printk(KERN_CRIT, dev, "set_fe_lro_auto_cfg()\n"); ++ ++ /* 1.1 Set my IP_1 */ ++ str_to_ip(&ip, "10.10.10.254"); ++ sysRegWrite(LRO_RX_RING0_DIP_DW0, ip); ++ sysRegWrite(LRO_RX_RING0_DIP_DW1, 0); ++ sysRegWrite(LRO_RX_RING0_DIP_DW2, 0); ++ sysRegWrite(LRO_RX_RING0_DIP_DW3, 0); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING0, 1); ++ ++ /* 1.2 Set my IP_2 */ ++ str_to_ip(&ip, "10.10.20.254"); ++ sysRegWrite(LRO_RX_RING1_DIP_DW0, ip); ++ sysRegWrite(LRO_RX_RING1_DIP_DW1, 0); ++ sysRegWrite(LRO_RX_RING1_DIP_DW2, 0); ++ sysRegWrite(LRO_RX_RING1_DIP_DW3, 0); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING1, 1); ++ ++ /* 1.3 Set my IP_3 */ ++ sysRegWrite(LRO_RX_RING2_DIP_DW3, 0x20010238); ++ sysRegWrite(LRO_RX_RING2_DIP_DW2, 0x08000000); ++ sysRegWrite(LRO_RX_RING2_DIP_DW1, 0x00000000); ++ sysRegWrite(LRO_RX_RING2_DIP_DW0, 0x00000254); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING2, 1); ++ ++ /* 1.4 Set my IP_4 */ ++ sysRegWrite(LRO_RX_RING3_DIP_DW3, 0x20010238); ++ sysRegWrite(LRO_RX_RING3_DIP_DW2, 0x08010000); ++ sysRegWrite(LRO_RX_RING3_DIP_DW1, 0x00000000); ++ sysRegWrite(LRO_RX_RING3_DIP_DW0, 0x00000254); ++ SET_PDMA_RXRING_MYIP_VALID(ADMA_RX_RING3, 1); ++ ++ /* 2.1 Set RX ring1~3 to auto-learn modes */ ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING1, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING2, PDMA_RX_AUTO_LEARN); ++ SET_PDMA_RXRING_MODE(ADMA_RX_RING3, PDMA_RX_AUTO_LEARN); ++ ++ /* 2.2 Valid LRO ring */ ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING0, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING1, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING2, 1); ++ SET_PDMA_RXRING_VALID(ADMA_RX_RING3, 1); ++ ++ /* 2.3 Set AGE timer */ ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING1, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING2, HW_LRO_AGE_TIME); ++ SET_PDMA_RXRING_AGE_TIME(ADMA_RX_RING3, HW_LRO_AGE_TIME); ++ ++ /* 2.4 Set max AGG timer */ ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING1, HW_LRO_AGG_TIME); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING2, HW_LRO_AGG_TIME); ++ SET_PDMA_RXRING_AGG_TIME(ADMA_RX_RING3, HW_LRO_AGG_TIME); ++ ++ /* 2.5 Set max LRO agg count */ ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING1, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING2, HW_LRO_MAX_AGG_CNT); ++ SET_PDMA_RXRING_MAX_AGG_CNT(ADMA_RX_RING3, HW_LRO_MAX_AGG_CNT); ++ ++ /* 3.0 IPv6 LRO enable */ ++ SET_PDMA_LRO_IPV6_EN(1); ++ ++ /* 3.1 IPv4 checksum update enable */ ++ SET_PDMA_LRO_IPV4_CSUM_UPDATE_EN(1); ++ ++ /* 3.2 TCP push option check disable */ ++ //SET_PDMA_LRO_IPV4_CTRL_PUSH_EN(0); ++ ++ /* PDMA prefetch enable setting */ ++ SET_PDMA_LRO_RXD_PREFETCH_EN(0x3); ++ ++ /* 3.2 switch priority comparison to byte count mode */ ++/* SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_BYTE_CNT_MODE); */ ++ SET_PDMA_LRO_ALT_SCORE_MODE(PDMA_LRO_ALT_PKT_CNT_MODE); ++ ++ /* 3.3 bandwidth threshold setting */ ++ SET_PDMA_LRO_BW_THRESHOLD(HW_LRO_BW_THRE); ++ ++ /* 3.4 auto-learn score delta setting */ ++ sysRegWrite(LRO_ALT_SCORE_DELTA, 0); ++ ++ /* 3.5 Set ALT timer to 20us: (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER_UNIT(HW_LRO_TIMER_UNIT); ++ /* 3.6 Set ALT refresh timer to 1 sec. (unit: 20us) */ ++ SET_PDMA_LRO_ALT_REFRESH_TIMER(HW_LRO_REFRESH_TIME); ++ ++ /* 3.7 the least remaining room of SDL0 in RXD for lro aggregation */ ++ SET_PDMA_LRO_MIN_RXD_SDL(1522); ++ ++ /* 4. Polling relinguish */ ++ while (sysRegRead(ADMA_LRO_CTRL_DW0) & PDMA_LRO_RELINGUISH) ++ ; ++ ++ /* 5. Enable LRO */ ++ regVal = sysRegRead(ADMA_LRO_CTRL_DW0); ++ regVal |= PDMA_LRO_EN; ++ sysRegWrite(ADMA_LRO_CTRL_DW0, regVal); ++ ++ return 0; ++} ++#endif /* CONFIG_RAETH_HW_LRO_FORCE */ ++ ++int fe_hw_lro_init(struct net_device *dev) ++{ ++ int i; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ++ /* Initial RX Ring 3 */ ++ ei_local->rx_ring3 = ++ pci_alloc_consistent(NULL, NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc), ++ &ei_local->phy_rx_ring3); ++ for (i = 0; i < NUM_LRO_RX_DESC; i++) { ++ memset(&ei_local->rx_ring3[i], 0, sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring3[i].rxd_info2.DDONE_bit = 0; ++ ei_local->rx_ring3[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring3[i].rxd_info2.PLEN0 = ++ SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH); ++ ei_local->rx_ring3[i].rxd_info2.PLEN1 = ++ SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14); ++ ei_local->rx_ring3[i].rxd_info1.PDP0 = ++ dma_map_single(NULL, ei_local->netrx3_skbuf[i]->data, ++ MAX_LRO_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ netdev_printk(KERN_CRIT, dev, ++ "\nphy_rx_ring3 = 0x%08x, rx_ring3 = 0x%p\n", ++ ei_local->phy_rx_ring3, ei_local->rx_ring3); ++ /* Initial RX Ring 2 */ ++ ei_local->rx_ring2 = ++ pci_alloc_consistent(NULL, NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc), ++ &ei_local->phy_rx_ring2); ++ for (i = 0; i < NUM_LRO_RX_DESC; i++) { ++ memset(&ei_local->rx_ring2[i], 0, sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring2[i].rxd_info2.DDONE_bit = 0; ++ ei_local->rx_ring2[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring2[i].rxd_info2.PLEN0 = ++ SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH); ++ ei_local->rx_ring2[i].rxd_info2.PLEN1 = ++ SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14); ++ ei_local->rx_ring2[i].rxd_info1.PDP0 = ++ dma_map_single(NULL, ei_local->netrx2_skbuf[i]->data, ++ MAX_LRO_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ netdev_printk(KERN_CRIT, dev, ++ "\nphy_rx_ring2 = 0x%08x, rx_ring2 = 0x%p\n", ++ ei_local->phy_rx_ring2, ei_local->rx_ring2); ++ /* Initial RX Ring 1 */ ++ ei_local->rx_ring1 = ++ pci_alloc_consistent(NULL, NUM_LRO_RX_DESC * sizeof(struct PDMA_rxdesc), ++ &ei_local->phy_rx_ring1); ++ for (i = 0; i < NUM_LRO_RX_DESC; i++) { ++ memset(&ei_local->rx_ring1[i], 0, sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0; ++ ei_local->rx_ring1[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring1[i].rxd_info2.PLEN0 = ++ SET_ADMA_RX_LEN0(MAX_LRO_RX_LENGTH); ++ ei_local->rx_ring1[i].rxd_info2.PLEN1 = ++ SET_ADMA_RX_LEN1(MAX_LRO_RX_LENGTH >> 14); ++ ei_local->rx_ring1[i].rxd_info1.PDP0 = ++ dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, ++ MAX_LRO_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ netdev_printk(KERN_CRIT, dev, ++ "\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n", ++ ei_local->phy_rx_ring1, ei_local->rx_ring1); ++ ++ sysRegWrite(RX_BASE_PTR3, phys_to_bus((u32) ei_local->phy_rx_ring3)); ++ sysRegWrite(RX_MAX_CNT3, cpu_to_le32((u32) NUM_LRO_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX3, cpu_to_le32((u32) (NUM_LRO_RX_DESC - 1))); ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX3); ++ sysRegWrite(RX_BASE_PTR2, phys_to_bus((u32) ei_local->phy_rx_ring2)); ++ sysRegWrite(RX_MAX_CNT2, cpu_to_le32((u32) NUM_LRO_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX2, cpu_to_le32((u32) (NUM_LRO_RX_DESC - 1))); ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX2); ++ sysRegWrite(RX_BASE_PTR1, phys_to_bus((u32) ei_local->phy_rx_ring1)); ++ sysRegWrite(RX_MAX_CNT1, cpu_to_le32((u32) NUM_LRO_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX1, cpu_to_le32((u32) (NUM_LRO_RX_DESC - 1))); ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX1); ++ ++#if defined(CONFIG_RAETH_HW_LRO_FORCE) ++ set_fe_lro_ring1_cfg(dev); ++ set_fe_lro_ring2_cfg(dev); ++ set_fe_lro_ring3_cfg(dev); ++ set_fe_lro_glo_cfg(dev); ++#else ++ set_fe_lro_auto_cfg(dev); ++#endif /* CONFIG_RAETH_HW_LRO_FORCE */ ++ ++ /* HW LRO parameter settings */ ++ ei_local->hw_lro_alpha = HW_LRO_PKT_INT_ALPHA; ++ ei_local->hw_lro_fix_setting = 1; ++ ++ return 1; ++} ++EXPORT_SYMBOL(fe_hw_lro_init); ++ +diff --git a/drivers/net/ethernet/raeth/raether_pdma.c b/drivers/net/ethernet/raeth/raether_pdma.c +new file mode 100755 +index 0000000..4d47ee2 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/raether_pdma.c +@@ -0,0 +1,1121 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined (CONFIG_RAETH_TSO) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++#if defined (CONFIG_RAETH_LRO) ++#include ++#endif ++#include ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) ++#include ++#else ++#include ++#endif ++ ++#include "ra2882ethreg.h" ++#include "raether.h" ++#include "ra_mac.h" ++#include "ra_ioctl.h" ++#include "ra_rfrw.h" ++#ifdef CONFIG_RAETH_NETLINK ++#include "ra_netlink.h" ++#endif ++#if defined (CONFIG_RAETH_QOS) ++#include "ra_qos.h" ++#endif ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++#include "../../../net/nat/hw_nat/ra_nat.h" ++#endif ++#if defined(CONFIG_RAETH_PDMA_DVT) ++#include "dvt/raether_pdma_dvt.h" ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ ++#if !defined(CONFIG_RA_NAT_NONE) ++/* bruce+ ++ */ ++extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb); ++extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no); ++#endif ++ ++#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE) ++/* Qwert+ ++ */ ++#include ++extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle); ++extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle); ++#endif /* CONFIG_RA_CLASSIFIER */ ++ ++#if defined (CONFIG_RALINK_RT3052_MP2) ++int32_t mcast_rx(struct sk_buff * skb); ++int32_t mcast_tx(struct sk_buff * skb); ++#endif ++ ++#if 0 ++#ifdef RA_MTD_RW_BY_NUM ++int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf); ++#else ++int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf); ++#endif ++#endif ++/* gmac driver feature set config */ ++#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS) ++#undef DELAY_INT ++#else ++#if defined (CONFIG_ARCH_MT7623) ++#undef DELAY_INT ++#else ++#define DELAY_INT 1 ++#endif ++#endif ++ ++//#define CONFIG_UNH_TEST ++/* end of config */ ++ ++#if defined (CONFIG_RAETH_JUMBOFRAME) ++#define MAX_RX_LENGTH 4096 ++#else ++#define MAX_RX_LENGTH 1536 ++#endif ++ ++extern struct net_device *dev_raether; ++ ++ ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++extern int rx_calc_idx1; ++#endif ++#endif ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++extern int rx_calc_idx0; ++static unsigned long tx_cpu_owner_idx0=0; ++#endif ++extern unsigned long tx_ring_full; ++ ++#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/ ++#include "ra_ethtool.h" ++extern struct ethtool_ops ra_ethtool_ops; ++#ifdef CONFIG_PSEUDO_SUPPORT ++extern struct ethtool_ops ra_virt_ethtool_ops; ++#endif // CONFIG_PSEUDO_SUPPORT // ++#endif // (CONFIG_ETHTOOL // ++ ++#ifdef CONFIG_RALINK_VISTA_BASIC ++int is_switch_175c = 1; ++#endif ++ ++#ifdef CONFIG_RAETH_PDMATX_QDMARX /* QDMA RX */ ++struct QDMA_txdesc *free_head = NULL; ++#endif ++ ++//#if defined (CONFIG_RAETH_LRO) ++#if 0 ++unsigned int lan_ip; ++struct lro_para_struct lro_para; ++int lro_flush_needed; ++extern char const *nvram_get(int index, char *name); ++#endif ++ ++#define KSEG1 0xa0000000 ++#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1)) ++#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1) ++ ++extern void set_fe_dma_glo_cfg(void); ++ ++/* ++ * @brief cal txd number for a page ++ * ++ * @parm size ++ * ++ * @return frag_txd_num ++ */ ++ ++unsigned int cal_frag_txd_num(unsigned int size) ++{ ++ unsigned int frag_txd_num = 0; ++ if(size == 0) ++ return 0; ++ while(size > 0){ ++ if(size > MAX_TXD_LEN){ ++ frag_txd_num++; ++ size -= MAX_TXD_LEN; ++ }else{ ++ frag_txd_num++; ++ size = 0; ++ } ++ } ++ return frag_txd_num; ++ ++} ++ ++#ifdef CONFIG_RAETH_PDMATX_QDMARX /* QDMA RX */ ++bool fq_qdma_init(struct net_device *dev) ++{ ++ END_DEVICE* ei_local = netdev_priv(dev); ++ unsigned int phy_free_head; ++ unsigned int phy_free_tail; ++ unsigned int *free_page_head = NULL; ++ unsigned int phy_free_page_head; ++ int i; ++ ++ free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &phy_free_head); ++ if (unlikely(free_head == NULL)){ ++ printk(KERN_ERR "QDMA FQ decriptor not available...\n"); ++ return 0; ++ } ++ memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE); ++ ++ free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &phy_free_page_head); ++ if (unlikely(free_page_head == NULL)){ ++ printk(KERN_ERR "QDMA FQ page not available...\n"); ++ return 0; ++ } ++ for (i=0; i < NUM_QDMA_PAGE; i++) { ++ free_head[i].txd_info1.SDP = (phy_free_page_head + (i * QDMA_PAGE_SIZE)); ++ if(i < (NUM_QDMA_PAGE-1)){ ++ free_head[i].txd_info2.NDP = (phy_free_head + ((i+1) * sizeof(struct QDMA_txdesc))); ++ ++ ++#if 0 ++ printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) ); ++ printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] ); ++ printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP ); ++ printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP ); ++#endif ++ } ++ free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE; ++ ++ } ++ phy_free_tail = (phy_free_head + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc))); ++ ++ printk("phy_free_head is 0x%x!!!\n", phy_free_head); ++ printk("phy_free_tail_phy is 0x%x!!!\n", phy_free_tail); ++ sysRegWrite(QDMA_FQ_HEAD, (u32)phy_free_head); ++ sysRegWrite(QDMA_FQ_TAIL, (u32)phy_free_tail); ++ sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE)); ++ sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16); ++ ++ ei_local->free_head = free_head; ++ ei_local->phy_free_head = phy_free_head; ++ ei_local->free_page_head = free_page_head; ++ ei_local->phy_free_page_head = phy_free_page_head; ++ return 1; ++} ++#endif ++ ++int fe_dma_init(struct net_device *dev) ++{ ++ ++ int i; ++ unsigned int regVal; ++ END_DEVICE* ei_local = netdev_priv(dev); ++#if defined (CONFIG_RAETH_QOS) ++ int j; ++#endif ++ ++ while(1) ++ { ++ regVal = sysRegRead(PDMA_GLO_CFG); ++ if((regVal & RX_DMA_BUSY)) ++ { ++ printk("\n RX_DMA_BUSY !!! "); ++ continue; ++ } ++ if((regVal & TX_DMA_BUSY)) ++ { ++ printk("\n TX_DMA_BUSY !!! "); ++ continue; ++ } ++ break; ++ } ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++ pdma_dvt_set_dma_mode(); ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ ++#if defined (CONFIG_RAETH_QOS) ++ for (i=0;iskb_free[i][j]=0; ++ } ++ ei_local->free_idx[i]=0; ++ } ++ /* ++ * RT2880: 2 x TX_Ring, 1 x Rx_Ring ++ * RT2883: 4 x TX_Ring, 1 x Rx_Ring ++ * RT3883: 4 x TX_Ring, 1 x Rx_Ring ++ * RT3052: 4 x TX_Ring, 1 x Rx_Ring ++ */ ++ fe_tx_desc_init(dev, 0, 3, 1); ++ if (ei_local->tx_ring0 == NULL) { ++ printk("RAETH: tx ring0 allocation failed\n"); ++ return 0; ++ } ++ ++ fe_tx_desc_init(dev, 1, 3, 1); ++ if (ei_local->tx_ring1 == NULL) { ++ printk("RAETH: tx ring1 allocation failed\n"); ++ return 0; ++ } ++ ++ printk("\nphy_tx_ring0 = %08x, tx_ring0 = %p, size: %d bytes\n", ei_local->phy_tx_ring0, ei_local->tx_ring0, sizeof(struct PDMA_txdesc)); ++ ++ printk("\nphy_tx_ring1 = %08x, tx_ring1 = %p, size: %d bytes\n", ei_local->phy_tx_ring1, ei_local->tx_ring1, sizeof(struct PDMA_txdesc)); ++ ++#if ! defined (CONFIG_RALINK_RT2880) ++ fe_tx_desc_init(dev, 2, 3, 1); ++ if (ei_local->tx_ring2 == NULL) { ++ printk("RAETH: tx ring2 allocation failed\n"); ++ return 0; ++ } ++ ++ fe_tx_desc_init(dev, 3, 3, 1); ++ if (ei_local->tx_ring3 == NULL) { ++ printk("RAETH: tx ring3 allocation failed\n"); ++ return 0; ++ } ++ ++ printk("\nphy_tx_ring2 = %08x, tx_ring2 = %p, size: %d bytes\n", ei_local->phy_tx_ring2, ei_local->tx_ring2, sizeof(struct PDMA_txdesc)); ++ ++ printk("\nphy_tx_ring3 = %08x, tx_ring3 = %p, size: %d bytes\n", ei_local->phy_tx_ring3, ei_local->tx_ring3, sizeof(struct PDMA_txdesc)); ++ ++#endif // CONFIG_RALINK_RT2880 // ++#else ++ for (i=0;iskb_free[i]=0; ++ } ++ ei_local->free_idx =0; ++#if defined (CONFIG_MIPS) ++ ei_local->tx_ring0 = pci_alloc_consistent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0); ++#else ++ ei_local->tx_ring0 = dma_alloc_coherent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0, GFP_KERNEL); ++#endif ++ printk("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n", ei_local->phy_tx_ring0, ei_local->tx_ring0); ++ ++ for (i=0; i < NUM_TX_DESC; i++) { ++ memset(&ei_local->tx_ring0[i],0,sizeof(struct PDMA_txdesc)); ++ ei_local->tx_ring0[i].txd_info2.LS0_bit = 1; ++ ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1; ++ ++ } ++#endif // CONFIG_RAETH_QOS ++ ++#ifdef CONFIG_RAETH_PDMATX_QDMARX /* QDMA RX */ ++ ++ fq_qdma_init(dev); ++ ++ while(1) ++ { ++ regVal = sysRegRead(QDMA_GLO_CFG); ++ if((regVal & RX_DMA_BUSY)) ++ { ++ printk("\n RX_DMA_BUSY !!! "); ++ continue; ++ } ++ if((regVal & TX_DMA_BUSY)) ++ { ++ printk("\n TX_DMA_BUSY !!! "); ++ continue; ++ } ++ break; ++ } ++ ++ /* Initial RX Ring 0*/ ++ ++#ifdef CONFIG_32B_DESC ++ ei_local->qrx_ring = kmalloc(NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL); ++ ei_local->phy_qrx_ring = virt_to_phys(ei_local->qrx_ring); ++#else ++ ei_local->qrx_ring = pci_alloc_consistent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_qrx_ring); ++#endif ++ for (i = 0; i < NUM_QRX_DESC; i++) { ++ memset(&ei_local->qrx_ring[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->qrx_ring[i].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ ei_local->qrx_ring[i].rxd_info2.LS0 = 0; ++ ei_local->qrx_ring[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++#else ++ ei_local->qrx_ring[i].rxd_info2.LS0 = 1; ++#endif ++ ei_local->qrx_ring[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("\nphy_qrx_ring = 0x%08x, qrx_ring = 0x%p\n",ei_local->phy_qrx_ring,ei_local->qrx_ring); ++ ++ regVal = sysRegRead(QDMA_GLO_CFG); ++ regVal &= 0x000000FF; ++ ++ sysRegWrite(QDMA_GLO_CFG, regVal); ++ regVal=sysRegRead(QDMA_GLO_CFG); ++ ++ /* Tell the adapter where the TX/RX rings are located. */ ++ ++ sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_qrx_ring)); ++ sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_QRX_DESC)); ++ sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_QRX_DESC - 1))); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = rx_dma_owner_idx0 = sysRegRead(QRX_CRX_IDX_0); ++#endif ++ sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0); ++ ++ ei_local->rx_ring0 = ei_local->qrx_ring; ++ ++#else /* PDMA RX */ ++ ++ /* Initial RX Ring 0*/ ++#ifdef CONFIG_32B_DESC ++ ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL); ++ ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0); ++#else ++#if defined (CONFIG_MIPS) ++ ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0); ++#else ++ ei_local->rx_ring0 = dma_alloc_coherent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0, GFP_KERNEL); ++#endif ++#endif ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++#else ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 1; ++#endif ++ ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0); ++ ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++ /* Initial RX Ring 1*/ ++#ifdef CONFIG_32B_DESC ++ ei_local->rx_ring1 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL); ++ ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1); ++#else ++#if defined (CONFIG_MIPS) ++ ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1); ++#else ++ ei_local->rx_ring1 = dma_alloc_coherent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1, GFP_KERNEL); ++ ++#endif ++#endif ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ ei_local->rx_ring1[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring1[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++#else ++ ei_local->rx_ring1[i].rxd_info2.LS0 = 1; ++#endif ++ ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1); ++#if defined(CONFIG_ARCH_MT7623) ++ /* Initial RX Ring 2*/ ++ ei_local->rx_ring2 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring2); ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ memset(&ei_local->rx_ring2[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring2[i].rxd_info2.DDONE_bit = 0; ++ ei_local->rx_ring2[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring2[i].rxd_info2.PLEN0 = SET_ADMA_RX_LEN0(MAX_RX_LENGTH); ++ ei_local->rx_ring2[i].rxd_info2.PLEN1 = SET_ADMA_RX_LEN1(MAX_RX_LENGTH >> 14); ++ ei_local->rx_ring2[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx2_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("\nphy_rx_ring2 = 0x%08x, rx_ring2 = 0x%p\n",ei_local->phy_rx_ring2,ei_local->rx_ring2); ++ /* Initial RX Ring 3*/ ++ ei_local->rx_ring3 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring3); ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ memset(&ei_local->rx_ring3[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring3[i].rxd_info2.DDONE_bit = 0; ++ ei_local->rx_ring3[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring3[i].rxd_info2.PLEN0 = SET_ADMA_RX_LEN0(MAX_RX_LENGTH); ++ ei_local->rx_ring3[i].rxd_info2.PLEN1 = SET_ADMA_RX_LEN1(MAX_RX_LENGTH >> 14); ++ ei_local->rx_ring3[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx3_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("\nphy_rx_ring3 = 0x%08x, rx_ring3 = 0x%p\n",ei_local->phy_rx_ring3,ei_local->rx_ring3); ++#endif /* CONFIG_ARCH_MT7623 */ ++#endif ++ ++#endif ++ ++ regVal = sysRegRead(PDMA_GLO_CFG); ++ regVal &= 0x000000FF; ++ sysRegWrite(PDMA_GLO_CFG, regVal); ++ regVal=sysRegRead(PDMA_GLO_CFG); ++ ++ /* Tell the adapter where the TX/RX rings are located. */ ++#if !defined (CONFIG_RAETH_QOS) ++ sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0)); ++ sysRegWrite(TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC)); ++ sysRegWrite(TX_CTX_IDX0, 0); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ tx_cpu_owner_idx0 = 0; ++#endif ++ sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0); ++#endif ++ ++#ifdef CONFIG_RAETH_PDMATX_QDMARX /* QDMA RX */ ++ sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_qrx_ring)); ++ sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_QRX_DESC)); ++ sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_QRX_DESC - 1))); ++#else /* PDMA RX */ ++ sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0)); ++ sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1))); ++#endif ++ ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = sysRegRead(RX_CALC_IDX0); ++#endif ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0); ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++ sysRegWrite(RX_BASE_PTR1, phys_to_bus((u32) ei_local->phy_rx_ring1)); ++ sysRegWrite(RX_MAX_CNT1, cpu_to_le32((u32) NUM_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX1, cpu_to_le32((u32) (NUM_RX_DESC - 1))); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx1 = sysRegRead(RX_CALC_IDX1); ++#endif ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX1); ++#if defined(CONFIG_ARCH_MT7623) ++ sysRegWrite(RX_BASE_PTR2, phys_to_bus((u32) ei_local->phy_rx_ring2)); ++ sysRegWrite(RX_MAX_CNT2, cpu_to_le32((u32) NUM_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX2, cpu_to_le32((u32) (NUM_RX_DESC - 1))); ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX2); ++ sysRegWrite(RX_BASE_PTR3, phys_to_bus((u32) ei_local->phy_rx_ring3)); ++ sysRegWrite(RX_MAX_CNT3, cpu_to_le32((u32) NUM_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX3, cpu_to_le32((u32) (NUM_RX_DESC - 1))); ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX3); ++#endif /* CONFIG_ARCH_MT7623 */ ++#endif ++#if defined (CONFIG_RALINK_RT6855A) ++ regVal = sysRegRead(RX_DRX_IDX0); ++ regVal = (regVal == 0)? (NUM_RX_DESC - 1) : (regVal - 1); ++ sysRegWrite(RX_CALC_IDX0, cpu_to_le32(regVal)); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = sysRegRead(RX_CALC_IDX0); ++#endif ++ regVal = sysRegRead(TX_DTX_IDX0); ++ sysRegWrite(TX_CTX_IDX0, cpu_to_le32(regVal)); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ tx_cpu_owner_idx0 = regVal; ++#endif ++ ei_local->free_idx = regVal; ++#endif ++ ++#if defined (CONFIG_RAETH_QOS) ++ set_scheduler_weight(); ++ set_schedule_pause_condition(); ++ set_output_shaper(); ++#endif ++ ++ set_fe_dma_glo_cfg(); ++ ++ return 1; ++} ++ ++inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no) ++{ ++ unsigned int length=skb->len; ++ END_DEVICE* ei_local = netdev_priv(dev); ++#ifndef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ unsigned long tx_cpu_owner_idx0 = sysRegRead(TX_CTX_IDX0); ++#endif ++#if defined (CONFIG_RAETH_TSO) ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ unsigned long ctx_idx_start_addr = tx_cpu_owner_idx0; ++#endif ++ struct iphdr *iph = NULL; ++ struct tcphdr *th = NULL; ++ struct skb_frag_struct *frag; ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags; ++ int i=0; ++ unsigned int len, size, offset, frag_txd_num, skb_txd_num ; ++#endif // CONFIG_RAETH_TSO // ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ struct ipv6hdr *ip6h = NULL; ++#endif ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ PSEUDO_ADAPTER *pAd; ++#endif ++ ++ while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0) ++ { ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (gmac_no == 2) { ++ if (ei_local->PseudoDev != NULL) { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.tx_errors++; ++ } ++ } else ++#endif ++ ei_local->stat.tx_errors++; ++ } ++ ++#if !defined (CONFIG_RAETH_TSO) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data); ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = length; ++#if defined (CONFIG_RALINK_MT7620) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FP_BMAP = 0; ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ if (gmac_no == 1) { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1; ++ }else { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2; ++ } ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = gmac_no; ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.QN = 3; ++#endif ++ ++#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined(CONFIG_RALINK_MT7628) ++ if (skb->ip_summed == CHECKSUM_PARTIAL){ ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO = 7; ++ }else { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO = 0; ++ } ++#endif ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++ if(vlan_tx_tag_present(skb)) { ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb); ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VPRI_VIDX = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF); ++#endif ++ }else { ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0; ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VPRI_VIDX = 0; ++#endif ++ } ++#endif ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++ raeth_pdma_tx_vlan_dvt( ei_local, tx_cpu_owner_idx0 ); ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if(ra_sw_nat_hook_rx!= NULL){ ++#if defined (CONFIG_RALINK_MT7620) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FP_BMAP = (1 << 7); /* PPE */ ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 4; /* PPE */ ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = 6; /* PPE */ ++#endif ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++ raeth_pdma_tx_desc_dvt( ei_local, tx_cpu_owner_idx0 ); ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0; ++ ++#if 0 ++ printk("---------------\n"); ++ printk("tx_info1=%x\n",ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1); ++ printk("tx_info2=%x\n",ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2); ++ printk("tx_info3=%x\n",ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3); ++ printk("tx_info4=%x\n",ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4); ++#endif ++ ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data); ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = (length - skb->data_len); ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit = nr_frags ? 0:1; ++#if defined (CONFIG_RALINK_MT7620) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FP_BMAP = 0; ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ if (gmac_no == 1) { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1; ++ }else { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2; ++ } ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = gmac_no; ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.QN = 3; ++#endif ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TSO = 0; ++ ++#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined(CONFIG_RALINK_MT7628) ++ if (skb->ip_summed == CHECKSUM_PARTIAL){ ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO = 7; ++ }else { ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.TUI_CO = 0; ++ } ++#endif ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++ if(vlan_tx_tag_present(skb)) { ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb); ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VPRI_VIDX = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF); ++#endif ++ }else { ++#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VLAN_TAG = 0; ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.VPRI_VIDX = 0; ++#endif ++ } ++#endif ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++ raeth_pdma_tx_vlan_dvt( ei_local, tx_cpu_owner_idx0 ); ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if(ra_sw_nat_hook_rx!= NULL){ ++#if defined (CONFIG_RALINK_MT7620) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FP_BMAP = (1 << 7); /* PPE */ ++#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_ARCH_MT7623) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 4; /* PPE */ ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.PN = 6; /* PPE */ ++#endif ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++ ++ skb_txd_num = 1; ++ ++ if(nr_frags > 0) { ++ ++ for(i=0;ifrags[i]; ++ offset = frag->page_offset; ++ len = frag->size; ++ frag_txd_num = cal_frag_txd_num(len); ++ ++ while(frag_txd_num > 0){ ++ if(len < MAX_TXD_LEN) ++ size = len; ++ else ++ size = MAX_TXD_LEN; ++ if(skb_txd_num%2 == 0) { ++ tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC; ++ ++ while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0) ++ { ++#ifdef config_pseudo_support ++ if (gmac_no == 2) { ++ if (ei_local->pseudodev != null) { ++ pad = netdev_priv(ei_local->pseudodev); ++ pad->stat.tx_errors++; ++ } ++ } else ++#endif ++ ei_local->stat.tx_errors++; ++ } ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = pci_map_page(NULL, frag->page, offset, size, PCI_DMA_TODEVICE); ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = pci_map_page(NULL, frag->page.p, offset, size, PCI_DMA_TODEVICE); ++#endif ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = size; ++ ++ if( (i==(nr_frags-1)) && (frag_txd_num == 1)) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit = 1; ++ else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS0_bit = 0; ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0; ++ }else { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3.SDP1 = pci_map_page(NULL, frag->page, offset, size, PCI_DMA_TODEVICE); ++#else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info3.SDP1 = pci_map_page(NULL, frag->page.p, offset, size, PCI_DMA_TODEVICE); ++ ++#endif ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL1 = size; ++ if( (i==(nr_frags-1)) && (frag_txd_num == 1)) ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS1_bit = 1; ++ else ++ ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.LS1_bit = 0; ++ } ++ offset += size; ++ len -= size; ++ frag_txd_num--; ++ skb_txd_num++; ++ } ++ } ++ } ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++ if( (pdma_dvt_get_debug_test_config() & PDMA_TEST_TSO_DEBUG) ){ ++ printk("skb_shinfo(skb)->gso_segs = %d\n", skb_shinfo(skb)->gso_segs); ++ } ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ /* fill in MSS info in tcp checksum field */ ++ if(skb_shinfo(skb)->gso_segs > 1) { ++ ++// TsoLenUpdate(skb->len); ++ ++ /* TCP over IPv4 */ ++ iph = (struct iphdr *)skb_network_header(skb); ++#if defined (CONFIG_RAETH_TSOV6) ++ /* TCP over IPv6 */ ++ ip6h = (struct ipv6hdr *)skb_network_header(skb); ++#endif ++ if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ ei_local->tx_ring0[ctx_idx_start_addr].txd_info4.TSO = 1; ++#else ++ ei_local->tx_ring0[sysRegRead(TX_CTX_IDX0)].txd_info4.TSO = 1; ++#endif ++ th->check = htons(skb_shinfo(skb)->gso_size); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++#endif ++ } ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ /* TCP over IPv6 */ ++ else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ ei_local->tx_ring0[ctx_idx_start_addr].txd_info4.TSO = 1; ++#else ++ ei_local->tx_ring0[sysRegRead(TX_CTX_IDX0)].txd_info4.TSO = 1; ++#endif ++ th->check = htons(skb_shinfo(skb)->gso_size); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++#endif ++ } ++#endif // CONFIG_RAETH_TSOV6 // ++ } ++ ++#if defined(CONFIG_RAETH_PDMA_DVT) ++ raeth_pdma_tx_desc_dvt( ei_local, tx_cpu_owner_idx0 ); ++#endif /* CONFIG_RAETH_PDMA_DVT */ ++ ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ ei_local->tx_ring0[ctx_idx_start_addr].txd_info2.DDONE_bit = 0; ++#else ++ ei_local->tx_ring0[sysRegRead(TX_CTX_IDX0)].txd_info2.DDONE_bit = 0; ++#endif ++#endif // CONFIG_RAETH_TSO // ++ ++ tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC; ++ while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0) ++ { ++// printk(KERN_ERR "%s: TXD=%lu TX DMA is Busy !!\n", dev->name, tx_cpu_owner_idx0); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (gmac_no == 2) { ++ if (ei_local->PseudoDev != NULL) { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.tx_errors++; ++ } ++ } else ++#endif ++ ei_local->stat.tx_errors++; ++ } ++ sysRegWrite(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0)); ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (gmac_no == 2) { ++ if (ei_local->PseudoDev != NULL) { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.tx_packets++; ++ pAd->stat.tx_bytes += length; ++ } ++ } else ++#endif ++ { ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += length; ++ } ++#ifdef CONFIG_RAETH_NAPI ++ if ( ei_local->tx_full == 1) { ++ ei_local->tx_full = 0; ++ netif_wake_queue(dev); ++ } ++#endif ++ ++ return length; ++} ++ ++int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned long flags; ++ unsigned long tx_cpu_owner_idx; ++ unsigned int tx_cpu_owner_idx_next; ++ unsigned int num_of_txd = 0; ++#if defined (CONFIG_RAETH_TSO) ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i; ++ struct skb_frag_struct *frag; ++#endif ++#if !defined(CONFIG_RAETH_QOS) ++ unsigned int tx_cpu_owner_idx_next2; ++#else ++ int ring_no, queue_no, port_no; ++#endif ++#ifdef CONFIG_RALINK_VISTA_BASIC ++ struct vlan_ethhdr *veth; ++#endif ++#ifdef CONFIG_PSEUDO_SUPPORT ++ PSEUDO_ADAPTER *pAd; ++#endif ++ ++#if !defined(CONFIG_RA_NAT_NONE) ++ if(ra_sw_nat_hook_tx!= NULL) ++ { ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(FOE_MAGIC_TAG(skb) != FOE_MAGIC_PPE) ++#endif ++ { ++ //spin_lock_irqsave(&ei_local->page_lock, flags); ++ if(ra_sw_nat_hook_tx(skb, gmac_no)==1){ ++ //spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ }else{ ++ kfree_skb(skb); ++ //spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++ } ++ } ++ } ++#endif ++#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE) ++ /* Qwert+ ++ */ ++ if(ra_classifier_hook_tx!= NULL) ++ { ++#if defined(CONFIG_RALINK_EXTERNAL_TIMER) ++ ra_classifier_hook_tx(skb, (*((volatile u32 *)(0xB0000D08))&0x0FFFF)); ++#else ++ ra_classifier_hook_tx(skb, read_c0_count()); ++#endif ++ } ++#endif /* CONFIG_RA_CLASSIFIER */ ++ ++#if defined (CONFIG_RALINK_RT3052_MP2) ++ mcast_tx(skb); ++#endif ++ ++#if !defined (CONFIG_RALINK_RT6855) && !defined (CONFIG_RALINK_RT6855A) && \ ++ !defined(CONFIG_RALINK_MT7621) && !defined (CONFIG_ARCH_MT7623) ++ ++#define MIN_PKT_LEN 60 ++ if (skb->len < MIN_PKT_LEN) { ++ if (skb_padto(skb, MIN_PKT_LEN)) { ++ printk("raeth: skb_padto failed\n"); ++ return 0; ++ } ++ skb_put(skb, MIN_PKT_LEN - skb->len); ++ } ++#endif ++ ++ dev->trans_start = jiffies; /* save the timestamp */ ++ spin_lock_irqsave(&ei_local->page_lock, flags); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE); ++ ++#endif ++ ++#ifdef CONFIG_RALINK_VISTA_BASIC ++ veth = (struct vlan_ethhdr *)(skb->data); ++ if (is_switch_175c && veth->h_vlan_proto == __constant_htons(ETH_P_8021Q)) { ++ if ((veth->h_vlan_TCI & __constant_htons(VLAN_VID_MASK)) == 0) { ++ veth->h_vlan_TCI |= htons(VLAN_DEV_INFO(dev)->vlan_id); ++ } ++ } ++#endif ++ ++#if defined (CONFIG_RAETH_QOS) ++ if(pkt_classifier(skb, gmac_no, &ring_no, &queue_no, &port_no)) { ++ get_tx_ctx_idx(ring_no, &tx_cpu_owner_idx); ++ tx_cpu_owner_idx_next = (tx_cpu_owner_idx + 1) % NUM_TX_DESC; ++ if(((ei_local->skb_free[ring_no][tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[ring_no][tx_cpu_owner_idx_next]==0)){ ++ fe_qos_packet_send(dev, skb, ring_no, queue_no, port_no); ++ }else{ ++ ei_local->stat.tx_dropped++; ++ kfree_skb(skb); ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++ } ++ } ++#else ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ tx_cpu_owner_idx = tx_cpu_owner_idx0; ++#else ++ tx_cpu_owner_idx = sysRegRead(TX_CTX_IDX0); ++#endif ++#if defined (CONFIG_RAETH_TSO) ++// num_of_txd = (nr_frags==0) ? 1 : ((nr_frags>>1) + 1); ++// NumOfTxdUpdate(num_of_txd); ++ if(nr_frags != 0){ ++ for(i=0;ifrags[i]; ++ num_of_txd += cal_frag_txd_num(frag->size); ++ } ++ num_of_txd = (num_of_txd >> 1) + 1; ++ }else ++ num_of_txd = 1; ++ ++#else ++ num_of_txd = 1; ++#endif ++ tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % NUM_TX_DESC; ++ ++ if(((ei_local->skb_free[tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[tx_cpu_owner_idx_next]==0)){ ++ rt2880_eth_send(dev, skb, gmac_no); ++ ++ tx_cpu_owner_idx_next2 = (tx_cpu_owner_idx_next + 1) % NUM_TX_DESC; ++ ++ if(ei_local->skb_free[tx_cpu_owner_idx_next2]!=0){ ++#if defined (CONFIG_RAETH_SW_FC) ++ netif_stop_queue(dev); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ netif_stop_queue(ei_local->PseudoDev); ++#endif ++ tx_ring_full=1; ++#endif ++ } ++ }else { ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (gmac_no == 2) { ++ if (ei_local->PseudoDev != NULL) { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.tx_dropped++; ++ } ++ } else ++#endif ++ ei_local->stat.tx_dropped++; ++#if defined (CONFIG_RAETH_SW_FC) ++ printk("tx_ring_full, drop packet\n"); ++#endif ++ kfree_skb(skb); ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++ } ++ ++#if defined (CONFIG_RAETH_TSO) ++ /* SG: use multiple TXD to send the packet (only have one skb) */ ++ ei_local->skb_free[(tx_cpu_owner_idx + num_of_txd - 1) % NUM_TX_DESC] = skb; ++ while(--num_of_txd) { ++ ei_local->skb_free[(tx_cpu_owner_idx + num_of_txd -1) % NUM_TX_DESC] = (struct sk_buff *)0xFFFFFFFF; //MAGIC ID ++ } ++#else ++ ei_local->skb_free[tx_cpu_owner_idx] = skb; ++#endif ++#endif ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++} ++ ++void ei_xmit_housekeeping(unsigned long unused) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ struct PDMA_txdesc *tx_desc; ++ unsigned long skb_free_idx; ++ unsigned long tx_dtx_idx __maybe_unused; ++#ifndef CONFIG_RAETH_NAPI ++ unsigned long reg_int_mask=0; ++#endif ++ ++#ifdef CONFIG_RAETH_QOS ++ int i; ++ for (i=0;ifree_idx[i]; ++ if((ei_local->skb_free[i][skb_free_idx])==0){ ++ continue; ++ } ++ ++ get_tx_desc_and_dtx_idx(ei_local, i, &tx_dtx_idx, &tx_desc); ++ ++ while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[i][skb_free_idx])!=0 ){ ++ dev_kfree_skb_any((ei_local->skb_free[i][skb_free_idx])); ++ ++ ei_local->skb_free[i][skb_free_idx]=0; ++ skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC; ++ } ++ ei_local->free_idx[i] = skb_free_idx; ++ } ++#else ++ tx_dtx_idx = sysRegRead(TX_DTX_IDX0); ++ tx_desc = ei_local->tx_ring0; ++ skb_free_idx = ei_local->free_idx; ++ if ((ei_local->skb_free[skb_free_idx]) != 0 && tx_desc[skb_free_idx].txd_info2.DDONE_bit==1) { ++ while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[skb_free_idx])!=0 ){ ++#if defined (CONFIG_RAETH_TSO) ++ if(ei_local->skb_free[skb_free_idx]!=(struct sk_buff *)0xFFFFFFFF) { ++ dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]); ++ } ++#else ++ dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]); ++#endif ++ ei_local->skb_free[skb_free_idx]=0; ++ skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC; ++ } ++ ++ netif_wake_queue(dev); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ netif_wake_queue(ei_local->PseudoDev); ++#endif ++ tx_ring_full=0; ++ ei_local->free_idx = skb_free_idx; ++ } /* if skb_free != 0 */ ++#endif ++ ++#ifndef CONFIG_RAETH_NAPI ++ reg_int_mask=sysRegRead(FE_INT_ENABLE); ++#if defined (DELAY_INT) ++ sysRegWrite(FE_INT_ENABLE, reg_int_mask| TX_DLY_INT); ++#else ++ ++ sysRegWrite(FE_INT_ENABLE, reg_int_mask | TX_DONE_INT0 \ ++ | TX_DONE_INT1 \ ++ | TX_DONE_INT2 \ ++ | TX_DONE_INT3); ++#endif ++#endif //CONFIG_RAETH_NAPI// ++} ++ ++ ++ ++EXPORT_SYMBOL(ei_start_xmit); ++EXPORT_SYMBOL(ei_xmit_housekeeping); ++EXPORT_SYMBOL(fe_dma_init); ++EXPORT_SYMBOL(rt2880_eth_send); +diff --git a/drivers/net/ethernet/raeth/raether_qdma.c b/drivers/net/ethernet/raeth/raether_qdma.c +new file mode 100644 +index 0000000..acf8bfe +--- /dev/null ++++ b/drivers/net/ethernet/raeth/raether_qdma.c +@@ -0,0 +1,1407 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined (CONFIG_RAETH_TSO) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++#include ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++#include ++#endif ++#if defined (CONFIG_HW_SFQ) ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) ++#include ++#else ++#include ++#endif ++ ++#include "ra2882ethreg.h" ++#include "raether.h" ++#include "ra_mac.h" ++#include "ra_ioctl.h" ++#include "ra_rfrw.h" ++#ifdef CONFIG_RAETH_NETLINK ++#include "ra_netlink.h" ++#endif ++#if defined (CONFIG_RAETH_QOS) ++#include "ra_qos.h" ++#endif ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++#include "../../../net/nat/hw_nat/ra_nat.h" ++#endif ++ ++ ++#if !defined(CONFIG_RA_NAT_NONE) ++/* bruce+ ++ */ ++extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb); ++extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no); ++#endif ++ ++#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE) ++/* Qwert+ ++ */ ++#include ++extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle); ++extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle); ++#endif /* CONFIG_RA_CLASSIFIER */ ++ ++#if defined (CONFIG_RALINK_RT3052_MP2) ++int32_t mcast_rx(struct sk_buff * skb); ++int32_t mcast_tx(struct sk_buff * skb); ++#endif ++ ++#ifdef RA_MTD_RW_BY_NUM ++int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf); ++#else ++int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf); ++#endif ++ ++/* gmac driver feature set config */ ++#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS) ++#undef DELAY_INT ++#else ++#if defined (CONFIG_ARCH_MT7623) ++#undef DELAY_INT ++#else ++#define DELAY_INT 1 ++#endif ++#endif ++ ++//#define CONFIG_UNH_TEST ++/* end of config */ ++ ++#if defined (CONFIG_RAETH_JUMBOFRAME) ++#define MAX_RX_LENGTH 4096 ++#else ++#define MAX_RX_LENGTH 1536 ++#endif ++ ++extern struct net_device *dev_raether; ++ ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++static int rx_dma_owner_idx1; ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++static int rx_calc_idx1; ++#endif ++#endif ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++static int rx_calc_idx0; ++static unsigned long tx_cpu_owner_idx0=0; ++#endif ++extern unsigned long tx_ring_full; ++ ++#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER) ++#include "ra_ethtool.h" ++extern struct ethtool_ops ra_ethtool_ops; ++#ifdef CONFIG_PSEUDO_SUPPORT ++extern struct ethtool_ops ra_virt_ethtool_ops; ++#endif // CONFIG_PSEUDO_SUPPORT // ++#endif // (CONFIG_ETHTOOL // ++ ++#ifdef CONFIG_RALINK_VISTA_BASIC ++int is_switch_175c = 1; ++#endif ++ ++//skb->mark to queue mapping table ++extern unsigned int M2Q_table[64]; ++struct QDMA_txdesc *free_head = NULL; ++extern unsigned int lan_wan_separate; ++#if defined (CONFIG_HW_SFQ) ++extern unsigned int web_sfq_enable; ++#define HwSfqQUp 3 ++#define HwSfqQDl 1 ++#endif ++int dbg =0;//debug used ++#if defined (CONFIG_HW_SFQ) ++struct SFQ_table *sfq0; ++struct SFQ_table *sfq1; ++struct SFQ_table *sfq2; ++struct SFQ_table *sfq3; ++#endif ++ ++#define KSEG1 0xa0000000 ++#if defined (CONFIG_MIPS) ++#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1)) ++#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1) ++#else ++#define PHYS_TO_VIRT(x) phys_to_virt(x) ++#define VIRT_TO_PHYS(x) virt_to_phys(x) ++#endif ++ ++extern void set_fe_dma_glo_cfg(void); ++ ++#if defined (CONFIG_HW_SFQ) ++ParseResult SfqParseResult; ++#endif ++ ++/** ++ * ++ * @brief: get the TXD index from its address ++ * ++ * @param: cpu_ptr ++ * ++ * @return: TXD index ++*/ ++ ++static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ int ctx_offset; ++ //ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc); ++ //ctx_offset = (*cpu_ptr - ei_local->txd_pool); ++ ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->phy_txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc); ++ ++ return ctx_offset; ++} ++ ++ ++ ++ ++/** ++ * @brief cal txd number for a page ++ * ++ * @parm size ++ * ++ * @return frag_txd_num ++ */ ++ ++unsigned int cal_frag_txd_num(unsigned int size) ++{ ++ unsigned int frag_txd_num = 0; ++ if(size == 0) ++ return 0; ++ while(size > 0){ ++ if(size > MAX_TXD_LEN){ ++ frag_txd_num++; ++ size -= MAX_TXD_LEN; ++ }else{ ++ frag_txd_num++; ++ size = 0; ++ } ++ } ++ return frag_txd_num; ++ ++} ++ ++/** ++ * @brief get free TXD from TXD queue ++ * ++ * @param free_txd ++ * ++ * @return ++ */ ++static int get_free_txd(struct QDMA_txdesc **free_txd) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned int tmp_idx; ++ ++ if(ei_local->free_txd_num > 0){ ++ tmp_idx = ei_local->free_txd_head; ++ ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx]; ++ ei_local->free_txd_num -= 1; ++ //*free_txd = &ei_local->txd_pool[tmp_idx]; ++ *free_txd = ei_local->phy_txd_pool + (sizeof(struct QDMA_txdesc) * tmp_idx); ++ return tmp_idx; ++ }else ++ return NUM_TX_DESC; ++} ++ ++ ++/** ++ * @brief add free TXD into TXD queue ++ * ++ * @param free_txd ++ * ++ * @return ++ */ ++int put_free_txd(int free_txd_idx) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx; ++ ei_local->free_txd_tail = free_txd_idx; ++ ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC; ++ ei_local->free_txd_num += 1; ++ return 1; ++} ++ ++/*define qdma initial alloc*/ ++/** ++ * @brief ++ * ++ * @param net_dev ++ * ++ * @return 0: fail ++ * 1: success ++ */ ++bool qdma_tx_desc_alloc(void) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ struct QDMA_txdesc *free_txd = NULL; ++ unsigned int txd_idx; ++ int i = 0; ++ ++ ++ ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool); ++ printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool); ++ ++ if (ei_local->txd_pool == NULL) { ++ printk("adapter->txd_pool allocation failed!\n"); ++ return 0; ++ } ++ printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free); ++ //set all txd_pool_info to 0. ++ for ( i = 0; i < NUM_TX_DESC; i++) ++ { ++ ei_local->skb_free[i]= 0; ++ ei_local->txd_pool_info[i] = i + 1; ++ ei_local->txd_pool[i].txd_info3.LS_bit = 1; ++ ei_local->txd_pool[i].txd_info3.OWN_bit = 1; ++ } ++ ++ ei_local->free_txd_head = 0; ++ ei_local->free_txd_tail = NUM_TX_DESC - 1; ++ ei_local->free_txd_num = NUM_TX_DESC; ++ ++ ++ //get free txd from txd pool ++ txd_idx = get_free_txd(&free_txd); ++ if( txd_idx == NUM_TX_DESC) { ++ printk("get_free_txd fail\n"); ++ return 0; ++ } ++ ++ //add null TXD for transmit ++ //ei_local->tx_dma_ptr = VIRT_TO_PHYS(free_txd); ++ //ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd); ++ ei_local->tx_dma_ptr = free_txd; ++ ei_local->tx_cpu_ptr = free_txd; ++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr); ++ sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr); ++ ++ //get free txd from txd pool ++ ++ txd_idx = get_free_txd(&free_txd); ++ if( txd_idx == NUM_TX_DESC) { ++ printk("get_free_txd fail\n"); ++ return 0; ++ } ++ // add null TXD for release ++ //sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(free_txd)); ++ //sysRegWrite(QTX_DRX_PTR, VIRT_TO_PHYS(free_txd)); ++ sysRegWrite(QTX_CRX_PTR, free_txd); ++ sysRegWrite(QTX_DRX_PTR, free_txd); ++ printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr); ++ ++ printk(" POOL HEAD_PTR | DMA_PTR | CPU_PTR \n"); ++ printk("----------------+---------+--------\n"); ++ printk(" 0x%p 0x%08X 0x%08X\n",ei_local->txd_pool, ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr); ++ return 1; ++} ++#if defined (CONFIG_HW_SFQ) ++bool sfq_init(void) ++{ ++ unsigned int regVal; ++ ++ unsigned int sfq_phy0; ++ unsigned int sfq_phy1; ++ unsigned int sfq_phy2; ++ unsigned int sfq_phy3; ++ struct SFQ_table *sfq0; ++ struct SFQ_table *sfq1; ++ struct SFQ_table *sfq2; ++ struct SFQ_table *sfq3; ++ int i = 0; ++ regVal = sysRegRead(VQTX_GLO); ++ regVal = regVal | VQTX_MIB_EN |(1<<16) ; ++ sysRegWrite(VQTX_GLO, regVal);// Virtual table extends to 32bytes ++ regVal = sysRegRead(VQTX_GLO); ++ sysRegWrite(VQTX_NUM, (VQTX_NUM_0) | (VQTX_NUM_1) | (VQTX_NUM_2) | (VQTX_NUM_3)); ++ sysRegWrite(VQTX_HASH_CFG, 0xF002710); //10 s change hash algorithm ++ sysRegWrite(VQTX_VLD_CFG, 0x00); ++ sysRegWrite(VQTX_HASH_SD, 0x0D); ++ sysRegWrite(QDMA_FC_THRES, 0x9b9b4444); ++ sysRegWrite(QDMA_HRED1, 0); ++ sysRegWrite(QDMA_HRED2, 0); ++ sysRegWrite(QDMA_SRED1, 0); ++ sysRegWrite(QDMA_SRED2, 0); ++ sfq0 = pci_alloc_consistent(NULL, 256*sizeof(struct SFQ_table), &sfq_phy0); ++ memset(sfq0, 0x0, 256*sizeof(struct SFQ_table) ); ++ for (i=0; i < 256; i++) { ++ sfq0[i].sfq_info1.VQHPTR = 0xdeadbeef; ++ sfq0[i].sfq_info2.VQTPTR = 0xdeadbeef; ++ } ++#if(1) ++ sfq1 = pci_alloc_consistent(NULL, 256*sizeof(struct SFQ_table), &sfq_phy1); ++ ++ memset(sfq1, 0x0, 256*sizeof(struct SFQ_table) ); ++ for (i=0; i < 256; i++) { ++ sfq1[i].sfq_info1.VQHPTR = 0xdeadbeef; ++ sfq1[i].sfq_info2.VQTPTR = 0xdeadbeef; ++ } ++ ++ sfq2 = pci_alloc_consistent(NULL, 256*sizeof(struct SFQ_table), &sfq_phy2); ++ memset(sfq2, 0x0, 256*sizeof(struct SFQ_table) ); ++ for (i=0; i < 256; i++) { ++ sfq2[i].sfq_info1.VQHPTR = 0xdeadbeef; ++ sfq2[i].sfq_info2.VQTPTR = 0xdeadbeef; ++ } ++ ++ sfq3 = pci_alloc_consistent(NULL, 256*sizeof(struct SFQ_table), &sfq_phy3); ++ memset(sfq3, 0x0, 256*sizeof(struct SFQ_table) ); ++ for (i=0; i < 256; i++) { ++ sfq3[i].sfq_info1.VQHPTR = 0xdeadbeef; ++ sfq3[i].sfq_info2.VQTPTR = 0xdeadbeef; ++ } ++ ++#endif ++ printk("*****sfq_phy0 is 0x%x!!!*******\n", sfq_phy0); ++ printk("*****sfq_phy1 is 0x%x!!!*******\n", sfq_phy1); ++ printk("*****sfq_phy2 is 0x%x!!!*******\n", sfq_phy2); ++ printk("*****sfq_phy3 is 0x%x!!!*******\n", sfq_phy3); ++ printk("*****sfq_virt0 is 0x%x!!!*******\n", sfq0); ++ printk("*****sfq_virt1 is 0x%x!!!*******\n", sfq1); ++ printk("*****sfq_virt2 is 0x%x!!!*******\n", sfq2); ++ printk("*****sfq_virt3 is 0x%x!!!*******\n", sfq3); ++ printk("*****sfq_virt0 is 0x%x!!!*******\n", sfq0); ++ sysRegWrite(VQTX_TB_BASE0, (u32)sfq_phy0); ++ sysRegWrite(VQTX_TB_BASE1, (u32)sfq_phy1); ++ sysRegWrite(VQTX_TB_BASE2, (u32)sfq_phy2); ++ sysRegWrite(VQTX_TB_BASE3, (u32)sfq_phy3); ++ ++ return 1; ++} ++#endif ++bool fq_qdma_init(struct net_device *dev) ++{ ++ END_DEVICE* ei_local = netdev_priv(dev); ++ //struct QDMA_txdesc *free_head = NULL; ++ unsigned int phy_free_head; ++ unsigned int phy_free_tail; ++ unsigned int *free_page_head = NULL; ++ unsigned int phy_free_page_head; ++ int i; ++ ++ free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &phy_free_head); ++ if (unlikely(free_head == NULL)){ ++ printk(KERN_ERR "QDMA FQ decriptor not available...\n"); ++ return 0; ++ } ++ memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE); ++ ++ free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &phy_free_page_head); ++ if (unlikely(free_page_head == NULL)){ ++ printk(KERN_ERR "QDMA FQ page not available...\n"); ++ return 0; ++ } ++ for (i=0; i < NUM_QDMA_PAGE; i++) { ++ free_head[i].txd_info1.SDP = (phy_free_page_head + (i * QDMA_PAGE_SIZE)); ++ if(i < (NUM_QDMA_PAGE-1)){ ++ free_head[i].txd_info2.NDP = (phy_free_head + ((i+1) * sizeof(struct QDMA_txdesc))); ++ ++ ++#if 0 ++ printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) ); ++ printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] ); ++ printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP ); ++ printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP ); ++#endif ++ } ++ free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE; ++ ++ } ++ phy_free_tail = (phy_free_head + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc))); ++ ++ printk("phy_free_head is 0x%x!!!\n", phy_free_head); ++ printk("phy_free_tail_phy is 0x%x!!!\n", phy_free_tail); ++ sysRegWrite(QDMA_FQ_HEAD, (u32)phy_free_head); ++ sysRegWrite(QDMA_FQ_TAIL, (u32)phy_free_tail); ++ sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE)); ++ sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16); ++ ++ ei_local->free_head = free_head; ++ ei_local->phy_free_head = phy_free_head; ++ ei_local->free_page_head = free_page_head; ++ ei_local->phy_free_page_head = phy_free_page_head; ++ return 1; ++} ++ ++int fe_dma_init(struct net_device *dev) ++{ ++ ++ int i; ++ unsigned int regVal; ++ END_DEVICE* ei_local = netdev_priv(dev); ++ ++ ++ #if defined (CONFIG_HW_SFQ) ++ sfq_init(); ++ #endif ++ fq_qdma_init(dev); ++ ++ while(1) ++ { ++ regVal = sysRegRead(QDMA_GLO_CFG); ++ if((regVal & RX_DMA_BUSY)) ++ { ++ printk("\n RX_DMA_BUSY !!! "); ++ continue; ++ } ++ if((regVal & TX_DMA_BUSY)) ++ { ++ printk("\n TX_DMA_BUSY !!! "); ++ continue; ++ } ++ break; ++ } ++ /*tx desc alloc, add a NULL TXD to HW*/ ++ ++ qdma_tx_desc_alloc(); ++ ++ /* Initial RX Ring 0*/ ++ ++#ifdef CONFIG_32B_DESC ++ ei_local->qrx_ring = kmalloc(NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL); ++ ei_local->phy_qrx_ring = virt_to_phys(ei_local->qrx_ring); ++#else ++ ei_local->qrx_ring = pci_alloc_consistent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_qrx_ring); ++#endif ++ for (i = 0; i < NUM_QRX_DESC; i++) { ++ memset(&ei_local->qrx_ring[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->qrx_ring[i].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ ei_local->qrx_ring[i].rxd_info2.LS0 = 0; ++ ei_local->qrx_ring[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++#else ++ ei_local->qrx_ring[i].rxd_info2.LS0 = 1; ++#endif ++ ei_local->qrx_ring[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("\nphy_qrx_ring = 0x%08x, qrx_ring = 0x%p\n",ei_local->phy_qrx_ring,ei_local->qrx_ring); ++ ++ regVal = sysRegRead(QDMA_GLO_CFG); ++ regVal &= 0x000000FF; ++ ++ sysRegWrite(QDMA_GLO_CFG, regVal); ++ regVal=sysRegRead(QDMA_GLO_CFG); ++ ++ /* Tell the adapter where the TX/RX rings are located. */ ++ ++ sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_qrx_ring)); ++ sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_QRX_DESC)); ++ sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_QRX_DESC - 1))); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = rx_dma_owner_idx0 = sysRegRead(QRX_CRX_IDX_0); ++#endif ++ sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0); ++ ++ ei_local->rx_ring0 = ei_local->qrx_ring; ++#if !defined (CONFIG_RAETH_QDMATX_QDMARX) ++ /* Initial PDMA RX Ring 0*/ ++#ifdef CONFIG_32B_DESC ++ ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL); ++ ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0); ++#else ++ ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0); ++#endif ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++#else ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 1; ++#endif ++ ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0); ++ ++ regVal = sysRegRead(PDMA_GLO_CFG); ++ regVal &= 0x000000FF; ++ sysRegWrite(PDMA_GLO_CFG, regVal); ++ regVal=sysRegRead(PDMA_GLO_CFG); ++ ++ sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0)); ++ sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1))); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = sysRegRead(RX_CALC_IDX0); ++#endif ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0); ++#endif ++#if !defined (CONFIG_HW_SFQ) ++ /* Enable randon early drop and set drop threshold automatically */ ++ sysRegWrite(QDMA_FC_THRES, 0x174444); ++#endif ++ sysRegWrite(QDMA_HRED2, 0x0); ++ set_fe_dma_glo_cfg(); ++#if defined (CONFIG_ARCH_MT7623) ++ printk("Enable QDMA TX NDP coherence check and re-read mechanism\n"); ++ regVal=sysRegRead(QDMA_GLO_CFG); ++ regVal = regVal | 0x400; ++ sysRegWrite(QDMA_GLO_CFG, regVal); ++ printk("***********QDMA_GLO_CFG=%x\n", sysRegRead(QDMA_GLO_CFG)); ++#endif ++ ++ return 1; ++} ++ ++#if defined (CONFIG_HW_SFQ) ++ ++int sfq_prot = 0; ++int proto_id=0; ++int udp_source_port=0; ++int tcp_source_port=0; ++int ack_packt =0; ++int SfqParseLayerInfo(struct sk_buff * skb) ++{ ++ ++ struct vlan_hdr *vh_sfq = NULL; ++ struct ethhdr *eth_sfq = NULL; ++ struct iphdr *iph_sfq = NULL; ++ struct ipv6hdr *ip6h_sfq = NULL; ++ struct tcphdr *th_sfq = NULL; ++ struct udphdr *uh_sfq = NULL; ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++ struct vlan_hdr pseudo_vhdr_sfq; ++#endif ++ ++ memset(&SfqParseResult, 0, sizeof(SfqParseResult)); ++ ++ eth_sfq = (struct ethhdr *)skb->data; ++ memcpy(SfqParseResult.dmac, eth_sfq->h_dest, ETH_ALEN); ++ memcpy(SfqParseResult.smac, eth_sfq->h_source, ETH_ALEN); ++ SfqParseResult.eth_type = eth_sfq->h_proto; ++ ++ ++ if (SfqParseResult.eth_type == htons(ETH_P_8021Q)){ ++ SfqParseResult.vlan1_gap = VLAN_HLEN; ++ vh_sfq = (struct vlan_hdr *)(skb->data + ETH_HLEN); ++ SfqParseResult.eth_type = vh_sfq->h_vlan_encapsulated_proto; ++ }else{ ++ SfqParseResult.vlan1_gap = 0; ++ } ++ ++ ++ ++ LAYER2_HEADER(skb) = skb->data; ++ LAYER3_HEADER(skb) = (skb->data + ETH_HLEN + (SfqParseResult.vlan1_gap)); ++ ++ ++ ++ /* set layer4 start addr */ ++ if ((SfqParseResult.eth_type == htons(ETH_P_IP)) || (SfqParseResult.eth_type == htons(ETH_P_PPP_SES) ++ && SfqParseResult.ppp_tag == htons(PPP_IP))) { ++ iph_sfq = (struct iphdr *)LAYER3_HEADER(skb); ++ ++ //prepare layer3/layer4 info ++ memcpy(&SfqParseResult.iph, iph_sfq, sizeof(struct iphdr)); ++ if (iph_sfq->protocol == IPPROTO_TCP) { ++ ++ LAYER4_HEADER(skb) = ((uint8_t *) iph_sfq + (iph_sfq->ihl * 4)); ++ th_sfq = (struct tcphdr *)LAYER4_HEADER(skb); ++ memcpy(&SfqParseResult.th, th_sfq, sizeof(struct tcphdr)); ++ SfqParseResult.pkt_type = IPV4_HNAPT; ++ //printk("tcp parsing\n"); ++ tcp_source_port = ntohs(SfqParseResult.th.source); ++ udp_source_port = 0; ++ #if(0) //for TCP ack, test use ++ if(ntohl(SfqParseResult.iph.saddr) == 0xa0a0a04){ // tcp ack packet ++ ack_packt = 1; ++ }else { ++ ack_packt = 0; ++ } ++ #endif ++ sfq_prot = 2;//IPV4_HNAPT ++ proto_id = 1;//TCP ++ if(iph_sfq->frag_off & htons(IP_MF|IP_OFFSET)) { ++ //return 1; ++ } ++ } else if (iph_sfq->protocol == IPPROTO_UDP) { ++ LAYER4_HEADER(skb) = ((uint8_t *) iph_sfq + iph_sfq->ihl * 4); ++ uh_sfq = (struct udphdr *)LAYER4_HEADER(skb); ++ memcpy(&SfqParseResult.uh, uh_sfq, sizeof(struct udphdr)); ++ SfqParseResult.pkt_type = IPV4_HNAPT; ++ udp_source_port = ntohs(SfqParseResult.uh.source); ++ tcp_source_port = 0; ++ ack_packt = 0; ++ sfq_prot = 2;//IPV4_HNAPT ++ proto_id =2;//UDP ++ if(iph_sfq->frag_off & htons(IP_MF|IP_OFFSET)) { ++ return 1; ++ } ++ }else{ ++ sfq_prot = 1; ++ } ++ }else if (SfqParseResult.eth_type == htons(ETH_P_IPV6) || ++ (SfqParseResult.eth_type == htons(ETH_P_PPP_SES) && ++ SfqParseResult.ppp_tag == htons(PPP_IPV6))) { ++ ip6h_sfq = (struct ipv6hdr *)LAYER3_HEADER(skb); ++ memcpy(&SfqParseResult.ip6h, ip6h_sfq, sizeof(struct ipv6hdr)); ++ ++ if (ip6h_sfq->nexthdr == NEXTHDR_TCP) { ++ LAYER4_HEADER(skb) = ((uint8_t *) ip6h_sfq + sizeof(struct ipv6hdr)); ++ th_sfq = (struct tcphdr *)LAYER4_HEADER(skb); ++ memcpy(&SfqParseResult.th, th_sfq, sizeof(struct tcphdr)); ++ SfqParseResult.pkt_type = IPV6_5T_ROUTE; ++ sfq_prot = 4;//IPV6_5T ++ #if(0) //for TCP ack, test use ++ if(ntohl(SfqParseResult.ip6h.saddr.s6_addr32[3]) == 8){ ++ ack_packt = 1; ++ }else { ++ ack_packt = 0; ++ } ++ #endif ++ } else if (ip6h_sfq->nexthdr == NEXTHDR_UDP) { ++ LAYER4_HEADER(skb) = ((uint8_t *) ip6h_sfq + sizeof(struct ipv6hdr)); ++ uh_sfq = (struct udphdr *)LAYER4_HEADER(skb); ++ memcpy(&SfqParseResult.uh, uh_sfq, sizeof(struct udphdr)); ++ SfqParseResult.pkt_type = IPV6_5T_ROUTE; ++ ack_packt = 0; ++ sfq_prot = 4;//IPV6_5T ++ ++ }else{ ++ sfq_prot = 3;//IPV6_3T ++ } ++ } ++ ++ return 0; ++} ++#endif ++ ++inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no) ++{ ++ unsigned int length=skb->len; ++ END_DEVICE* ei_local = netdev_priv(dev); ++ ++ struct QDMA_txdesc *cpu_ptr; ++ ++ struct QDMA_txdesc *dma_ptr __maybe_unused; ++ struct QDMA_txdesc *free_txd; ++ int ctx_offset; ++#if defined (CONFIG_RAETH_TSO) ++ struct iphdr *iph = NULL; ++ struct QDMA_txdesc *init_cpu_ptr; ++ struct tcphdr *th = NULL; ++ struct skb_frag_struct *frag; ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags; ++ unsigned int len, size, offset, frag_txd_num; ++ int init_txd_idx, i; ++#endif // CONFIG_RAETH_TSO // ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ struct ipv6hdr *ip6h = NULL; ++#endif ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ PSEUDO_ADAPTER *pAd; ++#endif ++ //cpu_ptr = PHYS_TO_VIRT(ei_local->tx_cpu_ptr); ++ //dma_ptr = PHYS_TO_VIRT(ei_local->tx_dma_ptr); ++ //ctx_offset = GET_TXD_OFFSET(&cpu_ptr); ++ cpu_ptr = (ei_local->tx_cpu_ptr); ++ ctx_offset = GET_TXD_OFFSET(&cpu_ptr); ++ cpu_ptr = phys_to_virt(ei_local->tx_cpu_ptr); ++ dma_ptr = phys_to_virt(ei_local->tx_dma_ptr); ++ cpu_ptr = (ei_local->txd_pool + (ctx_offset)); ++ ei_local->skb_free[ctx_offset] = skb; ++#if defined (CONFIG_RAETH_TSO) ++ init_cpu_ptr = cpu_ptr; ++ init_txd_idx = ctx_offset; ++#endif ++ ++#if !defined (CONFIG_RAETH_TSO) ++ ++ //2. prepare data ++ //cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data); ++ cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data); ++ cpu_ptr->txd_info3.SDL = skb->len; ++#if defined (CONFIG_HW_SFQ) ++ SfqParseLayerInfo(skb); ++ cpu_ptr->txd_info4.VQID0 = 1;//1:HW hash 0:CPU ++ ++ ++#if(0)// for tcp ack use, test use ++ if (ack_packt==1){ ++ cpu_ptr->txd_info3.QID = 0x0a; ++ //cpu_ptr->txd_info3.VQID = 0; ++ }else{ ++ cpu_ptr->txd_info3.QID = 0; ++ } ++#endif ++ cpu_ptr->txd_info3.PROT = sfq_prot; ++ cpu_ptr->txd_info3.IPOFST = 14 + (SfqParseResult.vlan1_gap); //no vlan ++ ++#endif ++ if (gmac_no == 1) { ++ cpu_ptr->txd_info4.FPORT = 1; ++ }else { ++ cpu_ptr->txd_info4.FPORT = 2; ++ } ++ ++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark]; ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if((lan_wan_separate==1) && (gmac_no==2)){ ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ } ++#if defined (CONFIG_HW_SFQ) ++ if((lan_wan_separate==1) && (gmac_no==1)){ ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++ } ++#endif ++#endif //end CONFIG_PSEUDO_SUPPORT ++ ++ if(dbg==1){ ++ printk("M2Q_table[%d]=%d\n", skb->mark, M2Q_table[skb->mark]); ++ printk("cpu_ptr->txd_info3.QID = %d\n", cpu_ptr->txd_info3.QID); ++ } ++#if 0 ++ iph = (struct iphdr *)skb_network_header(skb); ++ if (iph->tos == 0xe0) ++ cpu_ptr->txd_info3.QID = 3; ++ else if (iph->tos == 0xa0) ++ cpu_ptr->txd_info3.QID = 2; ++ else if (iph->tos == 0x20) ++ cpu_ptr->txd_info3.QID = 1; ++ else ++ cpu_ptr->txd_info3.QID = 0; ++#endif ++ ++#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628) ++ if (skb->ip_summed == CHECKSUM_PARTIAL){ ++ cpu_ptr->txd_info4.TUI_CO = 7; ++ }else { ++ cpu_ptr->txd_info4.TUI_CO = 0; ++ } ++#endif ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++ if(vlan_tx_tag_present(skb)) { ++ cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb); ++ }else { ++ cpu_ptr->txd_info4.VLAN_TAG = 0; ++ } ++#endif ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX // QoS Web UI used ++ ++ if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==2)){ ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ } ++#if defined (CONFIG_HW_SFQ) ++ if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==1)){ ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++ } ++#endif ++#endif // CONFIG_RAETH_HW_VLAN_TX ++ ++ ++//no hw van, no GE2, web UI used ++#ifndef CONFIG_PSEUDO_SUPPORT ++#ifndef CONFIG_RAETH_HW_VLAN_TX ++ if(lan_wan_separate==1){ ++ struct vlan_hdr *vh = NULL; ++ unsigned short vlanid = 0; ++ unsigned short vlan_TCI; ++ vh = (struct vlan_hdr *)(skb->data + ETH_HLEN); ++ vlan_TCI = vh->h_vlan_TCI; ++ vlanid = (vlan_TCI & VLAN_VID_MASK)>>8; ++ if(vlanid == 2)//to wan ++ { ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ }else if(vlanid == 1){ //to lan ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++#endif ++ } ++ } ++#endif ++#endif ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if(ra_sw_nat_hook_rx!= NULL){ ++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */ ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++#if 0 ++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */ ++ cpu_ptr->txd_info4.UDF = 0x2F; ++#endif ++ ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE); ++#endif ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ ++ //3. get NULL TXD and decrease free_tx_num by 1. ++ ctx_offset = get_free_txd(&free_txd); ++ if(ctx_offset == NUM_TX_DESC) { ++ printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least. ++ return 0; ++ } ++ ++ //4. hook new TXD in the end of queue ++ //cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd); ++ cpu_ptr->txd_info2.NDP = (free_txd); ++ ++ ++ //5. move CPU_PTR to new TXD ++ //ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd); ++ ei_local->tx_cpu_ptr = (free_txd); ++ cpu_ptr->txd_info3.OWN_bit = 0; ++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr); ++ ++#if 0 ++ printk("----------------------------------------------\n"); ++ printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1); ++ printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2); ++ printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3); ++ printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4); ++#endif ++ ++#else //#if !defined (CONFIG_RAETH_TSO) ++ cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data); ++ cpu_ptr->txd_info3.SDL = (length - skb->data_len); ++ cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1; ++#if defined (CONFIG_HW_SFQ) ++ SfqParseLayerInfo(skb); ++ // printk("tcp_source_port=%d\n", tcp_source_port); ++#if(0) ++ cpu_ptr->txd_info4.VQID0 = 0;//1:HW hash 0:CPU ++ if (tcp_source_port==1000) cpu_ptr->txd_info3.VQID = 0; ++ else if (tcp_source_port==1100) cpu_ptr->txd_info3.VQID = 1; ++ else if (tcp_source_port==1200) cpu_ptr->txd_info3.VQID = 2; ++ else cpu_ptr->txd_info3.VQID = 0; ++ #else ++ cpu_ptr->txd_info4.VQID0 = 1; ++ cpu_ptr->txd_info3.PROT = sfq_prot; ++ cpu_ptr->txd_info3.IPOFST = 14 + (SfqParseResult.vlan1_gap); //no vlan ++#endif ++#endif ++ if (gmac_no == 1) { ++ cpu_ptr->txd_info4.FPORT = 1; ++ }else { ++ cpu_ptr->txd_info4.FPORT = 2; ++ } ++ ++ cpu_ptr->txd_info4.TSO = 0; ++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark]; ++#ifdef CONFIG_PSEUDO_SUPPORT //web UI used tso ++ if((lan_wan_separate==1) && (gmac_no==2)){ ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable == 1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ } ++#if defined (CONFIG_HW_SFQ) ++ if((lan_wan_separate==1) && (gmac_no==1)){ ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++ } ++#endif ++#endif //CONFIG_PSEUDO_SUPPORT ++ if(dbg==1){ ++ printk("M2Q_table[%d]=%d\n", skb->mark, M2Q_table[skb->mark]); ++ printk("cpu_ptr->txd_info3.QID = %d\n", cpu_ptr->txd_info3.QID); ++ } ++#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628) ++ if (skb->ip_summed == CHECKSUM_PARTIAL){ ++ cpu_ptr->txd_info4.TUI_CO = 7; ++ }else { ++ cpu_ptr->txd_info4.TUI_CO = 0; ++ } ++#endif ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++ if(vlan_tx_tag_present(skb)) { ++ cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb); ++ }else { ++ cpu_ptr->txd_info4.VLAN_TAG = 0; ++ } ++#endif ++#ifdef CONFIG_RAETH_HW_VLAN_TX // QoS Web UI used tso ++ ++ if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==2)){ ++ //cpu_ptr->txd_info3.QID += 8; ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ } ++#if defined (CONFIG_HW_SFQ) ++ if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==1)){ ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++ } ++#endif ++#endif // CONFIG_RAETH_HW_VLAN_TX ++ ++ ++//no hw van, no GE2, web UI used ++#ifndef CONFIG_PSEUDO_SUPPORT ++#ifndef CONFIG_RAETH_HW_VLAN_TX ++ if(lan_wan_separate==1){ ++ struct vlan_hdr *vh = NULL; ++ unsigned short vlanid = 0; ++ unsigned short vlan_TCI; ++ vh = (struct vlan_hdr *)(skb->data + ETH_HLEN); ++ vlan_TCI = vh->h_vlan_TCI; ++ vlanid = (vlan_TCI & VLAN_VID_MASK)>>8; ++ if(vlanid == 2)//eth2.2 to wan ++ { ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ }else if(!strcmp(netdev, "eth2.1")){ // eth2.1 to lan ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++#endif ++ } ++} ++#endif ++#endif ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if(ra_sw_nat_hook_rx!= NULL){ ++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */ ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++ ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ ++ ctx_offset = get_free_txd(&free_txd); ++ if(ctx_offset == NUM_TX_DESC) { ++ printk("get_free_txd fail\n"); ++ return 0; ++ } ++ //cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd); ++ //ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd); ++ cpu_ptr->txd_info2.NDP = free_txd; ++ ei_local->tx_cpu_ptr = free_txd; ++ ++ ++ if(nr_frags > 0) { ++ for(i=0;ifrags[i]; ++ len = frag->size; ++ frag_txd_num = cal_frag_txd_num(len); // calculate the needed TXD numbers for this fragment ++ for(frag_txd_num = frag_txd_num;frag_txd_num > 0; frag_txd_num --){ ++ // 2. size will be assigned to SDL and can't be larger than MAX_TXD_LEN ++ if(len < MAX_TXD_LEN) ++ size = len; ++ else ++ size = MAX_TXD_LEN; ++ ++ //3. Update TXD info ++ cpu_ptr = (ei_local->txd_pool + (ctx_offset)); ++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark]; ++#ifdef CONFIG_PSEUDO_SUPPORT //QoS Web UI used , nr_frags ++ if((lan_wan_separate==1) && (gmac_no==2)){ ++ //cpu_ptr->txd_info3.QID += 8; ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ } ++#if defined (CONFIG_HW_SFQ) ++ if((lan_wan_separate==1) && (gmac_no==1)){ ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++ } ++#endif ++#endif //CONFIG_PSEUDO_SUPPORT ++ ++//QoS web used, nr_frags ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++ if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==2)){ ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ } ++#if defined (CONFIG_HW_SFQ) ++ if((lan_wan_separate==1) && (vlan_tx_tag_get(skb)==1)){ ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++ } ++#endif ++#endif // CONFIG_RAETH_HW_VLAN_TX ++//no hw van, no GE2, web UI used ++#ifndef CONFIG_PSEUDO_SUPPORT ++#ifndef CONFIG_RAETH_HW_VLAN_TX ++ if(lan_wan_separate==1){ ++ struct vlan_hdr *vh = NULL; ++ unsigned short vlanid = 0; ++ unsigned short vlan_TCI; ++ vh = (struct vlan_hdr *)(skb->data + ETH_HLEN); ++ vlan_TCI = vh->h_vlan_TCI; ++ vlanid = (vlan_TCI & VLAN_VID_MASK)>>8; ++ if(vlanid == 2))//eth2.2 to wan ++ { ++ cpu_ptr->txd_info3.QID += 8; ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQUp; ++ } ++#endif ++ } ++ }else if(vlanid == 1){ // eth2.1 to lan ++#if defined (CONFIG_HW_SFQ) ++ if(web_sfq_enable==1 &&(skb->mark == 2)){ ++ cpu_ptr->txd_info3.QID = HwSfqQDl; ++ } ++#endif ++ } ++ } ++#endif ++#endif ++ if(dbg==1){ ++ printk("M2Q_table[%d]=%d\n", skb->mark, M2Q_table[skb->mark]); ++ printk("cpu_ptr->txd_info3.QID = %d\n", cpu_ptr->txd_info3.QID); ++ } ++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) ++ cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE); ++#else ++ cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page.p, frag->page_offset + offset, size, PCI_DMA_TODEVICE); ++// printk(" frag->page = %08x. frag->page_offset = %08x. frag->size = % 08x.\n", frag->page, (frag->page_offset+offset), size); ++#endif ++ cpu_ptr->txd_info3.SDL = size; ++ if( (i==(nr_frags-1)) && (frag_txd_num == 1)) ++ cpu_ptr->txd_info3.LS_bit = 1; ++ else ++ cpu_ptr->txd_info3.LS_bit = 0; ++ cpu_ptr->txd_info3.OWN_bit = 0; ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ //4. Update skb_free for housekeeping ++ ei_local->skb_free[ctx_offset] = (cpu_ptr->txd_info3.LS_bit == 1)?skb:(struct sk_buff *)0xFFFFFFFF; //MAGIC ID ++ ++ //5. Get next TXD ++ ctx_offset = get_free_txd(&free_txd); ++ //cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd); ++ //ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd); ++ cpu_ptr->txd_info2.NDP = free_txd; ++ ei_local->tx_cpu_ptr = free_txd; ++ //6. Update offset and len. ++ offset += size; ++ len -= size; ++ } ++ } ++ ei_local->skb_free[init_txd_idx]= (struct sk_buff *)0xFFFFFFFF; //MAGIC ID ++ } ++ ++ if(skb_shinfo(skb)->gso_segs > 1) { ++ ++// TsoLenUpdate(skb->len); ++ ++ /* TCP over IPv4 */ ++ iph = (struct iphdr *)skb_network_header(skb); ++#if defined (CONFIG_RAETH_TSOV6) ++ /* TCP over IPv6 */ ++ ip6h = (struct ipv6hdr *)skb_network_header(skb); ++#endif ++ if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++#if defined (CONFIG_HW_SFQ) ++#if(0) ++ init_cpu_ptr->txd_info4.VQID0 = 0;//1:HW hash 0:CPU ++ if (tcp_source_port==1000) init_cpu_ptr->txd_info3.VQID = 0; ++ else if (tcp_source_port==1100) init_cpu_ptr->txd_info3.VQID = 1; ++ else if (tcp_source_port==1200) init_cpu_ptr->txd_info3.VQID = 2; ++ else cpu_ptr->txd_info3.VQID = 0; ++ #else ++ init_cpu_ptr->txd_info4.VQID0 = 1; ++ init_cpu_ptr->txd_info3.PROT = sfq_prot; ++ init_cpu_ptr->txd_info3.IPOFST = 14 + (SfqParseResult.vlan1_gap); //no vlan ++#endif ++#endif ++ init_cpu_ptr->txd_info4.TSO = 1; ++ ++ th->check = htons(skb_shinfo(skb)->gso_size); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++#endif ++ } ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ /* TCP over IPv6 */ ++ //ip6h = (struct ipv6hdr *)skb_network_header(skb); ++ else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ init_cpu_ptr->txd_info4.TSO = 1; ++#else ++ init_cpu_ptr->txd_info4.TSO = 1; ++#endif ++ th->check = htons(skb_shinfo(skb)->gso_size); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++#endif ++ } ++#endif ++ } ++ ++ ++// dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++ ++ init_cpu_ptr->txd_info3.OWN_bit = 0; ++#endif // CONFIG_RAETH_TSO // ++ ++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr); ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (gmac_no == 2) { ++ if (ei_local->PseudoDev != NULL) { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.tx_packets++; ++ pAd->stat.tx_bytes += length; ++ } ++ } else ++ ++#endif ++ { ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += skb->len; ++ } ++#ifdef CONFIG_RAETH_NAPI ++ if ( ei_local->tx_full == 1) { ++ ei_local->tx_full = 0; ++ netif_wake_queue(dev); ++ } ++#endif ++ ++ return length; ++} ++ ++int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned long flags; ++ unsigned int num_of_txd = 0; ++#if defined (CONFIG_RAETH_TSO) ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i; ++ struct skb_frag_struct *frag; ++#endif ++#ifdef CONFIG_PSEUDO_SUPPORT ++ PSEUDO_ADAPTER *pAd; ++#endif ++ ++#if !defined(CONFIG_RA_NAT_NONE) ++ if(ra_sw_nat_hook_tx!= NULL) ++ { ++// spin_lock_irqsave(&ei_local->page_lock, flags); ++ if(ra_sw_nat_hook_tx(skb, gmac_no)==1){ ++// spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ }else{ ++ kfree_skb(skb); ++// spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++ } ++ } ++#endif ++ ++ ++ ++ dev->trans_start = jiffies; /* save the timestamp */ ++ spin_lock_irqsave(&ei_local->page_lock, flags); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE); ++#endif ++ ++ ++//check free_txd_num before calling rt288_eth_send() ++ ++#if defined (CONFIG_RAETH_TSO) ++ // num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1); ++ if(nr_frags != 0){ ++ for(i=0;ifrags[i]; ++ num_of_txd += cal_frag_txd_num(frag->size); ++ } ++ }else ++ num_of_txd = 1; ++#else ++ num_of_txd = 1; ++#endif ++ ++#if defined(CONFIG_RALINK_MT7621) ++ if((sysRegRead(0xbe00000c)&0xFFFF) == 0x0101) { ++ ei_xmit_housekeeping(0); ++ } ++#endif ++ ++ ++ if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC)) ++ { ++ rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA ++ if (ei_local->free_txd_num < 3) ++ { ++#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL) ++ netif_stop_queue(dev); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ netif_stop_queue(ei_local->PseudoDev); ++#endif ++ tx_ring_full = 1; ++#endif ++ } ++ } else { ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (gmac_no == 2) ++ { ++ if (ei_local->PseudoDev != NULL) ++ { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.tx_dropped++; ++ } ++ } else ++#endif ++ ei_local->stat.tx_dropped++; ++ kfree_skb(skb); ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++ } ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++} ++ ++void ei_xmit_housekeeping(unsigned long unused) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++#ifndef CONFIG_RAETH_NAPI ++ unsigned long reg_int_mask=0; ++#endif ++ struct QDMA_txdesc *dma_ptr = NULL; ++ struct QDMA_txdesc *cpu_ptr = NULL; ++ struct QDMA_txdesc *tmp_ptr = NULL; ++ unsigned int ctx_offset = 0; ++ unsigned int dtx_offset = 0; ++ ++ cpu_ptr = sysRegRead(QTX_CRX_PTR); ++ dma_ptr = sysRegRead(QTX_DRX_PTR); ++ ctx_offset = GET_TXD_OFFSET(&cpu_ptr); ++ dtx_offset = GET_TXD_OFFSET(&dma_ptr); ++ cpu_ptr = (ei_local->txd_pool + (ctx_offset)); ++ dma_ptr = (ei_local->txd_pool + (dtx_offset)); ++ ++ while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) { ++ //1. keep cpu next TXD ++ tmp_ptr = cpu_ptr->txd_info2.NDP; ++ //2. release TXD ++ put_free_txd(ctx_offset); ++ //3. update ctx_offset and free skb memory ++ ctx_offset = GET_TXD_OFFSET(&tmp_ptr); ++#if defined (CONFIG_RAETH_TSO) ++ if(ei_local->skb_free[ctx_offset]!=(struct sk_buff *)0xFFFFFFFF) { ++ dev_kfree_skb_any(ei_local->skb_free[ctx_offset]); ++ } ++#else ++ dev_kfree_skb_any(ei_local->skb_free[ctx_offset]); ++#endif ++ ei_local->skb_free[ctx_offset] = 0; ++ ++ netif_wake_queue(dev); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ netif_wake_queue(ei_local->PseudoDev); ++#endif ++ tx_ring_full=0; ++ //4. update cpu_ptr ++ cpu_ptr = (ei_local->txd_pool + ctx_offset); ++ } ++ sysRegWrite(QTX_CRX_PTR, (ei_local->phy_txd_pool + (ctx_offset << 4))); ++#ifndef CONFIG_RAETH_NAPI ++ reg_int_mask=sysRegRead(QFE_INT_ENABLE); ++#if defined (DELAY_INT) ++ sysRegWrite(QFE_INT_ENABLE, reg_int_mask| RLS_DLY_INT); ++#else ++ ++ sysRegWrite(QFE_INT_ENABLE, reg_int_mask | RLS_DONE_INT); ++#endif ++#endif //CONFIG_RAETH_NAPI// ++} ++ ++EXPORT_SYMBOL(ei_start_xmit); ++EXPORT_SYMBOL(ei_xmit_housekeeping); ++EXPORT_SYMBOL(fe_dma_init); ++EXPORT_SYMBOL(rt2880_eth_send); +diff --git a/drivers/net/ethernet/raeth/raether_qdma_mt7623.c b/drivers/net/ethernet/raeth/raether_qdma_mt7623.c +new file mode 100644 +index 0000000..b465b75 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/raether_qdma_mt7623.c +@@ -0,0 +1,1020 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if defined (CONFIG_RAETH_TSO) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++#include ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) ++#include ++#else ++#include ++#endif ++ ++#include "ra2882ethreg.h" ++#include "raether.h" ++#include "ra_mac.h" ++#include "ra_ioctl.h" ++#include "ra_rfrw.h" ++#ifdef CONFIG_RAETH_NETLINK ++#include "ra_netlink.h" ++#endif ++#if defined (CONFIG_RAETH_QOS) ++#include "ra_qos.h" ++#endif ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++#include "../../../net/nat/hw_nat/ra_nat.h" ++#endif ++ ++ ++#if !defined(CONFIG_RA_NAT_NONE) ++/* bruce+ ++ */ ++extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb); ++extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no); ++#endif ++ ++#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE) ++/* Qwert+ ++ */ ++#include ++extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle); ++extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle); ++#endif /* CONFIG_RA_CLASSIFIER */ ++ ++#if defined (CONFIG_RALINK_RT3052_MP2) ++int32_t mcast_rx(struct sk_buff * skb); ++int32_t mcast_tx(struct sk_buff * skb); ++#endif ++ ++#ifdef RA_MTD_RW_BY_NUM ++int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf); ++#else ++int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf); ++#endif ++ ++/* gmac driver feature set config */ ++#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS) ++#undef DELAY_INT ++#else ++#define DELAY_INT 1 ++#endif ++ ++//#define CONFIG_UNH_TEST ++/* end of config */ ++ ++#if defined (CONFIG_RAETH_JUMBOFRAME) ++#define MAX_RX_LENGTH 4096 ++#else ++#define MAX_RX_LENGTH 1536 ++#endif ++ ++extern struct net_device *dev_raether; ++ ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++static int rx_dma_owner_idx1; ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++static int rx_calc_idx1; ++#endif ++#endif ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++static int rx_calc_idx0; ++static unsigned long tx_cpu_owner_idx0=0; ++#endif ++static unsigned long tx_ring_full=0; ++ ++#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER) ++#include "ra_ethtool.h" ++extern struct ethtool_ops ra_ethtool_ops; ++#ifdef CONFIG_PSEUDO_SUPPORT ++extern struct ethtool_ops ra_virt_ethtool_ops; ++#endif // CONFIG_PSEUDO_SUPPORT // ++#endif // (CONFIG_ETHTOOL // ++ ++#ifdef CONFIG_RALINK_VISTA_BASIC ++int is_switch_175c = 1; ++#endif ++ ++//skb->mark to queue mapping table ++extern unsigned int M2Q_table[64]; ++ ++ ++#define KSEG1 0xa0000000 ++#if defined (CONFIG_MIPS) ++#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1)) ++#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1) ++#else ++#define PHYS_TO_VIRT(x) phys_to_virt(x) ++#define VIRT_TO_PHYS(x) virt_to_phys(x) ++#endif ++ ++ ++extern void set_fe_dma_glo_cfg(void); ++ ++ ++/** ++ * ++ * @brief: get the TXD index from its address ++ * ++ * @param: cpu_ptr ++ * ++ * @return: TXD index ++*/ ++ ++static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ int ctx_offset; ++ //ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc); ++ //ctx_offset = (*cpu_ptr - ei_local->txd_pool); ++ /*kurtis*/ ++ ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->phy_txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc); ++ return ctx_offset; ++} ++ ++ ++ ++ ++/** ++ * @brief cal txd number for a page ++ * ++ * @parm size ++ * ++ * @return frag_txd_num ++ */ ++ ++unsigned int cal_frag_txd_num(unsigned int size) ++{ ++ unsigned int frag_txd_num = 0; ++ if(size == 0) ++ return 0; ++ while(size > 0){ ++ if(size > MAX_TXD_LEN){ ++ frag_txd_num++; ++ size -= MAX_TXD_LEN; ++ }else{ ++ frag_txd_num++; ++ size = 0; ++ } ++ } ++ return frag_txd_num; ++ ++} ++ ++/** ++ * @brief get free TXD from TXD queue ++ * ++ * @param free_txd ++ * ++ * @return ++ */ ++static int get_free_txd(struct QDMA_txdesc **free_txd) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned int tmp_idx; ++ ++ if(ei_local->free_txd_num > 0){ ++ tmp_idx = ei_local->free_txd_head; ++ ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx]; ++ ei_local->free_txd_num -= 1; ++ //*free_txd = &ei_local->txd_pool[tmp_idx]; ++ *free_txd = ei_local->phy_txd_pool + (sizeof(struct QDMA_txdesc) * tmp_idx); ++ return tmp_idx; ++ }else ++ return NUM_TX_DESC; ++} ++ ++ ++/** ++ * @brief add free TXD into TXD queue ++ * ++ * @param free_txd ++ * ++ * @return ++ */ ++int put_free_txd(int free_txd_idx) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx; ++ ei_local->free_txd_tail = free_txd_idx; ++ ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC; ++ ei_local->free_txd_num += 1; ++ return 1; ++} ++ ++/*define qdma initial alloc*/ ++/** ++ * @brief ++ * ++ * @param net_dev ++ * ++ * @return 0: fail ++ * 1: success ++ */ ++bool qdma_tx_desc_alloc(void) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++ struct QDMA_txdesc *free_txd = NULL; ++ unsigned int txd_idx; ++ int i = 0; ++ ++ ++ ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool); ++ printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool); ++ ++ if (ei_local->txd_pool == NULL) { ++ printk("adapter->txd_pool allocation failed!\n"); ++ return 0; ++ } ++ printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free); ++ //set all txd_pool_info to 0. ++ for ( i = 0; i < NUM_TX_DESC; i++) ++ { ++ ei_local->skb_free[i]= 0; ++ ei_local->txd_pool_info[i] = i + 1; ++ ei_local->txd_pool[i].txd_info3.LS_bit = 1; ++ ei_local->txd_pool[i].txd_info3.OWN_bit = 1; ++ } ++ ++ ei_local->free_txd_head = 0; ++ ei_local->free_txd_tail = NUM_TX_DESC - 1; ++ ei_local->free_txd_num = NUM_TX_DESC; ++ ++ ++ //get free txd from txd pool ++ txd_idx = get_free_txd(&free_txd); ++ if( txd_idx == NUM_TX_DESC) { ++ printk("get_free_txd fail\n"); ++ return 0; ++ } ++ ++ //add null TXD for transmit ++ ++ /*kurtis test*/ ++ ei_local->tx_dma_ptr = free_txd; ++ ei_local->tx_cpu_ptr = free_txd; ++ //ei_local->tx_dma_ptr = virt_to_phys(free_txd); ++ //ei_local->tx_cpu_ptr = virt_to_phys(free_txd); ++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr); ++ sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr); ++ ++ printk("kurtis: free_txd = 0x%x!!!\n", free_txd); ++ printk("kurtis: ei_local->tx_dma_ptr = 0x%x!!!\n", ei_local->tx_dma_ptr); ++ ++ //get free txd from txd pool ++ ++ txd_idx = get_free_txd(&free_txd); ++ if( txd_idx == NUM_TX_DESC) { ++ printk("get_free_txd fail\n"); ++ return 0; ++ } ++ // add null TXD for release ++ //sysRegWrite(QTX_CRX_PTR, virt_to_phys(free_txd)); ++ //sysRegWrite(QTX_DRX_PTR, virt_to_phys(free_txd)); ++ sysRegWrite(QTX_CRX_PTR, free_txd); ++ sysRegWrite(QTX_DRX_PTR, free_txd); ++ ++ printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr); ++ ++ printk(" POOL HEAD_PTR | DMA_PTR | CPU_PTR \n"); ++ printk("----------------+---------+--------\n"); ++#if 1 ++ printk(" 0x%p 0x%08X 0x%08X\n",ei_local->txd_pool, ++ ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr); ++#endif ++ return 1; ++} ++ ++bool fq_qdma_init(void) ++{ ++ struct QDMA_txdesc *free_head = NULL; ++ unsigned int free_head_phy; ++ unsigned int free_tail_phy; ++ unsigned int *free_page_head = NULL; ++ unsigned int free_page_head_phy; ++ int i; ++ ++ free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &free_head_phy); ++ if (unlikely(free_head == NULL)){ ++ printk(KERN_ERR "QDMA FQ decriptor not available...\n"); ++ return 0; ++ } ++ memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE); ++ ++ free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &free_page_head_phy); ++ if (unlikely(free_page_head == NULL)){ ++ printk(KERN_ERR "QDMA FQ pager not available...\n"); ++ return 0; ++ } ++ for (i=0; i < NUM_QDMA_PAGE; i++) { ++ free_head[i].txd_info1.SDP = (free_page_head_phy + (i * QDMA_PAGE_SIZE)); ++ if(i < (NUM_QDMA_PAGE-1)){ ++ free_head[i].txd_info2.NDP = (free_head_phy + ((i+1) * sizeof(struct QDMA_txdesc))); ++ ++ ++#if 0 ++ printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) ); ++ printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] ); ++ printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP ); ++ printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP ); ++#endif ++ } ++ free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE; ++ ++ } ++ free_tail_phy = (free_head_phy + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc))); ++ ++ printk("free_head_phy is 0x%x!!!\n", free_head_phy); ++ printk("free_tail_phy is 0x%x!!!\n", free_tail_phy); ++ sysRegWrite(QDMA_FQ_HEAD, (u32)free_head_phy); ++ sysRegWrite(QDMA_FQ_TAIL, (u32)free_tail_phy); ++ sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE)); ++ sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16); ++ return 1; ++} ++ ++int fe_dma_init(struct net_device *dev) ++{ ++ ++ int i; ++ unsigned int regVal; ++ END_DEVICE* ei_local = netdev_priv(dev); ++ ++ fq_qdma_init(); ++ ++ while(1) ++ { ++ regVal = sysRegRead(QDMA_GLO_CFG); ++ if((regVal & RX_DMA_BUSY)) ++ { ++ printk("\n RX_DMA_BUSY !!! "); ++ continue; ++ } ++ if((regVal & TX_DMA_BUSY)) ++ { ++ printk("\n TX_DMA_BUSY !!! "); ++ continue; ++ } ++ break; ++ } ++ /*tx desc alloc, add a NULL TXD to HW*/ ++ ++ qdma_tx_desc_alloc(); ++ ++ ++ /* Initial RX Ring 0*/ ++#ifdef CONFIG_32B_DESC ++ ei_local->rx_ring0 = kmalloc(NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL); ++ ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0); ++#else ++ ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0); ++#endif ++ for (i = 0; i < NUM_QRX_DESC; i++) { ++ memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++#else ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 1; ++#endif ++ ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("QDMA_RX:phy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0); ++ ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++ /* Initial RX Ring 1*/ ++#ifdef CONFIG_32B_DESC ++ ei_local->rx_ring1 = kmalloc(NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL); ++ ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1); ++#else ++ ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_QRX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1); ++#endif ++ for (i = 0; i < NUM_QRX_DESC; i++) { ++ memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++#else ++ ei_local->rx_ring1[i].rxd_info2.LS0 = 1; ++#endif ++ ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1); ++#endif ++ ++ regVal = sysRegRead(QDMA_GLO_CFG); ++ regVal &= 0x000000FF; ++ sysRegWrite(QDMA_GLO_CFG, regVal); ++ regVal=sysRegRead(QDMA_GLO_CFG); ++ ++ /* Tell the adapter where the TX/RX rings are located. */ ++ ++ sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_rx_ring0)); ++ sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_QRX_DESC)); ++ sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_QRX_DESC - 1))); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = rx_dma_owner_idx0 = sysRegRead(QRX_CRX_IDX_0); ++#endif ++ sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0); ++#if defined (CONFIG_RAETH_MULTIPLE_RX_RING) ++ sysRegWrite(QRX_BASE_PTR_1, phys_to_bus((u32) ei_local->phy_rx_ring1)); ++ sysRegWrite(QRX_MAX_CNT_1, cpu_to_le32((u32) NUM_QRX_DESC)); ++ sysRegWrite(QRX_CRX_IDX_1, cpu_to_le32((u32) (NUM_QRX_DESC - 1))); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx1 = rx_dma_owner_idx1 = sysRegRead(QRX_CRX_IDX_1); ++#endif ++ sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX1); ++#endif ++ ++#if !defined (CONFIG_RAETH_QDMATX_QDMARX) ++ /* Initial PDMA RX Ring 0*/ ++#ifdef CONFIG_32B_DESC ++ ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL); ++ ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0); ++#else ++ ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0); ++#endif ++ for (i = 0; i < NUM_RX_DESC; i++) { ++ memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc)); ++ ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0; ++#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA) ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 0; ++ ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH; ++#else ++ ei_local->rx_ring0[i].rxd_info2.LS0 = 1; ++#endif ++ ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE); ++ } ++ printk("PDMA_RX:phy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0); ++ ++ regVal = sysRegRead(PDMA_GLO_CFG); ++ regVal &= 0x000000FF; ++ sysRegWrite(PDMA_GLO_CFG, regVal); ++ regVal=sysRegRead(PDMA_GLO_CFG); ++ ++ sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0)); ++ sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC)); ++ sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1))); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ rx_calc_idx0 = sysRegRead(RX_CALC_IDX0); ++#endif ++ sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0); ++ ++#endif/*kurtis*/ ++ /* Enable randon early drop and set drop threshold automatically */ ++ sysRegWrite(QDMA_FC_THRES, 0x174444); ++ sysRegWrite(QDMA_HRED2, 0x0); ++ set_fe_dma_glo_cfg(); ++ ++ return 1; ++} ++ ++inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no) ++{ ++ unsigned int length=skb->len; ++ END_DEVICE* ei_local = netdev_priv(dev); ++ ++ struct QDMA_txdesc *cpu_ptr; ++ ++ struct QDMA_txdesc *dma_ptr __maybe_unused; ++ struct QDMA_txdesc *free_txd; ++ unsigned int ctx_offset = 0; ++ unsigned int dtx_offset = 0; ++#if defined (CONFIG_RAETH_TSO) ++ struct iphdr *iph = NULL; ++ struct QDMA_txdesc *init_cpu_ptr; ++ struct tcphdr *th = NULL; ++ struct skb_frag_struct *frag; ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags; ++ unsigned int len, size, offset, frag_txd_num; ++ int init_txd_idx, i; ++#endif // CONFIG_RAETH_TSO // ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ struct ipv6hdr *ip6h = NULL; ++#endif ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ PSEUDO_ADAPTER *pAd; ++#endif ++ cpu_ptr = (ei_local->tx_cpu_ptr); ++ ctx_offset = GET_TXD_OFFSET(&cpu_ptr); ++ cpu_ptr = phys_to_virt(ei_local->tx_cpu_ptr); ++ dma_ptr = phys_to_virt(ei_local->tx_dma_ptr); ++/*kurtis test*/ ++ //dma_ptr = (ei_local->tx_dma_ptr); ++ ++ ++ /*only modify virtual address*/ ++ //cpu_ptr = (ei_local->txd_pool) + (ctx_offset * sizeof(struct QDMA_txdesc)); ++ cpu_ptr = (ei_local->txd_pool + (ctx_offset)); ++ ++ //dtx_offset = GET_TXD_OFFSET(&dma_ptr); ++ //dma_ptr = (ei_local->txd_pool) + (dtx_offset * sizeof(struct QDMA_txdesc)); ++ ++ //printk("eth_send ctx_offset = 0x%x!!!\n", ctx_offset); ++ //printk("eth_send dtx_offset = 0x%x!!!\n", dtx_offset); ++ //printk("eth_send ei_local->txd_pool = 0x%x!!!\n", ei_local->txd_pool); ++ //printk("eth_send cpu_ptr = 0x%x!!!\n", cpu_ptr); ++ //printk("eth_send ctx_offset = 0x%x!!!\n", ctx_offset); ++ //printk("eth_send ei_local->skb_free[ctx_offset] = 0x%x!!!\n", skb); ++ ++ ++ ei_local->skb_free[ctx_offset] = skb; ++#if defined (CONFIG_RAETH_TSO) ++ init_cpu_ptr = cpu_ptr; ++ init_txd_idx = ctx_offset; ++#endif ++ ++#if !defined (CONFIG_RAETH_TSO) ++ ++ //2. prepare data ++ cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data); ++ cpu_ptr->txd_info3.SDL = skb->len; ++ ++ if (gmac_no == 1) { ++ cpu_ptr->txd_info4.FPORT = 1; ++ }else { ++ cpu_ptr->txd_info4.FPORT = 2; ++ } ++ ++ ++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark]; ++#if 0 ++ iph = (struct iphdr *)skb_network_header(skb); ++ if (iph->tos == 0xe0) ++ cpu_ptr->txd_info3.QID = 3; ++ else if (iph->tos == 0xa0) ++ cpu_ptr->txd_info3.QID = 2; ++ else if (iph->tos == 0x20) ++ cpu_ptr->txd_info3.QID = 1; ++ else ++ cpu_ptr->txd_info3.QID = 0; ++#endif ++ ++#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628) ++ if (skb->ip_summed == CHECKSUM_PARTIAL){ ++ cpu_ptr->txd_info4.TUI_CO = 7; ++ }else { ++ cpu_ptr->txd_info4.TUI_CO = 0; ++ } ++#endif ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++ if(vlan_tx_tag_present(skb)) { ++ cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb); ++ }else { ++ cpu_ptr->txd_info4.VLAN_TAG = 0; ++ } ++#endif ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if(ra_sw_nat_hook_rx!= NULL){ ++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */ ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++#if 0 ++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */ ++ cpu_ptr->txd_info4.UDF = 0x2F; ++#endif ++ ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE); ++#endif ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ ++ //3. get NULL TXD and decrease free_tx_num by 1. ++ ctx_offset = get_free_txd(&free_txd); ++ if(ctx_offset == NUM_TX_DESC) { ++ printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least. ++ return 0; ++ } ++ ++ //4. hook new TXD in the end of queue ++ //cpu_ptr->txd_info2.NDP = virt_to_phys(free_txd); ++ cpu_ptr->txd_info2.NDP = (free_txd); ++ ++ ++ //5. move CPU_PTR to new TXD ++ //ei_local->tx_cpu_ptr = virt_to_phys(free_txd); ++ ei_local->tx_cpu_ptr = (free_txd); ++ cpu_ptr->txd_info3.OWN_bit = 0; ++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr); ++ ++#if 0 ++ printk("----------------------------------------------\n"); ++ printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1); ++ printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2); ++ printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3); ++ printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4); ++#endif ++ ++#else //#if !defined (CONFIG_RAETH_TSO) ++ cpu_ptr->txd_info1.SDP = virt_to_phys(skb->data); ++ cpu_ptr->txd_info3.SDL = (length - skb->data_len); ++ cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1; ++ if (gmac_no == 1) { ++ cpu_ptr->txd_info4.FPORT = 1; ++ }else { ++ cpu_ptr->txd_info4.FPORT = 2; ++ } ++ ++ cpu_ptr->txd_info4.TSO = 0; ++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark]; ++#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628) ++ if (skb->ip_summed == CHECKSUM_PARTIAL){ ++ cpu_ptr->txd_info4.TUI_CO = 7; ++ }else { ++ cpu_ptr->txd_info4.TUI_CO = 0; ++ } ++#endif ++ ++#ifdef CONFIG_RAETH_HW_VLAN_TX ++ if(vlan_tx_tag_present(skb)) { ++ cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb); ++ }else { ++ cpu_ptr->txd_info4.VLAN_TAG = 0; ++ } ++#endif ++ ++#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE) ++ if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) { ++ if(ra_sw_nat_hook_rx!= NULL){ ++ cpu_ptr->txd_info4.FPORT = 4; /* PPE */ ++ FOE_MAGIC_TAG(skb) = 0; ++ } ++ } ++#endif ++ ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ ++ ctx_offset = get_free_txd(&free_txd); ++ if(ctx_offset == NUM_TX_DESC) { ++ printk("get_free_txd fail\n"); ++ return 0; ++ } ++ //cpu_ptr->txd_info2.NDP = virt_to_phys(free_txd); ++ //ei_local->tx_cpu_ptr = virt_to_phys(free_txd); ++ cpu_ptr->txd_info2.NDP = free_txd; ++ ei_local->tx_cpu_ptr = free_txd; ++ ++ if(nr_frags > 0) { ++ for(i=0;ifrags[i]; ++ len = frag->size; ++ frag_txd_num = cal_frag_txd_num(len); // calculate the needed TXD numbers for this fragment ++ for(frag_txd_num = frag_txd_num;frag_txd_num > 0; frag_txd_num --){ ++ // 2. size will be assigned to SDL and can't be larger than MAX_TXD_LEN ++ if(len < MAX_TXD_LEN) ++ size = len; ++ else ++ size = MAX_TXD_LEN; ++ ++ //3. Update TXD info ++ cpu_ptr = (ei_local->txd_pool + (ctx_offset)); ++ cpu_ptr->txd_info3.QID = M2Q_table[skb->mark]; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) ++ cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE); ++#else ++ cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page.p, frag->page_offset + offset, size, PCI_DMA_TODEVICE); ++// printk(" frag->page = %08x. frag->page_offset = %08x. frag->size = % 08x.\n", frag->page, (frag->page_offset+offset), size); ++#endif ++ cpu_ptr->txd_info3.SDL = size; ++ if( (i==(nr_frags-1)) && (frag_txd_num == 1)) ++ cpu_ptr->txd_info3.LS_bit = 1; ++ else ++ cpu_ptr->txd_info3.LS_bit = 0; ++ cpu_ptr->txd_info3.OWN_bit = 0; ++ cpu_ptr->txd_info3.SWC_bit = 1; ++ //4. Update skb_free for housekeeping ++ ei_local->skb_free[ctx_offset] = (cpu_ptr->txd_info3.LS_bit == 1)?skb:(struct sk_buff *)0xFFFFFFFF; //MAGIC ID ++ ++ //5. Get next TXD ++ ctx_offset = get_free_txd(&free_txd); ++ //cpu_ptr->txd_info2.NDP = virt_to_phys(free_txd); ++ //ei_local->tx_cpu_ptr = virt_to_phys(free_txd); ++ cpu_ptr->txd_info2.NDP = free_txd; ++ ei_local->tx_cpu_ptr = free_txd; ++ //6. Update offset and len. ++ offset += size; ++ len -= size; ++ } ++ } ++ ei_local->skb_free[init_txd_idx]= (struct sk_buff *)0xFFFFFFFF; //MAGIC ID ++ } ++ ++ if(skb_shinfo(skb)->gso_segs > 1) { ++ ++// TsoLenUpdate(skb->len); ++ ++ /* TCP over IPv4 */ ++ iph = (struct iphdr *)skb_network_header(skb); ++#if defined (CONFIG_RAETH_TSOV6) ++ /* TCP over IPv6 */ ++ ip6h = (struct ipv6hdr *)skb_network_header(skb); ++#endif ++ if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++ ++ init_cpu_ptr->txd_info4.TSO = 1; ++ ++ th->check = htons(skb_shinfo(skb)->gso_size); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++#endif ++ } ++ ++#if defined (CONFIG_RAETH_TSOV6) ++ /* TCP over IPv6 */ ++ //ip6h = (struct ipv6hdr *)skb_network_header(skb); ++ else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) { ++ th = (struct tcphdr *)skb_transport_header(skb); ++#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR ++ init_cpu_ptr->txd_info4.TSO = 1; ++#else ++ init_cpu_ptr->txd_info4.TSO = 1; ++#endif ++ th->check = htons(skb_shinfo(skb)->gso_size); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(th), sizeof(struct tcphdr), DMA_TO_DEVICE); ++#endif ++ } ++#endif ++ } ++ ++ ++// dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++ ++ init_cpu_ptr->txd_info3.OWN_bit = 0; ++#endif // CONFIG_RAETH_TSO // ++ ++ sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr); ++ ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (gmac_no == 2) { ++ if (ei_local->PseudoDev != NULL) { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.tx_packets++; ++ pAd->stat.tx_bytes += length; ++ } ++ } else ++ ++#endif ++ { ++ ei_local->stat.tx_packets++; ++ ei_local->stat.tx_bytes += skb->len; ++ } ++#ifdef CONFIG_RAETH_NAPI ++ if ( ei_local->tx_full == 1) { ++ ei_local->tx_full = 0; ++ netif_wake_queue(dev); ++ } ++#endif ++ ++ return length; ++} ++ ++int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no) ++{ ++ END_DEVICE *ei_local = netdev_priv(dev); ++ unsigned long flags; ++ unsigned int num_of_txd = 0; ++#if defined (CONFIG_RAETH_TSO) ++ unsigned int nr_frags = skb_shinfo(skb)->nr_frags, i; ++ struct skb_frag_struct *frag; ++#endif ++#ifdef CONFIG_PSEUDO_SUPPORT ++ PSEUDO_ADAPTER *pAd; ++#endif ++ ++#if !defined(CONFIG_RA_NAT_NONE) ++ if(ra_sw_nat_hook_tx!= NULL) ++ { ++// spin_lock_irqsave(&ei_local->page_lock, flags); ++ if(ra_sw_nat_hook_tx(skb, gmac_no)==1){ ++// spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ }else{ ++ kfree_skb(skb); ++// spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++ } ++ } ++#endif ++ ++#if defined(CONFIG_RALINK_MT7621) || defined(CONFIG_ARCH_MT7623) ++#define MIN_PKT_LEN 64 ++ if (skb->len < MIN_PKT_LEN) { ++ if (skb_padto(skb, MIN_PKT_LEN)) { ++ printk("raeth: skb_padto failed\n"); ++ return 0; ++ } ++ skb_put(skb, MIN_PKT_LEN - skb->len); ++ } ++#endif ++ ++ ++ dev->trans_start = jiffies; /* save the timestamp */ ++ spin_lock_irqsave(&ei_local->page_lock, flags); ++#if defined (CONFIG_MIPS) ++ dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++#else ++ dma_sync_single_for_device(NULL, virt_to_phys(skb->data), skb->len, DMA_TO_DEVICE); ++#endif ++ ++ ++//check free_txd_num before calling rt288_eth_send() ++ ++#if defined (CONFIG_RAETH_TSO) ++ // num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1); ++ if(nr_frags != 0){ ++ for(i=0;ifrags[i]; ++ num_of_txd += cal_frag_txd_num(frag->size); ++ } ++ }else ++ num_of_txd = 1; ++#else ++ num_of_txd = 1; ++#endif ++ ++#if defined(CONFIG_RALINK_MT7621) ++ if((sysRegRead(0xbe00000c)&0xFFFF) == 0x0101) { ++ ei_xmit_housekeeping(0); ++ } ++#endif ++ ++ ei_xmit_housekeeping(0); ++ ++ //if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC)) ++ if ((ei_local->free_txd_num > num_of_txd + 5) && (ei_local->free_txd_num != NUM_TX_DESC)) ++ { ++ rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA ++ if (ei_local->free_txd_num < 3) ++ { ++#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL) ++ netif_stop_queue(dev); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ netif_stop_queue(ei_local->PseudoDev); ++#endif ++ tx_ring_full = 1; ++#endif ++ } ++ } else { ++#ifdef CONFIG_PSEUDO_SUPPORT ++ if (gmac_no == 2) ++ { ++ if (ei_local->PseudoDev != NULL) ++ { ++ pAd = netdev_priv(ei_local->PseudoDev); ++ pAd->stat.tx_dropped++; ++ } ++ } else ++#endif ++ ei_local->stat.tx_dropped++; ++ kfree_skb(skb); ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++ } ++ spin_unlock_irqrestore(&ei_local->page_lock, flags); ++ return 0; ++} ++ ++void ei_xmit_housekeeping(unsigned long unused) ++{ ++ struct net_device *dev = dev_raether; ++ END_DEVICE *ei_local = netdev_priv(dev); ++#ifndef CONFIG_RAETH_NAPI ++ unsigned long reg_int_mask=0; ++#endif ++ struct QDMA_txdesc *dma_ptr = NULL; ++ struct QDMA_txdesc *cpu_ptr = NULL; ++ struct QDMA_txdesc *tmp_ptr = NULL; ++ unsigned int htx_offset = 0; ++ unsigned int ctx_offset = 0; ++ unsigned int dtx_offset = 0; ++ ++ //dma_ptr = phys_to_virt(sysRegRead(QTX_DRX_PTR)); ++ //cpu_ptr = phys_to_virt(sysRegRead(QTX_CRX_PTR)); ++ //printk("kurtis:housekeeping QTX_DRX_PTR = 0x%x!!!\n", sysRegRead(QTX_DRX_PTR)); ++ //printk("kurtis:housekeeping DMA_PTR = 0x%x!!!\n", dma_ptr); ++ ++ cpu_ptr = sysRegRead(QTX_CRX_PTR); ++ dma_ptr = sysRegRead(QTX_DRX_PTR); ++ ++ //printk("kurtis:housekeeping QTX_CRX_PTR = 0x%x!!!\n", cpu_ptr); ++ //printk("kurtis:housekeeping QTX_DRX_PTR = 0x%x!!!\n", dma_ptr); ++ ctx_offset = GET_TXD_OFFSET(&cpu_ptr); ++ dtx_offset = GET_TXD_OFFSET(&dma_ptr); ++ htx_offset = ctx_offset; ++ cpu_ptr = (ei_local->txd_pool + (ctx_offset)); ++ dma_ptr = (ei_local->txd_pool + (dtx_offset)); ++ ++ ++ //printk("kurtis:housekeeping CPU_PTR = 0x%x!!!\n", cpu_ptr); ++ //printk("kurtis:housekeeping DMA_PTR = 0x%x!!!\n", dma_ptr); ++ ++/*temp mark*/ ++#if 1 ++ ++ ++ if(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) { ++ while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) { ++ ++ //1. keep cpu next TXD ++ //tmp_ptr = phys_to_virt(cpu_ptr->txd_info2.NDP); ++ tmp_ptr = cpu_ptr->txd_info2.NDP; ++ htx_offset = GET_TXD_OFFSET(&tmp_ptr); ++ //printk("kurtis:housekeeping cpu_ptr->txd_info2.NDP = 0x%x!!!\n", cpu_ptr->txd_info2.NDP); ++ //printk("kurtis:housekeeping tmp_ptr = 0x%x!!!\n", tmp_ptr); ++ //printk("kurtis:housekeeping htx_offset = 0x%x!!!\n", htx_offset); ++ //2. free skb meomry ++#if defined (CONFIG_RAETH_TSO) ++ if(ei_local->skb_free[htx_offset]!=(struct sk_buff *)0xFFFFFFFF) { ++ dev_kfree_skb_any(ei_local->skb_free[htx_offset]); ++ } ++#else ++ dev_kfree_skb_any(ei_local->skb_free[htx_offset]); ++#endif ++ ++ //3. release TXD ++ //htx_offset = GET_TXD_OFFSET(&cpu_ptr); ++ //put_free_txd(htx_offset); ++ put_free_txd(ctx_offset); ++ ++ ++ ++ netif_wake_queue(dev); ++#ifdef CONFIG_PSEUDO_SUPPORT ++ netif_wake_queue(ei_local->PseudoDev); ++#endif ++ tx_ring_full=0; ++ ++ //4. update cpu_ptr to next ptr ++ //cpu_ptr = tmp_ptr; ++ cpu_ptr = (ei_local->txd_pool + htx_offset); ++ ctx_offset = htx_offset; ++ //cpu_ptr = (cpu_ptr + (htx_offset)); ++ //printk("kurtis:housekeeping 4. update cpu_ptr = 0x%x!!!\n", cpu_ptr); ++ } ++ } ++ //sysRegWrite(QTX_CRX_PTR, virt_to_phys(cpu_ptr)); ++ //sysRegWrite(QTX_CRX_PTR, cpu_ptr); ++ tmp_ptr = (ei_local->phy_txd_pool + (htx_offset << 4)); ++ //printk("kurtis:housekeeping 5. update QTX_CRX_PTR = 0x%x!!!\n", tmp_ptr); ++ sysRegWrite(QTX_CRX_PTR, tmp_ptr); ++ ++#endif ++ ++#ifndef CONFIG_RAETH_NAPI ++ reg_int_mask=sysRegRead(QFE_INT_ENABLE); ++#if defined (DELAY_INT) ++ sysRegWrite(FE_INT_ENABLE, reg_int_mask| RLS_DLY_INT); ++#else ++ ++ sysRegWrite(FE_INT_ENABLE, reg_int_mask | RLS_DONE_INT); ++#endif ++#endif //CONFIG_RAETH_NAPI// ++} ++ ++EXPORT_SYMBOL(ei_start_xmit); ++EXPORT_SYMBOL(ei_xmit_housekeeping); ++EXPORT_SYMBOL(fe_dma_init); ++EXPORT_SYMBOL(rt2880_eth_send); +diff --git a/drivers/net/ethernet/raeth/smb_hook.c b/drivers/net/ethernet/raeth/smb_hook.c +new file mode 100644 +index 0000000..617139c +--- /dev/null ++++ b/drivers/net/ethernet/raeth/smb_hook.c +@@ -0,0 +1,17 @@ ++#include ++#include ++#include ++#include ++#include ++ ++ ++int (*smb_nf_local_in_hook)(struct sk_buff *skb) = NULL; ++int (*smb_nf_pre_routing_hook)(struct sk_buff *skb) = NULL; ++int (*smb_nf_local_out_hook)(struct sk_buff *skb) = NULL; ++int (*smb_nf_post_routing_hook)(struct sk_buff *skb) = NULL; ++EXPORT_SYMBOL(smb_nf_local_in_hook); ++EXPORT_SYMBOL(smb_nf_pre_routing_hook); ++EXPORT_SYMBOL(smb_nf_local_out_hook); ++EXPORT_SYMBOL(smb_nf_post_routing_hook); ++ ++ +diff --git a/drivers/net/ethernet/raeth/smb_nf.c b/drivers/net/ethernet/raeth/smb_nf.c +new file mode 100644 +index 0000000..86250eb +--- /dev/null ++++ b/drivers/net/ethernet/raeth/smb_nf.c +@@ -0,0 +1,177 @@ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++extern int (*smb_nf_local_in_hook)(struct sk_buff *skb); ++extern int (*smb_nf_pre_routing_hook)(struct sk_buff *skb); ++extern int (*smb_nf_local_out_hook)(struct sk_buff *skb); ++extern int (*smb_nf_post_routing_hook)(struct sk_buff *skb); ++ ++struct net_device *lan_int = NULL; ++struct in_ifaddr *lan_ifa = NULL; ++ ++ ++int mtk_smb_nf_local_in_hook(struct sk_buff *skb) ++{ ++ struct iphdr *iph = ip_hdr(skb); ++ ++ if (skb->protocol == htons(ETH_P_IP)) { ++ struct iphdr *iph = ip_hdr(skb); ++ ++ if (iph->protocol == IPPROTO_TCP) { ++ struct tcphdr *th = tcp_hdr(skb); ++ unsigned short sport, dport; ++ ++ th = tcp_hdr(skb); ++ th = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl*4); ++ ++ if ((iph->daddr == lan_ifa->ifa_local) ++ && ((th->dest == 0xbd01) || (th->dest == 0x8900) ++ || (th->dest == 0x8a00) || (th->dest == 0x8b00))) ++ return 1; ++ else ++ return 0; ++ } ++ ++ } ++ ++ return 0; ++} ++ ++int mtk_smb_nf_pre_routing_hook(struct sk_buff *skb) ++{ ++ struct iphdr *iph = ip_hdr(skb); ++ ++ if (skb->protocol == htons(ETH_P_IP)) { ++ struct iphdr *iph = ip_hdr(skb); ++ ++ if (iph->protocol == IPPROTO_TCP) { ++ struct tcphdr *th = tcp_hdr(skb); ++ unsigned short sport, dport; ++ ++ th = tcp_hdr(skb); ++ th = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl*4); ++ if ((iph->daddr == lan_ifa->ifa_local) ++ && ((th->dest == 0xbd01) || (th->dest == 0x8900) ++ || (th->dest == 0x8a00) || (th->dest == 0x8b00))) ++ return 1; ++ else ++ return 0; ++ } ++ ++ } ++ ++ return 0; ++} ++ ++int mtk_smb_nf_local_out_hook(struct sk_buff *skb) ++{ ++ struct iphdr *iph = ip_hdr(skb); ++ ++ if (iph->protocol == IPPROTO_TCP) { ++ struct tcphdr *th = tcp_hdr(skb); ++ ++ th = tcp_hdr(skb); ++ th = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl*4); ++ ++ if ((iph->saddr == lan_ifa->ifa_local) ++ && ((th->source == 0xbd01) || (th->source == 0x8900) ++ || (th->source == 0x8a00) || (th->source == 0x8b00))) ++ return 1; ++ else ++ return 0; ++ } ++ ++ return 0; ++} ++ ++int mtk_smb_nf_post_routing_hook(struct sk_buff *skb) ++{ ++ struct iphdr *iph = ip_hdr(skb); ++ ++ if (skb->protocol == htons(ETH_P_IP)) { ++ struct iphdr *iph = ip_hdr(skb); ++ ++ if (iph->protocol == IPPROTO_TCP) { ++ struct tcphdr *th = tcp_hdr(skb); ++ ++ th = tcp_hdr(skb); ++ th = (struct tcphdr *)(((unsigned char *)iph) + iph->ihl*4); ++ ++ if ((iph->saddr == lan_ifa->ifa_local) ++ && ((th->source == 0xbd01) || (th->source == 0x8900) ++ || (th->source == 0x8a00) || (th->source == 0x8b00))) ++ return 1; ++ else ++ return 0; ++ } ++ ++ } ++ ++ return 0; ++} ++ ++int __init mtk_smb_hook_init(void) ++{ ++ struct in_device *in_dev; ++ struct in_ifaddr **ifap = NULL; ++ struct in_ifaddr *ifa = NULL; ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35) ++ lan_int = dev_get_by_name(&init_net, "br0"); ++#else ++ lan_int = dev_get_by_name("br0"); ++#endif ++ if (lan_int) ++ in_dev = __in_dev_get_rtnl(lan_int); ++ else ++ return 0; ++ ++ if (in_dev) { ++ for (ifap = &in_dev->ifa_list; (ifa = *ifap) != NULL; ++ ifap = &ifa->ifa_next) { ++ if (!strcmp("br0", ifa->ifa_label)) ++ { ++ lan_ifa = ifa; ++ break; /* found */ ++ } ++ } ++ } ++ else ++ return 0; ++ ++ if (lan_ifa) { ++ smb_nf_local_in_hook = mtk_smb_nf_local_in_hook; ++ smb_nf_pre_routing_hook = mtk_smb_nf_pre_routing_hook; ++ smb_nf_local_out_hook = mtk_smb_nf_local_out_hook; ++ smb_nf_post_routing_hook = mtk_smb_nf_post_routing_hook; ++ } ++ ++ printk("Samba Netfilter Hook Enabled\n"); ++ ++ return 0; ++} ++ ++void mtk_smb_hook_cleanup(void) ++{ ++ lan_int = NULL; ++ lan_ifa = NULL; ++ smb_nf_local_in_hook = NULL; ++ smb_nf_pre_routing_hook = NULL; ++ smb_nf_local_out_hook = NULL; ++ smb_nf_post_routing_hook = NULL; ++ ++ return; ++} ++ ++module_init(mtk_smb_hook_init); ++module_exit(mtk_smb_hook_cleanup); ++ ++MODULE_LICENSE("GPL"); +diff --git a/drivers/net/ethernet/raeth/sync_write.h b/drivers/net/ethernet/raeth/sync_write.h +new file mode 100644 +index 0000000..8b800e6 +--- /dev/null ++++ b/drivers/net/ethernet/raeth/sync_write.h +@@ -0,0 +1,103 @@ ++#ifndef _MT_SYNC_WRITE_H ++#define _MT_SYNC_WRITE_H ++ ++#if defined(__KERNEL__) ++ ++#include ++#include ++//#include ++ ++/* ++ * Define macros. ++ */ ++ ++#define mt65xx_reg_sync_writel(v, a) \ ++ do { \ ++ __raw_writel((v), IOMEM((a))); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt65xx_reg_sync_writew(v, a) \ ++ do { \ ++ __raw_writew((v), IOMEM((a))); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt65xx_reg_sync_writeb(v, a) \ ++ do { \ ++ __raw_writeb((v), IOMEM((a))); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt_reg_sync_writel(v, a) \ ++ do { \ ++ __raw_writel((v), IOMEM((a))); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt_reg_sync_writew(v, a) \ ++ do { \ ++ __raw_writew((v), IOMEM((a))); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt_reg_sync_writeb(v, a) \ ++ do { \ ++ __raw_writeb((v), IOMEM((a))); \ ++ dsb(); \ ++ } while (0) ++ ++ ++#else /* __KERNEL__ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define dsb() \ ++ do { \ ++ __asm__ __volatile__ ("dsb" : : : "memory"); \ ++ } while (0) ++ ++#define mt65xx_reg_sync_writel(v, a) \ ++ do { \ ++ *(volatile unsigned int *)(a) = (v); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt65xx_reg_sync_writew(v, a) \ ++ do { \ ++ *(volatile unsigned short *)(a) = (v); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt65xx_reg_sync_writeb(v, a) \ ++ do { \ ++ *(volatile unsigned char *)(a) = (v); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt_reg_sync_writel(v, a) \ ++ do { \ ++ *(volatile unsigned int *)(a) = (v); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt_reg_sync_writew(v, a) \ ++ do { \ ++ *(volatile unsigned short *)(a) = (v); \ ++ dsb(); \ ++ } while (0) ++ ++#define mt_reg_sync_writeb(v, a) \ ++ do { \ ++ *(volatile unsigned char *)(a) = (v); \ ++ dsb(); \ ++ } while (0) ++ ++ ++#endif /* __KERNEL__ */ ++ ++#endif /* !_MT_SYNC_WRITE_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0064-arm-mediatek-add-mt7623-pcie-support.patch b/target/linux/mediatek/patches/0064-arm-mediatek-add-mt7623-pcie-support.patch new file mode 100644 index 0000000..ee82f9c --- /dev/null +++ b/target/linux/mediatek/patches/0064-arm-mediatek-add-mt7623-pcie-support.patch @@ -0,0 +1,436 @@ +From 29ceb2449cb3622ccfba9eb1c77bf2ac4162464b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:15:29 +0200 +Subject: [PATCH 64/76] arm: mediatek: add mt7623 pcie support + +Signed-off-by: John Crispin +--- + arch/arm/mach-mediatek/Makefile | 2 +- + arch/arm/mach-mediatek/pcie.c | 383 +++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-mediatek/pcie.h | 14 ++ + 3 files changed, 398 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/mach-mediatek/pcie.c + create mode 100644 arch/arm/mach-mediatek/pcie.h + +diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile +index 2116460..aca28a2 100644 +--- a/arch/arm/mach-mediatek/Makefile ++++ b/arch/arm/mach-mediatek/Makefile +@@ -1,4 +1,4 @@ + ifeq ($(CONFIG_SMP),y) + obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o + endif +-obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o ++obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o pcie.o +diff --git a/arch/arm/mach-mediatek/pcie.c b/arch/arm/mach-mediatek/pcie.c +new file mode 100644 +index 0000000..8394712 +--- /dev/null ++++ b/arch/arm/mach-mediatek/pcie.c +@@ -0,0 +1,383 @@ ++/* ++ * Mediatek MT7623 SoC PCIE support ++ * ++ * Copyright (C) 2015 Mediatek ++ * Copyright (C) 2015 John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "pcie.h" ++ ++#define PCICFG 0x00 ++#define PCIINT 0x08 ++#define PCIENA 0x0C ++#define CFGADDR 0x20 ++#define CFGDATA 0x24 ++#define MEMBASE 0x28 ++#define IOBASE 0x2C ++ ++#define BAR0SETUP 0x10 ++#define IMBASEBAR0 0x18 ++#define PCIE_CLASS 0x34 ++#define PCIE_SISTAT 0x50 ++ ++#define MTK_PCIE_HIGH_PERF BIT(14) ++#define PCIEP0_BASE 0x2000 ++#define PCIEP1_BASE 0x3000 ++#define PCIEP2_BASE 0x4000 ++ ++#define PHY_P0_CTL 0x9000 ++#define PHY_P1_CTL 0xA000 ++#define PHY_P2_CTL 0x4000 ++ ++#define RSTCTL_PCIE0_RST BIT(24) ++#define RSTCTL_PCIE1_RST BIT(25) ++#define RSTCTL_PCIE2_RST BIT(26) ++ ++static void __iomem *pcie_base; ++static int pcie_card_link; ++ ++static struct mtk_pcie_port { ++ int id; ++ int enable; ++ u32 base; ++ u32 phy_base; ++ u32 perst_n; ++ u32 reset; ++ u32 interrupt; ++ u32 link; ++} mtk_pcie_port[] = { ++ { 0, 1, PCIEP0_BASE, PHY_P0_CTL, BIT(1), RSTCTL_PCIE0_RST, BIT(20) }, ++ { 1, 1, PCIEP1_BASE, PHY_P1_CTL, BIT(2), RSTCTL_PCIE1_RST, BIT(21) }, ++ { 2, 0, PCIEP2_BASE, PHY_P2_CTL, BIT(3), RSTCTL_PCIE2_RST, BIT(22) }, ++}; ++ ++#define mtk_foreach_port(p) \ ++ for (p = mtk_pcie_port; p != &mtk_pcie_port[ARRAY_SIZE(mtk_pcie_port)]; p++) ++ ++#define mtk_foreach_port_enabled(p) \ ++ mtk_foreach_port(p) \ ++ if (p->enable) ++ ++#define mtk_foreach_port_link(p) \ ++ mtk_foreach_port(p) \ ++ if (p->link) ++ ++static struct mtk_phy_init { ++ uint32_t reg; ++ uint32_t mask; ++ uint32_t val; ++} mtk_phy_init[] = { ++ { 0xC00, 0x33000, 0x22000 }, ++ { 0xB04, 0xe0000000, 0x40000000 }, ++ { 0xB00, 0xe, 0x4 }, ++ { 0xC3C, 0xffff0000, 0x3c0000 }, ++ { 0xC48, 0xffff, 0x36 }, ++ { 0xC0C, 0x30000000, 0x10000000 }, ++ { 0xC08, 0x3800c0, 0xc0 }, ++ { 0xC10, 0xf0000, 0x20000 }, ++ { 0xC0C, 0xf000, 0x1000 }, ++ { 0xC14, 0xf0000, 0xa0000 }, ++}; ++ ++static inline void pcie_w32(u32 val, unsigned reg) ++{ ++ iowrite32(val, pcie_base + reg); ++} ++ ++static inline u32 pcie_r32(unsigned reg) ++{ ++ return ioread32(pcie_base + reg); ++} ++ ++static inline void pcie_m32(u32 mask, u32 val, unsigned reg) ++{ ++ u32 v = pcie_r32(reg); ++ ++ v &= mask; ++ v |= val; ++ pcie_w32(v, reg); ++} ++ ++static int pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) ++{ ++ unsigned int slot = PCI_SLOT(devfn); ++ u8 func = PCI_FUNC(devfn); ++ u32 address; ++ u32 data; ++ u32 num = 0; ++ ++ if (bus) ++ num = bus->number; ++ ++ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc); ++ pcie_m32(0xf0000000, address, CFGADDR); ++ data = pcie_r32(CFGDATA); ++ ++ switch (size) { ++ case 1: ++ *val = (data >> ((where & 3) << 3)) & 0xff; ++ break; ++ case 2: ++ *val = (data >> ((where & 3) << 3)) & 0xffff; ++ break; ++ case 4: ++ *val = data; ++ break; ++ } ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) ++{ ++ unsigned int slot = PCI_SLOT(devfn); ++ u8 func = PCI_FUNC(devfn); ++ u32 address; ++ u32 data; ++ u32 num = 0; ++ ++ if (bus) ++ num = bus->number; ++ ++ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc); ++ pcie_m32(0xf0000000, address, CFGADDR); ++ data = pcie_r32(CFGDATA); ++ ++ switch (size) { ++ case 1: ++ data = (data & ~(0xff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ break; ++ case 2: ++ data = (data & ~(0xffff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ break; ++ case 4: ++ data = val; ++ break; ++ } ++ ++ pcie_w32(data, CFGDATA); ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static struct pci_ops mtk_pcie_ops = { ++ .read = pcie_config_read, ++ .write = pcie_config_write, ++}; ++ ++static struct resource pci_mem = { ++ .name = "PCIe Memory space", ++ .start = MEM_DIRECT1, ++ .end = (u32) (MEM_DIRECT1 + (unsigned char *) 0x0fffffff), ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct resource pci_io = { ++ .name = "PCIe IO space", ++ .start = IO_WIN, ++ .end = (u32) (IO_WIN + (unsigned char *) 0x0ffff), ++ .flags = IORESOURCE_IO, ++}; ++ ++static int __init mtk_pcie_setup(int nr, struct pci_sys_data *sys) ++{ ++ sys->mem_offset = 0; ++ sys->io_offset = 0; ++ ++ request_resource(&ioport_resource, &pci_io); ++ request_resource(&iomem_resource, &pci_mem); ++ ++ pci_add_resource_offset(&sys->resources, &pci_io, sys->io_offset); ++ pci_add_resource_offset(&sys->resources, &pci_mem, sys->mem_offset); ++ ++ return 1; ++} ++ ++static struct pci_bus * __init mtk_pcie_scan_bus(int nr, struct pci_sys_data *sys) ++{ ++ return pci_scan_root_bus(NULL, sys->busnr, &mtk_pcie_ops, sys, ++ &sys->resources); ++} ++ ++static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ u16 cmd; ++ u32 val; ++ ++ if (dev->bus->number == 0) { ++ pcie_config_write(NULL, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); ++ pcie_config_read(NULL, slot, 0, PCI_BASE_ADDRESS_0, &val); ++ printk("BAR0 at bus %d, slot %d\n", dev->bus->number, slot); ++ } ++ ++ printk("bus=0x%x, slot = 0x%x, pin=0x%x, irq=0x%x\n", dev->bus->number, slot, pin, dev->irq); ++ ++ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); ++ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); ++ ++ return dev->irq; ++} ++ ++static void __init mtk_pcie_preinit(void) ++{ ++ struct mtk_pcie_port *port; ++ u32 val = 0; ++ int i; ++ ++ pcibios_min_io = 0; ++ pcibios_min_mem = 0; ++ ++#if defined (CONFIG_PCIE_PORT2) ++ printk("%s: PCIe/USB3 combo PHY mode (%x) =%x\n", __func__, SYSCFG1, REGDATA(SYSCFG1)); ++ REGDATA(SYSCFG1) &= ~(0x300000); ++ printk("%s: PCIe/USB3 combo PHY mode (%x) =%x\n", __func__, SYSCFG1, REGDATA(SYSCFG1)); ++#endif ++ ++ /* PCIe RC Reset */ ++ val = 0; ++ mtk_foreach_port_enabled(port) ++ val |= port->reset; ++ REGDATA(RSTCTL) |= val; ++ mdelay(10); ++ REGDATA(RSTCTL) &= ~val; ++ mdelay(10); ++ ++ /* Configure PCIe PHY */ ++ mtk_foreach_port_enabled(port) { ++ for (i = 0; i < ARRAY_SIZE(mtk_phy_init); i++) { ++ u32 val = pcie_r32(port->phy_base + mtk_phy_init[i].reg); ++ val &= ~mtk_phy_init[i].mask; ++ val |= mtk_phy_init[i].val; ++ pcie_w32(val, port->phy_base + mtk_phy_init[i].reg); ++ } ++ mdelay(10); ++ } ++ ++ /* Enable RC */ ++ mtk_foreach_port_enabled(port) { ++ val = 0; ++ pcie_config_read(NULL, port->id, 0, 0x73c, &val); ++ val &= ~(0x9fff)<<16; ++ val |= 0x806c<<16; ++ pcie_config_write(NULL, port->id, 0, 0x73c, val); ++ } ++ ++ /* PCIe EP reset */ ++ val = 0; ++ mtk_foreach_port_enabled(port) ++ val |= port->perst_n; ++ val |= MTK_PCIE_HIGH_PERF; ++ pcie_w32(pcie_r32(PCICFG) | val, PCICFG); ++ mdelay(10); ++ pcie_w32(pcie_r32(PCICFG) & ~val, PCICFG); ++ mdelay(10); ++ ++ /* check the link status */ ++ val = 0; ++ mtk_foreach_port_enabled(port) { ++ if ((pcie_r32(port->base + PCIE_SISTAT) & 0x1)) ++ port->link = 1; ++ else ++ val |= port->reset; ++ } ++ REGDATA(RSTCTL) |= val; ++ ++ mtk_foreach_port_link(port) ++ pcie_card_link++; ++ ++ printk("PCIe Link count = %d\n", pcie_card_link); ++ if (!pcie_card_link) ++ return; ++ ++ pcie_w32(MEM_WIN, MEMBASE); ++ pcie_w32(IO_WIN, IOBASE); ++ ++ mtk_foreach_port_link(port) { ++ pcie_m32(0, port->interrupt, PCIENA); ++ pcie_w32(0x7FFF0001, port->base + BAR0SETUP); ++ pcie_w32(MEMORY_BASE, port->base + IMBASEBAR0); ++ pcie_w32(0x06040001, port->base + PCIE_CLASS); ++ printk("PCIE%d Setup OK\n", port->id); ++ } ++ val = 0; ++ ++ pcie_config_read(NULL, pcie_card_link - 1, 0, 0x4, &val); ++ pcie_config_write(NULL, pcie_card_link - 1, 0, 0x4, val|0x4); ++ pcie_config_read(NULL, pcie_card_link - 1, 0, 0x70c, &val); ++ val &= ~(0xff3) << 8; ++ val |= 0x50 << 8; ++ pcie_config_write(NULL, pcie_card_link - 1, 0, 0x70c, val); ++ pcie_config_read(NULL, pcie_card_link - 1, 0, 0x70c, &val); ++} ++ ++static struct hw_pci mtk_pci __initdata = { ++ .nr_controllers = 1, ++ .map_irq = mtk_pcie_map_irq, ++ .setup = mtk_pcie_setup, ++ .scan = mtk_pcie_scan_bus, ++ .preinit = mtk_pcie_preinit, ++}; ++ ++extern void mt7623_ethifsys_init(void); ++static int mtk_pcie_probe(struct platform_device *pdev) ++{ ++ struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res); ++ if (!pcie_base) ++ return -ENOMEM; ++ ++ mt7623_ethifsys_init(); ++ pci_common_init_dev(&pdev->dev, &mtk_pci); ++ ++ return 0; ++} ++ ++static const struct of_device_id mtk_pcie_ids[] = { ++ { .compatible = "mediatek,mt7623-pcie" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, mtk_pcie_ids); ++ ++static struct platform_driver mtk_pcie_driver = { ++ .probe = mtk_pcie_probe, ++ .driver = { ++ .name = "mt7623-pcie", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(mtk_pcie_ids), ++ }, ++}; ++ ++static int __init mtk_pcie_init(void) ++{ ++ return platform_driver_register(&mtk_pcie_driver); ++} ++ ++late_initcall(mtk_pcie_init); +diff --git a/arch/arm/mach-mediatek/pcie.h b/arch/arm/mach-mediatek/pcie.h +new file mode 100644 +index 0000000..400a760e +--- /dev/null ++++ b/arch/arm/mach-mediatek/pcie.h +@@ -0,0 +1,14 @@ ++#define SYSCTL_BASE 0xFA000000 ++#define MEM_WIN 0x1A150000 ++#define IO_WIN 0x1A160000 ++#define MEM_DIRECT1 0x60000000 ++#define MEMORY_BASE 0x80000000 ++ ++#define REGADDR(x, y) (x##_BASE + y) ++#define REGDATA(x) *((volatile unsigned int *)(x)) ++ ++#define SYSCFG1 REGADDR(SYSCTL, 0x14) ++#define RSTCTL REGADDR(SYSCTL, 0x34) ++ ++ ++ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0065-arm-mediatek-add-mt7623-smp-support.patch b/target/linux/mediatek/patches/0065-arm-mediatek-add-mt7623-smp-support.patch new file mode 100644 index 0000000..98f8acb --- /dev/null +++ b/target/linux/mediatek/patches/0065-arm-mediatek-add-mt7623-smp-support.patch @@ -0,0 +1,38 @@ +From 3f181d60fcd80b0d98849076ed2aa43de2cb6d8c Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:16:27 +0200 +Subject: [PATCH 65/76] arm: mediatek: add mt7623 smp support + +Signed-off-by: John Crispin +--- + arch/arm/mach-mediatek/platsmp.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c +index e266b3d..81fdcff 100644 +--- a/arch/arm/mach-mediatek/platsmp.c ++++ b/arch/arm/mach-mediatek/platsmp.c +@@ -45,6 +45,12 @@ static const struct mtk_smp_boot_info mtk_mt6589_boot = { + { 0x38, 0x3c, 0x40 }, + }; + ++static const struct mtk_smp_boot_info mtk_mt7623_boot = { ++ 0x10202000, 0x34, 0x30, ++ { 0x534c4131, 0x4c415332, 0x41534c33 }, ++ { 0x38, 0x3c, 0x40 }, ++}; ++ + static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = { + { .compatible = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot }, + { .compatible = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot }, +@@ -52,6 +58,7 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = { + + static const struct of_device_id mtk_smp_boot_infos[] __initconst = { + { .compatible = "mediatek,mt6589", .data = &mtk_mt6589_boot }, ++ { .compatible = "mediatek,mt7623", .data = &mtk_mt7623_boot }, + }; + + static void __iomem *mtk_smp_base; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0066-arm-mediatek-add-m7623-devicetree.patch b/target/linux/mediatek/patches/0066-arm-mediatek-add-m7623-devicetree.patch new file mode 100644 index 0000000..4516561 --- /dev/null +++ b/target/linux/mediatek/patches/0066-arm-mediatek-add-m7623-devicetree.patch @@ -0,0 +1,551 @@ +From a6bf117b5fe3acd76bbc45cc87fd80f589136e59 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:14:42 +0200 +Subject: [PATCH 66/76] arm: mediatek: add m7623 devicetree + +Signed-off-by: John Crispin +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/mt7623-evb.dts | 162 ++++++++++++++++++ + arch/arm/boot/dts/mt7623.dtsi | 348 ++++++++++++++++++++++++++++++++++++++ + 3 files changed, 511 insertions(+) + create mode 100644 arch/arm/boot/dts/mt7623-evb.dts + create mode 100644 arch/arm/boot/dts/mt7623.dtsi + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 992736b..525392e 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -658,6 +658,7 @@ dtb-$(CONFIG_MACH_DOVE) += \ + dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt6589-aquaris5.dtb \ + mt6592-evb.dtb \ ++ mt7623-evb.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb + endif +diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts +new file mode 100644 +index 0000000..759142f +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623-evb.dts +@@ -0,0 +1,162 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Joe.C ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include ++#include "mt7623.dtsi" ++ ++/ { ++ model = "MediaTek MT7623 Evaluation Board"; ++ compatible = "mediatek,mt7623-evb", "mediatek,mt7623"; ++ ++ chosen { ++ stdout-path = &uart2; ++ }; ++ ++ memory { ++ reg = <0 0x80000000 0 0x10000000>; ++ }; ++ ++ usb_p1_vbus: fixedregulator@0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&pio 130 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++ ++&pio { ++ pinctrl_uart2_default: uart2@0 { ++ pins { ++ pinmux = , ++ ; ++ }; ++ }; ++ ++ pinctrl_i2c0_default: i2c@0 { ++ pins { ++ pinmux = , ++ ; ++ }; ++ }; ++ ++ pinctrl_pcie_default: pcie@0 { ++ pins { ++ pinmux = , ++ , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ }; ++ }; ++ ++ pinctrl_spi_default: spi@0 { ++ pins { ++ pinmux = , ++ , ++ , ++ ; ++ bias-disable; ++ }; ++ }; ++}; ++ ++&thermal { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2_default>; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c0_default>; ++}; ++ ++&spi { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_spi_default>; ++ ++ m25p80@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "mx25l12805d"; ++ reg = <0 0 0 0>; ++ linux,modalias = "m25p80", "w25q128"; ++ spi-max-frequency = <10000000>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0 0x30000>; ++ read-only; ++ }; ++ ++ partition@30000 { ++ label = "u-boot-env"; ++ reg = <0x30000 0x10000>; ++ read-only; ++ }; ++ ++ factory: partition@40000 { ++ label = "factory"; ++ reg = <0x40000 0x10000>; ++ read-only; ++ }; ++ ++ partition@50000 { ++ label = "firmware"; ++ reg = <0x50000 0xfb0000>; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ status = "okay"; ++ ++// pinctrl-names = "default", "state_uhs"; ++// pinctrl-0 = <&mmc0_pins_default>; ++// pinctrl-1 = <&mmc0_pins_uhs>; ++ bus-width = <8>; ++ max-frequency = <50000000>; ++ cap-mmc-highspeed; ++// vmmc-supply = <&mt6397_vemc_3v3_reg>; ++// vqmmc-supply = <&mt6397_vio18_reg>; ++ non-removable; ++}; ++ ++&u3phy { ++ reg-p1-vbus-supply = <&usb_p1_vbus>; ++}; ++ ++&pcie { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pcie_default>; ++}; +diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi +new file mode 100644 +index 0000000..ba74ed9 +--- /dev/null ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -0,0 +1,348 @@ ++/* ++ * Copyright (c) 2014 MediaTek Inc. ++ * Author: Joe.C ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "skeleton64.dtsi" ++ ++/ { ++ compatible = "mediatek,mt7623"; ++ interrupt-parent = <&sysirq>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ enable-method = "mediatek,mt65xx-smp"; ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x0>; ++ }; ++ cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x1>; ++ }; ++ cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x2>; ++ }; ++ cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x3>; ++ }; ++ ++ }; ++ ++ clk26m: oscillator@0 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <26000000>; ++ clock-output-names = "clk26m"; ++ }; ++ ++ clk32k: oscillator@1 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <32000>; ++ clock-output-names = "clk32k"; ++ }; ++ ++ timer { ++ compatible = "arm,armv7-timer"; ++ interrupt-parent = <&gic>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <13000000>; ++ arm,cpu-registers-not-fw-configured; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu_thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <5000>; ++ ++ thermal-sensors = <&thermal 1>; ++ }; ++ }; ++ ++ soc { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ compatible = "simple-bus"; ++ ranges; ++ ++ topckgen: topckgen@10000000 { ++ compatible = "mediatek,mt7623-topckgen"; ++ reg = <0 0x10000000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ ++ infracfg: infracfg@10001000 { ++ compatible = "mediatek,mt7623-infracfg", "syscon"; ++ reg = <0 0x10001000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ pericfg: pericfg@10003000 { ++ compatible = "mediatek,mt7623-pericfg", "syscon"; ++ reg = <0 0x10003000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ /* ++ * Pinctrl access register at 0x10005000 through regmap. ++ * Register 0x1000b000 is used by EINT. ++ */ ++ pio: pinctrl@10005000 { ++ compatible = "mediatek,mt7623-pinctrl"; ++ reg = <0 0x1000b000 0 0x1000>; ++ mediatek,pctl-regmap = <&syscfg_pctl_a>; ++ pins-are-numbered; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupts = ; ++ }; ++ ++ syscfg_pctl_a: syscfg_pctl_a@10005000 { ++ compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; ++ reg = <0 0x10005000 0 0x1000>; ++ }; ++ ++ wdt: watchdog@10007000 { ++ compatible = "mediatek,mt7623-wdt", "mediatek,mt6589-wdt"; ++ reg = <0 0x10007000 0 0x18>; ++ }; ++ ++ timer: timer@10008000 { ++ compatible = "mediatek,mt7623-timer", ++ "mediatek,mt6577-timer"; ++ reg = <0 0x10008000 0 0x80>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_AXI_SEL>, ++ <&topckgen CLK_TOP_RTC_SEL>; ++ clock-names = "system-clk", "rtc-clk"; ++ }; ++ ++ sysirq: interrupt-controller@10200100 { ++ compatible = "mediatek,mt7623-sysirq", ++ "mediatek,mt6577-sysirq"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ reg = <0 0x10200100 0 0x1c>; ++ }; ++ ++ apmixedsys: apmixedsys@10209000 { ++ compatible = "mediatek,mt7623-apmixedsys"; ++ reg = <0 0x10209000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ ++ gic: interrupt-controller@10211000 { ++ compatible = "arm,cortex-a7-gic"; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupt-parent = <&gic>; ++ reg = <0 0x10211000 0 0x1000>, ++ <0 0x10212000 0 0x1000>, ++ <0 0x10214000 0 0x2000>, ++ <0 0x10216000 0 0x2000>; ++ }; ++ ++ auxadc: auxadc@11001000 { ++ compatible = "mediatek,mt7623-auxadc", "mediatek,mt8173-auxadc"; ++ reg = <0 0x11001000 0 0x1000>; ++ }; ++ ++ uart0: serial@11006000 { ++ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart"; ++ reg = <0 0x11002000 0 0x400>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; ++ clock-names = "baud", "bus"; ++ ++ status = "disabled"; ++ }; ++ ++ uart1: serial@11007000 { ++ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart"; ++ reg = <0 0x11003000 0 0x400>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; ++ clock-names = "baud", "bus"; ++ ++ status = "disabled"; ++ }; ++ ++ uart2: serial@11008000 { ++ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart"; ++ reg = <0 0x11004000 0 0x400>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; ++ clock-names = "baud", "bus"; ++ ++ status = "disabled"; ++ }; ++ ++ uart3: serial@11009000 { ++ compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart"; ++ reg = <0 0x11005000 0 0x400>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; ++ clock-names = "baud", "bus"; ++ ++ status = "disabled"; ++ }; ++ ++ spi: spi@1100a000 { ++ compatible = "medi/THEatek,mt7623-spi", "mediatek,mt6589-spi"; ++ reg = <0 0x1100a000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_SPI0>; ++ clock-names = "main"; ++ ++ status = "disabled"; ++ }; ++ ++ thermal: thermal@1100b000 { ++ #thermal-sensor-cells = <1>; ++ compatible = "mediatek,mt7623-thermal", "mediatek,mt8173-thermal"; ++ reg = <0 0x1100b000 0 0x1000>; ++ interrupts = <0 38 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; ++ clock-names = "therm", "auxadc"; ++ resets = <&pericfg MT7623_PERI_THERM_SW_RST>; ++ reset-names = "therm"; ++ auxadc = <&auxadc>; ++ apmixedsys = <&apmixedsys>; ++ ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@11007000 { ++ compatible = "mediatek,mt7623-i2c", "mediatek,mt6577-i2c"; ++ reg = <0 0x11007000 0 0x70>, ++ <0 0x11000300 0 0x80>; ++ interrupts = <0 44 IRQ_TYPE_LEVEL_LOW>; ++ clock-frequency = <400000>; ++ clock-div = <16>; ++ clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; ++ clock-names = "main", "dma"; ++ ++ status = "disabled"; ++ }; ++ ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7623-mmc", ++ "mediatek,mt8135-mmc"; ++ reg = <0 0x11230000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_MSDC20_1>, ++ <&topckgen CLK_TOP_MSDC30_0_SEL>; ++ clock-names = "source", "hclk"; ++ status = "disabled"; ++ }; ++ ++ usb: usb30@11270000 { ++ compatible = "mediatek,mt7623-xhci", "mediatek,mt8173-xhci", "generic-xhci"; ++ reg = <0 0x11270000 0 0x1000>; ++ interrupts = ; ++ usb-phy = <&u3phy>; ++ usb3-lpm-capable; ++ }; ++ ++ u3phy: usb-phy@11271000 { ++ compatible = "mediatek,mt7623-u3phy", "mediatek,mt8173-u3phy"; ++ reg = <0 0x11271000 0 0x3000>, ++ <0 0x11280000 0 0x20000>; ++// power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; ++// reg-vusb33-supply = <&mt6397_vusb_reg>; ++ clocks = <&pericfg CLK_PERI_USB0>, ++ <&pericfg CLK_PERI_USB1>, ++ <&topckgen CLK_TOP_USB20_SEL>; ++// <&apmixedsys CLK_APMIXED_REF2USB_TX>; ++ clock-names = "wakeup_deb_p0", ++ "wakeup_deb_p1", ++ "sys_mac"; ++// "u3phya_ref"; ++ disable-usb2-p1; ++ }; ++ }; ++ ++ ethernet@1B100000 { ++ compatible = "mediatek,mt7623-net"; ++ interrupts = <0 200 IRQ_TYPE_LEVEL_LOW>; ++ }; ++ ++ pcie: pcie@1a140000 { ++ compatible = "mediatek,mt7623-pcie"; ++ reg = <0 0x1a140000 0 0x10000>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ device_type = "pci"; ++ ++ bus-range = <0 255>; ++ ranges = < ++ 0x02000000 0 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ ++ 0x01000000 0 0 0x00000000 0x1A160000 0 0x00010000 /* io space */ ++ >; ++ ++ pcie0 { ++ reg = <0x0000 0 0 0 0>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ device_type = "pci"; ++ }; ++ ++ pcie1 { ++ reg = <0x0800 0 0 0 0>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ device_type = "pci"; ++ }; ++ ++ pcie2 { ++ reg = <0x1000 0 0 0 0>; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ device_type = "pci"; ++ }; ++ ++ status = "disabled"; ++ }; ++}; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0067-arm-mediatek-add-mt7623-support.patch b/target/linux/mediatek/patches/0067-arm-mediatek-add-mt7623-support.patch new file mode 100644 index 0000000..28193cc --- /dev/null +++ b/target/linux/mediatek/patches/0067-arm-mediatek-add-mt7623-support.patch @@ -0,0 +1,118 @@ +From 89556b1a4d98fbfe498c8f26e988cbb8266f7dfe Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 13:17:35 +0200 +Subject: [PATCH 67/76] arm: mediatek: add mt7623 support + +Signed-off-by: John Crispin +--- + arch/arm/mach-mediatek/Kconfig | 6 ++ + arch/arm/mach-mediatek/mediatek.c | 2 + + .../dt-bindings/reset-controller/mt7623-resets.h | 59 ++++++++++++++++++++ + 3 files changed, 67 insertions(+) + create mode 100644 include/dt-bindings/reset-controller/mt7623-resets.h + +diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig +index 7704818..5393d25 100644 +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -17,6 +17,12 @@ config MACH_MT6592 + bool "MediaTek MT6592 SoCs support" + default ARCH_MEDIATEK + ++config MACH_MT7623 ++ bool "MediaTek MT7623 SoCs support" ++ default ARCH_MEDIATEK ++ select ARCH_HAS_PCI ++ select PCI ++ + config MACH_MT8127 + bool "MediaTek MT8127 SoCs support" + default ARCH_MEDIATEK +diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c +index 6b38d67..ab8cf21 100644 +--- a/arch/arm/mach-mediatek/mediatek.c ++++ b/arch/arm/mach-mediatek/mediatek.c +@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(void) + void __iomem *gpt_base = 0; + + if (of_machine_is_compatible("mediatek,mt6589") || ++ of_machine_is_compatible("mediatek,mt7623") || + of_machine_is_compatible("mediatek,mt8135") || + of_machine_is_compatible("mediatek,mt8127")) { + /* turn on GPT6 which ungates arch timer clocks */ +@@ -48,6 +49,7 @@ static void __init mediatek_timer_init(void) + static const char * const mediatek_board_dt_compat[] = { + "mediatek,mt6589", + "mediatek,mt6592", ++ "mediatek,mt7623", + "mediatek,mt8127", + "mediatek,mt8135", + NULL, +diff --git a/include/dt-bindings/reset-controller/mt7623-resets.h b/include/dt-bindings/reset-controller/mt7623-resets.h +new file mode 100644 +index 0000000..28a7d69 +--- /dev/null ++++ b/include/dt-bindings/reset-controller/mt7623-resets.h +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (c) 2015 OpenWrt ++ * Author: John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7623 ++#define _DT_BINDINGS_RESET_CONTROLLER_MT7623 ++ ++/* INFRACFG resets */ ++#define MT7623_INFRA_EMI_REG_RST 0 ++#define MT7623_INFRA_DRAMC0_A0_RST 1 ++#define MT7623_INFRA_FHCTL_RST 2 ++#define MT7623_INFRA_APCIRQ_EINT_RST 3 ++#define MT7623_INFRA_APXGPT_RST 4 ++#define MT7623_INFRA_SCPSYS_RST 5 ++#define MT7623_INFRA_KP_RST 6 ++#define MT7623_INFRA_PMIC_WRAP_RST 7 ++#define MT7623_INFRA_MIPI_RST 8 ++#define MT7623_INFRA_IRRX_RST 9 ++#define MT7623_INFRA_CEC_RST 10 ++#define MT7623_INFRA_EMI_RST 32 ++#define MT7623_INFRA_DRAMC0_RST 34 ++#define MT7623_INFRA_SMI_RST 37 ++#define MT7623_INFRA_M4U_RST 38 ++ ++/* PERICFG resets */ ++#define MT7623_PERI_UART0_SW_RST 0 ++#define MT7623_PERI_UART1_SW_RST 1 ++#define MT7623_PERI_UART2_SW_RST 2 ++#define MT7623_PERI_UART3_SW_RST 3 ++#define MT7623_PERI_GCPU_SW_RST 5 ++#define MT7623_PERI_BTIF_SW_RST 6 ++#define MT7623_PERI_PWM_SW_RST 8 ++#define MT7623_PERI_AUXADC_SW_RST 10 ++#define MT7623_PERI_DMA_SW_RST 11 ++#define MT7623_PERI_NFI_SW_RST 14 ++#define MT7623_PERI_NLI_SW_RST 15 ++#define MT7623_PERI_THERM_SW_RST 16 ++#define MT7623_PERI_MSDC0_SW_RST 17 ++#define MT7623_PERI_MSDC1_SW_RST 19 ++#define MT7623_PERI_MSDC2_SW_RST 20 ++#define MT7623_PERI_I2C0_SW_RST 22 ++#define MT7623_PERI_I2C1_SW_RST 23 ++#define MT7623_PERI_I2C2_SW_RST 24 ++#define MT7623_PERI_I2C3_SW_RST 25 ++#define MT7623_PERI_USB_SW_RST 28 ++#define MT7623_PERI_ETH_SW_RST 29 ++#define MT7623_PERI_SPI0_SW_RST 33 ++ ++#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7623 */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0068-SDK_compat.patch b/target/linux/mediatek/patches/0068-SDK_compat.patch new file mode 100644 index 0000000..2800dbd --- /dev/null +++ b/target/linux/mediatek/patches/0068-SDK_compat.patch @@ -0,0 +1,1579 @@ +From 4c48177826502673737609ffa04b66051a1e0f75 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sat, 27 Jun 2015 17:05:12 +0200 +Subject: [PATCH 68/76] SDK_compat + +--- + arch/arm/include/asm/mach/mt_irq.h | 174 ++++++++ + arch/arm/include/asm/rt2880/mt_irq.h | 174 ++++++++ + arch/arm/include/asm/rt2880/rt_mmap.h | 58 +++ + arch/arm/include/asm/rt2880/surfboardint.h | 42 ++ + arch/arm/include/asm/rt2880/x_define_irq.h | 160 +++++++ + arch/arm/mach-mediatek/mediatek.c | 186 ++++++++ + arch/arm/mach-mediatek/mt_reg_base.h | 640 ++++++++++++++++++++++++++++ + arch/arm/mach-mediatek/rt_mmap.h | 58 +++ + 8 files changed, 1492 insertions(+) + create mode 100644 arch/arm/include/asm/mach/mt_irq.h + create mode 100644 arch/arm/include/asm/rt2880/mt_irq.h + create mode 100644 arch/arm/include/asm/rt2880/rt_mmap.h + create mode 100644 arch/arm/include/asm/rt2880/surfboardint.h + create mode 100644 arch/arm/include/asm/rt2880/x_define_irq.h + create mode 100644 arch/arm/mach-mediatek/mt_reg_base.h + create mode 100644 arch/arm/mach-mediatek/rt_mmap.h + +diff --git a/arch/arm/include/asm/mach/mt_irq.h b/arch/arm/include/asm/mach/mt_irq.h +new file mode 100644 +index 0000000..ff265e0 +--- /dev/null ++++ b/arch/arm/include/asm/mach/mt_irq.h +@@ -0,0 +1,174 @@ ++#ifndef __MT_IRQ_H ++#define __MT_IRQ_H ++ ++#define GIC_PRIVATE_SIGNALS (32) ++#define NR_GIC_SGI (16) ++#define NR_GIC_PPI (16) ++#define GIC_PPI_OFFSET (27) ++#define MT_NR_PPI (5) ++#define MT_NR_SPI (224) ++#define NR_MT_IRQ_LINE (GIC_PPI_OFFSET + MT_NR_PPI + MT_NR_SPI) ++ ++#define MT65xx_EDGE_SENSITIVE 0 ++#define MT65xx_LEVEL_SENSITIVE 1 ++ ++#define MT65xx_POLARITY_LOW 0 ++#define MT65xx_POLARITY_HIGH 1 ++ ++#define GIC_PPI_GLOBAL_TIMER (GIC_PPI_OFFSET + 0) ++#define GIC_PPI_LEGACY_FIQ (GIC_PPI_OFFSET + 1) ++#define GIC_PPI_PRIVATE_TIMER (GIC_PPI_OFFSET + 2) ++#define GIC_PPI_NS_PRIVATE_TIMER (GIC_PPI_OFFSET + 3) ++#define GIC_PPI_LEGACY_IRQ (GIC_PPI_OFFSET + 4) ++ ++#define MT_BTIF_IRQ_ID (GIC_PRIVATE_SIGNALS + 50) ++#define MT_DMA_BTIF_TX_IRQ_ID (GIC_PRIVATE_SIGNALS + 71) ++#define MT_DMA_BTIF_RX_IRQ_ID (GIC_PRIVATE_SIGNALS + 72) ++ ++#if !defined(CONFIG_MT8127_FPGA) ++ ++#if !defined(__ASSEMBLY__) ++#define X_DEFINE_IRQ(__name, __num, __pol, __sens) __name = __num, ++enum ++{ ++#include "x_define_irq.h" ++}; ++#undef X_DEFINE_IRQ ++#define MT6582_AHB_SLAVE_HIF_IRQ_ID WF_HIF_IRQ_ID /* FIXME */ ++ ++#endif ++ ++#else ++ ++#define MT6582_USB0_IRQ_ID (GIC_PRIVATE_SIGNALS + 32) ++#define MT6582_USB1_IRQ_ID (GIC_PRIVATE_SIGNALS + 33) ++#define MT_PTP_THERM_IRQ_ID (GIC_PRIVATE_SIGNALS + 38) ++#define MT_MSDC0_IRQ_ID (GIC_PRIVATE_SIGNALS + 39) ++#define MT_MSDC1_IRQ_ID (GIC_PRIVATE_SIGNALS + 40) ++//#define MT_MSDC2_IRQ_ID (GIC_PRIVATE_SIGNALS + 41) //6582 take off ++//#define MT_MSDC3_IRQ_ID (GIC_PRIVATE_SIGNALS + 42) //6582 take off ++#define MT6582_AP_HIF_IRQ_ID (GIC_PRIVATE_SIGNALS + 43) ++#define MT_I2C0_IRQ_ID (GIC_PRIVATE_SIGNALS + 44) ++#define MT_I2C1_IRQ_ID (GIC_PRIVATE_SIGNALS + 45) ++#define MT_I2C2_IRQ_ID (GIC_PRIVATE_SIGNALS + 46) ++#define MT_UART1_IRQ_ID (GIC_PRIVATE_SIGNALS + 51) ++#define MT_UART2_IRQ_ID (GIC_PRIVATE_SIGNALS + 52) ++#define MT_UART3_IRQ_ID (GIC_PRIVATE_SIGNALS + 53) ++#define MT_UART4_IRQ_ID (GIC_PRIVATE_SIGNALS + 54) ++#define MT_NFIECC_IRQ_ID (GIC_PRIVATE_SIGNALS + 55) ++#define MT_NFI_IRQ_ID (GIC_PRIVATE_SIGNALS + 56) ++#define MT_GDMA1_IRQ_ID (GIC_PRIVATE_SIGNALS + 57) ++#define MT_GDMA2_IRQ_ID (GIC_PRIVATE_SIGNALS + 58) ++#define MT_DMA_UART0_TX_IRQ_ID (GIC_PRIVATE_SIGNALS + 63) ++#define MT_DMA_UART0_RX_IRQ_ID (GIC_PRIVATE_SIGNALS + 64) ++#define MT_DMA_UART1_TX_IRQ_ID (GIC_PRIVATE_SIGNALS + 65) ++#define MT_DMA_UART1_RX_IRQ_ID (GIC_PRIVATE_SIGNALS + 66) ++#define MT_DMA_UART2_TX_IRQ_ID (GIC_PRIVATE_SIGNALS + 67) ++#define MT_DMA_UART2_RX_IRQ_ID (GIC_PRIVATE_SIGNALS + 68) ++#define MT6582_SPI1_IRQ_ID (GIC_PRIVATE_SIGNALS + 78) ++//#define MT_MSDC4_IRQ_ID (GIC_PRIVATE_SIGNALS + 83) //6582 take off ++#define MT_PTP_FSM_IRQ_ID (GIC_PRIVATE_SIGNALS + 85) ++#define MT_WDT_IRQ_ID (GIC_PRIVATE_SIGNALS + 88)//TBD:For build pass ++#define MT_APARM_DOMAIN_IRQ_ID (GIC_PRIVATE_SIGNALS + 94) ++#define MT_APARM_DECERR_IRQ_ID (GIC_PRIVATE_SIGNALS + 95) ++#if 1 //cliff ++#define MT6582_GPT_IRQ_ID (GIC_PRIVATE_SIGNALS + 112)//10.2 update ++#define MT_EINT_IRQ_ID (GIC_PRIVATE_SIGNALS + 113)//10.2 update ++#else ++#define MT6582_GPT_IRQ_ID (GIC_PRIVATE_SIGNALS + 113)//10.2 update ++#define MT_EINT_IRQ_ID (GIC_PRIVATE_SIGNALS + 116)//10.2 update ++#endif ++#define MT6582_PMIC_WRAP_IRQ_ID (GIC_PRIVATE_SIGNALS + 115)//0x80 ++#define MT_KP_IRQ_ID (GIC_PRIVATE_SIGNALS + 116) ++#define MT_SPM_IRQ_ID (GIC_PRIVATE_SIGNALS + 117) ++#define MT_SPM1_IRQ_ID (GIC_PRIVATE_SIGNALS + 118) ++#define MT_VENC_IRQ_ID (GIC_PRIVATE_SIGNALS + 139) ++#define MT_VDEC_IRQ_ID (GIC_PRIVATE_SIGNALS + 140) ++#define CAMERA_ISP_IRQ0_ID (GIC_PRIVATE_SIGNALS + 143) // cam_irq_b ++#define CAMERA_ISP_IRQ1_ID (GIC_PRIVATE_SIGNALS + 144) // cam_irq1_b ++#define CAMERA_ISP_IRQ2_ID (GIC_PRIVATE_SIGNALS + 145) // cam_irq2_b ++//#define CAMERA_ISP_IRQ3_ID (GIC_PRIVATE_SIGNALS + 144) // cam_irq3_b 6582 take off ++#define MT6582_JPEG_ENC_IRQ_ID (GIC_PRIVATE_SIGNALS + 141) ++//#define MT6582_JPEG_DEC_IRQ_ID (GIC_PRIVATE_SIGNALS + 148) //6582 take off ++/* Not sure and comments for early porting */ ++#define MT_EINT_DIRECT0_IRQ_ID (GIC_PRIVATE_SIGNALS + 121) ++ ++#if 0 ++#define MT_MFG_IRQ_GP_ID (GIC_PRIVATE_SIGNALS + 170) ++#define MT_MFG_IRQ_GPMMU_ID (GIC_PRIVATE_SIGNALS + 171) ++#define MT_MFG_IRQ_PP0_ID (GIC_PRIVATE_SIGNALS + 172) ++#define MT_MFG_IRQ_PPMMU0_ID (GIC_PRIVATE_SIGNALS + 173) ++#define MT_MFG_IRQ_PP1_ID (GIC_PRIVATE_SIGNALS + 174) ++#define MT_MFG_IRQ_PPMMU1_ID (GIC_PRIVATE_SIGNALS + 175) ++#else ++#define MT_MFG_IRQ0_ID (GIC_PRIVATE_SIGNALS + 170) ++#define MT_MFG_IRQ1_ID (GIC_PRIVATE_SIGNALS + 171) ++#define MT_MFG_IRQ2_ID (GIC_PRIVATE_SIGNALS + 172) ++#define MT_MFG_IRQ3_ID (GIC_PRIVATE_SIGNALS + 173) ++#define MT_MFG_IRQ4_ID (GIC_PRIVATE_SIGNALS + 174) ++#define MT_MFG_IRQ5_ID (GIC_PRIVATE_SIGNALS + 175) ++#define MT_MFG_IRQ6_ID (GIC_PRIVATE_SIGNALS + 176) ++#define MT_MFG_IRQ7_ID (GIC_PRIVATE_SIGNALS + 177) ++#define MT_MFG_IRQ8_ID (GIC_PRIVATE_SIGNALS + 178) ++#define MT_MFG_IRQ9_ID (GIC_PRIVATE_SIGNALS + 179) ++#define MT_MFG_IRQ10_ID (GIC_PRIVATE_SIGNALS + 180) ++#endif ++ ++ ++#if 0 ++#define MT6582_DISP_MUTEX_IRQ_ID (GIC_PRIVATE_SIGNALS + 160) ++#define MT6582_DISP_ROT_IRQ_ID (GIC_PRIVATE_SIGNALS + 161) ++#define MT6582_DISP_SCL_IRQ_ID (GIC_PRIVATE_SIGNALS + 162) ++#define MT6582_DISP_OVL_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++#define MT6582_DISP_WDMA0_IRQ_ID (GIC_PRIVATE_SIGNALS + 164) ++#define MT6582_DISP_WDMA1_IRQ_ID (GIC_PRIVATE_SIGNALS + 165) ++#define MT6582_DISP_RDMA0_IRQ_ID (GIC_PRIVATE_SIGNALS + 166) ++#define MT6582_DISP_RDMA1_IRQ_ID (GIC_PRIVATE_SIGNALS + 167) ++#define MT6582_DISP_BLS_IRQ_ID (GIC_PRIVATE_SIGNALS + 168) ++#define MT6582_DISP_COLOR_IRQ_ID (GIC_PRIVATE_SIGNALS + 169) ++#define MT6582_DISP_TDSHP_IRQ_ID (GIC_PRIVATE_SIGNALS + 170) ++#define MT6582_DISP_DBI_IRQ_ID (GIC_PRIVATE_SIGNALS + 171) ++#define MT6582_DISP_DSI_IRQ_ID (GIC_PRIVATE_SIGNALS + 172) ++#define MT6582_DISP_DPI0_IRQ_ID (GIC_PRIVATE_SIGNALS + 173) ++#define MT6582_DISP_DPI1_IRQ_ID (GIC_PRIVATE_SIGNALS + 174) ++#define MT6582_DISP_CMDQ_IRQ_ID (GIC_PRIVATE_SIGNALS + 176) ++#else ++#define MT6582_DISP_MDP_RDMA_IRQ_ID (GIC_PRIVATE_SIGNALS+146) ++#define MT6582_DISP_MDP_RSZ0_IRQ_ID (GIC_PRIVATE_SIGNALS+147) ++#define MT6582_DISP_MDP_RSZ1_IRQ_ID (GIC_PRIVATE_SIGNALS+148) ++#define MT6582_DISP_MDP_TDSHP_IRQ_ID (GIC_PRIVATE_SIGNALS+149) ++#define MT6582_DISP_MDP_WDMA_IRQ_ID (GIC_PRIVATE_SIGNALS+150) ++#define MT6582_DISP_MDP_WROT_IRQ_ID (GIC_PRIVATE_SIGNALS+151) ++#define MT6582_DISP_RDMA_IRQ_ID (GIC_PRIVATE_SIGNALS+152) ++#define MT6582_DISP_OVL_IRQ_ID (GIC_PRIVATE_SIGNALS+153) ++#define MT6582_DISP_WDMA_IRQ_ID (GIC_PRIVATE_SIGNALS+154) ++#define MT6582_DISP_BLS_IRQ_ID (GIC_PRIVATE_SIGNALS+155) ++#define MT6582_DISP_COLOR_IRQ_ID (GIC_PRIVATE_SIGNALS+156) ++#define MT6582_DISP_DSI_IRQ_ID (GIC_PRIVATE_SIGNALS+157) ++#define MT6582_DISP_DPI0_IRQ_ID (GIC_PRIVATE_SIGNALS+158) ++#define MT6582_DISP_CMDQ_IRQ_ID (GIC_PRIVATE_SIGNALS+159) ++#define MT6582_DISP_CMDQ_SECURE_IRQ_ID (GIC_PRIVATE_SIGNALS+160) ++#define MT6582_DISP_MUTEX_IRQ_ID (GIC_PRIVATE_SIGNALS+161) ++#define MT6582_DISP_SMI_LARB0_IRQ_ID (GIC_PRIVATE_SIGNALS+162) ++#define MT_CIRQ_IRQ_ID (GIC_PRIVATE_SIGNALS+187) ++#endif ++#define MT6582_APARM_GPTTIMER_IRQ_LINE MT6582_GPT_IRQ_ID ++ ++// MT6582 Wifi AHB Slave HIF ++#define MT6582_AHB_SLAVE_HIF_IRQ_ID (GIC_PRIVATE_SIGNALS + 160) ++#define MT6582_HIF_PDMA_IRQ_ID (GIC_PRIVATE_SIGNALS + 59) ++ ++/* These are defined for solving compile errors only. They are not existing on FPGA */ ++#define TS_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++#define CONN_WDT_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++#define LOWBATTERY_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++#define MD_WDT_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++ ++#define WF_HIF_IRQ_ID (GIC_PRIVATE_SIGNALS + 184) ++#define MT_CONN2AP_BTIF_WAKEUP_IRQ_ID (GIC_PRIVATE_SIGNALS + 185) ++#define BT_CVSD_IRQ_ID (GIC_PRIVATE_SIGNALS + 186) ++ ++#define CCIF0_AP_IRQ_ID (GIC_PRIVATE_SIGNALS + 100) ++#endif ++ ++#endif +diff --git a/arch/arm/include/asm/rt2880/mt_irq.h b/arch/arm/include/asm/rt2880/mt_irq.h +new file mode 100644 +index 0000000..ff265e0 +--- /dev/null ++++ b/arch/arm/include/asm/rt2880/mt_irq.h +@@ -0,0 +1,174 @@ ++#ifndef __MT_IRQ_H ++#define __MT_IRQ_H ++ ++#define GIC_PRIVATE_SIGNALS (32) ++#define NR_GIC_SGI (16) ++#define NR_GIC_PPI (16) ++#define GIC_PPI_OFFSET (27) ++#define MT_NR_PPI (5) ++#define MT_NR_SPI (224) ++#define NR_MT_IRQ_LINE (GIC_PPI_OFFSET + MT_NR_PPI + MT_NR_SPI) ++ ++#define MT65xx_EDGE_SENSITIVE 0 ++#define MT65xx_LEVEL_SENSITIVE 1 ++ ++#define MT65xx_POLARITY_LOW 0 ++#define MT65xx_POLARITY_HIGH 1 ++ ++#define GIC_PPI_GLOBAL_TIMER (GIC_PPI_OFFSET + 0) ++#define GIC_PPI_LEGACY_FIQ (GIC_PPI_OFFSET + 1) ++#define GIC_PPI_PRIVATE_TIMER (GIC_PPI_OFFSET + 2) ++#define GIC_PPI_NS_PRIVATE_TIMER (GIC_PPI_OFFSET + 3) ++#define GIC_PPI_LEGACY_IRQ (GIC_PPI_OFFSET + 4) ++ ++#define MT_BTIF_IRQ_ID (GIC_PRIVATE_SIGNALS + 50) ++#define MT_DMA_BTIF_TX_IRQ_ID (GIC_PRIVATE_SIGNALS + 71) ++#define MT_DMA_BTIF_RX_IRQ_ID (GIC_PRIVATE_SIGNALS + 72) ++ ++#if !defined(CONFIG_MT8127_FPGA) ++ ++#if !defined(__ASSEMBLY__) ++#define X_DEFINE_IRQ(__name, __num, __pol, __sens) __name = __num, ++enum ++{ ++#include "x_define_irq.h" ++}; ++#undef X_DEFINE_IRQ ++#define MT6582_AHB_SLAVE_HIF_IRQ_ID WF_HIF_IRQ_ID /* FIXME */ ++ ++#endif ++ ++#else ++ ++#define MT6582_USB0_IRQ_ID (GIC_PRIVATE_SIGNALS + 32) ++#define MT6582_USB1_IRQ_ID (GIC_PRIVATE_SIGNALS + 33) ++#define MT_PTP_THERM_IRQ_ID (GIC_PRIVATE_SIGNALS + 38) ++#define MT_MSDC0_IRQ_ID (GIC_PRIVATE_SIGNALS + 39) ++#define MT_MSDC1_IRQ_ID (GIC_PRIVATE_SIGNALS + 40) ++//#define MT_MSDC2_IRQ_ID (GIC_PRIVATE_SIGNALS + 41) //6582 take off ++//#define MT_MSDC3_IRQ_ID (GIC_PRIVATE_SIGNALS + 42) //6582 take off ++#define MT6582_AP_HIF_IRQ_ID (GIC_PRIVATE_SIGNALS + 43) ++#define MT_I2C0_IRQ_ID (GIC_PRIVATE_SIGNALS + 44) ++#define MT_I2C1_IRQ_ID (GIC_PRIVATE_SIGNALS + 45) ++#define MT_I2C2_IRQ_ID (GIC_PRIVATE_SIGNALS + 46) ++#define MT_UART1_IRQ_ID (GIC_PRIVATE_SIGNALS + 51) ++#define MT_UART2_IRQ_ID (GIC_PRIVATE_SIGNALS + 52) ++#define MT_UART3_IRQ_ID (GIC_PRIVATE_SIGNALS + 53) ++#define MT_UART4_IRQ_ID (GIC_PRIVATE_SIGNALS + 54) ++#define MT_NFIECC_IRQ_ID (GIC_PRIVATE_SIGNALS + 55) ++#define MT_NFI_IRQ_ID (GIC_PRIVATE_SIGNALS + 56) ++#define MT_GDMA1_IRQ_ID (GIC_PRIVATE_SIGNALS + 57) ++#define MT_GDMA2_IRQ_ID (GIC_PRIVATE_SIGNALS + 58) ++#define MT_DMA_UART0_TX_IRQ_ID (GIC_PRIVATE_SIGNALS + 63) ++#define MT_DMA_UART0_RX_IRQ_ID (GIC_PRIVATE_SIGNALS + 64) ++#define MT_DMA_UART1_TX_IRQ_ID (GIC_PRIVATE_SIGNALS + 65) ++#define MT_DMA_UART1_RX_IRQ_ID (GIC_PRIVATE_SIGNALS + 66) ++#define MT_DMA_UART2_TX_IRQ_ID (GIC_PRIVATE_SIGNALS + 67) ++#define MT_DMA_UART2_RX_IRQ_ID (GIC_PRIVATE_SIGNALS + 68) ++#define MT6582_SPI1_IRQ_ID (GIC_PRIVATE_SIGNALS + 78) ++//#define MT_MSDC4_IRQ_ID (GIC_PRIVATE_SIGNALS + 83) //6582 take off ++#define MT_PTP_FSM_IRQ_ID (GIC_PRIVATE_SIGNALS + 85) ++#define MT_WDT_IRQ_ID (GIC_PRIVATE_SIGNALS + 88)//TBD:For build pass ++#define MT_APARM_DOMAIN_IRQ_ID (GIC_PRIVATE_SIGNALS + 94) ++#define MT_APARM_DECERR_IRQ_ID (GIC_PRIVATE_SIGNALS + 95) ++#if 1 //cliff ++#define MT6582_GPT_IRQ_ID (GIC_PRIVATE_SIGNALS + 112)//10.2 update ++#define MT_EINT_IRQ_ID (GIC_PRIVATE_SIGNALS + 113)//10.2 update ++#else ++#define MT6582_GPT_IRQ_ID (GIC_PRIVATE_SIGNALS + 113)//10.2 update ++#define MT_EINT_IRQ_ID (GIC_PRIVATE_SIGNALS + 116)//10.2 update ++#endif ++#define MT6582_PMIC_WRAP_IRQ_ID (GIC_PRIVATE_SIGNALS + 115)//0x80 ++#define MT_KP_IRQ_ID (GIC_PRIVATE_SIGNALS + 116) ++#define MT_SPM_IRQ_ID (GIC_PRIVATE_SIGNALS + 117) ++#define MT_SPM1_IRQ_ID (GIC_PRIVATE_SIGNALS + 118) ++#define MT_VENC_IRQ_ID (GIC_PRIVATE_SIGNALS + 139) ++#define MT_VDEC_IRQ_ID (GIC_PRIVATE_SIGNALS + 140) ++#define CAMERA_ISP_IRQ0_ID (GIC_PRIVATE_SIGNALS + 143) // cam_irq_b ++#define CAMERA_ISP_IRQ1_ID (GIC_PRIVATE_SIGNALS + 144) // cam_irq1_b ++#define CAMERA_ISP_IRQ2_ID (GIC_PRIVATE_SIGNALS + 145) // cam_irq2_b ++//#define CAMERA_ISP_IRQ3_ID (GIC_PRIVATE_SIGNALS + 144) // cam_irq3_b 6582 take off ++#define MT6582_JPEG_ENC_IRQ_ID (GIC_PRIVATE_SIGNALS + 141) ++//#define MT6582_JPEG_DEC_IRQ_ID (GIC_PRIVATE_SIGNALS + 148) //6582 take off ++/* Not sure and comments for early porting */ ++#define MT_EINT_DIRECT0_IRQ_ID (GIC_PRIVATE_SIGNALS + 121) ++ ++#if 0 ++#define MT_MFG_IRQ_GP_ID (GIC_PRIVATE_SIGNALS + 170) ++#define MT_MFG_IRQ_GPMMU_ID (GIC_PRIVATE_SIGNALS + 171) ++#define MT_MFG_IRQ_PP0_ID (GIC_PRIVATE_SIGNALS + 172) ++#define MT_MFG_IRQ_PPMMU0_ID (GIC_PRIVATE_SIGNALS + 173) ++#define MT_MFG_IRQ_PP1_ID (GIC_PRIVATE_SIGNALS + 174) ++#define MT_MFG_IRQ_PPMMU1_ID (GIC_PRIVATE_SIGNALS + 175) ++#else ++#define MT_MFG_IRQ0_ID (GIC_PRIVATE_SIGNALS + 170) ++#define MT_MFG_IRQ1_ID (GIC_PRIVATE_SIGNALS + 171) ++#define MT_MFG_IRQ2_ID (GIC_PRIVATE_SIGNALS + 172) ++#define MT_MFG_IRQ3_ID (GIC_PRIVATE_SIGNALS + 173) ++#define MT_MFG_IRQ4_ID (GIC_PRIVATE_SIGNALS + 174) ++#define MT_MFG_IRQ5_ID (GIC_PRIVATE_SIGNALS + 175) ++#define MT_MFG_IRQ6_ID (GIC_PRIVATE_SIGNALS + 176) ++#define MT_MFG_IRQ7_ID (GIC_PRIVATE_SIGNALS + 177) ++#define MT_MFG_IRQ8_ID (GIC_PRIVATE_SIGNALS + 178) ++#define MT_MFG_IRQ9_ID (GIC_PRIVATE_SIGNALS + 179) ++#define MT_MFG_IRQ10_ID (GIC_PRIVATE_SIGNALS + 180) ++#endif ++ ++ ++#if 0 ++#define MT6582_DISP_MUTEX_IRQ_ID (GIC_PRIVATE_SIGNALS + 160) ++#define MT6582_DISP_ROT_IRQ_ID (GIC_PRIVATE_SIGNALS + 161) ++#define MT6582_DISP_SCL_IRQ_ID (GIC_PRIVATE_SIGNALS + 162) ++#define MT6582_DISP_OVL_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++#define MT6582_DISP_WDMA0_IRQ_ID (GIC_PRIVATE_SIGNALS + 164) ++#define MT6582_DISP_WDMA1_IRQ_ID (GIC_PRIVATE_SIGNALS + 165) ++#define MT6582_DISP_RDMA0_IRQ_ID (GIC_PRIVATE_SIGNALS + 166) ++#define MT6582_DISP_RDMA1_IRQ_ID (GIC_PRIVATE_SIGNALS + 167) ++#define MT6582_DISP_BLS_IRQ_ID (GIC_PRIVATE_SIGNALS + 168) ++#define MT6582_DISP_COLOR_IRQ_ID (GIC_PRIVATE_SIGNALS + 169) ++#define MT6582_DISP_TDSHP_IRQ_ID (GIC_PRIVATE_SIGNALS + 170) ++#define MT6582_DISP_DBI_IRQ_ID (GIC_PRIVATE_SIGNALS + 171) ++#define MT6582_DISP_DSI_IRQ_ID (GIC_PRIVATE_SIGNALS + 172) ++#define MT6582_DISP_DPI0_IRQ_ID (GIC_PRIVATE_SIGNALS + 173) ++#define MT6582_DISP_DPI1_IRQ_ID (GIC_PRIVATE_SIGNALS + 174) ++#define MT6582_DISP_CMDQ_IRQ_ID (GIC_PRIVATE_SIGNALS + 176) ++#else ++#define MT6582_DISP_MDP_RDMA_IRQ_ID (GIC_PRIVATE_SIGNALS+146) ++#define MT6582_DISP_MDP_RSZ0_IRQ_ID (GIC_PRIVATE_SIGNALS+147) ++#define MT6582_DISP_MDP_RSZ1_IRQ_ID (GIC_PRIVATE_SIGNALS+148) ++#define MT6582_DISP_MDP_TDSHP_IRQ_ID (GIC_PRIVATE_SIGNALS+149) ++#define MT6582_DISP_MDP_WDMA_IRQ_ID (GIC_PRIVATE_SIGNALS+150) ++#define MT6582_DISP_MDP_WROT_IRQ_ID (GIC_PRIVATE_SIGNALS+151) ++#define MT6582_DISP_RDMA_IRQ_ID (GIC_PRIVATE_SIGNALS+152) ++#define MT6582_DISP_OVL_IRQ_ID (GIC_PRIVATE_SIGNALS+153) ++#define MT6582_DISP_WDMA_IRQ_ID (GIC_PRIVATE_SIGNALS+154) ++#define MT6582_DISP_BLS_IRQ_ID (GIC_PRIVATE_SIGNALS+155) ++#define MT6582_DISP_COLOR_IRQ_ID (GIC_PRIVATE_SIGNALS+156) ++#define MT6582_DISP_DSI_IRQ_ID (GIC_PRIVATE_SIGNALS+157) ++#define MT6582_DISP_DPI0_IRQ_ID (GIC_PRIVATE_SIGNALS+158) ++#define MT6582_DISP_CMDQ_IRQ_ID (GIC_PRIVATE_SIGNALS+159) ++#define MT6582_DISP_CMDQ_SECURE_IRQ_ID (GIC_PRIVATE_SIGNALS+160) ++#define MT6582_DISP_MUTEX_IRQ_ID (GIC_PRIVATE_SIGNALS+161) ++#define MT6582_DISP_SMI_LARB0_IRQ_ID (GIC_PRIVATE_SIGNALS+162) ++#define MT_CIRQ_IRQ_ID (GIC_PRIVATE_SIGNALS+187) ++#endif ++#define MT6582_APARM_GPTTIMER_IRQ_LINE MT6582_GPT_IRQ_ID ++ ++// MT6582 Wifi AHB Slave HIF ++#define MT6582_AHB_SLAVE_HIF_IRQ_ID (GIC_PRIVATE_SIGNALS + 160) ++#define MT6582_HIF_PDMA_IRQ_ID (GIC_PRIVATE_SIGNALS + 59) ++ ++/* These are defined for solving compile errors only. They are not existing on FPGA */ ++#define TS_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++#define CONN_WDT_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++#define LOWBATTERY_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++#define MD_WDT_IRQ_ID (GIC_PRIVATE_SIGNALS + 163) ++ ++#define WF_HIF_IRQ_ID (GIC_PRIVATE_SIGNALS + 184) ++#define MT_CONN2AP_BTIF_WAKEUP_IRQ_ID (GIC_PRIVATE_SIGNALS + 185) ++#define BT_CVSD_IRQ_ID (GIC_PRIVATE_SIGNALS + 186) ++ ++#define CCIF0_AP_IRQ_ID (GIC_PRIVATE_SIGNALS + 100) ++#endif ++ ++#endif +diff --git a/arch/arm/include/asm/rt2880/rt_mmap.h b/arch/arm/include/asm/rt2880/rt_mmap.h +new file mode 100644 +index 0000000..e86b3bb +--- /dev/null ++++ b/arch/arm/include/asm/rt2880/rt_mmap.h +@@ -0,0 +1,58 @@ ++#define HIFSYS_BASE 0xFA000000 //for PCIe/USB ++#define ETHDMASYS_BASE 0xFB000000 //for I2S/PCM/GDMA/HSDMA/FE/GMAC ++ ++#define HIFSYS_PCI_BASE 0xFA140000 ++#define HIFSYS_USB_HOST_BASE 0xFA1C0000 ++#define HIFSYS_USB_HOST2_BASE 0xFA240000 ++ ++#define ETHDMASYS_SYSCTL_BASE 0xFB000000 ++#define ETHDMASYS_RBUS_MATRIXCTL_BASE 0xFB000400 ++#define ETHDMASYS_I2S_BASE 0xFB000A00 ++#define ETHDMASYS_PCM_BASE 0xFB002000 ++#define ETHDMASYS_GDMA_BASE 0xFB002800 ++#define ETHDMASYS_HS_DMA_BASE 0xFB007000 ++#define ETHDMASYS_FRAME_ENGINE_BASE 0xFB100000 ++#define ETHDMASYS_PPE_BASE 0xFB100C00 ++#define ETHDMASYS_ETH_SW_BASE 0xFB110000 ++#define ETHDMASYS_CRYPTO_ENGINE_BASE 0xFB240000 ++ ++//for backward-compatible ++#define RALINK_FRAME_ENGINE_BASE ETHDMASYS_FRAME_ENGINE_BASE ++#define RALINK_PPE_BASE ETHDMASYS_PPE_BASE ++#define RALINK_SYSCTL_BASE ETHDMASYS_SYSCTL_BASE ++#define RALINK_ETH_SW_BASE ETHDMASYS_ETH_SW_BASE ++#define RALINK_GDMA_BASE ETHDMASYS_GDMA_BASE ++#define RALINK_HS_DMA_BASE ETHDMASYS_HS_DMA_BASE ++#define RALINK_11N_MAC_BASE 0 //unused for rt_rdm usage ++ ++//Reset Control Register ++#define RSTCTL_SYS_RST (1<<0) ++#define RSTCTL_MCM_RST (1<<2) ++#define RSTCTL_HSDMA_RST (1<<5) ++#define RSTCTL_FE_RST (1<<6) ++#define RSTCTL_SPDIF_RST (1<<7) ++#define RSTCTL_TIMER_RST (1<<8) ++#define RSTCTL_CIRQ_RST (1<<9) ++#define RSTCTL_MC_RST (1<<10) ++#define RSTCTL_PCM_RST (1<<11) ++#define RSTCTL_GPIO_RST (1<<13) ++#define RSTCTL_GDMA_RST (1<<14) ++#define RSTCTL_NAND_RST (1<<15) ++#define RSTCTL_I2C_RST (1<<16) ++#define RSTCTL_I2S_RST (1<<17) ++#define RSTCTL_SPI_RST (1<<18) ++#define RSTCTL_UART0_RST (1<<19) ++#define RSTCTL_UART1_RST (1<<20) ++#define RSTCTL_UART2_RST (1<<21) ++#define RSTCTL_UPHY_RST (1<<22) ++#define RSTCTL_ETH_RST (1<<23) ++#define RSTCTL_PCIE0_RST (1<<24) ++#define RSTCTL_PCIE1_RST (1<<25) ++#define RSTCTL_PCIE2_RST (1<<26) ++#define RSTCTL_AUX_STCK_RST (1<<28) ++#define RSTCTL_CRYPT_RST (1<<29) ++#define RSTCTL_SDXC_RST (1<<30) ++#define RSTCTL_PWM_RST (1<<31) ++ ++//for backward-compatible ++#define RALINK_FE_RST RSTCTL_FE_RST +diff --git a/arch/arm/include/asm/rt2880/surfboardint.h b/arch/arm/include/asm/rt2880/surfboardint.h +new file mode 100644 +index 0000000..4581598 +--- /dev/null ++++ b/arch/arm/include/asm/rt2880/surfboardint.h +@@ -0,0 +1,42 @@ ++#include "mt_irq.h" ++ ++//#define SURFBOARDINT_SYSCTL 0 /* SYSCTL */ ++#define SURFBOARDINT_FE MT_FE_ORIG_IRQ_ID /* FE */ ++#define SURFBOARDINT_PCM MT_PCM_IRQ_ID /* PCM */ ++//#define SURFBOARDINT_GPIO 6 /* GPIO */ ++#define SURFBOARDINT_HSGDMA MT_HSDMA_IRQ_ID /* HSGDMA */ ++#define SURFBOARDINT_DMA MT_GDMA_IRQ_ID /* DMA */ ++//#define SURFBOARDINT_PC 9 /* Performance counter */ ++#define SURFBOARDINT_I2S MT_I2S_IRQ_ID /* I2S */ ++//#define SURFBOARDINT_SPI 11 /* SPI */ ++//#define SURFBOARDINT_AES 13 /* AES */ ++//#define SURFBOARDINT_AESENGINE 13 /* AES Engine */ ++#define SURFBOARDINT_CRYPTO MT_CRYPTO_IRQ_ID /* CryptoEngine */ ++//#define SURFBOARDINT_SDXC 14 /* SDXC */ ++//#define SURFBOARDINT_ESW 17 /* ESW */ ++#define SURFBOARDINT_USB0 MT_SSUSB_XHCI0_IRQ_ID /* USB0 */ ++#define SURFBOARDINT_USB1 MT_SSUSB_XHCI1_IRQ_ID /* USB1 */ ++//#define SURFBOARDINT_UART_LITE1 20 /* UART Lite */ ++//#define SURFBOARDINT_UART_LITE2 21 /* UART Lite */ ++//#define SURFBOARDINT_UART_LITE3 22 /* UART Lite */ ++//#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1 ++//#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2 ++//#define SURFBOARDINT_WDG 23 /* WDG timer */ ++//#define SURFBOARDINT_TIMER0 24 /* Timer0 */ ++//#define SURFBOARDINT_TIMER1 25 /* Timer1 */ ++//#define SURFBOARDINT_ILL_ACC 35 /* illegal access */ ++#define RALINK_INT_PCIE0 MT_PCIE0_IRQ_ID /* PCIE0 */ ++#define RALINK_INT_PCIE1 MT_PCIE1_IRQ_ID /* PCIE1 */ ++#define RALINK_INT_PCIE2 MT_PCIE2_IRQ_ID /* PCIE2 */ ++ ++// Wait for RD to define IRQ source ++ ++//#define RALINK_INT_xxx MT_CRYPTO_RING0_IRQ_ID /* */ ++//#define RALINK_INT_xxx MT_CRYPTO_RING1_IRQ_ID /* */ ++//#define RALINK_INT_xxx MT_CRYPTO_RING2_IRQ_ID /* */ ++//#define RALINK_INT_xxx MT_FE_PDMA_IRQ_ID /* */ ++//#define RALINK_INT_xxx MT_FE_QDMA_IRQ_ID /* */ ++//#define RALINK_INT_xxx MT_PCIE_LINK_DOWN_RST_IRQ_ID /* */ ++ ++ ++ +diff --git a/arch/arm/include/asm/rt2880/x_define_irq.h b/arch/arm/include/asm/rt2880/x_define_irq.h +new file mode 100644 +index 0000000..4b2e669 +--- /dev/null ++++ b/arch/arm/include/asm/rt2880/x_define_irq.h +@@ -0,0 +1,160 @@ ++/* ++ * This file is generated automatically according to the design of silicon. ++ * Don't modify it directly. ++ */ ++ ++X_DEFINE_IRQ(MT6582_USB0_IRQ_ID , 64, L,LEVEL) ++X_DEFINE_IRQ(MT6582_USB1_IRQ_ID , 65, L,LEVEL) ++X_DEFINE_IRQ(TS_IRQ_ID , 66, L,EDGE) ++X_DEFINE_IRQ(TS_BATCH_IRQ_ID , 67, L,EDGE) ++X_DEFINE_IRQ(LOWBATTERY_IRQ_ID , 68, L,EDGE) ++X_DEFINE_IRQ(PWM_IRQ_ID , 69, L,LEVEL) ++X_DEFINE_IRQ(THERM_CTRL_IRQ_ID , 70, L,LEVEL) ++X_DEFINE_IRQ(MT_MSDC0_IRQ_ID , 71, L,LEVEL) ++X_DEFINE_IRQ(MT_MSDC1_IRQ_ID , 72, L,LEVEL) ++X_DEFINE_IRQ(MT_MSDC2_IRQ_ID , 73, L,LEVEL) ++X_DEFINE_IRQ(MT_MSDC3_IRQ_ID , 74, L,LEVEL) ++X_DEFINE_IRQ(MT_I2C0_IRQ_ID , 76, L,LEVEL) ++X_DEFINE_IRQ(MT_I2C1_IRQ_ID , 77, L,LEVEL) ++X_DEFINE_IRQ(MT_I2C2_IRQ_ID , 78, L,LEVEL) ++X_DEFINE_IRQ(BITF_IRQ_ID , 82, L,LEVEL) ++X_DEFINE_IRQ(MT_UART1_IRQ_ID , 83, L,LEVEL) ++X_DEFINE_IRQ(MT_UART2_IRQ_ID , 84, L,LEVEL) ++X_DEFINE_IRQ(MT_UART3_IRQ_ID , 85, L,LEVEL) ++X_DEFINE_IRQ(MT_UART4_IRQ_ID , 86, L,LEVEL) ++X_DEFINE_IRQ(MT_NFIECC_IRQ_ID , 87, L,LEVEL) ++X_DEFINE_IRQ(MT_NFI_IRQ_ID , 88, L,LEVEL) ++X_DEFINE_IRQ(MT_GDMA1_IRQ_ID , 89, L,LEVEL) ++X_DEFINE_IRQ(MT_GDMA2_IRQ_ID , 90, L,LEVEL) ++X_DEFINE_IRQ(MT6582_HIF_PDMA_IRQ_ID , 91, L,LEVEL) ++X_DEFINE_IRQ(AP_DMA_I2C0_IRQ_ID , 92, L,LEVEL) ++X_DEFINE_IRQ(AP_DMA_I2C1_IRQ_ID , 93, L,LEVEL) ++X_DEFINE_IRQ(AP_DMA_I2C2_IRQ_ID , 94, L,LEVEL) ++X_DEFINE_IRQ(MT_DMA_UART0_TX_IRQ_ID , 95, L,LEVEL) ++X_DEFINE_IRQ(MT_DMA_UART0_RX_IRQ_ID , 96, L,LEVEL) ++X_DEFINE_IRQ(MT_DMA_UART1_TX_IRQ_ID , 97, L,LEVEL) ++X_DEFINE_IRQ(MT_DMA_UART1_RX_IRQ_ID , 98, L,LEVEL) ++X_DEFINE_IRQ(MT_DMA_UART2_TX_IRQ_ID , 99, L,LEVEL) ++X_DEFINE_IRQ(MT_DMA_UART2_RX_IRQ_ID , 100, L,LEVEL) ++X_DEFINE_IRQ(MT_DMA_UART3_TX_IRQ_ID , 101, L,LEVEL) ++X_DEFINE_IRQ(MT_DMA_UART3_RX_IRQ_ID , 102, L,LEVEL) ++X_DEFINE_IRQ(AP_DMA_BTIF_TX_IRQ_ID , 103, L,LEVEL) ++X_DEFINE_IRQ(AP_DMA_BTIF_RX_IRQ_ID , 104, L,LEVEL) ++X_DEFINE_IRQ(MT_GCPU_IRQ_ID , 105, L,LEVEL) ++X_DEFINE_IRQ(MT_GCPU_DMX_IRQ_ID , 106, L,LEVEL) ++X_DEFINE_IRQ(MT_GCPU_MMU_IRQ_ID , 107, L,LEVEL) ++X_DEFINE_IRQ(MT_GCPU_MMU_SEC_IRQ_ID , 108, L,LEVEL) ++X_DEFINE_IRQ(MT_ETHER_NIC_WRAP_IRQ_ID , 109, L,LEVEL) ++X_DEFINE_IRQ(MT6582_SPI1_IRQ_ID , 110, L,LEVEL) ++X_DEFINE_IRQ(MSDC0_WAKEUP_PS_IRQ_ID , 111, H,EDGE) ++X_DEFINE_IRQ(MSDC1_WAKEUP_PS_IRQ_ID , 112, H,EDGE) ++X_DEFINE_IRQ(MSDC2_WAKEUP_PS_IRQ_ID , 113, H,EDGE) ++X_DEFINE_IRQ(MT_CRYPTO_RING0_IRQ_ID , 114, H,LEVEL) ++X_DEFINE_IRQ(MT_CRYPTO_RING1_IRQ_ID , 115, H,LEVEL) ++X_DEFINE_IRQ(MT_CRYPTO_RING2_IRQ_ID , 116, H,LEVEL) ++X_DEFINE_IRQ(MT_PTP_FSM_IRQ_ID , 117, L,LEVEL) ++X_DEFINE_IRQ(BTIF_WAKEUP_IRQ_ID , 118, L,LEVEL) ++X_DEFINE_IRQ(MT_IRRX_IRQ_ID , 119, L,LEVEL) ++X_DEFINE_IRQ(MT_WDT_IRQ_ID , 120, L,EDGE) ++X_DEFINE_IRQ(MT_CRYPTO_RING3_IRQ_ID , 123, H,LEVEL) ++X_DEFINE_IRQ(DCC_APARM_IRQ_ID , 124, L,LEVEL) ++X_DEFINE_IRQ(APARM_CTI_IRQ_ID , 125, L,LEVEL) ++X_DEFINE_IRQ(MT_APARM_DOMAIN_IRQ_ID , 126, L,LEVEL) ++X_DEFINE_IRQ(MT_APARM_DECERR_IRQ_ID , 127, L,LEVEL) ++X_DEFINE_IRQ(DOMAIN_ABORT_IRQ_ID0 , 128, L,LEVEL) ++X_DEFINE_IRQ(MT_CRYPTO_IRQ_ID , 129, H,LEVEL) ++X_DEFINE_IRQ(MT_HSDMA_IRQ_ID , 130, H,LEVEL) ++X_DEFINE_IRQ(MT_GDMA_IRQ_ID , 131, H,LEVEL) ++X_DEFINE_IRQ(CCIF0_AP_IRQ_ID , 132, L,LEVEL) ++X_DEFINE_IRQ(MT_I2S_IRQ_ID , 134, H,LEVEL) ++X_DEFINE_IRQ(MT_PCM_IRQ_ID , 135, H,LEVEL) ++X_DEFINE_IRQ(AFE_MCU_IRQ_ID , 136, L,LEVEL) ++X_DEFINE_IRQ(M4U1_IRQ_ID , 138, L,LEVEL) ++X_DEFINE_IRQ(M4UL2_IRQ_ID , 139, L,LEVEL) ++X_DEFINE_IRQ(M4UL2_SEC_IRQ_ID , 140, L,LEVEL) ++X_DEFINE_IRQ(REFRESH_RATE_IRQ_ID , 141, L,EDGE) ++X_DEFINE_IRQ(MT6582_APARM_GPTTIMER_IRQ_LINE, 144, L,LEVEL) ++X_DEFINE_IRQ(MT_EINT_IRQ_ID , 145, H,LEVEL) ++X_DEFINE_IRQ(EINT_EVENT_IRQ_ID , 146, L,LEVEL) ++X_DEFINE_IRQ(MT6582_PMIC_WRAP_IRQ_ID , 147, H,LEVEL) ++X_DEFINE_IRQ(MT_KP_IRQ_ID , 148, L,EDGE) ++X_DEFINE_IRQ(MT_SPM_IRQ_ID , 149, L,LEVEL) ++X_DEFINE_IRQ(MT_SPM1_IRQ_ID , 150, L,LEVEL) ++X_DEFINE_IRQ(MT_SPM2_IRQ_ID , 151, L,LEVEL) ++X_DEFINE_IRQ(MT_SPM3_IRQ_ID , 152, L,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT0_IRQ_ID , 153, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT1_IRQ_ID , 154, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT2_IRQ_ID , 155, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT3_IRQ_ID , 156, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT4_IRQ_ID , 157, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT5_IRQ_ID , 158, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT6_IRQ_ID , 159, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT7_IRQ_ID , 160, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT8_IRQ_ID , 161, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT9_IRQ_ID , 162, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT10_IRQ_ID , 163, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT11_IRQ_ID , 164, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT12_IRQ_ID , 165, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT13_IRQ_ID , 166, H,LEVEL) ++X_DEFINE_IRQ(MT_EINT_DIRECT14_IRQ_ID , 167, H,LEVEL) ++X_DEFINE_IRQ(SMI_LARB0_IRQ_ID , 168, L,LEVEL) ++X_DEFINE_IRQ(SMI_LARB1_IRQ_ID , 169, L,LEVEL) ++X_DEFINE_IRQ(SMI_LARB2_IRQ_ID , 170, L,LEVEL) ++X_DEFINE_IRQ(MT_VDEC_IRQ_ID , 171, L,LEVEL) ++X_DEFINE_IRQ(MT_VENC_IRQ_ID , 172, L,LEVEL) ++X_DEFINE_IRQ(MT6582_JPEG_ENC_IRQ_ID , 173, L,LEVEL) ++X_DEFINE_IRQ(SENINF_IRQ_ID , 174, L,LEVEL) ++X_DEFINE_IRQ(CAMERA_ISP_IRQ0_ID , 175, L,LEVEL) ++X_DEFINE_IRQ(CAMERA_ISP_IRQ1_ID , 176, L,LEVEL) ++X_DEFINE_IRQ(CAMERA_ISP_IRQ2_ID , 177, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_MDP_RDMA_IRQ_ID , 178, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_MDP_RSZ0_IRQ_ID , 179, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_MDP_RSZ1_IRQ_ID , 180, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_MDP_TDSHP_IRQ_ID , 181, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_MDP_WDMA_IRQ_ID , 182, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_MDP_WROT_IRQ_ID , 183, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_RDMA_IRQ_ID , 184, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_OVL_IRQ_ID , 185, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_WDMA_IRQ_ID , 186, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_BLS_IRQ_ID , 187, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_COLOR_IRQ_ID , 188, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_DSI_IRQ_ID , 189, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_DPI0_IRQ_ID , 190, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_CMDQ_IRQ_ID , 191, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_CMDQ_SECURE_IRQ_ID, 192, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_MUTEX_IRQ_ID , 193, L,LEVEL) ++X_DEFINE_IRQ(MM_DUMMY0_IRQ_ID , 194, L,LEVEL) ++X_DEFINE_IRQ(MM_DUMMY1_IRQ_ID , 195, L,LEVEL) ++X_DEFINE_IRQ(MT6582_DISP_RDMA1_IRQ_ID , 196, L,LEVEL) ++X_DEFINE_IRQ(MM_DUMMY3_IRQ_ID , 197, L,LEVEL) ++X_DEFINE_IRQ(MM_DUMMY4_IRQ_ID , 198, L,LEVEL) ++X_DEFINE_IRQ(MM_DUMMY5_IRQ_ID , 199, L,LEVEL) ++X_DEFINE_IRQ(MM_DUMMY6_IRQ_ID , 200, L,LEVEL) ++X_DEFINE_IRQ(MM_DUMMY7_IRQ_ID , 201, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ0_ID , 202, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ1_ID , 203, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ2_ID , 204, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ3_ID , 205, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ4_ID , 206, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ5_ID , 207, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ6_ID , 208, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ7_ID , 209, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ8_ID , 210, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ9_ID , 211, L,LEVEL) ++X_DEFINE_IRQ(MT_MFG_IRQ10_ID , 212, L,LEVEL) ++X_DEFINE_IRQ(MT_APXGPT_SECURE_IRQ_ID , 213, L,LEVEL) ++X_DEFINE_IRQ(MT_CEC_IRQ_ID , 214, L,LEVEL) ++X_DEFINE_IRQ(CONN_WDT_IRQ_ID , 215, L,EDGE) ++X_DEFINE_IRQ(WF_HIF_IRQ_ID , 216, L,LEVEL) ++X_DEFINE_IRQ(MT_CONN2AP_BTIF_WAKEUP_IRQ_ID , 217, L,LEVEL) ++X_DEFINE_IRQ(BT_CVSD_IRQ_ID , 218, L,LEVEL) ++X_DEFINE_IRQ(MT_CIRQ_IRQ_ID , 219, L,LEVEL) ++X_DEFINE_IRQ(MT_PCIE_LINK_DOWN_RST_IRQ_ID , 224, H,EDGE) ++X_DEFINE_IRQ(MT_PCIE0_IRQ_ID , 225, H,LEVEL) ++X_DEFINE_IRQ(MT_PCIE1_IRQ_ID , 226, H,LEVEL) ++X_DEFINE_IRQ(MT_PCIE2_IRQ_ID , 227, H,LEVEL) ++X_DEFINE_IRQ(MT_SSUSB_XHCI0_IRQ_ID , 228, H,LEVEL) ++X_DEFINE_IRQ(MT_SSUSB_XHCI1_IRQ_ID , 229, H,LEVEL) ++X_DEFINE_IRQ(MT_FE_PDMA_IRQ_ID , 230, H,LEVEL) ++X_DEFINE_IRQ(MT_FE_QDMA_IRQ_ID , 231, H,LEVEL) ++X_DEFINE_IRQ(MT_FE_ORIG_IRQ_ID , 232, H,LEVEL) +diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c +index ab8cf21..c0e373b 100644 +--- a/arch/arm/mach-mediatek/mediatek.c ++++ b/arch/arm/mach-mediatek/mediatek.c +@@ -19,6 +19,186 @@ + #include + #include + #include ++#include ++#include "rt_mmap.h" ++#include "mt_reg_base.h" ++ ++#define IO_VIRT_TO_PHYS(v) (0x10000000 | ((v) & 0x0fffffff)) ++ ++static struct map_desc mt_io_desc[] __initdata = ++{ ++#if !defined(CONFIG_MT8127_FPGA) ++ { ++ .virtual = INFRA_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(INFRA_BASE)), ++ .length = (SZ_1M - SZ_4K), ++ .type = MT_DEVICE ++ }, ++ /* Skip the mapping of 0xF0130000~0xF013FFFF to protect access from APMCU */ ++ { ++ .virtual = (DEBUGTOP_BASE - SZ_4K), ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS((DEBUGTOP_BASE - SZ_4K))), ++ .length = (0x30000 + SZ_4K), ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = (DEBUGTOP_BASE + 0x40000), ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(DEBUGTOP_BASE + 0x40000)), ++ .length = 0xC0000, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = MCUSYS_CFGREG_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(MCUSYS_CFGREG_BASE)), ++ .length = SZ_2M, ++ .type = MT_DEVICE ++ }, ++ /* //// */ ++ { ++ .virtual = AP_DMA_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(AP_DMA_BASE)), ++ .length = SZ_2M + SZ_1M, ++ .type = MT_DEVICE ++ }, ++ { ++ /* virtual 0xF2000000, physical 0x00200000 */ ++ .virtual = SYSRAM_BASE, ++ .pfn = __phys_to_pfn(0x00200000), ++ .length = SZ_128K, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = G3D_CONFIG_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(G3D_CONFIG_BASE)), ++ .length = SZ_128K, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = DISPSYS_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(DISPSYS_BASE)), ++ .length = SZ_16M, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = IMGSYS_CONFG_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(IMGSYS_CONFG_BASE)), ++ .length = SZ_16M, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = VDEC_GCON_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(VDEC_GCON_BASE)), ++ .length = SZ_16M, ++ .type = MT_DEVICE ++ }, ++ { ++ /* virtual 0xF7000000, physical 0x08000000 */ ++ .virtual = DEVINFO_BASE, ++ .pfn = __phys_to_pfn(0x08000000), ++ .length = SZ_64K, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = CONN_BTSYS_PKV_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(CONN_BTSYS_PKV_BASE)), ++ .length = SZ_1M, ++ .type = MT_DEVICE ++ }, ++ { ++ /* virtual 0xF9000000, physical 0x00100000 */ ++ .virtual = INTER_SRAM, ++ .pfn = __phys_to_pfn(0x00100000), ++ .length = SZ_64K, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = HIFSYS_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(HIFSYS_BASE)), ++ .length = SZ_16M, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = ETHDMASYS_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(ETHDMASYS_BASE)), ++ .length = SZ_16M, ++ .type = MT_DEVICE ++ }, ++#if 0 ++ { ++ .virtual = BDP_DISPSYS_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(BDP_DISPSYS_BASE)), ++ .length = SZ_32K + SZ_16K, ++ .type = MT_DEVICE ++ }, ++#endif ++#else ++ { ++ .virtual = INFRA_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(INFRA_BASE)), ++ .length = SZ_4M, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = AP_DMA_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(AP_DMA_BASE)), ++ .length = SZ_2M + SZ_1M, ++ .type = MT_DEVICE ++ }, ++ #if 0 ++ { ++ .virtual = MMSYS1_CONFIG_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(MMSYS1_CONFIG_BASE)), ++ .length = SZ_16M, ++ .type = MT_DEVICE ++ }, ++ #endif ++ { ++ /* From: 0xF2000000 to 0xF2020000*/ ++ .virtual = SYSRAM_BASE, ++ .pfn = __phys_to_pfn(0x00200000), ++ .length = SZ_128K, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = DISPSYS_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(DISPSYS_BASE)), ++ .length = SZ_16M, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = IMGSYS_CONFG_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(IMGSYS_CONFG_BASE)), ++ .length = SZ_16M, ++ .type = MT_DEVICE ++ }, ++ /* G3DSYS */ ++ { ++ .virtual = G3D_CONFIG_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(G3D_CONFIG_BASE)), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = DEVINFO_BASE, ++ .pfn = __phys_to_pfn(0x08000000), ++ .length = SZ_64K, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = MALI_BASE, ++ .pfn = __phys_to_pfn(IO_VIRT_TO_PHYS(MALI_BASE)), ++ .length = SZ_64K, ++ .type = MT_DEVICE ++ }, ++ { ++ .virtual = INTER_SRAM, ++ .pfn = __phys_to_pfn(0x00100000), ++ .length = SZ_64K, ++ .type = MT_DEVICE ++ }, ++#endif ++}; ++ + + + #define GPT6_CON_MT65xx 0x10008060 +@@ -55,7 +235,13 @@ static const char * const mediatek_board_dt_compat[] = { + NULL, + }; + ++void __init mt_map_io(void) ++{ ++ iotable_init(mt_io_desc, ARRAY_SIZE(mt_io_desc)); ++} ++ + DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)") + .dt_compat = mediatek_board_dt_compat, + .init_time = mediatek_timer_init, ++ .map_io = mt_map_io, + MACHINE_END +diff --git a/arch/arm/mach-mediatek/mt_reg_base.h b/arch/arm/mach-mediatek/mt_reg_base.h +new file mode 100644 +index 0000000..cf2bb9e +--- /dev/null ++++ b/arch/arm/mach-mediatek/mt_reg_base.h +@@ -0,0 +1,640 @@ ++/* ++ * This file is generated automatically according to the design of silicon. ++ * Don't modify it directly. ++ */ ++ ++#ifndef __MT_REG_BASE ++#define __MT_REG_BASE ++ ++#if !defined(CONFIG_MT8127_FPGA) ++ ++// APB Module cksys ++#define INFRA_BASE (0xF0000000) ++ ++// APB Module infracfg_ao ++#define INFRACFG_AO_BASE (0xF0001000) ++ ++// APB Module fhctl ++#define FHCTL_BASE (0xF0002000) ++ ++// APB Module pericfg ++#define PERICFG_BASE (0xF0003000) ++ ++// APB Module dramc ++#define DRAMC0_BASE (0xF0004000) ++ ++// APB Module gpio ++#define GPIO_BASE (0xF0005000) ++ ++// APB Module sleep ++#define SPM_BASE (0xF0006000) ++ ++// APB Module toprgu ++#define TOPRGU_BASE (0xF0007000) ++#define AP_RGU_BASE TOPRGU_BASE ++ ++// APB Module apxgpt ++#define APMCU_GPTIMER_BASE (0xF0008000) ++ ++// APB Module rsvd ++#define RSVD_BASE (0xF0009000) ++ ++// APB Module sej ++#define HACC_BASE (0xF000A000) ++ ++// APB Module ap_cirq_eint ++#define AP_CIRQ_EINT (0xF000B000) ++ ++// APB Module ap_cirq_eint ++#define EINT_BASE (0xF000B000) ++ ++// APB Module smi ++#define SMI1_BASE (0xF000C000) ++ ++// APB Module pmic_wrap ++#define PWRAP_BASE (0xF000D000) ++ ++// APB Module device_apc_ao ++#define DEVAPC_AO_BASE (0xF000E000) ++ ++// APB Module ddrphy ++#define DDRPHY_BASE (0xF000F000) ++ ++// APB Module vencpll ++#define VENCPLL_BASE (0xF000F000) ++ ++// APB Module mipi_tx_config ++#define MIPI_CONFIG_BASE (0xF0010000) ++ ++// APB Module LVDS ANA ++#define LVDS_ANA_BASE (0xF0010400) ++ ++// APB Module mipi_rx_ana ++#define MIPI_RX_ANA_BASE (0xF0215000) ++ ++// APB Module kp ++#define KP_BASE (0xF0011000) ++ ++// APB Module dbgapb ++#define DEBUGTOP_BASE (0xF0100000) ++ ++// APB Module mcucfg ++#define MCUSYS_CFGREG_BASE (0xF0200000) ++ ++// APB Module infracfg ++#define INFRACFG_BASE (0xF0201000) ++ ++// APB Module sramrom ++#define SRAMROM_BASE (0xF0202000) ++ ++// APB Module emi ++#define EMI_BASE (0xF0203000) ++ ++// APB Module sys_cirq ++#define SYS_CIRQ_BASE (0xF0204000) ++ ++// APB Module m4u ++#define SMI_MMU_TOP_BASE (0xF0205000) ++ ++// APB Module nb_mmu ++#define NB_MMU0_BASE (0xF0205200) ++ ++// APB Module nb_mmu ++#define NB_MMU1_BASE (0xF0205800) ++ ++// APB Module efusec ++#define EFUSEC_BASE (0xF0206000) ++ ++// APB Module device_apc ++#define DEVAPC_BASE (0xF0207000) ++ ++// APB Module mcu_biu_cfg ++#define MCU_BIU_BASE (0xF0208000) ++ ++// APB Module apmixed ++#define APMIXEDSYS_BASE (0xF0209000) ++ ++// APB Module ccif ++#define AP_CCIF_BASE (0xF020A000) ++ ++// APB Module ccif ++#define MD_CCIF_BASE (0xF020B000) ++ ++// APB Module gpio1 ++#define GPIO1_BASE (0xF020C000) ++ ++// APB Module infra_mbist ++#define INFRA_TOP_MBIST_CTRL_BASE (0xF020D000) ++ ++// APB Module dramc_conf_nao ++#define DRAMC_NAO_BASE (0xF020E000) ++ ++// APB Module trng ++#define TRNG_BASE (0xF020F000) ++ ++// APB Module ca9 ++#define CORTEXA7MP_BASE (0xF0210000) ++ ++// APB Module ap_dma ++#define AP_DMA_BASE (0xF1000000) ++ ++// APB Module auxadc ++#define AUXADC_BASE (0xF1001000) ++ ++// APB Module uart ++#define UART1_BASE (0xF1002000) ++ ++// APB Module uart ++#define UART2_BASE (0xF1003000) ++ ++// APB Module uart ++#define UART3_BASE (0xF1004000) ++ ++// APB Module uart ++#define UART4_BASE (0xF1005000) ++ ++// APB Module pwm ++#define PWM_BASE (0xF1006000) ++ ++// APB Module i2c ++#define I2C0_BASE (0xF1007000) ++ ++// APB Module i2c ++#define I2C1_BASE (0xF1008000) ++ ++// APB Module i2c ++#define I2C2_BASE (0xF1009000) ++ ++// APB Module spi ++#define SPI0_BASE (0xF100A000) ++#define SPI1_BASE (0xF100A000) ++ ++// APB Module therm_ctrl ++#define THERMAL_BASE (0xF100B000) ++ ++// APB Module btif ++#define BTIF_BASE (0xF100C000) ++ ++// APB Module nfi ++#define NFI_BASE (0xF100D000) ++ ++// APB Module nfiecc_16bit ++#define NFIECC_BASE (0xF100E000) ++ ++// APB Module nli_arb ++#define NLI_ARB_BASE (0xF100F000) ++ ++// APB Module peri_pwrap_bridge ++#define PERI_PWRAP_BRIDGE_BASE (0xF1017000) ++ ++// APB Module usb2 ++#define USB_BASE (0xF1200000) ++#define USB1_BASE (0xF1270000) ++ ++// APB Module usb_sif ++#define USB_SIF_BASE (0xF1210000) ++ ++// APB Module msdc ++#define MSDC_0_BASE (0xF1230000) ++ ++// APB Module msdc ++#define MSDC_1_BASE (0xF1240000) ++ ++// APB Module msdc ++#define MSDC_2_BASE (0xF1250000) ++ ++// APB Module msdc ++#define MSDC_3_BASE (0xF12C0000) ++ ++// APB Module wcn_ahb ++#define WCN_AHB_BASE (0xF1260000) ++ ++// ARB Module ethernet ++#define ETHERNET_BASE (0xF1280000) ++// APB Module mfg_top ++#define G3D_CONFIG_BASE (0xF3000000) ++ ++// APB Module mali ++#define MALI_BASE (0xF3040000) ++ ++// APB Module mali_tb_cmd ++#define MALI_TB_BASE (0xF301f000) ++ ++// APB Module mmsys_config ++#define DISPSYS_BASE (0xF4000000) ++ ++// APB Module mdp_rdma ++#define MDP_RDMA_BASE (0xF4001000) ++ ++// APB Module mdp_rsz ++#define MDP_RSZ0_BASE (0xF4002000) ++ ++// APB Module mdp_rsz ++#define MDP_RSZ1_BASE (0xF4003000) ++ ++// APB Module disp_wdma ++#define MDP_WDMA_BASE (0xF4004000) ++ ++// APB Module disp_wdma ++#define WDMA1_BASE (0xF4004000) ++ ++// APB Module mdp_wrot ++#define MDP_WROT_BASE (0xF4005000) ++ ++// APB Module mdp_tdshp ++#define MDP_TDSHP_BASE (0xF4006000) ++ ++// APB Module ovl ++#define DISP_OVL_BASE (0xF4007000) ++ ++// APB Module ovl ++#define OVL0_BASE (0xF4007000) ++ ++// APB Module ovl ++#define OVL1_BASE (0xF4007000) ++ ++// APB Module disp_rdma ++#define DISP_RDMA_BASE (0xF4008000) ++ ++// APB Module disp_rdma ++#define R_DMA1_BASE (0xF4008000) ++ ++// APB Module disp_rdma ++#define R_DMA0_BASE (0xF4008000) ++ ++// APB Module disp_wdma ++#define DISP_WDMA_BASE (0xF4009000) ++ ++// APB Module disp_wdma ++#define WDMA0_BASE (0xF4009000) ++ ++// APB Module disp_bls ++#define DISP_BLS_BASE (0xF400A000) ++ ++// APB Module disp_color_config ++#define DISP_COLOR_BASE (0xF400B000) ++ ++// APB Module dsi ++#define DSI_BASE (0xF400C000) ++ ++// APB Module disp_dpi ++#define DPI_BASE (0xF400D000) ++ ++// APB Module disp_mutex ++#define MMSYS_MUTEX_BASE (0xF400E000) ++ ++// APB Module mm_cmdq ++#define MMSYS_CMDQ_BASE (0xF400F000) ++ ++#define DPI1_BASE (0xF4014000) ++ ++ ++// APB Module smi_larb ++#define SMI_LARB0_BASE (0xF4010000) ++ ++// APB Module smi ++#define SMI_BASE (0xF4011000) ++ ++// LVDS TX ++#define LVDS_TX_BASE (0xF4016200) ++ ++// APB Module smi_larb ++#define SMILARB2_BASE (0xF5001000) ++ ++// APB Module smi_larb ++#define SMI_LARB3_BASE (0xF5001000) ++ ++// APB Module mmu ++#define SMI_LARB3_MMU_BASE (0xF5001800) ++ ++// APB Module smi_larb ++#define SMI_LARB4_BASE (0xF5002000) ++ ++// APB Module fake_eng ++#define FAKE_ENG_BASE (0xF5002000) ++ ++// APB Module mmu ++#define SMI_LARB4_MMU_BASE (0xF5002800) ++ ++// APB Module smi ++#define VENC_BASE (0xF5009000) ++ ++// APB Module jpgenc ++#define JPGENC_BASE (0xF500A000) ++ ++// APB Module vdecsys_config ++#define VDEC_GCON_BASE (0xF6000000) ++ ++// APB Module smi_larb ++#define SMI_LARB1_BASE (0xF6010000) ++ ++// APB Module mmu ++#define SMI_LARB1_MMU_BASE (0xF6010800) ++ ++// APB Module vdtop ++#define VDEC_BASE (0xF6020000) ++ ++// APB Module vdtop ++#define VDTOP_BASE (0xF6020000) ++ ++// APB Module vld ++#define VLD_BASE (0xF6021000) ++ ++// APB Module vld_top ++#define VLD_TOP_BASE (0xF6021800) ++ ++// APB Module mc ++#define MC_BASE (0xF6022000) ++ ++// APB Module avc_vld ++#define AVC_VLD_BASE (0xF6023000) ++ ++// APB Module avc_mv ++#define AVC_MV_BASE (0xF6024000) ++ ++// APB Module vdec_pp ++#define VDEC_PP_BASE (0xF6025000) ++ ++// APB Module vp8_vld ++#define VP8_VLD_BASE (0xF6026800) ++ ++// APB Module vp6 ++#define VP6_BASE (0xF6027000) ++ ++// APB Module vld2 ++#define VLD2_BASE (0xF6027800) ++ ++// APB Module mc_vmmu ++#define MC_VMMU_BASE (0xF6028000) ++ ++// APB Module pp_vmmu ++#define PP_VMMU_BASE (0xF6029000) ++ ++// APB Module imgsys ++#define IMGSYS_CONFG_BASE (0xF5000000) ++ ++// APB Module cam ++#define CAMINF_BASE (0xF5000000) ++ ++// APB Module csi2 ++#define CSI2_BASE (0xF5000000) ++ ++// APB Module seninf ++#define SENINF_BASE (0xF5000000) ++ ++// APB Module seninf_tg ++#define SENINF_TG_BASE (0xF5000000) ++ ++// APB Module seninf_top ++#define SENINF_TOP_BASE (0xF5000000) ++ ++// APB Module mipi_rx_config ++#define MIPI_RX_CONFIG_BASE (0xF500C000) ++ ++// APB Module scam ++#define SCAM_BASE (0xF5008000) ++ ++// APB Module ncsi2 ++#define NCSI2_BASE (0xF5008000) ++ ++// APB Module ccir656 ++#define CCIR656_BASE (0xF5000000) ++ ++// APB Module n3d_ctl ++#define N3D_CTL_BASE (0xF5000000) ++ ++// APB Module fdvt ++#define FDVT_BASE (0xF500B000) ++ ++// APB Module audiosys ++#define AUDIO_BASE (0xF1221000) ++#define AUDIO_REG_BASE (0xF1220000) ++ ++// CONNSYS ++#define CONN_BTSYS_PKV_BASE (0xF8000000) ++#define CONN_BTSYS_TIMCON_BASE (0xF8010000) ++#define CONN_BTSYS_RF_CONTROL_BASE (0xF8020000) ++#define CONN_BTSYS_MODEM_BASE (0xF8030000) ++#define CONN_BTSYS_BT_CONFIG_BASE (0xF8040000) ++#define CONN_MCU_CONFIG_BASE (0xF8070000) ++#define CONN_TOP_CR_BASE (0xF80B0000) ++#define CONN_HIF_CR_BASE (0xF80F0000) ++ ++/* ++ * Addresses below are added manually. ++ * They cannot be mapped via IO_VIRT_TO_PHYS(). ++ */ ++ ++#define GIC_CPU_BASE (CORTEXA7MP_BASE + 0x2000) ++#define GIC_DIST_BASE (CORTEXA7MP_BASE + 0x1000) ++#define SYSRAM_BASE 0xF2000000 /* L2 cache shared RAM */ ++#define DEVINFO_BASE 0xF7000000 ++#define INTER_SRAM 0xF9000000 ++ ++#else ++ ++#define SMI_MMU_TOP_BASE 0xF0205000 ++#define SMILARB2_BASE 0xF5001000 ++ ++/* on-chip SRAM */ ++#define INTER_SRAM 0xF9000000 ++ ++/* infrasys */ ++//#define TOPRGU_BASE 0xF0000000 ++#define INFRA_BASE 0xF0000000 ++#define INFRACFG_BASE 0xF0001000 ++#define INFRACFG_AO_BASE 0xF0001000 ++#define FHCTL_BASE 0xF0002000 ++#define PERICFG_BASE 0xF0003000 ++#define DRAMC0_BASE 0xF0004000 ++#define DDRPHY_BASE 0xF000F000 ++#define DRAMC_NAO_BASE 0xF020E000 ++#define GPIO_BASE 0xF0005000 ++#define GPIO1_BASE 0xF020C000 ++#define TOPSM_BASE 0xF0006000 ++#define SPM_BASE 0xF0006000 ++#define TOPRGU_BASE 0xF0007000 ++#define AP_RGU_BASE TOPRGU_BASE ++#define APMCU_GPTIMER_BASE 0xF0008000 ++#define HACC_BASE 0xF000A000 ++#define AP_CIRQ_EINT 0xF000B000 ++#define SMI1_BASE 0xF000C000 ++#define MIPI_CONFIG_BASE 0xF0010000 ++// APB Module LVDS ANA ++#define LVDS_ANA_BASE (0xF0010400) ++ ++ ++#define KP_BASE 0xF0011000 ++#if 0 ++#define DEVICE_APC_0_BASE 0xF0010000 ++#define DEVICE_APC_1_BASE 0xF0011000 ++#define DEVICE_APC_2_BASE 0xF0012000 ++#define DEVICE_APC_3_BASE 0xF0013000 ++#define DEVICE_APC_4_BASE 0xF0014000 ++#define SMI0_BASE 0xF0208000 ++#endif ++#define EINT_BASE 0xF000B000 ++ ++ ++#define DEBUGTOP_BASE 0xF0100000 ++#define MCUSYS_CFGREG_BASE 0xF0200000 ++#define SRAMROM_BASE 0xF0202000 ++#define EMI_BASE 0xF0203000 ++#define EFUSEC_BASE 0xF0206000 ++#define MCU_BIU_BASE 0xF0208000 ++#define APMIXED_BASE 0xF0209000 ++#define APMIXEDSYS_BASE 0xF0209000 ++#define AP_CCIF_BASE 0xF020A000 ++#define MD_CCIF_BASE 0xF020B000 ++#define INFRA_TOP_MBIST_CTRL_BASE 0xF020D000 ++#define DRAMC_NAO_BASE 0xF020E000 ++#define CORTEXA7MP_BASE 0xF0210000 ++#define GIC_CPU_BASE (CORTEXA7MP_BASE + 0x2000) ++#define GIC_DIST_BASE (CORTEXA7MP_BASE + 0x1000) ++//#define SMI_LARB_BASE 0xF0211000 ++//#define MCUSYS_AVS_BASE 0xF0212000 ++ ++/* perisys */ ++/*avalaible*/ ++#define AP_DMA_BASE 0xF1000000 ++#define AUXADC_BASE 0xF1001000 ++#define UART1_BASE 0xF1002000 ++#define UART2_BASE 0xF1003000 ++#define UART3_BASE 0xF1004000 ++#define UART4_BASE 0xF1005000 ++#define PWM_BASE 0xF1006000 ++#define I2C0_BASE 0xF1007000 ++#define I2C1_BASE 0xF1008000 ++#define I2C2_BASE 0xF1009000 ++#define SPI0_BASE 0xF100A000 ++#define BTIF_BASE (0xF100C000) ++#define NFI_BASE 0xF100D000 ++#define NFIECC_BASE 0xF100E000 ++#define NLI_ARB_BASE 0xF100F000 ++#define I2C3_BASE 0xF1010000 //FIXME 6582 take off ++#define SPI1_BASE 0xF100A000 ++#define THERMAL_BASE 0xF100B000 ++ ++// APB Module pmic_wrap ++#define PWRAP_BASE (0xF000D000) ++ ++#if 0 ++//#define IRDA_BASE 0xF1007000 ++#define I2C4_BASE 0xF1014000 ++#define I2CDUAL_BASE 0xF1015000 ++#define ACCDET_BASE 0xF1016000 ++#define AP_HIF_BASE 0xF1017000 ++#define MD_HIF_BASE 0xF1018000 ++#define GCPU_BASE 0xF101B000 ++#define GCPU_NS_BASE 0xF01C000 ++#define GCPU_MMU_BASE 0xF01D000 ++#define SATA_BASE 0xF01E000 ++#define CEC_BASE 0xF01F000 ++//#define SPI1_BASE 0xF1022000 ++#endif ++ ++#define USB1_BASE 0xF1270000 ++#define USB2_BASE 0xF1200000 ++#define USB_BASE 0xF1200000 ++#define USB_SIF_BASE 0xF1210000 ++//#define USB3_BASE 0xF1220000 ++#define MSDC_0_BASE 0xF1230000 ++#define MSDC_1_BASE 0xF1240000 ++#define MSDC_2_BASE 0xF1250000 ++#define MSDC_3_BASE 0xF12C0000 ++#define MSDC_4_BASE 0xF1270000 ++//#define ETHERNET_BASE 0xF1290000 ++ ++//#define ETB_BASE 0xF0111000 ++//#define ETM_BASE 0xF017C000 ++ ++ ++/* SMI common subsystem */ ++#define SYSRAM_BASE 0xF2000000 ++#define AUDIO_REG_BASE 0xF2030000 ++#define MFG_AXI_BASE 0xF2060000 ++#define CONN_MCU_CONFIG_BASE 0xF8070000 ++#define AUDIO_BASE 0xF1200000 //0xF2071000 ++#define MMSYS1_CONFIG_BASE 0xF2080000 ++#define SMI_LARB0_BASE 0xF2081000 ++// APB Module smi ++#define SMI_BASE (0xF4011000) ++#define SMI_LARB1_BASE 0xF2082000 ++#define SMI_LARB2_BASE 0xF2083000 ++#define VDEC_GCON_BASE 0xF6000000 //0xF4000000 ++#define VDEC_BASE 0xF4020000 ++#define VENC_TOP_BASE 0xF7000000 ++#define VENC_BASE 0xF7002000 ++#define JPGENC_BASE 0xF500A000 ++#define R_DMA0_BASE 0xF2086000 ++#define R_DMA1_BASE 0xF2087000 ++#define VDO_ROT0_BASE 0xF2088000 ++#define RGB_ROT0_BASE 0xF2089000 ++#define VDO_ROT1_BASE 0xF208A000 ++#define RGB_ROT1_BASE 0xF208B000 ++//#define DPI_BASE 0xF208C000 ++#define BRZ_BASE 0xF208D000 ++#define JPG_DMA_BASE 0xF208E000 ++#define OVL_DMA_BASE 0xF208F000 ++#define CSI2_BASE 0xF2092000 ++#define CRZ_BASE 0xF2093000 ++#define VRZ0_BASE 0xF2094000 ++#define IMGPROC_BASE 0xF2095000 ++#define EIS_BASE 0xF2096000 ++#define SPI_BASE 0xF2097000 ++#define SCAM_BASE 0xF2098000 ++#define PRZ0_BASE 0xF2099000 ++#define PRZ1_BASE 0xF209A000 ++#define JPG_CODEC_BASE 0xF209B000 ++//#define DSI_BASE 0xF209C000 ++#define TVC_BASE 0xF209D000 ++#define TVE_BASE 0xF209E000 ++#define TV_ROT_BASE 0xF209F000 ++#define RGB_ROT2_BASE 0xF20A0000 ++//#define LCD_BASE 0xF20A1000 ++#define FD_BASE 0xF20A2000 ++#define MIPI_CONFG_BASE 0xF20A3000 ++#define VRZ1_BASE 0xF20A4000 ++#define MMSYS2_CONFG_BASE 0xF20C0000 ++#define SMI_LARB3_BASE 0xF20C1000 ++#define MFG_APB_BASE 0xF20C4000 ++#define G2D_BASE 0xF20C6000 ++ ++#define DISPSYS_BASE 0xF4000000 ++#define ROT_BASE 0xF4001000 ++#define SCL_BASE 0xF4002000 ++#define OVL_BASE 0xF4007000 ++#define WDMA0_BASE 0xF4009000 ++#define WDMA1_BASE 0xF4005000 ++#define RDMA0_BASE 0xF4008000 ++//#define RDMA1_BASE 0xF4007000 ++#define BLS_BASE 0xF400A000 ++//#define GAMMA_BASE 0xF400000 ++#define COLOR_BASE 0xF400B000 ++#define TDSHP_BASE 0xF4006000 ++#define LCD_BASE 0xF4012000// only exist on FPGA ++#define DSI_BASE 0xF400C000 ++#define DPI_BASE 0xF400D000 ++ ++#define DPI1_BASE 0xF4014000 ++ ++// LVDS TX ++#define LVDS_TX_BASE (0xF4016200) ++ ++#define SMILARB1_BASE 0xF4010000 ++#define DISP_MUTEX_BASE 0xF400E000 ++#define DISP_CMDQ_BASE 0xF400F000 ++ ++/* imgsys */ ++#define IMGSYS_CONFG_BASE 0xF5000000 ++#define CAMINF_BASE IMGSYS_CONFG_BASE ++ ++/* G3DSYS */ ++#define G3D_CONFIG_BASE 0xF3000000 ++#define MALI_BASE 0xF3040000 ++ ++#define DEVINFO_BASE 0xF8000000 ++ ++#endif ++ ++#endif +diff --git a/arch/arm/mach-mediatek/rt_mmap.h b/arch/arm/mach-mediatek/rt_mmap.h +new file mode 100644 +index 0000000..e86b3bb +--- /dev/null ++++ b/arch/arm/mach-mediatek/rt_mmap.h +@@ -0,0 +1,58 @@ ++#define HIFSYS_BASE 0xFA000000 //for PCIe/USB ++#define ETHDMASYS_BASE 0xFB000000 //for I2S/PCM/GDMA/HSDMA/FE/GMAC ++ ++#define HIFSYS_PCI_BASE 0xFA140000 ++#define HIFSYS_USB_HOST_BASE 0xFA1C0000 ++#define HIFSYS_USB_HOST2_BASE 0xFA240000 ++ ++#define ETHDMASYS_SYSCTL_BASE 0xFB000000 ++#define ETHDMASYS_RBUS_MATRIXCTL_BASE 0xFB000400 ++#define ETHDMASYS_I2S_BASE 0xFB000A00 ++#define ETHDMASYS_PCM_BASE 0xFB002000 ++#define ETHDMASYS_GDMA_BASE 0xFB002800 ++#define ETHDMASYS_HS_DMA_BASE 0xFB007000 ++#define ETHDMASYS_FRAME_ENGINE_BASE 0xFB100000 ++#define ETHDMASYS_PPE_BASE 0xFB100C00 ++#define ETHDMASYS_ETH_SW_BASE 0xFB110000 ++#define ETHDMASYS_CRYPTO_ENGINE_BASE 0xFB240000 ++ ++//for backward-compatible ++#define RALINK_FRAME_ENGINE_BASE ETHDMASYS_FRAME_ENGINE_BASE ++#define RALINK_PPE_BASE ETHDMASYS_PPE_BASE ++#define RALINK_SYSCTL_BASE ETHDMASYS_SYSCTL_BASE ++#define RALINK_ETH_SW_BASE ETHDMASYS_ETH_SW_BASE ++#define RALINK_GDMA_BASE ETHDMASYS_GDMA_BASE ++#define RALINK_HS_DMA_BASE ETHDMASYS_HS_DMA_BASE ++#define RALINK_11N_MAC_BASE 0 //unused for rt_rdm usage ++ ++//Reset Control Register ++#define RSTCTL_SYS_RST (1<<0) ++#define RSTCTL_MCM_RST (1<<2) ++#define RSTCTL_HSDMA_RST (1<<5) ++#define RSTCTL_FE_RST (1<<6) ++#define RSTCTL_SPDIF_RST (1<<7) ++#define RSTCTL_TIMER_RST (1<<8) ++#define RSTCTL_CIRQ_RST (1<<9) ++#define RSTCTL_MC_RST (1<<10) ++#define RSTCTL_PCM_RST (1<<11) ++#define RSTCTL_GPIO_RST (1<<13) ++#define RSTCTL_GDMA_RST (1<<14) ++#define RSTCTL_NAND_RST (1<<15) ++#define RSTCTL_I2C_RST (1<<16) ++#define RSTCTL_I2S_RST (1<<17) ++#define RSTCTL_SPI_RST (1<<18) ++#define RSTCTL_UART0_RST (1<<19) ++#define RSTCTL_UART1_RST (1<<20) ++#define RSTCTL_UART2_RST (1<<21) ++#define RSTCTL_UPHY_RST (1<<22) ++#define RSTCTL_ETH_RST (1<<23) ++#define RSTCTL_PCIE0_RST (1<<24) ++#define RSTCTL_PCIE1_RST (1<<25) ++#define RSTCTL_PCIE2_RST (1<<26) ++#define RSTCTL_AUX_STCK_RST (1<<28) ++#define RSTCTL_CRYPT_RST (1<<29) ++#define RSTCTL_SDXC_RST (1<<30) ++#define RSTCTL_PWM_RST (1<<31) ++ ++//for backward-compatible ++#define RALINK_FE_RST RSTCTL_FE_RST +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0069-arm-mediatek-add-mt7623-support-to-pmic-wrapper.patch b/target/linux/mediatek/patches/0069-arm-mediatek-add-mt7623-support-to-pmic-wrapper.patch new file mode 100644 index 0000000..b724682 --- /dev/null +++ b/target/linux/mediatek/patches/0069-arm-mediatek-add-mt7623-support-to-pmic-wrapper.patch @@ -0,0 +1,554 @@ +From 0ec1ddd9233579b6d6dc0df325e870c5560344be Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Sun, 28 Jun 2015 19:50:51 +0200 +Subject: [PATCH 69/76] arm: mediatek: add mt7623 support to pmic-wrapper + +Signed-off-by: John Crispin +--- + drivers/soc/mediatek/mtk-pmic-wrap.c | 345 +++++++++++++++++++++++++++++----- + 1 file changed, 296 insertions(+), 49 deletions(-) + +diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c +index f432291..9ff02a1 100644 +--- a/drivers/soc/mediatek/mtk-pmic-wrap.c ++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c +@@ -31,6 +31,13 @@ + #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 + #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 + ++#define PWRAP_MT7623_AUXADC_CON21 0x076C ++#define PWRAP_MT7623_AUXADC_ADC12 0x072C ++#define PWRAP_MT7623_AUXADC_ADC13 0x072E ++#define PWRAP_MT7623_AUXADC_ADC14 0x0730 ++#define PWRAP_MT7623_AUXADC_CON2 0x0746 ++#define PWRAP_MT7623_AUXADC_CON3 0x0748 ++ + /* macro for wrapper status */ + #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) + #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007) +@@ -61,32 +68,104 @@ + #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8) + + /* macro for slave device wrapper registers */ +-#define PWRAP_DEW_BASE 0xbc00 +-#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0) +-#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2) +-#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4) +-#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6) +-#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8) +-#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa) +-#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc) +-#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe) +-#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10) +-#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12) +-#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14) +-#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16) +-#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18) +-#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a) +-#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c) +-#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e) +-#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20) +-#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22) +-#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24) +-#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26) +-#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28) +-#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a) +-#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c) +-#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e) +-#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30) ++enum pwrap_dew_regs { ++ PWRAP_DEW_EVENT_OUT_EN, ++ PWRAP_DEW_DIO_EN, ++ PWRAP_DEW_EVENT_SRC_EN, ++ PWRAP_DEW_EVENT_SRC, ++ PWRAP_DEW_EVENT_FLAG, ++ PWRAP_DEW_READ_TEST, ++ PWRAP_DEW_WRITE_TEST, ++ PWRAP_DEW_CRC_EN, ++ PWRAP_DEW_CRC_VAL, ++ PWRAP_DEW_MON_GRP_SEL, ++ PWRAP_DEW_MON_FLAG_SEL, ++ PWRAP_DEW_EVENT_TEST, ++ PWRAP_DEW_CIPHER_KEY_SEL, ++ PWRAP_DEW_CIPHER_IV_SEL, ++ PWRAP_DEW_CIPHER_LOAD, ++ PWRAP_DEW_CIPHER_START, ++ PWRAP_DEW_CIPHER_RDY, ++ PWRAP_DEW_CIPHER_MODE, ++ PWRAP_DEW_CIPHER_SWRST, ++ ++ /* MT7623 only regs */ ++ PWRAP_DEW_CIPHER_EN, ++ PWRAP_DEW_RDDMY_NO, ++ ++ /* MT8173 only regs */ ++ PWRAP_DEW_CIPHER_IV0, ++ PWRAP_DEW_CIPHER_IV1, ++ PWRAP_DEW_CIPHER_IV2, ++ PWRAP_DEW_CIPHER_IV3, ++ PWRAP_DEW_CIPHER_IV4, ++ PWRAP_DEW_CIPHER_IV5, ++}; ++ ++static int mt7623_dew_regs[] = { ++ [PWRAP_DEW_DIO_EN] = 0x18a, ++ [PWRAP_DEW_READ_TEST] = 0x18c, ++ [PWRAP_DEW_WRITE_TEST] = 0x18e, ++ [PWRAP_DEW_CRC_EN] = 0x192, ++ [PWRAP_DEW_CRC_VAL] = 0x194, ++ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x198, ++ [PWRAP_DEW_CIPHER_IV_SEL] = 0x19a, ++ [PWRAP_DEW_CIPHER_EN] = 0x19c, ++ [PWRAP_DEW_CIPHER_RDY] = 0x19e, ++ [PWRAP_DEW_CIPHER_MODE] = 0x1a0, ++ [PWRAP_DEW_CIPHER_SWRST] = 0x1a2, ++ [PWRAP_DEW_RDDMY_NO] = 0x1a4, ++}; ++ ++static int mt8135_dew_regs[] = { ++ [PWRAP_DEW_EVENT_OUT_EN] = 0x0, ++ [PWRAP_DEW_DIO_EN] = 0x2, ++ [PWRAP_DEW_EVENT_SRC_EN] = 0x4, ++ [PWRAP_DEW_EVENT_SRC] = 0x6, ++ [PWRAP_DEW_EVENT_FLAG] = 0x8, ++ [PWRAP_DEW_READ_TEST] = 0xa, ++ [PWRAP_DEW_WRITE_TEST] = 0xc, ++ [PWRAP_DEW_CRC_EN] = 0xe, ++ [PWRAP_DEW_CRC_VAL] = 0x10, ++ [PWRAP_DEW_MON_GRP_SEL] = 0x12, ++ [PWRAP_DEW_MON_FLAG_SEL] = 0x14, ++ [PWRAP_DEW_EVENT_TEST] = 0x16, ++ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18, ++ [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a, ++ [PWRAP_DEW_CIPHER_LOAD] = 0x1c, ++ [PWRAP_DEW_CIPHER_START] = 0x1e, ++ [PWRAP_DEW_CIPHER_RDY] = 0x20, ++ [PWRAP_DEW_CIPHER_MODE] = 0x22, ++ [PWRAP_DEW_CIPHER_SWRST] = 0x24, ++}; ++ ++static int mt8173_dew_regs[] = { ++ [PWRAP_DEW_EVENT_OUT_EN] = 0x0, ++ [PWRAP_DEW_DIO_EN] = 0x2, ++ [PWRAP_DEW_EVENT_SRC_EN] = 0x4, ++ [PWRAP_DEW_EVENT_SRC] = 0x6, ++ [PWRAP_DEW_EVENT_FLAG] = 0x8, ++ [PWRAP_DEW_READ_TEST] = 0xa, ++ [PWRAP_DEW_WRITE_TEST] = 0xc, ++ [PWRAP_DEW_CRC_EN] = 0xe, ++ [PWRAP_DEW_CRC_VAL] = 0x10, ++ [PWRAP_DEW_MON_GRP_SEL] = 0x12, ++ [PWRAP_DEW_MON_FLAG_SEL] = 0x14, ++ [PWRAP_DEW_EVENT_TEST] = 0x16, ++ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18, ++ [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a, ++ [PWRAP_DEW_CIPHER_LOAD] = 0x1c, ++ [PWRAP_DEW_CIPHER_START] = 0x1e, ++ [PWRAP_DEW_CIPHER_RDY] = 0x20, ++ [PWRAP_DEW_CIPHER_MODE] = 0x22, ++ [PWRAP_DEW_CIPHER_SWRST] = 0x24, ++ [PWRAP_DEW_CIPHER_IV0] = 0x26, ++ [PWRAP_DEW_CIPHER_IV1] = 0x28, ++ [PWRAP_DEW_CIPHER_IV2] = 0x2a, ++ [PWRAP_DEW_CIPHER_IV3] = 0x2c, ++ [PWRAP_DEW_CIPHER_IV4] = 0x2e, ++ [PWRAP_DEW_CIPHER_IV5] = 0x30, ++}; + + enum pwrap_regs { + PWRAP_MUX_SEL, +@@ -162,7 +241,7 @@ enum pwrap_regs { + PWRAP_CIPHER_LOAD, + PWRAP_CIPHER_START, + +- /* MT8173 only regs */ ++ /* MT7623/MT8173 only regs */ + PWRAP_RDDMY, + PWRAP_SI_CK_CON, + PWRAP_DVFS_ADR0, +@@ -183,6 +262,107 @@ enum pwrap_regs { + PWRAP_DVFS_WDATA7, + PWRAP_SPMINF_STA, + PWRAP_CIPHER_EN, ++ ++ /* MT7623 only regs */ ++ PWRAP_OP_TYPE, ++ PWRAP_MSB_FIRST, ++ PWRAP_TOP_CKCON1, ++ PWRAP_TOP_CKCON1_CLR, ++ PWRAP_ADC_CMD_ADDR, ++ PWRAP_ADC_CMD, ++ PWRAP_ADC_RDY_ADDR, ++ PWRAP_ADC_RDATA_ADDR1, ++ PWRAP_ADC_RDATA_ADDR2, ++}; ++ ++static int mt7623_regs[] = { ++ [PWRAP_MUX_SEL] = 0x0, ++ [PWRAP_WRAP_EN] = 0x4, ++ [PWRAP_DIO_EN] = 0x8, ++ [PWRAP_SIDLY] = 0xc, ++ [PWRAP_OP_TYPE] = 0x10, ++ [PWRAP_MSB_FIRST] = 0x14, ++ [PWRAP_RDDMY] = 0x18, ++ [PWRAP_SI_CK_CON] = 0x1c, ++ [PWRAP_CSHEXT_WRITE] = 0x20, ++ [PWRAP_CSHEXT_READ] = 0x24, ++ [PWRAP_CSLEXT_START] = 0x28, ++ [PWRAP_CSLEXT_END] = 0x2c, ++ [PWRAP_STAUPD_PRD] = 0x30, ++ [PWRAP_STAUPD_GRPEN] = 0x34, ++ [PWRAP_STAUPD_MAN_TRIG] = 0x38, ++ [PWRAP_STAUPD_STA] = 0x3C, ++ [PWRAP_WRAP_STA] = 0x44, ++ [PWRAP_HARB_INIT] = 0x48, ++ [PWRAP_HARB_HPRIO] = 0x4c, ++ [PWRAP_HIPRIO_ARB_EN] = 0x50, ++ [PWRAP_HARB_STA0] = 0x54, ++ [PWRAP_HARB_STA1] = 0x58, ++ [PWRAP_MAN_EN] = 0x5c, ++ [PWRAP_MAN_CMD] = 0x60, ++ [PWRAP_MAN_RDATA] = 0x6c, ++ [PWRAP_MAN_VLDCLR] = 0x68, ++ [PWRAP_WACS0_EN] = 0x6c, ++ [PWRAP_INIT_DONE0] = 0x70, ++ [PWRAP_WACS0_CMD] = 0x74, ++ [PWRAP_WACS0_RDATA] = 0x78, ++ [PWRAP_WACS0_VLDCLR] = 0x7c, ++ [PWRAP_WACS1_EN] = 0x80, ++ [PWRAP_INIT_DONE1] = 0x84, ++ [PWRAP_WACS1_CMD] = 0x88, ++ [PWRAP_WACS1_RDATA] = 0x9c, ++ [PWRAP_WACS1_VLDCLR] = 0x90, ++ [PWRAP_WACS2_EN] = 0x94, ++ [PWRAP_INIT_DONE2] = 0x98, ++ [PWRAP_WACS2_CMD] = 0x9c, ++ [PWRAP_WACS2_RDATA] = 0xa0, ++ [PWRAP_WACS2_VLDCLR] = 0xa4, ++ [PWRAP_INT_EN] = 0xa8, ++ [PWRAP_INT_FLG_RAW] = 0xac, ++ [PWRAP_INT_FLG] = 0xb0, ++ [PWRAP_INT_CLR] = 0xb4, ++ [PWRAP_SIG_ADR] = 0xb8, ++ [PWRAP_SIG_MODE] = 0xbc, ++ [PWRAP_SIG_VALUE] = 0xc0, ++ [PWRAP_SIG_ERRVAL] = 0xc4, ++ [PWRAP_CRC_EN] = 0xc8, ++ [PWRAP_TIMER_EN] = 0xcc, ++ [PWRAP_TIMER_STA] = 0xd0, ++ [PWRAP_WDT_UNIT] = 0xd4, ++ [PWRAP_WDT_SRC_EN] = 0xd8, ++ [PWRAP_WDT_FLG] = 0xdc, ++ [PWRAP_DEBUG_INT_SEL] = 0xe0, ++ [PWRAP_DVFS_ADR0] = 0xe4, ++ [PWRAP_DVFS_WDATA0] = 0xe8, ++ [PWRAP_DVFS_ADR1] = 0xec, ++ [PWRAP_DVFS_WDATA1] = 0xf0, ++ [PWRAP_DVFS_ADR2] = 0xf4, ++ [PWRAP_DVFS_WDATA2] = 0xf8, ++ [PWRAP_DVFS_ADR3] = 0xfc, ++ [PWRAP_DVFS_WDATA3] = 0x100, ++ [PWRAP_DVFS_ADR4] = 0x104, ++ [PWRAP_DVFS_WDATA4] = 0x108, ++ [PWRAP_DVFS_ADR5] = 0x10c, ++ [PWRAP_DVFS_WDATA5] = 0x110, ++ [PWRAP_DVFS_ADR6] = 0x114, ++ [PWRAP_DVFS_WDATA6] = 0x118, ++ [PWRAP_DVFS_ADR7] = 0x11c, ++ [PWRAP_DVFS_WDATA7] = 0x120, ++ [PWRAP_CIPHER_KEY_SEL] = 0x124, ++ [PWRAP_TOP_CKCON1] = 0x126, ++ [PWRAP_CIPHER_IV_SEL] = 0x128, ++ [PWRAP_TOP_CKCON1_CLR] = 0x12a, ++ [PWRAP_CIPHER_EN] = 0x12c, ++ [PWRAP_CIPHER_RDY] = 0x130, ++ [PWRAP_CIPHER_MODE] = 0x134, ++ [PWRAP_CIPHER_SWRST] = 0x138, ++ [PWRAP_DCM_EN] = 0x13c, ++ [PWRAP_DCM_DBC_PRD] = 0x140, ++ [PWRAP_ADC_CMD_ADDR] = 0x144, ++ [PWRAP_ADC_CMD] = 0x148, ++ [PWRAP_ADC_RDY_ADDR] = 0x14C, ++ [PWRAP_ADC_RDATA_ADDR1] = 0x150, ++ [PWRAP_ADC_RDATA_ADDR2] = 0x154, + }; + + static int mt8173_regs[] = { +@@ -341,24 +521,39 @@ static int mt8135_regs[] = { + }; + + enum pwrap_type { ++ PWRAP_MT7623, + PWRAP_MT8135, + PWRAP_MT8173, + }; + + struct pmic_wrapper_type { + int *regs; ++ int *dew_regs; ++ u32 dew_base; + enum pwrap_type type; + u32 arb_en_all; + }; + ++static struct pmic_wrapper_type pwrap_mt7623 = { ++ .regs = mt7623_regs, ++ .dew_regs = mt7623_dew_regs, ++ .dew_base = 0x0, ++ .type = PWRAP_MT7623, ++ .arb_en_all = 0x3f, ++}; ++ + static struct pmic_wrapper_type pwrap_mt8135 = { + .regs = mt8135_regs, ++ .dew_regs = mt8135_dew_regs, ++ .dew_base = 0xbc00, + .type = PWRAP_MT8135, + .arb_en_all = 0x1ff, + }; + + static struct pmic_wrapper_type pwrap_mt8173 = { + .regs = mt8173_regs, ++ .dew_regs = mt8173_dew_regs, ++ .dew_base = 0xbc00, + .type = PWRAP_MT8173, + .arb_en_all = 0x3f, + }; +@@ -368,6 +563,8 @@ struct pmic_wrapper { + void __iomem *base; + struct regmap *regmap; + int *regs; ++ int *dew_regs; ++ u32 dew_base; + enum pwrap_type type; + u32 arb_en_all; + struct clk *clk_spi; +@@ -378,6 +575,11 @@ struct pmic_wrapper { + void __iomem *bridge_base; + }; + ++static inline int pwrap_is_mt7623(struct pmic_wrapper *wrp) ++{ ++ return wrp->type == PWRAP_MT7623; ++} ++ + static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp) + { + return wrp->type == PWRAP_MT8135; +@@ -475,6 +677,16 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) + return 0; + } + ++static int pwrap_dew_write(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg, u32 wdata) ++{ ++ return pwrap_write(wrp, wrp->dew_base + wrp->dew_regs[reg], wdata); ++} ++ ++static int pwrap_dew_read(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg, u32 *rdata) ++{ ++ return pwrap_read(wrp, wrp->dew_base + wrp->dew_regs[reg], rdata); ++} ++ + static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata) + { + return pwrap_read(context, adr, rdata); +@@ -535,7 +747,7 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp) + + for (i = 0; i < 4; i++) { + pwrap_writel(wrp, i, PWRAP_SIDLY); +- pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata); ++ pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata); + if (rdata == PWRAP_DEW_READ_TEST_VAL) { + dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i); + pass |= 1 << i; +@@ -561,6 +773,14 @@ static int pwrap_init_reg_clock(struct pmic_wrapper *wrp) + pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ); + pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START); + pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END); ++ } else if (pwrap_is_mt7623(wrp)) { ++ pwrap_writel(wrp, 0x3, PWRAP_TOP_CKCON1_CLR); ++ pwrap_dew_write(wrp, 0x8, PWRAP_DEW_RDDMY_NO); ++ pwrap_writel(wrp, 0x8, PWRAP_RDDMY); ++ pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE); ++ pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ); ++ pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START); ++ pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END); + } else { + pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE); + pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ); +@@ -581,7 +801,7 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) + u32 rdata; + int ret; + +- ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata); ++ ret = pwrap_dew_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata); + if (ret) + return 0; + +@@ -606,12 +826,16 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) + } + + /* Config cipher mode @PMIC */ +- pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1); +- pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0); +- pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1); +- pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2); +- pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1); +- pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1); ++ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1); ++ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0); ++ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1); ++ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2); ++ if (pwrap_is_mt7623(wrp)) { ++ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_EN, 0x1); ++ } else { ++ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1); ++ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_START, 0x1); ++ } + + /* wait for cipher data ready@AP */ + ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready); +@@ -628,7 +852,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) + } + + /* wait for cipher mode idle */ +- pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1); ++ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1); + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle); + if (ret) { + dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret); +@@ -638,8 +862,8 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) + pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE); + + /* Write Test */ +- if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) || +- pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) || ++ if (pwrap_dew_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) || ++ pwrap_dew_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) || + (rdata != PWRAP_DEW_WRITE_TEST_VAL)) { + dev_err(wrp->dev, "rdata=0x%04X\n", rdata); + return -EFAULT; +@@ -657,12 +881,17 @@ static int pwrap_init(struct pmic_wrapper *wrp) + if (wrp->rstc_bridge) + reset_control_reset(wrp->rstc_bridge); + +- if (pwrap_is_mt8173(wrp)) { ++ if (pwrap_is_mt7623(wrp) || pwrap_is_mt8173(wrp)) { + /* Enable DCM */ + pwrap_writel(wrp, 3, PWRAP_DCM_EN); + pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); + } + ++ if (pwrap_is_mt7623(wrp)) { ++ pwrap_writel(wrp, 0, PWRAP_OP_TYPE); ++ pwrap_writel(wrp, 1, PWRAP_MSB_FIRST); ++ } ++ + /* Reset SPI slave */ + ret = pwrap_reset_spislave(wrp); + if (ret) +@@ -674,6 +903,9 @@ static int pwrap_init(struct pmic_wrapper *wrp) + + pwrap_writel(wrp, 1, PWRAP_WACS2_EN); + ++ if (pwrap_is_mt7623(wrp)) ++ pwrap_writel(wrp, 0xf, PWRAP_RDDMY); ++ + ret = pwrap_init_reg_clock(wrp); + if (ret) + return ret; +@@ -684,7 +916,7 @@ static int pwrap_init(struct pmic_wrapper *wrp) + return ret; + + /* Enable dual IO mode */ +- pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1); ++ pwrap_dew_write(wrp, PWRAP_DEW_DIO_EN, 1); + + /* Check IDLE & INIT_DONE in advance */ + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle); +@@ -696,7 +928,7 @@ static int pwrap_init(struct pmic_wrapper *wrp) + pwrap_writel(wrp, 1, PWRAP_DIO_EN); + + /* Read Test */ +- pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata); ++ pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata); + if (rdata != PWRAP_DEW_READ_TEST_VAL) { + dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n", + PWRAP_DEW_READ_TEST_VAL, rdata); +@@ -709,12 +941,13 @@ static int pwrap_init(struct pmic_wrapper *wrp) + return ret; + + /* Signature checking - using CRC */ +- if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1)) ++ if (pwrap_dew_write(wrp, PWRAP_DEW_CRC_EN, 0x1)) + return -EFAULT; + + pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); + pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); +- pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR); ++ pwrap_writel(wrp, wrp->dew_base + wrp->dew_regs[PWRAP_DEW_CRC_VAL], ++ PWRAP_SIG_ADR); + pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN); + + if (pwrap_is_mt8135(wrp)) +@@ -728,7 +961,16 @@ static int pwrap_init(struct pmic_wrapper *wrp) + pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT); + pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN); + pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN); +- pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN); ++// pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN); ++ pwrap_writel(wrp, ~(BIT(31) | BIT(2)), PWRAP_INT_EN); ++ ++ if (pwrap_is_mt7623(wrp)) { ++ pwrap_writel(wrp, PWRAP_MT7623_AUXADC_CON21, PWRAP_ADC_CMD_ADDR); ++ pwrap_writel(wrp, 0x8000, PWRAP_ADC_CMD); ++ pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC12, PWRAP_ADC_RDY_ADDR); ++ pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC13, PWRAP_ADC_RDATA_ADDR1); ++ pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC14, PWRAP_ADC_RDATA_ADDR2); ++ } + + if (pwrap_is_mt8135(wrp)) { + /* enable pwrap events and pwrap bridge in AP side */ +@@ -743,15 +985,15 @@ static int pwrap_init(struct pmic_wrapper *wrp) + writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); + + /* enable PMIC event out and sources */ +- if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) || +- pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) { ++ if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) || ++ pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) { + dev_err(wrp->dev, "enable dewrap fail\n"); + return -EFAULT; + } +- } else { ++ } else if (!pwrap_is_mt7623(wrp)) { + /* PMIC_DEWRAP enables */ +- if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) || +- pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) { ++ if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) || ++ pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) { + dev_err(wrp->dev, "enable dewrap fail\n"); + return -EFAULT; + } +@@ -795,6 +1037,9 @@ static const struct regmap_config pwrap_regmap_config = { + + static struct of_device_id of_pwrap_match_tbl[] = { + { ++ .compatible = "mediatek,mt7623-pwrap", ++ .data = &pwrap_mt7623, ++ }, { + .compatible = "mediatek,mt8135-pwrap", + .data = &pwrap_mt8135, + }, { +@@ -824,6 +1069,8 @@ static int pwrap_probe(struct platform_device *pdev) + + type = of_id->data; + wrp->regs = type->regs; ++ wrp->dew_regs = type->dew_regs; ++ wrp->dew_base = type->dew_base; + wrp->type = type->type; + wrp->arb_en_all = type->arb_en_all; + wrp->dev = &pdev->dev; +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0070-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch b/target/linux/mediatek/patches/0070-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch new file mode 100644 index 0000000..87de0f9 --- /dev/null +++ b/target/linux/mediatek/patches/0070-clk-mediatek-Export-CPU-mux-clocks-for-CPU-frequency.patch @@ -0,0 +1,199 @@ +From ac825c0dd7370ae1b9a1a4346f895728e09d9cc7 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Wed, 1 Jul 2015 07:58:44 +0200 +Subject: [PATCH 70/76] clk: mediatek: Export CPU mux clocks for CPU frequency + control + +This patch adds CPU mux clocks which are used by Mediatek cpufreq driver +for intermediate clock source switching. + +Changes in v3: +- Rebase to 4.2-rc1 +- Fix some issues of v2 + +Changes in v2: +- Remove use of .determine_rate callback + +Signed-off-by: Pi-Cheng Chen +--- + drivers/clk/mediatek/Makefile | 2 +- + drivers/clk/mediatek/clk-cpumux.c | 119 +++++++++++++++++++++++++++++++++++++ + drivers/clk/mediatek/clk-cpumux.h | 30 ++++++++++ + 3 files changed, 150 insertions(+), 1 deletion(-) + create mode 100644 drivers/clk/mediatek/clk-cpumux.c + create mode 100644 drivers/clk/mediatek/clk-cpumux.h + +diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile +index 19a3763..fe07e26 100644 +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -1,4 +1,4 @@ +-obj-y += clk-mtk.o clk-pll.o clk-gate.o ++obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-cpumux.o + obj-$(CONFIG_RESET_CONTROLLER) += reset.o + obj-y += clk-mt7623.o + obj-y += clk-mt8135.o +diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c +new file mode 100644 +index 0000000..593df45 +--- /dev/null ++++ b/drivers/clk/mediatek/clk-cpumux.c +@@ -0,0 +1,119 @@ ++/* ++ * Copyright (c) 2015 Linaro Ltd. ++ * Author: Pi-Cheng Chen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-cpumux.h" ++ ++static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw) ++{ ++ return container_of(_hw, struct mtk_clk_cpumux, hw); ++} ++ ++static u8 clk_cpumux_get_parent(struct clk_hw *hw) ++{ ++ struct mtk_clk_cpumux *mux = to_clk_mux(hw); ++ int num_parents = __clk_get_num_parents(hw->clk); ++ unsigned int val; ++ ++ regmap_read(mux->regmap, mux->reg, &val); ++ ++ val >>= mux->shift; ++ val &= mux->mask; ++ ++ if (val >= num_parents) ++ return -EINVAL; ++ ++ return val; ++} ++ ++static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct mtk_clk_cpumux *mux = to_clk_mux(hw); ++ u32 mask, val; ++ ++ val = index << mux->shift; ++ mask = mux->mask << mux->shift; ++ ++ return regmap_update_bits(mux->regmap, mux->reg, mask, val); ++} ++ ++static const struct clk_ops clk_cpumux_ops = { ++ .get_parent = clk_cpumux_get_parent, ++ .set_parent = clk_cpumux_set_parent, ++}; ++ ++static struct clk *mtk_clk_register_cpumux(const struct mtk_composite *mux, ++ struct regmap *regmap) ++{ ++ struct mtk_clk_cpumux *cpumux; ++ struct clk *clk; ++ struct clk_init_data init; ++ ++ cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL); ++ if (!cpumux) ++ return ERR_PTR(-ENOMEM); ++ ++ init.name = mux->name; ++ init.ops = &clk_cpumux_ops; ++ init.parent_names = mux->parent_names; ++ init.num_parents = mux->num_parents; ++ init.flags = mux->flags; ++ ++ cpumux->reg = mux->mux_reg; ++ cpumux->shift = mux->mux_shift; ++ cpumux->mask = BIT(mux->mux_width) - 1; ++ cpumux->regmap = regmap; ++ cpumux->hw.init = &init; ++ ++ clk = clk_register(NULL, &cpumux->hw); ++ if (IS_ERR(clk)) ++ kfree(cpumux); ++ ++ return clk; ++} ++ ++int mtk_clk_register_cpumuxes(struct device_node *node, ++ const struct mtk_composite *clks, int num, ++ struct clk_onecell_data *clk_data) ++{ ++ int i; ++ struct clk *clk; ++ struct regmap *regmap; ++ ++ regmap = syscon_node_to_regmap(node); ++ if (IS_ERR(regmap)) { ++ pr_err("Cannot find regmap for %s: %d\n", node->full_name, ++ PTR_ERR(regmap)); ++ return PTR_ERR(regmap); ++ } ++ ++ for (i = 0; i < num; i++) { ++ const struct mtk_composite *mux = &clks[i]; ++ ++ clk = mtk_clk_register_cpumux(mux, regmap); ++ if (IS_ERR(clk)) { ++ pr_err("Failed to register clk %s: %ld\n", ++ mux->name, PTR_ERR(clk)); ++ continue; ++ } ++ ++ clk_data->clks[mux->id] = clk; ++ } ++ ++ return 0; ++} +diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h +new file mode 100644 +index 0000000..dddaad5 +--- /dev/null ++++ b/drivers/clk/mediatek/clk-cpumux.h +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (c) 2015 Linaro Ltd. ++ * Author: Pi-Cheng Chen ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __DRV_CLK_CPUMUX_H ++#define __DRV_CLK_CPUMUX_H ++ ++struct mtk_clk_cpumux { ++ struct clk_hw hw; ++ struct regmap *regmap; ++ u32 reg; ++ u32 mask; ++ u8 shift; ++}; ++ ++int mtk_clk_register_cpumuxes(struct device_node *node, ++ const struct mtk_composite *clks, int num, ++ struct clk_onecell_data *clk_data); ++ ++#endif /* __DRV_CLK_CPUMUX_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0071-clk.patch b/target/linux/mediatek/patches/0071-clk.patch new file mode 100644 index 0000000..f920dce --- /dev/null +++ b/target/linux/mediatek/patches/0071-clk.patch @@ -0,0 +1,342 @@ +From c3a3617a8c37b43db7ff622a31f171d3ce870173 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jul 2015 05:44:57 +0200 +Subject: [PATCH 71/76] clk + +--- + drivers/clk/mediatek/clk-mt7623.c | 194 ++++++++++++++++--------------------- + 1 file changed, 83 insertions(+), 111 deletions(-) + +diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c +index 07843bb..d46b2ad 100644 +--- a/drivers/clk/mediatek/clk-mt7623.c ++++ b/drivers/clk/mediatek/clk-mt7623.c +@@ -20,6 +20,7 @@ + + #include "clk-mtk.h" + #include "clk-gate.h" ++#include "clk-cpumux.h" + + static DEFINE_SPINLOCK(mt7623_clk_lock); + +@@ -37,18 +38,11 @@ static void mtk_clk_enable_critical(void) + clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]); + } + +-static const struct mtk_fixed_factor root_clk_alias[] __initconst = { +- FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1), +- FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1), +- FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), +- FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), +-}; +- + static const struct mtk_fixed_factor top_divs[] __initconst = { +- FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_650m", "mainpll", 1, 2), +- FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_433p3m", "mainpll", 1, 3), +- FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_260m", "mainpll", 1, 5), +- FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_185p6m", "mainpll", 1, 7), ++ FACTOR(CLK_TOP_MAINPLL_650M, "mainpll_650m", "mainpll", 1, 2), ++ FACTOR(CLK_TOP_MAINPLL_433P3M, "mainpll_433p3m", "mainpll", 1, 3), ++ FACTOR(CLK_TOP_MAINPLL_260M, "mainpll_260m", "mainpll", 1, 5), ++ FACTOR(CLK_TOP_MAINPLL_185P6M, "mainpll_185p6m", "mainpll", 1, 7), + + FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2), + FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3), +@@ -61,13 +55,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { + FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll", 1, 16), + FACTOR(CLK_TOP_AUDPLL_24, "audpll_d24", "audpll", 1, 24), + +- FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), +- FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), +- FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), +- FACTOR(CLK_TOP_LVDS_ETH, "lvdspll_eth", "lvdspll", 1, 16), +- +- FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), +- + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), + + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll_650m", 1, 2), +@@ -85,9 +72,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_260m", 1, 1), + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll_185p6m", 1, 1), + +- FACTOR(CLK_TOP_TVDPLL_d2, "tvdpll_d2", "tvdpll", 1, 2), +- FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), +- + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4), + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8), +@@ -110,9 +94,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { + + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1), + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1), +- +- +- FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), + }; + + static const char * const axi_parents[] __initconst = { +@@ -155,18 +136,6 @@ static const char * const pwm_parents[] __initconst = { + "univpll1_d4", + }; + +-static const char * const vdec_parents[] __initconst = { +- "clk26m", +- "syspll1_d2", +- "syspll_d5", +- "syspll1_d4", +- "univpll_d5", +- "univpll2_d2", +- "univpll2_d4", +- "msdcpll_d2", +- "mmpll_d2", +-}; +- + static const char * const mfg_parents[] __initconst = { + "clk26m", + "mmpll_ck", +@@ -178,17 +147,6 @@ static const char * const mfg_parents[] __initconst = { + "univpll1_d2", + }; + +-static const char * const cam_parents[] __initconst = { +- "clk26m", +- "univpll_d26", +- "univpll2_d2", +- "syspll3_d2", +- "syspll3_d4", +- "msdcpll_d2", +- "mmpll_d2", +- "clk26m", +-}; +- + static const char * const uart_parents[] __initconst = { + "clk26m", + "univpll2_d8", +@@ -277,35 +235,6 @@ static const char * const scp_parents[] __initconst = { + "dmpll_d4", + }; + +-static const char * const dpi0_parents[] __initconst = { +- "clk26m", +- "mipipll", +- "mipipll_d2", +- "mipipll_d4", +- "lvdspll", +- "lvdspll_d2", +- "lvdspll_d4", +- "lvdspll_d8", +-}; +- +-static const char * const dpi1_parents[] __initconst = { +- "clk26m", +- "tvdpll", +- "tvdpll_d2", +- "tvdpll_d4", +-}; +- +-static const char * const tve_parents[] __initconst = { +- "clk26m", +- "mipipll", +- "mipipll_d2", +- "mipipll_d4", +- "clk26m", +- "tvdpll", +- "tvdpll_d2", +- "tvdpll_d4", +-}; +- + static const char * const apll_parents[] __initconst = { + "clk26m", + "audpll", +@@ -317,17 +246,6 @@ static const char * const apll_parents[] __initconst = { + "clk26m", + }; + +-static const char * const dpilvds_parents[] __initconst = { +- "clk26m", +- "lvdspll", +- "lvdspll_d2", +- "lvdspll_d4", +- "lvdspll_d8", +- "fpc_ck", +- "clk26m", +- "clk26m", +-}; +- + static const char * const rtc_parents[] __initconst = { + "clk32k", + "external_32k", +@@ -367,9 +285,7 @@ static const struct mtk_composite top_muxes[] __initconst = { + 0x0140, 24, 3, INVALID_MUX_GATE_BIT), + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), +- MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15), + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 16, 3, 23), +- MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0050, 24, 3, 31), + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 8, 3, 15), +@@ -384,12 +300,8 @@ static const struct mtk_composite top_muxes[] __initconst = { + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmic_spi_parents, 0x0080, 0, 4, 7), + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15), +- MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23), +- MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0080, 24, 2, 31), + /* CLK_CFG_5 */ +- MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7), + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0090, 16, 3, 23), +- MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0090, 24, 3, 31), + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00a0, 0, 2, 7), + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00a0, 8, 3, 15), +@@ -428,6 +340,17 @@ static const struct mtk_gate infra_clks[] __initconst = { + GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), + }; + ++static const char * const ca7_parents[] __initconst = { ++ "clk26m", ++ "armpll", ++ "mainpll", ++ "univpll" ++}; ++ ++static struct mtk_composite cpu_muxes[] __initdata = { ++ MUX(CLK_INFRA_CA7SEL, "infra_ca7_sel", ca7_parents, 0x0000, 2, 2), ++}; ++ + static const struct mtk_gate_regs peri0_cg_regs = { + .set_ofs = 0x0008, + .clr_ofs = 0x0010, +@@ -499,6 +422,29 @@ static const struct mtk_gate peri_gates[] __initconst = { + GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "axi_sel", 2), + }; + ++static const struct mtk_gate_regs hifsys_cg_regs = { ++ .set_ofs = 0x0034, ++ .clr_ofs = 0x0014, ++ .sta_ofs = 0x0038, ++}; ++ ++#define GATE_HIFSYS(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &hifsys_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate hifsys_gates[] __initconst = { ++ GATE_HIFSYS(CLK_HIFSYS_USB0_PHY, "usb0_phy_ck", "axi_sel", 21), ++ GATE_HIFSYS(CLK_HIFSYS_USB1_PHY, "usb1_phy_ck", "axi_sel", 22), ++ GATE_HIFSYS(CLK_HIFSYS_PCIE0, "pcie0_ck", "axi_sel", 24), ++ GATE_HIFSYS(CLK_HIFSYS_PCIE1, "pcie1_ck", "axi_sel", 25), ++ GATE_HIFSYS(CLK_HIFSYS_PCIE2, "pcie2_ck", "axi_sel", 26), ++}; ++ + static const char * const uart_ck_sel_parents[] __initconst = { + "clk26m", + "uart_sel", +@@ -525,10 +471,9 @@ static void __init mtk_topckgen_init(struct device_node *node) + + mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); + +- mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, +- &mt7623_clk_lock, clk_data); ++ &mt7623_clk_lock, clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) +@@ -547,7 +492,10 @@ static void __init mtk_infrasys_init(struct device_node *node) + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), +- clk_data); ++ clk_data); ++ ++ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), ++ clk_data); + + clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]); + +@@ -588,35 +536,59 @@ static void __init mtk_pericfg_init(struct device_node *node) + } + CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt7623-pericfg", mtk_pericfg_init); + +-#define MT7623_PLL_FMAX (2000 * MHZ) +-#define CON0_MT7623_RST_BAR BIT(27) ++static void __init mtk_hifsys_init(struct device_node *node) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ void __iomem *base; ++ ++ base = of_iomap(node, 0); ++ if (!base) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return; ++ } ++ ++ clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR_CLK); ++ ++ mtk_clk_register_gates(node, hifsys_gates, ARRAY_SIZE(hifsys_gates), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 1, 0x34); ++} ++CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt7623-hifsys", mtk_hifsys_init); ++ ++#define MT7623_PLL_FMAX (1300 * MHZ) ++#define CON0_MT7623_RST_BAR BIT(24) + +-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ ++#define PLL(_id, _name, _con0_reg, _con1_reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pcw_shift, _pd_shift) { \ + .id = _id, \ + .name = _name, \ +- .reg = _reg, \ ++ .reg = _con0_reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT7623_RST_BAR, \ + .fmax = MT7623_PLL_FMAX, \ + .pcwbits = _pcwbits, \ +- .pd_reg = _pd_reg, \ ++ .pd_reg = _con0_reg, \ + .pd_shift = _pd_shift, \ +- .tuner_reg = _tuner_reg, \ +- .pcw_reg = _pcw_reg, \ ++ .pcw_reg = _con1_reg, \ + .pcw_shift = _pcw_shift, \ + } + + static const struct mtk_pll_data plls[] = { +- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0), +- PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0x214, 6, 0x0, 0x214, 0), +- PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 0x224, 6, 0x0, 0x224, 0), +- PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 21, 0x254, 6, 0x0, 0x258, 0), +- PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 6, 0x0, 0x244, 0), +- PLL(CLK_APMIXED_AUDPLL, "audpll", 0x250, 0x25c, 0x00000001, 0, 31, 0x2e8, 6, 0x2f8, 0x254, 0), +- PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x260, 0x26c, 0x00000001, 0, 31, 0x294, 6, 0x0, 0x298, 0), +- PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x270, 0x27c, 0x00000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0), ++ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x204, 0x20c, 0x00000001, 0, 21, 0, 4 ), ++ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x214, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0, 4 ), ++ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x224, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 14, 4 ), ++ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x244, 0x24c, 0x00000001, 0, 21, 0, 4 ), ++ PLL(CLK_APMIXED_AUDPLL, "audpll", 0x270, 0x274, 0x27c, 0x00000001, 0, 31, 0, 4 ), ++ PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x284, 0x28c, 0x00000001, 0, 31, 0, 4 ), ++ PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x294, 0x29c, 0x00000001, 0, 31, 0, 4 ), + }; + + static void __init mtk_apmixedsys_init(struct device_node *node) +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0072-mfd.patch b/target/linux/mediatek/patches/0072-mfd.patch new file mode 100644 index 0000000..cbcadb7 --- /dev/null +++ b/target/linux/mediatek/patches/0072-mfd.patch @@ -0,0 +1,1591 @@ +From 1a4dcc30578512d687528adcf963203faee50d83 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jul 2015 05:45:17 +0200 +Subject: [PATCH 72/76] mfd + +--- + drivers/mfd/mt6323-core.c | 168 +++---- + drivers/regulator/mt6323-regulator.c | 218 ++++---- + include/linux/mfd/mt6323/core.h | 76 +-- + include/linux/mfd/mt6323/registers.h | 745 +++++++++++++++------------- + include/linux/regulator/mt6323-regulator.h | 37 ++ + 5 files changed, 636 insertions(+), 608 deletions(-) + create mode 100644 include/linux/regulator/mt6323-regulator.h + +diff --git a/drivers/mfd/mt6323-core.c b/drivers/mfd/mt6323-core.c +index 012c620..9b7f5b9 100644 +--- a/drivers/mfd/mt6323-core.c ++++ b/drivers/mfd/mt6323-core.c +@@ -18,111 +18,99 @@ + #include + #include + #include +-#include +-#include ++#include ++#include + +-static const struct mfd_cell mt6397_devs[] = { ++static const struct mfd_cell mt6323_devs[] = { + { +- .name = "mt6397-rtc", +- .of_compatible = "mediatek,mt6397-rtc", +- }, { +- .name = "mt6397-regulator", +- .of_compatible = "mediatek,mt6397-regulator", +- }, { +- .name = "mt6397-codec", +- .of_compatible = "mediatek,mt6397-codec", +- }, { +- .name = "mt6397-clk", +- .of_compatible = "mediatek,mt6397-clk", +- }, { +- .name = "mediatek-mt6397-pinctrl", +- .of_compatible = "mediatek,mt6397-pinctrl", ++ .name = "mt6323-regulator", ++ .of_compatible = "mediatek,mt6323-regulator", + }, + }; + +-static void mt6397_irq_lock(struct irq_data *data) ++static void mt6323_irq_lock(struct irq_data *data) + { +- struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); ++ struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq); + +- mutex_lock(&mt6397->irqlock); ++ mutex_lock(&mt6323->irqlock); + } + +-static void mt6397_irq_sync_unlock(struct irq_data *data) ++static void mt6323_irq_sync_unlock(struct irq_data *data) + { +- struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); ++ struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq); + +- regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]); +- regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]); ++ regmap_write(mt6323->regmap, MT6323_INT_CON0, mt6323->irq_masks_cur[0]); ++ regmap_write(mt6323->regmap, MT6323_INT_CON1, mt6323->irq_masks_cur[1]); + +- mutex_unlock(&mt6397->irqlock); ++ mutex_unlock(&mt6323->irqlock); + } + +-static void mt6397_irq_disable(struct irq_data *data) ++static void mt6323_irq_disable(struct irq_data *data) + { +- struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); ++ struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq); + int shift = data->hwirq & 0xf; + int reg = data->hwirq >> 4; + +- mt6397->irq_masks_cur[reg] &= ~BIT(shift); ++ mt6323->irq_masks_cur[reg] &= ~BIT(shift); + } + +-static void mt6397_irq_enable(struct irq_data *data) ++static void mt6323_irq_enable(struct irq_data *data) + { +- struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq); ++ struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq); + int shift = data->hwirq & 0xf; + int reg = data->hwirq >> 4; + +- mt6397->irq_masks_cur[reg] |= BIT(shift); ++ mt6323->irq_masks_cur[reg] |= BIT(shift); + } + +-static struct irq_chip mt6397_irq_chip = { +- .name = "mt6397-irq", +- .irq_bus_lock = mt6397_irq_lock, +- .irq_bus_sync_unlock = mt6397_irq_sync_unlock, +- .irq_enable = mt6397_irq_enable, +- .irq_disable = mt6397_irq_disable, ++static struct irq_chip mt6323_irq_chip = { ++ .name = "mt6323-irq", ++ .irq_bus_lock = mt6323_irq_lock, ++ .irq_bus_sync_unlock = mt6323_irq_sync_unlock, ++ .irq_enable = mt6323_irq_enable, ++ .irq_disable = mt6323_irq_disable, + }; + +-static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg, ++static void mt6323_irq_handle_reg(struct mt6323_chip *mt6323, int reg, + int irqbase) + { + unsigned int status; + int i, irq, ret; + +- ret = regmap_read(mt6397->regmap, reg, &status); ++ ret = regmap_read(mt6323->regmap, reg, &status); + if (ret) { +- dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret); ++ dev_err(mt6323->dev, "Failed to read irq status: %d\n", ret); + return; + } + + for (i = 0; i < 16; i++) { + if (status & BIT(i)) { +- irq = irq_find_mapping(mt6397->irq_domain, irqbase + i); ++ irq = irq_find_mapping(mt6323->irq_domain, irqbase + i); + if (irq) + handle_nested_irq(irq); + } + } + +- regmap_write(mt6397->regmap, reg, status); ++ regmap_write(mt6323->regmap, reg, status); + } + +-static irqreturn_t mt6397_irq_thread(int irq, void *data) ++static irqreturn_t mt6323_irq_thread(int irq, void *data) + { +- struct mt6397_chip *mt6397 = data; ++ struct mt6323_chip *mt6323 = data; + +- mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0); +- mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16); ++ mt6323_irq_handle_reg(mt6323, MT6323_INT_STATUS0, 0); ++ mt6323_irq_handle_reg(mt6323, MT6323_INT_STATUS1, 16); + + return IRQ_HANDLED; + } + +-static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq, ++static int mt6323_irq_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) + { +- struct mt6397_chip *mt6397 = d->host_data; ++ struct mt6323_chip *mt6323 = d->host_data; + +- irq_set_chip_data(irq, mt6397); +- irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq); ++ irq_set_chip_data(irq, mt6323); ++ irq_set_chip_and_handler(irq, &mt6323_irq_chip, handle_level_irq); + irq_set_nested_thread(irq, 1); + #ifdef CONFIG_ARM + set_irq_flags(irq, IRQF_VALID); +@@ -133,98 +121,98 @@ static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq, + return 0; + } + +-static struct irq_domain_ops mt6397_irq_domain_ops = { +- .map = mt6397_irq_domain_map, ++static struct irq_domain_ops mt6323_irq_domain_ops = { ++ .map = mt6323_irq_domain_map, + }; + +-static int mt6397_irq_init(struct mt6397_chip *mt6397) ++static int mt6323_irq_init(struct mt6323_chip *mt6323) + { + int ret; + +- mutex_init(&mt6397->irqlock); ++ mutex_init(&mt6323->irqlock); + + /* Mask all interrupt sources */ +- regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0); +- regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0); ++ regmap_write(mt6323->regmap, MT6323_INT_CON0, 0x0); ++ regmap_write(mt6323->regmap, MT6323_INT_CON1, 0x0); + +- mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node, +- MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397); +- if (!mt6397->irq_domain) { +- dev_err(mt6397->dev, "could not create irq domain\n"); ++ mt6323->irq_domain = irq_domain_add_linear(mt6323->dev->of_node, ++ MT6323_IRQ_NR, &mt6323_irq_domain_ops, mt6323); ++ if (!mt6323->irq_domain) { ++ dev_err(mt6323->dev, "could not create irq domain\n"); + return -ENOMEM; + } + +- ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL, +- mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397); ++ ret = devm_request_threaded_irq(mt6323->dev, mt6323->irq, NULL, ++ mt6323_irq_thread, IRQF_ONESHOT, "mt6323-pmic", mt6323); + if (ret) { +- dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n", +- mt6397->irq, ret); ++ dev_err(mt6323->dev, "failed to register irq=%d; err: %d\n", ++ mt6323->irq, ret); + return ret; + } + + return 0; + } + +-static int mt6397_probe(struct platform_device *pdev) ++static int mt6323_probe(struct platform_device *pdev) + { + int ret; +- struct mt6397_chip *mt6397; ++ struct mt6323_chip *mt6323; + +- mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL); +- if (!mt6397) ++ mt6323 = devm_kzalloc(&pdev->dev, sizeof(*mt6323), GFP_KERNEL); ++ if (!mt6323) + return -ENOMEM; + +- mt6397->dev = &pdev->dev; ++ mt6323->dev = &pdev->dev; + /* +- * mt6397 MFD is child device of soc pmic wrapper. ++ * mt6323 MFD is child device of soc pmic wrapper. + * Regmap is set from its parent. + */ +- mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL); +- if (!mt6397->regmap) ++ mt6323->regmap = dev_get_regmap(pdev->dev.parent, NULL); ++ if (!mt6323->regmap) + return -ENODEV; + +- platform_set_drvdata(pdev, mt6397); ++ platform_set_drvdata(pdev, mt6323); + +- mt6397->irq = platform_get_irq(pdev, 0); +- if (mt6397->irq > 0) { +- ret = mt6397_irq_init(mt6397); ++ mt6323->irq = platform_get_irq(pdev, 0); ++ if (mt6323->irq > 0) { ++ ret = mt6323_irq_init(mt6323); + if (ret) + return ret; + } + +- ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs, +- ARRAY_SIZE(mt6397_devs), NULL, 0, NULL); ++ ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs, ++ ARRAY_SIZE(mt6323_devs), NULL, 0, NULL); + if (ret) + dev_err(&pdev->dev, "failed to add child devices: %d\n", ret); + + return ret; + } + +-static int mt6397_remove(struct platform_device *pdev) ++static int mt6323_remove(struct platform_device *pdev) + { + mfd_remove_devices(&pdev->dev); + + return 0; + } + +-static const struct of_device_id mt6397_of_match[] = { +- { .compatible = "mediatek,mt6397" }, ++static const struct of_device_id mt6323_of_match[] = { ++ { .compatible = "mediatek,mt6323" }, + { } + }; +-MODULE_DEVICE_TABLE(of, mt6397_of_match); ++MODULE_DEVICE_TABLE(of, mt6323_of_match); + +-static struct platform_driver mt6397_driver = { +- .probe = mt6397_probe, +- .remove = mt6397_remove, ++static struct platform_driver mt6323_driver = { ++ .probe = mt6323_probe, ++ .remove = mt6323_remove, + .driver = { +- .name = "mt6397", +- .of_match_table = of_match_ptr(mt6397_of_match), ++ .name = "mt6323", ++ .of_match_table = of_match_ptr(mt6323_of_match), + }, + }; + +-module_platform_driver(mt6397_driver); ++module_platform_driver(mt6323_driver); + + MODULE_AUTHOR("Flora Fu, MediaTek"); +-MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC"); ++MODULE_DESCRIPTION("Driver for MediaTek MT6323 PMIC"); + MODULE_LICENSE("GPL"); +-MODULE_ALIAS("platform:mt6397"); ++MODULE_ALIAS("platform:mt6323"); +diff --git a/drivers/regulator/mt6323-regulator.c b/drivers/regulator/mt6323-regulator.c +index a5b2f47..f5e3f67 100644 +--- a/drivers/regulator/mt6323-regulator.c ++++ b/drivers/regulator/mt6323-regulator.c +@@ -16,15 +16,15 @@ + #include + #include + #include +-#include +-#include ++#include ++#include + #include + #include +-#include ++#include + #include + + /* +- * MT6397 regulators' information ++ * MT6323 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators +@@ -32,7 +32,7 @@ + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + */ +-struct mt6397_regulator_info { ++struct mt6323_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; +@@ -40,15 +40,15 @@ struct mt6397_regulator_info { + u32 vselctrl_mask; + }; + +-#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ ++#define MT6323_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl) \ +-[MT6397_ID_##vreg] = { \ ++[MT6323_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ +- .ops = &mt6397_volt_range_ops, \ ++ .ops = &mt6323_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ +- .id = MT6397_ID_##vreg, \ ++ .id = MT6323_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = (max - min)/step + 1, \ + .linear_ranges = volt_ranges, \ +@@ -64,15 +64,15 @@ struct mt6397_regulator_info { + .vselctrl_mask = BIT(1), \ + } + +-#define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ ++#define MT6323_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ + vosel_mask) \ +-[MT6397_ID_##vreg] = { \ ++[MT6323_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ +- .ops = &mt6397_volt_table_ops, \ ++ .ops = &mt6323_volt_table_ops, \ + .type = REGULATOR_VOLTAGE, \ +- .id = MT6397_ID_##vreg, \ ++ .id = MT6323_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ +@@ -84,14 +84,14 @@ struct mt6397_regulator_info { + .qi = BIT(15), \ + } + +-#define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \ +-[MT6397_ID_##vreg] = { \ ++#define MT6323_REG_FIXED(match, vreg, enreg, enbit, volt) \ ++[MT6323_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ +- .ops = &mt6397_volt_fixed_ops, \ ++ .ops = &mt6323_volt_fixed_ops, \ + .type = REGULATOR_VOLTAGE, \ +- .id = MT6397_ID_##vreg, \ ++ .id = MT6323_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = enreg, \ +@@ -106,50 +106,34 @@ static const struct regulator_linear_range buck_volt_range1[] = { + }; + + static const struct regulator_linear_range buck_volt_range2[] = { +- REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250), ++ REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500), + }; + + static const struct regulator_linear_range buck_volt_range3[] = { +- REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000), ++ REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), + }; + + static const u32 ldo_volt_table1[] = { +- 1500000, 1800000, 2500000, 2800000, ++ 1800000, 3300000, + }; + + static const u32 ldo_volt_table2[] = { +- 1800000, 3300000, ++ 3000000, 3300000, + }; + + static const u32 ldo_volt_table3[] = { +- 3000000, 3300000, ++ 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, + }; + + static const u32 ldo_volt_table4[] = { +- 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, +-}; +- +-static const u32 ldo_volt_table5[] = { + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, + }; + +-static const u32 ldo_volt_table5_v2[] = { +- 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, +-}; +- +-static const u32 ldo_volt_table6[] = { +- 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000, +-}; +- +-static const u32 ldo_volt_table7[] = { +- 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000, +-}; +- +-static int mt6397_get_status(struct regulator_dev *rdev) ++static int mt6323_get_status(struct regulator_dev *rdev) + { + int ret; + u32 regval; +- struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); ++ struct mt6323_regulator_info *info = rdev_get_drvdata(rdev); + + ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); + if (ret != 0) { +@@ -160,7 +144,7 @@ static int mt6397_get_status(struct regulator_dev *rdev) + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; + } + +-static struct regulator_ops mt6397_volt_range_ops = { ++static struct regulator_ops mt6323_volt_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, +@@ -169,10 +153,10 @@ static struct regulator_ops mt6397_volt_range_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, +- .get_status = mt6397_get_status, ++ .get_status = mt6323_get_status, + }; + +-static struct regulator_ops mt6397_volt_table_ops = { ++static struct regulator_ops mt6323_volt_table_ops = { + .list_voltage = regulator_list_voltage_table, + .map_voltage = regulator_map_voltage_iterate, + .set_voltage_sel = regulator_set_voltage_sel_regmap, +@@ -181,90 +165,68 @@ static struct regulator_ops mt6397_volt_table_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, +- .get_status = mt6397_get_status, ++ .get_status = mt6323_get_status, + }; + +-static struct regulator_ops mt6397_volt_fixed_ops = { ++static struct regulator_ops mt6323_volt_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, +- .get_status = mt6397_get_status, ++ .get_status = mt6323_get_status, + }; + +-/* The array is indexed by id(MT6397_ID_XXX) */ +-static struct mt6397_regulator_info mt6397_regulators[] = { +- MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250, +- buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f, +- MT6397_VCA15_CON10, MT6397_VCA15_CON5), +- MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250, +- buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f, +- MT6397_VPCA7_CON10, MT6397_VPCA7_CON5), +- MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250, +- buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9, +- 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5), +- MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250, +- buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9, +- 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5), +- MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, +- buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f, +- MT6397_VCORE_CON10, MT6397_VCORE_CON5), +- MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1, +- MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f, +- MT6397_VGPU_CON10, MT6397_VGPU_CON5), +- MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2, +- MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f, +- MT6397_VDRM_CON10, MT6397_VDRM_CON5), +- MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000, +- buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f, +- MT6397_VIO18_CON10, MT6397_VIO18_CON5), +- MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000), +- MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000), +- MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1, +- MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0), +- MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000), +- MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000), +- MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2, +- MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10), +- MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3, +- MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80), +- MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3, +- MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10), +- MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4, +- MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0), +- MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5, +- MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0), +- MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5, +- MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0), +- MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5, +- MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0), +- MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6, +- MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0), +- MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5, +- MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0), +- MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7, +- MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00), ++/* The array is indexed by id(MT6323_ID_XXX) */ ++static struct mt6323_regulator_info mt6323_regulators[] = { ++ /* buck */ ++ MT6323_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250, ++ buck_volt_range1, MT6323_VPROC_CON7, MT6323_VPROC_CON9, 0x7f, ++ MT6323_VPROC_CON10, MT6323_VPROC_CON5), ++ MT6323_BUCK("buck_vsys", VSYS, 1400000, 3000000, 12500, ++ buck_volt_range2, MT6323_VSYS_CON7, MT6323_VSYS_CON9, ++ 0x7f, MT6323_VSYS_CON10, MT6323_VSYS_CON5), ++ MT6323_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, ++ buck_volt_range3, MT6323_VPA_CON7, MT6323_VPA_CON9, 0x7f, ++ MT6323_VPA_CON10, MT6323_VPA_CON5), ++ ++ /* analog */ ++ MT6323_REG_FIXED("ldo_vtcxo", VTCXO, MT6323_ANALDO_CON1, 10, 2800000), ++ MT6323_REG_FIXED("ldo_va", VA, MT6323_ANALDO_CON2, 14, 2800000), ++ MT6323_REG_FIXED("ldo_vcn28", VCN28, MT6323_ANALDO_CON19, 12, 2800000), ++ MT6323_REG_FIXED("ldo_vcn33", VCN33, MT6323_ANALDO_CON21, 12, 3300000), ++ ++ /* digital */ ++ MT6323_REG_FIXED("ldo_vio28", VIO28, MT6323_DIGLDO_CON0, 15, 2800000), ++ MT6323_REG_FIXED("ldo_vusb", VUSB, MT6323_DIGLDO_CON2, 15, 3300000), ++ MT6323_LDO("ldo_vmc", VMC, ldo_volt_table1, ++ MT6323_DIGLDO_CON3, 12, MT6323_DIGLDO_CON24, 0x10), ++ MT6323_LDO("ldo_vmch", VMCH, ldo_volt_table2, ++ MT6323_DIGLDO_CON5, 14, MT6323_DIGLDO_CON26, 0x80), ++ MT6323_LDO("ldo_vgp1", VGP1, ldo_volt_table3, ++ MT6323_DIGLDO_CON7, 15, MT6323_DIGLDO_CON28, 0xE0), ++ MT6323_LDO("ldo_vgp2", VGP2, ldo_volt_table4, ++ MT6323_DIGLDO_CON8, 15, MT6323_DIGLDO_CON29, 0xE0), + }; + +-static int mt6397_set_buck_vosel_reg(struct platform_device *pdev) ++static int mt6323_set_buck_vosel_reg(struct platform_device *pdev) + { +- struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); ++ struct mt6323_chip *mt6323 = dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + +- for (i = 0; i < MT6397_MAX_REGULATOR; i++) { +- if (mt6397_regulators[i].vselctrl_reg) { +- if (regmap_read(mt6397->regmap, +- mt6397_regulators[i].vselctrl_reg, ++ for (i = 0; i < MT6323_MAX_REGULATOR; i++) { ++ if (mt6323_regulators[i].vselctrl_reg) { ++ if (regmap_read(mt6323->regmap, ++ mt6323_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + +- if (regval & mt6397_regulators[i].vselctrl_mask) { +- mt6397_regulators[i].desc.vsel_reg = +- mt6397_regulators[i].vselon_reg; ++ if (regval & mt6323_regulators[i].vselctrl_mask) { ++ mt6323_regulators[i].desc.vsel_reg = ++ mt6323_regulators[i].vselon_reg; + } + } + } +@@ -272,44 +234,34 @@ static int mt6397_set_buck_vosel_reg(struct platform_device *pdev) + return 0; + } + +-static int mt6397_regulator_probe(struct platform_device *pdev) ++static int mt6323_regulator_probe(struct platform_device *pdev) + { +- struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); ++ struct mt6323_chip *mt6323 = dev_get_drvdata(pdev->dev.parent); + struct regulator_config config = {}; + struct regulator_dev *rdev; + int i; +- u32 reg_value, version; ++ u32 reg_value; + + /* Query buck controller to select activated voltage register part */ +- if (mt6397_set_buck_vosel_reg(pdev)) ++ if (mt6323_set_buck_vosel_reg(pdev)) + return -EIO; + + /* Read PMIC chip revision to update constraints and voltage table */ +- if (regmap_read(mt6397->regmap, MT6397_CID, ®_value) < 0) { ++ if (regmap_read(mt6323->regmap, MT6323_CID, ®_value) < 0) { + dev_err(&pdev->dev, "Failed to read Chip ID\n"); + return -EIO; + } + dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); + +- version = (reg_value & 0xFF); +- switch (version) { +- case MT6397_REGULATOR_ID91: +- mt6397_regulators[MT6397_ID_VGP2].desc.volt_table = +- ldo_volt_table5_v2; +- break; +- default: +- break; +- } +- +- for (i = 0; i < MT6397_MAX_REGULATOR; i++) { ++ for (i = 0; i < MT6323_MAX_REGULATOR; i++) { + config.dev = &pdev->dev; +- config.driver_data = &mt6397_regulators[i]; +- config.regmap = mt6397->regmap; ++ config.driver_data = &mt6323_regulators[i]; ++ config.regmap = mt6323->regmap; + rdev = devm_regulator_register(&pdev->dev, +- &mt6397_regulators[i].desc, &config); ++ &mt6323_regulators[i].desc, &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", +- mt6397_regulators[i].desc.name); ++ mt6323_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } +@@ -317,16 +269,16 @@ static int mt6397_regulator_probe(struct platform_device *pdev) + return 0; + } + +-static struct platform_driver mt6397_regulator_driver = { ++static struct platform_driver mt6323_regulator_driver = { + .driver = { +- .name = "mt6397-regulator", ++ .name = "mt6323-regulator", + }, +- .probe = mt6397_regulator_probe, ++ .probe = mt6323_regulator_probe, + }; + +-module_platform_driver(mt6397_regulator_driver); ++module_platform_driver(mt6323_regulator_driver); + + MODULE_AUTHOR("Flora Fu "); +-MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC"); ++MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6323 PMIC"); + MODULE_LICENSE("GPL"); +-MODULE_ALIAS("platform:mt6397-regulator"); ++MODULE_ALIAS("platform:mt6323-regulator"); +diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h +index cf5265b..5bb2d32 100644 +--- a/include/linux/mfd/mt6323/core.h ++++ b/include/linux/mfd/mt6323/core.h +@@ -12,46 +12,46 @@ + * GNU General Public License for more details. + */ + +-#ifndef __MFD_MT6397_CORE_H__ +-#define __MFD_MT6397_CORE_H__ ++#ifndef __MFD_MT6323_CORE_H__ ++#define __MFD_MT6323_CORE_H__ + +-enum mt6397_irq_numbers { +- MT6397_IRQ_SPKL_AB = 0, +- MT6397_IRQ_SPKR_AB, +- MT6397_IRQ_SPKL, +- MT6397_IRQ_SPKR, +- MT6397_IRQ_BAT_L, +- MT6397_IRQ_BAT_H, +- MT6397_IRQ_FG_BAT_L, +- MT6397_IRQ_FG_BAT_H, +- MT6397_IRQ_WATCHDOG, +- MT6397_IRQ_PWRKEY, +- MT6397_IRQ_THR_L, +- MT6397_IRQ_THR_H, +- MT6397_IRQ_VBATON_UNDET, +- MT6397_IRQ_BVALID_DET, +- MT6397_IRQ_CHRDET, +- MT6397_IRQ_OV, +- MT6397_IRQ_LDO, +- MT6397_IRQ_HOMEKEY, +- MT6397_IRQ_ACCDET, +- MT6397_IRQ_AUDIO, +- MT6397_IRQ_RTC, +- MT6397_IRQ_PWRKEY_RSTB, +- MT6397_IRQ_HDMI_SIFM, +- MT6397_IRQ_HDMI_CEC, +- MT6397_IRQ_VCA15, +- MT6397_IRQ_VSRMCA15, +- MT6397_IRQ_VCORE, +- MT6397_IRQ_VGPU, +- MT6397_IRQ_VIO18, +- MT6397_IRQ_VPCA7, +- MT6397_IRQ_VSRMCA7, +- MT6397_IRQ_VDRM, +- MT6397_IRQ_NR, ++enum mt6323_irq_numbers { ++ MT6323_IRQ_SPKL_AB = 0, ++ MT6323_IRQ_SPKR_AB, ++ MT6323_IRQ_SPKL, ++ MT6323_IRQ_SPKR, ++ MT6323_IRQ_BAT_L, ++ MT6323_IRQ_BAT_H, ++ MT6323_IRQ_FG_BAT_L, ++ MT6323_IRQ_FG_BAT_H, ++ MT6323_IRQ_WATCHDOG, ++ MT6323_IRQ_PWRKEY, ++ MT6323_IRQ_THR_L, ++ MT6323_IRQ_THR_H, ++ MT6323_IRQ_VBATON_UNDET, ++ MT6323_IRQ_BVALID_DET, ++ MT6323_IRQ_CHRDET, ++ MT6323_IRQ_OV, ++ MT6323_IRQ_LDO, ++ MT6323_IRQ_HOMEKEY, ++ MT6323_IRQ_ACCDET, ++ MT6323_IRQ_AUDIO, ++ MT6323_IRQ_RTC, ++ MT6323_IRQ_PWRKEY_RSTB, ++ MT6323_IRQ_HDMI_SIFM, ++ MT6323_IRQ_HDMI_CEC, ++ MT6323_IRQ_VCA15, ++ MT6323_IRQ_VSRMCA15, ++ MT6323_IRQ_VCORE, ++ MT6323_IRQ_VGPU, ++ MT6323_IRQ_VIO18, ++ MT6323_IRQ_VPCA7, ++ MT6323_IRQ_VSRMCA7, ++ MT6323_IRQ_VDRM, ++ MT6323_IRQ_NR, + }; + +-struct mt6397_chip { ++struct mt6323_chip { + struct device *dev; + struct regmap *regmap; + int irq; +@@ -61,4 +61,4 @@ struct mt6397_chip { + u16 irq_masks_cache[2]; + }; + +-#endif /* __MFD_MT6397_CORE_H__ */ ++#endif /* __MFD_MT6323_CORE_H__ */ +diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h +index f23a0a6..4ee5e1f0 100644 +--- a/include/linux/mfd/mt6323/registers.h ++++ b/include/linux/mfd/mt6323/registers.h +@@ -1,6 +1,5 @@ + /* +- * Copyright (c) 2014 MediaTek Inc. +- * Author: Flora Fu, MediaTek ++ * Copyright (c) 2015 - John Crispin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as +@@ -12,351 +11,403 @@ + * GNU General Public License for more details. + */ + +-#ifndef __MFD_MT6397_REGISTERS_H__ +-#define __MFD_MT6397_REGISTERS_H__ ++#ifndef __MFD_MT6323_REGISTERS_H__ ++#define __MFD_MT6323_REGISTERS_H__ + + /* PMIC Registers */ +-#define MT6397_CID 0x0100 +-#define MT6397_TOP_CKPDN 0x0102 +-#define MT6397_TOP_CKPDN_SET 0x0104 +-#define MT6397_TOP_CKPDN_CLR 0x0106 +-#define MT6397_TOP_CKPDN2 0x0108 +-#define MT6397_TOP_CKPDN2_SET 0x010A +-#define MT6397_TOP_CKPDN2_CLR 0x010C +-#define MT6397_TOP_GPIO_CKPDN 0x010E +-#define MT6397_TOP_RST_CON 0x0114 +-#define MT6397_WRP_CKPDN 0x011A +-#define MT6397_WRP_RST_CON 0x0120 +-#define MT6397_TOP_RST_MISC 0x0126 +-#define MT6397_TOP_CKCON1 0x0128 +-#define MT6397_TOP_CKCON2 0x012A +-#define MT6397_TOP_CKTST1 0x012C +-#define MT6397_TOP_CKTST2 0x012E +-#define MT6397_OC_DEG_EN 0x0130 +-#define MT6397_OC_CTL0 0x0132 +-#define MT6397_OC_CTL1 0x0134 +-#define MT6397_OC_CTL2 0x0136 +-#define MT6397_INT_RSV 0x0138 +-#define MT6397_TEST_CON0 0x013A +-#define MT6397_TEST_CON1 0x013C +-#define MT6397_STATUS0 0x013E +-#define MT6397_STATUS1 0x0140 +-#define MT6397_PGSTATUS 0x0142 +-#define MT6397_CHRSTATUS 0x0144 +-#define MT6397_OCSTATUS0 0x0146 +-#define MT6397_OCSTATUS1 0x0148 +-#define MT6397_OCSTATUS2 0x014A +-#define MT6397_HDMI_PAD_IE 0x014C +-#define MT6397_TEST_OUT_L 0x014E +-#define MT6397_TEST_OUT_H 0x0150 +-#define MT6397_TDSEL_CON 0x0152 +-#define MT6397_RDSEL_CON 0x0154 +-#define MT6397_GPIO_SMT_CON0 0x0156 +-#define MT6397_GPIO_SMT_CON1 0x0158 +-#define MT6397_GPIO_SMT_CON2 0x015A +-#define MT6397_GPIO_SMT_CON3 0x015C +-#define MT6397_DRV_CON0 0x015E +-#define MT6397_DRV_CON1 0x0160 +-#define MT6397_DRV_CON2 0x0162 +-#define MT6397_DRV_CON3 0x0164 +-#define MT6397_DRV_CON4 0x0166 +-#define MT6397_DRV_CON5 0x0168 +-#define MT6397_DRV_CON6 0x016A +-#define MT6397_DRV_CON7 0x016C +-#define MT6397_DRV_CON8 0x016E +-#define MT6397_DRV_CON9 0x0170 +-#define MT6397_DRV_CON10 0x0172 +-#define MT6397_DRV_CON11 0x0174 +-#define MT6397_DRV_CON12 0x0176 +-#define MT6397_INT_CON0 0x0178 +-#define MT6397_INT_CON1 0x017E +-#define MT6397_INT_STATUS0 0x0184 +-#define MT6397_INT_STATUS1 0x0186 +-#define MT6397_FQMTR_CON0 0x0188 +-#define MT6397_FQMTR_CON1 0x018A +-#define MT6397_FQMTR_CON2 0x018C +-#define MT6397_EFUSE_DOUT_0_15 0x01C4 +-#define MT6397_EFUSE_DOUT_16_31 0x01C6 +-#define MT6397_EFUSE_DOUT_32_47 0x01C8 +-#define MT6397_EFUSE_DOUT_48_63 0x01CA +-#define MT6397_SPI_CON 0x01CC +-#define MT6397_TOP_CKPDN3 0x01CE +-#define MT6397_TOP_CKCON3 0x01D4 +-#define MT6397_EFUSE_DOUT_64_79 0x01D6 +-#define MT6397_EFUSE_DOUT_80_95 0x01D8 +-#define MT6397_EFUSE_DOUT_96_111 0x01DA +-#define MT6397_EFUSE_DOUT_112_127 0x01DC +-#define MT6397_EFUSE_DOUT_128_143 0x01DE +-#define MT6397_EFUSE_DOUT_144_159 0x01E0 +-#define MT6397_EFUSE_DOUT_160_175 0x01E2 +-#define MT6397_EFUSE_DOUT_176_191 0x01E4 +-#define MT6397_EFUSE_DOUT_192_207 0x01E6 +-#define MT6397_EFUSE_DOUT_208_223 0x01E8 +-#define MT6397_EFUSE_DOUT_224_239 0x01EA +-#define MT6397_EFUSE_DOUT_240_255 0x01EC +-#define MT6397_EFUSE_DOUT_256_271 0x01EE +-#define MT6397_EFUSE_DOUT_272_287 0x01F0 +-#define MT6397_EFUSE_DOUT_288_300 0x01F2 +-#define MT6397_EFUSE_DOUT_304_319 0x01F4 +-#define MT6397_BUCK_CON0 0x0200 +-#define MT6397_BUCK_CON1 0x0202 +-#define MT6397_BUCK_CON2 0x0204 +-#define MT6397_BUCK_CON3 0x0206 +-#define MT6397_BUCK_CON4 0x0208 +-#define MT6397_BUCK_CON5 0x020A +-#define MT6397_BUCK_CON6 0x020C +-#define MT6397_BUCK_CON7 0x020E +-#define MT6397_BUCK_CON8 0x0210 +-#define MT6397_BUCK_CON9 0x0212 +-#define MT6397_VCA15_CON0 0x0214 +-#define MT6397_VCA15_CON1 0x0216 +-#define MT6397_VCA15_CON2 0x0218 +-#define MT6397_VCA15_CON3 0x021A +-#define MT6397_VCA15_CON4 0x021C +-#define MT6397_VCA15_CON5 0x021E +-#define MT6397_VCA15_CON6 0x0220 +-#define MT6397_VCA15_CON7 0x0222 +-#define MT6397_VCA15_CON8 0x0224 +-#define MT6397_VCA15_CON9 0x0226 +-#define MT6397_VCA15_CON10 0x0228 +-#define MT6397_VCA15_CON11 0x022A +-#define MT6397_VCA15_CON12 0x022C +-#define MT6397_VCA15_CON13 0x022E +-#define MT6397_VCA15_CON14 0x0230 +-#define MT6397_VCA15_CON15 0x0232 +-#define MT6397_VCA15_CON16 0x0234 +-#define MT6397_VCA15_CON17 0x0236 +-#define MT6397_VCA15_CON18 0x0238 +-#define MT6397_VSRMCA15_CON0 0x023A +-#define MT6397_VSRMCA15_CON1 0x023C +-#define MT6397_VSRMCA15_CON2 0x023E +-#define MT6397_VSRMCA15_CON3 0x0240 +-#define MT6397_VSRMCA15_CON4 0x0242 +-#define MT6397_VSRMCA15_CON5 0x0244 +-#define MT6397_VSRMCA15_CON6 0x0246 +-#define MT6397_VSRMCA15_CON7 0x0248 +-#define MT6397_VSRMCA15_CON8 0x024A +-#define MT6397_VSRMCA15_CON9 0x024C +-#define MT6397_VSRMCA15_CON10 0x024E +-#define MT6397_VSRMCA15_CON11 0x0250 +-#define MT6397_VSRMCA15_CON12 0x0252 +-#define MT6397_VSRMCA15_CON13 0x0254 +-#define MT6397_VSRMCA15_CON14 0x0256 +-#define MT6397_VSRMCA15_CON15 0x0258 +-#define MT6397_VSRMCA15_CON16 0x025A +-#define MT6397_VSRMCA15_CON17 0x025C +-#define MT6397_VSRMCA15_CON18 0x025E +-#define MT6397_VSRMCA15_CON19 0x0260 +-#define MT6397_VSRMCA15_CON20 0x0262 +-#define MT6397_VSRMCA15_CON21 0x0264 +-#define MT6397_VCORE_CON0 0x0266 +-#define MT6397_VCORE_CON1 0x0268 +-#define MT6397_VCORE_CON2 0x026A +-#define MT6397_VCORE_CON3 0x026C +-#define MT6397_VCORE_CON4 0x026E +-#define MT6397_VCORE_CON5 0x0270 +-#define MT6397_VCORE_CON6 0x0272 +-#define MT6397_VCORE_CON7 0x0274 +-#define MT6397_VCORE_CON8 0x0276 +-#define MT6397_VCORE_CON9 0x0278 +-#define MT6397_VCORE_CON10 0x027A +-#define MT6397_VCORE_CON11 0x027C +-#define MT6397_VCORE_CON12 0x027E +-#define MT6397_VCORE_CON13 0x0280 +-#define MT6397_VCORE_CON14 0x0282 +-#define MT6397_VCORE_CON15 0x0284 +-#define MT6397_VCORE_CON16 0x0286 +-#define MT6397_VCORE_CON17 0x0288 +-#define MT6397_VCORE_CON18 0x028A +-#define MT6397_VGPU_CON0 0x028C +-#define MT6397_VGPU_CON1 0x028E +-#define MT6397_VGPU_CON2 0x0290 +-#define MT6397_VGPU_CON3 0x0292 +-#define MT6397_VGPU_CON4 0x0294 +-#define MT6397_VGPU_CON5 0x0296 +-#define MT6397_VGPU_CON6 0x0298 +-#define MT6397_VGPU_CON7 0x029A +-#define MT6397_VGPU_CON8 0x029C +-#define MT6397_VGPU_CON9 0x029E +-#define MT6397_VGPU_CON10 0x02A0 +-#define MT6397_VGPU_CON11 0x02A2 +-#define MT6397_VGPU_CON12 0x02A4 +-#define MT6397_VGPU_CON13 0x02A6 +-#define MT6397_VGPU_CON14 0x02A8 +-#define MT6397_VGPU_CON15 0x02AA +-#define MT6397_VGPU_CON16 0x02AC +-#define MT6397_VGPU_CON17 0x02AE +-#define MT6397_VGPU_CON18 0x02B0 +-#define MT6397_VIO18_CON0 0x0300 +-#define MT6397_VIO18_CON1 0x0302 +-#define MT6397_VIO18_CON2 0x0304 +-#define MT6397_VIO18_CON3 0x0306 +-#define MT6397_VIO18_CON4 0x0308 +-#define MT6397_VIO18_CON5 0x030A +-#define MT6397_VIO18_CON6 0x030C +-#define MT6397_VIO18_CON7 0x030E +-#define MT6397_VIO18_CON8 0x0310 +-#define MT6397_VIO18_CON9 0x0312 +-#define MT6397_VIO18_CON10 0x0314 +-#define MT6397_VIO18_CON11 0x0316 +-#define MT6397_VIO18_CON12 0x0318 +-#define MT6397_VIO18_CON13 0x031A +-#define MT6397_VIO18_CON14 0x031C +-#define MT6397_VIO18_CON15 0x031E +-#define MT6397_VIO18_CON16 0x0320 +-#define MT6397_VIO18_CON17 0x0322 +-#define MT6397_VIO18_CON18 0x0324 +-#define MT6397_VPCA7_CON0 0x0326 +-#define MT6397_VPCA7_CON1 0x0328 +-#define MT6397_VPCA7_CON2 0x032A +-#define MT6397_VPCA7_CON3 0x032C +-#define MT6397_VPCA7_CON4 0x032E +-#define MT6397_VPCA7_CON5 0x0330 +-#define MT6397_VPCA7_CON6 0x0332 +-#define MT6397_VPCA7_CON7 0x0334 +-#define MT6397_VPCA7_CON8 0x0336 +-#define MT6397_VPCA7_CON9 0x0338 +-#define MT6397_VPCA7_CON10 0x033A +-#define MT6397_VPCA7_CON11 0x033C +-#define MT6397_VPCA7_CON12 0x033E +-#define MT6397_VPCA7_CON13 0x0340 +-#define MT6397_VPCA7_CON14 0x0342 +-#define MT6397_VPCA7_CON15 0x0344 +-#define MT6397_VPCA7_CON16 0x0346 +-#define MT6397_VPCA7_CON17 0x0348 +-#define MT6397_VPCA7_CON18 0x034A +-#define MT6397_VSRMCA7_CON0 0x034C +-#define MT6397_VSRMCA7_CON1 0x034E +-#define MT6397_VSRMCA7_CON2 0x0350 +-#define MT6397_VSRMCA7_CON3 0x0352 +-#define MT6397_VSRMCA7_CON4 0x0354 +-#define MT6397_VSRMCA7_CON5 0x0356 +-#define MT6397_VSRMCA7_CON6 0x0358 +-#define MT6397_VSRMCA7_CON7 0x035A +-#define MT6397_VSRMCA7_CON8 0x035C +-#define MT6397_VSRMCA7_CON9 0x035E +-#define MT6397_VSRMCA7_CON10 0x0360 +-#define MT6397_VSRMCA7_CON11 0x0362 +-#define MT6397_VSRMCA7_CON12 0x0364 +-#define MT6397_VSRMCA7_CON13 0x0366 +-#define MT6397_VSRMCA7_CON14 0x0368 +-#define MT6397_VSRMCA7_CON15 0x036A +-#define MT6397_VSRMCA7_CON16 0x036C +-#define MT6397_VSRMCA7_CON17 0x036E +-#define MT6397_VSRMCA7_CON18 0x0370 +-#define MT6397_VSRMCA7_CON19 0x0372 +-#define MT6397_VSRMCA7_CON20 0x0374 +-#define MT6397_VSRMCA7_CON21 0x0376 +-#define MT6397_VDRM_CON0 0x0378 +-#define MT6397_VDRM_CON1 0x037A +-#define MT6397_VDRM_CON2 0x037C +-#define MT6397_VDRM_CON3 0x037E +-#define MT6397_VDRM_CON4 0x0380 +-#define MT6397_VDRM_CON5 0x0382 +-#define MT6397_VDRM_CON6 0x0384 +-#define MT6397_VDRM_CON7 0x0386 +-#define MT6397_VDRM_CON8 0x0388 +-#define MT6397_VDRM_CON9 0x038A +-#define MT6397_VDRM_CON10 0x038C +-#define MT6397_VDRM_CON11 0x038E +-#define MT6397_VDRM_CON12 0x0390 +-#define MT6397_VDRM_CON13 0x0392 +-#define MT6397_VDRM_CON14 0x0394 +-#define MT6397_VDRM_CON15 0x0396 +-#define MT6397_VDRM_CON16 0x0398 +-#define MT6397_VDRM_CON17 0x039A +-#define MT6397_VDRM_CON18 0x039C +-#define MT6397_BUCK_K_CON0 0x039E +-#define MT6397_BUCK_K_CON1 0x03A0 +-#define MT6397_ANALDO_CON0 0x0400 +-#define MT6397_ANALDO_CON1 0x0402 +-#define MT6397_ANALDO_CON2 0x0404 +-#define MT6397_ANALDO_CON3 0x0406 +-#define MT6397_ANALDO_CON4 0x0408 +-#define MT6397_ANALDO_CON5 0x040A +-#define MT6397_ANALDO_CON6 0x040C +-#define MT6397_ANALDO_CON7 0x040E +-#define MT6397_DIGLDO_CON0 0x0410 +-#define MT6397_DIGLDO_CON1 0x0412 +-#define MT6397_DIGLDO_CON2 0x0414 +-#define MT6397_DIGLDO_CON3 0x0416 +-#define MT6397_DIGLDO_CON4 0x0418 +-#define MT6397_DIGLDO_CON5 0x041A +-#define MT6397_DIGLDO_CON6 0x041C +-#define MT6397_DIGLDO_CON7 0x041E +-#define MT6397_DIGLDO_CON8 0x0420 +-#define MT6397_DIGLDO_CON9 0x0422 +-#define MT6397_DIGLDO_CON10 0x0424 +-#define MT6397_DIGLDO_CON11 0x0426 +-#define MT6397_DIGLDO_CON12 0x0428 +-#define MT6397_DIGLDO_CON13 0x042A +-#define MT6397_DIGLDO_CON14 0x042C +-#define MT6397_DIGLDO_CON15 0x042E +-#define MT6397_DIGLDO_CON16 0x0430 +-#define MT6397_DIGLDO_CON17 0x0432 +-#define MT6397_DIGLDO_CON18 0x0434 +-#define MT6397_DIGLDO_CON19 0x0436 +-#define MT6397_DIGLDO_CON20 0x0438 +-#define MT6397_DIGLDO_CON21 0x043A +-#define MT6397_DIGLDO_CON22 0x043C +-#define MT6397_DIGLDO_CON23 0x043E +-#define MT6397_DIGLDO_CON24 0x0440 +-#define MT6397_DIGLDO_CON25 0x0442 +-#define MT6397_DIGLDO_CON26 0x0444 +-#define MT6397_DIGLDO_CON27 0x0446 +-#define MT6397_DIGLDO_CON28 0x0448 +-#define MT6397_DIGLDO_CON29 0x044A +-#define MT6397_DIGLDO_CON30 0x044C +-#define MT6397_DIGLDO_CON31 0x044E +-#define MT6397_DIGLDO_CON32 0x0450 +-#define MT6397_DIGLDO_CON33 0x045A +-#define MT6397_SPK_CON0 0x0600 +-#define MT6397_SPK_CON1 0x0602 +-#define MT6397_SPK_CON2 0x0604 +-#define MT6397_SPK_CON3 0x0606 +-#define MT6397_SPK_CON4 0x0608 +-#define MT6397_SPK_CON5 0x060A +-#define MT6397_SPK_CON6 0x060C +-#define MT6397_SPK_CON7 0x060E +-#define MT6397_SPK_CON8 0x0610 +-#define MT6397_SPK_CON9 0x0612 +-#define MT6397_SPK_CON10 0x0614 +-#define MT6397_SPK_CON11 0x0616 +-#define MT6397_AUDDAC_CON0 0x0700 +-#define MT6397_AUDBUF_CFG0 0x0702 +-#define MT6397_AUDBUF_CFG1 0x0704 +-#define MT6397_AUDBUF_CFG2 0x0706 +-#define MT6397_AUDBUF_CFG3 0x0708 +-#define MT6397_AUDBUF_CFG4 0x070A +-#define MT6397_IBIASDIST_CFG0 0x070C +-#define MT6397_AUDACCDEPOP_CFG0 0x070E +-#define MT6397_AUD_IV_CFG0 0x0710 +-#define MT6397_AUDCLKGEN_CFG0 0x0712 +-#define MT6397_AUDLDO_CFG0 0x0714 +-#define MT6397_AUDLDO_CFG1 0x0716 +-#define MT6397_AUDNVREGGLB_CFG0 0x0718 +-#define MT6397_AUD_NCP0 0x071A +-#define MT6397_AUDPREAMP_CON0 0x071C +-#define MT6397_AUDADC_CON0 0x071E +-#define MT6397_AUDADC_CON1 0x0720 +-#define MT6397_AUDADC_CON2 0x0722 +-#define MT6397_AUDADC_CON3 0x0724 +-#define MT6397_AUDADC_CON4 0x0726 +-#define MT6397_AUDADC_CON5 0x0728 +-#define MT6397_AUDADC_CON6 0x072A +-#define MT6397_AUDDIGMI_CON0 0x072C +-#define MT6397_AUDLSBUF_CON0 0x072E +-#define MT6397_AUDLSBUF_CON1 0x0730 +-#define MT6397_AUDENCSPARE_CON0 0x0732 +-#define MT6397_AUDENCCLKSQ_CON0 0x0734 +-#define MT6397_AUDPREAMPGAIN_CON0 0x0736 +-#define MT6397_ZCD_CON0 0x0738 +-#define MT6397_ZCD_CON1 0x073A +-#define MT6397_ZCD_CON2 0x073C +-#define MT6397_ZCD_CON3 0x073E +-#define MT6397_ZCD_CON4 0x0740 +-#define MT6397_ZCD_CON5 0x0742 +-#define MT6397_NCP_CLKDIV_CON0 0x0744 +-#define MT6397_NCP_CLKDIV_CON1 0x0746 ++#define MT6323_CHR_CON0 0x0000 ++#define MT6323_CHR_CON1 0x0002 ++#define MT6323_CHR_CON2 0x0004 ++#define MT6323_CHR_CON3 0x0006 ++#define MT6323_CHR_CON4 0x0008 ++#define MT6323_CHR_CON5 0x000A ++#define MT6323_CHR_CON6 0x000C ++#define MT6323_CHR_CON7 0x000E ++#define MT6323_CHR_CON8 0x0010 ++#define MT6323_CHR_CON9 0x0012 ++#define MT6323_CHR_CON10 0x0014 ++#define MT6323_CHR_CON11 0x0016 ++#define MT6323_CHR_CON12 0x0018 ++#define MT6323_CHR_CON13 0x001A ++#define MT6323_CHR_CON14 0x001C ++#define MT6323_CHR_CON15 0x001E ++#define MT6323_CHR_CON16 0x0020 ++#define MT6323_CHR_CON17 0x0022 ++#define MT6323_CHR_CON18 0x0024 ++#define MT6323_CHR_CON19 0x0026 ++#define MT6323_CHR_CON20 0x0028 ++#define MT6323_CHR_CON21 0x002A ++#define MT6323_CHR_CON22 0x002C ++#define MT6323_CHR_CON23 0x002E ++#define MT6323_CHR_CON24 0x0030 ++#define MT6323_CHR_CON25 0x0032 ++#define MT6323_CHR_CON26 0x0034 ++#define MT6323_CHR_CON27 0x0036 ++#define MT6323_CHR_CON28 0x0038 ++#define MT6323_CHR_CON29 0x003A ++#define MT6323_STRUP_CON0 0x003C ++#define MT6323_STRUP_CON2 0x003E ++#define MT6323_STRUP_CON3 0x0040 ++#define MT6323_STRUP_CON4 0x0042 ++#define MT6323_STRUP_CON5 0x0044 ++#define MT6323_STRUP_CON6 0x0046 ++#define MT6323_STRUP_CON7 0x0048 ++#define MT6323_STRUP_CON8 0x004A ++#define MT6323_STRUP_CON9 0x004C ++#define MT6323_STRUP_CON10 0x004E ++#define MT6323_STRUP_CON11 0x0050 ++#define MT6323_SPK_CON0 0x0052 ++#define MT6323_SPK_CON1 0x0054 ++#define MT6323_SPK_CON2 0x0056 ++#define MT6323_SPK_CON6 0x005E ++#define MT6323_SPK_CON7 0x0060 ++#define MT6323_SPK_CON8 0x0062 ++#define MT6323_SPK_CON9 0x0064 ++#define MT6323_SPK_CON10 0x0066 ++#define MT6323_SPK_CON11 0x0068 ++#define MT6323_SPK_CON12 0x006A ++#define MT6323_CID 0x0100 ++#define MT6323_TOP_CKPDN0 0x0102 ++#define MT6323_TOP_CKPDN0_SET 0x0104 ++#define MT6323_TOP_CKPDN0_CLR 0x0106 ++#define MT6323_TOP_CKPDN1 0x0108 ++#define MT6323_TOP_CKPDN1_SET 0x010A ++#define MT6323_TOP_CKPDN1_CLR 0x010C ++#define MT6323_TOP_CKPDN2 0x010E ++#define MT6323_TOP_CKPDN2_SET 0x0110 ++#define MT6323_TOP_CKPDN2_CLR 0x0112 ++#define MT6323_TOP_RST_CON 0x0114 ++#define MT6323_TOP_RST_CON_SET 0x0116 ++#define MT6323_TOP_RST_CON_CLR 0x0118 ++#define MT6323_TOP_RST_MISC 0x011A ++#define MT6323_TOP_RST_MISC_SET 0x011C ++#define MT6323_TOP_RST_MISC_CLR 0x011E ++#define MT6323_TOP_CKCON0 0x0120 ++#define MT6323_TOP_CKCON0_SET 0x0122 ++#define MT6323_TOP_CKCON0_CLR 0x0124 ++#define MT6323_TOP_CKCON1 0x0126 ++#define MT6323_TOP_CKCON1_SET 0x0128 ++#define MT6323_TOP_CKCON1_CLR 0x012A ++#define MT6323_TOP_CKTST0 0x012C ++#define MT6323_TOP_CKTST1 0x012E ++#define MT6323_TOP_CKTST2 0x0130 ++#define MT6323_TEST_OUT 0x0132 ++#define MT6323_TEST_CON0 0x0134 ++#define MT6323_TEST_CON1 0x0136 ++#define MT6323_EN_STATUS0 0x0138 ++#define MT6323_EN_STATUS1 0x013A ++#define MT6323_OCSTATUS0 0x013C ++#define MT6323_OCSTATUS1 0x013E ++#define MT6323_PGSTATUS 0x0140 ++#define MT6323_CHRSTATUS 0x0142 ++#define MT6323_TDSEL_CON 0x0144 ++#define MT6323_RDSEL_CON 0x0146 ++#define MT6323_SMT_CON0 0x0148 ++#define MT6323_SMT_CON1 0x014A ++#define MT6323_SMT_CON2 0x014C ++#define MT6323_SMT_CON3 0x014E ++#define MT6323_SMT_CON4 0x0150 ++#define MT6323_DRV_CON0 0x0152 ++#define MT6323_DRV_CON1 0x0154 ++#define MT6323_DRV_CON2 0x0156 ++#define MT6323_DRV_CON3 0x0158 ++#define MT6323_DRV_CON4 0x015A ++#define MT6323_SIMLS1_CON 0x015C ++#define MT6323_SIMLS2_CON 0x015E ++#define MT6323_INT_CON0 0x0160 ++#define MT6323_INT_CON0_SET 0x0162 ++#define MT6323_INT_CON0_CLR 0x0164 ++#define MT6323_INT_CON1 0x0166 ++#define MT6323_INT_CON1_SET 0x0168 ++#define MT6323_INT_CON1_CLR 0x016A ++#define MT6323_INT_MISC_CON 0x016C ++#define MT6323_INT_MISC_CON_SET 0x016E ++#define MT6323_INT_MISC_CON_CLR 0x0170 ++#define MT6323_INT_STATUS0 0x0172 ++#define MT6323_INT_STATUS1 0x0174 ++#define MT6323_OC_GEAR_0 0x0176 ++#define MT6323_OC_GEAR_1 0x0178 ++#define MT6323_OC_GEAR_2 0x017A ++#define MT6323_OC_CTL_VPROC 0x017C ++#define MT6323_OC_CTL_VSYS 0x017E ++#define MT6323_OC_CTL_VPA 0x0180 ++#define MT6323_FQMTR_CON0 0x0182 ++#define MT6323_FQMTR_CON1 0x0184 ++#define MT6323_FQMTR_CON2 0x0186 ++#define MT6323_RG_SPI_CON 0x0188 ++#define MT6323_DEW_DIO_EN 0x018A ++#define MT6323_DEW_READ_TEST 0x018C ++#define MT6323_DEW_WRITE_TEST 0x018E ++#define MT6323_DEW_CRC_SWRST 0x0190 ++#define MT6323_DEW_CRC_EN 0x0192 ++#define MT6323_DEW_CRC_VAL 0x0194 ++#define MT6323_DEW_DBG_MON_SEL 0x0196 ++#define MT6323_DEW_CIPHER_KEY_SEL 0x0198 ++#define MT6323_DEW_CIPHER_IV_SEL 0x019A ++#define MT6323_DEW_CIPHER_EN 0x019C ++#define MT6323_DEW_CIPHER_RDY 0x019E ++#define MT6323_DEW_CIPHER_MODE 0x01A0 ++#define MT6323_DEW_CIPHER_SWRST 0x01A2 ++#define MT6323_DEW_RDDMY_NO 0x01A4 ++#define MT6323_DEW_RDATA_DLY_SEL 0x01A6 ++#define MT6323_BUCK_CON0 0x0200 ++#define MT6323_BUCK_CON1 0x0202 ++#define MT6323_BUCK_CON2 0x0204 ++#define MT6323_BUCK_CON3 0x0206 ++#define MT6323_BUCK_CON4 0x0208 ++#define MT6323_BUCK_CON5 0x020A ++#define MT6323_VPROC_CON0 0x020C ++#define MT6323_VPROC_CON1 0x020E ++#define MT6323_VPROC_CON2 0x0210 ++#define MT6323_VPROC_CON3 0x0212 ++#define MT6323_VPROC_CON4 0x0214 ++#define MT6323_VPROC_CON5 0x0216 ++#define MT6323_VPROC_CON7 0x021A ++#define MT6323_VPROC_CON8 0x021C ++#define MT6323_VPROC_CON9 0x021E ++#define MT6323_VPROC_CON10 0x0220 ++#define MT6323_VPROC_CON11 0x0222 ++#define MT6323_VPROC_CON12 0x0224 ++#define MT6323_VPROC_CON13 0x0226 ++#define MT6323_VPROC_CON14 0x0228 ++#define MT6323_VPROC_CON15 0x022A ++#define MT6323_VPROC_CON18 0x0230 ++#define MT6323_VSYS_CON0 0x0232 ++#define MT6323_VSYS_CON1 0x0234 ++#define MT6323_VSYS_CON2 0x0236 ++#define MT6323_VSYS_CON3 0x0238 ++#define MT6323_VSYS_CON4 0x023A ++#define MT6323_VSYS_CON5 0x023C ++#define MT6323_VSYS_CON7 0x0240 ++#define MT6323_VSYS_CON8 0x0242 ++#define MT6323_VSYS_CON9 0x0244 ++#define MT6323_VSYS_CON10 0x0246 ++#define MT6323_VSYS_CON11 0x0248 ++#define MT6323_VSYS_CON12 0x024A ++#define MT6323_VSYS_CON13 0x024C ++#define MT6323_VSYS_CON14 0x024E ++#define MT6323_VSYS_CON15 0x0250 ++#define MT6323_VSYS_CON18 0x0256 ++#define MT6323_VPA_CON0 0x0300 ++#define MT6323_VPA_CON1 0x0302 ++#define MT6323_VPA_CON2 0x0304 ++#define MT6323_VPA_CON3 0x0306 ++#define MT6323_VPA_CON4 0x0308 ++#define MT6323_VPA_CON5 0x030A ++#define MT6323_VPA_CON7 0x030E ++#define MT6323_VPA_CON8 0x0310 ++#define MT6323_VPA_CON9 0x0312 ++#define MT6323_VPA_CON10 0x0314 ++#define MT6323_VPA_CON11 0x0316 ++#define MT6323_VPA_CON12 0x0318 ++#define MT6323_VPA_CON14 0x031C ++#define MT6323_VPA_CON16 0x0320 ++#define MT6323_VPA_CON17 0x0322 ++#define MT6323_VPA_CON18 0x0324 ++#define MT6323_VPA_CON19 0x0326 ++#define MT6323_VPA_CON20 0x0328 ++#define MT6323_BUCK_K_CON0 0x032A ++#define MT6323_BUCK_K_CON1 0x032C ++#define MT6323_BUCK_K_CON2 0x032E ++#define MT6323_ISINK0_CON0 0x0330 ++#define MT6323_ISINK0_CON1 0x0332 ++#define MT6323_ISINK0_CON2 0x0334 ++#define MT6323_ISINK0_CON3 0x0336 ++#define MT6323_ISINK1_CON0 0x0338 ++#define MT6323_ISINK1_CON1 0x033A ++#define MT6323_ISINK1_CON2 0x033C ++#define MT6323_ISINK1_CON3 0x033E ++#define MT6323_ISINK2_CON0 0x0340 ++#define MT6323_ISINK2_CON1 0x0342 ++#define MT6323_ISINK2_CON2 0x0344 ++#define MT6323_ISINK2_CON3 0x0346 ++#define MT6323_ISINK3_CON0 0x0348 ++#define MT6323_ISINK3_CON1 0x034A ++#define MT6323_ISINK3_CON2 0x034C ++#define MT6323_ISINK3_CON3 0x034E ++#define MT6323_ISINK_ANA0 0x0350 ++#define MT6323_ISINK_ANA1 0x0352 ++#define MT6323_ISINK_PHASE_DLY 0x0354 ++#define MT6323_ISINK_EN_CTRL 0x0356 ++#define MT6323_ANALDO_CON0 0x0400 ++#define MT6323_ANALDO_CON1 0x0402 ++#define MT6323_ANALDO_CON2 0x0404 ++#define MT6323_ANALDO_CON3 0x0406 ++#define MT6323_ANALDO_CON4 0x0408 ++#define MT6323_ANALDO_CON5 0x040A ++#define MT6323_ANALDO_CON6 0x040C ++#define MT6323_ANALDO_CON7 0x040E ++#define MT6323_ANALDO_CON8 0x0410 ++#define MT6323_ANALDO_CON10 0x0412 ++#define MT6323_ANALDO_CON15 0x0414 ++#define MT6323_ANALDO_CON16 0x0416 ++#define MT6323_ANALDO_CON17 0x0418 ++#define MT6323_ANALDO_CON18 0x041A ++#define MT6323_ANALDO_CON19 0x041C ++#define MT6323_ANALDO_CON20 0x041E ++#define MT6323_ANALDO_CON21 0x0420 ++#define MT6323_DIGLDO_CON0 0x0500 ++#define MT6323_DIGLDO_CON2 0x0502 ++#define MT6323_DIGLDO_CON3 0x0504 ++#define MT6323_DIGLDO_CON5 0x0506 ++#define MT6323_DIGLDO_CON6 0x0508 ++#define MT6323_DIGLDO_CON7 0x050A ++#define MT6323_DIGLDO_CON8 0x050C ++#define MT6323_DIGLDO_CON9 0x050E ++#define MT6323_DIGLDO_CON10 0x0510 ++#define MT6323_DIGLDO_CON11 0x0512 ++#define MT6323_DIGLDO_CON12 0x0514 ++#define MT6323_DIGLDO_CON13 0x0516 ++#define MT6323_DIGLDO_CON14 0x0518 ++#define MT6323_DIGLDO_CON15 0x051A ++#define MT6323_DIGLDO_CON16 0x051C ++#define MT6323_DIGLDO_CON17 0x051E ++#define MT6323_DIGLDO_CON18 0x0520 ++#define MT6323_DIGLDO_CON19 0x0522 ++#define MT6323_DIGLDO_CON20 0x0524 ++#define MT6323_DIGLDO_CON21 0x0526 ++#define MT6323_DIGLDO_CON23 0x0528 ++#define MT6323_DIGLDO_CON24 0x052A ++#define MT6323_DIGLDO_CON26 0x052C ++#define MT6323_DIGLDO_CON27 0x052E ++#define MT6323_DIGLDO_CON28 0x0530 ++#define MT6323_DIGLDO_CON29 0x0532 ++#define MT6323_DIGLDO_CON30 0x0534 ++#define MT6323_DIGLDO_CON31 0x0536 ++#define MT6323_DIGLDO_CON32 0x0538 ++#define MT6323_DIGLDO_CON33 0x053A ++#define MT6323_DIGLDO_CON34 0x053C ++#define MT6323_DIGLDO_CON35 0x053E ++#define MT6323_DIGLDO_CON36 0x0540 ++#define MT6323_DIGLDO_CON39 0x0542 ++#define MT6323_DIGLDO_CON40 0x0544 ++#define MT6323_DIGLDO_CON41 0x0546 ++#define MT6323_DIGLDO_CON42 0x0548 ++#define MT6323_DIGLDO_CON43 0x054A ++#define MT6323_DIGLDO_CON44 0x054C ++#define MT6323_DIGLDO_CON45 0x054E ++#define MT6323_DIGLDO_CON46 0x0550 ++#define MT6323_DIGLDO_CON47 0x0552 ++#define MT6323_DIGLDO_CON48 0x0554 ++#define MT6323_DIGLDO_CON49 0x0556 ++#define MT6323_DIGLDO_CON50 0x0558 ++#define MT6323_DIGLDO_CON51 0x055A ++#define MT6323_DIGLDO_CON52 0x055C ++#define MT6323_DIGLDO_CON53 0x055E ++#define MT6323_DIGLDO_CON54 0x0560 ++#define MT6323_EFUSE_CON0 0x0600 ++#define MT6323_EFUSE_CON1 0x0602 ++#define MT6323_EFUSE_CON2 0x0604 ++#define MT6323_EFUSE_CON3 0x0606 ++#define MT6323_EFUSE_CON4 0x0608 ++#define MT6323_EFUSE_CON5 0x060A ++#define MT6323_EFUSE_CON6 0x060C ++#define MT6323_EFUSE_VAL_0_15 0x060E ++#define MT6323_EFUSE_VAL_16_31 0x0610 ++#define MT6323_EFUSE_VAL_32_47 0x0612 ++#define MT6323_EFUSE_VAL_48_63 0x0614 ++#define MT6323_EFUSE_VAL_64_79 0x0616 ++#define MT6323_EFUSE_VAL_80_95 0x0618 ++#define MT6323_EFUSE_VAL_96_111 0x061A ++#define MT6323_EFUSE_VAL_112_127 0x061C ++#define MT6323_EFUSE_VAL_128_143 0x061E ++#define MT6323_EFUSE_VAL_144_159 0x0620 ++#define MT6323_EFUSE_VAL_160_175 0x0622 ++#define MT6323_EFUSE_VAL_176_191 0x0624 ++#define MT6323_EFUSE_DOUT_0_15 0x0626 ++#define MT6323_EFUSE_DOUT_16_31 0x0628 ++#define MT6323_EFUSE_DOUT_32_47 0x062A ++#define MT6323_EFUSE_DOUT_48_63 0x062C ++#define MT6323_EFUSE_DOUT_64_79 0x062E ++#define MT6323_EFUSE_DOUT_80_95 0x0630 ++#define MT6323_EFUSE_DOUT_96_111 0x0632 ++#define MT6323_EFUSE_DOUT_112_127 0x0634 ++#define MT6323_EFUSE_DOUT_128_143 0x0636 ++#define MT6323_EFUSE_DOUT_144_159 0x0638 ++#define MT6323_EFUSE_DOUT_160_175 0x063A ++#define MT6323_EFUSE_DOUT_176_191 0x063C ++#define MT6323_EFUSE_CON7 0x063E ++#define MT6323_EFUSE_CON8 0x0640 ++#define MT6323_EFUSE_CON9 0x0642 ++#define MT6323_RTC_MIX_CON0 0x0644 ++#define MT6323_RTC_MIX_CON1 0x0646 ++#define MT6323_AUDTOP_CON0 0x0700 ++#define MT6323_AUDTOP_CON1 0x0702 ++#define MT6323_AUDTOP_CON2 0x0704 ++#define MT6323_AUDTOP_CON3 0x0706 ++#define MT6323_AUDTOP_CON4 0x0708 ++#define MT6323_AUDTOP_CON5 0x070A ++#define MT6323_AUDTOP_CON6 0x070C ++#define MT6323_AUDTOP_CON7 0x070E ++#define MT6323_AUDTOP_CON8 0x0710 ++#define MT6323_AUDTOP_CON9 0x0712 ++#define MT6323_AUXADC_ADC0 0x0714 ++#define MT6323_AUXADC_ADC1 0x0716 ++#define MT6323_AUXADC_ADC2 0x0718 ++#define MT6323_AUXADC_ADC3 0x071A ++#define MT6323_AUXADC_ADC4 0x071C ++#define MT6323_AUXADC_ADC5 0x071E ++#define MT6323_AUXADC_ADC6 0x0720 ++#define MT6323_AUXADC_ADC7 0x0722 ++#define MT6323_AUXADC_ADC8 0x0724 ++#define MT6323_AUXADC_ADC9 0x0726 ++#define MT6323_AUXADC_ADC10 0x0728 ++#define MT6323_AUXADC_ADC11 0x072A ++#define MT6323_AUXADC_ADC12 0x072C ++#define MT6323_AUXADC_ADC13 0x072E ++#define MT6323_AUXADC_ADC14 0x0730 ++#define MT6323_AUXADC_ADC15 0x0732 ++#define MT6323_AUXADC_ADC16 0x0734 ++#define MT6323_AUXADC_ADC17 0x0736 ++#define MT6323_AUXADC_ADC18 0x0738 ++#define MT6323_AUXADC_ADC19 0x073A ++#define MT6323_AUXADC_ADC20 0x073C ++#define MT6323_AUXADC_RSV1 0x073E ++#define MT6323_AUXADC_RSV2 0x0740 ++#define MT6323_AUXADC_CON0 0x0742 ++#define MT6323_AUXADC_CON1 0x0744 ++#define MT6323_AUXADC_CON2 0x0746 ++#define MT6323_AUXADC_CON3 0x0748 ++#define MT6323_AUXADC_CON4 0x074A ++#define MT6323_AUXADC_CON5 0x074C ++#define MT6323_AUXADC_CON6 0x074E ++#define MT6323_AUXADC_CON7 0x0750 ++#define MT6323_AUXADC_CON8 0x0752 ++#define MT6323_AUXADC_CON9 0x0754 ++#define MT6323_AUXADC_CON10 0x0756 ++#define MT6323_AUXADC_CON11 0x0758 ++#define MT6323_AUXADC_CON12 0x075A ++#define MT6323_AUXADC_CON13 0x075C ++#define MT6323_AUXADC_CON14 0x075E ++#define MT6323_AUXADC_CON15 0x0760 ++#define MT6323_AUXADC_CON16 0x0762 ++#define MT6323_AUXADC_CON17 0x0764 ++#define MT6323_AUXADC_CON18 0x0766 ++#define MT6323_AUXADC_CON19 0x0768 ++#define MT6323_AUXADC_CON20 0x076A ++#define MT6323_AUXADC_CON21 0x076C ++#define MT6323_AUXADC_CON22 0x076E ++#define MT6323_AUXADC_CON23 0x0770 ++#define MT6323_AUXADC_CON24 0x0772 ++#define MT6323_AUXADC_CON25 0x0774 ++#define MT6323_AUXADC_CON26 0x0776 ++#define MT6323_AUXADC_CON27 0x0778 ++#define MT6323_ACCDET_CON0 0x077A ++#define MT6323_ACCDET_CON1 0x077C ++#define MT6323_ACCDET_CON2 0x077E ++#define MT6323_ACCDET_CON3 0x0780 ++#define MT6323_ACCDET_CON4 0x0782 ++#define MT6323_ACCDET_CON5 0x0784 ++#define MT6323_ACCDET_CON6 0x0786 ++#define MT6323_ACCDET_CON7 0x0788 ++#define MT6323_ACCDET_CON8 0x078A ++#define MT6323_ACCDET_CON9 0x078C ++#define MT6323_ACCDET_CON10 0x078E ++#define MT6323_ACCDET_CON11 0x0790 ++#define MT6323_ACCDET_CON12 0x0792 ++#define MT6323_ACCDET_CON13 0x0794 ++#define MT6323_ACCDET_CON14 0x0796 ++#define MT6323_ACCDET_CON15 0x0798 ++#define MT6323_ACCDET_CON16 0x079A + +-#endif /* __MFD_MT6397_REGISTERS_H__ */ ++#endif +diff --git a/include/linux/regulator/mt6323-regulator.h b/include/linux/regulator/mt6323-regulator.h +new file mode 100644 +index 0000000..620b0e3 +--- /dev/null ++++ b/include/linux/regulator/mt6323-regulator.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (c) 2015 MediaTek Inc. ++ * Author: John Crispin ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __LINUX_REGULATOR_MT6323_H ++#define __LINUX_REGULATOR_MT6323_H ++ ++enum { ++ MT6323_ID_VPROC = 0, ++ MT6323_ID_VSYS, ++ MT6323_ID_VPA, ++ MT6323_ID_VTCXO, ++ MT6323_ID_VA, ++ MT6323_ID_VCN28, ++ MT6323_ID_VCN33, ++ MT6323_ID_VIO28, ++ MT6323_ID_VUSB, ++ MT6323_ID_VMC, ++ MT6323_ID_VMCH, ++ MT6323_ID_VGP1, ++ MT6323_ID_VGP2, ++ MT6323_ID_RG_MAX, ++}; ++ ++#define MT6323_MAX_REGULATOR MT6323_ID_RG_MAX ++ ++#endif /* __LINUX_REGULATOR_MT6323_H */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0073-clk.patch b/target/linux/mediatek/patches/0073-clk.patch new file mode 100644 index 0000000..a3b36a5 --- /dev/null +++ b/target/linux/mediatek/patches/0073-clk.patch @@ -0,0 +1,200 @@ +From a4df453fbfa6199ad33435cee6ce2dfcc65321b0 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jul 2015 05:45:58 +0200 +Subject: [PATCH 73/76] clk + +--- + include/dt-bindings/clock/mt7623-clk.h | 158 +++++++++++++++----------------- + 1 file changed, 73 insertions(+), 85 deletions(-) + +diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h +index cb1e8a9..410ef31 100644 +--- a/include/dt-bindings/clock/mt7623-clk.h ++++ b/include/dt-bindings/clock/mt7623-clk.h +@@ -17,96 +17,76 @@ + + /* TOPCKGEN */ + +-#define CLK_TOP_AUDPLL_24 1 +-#define CLK_TOP_AUDPLL_D16 2 +-#define CLK_TOP_AUDPLL_D4 3 +-#define CLK_TOP_AUDPLL_D8 4 +-#define CLK_TOP_CLKPH_MCK 5 +-#define CLK_TOP_CPUM_TCK_IN 6 +-#define CLK_TOP_DSI0_LNTC_DSICLK 7 +-#define CLK_TOP_HDMITX_CLKDIG_CTS 8 +-#define CLK_TOP_LVDS_ETH 9 +-#define CLK_TOP_LVDSPLL_D2 10 +-#define CLK_TOP_LVDSPLL_D4 11 +-#define CLK_TOP_LVDSPLL_D8 12 +-#define CLK_TOP_MAINPLL_230P3M 13 +-#define CLK_TOP_MAINPLL_322P4M 14 +-#define CLK_TOP_MAINPLL_537P3M 15 +-#define CLK_TOP_MAINPLL_806M 16 +-#define CLK_TOP_MEMPLL_MCK_D4 17 +-#define CLK_TOP_MMPLL_D2 18 +-#define CLK_TOP_MSDCPLL_D2 19 +-#define CLK_TOP_SYSPLL1_D16 20 +-#define CLK_TOP_SYSPLL1_D2 21 +-#define CLK_TOP_SYSPLL1_D4 22 +-#define CLK_TOP_SYSPLL1_D8 23 +-#define CLK_TOP_SYSPLL2_D2 24 +-#define CLK_TOP_SYSPLL2_D4 25 +-#define CLK_TOP_SYSPLL2_D8 26 +-#define CLK_TOP_SYSPLL3_D2 27 +-#define CLK_TOP_SYSPLL3_D4 28 +-#define CLK_TOP_SYSPLL4_D2 29 +-#define CLK_TOP_SYSPLL4_D4 30 +-#define CLK_TOP_SYSPLL_D3 31 +-#define CLK_TOP_SYSPLL_D5 32 +-#define CLK_TOP_SYSPLL_D7 33 +-#define CLK_TOP_TVDPLL_d2 34 +-#define CLK_TOP_TVDPLL_D4 35 +-#define CLK_TOP_UNIVPLL_178P3M 36 +-#define CLK_TOP_UNIVPLL1_D10 37 +-#define CLK_TOP_UNIVPLL1_D2 38 +-#define CLK_TOP_UNIVPLL1_D4 39 +-#define CLK_TOP_UNIVPLL1_D6 40 +-#define CLK_TOP_UNIVPLL1_D8 41 +-#define CLK_TOP_UNIVPLL_249P6M 42 +-#define CLK_TOP_UNIVPLL2_D2 43 +-#define CLK_TOP_UNIVPLL2_D4 44 +-#define CLK_TOP_UNIVPLL2_D6 45 +-#define CLK_TOP_UNIVPLL2_D8 46 +-#define CLK_TOP_UNIVPLL_416M 47 +-#define CLK_TOP_UNIVPLL_48M 48 +-#define CLK_TOP_UNIVPLL_624M 49 +-#define CLK_TOP_UNIVPLL_D26 50 +-#define CLK_TOP_UNIVPLL_D5 51 +-#define CLK_TOP_APLL_SEL 52 ++#define CLK_TOP_MAINPLL_650M 1 ++#define CLK_TOP_MAINPLL_433P3M 2 ++#define CLK_TOP_MAINPLL_260M 3 ++#define CLK_TOP_MAINPLL_185P6M 4 ++#define CLK_TOP_UNIVPLL_624M 5 ++#define CLK_TOP_UNIVPLL_416M 6 ++#define CLK_TOP_UNIVPLL_249P6M 7 ++#define CLK_TOP_UNIVPLL_178P3M 8 ++#define CLK_TOP_UNIVPLL_48M 9 ++#define CLK_TOP_AUDPLL_D4 10 ++#define CLK_TOP_AUDPLL_D8 11 ++#define CLK_TOP_AUDPLL_D16 12 ++#define CLK_TOP_AUDPLL_24 13 ++#define CLK_TOP_MSDCPLL_D2 14 ++#define CLK_TOP_SYSPLL1_D2 15 ++#define CLK_TOP_SYSPLL1_D4 16 ++#define CLK_TOP_SYSPLL1_D8 17 ++#define CLK_TOP_SYSPLL1_D16 18 ++#define CLK_TOP_SYSPLL2_D2 19 ++#define CLK_TOP_SYSPLL2_D4 20 ++#define CLK_TOP_SYSPLL2_D8 21 ++#define CLK_TOP_SYSPLL3_D2 22 ++#define CLK_TOP_SYSPLL3_D4 23 ++#define CLK_TOP_SYSPLL4_D2 24 ++#define CLK_TOP_SYSPLL4_D4 25 ++#define CLK_TOP_SYSPLL_D3 26 ++#define CLK_TOP_SYSPLL_D5 27 ++#define CLK_TOP_SYSPLL_D7 28 ++#define CLK_TOP_UNIVPLL1_D2 29 ++#define CLK_TOP_UNIVPLL1_D4 30 ++#define CLK_TOP_UNIVPLL1_D6 31 ++#define CLK_TOP_UNIVPLL1_D8 32 ++#define CLK_TOP_UNIVPLL1_D10 33 ++#define CLK_TOP_UNIVPLL2_D2 34 ++#define CLK_TOP_UNIVPLL2_D4 35 ++#define CLK_TOP_UNIVPLL2_D6 36 ++#define CLK_TOP_UNIVPLL2_D8 37 ++#define CLK_TOP_UNIVPLL_D5 38 ++#define CLK_TOP_UNIVPLL_D26 39 ++#define CLK_TOP_AXI_SEL 40 ++#define CLK_TOP_MEM_SEL 41 ++#define CLK_TOP_DDR_SEL 42 ++#define CLK_TOP_MM_SEL 43 ++#define CLK_TOP_PWM_SEL 44 ++#define CLK_TOP_MFG_SEL 45 ++#define CLK_TOP_UART_SEL 46 ++#define CLK_TOP_SPI_SEL 47 ++#define CLK_TOP_USB20_SEL 48 ++#define CLK_TOP_MSDC30_0_SEL 49 ++#define CLK_TOP_MSDC30_1_SEL 50 ++#define CLK_TOP_MSDC30_2_SEL 51 ++#define CLK_TOP_AUDIO_SEL 52 + #define CLK_TOP_AUDIO_INTBUS_SEL 53 +-#define CLK_TOP_AUDIO_SEL 54 +-#define CLK_TOP_AXI_SEL 55 +-#define CLK_TOP_CAM_SEL 56 +-#define CLK_TOP_DDR_SEL 57 +-#define CLK_TOP_DPI0_SEL 58 +-#define CLK_TOP_DPI1_SEL 59 +-#define CLK_TOP_DPILVDS_SEL 60 +-#define CLK_TOP_ETH_SEL 61 +-#define CLK_TOP_MEM_SEL 62 +-#define CLK_TOP_MFG_SEL 63 +-#define CLK_TOP_MM_SEL 64 +-#define CLK_TOP_MSDC30_0_SEL 65 +-#define CLK_TOP_MSDC30_1_SEL 66 +-#define CLK_TOP_MSDC30_2_SEL 67 +-#define CLK_TOP_NFI2X_SEL 68 +-#define CLK_TOP_PMICSPI_SEL 69 +-#define CLK_TOP_PWM_SEL 70 +-#define CLK_TOP_RTC_SEL 71 +-#define CLK_TOP_SCP_SEL 72 +-#define CLK_TOP_SPI_SEL 73 +-#define CLK_TOP_TVE_SEL 74 +-#define CLK_TOP_UART_SEL 75 +-#define CLK_TOP_USB20_SEL 76 +-#define CLK_TOP_VDEC_SEL 77 +-#define CLK_TOP_NR_CLK 78 ++#define CLK_TOP_PMICSPI_SEL 54 ++#define CLK_TOP_SCP_SEL 55 ++#define CLK_TOP_APLL_SEL 56 ++#define CLK_TOP_RTC_SEL 57 ++#define CLK_TOP_NFI2X_SEL 58 ++#define CLK_TOP_ETH_SEL 59 ++#define CLK_TOP_NR_CLK 60 + + /* APMIXED_SYS */ + + #define CLK_APMIXED_ARMPLL 1 + #define CLK_APMIXED_MAINPLL 2 +-#define CLK_APMIXED_MSDCPLL 3 +-#define CLK_APMIXED_UNIVPLL 4 +-#define CLK_APMIXED_MMPLL 5 +-#define CLK_APMIXED_VENCPLL 6 +-#define CLK_APMIXED_TVDPLL 7 +-#define CLK_APMIXED_LVDSPLL 8 +-#define CLK_APMIXED_AUDPLL 9 ++#define CLK_APMIXED_UNIVPLL 3 ++#define CLK_APMIXED_MSDCPLL 4 ++#define CLK_APMIXED_AUDPLL 5 ++#define CLK_APMIXED_TRGPLL 6 ++#define CLK_APMIXED_ETHPLL 7 + + /* INFRA_SYS */ + +@@ -124,7 +104,8 @@ + #define CLK_INFRA_IRRX 19 + #define CLK_INFRA_PMICSPI 22 + #define CLK_INFRA_PMIC_WRAP 23 +-#define CLK_INFRA_NR_CLK 24 ++#define CLK_INFRA_CA7SEL 24 ++#define CLK_INFRA_NR_CLK 25 + + /* PERI_SYS */ + +@@ -169,5 +150,12 @@ + #define CLK_PERI_UART3_SEL 38 + #define CLK_PERI_NR_CLK 39 + ++#define CLK_HIFSYS_USB0_PHY 1 ++#define CLK_HIFSYS_USB1_PHY 2 ++#define CLK_HIFSYS_PCIE0 3 ++#define CLK_HIFSYS_PCIE1 4 ++#define CLK_HIFSYS_PCIE2 5 ++#define CLK_HIFSYS_NR_CLK 6 ++ + #endif /* _DT_BINDINGS_CLK_MT7623_H */ + +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0074-dts.patch b/target/linux/mediatek/patches/0074-dts.patch new file mode 100644 index 0000000..eddafb6 --- /dev/null +++ b/target/linux/mediatek/patches/0074-dts.patch @@ -0,0 +1,182 @@ +From df59c3b7030b6d7802fe5e5abda81467fcdf2178 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jul 2015 05:46:13 +0200 +Subject: [PATCH 74/76] dts + +--- + arch/arm/boot/dts/mt7623-evb.dts | 124 +++++++++++++++++++++++++++++++++++++- + arch/arm/boot/dts/mt7623.dtsi | 11 ++++ + 2 files changed, 133 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/mt7623-evb.dts ++++ b/arch/arm/boot/dts/mt7623-evb.dts +@@ -145,8 +145,8 @@ + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; +-// vmmc-supply = <&mt6397_vemc_3v3_reg>; +-// vqmmc-supply = <&mt6397_vio18_reg>; ++// vmmc-supply = <&mt6323_vemc_3v3_reg>; ++// vqmmc-supply = <&mt6323_vio18_reg>; + non-removable; + }; + +@@ -160,3 +160,123 @@ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_default>; + }; ++ ++&pwrap { ++ pmic: mt6323 { ++ compatible = "mediatek,mt6323"; ++ ++ mt6323regulator: mt6323regulator { ++ compatible = "mediatek,mt6323-regulator"; ++ ++ mt6323_vproc_reg: buck_vproc { ++ regulator-compatible = "buck_vproc"; ++ regulator-name = "vproc"; ++ regulator-min-microvolt = < 700000>; ++ regulator-max-microvolt = <1493750>; ++ regulator-ramp-delay = <6250>; ++ regulator-always-on; ++ }; ++ ++ mt6323_vsys_reg: buck_vsys { ++ regulator-compatible = "buck_vsys"; ++ regulator-name = "vsys"; ++ regulator-min-microvolt = <1400000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-ramp-delay = <12500>; ++ regulator-always-on; ++ }; ++ ++ mt6323_vpa_reg: buck_vpa { ++ regulator-compatible = "buck_vpa"; ++ regulator-name = "vpa"; ++ regulator-min-microvolt = < 500000>; ++ regulator-max-microvolt = <3650000>; ++ regulator-ramp-delay = <50000>; ++ regulator-always-on; ++ }; ++ ++ mt6323_vtcxo_reg: ldo_vtcxo { ++ regulator-compatible = "ldo_vtcxo"; ++ regulator-name = "vtcxo"; ++ regulator-always-on; ++ }; ++ ++ mt6323_va_reg: ldo_va { ++ regulator-compatible = "ldo_va"; ++ regulator-name = "va"; ++ regulator-always-on; ++ }; ++ ++ mt6323_vcn28_reg: ldo_vcn28 { ++ regulator-compatible = "ldo_vcn28"; ++ regulator-name = "vcn28"; ++ regulator-always-on; ++ }; ++ ++ mt6323_vcn33_reg: ldo_vcn33 { ++ regulator-compatible = "ldo_vcn33"; ++ regulator-name = "vcn33"; ++ regulator-always-on; ++ }; ++ ++ mt6323_vcama_reg: ldo_vcama { ++ regulator-compatible = "ldo_vcama"; ++ regulator-name = "vcama"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-enable-ramp-delay = <218>; ++ }; ++ ++ mt6323_vio28_reg: ldo_vio28 { ++ regulator-compatible = "ldo_vio28"; ++ regulator-name = "vio28"; ++ regulator-always-on; ++ }; ++ ++ mt6323_vusb_reg: ldo_vusb { ++ regulator-compatible = "ldo_vusb"; ++ regulator-name = "vusb"; ++ }; ++ ++ mt6323_vmc_reg: ldo_vmc { ++ regulator-compatible = "ldo_vmc"; ++ regulator-name = "vmc"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <218>; ++ }; ++ ++ mt6323_vmch_reg: ldo_vmch { ++ regulator-compatible = "ldo_vmch"; ++ regulator-name = "vmch"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <218>; ++ }; ++ ++ mt6323_vemc_3v3_reg: ldo_vemc3v3 { ++ regulator-compatible = "ldo_vemc3v3"; ++ regulator-name = "vemc_3v3"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <218>; ++ }; ++ ++ mt6323_vgp1_reg: ldo_vgp1 { ++ regulator-compatible = "ldo_vgp1"; ++ regulator-name = "vcamd"; ++ regulator-min-microvolt = <1220000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <240>; ++ }; ++ ++ mt6323_vgp2_reg: ldo_vgp2 { ++ regulator-compatible = "ldo_vgp2"; ++ regulator-name = "vcamio"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-enable-ramp-delay = <218>; ++ }; ++ }; ++ }; ++}; +--- a/arch/arm/boot/dts/mt7623.dtsi ++++ b/arch/arm/boot/dts/mt7623.dtsi +@@ -150,6 +150,17 @@ + clock-names = "system-clk", "rtc-clk"; + }; + ++ pwrap: pwrap@1000f000 { ++ compatible = "mediatek,mt7623-pwrap"; ++ reg = <0 0x1000f000 0 0x1000>; ++ reg-names = "pwrap"; ++ interrupts = ; ++ resets = <&infracfg MT7623_INFRA_PMIC_WRAP_RST>; ++ reset-names = "pwrap"; ++ clocks = <&clk26m>, <&clk26m>; ++ clock-names = "spi", "wrap"; ++ }; ++ + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt7623-sysirq", + "mediatek,mt6577-sysirq"; +@@ -311,6 +322,7 @@ + device_type = "pci"; + + bus-range = <0 255>; ++ status = "disabled"; + ranges = < + 0x02000000 0 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ + 0x01000000 0 0 0x00000000 0x1A160000 0 0x00010000 /* io space */ +@@ -343,6 +355,5 @@ + device_type = "pci"; + }; + +- status = "disabled"; + }; + }; diff --git a/target/linux/mediatek/patches/0075-sd.patch b/target/linux/mediatek/patches/0075-sd.patch new file mode 100644 index 0000000..1dcfae3 --- /dev/null +++ b/target/linux/mediatek/patches/0075-sd.patch @@ -0,0 +1,55 @@ +From a5982c5e4b58c4335e789969e04f9e24b894f510 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jul 2015 05:46:39 +0200 +Subject: [PATCH 75/76] sd + +--- + drivers/mmc/host/mtk-sd.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c +index 7c20f28..be2b00c 100644 +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -227,11 +227,13 @@ struct mt_gpdma_desc { + #define GPDMA_DESC_BDP (0x1 << 1) + #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ + #define GPDMA_DESC_INT (0x1 << 16) ++#define GPDMA_DESC_GPDH4B (0x1 << 24) ++#define GPDMA_DESC_BDH4B (0x1 << 28) + u32 next; + u32 ptr; + u32 gpd_data_len; +-#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ +-#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ ++#define GPDMA_DESC_BUFLEN (0xffffff) /* bit0 ~ bit15 */ ++#define GPDMA_DESC_EXTLEN (0xff << 24) /* bit16 ~ bit23 */ + u32 arg; + u32 blknum; + u32 cmd; +@@ -243,10 +245,12 @@ struct mt_bdma_desc { + #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ + #define BDMA_DESC_BLKPAD (0x1 << 17) + #define BDMA_DESC_DWPAD (0x1 << 18) ++#define BDMA_DESC_GPDH4B (0x1 << 24) ++#define BDMA_DESC_BDH4B (0x1 << 28) + u32 next; + u32 ptr; + u32 bd_data_len; +-#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ ++#define BDMA_DESC_BUFLEN (0xffffff) /* bit0 ~ bit15 */ + }; + + struct msdc_dma { +@@ -1115,7 +1119,7 @@ static void msdc_init_hw(struct msdc_host *host) + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); + writel(0x403c004f, host->base + MSDC_PATCH_BIT); + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); +- writel(0xffff0089, host->base + MSDC_PATCH_BIT1); ++// writel(0xffff0089, host->base + MSDC_PATCH_BIT1); + /* Configure to enable SDIO mode. + * it's must otherwise sdio cmd5 failed + */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/patches/0076-reset.patch b/target/linux/mediatek/patches/0076-reset.patch new file mode 100644 index 0000000..6157779 --- /dev/null +++ b/target/linux/mediatek/patches/0076-reset.patch @@ -0,0 +1,30 @@ +From 1671d902f8dcfce70f920ad3dfebb1031a7a38de Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Jul 2015 05:46:51 +0200 +Subject: [PATCH 76/76] reset + +--- + include/dt-bindings/reset-controller/mt7623-resets.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/include/dt-bindings/reset-controller/mt7623-resets.h b/include/dt-bindings/reset-controller/mt7623-resets.h +index 28a7d69..3e0f39a 100644 +--- a/include/dt-bindings/reset-controller/mt7623-resets.h ++++ b/include/dt-bindings/reset-controller/mt7623-resets.h +@@ -56,4 +56,13 @@ + #define MT7623_PERI_ETH_SW_RST 29 + #define MT7623_PERI_SPI0_SW_RST 33 + ++/* high speed interface resets */ ++#define MT7623_HIFSYS_UHOST0_SW_RST 3 ++#define MT7623_HIFSYS_UHOST1_SW_RST 4 ++#define MT7623_HIFSYS_UPHY0_SW_RST 21 ++#define MT7623_HIFSYS_UPHY1_SW_RST 22 ++#define MT7623_HIFSYS_PCIE0_SW_RST 24 ++#define MT7623_HIFSYS_PCIE0_SW_RST 25 ++#define MT7623_HIFSYS_PCIE0_SW_RST 26 ++ + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7623 */ +-- +1.7.10.4 + diff --git a/target/linux/mediatek/profiles/default.mk b/target/linux/mediatek/profiles/default.mk new file mode 100644 index 0000000..b83792a --- /dev/null +++ b/target/linux/mediatek/profiles/default.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (minimum package set) + PACKAGES:= \ + kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-ledtrig-usbdev \ + kmod-usb3 +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/mpc85xx/Makefile b/target/linux/mpc85xx/Makefile new file mode 100644 index 0000000..5f3ad6c --- /dev/null +++ b/target/linux/mpc85xx/Makefile @@ -0,0 +1,35 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=powerpc +BOARD:=mpc85xx +BOARDNAME:=Freescale MPC85xx +CPU_TYPE:=8540 +FEATURES:=squashfs +MAINTAINER:=Imre Kaloz +SUBTARGETS=generic p1020 + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +KERNEL_IMAGES := zImage +ifeq ($(SUBTARGET),generic) +KERNEL_IMAGES += cuImage.tl-wdr4900-v1 +endif + +DEFAULT_PACKAGES += \ + kmod-input-core kmod-input-gpio-keys kmod-button-hotplug \ + kmod-leds-gpio kmod-booke-wdt \ + swconfig kmod-ath9k wpad-mini + +define Target/Description + Build images for the Freescale MPC85xx based boards. +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/mpc85xx/base-files.mk b/target/linux/mpc85xx/base-files.mk new file mode 100644 index 0000000..d6682bd --- /dev/null +++ b/target/linux/mpc85xx/base-files.mk @@ -0,0 +1,5 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef + + diff --git a/target/linux/mpc85xx/base-files/etc/diag.sh b/target/linux/mpc85xx/base-files/etc/diag.sh new file mode 100644 index 0000000..1107763 --- /dev/null +++ b/target/linux/mpc85xx/base-files/etc/diag.sh @@ -0,0 +1,35 @@ +#!/bin/sh +# Copyright (C) 2013 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/mpc85xx.sh + +get_status_led() { + case $(mpc85xx_board_name) in + tl-wdr4900-v1) + status_led="tp-link:blue:system" + ;; + esac +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_blink_preinit + ;; + + failsafe) + status_led_blink_failsafe + ;; + + preinit_regular) + status_led_blink_preinit_regular + ;; + + done) + status_led_on + ;; + esac +} diff --git a/target/linux/mpc85xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom b/target/linux/mpc85xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom new file mode 100644 index 0000000..0baec28 --- /dev/null +++ b/target/linux/mpc85xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom @@ -0,0 +1,71 @@ +#!/bin/sh + +FW_FILE="/lib/firmware/$FIRMWARE" + +ath9k_eeprom_die() { + echo "ath9k eeprom: " "$*" >&2 + exit 1 +} + +ath9k_eeprom_extract() { + local part=$1 + local offset=$2 + local count=$3 + local mtd + + . /lib/functions.sh + . /lib/functions/system.sh + + mtd=$(find_mtd_chardev $part) + [ -n "$mtd" ] || \ + ath9k_eeprom_die "no mtd device found for partition $part" + + dd if=$mtd bs=$offset skip=1 count=1 2>/dev/null | dd of=$FW_FILE bs=$count count=1 2>/dev/null || \ + ath9k_eeprom_die "failed to extract from $mtd" +} + +tpl_set_wireless_mac() +{ + local offset=$1 + local mac + + . /lib/functions.sh + . /lib/functions/system.sh + + mac=$(mtd_get_mac_binary u-boot 326656) + mac=$(macaddr_add $mac $offset) + + macaddr_2bin $mac | dd bs=1 count=6 seek=2 conv=notrunc of=$FW_FILE 2>/dev/null +} + +[ -e $FW_FILE ] && exit 0 + +. /lib/mpc85xx.sh + +board=$(mpc85xx_board_name) + +case "$FIRMWARE" in +"pci_wmac0.eeprom") + case $board in + tl-wdr4900-v1) + ath9k_eeprom_extract "caldata" 4096 2048 + tpl_set_wireless_mac 0 + ;; + *) + ath9k_eeprom_die "board $board is not supported yet" + ;; + esac + ;; + +"pci_wmac1.eeprom") + case $board in + tl-wdr4900-v1) + ath9k_eeprom_extract "caldata" 20480 2048 + tpl_set_wireless_mac -1 + ;; + *) + ath9k_eeprom_die "board $board is not supported yet" + ;; + esac + ;; +esac diff --git a/target/linux/mpc85xx/base-files/etc/uci-defaults/02_network b/target/linux/mpc85xx/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..525a552 --- /dev/null +++ b/target/linux/mpc85xx/base-files/etc/uci-defaults/02_network @@ -0,0 +1,31 @@ +#!/bin/sh +# Copyright (C) 2014 OpenWrt.org + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/mpc85xx.sh +. /lib/functions.sh +. /lib/functions/system.sh + +ucidef_set_interface_loopback + +board=$(mpc85xx_board_name) + +case "$board" in +tl-wdr4900-v1) + ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0t 2 3 4 5" + ucidef_add_switch_vlan "switch0" "2" "0t 1" + ;; +*) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/mpc85xx/base-files/lib/mpc85xx.sh b/target/linux/mpc85xx/base-files/lib/mpc85xx.sh new file mode 100755 index 0000000..5757563 --- /dev/null +++ b/target/linux/mpc85xx/base-files/lib/mpc85xx.sh @@ -0,0 +1,39 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +MPC85XX_BOARD_NAME= +MPC85XX_MODEL= + +mpc85xx_board_detect() { + local model + local name + + model=$(awk 'BEGIN{FS="[ \t]+:[ \t]"} /model/ {print $2}' /proc/cpuinfo) + + case "$model" in + *"TL-WDR4900 v1") + name="tl-wdr4900-v1" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$MPC85XX_BOARD_NAME" ] && MPC85XX_BOARD_NAME="$name" + [ -z "$MPC85XX_MODEL" ] && MPC85XX_MODEL="$model" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$MPC85XX_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$MPC85XX_MODEL" > /tmp/sysinfo/model +} + +mpc85xx_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/mpc85xx/base-files/lib/preinit/03_preinit_do_mpc85xx.sh b/target/linux/mpc85xx/base-files/lib/preinit/03_preinit_do_mpc85xx.sh new file mode 100644 index 0000000..88ba608 --- /dev/null +++ b/target/linux/mpc85xx/base-files/lib/preinit/03_preinit_do_mpc85xx.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_mpc85xx() { + . /lib/mpc85xx.sh + + mpc85xx_board_detect +} + +boot_hook_add preinit_main do_mpc85xx diff --git a/target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx b/target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx new file mode 100644 index 0000000..22d7471 --- /dev/null +++ b/target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx @@ -0,0 +1,12 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +. /lib/mpc85xx.sh + +mpc85xx_set_preinit_iface() { + ifname=eth0 +} + +boot_hook_add preinit_main mpc85xx_set_preinit_iface diff --git a/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh b/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000..d95ec30 --- /dev/null +++ b/target/linux/mpc85xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,85 @@ +# +# Copyright (C) 2011 OpenWrt.org +# + +. /lib/mpc85xx.sh + +PART_NAME=firmware +RAMFS_COPY_DATA=/lib/mpc85xx.sh + +tplink_get_hwid() { + local part + + part=$(find_mtd_part u-boot) + [ -z "$part" ] && return 1 + + dd if=$part bs=4 count=1 skip=81728 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_get_image_hwid() { + get_image "$@" | dd bs=4 count=1 skip=16 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +tplink_get_image_boot_size() { + get_image "$@" | dd bs=4 count=1 skip=37 2>/dev/null | hexdump -v -n 4 -e '1/1 "%02x"' +} + +platform_check_image() { + local board=$(mpc85xx_board_name) + local magic="$(get_magic_long "$1")" + + [ "$#" -gt 1 ] && return 1 + + case $board in + tl-wdr4900-v1) + [ "$magic" != "01000000" ] && { + echo "Invalid image type." + return 1 + } + + local hwid + local imageid + + hwid=$(tplink_get_hwid) + imageid=$(tplink_get_image_hwid "$1") + + [ "$hwid" != "$imageid" ] && { + echo "Invalid image, hardware ID mismatch, hw:$hwid image:$imageid." + return 1 + } + + local boot_size + + boot_size=$(tplink_get_image_boot_size "$1") + [ "$boot_size" != "00000000" ] && { + echo "Invalid image, it contains a bootloader." + return 1 + } + + return 0 + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_do_upgrade() { + local board=$(mpc85xx_board_name) + + case "$board" in + *) + default_do_upgrade "$ARGV" + ;; + esac +} + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/mpc85xx/config-3.18 b/target/linux/mpc85xx/config-3.18 new file mode 100644 index 0000000..4605f27 --- /dev/null +++ b/target/linux/mpc85xx/config-3.18 @@ -0,0 +1,293 @@ +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_ADVANCED_OPTIONS is not set +CONFIG_AR8216_PHY=y +CONFIG_AR8216_PHY_LEDS=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_WALK_MEMORY=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +# CONFIG_ARCH_RANDOM is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_AUDIT_ARCH=y +CONFIG_BOOKE=y +CONFIG_BOUNCE=y +# CONFIG_BSC9131_RDB is not set +# CONFIG_BSC9132_QDS is not set +# CONFIG_C293_PCIE is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyS0,115200" +CONFIG_CMDLINE_BOOL=y +# CONFIG_CORENET_GENERIC is not set +# CONFIG_CPM2 is not set +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +# CONFIG_CRYPTO_SHA1_PPC is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEFAULT_UIMAGE=y +CONFIG_DEVKMEM=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +# CONFIG_E200 is not set +CONFIG_E500=y +CONFIG_EARLY_PRINTK=y +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_EPAPR_BOOT is not set +CONFIG_ETHERNET_PACKET_MANGLE=y +CONFIG_FSL_BOOKE=y +CONFIG_FSL_EMB_PERFMON=y +CONFIG_FSL_LBC=y +CONFIG_FSL_PCI=y +CONFIG_FSL_PQ_MDIO=y +CONFIG_FSL_SOC=y +CONFIG_FSL_SOC_BOOKE=y +CONFIG_FSL_ULI1575=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +# CONFIG_GENERIC_CSUM is not set +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_NVRAM=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +# CONFIG_GENERIC_TBSYNC is not set +CONFIG_GENERIC_TIME_VSYSCALL_OLD=y +CONFIG_GEN_RTC=y +# CONFIG_GEN_RTC_X is not set +# CONFIG_GE_FPGA is not set +# CONFIG_GE_IMP3A is not set +CONFIG_GIANFAR=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_MPC8XXX=y +CONFIG_GPIO_SYSFS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_RAPIDIO=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +# CONFIG_IPIC is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_ISA_DMA_API=y +CONFIG_KERNEL_START=0xc0000000 +# CONFIG_KSI8560 is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_LIBFDT=y +CONFIG_LOWMEM_CAM_NUM=3 +CONFIG_LOWMEM_SIZE=0x30000000 +CONFIG_LXT_PHY=y +# CONFIG_MATH_EMULATION is not set +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIGRATION=y +# CONFIG_MMIO_NVRAM is not set +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MPC8536_DS is not set +# CONFIG_MPC8540_ADS is not set +# CONFIG_MPC8560_ADS is not set +CONFIG_MPC85xx_CDS=y +# CONFIG_MPC85xx_DS is not set +CONFIG_MPC85xx_MDS=y +CONFIG_MPC85xx_RDB=y +CONFIG_MPIC=y +# CONFIG_MPIC_MSGR is not set +CONFIG_MPIC_TIMER=y +# CONFIG_MPIC_U3_HT_IRQS is not set +# CONFIG_MPIC_WEIRD is not set +# CONFIG_MTD_CFI is not set +CONFIG_MTD_M25P80=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_NEED_DMA_MAP_STATE is not set +# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NEED_SG_DMA_LENGTH=y +# CONFIG_NONSTATIC_KERNEL is not set +CONFIG_NR_IRQS=512 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND=y +CONFIG_P1010_RDB=y +# CONFIG_P1022_DS is not set +# CONFIG_P1022_RDK is not set +# CONFIG_P1023_RDB is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xc0000000 +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEASPM=y +# CONFIG_PCIEASPM_DEBUG is not set +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PHYLIB=y +CONFIG_PHYSICAL_ALIGN=0x04000000 +CONFIG_PHYSICAL_START=0x00000000 +# CONFIG_PHYS_64BIT is not set +# CONFIG_PPA8548 is not set +CONFIG_PPC=y +CONFIG_PPC32=y +# CONFIG_PPC64 is not set +CONFIG_PPC_85xx=y +# CONFIG_PPC_8xx is not set +# CONFIG_PPC_970_NAP is not set +CONFIG_PPC_ADV_DEBUG_DACS=2 +CONFIG_PPC_ADV_DEBUG_DVCS=0 +CONFIG_PPC_ADV_DEBUG_IACS=2 +CONFIG_PPC_ADV_DEBUG_REGS=y +CONFIG_PPC_BOOK3E_MMU=y +# CONFIG_PPC_BOOK3S_32 is not set +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PPC_COPRO_BASE is not set +# CONFIG_PPC_DCR_MMIO is not set +# CONFIG_PPC_DCR_NATIVE is not set +CONFIG_PPC_DOORBELL=y +# CONFIG_PPC_E500MC is not set +# CONFIG_PPC_EARLY_DEBUG is not set +# CONFIG_PPC_EPAPR_HV_PIC is not set +CONFIG_PPC_FSL_BOOK3E=y +CONFIG_PPC_I8259=y +# CONFIG_PPC_ICP_HV is not set +# CONFIG_PPC_ICP_NATIVE is not set +# CONFIG_PPC_ICS_RTAS is not set +CONFIG_PPC_INDIRECT_PCI=y +CONFIG_PPC_LIB_RHEAP=y +CONFIG_PPC_MMU_NOHASH=y +# CONFIG_PPC_MM_SLICES is not set +# CONFIG_PPC_MPC106 is not set +CONFIG_PPC_OF=y +# CONFIG_PPC_P7_NAP is not set +CONFIG_PPC_PCI_CHOICE=y +# CONFIG_PPC_QEMU_E500 is not set +# CONFIG_PPC_RTAS is not set +CONFIG_PPC_SMP_MUXED_IPI=y +CONFIG_PPC_UDBG_16550=y +CONFIG_PPC_WERROR=y +# CONFIG_PPC_XICS is not set +# CONFIG_PQ2ADS is not set +# CONFIG_PREEMPT_RCU is not set +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PTP_1588_CLOCK_GIANFAR is not set +CONFIG_QE_GPIO=y +CONFIG_QUICC_ENGINE=y +CONFIG_RAS=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +# CONFIG_SBC8548 is not set +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_QE is not set +CONFIG_SIMPLE_GPIO=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SOCK_DIAG=y +# CONFIG_SOCRATES is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPE=y +CONFIG_SPE_POSSIBLE=y +CONFIG_SPI=y +CONFIG_SPI_FSL_ESPI=y +CONFIG_SPI_FSL_LIB=y +CONFIG_SPI_MASTER=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_STX_GP3 is not set +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_TASK_SIZE=0xc0000000 +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TL_WDR4900_V1=y +# CONFIG_TQM8540 is not set +# CONFIG_TQM8541 is not set +# CONFIG_TQM8548 is not set +# CONFIG_TQM8555 is not set +# CONFIG_TQM8560 is not set +# CONFIG_TWR_P102x is not set +CONFIG_UCC=y +CONFIG_UCC_FAST=y +CONFIG_UCC_GETH=y +# CONFIG_UGETH_TX_ON_DEMAND is not set +CONFIG_USB_SUPPORT=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WORD_SIZE=32 +# CONFIG_XES_MPC85xx is not set +CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_POWERPC=y diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/cuboot-tl-wdr4900-v1.c b/target/linux/mpc85xx/files/arch/powerpc/boot/cuboot-tl-wdr4900-v1.c new file mode 100644 index 0000000..17459ef --- /dev/null +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/cuboot-tl-wdr4900-v1.c @@ -0,0 +1,168 @@ +/* + * U-Boot compatibility wrapper for the TP-Link TL-WDR4900 v1 board + * + * Copyright (c) 2013 Gabor Juhos + * + * Based on: + * cuboot-85xx.c + * Author: Scott Wood + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * + * simpleboot.c + * Authors: Scott Wood + * Grant Likely + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * Copyright (c) 2008 Secret Lab Technologies Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "types.h" +#include "io.h" +#include "stdio.h" +#include + +BSS_STACK(4*1024); + +static unsigned long bus_freq; +static unsigned long int_freq; +static u64 mem_size; +static unsigned char enetaddr[6]; + +static void process_boot_dtb(void *boot_dtb) +{ + const u32 *na, *ns, *reg, *val32; + const char *path; + u64 memsize64; + int node, size, i; + + /* Make sure FDT blob is sane */ + if (fdt_check_header(boot_dtb) != 0) + fatal("Invalid device tree blob\n"); + + /* Find the #address-cells and #size-cells properties */ + node = fdt_path_offset(boot_dtb, "/"); + if (node < 0) + fatal("Cannot find root node\n"); + na = fdt_getprop(boot_dtb, node, "#address-cells", &size); + if (!na || (size != 4)) + fatal("Cannot find #address-cells property"); + + ns = fdt_getprop(boot_dtb, node, "#size-cells", &size); + if (!ns || (size != 4)) + fatal("Cannot find #size-cells property"); + + /* Find the memory range */ + node = fdt_node_offset_by_prop_value(boot_dtb, -1, "device_type", + "memory", sizeof("memory")); + if (node < 0) + fatal("Cannot find memory node\n"); + reg = fdt_getprop(boot_dtb, node, "reg", &size); + if (size < (*na+*ns) * sizeof(u32)) + fatal("cannot get memory range\n"); + + /* Only interested in memory based at 0 */ + for (i = 0; i < *na; i++) + if (*reg++ != 0) + fatal("Memory range is not based at address 0\n"); + + /* get the memsize and trucate it to under 4G on 32 bit machines */ + memsize64 = 0; + for (i = 0; i < *ns; i++) + memsize64 = (memsize64 << 32) | *reg++; + if (sizeof(void *) == 4 && memsize64 >= 0x100000000ULL) + memsize64 = 0xffffffff; + + mem_size = memsize64; + + /* get clock frequencies */ + node = fdt_node_offset_by_prop_value(boot_dtb, -1, "device_type", + "cpu", sizeof("cpu")); + if (!node) + fatal("Cannot find cpu node\n"); + + val32 = fdt_getprop(boot_dtb, node, "clock-frequency", &size); + if (!val32 || (size != 4)) + fatal("Cannot get clock frequency"); + + int_freq = *val32; + + val32 = fdt_getprop(boot_dtb, node, "bus-frequency", &size); + if (!val32 || (size != 4)) + fatal("Cannot get bus frequency"); + + bus_freq = *val32; + + path = fdt_get_alias(boot_dtb, "ethernet0"); + if (path) { + const void *p; + + node = fdt_path_offset(boot_dtb, path); + if (node < 0) + fatal("Cannot find ethernet0 node"); + + p = fdt_getprop(boot_dtb, node, "mac-address", &size); + if (!p || (size < 6)) { + printf("no mac-address property, finding local\n\r"); + p = fdt_getprop(boot_dtb, node, "local-mac-address", &size); + } + + if (!p || (size < 6)) + fatal("cannot get MAC addres"); + + memcpy(enetaddr, p, sizeof(enetaddr)); + } +} + +static void platform_fixups(void) +{ + void *soc, *mpic; + + dt_fixup_memory(0, mem_size); + + dt_fixup_mac_address_by_alias("ethernet0", enetaddr); + dt_fixup_cpu_clocks(int_freq, bus_freq / 8, bus_freq); + + /* Unfortunately, the specific model number is encoded in the + * soc node name in existing dts files -- once that is fixed, + * this can do a simple path lookup. + */ + soc = find_node_by_devtype(NULL, "soc"); + if (soc) { + void *serial = NULL; + + setprop(soc, "bus-frequency", &bus_freq, sizeof(bus_freq)); + + while ((serial = find_node_by_devtype(serial, "serial"))) { + if (get_parent(serial) != soc) + continue; + + setprop(serial, "clock-frequency", &bus_freq, + sizeof(bus_freq)); + } + } + + mpic = find_node_by_compatible(NULL, "fsl,mpic"); + if (mpic) + setprop(mpic, "clock-frequency", &bus_freq, sizeof(bus_freq)); +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + mem_size = 64 * 1024 * 1024; + + simple_alloc_init(_end, mem_size - (u32)_end - 1024*1024, 32, 64); + + fdt_init(_dtb_start); + serial_console_init(); + + printf("\n\r-- TL-WDR4900 v1 boot wrapper --\n\r"); + + process_boot_dtb((void *) r3); + + platform_ops.fixups = platform_fixups; +} diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts new file mode 100644 index 0000000..148c7a2 --- /dev/null +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts @@ -0,0 +1,225 @@ +/* + * TP-Link TL-WDR4900 v1 Device Tree Source + * + * Copyright 2013 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/include/ "fsl/p1010si-pre.dtsi" + +/ { + model = "TP-Link TL-WDR4900 v1"; + compatible = "tp-link,TL-WDR4900v1"; + + chosen { + bootargs = "console=ttyS0,115200"; +/* + linux,stdout-path = "/soc@ffe00000/serial@4500"; +*/ + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + }; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + + spi0: spi@7000 { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl129p1"; + reg = <0>; + spi-max-frequency = <25000000>; + + u-boot@0 { + reg = <0x0 0x0050000>; + label = "u-boot"; + read-only; + }; + + dtb@50000 { + reg = <0x00050000 0x00010000>; + label = "dtb"; + read-only; + }; + + kernel@60000 { + reg = <0x00060000 0x002a0000>; + label = "kernel"; + }; + + rootfs@300000 { + reg = <0x00300000 0x00ce0000>; + label = "rootfs"; + }; + + config: config@fe0000 { + reg = <0x00fe0000 0x00010000>; + label = "config"; + read-only; + }; + + caldata@ff0000 { + reg = <0x00ff0000 0x00010000>; + label = "caldata"; + read-only; + }; + + firmware@60000 { + reg = <0x00060000 0x00f80000>; + label = "firmware"; + }; + }; + }; + + gpio0: gpio-controller@f000 { + }; + + usb@22000 { + phy_type = "utmi"; + dr_mode = "host"; + }; + + mdio@24000 { + phy0: ethernet-phy@0 { + reg = <0x0>; + qca,ar8327-initvals = < + 0x00004 0x07600000 /* PAD0_MODE */ + 0x00008 0x00000000 /* PAD5_MODE */ + 0x0000c 0x01000000 /* PAD6_MODE */ + 0x00010 0x40000000 /* POWER_ON_STRIP */ + 0x00050 0xcf35cf35 /* LED_CTRL0 */ + 0x00054 0xcf35cf35 /* LED_CTRL1 */ + 0x00058 0xcf35cf35 /* LED_CTRL2 */ + 0x0005c 0x03ffff00 /* LED_CTRL3 */ + 0x0007c 0x0000007e /* PORT0_STATUS */ + 0x00094 0x00000200 /* PORT6_STATUS */ + >; + }; + }; + + mdio@25000 { + status = "disabled"; + }; + + mdio@26000 { + status = "disabled"; + }; + + enet0: ethernet@b0000 { + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + mtd-mac-address = <&config 0x14c>; + }; + + enet1: ethernet@b1000 { + status = "disabled"; + }; + + enet2: ethernet@b2000 { + status = "disabled"; + }; + + sdhc@2e000 { + status = "disabled"; + }; + + serial1: serial@4600 { + status = "disabled"; + }; + + can0: can@1c000 { + status = "disabled"; + }; + + can1: can@1d000 { + status = "disabled"; + }; + }; + + pci0: pcie@ffe09000 { + reg = <0 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; + pcie@0 { + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + pci1: pcie@ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; + pcie@0 { + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + ifc: ifc@ffe1e000 { + status = "disabled"; + }; + + leds { + compatible = "gpio-leds"; + + system { + gpios = <&gpio0 2 1>; /* active low */ + label = "tp-link:blue:system"; + }; + + usb1 { + gpios = <&gpio0 3 1>; /* active low */ + label = "tp-link:green:usb1"; + }; + + usb2 { + gpios = <&gpio0 4 1>; /* active low */ + label = "tp-link:green:usb2"; + }; + + usbpower { + gpios = <&gpio0 10 1>; /* active low */ + label = "tp-link:usb:power"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + reset { + label = "Reset button"; + gpios = <&gpio0 5 1>; /* active low */ + linux,code = <0x198>; /* KEY_RESTART */ + }; + + rfkill { + label = "RFKILL switch"; + gpios = <&gpio0 11 1>; /* active low */ + linux,code = <0xf7>; /* RFKill */ + }; + }; +}; + +/include/ "fsl/p1010si-post.dtsi" diff --git a/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/tl_wdr4900_v1.c b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/tl_wdr4900_v1.c new file mode 100644 index 0000000..95afa4d --- /dev/null +++ b/target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/tl_wdr4900_v1.c @@ -0,0 +1,145 @@ +/* + * TL-WDR4900 v1 board setup + * + * Copyright (c) 2013 Gabor Juhos + * + * Based on: + * p1010rdb.c: + * P1010RDB Board Setup + * Copyright 2011 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mpc85xx.h" + +void __init tl_wdr4900_v1_pic_init(void) +{ + struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | + MPIC_SINGLE_DEST_CPU, + 0, 256, " OpenPIC "); + + BUG_ON(mpic == NULL); + + mpic_init(mpic); +} + +#ifdef CONFIG_PCI +static struct gpio_led tl_wdr4900_v1_wmac_leds_gpio[] = { + { + .name = "tp-link:blue:wps", + .gpio = 1, + .active_low = 1, + }, +}; + +static struct ath9k_platform_data tl_wdr4900_v1_wmac0_data = { + .led_pin = 0, + .eeprom_name = "pci_wmac0.eeprom", + .leds = tl_wdr4900_v1_wmac_leds_gpio, + .num_leds = ARRAY_SIZE(tl_wdr4900_v1_wmac_leds_gpio), +}; + +static struct ath9k_platform_data tl_wdr4900_v1_wmac1_data = { + .led_pin = 0, + .eeprom_name = "pci_wmac1.eeprom", +}; + +static void tl_wdr4900_v1_pci_wmac_fixup(struct pci_dev *dev) +{ + if (!machine_is(tl_wdr4900_v1)) + return; + + if (dev->bus->number == 1 && + PCI_SLOT(dev->devfn) == 0) { + dev->dev.platform_data = &tl_wdr4900_v1_wmac0_data; + return; + } + + if (dev->bus->number == 3 && + PCI_SLOT(dev->devfn) == 0 && + dev->device == 0xabcd) { + dev->dev.platform_data = &tl_wdr4900_v1_wmac1_data; + + /* + * The PCI header of the AR9381 chip is not programmed + * correctly by the bootloader and the device uses wrong + * data due to that. Replace the broken values with the + * correct ones. + */ + dev->device = 0x30; + dev->class = 0x028000; + + pr_info("pci %s: AR9381 fixup applied\n", pci_name(dev)); + } +} + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, + tl_wdr4900_v1_pci_wmac_fixup); +#endif /* CONFIG_PCI */ + +/* + * Setup the architecture + */ +static void __init tl_wdr4900_v1_setup_arch(void) +{ + if (ppc_md.progress) + ppc_md.progress("tl_wdr4900_v1_setup_arch()", 0); + + fsl_pci_assign_primary(); + + printk(KERN_INFO "TL-WDR4900 v1 board from TP-Link\n"); +} + +machine_arch_initcall(tl_wdr4900_v1, mpc85xx_common_publish_devices); +machine_arch_initcall(tl_wdr4900_v1, swiotlb_setup_bus_notifier); + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init tl_wdr4900_v1_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (of_flat_dt_is_compatible(root, "tp-link,TL-WDR4900v1")) + return 1; + + return 0; +} + +define_machine(tl_wdr4900_v1) { + .name = "Freescale P1014", + .probe = tl_wdr4900_v1_probe, + .setup_arch = tl_wdr4900_v1_setup_arch, + .init_IRQ = tl_wdr4900_v1_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +}; diff --git a/target/linux/mpc85xx/generic/config-default b/target/linux/mpc85xx/generic/config-default new file mode 100644 index 0000000..e69de29 diff --git a/target/linux/mpc85xx/generic/target.mk b/target/linux/mpc85xx/generic/target.mk new file mode 100644 index 0000000..f8a79a7 --- /dev/null +++ b/target/linux/mpc85xx/generic/target.mk @@ -0,0 +1,6 @@ +BOARDNAME:=Generic + +define Target/Description + Build firmware images for generic MPC85xx based boards. +endef + diff --git a/target/linux/mpc85xx/image/Makefile b/target/linux/mpc85xx/image/Makefile new file mode 100644 index 0000000..0ec067e --- /dev/null +++ b/target/linux/mpc85xx/image/Makefile @@ -0,0 +1,75 @@ +# +# Copyright (C) 2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define imgname +$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(patsubst jffs2-%,jffs2,$(patsubst squashfs-%,squashfs,$(1))) +endef + +define sysupname +$(call imgname,$(1),$(2))-sysupgrade.bin +endef + +define factoryname +$(call imgname,$(1),$(2))-factory.bin +endef + +zImage:=$(BIN_DIR)/$(IMG_PREFIX)-zImage + +DTS_TARGETS = mpc8548cds_32b p1010rdb-pa tl-wdr4900-v1 p1020rdb + +define Image/BuildKernel + cp $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage + $(foreach dts,$(DTS_TARGETS), + $(LINUX_DIR)/scripts/dtc/dtc -I dts -O dtb $(DTS_DIR)/$(dts).dts > $(BIN_DIR)/$(IMG_PREFIX)-$(dts).fdt + ) +endef + +define Image/BuildKernel/Initramfs + cp $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-initramfs-zImage + cp $(KDIR)/cuImage.tl-wdr4900-v1-initramfs $(BIN_DIR)/$(IMG_PREFIX)-tl-wdr4900-v1-initramfs.uImage +endef + +define Image/Build/TPLINK + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) $(7) \ + -k $(KDIR)/$(3) \ + -r $(KDIR)/root.$(1) \ + -o $(call factoryname,$(1),$(2)) + -$(STAGING_DIR_HOST)/bin/mktplinkfw \ + -H $(4) -W $(5) -F $(6) -N OpenWrt -V $(REVISION) $(7) -s \ + -k $(KDIR)/$(3) \ + -r $(KDIR)/root.$(1) \ + -o $(call sysupname,$(1),$(2)) +endef + +define Image/Build/Profile/TLWDR4900 + $(call Image/Build/TPLINK,$(1),tl-wdr4900-v1,cuImage.tl-wdr4900-v1,0x49000001,1,16Mppc) +endef + +define Image/Build/Profile/Default + $(call Image/Build/Profile/TLWDR4900,$(1)) +endef + +define Image/Build/ext2 + cp $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-ext2.img +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + cp $(KDIR)/root.squashfs $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs +endef + +PROFILE ?= Default + +define Image/Build + $(call Image/Build/$(1),$(1)) + $(call Image/Build/Profile/$(PROFILE),$(1)) +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/mpc85xx/p1020/config-default b/target/linux/mpc85xx/p1020/config-default new file mode 100644 index 0000000..29c7ebb --- /dev/null +++ b/target/linux/mpc85xx/p1020/config-default @@ -0,0 +1,21 @@ +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +# CONFIG_ARCH_RANDOM is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_CPU_RMAP=y +# CONFIG_GENERIC_CSUM is not set +CONFIG_GENERIC_TBSYNC=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NR_CPUS=2 +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SMP=y +CONFIG_STOP_MACHINE=y +CONFIG_TREE_RCU=y +CONFIG_XPS=y diff --git a/target/linux/mpc85xx/p1020/target.mk b/target/linux/mpc85xx/p1020/target.mk new file mode 100644 index 0000000..c111d7a --- /dev/null +++ b/target/linux/mpc85xx/p1020/target.mk @@ -0,0 +1,6 @@ +BOARDNAME:=P1020 + +define Target/Description + Build firmware images for Freescale P1020 based boards. +endef + diff --git a/target/linux/mpc85xx/patches-3.18/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch b/target/linux/mpc85xx/patches-3.18/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch new file mode 100644 index 0000000..5e5ab10 --- /dev/null +++ b/target/linux/mpc85xx/patches-3.18/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch @@ -0,0 +1,10 @@ +--- a/arch/powerpc/platforms/85xx/common.c ++++ b/arch/powerpc/platforms/85xx/common.c +@@ -30,6 +30,7 @@ static const struct of_device_id mpc85xx + { .compatible = "fsl,mpc8548-guts", }, + /* Probably unnecessary? */ + { .compatible = "gpio-leds", }, ++ { .compatible = "gpio-keys", }, + /* For all PCI controllers */ + { .compatible = "fsl,mpc8540-pci", }, + { .compatible = "fsl,mpc8548-pcie", }, diff --git a/target/linux/mpc85xx/patches-3.18/100-fix_mpc8568e_mds.patch b/target/linux/mpc85xx/patches-3.18/100-fix_mpc8568e_mds.patch new file mode 100644 index 0000000..993b5f7 --- /dev/null +++ b/target/linux/mpc85xx/patches-3.18/100-fix_mpc8568e_mds.patch @@ -0,0 +1,32 @@ +--- a/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi ++++ b/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi +@@ -134,17 +134,8 @@ + + }; + +- duart-sleep-nexus { +- #address-cells = <1>; +- #size-cells = <1>; +- compatible = "simple-bus"; +- sleep = <&pmc 0x00000002>; +- ranges; +- + /include/ "pq3-duart-0.dtsi" + +- }; +- + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8568-l2-cache-controller"; + reg = <0x20000 0x1000>; +--- a/arch/powerpc/boot/dts/mpc8568mds.dts ++++ b/arch/powerpc/boot/dts/mpc8568mds.dts +@@ -309,6 +309,9 @@ + gpios = <&bcsr5 3 0>; + }; + }; ++ chosen { ++ linux,stdout-path = "/soc8568@e0000000/serial@4500"; ++ }; + }; + + /include/ "fsl/mpc8568si-post.dtsi" diff --git a/target/linux/mpc85xx/patches-3.18/101-net-gianfar-use-mtd-mac-address.patch b/target/linux/mpc85xx/patches-3.18/101-net-gianfar-use-mtd-mac-address.patch new file mode 100644 index 0000000..1b7abc8 --- /dev/null +++ b/target/linux/mpc85xx/patches-3.18/101-net-gianfar-use-mtd-mac-address.patch @@ -0,0 +1,19 @@ +--- a/drivers/net/ethernet/freescale/gianfar.c ++++ b/drivers/net/ethernet/freescale/gianfar.c +@@ -858,10 +858,13 @@ static int gfar_of_init(struct platform_ + if (stash_len || stash_idx) + priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; + +- mac_addr = of_get_mac_address(np); ++ err = of_get_mac_address_mtd(np, dev->dev_addr); ++ if (err) { ++ mac_addr = of_get_mac_address(np); + +- if (mac_addr) +- memcpy(dev->dev_addr, mac_addr, ETH_ALEN); ++ if (mac_addr) ++ memcpy(dev->dev_addr, mac_addr, ETH_ALEN); ++ } + + if (model && !strcasecmp(model, "TSEC")) + priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT | diff --git a/target/linux/mpc85xx/patches-3.18/110-fix_mpc8548_cds.patch b/target/linux/mpc85xx/patches-3.18/110-fix_mpc8548_cds.patch new file mode 100644 index 0000000..b6dbd0d --- /dev/null +++ b/target/linux/mpc85xx/patches-3.18/110-fix_mpc8548_cds.patch @@ -0,0 +1,40 @@ +--- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi ++++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi +@@ -131,7 +131,24 @@ + + /include/ "pq3-i2c-0.dtsi" + /include/ "pq3-i2c-1.dtsi" +-/include/ "pq3-duart-0.dtsi" ++ ++ serial0: serial@4600 { ++ cell-index = <1>; ++ device_type = "serial"; ++ compatible = "fsl,ns16550", "ns16550"; ++ reg = <0x4600 0x100>; ++ clock-frequency = <0>; ++ interrupts = <42 2 0 0>; ++ }; ++ ++ serial1: serial@4500 { ++ cell-index = <0>; ++ device_type = "serial"; ++ compatible = "fsl,ns16550", "ns16550"; ++ reg = <0x4500 0x100>; ++ clock-frequency = <0>; ++ interrupts = <42 2 0 0>; ++ }; + + L2: l2-cache-controller@20000 { + compatible = "fsl,mpc8548-l2-cache-controller"; +--- a/arch/powerpc/boot/dts/mpc8548cds_32b.dts ++++ b/arch/powerpc/boot/dts/mpc8548cds_32b.dts +@@ -75,6 +75,9 @@ + ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>; + }; + }; ++ chosen { ++ linux,stdout-path = "/soc8548@e0000000/serial@4600"; ++ }; + }; + + /* diff --git a/target/linux/mpc85xx/patches-3.18/120-mpc8548_cds_i8259_noirq_init.patch b/target/linux/mpc85xx/patches-3.18/120-mpc8548_cds_i8259_noirq_init.patch new file mode 100644 index 0000000..81b9193 --- /dev/null +++ b/target/linux/mpc85xx/patches-3.18/120-mpc8548_cds_i8259_noirq_init.patch @@ -0,0 +1,23 @@ +--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c ++++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c +@@ -247,15 +247,16 @@ static int mpc85xx_cds_8259_attach(void) + return -ENODEV; + } + ++ i8259_init(cascade_node, 0); ++ of_node_put(cascade_node); ++ + cascade_irq = irq_of_parse_and_map(cascade_node, 0); + if (cascade_irq == NO_IRQ) { +- printk(KERN_ERR "Failed to map cascade interrupt\n"); ++ of_node_put(cascade_node); ++ printk(KERN_DEBUG "No interrupt for i8259 PIC\n"); + return -ENXIO; + } + +- i8259_init(cascade_node, 0); +- of_node_put(cascade_node); +- + /* + * Hook the interrupt to make sure desc->action is never NULL. + * This is required to ensure that the interrupt does not get diff --git a/target/linux/mpc85xx/patches-3.18/130-mpc8548_cds_disable_i8259_irq.patch b/target/linux/mpc85xx/patches-3.18/130-mpc8548_cds_disable_i8259_irq.patch new file mode 100644 index 0000000..7d9e63c --- /dev/null +++ b/target/linux/mpc85xx/patches-3.18/130-mpc8548_cds_disable_i8259_irq.patch @@ -0,0 +1,13 @@ +--- a/arch/powerpc/boot/dts/mpc8548cds.dtsi ++++ b/arch/powerpc/boot/dts/mpc8548cds.dtsi +@@ -289,8 +289,10 @@ + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "chrp,iic"; ++/* + interrupts = <0 1 0 0>; + interrupt-parent = <&mpic>; ++*/ + }; + + rtc@70 { diff --git a/target/linux/mpc85xx/patches-3.18/140-powerpc-85xx-tl-wdr4900-v1-support.patch b/target/linux/mpc85xx/patches-3.18/140-powerpc-85xx-tl-wdr4900-v1-support.patch new file mode 100644 index 0000000..9b4815c --- /dev/null +++ b/target/linux/mpc85xx/patches-3.18/140-powerpc-85xx-tl-wdr4900-v1-support.patch @@ -0,0 +1,78 @@ +From 406d86e5990ac171f18ef6e2973672d8fbfe1556 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Wed, 20 Feb 2013 08:40:33 +0100 +Subject: [PATCH] powerpc: 85xx: add support for the TP-Link TL-WDR4900 v1 + board + +This patch adds support for the TP-Link TL-WDR4900 v1 +concurrent dual-band wireless router. The devices uses +the Freescale P1014 SoC. + +Signed-off-by: Gabor Juhos +--- + arch/powerpc/boot/Makefile | 3 + + arch/powerpc/boot/wrapper | 4 + + arch/powerpc/platforms/85xx/Kconfig | 11 ++ + arch/powerpc/platforms/85xx/Makefile | 1 + + +--- a/arch/powerpc/boot/Makefile ++++ b/arch/powerpc/boot/Makefile +@@ -112,6 +112,7 @@ src-plat-$(CONFIG_PPC_POWERNV) += pserie + src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S + src-plat-$(CONFIG_PPC_CELLEB) += pseries-head.S + src-plat-$(CONFIG_PPC_CELL_QPACE) += pseries-head.S ++src-plat-$(CONFIG_TL_WDR4900_V1) += cuboot-tl-wdr4900-v1.c + + src-wlib := $(sort $(src-wlib-y)) + src-plat := $(sort $(src-plat-y)) +@@ -296,6 +297,7 @@ image-$(CONFIG_TQM8555) += cuImage.tqm + image-$(CONFIG_TQM8560) += cuImage.tqm8560 + image-$(CONFIG_SBC8548) += cuImage.sbc8548 + image-$(CONFIG_KSI8560) += cuImage.ksi8560 ++image-$(CONFIG_TL_WDR4900_V1) += cuImage.tl-wdr4900-v1 + + # Board ports in arch/powerpc/platform/embedded6xx/Kconfig + image-$(CONFIG_STORCENTER) += cuImage.storcenter +--- a/arch/powerpc/boot/wrapper ++++ b/arch/powerpc/boot/wrapper +@@ -218,6 +218,10 @@ cuboot*) + *-mpc85*|*-tqm85*|*-sbc85*) + platformo=$object/cuboot-85xx.o + ;; ++ *-tl-wdr4900-v1) ++ platformo=$object/cuboot-tl-wdr4900-v1.o ++ link_address='0x1000000' ++ ;; + *-amigaone) + link_address='0x800000' + ;; +--- a/arch/powerpc/platforms/85xx/Kconfig ++++ b/arch/powerpc/platforms/85xx/Kconfig +@@ -168,6 +168,17 @@ config STX_GP3 + select CPM2 + select DEFAULT_UIMAGE + ++config TL_WDR4900_V1 ++ bool "TP-Link TL-WDR4900 v1" ++ select DEFAULT_UIMAGE ++ select ARCH_REQUIRE_GPIOLIB ++ select GPIO_MPC8XXX ++ help ++ This option enables support for the TP-Link TL-WDR4900 v1 board. ++ ++ This board is a Concurrent Dual-Band wireless router with a ++ Freescale P1014 SoC. ++ + config TQM8540 + bool "TQ Components TQM8540" + help +--- a/arch/powerpc/platforms/85xx/Makefile ++++ b/arch/powerpc/platforms/85xx/Makefile +@@ -23,6 +23,7 @@ obj-$(CONFIG_TWR_P102x) += twr_p102x.o + obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o + obj-$(CONFIG_STX_GP3) += stx_gp3.o + obj-$(CONFIG_TQM85xx) += tqm85xx.o ++obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o + obj-$(CONFIG_SBC8548) += sbc8548.o + obj-$(CONFIG_PPA8548) += ppa8548.o + obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o diff --git a/target/linux/mpc85xx/patches-3.18/210-spi-fsl-espi-preallocate-local-buffer.patch b/target/linux/mpc85xx/patches-3.18/210-spi-fsl-espi-preallocate-local-buffer.patch new file mode 100644 index 0000000..7335f18 --- /dev/null +++ b/target/linux/mpc85xx/patches-3.18/210-spi-fsl-espi-preallocate-local-buffer.patch @@ -0,0 +1,147 @@ +From: Gabor Juhos +Subject: spi-fsl-espi: avoid frequent high order allocations + +The driver allocates 64KiB of memory fro a local buffer before +each transfer and releases that afterwards. When the memory is +fragmented this allocation often fails and causes a warning like +this: + + kworker/u2:2: page allocation failure: order:4, mode:0x10c0d0 + CPU: 0 PID: 7011 Comm: kworker/u2:2 Not tainted 3.10.24 #1 + Workqueue: ffe07000.spi mpc8xxx_spi_work + Call Trace: + [c1c6dcf0] [c0006914] show_stack+0x50/0x170 (unreliable) + [c1c6dd30] [c0259858] dump_stack+0x24/0x34 + [c1c6dd40] [c00672e8] warn_alloc_failed+0x120/0x13c + [c1c6dd90] [c0069920] __alloc_pages_nodemask+0x574/0x5c8 + [c1c6de20] [c0069990] __get_free_pages+0x1c/0x4c + [c1c6de30] [c0185174] fsl_espi_do_one_msg+0x128/0x2a0 + [c1c6de90] [c0184290] mpc8xxx_spi_work+0x50/0x7c + [c1c6dea0] [c0037af8] process_one_work+0x208/0x30c + [c1c6dec0] [c00387a0] worker_thread+0x20c/0x308 + [c1c6def0] [c003de60] kthread+0xa4/0xa8 + [c1c6df40] [c000c4bc] ret_from_kernel_thread+0x5c/0x64 + + m25p80 spi0.0: error -12 reading SR + end_request: I/O error, dev mtdblock3, sector 680 + SQUASHFS error: squashfs_read_data failed to read block 0x54a4a + SQUASHFS error: Unable to read data cache entry [54a4a] + +Preallocate the buffer from the probe routine to avoid +this. + +Signed-off-by: Gabor Juhos +--- + drivers/spi/spi-fsl-espi.c | 34 ++++++++++++++++------------------ + drivers/spi/spi-fsl-lib.h | 1 + + 2 files changed, 17 insertions(+), 18 deletions(-) + +--- a/drivers/spi/spi-fsl-espi.c ++++ b/drivers/spi/spi-fsl-espi.c +@@ -329,17 +329,13 @@ static void fsl_espi_do_trans(struct spi + static void fsl_espi_cmd_trans(struct spi_message *m, + struct fsl_espi_transfer *trans, u8 *rx_buff) + { ++ struct spi_device *spi = m->spi; ++ struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); + struct spi_transfer *t; +- u8 *local_buf; ++ u8 *local_buf = mspi->local_buf; + int i = 0; + struct fsl_espi_transfer *espi_trans = trans; + +- local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); +- if (!local_buf) { +- espi_trans->status = -ENOMEM; +- return; +- } +- + list_for_each_entry(t, &m->transfers, transfer_list) { + if (t->tx_buf) { + memcpy(local_buf + i, t->tx_buf, t->len); +@@ -352,28 +348,23 @@ static void fsl_espi_cmd_trans(struct sp + fsl_espi_do_trans(m, espi_trans); + + espi_trans->actual_length = espi_trans->len; +- kfree(local_buf); + } + + static void fsl_espi_rw_trans(struct spi_message *m, + struct fsl_espi_transfer *trans, u8 *rx_buff) + { ++ struct spi_device *spi = m->spi; ++ struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); + struct fsl_espi_transfer *espi_trans = trans; + unsigned int n_tx = espi_trans->n_tx; + unsigned int n_rx = espi_trans->n_rx; + struct spi_transfer *t; +- u8 *local_buf; ++ u8 *local_buf = mspi->local_buf; + u8 *rx_buf = rx_buff; + unsigned int trans_len; + unsigned int addr; + int i, pos, loop; + +- local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); +- if (!local_buf) { +- espi_trans->status = -ENOMEM; +- return; +- } +- + for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) { + trans_len = n_rx - pos; + if (trans_len > SPCOM_TRANLEN_MAX - n_tx) +@@ -407,8 +398,6 @@ static void fsl_espi_rw_trans(struct spi + else + espi_trans->actual_length += espi_trans->len; + } +- +- kfree(local_buf); + } + + static void fsl_espi_do_one_msg(struct spi_message *m) +@@ -585,6 +574,7 @@ static irqreturn_t fsl_espi_irq(s32 irq, + static void fsl_espi_remove(struct mpc8xxx_spi *mspi) + { + iounmap(mspi->reg_base); ++ kfree(mspi->local_buf); + } + + static struct spi_master * fsl_espi_probe(struct device *dev, +@@ -619,10 +609,16 @@ static struct spi_master * fsl_espi_prob + mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg; + mpc8xxx_spi->spi_remove = fsl_espi_remove; + ++ mpc8xxx_spi->local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL); ++ if (!mpc8xxx_spi->local_buf) { ++ ret = -ENOMEM; ++ goto err_probe; ++ } ++ + mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); + if (!mpc8xxx_spi->reg_base) { + ret = -ENOMEM; +- goto err_probe; ++ goto free_buf; + } + + reg_base = mpc8xxx_spi->reg_base; +@@ -689,6 +685,8 @@ unreg_master: + free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); + free_irq: + iounmap(mpc8xxx_spi->reg_base); ++free_buf: ++ kfree(mpc8xxx_spi->local_buf); + err_probe: + spi_master_put(master); + err: +--- a/drivers/spi/spi-fsl-lib.h ++++ b/drivers/spi/spi-fsl-lib.h +@@ -30,6 +30,7 @@ struct mpc8xxx_spi { + void *rx; + #ifdef CONFIG_SPI_FSL_ESPI + int len; ++ u8 *local_buf; + #endif + + int subblock; diff --git a/target/linux/mpc85xx/profiles/00-default.mk b/target/linux/mpc85xx/profiles/00-default.mk new file mode 100644 index 0000000..a0b2558 --- /dev/null +++ b/target/linux/mpc85xx/profiles/00-default.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (all drivers) + PACKAGES:=kmod-usb-core kmod-usb2 kmod-usb2-fsl +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/mpc85xx/profiles/tp-link.mk b/target/linux/mpc85xx/profiles/tp-link.mk new file mode 100644 index 0000000..47ddacd --- /dev/null +++ b/target/linux/mpc85xx/profiles/tp-link.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/TLWDR4900 + NAME:=TP-Link TL-WDR4900 + PACKAGES:=\ + kmod-usb-core kmod-usb2 kmod-usb2-fsl \ + kmod-ath9k wpad-mini +endef + +define Profile/TLWDR4900/Description + Package set optimized for the TP-Link TL-WDR4900. +endef +$(eval $(call Profile,TLWDR4900)) diff --git a/target/linux/mvebu/Makefile b/target/linux/mvebu/Makefile new file mode 100644 index 0000000..5b09285 --- /dev/null +++ b/target/linux/mvebu/Makefile @@ -0,0 +1,25 @@ +# +# Copyright (C) 2012-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=mvebu +BOARDNAME:=Marvell Armada 37x/38x/XP +FEATURES:=usb pci pcie gpio nand squashfs +CPU_TYPE:=cortex-a9 +CPU_SUBTYPE:=vfpv3 +MAINTAINER:=Imre Kaloz + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +KERNELNAME:=zImage dtbs + +DEFAULT_PACKAGES += uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/target/linux/mvebu/base-files.mk b/target/linux/mvebu/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/mvebu/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/mvebu/base-files/etc/crontabs/root b/target/linux/mvebu/base-files/etc/crontabs/root new file mode 100644 index 0000000..e692f57 --- /dev/null +++ b/target/linux/mvebu/base-files/etc/crontabs/root @@ -0,0 +1 @@ +*/5 * * * * /sbin/fan_ctrl.sh diff --git a/target/linux/mvebu/base-files/etc/diag.sh b/target/linux/mvebu/base-files/etc/diag.sh new file mode 100644 index 0000000..6534ac3 --- /dev/null +++ b/target/linux/mvebu/base-files/etc/diag.sh @@ -0,0 +1,32 @@ +#!/bin/sh +# Copyright (C) 2014 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/mvebu.sh + +get_status_led() { + case $(mvebu_board_name) in + armada-xp-linksys-mamba) + status_led="mamba:white:power" + ;; + esac +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/mvebu/base-files/etc/init.d/linksys_recovery b/target/linux/mvebu/base-files/etc/init.d/linksys_recovery new file mode 100755 index 0000000..d9cae7b --- /dev/null +++ b/target/linux/mvebu/base-files/etc/init.d/linksys_recovery @@ -0,0 +1,20 @@ +#!/bin/sh /etc/rc.common +# Copyright (C) 2015 OpenWrt.org + +START=97 +boot() { +. /lib/functions.sh +. /lib/mvebu.sh + +case $(mvebu_board_name) in + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-385-linksys-shelby|armada-xp-linksys-mamba) + # make sure auto_recovery in uboot is always on + AUTO_RECOVERY_ENA="`fw_printenv -n auto_recovery`" + if [ "$AUTO_RECOVERY_ENA" != "yes" ] ; then + fw_setenv auto_recovery yes + fi + # reset the boot counter + mtd resetbc s_env + ;; +esac +} diff --git a/target/linux/mvebu/base-files/etc/uci-defaults/01_leds b/target/linux/mvebu/base-files/etc/uci-defaults/01_leds new file mode 100644 index 0000000..612f949 --- /dev/null +++ b/target/linux/mvebu/base-files/etc/uci-defaults/01_leds @@ -0,0 +1,37 @@ +#!/bin/sh +# +# Copyright (C) 2014 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/mvebu.sh + +board=$(mvebu_board_name) + +case "$board" in +armada-385-linksys-caiman) + ucidef_set_led_netdev "wan" "WAN" "pca963x:caiman:white:wan" "eth0" + ucidef_set_led_usbdev "usb2" "USB2" "pca963x:caiman:white:usb2" "1-1" + ucidef_set_led_usbdev "usb3" "USB3" "pca963x:caiman:white:usb3_1" "2-1" + ;; +armada-385-linksys-cobra) + ucidef_set_led_netdev "wan" "WAN" "pca963x:cobra:white:wan" "eth0" + ucidef_set_led_usbdev "usb2" "USB2" "pca963x:cobra:white:usb2" "1-1" + ucidef_set_led_usbdev "usb3" "USB3" "pca963x:cobra:white:usb3_1" "2-1" + ;; +armada-385-linksys-shelby) + ucidef_set_led_netdev "wan" "WAN" "pca963x:shelby:white:wan" "eth0" + ucidef_set_led_usbdev "usb2" "USB2" "pca963x:shelby:white:usb2" "1-1" + ucidef_set_led_usbdev "usb3" "USB3" "pca963x:shelby:white:usb3_1" "2-1" + ;; +armada-xp-linksys-mamba) + ucidef_set_led_netdev "wan" "WAN" "mamba:white:wan" "eth1" + ucidef_set_led_usbdev "usb2" "USB2" "mamba:white:usb2" "1-1" + ucidef_set_led_usbdev "usb3" "USB3" "mamba:white:usb3_1" "2-2" + ;; + +esac + +ucidef_commit_leds + +exit 0 diff --git a/target/linux/mvebu/base-files/etc/uci-defaults/02_network b/target/linux/mvebu/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..d1da59f --- /dev/null +++ b/target/linux/mvebu/base-files/etc/uci-defaults/02_network @@ -0,0 +1,46 @@ +#!/bin/sh +# +# Copyright (C) 2014-2015 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/mvebu.sh + +ucidef_set_interface_loopback + +board=$(mvebu_board_name) + +case "$board" in +armada-385-linksys-caiman) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +armada-385-linksys-cobra) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +armada-385-linksys-shelby) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +armada-xp-linksys-mamba) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ucidef_add_switch "switch0" "1" "1" + ucidef_add_switch_vlan "switch0" "1" "0 1 2 3 5" + ucidef_add_switch_vlan "switch0" "2" "4 6" + ;; +armada-385-db-ap) + ucidef_set_interfaces_lan_wan "eth0 eth1" "eth2" + ;; +armada-xp-gp) + ucidef_set_interface_lan "eth0 eth1 eth2 eth3" + ;; +*) + ucidef_set_interface_lan "eth0" + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/mvebu/base-files/etc/uci-defaults/03_wireless b/target/linux/mvebu/base-files/etc/uci-defaults/03_wireless new file mode 100644 index 0000000..fcf43ee --- /dev/null +++ b/target/linux/mvebu/base-files/etc/uci-defaults/03_wireless @@ -0,0 +1,39 @@ +#!/bin/sh +# +# Copyright (C) 2015 OpenWrt.org +# + +[ ! -e /etc/config/wireless ] && exit 0 + +. /lib/mvebu.sh + +board=$(mvebu_board_name) + +case "$board" in +armada-385-linksys-caiman|armada-385-linksys-cobra|armada-385-linksys-shelby|armada-xp-linksys-mamba) + SKU=$(strings /dev/mtd3|sed -ne 's/^cert_region=//p') + case "$SKU" in + AP) + REGD=CN + ;; + AU) + REGD=AU + ;; + CA) + REGD=CA + ;; + EU) + REGD=DE + ;; + US) + REGD=US + ;; + esac + uci get wireless.radio0.country || uci set wireless.radio0.country=$REGD + uci get wireless.radio1.country || uci set wireless.radio1.country=$REGD + ;; +esac + +uci commit wireless + +exit 0 diff --git a/target/linux/mvebu/base-files/lib/mvebu.sh b/target/linux/mvebu/base-files/lib/mvebu.sh new file mode 100755 index 0000000..09ebff3 --- /dev/null +++ b/target/linux/mvebu/base-files/lib/mvebu.sh @@ -0,0 +1,73 @@ +#!/bin/sh +# +# Copyright (C) 2013-2015 OpenWrt.org +# + +MVEBU_BOARD_NAME= +MVEBU_MODEL= + +mvebu_board_detect() { + local machine + local name + + machine=$(cat /proc/device-tree/model) + + case "$machine" in + *"Marvell Armada 370 Evaluation Board") + name="armada-370-db" + ;; + *"Globalscale Mirabox") + name="mirabox" + ;; + *"Marvell Armada 370 Reference Design") + name="armada-370-rd" + ;; + *"Marvell Armada XP Evaluation Board") + name="armada-xp-db" + ;; + *"PlatHome OpenBlocks AX3-4 board") + name="openblocks-ax3-4" + ;; + *"Marvell Armada XP GP Board") + name="armada-xp-gp" + ;; + *"Linksys WRT1200AC") + name="armada-385-linksys-caiman" + ;; + *"Linksys WRT1900AC") + name="armada-xp-linksys-mamba" + ;; + *"Linksys WRT1900ACv2") + name="armada-385-linksys-cobra" + ;; + *"Linksys WRT1900ACS") + name="armada-385-linksys-shelby" + ;; + *"Marvell Armada 385 Access Point Development Board") + name="armada-385-db-ap" + ;; + *"Marvell Armada XP Development Board DB-MV784MP-GP") + name="armada-xp-gp" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$MVEBU_BOARD_NAME" ] && MVEBU_BOARD_NAME="$name" + [ -z "$MVEBU_MODEL" ] && MVEBU_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$MVEBU_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$MVEBU_MODEL" > /tmp/sysinfo/model +} + +mvebu_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] || mvebu_board_detect + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/mvebu/base-files/lib/preinit/06_set_iface_mac b/target/linux/mvebu/base-files/lib/preinit/06_set_iface_mac new file mode 100644 index 0000000..876c08b --- /dev/null +++ b/target/linux/mvebu/base-files/lib/preinit/06_set_iface_mac @@ -0,0 +1,26 @@ +# +# Copyright (C) 2014-2015 OpenWrt.org +# + +preinit_set_mac_address() { + local mac + + . /lib/functions.sh + . /lib/mvebu.sh + + case $(mvebu_board_name) in + armada-xp-linksys-mamba) + mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) + ifconfig eth0 hw ether $mac 2>/dev/null + ifconfig eth1 hw ether $mac 2>/dev/null + ;; + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-385-linksys-shelby) + mac=$(mtd_get_mac_ascii devinfo hw_mac_addr) + mac_wan=$(macaddr_setbit_la "$mac") + ifconfig eth1 hw ether $mac 2>/dev/null + ifconfig eth0 hw ether $mac_wan 2>/dev/null + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address diff --git a/target/linux/mvebu/base-files/lib/preinit/81_linksys_syscfg b/target/linux/mvebu/base-files/lib/preinit/81_linksys_syscfg new file mode 100644 index 0000000..a54226f --- /dev/null +++ b/target/linux/mvebu/base-files/lib/preinit/81_linksys_syscfg @@ -0,0 +1,36 @@ +# +# Copyright (C) 2014 OpenWrt.org +# + +preinit_mount_syscfg() { + + . /lib/functions.sh + . /lib/mvebu.sh + + case $(mvebu_board_name) in + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-385-linksys-shelby|armada-xp-linksys-mamba) + needs_recovery=0 + ubiattach -m 8 || needs_recovery=1 + if [ $needs_recovery -eq 1 ] + then + echo "ubifs syscfg partition is damaged, reformatting" + ubidetach -m 8 + ubiformat -y -O 2048 -q /dev/mtd8 + ubiattach -m 8 + ubimkvol /dev/ubi1 -n 0 -N syscfg -t dynamic --maxavsize + fi + mkdir /tmp/syscfg + mount -t ubifs ubi1:syscfg /tmp/syscfg + [ -f /tmp/syscfg/sysupgrade.tgz ] && { + echo "- config restore -" + cd / + mv /tmp/syscfg/sysupgrade.tgz /tmp + tar xzf /tmp/sysupgrade.tgz + rm -f /tmp/sysupgrade.tgz + sync + } + ;; + esac +} + +boot_hook_add preinit_main preinit_mount_syscfg diff --git a/target/linux/mvebu/base-files/lib/upgrade/linksys.sh b/target/linux/mvebu/base-files/lib/upgrade/linksys.sh new file mode 100644 index 0000000..fc40333 --- /dev/null +++ b/target/linux/mvebu/base-files/lib/upgrade/linksys.sh @@ -0,0 +1,86 @@ +# +# Copyright (C) 2014-2015 OpenWrt.org +# + +linksys_get_target_firmware() { + cur_boot_part=`/usr/sbin/fw_printenv -n boot_part` + target_firmware="" + if [ "$cur_boot_part" = "1" ] + then + # current primary boot - update alt boot + target_firmware="kernel2" + fw_setenv boot_part 2 + fw_setenv bootcmd "run altnandboot" + elif [ "$cur_boot_part" = "2" ] + then + # current alt boot - update primary boot + target_firmware="kernel1" + fw_setenv boot_part 1 + fw_setenv bootcmd "run nandboot" + fi + + # re-enable recovery so we get back if the new firmware is broken + fw_setenv auto_recovery yes + + echo "$target_firmware" +} + +linksys_get_root_magic() { + (get_image "$@" | dd skip=786432 bs=4 count=1 | hexdump -v -n 4 -e '1/1 "%02x"') 2>/dev/null +} + +platform_do_upgrade_linksys() { + local magic_long="$(get_magic_long "$1")" + + mkdir -p /var/lock + local part_label="$(linksys_get_target_firmware)" + touch /var/lock/fw_printenv.lock + + if [ ! -n "$part_label" ] + then + echo "cannot find target partition" + exit 1 + fi + + local target_mtd=$(find_mtd_part $part_label) + + [ "$magic_long" = "73797375" ] && { + CI_KERNPART="$part_label" + if [ "$part_label" = "kernel1" ] + then + CI_UBIPART="rootfs1" + else + CI_UBIPART="rootfs2" + fi + + nand_upgrade_tar "$1" + } + [ "$magic_long" = "27051956" ] && { + # check firmwares' rootfs types + local target_mtd=$(find_mtd_part $part_label) + local oldroot="$(linksys_get_root_magic $target_mtd)" + local newroot="$(linksys_get_root_magic "$1")" + + if [ "$newroot" = "55424923" -a "$oldroot" = "55424923" ] + # we're upgrading from a firmware with UBI to one with UBI + then + # erase everything to be safe + mtd erase $part_label + get_image "$1" | mtd -n write - $part_label + else + get_image "$1" | mtd write - $part_label + fi + } +} + +linksys_preupgrade() { + export RAMFS_COPY_BIN="${RAMFS_COPY_BIN} /usr/sbin/fw_printenv /usr/sbin/fw_setenv" + export RAMFS_COPY_BIN="${RAMFS_COPY_BIN} /bin/mkdir /bin/touch" + export RAMFS_COPY_DATA="${RAMFS_COPY_DATA} /etc/fw_env.config /var/lock/fw_printenv.lock" + + [ -f /tmp/sysupgrade.tgz ] && { + cp /tmp/sysupgrade.tgz /tmp/syscfg/sysupgrade.tgz + } +} + +append sysupgrade_pre_upgrade linksys_preupgrade diff --git a/target/linux/mvebu/base-files/lib/upgrade/platform.sh b/target/linux/mvebu/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000..2f699a7 --- /dev/null +++ b/target/linux/mvebu/base-files/lib/upgrade/platform.sh @@ -0,0 +1,50 @@ +# +# Copyright (C) 2014 OpenWrt.org +# + +. /lib/mvebu.sh + +RAMFS_COPY_DATA=/lib/mvebu.sh + +platform_check_image() { + local board=$(mvebu_board_name) + local magic_long="$(get_magic_long "$1")" + + [ "$#" -gt 1 ] && return 1 + + case "$board" in + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-385-linksys-shelby|armada-xp-linksys-mamba) + [ "$magic_long" != "27051956" -a "$magic_long" != "73797375" ] && { + echo "Invalid image type." + return 1 + } + return 0; + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} + +platform_do_upgrade() { + local board=$(mvebu_board_name) + + case "$board" in + armada-385-linksys-caiman|armada-385-linksys-cobra|armada-385-linksys-shelby|armada-xp-linksys-mamba) + platform_do_upgrade_linksys "$ARGV" + ;; + *) + default_do_upgrade "$ARGV" + ;; + esac +} + +disable_watchdog() { + killall watchdog + ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { + echo 'Could not disable watchdog' + return 1 + } +} + +append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/mvebu/base-files/sbin/fan_ctrl.sh b/target/linux/mvebu/base-files/sbin/fan_ctrl.sh new file mode 100755 index 0000000..06e4621 --- /dev/null +++ b/target/linux/mvebu/base-files/sbin/fan_ctrl.sh @@ -0,0 +1,28 @@ +#!/bin/sh + +CPU_TEMP=`cut -c1-2 /sys/class/hwmon/hwmon2/temp1_input` +DDR_TEMP=`cut -c1-2 /sys/class/hwmon/hwmon1/temp1_input` +WIFI_TEMP=`cut -c1-2 /sys/class/hwmon/hwmon1/temp2_input` + +CPU_LOW=85 +CPU_HIGH=95 +DDR_LOW=65 +DDR_HIGH=75 +WIFI_LOW=100 +WIFI_HIGH=115 + +if [ -d /sys/devices/pwm_fan ];then + FAN_CTRL=/sys/devices/pwm_fan/hwmon/hwmon0/pwm1 +elif [ -d /sys/devices/platform/pwm_fan ];then + FAN_CTRL=/sys/devices/platform/pwm_fan/hwmon/hwmon0/pwm1 +else + exit 0 +fi + +if [ "$CPU_TEMP" -ge "$CPU_HIGH" -o "$DDR_TEMP" -ge "$DDR_HIGH" -o "$WIFI_TEMP" -ge "$WIFI_HIGH" ];then + echo "255" > $FAN_CTRL +elif [ "$CPU_TEMP" -ge "$CPU_LOW" -o "$DDR_TEMP" -ge "$DDR_LOW" -o "$WIFI_TEMP" -ge "$WIFI_LOW" ];then + echo "100" > $FAN_CTRL +else + echo "0" > $FAN_CTRL +fi diff --git a/target/linux/mvebu/config-3.18 b/target/linux/mvebu/config-3.18 new file mode 100644 index 0000000..a5eac43 --- /dev/null +++ b/target/linux/mvebu/config-3.18 @@ -0,0 +1,355 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARMADA_370_CLK=y +CONFIG_ARMADA_370_XP_TIMER=y +CONFIG_ARMADA_38X_CLK=y +CONFIG_ARMADA_XP_CLK=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_MVEBU_V7_CPUIDLE=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_FEROCEON_L2 is not set +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PJ4B=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MVEBU_UART=y +# CONFIG_DEBUG_MVEBU_UART_ALTERNATE is not set +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xd0012000 +# CONFIG_DEBUG_UART_PL01X is not set +CONFIG_DEBUG_UART_VIRT=0xfec12000 +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_DEBUG_USER=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_EARLY_PRINTK=y +CONFIG_FIXED_PHY=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MVEBU=y +CONFIG_GPIO_MVEBU_PWM=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LIBFDT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_ARMADA_370=y +# CONFIG_MACH_ARMADA_375 is not set +CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_XP=y +# CONFIG_MACH_DOVE is not set +CONFIG_MACH_MVEBU_ANY=y +CONFIG_MACH_MVEBU_V7=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MANGLE_BOOTARGS=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MEMORY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PXA3xx=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UIMAGE_SPLIT=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MVEBU_CLK_COMMON=y +CONFIG_MVEBU_CLK_COREDIV=y +CONFIG_MVEBU_CLK_CPU=y +CONFIG_MVEBU_DEVBUS=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +CONFIG_MVNETA=y +CONFIG_MVSW61XX_PHY=y +CONFIG_MV_XOR=y +CONFIG_NEED_DMA_MAP_STATE=y +# CONFIG_NEON is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_BOOTMEM=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MVEBU=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_370=y +CONFIG_PINCTRL_ARMADA_38X=y +CONFIG_PINCTRL_ARMADA_XP=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PLAT_ORION=y +CONFIG_PM_OPP=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PWM=y +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_SYSFS=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_ARMADA38X is not set +# CONFIG_RTC_DRV_MV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_DW=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_ORION=y +CONFIG_STOP_MACHINE=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_PHY=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_XEN is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/mvebu/config-4.0 b/target/linux/mvebu/config-4.0 new file mode 100644 index 0000000..a682f1f --- /dev/null +++ b/target/linux/mvebu/config-4.0 @@ -0,0 +1,362 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MVEBU=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARMADA_370_CLK=y +CONFIG_ARMADA_370_XP_TIMER=y +CONFIG_ARMADA_38X_CLK=y +CONFIG_ARMADA_XP_CLK=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_MVEBU_V7_CPUIDLE=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BOUNCE=y +# CONFIG_CACHE_FEROCEON_L2 is not set +CONFIG_CACHE_L2X0=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PJ4B=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_MVEBU_UART0=y +# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set +# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set +CONFIG_DEBUG_UART_8250=y +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=2 +# CONFIG_DEBUG_UART_8250_WORD is not set +CONFIG_DEBUG_UART_PHYS=0xd0012000 +CONFIG_DEBUG_UART_VIRT=0xfec12000 +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_DEBUG_USER=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_EARLY_PRINTK=y +CONFIG_FIXED_PHY=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MVEBU=y +CONFIG_GPIO_MVEBU_PWM=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_IWMMXT is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LIBFDT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_LZ4_COMPRESS is not set +# CONFIG_LZ4_DECOMPRESS is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_ARMADA_370=y +# CONFIG_MACH_ARMADA_375 is not set +CONFIG_MACH_ARMADA_38X=y +CONFIG_MACH_ARMADA_XP=y +# CONFIG_MACH_DOVE is not set +CONFIG_MACH_MVEBU_ANY=y +CONFIG_MACH_MVEBU_V7=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MANGLE_BOOTARGS=y +CONFIG_MARVELL_PHY=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MEMORY=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PXA3xx=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UIMAGE_SPLIT=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_MVEBU_CLK_COMMON=y +CONFIG_MVEBU_CLK_COREDIV=y +CONFIG_MVEBU_CLK_CPU=y +CONFIG_MVEBU_DEVBUS=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +CONFIG_MVNETA=y +CONFIG_MVSW61XX_PHY=y +CONFIG_MV_XOR=y +CONFIG_NEED_DMA_MAP_STATE=y +# CONFIG_NEON is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_NO_BOOTMEM=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +# CONFIG_PCI_DOMAINS_GENERIC is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MVEBU=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_370=y +CONFIG_PINCTRL_ARMADA_38X=y +CONFIG_PINCTRL_ARMADA_XP=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PLAT_ORION=y +CONFIG_PM_OPP=y +CONFIG_PWM=y +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_SYSFS=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MV is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_DW=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SOC_BUS=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_ORION=y +CONFIG_SRCU=y +CONFIG_STOP_MACHINE=y +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_TREE_RCU=y +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_PHY=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_XEN is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-caiman.dts new file mode 100644 index 0000000..2c3b77f --- /dev/null +++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-caiman.dts @@ -0,0 +1,320 @@ +/* + * Device Tree include for the Linksys WRT1200AC (Caiman) + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1200AC"; + compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + soc { + internal-regs{ + i2c@11000 { + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + + wan_amber@0 { + label = "caiman:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "caiman:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "caiman:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "caiman:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "caiman:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "caiman:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "caiman:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "caiman:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "caiman:amber:wps"; + reg = <0x9>; + }; + }; + }; + }; + + pcie-controller { + pcie@1,0 { + mwlwifi { + marvell,2ghz = <0>; + marvell,chainmask = <2 2>; + marvell,powertable { + AU = + <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, + <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, + <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, + <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, + <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, + <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>; 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+ ETSI = + <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, + <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>; + FCC = + <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, + <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, + <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, + <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, + <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>; + }; + }; + }; + + pcie@2,0 { + mwlwifi { + marvell,5ghz = <0>; + marvell,chainmask = <2 2>; + marvell,powertable { + AU = + <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; + CA = + <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>, + <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, + <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>; + CN = + <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; + ETSI = + <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; + FCC = + <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>; + }; + }; + }; + }; + }; + + gpio-leds { + power { + label = "caiman:white:power"; + }; + + sata { + label = "caiman:white:sata"; + }; + }; +}; diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-cobra.dts new file mode 100644 index 0000000..890cfa8 --- /dev/null +++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-cobra.dts @@ -0,0 +1,320 @@ +/* + * Device Tree file for the Linksys WRT1900ACv2 (Cobra) + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1900ACv2"; + compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + soc { + internal-regs{ + i2c@11000 { + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + + wan_amber@0 { + label = "cobra:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "cobra:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "cobra:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "cobra:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "cobra:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "cobra:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "cobra:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "cobra:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "cobra:amber:wps"; + reg = <0x9>; + }; + }; + }; + }; + + pcie-controller { + pcie@1,0 { + mwlwifi { + marvell,2ghz = <0>; + marvell,chainmask = <4 4>; + marvell,powertable { + AU = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; + CA = + <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; + CN = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; + ETSI = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; + FCC = + <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, + <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; + }; + }; + }; + + pcie@2,0 { + mwlwifi { + marvell,5ghz = <0>; + marvell,chainmask = <4 4>; + marvell,powertable { + AU = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + CA = + <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; + CN = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + ETSI = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + FCC = + <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; + }; + }; + }; + }; + }; + + gpio-leds { + power { + label = "cobra:white:power"; + }; + + sata { + label = "cobra:white:sata"; + }; + }; +}; diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-shelby.dts new file mode 100644 index 0000000..da67644 --- /dev/null +++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-shelby.dts @@ -0,0 +1,320 @@ +/* + * Device Tree file for the Linksys WRT1900ACS (Shelby) + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-385-linksys.dtsi" + +/ { + model = "Linksys WRT1900ACS"; + compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + soc { + internal-regs{ + i2c@11000 { + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + + wan_amber@0 { + label = "shelby:amber:wan"; + reg = <0x0>; + }; + + wan_white@1 { + label = "shelby:white:wan"; + reg = <0x1>; + }; + + wlan_2g@2 { + label = "shelby:white:wlan_2g"; + reg = <0x2>; + }; + + wlan_5g@3 { + label = "shelby:white:wlan_5g"; + reg = <0x3>; + }; + + usb2@5 { + label = "shelby:white:usb2"; + reg = <0x5>; + }; + + usb3_1@6 { + label = "shelby:white:usb3_1"; + reg = <0x6>; + }; + + usb3_2@7 { + label = "shelby:white:usb3_2"; + reg = <0x7>; + }; + + wps_white@8 { + label = "shelby:white:wps"; + reg = <0x8>; + }; + + wps_amber@9 { + label = "shelby:amber:wps"; + reg = <0x9>; + }; + }; + }; + }; + + pcie-controller { + pcie@1,0 { + mwlwifi { + marvell,2ghz = <0>; + marvell,chainmask = <4 4>; + marvell,powertable { + AU = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, + <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, + <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; + CA = + <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; + CN = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, + <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; + ETSI = + <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, + <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; + FCC = + <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, + <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, + <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, + <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, + <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, + <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; + }; + }; + }; + + pcie@2,0 { + mwlwifi { + marvell,5ghz = <0>; + marvell,chainmask = <4 4>; + marvell,powertable { + AU = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + CA = + <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; + CN = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + ETSI = + <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, + <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; + FCC = + <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, + <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, + <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; + }; + }; + }; + }; + }; + + gpio-leds { + power { + label = "shelby:white:power"; + }; + + sata { + label = "shelby:white:sata"; + }; + }; +}; diff --git a/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys.dtsi b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys.dtsi new file mode 100644 index 0000000..c6caa86 --- /dev/null +++ b/target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -0,0 +1,301 @@ +/* + * Device Tree include file for Armada 385 based Linksys boards + * + * Copyright (C) 2015 Imre Kaloz + * + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "armada-385.dtsi" + +/ { + model = "Linksys boards based on Armada 385"; + compatible = "linksys,armada385", "marvell,armada385", + "marvell,armada380"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = ; + + internal-regs { + + spi@10600 { + status = "disabled"; + }; + + i2c@11000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + pca9635@68 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9635"; + reg = <0x68>; + }; + }; + + /* J10: VCC, NC, RX, NC, TX, GND */ + serial@12000 { + status = "okay"; + }; + + ethernet@70000 { + status = "okay"; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + ethernet@34000 { + status = "okay"; + phy-mode = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + mdio { + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + }; + + /* USB part of the eSATA/USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + usb-phy = <&usb3_phy>; + }; + + flash@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x200000>; /* 2MB */ + read-only; + }; + + partition@100000 { + label = "u_env"; + reg = <0x200000 0x40000>; /* 256KB */ + }; + + partition@140000 { + label = "s_env"; + reg = <0x240000 0x40000>; /* 256KB */ + }; + + partition@900000 { + label = "devinfo"; + reg = <0x900000 0x100000>; /* 1MB */ + read-only; + }; + + /* kernel1 overlaps with rootfs1 by design */ + partition@a00000 { + label = "kernel1"; + reg = <0xa00000 0x2800000>; /* 40MB */ + }; + + partition@1000000 { + label = "rootfs1"; + reg = <0x1000000 0x2200000>; /* 34MB */ + }; + + /* kernel2 overlaps with rootfs2 by design */ + partition@3200000 { + label = "kernel2"; + reg = <0x3200000 0x2800000>; /* 40MB */ + }; + + partition@3800000 { + label = "rootfs2"; + reg = <0x3800000 0x2200000>; /* 34MB */ + }; + + /* + * 38MB, last MB is for the BBT, not writable + */ + partition@5a00000 { + label = "syscfg"; + reg = <0x5a00000 0x2600000>; + }; + + /* + * Unused area between "s_env" and "devinfo". + * Moved here because otherwise the renumbered + * partitions would break the bootloader + * supplied bootargs + */ + partition@180000 { + label = "unused_area"; + reg = <0x280000 0x680000>; /* 6.5MB */ + }; + }; + + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + }; + + usb3_phy: usb3_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_xhci0_vbus>; + }; + + reg_xhci0_vbus: xhci0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci0_vbus_pins>; + regulator-name = "xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button@1 { + label = "WPS"; + linux,code = ; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "Factory Reset Button"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&power_led_pin &sata_led_pin>; + pinctrl-names = "default"; + + power { + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + sata { + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + mvsw61xx { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,88e6176"; + status = "okay"; + reg = <0x10>; + + mii-bus = <&mdio>; + cpu-port-0 = <5>; + cpu-port-1 = <6>; + }; +}; + +&pinctrl { + keys_pin: keys-pin { + marvell,pins = "mpp24", "mpp29"; + marvell,function = "gpio"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp55"; + marvell,function = "gpio"; + }; + + sata_led_pin: sata-led-pin { + marvell,pins = "mpp54"; + marvell,function = "gpio"; + }; + + xhci0_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp50"; + marvell,function = "gpio"; + }; +}; diff --git a/target/linux/mvebu/image/Makefile b/target/linux/mvebu/image/Makefile new file mode 100644 index 0000000..20a7ac1 --- /dev/null +++ b/target/linux/mvebu/image/Makefile @@ -0,0 +1,225 @@ +# +# Copyright (C) 2012-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +JFFS2_BLOCKSIZE = 128k + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +LOADADDR:=0x00008000 + +define Image/Build/DTB + cp $(KDIR)/zImage$(2) $(KDIR)/zImage$(2)-$(1); + cat $(DTS_DIR)/$(1).dtb >> $(KDIR)/zImage$(2)-$(1); + $(call Image/BuildKernel/MkuImage, \ + none, $(LOADADDR), $(LOADADDR), \ + $(KDIR)/zImage$(2)-$(1), $(KDIR)/uImage$(2)-$(1)) +endef + +# $(1): Profile Name +# $(2): DTB Name +# $(3): Erase Block Size +# $(4): Page Size +# $(5): Sub-Page Size (optional) +# $(6): VID offset (optional) +define NANDProfile + define Image/BuildKernel/Profile/$(1) + $(call Image/Build/DTB,$(2)) + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Profile,$(1)/Initramfs) + endif + endef + + define Image/Build/Profile/$(1)/BuildSysupgrade + $(call Image/Build/SysupgradeNAND,$(2),$$(1),$(KDIR)/uImage-$(2)) + endef + + define Image/Build/Profile/$(1)/Initramfs + $(call Image/Build/DTB,$(2),-initramfs) + cp $(KDIR)/uImage-initramfs-$(2) $(BIN_DIR)/$(IMG_PREFIX)-$(2)-initramfs + endef + + define Image/Build/Profile/$(1)/squashfs + $(call Image/Build/UbinizeImage,$(2),,squashfs, -p $(3) -m $(4) $(if $(5),-s $(5)) $(if $(6),-O $(6))) + endef + + PROFILES_LIST += $(1) +endef + +# $(1): Profile Name +# $(2): DTB Name +# $(3): Erase Block Size +define UBINORProfile + define Image/BuildKernel/Profile/$(1) + $(call Image/Build/DTB,$(2)) + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Profile,$(1)/Initramfs) + endif + endef + + define Image/Build/Profile/$(1)/Initramfs + $(call Image/Build/DTB,$(2),-initramfs) + endef + + define Image/Build/Profile/$(1)/squashfs + $(call Image/Build/UbinizeImage,$(2),,squashfs, -p $(3) -m 1) + endef + + PROFILES_LIST += $(1) +endef + +# $(1): Profile Name +# $(2): DTB Name +# $(3): Erase Block Size +define NORProfile + define Image/BuildKernel/Profile/$(1) + $(call Image/Build/DTB,$(2)) + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Profile,$(1)/Initramfs) + endif + endef + + define Image/Build/Profile/$(1)/Initramfs + $(call Image/Build/DTB,$(2),-initramfs) + endef + + define Image/Build/Profile/$(1)/squashfs + ( \ + dd if=$(KDIR)/uImage-$(2) bs=$(3) conv=sync; \ + dd if=$(KDIR)/root.squashfs bs=$(3) conv=sync; \ + ) > $$(BIN_DIR)/$$(IMG_PREFIX)-$(2)-squashfs-firmware.bin + endef + + PROFILES_LIST += $(1) +endef + +# $(1): Profile Name +# $(2): Sub Profiles list +define MultiProfile + define Image/BuildKernel/Profile/$(1) + $(foreach profile, $(2), + $(call Image/BuildKernel/Profile/$(profile))) + endef + + define Image/Build/Profile/$(1)/BuildSysupgrade + $(foreach profile, $(2), + $(call Image/Build/Profile/$(profile)/BuildSysupgrade,$$(1))) + endef + + define Image/Build/Profile/$(1)/Initramfs + $(foreach profile, $(2), + $(call Image/Build/Profile/$(profile)/Initramfs)) + endef + + define Image/Build/Profile/$(1)/squashfs + $(foreach profile, $(2), + $(call Image/Build/Profile/$(profile)/squashfs)) + endef +endef + +# Boards with NAND, without subpages +$(eval $(call NANDProfile,370-DB,armada-370-db,512KiB,4096)) +$(eval $(call NANDProfile,370-RD,armada-370-rd,512KiB,4096)) +$(eval $(call NANDProfile,385-DB-AP,armada-385-db-ap,256KiB,4096)) +$(eval $(call NANDProfile,Mirabox,armada-370-mirabox,512KiB,4096)) +$(eval $(call NANDProfile,XP-DB,armada-xp-db,512KiB,4096)) +$(eval $(call NANDProfile,XP-GP,armada-xp-gp,512KiB,4096)) + +# Boards with NAND, with subpages +$(eval $(call NANDProfile,Mamba,armada-xp-linksys-mamba,128KiB,2048,512,2048)) +$(eval $(call NANDProfile,Caiman,armada-385-linksys-caiman,128KiB,2048,512,2048)) +$(eval $(call NANDProfile,Cobra,armada-385-linksys-cobra,128KiB,2048,512,2048)) +$(eval $(call NANDProfile,Shelby,armada-385-linksys-shelby,128KiB,2048,512,2048)) + +# Boards with large NOR, where we want to use UBI +$(eval $(call UBINORProfile,OpenBlocks-AX-3-4,armada-xp-openblocks-ax3-4,128KiB)) + +# Boards with small NOR, where UBI doesn't make sense +$(eval $(call NORProfile,385-RD,armada-385-rd,256KiB)) + +### +### Linksys +### + +# Caiman: Linksys WRT1200AC +define Image/Build/Profile/Caiman/squashfs + $(call Image/Build/UbinizeImage,armada-385-linksys-caiman,,squashfs, -p 128KiB -m 2048 -s 512 -O 2048) + ( \ + dd if=$(KDIR)/uImage-armada-385-linksys-caiman bs=6M conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-385-linksys-caiman-squashfs-ubinized.bin \ + bs=2048 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-385-linksys-caiman-squashfs-factory.img +endef + +# Cobra: Linksys WRT1900ACv2 +define Image/Build/Profile/Cobra/squashfs + $(call Image/Build/UbinizeImage,armada-385-linksys-cobra,,squashfs, -p 128KiB -m 2048 -s 512 -O 2048) + ( \ + dd if=$(KDIR)/uImage-armada-385-linksys-cobra bs=6M conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-385-linksys-cobra-squashfs-ubinized.bin \ + bs=2048 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-385-linksys-cobra-squashfs-factory.img +endef + +# Mamba: Linksys WRT1900AC +define Image/Build/Profile/Mamba/squashfs + $(call Image/Build/UbinizeImage,armada-xp-linksys-mamba,,squashfs, -p 128KiB -m 2048 -s 512 -O 2048) + ( \ + dd if=$(KDIR)/uImage-armada-xp-linksys-mamba bs=3072k conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-xp-linksys-mamba-squashfs-ubinized.bin \ + bs=2048 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-xp-linksys-mamba-squashfs-factory.img +endef + +# Shelby: Linksys WRT1900ACS +define Image/Build/Profile/Shelby/squashfs + $(call Image/Build/UbinizeImage,armada-385-linksys-shelby,,squashfs, -p 128KiB -m 2048 -s 512 -O 2048) + ( \ + dd if=$(KDIR)/uImage-armada-385-linksys-shelby bs=6M conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-385-linksys-shelby-squashfs-ubinized.bin \ + bs=2048 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-385-linksys-shelby-squashfs-factory.img +endef + +### +### Marvell +### + +# Marvell Armada 385 Access Point Development board (DB-88F6820-AP) +define Image/Build/Profile/385-DB-AP/squashfs + $(call Image/Build/UbinizeImage,armada-385-db-ap,,squashfs, -p 256KiB -m 4096) + ( \ + dd if=$(KDIR)/uImage-armada-385-db-ap bs=8M conv=sync; \ + dd if=$(KDIR)/$(IMG_PREFIX)-armada-385-db-ap-squashfs-ubinized.bin \ + bs=4096 conv=sync; \ + ) > $(BIN_DIR)/$(IMG_PREFIX)-armada-385-db-ap-squashfs-factory.img +endef + + +# The Default profile should build everything +$(eval $(call MultiProfile,Default,$(PROFILES_LIST))) + +define Image/BuildKernel + $(call Image/BuildKernel/Profile/$(PROFILE)) +endef + +define Image/Build/squashfs + # Align the squashfs image size before calling the profiles, + # otherwise the size would keep growing + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + $(call Image/Build/Profile/$(PROFILE)/squashfs) +endef + +define Image/Build + $(call Image/Build/$(1)) + $(call Image/Build/Profile/$(PROFILE)/BuildSysupgrade,$(1)) +ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(call Image/Build/Profile/$(PROFILE)/Initramfs) +endif +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/mvebu/patches-3.18/001-add_mamba_support.patch b/target/linux/mvebu/patches-3.18/001-add_mamba_support.patch new file mode 100644 index 0000000..44a1adc --- /dev/null +++ b/target/linux/mvebu/patches-3.18/001-add_mamba_support.patch @@ -0,0 +1,388 @@ +From 4824140f4bd1caaf900215aabe27e4bdd1677704 Mon Sep 17 00:00:00 2001 +From: Imre Kaloz +Date: Mon, 16 Feb 2015 13:31:04 +0100 +Subject: [PATCH] ARM: mvebu: add Linksys WRT1900AC (Mamba) support + +The Linksys WRT1900AC (Mamba) is a router that has + +- 2 mini-PCIe slots with Marvell 88W8864 radios +- 1 USB 3.0 port +- 1 USB 2.0/eSATAp port +- 2 Ethernet interfaces connected to a 88E6172 switch (1x WAN + 4x LAN) +- 128MB NAND flash +- 256MB RAM + +gregory.clement@free-electrons.com: - add ARM to the title + - fix the reference to CONFIG_DEBUG_MVEBU_UART0_ALTERNATE + - fix the unbalanced comment for the syscfg partition + +Signed-off-by: Imre Kaloz +Acked-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 348 ++++++++++++++++++++++++++ + 2 files changed, 349 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-xp-linksys-mamba.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -506,6 +506,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-db.dtb \ + armada-xp-gp.dtb \ + armada-xp-lenovo-ix4-300d.dtb \ ++ armada-xp-linksys-mamba.dtb \ + armada-xp-matrix.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-openblocks-ax3-4.dtb +--- /dev/null ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -0,0 +1,348 @@ ++/* ++ * Device Tree file for the Linksys WRT1900AC (Mamba). ++ * ++ * Note: this board is shipped with a new generation boot loader that ++ * remaps internal registers at 0xf1000000. Therefore, if earlyprintk ++ * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be ++ * used. ++ * ++ * Copyright (C) 2014 Imre Kaloz ++ * ++ * Based on armada-xp-axpwifiap.dts: ++ * ++ * Copyright (C) 2013 Marvell ++ * ++ * Thomas Petazzoni ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without ++ * any warranty of any kind, whether express or implied. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include "armada-xp-mv78230.dtsi" ++ ++/ { ++ model = "Linksys WRT1900AC"; ++ compatible = "linksys,mamba", "marvell,armadaxp-mv78230", ++ "marvell,armadaxp", "marvell,armada-370-xp"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ ++ }; ++ ++ soc { ++ ranges = ; ++ ++ pcie-controller { ++ status = "okay"; ++ ++ /* Etron EJ168 USB 3.0 controller */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ /* First mini-PCIe port */ ++ pcie@2,0 { ++ /* Port 0, Lane 1 */ ++ status = "okay"; ++ }; ++ ++ /* Second mini-PCIe port */ ++ pcie@3,0 { ++ /* Port 0, Lane 3 */ ++ status = "okay"; ++ }; ++ }; ++ ++ internal-regs { ++ ++ /* J10: VCC, NC, RX, NC, TX, GND */ ++ serial@12000 { ++ status = "okay"; ++ }; ++ ++ sata@a0000 { ++ nr-ports = <1>; ++ status = "okay"; ++ }; ++ ++ ethernet@70000 { ++ pinctrl-0 = <&ge0_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ ethernet@74000 { ++ pinctrl-0 = <&ge1_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ /* USB part of the eSATA/USB 2.0 port */ ++ usb@50000 { ++ status = "okay"; ++ }; ++ ++ i2c@11000 { ++ status = "okay"; ++ clock-frequency = <100000>; ++ ++ tmp421@4c { ++ compatible = "ti,tmp421"; ++ reg = <0x4c>; ++ }; ++ ++ tlc59116@68 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #gpio-cells = <2>; ++ compatible = "ti,tlc59116"; ++ reg = <0x68>; ++ ++ wan_amber@0 { ++ label = "mamba:amber:wan"; ++ reg = <0x0>; ++ }; ++ ++ wan_white@1 { ++ label = "mamba:white:wan"; ++ reg = <0x1>; ++ }; ++ ++ wlan_2g@2 { ++ label = "mamba:white:wlan_2g"; ++ reg = <0x2>; ++ }; ++ ++ wlan_5g@3 { ++ label = "mamba:white:wlan_5g"; ++ reg = <0x3>; ++ }; ++ ++ esata@4 { ++ label = "mamba:white:esata"; ++ reg = <0x4>; ++ }; ++ ++ usb2@5 { ++ label = "mamba:white:usb2"; ++ reg = <0x5>; ++ }; ++ ++ usb3_1@6 { ++ label = "mamba:white:usb3_1"; ++ reg = <0x6>; ++ }; ++ ++ usb3_2@7 { ++ label = "mamba:white:usb3_2"; ++ reg = <0x7>; ++ }; ++ ++ wps_white@8 { ++ label = "mamba:white:wps"; ++ reg = <0x8>; ++ }; ++ ++ wps_amber@9 { ++ label = "mamba:amber:wps"; ++ reg = <0x9>; ++ }; ++ }; ++ }; ++ ++ nand@d0000 { ++ status = "okay"; ++ num-cs = <1>; ++ marvell,nand-keep-config; ++ marvell,nand-enable-arbiter; ++ nand-on-flash-bbt; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0x100000>; /* 1MB */ ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "u_env"; ++ reg = <0x100000 0x40000>; /* 256KB */ ++ }; ++ ++ partition@140000 { ++ label = "s_env"; ++ reg = <0x140000 0x40000>; /* 256KB */ ++ }; ++ ++ partition@900000 { ++ label = "devinfo"; ++ reg = <0x900000 0x100000>; /* 1MB */ ++ read-only; ++ }; ++ ++ /* kernel1 overlaps with rootfs1 by design */ ++ partition@a00000 { ++ label = "kernel1"; ++ reg = <0xa00000 0x2800000>; /* 40MB */ ++ }; ++ ++ partition@d00000 { ++ label = "rootfs1"; ++ reg = <0xd00000 0x2500000>; /* 37MB */ ++ }; ++ ++ /* kernel2 overlaps with rootfs2 by design */ ++ partition@3200000 { ++ label = "kernel2"; ++ reg = <0x3200000 0x2800000>; /* 40MB */ ++ }; ++ ++ partition@3500000 { ++ label = "rootfs2"; ++ reg = <0x3500000 0x2500000>; /* 37MB */ ++ }; ++ ++ /* ++ * 38MB, last MB is for the BBT, not writable ++ */ ++ partition@5a00000 { ++ label = "syscfg"; ++ reg = <0x5a00000 0x2600000>; ++ }; ++ ++ /* ++ * Unused area between "s_env" and "devinfo". ++ * Moved here because otherwise the renumbered ++ * partitions would break the bootloader ++ * supplied bootargs ++ */ ++ partition@180000 { ++ label = "unused_area"; ++ reg = <0x180000 0x780000>; /* 7.5MB */ ++ }; ++ }; ++ ++ spi0: spi@10600 { ++ status = "okay"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "everspin,mr25h256"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <40000000>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&keys_pin>; ++ pinctrl-names = "default"; ++ ++ button@1 { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button@2 { ++ label = "Factory Reset Button"; ++ linux,code = ; ++ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&power_led_pin>; ++ pinctrl-names = "default"; ++ ++ power { ++ label = "mamba:white:power"; ++ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ gpio_fan { ++ /* SUNON HA4010V4-0000-C99 */ ++ compatible = "gpio-fan"; ++ gpios = <&gpio0 24 0>; ++ ++ gpio-fan,speed-map = <0 0 ++ 4500 1>; ++ }; ++}; ++ ++&pinctrl { ++ ++ keys_pin: keys-pin { ++ marvell,pins = "mpp32", "mpp33"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_led_pin: power-led-pin { ++ marvell,pins = "mpp40"; ++ marvell,function = "gpio"; ++ }; ++ ++ gpio_fan_pin: gpio-fan-pin { ++ marvell,pins = "mpp24"; ++ marvell,function = "gpio"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/002-add_mamba_powertables.patch b/target/linux/mvebu/patches-3.18/002-add_mamba_powertables.patch new file mode 100644 index 0000000..6b51e48 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/002-add_mamba_powertables.patch @@ -0,0 +1,103 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -84,12 +84,100 @@ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; ++ ++ mwlwifi { ++ marvell,5ghz = <0>; ++ marvell,chainmask = <4 4>; ++ marvell,powertable { ++ FCC = ++ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>, ++ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>; ++ ++ ETSI = ++ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>; ++ }; ++ }; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; ++ ++ mwlwifi { ++ marvell,2ghz = <0>; ++ marvell,chainmask = <4 4>; ++ marvell,powertable { ++ FCC = ++ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>; ++ ++ ETSI = ++ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-3.18/003-add_mamba_switch.patch b/target/linux/mvebu/patches-3.18/003-add_mamba_switch.patch new file mode 100644 index 0000000..e43d164 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/003-add_mamba_switch.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -415,6 +415,16 @@ + gpio-fan,speed-map = <0 0 + 4500 1>; + }; ++ ++ mvsw61xx { ++ compatible = "marvell,88e6172"; ++ status = "okay"; ++ reg = <0x10>; ++ ++ mii-bus = <&mdio>; ++ cpu-port-0 = <5>; ++ cpu-port-1 = <6>; ++ }; + }; + + &pinctrl { diff --git a/target/linux/mvebu/patches-3.18/004-mamba_disable_rtc.patch b/target/linux/mvebu/patches-3.18/004-mamba_disable_rtc.patch new file mode 100644 index 0000000..925bab0 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/004-mamba_disable_rtc.patch @@ -0,0 +1,14 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -183,6 +183,11 @@ + + internal-regs { + ++ rtc@10300 { ++ /* No crystal connected to the internal RTC */ ++ status = "disabled"; ++ }; ++ + /* J10: VCC, NC, RX, NC, TX, GND */ + serial@12000 { + status = "okay"; diff --git a/target/linux/mvebu/patches-3.18/007-fix_the_aurora_l2_cache_node.patch b/target/linux/mvebu/patches-3.18/007-fix_the_aurora_l2_cache_node.patch new file mode 100644 index 0000000..20f0f71 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/007-fix_the_aurora_l2_cache_node.patch @@ -0,0 +1,40 @@ +From a9ce1afb35317d2a0646c7530f0ae9822c93cd69 Mon Sep 17 00:00:00 2001 +From: Gregory CLEMENT +Date: Mon, 6 Oct 2014 11:37:56 +0200 +Subject: ARM: mvebu: Fix the Aurora L2 cache node with the required + cache-unified property + +The L2 cache controller on the Armada 370 and Armada XP SoCs is a +unified cache. Moreover, the Aurora cache controller is compatible +with the L2x0 cache controller: the "cache-unified" property is +required by its binding. + +This patch fixes the Aurora L2 cache node for the Armada 370 and +Armada XP SoCs by adding this property. + +Reported-by: Sebastian Hesselbarth +Signed-off-by: Gregory CLEMENT +Acked-by: Sebastian Hesselbarth +Link: https://lkml.kernel.org/r/1412588276-4514-1-git-send-email-gregory.clement@free-electrons.com +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -95,6 +95,7 @@ + compatible = "marvell,aurora-outer-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; ++ cache-unified; + wt-override; + }; + +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -39,6 +39,7 @@ + compatible = "marvell,aurora-system-cache"; + reg = <0x08000 0x1000>; + cache-id-part = <0x100>; ++ cache-unified; + wt-override; + }; + diff --git a/target/linux/mvebu/patches-3.18/008-armada-xp_consolidate_pinctrl_node.patch b/target/linux/mvebu/patches-3.18/008-armada-xp_consolidate_pinctrl_node.patch new file mode 100644 index 0000000..2e1010c --- /dev/null +++ b/target/linux/mvebu/patches-3.18/008-armada-xp_consolidate_pinctrl_node.patch @@ -0,0 +1,81 @@ +From b324fa60ac94b9c00c59f621743715c036d134fa Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:07:09 +0200 +Subject: ARM: mvebu: armada-xp: Consolidate pinctrl node + +All current Armada XP SoCs have their pin controller at 0x18000/0x38. +Move the common properties of pinctrl nodes to armada-xp.dtsi to allow +to share pinctrl settings later. + +Signed-off-by: Sebastian Hesselbarth +Acked-by: Thomas Petazzoni +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -169,13 +169,6 @@ + internal-regs { + pinctrl { + compatible = "marvell,mv78230-pinctrl"; +- reg = <0x18000 0x38>; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; + }; + + gpio0: gpio@18100 { +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -253,13 +253,6 @@ + internal-regs { + pinctrl { + compatible = "marvell,mv78260-pinctrl"; +- reg = <0x18000 0x38>; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; + }; + + gpio0: gpio@18100 { +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -291,13 +291,6 @@ + internal-regs { + pinctrl { + compatible = "marvell,mv78460-pinctrl"; +- reg = <0x18000 0x38>; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; + }; + + gpio0: gpio@18100 { +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -72,6 +72,16 @@ + status = "disabled"; + }; + ++ pinctrl { ++ reg = <0x18000 0x38>; ++ ++ sdio_pins: sdio-pins { ++ marvell,pins = "mpp30", "mpp31", "mpp32", ++ "mpp33", "mpp34", "mpp35"; ++ marvell,function = "sd0"; ++ }; ++ }; ++ + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; diff --git a/target/linux/mvebu/patches-3.18/010-add_node_alias_to_pinctrl_and_add_base_address.patch b/target/linux/mvebu/patches-3.18/010-add_node_alias_to_pinctrl_and_add_base_address.patch new file mode 100644 index 0000000..7224361 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/010-add_node_alias_to_pinctrl_and_add_base_address.patch @@ -0,0 +1,103 @@ +From 264a05e19bf50f93f1a377e16497a626ae9f931e Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:12:00 +0200 +Subject: ARM: mvebu: armada-xp: Add node alias to pinctrl and add base address + +In other MVEBU SoCs, the pin controller node is called pin-ctrl with +its base address added. Also, we have a node alias to access the pinctrl +node easily. Fix this for Armada XP pinctrl nodes to be consistent with +other SoCs. + +Signed-off-by: Sebastian Hesselbarth +Acked-by: Thomas Petazzoni +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -60,7 +60,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + pinctrl-0 = <&pmx_phy_int>; + pinctrl-names = "default"; + +--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts ++++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +@@ -51,7 +51,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + poweroff_pin: poweroff-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -167,7 +167,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + compatible = "marvell,mv78230-pinctrl"; + }; + +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -251,7 +251,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + compatible = "marvell,mv78260-pinctrl"; + }; + +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -289,7 +289,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + compatible = "marvell,mv78460-pinctrl"; + }; + +--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts ++++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +@@ -55,7 +55,7 @@ + }; + + internal-regs { +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + poweroff: poweroff { + marvell,pins = "mpp42"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts ++++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +@@ -81,7 +81,7 @@ + serial@12100 { + status = "okay"; + }; +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + led_pins: led-pins-0 { + marvell,pins = "mpp49", "mpp51", "mpp53"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -72,7 +72,7 @@ + status = "disabled"; + }; + +- pinctrl { ++ pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + + sdio_pins: sdio-pins { diff --git a/target/linux/mvebu/patches-3.18/011-use_pinctrl_node_alias.patch b/target/linux/mvebu/patches-3.18/011-use_pinctrl_node_alias.patch new file mode 100644 index 0000000..d10e092 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/011-use_pinctrl_node_alias.patch @@ -0,0 +1,258 @@ +From 01c434225ee67388711e78166cfe9b159e34fc9d Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:20:09 +0200 +Subject: ARM: mvebu: armada-xp: Use pinctrl node alias + +Armada XP pinctrl node gained an alias, make use of it. + +Signed-off-by: Sebastian Hesselbarth +Acked-by: Thomas Petazzoni +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -60,40 +60,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- pinctrl-0 = <&pmx_phy_int>; +- pinctrl-names = "default"; +- +- pmx_ge0: pmx-ge0 { +- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11"; +- marvell,function = "ge0"; +- }; +- +- pmx_ge1: pmx-ge1 { +- marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge1"; +- }; +- +- pmx_keys: pmx-keys { +- marvell,pins = "mpp33"; +- marvell,function = "gpio"; +- }; +- +- pmx_spi: pmx-spi { +- marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; +- marvell,function = "spi"; +- }; +- +- pmx_phy_int: pmx-phy-int { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +- }; +- + serial@12000 { + status = "okay"; + }; +@@ -162,3 +128,37 @@ + }; + }; + }; ++ ++&pinctrl { ++ pinctrl-0 = <&pmx_phy_int>; ++ pinctrl-names = "default"; ++ ++ pmx_ge0: pmx-ge0 { ++ marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11"; ++ marvell,function = "ge0"; ++ }; ++ ++ pmx_ge1: pmx-ge1 { ++ marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge1"; ++ }; ++ ++ pmx_keys: pmx-keys { ++ marvell,pins = "mpp33"; ++ marvell,function = "gpio"; ++ }; ++ ++ pmx_spi: pmx-spi { ++ marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; ++ marvell,function = "spi"; ++ }; ++ ++ pmx_phy_int: pmx-phy-int { ++ marvell,pins = "mpp32"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts ++++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +@@ -51,37 +51,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- poweroff_pin: poweroff-pin { +- marvell,pins = "mpp24"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp44"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp45"; +- marvell,function = "gpio"; +- }; +- select_button_pin: select-button-pin { +- marvell,pins = "mpp41"; +- marvell,function = "gpio"; +- }; +- +- scroll_button_pin: scroll-button-pin { +- marvell,pins = "mpp42"; +- marvell,function = "gpio"; +- }; +- +- hdd_led_pin: hdd-led-pin { +- marvell,pins = "mpp26"; +- marvell,function = "gpio"; +- }; +- }; +- + serial@12000 { + status = "okay"; + }; +@@ -282,3 +251,34 @@ + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + }; ++ ++&pinctrl { ++ poweroff_pin: poweroff-pin { ++ marvell,pins = "mpp24"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_button_pin: power-button-pin { ++ marvell,pins = "mpp44"; ++ marvell,function = "gpio"; ++ }; ++ ++ reset_button_pin: reset-button-pin { ++ marvell,pins = "mpp45"; ++ marvell,function = "gpio"; ++ }; ++ select_button_pin: select-button-pin { ++ marvell,pins = "mpp41"; ++ marvell,function = "gpio"; ++ }; ++ ++ scroll_button_pin: scroll-button-pin { ++ marvell,pins = "mpp42"; ++ marvell,function = "gpio"; ++ }; ++ ++ hdd_led_pin: hdd-led-pin { ++ marvell,pins = "mpp26"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -167,10 +167,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- compatible = "marvell,mv78230-pinctrl"; +- }; +- + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; +@@ -195,3 +191,7 @@ + }; + }; + }; ++ ++&pinctrl { ++ compatible = "marvell,mv78230-pinctrl"; ++}; +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -251,10 +251,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- compatible = "marvell,mv78260-pinctrl"; +- }; +- + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; +@@ -298,3 +294,7 @@ + }; + }; + }; ++ ++&pinctrl { ++ compatible = "marvell,mv78260-pinctrl"; ++}; +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -289,10 +289,6 @@ + }; + + internal-regs { +- pinctrl: pin-ctrl@18000 { +- compatible = "marvell,mv78460-pinctrl"; +- }; +- + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; +@@ -336,3 +332,7 @@ + }; + }; + }; ++ ++&pinctrl { ++ compatible = "marvell,mv78460-pinctrl"; ++}; +--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts ++++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +@@ -81,12 +81,7 @@ + serial@12100 { + status = "okay"; + }; +- pinctrl: pin-ctrl@18000 { +- led_pins: led-pins-0 { +- marvell,pins = "mpp49", "mpp51", "mpp53"; +- marvell,function = "gpio"; +- }; +- }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -191,3 +186,10 @@ + }; + }; + }; ++ ++&pinctrl { ++ led_pins: led-pins-0 { ++ marvell,pins = "mpp49", "mpp51", "mpp53"; ++ marvell,function = "gpio"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/012-move_ge_pinctrl_settings_for_rgmii.patch b/target/linux/mvebu/patches-3.18/012-move_ge_pinctrl_settings_for_rgmii.patch new file mode 100644 index 0000000..0aadd89 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/012-move_ge_pinctrl_settings_for_rgmii.patch @@ -0,0 +1,81 @@ +From e59451432d7e0f7953e29c15e70111dfdbecc145 Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:24:34 +0200 +Subject: ARM: mvebu: armada-xp: Move GE0/1 pinctrl settings for RGMII + +Pinctrl settings for GE0 and GE1 are not only usable on RD-AXPWiFiAP. +Moreover, naming the RGMII settings pmx-ge{0,1} is not precise enough +as there is also a GMII setting for GE0. + +Move the pinctrl sub-nodes to the common pinctrl node and rename them +to pmx-ge{0,1}-rgmii. + +Signed-off-by: Sebastian Hesselbarth +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -84,14 +84,14 @@ + }; + + ethernet@70000 { +- pinctrl-0 = <&pmx_ge0>; ++ pinctrl-0 = <&pmx_ge0_rgmii>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { +- pinctrl-0 = <&pmx_ge1>; ++ pinctrl-0 = <&pmx_ge1_rgmii>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; +@@ -133,20 +133,6 @@ + pinctrl-0 = <&pmx_phy_int>; + pinctrl-names = "default"; + +- pmx_ge0: pmx-ge0 { +- marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11"; +- marvell,function = "ge0"; +- }; +- +- pmx_ge1: pmx-ge1 { +- marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge1"; +- }; +- + pmx_keys: pmx-keys { + marvell,pins = "mpp33"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -75,6 +75,22 @@ + pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + ++ pmx_ge0_rgmii: pmx-ge0-rgmii { ++ marvell,pins = ++ "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11"; ++ marvell,function = "ge0"; ++ }; ++ ++ pmx_ge1_rgmii: pmx-ge1-rgmii { ++ marvell,pins = ++ "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge1"; ++ }; ++ + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; diff --git a/target/linux/mvebu/patches-3.18/013-add_ge0_pinctrl_settings_for_gmii.patch b/target/linux/mvebu/patches-3.18/013-add_ge0_pinctrl_settings_for_gmii.patch new file mode 100644 index 0000000..37bdae6 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/013-add_ge0_pinctrl_settings_for_gmii.patch @@ -0,0 +1,31 @@ +From 7254f6c52b5da38c0a79ab953d34e556fe16942f Mon Sep 17 00:00:00 2001 +From: Sebastian Hesselbarth +Date: Fri, 19 Sep 2014 21:27:55 +0200 +Subject: ARM: mvebu: armada-xp: Add GE0 pinctrl settings for GMII + +There is a GMII setting for GE0, add it to the common pinctrl node. + +Signed-off-by: Sebastian Hesselbarth +Tested-By: Benoit Masson +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -75,6 +75,17 @@ + pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + ++ pmx_ge0_gmii: pmx-ge0-gmii { ++ marvell,pins = ++ "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11", ++ "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge0"; ++ }; ++ + pmx_ge0_rgmii: pmx-ge0-rgmii { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", diff --git a/target/linux/mvebu/patches-3.18/014-add_uartx_labels.patch b/target/linux/mvebu/patches-3.18/014-add_uartx_labels.patch new file mode 100644 index 0000000..acd6ecc --- /dev/null +++ b/target/linux/mvebu/patches-3.18/014-add_uartx_labels.patch @@ -0,0 +1,58 @@ +From 181d9b28cbc9ae10e1467e2d013033b672d91d4b Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 00:45:35 +0100 +Subject: arm: mvebu: add uartX labels for Armada SoC serial nodes + +This patch adds uartX labels for Armada SoC serial nodes. This is +a preliminary work to be able to easily reference the serial lines +in Device Tree files. One expected use is when providing stdout-path +property for barebox. + +Reviewed-by: Thomas Petazzoni +Acked-by: Andrew Lunn +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/0683d1a823fe9b75849f3dafcf1cf6ee291cdca6.1416613429.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -151,7 +151,7 @@ + status = "disabled"; + }; + +- serial@12000 { ++ uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; +@@ -160,7 +160,8 @@ + clocks = <&coreclk 0>; + status = "disabled"; + }; +- serial@12100 { ++ ++ uart1: serial@12100 { + compatible = "snps,dw-apb-uart"; + reg = <0x12100 0x100>; + reg-shift = <2>; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -53,7 +53,7 @@ + reg = <0x11100 0x100>; + }; + +- serial@12200 { ++ uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; + reg = <0x12200 0x100>; + reg-shift = <2>; +@@ -62,7 +62,8 @@ + clocks = <&coreclk 0>; + status = "disabled"; + }; +- serial@12300 { ++ ++ uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; + reg = <0x12300 0x100>; + reg-shift = <2>; diff --git a/target/linux/mvebu/patches-3.18/015-move_armada_370_xp_pinctrl_node_definition.patch b/target/linux/mvebu/patches-3.18/015-move_armada_370_xp_pinctrl_node_definition.patch new file mode 100644 index 0000000..ed36d68 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/015-move_armada_370_xp_pinctrl_node_definition.patch @@ -0,0 +1,538 @@ +From 4904a82a9399d037588162e6fb4b293fa6a37f7c Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 00:45:56 +0100 +Subject: arm: mvebu: move Armada 370/XP pinctrl node definition + armada-370-xp.dtsi + +What was done by Sebastian in 264a05e19bf5 ("ARM: mvebu: armada-xp: +Add node alias to pinctrl and add base address") and 01c434225ee6 +("ARM: mvebu: armada-xp: Use pinctrl node alias") can also be done for +Armada 370, i.e. + + - Rename Armada 370 pinctrl node to pin-ctrl with its address encoded + - Add a node alias to access the pinctrl node easily. + - use the newly available alias in existing Armada 370 .dts files + +We can even go a bit further by putting the pinctrl node definition in +armada-370-xp.dtsi, with only its reg property defined. This allows us +to then also use the newly defined node alias in armada-xp.dtsi, +armada-370.dtsi. + +Suggested-by: Sebastian Hesselbarth +Suggested-by: Andrew Lunn +Acked-by: Andrew Lunn +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/b54eb45e5242728aace3ce8aef2eae4251f8dea3.1416613429.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-370-db.dts ++++ b/arch/arm/boot/dts/armada-370-db.dts +@@ -157,3 +157,27 @@ + compatible = "linux,spdif-dir"; + }; + }; ++ ++&pinctrl { ++ /* ++ * These pins might be muxed as I2S by ++ * the bootloader, but it conflicts ++ * with the real I2S pins that are ++ * muxed using i2s_pins. We must mux ++ * those pins to a function other than ++ * I2S. ++ */ ++ pinctrl-0 = <&hog_pins1 &hog_pins2>; ++ pinctrl-names = "default"; ++ ++ hog_pins1: hog-pins1 { ++ marvell,pins = "mpp6", "mpp8", "mpp10", ++ "mpp12", "mpp13"; ++ marvell,function = "gpio"; ++ }; ++ ++ hog_pins2: hog-pins2 { ++ marvell,pins = "mpp5", "mpp7", "mpp9"; ++ marvell,function = "gpo"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-370-mirabox.dts ++++ b/arch/arm/boot/dts/armada-370-mirabox.dts +@@ -54,18 +54,6 @@ + status = "okay"; + }; + +- pinctrl { +- pwr_led_pin: pwr-led-pin { +- marvell,pins = "mpp63"; +- marvell,function = "gpo"; +- }; +- +- stat_led_pins: stat-led-pins { +- marvell,pins = "mpp64", "mpp65"; +- marvell,function = "gpio"; +- }; +- }; +- + gpio_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -169,3 +157,16 @@ + }; + }; + }; ++ ++&pinctrl { ++ pwr_led_pin: pwr-led-pin { ++ marvell,pins = "mpp63"; ++ marvell,function = "gpo"; ++ }; ++ ++ stat_led_pins: stat-led-pins { ++ marvell,pins = "mpp64", "mpp65"; ++ marvell,function = "gpio"; ++ }; ++}; ++ +--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts ++++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts +@@ -58,48 +58,6 @@ + status = "okay"; + }; + +- pinctrl { +- power_led_pin: power-led-pin { +- marvell,pins = "mpp57"; +- marvell,function = "gpio"; +- }; +- +- sata1_led_pin: sata1-led-pin { +- marvell,pins = "mpp15"; +- marvell,function = "gpio"; +- }; +- +- sata2_led_pin: sata2-led-pin { +- marvell,pins = "mpp14"; +- marvell,function = "gpio"; +- }; +- +- backup_led_pin: backup-led-pin { +- marvell,pins = "mpp56"; +- marvell,function = "gpio"; +- }; +- +- backup_button_pin: backup-button-pin { +- marvell,pins = "mpp58"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp62"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp6"; +- marvell,function = "gpio"; +- }; +- +- poweroff: poweroff { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- }; +- + mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +@@ -256,3 +214,45 @@ + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + }; ++ ++&pinctrl { ++ power_led_pin: power-led-pin { ++ marvell,pins = "mpp57"; ++ marvell,function = "gpio"; ++ }; ++ ++ sata1_led_pin: sata1-led-pin { ++ marvell,pins = "mpp15"; ++ marvell,function = "gpio"; ++ }; ++ ++ sata2_led_pin: sata2-led-pin { ++ marvell,pins = "mpp14"; ++ marvell,function = "gpio"; ++ }; ++ ++ backup_led_pin: backup-led-pin { ++ marvell,pins = "mpp56"; ++ marvell,function = "gpio"; ++ }; ++ ++ backup_button_pin: backup-button-pin { ++ marvell,pins = "mpp58"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_button_pin: power-button-pin { ++ marvell,pins = "mpp62"; ++ marvell,function = "gpio"; ++ }; ++ ++ reset_button_pin: reset-button-pin { ++ marvell,pins = "mpp6"; ++ marvell,function = "gpio"; ++ }; ++ ++ poweroff: poweroff { ++ marvell,pins = "mpp8"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts ++++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts +@@ -53,38 +53,6 @@ + status = "okay"; + }; + +- pinctrl { +- poweroff: poweroff { +- marvell,pins = "mpp60"; +- marvell,function = "gpio"; +- }; +- +- backup_button_pin: backup-button-pin { +- marvell,pins = "mpp52"; +- marvell,function = "gpio"; +- }; +- +- power_button_pin: power-button-pin { +- marvell,pins = "mpp62"; +- marvell,function = "gpio"; +- }; +- +- backup_led_pin: backup-led-pin { +- marvell,pins = "mpp63"; +- marvell,function = "gpo"; +- }; +- +- power_led_pin: power-led-pin { +- marvell,pins = "mpp64"; +- marvell,function = "gpio"; +- }; +- +- reset_button_pin: reset-button-pin { +- marvell,pins = "mpp65"; +- marvell,function = "gpio"; +- }; +- }; +- + mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; +@@ -269,3 +237,35 @@ + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + }; + }; ++ ++&pinctrl { ++ poweroff: poweroff { ++ marvell,pins = "mpp60"; ++ marvell,function = "gpio"; ++ }; ++ ++ backup_button_pin: backup-button-pin { ++ marvell,pins = "mpp52"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_button_pin: power-button-pin { ++ marvell,pins = "mpp62"; ++ marvell,function = "gpio"; ++ }; ++ ++ backup_led_pin: backup-led-pin { ++ marvell,pins = "mpp63"; ++ marvell,function = "gpo"; ++ }; ++ ++ power_led_pin: power-led-pin { ++ marvell,pins = "mpp64"; ++ marvell,function = "gpio"; ++ }; ++ ++ reset_button_pin: reset-button-pin { ++ marvell,pins = "mpp65"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-370-rd.dts ++++ b/arch/arm/boot/dts/armada-370-rd.dts +@@ -59,18 +59,6 @@ + }; + + internal-regs { +- pinctrl { +- fan_pins: fan-pins { +- marvell,pins = "mpp8"; +- marvell,function = "gpio"; +- }; +- +- led_pins: led-pins { +- marvell,pins = "mpp32"; +- marvell,function = "gpio"; +- }; +- }; +- + serial@12000 { + status = "okay"; + }; +@@ -174,3 +162,15 @@ + }; + }; + }; ++ ++&pinctrl { ++ fan_pins: fan-pins { ++ marvell,pins = "mpp8"; ++ marvell,function = "gpio"; ++ }; ++ ++ led_pins: led-pins { ++ marvell,pins = "mpp32"; ++ marvell,function = "gpio"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -171,6 +171,10 @@ + status = "disabled"; + }; + ++ pinctrl: pin-ctrl@18000 { ++ reg = <0x18000 0x38>; ++ }; ++ + coredivclk: corediv-clock@18740 { + compatible = "marvell,armada-370-corediv-clock"; + reg = <0x18740 0xc>; +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -107,67 +107,6 @@ + reg = <0x11100 0x20>; + }; + +- pinctrl { +- compatible = "marvell,mv88f6710-pinctrl"; +- reg = <0x18000 0x38>; +- +- sdio_pins1: sdio-pins1 { +- marvell,pins = "mpp9", "mpp11", "mpp12", +- "mpp13", "mpp14", "mpp15"; +- marvell,function = "sd0"; +- }; +- +- sdio_pins2: sdio-pins2 { +- marvell,pins = "mpp47", "mpp48", "mpp49", +- "mpp50", "mpp51", "mpp52"; +- marvell,function = "sd0"; +- }; +- +- sdio_pins3: sdio-pins3 { +- marvell,pins = "mpp48", "mpp49", "mpp50", +- "mpp51", "mpp52", "mpp53"; +- marvell,function = "sd0"; +- }; +- +- i2c0_pins: i2c0-pins { +- marvell,pins = "mpp2", "mpp3"; +- marvell,function = "i2c0"; +- }; +- +- i2s_pins1: i2s-pins1 { +- marvell,pins = "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", +- "mpp12", "mpp13"; +- marvell,function = "audio"; +- }; +- +- i2s_pins2: i2s-pins2 { +- marvell,pins = "mpp49", "mpp47", "mpp50", +- "mpp59", "mpp57", "mpp61", +- "mpp62", "mpp60", "mpp58"; +- marvell,function = "audio"; +- }; +- +- mdio_pins: mdio-pins { +- marvell,pins = "mpp17", "mpp18"; +- marvell,function = "ge"; +- }; +- +- ge0_rgmii_pins: ge0-rgmii-pins { +- marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", +- "mpp9", "mpp10", "mpp11", "mpp12", +- "mpp13", "mpp14", "mpp15", "mpp16"; +- marvell,function = "ge0"; +- }; +- +- ge1_rgmii_pins: ge1-rgmii-pins { +- marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", +- "mpp23", "mpp24", "mpp25", "mpp26", +- "mpp27", "mpp28", "mpp29", "mpp30"; +- marvell,function = "ge1"; +- }; +- }; +- + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; +@@ -314,3 +253,63 @@ + }; + }; + }; ++ ++&pinctrl { ++ compatible = "marvell,mv88f6710-pinctrl"; ++ ++ sdio_pins1: sdio-pins1 { ++ marvell,pins = "mpp9", "mpp11", "mpp12", ++ "mpp13", "mpp14", "mpp15"; ++ marvell,function = "sd0"; ++ }; ++ ++ sdio_pins2: sdio-pins2 { ++ marvell,pins = "mpp47", "mpp48", "mpp49", ++ "mpp50", "mpp51", "mpp52"; ++ marvell,function = "sd0"; ++ }; ++ ++ sdio_pins3: sdio-pins3 { ++ marvell,pins = "mpp48", "mpp49", "mpp50", ++ "mpp51", "mpp52", "mpp53"; ++ marvell,function = "sd0"; ++ }; ++ ++ i2c0_pins: i2c0-pins { ++ marvell,pins = "mpp2", "mpp3"; ++ marvell,function = "i2c0"; ++ }; ++ ++ i2s_pins1: i2s-pins1 { ++ marvell,pins = "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", ++ "mpp12", "mpp13"; ++ marvell,function = "audio"; ++ }; ++ ++ i2s_pins2: i2s-pins2 { ++ marvell,pins = "mpp49", "mpp47", "mpp50", ++ "mpp59", "mpp57", "mpp61", ++ "mpp62", "mpp60", "mpp58"; ++ marvell,function = "audio"; ++ }; ++ ++ mdio_pins: mdio-pins { ++ marvell,pins = "mpp17", "mpp18"; ++ marvell,function = "ge"; ++ }; ++ ++ ge0_rgmii_pins: ge0-rgmii-pins { ++ marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", ++ "mpp9", "mpp10", "mpp11", "mpp12", ++ "mpp13", "mpp14", "mpp15", "mpp16"; ++ marvell,function = "ge0"; ++ }; ++ ++ ge1_rgmii_pins: ge1-rgmii-pins { ++ marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", ++ "mpp23", "mpp24", "mpp25", "mpp26", ++ "mpp27", "mpp28", "mpp29", "mpp30"; ++ marvell,function = "ge1"; ++ }; ++}; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -73,43 +73,6 @@ + status = "disabled"; + }; + +- pinctrl: pin-ctrl@18000 { +- reg = <0x18000 0x38>; +- +- pmx_ge0_gmii: pmx-ge0-gmii { +- marvell,pins = +- "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11", +- "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge0"; +- }; +- +- pmx_ge0_rgmii: pmx-ge0-rgmii { +- marvell,pins = +- "mpp0", "mpp1", "mpp2", "mpp3", +- "mpp4", "mpp5", "mpp6", "mpp7", +- "mpp8", "mpp9", "mpp10", "mpp11"; +- marvell,function = "ge0"; +- }; +- +- pmx_ge1_rgmii: pmx-ge1-rgmii { +- marvell,pins = +- "mpp12", "mpp13", "mpp14", "mpp15", +- "mpp16", "mpp17", "mpp18", "mpp19", +- "mpp20", "mpp21", "mpp22", "mpp23"; +- marvell,function = "ge1"; +- }; +- +- sdio_pins: sdio-pins { +- marvell,pins = "mpp30", "mpp31", "mpp32", +- "mpp33", "mpp34", "mpp35"; +- marvell,function = "sd0"; +- }; +- }; +- + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; +@@ -246,3 +209,38 @@ + }; + }; + }; ++ ++&pinctrl { ++ pmx_ge0_gmii: pmx-ge0-gmii { ++ marvell,pins = ++ "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11", ++ "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge0"; ++ }; ++ ++ pmx_ge0_rgmii: pmx-ge0-rgmii { ++ marvell,pins = ++ "mpp0", "mpp1", "mpp2", "mpp3", ++ "mpp4", "mpp5", "mpp6", "mpp7", ++ "mpp8", "mpp9", "mpp10", "mpp11"; ++ marvell,function = "ge0"; ++ }; ++ ++ pmx_ge1_rgmii: pmx-ge1-rgmii { ++ marvell,pins = ++ "mpp12", "mpp13", "mpp14", "mpp15", ++ "mpp16", "mpp17", "mpp18", "mpp19", ++ "mpp20", "mpp21", "mpp22", "mpp23"; ++ marvell,function = "ge1"; ++ }; ++ ++ sdio_pins: sdio-pins { ++ marvell,pins = "mpp30", "mpp31", "mpp32", ++ "mpp33", "mpp34", "mpp35"; ++ marvell,function = "sd0"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/016-common_armada_xp_uart2_3_pinctrl.patch b/target/linux/mvebu/patches-3.18/016-common_armada_xp_uart2_3_pinctrl.patch new file mode 100644 index 0000000..4cccdb3 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/016-common_armada_xp_uart2_3_pinctrl.patch @@ -0,0 +1,52 @@ +From d352f41e87e7226692d1346bb97c603615eeb817 Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 00:46:28 +0100 +Subject: arm: mvebu: define and use common Armada XP UART2/3 pinctrl settings + +This patch defines common Armada XP pinctrl settings for uart2 and +uart3 interfaces (uart0 and uart1 rx/tx do not rely on MPP): + + uart2: MPP42-43 as default + uart3: MPP44-45 as default + +Suggested-by: Andrew Lunn +Acked-by: Andrew Lunn +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/fd51c080c7139a67ec01df8d797f1e88ce557796.1416613429.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -55,6 +55,8 @@ + + uart2: serial@12200 { + compatible = "snps,dw-apb-uart"; ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; + reg = <0x12200 0x100>; + reg-shift = <2>; + interrupts = <43>; +@@ -65,6 +67,8 @@ + + uart3: serial@12300 { + compatible = "snps,dw-apb-uart"; ++ pinctrl-0 = <&uart3_pins>; ++ pinctrl-names = "default"; + reg = <0x12300 0x100>; + reg-shift = <2>; + interrupts = <44>; +@@ -243,4 +247,14 @@ + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; ++ ++ uart2_pins: uart2-pins { ++ marvell,pins = "mpp42", "mpp43"; ++ marvell,function = "uart2"; ++ }; ++ ++ uart3_pins: uart3-pins { ++ marvell,pins = "mpp44", "mpp45"; ++ marvell,function = "uart3"; ++ }; + }; diff --git a/target/linux/mvebu/patches-3.18/017-define_and_use_common_armada_xp_spi_pinctrl_setting.patch b/target/linux/mvebu/patches-3.18/017-define_and_use_common_armada_xp_spi_pinctrl_setting.patch new file mode 100644 index 0000000..9085db0 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/017-define_and_use_common_armada_xp_spi_pinctrl_setting.patch @@ -0,0 +1,69 @@ +From 547c653b64022618250ca9c7c30151927509ae98 Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 00:46:39 +0100 +Subject: arm: mvebu: define and use common Armada XP SPI pinctrl setting + +This patch defines common Armada XP pinctrl settings in armada-xp.dtsi +for the supported SPI interface (MPP36-39) and use it as default +for Armada XP spi interface. That being done, it removes the now +redundant definitions in armada-xp-axpwifiap.dts. + +Note: this patch has the potential to break out-of-tree users w/o +specific pinctrl settings for their spi interfaces if the default +above does not match their config (i.e. if they do not use CS0). + +Acked-by: Andrew Lunn +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/d404b7abd80ee5a0fd8e8d3586d33cd37740d589.1416613429.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -100,8 +100,6 @@ + + spi0: spi@10600 { + status = "okay"; +- pinctrl-0 = <&pmx_spi>; +- pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; +@@ -138,11 +136,6 @@ + marvell,function = "gpio"; + }; + +- pmx_spi: pmx-spi { +- marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; +- marvell,function = "spi"; +- }; +- + pmx_phy_int: pmx-phy-int { + marvell,pins = "mpp32"; + marvell,function = "gpio"; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -43,6 +43,11 @@ + wt-override; + }; + ++ spi0: spi@10600 { ++ pinctrl-0 = <&spi0_pins>; ++ pinctrl-names = "default"; ++ }; ++ + i2c0: i2c@11000 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; +@@ -248,6 +253,12 @@ + marvell,function = "sd0"; + }; + ++ spi0_pins: spi0-pins { ++ marvell,pins = "mpp36", "mpp37", ++ "mpp38", "mpp39"; ++ marvell,function = "spi"; ++ }; ++ + uart2_pins: uart2-pins { + marvell,pins = "mpp42", "mpp43"; + marvell,function = "uart2"; diff --git a/target/linux/mvebu/patches-3.18/018-normalize_pinctrl_entries_for_armada_socs.patch b/target/linux/mvebu/patches-3.18/018-normalize_pinctrl_entries_for_armada_socs.patch new file mode 100644 index 0000000..ca7b13b --- /dev/null +++ b/target/linux/mvebu/patches-3.18/018-normalize_pinctrl_entries_for_armada_socs.patch @@ -0,0 +1,98 @@ +From 70ee4e9d9f054e258480fd51c90cfc2b72be8b78 Mon Sep 17 00:00:00 2001 +From: Arnaud Ebalard +Date: Sat, 22 Nov 2014 17:23:30 +0100 +Subject: arm: mvebu: normalize pinctrl entries for Armada SoCs + +There are currently 2 differents naming conventions used between the +existing Armada SoC DT files for pinctrl entries (*_pin(s): *-pin(s) +and pmx_*: pmx-*) with a vast majority of files using the former: + +$ grep _pin arch/arm/boot/dts/armada-*.dts* | wc -l +155 +$ grep pmx arch/arm/boot/dts/armada-*.dts* | wc -l +13 + +In fact, only some Armada XP files are using the second variant. +This patch normalizes those files (mainly ge0/1 entries) to use +the first variant. + +Signed-off-by: Arnaud Ebalard +Link: https://lkml.kernel.org/r/00114c3169e1d93259ff4150ed46ee36eae16b1e.1416670812.git.arno@natisbad.org +Signed-off-by: Jason Cooper + +--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts ++++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts +@@ -84,14 +84,14 @@ + }; + + ethernet@70000 { +- pinctrl-0 = <&pmx_ge0_rgmii>; ++ pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + ethernet@74000 { +- pinctrl-0 = <&pmx_ge1_rgmii>; ++ pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy1>; +@@ -116,7 +116,7 @@ + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; +- pinctrl-0 = <&pmx_keys>; ++ pinctrl-0 = <&keys_pin>; + pinctrl-names = "default"; + + button@1 { +@@ -128,15 +128,15 @@ + }; + + &pinctrl { +- pinctrl-0 = <&pmx_phy_int>; ++ pinctrl-0 = <&phy_int_pin>; + pinctrl-names = "default"; + +- pmx_keys: pmx-keys { ++ keys_pin: keys-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + +- pmx_phy_int: pmx-phy-int { ++ phy_int_pin: phy-int-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -220,7 +220,7 @@ + }; + + &pinctrl { +- pmx_ge0_gmii: pmx-ge0-gmii { ++ ge0_gmii_pins: ge0-gmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", +@@ -231,7 +231,7 @@ + marvell,function = "ge0"; + }; + +- pmx_ge0_rgmii: pmx-ge0-rgmii { ++ ge0_rgmii_pins: ge0-rgmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", +@@ -239,7 +239,7 @@ + marvell,function = "ge0"; + }; + +- pmx_ge1_rgmii: pmx-ge1-rgmii { ++ ge1_rgmii_pins: ge1-rgmii-pins { + marvell,pins = + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", diff --git a/target/linux/mvebu/patches-3.18/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch b/target/linux/mvebu/patches-3.18/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch new file mode 100644 index 0000000..551d5bf --- /dev/null +++ b/target/linux/mvebu/patches-3.18/020-ARM-mvebu-Add-a-number-of-pinctrl-functions.patch @@ -0,0 +1,65 @@ +From 91b4c91f919abffa72cbf7545a944252f8e4f775 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 8 Jan 2015 18:38:08 +0100 +Subject: [PATCH 3/4] ARM: mvebu: Add a number of pinctrl functions + +Some pinctrl functions can be shared with all DTS out there, since they are +generic, SoC-wide muxing options. Add a number of these to the DTSI to avoid +duplication. + +Signed-off-by: Maxime Ripard +Acked-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-38x.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -196,6 +196,45 @@ + pinctrl { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; ++ ++ ge0_rgmii_pins: ge-rgmii-pins-0 { ++ marvell,pins = "mpp6", "mpp7", "mpp8", ++ "mpp9", "mpp10", "mpp11", ++ "mpp12", "mpp13", "mpp14", ++ "mpp15", "mpp16", "mpp17"; ++ marvell,function = "ge0"; ++ }; ++ ++ i2c0_pins: i2c-pins-0 { ++ marvell,pins = "mpp2", "mpp3"; ++ marvell,function = "i2c0"; ++ }; ++ ++ mdio_pins: mdio-pins { ++ marvell,pins = "mpp4", "mpp5"; ++ marvell,function = "ge"; ++ }; ++ ++ ref_clk0_pins: ref-clk-pins-0 { ++ marvell,pins = "mpp45"; ++ marvell,function = "ref"; ++ }; ++ ++ spi1_pins: spi-pins-1 { ++ marvell,pins = "mpp56", "mpp57", "mpp58", ++ "mpp59"; ++ marvell,function = "spi1"; ++ }; ++ ++ uart0_pins: uart-pins-0 { ++ marvell,pins = "mpp0", "mpp1"; ++ marvell,function = "ua0"; ++ }; ++ ++ uart1_pins: uart-pins-1 { ++ marvell,pins = "mpp19", "mpp20"; ++ marvell,function = "ua1"; ++ }; + }; + + gpio0: gpio@18100 { diff --git a/target/linux/mvebu/patches-3.18/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch b/target/linux/mvebu/patches-3.18/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch new file mode 100644 index 0000000..cc9311b --- /dev/null +++ b/target/linux/mvebu/patches-3.18/021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch @@ -0,0 +1,212 @@ +From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 8 Jan 2015 18:38:09 +0100 +Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board + support + +The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB +SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage. + +[gregory.clement@free-electrons.com: switch the license to the dual +X11/GPL with the agreement of the author] + +Signed-off-by: Maxime Ripard +Signed-off-by: Gregory CLEMENT +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++ + 2 files changed, 179 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -500,6 +500,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb + dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db.dtb \ ++ armada-385-db-ap.dtb \ + armada-385-rd.dtb + dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -0,0 +1,178 @@ ++/* ++ * Device Tree file for Marvell Armada 385 Access Point Development board ++ * (DB-88F6820-AP) ++ * ++ * Copyright (C) 2014 Marvell ++ * ++ * Nadav Haklai ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without ++ * any warranty of any kind, whether express or implied. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "armada-385.dtsi" ++ ++#include ++ ++/ { ++ model = "Marvell Armada 385 Access Point Development Board"; ++ compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ stdout-path = &uart1; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x80000000>; /* 2GB */ ++ }; ++ ++ soc { ++ ranges = ; ++ ++ internal-regs { ++ spi1: spi@10680 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>; ++ status = "okay"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,m25p128"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <54000000>; ++ }; ++ }; ++ ++ i2c0: i2c@11000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++ ++ /* ++ * This bus is wired to two EEPROM ++ * sockets, one of which holding the ++ * board ID used by the bootloader. ++ * Erasing this EEPROM's content will ++ * brick the board. ++ * Use this bus with caution. ++ */ ++ }; ++ ++ mdio@72004 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mdio_pins>; ++ ++ phy0: ethernet-phy@1 { ++ reg = <1>; ++ }; ++ ++ phy1: ethernet-phy@4 { ++ reg = <4>; ++ }; ++ ++ phy2: ethernet-phy@6 { ++ reg = <6>; ++ }; ++ }; ++ ++ /* UART0 is exposed through the JP8 connector */ ++ uart0: serial@12000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++ status = "okay"; ++ }; ++ ++ /* ++ * UART1 is exposed through a FTDI chip ++ * wired to the mini-USB connector ++ */ ++ uart1: serial@12100 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ ++ ethernet@30000 { ++ status = "okay"; ++ phy = <&phy2>; ++ phy-mode = "sgmii"; ++ }; ++ ++ ethernet@34000 { ++ status = "okay"; ++ phy = <&phy1>; ++ phy-mode = "sgmii"; ++ }; ++ ++ ethernet@70000 { ++ pinctrl-names = "default"; ++ ++ /* ++ * The Reference Clock 0 is used to ++ * provide a clock to the PHY ++ */ ++ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; ++ status = "okay"; ++ phy = <&phy0>; ++ phy-mode = "rgmii-id"; ++ }; ++ }; ++ ++ pcie-controller { ++ status = "okay"; ++ ++ /* ++ * The three PCIe units are accessible through ++ * standard mini-PCIe slots on the board. ++ */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ pcie@2,0 { ++ /* Port 1, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ pcie@3,0 { ++ /* Port 2, Lane 0 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch b/target/linux/mvebu/patches-3.18/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch new file mode 100644 index 0000000..3c4a111 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch @@ -0,0 +1,34 @@ +From 7eb1f09ec8e25aa2fc3f6fc5fc9405d9f917d503 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 11 Dec 2014 14:14:58 +0100 +Subject: [PATCH 1/2] ARM: mvebu: A385-AP: Enable the NAND controller + +The A385 AP has a 1GB NAND chip. Enable it. + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -150,6 +150,19 @@ + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; ++ ++ nfc: flash@d0000 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ num-cs = <1>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ marvell,nand-keep-config; ++ marvell,nand-enable-arbiter; ++ nand-on-flash-bbt; ++ }; + }; + + pcie-controller { diff --git a/target/linux/mvebu/patches-3.18/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch b/target/linux/mvebu/patches-3.18/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch new file mode 100644 index 0000000..07f8e29 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/023-pinctrl-mvebu-a38x-Add-UART1-muxing-options.patch @@ -0,0 +1,37 @@ +From a95308d88c07e0093aedae7e64f92cb1e165f592 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Fri, 5 Dec 2014 15:44:57 +0100 +Subject: [PATCH] pinctrl: mvebu: a38x: Add UART1 muxing options + +The MPP19 and MMP20 pins also have the ability to be muxed to the uart1 +function. + +Add this case to the pinctrl driver. + +Signed-off-by: Maxime Ripard +Acked-by: Jason Cooper +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +@@ -146,13 +146,15 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), + MPP_MODE(20, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), + MPP_MODE(21, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS), diff --git a/target/linux/mvebu/patches-3.18/024-ARM-mvebu-a38x-Fix-node-names.patch b/target/linux/mvebu/patches-3.18/024-ARM-mvebu-a38x-Fix-node-names.patch new file mode 100644 index 0000000..37dd4c2 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/024-ARM-mvebu-a38x-Fix-node-names.patch @@ -0,0 +1,85 @@ +From 4a25432b13090b57d257fa0ffb6712d8acf94523 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 8 Jan 2015 18:38:05 +0100 +Subject: [PATCH 1/4] ARM: mvebu: a38x: Fix node names + +Some nodes in the DTs have a reg property but no unit name in their node name. + +This contradicts the way the ePAPR defines the node names. Fix this. + +Signed-off-by: Maxime Ripard +Acked-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-380.dtsi | 2 +- + arch/arm/boot/dts/armada-385-db.dts | 2 +- + arch/arm/boot/dts/armada-385-rd.dts | 2 +- + arch/arm/boot/dts/armada-385.dtsi | 2 +- + arch/arm/boot/dts/armada-38x.dtsi | 4 ++-- + 5 files changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm/boot/dts/armada-380.dtsi ++++ b/arch/arm/boot/dts/armada-380.dtsi +@@ -32,7 +32,7 @@ + + soc { + internal-regs { +- pinctrl { ++ pinctrl@18000 { + compatible = "marvell,mv88f6810-pinctrl"; + reg = <0x18000 0x20>; + }; +--- a/arch/arm/boot/dts/armada-385-db.dts ++++ b/arch/arm/boot/dts/armada-385-db.dts +@@ -74,7 +74,7 @@ + phy-mode = "rgmii-id"; + }; + +- mdio { ++ mdio@72004 { + phy0: ethernet-phy@0 { + reg = <0>; + }; +--- a/arch/arm/boot/dts/armada-385-rd.dts ++++ b/arch/arm/boot/dts/armada-385-rd.dts +@@ -67,7 +67,7 @@ + }; + + +- mdio { ++ mdio@72004 { + phy0: ethernet-phy@0 { + reg = <0>; + }; +--- a/arch/arm/boot/dts/armada-385.dtsi ++++ b/arch/arm/boot/dts/armada-385.dtsi +@@ -37,7 +37,7 @@ + + soc { + internal-regs { +- pinctrl { ++ pinctrl@18000 { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + }; +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -193,7 +193,7 @@ + status = "disabled"; + }; + +- pinctrl { ++ pinctrl@18000 { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + +@@ -412,7 +412,7 @@ + status = "disabled"; + }; + +- mdio { ++ mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; diff --git a/target/linux/mvebu/patches-3.18/025-ARM-mvebu-Use-arm_coherent_dma_ops.patch b/target/linux/mvebu/patches-3.18/025-ARM-mvebu-Use-arm_coherent_dma_ops.patch new file mode 100644 index 0000000..e3d1415 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/025-ARM-mvebu-Use-arm_coherent_dma_ops.patch @@ -0,0 +1,111 @@ +From 1bd4d8a6de5cda605e8b99fbf081be2ea2959380 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Fri, 16 Jan 2015 17:11:29 +0100 +Subject: ARM: mvebu: use arm_coherent_dma_ops and re-enable hardware I/O + coherency + +Now that we have enabled automatic I/O synchronization barriers, we no +longer need any explicit barriers. We can therefore simplify +arch/arm/mach-mvebu/coherency.c by using the existing +arm_coherent_dma_ops instead of our custom mvebu_hwcc_dma_ops, and +re-enable hardware I/O coherency support. + +Signed-off-by: Thomas Petazzoni +[Andrew Lunn : Remove forgotten comment] +Signed-off-by: Andrew Lunn + +--- a/arch/arm/mach-mvebu/coherency.c ++++ b/arch/arm/mach-mvebu/coherency.c +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + #include "armada-370-xp.h" + #include "coherency.h" + #include "mvebu-soc-id.h" +@@ -223,59 +224,6 @@ static void __init armada_375_coherency_ + coherency_wa_enabled = true; + } + +-static inline void mvebu_hwcc_sync_io_barrier(void) +-{ +- if (coherency_wa_enabled) { +- mvebu_hwcc_armada375_sync_io_barrier_wa(); +- return; +- } +- +- writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET); +- while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1); +-} +- +-static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page, +- unsigned long offset, size_t size, +- enum dma_data_direction dir, +- struct dma_attrs *attrs) +-{ +- if (dir != DMA_TO_DEVICE) +- mvebu_hwcc_sync_io_barrier(); +- return pfn_to_dma(dev, page_to_pfn(page)) + offset; +-} +- +- +-static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle, +- size_t size, enum dma_data_direction dir, +- struct dma_attrs *attrs) +-{ +- if (dir != DMA_TO_DEVICE) +- mvebu_hwcc_sync_io_barrier(); +-} +- +-static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle, +- size_t size, enum dma_data_direction dir) +-{ +- if (dir != DMA_TO_DEVICE) +- mvebu_hwcc_sync_io_barrier(); +-} +- +-static struct dma_map_ops mvebu_hwcc_dma_ops = { +- .alloc = arm_dma_alloc, +- .free = arm_dma_free, +- .mmap = arm_dma_mmap, +- .map_page = mvebu_hwcc_dma_map_page, +- .unmap_page = mvebu_hwcc_dma_unmap_page, +- .get_sgtable = arm_dma_get_sgtable, +- .map_sg = arm_dma_map_sg, +- .unmap_sg = arm_dma_unmap_sg, +- .sync_single_for_cpu = mvebu_hwcc_dma_sync, +- .sync_single_for_device = mvebu_hwcc_dma_sync, +- .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, +- .sync_sg_for_device = arm_dma_sync_sg_for_device, +- .set_dma_mask = arm_dma_set_mask, +-}; +- + static int mvebu_hwcc_notifier(struct notifier_block *nb, + unsigned long event, void *__dev) + { +@@ -283,7 +231,7 @@ static int mvebu_hwcc_notifier(struct no + + if (event != BUS_NOTIFY_ADD_DEVICE) + return NOTIFY_DONE; +- set_dma_ops(dev, &mvebu_hwcc_dma_ops); ++ set_dma_ops(dev, &arm_coherent_dma_ops); + + return NOTIFY_OK; + } +@@ -405,14 +353,9 @@ static int coherency_type(void) + return type; + } + +-/* +- * As a precaution, we currently completely disable hardware I/O +- * coherency, until enough testing is done with automatic I/O +- * synchronization barriers to validate that it is a proper solution. +- */ + int coherency_available(void) + { +- return false; ++ return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; + } + + int __init coherency_init(void) diff --git a/target/linux/mvebu/patches-3.18/050-leds_tlc59116_document_binding.patch b/target/linux/mvebu/patches-3.18/050-leds_tlc59116_document_binding.patch new file mode 100644 index 0000000..e55eca3 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/050-leds_tlc59116_document_binding.patch @@ -0,0 +1,51 @@ +Document the binding for the TLC59116 LED driver. + +Signed-off-by: Andrew Lunn +--- + .../devicetree/bindings/leds/leds-tlc59116.txt | 40 ++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + create mode 100644 Documentation/devicetree/bindings/leds/leds-tlc59116.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/leds/leds-tlc59116.txt +@@ -0,0 +1,40 @@ ++LEDs connected to tcl59116 ++ ++Required properties ++- compatible: should be "ti,tlc59116" ++- #address-cells: must be 1 ++- #size-cells: must be 0 ++- reg: typically 0x68 ++ ++Each led is represented as a sub-node of the ti,,tlc59116. ++See Documentation/devicetree/bindings/leds/common.txt ++ ++LED sub-node properties: ++- reg: number of LED line, 0 to 15 ++- label: (optional) name of LED ++- linux,default-trigger : (optional) ++ ++Examples: ++ ++tlc59116@68 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "ti,tlc59116"; ++ reg = <0x68>; ++ ++ wan@0 { ++ label = "wrt1900ac:amber:wan"; ++ reg = <0x0>; ++ }; ++ ++ 2g@2 { ++ label = "wrt1900ac:white:2g"; ++ reg = <0x2>; ++ }; ++ ++ alive@9 { ++ label = "wrt1900ac:green:alive"; ++ reg = <0x9>; ++ linux,default_trigger = "heartbeat"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-3.18/051-leds_tlc59116_add_driver.patch b/target/linux/mvebu/patches-3.18/051-leds_tlc59116_add_driver.patch new file mode 100644 index 0000000..fd22aef --- /dev/null +++ b/target/linux/mvebu/patches-3.18/051-leds_tlc59116_add_driver.patch @@ -0,0 +1,297 @@ +The TLC59116 is an I2C bus controlled 16-channel LED driver. Each LED +output has its own 8-bit fixed-frequency PWM controller to control the +brightness of the LED. + +This is based on a driver from Belkin, but has been extensively +rewritten. + +Signed-off-by: Andrew Lunn +--- + drivers/leds/Kconfig | 8 ++ + drivers/leds/Makefile | 1 + + drivers/leds/leds-tlc59116.c | 252 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 261 insertions(+) + create mode 100644 drivers/leds/leds-tlc59116.c + +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -446,6 +446,14 @@ config LEDS_TCA6507 + LED driver chips accessed via the I2C bus. + Driver support brightness control and hardware-assisted blinking. + ++config LEDS_TLC59116 ++ tristate "LED driver for TLC59116F controllers" ++ depends on LEDS_CLASS && I2C ++ select REGMAP_I2C ++ help ++ This option enables support for Texas Instruments TLC59116F ++ LED controller. ++ + config LEDS_MAX8997 + tristate "LED support for MAX8997 PMIC" + depends on LEDS_CLASS && MFD_MAX8997 +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -29,6 +29,7 @@ obj-$(CONFIG_LEDS_LP5562) += leds-lp556 + obj-$(CONFIG_LEDS_LP8501) += leds-lp8501.o + obj-$(CONFIG_LEDS_LP8788) += leds-lp8788.o + obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o ++obj-$(CONFIG_LEDS_TLC59116) += leds-tlc59116.o + obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o + obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o + obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o +--- /dev/null ++++ b/drivers/leds/leds-tlc59116.c +@@ -0,0 +1,252 @@ ++/* ++ * Copyright 2014 Belkin Inc. ++ * Copyright 2014 Andrew Lunn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TLC59116_LEDS 16 ++ ++#define TLC59116_REG_MODE1 0x00 ++#define MODE1_RESPON_ADDR_MASK 0xF0 ++#define MODE1_NORMAL_MODE (0 << 4) ++#define MODE1_SPEED_MODE (1 << 4) ++ ++#define TLC59116_REG_MODE2 0x01 ++#define MODE2_DIM (0 << 5) ++#define MODE2_BLINK (1 << 5) ++#define MODE2_OCH_STOP (0 << 3) ++#define MODE2_OCH_ACK (1 << 3) ++ ++#define TLC59116_REG_PWM(x) (0x02 + (x)) ++ ++#define TLC59116_REG_GRPPWM 0x12 ++#define TLC59116_REG_GRPFREQ 0x13 ++ ++/* LED Driver Output State, determine the source that drives LED outputs */ ++#define TLC59116_REG_LEDOUT(x) (0x14 + ((x) >> 2)) ++#define TLC59116_LED_OFF 0x0 /* Output LOW */ ++#define TLC59116_LED_ON 0x1 /* Output HI-Z */ ++#define TLC59116_DIM 0x2 /* Dimming */ ++#define TLC59116_BLINK 0x3 /* Blinking */ ++#define LED_MASK 0x3 ++ ++#define ldev_to_led(c) container_of(c, struct tlc59116_led, ldev) ++#define work_to_led(work) container_of(work, struct tlc59116_led, work) ++ ++struct tlc59116_led { ++ bool active; ++ struct regmap *regmap; ++ unsigned int led_no; ++ struct led_classdev ldev; ++ struct work_struct work; ++}; ++ ++struct tlc59116_priv { ++ struct tlc59116_led leds[TLC59116_LEDS]; ++}; ++ ++static int ++tlc59116_set_mode(struct regmap *regmap, u8 mode) ++{ ++ int err; ++ u8 val; ++ ++ if ((mode != MODE2_DIM) && (mode != MODE2_BLINK)) ++ mode = MODE2_DIM; ++ ++ /* Configure MODE1 register */ ++ err = regmap_write(regmap, TLC59116_REG_MODE1, MODE1_NORMAL_MODE); ++ if (err) ++ return err; ++ ++ /* Configure MODE2 Reg */ ++ val = MODE2_OCH_STOP | mode; ++ ++ return regmap_write(regmap, TLC59116_REG_MODE2, val); ++} ++ ++static int ++tlc59116_set_led(struct tlc59116_led *led, u8 val) ++{ ++ struct regmap *regmap = led->regmap; ++ unsigned int i = (led->led_no % 4) * 2; ++ unsigned int addr = TLC59116_REG_LEDOUT(led->led_no); ++ unsigned int mask = LED_MASK << i; ++ ++ val = val << i; ++ ++ return regmap_update_bits(regmap, addr, mask, val); ++} ++ ++static void ++tlc59116_led_work(struct work_struct *work) ++{ ++ struct tlc59116_led *led = work_to_led(work); ++ struct regmap *regmap = led->regmap; ++ int err; ++ u8 pwm; ++ ++ pwm = TLC59116_REG_PWM(led->led_no); ++ err = regmap_write(regmap, pwm, led->ldev.brightness); ++ if (err) ++ dev_err(led->ldev.dev, "Failed setting brightness\n"); ++} ++ ++static void ++tlc59116_led_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ struct tlc59116_led *led = ldev_to_led(led_cdev); ++ ++ led->ldev.brightness = value; ++ schedule_work(&led->work); ++} ++ ++static void ++tlc59116_destroy_devices(struct tlc59116_priv *priv, unsigned int i) ++{ ++ while (--i >= 0) { ++ if (priv->leds[i].active) { ++ led_classdev_unregister(&priv->leds[i].ldev); ++ cancel_work_sync(&priv->leds[i].work); ++ } ++ } ++} ++ ++static int ++tlc59116_configure(struct device *dev, ++ struct tlc59116_priv *priv, ++ struct regmap *regmap) ++{ ++ unsigned int i; ++ int err = 0; ++ ++ tlc59116_set_mode(regmap, MODE2_DIM); ++ for (i = 0; i < TLC59116_LEDS; i++) { ++ struct tlc59116_led *led = &priv->leds[i]; ++ ++ if (!led->active) ++ continue; ++ ++ led->regmap = regmap; ++ led->led_no = i; ++ led->ldev.brightness_set = tlc59116_led_set; ++ led->ldev.max_brightness = LED_FULL; ++ INIT_WORK(&led->work, tlc59116_led_work); ++ err = led_classdev_register(dev, &led->ldev); ++ if (err < 0) { ++ dev_err(dev, "couldn't register LED %s\n", ++ led->ldev.name); ++ goto exit; ++ } ++ tlc59116_set_led(led, TLC59116_DIM); ++ } ++ ++ return 0; ++ ++exit: ++ tlc59116_destroy_devices(priv, i); ++ return err; ++} ++ ++static const struct regmap_config tlc59116_regmap = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = 0x1e, ++}; ++ ++static int ++tlc59116_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct tlc59116_priv *priv = i2c_get_clientdata(client); ++ struct device *dev = &client->dev; ++ struct device_node *np = client->dev.of_node, *child; ++ struct regmap *regmap; ++ int err, count, reg; ++ ++ count = of_get_child_count(np); ++ if (!count || count > TLC59116_LEDS) ++ return -EINVAL; ++ ++ if (!i2c_check_functionality(client->adapter, ++ I2C_FUNC_SMBUS_BYTE_DATA)) ++ return -EIO; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ regmap = devm_regmap_init_i2c(client, &tlc59116_regmap); ++ if (IS_ERR(regmap)) { ++ err = PTR_ERR(regmap); ++ dev_err(dev, "Failed to allocate register map: %d\n", err); ++ return err; ++ } ++ ++ i2c_set_clientdata(client, priv); ++ ++ for_each_child_of_node(np, child) { ++ err = of_property_read_u32(child, "reg", ®); ++ if (err) ++ return err; ++ if (reg < 0 || reg >= TLC59116_LEDS) ++ return -EINVAL; ++ if (priv->leds[reg].active) ++ return -EINVAL; ++ priv->leds[reg].active = true; ++ priv->leds[reg].ldev.name = ++ of_get_property(child, "label", NULL) ? : child->name; ++ priv->leds[reg].ldev.default_trigger = ++ of_get_property(child, "linux,default-trigger", NULL); ++ } ++ return tlc59116_configure(dev, priv, regmap); ++} ++ ++static int ++tlc59116_remove(struct i2c_client *client) ++{ ++ struct tlc59116_priv *priv = i2c_get_clientdata(client); ++ ++ tlc59116_destroy_devices(priv, TLC59116_LEDS); ++ ++ return 0; ++} ++ ++static const struct of_device_id of_tlc59116_leds_match[] = { ++ { .compatible = "ti,tlc59116", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, of_tlc59116_leds_match); ++ ++static const struct i2c_device_id tlc59116_id[] = { ++ { "tlc59116" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(i2c, tlc59116_id); ++ ++static struct i2c_driver tlc59116_driver = { ++ .driver = { ++ .name = "tlc59116", ++ .of_match_table = of_match_ptr(of_tlc59116_leds_match), ++ }, ++ .probe = tlc59116_probe, ++ .remove = tlc59116_remove, ++ .id_table = tlc59116_id, ++}; ++ ++module_i2c_driver(tlc59116_driver); ++ ++MODULE_AUTHOR("Andrew Lunn "); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("TLC59116 LED driver"); diff --git a/target/linux/mvebu/patches-3.18/061-cpuidle-mvebu-Update-cpuidle-thresholds-for-Armada-X.patch b/target/linux/mvebu/patches-3.18/061-cpuidle-mvebu-Update-cpuidle-thresholds-for-Armada-X.patch new file mode 100644 index 0000000..bc0f1a6 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/061-cpuidle-mvebu-Update-cpuidle-thresholds-for-Armada-X.patch @@ -0,0 +1,66 @@ +From ce6031c89a35cffd5a5992b08377b77f49a004b9 Mon Sep 17 00:00:00 2001 +From: Sebastien Rannou +Date: Fri, 13 Feb 2015 15:55:03 +0100 +Subject: [PATCH] cpuidle: mvebu: Update cpuidle thresholds for Armada XP SOCs + +Originally, the thresholds used in the cpuidle driver for Armada SOCs +were temporarily chosen, leaving room for improvements. + +This commit updates the thresholds for the Armada XP SOCs with values +that positively impact performances: + + without patch with patch vendor kernel + - iperf localhost (gbit/sec) ~3.7 ~6.4 ~5.4 + - ioping tmpfs (iops) ~163k ~206k ~179k + - ioping tmpfs (mib/s) ~636 ~805 ~699 + +The idle power consumption is negatively impacted (proportionally less +than the performance gain), and we are still performing better than +the vendor kernel here: + + without patch with patch vendor kernel + - power consumption idle (W) ~2.4 ~3.2 ~4.4 + - power consumption busy (W) ~8.6 ~8.3 ~8.6 + +There is still room for improvement regarding the value of these +thresholds, they were chosen to mimic the vendor kernel. + +This patch only impacts Armada XP SOCs and was tested on Online Labs +C1 boards. A similar approach can be taken to improve the performances +of the Armada 370 and Armada 38x SOCs. + +Thanks a lot to Thomas Petazzoni, Gregory Clement and Willy Tarreau +for the discussions and tips around this topic. + +Signed-off-by: Sebastien Rannou +Signed-off-by: Daniel Lezcano +Acked-by: Gregory CLEMENT +--- + drivers/cpuidle/cpuidle-mvebu-v7.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/cpuidle/cpuidle-mvebu-v7.c ++++ b/drivers/cpuidle/cpuidle-mvebu-v7.c +@@ -50,18 +50,18 @@ static struct cpuidle_driver armadaxp_id + .states[0] = ARM_CPUIDLE_WFI_STATE, + .states[1] = { + .enter = mvebu_v7_enter_idle, +- .exit_latency = 10, ++ .exit_latency = 100, + .power_usage = 50, +- .target_residency = 100, ++ .target_residency = 1000, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "MV CPU IDLE", + .desc = "CPU power down", + }, + .states[2] = { + .enter = mvebu_v7_enter_idle, +- .exit_latency = 100, ++ .exit_latency = 1000, + .power_usage = 5, +- .target_residency = 1000, ++ .target_residency = 10000, + .flags = CPUIDLE_FLAG_TIME_VALID | + MVEBU_V7_FLAG_DEEP_IDLE, + .name = "MV CPU DEEP IDLE", diff --git a/target/linux/mvebu/patches-3.18/099-build_linksys_a385_dts.patch b/target/linux/mvebu/patches-3.18/099-build_linksys_a385_dts.patch new file mode 100644 index 0000000..efdd94c --- /dev/null +++ b/target/linux/mvebu/patches-3.18/099-build_linksys_a385_dts.patch @@ -0,0 +1,12 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -501,6 +501,9 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ + dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db.dtb \ + armada-385-db-ap.dtb \ ++ armada-385-linksys-caiman.dtb \ ++ armada-385-linksys-cobra.dtb \ ++ armada-385-linksys-shelby.dtb \ + armada-385-rd.dtb + dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-axpwifiap.dtb \ diff --git a/target/linux/mvebu/patches-3.18/100-find_active_root.patch b/target/linux/mvebu/patches-3.18/100-find_active_root.patch new file mode 100644 index 0000000..e32b608 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/100-find_active_root.patch @@ -0,0 +1,61 @@ +The WRT1900AC among other Linksys routers uses a dual-firmware layout. +Dynamically rename the active partition to "ubi". + +Signed-off-by: Imre Kaloz + +--- a/drivers/mtd/ofpart.c ++++ b/drivers/mtd/ofpart.c +@@ -25,12 +25,15 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static int mangled_rootblock; ++ + static int parse_ofpart_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) + { + struct device_node *node; + const char *partname; ++ const char *owrtpart = "ubi"; + struct device_node *pp; + int nr_parts, i; + +@@ -78,9 +81,15 @@ static int parse_ofpart_partitions(struc + (*pparts)[i].offset = of_read_number(reg, a_cells); + (*pparts)[i].size = of_read_number(reg + a_cells, s_cells); + +- partname = of_get_property(pp, "label", &len); +- if (!partname) +- partname = of_get_property(pp, "name", &len); ++ if (mangled_rootblock && (i == mangled_rootblock)) { ++ partname = owrtpart; ++ } else { ++ partname = of_get_property(pp, "label", &len); ++ ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ } ++ + (*pparts)[i].name = partname; + + if (of_get_property(pp, "read-only", &len)) +@@ -178,6 +187,18 @@ static int __init ofpart_parser_init(voi + return 0; + } + ++static int __init active_root(char *str) ++{ ++ get_option(&str, &mangled_rootblock); ++ ++ if (!mangled_rootblock) ++ return 1; ++ ++ return 1; ++} ++ ++__setup("mangled_rootblock=", active_root); ++ + static void __exit ofpart_parser_exit(void) + { + deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/mvebu/patches-3.18/102-revert_i2c_delay.patch b/target/linux/mvebu/patches-3.18/102-revert_i2c_delay.patch new file mode 100644 index 0000000..9089534 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/102-revert_i2c_delay.patch @@ -0,0 +1,15 @@ +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -49,12 +49,10 @@ + }; + + i2c0: i2c@11000 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; + }; + + i2c1: i2c@11100 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; + }; + diff --git a/target/linux/mvebu/patches-3.18/140-alias_mdio_node.patch b/target/linux/mvebu/patches-3.18/140-alias_mdio_node.patch new file mode 100644 index 0000000..818fae7 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/140-alias_mdio_node.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -236,7 +236,7 @@ + status = "disabled"; + }; + +- mdio { ++ mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; diff --git a/target/linux/mvebu/patches-3.18/150-use_the_cpufreq-dt_platform_data_for_independent_clocks.patch b/target/linux/mvebu/patches-3.18/150-use_the_cpufreq-dt_platform_data_for_independent_clocks.patch new file mode 100644 index 0000000..1fea44f --- /dev/null +++ b/target/linux/mvebu/patches-3.18/150-use_the_cpufreq-dt_platform_data_for_independent_clocks.patch @@ -0,0 +1,44 @@ +From 842f7d2c4d392c0571cf72e3eaca26742bebbd1e Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 2 Dec 2014 17:48:02 +0100 +Subject: ARM: mvebu: use the cpufreq-dt platform_data for independent clocks + +This commit adjusts the registration of the cpufreq-dt driver in the +mvebu platform to indicate to the cpufreq driver that the platform has +independent clocks for each CPU. + +Signed-off-by: Thomas Petazzoni +Acked-by: Jason Cooper +Signed-off-by: Arnd Bergmann + +--- a/arch/arm/mach-mvebu/pmsu.c ++++ b/arch/arm/mach-mvebu/pmsu.c +@@ -20,6 +20,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -586,6 +587,10 @@ int mvebu_pmsu_dfs_request(int cpu) + return 0; + } + ++struct cpufreq_dt_platform_data cpufreq_dt_pd = { ++ .independent_clocks = true, ++}; ++ + static int __init armada_xp_pmsu_cpufreq_init(void) + { + struct device_node *np; +@@ -658,7 +663,8 @@ static int __init armada_xp_pmsu_cpufreq + } + } + +- platform_device_register_simple("cpufreq-dt", -1, NULL, 0); ++ platform_device_register_data(NULL, "cpufreq-dt", -1, ++ &cpufreq_dt_pd, sizeof(cpufreq_dt_pd)); + return 0; + } + diff --git a/target/linux/mvebu/patches-3.18/198-gpio_mvebu_suspend.patch b/target/linux/mvebu/patches-3.18/198-gpio_mvebu_suspend.patch new file mode 100644 index 0000000..9ef1815 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/198-gpio_mvebu_suspend.patch @@ -0,0 +1,137 @@ +This commit adds the implementation of ->suspend() and ->resume() +platform_driver hooks in order to save and restore the state of the +GPIO configuration. In order to achieve that, additional fields are +added to the mvebu_gpio_chip structure. + +Signed-off-by: Thomas Petazzoni +Acked-by: Alexandre Courbot +Signed-off-by: Linus Walleij + +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -83,6 +83,14 @@ struct mvebu_gpio_chip { + int irqbase; + struct irq_domain *domain; + int soc_variant; ++ ++ /* Used to preserve GPIO registers accross suspend/resume */ ++ u32 out_reg; ++ u32 io_conf_reg; ++ u32 blink_en_reg; ++ u32 in_pol_reg; ++ u32 edge_mask_regs[4]; ++ u32 level_mask_regs[4]; + }; + + /* +@@ -562,6 +570,93 @@ static const struct of_device_id mvebu_g + }; + MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match); + ++static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); ++ int i; ++ ++ mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip)); ++ mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip)); ++ mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip)); ++ mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip)); ++ ++ switch (mvchip->soc_variant) { ++ case MVEBU_GPIO_SOC_VARIANT_ORION: ++ mvchip->edge_mask_regs[0] = ++ readl(mvchip->membase + GPIO_EDGE_MASK_OFF); ++ mvchip->level_mask_regs[0] = ++ readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); ++ break; ++ case MVEBU_GPIO_SOC_VARIANT_MV78200: ++ for (i = 0; i < 2; i++) { ++ mvchip->edge_mask_regs[i] = ++ readl(mvchip->membase + ++ GPIO_EDGE_MASK_MV78200_OFF(i)); ++ mvchip->level_mask_regs[i] = ++ readl(mvchip->membase + ++ GPIO_LEVEL_MASK_MV78200_OFF(i)); ++ } ++ break; ++ case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: ++ for (i = 0; i < 4; i++) { ++ mvchip->edge_mask_regs[i] = ++ readl(mvchip->membase + ++ GPIO_EDGE_MASK_ARMADAXP_OFF(i)); ++ mvchip->level_mask_regs[i] = ++ readl(mvchip->membase + ++ GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); ++ } ++ break; ++ default: ++ BUG(); ++ } ++ ++ return 0; ++} ++ ++static int mvebu_gpio_resume(struct platform_device *pdev) ++{ ++ struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); ++ int i; ++ ++ writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip)); ++ writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip)); ++ writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip)); ++ writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip)); ++ ++ switch (mvchip->soc_variant) { ++ case MVEBU_GPIO_SOC_VARIANT_ORION: ++ writel(mvchip->edge_mask_regs[0], ++ mvchip->membase + GPIO_EDGE_MASK_OFF); ++ writel(mvchip->level_mask_regs[0], ++ mvchip->membase + GPIO_LEVEL_MASK_OFF); ++ break; ++ case MVEBU_GPIO_SOC_VARIANT_MV78200: ++ for (i = 0; i < 2; i++) { ++ writel(mvchip->edge_mask_regs[i], ++ mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); ++ writel(mvchip->level_mask_regs[i], ++ mvchip->membase + ++ GPIO_LEVEL_MASK_MV78200_OFF(i)); ++ } ++ break; ++ case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: ++ for (i = 0; i < 4; i++) { ++ writel(mvchip->edge_mask_regs[i], ++ mvchip->membase + ++ GPIO_EDGE_MASK_ARMADAXP_OFF(i)); ++ writel(mvchip->level_mask_regs[i], ++ mvchip->membase + ++ GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); ++ } ++ break; ++ default: ++ BUG(); ++ } ++ ++ return 0; ++} ++ + static int mvebu_gpio_probe(struct platform_device *pdev) + { + struct mvebu_gpio_chip *mvchip; +@@ -585,6 +680,8 @@ static int mvebu_gpio_probe(struct platf + if (!mvchip) + return -ENOMEM; + ++ platform_set_drvdata(pdev, mvchip); ++ + if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { + dev_err(&pdev->dev, "Missing ngpios OF property\n"); + return -ENODEV; +@@ -743,5 +840,7 @@ static struct platform_driver mvebu_gpio + .of_match_table = mvebu_gpio_of_match, + }, + .probe = mvebu_gpio_probe, ++ .suspend = mvebu_gpio_suspend, ++ .resume = mvebu_gpio_resume, + }; + module_platform_driver(mvebu_gpio_driver); diff --git a/target/linux/mvebu/patches-3.18/199-gpio_mvebu_drop_owner.patch b/target/linux/mvebu/patches-3.18/199-gpio_mvebu_drop_owner.patch new file mode 100644 index 0000000..fe74199 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/199-gpio_mvebu_drop_owner.patch @@ -0,0 +1,15 @@ +A platform_driver does not need to set an owner, it will be populated by the +driver core. + +Signed-off-by: Wolfram Sang + +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -836,7 +836,6 @@ static int mvebu_gpio_probe(struct platf + static struct platform_driver mvebu_gpio_driver = { + .driver = { + .name = "mvebu-gpio", +- .owner = THIS_MODULE, + .of_match_table = mvebu_gpio_of_match, + }, + .probe = mvebu_gpio_probe, diff --git a/target/linux/mvebu/patches-3.18/200-gpio_mvebu_checkpatch_fixes.patch b/target/linux/mvebu/patches-3.18/200-gpio_mvebu_checkpatch_fixes.patch new file mode 100644 index 0000000..48ab67d --- /dev/null +++ b/target/linux/mvebu/patches-3.18/200-gpio_mvebu_checkpatch_fixes.patch @@ -0,0 +1,223 @@ +Wrap some long lines. +Prefer seq_puts() over seq_printf(). +space to tab conversions. +Spelling error fix. + +Signed-off-by: Andrew Lunn +--- + drivers/gpio/gpio-mvebu.c | 77 ++++++++++++++++++++++++++--------------------- + 1 file changed, 42 insertions(+), 35 deletions(-) + +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -59,7 +59,7 @@ + #define GPIO_LEVEL_MASK_OFF 0x001c + + /* The MV78200 has per-CPU registers for edge mask and level mask */ +-#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) ++#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) + #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) + + /* The Armada XP has per-CPU registers for interrupt cause, interrupt +@@ -69,11 +69,11 @@ + #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) + #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) + +-#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 +-#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 ++#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 ++#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 + #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 + +-#define MVEBU_MAX_GPIO_PER_BANK 32 ++#define MVEBU_MAX_GPIO_PER_BANK 32 + + struct mvebu_gpio_chip { + struct gpio_chip chip; +@@ -82,9 +82,9 @@ struct mvebu_gpio_chip { + void __iomem *percpu_membase; + int irqbase; + struct irq_domain *domain; +- int soc_variant; ++ int soc_variant; + +- /* Used to preserve GPIO registers accross suspend/resume */ ++ /* Used to preserve GPIO registers across suspend/resume */ + u32 out_reg; + u32 io_conf_reg; + u32 blink_en_reg; +@@ -107,7 +107,8 @@ static inline void __iomem *mvebu_gpiore + return mvchip->membase + GPIO_BLINK_EN_OFF; + } + +-static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) ++static inline void __iomem * ++mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) + { + return mvchip->membase + GPIO_IO_CONF_OFF; + } +@@ -117,12 +118,14 @@ static inline void __iomem *mvebu_gpiore + return mvchip->membase + GPIO_IN_POL_OFF; + } + +-static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) ++static inline void __iomem * ++mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) + { + return mvchip->membase + GPIO_DATA_IN_OFF; + } + +-static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) ++static inline void __iomem * ++mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) + { + int cpu; + +@@ -132,13 +135,15 @@ static inline void __iomem *mvebu_gpiore + return mvchip->membase + GPIO_EDGE_CAUSE_OFF; + case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: + cpu = smp_processor_id(); +- return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); ++ return mvchip->percpu_membase + ++ GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); + default: + BUG(); + } + } + +-static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) ++static inline void __iomem * ++mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) + { + int cpu; + +@@ -150,7 +155,8 @@ static inline void __iomem *mvebu_gpiore + return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); + case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: + cpu = smp_processor_id(); +- return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); ++ return mvchip->percpu_membase + ++ GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); + default: + BUG(); + } +@@ -168,7 +174,8 @@ static void __iomem *mvebu_gpioreg_level + return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); + case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: + cpu = smp_processor_id(); +- return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); ++ return mvchip->percpu_membase + ++ GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); + default: + BUG(); + } +@@ -372,22 +379,22 @@ static void mvebu_gpio_level_irq_unmask( + * value of the line or the opposite value. + * + * Level IRQ handlers: DATA_IN is used directly as cause register. +- * Interrupt are masked by LEVEL_MASK registers. ++ * Interrupt are masked by LEVEL_MASK registers. + * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. +- * Interrupt are masked by EDGE_MASK registers. ++ * Interrupt are masked by EDGE_MASK registers. + * Both-edge handlers: Similar to regular Edge handlers, but also swaps +- * the polarity to catch the next line transaction. +- * This is a race condition that might not perfectly +- * work on some use cases. ++ * the polarity to catch the next line transaction. ++ * This is a race condition that might not perfectly ++ * work on some use cases. + * + * Every eight GPIO lines are grouped (OR'ed) before going up to main + * cause register. + * +- * EDGE cause mask +- * data-in /--------| |-----| |----\ +- * -----| |----- ---- to main cause reg +- * X \----------------| |----/ +- * polarity LEVEL mask ++ * EDGE cause mask ++ * data-in /--------| |-----| |----\ ++ * -----| |----- ---- to main cause reg ++ * X \----------------| |----/ ++ * polarity LEVEL mask + * + ****************************************************************************/ + +@@ -402,9 +409,8 @@ static int mvebu_gpio_irq_set_type(struc + pin = d->hwirq; + + u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); +- if (!u) { ++ if (!u) + return -EINVAL; +- } + + type &= IRQ_TYPE_SENSE_MASK; + if (type == IRQ_TYPE_NONE) +@@ -537,13 +543,13 @@ static void mvebu_gpio_dbg_show(struct s + (data_in ^ in_pol) & msk ? "hi" : "lo", + in_pol & msk ? "lo" : "hi"); + if (!((edg_msk | lvl_msk) & msk)) { +- seq_printf(s, " disabled\n"); ++ seq_puts(s, " disabled\n"); + continue; + } + if (edg_msk & msk) +- seq_printf(s, " edge "); ++ seq_puts(s, " edge "); + if (lvl_msk & msk) +- seq_printf(s, " level"); ++ seq_puts(s, " level"); + seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); + } + } +@@ -554,15 +560,15 @@ static void mvebu_gpio_dbg_show(struct s + static const struct of_device_id mvebu_gpio_of_match[] = { + { + .compatible = "marvell,orion-gpio", +- .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, ++ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, + }, + { + .compatible = "marvell,mv78200-gpio", +- .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, ++ .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, + }, + { + .compatible = "marvell,armadaxp-gpio", +- .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, ++ .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, + }, + { + /* sentinel */ +@@ -676,7 +682,8 @@ static int mvebu_gpio_probe(struct platf + else + soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; + +- mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL); ++ mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), ++ GFP_KERNEL); + if (!mvchip) + return -ENOMEM; + +@@ -775,8 +782,8 @@ static int mvebu_gpio_probe(struct platf + * interrupt handlers, with each handler dealing with 8 GPIO + * pins. */ + for (i = 0; i < 4; i++) { +- int irq; +- irq = platform_get_irq(pdev, i); ++ int irq = platform_get_irq(pdev, i); ++ + if (irq < 0) + continue; + irq_set_handler_data(irq, mvchip); +@@ -835,7 +842,7 @@ static int mvebu_gpio_probe(struct platf + + static struct platform_driver mvebu_gpio_driver = { + .driver = { +- .name = "mvebu-gpio", ++ .name = "mvebu-gpio", + .of_match_table = mvebu_gpio_of_match, + }, + .probe = mvebu_gpio_probe, diff --git a/target/linux/mvebu/patches-3.18/201-gpio_mvebu_fix_probe_cleanup_on_error.patch b/target/linux/mvebu/patches-3.18/201-gpio_mvebu_fix_probe_cleanup_on_error.patch new file mode 100644 index 0000000..aeb884a --- /dev/null +++ b/target/linux/mvebu/patches-3.18/201-gpio_mvebu_fix_probe_cleanup_on_error.patch @@ -0,0 +1,63 @@ +Ensure that when there is an error during probe that the gpiochip is +removed and the generic irq chip is removed. + +Signed-off-by: Andrew Lunn +--- + drivers/gpio/gpio-mvebu.c | 23 +++++++++++++++++------ + 1 file changed, 17 insertions(+), 6 deletions(-) + +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -675,6 +675,7 @@ static int mvebu_gpio_probe(struct platf + unsigned int ngpios; + int soc_variant; + int i, cpu, id; ++ int err; + + match = of_match_device(mvebu_gpio_of_match, &pdev->dev); + if (match) +@@ -793,14 +794,16 @@ static int mvebu_gpio_probe(struct platf + mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1); + if (mvchip->irqbase < 0) { + dev_err(&pdev->dev, "no irqs\n"); +- return mvchip->irqbase; ++ err = mvchip->irqbase; ++ goto err_gpiochip_add; + } + + gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase, + mvchip->membase, handle_level_irq); + if (!gc) { + dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n"); +- return -ENOMEM; ++ err = -ENOMEM; ++ goto err_gpiochip_add; + } + + gc->private = mvchip; +@@ -831,13 +834,21 @@ static int mvebu_gpio_probe(struct platf + if (!mvchip->domain) { + dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", + mvchip->chip.label); +- irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, +- IRQ_LEVEL | IRQ_NOPROBE); +- kfree(gc); +- return -ENODEV; ++ err = -ENODEV; ++ goto err_generic_chip; + } + + return 0; ++ ++err_generic_chip: ++ irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, ++ IRQ_LEVEL | IRQ_NOPROBE); ++ kfree(gc); ++ ++err_gpiochip_add: ++ gpiochip_remove(&mvchip->chip); ++ ++ return err; + } + + static struct platform_driver mvebu_gpio_driver = { diff --git a/target/linux/mvebu/patches-3.18/202-gpio_mvebu_add_limited_pwm_support.patch b/target/linux/mvebu/patches-3.18/202-gpio_mvebu_add_limited_pwm_support.patch new file mode 100644 index 0000000..49a8c0a --- /dev/null +++ b/target/linux/mvebu/patches-3.18/202-gpio_mvebu_add_limited_pwm_support.patch @@ -0,0 +1,433 @@ +Armada 370/XP devices can 'blink' gpio lines with a configurable on +and off period. This can be modelled as a PWM. + +However, there are only two sets of PWM configuration registers for +all the gpio lines. This driver simply allows a single gpio line per +gpio chip of 32 lines to be used as a PWM. Attempts to use more return +EBUSY. + +Due to the interleaving of registers it is not simple to separate the +PWM driver from the gpio driver. Thus the gpio driver has been +extended with a PWM driver. + +Signed-off-by: Andrew Lunn +--- + drivers/gpio/Kconfig | 5 ++ + drivers/gpio/Makefile | 1 + + drivers/gpio/gpio-mvebu-pwm.c | 202 ++++++++++++++++++++++++++++++++++++++++++ + drivers/gpio/gpio-mvebu.c | 37 +++----- + drivers/gpio/gpio-mvebu.h | 79 +++++++++++++++++ + 5 files changed, 299 insertions(+), 25 deletions(-) + create mode 100644 drivers/gpio/gpio-mvebu-pwm.c + create mode 100644 drivers/gpio/gpio-mvebu.h + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -223,6 +223,11 @@ config GPIO_MVEBU + select GPIO_GENERIC + select GENERIC_IRQ_CHIP + ++config GPIO_MVEBU_PWM ++ def_bool y ++ depends on GPIO_MVEBU ++ depends on PWM ++ + config GPIO_MXC + def_bool y + depends on ARCH_MXC +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -58,6 +58,7 @@ obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o + obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o + obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o + obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o ++obj-$(CONFIG_GPIO_MVEBU_PWM) += gpio-mvebu-pwm.o + obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o + obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o + obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o +--- /dev/null ++++ b/drivers/gpio/gpio-mvebu-pwm.c +@@ -0,0 +1,202 @@ ++#include "asm/io.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include "gpio-mvebu.h" ++#include "gpiolib.h" ++static void __iomem *mvebu_gpioreg_blink_select(struct mvebu_gpio_chip *mvchip) ++{ ++ return mvchip->membase + GPIO_BLINK_CNT_SELECT; ++} ++ ++static inline struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) ++{ ++ return container_of(chip, struct mvebu_pwm, chip); ++} ++ ++static inline struct mvebu_gpio_chip *to_mvchip(struct mvebu_pwm *pwm) ++{ ++ return container_of(pwm, struct mvebu_gpio_chip, pwm); ++} ++ ++static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ struct gpio_desc *desc = gpio_to_desc(pwmd->pwm); ++ unsigned long flags; ++ int ret = 0; ++ ++ spin_lock_irqsave(&pwm->lock, flags); ++ if (pwm->used) { ++ ret = -EBUSY; ++ } else { ++ if (!desc) { ++ ret = -ENODEV; ++ goto out; ++ } ++ ret = gpiod_request(desc, "mvebu-pwm"); ++ if (ret) ++ goto out; ++ ++ ret = gpiod_direction_output(desc, 0); ++ if (ret) { ++ gpiod_free(desc); ++ goto out; ++ } ++ ++ pwm->pin = pwmd->pwm - mvchip->chip.base; ++ pwm->used = true; ++ } ++ ++out: ++ spin_unlock_irqrestore(&pwm->lock, flags); ++ return ret; ++} ++ ++static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct gpio_desc *desc = gpio_to_desc(pwmd->pwm); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&pwm->lock, flags); ++ gpiod_free(desc); ++ pwm->used = false; ++ spin_unlock_irqrestore(&pwm->lock, flags); ++} ++ ++static int mvebu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwmd, ++ int duty_ns, int period_ns) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ unsigned int on, off; ++ unsigned long long val; ++ u32 u; ++ ++ val = (unsigned long long) pwm->clk_rate * duty_ns; ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ on = val; ++ else ++ on = 1; ++ ++ val = (unsigned long long) pwm->clk_rate * (period_ns - duty_ns); ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ off = val; ++ else ++ off = 1; ++ ++ u = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ u &= ~(1 << pwm->pin); ++ u |= (pwm->id << pwm->pin); ++ writel_relaxed(u, mvebu_gpioreg_blink_select(mvchip)); ++ ++ writel_relaxed(on, pwm->membase + BLINK_ON_DURATION); ++ writel_relaxed(off, pwm->membase + BLINK_OFF_DURATION); ++ ++ return 0; ++} ++ ++static int mvebu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ ++ mvebu_gpio_blink(&mvchip->chip, pwm->pin, 1); ++ ++ return 0; ++} ++ ++static void mvebu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ ++ mvebu_gpio_blink(&mvchip->chip, pwm->pin, 0); ++} ++ ++static const struct pwm_ops mvebu_pwm_ops = { ++ .request = mvebu_pwm_request, ++ .free = mvebu_pwm_free, ++ .config = mvebu_pwm_config, ++ .enable = mvebu_pwm_enable, ++ .disable = mvebu_pwm_disable, ++ .owner = THIS_MODULE, ++}; ++ ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ ++ pwm->blink_select = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ pwm->blink_on_duration = ++ readl_relaxed(pwm->membase + BLINK_ON_DURATION); ++ pwm->blink_off_duration = ++ readl_relaxed(pwm->membase + BLINK_OFF_DURATION); ++} ++ ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ ++ writel_relaxed(pwm->blink_select, mvebu_gpioreg_blink_select(mvchip)); ++ writel_relaxed(pwm->blink_on_duration, ++ pwm->membase + BLINK_ON_DURATION); ++ writel_relaxed(pwm->blink_off_duration, ++ pwm->membase + BLINK_OFF_DURATION); ++} ++ ++/* ++ * Armada 370/XP has simple PWM support for gpio lines. Other SoCs ++ * don't have this hardware. So if we don't have the necessary ++ * resource, it is not an error. ++ */ ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ struct device *dev = &pdev->dev; ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ struct resource *res; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); ++ if (!res) ++ return 0; ++ ++ mvchip->pwm.membase = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(mvchip->pwm.membase)) ++ return PTR_ERR(mvchip->percpu_membase); ++ ++ if (id < 0 || id > 1) ++ return -EINVAL; ++ pwm->id = id; ++ ++ if (IS_ERR(mvchip->clk)) ++ return PTR_ERR(mvchip->clk); ++ ++ pwm->clk_rate = clk_get_rate(mvchip->clk); ++ if (!pwm->clk_rate) { ++ dev_err(dev, "failed to get clock rate\n"); ++ return -EINVAL; ++ } ++ ++ pwm->chip.dev = dev; ++ pwm->chip.ops = &mvebu_pwm_ops; ++ pwm->chip.base = mvchip->chip.base; ++ pwm->chip.npwm = mvchip->chip.ngpio; ++ pwm->chip.can_sleep = false; ++ ++ spin_lock_init(&pwm->lock); ++ ++ return pwmchip_add(&pwm->chip); ++} +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -42,10 +42,11 @@ + #include + #include + #include ++#include + #include + #include + #include +- ++#include "gpio-mvebu.h" + /* + * GPIO unit register offsets. + */ +@@ -75,24 +76,6 @@ + + #define MVEBU_MAX_GPIO_PER_BANK 32 + +-struct mvebu_gpio_chip { +- struct gpio_chip chip; +- spinlock_t lock; +- void __iomem *membase; +- void __iomem *percpu_membase; +- int irqbase; +- struct irq_domain *domain; +- int soc_variant; +- +- /* Used to preserve GPIO registers across suspend/resume */ +- u32 out_reg; +- u32 io_conf_reg; +- u32 blink_en_reg; +- u32 in_pol_reg; +- u32 edge_mask_regs[4]; +- u32 level_mask_regs[4]; +-}; +- + /* + * Functions returning addresses of individual registers for a given + * GPIO controller. +@@ -228,7 +211,7 @@ static int mvebu_gpio_get(struct gpio_ch + return (u >> pin) & 1; + } + +-static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) ++void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) + { + struct mvebu_gpio_chip *mvchip = + container_of(chip, struct mvebu_gpio_chip, chip); +@@ -617,6 +600,8 @@ static int mvebu_gpio_suspend(struct pla + BUG(); + } + ++ mvebu_pwm_suspend(mvchip); ++ + return 0; + } + +@@ -660,6 +645,8 @@ static int mvebu_gpio_resume(struct plat + BUG(); + } + ++ mvebu_pwm_resume(mvchip); ++ + return 0; + } + +@@ -671,7 +658,6 @@ static int mvebu_gpio_probe(struct platf + struct resource *res; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; +- struct clk *clk; + unsigned int ngpios; + int soc_variant; + int i, cpu, id; +@@ -701,10 +687,10 @@ static int mvebu_gpio_probe(struct platf + return id; + } + +- clk = devm_clk_get(&pdev->dev, NULL); ++ mvchip->clk = devm_clk_get(&pdev->dev, NULL); + /* Not all SoCs require a clock.*/ +- if (!IS_ERR(clk)) +- clk_prepare_enable(clk); ++ if (!IS_ERR(mvchip->clk)) ++ clk_prepare_enable(mvchip->clk); + + mvchip->soc_variant = soc_variant; + mvchip->chip.label = dev_name(&pdev->dev); +@@ -838,7 +824,8 @@ static int mvebu_gpio_probe(struct platf + goto err_generic_chip; + } + +- return 0; ++ /* Armada 370/XP has simple PWM support for gpio lines */ ++ return mvebu_pwm_probe(pdev, mvchip, id); + + err_generic_chip: + irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, +--- /dev/null ++++ b/drivers/gpio/gpio-mvebu.h +@@ -0,0 +1,79 @@ ++/* ++ * Interface between MVEBU GPIO driver and PWM driver for GPIO pins ++ * ++ * Copyright (C) 2015, Andrew Lunn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef MVEBU_GPIO_PWM_H ++#define MVEBU_GPIO_PWM_H ++ ++#define BLINK_ON_DURATION 0x0 ++#define BLINK_OFF_DURATION 0x4 ++#define GPIO_BLINK_CNT_SELECT 0x0020 ++ ++struct mvebu_pwm { ++ void __iomem *membase; ++ unsigned long clk_rate; ++ bool used; ++ unsigned pin; ++ struct pwm_chip chip; ++ int id; ++ spinlock_t lock; ++ ++ /* Used to preserve GPIO/PWM registers across suspend / ++ * resume */ ++ u32 blink_select; ++ u32 blink_on_duration; ++ u32 blink_off_duration; ++}; ++ ++struct mvebu_gpio_chip { ++ struct gpio_chip chip; ++ spinlock_t lock; ++ void __iomem *membase; ++ void __iomem *percpu_membase; ++ int irqbase; ++ struct irq_domain *domain; ++ int soc_variant; ++ struct clk *clk; ++#ifdef CONFIG_PWM ++ struct mvebu_pwm pwm; ++#endif ++ /* Used to preserve GPIO registers across suspend/resume */ ++ u32 out_reg; ++ u32 io_conf_reg; ++ u32 blink_en_reg; ++ u32 in_pol_reg; ++ u32 edge_mask_regs[4]; ++ u32 level_mask_regs[4]; ++}; ++ ++void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value); ++ ++#ifdef CONFIG_PWM ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id); ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip); ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip); ++#else ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ return 0; ++} ++ ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++} ++ ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++} ++#endif ++#endif diff --git a/target/linux/mvebu/patches-3.18/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch b/target/linux/mvebu/patches-3.18/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch new file mode 100644 index 0000000..48f9394 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch @@ -0,0 +1,52 @@ +Document the optional parameters needed for PWM operation of gpio +lines. + +Signed-off-by: Andrew Lunn +--- + .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 ++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt ++++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +@@ -38,6 +38,23 @@ Required properties: + - #gpio-cells: Should be two. The first cell is the pin number. The + second cell is reserved for flags, unused at the moment. + ++Optional properties: ++ ++In order to use the gpio lines in PWM mode, some additional optional ++properties are required. Only Armada 370 and XP supports these ++properties. ++ ++- reg: an additional register set is needed, for the GPIO Blink ++ Counter on/off registers. ++ ++- reg-names: Must contain an entry "pwm" corresponding to the ++ additional register range needed for pwm operation. ++ ++- #pwm-cells: Should be two. The first cell is the pin number. The ++ second cell is reserved for flags, unused at the moment. ++ ++- clocks: Must be a phandle to the clock for the gpio controller. ++ + Example: + + gpio0: gpio@d0018100 { +@@ -51,3 +68,17 @@ Example: + #interrupt-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; ++ ++ gpio1: gpio@18140 { ++ compatible = "marvell,orion-gpio"; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; ++ ngpios = <17>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ #pwm-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; ++ }; diff --git a/target/linux/mvebu/patches-3.18/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch b/target/linux/mvebu/patches-3.18/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch new file mode 100644 index 0000000..9272d99 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch @@ -0,0 +1,149 @@ +Add properties to the gpio nodes to allow them to be also used +as pwm lines. + +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-370.dtsi | 10 ++++++++-- + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 10 ++++++++-- + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 8 ++++++-- + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 10 ++++++++-- + 4 files changed, 30 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -109,24 +109,30 @@ + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -169,24 +169,30 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -253,24 +253,28 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -291,24 +291,30 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { diff --git a/target/linux/mvebu/patches-3.18/205-arm_mvebu_enable_pwm_in_defconfig.patch b/target/linux/mvebu/patches-3.18/205-arm_mvebu_enable_pwm_in_defconfig.patch new file mode 100644 index 0000000..1ff724c --- /dev/null +++ b/target/linux/mvebu/patches-3.18/205-arm_mvebu_enable_pwm_in_defconfig.patch @@ -0,0 +1,18 @@ +Now that the gpio driver also supports PWM operation, enable +the PWM framework in mvebu_v7_defconfig. + +Signed-off-by: Andrew Lunn +--- + arch/arm/configs/mvebu_v7_defconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/configs/mvebu_v7_defconfig ++++ b/arch/arm/configs/mvebu_v7_defconfig +@@ -109,6 +109,7 @@ CONFIG_DMADEVICES=y + CONFIG_MV_XOR=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_MEMORY=y ++CONFIG_PWM=y + CONFIG_EXT4_FS=y + CONFIG_ISO9660_FS=y + CONFIG_JOLIET=y diff --git a/target/linux/mvebu/patches-3.18/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch b/target/linux/mvebu/patches-3.18/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch new file mode 100644 index 0000000..58d8280 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch @@ -0,0 +1,28 @@ +The mvebu gpio driver can also perform PWM on some pins. Us the +pwm-fan driver to control the fan of the WRT1900AC, giving us fine +grain control over its speed and hence noise. + +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-xp-wrt1900ac.dts | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -412,13 +412,11 @@ + }; + }; + +- gpio_fan { ++ pwm_fan { + /* SUNON HA4010V4-0000-C99 */ +- compatible = "gpio-fan"; +- gpios = <&gpio0 24 0>; + +- gpio-fan,speed-map = <0 0 +- 4500 1>; ++ compatible = "pwm-fan"; ++ pwms = <&gpio0 24 4000 0>; + }; + + mvsw61xx { diff --git a/target/linux/mvebu/patches-3.18/207-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-3.18/207-armada-385-rd-mtd-partitions.patch new file mode 100644 index 0000000..80cec30 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/207-armada-385-rd-mtd-partitions.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/armada-385-rd.dts ++++ b/arch/arm/boot/dts/armada-385-rd.dts +@@ -42,6 +42,16 @@ + compatible = "st,m25p128"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; ++ ++ partition@0 { ++ label = "uboot"; ++ reg = <0 0x400000>; ++ }; ++ ++ partition@1 { ++ label = "firmware"; ++ reg = <0x400000 0xc00000>; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-3.18/208-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-3.18/208-ARM-mvebu-385-ap-Add-partitions.patch new file mode 100644 index 0000000..2845181 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/208-ARM-mvebu-385-ap-Add-partitions.patch @@ -0,0 +1,34 @@ +From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Tue, 13 Jan 2015 11:14:09 +0100 +Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -162,6 +162,21 @@ + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; ++ ++ mtd0@00000000 { ++ label = "u-boot"; ++ reg = <0x00000000 0x00800000>; ++ }; ++ ++ mtd1@00800000 { ++ label = "kernel"; ++ reg = <0x00800000 0x00800000>; ++ }; ++ ++ mtd2@01000000 { ++ label = "ubi"; ++ reg = <0x01000000 0x3f000000>; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-3.18/300-add_missing_labels.patch b/target/linux/mvebu/patches-3.18/300-add_missing_labels.patch new file mode 100644 index 0000000..b674b56 --- /dev/null +++ b/target/linux/mvebu/patches-3.18/300-add_missing_labels.patch @@ -0,0 +1,29 @@ +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -173,7 +173,7 @@ + status = "disabled"; + }; + +- serial@12000 { ++ uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; +@@ -193,7 +193,7 @@ + status = "disabled"; + }; + +- pinctrl@18000 { ++ pinctrl: pinctrl@18000 { + compatible = "marvell,mv88f6820-pinctrl"; + reg = <0x18000 0x20>; + +@@ -412,7 +412,7 @@ + status = "disabled"; + }; + +- mdio@72004 { ++ mdio: mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; diff --git a/target/linux/mvebu/patches-3.18/600-armada_38x_rtc.patch b/target/linux/mvebu/patches-3.18/600-armada_38x_rtc.patch new file mode 100644 index 0000000..399421d --- /dev/null +++ b/target/linux/mvebu/patches-3.18/600-armada_38x_rtc.patch @@ -0,0 +1,403 @@ +--- /dev/null ++++ b/Documentation/devicetree/bindings/rtc/armada-380-rtc.txt +@@ -0,0 +1,22 @@ ++* Real Time Clock of the Armada 38x SoCs ++ ++RTC controller for the Armada 38x SoCs ++ ++Required properties: ++- compatible : Should be "marvell,armada-380-rtc" ++- reg: a list of base address and size pairs, one for each entry in ++ reg-names ++- reg names: should contain: ++ * "rtc" for the RTC registers ++ * "rtc-soc" for the SoC related registers and among them the one ++ related to the interrupt. ++- interrupts: IRQ line for the RTC. ++ ++Example: ++ ++rtc@a3800 { ++ compatible = "marvell,armada-380-rtc"; ++ reg = <0xa3800 0x20>, <0x184a0 0x0c>; ++ reg-names = "rtc", "rtc-soc"; ++ interrupts = ; ++}; +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1262,6 +1262,16 @@ config RTC_DRV_MV + This driver can also be built as a module. If so, the module + will be called rtc-mv. + ++config RTC_DRV_ARMADA38X ++ tristate "Armada 38x Marvell SoC RTC" ++ depends on ARCH_MVEBU ++ help ++ If you say yes here you will get support for the in-chip RTC ++ that can be found in the Armada 38x Marvell's SoC device ++ ++ This driver can also be built as a module. If so, the module ++ will be called armada38x-rtc. ++ + config RTC_DRV_PS3 + tristate "PS3 RTC" + depends on PPC_PS3 +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-8 + obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o + obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o + obj-$(CONFIG_RTC_DRV_AB8500) += rtc-ab8500.o ++obj-$(CONFIG_RTC_DRV_ARMADA38X) += rtc-armada38x.o + obj-$(CONFIG_RTC_DRV_AS3722) += rtc-as3722.o + obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o + obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o +--- /dev/null ++++ b/drivers/rtc/rtc-armada38x.c +@@ -0,0 +1,320 @@ ++/* ++ * RTC driver for the Armada 38x Marvell SoCs ++ * ++ * Copyright (C) 2015 Marvell ++ * ++ * Gregory Clement ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RTC_STATUS 0x0 ++#define RTC_STATUS_ALARM1 BIT(0) ++#define RTC_STATUS_ALARM2 BIT(1) ++#define RTC_IRQ1_CONF 0x4 ++#define RTC_IRQ1_AL_EN BIT(0) ++#define RTC_IRQ1_FREQ_EN BIT(1) ++#define RTC_IRQ1_FREQ_1HZ BIT(2) ++#define RTC_TIME 0xC ++#define RTC_ALARM1 0x10 ++ ++#define SOC_RTC_INTERRUPT 0x8 ++#define SOC_RTC_ALARM1 BIT(0) ++#define SOC_RTC_ALARM2 BIT(1) ++#define SOC_RTC_ALARM1_MASK BIT(2) ++#define SOC_RTC_ALARM2_MASK BIT(3) ++ ++struct armada38x_rtc { ++ struct rtc_device *rtc_dev; ++ void __iomem *regs; ++ void __iomem *regs_soc; ++ spinlock_t lock; ++ int irq; ++}; ++ ++/* ++ * According to the datasheet, the OS should wait 5us after every ++ * register write to the RTC hard macro so that the required update ++ * can occur without holding off the system bus ++ */ ++static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset) ++{ ++ writel(val, rtc->regs + offset); ++ udelay(5); ++} ++ ++static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long time, time_check, flags; ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ time = readl(rtc->regs + RTC_TIME); ++ /* ++ * WA for failing time set attempts. As stated in HW ERRATA if ++ * more than one second between two time reads is detected ++ * then read once again. ++ */ ++ time_check = readl(rtc->regs + RTC_TIME); ++ if ((time_check - time) > 1) ++ time_check = readl(rtc->regs + RTC_TIME); ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++ rtc_time_to_tm(time_check, tm); ++ ++ return 0; ++} ++ ++static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ int ret = 0; ++ unsigned long time, flags; ++ ++ ret = rtc_tm_to_time(tm, &time); ++ ++ if (ret) ++ goto out; ++ /* ++ * Setting the RTC time not always succeeds. According to the ++ * errata we need to first write on the status register and ++ * then wait for 100ms before writing to the time register to be ++ * sure that the data will be taken into account. ++ */ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ rtc_delayed_write(0, rtc, RTC_STATUS); ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++ msleep(100); ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ rtc_delayed_write(time, rtc, RTC_TIME); ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++out: ++ return ret; ++} ++ ++static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long time, flags; ++ u32 val; ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ time = readl(rtc->regs + RTC_ALARM1); ++ val = readl(rtc->regs + RTC_IRQ1_CONF) & RTC_IRQ1_AL_EN; ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++ alrm->enabled = val ? 1 : 0; ++ rtc_time_to_tm(time, &alrm->time); ++ ++ return 0; ++} ++ ++static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long time, flags; ++ int ret = 0; ++ u32 val; ++ ++ ret = rtc_tm_to_time(&alrm->time, &time); ++ ++ if (ret) ++ goto out; ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ rtc_delayed_write(time, rtc, RTC_ALARM1); ++ ++ if (alrm->enabled) { ++ rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF); ++ val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); ++ writel(val | SOC_RTC_ALARM1_MASK, ++ rtc->regs_soc + SOC_RTC_INTERRUPT); ++ } ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++out: ++ return ret; ++} ++ ++static int armada38x_rtc_alarm_irq_enable(struct device *dev, ++ unsigned int enabled) ++{ ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&rtc->lock, flags); ++ ++ if (enabled) ++ rtc_delayed_write(RTC_IRQ1_AL_EN, rtc, RTC_IRQ1_CONF); ++ else ++ rtc_delayed_write(0, rtc, RTC_IRQ1_CONF); ++ ++ spin_unlock_irqrestore(&rtc->lock, flags); ++ ++ return 0; ++} ++ ++static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data) ++{ ++ struct armada38x_rtc *rtc = data; ++ u32 val; ++ int event = RTC_IRQF | RTC_AF; ++ ++ dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq); ++ ++ spin_lock(&rtc->lock); ++ ++ val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT); ++ ++ writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT); ++ val = readl(rtc->regs + RTC_IRQ1_CONF); ++ /* disable all the interrupts for alarm 1 */ ++ rtc_delayed_write(0, rtc, RTC_IRQ1_CONF); ++ /* Ack the event */ ++ rtc_delayed_write(RTC_STATUS_ALARM1, rtc, RTC_STATUS); ++ ++ spin_unlock(&rtc->lock); ++ ++ if (val & RTC_IRQ1_FREQ_EN) { ++ if (val & RTC_IRQ1_FREQ_1HZ) ++ event |= RTC_UF; ++ else ++ event |= RTC_PF; ++ } ++ ++ rtc_update_irq(rtc->rtc_dev, 1, event); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct rtc_class_ops armada38x_rtc_ops = { ++ .read_time = armada38x_rtc_read_time, ++ .set_time = armada38x_rtc_set_time, ++ .read_alarm = armada38x_rtc_read_alarm, ++ .set_alarm = armada38x_rtc_set_alarm, ++ .alarm_irq_enable = armada38x_rtc_alarm_irq_enable, ++}; ++ ++static __init int armada38x_rtc_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct armada38x_rtc *rtc; ++ int ret; ++ ++ rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc), ++ GFP_KERNEL); ++ if (!rtc) ++ return -ENOMEM; ++ ++ spin_lock_init(&rtc->lock); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc"); ++ rtc->regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(rtc->regs)) ++ return PTR_ERR(rtc->regs); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc"); ++ rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(rtc->regs_soc)) ++ return PTR_ERR(rtc->regs_soc); ++ ++ rtc->irq = platform_get_irq(pdev, 0); ++ ++ if (rtc->irq < 0) { ++ dev_err(&pdev->dev, "no irq\n"); ++ return rtc->irq; ++ } ++ if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq, ++ 0, pdev->name, rtc) < 0) { ++ dev_warn(&pdev->dev, "Interrupt not available.\n"); ++ rtc->irq = -1; ++ /* ++ * If there is no interrupt available then we can't ++ * use the alarm ++ */ ++ armada38x_rtc_ops.set_alarm = NULL; ++ armada38x_rtc_ops.alarm_irq_enable = NULL; ++ } ++ platform_set_drvdata(pdev, rtc); ++ if (rtc->irq != -1) ++ device_init_wakeup(&pdev->dev, 1); ++ ++ rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name, ++ &armada38x_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtc->rtc_dev)) { ++ ret = PTR_ERR(rtc->rtc_dev); ++ dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int armada38x_rtc_suspend(struct device *dev) ++{ ++ if (device_may_wakeup(dev)) { ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ ++ return enable_irq_wake(rtc->irq); ++ } ++ ++ return 0; ++} ++ ++static int armada38x_rtc_resume(struct device *dev) ++{ ++ if (device_may_wakeup(dev)) { ++ struct armada38x_rtc *rtc = dev_get_drvdata(dev); ++ ++ return disable_irq_wake(rtc->irq); ++ } ++ ++ return 0; ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops, ++ armada38x_rtc_suspend, armada38x_rtc_resume); ++ ++#ifdef CONFIG_OF ++static const struct of_device_id armada38x_rtc_of_match_table[] = { ++ { .compatible = "marvell,armada-380-rtc", }, ++ {} ++}; ++#endif ++ ++static struct platform_driver armada38x_rtc_driver = { ++ .driver = { ++ .name = "armada38x-rtc", ++ .pm = &armada38x_rtc_pm_ops, ++ .of_match_table = of_match_ptr(armada38x_rtc_of_match_table), ++ }, ++}; ++ ++module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe); ++ ++MODULE_DESCRIPTION("Marvell Armada 38x RTC driver"); ++MODULE_AUTHOR("Gregory CLEMENT "); ++MODULE_LICENSE("GPL"); +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1136,6 +1136,7 @@ M: Sebastian Hesselbarth +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -420,6 +420,13 @@ + clocks = <&gateclk 4>; + }; + ++ rtc@a3800 { ++ compatible = "marvell,armada-380-rtc"; ++ reg = <0xa3800 0x20>, <0x184a0 0x0c>; ++ reg-names = "rtc", "rtc-soc"; ++ interrupts = ; ++ }; ++ + sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; diff --git a/target/linux/mvebu/patches-3.18/700-usb_xhci_plat_phy_support.patch b/target/linux/mvebu/patches-3.18/700-usb_xhci_plat_phy_support.patch new file mode 100644 index 0000000..3ee9f5c --- /dev/null +++ b/target/linux/mvebu/patches-3.18/700-usb_xhci_plat_phy_support.patch @@ -0,0 +1,47 @@ +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -158,12 +159,27 @@ static int xhci_plat_probe(struct platfo + if (HCC_MAX_PSA(xhci->hcc_params) >= 4) + xhci->shared_hcd->can_do_streams = 1; + ++ hcd->usb_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "usb-phy", 0); ++ if (IS_ERR(hcd->usb_phy)) { ++ ret = PTR_ERR(hcd->usb_phy); ++ if (ret == -EPROBE_DEFER) ++ goto put_usb3_hcd; ++ hcd->usb_phy = NULL; ++ } else { ++ ret = usb_phy_init(hcd->usb_phy); ++ if (ret) ++ goto put_usb3_hcd; ++ } ++ + ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); + if (ret) +- goto put_usb3_hcd; ++ goto disable_usb_phy; + + return 0; + ++disable_usb_phy: ++ usb_phy_shutdown(hcd->usb_phy); ++ + put_usb3_hcd: + usb_put_hcd(xhci->shared_hcd); + +@@ -187,6 +203,7 @@ static int xhci_plat_remove(struct platf + struct clk *clk = xhci->clk; + + usb_remove_hcd(xhci->shared_hcd); ++ usb_phy_shutdown(hcd->usb_phy); + usb_put_hcd(xhci->shared_hcd); + + usb_remove_hcd(hcd); diff --git a/target/linux/mvebu/patches-4.0/001-add_mamba_support.patch b/target/linux/mvebu/patches-4.0/001-add_mamba_support.patch new file mode 100644 index 0000000..0fc2638 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/001-add_mamba_support.patch @@ -0,0 +1,388 @@ +From 4824140f4bd1caaf900215aabe27e4bdd1677704 Mon Sep 17 00:00:00 2001 +From: Imre Kaloz +Date: Mon, 16 Feb 2015 13:31:04 +0100 +Subject: [PATCH] ARM: mvebu: add Linksys WRT1900AC (Mamba) support + +The Linksys WRT1900AC (Mamba) is a router that has + +- 2 mini-PCIe slots with Marvell 88W8864 radios +- 1 USB 3.0 port +- 1 USB 2.0/eSATAp port +- 2 Ethernet interfaces connected to a 88E6172 switch (1x WAN + 4x LAN) +- 128MB NAND flash +- 256MB RAM + +gregory.clement@free-electrons.com: - add ARM to the title + - fix the reference to CONFIG_DEBUG_MVEBU_UART0_ALTERNATE + - fix the unbalanced comment for the syscfg partition + +Signed-off-by: Imre Kaloz +Acked-by: Gregory CLEMENT +Signed-off-by: Gregory CLEMENT +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 348 ++++++++++++++++++++++++++ + 2 files changed, 349 insertions(+) + create mode 100644 arch/arm/boot/dts/armada-xp-linksys-mamba.dts + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -629,6 +629,7 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ + armada-xp-db.dtb \ + armada-xp-gp.dtb \ + armada-xp-lenovo-ix4-300d.dtb \ ++ armada-xp-linksys-mamba.dtb \ + armada-xp-matrix.dtb \ + armada-xp-netgear-rn2120.dtb \ + armada-xp-openblocks-ax3-4.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -0,0 +1,348 @@ ++/* ++ * Device Tree file for the Linksys WRT1900AC (Mamba). ++ * ++ * Note: this board is shipped with a new generation boot loader that ++ * remaps internal registers at 0xf1000000. Therefore, if earlyprintk ++ * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be ++ * used. ++ * ++ * Copyright (C) 2014 Imre Kaloz ++ * ++ * Based on armada-xp-axpwifiap.dts: ++ * ++ * Copyright (C) 2013 Marvell ++ * ++ * Thomas Petazzoni ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without ++ * any warranty of any kind, whether express or implied. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include "armada-xp-mv78230.dtsi" ++ ++/ { ++ model = "Linksys WRT1900AC"; ++ compatible = "linksys,mamba", "marvell,armadaxp-mv78230", ++ "marvell,armadaxp", "marvell,armada-370-xp"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ stdout-path = &uart0; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */ ++ }; ++ ++ soc { ++ ranges = ; ++ ++ pcie-controller { ++ status = "okay"; ++ ++ /* Etron EJ168 USB 3.0 controller */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ /* First mini-PCIe port */ ++ pcie@2,0 { ++ /* Port 0, Lane 1 */ ++ status = "okay"; ++ }; ++ ++ /* Second mini-PCIe port */ ++ pcie@3,0 { ++ /* Port 0, Lane 3 */ ++ status = "okay"; ++ }; ++ }; ++ ++ internal-regs { ++ ++ /* J10: VCC, NC, RX, NC, TX, GND */ ++ serial@12000 { ++ status = "okay"; ++ }; ++ ++ sata@a0000 { ++ nr-ports = <1>; ++ status = "okay"; ++ }; ++ ++ ethernet@70000 { ++ pinctrl-0 = <&ge0_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ ethernet@74000 { ++ pinctrl-0 = <&ge1_rgmii_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ phy-mode = "rgmii-id"; ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++ }; ++ ++ /* USB part of the eSATA/USB 2.0 port */ ++ usb@50000 { ++ status = "okay"; ++ }; ++ ++ i2c@11000 { ++ status = "okay"; ++ clock-frequency = <100000>; ++ ++ tmp421@4c { ++ compatible = "ti,tmp421"; ++ reg = <0x4c>; ++ }; ++ ++ tlc59116@68 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #gpio-cells = <2>; ++ compatible = "ti,tlc59116"; ++ reg = <0x68>; ++ ++ wan_amber@0 { ++ label = "mamba:amber:wan"; ++ reg = <0x0>; ++ }; ++ ++ wan_white@1 { ++ label = "mamba:white:wan"; ++ reg = <0x1>; ++ }; ++ ++ wlan_2g@2 { ++ label = "mamba:white:wlan_2g"; ++ reg = <0x2>; ++ }; ++ ++ wlan_5g@3 { ++ label = "mamba:white:wlan_5g"; ++ reg = <0x3>; ++ }; ++ ++ esata@4 { ++ label = "mamba:white:esata"; ++ reg = <0x4>; ++ }; ++ ++ usb2@5 { ++ label = "mamba:white:usb2"; ++ reg = <0x5>; ++ }; ++ ++ usb3_1@6 { ++ label = "mamba:white:usb3_1"; ++ reg = <0x6>; ++ }; ++ ++ usb3_2@7 { ++ label = "mamba:white:usb3_2"; ++ reg = <0x7>; ++ }; ++ ++ wps_white@8 { ++ label = "mamba:white:wps"; ++ reg = <0x8>; ++ }; ++ ++ wps_amber@9 { ++ label = "mamba:amber:wps"; ++ reg = <0x9>; ++ }; ++ }; ++ }; ++ ++ nand@d0000 { ++ status = "okay"; ++ num-cs = <1>; ++ marvell,nand-keep-config; ++ marvell,nand-enable-arbiter; ++ nand-on-flash-bbt; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0000000 0x100000>; /* 1MB */ ++ read-only; ++ }; ++ ++ partition@100000 { ++ label = "u_env"; ++ reg = <0x100000 0x40000>; /* 256KB */ ++ }; ++ ++ partition@140000 { ++ label = "s_env"; ++ reg = <0x140000 0x40000>; /* 256KB */ ++ }; ++ ++ partition@900000 { ++ label = "devinfo"; ++ reg = <0x900000 0x100000>; /* 1MB */ ++ read-only; ++ }; ++ ++ /* kernel1 overlaps with rootfs1 by design */ ++ partition@a00000 { ++ label = "kernel1"; ++ reg = <0xa00000 0x2800000>; /* 40MB */ ++ }; ++ ++ partition@d00000 { ++ label = "rootfs1"; ++ reg = <0xd00000 0x2500000>; /* 37MB */ ++ }; ++ ++ /* kernel2 overlaps with rootfs2 by design */ ++ partition@3200000 { ++ label = "kernel2"; ++ reg = <0x3200000 0x2800000>; /* 40MB */ ++ }; ++ ++ partition@3500000 { ++ label = "rootfs2"; ++ reg = <0x3500000 0x2500000>; /* 37MB */ ++ }; ++ ++ /* ++ * 38MB, last MB is for the BBT, not writable ++ */ ++ partition@5a00000 { ++ label = "syscfg"; ++ reg = <0x5a00000 0x2600000>; ++ }; ++ ++ /* ++ * Unused area between "s_env" and "devinfo". ++ * Moved here because otherwise the renumbered ++ * partitions would break the bootloader ++ * supplied bootargs ++ */ ++ partition@180000 { ++ label = "unused_area"; ++ reg = <0x180000 0x780000>; /* 7.5MB */ ++ }; ++ }; ++ ++ spi0: spi@10600 { ++ status = "okay"; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "everspin,mr25h256"; ++ reg = <0>; /* Chip select 0 */ ++ spi-max-frequency = <40000000>; ++ }; ++ }; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&keys_pin>; ++ pinctrl-names = "default"; ++ ++ button@1 { ++ label = "WPS"; ++ linux,code = ; ++ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button@2 { ++ label = "Factory Reset Button"; ++ linux,code = ; ++ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&power_led_pin>; ++ pinctrl-names = "default"; ++ ++ power { ++ label = "mamba:white:power"; ++ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ }; ++ ++ gpio_fan { ++ /* SUNON HA4010V4-0000-C99 */ ++ compatible = "gpio-fan"; ++ gpios = <&gpio0 24 0>; ++ ++ gpio-fan,speed-map = <0 0 ++ 4500 1>; ++ }; ++}; ++ ++&pinctrl { ++ ++ keys_pin: keys-pin { ++ marvell,pins = "mpp32", "mpp33"; ++ marvell,function = "gpio"; ++ }; ++ ++ power_led_pin: power-led-pin { ++ marvell,pins = "mpp40"; ++ marvell,function = "gpio"; ++ }; ++ ++ gpio_fan_pin: gpio-fan-pin { ++ marvell,pins = "mpp24"; ++ marvell,function = "gpio"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-4.0/002-add_mamba_powertables.patch b/target/linux/mvebu/patches-4.0/002-add_mamba_powertables.patch new file mode 100644 index 0000000..6b51e48 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/002-add_mamba_powertables.patch @@ -0,0 +1,103 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -84,12 +84,100 @@ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; ++ ++ mwlwifi { ++ marvell,5ghz = <0>; ++ marvell,chainmask = <4 4>; ++ marvell,powertable { ++ FCC = ++ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>, ++ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, ++ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>; ++ ++ ETSI = ++ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, ++ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>; ++ }; ++ }; + }; + + /* Second mini-PCIe port */ + pcie@3,0 { + /* Port 0, Lane 3 */ + status = "okay"; ++ ++ mwlwifi { ++ marvell,2ghz = <0>; ++ marvell,chainmask = <4 4>; ++ marvell,powertable { ++ FCC = ++ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, ++ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, ++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, ++ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, ++ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>; ++ ++ ETSI = ++ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, ++ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>; ++ }; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-4.0/003-add_mamba_switch.patch b/target/linux/mvebu/patches-4.0/003-add_mamba_switch.patch new file mode 100644 index 0000000..e43d164 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/003-add_mamba_switch.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -415,6 +415,16 @@ + gpio-fan,speed-map = <0 0 + 4500 1>; + }; ++ ++ mvsw61xx { ++ compatible = "marvell,88e6172"; ++ status = "okay"; ++ reg = <0x10>; ++ ++ mii-bus = <&mdio>; ++ cpu-port-0 = <5>; ++ cpu-port-1 = <6>; ++ }; + }; + + &pinctrl { diff --git a/target/linux/mvebu/patches-4.0/005-build_linksys_a385_dts.patch b/target/linux/mvebu/patches-4.0/005-build_linksys_a385_dts.patch new file mode 100644 index 0000000..960a9fa --- /dev/null +++ b/target/linux/mvebu/patches-4.0/005-build_linksys_a385_dts.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -621,6 +621,8 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \ + armada-375-db.dtb + dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-385-db-ap.dtb \ ++ armada-385-linksys-caiman.dtb \ ++ armada-385-linksys-cobra.dtb \ + armada-388-db.dtb \ + armada-388-gp.dtb \ + armada-388-rd.dtb diff --git a/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch b/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch new file mode 100644 index 0000000..3c4a111 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/022-ARM-mvebu-A385-AP-Enable-the-NAND-controller.patch @@ -0,0 +1,34 @@ +From 7eb1f09ec8e25aa2fc3f6fc5fc9405d9f917d503 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Thu, 11 Dec 2014 14:14:58 +0100 +Subject: [PATCH 1/2] ARM: mvebu: A385-AP: Enable the NAND controller + +The A385 AP has a 1GB NAND chip. Enable it. + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/armada-385-db-ap.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -150,6 +150,19 @@ + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; ++ ++ nfc: flash@d0000 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ num-cs = <1>; ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ marvell,nand-keep-config; ++ marvell,nand-enable-arbiter; ++ nand-on-flash-bbt; ++ }; + }; + + pcie-controller { diff --git a/target/linux/mvebu/patches-4.0/050-leds_tlc59116_document_binding.patch b/target/linux/mvebu/patches-4.0/050-leds_tlc59116_document_binding.patch new file mode 100644 index 0000000..e55eca3 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/050-leds_tlc59116_document_binding.patch @@ -0,0 +1,51 @@ +Document the binding for the TLC59116 LED driver. + +Signed-off-by: Andrew Lunn +--- + .../devicetree/bindings/leds/leds-tlc59116.txt | 40 ++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + create mode 100644 Documentation/devicetree/bindings/leds/leds-tlc59116.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/leds/leds-tlc59116.txt +@@ -0,0 +1,40 @@ ++LEDs connected to tcl59116 ++ ++Required properties ++- compatible: should be "ti,tlc59116" ++- #address-cells: must be 1 ++- #size-cells: must be 0 ++- reg: typically 0x68 ++ ++Each led is represented as a sub-node of the ti,,tlc59116. ++See Documentation/devicetree/bindings/leds/common.txt ++ ++LED sub-node properties: ++- reg: number of LED line, 0 to 15 ++- label: (optional) name of LED ++- linux,default-trigger : (optional) ++ ++Examples: ++ ++tlc59116@68 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "ti,tlc59116"; ++ reg = <0x68>; ++ ++ wan@0 { ++ label = "wrt1900ac:amber:wan"; ++ reg = <0x0>; ++ }; ++ ++ 2g@2 { ++ label = "wrt1900ac:white:2g"; ++ reg = <0x2>; ++ }; ++ ++ alive@9 { ++ label = "wrt1900ac:green:alive"; ++ reg = <0x9>; ++ linux,default_trigger = "heartbeat"; ++ }; ++}; diff --git a/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch b/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch new file mode 100644 index 0000000..31110ad --- /dev/null +++ b/target/linux/mvebu/patches-4.0/051-leds_tlc59116_add_driver.patch @@ -0,0 +1,297 @@ +The TLC59116 is an I2C bus controlled 16-channel LED driver. Each LED +output has its own 8-bit fixed-frequency PWM controller to control the +brightness of the LED. + +This is based on a driver from Belkin, but has been extensively +rewritten. + +Signed-off-by: Andrew Lunn +--- + drivers/leds/Kconfig | 8 ++ + drivers/leds/Makefile | 1 + + drivers/leds/leds-tlc59116.c | 252 +++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 261 insertions(+) + create mode 100644 drivers/leds/leds-tlc59116.c + +--- a/drivers/leds/Kconfig ++++ b/drivers/leds/Kconfig +@@ -467,6 +467,14 @@ config LEDS_TCA6507 + LED driver chips accessed via the I2C bus. + Driver support brightness control and hardware-assisted blinking. + ++config LEDS_TLC59116 ++ tristate "LED driver for TLC59116F controllers" ++ depends on LEDS_CLASS && I2C ++ select REGMAP_I2C ++ help ++ This option enables support for Texas Instruments TLC59116F ++ LED controller. ++ + config LEDS_MAX8997 + tristate "LED support for MAX8997 PMIC" + depends on LEDS_CLASS && MFD_MAX8997 +--- a/drivers/leds/Makefile ++++ b/drivers/leds/Makefile +@@ -31,6 +31,7 @@ obj-$(CONFIG_LEDS_LP8501) += leds-lp850 + obj-$(CONFIG_LEDS_LP8788) += leds-lp8788.o + obj-$(CONFIG_LEDS_LP8860) += leds-lp8860.o + obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o ++obj-$(CONFIG_LEDS_TLC59116) += leds-tlc59116.o + obj-$(CONFIG_LEDS_CLEVO_MAIL) += leds-clevo-mail.o + obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o + obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o +--- /dev/null ++++ b/drivers/leds/leds-tlc59116.c +@@ -0,0 +1,252 @@ ++/* ++ * Copyright 2014 Belkin Inc. ++ * Copyright 2014 Andrew Lunn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TLC59116_LEDS 16 ++ ++#define TLC59116_REG_MODE1 0x00 ++#define MODE1_RESPON_ADDR_MASK 0xF0 ++#define MODE1_NORMAL_MODE (0 << 4) ++#define MODE1_SPEED_MODE (1 << 4) ++ ++#define TLC59116_REG_MODE2 0x01 ++#define MODE2_DIM (0 << 5) ++#define MODE2_BLINK (1 << 5) ++#define MODE2_OCH_STOP (0 << 3) ++#define MODE2_OCH_ACK (1 << 3) ++ ++#define TLC59116_REG_PWM(x) (0x02 + (x)) ++ ++#define TLC59116_REG_GRPPWM 0x12 ++#define TLC59116_REG_GRPFREQ 0x13 ++ ++/* LED Driver Output State, determine the source that drives LED outputs */ ++#define TLC59116_REG_LEDOUT(x) (0x14 + ((x) >> 2)) ++#define TLC59116_LED_OFF 0x0 /* Output LOW */ ++#define TLC59116_LED_ON 0x1 /* Output HI-Z */ ++#define TLC59116_DIM 0x2 /* Dimming */ ++#define TLC59116_BLINK 0x3 /* Blinking */ ++#define LED_MASK 0x3 ++ ++#define ldev_to_led(c) container_of(c, struct tlc59116_led, ldev) ++#define work_to_led(work) container_of(work, struct tlc59116_led, work) ++ ++struct tlc59116_led { ++ bool active; ++ struct regmap *regmap; ++ unsigned int led_no; ++ struct led_classdev ldev; ++ struct work_struct work; ++}; ++ ++struct tlc59116_priv { ++ struct tlc59116_led leds[TLC59116_LEDS]; ++}; ++ ++static int ++tlc59116_set_mode(struct regmap *regmap, u8 mode) ++{ ++ int err; ++ u8 val; ++ ++ if ((mode != MODE2_DIM) && (mode != MODE2_BLINK)) ++ mode = MODE2_DIM; ++ ++ /* Configure MODE1 register */ ++ err = regmap_write(regmap, TLC59116_REG_MODE1, MODE1_NORMAL_MODE); ++ if (err) ++ return err; ++ ++ /* Configure MODE2 Reg */ ++ val = MODE2_OCH_STOP | mode; ++ ++ return regmap_write(regmap, TLC59116_REG_MODE2, val); ++} ++ ++static int ++tlc59116_set_led(struct tlc59116_led *led, u8 val) ++{ ++ struct regmap *regmap = led->regmap; ++ unsigned int i = (led->led_no % 4) * 2; ++ unsigned int addr = TLC59116_REG_LEDOUT(led->led_no); ++ unsigned int mask = LED_MASK << i; ++ ++ val = val << i; ++ ++ return regmap_update_bits(regmap, addr, mask, val); ++} ++ ++static void ++tlc59116_led_work(struct work_struct *work) ++{ ++ struct tlc59116_led *led = work_to_led(work); ++ struct regmap *regmap = led->regmap; ++ int err; ++ u8 pwm; ++ ++ pwm = TLC59116_REG_PWM(led->led_no); ++ err = regmap_write(regmap, pwm, led->ldev.brightness); ++ if (err) ++ dev_err(led->ldev.dev, "Failed setting brightness\n"); ++} ++ ++static void ++tlc59116_led_set(struct led_classdev *led_cdev, enum led_brightness value) ++{ ++ struct tlc59116_led *led = ldev_to_led(led_cdev); ++ ++ led->ldev.brightness = value; ++ schedule_work(&led->work); ++} ++ ++static void ++tlc59116_destroy_devices(struct tlc59116_priv *priv, unsigned int i) ++{ ++ while (--i >= 0) { ++ if (priv->leds[i].active) { ++ led_classdev_unregister(&priv->leds[i].ldev); ++ cancel_work_sync(&priv->leds[i].work); ++ } ++ } ++} ++ ++static int ++tlc59116_configure(struct device *dev, ++ struct tlc59116_priv *priv, ++ struct regmap *regmap) ++{ ++ unsigned int i; ++ int err = 0; ++ ++ tlc59116_set_mode(regmap, MODE2_DIM); ++ for (i = 0; i < TLC59116_LEDS; i++) { ++ struct tlc59116_led *led = &priv->leds[i]; ++ ++ if (!led->active) ++ continue; ++ ++ led->regmap = regmap; ++ led->led_no = i; ++ led->ldev.brightness_set = tlc59116_led_set; ++ led->ldev.max_brightness = LED_FULL; ++ INIT_WORK(&led->work, tlc59116_led_work); ++ err = led_classdev_register(dev, &led->ldev); ++ if (err < 0) { ++ dev_err(dev, "couldn't register LED %s\n", ++ led->ldev.name); ++ goto exit; ++ } ++ tlc59116_set_led(led, TLC59116_DIM); ++ } ++ ++ return 0; ++ ++exit: ++ tlc59116_destroy_devices(priv, i); ++ return err; ++} ++ ++static const struct regmap_config tlc59116_regmap = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ .max_register = 0x1e, ++}; ++ ++static int ++tlc59116_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct tlc59116_priv *priv = i2c_get_clientdata(client); ++ struct device *dev = &client->dev; ++ struct device_node *np = client->dev.of_node, *child; ++ struct regmap *regmap; ++ int err, count, reg; ++ ++ count = of_get_child_count(np); ++ if (!count || count > TLC59116_LEDS) ++ return -EINVAL; ++ ++ if (!i2c_check_functionality(client->adapter, ++ I2C_FUNC_SMBUS_BYTE_DATA)) ++ return -EIO; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ regmap = devm_regmap_init_i2c(client, &tlc59116_regmap); ++ if (IS_ERR(regmap)) { ++ err = PTR_ERR(regmap); ++ dev_err(dev, "Failed to allocate register map: %d\n", err); ++ return err; ++ } ++ ++ i2c_set_clientdata(client, priv); ++ ++ for_each_child_of_node(np, child) { ++ err = of_property_read_u32(child, "reg", ®); ++ if (err) ++ return err; ++ if (reg < 0 || reg >= TLC59116_LEDS) ++ return -EINVAL; ++ if (priv->leds[reg].active) ++ return -EINVAL; ++ priv->leds[reg].active = true; ++ priv->leds[reg].ldev.name = ++ of_get_property(child, "label", NULL) ? : child->name; ++ priv->leds[reg].ldev.default_trigger = ++ of_get_property(child, "linux,default-trigger", NULL); ++ } ++ return tlc59116_configure(dev, priv, regmap); ++} ++ ++static int ++tlc59116_remove(struct i2c_client *client) ++{ ++ struct tlc59116_priv *priv = i2c_get_clientdata(client); ++ ++ tlc59116_destroy_devices(priv, TLC59116_LEDS); ++ ++ return 0; ++} ++ ++static const struct of_device_id of_tlc59116_leds_match[] = { ++ { .compatible = "ti,tlc59116", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, of_tlc59116_leds_match); ++ ++static const struct i2c_device_id tlc59116_id[] = { ++ { "tlc59116" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(i2c, tlc59116_id); ++ ++static struct i2c_driver tlc59116_driver = { ++ .driver = { ++ .name = "tlc59116", ++ .of_match_table = of_match_ptr(of_tlc59116_leds_match), ++ }, ++ .probe = tlc59116_probe, ++ .remove = tlc59116_remove, ++ .id_table = tlc59116_id, ++}; ++ ++module_i2c_driver(tlc59116_driver); ++ ++MODULE_AUTHOR("Andrew Lunn "); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("TLC59116 LED driver"); diff --git a/target/linux/mvebu/patches-4.0/100-find_active_root.patch b/target/linux/mvebu/patches-4.0/100-find_active_root.patch new file mode 100644 index 0000000..e32b608 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/100-find_active_root.patch @@ -0,0 +1,61 @@ +The WRT1900AC among other Linksys routers uses a dual-firmware layout. +Dynamically rename the active partition to "ubi". + +Signed-off-by: Imre Kaloz + +--- a/drivers/mtd/ofpart.c ++++ b/drivers/mtd/ofpart.c +@@ -25,12 +25,15 @@ static bool node_has_compatible(struct d + return of_get_property(pp, "compatible", NULL); + } + ++static int mangled_rootblock; ++ + static int parse_ofpart_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + struct mtd_part_parser_data *data) + { + struct device_node *node; + const char *partname; ++ const char *owrtpart = "ubi"; + struct device_node *pp; + int nr_parts, i; + +@@ -78,9 +81,15 @@ static int parse_ofpart_partitions(struc + (*pparts)[i].offset = of_read_number(reg, a_cells); + (*pparts)[i].size = of_read_number(reg + a_cells, s_cells); + +- partname = of_get_property(pp, "label", &len); +- if (!partname) +- partname = of_get_property(pp, "name", &len); ++ if (mangled_rootblock && (i == mangled_rootblock)) { ++ partname = owrtpart; ++ } else { ++ partname = of_get_property(pp, "label", &len); ++ ++ if (!partname) ++ partname = of_get_property(pp, "name", &len); ++ } ++ + (*pparts)[i].name = partname; + + if (of_get_property(pp, "read-only", &len)) +@@ -178,6 +187,18 @@ static int __init ofpart_parser_init(voi + return 0; + } + ++static int __init active_root(char *str) ++{ ++ get_option(&str, &mangled_rootblock); ++ ++ if (!mangled_rootblock) ++ return 1; ++ ++ return 1; ++} ++ ++__setup("mangled_rootblock=", active_root); ++ + static void __exit ofpart_parser_exit(void) + { + deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch b/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch new file mode 100644 index 0000000..42ee3b4 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/102-revert_i2c_delay.patch @@ -0,0 +1,15 @@ +--- a/arch/arm/boot/dts/armada-xp.dtsi ++++ b/arch/arm/boot/dts/armada-xp.dtsi +@@ -88,12 +88,10 @@ + }; + + i2c0: i2c@11000 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; + }; + + i2c1: i2c@11100 { +- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; + }; + diff --git a/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch b/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch new file mode 100644 index 0000000..f1b8688 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/202-gpio_mvebu_add_limited_pwm_support.patch @@ -0,0 +1,433 @@ +Armada 370/XP devices can 'blink' gpio lines with a configurable on +and off period. This can be modelled as a PWM. + +However, there are only two sets of PWM configuration registers for +all the gpio lines. This driver simply allows a single gpio line per +gpio chip of 32 lines to be used as a PWM. Attempts to use more return +EBUSY. + +Due to the interleaving of registers it is not simple to separate the +PWM driver from the gpio driver. Thus the gpio driver has been +extended with a PWM driver. + +Signed-off-by: Andrew Lunn +--- + drivers/gpio/Kconfig | 5 ++ + drivers/gpio/Makefile | 1 + + drivers/gpio/gpio-mvebu-pwm.c | 202 ++++++++++++++++++++++++++++++++++++++++++ + drivers/gpio/gpio-mvebu.c | 37 +++----- + drivers/gpio/gpio-mvebu.h | 79 +++++++++++++++++ + 5 files changed, 299 insertions(+), 25 deletions(-) + create mode 100644 drivers/gpio/gpio-mvebu-pwm.c + create mode 100644 drivers/gpio/gpio-mvebu.h + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -246,6 +246,11 @@ config GPIO_MVEBU + select GPIO_GENERIC + select GENERIC_IRQ_CHIP + ++config GPIO_MVEBU_PWM ++ def_bool y ++ depends on GPIO_MVEBU ++ depends on PWM ++ + config GPIO_MXC + def_bool y + depends on ARCH_MXC +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -61,6 +61,7 @@ obj-$(CONFIG_GPIO_MSIC) += gpio-msic.o + obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o + obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o + obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o ++obj-$(CONFIG_GPIO_MVEBU_PWM) += gpio-mvebu-pwm.o + obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o + obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o + obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o +--- /dev/null ++++ b/drivers/gpio/gpio-mvebu-pwm.c +@@ -0,0 +1,202 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "gpio-mvebu.h" ++#include "gpiolib.h" ++ ++static void __iomem *mvebu_gpioreg_blink_select(struct mvebu_gpio_chip *mvchip) ++{ ++ return mvchip->membase + GPIO_BLINK_CNT_SELECT; ++} ++ ++static inline struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) ++{ ++ return container_of(chip, struct mvebu_pwm, chip); ++} ++ ++static inline struct mvebu_gpio_chip *to_mvchip(struct mvebu_pwm *pwm) ++{ ++ return container_of(pwm, struct mvebu_gpio_chip, pwm); ++} ++ ++static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ struct gpio_desc *desc = gpio_to_desc(pwmd->pwm); ++ unsigned long flags; ++ int ret = 0; ++ ++ spin_lock_irqsave(&pwm->lock, flags); ++ if (pwm->used) { ++ ret = -EBUSY; ++ } else { ++ if (!desc) { ++ ret = -ENODEV; ++ goto out; ++ } ++ ret = gpiod_request(desc, "mvebu-pwm"); ++ if (ret) ++ goto out; ++ ++ ret = gpiod_direction_output(desc, 0); ++ if (ret) { ++ gpiod_free(desc); ++ goto out; ++ } ++ ++ pwm->pin = pwmd->pwm - mvchip->chip.base; ++ pwm->used = true; ++ } ++ ++out: ++ spin_unlock_irqrestore(&pwm->lock, flags); ++ return ret; ++} ++ ++static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct gpio_desc *desc = gpio_to_desc(pwmd->pwm); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&pwm->lock, flags); ++ gpiod_free(desc); ++ pwm->used = false; ++ spin_unlock_irqrestore(&pwm->lock, flags); ++} ++ ++static int mvebu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwmd, ++ int duty_ns, int period_ns) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ unsigned int on, off; ++ unsigned long long val; ++ u32 u; ++ ++ val = (unsigned long long) pwm->clk_rate * duty_ns; ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ on = val; ++ else ++ on = 1; ++ ++ val = (unsigned long long) pwm->clk_rate * (period_ns - duty_ns); ++ do_div(val, NSEC_PER_SEC); ++ if (val > UINT_MAX) ++ return -EINVAL; ++ if (val) ++ off = val; ++ else ++ off = 1; ++ ++ u = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ u &= ~(1 << pwm->pin); ++ u |= (pwm->id << pwm->pin); ++ writel_relaxed(u, mvebu_gpioreg_blink_select(mvchip)); ++ ++ writel_relaxed(on, pwm->membase + BLINK_ON_DURATION); ++ writel_relaxed(off, pwm->membase + BLINK_OFF_DURATION); ++ ++ return 0; ++} ++ ++static int mvebu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ ++ mvebu_gpio_blink(&mvchip->chip, pwm->pin, 1); ++ ++ return 0; ++} ++ ++static void mvebu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwmd) ++{ ++ struct mvebu_pwm *pwm = to_mvebu_pwm(chip); ++ struct mvebu_gpio_chip *mvchip = to_mvchip(pwm); ++ ++ mvebu_gpio_blink(&mvchip->chip, pwm->pin, 0); ++} ++ ++static const struct pwm_ops mvebu_pwm_ops = { ++ .request = mvebu_pwm_request, ++ .free = mvebu_pwm_free, ++ .config = mvebu_pwm_config, ++ .enable = mvebu_pwm_enable, ++ .disable = mvebu_pwm_disable, ++ .owner = THIS_MODULE, ++}; ++ ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ ++ pwm->blink_select = readl_relaxed(mvebu_gpioreg_blink_select(mvchip)); ++ pwm->blink_on_duration = ++ readl_relaxed(pwm->membase + BLINK_ON_DURATION); ++ pwm->blink_off_duration = ++ readl_relaxed(pwm->membase + BLINK_OFF_DURATION); ++} ++ ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ ++ writel_relaxed(pwm->blink_select, mvebu_gpioreg_blink_select(mvchip)); ++ writel_relaxed(pwm->blink_on_duration, ++ pwm->membase + BLINK_ON_DURATION); ++ writel_relaxed(pwm->blink_off_duration, ++ pwm->membase + BLINK_OFF_DURATION); ++} ++ ++/* ++ * Armada 370/XP has simple PWM support for gpio lines. Other SoCs ++ * don't have this hardware. So if we don't have the necessary ++ * resource, it is not an error. ++ */ ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ struct device *dev = &pdev->dev; ++ struct mvebu_pwm *pwm = &mvchip->pwm; ++ struct resource *res; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); ++ if (!res) ++ return 0; ++ ++ mvchip->pwm.membase = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(mvchip->pwm.membase)) ++ return PTR_ERR(mvchip->percpu_membase); ++ ++ if (id < 0 || id > 1) ++ return -EINVAL; ++ pwm->id = id; ++ ++ if (IS_ERR(mvchip->clk)) ++ return PTR_ERR(mvchip->clk); ++ ++ pwm->clk_rate = clk_get_rate(mvchip->clk); ++ if (!pwm->clk_rate) { ++ dev_err(dev, "failed to get clock rate\n"); ++ return -EINVAL; ++ } ++ ++ pwm->chip.dev = dev; ++ pwm->chip.ops = &mvebu_pwm_ops; ++ pwm->chip.base = mvchip->chip.base; ++ pwm->chip.npwm = mvchip->chip.ngpio; ++ pwm->chip.can_sleep = false; ++ ++ spin_lock_init(&pwm->lock); ++ ++ return pwmchip_add(&pwm->chip); ++} +--- a/drivers/gpio/gpio-mvebu.c ++++ b/drivers/gpio/gpio-mvebu.c +@@ -42,10 +42,11 @@ + #include + #include + #include ++#include + #include + #include + #include +- ++#include "gpio-mvebu.h" + /* + * GPIO unit register offsets. + */ +@@ -75,24 +76,6 @@ + + #define MVEBU_MAX_GPIO_PER_BANK 32 + +-struct mvebu_gpio_chip { +- struct gpio_chip chip; +- spinlock_t lock; +- void __iomem *membase; +- void __iomem *percpu_membase; +- int irqbase; +- struct irq_domain *domain; +- int soc_variant; +- +- /* Used to preserve GPIO registers across suspend/resume */ +- u32 out_reg; +- u32 io_conf_reg; +- u32 blink_en_reg; +- u32 in_pol_reg; +- u32 edge_mask_regs[4]; +- u32 level_mask_regs[4]; +-}; +- + /* + * Functions returning addresses of individual registers for a given + * GPIO controller. +@@ -228,7 +211,7 @@ static int mvebu_gpio_get(struct gpio_ch + return (u >> pin) & 1; + } + +-static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) ++void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) + { + struct mvebu_gpio_chip *mvchip = + container_of(chip, struct mvebu_gpio_chip, chip); +@@ -617,6 +600,8 @@ static int mvebu_gpio_suspend(struct pla + BUG(); + } + ++ mvebu_pwm_suspend(mvchip); ++ + return 0; + } + +@@ -660,6 +645,8 @@ static int mvebu_gpio_resume(struct plat + BUG(); + } + ++ mvebu_pwm_resume(mvchip); ++ + return 0; + } + +@@ -671,7 +658,6 @@ static int mvebu_gpio_probe(struct platf + struct resource *res; + struct irq_chip_generic *gc; + struct irq_chip_type *ct; +- struct clk *clk; + unsigned int ngpios; + int soc_variant; + int i, cpu, id; +@@ -701,10 +687,10 @@ static int mvebu_gpio_probe(struct platf + return id; + } + +- clk = devm_clk_get(&pdev->dev, NULL); ++ mvchip->clk = devm_clk_get(&pdev->dev, NULL); + /* Not all SoCs require a clock.*/ +- if (!IS_ERR(clk)) +- clk_prepare_enable(clk); ++ if (!IS_ERR(mvchip->clk)) ++ clk_prepare_enable(mvchip->clk); + + mvchip->soc_variant = soc_variant; + mvchip->chip.label = dev_name(&pdev->dev); +@@ -838,7 +824,8 @@ static int mvebu_gpio_probe(struct platf + goto err_generic_chip; + } + +- return 0; ++ /* Armada 370/XP has simple PWM support for gpio lines */ ++ return mvebu_pwm_probe(pdev, mvchip, id); + + err_generic_chip: + irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, +--- /dev/null ++++ b/drivers/gpio/gpio-mvebu.h +@@ -0,0 +1,79 @@ ++/* ++ * Interface between MVEBU GPIO driver and PWM driver for GPIO pins ++ * ++ * Copyright (C) 2015, Andrew Lunn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef MVEBU_GPIO_PWM_H ++#define MVEBU_GPIO_PWM_H ++ ++#define BLINK_ON_DURATION 0x0 ++#define BLINK_OFF_DURATION 0x4 ++#define GPIO_BLINK_CNT_SELECT 0x0020 ++ ++struct mvebu_pwm { ++ void __iomem *membase; ++ unsigned long clk_rate; ++ bool used; ++ unsigned pin; ++ struct pwm_chip chip; ++ int id; ++ spinlock_t lock; ++ ++ /* Used to preserve GPIO/PWM registers across suspend / ++ * resume */ ++ u32 blink_select; ++ u32 blink_on_duration; ++ u32 blink_off_duration; ++}; ++ ++struct mvebu_gpio_chip { ++ struct gpio_chip chip; ++ spinlock_t lock; ++ void __iomem *membase; ++ void __iomem *percpu_membase; ++ int irqbase; ++ struct irq_domain *domain; ++ int soc_variant; ++ struct clk *clk; ++#ifdef CONFIG_PWM ++ struct mvebu_pwm pwm; ++#endif ++ /* Used to preserve GPIO registers across suspend/resume */ ++ u32 out_reg; ++ u32 io_conf_reg; ++ u32 blink_en_reg; ++ u32 in_pol_reg; ++ u32 edge_mask_regs[4]; ++ u32 level_mask_regs[4]; ++}; ++ ++void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value); ++ ++#ifdef CONFIG_PWM ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id); ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip); ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip); ++#else ++int mvebu_pwm_probe(struct platform_device *pdev, ++ struct mvebu_gpio_chip *mvchip, ++ int id) ++{ ++ return 0; ++} ++ ++void mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) ++{ ++} ++ ++void mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) ++{ ++} ++#endif ++#endif diff --git a/target/linux/mvebu/patches-4.0/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch b/target/linux/mvebu/patches-4.0/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch new file mode 100644 index 0000000..48f9394 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/203-dt_bindings_extend_mvebu_gpio_documentation_with_pwm.patch @@ -0,0 +1,52 @@ +Document the optional parameters needed for PWM operation of gpio +lines. + +Signed-off-by: Andrew Lunn +--- + .../devicetree/bindings/gpio/gpio-mvebu.txt | 31 ++++++++++++++++++++++ + 1 file changed, 31 insertions(+) + +--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt ++++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt +@@ -38,6 +38,23 @@ Required properties: + - #gpio-cells: Should be two. The first cell is the pin number. The + second cell is reserved for flags, unused at the moment. + ++Optional properties: ++ ++In order to use the gpio lines in PWM mode, some additional optional ++properties are required. Only Armada 370 and XP supports these ++properties. ++ ++- reg: an additional register set is needed, for the GPIO Blink ++ Counter on/off registers. ++ ++- reg-names: Must contain an entry "pwm" corresponding to the ++ additional register range needed for pwm operation. ++ ++- #pwm-cells: Should be two. The first cell is the pin number. The ++ second cell is reserved for flags, unused at the moment. ++ ++- clocks: Must be a phandle to the clock for the gpio controller. ++ + Example: + + gpio0: gpio@d0018100 { +@@ -51,3 +68,17 @@ Example: + #interrupt-cells = <2>; + interrupts = <16>, <17>, <18>, <19>; + }; ++ ++ gpio1: gpio@18140 { ++ compatible = "marvell,orion-gpio"; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; ++ ngpios = <17>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ #pwm-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; ++ }; diff --git a/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch b/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch new file mode 100644 index 0000000..dff29dc --- /dev/null +++ b/target/linux/mvebu/patches-4.0/204-mvebu_xp_add_pwm_properties_to_dtsi_files.patch @@ -0,0 +1,149 @@ +Add properties to the gpio nodes to allow them to be also used +as pwm lines. + +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-370.dtsi | 10 ++++++++-- + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 10 ++++++++-- + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 8 ++++++-- + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 10 ++++++++-- + 4 files changed, 30 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -157,24 +157,30 @@ + + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -203,24 +203,30 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <17>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>; ++ clocks = <&coreclk 0>; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -287,24 +287,28 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -325,24 +325,30 @@ + internal-regs { + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; +- reg = <0x18100 0x40>; ++ reg = <0x18100 0x40>, <0x181c0 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <82>, <83>, <84>, <85>; ++ clocks = <&coreclk 0>; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; +- reg = <0x18140 0x40>; ++ reg = <0x18140 0x40>, <0x181c8 0x08>; ++ reg-names = "gpio", "pwm"; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; ++ #pwm-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <87>, <88>, <89>, <90>; ++ clocks = <&coreclk 0>; + }; + + gpio2: gpio@18180 { diff --git a/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch b/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch new file mode 100644 index 0000000..4b52ac2 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/205-arm_mvebu_enable_pwm_in_defconfig.patch @@ -0,0 +1,18 @@ +Now that the gpio driver also supports PWM operation, enable +the PWM framework in mvebu_v7_defconfig. + +Signed-off-by: Andrew Lunn +--- + arch/arm/configs/mvebu_v7_defconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/configs/mvebu_v7_defconfig ++++ b/arch/arm/configs/mvebu_v7_defconfig +@@ -118,6 +118,7 @@ CONFIG_DMADEVICES=y + CONFIG_MV_XOR=y + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_MEMORY=y ++CONFIG_PWM=y + CONFIG_EXT4_FS=y + CONFIG_ISO9660_FS=y + CONFIG_JOLIET=y diff --git a/target/linux/mvebu/patches-4.0/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch b/target/linux/mvebu/patches-4.0/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch new file mode 100644 index 0000000..dddd67a --- /dev/null +++ b/target/linux/mvebu/patches-4.0/206-mvebu_wrt1900ac_use_pwm-fan_rather_than_gpio-fan.patch @@ -0,0 +1,28 @@ +The mvebu gpio driver can also perform PWM on some pins. Us the +pwm-fan driver to control the fan of the WRT1900AC, giving us fine +grain control over its speed and hence noise. + +Signed-off-by: Andrew Lunn +--- + arch/arm/boot/dts/armada-xp-wrt1900ac.dts | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts ++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +@@ -407,13 +407,11 @@ + }; + }; + +- gpio_fan { ++ pwm_fan { + /* SUNON HA4010V4-0000-C99 */ +- compatible = "gpio-fan"; +- gpios = <&gpio0 24 0>; + +- gpio-fan,speed-map = <0 0 +- 4500 1>; ++ compatible = "pwm-fan"; ++ pwms = <&gpio0 24 4000 0>; + }; + + mvsw61xx { diff --git a/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch new file mode 100644 index 0000000..51408dd --- /dev/null +++ b/target/linux/mvebu/patches-4.0/207-armada-385-rd-mtd-partitions.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/boot/dts/armada-388-rd.dts ++++ b/arch/arm/boot/dts/armada-388-rd.dts +@@ -77,6 +77,16 @@ + compatible = "st,m25p128"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; ++ ++ partition@0 { ++ label = "uboot"; ++ reg = <0 0x400000>; ++ }; ++ ++ partition@1 { ++ label = "firmware"; ++ reg = <0x400000 0xc00000>; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch new file mode 100644 index 0000000..2845181 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/208-ARM-mvebu-385-ap-Add-partitions.patch @@ -0,0 +1,34 @@ +From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001 +From: Maxime Ripard +Date: Tue, 13 Jan 2015 11:14:09 +0100 +Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm/boot/dts/armada-385-db-ap.dts ++++ b/arch/arm/boot/dts/armada-385-db-ap.dts +@@ -162,6 +162,21 @@ + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; ++ ++ mtd0@00000000 { ++ label = "u-boot"; ++ reg = <0x00000000 0x00800000>; ++ }; ++ ++ mtd1@00800000 { ++ label = "kernel"; ++ reg = <0x00800000 0x00800000>; ++ }; ++ ++ mtd2@01000000 { ++ label = "ubi"; ++ reg = <0x01000000 0x3f000000>; ++ }; + }; + }; + diff --git a/target/linux/mvebu/patches-4.0/300-add_missing_labels.patch b/target/linux/mvebu/patches-4.0/300-add_missing_labels.patch new file mode 100644 index 0000000..a34f689 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/300-add_missing_labels.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/armada-38x.dtsi ++++ b/arch/arm/boot/dts/armada-38x.dtsi +@@ -491,7 +491,7 @@ + status = "disabled"; + }; + +- mdio@72004 { ++ mdio: mdio@72004 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; diff --git a/target/linux/mvebu/patches-4.0/700-usb_xhci_plat_phy_support.patch b/target/linux/mvebu/patches-4.0/700-usb_xhci_plat_phy_support.patch new file mode 100644 index 0000000..a315b87 --- /dev/null +++ b/target/linux/mvebu/patches-4.0/700-usb_xhci_plat_phy_support.patch @@ -0,0 +1,47 @@ +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -155,12 +156,27 @@ static int xhci_plat_probe(struct platfo + if (HCC_MAX_PSA(xhci->hcc_params) >= 4) + xhci->shared_hcd->can_do_streams = 1; + ++ hcd->usb_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "usb-phy", 0); ++ if (IS_ERR(hcd->usb_phy)) { ++ ret = PTR_ERR(hcd->usb_phy); ++ if (ret == -EPROBE_DEFER) ++ goto put_usb3_hcd; ++ hcd->usb_phy = NULL; ++ } else { ++ ret = usb_phy_init(hcd->usb_phy); ++ if (ret) ++ goto put_usb3_hcd; ++ } ++ + ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); + if (ret) +- goto put_usb3_hcd; ++ goto disable_usb_phy; + + return 0; + ++disable_usb_phy: ++ usb_phy_shutdown(hcd->usb_phy); ++ + put_usb3_hcd: + usb_put_hcd(xhci->shared_hcd); + +@@ -184,6 +200,7 @@ static int xhci_plat_remove(struct platf + struct clk *clk = xhci->clk; + + usb_remove_hcd(xhci->shared_hcd); ++ usb_phy_shutdown(hcd->usb_phy); + usb_put_hcd(xhci->shared_hcd); + + usb_remove_hcd(hcd); diff --git a/target/linux/mvebu/profiles/000-Default.mk b/target/linux/mvebu/profiles/000-Default.mk new file mode 100644 index 0000000..5660836 --- /dev/null +++ b/target/linux/mvebu/profiles/000-Default.mk @@ -0,0 +1,26 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (all drivers) + PACKAGES:= \ + kmod-mmc kmod-mvsdio swconfig \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-hwmon-pwmfan kmod-leds-tlc59116 \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + kmod-ata-mvebu-ahci +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef + +$(eval $(call Profile,Default)) diff --git a/target/linux/mvebu/profiles/globalscale.mk b/target/linux/mvebu/profiles/globalscale.mk new file mode 100644 index 0000000..7938c35 --- /dev/null +++ b/target/linux/mvebu/profiles/globalscale.mk @@ -0,0 +1,21 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Mirabox + NAME:=Globalscale Mirabox + PACKAGES:= \ + kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-rtc-marvell kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-mmc kmod-mvsdio +endef + +define Profile/Mirabox/Description + Package set compatible with the Globalscale Mirabox. +endef + +$(eval $(call Profile,Mirabox)) diff --git a/target/linux/mvebu/profiles/linksys.mk b/target/linux/mvebu/profiles/linksys.mk new file mode 100644 index 0000000..1a5b8af --- /dev/null +++ b/target/linux/mvebu/profiles/linksys.mk @@ -0,0 +1,85 @@ +# +# Copyright (C) 2013-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Caiman + NAME:=Linksys WRT1200AC (Caiman) + PACKAGES:= \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-mvebu-ahci \ + kmod-rtc-armada38x kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-leds-pca963x \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + swconfig +endef + +define Profile/Caiman/Description + Package set compatible with the Linksys WRT1200AC (Caiman). +endef + +$(eval $(call Profile,Caiman)) + + +define Profile/Cobra + NAME:=Linksys WRT1900ACv2 (Cobra) + PACKAGES:= \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-mvebu-ahci \ + kmod-rtc-armada38x kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-leds-pca963x \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + swconfig +endef + +define Profile/Cobra/Description + Package set compatible with the Linksys WRT1900AC (Cobra). +endef + +$(eval $(call Profile,Cobra)) + + +define Profile/Mamba + NAME:=Linksys WRT1900AC (Mamba) + PACKAGES:= \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-hwmon-pwmfan kmod-leds-tlc59116 \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + swconfig +endef + +define Profile/Mamba/Description + Package set compatible with the Linksys WRT1900AC (Mamba). +endef + +$(eval $(call Profile,Mamba)) + + +define Profile/Shelby + NAME:=Linksys WRT1900ACS (Shelby) + PACKAGES:= \ + kmod-usb2 kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-mvebu-ahci \ + kmod-rtc-armada38x kmod-thermal-armada \ + kmod-gpio-button-hotplug kmod-hwmon-tmp421 \ + kmod-leds-pca963x \ + kmod-ledtrig-usbdev kmod-mwlwifi wpad-mini \ + swconfig +endef + +define Profile/Shelby/Description + Package set compatible with the Linksys WRT1900ACS (Shelby). +endef + +$(eval $(call Profile,Shelby)) diff --git a/target/linux/mvebu/profiles/marvell.mk b/target/linux/mvebu/profiles/marvell.mk new file mode 100644 index 0000000..e8ca9bd --- /dev/null +++ b/target/linux/mvebu/profiles/marvell.mk @@ -0,0 +1,95 @@ +# +# Copyright (C) 2013-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/370-DB + NAME:=Marvell Armada 370 DB (DB-88F6710-BP-DDR3) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/370-DB/Description + Package set compatible with the Armada 370 evaluation board (DB-88F6710-BP-DDR3). +endef + +$(eval $(call Profile,370-DB)) + +define Profile/370-RD + NAME:=Marvell Armada 370 RD (RD-88F6710-A1) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/370-RD/Description + Package set compatible with the Armada 370 reference design board (RD-88F6710-A1). +endef + +$(eval $(call Profile,370-RD)) + +define Profile/385-RD + NAME:=Marvell Armada 385 RD (RD-88F6820-AP) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-thermal-armada +endef + +define Profile/385-RD/Description + Package set compatible with the Armada 385 reference design board (RD-88F6820-AP). +endef + +$(eval $(call Profile,385-RD)) + +define Profile/385-DB-AP + NAME:=Marvell Armada 385 DB AP (DB-88F6820-AP) + PACKAGES:= \ + kmod-usb3 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-thermal-armada +endef + +define Profile/385-DB-AP/Description + Package set compatible with the Armada 385 access point development board (DB-88F6820-AP). +endef + +$(eval $(call Profile,385-DB-AP)) + +define Profile/XP-DB + NAME:=Marvell Armada XP DB (DB-78460-BP) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/XP-DB/Description + Package set compatible with the Marvell Armada XP evaluation board (DB-78460-BP). +endef + +$(eval $(call Profile,XP-DB)) + +define Profile/XP-GP + NAME:=Marvell Armada XP GP (DB-MV784MP-GP) + PACKAGES:= \ + kmod-mmc kmod-mvsdio kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/XP-GP/Description + Package set compatible with the Armada XP development board (DB-MV784MP-GP). +endef + +$(eval $(call Profile,XP-GP)) diff --git a/target/linux/mvebu/profiles/plathome.mk b/target/linux/mvebu/profiles/plathome.mk new file mode 100644 index 0000000..63cdb71 --- /dev/null +++ b/target/linux/mvebu/profiles/plathome.mk @@ -0,0 +1,21 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/OpenBlocks-AX-3-4 + NAME:=Plat'Home OpenBlocks AX3 + PACKAGES:= \ + kmod-usb2 kmod-usb-storage \ + kmod-i2c-core kmod-i2c-mv64xxx \ + kmod-ata-core kmod-ata-marvell-sata \ + kmod-rtc-marvell kmod-thermal-armada +endef + +define Profile/OpenBlocks-AX-3-4/Description + Package set compatible with the Plat'Home OpenBlocks AX3. +endef + +$(eval $(call Profile,OpenBlocks-AX-3-4)) diff --git a/target/linux/mxs/Makefile b/target/linux/mxs/Makefile new file mode 100644 index 0000000..91cab96 --- /dev/null +++ b/target/linux/mxs/Makefile @@ -0,0 +1,27 @@ +# +# Copyright (C) 2013-2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=mxs +BOARDNAME:=Freescale i.MX23/i.MX28 +FEATURES:=ext4 rtc usb gpio +CPU_TYPE:=arm926ej-s + +MAINTAINER:=Zoltan HERPAI +KERNEL_PATCHVER:=4.1 +KERNELNAME:=zImage dtbs + +define Target/Description + Support for Freescale i.MX23/i.MX28 boards +endef + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += kmod-wdt-stmp3xxx + +$(eval $(call BuildTarget)) diff --git a/target/linux/mxs/base-files/etc/diag.sh b/target/linux/mxs/base-files/etc/diag.sh new file mode 100644 index 0000000..11b1f75 --- /dev/null +++ b/target/linux/mxs/base-files/etc/diag.sh @@ -0,0 +1,38 @@ +#!/bin/sh +# Copyright (C) 2013-2014 OpenWrt.org + +. /lib/functions/leds.sh +. /lib/mxs.sh + +get_status_led() { + case $(mxs_board_name) in + duckbill) + status_led="duckbill:green:status" + ;; + olinuxino) + status_led="green" + ;; + *) + status_led=$(cd /sys/class/leds && ls -1d *:status 2> /dev/null | head -n 1) + ;; + esac +} + +set_state() { + get_status_led + + case "$1" in + preinit) + status_led_blink_preinit + ;; + failsafe) + status_led_blink_failsafe + ;; + preinit_regular) + status_led_blink_preinit_regular + ;; + done) + status_led_on + ;; + esac +} diff --git a/target/linux/mxs/base-files/etc/inittab b/target/linux/mxs/base-files/etc/inittab new file mode 100644 index 0000000..09359b7 --- /dev/null +++ b/target/linux/mxs/base-files/etc/inittab @@ -0,0 +1,3 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttyAMA0::askfirst:/bin/ash --login diff --git a/target/linux/mxs/base-files/etc/uci-defaults/02_network b/target/linux/mxs/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..246cd89 --- /dev/null +++ b/target/linux/mxs/base-files/etc/uci-defaults/02_network @@ -0,0 +1,23 @@ +#!/bin/sh +# Copyright (C) 2013 OpenWrt.org + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/mxs.sh + +ucidef_set_interface_loopback + +board=$(mxs_board_name) + +case "$board" in +*) + ucidef_set_interface_lan 'eth0' + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/mxs/base-files/lib/mxs.sh b/target/linux/mxs/base-files/lib/mxs.sh new file mode 100644 index 0000000..ed5a527 --- /dev/null +++ b/target/linux/mxs/base-files/lib/mxs.sh @@ -0,0 +1,42 @@ +#!/bin/sh +# +# Copyright (C) 2013 OpenWrt.org +# + +MXS_BOARD_NAME= +MXS_MODEL= + +mxs_board_detect() { + local machine + local name + + machine=$(cat /proc/device-tree/model) + + case "$machine" in + *"I2SE Duckbill"*) + name="duckbill" + ;; + *"i.MX23 Olinuxino Low Cost Board") + name="olinuxino" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$MXS_BOARD_NAME" ] && MXS_BOARD_NAME="$name" + [ -z "$MXS_MODEL" ] && MXS_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$MXS_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$MXS_MODEL" > /tmp/sysinfo/model +} + +mxs_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/mxs/base-files/lib/preinit/03_preinit_do_mxs.sh b/target/linux/mxs/base-files/lib/preinit/03_preinit_do_mxs.sh new file mode 100644 index 0000000..692078d --- /dev/null +++ b/target/linux/mxs/base-files/lib/preinit/03_preinit_do_mxs.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_mxs() { + . /lib/mxs.sh + + mxs_board_detect +} + +boot_hook_add preinit_main do_mxs diff --git a/target/linux/mxs/config-3.18 b/target/linux/mxs/config-3.18 new file mode 100644 index 0000000..2e1f81b --- /dev/null +++ b/target/linux/mxs/config-3.18 @@ -0,0 +1,293 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_AMBA_PL08X is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_MXS=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_COREDUMP=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_DEV_MXS_DCP is not set +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HW=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +# CONFIG_DW_DMAC_CORE is not set +# CONFIG_EMAC_ROCKCHIP is not set +CONFIG_EXT4_FS=y +CONFIG_FEC=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_MBCACHE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_MXS=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCA=y +CONFIG_I2C_ALGOPCF=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_MUX=y +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +CONFIG_I2C_MUX_PINCTRL=y +# CONFIG_I2C_MXS is not set +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_PERIODIC_RTC_TRIGGER=y +CONFIG_IIO_SYSFS_TRIGGER=y +CONFIG_IIO_TRIGGER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_JBD2=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LIBFDT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_MXS=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MXS_DMA=y +# CONFIG_MXS_LRADC is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PCI is not set +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX23=y +CONFIG_PINCTRL_IMX28=y +CONFIG_PINCTRL_MXS=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PL330_DMA is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_RUNTIME=y +CONFIG_PPS=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PTP_1588_CLOCK=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_STMP is not set +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MXS_AUART=y +CONFIG_SERIAL_MXS_AUART_CONSOLE=y +CONFIG_SMSC_PHY=y +CONFIG_SOC_BUS=y +CONFIG_SOC_IMX23=y +CONFIG_SOC_IMX28=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_MXS is not set +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_STMP_DEVICE=y +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_MXS_PHY is not set +CONFIG_USB_OTG=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/mxs/config-4.1 b/target/linux/mxs/config-4.1 new file mode 100644 index 0000000..b837442 --- /dev/null +++ b/target/linux/mxs/config-4.1 @@ -0,0 +1,297 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_AMBA_PL08X is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_CPU_AUTO=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +CONFIG_ARCH_MXS=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_ARM_CPUIDLE is not set +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +CONFIG_ATAGS=y +CONFIG_AUTO_ZRELADDR=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_COREDUMP=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_DEV_MXS_DCP is not set +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HW=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +CONFIG_EXT4_FS=y +CONFIG_FEC=y +CONFIG_FRAME_POINTER=y +# CONFIG_FSL_PQ_MDIO is not set +CONFIG_FS_MBCACHE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_MXS=y +CONFIG_GPIO_SYSFS=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCA=y +CONFIG_I2C_ALGOPCF=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_MUX=y +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +CONFIG_I2C_MUX_PINCTRL=y +# CONFIG_I2C_MXS is not set +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_PERIODIC_RTC_TRIGGER=y +CONFIG_IIO_SYSFS_TRIGGER=y +CONFIG_IIO_TRIGGER=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISDN is not set +CONFIG_JBD2=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LIBFDT=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_MXS=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MXS_DMA=y +# CONFIG_MXS_LRADC is not set +CONFIG_MXS_POWER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PCI is not set +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX23=y +CONFIG_PINCTRL_IMX28=y +CONFIG_PINCTRL_MXS=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PL330_DMA is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PTP_1588_CLOCK=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MXS=y +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_STMP is not set +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_MXS_AUART=y +CONFIG_SERIAL_MXS_AUART_CONSOLE=y +CONFIG_SMSC_PHY=y +CONFIG_SOC_BUS=y +CONFIG_SOC_IMX23=y +CONFIG_SOC_IMX28=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_MXS is not set +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SRCU=y +CONFIG_STMP_DEVICE=y +CONFIG_SWIOTLB=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_MXS_PHY is not set +CONFIG_USB_OTG=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFP is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/mxs/files/arch/arm/boot/dts/imx28-duckbill.dts b/target/linux/mxs/files/arch/arm/boot/dts/imx28-duckbill.dts new file mode 100644 index 0000000..305b4d0 --- /dev/null +++ b/target/linux/mxs/files/arch/arm/boot/dts/imx28-duckbill.dts @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2013-2014 Michael Heimpold + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx28.dtsi" + +/ { + model = "I2SE Duckbill"; + compatible = "i2se,duckbill", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; + }; + + ssp2: ssp@80014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + spidev: spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins_a: led_gpio@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__GPIO_3_4 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + }; + }; + + apbx@80040000 { + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + status = "okay"; + }; + + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-supply = <®_3p3v>; + phy-reset-gpios = <&gpio2 7 1>; + phy-reset-duration = <100>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_a>; + + status { + label = "duckbill:green:status"; + gpios = <&gpio3 5 0>; + }; + + failure { + label = "duckbill:red:status"; + gpios = <&gpio3 4 0>; + }; + }; +}; diff --git a/target/linux/mxs/image/Config.in b/target/linux/mxs/image/Config.in new file mode 100644 index 0000000..250553e --- /dev/null +++ b/target/linux/mxs/image/Config.in @@ -0,0 +1,8 @@ +config TARGET_BOOTFS_PARTSIZE + int "Boot (SD Card) filesystem partition size (in MB)" + depends on TARGET_mxs_olinuxino-maxi || TARGET_mxs_olinuxino-micro + default 8 + help + On the Olimex OLinuXino boards, mainline U-Boot loads the + linux kernel and device tree file from a FAT partition. + The default value of 8 MB should be more than adequate. diff --git a/target/linux/mxs/image/Makefile b/target/linux/mxs/image/Makefile new file mode 100644 index 0000000..94fed82 --- /dev/null +++ b/target/linux/mxs/image/Makefile @@ -0,0 +1,89 @@ +# +# Copyright (C) 2013-2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +BOARDS:= \ + imx23-olinuxino \ + imx28-duckbill + +FAT32_BLOCK_SIZE=1024 +FAT32_BLOCKS=$(shell echo $$(($(CONFIG_TARGET_BOOTFS_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE)))) + +define Image/BuildKernel + mkimage -A arm -O linux -T kernel -C none \ + -a 0x40008000 -e 0x40008000 \ + -n 'ARM OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(KDIR)/zImage $(KDIR)/uImage + cp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage +endef + +define Image/InstallKernel + + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_ZIMAGE),) + mkdir -p $(TARGET_DIR)/boot + cp $(KDIR)/zImage $(TARGET_DIR)/boot/ + endif + + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_UIMAGE),) + mkdir -p $(TARGET_DIR)/boot + cp $(KDIR)/uImage $(TARGET_DIR)/boot/ + endif + + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB),) + mkdir -p $(TARGET_DIR)/boot + $(foreach board,$(BOARDS), + $(CP) $(DTS_DIR)/$(board).dtb $(TARGET_DIR)/boot/ + ) + endif + +endef + +define Image/Build/SDCard-vfat-ext4 + rm -f $(KDIR)/boot.img + mkdosfs $(KDIR)/boot.img -C $(FAT32_BLOCKS) + + mcopy -i $(KDIR)/boot.img $(DTS_DIR)/$(3).dtb ::$(3).dtb + mcopy -i $(KDIR)/boot.img $(BIN_DIR)/$(IMG_PREFIX)-uImage ::uImage + + ./gen_sdcard_vfat_ext4.sh \ + $(BIN_DIR)/$(2) \ + $(BIN_DIR)/uboot-mxs-$(4)/uboot-mxs-$(4).sb \ + $(KDIR)/boot.img \ + $(KDIR)/root.$(1) \ + $(CONFIG_TARGET_BOOTFS_PARTSIZE) \ + $(CONFIG_TARGET_ROOTFS_PARTSIZE) +endef + +define Image/Build/SDCard-ext4-ext4 + ./gen_sdcard_ext4_ext4.sh \ + $(BIN_DIR)/$(2) \ + $(BIN_DIR)/uboot-mxs-$(4)/uboot-mxs-$(4).sb \ + $(KDIR)/root.$(1) \ + $(CONFIG_TARGET_ROOTFS_PARTSIZE) +endef + +define Image/Build/Profile/olinuxino-maxi + $(call Image/Build/SDCard-vfat-ext4,$(1),$(2),imx23-olinuxino,mx23_olinuxino) +endef + +define Image/Build/Profile/olinuxino-micro + $(call Image/Build/SDCard-vfat-ext4,$(1),$(2),imx23-olinuxino,mx23_olinuxino) +endef + +define Image/Build/Profile/duckbill + $(call Image/Build/SDCard-ext4-ext4,$(1),$(2),imx28-duckbill,duckbill) +endef + +define Image/Build + $(call Image/Build/$(1),$(1)) + $(call Image/Build/Profile/$(PROFILE),$(1),$(IMG_PREFIX)-$(PROFILE)-sdcard.img) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/mxs/image/gen_sdcard_ext4_ext4.sh b/target/linux/mxs/image/gen_sdcard_ext4_ext4.sh new file mode 100755 index 0000000..5653ba8 --- /dev/null +++ b/target/linux/mxs/image/gen_sdcard_ext4_ext4.sh @@ -0,0 +1,33 @@ +#!/usr/bin/env bash +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +set -x +[ $# -eq 4 ] || { + echo "SYNTAX: $0 " + exit 1 +} + +OUTPUT="$1" +UBOOT="$2" +ROOTFS="$3" +ROOTFSSIZE="$4" + +head=4 +sect=63 + +# set the Boot stream partition size to 1M +set `ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t 53 -p 1M -t 83 -p ${ROOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M` + +ROOTFS1OFFSET="$(($3 / 512))" +ROOTFS1SIZE="$(($4 / 512))" +ROOTFS2OFFSET="$(($5 / 512))" +ROOTFS2SIZE="$(($6 / 512))" + +dd bs=512 if="$ROOTFS" of="$OUTPUT" seek="$ROOTFS1OFFSET" conv=notrunc +dd bs=512 if="$ROOTFS" of="$OUTPUT" seek="$ROOTFS2OFFSET" conv=notrunc +sdimage -d "$OUTPUT" -f "$UBOOT" diff --git a/target/linux/mxs/image/gen_sdcard_vfat_ext4.sh b/target/linux/mxs/image/gen_sdcard_vfat_ext4.sh new file mode 100755 index 0000000..616639d --- /dev/null +++ b/target/linux/mxs/image/gen_sdcard_vfat_ext4.sh @@ -0,0 +1,37 @@ +#!/usr/bin/env bash +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +set -x +[ $# -eq 6 ] || { + echo "SYNTAX: $0 " + exit 1 +} + +OUTPUT="$1" +UBOOT="$2" +BOOTFS="$3" +ROOTFS="$4" +BOOTFSSIZE="$5" +ROOTFSSIZE="$6" + +head=4 +sect=63 + +# Set the u-boot storage to 2M +set `ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t 53 -p 2M -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M` + +UBOOTOFFSET="$(($1 / 512))" +UBOOTSIZE="$(($2 / 512))" +BOOTOFFSET="$(($3 / 512))" +BOOTSIZE="$(($4 / 512))" +ROOTFSOFFSET="$(($5 / 512))" +ROOTFSSIZE="$(($6 / 512))" + +dd bs=512 if="$BOOTFS" of="$OUTPUT" seek="$BOOTOFFSET" conv=notrunc +dd bs=512 if="$ROOTFS" of="$OUTPUT" seek="$ROOTFSOFFSET" conv=notrunc +sdimage -d "$OUTPUT" -f "$UBOOT" diff --git a/target/linux/mxs/modules.mk b/target/linux/mxs/modules.mk new file mode 100644 index 0000000..d363360 --- /dev/null +++ b/target/linux/mxs/modules.mk @@ -0,0 +1,115 @@ +# +# Copyright (C) 2013-2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. + +define KernelPackage/rtc-stmp3xxx + SUBMENU:=$(OTHER_MENU) + TITLE:=STMP3xxx SoC built-in RTC support + DEPENDS:=@TARGET_mxs + $(call AddDepends/rtc) + KCONFIG:= \ + CONFIG_RTC_CLASS=y \ + CONFIG_RTC_DRV_STMP=m + FILES:=$(LINUX_DIR)/drivers/rtc/rtc-stmp3xxx.ko + AUTOLOAD:=$(call AutoLoad,50,rtc-stmp3xxx) +endef + +$(eval $(call KernelPackage,rtc-stmp3xxx)) + +define KernelPackage/wdt-stmp3xxx + SUBMENU:=$(OTHER_MENU) + TITLE:=STMP3xxx Watchdog timer + DEPENDS:=kmod-rtc-stmp3xxx + KCONFIG:=CONFIG_STMP3XXX_RTC_WATCHDOG + FILES:=$(LINUX_DIR)/drivers/$(WATCHDOG_DIR)/stmp3xxx_rtc_wdt.ko + AUTOLOAD:=$(call AutoLoad,51,stmp3xxx_rtc_wdt) +endef + +define KernelPackage/wdt-stmp3xxx/description + Kernel module for STMP3xxx watchdog timer. +endef + +$(eval $(call KernelPackage,wdt-stmp3xxx)) + +define KernelPackage/sound-soc-mxs + TITLE:=Freescale i.MX23/i.MX28 built-in SoC sound support + KCONFIG:= \ + CONFIG_SND_SOC_MXS_BUILTIN_CODEC \ + CONFIG_SND_MXS_SOC_BUILTIN + FILES:= \ + $(LINUX_DIR)/sound/soc/mxs/snd-soc-mxs-builtin-audio.ko \ + $(LINUX_DIR)/sound/soc/mxs/snd-soc-mxs-builtin-dai.ko \ + $(LINUX_DIR)/sound/soc/mxs/snd-soc-mxs-builtin-pcm.ko \ + $(LINUX_DIR)/sound/soc/codecs/snd-soc-mxs-builtin-codec.ko + AUTOLOAD:=$(call AutoLoad,65,snd-soc-mxs-builtin-pcm snd-soc-mxs-builtin-dai snd-soc-mxs-builtin-codec snd-soc-mxs-builtin-audio) + DEPENDS:=@TARGET_mxs +kmod-sound-soc-core @LINUX_3_18 + $(call AddDepends/sound) +endef + +define KernelPackage/sound-soc-mxs/description + Kernel support for Freescale i.MX23/i.MX28 built-in SoC audio +endef + +$(eval $(call KernelPackage,sound-soc-mxs)) + +define KernelPackage/iio-mxs-lradc + SUBMENU:=$(OTHER_MENU) + TITLE:=Freescale i.MX23/28 LRADC driver + DEPENDS:=@TARGET_mxs +kmod-iio-core + KCONFIG:=CONFIG_MXS_LRADC + FILES:=$(LINUX_DIR)/drivers/staging/iio/adc/mxs-lradc.ko + AUTOLOAD:=$(call AutoLoad,70,mxs-lradc) +endef + +define KernelPackage/iio-mxs-lradc/description + Kernel module for Freescale i.MX23/28 LRADC driver +endef + +$(eval $(call KernelPackage,iio-mxs-lradc)) + +define KernelPackage/crypto-hw-dcp + TITLE:=Freescale i.MX23/28 DCP hardware crypto module + DEPENDS:=@TARGET_mxs + KCONFIG:=CONFIG_CRYPTO_DEV_MXS_DCP + FILES:=$(LINUX_DIR)/drivers/crypto/mxs-dcp.ko + AUTOLOAD:=$(call AutoLoad,90,mxs-dcp) + $(call AddDepends/crypto,+kmod-crypto-authenc +kmod-crypto-des) +endef + +define KernelPackage/crypto-hw-dcp/description + Kernel support for Freescale i.MX23/28 DCP crypto engine +endef + +$(eval $(call KernelPackage,crypto-hw-dcp)) + +define KernelPackage/spi-mxs + SUBMENU:=$(SPI_MENU) + TITLE:=Freescale i.MX23/28 SPI driver + DEPENDS:=@TARGET_mxs + KCONFIG:=CONFIG_SPI_MXS + FILES:=$(LINUX_DIR)/drivers/spi/spi-mxs.ko + AUTOLOAD:=$(call AutoProbe,spi-mxs) +endef + +define KernelPackage/spi-mxs/description + Kernel module for Freescale i.MX23/28 SPI controller +endef + +$(eval $(call KernelPackage,spi-mxs)) + +I2C_MXS_MODULES:= \ + CONFIG_I2C_MXS:drivers/i2c/busses/i2c-mxs + +define KernelPackage/i2c-mxs + $(call i2c_defaults,$(I2C_MXS_MODULES),55) + TITLE:=Freescale i.MX23/28 I2C driver + DEPENDS:=@TARGET_mxs +kmod-i2c-core +endef + +define KernelPackage/i2c-mxs/description + Kernel module for Freescale i.MX23/28 I2C controller +endef + +$(eval $(call KernelPackage,i2c-mxs)) diff --git a/target/linux/mxs/patches-3.18/001-soc-audio-support.patch b/target/linux/mxs/patches-3.18/001-soc-audio-support.patch new file mode 100644 index 0000000..65c3438 --- /dev/null +++ b/target/linux/mxs/patches-3.18/001-soc-audio-support.patch @@ -0,0 +1,2866 @@ +From ef05a3ce8340c7156610b173324ab793b06e0ae2 Mon Sep 17 00:00:00 2001 +From: Michal Ulianko +Date: Mon, 29 Jul 2013 20:14:38 +0200 +Subject: [PATCH 1/2] Added ASoC driver for i.MX233's builtin ADC/DAC codec. + +--- + sound/soc/codecs/Kconfig | 4 + + sound/soc/codecs/Makefile | 2 + + sound/soc/codecs/mxs-builtin-codec.c | 1128 ++++++++++++++++++++++++++++++++++ + sound/soc/codecs/mxs-builtin-codec.h | 825 +++++++++++++++++++++++++ + sound/soc/mxs/Kconfig | 10 + + sound/soc/mxs/Makefile | 9 + + sound/soc/mxs/mxs-builtin-audio.c | 120 ++++ + sound/soc/mxs/mxs-builtin-dai.c | 588 ++++++++++++++++++ + sound/soc/mxs/mxs-builtin-pcm.c | 69 +++ + sound/soc/mxs/mxs-builtin-pcm.h | 25 + + 10 files changed, 2780 insertions(+) + create mode 100644 sound/soc/codecs/mxs-builtin-codec.c + create mode 100644 sound/soc/codecs/mxs-builtin-codec.h + create mode 100644 sound/soc/mxs/mxs-builtin-audio.c + create mode 100644 sound/soc/mxs/mxs-builtin-dai.c + create mode 100644 sound/soc/mxs/mxs-builtin-pcm.c + create mode 100644 sound/soc/mxs/mxs-builtin-pcm.h + +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -164,6 +164,7 @@ config SND_SOC_ALL_CODECS + select SND_SOC_WM9705 if SND_SOC_AC97_BUS + select SND_SOC_WM9712 if SND_SOC_AC97_BUS + select SND_SOC_WM9713 if SND_SOC_AC97_BUS ++ select SND_SOC_MXS_BUILTIN_CODEC + help + Normally ASoC codec drivers are only built if a machine driver which + uses them is also built since they are only usable with a machine +@@ -789,6 +790,9 @@ config SND_SOC_WM9712 + config SND_SOC_WM9713 + tristate + ++config SND_SOC_MXS_BUILTIN_CODEC ++ tristate ++ + # Amp + config SND_SOC_LM4857 + tristate +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -166,6 +166,7 @@ snd-soc-wm9705-objs := wm9705.o + snd-soc-wm9712-objs := wm9712.o + snd-soc-wm9713-objs := wm9713.o + snd-soc-wm-hubs-objs := wm_hubs.o ++snd-soc-mxs-builtin-codec-objs := mxs-builtin-codec.o + + # Amp + snd-soc-max9877-objs := max9877.o +@@ -339,6 +340,7 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc- + obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o + obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o + obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o ++obj-$(CONFIG_SND_SOC_MXS_BUILTIN_CODEC) += snd-soc-mxs-builtin-codec.o + + # Amp + obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o +--- /dev/null ++++ b/sound/soc/codecs/mxs-builtin-codec.c +@@ -0,0 +1,1128 @@ ++/* ++ * mxs-builtin-codec.c -- i.MX233 built-in codec ALSA Soc Audio driver ++ * ++ * Author: Michal Ulianko ++ * ++ * Based on sound/soc/codecs/mxs-adc-codec.c for kernel 2.6.35 ++ * by Vladislav Buzov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mxs-builtin-codec.h" ++ ++#ifndef BF ++#define BF(value, field) (((value) << BP_##field) & BM_##field) ++#endif ++ ++/* TODO Delete this and use BM_RTC_PERSISTENT0_RELEASE_GND from header file ++ * if it works. */ ++#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 ++#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 ++#define BM_RTC_PERSISTENT0_RELEASE_GND BF(0x2, RTC_PERSISTENT0_SPARE_ANALOG) ++ ++/* TODO Use codec IO function soc snd write etc, instead of __writel __readl */ ++ ++struct mxs_adc_priv { ++ void __iomem *ain_base; ++ void __iomem *aout_base; ++ void __iomem *rtc_base; ++ struct clk *clk; ++}; ++ ++static unsigned int mxs_regmap[] = { ++ HW_AUDIOOUT_CTRL, ++ HW_AUDIOOUT_STAT, ++ HW_AUDIOOUT_DACSRR, ++ HW_AUDIOOUT_DACVOLUME, ++ HW_AUDIOOUT_DACDEBUG, ++ HW_AUDIOOUT_HPVOL, ++ HW_AUDIOOUT_PWRDN, ++ HW_AUDIOOUT_REFCTRL, ++ HW_AUDIOOUT_ANACTRL, ++ HW_AUDIOOUT_TEST, ++ HW_AUDIOOUT_BISTCTRL, ++ HW_AUDIOOUT_BISTSTAT0, ++ HW_AUDIOOUT_BISTSTAT1, ++ HW_AUDIOOUT_ANACLKCTRL, ++ HW_AUDIOOUT_DATA, ++ HW_AUDIOOUT_SPEAKERCTRL, ++ HW_AUDIOOUT_VERSION, ++ HW_AUDIOIN_CTRL, ++ HW_AUDIOIN_STAT, ++ HW_AUDIOIN_ADCSRR, ++ HW_AUDIOIN_ADCVOLUME, ++ HW_AUDIOIN_ADCDEBUG, ++ HW_AUDIOIN_ADCVOL, ++ HW_AUDIOIN_MICLINE, ++ HW_AUDIOIN_ANACLKCTRL, ++ HW_AUDIOIN_DATA, ++}; ++ ++static void __iomem *mxs_getreg(struct mxs_adc_priv *mxs_adc, int i) ++{ ++ if (i <= 16) ++ return mxs_adc->aout_base + mxs_regmap[i]; ++ else if (i < ADC_REGNUM) ++ return mxs_adc->ain_base + mxs_regmap[i]; ++ else ++ return NULL; ++} ++ ++static u8 dac_volumn_control_word[] = { ++ 0x37, 0x5e, 0x7e, 0x8e, ++ 0x9e, 0xae, 0xb6, 0xbe, ++ 0xc6, 0xce, 0xd6, 0xde, ++ 0xe6, 0xee, 0xf6, 0xfe, ++}; ++ ++struct dac_srr { ++ u32 rate; ++ u32 basemult; ++ u32 src_hold; ++ u32 src_int; ++ u32 src_frac; ++}; ++ ++static struct dac_srr srr_values[] = { ++ {192000, 0x4, 0x0, 0x0F, 0x13FF}, ++ {176400, 0x4, 0x0, 0x11, 0x0037}, ++ {128000, 0x4, 0x0, 0x17, 0x0E00}, ++ {96000, 0x2, 0x0, 0x0F, 0x13FF}, ++ {88200, 0x2, 0x0, 0x11, 0x0037}, ++ {64000, 0x2, 0x0, 0x17, 0x0E00}, ++ {48000, 0x1, 0x0, 0x0F, 0x13FF}, ++ {44100, 0x1, 0x0, 0x11, 0x0037}, ++ {32000, 0x1, 0x0, 0x17, 0x0E00}, ++ {24000, 0x1, 0x1, 0x0F, 0x13FF}, ++ {22050, 0x1, 0x1, 0x11, 0x0037}, ++ {16000, 0x1, 0x1, 0x17, 0x0E00}, ++ {12000, 0x1, 0x3, 0x0F, 0x13FF}, ++ {11025, 0x1, 0x3, 0x11, 0x0037}, ++ {8000, 0x1, 0x3, 0x17, 0x0E00} ++}; ++ ++static inline int get_srr_values(int rate) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(srr_values); i++) ++ if (srr_values[i].rate == rate) ++ return i; ++ ++ return -1; ++} ++ ++/* SoC IO functions */ ++static void mxs_codec_write_cache(struct snd_soc_codec *codec, unsigned int reg, unsigned int value) ++{ ++ u16 *cache = codec->reg_cache; ++ if (reg < ADC_REGNUM) ++ cache[reg] = value; ++} ++ ++static int mxs_codec_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); ++ unsigned int reg_val; ++ unsigned int mask = 0xffff; ++ ++ if (reg >= ADC_REGNUM) ++ return -EIO; ++ ++ mxs_codec_write_cache(codec, reg, value); ++ ++ if (reg & 0x1) { ++ mask <<= 16; ++ value <<= 16; ++ } ++ ++ reg_val = __raw_readl(mxs_getreg(mxs_adc, reg >> 1)); ++ reg_val = (reg_val & ~mask) | value; ++ __raw_writel(reg_val, mxs_getreg(mxs_adc, reg >> 1)); ++ ++ return 0; ++} ++ ++static unsigned int mxs_codec_read(struct snd_soc_codec *codec, unsigned int reg) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); ++ unsigned int reg_val; ++ ++ if (reg >= ADC_REGNUM) ++ return -1; ++ ++ reg_val = __raw_readl(mxs_getreg(mxs_adc, reg >> 1)); ++ if (reg & 1) ++ reg_val >>= 16; ++ ++ return reg_val & 0xffff; ++} ++ ++// static unsigned int mxs_codec_read_cache(struct snd_soc_codec *codec, unsigned int reg) ++// { ++// u16 *cache = codec->reg_cache; ++// if (reg >= ADC_REGNUM) ++// return -EINVAL; ++// return cache[reg]; ++// } ++ ++static void mxs_codec_sync_reg_cache(struct snd_soc_codec *codec) ++{ ++ int reg; ++ for (reg = 0; reg < ADC_REGNUM; reg += 1) ++ mxs_codec_write_cache(codec, reg, ++ mxs_codec_read(codec, reg)); ++} ++ ++// static int mxs_codec_restore_reg(struct snd_soc_codec *codec, unsigned int reg) ++// { ++// unsigned int cached_val, hw_val; ++// ++// cached_val = mxs_codec_read_cache(codec, reg); ++// hw_val = mxs_codec_read(codec, reg); ++// ++// if (hw_val != cached_val) ++// return mxs_codec_write(codec, reg, cached_val); ++// ++// return 0; ++// } ++/* END SoC IO functions */ ++ ++/* Codec routines */ ++#define VAG_BASE_VALUE ((1400/2 - 625)/25) ++ ++static void mxs_codec_dac_set_vag(struct mxs_adc_priv *mxs_adc) ++{ ++ u32 refctrl_val = __raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL); ++ ++ refctrl_val &= ~(BM_AUDIOOUT_REFCTRL_VAG_VAL); ++ refctrl_val &= ~(BM_AUDIOOUT_REFCTRL_VBG_ADJ); ++ refctrl_val |= BF(VAG_BASE_VALUE, AUDIOOUT_REFCTRL_VAG_VAL) | ++ BM_AUDIOOUT_REFCTRL_ADJ_VAG | ++ BF(0xF, AUDIOOUT_REFCTRL_ADC_REFVAL) | ++ BM_AUDIOOUT_REFCTRL_ADJ_ADC | ++ BF(0x3, AUDIOOUT_REFCTRL_VBG_ADJ) | BM_AUDIOOUT_REFCTRL_RAISE_REF; ++ ++ __raw_writel(refctrl_val, mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL); ++} ++ ++static bool mxs_codec_dac_is_capless(struct mxs_adc_priv *mxs_adc) ++{ ++ if ((__raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_PWRDN) ++ & BM_AUDIOOUT_PWRDN_CAPLESS) == 0) ++ return false; ++ else ++ return true; ++} ++ ++static void mxs_codec_dac_arm_short_cm(struct mxs_adc_priv *mxs_adc, bool bShort) ++{ ++ __raw_writel(BF(3, AUDIOOUT_ANACTRL_SHORTMODE_CM), ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_CM_STS, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ if (bShort) ++ __raw_writel(BF(1, AUDIOOUT_ANACTRL_SHORTMODE_CM), ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET); ++} ++ ++static void mxs_codec_dac_arm_short_lr(struct mxs_adc_priv *mxs_adc, bool bShort) ++{ ++ __raw_writel(BF(3, AUDIOOUT_ANACTRL_SHORTMODE_LR), ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ if (bShort) ++ __raw_writel(BF(1, AUDIOOUT_ANACTRL_SHORTMODE_LR), ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET); ++} ++ ++static void mxs_codec_dac_set_short_trip_level(struct mxs_adc_priv *mxs_adc, u8 u8level) ++{ ++ __raw_writel(__raw_readl(mxs_adc->aout_base + ++ HW_AUDIOOUT_ANACTRL) ++ & (~BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL) ++ & (~BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR) ++ | BF(u8level, AUDIOOUT_ANACTRL_SHORT_LVLADJL) ++ | BF(u8level, AUDIOOUT_ANACTRL_SHORT_LVLADJR), ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL); ++} ++ ++static void mxs_codec_dac_arm_short(struct mxs_adc_priv *mxs_adc, bool bLatchCM, bool bLatchLR) ++{ ++ if (bLatchCM) { ++ if (mxs_codec_dac_is_capless(mxs_adc)) ++ mxs_codec_dac_arm_short_cm(mxs_adc, true); ++ } else ++ mxs_codec_dac_arm_short_cm(mxs_adc, false); ++ ++ if (bLatchLR) ++ mxs_codec_dac_arm_short_lr(mxs_adc, true); ++ else ++ mxs_codec_dac_arm_short_lr(mxs_adc, false); ++} ++ ++static void ++mxs_codec_dac_power_on(struct mxs_adc_priv *mxs_adc) ++{ ++ /* Ungate DAC clocks */ ++ __raw_writel(BM_AUDIOOUT_CTRL_CLKGATE, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR); ++ __raw_writel(BM_AUDIOOUT_ANACLKCTRL_CLKGATE, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACLKCTRL_CLR); ++ ++ /* 16 bit word length */ ++ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET); ++ ++ /* Arm headphone LR short protect */ ++ mxs_codec_dac_set_short_trip_level(mxs_adc, 0); ++ mxs_codec_dac_arm_short(mxs_adc, false, true); ++ ++ /* Update DAC volume over zero crossings */ ++ __raw_writel(BM_AUDIOOUT_DACVOLUME_EN_ZCD, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET); ++ /* Mute DAC */ ++ __raw_writel(BM_AUDIOOUT_DACVOLUME_MUTE_LEFT | ++ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET); ++ ++ /* Update HP volume over zero crossings */ ++ __raw_writel(BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD, ++ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET); ++ ++ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET); ++ ++ /* Mute HP output */ ++ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, ++ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET); ++ /* Mute speaker amp */ ++ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE, ++ mxs_adc->aout_base + HW_AUDIOOUT_SPEAKERCTRL_SET); ++ /* Enable the audioout */ ++ __raw_writel(BM_AUDIOOUT_CTRL_RUN, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET); ++} ++ ++static void ++mxs_codec_dac_power_down(struct mxs_adc_priv *mxs_adc) ++{ ++ /* Disable the audioout */ ++ __raw_writel(BM_AUDIOOUT_CTRL_RUN, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR); ++ /* Disable class AB */ ++ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ ++ /* Set hold to ground */ ++ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET); ++ ++ /* Mute HP output */ ++ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, ++ mxs_adc->aout_base + HW_AUDIOOUT_HPVOL_SET); ++ /* Power down HP output */ ++ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, ++ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET); ++ ++ /* Mute speaker amp */ ++ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE, ++ mxs_adc->aout_base + HW_AUDIOOUT_SPEAKERCTRL_SET); ++ /* Power down speaker amp */ ++ __raw_writel(BM_AUDIOOUT_PWRDN_SPEAKER, ++ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET); ++ ++ /* Mute DAC */ ++ __raw_writel(BM_AUDIOOUT_DACVOLUME_MUTE_LEFT | ++ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET); ++ /* Power down DAC */ ++ __raw_writel(BM_AUDIOOUT_PWRDN_DAC, ++ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET); ++ ++ /* Gate DAC clocks */ ++ __raw_writel(BM_AUDIOOUT_ANACLKCTRL_CLKGATE, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACLKCTRL_SET); ++ __raw_writel(BM_AUDIOOUT_CTRL_CLKGATE, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET); ++} ++ ++static void ++mxs_codec_adc_power_on(struct mxs_adc_priv *mxs_adc) ++{ ++ u32 reg; ++ ++ /* Ungate ADC clocks */ ++ __raw_writel(BM_AUDIOIN_CTRL_CLKGATE, ++ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR); ++ __raw_writel(BM_AUDIOIN_ANACLKCTRL_CLKGATE, ++ mxs_adc->ain_base + HW_AUDIOIN_ANACLKCTRL_CLR); ++ ++ /* 16 bit word length */ ++ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH, ++ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET); ++ ++ /* Unmute ADC channels */ ++ __raw_writel(BM_AUDIOIN_ADCVOL_MUTE, ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR); ++ ++ /* ++ * The MUTE_LEFT and MUTE_RIGHT fields need to be cleared. ++ * They aren't presented in the datasheet, so this is hardcode. ++ */ ++ __raw_writel(0x01000100, mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME_CLR); ++ ++ /* Set the Input channel gain 3dB */ ++ __raw_writel(BM_AUDIOIN_ADCVOL_GAIN_LEFT, ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR); ++ __raw_writel(BM_AUDIOIN_ADCVOL_GAIN_RIGHT, ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR); ++ __raw_writel(BF(2, AUDIOIN_ADCVOL_GAIN_LEFT), ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET); ++ __raw_writel(BF(2, AUDIOIN_ADCVOL_GAIN_RIGHT), ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET); ++ ++ /* Select default input - Microphone */ ++ __raw_writel(BM_AUDIOIN_ADCVOL_SELECT_LEFT, ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR); ++ __raw_writel(BM_AUDIOIN_ADCVOL_SELECT_RIGHT, ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_CLR); ++ __raw_writel(BF ++ (BV_AUDIOIN_ADCVOL_SELECT__MIC, ++ AUDIOIN_ADCVOL_SELECT_LEFT), ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET); ++ __raw_writel(BF ++ (BV_AUDIOIN_ADCVOL_SELECT__MIC, ++ AUDIOIN_ADCVOL_SELECT_RIGHT), ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET); ++ ++ /* Supply bias voltage to microphone */ ++ __raw_writel(BF(1, AUDIOIN_MICLINE_MIC_RESISTOR), ++ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET); ++ __raw_writel(BM_AUDIOIN_MICLINE_MIC_SELECT, ++ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET); ++ __raw_writel(BF(1, AUDIOIN_MICLINE_MIC_GAIN), ++ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET); ++ __raw_writel(BF(7, AUDIOIN_MICLINE_MIC_BIAS), ++ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET); ++ ++ /* Set max ADC volume */ ++ reg = __raw_readl(mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME); ++ reg &= ~BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT; ++ reg &= ~BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT; ++ reg |= BF(ADC_VOLUME_MAX, AUDIOIN_ADCVOLUME_VOLUME_LEFT); ++ reg |= BF(ADC_VOLUME_MAX, AUDIOIN_ADCVOLUME_VOLUME_RIGHT); ++ __raw_writel(reg, mxs_adc->ain_base + HW_AUDIOIN_ADCVOLUME); ++} ++ ++static void ++mxs_codec_adc_power_down(struct mxs_adc_priv *mxs_adc) ++{ ++ /* Mute ADC channels */ ++ __raw_writel(BM_AUDIOIN_ADCVOL_MUTE, ++ mxs_adc->ain_base + HW_AUDIOIN_ADCVOL_SET); ++ ++ /* Power Down ADC */ ++ __raw_writel(BM_AUDIOOUT_PWRDN_ADC | BM_AUDIOOUT_PWRDN_RIGHT_ADC, ++ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET); ++ ++ /* Gate ADC clocks */ ++ __raw_writel(BM_AUDIOIN_CTRL_CLKGATE, ++ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET); ++ __raw_writel(BM_AUDIOIN_ANACLKCTRL_CLKGATE, ++ mxs_adc->ain_base + HW_AUDIOIN_ANACLKCTRL_SET); ++ ++ /* Disable bias voltage to microphone */ ++ __raw_writel(BF(0, AUDIOIN_MICLINE_MIC_RESISTOR), ++ mxs_adc->ain_base + HW_AUDIOIN_MICLINE_SET); ++} ++ ++static void mxs_codec_dac_enable(struct mxs_adc_priv *mxs_adc) ++{ ++ /* Move DAC codec out of reset */ ++ __raw_writel(BM_AUDIOOUT_CTRL_SFTRST, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR); ++ ++ /* Reduce analog power */ ++ __raw_writel(BM_AUDIOOUT_TEST_HP_I1_ADJ, ++ mxs_adc->aout_base + HW_AUDIOOUT_TEST_CLR); ++ __raw_writel(BF(0x1, AUDIOOUT_TEST_HP_I1_ADJ), ++ mxs_adc->aout_base + HW_AUDIOOUT_TEST_SET); ++ __raw_writel(BM_AUDIOOUT_REFCTRL_LOW_PWR, ++ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_SET); ++ __raw_writel(BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS, ++ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_SET); ++ __raw_writel(BM_AUDIOOUT_REFCTRL_BIAS_CTRL, ++ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_CLR); ++ __raw_writel(BF(0x1, AUDIOOUT_REFCTRL_BIAS_CTRL), ++ mxs_adc->aout_base + HW_AUDIOOUT_REFCTRL_CLR); ++ ++ /* Set Vag value */ ++ mxs_codec_dac_set_vag(mxs_adc); ++ ++ /* Power on DAC codec */ ++ mxs_codec_dac_power_on(mxs_adc); ++} ++ ++static void mxs_codec_dac_disable(struct mxs_adc_priv *mxs_adc) ++{ ++ mxs_codec_dac_power_down(mxs_adc); ++} ++ ++static void mxs_codec_adc_enable(struct mxs_adc_priv *mxs_adc) ++{ ++ /* Move ADC codec out of reset */ ++ __raw_writel(BM_AUDIOIN_CTRL_SFTRST, ++ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR); ++ ++ /* Power on ADC codec */ ++ mxs_codec_adc_power_on(mxs_adc); ++} ++ ++static void mxs_codec_adc_disable(struct mxs_adc_priv *mxs_adc) ++{ ++ mxs_codec_adc_power_down(mxs_adc); ++} ++ ++static void mxs_codec_startup(struct snd_soc_codec *codec) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); ++ ++ /* Soft reset DAC block */ ++ __raw_writel(BM_AUDIOOUT_CTRL_SFTRST, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET); ++ while (!(__raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_CTRL) ++ & BM_AUDIOOUT_CTRL_CLKGATE)){ ++ } ++ ++ /* Soft reset ADC block */ ++ __raw_writel(BM_AUDIOIN_CTRL_SFTRST, ++ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET); ++ while (!(__raw_readl(mxs_adc->ain_base + HW_AUDIOIN_CTRL) ++ & BM_AUDIOIN_CTRL_CLKGATE)){ ++ } ++ ++ mxs_codec_dac_enable(mxs_adc); ++ mxs_codec_adc_enable(mxs_adc); ++ ++ /* Sync regs and cache */ ++ mxs_codec_sync_reg_cache(codec); ++} ++ ++static void mxs_codec_stop(struct snd_soc_codec *codec) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); ++ ++ mxs_codec_dac_disable(mxs_adc); ++ mxs_codec_adc_disable(mxs_adc); ++} ++/* END Codec routines */ ++ ++/* kcontrol */ ++static int dac_info_volsw(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 2; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = 0xf; ++ return 0; ++} ++ ++static int dac_get_volsw(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); ++ int reg, l, r; ++ int i; ++ ++ reg = __raw_readl(mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME); ++ ++ l = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) >> ++ BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT; ++ r = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) >> ++ BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT; ++ /*Left channel */ ++ i = 0; ++ while (i < 16) { ++ if (l == dac_volumn_control_word[i]) { ++ ucontrol->value.integer.value[0] = i; ++ break; ++ } ++ i++; ++ } ++ if (i == 16) ++ ucontrol->value.integer.value[0] = i; ++ /*Right channel */ ++ i = 0; ++ while (i < 16) { ++ if (r == dac_volumn_control_word[i]) { ++ ucontrol->value.integer.value[1] = i; ++ break; ++ } ++ i++; ++ } ++ if (i == 16) ++ ucontrol->value.integer.value[1] = i; ++ ++ return 0; ++} ++ ++static int dac_put_volsw(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); ++ int reg, l, r; ++ int i; ++ ++ i = ucontrol->value.integer.value[0]; ++ l = dac_volumn_control_word[i]; ++ /*Get dac volume for left channel */ ++ reg = BF(l, AUDIOOUT_DACVOLUME_VOLUME_LEFT); ++ ++ i = ucontrol->value.integer.value[1]; ++ r = dac_volumn_control_word[i]; ++ /*Get dac volume for right channel */ ++ reg = reg | BF(r, AUDIOOUT_DACVOLUME_VOLUME_RIGHT); ++ ++ /*Clear left/right dac volume */ ++ __raw_writel(BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT | ++ BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_CLR); ++ __raw_writel(reg, mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET); ++ ++ return 0; ++} ++ ++static const char *mxs_codec_adc_input_sel[] = { ++ "Mic", "Line In 1", "Head Phone", "Line In 2" }; ++ ++static const char *mxs_codec_hp_output_sel[] = { "DAC Out", "Line In 1" }; ++ ++static const char *mxs_codec_adc_3d_sel[] = { ++ "Off", "Low", "Medium", "High" }; ++ ++static const struct soc_enum mxs_codec_enum[] = { ++ SOC_ENUM_SINGLE(ADC_ADCVOL_L, 12, 4, mxs_codec_adc_input_sel), ++ SOC_ENUM_SINGLE(ADC_ADCVOL_L, 4, 4, mxs_codec_adc_input_sel), ++ SOC_ENUM_SINGLE(DAC_HPVOL_H, 0, 2, mxs_codec_hp_output_sel), ++ SOC_ENUM_SINGLE(DAC_CTRL_L, 8, 4, mxs_codec_adc_3d_sel), ++}; ++ ++static const struct snd_kcontrol_new mxs_snd_controls[] = { ++ /* Playback Volume */ ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "DAC Playback Volume", ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | ++ SNDRV_CTL_ELEM_ACCESS_VOLATILE, ++ .info = dac_info_volsw, ++ .get = dac_get_volsw, ++ .put = dac_put_volsw, ++ }, ++ ++ SOC_DOUBLE_R("DAC Playback Switch", ++ DAC_VOLUME_H, DAC_VOLUME_L, 8, 0x01, 1), ++ SOC_DOUBLE("HP Playback Volume", DAC_HPVOL_L, 8, 0, 0x7F, 1), ++ ++ /* Capture Volume */ ++ SOC_DOUBLE_R("ADC Capture Volume", ++ ADC_VOLUME_H, ADC_VOLUME_L, 0, 0xFF, 0), ++ SOC_DOUBLE("ADC PGA Capture Volume", ADC_ADCVOL_L, 8, 0, 0x0F, 0), ++ SOC_SINGLE("ADC PGA Capture Switch", ADC_ADCVOL_H, 8, 0x1, 1), ++ SOC_SINGLE("Mic PGA Capture Volume", ADC_MICLINE_L, 0, 0x03, 0), ++ ++ /* Virtual 3D effect */ ++ SOC_ENUM("3D effect", mxs_codec_enum[3]), ++}; ++/* END kcontrol */ ++ ++/* DAPM */ ++static int pga_event(struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol *kcontrol, int event) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(w->codec); ++ ++ switch (event) { ++ case SND_SOC_DAPM_PRE_PMU: ++ /* Prepare powering up HP and SPEAKER output */ ++ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_SET); ++ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND, ++ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_SET); ++ msleep(100); ++ break; ++ case SND_SOC_DAPM_POST_PMU: ++ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_HOLD_GND, ++ mxs_adc->aout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ break; ++ case SND_SOC_DAPM_POST_PMD: ++ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND, ++ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_CLR); ++ break; ++ } ++ return 0; ++} ++ ++static int adc_event(struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol *kcontrol, int event) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(w->codec); ++ ++ switch (event) { ++ case SND_SOC_DAPM_PRE_PMU: ++ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND, ++ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_SET); ++ msleep(100); ++ break; ++ case SND_SOC_DAPM_POST_PMD: ++ __raw_writel(BM_RTC_PERSISTENT0_RELEASE_GND, ++ mxs_adc->rtc_base + HW_RTC_PERSISTENT0_CLR); ++ break; ++ } ++ return 0; ++} ++ ++/* Left ADC Mux */ ++static const struct snd_kcontrol_new mxs_left_adc_controls = ++SOC_DAPM_ENUM("Route", mxs_codec_enum[0]); ++ ++/* Right ADC Mux */ ++static const struct snd_kcontrol_new mxs_right_adc_controls = ++SOC_DAPM_ENUM("Route", mxs_codec_enum[1]); ++ ++/* Head Phone Mux */ ++static const struct snd_kcontrol_new mxs_hp_controls = ++SOC_DAPM_ENUM("Route", mxs_codec_enum[2]); ++ ++static const struct snd_soc_dapm_widget mxs_dapm_widgets[] = { ++ SND_SOC_DAPM_ADC_E("ADC", "Capture", DAC_PWRDN_L, 8, 1, adc_event, ++ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), ++ ++ SND_SOC_DAPM_DAC("DAC", "Playback", DAC_PWRDN_L, 12, 1), ++ ++ SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, ++ &mxs_left_adc_controls), ++ SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, ++ &mxs_right_adc_controls), ++ SND_SOC_DAPM_MUX("HP Mux", SND_SOC_NOPM, 0, 0, ++ &mxs_hp_controls), ++ SND_SOC_DAPM_PGA_E("HP AMP", DAC_PWRDN_L, 0, 1, NULL, 0, pga_event, ++ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | ++ SND_SOC_DAPM_POST_PMD), ++ SND_SOC_DAPM_PGA("SPEAKER AMP", DAC_PWRDN_H, 8, 1, NULL, 0), ++ SND_SOC_DAPM_INPUT("LINE1L"), ++ SND_SOC_DAPM_INPUT("LINE1R"), ++ SND_SOC_DAPM_INPUT("LINE2L"), ++ SND_SOC_DAPM_INPUT("LINE2R"), ++ SND_SOC_DAPM_INPUT("MIC"), ++ ++ SND_SOC_DAPM_OUTPUT("SPEAKER"), ++ SND_SOC_DAPM_OUTPUT("HPL"), ++ SND_SOC_DAPM_OUTPUT("HPR"), ++}; ++ ++/* routes for sgtl5000 */ ++static const struct snd_soc_dapm_route mxs_dapm_routes[] = { ++ /* Left ADC Mux */ ++ {"Left ADC Mux", "Mic", "MIC"}, ++ {"Left ADC Mux", "Line In 1", "LINE1L"}, ++ {"Left ADC Mux", "Line In 2", "LINE2L"}, ++ {"Left ADC Mux", "Head Phone", "HPL"}, ++ ++ /* Right ADC Mux */ ++ {"Right ADC Mux", "Mic", "MIC"}, ++ {"Right ADC Mux", "Line In 1", "LINE1R"}, ++ {"Right ADC Mux", "Line In 2", "LINE2R"}, ++ {"Right ADC Mux", "Head Phone", "HPR"}, ++ ++ /* ADC */ ++ {"ADC", NULL, "Left ADC Mux"}, ++ {"ADC", NULL, "Right ADC Mux"}, ++ ++ /* HP Mux */ ++ {"HP Mux", "DAC Out", "DAC"}, ++ {"HP Mux", "Line In 1", "LINE1L"}, ++ {"HP Mux", "Line In 1", "LINE1R"}, ++ ++ /* HP amp */ ++ {"HP AMP", NULL, "HP Mux"}, ++ /* HP output */ ++ {"HPR", NULL, "HP AMP"}, ++ {"HPL", NULL, "HP AMP"}, ++ ++ /* Speaker amp */ ++ {"SPEAKER AMP", NULL, "DAC"}, ++ {"SPEAKER", NULL, "SPEAKER AMP"}, ++}; ++/* END DAPM */ ++ ++static int mxs_set_bias_level(struct snd_soc_codec *codec, ++ enum snd_soc_bias_level level) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); ++ ++ pr_debug("dapm level %d\n", level); ++ switch (level) { ++ case SND_SOC_BIAS_ON: /* full On */ ++ if (codec->dapm.bias_level == SND_SOC_BIAS_ON) ++ break; ++ break; ++ ++ case SND_SOC_BIAS_PREPARE: /* partial On */ ++ if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) ++ break; ++ /* Set Capless mode */ ++ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS, ++ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_CLR); ++ break; ++ ++ case SND_SOC_BIAS_STANDBY: /* Off, with power */ ++ if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) ++ break; ++ /* Unset Capless mode */ ++ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS, ++ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET); ++ break; ++ ++ case SND_SOC_BIAS_OFF: /* Off, without power */ ++ if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) ++ break; ++ /* Unset Capless mode */ ++ __raw_writel(BM_AUDIOOUT_PWRDN_CAPLESS, ++ mxs_adc->aout_base + HW_AUDIOOUT_PWRDN_SET); ++ break; ++ } ++ ++ codec->dapm.bias_level = level; ++ return 0; ++} ++ ++/* MXS-ADC Codec DAI driver */ ++static int mxs_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec); ++ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; ++ int i; ++ u32 srr_value = 0; ++ u32 src_hold = 0; ++ ++ i = get_srr_values(params_rate(params)); ++ if (i < 0) ++ dev_warn(codec->dev, "codec doesn't support rate %d\n", ++ params_rate(params)); ++ else { ++ src_hold = srr_values[i].src_hold; ++ ++ srr_value = ++ BF(srr_values[i].basemult, AUDIOOUT_DACSRR_BASEMULT) | ++ BF(srr_values[i].src_int, AUDIOOUT_DACSRR_SRC_INT) | ++ BF(srr_values[i].src_frac, AUDIOOUT_DACSRR_SRC_FRAC) | ++ BF(src_hold, AUDIOOUT_DACSRR_SRC_HOLD); ++ ++ if (playback) ++ __raw_writel(srr_value, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACSRR); ++ else ++ __raw_writel(srr_value, ++ mxs_adc->ain_base + HW_AUDIOIN_ADCSRR); ++ } ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ if (playback) ++ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_SET); ++ else ++ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH, ++ mxs_adc->ain_base + HW_AUDIOIN_CTRL_SET); ++ ++ break; ++ ++ case SNDRV_PCM_FORMAT_S32_LE: ++ if (playback) ++ __raw_writel(BM_AUDIOOUT_CTRL_WORD_LENGTH, ++ mxs_adc->aout_base + HW_AUDIOOUT_CTRL_CLR); ++ else ++ __raw_writel(BM_AUDIOIN_CTRL_WORD_LENGTH, ++ mxs_adc->ain_base + HW_AUDIOIN_CTRL_CLR); ++ ++ break; ++ ++ default: ++ dev_warn(codec->dev, "codec doesn't support format %d\n", ++ params_format(params)); ++ ++ } ++ ++ return 0; ++} ++ ++/* mute the codec used by alsa core */ ++static int mxs_codec_dig_mute(struct snd_soc_dai *codec_dai, int mute) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_codec_get_drvdata(codec_dai->codec); ++ int l, r; ++ int ll, rr; ++ u32 reg, reg1, reg2; ++ u32 dac_mask = BM_AUDIOOUT_DACVOLUME_MUTE_LEFT | ++ BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT; ++ ++ if (mute) { ++ reg = __raw_readl(mxs_adc->aout_base + \ ++ HW_AUDIOOUT_DACVOLUME); ++ ++ reg1 = reg & ~BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT; ++ reg1 = reg1 & ~BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT; ++ ++ l = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) >> ++ BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT; ++ r = (reg & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) >> ++ BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT; ++ ++ /* fade out dac vol */ ++ while ((l > DAC_VOLUME_MIN) || (r > DAC_VOLUME_MIN)) { ++ l -= 0x8; ++ r -= 0x8; ++ ll = l > DAC_VOLUME_MIN ? l : DAC_VOLUME_MIN; ++ rr = r > DAC_VOLUME_MIN ? r : DAC_VOLUME_MIN; ++ reg2 = reg1 | BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(ll) ++ | BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(rr); ++ __raw_writel(reg2, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME); ++ msleep(1); ++ } ++ ++ __raw_writel(dac_mask, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_SET); ++ reg = reg | dac_mask; ++ __raw_writel(reg, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME); ++ } else ++ __raw_writel(dac_mask, ++ mxs_adc->aout_base + HW_AUDIOOUT_DACVOLUME_CLR); ++ ++ return 0; ++} ++ ++#define MXS_ADC_RATES SNDRV_PCM_RATE_8000_192000 ++#define MXS_ADC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) ++ ++static const struct snd_soc_dai_ops mxs_codec_dai_ops = { ++ .hw_params = mxs_pcm_hw_params, ++ .digital_mute = mxs_codec_dig_mute, ++}; ++ ++static struct snd_soc_dai_driver mxs_codec_dai_driver = { ++ .name = "mxs-builtin-codec-dai", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = MXS_ADC_RATES, ++ .formats = MXS_ADC_FORMATS, ++ }, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = MXS_ADC_RATES, ++ .formats = MXS_ADC_FORMATS, ++ }, ++ .ops = &mxs_codec_dai_ops, ++}; ++/* END MXS-ADC Codec DAI driver */ ++ ++/* MXS-ADC Codec driver */ ++static int mxs_codec_driver_probe(struct snd_soc_codec *codec) ++{ ++ int ret = 0; ++ /* We don't use snd_soc_codec_set_cache_io because we are using ++ * our own IO functions: write, read. */ ++ ++ mxs_codec_startup(codec); ++ ++ /* leading to standby state */ ++ ret = mxs_set_bias_level(codec, SND_SOC_BIAS_STANDBY); ++ if (ret) ++ goto err; ++ ++ return 0; ++ ++err: ++ mxs_codec_stop(codec); ++ ++ return ret; ++} ++ ++static int mxs_codec_driver_remove(struct snd_soc_codec *codec) ++{ ++ mxs_codec_stop(codec); ++ ++ return 0; ++} ++ ++// static int mxs_codec_driver_suspend(struct snd_soc_codec *codec) ++// { ++// /* TODO Enable power management. */ ++// return 0; ++// } ++ ++// static int mxs_codec_driver_resume(struct snd_soc_codec *codec) ++// { ++// /* TODO Enable power management. */ ++// return 0; ++// } ++ ++static struct snd_soc_codec_driver mxs_codec_driver = { ++ .probe = mxs_codec_driver_probe, ++ .remove = mxs_codec_driver_remove, ++// .suspend = mxs_codec_driver_suspend, ++// .resume = mxs_codec_driver_resume, ++ .set_bias_level = mxs_set_bias_level, ++ .reg_cache_size = ADC_REGNUM, ++ .reg_word_size = sizeof(u16), ++ .reg_cache_step = 1, ++// .reg_cache_default = mxsadc_regs, ++// .volatile_register = sgtl5000_volatile_register, ++ .controls = mxs_snd_controls, ++ .num_controls = ARRAY_SIZE(mxs_snd_controls), ++ .dapm_widgets = mxs_dapm_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(mxs_dapm_widgets), ++ .dapm_routes = mxs_dapm_routes, ++ .num_dapm_routes = ARRAY_SIZE(mxs_dapm_routes), ++ .write = mxs_codec_write, ++ .read = mxs_codec_read, ++}; ++/* END MXS-ADC Codec driver */ ++ ++/* Underlying platform device that registers codec */ ++static int mxs_adc_probe(struct platform_device *pdev) ++{ ++ struct mxs_adc_priv *mxs_adc; ++ struct resource *r; ++ int ret; ++ ++ mxs_adc = devm_kzalloc(&pdev->dev, sizeof(struct mxs_adc_priv), GFP_KERNEL); ++ if (!mxs_adc) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, mxs_adc); ++ ++ /* audio-in IO memory */ ++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audioin"); ++ if (IS_ERR(r)) { ++ dev_err(&pdev->dev, "failed to get resource\n"); ++ return PTR_ERR(r); ++ } ++ ++ mxs_adc->ain_base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); ++ if (IS_ERR(mxs_adc->ain_base)) { ++ dev_err(&pdev->dev, "ioremap failed\n"); ++ return PTR_ERR(mxs_adc->ain_base); ++ } ++ ++ /* audio-out IO memory */ ++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audioout"); ++ if (IS_ERR(r)) { ++ dev_err(&pdev->dev, "failed to get resource\n"); ++ return PTR_ERR(r); ++ } ++ ++ mxs_adc->aout_base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); ++ if (IS_ERR(mxs_adc->aout_base)) { ++ dev_err(&pdev->dev, "ioremap failed\n"); ++ return PTR_ERR(mxs_adc->aout_base); ++ } ++ ++ /* rtc IO memory */ ++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc"); ++ if (IS_ERR(r)) { ++ dev_err(&pdev->dev, "failed to get resource\n"); ++ return PTR_ERR(r); ++ } ++ ++ mxs_adc->rtc_base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); ++ if (IS_ERR(mxs_adc->rtc_base)) { ++ dev_err(&pdev->dev, "ioremap failed\n"); ++ return PTR_ERR(mxs_adc->rtc_base); ++ } ++ ++ /* Get audio clock */ ++ mxs_adc->clk = devm_clk_get(&pdev->dev, "filt"); ++ if (IS_ERR(mxs_adc->clk)) { ++ ret = PTR_ERR(mxs_adc->clk); ++ dev_err(&pdev->dev, "%s: Clock initialization failed\n", __func__); ++ return ret; ++ } ++ ++ /* Turn on audio clock */ ++ ret = clk_prepare_enable(mxs_adc->clk); ++ if (unlikely(ret != 0)) { ++ dev_err(&pdev->dev, "%s: Clock prepare or enable failed\n", __func__); ++ return ret; ++ } ++ ++ ret = snd_soc_register_codec(&pdev->dev, ++ &mxs_codec_driver,&mxs_codec_dai_driver, 1); ++ if (unlikely(ret != 0)) { ++ dev_err(&pdev->dev, "Codec registration failed\n"); ++ goto disable_clk; ++ } ++ ++ return 0; ++ ++disable_clk: ++ clk_disable_unprepare(mxs_adc->clk); ++ return ret; ++} ++ ++static int mxs_adc_remove(struct platform_device *pdev) ++{ ++ struct mxs_adc_priv *mxs_adc = platform_get_drvdata(pdev); ++ ++ clk_disable_unprepare(mxs_adc->clk); ++ snd_soc_unregister_codec(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id mxs_adc_dt_ids[] = { ++ { .compatible = "fsl,mxs-builtin-codec", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, mxs_adc_dt_ids); ++ ++static struct platform_driver mxs_adc_driver = { ++ .driver = { ++ .name = "mxs-builtin-codec", ++ .owner = THIS_MODULE, ++ .of_match_table = mxs_adc_dt_ids, ++ }, ++ .probe = mxs_adc_probe, ++ .remove = mxs_adc_remove, ++}; ++ ++module_platform_driver(mxs_adc_driver); ++/* END Underlying platform device that registers codec */ ++ ++MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Codec Driver"); ++MODULE_AUTHOR("Michal Ulianko "); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/codecs/mxs-builtin-codec.h +@@ -0,0 +1,825 @@ ++#ifndef __MXS_ADC_CODEC_H ++ ++#include ++ ++/* MXS ADC/DAC registers */ ++#define DAC_CTRL_L 0 ++#define DAC_CTRL_H 1 ++#define DAC_STAT_L 2 ++#define DAC_STAT_H 3 ++#define DAC_SRR_L 4 ++#define DAC_VOLUME_L 6 ++#define DAC_VOLUME_H 7 ++#define DAC_DEBUG_L 8 ++#define DAC_DEBUG_H 9 ++#define DAC_HPVOL_L 10 ++#define DAC_HPVOL_H 11 ++#define DAC_PWRDN_L 12 ++#define DAC_PWRDN_H 13 ++#define DAC_REFCTRL_L 14 ++#define DAC_REFCTRL_H 15 ++#define DAC_ANACTRL_L 16 ++#define DAC_ANACTRL_H 17 ++#define DAC_TEST_L 18 ++#define DAC_TEST_H 19 ++#define DAC_BISTCTRL_L 20 ++#define DAC_BISTCTRL_H 21 ++#define DAC_BISTSTAT0_L 22 ++#define DAC_BISTSTAT0_H 23 ++#define DAC_BISTSTAT1_L 24 ++#define DAC_BISTSTAT1_H 25 ++#define DAC_ANACLKCTRL_L 26 ++#define DAC_ANACLKCTRL_H 27 ++#define DAC_DATA_L 28 ++#define DAC_DATA_H 29 ++#define DAC_SPEAKERCTRL_L 30 ++#define DAC_SPEAKERCTRL_H 31 ++#define DAC_VERSION_L 32 ++#define DAC_VERSION_H 33 ++#define ADC_CTRL_L 34 ++#define ADC_CTRL_H 35 ++#define ADC_STAT_L 36 ++#define ADC_STAT_H 37 ++#define ADC_SRR_L 38 ++#define ADC_SRR_H 39 ++#define ADC_VOLUME_L 40 ++#define ADC_VOLUME_H 41 ++#define ADC_DEBUG_L 42 ++#define ADC_DEBUG_H 43 ++#define ADC_ADCVOL_L 44 ++#define ADC_ADCVOL_H 45 ++#define ADC_MICLINE_L 46 ++#define ADC_MICLINE_H 47 ++#define ADC_ANACLKCTRL_L 48 ++#define ADC_ANACLKCTRL_H 49 ++#define ADC_DATA_L 50 ++#define ADC_DATA_H 51 ++ ++#define ADC_REGNUM 52 ++ ++#define DAC_VOLUME_MIN 0x37 ++#define DAC_VOLUME_MAX 0xFE ++#define ADC_VOLUME_MIN 0x37 ++#define ADC_VOLUME_MAX 0xFE ++#define HP_VOLUME_MAX 0x0 ++#define HP_VOLUME_MIN 0x7F ++#define LO_VOLUME_MAX 0x0 ++#define LO_VOLUME_MIN 0x1F ++ ++/* RTC */ ++#define HW_RTC_PERSISTENT0 (0x00000060) ++#define HW_RTC_PERSISTENT0_SET (0x00000064) ++#define HW_RTC_PERSISTENT0_CLR (0x00000068) ++#define HW_RTC_PERSISTENT0_TOG (0x0000006c) ++ ++// TODO ++//#define BM_RTC_PERSISTENT0_RELEASE_GND 0x00080000 ++ ++/* AUDIOOUT */ ++#define HW_AUDIOOUT_CTRL (0x00000000) ++#define HW_AUDIOOUT_CTRL_SET (0x00000004) ++#define HW_AUDIOOUT_CTRL_CLR (0x00000008) ++#define HW_AUDIOOUT_CTRL_TOG (0x0000000c) ++ ++#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 ++#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 ++#define BP_AUDIOOUT_CTRL_RSRVD4 21 ++#define BM_AUDIOOUT_CTRL_RSRVD4 0x3FE00000 ++#define BF_AUDIOOUT_CTRL_RSRVD4(v) \ ++ (((v) << 21) & BM_AUDIOOUT_CTRL_RSRVD4) ++#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 ++#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x001F0000 ++#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) \ ++ (((v) << 16) & BM_AUDIOOUT_CTRL_DMAWAIT_COUNT) ++#define BM_AUDIOOUT_CTRL_RSRVD3 0x00008000 ++#define BM_AUDIOOUT_CTRL_LR_SWAP 0x00004000 ++#define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x00002000 ++#define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x00001000 ++#define BP_AUDIOOUT_CTRL_RSRVD2 10 ++#define BM_AUDIOOUT_CTRL_RSRVD2 0x00000C00 ++#define BF_AUDIOOUT_CTRL_RSRVD2(v) \ ++ (((v) << 10) & BM_AUDIOOUT_CTRL_RSRVD2) ++#define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 ++#define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x00000300 ++#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) \ ++ (((v) << 8) & BM_AUDIOOUT_CTRL_SS3D_EFFECT) ++#define BM_AUDIOOUT_CTRL_RSRVD1 0x00000080 ++#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 ++#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x00000020 ++#define BM_AUDIOOUT_CTRL_LOOPBACK 0x00000010 ++#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 ++#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 ++#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 ++#define BM_AUDIOOUT_CTRL_RUN 0x00000001 ++ ++#define HW_AUDIOOUT_STAT (0x00000010) ++#define HW_AUDIOOUT_STAT_SET (0x00000014) ++#define HW_AUDIOOUT_STAT_CLR (0x00000018) ++#define HW_AUDIOOUT_STAT_TOG (0x0000001c) ++ ++#define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 ++#define BP_AUDIOOUT_STAT_RSRVD1 0 ++#define BM_AUDIOOUT_STAT_RSRVD1 0x7FFFFFFF ++#define BF_AUDIOOUT_STAT_RSRVD1(v) \ ++ (((v) << 0) & BM_AUDIOOUT_STAT_RSRVD1) ++ ++#define HW_AUDIOOUT_DACSRR (0x00000020) ++#define HW_AUDIOOUT_DACSRR_SET (0x00000024) ++#define HW_AUDIOOUT_DACSRR_CLR (0x00000028) ++#define HW_AUDIOOUT_DACSRR_TOG (0x0000002c) ++ ++#define BM_AUDIOOUT_DACSRR_OSR 0x80000000 ++#define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 ++#define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 ++#define BP_AUDIOOUT_DACSRR_BASEMULT 28 ++#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 ++#define BF_AUDIOOUT_DACSRR_BASEMULT(v) \ ++ (((v) << 28) & BM_AUDIOOUT_DACSRR_BASEMULT) ++#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 ++#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 ++#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 ++#define BM_AUDIOOUT_DACSRR_RSRVD2 0x08000000 ++#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 ++#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 ++#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) \ ++ (((v) << 24) & BM_AUDIOOUT_DACSRR_SRC_HOLD) ++#define BP_AUDIOOUT_DACSRR_RSRVD1 21 ++#define BM_AUDIOOUT_DACSRR_RSRVD1 0x00E00000 ++#define BF_AUDIOOUT_DACSRR_RSRVD1(v) \ ++ (((v) << 21) & BM_AUDIOOUT_DACSRR_RSRVD1) ++#define BP_AUDIOOUT_DACSRR_SRC_INT 16 ++#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 ++#define BF_AUDIOOUT_DACSRR_SRC_INT(v) \ ++ (((v) << 16) & BM_AUDIOOUT_DACSRR_SRC_INT) ++#define BP_AUDIOOUT_DACSRR_RSRVD0 13 ++#define BM_AUDIOOUT_DACSRR_RSRVD0 0x0000E000 ++#define BF_AUDIOOUT_DACSRR_RSRVD0(v) \ ++ (((v) << 13) & BM_AUDIOOUT_DACSRR_RSRVD0) ++#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 ++#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF ++#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) \ ++ (((v) << 0) & BM_AUDIOOUT_DACSRR_SRC_FRAC) ++ ++#define HW_AUDIOOUT_DACVOLUME (0x00000030) ++#define HW_AUDIOOUT_DACVOLUME_SET (0x00000034) ++#define HW_AUDIOOUT_DACVOLUME_CLR (0x00000038) ++#define HW_AUDIOOUT_DACVOLUME_TOG (0x0000003c) ++ ++#define BP_AUDIOOUT_DACVOLUME_RSRVD4 29 ++#define BM_AUDIOOUT_DACVOLUME_RSRVD4 0xE0000000 ++#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v) \ ++ (((v) << 29) & BM_AUDIOOUT_DACVOLUME_RSRVD4) ++#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 ++#define BP_AUDIOOUT_DACVOLUME_RSRVD3 26 ++#define BM_AUDIOOUT_DACVOLUME_RSRVD3 0x0C000000 ++#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v) \ ++ (((v) << 26) & BM_AUDIOOUT_DACVOLUME_RSRVD3) ++#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 ++#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 ++#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 ++#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0x00FF0000 ++#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) \ ++ (((v) << 16) & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) ++#define BP_AUDIOOUT_DACVOLUME_RSRVD2 13 ++#define BM_AUDIOOUT_DACVOLUME_RSRVD2 0x0000E000 ++#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v) \ ++ (((v) << 13) & BM_AUDIOOUT_DACVOLUME_RSRVD2) ++#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x00001000 ++#define BP_AUDIOOUT_DACVOLUME_RSRVD1 9 ++#define BM_AUDIOOUT_DACVOLUME_RSRVD1 0x00000E00 ++#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v) \ ++ (((v) << 9) & BM_AUDIOOUT_DACVOLUME_RSRVD1) ++#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 ++#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 ++#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0x000000FF ++#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) \ ++ (((v) << 0) & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) ++ ++#define HW_AUDIOOUT_DACDEBUG (0x00000040) ++#define HW_AUDIOOUT_DACDEBUG_SET (0x00000044) ++#define HW_AUDIOOUT_DACDEBUG_CLR (0x00000048) ++#define HW_AUDIOOUT_DACDEBUG_TOG (0x0000004c) ++ ++#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 ++#define BP_AUDIOOUT_DACDEBUG_RSRVD2 12 ++#define BM_AUDIOOUT_DACDEBUG_RSRVD2 0x7FFFF000 ++#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v) \ ++ (((v) << 12) & BM_AUDIOOUT_DACDEBUG_RSRVD2) ++#define BP_AUDIOOUT_DACDEBUG_RAM_SS 8 ++#define BM_AUDIOOUT_DACDEBUG_RAM_SS 0x00000F00 ++#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) \ ++ (((v) << 8) & BM_AUDIOOUT_DACDEBUG_RAM_SS) ++#define BP_AUDIOOUT_DACDEBUG_RSRVD1 6 ++#define BM_AUDIOOUT_DACDEBUG_RSRVD1 0x000000C0 ++#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v) \ ++ (((v) << 6) & BM_AUDIOOUT_DACDEBUG_RSRVD1) ++#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x00000020 ++#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x00000010 ++#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x00000008 ++#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x00000004 ++#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x00000002 ++#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x00000001 ++ ++#define HW_AUDIOOUT_HPVOL (0x00000050) ++#define HW_AUDIOOUT_HPVOL_SET (0x00000054) ++#define HW_AUDIOOUT_HPVOL_CLR (0x00000058) ++#define HW_AUDIOOUT_HPVOL_TOG (0x0000005c) ++ ++#define BP_AUDIOOUT_HPVOL_RSRVD5 29 ++#define BM_AUDIOOUT_HPVOL_RSRVD5 0xE0000000 ++#define BF_AUDIOOUT_HPVOL_RSRVD5(v) \ ++ (((v) << 29) & BM_AUDIOOUT_HPVOL_RSRVD5) ++#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000 ++#define BP_AUDIOOUT_HPVOL_RSRVD4 26 ++#define BM_AUDIOOUT_HPVOL_RSRVD4 0x0C000000 ++#define BF_AUDIOOUT_HPVOL_RSRVD4(v) \ ++ (((v) << 26) & BM_AUDIOOUT_HPVOL_RSRVD4) ++#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 ++#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 ++#define BP_AUDIOOUT_HPVOL_RSRVD3 17 ++#define BM_AUDIOOUT_HPVOL_RSRVD3 0x00FE0000 ++#define BF_AUDIOOUT_HPVOL_RSRVD3(v) \ ++ (((v) << 17) & BM_AUDIOOUT_HPVOL_RSRVD3) ++#define BM_AUDIOOUT_HPVOL_SELECT 0x00010000 ++#define BM_AUDIOOUT_HPVOL_RSRVD2 0x00008000 ++#define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 ++#define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x00007F00 ++#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) \ ++ (((v) << 8) & BM_AUDIOOUT_HPVOL_VOL_LEFT) ++#define BM_AUDIOOUT_HPVOL_RSRVD1 0x00000080 ++#define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 ++#define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x0000007F ++#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) \ ++ (((v) << 0) & BM_AUDIOOUT_HPVOL_VOL_RIGHT) ++ ++#define HW_AUDIOOUT_RESERVED (0x00000060) ++#define HW_AUDIOOUT_RESERVED_SET (0x00000064) ++#define HW_AUDIOOUT_RESERVED_CLR (0x00000068) ++#define HW_AUDIOOUT_RESERVED_TOG (0x0000006c) ++ ++#define BP_AUDIOOUT_RESERVED_RSRVD1 0 ++#define BM_AUDIOOUT_RESERVED_RSRVD1 0xFFFFFFFF ++#define BF_AUDIOOUT_RESERVED_RSRVD1(v) (v) ++ ++#define HW_AUDIOOUT_PWRDN (0x00000070) ++#define HW_AUDIOOUT_PWRDN_SET (0x00000074) ++#define HW_AUDIOOUT_PWRDN_CLR (0x00000078) ++#define HW_AUDIOOUT_PWRDN_TOG (0x0000007c) ++ ++#define BP_AUDIOOUT_PWRDN_RSRVD7 25 ++#define BM_AUDIOOUT_PWRDN_RSRVD7 0xFE000000 ++#define BF_AUDIOOUT_PWRDN_RSRVD7(v) \ ++ (((v) << 25) & BM_AUDIOOUT_PWRDN_RSRVD7) ++#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000 ++#define BP_AUDIOOUT_PWRDN_RSRVD6 21 ++#define BM_AUDIOOUT_PWRDN_RSRVD6 0x00E00000 ++#define BF_AUDIOOUT_PWRDN_RSRVD6(v) \ ++ (((v) << 21) & BM_AUDIOOUT_PWRDN_RSRVD6) ++#define BM_AUDIOOUT_PWRDN_SELFBIAS 0x00100000 ++#define BP_AUDIOOUT_PWRDN_RSRVD5 17 ++#define BM_AUDIOOUT_PWRDN_RSRVD5 0x000E0000 ++#define BF_AUDIOOUT_PWRDN_RSRVD5(v) \ ++ (((v) << 17) & BM_AUDIOOUT_PWRDN_RSRVD5) ++#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 ++#define BP_AUDIOOUT_PWRDN_RSRVD4 13 ++#define BM_AUDIOOUT_PWRDN_RSRVD4 0x0000E000 ++#define BF_AUDIOOUT_PWRDN_RSRVD4(v) \ ++ (((v) << 13) & BM_AUDIOOUT_PWRDN_RSRVD4) ++#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 ++#define BP_AUDIOOUT_PWRDN_RSRVD3 9 ++#define BM_AUDIOOUT_PWRDN_RSRVD3 0x00000E00 ++#define BF_AUDIOOUT_PWRDN_RSRVD3(v) \ ++ (((v) << 9) & BM_AUDIOOUT_PWRDN_RSRVD3) ++#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 ++#define BP_AUDIOOUT_PWRDN_RSRVD2 5 ++#define BM_AUDIOOUT_PWRDN_RSRVD2 0x000000E0 ++#define BF_AUDIOOUT_PWRDN_RSRVD2(v) \ ++ (((v) << 5) & BM_AUDIOOUT_PWRDN_RSRVD2) ++#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 ++#define BP_AUDIOOUT_PWRDN_RSRVD1 1 ++#define BM_AUDIOOUT_PWRDN_RSRVD1 0x0000000E ++#define BF_AUDIOOUT_PWRDN_RSRVD1(v) \ ++ (((v) << 1) & BM_AUDIOOUT_PWRDN_RSRVD1) ++#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 ++ ++#define HW_AUDIOOUT_REFCTRL (0x00000080) ++#define HW_AUDIOOUT_REFCTRL_SET (0x00000084) ++#define HW_AUDIOOUT_REFCTRL_CLR (0x00000088) ++#define HW_AUDIOOUT_REFCTRL_TOG (0x0000008c) ++ ++#define BP_AUDIOOUT_REFCTRL_RSRVD4 27 ++#define BM_AUDIOOUT_REFCTRL_RSRVD4 0xF8000000 ++#define BF_AUDIOOUT_REFCTRL_RSRVD4(v) \ ++ (((v) << 27) & BM_AUDIOOUT_REFCTRL_RSRVD4) ++#define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x04000000 ++#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 ++#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 ++#define BM_AUDIOOUT_REFCTRL_RSRVD3 0x00800000 ++#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 ++#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 ++#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) \ ++ (((v) << 20) & BM_AUDIOOUT_REFCTRL_VBG_ADJ) ++#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 ++#define BM_AUDIOOUT_REFCTRL_LW_REF 0x00040000 ++#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 ++#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 ++#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) \ ++ (((v) << 16) & BM_AUDIOOUT_REFCTRL_BIAS_CTRL) ++#define BM_AUDIOOUT_REFCTRL_RSRVD2 0x00008000 ++#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x00004000 ++#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 ++#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 ++#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 ++#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 ++#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) \ ++ (((v) << 8) & BM_AUDIOOUT_REFCTRL_ADC_REFVAL) ++#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 ++#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 ++#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) \ ++ (((v) << 4) & BM_AUDIOOUT_REFCTRL_VAG_VAL) ++#define BM_AUDIOOUT_REFCTRL_RSRVD1 0x00000008 ++#define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 ++#define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x00000007 ++#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) \ ++ (((v) << 0) & BM_AUDIOOUT_REFCTRL_DAC_ADJ) ++ ++#define HW_AUDIOOUT_ANACTRL (0x00000090) ++#define HW_AUDIOOUT_ANACTRL_SET (0x00000094) ++#define HW_AUDIOOUT_ANACTRL_CLR (0x00000098) ++#define HW_AUDIOOUT_ANACTRL_TOG (0x0000009c) ++ ++#define BP_AUDIOOUT_ANACTRL_RSRVD8 29 ++#define BM_AUDIOOUT_ANACTRL_RSRVD8 0xE0000000 ++#define BF_AUDIOOUT_ANACTRL_RSRVD8(v) \ ++ (((v) << 29) & BM_AUDIOOUT_ANACTRL_RSRVD8) ++#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 ++#define BP_AUDIOOUT_ANACTRL_RSRVD7 25 ++#define BM_AUDIOOUT_ANACTRL_RSRVD7 0x0E000000 ++#define BF_AUDIOOUT_ANACTRL_RSRVD7(v) \ ++ (((v) << 25) & BM_AUDIOOUT_ANACTRL_RSRVD7) ++#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x01000000 ++#define BP_AUDIOOUT_ANACTRL_RSRVD6 22 ++#define BM_AUDIOOUT_ANACTRL_RSRVD6 0x00C00000 ++#define BF_AUDIOOUT_ANACTRL_RSRVD6(v) \ ++ (((v) << 22) & BM_AUDIOOUT_ANACTRL_RSRVD6) ++#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 ++#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x00300000 ++#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) \ ++ (((v) << 20) & BM_AUDIOOUT_ANACTRL_SHORTMODE_CM) ++#define BM_AUDIOOUT_ANACTRL_RSRVD5 0x00080000 ++#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 ++#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x00060000 ++#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) \ ++ (((v) << 17) & BM_AUDIOOUT_ANACTRL_SHORTMODE_LR) ++#define BP_AUDIOOUT_ANACTRL_RSRVD4 15 ++#define BM_AUDIOOUT_ANACTRL_RSRVD4 0x00018000 ++#define BF_AUDIOOUT_ANACTRL_RSRVD4(v) \ ++ (((v) << 15) & BM_AUDIOOUT_ANACTRL_RSRVD4) ++#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 ++#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x00007000 ++#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) \ ++ (((v) << 12) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL) ++#define BM_AUDIOOUT_ANACTRL_RSRVD3 0x00000800 ++#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 ++#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x00000700 ++#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) \ ++ (((v) << 8) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR) ++#define BP_AUDIOOUT_ANACTRL_RSRVD2 6 ++#define BM_AUDIOOUT_ANACTRL_RSRVD2 0x000000C0 ++#define BF_AUDIOOUT_ANACTRL_RSRVD2(v) \ ++ (((v) << 6) & BM_AUDIOOUT_ANACTRL_RSRVD2) ++#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 ++#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 ++#define BP_AUDIOOUT_ANACTRL_RSRVD1 0 ++#define BM_AUDIOOUT_ANACTRL_RSRVD1 0x0000000F ++#define BF_AUDIOOUT_ANACTRL_RSRVD1(v) \ ++ (((v) << 0) & BM_AUDIOOUT_ANACTRL_RSRVD1) ++ ++#define HW_AUDIOOUT_TEST (0x000000a0) ++#define HW_AUDIOOUT_TEST_SET (0x000000a4) ++#define HW_AUDIOOUT_TEST_CLR (0x000000a8) ++#define HW_AUDIOOUT_TEST_TOG (0x000000ac) ++ ++#define BM_AUDIOOUT_TEST_RSRVD4 0x80000000 ++#define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 ++#define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 ++#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) \ ++ (((v) << 28) & BM_AUDIOOUT_TEST_HP_ANTIPOP) ++#define BM_AUDIOOUT_TEST_RSRVD3 0x08000000 ++#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x04000000 ++#define BM_AUDIOOUT_TEST_TM_LOOP 0x02000000 ++#define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x01000000 ++#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 ++#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 ++#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) \ ++ (((v) << 22) & BM_AUDIOOUT_TEST_HP_I1_ADJ) ++#define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 ++#define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x00300000 ++#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) \ ++ (((v) << 20) & BM_AUDIOOUT_TEST_HP_IALL_ADJ) ++#define BP_AUDIOOUT_TEST_RSRVD2 14 ++#define BM_AUDIOOUT_TEST_RSRVD2 0x000FC000 ++#define BF_AUDIOOUT_TEST_RSRVD2(v) \ ++ (((v) << 14) & BM_AUDIOOUT_TEST_RSRVD2) ++#define BM_AUDIOOUT_TEST_VAG_CLASSA 0x00002000 ++#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x00001000 ++#define BP_AUDIOOUT_TEST_RSRVD1 4 ++#define BM_AUDIOOUT_TEST_RSRVD1 0x00000FF0 ++#define BF_AUDIOOUT_TEST_RSRVD1(v) \ ++ (((v) << 4) & BM_AUDIOOUT_TEST_RSRVD1) ++#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP 0x00000008 ++#define BM_AUDIOOUT_TEST_DAC_CLASSA 0x00000004 ++#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x00000002 ++#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x00000001 ++ ++#define HW_AUDIOOUT_BISTCTRL (0x000000b0) ++#define HW_AUDIOOUT_BISTCTRL_SET (0x000000b4) ++#define HW_AUDIOOUT_BISTCTRL_CLR (0x000000b8) ++#define HW_AUDIOOUT_BISTCTRL_TOG (0x000000bc) ++ ++#define BP_AUDIOOUT_BISTCTRL_RSVD0 4 ++#define BM_AUDIOOUT_BISTCTRL_RSVD0 0xFFFFFFF0 ++#define BF_AUDIOOUT_BISTCTRL_RSVD0(v) \ ++ (((v) << 4) & BM_AUDIOOUT_BISTCTRL_RSVD0) ++#define BM_AUDIOOUT_BISTCTRL_FAIL 0x00000008 ++#define BM_AUDIOOUT_BISTCTRL_PASS 0x00000004 ++#define BM_AUDIOOUT_BISTCTRL_DONE 0x00000002 ++#define BM_AUDIOOUT_BISTCTRL_START 0x00000001 ++ ++#define HW_AUDIOOUT_BISTSTAT0 (0x000000c0) ++#define HW_AUDIOOUT_BISTSTAT0_SET (0x000000c4) ++#define HW_AUDIOOUT_BISTSTAT0_CLR (0x000000c8) ++#define HW_AUDIOOUT_BISTSTAT0_TOG (0x000000cc) ++ ++#define BP_AUDIOOUT_BISTSTAT0_RSVD0 24 ++#define BM_AUDIOOUT_BISTSTAT0_RSVD0 0xFF000000 ++#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v) \ ++ (((v) << 24) & BM_AUDIOOUT_BISTSTAT0_RSVD0) ++#define BP_AUDIOOUT_BISTSTAT0_DATA 0 ++#define BM_AUDIOOUT_BISTSTAT0_DATA 0x00FFFFFF ++#define BF_AUDIOOUT_BISTSTAT0_DATA(v) \ ++ (((v) << 0) & BM_AUDIOOUT_BISTSTAT0_DATA) ++ ++#define HW_AUDIOOUT_BISTSTAT1 (0x000000d0) ++#define HW_AUDIOOUT_BISTSTAT1_SET (0x000000d4) ++#define HW_AUDIOOUT_BISTSTAT1_CLR (0x000000d8) ++#define HW_AUDIOOUT_BISTSTAT1_TOG (0x000000dc) ++ ++#define BP_AUDIOOUT_BISTSTAT1_RSVD1 29 ++#define BM_AUDIOOUT_BISTSTAT1_RSVD1 0xE0000000 ++#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v) \ ++ (((v) << 29) & BM_AUDIOOUT_BISTSTAT1_RSVD1) ++#define BP_AUDIOOUT_BISTSTAT1_STATE 24 ++#define BM_AUDIOOUT_BISTSTAT1_STATE 0x1F000000 ++#define BF_AUDIOOUT_BISTSTAT1_STATE(v) \ ++ (((v) << 24) & BM_AUDIOOUT_BISTSTAT1_STATE) ++#define BP_AUDIOOUT_BISTSTAT1_RSVD0 8 ++#define BM_AUDIOOUT_BISTSTAT1_RSVD0 0x00FFFF00 ++#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v) \ ++ (((v) << 8) & BM_AUDIOOUT_BISTSTAT1_RSVD0) ++#define BP_AUDIOOUT_BISTSTAT1_ADDR 0 ++#define BM_AUDIOOUT_BISTSTAT1_ADDR 0x000000FF ++#define BF_AUDIOOUT_BISTSTAT1_ADDR(v) \ ++ (((v) << 0) & BM_AUDIOOUT_BISTSTAT1_ADDR) ++ ++#define HW_AUDIOOUT_ANACLKCTRL (0x000000e0) ++#define HW_AUDIOOUT_ANACLKCTRL_SET (0x000000e4) ++#define HW_AUDIOOUT_ANACLKCTRL_CLR (0x000000e8) ++#define HW_AUDIOOUT_ANACLKCTRL_TOG (0x000000ec) ++ ++#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 ++#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3 5 ++#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3 0x7FFFFFE0 ++#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v) \ ++ (((v) << 5) & BM_AUDIOOUT_ANACLKCTRL_RSRVD3) ++#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x00000010 ++#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2 0x00000008 ++#define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 ++#define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x00000007 ++#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) \ ++ (((v) << 0) & BM_AUDIOOUT_ANACLKCTRL_DACDIV) ++ ++#define HW_AUDIOOUT_DATA (0x000000f0) ++#define HW_AUDIOOUT_DATA_SET (0x000000f4) ++#define HW_AUDIOOUT_DATA_CLR (0x000000f8) ++#define HW_AUDIOOUT_DATA_TOG (0x000000fc) ++ ++#define BP_AUDIOOUT_DATA_HIGH 16 ++#define BM_AUDIOOUT_DATA_HIGH 0xFFFF0000 ++#define BF_AUDIOOUT_DATA_HIGH(v) \ ++ (((v) << 16) & BM_AUDIOOUT_DATA_HIGH) ++#define BP_AUDIOOUT_DATA_LOW 0 ++#define BM_AUDIOOUT_DATA_LOW 0x0000FFFF ++#define BF_AUDIOOUT_DATA_LOW(v) \ ++ (((v) << 0) & BM_AUDIOOUT_DATA_LOW) ++ ++#define HW_AUDIOOUT_SPEAKERCTRL (0x00000100) ++#define HW_AUDIOOUT_SPEAKERCTRL_SET (0x00000104) ++#define HW_AUDIOOUT_SPEAKERCTRL_CLR (0x00000108) ++#define HW_AUDIOOUT_SPEAKERCTRL_TOG (0x0000010c) ++ ++#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2 25 ++#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 0xFE000000 ++#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) \ ++ (((v) << 25) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD2) ++#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000 ++#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ 22 ++#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ 0x00C00000 ++#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) \ ++ (((v) << 22) & BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ) ++#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 20 ++#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 0x00300000 ++#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) \ ++ (((v) << 20) & BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ) ++#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1 16 ++#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 0x000F0000 ++#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) \ ++ (((v) << 16) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD1) ++#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER 14 ++#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER 0x0000C000 ++#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) \ ++ (((v) << 14) & BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER) ++#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 12 ++#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 0x00003000 ++#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) \ ++ (((v) << 12) & BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER) ++#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0 0 ++#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 0x00000FFF ++#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) \ ++ (((v) << 0) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD0) ++ ++#define HW_AUDIOOUT_VERSION (0x00000200) ++ ++#define BP_AUDIOOUT_VERSION_MAJOR 24 ++#define BM_AUDIOOUT_VERSION_MAJOR 0xFF000000 ++#define BF_AUDIOOUT_VERSION_MAJOR(v) \ ++ (((v) << 24) & BM_AUDIOOUT_VERSION_MAJOR) ++#define BP_AUDIOOUT_VERSION_MINOR 16 ++#define BM_AUDIOOUT_VERSION_MINOR 0x00FF0000 ++#define BF_AUDIOOUT_VERSION_MINOR(v) \ ++ (((v) << 16) & BM_AUDIOOUT_VERSION_MINOR) ++#define BP_AUDIOOUT_VERSION_STEP 0 ++#define BM_AUDIOOUT_VERSION_STEP 0x0000FFFF ++#define BF_AUDIOOUT_VERSION_STEP(v) \ ++ (((v) << 0) & BM_AUDIOOUT_VERSION_STEP) ++ ++/* AUDIOIN */ ++#define HW_AUDIOIN_CTRL (0x00000000) ++#define HW_AUDIOIN_CTRL_SET (0x00000004) ++#define HW_AUDIOIN_CTRL_CLR (0x00000008) ++#define HW_AUDIOIN_CTRL_TOG (0x0000000c) ++ ++#define BM_AUDIOIN_CTRL_SFTRST 0x80000000 ++#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 ++#define BP_AUDIOIN_CTRL_RSRVD3 21 ++#define BM_AUDIOIN_CTRL_RSRVD3 0x3FE00000 ++#define BF_AUDIOIN_CTRL_RSRVD3(v) \ ++ (((v) << 21) & BM_AUDIOIN_CTRL_RSRVD3) ++#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 ++#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x001F0000 ++#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) \ ++ (((v) << 16) & BM_AUDIOIN_CTRL_DMAWAIT_COUNT) ++#define BP_AUDIOIN_CTRL_RSRVD1 11 ++#define BM_AUDIOIN_CTRL_RSRVD1 0x0000F800 ++#define BF_AUDIOIN_CTRL_RSRVD1(v) \ ++ (((v) << 11) & BM_AUDIOIN_CTRL_RSRVD1) ++#define BM_AUDIOIN_CTRL_LR_SWAP 0x00000400 ++#define BM_AUDIOIN_CTRL_EDGE_SYNC 0x00000200 ++#define BM_AUDIOIN_CTRL_INVERT_1BIT 0x00000100 ++#define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x00000080 ++#define BM_AUDIOIN_CTRL_HPF_ENABLE 0x00000040 ++#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 ++#define BM_AUDIOIN_CTRL_LOOPBACK 0x00000010 ++#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 ++#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 ++#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 ++#define BM_AUDIOIN_CTRL_RUN 0x00000001 ++ ++#define HW_AUDIOIN_STAT (0x00000010) ++#define HW_AUDIOIN_STAT_SET (0x00000014) ++#define HW_AUDIOIN_STAT_CLR (0x00000018) ++#define HW_AUDIOIN_STAT_TOG (0x0000001c) ++ ++#define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 ++#define BP_AUDIOIN_STAT_RSRVD3 0 ++#define BM_AUDIOIN_STAT_RSRVD3 0x7FFFFFFF ++#define BF_AUDIOIN_STAT_RSRVD3(v) \ ++ (((v) << 0) & BM_AUDIOIN_STAT_RSRVD3) ++ ++#define HW_AUDIOIN_ADCSRR (0x00000020) ++#define HW_AUDIOIN_ADCSRR_SET (0x00000024) ++#define HW_AUDIOIN_ADCSRR_CLR (0x00000028) ++#define HW_AUDIOIN_ADCSRR_TOG (0x0000002c) ++ ++#define BM_AUDIOIN_ADCSRR_OSR 0x80000000 ++#define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 ++#define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 ++#define BP_AUDIOIN_ADCSRR_BASEMULT 28 ++#define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 ++#define BF_AUDIOIN_ADCSRR_BASEMULT(v) \ ++ (((v) << 28) & BM_AUDIOIN_ADCSRR_BASEMULT) ++#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 ++#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 ++#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 ++#define BM_AUDIOIN_ADCSRR_RSRVD2 0x08000000 ++#define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 ++#define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x07000000 ++#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) \ ++ (((v) << 24) & BM_AUDIOIN_ADCSRR_SRC_HOLD) ++#define BP_AUDIOIN_ADCSRR_RSRVD1 21 ++#define BM_AUDIOIN_ADCSRR_RSRVD1 0x00E00000 ++#define BF_AUDIOIN_ADCSRR_RSRVD1(v) \ ++ (((v) << 21) & BM_AUDIOIN_ADCSRR_RSRVD1) ++#define BP_AUDIOIN_ADCSRR_SRC_INT 16 ++#define BM_AUDIOIN_ADCSRR_SRC_INT 0x001F0000 ++#define BF_AUDIOIN_ADCSRR_SRC_INT(v) \ ++ (((v) << 16) & BM_AUDIOIN_ADCSRR_SRC_INT) ++#define BP_AUDIOIN_ADCSRR_RSRVD0 13 ++#define BM_AUDIOIN_ADCSRR_RSRVD0 0x0000E000 ++#define BF_AUDIOIN_ADCSRR_RSRVD0(v) \ ++ (((v) << 13) & BM_AUDIOIN_ADCSRR_RSRVD0) ++#define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 ++#define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x00001FFF ++#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) \ ++ (((v) << 0) & BM_AUDIOIN_ADCSRR_SRC_FRAC) ++ ++#define HW_AUDIOIN_ADCVOLUME (0x00000030) ++#define HW_AUDIOIN_ADCVOLUME_SET (0x00000034) ++#define HW_AUDIOIN_ADCVOLUME_CLR (0x00000038) ++#define HW_AUDIOIN_ADCVOLUME_TOG (0x0000003c) ++ ++#define BP_AUDIOIN_ADCVOLUME_RSRVD5 29 ++#define BM_AUDIOIN_ADCVOLUME_RSRVD5 0xE0000000 ++#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v) \ ++ (((v) << 29) & BM_AUDIOIN_ADCVOLUME_RSRVD5) ++#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 ++#define BP_AUDIOIN_ADCVOLUME_RSRVD4 26 ++#define BM_AUDIOIN_ADCVOLUME_RSRVD4 0x0C000000 ++#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v) \ ++ (((v) << 26) & BM_AUDIOIN_ADCVOLUME_RSRVD4) ++#define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x02000000 ++#define BM_AUDIOIN_ADCVOLUME_RSRVD3 0x01000000 ++#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 ++#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 ++#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) \ ++ (((v) << 16) & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT) ++#define BP_AUDIOIN_ADCVOLUME_RSRVD2 13 ++#define BM_AUDIOIN_ADCVOLUME_RSRVD2 0x0000E000 ++#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v) \ ++ (((v) << 13) & BM_AUDIOIN_ADCVOLUME_RSRVD2) ++#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x00001000 ++#define BP_AUDIOIN_ADCVOLUME_RSRVD1 8 ++#define BM_AUDIOIN_ADCVOLUME_RSRVD1 0x00000F00 ++#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v) \ ++ (((v) << 8) & BM_AUDIOIN_ADCVOLUME_RSRVD1) ++#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 ++#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF ++#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) \ ++ (((v) << 0) & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT) ++ ++#define HW_AUDIOIN_ADCDEBUG (0x00000040) ++#define HW_AUDIOIN_ADCDEBUG_SET (0x00000044) ++#define HW_AUDIOIN_ADCDEBUG_CLR (0x00000048) ++#define HW_AUDIOIN_ADCDEBUG_TOG (0x0000004c) ++ ++#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 ++#define BP_AUDIOIN_ADCDEBUG_RSRVD1 4 ++#define BM_AUDIOIN_ADCDEBUG_RSRVD1 0x7FFFFFF0 ++#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v) \ ++ (((v) << 4) & BM_AUDIOIN_ADCDEBUG_RSRVD1) ++#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x00000008 ++#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x00000004 ++#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x00000002 ++#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x00000001 ++ ++#define HW_AUDIOIN_ADCVOL (0x00000050) ++#define HW_AUDIOIN_ADCVOL_SET (0x00000054) ++#define HW_AUDIOIN_ADCVOL_CLR (0x00000058) ++#define HW_AUDIOIN_ADCVOL_TOG (0x0000005c) ++ ++#define BP_AUDIOIN_ADCVOL_RSRVD4 29 ++#define BM_AUDIOIN_ADCVOL_RSRVD4 0xE0000000 ++#define BF_AUDIOIN_ADCVOL_RSRVD4(v) \ ++ (((v) << 29) & BM_AUDIOIN_ADCVOL_RSRVD4) ++#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000 ++#define BP_AUDIOIN_ADCVOL_RSRVD3 26 ++#define BM_AUDIOIN_ADCVOL_RSRVD3 0x0C000000 ++#define BF_AUDIOIN_ADCVOL_RSRVD3(v) \ ++ (((v) << 26) & BM_AUDIOIN_ADCVOL_RSRVD3) ++#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x02000000 ++#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 ++#define BP_AUDIOIN_ADCVOL_RSRVD2 14 ++#define BM_AUDIOIN_ADCVOL_RSRVD2 0x00FFC000 ++#define BF_AUDIOIN_ADCVOL_RSRVD2(v) \ ++ (((v) << 14) & BM_AUDIOIN_ADCVOL_RSRVD2) ++#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 ++#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 ++#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) \ ++ (((v) << 12) & BM_AUDIOIN_ADCVOL_SELECT_LEFT) ++#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 ++#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 ++#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) \ ++ (((v) << 8) & BM_AUDIOIN_ADCVOL_GAIN_LEFT) ++#define BP_AUDIOIN_ADCVOL_RSRVD1 6 ++#define BM_AUDIOIN_ADCVOL_RSRVD1 0x000000C0 ++#define BF_AUDIOIN_ADCVOL_RSRVD1(v) \ ++ (((v) << 6) & BM_AUDIOIN_ADCVOL_RSRVD1) ++#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 ++#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 ++#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) \ ++ (((v) << 4) & BM_AUDIOIN_ADCVOL_SELECT_RIGHT) ++#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 ++#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F ++#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) \ ++ (((v) << 0) & BM_AUDIOIN_ADCVOL_GAIN_RIGHT) ++ ++#define HW_AUDIOIN_MICLINE (0x00000060) ++#define HW_AUDIOIN_MICLINE_SET (0x00000064) ++#define HW_AUDIOIN_MICLINE_CLR (0x00000068) ++#define HW_AUDIOIN_MICLINE_TOG (0x0000006c) ++ ++#define BP_AUDIOIN_MICLINE_RSRVD6 30 ++#define BM_AUDIOIN_MICLINE_RSRVD6 0xC0000000 ++#define BF_AUDIOIN_MICLINE_RSRVD6(v) \ ++ (((v) << 30) & BM_AUDIOIN_MICLINE_RSRVD6) ++#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 ++#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 ++#define BP_AUDIOIN_MICLINE_RSRVD5 25 ++#define BM_AUDIOIN_MICLINE_RSRVD5 0x0E000000 ++#define BF_AUDIOIN_MICLINE_RSRVD5(v) \ ++ (((v) << 25) & BM_AUDIOIN_MICLINE_RSRVD5) ++#define BM_AUDIOIN_MICLINE_MIC_SELECT 0x01000000 ++#define BP_AUDIOIN_MICLINE_RSRVD4 22 ++#define BM_AUDIOIN_MICLINE_RSRVD4 0x00C00000 ++#define BF_AUDIOIN_MICLINE_RSRVD4(v) \ ++ (((v) << 22) & BM_AUDIOIN_MICLINE_RSRVD4) ++#define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 ++#define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x00300000 ++#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) \ ++ (((v) << 20) & BM_AUDIOIN_MICLINE_MIC_RESISTOR) ++#define BM_AUDIOIN_MICLINE_RSRVD3 0x00080000 ++#define BP_AUDIOIN_MICLINE_MIC_BIAS 16 ++#define BM_AUDIOIN_MICLINE_MIC_BIAS 0x00070000 ++#define BF_AUDIOIN_MICLINE_MIC_BIAS(v) \ ++ (((v) << 16) & BM_AUDIOIN_MICLINE_MIC_BIAS) ++#define BP_AUDIOIN_MICLINE_RSRVD2 6 ++#define BM_AUDIOIN_MICLINE_RSRVD2 0x0000FFC0 ++#define BF_AUDIOIN_MICLINE_RSRVD2(v) \ ++ (((v) << 6) & BM_AUDIOIN_MICLINE_RSRVD2) ++#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4 ++#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x00000030 ++#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) \ ++ (((v) << 4) & BM_AUDIOIN_MICLINE_MIC_CHOPCLK) ++#define BP_AUDIOIN_MICLINE_RSRVD1 2 ++#define BM_AUDIOIN_MICLINE_RSRVD1 0x0000000C ++#define BF_AUDIOIN_MICLINE_RSRVD1(v) \ ++ (((v) << 2) & BM_AUDIOIN_MICLINE_RSRVD1) ++#define BP_AUDIOIN_MICLINE_MIC_GAIN 0 ++#define BM_AUDIOIN_MICLINE_MIC_GAIN 0x00000003 ++#define BF_AUDIOIN_MICLINE_MIC_GAIN(v) \ ++ (((v) << 0) & BM_AUDIOIN_MICLINE_MIC_GAIN) ++ ++#define HW_AUDIOIN_ANACLKCTRL (0x00000070) ++#define HW_AUDIOIN_ANACLKCTRL_SET (0x00000074) ++#define HW_AUDIOIN_ANACLKCTRL_CLR (0x00000078) ++#define HW_AUDIOIN_ANACLKCTRL_TOG (0x0000007c) ++ ++#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 ++#define BP_AUDIOIN_ANACLKCTRL_RSRVD4 11 ++#define BM_AUDIOIN_ANACLKCTRL_RSRVD4 0x7FFFF800 ++#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v) \ ++ (((v) << 11) & BM_AUDIOIN_ANACLKCTRL_RSRVD4) ++#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x00000400 ++#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x00000200 ++#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x00000100 ++#define BP_AUDIOIN_ANACLKCTRL_RSRVD3 6 ++#define BM_AUDIOIN_ANACLKCTRL_RSRVD3 0x000000C0 ++#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v) \ ++ (((v) << 6) & BM_AUDIOIN_ANACLKCTRL_RSRVD3) ++#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 4 ++#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 0x00000030 ++#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) \ ++ (((v) << 4) & BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT) ++#define BM_AUDIOIN_ANACLKCTRL_RSRVD2 0x00000008 ++#define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 ++#define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x00000007 ++#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) \ ++ (((v) << 0) & BM_AUDIOIN_ANACLKCTRL_ADCDIV) ++ ++#define HW_AUDIOIN_DATA (0x00000080) ++#define HW_AUDIOIN_DATA_SET (0x00000084) ++#define HW_AUDIOIN_DATA_CLR (0x00000088) ++#define HW_AUDIOIN_DATA_TOG (0x0000008c) ++ ++#define BP_AUDIOIN_DATA_HIGH 16 ++#define BM_AUDIOIN_DATA_HIGH 0xFFFF0000 ++#define BF_AUDIOIN_DATA_HIGH(v) \ ++ (((v) << 16) & BM_AUDIOIN_DATA_HIGH) ++#define BP_AUDIOIN_DATA_LOW 0 ++#define BM_AUDIOIN_DATA_LOW 0x0000FFFF ++#define BF_AUDIOIN_DATA_LOW(v) \ ++ (((v) << 0) & BM_AUDIOIN_DATA_LOW) ++ ++#define BV_AUDIOIN_ADCVOL_SELECT__MIC 0x00 ++ ++#endif /* __MXS_ADC_CODEC_H */ +--- a/sound/soc/mxs/Kconfig ++++ b/sound/soc/mxs/Kconfig +@@ -19,3 +19,13 @@ config SND_SOC_MXS_SGTL5000 + a sgtl5000 codec. + + endif # SND_MXS_SOC ++ ++ ++config SND_MXS_SOC_BUILTIN ++ tristate "SoC Audio for Freescale i.MX23 built-in codec" ++ depends on ARCH_MXS ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ select SND_SOC_MXS_BUILTIN_CODEC ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the MXS SAIF interface. +--- a/sound/soc/mxs/Makefile ++++ b/sound/soc/mxs/Makefile +@@ -8,3 +8,12 @@ obj-$(CONFIG_SND_MXS_SOC) += snd-soc-mxs + snd-soc-mxs-sgtl5000-objs := mxs-sgtl5000.o + + obj-$(CONFIG_SND_SOC_MXS_SGTL5000) += snd-soc-mxs-sgtl5000.o ++ ++# i.MX23 built-in audio Machine and Platform support ++snd-soc-mxs-builtin-pcm-objs := mxs-builtin-pcm.o ++snd-soc-mxs-builtin-dai-objs := mxs-builtin-dai.o ++snd-soc-mxs-builtin-audio-objs := mxs-builtin-audio.o ++ ++obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-pcm.o ++obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-dai.o ++obj-$(CONFIG_SND_MXS_SOC_BUILTIN) += snd-soc-mxs-builtin-audio.o +--- /dev/null ++++ b/sound/soc/mxs/mxs-builtin-audio.c +@@ -0,0 +1,120 @@ ++/* ++ * mxs-builtin-audio.c -- i.MX233 built-in codec ALSA Soc Audio driver ++ * ++ * Author: Michal Ulianko ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct snd_soc_dai_link mxs_adc_dai_link[] = { ++ { ++ .name = "MXS ADC/DAC", ++ .stream_name = "MXS ADC/DAC", ++ .codec_dai_name = "mxs-builtin-codec-dai", ++// .codec_name = "mxs-builtin-codec", ++// .cpu_dai_name = "mxs-builtin-cpu-dai", ++// .platform_name = "mxs-builtin-cpu-dai", ++// .ops = &mxs_sgtl5000_hifi_ops, ++ }, ++}; ++ ++static struct snd_soc_card mxs_adc_audio = { ++ .name = "mxs-builtin-audio", ++ .owner = THIS_MODULE, ++ .dai_link = mxs_adc_dai_link, ++ .num_links = ARRAY_SIZE(mxs_adc_dai_link), ++}; ++ ++static int mxsadc_audio_probe_dt(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct device_node *cpu_dai_np, *codec_np; ++ int ret = 0; ++ ++ if (!np) ++ return 1; /* no device tree */ ++ ++ cpu_dai_np = of_parse_phandle(np, "cpu-dai", 0); ++ codec_np = of_parse_phandle(np, "audio-codec", 0); ++ if (!cpu_dai_np || !codec_np) { ++ dev_err(&pdev->dev, "phandle missing or invalid\n"); ++ return -EINVAL; ++ } ++ ++ mxs_adc_dai_link[0].codec_name = NULL; ++ mxs_adc_dai_link[0].codec_of_node = codec_np; ++ mxs_adc_dai_link[0].cpu_dai_name = NULL; ++ mxs_adc_dai_link[0].cpu_of_node = cpu_dai_np; ++ mxs_adc_dai_link[0].platform_name = NULL; ++ mxs_adc_dai_link[0].platform_of_node = cpu_dai_np; ++ ++// of_node_put(codec_np); ++// of_node_put(cpu_dai_np); ++ ++ return ret; ++} ++ ++static int mxsadc_audio_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = &mxs_adc_audio; ++ int ret; ++ ++ ret = mxsadc_audio_probe_dt(pdev); ++ if (ret < 0) ++ return ret; ++ ++ card->dev = &pdev->dev; ++ platform_set_drvdata(pdev, card); ++ ++ ret = snd_soc_register_card(card); ++ if (ret) { ++ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int mxsadc_audio_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = platform_get_drvdata(pdev); ++ ++ snd_soc_unregister_card(card); ++ ++ return 0; ++} ++ ++static const struct of_device_id mxs_adc_audio_dt_ids[] = { ++ { .compatible = "fsl,mxs-builtin-audio", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, mxs_adc_audio_dt_ids); ++ ++static struct platform_driver mxs_adc_audio_driver = { ++ .driver = { ++ .name = "mxs-builtin-audio", ++ .owner = THIS_MODULE, ++ .of_match_table = mxs_adc_audio_dt_ids, ++ }, ++ .probe = mxsadc_audio_probe, ++ .remove = mxsadc_audio_remove, ++}; ++ ++module_platform_driver(mxs_adc_audio_driver); ++ ++MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Machine Driver"); ++MODULE_AUTHOR("Michal Ulianko "); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/mxs/mxs-builtin-dai.c +@@ -0,0 +1,588 @@ ++/* ++ * mxs-builtin-dai.c -- i.MX233 built-in codec ALSA Soc Audio driver ++ * ++ * Author: Michal Ulianko ++ * ++ * Based on sound/soc/mxs/mxs-adc.c for kernel 2.6.35 ++ * by Vladislav Buzov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/mxs-builtin-codec.h" ++#include "mxs-builtin-pcm.h" ++ ++#define ADC_VOLUME_MIN 0x37 ++ ++/* TODO Use codec IO function soc snd write etc, instead of __writel __readl */ ++ ++// TODO use container_of ++struct mxs_irq_data { ++ struct snd_pcm_substream *substream; ++ struct mxs_adc_priv *mxs_adc; ++}; ++ ++struct mxs_adc_priv { ++ struct mxs_irq_data irq_data; ++ int dma_adc_err_irq; ++ int dma_dac_err_irq; ++ int hp_short_irq; ++ void __iomem *audioin_base; ++ void __iomem *audioout_base; ++ void __iomem *rtc_base; ++}; ++ ++typedef struct { ++ struct work_struct work; ++ struct timer_list timer; ++ ++ /* target workqueue and CPU ->timer uses to queue ->work */ ++ struct workqueue_struct *wq; ++ int cpu; ++ ++ struct mxs_adc_priv *mxs_adc; ++} my_delayed_work_t; ++ ++// static struct delayed_work work; ++// static struct delayed_work adc_ramp_work; ++// static struct delayed_work dac_ramp_work; ++// static struct delayed_work test; ++static my_delayed_work_t work; ++static my_delayed_work_t adc_ramp_work; ++static my_delayed_work_t dac_ramp_work; ++static my_delayed_work_t test; ++static bool adc_ramp_done = 1; ++static bool dac_ramp_done = 1; ++ ++static inline void mxs_adc_schedule_work(struct delayed_work *work) ++{ ++ schedule_delayed_work(work, HZ / 10); ++} ++ ++static void mxs_adc_work(struct work_struct *work) ++{ ++ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc; ++ /* disable irq */ ++ disable_irq(mxs_adc->hp_short_irq); ++ ++ while (true) { ++ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_CLR); ++ msleep(10); ++ if ((__raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL) ++ & BM_AUDIOOUT_ANACTRL_SHORT_LR_STS) != 0) { ++ /* rearm the short protection */ ++ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORTMODE_LR, ++ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS, ++ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ __raw_writel(BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(0x1), ++ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET); ++ ++ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_SET); ++ printk(KERN_WARNING "WARNING : Headphone LR short!\r\n"); ++ } else { ++ printk(KERN_WARNING "INFO : Headphone LR no longer short!\r\n"); ++ break; ++ } ++ msleep(1000); ++ } ++ ++ /* power up the HEADPHONE and un-mute the HPVOL */ ++ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_CLR); ++ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_CLR); ++ ++ /* enable irq for next short detect*/ ++ enable_irq(mxs_adc->hp_short_irq); ++} ++ ++static void mxs_adc_schedule_ramp_work(struct delayed_work *work) ++{ ++ schedule_delayed_work(work, msecs_to_jiffies(2)); ++ adc_ramp_done = 0; ++} ++ ++static void mxs_adc_ramp_work(struct work_struct *work) ++{ ++ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc; ++ u32 reg = 0; ++ u32 reg1 = 0; ++ u32 reg2 = 0; ++ u32 l, r; ++ u32 ll, rr; ++ int i; ++ ++ reg = __raw_readl(mxs_adc->audioin_base + \ ++ HW_AUDIOIN_ADCVOLUME); ++ ++ reg1 = reg & ~BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT; ++ reg1 = reg1 & ~BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT; ++ /* minimize adc volume */ ++ reg2 = reg1 | ++ BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(ADC_VOLUME_MIN) | ++ BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(ADC_VOLUME_MIN); ++ __raw_writel(reg2, ++ mxs_adc->audioin_base + HW_AUDIOIN_ADCVOLUME); ++ msleep(1); ++ ++ l = (reg & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT) >> ++ BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT; ++ r = (reg & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT) >> ++ BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT; ++ ++ /* fade in adc vol */ ++ for (i = ADC_VOLUME_MIN; (i < l) || (i < r);) { ++ i += 0x8; ++ ll = i < l ? i : l; ++ rr = i < r ? i : r; ++ reg2 = reg1 | ++ BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(ll) | ++ BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(rr); ++ __raw_writel(reg2, ++ mxs_adc->audioin_base + HW_AUDIOIN_ADCVOLUME); ++ msleep(1); ++ } ++ adc_ramp_done = 1; ++} ++ ++static void mxs_dac_schedule_ramp_work(struct delayed_work *work) ++{ ++ schedule_delayed_work(work, msecs_to_jiffies(2)); ++ dac_ramp_done = 0; ++} ++ ++static void mxs_dac_ramp_work(struct work_struct *work) ++{ ++ struct mxs_adc_priv *mxs_adc = ((my_delayed_work_t *)work)->mxs_adc; ++ u32 reg = 0; ++ u32 reg1 = 0; ++ u32 l, r; ++ u32 ll, rr; ++ int i; ++ ++ /* unmute hp and speaker */ ++ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_CLR); ++ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_SPEAKERCTRL_CLR); ++ ++ reg = __raw_readl(mxs_adc->audioout_base + \ ++ HW_AUDIOOUT_HPVOL); ++ ++ reg1 = reg & ~BM_AUDIOOUT_HPVOL_VOL_LEFT; ++ reg1 = reg1 & ~BM_AUDIOOUT_HPVOL_VOL_RIGHT; ++ ++ l = (reg & BM_AUDIOOUT_HPVOL_VOL_LEFT) >> ++ BP_AUDIOOUT_HPVOL_VOL_LEFT; ++ r = (reg & BM_AUDIOOUT_HPVOL_VOL_RIGHT) >> ++ BP_AUDIOOUT_HPVOL_VOL_RIGHT; ++ /* fade in hp vol */ ++ for (i = 0x7f; i > 0 ;) { ++ i -= 0x8; ++ ll = i > (int)l ? i : l; ++ rr = i > (int)r ? i : r; ++ reg = reg1 | BF_AUDIOOUT_HPVOL_VOL_LEFT(ll) ++ | BF_AUDIOOUT_HPVOL_VOL_RIGHT(rr); ++ __raw_writel(reg, ++ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL); ++ msleep(1); ++ } ++ dac_ramp_done = 1; ++} ++ ++/* IRQs */ ++static irqreturn_t mxs_short_irq(int irq, void *dev_id) ++{ ++ struct mxs_adc_priv *mxs_adc = dev_id; ++ //struct snd_pcm_substream *substream = mxs_adc->irq_data.substream; ++ ++ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORTMODE_LR, ++ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ __raw_writel(BM_AUDIOOUT_ANACTRL_SHORT_LR_STS, ++ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_CLR); ++ __raw_writel(BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(0x1), ++ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET); ++ ++ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_SET); ++ __raw_writel(BM_AUDIOOUT_PWRDN_HEADPHONE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN_SET); ++ __raw_writel(BM_AUDIOOUT_ANACTRL_HP_CLASSAB, ++ mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL_SET); ++ ++ mxs_adc_schedule_work((struct delayed_work *) &work); ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t mxs_err_irq(int irq, void *dev_id) ++{ ++ struct mxs_adc_priv *mxs_adc = dev_id; ++ struct snd_pcm_substream *substream = mxs_adc->irq_data.substream; ++ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; ++ u32 ctrl_reg; ++ u32 overflow_mask; ++ u32 underflow_mask; ++ ++ if (playback) { ++ ctrl_reg = __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_CTRL); ++ underflow_mask = BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ; ++ overflow_mask = BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ; ++ } else { ++ ctrl_reg = __raw_readl(mxs_adc->audioin_base + HW_AUDIOIN_CTRL); ++ underflow_mask = BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ; ++ overflow_mask = BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ; ++ } ++ ++ if (ctrl_reg & underflow_mask) { ++ printk(KERN_DEBUG "%s underflow detected\n", ++ playback ? "DAC" : "ADC"); ++ ++ if (playback) ++ __raw_writel( ++ BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ, ++ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR); ++ else ++ __raw_writel( ++ BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ, ++ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR); ++ ++ } else if (ctrl_reg & overflow_mask) { ++ printk(KERN_DEBUG "%s overflow detected\n", ++ playback ? "DAC" : "ADC"); ++ ++ if (playback) ++ __raw_writel( ++ BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ, ++ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR); ++ else ++ __raw_writel(BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ, ++ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR); ++ } else ++ printk(KERN_WARNING "Unknown DAC error interrupt\n"); ++ ++ return IRQ_HANDLED; ++} ++/* END IRQs */ ++ ++static int mxs_trigger(struct snd_pcm_substream *substream, ++ int cmd, ++ struct snd_soc_dai *cpu_dai) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai); ++ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ ++ if (playback) { ++ /* enable the fifo error interrupt */ ++ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN, ++ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_SET); ++ /* write a data to data reg to trigger the transfer */ ++ __raw_writel(0x0, ++ mxs_adc->audioout_base + HW_AUDIOOUT_DATA); ++ mxs_dac_schedule_ramp_work((struct delayed_work *) &dac_ramp_work); ++ } else { ++// mxs_dma_get_info(prtd->dma_ch, &dma_info); ++// cur_bar1 = dma_info.buf_addr; ++// xfer_count1 = dma_info.xfer_count; ++ ++ __raw_writel(BM_AUDIOIN_CTRL_RUN, ++ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_SET); ++ udelay(100); ++ ++// mxs_dma_get_info(prtd->dma_ch, &dma_info); ++// cur_bar2 = dma_info.buf_addr; ++// xfer_count2 = dma_info.xfer_count; ++// ++// /* check if DMA getting stuck */ ++// if ((xfer_count1 == xfer_count2) && (cur_bar1 == cur_bar2)) ++// /* read a data from data reg to trigger the receive */ ++// reg = __raw_readl(mxs_adc->audioin_base + HW_AUDIOIN_DATA); ++ ++ mxs_adc_schedule_ramp_work((struct delayed_work *) &adc_ramp_work); ++ } ++ break; ++ ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ ++ if (playback) { ++// printk(KERN_INFO "SNDRV_PCM_TRIGGER_START\n"); ++// printk(KERN_INFO "ctrl:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_CTRL)); ++// printk(KERN_INFO "stat:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_STAT)); ++// printk(KERN_INFO "srr:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACSRR)); ++// printk(KERN_INFO "vol:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACVOLUME)); ++// printk(KERN_INFO "debug:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_DACDEBUG)); ++// printk(KERN_INFO "hpvol:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL)); ++// printk(KERN_INFO "pwrdn:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_PWRDN)); ++// printk(KERN_INFO "refc:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_REFCTRL)); ++// printk(KERN_INFO "anac:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACTRL)); ++// printk(KERN_INFO "test:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_TEST)); ++// printk(KERN_INFO "bist:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_BISTCTRL)); ++// printk(KERN_INFO "anaclk:%x\n", __raw_readl(mxs_adc->audioout_base + HW_AUDIOOUT_ANACLKCTRL)); ++ ++ if (dac_ramp_done == 0) { ++ cancel_delayed_work((struct delayed_work *) &dac_ramp_work); ++ dac_ramp_done = 1; ++ } ++ __raw_writel(BM_AUDIOOUT_HPVOL_MUTE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_HPVOL_SET); ++ __raw_writel(BM_AUDIOOUT_SPEAKERCTRL_MUTE, ++ mxs_adc->audioout_base + HW_AUDIOOUT_SPEAKERCTRL_SET); ++ /* disable the fifo error interrupt */ ++ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN, ++ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR); ++ mdelay(50); ++ } else { ++ if (adc_ramp_done == 0) { ++ cancel_delayed_work((struct delayed_work *) &adc_ramp_work); ++ adc_ramp_done = 1; ++ } ++ __raw_writel(BM_AUDIOIN_CTRL_RUN, ++ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR); ++ } ++ break; ++ ++ default: ++ printk(KERN_ERR "TRIGGER ERROR\n"); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++static int mxs_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *cpu_dai) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai); ++ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; ++ mxs_adc->irq_data.mxs_adc = mxs_adc; ++ mxs_adc->irq_data.substream = substream; ++ ++ work.mxs_adc = mxs_adc; ++ adc_ramp_work.mxs_adc = mxs_adc; ++ dac_ramp_work.mxs_adc = mxs_adc; ++ test.mxs_adc = mxs_adc; ++ INIT_DELAYED_WORK(&work, mxs_adc_work); ++ INIT_DELAYED_WORK(&adc_ramp_work, mxs_adc_ramp_work); ++ INIT_DELAYED_WORK(&dac_ramp_work, mxs_dac_ramp_work); ++ ++ /* Enable error interrupt */ ++ if (playback) { ++ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ, ++ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR); ++ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ, ++ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR); ++ } else { ++ __raw_writel(BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ, ++ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR); ++ __raw_writel(BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ, ++ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR); ++ __raw_writel(BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN, ++ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_SET); ++ } ++ ++ return 0; ++} ++ ++static void mxs_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *cpu_dai) ++{ ++ struct mxs_adc_priv *mxs_adc = snd_soc_dai_get_drvdata(cpu_dai); ++ int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 1 : 0; ++ ++ /* Disable error interrupt */ ++ if (playback) { ++ __raw_writel(BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN, ++ mxs_adc->audioout_base + HW_AUDIOOUT_CTRL_CLR); ++ } else { ++ __raw_writel(BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN, ++ mxs_adc->audioin_base + HW_AUDIOIN_CTRL_CLR); ++ } ++} ++ ++#define MXS_ADC_RATES SNDRV_PCM_RATE_8000_192000 ++#define MXS_ADC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) ++ ++static const struct snd_soc_dai_ops mxs_adc_dai_ops = { ++ .startup = mxs_startup, ++ .trigger = mxs_trigger, ++ .shutdown = mxs_shutdown, ++}; ++ ++static int mxs_dai_probe(struct snd_soc_dai *dai) ++{ ++ // TODO This does not make any sense. ++ struct mxs_adc_priv *mxs_adc = dev_get_drvdata(dai->dev); ++ ++ snd_soc_dai_set_drvdata(dai, mxs_adc); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_driver mxs_adc_dai = { ++ .name = "mxs-builtin-cpu-dai", ++ .probe = mxs_dai_probe, ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = MXS_ADC_RATES, ++ .formats = MXS_ADC_FORMATS, ++ }, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = MXS_ADC_RATES, ++ .formats = MXS_ADC_FORMATS, ++ }, ++ .ops = &mxs_adc_dai_ops, ++}; ++ ++static const struct snd_soc_component_driver mxs_adc_component = { ++ .name = "mxs-xxx", //TODO change this name ++}; ++ ++static int mxs_adc_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct mxs_adc_priv *mxs_adc; ++ int ret = 0; ++ ++ if (!np) ++ return -EINVAL; ++ ++ mxs_adc = devm_kzalloc(&pdev->dev, sizeof(*mxs_adc), GFP_KERNEL); ++ if (!mxs_adc) ++ return -ENOMEM; ++ ++ mxs_adc->audioout_base = devm_ioremap(&pdev->dev, 0x80048000, 0x2000); ++ if (IS_ERR(mxs_adc->audioout_base)) ++ return PTR_ERR(mxs_adc->audioout_base); ++ ++ mxs_adc->audioin_base = devm_ioremap(&pdev->dev, 0x8004c000, 0x2000); ++ if (IS_ERR(mxs_adc->audioin_base)) ++ return PTR_ERR(mxs_adc->audioin_base); ++ ++ mxs_adc->rtc_base = devm_ioremap(&pdev->dev, 0x8005c000, 0x2000); ++ if (IS_ERR(mxs_adc->rtc_base)) ++ return PTR_ERR(mxs_adc->rtc_base); ++ ++ /* Get IRQ numbers */ ++ mxs_adc->dma_adc_err_irq = platform_get_irq(pdev, 0); ++ if (mxs_adc->dma_adc_err_irq < 0) { ++ ret = mxs_adc->dma_adc_err_irq; ++ dev_err(&pdev->dev, "failed to get ADC DMA ERR irq resource: %d\n", ret); ++ return ret; ++ } ++ ++ mxs_adc->dma_dac_err_irq = platform_get_irq(pdev, 1); ++ if (mxs_adc->dma_dac_err_irq < 0) { ++ ret = mxs_adc->dma_dac_err_irq; ++ dev_err(&pdev->dev, "failed to get DAC DMA ERR irq resource: %d\n", ret); ++ return ret; ++ } ++ ++ mxs_adc->hp_short_irq = platform_get_irq(pdev, 2); ++ if (mxs_adc->hp_short_irq < 0) { ++ ret = mxs_adc->hp_short_irq; ++ dev_err(&pdev->dev, "failed to get HP_SHORT irq resource: %d\n", ret); ++ return ret; ++ } ++ ++ /* Request IRQs */ ++ ret = devm_request_irq(&pdev->dev, mxs_adc->dma_adc_err_irq, mxs_err_irq, 0, "MXS DAC and ADC Error", ++ mxs_adc); ++ if (ret) { ++ printk(KERN_ERR "%s: Unable to request ADC/DAC error irq %d\n", ++ __func__, mxs_adc->dma_adc_err_irq); ++ return ret; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, mxs_adc->dma_dac_err_irq, mxs_err_irq, 0, "MXS DAC and ADC Error", ++ mxs_adc); ++ if (ret) { ++ printk(KERN_ERR "%s: Unable to request ADC/DAC error irq %d\n", ++ __func__, mxs_adc->dma_dac_err_irq); ++ return ret; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, mxs_adc->hp_short_irq, mxs_short_irq, ++ IRQF_DISABLED | IRQF_SHARED, "MXS DAC and ADC HP SHORT", mxs_adc); ++ if (ret) { ++ printk(KERN_ERR "%s: Unable to request ADC/DAC HP SHORT irq %d\n", ++ __func__, mxs_adc->hp_short_irq); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, mxs_adc); ++ ++ ret = snd_soc_register_component(&pdev->dev, &mxs_adc_component, &mxs_adc_dai, 1); ++ if (ret) { ++ dev_err(&pdev->dev, "register DAI failed\n"); ++ return ret; ++ } ++ ++ ret = mxs_adc_pcm_platform_register(&pdev->dev); ++ if (ret) { ++ dev_err(&pdev->dev, "register PCM failed: %d\n", ret); ++ goto failed_pdev_alloc; ++ } ++ ++ return 0; ++ ++failed_pdev_alloc: ++ snd_soc_unregister_component(&pdev->dev); ++ ++ return ret; ++} ++ ++static int mxs_adc_remove(struct platform_device *pdev) ++{ ++ mxs_adc_pcm_platform_unregister(&pdev->dev); ++ snd_soc_unregister_component(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id mxs_adc_dai_dt_ids[] = { ++ { .compatible = "fsl,mxs-builtin-cpu-dai", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, mxs_adc_dai_dt_ids); ++ ++static struct platform_driver mxs_adc_dai_driver = { ++ .probe = mxs_adc_probe, ++ .remove = mxs_adc_remove, ++ ++ .driver = { ++ .name = "mxs-builtin-cpu-dai", ++ .owner = THIS_MODULE, ++ .of_match_table = mxs_adc_dai_dt_ids, ++ }, ++}; ++ ++module_platform_driver(mxs_adc_dai_driver); ++ ++MODULE_DESCRIPTION("Freescale MXS ADC/DAC SoC Codec DAI Driver"); ++MODULE_AUTHOR("Michal Ulianko "); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/mxs/mxs-builtin-pcm.c +@@ -0,0 +1,69 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * Based on sound/soc/imx/imx-pcm-dma-mx2.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "mxs-builtin-pcm.h" ++ ++static const struct snd_pcm_hardware snd_mxs_hardware = { ++ .info = SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID | ++ SNDRV_PCM_INFO_PAUSE | ++ SNDRV_PCM_INFO_RESUME | ++ SNDRV_PCM_INFO_INTERLEAVED, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S20_3LE | ++ SNDRV_PCM_FMTBIT_S24_LE, ++ .channels_min = 2, ++ .channels_max = 2, ++ .period_bytes_min = 32, ++ .period_bytes_max = 8192, ++ .periods_min = 1, ++ .periods_max = 52, ++ .buffer_bytes_max = 64 * 1024, ++ .fifo_size = 32, ++}; ++ ++static const struct snd_dmaengine_pcm_config mxs_dmaengine_pcm_config = { ++ .pcm_hardware = &snd_mxs_hardware, ++ .prealloc_buffer_size = 64 * 1024, ++}; ++ ++int mxs_adc_pcm_platform_register(struct device *dev) ++{ ++ return snd_dmaengine_pcm_register(dev, &mxs_dmaengine_pcm_config, ++ SND_DMAENGINE_PCM_FLAG_NO_RESIDUE); ++} ++EXPORT_SYMBOL_GPL(mxs_adc_pcm_platform_register); ++ ++void mxs_adc_pcm_platform_unregister(struct device *dev) ++{ ++ snd_dmaengine_pcm_unregister(dev); ++} ++EXPORT_SYMBOL_GPL(mxs_adc_pcm_platform_unregister); ++ ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/sound/soc/mxs/mxs-builtin-pcm.h +@@ -0,0 +1,25 @@ ++/* ++ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. ++ */ ++ ++#ifndef _MXS_PCM_H ++#define _MXS_PCM_H ++ ++int mxs_adc_pcm_platform_register(struct device *dev); ++void mxs_adc_pcm_platform_unregister(struct device *dev); ++ ++#endif diff --git a/target/linux/mxs/patches-3.18/101-soc-audio-dts.patch b/target/linux/mxs/patches-3.18/101-soc-audio-dts.patch new file mode 100644 index 0000000..3c3ad86 --- /dev/null +++ b/target/linux/mxs/patches-3.18/101-soc-audio-dts.patch @@ -0,0 +1,39 @@ +--- a/arch/arm/boot/dts/imx23-olinuxino.dts ++++ b/arch/arm/boot/dts/imx23-olinuxino.dts +@@ -89,6 +89,25 @@ + usbphy0: usbphy@8007c000 { + status = "okay"; + }; ++ ++ codec: mxs-builtin-codec { ++ compatible = "fsl,mxs-builtin-codec"; ++ reg = <0x80048000 0x2000>, <0x8004c000 0x2000>, ++ <0x8005c000 0x2000>; ++ reg-names = "audioout", "audioin", "rtc"; ++ clocks = <&clks 31>; ++ clock-names = "filt"; ++ }; ++ ++ platform_dai: mxs-builtin-cpu-dai { ++ compatible = "fsl,mxs-builtin-cpu-dai"; ++ reg = <0x80048000 0x2000>, <0x8004c000 0x2000>, ++ <0x8005c000 0x2000>; ++ reg-names = "audioout", "audioin", "rtc"; ++ interrupts = <8 6 4>; ++ dmas = <&dma_apbx 0>, <&dma_apbx 1>; ++ dma-names = "rx", "tx"; ++ }; + }; + }; + +@@ -127,4 +146,10 @@ + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + }; ++ ++ mxs-builtin-audio { ++ compatible = "fsl,mxs-builtin-audio"; ++ audio-codec = <&codec>; ++ cpu-dai = <&platform_dai>; ++ }; + }; diff --git a/target/linux/mxs/patches-3.18/120-dt-add-i2c.patch b/target/linux/mxs/patches-3.18/120-dt-add-i2c.patch new file mode 100644 index 0000000..43b42ce --- /dev/null +++ b/target/linux/mxs/patches-3.18/120-dt-add-i2c.patch @@ -0,0 +1,79 @@ +--- a/arch/arm/boot/dts/imx23.dtsi ++++ b/arch/arm/boot/dts/imx23.dtsi +@@ -147,6 +147,39 @@ + fsl,pull-up = ; + }; + ++ i2c0_pins_a: i2c0@0 { ++ reg = <0>; ++ fsl,pinmux-ids = < ++ 0x01e0 /* MX23_PAD_I2C_SCL__I2C_SCL */ ++ 0x01f0 /* MX23_PAD_I2C_SDA__I2C_SDA */ ++ >; ++ fsl,drive-strength = <1>; ++ fsl,voltage = <1>; ++ fsl,pull-up = <1>; ++ }; ++ ++ i2c1_pins_a: i2c1@0 { ++ reg = <0>; ++ fsl,pinmux-ids = < ++ 0x1171 /* MX23_PAD_LCD_ENABLE__I2C_SCL */ ++ 0x1181 /* MX23_PAD_LCD_HSYNC__I2C_SDA */ ++ >; ++ fsl,drive-strength = <1>; ++ fsl,voltage = <1>; ++ fsl,pull-up = <1>; ++ }; ++ ++ i2c2_pins_a: i2c2@0 { ++ reg = <0>; ++ fsl,pinmux-ids = < ++ 0x2031 /* MX23_PAD_SSP1_DATA1__I2C_SCL */ ++ 0x2041 /* MX23_PAD_SSP1_DATA2__I2C_SDA */ ++ >; ++ fsl,drive-strength = <1>; ++ fsl,voltage = <1>; ++ fsl,pull-up = <1>; ++ }; ++ + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < +@@ -445,7 +478,12 @@ + }; + + i2c@80058000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "fsl,imx23-i2c"; + reg = <0x80058000 0x2000>; ++ interrupts = <27>; ++ clock-frequency = <100000>; + dmas = <&dma_apbx 3>; + dma-names = "rx-tx"; + status = "disabled"; +--- a/arch/arm/boot/dts/imx23-olinuxino.dts ++++ b/arch/arm/boot/dts/imx23-olinuxino.dts +@@ -74,6 +74,12 @@ + status = "okay"; + }; + ++ i2c0: i2c@80058000 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins_a>; ++ status = "okay"; ++ }; ++ + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; +@@ -89,7 +95,7 @@ + usbphy0: usbphy@8007c000 { + status = "okay"; + }; +- ++ + codec: mxs-builtin-codec { + compatible = "fsl,mxs-builtin-codec"; + reg = <0x80048000 0x2000>, <0x8004c000 0x2000>, diff --git a/target/linux/mxs/patches-4.1/100-mxs-select-syscon.patch b/target/linux/mxs/patches-4.1/100-mxs-select-syscon.patch new file mode 100644 index 0000000..81ebec4 --- /dev/null +++ b/target/linux/mxs/patches-4.1/100-mxs-select-syscon.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/mach-mxs/Kconfig ++++ b/arch/arm/mach-mxs/Kconfig +@@ -17,6 +17,7 @@ config ARCH_MXS + depends on ARCH_MULTI_V5 + select ARCH_REQUIRE_GPIOLIB + select CLKSRC_MMIO ++ select MFD_SYSCON + select PINCTRL + select SOC_BUS + select SOC_IMX23 diff --git a/target/linux/mxs/patches-4.1/101-mxs-add-mxs_power.patch b/target/linux/mxs/patches-4.1/101-mxs-add-mxs_power.patch new file mode 100644 index 0000000..104736c --- /dev/null +++ b/target/linux/mxs/patches-4.1/101-mxs-add-mxs_power.patch @@ -0,0 +1,166 @@ +--- a/drivers/power/Kconfig ++++ b/drivers/power/Kconfig +@@ -43,6 +43,14 @@ config MAX8925_POWER + Say Y here to enable support for the battery charger in the Maxim + MAX8925 PMIC. + ++config MXS_POWER ++ tristate "Freescale MXS power subsystem support" ++ depends on ARCH_MXS || COMPILE_TEST ++ help ++ Say Y here to enable support for the Freescale i.MX23/i.MX28 ++ power subsystem. This is a requirement to get access to on-chip ++ regulators, battery charger and many more. ++ + config WM831X_BACKUP + tristate "WM831X backup battery charger support" + depends on MFD_WM831X +--- a/drivers/power/Makefile ++++ b/drivers/power/Makefile +@@ -10,6 +10,7 @@ obj-$(CONFIG_GENERIC_ADC_BATTERY) += gen + obj-$(CONFIG_PDA_POWER) += pda_power.o + obj-$(CONFIG_APM_POWER) += apm_power.o + obj-$(CONFIG_MAX8925_POWER) += max8925_power.o ++obj-$(CONFIG_MXS_POWER) += mxs_power.o + obj-$(CONFIG_WM831X_BACKUP) += wm831x_backup.o + obj-$(CONFIG_WM831X_POWER) += wm831x_power.o + obj-$(CONFIG_WM8350_POWER) += wm8350_power.o +--- /dev/null ++++ b/drivers/power/mxs_power.c +@@ -0,0 +1,136 @@ ++/* ++ * Freescale MXS power subsystem ++ * ++ * Copyright (C) 2014 Stefan Wahren ++ * ++ * Inspired by imx-bootlets ++ */ ++ ++/* ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BM_POWER_CTRL_POLARITY_VBUSVALID BIT(5) ++#define BM_POWER_CTRL_VBUSVALID_IRQ BIT(4) ++#define BM_POWER_CTRL_ENIRQ_VBUS_VALID BIT(3) ++ ++#define HW_POWER_5VCTRL_OFFSET 0x10 ++ ++#define BM_POWER_5VCTRL_VBUSVALID_THRESH (7 << 8) ++#define BM_POWER_5VCTRL_PWDN_5VBRNOUT BIT(7) ++#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT BIT(6) ++#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT BIT(4) ++ ++#define HW_POWER_5VCTRL_VBUSVALID_THRESH_4_40V (5 << 8) ++ ++struct mxs_power_data { ++ void __iomem *base_addr; ++ struct power_supply *ac; ++}; ++ ++static enum power_supply_property mxs_power_ac_props[] = { ++ POWER_SUPPLY_PROP_ONLINE, ++}; ++ ++static int mxs_power_ac_get_property(struct power_supply *psy, ++ enum power_supply_property psp, ++ union power_supply_propval *val) ++{ ++ int ret = 0; ++ ++ switch (psp) { ++ case POWER_SUPPLY_PROP_ONLINE: ++ val->intval = 1; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ return ret; ++} ++ ++static const struct of_device_id of_mxs_power_match[] = { ++ { .compatible = "fsl,imx23-power" }, ++ { .compatible = "fsl,imx28-power" }, ++ { /* end */ } ++}; ++MODULE_DEVICE_TABLE(of, of_mxs_power_match); ++ ++static const struct power_supply_desc ac_desc = { ++ .properties = mxs_power_ac_props, ++ .num_properties = ARRAY_SIZE(mxs_power_ac_props), ++ .get_property = mxs_power_ac_get_property, ++ .name = "ac", ++ .type = POWER_SUPPLY_TYPE_MAINS, ++}; ++ ++static int mxs_power_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct resource *res; ++ struct mxs_power_data *data; ++ struct power_supply_config psy_cfg = {}; ++ void __iomem *v5ctrl_addr; ++ ++ if (!np) { ++ dev_err(dev, "missing device tree\n"); ++ return -EINVAL; ++ } ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ data->base_addr = devm_ioremap_resource(dev, res); ++ if (IS_ERR(data->base_addr)) ++ return PTR_ERR(data->base_addr); ++ ++ psy_cfg.drv_data = data; ++ ++ data->ac = devm_power_supply_register(dev, &ac_desc, &psy_cfg); ++ if (IS_ERR(data->ac)) ++ return PTR_ERR(data->ac); ++ ++ platform_set_drvdata(pdev, data); ++ ++ v5ctrl_addr = data->base_addr + HW_POWER_5VCTRL_OFFSET; ++ ++ /* Make sure the current limit of the linregs are disabled. */ ++ writel(BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT, ++ v5ctrl_addr + STMP_OFFSET_REG_CLR); ++ ++ return of_platform_populate(np, NULL, NULL, dev); ++} ++ ++static struct platform_driver mxs_power_driver = { ++ .driver = { ++ .name = "mxs_power", ++ .of_match_table = of_mxs_power_match, ++ }, ++ .probe = mxs_power_probe, ++}; ++ ++module_platform_driver(mxs_power_driver); ++ ++MODULE_AUTHOR("Stefan Wahren "); ++MODULE_DESCRIPTION("Freescale MXS power subsystem"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/mxs/patches-4.1/102-mxs-add-regulator-driver.patch b/target/linux/mxs/patches-4.1/102-mxs-add-regulator-driver.patch new file mode 100644 index 0000000..4690b3c --- /dev/null +++ b/target/linux/mxs/patches-4.1/102-mxs-add-regulator-driver.patch @@ -0,0 +1,570 @@ +--- a/drivers/regulator/Kconfig ++++ b/drivers/regulator/Kconfig +@@ -450,6 +450,14 @@ config REGULATOR_MT6397 + This driver supports the control of different power rails of device + through regulator interface. + ++config REGULATOR_MXS ++ tristate "Freescale MXS on-chip regulators" ++ depends on (MXS_POWER || COMPILE_TEST) ++ help ++ Say y here to support Freescale MXS on-chip regulators. ++ It is recommended that this option be enabled on i.MX23, ++ i.MX28 platform. ++ + config REGULATOR_PALMAS + tristate "TI Palmas PMIC Regulators" + depends on MFD_PALMAS +--- a/drivers/regulator/Makefile ++++ b/drivers/regulator/Makefile +@@ -60,6 +60,7 @@ obj-$(CONFIG_REGULATOR_MC13783) += mc137 + obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o + obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o + obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o ++obj-$(CONFIG_REGULATOR_MXS) += mxs-regulator.o + obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o + obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o + obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o +--- /dev/null ++++ b/drivers/regulator/mxs-regulator.c +@@ -0,0 +1,540 @@ ++/* ++ * Freescale MXS on-chip regulators ++ * ++ * Embedded Alley Solutions, Inc ++ * ++ * Copyright (C) 2014 Stefan Wahren ++ * Copyright (C) 2010 Freescale Semiconductor, Inc. ++ * Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved. ++ * ++ * Inspired by imx-bootlets ++ */ ++ ++/* ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Powered by linear regulator. DCDC output is gated off and ++ the linreg output is equal to the target. */ ++#define HW_POWER_LINREG_DCDC_OFF 1 ++ ++/* Powered by linear regulator. DCDC output is not gated off ++ and is ready for the automatic hardware transistion after a 5V ++ event. The converters are not enabled when 5V is present. LinReg output ++ is 25mV below target. */ ++#define HW_POWER_LINREG_DCDC_READY 2 ++ ++/* Powered by DCDC converter and the LinReg is on. LinReg output ++ is 25mV below target. */ ++#define HW_POWER_DCDC_LINREG_ON 3 ++ ++/* Powered by DCDC converter and the LinReg is off. LinReg output ++ is 25mV below target. */ ++#define HW_POWER_DCDC_LINREG_OFF 4 ++ ++/* Powered by DCDC converter and the LinReg is ready for the ++ automatic hardware transfer. The LinReg output is not enabled and ++ depends on the 5V presence to enable the LinRegs. LinReg offset is 25mV ++ below target. */ ++#define HW_POWER_DCDC_LINREG_READY 5 ++ ++/* Powered by an external source when 5V is present. This does not ++ necessarily mean the external source is powered by 5V,but the chip needs ++ to be aware that 5V is present. */ ++#define HW_POWER_EXTERNAL_SOURCE_5V 6 ++ ++/* Powered by an external source when 5V is not present.This doesn't ++ necessarily mean the external source is powered by the battery, but the ++ chip needs to be aware that the battery is present */ ++#define HW_POWER_EXTERNAL_SOURCE_BATTERY 7 ++ ++/* Unknown configuration. This is an error. */ ++#define HW_POWER_UNKNOWN_SOURCE 8 ++ ++/* TODO: Move power register offsets into header file */ ++#define HW_POWER_5VCTRL 0x00000010 ++#define HW_POWER_VDDDCTRL 0x00000040 ++#define HW_POWER_VDDACTRL 0x00000050 ++#define HW_POWER_VDDIOCTRL 0x00000060 ++#define HW_POWER_MISC 0x00000090 ++#define HW_POWER_STS 0x000000c0 ++ ++#define BM_POWER_STS_VBUSVALID0_STATUS BIT(15) ++#define BM_POWER_STS_DC_OK BIT(9) ++ ++#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO BIT(2) ++#define BM_POWER_5VCTRL_ENABLE_DCDC BIT(0) ++ ++#define BM_POWER_LINREG_OFFSET_DCDC_MODE BIT(1) ++ ++#define SHIFT_FREQSEL 4 ++ ++#define BM_POWER_MISC_FREQSEL (7 << SHIFT_FREQSEL) ++ ++/* Recommended DC-DC clock source values */ ++#define HW_POWER_MISC_FREQSEL_20000_KHZ 1 ++#define HW_POWER_MISC_FREQSEL_24000_KHZ 2 ++#define HW_POWER_MISC_FREQSEL_19200_KHZ 3 ++ ++#define HW_POWER_MISC_SEL_PLLCLK BIT(0) ++ ++/* Regulator IDs */ ++#define MXS_DCDC 1 ++#define MXS_VDDIO 2 ++#define MXS_VDDA 3 ++#define MXS_VDDD 4 ++ ++struct mxs_reg_info { ++ /* regulator descriptor */ ++ struct regulator_desc desc; ++ ++ /* regulator control register */ ++ int ctrl_reg; ++ ++ /* disable DC-DC output */ ++ unsigned int disable_fet_mask; ++ ++ /* steps between linreg output and DC-DC target */ ++ unsigned int linreg_offset_mask; ++ u8 linreg_offset_shift; ++ ++ /* function which determine power source */ ++ u8 (*get_power_source)(struct regulator_dev *); ++}; ++ ++static inline u8 get_linreg_offset(struct mxs_reg_info *ldo, u32 regs) ++{ ++ return (regs & ldo->linreg_offset_mask) >> ldo->linreg_offset_shift; ++} ++ ++static u8 get_vddio_power_source(struct regulator_dev *reg) ++{ ++ struct mxs_reg_info *ldo = rdev_get_drvdata(reg); ++ u32 v5ctrl, status, base; ++ u8 offset; ++ ++ if (regmap_read(reg->regmap, HW_POWER_5VCTRL, &v5ctrl)) ++ return HW_POWER_UNKNOWN_SOURCE; ++ ++ if (regmap_read(reg->regmap, HW_POWER_STS, &status)) ++ return HW_POWER_UNKNOWN_SOURCE; ++ ++ if (regmap_read(reg->regmap, ldo->ctrl_reg, &base)) ++ return HW_POWER_UNKNOWN_SOURCE; ++ ++ offset = get_linreg_offset(ldo, base); ++ ++ /* If VBUS valid then 5 V power supply present */ ++ if (status & BM_POWER_STS_VBUSVALID0_STATUS) { ++ /* Powered by Linreg, DC-DC is off */ ++ if ((base & ldo->disable_fet_mask) && ++ !(offset & BM_POWER_LINREG_OFFSET_DCDC_MODE)) { ++ return HW_POWER_LINREG_DCDC_OFF; ++ } ++ ++ if (v5ctrl & BM_POWER_5VCTRL_ENABLE_DCDC) { ++ /* Powered by DC-DC, Linreg is on */ ++ if (offset & BM_POWER_LINREG_OFFSET_DCDC_MODE) ++ return HW_POWER_DCDC_LINREG_ON; ++ } else { ++ /* Powered by Linreg, DC-DC is off */ ++ if (!(offset & BM_POWER_LINREG_OFFSET_DCDC_MODE)) ++ return HW_POWER_LINREG_DCDC_OFF; ++ } ++ } else { ++ /* Powered by DC-DC, Linreg is on */ ++ if (offset & BM_POWER_LINREG_OFFSET_DCDC_MODE) ++ return HW_POWER_DCDC_LINREG_ON; ++ } ++ ++ return HW_POWER_UNKNOWN_SOURCE; ++} ++ ++static u8 get_vdda_vddd_power_source(struct regulator_dev *reg) ++{ ++ struct mxs_reg_info *ldo = rdev_get_drvdata(reg); ++ struct regulator_desc *desc = &ldo->desc; ++ u32 v5ctrl, status, base; ++ u8 offset; ++ ++ if (regmap_read(reg->regmap, HW_POWER_5VCTRL, &v5ctrl)) ++ return HW_POWER_UNKNOWN_SOURCE; ++ ++ if (regmap_read(reg->regmap, HW_POWER_STS, &status)) ++ return HW_POWER_UNKNOWN_SOURCE; ++ ++ if (regmap_read(reg->regmap, ldo->ctrl_reg, &base)) ++ return HW_POWER_UNKNOWN_SOURCE; ++ ++ offset = get_linreg_offset(ldo, base); ++ ++ /* DC-DC output is disabled */ ++ if (base & ldo->disable_fet_mask) { ++ /* Powered by 5 V supply */ ++ if (status & BM_POWER_STS_VBUSVALID0_STATUS) ++ return HW_POWER_EXTERNAL_SOURCE_5V; ++ ++ /* Powered by Linreg, DC-DC is off */ ++ if (!(offset & BM_POWER_LINREG_OFFSET_DCDC_MODE)) ++ return HW_POWER_LINREG_DCDC_OFF; ++ } ++ ++ /* If VBUS valid then 5 V power supply present */ ++ if (status & BM_POWER_STS_VBUSVALID0_STATUS) { ++ /* Powered by DC-DC, Linreg is on */ ++ if (v5ctrl & BM_POWER_5VCTRL_ENABLE_DCDC) ++ return HW_POWER_DCDC_LINREG_ON; ++ ++ /* Powered by Linreg, DC-DC is off */ ++ return HW_POWER_LINREG_DCDC_OFF; ++ } ++ ++ /* DC-DC is on */ ++ if (offset & BM_POWER_LINREG_OFFSET_DCDC_MODE) { ++ /* Powered by DC-DC, Linreg is on */ ++ if (base & desc->enable_mask) ++ return HW_POWER_DCDC_LINREG_ON; ++ ++ /* Powered by DC-DC, Linreg is off */ ++ return HW_POWER_DCDC_LINREG_OFF; ++ } ++ ++ return HW_POWER_UNKNOWN_SOURCE; ++} ++ ++static int mxs_set_dcdc_freq(struct regulator_dev *reg, u32 hz) ++{ ++ struct mxs_reg_info *dcdc = rdev_get_drvdata(reg); ++ u32 val; ++ int ret; ++ ++ if (dcdc->desc.id != MXS_DCDC) { ++ dev_warn(®->dev, "Setting switching freq is not supported\n"); ++ return -EINVAL; ++ } ++ ++ ret = regmap_read(reg->regmap, HW_POWER_MISC, &val); ++ if (ret) ++ return ret; ++ ++ val &= ~BM_POWER_MISC_FREQSEL; ++ val &= ~HW_POWER_MISC_SEL_PLLCLK; ++ ++ /* ++ * Select the PLL/PFD based frequency that the DC-DC converter uses. ++ * The actual switching frequency driving the power inductor is ++ * DCDC_CLK/16. Accept only values recommend by Freescale. ++ */ ++ switch (hz) { ++ case 1200000: ++ val |= HW_POWER_MISC_FREQSEL_19200_KHZ << SHIFT_FREQSEL; ++ break; ++ case 1250000: ++ val |= HW_POWER_MISC_FREQSEL_20000_KHZ << SHIFT_FREQSEL; ++ break; ++ case 1500000: ++ val |= HW_POWER_MISC_FREQSEL_24000_KHZ << SHIFT_FREQSEL; ++ break; ++ default: ++ dev_warn(®->dev, "Switching freq: %u Hz not supported\n", ++ hz); ++ return -EINVAL; ++ } ++ ++ /* First program FREQSEL */ ++ ret = regmap_write(reg->regmap, HW_POWER_MISC, val); ++ if (ret) ++ return ret; ++ ++ /* then set PLL as clock for DC-DC converter */ ++ val |= HW_POWER_MISC_SEL_PLLCLK; ++ ++ return regmap_write(reg->regmap, HW_POWER_MISC, val); ++} ++ ++static int mxs_ldo_set_voltage_sel(struct regulator_dev *reg, unsigned sel) ++{ ++ struct mxs_reg_info *ldo = rdev_get_drvdata(reg); ++ struct regulator_desc *desc = &ldo->desc; ++ u32 status = 0; ++ int timeout; ++ int ret; ++ ++ ret = regmap_update_bits(reg->regmap, desc->vsel_reg, desc->vsel_mask, ++ sel); ++ if (ret) ++ return ret; ++ ++ if (ldo->get_power_source) { ++ switch (ldo->get_power_source(reg)) { ++ case HW_POWER_LINREG_DCDC_OFF: ++ case HW_POWER_LINREG_DCDC_READY: ++ case HW_POWER_EXTERNAL_SOURCE_5V: ++ /* ++ * Since the DC-DC converter is off we can't ++ * trigger on DC_OK. So wait at least 1 ms ++ * for stabilization. ++ */ ++ usleep_range(1000, 2000); ++ return 0; ++ } ++ } ++ ++ /* Make sure DC_OK has changed */ ++ usleep_range(15, 20); ++ ++ for (timeout = 0; timeout < 20; timeout++) { ++ ret = regmap_read(reg->regmap, HW_POWER_STS, &status); ++ ++ if (ret) ++ break; ++ ++ /* DC-DC converter control loop has stabilized */ ++ if (status & BM_POWER_STS_DC_OK) ++ return 0; ++ ++ udelay(1); ++ } ++ ++ if (!ret) ++ dev_warn_ratelimited(®->dev, "%s: timeout status=0x%08x\n", ++ __func__, status); ++ ++ msleep(20); ++ ++ return -ETIMEDOUT; ++} ++ ++static int mxs_ldo_is_enabled(struct regulator_dev *reg) ++{ ++ struct mxs_reg_info *ldo = rdev_get_drvdata(reg); ++ ++ if (ldo->get_power_source) { ++ switch (ldo->get_power_source(reg)) { ++ case HW_POWER_LINREG_DCDC_OFF: ++ case HW_POWER_LINREG_DCDC_READY: ++ case HW_POWER_DCDC_LINREG_ON: ++ return 1; ++ } ++ } ++ ++ return 0; ++} ++ ++static struct regulator_ops mxs_dcdc_ops = { ++ .is_enabled = regulator_is_enabled_regmap, ++}; ++ ++static struct regulator_ops mxs_ldo_ops = { ++ .list_voltage = regulator_list_voltage_linear, ++ .map_voltage = regulator_map_voltage_linear, ++ .set_voltage_sel = mxs_ldo_set_voltage_sel, ++ .get_voltage_sel = regulator_get_voltage_sel_regmap, ++ .is_enabled = mxs_ldo_is_enabled, ++}; ++ ++static const struct mxs_reg_info mxs_info_dcdc = { ++ .desc = { ++ .name = "dcdc", ++ .id = MXS_DCDC, ++ .type = REGULATOR_VOLTAGE, ++ .owner = THIS_MODULE, ++ .ops = &mxs_dcdc_ops, ++ .enable_reg = HW_POWER_STS, ++ .enable_mask = (1 << 0), ++ }, ++}; ++ ++static const struct mxs_reg_info imx23_info_vddio = { ++ .desc = { ++ .name = "vddio", ++ .id = MXS_VDDIO, ++ .type = REGULATOR_VOLTAGE, ++ .owner = THIS_MODULE, ++ .n_voltages = 0x20, ++ .uV_step = 25000, ++ .linear_min_sel = 0, ++ .min_uV = 2800000, ++ .vsel_reg = HW_POWER_VDDIOCTRL, ++ .vsel_mask = 0x1f, ++ .ops = &mxs_ldo_ops, ++ }, ++ .ctrl_reg = HW_POWER_VDDIOCTRL, ++ .disable_fet_mask = 1 << 16, ++ .linreg_offset_mask = 3 << 12, ++ .linreg_offset_shift = 12, ++ .get_power_source = get_vddio_power_source, ++}; ++ ++static const struct mxs_reg_info imx28_info_vddio = { ++ .desc = { ++ .name = "vddio", ++ .id = MXS_VDDIO, ++ .type = REGULATOR_VOLTAGE, ++ .owner = THIS_MODULE, ++ .n_voltages = 0x11, ++ .uV_step = 50000, ++ .linear_min_sel = 0, ++ .min_uV = 2800000, ++ .vsel_reg = HW_POWER_VDDIOCTRL, ++ .vsel_mask = 0x1f, ++ .ops = &mxs_ldo_ops, ++ }, ++ .ctrl_reg = HW_POWER_VDDIOCTRL, ++ .disable_fet_mask = 1 << 16, ++ .linreg_offset_mask = 3 << 12, ++ .linreg_offset_shift = 12, ++ .get_power_source = get_vddio_power_source, ++}; ++ ++static const struct mxs_reg_info mxs_info_vdda = { ++ .desc = { ++ .name = "vdda", ++ .id = MXS_VDDA, ++ .type = REGULATOR_VOLTAGE, ++ .owner = THIS_MODULE, ++ .n_voltages = 0x20, ++ .uV_step = 25000, ++ .linear_min_sel = 0, ++ .min_uV = 1500000, ++ .vsel_reg = HW_POWER_VDDACTRL, ++ .vsel_mask = 0x1f, ++ .ops = &mxs_ldo_ops, ++ .enable_mask = (1 << 17), ++ }, ++ .ctrl_reg = HW_POWER_VDDACTRL, ++ .disable_fet_mask = 1 << 16, ++ .linreg_offset_mask = 3 << 12, ++ .linreg_offset_shift = 12, ++ .get_power_source = get_vdda_vddd_power_source, ++}; ++ ++static const struct mxs_reg_info mxs_info_vddd = { ++ .desc = { ++ .name = "vddd", ++ .id = MXS_VDDD, ++ .type = REGULATOR_VOLTAGE, ++ .owner = THIS_MODULE, ++ .n_voltages = 0x20, ++ .uV_step = 25000, ++ .linear_min_sel = 0, ++ .min_uV = 800000, ++ .vsel_reg = HW_POWER_VDDDCTRL, ++ .vsel_mask = 0x1f, ++ .ops = &mxs_ldo_ops, ++ .enable_mask = (1 << 21), ++ }, ++ .ctrl_reg = HW_POWER_VDDDCTRL, ++ .disable_fet_mask = 1 << 20, ++ .linreg_offset_mask = 3 << 16, ++ .linreg_offset_shift = 16, ++ .get_power_source = get_vdda_vddd_power_source, ++}; ++ ++static const struct of_device_id of_mxs_regulator_match[] = { ++ { .compatible = "fsl,imx23-dcdc", .data = &mxs_info_dcdc }, ++ { .compatible = "fsl,imx28-dcdc", .data = &mxs_info_dcdc }, ++ { .compatible = "fsl,imx23-vddio", .data = &imx23_info_vddio }, ++ { .compatible = "fsl,imx23-vdda", .data = &mxs_info_vdda }, ++ { .compatible = "fsl,imx23-vddd", .data = &mxs_info_vddd }, ++ { .compatible = "fsl,imx28-vddio", .data = &imx28_info_vddio }, ++ { .compatible = "fsl,imx28-vdda", .data = &mxs_info_vdda }, ++ { .compatible = "fsl,imx28-vddd", .data = &mxs_info_vddd }, ++ { /* end */ } ++}; ++MODULE_DEVICE_TABLE(of, of_mxs_regulator_match); ++ ++static int mxs_regulator_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ const struct of_device_id *match; ++ struct device_node *parent_np; ++ struct regulator_dev *rdev = NULL; ++ struct mxs_reg_info *info; ++ struct regulator_init_data *initdata; ++ struct regulator_config config = { }; ++ u32 switch_freq; ++ ++ match = of_match_device(of_mxs_regulator_match, dev); ++ if (!match) { ++ /* We do not expect this to happen */ ++ dev_err(dev, "%s: Unable to match device\n", __func__); ++ return -ENODEV; ++ } ++ ++ info = devm_kmemdup(dev, match->data, sizeof(struct mxs_reg_info), ++ GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ initdata = of_get_regulator_init_data(dev, dev->of_node, &info->desc); ++ if (!initdata) { ++ dev_err(dev, "missing regulator init data\n"); ++ return -EINVAL; ++ } ++ ++ parent_np = of_get_parent(dev->of_node); ++ if (!parent_np) ++ return -ENODEV; ++ config.regmap = syscon_node_to_regmap(parent_np); ++ of_node_put(parent_np); ++ if (IS_ERR(config.regmap)) ++ return PTR_ERR(config.regmap); ++ ++ config.dev = dev; ++ config.init_data = initdata; ++ config.driver_data = info; ++ config.of_node = dev->of_node; ++ ++ rdev = devm_regulator_register(dev, &info->desc, &config); ++ if (IS_ERR(rdev)) { ++ int ret = PTR_ERR(rdev); ++ ++ dev_err(dev, "%s: failed to register regulator(%d)\n", ++ __func__, ret); ++ return ret; ++ } ++ ++ if (!of_property_read_u32(dev->of_node, "switching-frequency", ++ &switch_freq)) ++ mxs_set_dcdc_freq(rdev, switch_freq); ++ ++ platform_set_drvdata(pdev, rdev); ++ ++ return 0; ++} ++ ++static struct platform_driver mxs_regulator_driver = { ++ .driver = { ++ .name = "mxs_regulator", ++ .of_match_table = of_mxs_regulator_match, ++ }, ++ .probe = mxs_regulator_probe, ++}; ++ ++module_platform_driver(mxs_regulator_driver); ++ ++MODULE_AUTHOR("Stefan Wahren "); ++MODULE_DESCRIPTION("Freescale MXS regulators"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:mxs_regulator"); diff --git a/target/linux/mxs/patches-4.1/103-dt-enable-regulator.patch b/target/linux/mxs/patches-4.1/103-dt-enable-regulator.patch new file mode 100644 index 0000000..bfcf247 --- /dev/null +++ b/target/linux/mxs/patches-4.1/103-dt-enable-regulator.patch @@ -0,0 +1,100 @@ +--- a/arch/arm/boot/dts/imx23.dtsi ++++ b/arch/arm/boot/dts/imx23.dtsi +@@ -404,8 +404,46 @@ + }; + + power@80044000 { ++ compatible = "fsl,imx23-power", "syscon"; + reg = <0x80044000 0x2000>; +- status = "disabled"; ++ interrupts = <3>; ++ ++ dcdc: regulator@1 { ++ compatible = "fsl,imx23-dcdc"; ++ regulator-name = "dcdc"; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vddd: regulator@2 { ++ compatible = "fsl,imx23-vddd"; ++ regulator-name = "vddd"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1550000>; ++ vddd-supply = <®_vdda>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vdda: regulator@3 { ++ compatible = "fsl,imx23-vdda"; ++ regulator-name = "vdda"; ++ regulator-min-microvolt = <1725000>; ++ regulator-max-microvolt = <1950000>; ++ vdda-supply = <®_vddio>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vddio: regulator@4 { ++ compatible = "fsl,imx23-vddio"; ++ regulator-name = "vddio"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3575000>; ++ regulator-microvolt-offset = <80000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; + }; + + saif1: saif@80046000 { +--- a/arch/arm/boot/dts/imx28.dtsi ++++ b/arch/arm/boot/dts/imx28.dtsi +@@ -1035,8 +1035,46 @@ + }; + + power: power@80044000 { ++ compatible = "fsl,imx28-power", "syscon"; + reg = <0x80044000 0x2000>; +- status = "disabled"; ++ interrupts = <6>; ++ ++ dcdc: regulator@1 { ++ compatible = "fsl,imx28-dcdc"; ++ regulator-name = "dcdc"; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vddd: regulator@2 { ++ compatible = "fsl,imx28-vddd"; ++ regulator-name = "vddd"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1550000>; ++ vddd-supply = <®_vdda>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vdda: regulator@3 { ++ compatible = "fsl,imx28-vdda"; ++ regulator-name = "vdda"; ++ regulator-min-microvolt = <1725000>; ++ regulator-max-microvolt = <1950000>; ++ vdda-supply = <®_vddio>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vddio: regulator@4 { ++ compatible = "fsl,imx28-vddio"; ++ regulator-name = "vddio"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3550000>; ++ regulator-microvolt-offset = <80000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; + }; + + saif1: saif@80046000 { diff --git a/target/linux/mxs/patches-4.1/120-dt-add-i2c.patch b/target/linux/mxs/patches-4.1/120-dt-add-i2c.patch new file mode 100644 index 0000000..79c162a --- /dev/null +++ b/target/linux/mxs/patches-4.1/120-dt-add-i2c.patch @@ -0,0 +1,55 @@ +--- a/arch/arm/boot/dts/imx23.dtsi ++++ b/arch/arm/boot/dts/imx23.dtsi +@@ -147,6 +147,39 @@ + fsl,pull-up = ; + }; + ++ i2c0_pins_a: i2c0@0 { ++ reg = <0>; ++ fsl,pinmux-ids = < ++ 0x01e0 /* MX23_PAD_I2C_SCL__I2C_SCL */ ++ 0x01f0 /* MX23_PAD_I2C_SDA__I2C_SDA */ ++ >; ++ fsl,drive-strength = <1>; ++ fsl,voltage = <1>; ++ fsl,pull-up = <1>; ++ }; ++ ++ i2c1_pins_a: i2c1@0 { ++ reg = <0>; ++ fsl,pinmux-ids = < ++ 0x1171 /* MX23_PAD_LCD_ENABLE__I2C_SCL */ ++ 0x1181 /* MX23_PAD_LCD_HSYNC__I2C_SDA */ ++ >; ++ fsl,drive-strength = <1>; ++ fsl,voltage = <1>; ++ fsl,pull-up = <1>; ++ }; ++ ++ i2c2_pins_a: i2c2@0 { ++ reg = <0>; ++ fsl,pinmux-ids = < ++ 0x2031 /* MX23_PAD_SSP1_DATA1__I2C_SCL */ ++ 0x2041 /* MX23_PAD_SSP1_DATA2__I2C_SDA */ ++ >; ++ fsl,drive-strength = <1>; ++ fsl,voltage = <1>; ++ fsl,pull-up = <1>; ++ }; ++ + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < +@@ -484,7 +517,12 @@ + }; + + i2c@80058000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "fsl,imx23-i2c"; + reg = <0x80058000 0x2000>; ++ interrupts = <27>; ++ clock-frequency = <100000>; + dmas = <&dma_apbx 3>; + dma-names = "rx-tx"; + status = "disabled"; diff --git a/target/linux/mxs/profiles/01-duckbill.mk b/target/linux/mxs/profiles/01-duckbill.mk new file mode 100644 index 0000000..85a1237 --- /dev/null +++ b/target/linux/mxs/profiles/01-duckbill.mk @@ -0,0 +1,22 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/duckbill + NAME:=I2SE Duckbill boards + DEPENDS:=+@TARGET_ROOTFS_INCLUDE_KERNEL +@TARGET_ROOTFS_INCLUDE_DTB + FEATURES+=usbgadget + PACKAGES+= \ + -dnsmasq -firewall -ppp -ip6tables -iptables -6relayd -mtd uboot-envtools \ + kmod-leds-gpio kmod-ledtrig-timer kmod-usb-mxs-phy -kmod-ipt-nathelper \ + kmod-i2c-mxs kmod-spi-mxs uboot-mxs-duckbill +endef + +define Profile/duckbill/Description + I2SE's Duckbill devices +endef + +$(eval $(call Profile,duckbill)) diff --git a/target/linux/mxs/profiles/02-olinuxino-maxi.mk b/target/linux/mxs/profiles/02-olinuxino-maxi.mk new file mode 100644 index 0000000..7885d1f --- /dev/null +++ b/target/linux/mxs/profiles/02-olinuxino-maxi.mk @@ -0,0 +1,21 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/olinuxino-maxi + NAME:=Olimex OLinuXino Maxi/Mini boards + PACKAGES += imx-bootlets uboot-mxs-mx23_olinuxino \ + kmod-usb-mxs-phy kmod-usb-net kmod-usb-net-smsc95xx \ + kmod-gpio-mcp23s08 kmod-leds-gpio kmod-ledtrig-heartbeat kmod-rtc-stmp3xxx \ + kmod-sound-core kmod-sound-soc-mxs kmod-iio-mxs-lradc kmod-crypto-hw-dcp \ + kmod-i2c-mxs kmod-spi-mxs +endef + +define Profile/olinuxino-maxi/Description + Olimex OLinuXino Maxi/Mini boards +endef + +$(eval $(call Profile,olinuxino-maxi)) diff --git a/target/linux/mxs/profiles/03-olinuxino-micro.mk b/target/linux/mxs/profiles/03-olinuxino-micro.mk new file mode 100644 index 0000000..356a877 --- /dev/null +++ b/target/linux/mxs/profiles/03-olinuxino-micro.mk @@ -0,0 +1,21 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/olinuxino-micro + NAME:=Olimex OLinuXino Micro/Nano boards + PACKAGES += imx-bootlets uboot-mxs-mx23_olinuxino \ + kmod-usb-mxs-phy kmod-gpio-mcp23s08 kmod-leds-gpio \ + kmod-ledtrig-heartbeat kmod-rtc-stmp3xxx \ + kmod-iio-mxs-lradc kmod-crypto-hw-dcp \ + kmod-i2c-mxs kmod-spi-mxs +endef + +define Profile/olinuxino-micro/Description + Olimex OLinuXino Micro/Nano boards +endef + +$(eval $(call Profile,olinuxino-micro)) diff --git a/target/linux/netlogic/Makefile b/target/linux/netlogic/Makefile new file mode 100644 index 0000000..5e15fff --- /dev/null +++ b/target/linux/netlogic/Makefile @@ -0,0 +1,20 @@ +# +# Copyright (C) 2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips64 +BOARD:=netlogic +BOARDNAME:=Broadcom/Netlogic XLP/XLR +FEATURES:=squashfs jffs2 ext4 pci usb +MAINTAINER:=Florian Fainelli +SUBTARGETS:=xlp xlr + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + +$(eval $(call BuildTarget)) diff --git a/target/linux/netlogic/base-files.mk b/target/linux/netlogic/base-files.mk new file mode 100644 index 0000000..d6682bd --- /dev/null +++ b/target/linux/netlogic/base-files.mk @@ -0,0 +1,5 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef + + diff --git a/target/linux/netlogic/base-files/etc/uci-defaults/02_network b/target/linux/netlogic/base-files/etc/uci-defaults/02_network new file mode 100644 index 0000000..e271e17 --- /dev/null +++ b/target/linux/netlogic/base-files/etc/uci-defaults/02_network @@ -0,0 +1,28 @@ +#!/bin/sh +# +# Copyright (C) 2014 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +touch /etc/config/network + +. /lib/functions/uci-defaults.sh +. /lib/netlogic.sh + +ucidef_set_interface_loopback + +case "$board_name" in +"xlp-evp" |\ +"xlp-fvp" |\ +"xlp-gvp" |\ +"xlp-svp" |\ +*) + ucidef_set_interface_lan "eth0" + ;; + +esac + +uci commit network + +exit 0 diff --git a/target/linux/netlogic/base-files/lib/netlogic.sh b/target/linux/netlogic/base-files/lib/netlogic.sh new file mode 100755 index 0000000..27b7c40 --- /dev/null +++ b/target/linux/netlogic/base-files/lib/netlogic.sh @@ -0,0 +1,48 @@ +#!/bin/sh +# +# Copyright (C) 2014 OpenWrt.org +# + +NETLOGIC_BOARD_NAME= +NETLOGIC_MODEL= + +netlogic_board_detect() { + local machine + local name + + machine=$(awk 'BEGIN{FS="[ \t:/]+"} /machine/ {print $2}' /proc/cpuinfo) + + case "$machine" in + *"netlogic,XLP-EVP") + name="xlp-evp" + ;; + *"netlogic,XLP-FVP") + name="xlp-fvp" + ;; + *"netlogic,XLP-GVP") + name="xlp-gvp" + ;; + *"netlogic,XLP-SVP") + name="xlp-svp" + ;; + esac + + [ -z "$name" ] && name="unknown" + + [ -z "$NETLOGIC_BOARD_NAME" ] && NETLOGIC_BOARD_NAME="$name" + [ -z "$NETLOGIC_MODEL" ] && NETLOGIC_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$NETLOGIC_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$NETLOGIC_MODEL" > /tmp/sysinfo/model +} + +netlogic_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/netlogic/base-files/lib/preinit/03_do_netlogic.sh b/target/linux/netlogic/base-files/lib/preinit/03_do_netlogic.sh new file mode 100755 index 0000000..712a231 --- /dev/null +++ b/target/linux/netlogic/base-files/lib/preinit/03_do_netlogic.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +do_netlogic() { + . /lib/netlogic.sh + + netlogic_board_detect +} + +boot_hook_add preinit_main do_netlogic diff --git a/target/linux/netlogic/config-default b/target/linux/netlogic/config-default new file mode 100644 index 0000000..ded67ef --- /dev/null +++ b/target/linux/netlogic/config-default @@ -0,0 +1,207 @@ +# CONFIG_32BIT is not set +CONFIG_64BIT=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_BINFMT_ELF32=y +CONFIG_BINFMT_MISC=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLOCK_COMPAT=y +CONFIG_BOOT_ELF32=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_R4K_CACHE_TLB=y +CONFIG_CPU_R4K_FPU=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CSRC_R4K=y +# CONFIG_CYCLADES is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_DMA_COHERENT=y +CONFIG_DTC=y +CONFIG_E1000E=y +CONFIG_EARLY_PRINTK=y +CONFIG_FS_POSIX_ACL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HW_HAS_PCI=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_OCORES=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +# CONFIG_ISI is not set +CONFIG_MIPS=y +CONFIG_MIPS32_COMPAT=y +CONFIG_MIPS32_N32=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=5 +# CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_MT_DISABLED=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULES_USE_ELF_RELA=y +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLM_COMMON=y +# CONFIG_NLM_MULTINODE is not set +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=32 +CONFIG_NR_CPUS_DEFAULT_32=y +# CONFIG_N_HDLC is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_IRQ=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PCI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PM=y +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_PM_DEBUG=y +CONFIG_PM_RUNTIME=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_PPS=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PROC_KCORE=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +# CONFIG_ROCKETPORT is not set +CONFIG_RPS=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SMP=y +CONFIG_STOP_MACHINE=y +CONFIG_SWIOTLB=y +# CONFIG_SYNCLINKMP is not set +# CONFIG_SYNCLINK_GT is not set +CONFIG_SYNC_R4K=y +CONFIG_SYSV68_PARTITION=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_OF=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_STATS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TREE_RCU=y +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_WEAK_ORDERING=y +CONFIG_WEAK_REORDERING_BEYOND_LLSC=y +CONFIG_XPS=y +CONFIG_ZONE_DMA32=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/netlogic/image/Makefile b/target/linux/netlogic/image/Makefile new file mode 100644 index 0000000..9541f6a --- /dev/null +++ b/target/linux/netlogic/image/Makefile @@ -0,0 +1,26 @@ +# +# Copyright (C) 2009-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Image/BuildKernel +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) +endef + +define Image/Build/Initramfs + cp $(KDIR)/vmlinux-initramfs.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.elf +endef + +define Image/Build + $(call Image/Build/$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/netlogic/xlp/config-default b/target/linux/netlogic/xlp/config-default new file mode 100644 index 0000000..eee7fb4 --- /dev/null +++ b/target/linux/netlogic/xlp/config-default @@ -0,0 +1,7 @@ +CONFIG_CPU_XLP=y +CONFIG_DT_XLP_EVP=y +CONFIG_DT_XLP_FVP=y +CONFIG_DT_XLP_GVP=y +CONFIG_DT_XLP_SVP=y +CONFIG_NLM_XLP_BOARD=y +CONFIG_SYS_HAS_CPU_XLP=y diff --git a/target/linux/netlogic/xlp/target.mk b/target/linux/netlogic/xlp/target.mk new file mode 100644 index 0000000..44c4460 --- /dev/null +++ b/target/linux/netlogic/xlp/target.mk @@ -0,0 +1,10 @@ +CPU_TYPE:=xlp +CPU_FLAGS_xlp:=-march=xlp -mabi=64 +BOARDNAME:=xlp + +DEFAULT_PACKAGES += kmod-usb-core kmod-usb2 kmod-usb2-pci kmod-usb3 \ + kmod-usb-net kmod-usb-net-smsc95xx + +define Target/Description + Build firmware images for Broadcom/Netlogic XLP boards. +endef diff --git a/target/linux/netlogic/xlr/config-default b/target/linux/netlogic/xlr/config-default new file mode 100644 index 0000000..daa1c91 --- /dev/null +++ b/target/linux/netlogic/xlr/config-default @@ -0,0 +1,12 @@ +CONFIG_CPU_SUPPORTS_HUGEPAGES=y +CONFIG_CPU_XLR=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +# CONFIG_HUGETLBFS is not set +CONFIG_I2C_XLR=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_NETLOGIC_XLR_NET=y +CONFIG_NLM_XLR_BOARD=y +CONFIG_PHYLIB=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SYS_HAS_CPU_XLR=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y diff --git a/target/linux/netlogic/xlr/target.mk b/target/linux/netlogic/xlr/target.mk new file mode 100644 index 0000000..e786598 --- /dev/null +++ b/target/linux/netlogic/xlr/target.mk @@ -0,0 +1,7 @@ +CPU_TYPE:=xlr +CPU_FLAGS_xlr:=-march=xlr -mabi=64 +BOARDNAME:=xlr + +define Target/Description + Build firmware images for Broadcom/Netlogic XLR boards. +endef diff --git a/target/linux/octeon/Makefile b/target/linux/octeon/Makefile new file mode 100644 index 0000000..e1739e7 --- /dev/null +++ b/target/linux/octeon/Makefile @@ -0,0 +1,26 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=mips64 +BOARD:=octeon +BOARDNAME:=Cavium Networks Octeon +FEATURES:=squashfs jffs2 ext4 initramfs pci usb +CPU_TYPE:=octeon +CPU_CFLAGS_octeon:=-march=octeon -mabi=64 +MAINTAINER:=John Crispin + +KERNEL_PATCHVER:=3.18 + +include $(INCLUDE_DIR)/target.mk + + +define Target/Description + Build firmware images for Cavium Networks Octeon-based boards. +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/octeon/base-files.mk b/target/linux/octeon/base-files.mk new file mode 100644 index 0000000..fdd2c71 --- /dev/null +++ b/target/linux/octeon/base-files.mk @@ -0,0 +1,3 @@ +define Package/base-files/install-target + rm -f $(1)/etc/config/network +endef diff --git a/target/linux/octeon/base-files/etc/uci-defaults/01_network b/target/linux/octeon/base-files/etc/uci-defaults/01_network new file mode 100644 index 0000000..bda8d0c --- /dev/null +++ b/target/linux/octeon/base-files/etc/uci-defaults/01_network @@ -0,0 +1,31 @@ +#!/bin/sh +# +# Copyright (C) 2014 OpenWrt.org +# + +[ -e /etc/config/network ] && exit 0 + +. /lib/functions/uci-defaults.sh +. /lib/functions/octeon.sh + +touch /etc/config/network + +board=$(octeon_board_name) + +case "$board" in +erlite) + ucidef_set_interface_loopback + ucidef_set_interface_lan 'eth0' + ucidef_set_interface_wan 'eth1' + ;; + +*) + ucidef_set_interface_loopback + ucidef_set_interface_wan 'eth1' + ucidef_set_interface_lan 'eth0' + ;; +esac + +uci commit network + +exit 0 diff --git a/target/linux/octeon/base-files/lib/functions/octeon.sh b/target/linux/octeon/base-files/lib/functions/octeon.sh new file mode 100755 index 0000000..deae9e3 --- /dev/null +++ b/target/linux/octeon/base-files/lib/functions/octeon.sh @@ -0,0 +1,50 @@ +#!/bin/sh +# +# Copyright (C) 2010-2013 OpenWrt.org +# + +OCTEON_BOARD_NAME= +OCTEON_MODEL= + +octeon_board_detect() { + local machine + local name + + machine=$(grep "^system type" /proc/cpuinfo | sed "s/system type.*: \(.*\)/\1/g") + + case "$machine" in + "UBNT_E100"*) + name="erlite" + ;; + + "UBNT_E200"*) + name="er" + ;; + + "UBNT_E220"*) + name="erpro" + ;; + + *) + name="generic" + ;; + esac + + [ -z "$OCTEON_BOARD_NAME" ] && OCTEON_BOARD_NAME="$name" + [ -z "$OCTEON_MODEL" ] && OCTEON_MODEL="$machine" + + [ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/" + + echo "$OCTEON_BOARD_NAME" > /tmp/sysinfo/board_name + echo "$OCTEON_MODEL" > /tmp/sysinfo/model +} + +octeon_board_name() { + local name + + [ -f /tmp/sysinfo/board_name ] || octeon_board_detect + [ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name) + [ -z "$name" ] && name="unknown" + + echo "$name" +} diff --git a/target/linux/octeon/base-files/lib/preinit/79_move_config b/target/linux/octeon/base-files/lib/preinit/79_move_config new file mode 100644 index 0000000..39cefd5 --- /dev/null +++ b/target/linux/octeon/base-files/lib/preinit/79_move_config @@ -0,0 +1,18 @@ +#!/bin/sh +# Copyright (C) 2014 OpenWrt.org + +move_config() { + . /lib/functions/octeon.sh + + local board="$(octeon_board_name)" + + case "$board" in + erlite) + mount -t vfat /dev/sda1 /mnt + mv -f /mnt/sysupgrade.tgz / + umount /mnt + ;; + esac +} + +boot_hook_add preinit_mount_root move_config diff --git a/target/linux/octeon/base-files/lib/upgrade/platform.sh b/target/linux/octeon/base-files/lib/upgrade/platform.sh new file mode 100755 index 0000000..4cb03bc --- /dev/null +++ b/target/linux/octeon/base-files/lib/upgrade/platform.sh @@ -0,0 +1,104 @@ +# +# Copyright (C) 2014 OpenWrt.org +# + +. /lib/functions/octeon.sh + +platform_get_rootfs() { + local rootfsdev + + if read cmdline < /proc/cmdline; then + case "$cmdline" in + *block2mtd=*) + rootfsdev="${cmdline##*block2mtd=}" + rootfsdev="${rootfsdev%%,*}" + ;; + *root=*) + rootfsdev="${cmdline##*root=}" + rootfsdev="${rootfsdev%% *}" + ;; + esac + + echo "${rootfsdev}" + fi +} + +platform_copy_config() { + local board="$(octeon_board_name)" + + case "$board" in + erlite) + mount -t vfat /dev/sda1 /mnt + cp -af "$CONF_TAR" /mnt/ + umount /mnt + ;; + esac +} + +platform_do_flash() { + local tar_file=$1 + local board=$2 + local kernel=$3 + local rootfs=$4 + + mkdir -p /boot + mount -t vfat /dev/$kernel /boot + + [ -f /boot/vmlinux.64 -a ! -L /boot/vmlinux.64 ] && { + mv /boot/vmlinux.64 /boot/vmlinux.64.previous + mv /boot/vmlinux.64.md5 /boot/vmlinux.64.md5.previous + } + + echo "flashing kernel to /dev/$kernel" + tar xf $tar_file sysupgrade-$board/kernel -O > /boot/vmlinux.64 + md5sum /boot/vmlinux.64 | cut -f1 -d " " > /boot/vmlinux.64.md5 + echo "flashing rootfs to ${rootfs}" + tar xf $tar_file sysupgrade-$board/root -O | dd of="${rootfs}" bs=4096 + sync + umount /boot +} + +platform_do_upgrade() { + local tar_file="$1" + local board=$(octeon_board_name) + local rootfs="$(platform_get_rootfs)" + local kernel= + + [ -b "${rootfs}" ] || return 1 + case "$board" in + erlite) + kernel=sda1 + ;; + er) + kernel=mmcblk0p1 + ;; + *) + return 1 + esac + + platform_do_flash $tar_file $board $kernel $rootfs + + return 0 + +} + +platform_check_image() { + local board=$(octeon_board_name) + + case "$board" in + erlite | \ + er) + local tar_file="$1" + local kernel_length=`(tar xf $tar_file sysupgrade-$board/kernel -O | wc -c) 2> /dev/null` + local rootfs_length=`(tar xf $tar_file sysupgrade-$board/root -O | wc -c) 2> /dev/null` + [ "$kernel_length" = 0 -o "$rootfs_length" = 0 ] && { + echo "The upgarde image is corrupt." + return 1 + } + return 0 + ;; + esac + + echo "Sysupgrade is not yet supported on $board." + return 1 +} diff --git a/target/linux/octeon/config-3.18 b/target/linux/octeon/config-3.18 new file mode 100644 index 0000000..44a154a --- /dev/null +++ b/target/linux/octeon/config-3.18 @@ -0,0 +1,250 @@ +CONFIG_64BIT=y +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_DISCARD_MEMBLOCK=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_BINFMT_ELF32=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLOCK_COMPAT=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_BUILTIN_DTB=y +# CONFIG_CAVIUM_CN63XXP1 is not set +# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set +CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2 +CONFIG_CAVIUM_OCTEON_LOCK_L2=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y +CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y +CONFIG_CAVIUM_OCTEON_SOC=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CEVT_R4K=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT=y +CONFIG_COMPAT_BRK=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_CPU_BIG_ENDIAN=y +CONFIG_CPU_CAVIUM_OCTEON=y +CONFIG_CPU_GENERIC_DUMP_TLB=y +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_CPU_MIPSR2=y +CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_CPU_SUPPORTS_HUGEPAGES=y +CONFIG_CRAMFS=y +CONFIG_CRC16=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEVKMEM=y +CONFIG_DMA_COHERENT=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_EARLY_PRINTK=y +CONFIG_EDAC_SUPPORT=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_EXT4_FS=y +CONFIG_FAT_FS=y +CONFIG_FRAME_WARN=2048 +CONFIG_FS_MBCACHE=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_OCTEON=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDWARE_WATCHPOINTS=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DEBUG_STACKOVERFLOW=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_HOLES_IN_ZONE=y +# CONFIG_HUGETLBFS is not set +CONFIG_HW_HAS_PCI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_OCTEON=y +CONFIG_HZ=250 +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +CONFIG_HZ_PERIODIC=y +CONFIG_IMAGE_CMDLINE_HACK=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KALLSYMS=y +CONFIG_KEXEC=y +CONFIG_LIBFDT=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MDIO_OCTEON=y +CONFIG_MIPS=y +CONFIG_MIPS32_COMPAT=y +CONFIG_MIPS32_N32=y +CONFIG_MIPS32_O32=y +# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set +CONFIG_MIPS_L1_CACHE_SHIFT=7 +CONFIG_MIPS_L1_CACHE_SHIFT_7=y +# CONFIG_MIPS_MACHINE is not set +CONFIG_MIPS_PGD_C0_CONTEXT=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_OCTEON=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_BLOCK2MTD=y +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NLS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y +# CONFIG_NO_IOPORT_MAP is not set +CONFIG_NR_CPUS=16 +CONFIG_NR_CPUS_DEFAULT_16=y +CONFIG_OCTEON_ETHERNET=y +# CONFIG_OCTEON_ILM is not set +CONFIG_OCTEON_MGMT_ETHERNET=y +CONFIG_OCTEON_USB=y +CONFIG_OCTEON_WDT=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RELAY=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_SCHED_DEBUG=y +CONFIG_SCSI=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SMP=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_STOP_MACHINE=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_SWIOTLB=y +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y +CONFIG_SYS_HAS_DMA_OPS=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_SYS_SUPPORTS_SMP=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_OCTEON2_COMMON=y +CONFIG_USB_OCTEON_EHCI=y +CONFIG_USB_OCTEON_OHCI=y +CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USE_OF=y +CONFIG_VFAT_FS=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WEAK_ORDERING=y +CONFIG_XPS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/octeon/image/Makefile b/target/linux/octeon/image/Makefile new file mode 100644 index 0000000..e74b06d --- /dev/null +++ b/target/linux/octeon/image/Makefile @@ -0,0 +1,65 @@ +# +# Copyright (C) 2009-2010 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Image/Prepare + # Workaround pre-SDK-1.9.0 u-boot versions not handling the .notes section + $(TARGET_CROSS)strip -R .notes $(KDIR)/vmlinux.elf -o $(KDIR)/vmlinux.elf.stripped +endef + +define Image/BuildKernel/Template + $(CP) $(KDIR)/vmlinux.elf.stripped $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux.64 + $(STAGING_DIR_HOST)/bin/patch-cmdline $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux.64 '$(strip $(2))' + md5sum $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux.64 | cut -d " " -f 1 | tee $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux.64.md5 +endef + +define Image/BuildKernel/Initramfs/Template + $(TARGET_CROSS)strip -R .notes $(KDIR)/vmlinux-initramfs.elf -o $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux-initramfs.elf + $(STAGING_DIR_HOST)/bin/patch-cmdline $(BIN_DIR)/$(IMG_PREFIX)-$(1)-vmlinux-initramfs.elf '$(strip $(2))' +endef + +ER_CMDLINE:=-mtdparts=phys_mapped_flash:640k(boot0)ro,640k(boot1)ro,64k(eeprom)ro block2mtd.block2mtd=/dev/mmcblk0p2,65536,rootfs,5 root=/dev/mtdblock3 rootfstype=squashfs rootwait +ERLITE_CMDLINE:=-mtdparts=phys_mapped_flash:512k(boot0),512k(boot1),64k@1024k(eeprom) block2mtd.block2mtd=/dev/sda2,65536,rootfs,5 root=/dev/mtdblock3 rootfstype=squashfs rootwait + +define Image/BuildKernel + $(call Image/BuildKernel/Template,generic,) + $(call Image/BuildKernel/Template,er,$(ER_CMDLINE)) + $(call Image/BuildKernel/Template,erlite,$(ERLITE_CMDLINE)) +endef + +define Image/BuildKernel/Initramfs + $(call Image/BuildKernel/Initramfs/Template,generic,) + $(call Image/BuildKernel/Initramfs/Template,er,$(ER_CMDLINE)) + $(call Image/BuildKernel/Initramfs/Template,erlite,$(ERLITE_CMDLINE)) +endef + +define Image/Build/sysupgrade + mkdir -p $(KDIR)/sysupgrade-$(1)/ + echo "BOARD=$(1)" > $(KDIR)/sysupgrade-$(1)/CONTROL + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-$(2)-vmlinux.64 $(KDIR)/sysupgrade-$(1)/kernel + $(CP) $(KDIR)/root.$(3) $(KDIR)/sysupgrade-$(1)/root + (cd $(KDIR); $(TAR) cvf \ + $(BIN_DIR)/$(IMG_PREFIX)-$(1)-$(3)-sysupgrade.tar sysupgrade-$(1)) +endef + +define Image/Build/ext4 + $(call Image/Build/sysupgrade,erlite,generic,ext4) +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + $(call Image/Build/sysupgrade,er,er,squashfs) + $(call Image/Build/sysupgrade,erlite,erlite,squashfs) +endef + +define Image/Build + $(call Image/Build/$(1)) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/octeon/patches-3.18/100-ubnt_edgerouter2_support.patch b/target/linux/octeon/patches-3.18/100-ubnt_edgerouter2_support.patch new file mode 100644 index 0000000..5b51b66 --- /dev/null +++ b/target/linux/octeon/patches-3.18/100-ubnt_edgerouter2_support.patch @@ -0,0 +1,31 @@ +--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h ++++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h +@@ -228,6 +228,8 @@ enum cvmx_board_types_enum { + */ + CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, + CVMX_BOARD_TYPE_UBNT_E100 = 20002, ++ CVMX_BOARD_TYPE_UBNT_E200 = 20003, ++ CVMX_BOARD_TYPE_UBNT_E220 = 20005, + CVMX_BOARD_TYPE_CUST_DSR1000N = 20006, + CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, + +@@ -328,6 +330,8 @@ static inline const char *cvmx_board_typ + /* Customer private range */ + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) ++ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200) ++ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) + } +--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c ++++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c +@@ -195,6 +195,8 @@ int cvmx_helper_board_get_mii_address(in + return 8; + else + return -1; ++ case CVMX_BOARD_TYPE_UBNT_E200: ++ return -1; + } + + /* Some unknown board. Somebody forgot to update this function... */ diff --git a/target/linux/octeon/patches-3.18/110-er200-ethernet_probe_order.patch b/target/linux/octeon/patches-3.18/110-er200-ethernet_probe_order.patch new file mode 100644 index 0000000..f5a943c --- /dev/null +++ b/target/linux/octeon/patches-3.18/110-er200-ethernet_probe_order.patch @@ -0,0 +1,34 @@ +--- a/drivers/staging/octeon/ethernet.c ++++ b/drivers/staging/octeon/ethernet.c +@@ -620,6 +620,7 @@ static int cvm_oct_probe(struct platform + int interface; + int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; + int qos; ++ int i; + struct device_node *pip; + + octeon_mdiobus_force_mod_depencency(); +@@ -705,13 +706,19 @@ static int cvm_oct_probe(struct platform + } + + num_interfaces = cvmx_helper_get_number_of_interfaces(); +- for (interface = 0; interface < num_interfaces; interface++) { +- cvmx_helper_interface_mode_t imode = +- cvmx_helper_interface_get_mode(interface); +- int num_ports = cvmx_helper_ports_on_interface(interface); ++ for (i = 0; i < num_interfaces; i++) { ++ cvmx_helper_interface_mode_t imode; ++ int interface; ++ int num_ports; + int port; + int port_index; + ++ interface = i; ++ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200) ++ interface = num_interfaces - (i + 1); ++ ++ num_ports = cvmx_helper_ports_on_interface(interface); ++ imode = cvmx_helper_interface_get_mode(interface); + for (port_index = 0, + port = cvmx_helper_get_ipd_port(interface, 0); + port < cvmx_helper_get_ipd_port(interface, num_ports); diff --git a/target/linux/octeon/patches-3.18/120-octeon_platform_usb.patch b/target/linux/octeon/patches-3.18/120-octeon_platform_usb.patch new file mode 100644 index 0000000..7cffaf6 --- /dev/null +++ b/target/linux/octeon/patches-3.18/120-octeon_platform_usb.patch @@ -0,0 +1,20 @@ +--- a/arch/mips/cavium-octeon/octeon-platform.c ++++ b/arch/mips/cavium-octeon/octeon-platform.c +@@ -82,7 +82,7 @@ static int __init octeon_ehci_device_ini + }; + + /* Only Octeon2 has ehci/ohci */ +- if (!OCTEON_IS_MODEL(OCTEON_CN63XX)) ++ if (!OCTEON_IS_MODEL(OCTEON_CN6XXX)) + return 0; + + if (octeon_is_simulation() || usb_disabled()) +@@ -131,7 +131,7 @@ static int __init octeon_ohci_device_ini + }; + + /* Only Octeon2 has ehci/ohci */ +- if (!OCTEON_IS_MODEL(OCTEON_CN63XX)) ++ if (!OCTEON_IS_MODEL(OCTEON_CN6XXX)) + return 0; + + if (octeon_is_simulation() || usb_disabled()) diff --git a/target/linux/octeon/patches-3.18/130-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch b/target/linux/octeon/patches-3.18/130-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch new file mode 100644 index 0000000..bfbb4a5 --- /dev/null +++ b/target/linux/octeon/patches-3.18/130-MIPS-octeon-add-semaphore-to-serialize-bootbus-access.patch @@ -0,0 +1,21 @@ +--- a/arch/mips/cavium-octeon/setup.c ++++ b/arch/mips/cavium-octeon/setup.c +@@ -50,6 +50,9 @@ extern void pci_console_init(const char + + static unsigned long long MAX_MEMORY = 512ull << 20; + ++DEFINE_SEMAPHORE(octeon_bootbus_sem); ++EXPORT_SYMBOL(octeon_bootbus_sem); ++ + struct octeon_boot_descriptor *octeon_boot_desc_ptr; + + struct cvmx_bootinfo *octeon_bootinfo; +--- a/arch/mips/include/asm/octeon/octeon.h ++++ b/arch/mips/include/asm/octeon/octeon.h +@@ -252,4 +252,6 @@ void octeon_irq_set_ip4_handler(octeon_i + + extern void octeon_fixup_irqs(void); + ++extern struct semaphore octeon_bootbus_sem; ++ + #endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/target/linux/octeon/patches-3.18/140-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch b/target/linux/octeon/patches-3.18/140-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch new file mode 100644 index 0000000..d3986c7 --- /dev/null +++ b/target/linux/octeon/patches-3.18/140-MIPS-OCTEON-Update-octeon-model.h-code-for-new-SoCs.patch @@ -0,0 +1,103 @@ +--- a/arch/mips/include/asm/octeon/octeon-model.h ++++ b/arch/mips/include/asm/octeon/octeon-model.h +@@ -45,6 +45,7 @@ + */ + + #define OCTEON_FAMILY_MASK 0x00ffff00 ++#define OCTEON_PRID_MASK 0x00ffffff + + /* Flag bits in top byte */ + /* Ignores revision in model checks */ +@@ -63,6 +64,46 @@ + #define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 + /* Match all cnf7XXX Octeon models. */ + #define OM_MATCH_F7XXX_FAMILY_MODELS 0x80000000 ++/* Match all cn7XXX Octeon models. */ ++#define OM_MATCH_7XXX_FAMILY_MODELS 0x10000000 ++#define OM_MATCH_FAMILY_MODELS (OM_MATCH_5XXX_FAMILY_MODELS | \ ++ OM_MATCH_6XXX_FAMILY_MODELS | \ ++ OM_MATCH_F7XXX_FAMILY_MODELS | \ ++ OM_MATCH_7XXX_FAMILY_MODELS) ++/* ++ * CN7XXX models with new revision encoding ++ */ ++ ++#define OCTEON_CN73XX_PASS1_0 0x000d9700 ++#define OCTEON_CN73XX (OCTEON_CN73XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN73XX_PASS1_X (OCTEON_CN73XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN70XX_PASS1_0 0x000d9600 ++#define OCTEON_CN70XX_PASS1_1 0x000d9601 ++#define OCTEON_CN70XX_PASS1_2 0x000d9602 ++ ++#define OCTEON_CN70XX_PASS2_0 0x000d9608 ++ ++#define OCTEON_CN70XX (OCTEON_CN70XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN70XX_PASS1_X (OCTEON_CN70XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++#define OCTEON_CN70XX_PASS2_X (OCTEON_CN70XX_PASS2_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN71XX OCTEON_CN70XX ++ ++#define OCTEON_CN78XX_PASS1_0 0x000d9500 ++#define OCTEON_CN78XX_PASS1_1 0x000d9501 ++#define OCTEON_CN78XX_PASS2_0 0x000d9508 ++ ++#define OCTEON_CN78XX (OCTEON_CN78XX_PASS1_0 | OM_IGNORE_REVISION) ++#define OCTEON_CN78XX_PASS1_X (OCTEON_CN78XX_PASS1_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++#define OCTEON_CN78XX_PASS2_X (OCTEON_CN78XX_PASS2_0 | \ ++ OM_IGNORE_MINOR_REVISION) ++ ++#define OCTEON_CN76XX (0x000d9540 | OM_CHECK_SUBMODEL) + + /* + * CNF7XXX models with new revision encoding +@@ -217,6 +258,10 @@ + #define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION) + #define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) + #define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) ++#define OCTEON_CNF7XXX (OCTEON_CNF71XX_PASS1_0 | \ ++ OM_MATCH_F7XXX_FAMILY_MODELS) ++#define OCTEON_CN7XXX (OCTEON_CN78XX_PASS1_0 | \ ++ OM_MATCH_7XXX_FAMILY_MODELS) + + /* These are used to cover entire families of OCTEON processors */ + #define OCTEON_FAM_1 (OCTEON_CN3XXX) +@@ -288,9 +333,16 @@ static inline uint64_t cvmx_read_csr(uin + ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \ + && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \ + ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \ +- && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \ ++ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN58XX_PASS1_0) \ ++ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN63XX_PASS1_0)) || \ + ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \ +- && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \ ++ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN63XX_PASS1_0) \ ++ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CNF71XX_PASS1_0)) || \ ++ ((((arg_model) & (OM_MATCH_F7XXX_FAMILY_MODELS)) == OM_MATCH_F7XXX_FAMILY_MODELS) \ ++ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CNF71XX_PASS1_0) \ ++ && ((chip_model & OCTEON_PRID_MASK) < OCTEON_CN78XX_PASS1_0)) || \ ++ ((((arg_model) & (OM_MATCH_7XXX_FAMILY_MODELS)) == OM_MATCH_7XXX_FAMILY_MODELS) \ ++ && ((chip_model & OCTEON_PRID_MASK) >= OCTEON_CN78XX_PASS1_0)) || \ + ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \ + && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \ + ))) +@@ -326,6 +378,15 @@ static inline int __octeon_is_model_runt + #define OCTEON_IS_COMMON_BINARY() 1 + #undef OCTEON_MODEL + ++#define OCTEON_IS_OCTEON1() OCTEON_IS_MODEL(OCTEON_CN3XXX) ++#define OCTEON_IS_OCTEONPLUS() OCTEON_IS_MODEL(OCTEON_CN5XXX) ++#define OCTEON_IS_OCTEON2() \ ++ (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)) ++ ++#define OCTEON_IS_OCTEON3() OCTEON_IS_MODEL(OCTEON_CN7XXX) ++ ++#define OCTEON_IS_OCTEON1PLUS() (OCTEON_IS_OCTEON1() || OCTEON_IS_OCTEONPLUS()) ++ + const char *octeon_model_get_string(uint32_t chip_id); + const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer); + diff --git a/target/linux/octeon/patches-3.18/150-mmc-octeon-add-host-driver-for-octeon-mmc-controller.patch b/target/linux/octeon/patches-3.18/150-mmc-octeon-add-host-driver-for-octeon-mmc-controller.patch new file mode 100644 index 0000000..599d4e2 --- /dev/null +++ b/target/linux/octeon/patches-3.18/150-mmc-octeon-add-host-driver-for-octeon-mmc-controller.patch @@ -0,0 +1,1622 @@ +--- /dev/null ++++ b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt +@@ -0,0 +1,69 @@ ++* OCTEON SD/MMC Host Controller ++ ++This controller is present on some members of the Cavium OCTEON SoC ++family, provide an interface for eMMC, MMC and SD devices. There is a ++single controller that may have several "slots" connected. These ++slots appear as children of the main controller node. ++The DMA engine is an integral part of the controller block. ++ ++Required properties: ++- compatible : Should be "cavium,octeon-6130-mmc" or "cavium,octeon-7890-mmc" ++- reg : Two entries: ++ 1) The base address of the MMC controller register bank. ++ 2) The base address of the MMC DMA engine register bank. ++- interrupts : ++ For "cavium,octeon-6130-mmc": two entries: ++ 1) The MMC controller interrupt line. ++ 2) The MMC DMA engine interrupt line. ++ For "cavium,octeon-7890-mmc": nine entries: ++ 1) The next block transfer of a multiblock transfer has completed (BUF_DONE) ++ 2) Operation completed successfully (CMD_DONE). ++ 3) DMA transfer completed successfully (DMA_DONE). ++ 4) Operation encountered an error (CMD_ERR). ++ 5) DMA transfer encountered an error (DMA_ERR). ++ 6) Switch operation completed successfully (SWITCH_DONE). ++ 7) Switch operation encountered an error (SWITCH_ERR). ++ 8) Internal DMA engine request completion interrupt (DONE). ++ 9) Internal DMA FIFO underflow (FIFO). ++- #address-cells : Must be <1> ++- #size-cells : Must be <0> ++ ++Required properties of child nodes: ++- compatible : Should be "cavium,octeon-6130-mmc-slot". ++- reg : The slot number. ++ ++Optional properties of child nodes: ++- cd-gpios : Specify GPIOs for card detection ++- wp-gpios : Specify GPIOs for write protection ++- power-gpios : Specify GPIOs for power control ++- cavium,bus-max-width : The number of data lines present in the slot. ++ Default is 8. ++- spi-max-frequency : The maximum operating frequency of the slot. ++ Default is 52000000. ++- cavium,cmd-clk-skew : the amount of delay (in pS) past the clock edge ++ to sample the command pin. ++- cavium,dat-clk-skew : the amount of delay (in pS) past the clock edge ++ to sample the data pin. ++ ++Example: ++ mmc@1180000002000 { ++ compatible = "cavium,octeon-6130-mmc"; ++ reg = <0x11800 0x00002000 0x0 0x100>, ++ <0x11800 0x00000168 0x0 0x20>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ /* EMM irq, DMA irq */ ++ interrupts = <1 19>, <0 63>; ++ ++ /* The board only has a single MMC slot */ ++ mmc-slot@0 { ++ compatible = "cavium,octeon-6130-mmc-slot"; ++ reg = <0>; ++ spi-max-frequency = <20000000>; ++ /* bus width can be 1, 4 or 8 */ ++ cavium,bus-max-width = <8>; ++ cd-gpios = <&gpio 9 0>; ++ wp-gpios = <&gpio 10 0>; ++ power-gpios = <&gpio 8 0>; ++ }; ++ }; +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -405,6 +405,16 @@ config MMC_MXS + + If unsure, say N. + ++config MMC_OCTEON ++ tristate "Cavium OCTEON Multimedia Card Interface support" ++ depends on CAVIUM_OCTEON_SOC ++ help ++ This selects Cavium OCTEON Multimedia card Interface. ++ If you have an OCTEON board with a Multimedia Card slot, ++ say Y or M here. ++ ++ If unsure, say N. ++ + config MMC_TIFM_SD + tristate "TI Flash Media MMC/SD Interface support" + depends on PCI +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci + obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o + obj-$(CONFIG_MMC_WBSD) += wbsd.o + obj-$(CONFIG_MMC_AU1X) += au1xmmc.o ++obj-$(CONFIG_MMC_OCTEON) += octeon_mmc.o + obj-$(CONFIG_MMC_OMAP) += omap.o + obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o + obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o +--- /dev/null ++++ b/drivers/mmc/host/octeon_mmc.c +@@ -0,0 +1,1518 @@ ++/* ++ * Driver for MMC and SSD cards for Cavium OCTEON SOCs. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2012-2014 Cavium Inc. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define DRV_NAME "octeon_mmc" ++ ++#define OCTEON_MAX_MMC 4 ++ ++#define OCT_MIO_NDF_DMA_CFG 0x00 ++#define OCT_MIO_EMM_DMA_ADR 0x08 ++ ++#define OCT_MIO_EMM_CFG 0x00 ++#define OCT_MIO_EMM_SWITCH 0x48 ++#define OCT_MIO_EMM_DMA 0x50 ++#define OCT_MIO_EMM_CMD 0x58 ++#define OCT_MIO_EMM_RSP_STS 0x60 ++#define OCT_MIO_EMM_RSP_LO 0x68 ++#define OCT_MIO_EMM_RSP_HI 0x70 ++#define OCT_MIO_EMM_INT 0x78 ++#define OCT_MIO_EMM_INT_EN 0x80 ++#define OCT_MIO_EMM_WDOG 0x88 ++#define OCT_MIO_EMM_SAMPLE 0x90 ++#define OCT_MIO_EMM_STS_MASK 0x98 ++#define OCT_MIO_EMM_RCA 0xa0 ++#define OCT_MIO_EMM_BUF_IDX 0xe0 ++#define OCT_MIO_EMM_BUF_DAT 0xe8 ++ ++#define CVMX_MIO_BOOT_CTL CVMX_ADD_IO_SEG(0x00011800000000D0ull) ++ ++struct octeon_mmc_host { ++ u64 base; ++ u64 ndf_base; ++ u64 emm_cfg; ++ u64 n_minus_one; /* OCTEON II workaround location */ ++ int last_slot; ++ ++ struct semaphore mmc_serializer; ++ struct mmc_request *current_req; ++ unsigned int linear_buf_size; ++ void *linear_buf; ++ struct sg_mapping_iter smi; ++ int sg_idx; ++ bool dma_active; ++ ++ struct platform_device *pdev; ++ int global_pwr_gpio; ++ bool global_pwr_gpio_low; ++ bool dma_err_pending; ++ bool need_bootbus_lock; ++ bool big_dma_addr; ++ bool need_irq_handler_lock; ++ spinlock_t irq_handler_lock; ++ ++ struct octeon_mmc_slot *slot[OCTEON_MAX_MMC]; ++}; ++ ++struct octeon_mmc_slot { ++ struct mmc_host *mmc; /* slot-level mmc_core object */ ++ struct octeon_mmc_host *host; /* common hw for all 4 slots */ ++ ++ unsigned int clock; ++ unsigned int sclock; ++ ++ u64 cached_switch; ++ u64 cached_rca; ++ ++ unsigned int cmd_cnt; /* sample delay */ ++ unsigned int dat_cnt; /* sample delay */ ++ ++ int bus_width; ++ int bus_id; ++ int ro_gpio; ++ int cd_gpio; ++ int pwr_gpio; ++ bool cd_gpio_low; ++ bool ro_gpio_low; ++ bool pwr_gpio_low; ++}; ++ ++static int bb_size = 1 << 16; ++module_param(bb_size, int, S_IRUGO); ++MODULE_PARM_DESC(bb_size, ++ "Size of DMA linearizing buffer (max transfer size)."); ++ ++static int ddr = 2; ++module_param(ddr, int, S_IRUGO); ++MODULE_PARM_DESC(ddr, ++ "enable DoubleDataRate clocking: 0=no, 1=always, 2=at spi-max-frequency/2"); ++ ++#if 0 ++#define octeon_mmc_dbg trace_printk ++#else ++static inline void octeon_mmc_dbg(const char *s, ...) { } ++#endif ++ ++static void octeon_mmc_acquire_bus(struct octeon_mmc_host *host) ++{ ++ if (host->need_bootbus_lock) { ++ down(&octeon_bootbus_sem); ++ /* On cn70XX switch the mmc unit onto the bus. */ ++ if (OCTEON_IS_MODEL(OCTEON_CN70XX)) ++ cvmx_write_csr(CVMX_MIO_BOOT_CTL, 0); ++ } else { ++ down(&host->mmc_serializer); ++ } ++} ++ ++static void octeon_mmc_release_bus(struct octeon_mmc_host *host) ++{ ++ if (host->need_bootbus_lock) ++ up(&octeon_bootbus_sem); ++ else ++ up(&host->mmc_serializer); ++} ++ ++struct octeon_mmc_cr_type { ++ u8 ctype; ++ u8 rtype; ++}; ++ ++/* ++ * The OCTEON MMC host hardware assumes that all commands have fixed ++ * command and response types. These are correct if MMC devices are ++ * being used. However, non-MMC devices like SD use command and ++ * response types that are unexpected by the host hardware. ++ * ++ * The command and response types can be overridden by supplying an ++ * XOR value that is applied to the type. We calculate the XOR value ++ * from the values in this table and the flags passed from the MMC ++ * core. ++ */ ++static struct octeon_mmc_cr_type octeon_mmc_cr_types[] = { ++ {0, 0}, /* CMD0 */ ++ {0, 3}, /* CMD1 */ ++ {0, 2}, /* CMD2 */ ++ {0, 1}, /* CMD3 */ ++ {0, 0}, /* CMD4 */ ++ {0, 1}, /* CMD5 */ ++ {0, 1}, /* CMD6 */ ++ {0, 1}, /* CMD7 */ ++ {1, 1}, /* CMD8 */ ++ {0, 2}, /* CMD9 */ ++ {0, 2}, /* CMD10 */ ++ {1, 1}, /* CMD11 */ ++ {0, 1}, /* CMD12 */ ++ {0, 1}, /* CMD13 */ ++ {1, 1}, /* CMD14 */ ++ {0, 0}, /* CMD15 */ ++ {0, 1}, /* CMD16 */ ++ {1, 1}, /* CMD17 */ ++ {1, 1}, /* CMD18 */ ++ {3, 1}, /* CMD19 */ ++ {2, 1}, /* CMD20 */ ++ {0, 0}, /* CMD21 */ ++ {0, 0}, /* CMD22 */ ++ {0, 1}, /* CMD23 */ ++ {2, 1}, /* CMD24 */ ++ {2, 1}, /* CMD25 */ ++ {2, 1}, /* CMD26 */ ++ {2, 1}, /* CMD27 */ ++ {0, 1}, /* CMD28 */ ++ {0, 1}, /* CMD29 */ ++ {1, 1}, /* CMD30 */ ++ {1, 1}, /* CMD31 */ ++ {0, 0}, /* CMD32 */ ++ {0, 0}, /* CMD33 */ ++ {0, 0}, /* CMD34 */ ++ {0, 1}, /* CMD35 */ ++ {0, 1}, /* CMD36 */ ++ {0, 0}, /* CMD37 */ ++ {0, 1}, /* CMD38 */ ++ {0, 4}, /* CMD39 */ ++ {0, 5}, /* CMD40 */ ++ {0, 0}, /* CMD41 */ ++ {2, 1}, /* CMD42 */ ++ {0, 0}, /* CMD43 */ ++ {0, 0}, /* CMD44 */ ++ {0, 0}, /* CMD45 */ ++ {0, 0}, /* CMD46 */ ++ {0, 0}, /* CMD47 */ ++ {0, 0}, /* CMD48 */ ++ {0, 0}, /* CMD49 */ ++ {0, 0}, /* CMD50 */ ++ {0, 0}, /* CMD51 */ ++ {0, 0}, /* CMD52 */ ++ {0, 0}, /* CMD53 */ ++ {0, 0}, /* CMD54 */ ++ {0, 1}, /* CMD55 */ ++ {0xff, 0xff}, /* CMD56 */ ++ {0, 0}, /* CMD57 */ ++ {0, 0}, /* CMD58 */ ++ {0, 0}, /* CMD59 */ ++ {0, 0}, /* CMD60 */ ++ {0, 0}, /* CMD61 */ ++ {0, 0}, /* CMD62 */ ++ {0, 0} /* CMD63 */ ++}; ++ ++struct octeon_mmc_cr_mods { ++ u8 ctype_xor; ++ u8 rtype_xor; ++}; ++ ++/* ++ * The functions below are used for the EMMC-17978 workaround. ++ * ++ * Due to an imperfection in the design of the MMC bus hardware, ++ * the 2nd to last cache block of a DMA read must be locked into the L2 Cache. ++ * Otherwise, data corruption may occur. ++ */ ++ ++static inline void *phys_to_ptr(u64 address) ++{ ++ return (void *)(address | (1ull<<63)); /* XKPHYS */ ++} ++ ++/** ++ * Lock a single line into L2. The line is zeroed before locking ++ * to make sure no dram accesses are made. ++ * ++ * @addr Physical address to lock ++ */ ++static void l2c_lock_line(u64 addr) ++{ ++ char *addr_ptr = phys_to_ptr(addr); ++ ++ asm volatile ( ++ "cache 31, %[line]" /* Unlock the line */ ++ :: [line] "m" (*addr_ptr)); ++} ++ ++/** ++ * Locks a memory region in the L2 cache ++ * ++ * @start - start address to begin locking ++ * @len - length in bytes to lock ++ */ ++static void l2c_lock_mem_region(u64 start, u64 len) ++{ ++ u64 end; ++ ++ /* Round start/end to cache line boundaries */ ++ end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE); ++ start = ALIGN(start, CVMX_CACHE_LINE_SIZE); ++ ++ while (start <= end) { ++ l2c_lock_line(start); ++ start += CVMX_CACHE_LINE_SIZE; ++ } ++ asm volatile("sync"); ++} ++ ++/** ++ * Unlock a single line in the L2 cache. ++ * ++ * @addr Physical address to unlock ++ * ++ * Return Zero on success ++ */ ++static void l2c_unlock_line(u64 addr) ++{ ++ char *addr_ptr = phys_to_ptr(addr); ++ asm volatile ( ++ "cache 23, %[line]" /* Unlock the line */ ++ :: [line] "m" (*addr_ptr)); ++} ++ ++/** ++ * Unlock a memory region in the L2 cache ++ * ++ * @start - start address to unlock ++ * @len - length to unlock in bytes ++ */ ++static void l2c_unlock_mem_region(u64 start, u64 len) ++{ ++ u64 end; ++ ++ /* Round start/end to cache line boundaries */ ++ end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE); ++ start = ALIGN(start, CVMX_CACHE_LINE_SIZE); ++ ++ while (start <= end) { ++ l2c_unlock_line(start); ++ start += CVMX_CACHE_LINE_SIZE; ++ } ++} ++ ++static struct octeon_mmc_cr_mods octeon_mmc_get_cr_mods(struct mmc_command *cmd) ++{ ++ struct octeon_mmc_cr_type *cr; ++ u8 desired_ctype, hardware_ctype; ++ u8 desired_rtype, hardware_rtype; ++ struct octeon_mmc_cr_mods r; ++ ++ desired_ctype = desired_rtype = 0; ++ ++ cr = octeon_mmc_cr_types + (cmd->opcode & 0x3f); ++ hardware_ctype = cr->ctype; ++ hardware_rtype = cr->rtype; ++ if (cmd->opcode == 56) { /* CMD56 GEN_CMD */ ++ hardware_ctype = (cmd->arg & 1) ? 1 : 2; ++ } ++ ++ switch (mmc_cmd_type(cmd)) { ++ case MMC_CMD_ADTC: ++ desired_ctype = (cmd->data->flags & MMC_DATA_WRITE) ? 2 : 1; ++ break; ++ case MMC_CMD_AC: ++ case MMC_CMD_BC: ++ case MMC_CMD_BCR: ++ desired_ctype = 0; ++ break; ++ } ++ ++ switch (mmc_resp_type(cmd)) { ++ case MMC_RSP_NONE: ++ desired_rtype = 0; ++ break; ++ case MMC_RSP_R1:/* MMC_RSP_R5, MMC_RSP_R6, MMC_RSP_R7 */ ++ case MMC_RSP_R1B: ++ desired_rtype = 1; ++ break; ++ case MMC_RSP_R2: ++ desired_rtype = 2; ++ break; ++ case MMC_RSP_R3: /* MMC_RSP_R4 */ ++ desired_rtype = 3; ++ break; ++ } ++ r.ctype_xor = desired_ctype ^ hardware_ctype; ++ r.rtype_xor = desired_rtype ^ hardware_rtype; ++ return r; ++} ++ ++static bool octeon_mmc_switch_val_changed(struct octeon_mmc_slot *slot, ++ u64 new_val) ++{ ++ /* Match BUS_ID, HS_TIMING, BUS_WIDTH, POWER_CLASS, CLK_HI, CLK_LO */ ++ u64 m = 0x3001070fffffffffull; ++ ++ return (slot->cached_switch & m) != (new_val & m); ++} ++ ++static unsigned int octeon_mmc_timeout_to_wdog(struct octeon_mmc_slot *slot, ++ unsigned int ns) ++{ ++ u64 bt = (u64)slot->clock * (u64)ns; ++ ++ return (unsigned int)(bt / 1000000000); ++} ++ ++static irqreturn_t octeon_mmc_interrupt(int irq, void *dev_id) ++{ ++ struct octeon_mmc_host *host = dev_id; ++ union cvmx_mio_emm_int emm_int; ++ struct mmc_request *req; ++ bool host_done; ++ union cvmx_mio_emm_rsp_sts rsp_sts; ++ unsigned long flags = 0; ++ ++ if (host->need_irq_handler_lock) ++ spin_lock_irqsave(&host->irq_handler_lock, flags); ++ emm_int.u64 = cvmx_read_csr(host->base + OCT_MIO_EMM_INT); ++ req = host->current_req; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_INT, emm_int.u64); ++ ++ octeon_mmc_dbg("Got interrupt: EMM_INT = 0x%llx\n", emm_int.u64); ++ ++ if (!req) ++ goto out; ++ ++ rsp_sts.u64 = cvmx_read_csr(host->base + OCT_MIO_EMM_RSP_STS); ++ octeon_mmc_dbg("octeon_mmc_interrupt MIO_EMM_RSP_STS 0x%llx\n", ++ rsp_sts.u64); ++ ++ if (host->dma_err_pending) { ++ host->current_req = NULL; ++ host->dma_err_pending = false; ++ req->done(req); ++ host_done = true; ++ goto no_req_done; ++ } ++ ++ if (!host->dma_active && emm_int.s.buf_done && req->data) { ++ unsigned int type = (rsp_sts.u64 >> 7) & 3; ++ ++ if (type == 1) { ++ /* Read */ ++ int dbuf = rsp_sts.s.dbuf; ++ struct sg_mapping_iter *smi = &host->smi; ++ unsigned int data_len = ++ req->data->blksz * req->data->blocks; ++ unsigned int bytes_xfered; ++ u64 dat = 0; ++ int shift = -1; ++ ++ /* Auto inc from offset zero */ ++ cvmx_write_csr(host->base + OCT_MIO_EMM_BUF_IDX, ++ (u64)(0x10000 | (dbuf << 6))); ++ ++ for (bytes_xfered = 0; bytes_xfered < data_len;) { ++ if (smi->consumed >= smi->length) { ++ if (!sg_miter_next(smi)) ++ break; ++ smi->consumed = 0; ++ } ++ if (shift < 0) { ++ dat = cvmx_read_csr(host->base + ++ OCT_MIO_EMM_BUF_DAT); ++ shift = 56; ++ } ++ ++ while (smi->consumed < smi->length && ++ shift >= 0) { ++ ((u8 *)(smi->addr))[smi->consumed] = ++ (dat >> shift) & 0xff; ++ bytes_xfered++; ++ smi->consumed++; ++ shift -= 8; ++ } ++ } ++ sg_miter_stop(smi); ++ req->data->bytes_xfered = bytes_xfered; ++ req->data->error = 0; ++ } else if (type == 2) { ++ /* write */ ++ req->data->bytes_xfered = req->data->blksz * ++ req->data->blocks; ++ req->data->error = 0; ++ } ++ } ++ host_done = emm_int.s.cmd_done || emm_int.s.dma_done || ++ emm_int.s.cmd_err || emm_int.s.dma_err; ++ if (host_done && req->done) { ++ if (rsp_sts.s.rsp_bad_sts || ++ rsp_sts.s.rsp_crc_err || ++ rsp_sts.s.rsp_timeout || ++ rsp_sts.s.blk_crc_err || ++ rsp_sts.s.blk_timeout || ++ rsp_sts.s.dbuf_err) { ++ req->cmd->error = -EILSEQ; ++ } else { ++ req->cmd->error = 0; ++ } ++ ++ if (host->dma_active && req->data) { ++ req->data->error = 0; ++ req->data->bytes_xfered = req->data->blocks * ++ req->data->blksz; ++ if (!(req->data->flags & MMC_DATA_WRITE) && ++ req->data->sg_len > 1) { ++ size_t r = sg_copy_from_buffer(req->data->sg, ++ req->data->sg_len, host->linear_buf, ++ req->data->bytes_xfered); ++ WARN_ON(r != req->data->bytes_xfered); ++ } ++ } ++ if (rsp_sts.s.rsp_val) { ++ u64 rsp_hi; ++ u64 rsp_lo = cvmx_read_csr( ++ host->base + OCT_MIO_EMM_RSP_LO); ++ ++ switch (rsp_sts.s.rsp_type) { ++ case 1: ++ case 3: ++ req->cmd->resp[0] = (rsp_lo >> 8) & 0xffffffff; ++ req->cmd->resp[1] = 0; ++ req->cmd->resp[2] = 0; ++ req->cmd->resp[3] = 0; ++ break; ++ case 2: ++ req->cmd->resp[3] = rsp_lo & 0xffffffff; ++ req->cmd->resp[2] = (rsp_lo >> 32) & 0xffffffff; ++ rsp_hi = cvmx_read_csr(host->base + ++ OCT_MIO_EMM_RSP_HI); ++ req->cmd->resp[1] = rsp_hi & 0xffffffff; ++ req->cmd->resp[0] = (rsp_hi >> 32) & 0xffffffff; ++ break; ++ default: ++ octeon_mmc_dbg("octeon_mmc_interrupt unhandled rsp_val %d\n", ++ rsp_sts.s.rsp_type); ++ break; ++ } ++ octeon_mmc_dbg("octeon_mmc_interrupt resp %08x %08x %08x %08x\n", ++ req->cmd->resp[0], req->cmd->resp[1], ++ req->cmd->resp[2], req->cmd->resp[3]); ++ } ++ if (emm_int.s.dma_err && rsp_sts.s.dma_pend) { ++ /* Try to clean up failed DMA */ ++ union cvmx_mio_emm_dma emm_dma; ++ ++ emm_dma.u64 = ++ cvmx_read_csr(host->base + OCT_MIO_EMM_DMA); ++ emm_dma.s.dma_val = 1; ++ emm_dma.s.dat_null = 1; ++ emm_dma.s.bus_id = rsp_sts.s.bus_id; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_DMA, ++ emm_dma.u64); ++ host->dma_err_pending = true; ++ host_done = false; ++ goto no_req_done; ++ } ++ ++ host->current_req = NULL; ++ req->done(req); ++ } ++no_req_done: ++ if (host->n_minus_one) { ++ l2c_unlock_mem_region(host->n_minus_one, 512); ++ host->n_minus_one = 0; ++ } ++ if (host_done) ++ octeon_mmc_release_bus(host); ++out: ++ if (host->need_irq_handler_lock) ++ spin_unlock_irqrestore(&host->irq_handler_lock, flags); ++ return IRQ_RETVAL(emm_int.u64 != 0); ++} ++ ++static void octeon_mmc_switch_to(struct octeon_mmc_slot *slot) ++{ ++ struct octeon_mmc_host *host = slot->host; ++ struct octeon_mmc_slot *old_slot; ++ union cvmx_mio_emm_switch sw; ++ union cvmx_mio_emm_sample samp; ++ ++ if (slot->bus_id == host->last_slot) ++ goto out; ++ ++ if (host->last_slot >= 0) { ++ old_slot = host->slot[host->last_slot]; ++ old_slot->cached_switch = ++ cvmx_read_csr(host->base + OCT_MIO_EMM_SWITCH); ++ old_slot->cached_rca = ++ cvmx_read_csr(host->base + OCT_MIO_EMM_RCA); ++ } ++ cvmx_write_csr(host->base + OCT_MIO_EMM_RCA, slot->cached_rca); ++ sw.u64 = slot->cached_switch; ++ sw.s.bus_id = 0; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_SWITCH, sw.u64); ++ sw.s.bus_id = slot->bus_id; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_SWITCH, sw.u64); ++ ++ samp.u64 = 0; ++ samp.s.cmd_cnt = slot->cmd_cnt; ++ samp.s.dat_cnt = slot->dat_cnt; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_SAMPLE, samp.u64); ++out: ++ host->last_slot = slot->bus_id; ++} ++ ++static void octeon_mmc_dma_request(struct mmc_host *mmc, ++ struct mmc_request *mrq) ++{ ++ struct octeon_mmc_slot *slot; ++ struct octeon_mmc_host *host; ++ struct mmc_command *cmd; ++ struct mmc_data *data; ++ union cvmx_mio_emm_int emm_int; ++ union cvmx_mio_emm_dma emm_dma; ++ union cvmx_mio_ndf_dma_cfg dma_cfg; ++ ++ cmd = mrq->cmd; ++ if (mrq->data == NULL || mrq->data->sg == NULL || !mrq->data->sg_len || ++ mrq->stop == NULL || mrq->stop->opcode != MMC_STOP_TRANSMISSION) { ++ dev_err(&mmc->card->dev, ++ "Error: octeon_mmc_dma_request no data\n"); ++ cmd->error = -EINVAL; ++ if (mrq->done) ++ mrq->done(mrq); ++ return; ++ } ++ ++ slot = mmc_priv(mmc); ++ host = slot->host; ++ ++ /* Only a single user of the bootbus at a time. */ ++ octeon_mmc_acquire_bus(host); ++ ++ octeon_mmc_switch_to(slot); ++ ++ data = mrq->data; ++ ++ if (data->timeout_ns) { ++ cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, ++ octeon_mmc_timeout_to_wdog(slot, data->timeout_ns)); ++ octeon_mmc_dbg("OCT_MIO_EMM_WDOG %llu\n", ++ cvmx_read_csr(host->base + OCT_MIO_EMM_WDOG)); ++ } ++ ++ WARN_ON(host->current_req); ++ host->current_req = mrq; ++ ++ host->sg_idx = 0; ++ ++ WARN_ON(data->blksz * data->blocks > host->linear_buf_size); ++ ++ if ((data->flags & MMC_DATA_WRITE) && data->sg_len > 1) { ++ size_t r = sg_copy_to_buffer(data->sg, data->sg_len, ++ host->linear_buf, data->blksz * data->blocks); ++ WARN_ON(data->blksz * data->blocks != r); ++ } ++ ++ dma_cfg.u64 = 0; ++ dma_cfg.s.en = 1; ++ dma_cfg.s.rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; ++#ifdef __LITTLE_ENDIAN ++ dma_cfg.s.endian = 1; ++#endif ++ dma_cfg.s.size = ((data->blksz * data->blocks) / 8) - 1; ++ if (!host->big_dma_addr) { ++ if (data->sg_len > 1) ++ dma_cfg.s.adr = virt_to_phys(host->linear_buf); ++ else ++ dma_cfg.s.adr = sg_phys(data->sg); ++ } ++ cvmx_write_csr(host->ndf_base + OCT_MIO_NDF_DMA_CFG, dma_cfg.u64); ++ octeon_mmc_dbg("MIO_NDF_DMA_CFG: %016llx\n", ++ (unsigned long long)dma_cfg.u64); ++ if (host->big_dma_addr) { ++ u64 addr; ++ ++ if (data->sg_len > 1) ++ addr = virt_to_phys(host->linear_buf); ++ else ++ addr = sg_phys(data->sg); ++ cvmx_write_csr(host->ndf_base + OCT_MIO_EMM_DMA_ADR, addr); ++ octeon_mmc_dbg("MIO_EMM_DMA_ADR: %016llx\n", ++ (unsigned long long)addr); ++ } ++ ++ emm_dma.u64 = 0; ++ emm_dma.s.bus_id = slot->bus_id; ++ emm_dma.s.dma_val = 1; ++ emm_dma.s.sector = mmc_card_blockaddr(mmc->card) ? 1 : 0; ++ emm_dma.s.rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; ++ if (mmc_card_mmc(mmc->card) || ++ (mmc_card_sd(mmc->card) && ++ (mmc->card->scr.cmds & SD_SCR_CMD23_SUPPORT))) ++ emm_dma.s.multi = 1; ++ emm_dma.s.block_cnt = data->blocks; ++ emm_dma.s.card_addr = cmd->arg; ++ ++ emm_int.u64 = 0; ++ emm_int.s.dma_done = 1; ++ emm_int.s.cmd_err = 1; ++ emm_int.s.dma_err = 1; ++ /* Clear the bit. */ ++ cvmx_write_csr(host->base + OCT_MIO_EMM_INT, emm_int.u64); ++ cvmx_write_csr(host->base + OCT_MIO_EMM_INT_EN, emm_int.u64); ++ host->dma_active = true; ++ ++ if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || ++ OCTEON_IS_MODEL(OCTEON_CNF7XXX)) && ++ cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK && ++ (data->blksz * data->blocks) > 1024) { ++ host->n_minus_one = dma_cfg.s.adr + ++ (data->blksz * data->blocks) - 1024; ++ l2c_lock_mem_region(host->n_minus_one, 512); ++ } ++ ++ if (mmc->card && mmc_card_sd(mmc->card)) ++ cvmx_write_csr(host->base + OCT_MIO_EMM_STS_MASK, ++ 0x00b00000ull); ++ else ++ cvmx_write_csr(host->base + OCT_MIO_EMM_STS_MASK, ++ 0xe4f90080ull); ++ cvmx_write_csr(host->base + OCT_MIO_EMM_DMA, emm_dma.u64); ++ octeon_mmc_dbg("MIO_EMM_DMA: %llx\n", emm_dma.u64); ++} ++ ++static void octeon_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct octeon_mmc_slot *slot; ++ struct octeon_mmc_host *host; ++ struct mmc_command *cmd; ++ union cvmx_mio_emm_int emm_int; ++ union cvmx_mio_emm_cmd emm_cmd; ++ struct octeon_mmc_cr_mods mods; ++ ++ cmd = mrq->cmd; ++ ++ if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK || ++ cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) { ++ octeon_mmc_dma_request(mmc, mrq); ++ return; ++ } ++ ++ mods = octeon_mmc_get_cr_mods(cmd); ++ ++ slot = mmc_priv(mmc); ++ host = slot->host; ++ ++ /* Only a single user of the bootbus at a time. */ ++ octeon_mmc_acquire_bus(host); ++ ++ octeon_mmc_switch_to(slot); ++ ++ WARN_ON(host->current_req); ++ host->current_req = mrq; ++ ++ emm_int.u64 = 0; ++ emm_int.s.cmd_done = 1; ++ emm_int.s.cmd_err = 1; ++ if (cmd->data) { ++ octeon_mmc_dbg("command has data\n"); ++ if (cmd->data->flags & MMC_DATA_READ) { ++ sg_miter_start(&host->smi, mrq->data->sg, ++ mrq->data->sg_len, ++ SG_MITER_ATOMIC | SG_MITER_TO_SG); ++ } else { ++ struct sg_mapping_iter *smi = &host->smi; ++ unsigned int data_len = ++ mrq->data->blksz * mrq->data->blocks; ++ unsigned int bytes_xfered; ++ u64 dat = 0; ++ int shift = 56; ++ /* ++ * Copy data to the xmit buffer before ++ * issuing the command ++ */ ++ sg_miter_start(smi, mrq->data->sg, ++ mrq->data->sg_len, SG_MITER_FROM_SG); ++ /* Auto inc from offset zero, dbuf zero */ ++ cvmx_write_csr(host->base + OCT_MIO_EMM_BUF_IDX, ++ 0x10000ull); ++ ++ for (bytes_xfered = 0; bytes_xfered < data_len;) { ++ if (smi->consumed >= smi->length) { ++ if (!sg_miter_next(smi)) ++ break; ++ smi->consumed = 0; ++ } ++ ++ while (smi->consumed < smi->length && ++ shift >= 0) { ++ ++ dat |= (u64)(((u8 *)(smi->addr)) ++ [smi->consumed]) << shift; ++ bytes_xfered++; ++ smi->consumed++; ++ shift -= 8; ++ } ++ if (shift < 0) { ++ cvmx_write_csr(host->base + ++ OCT_MIO_EMM_BUF_DAT, dat); ++ shift = 56; ++ dat = 0; ++ } ++ } ++ sg_miter_stop(smi); ++ } ++ if (cmd->data->timeout_ns) { ++ cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, ++ octeon_mmc_timeout_to_wdog(slot, ++ cmd->data->timeout_ns)); ++ octeon_mmc_dbg("OCT_MIO_EMM_WDOG %llu\n", ++ cvmx_read_csr(host->base + ++ OCT_MIO_EMM_WDOG)); ++ } ++ } else { ++ cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, ++ ((u64)slot->clock * 850ull) / 1000ull); ++ octeon_mmc_dbg("OCT_MIO_EMM_WDOG %llu\n", ++ cvmx_read_csr(host->base + OCT_MIO_EMM_WDOG)); ++ } ++ /* Clear the bit. */ ++ cvmx_write_csr(host->base + OCT_MIO_EMM_INT, emm_int.u64); ++ cvmx_write_csr(host->base + OCT_MIO_EMM_INT_EN, emm_int.u64); ++ host->dma_active = false; ++ ++ emm_cmd.u64 = 0; ++ emm_cmd.s.cmd_val = 1; ++ emm_cmd.s.ctype_xor = mods.ctype_xor; ++ emm_cmd.s.rtype_xor = mods.rtype_xor; ++ if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) ++ emm_cmd.s.offset = 64 - ++ ((cmd->data->blksz * cmd->data->blocks) / 8); ++ emm_cmd.s.bus_id = slot->bus_id; ++ emm_cmd.s.cmd_idx = cmd->opcode; ++ emm_cmd.s.arg = cmd->arg; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_STS_MASK, 0); ++ cvmx_write_csr(host->base + OCT_MIO_EMM_CMD, emm_cmd.u64); ++ octeon_mmc_dbg("MIO_EMM_CMD: %llx\n", emm_cmd.u64); ++} ++ ++static void octeon_mmc_reset_bus(struct octeon_mmc_slot *slot, int preserve) ++{ ++ union cvmx_mio_emm_cfg emm_cfg; ++ union cvmx_mio_emm_switch emm_switch; ++ u64 wdog = 0; ++ ++ emm_cfg.u64 = cvmx_read_csr(slot->host->base + OCT_MIO_EMM_CFG); ++ if (preserve) { ++ emm_switch.u64 = cvmx_read_csr(slot->host->base + ++ OCT_MIO_EMM_SWITCH); ++ wdog = cvmx_read_csr(slot->host->base + OCT_MIO_EMM_WDOG); ++ } ++ ++ /* Restore switch settings */ ++ if (preserve) { ++ emm_switch.s.switch_exe = 0; ++ emm_switch.s.switch_err0 = 0; ++ emm_switch.s.switch_err1 = 0; ++ emm_switch.s.switch_err2 = 0; ++ emm_switch.s.bus_id = 0; ++ cvmx_write_csr(slot->host->base + OCT_MIO_EMM_SWITCH, ++ emm_switch.u64); ++ emm_switch.s.bus_id = slot->bus_id; ++ cvmx_write_csr(slot->host->base + OCT_MIO_EMM_SWITCH, ++ emm_switch.u64); ++ ++ slot->cached_switch = emm_switch.u64; ++ ++ msleep(10); ++ cvmx_write_csr(slot->host->base + OCT_MIO_EMM_WDOG, wdog); ++ } else { ++ slot->cached_switch = 0; ++ } ++} ++ ++static void octeon_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct octeon_mmc_slot *slot; ++ struct octeon_mmc_host *host; ++ int bus_width; ++ int clock; ++ bool ddr_clock; ++ int hs_timing; ++ int power_class = 10; ++ int clk_period; ++ int timeout = 2000; ++ union cvmx_mio_emm_switch emm_switch; ++ union cvmx_mio_emm_rsp_sts emm_sts; ++ ++ slot = mmc_priv(mmc); ++ host = slot->host; ++ ++ /* Only a single user of the bootbus at a time. */ ++ octeon_mmc_acquire_bus(host); ++ ++ octeon_mmc_switch_to(slot); ++ ++ octeon_mmc_dbg("Calling set_ios: slot: clk = 0x%x, bus_width = %d\n", ++ slot->clock, slot->bus_width); ++ octeon_mmc_dbg("Calling set_ios: ios: clk = 0x%x, vdd = %u, bus_width = %u, power_mode = %u, timing = %u\n", ++ ios->clock, ios->vdd, ios->bus_width, ios->power_mode, ++ ios->timing); ++ octeon_mmc_dbg("Calling set_ios: mmc: caps = 0x%x, bus_width = %d\n", ++ mmc->caps, mmc->ios.bus_width); ++ ++ /* ++ * Reset the chip on each power off ++ */ ++ if (ios->power_mode == MMC_POWER_OFF) { ++ octeon_mmc_reset_bus(slot, 1); ++ if (slot->pwr_gpio >= 0) ++ gpio_set_value_cansleep(slot->pwr_gpio, ++ slot->pwr_gpio_low); ++ } else { ++ if (slot->pwr_gpio >= 0) ++ gpio_set_value_cansleep(slot->pwr_gpio, ++ !slot->pwr_gpio_low); ++ } ++ ++ switch (ios->bus_width) { ++ case MMC_BUS_WIDTH_8: ++ bus_width = 2; ++ break; ++ case MMC_BUS_WIDTH_4: ++ bus_width = 1; ++ break; ++ case MMC_BUS_WIDTH_1: ++ bus_width = 0; ++ break; ++ default: ++ octeon_mmc_dbg("unknown bus width %d\n", ios->bus_width); ++ bus_width = 0; ++ break; ++ } ++ ++ hs_timing = (ios->timing == MMC_TIMING_MMC_HS); ++ ddr_clock = (bus_width && ios->timing >= MMC_TIMING_UHS_DDR50); ++ ++ if (ddr_clock) ++ bus_width |= 4; ++ ++ if (ios->clock) { ++ slot->clock = ios->clock; ++ slot->bus_width = bus_width; ++ ++ clock = slot->clock; ++ ++ if (clock > 52000000) ++ clock = 52000000; ++ ++ clk_period = (octeon_get_io_clock_rate() + clock - 1) / ++ (2 * clock); ++ ++ /* until clock-renengotiate-on-CRC is in */ ++ if (ddr_clock && ddr > 1) ++ clk_period *= 2; ++ ++ emm_switch.u64 = 0; ++ emm_switch.s.hs_timing = hs_timing; ++ emm_switch.s.bus_width = bus_width; ++ emm_switch.s.power_class = power_class; ++ emm_switch.s.clk_hi = clk_period; ++ emm_switch.s.clk_lo = clk_period; ++ ++ if (!octeon_mmc_switch_val_changed(slot, emm_switch.u64)) { ++ octeon_mmc_dbg("No change from 0x%llx mio_emm_switch, returning.\n", ++ emm_switch.u64); ++ goto out; ++ } ++ ++ octeon_mmc_dbg("Writing 0x%llx to mio_emm_wdog\n", ++ ((u64)clock * 850ull) / 1000ull); ++ cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, ++ ((u64)clock * 850ull) / 1000ull); ++ octeon_mmc_dbg("Writing 0x%llx to mio_emm_switch\n", ++ emm_switch.u64); ++ ++ cvmx_write_csr(host->base + OCT_MIO_EMM_SWITCH, emm_switch.u64); ++ emm_switch.s.bus_id = slot->bus_id; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_SWITCH, emm_switch.u64); ++ slot->cached_switch = emm_switch.u64; ++ ++ do { ++ emm_sts.u64 = ++ cvmx_read_csr(host->base + OCT_MIO_EMM_RSP_STS); ++ if (!emm_sts.s.switch_val) ++ break; ++ udelay(100); ++ } while (timeout-- > 0); ++ ++ if (timeout <= 0) { ++ octeon_mmc_dbg("switch command timed out, status=0x%llx\n", ++ emm_sts.u64); ++ goto out; ++ } ++ } ++out: ++ octeon_mmc_release_bus(host); ++} ++ ++static int octeon_mmc_get_ro(struct mmc_host *mmc) ++{ ++ struct octeon_mmc_slot *slot = mmc_priv(mmc); ++ ++ if (slot->ro_gpio >= 0) { ++ int pin = gpio_get_value_cansleep(slot->ro_gpio); ++ ++ if (pin < 0) ++ return pin; ++ if (slot->ro_gpio_low) ++ pin = !pin; ++ return pin; ++ } else { ++ return -ENOSYS; ++ } ++} ++ ++static int octeon_mmc_get_cd(struct mmc_host *mmc) ++{ ++ struct octeon_mmc_slot *slot = mmc_priv(mmc); ++ ++ if (slot->cd_gpio >= 0) { ++ int pin = gpio_get_value_cansleep(slot->cd_gpio); ++ ++ if (pin < 0) ++ return pin; ++ if (slot->cd_gpio_low) ++ pin = !pin; ++ return pin; ++ } else { ++ return -ENOSYS; ++ } ++} ++ ++static const struct mmc_host_ops octeon_mmc_ops = { ++ .request = octeon_mmc_request, ++ .set_ios = octeon_mmc_set_ios, ++ .get_ro = octeon_mmc_get_ro, ++ .get_cd = octeon_mmc_get_cd, ++}; ++ ++static void octeon_mmc_set_clock(struct octeon_mmc_slot *slot, ++ unsigned int clock) ++{ ++ struct mmc_host *mmc = slot->mmc; ++ ++ clock = min(clock, mmc->f_max); ++ clock = max(clock, mmc->f_min); ++ slot->clock = clock; ++} ++ ++static int octeon_mmc_initlowlevel(struct octeon_mmc_slot *slot, ++ int bus_width) ++{ ++ union cvmx_mio_emm_switch emm_switch; ++ struct octeon_mmc_host *host = slot->host; ++ ++ host->emm_cfg |= 1ull << slot->bus_id; ++ cvmx_write_csr(slot->host->base + OCT_MIO_EMM_CFG, host->emm_cfg); ++ octeon_mmc_set_clock(slot, 400000); ++ ++ /* Program initial clock speed and power */ ++ emm_switch.u64 = 0; ++ emm_switch.s.power_class = 10; ++ emm_switch.s.clk_hi = (slot->sclock / slot->clock) / 2; ++ emm_switch.s.clk_lo = (slot->sclock / slot->clock) / 2; ++ ++ cvmx_write_csr(host->base + OCT_MIO_EMM_SWITCH, emm_switch.u64); ++ emm_switch.s.bus_id = slot->bus_id; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_SWITCH, emm_switch.u64); ++ slot->cached_switch = emm_switch.u64; ++ ++ cvmx_write_csr(host->base + OCT_MIO_EMM_WDOG, ++ ((u64)slot->clock * 850ull) / 1000ull); ++ cvmx_write_csr(host->base + OCT_MIO_EMM_STS_MASK, 0xe4f90080ull); ++ cvmx_write_csr(host->base + OCT_MIO_EMM_RCA, 1); ++ return 0; ++} ++ ++static int __init octeon_init_slot(struct octeon_mmc_host *host, int id, ++ int bus_width, int max_freq, ++ int ro_gpio, int cd_gpio, int pwr_gpio, ++ bool ro_low, bool cd_low, bool power_low, ++ u32 cmd_skew, u32 dat_skew) ++{ ++ struct mmc_host *mmc; ++ struct octeon_mmc_slot *slot; ++ u64 clock_period; ++ int ret; ++ ++ /* ++ * Allocate MMC structue ++ */ ++ mmc = mmc_alloc_host(sizeof(struct octeon_mmc_slot), &host->pdev->dev); ++ if (!mmc) { ++ dev_err(&host->pdev->dev, "alloc host failed\n"); ++ return -ENOMEM; ++ } ++ ++ slot = mmc_priv(mmc); ++ slot->mmc = mmc; ++ slot->host = host; ++ slot->ro_gpio = ro_gpio; ++ slot->cd_gpio = cd_gpio; ++ slot->pwr_gpio = pwr_gpio; ++ slot->ro_gpio_low = ro_low; ++ slot->cd_gpio_low = cd_low; ++ slot->pwr_gpio_low = power_low; ++ ++ if (slot->ro_gpio >= 0) { ++ ret = gpio_request(slot->ro_gpio, "mmc_ro"); ++ if (ret) { ++ dev_err(&host->pdev->dev, ++ "Could not request mmc_ro GPIO %d\n", ++ slot->ro_gpio); ++ return ret; ++ } ++ gpio_direction_input(slot->ro_gpio); ++ } ++ if (slot->cd_gpio >= 0) { ++ ret = gpio_request(slot->cd_gpio, "mmc_card_detect"); ++ if (ret) { ++ if (slot->ro_gpio >= 0) ++ gpio_free(slot->ro_gpio); ++ dev_err(&host->pdev->dev, "Could not request mmc_card_detect GPIO %d\n", ++ slot->cd_gpio); ++ return ret; ++ } ++ gpio_direction_input(slot->cd_gpio); ++ } ++ if (slot->pwr_gpio >= 0) { ++ ret = gpio_request(slot->pwr_gpio, "mmc_power"); ++ if (ret) { ++ dev_err(&host->pdev->dev, ++ "Could not request mmc_power GPIO %d\n", ++ slot->pwr_gpio); ++ if (slot->ro_gpio >= 0) ++ gpio_free(slot->ro_gpio); ++ if (slot->cd_gpio) ++ gpio_free(slot->cd_gpio); ++ return ret; ++ } ++ octeon_mmc_dbg("%s: Shutting off power to slot %d via gpio %d\n", ++ DRV_NAME, slot->bus_id, slot->pwr_gpio); ++ gpio_direction_output(slot->pwr_gpio, ++ slot->pwr_gpio_low); ++ } ++ /* ++ * Set up host parameters. ++ */ ++ mmc->ops = &octeon_mmc_ops; ++ mmc->f_min = 400000; ++ mmc->f_max = max_freq; ++ mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | ++ MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | ++ MMC_CAP_ERASE; ++ mmc->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | ++ MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | ++ MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36; ++ ++ /* post-sdk23 caps */ ++ mmc->caps |= ++ ((mmc->f_max >= 12000000) * MMC_CAP_UHS_SDR12) | ++ ((mmc->f_max >= 25000000) * MMC_CAP_UHS_SDR25) | ++ ((mmc->f_max >= 50000000) * MMC_CAP_UHS_SDR50) | ++ MMC_CAP_CMD23; ++ ++ if (host->global_pwr_gpio >= 0) ++ mmc->caps |= MMC_CAP_POWER_OFF_CARD; ++ ++ /* "1.8v" capability is actually 1.8-or-3.3v */ ++ if (ddr) ++ mmc->caps |= MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR; ++ ++ mmc->max_segs = 64; ++ mmc->max_seg_size = host->linear_buf_size; ++ mmc->max_req_size = host->linear_buf_size; ++ mmc->max_blk_size = 512; ++ mmc->max_blk_count = mmc->max_req_size / 512; ++ ++ slot->clock = mmc->f_min; ++ slot->sclock = octeon_get_io_clock_rate(); ++ ++ clock_period = 1000000000000ull / slot->sclock; /* period in pS */ ++ slot->cmd_cnt = (cmd_skew + clock_period / 2) / clock_period; ++ slot->dat_cnt = (dat_skew + clock_period / 2) / clock_period; ++ ++ slot->bus_width = bus_width; ++ slot->bus_id = id; ++ slot->cached_rca = 1; ++ ++ /* Only a single user of the bootbus at a time. */ ++ octeon_mmc_acquire_bus(host); ++ host->slot[id] = slot; ++ ++ octeon_mmc_switch_to(slot); ++ /* Initialize MMC Block. */ ++ octeon_mmc_initlowlevel(slot, bus_width); ++ ++ octeon_mmc_release_bus(host); ++ ++ ret = mmc_add_host(mmc); ++ octeon_mmc_dbg("mmc_add_host returned %d\n", ret); ++ ++ return 0; ++} ++ ++static int octeon_mmc_probe(struct platform_device *pdev) ++{ ++ union cvmx_mio_emm_cfg emm_cfg; ++ struct octeon_mmc_host *host; ++ struct resource *res; ++ void __iomem *base; ++ int mmc_irq[9]; ++ int i; ++ int ret = 0; ++ struct device_node *node = pdev->dev.of_node; ++ bool cn78xx_style; ++ u64 t; ++ enum of_gpio_flags f; ++ ++ host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); ++ if (!host) ++ return -ENOMEM; ++ ++ spin_lock_init(&host->irq_handler_lock); ++ sema_init(&host->mmc_serializer, 1); ++ ++ cn78xx_style = of_device_is_compatible(node, "cavium,octeon-7890-mmc"); ++ if (cn78xx_style) { ++ host->need_bootbus_lock = false; ++ host->big_dma_addr = true; ++ host->need_irq_handler_lock = true; ++ /* ++ * First seven are the EMM_INT bits 0..6, then two for ++ * the EMM_DMA_INT bits ++ */ ++ for (i = 0; i < 9; i++) { ++ mmc_irq[i] = platform_get_irq(pdev, i); ++ if (mmc_irq[i] < 0) ++ return mmc_irq[i]; ++ } ++ } else { ++ host->need_bootbus_lock = true; ++ host->big_dma_addr = false; ++ host->need_irq_handler_lock = false; ++ /* First one is EMM second NDF_DMA */ ++ for (i = 0; i < 2; i++) { ++ mmc_irq[i] = platform_get_irq(pdev, i); ++ if (mmc_irq[i] < 0) ++ return mmc_irq[i]; ++ } ++ } ++ host->last_slot = -1; ++ ++ if (bb_size < 512 || bb_size >= (1 << 24)) ++ bb_size = 1 << 16; ++ host->linear_buf_size = bb_size; ++ host->linear_buf = devm_kzalloc(&pdev->dev, host->linear_buf_size, ++ GFP_KERNEL); ++ ++ if (!host->linear_buf) { ++ dev_err(&pdev->dev, "devm_kzalloc failed\n"); ++ return -ENOMEM; ++ } ++ ++ host->pdev = pdev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "Platform resource[0] is missing\n"); ++ return -ENXIO; ++ } ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ host->base = (u64)base; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!res) { ++ dev_err(&pdev->dev, "Platform resource[1] is missing\n"); ++ ret = -EINVAL; ++ goto err; ++ } ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) { ++ ret = PTR_ERR(base); ++ goto err; ++ } ++ host->ndf_base = (u64)base; ++ /* ++ * Clear out any pending interrupts that may be left over from ++ * bootloader. ++ */ ++ t = cvmx_read_csr(host->base + OCT_MIO_EMM_INT); ++ cvmx_write_csr(host->base + OCT_MIO_EMM_INT, t); ++ if (cn78xx_style) { ++ /* Only CMD_DONE, DMA_DONE, CMD_ERR, DMA_ERR */ ++ for (i = 1; i <= 4; i++) { ++ ret = devm_request_irq(&pdev->dev, mmc_irq[i], ++ octeon_mmc_interrupt, ++ 0, DRV_NAME, host); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Error: devm_request_irq %d\n", ++ mmc_irq[i]); ++ goto err; ++ } ++ } ++ } else { ++ ret = devm_request_irq(&pdev->dev, mmc_irq[0], ++ octeon_mmc_interrupt, 0, DRV_NAME, host); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Error: devm_request_irq %d\n", ++ mmc_irq[0]); ++ goto err; ++ } ++ } ++ ++ ret = of_get_named_gpio_flags(node, "power-gpios", 0, &f); ++ if (ret == -EPROBE_DEFER) ++ goto err; ++ ++ host->global_pwr_gpio = ret; ++ host->global_pwr_gpio_low = ++ (host->global_pwr_gpio >= 0 && f == OF_GPIO_ACTIVE_LOW); ++ ++ if (host->global_pwr_gpio >= 0) { ++ ret = gpio_request(host->global_pwr_gpio, "mmc global power"); ++ if (ret) { ++ dev_err(&pdev->dev, ++ "Could not request mmc global power gpio %d\n", ++ host->global_pwr_gpio); ++ goto err; ++ } ++ dev_dbg(&pdev->dev, "Global power on\n"); ++ gpio_direction_output(host->global_pwr_gpio, ++ !host->global_pwr_gpio_low); ++ } ++ ++ platform_set_drvdata(pdev, host); ++ ++ for_each_child_of_node(pdev->dev.of_node, node) { ++ ++ int r; ++ u32 slot; ++ int ro_gpio, cd_gpio, pwr_gpio; ++ bool ro_low, cd_low, pwr_low; ++ u32 bus_width, max_freq, cmd_skew, dat_skew; ++ ++ if (!of_device_is_compatible(node, ++ "cavium,octeon-6130-mmc-slot")) { ++ pr_warn("Sub node isn't slot: %s\n", ++ of_node_full_name(node)); ++ continue; ++ } ++ ++ if (of_property_read_u32(node, "reg", &slot) != 0) { ++ pr_warn("Missing or invalid reg property on %s\n", ++ of_node_full_name(node)); ++ continue; ++ } ++ ++ r = of_property_read_u32(node, "cavium,bus-max-width", ++ &bus_width); ++ if (r) { ++ bus_width = 8; ++ pr_info("Bus width not found for slot %d, defaulting to %d\n", ++ slot, bus_width); ++ } else { ++ switch (bus_width) { ++ case 1: ++ case 4: ++ case 8: ++ break; ++ default: ++ pr_warn("Invalid bus width property for slot %d\n", ++ slot); ++ continue; ++ } ++ } ++ ++ r = of_property_read_u32(node, "cavium,cmd-clk-skew", ++ &cmd_skew); ++ if (r) ++ cmd_skew = 0; ++ ++ r = of_property_read_u32(node, "cavium,dat-clk-skew", ++ &dat_skew); ++ if (r) ++ dat_skew = 0; ++ ++ r = of_property_read_u32(node, "spi-max-frequency", &max_freq); ++ if (r) { ++ max_freq = 52000000; ++ pr_info("No spi-max-frequency for slot %d, defaulting to %d\n", ++ slot, max_freq); ++ } ++ ++ ro_gpio = of_get_named_gpio_flags(node, "wp-gpios", 0, &f); ++ ro_low = (ro_gpio >= 0 && f == OF_GPIO_ACTIVE_LOW); ++ cd_gpio = of_get_named_gpio_flags(node, "cd-gpios", 0, &f); ++ cd_low = (cd_gpio >= 0 && f == OF_GPIO_ACTIVE_LOW); ++ pwr_gpio = of_get_named_gpio_flags(node, "power-gpios", 0, &f); ++ pwr_low = (pwr_gpio >= 0 && f == OF_GPIO_ACTIVE_LOW); ++ ++ ret = octeon_init_slot(host, slot, bus_width, max_freq, ++ ro_gpio, cd_gpio, pwr_gpio, ++ ro_low, cd_low, pwr_low, ++ cmd_skew, dat_skew); ++ octeon_mmc_dbg("init slot %d, ret = %d\n", slot, ret); ++ if (ret) ++ goto err; ++ } ++ ++ return ret; ++ ++err: ++ dev_err(&pdev->dev, "Probe failed: %d\n", ret); ++ ++ /* Disable MMC controller */ ++ emm_cfg.s.bus_ena = 0; ++ cvmx_write_csr(host->base + OCT_MIO_EMM_CFG, emm_cfg.u64); ++ ++ if (host->global_pwr_gpio >= 0) { ++ dev_dbg(&pdev->dev, "Global power off\n"); ++ gpio_set_value_cansleep(host->global_pwr_gpio, ++ host->global_pwr_gpio_low); ++ gpio_free(host->global_pwr_gpio); ++ } ++ ++ return ret; ++} ++ ++static int octeon_mmc_remove(struct platform_device *pdev) ++{ ++ union cvmx_mio_ndf_dma_cfg ndf_dma_cfg; ++ struct octeon_mmc_host *host = platform_get_drvdata(pdev); ++ struct octeon_mmc_slot *slot; ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ if (host) { ++ int i; ++ ++ /* quench all users */ ++ for (i = 0; i < OCTEON_MAX_MMC; i++) { ++ slot = host->slot[i]; ++ if (slot) ++ mmc_remove_host(slot->mmc); ++ } ++ ++ /* Reset bus_id */ ++ ndf_dma_cfg.u64 = ++ cvmx_read_csr(host->ndf_base + OCT_MIO_NDF_DMA_CFG); ++ ndf_dma_cfg.s.en = 0; ++ cvmx_write_csr(host->ndf_base + OCT_MIO_NDF_DMA_CFG, ++ ndf_dma_cfg.u64); ++ ++ for (i = 0; i < OCTEON_MAX_MMC; i++) { ++ struct octeon_mmc_slot *slot; ++ ++ slot = host->slot[i]; ++ if (!slot) ++ continue; ++ /* Free the GPIOs */ ++ if (slot->ro_gpio >= 0) ++ gpio_free(slot->ro_gpio); ++ if (slot->cd_gpio >= 0) ++ gpio_free(slot->cd_gpio); ++ if (slot->pwr_gpio >= 0) { ++ gpio_set_value_cansleep(slot->pwr_gpio, ++ slot->pwr_gpio_low); ++ gpio_free(slot->pwr_gpio); ++ } ++ } ++ ++ if (host->global_pwr_gpio >= 0) { ++ dev_dbg(&pdev->dev, "Global power off\n"); ++ gpio_set_value_cansleep(host->global_pwr_gpio, ++ host->global_pwr_gpio_low); ++ gpio_free(host->global_pwr_gpio); ++ } ++ ++ for (i = 0; i < OCTEON_MAX_MMC; i++) { ++ slot = host->slot[i]; ++ if (slot) ++ mmc_free_host(slot->mmc); ++ } ++ ++ } ++ return 0; ++} ++ ++static struct of_device_id octeon_mmc_match[] = { ++ { ++ .compatible = "cavium,octeon-6130-mmc", ++ }, ++ { ++ .compatible = "cavium,octeon-7890-mmc", ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, octeon_mmc_match); ++ ++static struct platform_driver octeon_mmc_driver = { ++ .probe = octeon_mmc_probe, ++ .remove = octeon_mmc_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = octeon_mmc_match, ++ }, ++}; ++ ++static int __init octeon_mmc_init(void) ++{ ++ int ret; ++ ++ octeon_mmc_dbg("calling octeon_mmc_init\n"); ++ ++ ret = platform_driver_register(&octeon_mmc_driver); ++ octeon_mmc_dbg("driver probe returned %d\n", ret); ++ ++ if (ret) ++ pr_err("%s: Failed to register driver\n", DRV_NAME); ++ ++ return ret; ++} ++ ++static void __exit octeon_mmc_cleanup(void) ++{ ++ /* Unregister MMC driver */ ++ platform_driver_unregister(&octeon_mmc_driver); ++} ++ ++module_init(octeon_mmc_init); ++module_exit(octeon_mmc_cleanup); ++ ++MODULE_AUTHOR("Cavium Inc. "); ++MODULE_DESCRIPTION("low-level driver for Cavium OCTEON MMC/SSD card"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/octeon/patches-3.18/160-cmdline-hack.patch b/target/linux/octeon/patches-3.18/160-cmdline-hack.patch new file mode 100644 index 0000000..8ef73a1 --- /dev/null +++ b/target/linux/octeon/patches-3.18/160-cmdline-hack.patch @@ -0,0 +1,47 @@ +--- a/arch/mips/cavium-octeon/setup.c ++++ b/arch/mips/cavium-octeon/setup.c +@@ -609,6 +609,35 @@ void octeon_user_io_init(void) + write_c0_derraddr1(0); + } + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++extern char __image_cmdline[]; ++ ++static int __init octeon_use_image_cmdline(void) ++{ ++ char *p = __image_cmdline; ++ int replace = 0; ++ ++ if (*p == '-') { ++ replace = 1; ++ p++; ++ } ++ ++ if (*p == '\0') ++ return 0; ++ ++ if (replace) { ++ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } else { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } ++ ++ return 1; ++} ++#else ++static inline int octeon_use_image_cmdline(void) { return 0; } ++#endif ++ + /** + * Early entry point for arch setup + */ +@@ -798,6 +827,8 @@ void __init prom_init(void) + } + } + ++ octeon_use_image_cmdline(); ++ + if (strstr(arcs_cmdline, "console=") == NULL) { + #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL + strcat(arcs_cmdline, " console=ttyS0,115200"); diff --git a/target/linux/octeon/profiles/000-Generic.mk b/target/linux/octeon/profiles/000-Generic.mk new file mode 100644 index 0000000..cf9a013 --- /dev/null +++ b/target/linux/octeon/profiles/000-Generic.mk @@ -0,0 +1,17 @@ +# +# Copyright (C) 2013 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/generic + NAME:=Generic Octeon board + PACKAGES:= +endef + +define Profile/generic/Description + Base packages for Octeon boards. +endef +$(eval $(call Profile,generic)) + diff --git a/target/linux/omap/Makefile b/target/linux/omap/Makefile new file mode 100644 index 0000000..20f7517 --- /dev/null +++ b/target/linux/omap/Makefile @@ -0,0 +1,30 @@ +# +# Copyright (C) 2012-2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=omap +BOARDNAME:=TI OMAP3/4/AM33xx +FEATURES:=usb usbgadget ext4 targz fpu audio display nand ubifs +CPU_TYPE:=cortex-a9 +CPU_SUBTYPE:=vfpv3 + +KERNEL_PATCHVER:=3.18 + +MAINTAINER:=Imre Kaloz + +KERNELNAME:=zImage dtbs + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += uboot-omap-am335x_evm uboot-omap-omap3_beagle uboot-omap-omap3_overo uboot-omap-omap4_panda + +define Target/Description + TI OMAP boards +endef + +$(eval $(call BuildTarget)) diff --git a/target/linux/omap/base-files/etc/inittab b/target/linux/omap/base-files/etc/inittab new file mode 100644 index 0000000..502c6f8 --- /dev/null +++ b/target/linux/omap/base-files/etc/inittab @@ -0,0 +1,5 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttyO0::askfirst:/bin/ash --login +ttyO2::askfirst:/bin/ash --login +tty1::askfirst:/bin/ash --login diff --git a/target/linux/omap/config-3.18 b/target/linux/omap/config-3.18 new file mode 100644 index 0000000..d5003c2 --- /dev/null +++ b/target/linux/omap/config-3.18 @@ -0,0 +1,582 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_BANDGAP=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_ARCH_OMAP2PLUS_TYPICAL=y +CONFIG_ARCH_OMAP3=y +CONFIG_ARCH_OMAP4=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_OMAP2PLUS_CPUFREQ=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_AT803X_PHY=y +# CONFIG_ATH_CARDS is not set +CONFIG_AUTO_ZRELADDR=y +CONFIG_AVERAGE=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_TPS65217 is not set +CONFIG_BCH=y +CONFIG_BOUNCE=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_CFG80211=m +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_WEXT=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +# CONFIG_CLK_TWL6040 is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyO0,115200n8" +CONFIG_COMMON_CLK=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_CPUFREQ_DT is not set +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=m +CONFIG_CRYPTO_SEQIV=m +# CONFIG_CRYPTO_SHA1_ARM_NEON is not set +# CONFIG_CRYPTO_SHA512_ARM_NEON is not set +CONFIG_CRYPTO_WORKQUEUE=m +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DDR=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DISPLAY_PANEL_DPI=y +CONFIG_DISPLAY_PANEL_DSI_CM=y +# CONFIG_DISPLAY_PANEL_NEC_NL8048HL11 is not set +CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=y +# CONFIG_DISPLAY_PANEL_SONY_ACX565AKM is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OMAP=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +# CONFIG_DW_DMAC_CORE is not set +CONFIG_EEPROM_AT24=y +# CONFIG_EMAC_ROCKCHIP is not set +CONFIG_EXT4_FS=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DA8XX=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_OMAP2=y +CONFIG_FB_OMAP2_DEBUG_SUPPORT=y +CONFIG_FB_OMAP2_NUM_FBS=3 +CONFIG_FIRMWARE_EDID=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FORCE_MAX_ZONEORDER=12 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAME_POINTER=y +CONFIG_FREEZER=y +CONFIG_FS_MBCACHE=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_OMAP=y +# CONFIG_GPIO_SYSCON is not set +CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_TWL4030=y +# CONFIG_GPIO_TWL6040 is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HDMI=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_OMAP=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_OMAP=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_TWL4030_PWRBUTTON=y +# CONFIG_INPUT_TWL4030_VIBRA is not set +# CONFIG_INPUT_TWL6040_VIBRA is not set +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_KEYBOARD_TWL4030=y +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_SYSCON is not set +CONFIG_LIBFDT=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAC80211=m +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +# CONFIG_MACH_CM_T35 is not set +# CONFIG_MACH_CM_T3517 is not set +# CONFIG_MACH_CRANEBOARD is not set +# CONFIG_MACH_DEVKIT8000 is not set +# CONFIG_MACH_NOKIA_RX51 is not set +# CONFIG_MACH_OMAP3517EVM is not set +# CONFIG_MACH_OMAP3530_LV_SOM is not set +CONFIG_MACH_OMAP3_BEAGLE=y +# CONFIG_MACH_OMAP3_PANDORA is not set +# CONFIG_MACH_OMAP3_TORPEDO is not set +# CONFIG_MACH_OMAP_3430SDP is not set +CONFIG_MACH_OMAP_GENERIC=y +# CONFIG_MACH_OMAP_LDP is not set +CONFIG_MACH_OVERO=y +# CONFIG_MACH_SBC3530 is not set +# CONFIG_MACH_TOUCHBOOK is not set +CONFIG_MAILBOX=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MEMORY=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_AM335X_TSCADC=y +CONFIG_MFD_TPS65217=y +CONFIG_MFD_TPS65910=y +CONFIG_MFD_TWL4030_AUDIO=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP_HS=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_BCH=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_BCH=y +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_NAND_OMAP_BCH=y +CONFIG_MTD_NAND_OMAP_BCH_BUILD=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_MWIFIEX is not set +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NET_VENDOR_I825XX is not set +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_TOUCHSCREEN=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OMAP2PLUS_MBOX=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_DSS_DPI=y +CONFIG_OMAP2_DSS_DSI=y +CONFIG_OMAP2_DSS_HDMI_COMMON=y +CONFIG_OMAP2_DSS_INIT=y +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 +CONFIG_OMAP2_DSS_SDI=y +CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y +# CONFIG_OMAP2_DSS_VENC is not set +CONFIG_OMAP2_VRFB=y +# CONFIG_OMAP3_EMU is not set +# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set +# CONFIG_OMAP3_SDRC_AC_TIMING is not set +CONFIG_OMAP4_DSS_HDMI=y +CONFIG_OMAP4_DSS_HDMI_AUDIO=y +CONFIG_OMAP5_DSS_HDMI=y +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_CONTROL_PHY=y +CONFIG_OMAP_DM_TIMER=y +CONFIG_OMAP_INTERCONNECT=y +CONFIG_OMAP_IRQCHIP=y +CONFIG_OMAP_MBOX_KFIFO_SIZE=256 +CONFIG_OMAP_MUX=y +# CONFIG_OMAP_MUX_DEBUG is not set +CONFIG_OMAP_MUX_WARNINGS=y +CONFIG_OMAP_OCP2SCP=y +CONFIG_OMAP_PACKAGE_CBB=y +CONFIG_OMAP_PM_NOOP=y +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_WATCHDOG=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PCI is not set +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_OPP=y +CONFIG_PM_RUNTIME=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_AVS=y +# CONFIG_POWER_AVS_OMAP is not set +CONFIG_PPS=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PTP_1588_CLOCK=y +CONFIG_PWM=y +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_SYSFS=y +CONFIG_PWM_TIECAP=y +CONFIG_PWM_TIEHRPWM=y +CONFIG_PWM_TIPWMSS=y +# CONFIG_PWM_TWL is not set +# CONFIG_PWM_TWL_LED is not set +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_ANATOP is not set +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_PBIAS is not set +# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_TPS65023=y +CONFIG_REGULATOR_TPS6507X=y +CONFIG_REGULATOR_TPS65217=y +CONFIG_REGULATOR_TPS65910=y +CONFIG_REGULATOR_TWL4030=y +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +# CONFIG_RSI_91X is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_OMAP=y +CONFIG_RTC_DRV_TPS65910=y +CONFIG_RTC_DRV_TWL4030=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SENSORS_LM75=y +# CONFIG_SENSORS_PWM_FAN is not set +CONFIG_SENSORS_TWL4030_MADC=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_OMAP=y +CONFIG_SERIAL_OMAP_CONSOLE=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SMSC911X=y +# CONFIG_SMSC911X_ARCH_HOOKS is not set +CONFIG_SND=y +CONFIG_SND_ARM=y +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_DAVINCI_SOC_MCASP=y +CONFIG_SND_DMAENGINE_PCM=y +# CONFIG_SND_EDMA_SOC is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_JACK=y +CONFIG_SND_OMAP_SOC=y +CONFIG_SND_OMAP_SOC_DMIC=y +CONFIG_SND_OMAP_SOC_HDMI=y +CONFIG_SND_OMAP_SOC_MCBSP=y +CONFIG_SND_OMAP_SOC_MCPDM=y +CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=y +CONFIG_SND_OMAP_SOC_OMAP_HDMI=y +CONFIG_SND_OMAP_SOC_OMAP_TWL4030=y +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +CONFIG_SND_PCM=y +CONFIG_SND_PCM_OSS=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_DMIC=y +# CONFIG_SND_SOC_FSL_SSI is not set +CONFIG_SND_SOC_HDMI_CODEC=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_IMX_AUDMUX is not set +CONFIG_SND_SOC_TLV320AIC3X=y +CONFIG_SND_SOC_TWL4030=y +CONFIG_SND_SOC_TWL6040=y +CONFIG_SND_TIMER=y +CONFIG_SOC_AM33XX=y +CONFIG_SOC_AM43XX=y +CONFIG_SOC_BUS=y +CONFIG_SOC_HAS_OMAP2_SDRC=y +# CONFIG_SOC_OMAP3430 is not set +# CONFIG_SOC_TI81XX is not set +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_OMAP24XX is not set +CONFIG_STOP_MACHINE=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TI_CPPI41=y +CONFIG_TI_CPSW=y +CONFIG_TI_CPSW_PHY_SEL=y +CONFIG_TI_CPTS=y +CONFIG_TI_DAVINCI_CPDMA=y +# CONFIG_TI_DAVINCI_EMAC is not set +CONFIG_TI_DAVINCI_MDIO=y +CONFIG_TI_EDMA=y +CONFIG_TI_EMIF=y +# CONFIG_TI_PIPE3 is not set +CONFIG_TI_PRIV_EDMA=y +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y +CONFIG_TREE_RCU=y +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_MADC=y +CONFIG_TWL4030_POWER=y +CONFIG_TWL4030_WATCHDOG=y +CONFIG_TWL6040_CORE=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_XEN is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/omap/config-4.1 b/target/linux/omap/config-4.1 new file mode 100644 index 0000000..14f13f0 --- /dev/null +++ b/target/linux/omap/config-4.1 @@ -0,0 +1,540 @@ +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_BANDGAP=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_ARCH_OMAP2PLUS_TYPICAL=y +CONFIG_ARCH_OMAP3=y +CONFIG_ARCH_OMAP4=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +# CONFIG_ARM_CPUIDLE is not set +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_OMAP2PLUS_CPUFREQ=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_AT803X_PHY=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_AVERAGE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_TPS65217 is not set +CONFIG_BCH=y +CONFIG_BOUNCE=y +CONFIG_CACHE_L2X0=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_OF=y +# CONFIG_CLK_TWL6040 is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="console=ttyO0,115200n8" +CONFIG_COMMON_CLK=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_CPUFREQ_DT is not set +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DDR=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DISPLAY_ENCODER_OPA362 is not set +CONFIG_DISPLAY_PANEL_DPI=y +CONFIG_DISPLAY_PANEL_DSI_CM=y +# CONFIG_DISPLAY_PANEL_NEC_NL8048HL11 is not set +CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=y +# CONFIG_DISPLAY_PANEL_SONY_ACX565AKM is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OMAP=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_EEPROM_AT24=y +CONFIG_EXT4_FS=y +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y +CONFIG_FB_CMDLINE=y +CONFIG_FB_DA8XX=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_OMAP2=y +CONFIG_FB_OMAP2_DEBUG_SUPPORT=y +CONFIG_FB_OMAP2_NUM_FBS=3 +CONFIG_FIRMWARE_EDID=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x16=y +CONFIG_FONT_8x8=y +CONFIG_FONT_SUPPORT=y +CONFIG_FORCE_MAX_ZONEORDER=12 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAME_POINTER=y +CONFIG_FREEZER=y +CONFIG_FS_MBCACHE=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_OMAP=y +CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_TWL4030=y +# CONFIG_GPIO_TWL6040 is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HDMI=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_OMAP=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_OMAP=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_INPUT=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_TWL4030_PWRBUTTON=y +# CONFIG_INPUT_TWL4030_VIBRA is not set +# CONFIG_INPUT_TWL6040_VIBRA is not set +CONFIG_IOMMU_HELPER=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KEYBOARD_TWL4030=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_PLATFORM is not set +CONFIG_LEDS_GPIO=y +CONFIG_LIBFDT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_MACH_CM_T35 is not set +# CONFIG_MACH_NOKIA_RX51 is not set +# CONFIG_MACH_OMAP3517EVM is not set +# CONFIG_MACH_OMAP3530_LV_SOM is not set +CONFIG_MACH_OMAP3_BEAGLE=y +# CONFIG_MACH_OMAP3_PANDORA is not set +# CONFIG_MACH_OMAP3_TORPEDO is not set +CONFIG_MACH_OMAP_GENERIC=y +# CONFIG_MACH_OMAP_LDP is not set +CONFIG_MACH_OVERO=y +CONFIG_MAILBOX=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MEMORY=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_AM335X_TSCADC=y +CONFIG_MFD_TPS65217=y +CONFIG_MFD_TPS65910=y +CONFIG_MFD_TWL4030_AUDIO=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP_HS=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_DATAFLASH_OTP is not set +# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_BCH=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_BCH=y +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_NAND_OMAP_BCH=y +CONFIG_MTD_NAND_OMAP_BCH_BUILD=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_OF is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_TOUCHSCREEN=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OMAP2PLUS_MBOX=y +CONFIG_OMAP2_DSS=y +CONFIG_OMAP2_DSS_DPI=y +CONFIG_OMAP2_DSS_DSI=y +CONFIG_OMAP2_DSS_HDMI_COMMON=y +CONFIG_OMAP2_DSS_INIT=y +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 +CONFIG_OMAP2_DSS_SDI=y +CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y +# CONFIG_OMAP2_DSS_VENC is not set +CONFIG_OMAP2_VRFB=y +# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set +# CONFIG_OMAP3_SDRC_AC_TIMING is not set +CONFIG_OMAP4_DSS_HDMI=y +CONFIG_OMAP5_DSS_HDMI=y +CONFIG_OMAP_32K_TIMER=y +CONFIG_OMAP_CONTROL_PHY=y +CONFIG_OMAP_DM_TIMER=y +CONFIG_OMAP_GPMC=y +CONFIG_OMAP_INTERCONNECT=y +CONFIG_OMAP_IRQCHIP=y +CONFIG_OMAP_MBOX_KFIFO_SIZE=256 +CONFIG_OMAP_MUX=y +# CONFIG_OMAP_MUX_DEBUG is not set +CONFIG_OMAP_MUX_WARNINGS=y +CONFIG_OMAP_OCP2SCP=y +CONFIG_OMAP_PACKAGE_CBB=y +CONFIG_OMAP_PM_NOOP=y +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_WATCHDOG=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PCI is not set +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_PHY_DM816X_USB is not set +CONFIG_PINCTRL=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_AVS=y +# CONFIG_POWER_AVS_OMAP is not set +CONFIG_PPS=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +CONFIG_PWM_TIECAP=y +CONFIG_PWM_TIEHRPWM=y +CONFIG_PWM_TIPWMSS=y +# CONFIG_PWM_TWL is not set +# CONFIG_PWM_TWL_LED is not set +CONFIG_RCU_STALL_COMMON=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_PBIAS is not set +CONFIG_REGULATOR_TPS65023=y +CONFIG_REGULATOR_TPS6507X=y +CONFIG_REGULATOR_TPS65217=y +CONFIG_REGULATOR_TPS65910=y +CONFIG_REGULATOR_TWL4030=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_OMAP=y +CONFIG_RTC_DRV_TPS65910=y +CONFIG_RTC_DRV_TWL4030=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_HRTICK=y +# CONFIG_SCSI_DMA is not set +CONFIG_SENSORS_LM75=y +CONFIG_SENSORS_TWL4030_MADC=y +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_OMAP is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_OMAP=y +CONFIG_SERIAL_OMAP_CONSOLE=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SMSC911X=y +# CONFIG_SMSC911X_ARCH_HOOKS is not set +CONFIG_SND=y +CONFIG_SND_ARM=y +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_DAVINCI_SOC_MCASP=y +CONFIG_SND_DMAENGINE_PCM=y +# CONFIG_SND_EDMA_SOC is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_JACK=y +CONFIG_SND_OMAP_SOC=y +CONFIG_SND_OMAP_SOC_DMIC=y +# CONFIG_SND_OMAP_SOC_HDMI_AUDIO is not set +CONFIG_SND_OMAP_SOC_MCBSP=y +CONFIG_SND_OMAP_SOC_MCPDM=y +CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=y +CONFIG_SND_OMAP_SOC_OMAP_TWL4030=y +# CONFIG_SND_OMAP_SOC_RX51 is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +CONFIG_SND_PCM=y +CONFIG_SND_PCM_OSS=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_DMIC=y +# CONFIG_SND_SOC_FSL_SSI is not set +CONFIG_SND_SOC_HDMI_CODEC=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_RT5677_SPI is not set +CONFIG_SND_SOC_TLV320AIC3X=y +CONFIG_SND_SOC_TWL4030=y +CONFIG_SND_SOC_TWL6040=y +CONFIG_SND_TIMER=y +CONFIG_SOC_AM33XX=y +CONFIG_SOC_AM43XX=y +CONFIG_SOC_BUS=y +CONFIG_SOC_HAS_OMAP2_SDRC=y +# CONFIG_SOC_OMAP3430 is not set +# CONFIG_SOC_TI81XX is not set +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +# CONFIG_SPI_OMAP24XX is not set +CONFIG_SRCU=y +CONFIG_STOP_MACHINE=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TI_CPPI41=y +CONFIG_TI_CPSW=y +CONFIG_TI_CPSW_ALE=y +CONFIG_TI_CPSW_PHY_SEL=y +CONFIG_TI_CPTS=y +CONFIG_TI_DAVINCI_CPDMA=y +# CONFIG_TI_DAVINCI_EMAC is not set +CONFIG_TI_DAVINCI_MDIO=y +CONFIG_TI_EDMA=y +CONFIG_TI_EMIF=y +# CONFIG_TI_PIPE3 is not set +CONFIG_TI_PRIV_EDMA=y +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y +CONFIG_TREE_RCU=y +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_MADC=y +CONFIG_TWL4030_POWER=y +CONFIG_TWL4030_WATCHDOG=y +CONFIG_TWL6040_CORE=y +CONFIG_UID16=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/omap/image/Makefile b/target/linux/omap/image/Makefile new file mode 100644 index 0000000..3fa2848 --- /dev/null +++ b/target/linux/omap/image/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (C) 2012-2014 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +UBIFS_OPTS = -F -m 2048 -e 124KiB -c 4096 -U +UBI_OPTS = -m 2048 -p 128KiB -s 512 -O 2048 + +define Image/BuildKernel + $(CP) $(KDIR)/zImage $(BIN_DIR)/$(IMG_PREFIX)-zImage + ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) + $(CP) $(KDIR)/zImage-initramfs $(BIN_DIR)/$(IMG_PREFIX)-zImage-initramfs + endif + + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_KERNEL),) + $(INSTALL_DIR) $(TARGET_DIR)/boot + $(CP) $(BIN_DIR)/$(IMG_PREFIX)-zImage $(TARGET_DIR)/boot/zImage + endif + ifneq ($(CONFIG_TARGET_ROOTFS_INCLUDE_DTB),) + $(INSTALL_DIR) $(TARGET_DIR)/boot + $(CP) $(DTS_DIR)/am335x*.dtb $(TARGET_DIR)/boot/ + $(CP) $(DTS_DIR)/omap3*.dtb $(TARGET_DIR)/boot/ + $(CP) $(DTS_DIR)/omap4*.dtb $(TARGET_DIR)/boot/ + endif + -mkdir $(BIN_DIR)/dtbs + -$(CP) $(DTS_DIR)/am335x*.dtb $(BIN_DIR)/dtbs/ + -$(CP) $(DTS_DIR)/omap3*.dtb $(BIN_DIR)/dtbs/ + -$(CP) $(DTS_DIR)/omap4*.dtb $(BIN_DIR)/dtbs/ +endef + +define Image/Build + $(call Image/Build/$(1),$(1)) +endef + +define Image/Build/jffs2-64k + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=65536 conv=sync +endef + +define Image/Build/jffs2-128k + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=131072 conv=sync +endef + +define Image/Build/squashfs + $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) + dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1).img bs=131072 conv=sync +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/omap/image/ubinize.cfg b/target/linux/omap/image/ubinize.cfg new file mode 100644 index 0000000..49d55b9 --- /dev/null +++ b/target/linux/omap/image/ubinize.cfg @@ -0,0 +1,14 @@ +[rootfs] +# Volume mode (other option is static) +mode=ubi +# Source image +image=root.ubifs +# Volume ID in UBI image +vol_id=0 +# Allow for dynamic resize +vol_type=dynamic +# Volume name +vol_name=rootfs +# Autoresize volume at first mount +vol_flags=autoresize + diff --git a/target/linux/omap/patches-3.18/0334-video-da8xx-fb-adding-dt-support.patch b/target/linux/omap/patches-3.18/0334-video-da8xx-fb-adding-dt-support.patch new file mode 100644 index 0000000..265602c --- /dev/null +++ b/target/linux/omap/patches-3.18/0334-video-da8xx-fb-adding-dt-support.patch @@ -0,0 +1,202 @@ +From 884d3962ef4787c8cf0b8a7a673531c623d1dff8 Mon Sep 17 00:00:00 2001 +From: Darren Etheridge +Date: Fri, 2 Aug 2013 15:35:36 -0500 +Subject: [PATCH 334/752] video: da8xx-fb: adding dt support + +Enhancing driver to enable probe triggered by a corresponding dt entry. + +Add da8xx-fb.txt documentation to devicetree section. + +Obtain fb_videomode details for the connected lcd panel using the +display timing details present in DT. + +Ensure that platform data is present before checking whether platform +callback is present (the one used to control backlight). So far this +was not an issue as driver was purely non-DT triggered, but now DT +support has been added this check must be performed. + +v2: squashing multiple commits from Afzal Mohammed (afzal@ti.com) +v3: remove superfluous cast +v4: expose both ti,am3352-lcdc and ti,da830-lcdc for .compatible + as driver can use enhanced features of all version of the + silicon block. +v5: addressed review comments from Prabhakar Lad +v6: Changed the .compatible naming to match the existing drm bindings + for am33xx devices +v7: clarify which compatible to use in the documentation for DA850 + +Acked-by: Lad, Prabhakar +Signed-off-by: Darren Etheridge +--- + .../devicetree/bindings/video/da8xx-fb.txt | 42 +++++++++++++ + drivers/video/fbdev/da8xx-fb.c | 66 +++++++++++++++++++- + 2 files changed, 105 insertions(+), 3 deletions(-) + create mode 100644 Documentation/devicetree/bindings/video/da8xx-fb.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/video/da8xx-fb.txt +@@ -0,0 +1,42 @@ ++TI LCD Controller on DA830/DA850/AM335x SoC's ++ ++Required properties: ++- compatible: ++ DA830, DA850 - "ti,da8xx-tilcdc" ++ AM335x SoC's - "ti,am33xx-tilcdc" ++- reg: Address range of lcdc register set ++- interrupts: lcdc interrupt ++- display-timings: typical videomode of lcd panel, represented as child. ++ Refer Documentation/devicetree/bindings/video/display-timing.txt for ++ display timing binding details. If multiple videomodes are mentioned ++ in display timings node, typical videomode has to be mentioned as the ++ native mode or it has to be first child (driver cares only for native ++ videomode). ++ ++Recommended properties: ++- ti,hwmods: Name of the hwmod associated to the LCDC ++ ++Example for am335x SoC's: ++ ++lcdc@4830e000 { ++ compatible = "ti,am33xx-tilcdc"; ++ reg = <0x4830e000 0x1000>; ++ interrupts = <36>; ++ ti,hwmods = "lcdc"; ++ status = "okay"; ++ display-timings { ++ 800x480p62 { ++ clock-frequency = <30000000>; ++ hactive = <800>; ++ vactive = <480>; ++ hfront-porch = <39>; ++ hback-porch = <39>; ++ hsync-len = <47>; ++ vback-porch = <29>; ++ vfront-porch = <13>; ++ vsync-len = <2>; ++ hsync-active = <1>; ++ vsync-active = <1>; ++ }; ++ }; ++}; +--- a/drivers/video/fbdev/da8xx-fb.c ++++ b/drivers/video/fbdev/da8xx-fb.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include